From 7310a42f92011ef24b115aaa586dd3e950d0d753 Mon Sep 17 00:00:00 2001 From: Mads Winther-Jensen Date: Tue, 20 Feb 2024 10:33:14 +0100 Subject: [PATCH 0001/2402] Blutooth: controller: Implement ISO test mode for sync receiver * Implement LL/IST/SNC/BV-01-C ISO Test Receive * Refactor data structure for common code between CIS and BIS Signed-off-by: Mads Winther-Jensen --- .../bluetooth/controller/ll_sw/lll_sync_iso.h | 1 + .../bluetooth/controller/ll_sw/ull_conn_iso.c | 8 +- subsys/bluetooth/controller/ll_sw/ull_iso.c | 425 +++++++++++------- .../controller/ll_sw/ull_iso_types.h | 22 +- .../bluetooth/controller/ll_sw/ull_sync_iso.c | 16 + .../controller/ll_sw/ull_sync_iso_internal.h | 1 + 6 files changed, 306 insertions(+), 167 deletions(-) diff --git a/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h b/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h index c47aa433c63..830153b1433 100644 --- a/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h +++ b/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h @@ -7,6 +7,7 @@ struct lll_sync_iso_stream { uint8_t big_handle; uint8_t bis_index; + struct ll_iso_rx_test_mode *test_mode; struct ll_iso_datapath *dp; }; diff --git a/subsys/bluetooth/controller/ll_sw/ull_conn_iso.c b/subsys/bluetooth/controller/ll_sw/ull_conn_iso.c index f1d6c1c922e..4d390576763 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_conn_iso.c +++ b/subsys/bluetooth/controller/ll_sw/ull_conn_iso.c @@ -1612,7 +1612,7 @@ void ull_conn_iso_transmit_test_cig_interval(uint16_t handle, uint32_t ticks_at_ cis = ll_conn_iso_stream_get_by_group(cig, &handle_iter); LL_ASSERT(cis); - if (!cis->hdr.test_mode.tx_enabled || cis->lll.handle == LLL_HANDLE_INVALID) { + if (!cis->hdr.test_mode.tx.enabled || cis->lll.handle == LLL_HANDLE_INVALID) { continue; } @@ -1623,13 +1623,13 @@ void ull_conn_iso_transmit_test_cig_interval(uint16_t handle, uint32_t ticks_at_ sdu_counter = DIV_ROUND_UP((cis->lll.event_count + 1U) * iso_interval, sdu_interval); - if (cis->hdr.test_mode.tx_sdu_counter == 0U) { + if (cis->hdr.test_mode.tx.sdu_counter == 0U) { /* First ISO event. Align SDU counter for next event */ - cis->hdr.test_mode.tx_sdu_counter = sdu_counter; + cis->hdr.test_mode.tx.sdu_counter = sdu_counter; tx_sdu_count = 0U; } else { /* Calculate number of SDUs to produce for next ISO event */ - tx_sdu_count = sdu_counter - cis->hdr.test_mode.tx_sdu_counter; + tx_sdu_count = sdu_counter - cis->hdr.test_mode.tx.sdu_counter; } /* Now process all SDUs due for next ISO event */ diff --git a/subsys/bluetooth/controller/ll_sw/ull_iso.c b/subsys/bluetooth/controller/ll_sw/ull_iso.c index 440777c78b8..f1853b75d83 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_iso.c +++ b/subsys/bluetooth/controller/ll_sw/ull_iso.c @@ -592,7 +592,7 @@ uint8_t ll_remove_iso_path(uint16_t handle, uint8_t path_dir) #if defined(CONFIG_BT_CTLR_SYNC_ISO) } else if (IS_SYNC_ISO_HANDLE(handle)) { struct lll_sync_iso_stream *sync_stream; - struct ll_iso_datapath *dp; + struct ll_iso_datapath *dp; uint16_t stream_handle; if (!(path_dir & BIT(BT_HCI_DATAPATH_DIR_CTLR_TO_HOST))) { @@ -643,12 +643,21 @@ static isoal_status_t ll_iso_test_sdu_alloc(const struct isoal_sink *sink_ctx, LL_ASSERT(cis); /* For unframed, SDU counter is the payload number */ - cis->hdr.test_mode.rx_sdu_counter = + cis->hdr.test_mode.rx.sdu_counter = (uint32_t)valid_pdu->meta->payload_number; } } else if (IS_SYNC_ISO_HANDLE(handle)) { - /* FIXME: Implement for sync receiver */ - LL_ASSERT(false); + if (!sink_ctx->session.framed) { + struct lll_sync_iso_stream *sync_stream; + uint16_t stream_handle; + + stream_handle = LL_BIS_SYNC_IDX_FROM_HANDLE(handle); + sync_stream = ull_sync_iso_stream_get(stream_handle); + LL_ASSERT(sync_stream); + + sync_stream->test_mode->sdu_counter = + (uint32_t)valid_pdu->meta->payload_number; + } } return sink_sdu_alloc_hci(sink_ctx, valid_pdu, sdu_buffer); @@ -662,106 +671,124 @@ static isoal_status_t ll_iso_test_sdu_emit(const struct isoal_sink * const struct isoal_emitted_sdu_frag *sdu_frag, const struct isoal_emitted_sdu *sdu) { + struct ll_iso_rx_test_mode *test_mode_rx; + isoal_sdu_len_t length; isoal_status_t status; struct net_buf *buf; + uint32_t sdu_counter; + uint16_t max_sdu; uint16_t handle; + uint8_t framed; handle = sink_ctx->session.handle; buf = (struct net_buf *)sdu_frag->sdu.contents.dbuf; if (IS_CIS_HANDLE(handle)) { struct ll_conn_iso_stream *cis; - isoal_sdu_len_t length; - uint32_t sdu_counter; - uint8_t framed; cis = ll_iso_stream_connected_get(sink_ctx->session.handle); LL_ASSERT(cis); - length = sink_ctx->sdu_production.sdu_written; - framed = sink_ctx->session.framed; + test_mode_rx = &cis->hdr.test_mode.rx; + max_sdu = cis->c_max_sdu; +#if defined(CONFIG_BT_CTLR_SYNC_ISO) + } else if (IS_SYNC_ISO_HANDLE(handle)) { + struct lll_sync_iso_stream *sync_stream; + struct ll_sync_iso_set *sync_iso; + uint16_t stream_handle; - /* In BT_HCI_ISO_TEST_ZERO_SIZE_SDU mode, all SDUs must have length 0 and there is - * no sdu_counter field. In the other modes, the first 4 bytes must contain a - * packet counter, which is used as SDU counter. The sdu_counter is extracted - * regardless of mode as a sanity check, unless the length does not allow it. - */ - if (length >= ISO_TEST_PACKET_COUNTER_SIZE) { - sdu_counter = sys_get_le32(buf->data); - } else { - sdu_counter = 0U; - } + stream_handle = LL_BIS_SYNC_IDX_FROM_HANDLE(handle); + sync_stream = ull_sync_iso_stream_get(stream_handle); + LL_ASSERT(sync_stream); - switch (sdu_frag->sdu.status) { - case ISOAL_SDU_STATUS_VALID: - if (framed && cis->hdr.test_mode.rx_sdu_counter == 0U) { - /* BT 5.3, Vol 6, Part B, section 7.2: - * When using framed PDUs the expected value of the SDU counter - * shall be initialized with the value of the SDU counter of the - * first valid received SDU. - */ - cis->hdr.test_mode.rx_sdu_counter = sdu_counter; - } + sync_iso = ull_sync_iso_by_stream_get(stream_handle); - switch (cis->hdr.test_mode.rx_payload_type) { - case BT_HCI_ISO_TEST_ZERO_SIZE_SDU: - if (length == 0) { - cis->hdr.test_mode.received_cnt++; - } else { - cis->hdr.test_mode.failed_cnt++; - } - break; + test_mode_rx = sync_stream->test_mode; + max_sdu = sync_iso->lll.max_sdu; +#endif /* CONFIG_BT_CTLR_SYNC_ISO */ + } else { + /* Handle is out of range */ + status = ISOAL_STATUS_ERR_SDU_EMIT; + net_buf_unref(buf); - case BT_HCI_ISO_TEST_VARIABLE_SIZE_SDU: - if ((length >= ISO_TEST_PACKET_COUNTER_SIZE) && - (length <= cis->c_max_sdu) && - (sdu_counter == cis->hdr.test_mode.rx_sdu_counter)) { - cis->hdr.test_mode.received_cnt++; - } else { - cis->hdr.test_mode.failed_cnt++; - } - break; + return status; + } - case BT_HCI_ISO_TEST_MAX_SIZE_SDU: - if ((length == cis->c_max_sdu) && - (sdu_counter == cis->hdr.test_mode.rx_sdu_counter)) { - cis->hdr.test_mode.received_cnt++; - } else { - cis->hdr.test_mode.failed_cnt++; - } - break; + length = sink_ctx->sdu_production.sdu_written; + framed = sink_ctx->session.framed; - default: - LL_ASSERT(0); - return ISOAL_STATUS_ERR_SDU_EMIT; + /* In BT_HCI_ISO_TEST_ZERO_SIZE_SDU mode, all SDUs must have length 0 and there is + * no sdu_counter field. In the other modes, the first 4 bytes must contain a + * packet counter, which is used as SDU counter. The sdu_counter is extracted + * regardless of mode as a sanity check, unless the length does not allow it. + */ + if (length >= ISO_TEST_PACKET_COUNTER_SIZE) { + sdu_counter = sys_get_le32(buf->data); + } else { + sdu_counter = 0U; + } + + switch (sdu_frag->sdu.status) { + case ISOAL_SDU_STATUS_VALID: + if (framed && test_mode_rx->sdu_counter == 0U) { + /* BT 5.3, Vol 6, Part B, section 7.2: + * When using framed PDUs the expected value of the SDU counter + * shall be initialized with the value of the SDU counter of the + * first valid received SDU. + */ + test_mode_rx->sdu_counter = sdu_counter; + } + + switch (test_mode_rx->payload_type) { + case BT_HCI_ISO_TEST_ZERO_SIZE_SDU: + if (length == 0) { + test_mode_rx->received_cnt++; + } else { + test_mode_rx->failed_cnt++; } break; - case ISOAL_SDU_STATUS_ERRORS: - case ISOAL_SDU_STATUS_LOST_DATA: - cis->hdr.test_mode.missed_cnt++; + case BT_HCI_ISO_TEST_VARIABLE_SIZE_SDU: + if ((length >= ISO_TEST_PACKET_COUNTER_SIZE) && + (length <= max_sdu) && + (sdu_counter == test_mode_rx->sdu_counter)) { + test_mode_rx->received_cnt++; + } else { + test_mode_rx->failed_cnt++; + } break; - } - /* In framed mode, we may start incrementing the SDU counter when rx_sdu_counter - * becomes non zero (initial state), or in case of zero-based counting, if zero - * is actually the first valid SDU counter received. - */ - if (framed && (cis->hdr.test_mode.rx_sdu_counter || - (sdu_frag->sdu.status == ISOAL_SDU_STATUS_VALID))) { - cis->hdr.test_mode.rx_sdu_counter++; + case BT_HCI_ISO_TEST_MAX_SIZE_SDU: + if ((length == max_sdu) && + (sdu_counter == test_mode_rx->sdu_counter)) { + test_mode_rx->received_cnt++; + } else { + test_mode_rx->failed_cnt++; + } + break; + + default: + LL_ASSERT(0); + return ISOAL_STATUS_ERR_SDU_EMIT; } + break; - status = ISOAL_STATUS_OK; + case ISOAL_SDU_STATUS_ERRORS: + case ISOAL_SDU_STATUS_LOST_DATA: + test_mode_rx->missed_cnt++; + break; + } - } else if (IS_SYNC_ISO_HANDLE(handle)) { - /* FIXME: Implement for sync receiver */ - status = ISOAL_STATUS_ERR_SDU_EMIT; - } else { - /* Handle is out of range */ - status = ISOAL_STATUS_ERR_SDU_EMIT; + /* In framed mode, we may start incrementing the SDU counter when rx_sdu_counter + * becomes non zero (initial state), or in case of zero-based counting, if zero + * is actually the first valid SDU counter received. + */ + if (framed && (test_mode_rx->sdu_counter || + (sdu_frag->sdu.status == ISOAL_SDU_STATUS_VALID))) { + test_mode_rx->sdu_counter++; } + status = ISOAL_STATUS_OK; net_buf_unref(buf); return status; @@ -769,13 +796,24 @@ static isoal_status_t ll_iso_test_sdu_emit(const struct isoal_sink * uint8_t ll_iso_receive_test(uint16_t handle, uint8_t payload_type) { + struct ll_iso_rx_test_mode *test_mode_rx; isoal_sink_handle_t sink_handle; struct ll_iso_datapath *dp; uint32_t sdu_interval; isoal_status_t err; - uint8_t status; - status = BT_HCI_ERR_SUCCESS; + struct ll_iso_datapath **stream_dp; + + uint32_t stream_sync_delay; + uint32_t group_sync_delay; +#if defined(CONFIG_BT_CTLR_SYNC_ISO) + uint16_t stream_handle; +#endif /* CONFIG_BT_CTLR_SYNC_ISO */ + uint16_t iso_interval; + uint8_t framed; + uint8_t role; + uint8_t ft; + uint8_t bn; if (IS_CIS_HANDLE(handle)) { struct ll_conn_iso_stream *cis; @@ -792,25 +830,8 @@ uint8_t ll_iso_receive_test(uint16_t handle, uint8_t payload_type) return BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL; } - if (cis->hdr.datapath_out) { - /* Data path already set up */ - return BT_HCI_ERR_CMD_DISALLOWED; - } - - if (payload_type > BT_HCI_ISO_TEST_MAX_SIZE_SDU) { - return BT_HCI_ERR_INVALID_LL_PARAM; - } - - /* Allocate and configure test datapath */ - dp = mem_acquire(&datapath_free); - if (!dp) { - return BT_HCI_ERR_CMD_DISALLOWED; - } - - dp->path_dir = BT_HCI_DATAPATH_DIR_CTLR_TO_HOST; - dp->path_id = BT_HCI_DATAPATH_ID_HCI; - - cis->hdr.datapath_out = dp; + test_mode_rx = &cis->hdr.test_mode.rx; + stream_dp = &cis->hdr.datapath_out; cig = cis->group; if (cig->lll.role == BT_HCI_ROLE_PERIPHERAL) { @@ -821,54 +842,114 @@ uint8_t ll_iso_receive_test(uint16_t handle, uint8_t payload_type) sdu_interval = cig->p_sdu_interval; } - err = isoal_sink_create(handle, cig->lll.role, cis->framed, - cis->lll.rx.bn, cis->lll.rx.ft, - sdu_interval, cig->iso_interval, - cis->sync_delay, cig->sync_delay, - ll_iso_test_sdu_alloc, - ll_iso_test_sdu_emit, - sink_sdu_write_hci, &sink_handle); - if (err) { - /* Error creating test source - cleanup source and - * datapath - */ - isoal_sink_destroy(sink_handle); - ull_iso_datapath_release(dp); - cis->hdr.datapath_out = NULL; + role = cig->lll.role; + framed = cis->framed; + bn = cis->lll.rx.bn; + ft = cis->lll.rx.ft; + iso_interval = cig->iso_interval; + stream_sync_delay = cis->sync_delay; + group_sync_delay = cig->sync_delay; +#if defined(CONFIG_BT_CTLR_SYNC_ISO) + } else if (IS_SYNC_ISO_HANDLE(handle)) { + /* Get the sync stream from the handle */ + struct lll_sync_iso_stream *sync_stream; + struct ll_sync_iso_set *sync_iso; + struct lll_sync_iso *lll_iso; + stream_handle = LL_BIS_SYNC_IDX_FROM_HANDLE(handle); + sync_stream = ull_sync_iso_stream_get(stream_handle); + if (!sync_stream) { + return BT_HCI_ERR_UNKNOWN_CONN_ID; + } + + if (sync_stream->dp) { + /* Data path already set up */ return BT_HCI_ERR_CMD_DISALLOWED; } - dp->sink_hdl = sink_handle; - isoal_sink_enable(sink_handle); + sync_iso = ull_sync_iso_by_stream_get(stream_handle); + lll_iso = &sync_iso->lll; - /* Enable Receive Test Mode */ - cis->hdr.test_mode.rx_enabled = 1; - cis->hdr.test_mode.rx_payload_type = payload_type; + test_mode_rx = sync_stream->test_mode; + stream_dp = &sync_stream->dp; - } else if (IS_SYNC_ISO_HANDLE(handle)) { - /* FIXME: Implement for sync receiver */ - status = BT_HCI_ERR_CMD_DISALLOWED; + /* BT Core v5.4 - Vol 6, Part B, Section 4.4.6.4: + * BIG_Sync_Delay = (Num_BIS – 1) × BIS_Spacing + * + (NSE – 1) × Sub_Interval + MPT. + */ + group_sync_delay = ull_big_sync_delay(lll_iso); + stream_sync_delay = group_sync_delay - stream_handle * lll_iso->bis_spacing; + + role = ISOAL_ROLE_BROADCAST_SINK; + framed = 0; /* FIXME: Get value from biginfo */ + bn = lll_iso->bn; + ft = 0; + sdu_interval = lll_iso->sdu_interval; + iso_interval = lll_iso->iso_interval; +#endif /* CONFIG_BT_CTLR_SYNC_ISO */ } else { /* Handle is out of range */ - status = BT_HCI_ERR_UNKNOWN_CONN_ID; + return BT_HCI_ERR_UNKNOWN_CONN_ID; } - return status; + if (*stream_dp) { + /* Data path already set up */ + return BT_HCI_ERR_CMD_DISALLOWED; + } + + if (payload_type > BT_HCI_ISO_TEST_MAX_SIZE_SDU) { + return BT_HCI_ERR_INVALID_LL_PARAM; + } + + /* Allocate and configure test datapath */ + dp = mem_acquire(&datapath_free); + if (!dp) { + return BT_HCI_ERR_CMD_DISALLOWED; + } + + dp->path_dir = BT_HCI_DATAPATH_DIR_CTLR_TO_HOST; + dp->path_id = BT_HCI_DATAPATH_ID_HCI; + + *stream_dp = dp; + memset(test_mode_rx, 0, sizeof(struct ll_iso_rx_test_mode)); + + err = isoal_sink_create(handle, role, framed, bn, ft, + sdu_interval, iso_interval, + stream_sync_delay, group_sync_delay, + ll_iso_test_sdu_alloc, + ll_iso_test_sdu_emit, + sink_sdu_write_hci, &sink_handle); + if (err) { + /* Error creating test source - cleanup source and + * datapath + */ + isoal_sink_destroy(sink_handle); + ull_iso_datapath_release(dp); + *stream_dp = NULL; + + return BT_HCI_ERR_CMD_DISALLOWED; + } + + dp->sink_hdl = sink_handle; + isoal_sink_enable(sink_handle); + + /* Enable Receive Test Mode */ + test_mode_rx->enabled = 1; + test_mode_rx->payload_type = payload_type; + + return BT_HCI_ERR_SUCCESS; } uint8_t ll_iso_read_test_counters(uint16_t handle, uint32_t *received_cnt, uint32_t *missed_cnt, uint32_t *failed_cnt) { - uint8_t status; + struct ll_iso_rx_test_mode *test_mode_rx; *received_cnt = 0U; *missed_cnt = 0U; *failed_cnt = 0U; - status = BT_HCI_ERR_SUCCESS; - if (IS_CIS_HANDLE(handle)) { struct ll_conn_iso_stream *cis; @@ -878,25 +959,37 @@ uint8_t ll_iso_read_test_counters(uint16_t handle, uint32_t *received_cnt, return BT_HCI_ERR_UNKNOWN_CONN_ID; } - if (!cis->hdr.test_mode.rx_enabled) { - /* ISO receive Test is not active */ - return BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL; + test_mode_rx = &cis->hdr.test_mode.rx; + + } else if (IS_SYNC_ISO_HANDLE(handle)) { + /* Get the sync stream from the handle */ + struct lll_sync_iso_stream *sync_stream; + uint16_t stream_handle; + + stream_handle = LL_BIS_SYNC_IDX_FROM_HANDLE(handle); + sync_stream = ull_sync_iso_stream_get(stream_handle); + if (!sync_stream) { + return BT_HCI_ERR_UNKNOWN_CONN_ID; } - /* Return SDU statistics */ - *received_cnt = cis->hdr.test_mode.received_cnt; - *missed_cnt = cis->hdr.test_mode.missed_cnt; - *failed_cnt = cis->hdr.test_mode.failed_cnt; + test_mode_rx = sync_stream->test_mode; - } else if (IS_SYNC_ISO_HANDLE(handle)) { - /* FIXME: Implement for sync receiver */ - status = BT_HCI_ERR_CMD_DISALLOWED; } else { /* Handle is out of range */ - status = BT_HCI_ERR_UNKNOWN_CONN_ID; + return BT_HCI_ERR_UNKNOWN_CONN_ID; } - return status; + if (!test_mode_rx->enabled) { + /* ISO receive Test is not active */ + return BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL; + } + + /* Return SDU statistics */ + *received_cnt = test_mode_rx->received_cnt; + *missed_cnt = test_mode_rx->missed_cnt; + *failed_cnt = test_mode_rx->failed_cnt; + + return BT_HCI_ERR_SUCCESS; } #if defined(CONFIG_BT_CTLR_READ_ISO_LINK_QUALITY) @@ -989,7 +1082,7 @@ void ll_iso_transmit_test_send_sdu(uint16_t handle, uint32_t ticks_at_expire) cis = ll_iso_stream_connected_get(handle); LL_ASSERT(cis); - if (!cis->hdr.test_mode.tx_enabled) { + if (!cis->hdr.test_mode.tx.enabled) { /* Transmit Test Mode not enabled */ return; } @@ -999,7 +1092,7 @@ void ll_iso_transmit_test_send_sdu(uint16_t handle, uint32_t ticks_at_expire) max_sdu = IS_PERIPHERAL(cig) ? cis->p_max_sdu : cis->c_max_sdu; - switch (cis->hdr.test_mode.tx_payload_type) { + switch (cis->hdr.test_mode.tx.payload_type) { case BT_HCI_ISO_TEST_ZERO_SIZE_SDU: remaining_tx = 0; break; @@ -1069,7 +1162,7 @@ void ll_iso_transmit_test_send_sdu(uint16_t handle, uint32_t ticks_at_expire) if ((sdu.size >= ISO_TEST_PACKET_COUNTER_SIZE) && ((sdu.sdu_state == BT_ISO_START) || (sdu.sdu_state == BT_ISO_SINGLE))) { if (cis->framed) { - sdu_counter = (uint32_t)cis->hdr.test_mode.tx_sdu_counter; + sdu_counter = (uint32_t)cis->hdr.test_mode.tx.sdu_counter; } else { /* Unframed. Get the next payload counter. * @@ -1099,7 +1192,7 @@ void ll_iso_transmit_test_send_sdu(uint16_t handle, uint32_t ticks_at_expire) } } while (remaining_tx); - cis->hdr.test_mode.tx_sdu_counter++; + cis->hdr.test_mode.tx.sdu_counter++; } else if (IS_ADV_ISO_HANDLE(handle)) { /* FIXME: Implement for broadcaster */ @@ -1180,8 +1273,8 @@ uint8_t ll_iso_transmit_test(uint16_t handle, uint8_t payload_type) isoal_source_enable(source_handle); /* Enable Transmit Test Mode */ - cis->hdr.test_mode.tx_enabled = 1; - cis->hdr.test_mode.tx_payload_type = payload_type; + cis->hdr.test_mode.tx.enabled = 1; + cis->hdr.test_mode.tx.payload_type = payload_type; } else if (IS_ADV_ISO_HANDLE(handle)) { struct lll_adv_iso_stream *stream; @@ -1209,14 +1302,10 @@ uint8_t ll_iso_transmit_test(uint16_t handle, uint8_t payload_type) uint8_t ll_iso_test_end(uint16_t handle, uint32_t *received_cnt, uint32_t *missed_cnt, uint32_t *failed_cnt) { - uint8_t status; - *received_cnt = 0U; *missed_cnt = 0U; *failed_cnt = 0U; - status = BT_HCI_ERR_SUCCESS; - if (IS_CIS_HANDLE(handle)) { struct ll_conn_iso_stream *cis; @@ -1226,23 +1315,23 @@ uint8_t ll_iso_test_end(uint16_t handle, uint32_t *received_cnt, return BT_HCI_ERR_UNKNOWN_CONN_ID; } - if (!cis->hdr.test_mode.rx_enabled && !cis->hdr.test_mode.tx_enabled) { + if (!cis->hdr.test_mode.rx.enabled && !cis->hdr.test_mode.tx.enabled) { /* Test Mode is not active */ return BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL; } - if (cis->hdr.test_mode.rx_enabled) { + if (cis->hdr.test_mode.rx.enabled) { isoal_sink_destroy(cis->hdr.datapath_out->sink_hdl); ull_iso_datapath_release(cis->hdr.datapath_out); cis->hdr.datapath_out = NULL; /* Return SDU statistics */ - *received_cnt = cis->hdr.test_mode.received_cnt; - *missed_cnt = cis->hdr.test_mode.missed_cnt; - *failed_cnt = cis->hdr.test_mode.failed_cnt; + *received_cnt = cis->hdr.test_mode.rx.received_cnt; + *missed_cnt = cis->hdr.test_mode.rx.missed_cnt; + *failed_cnt = cis->hdr.test_mode.rx.failed_cnt; } - if (cis->hdr.test_mode.tx_enabled) { + if (cis->hdr.test_mode.tx.enabled) { /* Tear down source and datapath */ isoal_source_destroy(cis->hdr.datapath_in->source_hdl); ull_iso_datapath_release(cis->hdr.datapath_in); @@ -1254,16 +1343,40 @@ uint8_t ll_iso_test_end(uint16_t handle, uint32_t *received_cnt, } else if (IS_ADV_ISO_HANDLE(handle)) { /* FIXME: Implement for broadcaster */ - status = BT_HCI_ERR_CMD_DISALLOWED; + return BT_HCI_ERR_CMD_DISALLOWED; + } else if (IS_SYNC_ISO_HANDLE(handle)) { - /* FIXME: Implement for sync receiver */ - status = BT_HCI_ERR_CMD_DISALLOWED; + struct lll_sync_iso_stream *sync_stream; + uint16_t stream_handle; + + stream_handle = LL_BIS_SYNC_IDX_FROM_HANDLE(handle); + sync_stream = ull_sync_iso_stream_get(stream_handle); + if (!sync_stream) { + return BT_HCI_ERR_UNKNOWN_CONN_ID; + } + + if (!sync_stream->test_mode->enabled || !sync_stream->dp) { + /* Test Mode is not active */ + return BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL; + } + + isoal_sink_destroy(sync_stream->dp->sink_hdl); + ull_iso_datapath_release(sync_stream->dp); + sync_stream->dp = NULL; + + /* Return SDU statistics */ + *received_cnt = sync_stream->test_mode->received_cnt; + *missed_cnt = sync_stream->test_mode->missed_cnt; + *failed_cnt = sync_stream->test_mode->failed_cnt; + + (void)memset(&sync_stream->test_mode, 0U, sizeof(sync_stream->test_mode)); + } else { /* Handle is out of range */ - status = BT_HCI_ERR_UNKNOWN_CONN_ID; + return BT_HCI_ERR_UNKNOWN_CONN_ID; } - return status; + return BT_HCI_ERR_SUCCESS; } #if defined(CONFIG_BT_CTLR_ADV_ISO) || defined(CONFIG_BT_CTLR_CONN_ISO) diff --git a/subsys/bluetooth/controller/ll_sw/ull_iso_types.h b/subsys/bluetooth/controller/ll_sw/ull_iso_types.h index 457ad1d2458..69c9adbb4b9 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_iso_types.h +++ b/subsys/bluetooth/controller/ll_sw/ull_iso_types.h @@ -57,16 +57,24 @@ #define IS_CIS_HANDLE(_handle) 0 #endif /* CONFIG_BT_CTLR_CONN_ISO */ -struct ll_iso_test_mode_data { +struct ll_iso_tx_test_mode { + uint64_t sdu_counter:53; /* 39 + 22 - 8 */ + uint64_t enabled:1; + uint64_t payload_type:4; /* Support up to 16 payload types (BT 5.3: 3, VS: 13) */ +}; + +struct ll_iso_rx_test_mode { uint32_t received_cnt; uint32_t missed_cnt; uint32_t failed_cnt; - uint32_t rx_sdu_counter; - uint64_t tx_sdu_counter:53; /* 39 + 22 - 8 */ - uint64_t tx_enabled:1; - uint64_t tx_payload_type:4; /* Support up to 16 payload types (BT 5.3: 3, VS: 13) */ - uint64_t rx_enabled:1; - uint64_t rx_payload_type:4; + uint32_t sdu_counter; + uint8_t enabled:1; + uint8_t payload_type:4; /* Support up to 16 payload types (BT 5.3: 3, VS: 13) */ +}; + +struct ll_iso_test_mode_data { + struct ll_iso_rx_test_mode rx; + struct ll_iso_tx_test_mode tx; }; struct ll_iso_link_quality { diff --git a/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c b/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c index 606077d9dae..8930f29ebd4 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c +++ b/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c @@ -71,6 +71,8 @@ static struct mayfly mfy_lll_prepare = {0U, 0U, &link_lll_prepare, NULL, NULL}; static struct ll_sync_iso_set ll_sync_iso[CONFIG_BT_CTLR_SCAN_SYNC_ISO_SET]; static struct lll_sync_iso_stream stream_pool[CONFIG_BT_CTLR_SYNC_ISO_STREAM_COUNT]; +static struct ll_iso_rx_test_mode + test_mode[CONFIG_BT_CTLR_SYNC_ISO_STREAM_COUNT]; static void *stream_free; uint8_t ll_big_sync_create(uint8_t big_handle, uint16_t sync_handle, @@ -182,6 +184,8 @@ uint8_t ll_big_sync_create(uint8_t big_handle, uint16_t sync_handle, stream->big_handle = big_handle; stream->bis_index = bis[i]; stream->dp = NULL; + stream->test_mode = &test_mode[i]; + memset(stream->test_mode, 0, sizeof(struct ll_iso_rx_test_mode)); lll->stream_handle[i] = sync_iso_stream_handle_get(stream); } @@ -776,6 +780,18 @@ void ull_sync_iso_done_terminate(struct node_rx_event_done *done) (ret == TICKER_STATUS_BUSY)); } +uint32_t ull_big_sync_delay(const struct lll_sync_iso *lll_iso) +{ + /* BT Core v5.4 - Vol 6, Part B, Section 4.4.6.4: + * BIG_Sync_Delay = (Num_BIS – 1) × BIS_Spacing + (NSE – 1) × Sub_Interval + MPT. + */ + return (lll_iso->num_bis - 1) * lll_iso->bis_spacing + + (lll_iso->nse - 1) * lll_iso->sub_interval + + BYTES2US(PDU_OVERHEAD_SIZE(lll_iso->phy) + + lll_iso->max_pdu + (lll_iso->enc ? 4 : 0), + lll_iso->phy); +} + static int init_reset(void) { /* Add initializations common to power up initialization and HCI reset diff --git a/subsys/bluetooth/controller/ll_sw/ull_sync_iso_internal.h b/subsys/bluetooth/controller/ll_sw/ull_sync_iso_internal.h index eeda1fc8fd5..65287328594 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_sync_iso_internal.h +++ b/subsys/bluetooth/controller/ll_sw/ull_sync_iso_internal.h @@ -15,3 +15,4 @@ void ull_sync_iso_setup(struct ll_sync_iso_set *sync_iso, void ull_sync_iso_estab_done(struct node_rx_event_done *done); void ull_sync_iso_done(struct node_rx_event_done *done); void ull_sync_iso_done_terminate(struct node_rx_event_done *done); +uint32_t ull_big_sync_delay(const struct lll_sync_iso *lll_iso); From f2a1a519b4ed06ead00ddead0a5fdf3e0b8415aa Mon Sep 17 00:00:00 2001 From: Tomasz Bursztyka Date: Mon, 13 Nov 2023 19:28:26 +0100 Subject: [PATCH 0002/2402] net/trickle: Rearrange net_trickle structure for better alignement Prior to this, 8 bytes were implicitely used for alignement. Which could be fully avoided. Now no bytes are lost. Signed-off-by: Tomasz Bursztyka --- include/zephyr/net/trickle.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/zephyr/net/trickle.h b/include/zephyr/net/trickle.h index fa0577dcc33..fb6ee8f74be 100644 --- a/include/zephyr/net/trickle.h +++ b/include/zephyr/net/trickle.h @@ -51,15 +51,15 @@ typedef void (*net_trickle_cb_t)(struct net_trickle *trickle, * only via the Trickle API. */ struct net_trickle { + uint32_t I; /**< Current interval size */ uint32_t Imin; /**< Min interval size in ms */ + uint32_t Istart; /**< Start of the interval in ms */ + uint32_t Imax_abs; /**< Max interval size in ms (not doublings) */ uint8_t Imax; /**< Max number of doublings */ - uint8_t k; /**< Redundancy constant */ - uint32_t I; /**< Current interval size */ - uint32_t Istart; /**< Start of the interval in ms */ + uint8_t k; /**< Redundancy constant */ uint8_t c; /**< Consistency counter */ - uint32_t Imax_abs; /**< Max interval size in ms (not doublings) */ bool double_to; struct k_work_delayable timer; From af85c8a11d80d6733baa72694e87358ba048696b Mon Sep 17 00:00:00 2001 From: Tomasz Bursztyka Date: Thu, 7 Dec 2023 11:17:17 +0100 Subject: [PATCH 0003/2402] drivers/ieee802154: Use net_pkt API for reading data on upipe driver Some legacy left overs. Just simplifying how to read data into a net_pkt. Signed-off-by: Tomasz Bursztyka --- drivers/ieee802154/ieee802154_uart_pipe.c | 19 ++++++------------- drivers/ieee802154/ieee802154_uart_pipe.h | 2 +- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/ieee802154/ieee802154_uart_pipe.c b/drivers/ieee802154/ieee802154_uart_pipe.c index 72bcf5b8ebf..ff8b27f88f7 100644 --- a/drivers/ieee802154/ieee802154_uart_pipe.c +++ b/drivers/ieee802154/ieee802154_uart_pipe.c @@ -117,7 +117,7 @@ static uint8_t *upipe_rx(uint8_t *buf, size_t *off) } if (!upipe->rx_len) { - if (*buf > 127) { + if (*buf > IEEE802154_MAX_PHY_PACKET_SIZE) { goto flush; } @@ -128,27 +128,20 @@ static uint8_t *upipe_rx(uint8_t *buf, size_t *off) upipe->rx_buf[upipe->rx_off++] = *buf; if (upipe->rx_len == upipe->rx_off) { - struct net_buf *frag; - - pkt = net_pkt_rx_alloc(K_NO_WAIT); + pkt = net_pkt_rx_alloc_with_buffer(upipe->iface, upipe->rx_len, + AF_UNSPEC, 0, K_NO_WAIT); if (!pkt) { LOG_DBG("No pkt available"); goto flush; } - frag = net_pkt_get_frag(pkt, upipe->rx_len, K_NO_WAIT); - if (!frag) { - LOG_DBG("No fragment available"); + if (net_pkt_write(pkt, upipe->rx_buf, upipe->rx_len)) { + LOG_DBG("No content read?"); goto out; } - net_pkt_frag_insert(pkt, frag); - - memcpy(frag->data, upipe->rx_buf, upipe->rx_len); - net_buf_add(frag, upipe->rx_len); - #if defined(CONFIG_IEEE802154_UPIPE_HW_FILTER) - if (received_dest_addr_matched(frag->data) == false) { + if (received_dest_addr_matched(pkt->buffer->data) == false) { LOG_DBG("Packet received is not addressed to me"); goto out; } diff --git a/drivers/ieee802154/ieee802154_uart_pipe.h b/drivers/ieee802154/ieee802154_uart_pipe.h index 491cdcf2b04..c2ac1c8bde3 100644 --- a/drivers/ieee802154/ieee802154_uart_pipe.h +++ b/drivers/ieee802154/ieee802154_uart_pipe.h @@ -20,7 +20,7 @@ struct upipe_context { bool rx; uint8_t rx_len; uint8_t rx_off; - uint8_t rx_buf[127]; + uint8_t rx_buf[IEEE802154_MAX_PHY_PACKET_SIZE]; }; #endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_UART_PIPE_H_ */ From 366402a0c7b212c131573e5b21f3c5e39d2e8ffa Mon Sep 17 00:00:00 2001 From: Tomasz Bursztyka Date: Mon, 11 Dec 2023 19:20:46 +0100 Subject: [PATCH 0004/2402] net/shell: Net shell has no mandatory support for IPv6 MLD It's an optional support, and it should not select it by default. Improving information message in case such support is disabled. Signed-off-by: Tomasz Bursztyka --- subsys/net/ip/Kconfig | 1 - subsys/net/lib/shell/ipv6.c | 8 ++++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/subsys/net/ip/Kconfig b/subsys/net/ip/Kconfig index 35ed6db87c1..5ffba57a691 100644 --- a/subsys/net/ip/Kconfig +++ b/subsys/net/ip/Kconfig @@ -164,7 +164,6 @@ config NET_SHELL bool "Network shell utilities" select SHELL select NET_IPV4_IGMP if NET_IPV4 - select NET_IPV6_MLD if NET_IPV6 select REQUIRES_FLOAT_PRINTF help Activate shell module that provides network commands like diff --git a/subsys/net/lib/shell/ipv6.c b/subsys/net/lib/shell/ipv6.c index 04efda65d0f..99614815b66 100644 --- a/subsys/net/lib/shell/ipv6.c +++ b/subsys/net/lib/shell/ipv6.c @@ -219,6 +219,10 @@ static int cmd_net_ip6_add(const struct shell *sh, size_t argc, char *argv[]) if (ret < 0) { PR_ERROR("Cannot %s multicast group %s for interface %d (%d)\n", "join", net_sprint_ipv6_addr(&addr), idx, ret); + if (ret == -ENOTSUP) { + PR_INFO("Enable CONFIG_NET_IPV6_MLD for %s multicast " + "group\n", "joining"); + } return ret; } } else { @@ -269,6 +273,10 @@ static int cmd_net_ip6_del(const struct shell *sh, size_t argc, char *argv[]) if (ret < 0) { PR_ERROR("Cannot %s multicast group %s for interface %d (%d)\n", "leave", net_sprint_ipv6_addr(&addr), idx, ret); + if (ret == -ENOTSUP) { + PR_INFO("Enable CONFIG_NET_IPV6_MLD for %s multicast " + "group\n", "leaving"); + } return ret; } } else { From 4d48f066a1af7c413fb82c892ced3f157fa9122c Mon Sep 17 00:00:00 2001 From: Tomasz Bursztyka Date: Mon, 11 Dec 2023 19:22:43 +0100 Subject: [PATCH 0005/2402] net/shell: Fixing a trivial error code As for adding an ipv6 address, removing one should return the same error code when the network interface is not found. Signed-off-by: Tomasz Bursztyka --- subsys/net/lib/shell/ipv6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/lib/shell/ipv6.c b/subsys/net/lib/shell/ipv6.c index 99614815b66..e9052750761 100644 --- a/subsys/net/lib/shell/ipv6.c +++ b/subsys/net/lib/shell/ipv6.c @@ -258,7 +258,7 @@ static int cmd_net_ip6_del(const struct shell *sh, size_t argc, char *argv[]) iface = net_if_get_by_index(idx); if (!iface) { PR_WARNING("No such interface in index %d\n", idx); - return -ENOEXEC; + return -ENOENT; } if (net_addr_pton(AF_INET6, argv[2], &addr)) { From 48216eff763e929fb8e231dbed505735498d593e Mon Sep 17 00:00:00 2001 From: Tomasz Bursztyka Date: Wed, 13 Dec 2023 13:01:58 +0100 Subject: [PATCH 0006/2402] net/config: Initialize and add the net mgmt callback at the right time Net MGMT mask should be fully configured first, prior to be used to initialize and add the callback. Signed-off-by: Tomasz Bursztyka --- subsys/net/lib/config/init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/subsys/net/lib/config/init.c b/subsys/net/lib/config/init.c index 192cd3f5685..fcd379c1559 100644 --- a/subsys/net/lib/config/init.c +++ b/subsys/net/lib/config/init.c @@ -298,9 +298,6 @@ static void setup_ipv6(struct net_if *iface, uint32_t flags) struct net_if_addr *ifaddr; uint32_t mask = NET_EVENT_IPV6_DAD_SUCCEED; - net_mgmt_init_event_callback(&mgmt6_cb, ipv6_event_handler, mask); - net_mgmt_add_event_callback(&mgmt6_cb); - if (sizeof(CONFIG_NET_CONFIG_MY_IPV6_ADDR) == 1) { /* Empty address, skip setting ANY address in this case */ goto exit; @@ -316,6 +313,9 @@ static void setup_ipv6(struct net_if *iface, uint32_t flags) mask |= NET_EVENT_IPV6_ROUTER_ADD; } + net_mgmt_init_event_callback(&mgmt6_cb, ipv6_event_handler, mask); + net_mgmt_add_event_callback(&mgmt6_cb); + /* * check for CMD_ADDR_ADD bit here, NET_EVENT_IPV6_ADDR_ADD is * a combination of _NET_EVENT_IPV6_BASE | NET_EVENT_IPV6_CMD_ADDR_ADD From 6d718ed480eb8329a9bc8712524642911bdfbee0 Mon Sep 17 00:00:00 2001 From: Tomasz Bursztyka Date: Wed, 13 Dec 2023 12:56:05 +0100 Subject: [PATCH 0007/2402] net/mgmt: Trivial debug output fix about layer Net MGMT uses layer identifiers that are meaningful only for itself, but for users it requires a trivial operation to show the real layer value. Signed-off-by: Tomasz Bursztyka --- subsys/net/ip/net_mgmt.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/subsys/net/ip/net_mgmt.c b/subsys/net/ip/net_mgmt.c index c351b3df4d1..106fbac49ed 100644 --- a/subsys/net/ip/net_mgmt.c +++ b/subsys/net/ip/net_mgmt.c @@ -181,8 +181,9 @@ static inline void mgmt_run_slist_callbacks(const struct mgmt_event_entry * cons sys_snode_t *prev = NULL; struct net_mgmt_event_callback *cb, *tmp; + /* Readable layer code is starting from 1, thus the increment */ NET_DBG("Event layer %u code %u cmd %u", - NET_MGMT_GET_LAYER(mgmt_event->event), + NET_MGMT_GET_LAYER(mgmt_event->event) + 1, NET_MGMT_GET_LAYER_CODE(mgmt_event->event), NET_MGMT_GET_COMMAND(mgmt_event->event)); @@ -361,8 +362,9 @@ void net_mgmt_event_notify_with_info(uint32_t mgmt_event, struct net_if *iface, const void *info, size_t length) { if (mgmt_is_event_handled(mgmt_event)) { + /* Readable layer code is starting from 1, thus the increment */ NET_DBG("Notifying Event layer %u code %u type %u", - NET_MGMT_GET_LAYER(mgmt_event), + NET_MGMT_GET_LAYER(mgmt_event) + 1, NET_MGMT_GET_LAYER_CODE(mgmt_event), NET_MGMT_GET_COMMAND(mgmt_event)); From 20ccc30273df4790cd3d3455b7f8f810fed2d54c Mon Sep 17 00:00:00 2001 From: Tomasz Bursztyka Date: Wed, 13 Dec 2023 19:05:52 +0100 Subject: [PATCH 0008/2402] net/if: Trivial comment fix about all-nodes s/net_ipv6_mcast_join/net_ipv6_mld_join Signed-off-by: Tomasz Bursztyka --- subsys/net/ip/net_if.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 0e908de4e2a..5bb862896ed 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -1793,7 +1793,7 @@ struct net_if_addr *net_if_ipv6_addr_add(struct net_if *iface, * address. */ /* The allnodes multicast group is only joined once as - * net_ipv6_mcast_join() checks if we have already + * net_ipv6_mld_join() checks if we have already * joined. */ join_mcast_nodes(iface, From a3d7278588347b9a2d7798e3d92774ca0ff2da21 Mon Sep 17 00:00:00 2001 From: Tomasz Bursztyka Date: Wed, 13 Dec 2023 19:08:48 +0100 Subject: [PATCH 0009/2402] net/ipv6: Enforce MLD to be selected if ND is enabled As noted in net_if.c:net_if_ipv6_addr_add() IPv6 ND needs MLD. It is not selected during test, as the combination of ND without DAD/MLD breaks (something to study/fix further it seems). Signed-off-by: Tomasz Bursztyka --- subsys/net/ip/Kconfig.ipv6 | 1 + 1 file changed, 1 insertion(+) diff --git a/subsys/net/ip/Kconfig.ipv6 b/subsys/net/ip/Kconfig.ipv6 index ef6665d228b..9367e068e7f 100644 --- a/subsys/net/ip/Kconfig.ipv6 +++ b/subsys/net/ip/Kconfig.ipv6 @@ -143,6 +143,7 @@ config NET_IPV6_NBR_CACHE config NET_IPV6_ND bool "Activate neighbor discovery" depends on NET_IPV6_NBR_CACHE + select NET_IPV6_MLD if !NET_TEST default y help The value depends on your network needs. ND should normally From a4af2ac8dc5df67469727aba67ac2ad8c5feaccf Mon Sep 17 00:00:00 2001 From: Tomasz Bursztyka Date: Mon, 20 Nov 2023 18:54:23 +0100 Subject: [PATCH 0010/2402] net/ip: Removing useless extra data capability in neighbors This is not used by anyone, and is unlikely to be useful actually. Helps to save 4 bytes for each instance of struct net_nbr also (removing a 2 bytes attributes, which was anyway generating a 4bytes loss due to structure misalignment). Removing relevant useless functions related to it as well. Signed-off-by: Tomasz Bursztyka --- subsys/net/ip/ipv6_nbr.c | 7 ++-- subsys/net/ip/nbr.c | 3 +- subsys/net/ip/nbr.h | 21 +--------- subsys/net/ip/route.c | 74 +---------------------------------- subsys/net/ip/route.h | 16 -------- tests/net/neighbor/src/main.c | 2 +- 6 files changed, 9 insertions(+), 114 deletions(-) diff --git a/subsys/net/ip/ipv6_nbr.c b/subsys/net/ip/ipv6_nbr.c index 528156cafa7..992078062f0 100644 --- a/subsys/net/ip/ipv6_nbr.c +++ b/subsys/net/ip/ipv6_nbr.c @@ -80,7 +80,7 @@ static void ipv6_nd_restart_reachable_timer(struct net_nbr *nbr, int64_t time); #define DELAY_FIRST_PROBE_TIME (5 * MSEC_PER_SEC) #define RETRANS_TIMER 1000 /* ms */ -extern void net_neighbor_data_remove(struct net_nbr *nbr); +extern void net_neighbor_remove(struct net_nbr *nbr); extern void net_neighbor_table_clear(struct net_nbr_table *table); /** Neighbor Solicitation reply timer */ @@ -89,8 +89,7 @@ static struct k_work_delayable ipv6_ns_reply_timer; NET_NBR_POOL_INIT(net_neighbor_pool, CONFIG_NET_IPV6_MAX_NEIGHBORS, sizeof(struct net_ipv6_nbr_data), - net_neighbor_data_remove, - 0); + net_neighbor_remove); NET_NBR_TABLE_INIT(NET_NBR_GLOBAL, neighbor, @@ -665,7 +664,7 @@ struct net_nbr *net_ipv6_nbr_add(struct net_if *iface, return nbr; } -void net_neighbor_data_remove(struct net_nbr *nbr) +void net_neighbor_remove(struct net_nbr *nbr) { NET_DBG("Neighbor %p removed", nbr); diff --git a/subsys/net/ip/nbr.c b/subsys/net/ip/nbr.c index 2396fe03372..8cf42862d0d 100644 --- a/subsys/net/ip/nbr.c +++ b/subsys/net/ip/nbr.c @@ -62,8 +62,7 @@ static inline struct net_nbr *get_nbr(struct net_nbr *start, int idx) NET_ASSERT(idx < CONFIG_NET_IPV6_MAX_NEIGHBORS); return (struct net_nbr *)((uint8_t *)start + - ((sizeof(struct net_nbr) + - start->size + start->extra_data_size) * idx)); + ((sizeof(struct net_nbr) + start->size) * idx)); } struct net_nbr *net_nbr_get(struct net_nbr_table *table) diff --git a/subsys/net/ip/nbr.h b/subsys/net/ip/nbr.h index ee6246f07a1..bab4249acba 100644 --- a/subsys/net/ip/nbr.h +++ b/subsys/net/ip/nbr.h @@ -56,9 +56,6 @@ struct net_nbr { /** Amount of data that this neighbor buffer can store. */ const uint16_t size; - /** Extra data size associated with this neighbor */ - const uint16_t extra_data_size; - /** Interface this neighbor is found */ struct net_if *iface; @@ -75,17 +72,15 @@ struct net_nbr { }; /* This is an array of struct net_nbr + some additional data */ -#define NET_NBR_POOL_INIT(_name, _count, _size, _remove, _extra_size) \ +#define NET_NBR_POOL_INIT(_name, _count, _size, _remove) \ struct { \ struct net_nbr nbr; \ uint8_t data[ROUND_UP(_size, 4)] __net_nbr_align; \ - uint8_t extra[ROUND_UP(_extra_size, 4)] __net_nbr_align;\ } _name[_count] = { \ [0 ... (_count - 1)] = { .nbr = { \ .idx = NET_NBR_LLADDR_UNKNOWN, \ .remove = _remove, \ - .size = ROUND_UP(_size, 4), \ - .extra_data_size = ROUND_UP(_extra_size, 4) } },\ + .size = ROUND_UP(_size, 4) } }, \ } struct net_nbr_table { @@ -115,18 +110,6 @@ struct net_nbr_table { } \ } -/** - * @brief Get a pointer to the extra data of a neighbor entry. - * - * @param nbr A valid pointer to neighbor - * - * @return Pointer to the extra data of the nbr. - */ -static inline void *net_nbr_extra_data(struct net_nbr *nbr) -{ - return (void *)ROUND_UP((nbr->__nbr + nbr->size), sizeof(int)); -} - /** * @brief Decrement the reference count. If count goes to 0, the neighbor * is released and returned to free list. diff --git a/subsys/net/ip/route.c b/subsys/net/ip/route.c index 5922a923df9..6d4ae1ff5f7 100644 --- a/subsys/net/ip/route.c +++ b/subsys/net/ip/route.c @@ -29,10 +29,6 @@ LOG_MODULE_REGISTER(net_route, CONFIG_NET_ROUTE_LOG_LEVEL); #include "nbr.h" #include "route.h" -#if !defined(NET_ROUTE_EXTRA_DATA_SIZE) -#define NET_ROUTE_EXTRA_DATA_SIZE 0 -#endif - /* We keep track of the routes in a separate list so that we can remove * the oldest routes (at tail) if needed. */ @@ -55,8 +51,7 @@ static void net_route_nexthop_remove(struct net_nbr *nbr) NET_NBR_POOL_INIT(net_route_nexthop_pool, CONFIG_NET_MAX_NEXTHOPS, sizeof(struct net_route_nexthop), - net_route_nexthop_remove, - 0); + net_route_nexthop_remove); static inline struct net_route_nexthop *net_nexthop_data(struct net_nbr *nbr) { @@ -115,8 +110,7 @@ static void net_route_entries_table_clear(struct net_nbr_table *table) NET_NBR_POOL_INIT(net_route_entries_pool, CONFIG_NET_MAX_ROUTES, sizeof(struct net_route_entry), - net_route_entry_remove, - NET_ROUTE_EXTRA_DATA_SIZE); + net_route_entry_remove); NET_NBR_TABLE_INIT(NET_NBR_LOCAL, nbr_routes, net_route_entries_pool, net_route_entries_table_clear); @@ -665,70 +659,6 @@ int net_route_del_by_nexthop(struct net_if *iface, struct in6_addr *nexthop) return 0; } -int net_route_del_by_nexthop_data(struct net_if *iface, - struct in6_addr *nexthop, - void *data) -{ - int count = 0, status = 0; - struct net_nbr *nbr_nexthop; - struct net_route_nexthop *nexthop_route; - int i, ret; - - NET_ASSERT(iface); - NET_ASSERT(nexthop); - - net_ipv6_nbr_lock(); - - nbr_nexthop = net_ipv6_nbr_lookup(iface, nexthop); - if (!nbr_nexthop) { - net_ipv6_nbr_unlock(); - return -EINVAL; - } - - for (i = 0; i < CONFIG_NET_MAX_ROUTES; i++) { - struct net_nbr *nbr = get_nbr(i); - struct net_route_entry *route = net_route_data(nbr); - - SYS_SLIST_FOR_EACH_CONTAINER(&route->nexthop, nexthop_route, - node) { - void *extra_data; - - if (nexthop_route->nbr != nbr_nexthop) { - continue; - } - - if (nbr->extra_data_size == 0U) { - continue; - } - - /* Routing engine specific extra data needs - * to match too. - */ - extra_data = net_nbr_extra_data(nbr_nexthop); - if (extra_data != data) { - continue; - } - - ret = net_route_del(route); - if (!ret) { - count++; - } else { - status = ret; - } - - break; - } - } - - net_ipv6_nbr_unlock(); - - if (count) { - return count; - } - - return status; -} - struct in6_addr *net_route_get_nexthop(struct net_route_entry *route) { struct net_route_nexthop *nexthop_route; diff --git a/subsys/net/ip/route.h b/subsys/net/ip/route.h index e54451234c6..1f2d36ee4a8 100644 --- a/subsys/net/ip/route.h +++ b/subsys/net/ip/route.h @@ -138,22 +138,6 @@ int net_route_del(struct net_route_entry *entry); int net_route_del_by_nexthop(struct net_if *iface, struct in6_addr *nexthop); -/** - * @brief Delete a route from routing table by nexthop if the routing engine - * specific data matches. - * - * @detail The routing engine specific data could be the RPL data. - * - * @param iface Network interface to use. - * @param nexthop IPv6 address of the nexthop device. - * @param data Routing engine specific data. - * - * @return number of routes deleted, <0 if error - */ -int net_route_del_by_nexthop_data(struct net_if *iface, - struct in6_addr *nexthop, - void *data); - /** * @brief Update the route lifetime. * diff --git a/tests/net/neighbor/src/main.c b/tests/net/neighbor/src/main.c index c6a04c1c16c..b598bd1ce5c 100644 --- a/tests/net/neighbor/src/main.c +++ b/tests/net/neighbor/src/main.c @@ -45,7 +45,7 @@ static void net_neighbor_table_clear(struct net_nbr_table *table) } NET_NBR_POOL_INIT(net_test_neighbor_pool, CONFIG_NET_IPV6_MAX_NEIGHBORS, - 0, net_neighbor_data_remove, 0); + 0, net_neighbor_data_remove); NET_NBR_TABLE_INIT(NET_NBR_LOCAL, test_neighbor, net_test_neighbor_pool, net_neighbor_table_clear); From e08301b3df556843084fcec6e05ff9d0aea0bef6 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Thu, 22 Feb 2024 14:39:48 +0100 Subject: [PATCH 0011/2402] Bluetooth: BAP: Fix missing cfg data in stream->codec_cfg for BIS The codec configuration data from the BIS in the BASE was not properly copied to the stream->codec_cfg, and thus it only contained the subgroup codec configuration values. This commit fixes that by first copying the subgroup codec configuration to the stream, and then setting or overwriting any fields (if they exist). This requires that each stream have their own codec configuration struct allocated, so this will slightly increase memory usage. This also adds verification of the SDU size from the BIGInfo in the ISO receive callback. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/bap_broadcast_sink.c | 172 ++++++++++++++++---- subsys/bluetooth/audio/bap_endpoint.h | 7 +- 2 files changed, 145 insertions(+), 34 deletions(-) diff --git a/subsys/bluetooth/audio/bap_broadcast_sink.c b/subsys/bluetooth/audio/bap_broadcast_sink.c index 9dc2374839e..bc444876bdd 100644 --- a/subsys/bluetooth/audio/bap_broadcast_sink.c +++ b/subsys/bluetooth/audio/bap_broadcast_sink.c @@ -186,7 +186,7 @@ static struct bt_bap_broadcast_sink *broadcast_sink_lookup_iso_chan( { for (size_t i = 0U; i < ARRAY_SIZE(broadcast_sinks); i++) { for (uint8_t j = 0U; j < broadcast_sinks[i].stream_count; j++) { - if (broadcast_sinks[i].bis[j] == chan) { + if (broadcast_sinks[i].bis[j].chan == chan) { return &broadcast_sinks[i]; } } @@ -251,6 +251,7 @@ static void broadcast_sink_iso_recv(struct bt_iso_chan *chan, const struct bt_bap_stream_ops *ops; struct bt_bap_stream *stream; struct bt_bap_ep *ep = iso->rx.ep; + size_t buf_len; if (ep == NULL) { LOG_ERR("iso %p not bound with ep", chan); @@ -265,8 +266,14 @@ static void broadcast_sink_iso_recv(struct bt_iso_chan *chan, ops = stream->ops; + buf_len = net_buf_frags_len(buf); if (IS_ENABLED(CONFIG_BT_BAP_DEBUG_STREAM_DATA)) { - LOG_DBG("stream %p ep %p len %zu", stream, stream->ep, net_buf_frags_len(buf)); + LOG_DBG("stream %p ep %p len %zu", stream, stream->ep, buf_len); + } + + if (buf_len > stream->qos->sdu) { + LOG_WRN("Received %u octets but stream %p was only configured for %u", buf_len, + stream, stream->qos->sdu); } if (ops != NULL && ops->recv != NULL) { @@ -522,79 +529,171 @@ static bool codec_lookup_id(const struct bt_pacs_cap *cap, void *user_data) return true; } +struct store_base_info_data { + struct bt_bap_broadcast_sink_bis bis[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT]; + struct bt_bap_broadcast_sink_subgroup subgroups[CONFIG_BT_BAP_BROADCAST_SNK_SUBGROUP_COUNT]; + struct bt_audio_codec_cfg *subgroup_codec_cfg; + uint32_t valid_indexes_bitfield; + uint8_t subgroup_count; + uint8_t bis_count; +}; + +static bool merge_bis_and_subgroup_data_cb(struct bt_data *data, void *user_data) +{ + struct bt_audio_codec_cfg *codec_cfg = user_data; + int err; + + err = bt_audio_codec_cfg_set_val(codec_cfg, data->type, data->data, data->data_len); + if (err < 0) { + LOG_DBG("Failed to set type %u with len %u in codec_cfg: %d", data->type, + data->data_len, err); + + return false; + } + + return true; +} + static bool base_subgroup_bis_index_cb(const struct bt_bap_base_subgroup_bis *bis, void *user_data) { - uint32_t *bis_indexes = user_data; + struct bt_bap_broadcast_sink_subgroup *sink_subgroup; + struct store_base_info_data *data = user_data; + struct bt_bap_broadcast_sink_bis *sink_bis; + + if (data->bis_count == ARRAY_SIZE(data->bis)) { + /* We've parsed as many subgroups as we support */ + LOG_DBG("Could only store %u BIS", data->bis_count); + return false; + } + + sink_bis = &data->bis[data->bis_count]; + sink_subgroup = &data->subgroups[data->subgroup_count]; + + sink_bis->index = bis->index; + sink_subgroup->bis_indexes |= BIT(bis->index); + +#if CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 + int err; + + memcpy(&sink_bis->codec_cfg, data->subgroup_codec_cfg, sizeof(sink_bis->codec_cfg)); + + /* Merge subgroup codec configuration with the BIS configuration + * As per the BAP spec, if a value exist at level 2 (subgroup) and 3 (BIS), then it is + * the value at level 3 that shall be used + */ + if (sink_bis->codec_cfg.id == BT_HCI_CODING_FORMAT_LC3) { + memcpy(&sink_bis->codec_cfg, data->subgroup_codec_cfg, sizeof(sink_bis->codec_cfg)); + + err = bt_audio_data_parse(bis->data, bis->data_len, merge_bis_and_subgroup_data_cb, + &sink_bis->codec_cfg); + if (err != 0) { + LOG_DBG("Could not merge BIS and subgroup config in codec_cfg: %d", err); + + return false; + } + } else { + /* If it is not LC3, then we don't know how to merge the subgroup and BIS codecs, + * so we just append them + */ + if (sink_bis->codec_cfg.data_len + bis->data_len > + sizeof(sink_bis->codec_cfg.data)) { + LOG_DBG("Could not store BIS and subgroup config in codec_cfg (%u > %u)", + sink_bis->codec_cfg.data_len + bis->data_len, + sizeof(sink_bis->codec_cfg.data)); - *bis_indexes |= BIT(bis->index); + return false; + } + + memcpy(&sink_bis->codec_cfg.data[sink_bis->codec_cfg.data_len], bis->data, + bis->data_len); + } +#endif /* CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 */ + + data->bis_count++; return true; } static bool base_subgroup_cb(const struct bt_bap_base_subgroup *subgroup, void *user_data) { - struct bt_bap_broadcast_sink *sink = user_data; - struct bt_bap_broadcast_sink_subgroup *sink_subgroup = - &sink->subgroups[sink->subgroup_count]; + struct bt_bap_broadcast_sink_subgroup *sink_subgroup; struct codec_cap_lookup_id_data lookup_data = {0}; + struct store_base_info_data *data = user_data; + struct bt_audio_codec_cfg codec_cfg; int ret; - if (sink->subgroup_count == ARRAY_SIZE(sink->subgroups)) { + if (data->subgroup_count == ARRAY_SIZE(data->subgroups)) { /* We've parsed as many subgroups as we support */ - LOG_DBG("Could only store %u subgroups", sink->subgroup_count); + LOG_DBG("Could only store %u subgroups", data->subgroup_count); return false; } - ret = bt_bap_base_subgroup_codec_to_codec_cfg(subgroup, &sink_subgroup->codec_cfg); - if (ret < 0) { - LOG_DBG("Could not store codec_cfg: %d", ret); - return false; - } + sink_subgroup = &data->subgroups[data->subgroup_count]; - ret = bt_bap_base_subgroup_foreach_bis(subgroup, base_subgroup_bis_index_cb, - &sink_subgroup->bis_indexes); + ret = bt_bap_base_subgroup_codec_to_codec_cfg(subgroup, &codec_cfg); if (ret < 0) { - LOG_DBG("Could not parse BISes: %d", ret); + LOG_DBG("Could not store codec_cfg: %d", ret); return false; } /* Lookup and assign path_id based on capabilities */ - lookup_data.id = sink_subgroup->codec_cfg.id; + lookup_data.id = codec_cfg.id; bt_pacs_cap_foreach(BT_AUDIO_DIR_SINK, codec_lookup_id, &lookup_data); if (lookup_data.codec_cap == NULL) { LOG_DBG("Codec with id %u is not supported by our capabilities", lookup_data.id); } else { + codec_cfg.path_id = lookup_data.codec_cap->path_id; + codec_cfg.ctlr_transcode = lookup_data.codec_cap->ctlr_transcode; + + data->subgroup_codec_cfg = &codec_cfg; + + ret = bt_bap_base_subgroup_foreach_bis(subgroup, base_subgroup_bis_index_cb, data); + if (ret < 0) { + LOG_DBG("Could not parse BISes: %d", ret); + return false; + } + /* Add BIS to bitfield of valid BIS indexes we support */ - sink->valid_indexes_bitfield |= sink_subgroup->bis_indexes; + data->valid_indexes_bitfield |= sink_subgroup->bis_indexes; + data->subgroup_count++; } - sink->subgroup_count++; - return true; } static int store_base_info(struct bt_bap_broadcast_sink *sink, const struct bt_bap_base *base) { + /* data is static due to its size, which easily can exceed the stack size */ + static struct store_base_info_data data; + uint32_t pres_delay; int ret; - sink->valid_indexes_bitfield = 0U; - sink->subgroup_count = 0U; - ret = bt_bap_base_get_pres_delay(base); if (ret < 0) { LOG_DBG("Could not get presentation delay: %d", ret); return ret; } - sink->codec_qos.pd = (uint32_t)ret; + pres_delay = (uint32_t)ret; - ret = bt_bap_base_foreach_subgroup(base, base_subgroup_cb, sink); + memset(&data, 0, sizeof(data)); + + ret = bt_bap_base_foreach_subgroup(base, base_subgroup_cb, &data); if (ret != 0) { LOG_DBG("Failed to parse all subgroups: %d", ret); return ret; } + /* Ensure that we have not synced while parsing the BASE */ + if (sink->big == NULL) { + sink->codec_qos.pd = pres_delay; + memcpy(sink->bis, data.bis, sizeof(sink->bis)); + memcpy(sink->subgroups, data.subgroups, sizeof(sink->subgroups)); + sink->subgroup_count = data.subgroup_count; + sink->valid_indexes_bitfield = data.valid_indexes_bitfield; + } + return 0; } @@ -940,14 +1039,18 @@ static void broadcast_sink_cleanup(struct bt_bap_broadcast_sink *sink) (void)memset(sink, 0, sizeof(*sink)); /* also clears flags */ } + static struct bt_audio_codec_cfg *codec_cfg_from_base_by_index(struct bt_bap_broadcast_sink *sink, uint8_t index) { - for (size_t i = 0U; i < sink->subgroup_count; i++) { - struct bt_bap_broadcast_sink_subgroup *subgroup = &sink->subgroups[i]; + for (size_t i = 0U; i < ARRAY_SIZE(sink->bis); i++) { + struct bt_bap_broadcast_sink_bis *bis = &sink->bis[i]; - if ((subgroup->bis_indexes & BIT(index)) != 0) { - return &subgroup->codec_cfg; + if (bis->index == index) { + return &bis->codec_cfg; + } else if (bis->index == 0) { + /* index 0 is invalid, so we can use that as a terminator in the array */ + break; } } @@ -1015,7 +1118,8 @@ int bt_bap_broadcast_sink_sync(struct bt_bap_broadcast_sink *sink, uint32_t inde struct bt_bap_stream *streams[], const uint8_t broadcast_code[16]) { struct bt_iso_big_sync_param param; - struct bt_audio_codec_cfg *codec_cfgs[CONFIG_BT_BAP_BROADCAST_SNK_SUBGROUP_COUNT] = {NULL}; + struct bt_audio_codec_cfg *codec_cfgs[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT] = {NULL}; + struct bt_iso_chan *bis_channels[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT]; uint8_t stream_count; int err; @@ -1110,12 +1214,14 @@ int bt_bap_broadcast_sink_sync(struct bt_bap_broadcast_sink *sink, uint32_t inde return err; } - sink->bis[i] = bt_bap_stream_iso_chan_get(stream); + sink->bis[i].chan = bt_bap_stream_iso_chan_get(stream); sys_slist_append(&sink->streams, &stream->_node); sink->stream_count++; + + bis_channels[i] = sink->bis[i].chan; } - param.bis_channels = sink->bis; + param.bis_channels = bis_channels; param.num_bis = sink->stream_count; param.bis_bitfield = indexes_bitfield; param.mse = 0; /* Let controller decide */ diff --git a/subsys/bluetooth/audio/bap_endpoint.h b/subsys/bluetooth/audio/bap_endpoint.h index aa2f326a71f..12b1209fb09 100644 --- a/subsys/bluetooth/audio/bap_endpoint.h +++ b/subsys/bluetooth/audio/bap_endpoint.h @@ -126,6 +126,11 @@ enum bt_bap_broadcast_sink_flag { struct bt_bap_broadcast_sink_subgroup { uint32_t bis_indexes; +}; + +struct bt_bap_broadcast_sink_bis { + uint8_t index; + struct bt_iso_chan *chan; struct bt_audio_codec_cfg codec_cfg; }; @@ -143,7 +148,7 @@ struct bt_bap_broadcast_sink { struct bt_audio_codec_qos codec_qos; struct bt_le_per_adv_sync *pa_sync; struct bt_iso_big *big; - struct bt_iso_chan *bis[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT]; + struct bt_bap_broadcast_sink_bis bis[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT]; struct bt_bap_broadcast_sink_subgroup subgroups[CONFIG_BT_BAP_BROADCAST_SNK_SUBGROUP_COUNT]; const struct bt_bap_scan_delegator_recv_state *recv_state; /* The streams used to create the broadcast sink */ From 8a6c1d9bfa1b1dc528693820cbcc3ca3c71e2973 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 23 Feb 2024 15:02:41 +0100 Subject: [PATCH 0012/2402] Bluetooth: BAP: Broadcast source: Add LTV validation for LC3 data When using the LC3 codec, all codec configuration are LTV encoded. The broadcast source did not properly validate this, and it also uncovered a bug in the bsim test for broadcast sources. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/bap_broadcast_source.c | 10 +++++++- subsys/bluetooth/audio/bap_stream.c | 23 +++++++++++++++++++ subsys/bluetooth/audio/bap_stream.h | 1 + .../bap_broadcast_source/uut/CMakeLists.txt | 1 + .../audio/src/bap_broadcast_source_test.c | 4 ++-- 5 files changed, 36 insertions(+), 3 deletions(-) diff --git a/subsys/bluetooth/audio/bap_broadcast_source.c b/subsys/bluetooth/audio/bap_broadcast_source.c index 4b7ca89fead..1b4993cb36b 100644 --- a/subsys/bluetooth/audio/bap_broadcast_source.c +++ b/subsys/bluetooth/audio/bap_broadcast_source.c @@ -578,6 +578,7 @@ static bool valid_broadcast_source_param(const struct bt_bap_broadcast_source_pa return false; } +#if CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 CHECKIF(stream_param->data == NULL && stream_param->data_len != 0) { LOG_DBG("subgroup_params[%zu].stream_params[%zu]->data is " "NULL with len %zu", @@ -585,7 +586,6 @@ static bool valid_broadcast_source_param(const struct bt_bap_broadcast_source_pa return false; } -#if CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 CHECKIF(stream_param->data_len > CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE) { LOG_DBG("subgroup_params[%zu].stream_params[%zu]->data_len too " "large: %zu > %d", @@ -593,6 +593,14 @@ static bool valid_broadcast_source_param(const struct bt_bap_broadcast_source_pa CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE); return false; } + + CHECKIF(subgroup_param->codec_cfg->id == BT_HCI_CODING_FORMAT_LC3 && + !bt_audio_valid_ltv(stream_param->data, stream_param->data_len)) { + LOG_DBG("subgroup_params[%zu].stream_params[%zu]->data not valid " + "LTV", + i, j); + return false; + } } #endif /* CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 */ } diff --git a/subsys/bluetooth/audio/bap_stream.c b/subsys/bluetooth/audio/bap_stream.c index 2f1cf71e8dd..1e132c57f00 100644 --- a/subsys/bluetooth/audio/bap_stream.c +++ b/subsys/bluetooth/audio/bap_stream.c @@ -180,6 +180,17 @@ enum bt_bap_ascs_reason bt_audio_verify_qos(const struct bt_audio_codec_qos *qos return BT_BAP_ASCS_REASON_NONE; } +static bool valid_ltv_cb(struct bt_data *data, void *user_data) +{ + /* just return true to continue parsing as bt_data_parse will validate for us */ + return true; +} + +bool bt_audio_valid_ltv(const uint8_t *data, uint8_t data_len) +{ + return bt_audio_data_parse(data, data_len, valid_ltv_cb, NULL) == 0; +} + bool bt_audio_valid_codec_cfg(const struct bt_audio_codec_cfg *codec_cfg) { if (codec_cfg == NULL) { @@ -212,6 +223,12 @@ bool bt_audio_valid_codec_cfg(const struct bt_audio_codec_cfg *codec_cfg) LOG_DBG("codec_cfg->data_len (%zu) is invalid", codec_cfg->data_len); return false; } + + if (codec_cfg->id == BT_HCI_CODING_FORMAT_LC3 && + !bt_audio_valid_ltv(codec_cfg->data, codec_cfg->data_len)) { + LOG_DBG("codec_cfg->data not valid LTV"); + return false; + } #endif /* CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 */ #if CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE > 0 @@ -219,6 +236,12 @@ bool bt_audio_valid_codec_cfg(const struct bt_audio_codec_cfg *codec_cfg) LOG_DBG("codec_cfg->meta_len (%zu) is invalid", codec_cfg->meta_len); return false; } + + if (codec_cfg->id == BT_HCI_CODING_FORMAT_LC3 && + !bt_audio_valid_ltv(codec_cfg->data, codec_cfg->data_len)) { + LOG_DBG("codec_cfg->meta not valid LTV"); + return false; + } #endif /* CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE > 0 */ return true; diff --git a/subsys/bluetooth/audio/bap_stream.h b/subsys/bluetooth/audio/bap_stream.h index d16cf2cfcc9..3d02c2cf30c 100644 --- a/subsys/bluetooth/audio/bap_stream.h +++ b/subsys/bluetooth/audio/bap_stream.h @@ -23,6 +23,7 @@ void bt_audio_codec_qos_to_iso_qos(struct bt_iso_chan_io_qos *io, void bt_bap_stream_detach(struct bt_bap_stream *stream); enum bt_bap_ascs_reason bt_audio_verify_qos(const struct bt_audio_codec_qos *qos); +bool bt_audio_valid_ltv(const uint8_t *data, uint8_t data_len); bool bt_audio_valid_codec_cfg(const struct bt_audio_codec_cfg *codec_cfg); bool bt_bap_stream_can_disconnect(const struct bt_bap_stream *stream); diff --git a/tests/bluetooth/audio/bap_broadcast_source/uut/CMakeLists.txt b/tests/bluetooth/audio/bap_broadcast_source/uut/CMakeLists.txt index 85f68a6d1a6..aea487e1b97 100644 --- a/tests/bluetooth/audio/bap_broadcast_source/uut/CMakeLists.txt +++ b/tests/bluetooth/audio/bap_broadcast_source/uut/CMakeLists.txt @@ -7,6 +7,7 @@ # add_library(uut STATIC + ${ZEPHYR_BASE}/subsys/bluetooth/audio/audio.c ${ZEPHYR_BASE}/subsys/bluetooth/audio/bap_iso.c ${ZEPHYR_BASE}/subsys/bluetooth/audio/bap_stream.c ${ZEPHYR_BASE}/subsys/bluetooth/audio/bap_broadcast_source.c diff --git a/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c b/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c index cd5800c539f..ccd26af4e9c 100644 --- a/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c +++ b/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c @@ -97,8 +97,8 @@ static struct bt_bap_stream_ops stream_ops = { static int setup_broadcast_source(struct bt_bap_broadcast_source **source) { uint8_t bis_codec_data[] = { - BT_AUDIO_CODEC_DATA(BT_AUDIO_CODEC_CFG_FREQ, - BT_BYTES_LIST_LE16(BT_AUDIO_CODEC_CFG_FREQ_16KHZ)), + BT_AUDIO_CODEC_DATA(BT_AUDIO_CODEC_CFG_CHAN_ALLOC, + BT_BYTES_LIST_LE32(BT_AUDIO_LOCATION_FRONT_LEFT)), }; struct bt_bap_broadcast_source_stream_param stream_params[ARRAY_SIZE(broadcast_source_streams)]; From a7fe85343622a85812985616dae15aec71ec8537 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 23 Feb 2024 15:03:59 +0100 Subject: [PATCH 0013/2402] tests: bsim: Bluetooth: Add broadcast sink cfg data validation Add additional validation of the config data in the broadcast sink test, both ensuring that the BASE is properly parsed, that the BASE contains mandatory information and that the stream get the right values copied. Signed-off-by: Emil Gydesen --- .../audio/src/bap_broadcast_sink_test.c | 246 +++++++++++++++++- 1 file changed, 243 insertions(+), 3 deletions(-) diff --git a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c index 17bd417e5f8..9dd143f59a5 100644 --- a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c +++ b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c @@ -37,10 +37,24 @@ static uint32_t requested_bis_sync; static struct bt_le_ext_adv *ext_adv; static const struct bt_bap_scan_delegator_recv_state *req_recv_state; +#define SUPPORTED_CHAN_COUNTS BT_AUDIO_CODEC_CAP_CHAN_COUNT_SUPPORT(1, 2) +#define SUPPORTED_MIN_OCTETS_PER_FRAME 30 +#define SUPPORTED_MAX_OCTETS_PER_FRAME 155 +#define SUPPORTED_MAX_FRAMES_PER_SDU 1 + +/* We support 1 or 2 channels, so the maximum SDU size we support will be 2 times the maximum frame + * size per frame we support + */ +#define SUPPORTED_MAX_SDU_SIZE (2 * SUPPORTED_MAX_FRAMES_PER_SDU * SUPPORTED_MAX_OCTETS_PER_FRAME) + +BUILD_ASSERT(CONFIG_BT_ISO_RX_MTU >= SUPPORTED_MAX_SDU_SIZE); + +#define SUPPORTED_CONTEXTS (BT_AUDIO_CONTEXT_TYPE_CONVERSATIONAL | BT_AUDIO_CONTEXT_TYPE_MEDIA) + static const struct bt_audio_codec_cap codec_cap = BT_AUDIO_CODEC_CAP_LC3( - BT_AUDIO_CODEC_CAP_FREQ_ANY, BT_AUDIO_CODEC_CAP_DURATION_ANY, - BT_AUDIO_CODEC_CAP_CHAN_COUNT_SUPPORT(1, 2), 30, 240, 2, - (BT_AUDIO_CONTEXT_TYPE_CONVERSATIONAL | BT_AUDIO_CONTEXT_TYPE_MEDIA)); + BT_AUDIO_CODEC_CAP_FREQ_ANY, BT_AUDIO_CODEC_CAP_DURATION_ANY, SUPPORTED_CHAN_COUNTS, + SUPPORTED_MIN_OCTETS_PER_FRAME, SUPPORTED_MAX_OCTETS_PER_FRAME, + SUPPORTED_MAX_FRAMES_PER_SDU, SUPPORTED_CONTEXTS); static K_SEM_DEFINE(sem_started, 0U, ARRAY_SIZE(streams)); static K_SEM_DEFINE(sem_stopped, 0U, ARRAY_SIZE(streams)); @@ -52,6 +66,122 @@ static K_SEM_DEFINE(sem_stopped, 0U, ARRAY_SIZE(streams)); static const uint32_t bis_index_mask = BIT_MASK(ARRAY_SIZE(streams) + 1U); static uint32_t bis_index_bitfield; +static uint8_t count_bits(enum bt_audio_location chan_allocation) +{ + uint8_t cnt = 0U; + + while (chan_allocation != 0) { + cnt += chan_allocation & 1U; + chan_allocation >>= 1; + } + + return cnt; +} + +static bool valid_base_subgroup(const struct bt_bap_base_subgroup *subgroup) +{ + struct bt_audio_codec_cfg codec_cfg = {0}; + enum bt_audio_location chan_allocation; + uint8_t frames_blocks_per_sdu; + size_t min_sdu_size_required; + uint16_t octets_per_frame; + uint8_t chan_cnt; + int ret; + + ret = bt_bap_base_subgroup_codec_to_codec_cfg(subgroup, &codec_cfg); + if (ret < 0) { + printk("Could not get subgroup codec_cfg: %d\n", ret); + + return false; + } + + ret = bt_audio_codec_cfg_get_freq(&codec_cfg); + if (ret >= 0) { + const int freq = bt_audio_codec_cfg_freq_to_freq_hz(ret); + + if (freq < 0) { + printk("Invalid subgroup frequency value: %d (%d)\n", ret, freq); + + return false; + } + } else { + printk("Could not get subgroup frequency: %d\n", ret); + + return false; + } + + ret = bt_audio_codec_cfg_get_frame_dur(&codec_cfg); + if (ret >= 0) { + const int frame_duration_us = bt_audio_codec_cfg_frame_dur_to_frame_dur_us(ret); + + if (frame_duration_us < 0) { + printk("Invalid subgroup frame duration value: %d (%d)\n", ret, + frame_duration_us); + + return false; + } + } else { + printk("Could not get subgroup frame duration: %d\n", ret); + + return false; + } + + ret = bt_audio_codec_cfg_get_chan_allocation(&codec_cfg, &chan_allocation); + if (ret == 0) { + chan_cnt = count_bits(chan_allocation); + } else { + printk("Could not get subgroup channel allocation: %d\n", ret); + /* Channel allocation is an optional field, and omitting it implicitly means mono */ + chan_cnt = 1U; + } + + if (chan_cnt == 0 || (BIT(chan_cnt - 1) & SUPPORTED_CHAN_COUNTS) == 0) { + printk("Unsupported channel count: %u\n", chan_cnt); + + return false; + } + + ret = bt_audio_codec_cfg_get_octets_per_frame(&codec_cfg); + if (ret > 0) { + octets_per_frame = (uint16_t)ret; + } else { + printk("Could not get subgroup octets per frame: %d\n", ret); + + return false; + } + + if (!IN_RANGE(octets_per_frame, SUPPORTED_MIN_OCTETS_PER_FRAME, + SUPPORTED_MAX_OCTETS_PER_FRAME)) { + printk("Unsupported octets per frame: %u\n", octets_per_frame); + + return false; + } + + ret = bt_audio_codec_cfg_get_frame_blocks_per_sdu(&codec_cfg, false); + if (ret > 0) { + frames_blocks_per_sdu = (uint8_t)ret; + } else { + printk("Could not get subgroup octets per frame: %d\n", ret); + /* Frame blocks per SDU is optional and is implicitly 1 */ + frames_blocks_per_sdu = 1U; + } + + /* An SDU can consist of X frame blocks, each with Y frames (one per channel) of size Z in + * them. The minimum SDU size required for this is X * Y * Z. + */ + min_sdu_size_required = chan_cnt * octets_per_frame * frames_blocks_per_sdu; + if (min_sdu_size_required > SUPPORTED_MAX_SDU_SIZE) { + printk("With %zu channels and %u octets per frame and %u frames per block, SDUs " + "shall be at minimum %zu, we only support %d\n", + chan_cnt, octets_per_frame, frames_blocks_per_sdu, min_sdu_size_required, + SUPPORTED_MAX_SDU_SIZE); + + return false; + } + + return true; +} + static bool base_subgroup_cb(const struct bt_bap_base_subgroup *subgroup, void *user_data) { static uint8_t metadata[CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE]; @@ -74,6 +204,11 @@ static bool base_subgroup_cb(const struct bt_bap_base_subgroup *subgroup, void * metadata_size = (size_t)ret; (void)memcpy(metadata, meta, metadata_size); + if (!valid_base_subgroup(subgroup)) { + printk("Invalid or unsupported subgroup\n"); + return false; + } + return true; } @@ -258,10 +393,115 @@ static struct bt_bap_scan_delegator_cb scan_delegator_cbs = { .bis_sync_req = bis_sync_req_cb, }; +static void validate_stream_codec_cfg(const struct bt_bap_stream *stream) +{ + struct bt_audio_codec_cfg *codec_cfg = stream->codec_cfg; + enum bt_audio_location chan_allocation; + uint8_t frames_blocks_per_sdu; + size_t min_sdu_size_required; + uint16_t octets_per_frame; + uint8_t chan_cnt; + int ret; + + ret = bt_audio_codec_cfg_get_freq(codec_cfg); + if (ret >= 0) { + const int freq = bt_audio_codec_cfg_freq_to_freq_hz(ret); + + if (freq < 0) { + FAIL("Invalid frequency value: %d (%d)\n", ret, freq); + + return; + } + } else { + FAIL("Could not get frequency: %d\n", ret); + + return; + } + + ret = bt_audio_codec_cfg_get_frame_dur(codec_cfg); + if (ret >= 0) { + const int frame_duration_us = bt_audio_codec_cfg_frame_dur_to_frame_dur_us(ret); + + if (frame_duration_us < 0) { + FAIL("Invalid frame duration value: %d (%d)\n", ret, frame_duration_us); + + return; + } + } else { + FAIL("Could not get frame duration: %d\n", ret); + + return; + } + + /* The broadcast source sets the channel allocation in the BIS to + * BT_AUDIO_LOCATION_FRONT_LEFT + */ + ret = bt_audio_codec_cfg_get_chan_allocation(codec_cfg, &chan_allocation); + if (ret == 0) { + if (chan_allocation != BT_AUDIO_LOCATION_FRONT_LEFT) { + FAIL("Unexpected channel allocation: 0x%08X", chan_allocation); + + return; + } + + chan_cnt = count_bits(chan_allocation); + } else { + FAIL("Could not get subgroup channel allocation: %d\n", ret); + + return; + } + + if (chan_cnt == 0 || (BIT(chan_cnt - 1) & SUPPORTED_CHAN_COUNTS) == 0) { + FAIL("Unsupported channel count: %u\n", chan_cnt); + + return; + } + + ret = bt_audio_codec_cfg_get_octets_per_frame(codec_cfg); + if (ret > 0) { + octets_per_frame = (uint16_t)ret; + } else { + FAIL("Could not get subgroup octets per frame: %d\n", ret); + + return; + } + + if (!IN_RANGE(octets_per_frame, SUPPORTED_MIN_OCTETS_PER_FRAME, + SUPPORTED_MAX_OCTETS_PER_FRAME)) { + FAIL("Unsupported octets per frame: %u\n", octets_per_frame); + + return; + } + + ret = bt_audio_codec_cfg_get_frame_blocks_per_sdu(codec_cfg, false); + if (ret > 0) { + frames_blocks_per_sdu = (uint8_t)ret; + } else { + printk("Could not get octets per frame: %d\n", ret); + /* Frame blocks per SDU is optional and is implicitly 1 */ + frames_blocks_per_sdu = 1U; + } + + /* An SDU can consist of X frame blocks, each with Y frames (one per channel) of size Z in + * them. The minimum SDU size required for this is X * Y * Z. + */ + min_sdu_size_required = chan_cnt * octets_per_frame * frames_blocks_per_sdu; + if (min_sdu_size_required > stream->qos->sdu) { + FAIL("With %zu channels and %u octets per frame and %u frames per block, SDUs " + "shall be at minimum %zu, but the stream has been configured for %u\n", + chan_cnt, octets_per_frame, frames_blocks_per_sdu, min_sdu_size_required, + stream->qos->sdu); + + return; + } +} + static void started_cb(struct bt_bap_stream *stream) { printk("Stream %p started\n", stream); k_sem_give(&sem_started); + + validate_stream_codec_cfg(stream); } static void stopped_cb(struct bt_bap_stream *stream, uint8_t reason) From 248bee9b17517b95cae1614eb8463a0d788abc3a Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 23 Feb 2024 17:45:07 +0100 Subject: [PATCH 0014/2402] Bluetooth: BAP: Broadcast Source: Remove unused variable Remove an unused variable in bt_bap_broadcast_source_reconfig that causes compiler warnings. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/bap_broadcast_source.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/subsys/bluetooth/audio/bap_broadcast_source.c b/subsys/bluetooth/audio/bap_broadcast_source.c index 1b4993cb36b..45b90e56d32 100644 --- a/subsys/bluetooth/audio/bap_broadcast_source.c +++ b/subsys/bluetooth/audio/bap_broadcast_source.c @@ -893,9 +893,6 @@ int bt_bap_broadcast_source_reconfig(struct bt_bap_broadcast_source *source, * params */ SYS_SLIST_FOR_EACH_CONTAINER(&subgroup->streams, stream, _node) { - struct bt_iso_chan_io_qos *iso_qos; - - iso_qos = stream->ep->iso->chan.qos->tx; bt_bap_stream_attach(NULL, stream, stream->ep, codec_cfg); bt_bap_iso_configure_data_path(stream->ep, codec_cfg); } From 8bb9bb67db5f4a4c202dc09dc1b1a53ef86e09a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20J=C3=A4ger?= Date: Mon, 15 Jan 2024 00:41:05 +0100 Subject: [PATCH 0015/2402] lorawan: add emulator for unit testing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The emulator can be used for unit testing of LoRaWAN services. It provides interfaces to send arbitrary messages to the LoRaWAN stack and receive the response through callbacks without using actual LoRa hardware. Signed-off-by: Martin Jäger --- include/zephyr/lorawan/emul.h | 45 ++++++++++ subsys/lorawan/CMakeLists.txt | 11 ++- subsys/lorawan/Kconfig | 10 +++ subsys/lorawan/lorawan_emul.c | 158 ++++++++++++++++++++++++++++++++++ 4 files changed, 222 insertions(+), 2 deletions(-) create mode 100644 include/zephyr/lorawan/emul.h create mode 100644 subsys/lorawan/lorawan_emul.c diff --git a/include/zephyr/lorawan/emul.h b/include/zephyr/lorawan/emul.h new file mode 100644 index 00000000000..f49ee8c987f --- /dev/null +++ b/include/zephyr/lorawan/emul.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 A Labs GmbH + * Copyright (c) 2024 tado GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_LORAWAN_EMUL_H_ +#define ZEPHYR_INCLUDE_LORAWAN_EMUL_H_ + +#include +#include + +#include + +/** + * @brief Defines the emulator uplink callback handler function signature. + * + * @param port LoRaWAN port + * @param len Payload data length + * @param data Pointer to the payload data + */ +typedef void (*lorawan_uplink_cb_t)(uint8_t port, uint8_t len, const uint8_t *data); + +/** + * @brief Emulate LoRaWAN downlink message + * + * @param port Port message was sent on + * @param data_pending Network server has more downlink packets pending + * @param rssi Received signal strength in dBm + * @param snr Signal to Noise ratio in dBm + * @param len Length of data received, will be 0 for ACKs + * @param data Data received, will be NULL for ACKs + */ +void lorawan_emul_send_downlink(uint8_t port, bool data_pending, int16_t rssi, int8_t snr, + uint8_t len, const uint8_t *data); + +/** + * @brief Register callback for emulated uplink messages + * + * @param cb Pointer to the uplink callback handler function + */ +void lorawan_emul_register_uplink_callback(lorawan_uplink_cb_t cb); + +#endif /* ZEPHYR_INCLUDE_LORAWAN_EMUL_H_ */ diff --git a/subsys/lorawan/CMakeLists.txt b/subsys/lorawan/CMakeLists.txt index 8b26ce10050..d0b3e175748 100644 --- a/subsys/lorawan/CMakeLists.txt +++ b/subsys/lorawan/CMakeLists.txt @@ -20,8 +20,15 @@ zephyr_compile_definitions_ifdef(CONFIG_LORAMAC_REGION_IN865 REGION_IN865) zephyr_compile_definitions_ifdef(CONFIG_LORAMAC_REGION_US915 REGION_US915) zephyr_compile_definitions_ifdef(CONFIG_LORAMAC_REGION_RU864 REGION_RU864) -zephyr_library_sources_ifdef(CONFIG_LORAWAN lorawan.c) -zephyr_library_sources_ifdef(CONFIG_LORAWAN lw_priv.c) +if(CONFIG_LORAWAN) + if(CONFIG_LORAWAN_EMUL) + zephyr_library_sources(lorawan_emul.c) + else() + zephyr_library_sources(lorawan.c) + endif() + + zephyr_library_sources(lw_priv.c) +endif() add_subdirectory(services) add_subdirectory(nvm) diff --git a/subsys/lorawan/Kconfig b/subsys/lorawan/Kconfig index 229e075b5c5..9d66144c8a2 100644 --- a/subsys/lorawan/Kconfig +++ b/subsys/lorawan/Kconfig @@ -20,6 +20,16 @@ module = LORAWAN module-str = lorawan source "subsys/logging/Kconfig.template.log_config" +config LORAWAN_EMUL + bool "LoRaWAN Emulator" + help + The emulator can be used for unit testing of LoRaWAN services. + It provides interfaces to send arbitrary messages to the LoRaWAN + stack and receive the response through callbacks without using + actual LoRa hardware. + + See include/zephyr/lorawan/emul.h for the emulator API. + config LORAWAN_SYSTEM_MAX_RX_ERROR int "LoRaWAN System Max Rx Error" default 20 diff --git a/subsys/lorawan/lorawan_emul.c b/subsys/lorawan/lorawan_emul.c new file mode 100644 index 00000000000..e3d29715a01 --- /dev/null +++ b/subsys/lorawan/lorawan_emul.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2024 A Labs GmbH + * Copyright (c) 2024 tado GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include +#include + +#include +#include +#include + +LOG_MODULE_REGISTER(lorawan_emul, CONFIG_LORAWAN_LOG_LEVEL); + +static bool lorawan_adr_enable; + +static sys_slist_t dl_callbacks; + +static DeviceClass_t current_class; + +static lorawan_battery_level_cb_t battery_level_cb; +static lorawan_dr_changed_cb_t dr_changed_cb; +static lorawan_uplink_cb_t uplink_cb; + +/* implementation required by the soft-se (software secure element) */ +void BoardGetUniqueId(uint8_t *id) +{ + /* Do not change the default value */ +} + +void lorawan_emul_send_downlink(uint8_t port, bool data_pending, int16_t rssi, int8_t snr, + uint8_t len, const uint8_t *data) +{ + struct lorawan_downlink_cb *cb; + + /* Iterate over all registered downlink callbacks */ + SYS_SLIST_FOR_EACH_CONTAINER(&dl_callbacks, cb, node) { + if ((cb->port == LW_RECV_PORT_ANY) || (cb->port == port)) { + cb->cb(port, data_pending, rssi, snr, len, data); + } + } +} + +int lorawan_join(const struct lorawan_join_config *join_cfg) +{ + return 0; +} + +int lorawan_set_class(enum lorawan_class dev_class) +{ + switch (dev_class) { + case LORAWAN_CLASS_A: + current_class = CLASS_A; + break; + case LORAWAN_CLASS_B: + LOG_ERR("Class B not supported yet!"); + return -ENOTSUP; + case LORAWAN_CLASS_C: + current_class = CLASS_C; + break; + default: + return -EINVAL; + } + + return 0; +} + +int lorawan_set_datarate(enum lorawan_datarate dr) +{ + ARG_UNUSED(dr); + + /* Bail out if using ADR */ + if (lorawan_adr_enable) { + return -EINVAL; + } + + return 0; +} + +void lorawan_get_payload_sizes(uint8_t *max_next_payload_size, uint8_t *max_payload_size) +{ + LoRaMacTxInfo_t tx_info; + + /* QueryTxPossible cannot fail */ + (void)LoRaMacQueryTxPossible(0, &tx_info); + + *max_next_payload_size = tx_info.MaxPossibleApplicationDataSize; + *max_payload_size = tx_info.CurrentPossiblePayloadSize; +} + +enum lorawan_datarate lorawan_get_min_datarate(void) +{ + return LORAWAN_DR_0; +} + +void lorawan_enable_adr(bool enable) +{ + lorawan_adr_enable = enable; +} + +int lorawan_set_conf_msg_tries(uint8_t tries) +{ + return 0; +} + +int lorawan_send(uint8_t port, uint8_t *data, uint8_t len, enum lorawan_message_type type) +{ + if (data == NULL) { + return -EINVAL; + } + + if (uplink_cb != NULL) { + uplink_cb(port, len, data); + } + + return 0; +} + +void lorawan_register_battery_level_callback(lorawan_battery_level_cb_t cb) +{ + battery_level_cb = cb; +} + +void lorawan_register_downlink_callback(struct lorawan_downlink_cb *cb) +{ + sys_slist_append(&dl_callbacks, &cb->node); +} + +void lorawan_register_dr_changed_callback(lorawan_dr_changed_cb_t cb) +{ + dr_changed_cb = cb; +} + +int lorawan_start(void) +{ + return 0; +} + +static int lorawan_init(void) +{ + sys_slist_init(&dl_callbacks); + + return 0; +} + +void lorawan_emul_register_uplink_callback(lorawan_uplink_cb_t cb) +{ + uplink_cb = cb; +} + +SYS_INIT(lorawan_init, POST_KERNEL, 0); From 776c850896b56f04c0bda9c82a10ead5043b1dcd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20J=C3=A4ger?= Date: Mon, 5 Feb 2024 13:59:40 +0100 Subject: [PATCH 0016/2402] lorawan: services: clock_sync: fix resync with multiple transmissions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only the first resync transmission was sent out immediately because the work item was rescheduled to the usual periodicity in the work handler immediately after sending out the first transmission. Signed-off-by: Martin Jäger --- subsys/lorawan/services/clock_sync.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/subsys/lorawan/services/clock_sync.c b/subsys/lorawan/services/clock_sync.c index 1c7b32d0072..8f9077927dc 100644 --- a/subsys/lorawan/services/clock_sync.c +++ b/subsys/lorawan/services/clock_sync.c @@ -191,11 +191,6 @@ static int clock_sync_app_time_req(void) lorawan_services_schedule_uplink(LORAWAN_PORT_CLOCK_SYNC, tx_buf, tx_pos, 0); - if (ctx.nb_transmissions > 0) { - ctx.nb_transmissions--; - lorawan_services_reschedule_work(&ctx.resync_work, K_SECONDS(CLOCK_RESYNC_DELAY)); - } - return 0; } @@ -205,10 +200,15 @@ static void clock_sync_resync_handler(struct k_work *work) clock_sync_app_time_req(); - /* Add +-30s jitter to actual periodicity as required */ - periodicity = ctx.periodicity - 30 + sys_rand32_get() % 61; + if (ctx.nb_transmissions > 0) { + ctx.nb_transmissions--; + lorawan_services_reschedule_work(&ctx.resync_work, K_SECONDS(CLOCK_RESYNC_DELAY)); + } else { + /* Add +-30s jitter to actual periodicity as required */ + periodicity = ctx.periodicity - 30 + sys_rand32_get() % 61; - lorawan_services_reschedule_work(&ctx.resync_work, K_SECONDS(periodicity)); + lorawan_services_reschedule_work(&ctx.resync_work, K_SECONDS(periodicity)); + } } int lorawan_clock_sync_get(uint32_t *gps_time) From bfcd887903ecc0e54d0f271a620128433a87f524 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20J=C3=A4ger?= Date: Mon, 5 Feb 2024 15:33:21 +0100 Subject: [PATCH 0017/2402] lorawan: services: clock_sync: apply changed periodicity immediately MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The work item for re-synchronization should be rescheduled immediately after the periodicity is changed. Calculation of the periodicity incl. jitter is moved to a dedicated function so that it can be re-used. Signed-off-by: Martin Jäger --- subsys/lorawan/services/clock_sync.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/subsys/lorawan/services/clock_sync.c b/subsys/lorawan/services/clock_sync.c index 8f9077927dc..a4532fdee14 100644 --- a/subsys/lorawan/services/clock_sync.c +++ b/subsys/lorawan/services/clock_sync.c @@ -85,6 +85,12 @@ static int clock_sync_serialize_device_time(uint8_t *buf, size_t size) return sizeof(uint32_t); } +static inline k_timeout_t clock_sync_calc_periodicity(void) +{ + /* add +-30s jitter to nominal periodicity as required by the spec */ + return K_SECONDS(ctx.periodicity - 30 + sys_rand32_get() % 61); +} + static void clock_sync_package_callback(uint8_t port, bool data_pending, int16_t rssi, int8_t snr, uint8_t len, const uint8_t *rx_buf) { @@ -145,6 +151,9 @@ static void clock_sync_package_callback(uint8_t port, bool data_pending, int16_t tx_pos += clock_sync_serialize_device_time(tx_buf + tx_pos, sizeof(tx_buf) - tx_pos); + lorawan_services_reschedule_work(&ctx.resync_work, + clock_sync_calc_periodicity()); + LOG_DBG("DeviceAppTimePeriodicityReq period: %u", period); break; } @@ -196,18 +205,14 @@ static int clock_sync_app_time_req(void) static void clock_sync_resync_handler(struct k_work *work) { - uint32_t periodicity; - clock_sync_app_time_req(); if (ctx.nb_transmissions > 0) { ctx.nb_transmissions--; lorawan_services_reschedule_work(&ctx.resync_work, K_SECONDS(CLOCK_RESYNC_DELAY)); } else { - /* Add +-30s jitter to actual periodicity as required */ - periodicity = ctx.periodicity - 30 + sys_rand32_get() % 61; - - lorawan_services_reschedule_work(&ctx.resync_work, K_SECONDS(periodicity)); + lorawan_services_reschedule_work(&ctx.resync_work, + clock_sync_calc_periodicity()); } } From 52da66ab00c3095885c46769b4f847ae0f16cab5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20J=C3=A4ger?= Date: Mon, 5 Feb 2024 18:49:10 +0100 Subject: [PATCH 0018/2402] west.yml: update loramac-node to fix double promotion warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes implicit double promotion in RegionCommon.c. The calculation is done with float variables. However, the floor function is meant for double variables. floorf should be used instead. The implicit double promotion leads to a warning/error if compiled with LLVM in CI. Signed-off-by: Martin Jäger --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index da5a202241b..3e8b2f0fa48 100644 --- a/west.yml +++ b/west.yml @@ -271,7 +271,7 @@ manifest: - fs revision: 408c16a909dd6cf128874a76f21c793798c9e423 - name: loramac-node - revision: 842413c5fb98707eb5f26e619e8e792453877897 + revision: 1bf2120cffcedae174ae35d695a28a46caefcb23 path: modules/lib/loramac-node - name: lvgl revision: 2b76c641749725ac90c6ac7959ca7718804cf356 From aef6588820d07d79a00ea5d0a5818d89f2c1d066 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20J=C3=A4ger?= Date: Mon, 5 Feb 2024 15:42:07 +0100 Subject: [PATCH 0019/2402] tests: subsys: lorawan: add clock_sync test MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Checks all commands of the application-layer clock sync service in CI. Signed-off-by: Martin Jäger --- .../subsys/lorawan/clock_sync/CMakeLists.txt | 9 + .../lorawan/clock_sync/boards/native_sim.conf | 4 + .../clock_sync/boards/native_sim.overlay | 50 +++++ tests/subsys/lorawan/clock_sync/prj.conf | 28 +++ tests/subsys/lorawan/clock_sync/src/main.c | 191 ++++++++++++++++++ tests/subsys/lorawan/clock_sync/testcase.yaml | 14 ++ 6 files changed, 296 insertions(+) create mode 100644 tests/subsys/lorawan/clock_sync/CMakeLists.txt create mode 100644 tests/subsys/lorawan/clock_sync/boards/native_sim.conf create mode 100644 tests/subsys/lorawan/clock_sync/boards/native_sim.overlay create mode 100644 tests/subsys/lorawan/clock_sync/prj.conf create mode 100644 tests/subsys/lorawan/clock_sync/src/main.c create mode 100644 tests/subsys/lorawan/clock_sync/testcase.yaml diff --git a/tests/subsys/lorawan/clock_sync/CMakeLists.txt b/tests/subsys/lorawan/clock_sync/CMakeLists.txt new file mode 100644 index 00000000000..61d12dc5725 --- /dev/null +++ b/tests/subsys/lorawan/clock_sync/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(lorawan_clock_sync_test) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/tests/subsys/lorawan/clock_sync/boards/native_sim.conf b/tests/subsys/lorawan/clock_sync/boards/native_sim.conf new file mode 100644 index 00000000000..ef6a0585184 --- /dev/null +++ b/tests/subsys/lorawan/clock_sync/boards/native_sim.conf @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Turn off log messages for failed communication with non-existing LoRa PHY +CONFIG_LORA_LOG_LEVEL_OFF=y diff --git a/tests/subsys/lorawan/clock_sync/boards/native_sim.overlay b/tests/subsys/lorawan/clock_sync/boards/native_sim.overlay new file mode 100644 index 00000000000..5101a21d8c3 --- /dev/null +++ b/tests/subsys/lorawan/clock_sync/boards/native_sim.overlay @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2024 A Labs GmbH + * + * SPDX-License-Identifier: Apache-2.0 + * + * This overlay defines a fake LoRa PHY node which is required to build the driver. + */ + +#include + +/ { + chosen { + zephyr,code-partition = &slot0_partition; + }; + + aliases { + lora0 = &lora; + }; + + test { + #address-cells = <1>; + #size-cells = <1>; + + test_spi: spi@33334444 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "vnd,spi"; + reg = <0x33334444 0x1000>; + status = "okay"; + clock-frequency = <2000000>; + + cs-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + + lora: lora@0 { + compatible = "semtech,sx1262"; + status = "okay"; + reg = <0>; + reset-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + busy-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + tx-enable-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + rx-enable-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + dio1-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + dio2-tx-enable; + dio3-tcxo-voltage = ; + tcxo-power-startup-delay-ms = <5>; + spi-max-frequency = <1000000>; + }; + }; + }; +}; diff --git a/tests/subsys/lorawan/clock_sync/prj.conf b/tests/subsys/lorawan/clock_sync/prj.conf new file mode 100644 index 00000000000..966bfa8225b --- /dev/null +++ b/tests/subsys/lorawan/clock_sync/prj.conf @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ZTEST=y + +# General Zephyr settings +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048 +CONFIG_THREAD_NAME=y +CONFIG_LOG=y + +# LoRa PHY and required peripherals +CONFIG_LORA=y +CONFIG_SPI=y +CONFIG_GPIO=y + +# Random number generator required for several LoRaWAN services +CONFIG_ENTROPY_GENERATOR=y + +# LoRaWAN application layer +CONFIG_LORAWAN=y +CONFIG_LORAWAN_EMUL=y +CONFIG_LORAMAC_REGION_EU868=y + +# LoRaWAN services required for this test +CONFIG_LORAWAN_SERVICES=y +CONFIG_LORAWAN_APP_CLOCK_SYNC=y +# use shortest possible periodicity for testing +CONFIG_LORAWAN_APP_CLOCK_SYNC_PERIODICITY=128 diff --git a/tests/subsys/lorawan/clock_sync/src/main.c b/tests/subsys/lorawan/clock_sync/src/main.c new file mode 100644 index 00000000000..f1557c9fcba --- /dev/null +++ b/tests/subsys/lorawan/clock_sync/src/main.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2024 A Labs GmbH + * Copyright (c) 2024 tado GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +#define CMD_PACKAGE_VERSION (0x00) +#define CMD_APP_TIME (0x01) +#define CMD_DEVICE_APP_TIME_PERIODICITY (0x02) +#define CMD_FORCE_DEVICE_RESYNC (0x03) + +#define CLOCK_SYNC_PORT (202) +#define CLOCK_SYNC_ID + +struct lorawan_msg { + /* large enough buffer to fit maximum clock sync message length */ + uint8_t data[6]; + uint8_t len; +}; + +K_MSGQ_DEFINE(uplink_msgq, sizeof(struct lorawan_msg), 10, 4); + +void uplink_handler(uint8_t port, uint8_t len, const uint8_t *data) +{ + struct lorawan_msg msg; + int ret; + + zassert_equal(port, CLOCK_SYNC_PORT); + + zassert_true(len <= sizeof(msg.data)); + memcpy(msg.data, data, len); + msg.len = len; + + ret = k_msgq_put(&uplink_msgq, &msg, K_NO_WAIT); + zassert_equal(ret, 0); +} + +ZTEST(clock_sync, test_package_version) +{ + struct lorawan_msg ans; + uint8_t req_data[] = {CMD_PACKAGE_VERSION}; + int ret; + + k_msgq_purge(&uplink_msgq); + + lorawan_emul_send_downlink(CLOCK_SYNC_PORT, false, 0, 0, sizeof(req_data), req_data); + + ret = k_msgq_get(&uplink_msgq, &ans, K_MSEC(100)); + zassert_equal(ret, 0, "receiving PackageVersionAns timed out"); + zassert_equal(ans.len, 3); + zassert_equal(ans.data[0], CMD_PACKAGE_VERSION); + zassert_equal(ans.data[1], 1); /* PackageIdentifier */ + zassert_equal(ans.data[2], 2); /* PackageVersion */ +} + +ZTEST(clock_sync, test_app_time) +{ + uint8_t ans_data[6] = {CMD_APP_TIME}; + struct lorawan_msg req; + uint32_t device_time; + uint32_t gps_time; + uint8_t token_req; + int ret; + + k_msgq_purge(&uplink_msgq); + + /* wait for more than the default (=minimum) periodicity of 128s + 30s jitter */ + ret = k_msgq_get(&uplink_msgq, &req, K_SECONDS(128 + 30 + 1)); + zassert_equal(ret, 0, "receiving AppTimeReq timed out"); + zassert_equal(req.len, 6); + zassert_equal(req.data[0], CMD_APP_TIME); + + device_time = sys_get_le32(req.data + 1); + token_req = req.data[5] & 0xF; + zassert_within((int)device_time, (int)(k_uptime_get() / 1000), 1); + + /* apply a time correction of 1000 seconds */ + sys_put_le32(1000, ans_data + 1); + ans_data[5] = token_req; + + lorawan_emul_send_downlink(CLOCK_SYNC_PORT, false, 0, 0, sizeof(ans_data), ans_data); + + lorawan_clock_sync_get(&gps_time); + zassert_within(gps_time, (k_uptime_get() / 1000) + 1000, 1); +} + +ZTEST(clock_sync, test_device_app_time_periodicity) +{ + const uint8_t period = 1; /* actual periodicity in seconds: 128 * 2^period */ + uint8_t req_data[] = { + CMD_DEVICE_APP_TIME_PERIODICITY, + period & 0xF, + }; + struct lorawan_msg app_time_req; + struct lorawan_msg ans; + uint32_t device_time; + uint32_t gps_time; + int ret; + + k_msgq_purge(&uplink_msgq); + + lorawan_emul_send_downlink(CLOCK_SYNC_PORT, false, 0, 0, sizeof(req_data), req_data); + + ret = k_msgq_get(&uplink_msgq, &ans, K_MSEC(100)); + zassert_equal(ret, 0, "receiving DeviceAppTimePeriodicityAns timed out"); + zassert_equal(ans.len, 6); + zassert_equal(ans.data[0], CMD_DEVICE_APP_TIME_PERIODICITY); + zassert_equal(ans.data[1], 0); + + device_time = sys_get_le32(ans.data + 2); + lorawan_clock_sync_get(&gps_time); + zassert_within(device_time, gps_time, 1); + + /* wait for more than the old periodicity of 128s + 30s jitter */ + ret = k_msgq_get(&uplink_msgq, &app_time_req, K_SECONDS(128 + 30 + 1)); + zassert_equal(ret, -EAGAIN, "received AppTimeReq too early"); + + /* wait for another 128s to cover the new periodicity of 256s + 30s jitter */ + ret = k_msgq_get(&uplink_msgq, &app_time_req, K_SECONDS(128)); + zassert_equal(ret, 0, "receiving AppTimeReq timed out"); + zassert_equal(app_time_req.len, 6); + zassert_equal(app_time_req.data[0], CMD_APP_TIME); + + /* reset to minimum periodicity */ + req_data[1] = 0; + lorawan_emul_send_downlink(CLOCK_SYNC_PORT, false, 0, 0, sizeof(req_data), req_data); + ret = k_msgq_get(&uplink_msgq, &ans, K_MSEC(100)); + zassert_equal(ret, 0, "receiving DeviceAppTimePeriodicityAns timed out"); + zassert_equal(ans.len, 6); + zassert_equal(ans.data[0], CMD_DEVICE_APP_TIME_PERIODICITY); +} + +ZTEST(clock_sync, test_force_device_resync) +{ + const uint8_t nb_transmissions = 2; + uint8_t resync_req_data[] = { + CMD_FORCE_DEVICE_RESYNC, + nb_transmissions, + }; + struct lorawan_msg app_time_req; + int ret; + + k_msgq_purge(&uplink_msgq); + + lorawan_emul_send_downlink(CLOCK_SYNC_PORT, false, 0, 0, sizeof(resync_req_data), + resync_req_data); + + for (int i = 0; i < nb_transmissions; i++) { + /* wait for more than CLOCK_RESYNC_DELAY of 10 secs */ + ret = k_msgq_get(&uplink_msgq, &app_time_req, K_SECONDS(11)); + zassert_equal(ret, 0, "receiving AppTimeReq #%d timed out", i + 1); + zassert_equal(app_time_req.len, 6); + zassert_equal(app_time_req.data[0], CMD_APP_TIME); + } +} + +static void *clock_sync_setup(void) +{ + const struct device *lora_dev = DEVICE_DT_GET(DT_ALIAS(lora0)); + struct lorawan_join_config join_cfg = {0}; + int ret; + + zassert_true(device_is_ready(lora_dev), "LoRa device not ready"); + + ret = lorawan_start(); + zassert_equal(ret, 0, "lorawan_start failed: %d", ret); + + ret = lorawan_join(&join_cfg); + zassert_equal(ret, 0, "lorawan_join failed: %d", ret); + + lorawan_emul_register_uplink_callback(uplink_handler); + + ret = lorawan_clock_sync_run(); + zassert_equal(ret, 0, "clock_sync_run failed: %d", ret); + + /* wait for first messages to be processed in the background */ + k_sleep(K_SECONDS(1)); + + return NULL; +} + +ZTEST_SUITE(clock_sync, NULL, clock_sync_setup, NULL, NULL, NULL); diff --git a/tests/subsys/lorawan/clock_sync/testcase.yaml b/tests/subsys/lorawan/clock_sync/testcase.yaml new file mode 100644 index 00000000000..8c1b8e9ed7b --- /dev/null +++ b/tests/subsys/lorawan/clock_sync/testcase.yaml @@ -0,0 +1,14 @@ +common: + tags: + - lorawan +tests: + lorawan.clock_sync.sim: + integration_platforms: + - native_sim + platform_allow: + - native_sim + lorawan.clock_sync.phy: + depends_on: lora + filter: CONFIG_ENTROPY_HAS_DRIVER + integration_platforms: + - nucleo_wl55jc From 9e9d18d945c8d457c1838b562b7de9720c70b0e7 Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Thu, 29 Feb 2024 11:10:19 -0500 Subject: [PATCH 0020/2402] doc: release: update eol for ltsv2 to 2025-01-26 Update the documentation page to reflect the latest LTSv2 release and tentative end-of-life (EOL) date. Note: the actual EOL date is still dependant on the official LTSv3 release date and may be subject to change. Signed-off-by: Christopher Friedt --- doc/releases/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/releases/index.rst b/doc/releases/index.rst index 6bb9fd225c7..544f721994b 100644 --- a/doc/releases/index.rst +++ b/doc/releases/index.rst @@ -56,7 +56,7 @@ Supported Releases +-----------------+----------------+---------------+ | Release | Release date | EOL | +=================+================+===============+ -| `Zephyr 2.7.5`_ | 2023-06-01 | 2024-08-31 | +| `Zephyr 2.7.6`_ | 2024-03-01 | 2025-01-26 | +-----------------+----------------+---------------+ | `Zephyr 3.6.0`_ | 2024-02-23 | 2024-11-29 | +-----------------+----------------+---------------+ @@ -112,6 +112,6 @@ in the migration guide. This includes: .. _`GitHub repository`: https://github.com/zephyrproject-rtos/zephyr .. _`GitHub tagged releases`: https://github.com/zephyrproject-rtos/zephyr/tags -.. _`Zephyr 2.7.5`: https://docs.zephyrproject.org/2.7.5/ +.. _`Zephyr 2.7.6`: https://docs.zephyrproject.org/2.7.6/ .. _`Zephyr 3.5.0`: https://docs.zephyrproject.org/3.5.0/ .. _`Zephyr 3.6.0`: https://docs.zephyrproject.org/3.6.0/ From b14f7d00ca50423d19bc7f0b3feddbcc82b6cd8f Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Fri, 1 Mar 2024 18:10:23 -0500 Subject: [PATCH 0021/2402] doc: lts: update conf.py to point at 2.7.6 (LTS) Point the configuration at 2.7.6 (LTS). Signed-off-by: Christopher Friedt --- doc/conf.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/conf.py b/doc/conf.py index a8da3477802..c9b8453a28b 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -189,7 +189,7 @@ ("latest", "/"), ("3.6.0", "/3.6.0/"), ("3.5.0", "/3.5.0/"), - ("2.7.5 (LTS)", "/2.7.5/"), + ("2.7.6 (LTS)", "/2.7.6/"), ), "display_gh_links": True, "reference_links": { From 1493271cf75653581fa8851da8f5c7a6fe560443 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Sat, 2 Mar 2024 10:59:01 +0900 Subject: [PATCH 0022/2402] ci: doc-publish: Publish API coverage docs only when available The API coverage documentation support was (relatively) recently introduced in bad87f1684e7fe8be11a39290d688d9585549184 and is not available in older release branches. Since doc-publish workflows always run in the default (main) branch context, it is necessary to make the API coverage documentation handling optional for the workflow runs that are triggered from older release branches. Signed-off-by: Stephanos Ioannidis --- .github/workflows/doc-publish-pr.yml | 12 ++++++++---- .github/workflows/doc-publish.yml | 8 ++++++-- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/.github/workflows/doc-publish-pr.yml b/.github/workflows/doc-publish-pr.yml index 07ee0c10604..de08d013bd1 100644 --- a/.github/workflows/doc-publish-pr.yml +++ b/.github/workflows/doc-publish-pr.yml @@ -46,7 +46,9 @@ jobs: - name: Uncompress HTML docs run: | tar xf html-output/html-output.tar.xz -C html-output - tar xf api-coverage/api-coverage.tar.xz -C api-coverage + if [ -f api-coverage/api-coverage.tar.xz ]; then + tar xf api-coverage/api-coverage.tar.xz -C api-coverage + fi - name: Configure AWS Credentials uses: aws-actions/configure-aws-credentials@v2 @@ -62,6 +64,8 @@ jobs: aws s3 sync --quiet html-output/html \ s3://builds.zephyrproject.org/${{ github.event.repository.name }}/pr/${PR_NUM}/docs \ --delete - aws s3 sync --quiet api-coverage/coverage-report/ \ - s3://builds.zephyrproject.org/${{ github.event.repository.name }}/pr/${PR_NUM}/api-coverage \ - --delete + if [ -d api-coverage/coverage-report ]; then + aws s3 sync --quiet api-coverage/coverage-report/ \ + s3://builds.zephyrproject.org/${{ github.event.repository.name }}/pr/${PR_NUM}/api-coverage \ + --delete + fi diff --git a/.github/workflows/doc-publish.yml b/.github/workflows/doc-publish.yml index c15313bb087..c250e6514aa 100644 --- a/.github/workflows/doc-publish.yml +++ b/.github/workflows/doc-publish.yml @@ -32,7 +32,9 @@ jobs: - name: Uncompress HTML docs run: | tar xf html-output/html-output.tar.xz -C html-output - tar xf api-coverage/api-coverage.tar.xz -C api-coverage + if [ -f api-coverage/api-coverage.tar.xz ]; then + tar xf api-coverage/api-coverage.tar.xz -C api-coverage + fi - name: Configure AWS Credentials uses: aws-actions/configure-aws-credentials@v2 @@ -53,5 +55,7 @@ jobs: aws s3 sync --quiet html-output/html s3://docs.zephyrproject.org/${VERSION} --delete aws s3 sync --quiet html-output/html/doxygen/html s3://docs.zephyrproject.org/apidoc/${VERSION} --delete - aws s3 sync --quiet api-coverage/coverage-report/ s3://docs.zephyrproject.org/api-coverage/${VERSION} --delete + if [ -d api-coverage/coverage-report ]; then + aws s3 sync --quiet api-coverage/coverage-report/ s3://docs.zephyrproject.org/api-coverage/${VERSION} --delete + fi aws s3 cp --quiet pdf-output/zephyr.pdf s3://docs.zephyrproject.org/${VERSION}/zephyr.pdf From d835772f38c701bd7f4e65cf493d9aad79867fa7 Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Fri, 1 Mar 2024 12:37:28 +0100 Subject: [PATCH 0023/2402] net: conn_mgr: set a thread name Set a thread name for net conn_mgr, so that e.g. thread listings within the shell are easier to look at. Signed-off-by: Florian La Roche --- subsys/net/conn_mgr/conn_mgr_monitor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/subsys/net/conn_mgr/conn_mgr_monitor.c b/subsys/net/conn_mgr/conn_mgr_monitor.c index 69c21f75b2c..0f8c9567b8c 100644 --- a/subsys/net/conn_mgr/conn_mgr_monitor.c +++ b/subsys/net/conn_mgr/conn_mgr_monitor.c @@ -338,6 +338,7 @@ static int conn_mgr_mon_init(void) CONFIG_NET_CONNECTION_MANAGER_MONITOR_STACK_SIZE, conn_mgr_mon_thread_fn, NULL, NULL, NULL, THREAD_PRIORITY, 0, K_NO_WAIT); + k_thread_name_set(&conn_mgr_mon_thread, "conn_mgr_monitor"); return 0; } From 0703a3532dd499b5200f553a2838884d28f3dc58 Mon Sep 17 00:00:00 2001 From: Andrzej Kuros Date: Wed, 28 Feb 2024 08:10:20 +0100 Subject: [PATCH 0024/2402] modules: hal_nordic: remove weak nrf_802154_clock_hfclk_ready MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The __WEAK-tagged function `nrf_802154_clock_hfclk_ready` is removed. The implementation is provided by the nRF 802.15.4 Radio Driver. Existence of __WEAK-tagged version causes incorrect behavior when Link Time Optimization is used. Signed-off-by: Andrzej Kuroś --- .../sl_opensource/platform/nrf_802154_clock_zephyr.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/modules/hal_nordic/nrf_802154/sl_opensource/platform/nrf_802154_clock_zephyr.c b/modules/hal_nordic/nrf_802154/sl_opensource/platform/nrf_802154_clock_zephyr.c index c9260bf278a..3a3d9501d0c 100644 --- a/modules/hal_nordic/nrf_802154/sl_opensource/platform/nrf_802154_clock_zephyr.c +++ b/modules/hal_nordic/nrf_802154/sl_opensource/platform/nrf_802154_clock_zephyr.c @@ -109,11 +109,6 @@ bool nrf_802154_clock_lfclk_is_running(void) return lfclk_is_running; } -__WEAK void nrf_802154_clock_hfclk_ready(void) -{ - /* Intentionally empty. */ -} - __WEAK void nrf_802154_clock_lfclk_ready(void) { /* Intentionally empty. */ From 955334708036b3ad6f794c427c0c125c356e8176 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Wed, 28 Feb 2024 14:51:47 +0100 Subject: [PATCH 0025/2402] Bluetooth: ISO: Add CONFIG_BT_ISO_{RX/TX} Add 2 new Kconfig promptless options that are shorthand for whether the ISO configuration can support RX and TX. This also applies these new options as guards for existing and missing code pieces. Signed-off-by: Emil Gydesen --- subsys/bluetooth/Kconfig | 2 +- subsys/bluetooth/Kconfig.iso | 10 +++++++ subsys/bluetooth/host/buf.c | 4 +-- subsys/bluetooth/host/conn.c | 4 +-- subsys/bluetooth/host/hci_core.c | 10 ++++--- subsys/bluetooth/host/iso.c | 16 +++++------ subsys/bluetooth/shell/iso.c | 46 +++++++++++++++++++------------- 7 files changed, 55 insertions(+), 37 deletions(-) diff --git a/subsys/bluetooth/Kconfig b/subsys/bluetooth/Kconfig index c8f71afb207..2bd29855e55 100644 --- a/subsys/bluetooth/Kconfig +++ b/subsys/bluetooth/Kconfig @@ -120,7 +120,7 @@ config BT_MAX_CONN config BT_CONN_TX bool - default BT_CONN || BT_ISO_BROADCASTER + default BT_CONN || BT_ISO_TX help Hidden configuration that is true if ACL or broadcast ISO is enabled diff --git a/subsys/bluetooth/Kconfig.iso b/subsys/bluetooth/Kconfig.iso index 0fc4be1401b..89955b70614 100644 --- a/subsys/bluetooth/Kconfig.iso +++ b/subsys/bluetooth/Kconfig.iso @@ -7,11 +7,19 @@ config BT_ISO bool +config BT_ISO_TX + bool + +config BT_ISO_RX + bool + # TODO: Split between client (central) and server (peripheral) config BT_ISO_UNICAST bool depends on BT_CONN select BT_ISO + select BT_ISO_TX + select BT_ISO_RX help This option enables support for Bluetooth Unicast Isochronous channels. @@ -45,6 +53,7 @@ config BT_ISO_BROADCASTER bool "Bluetooth Isochronous Broadcaster Support [EXPERIMENTAL]" depends on !BT_CTLR || BT_CTLR_ADV_ISO_SUPPORT select BT_ISO_BROADCAST + select BT_ISO_TX select BT_BROADCASTER select BT_PER_ADV select EXPERIMENTAL @@ -55,6 +64,7 @@ config BT_ISO_SYNC_RECEIVER bool "Bluetooth Isochronous Synchronized Receiver Support [EXPERIMENTAL]" depends on !BT_CTLR || BT_CTLR_SYNC_ISO_SUPPORT select BT_ISO_BROADCAST + select BT_ISO_RX select BT_OBSERVER select BT_PER_ADV_SYNC select EXPERIMENTAL diff --git a/subsys/bluetooth/host/buf.c b/subsys/bluetooth/host/buf.c index 9d87a6390e2..eeaacd49aae 100644 --- a/subsys/bluetooth/host/buf.c +++ b/subsys/bluetooth/host/buf.c @@ -62,9 +62,7 @@ struct net_buf *bt_buf_get_rx(enum bt_buf_type type, k_timeout_t timeout) __ASSERT(type == BT_BUF_EVT || type == BT_BUF_ACL_IN || type == BT_BUF_ISO_IN, "Invalid buffer type requested"); - if ((IS_ENABLED(CONFIG_BT_ISO_UNICAST) || - IS_ENABLED(CONFIG_BT_ISO_SYNC_RECEIVER)) && - type == BT_BUF_ISO_IN) { + if (IS_ENABLED(CONFIG_BT_ISO_RX) && type == BT_BUF_ISO_IN) { return bt_iso_get_rx(timeout); } diff --git a/subsys/bluetooth/host/conn.c b/subsys/bluetooth/host/conn.c index 176e5223242..88d9a8b6dff 100644 --- a/subsys/bluetooth/host/conn.c +++ b/subsys/bluetooth/host/conn.c @@ -403,9 +403,7 @@ void bt_conn_recv(struct bt_conn *conn, struct net_buf *buf, uint8_t flags) LOG_DBG("handle %u len %u flags %02x", conn->handle, buf->len, flags); - if ((IS_ENABLED(CONFIG_BT_ISO_UNICAST) || - IS_ENABLED(CONFIG_BT_ISO_SYNC_RECEIVER)) && - conn->type == BT_CONN_TYPE_ISO) { + if (IS_ENABLED(CONFIG_BT_ISO_RX) && conn->type == BT_CONN_TYPE_ISO) { bt_iso_recv(conn, buf, flags); return; } else if (IS_ENABLED(CONFIG_BT_CONN)) { diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c index 990e3472585..0c6a96e2aec 100644 --- a/subsys/bluetooth/host/hci_core.c +++ b/subsys/bluetooth/host/hci_core.c @@ -3266,10 +3266,14 @@ static int le_init_iso(void) net_buf_unref(rsp); } else if (IS_ENABLED(CONFIG_BT_CONN_TX)) { - LOG_WRN("Read Buffer Size V2 command is not supported. " - "No ISO TX buffers will be available"); + if (IS_ENABLED(CONFIG_BT_ISO_TX)) { + LOG_WRN("Read Buffer Size V2 command is not supported. " + "No ISO TX buffers will be available"); + } - /* Read LE Buffer Size */ + /* Read LE Buffer Size in the case that we support ACL without TX ISO (e.g. if we + * only support ISO sync receiver). + */ err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_READ_BUFFER_SIZE, NULL, &rsp); if (err) { diff --git a/subsys/bluetooth/host/iso.c b/subsys/bluetooth/host/iso.c index d8a563afd1e..f71625f22ac 100644 --- a/subsys/bluetooth/host/iso.c +++ b/subsys/bluetooth/host/iso.c @@ -34,14 +34,14 @@ LOG_MODULE_REGISTER(bt_iso); #define iso_chan(_iso) ((_iso)->iso.chan); -#if defined(CONFIG_BT_ISO_UNICAST) || defined(CONFIG_BT_ISO_SYNC_RECEIVER) +#if defined(CONFIG_BT_ISO_RX) NET_BUF_POOL_FIXED_DEFINE(iso_rx_pool, CONFIG_BT_ISO_RX_BUF_COUNT, BT_ISO_SDU_BUF_SIZE(CONFIG_BT_ISO_RX_MTU), sizeof(struct iso_data), NULL); static struct bt_iso_recv_info iso_info_data[CONFIG_BT_ISO_RX_BUF_COUNT]; #define iso_info(buf) (&iso_info_data[net_buf_id(buf)]) -#endif /* CONFIG_BT_ISO_UNICAST || CONFIG_BT_ISO_SYNC_RECEIVER */ +#endif /* CONFIG_BT_ISO_RX */ #if defined(CONFIG_BT_ISO_UNICAST) || defined(CONFIG_BT_ISO_BROADCAST) NET_BUF_POOL_FIXED_DEFINE(iso_tx_pool, CONFIG_BT_ISO_TX_BUF_COUNT, @@ -80,7 +80,7 @@ struct bt_iso_big bigs[CONFIG_BT_ISO_MAX_BIG]; static struct bt_iso_big *lookup_big_by_handle(uint8_t big_handle); #endif /* CONFIG_BT_ISO_BROADCAST */ -#if defined(CONFIG_BT_CONN_TX) +#if defined(CONFIG_BT_ISO_TX) static void bt_iso_send_cb(struct bt_conn *iso, void *user_data, int err) { struct bt_iso_chan *chan = iso->iso.chan; @@ -94,7 +94,7 @@ static void bt_iso_send_cb(struct bt_conn *iso, void *user_data, int err) ops->sent(chan); } } -#endif /* CONFIG_BT_CONN_TX */ +#endif /* CONFIG_BT_ISO_TX */ void hci_iso(struct net_buf *buf) { @@ -570,7 +570,7 @@ int bt_iso_chan_get_info(const struct bt_iso_chan *chan, return 0; } -#if defined(CONFIG_BT_ISO_UNICAST) || defined(CONFIG_BT_ISO_SYNC_RECEIVER) +#if defined(CONFIG_BT_ISO_RX) struct net_buf *bt_iso_get_rx(k_timeout_t timeout) { struct net_buf *buf = net_buf_alloc(&iso_rx_pool, timeout); @@ -727,9 +727,9 @@ void bt_iso_recv(struct bt_conn *iso, struct net_buf *buf, uint8_t flags) bt_conn_reset_rx_state(iso); } -#endif /* CONFIG_BT_ISO_UNICAST) || defined(CONFIG_BT_ISO_SYNC_RECEIVER */ +#endif /* CONFIG_BT_ISO_RX */ -#if defined(CONFIG_BT_CONN_TX) +#if defined(CONFIG_BT_ISO_TX) static uint16_t iso_chan_max_data_len(const struct bt_iso_chan *chan) { size_t max_controller_data_len; @@ -954,7 +954,7 @@ int bt_iso_chan_get_tx_sync(const struct bt_iso_chan *chan, struct bt_iso_tx_inf return 0; } -#endif /* CONFIG_BT_CONN_TX */ +#endif /* CONFIG_BT_ISO_TX */ #if defined(CONFIG_BT_ISO_UNICAST) int bt_iso_chan_disconnect(struct bt_iso_chan *chan) diff --git a/subsys/bluetooth/shell/iso.c b/subsys/bluetooth/shell/iso.c index 296e1374b22..625e8f5a316 100644 --- a/subsys/bluetooth/shell/iso.c +++ b/subsys/bluetooth/shell/iso.c @@ -24,8 +24,15 @@ #include "bt.h" +#if defined(CONFIG_BT_ISO_TX) +#define DEFAULT_IO_QOS \ + { \ + .sdu = 40u, .phy = BT_GAP_LE_PHY_2M, .rtn = 2u, \ + } + #define TX_BUF_TIMEOUT K_SECONDS(1) +static struct bt_iso_chan_io_qos iso_tx_qos = DEFAULT_IO_QOS; static uint32_t cis_sn_last; static uint32_t bis_sn_last; static int64_t cis_sn_last_updated_ticks; @@ -61,7 +68,9 @@ static uint32_t get_next_sn(uint32_t last_sn, int64_t *last_ticks, return (uint32_t)next_sn; } +#endif /* CONFIG_BT_ISO_TX */ +#if defined(CONFIG_BT_ISO_RX) static void iso_recv(struct bt_iso_chan *chan, const struct bt_iso_recv_info *info, struct net_buf *buf) { @@ -70,6 +79,7 @@ static void iso_recv(struct bt_iso_chan *chan, const struct bt_iso_recv_info *in chan, buf->len, info->seq_num, info->ts); } } +#endif /* CONFIG_BT_ISO_RX */ static void iso_connected(struct bt_iso_chan *chan) { @@ -85,6 +95,7 @@ static void iso_connected(struct bt_iso_chan *chan) return; } +#if defined(CONFIG_BT_ISO_TX) if (iso_info.type == BT_ISO_CHAN_TYPE_CONNECTED) { cis_sn_last = 0U; cis_sn_last_updated_ticks = k_uptime_ticks(); @@ -92,6 +103,7 @@ static void iso_connected(struct bt_iso_chan *chan) bis_sn_last = 0U; bis_sn_last_updated_ticks = k_uptime_ticks(); } +#endif /* CONFIG_BT_ISO_TX */ } static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason) @@ -101,20 +113,13 @@ static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason) } static struct bt_iso_chan_ops iso_ops = { - .recv = iso_recv, - .connected = iso_connected, - .disconnected = iso_disconnected, +#if defined(CONFIG_BT_ISO_RX) + .recv = iso_recv, +#endif /* CONFIG_BT_ISO_RX */ + .connected = iso_connected, + .disconnected = iso_disconnected, }; -#define DEFAULT_IO_QOS \ -{ \ - .sdu = 40u, \ - .phy = BT_GAP_LE_PHY_2M, \ - .rtn = 2u, \ -} - -static struct bt_iso_chan_io_qos iso_tx_qos = DEFAULT_IO_QOS; - #if defined(CONFIG_BT_ISO_UNICAST) static uint32_t cis_sdu_interval_us; @@ -934,7 +939,8 @@ static int cmd_big_term(const struct shell *sh, size_t argc, char *argv[]) SHELL_STATIC_SUBCMD_SET_CREATE(iso_cmds, #if defined(CONFIG_BT_ISO_UNICAST) #if defined(CONFIG_BT_ISO_CENTRAL) - SHELL_CMD_ARG(cig_create, NULL, "[dir=tx,rx,txrx] [C to P interval] [P to C interval] " + SHELL_CMD_ARG(cig_create, NULL, + "[dir=tx,rx,txrx] [C to P interval] [P to C interval] " "[packing] [framing] [C to P latency] [P to C latency] [sdu] [phy] [rtn]", cmd_cig_create, 1, 10), SHELL_CMD_ARG(cig_term, NULL, "Terminate the CIG", cmd_cig_term, 1, 0), @@ -951,10 +957,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE(iso_cmds, SHELL_CMD_ARG(listen, NULL, "", cmd_listen, 2, 0), #endif /* CONFIG_BT_SMP */ #endif /* CONFIG_BT_ISO_PERIPHERAL */ - SHELL_CMD_ARG(send, NULL, "Send to ISO Channel [count]", - cmd_send, 1, 1), - SHELL_CMD_ARG(disconnect, NULL, "Disconnect ISO Channel", - cmd_disconnect, 1, 0), +#if defined(CONFIG_BT_ISO_TX) + SHELL_CMD_ARG(send, NULL, "Send to ISO Channel [count]", cmd_send, 1, 1), +#endif /* CONFIG_BT_ISO_TX */ + SHELL_CMD_ARG(disconnect, NULL, "Disconnect ISO Channel", cmd_disconnect, 1, 0), SHELL_CMD_ARG(tx_sync_read_cis, NULL, "Read CIS TX sync info", cmd_tx_sync_read_cis, 1, 0), #endif /* CONFIG_BT_ISO_UNICAST */ #if defined(CONFIG_BT_ISO_BROADCASTER) @@ -964,8 +970,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE(iso_cmds, SHELL_CMD_ARG(tx_sync_read_bis, NULL, "Read BIS TX sync info", cmd_tx_sync_read_bis, 1, 0), #endif /* CONFIG_BT_ISO_BROADCASTER */ #if defined(CONFIG_BT_ISO_SYNC_RECEIVER) - SHELL_CMD_ARG(sync-big, NULL, "Synchronize to a BIG as a receiver [mse] " - "[timeout] [enc ]", cmd_big_sync, 2, 4), + SHELL_CMD_ARG(sync-big, NULL, + "Synchronize to a BIG as a receiver [mse] " + "[timeout] [enc ]", + cmd_big_sync, 2, 4), #endif /* CONFIG_BT_ISO_SYNC_RECEIVER */ #if defined(CONFIG_BT_ISO_BROADCAST) SHELL_CMD_ARG(term-big, NULL, "Terminate a BIG", cmd_big_term, 1, 0), From 46484da502d1d9680c46a50554eb3e121b9ea38b Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 26 Feb 2024 11:30:49 -0500 Subject: [PATCH 0026/2402] kernel: move priority queue handling to own file/header clean up headers under include/ and move handling of priority queue to own file/header. No need for the header include/zephyr/kernel/internal/sched_priq.h anymore. Move the relevant structures where they are being used in kernel_structs.h. Signed-off-by: Anas Nashif --- include/zephyr/kernel/internal/sched_priq.h | 60 -------- include/zephyr/kernel_includes.h | 1 - include/zephyr/kernel_structs.h | 44 +++++- kernel/CMakeLists.txt | 1 + kernel/include/priority_q.h | 87 +++++++++++ kernel/include/wait_q.h | 2 +- kernel/priority_queues.c | 109 +++++++++++++ kernel/sched.c | 162 +------------------- 8 files changed, 240 insertions(+), 226 deletions(-) delete mode 100644 include/zephyr/kernel/internal/sched_priq.h create mode 100644 kernel/include/priority_q.h create mode 100644 kernel/priority_queues.c diff --git a/include/zephyr/kernel/internal/sched_priq.h b/include/zephyr/kernel/internal/sched_priq.h deleted file mode 100644 index 62b0984b77f..00000000000 --- a/include/zephyr/kernel/internal/sched_priq.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2018 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef ZEPHYR_INCLUDE_SCHED_PRIQ_H_ -#define ZEPHYR_INCLUDE_SCHED_PRIQ_H_ - -#include -#include -#include - -/* Two abstractions are defined here for "thread priority queues". - * - * One is a "dumb" list implementation appropriate for systems with - * small numbers of threads and sensitive to code size. It is stored - * in sorted order, taking an O(N) cost every time a thread is added - * to the list. This corresponds to the way the original _wait_q_t - * abstraction worked and is very fast as long as the number of - * threads is small. - * - * The other is a balanced tree "fast" implementation with rather - * larger code size (due to the data structure itself, the code here - * is just stubs) and higher constant-factor performance overhead, but - * much better O(logN) scaling in the presence of large number of - * threads. - * - * Each can be used for either the wait_q or system ready queue, - * configurable at build time. - */ - -struct k_thread; - -struct k_thread *z_priq_dumb_best(sys_dlist_t *pq); -void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread); - -struct _priq_rb { - struct rbtree tree; - int next_order_key; -}; - -void z_priq_rb_add(struct _priq_rb *pq, struct k_thread *thread); -void z_priq_rb_remove(struct _priq_rb *pq, struct k_thread *thread); -struct k_thread *z_priq_rb_best(struct _priq_rb *pq); - -/* Traditional/textbook "multi-queue" structure. Separate lists for a - * small number (max 32 here) of fixed priorities. This corresponds - * to the original Zephyr scheduler. RAM requirements are - * comparatively high, but performance is very fast. Won't work with - * features like deadline scheduling which need large priority spaces - * to represent their requirements. - */ -struct _priq_mq { - sys_dlist_t queues[32]; - unsigned int bitmask; /* bit 1< #include #include -#include #include #include #include diff --git a/include/zephyr/kernel_structs.h b/include/zephyr/kernel_structs.h index 986165006eb..093fcd0a188 100644 --- a/include/zephyr/kernel_structs.h +++ b/include/zephyr/kernel_structs.h @@ -23,13 +23,13 @@ #if !defined(_ASMLANGUAGE) #include #include -#include #include #include #include #include #include #include +#include #endif #ifdef __cplusplus @@ -84,6 +84,43 @@ extern "C" { #if !defined(_ASMLANGUAGE) +/* Two abstractions are defined here for "thread priority queues". + * + * One is a "dumb" list implementation appropriate for systems with + * small numbers of threads and sensitive to code size. It is stored + * in sorted order, taking an O(N) cost every time a thread is added + * to the list. This corresponds to the way the original _wait_q_t + * abstraction worked and is very fast as long as the number of + * threads is small. + * + * The other is a balanced tree "fast" implementation with rather + * larger code size (due to the data structure itself, the code here + * is just stubs) and higher constant-factor performance overhead, but + * much better O(logN) scaling in the presence of large number of + * threads. + * + * Each can be used for either the wait_q or system ready queue, + * configurable at build time. + */ + +struct _priq_rb { + struct rbtree tree; + int next_order_key; +}; + + +/* Traditional/textbook "multi-queue" structure. Separate lists for a + * small number (max 32 here) of fixed priorities. This corresponds + * to the original Zephyr scheduler. RAM requirements are + * comparatively high, but performance is very fast. Won't work with + * features like deadline scheduling which need large priority spaces + * to represent their requirements. + */ +struct _priq_mq { + sys_dlist_t queues[32]; + unsigned int bitmask; /* bit 1<waitq) } -#endif +#endif /* CONFIG_WAITQ_SCALABLE */ /* kernel timeout record */ - struct _timeout; typedef void (*_timeout_func_t)(struct _timeout *t); diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt index cd9f39c9558..f519b545564 100644 --- a/kernel/CMakeLists.txt +++ b/kernel/CMakeLists.txt @@ -59,6 +59,7 @@ list(APPEND kernel_files mem_slab.c thread.c version.c + priority_queues.c sched.c ) diff --git a/kernel/include/priority_q.h b/kernel/include/priority_q.h new file mode 100644 index 00000000000..8c9a1a70836 --- /dev/null +++ b/kernel/include/priority_q.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_KERNEL_INCLUDE_PRIORITY_Q_H_ +#define ZEPHYR_KERNEL_INCLUDE_PRIORITY_Q_H_ + + +/* Dump Scheduling */ +#if defined(CONFIG_SCHED_DUMB) +#define _priq_run_add z_priq_dumb_add +#define _priq_run_remove z_priq_dumb_remove +# if defined(CONFIG_SCHED_CPU_MASK) +# define _priq_run_best _priq_dumb_mask_best +# else +# define _priq_run_best z_priq_dumb_best +# endif +/* Scalable Scheduling */ +#elif defined(CONFIG_SCHED_SCALABLE) +#define _priq_run_add z_priq_rb_add +#define _priq_run_remove z_priq_rb_remove +#define _priq_run_best z_priq_rb_best + /* Multi Queue Scheduling */ +#elif defined(CONFIG_SCHED_MULTIQ) +#define _priq_run_add z_priq_mq_add +#define _priq_run_remove z_priq_mq_remove +#define _priq_run_best z_priq_mq_best +static ALWAYS_INLINE void z_priq_mq_add(struct _priq_mq *pq, struct k_thread *thread); +static ALWAYS_INLINE void z_priq_mq_remove(struct _priq_mq *pq, struct k_thread *thread); +#endif + +/* Scalable Wait Queue */ +#if defined(CONFIG_WAITQ_SCALABLE) +#define z_priq_wait_add z_priq_rb_add +#define _priq_wait_remove z_priq_rb_remove +#define _priq_wait_best z_priq_rb_best +/* Dump Wait Queue */ +#elif defined(CONFIG_WAITQ_DUMB) +#define z_priq_wait_add z_priq_dumb_add +#define _priq_wait_remove z_priq_dumb_remove +#define _priq_wait_best z_priq_dumb_best +#endif + +/* Dumb Scheduling*/ +struct k_thread *z_priq_dumb_best(sys_dlist_t *pq); +void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread); + +/* Scalable Scheduling */ +void z_priq_rb_add(struct _priq_rb *pq, struct k_thread *thread); +void z_priq_rb_remove(struct _priq_rb *pq, struct k_thread *thread); + +/* Multi Queue Scheduling */ +struct k_thread *z_priq_mq_best(struct _priq_mq *pq); +struct k_thread *z_priq_rb_best(struct _priq_rb *pq); + + +bool z_priq_rb_lessthan(struct rbnode *a, struct rbnode *b); + + +#ifdef CONFIG_SCHED_MULTIQ +# if (K_LOWEST_THREAD_PRIO - K_HIGHEST_THREAD_PRIO) > 31 +# error Too many priorities for multiqueue scheduler (max 32) +# endif + +static ALWAYS_INLINE void z_priq_mq_add(struct _priq_mq *pq, + struct k_thread *thread) +{ + int priority_bit = thread->base.prio - K_HIGHEST_THREAD_PRIO; + + sys_dlist_append(&pq->queues[priority_bit], &thread->base.qnode_dlist); + pq->bitmask |= BIT(priority_bit); +} + +static ALWAYS_INLINE void z_priq_mq_remove(struct _priq_mq *pq, + struct k_thread *thread) +{ + int priority_bit = thread->base.prio - K_HIGHEST_THREAD_PRIO; + + sys_dlist_remove(&thread->base.qnode_dlist); + if (sys_dlist_is_empty(&pq->queues[priority_bit])) { + pq->bitmask &= ~BIT(priority_bit); + } +} +#endif /* CONFIG_SCHED_MULTIQ */ +#endif /* ZEPHYR_KERNEL_INCLUDE_PRIORITY_Q_H_ */ diff --git a/kernel/include/wait_q.h b/kernel/include/wait_q.h index 0c44a89eb66..2203a036ad2 100644 --- a/kernel/include/wait_q.h +++ b/kernel/include/wait_q.h @@ -12,8 +12,8 @@ #include #include #include -#include #include +#include #ifdef __cplusplus extern "C" { diff --git a/kernel/priority_queues.c b/kernel/priority_queues.c new file mode 100644 index 00000000000..5de9cdccf84 --- /dev/null +++ b/kernel/priority_queues.c @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2018,2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread) +{ + ARG_UNUSED(pq); + + __ASSERT_NO_MSG(!z_is_idle_thread_object(thread)); + + sys_dlist_remove(&thread->base.qnode_dlist); +} + +struct k_thread *z_priq_dumb_best(sys_dlist_t *pq) +{ + struct k_thread *thread = NULL; + sys_dnode_t *n = sys_dlist_peek_head(pq); + + if (n != NULL) { + thread = CONTAINER_OF(n, struct k_thread, base.qnode_dlist); + } + return thread; +} + +bool z_priq_rb_lessthan(struct rbnode *a, struct rbnode *b) +{ + struct k_thread *thread_a, *thread_b; + int32_t cmp; + + thread_a = CONTAINER_OF(a, struct k_thread, base.qnode_rb); + thread_b = CONTAINER_OF(b, struct k_thread, base.qnode_rb); + + cmp = z_sched_prio_cmp(thread_a, thread_b); + + if (cmp > 0) { + return true; + } else if (cmp < 0) { + return false; + } else { + return thread_a->base.order_key < thread_b->base.order_key + ? 1 : 0; + } +} + +void z_priq_rb_add(struct _priq_rb *pq, struct k_thread *thread) +{ + struct k_thread *t; + + __ASSERT_NO_MSG(!z_is_idle_thread_object(thread)); + + thread->base.order_key = pq->next_order_key++; + + /* Renumber at wraparound. This is tiny code, and in practice + * will almost never be hit on real systems. BUT on very + * long-running systems where a priq never completely empties + * AND that contains very large numbers of threads, it can be + * a latency glitch to loop over all the threads like this. + */ + if (!pq->next_order_key) { + RB_FOR_EACH_CONTAINER(&pq->tree, t, base.qnode_rb) { + t->base.order_key = pq->next_order_key++; + } + } + + rb_insert(&pq->tree, &thread->base.qnode_rb); +} + +void z_priq_rb_remove(struct _priq_rb *pq, struct k_thread *thread) +{ + __ASSERT_NO_MSG(!z_is_idle_thread_object(thread)); + + rb_remove(&pq->tree, &thread->base.qnode_rb); + + if (!pq->tree.root) { + pq->next_order_key = 0; + } +} + +struct k_thread *z_priq_rb_best(struct _priq_rb *pq) +{ + struct k_thread *thread = NULL; + struct rbnode *n = rb_get_min(&pq->tree); + + if (n != NULL) { + thread = CONTAINER_OF(n, struct k_thread, base.qnode_rb); + } + return thread; +} + +struct k_thread *z_priq_mq_best(struct _priq_mq *pq) +{ + if (!pq->bitmask) { + return NULL; + } + + struct k_thread *thread = NULL; + sys_dlist_t *l = &pq->queues[__builtin_ctz(pq->bitmask)]; + sys_dnode_t *n = sys_dlist_peek_head(l); + + if (n != NULL) { + thread = CONTAINER_OF(n, struct k_thread, base.qnode_dlist); + } + return thread; +} diff --git a/kernel/sched.c b/kernel/sched.c index 13a7b14b8c8..15d9b1d6164 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -6,8 +6,8 @@ #include #include #include -#include #include +#include #include #include #include @@ -22,38 +22,6 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); -#if defined(CONFIG_SCHED_DUMB) -#define _priq_run_add z_priq_dumb_add -#define _priq_run_remove z_priq_dumb_remove -# if defined(CONFIG_SCHED_CPU_MASK) -# define _priq_run_best _priq_dumb_mask_best -# else -# define _priq_run_best z_priq_dumb_best -# endif -#elif defined(CONFIG_SCHED_SCALABLE) -#define _priq_run_add z_priq_rb_add -#define _priq_run_remove z_priq_rb_remove -#define _priq_run_best z_priq_rb_best -#elif defined(CONFIG_SCHED_MULTIQ) -#define _priq_run_add z_priq_mq_add -#define _priq_run_remove z_priq_mq_remove -#define _priq_run_best z_priq_mq_best -static ALWAYS_INLINE void z_priq_mq_add(struct _priq_mq *pq, - struct k_thread *thread); -static ALWAYS_INLINE void z_priq_mq_remove(struct _priq_mq *pq, - struct k_thread *thread); -#endif - -#if defined(CONFIG_WAITQ_SCALABLE) -#define z_priq_wait_add z_priq_rb_add -#define _priq_wait_remove z_priq_rb_remove -#define _priq_wait_best z_priq_rb_best -#elif defined(CONFIG_WAITQ_DUMB) -#define z_priq_wait_add z_priq_dumb_add -#define _priq_wait_remove z_priq_dumb_remove -#define _priq_wait_best z_priq_dumb_best -#endif - struct k_spinlock sched_spinlock; static void update_cache(int preempt_ok); @@ -61,6 +29,7 @@ static void halt_thread(struct k_thread *thread, uint8_t new_state); static void add_to_waitq_locked(struct k_thread *thread, _wait_q_t *wait_q); + static inline int is_preempt(struct k_thread *thread) { /* explanation in kernel_struct.h */ @@ -1252,133 +1221,6 @@ void *z_get_next_switch_handle(void *interrupted) } #endif -void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread) -{ - ARG_UNUSED(pq); - - __ASSERT_NO_MSG(!z_is_idle_thread_object(thread)); - - sys_dlist_remove(&thread->base.qnode_dlist); -} - -struct k_thread *z_priq_dumb_best(sys_dlist_t *pq) -{ - struct k_thread *thread = NULL; - sys_dnode_t *n = sys_dlist_peek_head(pq); - - if (n != NULL) { - thread = CONTAINER_OF(n, struct k_thread, base.qnode_dlist); - } - return thread; -} - -bool z_priq_rb_lessthan(struct rbnode *a, struct rbnode *b) -{ - struct k_thread *thread_a, *thread_b; - int32_t cmp; - - thread_a = CONTAINER_OF(a, struct k_thread, base.qnode_rb); - thread_b = CONTAINER_OF(b, struct k_thread, base.qnode_rb); - - cmp = z_sched_prio_cmp(thread_a, thread_b); - - if (cmp > 0) { - return true; - } else if (cmp < 0) { - return false; - } else { - return thread_a->base.order_key < thread_b->base.order_key - ? 1 : 0; - } -} - -void z_priq_rb_add(struct _priq_rb *pq, struct k_thread *thread) -{ - struct k_thread *t; - - __ASSERT_NO_MSG(!z_is_idle_thread_object(thread)); - - thread->base.order_key = pq->next_order_key++; - - /* Renumber at wraparound. This is tiny code, and in practice - * will almost never be hit on real systems. BUT on very - * long-running systems where a priq never completely empties - * AND that contains very large numbers of threads, it can be - * a latency glitch to loop over all the threads like this. - */ - if (!pq->next_order_key) { - RB_FOR_EACH_CONTAINER(&pq->tree, t, base.qnode_rb) { - t->base.order_key = pq->next_order_key++; - } - } - - rb_insert(&pq->tree, &thread->base.qnode_rb); -} - -void z_priq_rb_remove(struct _priq_rb *pq, struct k_thread *thread) -{ - __ASSERT_NO_MSG(!z_is_idle_thread_object(thread)); - - rb_remove(&pq->tree, &thread->base.qnode_rb); - - if (!pq->tree.root) { - pq->next_order_key = 0; - } -} - -struct k_thread *z_priq_rb_best(struct _priq_rb *pq) -{ - struct k_thread *thread = NULL; - struct rbnode *n = rb_get_min(&pq->tree); - - if (n != NULL) { - thread = CONTAINER_OF(n, struct k_thread, base.qnode_rb); - } - return thread; -} - -#ifdef CONFIG_SCHED_MULTIQ -# if (K_LOWEST_THREAD_PRIO - K_HIGHEST_THREAD_PRIO) > 31 -# error Too many priorities for multiqueue scheduler (max 32) -# endif - -static ALWAYS_INLINE void z_priq_mq_add(struct _priq_mq *pq, - struct k_thread *thread) -{ - int priority_bit = thread->base.prio - K_HIGHEST_THREAD_PRIO; - - sys_dlist_append(&pq->queues[priority_bit], &thread->base.qnode_dlist); - pq->bitmask |= BIT(priority_bit); -} - -static ALWAYS_INLINE void z_priq_mq_remove(struct _priq_mq *pq, - struct k_thread *thread) -{ - int priority_bit = thread->base.prio - K_HIGHEST_THREAD_PRIO; - - sys_dlist_remove(&thread->base.qnode_dlist); - if (sys_dlist_is_empty(&pq->queues[priority_bit])) { - pq->bitmask &= ~BIT(priority_bit); - } -} -#endif - -struct k_thread *z_priq_mq_best(struct _priq_mq *pq) -{ - if (!pq->bitmask) { - return NULL; - } - - struct k_thread *thread = NULL; - sys_dlist_t *l = &pq->queues[__builtin_ctz(pq->bitmask)]; - sys_dnode_t *n = sys_dlist_peek_head(l); - - if (n != NULL) { - thread = CONTAINER_OF(n, struct k_thread, base.qnode_dlist); - } - return thread; -} - int z_unpend_all(_wait_q_t *wait_q) { int need_sched = 0; From 118f1592ff5d04cdcb35d779c3e93575cfad71ae Mon Sep 17 00:00:00 2001 From: Radoslaw Koppel Date: Tue, 27 Feb 2024 13:17:37 +0100 Subject: [PATCH 0027/2402] buildsystem: Enable LTO also for the application MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It turns out that currently LTO is enabled only for the kernel. This commit updates it to enable it for the whole application and adds additional LTO exclusions required for the standard C libraries to build and link properly. Signed-off-by: Radosław Koppel --- CMakeLists.txt | 2 +- lib/libc/newlib/CMakeLists.txt | 3 +++ lib/libc/picolibc/CMakeLists.txt | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index f1fb89660f9..a229c06413e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -214,7 +214,7 @@ endif() zephyr_compile_options(${OPTIMIZATION_FLAG}) if(CONFIG_LTO) - add_compile_options($) + zephyr_compile_options($) add_link_options($) endif() diff --git a/lib/libc/newlib/CMakeLists.txt b/lib/libc/newlib/CMakeLists.txt index 6556a3e814c..35c6a9b6337 100644 --- a/lib/libc/newlib/CMakeLists.txt +++ b/lib/libc/newlib/CMakeLists.txt @@ -3,6 +3,9 @@ zephyr_library() zephyr_library_sources(libc-hooks.c) +# Do not allow LTO when compiling libc-hooks.c file +set_source_files_properties(libc-hooks.c PROPERTIES COMPILE_OPTIONS $) + # Zephyr normally uses -ffreestanding, which with current GNU toolchains # means that the flag macros used by newlib 3.x to signal # support for PRI.64 macros are not present. To make them available we diff --git a/lib/libc/picolibc/CMakeLists.txt b/lib/libc/picolibc/CMakeLists.txt index 23e84231e2a..87fb0d9d8ec 100644 --- a/lib/libc/picolibc/CMakeLists.txt +++ b/lib/libc/picolibc/CMakeLists.txt @@ -3,6 +3,9 @@ zephyr_library() zephyr_library_sources(libc-hooks.c) +# Do not allow LTO when compiling libc-hooks.c file +set_source_files_properties(libc-hooks.c PROPERTIES COMPILE_OPTIONS $) + # define __LINUX_ERRNO_EXTENSIONS__ so we get errno defines like -ESHUTDOWN # used by the network stack zephyr_compile_definitions(__LINUX_ERRNO_EXTENSIONS__) From a57db0ddcb95ee6ddd0269c07359dfe333de91ce Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Wed, 14 Feb 2024 22:38:34 +0100 Subject: [PATCH 0028/2402] drivers: can: rework support for manual bus-off recovery Since all CAN controllers drivers seem to support automatic recovery (for any future drivers for hardware without this hardware capability this can easily be implemented in the driver), change the Zephyr CAN controller API policy to: - Always enable automatic bus recovery upon driver initialization, regardless of Kconfig options. Since CAN controllers are initialized in "stopped" state, no unwanted bus-off recovery will be started at this point. - Invert and rename the Kconfig CONFIG_CAN_AUTO_BUS_OFF_RECOVERY, which is enabled by default, to CONFIG_CAN_MANUAL_RECOVERY_MODE, which is disabled by default. Enabling CONFIG_CAN_MANUAL_RECOVERY_MODE=y enables support for the can_recover() API function and a new manual recovery mode (see next bullet). Keeping this guarded by Kconfig allows keeping the flash footprint down for applications not using manual bus-off recovery. - Introduce a new CAN controller operational mode CAN_MODE_MANUAL_RECOVERY. Support for this is only enabled if CONFIG_CAN_MANUAL_RECOVERY_MODE=y. Having this as a mode allows applications to inquire whether the CAN controller supports manual recovery mode via the can_get_capabilities() API function and either fail or rely on automatic recovery - and it allows CAN controller drivers not supporting manual recovery mode to fail early in can_set_mode() during application startup instead of failing when can_recover() is called at a later point in time. Signed-off-by: Henrik Brix Andersen --- doc/hardware/peripherals/can/shell.rst | 11 ++--- drivers/can/Kconfig | 17 +++---- drivers/can/can_esp32_twai.c | 4 +- drivers/can/can_fake.c | 4 +- drivers/can/can_handlers.c | 7 +-- drivers/can/can_kvaser_pci.c | 4 +- drivers/can/can_loopback.c | 18 ------- drivers/can/can_mcan.c | 37 ++++++++++----- drivers/can/can_mcp2515.c | 18 ------- drivers/can/can_mcp251xfd.c | 18 ------- drivers/can/can_mcux_flexcan.c | 39 +++++++++++---- drivers/can/can_mcux_mcan.c | 4 +- drivers/can/can_native_linux.c | 18 ------- drivers/can/can_numaker.c | 4 +- drivers/can/can_nxp_s32_canxl.c | 60 ++++++++++++++++-------- drivers/can/can_rcar.c | 37 +++++++++++---- drivers/can/can_sam.c | 4 +- drivers/can/can_sam0.c | 4 +- drivers/can/can_shell.c | 5 +- drivers/can/can_sja1000.c | 27 ++++++++--- drivers/can/can_stm32_bxcan.c | 38 +++++++++++---- drivers/can/can_stm32_fdcan.c | 4 +- drivers/can/can_stm32h7_fdcan.c | 4 +- drivers/can/can_tcan4x5x.c | 4 +- drivers/can/can_xmc4xxx.c | 18 ------- include/zephyr/drivers/can.h | 39 +++++++-------- include/zephyr/drivers/can/can_mcan.h | 4 +- include/zephyr/drivers/can/can_sja1000.h | 4 +- samples/drivers/can/counter/src/main.c | 10 ---- tests/drivers/build_all/can/prj.conf | 2 +- tests/drivers/can/api/prj.conf | 2 +- tests/drivers/can/api/src/classic.c | 57 ++++++++++++++++++++-- tests/drivers/can/shell/prj.conf | 2 +- tests/drivers/can/shell/src/main.c | 2 +- 34 files changed, 293 insertions(+), 237 deletions(-) diff --git a/doc/hardware/peripherals/can/shell.rst b/doc/hardware/peripherals/can/shell.rst index 5b161fde5d6..d10759ac302 100644 --- a/doc/hardware/peripherals/can/shell.rst +++ b/doc/hardware/peripherals/can/shell.rst @@ -33,8 +33,7 @@ The following :ref:`Kconfig ` options enable additional subcommands and * :kconfig:option:`CONFIG_CAN_STATS` enables printing of various statistics for the CAN controller in the ``can show`` subcommand. This depends on :kconfig:option:`CONFIG_STATS` being enabled as well. -* :kconfig:option:`CONFIG_CAN_AUTO_BUS_OFF_RECOVERY` enables the ``can recover`` subcommand when - disabled. +* :kconfig:option:`CONFIG_CAN_MANUAL_RECOVERY_MODE` enables the ``can recover`` subcommand. For example, building the :ref:`hello_world` sample for the :ref:`frdm_k64f` with the CAN shell and CAN statistics enabled: @@ -253,8 +252,8 @@ details on the supported arguments. Bus Recovery ************ -The ``can recover`` subcommand can be used for initiating recovery from a CAN bus-off event as shown -below: +The ``can recover`` subcommand can be used for initiating manual recovery from a CAN bus-off event +as shown below: .. code-block:: console @@ -265,5 +264,5 @@ The subcommand accepts an optional bus recovery timeout in milliseconds. If no t the command will wait indefinitely for the bus recovery to succeed. .. note:: - The ``recover`` subcommand is only available if - :kconfig:option:`CONFIG_CAN_AUTO_BUS_OFF_RECOVERY` is disabled. + The ``recover`` subcommand is only available if :kconfig:option:`CONFIG_CAN_MANUAL_RECOVERY_MODE` + is enabled. diff --git a/drivers/can/Kconfig b/drivers/can/Kconfig index 702676c09a3..4f929ba32f8 100644 --- a/drivers/can/Kconfig +++ b/drivers/can/Kconfig @@ -62,10 +62,16 @@ config CAN_ACCEPT_RTR level. config CAN_FD_MODE - bool "CAN FD" + bool "CAN FD support" help Enable CAN FD support. Not all CAN controllers support CAN FD. +config CAN_MANUAL_RECOVERY_MODE + bool "Manual bus-off recovery support" + help + Enable support for manual (non-automatic) recovery from bus-off state. Not all CAN + controllers support manual recovery mode. + config CAN_RX_TIMESTAMP bool "Receiving timestamps" help @@ -73,15 +79,6 @@ config CAN_RX_TIMESTAMP The value is incremented every bit time and starts when the controller is initialized. Not all CAN controllers support timestamps. -config CAN_AUTO_BUS_OFF_RECOVERY - bool "Automatic recovery from bus-off" - default y - help - This option enables the automatic bus-off recovery according to - ISO 11898-1 (recovery after 128 occurrences of 11 consecutive - recessive bits). When this option is enabled, the recovery API is not - available. - config CAN_QEMU_IFACE_NAME string "SocketCAN interface name for QEMU" default "" diff --git a/drivers/can/can_esp32_twai.c b/drivers/can/can_esp32_twai.c index 11c30a2338c..0f7eec51955 100644 --- a/drivers/can/can_esp32_twai.c +++ b/drivers/can/can_esp32_twai.c @@ -224,9 +224,9 @@ const struct can_driver_api can_esp32_twai_driver_api = { .set_state_change_callback = can_sja1000_set_state_change_callback, .get_core_clock = can_esp32_twai_get_core_clock, .get_max_filters = can_sja1000_get_max_filters, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_sja1000_recover, -#endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .timing_min = CAN_SJA1000_TIMING_MIN_INITIALIZER, #ifdef CONFIG_SOC_SERIES_ESP32 .timing_max = CAN_SJA1000_TIMING_MAX_INITIALIZER, diff --git a/drivers/can/can_fake.c b/drivers/can/can_fake.c index 097a614a35e..9da4ad80b23 100644 --- a/drivers/can/can_fake.c +++ b/drivers/can/can_fake.c @@ -103,9 +103,9 @@ static const struct can_driver_api fake_can_driver_api = { .add_rx_filter = fake_can_add_rx_filter, .remove_rx_filter = fake_can_remove_rx_filter, .get_state = fake_can_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = fake_can_recover, -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .set_state_change_callback = fake_can_set_state_change_callback, .get_core_clock = fake_can_get_core_clock, .get_max_filters = fake_can_get_max_filters, diff --git a/drivers/can/can_handlers.c b/drivers/can/can_handlers.c index aa0a62674cb..a5b728ca297 100644 --- a/drivers/can/can_handlers.c +++ b/drivers/can/can_handlers.c @@ -249,15 +249,16 @@ static inline int z_vrfy_can_get_state(const struct device *dev, enum can_state } #include -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE static inline int z_vrfy_can_recover(const struct device *dev, k_timeout_t timeout) { - K_OOPS(K_SYSCALL_DRIVER_CAN(dev, recover)); + /* Optional API function */ + K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_CAN)); return z_impl_can_recover(dev, timeout); } #include -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ #ifdef CONFIG_CAN_STATS diff --git a/drivers/can/can_kvaser_pci.c b/drivers/can/can_kvaser_pci.c index 909b29a0a34..a1490416076 100644 --- a/drivers/can/can_kvaser_pci.c +++ b/drivers/can/can_kvaser_pci.c @@ -143,9 +143,9 @@ const struct can_driver_api can_kvaser_pci_driver_api = { .set_state_change_callback = can_sja1000_set_state_change_callback, .get_core_clock = can_kvaser_pci_get_core_clock, .get_max_filters = can_sja1000_get_max_filters, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_sja1000_recover, -#endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .timing_min = CAN_SJA1000_TIMING_MIN_INITIALIZER, .timing_max = CAN_SJA1000_TIMING_MAX_INITIALIZER, }; diff --git a/drivers/can/can_loopback.c b/drivers/can/can_loopback.c index ffab53b315e..dcfb2a6cce8 100644 --- a/drivers/can/can_loopback.c +++ b/drivers/can/can_loopback.c @@ -340,21 +340,6 @@ static int can_loopback_get_state(const struct device *dev, enum can_state *stat return 0; } -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY -static int can_loopback_recover(const struct device *dev, k_timeout_t timeout) -{ - struct can_loopback_data *data = dev->data; - - ARG_UNUSED(timeout); - - if (!data->common.started) { - return -ENETDOWN; - } - - return 0; -} -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ - static void can_loopback_set_state_change_callback(const struct device *dev, can_state_change_callback_t cb, void *user_data) @@ -388,9 +373,6 @@ static const struct can_driver_api can_loopback_driver_api = { .add_rx_filter = can_loopback_add_rx_filter, .remove_rx_filter = can_loopback_remove_rx_filter, .get_state = can_loopback_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY - .recover = can_loopback_recover, -#endif .set_state_change_callback = can_loopback_set_state_change_callback, .get_core_clock = can_loopback_get_core_clock, .get_max_filters = can_loopback_get_max_filters, diff --git a/drivers/can/can_mcan.c b/drivers/can/can_mcan.c index df77962232c..2e33bda2d61 100644 --- a/drivers/can/can_mcan.c +++ b/drivers/can/can_mcan.c @@ -258,9 +258,13 @@ int can_mcan_get_capabilities(const struct device *dev, can_mode_t *cap) *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY; -#if CONFIG_CAN_FD_MODE - *cap |= CAN_MODE_FD; -#endif /* CONFIG_CAN_FD_MODE */ + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + *cap |= CAN_MODE_MANUAL_RECOVERY; + } + + if (IS_ENABLED(CONFIG_CAN_FD_MODE)) { + *cap |= CAN_MODE_FD; + } return 0; } @@ -350,22 +354,24 @@ int can_mcan_stop(const struct device *dev) int can_mcan_set_mode(const struct device *dev, can_mode_t mode) { + can_mode_t supported = CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY; struct can_mcan_data *data = dev->data; uint32_t cccr; uint32_t test; int err; -#ifdef CONFIG_CAN_FD_MODE - if ((mode & ~(CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_FD)) != 0U) { - LOG_ERR("unsupported mode: 0x%08x", mode); - return -ENOTSUP; + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + supported |= CAN_MODE_MANUAL_RECOVERY; } -#else /* CONFIG_CAN_FD_MODE */ - if ((mode & ~(CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY)) != 0U) { + + if (IS_ENABLED(CONFIG_CAN_FD_MODE)) { + supported |= CAN_MODE_FD; + } + + if ((mode & ~(supported)) != 0U) { LOG_ERR("unsupported mode: 0x%08x", mode); return -ENOTSUP; } -#endif /* !CONFIG_CAN_FD_MODE */ if (data->common.started) { return -EBUSY; @@ -462,7 +468,8 @@ static void can_mcan_state_change_handler(const struct device *dev) } } - if (IS_ENABLED(CONFIG_CAN_AUTO_BUS_OFF_RECOVERY)) { + if (!IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE) || + (data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) { /* * Request leaving init mode, but do not take the lock (as we are in ISR * context), nor wait for the result. @@ -847,7 +854,7 @@ int can_mcan_get_state(const struct device *dev, enum can_state *state, return 0; } -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE int can_mcan_recover(const struct device *dev, k_timeout_t timeout) { struct can_mcan_data *data = dev->data; @@ -856,9 +863,13 @@ int can_mcan_recover(const struct device *dev, k_timeout_t timeout) return -ENETDOWN; } + if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) { + return -ENOTSUP; + } + return can_mcan_leave_init_mode(dev, timeout); } -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ int can_mcan_send(const struct device *dev, const struct can_frame *frame, k_timeout_t timeout, can_tx_callback_t callback, void *user_data) diff --git a/drivers/can/can_mcp2515.c b/drivers/can/can_mcp2515.c index 13693f69c77..692015cdff3 100644 --- a/drivers/can/can_mcp2515.c +++ b/drivers/can/can_mcp2515.c @@ -789,21 +789,6 @@ static void mcp2515_handle_errors(const struct device *dev) } } -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY -static int mcp2515_recover(const struct device *dev, k_timeout_t timeout) -{ - struct mcp2515_data *dev_data = dev->data; - - ARG_UNUSED(timeout); - - if (!dev_data->common.started) { - return -ENETDOWN; - } - - return -ENOTSUP; -} -#endif - static void mcp2515_handle_interrupts(const struct device *dev) { const struct mcp2515_config *dev_cfg = dev->config; @@ -904,9 +889,6 @@ static const struct can_driver_api can_api_funcs = { .add_rx_filter = mcp2515_add_rx_filter, .remove_rx_filter = mcp2515_remove_rx_filter, .get_state = mcp2515_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY - .recover = mcp2515_recover, -#endif .set_state_change_callback = mcp2515_set_state_change_callback, .get_core_clock = mcp2515_get_core_clock, .get_max_filters = mcp2515_get_max_filters, diff --git a/drivers/can/can_mcp251xfd.c b/drivers/can/can_mcp251xfd.c index 97e16bf0652..04ee18bba2a 100644 --- a/drivers/can/can_mcp251xfd.c +++ b/drivers/can/can_mcp251xfd.c @@ -740,21 +740,6 @@ static int mcp251xfd_get_max_filters(const struct device *dev, bool ide) return CONFIG_CAN_MAX_FILTER; } -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY -static int mcp251xfd_recover(const struct device *dev, k_timeout_t timeout) -{ - struct mcp251xfd_data *dev_data = dev->data; - - ARG_UNUSED(timeout); - - if (!dev_data->common.started) { - return -ENETDOWN; - } - - return -ENOTSUP; -} -#endif - static int mcp251xfd_handle_fifo_read(const struct device *dev, const struct mcp251xfd_fifo *fifo, uint8_t fifo_type) { @@ -1646,9 +1631,6 @@ static const struct can_driver_api mcp251xfd_api_funcs = { .send = mcp251xfd_send, .add_rx_filter = mcp251xfd_add_rx_filter, .remove_rx_filter = mcp251xfd_remove_rx_filter, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY - .recover = mcp251xfd_recover, -#endif .get_state = mcp251xfd_get_state, .set_state_change_callback = mcp251xfd_set_state_change_callback, .get_core_clock = mcp251xfd_get_core_clock, diff --git a/drivers/can/can_mcux_flexcan.c b/drivers/can/can_mcux_flexcan.c index 6f41e6dbb8b..7a1e5dde4e3 100644 --- a/drivers/can/can_mcux_flexcan.c +++ b/drivers/can/can_mcux_flexcan.c @@ -177,6 +177,10 @@ static int mcux_flexcan_get_capabilities(const struct device *dev, can_mode_t *c *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_3_SAMPLES; + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + *cap |= CAN_MODE_MANUAL_RECOVERY; + } + if (UTIL_AND(IS_ENABLED(CONFIG_CAN_MCUX_FLEXCAN_FD), config->flexcan_fd)) { *cap |= CAN_MODE_FD; } @@ -388,6 +392,10 @@ static int mcux_flexcan_set_mode(const struct device *dev, can_mode_t mode) return -EBUSY; } + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + supported |= CAN_MODE_MANUAL_RECOVERY; + } + if (UTIL_AND(IS_ENABLED(CONFIG_CAN_MCUX_FLEXCAN_FD), config->flexcan_fd)) { supported |= CAN_MODE_FD; } @@ -431,6 +439,16 @@ static int mcux_flexcan_set_mode(const struct device *dev, can_mode_t mode) ctrl1 &= ~(CAN_CTRL1_SMP_MASK); } + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + if ((mode & CAN_MODE_MANUAL_RECOVERY) != 0) { + /* Disable auto-recovery from bus-off */ + ctrl1 |= CAN_CTRL1_BOFFREC_MASK; + } else { + /* Enable auto-recovery from bus-off */ + ctrl1 &= ~(CAN_CTRL1_BOFFREC_MASK); + } + } + #ifdef CONFIG_CAN_MCUX_FLEXCAN_FD if (config->flexcan_fd) { if ((mode & CAN_MODE_FD) != 0) { @@ -819,7 +837,7 @@ static void mcux_flexcan_set_state_change_callback(const struct device *dev, data->common.state_change_cb_user_data = user_data; } -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE static int mcux_flexcan_recover(const struct device *dev, k_timeout_t timeout) { const struct mcux_flexcan_config *config = dev->config; @@ -832,6 +850,10 @@ static int mcux_flexcan_recover(const struct device *dev, k_timeout_t timeout) return -ENETDOWN; } + if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) { + return -ENOTSUP; + } + (void)mcux_flexcan_get_state(dev, &state, NULL); if (state != CAN_STATE_BUS_OFF) { return 0; @@ -857,7 +879,7 @@ static int mcux_flexcan_recover(const struct device *dev, k_timeout_t timeout) return ret; } -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ static void mcux_flexcan_remove_rx_filter(const struct device *dev, int filter_id) { @@ -1225,9 +1247,8 @@ static int mcux_flexcan_init(const struct device *dev) config->irq_config_func(dev); -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY - config->base->CTRL1 |= CAN_CTRL1_BOFFREC_MASK; -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ + /* Enable auto-recovery from bus-off */ + config->base->CTRL1 &= ~(CAN_CTRL1_BOFFREC_MASK); (void)mcux_flexcan_get_state(dev, &data->state, NULL); @@ -1244,9 +1265,9 @@ __maybe_unused static const struct can_driver_api mcux_flexcan_driver_api = { .add_rx_filter = mcux_flexcan_add_rx_filter, .remove_rx_filter = mcux_flexcan_remove_rx_filter, .get_state = mcux_flexcan_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = mcux_flexcan_recover, -#endif +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .set_state_change_callback = mcux_flexcan_set_state_change_callback, .get_core_clock = mcux_flexcan_get_core_clock, .get_max_filters = mcux_flexcan_get_max_filters, @@ -1287,9 +1308,9 @@ static const struct can_driver_api mcux_flexcan_fd_driver_api = { .add_rx_filter = mcux_flexcan_add_rx_filter, .remove_rx_filter = mcux_flexcan_remove_rx_filter, .get_state = mcux_flexcan_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = mcux_flexcan_recover, -#endif +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .set_state_change_callback = mcux_flexcan_set_state_change_callback, .get_core_clock = mcux_flexcan_get_core_clock, .get_max_filters = mcux_flexcan_get_max_filters, diff --git a/drivers/can/can_mcux_mcan.c b/drivers/can/can_mcux_mcan.c index 28a709a023c..2ca5d3e0277 100644 --- a/drivers/can/can_mcux_mcan.c +++ b/drivers/can/can_mcux_mcan.c @@ -132,9 +132,9 @@ static const struct can_driver_api mcux_mcan_driver_api = { .send = can_mcan_send, .add_rx_filter = can_mcan_add_rx_filter, .remove_rx_filter = can_mcan_remove_rx_filter, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_mcan_recover, -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .get_state = can_mcan_get_state, .set_state_change_callback = can_mcan_set_state_change_callback, .get_core_clock = mcux_mcan_get_core_clock, diff --git a/drivers/can/can_native_linux.c b/drivers/can/can_native_linux.c index a2014fca0be..9356588a411 100644 --- a/drivers/can/can_native_linux.c +++ b/drivers/can/can_native_linux.c @@ -373,21 +373,6 @@ static int can_native_linux_get_state(const struct device *dev, enum can_state * return 0; } -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY -static int can_native_linux_recover(const struct device *dev, k_timeout_t timeout) -{ - struct can_native_linux_data *data = dev->data; - - ARG_UNUSED(timeout); - - if (!data->common.started) { - return -ENETDOWN; - } - - return 0; -} -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ - static void can_native_linux_set_state_change_callback(const struct device *dev, can_state_change_callback_t cb, void *user_data) @@ -422,9 +407,6 @@ static const struct can_driver_api can_native_linux_driver_api = { .add_rx_filter = can_native_linux_add_rx_filter, .remove_rx_filter = can_native_linux_remove_rx_filter, .get_state = can_native_linux_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY - .recover = can_native_linux_recover, -#endif .set_state_change_callback = can_native_linux_set_state_change_callback, .get_core_clock = can_native_linux_get_core_clock, .get_max_filters = can_native_linux_get_max_filters, diff --git a/drivers/can/can_numaker.c b/drivers/can/can_numaker.c index ba51b8b82fd..7580708052c 100644 --- a/drivers/can/can_numaker.c +++ b/drivers/can/can_numaker.c @@ -169,9 +169,9 @@ static const struct can_driver_api can_numaker_driver_api = { .send = can_mcan_send, .add_rx_filter = can_mcan_add_rx_filter, .remove_rx_filter = can_mcan_remove_rx_filter, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_mcan_recover, -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .get_state = can_mcan_get_state, .set_state_change_callback = can_mcan_set_state_change_callback, .get_core_clock = can_numaker_get_core_clock, diff --git a/drivers/can/can_nxp_s32_canxl.c b/drivers/can/can_nxp_s32_canxl.c index 50464ac7a6a..217d78981ca 100644 --- a/drivers/can/can_nxp_s32_canxl.c +++ b/drivers/can/can_nxp_s32_canxl.c @@ -123,9 +123,13 @@ static int can_nxp_s32_get_capabilities(const struct device *dev, can_mode_t *ca *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY; -#ifdef CAN_NXP_S32_FD_MODE - *cap |= CAN_MODE_FD; -#endif + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + *cap |= CAN_MODE_MANUAL_RECOVERY; + } + + if (IS_ENABLED(CAN_NXP_S32_FD_MODE)) { + *cap |= CAN_MODE_FD; + } return 0; } @@ -271,6 +275,7 @@ static int can_nxp_s32_stop(const struct device *dev) static int can_nxp_s32_set_mode(const struct device *dev, can_mode_t mode) { + can_mode_t supported = CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY; const struct can_nxp_s32_config *config = dev->config; struct can_nxp_s32_data *data = dev->data; Canexcel_Ip_ModesType can_nxp_s32_mode = CAN_MODE_NORMAL; @@ -280,11 +285,16 @@ static int can_nxp_s32_set_mode(const struct device *dev, can_mode_t mode) if (data->common.started) { return -EBUSY; } -#ifdef CAN_NXP_S32_FD_MODE - if ((mode & ~(CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_FD)) != 0) { -#else - if ((mode & ~(CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY)) != 0) { -#endif + + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + supported |= CAN_MODE_MANUAL_RECOVERY; + } + + if (IS_ENABLED(CAN_NXP_S32_FD_MODE)) { + supported |= CAN_MODE_FD; + } + + if ((mode & ~(supported)) != 0) { LOG_ERR("unsupported mode: 0x%08x", mode); return -ENOTSUP; } @@ -309,6 +319,20 @@ static int can_nxp_s32_set_mode(const struct device *dev, can_mode_t mode) CanXL_SetFDEnabled(config->base_sic, canfd, brs); + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + Canexcel_Ip_StatusType status; + uint32_t options = 0U; + + if ((mode & CAN_MODE_MANUAL_RECOVERY) == 0U) { + options = CANXL_IP_BUSOFF_RECOVERY_U32; + } + + status = CanXL_ConfigCtrlOptions(config->base_sic, options); + if (status != CANEXCEL_STATUS_SUCCESS) { + return -EIO; + } + } + CanXL_SetOperationMode(config->base_sic, can_nxp_s32_mode); Canexcel_Ip_ExitFreezeMode(config->instance); @@ -377,7 +401,7 @@ static void can_nxp_s32_set_state_change_callback(const struct device *dev, data->common.state_change_cb_user_data = user_data; } -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE static int can_nxp_s32_recover(const struct device *dev, k_timeout_t timeout) { const struct can_nxp_s32_config *config = dev->config; @@ -390,6 +414,10 @@ static int can_nxp_s32_recover(const struct device *dev, k_timeout_t timeout) return -ENETDOWN; } + if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) { + return -ENOTSUP; + } + can_nxp_s32_get_state(dev, &state, NULL); if (state != CAN_STATE_BUS_OFF) { return 0; @@ -415,7 +443,7 @@ static int can_nxp_s32_recover(const struct device *dev, k_timeout_t timeout) return ret; } -#endif +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ static void can_nxp_s32_remove_rx_filter(const struct device *dev, int filter_id) { @@ -1024,9 +1052,9 @@ static const struct can_driver_api can_nxp_s32_driver_api = { .add_rx_filter = can_nxp_s32_add_rx_filter, .remove_rx_filter = can_nxp_s32_remove_rx_filter, .get_state = can_nxp_s32_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_nxp_s32_recover, -#endif +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .set_state_change_callback = can_nxp_s32_set_state_change_callback, .get_core_clock = can_nxp_s32_get_core_clock, .get_max_filters = can_nxp_s32_get_max_filters, @@ -1102,12 +1130,6 @@ static const struct can_driver_api can_nxp_s32_driver_api = { #define CAN_NXP_S32_BRS 0 #endif -#ifdef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY -#define CAN_NXP_S32_CTRL_OPTIONS CANXL_IP_BUSOFF_RECOVERY_U32 -#else -#define CAN_NXP_S32_CTRL_OPTIONS 0 -#endif - #define CAN_NXP_S32_HW_INSTANCE_CHECK(i, n) \ ((DT_INST_REG_ADDR(n) == IP_CANXL_##i##__SIC_BASE) ? i : 0) @@ -1135,7 +1157,7 @@ static const struct can_driver_api can_nxp_s32_driver_api = { .CanxlMode = CANEXCEL_LISTEN_ONLY_MODE, \ .fd_enable = (boolean)IS_ENABLED(CAN_NXP_S32_FD_MODE), \ .bitRateSwitch = (boolean)CAN_NXP_S32_BRS, \ - .ctrlOptions = (uint32)CAN_NXP_S32_CTRL_OPTIONS, \ + .ctrlOptions = CANXL_IP_BUSOFF_RECOVERY_U32, \ .Callback = nxp_s32_can_##n##_ctrl_callback, \ .ErrorCallback = nxp_s32_can_##n##_err_callback, \ IF_ENABLED(CONFIG_CAN_NXP_S32_RX_FIFO, \ diff --git a/drivers/can/can_rcar.c b/drivers/can/can_rcar.c index 8ed931c4d10..b389b638a3b 100644 --- a/drivers/can/can_rcar.c +++ b/drivers/can/can_rcar.c @@ -653,12 +653,17 @@ static int can_rcar_stop(const struct device *dev) static int can_rcar_set_mode(const struct device *dev, can_mode_t mode) { + can_mode_t supported = CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY; const struct can_rcar_cfg *config = dev->config; struct can_rcar_data *data = dev->data; uint8_t tcr = 0; int ret = 0; - if ((mode & ~(CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY)) != 0) { + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + supported |= CAN_MODE_MANUAL_RECOVERY; + } + + if ((mode & ~(supported)) != 0) { LOG_ERR("Unsupported mode: 0x%08x", mode); return -ENOTSUP; } @@ -687,6 +692,20 @@ static int can_rcar_set_mode(const struct device *dev, can_mode_t mode) sys_write8(tcr, config->reg_addr + RCAR_CAN_TCR); + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + uint16_t ctlr = can_rcar_read16(config, RCAR_CAN_CTLR); + + if ((mode & CAN_MODE_MANUAL_RECOVERY) != 0U) { + /* Set entry to halt automatically at bus-off */ + ctlr |= RCAR_CAN_CTLR_BOM_ENT; + } else { + /* Clear entry to halt automatically at bus-off */ + ctlr &= ~RCAR_CAN_CTLR_BOM_ENT; + } + + can_rcar_write16(config, RCAR_CAN_CTLR, ctlr); + } + data->common.mode = mode; unlock: @@ -805,7 +824,7 @@ static int can_rcar_get_state(const struct device *dev, enum can_state *state, return 0; } -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE static int can_rcar_recover(const struct device *dev, k_timeout_t timeout) { const struct can_rcar_cfg *config = dev->config; @@ -817,6 +836,10 @@ static int can_rcar_recover(const struct device *dev, k_timeout_t timeout) return -ENETDOWN; } + if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) { + return -ENOTSUP; + } + if (data->state != CAN_STATE_BUS_OFF) { return 0; } @@ -843,7 +866,7 @@ static int can_rcar_recover(const struct device *dev, k_timeout_t timeout) k_mutex_unlock(&data->inst_mutex); return ret; } -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ static int can_rcar_send(const struct device *dev, const struct can_frame *frame, k_timeout_t timeout, can_tx_callback_t callback, @@ -1078,9 +1101,7 @@ static int can_rcar_init(const struct device *dev) ctlr = can_rcar_read16(config, RCAR_CAN_CTLR); ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY - ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically at bus-off */ -#endif + ctlr &= ~RCAR_CAN_CTLR_BOM_ENT; /* Clear entry to halt automatically at bus-off */ ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ ctlr &= ~RCAR_CAN_CTLR_SLPM; /* Clear CAN Sleep mode */ @@ -1142,9 +1163,9 @@ static const struct can_driver_api can_rcar_driver_api = { .add_rx_filter = can_rcar_add_rx_filter, .remove_rx_filter = can_rcar_remove_rx_filter, .get_state = can_rcar_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_rcar_recover, -#endif +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .set_state_change_callback = can_rcar_set_state_change_callback, .get_core_clock = can_rcar_get_core_clock, .get_max_filters = can_rcar_get_max_filters, diff --git a/drivers/can/can_sam.c b/drivers/can/can_sam.c index 4f0f32bce91..a77c189ba0a 100644 --- a/drivers/can/can_sam.c +++ b/drivers/can/can_sam.c @@ -126,9 +126,9 @@ static const struct can_driver_api can_sam_driver_api = { .add_rx_filter = can_mcan_add_rx_filter, .remove_rx_filter = can_mcan_remove_rx_filter, .get_state = can_mcan_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_mcan_recover, -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .get_core_clock = can_sam_get_core_clock, .get_max_filters = can_mcan_get_max_filters, .set_state_change_callback = can_mcan_set_state_change_callback, diff --git a/drivers/can/can_sam0.c b/drivers/can/can_sam0.c index 0a8bacda05c..adcbf6a567d 100644 --- a/drivers/can/can_sam0.c +++ b/drivers/can/can_sam0.c @@ -171,9 +171,9 @@ static const struct can_driver_api can_sam0_driver_api = { .add_rx_filter = can_mcan_add_rx_filter, .remove_rx_filter = can_mcan_remove_rx_filter, .get_state = can_mcan_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_mcan_recover, -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .get_core_clock = can_sam0_get_core_clock, .get_max_filters = can_mcan_get_max_filters, .set_state_change_callback = can_mcan_set_state_change_callback, diff --git a/drivers/can/can_shell.c b/drivers/can/can_shell.c index 3bb74f9552c..b6b64fe371e 100644 --- a/drivers/can/can_shell.c +++ b/drivers/can/can_shell.c @@ -35,6 +35,7 @@ static const struct can_shell_mode_mapping can_shell_mode_map[] = { CAN_SHELL_MODE_MAPPING("normal", CAN_MODE_NORMAL), CAN_SHELL_MODE_MAPPING("one-shot", CAN_MODE_ONE_SHOT), CAN_SHELL_MODE_MAPPING("triple-sampling", CAN_MODE_3_SAMPLES), + CAN_SHELL_MODE_MAPPING("manual-recovery", CAN_MODE_MANUAL_RECOVERY), }; K_MSGQ_DEFINE(can_shell_tx_msgq, sizeof(struct can_shell_tx_event), @@ -1054,9 +1055,9 @@ SHELL_STATIC_SUBCMD_SET_CREATE(sub_can_cmds, "CAN rx filter commands\n" "Usage: can filter ...", NULL), - SHELL_EXPR_CMD_ARG(!IS_ENABLED(CONFIG_CAN_AUTO_BUS_OFF_RECOVERY), + SHELL_COND_CMD_ARG(CONFIG_CAN_MANUAL_RECOVERY_MODE, recover, &dsub_can_device_name, - "Recover CAN controller from bus-off state\n" + "Manually recover CAN controller from bus-off state\n" "Usage: can recover [timeout ms]", cmd_can_recover, 2, 1), SHELL_SUBCMD_SET_END diff --git a/drivers/can/can_sja1000.c b/drivers/can/can_sja1000.c index 39d823d0137..b9cdc146822 100644 --- a/drivers/can/can_sja1000.c +++ b/drivers/can/can_sja1000.c @@ -141,6 +141,10 @@ int can_sja1000_get_capabilities(const struct device *dev, can_mode_t *cap) *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_ONE_SHOT | CAN_MODE_3_SAMPLES; + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + *cap |= CAN_MODE_MANUAL_RECOVERY; + } + return 0; } @@ -213,12 +217,17 @@ int can_sja1000_stop(const struct device *dev) int can_sja1000_set_mode(const struct device *dev, can_mode_t mode) { + can_mode_t supported = CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_ONE_SHOT | + CAN_MODE_3_SAMPLES; struct can_sja1000_data *data = dev->data; uint8_t btr1; uint8_t mod; - if ((mode & ~(CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_ONE_SHOT | - CAN_MODE_3_SAMPLES)) != 0) { + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + supported |= CAN_MODE_MANUAL_RECOVERY; + } + + if ((mode & ~(supported)) != 0) { LOG_ERR("unsupported mode: 0x%08x", mode); return -ENOTSUP; } @@ -464,7 +473,7 @@ void can_sja1000_remove_rx_filter(const struct device *dev, int filter_id) } } -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE int can_sja1000_recover(const struct device *dev, k_timeout_t timeout) { struct can_sja1000_data *data = dev->data; @@ -476,6 +485,10 @@ int can_sja1000_recover(const struct device *dev, k_timeout_t timeout) return -ENETDOWN; } + if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) { + return -ENOTSUP; + } + sr = can_sja1000_read_reg(dev, CAN_SJA1000_SR); if ((sr & CAN_SJA1000_SR_BS) == 0) { return 0; @@ -509,7 +522,7 @@ int can_sja1000_recover(const struct device *dev, k_timeout_t timeout) return 0; } -#endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ int can_sja1000_get_state(const struct device *dev, enum can_state *state, struct can_bus_err_cnt *err_cnt) @@ -659,11 +672,11 @@ static void can_sja1000_handle_error_warning_irq(const struct device *dev) if ((sr & CAN_SJA1000_SR_BS) != 0) { data->state = CAN_STATE_BUS_OFF; can_sja1000_tx_done(dev, -ENETUNREACH); -#ifdef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY - if (data->common.started) { + + if (data->common.started && + (data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) { can_sja1000_leave_reset_mode_nowait(dev); } -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ } else if ((sr & CAN_SJA1000_SR_ES) != 0) { data->state = CAN_STATE_ERROR_WARNING; } else { diff --git a/drivers/can/can_stm32_bxcan.c b/drivers/can/can_stm32_bxcan.c index 7d8de00d4e6..212d7622d9c 100644 --- a/drivers/can/can_stm32_bxcan.c +++ b/drivers/can/can_stm32_bxcan.c @@ -380,6 +380,10 @@ static int can_stm32_get_capabilities(const struct device *dev, can_mode_t *cap) *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_ONE_SHOT; + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + *cap |= CAN_MODE_MANUAL_RECOVERY; + } + return 0; } @@ -473,13 +477,18 @@ static int can_stm32_stop(const struct device *dev) static int can_stm32_set_mode(const struct device *dev, can_mode_t mode) { + can_mode_t supported = CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_ONE_SHOT; const struct can_stm32_config *cfg = dev->config; CAN_TypeDef *can = cfg->can; struct can_stm32_data *data = dev->data; LOG_DBG("Set mode %d", mode); - if ((mode & ~(CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_ONE_SHOT)) != 0) { + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + supported |= CAN_MODE_MANUAL_RECOVERY; + } + + if ((mode & ~(supported)) != 0) { LOG_ERR("unsupported mode: 0x%08x", mode); return -ENOTSUP; } @@ -511,6 +520,15 @@ static int can_stm32_set_mode(const struct device *dev, can_mode_t mode) can->MCR &= ~CAN_MCR_NART; } + if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) { + if ((mode & CAN_MODE_MANUAL_RECOVERY) != 0) { + /* No automatic recovery from bus-off */ + can->MCR &= ~CAN_MCR_ABOM; + } else { + can->MCR |= CAN_MCR_ABOM; + } + } + data->common.mode = mode; k_mutex_unlock(&data->inst_mutex); @@ -637,9 +655,10 @@ static int can_stm32_init(const struct device *dev) #ifdef CONFIG_CAN_RX_TIMESTAMP can->MCR |= CAN_MCR_TTCM; #endif -#ifdef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY + + /* Enable automatic bus-off recovery */ can->MCR |= CAN_MCR_ABOM; -#endif + ret = can_calc_timing(dev, &timing, cfg->common.bus_speed, cfg->common.sample_point); if (ret == -EINVAL) { @@ -686,7 +705,7 @@ static void can_stm32_set_state_change_callback(const struct device *dev, } } -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE static int can_stm32_recover(const struct device *dev, k_timeout_t timeout) { const struct can_stm32_config *cfg = dev->config; @@ -699,6 +718,10 @@ static int can_stm32_recover(const struct device *dev, k_timeout_t timeout) return -ENETDOWN; } + if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) { + return -ENOTSUP; + } + if (!(can->ESR & CAN_ESR_BOFF)) { return 0; } @@ -729,8 +752,7 @@ static int can_stm32_recover(const struct device *dev, k_timeout_t timeout) k_mutex_unlock(&data->inst_mutex); return ret; } -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ - +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ static int can_stm32_send(const struct device *dev, const struct can_frame *frame, k_timeout_t timeout, can_tx_callback_t callback, @@ -1053,9 +1075,9 @@ static const struct can_driver_api can_api_funcs = { .add_rx_filter = can_stm32_add_rx_filter, .remove_rx_filter = can_stm32_remove_rx_filter, .get_state = can_stm32_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_stm32_recover, -#endif +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .set_state_change_callback = can_stm32_set_state_change_callback, .get_core_clock = can_stm32_get_core_clock, .get_max_filters = can_stm32_get_max_filters, diff --git a/drivers/can/can_stm32_fdcan.c b/drivers/can/can_stm32_fdcan.c index fffd291778d..5eb3210eb31 100644 --- a/drivers/can/can_stm32_fdcan.c +++ b/drivers/can/can_stm32_fdcan.c @@ -586,9 +586,9 @@ static const struct can_driver_api can_stm32fd_driver_api = { .add_rx_filter = can_mcan_add_rx_filter, .remove_rx_filter = can_mcan_remove_rx_filter, .get_state = can_mcan_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_mcan_recover, -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .get_core_clock = can_stm32fd_get_core_clock, .get_max_filters = can_mcan_get_max_filters, .set_state_change_callback = can_mcan_set_state_change_callback, diff --git a/drivers/can/can_stm32h7_fdcan.c b/drivers/can/can_stm32h7_fdcan.c index e4965f32a92..4bf917a5ede 100644 --- a/drivers/can/can_stm32h7_fdcan.c +++ b/drivers/can/can_stm32h7_fdcan.c @@ -204,9 +204,9 @@ static const struct can_driver_api can_stm32h7_driver_api = { .add_rx_filter = can_mcan_add_rx_filter, .remove_rx_filter = can_mcan_remove_rx_filter, .get_state = can_mcan_get_state, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_mcan_recover, -#endif +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE*/ .get_core_clock = can_stm32h7_get_core_clock, .get_max_filters = can_mcan_get_max_filters, .set_state_change_callback = can_mcan_set_state_change_callback, diff --git a/drivers/can/can_tcan4x5x.c b/drivers/can/can_tcan4x5x.c index 8d8a1a612ad..a68ea5e22a4 100644 --- a/drivers/can/can_tcan4x5x.c +++ b/drivers/can/can_tcan4x5x.c @@ -722,9 +722,9 @@ static const struct can_driver_api tcan4x5x_driver_api = { .send = can_mcan_send, .add_rx_filter = can_mcan_add_rx_filter, .remove_rx_filter = can_mcan_remove_rx_filter, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE .recover = can_mcan_recover, -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ .get_state = can_mcan_get_state, .set_state_change_callback = can_mcan_set_state_change_callback, .get_core_clock = tcan4x5x_get_core_clock, diff --git a/drivers/can/can_xmc4xxx.c b/drivers/can/can_xmc4xxx.c index b2b96bf2b3c..3dc0bb9380c 100644 --- a/drivers/can/can_xmc4xxx.c +++ b/drivers/can/can_xmc4xxx.c @@ -514,21 +514,6 @@ static int can_xmc4xxx_get_max_filters(const struct device *dev, bool ide) return CONFIG_CAN_MAX_FILTER; } -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY -static int can_xmc4xxx_recover(const struct device *dev, k_timeout_t timeout) -{ - struct can_xmc4xxx_data *dev_data = dev->data; - - ARG_UNUSED(timeout); - - if (!dev_data->common.started) { - return -ENETDOWN; - } - - return -ENOTSUP; -} -#endif - static void can_xmc4xxx_reset_tx_fifos(const struct device *dev, int status) { struct can_xmc4xxx_data *dev_data = dev->data; @@ -908,9 +893,6 @@ static const struct can_driver_api can_xmc4xxx_api_funcs = { .send = can_xmc4xxx_send, .add_rx_filter = can_xmc4xxx_add_rx_filter, .remove_rx_filter = can_xmc4xxx_remove_rx_filter, -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY - .recover = can_xmc4xxx_recover, -#endif .get_state = can_xmc4xxx_get_state, .set_state_change_callback = can_xmc4xxx_set_state_change_callback, .get_core_clock = can_xmc4xxx_get_core_clock, diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index 59be684fd38..a4556baedf1 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -89,19 +89,22 @@ extern "C" { #define CAN_MODE_NORMAL 0 /** Controller is in loopback mode (receives own frames). */ -#define CAN_MODE_LOOPBACK BIT(0) +#define CAN_MODE_LOOPBACK BIT(0) /** Controller is not allowed to send dominant bits. */ -#define CAN_MODE_LISTENONLY BIT(1) +#define CAN_MODE_LISTENONLY BIT(1) /** Controller allows transmitting/receiving CAN FD frames. */ -#define CAN_MODE_FD BIT(2) +#define CAN_MODE_FD BIT(2) /** Controller does not retransmit in case of lost arbitration or missing ACK */ -#define CAN_MODE_ONE_SHOT BIT(3) +#define CAN_MODE_ONE_SHOT BIT(3) /** Controller uses triple sampling mode */ -#define CAN_MODE_3_SAMPLES BIT(4) +#define CAN_MODE_3_SAMPLES BIT(4) + +/** Controller requires manual recovery after entering bus-off state */ +#define CAN_MODE_MANUAL_RECOVERY BIT(5) /** @} */ @@ -450,7 +453,7 @@ typedef int (*can_add_rx_filter_t)(const struct device *dev, typedef void (*can_remove_rx_filter_t)(const struct device *dev, int filter_id); /** - * @brief Callback API upon recovering the CAN bus + * @brief Optional callback API upon manually recovering the CAN controller from bus-off state * See @a can_recover() for argument description */ typedef int (*can_recover_t)(const struct device *dev, k_timeout_t timeout); @@ -491,9 +494,9 @@ __subsystem struct can_driver_api { can_send_t send; can_add_rx_filter_t add_rx_filter; can_remove_rx_filter_t remove_rx_filter; -#if !defined(CONFIG_CAN_AUTO_BUS_OFF_RECOVERY) || defined(__DOXYGEN__) +#if defined(CONFIG_CAN_MANUAL_RECOVERY_MODE) || defined(__DOXYGEN__) can_recover_t recover; -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ can_get_state_t get_state; can_set_state_change_callback_t set_state_change_callback; can_get_core_clock_t get_core_clock; @@ -1413,34 +1416,32 @@ static inline int z_impl_can_get_state(const struct device *dev, enum can_state * * Recover the CAN controller from bus-off state to error-active state. * - * @note @kconfig{CONFIG_CAN_AUTO_BUS_OFF_RECOVERY} must be deselected for this + * @note @kconfig{CONFIG_CAN_MANUAL_RECOVERY_MODE} must be enabled for this * function to be available. * * @param dev Pointer to the device structure for the driver instance. * @param timeout Timeout for waiting for the recovery or ``K_FOREVER``. * * @retval 0 on success. + * @retval -ENOTSUP if the CAN controller is not in manual recovery mode. * @retval -ENETDOWN if the CAN controller is in stopped state. * @retval -EAGAIN on timeout. + * @retval -ENOSYS If this function is not implemented by the driver. */ -#if !defined(CONFIG_CAN_AUTO_BUS_OFF_RECOVERY) || defined(__DOXYGEN__) __syscall int can_recover(const struct device *dev, k_timeout_t timeout); +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE static inline int z_impl_can_recover(const struct device *dev, k_timeout_t timeout) { const struct can_driver_api *api = (const struct can_driver_api *)dev->api; + if (api->recover == NULL) { + return -ENOSYS; + } + return api->recover(dev, timeout); } -#else /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ -/* This implementation prevents inking errors for auto recovery */ -static inline int z_impl_can_recover(const struct device *dev, k_timeout_t timeout) -{ - ARG_UNUSED(dev); - ARG_UNUSED(timeout); - return 0; -} -#endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ /** * @brief Set a callback for CAN controller state change events diff --git a/include/zephyr/drivers/can/can_mcan.h b/include/zephyr/drivers/can/can_mcan.h index 4df3754a2af..ca7190412c2 100644 --- a/include/zephyr/drivers/can/can_mcan.h +++ b/include/zephyr/drivers/can/can_mcan.h @@ -1653,13 +1653,13 @@ int can_mcan_set_timing(const struct device *dev, const struct can_timing *timin */ int can_mcan_set_timing_data(const struct device *dev, const struct can_timing *timing_data); -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE /** * @brief Bosch M_CAN driver callback API upon recovering the CAN bus * See @a can_recover() for argument description */ int can_mcan_recover(const struct device *dev, k_timeout_t timeout); -#endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ int can_mcan_send(const struct device *dev, const struct can_frame *frame, k_timeout_t timeout, can_tx_callback_t callback, void *user_data); diff --git a/include/zephyr/drivers/can/can_sja1000.h b/include/zephyr/drivers/can/can_sja1000.h index b4a3c5e4da2..de11d69031d 100644 --- a/include/zephyr/drivers/can/can_sja1000.h +++ b/include/zephyr/drivers/can/can_sja1000.h @@ -227,13 +227,13 @@ int can_sja1000_add_rx_filter(const struct device *dev, can_rx_callback_t callba */ void can_sja1000_remove_rx_filter(const struct device *dev, int filter_id); -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY +#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE /** * @brief SJA1000 callback API upon recovering the CAN bus * See @a can_recover() for argument description */ int can_sja1000_recover(const struct device *dev, k_timeout_t timeout); -#endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ +#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */ /** * @brief SJA1000 callback API upon getting the CAN controller state diff --git a/samples/drivers/can/counter/src/main.c b/samples/drivers/can/counter/src/main.c index 2119069e43e..2fa0688eb58 100644 --- a/samples/drivers/can/counter/src/main.c +++ b/samples/drivers/can/counter/src/main.c @@ -173,16 +173,6 @@ void state_change_work_handler(struct k_work *work) "tx error count: %d\n", state_to_str(current_state), current_err_cnt.rx_err_cnt, current_err_cnt.tx_err_cnt); - -#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY - if (current_state == CAN_STATE_BUS_OFF) { - printf("Recover from bus-off\n"); - - if (can_recover(can_dev, K_MSEC(100)) != 0) { - printf("Recovery timed out\n"); - } - } -#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ } void state_change_callback(const struct device *dev, enum can_state state, diff --git a/tests/drivers/build_all/can/prj.conf b/tests/drivers/build_all/can/prj.conf index 4f651d30e26..5b33c40c8cc 100644 --- a/tests/drivers/build_all/can/prj.conf +++ b/tests/drivers/build_all/can/prj.conf @@ -3,4 +3,4 @@ CONFIG_TEST_USERSPACE=y CONFIG_GPIO=y CONFIG_CAN=y CONFIG_CAN_FD_MODE=y -CONFIG_CAN_AUTO_BUS_OFF_RECOVERY=n +CONFIG_CAN_MANUAL_RECOVERY_MODE=y diff --git a/tests/drivers/can/api/prj.conf b/tests/drivers/can/api/prj.conf index a163dc5077f..01dacc0dbab 100644 --- a/tests/drivers/can/api/prj.conf +++ b/tests/drivers/can/api/prj.conf @@ -1,6 +1,6 @@ CONFIG_CAN=y CONFIG_CAN_FD_MODE=y -CONFIG_CAN_AUTO_BUS_OFF_RECOVERY=n +CONFIG_CAN_MANUAL_RECOVERY_MODE=y CONFIG_STATS=y CONFIG_CAN_STATS=y CONFIG_TEST_USERSPACE=y diff --git a/tests/drivers/can/api/src/classic.c b/tests/drivers/can/api/src/classic.c index 4a871ebd9aa..b34bd7d98fc 100644 --- a/tests/drivers/can/api/src/classic.c +++ b/tests/drivers/can/api/src/classic.c @@ -853,18 +853,55 @@ ZTEST_USER(can_classic, test_send_fd_format) /** * @brief Test CAN controller bus recovery. + * + * It is not possible to provoke a bus off state, but verify the API call return codes. */ ZTEST_USER(can_classic, test_recover) { + can_mode_t cap; int err; - /* It is not possible to provoke a bus off state, but test the API call */ - err = can_recover(can_dev, TEST_RECOVER_TIMEOUT); - if (err == -ENOTSUP) { - ztest_test_skip(); + Z_TEST_SKIP_IFNDEF(CONFIG_CAN_MANUAL_RECOVERY_MODE); + + err = can_get_capabilities(can_dev, &cap); + zassert_equal(err, 0, "failed to get CAN capabilities (err %d)", err); + + if ((cap & CAN_MODE_MANUAL_RECOVERY) != 0U) { + /* Check that manual recovery fails when not in manual recovery mode */ + err = can_recover(can_dev, TEST_RECOVER_TIMEOUT); + zassert_equal(err, -ENOTSUP, "wrong error return code (err %d)", err); + + err = can_stop(can_dev); + zassert_equal(err, 0, "failed to stop CAN controller (err %d)", err); + + /* Enter manual recovery mode */ + err = can_set_mode(can_dev, CAN_MODE_NORMAL | CAN_MODE_MANUAL_RECOVERY); + zassert_equal(err, 0, "failed to set manual recovery mode (err %d)", err); + zassert_equal(CAN_MODE_NORMAL | CAN_MODE_MANUAL_RECOVERY, can_get_mode(can_dev)); + + err = can_start(can_dev); + zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); } - zassert_equal(err, 0, "failed to recover (err %d)", err); + err = can_recover(can_dev, TEST_RECOVER_TIMEOUT); + + if ((cap & CAN_MODE_MANUAL_RECOVERY) != 0U) { + zassert_equal(err, 0, "failed to recover (err %d)", err); + + err = can_stop(can_dev); + zassert_equal(err, 0, "failed to stop CAN controller (err %d)", err); + + /* Restore loopback mode */ + err = can_set_mode(can_dev, CAN_MODE_LOOPBACK); + zassert_equal(err, 0, "failed to set loopback-mode (err %d)", err); + zassert_equal(CAN_MODE_LOOPBACK, can_get_mode(can_dev)); + + err = can_start(can_dev); + zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); + } else { + /* Check that manual recovery fails when not supported */ + zassert_equal(err, -ENOSYS, "wrong error return code (err %d)", err); + } } /** @@ -1036,8 +1073,18 @@ ZTEST_USER(can_classic, test_start_while_started) */ ZTEST_USER(can_classic, test_recover_while_stopped) { + can_mode_t cap; int err; + Z_TEST_SKIP_IFNDEF(CONFIG_CAN_MANUAL_RECOVERY_MODE); + + err = can_get_capabilities(can_dev, &cap); + zassert_equal(err, 0, "failed to get CAN capabilities (err %d)", err); + + if ((cap & CAN_MODE_MANUAL_RECOVERY) == 0U) { + ztest_test_skip(); + } + err = can_stop(can_dev); zassert_equal(err, 0, "failed to stop CAN controller (err %d)", err); diff --git a/tests/drivers/can/shell/prj.conf b/tests/drivers/can/shell/prj.conf index 15c6eafdff7..0964517c154 100644 --- a/tests/drivers/can/shell/prj.conf +++ b/tests/drivers/can/shell/prj.conf @@ -2,7 +2,7 @@ CONFIG_SHELL=y CONFIG_SHELL_BACKEND_SERIAL=n CONFIG_SHELL_BACKEND_DUMMY=y CONFIG_CAN=y -CONFIG_CAN_AUTO_BUS_OFF_RECOVERY=n +CONFIG_CAN_MANUAL_RECOVERY_MODE=y CONFIG_CAN_FD_MODE=y CONFIG_CAN_SHELL=y CONFIG_ZTEST=y diff --git a/tests/drivers/can/shell/src/main.c b/tests/drivers/can/shell/src/main.c index bcd54bc36d7..227606fcb83 100644 --- a/tests/drivers/can/shell/src/main.c +++ b/tests/drivers/can/shell/src/main.c @@ -572,7 +572,7 @@ static void can_shell_test_recover(const char *cmd, k_timeout_t expected) const struct shell *sh = shell_backend_dummy_get_ptr(); int err; - Z_TEST_SKIP_IFDEF(CONFIG_CAN_AUTO_BUS_OFF_RECOVERY); + Z_TEST_SKIP_IFNDEF(CONFIG_CAN_MANUAL_RECOVERY_MODE); err = shell_execute_cmd(sh, cmd); zassert_ok(err, "failed to execute shell command (err %d)", err); From 418b0a1e6572eb31f5b80204b49593ec328040cc Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Wed, 28 Feb 2024 22:48:43 +0100 Subject: [PATCH 0029/2402] docs: release: migration-guide: 3.7: list CAN bus-off recovery changes List the changes to the CAN bus-off recovery functionality. Signed-off-by: Henrik Brix Andersen --- doc/releases/migration-guide-3.7.rst | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index f2867bf5a49..64763e03d7c 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -58,6 +58,24 @@ Controller Area Network (CAN) * ``phase-seg1-data`` * ``phase-seg1-data`` +* Support for manual bus-off recovery was reworked: + + * Automatic bus recovery will always be enabled upon driver initialization regardless of Kconfig + options. Since CAN controllers are initialized in "stopped" state, no unwanted bus-off recovery + will be started at this point. + * The Kconfig ``CONFIG_CAN_AUTO_BUS_OFF_RECOVERY`` was renamed (and inverted) to + :kconfig:option:`CONFIG_CAN_MANUAL_RECOVERY_MODE`, which is disabled by default. This Kconfig + option enables support for the :c:func:`can_recover()` API function and a new manual recovery mode + (see the next bullet). + * A new CAN controller operational mode :c:macro:`CAN_MODE_MANUAL_RECOVERY` was added. Support for + this is only enabled if :kconfig:option:`CONFIG_CAN_MANUAL_RECOVERY_MODE` is enabled. Having + this as a mode allows applications to inquire whether the CAN controller supports manual + recovery mode via the :c:func:`can_get_capabilities` API function. The application can then + either fail initialization or rely on automatic bus-off recovery. Having this as a mode + furthermore allows CAN controller drivers not supporting manual recovery mode to fail early in + :c:func:`can_set_mode` during application startup instead of failing when :c:func:`can_recover` + is called at a later point in time. + Display ======= From 8dc3f856229ce083c956aa301c31a23e65bd8cd8 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Wed, 14 Sep 2022 22:23:15 +0200 Subject: [PATCH 0030/2402] hwmv2: Introduce Hardware model version 2 and convert devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a squash of the ``collab-hwm`` branch which converts all in-tree boards to hardware model version 2 including build system changes, board updates and soc conversions. This squash is a combination of the following commits: ca214745a1 soc: Remove soc_legacy folder and move ARM Kconfig f12cb0979f scripts: ci: check_compliance: remove HWMv1 checks 1807bcf4d4 boards: mimx8mq_evk: port to HWMv2 3ec2299c62 soc: nxp: port imx8mq SOC to HWMv2 8ea02f4e63 boards: verdin_imx8mp: convert to HVMv2 f2eb7652ce boards: phyboard_pollux: move to HVMv2 ab509a5ee0 boards: nxp: mimx8mp_evk: port M7 core to HWMv2 06ad037f99 soc: nxp: imx8mp: port M7 core to HWMv2 3f9e706859 boards: mimx8mm_phyboard: convert to HVMv2 204372d264 boards: imx8mm_evk: port CM4 core to HWMv2 f82c961a46 soc: nxp: imx8mm: port iMX8MM M4 core to HVMv2 6987b2e305 boards: pico_pi: convert to HVMv2 84484e6707 boards: warp7: convert to HWMv2 ae443d1e3c boards: meerkat96: port to HWMv2 e3629c64e6 boards: colibri_imx7d: port to HWMv2 fc835d893d soc: nxp: convert iMX7 Dual core to HWMv2 29ef2f23eb boards: udoo_neo_full: convert to HWMv2 fd49b1749e soc: nxp: convert iMX6 SoloX core to HWMv2 1e59b7a3fd soc: nxp: imxrt11xx: only set CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION for M7 69bb0eb258 hwmv2: MAINTAINERS: Fix NXP maintainer yaml 1c4458890f boards: firefly: roc_rk3568_pc: Fix SMP configuration 651a4370ad boards: Fix variants and revisions 196cfda66d tests/samples: Drop default revision identifiers 6ec6b1d75a boards: Drop revision from twister identifiers for default revisions b774cdd59f scripts: utils: board_v1_to_v2: drop board_legacy prefix 7aa36e6640 boards: riscv: esp32c3_luatos_core: make usb variant fe25709a9c twister: add unit_testing soc and board f88f211b4e scripts: ci: check_compliance: improve the "not sorted" command b21a455dfb bluetooth: controller: Fix openisa checks fdc76c48a7 workflow: compliance: Add rename limit 14ecafc67d dts: bindings: vendor-prefixes: Sort entries dbc366c3c7 soc: nxp: lpc: Move wrong configurations 8e02c08f96 maintainers: Fix invalid paths b1b85e2495 boards: up: Fix spaces 58cc4013b3 maintainers: Fix xen path 66ce5c0b09 boards/soc: Add missing copyright headers bb47243254 boards: qemu: x86: Remove pointless file 2e816a8a3a samples: tests: update esp32-based board naming 9aeab17139 samples: tests: remove platform_exclude of esp32 boards a4fe97b9de boards: shields: m5stack_core2_ext: update board name 615fcab94a samples: ipm_esp32: fix board labels and skip testing 7752f69b7f boards: legacy: remove index entry for xtensa/riscv boards. 3eba827956 MAINTAINERS: update Espressif entries 914362bbd5 boards: xtensa: yd_esp32: Convert to v2 a62278fd23 boards: xtensa: xiao_esp32s3: Convert to v2 b6a11ccec4 boards: xtensa: olimex_esp32_evb: Convert to v2 c1067c16d2 boards: xtensa: odroid_go: Convert to v2 b8340b0109 boards: xtensa: m5stickc_plus: Convert to v2 9d81e417be boards: xtensa: m5stack_stamps3: Convert to v2 c296672720 boards: xtensa: m5stack_core2: Convert to v2 fada12aa9d boards: xtensa: m5stack_atoms3_lite: Convert to v2 fe37ebac1e boards: xtensa: m5stack_atoms3: Convert to v2 d32828fe6a boards: xtensa: kincony_kc868_a32: Convert to v2 5afba7855b boards: xtensa: heltec_wireless_stick_lite_v3: Convert to v2 ca48c17723 boards: xtensa: heltec_wifi_lora32_v2: Convert to v2 db1fd4d229 boards: xtensa: esp32s3_luatos_core: Convert to v2 a78b2552eb boards: xtensa: esp32s3_devkitm: Convert to v2 cc96061d96 boards: xtensa: esp32s2_saola: Convert to v2 ed854e05d1 boards: xtensa: esp32s2_lolin_mini: Convert to v2 4fa1ae8110 boards: xtensa: esp32s2_franzininho: Convert to v2 5543040a18 boards: xtensa: esp_wrover_kit: Convert to v2 2335ae79b3 boards: xtensa: esp32_ethernet_kit: Convert to v2 f910b7ad4f boards: xtensa: esp32_devkitc_wrover: Convert to v2 32104db555 boards: xtensa: esp32_devkitc_wroom: Convert to v2 e23a41200d boards: riscv: icev_wireless: Convert to v2 3c670e4e53 boards: riscv: xiao_esp32c3: Convert to v2 fc7c6a060b boards: riscv: stamp_c3: Convert to v2 22c2edb89c boards: riscv: esp32c3_luatos_core: Convert to v2 0a96dcb778 boards: riscv: esp32c3_devkitm: Convert to v2 be1ee1c446 vendors: update vendors lists 5e6c62137f soc: espressif_esp32: Port to HWMv2 037a3b52a4 boards: Raspberry Pi pico pwm led adjustment 7277cae6fa samples: blinky_pwm: enable pwm_leds in rpi_pico overlay da3e49d34e boards: nxp: update selection of FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET bc8424dd3b soc: nxp: imxrt: move FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET to SOC level 041cb52939 soc: brcm: bcm_vk: Rename to bcnvk 576b43a95c soc: Fix SOC_FAMILY name mismatches e8f3e6494d hwmv2: boards: intel: adsp: Fix runner after paths renamed 550399e927 boards: weact: stm32g431_core: Add wrongly deleted file back 08708c909e tests: drivers: flash: Renamed missed board rename 06dac41e68 hwmv2: Convert Seagate Faze board to hwmv2 dd8f842b40 hwmv2: nxp: update MAINTAINER paths for hwmv2 b4d1c04978 hwmv2: lpc: updated overlay and conf files in samples and tests 067c69089e boards: nxp: convert lpcxpresso55s69 to hwmv2 097205b40a hwmv2: Global fix of lpc54114_m4 overlay and conf files d8cfa6fb29 boards: nxp: convert lpcxpresso54114 to hwmv2 c29ed228c6 boards: nxp: convert lpcxpresso55s36 to hwmv2 88cfd3d6ac boards: nxp: convert lpcxpresso55s28 to hwmv2 ad30c940ee boards: nxp: convert lpcxpresso55s16 to hwmv2 9e5a10ec80 boards: nxp: convert lpcxpresso55s06 to hwmv2 5650c83268 boards: nxp: convert lpcxpresso51u68 to hwmv2 82cf44be45 boards: nxp: convert lpcxpresso11u68 to hwmv2 1a9c405a6f soc: nxp: convert LPC SOC family to hardware model V2 f2b536d253 boards: intel: doc: hwmv2: Fix some renamed paths 5ee6058710 samples/tests: Use board revisions b76687602f boards: Add yaml files for boards missing revisions 32ae4918d0 boards: nordic: Fix board names cc1dabca65 MAINTAINERS: Update for renamed folders a37ddce659 soc: xilinx: Rename to xlnx a1393a07f6 soc: xenvm: Rename to xen 813ed00f67 soc: raspberry_pi: Rename to raspberrypi 71317d6798 soc: cadence: Rename to cdns 8cb0c51ec6 soc: broadcom: Rename to brcm 2b9db15c69 soc: andes: Rename to andestech 0101216ce1 soc: altera: Rename to altr 4b4c3ca65d boards: wurth_elektronik: Rename to we cdc3ef499f boards: ublox: Rename to u-blox cabdd4ad05 boards: space_cubics: Rename to sc 4b5bd7ae8a boards: seeed_studio: Rename to seeed a992785ceb boards: raspberry_pi: Rename to raspberrypi 3c1cdc20fe boards: laird_connect: Rename to lairdconnect 291c7cde2b boards: cadence: Rename to cdns 95db897526 boards: broadcom: Rename to brcm 0a47b94879 boards: beagleboard: Change to beagle 9f9f221c24 boards: andes: Rename to andestech e7869ca38a boards: altera: Rename to altr bf2fb5eca3 various: Change SOC_FAMILY_NRF to SOC_FAMILY_NORDIC_NRF e25730ba56 modules: tf-m: Rename from nordic_nrf to nordic 9e3466606a boards: nordic_nrf: Rename to nordic 09a398dcc8 soc: nordic_nrf: Rename to nordic cb8ffc74f8 boards: renode: Add documentation index 2291ff4b55 boards: arm: riscv32_virtual: Convert to v2 484b7f1996 soc: riscv_renode_virtual: Port to HWMv2 cc5c2fb0c7 soc: raspberry_pi: Fix SOC_SERIES and SOC mismatch 59cb580513 soc: arm: designstart: Fix SOC_SERIES and SOC mismatch aa9e0de7af samples: Fix invalid links a1480cf1cf maintainers: Fix paths 0d719e004b boards: Update documentation links eb5c3e6f79 boards: wurth_elektronik: Drop duplicate prefix a34a3640b7 boards: waveshare: Drop duplicate prefix cf50e950e7 boards: weact: Drop duplicate prefix 737cfb548f boards: sparkfun: Drop duplicate prefix 505494c97a boards: segger: Drop duplicate prefix 4eaf69f37a boards: ruuvi: Drop duplicate prefix a1335caeae boards: ronoth: Drop duplicate prefix a9f7f30bf6 boards: raytac: Drop duplicate prefix 80db4c81b3 boards: qemu: Drop duplicate prefix 433d7e9976 boards: particle: Drop duplicate prefix 4ea79d19e7 boards: olimex: Drop duplicate prefix fd4ae6f6a8 boards: mikroe: Drop duplicate prefix 36080549bd boards: khados: Drop duplicate prefix 169bf8ae1d boards: intel: Drop duplicate prefix 25f04d5222 boards: holyiot: Drop duplicate prefix 11c2af0de8 boards: google: Drop duplicate prefix d5128f4016 boards: ebyte: Drop duplicate prefix 44fbc68cad boards: dragino: Drop duplicate prefix f7fe431b44 boards: contextual_electronics: Drop duplicate prefix 9094fea63b boards: circuit_dojo: Drop duplicate prefix b632acc1fc boards: blue_clover: Drop duplicate prefix 1a3316ebdc boards: bbc: Drop duplicate prefix 71c0344f8c boards: arduino: Drop duplicate prefix f0176fc25f boards: altera: Drop duplicate prefix 36b920ed0f boards: adi: Drop duplicate prefix 22520368d9 boards: adafruit: Drop duplicate prefix 296acfb2bc boards: actinius: Drop duplicate prefix 55063380b7 boards: 96boards: Drop duplicate prefix 1f93394b55 boards: nxp: convert mimxrt595_evk to hardware model v2 e7a4fd2ec1 soc: nxp: rt5xx: convert RT5xx SOC to HWMv2 01942f1d11 twister: normalize platform name when storing files/data 477c8b84dd twister: tests: test with slashes in platform names 64e3e816c4 soc: Add include guards 3a7aa2fa49 gitignore: update the compliance file list 84e1c17ad9 scripts: ci: check_compliance: add a check for board yml file a90f53ad57 boards: sync up the vendor tags and vendor-list af9aa65299 dts: vendor-prefixes: add keep-sorted markers 50f0bf05a3 dts: vendor-prefixes: sort the vendor list a10b614aa4 dts: vendor-prefixes: ensure all prefixes are lowercase 5abe735e93 manifest: update SOF sha for NXP HWMv2 9ab8f64ca9 modules: rename SOC_FAMILY_IMX 483ff8dd4d modules: mcux: remove SOC_FAMILY_NXP_ADSP f113dd5342 samples: update board name 39b31287d9 boards: nxp: Convert i.MX ADSP boards to hardware model v2 1511e356a2 soc: nxp: Port i.MX ADSP family to hardware model v2 c91e25ab47 soc: mec: rename all mec1501x reference to mec15xx 1c231fd939 hwmv2: boards: Convert IMXRT boards 417cff1e60 hwmv2: soc: Port IMXRT family to HWMV2 28d4e41b1b hwmv2: clean up arm64 soc and board empty directory 2b520f83cb hwmv2: port NXP SoC LS1046A to V2 bf7899c645 hwmv2: port nxp_ls1046ardb board to V2 33f7b61866 samples/tests: Rename numaker boards 8f20ea6e93 boards: nuvoton: numaker_pfm: Split into 2 boards 7cf4ff43a1 drivers: pinctrl: imx: align with hwm v2 c68e1fea4e drivers: clock_control: ccm_rev2: align with hwm v2 update 3b49014a0f hwmv2: move imx8mn EVK board to V2 14f344eeab hwmv2: move imx8mp EVK board to V2 40f3f8f22d hwmv2: move imx8mm EVK board to V2 10bf79ea51 hwmv2: move imx8m soc for a-core to V2 8727d5ca80 hwmv2: move imx93 EVK board to V2 c81ef01563 hwmv2: move imx93 soc to V2 5836c1b699 modules: mcux: introduce CONFIG_MCUX_CORE_SUFFIX 338f6f2bf1 doc: update board porting guide to match new hardware model 9639a1b5dc soc: silabs: drop useless defconfigs 981807444e soc: silabs: introduce SOC_GECKO_SDID 5d07e82485 soc: silabs: SOC_FAMILY_* replace SOC_GECKO_SERIES* 2fd081ac86 soc: silabs: align comments with soc tree 66d425f571 soc: silabs: split in families 5bd38f47a9 arch: arch: kconfig: Fix wrong placement of endmenu 00c6ef25be tests/samples: Rename overlay files for renamed boards 0c639b8378 boards: Fix bools and selections c2ef907d1d drivers: flash: it8xxx2: Add missing Kconfigs 553de2ebc9 soc: ite: ec: it8xxx2: Fix SOC_SERIES being in wrong file b8ec0080c2 boards: Documentation link fixes eb7025e50f tests: Update board names for hwmv2 10ef3d4bd2 boards: silab: Add documentation index file ba9fdaa1d6 boards: arm: efr32_radio: Convert to v2 86c8d4a0ca boards: arm: efm32pg_stk3402a: Convert to v2 575ac5cafb manifest: Update hal_silabs 87b2907304 boards: arm: efr32_thunderboard: Convert to v2 14b30055ab boards: arm: efr32mg_sltb004a: Convert to v2 0012bfc15d boards: arm: efr32xg24_dk2601b: Convert to v2 f526225ead boards: arm: efm32wg_stk3800: Convert to v2 19e7df29df boards: arm: efm32pg_stk3401a: Convert to v2 0bd7d963d6 boards: arm: efm32hg_slstk3400a: Convert to v2 795a90f9bf boards: arm: efm32gg_stk3701a: Convert to v2 43d5540be7 boards: arm: efm32gg_slwstk6121a: Convert to v2 065148d856 boards: arm: efm32gg_sltb009a: Convert to v2 1dc9a8aa17 soc: silabs_exx32: Port to HWMv2 763571e878 tests: Expand names dae301b8a3 boards: xen: xenvm: Expand name 19e60eef36 boards: qemu: qemu_cortex_a53: Expand names a0a7c30f28 soc: intel: intel_adsp: Fix issues df9a4223fe scripts: ci: introduce soc name check in check_compliance ed401abaff soc: emsdsp: align SoC name defined in soc.yml to Kconfig SOC setting fc78e5eaa4 MAINTAINERS: update RISC-V arch area paths 4e586958ff boards: convert QEMU RISC-V 64 bit board to Zephyr HWMv2 f4c31a2b86 boards: convert QEMU RV32E board to Zephyr HWMv2 5b2ffc652b boards: convert QEMU RISC-V 32 bit board to Zephyr HWMv2 5db061a4c6 soc/riscv: convert the QEMU virt RISCV-32 SoC to HWMv2 6547845e9d boards: convert SparkFun RED-V Things Plus to Zephyr HWMv2 95a1f96399 boards: convert SiFive HiFive Unmatched to Zephyr HWMv2 e563eb0a62 soc/sifive/sifive_freedom: add SiFive Freedom FU740 SoC 8914bc58b6 boards: convert SiFive HiFive Unleashed to Zephyr HWMv2 7e8de1e781 soc/sifive/sifive_freedom: add SiFive Freedom U540 SoC bfcc2ed18f boards: convert SiFive HiFive1 Rev. B to Zephyr HWMv2 330fc38f9f boards: convert SiFive HiFive1 to Zephyr HWMv2 b9e06f4c38 soc/sifive/sifive_freedom: add SiFive Freedom E310 SoC 4b90b30b9d scripts: west_commands: completion: Add hwmv2 complete to fish 0f6842e2fa scripts: west_commands: completion: Add hwmv2 complete to zsh b2af1e1737 scripts: west: list_boards: Fix hwmv2 output 686a4b78b8 scripts: west_commands: completion: Add hwmv2 complete to bash 396b6bb856 soc: nxp: fix typo in SoC name 765299c627 soc: broadcom: align SoC names defined in soc.yml to Kconfig SOC setting 7efd46eb41 soc: arm: align SoC names defined in soc.yml to Kconfig SOC setting 505cbc5c42 soc: mec: align SoC names defined in soc.yml to Kconfig SOC setting 951a140701 soc: ti: define SOC name in Kconfig a795d28810 snippets: Initial HWMv2 support f9a957e6f6 boards: nordic: nrf9160dk: Fix missing nrf52840 config df994e7ee8 soc: xilinx: zync7000: Remove xilinx from soc series name 8dfabd56ca soc: cypress: Add protection guard to file 447b951593 tests: kernel: tickless: Remove old board name bad5dfa71f boards: nordic: nrf5340dk: Fix board names ad2e863f39 soc: atmel: Use new family prefix 3f08e714b2 soc: intel_adsp: hwmv2: Align SOC_SERIES_INTEL_ACE name and value 6734597a76 soc: intel_adsp_cavs: hwmv2: Align SOC_SERIES name and value 2908af0bcc boards: nrf51dk/dongle: change SoC to nRF51822 d1ceb29fca soc: align CONFIG_SOC values to match soc.yml names 4768ccaf70 tests: drivers: gpio: gpio_api_1pin: exclude hifive1 ebdb0879ad boards: nxp: s32z2xxdc2: convert to hwmv2 ae82580d08 boards: nxp: mr_canhubk3: convert to hwmv2 c5f0defbae boards: nxp: ucans32k1sic: convert to hwmv2 1e46cabce6 soc: nxp: convert NXP S32 family to hwmv2 f2f85133f2 soc: stm32: Rename series path 86642f4e78 soc: stm32: Rename Kconfig SOC_SERIES symbols c61e807896 soc: stm32: Cleanup Kconfig.defconfig files ca46c8abc9 tests: Fix board names fbfed5f48f maintainers: Update synopsys entries 8cd8b1cc47 boards: synopsys: Add documentation index 6f6cc57a04 boards: arc: hsdk4xd: Convert to v2 c4c14a54ca soc: snps_arc_hsdk4xd: Port to HWMv2 06c2054e5c boards: arc: iotdk: Convert to v2 ff0e0fce1b soc: snps_arc_iot: Port to HWMv2 334264c46a boards: arc: emsdp: Convert to v2 8b947a0e91 soc: snps_emsdp: Port to HWMv2 990417bbde tests: Update board names for hwmv2 e12719154a boards: arc: em_starterkit: Convert to v2 437a430fbe soc: snps_emsk: Port to HWMv2 f93387f968 boards: arc: hsdk: Convert to v2 1cf2498b13 soc: snps_arc_hsdk: Port to HWMv2 47abe81256 boards: arc: nsim: Convert to v2 1e33786dc4 soc: snps_nsim: Port to HWMv2 7f081914db boards: arc: qemu_arc: Convert to v2 bc97349dbd soc: snps_qemu: Port to HWMv2 a9902ff58e boards: Use zephyr_file for file links 126e1a4e72 boards: Fix invalid documentation links 899f0257c3 boards: stm32wb: Restore missing .defconfig files 790c10b1ee soc: x86/atom: imply mmu, do not select it faee62088d boards: x86: remove qemu_x86_tiny_768 c34d186a57 x86: atom: remove soc.h with unused content 1be3a9e9d3 x86: remove legacy ia32, use atom instead 60e6b400f9 boards: qemu: move qemu_x86 -> x86 c4fbac27e8 boards: infineon: Add documentation index b4dd29a9c4 maintainers: Update paths for hwmv2 380f5fdb2b boards: cypress: Add documentation index 9de981be05 boards: arm: xmc47_relax_kit: Convert to v2 6394e8a348 boards: arm: xmc45_relax_kit: Convert to v2 04dbf17e19 soc: xmc_4xxx: Port to HWMv2 c9731f1bce boards: arm: cy8cproto_063_ble: Convert to v2 53d41869d1 boards: arm: cy8cproto_062_4343w: Convert to v2 46c4f01427 boards: arm: cy8ckit_062s4: Convert to v2 d285e19cf2 boards: arm: cy8ckit_062_wifi_bt: Convert to v2 2bebd7298c boards: arm: cy8ckit_062_ble: Convert to v2 af243274c2 soc: psoc6 and psoc_6: Port to HWMv2 105a2bae84 cmake: modules: boards: Fix board deprecation for HWMv2 dca54e000a cmake: modules: boards: Enhance board aliases for HWMv2 fc314e8e3f cmake: modules: boards: Fix BOARD_ALIAS 9a7c2ce6d5 soc: gaisler: Move Kconfig file 1ac56d0501 soc: soc_legacy: mips: Remove out file c054381a7a boards: adjust few boards/ paths 4d93b8d9fd boards: convert all microchip MEC boards to hwmv2 ab2fcb1245 soc: convert microchip_mec to hwmv2 ead4b57a7b soc: arm64: intel_socfpga: hwmv2: Rename SoCs d4c143d306 MAINTAINERS: intel_socfpga: Adjust to HWMv2 move 70a66ac03a boards: arm64: intel_socfpga: Move boards to subdirectories 8a85c07799 boards: arm64: intel_socfpga_agilex5_socdk: move to HWMv2 8c253a99fc boards: arm64: intel_socfpga_agilex_socdk: move to HWMv2 ab883b8019 soc: arm64: intel_socfpga: Move and convert to HWMv2 7c8b7a153b soc: arm: intel_socfpga_std: Rename with HWMv2 8dc2b911f6 soc: board: intel_socfpga_std: Align names to 'Cyclone V' 402366117a soc: arm: intel_socfpga_std: Align board subdirectory f0a8d12745 boards: arm: cyclonev_socdk: Move to HWMv2 2271f17a86 soc: arm: intel_socfpga_std: Move and convert to HWMv2 841c2a9d99 boards: riscv: beaglev_fire: Convert to v2 3b314531ab boards: riscv: mpfs_icicle: Convert to v2 d4ea2bf70b boards: riscv: m2gl025_miv: Convert to v2 5256e9fcc3 soc: microchip_miv: Port to HWMv2 18e5cf1d51 maintainers: Update path for hwmv2 eab8628f98 boards: arm: qemu_cortex_m3: Convert to v2 1532f2fee1 soc: ti_lm3s6965: Port to HWMv2 430ca6a475 maintainers: Update ambiq paths a9b9b41b91 boards: ambiq: Add index db0271ecbb boards: arm: apollo4p_blue_kxr_evb: Convert to v2 957e2b2061 boards: arm: apollo4p_evb: Convert to v2 5a90a44454 soc: ambiq: Port to HWMv2 a20c113fbd boards: nxp: convert ip_k66f to hwmv2 34e3852a54 boards: nxp: convert usb_kw24d512 to hwmv2 20ad604de6 boards: nxp: convert twr_kv58f220m to hwmv2 2e2a7b7656 boards: nxp: twr_ke18f: convert to hwmv2 f7dcc2eb5e boards: nxp: convert rddrone_fmuk66 to hwmv2 b58e90a2e9 boards: nxp: convert hexiwear to hwmv2 aae6e9e454 boards: nxp: frdm_kw41z: convert to hwmv2 1d3baac2d6 boards: nxp: convert frdm_kl25z to hwmv2 3b1d21483f boards: nxp: frdm_k82f: port to hwmv2 6046e6ded9 boards: nxp: port frdm_k64f to hwmv2 0a7bf9fd79 boards: nxp: port frdm_k22f to hwmv2 dce697c823 boards: nxp: add toctree placeholder 666a353409 soc: nxp: kinetis: convert kinetis SOC family to hardware model V2 89f0a6034b maintainers: Update paths for renesas boards/socs 004bd43c48 tests/samples/snippets: Update board names for hwmv2 a6d756923d boards: arm and arm64: rcar_h3ulcb: Convert to v2 3801216b8d boards: arm64: rcar_salvator_xs_m3: Convert to v2 b7cc30aaea boards: arm: rcar_h3_salvatorx_cr7: Convert to v2 866427ea29 boards: arm: arduino_uno_r4: Convert to v2 2689b3f0ee soc: ra: Port to HWMv2 e7ebc727c8 boards: arm: da1469x_dk_pro: Convert to v2 903265b2bb boards: arm: da14695_dk_usb: Convert to v2 529a78ed51 soc: smartbond: Port to HWMv2 97cf636ae0 boards: arm: rcar_spider_cr52: Convert to v2 6d0c53f3a1 soc: rcar: Port to HWMv2 44e0aa0668 soc: renesas: rzt2m: Move folder structure for more SoCs 85238fc205 boards: misc: Fixed STM32 based boards doc links dffc08af56 boards: riscv: niosv_m: move and convert to HWMv2 545093abe4 boards: riscv: niosv_g: move and convert to HWMv2 ecfa192f1b soc: riscv: intel_niosv: move and convert to HWMv2 fd1e8cdc30 hwmv2: sof: intel_adsp: submanifest provisional link 8bf067e625 doc: boards: intel_adsp: Re-order pages 4833275ccd MAINTAINERS: intel_adsp: Adjust to HWMv2 move b9a70e5ea2 soc: intel_adsp: tools: pylint compliance workaround 18c70cc4bf hwmv2: tests: boards: intel_adsp: Adjust board names ca52baf9de hwmv2: boards: intel_adsp: Overhaul board configurations d1b3bcce64 soc: boards: xtensa: intel_adsp_ace: Rename with HWMv2 f362a8ae2c doc: soc: boards: intel_adsp_cavs25: Rename with HWMv2 51dee5da92 tests: samples: boards: intel_adsp_cavs25: Rename with HWMv2 e66c35e0d0 boards: xtensa: intel_adsp_cavs25: Rename board with HWMv2 d1491a4810 soc: boards: xtensa: intel_adsp_cavs25: Rename with HWMv2 fa0fca79c4 scripts: west: runners: intel_adsp: Adjust path to HWMv2 acd18bfaf7 boards: xtensa: intel_adsp_ace20_lnl: move and convert to HWMv2 546c94b958 boards: xtensa: intel_adsp_ace15_mtpm: move and convert to HWMv2 8aab718c3e boards: xtensa: intel_adsp_cavs25_tgph: change to board variant 30f17424a4 boards: xtensa: intel_adsp_cavs25: move and convert to HWMv2 35a97cb524 soc: xtensa: intel_adsp: HWMv2 workaround for SOF config fdc20fdff6 soc: xtensa: intel_adsp: move and convert to HWMv2 22dc2b6391 cmake: improved board handling for revisions 2f1e33a2e6 cmake: improve arch error message for invalid arch selection c47c37d3db sample: basic: blinky_pwm: Exclude rpi_pico w variant 7a788b9a18 boards: raspberry_pi: rpi_pico: Use full name for w variant 7046b92d41 tests: atmel_sam: adc: Fix sam4e_xpro adc build 253ee9638c tests: atmel_sam0: Update platform name ccb4c63324 samples: atmel_sam0: Update platform name 2d4acf9230 boards: arduino_nano_33_iot: Convert to HWMv2 a60d28969a boards: arduino_mkrzero: Convert to HWMv2 0409e51d3f boards: arduino_zero: Convert to HWMv2 1b2528df1b boards: wio_terminal: Convert to HWMv2 af1096e7ca boards: ev11l78a: Convert to HWMv2 0b1db9c53d boards: adafruit_trinket_m0: Convert to HWMv2 e9874671e2 boards: adafruit_itsybitsy_m4_express: Convert to HWMv2 ba6c014071 boards: adafruit_grand_central_m4_express: Convert to HWMv2 33ad4a51ca boards: adafruit_feather_m0_lora: Convert to HWMv2 9812f3d54e boards: adafruit_feather_m0_basic_proto: Convert to HWMv2 c76b1fbeca boards: serpente: Convert to HWMv2 649789e433 boards: seeeduino_xiao: Convert to HWMv2 6b3bdb7364 boards: same54_xpro: Convert to HWMv2 93dda5ee4b boards: samr34_xpro: Convert to HWMv2 e48e1f5d5b boards: samc21n_xpro: Convert to HWMv2 f11cf73df1 boards: saml21_xpro: Convert to HWMv2 ac73ed6dcd boards: samd20_xpro: Convert to HWMv2 0fdbe3552e boards: samd21_xpro: Convert to HWMv2 854cff3905 boards: samr21_xpro: Convert to HWMv2 a87ea5bc0a soc: atmel: sam0: Port to HWMv2 706e5d27cd boards: riscv: neorv32: Convert to v2 d1edcdd088 soc: neorv32: Port to HWMv2 0f7add89ca boards: native_sim/posix: Add 64bit versions as variants b6edad8d68 soc: soc_legacy: remove the arm/st_stm32 folder c58e0822a6 boards: Convert nucleo_f207zg to HWM v2 b987093a80 soc: v2: stm32: Migrate STM32F2 series 2096fd4652 samples: bluetooth: hci_uart: Fix wrongly converted board names 830f9c5a82 MAINTAINERS: Update Atmel entries 527cd9d8cd CODEOWNERS: Update Atmel entries 83af7d0c1c samples: atmel_sam: Update platform name fd9b84d457 tests: atmel_sam: Update platform name 3c72fe863c boards: arduino_due: Convert to HWMv2 37dfacbf9e boards: RoboKit1: Convert to HWMv2 1108d7b0ed boards: sam_v71_xult: Convert to HWMv2 bed44a5c28 boards: sam_e70_xplained: Convert to HWMv2 40448c5a9f boards: sam4s_xplained: Convert to HWMv2 31273692c0 boards: sam4l_ek: Convert to HWMv2 35b5d33ef0 boards: sam4e_xpro: Convert to HWMv2 3b84b9910a soc: atmel: Port SAM family to HWMv2 da00d0e7b9 boards: Convert nucleo_wba55cg to HWM v2 fb2103f89e boards: Convert nucleo_wba52cg to HWM v2 1f9a533fbc soc: st: stm32: Migrate STM32WBA series 3f92f65b28 boards: fix documentation for alientek and blues boards 7646b74aaf boards: stm32l4: doc: add zephyr_file to defconfig path fea54ddcd9 boards: Convert adi_eval_adin2111ebz to HWM v2 d47f1878b1 boards: Convert adi_eval_adin1110ebz to HWM v2 ae42be236b boards: Convert swan_r5 to HWM v2 83bd1a9ecc boards: Convert stm32l4r9i_disco to HWM v2 39c26f09ed boards: Convert stm32l496g_disco to HWM v2 29d03c970b boards: Convert stm32l476g_disco to HWM v2 74acec315c boards: Convert sensortile_box to HWM v2 fee6d8676e boards: Convert pandora_stm32l475 to HWM v2 008b5d9392 boards: Convert nucleo_l4r5zi to HWM v2 24e357d623 boards: Convert nucleo_l4a6zg to HWM v2 2c5f9dcce0 boards: Convert nucleo_l496zg to HWM v2 4da061646f boards: Convert nucleo_l476rg to HWM v2 15956a69b8 tests: drivers: flash: stm32: update platform name 80324f7707 boards: Convert nucleo_l452re_p to HWM v2 9893e0d111 boards: Convert nucleo_l452re to HWM v2 46f92b227b boards: Convert nucleo_l433rc_p to HWM v2 ed5d1bb4cd boards: Convert nucleo_l432kc to HWM v2 325f95ec20 boards: Convert nucleo_l412rb_p to HWM v2 d055676307 boards: Convert disco_l475_iot1 to HWM v2 c7a415d92c boards: Convert b_l4s5i_iot01a to HWM v2 d15144f582 soc: st: stm32: Migrate STM32L4 series a63ff71bcb boards: nrf_bsim: Add new nrf5340 board definitions b53c6f412c boards: nrf_bsim: Remove redundant option setting 83eb4fc069 MAINTAINERS: intel_ish: Adjust to HWMv2 move 715685b19f boards: x86: intel_ish: move and convert intel_ish boards to HWMv2 5b9ef94106 soc: x86: intel_ish: move and convert to HWMv2 12b297707a boards: Convert stm32wb5mmg to HWM v2 cdcea932bc boards: Convert stm32wb5mm_dk to HWM v2 0a3ae2b223 boards: Convert nucleo_wb55rg to HWM v2 20b4ce17d5 soc: st: stm32: Migrate STM32WB series 47c65400d6 soc: st: stm32: fix stm32l0 family 59ec56f9e6 boards: Convert stm32h573i_dk to HWM v2 dc5977dbba boards: Convert nucleo_h563zi to HWM v2 a6e4928543 soc: st: stm32: Migrate STM32H5 series 99f248e048 soc: stm32u5: Fix references after conversion to hw modelv2 15f16834e6 boards: Convert stm32u5a9j_dk to HWM v2 c1ee449ef1 boards: Convert sensortile_box_pro to HWM v2 db4deddf9d boards: Convert nucleo_u5a5zj_q to HWM v2 2fd3ed43d2 boards: Convert nucleo_u575zi_q to HWM v2 902fceb173 boards: Convert b_u585i_iot02a to HWM v2 d716ca1a10 soc: st: Migrate stm32u5 series to new hw model b7abc89428 hwmv2: boards: x86: doc: Adjust common docs to new locations 69b334f54b MAINTAINERS: Change paths to native and nrf*bsim boards 614611a528 boards: nrf*_bsim: Convert to HW model v2 5821b9ec2e board: native_sim/posix: Convert to hwmv2 04cbad174e soc: native: Convert to HWMv2 24ca0febfc boards: nrf_bsim: Fix path to pinctrl_soc.h 9a32559a2d cmake: FindHostTools: Fix for hwmv2 for host based targets c4b11e0251 boards: longan_nano: port to HWMv2 97edd05be3 boards: gd32vf103c_starter: port to HWMv2 9cf624c410 boards: gd32vf103v_eval: port to HWMv2 b40bf25e5e soc: gd_gd32: reorganize folders 71600d7e95 soc: gd_gd32: move pinctrl_soc.h content back to soc folder 2bd84a1bc5 soc: gd_gd32: port gd32vf103 series to HWMv2 9dc342143b boards: doc: fix a bunch of broken reference 10392d693d doc: boards: split out shields b2def8ed3a boards: acrn: fix title bf7d3efe78 boards: riscv: tlsr9518adk80d: Convert to v2 c579770e1d soc: telink_tlsr: Port to HWMv2 9131540109 soc: stm32h7: Couple of tests fixes following migration 2efcefc089 boards: Convert stm32h7b3i_dk to HWM v2 d9b295a85b boards: Convert stm32h750b_dk to HWM v2 a2f56bdcd5 boards: Convert stm32h747i_disco to HWM v2 00314155df boards: Convert stm32h735g_disco to HWM v2 b08819dff7 boards: Convert nucleo_h7a3zi_q to HWM v2 56456c16e5 boards: Convert nucleo_h753zi to HWM v2 91f9198dc4 boards: Convert nucleo_h745zi_q to HWM v2 96f1bafbf9 boards: Convert nucleo_h743zi to HWM v2 b290f25baa boards: Convert nucleo_h723zg to HWM v2 9fbe6bf191 boards: Convert fk7b0m1_vbt6 to HWM v2 44bcfe57c7 boards: Convert arduino_portenta_h7 to HWM v2 4c86af7eae boards: Convert arduino_opta_m4 to HWM v2 b4f852f738 boards: Convert arduino_giga_r1 to HWM v2 bac9789264 soc: st: Migrate stm32h7 series to new hw model a954e1722d boards: stm32l0: Cleanup board _defconfig files after migration 7e8515b241 boards: Convert ronoth_lodev to HWM v2 25246c21ef boards: Convert nucleo_l073rz to HWM v2 09396eb2e6 boards: Convert nucleo_l053r8 to HWM v2 70c004fd83 boards: Convert nucleo_l031k6 to HWM v2 e3daa98e79 boards: Convert nucleo_l011k4 to HWM v2 a2de60c6da boards: Convert dragino_nbsn95 to HWM v2 e877ce9cec boards: Convert dragino_lsn50 to HWM v2 2b50218c23 boards: Convert b_l072z_lrwan1 to HWM v2 4a65f55916 soc: st: Migrate stm32l0 series to new hw model cc6e6be01f boards: fix few leftover ITE board references a837303268 soc: stm32: Protect Kconfig symbols by SOC_FAMILY_STM32 88e5959f17 hwm2: Fix unit_testing: it is also a legacy board by now 95e06e8663 cmake: Fix uses of old SOC path d517d3cc24 soc: set linker script for ra4m1 68f9aeddab soc: ite: add SOC_SERIES_ITE_IT8XXX2 guards around ITE options ccf4f48f01 boards: convert ite boards to hwmv2 4a6e286a3b soc: convert ite_ec to hwmv2 12e375f826 doc: handle arch / soc / board docs in new hardware model b4db917de9 boards: Add documentation index files d6e0d27efe samples: bluetooth: hci_uart: Fix wrong named files bc16a7a727 tests: Update board names for hwmv2 2834883843 boards: riscv: rv32m1_vega: Convert to v2 9c68231ba9 soc: openisa_rv32m1: Port to HWMv2 986e9619fd soc: starfive_jh71xx: Port to HWMv2 e82932e787 boards: riscv: litex_vexriscv: Convert to v2 cb9339f88f soc: litex_vexriscv: Port to HWMv2 1cd4c34654 boards: riscv: opentitan_earlgrey: Convert to v2 92eadf06b8 soc: opentitan: Port to HWMv2 a8659e170b boards: riscv: titanium_ti60_f225: Convert to v2 359133d725 soc: efinix_sapphire: Port to HWMv2 6d466429ed soc: soc_legacy: riscv: litex_vexriscv: Add updated paths a1ff441eb3 boards: riscv: adp_xc7k_ae350: Convert to v2 ef82a8255c soc: ae350: Port to HWMv2 282204758a samples: boards: stm32: ccm: fix include path 8ca9341195 samples: basic: threads: fix broken reference 8a947f446d boards: nrf52840dk: fix rst syntax 324cb41153 boards: nordic_nrf: fix broken references 963c74df1c boards: intel_(ish|adl|ehl|rpl), up_squared: fix include paths 8d518ce504 boards: legacy: drop empty folders 0fef0cef5b boards: mps2: fix table formatting e52ccc244f boards: add HWMv2 board index c7426eca5e boards: arm: add legacy tag 1eba9d8a8f boards: acrn: create vendor folder 8d92edc727 tests: kernel: Adjust qemu_x86_tiny_768 configuration HWMv2 75117d1b2d scripts: ensure posix path is used with --cmakeformat 0b0384b56a maintainers: update paths after HWMv2 changes c1b77b223d boards: arm: pan1783: Convert to v2 91a077b2ab boards: posix: nrf_bsim: Update paths 413b6c2a40 cmake: modules: configuration_files: Add board identifier overlay file 4f572ba24f treewide: Update board names for hwmv2 cb348c7edf boards: arm: nrf54l15pdk_nrf54l15: Convert to v2 811ad90566 boards: arm: nrf54h20pdk_nrf54h20: Convert to v2 d44ef90cf8 soc: nordic_nrf: Migrate nRF54H/nRF54L to v2 and fix nrf c860f205de boards: arm: nrf9151dk_nrf9151: Convert to v2 fba98a1763 soc: nordic_nrf: Migrate nRF9151 to v2 5c156a2d35 boards: arm: 96b_carbon_nrf51: Convert to v2 cfc47a3a4b boards: arm: nrf9161dk_nrf9161: Convert to v2 37129b4e44 boards: arm: nrf9131ek_nrf9131: Convert to v2 a923beba5d boards: arm: bl5340_dvk: Convert to v2 d242b2703b boards: arm: raytac_mdbt53v_db_40_nrf5340: Convert to v2 9c80d4e644 boards: arm: raytac_mdbt53_db_40: Convert to v2 28268c4938 boards: arm: nrf5340_audio_dk_nrf5340: Convert to v2 33ad2b5bc6 boards: arm: thingy53_nrf5340: Convert to v2 40daa94f2d boards: arm: nrf9160_innblue22: Convert to v2 2b0dbb9d51 boards: arm: nrf9160_innblue21: Convert to v2 ee6f7697ac boards: arm: sparkfun_thing_plus_nrf9160: Convert to v2 594e4bad6b boards: arm: circuitdojo_feather_nrf9160: Convert to v2 a5803ba099 boards: arm: actinius_icarus: Convert to v2 db8c275456 boards: arm: actinius_icarus_bee: Convert to v2 30177cf53d boards: arm: actinius_icarus_som: Convert to v2 486504cf24 boards: arm: actinius_icarus_som_dk: Convert to v2 dd0672a64c boards: arm: nrf9160dk_*: Convert to v2 c1565b3d14 boards: arm: xiao_ble: Convert to v2 6dd2723314 boards: arm: qemu_cortex_m0: Convert to v2 ee1ce24a42 boards: arm: bbc_microbit: Convert to v2 1952d559f2 boards: arm: rm1xx_dvk: Convert to v2 9e12c3d8bd boards: arm: nrf51dongle_nrf51422: Convert to v2 0ffbc1da33 boards: arm: nrf51_blenano: Convert to v2 be52dfb7b6 boards: arm: nrf51_vbluno51: Convert to v2 4c29d1827f boards: arm: nrf51_ble400: Convert to v2 5b4a9556fd boards: arm: raytac_mdbt53_db_40_nrf5340: Fix typo 69e5d87a15 boards: arm: contextualelectronics_abc: Convert to v2 5e4ace1bbe boards: arm: degu_evk: Convert to v2 2762460a64 boards: arm: pan1781_evb: Convert to v2 fdc3913e76 boards: arm: ubx_evkninab1_nrf52832: Convert to v2 9c9c3a09a1 boards: arm: holyiot_yj16019: Convert to v2 109edc296f boards: arm: blueclover_plt_demo_v2_nrf52832: Convert to v2 7bfcdbbe8f boards: arm: decawave_dwm1001_dev: Convert to v2 0fbb543983 boards: arm: acn52832: Convert to v2 073e0f8080 boards: arm: we_proteus2ev_nrf52832: Convert to v2 197a19f396 boards: arm: ebyte_e73_tbb_nrf52832: Convert to v2 1616fc8ae5 boards: arm: nrf52_vbluno52: Convert to v2 5622077738 boards: arm: nrf52_sparkfun: Convert to v2 a6289516e4 boards: arm: 96b_nitrogen: Convert to v2 439d836883 boards: arm: nrf52_blenano2: Convert to v2 16e65f09c4 boards: arm: arduino_nicla_sense_me: Convert to v2 862efd5a21 boards: arm: thingy52_nrf52832: Convert to v2 dede0f6cd3 boards: arm: nrf52_adafruit_feather: Convert to v2 91e864ea29 boards: arm: nrf52832_mdk: Convert to v2 47ec3e416b boards: arm: ruuvi_ruuvitag: Convert to v2 52f797a227 boards: arm: pinetime_devkit0: Convert to v2 433db339f9 boards: arm: ubx_evkannab1_nrf52832: Convert to v2 a646d3f2d5 boards: arm: ubx_bmd300eval_nrf52832: Convert to v2 d0d434bf86 cmake: print identifier instead of variant c3f5ed8157 boards: arm: we_proteus3ev_nrf52840: Convert to v2 eecff8ee7a boards: arm: nrf52840_mdk_usb_dongle: Convert to v2 34507614f6 boards: arm: nrf52840_mdk: Convert to v2 f02b56cb96 boards: arm: nrf52840_blip: Convert to v2 600c55c92a boards: arm: nrf52840_papyr: Convert to v2 f294bfc5e4 boards: arm: reel_board: Convert to v2 882524d2a0 boards: arm: nrf21540dk_nrf52840: Convert to v2 4bce0e9b39 boards: arm: nrf52840dongle_nrf52840: Convert to v2 d0229c771f boards: arm: particle_argon: Convert to v2 23a0570e64 boards: arm: particle_boron: Convert to v2 b6d3e1764f boards: arm: particle_xenon: Convert to v2 499f3e7902 boards: arm: rak5010_nrf52840: Convert to v2 9ae6b1804d boards: arm: rak4631_nrf52840: Convert to v2 fe2c90da5c boards: arm: pinnacle_100_dvk: Convert to v2 3d4d46698c boards: arm: ubx_evkninab3_nrf52840: Convert to v2 b1afbf0158 boards: arm: ubx_bmd380eval_nrf52840: Convert to v2 9f9897c872 boards: arm: ubx_bmd345eval_nrf52840: Convert to v2 f7fb2030c7 boards: arm: ubx_bmd340eval_nrf52840: Convert to v2 7186432662 boards: arm: raytac_mdbt50q_db_40_nrf52840: Convert to v2 32c4bdc0c4 boards: arm: pan1780_evb: Convert to v2 7b64c638a8 boards: arm: pan1770_evb: Convert to v2 156ee8ad8a boards: arm: mg100: Convert to v2 3d33dadeb0 boards: arm: arduino_nano_33_ble: Convert to v2 4fee7371d2 boards: arm: adafruit_itsybitsy_nrf52840: Convert to v2 ad37a0c222 boards: arm: adafruit_feather_nrf52840: Convert to v2 cf85b7169f boards: arm: bt510: Convert to v2 44b67ac430 boards: arm: bt610: Convert to v2 7dbb65d371 boards: arm: ubx_evkninab4_nrf52833: Convert to v2 5e79cb957d boards: arm: raytac_mdbt50q_db_33_nrf52833: Convert to v2 12bd83a218 boards: arm: pan1782_evb: Convert to v2 1a135ec352 boards: arm: bbc_microbit_v2: Convert to v2 4dbe97e5ea boards: arm: nrf52833dk: Convert to v2 d632b90043 boards: arm: ubx_bmd360eval_nrf52811: Convert to v2 cc1a30f24b boards: arm: we_ophelia1ev_nrf52805: Convert to v2 df0df9000b boards: arm: ubx_bmd330eval_nrf52810: Convert to v2 d2c7972a9a boards: arm: nrf52dk: Convert to v2 202c2bf447 boards: arm: bl654_sensor_board: Convert to v2 c3e36f2042 boards: arm: bl654_usb: Convert to v2 b9dd58aea1 boards: arm: bl654_dvk: Convert to v2 0e1898b093 boards: arm: bl653_dvk: Convert to v2 286f4a7524 boards: arm: bl652_dvk: Convert to v2 d1709cdb37 boards: update nRF51dk board to board scheme v2. 8f040cff2c boards: Update nrf5340dk_nrf5340 to HWMv2 scheme 8c90fae8e0 boards: update nRF52840dk_nrf52840/nrf52811 board to board scheme v2. c828dcc60e boards: common: openocd-nrf5: Add HWMv2 support c79f1b0d94 kconfig: soc: adopt Nordic SoC series to support hw model v2 scheme 3584b30fc1 tests: Update board names for hwmv2 94024d940e boards: arm: arty_a7: Convert to v2 8053c3a8df boards: arm: scobc_module1: Convert to v2 d5473b76fe soc: designstart: Port to HWMv2 f5792b05e7 boards: arm: fvp_baser_aemv8r_aarch32: Convert to v2 ff202daa8e soc: fvp_aemv8r_aarch32: Port to HWMv2 e66cbc2945 boards: arm: v2m_musca_s1: Convert to v2 33b47b2edb boards: arm: v2m_musca_b1: Convert to v2 baeebd31d2 soc: musca: Port to HWMv2 73b257a3f9 boards: arm: v2m_beetle: Convert to v2 85de0888ec soc: beetle: Port to HWMv2 867960a891 manifest: Update modules 6ca677ed3a boards: arm: mps2: Convert to v2 bcf4ad19d4 twister: build_dir: convert / to _ to support hwmv2 0ac386683f soc: Kconfig.v2: Add SOC_PART_NUMBER 9242c3c78f soc: stm32: soc.yml: reorder series 248d17f160 boards: stm32: cleanup 0a67265e99 boards: stm32: fix for boards with revisions f8d44317ee soc: stm32l5: Rename overlays for nucleo_l552ze_q ns target. 400343d17e soc: stm32: Set default on USE_DT_CODE_PARTITION d783ef549a soc: stm32l5: Update stm32l5 non secure targets in various places 643aeac552 boards: Convert stm32l562e_dk to HWM v2 e601d64344 boards: Convert nucleo_l552ze_q to HWM v2 2f7a387b32 soc: st: Migrate stm32l5 series to new hw model 519752efcd boards: xenvm: doc: Remove reference to deleted file 06263dd717 boards: xenvm: Unset HEAP_MEM_POOL_SIZE in gicv3 variant 66b0df5526 boards: qemu_cortex_a53: Fix Kconfig warnings in SMP variant fa07bd9419 boards: mps3: Fix non-secure variant 8f6f0726dd boards: Move xenvm under xen 7b155a7031 boards: Raspberry Pi vendor fix 804697afa5 boards: Move 96b_aerocore to 96boards d2f001e320 boards: x86: acrn: move and convert to HWMv2 ec7f7b3c30 tests: kernel: qemu_x86: adjust to the HWMv2 89dfcddc7e boards: x86: qemu_x86_tiny@768: change to board variant eb724eb6a7 boards: x86: qemu_x86: optimize default HWMv2 configurations 6f1043cde6 boards: x86: qemu_x86: move and convert to HWMv2 cab924cbfb soc: x86: ia32: move and convert to HWMv2 237fdff918 soc: x86: lakemont: move and convert to HWMv2 03042b7704 boards: move 96b_carbon to 96boards folder 767b94414e boards: rename vendor seeed to seeed_studio 07fa3a3d79 boards: Convert olimex_lora_stm32wl_devkit to HWM v2 ba01d3beca boards: Convert nucleo_wl55jc to HWM v2 7ce84f4041 boards: Convert lora_e5_mini to HWM v2 b988bae576 boards: Convert lora_e5_dev_board to HWM v2 6fbf39c726 soc: v2: stm32: Migrate STM32WL series 4a41878442 soc: st: stm32g4: add missing include 1e79ba15f6 boards: Convert weact_stm32g431_core to HWM v2 ffdcb60185 boards: Convert nucleo_g474re to HWM v2 d6acb08d3e boards: Convert nucleo_g431rb to HWM v2 90e592ffd1 boards: Convert b_g474e_dpow1 to HWM v2 eb8a7e3441 soc: st: stm32: Migrate STM32G4 series ada469f237 tests: Update board names for hwmv2 0342433187 boards: arm: npcx9m6f_evb: Convert to v2 c10248d964 boards: arm: npcx7m6fb_evb: Convert to v2 21ddc5e6a6 boards: arm: npcx4m8f_evb: Convert to v2 5500f3ef21 soc: npcx*: Port to HWMv2 e7baf09ede soc: m48x: Port to HWMv2 5bae4a6480 boards: arm: numaker_pfm_m467: Convert to v2 3b0bd70c8c soc: m46x: Port to HWMv2 d52eab9e83 boards: Convert stm32g081b_eval to HWM v2 6f2835cb11 boards: Convert stm32g071b_disco to HWM v2 ca36d331d2 boards: Convert stm32g0316_disco to HWM v2 662cc4e09b boards: Convert nucleo_g0b1re to HWM v2 dd9bc29769 boards: Convert nucleo_g071rb to HWM v2 353da23ffb boards: Convert nucleo_g070rb to HWM v2 acc932b424 boards: Convert nucleo_g031k8 to HWM v2 cea9b140fd boards: Convert google_twinkie_v2 to HWM v2 52e025943a soc: st: stm32: Migrate STM32G0 series 1c7347686a ci: update check_compliance to not create duplicate lines in Kconfig 9debd98799 hwmv2: boards: up_squared_pro_700: Add missed intel_adl changes adab07c42f boards: Convert msp_exp432p401r_launchxl to HWM v2 642aacdcdf soc: ti_simplelink: Add missing SoC 48637066d3 boards: Fix file paths in documentation e983bc2a23 samples/tests: Fix mps3 board name 61e0f32716 boards: Convert stm32f3_seco_d23 to HWM v2 a1688ff641 boards: Convert stm32f3_disco to HWM v2 35fb228599 boards: Convert stm32373c_eval to HWM v2 10e5d1122b boards: Convert nucleo_f334r8 to HWM v2 c319cb19f0 boards: Convert nucleo_f303re to HWM v2 11725ccac1 boards: Convert nucleo_f303k8 to HWM v2 400f7f6a4f boards: Convert nucleo_f302r8 to HWM v2 8d84861390 soc: v2: stm32: Migrate STM32F3 series 85b9eee7e8 boards: arm: kv260_r5: Convert to v2 dafbd638e4 boards: arm: mercury_xu: Convert to v2 3ecd12f415 boards: arm: qemu_cortex_r5: Convert to v2 5db2390e9d soc: xilinx_zyncmp: Port to HWMv2 9ba8195cdc boards: arm: qemu_cortex_a9: Convert to v2 8e94b85361 boards: arm: zybo: Convert to v2 c970127fc2 soc: xilinx_zynq7000: Port to HWMv2 394c75373c boards: arm: ast1030_evb: Convert to v2 f2a1cc8714 soc: ast10x0: Port to HWMv2 28f3f25945 boards: arm: cc3235sf_launchxl: Convert to v2 c3e480f740 boards: arm: cc3220sf_launchxl: Convert to v2 fd5847123f boards: arm: beagleconnect_freedom: Convert to v2 76ba9a0587 boards: arm: cc1352p1_launchxl: Convert to v2 719baa8850 boards: arm: cc1352r1_launchxl: Convert to v2 5060a61ae1 boards: arm: cc1352r_sensortag: Convert to v2 99584be1c5 boards: arm: cc26x2r1_launchxl: Convert to v2 2dc8933942 soc: ti_simplelink: Port to HWMv2 a5b004663b scripts/utils/board_v1_to_v2.py: couple of fixes 77c2c333e5 boards: move 96b_stm32_sensor_mez to 96boards c14ff98650 boards: stm32f411e_disco: delete obsolete file bcdc268ccf boards: Convert stm32mp157c_dk2 to HWM v2 0c8ba92e1f boards: Convert 96b_avenger96 to HWM v2 b54fe33077 soc: v2: stm32: Migrate STM32MP1 series 2ba3639b2a boards: Convert nucleo_c031c6 to HWM v2 dbc5ed79f5 soc: st: stm32: Migrate STM32C0 series ce6d493aa3 boards: Convert stm32l1_disco to HWM v2 a28086a9ca boards: Convert nucleo_l152re to HWM v2 1b2a511d06 boards: Convert 96b_wistrio to HWM v2 ce281f09ab soc: v2: stm32: Migrate STM32L1 series cdb5364fd7 boards: Convert stm32f769i_disco to HWM v2 768f173dcb boards: Convert stm32f7508_dk to HWM v2 21bbbbd9cb boards: Convert stm32f746g_disco to HWM v2 bab4265693 boards: Convert stm32f723e_disco to HWM v2 58f8fe82ba boards: Convert nucleo_f767zi to HWM v2 37e9084070 boards: Convert nucleo_f756zg to HWM v2 d467e7053a boards: Convert nucleo_f746zg to HWM v2 5f2808d7cc boards: Convert nucleo_f722ze to HWM v2 bbb73e7550 soc: st: Migrate stm32f7 series to new hw model e9094afc4d soc: st: stm32: stm32f4: change SOC_STM32F405XG to SOC_STM32F405XX a1712cdd53 boards: Convert stm32f4_disco to HWM v2 5be404b365 boards: Convert stm32f469i_disco to HWM v2 baaa697ab2 boards: Convert stm32f429i_disc1 to HWM v2 69ecab3c90 boards: Convert stm32f412g_disco to HWM v2 2a572e3fb0 boards: Convert stm32f411e_disco to HWM v2 ecfbf42757 boards: Convert stm32f401_mini to HWM v2 e0191d03bb boards: Convert steval_fcu001v1 to HWM v2 4454648976 boards: Convert segger_trb_stm32f407 to HWM v2 f0ad6ee6b8 boards: Convert olimex_stm32_p405 to HWM v2 1f5e228ec8 boards: Convert olimex_stm32_h407 to HWM v2 834bdb615e boards: Convert olimex_stm32_h405 to HWM v2 8f27fa8de2 boards: Convert olimex_stm32_e407 to HWM v2 f8633a9038 boards: Convert nucleo_f446ze to HWM v2 07e0bd2c07 boards: Convert nucleo_f446re to HWM v2 24d7f625dc boards: Convert nucleo_f429zi to HWM v2 157a8cde53 boards: Convert nucleo_f413zh to HWM v2 4ec99c31b0 boards: Convert nucleo_f412zg to HWM v2 a21546140a boards: Convert nucleo_f411re to HWM v2 43f01ab6de boards: Convert nucleo_f410rb to HWM v2 60c16bcb8b boards: Convert nucleo_f401re to HWM v2 2db228d730 boards: Convert mikroe_mini_m4_for_stm32 to HWM v2 73fc26225c boards: Convert mikroe_clicker_2 to HWM v2 6b62d90114 boards: Convert google_dragonclaw to HWM v2 fa845af309 boards: Convert blackpill_f411ce to HWM v2 5c8c3c3be0 boards: Convert blackpill_f401ce to HWM v2 3c02db1290 boards: Convert blackpill_f401cc to HWM v2 7eeb723cb7 boards: Convert black_f407zg_pro to HWM v2 4f9461d068 boards: Convert black_f407ve to HWM v2 a821de8532 boards: Convert az3166_iotdevkit to HWM v2 ba580c7236 boards: Convert adi_sdp_k1 to HWM v2 eb272ddf19 boards: Convert adafruit_feather_stm32f405 to HWM v2 58ed121c3a boards: Convert 96b_stm32_sensor_mez to HWM v2 b0d70959d3 boards: Convert 96b_neonkey to HWM v2 b1088baadc boards: Convert 96b_carbon to HWM v2 18d867b0a9 boards: Convert 96b_argonkey to HWM v2 ee6ede7119 boards: Convert 96b_aerocore2 to HWM v2 b48e70ead9 soc: v2: stm32: Migrate STM32F4 series 14d2b955da cmake: convert path to CMake style before writing Kconfig files 9c4ac6a202 boards: posix: bsim: Update paths 14b57f56d7 tests: drivers: gpio: gpio_ite_it8xxx2_v2: Temp fix f3b173be18 scripts: board_v1_to_v2: Update following move to boards_legacy 05b50f6691 cmake: CMake soc dir variable improvements for HWMv2 a188e01a12 hwmv2: move all ported boards and socs to their final location 22c53e97b5 hwmv2: move all non-ported legacy boards and socs to legacy folders 53f3b181b0 soc: ti_k3: Port to HWMv2 9f19a2075a soc: rk3568: Port to HWMv2 b8928b1628 soc: rk3399: Port to HWMv2 cda3a74868 boards: arm64: qemu_kvm_arm64: Convert to v2 70d704bd20 soc: x86: atom: move and convert to HWMv2 4789e1068e boards: x86: intel_rpl: move and convert raptor_lake boards to HWMv2 384307e3dc soc: x86: raptor_lake: move and convert to HWMv2 ed025df674 boards: x86: intel_ehl: move and convert elkhart_lake boards to HWMv2 994b6e1731 soc: x86: elkhart_lake: move and convert to HWMv2 73b30a04cf boards: x86: up_squared_pro_7000: move and convert to HWMv2 83b133c207 boards: x86: intel_adl: move and convert alder_lake boards to HWMv2 847a12f1e4 soc: alder_lake: move and convert to HWMv2 67f4c8d2a1 samples: up_squared: adjust gpio_counter to HWMv2 5326b5bfc0 boards: x86: up_squared: move and convert to HWMv2 cfd5e691b4 soc: apollo_lake: move and convert to HWMv2 ac9c235741 boards: xtensa: qemu_xtensa: Convert to v2 f198c3a761 ci: update to osource for soc/Kconfig.defconfig files e438e6cad4 ci: add SOC_SERIES_ as false positive in check_compliance.py 95e34da7c1 soc: v2: Convert st_stm32 to st/stm32 313717df76 soc: mps3: Fix missing family 392c3969ed boards: arm: am62x_m4: Convert to v2 8f245d764d tests: Update board names for hwmv2 8f71bb7b4f boards: arm64: khadas_edgev: Convert to v2 e27d23aad0 soc: rk3399: Port to HWMv2 80823b860e boards: arm64: roc_rk3568_pc: Convert to v2 72e4483dec soc: rk3568: Port to HWMv2 bed94669e3 boards: arm64: phycore_am62x_a53: Convert to v2 c01af5a7b8 soc: ti_k3: Port to HWMv2 1e563b4ca3 boards: arm64: xenvm: Convert to v2 76e484adae soc: xenvm: Port to HWMv2 34412f7fe2 boards: arm64: rpi_4b: Convert to v2 9be50e2ca9 soc: bcm2711: Port to HWMv2 bbbed12c2f boards: arm64: qemu_kvm_arm64: Convert to v2 4f5ec7ff8f soc: qemu_virt_arm64: Port to HWMv2 d8d1b9f200 boards: arm64: qemu_cortex_a53: Convert to v2 30bd34b31e soc: qemu_cortex_a53: Port to HWMv2 c20d0dcbb6 boards: arm64: fvp_baser_aemv8r: Convert to v2 02ed6af463 boards: arm64: fvp_base_revc_2xaemv8a: Convert to v2 1b175003a4 soc: fvp_aemv8*: Port to HWMv2 de231b911d boards: v2: Clean up obsolete comments aa9597f6d9 boards: Convert waveshare_open103z to HWM v2 9644828c81 boards: Convert stm32vl_disco to HWM v2 86ab2bd430 boards: Convert stm32_min_dev to HWM v2 d88d3ddcc4 boards: Convert stm32f103_mini to HWM v2 0ccc0204e1 boards: Convert stm3210c_eval to HWM v2 dd9972d782 boards: Convert olimex_stm32_h103 to HWM v2 a2c2e1406d boards: Convert olimexino_stm32 to HWM v2 2d9c62e118 boards: Convert nucleo_f103rb to HWM v2 e8ba99dc59 soc: v2: stm32: Migrate STM32F1 series 9a93916604 tests: Update board names for hwmv2 9c4d94844d boards: arm: bcm958401m2: Convert to v2 feaf4ffba1 boards: arm: bcm958402m2: Convert to v2 87f0827121 soc: bcm_vk: Port to HWMv2 4526be24a5 boards: arm: quick_feather: Convert to v2 cd921d2b97 boards: arm: qomu: Convert to v2 b3c04051fc soc: quicklogic_eos_s3: Port to HWMv2 a73a9e7533 boards: v2: Clean up obsolete comments 8d87bcc167 boards: Convert stm32f0_disco to HWM v2 1933585785 boards: Convert stm32f072_eval to HWM v2 6f9fe5429d boards: Convert stm32f072b_disco to HWM v2 9dc78e4025 boards: Convert stm32f030_demo to HWM v2 35113e8923 boards: Convert nucleo_f091rc to HWM v2 b276aee9a4 boards: Convert nucleo_f070rb to HWM v2 795f8d611b boards: Convert nucleo_f042k6 to HWM v2 2d82646443 boards: Convert nucleo_f031k6 to HWM v2 959786f12d boards: Convert nucleo_f030r8 to HWM v2 81670db2e9 boards: Convert legend to HWM v2 8980430aad boards: Convert google_kukui to HWM v2 ac020f66e0 dts: stm32f0: fix few warnings 5140e4551a boards: v2: doc: Add vendors 77d640e0c9 soc: v2: stm32: Migrate STM32F0 series 0131e1c159 soc: v2: Add st_stm32 structure and common folder 36b63787a7 boards: v2: Add documentation index for converted boards ae02fc5047 boards: sparc: qemu_leon3: Convert to v2 f38f7bb223 boards: sparc: gr716a: Convert to v2 d3cca3580e soc: gr716a: Port to HWMv2 6a8a0c1647 boards: sparc: generic_leon3: Convert to v2 faf22185ce soc: leon3: Port to HWMv2 e94762ecdc tests: Update board names for hwmv2 9afcc27e05 boards: xtensa: qemu_xtensa: Convert to v2 3e4a17018f soc: dc233c: Port to HWMv2 9188fdcd78 boards: xtensa: xt-sim: Convert to v2 fcaa41cb5d soc: xtensa_sample_controller: Port to HWMv2 dbc413f7f7 scripts: board_v1_to_v2: Fix CONFIG_SOC_SERIES_ exclusion 6be3d4bc80 kconfig: remove Kconfig BOARD_RPI_PICO_W safe guard. f4442fa698 boards: v2: Add documentation index for converted boards ec5fbd67f7 boards: nios2: qemu_nios2: Convert to v2 d3ef220460 soc: nios2-qemu: Port to HWMv2 a223f284b5 boards: nios2: altera_max10: Convert to v2 c381edcb73 soc: nios2f-zephyr: Port to HWMv2 97401c7d2a boards: mips: qemu_malta: Convert to v2 e7a3243a24 soc: qemu_malta: Port to HWMv2 bec82c690d boards: v2: Add documentation index for converted boards 94f6f9b636 boards: arm: w5500_evb_pico: Convert to v2 209235ab6e boards: arm: sparkfun_pro_micro_rp2040: Convert to v2 e5b1885907 boards: arm: adafruit_qt_py_rp2040: Convert to v2 4c750818f9 boards: arm: adafruit_kb2040: Convert to v2 8d3896caa4 boards: arm: rpi_pico: Convert to v2 42cff42c42 soc: rpi_pico: Port to HWMv2 c2df4ca9cb scripts: improve yaml schema and board.yml validation for revisions 3970f90f71 cmake: clear BOARD_CACHE when invalid board identifier is given 3a70ee9ccd cmake: improve board revision handling 3cda715fae scripts: board_v1_to_v2: Don't add select CONFIG_SOC_SERIES_FOO dc56a543f3 scripts: board_v1_to_v2: Add License + copyright 87147f88c4 cmake: prefer cache BOARD_IDENTIFIER over extracting from BOARD 65f5dc5b8c cmake: fail when board identifier is applied in legacy hw model 7db2b6efd8 cmake: cache BOARD_IDENTIFIER to preserve it between CMake invocations 85dddac5a2 scripts: using extend in list_boards for variant list 6ae5c4e7fd scripts: utils: add board v1->v2 conversion utility ef834a12d0 maintainers: update Renesas RZT2M path 3ab7830625 boards: renesas: add documentation entry a0c2ca0491 boards: arm: add documentation entry 27ff3654b7 boards: gigadevice: add documentation entry 6e02f43c0a maintainers: update GD32 paths 1bfcf1d974 boards: gd32l233r_eval: convert to HWMv2 6e621ee43f boards: gd32f470i_eval: convert to HWMv2 219b149768 boards: gd32f450z_eval: convert to HWMv2 91c52b0d39 boards: gd32f450v_start: convert to HWMv2 f0e0a973f6 boards: gd32f407v_start: convert to HWMv2 6f592b64c9 boards: gd32f403z_eval: convert to HWMv2 4bcb4b2ac8 boards: gd32f350r_eval: convert to HWMv2 fdc7ed6eb0 boards: gd32e507z_eval: convert to HWMv2 770376250d boards: gd32e507v_start: convert to HWMv2 a6d8b92e86 boards: gd32e103v_eval: convert to HWMv2 a5f8e5daa1 boards: gd32a503v_eval: convert to HWMv2 5ee799cc5f boards: gd32f450i_eval: convert to HWMv2 8aa8ce4ac8 soc: gigadevice: port to HWMv2 4e203c14c7 cmake: enhanced board entry file handling 312265ee04 scripts: make SoC field mandatory in board.yml c12ae3bcbc boards: update Renesas rzt2m board.yml to contain SoC information c5321c1dbe cmake: make SoC optional for boards containing a single SoC bcc06c60ae scripts: support SoC list output for boards db9e46010c twister: update testcase.yaml and sample.yaml to mps3/an547 identifier a988adee7d boards: update arm mps3 an547 board to HWMv2 scheme 7dc2c9db0c soc: use HWMv2 for arm mps3 SoC c506675b7c boards: update Renesas Starter Kit+ for RZ/T2M board to HWMv2 scheme 3abb792073 soc: use HWMv2 for renesas_rzt2m SoC 4f52bc646e cmake: support hw model v2 in arch/Kconfig tree a712b5005b scripts: extend kconfig compliance to verify board / SoC scheme v2 baa55141a1 twister: update twister testplan.py to handle HWMv2 boards 1f026f70eb boards: extend list_boards.py and update boards CMake module bd854a3af8 cmake: introduce arch and soc cmake modules for hw model v2 c9edefa8fd arch: add existing archs to archs.yml for HWMv2 support 61bbfb5ba2 scripts: introduce list_hardware.py for listing of architectures and SoCs a4d1980c35 build: board/ soc: introduce hw model v2 scheme Signed-off-by: Daniel DeGrasse Signed-off-by: Declan Snyder Signed-off-by: Gerard Marull-Paretas Signed-off-by: Sylvio Alves Signed-off-by: Torsten Rasmussen Signed-off-by: Fabio Baltieri Signed-off-by: Dmitrii Golovanov Signed-off-by: David Leach Signed-off-by: Emilio Benavente Signed-off-by: Anas Nashif Signed-off-by: Iuliana Prodan Signed-off-by: Jiafei Pan Signed-off-by: Jérôme Pouiller Signed-off-by: Filip Kokosinski Signed-off-by: Grzegorz Swiderski Signed-off-by: Gerson Fernando Budke Signed-off-by: Manuel Argüelles Signed-off-by: Erwan Gouriou Signed-off-by: Mahesh Mahadevan Signed-off-by: Alberto Escolar Piedras Signed-off-by: Francois Ramu Signed-off-by: Guillaume Gautier Signed-off-by: Carles Cufi Signed-off-by: Abderrahmane Jarmouni Signed-off-by: Yves Vandervennet Signed-off-by: Jamie McCrae --- .github/workflows/codecov.yaml | 2 +- .github/workflows/compliance.yml | 2 + .gitignore | 3 + CMakeLists.txt | 2 +- CODEOWNERS | 25 +- Kconfig.zephyr | 13 +- MAINTAINERS.yml | 301 ++--- arch/Kconfig | 27 +- arch/Kconfig.v1 | 5 + arch/Kconfig.v2 | 5 + arch/arc/Kconfig | 5 +- arch/archs.yml | 21 + arch/arm/Kconfig | 43 + arch/arm/core/cortex_m/timing.c | 6 +- arch/common/CMakeLists.txt | 2 +- arch/riscv/core/fatal.c | 4 +- arch/x86/core/early_serial.c | 1 - arch/xtensa/core/CMakeLists.txt | 2 +- .../aerocore2}/96b_aerocore2.dts | 0 .../aerocore2}/96b_aerocore2.yaml | 2 +- .../aerocore2}/96b_aerocore2_defconfig | 3 - .../96boards/aerocore2/Kconfig.96b_aerocore2 | 5 + .../aerocore2}/board.cmake | 0 boards/96boards/aerocore2/board.yml | 5 + .../aerocore2}/doc/img/96b_aerocore2.jpg | Bin boards/96boards/aerocore2/doc/index.rst | 349 ++++++ .../argonkey}/96b_argonkey.dts | 0 .../argonkey}/96b_argonkey.yaml | 0 .../argonkey}/96b_argonkey_defconfig | 3 - boards/96boards/argonkey/Kconfig.96b_argonkey | 5 + boards/96boards/argonkey/Kconfig.defconfig | 23 + boards/96boards/argonkey/board.yml | 5 + .../argonkey}/doc/img/96b_argonkey.jpg | Bin boards/96boards/argonkey/doc/index.rst | 239 ++++ .../avenger96}/96b_avenger96.dts | 0 .../avenger96}/96b_avenger96.yaml | 2 +- .../avenger96}/96b_avenger96_defconfig | 3 - .../96boards/avenger96/Kconfig.96b_avenger96 | 5 + .../avenger96}/board.cmake | 0 boards/96boards/avenger96/board.yml | 5 + .../avenger96}/doc/img/96b_avenger96.jpg | Bin boards/96boards/avenger96/doc/index.rst | 279 +++++ .../carbon/96b_carbon_nrf51822-pinctrl.dtsi} | 0 .../96boards/carbon/96b_carbon_nrf51822.dts | 63 + .../96boards/carbon/96b_carbon_nrf51822.yaml | 13 + .../carbon/96b_carbon_nrf51822_defconfig | 11 + .../carbon/96b_carbon_stm32f401xe.dts} | 0 .../carbon/96b_carbon_stm32f401xe.yaml | 18 + .../carbon/96b_carbon_stm32f401xe_defconfig | 22 + .../carbon}/96b_lscon.dtsi | 0 boards/96boards/carbon/Kconfig.96b_carbon | 6 + boards/96boards/carbon/Kconfig.defconfig | 61 + boards/96boards/carbon/board.cmake | 7 + boards/96boards/carbon/board.yml | 6 + .../carbon}/doc/img/96b_carbon.jpg | Bin .../carbon}/doc/img/96b_carbon_nrf51.jpg | Bin boards/96boards/carbon/doc/nrf51822.rst | 170 +++ boards/96boards/carbon/doc/stm32f401xe.rst | 383 ++++++ boards/96boards/carbon/pre_dt_board.cmake | 8 + boards/96boards/index.rst | 10 + .../meerkat96}/96b_meerkat96-pinctrl.dtsi | 0 .../meerkat96/96b_meerkat96_mcimx7d_m4.dts} | 0 .../meerkat96/96b_meerkat96_mcimx7d_m4.yaml | 24 + .../96b_meerkat96_mcimx7d_m4_defconfig | 18 + .../96boards/meerkat96/Kconfig.96b_meerkat96 | 7 + boards/96boards/meerkat96/Kconfig.defconfig | 15 + boards/96boards/meerkat96/board.yml | 5 + .../meerkat96}/doc/img/96b_meerkat96.jpg | Bin boards/96boards/meerkat96/doc/index.rst | 325 +++++ .../neonkey}/96b_neonkey.dts | 0 .../neonkey}/96b_neonkey.yaml | 0 .../neonkey}/96b_neonkey_defconfig | 3 - boards/96boards/neonkey/Kconfig.96b_neonkey | 5 + boards/96boards/neonkey/Kconfig.defconfig | 12 + boards/96boards/neonkey/board.yml | 5 + .../neonkey}/doc/img/96b_neonkey.jpg | Bin boards/96boards/neonkey/doc/index.rst | 232 ++++ .../nitrogen}/96b_lscon.dtsi | 0 .../nitrogen}/96b_nitrogen-pinctrl.dtsi | 0 .../nitrogen}/96b_nitrogen.dts | 0 .../nitrogen}/96b_nitrogen.yaml | 0 .../nitrogen}/96b_nitrogen_defconfig | 3 - boards/96boards/nitrogen/Kconfig.96b_nitrogen | 7 + boards/96boards/nitrogen/Kconfig.defconfig | 11 + .../nitrogen}/board.cmake | 0 boards/96boards/nitrogen/board.yml | 5 + .../nitrogen}/doc/img/96b_nitrogen.jpg | Bin boards/96boards/nitrogen/doc/index.rst | 329 +++++ .../nitrogen}/pre_dt_board.cmake | 0 .../96b_stm32_sensor_mez.dts | 0 .../96b_stm32_sensor_mez.yaml | 0 .../96b_stm32_sensor_mez_defconfig | 3 - .../Kconfig.96b_stm32_sensor_mez | 5 + .../stm32_sensor_mez/Kconfig.defconfig | 12 + .../stm32_sensor_mez}/board.cmake | 0 boards/96boards/stm32_sensor_mez/board.yml | 5 + .../doc/img/96b_stm32_sensor_mez.jpg | Bin .../96boards/stm32_sensor_mez/doc/index.rst | 247 ++++ .../stm32_sensor_mez}/support/openocd.cfg | 0 .../wistrio}/96b_lscon.dtsi | 0 .../wistrio}/96b_wistrio.dts | 0 .../wistrio}/96b_wistrio.yaml | 0 .../wistrio}/96b_wistrio_defconfig | 3 - .../wistrio}/CMakeLists.txt | 0 boards/96boards/wistrio/Kconfig.96b_wistrio | 5 + boards/96boards/wistrio/Kconfig.defconfig | 11 + .../wistrio}/board.cmake | 0 boards/96boards/wistrio/board.yml | 5 + .../wistrio}/doc/96b_wistrio.rst | 5 +- .../wistrio}/doc/img/96b-wistrio.jpg | Bin .../wistrio}/dts/bindings/qorvo,rfsw8001.yaml | 0 .../96b_wistrio => 96boards/wistrio}/rf.c | 0 boards/Kconfig | 11 +- boards/Kconfig.v1 | 10 + boards/Kconfig.v2 | 18 + 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18 - boards/arc/hsdk/Kconfig.board | 13 - boards/arc/hsdk/Kconfig.defconfig | 23 - boards/arc/hsdk/board.cmake | 10 - boards/arc/hsdk/hsdk_2cores.yaml | 16 - boards/arc/hsdk/hsdk_2cores_defconfig | 16 - boards/arc/hsdk4xd/Kconfig.board | 13 - boards/arc/hsdk4xd/Kconfig.defconfig | 9 - boards/arc/hsdk4xd/board.cmake | 6 - boards/arc/hsdk4xd/doc/index.rst | 557 --------- boards/arc/hsdk4xd/hsdk4xd.dts | 14 - boards/arc/hsdk4xd/hsdk4xd.dtsi | 34 - boards/arc/index.rst | 10 - boards/arc/iotdk/Kconfig.board | 10 - boards/arc/iotdk/Kconfig.defconfig | 5 - boards/arc/iotdk/board.cmake | 6 - boards/arc/iotdk/board.dtsi | 2 - boards/arc/nsim/Kconfig.board | 13 - boards/arc/nsim/Kconfig.defconfig | 8 - boards/arc/nsim/doc/index.rst | 339 ------ boards/arc/nsim/nsim_em.yaml | 15 - boards/arc/nsim/nsim_em11d.yaml | 15 - boards/arc/nsim/nsim_em11d_defconfig | 15 - boards/arc/nsim/nsim_em7d_v22.yaml | 14 - boards/arc/nsim/nsim_em7d_v22_defconfig | 15 - boards/arc/nsim/nsim_em_defconfig | 15 - boards/arc/nsim/nsim_hs.yaml | 15 - boards/arc/nsim/nsim_hs3x_hostlink.yaml | 15 - boards/arc/nsim/nsim_hs3x_hostlink_defconfig | 14 - boards/arc/nsim/nsim_hs5x.yaml | 15 - boards/arc/nsim/nsim_hs5x_defconfig | 14 - boards/arc/nsim/nsim_hs5x_smp.yaml | 18 - boards/arc/nsim/nsim_hs5x_smp_12cores.yaml | 17 - .../arc/nsim/nsim_hs5x_smp_12cores_defconfig | 17 - boards/arc/nsim/nsim_hs5x_smp_defconfig | 17 - boards/arc/nsim/nsim_hs6x.yaml | 15 - boards/arc/nsim/nsim_hs6x_defconfig | 14 - boards/arc/nsim/nsim_hs6x_smp.yaml | 18 - boards/arc/nsim/nsim_hs6x_smp_12cores.yaml | 17 - .../arc/nsim/nsim_hs6x_smp_12cores_defconfig | 17 - boards/arc/nsim/nsim_hs6x_smp_defconfig | 17 - boards/arc/nsim/nsim_hs_defconfig | 14 - boards/arc/nsim/nsim_hs_flash_xip.yaml | 15 - boards/arc/nsim/nsim_hs_flash_xip_defconfig | 15 - boards/arc/nsim/nsim_hs_mpuv6.yaml | 16 - boards/arc/nsim/nsim_hs_mpuv6_defconfig | 14 - boards/arc/nsim/nsim_hs_smp.yaml | 19 - boards/arc/nsim/nsim_hs_smp_defconfig | 16 - boards/arc/nsim/nsim_hs_sram.yaml | 15 - boards/arc/nsim/nsim_hs_sram_defconfig | 15 - boards/arc/nsim/nsim_sem.yaml | 16 - boards/arc/nsim/nsim_sem_defconfig | 15 - boards/arc/nsim/nsim_sem_mpu_stack_guard.yaml | 15 - .../nsim/nsim_sem_mpu_stack_guard_defconfig | 16 - boards/arc/nsim/nsim_vpx5.yaml | 13 - boards/arc/nsim/nsim_vpx5_defconfig | 13 - boards/arc/qemu_arc/Kconfig.board | 9 - boards/arc/qemu_arc/Kconfig.defconfig | 20 - boards/arc/qemu_arc/board.cmake | 44 - boards/arc/qemu_arc/doc/index.rst | 102 -- boards/arc/qemu_arc/qemu_arc_em.yaml | 14 - boards/arc/qemu_arc/qemu_arc_em_defconfig | 12 - boards/arc/qemu_arc/qemu_arc_hs.yaml | 15 - boards/arc/qemu_arc/qemu_arc_hs5x.yaml | 14 - boards/arc/qemu_arc/qemu_arc_hs5x_defconfig | 12 - boards/arc/qemu_arc/qemu_arc_hs6x.yaml | 14 - boards/arc/qemu_arc/qemu_arc_hs6x_defconfig | 12 - boards/arc/qemu_arc/qemu_arc_hs_defconfig | 12 - boards/arc/qemu_arc/qemu_arc_hs_xip.yaml | 14 - boards/arc/qemu_arc/qemu_arc_hs_xip_defconfig | 12 - boards/arduino/due/Kconfig.arduino_due | 5 + .../due}/arduino_due-pinctrl.dtsi | 0 .../due}/arduino_due.dts | 0 .../due}/arduino_due.yaml | 8 +- boards/arduino/due/arduino_due_defconfig | 9 + .../arduino_due => arduino/due}/board.cmake | 0 boards/arduino/due/board.yml | 5 + .../due}/doc/img/arduino_due.jpg | Bin boards/arduino/due/doc/index.rst | 214 ++++ .../arduino/giga_r1/Kconfig.arduino_giga_r1 | 6 + boards/arduino/giga_r1/Kconfig.defconfig | 18 + .../giga_r1}/arduino_giga_r1.dtsi | 0 .../arduino_giga_r1_stm32h747xx_m4.dts} | 0 .../arduino_giga_r1_stm32h747xx_m4.yaml | 19 + .../arduino_giga_r1_stm32h747xx_m4_defconfig | 24 + .../arduino_giga_r1_stm32h747xx_m7.dts} | 0 .../arduino_giga_r1_stm32h747xx_m7.yaml | 19 + .../arduino_giga_r1_stm32h747xx_m7_defconfig | 30 + .../giga_r1}/arduino_r3_connector.dtsi | 0 boards/arduino/giga_r1/board.cmake | 18 + boards/arduino/giga_r1/board.yml | 5 + .../giga_r1}/doc/img/arduino_giga_r1.jpg | Bin boards/arduino/giga_r1/doc/index.rst | 186 +++ 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.../arduino_nano_33_ble_nrf52840_sense.dts} | 0 .../arduino_nano_33_ble_nrf52840_sense.yaml | 20 + ...duino_nano_33_ble_nrf52840_sense_defconfig | 17 + .../arduino_nano_r3_connector.dtsi | 0 .../nano_33_ble}/board.c | 0 .../nano_33_ble}/board.cmake | 0 boards/arduino/nano_33_ble/board.yml | 7 + .../doc/img/arduino_nano_33_ble_sense.jpg | Bin .../nano_33_ble}/doc/img/nano_33_ble_swd.jpg | Bin .../nano_33_ble}/doc/index.rst | 0 .../nano_33_ble}/pre_dt_board.cmake | 0 .../nano_33_ble}/support/debug.cmm | 0 .../nano_33_ble}/support/startup.cmm | 0 .../nano_33_iot/Kconfig.arduino_nano_33_iot | 6 + .../arduino_nano_33_iot-pinctrl.dtsi | 0 .../nano_33_iot}/arduino_nano_33_iot.dts | 0 .../nano_33_iot}/arduino_nano_33_iot.yaml | 0 .../nano_33_iot/arduino_nano_33_iot_defconfig | 13 + .../arduino_nano_r3_connector.dtsi | 0 .../nano_33_iot}/board.cmake | 0 boards/arduino/nano_33_iot/board.yml | 5 + .../nano_33_iot}/doc/img/nano_33_iot.jpg | Bin boards/arduino/nano_33_iot/doc/index.rst | 171 +++ .../nano_33_iot}/pre_dt_board.cmake | 0 .../Kconfig.arduino_nicla_sense_me | 7 + .../arduino/nicla_sense_me/Kconfig.defconfig | 11 + .../arduino_nicla_sense_me-pinctrl.dtsi | 0 .../arduino_nicla_sense_me.dts | 0 .../arduino_nicla_sense_me.yaml | 0 .../arduino_nicla_sense_me_defconfig | 18 + .../nicla_sense_me}/board.cmake | 0 boards/arduino/nicla_sense_me/board.yml | 5 + .../doc/arduino_nicla_sense_me.jpg | Bin .../doc/arduino_nicla_sense_me_pinout.jpg | Bin .../nicla_sense_me}/doc/index.rst | 0 .../nicla_sense_me}/pre_dt_board.cmake | 0 boards/arduino/opta/Kconfig.arduino_opta | 5 + .../opta/arduino_opta_stm32h747xx_m4.dts} | 0 .../opta/arduino_opta_stm32h747xx_m4.yaml | 21 + .../arduino_opta_stm32h747xx_m4_defconfig | 20 + .../opta}/board.cmake | 0 boards/arduino/opta/board.yml | 5 + .../opta}/doc/img/arduino_opta.jpeg | Bin boards/arduino/opta/doc/index.rst | 177 +++ boards/arduino/portenta_h7/CMakeLists.txt | 9 + .../portenta_h7/Kconfig.arduino_portenta_h7 | 8 + .../arduino_portenta_h7-common.dtsi | 0 .../arduino_portenta_h7_stm32h747xx_m4.dts} | 0 .../arduino_portenta_h7_stm32h747xx_m4.yaml | 17 + ...duino_portenta_h7_stm32h747xx_m4_defconfig | 24 + .../arduino_portenta_h7_stm32h747xx_m7.dts} | 0 .../arduino_portenta_h7_stm32h747xx_m7.yaml | 13 + ...duino_portenta_h7_stm32h747xx_m7_defconfig | 36 + .../portenta_h7}/board.c | 0 .../portenta_h7}/board.cmake | 0 boards/arduino/portenta_h7/board.yml | 5 + .../doc/img/arduino_portenta_h7.jpeg | Bin boards/arduino/portenta_h7/doc/index.rst | 144 +++ .../Kconfig.arduino_uno_r4_minima | 5 + .../uno_r4_minima}/arduino_uno_r4_common.dtsi | 0 .../arduino_uno_r4_minima-pinctrl.dtsi | 0 .../uno_r4_minima}/arduino_uno_r4_minima.dts | 0 .../uno_r4_minima}/arduino_uno_r4_minima.yaml | 0 .../arduino_uno_r4_minima_defconfig | 9 +- .../uno_r4_minima}/board.cmake | 0 boards/arduino/uno_r4_minima/board.yml | 5 + .../uno_r4_minima}/doc/index.rst | 0 boards/arduino/zero/Kconfig.arduino_zero | 6 + .../zero}/arduino_zero-pinctrl.dtsi | 0 .../zero}/arduino_zero.dts | 0 .../zero}/arduino_zero.yaml | 0 boards/arduino/zero/arduino_zero_defconfig | 12 + .../arduino_zero => arduino/zero}/board.cmake | 0 boards/arduino/zero/board.yml | 5 + .../zero}/doc/img/arduino_zero.jpg | Bin boards/arduino/zero/doc/index.rst | 166 +++ .../zero}/pre_dt_board.cmake | 0 .../zero}/support/openocd.cfg | 0 boards/arm/96b_aerocore2/Kconfig.board | 6 - boards/arm/96b_aerocore2/Kconfig.defconfig | 9 - boards/arm/96b_aerocore2/doc/index.rst | 350 ------ boards/arm/96b_argonkey/Kconfig.board | 8 - boards/arm/96b_argonkey/Kconfig.defconfig | 26 - boards/arm/96b_argonkey/doc/index.rst | 240 ---- boards/arm/96b_avenger96/Kconfig.board | 8 - boards/arm/96b_avenger96/Kconfig.defconfig | 11 - boards/arm/96b_avenger96/doc/index.rst | 279 ----- boards/arm/96b_carbon/96b_carbon.yaml | 18 - boards/arm/96b_carbon/96b_carbon_defconfig | 25 - boards/arm/96b_carbon/Kconfig.board | 8 - boards/arm/96b_carbon/Kconfig.defconfig | 57 - boards/arm/96b_carbon/doc/index.rst | 384 ------ .../arm/96b_carbon_nrf51/96b_carbon_nrf51.dts | 63 - .../96b_carbon_nrf51/96b_carbon_nrf51.yaml | 13 - .../96b_carbon_nrf51_defconfig | 14 - boards/arm/96b_carbon_nrf51/Kconfig.board | 8 - boards/arm/96b_carbon_nrf51/Kconfig.defconfig | 14 - boards/arm/96b_carbon_nrf51/doc/index.rst | 171 --- boards/arm/96b_meerkat96/96b_meerkat96.yaml | 24 - .../arm/96b_meerkat96/96b_meerkat96_defconfig | 22 - boards/arm/96b_meerkat96/Kconfig.board | 9 - boards/arm/96b_meerkat96/Kconfig.defconfig | 18 - boards/arm/96b_meerkat96/doc/index.rst | 325 ----- boards/arm/96b_neonkey/Kconfig.board | 8 - boards/arm/96b_neonkey/Kconfig.defconfig | 15 - boards/arm/96b_neonkey/doc/index.rst | 233 ---- boards/arm/96b_nitrogen/Kconfig | 8 - boards/arm/96b_nitrogen/Kconfig.board | 8 - boards/arm/96b_nitrogen/Kconfig.defconfig | 14 - boards/arm/96b_nitrogen/doc/index.rst | 330 ----- boards/arm/96b_stm32_sensor_mez/Kconfig.board | 8 - .../96b_stm32_sensor_mez/Kconfig.defconfig | 15 - boards/arm/96b_stm32_sensor_mez/doc/index.rst | 248 ---- boards/arm/96b_wistrio/Kconfig.board | 8 - boards/arm/96b_wistrio/Kconfig.defconfig | 14 - boards/arm/acn52832/Kconfig.board | 8 - boards/arm/acn52832/Kconfig.defconfig | 14 - boards/arm/acn52832/acn52832_defconfig | 18 - boards/arm/actinius_icarus/CMakeLists.txt | 8 - boards/arm/actinius_icarus/Kconfig.board | 14 - boards/arm/actinius_icarus/Kconfig.defconfig | 40 - .../arm/actinius_icarus/actinius_icarus.yaml | 23 - .../actinius_icarus_1_4_0.overlay | 7 - .../actinius_icarus_2_0_0.overlay | 7 - .../actinius_icarus/actinius_icarus_defconfig | 24 - .../actinius_icarus/actinius_icarus_ns.yaml | 23 - .../actinius_icarus_ns_1_4_0.overlay | 7 - .../actinius_icarus_ns_2_0_0.overlay | 7 - .../actinius_icarus_ns_defconfig | 27 - boards/arm/actinius_icarus/doc/index.rst | 238 ---- boards/arm/actinius_icarus/revision.cmake | 8 - boards/arm/actinius_icarus_bee/CMakeLists.txt | 8 - boards/arm/actinius_icarus_bee/Kconfig.board | 14 - .../arm/actinius_icarus_bee/Kconfig.defconfig | 40 - .../actinius_icarus_bee.yaml | 18 - .../actinius_icarus_bee_defconfig | 24 - .../actinius_icarus_bee_ns.yaml | 18 - .../actinius_icarus_bee_ns_defconfig | 27 - boards/arm/actinius_icarus_bee/doc/index.rst | 137 --- boards/arm/actinius_icarus_som/CMakeLists.txt | 8 - boards/arm/actinius_icarus_som/Kconfig.board | 14 - .../arm/actinius_icarus_som/Kconfig.defconfig | 40 - .../actinius_icarus_som.yaml | 17 - .../actinius_icarus_som_defconfig | 24 - .../actinius_icarus_som_ns.yaml | 17 - .../actinius_icarus_som_ns_defconfig | 27 - boards/arm/actinius_icarus_som/doc/index.rst | 137 --- .../arm/actinius_icarus_som_dk/CMakeLists.txt | 8 - .../arm/actinius_icarus_som_dk/Kconfig.board | 14 - .../actinius_icarus_som_dk/Kconfig.defconfig | 40 - .../actinius_icarus_som_dk.yaml | 22 - .../actinius_icarus_som_dk_defconfig | 24 - .../actinius_icarus_som_dk_ns.yaml | 22 - .../actinius_icarus_som_dk_ns_defconfig | 27 - .../arm/actinius_icarus_som_dk/doc/index.rst | 245 ---- .../Kconfig.board | 8 - .../Kconfig.defconfig | 8 - .../adafruit_feather_m0_basic_proto_defconfig | 12 - .../doc/index.rst | 167 --- .../adafruit_feather_m0_lora/Kconfig.board | 8 - .../Kconfig.defconfig | 8 - .../adafruit_feather_m0_lora_defconfig | 12 - .../adafruit_feather_m0_lora/doc/index.rst | 176 --- boards/arm/adafruit_feather_nrf52840/Kconfig | 10 - .../adafruit_feather_nrf52840/Kconfig.board | 8 - .../Kconfig.defconfig | 14 - .../adafruit_feather_nrf52840_defconfig | 18 - .../adafruit_feather_nrf52840/doc/index.rst | 146 --- .../adafruit_feather_stm32f405/Kconfig.board | 8 - .../Kconfig.defconfig | 11 - .../Kconfig.board | 8 - .../Kconfig.defconfig | 8 - ...dafruit_grand_central_m4_express_defconfig | 19 - .../doc/index.rst | 195 --- .../Kconfig.board | 8 - .../Kconfig.defconfig | 8 - .../adafruit_itsybitsy_m4_express_defconfig | 13 - .../doc/index.rst | 209 ---- .../arm/adafruit_itsybitsy_nrf52840/Kconfig | 14 - .../adafruit_itsybitsy_nrf52840/Kconfig.board | 8 - .../Kconfig.defconfig | 56 - .../adafruit_itsybitsy_nrf52840_defconfig | 22 - .../adafruit_itsybitsy_nrf52840/doc/index.rst | 192 --- boards/arm/adafruit_kb2040/Kconfig.board | 6 - boards/arm/adafruit_kb2040/Kconfig.defconfig | 22 - .../arm/adafruit_qt_py_rp2040/Kconfig.board | 6 - .../adafruit_qt_py_rp2040/Kconfig.defconfig | 22 - boards/arm/adafruit_trinket_m0/Kconfig.board | 8 - .../arm/adafruit_trinket_m0/Kconfig.defconfig | 8 - .../adafruit_trinket_m0_defconfig | 14 - boards/arm/adafruit_trinket_m0/doc/index.rst | 170 --- boards/arm/adi_eval_adin1110ebz/Kconfig.board | 8 - .../adi_eval_adin1110ebz/Kconfig.defconfig | 33 - .../adi_eval_adin1110ebz_defconfig | 21 - boards/arm/adi_eval_adin1110ebz/doc/index.rst | 183 --- boards/arm/adi_eval_adin2111ebz/Kconfig.board | 8 - .../adi_eval_adin2111ebz/Kconfig.defconfig | 37 - .../adi_eval_adin2111ebz_defconfig | 21 - boards/arm/adi_eval_adin2111ebz/doc/index.rst | 184 --- boards/arm/adi_sdp_k1/Kconfig.board | 8 - boards/arm/adi_sdp_k1/Kconfig.defconfig | 15 - boards/arm/adi_sdp_k1/doc/index.rst | 184 --- boards/arm/am62x_m4/Kconfig.board | 14 - boards/arm/am62x_m4/Kconfig.defconfig | 20 - .../arm/am62x_m4/am62x_m4_phyboard_lyra.yaml | 8 - .../am62x_m4/am62x_m4_phyboard_lyra_defconfig | 28 - boards/arm/am62x_m4/am62x_m4_sk.yaml | 8 - boards/arm/am62x_m4/am62x_m4_sk_defconfig | 25 - .../am62x_m4/doc/am62x_m4_phyboard_lyra.rst | 148 --- boards/arm/am62x_m4/doc/am62x_m4_sk.rst | 141 --- boards/arm/am62x_m4/doc/index.rst | 38 - .../arm/apollo4p_blue_kxr_evb/Kconfig.board | 7 - .../apollo4p_blue_kxr_evb/Kconfig.defconfig | 38 - .../arm/apollo4p_blue_kxr_evb/doc/index.rst | 110 -- boards/arm/apollo4p_evb/Kconfig.board | 7 - boards/arm/apollo4p_evb/Kconfig.defconfig | 7 - boards/arm/apollo4p_evb/doc/index.rst | 105 -- boards/arm/arduino_due/Kconfig.board | 8 - boards/arm/arduino_due/Kconfig.defconfig | 11 - boards/arm/arduino_due/arduino_due_defconfig | 14 - boards/arm/arduino_due/doc/index.rst | 214 ---- boards/arm/arduino_giga_r1/Kconfig.board | 12 - boards/arm/arduino_giga_r1/Kconfig.defconfig | 22 - .../arduino_giga_r1/arduino_giga_r1_m4.yaml | 19 - .../arduino_giga_r1_m4_defconfig | 30 - .../arduino_giga_r1/arduino_giga_r1_m7.yaml | 19 - .../arduino_giga_r1_m7_defconfig | 36 - boards/arm/arduino_giga_r1/board.cmake | 18 - boards/arm/arduino_giga_r1/doc/index.rst | 186 --- boards/arm/arduino_mkrzero/Kconfig.board | 8 - boards/arm/arduino_mkrzero/Kconfig.defconfig | 21 - .../arduino_mkrzero/arduino_mkrzero_defconfig | 14 - boards/arm/arduino_mkrzero/doc/index.rst | 183 --- boards/arm/arduino_nano_33_ble/Kconfig.board | 10 - .../arm/arduino_nano_33_ble/Kconfig.defconfig | 16 - .../arduino_nano_33_ble_sense.yaml | 20 - .../arduino_nano_33_ble_sense_defconfig | 21 - boards/arm/arduino_nano_33_iot/Kconfig.board | 8 - .../arm/arduino_nano_33_iot/Kconfig.defconfig | 8 - .../arduino_nano_33_iot_defconfig | 13 - boards/arm/arduino_nano_33_iot/doc/index.rst | 171 --- .../arm/arduino_nicla_sense_me/Kconfig.board | 8 - .../arduino_nicla_sense_me/Kconfig.defconfig | 14 - .../arduino_nicla_sense_me_defconfig | 22 - boards/arm/arduino_opta_m4/Kconfig.board | 7 - boards/arm/arduino_opta_m4/Kconfig.defconfig | 9 - .../arm/arduino_opta_m4/arduino_opta_m4.yaml | 21 - .../arduino_opta_m4/arduino_opta_m4_defconfig | 25 - boards/arm/arduino_opta_m4/doc/index.rst | 177 --- boards/arm/arduino_portenta_h7/CMakeLists.txt | 9 - boards/arm/arduino_portenta_h7/Kconfig.board | 14 - .../arm/arduino_portenta_h7/Kconfig.defconfig | 12 - .../arduino_portenta_h7_m4.yaml | 17 - .../arduino_portenta_h7_m4_defconfig | 30 - .../arduino_portenta_h7_m7.yaml | 13 - .../arduino_portenta_h7_m7_defconfig | 42 - boards/arm/arduino_portenta_h7/doc/index.rst | 144 --- boards/arm/arduino_uno_r4/Kconfig.board | 6 - boards/arm/arduino_uno_r4/Kconfig.defconfig | 9 - boards/arm/arduino_zero/Kconfig.board | 8 - boards/arm/arduino_zero/Kconfig.defconfig | 8 - .../arm/arduino_zero/arduino_zero_defconfig | 12 - boards/arm/arduino_zero/doc/index.rst | 166 --- boards/arm/arty/CMakeLists.txt | 29 - boards/arm/arty/Kconfig | 13 - boards/arm/arty/Kconfig.board | 12 - boards/arm/arty/Kconfig.defconfig | 24 - .../arm/arty/arty_a7_arm_designstart_m1.yaml | 14 - .../arty/arty_a7_arm_designstart_m1_defconfig | 11 - .../arm/arty/arty_a7_arm_designstart_m3.yaml | 14 - .../arty/arty_a7_arm_designstart_m3_defconfig | 12 - boards/arm/arty/board.cmake | 15 - boards/arm/arty/doc/index.rst | 228 ---- boards/arm/ast1030_evb/Kconfig.board | 9 - boards/arm/ast1030_evb/Kconfig.defconfig | 10 - boards/arm/ast1030_evb/doc/index.rst | 93 -- boards/arm/atsamc21n_xpro/Kconfig.board | 8 - boards/arm/atsamc21n_xpro/Kconfig.defconfig | 8 - boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts | 183 --- boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml | 22 - .../atsamc21n_xpro/atsamc21n_xpro_defconfig | 11 - boards/arm/atsamc21n_xpro/doc/index.rst | 194 --- boards/arm/atsamd20_xpro/Kconfig.board | 8 - boards/arm/atsamd20_xpro/Kconfig.defconfig | 8 - boards/arm/atsamd20_xpro/atsamd20_xpro.dts | 116 -- boards/arm/atsamd20_xpro/atsamd20_xpro.yaml | 19 - .../arm/atsamd20_xpro/atsamd20_xpro_defconfig | 14 - boards/arm/atsamd20_xpro/doc/index.rst | 161 --- boards/arm/atsamd21_xpro/Kconfig.board | 8 - boards/arm/atsamd21_xpro/Kconfig.defconfig | 8 - boards/arm/atsamd21_xpro/atsamd21_xpro.dts | 134 -- boards/arm/atsamd21_xpro/atsamd21_xpro.yaml | 25 - .../arm/atsamd21_xpro/atsamd21_xpro_defconfig | 15 - boards/arm/atsamd21_xpro/doc/index.rst | 202 ---- boards/arm/atsame54_xpro/Kconfig.board | 8 - boards/arm/atsame54_xpro/Kconfig.defconfig | 34 - boards/arm/atsame54_xpro/atsame54_xpro.dts | 158 --- boards/arm/atsame54_xpro/atsame54_xpro.yaml | 23 - .../arm/atsame54_xpro/atsame54_xpro_defconfig | 18 - boards/arm/atsame54_xpro/doc/index.rst | 230 ---- boards/arm/atsaml21_xpro/Kconfig.board | 8 - boards/arm/atsaml21_xpro/Kconfig.defconfig | 8 - boards/arm/atsaml21_xpro/atsaml21_xpro.dts | 147 --- boards/arm/atsaml21_xpro/atsaml21_xpro.yaml | 25 - .../arm/atsaml21_xpro/atsaml21_xpro_defconfig | 15 - boards/arm/atsaml21_xpro/doc/index.rst | 198 --- boards/arm/atsamr21_xpro/Kconfig.board | 8 - boards/arm/atsamr21_xpro/Kconfig.defconfig | 11 - boards/arm/atsamr21_xpro/atsamr21_xpro.dts | 227 ---- boards/arm/atsamr21_xpro/atsamr21_xpro.yaml | 28 - .../arm/atsamr21_xpro/atsamr21_xpro_defconfig | 16 - boards/arm/atsamr21_xpro/doc/index.rst | 225 ---- boards/arm/atsamr34_xpro/Kconfig.board | 8 - boards/arm/atsamr34_xpro/Kconfig.defconfig | 8 - boards/arm/atsamr34_xpro/atsamr34_xpro.dts | 127 -- boards/arm/atsamr34_xpro/atsamr34_xpro.yaml | 25 - .../arm/atsamr34_xpro/atsamr34_xpro_defconfig | 15 - boards/arm/atsamr34_xpro/doc/index.rst | 218 ---- boards/arm/az3166_iotdevkit/Kconfig.board | 8 - boards/arm/az3166_iotdevkit/Kconfig.defconfig | 15 - boards/arm/b_g474e_dpow1/Kconfig.board | 8 - boards/arm/b_g474e_dpow1/Kconfig.defconfig | 11 - boards/arm/b_g474e_dpow1/doc/index.rst | 159 --- boards/arm/b_l072z_lrwan1/Kconfig.board | 8 - boards/arm/b_l072z_lrwan1/Kconfig.defconfig | 11 - .../b_l072z_lrwan1/b_l072z_lrwan1_defconfig | 27 - boards/arm/b_l072z_lrwan1/doc/index.rst | 250 ---- boards/arm/b_l4s5i_iot01a/Kconfig.board | 8 - boards/arm/b_l4s5i_iot01a/Kconfig.defconfig | 47 - boards/arm/b_l4s5i_iot01a/doc/index.rst | 233 ---- boards/arm/b_u585i_iot02a/Kconfig.board | 8 - boards/arm/b_u585i_iot02a/Kconfig.defconfig | 38 - .../arm/b_u585i_iot02a/b_u585i_iot02a_ns.yaml | 11 - .../b_u585i_iot02a_ns_defconfig | 24 - boards/arm/b_u585i_iot02a/doc/index.rst | 439 ------- boards/arm/bbc_microbit/Kconfig.board | 8 - boards/arm/bbc_microbit/Kconfig.defconfig | 22 - .../arm/bbc_microbit/bbc_microbit_defconfig | 19 - boards/arm/bbc_microbit_v2/Kconfig.board | 8 - boards/arm/bbc_microbit_v2/Kconfig.defconfig | 14 - .../bbc_microbit_v2/bbc_microbit_v2_defconfig | 19 - boards/arm/bcm958401m2/Kconfig.board | 8 - boards/arm/bcm958401m2/Kconfig.defconfig | 7 - boards/arm/bcm958401m2/bcm958401m2_defconfig | 12 - boards/arm/bcm958401m2/doc/index.rst | 58 - boards/arm/bcm958402m2_m7/Kconfig.board | 6 - boards/arm/bcm958402m2_m7/Kconfig.defconfig | 6 - boards/arm/bcm958402m2_m7/bcm958402m2_m7.yaml | 8 - .../bcm958402m2_m7/bcm958402m2_m7_defconfig | 28 - boards/arm/bcm958402m2_m7/doc/index.rst | 51 - boards/arm/beagle_bcf/Kconfig.board | 21 - boards/arm/beagle_bcf/Kconfig.defconfig | 12 - boards/arm/bl5340_dvk/CMakeLists.txt | 16 - boards/arm/bl5340_dvk/Kconfig | 62 - boards/arm/bl5340_dvk/Kconfig.board | 18 - boards/arm/bl5340_dvk/Kconfig.defconfig | 131 -- boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts | 27 - boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.yaml | 22 - .../bl5340_dvk/bl5340_dvk_cpuapp_common.dtsi | 381 ------ .../bl5340_dvk/bl5340_dvk_cpuapp_defconfig | 30 - .../arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.dts | 25 - .../arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.yaml | 21 - .../bl5340_dvk/bl5340_dvk_cpuapp_ns_defconfig | 27 - .../bl5340_dvk_cpuapp_partition_conf.dtsi | 61 - boards/arm/bl5340_dvk/bl5340_dvk_cpunet.dts | 39 - boards/arm/bl5340_dvk/bl5340_dvk_cpunet.yaml | 18 - .../bl5340_dvk/bl5340_dvk_cpunet_common.dtsi | 67 - .../bl5340_dvk/bl5340_dvk_cpunet_defconfig | 21 - boards/arm/bl5340_dvk/board.cmake | 22 - boards/arm/bl5340_dvk/doc/index.rst | 436 ------- boards/arm/bl652_dvk/Kconfig.board | 8 - boards/arm/bl652_dvk/Kconfig.defconfig | 21 - boards/arm/bl653_dvk/Kconfig.board | 8 - boards/arm/bl653_dvk/Kconfig.defconfig | 21 - boards/arm/bl654_dvk/Kconfig.board | 8 - boards/arm/bl654_dvk/Kconfig.defconfig | 21 - boards/arm/bl654_sensor_board/Kconfig.board | 8 - .../arm/bl654_sensor_board/Kconfig.defconfig | 14 - boards/arm/bl654_usb/Kconfig.board | 8 - boards/arm/bl654_usb/Kconfig.defconfig | 62 - boards/arm/black_f407ve/Kconfig.board | 8 - boards/arm/black_f407ve/Kconfig.defconfig | 15 - boards/arm/black_f407ve/doc/index.rst | 244 ---- boards/arm/black_f407zg_pro/Kconfig.board | 8 - boards/arm/black_f407zg_pro/Kconfig.defconfig | 15 - boards/arm/black_f407zg_pro/doc/index.rst | 217 ---- boards/arm/blackpill_f401cc/Kconfig.board | 8 - boards/arm/blackpill_f401cc/Kconfig.defconfig | 15 - boards/arm/blackpill_f401cc/doc/index.rst | 174 --- boards/arm/blackpill_f401ce/Kconfig.board | 8 - boards/arm/blackpill_f401ce/Kconfig.defconfig | 15 - boards/arm/blackpill_f401ce/doc/index.rst | 179 --- boards/arm/blackpill_f411ce/Kconfig.board | 8 - boards/arm/blackpill_f411ce/Kconfig.defconfig | 15 - boards/arm/blackpill_f411ce/doc/index.rst | 179 --- .../Kconfig.board | 8 - .../Kconfig.defconfig | 17 - .../doc/index.rst | 153 --- boards/arm/bt510/Kconfig.board | 8 - boards/arm/bt510/Kconfig.defconfig | 17 - boards/arm/bt610/Kconfig.board | 8 - boards/arm/bt610/Kconfig.defconfig | 17 - boards/arm/cc1352p1_launchxl/CMakeLists.txt | 6 - boards/arm/cc1352p1_launchxl/Kconfig.board | 20 - .../arm/cc1352p1_launchxl/Kconfig.defconfig | 11 - boards/arm/cc1352r1_launchxl/Kconfig.board | 8 - .../arm/cc1352r1_launchxl/Kconfig.defconfig | 11 - boards/arm/cc1352r_sensortag/Kconfig.board | 9 - .../arm/cc1352r_sensortag/Kconfig.defconfig | 15 - boards/arm/cc26x2r1_launchxl/Kconfig.board | 8 - .../arm/cc26x2r1_launchxl/Kconfig.defconfig | 11 - boards/arm/cc3220sf_launchxl/Kconfig.board | 7 - .../arm/cc3220sf_launchxl/Kconfig.defconfig | 10 - .../cc3220sf_launchxl_defconfig | 17 - boards/arm/cc3220sf_launchxl/doc/index.rst | 325 ----- boards/arm/cc3235sf_launchxl/CMakeLists.txt | 4 - boards/arm/cc3235sf_launchxl/Kconfig.board | 8 - .../arm/cc3235sf_launchxl/Kconfig.defconfig | 11 - .../cc3235sf_launchxl_defconfig | 17 - boards/arm/cc3235sf_launchxl/doc/index.rst | 325 ----- .../arm/circuitdojo_feather_nrf9160/Kconfig | 5 - .../circuitdojo_feather_nrf9160/Kconfig.board | 15 - .../Kconfig.defconfig | 39 - .../circuitdojo_feather_nrf9160_defconfig | 27 - .../circuitdojo_feather_nrf9160_ns_defconfig | 30 - .../circuitdojo_feather_nrf9160/doc/index.rst | 161 --- boards/arm/colibri_imx7d_m4/Kconfig.board | 9 - boards/arm/colibri_imx7d_m4/Kconfig.defconfig | 19 - .../arm/colibri_imx7d_m4/colibri_imx7d_m4.dts | 107 -- .../colibri_imx7d_m4/colibri_imx7d_m4.yaml | 23 - .../colibri_imx7d_m4_defconfig | 15 - boards/arm/colibri_imx7d_m4/doc/index.rst | 324 ----- boards/arm/contextualelectronics_abc/Kconfig | 10 - .../contextualelectronics_abc/Kconfig.board | 8 - .../Kconfig.defconfig | 14 - .../arm/contextualelectronics_abc/board.cmake | 9 - boards/arm/cy8ckit_062_ble/Kconfig.board | 13 - boards/arm/cy8ckit_062_ble/Kconfig.defconfig | 15 - boards/arm/cy8ckit_062_ble/board.cmake | 16 - .../cy8ckit_062_ble/cy8ckit_062_ble_m0.yaml | 23 - .../cy8ckit_062_ble_m0_0_0_0.conf | 5 - .../cy8ckit_062_ble_m0_1_0_0.conf | 5 - .../cy8ckit_062_ble_m0_defconfig | 17 - .../cy8ckit_062_ble/cy8ckit_062_ble_m4.yaml | 21 - .../cy8ckit_062_ble_m4_0_0_0.conf | 5 - .../cy8ckit_062_ble_m4_defconfig | 17 - boards/arm/cy8ckit_062_ble/doc/index.rst | 305 ----- boards/arm/cy8ckit_062_ble/revision.cmake | 7 - boards/arm/cy8ckit_062_wifi_bt/Kconfig.board | 13 - .../arm/cy8ckit_062_wifi_bt/Kconfig.defconfig | 14 - .../cy8ckit_062_wifi_bt_m0.yaml | 19 - .../cy8ckit_062_wifi_bt_m0_defconfig | 16 - .../cy8ckit_062_wifi_bt_m4.yaml | 19 - .../cy8ckit_062_wifi_bt_m4_defconfig | 16 - boards/arm/cy8ckit_062_wifi_bt/doc/index.rst | 208 ---- boards/arm/cy8ckit_062s4/Kconfig.board | 6 - boards/arm/cy8ckit_062s4/Kconfig.defconfig | 10 - .../arm/cy8ckit_062s4/cy8ckit_062s4_m4.yaml | 15 - .../cy8ckit_062s4/cy8ckit_062s4_m4_defconfig | 16 - boards/arm/cy8ckit_062s4/doc/index.rst | 115 -- boards/arm/cy8cproto_062_4343w/Kconfig.board | 7 - .../arm/cy8cproto_062_4343w/Kconfig.defconfig | 57 - boards/arm/cy8cproto_062_4343w/doc/index.rst | 184 --- boards/arm/cy8cproto_063_ble/Kconfig.board | 8 - .../arm/cy8cproto_063_ble/Kconfig.defconfig | 16 - boards/arm/cy8cproto_063_ble/doc/index.rst | 145 --- boards/arm/cyclonev_socdk/Kconfig.board | 8 - boards/arm/cyclonev_socdk/Kconfig.defconfig | 33 - boards/arm/cyclonev_socdk/board.cmake | 22 - .../cyclonev_socdk/cyclonev_socdk_defconfig | 26 - boards/arm/cyclonev_socdk/doc/index.rst | 359 ------ .../cyclonev_socdk/support/download_all.gdb | 18 - .../support/preloader_dl_cmd.txt | 9 - boards/arm/da14695_dk_usb/Kconfig | 4 - boards/arm/da14695_dk_usb/Kconfig.board | 8 - boards/arm/da14695_dk_usb/Kconfig.defconfig | 11 - boards/arm/da1469x_dk_pro/Kconfig | 4 - boards/arm/da1469x_dk_pro/Kconfig.board | 8 - boards/arm/da1469x_dk_pro/Kconfig.defconfig | 11 - .../da1469x_dk_pro/da1469x_dk_pro_defconfig | 18 - boards/arm/decawave_dwm1001_dev/Kconfig.board | 8 - .../decawave_dwm1001_dev/Kconfig.defconfig | 21 - .../decawave_dwm1001_dev_defconfig | 22 - boards/arm/degu_evk/Kconfig.board | 8 - boards/arm/degu_evk/Kconfig.defconfig | 36 - boards/arm/degu_evk/degu_evk_defconfig | 22 - boards/arm/disco_l475_iot1/Kconfig.board | 8 - boards/arm/disco_l475_iot1/Kconfig.defconfig | 47 - boards/arm/disco_l475_iot1/doc/index.rst | 248 ---- boards/arm/dragino_lsn50/Kconfig.board | 8 - boards/arm/dragino_lsn50/Kconfig.defconfig | 11 - boards/arm/dragino_lsn50/doc/index.rst | 194 --- .../arm/dragino_lsn50/dragino_lsn50_defconfig | 24 - boards/arm/dragino_nbsn95/Kconfig.board | 8 - boards/arm/dragino_nbsn95/Kconfig.defconfig | 11 - boards/arm/dragino_nbsn95/doc/index.rst | 193 --- .../dragino_nbsn95/dragino_nbsn95_defconfig | 25 - .../arm/ebyte_e73_tbb_nrf52832/Kconfig.board | 8 - .../ebyte_e73_tbb_nrf52832/Kconfig.defconfig | 15 - .../arm/ebyte_e73_tbb_nrf52832/doc/index.rst | 222 ---- boards/arm/efm32gg_sltb009a/Kconfig.board | 8 - boards/arm/efm32gg_sltb009a/Kconfig.defconfig | 24 - boards/arm/efm32gg_sltb009a/doc/index.rst | 167 --- boards/arm/efm32gg_slwstk6121a/Kconfig.board | 10 - .../arm/efm32gg_slwstk6121a/Kconfig.defconfig | 33 - boards/arm/efm32gg_slwstk6121a/doc/index.rst | 187 --- boards/arm/efm32gg_stk3701a/Kconfig.board | 9 - boards/arm/efm32gg_stk3701a/Kconfig.defconfig | 32 - boards/arm/efm32gg_stk3701a/doc/index.rst | 201 --- boards/arm/efm32hg_slstk3400a/Kconfig.board | 9 - .../arm/efm32hg_slstk3400a/Kconfig.defconfig | 17 - boards/arm/efm32hg_slstk3400a/doc/index.rst | 176 --- boards/arm/efm32pg_stk3401a/Kconfig.board | 9 - boards/arm/efm32pg_stk3401a/Kconfig.defconfig | 17 - boards/arm/efm32pg_stk3401a/doc/index.rst | 189 --- boards/arm/efm32pg_stk3402a/Kconfig.board | 15 - boards/arm/efm32pg_stk3402a/Kconfig.defconfig | 19 - boards/arm/efm32pg_stk3402a/doc/index.rst | 215 ---- .../efm32pg_stk3402a/efm32pg_stk3402a.yaml | 20 - .../efm32pg_stk3402a_defconfig | 11 - .../efm32pg_stk3402a/efm32pg_stk3402a_jg.yaml | 19 - .../efm32pg_stk3402a_jg_defconfig | 11 - boards/arm/efm32wg_stk3800/Kconfig.board | 9 - boards/arm/efm32wg_stk3800/Kconfig.defconfig | 17 - boards/arm/efm32wg_stk3800/doc/index.rst | 178 --- boards/arm/efr32_radio/Kconfig | 7 - boards/arm/efr32_radio/Kconfig.board | 48 - boards/arm/efr32_radio/Kconfig.defconfig | 60 - boards/arm/efr32_radio/board.cmake | 22 - .../arm/efr32_radio/efr32_radio_brd4104a.yaml | 22 - .../efr32_radio_brd4104a_defconfig | 13 - .../arm/efr32_radio/efr32_radio_brd4161a.yaml | 21 - .../efr32_radio_brd4161a_defconfig | 13 - .../arm/efr32_radio/efr32_radio_brd4170a.yaml | 21 - .../efr32_radio_brd4170a_defconfig | 13 - .../arm/efr32_radio/efr32_radio_brd4180a.dts | 147 --- .../arm/efr32_radio/efr32_radio_brd4180a.yaml | 21 - .../efr32_radio_brd4180a_defconfig | 12 - .../arm/efr32_radio/efr32_radio_brd4187c.dts | 156 --- .../arm/efr32_radio/efr32_radio_brd4187c.yaml | 21 - .../efr32_radio_brd4187c_defconfig | 18 - .../arm/efr32_radio/efr32_radio_brd4250b.yaml | 22 - .../efr32_radio_brd4250b_defconfig | 13 - .../arm/efr32_radio/efr32_radio_brd4255a.yaml | 22 - .../efr32_radio_brd4255a_defconfig | 13 - boards/arm/efr32_thunderboard/Kconfig.board | 19 - .../arm/efr32_thunderboard/Kconfig.defconfig | 59 - boards/arm/efr32_thunderboard/board.cmake | 11 - boards/arm/efr32mg_sltb004a/Kconfig.board | 9 - boards/arm/efr32mg_sltb004a/Kconfig.defconfig | 17 - boards/arm/efr32mg_sltb004a/doc/index.rst | 220 ---- boards/arm/efr32xg24_dk2601b/Kconfig.board | 9 - .../arm/efr32xg24_dk2601b/Kconfig.defconfig | 45 - boards/arm/efr32xg24_dk2601b/doc/index.rst | 185 --- boards/arm/ev11l78a/Kconfig.board | 8 - boards/arm/ev11l78a/Kconfig.defconfig | 8 - boards/arm/ev11l78a/doc/index.rst | 105 -- boards/arm/ev11l78a/ev11l78a_defconfig | 26 - boards/arm/faze/Kconfig.board | 9 - boards/arm/faze/Kconfig.defconfig | 11 - boards/arm/fk7b0m1_vbt6/Kconfig.board | 8 - boards/arm/fk7b0m1_vbt6/Kconfig.defconfig | 11 - boards/arm/fk7b0m1_vbt6/doc/index.rst | 179 --- boards/arm/frdm_k22f/Kconfig.board | 9 - boards/arm/frdm_k22f/Kconfig.defconfig | 23 - boards/arm/frdm_k22f/doc/index.rst | 298 ----- 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- .../mimxrt1170_evkb_cm7_defconfig | 17 - boards/arm/mimxrt595_evk/CMakeLists.txt | 30 - boards/arm/mimxrt595_evk/Kconfig | 8 - boards/arm/mimxrt595_evk/Kconfig.board | 9 - boards/arm/mimxrt595_evk/Kconfig.defconfig | 42 - boards/arm/mimxrt595_evk/doc/index.rst | 334 ----- .../arm/mimxrt595_evk/mimxrt595_evk_cm33.dts | 512 -------- .../arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml | 32 - .../mimxrt595_evk_cm33_defconfig | 19 - boards/arm/mimxrt685_evk/CMakeLists.txt | 25 - boards/arm/mimxrt685_evk/Kconfig.board | 8 - boards/arm/mimxrt685_evk/Kconfig.defconfig | 29 - boards/arm/mimxrt685_evk/doc/index.rst | 370 ------ .../arm/mimxrt685_evk/mimxrt685_evk_cm33.dts | 387 ------ .../arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml | 34 - .../mimxrt685_evk_cm33_defconfig | 20 - boards/arm/mm_feather/CMakeLists.txt | 13 - boards/arm/mm_feather/Kconfig.board | 10 - boards/arm/mm_feather/Kconfig.defconfig | 25 - boards/arm/mm_feather/flexspi_nor_config.c | 43 - boards/arm/mm_swiftio/CMakeLists.txt | 13 - boards/arm/mm_swiftio/Kconfig.board | 10 - boards/arm/mm_swiftio/Kconfig.defconfig | 25 - boards/arm/mm_swiftio/flexspi_nor_config.c | 43 - boards/arm/mps2/CMakeLists.txt | 23 + boards/arm/mps2/Kconfig | 6 + boards/arm/mps2/Kconfig.defconfig | 60 + boards/arm/mps2/Kconfig.mps2 | 8 + boards/arm/mps2/board.cmake | 43 + boards/arm/mps2/board.yml | 9 + .../doc/img/mps2_an385.jpg | Bin .../doc/img/mps2_an521.jpg | Bin boards/arm/mps2/doc/mps2_an385.rst | 281 +++++ boards/arm/mps2/doc/mps2_an521.rst | 574 +++++++++ .../empty_cpu0/CMakeLists.txt | 0 .../{mps2_an521 => mps2}/empty_cpu0/prj.conf | 0 .../empty_cpu0/src/main.c | 0 .../arm/{mps2_an385 => mps2}/mps2_an385.dts | 0 .../arm/{mps2_an385 => mps2}/mps2_an385.yaml | 2 +- .../{mps2_an385 => mps2}/mps2_an385_defconfig | 3 - .../mps2_an521-common.dtsi | 0 .../mps2_an521_cpu0.dts} | 0 boards/arm/mps2/mps2_an521_cpu0.yaml | 21 + boards/arm/mps2/mps2_an521_cpu0_defconfig | 21 + .../mps2_an521_cpu0_ns.dts} | 0 boards/arm/mps2/mps2_an521_cpu0_ns.yaml | 19 + boards/arm/mps2/mps2_an521_cpu0_ns_defconfig | 11 + .../mps2_an521_cpu1.dts} | 0 boards/arm/mps2/mps2_an521_cpu1.yaml | 16 + boards/arm/mps2/mps2_an521_cpu1_defconfig | 18 + boards/arm/{mps2_an385 => mps2}/pinmux.c | 0 boards/arm/mps2_an385/CMakeLists.txt | 4 - boards/arm/mps2_an385/Kconfig.board | 8 - boards/arm/mps2_an385/Kconfig.defconfig | 38 - boards/arm/mps2_an385/board.cmake | 13 - boards/arm/mps2_an385/doc/index.rst | 284 ----- boards/arm/mps2_an521/CMakeLists.txt | 29 - boards/arm/mps2_an521/Kconfig.board | 20 - boards/arm/mps2_an521/Kconfig.defconfig | 32 - boards/arm/mps2_an521/board.cmake | 33 - boards/arm/mps2_an521/doc/index.rst | 574 --------- boards/arm/mps2_an521/mps2_an521.yaml | 21 - boards/arm/mps2_an521/mps2_an521_defconfig | 24 - boards/arm/mps2_an521/mps2_an521_ns.yaml | 19 - boards/arm/mps2_an521/mps2_an521_ns_defconfig | 22 - boards/arm/mps2_an521/mps2_an521_remote.yaml | 16 - .../mps2_an521/mps2_an521_remote_defconfig | 21 - boards/arm/mps2_an521/pinmux.c | 164 --- boards/arm/mps3/Kconfig | 5 + boards/arm/mps3/Kconfig.defconfig | 21 + boards/arm/mps3/Kconfig.mps3 | 7 + boards/arm/{mps3_an547 => mps3}/board.cmake | 0 boards/arm/mps3/board.yml | 7 + .../doc/img/mps3_an547.jpg | Bin boards/arm/mps3/doc/index.rst | 245 ++++ .../mps3_an547-common.dtsi | 0 .../arm/{mps3_an547 => mps3}/mps3_an547.dts | 0 .../arm/{mps3_an547 => mps3}/mps3_an547.yaml | 2 +- .../{mps3_an547 => mps3}/mps3_an547_defconfig | 3 - .../{mps3_an547 => mps3}/mps3_an547_ns.dts | 0 .../{mps3_an547 => mps3}/mps3_an547_ns.yaml | 2 +- .../mps3_an547_ns_defconfig | 8 +- boards/arm/mps3_an547/Kconfig.board | 7 - boards/arm/mps3_an547/Kconfig.defconfig | 24 - boards/arm/mps3_an547/doc/index.rst | 245 ---- boards/arm/mr_canhubk3/Kconfig.board | 7 - boards/arm/mr_canhubk3/Kconfig.defconfig | 46 - boards/arm/mr_canhubk3/doc/index.rst | 339 ------ boards/arm/msp_exp432p401r_launchxl/Kconfig | 7 - .../msp_exp432p401r_launchxl/Kconfig.board | 7 - .../Kconfig.defconfig | 7 - .../arm/msp_exp432p401r_launchxl/board.cmake | 3 - .../msp_exp432p401r_launchxl/doc/index.rst | 152 --- .../msp_exp432p401r_launchxl_defconfig | 16 - boards/arm/npcx4m8f_evb/Kconfig.board | 6 - boards/arm/npcx4m8f_evb/Kconfig.defconfig | 15 - boards/arm/npcx4m8f_evb/doc/index.rst | 131 -- boards/arm/npcx7m6fb_evb/Kconfig.board | 6 - boards/arm/npcx7m6fb_evb/Kconfig.defconfig | 15 - boards/arm/npcx7m6fb_evb/doc/index.rst | 107 -- boards/arm/npcx9m6f_evb/Kconfig.board | 6 - boards/arm/npcx9m6f_evb/Kconfig.defconfig | 15 - boards/arm/npcx9m6f_evb/doc/index.rst | 121 -- boards/arm/nrf21540dk_nrf52840/Kconfig | 10 - boards/arm/nrf21540dk_nrf52840/Kconfig.board | 8 - .../arm/nrf21540dk_nrf52840/Kconfig.defconfig | 14 - boards/arm/nrf21540dk_nrf52840/doc/index.rst | 236 ---- boards/arm/nrf51_ble400/Kconfig.board | 8 - boards/arm/nrf51_ble400/Kconfig.defconfig | 14 - boards/arm/nrf51_ble400/doc/index.rst | 223 ---- .../arm/nrf51_ble400/nrf51_ble400_defconfig | 15 - boards/arm/nrf51_blenano/Kconfig.board | 8 - boards/arm/nrf51_blenano/Kconfig.defconfig | 14 - .../arm/nrf51_blenano/nrf51_blenano_defconfig | 15 - boards/arm/nrf51_vbluno51/Kconfig.board | 8 - boards/arm/nrf51_vbluno51/Kconfig.defconfig | 14 - .../nrf51_vbluno51/nrf51_vbluno51_defconfig | 15 - boards/arm/nrf51dk_nrf51422/Kconfig.board | 8 - boards/arm/nrf51dk_nrf51422/Kconfig.defconfig | 14 - boards/arm/nrf51dk_nrf51422/doc/index.rst | 159 --- .../arm/nrf51dk_nrf51422/nrf51dk_nrf51422.dts | 177 --- .../nrf51dk_nrf51422/nrf51dk_nrf51422.yaml | 24 - .../nrf51dk_nrf51422_defconfig | 15 - boards/arm/nrf51dongle_nrf51422/Kconfig.board | 8 - .../nrf51dongle_nrf51422/Kconfig.defconfig | 14 - boards/arm/nrf51dongle_nrf51422/doc/index.rst | 144 --- .../nrf51dongle_nrf51422.dts | 109 -- .../nrf51dongle_nrf51422.yaml | 14 - .../nrf51dongle_nrf51422_defconfig | 15 - boards/arm/nrf52832_mdk/Kconfig.board | 8 - boards/arm/nrf52832_mdk/Kconfig.defconfig | 14 - .../arm/nrf52832_mdk/nrf52832_mdk_defconfig | 18 - boards/arm/nrf52833dk_nrf52820/CMakeLists.txt | 7 - boards/arm/nrf52833dk_nrf52820/Kconfig | 10 - boards/arm/nrf52833dk_nrf52820/Kconfig.board | 8 - .../arm/nrf52833dk_nrf52820/Kconfig.defconfig | 14 - boards/arm/nrf52833dk_nrf52820/board.cmake | 9 - boards/arm/nrf52833dk_nrf52820/doc/index.rst | 23 - boards/arm/nrf52833dk_nrf52833/Kconfig | 10 - boards/arm/nrf52833dk_nrf52833/Kconfig.board | 8 - .../arm/nrf52833dk_nrf52833/Kconfig.defconfig | 14 - boards/arm/nrf52833dk_nrf52833/doc/index.rst | 217 ---- boards/arm/nrf52840_blip/Kconfig.board | 8 - boards/arm/nrf52840_blip/Kconfig.defconfig | 14 - boards/arm/nrf52840_blip/doc/index.rst | 196 --- .../arm/nrf52840_blip/nrf52840_blip_defconfig | 18 - boards/arm/nrf52840_mdk/Kconfig.board | 8 - boards/arm/nrf52840_mdk/Kconfig.defconfig | 14 - .../arm/nrf52840_mdk/nrf52840_mdk_defconfig | 18 - .../arm/nrf52840_mdk_usb_dongle/Kconfig.board | 9 - .../nrf52840_mdk_usb_dongle/Kconfig.defconfig | 40 - .../nrf52840_mdk_usb_dongle_defconfig | 19 - boards/arm/nrf52840_papyr/Kconfig.board | 8 - boards/arm/nrf52840_papyr/Kconfig.defconfig | 14 - .../nrf52840_papyr/nrf52840_papyr_defconfig | 18 - boards/arm/nrf52840dk_nrf52811/CMakeLists.txt | 9 - boards/arm/nrf52840dk_nrf52811/Kconfig | 10 - boards/arm/nrf52840dk_nrf52811/Kconfig.board | 8 - .../arm/nrf52840dk_nrf52811/Kconfig.defconfig | 14 - boards/arm/nrf52840dk_nrf52811/board.cmake | 9 - boards/arm/nrf52840dk_nrf52811/doc/index.rst | 24 - boards/arm/nrf52840dk_nrf52840/Kconfig | 18 - boards/arm/nrf52840dk_nrf52840/Kconfig.board | 8 - .../arm/nrf52840dk_nrf52840/Kconfig.defconfig | 14 - boards/arm/nrf52840dk_nrf52840/doc/index.rst | 224 ---- boards/arm/nrf52840dongle_nrf52840/Kconfig | 29 - .../arm/nrf52840dongle_nrf52840/Kconfig.board | 8 - .../nrf52840dongle_nrf52840/Kconfig.defconfig | 86 -- .../arm/nrf52840dongle_nrf52840/doc/index.rst | 348 ------ .../arm/nrf52_adafruit_feather/Kconfig.board | 8 - .../nrf52_adafruit_feather/Kconfig.defconfig | 14 - .../arm/nrf52_adafruit_feather/doc/index.rst | 192 --- .../nrf52_adafruit_feather_defconfig | 18 - boards/arm/nrf52_blenano2/Kconfig.board | 8 - boards/arm/nrf52_blenano2/Kconfig.defconfig | 14 - .../nrf52_blenano2/nrf52_blenano2_defconfig | 18 - boards/arm/nrf52_sparkfun/Kconfig.board | 9 - boards/arm/nrf52_sparkfun/Kconfig.defconfig | 15 - .../nrf52_sparkfun/nrf52_sparkfun_defconfig | 18 - boards/arm/nrf52_vbluno52/Kconfig | 8 - boards/arm/nrf52_vbluno52/Kconfig.board | 8 - boards/arm/nrf52_vbluno52/Kconfig.defconfig | 14 - .../nrf52_vbluno52/nrf52_vbluno52_defconfig | 18 - boards/arm/nrf52dk_nrf52805/CMakeLists.txt | 7 - boards/arm/nrf52dk_nrf52805/Kconfig | 10 - boards/arm/nrf52dk_nrf52805/Kconfig.board | 8 - boards/arm/nrf52dk_nrf52805/Kconfig.defconfig | 14 - boards/arm/nrf52dk_nrf52805/board.cmake | 7 - boards/arm/nrf52dk_nrf52805/doc/index.rst | 23 - boards/arm/nrf52dk_nrf52810/CMakeLists.txt | 7 - boards/arm/nrf52dk_nrf52810/Kconfig | 18 - boards/arm/nrf52dk_nrf52810/Kconfig.board | 8 - boards/arm/nrf52dk_nrf52810/Kconfig.defconfig | 11 - boards/arm/nrf52dk_nrf52810/board.cmake | 7 - boards/arm/nrf52dk_nrf52810/doc/index.rst | 24 - boards/arm/nrf52dk_nrf52832/Kconfig | 10 - boards/arm/nrf52dk_nrf52832/Kconfig.board | 8 - boards/arm/nrf52dk_nrf52832/Kconfig.defconfig | 14 - boards/arm/nrf52dk_nrf52832/doc/index.rst | 406 ------- .../nrf5340_audio_dk_nrf5340/CMakeLists.txt | 15 - boards/arm/nrf5340_audio_dk_nrf5340/Kconfig | 58 - .../nrf5340_audio_dk_nrf5340/Kconfig.board | 18 - .../Kconfig.defconfig | 87 -- .../arm/nrf5340_audio_dk_nrf5340/board.cmake | 17 - .../nrf5340_audio_dk_nrf5340/doc/index.rst | 109 -- .../nrf5340_audio_dk_nrf5340_cpuapp_defconfig | 21 - ...f5340_audio_dk_nrf5340_cpuapp_ns_defconfig | 22 - .../nrf5340_audio_dk_nrf5340_cpunet_defconfig | 21 - boards/arm/nrf5340dk_nrf5340/Kconfig | 58 - boards/arm/nrf5340dk_nrf5340/Kconfig.board | 18 - .../arm/nrf5340dk_nrf5340/Kconfig.defconfig | 84 -- boards/arm/nrf5340dk_nrf5340/doc/index.rst | 330 ----- .../nrf5340dk_nrf5340_cpunet_defconfig | 21 - boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board | 10 - .../nrf54h20pdk_nrf54h20/Kconfig.defconfig | 14 - boards/arm/nrf54h20pdk_nrf54h20/doc/index.rst | 153 --- .../nrf54h20pdk_nrf54h20_cpuapp_defconfig | 33 - .../nrf54h20pdk_nrf54h20_cpurad_defconfig | 30 - boards/arm/nrf54l15pdk_nrf54l15/Kconfig.board | 6 - .../nrf54l15pdk_nrf54l15/Kconfig.defconfig | 12 - boards/arm/nrf54l15pdk_nrf54l15/doc/index.rst | 139 --- boards/arm/nrf9131ek_nrf9131/Kconfig.board | 14 - .../arm/nrf9131ek_nrf9131/Kconfig.defconfig | 38 - boards/arm/nrf9131ek_nrf9131/doc/index.rst | 229 ---- .../nrf9131ek_nrf9131_defconfig | 26 - .../nrf9131ek_nrf9131_ns_defconfig | 35 - boards/arm/nrf9151dk_nrf9151/Kconfig.board | 14 - .../arm/nrf9151dk_nrf9151/Kconfig.defconfig | 47 - boards/arm/nrf9151dk_nrf9151/doc/index.rst | 203 ---- .../nrf9151dk_nrf9151_defconfig | 24 - .../nrf9151dk_nrf9151_ns_defconfig | 27 - boards/arm/nrf9160_innblue21/Kconfig.board | 14 - .../arm/nrf9160_innblue21/Kconfig.defconfig | 48 - boards/arm/nrf9160_innblue21/doc/index.rst | 144 --- .../nrf9160_innblue21/nrf9160_innblue21.dts | 17 - .../nrf9160_innblue21/nrf9160_innblue21.yaml | 14 - .../nrf9160_innblue21_common.dtsi | 205 ---- .../nrf9160_innblue21_defconfig | 23 - .../nrf9160_innblue21_ns.dts | 17 - .../nrf9160_innblue21_ns.yaml | 14 - .../nrf9160_innblue21_ns_defconfig | 26 - boards/arm/nrf9160_innblue22/Kconfig.board | 14 - .../arm/nrf9160_innblue22/Kconfig.defconfig | 48 - boards/arm/nrf9160_innblue22/doc/index.rst | 144 --- .../nrf9160_innblue22/nrf9160_innblue22.dts | 17 - .../nrf9160_innblue22/nrf9160_innblue22.yaml | 14 - .../nrf9160_innblue22_common.dtsi | 209 ---- .../nrf9160_innblue22_defconfig | 23 - .../nrf9160_innblue22_ns.dts | 17 - .../nrf9160_innblue22_ns.yaml | 14 - .../nrf9160_innblue22_ns_defconfig | 26 - boards/arm/nrf9160dk_nrf52840/Kconfig | 17 - boards/arm/nrf9160dk_nrf52840/Kconfig.board | 12 - .../arm/nrf9160dk_nrf52840/Kconfig.defconfig | 17 - boards/arm/nrf9160dk_nrf52840/board.cmake | 7 - boards/arm/nrf9160dk_nrf52840/doc/index.rst | 266 ---- .../nrf9160dk_nrf52840.yaml | 14 - .../nrf9160dk_nrf52840_defconfig | 18 - boards/arm/nrf9160dk_nrf52840/revision.cmake | 8 - boards/arm/nrf9160dk_nrf9160/CMakeLists.txt | 5 - boards/arm/nrf9160dk_nrf9160/Kconfig.board | 14 - .../arm/nrf9160dk_nrf9160/Kconfig.defconfig | 47 - boards/arm/nrf9160dk_nrf9160/board.cmake | 14 - boards/arm/nrf9160dk_nrf9160/doc/index.rst | 264 ---- .../nordic,nrf9160dk-nrf52840-interface.yaml | 42 - .../nordic,nrf9160dk-nrf52840-reset.yaml | 21 - .../nrf9160dk_nrf9160/nrf9160dk_nrf9160.yaml | 22 - .../nrf9160dk_nrf9160_defconfig | 24 - .../nrf9160dk_nrf9160_ns.yaml | 21 - .../nrf9160dk_nrf9160_ns_defconfig | 27 - boards/arm/nrf9160dk_nrf9160/revision.cmake | 8 - boards/arm/nrf9161dk_nrf9161/Kconfig.board | 14 - .../arm/nrf9161dk_nrf9161/Kconfig.defconfig | 47 - boards/arm/nrf9161dk_nrf9161/doc/index.rst | 203 ---- .../nrf9161dk_nrf9161/nrf9161dk_nrf9161.yaml | 22 - .../nrf9161dk_nrf9161_defconfig | 24 - .../nrf9161dk_nrf9161_ns.yaml | 20 - .../nrf9161dk_nrf9161_ns_defconfig | 27 - .../arm/nrf9161dk_nrf9161/pre_dt_board.cmake | 7 - boards/arm/nrf9161dk_nrf9161/revision.cmake | 8 - boards/arm/nucleo_c031c6/Kconfig.board | 8 - boards/arm/nucleo_c031c6/Kconfig.defconfig | 11 - boards/arm/nucleo_c031c6/doc/index.rst | 151 --- .../arm/nucleo_c031c6/nucleo_c031c6_defconfig | 24 - boards/arm/nucleo_f030r8/Kconfig.board | 8 - boards/arm/nucleo_f030r8/Kconfig.defconfig | 11 - boards/arm/nucleo_f030r8/doc/index.rst | 217 ---- boards/arm/nucleo_f030r8/nucleo_f030r8_1.conf | 2 - boards/arm/nucleo_f030r8/nucleo_f030r8_2.conf | 2 - boards/arm/nucleo_f030r8/revision.cmake | 8 - boards/arm/nucleo_f031k6/Kconfig.board | 8 - boards/arm/nucleo_f031k6/Kconfig.defconfig | 11 - boards/arm/nucleo_f031k6/doc/index.rst | 155 --- boards/arm/nucleo_f042k6/Kconfig.board | 9 - boards/arm/nucleo_f042k6/Kconfig.defconfig | 12 - boards/arm/nucleo_f042k6/doc/index.rst | 155 --- .../arm/nucleo_f042k6/nucleo_f042k6_defconfig | 23 - boards/arm/nucleo_f070rb/Kconfig.board | 8 - boards/arm/nucleo_f070rb/Kconfig.defconfig | 15 - boards/arm/nucleo_f070rb/doc/index.rst | 180 --- .../arm/nucleo_f070rb/nucleo_f070rb_defconfig | 23 - boards/arm/nucleo_f091rc/Kconfig.board | 8 - boards/arm/nucleo_f091rc/Kconfig.defconfig | 15 - boards/arm/nucleo_f091rc/doc/index.rst | 197 --- .../arm/nucleo_f091rc/nucleo_f091rc_defconfig | 23 - boards/arm/nucleo_f103rb/Kconfig.board | 8 - boards/arm/nucleo_f103rb/Kconfig.defconfig | 11 - boards/arm/nucleo_f103rb/doc/index.rst | 190 --- boards/arm/nucleo_f207zg/Kconfig.board | 8 - boards/arm/nucleo_f207zg/Kconfig.defconfig | 18 - boards/arm/nucleo_f207zg/doc/index.rst | 206 ---- boards/arm/nucleo_f302r8/Kconfig.board | 8 - boards/arm/nucleo_f302r8/Kconfig.defconfig | 11 - boards/arm/nucleo_f302r8/doc/index.rst | 168 --- boards/arm/nucleo_f303k8/Kconfig.board | 9 - boards/arm/nucleo_f303k8/Kconfig.defconfig | 12 - boards/arm/nucleo_f303k8/doc/index.rst | 159 --- boards/arm/nucleo_f303re/Kconfig.board | 8 - boards/arm/nucleo_f303re/Kconfig.defconfig | 11 - boards/arm/nucleo_f303re/doc/index.rst | 162 --- boards/arm/nucleo_f334r8/Kconfig.board | 8 - boards/arm/nucleo_f334r8/Kconfig.defconfig | 15 - boards/arm/nucleo_f334r8/doc/index.rst | 179 --- .../arm/nucleo_f334r8/nucleo_f334r8_defconfig | 23 - boards/arm/nucleo_f401re/Kconfig.board | 8 - boards/arm/nucleo_f401re/Kconfig.defconfig | 16 - boards/arm/nucleo_f401re/doc/index.rst | 206 ---- boards/arm/nucleo_f410rb/Kconfig.board | 8 - boards/arm/nucleo_f410rb/Kconfig.defconfig | 15 - boards/arm/nucleo_f410rb/doc/index.rst | 212 ---- boards/arm/nucleo_f411re/Kconfig.board | 8 - boards/arm/nucleo_f411re/Kconfig.defconfig | 15 - boards/arm/nucleo_f411re/doc/index.rst | 200 --- boards/arm/nucleo_f412zg/Kconfig.board | 8 - boards/arm/nucleo_f412zg/Kconfig.defconfig | 21 - boards/arm/nucleo_f412zg/doc/index.rst | 172 --- boards/arm/nucleo_f413zh/Kconfig.board | 8 - boards/arm/nucleo_f413zh/Kconfig.defconfig | 21 - boards/arm/nucleo_f413zh/doc/index.rst | 174 --- boards/arm/nucleo_f429zi/Kconfig.board | 8 - boards/arm/nucleo_f429zi/Kconfig.defconfig | 18 - boards/arm/nucleo_f429zi/doc/index.rst | 217 ---- boards/arm/nucleo_f446re/Kconfig.board | 8 - boards/arm/nucleo_f446re/Kconfig.defconfig | 15 - boards/arm/nucleo_f446re/doc/index.rst | 226 ---- boards/arm/nucleo_f446ze/Kconfig.board | 8 - boards/arm/nucleo_f446ze/Kconfig.defconfig | 15 - boards/arm/nucleo_f446ze/doc/index.rst | 248 ---- boards/arm/nucleo_f722ze/Kconfig.board | 8 - boards/arm/nucleo_f722ze/Kconfig.defconfig | 15 - boards/arm/nucleo_f746zg/Kconfig.board | 8 - boards/arm/nucleo_f746zg/Kconfig.defconfig | 18 - boards/arm/nucleo_f746zg/doc/index.rst | 235 ---- boards/arm/nucleo_f756zg/Kconfig.board | 8 - boards/arm/nucleo_f756zg/Kconfig.defconfig | 18 - boards/arm/nucleo_f756zg/doc/index.rst | 218 ---- boards/arm/nucleo_f767zi/Kconfig.board | 8 - boards/arm/nucleo_f767zi/Kconfig.defconfig | 18 - boards/arm/nucleo_f767zi/doc/index.rst | 236 ---- boards/arm/nucleo_g031k8/Kconfig.board | 8 - boards/arm/nucleo_g031k8/Kconfig.defconfig | 15 - boards/arm/nucleo_g031k8/doc/index.rst | 168 --- boards/arm/nucleo_g070rb/Kconfig.board | 8 - boards/arm/nucleo_g070rb/Kconfig.defconfig | 11 - boards/arm/nucleo_g070rb/doc/index.rst | 191 --- boards/arm/nucleo_g071rb/Kconfig.board | 9 - boards/arm/nucleo_g071rb/Kconfig.defconfig | 12 - boards/arm/nucleo_g071rb/doc/index.rst | 198 --- boards/arm/nucleo_g0b1re/Kconfig.board | 8 - boards/arm/nucleo_g0b1re/Kconfig.defconfig | 11 - boards/arm/nucleo_g0b1re/doc/index.rst | 211 ---- boards/arm/nucleo_g431rb/Kconfig.board | 8 - boards/arm/nucleo_g431rb/Kconfig.defconfig | 15 - boards/arm/nucleo_g431rb/doc/index.rst | 263 ---- boards/arm/nucleo_g474re/Kconfig.board | 8 - boards/arm/nucleo_g474re/Kconfig.defconfig | 15 - boards/arm/nucleo_g474re/doc/index.rst | 255 ---- boards/arm/nucleo_h563zi/Kconfig.board | 8 - boards/arm/nucleo_h563zi/Kconfig.defconfig | 18 - boards/arm/nucleo_h563zi/doc/index.rst | 317 ----- boards/arm/nucleo_h723zg/Kconfig.board | 8 - boards/arm/nucleo_h723zg/Kconfig.defconfig | 22 - boards/arm/nucleo_h723zg/doc/index.rst | 248 ---- boards/arm/nucleo_h743zi/Kconfig.board | 8 - boards/arm/nucleo_h743zi/Kconfig.defconfig | 18 - boards/arm/nucleo_h743zi/doc/index.rst | 246 ---- boards/arm/nucleo_h745zi_q/Kconfig.board | 14 - boards/arm/nucleo_h745zi_q/Kconfig.defconfig | 19 - boards/arm/nucleo_h745zi_q/board.cmake | 11 - boards/arm/nucleo_h745zi_q/doc/index.rst | 290 ----- .../nucleo_h745zi_q/nucleo_h745zi_q_m4.yaml | 19 - .../nucleo_h745zi_q_m4_defconfig | 25 - .../nucleo_h745zi_q/nucleo_h745zi_q_m7.yaml | 20 - .../nucleo_h745zi_q_m7_defconfig | 32 - boards/arm/nucleo_h753zi/Kconfig.board | 8 - boards/arm/nucleo_h753zi/Kconfig.defconfig | 18 - boards/arm/nucleo_h753zi/doc/index.rst | 233 ---- boards/arm/nucleo_h7a3zi_q/Kconfig.board | 8 - boards/arm/nucleo_h7a3zi_q/Kconfig.defconfig | 15 - boards/arm/nucleo_h7a3zi_q/doc/index.rst | 206 ---- boards/arm/nucleo_l011k4/Kconfig.board | 8 - boards/arm/nucleo_l011k4/Kconfig.defconfig | 15 - boards/arm/nucleo_l011k4/doc/index.rst | 167 --- boards/arm/nucleo_l031k6/Kconfig.board | 8 - boards/arm/nucleo_l031k6/Kconfig.defconfig | 15 - boards/arm/nucleo_l031k6/doc/index.rst | 160 --- boards/arm/nucleo_l053r8/Kconfig.board | 8 - boards/arm/nucleo_l053r8/Kconfig.defconfig | 15 - boards/arm/nucleo_l053r8/doc/index.rst | 176 --- boards/arm/nucleo_l073rz/Kconfig.board | 8 - boards/arm/nucleo_l073rz/Kconfig.defconfig | 15 - boards/arm/nucleo_l073rz/doc/index.rst | 190 --- .../arm/nucleo_l073rz/nucleo_l073rz_defconfig | 26 - boards/arm/nucleo_l152re/Kconfig.board | 9 - boards/arm/nucleo_l152re/Kconfig.defconfig | 12 - boards/arm/nucleo_l152re/board.cmake | 3 - boards/arm/nucleo_l152re/doc/index.rst | 187 --- boards/arm/nucleo_l412rb_p/Kconfig.board | 8 - boards/arm/nucleo_l412rb_p/Kconfig.defconfig | 15 - boards/arm/nucleo_l412rb_p/doc/index.rst | 269 ----- boards/arm/nucleo_l432kc/Kconfig.board | 9 - boards/arm/nucleo_l432kc/Kconfig.defconfig | 16 - boards/arm/nucleo_l432kc/doc/index.rst | 229 ---- boards/arm/nucleo_l433rc_p/Kconfig.board | 8 - boards/arm/nucleo_l433rc_p/Kconfig.defconfig | 15 - boards/arm/nucleo_l433rc_p/doc/index.rst | 234 ---- boards/arm/nucleo_l452re/Kconfig.board | 13 - boards/arm/nucleo_l452re/Kconfig.defconfig | 17 - boards/arm/nucleo_l452re/doc/index.rst | 256 ---- boards/arm/nucleo_l452re/nucleo_l452re_p.yaml | 17 - .../nucleo_l452re/nucleo_l452re_p_defconfig | 26 - boards/arm/nucleo_l476rg/Kconfig.board | 9 - boards/arm/nucleo_l476rg/Kconfig.defconfig | 16 - boards/arm/nucleo_l476rg/doc/index.rst | 243 ---- boards/arm/nucleo_l496zg/Kconfig.board | 8 - boards/arm/nucleo_l496zg/Kconfig.defconfig | 15 - boards/arm/nucleo_l496zg/doc/index.rst | 244 ---- boards/arm/nucleo_l4a6zg/Kconfig.board | 8 - boards/arm/nucleo_l4a6zg/Kconfig.defconfig | 15 - boards/arm/nucleo_l4a6zg/doc/index.rst | 243 ---- boards/arm/nucleo_l4r5zi/Kconfig.board | 8 - boards/arm/nucleo_l4r5zi/Kconfig.defconfig | 25 - boards/arm/nucleo_l4r5zi/doc/index.rst | 275 ----- boards/arm/nucleo_l552ze_q/Kconfig.board | 8 - boards/arm/nucleo_l552ze_q/Kconfig.defconfig | 19 - .../nucleo_l552ze_q/nucleo_l552ze_q_ns.yaml | 13 - .../nucleo_l552ze_q_ns_defconfig | 27 - boards/arm/nucleo_u575zi_q/Kconfig.board | 8 - boards/arm/nucleo_u575zi_q/Kconfig.defconfig | 11 - boards/arm/nucleo_u575zi_q/doc/index.rst | 343 ------ boards/arm/nucleo_u5a5zj_q/Kconfig.board | 8 - boards/arm/nucleo_u5a5zj_q/Kconfig.defconfig | 11 - boards/arm/nucleo_u5a5zj_q/doc/index.rst | 377 ------ boards/arm/nucleo_wb55rg/Kconfig.board | 8 - boards/arm/nucleo_wb55rg/Kconfig.defconfig | 16 - boards/arm/nucleo_wba52cg/Kconfig.board | 8 - boards/arm/nucleo_wba52cg/Kconfig.defconfig | 16 - boards/arm/nucleo_wba55cg/Kconfig.board | 8 - boards/arm/nucleo_wba55cg/Kconfig.defconfig | 16 - boards/arm/nucleo_wl55jc/Kconfig.board | 8 - boards/arm/nucleo_wl55jc/Kconfig.defconfig | 11 - boards/arm/numaker_pfm_m467/Kconfig.board | 9 - boards/arm/numaker_pfm_m467/Kconfig.defconfig | 19 - boards/arm/numaker_pfm_m467/board.cmake | 9 - boards/arm/nuvoton_pfm_m487/Kconfig.board | 10 - boards/arm/nuvoton_pfm_m487/Kconfig.defconfig | 13 - boards/arm/nuvoton_pfm_m487/doc/index.rst | 98 -- .../arm/nuvoton_pfm_m487/nuvoton_pfm_m487.dts | 91 -- .../nuvoton_pfm_m487/nuvoton_pfm_m487.yaml | 11 - .../nuvoton_pfm_m487_defconfig | 20 - .../olimex_lora_stm32wl_devkit/Kconfig.board | 8 - .../Kconfig.defconfig | 11 - .../olimex_lora_stm32wl_devkit/revision.cmake | 11 - boards/arm/olimex_stm32_e407/Kconfig.board | 8 - .../arm/olimex_stm32_e407/Kconfig.defconfig | 11 - boards/arm/olimex_stm32_h103/Kconfig.board | 8 - .../arm/olimex_stm32_h103/Kconfig.defconfig | 11 - boards/arm/olimex_stm32_h405/Kconfig.board | 8 - .../arm/olimex_stm32_h405/Kconfig.defconfig | 11 - boards/arm/olimex_stm32_h407/Kconfig.board | 8 - .../arm/olimex_stm32_h407/Kconfig.defconfig | 11 - boards/arm/olimex_stm32_p405/Kconfig.board | 8 - .../arm/olimex_stm32_p405/Kconfig.defconfig | 11 - boards/arm/olimexino_stm32/Kconfig.board | 8 - boards/arm/olimexino_stm32/Kconfig.defconfig | 15 - boards/arm/pan1770_evb/Kconfig.board | 8 - boards/arm/pan1770_evb/Kconfig.defconfig | 14 - boards/arm/pan1780_evb/Kconfig.board | 8 - boards/arm/pan1780_evb/Kconfig.defconfig | 14 - boards/arm/pan1781_evb/Kconfig.board | 8 - boards/arm/pan1781_evb/Kconfig.defconfig | 14 - boards/arm/pan1782_evb/Kconfig.board | 8 - boards/arm/pan1782_evb/Kconfig.defconfig | 14 - boards/arm/pan1783/CMakeLists.txt | 7 - boards/arm/pan1783/Kconfig | 56 - boards/arm/pan1783/Kconfig.board | 28 - boards/arm/pan1783/Kconfig.defconfig | 34 - boards/arm/pan1783/board.cmake | 12 - boards/arm/pan1783/pan1783_cpuapp_common.dtsi | 300 ----- .../pan1783_cpuapp_partition_conf.dtsi | 38 - boards/arm/pan1783/pan1783_cpunet_common.dtsi | 207 ---- boards/arm/pan1783/pan1783_cpunet_reset.c | 52 - boards/arm/pan1783/pan1783_evb_cpuapp.dts | 21 - boards/arm/pan1783/pan1783_evb_cpuapp.yaml | 21 - .../arm/pan1783/pan1783_evb_cpuapp_defconfig | 25 - boards/arm/pan1783/pan1783_evb_cpunet.dts | 23 - boards/arm/pan1783/pan1783_evb_cpunet.yaml | 14 - .../arm/pan1783/pan1783_evb_cpunet_defconfig | 18 - boards/arm/pan1783/pan1783a_evb_cpuapp.dts | 21 - boards/arm/pan1783/pan1783a_evb_cpuapp.yaml | 21 - .../arm/pan1783/pan1783a_evb_cpuapp_defconfig | 25 - boards/arm/pan1783/pan1783a_evb_cpunet.dts | 23 - boards/arm/pan1783/pan1783a_evb_cpunet.yaml | 14 - .../arm/pan1783/pan1783a_evb_cpunet_defconfig | 18 - boards/arm/pan1783/pan1783a_pa_evb_cpuapp.dts | 30 - .../arm/pan1783/pan1783a_pa_evb_cpuapp.yaml | 21 - .../pan1783/pan1783a_pa_evb_cpuapp_defconfig | 25 - boards/arm/pan1783/pan1783a_pa_evb_cpunet.dts | 33 - .../arm/pan1783/pan1783a_pa_evb_cpunet.yaml | 14 - .../pan1783/pan1783a_pa_evb_cpunet_defconfig | 18 - boards/arm/pandora_stm32l475/Kconfig.board | 8 - .../arm/pandora_stm32l475/Kconfig.defconfig | 11 - boards/arm/pandora_stm32l475/doc/index.rst | 214 ---- boards/arm/particle_argon/Kconfig.board | 8 - boards/arm/particle_argon/Kconfig.defconfig | 14 - boards/arm/particle_boron/Kconfig.board | 8 - boards/arm/particle_boron/Kconfig.defconfig | 28 - boards/arm/particle_xenon/Kconfig.board | 8 - boards/arm/particle_xenon/Kconfig.defconfig | 15 - .../particle_xenon/particle_xenon_defconfig | 21 - boards/arm/pico_pi_m4/Kconfig.board | 8 - boards/arm/pico_pi_m4/Kconfig.defconfig | 18 - boards/arm/pico_pi_m4/doc/index.rst | 239 ---- boards/arm/pico_pi_m4/pico_pi_m4.dts | 65 - boards/arm/pico_pi_m4/pico_pi_m4.yaml | 21 - boards/arm/pico_pi_m4/pico_pi_m4_defconfig | 16 - boards/arm/pinetime_devkit0/Kconfig.board | 8 - boards/arm/pinetime_devkit0/Kconfig.defconfig | 24 - .../pinetime_devkit0_defconfig | 14 - boards/arm/pinnacle_100_dvk/Kconfig.board | 8 - boards/arm/pinnacle_100_dvk/Kconfig.defconfig | 26 - boards/arm/pinnacle_100_dvk/doc/index.rst | 220 ---- boards/arm/qemu_cortex_a9/Kconfig.board | 11 - boards/arm/qemu_cortex_a9/Kconfig.defconfig | 80 -- boards/arm/qemu_cortex_a9/board.cmake | 21 - boards/arm/qemu_cortex_m0/Kconfig | 14 - boards/arm/qemu_cortex_m0/Kconfig.board | 9 - boards/arm/qemu_cortex_m0/Kconfig.defconfig | 20 - .../qemu_cortex_m0/qemu_cortex_m0_defconfig | 22 - boards/arm/qemu_cortex_m3/Kconfig.board | 6 - boards/arm/qemu_cortex_m3/Kconfig.defconfig | 17 - boards/arm/qemu_cortex_m3/board.cmake | 12 - boards/arm/qemu_cortex_r5/Kconfig.board | 7 - boards/arm/qemu_cortex_r5/Kconfig.defconfig | 19 - boards/arm/qemu_cortex_r5/board.cmake | 21 - boards/arm/qomu/Kconfig.board | 8 - boards/arm/qomu/Kconfig.defconfig | 11 - boards/arm/quick_feather/Kconfig.board | 8 - boards/arm/quick_feather/Kconfig.defconfig | 11 - boards/arm/quick_feather/doc/index.rst | 125 -- boards/arm/rak4631_nrf52840/Kconfig.board | 8 - boards/arm/rak4631_nrf52840/Kconfig.defconfig | 14 - boards/arm/rak4631_nrf52840/doc/index.rst | 155 --- boards/arm/rak5010_nrf52840/Kconfig.board | 8 - boards/arm/rak5010_nrf52840/Kconfig.defconfig | 14 - boards/arm/rak5010_nrf52840/doc/index.rst | 159 --- .../arm/raytac_mdbt50q_db_33_nrf52833/Kconfig | 10 - .../Kconfig.board | 8 - .../Kconfig.defconfig | 14 - .../doc/index.rst | 213 ---- .../arm/raytac_mdbt50q_db_40_nrf52840/Kconfig | 18 - .../Kconfig.board | 8 - .../Kconfig.defconfig | 14 - .../doc/index.rst | 215 ---- .../CMakeLists.txt | 7 - .../arm/raytac_mdbt53_db_40_nrf5340/Kconfig | 58 - .../raytac_mdbt53_db_40_nrf5340/Kconfig.board | 18 - .../Kconfig.defconfig | 87 -- .../raytac_mdbt53_db_40_nrf5340/board.cmake | 13 - .../raytac_mdbt53_db_40_nrf5340/doc/index.rst | 271 ----- ...ytac_mdbt53_db_40_nrf5340_cpuapp_defconfig | 24 - ...c_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig | 27 - ...ytac_mdbt53_db_40_nrf5340_cpunet_defconfig | 21 - .../CMakeLists.txt | 7 - .../arm/raytac_mdbt53v_db_40_nrf5340/Kconfig | 58 - .../Kconfig.board | 18 - .../Kconfig.defconfig | 87 -- .../raytac_mdbt53v_db_40_nrf5340/board.cmake | 12 - ...tac_mdbt53v_db_40_nrf5340_cpuapp_defconfig | 24 - ..._mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig | 27 - ...tac_mdbt53v_db_40_nrf5340_cpunet_defconfig | 21 - boards/arm/rcar_h3_salvatorx/Kconfig.board | 6 - .../arm/rcar_h3_salvatorx/Kconfig.defconfig | 7 - .../doc/rcar_h3_salvatorx.rst | 183 --- .../rcar_h3_salvatorx_cr7.dts | 93 -- .../rcar_h3_salvatorx_cr7.yaml | 16 - .../rcar_h3_salvatorx_cr7_defconfig | 13 - boards/arm/rcar_h3ulcb/Kconfig.board | 6 - boards/arm/rcar_h3ulcb/Kconfig.defconfig | 7 - boards/arm/rcar_h3ulcb/doc/rcar_h3ulcb.rst | 276 ----- boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts | 85 -- boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.yaml | 17 - .../arm/rcar_h3ulcb/rcar_h3ulcb_cr7_defconfig | 13 - boards/arm/rcar_h3ulcb/support/openocd.cfg | 88 -- boards/arm/rcar_spider/Kconfig.board | 6 - boards/arm/rcar_spider/Kconfig.defconfig | 9 - boards/arm/rcar_spider/board.cmake | 3 - boards/arm/rcar_spider/rcar_spider_cr52.dts | 58 - boards/arm/rcar_spider/rcar_spider_cr52.yaml | 11 - .../rcar_spider/rcar_spider_cr52_defconfig | 13 - boards/arm/rddrone_fmuk66/Kconfig.board | 7 - boards/arm/rddrone_fmuk66/Kconfig.defconfig | 30 - boards/arm/rddrone_fmuk66/doc/index.rst | 203 ---- boards/arm/reel_board/Kconfig | 10 - boards/arm/reel_board/Kconfig.board | 12 - boards/arm/reel_board/Kconfig.defconfig | 44 - boards/arm/reel_board/doc/index.rst | 564 --------- boards/arm/reel_board/reel_board_defconfig | 18 - boards/arm/reel_board/reel_board_v2.dts | 119 -- boards/arm/reel_board/reel_board_v2.yaml | 22 - boards/arm/reel_board/reel_board_v2_defconfig | 18 - boards/arm/rm1xx_dvk/Kconfig.board | 8 - boards/arm/rm1xx_dvk/Kconfig.defconfig | 14 - boards/arm/rm1xx_dvk/pre_dt_board.cmake | 6 - boards/arm/rm1xx_dvk/rm1xx_dvk_defconfig | 17 - boards/arm/ronoth_lodev/Kconfig.board | 7 - boards/arm/ronoth_lodev/Kconfig.defconfig | 14 - boards/arm/rpi_pico/Kconfig.board | 10 - boards/arm/rpi_pico/Kconfig.defconfig | 23 - boards/arm/rpi_pico/rpi_pico_w.yaml | 24 - boards/arm/rpi_pico/rpi_pico_w_defconfig | 14 - boards/arm/ruuvi_ruuvitag/Kconfig.board | 6 - boards/arm/ruuvi_ruuvitag/Kconfig.defconfig | 17 - boards/arm/ruuvi_ruuvitag/doc/index.rst | 184 --- boards/arm/rzt2m_starterkit/Kconfig.board | 6 - boards/arm/rzt2m_starterkit/Kconfig.defconfig | 9 - .../rzt2m_starter_kit_defconfig | 10 - boards/arm/s32z270dc2_r52/Kconfig.board | 12 - boards/arm/s32z270dc2_r52/Kconfig.defconfig | 34 - boards/arm/s32z270dc2_r52/doc/index.rst | 311 ----- boards/arm/s32z270dc2_r52/revision.cmake | 8 - boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi | 51 - .../s32z270dc2_r52/s32z270dc2_rtu0_r52.dts | 33 - .../s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml | 19 - .../s32z270dc2_r52/s32z270dc2_rtu0_r52_D.yaml | 19 - .../s32z270dc2_rtu0_r52_defconfig | 14 - .../s32z270dc2_r52/s32z270dc2_rtu1_r52.dts | 35 - .../s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml | 19 - .../s32z270dc2_r52/s32z270dc2_rtu1_r52_D.yaml | 19 - .../s32z270dc2_rtu1_r52_defconfig | 14 - boards/arm/sam4e_xpro/Kconfig.board | 8 - boards/arm/sam4e_xpro/Kconfig.defconfig | 11 - boards/arm/sam4e_xpro/doc/index.rst | 191 --- boards/arm/sam4e_xpro/sam4e_xpro_defconfig | 16 - boards/arm/sam4l_ek/Kconfig.board | 8 - boards/arm/sam4l_ek/Kconfig.defconfig | 11 - boards/arm/sam4l_ek/doc/index.rst | 172 --- boards/arm/sam4l_ek/sam4l_ek_defconfig | 13 - boards/arm/sam4s_xplained/Kconfig.board | 8 - boards/arm/sam4s_xplained/Kconfig.defconfig | 11 - boards/arm/sam4s_xplained/doc/index.rst | 187 --- .../sam4s_xplained/sam4s_xplained_defconfig | 16 - boards/arm/sam_e70_xplained/Kconfig.board | 8 - boards/arm/sam_e70_xplained/Kconfig.defconfig | 34 - boards/arm/sam_e70_xplained/doc/index.rst | 187 --- .../arm/sam_e70_xplained/sam_e70_xplained.dts | 49 - .../sam_e70_xplained/sam_e70_xplained.yaml | 23 - .../sam_e70_xplained_defconfig | 20 - .../sam_e70_xplained/sam_e70b_xplained.dts | 16 - .../sam_e70_xplained/sam_e70b_xplained.yaml | 22 - .../sam_e70b_xplained_defconfig | 20 - boards/arm/sam_v71_xult/Kconfig.board | 9 - boards/arm/sam_v71_xult/Kconfig.defconfig | 35 - boards/arm/sam_v71_xult/doc/index.rst | 190 --- boards/arm/sam_v71_xult/sam_v71_xult.dts | 17 - boards/arm/sam_v71_xult/sam_v71_xult.yaml | 27 - .../arm/sam_v71_xult/sam_v71_xult_defconfig | 20 - boards/arm/sam_v71_xult/sam_v71b_xult.dts | 16 - boards/arm/sam_v71_xult/sam_v71b_xult.yaml | 27 - .../arm/sam_v71_xult/sam_v71b_xult_defconfig | 20 - boards/arm/scobc_module1/Kconfig.board | 8 - boards/arm/scobc_module1/Kconfig.defconfig | 20 - boards/arm/scobc_module1/board.cmake | 7 - .../arm/scobc_module1/scobc_module1_defconfig | 16 - boards/arm/seeeduino_xiao/Kconfig.board | 8 - boards/arm/seeeduino_xiao/Kconfig.defconfig | 8 - boards/arm/seeeduino_xiao/doc/index.rst | 176 --- boards/arm/segger_trb_stm32f407/Kconfig.board | 8 - .../segger_trb_stm32f407/Kconfig.defconfig | 11 - boards/arm/sensortile_box/Kconfig.board | 8 - boards/arm/sensortile_box/Kconfig.defconfig | 34 - boards/arm/sensortile_box/board.cmake | 5 - boards/arm/sensortile_box_pro/Kconfig.board | 8 - .../arm/sensortile_box_pro/Kconfig.defconfig | 42 - boards/arm/sensortile_box_pro/doc/index.rst | 386 ------ boards/arm/serpente/Kconfig.board | 7 - boards/arm/serpente/Kconfig.defconfig | 7 - boards/arm/serpente/doc/index.rst | 125 -- boards/arm/serpente/pre_dt_board.cmake | 7 - boards/arm/serpente/serpente_defconfig | 14 - .../sparkfun_pro_micro_rp2040/Kconfig.board | 6 - .../Kconfig.defconfig | 22 - .../arm/sparkfun_thing_plus_nrf9160/Kconfig | 5 - .../sparkfun_thing_plus_nrf9160/Kconfig.board | 23 - .../Kconfig.defconfig | 39 - .../sparkfun_thing_plus_nrf9160/doc/index.rst | 153 --- .../sparkfun_thing_plus_nrf9160_defconfig | 23 - .../sparkfun_thing_plus_nrf9160_ns_defconfig | 26 - boards/arm/steval_fcu001v1/Kconfig.board | 8 - boards/arm/steval_fcu001v1/Kconfig.defconfig | 11 - boards/arm/steval_fcu001v1/doc/index.rst | 158 --- boards/arm/stm3210c_eval/Kconfig.board | 8 - boards/arm/stm3210c_eval/Kconfig.defconfig | 11 - boards/arm/stm3210c_eval/doc/index.rst | 165 --- .../arm/stm3210c_eval/stm3210c_eval_defconfig | 23 - boards/arm/stm32373c_eval/Kconfig.board | 8 - boards/arm/stm32373c_eval/Kconfig.defconfig | 11 - boards/arm/stm32373c_eval/doc/index.rst | 159 --- boards/arm/stm32_min_dev/Kconfig.board | 12 - boards/arm/stm32_min_dev/Kconfig.defconfig | 12 - boards/arm/stm32_min_dev/doc/index.rst | 186 --- .../arm/stm32_min_dev/stm32_min_dev_black.dts | 19 - .../stm32_min_dev/stm32_min_dev_black.yaml | 16 - .../stm32_min_dev_black_defconfig | 25 - .../arm/stm32_min_dev/stm32_min_dev_blue.dts | 19 - .../arm/stm32_min_dev/stm32_min_dev_blue.yaml | 15 - .../stm32_min_dev_blue_defconfig | 20 - boards/arm/stm32f030_demo/Kconfig.board | 6 - boards/arm/stm32f030_demo/Kconfig.defconfig | 9 - boards/arm/stm32f030_demo/doc/index.rst | 123 -- boards/arm/stm32f072_eval/Kconfig.board | 8 - boards/arm/stm32f072_eval/Kconfig.defconfig | 11 - boards/arm/stm32f072_eval/doc/index.rst | 185 --- .../stm32f072_eval/stm32f072_eval_defconfig | 23 - boards/arm/stm32f072b_disco/Kconfig.board | 8 - boards/arm/stm32f072b_disco/Kconfig.defconfig | 15 - boards/arm/stm32f072b_disco/doc/index.rst | 219 ---- .../stm32f072b_disco_defconfig | 23 - boards/arm/stm32f0_disco/Kconfig.board | 8 - boards/arm/stm32f0_disco/Kconfig.defconfig | 11 - boards/arm/stm32f0_disco/doc/index.rst | 143 --- boards/arm/stm32f103_mini/Kconfig.board | 8 - boards/arm/stm32f103_mini/Kconfig.defconfig | 11 - boards/arm/stm32f103_mini/doc/index.rst | 166 --- boards/arm/stm32f3_disco/Kconfig.board | 8 - boards/arm/stm32f3_disco/Kconfig.defconfig | 11 - boards/arm/stm32f3_disco/doc/index.rst | 281 ----- boards/arm/stm32f3_disco/revision.cmake | 4 - boards/arm/stm32f3_disco/stm32f3_disco.yaml | 24 - boards/arm/stm32f3_disco/stm32f3_disco_B.conf | 2 - boards/arm/stm32f3_disco/stm32f3_disco_E.conf | 2 - boards/arm/stm32f3_disco/stm32f3_disco_E.yaml | 22 - boards/arm/stm32f3_seco_d23/Kconfig.board | 8 - boards/arm/stm32f3_seco_d23/Kconfig.defconfig | 11 - boards/arm/stm32f401_mini/Kconfig.board | 8 - boards/arm/stm32f401_mini/Kconfig.defconfig | 15 - boards/arm/stm32f401_mini/doc/index.rst | 154 --- boards/arm/stm32f411e_disco/Kconfig.board | 8 - boards/arm/stm32f411e_disco/Kconfig.defconfig | 11 - boards/arm/stm32f411e_disco/doc/index.rst | 188 --- boards/arm/stm32f411e_disco/revision.cmake | 4 - .../stm32f411e_disco/stm32f411e_disco_B.conf | 2 - .../stm32f411e_disco/stm32f411e_disco_D.conf | 2 - boards/arm/stm32f412g_disco/Kconfig.board | 7 - boards/arm/stm32f412g_disco/Kconfig.defconfig | 10 - boards/arm/stm32f412g_disco/doc/index.rst | 202 ---- boards/arm/stm32f429i_disc1/Kconfig.board | 8 - boards/arm/stm32f429i_disc1/Kconfig.defconfig | 17 - boards/arm/stm32f429i_disc1/doc/index.rst | 230 ---- boards/arm/stm32f469i_disco/Kconfig.board | 8 - boards/arm/stm32f469i_disco/Kconfig.defconfig | 16 - boards/arm/stm32f469i_disco/doc/index.rst | 208 ---- boards/arm/stm32f4_disco/Kconfig.board | 8 - boards/arm/stm32f4_disco/Kconfig.defconfig | 11 - boards/arm/stm32f4_disco/doc/index.rst | 214 ---- boards/arm/stm32f723e_disco/Kconfig.board | 8 - boards/arm/stm32f723e_disco/Kconfig.defconfig | 16 - boards/arm/stm32f723e_disco/doc/index.rst | 192 --- boards/arm/stm32f746g_disco/Kconfig.board | 8 - boards/arm/stm32f746g_disco/Kconfig.defconfig | 40 - boards/arm/stm32f746g_disco/doc/index.rst | 243 ---- boards/arm/stm32f7508_dk/Kconfig.board | 8 - boards/arm/stm32f7508_dk/Kconfig.defconfig | 40 - boards/arm/stm32f7508_dk/doc/index.rst | 238 ---- boards/arm/stm32f769i_disco/Kconfig.board | 8 - boards/arm/stm32f769i_disco/Kconfig.defconfig | 25 - boards/arm/stm32f769i_disco/doc/index.rst | 225 ---- boards/arm/stm32g0316_disco/Kconfig.board | 8 - boards/arm/stm32g0316_disco/Kconfig.defconfig | 11 - boards/arm/stm32g0316_disco/doc/index.rst | 134 -- boards/arm/stm32g071b_disco/Kconfig.board | 8 - boards/arm/stm32g071b_disco/Kconfig.defconfig | 11 - boards/arm/stm32g071b_disco/doc/index.rst | 169 --- boards/arm/stm32g081b_eval/Kconfig.board | 8 - boards/arm/stm32g081b_eval/Kconfig.defconfig | 11 - boards/arm/stm32g081b_eval/doc/index.rst | 207 ---- boards/arm/stm32h573i_dk/Kconfig.board | 10 - boards/arm/stm32h573i_dk/Kconfig.defconfig | 20 - boards/arm/stm32h573i_dk/doc/index.rst | 326 ----- boards/arm/stm32h735g_disco/Kconfig.board | 8 - boards/arm/stm32h735g_disco/Kconfig.defconfig | 22 - boards/arm/stm32h735g_disco/doc/index.rst | 152 --- boards/arm/stm32h747i_disco/Kconfig.board | 14 - boards/arm/stm32h747i_disco/Kconfig.defconfig | 22 - boards/arm/stm32h747i_disco/board.cmake | 16 - boards/arm/stm32h747i_disco/doc/index.rst | 313 ----- .../stm32h747i_disco/stm32h747i_disco_m4.yaml | 19 - .../stm32h747i_disco_m4_defconfig | 29 - .../stm32h747i_disco/stm32h747i_disco_m7.yaml | 21 - .../stm32h747i_disco_m7_defconfig | 33 - boards/arm/stm32h750b_dk/Kconfig.board | 8 - boards/arm/stm32h750b_dk/Kconfig.defconfig | 11 - boards/arm/stm32h750b_dk/board.cmake | 7 - boards/arm/stm32h750b_dk/doc/index.rst | 145 --- boards/arm/stm32h7b3i_dk/Kconfig.board | 8 - boards/arm/stm32h7b3i_dk/Kconfig.defconfig | 22 - boards/arm/stm32h7b3i_dk/doc/index.rst | 171 --- boards/arm/stm32l1_disco/Kconfig.board | 8 - boards/arm/stm32l1_disco/Kconfig.defconfig | 11 - boards/arm/stm32l1_disco/doc/index.rst | 179 --- boards/arm/stm32l476g_disco/Kconfig.board | 8 - boards/arm/stm32l476g_disco/Kconfig.defconfig | 11 - boards/arm/stm32l476g_disco/doc/index.rst | 218 ---- boards/arm/stm32l496g_disco/Kconfig.board | 10 - boards/arm/stm32l496g_disco/Kconfig.defconfig | 19 - boards/arm/stm32l496g_disco/doc/index.rst | 259 ---- boards/arm/stm32l4r9i_disco/Kconfig.board | 8 - boards/arm/stm32l4r9i_disco/Kconfig.defconfig | 11 - boards/arm/stm32l4r9i_disco/doc/index.rst | 150 --- boards/arm/stm32l562e_dk/Kconfig.board | 8 - boards/arm/stm32l562e_dk/Kconfig.defconfig | 40 - boards/arm/stm32l562e_dk/doc/index.rst | 387 ------ .../arm/stm32l562e_dk/stm32l562e_dk_ns.yaml | 21 - .../stm32l562e_dk/stm32l562e_dk_ns_defconfig | 27 - boards/arm/stm32mp157c_dk2/Kconfig.board | 8 - boards/arm/stm32mp157c_dk2/Kconfig.defconfig | 18 - boards/arm/stm32u5a9j_dk/Kconfig.board | 8 - boards/arm/stm32u5a9j_dk/Kconfig.defconfig | 11 - boards/arm/stm32u5a9j_dk/doc/index.rst | 198 --- boards/arm/stm32vl_disco/Kconfig.board | 8 - boards/arm/stm32vl_disco/Kconfig.defconfig | 11 - boards/arm/stm32vl_disco/doc/index.rst | 188 --- boards/arm/stm32wb5mm_dk/Kconfig.board | 8 - boards/arm/stm32wb5mm_dk/Kconfig.defconfig | 16 - boards/arm/stm32wb5mmg/Kconfig.board | 8 - boards/arm/stm32wb5mmg/Kconfig.defconfig | 16 - boards/arm/swan_r5/CMakeLists.txt | 4 - boards/arm/swan_r5/Kconfig.board | 8 - boards/arm/swan_r5/Kconfig.defconfig | 25 - boards/arm/swan_r5/doc/index.rst | 232 ---- boards/arm/tdk_robokit1/Kconfig.board | 8 - boards/arm/tdk_robokit1/Kconfig.defconfig | 11 - boards/arm/tdk_robokit1/board.cmake | 6 - boards/arm/tdk_robokit1/doc/index.rst | 184 --- .../arm/tdk_robokit1/tdk_robokit1-common.dtsi | 223 ---- boards/arm/tdk_robokit1/tdk_robokit1.dts | 16 - boards/arm/tdk_robokit1/tdk_robokit1.yaml | 21 - .../arm/tdk_robokit1/tdk_robokit1_defconfig | 17 - boards/arm/teensy4/CMakeLists.txt | 14 - boards/arm/teensy4/Kconfig.board | 15 - boards/arm/teensy4/Kconfig.defconfig | 24 - boards/arm/teensy4/flexspi_nor_config.c | 44 - boards/arm/thingy52_nrf52832/CMakeLists.txt | 6 - boards/arm/thingy52_nrf52832/Kconfig | 17 - boards/arm/thingy52_nrf52832/Kconfig.board | 8 - .../arm/thingy52_nrf52832/Kconfig.defconfig | 14 - boards/arm/thingy52_nrf52832/doc/index.rst | 388 ------ .../thingy52_nrf52832_defconfig | 32 - boards/arm/thingy53_nrf5340/CMakeLists.txt | 7 - boards/arm/thingy53_nrf5340/Kconfig | 74 -- boards/arm/thingy53_nrf5340/Kconfig.board | 21 - boards/arm/thingy53_nrf5340/Kconfig.defconfig | 152 --- boards/arm/thingy53_nrf5340/board.cmake | 13 - boards/arm/thingy53_nrf5340/doc/index.rst | 51 - .../thingy53_nrf5340_cpunet_defconfig | 14 - boards/arm/twr_ke18f/Kconfig.board | 9 - boards/arm/twr_ke18f/Kconfig.defconfig | 20 - boards/arm/twr_ke18f/doc/index.rst | 254 ---- boards/arm/twr_ke18f/twr_ke18f_defconfig | 14 - boards/arm/twr_kv58f220m/Kconfig.board | 9 - boards/arm/twr_kv58f220m/Kconfig.defconfig | 23 - boards/arm/twr_kv58f220m/doc/index.rst | 200 --- boards/arm/ubx_bmd300eval_nrf52832/Kconfig | 10 - .../arm/ubx_bmd300eval_nrf52832/Kconfig.board | 8 - .../ubx_bmd300eval_nrf52832/Kconfig.defconfig | 14 - .../arm/ubx_bmd300eval_nrf52832/doc/index.rst | 397 ------ boards/arm/ubx_bmd330eval_nrf52810/Kconfig | 15 - .../arm/ubx_bmd330eval_nrf52810/Kconfig.board | 8 - .../ubx_bmd330eval_nrf52810/Kconfig.defconfig | 11 - .../arm/ubx_bmd330eval_nrf52810/doc/index.rst | 388 ------ .../ubx_bmd330eval_nrf52810.yaml | 23 - boards/arm/ubx_bmd340eval_nrf52840/Kconfig | 10 - .../arm/ubx_bmd340eval_nrf52840/Kconfig.board | 8 - .../ubx_bmd340eval_nrf52840/Kconfig.defconfig | 14 - .../arm/ubx_bmd340eval_nrf52840/doc/index.rst | 521 -------- boards/arm/ubx_bmd345eval_nrf52840/Kconfig | 8 - .../arm/ubx_bmd345eval_nrf52840/Kconfig.board | 9 - .../ubx_bmd345eval_nrf52840/Kconfig.defconfig | 15 - .../arm/ubx_bmd345eval_nrf52840/doc/index.rst | 533 -------- boards/arm/ubx_bmd360eval_nrf52811/Kconfig | 14 - .../arm/ubx_bmd360eval_nrf52811/Kconfig.board | 8 - .../ubx_bmd360eval_nrf52811/Kconfig.defconfig | 11 - .../arm/ubx_bmd360eval_nrf52811/doc/index.rst | 386 ------ boards/arm/ubx_bmd380eval_nrf52840/Kconfig | 10 - .../arm/ubx_bmd380eval_nrf52840/Kconfig.board | 11 - .../ubx_bmd380eval_nrf52840/Kconfig.defconfig | 14 - .../arm/ubx_bmd380eval_nrf52840/doc/index.rst | 519 -------- boards/arm/ubx_evkannab1_nrf52832/Kconfig | 10 - .../arm/ubx_evkannab1_nrf52832/Kconfig.board | 8 - .../ubx_evkannab1_nrf52832/Kconfig.defconfig | 14 - .../arm/ubx_evkannab1_nrf52832/doc/index.rst | 169 --- boards/arm/ubx_evkninab1_nrf52832/Kconfig | 10 - .../arm/ubx_evkninab1_nrf52832/Kconfig.board | 8 - .../ubx_evkninab1_nrf52832/Kconfig.defconfig | 14 - .../arm/ubx_evkninab1_nrf52832/doc/index.rst | 178 --- boards/arm/ubx_evkninab3_nrf52840/Kconfig | 10 - .../arm/ubx_evkninab3_nrf52840/Kconfig.board | 8 - .../ubx_evkninab3_nrf52840/Kconfig.defconfig | 14 - .../arm/ubx_evkninab3_nrf52840/doc/index.rst | 328 ----- boards/arm/ubx_evkninab4_nrf52833/Kconfig | 10 - .../arm/ubx_evkninab4_nrf52833/Kconfig.board | 8 - .../ubx_evkninab4_nrf52833/Kconfig.defconfig | 14 - .../arm/ubx_evkninab4_nrf52833/doc/index.rst | 230 ---- boards/arm/ucans32k1sic/Kconfig.board | 7 - boards/arm/ucans32k1sic/Kconfig.defconfig | 23 - boards/arm/ucans32k1sic/doc/index.rst | 197 --- .../arm/ucans32k1sic/ucans32k1sic_defconfig | 20 - boards/arm/udoo_neo_full_m4/Kconfig.board | 7 - boards/arm/udoo_neo_full_m4/Kconfig.defconfig | 11 - boards/arm/udoo_neo_full_m4/doc/index.rst | 368 ------ .../arm/udoo_neo_full_m4/udoo_neo_full_m4.dts | 84 -- .../udoo_neo_full_m4/udoo_neo_full_m4.yaml | 21 - .../udoo_neo_full_m4_defconfig | 16 - boards/arm/usb_kw24d512/Kconfig.board | 9 - boards/arm/usb_kw24d512/Kconfig.defconfig | 31 - boards/arm/usb_kw24d512/doc/index.rst | 231 ---- .../arm/usb_kw24d512/usb_kw24d512_defconfig | 13 - boards/arm/v2m_beetle/Kconfig.board | 9 - boards/arm/v2m_beetle/Kconfig.defconfig | 3 - boards/arm/v2m_beetle/Kconfig.v2m_beetle | 8 + boards/arm/v2m_beetle/board.yml | 5 + boards/arm/v2m_beetle/v2m_beetle_defconfig | 4 +- boards/arm/v2m_musca_b1/Kconfig.board | 6 - boards/arm/v2m_musca_b1/Kconfig.defconfig | 8 +- boards/arm/v2m_musca_b1/Kconfig.v2m_musca_b1 | 5 + boards/arm/v2m_musca_b1/board.yml | 7 + boards/arm/v2m_musca_b1/doc/index.rst | 2 +- boards/arm/v2m_musca_b1/v2m_musca_b1.yaml | 2 +- .../arm/v2m_musca_b1/v2m_musca_b1_defconfig | 2 - ...b1_ns.dts => v2m_musca_b1_musca_b1_ns.dts} | 0 .../v2m_musca_b1_musca_b1_ns.yaml | 11 + .../v2m_musca_b1_musca_b1_ns_defconfig | 7 + boards/arm/v2m_musca_b1/v2m_musca_b1_ns.yaml | 11 - .../v2m_musca_b1/v2m_musca_b1_ns_defconfig | 17 - boards/arm/v2m_musca_s1/Kconfig.board | 6 - boards/arm/v2m_musca_s1/Kconfig.defconfig | 8 +- boards/arm/v2m_musca_s1/Kconfig.v2m_musca_s1 | 5 + boards/arm/v2m_musca_s1/board.yml | 7 + boards/arm/v2m_musca_s1/doc/index.rst | 6 +- boards/arm/v2m_musca_s1/v2m_musca_s1.yaml | 2 +- .../arm/v2m_musca_s1/v2m_musca_s1_defconfig | 2 - ...s1_ns.dts => v2m_musca_s1_musca_s1_ns.dts} | 0 .../v2m_musca_s1_musca_s1_ns.yaml | 11 + .../v2m_musca_s1_musca_s1_ns_defconfig | 7 + boards/arm/v2m_musca_s1/v2m_musca_s1_ns.yaml | 11 - .../v2m_musca_s1/v2m_musca_s1_ns_defconfig | 17 - boards/arm/verdin_imx8mp_m7/Kconfig.board | 9 - boards/arm/verdin_imx8mp_m7/Kconfig.defconfig | 18 - boards/arm/verdin_imx8mp_m7/doc/index.rst | 304 ----- .../verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.dts | 46 - .../verdin_imx8mp_m7_ddr.yaml | 18 - .../verdin_imx8mp_m7_ddr_defconfig | 16 - .../verdin_imx8mp_m7_itcm.dts | 46 - .../verdin_imx8mp_m7_itcm.yaml | 18 - .../verdin_imx8mp_m7_itcm_defconfig | 16 - boards/arm/vmu_rt1170/CMakeLists.txt | 26 - boards/arm/vmu_rt1170/Kconfig.board | 7 - boards/arm/vmu_rt1170/Kconfig.defconfig | 45 - boards/arm/vmu_rt1170/flexspi_nor_config.c | 149 --- boards/arm/w5500_evb_pico/Kconfig.board | 7 - boards/arm/w5500_evb_pico/Kconfig.defconfig | 30 - boards/arm/warp7_m4/Kconfig.board | 9 - boards/arm/warp7_m4/Kconfig.defconfig | 26 - boards/arm/warp7_m4/doc/index.rst | 345 ------ boards/arm/warp7_m4/warp7_m4.dts | 96 -- boards/arm/warp7_m4/warp7_m4.yaml | 24 - boards/arm/warp7_m4/warp7_m4_defconfig | 15 - boards/arm/waveshare_open103z/Kconfig.board | 8 - .../arm/waveshare_open103z/Kconfig.defconfig | 11 - boards/arm/we_ophelia1ev_nrf52805/Kconfig | 10 - .../arm/we_ophelia1ev_nrf52805/Kconfig.board | 6 - .../we_ophelia1ev_nrf52805/Kconfig.defconfig | 12 - .../arm/we_ophelia1ev_nrf52805/doc/index.rst | 115 -- .../arm/we_proteus2ev_nrf52832/Kconfig.board | 6 - .../we_proteus2ev_nrf52832/Kconfig.defconfig | 12 - .../arm/we_proteus2ev_nrf52832/doc/index.rst | 162 --- boards/arm/we_proteus3ev_nrf52840/Kconfig | 18 - .../arm/we_proteus3ev_nrf52840/Kconfig.board | 6 - .../we_proteus3ev_nrf52840/Kconfig.defconfig | 12 - .../arm/we_proteus3ev_nrf52840/doc/index.rst | 164 --- boards/arm/weact_stm32g431_core/Kconfig.board | 9 - .../weact_stm32g431_core/Kconfig.defconfig | 12 - boards/arm/weact_stm32g431_core/doc/index.rst | 147 --- boards/arm/wio_terminal/Kconfig.board | 8 - boards/arm/wio_terminal/Kconfig.defconfig | 11 - boards/arm/wio_terminal/doc/index.rst | 213 ---- boards/arm/xiao_ble/Kconfig.board | 8 - boards/arm/xiao_ble/Kconfig.defconfig | 24 - boards/arm/xiao_ble/doc/index.rst | 219 ---- boards/arm/xiao_ble/pre_dt_board.cmake | 7 - boards/arm/xiao_ble/xiao_ble_defconfig | 30 - boards/arm/xiao_ble/xiao_ble_sense.yaml | 24 - boards/arm/xiao_ble/xiao_ble_sense_defconfig | 33 - boards/arm/xmc45_relax_kit/Kconfig.board | 9 - boards/arm/xmc45_relax_kit/Kconfig.defconfig | 22 - boards/arm/xmc47_relax_kit/Kconfig.board | 8 - boards/arm/xmc47_relax_kit/Kconfig.defconfig | 21 - .../xmc47_relax_kit/xmc47_relax_kit_defconfig | 15 - boards/arm/zybo/Kconfig.board | 8 - boards/arm/zybo/Kconfig.defconfig | 11 - boards/arm/zybo/doc/index.rst | 147 --- boards/arm/zybo/zybo_defconfig | 14 - boards/arm64/bcm958402m2_a72/Kconfig.board | 6 - .../arm64/bcm958402m2_a72/Kconfig.defconfig | 6 - .../bcm958402m2_a72/bcm958402m2_a72.yaml | 8 - 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++ .../mimxrt1170_evk_mimxrt1176_cm4_B.yaml | 23 + .../mimxrt1170_evk_mimxrt1176_cm4_defconfig | 13 + .../mimxrt1170_evk_mimxrt1176_cm7.dts} | 0 .../mimxrt1170_evk_mimxrt1176_cm7.yaml | 31 + .../mimxrt1170_evk_mimxrt1176_cm7_B.overlay | 76 ++ .../mimxrt1170_evk_mimxrt1176_cm7_B.yaml | 29 + .../mimxrt1170_evk_mimxrt1176_cm7_defconfig | 13 + boards/nxp/mimxrt595_evk/CMakeLists.txt | 32 + boards/nxp/mimxrt595_evk/Kconfig | 48 + boards/nxp/mimxrt595_evk/Kconfig.defconfig | 39 + .../nxp/mimxrt595_evk/Kconfig.mimxrt595_evk | 10 + boards/{arm => nxp}/mimxrt595_evk/board.c | 0 boards/{arm => nxp}/mimxrt595_evk/board.cmake | 0 boards/{arm => nxp}/mimxrt595_evk/board.h | 0 boards/nxp/mimxrt595_evk/board.yml | 5 + boards/{arm => nxp}/mimxrt595_evk/dc_ram.ld | 0 boards/nxp/mimxrt595_evk/doc/index.rst | 334 +++++ .../mimxrt595_evk/doc/mimxrt595_evk.jpg | Bin ...imxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi} | 0 .../mimxrt595_evk_mimxrt595s_cm33.dts | 512 ++++++++ .../mimxrt595_evk_mimxrt595s_cm33.yaml | 32 + .../mimxrt595_evk_mimxrt595s_cm33_defconfig | 16 + .../mimxrt595_evk_mimxrt595s_f1.dts} | 0 .../mimxrt595_evk_mimxrt595s_f1.yaml | 10 + .../mimxrt595_evk_mimxrt595s_f1_defconfig | 4 + .../mimxrt595_evk/pre_dt_board.cmake | 0 boards/nxp/mimxrt685_evk/CMakeLists.txt | 25 + boards/{arm => nxp}/mimxrt685_evk/Kconfig | 0 boards/nxp/mimxrt685_evk/Kconfig.defconfig | 29 + .../nxp/mimxrt685_evk/Kconfig.mimxrt685_evk | 5 + boards/{arm => nxp}/mimxrt685_evk/board.cmake | 0 boards/nxp/mimxrt685_evk/board.yml | 5 + boards/nxp/mimxrt685_evk/doc/index.rst | 370 ++++++ .../mimxrt685_evk/doc/mimxrt685_evk.jpg | Bin boards/{arm => nxp}/mimxrt685_evk/init.c | 0 .../mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi} | 0 boards/nxp/mimxrt685_evk/mimxrt685_evk.dts | 387 ++++++ boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml | 34 + .../nxp/mimxrt685_evk/mimxrt685_evk_defconfig | 17 + .../mimxrt685_evk/pre_dt_board.cmake | 0 boards/nxp/mr_canhubk3/Kconfig.defconfig | 43 + boards/nxp/mr_canhubk3/Kconfig.mr_canhubk3 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boards/nxp/s32z2xxdc2/Kconfig.defconfig | 26 + boards/nxp/s32z2xxdc2/Kconfig.s32z2xxdc2 | 7 + .../s32z2xxdc2}/board.cmake | 0 boards/nxp/s32z2xxdc2/board.yml | 11 + boards/nxp/s32z2xxdc2/doc/index.rst | 310 +++++ boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi | 51 + .../s32z2xxdc2_s32z270_pinctrl.dtsi} | 0 .../s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts | 33 + .../s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml | 19 + .../s32z2xxdc2_s32z270_rtu0_B.overlay} | 0 .../s32z2xxdc2_s32z270_rtu0_D.overlay} | 0 .../s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml | 19 + .../s32z2xxdc2_s32z270_rtu0_defconfig | 11 + .../s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts | 35 + .../s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml | 19 + .../s32z2xxdc2_s32z270_rtu1_B.overlay} | 0 .../s32z2xxdc2_s32z270_rtu1_D.overlay} | 0 .../s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml | 19 + .../s32z2xxdc2_s32z270_rtu1_defconfig | 11 + .../s32z2xxdc2}/support/debug.cmm | 4 +- .../s32z2xxdc2}/support/flash.cmm | 4 +- .../s32z2xxdc2}/support/startup.cmm | 0 boards/{arm => nxp}/twr_ke18f/CMakeLists.txt | 0 boards/{arm => nxp}/twr_ke18f/Kconfig | 0 boards/nxp/twr_ke18f/Kconfig.defconfig | 17 + boards/nxp/twr_ke18f/Kconfig.twr_ke18f | 6 + boards/{arm => nxp}/twr_ke18f/board.cmake | 0 boards/nxp/twr_ke18f/board.yml | 5 + .../twr_ke18f/doc/TWR-KE18F-DEVICE.jpg | Bin boards/nxp/twr_ke18f/doc/index.rst | 254 ++++ .../twr_ke18f/dts/bindings/nxp,flexio.yaml | 0 .../twr_ke18f/dts/lpspi0_pcs2.overlay | 0 .../twr_ke18f/dts/lpspi1_pcs0.overlay | 0 .../twr_ke18f/dts/lpspi1_pcs0_pcs2.overlay | 0 .../twr_ke18f/dts/lpspi1_pcs2.overlay | 0 boards/{arm => nxp}/twr_ke18f/pinmux.c | 0 .../twr_ke18f/twr_ke18f-pinctrl.dtsi | 0 boards/{arm => nxp}/twr_ke18f/twr_ke18f.dts | 0 boards/{arm => nxp}/twr_ke18f/twr_ke18f.yaml | 0 boards/nxp/twr_ke18f/twr_ke18f_defconfig | 11 + .../twr_kv58f220m}/CMakeLists.txt | 0 boards/nxp/twr_kv58f220m/Kconfig.defconfig | 20 + .../nxp/twr_kv58f220m/Kconfig.twr_kv58f220m | 6 + boards/{arm => nxp}/twr_kv58f220m/board.cmake | 0 boards/nxp/twr_kv58f220m/board.yml | 5 + boards/nxp/twr_kv58f220m/doc/index.rst | 200 +++ .../twr_kv58f220m/doc/twr_kv58f220m.jpg | Bin .../twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi | 0 .../twr_kv58f220m/twr_kv58f220m.dts | 0 .../twr_kv58f220m/twr_kv58f220m.yaml | 0 .../twr_kv58f220m/twr_kv58f220m_defconfig | 3 - boards/nxp/ucans32k1sic/Kconfig.defconfig | 20 + boards/nxp/ucans32k1sic/Kconfig.ucans32k1sic | 6 + boards/{arm => nxp}/ucans32k1sic/board.cmake | 0 boards/nxp/ucans32k1sic/board.yml | 5 + .../doc/img/ucans32k1sic_top.webp | Bin boards/nxp/ucans32k1sic/doc/index.rst | 197 +++ .../ucans32k1sic/support/debug.cmm | 0 .../ucans32k1sic/support/flash.cmm | 0 .../ucans32k1sic/support/startup.cmm | 0 .../ucans32k1sic/ucans32k1sic-pinctrl.dtsi | 0 .../ucans32k1sic/ucans32k1sic.dts | 0 .../ucans32k1sic/ucans32k1sic.yaml | 0 .../nxp/ucans32k1sic/ucans32k1sic_defconfig | 17 + .../usb_kw24d512}/CMakeLists.txt | 0 boards/nxp/usb_kw24d512/Kconfig.defconfig | 28 + boards/nxp/usb_kw24d512/Kconfig.usb_kw24d512 | 6 + boards/{arm => nxp}/usb_kw24d512/board.cmake | 0 boards/nxp/usb_kw24d512/board.yml | 5 + boards/nxp/usb_kw24d512/doc/index.rst | 230 ++++ .../usb_kw24d512/usb_kw24d512-pinctrl.dtsi | 0 .../usb_kw24d512/usb_kw24d512.dts | 0 .../usb_kw24d512/usb_kw24d512.yaml | 0 .../nxp/usb_kw24d512/usb_kw24d512_defconfig | 10 + boards/nxp/vmu_rt1170/CMakeLists.txt | 26 + boards/nxp/vmu_rt1170/Kconfig.defconfig | 38 + boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 | 6 + boards/{arm => nxp}/vmu_rt1170/board.cmake | 0 boards/nxp/vmu_rt1170/board.yml | 5 + boards/{arm => nxp}/vmu_rt1170/doc/index.rst | 0 .../vmu_rt1170/doc/vmu_rt1170.jpg | Bin boards/nxp/vmu_rt1170/flexspi_nor_config.c | 149 +++ .../vmu_rt1170/vmu_rt1170-pinctrl.dtsi | 0 boards/{arm => nxp}/vmu_rt1170/vmu_rt1170.dts | 0 .../{arm => nxp}/vmu_rt1170/vmu_rt1170.dtsi | 0 .../{arm => nxp}/vmu_rt1170/vmu_rt1170.yaml | 2 +- .../vmu_rt1170/vmu_rt1170_defconfig | 2 - boards/olimex/index.rst | 10 + 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boards/posix/native_sim/board.cmake | 6 - .../posix/native_sim/native_sim_64_defconfig | 6 - boards/posix/native_sim/native_sim_defconfig | 6 - boards/posix/nrf_bsim/CMakeLists.txt | 80 -- boards/posix/nrf_bsim/Kconfig | 58 - boards/posix/nrf_bsim/Kconfig.board | 31 - boards/posix/nrf_bsim/Kconfig.defconfig | 94 -- boards/posix/nrf_bsim/board.cmake | 6 - boards/posix/nrf_bsim/nrf52_bsim_defconfig | 7 - .../nrf5340bsim_nrf5340_cpuapp_defconfig | 6 - .../nrf5340bsim_nrf5340_cpunet_defconfig | 6 - boards/posix/nrf_bsim/pre_dt_board.cmake | 7 - boards/posix/nrf_bsim/soc/pinctrl_soc.h | 13 - boards/{arc/iotdk => qemu/arc}/CMakeLists.txt | 0 boards/qemu/arc/Kconfig | 7 + boards/qemu/arc/Kconfig.defconfig | 17 + boards/qemu/arc/Kconfig.qemu_arc | 9 + .../qemu_arc => qemu/arc}/arc_mpu_regions.c | 0 boards/qemu/arc/board.cmake | 44 + boards/qemu/arc/board.yml | 10 + boards/qemu/arc/doc/index.rst | 102 ++ .../{arc/qemu_arc => qemu/arc}/qemu_arc.dtsi | 0 .../arc/qemu_arc_qemu_arc_em.dts} | 0 boards/qemu/arc/qemu_arc_qemu_arc_em.yaml | 14 + .../qemu/arc/qemu_arc_qemu_arc_em_defconfig | 10 + .../arc/qemu_arc_qemu_arc_hs.dts} | 0 boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml | 15 + .../arc/qemu_arc_qemu_arc_hs5x.dts} | 0 boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml | 14 + .../qemu/arc/qemu_arc_qemu_arc_hs5x_defconfig | 10 + .../arc/qemu_arc_qemu_arc_hs6x.dts} | 0 boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml | 14 + .../qemu/arc/qemu_arc_qemu_arc_hs6x_defconfig | 10 + .../qemu/arc/qemu_arc_qemu_arc_hs_defconfig | 10 + .../arc/qemu_arc_qemu_arc_hs_xip.dts} | 0 boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml | 14 + .../arc/qemu_arc_qemu_arc_hs_xip_defconfig | 10 + boards/qemu/cortex_a53/Kconfig | 12 + boards/qemu/cortex_a53/Kconfig.defconfig | 46 + .../qemu/cortex_a53/Kconfig.qemu_cortex_a53 | 5 + boards/qemu/cortex_a53/board.cmake | 30 + boards/qemu/cortex_a53/board.yml | 8 + .../cortex_a53}/doc/index.rst | 0 .../cortex_a53}/qemu_cortex_a53.dts | 0 .../cortex_a53}/qemu_cortex_a53.yaml | 0 .../qemu/cortex_a53/qemu_cortex_a53_defconfig | 17 + .../qemu_cortex_a53_qemu_cortex_a53_smp.dts} | 0 .../qemu_cortex_a53_qemu_cortex_a53_smp.yaml | 17 + ...u_cortex_a53_qemu_cortex_a53_smp_defconfig | 29 + .../qemu_cortex_a53_qemu_cortex_a53_xip.dts} | 0 .../qemu_cortex_a53_qemu_cortex_a53_xip.yaml | 14 + ...u_cortex_a53_qemu_cortex_a53_xip_defconfig | 20 + boards/qemu/cortex_a9/Kconfig | 9 + boards/qemu/cortex_a9/Kconfig.defconfig | 70 ++ boards/qemu/cortex_a9/Kconfig.qemu_cortex_a9 | 9 + boards/qemu/cortex_a9/board.cmake | 21 + boards/qemu/cortex_a9/board.yml | 5 + .../cortex_a9}/fdt-zynq7000s.dtb | Bin .../cortex_a9}/qemu_cortex_a9.dts | 0 .../cortex_a9}/qemu_cortex_a9.yaml | 0 .../cortex_a9}/qemu_cortex_a9_defconfig | 5 - .../cortex_m0}/CMakeLists.txt | 0 boards/qemu/cortex_m0/Kconfig | 17 + boards/qemu/cortex_m0/Kconfig.defconfig | 17 + boards/qemu/cortex_m0/Kconfig.qemu_cortex_m0 | 7 + .../cortex_m0}/board.cmake | 0 boards/qemu/cortex_m0/board.yml | 5 + .../cortex_m0}/doc/index.rst | 0 .../cortex_m0}/nrf_timer_timer.c | 0 .../cortex_m0}/pre_dt_board.cmake | 0 .../cortex_m0}/qemu_cortex_m0-pinctrl.dtsi | 0 .../cortex_m0}/qemu_cortex_m0.dts | 0 .../cortex_m0}/qemu_cortex_m0.yaml | 0 .../qemu/cortex_m0/qemu_cortex_m0_defconfig | 19 + boards/qemu/cortex_m3/Kconfig | 5 + boards/qemu/cortex_m3/Kconfig.defconfig | 15 + boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 | 7 + boards/qemu/cortex_m3/board.cmake | 13 + boards/qemu/cortex_m3/board.yml | 5 + .../cortex_m3}/doc/index.rst | 0 .../cortex_m3}/qemu_cortex_m3.dts | 1 + .../cortex_m3}/qemu_cortex_m3.yaml | 0 .../cortex_m3}/qemu_cortex_m3_defconfig | 3 +- boards/qemu/cortex_r5/Kconfig | 5 + boards/qemu/cortex_r5/Kconfig.defconfig | 16 + boards/qemu/cortex_r5/Kconfig.qemu_cortex_r5 | 5 + boards/qemu/cortex_r5/board.cmake | 21 + boards/qemu/cortex_r5/board.yml | 5 + .../cortex_r5}/doc/index.rst | 0 .../cortex_r5}/fdt-single_arch-zcu102-arm.dtb | Bin .../cortex_r5}/qemu_cortex_r5.dts | 0 .../cortex_r5}/qemu_cortex_r5.yaml | 0 .../cortex_r5}/qemu_cortex_r5_defconfig | 2 - boards/qemu/index.rst | 10 + boards/qemu/kvm_arm64/Kconfig | 6 + boards/qemu/kvm_arm64/Kconfig.defconfig | 9 + boards/qemu/kvm_arm64/Kconfig.qemu_kvm_arm64 | 5 + .../kvm_arm64}/board.cmake | 0 boards/qemu/kvm_arm64/board.yml | 5 + .../kvm_arm64}/doc/index.rst | 0 .../kvm_arm64}/qemu_kvm_arm64.dts | 0 .../kvm_arm64}/qemu_kvm_arm64.yaml | 0 .../kvm_arm64}/qemu_kvm_arm64_defconfig | 2 - boards/qemu/leon3/Kconfig | 7 + boards/qemu/leon3/Kconfig.defconfig | 10 + boards/qemu/leon3/Kconfig.qemu_leon3 | 6 + .../qemu_leon3 => qemu/leon3}/board.cmake | 0 boards/qemu/leon3/board.yml | 5 + .../qemu_leon3 => qemu/leon3}/doc/index.rst | 0 .../qemu_leon3 => qemu/leon3}/qemu_leon3.dts | 0 .../qemu_leon3 => qemu/leon3}/qemu_leon3.yaml | 0 .../leon3}/qemu_leon3_defconfig | 2 - boards/qemu/malta/Kconfig | 9 + boards/qemu/malta/Kconfig.defconfig | 12 + boards/qemu/malta/Kconfig.qemu_malta | 8 + .../qemu_malta => qemu/malta}/board.cmake | 0 boards/qemu/malta/board.yml | 7 + boards/qemu/malta/doc/index.rst | 106 ++ .../qemu_malta => qemu/malta}/qemu_malta.dts | 0 .../qemu_malta => qemu/malta}/qemu_malta.yaml | 0 boards/qemu/malta/qemu_malta_defconfig | 6 + .../malta/qemu_malta_qemu_malta_be.dts} | 0 .../qemu/malta/qemu_malta_qemu_malta_be.yaml | 16 + .../malta/qemu_malta_qemu_malta_be_defconfig | 6 + boards/qemu/nios2/Kconfig | 5 + boards/qemu/nios2/Kconfig.defconfig | 9 + boards/qemu/nios2/Kconfig.qemu_nios2 | 5 + boards/qemu/nios2/board.cmake | 13 + boards/qemu/nios2/board.yml | 5 + .../qemu_nios2 => qemu/nios2}/doc/index.rst | 0 .../qemu_nios2 => qemu/nios2}/qemu_nios2.dts | 0 .../qemu_nios2 => qemu/nios2}/qemu_nios2.yaml | 0 .../nios2}/qemu_nios2_defconfig | 3 +- boards/qemu/riscv32/Kconfig | 5 + boards/qemu/riscv32/Kconfig.defconfig | 19 + boards/qemu/riscv32/Kconfig.qemu_riscv32 | 5 + boards/qemu/riscv32/board.cmake | 14 + boards/qemu/riscv32/board.yml | 7 + .../riscv32}/doc/index.rst | 0 .../riscv32}/qemu_riscv32.dts | 0 .../riscv32}/qemu_riscv32.yaml | 0 boards/qemu/riscv32/qemu_riscv32_defconfig | 8 + .../qemu_riscv32_qemu_virt_riscv32_smp.yaml | 16 + ...mu_riscv32_qemu_virt_riscv32_smp_defconfig | 6 + boards/qemu/riscv32_xip/Kconfig | 5 + boards/qemu/riscv32_xip/Kconfig.defconfig | 16 + .../qemu/riscv32_xip/Kconfig.qemu_riscv32_xip | 5 + boards/qemu/riscv32_xip/board.cmake | 12 + boards/qemu/riscv32_xip/board.yml | 5 + boards/qemu/riscv32_xip/doc/index.rst | 55 + .../qemu_riscv32_xip-pinctrl.dtsi | 0 .../riscv32_xip}/qemu_riscv32_xip.dts | 0 .../riscv32_xip}/qemu_riscv32_xip.yaml | 0 .../riscv32_xip/qemu_riscv32_xip_defconfig | 11 + boards/qemu/riscv32e/Kconfig | 5 + boards/qemu/riscv32e/Kconfig.defconfig | 16 + boards/qemu/riscv32e/Kconfig.qemu_riscv32e | 5 + .../riscv32e}/board.cmake | 0 boards/qemu/riscv32e/board.yml | 5 + .../riscv32e}/doc/index.rst | 0 .../riscv32e}/qemu_riscv32e.dts | 0 .../riscv32e}/qemu_riscv32e.yaml | 0 .../riscv32e}/qemu_riscv32e_defconfig | 2 - boards/qemu/riscv64/Kconfig | 5 + boards/qemu/riscv64/Kconfig.defconfig | 15 + boards/qemu/riscv64/Kconfig.qemu_riscv64 | 5 + .../qemu_riscv64 => qemu/riscv64}/board.cmake | 0 boards/qemu/riscv64/board.yml | 7 + .../riscv64}/doc/index.rst | 0 .../riscv64}/qemu_riscv64.dts | 0 .../riscv64}/qemu_riscv64.yaml | 0 boards/qemu/riscv64/qemu_riscv64_defconfig | 9 + .../qemu_riscv64_qemu_virt_riscv64_smp.yaml | 15 + ...mu_riscv64_qemu_virt_riscv64_smp_defconfig | 6 + boards/qemu/x86/CMakeLists.txt | 14 + boards/qemu/x86/Kconfig | 19 + boards/qemu/x86/Kconfig.defconfig | 113 ++ boards/qemu/x86/Kconfig.qemu_x86 | 6 + boards/qemu/x86/Kconfig.qemu_x86_64 | 6 + boards/qemu/x86/Kconfig.qemu_x86_lakemont | 6 + boards/qemu/x86/Kconfig.qemu_x86_tiny | 6 + boards/qemu/x86/board.cmake | 88 ++ boards/qemu/x86/board.yml | 25 + .../{x86/qemu_x86 => qemu/x86}/doc/index.rst | 0 .../{x86/qemu_x86 => qemu/x86}/qemu_x86.dts | 3 +- .../{x86/qemu_x86 => qemu/x86}/qemu_x86.yaml | 0 .../qemu_x86 => qemu/x86}/qemu_x86_64.dts | 0 .../qemu_x86 => qemu/x86}/qemu_x86_64.yaml | 0 .../x86/qemu_x86_64_atom_nokpti.dts} | 0 boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml | 18 + .../x86/qemu_x86_64_atom_nokpti_defconfig | 4 + .../x86}/qemu_x86_64_defconfig | 3 +- .../x86/qemu_x86_atom_nokpti.dts} | 0 boards/qemu/x86/qemu_x86_atom_nokpti.yaml | 16 + .../qemu/x86/qemu_x86_atom_nokpti_defconfig | 4 + boards/qemu/x86/qemu_x86_atom_nommu.dts | 4 + boards/qemu/x86/qemu_x86_atom_nommu.yaml | 14 + boards/qemu/x86/qemu_x86_atom_nommu_defconfig | 7 + .../x86/qemu_x86_atom_nopae.dts} | 0 boards/qemu/x86/qemu_x86_atom_nopae.yaml | 16 + boards/qemu/x86/qemu_x86_atom_nopae_defconfig | 4 + .../x86/qemu_x86_atom_virt.dts} | 0 boards/qemu/x86/qemu_x86_atom_virt.yaml | 16 + boards/qemu/x86/qemu_x86_atom_virt_defconfig | 10 + .../x86/qemu_x86_atom_xip.dts} | 0 boards/qemu/x86/qemu_x86_atom_xip.yaml | 13 + boards/qemu/x86/qemu_x86_atom_xip_defconfig | 5 + .../qemu_x86 => qemu/x86}/qemu_x86_defconfig | 3 +- .../x86}/qemu_x86_lakemont.dts | 0 .../x86}/qemu_x86_lakemont.yaml | 0 .../x86}/qemu_x86_lakemont_defconfig | 3 +- .../qemu_x86 => qemu/x86}/qemu_x86_tiny.dts | 0 .../qemu_x86 => qemu/x86}/qemu_x86_tiny.ld | 0 .../qemu_x86 => qemu/x86}/qemu_x86_tiny.yaml | 0 .../x86}/qemu_x86_tiny_defconfig | 3 +- boards/qemu/xtensa/Kconfig | 9 + boards/qemu/xtensa/Kconfig.defconfig | 12 + boards/qemu/xtensa/Kconfig.qemu_xtensa | 7 + boards/qemu/xtensa/board.cmake | 16 + boards/qemu/xtensa/board.yml | 7 + .../qemu_xtensa => qemu/xtensa}/doc/index.rst | 0 .../xtensa}/qemu_xtensa.dts | 0 .../xtensa}/qemu_xtensa.yaml | 0 .../xtensa/qemu_xtensa_dc233c_mmu.dts} | 0 .../qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml | 13 + .../xtensa/qemu_xtensa_dc233c_mmu_defconfig | 10 + .../xtensa}/qemu_xtensa_defconfig | 2 - .../decawave_dwm1001_dev/Kconfig | 0 .../Kconfig.decawave_dwm1001_dev | 7 + .../decawave_dwm1001_dev/Kconfig.defconfig | 18 + .../decawave_dwm1001_dev/board.cmake | 0 boards/qorvo/decawave_dwm1001_dev/board.yml | 5 + .../decawave_dwm1001_dev-pinctrl.dtsi | 0 .../decawave_dwm1001_dev.dts | 0 .../decawave_dwm1001_dev.yaml | 0 .../decawave_dwm1001_dev_defconfig | 18 + .../decawave_dwm1001_dev/doc/index.rst | 0 .../decawave_dwm1001_dev}/pre_dt_board.cmake | 0 boards/qorvo/index.rst | 10 + boards/quicklogic/index.rst | 10 + boards/{arm => quicklogic}/qomu/Kconfig | 0 boards/quicklogic/qomu/Kconfig.qomu | 7 + boards/quicklogic/qomu/board.yml | 5 + .../qomu/doc/img/qomu-board.png | Bin boards/{arm => quicklogic}/qomu/doc/index.rst | 0 boards/{arm => quicklogic}/qomu/qomu.dts | 0 boards/{arm => quicklogic}/qomu/qomu.yaml | 0 .../{arm => quicklogic}/qomu/qomu_defconfig | 6 +- .../{arm => quicklogic}/quick_feather/Kconfig | 0 .../quick_feather/Kconfig.quick_feather | 7 + boards/quicklogic/quick_feather/board.yml | 5 + .../quick_feather/doc/img/feather-board.jpg | Bin boards/quicklogic/quick_feather/doc/index.rst | 125 ++ .../quick_feather/quick_feather.dts | 0 .../quick_feather/quick_feather.yaml | 0 .../quick_feather/quick_feather_defconfig | 6 +- boards/rak/index.rst | 10 + boards/rak/rak4631/Kconfig.defconfig | 11 + boards/rak/rak4631/Kconfig.rak4631 | 7 + .../rak4631}/board.cmake | 0 boards/rak/rak4631/board.yml | 5 + .../rak4631}/doc/img/rak4631-front-parts.jpg | Bin boards/rak/rak4631/doc/index.rst | 154 +++ .../rak4631}/pre_dt_board.cmake | 0 .../rak4631}/rak4631_nrf52840-pinctrl.dtsi | 0 .../rak4631}/rak4631_nrf52840.dts | 0 .../rak4631}/rak4631_nrf52840.yaml | 2 +- .../rak4631}/rak4631_nrf52840_defconfig | 3 - boards/rak/rak5010/Kconfig.defconfig | 11 + boards/rak/rak5010/Kconfig.rak5010 | 7 + .../rak5010}/board.cmake | 0 boards/rak/rak5010/board.yml | 5 + .../rak5010}/doc/img/rak5010-front-parts.jpg | Bin boards/rak/rak5010/doc/index.rst | 159 +++ .../rak5010}/pre_dt_board.cmake | 0 .../rak5010}/rak5010_nrf52840-pinctrl.dtsi | 0 .../rak5010}/rak5010_nrf52840.dts | 0 .../rak5010}/rak5010_nrf52840.yaml | 2 +- .../rak5010}/rak5010_nrf52840_defconfig | 3 - boards/raspberrypi/index.rst | 10 + .../rpi_4b/CMakeLists.txt} | 0 boards/raspberrypi/rpi_4b/Kconfig.defconfig | 2 + boards/raspberrypi/rpi_4b/Kconfig.rpi_4b | 5 + .../rpi_4b}/board.cmake | 0 boards/raspberrypi/rpi_4b/board.yml | 5 + boards/raspberrypi/rpi_4b/doc/index.rst | 70 ++ .../{arm64 => raspberrypi}/rpi_4b/rpi_4b.dts | 0 .../{arm64 => raspberrypi}/rpi_4b/rpi_4b.yaml | 0 .../rpi_4b/rpi_4b_defconfig | 2 - boards/raspberrypi/rpi_pico/Kconfig.defconfig | 19 + boards/raspberrypi/rpi_pico/Kconfig.rpi_pico | 5 + .../{arm => raspberrypi}/rpi_pico/board.cmake | 0 boards/raspberrypi/rpi_pico/board.yml | 7 + .../rpi_pico/doc/img/rpi_pico.jpg | Bin .../rpi_pico/doc/img/rpi_pico_w.jpg | Bin .../rpi_pico/doc/index.rst | 0 .../rpi_pico/rpi_pico-common.dtsi | 0 .../rpi_pico/rpi_pico-pinctrl.dtsi | 0 .../rpi_pico/rpi_pico.dts | 4 + .../rpi_pico/rpi_pico.yaml | 0 .../rpi_pico/rpi_pico_defconfig | 3 - .../rpi_pico/rpi_pico_rp2040_w.dts} | 0 .../rpi_pico/rpi_pico_rp2040_w.yaml | 24 + .../rpi_pico/rpi_pico_rp2040_w_defconfig | 11 + .../rpi_pico/support/openocd.cfg | 0 boards/raytac/index.rst | 10 + boards/raytac/mdbt50q_db_33/Kconfig | 10 + boards/raytac/mdbt50q_db_33/Kconfig.defconfig | 11 + .../Kconfig.raytac_mdbt50q_db_33 | 7 + .../mdbt50q_db_33}/board.cmake | 0 boards/raytac/mdbt50q_db_33/board.yml | 5 + .../mdbt50q_db_33}/doc/img/mdbt50q_db_33.jpg | Bin boards/raytac/mdbt50q_db_33/doc/index.rst | 213 ++++ .../mdbt50q_db_33}/pre_dt_board.cmake | 0 ...raytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi | 0 .../raytac_mdbt50q_db_33_nrf52833.dts | 0 .../raytac_mdbt50q_db_33_nrf52833.yaml | 2 +- .../raytac_mdbt50q_db_33_nrf52833_defconfig | 4 - boards/raytac/mdbt50q_db_40/Kconfig | 18 + boards/raytac/mdbt50q_db_40/Kconfig.defconfig | 11 + .../Kconfig.raytac_mdbt50q_db_40 | 7 + .../mdbt50q_db_40}/board.cmake | 0 boards/raytac/mdbt50q_db_40/board.yml | 5 + .../mdbt50q_db_40}/doc/img/mdbt50q_db_40.jpg | Bin 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.../mdbt53v_db_40}/pre_dt_board.cmake | 0 .../raytac_mdbt53v_db_40_nrf5340_cpuapp.dts | 0 .../raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml | 2 +- ...v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi | 0 ...ac_mdbt53v_db_40_nrf5340_cpuapp_common.dts | 0 ...tac_mdbt53v_db_40_nrf5340_cpuapp_defconfig | 20 + ...raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts | 0 ...aytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml | 2 +- ..._mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig | 23 + ...3v_db_40_nrf5340_cpuapp_partition_conf.dts | 0 ..._mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi | 0 .../raytac_mdbt53v_db_40_nrf5340_cpunet.dts | 0 .../raytac_mdbt53v_db_40_nrf5340_cpunet.yaml | 2 +- ...ac_mdbt53v_db_40_nrf5340_cpunet_common.dts | 0 ...tac_mdbt53v_db_40_nrf5340_cpunet_defconfig | 17 + ...aytac_mdbt53v_db_40_nrf5340_cpunet_reset.c | 0 .../raytac_mdbt53v_db_40_nrf5340_defconfig} | 0 ...b_40_nrf5340_shared_sram_planning_conf.dts | 0 .../da14695_dk_usb/Kconfig.da14695_dk_usb | 7 + .../da14695_dk_usb/board.cmake | 0 boards/renesas/da14695_dk_usb/board.yml | 5 + .../da14695_dk_usb-pinctrl.dtsi | 0 .../da14695_dk_usb/da14695_dk_usb.dts | 0 .../da14695_dk_usb/da14695_dk_usb.yaml | 0 .../da14695_dk_usb/da14695_dk_usb_defconfig | 4 - .../doc/da14695-00hqdevkt-u-usb-board.jpg | Bin .../da14695_dk_usb/doc/index.rst | 0 .../da1469x_dk_pro/Kconfig.da1469x_dk_pro | 7 + .../da1469x_dk_pro/board.cmake | 0 boards/renesas/da1469x_dk_pro/board.yml | 5 + .../da1469x_dk_pro-pinctrl.dtsi | 0 .../da1469x_dk_pro/da1469x_dk_pro.dts | 0 .../da1469x_dk_pro/da1469x_dk_pro.yaml | 0 .../da1469x_dk_pro/da1469x_dk_pro_defconfig | 14 + .../doc/da14695-00hqdevkt-board.jpg | Bin .../da1469x_dk_pro/doc/index.rst | 0 boards/renesas/index.rst | 10 + boards/renesas/rcar_h3ulcb/Kconfig.defconfig | 9 + .../renesas/rcar_h3ulcb/Kconfig.rcar_h3ulcb | 6 + boards/renesas/rcar_h3ulcb/board.cmake | 6 + boards/renesas/rcar_h3ulcb/board.yml | 5 + .../doc/img/rcar_h3ulcb_bottom.jpg | Bin .../doc/img/rcar_h3ulcb_features.jpg | Bin .../doc/img/rcar_h3ulcb_starter_kit.jpg | Bin .../rcar_h3ulcb}/doc/img/rcar_h3ulcb_top.jpg | Bin .../rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst | 85 ++ .../rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst | 276 +++++ .../rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi} | 0 .../rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts | 32 + .../rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.yaml | 17 + .../rcar_h3ulcb_r8a77951_a57_defconfig | 21 + .../rcar_h3ulcb_r8a77951_r7-pinctrl.dtsi} | 0 .../rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.dts | 85 ++ .../rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.yaml | 17 + .../rcar_h3ulcb_r8a77951_r7_defconfig | 10 + .../rcar_salvator_x/Kconfig.rcar_salvator_x | 5 + .../rcar_salvator_x}/board.cmake | 0 boards/renesas/rcar_salvator_x/board.yml | 5 + .../img/r-car-h3-salvator-x-connections.jpg | Bin .../doc/img/rcar_h3_features.jpg | Bin .../doc/img/rcar_h3_salvatorx.jpg | Bin .../rcar_salvator_x/doc/rcar_salvator_x.rst | 183 +++ .../rcar_salvator_x_r8a77951_r7-pinctrl.dtsi} | 0 .../rcar_salvator_x_r8a77951_r7.dts | 93 ++ .../rcar_salvator_x_r8a77951_r7.yaml | 16 + .../rcar_salvator_x_r8a77951_r7_defconfig | 10 + .../rcar_salvator_x}/support/openocd.cfg | 0 .../rcar_salvator_xs/Kconfig.defconfig | 9 + .../rcar_salvator_xs/Kconfig.rcar_salvator_xs | 5 + boards/renesas/rcar_salvator_xs/board.yml | 5 + boards/renesas/rcar_salvator_xs/doc/index.rst | 68 ++ .../rcar_salvator_xs-pinctrl.dtsi} | 0 .../rcar_salvator_xs/rcar_salvator_xs.dts | 32 + .../rcar_salvator_xs/rcar_salvator_xs.yaml | 17 + .../rcar_salvator_xs_defconfig | 21 + .../rcar_spider_s4/Kconfig.rcar_spider_s4 | 5 + .../rcar_spider_s4}/board.cmake | 0 boards/renesas/rcar_spider_s4/board.yml | 5 + .../doc/img/rcar_s4_block_diagram.jpg | Bin .../doc/img/rcar_s4_spider_full.jpg | Bin .../rcar_spider_s4}/doc/rcar_spider.rst | 10 +- .../rcar_spider_s4-pinctrl.dtsi} | 0 .../renesas/rcar_spider_s4/rcar_spider_s4.dts | 58 + .../rcar_spider_s4/rcar_spider_s4.yaml | 11 + .../rcar_spider_s4/rcar_spider_s4_defconfig | 10 + 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| 13 - .../rv32m1_vega_zero_riscy_defconfig | 10 - .../sparkfun_red_v_things_plus/Kconfig.board | 6 - .../Kconfig.defconfig | 21 - .../sparkfun_red_v_things_plus/board.cmake | 8 - .../sparkfun_red_v_things_plus_defconfig | 14 - boards/riscv/stamp_c3/Kconfig.board | 12 - boards/riscv/stamp_c3/Kconfig.defconfig | 23 - boards/riscv/stamp_c3/doc/index.rst | 205 ---- boards/riscv/stamp_c3/stamp_c3_defconfig | 11 - boards/riscv/titanium_ti60_f225/Kconfig.board | 6 - .../titanium_ti60_f225/Kconfig.defconfig | 9 - boards/riscv/tlsr9518adk80d/Kconfig.board | 6 - boards/riscv/tlsr9518adk80d/Kconfig.defconfig | 41 - boards/riscv/tlsr9518adk80d/doc/index.rst | 267 ---- boards/riscv/xiao_esp32c3/Kconfig.board | 10 - boards/riscv/xiao_esp32c3/Kconfig.defconfig | 17 - boards/riscv/xiao_esp32c3/doc/index.rst | 218 ---- .../riscv/xiao_esp32c3/xiao_esp32c3_defconfig | 11 - boards/ronoth/index.rst | 10 + boards/ronoth/lodev/Kconfig.defconfig | 11 + boards/ronoth/lodev/Kconfig.ronoth_lodev | 5 + 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.../esp32s3_devkitm/esp32s3_devkitm.dts | 183 --- .../esp32s3_devkitm/esp32s3_devkitm.yaml | 23 - .../esp32s3_devkitm_appcpu.dts | 34 - .../esp32s3_devkitm_appcpu.yaml | 26 - .../esp32s3_devkitm_appcpu_defconfig | 9 - .../esp32s3_devkitm/esp32s3_devkitm_defconfig | 12 - .../xtensa/esp32s3_luatos_core/Kconfig.board | 15 - .../esp32s3_luatos_core/Kconfig.defconfig | 22 - .../xtensa/esp32s3_luatos_core/doc/index.rst | 292 ----- .../esp32s3_luatos_core.dts | 30 - .../esp32s3_luatos_core.yaml | 22 - .../esp32s3_luatos_core_defconfig | 12 - .../esp32s3_luatos_core_usb.dts | 37 - .../esp32s3_luatos_core_usb.yaml | 22 - .../esp32s3_luatos_core_usb_defconfig | 12 - boards/xtensa/esp_wrover_kit/Kconfig.board | 12 - .../xtensa/esp_wrover_kit/Kconfig.defconfig | 22 - boards/xtensa/esp_wrover_kit/doc/index.rst | 658 ---------- .../xtensa/esp_wrover_kit/esp_wrover_kit.dts | 227 ---- .../xtensa/esp_wrover_kit/esp_wrover_kit.yaml | 23 - .../esp_wrover_kit/esp_wrover_kit_defconfig | 12 - .../heltec_wifi_lora32_v2/Kconfig.board | 12 - .../heltec_wifi_lora32_v2/Kconfig.defconfig | 22 - .../heltec_wifi_lora32_v2/doc/index.rst | 208 ---- .../heltec_wifi_lora32_v2.dts | 161 --- .../heltec_wifi_lora32_v2.yaml | 17 - .../heltec_wifi_lora32_v2_defconfig | 12 - .../Kconfig.board | 13 - .../Kconfig.defconfig | 23 - .../doc/index.rst | 306 ----- .../heltec_wireless_stick_lite_v3.dts | 216 ---- .../heltec_wireless_stick_lite_v3.yaml | 22 - .../heltec_wireless_stick_lite_v3_defconfig | 14 - boards/xtensa/index.rst | 10 - .../intel_adsp_ace15_mtpm/Kconfig.board | 8 - .../intel_adsp_ace15_mtpm/Kconfig.defconfig | 17 - .../xtensa/intel_adsp_ace15_mtpm/board.cmake | 9 - .../intel_adsp_ace15_mtpm_defconfig | 16 - .../intel_adsp_ace15_mtpm/pre_dt_board.cmake | 6 - .../xtensa/intel_adsp_ace20_lnl/Kconfig.board | 8 - .../intel_adsp_ace20_lnl/Kconfig.defconfig | 10 - .../xtensa/intel_adsp_ace20_lnl/board.cmake | 7 - .../intel_adsp_ace20_lnl_defconfig | 16 - boards/xtensa/intel_adsp_cavs25/Kconfig.board | 12 - .../intel_adsp_cavs25/Kconfig.defconfig | 20 - boards/xtensa/intel_adsp_cavs25/board.cmake | 20 - .../intel_adsp_cavs25_tgph_defconfig | 24 - .../intel_adsp_cavs25/pre_dt_board.cmake | 6 - boards/xtensa/kincony_kc868_a32/Kconfig.board | 10 - .../kincony_kc868_a32/Kconfig.defconfig | 15 - boards/xtensa/kincony_kc868_a32/doc/index.rst | 97 -- .../kincony_kc868_a32/kincony_kc868_a32.dts | 214 ---- .../kincony_kc868_a32/kincony_kc868_a32.yaml | 19 - .../kincony_kc868_a32_defconfig | 14 - boards/xtensa/m5stack_atoms3/Kconfig.board | 12 - .../xtensa/m5stack_atoms3/Kconfig.defconfig | 31 - boards/xtensa/m5stack_atoms3/doc/index.rst | 136 --- .../xtensa/m5stack_atoms3/m5stack_atoms3.dts | 187 --- .../xtensa/m5stack_atoms3/m5stack_atoms3.yaml | 21 - .../m5stack_atoms3/m5stack_atoms3_defconfig | 13 - .../xtensa/m5stack_atoms3_lite/Kconfig.board | 12 - .../m5stack_atoms3_lite/Kconfig.defconfig | 26 - .../xtensa/m5stack_atoms3_lite/doc/index.rst | 134 -- .../m5stack_atoms3_lite.dts | 155 --- .../m5stack_atoms3_lite.yaml | 23 - .../m5stack_atoms3_lite_defconfig | 12 - boards/xtensa/m5stack_core2/Kconfig.board | 12 - boards/xtensa/m5stack_core2/Kconfig.defconfig | 53 - boards/xtensa/m5stack_core2/doc/index.rst | 197 --- boards/xtensa/m5stack_core2/m5stack_core2.dts | 285 ----- .../xtensa/m5stack_core2/m5stack_core2.yaml | 20 - .../m5stack_core2/m5stack_core2_defconfig | 19 - boards/xtensa/m5stack_stamps3/Kconfig.board | 12 - .../xtensa/m5stack_stamps3/Kconfig.defconfig | 27 - boards/xtensa/m5stack_stamps3/doc/index.rst | 199 --- .../m5stack_stamps3/m5stack_stamps3.dts | 195 --- .../m5stack_stamps3/m5stack_stamps3.yaml | 20 - .../m5stack_stamps3/m5stack_stamps3_defconfig | 14 - boards/xtensa/m5stickc_plus/Kconfig.board | 12 - boards/xtensa/m5stickc_plus/Kconfig.defconfig | 22 - boards/xtensa/m5stickc_plus/doc/index.rst | 218 ---- boards/xtensa/m5stickc_plus/m5stickc_plus.dts | 167 --- .../xtensa/m5stickc_plus/m5stickc_plus.yaml | 19 - .../m5stickc_plus/m5stickc_plus_defconfig | 13 - boards/xtensa/nxp_adsp_imx8/Kconfig.board | 9 - boards/xtensa/nxp_adsp_imx8/Kconfig.defconfig | 10 - boards/xtensa/nxp_adsp_imx8/board.cmake | 6 - boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.dts | 28 - .../xtensa/nxp_adsp_imx8/nxp_adsp_imx8.yaml | 11 - .../nxp_adsp_imx8/nxp_adsp_imx8_defconfig | 22 - boards/xtensa/nxp_adsp_imx8m/Kconfig.board | 10 - .../xtensa/nxp_adsp_imx8m/Kconfig.defconfig | 10 - boards/xtensa/nxp_adsp_imx8m/board.cmake | 6 - .../xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.dts | 41 - .../xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.yaml | 16 - .../nxp_adsp_imx8m/nxp_adsp_imx8m_defconfig | 29 - boards/xtensa/nxp_adsp_imx8ulp/Kconfig.board | 7 - .../xtensa/nxp_adsp_imx8ulp/Kconfig.defconfig | 10 - boards/xtensa/nxp_adsp_imx8ulp/board.cmake | 6 - .../nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.dts | 18 - .../nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.yaml | 10 - .../nxp_adsp_imx8ulp_defconfig | 11 - boards/xtensa/nxp_adsp_imx8x/Kconfig.board | 9 - .../xtensa/nxp_adsp_imx8x/Kconfig.defconfig | 10 - boards/xtensa/nxp_adsp_imx8x/board.cmake | 6 - .../xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.dts | 28 - .../xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.yaml | 11 - .../nxp_adsp_imx8x/nxp_adsp_imx8x_defconfig | 22 - boards/xtensa/nxp_adsp_rt595/Kconfig | 41 - boards/xtensa/nxp_adsp_rt595/Kconfig.board | 6 - .../xtensa/nxp_adsp_rt595/Kconfig.defconfig | 9 - .../xtensa/nxp_adsp_rt595/nxp_adsp_rt595.yaml | 10 - .../nxp_adsp_rt595/nxp_adsp_rt595_defconfig | 7 - boards/xtensa/odroid_go/Kconfig.board | 12 - boards/xtensa/odroid_go/Kconfig.defconfig | 28 - boards/xtensa/odroid_go/doc/index.rst | 245 ---- boards/xtensa/odroid_go/odroid_go.dts | 215 ---- boards/xtensa/odroid_go/odroid_go.yaml | 18 - boards/xtensa/odroid_go/odroid_go_defconfig | 15 - boards/xtensa/olimex_esp32_evb/Kconfig.board | 12 - .../xtensa/olimex_esp32_evb/Kconfig.defconfig | 25 - boards/xtensa/olimex_esp32_evb/doc/index.rst | 265 ---- .../olimex_esp32_evb/olimex_esp32_evb.yaml | 20 - .../olimex_esp32_evb_defconfig | 12 - boards/xtensa/qemu_xtensa/Kconfig | 4 - boards/xtensa/qemu_xtensa/Kconfig.board | 17 - boards/xtensa/qemu_xtensa/Kconfig.defconfig | 28 - boards/xtensa/qemu_xtensa/board.cmake | 16 - .../xtensa/qemu_xtensa/qemu_xtensa_mmu.yaml | 13 - .../qemu_xtensa/qemu_xtensa_mmu_defconfig | 12 - boards/xtensa/xiao_esp32s3/Kconfig.board | 12 - boards/xtensa/xiao_esp32s3/Kconfig.defconfig | 20 - boards/xtensa/xiao_esp32s3/doc/index.rst | 243 ---- boards/xtensa/xiao_esp32s3/xiao_esp32s3.dts | 138 --- boards/xtensa/xiao_esp32s3/xiao_esp32s3.yaml | 22 - .../xiao_esp32s3/xiao_esp32s3_defconfig | 9 - boards/xtensa/xt-sim/Kconfig.board | 8 - boards/xtensa/xt-sim/Kconfig.defconfig | 8 - boards/xtensa/yd_esp32/Kconfig.board | 12 - boards/xtensa/yd_esp32/Kconfig.defconfig | 22 - boards/xtensa/yd_esp32/doc/index.rst | 310 ----- boards/xtensa/yd_esp32/yd_esp32.dts | 184 --- boards/xtensa/yd_esp32/yd_esp32.yaml | 24 - boards/xtensa/yd_esp32/yd_esp32_defconfig | 13 - cmake/compiler/gcc/target_arc.cmake | 4 +- cmake/modules/FindDeprecated.cmake | 2 +- cmake/modules/FindHostTools.cmake | 5 +- cmake/modules/arch.cmake | 48 - cmake/modules/arch_v1.cmake | 54 + cmake/modules/arch_v2.cmake | 48 + cmake/modules/boards.cmake | 253 +++- cmake/modules/configuration_files.cmake | 9 +- cmake/modules/dts.cmake | 21 +- cmake/modules/extensions.cmake | 102 +- cmake/modules/hwm_v2.cmake | 118 ++ cmake/modules/kconfig.cmake | 82 +- cmake/modules/pre_dt.cmake | 10 +- cmake/modules/soc.cmake | 71 -- cmake/modules/soc_v1.cmake | 78 ++ cmake/modules/soc_v2.cmake | 31 + cmake/modules/unittest.cmake | 2 +- cmake/modules/zephyr_default.cmake | 7 +- doc/_extensions/zephyr/kconfig/__init__.py | 52 +- .../bluetooth/autopts/autopts-win10.rst | 2 +- doc/develop/beyond-GSG.rst | 4 +- doc/develop/flash_debug/nordic_segger.rst | 2 +- doc/develop/getting_started/index.rst | 11 + doc/develop/sca/sparse.rst | 2 +- doc/develop/test/coverage.rst | 2 +- doc/develop/test/twister.rst | 18 +- doc/hardware/porting/board_porting.rst | 669 +++++----- doc/services/device_mgmt/mcumgr.rst | 2 +- doc/services/tfm/requirements.rst | 12 +- drivers/can/Kconfig.mcux | 14 +- drivers/clock_control/Kconfig.rcar | 2 +- drivers/clock_control/Kconfig.smartbond | 2 +- .../clock_control/clock_control_mchp_xec.c | 8 +- .../clock_control/clock_control_mcux_ccm.c | 2 +- .../clock_control_mcux_ccm_rev2.c | 6 +- .../clock_control/clock_control_mcux_syscon.c | 2 +- drivers/clock_control/clock_stm32_ll_h7.c | 4 +- drivers/counter/counter_cmos.c | 7 +- drivers/dai/intel/dmic/dmic.c | 4 +- drivers/dai/intel/dmic/dmic_nhlt.c | 18 +- drivers/dai/intel/ssp/Kconfig.ssp | 2 +- drivers/dai/intel/ssp/ssp.c | 6 +- drivers/dai/intel/ssp/ssp.h | 2 +- drivers/disk/nvme/nvme_controller.c | 1 - drivers/dma/Kconfig.intel_adsp_gpdma | 2 +- drivers/dma/Kconfig.mcux_edma | 4 +- drivers/dma/dma_intel_adsp_gpdma.c | 30 +- drivers/dma/dma_intel_adsp_hda_host_in.c | 3 +- drivers/dma/dma_intel_adsp_hda_host_out.c | 3 +- drivers/espi/Kconfig.xec | 4 +- drivers/ethernet/Kconfig.mcux | 4 +- drivers/ethernet/eth_mcux.c | 18 +- drivers/ethernet/eth_nxp_enet.c | 4 +- drivers/ethernet/eth_nxp_s32_gmac.c | 4 +- drivers/ethernet/eth_sam_gmac.c | 12 +- drivers/ethernet/eth_sam_gmac_priv.h | 2 +- drivers/flash/Kconfig.it8xxx2 | 3 + drivers/flash/Kconfig.mcux | 26 - drivers/gpio/gpio_mcux_igpio.c | 8 +- drivers/hwinfo/Kconfig | 18 +- drivers/hwinfo/hwinfo_imxrt.c | 2 +- drivers/i2c/Kconfig.nrfx | 2 +- drivers/i2s/i2s_mcux_sai.c | 4 +- drivers/interrupt_controller/Kconfig.esp32 | 2 +- drivers/led/led_mchp_xec.c | 4 +- drivers/mdio/mdio_sam.c | 8 +- drivers/mm/mm_drv_intel_adsp_mtl_tlb.c | 8 +- drivers/pinctrl/pinctrl_gecko.c | 14 +- drivers/pinctrl/pinctrl_imx.c | 14 +- drivers/ps2/Kconfig.xec | 2 +- drivers/pwm/Kconfig.rcar | 2 +- drivers/sensor/mchp_tach_xec/Kconfig | 2 +- drivers/sensor/qdec_sam/Kconfig | 2 +- drivers/serial/Kconfig.gecko | 2 +- drivers/serial/uart_mcux_flexcomm.c | 6 +- drivers/spi/Kconfig.nrfx | 2 +- drivers/timer/Kconfig.gecko | 2 +- drivers/timer/Kconfig.x86 | 2 +- drivers/timer/hpet.c | 2 - drivers/timer/intel_adsp_timer.c | 4 +- drivers/timer/mchp_xec_rtos_timer.c | 2 +- drivers/usb/device/usb_dc_mcux.c | 6 +- ...ga_cyclone5.dtsi => socfpga_cyclonev.dtsi} | 0 dts/arm/{seeed => seeed_studio}/lora-e5.dtsi | 0 dts/arm/st/f0/stm32f071.dtsi | 18 +- dts/arm/st/f0/stm32f091.dtsi | 4 +- dts/bindings/vendor-prefixes.txt | 94 +- dts/x86/intel/{ia32.dtsi => atom.dtsi} | 0 .../drivers/pinctrl/pinctrl_soc_sam_common.h | 4 +- modules/Kconfig.atmel | 2 +- modules/Kconfig.esp32 | 2 +- modules/Kconfig.imx | 2 +- modules/Kconfig.infineon | 2 +- modules/Kconfig.mcux | 11 +- modules/Kconfig.silabs | 2 +- modules/Kconfig.vega | 2 +- modules/hal_nxp/CMakeLists.txt | 8 + modules/trusted-firmware-m/CMakeLists.txt | 6 +- modules/trusted-firmware-m/Kconfig.tfm | 14 +- .../{nordic_nrf => nordic}/CMakeLists.txt | 0 .../include/RTE_Device.h | 0 .../include/device_cfg.h | 0 .../include/tfm_ioctl_api.h | 0 .../include/tfm_peripherals_config.h | 0 .../include/tfm_read_ranges.h | 0 .../include/util/array.h | 0 .../nrf5340_cpuapp/CMakeLists.txt | 0 .../nrf5340_cpuapp/config.cmake | 0 .../nrf5340_cpuapp/cpuarch.cmake | 0 .../nrf5340_cpuapp/ns/cpuarch_ns.cmake | 0 .../nrf9120/CMakeLists.txt | 0 .../nrf9120/config.cmake | 0 .../nrf9120/cpuarch.cmake | 0 .../nrf9120/ns/cpuarch_ns.cmake | 0 .../nrf9160/CMakeLists.txt | 0 .../nrf9160/config.cmake | 0 .../nrf9160/cpuarch.cmake | 0 .../nrf9160/ns/cpuarch_ns.cmake | 0 .../{nordic_nrf => nordic}/ns/CMakeLists.txt | 0 .../src/tfm_hal_platform.c | 0 .../src/tfm_platform_system.c | 0 .../code_relocation_nocopy/README.rst | 4 +- .../code_relocation_nocopy/sample.yaml | 2 +- .../sysbuild/with_mcuboot/README.rst | 2 +- .../sysbuild/with_mcuboot/sample.yaml | 4 +- samples/arch/smp/pktqueue/sample.yaml | 8 - samples/basic/blinky_pwm/README.rst | 4 +- ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 ...verlay => rcar_h3ulcb_r8a77951_r7.overlay} | 0 .../basic/blinky_pwm/boards/rpi_pico.overlay | 10 + samples/basic/button/sample.yaml | 2 +- samples/basic/fade_led/README.rst | 4 +- samples/basic/fade_led/sample.yaml | 2 +- samples/basic/hash_map/sample.yaml | 2 +- samples/basic/minimal/sample.yaml | 22 +- samples/basic/rgb_led/README.rst | 8 +- samples/basic/threads/README.rst | 4 +- samples/basic/threads/sample.yaml | 2 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 samples/bluetooth/beacon/sample.yaml | 4 +- samples/bluetooth/bluetooth.rst | 4 +- .../broadcast_audio_assistant/README.rst | 2 +- .../broadcast_audio_assistant/sample.yaml | 4 +- .../broadcast_audio_sink/Kconfig.sysbuild | 6 +- .../bluetooth/broadcast_audio_sink/README.rst | 4 +- .../broadcast_audio_sink/sample.yaml | 10 +- .../broadcast_audio_source/Kconfig.sysbuild | 6 +- .../broadcast_audio_source/README.rst | 4 +- .../broadcast_audio_source/sample.yaml | 14 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 samples/bluetooth/broadcaster/sample.yaml | 4 +- .../broadcaster_multiple/sample.yaml | 4 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 samples/bluetooth/central_ht/sample.yaml | 4 +- .../bluetooth/central_multilink/sample.yaml | 2 +- samples/bluetooth/central_otc/sample.yaml | 8 +- .../direction_finding_central/README.rst | 4 +- .../direction_finding_central/sample.yaml | 24 +- .../README.rst | 4 +- .../sample.yaml | 24 +- .../README.rst | 4 +- .../sample.yaml | 24 +- .../direction_finding_peripheral/README.rst | 4 +- .../direction_finding_peripheral/sample.yaml | 24 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 .../encrypted_advertising/central/sample.yaml | 2 +- .../peripheral/sample.yaml | 2 +- .../extended_adv/advertiser/sample.yaml | 2 +- .../extended_adv/scanner/sample.yaml | 2 +- samples/bluetooth/hci_ipc/sample.yaml | 62 +- samples/bluetooth/hci_pwr_ctrl/sample.yaml | 4 +- ...51422.overlay => nrf51dk_nrf51822.overlay} | 0 samples/bluetooth/hci_spi/sample.yaml | 8 +- samples/bluetooth/hci_uart/README.rst | 8 +- ...dk_nrf51422.conf => nrf51dk_nrf51822.conf} | 0 ...51422.overlay => nrf51dk_nrf51822.overlay} | 0 ...rf51422.conf => nrf51dongle_nrf51822.conf} | 0 ...2.overlay => nrf51dongle_nrf51822.overlay} | 0 ... => rv32m1_vega_openisa_rv32m1_ri5cy.conf} | 0 ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 samples/bluetooth/hci_uart/sample.yaml | 14 +- samples/bluetooth/hci_uart_async/README.rst | 2 +- samples/bluetooth/hci_uart_async/sample.yaml | 2 +- samples/bluetooth/hci_usb/sample.yaml | 2 +- samples/bluetooth/hci_usb_h4/sample.yaml | 2 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 samples/bluetooth/ipsp/README.rst | 6 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 samples/bluetooth/iso_broadcast/sample.yaml | 6 +- .../iso_broadcast_benchmark/sample.yaml | 8 +- .../iso_connected_benchmark/sample.yaml | 4 +- samples/bluetooth/iso_receive/sample.yaml | 6 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 samples/bluetooth/mesh/sample.yaml | 4 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 samples/bluetooth/mesh_demo/sample.yaml | 4 +- .../bluetooth/mesh_provisioner/sample.yaml | 4 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 samples/bluetooth/observer/sample.yaml | 4 +- samples/bluetooth/periodic_adv/sample.yaml | 2 +- .../bluetooth/periodic_adv_conn/sample.yaml | 4 +- .../bluetooth/periodic_adv_rsp/sample.yaml | 4 +- samples/bluetooth/periodic_sync/sample.yaml | 2 +- .../bluetooth/periodic_sync_conn/sample.yaml | 4 +- .../bluetooth/periodic_sync_rsp/sample.yaml | 4 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 samples/bluetooth/peripheral_hr/sample.yaml | 4 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 samples/bluetooth/peripheral_ht/sample.yaml | 4 +- .../bluetooth/peripheral_identity/sample.yaml | 2 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 .../public_broadcast_sink/Kconfig.sysbuild | 6 +- .../public_broadcast_sink/README.rst | 4 +- .../public_broadcast_sink/sample.yaml | 10 +- .../public_broadcast_source/Kconfig.sysbuild | 6 +- .../public_broadcast_source/README.rst | 4 +- .../public_broadcast_source/sample.yaml | 10 +- ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 .../unicast_audio_client/Kconfig.sysbuild | 6 +- .../bluetooth/unicast_audio_client/README.rst | 6 +- .../unicast_audio_client/sample.yaml | 10 +- .../unicast_audio_server/Kconfig.sysbuild | 6 +- .../bluetooth/unicast_audio_server/README.rst | 6 +- .../unicast_audio_server/sample.yaml | 10 +- .../em_starterkit_em7d_normal_defconfig | 1 - .../boards/arc_secure_services/sample.yaml | 6 +- samples/boards/esp32/deep_sleep/README.rst | 2 +- samples/boards/esp32/ethernet/sample.yaml | 2 +- .../boards/esp32/flash_encryption/sample.yaml | 6 +- .../esp32/flash_memory_mapped/sample.yaml | 4 +- samples/boards/esp32/light_sleep/README.rst | 2 +- samples/boards/esp32/spiram_test/sample.yaml | 2 +- .../intel_adsp/code_relocation/README.rst | 2 +- .../intel_adsp/code_relocation/sample.yaml | 2 +- .../mimxrt1170_evk_cm7/magic_addr/sample.yaml | 8 +- .../mimxrt1170_evk_cm7/magic_addr/src/main.c | 1 - .../mimxrt595_evk/system_off/CMakeLists.txt | 9 + .../system_off/Kconfig | 0 .../system_off/README.rst | 4 +- .../system_off/app.overlay | 0 .../system_off/prj.conf | 0 .../mimxrt595_evk/system_off/sample.yaml | 13 + .../system_off/src/main.c | 0 .../system_off/CMakeLists.txt | 9 - .../mimxrt595_evk_cm33/system_off/sample.yaml | 13 - samples/boards/nrf/battery/README.rst | 2 +- samples/boards/nrf/battery/sample.yaml | 2 +- samples/boards/nrf/clock_skew/README.rst | 2 +- samples/boards/nrf/clock_skew/sample.yaml | 8 +- samples/boards/nrf/dynamic_pinctrl/README.rst | 2 +- .../boards/nrf/dynamic_pinctrl/sample.yaml | 4 +- .../nrf/ieee802154/802154_rpmsg/sample.yaml | 2 +- samples/boards/nrf/mesh/onoff-app/README.rst | 4 +- samples/boards/nrf/mesh/onoff-app/sample.yaml | 2 +- .../onoff_level_lighting_vnd_app/README.rst | 4 +- .../onoff_level_lighting_vnd_app/sample.yaml | 2 +- .../boards/nrf/nrf53_sync_rtc/CMakeLists.txt | 2 +- .../nrf/nrf53_sync_rtc/Kconfig.sysbuild | 2 +- samples/boards/nrf/nrf53_sync_rtc/README.rst | 4 +- .../nrf/nrf53_sync_rtc/net/CMakeLists.txt | 2 +- samples/boards/nrf/nrf53_sync_rtc/sample.yaml | 4 +- samples/boards/nrf/nrfx/README.rst | 4 +- samples/boards/nrf/nrfx/sample.yaml | 6 +- samples/boards/nrf/nrfx_prs/README.rst | 4 +- .../nrfx_prs/boards/nrf9160dk_nrf9160.overlay | 2 +- samples/boards/nrf/nrfx_prs/sample.yaml | 8 +- samples/boards/nrf/system_off/README.rst | 2 +- samples/boards/nrf/system_off/sample.yaml | 12 +- samples/boards/nxp_s32/netc/README.rst | 4 +- samples/boards/nxp_s32/netc/sample.yaml | 4 +- samples/boards/stm32/ccm/README.rst | 2 +- samples/boards/stm32/h7_dual_core/README.rst | 8 +- ...> stm32h747i_disco_stm32h747xx_m4.overlay} | 0 ...> stm32h747i_disco_stm32h747xx_m7.overlay} | 0 .../up_squared/gpio_counter/CMakeLists.txt | 1 - samples/compression/lz4/README.rst | 6 +- samples/compression/lz4/sample.yaml | 2 +- ...lay => longan_nano_gd32vf103_lite.overlay} | 0 .../mimxrt1160_evk_mimxrt1166_cm7.overlay | 34 + ...> mimxrt1170_evk_mimxrt1176_cm7_A.overlay} | 0 ...> mimxrt1170_evk_mimxrt1176_cm7_B.overlay} | 0 ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 ...51422.overlay => nrf51dk_nrf51822.overlay} | 0 ...{tdk_robokit1.overlay => robokit1.overlay} | 0 ...lay => sam_e70_xplained_same70q21.overlay} | 0 ...overlay => sam_v71_xult_samv71q21.overlay} | 0 ...c21n_xpro.overlay => samc21n_xpro.overlay} | 0 ...amd21_xpro.overlay => samd21_xpro.overlay} | 0 ...ame54_xpro.overlay => same54_xpro.overlay} | 0 ...aml21_xpro.overlay => saml21_xpro.overlay} | 0 ...amr21_xpro.overlay => samr21_xpro.overlay} | 0 ...amr34_xpro.overlay => samr34_xpro.overlay} | 0 samples/drivers/adc/sample.yaml | 12 +- samples/drivers/audio/dmic/README.rst | 6 +- ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 samples/drivers/audio/dmic/sample.yaml | 4 +- samples/drivers/can/counter/README.rst | 4 +- samples/drivers/clock_control_xec/src/main.c | 2 +- ...pp.conf => bl5340_dvk_nrf5340_cpuapp.conf} | 0 ...rlay => bl5340_dvk_nrf5340_cpuapp.overlay} | 0 ...51422.overlay => nrf51dk_nrf51822.overlay} | 0 ...verlay => s32z2xxdc2_s32z270_rtu0.overlay} | 0 ...verlay => s32z2xxdc2_s32z270_rtu1.overlay} | 0 ...lay => sam_e70_xplained_same70q21.overlay} | 0 ...ay => sam_e70_xplained_same70q21b.overlay} | 0 ...overlay => sam_v71_xult_samv71q21.overlay} | 0 ...verlay => sam_v71_xult_samv71q21b.overlay} | 0 ...conf => stm32l562e_dk_stm32l562xx_ns.conf} | 0 samples/drivers/counter/alarm/sample.yaml | 12 +- samples/drivers/counter/alarm/src/main.c | 4 +- ...51422.overlay => nrf51dk_nrf51822.overlay} | 0 .../drivers/counter/maxim_ds3231/sample.yaml | 2 +- samples/drivers/dac/README.rst | 4 +- ...rlay => bl5340_dvk_nrf5340_cpuapp.overlay} | 0 ...lay => longan_nano_gd32vf103_lite.overlay} | 0 ...lay => sam_e70_xplained_same70q21.overlay} | 0 ...ay => sam_e70_xplained_same70q21b.overlay} | 0 ...overlay => sam_v71_xult_samv71q21.overlay} | 0 ...verlay => sam_v71_xult_samv71q21b.overlay} | 0 samples/drivers/dac/sample.yaml | 16 +- samples/drivers/display/README.rst | 2 +- ...f => mimxrt1170_evk_mimxrt1176_cm7_A.conf} | 0 .../mimxrt1170_evk_mimxrt1176_cm7_B.conf | 7 + ...onf => mimxrt595_evk_mimxrt595s_cm33.conf} | 0 samples/drivers/display/sample.yaml | 28 +- samples/drivers/eeprom/README.rst | 2 +- samples/drivers/eeprom/sample.yaml | 6 +- samples/drivers/flash_shell/sample.yaml | 8 +- samples/drivers/ht16k33/README.rst | 2 +- samples/drivers/ht16k33/sample.yaml | 2 +- samples/drivers/i2s/echo/README.rst | 6 +- samples/drivers/i2s/echo/sample.yaml | 4 +- samples/drivers/ipm/ipm_esp32/CMakeLists.txt | 12 +- samples/drivers/ipm/ipm_esp32/README.rst | 2 +- .../ipm_esp32/boards/esp32_devkitc_wroom.conf | 1 - ... esp32_devkitc_wroom_esp32_procpu.overlay} | 0 .../boards/esp32_devkitc_wrover.conf | 1 - ...esp32_devkitc_wrover_esp32_procpu.overlay} | 0 .../ipm/ipm_esp32/boards/esp32s3_devkitm.conf | 1 - ...=> esp32s3_devkitm_esp32s3_procpu.overlay} | 0 ....overlay => yd_esp32_esp32_procpu.overlay} | 0 .../boards/esp32_devkitc_wroom_appcpu.overlay | 3 - .../esp32_devkitc_wrover_appcpu.overlay | 3 - .../boards/esp32s3_dekvitm_appcpu.overlay | 3 - samples/drivers/ipm/ipm_esp32/sample.yaml | 5 +- samples/drivers/ipm/ipm_imx/README.rst | 4 +- samples/drivers/ipm/ipm_imx/sample.yaml | 10 +- samples/drivers/ipm/ipm_mcux/Kconfig.sysbuild | 4 +- samples/drivers/ipm/ipm_mcux/README.rst | 12 +- ....conf => lpcxpresso54114_lpc54114_m4.conf} | 0 .../drivers/ipm/ipm_mcux/remote/sample.yaml | 6 +- samples/drivers/ipm/ipm_mcux/sample.yaml | 6 +- .../drivers/ipm/ipm_mhu_dual_core/README.rst | 4 +- .../drivers/ipm/ipm_mhu_dual_core/sample.yaml | 6 +- .../boards/nrf52840dk_nrf52840_spi.overlay | 2 +- samples/drivers/jesd216/sample.yaml | 8 +- samples/drivers/lcd_hd44780/src/main.c | 5 +- samples/drivers/led_lp5562/README.rst | 2 +- samples/drivers/led_lp5562/sample.yaml | 2 +- samples/drivers/led_lp5569/README.rst | 2 +- samples/drivers/led_lp5569/sample.yaml | 2 +- ...arbon.conf => 96b_carbon_stm32f401xe.conf} | 0 ...overlay => 96b_carbon_stm32f401xe.overlay} | 0 samples/drivers/led_lpd8806/sample.yaml | 2 +- .../drivers/led_sx1509b_intensity/README.rst | 2 +- .../drivers/led_sx1509b_intensity/sample.yaml | 2 +- samples/drivers/led_ws2812/README.rst | 11 +- ...dk_nrf51422.conf => nrf51dk_nrf51822.conf} | 0 ...51422.overlay => nrf51dk_nrf51822.overlay} | 0 samples/drivers/mbox/CMakeLists.txt | 12 +- samples/drivers/mbox/Kconfig.sysbuild | 12 +- samples/drivers/mbox/README.rst | 4 +- ...onf => lpcxpresso55s69_lpc55s69_cpu0.conf} | 0 ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 ...onf => mimxrt1160_evk_mimxrt1166_cm7.conf} | 0 ... => mimxrt1160_evk_mimxrt1166_cm7.overlay} | 0 .../mimxrt1170_evk_mimxrt1176_cm7_A.conf} | 0 ...> mimxrt1170_evk_mimxrt1176_cm7_A.overlay} | 0 .../mimxrt1170_evk_mimxrt1176_cm7_B.conf | 3 + .../mimxrt1170_evk_mimxrt1176_cm7_B.overlay | 29 + samples/drivers/mbox/remote/CMakeLists.txt | 12 +- ...onf => lpcxpresso55s69_lpc55s69_cpu1.conf} | 0 ... => lpcxpresso55s69_lpc55s69_cpu1.overlay} | 0 .../boards/mimxrt1160_evk_mimxrt1166_cm4.conf | 4 + .../mimxrt1160_evk_mimxrt1166_cm4.overlay | 48 + .../boards/mimxrt1170_evk_mimxrt1176_cm4.conf | 4 + .../mimxrt1170_evk_mimxrt1176_cm4.overlay | 48 + .../mimxrt1170_evk_mimxrt1176_cm4_B.conf | 4 + .../mimxrt1170_evk_mimxrt1176_cm4_B.overlay | 49 + samples/drivers/mbox/sample.yaml | 14 +- samples/drivers/mbox/sysbuild.cmake | 2 +- samples/drivers/mbox_data/CMakeLists.txt | 8 +- samples/drivers/mbox_data/Kconfig.sysbuild | 8 +- ...onf => lpcxpresso55s69_lpc55s69_cpu0.conf} | 0 ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 .../boards/mimxrt1160_evk_mimxrt1166_cm7.conf | 0 ... => mimxrt1160_evk_mimxrt1166_cm7.overlay} | 0 .../mimxrt1170_evk_mimxrt1176_cm7_A.conf | 3 + ...> mimxrt1170_evk_mimxrt1176_cm7_A.overlay} | 0 .../mimxrt1170_evk_mimxrt1176_cm7_B.conf | 3 + .../mimxrt1170_evk_mimxrt1176_cm7_B.overlay | 0 .../drivers/mbox_data/remote/CMakeLists.txt | 8 +- ...onf => lpcxpresso55s69_lpc55s69_cpu1.conf} | 0 ... => lpcxpresso55s69_lpc55s69_cpu1.overlay} | 0 .../boards/mimxrt1160_evk_mimxrt1166_cm4.conf | 4 + .../mimxrt1160_evk_mimxrt1166_cm4.overlay | 54 + .../boards/mimxrt1170_evk_mimxrt1176_cm4.conf | 4 + .../mimxrt1170_evk_mimxrt1176_cm4.overlay | 54 + .../mimxrt1170_evk_mimxrt1176_cm4_B.conf | 4 + .../mimxrt1170_evk_mimxrt1176_cm4_B.overlay | 55 + samples/drivers/mbox_data/sample.yaml | 12 +- samples/drivers/memc/README.rst | 4 +- ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 samples/drivers/memc/sample.yaml | 2 +- samples/drivers/misc/ft800/README.rst | 4 +- samples/drivers/misc/ft800/sample.yaml | 2 +- samples/drivers/soc_flash_nrf/README.rst | 2 +- samples/drivers/soc_flash_nrf/sample.yaml | 8 +- samples/drivers/spi_bitbang/README.rst | 2 +- samples/drivers/spi_bitbang/sample.yaml | 2 +- samples/drivers/spi_flash/README.rst | 2 +- samples/drivers/spi_flash/src/main.c | 4 +- samples/drivers/spi_flash_at45/README.rst | 10 +- samples/drivers/uart/echo_bot/README.rst | 4 +- samples/drivers/uart/native_tty/README.rst | 2 +- samples/drivers/w1/scanner/README.rst | 2 +- samples/drivers/w1/scanner/sample.yaml | 8 +- samples/drivers/watchdog/sample.yaml | 18 +- samples/fuel_gauge/max17048/sample.yaml | 4 +- samples/kernel/metairq_dispatch/sample.yaml | 2 +- samples/modules/canopennode/sample.yaml | 2 +- ...f => mimxrt1170_evk_mimxrt1176_cm7_A.conf} | 0 samples/modules/lvgl/demos/sample.yaml | 2 +- .../tflite-micro/hello_world/README.rst | 2 +- .../tflite-micro/hello_world/sample.yaml | 2 +- .../tflite-micro/tflm_ethosu/README.rst | 2 +- .../tflite-micro/tflm_ethosu/sample.yaml | 2 +- .../modules/thrift/hello/client/sample.yaml | 2 +- .../modules/thrift/hello/server/sample.yaml | 2 +- samples/net/cloud/mqtt_azure/sample.yaml | 2 +- samples/net/cloud/tagoio_http_post/README.rst | 4 +- ...d.conf => sam_e70_xplained_same70q21.conf} | 0 samples/net/gptp/sample.yaml | 4 +- .../boards/sam_e70_xplained.conf | 6 - .../boards/sam_e70_xplained_same70q21.conf | 6 + samples/net/lwm2m_client/sample.yaml | 4 +- samples/net/openthread/coprocessor/README.rst | 6 +- .../net/openthread/coprocessor/sample.yaml | 18 +- .../net/sockets/dumb_http_server/sample.yaml | 2 +- samples/net/sockets/echo_client/README.rst | 6 +- .../{atsamr21_xpro.conf => samr21_xpro.conf} | 0 samples/net/sockets/echo_client/sample.yaml | 22 +- samples/net/sockets/echo_server/README.rst | 8 +- .../{atsamr21_xpro.conf => samr21_xpro.conf} | 0 samples/net/sockets/echo_server/sample.yaml | 22 +- samples/net/sockets/txtime/README.rst | 2 +- .../net/sockets/websocket_client/sample.yaml | 2 +- samples/net/wifi/sample.yaml | 2 +- samples/net/wpan_serial/README.rst | 2 +- samples/net/wpan_serial/sample.yaml | 4 +- samples/net/wpanusb/README.rst | 4 +- samples/net/wpanusb/sample.yaml | 4 +- ...f => mimxrt1170_evk_mimxrt1176_cm7_A.conf} | 0 samples/net/zperf/sample.yaml | 8 +- samples/posix/eventfd/sample.yaml | 2 +- samples/sensor/accel_polling/sample.yaml | 10 +- samples/sensor/adt7420/README.rst | 2 +- samples/sensor/bme680/README.rst | 2 +- samples/sensor/bme680/sample.yaml | 6 +- samples/sensor/bmi270/README.rst | 2 +- samples/sensor/bq274xx/README.rst | 4 +- samples/sensor/bq274xx/sample.yaml | 8 +- samples/sensor/ccs811/README.rst | 6 +- samples/sensor/ccs811/sample.yaml | 2 +- samples/sensor/dht/README.rst | 2 +- samples/sensor/dht/sample.yaml | 4 +- ...51422.overlay => nrf51dk_nrf51822.overlay} | 0 samples/sensor/dps310/README.rst | 4 +- samples/sensor/ds18b20/sample.yaml | 4 +- samples/sensor/fdc2x1x/README.rst | 2 +- samples/sensor/fdc2x1x/sample.yaml | 4 +- samples/sensor/fxas21002/README.rst | 4 +- samples/sensor/fxas21002/sample.yaml | 4 +- samples/sensor/fxos8700/README.rst | 6 +- ...onf => mimxrt1160_evk_mimxrt1166_cm4.conf} | 0 .../boards/mimxrt1160_evk_mimxrt1166_cm7.conf | 2 + .../boards/mimxrt1170_evk_mimxrt1176_cm4.conf | 2 + .../mimxrt1170_evk_mimxrt1176_cm7_A.conf | 2 + samples/sensor/fxos8700/sample.yaml | 16 +- samples/sensor/grove_light/sample.yaml | 4 +- samples/sensor/grove_temperature/sample.yaml | 4 +- samples/sensor/grow_r502a/README.rst | 2 +- samples/sensor/icm42605/README.rst | 2 +- samples/sensor/icm42605/sample.yaml | 4 +- samples/sensor/isl29035/README.rst | 2 +- samples/sensor/isl29035/sample.yaml | 4 +- samples/sensor/lps22hh/README.rst | 2 +- samples/sensor/lps22hh_i3c/README.rst | 6 +- ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 samples/sensor/lsm6dsl/README.rst | 4 +- samples/sensor/lsm6dso_i2c_on_i3c/README.rst | 6 +- ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 samples/sensor/magn_polling/sample.yaml | 2 +- samples/sensor/max17262/README.rst | 2 +- samples/sensor/max17262/sample.yaml | 2 +- samples/sensor/max30101/README.rst | 4 +- ...r_k64.overlay => hexiwear_mk64f12.overlay} | 0 samples/sensor/max30101/sample.yaml | 4 +- ... => mimxrt1170_evk_mimxrt1176_cm4.overlay} | 0 .../mimxrt1170_evk_mimxrt1176_cm7_A.overlay | 22 + samples/sensor/mcux_acmp/sample.yaml | 4 +- samples/sensor/mcux_acmp/src/main.c | 2 +- samples/sensor/mpu6050/README.rst | 2 +- samples/sensor/mpu6050/sample.yaml | 4 +- samples/sensor/ms5837/README.rst | 2 +- samples/sensor/ms5837/sample.yaml | 4 +- samples/sensor/proximity_polling/sample.yaml | 2 +- samples/sensor/qdec/sample.yaml | 8 +- .../{tdk_robokit1.conf => robokit1.conf} | 0 samples/sensor/sht3xd/sample.yaml | 4 +- samples/sensor/thermometer/README.rst | 8 +- samples/sensor/thermometer/sample.yaml | 4 +- samples/shields/npm1300_ek/doc/index.rst | 2 +- samples/shields/npm1300_ek/sample.yaml | 2 +- samples/shields/npm6001_ek/doc/index.rst | 2 +- .../x_nucleo_iks01a2/standard/README.rst | 4 +- .../x_nucleo_iks02a1/microphone/README.rst | 4 +- .../x_nucleo_iks02a1/sensorhub/README.rst | 4 +- samples/subsys/console/echo/sample.yaml | 2 +- samples/subsys/console/getchar/sample.yaml | 2 +- samples/subsys/console/getline/sample.yaml | 2 +- .../display/cfb/boards/reel_board_v2.conf | 1 - samples/subsys/display/lvgl/README.rst | 2 +- ...f => mimxrt1170_evk_mimxrt1176_cm7_A.conf} | 0 samples/subsys/display/lvgl/sample.yaml | 8 +- samples/subsys/fs/format/README.rst | 4 +- samples/subsys/fs/format/sample.yaml | 2 +- samples/subsys/fs/fs_sample/README.rst | 12 +- ...f => stm32h747i_disco_stm32h747xx_m7.conf} | 0 ...> stm32h747i_disco_stm32h747xx_m7.overlay} | 0 samples/subsys/fs/fs_sample/sample.yaml | 10 +- samples/subsys/fs/littlefs/README.rst | 2 +- ...onf => lpcxpresso55s69_lpc55s69_cpu0.conf} | 0 .../boards/nrf52840dk_nrf52840_spi.overlay | 2 +- ...f => stm32h747i_disco_stm32h747xx_m7.conf} | 0 ...> stm32h747i_disco_stm32h747xx_m7.overlay} | 0 samples/subsys/fs/littlefs/sample.yaml | 17 +- samples/subsys/input/input_dump/README.rst | 4 +- .../ipc/ipc_service/icmsg/CMakeLists.txt | 2 +- .../ipc/ipc_service/icmsg/Kconfig.sysbuild | 2 +- .../subsys/ipc/ipc_service/icmsg/README.rst | 4 +- .../subsys/ipc/ipc_service/icmsg/sample.yaml | 4 +- .../ipc_service/multi_endpoint/CMakeLists.txt | 2 +- .../multi_endpoint/Kconfig.sysbuild | 2 +- .../ipc/ipc_service/multi_endpoint/README.rst | 6 +- .../ipc_service/multi_endpoint/sample.yaml | 8 +- .../ipc_service/static_vrings/CMakeLists.txt | 2 +- .../static_vrings/Kconfig.sysbuild | 2 +- .../ipc/ipc_service/static_vrings/README.rst | 4 +- .../ipc/ipc_service/static_vrings/sample.yaml | 4 +- samples/subsys/ipc/openamp/Kconfig.sysbuild | 14 +- samples/subsys/ipc/openamp/README.rst | 20 +- ....conf => lpcxpresso54114_lpc54114_m4.conf} | 0 ...ay => lpcxpresso54114_lpc54114_m4.overlay} | 0 ...onf => lpcxpresso55s69_lpc55s69_cpu0.conf} | 0 ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 ...onf => mimxrt1160_evk_mimxrt1166_cm7.conf} | 0 ... => mimxrt1160_evk_mimxrt1166_cm7.overlay} | 0 .../mimxrt1170_evk_mimxrt1176_cm7_A.conf | 2 + .../mimxrt1170_evk_mimxrt1176_cm7_A.overlay | 24 + .../mimxrt1170_evk_mimxrt1176_cm7_B.conf | 7 + ...> mimxrt1170_evk_mimxrt1176_cm7_B.overlay} | 0 ....conf => lpcxpresso54114_lpc54114_m0.conf} | 0 ...ay => lpcxpresso54114_lpc54114_m0.overlay} | 0 ...onf => lpcxpresso55s69_lpc55s69_cpu1.conf} | 0 ... => lpcxpresso55s69_lpc55s69_cpu1.overlay} | 0 .../boards/mimxrt1160_evk_mimxrt1166_cm4.conf | 3 + .../mimxrt1160_evk_mimxrt1166_cm4.overlay | 51 + .../boards/mimxrt1170_evk_mimxrt1176_cm4.conf | 3 + .../mimxrt1170_evk_mimxrt1176_cm4.overlay | 51 + .../mimxrt1170_evk_mimxrt1176_cm4_B.conf | 8 + .../mimxrt1170_evk_mimxrt1176_cm4_B.overlay | 49 + ...remote.overlay => mps2_an521_cpu1.overlay} | 0 ...erlay => v2m_musca_b1_musca_b1_ns.overlay} | 0 samples/subsys/ipc/openamp/remote/sample.yaml | 6 +- samples/subsys/ipc/openamp/sample.yaml | 10 +- ...x8m.conf => imx8mp_evk_mimx8ml8_adsp.conf} | 0 ...erlay => imx8mp_evk_mimx8ml8_adsp.overlay} | 0 .../subsys/ipc/openamp_rsc_table/sample.yaml | 4 +- .../subsys/ipc/rpmsg_service/Kconfig.sysbuild | 8 +- samples/subsys/ipc/rpmsg_service/README.rst | 24 +- ...pp.conf => bl5340_dvk_nrf5340_cpuapp.conf} | 0 ...remote.overlay => mps2_an521_cpu1.overlay} | 0 ...erlay => v2m_musca_b1_musca_b1_ns.overlay} | 0 samples/subsys/llext/shell_loader/README.rst | 2 +- samples/subsys/llext/shell_loader/sample.yaml | 4 +- samples/subsys/logging/dictionary/sample.yaml | 8 +- samples/subsys/logging/logger/sample.yaml | 2 +- .../subsys/logging/multidomain/CMakeLists.txt | 2 +- .../logging/multidomain/Kconfig.sysbuild | 2 +- .../subsys/logging/multidomain/sample.yaml | 4 +- samples/subsys/logging/syst/sample.yaml | 6 +- samples/subsys/mgmt/mcumgr/smp_svr/README.rst | 4 +- .../subsys/mgmt/mcumgr/smp_svr/sample.yaml | 48 +- .../mgmt/osdp/control_panel/sample.yaml | 3 +- .../mgmt/osdp/peripheral_device/sample.yaml | 3 +- samples/subsys/mgmt/updatehub/README.rst | 10 +- samples/subsys/modbus/rtu_client/sample.yaml | 4 +- samples/subsys/modbus/rtu_server/README.rst | 4 +- samples/subsys/modbus/rtu_server/sample.yaml | 8 +- samples/subsys/nvs/README.rst | 4 +- samples/subsys/nvs/sample.yaml | 2 +- samples/subsys/pm/device_pm/sample.yaml | 6 +- .../timer_synchronization/sample.yaml | 2 +- samples/subsys/settings/README.rst | 2 +- samples/subsys/shell/fs/sample.yaml | 4 +- samples/subsys/shell/shell_module/sample.yaml | 2 +- samples/subsys/task_wdt/sample.yaml | 6 +- samples/subsys/tracing/README.rst | 8 +- samples/subsys/tracing/sample.yaml | 8 +- .../audio/headphones_microphone/sample.yaml | 4 +- samples/subsys/usb/audio/headset/sample.yaml | 4 +- samples/subsys/usb/cdc_acm/sample.yaml | 4 +- samples/subsys/usb/dfu/README.rst | 10 +- samples/subsys/usb/dfu/sample.yaml | 10 +- samples/subsys/usb/hid-cdc/README.rst | 2 +- samples/subsys/usb/hid-cdc/sample.yaml | 6 +- samples/subsys/usb/mass/README.rst | 6 +- ...conf => stm32l562e_dk_stm32l562xx_ns.conf} | 0 samples/subsys/usb/mass/sample.yaml | 26 +- samples/subsys/usb/shell/README.rst | 4 +- samples/subsys/usb/shell/sample.yaml | 4 +- .../usb/uac2_explicit_feedback/README.rst | 2 +- .../usb/uac2_explicit_feedback/sample.yaml | 2 +- samples/subsys/zbus/benchmark/README.rst | 4 +- .../zbus/benchmark/benchmark_256KB.robot | 2 +- samples/subsys/zbus/dyn_channel/sample.yaml | 2 +- ...hifive1_revb.conf => hifive1_fe310_B.conf} | 0 ...1_revb.overlay => hifive1_fe310_B.overlay} | 0 samples/subsys/zbus/remote_mock/sample.yaml | 2 +- ...hifive1_revb.conf => hifive1_fe310_B.conf} | 0 ...1_revb.overlay => hifive1_fe310_B.overlay} | 0 samples/tfm_integration/psa_crypto/README.rst | 24 +- .../tfm_integration/psa_crypto/sample.yaml | 6 +- .../psa_protected_storage/README.rst | 2 +- .../psa_protected_storage/sample.yaml | 12 +- samples/tfm_integration/tfm_ipc/README.rst | 20 +- ...=> nucleo_l552ze_q_stm32l552xx_ns.overlay} | 0 samples/tfm_integration/tfm_ipc/sample.yaml | 20 +- .../tfm_integration/tfm_psa_test/README.rst | 4 +- .../tfm_integration/tfm_psa_test/sample.yaml | 12 +- .../tfm_regression_test/README.rst | 2 +- ...=> nucleo_l552ze_q_stm32l552xx_ns.overlay} | 0 .../tfm_regression_test/sample.yaml | 10 +- .../tfm_secure_partition/sample.yaml | 10 +- .../userspace/hello_world_user/sample.yaml | 4 +- samples/userspace/prod_consumer/sample.yaml | 2 +- samples/userspace/shared_mem/README.rst | 2 +- samples/userspace/shared_mem/sample.yaml | 2 +- samples/userspace/syscall_perf/sample.yaml | 2 +- scripts/ci/Kconfig.board.v2 | 10 + scripts/ci/check_compliance.py | 201 ++- scripts/ci/test_plan.py | 3 +- scripts/footprint/plan.txt | 30 +- scripts/kconfig/kconfigfunctions.py | 13 + scripts/list_boards.py | 280 ++++- scripts/list_hardware.py | 283 +++++ .../pylib/pytest-twister-harness/README.rst | 4 +- .../src/twister_harness/plugin.py | 2 +- .../boards/unit/unit_testing/board.yml | 5 + .../twister/soc/unit/unit_testing/soc.yml | 2 + scripts/pylib/twister/twisterlib/platform.py | 1 + scripts/pylib/twister/twisterlib/reports.py | 14 +- .../pylib/twister/twisterlib/testinstance.py | 6 +- scripts/pylib/twister/twisterlib/testplan.py | 28 +- scripts/schemas/arch-schema.yml | 29 + scripts/schemas/board-schema.yml | 80 ++ scripts/schemas/soc-schema.yml | 72 ++ scripts/snippets.py | 4 +- scripts/tests/twister_blackbox/test_report.py | 20 +- scripts/utils/board_v1_to_v2.py | 215 ++++ scripts/west_commands/boards.py | 10 +- .../completion/west-completion.bash | 4 +- .../completion/west-completion.fish | 11 + .../completion/west-completion.zsh | 7 +- scripts/west_commands/runners/core.py | 2 +- scripts/west_commands/runners/intel_adsp.py | 6 +- .../cmake/modules/sysbuild_extensions.cmake | 4 +- snippets/nordic-ppr/snippet.yml | 2 +- ...erlay => rcar_h3ulcb_r8a77951_a57.overlay} | 0 ...xs_m3.overlay => rcar_salvator_xs.overlay} | 0 snippets/xen_dom0/snippet.yml | 10 +- soc/CMakeLists.txt | 38 +- soc/Kconfig | 31 +- soc/Kconfig.v1 | 27 + soc/Kconfig.v1.choice | 13 + soc/Kconfig.v2 | 39 + soc/altr/qemu_nios2/CMakeLists.txt | 7 + soc/altr/qemu_nios2/Kconfig | 8 + soc/altr/qemu_nios2/Kconfig.defconfig | 9 + soc/altr/qemu_nios2/Kconfig.soc | 8 + .../qemu_nios2}/include/layout.h | 0 .../qemu_nios2}/include/linker.h | 0 .../qemu_nios2}/include/system.h | 0 .../nios2-qemu => altr/qemu_nios2}/linker.ld | 0 .../nios2-qemu => altr/qemu_nios2}/soc.h | 0 soc/altr/qemu_nios2/soc.yml | 2 + soc/altr/zephyr_nios2f/CMakeLists.txt | 7 + soc/altr/zephyr_nios2f/Kconfig | 7 + soc/altr/zephyr_nios2f/Kconfig.defconfig | 24 + soc/altr/zephyr_nios2f/Kconfig.soc | 8 + .../zephyr_nios2f}/cpu/README | 0 .../zephyr_nios2f}/cpu/ghrd_10m50da.qpf | 0 .../zephyr_nios2f}/cpu/ghrd_10m50da.qsf | 0 .../zephyr_nios2f}/cpu/ghrd_10m50da.qsys | 0 .../zephyr_nios2f}/cpu/ghrd_10m50da.sof | Bin .../zephyr_nios2f}/cpu/ghrd_10m50da.sopcinfo | 0 .../zephyr_nios2f}/cpu/ghrd_10m50da_top.v | 0 .../zephyr_nios2f}/cpu/ghrd_timing.sdc | 0 .../zephyr_nios2f}/include/layout.h | 0 .../zephyr_nios2f}/include/linker.h | 0 .../zephyr_nios2f}/include/system.h | 0 .../zephyr_nios2f}/linker.ld | 0 .../zephyr_nios2f}/soc.h | 0 soc/altr/zephyr_nios2f/soc.yml | 2 + soc/{arm => }/ambiq/CMakeLists.txt | 0 soc/ambiq/Kconfig | 9 + soc/ambiq/Kconfig.defconfig | 15 + soc/ambiq/Kconfig.soc | 11 + soc/ambiq/apollo4x/CMakeLists.txt | 9 + soc/ambiq/apollo4x/Kconfig | 13 + soc/ambiq/apollo4x/Kconfig.defconfig | 9 + .../ambiq/apollo4x/Kconfig.defconfig.apollo4p | 0 .../apollo4x/Kconfig.defconfig.apollo4p_blue | 0 soc/ambiq/apollo4x/Kconfig.soc | 29 + soc/{arm => }/ambiq/apollo4x/pinctrl_soc.h | 0 soc/{arm => }/ambiq/apollo4x/soc.c | 0 soc/{arm => }/ambiq/apollo4x/soc.h | 0 soc/ambiq/soc.yml | 7 + .../andes_v5 => andestech}/CMakeLists.txt | 0 soc/andestech/Kconfig | 8 + soc/andestech/Kconfig.defconfig | 8 + soc/andestech/Kconfig.soc | 10 + .../ae350/CMakeLists.txt | 0 soc/andestech/ae350/Kconfig | 122 ++ soc/andestech/ae350/Kconfig.defconfig | 39 + .../ae350/Kconfig.defconfig.ae350 | 3 - soc/andestech/ae350/Kconfig.soc | 20 + .../ae350/common_linker/execit.ld | 0 .../ae350/common_linker/init.ld | 0 .../ae350/common_linker/ram_start_nonzero.ld | 0 .../andes_v5 => andestech}/ae350/l2_cache.c | 0 .../andes_v5 => andestech}/ae350/linker.ld | 0 soc/{riscv/andes_v5 => andestech}/ae350/pma.c | 0 .../ae350/soc_context.h | 0 .../andes_v5 => andestech}/ae350/soc_irq.S | 0 .../ae350/soc_offsets.h | 0 .../andes_v5 => andestech}/ae350/soc_v5.h | 0 .../andes_v5 => andestech}/ae350/start.S | 0 soc/andestech/soc.yml | 6 + soc/arc/snps_arc_hsdk/Kconfig.defconfig | 49 - soc/arc/snps_arc_hsdk/Kconfig.soc | 7 - soc/arc/snps_arc_hsdk4xd/CMakeLists.txt | 18 - soc/arc/snps_arc_hsdk4xd/Kconfig.defconfig | 56 - soc/arc/snps_arc_hsdk4xd/Kconfig.soc | 8 - soc/arc/snps_arc_iot/Kconfig.defconfig | 37 - soc/arc/snps_arc_iot/Kconfig.soc | 9 - soc/arc/snps_emsdp/CMakeLists.txt | 22 - soc/arc/snps_emsdp/Kconfig | 43 - soc/arc/snps_emsdp/Kconfig.defconfig | 23 - soc/arc/snps_emsdp/Kconfig.soc | 6 - soc/arc/snps_emsk/CMakeLists.txt | 12 - soc/arc/snps_emsk/Kconfig | 22 - soc/arc/snps_emsk/Kconfig.defconfig | 14 - soc/arc/snps_emsk/Kconfig.defconfig.em7d | 55 - soc/arc/snps_emsk/Kconfig.soc | 7 - soc/arc/snps_nsim/Kconfig | 58 - soc/arc/snps_nsim/Kconfig.defconfig | 25 - soc/arc/snps_nsim/Kconfig.soc | 6 - soc/arc/snps_qemu/CMakeLists.txt | 23 - soc/arc/snps_qemu/Kconfig | 21 - soc/arc/snps_qemu/Kconfig.defconfig | 38 - soc/arc/snps_qemu/Kconfig.defconfig.em | 9 - soc/arc/snps_qemu/Kconfig.defconfig.hs | 9 - soc/arc/snps_qemu/Kconfig.defconfig.hs5x | 9 - soc/arc/snps_qemu/Kconfig.defconfig.hs6x | 9 - soc/arc/snps_qemu/Kconfig.soc | 7 - soc/arm/CMakeLists.txt | 5 +- soc/arm/Kconfig | 53 +- soc/arm/Kconfig.defconfig | 8 + soc/arm/Kconfig.soc | 14 + soc/arm/ambiq/Kconfig | 16 - soc/arm/ambiq/Kconfig.defconfig | 11 - soc/arm/ambiq/Kconfig.soc | 5 - soc/arm/ambiq/apollo4x/CMakeLists.txt | 9 - .../ambiq/apollo4x/Kconfig.defconfig.series | 12 - soc/arm/ambiq/apollo4x/Kconfig.series | 18 - soc/arm/ambiq/apollo4x/Kconfig.soc | 16 - soc/arm/arm/Kconfig | 15 - soc/arm/arm/Kconfig.defconfig | 6 - soc/arm/arm/Kconfig.soc | 6 - soc/arm/arm/beetle/CMakeLists.txt | 8 - .../arm/beetle/Kconfig.defconfig.beetle_r0 | 8 - soc/arm/arm/beetle/Kconfig.defconfig.series | 23 - soc/arm/arm/beetle/Kconfig.series | 14 - soc/arm/arm/beetle/Kconfig.soc | 13 - soc/arm/arm/designstart/CMakeLists.txt | 3 - .../designstart/Kconfig.defconfig.cortex_m1 | 9 - .../designstart/Kconfig.defconfig.cortex_m3 | 9 - .../arm/designstart/Kconfig.defconfig.series | 11 - soc/arm/arm/designstart/Kconfig.series | 9 - soc/arm/arm/designstart/Kconfig.soc | 20 - soc/arm/arm/fvp_aemv8r_aarch32/CMakeLists.txt | 7 - .../Kconfig.defconfig.series | 34 - soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.series | 9 - soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.soc | 18 - soc/arm/arm/mps2/CMakeLists.txt | 7 - soc/arm/arm/mps2/Kconfig.defconfig.mps2_an385 | 12 - soc/arm/arm/mps2/Kconfig.defconfig.mps2_an521 | 12 - soc/arm/arm/mps2/Kconfig.defconfig.series | 14 - soc/arm/arm/mps2/Kconfig.series | 10 - soc/arm/arm/mps2/Kconfig.soc | 29 - soc/arm/arm/mps2/soc.c | 70 -- soc/arm/arm/mps3/CMakeLists.txt | 8 - soc/arm/arm/mps3/Kconfig.defconfig.series | 14 - soc/arm/arm/mps3/Kconfig.series | 10 - soc/arm/arm/mps3/Kconfig.soc | 23 - soc/arm/arm/musca_b1/CMakeLists.txt | 11 - .../arm/musca_b1/Kconfig.defconfig.musca_b1 | 12 - soc/arm/arm/musca_b1/Kconfig.defconfig.series | 14 - soc/arm/arm/musca_b1/Kconfig.series | 10 - soc/arm/arm/musca_b1/Kconfig.soc | 15 - soc/arm/arm/musca_s1/CMakeLists.txt | 7 - .../arm/musca_s1/Kconfig.defconfig.musca_s1 | 12 - soc/arm/arm/musca_s1/Kconfig.defconfig.series | 14 - soc/arm/arm/musca_s1/Kconfig.series | 10 - soc/arm/arm/musca_s1/Kconfig.soc | 17 - soc/arm/aspeed/Kconfig | 17 - soc/arm/aspeed/Kconfig.defconfig | 5 - soc/arm/aspeed/Kconfig.soc | 5 - soc/arm/aspeed/ast10x0/CMakeLists.txt | 17 - .../aspeed/ast10x0/Kconfig.defconfig.series | 22 - soc/arm/aspeed/ast10x0/Kconfig.series | 19 - soc/arm/aspeed/ast10x0/Kconfig.soc | 26 - soc/arm/atmel_sam/CMakeLists.txt | 8 - soc/arm/atmel_sam/Kconfig | 19 - soc/arm/atmel_sam/Kconfig.defconfig | 22 - soc/arm/atmel_sam/Kconfig.soc | 6 - soc/arm/atmel_sam/common/CMakeLists.txt | 12 - soc/arm/atmel_sam/sam3x/CMakeLists.txt | 7 - .../atmel_sam/sam3x/Kconfig.defconfig.series | 27 - soc/arm/atmel_sam/sam3x/Kconfig.series | 21 - soc/arm/atmel_sam/sam3x/Kconfig.soc | 89 -- soc/arm/atmel_sam/sam3x/soc.c | 112 -- soc/arm/atmel_sam/sam3x/soc.h | 52 - soc/arm/atmel_sam/sam4e/CMakeLists.txt | 7 - .../atmel_sam/sam4e/Kconfig.defconfig.series | 33 - soc/arm/atmel_sam/sam4e/Kconfig.series | 21 - soc/arm/atmel_sam/sam4e/Kconfig.soc | 91 -- soc/arm/atmel_sam/sam4e/soc.c | 104 -- soc/arm/atmel_sam/sam4e/soc.h | 52 - soc/arm/atmel_sam/sam4l/CMakeLists.txt | 7 - .../atmel_sam/sam4l/Kconfig.defconfig.series | 44 - soc/arm/atmel_sam/sam4l/Kconfig.series | 19 - soc/arm/atmel_sam/sam4l/Kconfig.soc | 61 - soc/arm/atmel_sam/sam4l/soc.h | 223 ---- soc/arm/atmel_sam/sam4s/CMakeLists.txt | 7 - .../atmel_sam/sam4s/Kconfig.defconfig.series | 32 - soc/arm/atmel_sam/sam4s/Kconfig.series | 21 - soc/arm/atmel_sam/sam4s/Kconfig.soc | 111 -- soc/arm/atmel_sam/sam4s/soc.c | 111 -- soc/arm/atmel_sam/sam4s/soc.h | 66 - soc/arm/atmel_sam/same70/CMakeLists.txt | 8 - .../atmel_sam/same70/Kconfig.defconfig.series | 41 - soc/arm/atmel_sam/same70/Kconfig.series | 28 - soc/arm/atmel_sam/same70/Kconfig.soc | 167 --- soc/arm/atmel_sam/same70/soc.c | 156 --- soc/arm/atmel_sam/same70/soc.h | 82 -- soc/arm/atmel_sam/same70/soc_config.c | 62 - soc/arm/atmel_sam/samv71/CMakeLists.txt | 8 - .../atmel_sam/samv71/Kconfig.defconfig.series | 41 - soc/arm/atmel_sam/samv71/Kconfig.series | 28 - soc/arm/atmel_sam/samv71/Kconfig.soc | 168 --- soc/arm/atmel_sam/samv71/soc.c | 153 --- soc/arm/atmel_sam/samv71/soc.h | 85 -- soc/arm/atmel_sam/samv71/soc_config.c | 66 - soc/arm/atmel_sam0/CMakeLists.txt | 7 - soc/arm/atmel_sam0/Kconfig | 23 - soc/arm/atmel_sam0/Kconfig.defconfig | 13 - soc/arm/atmel_sam0/Kconfig.soc | 6 - soc/arm/atmel_sam0/Kconfig.soc.revisions | 10 - .../common/Kconfig.defconfig.series | 18 - soc/arm/atmel_sam0/common/Kconfig.samc2x | 6 - .../samc20/Kconfig.defconfig.series | 35 - soc/arm/atmel_sam0/samc20/Kconfig.series | 17 - soc/arm/atmel_sam0/samc20/Kconfig.soc | 60 - soc/arm/atmel_sam0/samc20/soc.h | 70 -- .../samc21/Kconfig.defconfig.series | 35 - soc/arm/atmel_sam0/samc21/Kconfig.series | 18 - soc/arm/atmel_sam0/samc21/Kconfig.soc | 60 - soc/arm/atmel_sam0/samc21/soc.h | 70 -- .../samd20/Kconfig.defconfig.series | 36 - soc/arm/atmel_sam0/samd20/Kconfig.series | 17 - soc/arm/atmel_sam0/samd20/Kconfig.soc | 61 - soc/arm/atmel_sam0/samd20/soc.h | 121 -- .../samd21/Kconfig.defconfig.series | 33 - soc/arm/atmel_sam0/samd21/Kconfig.series | 17 - soc/arm/atmel_sam0/samd21/Kconfig.soc | 52 - soc/arm/atmel_sam0/samd21/soc.h | 115 -- .../samd51/Kconfig.defconfig.series | 35 - soc/arm/atmel_sam0/samd51/Kconfig.series | 18 - soc/arm/atmel_sam0/samd51/Kconfig.soc | 37 - soc/arm/atmel_sam0/samd51/soc.h | 56 - .../same51/Kconfig.defconfig.series | 31 - soc/arm/atmel_sam0/same51/Kconfig.series | 18 - soc/arm/atmel_sam0/same51/Kconfig.soc | 25 - soc/arm/atmel_sam0/same51/soc.h | 49 - .../same53/Kconfig.defconfig.series | 31 - soc/arm/atmel_sam0/same53/Kconfig.series | 18 - soc/arm/atmel_sam0/same53/Kconfig.soc | 25 - soc/arm/atmel_sam0/same53/soc.h | 49 - .../same54/Kconfig.defconfig.series | 30 - soc/arm/atmel_sam0/same54/Kconfig.series | 18 - soc/arm/atmel_sam0/same54/Kconfig.soc | 22 - soc/arm/atmel_sam0/same54/soc.h | 48 - .../saml21/Kconfig.defconfig.series | 31 - soc/arm/atmel_sam0/saml21/Kconfig.series | 17 - soc/arm/atmel_sam0/saml21/Kconfig.soc | 46 - soc/arm/atmel_sam0/saml21/soc.h | 76 -- .../samr21/Kconfig.defconfig.series | 26 - soc/arm/atmel_sam0/samr21/Kconfig.series | 17 - soc/arm/atmel_sam0/samr21/Kconfig.soc | 31 - soc/arm/atmel_sam0/samr21/soc.h | 101 -- .../samr34/Kconfig.defconfig.series | 22 - soc/arm/atmel_sam0/samr34/Kconfig.series | 17 - soc/arm/atmel_sam0/samr34/Kconfig.soc | 19 - soc/arm/atmel_sam0/samr34/soc.h | 60 - .../samr35/Kconfig.defconfig.series | 22 - soc/arm/atmel_sam0/samr35/Kconfig.series | 17 - soc/arm/atmel_sam0/samr35/Kconfig.soc | 19 - soc/arm/atmel_sam0/samr35/soc.h | 60 - soc/arm/bcm_vk/Kconfig | 16 - soc/arm/bcm_vk/Kconfig.defconfig | 6 - soc/arm/bcm_vk/Kconfig.soc | 6 - .../bcm_vk/valkyrie/Kconfig.defconfig.series | 21 - .../Kconfig.defconfig.valkyrie_bcm58400 | 7 - soc/arm/bcm_vk/valkyrie/Kconfig.series | 14 - soc/arm/bcm_vk/valkyrie/Kconfig.soc | 12 - soc/arm/bcm_vk/viper/CMakeLists.txt | 8 - soc/arm/bcm_vk/viper/Kconfig.defconfig.series | 11 - soc/arm/bcm_vk/viper/Kconfig.series | 9 - soc/arm/bcm_vk/viper/Kconfig.soc | 14 - soc/arm/{arm => }/beetle/CMSDK_BEETLE.h | 0 soc/arm/beetle/CMakeLists.txt | 10 + soc/arm/beetle/Kconfig | 10 + soc/arm/beetle/Kconfig.defconfig | 18 + soc/arm/beetle/Kconfig.soc | 22 + soc/arm/{arm => }/beetle/power.c | 0 soc/arm/{arm => }/beetle/soc.c | 0 soc/arm/{arm => }/beetle/soc.h | 0 soc/arm/beetle/soc.yml | 4 + soc/arm/{arm => }/beetle/soc_irq.h | 0 soc/arm/{arm => }/beetle/soc_pins.h | 0 soc/arm/{arm => }/beetle/soc_pll.h | 0 soc/arm/{arm => }/beetle/soc_power.h | 0 soc/arm/{arm => }/beetle/soc_registers.h | 0 soc/arm/cypress/CMakeLists.txt | 9 - soc/arm/cypress/Kconfig | 44 - soc/arm/cypress/Kconfig.defconfig | 4 - soc/arm/cypress/Kconfig.soc | 4 - soc/arm/cypress/psoc6/CMakeLists.txt | 16 - .../cypress/psoc6/Kconfig.defconfig.psoc6_m0 | 14 - .../cypress/psoc6/Kconfig.defconfig.psoc6_m4 | 14 - .../cypress/psoc6/Kconfig.defconfig.series | 25 - soc/arm/cypress/psoc6/Kconfig.series | 21 - soc/arm/cypress/psoc6/Kconfig.soc | 20 - .../valkyrie => designstart}/CMakeLists.txt | 0 soc/arm/designstart/Kconfig | 15 + soc/arm/designstart/Kconfig.soc | 27 + soc/arm/{arm => }/designstart/soc.h | 0 soc/arm/fvp_aemv8a/CMakeLists.txt | 8 + soc/arm/fvp_aemv8a/Kconfig | 10 + soc/arm/fvp_aemv8a/Kconfig.defconfig | 26 + soc/arm/fvp_aemv8a/Kconfig.soc | 15 + soc/{arm64 => }/arm/fvp_aemv8a/mmu_regions.c | 0 soc/arm/fvp_aemv8r/CMakeLists.txt | 14 + soc/arm/fvp_aemv8r/Kconfig | 18 + soc/arm/fvp_aemv8r/Kconfig.defconfig | 25 + soc/arm/fvp_aemv8r/Kconfig.soc | 33 + .../aarch32}/arm_mpu_regions.c | 0 .../aarch32}/soc.c | 0 .../aarch32}/soc.h | 0 .../fvp_aemv8r/aarch64}/arm_mpu_regions.c | 0 .../fvp_aemv8r/aarch64}/soc.c | 0 soc/arm/gd_gd32/Kconfig | 23 - soc/arm/gd_gd32/Kconfig.defconfig | 17 - soc/arm/gd_gd32/Kconfig.soc | 4 - soc/arm/gd_gd32/common/pinctrl_soc.h | 17 - .../gd_gd32/gd32a50x/Kconfig.defconfig.series | 11 - soc/arm/gd_gd32/gd32a50x/Kconfig.series | 16 - soc/arm/gd_gd32/gd32a50x/Kconfig.soc | 11 - .../gd_gd32/gd32e10x/Kconfig.defconfig.series | 11 - soc/arm/gd_gd32/gd32e10x/Kconfig.series | 15 - soc/arm/gd_gd32/gd32e10x/Kconfig.soc | 10 - .../gd_gd32/gd32e50x/Kconfig.defconfig.series | 11 - soc/arm/gd_gd32/gd32e50x/Kconfig.series | 15 - soc/arm/gd_gd32/gd32e50x/Kconfig.soc | 11 - .../gd_gd32/gd32f3x0/Kconfig.defconfig.series | 11 - soc/arm/gd_gd32/gd32f3x0/Kconfig.series | 13 - soc/arm/gd_gd32/gd32f3x0/Kconfig.soc | 10 - .../gd_gd32/gd32f403/Kconfig.defconfig.series | 11 - soc/arm/gd_gd32/gd32f403/Kconfig.series | 16 - soc/arm/gd_gd32/gd32f403/Kconfig.soc | 11 - .../gd_gd32/gd32f4xx/Kconfig.defconfig.series | 11 - soc/arm/gd_gd32/gd32f4xx/Kconfig.series | 14 - soc/arm/gd_gd32/gd32f4xx/Kconfig.soc | 21 - .../gd_gd32/gd32l23x/Kconfig.defconfig.series | 11 - soc/arm/gd_gd32/gd32l23x/Kconfig.series | 14 - soc/arm/gd_gd32/gd32l23x/Kconfig.soc | 10 - soc/arm/infineon_cat1/CMakeLists.txt | 6 - soc/arm/infineon_cat1/Kconfig | 19 - soc/arm/infineon_cat1/Kconfig.defconfig | 5 - soc/arm/infineon_cat1/Kconfig.soc | 5 - soc/arm/infineon_cat1/psoc6/CMakeLists.txt | 21 - soc/arm/infineon_cat1/psoc6/Kconfig.defconfig | 22 - .../infineon_cat1/psoc6/Kconfig.defconfig.soc | 5 - .../psoc6/Kconfig.defconfig.soc.psoc6_01 | 77 -- .../psoc6/Kconfig.defconfig.soc.psoc6_02 | 49 - .../psoc6/Kconfig.defconfig.soc.psoc6_04 | 37 - soc/arm/infineon_cat1/psoc6/Kconfig.series | 34 - soc/arm/infineon_cat1/psoc6/Kconfig.soc | 117 -- .../infineon_cat1/psoc6/Kconfig.soc.psoc6_01 | 365 ------ .../infineon_cat1/psoc6/Kconfig.soc.psoc6_02 | 197 --- .../infineon_cat1/psoc6/Kconfig.soc.psoc6_04 | 125 -- soc/arm/infineon_xmc/4xxx/CMakeLists.txt | 9 - .../4xxx/Kconfig.defconfig.series | 17 - soc/arm/infineon_xmc/4xxx/Kconfig.series | 27 - soc/arm/infineon_xmc/4xxx/Kconfig.soc | 38 - soc/arm/infineon_xmc/Kconfig | 22 - soc/arm/infineon_xmc/Kconfig.defconfig | 13 - soc/arm/infineon_xmc/Kconfig.soc | 6 - soc/arm/intel_socfpga_std/CMakeLists.txt | 6 - soc/arm/intel_socfpga_std/Kconfig | 15 - soc/arm/intel_socfpga_std/Kconfig.defconfig | 6 - soc/arm/intel_socfpga_std/Kconfig.soc | 6 - .../intel_socfpga_std/cyclonev/CMakeLists.txt | 9 - .../cyclonev/Kconfig.defconfig.cyclonev | 19 - .../cyclonev/Kconfig.defconfig.series | 13 - .../intel_socfpga_std/cyclonev/Kconfig.series | 14 - .../intel_socfpga_std/cyclonev/Kconfig.soc | 12 - soc/arm/microchip_mec/Kconfig | 222 ---- soc/arm/microchip_mec/Kconfig.defconfig | 3 - soc/arm/microchip_mec/Kconfig.soc | 6 - soc/arm/microchip_mec/common/CMakeLists.txt | 27 - soc/arm/microchip_mec/mec1501/CMakeLists.txt | 25 - .../mec1501/Kconfig.defconfig.series | 32 - soc/arm/microchip_mec/mec1501/Kconfig.series | 15 - soc/arm/microchip_mec/mec1501/Kconfig.soc | 97 -- soc/arm/microchip_mec/mec172x/CMakeLists.txt | 25 - .../mec172x/Kconfig.defconfig.series | 36 - soc/arm/microchip_mec/mec172x/Kconfig.series | 17 - soc/arm/microchip_mec/mec172x/Kconfig.soc | 84 -- soc/arm/mps2/CMakeLists.txt | 7 + soc/arm/mps2/Kconfig | 21 + soc/arm/mps2/Kconfig.defconfig | 11 + soc/arm/mps2/Kconfig.defconfig.an385 | 9 + soc/arm/mps2/Kconfig.defconfig.an521 | 9 + soc/arm/mps2/Kconfig.soc | 37 + soc/arm/mps2/soc.c | 70 ++ soc/arm/{arm => }/mps2/soc.h | 0 soc/arm/{arm => }/mps2/soc_registers.h | 0 soc/arm/mps3/CMakeLists.txt | 10 + soc/arm/mps3/Kconfig | 20 + soc/arm/mps3/Kconfig.defconfig | 11 + .../mps3/Kconfig.defconfig.mps3_an547 | 3 - soc/arm/mps3/Kconfig.soc | 18 + soc/arm/{arm => }/mps3/soc.c | 0 soc/arm/{arm => }/mps3/soc.h | 0 soc/arm/musca/CMakeLists.txt | 14 + soc/arm/musca/Kconfig | 20 + soc/arm/musca/Kconfig.defconfig | 9 + soc/arm/musca/Kconfig.soc | 27 + soc/arm/{arm/musca_b1 => musca/b1}/soc.c | 0 soc/arm/{arm/musca_b1 => musca/b1}/soc.h | 0 .../b1}/system_cmsdk_musca_b1.h | 0 soc/arm/{arm/musca_s1 => musca/s1}/soc.h | 0 .../s1}/system_cmsdk_musca_s1.h | 0 soc/arm/nordic_nrf/CMakeLists.txt | 34 - soc/arm/nordic_nrf/Kconfig | 175 --- soc/arm/nordic_nrf/Kconfig.defconfig | 45 - soc/arm/nordic_nrf/Kconfig.soc | 6 - soc/arm/nordic_nrf/common/CMakeLists.txt | 16 - soc/arm/nordic_nrf/nrf51/CMakeLists.txt | 3 - .../nrf51/Kconfig.defconfig.nrf51822_QFAA | 9 - .../nrf51/Kconfig.defconfig.nrf51822_QFAB | 9 - .../nrf51/Kconfig.defconfig.nrf51822_QFAC | 9 - .../nordic_nrf/nrf51/Kconfig.defconfig.series | 21 - soc/arm/nordic_nrf/nrf51/Kconfig.series | 17 - soc/arm/nordic_nrf/nrf51/Kconfig.soc | 19 - soc/arm/nordic_nrf/nrf52/CMakeLists.txt | 15 - .../nordic_nrf/nrf52/Kconfig.defconfig.series | 17 - soc/arm/nordic_nrf/nrf52/Kconfig.series | 20 - soc/arm/nordic_nrf/nrf52/Kconfig.soc | 158 --- soc/arm/nordic_nrf/nrf53/CMakeLists.txt | 17 - .../nordic_nrf/nrf53/Kconfig.defconfig.series | 17 - soc/arm/nordic_nrf/nrf53/Kconfig.series | 20 - soc/arm/nordic_nrf/nrf53/Kconfig.soc | 225 ---- soc/arm/nordic_nrf/nrf54h/CMakeLists.txt | 7 - .../nrf54h/Kconfig.defconfig.nrf54h20_cpuapp | 17 - .../nrf54h/Kconfig.defconfig.nrf54h20_cpurad | 17 - .../nrf54h/Kconfig.defconfig.series | 16 - soc/arm/nordic_nrf/nrf54h/Kconfig.series | 16 - soc/arm/nordic_nrf/nrf54h/Kconfig.soc | 37 - soc/arm/nordic_nrf/nrf54l/CMakeLists.txt | 10 - .../nrf54l/Kconfig.defconfig.series | 19 - soc/arm/nordic_nrf/nrf54l/Kconfig.series | 13 - soc/arm/nordic_nrf/nrf54l/Kconfig.soc | 70 -- soc/arm/nordic_nrf/nrf91/CMakeLists.txt | 3 - .../nordic_nrf/nrf91/Kconfig.defconfig.series | 17 - soc/arm/nordic_nrf/nrf91/Kconfig.series | 35 - soc/arm/nordic_nrf/nrf91/Kconfig.soc | 47 - soc/arm/nuvoton_npcx/Kconfig | 195 --- soc/arm/nuvoton_npcx/Kconfig.defconfig | 6 - soc/arm/nuvoton_npcx/Kconfig.soc | 6 - soc/arm/nuvoton_npcx/common/CMakeLists.txt | 47 - soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt | 9 - .../npcx4/Kconfig.defconfig.npcx4m3f | 11 - .../npcx4/Kconfig.defconfig.npcx4m8f | 11 - .../npcx4/Kconfig.defconfig.series | 23 - soc/arm/nuvoton_npcx/npcx4/Kconfig.series | 16 - soc/arm/nuvoton_npcx/npcx4/Kconfig.soc | 16 - soc/arm/nuvoton_npcx/npcx7/CMakeLists.txt | 14 - .../npcx7/Kconfig.defconfig.npcx7m6fb | 11 - .../npcx7/Kconfig.defconfig.npcx7m6fc | 11 - .../npcx7/Kconfig.defconfig.npcx7m7fc | 11 - .../npcx7/Kconfig.defconfig.series | 19 - soc/arm/nuvoton_npcx/npcx7/Kconfig.series | 17 - soc/arm/nuvoton_npcx/npcx7/Kconfig.soc | 19 - soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt | 5 - .../npcx9/Kconfig.defconfig.npcx9m3f | 11 - .../npcx9/Kconfig.defconfig.npcx9m6f | 11 - .../npcx9/Kconfig.defconfig.npcx9m7f | 11 - .../npcx9/Kconfig.defconfig.npcx9mfp | 11 - .../npcx9/Kconfig.defconfig.series | 19 - soc/arm/nuvoton_npcx/npcx9/Kconfig.series | 16 - soc/arm/nuvoton_npcx/npcx9/Kconfig.soc | 22 - soc/arm/nuvoton_numaker/Kconfig | 18 - soc/arm/nuvoton_numaker/Kconfig.defconfig | 12 - soc/arm/nuvoton_numaker/Kconfig.soc | 5 - soc/arm/nuvoton_numaker/m46x/CMakeLists.txt | 7 - .../m46x/Kconfig.defconfig.series | 12 - soc/arm/nuvoton_numaker/m46x/Kconfig.series | 15 - soc/arm/nuvoton_numaker/m46x/Kconfig.soc | 13 - soc/arm/nuvoton_numicro/Kconfig | 17 - soc/arm/nuvoton_numicro/Kconfig.defconfig | 6 - soc/arm/nuvoton_numicro/Kconfig.soc | 6 - soc/arm/nuvoton_numicro/m48x/CMakeLists.txt | 8 - .../m48x/Kconfig.defconfig.series | 13 - soc/arm/nuvoton_numicro/m48x/Kconfig.series | 15 - soc/arm/nuvoton_numicro/m48x/Kconfig.soc | 14 - soc/arm/nxp_imx/CMakeLists.txt | 7 - soc/arm/nxp_imx/Kconfig | 45 - soc/arm/nxp_imx/Kconfig.defconfig | 8 - soc/arm/nxp_imx/Kconfig.soc | 4 - soc/arm/nxp_imx/mcimx6x_m4/CMakeLists.txt | 12 - .../mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 | 14 - .../mcimx6x_m4/Kconfig.defconfig.series | 21 - soc/arm/nxp_imx/mcimx6x_m4/Kconfig.series | 17 - soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc | 85 -- soc/arm/nxp_imx/mcimx7_m4/CMakeLists.txt | 12 - .../mcimx7_m4/Kconfig.defconfig.mcimx7_m4 | 17 - .../mcimx7_m4/Kconfig.defconfig.series | 21 - soc/arm/nxp_imx/mcimx7_m4/Kconfig.series | 16 - soc/arm/nxp_imx/mcimx7_m4/Kconfig.soc | 40 - soc/arm/nxp_imx/mimx8ml8_m7/CMakeLists.txt | 19 - .../mimx8ml8_m7/Kconfig.defconfig.mimx8ml8_m7 | 43 - .../mimx8ml8_m7/Kconfig.defconfig.series | 22 - soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.series | 16 - soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc | 50 - soc/arm/nxp_imx/mimx8mm6_m4/CMakeLists.txt | 16 - .../mimx8mm6_m4/Kconfig.defconfig.mimx8mm6_m4 | 20 - .../mimx8mm6_m4/Kconfig.defconfig.series | 22 - soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.series | 14 - soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.soc | 33 - soc/arm/nxp_imx/mimx8mq6_m4/CMakeLists.txt | 11 - .../mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4 | 20 - .../mimx8mq6_m4/Kconfig.defconfig.series | 18 - soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.series | 14 - soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.soc | 32 - soc/arm/nxp_imx/rt/CMakeLists.txt | 76 -- .../nxp_imx/rt/Kconfig.defconfig.mimxrt1010 | 24 - .../nxp_imx/rt/Kconfig.defconfig.mimxrt1015 | 20 - .../nxp_imx/rt/Kconfig.defconfig.mimxrt1021 | 20 - .../nxp_imx/rt/Kconfig.defconfig.mimxrt1024 | 20 - .../nxp_imx/rt/Kconfig.defconfig.mimxrt1042 | 19 - .../nxp_imx/rt/Kconfig.defconfig.mimxrt1052 | 17 - .../nxp_imx/rt/Kconfig.defconfig.mimxrt1062 | 17 - .../nxp_imx/rt/Kconfig.defconfig.mimxrt1064 | 17 - .../rt/Kconfig.defconfig.mimxrt1166_cm4 | 20 - .../rt/Kconfig.defconfig.mimxrt1166_cm7 | 20 - .../rt/Kconfig.defconfig.mimxrt1176_cm4 | 20 - .../rt/Kconfig.defconfig.mimxrt1176_cm7 | 20 - soc/arm/nxp_imx/rt/Kconfig.defconfig.series | 146 --- soc/arm/nxp_imx/rt/Kconfig.series | 14 - soc/arm/nxp_imx/rt/Kconfig.soc | 837 ------------- soc/arm/nxp_imx/rt/boot_header.ld | 15 - soc/arm/nxp_imx/rt/linker.ld | 18 - soc/arm/nxp_imx/rt/pinctrl_soc.h | 15 - soc/arm/nxp_imx/rt/power_rt10xx.c | 276 ----- soc/arm/nxp_imx/rt/soc.h | 45 - soc/arm/nxp_imx/rt/soc_rt10xx.c | 344 ------ soc/arm/nxp_imx/rt/soc_rt11xx.c | 728 ----------- soc/arm/nxp_imx/rt5xx/CMakeLists.txt | 33 - .../rt5xx/Kconfig.defconfig.mimxrt595_cm33 | 40 - .../nxp_imx/rt5xx/Kconfig.defconfig.series | 82 -- soc/arm/nxp_imx/rt5xx/Kconfig.series | 16 - soc/arm/nxp_imx/rt5xx/Kconfig.soc | 156 --- soc/arm/nxp_imx/rt5xx/boot_header.ld | 10 - soc/arm/nxp_imx/rt5xx/soc.c | 544 --------- soc/arm/nxp_imx/rt6xx/CMakeLists.txt | 36 - .../rt6xx/Kconfig.defconfig.mimxrt685_cm33 | 32 - .../nxp_imx/rt6xx/Kconfig.defconfig.series | 81 -- soc/arm/nxp_imx/rt6xx/Kconfig.series | 17 - soc/arm/nxp_imx/rt6xx/Kconfig.soc | 136 --- soc/arm/nxp_imx/rt6xx/boot_header.ld | 10 - soc/arm/nxp_imx/rt6xx/soc.c | 395 ------ soc/arm/nxp_kinetis/Kconfig | 168 --- soc/arm/nxp_kinetis/Kconfig.defconfig | 11 - soc/arm/nxp_kinetis/Kconfig.soc | 4 - soc/arm/nxp_kinetis/k2x/CMakeLists.txt | 17 - .../nxp_kinetis/k2x/Kconfig.defconfig.mk22f12 | 17 - .../k2x/Kconfig.defconfig.mk22fx12 | 17 - .../nxp_kinetis/k2x/Kconfig.defconfig.series | 17 - soc/arm/nxp_kinetis/k2x/Kconfig.series | 19 - soc/arm/nxp_kinetis/k2x/Kconfig.soc | 69 -- soc/arm/nxp_kinetis/k6x/CMakeLists.txt | 11 - .../nxp_kinetis/k6x/Kconfig.defconfig.mk64f12 | 21 - .../nxp_kinetis/k6x/Kconfig.defconfig.mk66f18 | 18 - .../nxp_kinetis/k6x/Kconfig.defconfig.series | 16 - soc/arm/nxp_kinetis/k6x/Kconfig.series | 17 - soc/arm/nxp_kinetis/k6x/Kconfig.soc | 110 -- soc/arm/nxp_kinetis/k8x/CMakeLists.txt | 11 - .../k8x/Kconfig.defconfig.mk80f25615 | 8 - .../k8x/Kconfig.defconfig.mk82f25615 | 8 - .../nxp_kinetis/k8x/Kconfig.defconfig.series | 27 - soc/arm/nxp_kinetis/k8x/Kconfig.series | 32 - soc/arm/nxp_kinetis/k8x/Kconfig.soc | 72 -- soc/arm/nxp_kinetis/ke1xf/CMakeLists.txt | 15 - .../ke1xf/Kconfig.defconfig.mke14f16 | 8 - .../ke1xf/Kconfig.defconfig.mke16f16 | 11 - .../ke1xf/Kconfig.defconfig.mke18f16 | 11 - .../ke1xf/Kconfig.defconfig.series | 41 - soc/arm/nxp_kinetis/ke1xf/Kconfig.series | 37 - soc/arm/nxp_kinetis/ke1xf/Kconfig.soc | 103 -- soc/arm/nxp_kinetis/kl2x/CMakeLists.txt | 5 - .../kl2x/Kconfig.defconfig.mkl25z4 | 14 - .../nxp_kinetis/kl2x/Kconfig.defconfig.series | 13 - soc/arm/nxp_kinetis/kl2x/Kconfig.series | 16 - soc/arm/nxp_kinetis/kl2x/Kconfig.soc | 81 -- soc/arm/nxp_kinetis/kv5x/CMakeLists.txt | 7 - .../kv5x/Kconfig.defconfig.mkv56f24 | 8 - .../kv5x/Kconfig.defconfig.mkv58f24 | 8 - .../nxp_kinetis/kv5x/Kconfig.defconfig.series | 20 - soc/arm/nxp_kinetis/kv5x/Kconfig.series | 27 - soc/arm/nxp_kinetis/kv5x/Kconfig.soc | 60 - soc/arm/nxp_kinetis/kwx/CMakeLists.txt | 8 - .../kwx/Kconfig.defconfig.mkw2xd512 | 22 - .../nxp_kinetis/kwx/Kconfig.defconfig.mkw40z4 | 24 - .../nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4 | 42 - .../nxp_kinetis/kwx/Kconfig.defconfig.series | 13 - soc/arm/nxp_kinetis/kwx/Kconfig.series | 15 - soc/arm/nxp_kinetis/kwx/Kconfig.soc | 96 -- soc/arm/nxp_lpc/Kconfig | 22 - soc/arm/nxp_lpc/Kconfig.defconfig | 8 - soc/arm/nxp_lpc/Kconfig.soc | 4 - soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt | 7 - .../lpc11u6x/Kconfig.defconfig.lpc11u66 | 11 - .../lpc11u6x/Kconfig.defconfig.lpc11u67 | 11 - .../lpc11u6x/Kconfig.defconfig.lpc11u68 | 11 - .../nxp_lpc/lpc11u6x/Kconfig.defconfig.series | 17 - soc/arm/nxp_lpc/lpc11u6x/Kconfig.series | 15 - soc/arm/nxp_lpc/lpc11u6x/Kconfig.soc | 52 - soc/arm/nxp_lpc/lpc51u68/CMakeLists.txt | 15 - .../nxp_lpc/lpc51u68/Kconfig.defconfig.series | 22 - soc/arm/nxp_lpc/lpc51u68/Kconfig.series | 19 - soc/arm/nxp_lpc/lpc51u68/Kconfig.soc | 27 - soc/arm/nxp_lpc/lpc54xxx/CMakeLists.txt | 23 - .../lpc54xxx/Kconfig.defconfig.lpc54114_m0 | 14 - .../lpc54xxx/Kconfig.defconfig.lpc54114_m4 | 11 - .../nxp_lpc/lpc54xxx/Kconfig.defconfig.series | 17 - soc/arm/nxp_lpc/lpc54xxx/Kconfig.series | 16 - soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc | 78 -- soc/arm/nxp_lpc/lpc55xxx/CMakeLists.txt | 27 - .../lpc55xxx/Kconfig.defconfig.lpc55S06 | 14 - .../lpc55xxx/Kconfig.defconfig.lpc55S16 | 19 - .../lpc55xxx/Kconfig.defconfig.lpc55S28 | 15 - .../lpc55xxx/Kconfig.defconfig.lpc55S36 | 18 - .../lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0 | 23 - .../lpc55xxx/Kconfig.defconfig.lpc55S69_cpu1 | 17 - .../nxp_lpc/lpc55xxx/Kconfig.defconfig.series | 17 - soc/arm/nxp_lpc/lpc55xxx/Kconfig.series | 18 - soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc | 177 --- soc/arm/nxp_s32/Kconfig | 38 - soc/arm/nxp_s32/Kconfig.defconfig | 4 - soc/arm/nxp_s32/Kconfig.soc | 4 - soc/arm/nxp_s32/common/CMakeLists.txt | 6 - soc/arm/nxp_s32/s32k1/CMakeLists.txt | 10 - .../nxp_s32/s32k1/Kconfig.defconfig.s32k146 | 14 - .../nxp_s32/s32k1/Kconfig.defconfig.series | 32 - soc/arm/nxp_s32/s32k1/Kconfig.series | 24 - soc/arm/nxp_s32/s32k1/Kconfig.soc | 445 ------- soc/arm/nxp_s32/s32k1/soc.c | 78 -- soc/arm/nxp_s32/s32k3/CMakeLists.txt | 11 - .../nxp_s32/s32k3/Kconfig.defconfig.s32k344 | 14 - .../nxp_s32/s32k3/Kconfig.defconfig.series | 40 - soc/arm/nxp_s32/s32k3/Kconfig.series | 27 - soc/arm/nxp_s32/s32k3/Kconfig.soc | 61 - soc/arm/nxp_s32/s32ze/CMakeLists.txt | 10 - .../nxp_s32/s32ze/Kconfig.defconfig.s32z27 | 9 - .../nxp_s32/s32ze/Kconfig.defconfig.series | 45 - soc/arm/nxp_s32/s32ze/Kconfig.series | 21 - soc/arm/nxp_s32/s32ze/Kconfig.soc | 35 - soc/arm/nxp_s32/s32ze/soc.h | 74 -- soc/arm/qemu_cortex_a53/CMakeLists.txt | 8 + soc/arm/qemu_cortex_a53/Kconfig | 7 + soc/arm/qemu_cortex_a53/Kconfig.defconfig | 25 + soc/arm/qemu_cortex_a53/Kconfig.soc | 9 + .../qemu_cortex_a53/mmu_regions.c | 0 .../qemu_virt_arm64/CMakeLists.txt | 0 soc/arm/qemu_virt_arm64/Kconfig | 7 + soc/arm/qemu_virt_arm64/Kconfig.defconfig | 26 + soc/arm/qemu_virt_arm64/Kconfig.soc | 9 + .../qemu_virt_arm64/mmu_regions.c | 0 soc/arm/quicklogic_eos_s3/CMakeLists.txt | 8 - soc/arm/quicklogic_eos_s3/Kconfig | 5 - soc/arm/quicklogic_eos_s3/Kconfig.defconfig | 22 - soc/arm/quicklogic_eos_s3/Kconfig.soc | 11 - soc/arm/renesas_ra/Kconfig | 18 - soc/arm/renesas_ra/Kconfig.defconfig | 4 - soc/arm/renesas_ra/Kconfig.soc | 4 - soc/arm/renesas_ra/ra4m1/CMakeLists.txt | 4 - .../ra4m1/Kconfig.defconfig.r7fa4m1xxxxxx | 9 - .../renesas_ra/ra4m1/Kconfig.defconfig.series | 14 - soc/arm/renesas_ra/ra4m1/Kconfig.series | 13 - soc/arm/renesas_ra/ra4m1/Kconfig.soc | 11 - soc/arm/renesas_ra/ra4m1/linker.ld | 8 - soc/arm/renesas_rcar/Kconfig | 17 - soc/arm/renesas_rcar/Kconfig.defconfig | 4 - soc/arm/renesas_rcar/Kconfig.soc | 7 - soc/arm/renesas_rcar/gen3/CMakeLists.txt | 9 - .../gen3/Kconfig.defconfig.r8a77951 | 9 - .../gen3/Kconfig.defconfig.series | 17 - soc/arm/renesas_rcar/gen3/Kconfig.series | 13 - soc/arm/renesas_rcar/gen3/Kconfig.soc | 11 - soc/arm/renesas_rcar/gen4/CMakeLists.txt | 4 - .../gen4/Kconfig.defconfig.series | 13 - soc/arm/renesas_rcar/gen4/Kconfig.series | 13 - soc/arm/renesas_rcar/gen4/Kconfig.soc | 11 - soc/arm/renesas_rcar/gen4/linker.ld | 7 - soc/arm/renesas_rzt2m/CMakeLists.txt | 6 - soc/arm/renesas_rzt2m/Kconfig | 15 - soc/arm/renesas_rzt2m/Kconfig.defconfig | 24 - soc/arm/renesas_rzt2m/Kconfig.soc | 12 - soc/arm/renesas_smartbond/Kconfig | 19 - soc/arm/renesas_smartbond/Kconfig.defconfig | 11 - soc/arm/renesas_smartbond/Kconfig.soc | 4 - .../renesas_smartbond/da1469x/CMakeLists.txt | 11 - .../da1469x/Kconfig.defconfig.da14695 | 9 - .../da1469x/Kconfig.defconfig.da14699 | 9 - .../da1469x/Kconfig.defconfig.series | 32 - .../renesas_smartbond/da1469x/Kconfig.series | 17 - soc/arm/renesas_smartbond/da1469x/Kconfig.soc | 14 - soc/arm/rpi_pico/CMakeLists.txt | 3 - soc/arm/rpi_pico/Kconfig | 18 - soc/arm/rpi_pico/Kconfig.defconfig | 13 - soc/arm/rpi_pico/Kconfig.soc | 6 - soc/arm/rpi_pico/rp2/CMakeLists.txt | 8 - soc/arm/rpi_pico/rp2/Kconfig.defconfig.series | 17 - soc/arm/rpi_pico/rp2/Kconfig.series | 19 - soc/arm/rpi_pico/rp2/Kconfig.soc | 50 - soc/arm/silabs_exx32/CMakeLists.txt | 3 - soc/arm/silabs_exx32/Kconfig | 352 ------ soc/arm/silabs_exx32/Kconfig.defconfig | 21 - soc/arm/silabs_exx32/Kconfig.soc | 4 - soc/arm/silabs_exx32/common/pinctrl_soc.h | 95 -- soc/arm/silabs_exx32/common/soc.c | 247 ---- soc/arm/silabs_exx32/common/soc_gpio.h | 32 - .../efm32gg11b/Kconfig.defconfig.efm32gg11b | 8 - .../efm32gg11b/Kconfig.defconfig.series | 22 - .../silabs_exx32/efm32gg11b/Kconfig.series | 23 - soc/arm/silabs_exx32/efm32gg11b/Kconfig.soc | 12 - .../efm32gg12b/Kconfig.defconfig.efm32gg12b | 7 - .../efm32gg12b/Kconfig.defconfig.series | 20 - .../silabs_exx32/efm32gg12b/Kconfig.series | 22 - soc/arm/silabs_exx32/efm32gg12b/Kconfig.soc | 7 - .../efm32hg/Kconfig.defconfig.series | 19 - soc/arm/silabs_exx32/efm32hg/Kconfig.series | 19 - soc/arm/silabs_exx32/efm32hg/Kconfig.soc | 8 - .../efm32jg12b/Kconfig.defconfig.series | 18 - .../silabs_exx32/efm32jg12b/Kconfig.series | 23 - soc/arm/silabs_exx32/efm32jg12b/Kconfig.soc | 8 - .../efm32pg12b/Kconfig.defconfig.series | 18 - .../silabs_exx32/efm32pg12b/Kconfig.series | 26 - soc/arm/silabs_exx32/efm32pg12b/Kconfig.soc | 8 - .../efm32pg1b/Kconfig.defconfig.series | 18 - soc/arm/silabs_exx32/efm32pg1b/Kconfig.series | 24 - soc/arm/silabs_exx32/efm32pg1b/Kconfig.soc | 8 - .../efm32wg/Kconfig.defconfig.series | 18 - soc/arm/silabs_exx32/efm32wg/Kconfig.series | 20 - soc/arm/silabs_exx32/efm32wg/Kconfig.soc | 8 - .../efr32bg13p/Kconfig.defconfig.series | 18 - .../silabs_exx32/efr32bg13p/Kconfig.series | 24 - soc/arm/silabs_exx32/efr32bg13p/Kconfig.soc | 11 - .../efr32bg22/Kconfig.defconfig.efr32bg22 | 7 - .../efr32bg22/Kconfig.defconfig.series | 24 - soc/arm/silabs_exx32/efr32bg22/Kconfig.series | 27 - soc/arm/silabs_exx32/efr32bg22/Kconfig.soc | 8 - .../efr32bg27/Kconfig.defconfig.efr32bg27 | 7 - .../efr32bg27/Kconfig.defconfig.series | 23 - soc/arm/silabs_exx32/efr32bg27/Kconfig.series | 26 - soc/arm/silabs_exx32/efr32bg27/Kconfig.soc | 8 - .../efr32fg13p/Kconfig.defconfig.series | 18 - .../silabs_exx32/efr32fg13p/Kconfig.series | 25 - soc/arm/silabs_exx32/efr32fg13p/Kconfig.soc | 8 - .../efr32fg1p/Kconfig.defconfig.series | 18 - soc/arm/silabs_exx32/efr32fg1p/Kconfig.series | 25 - soc/arm/silabs_exx32/efr32fg1p/Kconfig.soc | 8 - .../efr32mg12p/Kconfig.defconfig.series | 20 - .../silabs_exx32/efr32mg12p/Kconfig.series | 26 - soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc | 16 - .../efr32mg21/Kconfig.defconfig.efr32mg21 | 8 - .../efr32mg21/Kconfig.defconfig.series | 21 - soc/arm/silabs_exx32/efr32mg21/Kconfig.series | 26 - soc/arm/silabs_exx32/efr32mg21/Kconfig.soc | 8 - soc/arm/silabs_exx32/efr32mg21/soc.h | 28 - soc/arm/silabs_exx32/efr32mg21/soc_pinmap.h | 22 - .../efr32mg24/Kconfig.defconfig.series | 29 - soc/arm/silabs_exx32/efr32mg24/Kconfig.series | 28 - soc/arm/silabs_exx32/efr32mg24/Kconfig.soc | 12 - soc/arm/silabs_exx32/efr32mg24/soc.h | 30 - soc/arm/silabs_exx32/efr32mg24/soc_pinmap.h | 22 - soc/arm/soc.yml | 33 + soc/arm/st_stm32/CMakeLists.txt | 6 - soc/arm/st_stm32/Kconfig | 29 - soc/arm/st_stm32/Kconfig.defconfig | 3 - soc/arm/st_stm32/Kconfig.soc | 6 - soc/arm/st_stm32/common/CMakeLists.txt | 14 - .../st_stm32/common/Kconfig.defconfig.series | 65 - soc/arm/st_stm32/common/Kconfig.soc | 72 -- soc/arm/st_stm32/common/pm_debug_swj.c | 40 - soc/arm/st_stm32/stm32c0/CMakeLists.txt | 8 - .../st_stm32/stm32c0/Kconfig.defconfig.series | 13 - soc/arm/st_stm32/stm32c0/Kconfig.series | 16 - soc/arm/st_stm32/stm32c0/Kconfig.soc | 13 - soc/arm/st_stm32/stm32f0/CMakeLists.txt | 12 - .../st_stm32/stm32f0/Kconfig.defconfig.series | 23 - .../stm32f0/Kconfig.defconfig.stm32f030x4 | 14 - soc/arm/st_stm32/stm32f0/Kconfig.series | 15 - soc/arm/st_stm32/stm32f0/Kconfig.soc | 46 - soc/arm/st_stm32/stm32f1/CMakeLists.txt | 8 - .../st_stm32/stm32f1/Kconfig.defconfig.series | 20 - soc/arm/st_stm32/stm32f1/Kconfig.series | 15 - soc/arm/st_stm32/stm32f1/Kconfig.soc | 59 - soc/arm/st_stm32/stm32f2/CMakeLists.txt | 8 - .../st_stm32/stm32f2/Kconfig.defconfig.series | 15 - .../stm32f2/Kconfig.defconfig.stm32f205xx | 14 - .../stm32f2/Kconfig.defconfig.stm32f207xx | 14 - soc/arm/st_stm32/stm32f2/Kconfig.series | 16 - soc/arm/st_stm32/stm32f2/Kconfig.soc | 16 - soc/arm/st_stm32/stm32f3/CMakeLists.txt | 8 - .../st_stm32/stm32f3/Kconfig.defconfig.series | 15 - .../stm32f3/Kconfig.defconfig.stm32f302x8 | 14 - .../stm32f3/Kconfig.defconfig.stm32f302xc | 14 - .../stm32f3/Kconfig.defconfig.stm32f303xe | 14 - .../stm32f3/Kconfig.defconfig.stm32f334x8 | 14 - .../stm32f3/Kconfig.defconfig.stm32f373xc | 14 - soc/arm/st_stm32/stm32f3/Kconfig.series | 16 - soc/arm/st_stm32/stm32f3/Kconfig.soc | 39 - soc/arm/st_stm32/stm32f4/CMakeLists.txt | 12 - .../st_stm32/stm32f4/Kconfig.defconfig.series | 33 - .../stm32f4/Kconfig.defconfig.stm32f405xx | 14 - .../stm32f4/Kconfig.defconfig.stm32f407xx | 24 - .../stm32f4/Kconfig.defconfig.stm32f412xx | 34 - soc/arm/st_stm32/stm32f4/Kconfig.series | 18 - soc/arm/st_stm32/stm32f4/Kconfig.soc | 70 -- soc/arm/st_stm32/stm32f7/CMakeLists.txt | 8 - .../st_stm32/stm32f7/Kconfig.defconfig.series | 15 - soc/arm/st_stm32/stm32f7/Kconfig.series | 19 - soc/arm/st_stm32/stm32f7/Kconfig.soc | 43 - soc/arm/st_stm32/stm32g0/CMakeLists.txt | 13 - .../st_stm32/stm32g0/Kconfig.defconfig.series | 15 - soc/arm/st_stm32/stm32g0/Kconfig.series | 18 - soc/arm/st_stm32/stm32g0/Kconfig.soc | 48 - soc/arm/st_stm32/stm32g4/CMakeLists.txt | 11 - .../st_stm32/stm32g4/Kconfig.defconfig.series | 21 - .../stm32g4/Kconfig.defconfig.stm32g431rb | 14 - .../stm32g4/Kconfig.defconfig.stm32g474re | 14 - soc/arm/st_stm32/stm32g4/Kconfig.series | 19 - soc/arm/st_stm32/stm32g4/Kconfig.soc | 34 - soc/arm/st_stm32/stm32g4/soc.c | 47 - soc/arm/st_stm32/stm32h5/CMakeLists.txt | 8 - .../st_stm32/stm32h5/Kconfig.defconfig.series | 16 - soc/arm/st_stm32/stm32h5/Kconfig.series | 20 - soc/arm/st_stm32/stm32h5/Kconfig.soc | 22 - soc/arm/st_stm32/stm32h7/CMakeLists.txt | 11 - .../st_stm32/stm32h7/Kconfig.defconfig.series | 20 - .../stm32h7/Kconfig.defconfig.stm32h745xx | 14 - .../stm32h7/Kconfig.defconfig.stm32h747xx | 14 - .../stm32h7/Kconfig.defconfig.stm32h7a3xx | 15 - .../stm32h7/Kconfig.defconfig.stm32h7b0xx | 15 - .../stm32h7/Kconfig.defconfig.stm32h7b3xx | 15 - soc/arm/st_stm32/stm32h7/Kconfig.series | 18 - soc/arm/st_stm32/stm32h7/Kconfig.soc | 132 -- soc/arm/st_stm32/stm32l0/CMakeLists.txt | 12 - .../st_stm32/stm32l0/Kconfig.defconfig.series | 20 - soc/arm/st_stm32/stm32l0/Kconfig.series | 16 - soc/arm/st_stm32/stm32l0/Kconfig.soc | 55 - soc/arm/st_stm32/stm32l1/CMakeLists.txt | 6 - .../st_stm32/stm32l1/Kconfig.defconfig.series | 18 - .../stm32l1/Kconfig.defconfig.stm32l151x8a | 14 - .../stm32l1/Kconfig.defconfig.stm32l151xb | 14 - .../stm32l1/Kconfig.defconfig.stm32l151xba | 14 - .../stm32l1/Kconfig.defconfig.stm32l151xc | 15 - .../stm32l1/Kconfig.defconfig.stm32l152xc | 16 - soc/arm/st_stm32/stm32l1/Kconfig.series | 16 - soc/arm/st_stm32/stm32l1/Kconfig.soc | 28 - soc/arm/st_stm32/stm32l4/CMakeLists.txt | 14 - .../st_stm32/stm32l4/Kconfig.defconfig.series | 16 - soc/arm/st_stm32/stm32l4/Kconfig.series | 20 - soc/arm/st_stm32/stm32l4/Kconfig.soc | 70 -- soc/arm/st_stm32/stm32l5/CMakeLists.txt | 12 - .../st_stm32/stm32l5/Kconfig.defconfig.series | 13 - soc/arm/st_stm32/stm32l5/Kconfig.series | 20 - soc/arm/st_stm32/stm32l5/Kconfig.soc | 16 - soc/arm/st_stm32/stm32mp1/CMakeLists.txt | 10 - .../stm32mp1/Kconfig.defconfig.series | 13 - .../stm32mp1/Kconfig.defconfig.stm32mp15_m4 | 14 - soc/arm/st_stm32/stm32mp1/Kconfig.series | 17 - soc/arm/st_stm32/stm32mp1/Kconfig.soc | 13 - soc/arm/st_stm32/stm32u5/CMakeLists.txt | 14 - .../st_stm32/stm32u5/Kconfig.defconfig.series | 16 - soc/arm/st_stm32/stm32u5/Kconfig.series | 21 - soc/arm/st_stm32/stm32u5/Kconfig.soc | 30 - soc/arm/st_stm32/stm32wb/CMakeLists.txt | 17 - .../st_stm32/stm32wb/Kconfig.defconfig.series | 16 - soc/arm/st_stm32/stm32wb/Kconfig.series | 19 - soc/arm/st_stm32/stm32wb/Kconfig.soc | 13 - soc/arm/st_stm32/stm32wba/CMakeLists.txt | 22 - .../stm32wba/Kconfig.defconfig.series | 64 - soc/arm/st_stm32/stm32wba/Kconfig.series | 21 - soc/arm/st_stm32/stm32wba/Kconfig.soc | 16 - soc/arm/st_stm32/stm32wl/CMakeLists.txt | 12 - .../st_stm32/stm32wl/Kconfig.defconfig.series | 13 - soc/arm/st_stm32/stm32wl/Kconfig.series | 18 - soc/arm/st_stm32/stm32wl/Kconfig.soc | 22 - soc/arm/ti_k3/CMakeLists.txt | 8 - soc/arm/ti_k3/Kconfig | 19 - soc/arm/ti_k3/Kconfig.defconfig | 8 - soc/arm/ti_k3/Kconfig.soc | 8 - soc/arm/ti_k3/am62x_m4/CMakeLists.txt | 13 - .../ti_k3/am62x_m4/Kconfig.defconfig.am62xm4 | 13 - .../ti_k3/am62x_m4/Kconfig.defconfig.series | 52 - soc/arm/ti_k3/am62x_m4/Kconfig.series | 22 - soc/arm/ti_k3/am62x_m4/Kconfig.soc | 28 - soc/arm/ti_k3/pinctrl_soc.h | 40 - soc/arm/ti_lm3s6965/CMakeLists.txt | 16 - soc/arm/ti_lm3s6965/Kconfig | 10 - soc/arm/ti_lm3s6965/Kconfig.defconfig | 32 - soc/arm/ti_lm3s6965/Kconfig.soc | 7 - soc/arm/ti_simplelink/CMakeLists.txt | 3 - soc/arm/ti_simplelink/Kconfig | 22 - soc/arm/ti_simplelink/Kconfig.defconfig | 3 - soc/arm/ti_simplelink/Kconfig.soc | 5 - .../cc13x2_cc26x2/CMakeLists.txt | 15 - .../cc13x2_cc26x2/Kconfig.defconfig.cc1352r | 9 - .../cc13x2_cc26x2/Kconfig.defconfig.cc2652r | 8 - .../cc13x2_cc26x2/Kconfig.defconfig.series | 47 - .../cc13x2_cc26x2/Kconfig.series | 21 - .../ti_simplelink/cc13x2_cc26x2/Kconfig.soc | 68 -- .../cc13x2x7_cc26x2x7/CMakeLists.txt | 13 - .../Kconfig.defconfig.cc1352r7 | 9 - .../Kconfig.defconfig.cc2652r7 | 8 - .../Kconfig.defconfig.series | 47 - .../cc13x2x7_cc26x2x7/Kconfig.series | 20 - .../cc13x2x7_cc26x2x7/Kconfig.soc | 75 -- soc/arm/ti_simplelink/cc32xx/CMakeLists.txt | 10 - .../cc32xx/Kconfig.defconfig.series | 12 - soc/arm/ti_simplelink/cc32xx/Kconfig.series | 13 - soc/arm/ti_simplelink/cc32xx/Kconfig.soc | 27 - .../ti_simplelink/msp432p4xx/CMakeLists.txt | 6 - .../msp432p4xx/Kconfig.defconfig.series | 13 - .../ti_simplelink/msp432p4xx/Kconfig.series | 16 - soc/arm/ti_simplelink/msp432p4xx/Kconfig.soc | 13 - soc/arm/xilinx_zynq7000/Kconfig | 17 - soc/arm/xilinx_zynq7000/Kconfig.defconfig | 27 - soc/arm/xilinx_zynq7000/Kconfig.soc | 6 - .../xilinx_zynq7000/xc7zxxx/CMakeLists.txt | 8 - .../xc7zxxx/Kconfig.defconfig.series | 17 - .../xc7zxxx/Kconfig.defconfig.xc7z010 | 8 - .../xc7zxxx/Kconfig.defconfig.xc7z015 | 8 - .../xc7zxxx/Kconfig.defconfig.xc7z020 | 8 - .../xc7zxxx/Kconfig.defconfig.xc7z030 | 8 - .../xc7zxxx/Kconfig.defconfig.xc7z035 | 8 - .../xc7zxxx/Kconfig.defconfig.xc7z045 | 8 - .../xc7zxxx/Kconfig.defconfig.xc7z100 | 8 - .../xilinx_zynq7000/xc7zxxx/Kconfig.series | 14 - soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.soc | 60 - .../xilinx_zynq7000/xc7zxxxs/CMakeLists.txt | 8 - .../xc7zxxxs/Kconfig.defconfig.series | 16 - .../xc7zxxxs/Kconfig.defconfig.xc7z007s | 8 - .../xc7zxxxs/Kconfig.defconfig.xc7z012s | 8 - .../xc7zxxxs/Kconfig.defconfig.xc7z014s | 8 - .../xilinx_zynq7000/xc7zxxxs/Kconfig.series | 14 - soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.soc | 32 - soc/arm/xilinx_zynqmp/CMakeLists.txt | 15 - soc/arm/xilinx_zynqmp/Kconfig | 5 - soc/arm/xilinx_zynqmp/Kconfig.defconfig | 31 - soc/arm/xilinx_zynqmp/Kconfig.soc | 12 - soc/arm64/CMakeLists.txt | 7 - soc/arm64/Kconfig | 11 - soc/arm64/arm/CMakeLists.txt | 4 - soc/arm64/arm/Kconfig | 16 - soc/arm64/arm/Kconfig.defconfig | 7 - soc/arm64/arm/Kconfig.soc | 7 - soc/arm64/arm/fvp_aemv8a/CMakeLists.txt | 6 - .../arm/fvp_aemv8a/Kconfig.defconfig.series | 32 - soc/arm64/arm/fvp_aemv8a/Kconfig.series | 9 - soc/arm64/arm/fvp_aemv8a/Kconfig.soc | 12 - soc/arm64/arm/fvp_aemv8r/CMakeLists.txt | 9 - .../arm/fvp_aemv8r/Kconfig.defconfig.series | 34 - soc/arm64/arm/fvp_aemv8r/Kconfig.series | 9 - soc/arm64/arm/fvp_aemv8r/Kconfig.soc | 23 - soc/arm64/bcm2711/Kconfig.defconfig | 17 - soc/arm64/bcm2711/Kconfig.soc | 8 - soc/arm64/bcm_vk/CMakeLists.txt | 3 - soc/arm64/bcm_vk/Kconfig | 16 - soc/arm64/bcm_vk/Kconfig.defconfig | 6 - soc/arm64/bcm_vk/Kconfig.soc | 6 - soc/arm64/bcm_vk/viper/CMakeLists.txt | 11 - .../bcm_vk/viper/Kconfig.defconfig.series | 11 - soc/arm64/bcm_vk/viper/Kconfig.series | 9 - soc/arm64/bcm_vk/viper/Kconfig.soc | 14 - soc/arm64/intel_socfpga/Kconfig | 13 - soc/arm64/intel_socfpga/Kconfig.defconfig | 4 - soc/arm64/intel_socfpga/Kconfig.soc | 4 - .../agilex/Kconfig.defconfig.series | 11 - soc/arm64/intel_socfpga/agilex/Kconfig.series | 10 - soc/arm64/intel_socfpga/agilex/Kconfig.soc | 10 - .../agilex5/Kconfig.defconfig.series | 11 - .../intel_socfpga/agilex5/Kconfig.series | 10 - soc/arm64/intel_socfpga/agilex5/Kconfig.soc | 10 - soc/arm64/nxp_imx/CMakeLists.txt | 7 - soc/arm64/nxp_imx/Kconfig | 16 - soc/arm64/nxp_imx/Kconfig.defconfig | 4 - soc/arm64/nxp_imx/Kconfig.soc | 4 - soc/arm64/nxp_imx/mimx8m/CMakeLists.txt | 7 - .../nxp_imx/mimx8m/Kconfig.defconfig.mimx8mm | 30 - .../nxp_imx/mimx8m/Kconfig.defconfig.mimx8mn | 30 - .../nxp_imx/mimx8m/Kconfig.defconfig.mimx8mp | 30 - .../nxp_imx/mimx8m/Kconfig.defconfig.series | 11 - soc/arm64/nxp_imx/mimx8m/Kconfig.series | 9 - soc/arm64/nxp_imx/mimx8m/Kconfig.soc | 93 -- soc/arm64/nxp_imx/mimx9/CMakeLists.txt | 7 - .../nxp_imx/mimx9/Kconfig.defconfig.mimx93 | 30 - .../nxp_imx/mimx9/Kconfig.defconfig.series | 11 - soc/arm64/nxp_imx/mimx9/Kconfig.series | 9 - soc/arm64/nxp_imx/mimx9/Kconfig.soc | 35 - soc/arm64/nxp_layerscape/Kconfig | 21 - soc/arm64/nxp_layerscape/Kconfig.defconfig | 7 - soc/arm64/nxp_layerscape/Kconfig.soc | 7 - .../ls1046a/Kconfig.defconfig.ls1046a | 22 - .../ls1046a/Kconfig.defconfig.series | 14 - .../nxp_layerscape/ls1046a/Kconfig.series | 12 - soc/arm64/nxp_layerscape/ls1046a/Kconfig.soc | 17 - soc/arm64/qemu_cortex_a53/CMakeLists.txt | 6 - soc/arm64/qemu_cortex_a53/Kconfig.defconfig | 28 - soc/arm64/qemu_cortex_a53/Kconfig.soc | 7 - soc/arm64/qemu_virt_arm64/Kconfig.defconfig | 29 - soc/arm64/qemu_virt_arm64/Kconfig.soc | 8 - soc/arm64/renesas_rcar/CMakeLists.txt | 4 - soc/arm64/renesas_rcar/Kconfig | 17 - soc/arm64/renesas_rcar/Kconfig.defconfig | 4 - soc/arm64/renesas_rcar/Kconfig.soc | 6 - soc/arm64/renesas_rcar/gen3/CMakeLists.txt | 8 - .../gen3/Kconfig.defconfig.r8a77951 | 9 - .../gen3/Kconfig.defconfig.r8a77961 | 9 - .../gen3/Kconfig.defconfig.series | 18 - soc/arm64/renesas_rcar/gen3/Kconfig.series | 12 - soc/arm64/renesas_rcar/gen3/Kconfig.soc | 14 - soc/arm64/renesas_rcar/gen3/pfc_r8a77951.c | 545 --------- soc/arm64/rockchip/CMakeLists.txt | 7 - soc/arm64/rockchip/Kconfig | 22 - soc/arm64/rockchip/Kconfig.defconfig | 7 - soc/arm64/rockchip/Kconfig.soc | 7 - .../rockchip/rk3399/Kconfig.defconfig.series | 14 - soc/arm64/rockchip/rk3399/Kconfig.series | 12 - soc/arm64/rockchip/rk3399/Kconfig.soc | 17 - soc/arm64/rockchip/rk3568/CMakeLists.txt | 3 - .../rockchip/rk3568/Kconfig.defconfig.series | 12 - soc/arm64/rockchip/rk3568/Kconfig.series | 10 - soc/arm64/rockchip/rk3568/Kconfig.soc | 16 - soc/arm64/rockchip/rk3568/linker.ld | 7 - soc/arm64/ti_k3/CMakeLists.txt | 6 - soc/arm64/ti_k3/Kconfig | 17 - soc/arm64/ti_k3/Kconfig.defconfig | 6 - soc/arm64/ti_k3/Kconfig.soc | 6 - soc/arm64/ti_k3/am6x/CMakeLists.txt | 6 - soc/arm64/ti_k3/am6x/Kconfig.defconfig.am6234 | 9 - soc/arm64/ti_k3/am6x/Kconfig.defconfig.series | 42 - soc/arm64/ti_k3/am6x/Kconfig.series | 11 - soc/arm64/ti_k3/am6x/Kconfig.soc | 26 - soc/arm64/xenvm/Kconfig.defconfig | 22 - soc/arm64/xenvm/Kconfig.soc | 8 - soc/{arm => }/aspeed/CMakeLists.txt | 0 soc/aspeed/Kconfig | 12 + soc/aspeed/Kconfig.defconfig | 9 + soc/aspeed/Kconfig.soc | 11 + soc/{arm => }/aspeed/aspeed_util.h | 0 soc/aspeed/ast10x0/CMakeLists.txt | 18 + soc/aspeed/ast10x0/Kconfig | 33 + soc/aspeed/ast10x0/Kconfig.defconfig | 19 + .../aspeed/ast10x0/Kconfig.defconfig.ast1030 | 0 soc/aspeed/ast10x0/Kconfig.soc | 21 + soc/{arm => }/aspeed/ast10x0/linker.ld | 0 soc/{arm => }/aspeed/ast10x0/nocache.ld | 0 soc/{arm => }/aspeed/ast10x0/sboot.ld | 0 soc/{arm => }/aspeed/ast10x0/soc.c | 0 soc/{arm => }/aspeed/ast10x0/soc.h | 0 .../ast10x0/tools/gen_uart_booting_image.py | 0 soc/aspeed/soc.yml | 6 + soc/atmel/sam/CMakeLists.txt | 9 + soc/atmel/sam/Kconfig | 12 + soc/atmel/sam/Kconfig.defconfig | 26 + soc/atmel/sam/Kconfig.soc | 10 + soc/atmel/sam/common/CMakeLists.txt | 14 + soc/atmel/sam/common/Kconfig | 96 ++ .../sam}/common/atmel_sam_dt.h | 0 .../sam}/common/pinctrl_soc.h | 0 .../sam}/common/pwm_fixup.h | 0 .../atmel_sam => atmel/sam}/common/soc_gpio.c | 0 .../atmel_sam => atmel/sam}/common/soc_gpio.h | 0 .../atmel_sam => atmel/sam}/common/soc_pmc.c | 0 .../atmel_sam => atmel/sam}/common/soc_pmc.h | 0 .../sam}/common/soc_power.c | 0 .../sam}/common/soc_poweroff.c | 0 .../sam}/common/soc_sam4l_gpio.c | 0 .../sam}/common/soc_sam4l_pm.c | 0 .../sam}/common/soc_sam4l_poweroff.c | 0 .../atmel_sam => atmel/sam}/common/soc_supc.c | 0 .../atmel_sam => atmel/sam}/common/soc_supc.h | 0 soc/atmel/sam/sam3x/CMakeLists.txt | 10 + soc/atmel/sam/sam3x/Kconfig | 15 + soc/atmel/sam/sam3x/Kconfig.defconfig | 14 + soc/atmel/sam/sam3x/Kconfig.soc | 43 + soc/atmel/sam/sam3x/soc.c | 112 ++ soc/atmel/sam/sam3x/soc.h | 52 + soc/atmel/sam/sam4e/CMakeLists.txt | 10 + soc/atmel/sam/sam4e/Kconfig | 15 + soc/atmel/sam/sam4e/Kconfig.defconfig | 13 + soc/atmel/sam/sam4e/Kconfig.soc | 37 + soc/atmel/sam/sam4e/soc.c | 104 ++ soc/atmel/sam/sam4e/soc.h | 51 + soc/atmel/sam/sam4l/CMakeLists.txt | 10 + soc/atmel/sam/sam4l/Kconfig | 10 + soc/atmel/sam/sam4l/Kconfig.defconfig | 9 + soc/atmel/sam/sam4l/Kconfig.soc | 107 ++ soc/{arm/atmel_sam => atmel/sam}/sam4l/soc.c | 0 soc/atmel/sam/sam4l/soc.h | 223 ++++ soc/atmel/sam/sam4s/CMakeLists.txt | 10 + soc/atmel/sam/sam4s/Kconfig | 14 + soc/atmel/sam/sam4s/Kconfig.defconfig | 13 + soc/atmel/sam/sam4s/Kconfig.soc | 74 ++ soc/atmel/sam/sam4s/soc.c | 111 ++ soc/atmel/sam/sam4s/soc.h | 65 + soc/atmel/sam/same70/CMakeLists.txt | 11 + soc/atmel/sam/same70/Kconfig | 19 + soc/atmel/sam/same70/Kconfig.defconfig | 13 + soc/atmel/sam/same70/Kconfig.soc | 122 ++ soc/atmel/sam/same70/soc.c | 156 +++ soc/atmel/sam/same70/soc.h | 82 ++ soc/atmel/sam/same70/soc_config.c | 65 + soc/atmel/sam/samv71/CMakeLists.txt | 11 + soc/atmel/sam/samv71/Kconfig | 19 + soc/atmel/sam/samv71/Kconfig.defconfig | 13 + soc/atmel/sam/samv71/Kconfig.soc | 122 ++ soc/atmel/sam/samv71/soc.c | 153 +++ soc/atmel/sam/samv71/soc.h | 84 ++ soc/atmel/sam/samv71/soc_config.c | 66 + soc/atmel/sam/soc.yml | 89 ++ soc/atmel/sam0/CMakeLists.txt | 10 + soc/atmel/sam0/Kconfig | 16 + soc/atmel/sam0/Kconfig.defconfig | 30 + soc/atmel/sam0/Kconfig.soc | 21 + .../sam0}/common/CMakeLists.txt | 0 .../sam0}/common/Kconfig.samd2x | 0 .../sam0}/common/Kconfig.samd5x | 7 + .../sam0}/common/Kconfig.saml2x | 4 +- .../sam0}/common/adc_fixup_sam0.h | 0 .../sam0}/common/atmel_sam0_dt.h | 0 .../atmel_sam0 => atmel/sam0}/common/bossa.c | 0 .../sam0}/common/gmac_fixup_samd5x.h | 0 .../sam0}/common/pinctrl_soc.h | 0 .../sam0}/common/sercom_fixup_samd5x.h | 0 .../sam0}/common/soc_port.c | 0 .../sam0}/common/soc_port.h | 0 .../sam0}/common/soc_samc2x.c | 0 .../sam0}/common/soc_samd2x.c | 0 .../sam0}/common/soc_samd5x.c | 0 .../sam0}/common/soc_saml2x.c | 0 .../sam0}/common/soc_samr3x_radio_off.c | 0 .../sam0}/common/tc_fixup_samd5x.h | 0 soc/atmel/sam0/samc20/CMakeLists.txt | 4 + soc/atmel/sam0/samc20/Kconfig | 12 + soc/atmel/sam0/samc20/Kconfig.defconfig | 12 + soc/atmel/sam0/samc20/Kconfig.soc | 98 ++ soc/atmel/sam0/samc20/soc.h | 70 ++ soc/atmel/sam0/samc21/CMakeLists.txt | 4 + soc/atmel/sam0/samc21/Kconfig | 13 + soc/atmel/sam0/samc21/Kconfig.defconfig | 12 + soc/atmel/sam0/samc21/Kconfig.soc | 98 ++ soc/atmel/sam0/samc21/soc.h | 70 ++ soc/atmel/sam0/samd20/CMakeLists.txt | 4 + soc/atmel/sam0/samd20/Kconfig | 12 + soc/atmel/sam0/samd20/Kconfig.defconfig | 12 + soc/atmel/sam0/samd20/Kconfig.soc | 100 ++ soc/atmel/sam0/samd20/soc.h | 122 ++ soc/atmel/sam0/samd21/CMakeLists.txt | 4 + soc/atmel/sam0/samd21/Kconfig | 12 + soc/atmel/sam0/samd21/Kconfig.defconfig | 12 + soc/atmel/sam0/samd21/Kconfig.soc | 90 ++ soc/atmel/sam0/samd21/soc.h | 116 ++ soc/atmel/sam0/samd51/CMakeLists.txt | 4 + soc/atmel/sam0/samd51/Kconfig | 13 + soc/atmel/sam0/samd51/Kconfig.defconfig | 16 + soc/atmel/sam0/samd51/Kconfig.soc | 62 + soc/atmel/sam0/samd51/soc.h | 56 + soc/atmel/sam0/same51/CMakeLists.txt | 4 + soc/atmel/sam0/same51/Kconfig | 13 + soc/atmel/sam0/same51/Kconfig.defconfig | 15 + soc/atmel/sam0/same51/Kconfig.soc | 41 + soc/atmel/sam0/same51/soc.h | 50 + soc/atmel/sam0/same53/CMakeLists.txt | 4 + soc/atmel/sam0/same53/Kconfig | 13 + soc/atmel/sam0/same53/Kconfig.defconfig | 15 + soc/atmel/sam0/same53/Kconfig.soc | 41 + soc/atmel/sam0/same53/soc.h | 49 + soc/atmel/sam0/same54/CMakeLists.txt | 4 + soc/atmel/sam0/same54/Kconfig | 13 + soc/atmel/sam0/same54/Kconfig.defconfig | 15 + soc/atmel/sam0/same54/Kconfig.soc | 36 + soc/atmel/sam0/same54/soc.h | 48 + soc/atmel/sam0/saml21/CMakeLists.txt | 4 + soc/atmel/sam0/saml21/Kconfig | 12 + soc/atmel/sam0/saml21/Kconfig.defconfig | 12 + soc/atmel/sam0/saml21/Kconfig.soc | 76 ++ soc/atmel/sam0/saml21/soc.h | 78 ++ soc/atmel/sam0/samr21/CMakeLists.txt | 4 + soc/atmel/sam0/samr21/Kconfig | 12 + soc/atmel/sam0/samr21/Kconfig.defconfig | 12 + soc/atmel/sam0/samr21/Kconfig.soc | 51 + soc/atmel/sam0/samr21/soc.h | 102 ++ soc/atmel/sam0/samr34/CMakeLists.txt | 4 + soc/atmel/sam0/samr34/Kconfig | 12 + soc/atmel/sam0/samr34/Kconfig.defconfig | 12 + soc/atmel/sam0/samr34/Kconfig.soc | 31 + soc/atmel/sam0/samr34/soc.h | 62 + soc/atmel/sam0/samr35/CMakeLists.txt | 4 + soc/atmel/sam0/samr35/Kconfig | 12 + soc/atmel/sam0/samr35/Kconfig.defconfig | 12 + soc/atmel/sam0/samr35/Kconfig.soc | 31 + soc/atmel/sam0/samr35/soc.h | 62 + soc/atmel/sam0/soc.yml | 138 +++ soc/{arm64 => brcm}/bcm2711/CMakeLists.txt | 0 soc/brcm/bcm2711/Kconfig | 7 + soc/brcm/bcm2711/Kconfig.defconfig | 14 + soc/brcm/bcm2711/Kconfig.soc | 8 + soc/{arm64 => brcm}/bcm2711/mmu_regions.c | 0 soc/brcm/bcm2711/soc.yml | 4 + soc/{arm/arm => brcm/bcmvk}/CMakeLists.txt | 0 soc/brcm/bcmvk/Kconfig | 10 + soc/brcm/bcmvk/Kconfig.defconfig | 10 + soc/brcm/bcmvk/Kconfig.soc | 12 + soc/brcm/bcmvk/soc.yml | 12 + soc/brcm/bcmvk/valkyrie/CMakeLists.txt | 5 + soc/brcm/bcmvk/valkyrie/Kconfig | 10 + soc/brcm/bcmvk/valkyrie/Kconfig.defconfig | 16 + soc/brcm/bcmvk/valkyrie/Kconfig.soc | 22 + soc/{arm/bcm_vk => brcm/bcmvk}/valkyrie/soc.h | 0 soc/brcm/bcmvk/viper/CMakeLists.txt | 19 + soc/brcm/bcmvk/viper/Kconfig | 13 + soc/brcm/bcmvk/viper/Kconfig.defconfig | 8 + .../Kconfig.defconfig.viper_bcm58402_a72 | 3 - .../viper/Kconfig.defconfig.viper_bcm58402_m7 | 3 - soc/brcm/bcmvk/viper/Kconfig.soc | 26 + .../bcmvk/viper/a72}/mmu_regions.c | 0 .../bcmvk/viper/a72}/plat_core.c | 0 .../viper => brcm/bcmvk/viper/a72}/soc.c | 0 .../viper => brcm/bcmvk/viper/a72}/soc.h | 0 .../viper => brcm/bcmvk/viper/m7}/soc.c | 0 .../viper => brcm/bcmvk/viper/m7}/soc.h | 0 soc/{xtensa => cdns}/dc233c/CMakeLists.txt | 0 soc/cdns/dc233c/Kconfig | 14 + soc/cdns/dc233c/Kconfig.defconfig | 25 + soc/cdns/dc233c/Kconfig.soc | 13 + .../dc233c/include/_soc_inthandlers.h | 0 .../dc233c/include/backtrace_helpers.h | 0 .../dc233c/include/xtensa-dc233c.ld | 0 soc/{xtensa => cdns}/dc233c/mmu.c | 0 soc/cdns/dc233c/soc.yml | 4 + .../xtensa_sample_controller}/CMakeLists.txt | 0 soc/cdns/xtensa_sample_controller/Kconfig | 7 + soc/cdns/xtensa_sample_controller/Kconfig.soc | 12 + .../include/_soc_inthandlers.h | 0 .../include/xtensa-sample-controller.ld | 0 soc/cdns/xtensa_sample_controller/soc.yml | 4 + soc/common/CMakeLists.txt | 2 +- soc/common/Kconfig | 8 + soc/common/nordic_nrf/CMakeLists.txt | 4 - .../common/riscv-privileged/CMakeLists.txt | 0 .../common/riscv-privileged/Kconfig | 0 .../common/riscv-privileged/soc_common_irq.c | 0 .../common/riscv-privileged/soc_irq.S | 0 .../common/riscv-privileged/vector.S | 0 soc/cypress/CMakeLists.txt | 8 + soc/cypress/Kconfig | 9 + soc/cypress/Kconfig.defconfig | 8 + soc/cypress/Kconfig.soc | 17 + soc/cypress/psoc6/CMakeLists.txt | 32 + soc/cypress/psoc6/Kconfig | 58 + soc/cypress/psoc6/Kconfig.defconfig | 30 + soc/cypress/psoc6/Kconfig.soc | 1074 +++++++++++++++++ .../psoc6/new/Kconfig.defconfig.psoc6_01 | 15 + .../psoc6/new/Kconfig.defconfig.psoc6_02 | 15 + .../psoc6/new/Kconfig.defconfig.psoc6_04 | 14 + .../psoc6/new}/common/pinctrl_soc.h | 0 .../psoc6 => cypress/psoc6/new}/noinit.ld | 0 .../psoc6/new}/ram_cm0image.ld | 0 .../psoc6 => cypress/psoc6/new}/ram_func.ld | 0 .../psoc6 => cypress/psoc6/new}/rom.ld | 0 .../psoc6/new}/rom_cm0image.ld | 0 .../psoc6 => cypress/psoc6/new}/soc.c | 0 .../psoc6 => cypress/psoc6/new}/soc.h | 0 .../psoc6/old/Kconfig.defconfig.psoc6_m0 | 10 + .../psoc6/old/Kconfig.defconfig.psoc6_m4 | 10 + .../psoc6/old}/common/CMakeLists.txt | 0 .../psoc6/old}/common/cypress_psoc6_dt.h | 0 .../psoc6/old}/common/soc_gpio.c | 0 .../psoc6/old}/common/soc_gpio.h | 0 .../psoc6 => cypress/psoc6/old}/noinit.ld | 0 .../psoc6 => cypress/psoc6/old}/rwdata.ld | 0 .../cypress/psoc6 => cypress/psoc6/old}/soc.c | 0 .../cypress/psoc6 => cypress/psoc6/old}/soc.h | 0 soc/cypress/soc.yml | 131 ++ .../sapphire}/CMakeLists.txt | 0 soc/efinix/sapphire/Kconfig | 14 + soc/efinix/sapphire/Kconfig.defconfig | 20 + soc/efinix/sapphire/Kconfig.soc | 10 + soc/efinix/sapphire/soc.yml | 2 + soc/espressif/CMakeLists.txt | 5 + soc/espressif/Kconfig | 8 + soc/espressif/Kconfig.defconfig | 8 + soc/espressif/Kconfig.soc | 10 + soc/espressif/common/CMakeLists.txt | 6 + soc/espressif/common/Kconfig | 215 ++++ soc/espressif/common/Kconfig.defconfig | 103 ++ .../common/include/_soc_inthandlers.h | 0 .../common/include/gdbstub/soc.h | 0 soc/espressif/esp32/CMakeLists.txt | 120 ++ soc/espressif/esp32/Kconfig | 263 ++++ soc/espressif/esp32/Kconfig.defconfig | 46 + soc/espressif/esp32/Kconfig.soc | 153 +++ soc/espressif/esp32/default.ld | 583 +++++++++ .../esp32/default_appcpu.ld | 0 .../esp32/esp32-mp.c | 0 .../esp32/gdbstub.c | 0 .../esp32/loader.c | 0 .../esp32/mcuboot.ld | 0 .../esp32/newlib_fix.c | 0 .../esp32/pinctrl_soc.h | 0 .../esp32/power.c | 0 .../esp32/poweroff.c | 0 soc/espressif/esp32/soc.c | 266 ++++ .../espressif_esp32 => espressif}/esp32/soc.h | 0 .../esp32/soc_appcpu.c | 0 soc/espressif/esp32c3/CMakeLists.txt | 103 ++ soc/espressif/esp32c3/Kconfig | 97 ++ soc/espressif/esp32c3/Kconfig.defconfig | 18 + soc/espressif/esp32c3/Kconfig.soc | 51 + .../esp32c3/default.ld | 0 .../esp32c3/loader.c | 0 .../esp32c3/mcuboot.ld | 0 .../esp32c3/pinctrl_soc.h | 0 .../esp32c3/power.c | 0 .../esp32c3/poweroff.c | 0 .../esp32c3/soc.c | 0 .../esp32c3/soc.h | 0 .../esp32c3/soc_irq.S | 0 .../esp32c3/soc_irq.c | 0 .../esp32c3/vectors.S | 0 soc/espressif/esp32s2/CMakeLists.txt | 103 ++ soc/espressif/esp32s2/Kconfig | 228 ++++ soc/espressif/esp32s2/Kconfig.defconfig | 24 + .../esp32s2/Kconfig.defconfig.series | 27 + soc/espressif/esp32s2/Kconfig.soc | 126 ++ .../esp32s2/default.ld | 0 .../esp32s2/loader.c | 0 .../esp32s2/mcuboot.ld | 0 .../esp32s2/newlib_fix.c | 0 .../esp32s2/pinctrl_soc.h | 0 .../esp32s2/power.c | 0 .../esp32s2/poweroff.c | 0 .../esp32s2/soc.c | 0 .../esp32s2/soc.h | 0 .../esp32s2/soc_cache.c | 0 soc/espressif/esp32s3/CMakeLists.txt | 118 ++ soc/espressif/esp32s3/Kconfig | 313 +++++ soc/espressif/esp32s3/Kconfig.defconfig | 24 + soc/espressif/esp32s3/Kconfig.soc | 146 +++ soc/espressif/esp32s3/default.ld | 693 +++++++++++ .../esp32s3/default_appcpu.ld | 0 .../esp32s3/esp32s3-mp.c | 0 .../esp32s3/loader.c | 0 .../esp32s3/mcuboot.ld | 0 .../esp32s3/newlib_fix.c | 0 .../esp32s3/pinctrl_soc.h | 0 soc/espressif/esp32s3/soc.c | 322 +++++ .../esp32s3/soc.h | 0 .../esp32s3/soc_appcpu.c | 0 .../esp32s3/soc_cache.c | 0 soc/espressif/soc.yml | 21 + soc/gaisler/Kconfig | 6 + soc/gaisler/Kconfig.soc | 5 + soc/gaisler/gr716a/CMakeLists.txt | 7 + soc/gaisler/gr716a/Kconfig | 9 + soc/gaisler/gr716a/Kconfig.defconfig | 26 + soc/gaisler/gr716a/Kconfig.soc | 10 + soc/{sparc => gaisler}/gr716a/linker.ld | 0 soc/{sparc => gaisler}/gr716a/soc.h | 0 soc/gaisler/gr716a/soc.yml | 2 + soc/gaisler/leon3/CMakeLists.txt | 7 + soc/gaisler/leon3/Kconfig | 8 + soc/gaisler/leon3/Kconfig.defconfig | 9 + soc/gaisler/leon3/Kconfig.soc | 10 + soc/{sparc => gaisler}/leon3/idle.c | 0 soc/{sparc => gaisler}/leon3/linker.ld | 0 soc/{sparc => gaisler}/leon3/soc.h | 0 soc/gaisler/leon3/soc.yml | 2 + soc/{arm/gd_gd32 => gd/gd32}/CMakeLists.txt | 0 soc/gd/gd32/Kconfig | 13 + soc/gd/gd32/Kconfig.defconfig | 17 + soc/gd/gd32/Kconfig.soc | 10 + .../gd_gd32 => gd/gd32}/common/CMakeLists.txt | 0 .../gd/gd32/common/pinctrl_soc.h | 0 .../gd32}/gd32a50x/CMakeLists.txt | 0 soc/gd/gd32/gd32a50x/Kconfig | 12 + .../gd32}/gd32a50x/Kconfig.defconfig.gd32a503 | 5 +- soc/gd/gd32/gd32a50x/Kconfig.defconfig.series | 11 + soc/gd/gd32/gd32a50x/Kconfig.soc | 18 + .../gd_gd32 => gd/gd32}/gd32a50x/gd32_regs.h | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32a50x/soc.c | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32a50x/soc.h | 0 .../gd32}/gd32e10x/CMakeLists.txt | 0 soc/gd/gd32/gd32e10x/Kconfig | 11 + .../gd32}/gd32e10x/Kconfig.defconfig.gd32e103 | 5 +- soc/gd/gd32/gd32e10x/Kconfig.defconfig.series | 11 + soc/gd/gd32/gd32e10x/Kconfig.soc | 18 + .../gd_gd32 => gd/gd32}/gd32e10x/gd32_regs.h | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32e10x/soc.c | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32e10x/soc.h | 0 .../gd32}/gd32e50x/CMakeLists.txt | 0 soc/gd/gd32/gd32e50x/Kconfig | 11 + .../gd32}/gd32e50x/Kconfig.defconfig.gd32e507 | 3 - soc/gd/gd32/gd32e50x/Kconfig.defconfig.series | 11 + soc/gd/gd32/gd32e50x/Kconfig.soc | 18 + .../gd_gd32 => gd/gd32}/gd32e50x/gd32_regs.h | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32e50x/soc.c | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32e50x/soc.h | 0 .../gd32}/gd32f3x0/CMakeLists.txt | 0 soc/gd/gd32/gd32f3x0/Kconfig | 9 + .../gd32}/gd32f3x0/Kconfig.defconfig.gd32f350 | 5 +- soc/gd/gd32/gd32f3x0/Kconfig.defconfig.series | 11 + soc/gd/gd32/gd32f3x0/Kconfig.soc | 18 + .../gd_gd32 => gd/gd32}/gd32f3x0/gd32_regs.h | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32f3x0/soc.c | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32f3x0/soc.h | 0 .../gd32}/gd32f403/CMakeLists.txt | 0 soc/gd/gd32/gd32f403/Kconfig | 12 + .../gd32}/gd32f403/Kconfig.defconfig.gd32f403 | 5 +- soc/gd/gd32/gd32f403/Kconfig.defconfig.series | 8 + soc/gd/gd32/gd32f403/Kconfig.soc | 18 + .../gd_gd32 => gd/gd32}/gd32f403/gd32_regs.h | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32f403/soc.c | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32f403/soc.h | 0 .../gd32}/gd32f4xx/CMakeLists.txt | 0 soc/gd/gd32/gd32f4xx/Kconfig | 10 + .../gd32}/gd32f4xx/Kconfig.defconfig.gd32f405 | 3 - .../gd32}/gd32f4xx/Kconfig.defconfig.gd32f407 | 3 - .../gd32}/gd32f4xx/Kconfig.defconfig.gd32f450 | 3 - .../gd32}/gd32f4xx/Kconfig.defconfig.gd32f470 | 3 - soc/gd/gd32/gd32f4xx/Kconfig.defconfig.series | 11 + soc/gd/gd32/gd32f4xx/Kconfig.soc | 34 + .../gd_gd32 => gd/gd32}/gd32f4xx/gd32_regs.h | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32f4xx/soc.c | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32f4xx/soc.h | 0 .../gd32}/gd32l23x/CMakeLists.txt | 0 soc/gd/gd32/gd32l23x/Kconfig | 10 + .../gd32}/gd32l23x/Kconfig.defconfig.gd32l233 | 5 +- soc/gd/gd32/gd32l23x/Kconfig.defconfig.series | 11 + soc/gd/gd32/gd32l23x/Kconfig.soc | 18 + .../gd_gd32 => gd/gd32}/gd32l23x/gd32_regs.h | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32l23x/soc.c | 0 soc/{arm/gd_gd32 => gd/gd32}/gd32l23x/soc.h | 0 soc/gd/gd32/gd32vf103/CMakeLists.txt | 11 + soc/gd/gd32/gd32vf103/Kconfig | 20 + .../gd32vf103/Kconfig.defconfig.gd32vf103 | 12 - .../gd32/gd32vf103/Kconfig.defconfig.series | 8 + soc/gd/gd32/gd32vf103/Kconfig.soc | 20 + .../gd_gd32 => gd/gd32}/gd32vf103/entry.S | 0 .../gd_gd32 => gd/gd32}/gd32vf103/gd32_regs.h | 0 .../gd_gd32 => gd/gd32}/gd32vf103/init.ld | 0 .../gd32}/gd32vf103/nuclei_csr.h | 0 .../gd_gd32 => gd/gd32}/gd32vf103/soc.c | 0 soc/gd/gd32/soc.yml | 30 + .../xmc}/CMakeLists.txt | 0 soc/infineon/xmc/Kconfig | 14 + soc/infineon/xmc/Kconfig.defconfig | 13 + soc/infineon/xmc/Kconfig.soc | 12 + soc/infineon/xmc/soc.yml | 7 + soc/infineon/xmc/xmc4xxx/CMakeLists.txt | 10 + soc/infineon/xmc/xmc4xxx/Kconfig | 24 + soc/infineon/xmc/xmc4xxx/Kconfig.defconfig | 14 + .../xmc/xmc4xxx}/Kconfig.defconfig.xmc4500 | 3 - .../xmc/xmc4xxx}/Kconfig.defconfig.xmc4700 | 3 - soc/infineon/xmc/xmc4xxx/Kconfig.soc | 40 + .../4xxx => infineon/xmc/xmc4xxx}/noinit.ld | 0 .../xmc/xmc4xxx}/pinctrl_soc.h | 0 .../4xxx => infineon/xmc/xmc4xxx}/soc.c | 0 .../4xxx => infineon/xmc/xmc4xxx}/soc.h | 0 soc/intel/alder_lake/CMakeLists.txt | 12 + soc/intel/alder_lake/Kconfig | 11 + soc/intel/alder_lake/Kconfig.defconfig | 16 + soc/intel/alder_lake/Kconfig.soc | 8 + soc/{x86 => intel}/alder_lake/cpu.c | 0 .../alder_lake/doc/supported_features.txt | 0 soc/{x86 => intel}/alder_lake/linker.ld | 0 soc/{x86 => intel}/alder_lake/soc.h | 0 soc/intel/alder_lake/soc.yml | 4 + soc/{x86 => intel}/alder_lake/soc_gpio.h | 0 soc/intel/apollo_lake/CMakeLists.txt | 12 + soc/intel/apollo_lake/Kconfig | 12 + soc/intel/apollo_lake/Kconfig.defconfig | 26 + soc/intel/apollo_lake/Kconfig.soc | 8 + soc/{x86 => intel}/apollo_lake/cpu.c | 0 .../apollo_lake/doc/supported_features.txt | 0 soc/{x86 => intel}/apollo_lake/linker.ld | 0 soc/{x86 => intel}/apollo_lake/soc.h | 0 soc/intel/apollo_lake/soc.yml | 4 + soc/{x86 => intel}/apollo_lake/soc_gpio.h | 0 soc/intel/atom/CMakeLists.txt | 6 + soc/intel/atom/Kconfig | 8 + soc/intel/atom/Kconfig.defconfig | 11 + soc/intel/atom/Kconfig.soc | 9 + soc/{x86/ia32 => intel/atom}/linker.ld | 0 soc/intel/atom/soc.yml | 4 + soc/intel/elkhart_lake/CMakeLists.txt | 12 + soc/intel/elkhart_lake/Kconfig | 11 + soc/intel/elkhart_lake/Kconfig.defconfig | 16 + soc/intel/elkhart_lake/Kconfig.soc | 8 + soc/{x86 => intel}/elkhart_lake/cpu.c | 0 .../elkhart_lake/doc/supported_features.txt | 0 soc/{x86 => intel}/elkhart_lake/linker.ld | 0 soc/{x86 => intel}/elkhart_lake/soc.h | 0 soc/intel/elkhart_lake/soc.yml | 4 + soc/{x86 => intel}/elkhart_lake/soc_gpio.h | 0 soc/intel/intel_adsp/CMakeLists.txt | 17 + soc/intel/intel_adsp/Kconfig | 132 ++ soc/intel/intel_adsp/Kconfig.defconfig | 51 + soc/intel/intel_adsp/Kconfig.soc | 12 + soc/intel/intel_adsp/ace/CMakeLists.txt | 22 + soc/intel/intel_adsp/ace/Kconfig | 21 + .../ace/Kconfig.defconfig.ace15_mtpm | 9 + .../ace/Kconfig.defconfig.ace20_lnl | 9 + .../intel_adsp/ace/Kconfig.defconfig.series | 65 + soc/intel/intel_adsp/ace/Kconfig.soc | 31 + .../intel_adsp/ace/_soc_inthandlers.h | 0 .../intel_adsp/ace/ace-link.ld | 0 .../intel_adsp/ace/asm_memory_management.h | 0 soc/{xtensa => intel}/intel_adsp/ace/boot.c | 0 .../intel_adsp/ace/comm_widget.c | 0 .../intel_adsp/ace/comm_widget.h | 0 .../intel_adsp/ace/comm_widget_messages.c | 0 .../intel_adsp/ace/include/adsp_imr_layout.h | 0 .../intel_adsp/ace/include/adsp_timestamp.h | 0 .../intel_adsp/ace/include/dmic_regs.h | 0 .../ace/include/intel_ace15_mtpm/adsp_boot.h | 0 .../intel_ace15_mtpm/adsp_comm_widget.h | 0 .../include/intel_ace15_mtpm/adsp_interrupt.h | 0 .../include/intel_ace15_mtpm/adsp_ipc_regs.h | 0 .../include/intel_ace15_mtpm/adsp_memory.h | 0 .../intel_ace15_mtpm/adsp_memory_regions.h | 0 .../ace/include/intel_ace15_mtpm/adsp_power.h | 0 .../ace/include/intel_ace15_mtpm/adsp_shim.h | 0 .../include/intel_ace15_mtpm/adsp_watchdog.h | 0 .../intel_ace15_mtpm/dmic_regs_ace1x.h | 0 .../ace/include/intel_ace20_lnl/adsp_boot.h | 0 .../include/intel_ace20_lnl/adsp_interrupt.h | 0 .../include/intel_ace20_lnl/adsp_ipc_regs.h | 0 .../ace/include/intel_ace20_lnl/adsp_memory.h | 0 .../intel_ace20_lnl/adsp_memory_regions.h | 0 .../ace/include/intel_ace20_lnl/adsp_power.h | 0 .../ace/include/intel_ace20_lnl/adsp_shim.h | 0 .../include/intel_ace20_lnl/dmic_regs_ace2x.h | 0 soc/{xtensa => intel}/intel_adsp/ace/irq.c | 0 .../intel_adsp/ace/linker.ld | 0 .../intel_adsp/ace/multiprocessing.c | 0 .../intel_adsp/ace/pmc_interface.h | 0 soc/{xtensa => intel}/intel_adsp/ace/power.c | 0 .../intel_adsp/ace/power_down.S | 0 soc/{xtensa => intel}/intel_adsp/ace/sram.c | 0 .../intel_adsp/ace/timestamp.c | 0 soc/intel/intel_adsp/cavs/CMakeLists.txt | 22 + soc/intel/intel_adsp/cavs/Kconfig | 17 + .../cavs/Kconfig.defconfig.cavs_v25 | 9 +- .../intel_adsp/cavs/Kconfig.defconfig.series | 47 + soc/intel/intel_adsp/cavs/Kconfig.soc | 24 + .../intel_adsp/cavs}/_soc_inthandlers.h | 0 .../intel_adsp/cavs/asm_ldo_management.h | 0 .../intel_adsp/cavs/asm_memory_management.h | 0 .../intel_adsp/cavs/include/adsp_interrupt.h | 0 .../include/intel_tgl_adsp/adsp_imr_layout.h | 0 .../include/intel_tgl_adsp/adsp_ipc_regs.h | 0 .../cavs/include/intel_tgl_adsp/adsp_memory.h | 0 .../cavs/include/intel_tgl_adsp/adsp_shim.h | 0 .../cavs/include/intel_tgl_adsp/dmic_regs.h | 0 .../cavs/include/xtensa-cavs-linker.ld | 0 soc/{xtensa => intel}/intel_adsp/cavs/irq.c | 0 .../intel_adsp/cavs/multiprocessing.c | 0 soc/{xtensa => intel}/intel_adsp/cavs/power.c | 0 .../intel_adsp/cavs/power_down_cavs.S | 0 soc/{xtensa => intel}/intel_adsp/cavs/sram.c | 0 soc/intel/intel_adsp/common/CMakeLists.txt | 149 +++ .../intel_adsp/common/boot.c | 2 +- .../intel_adsp/common/boot_complete.c | 0 soc/{xtensa => intel}/intel_adsp/common/clk.c | 6 +- .../intel_adsp/common/include/adsp-vectors.h | 4 +- .../intel_adsp/common/include/adsp_clk.h | 2 +- .../common/include/adsp_debug_window.h | 0 .../intel_adsp/common/include/cavs-idc.h | 0 .../intel_adsp/common/include/cavstool.h | 0 .../intel_adsp/common/include/cpu_init.h | 0 .../intel_adsp/common/include/debug_helpers.h | 0 .../common/include/intel_adsp_hda.h | 4 +- .../common/include/intel_adsp_ipc.h | 0 .../common/include/intel_adsp_ipc_devtree.h | 0 .../intel_adsp/common/include/manifest.h | 0 .../intel_adsp/common/include/mem_window.h | 0 .../intel_adsp/common/include/soc.h | 0 .../intel_adsp/common/include/soc_util.h | 0 soc/{xtensa => intel}/intel_adsp/common/ipc.c | 8 +- .../intel_adsp/common/mem_window.c | 0 .../intel_adsp/common/multiprocessing.c | 0 .../intel_adsp/common/rimage_modules.c | 0 soc/{xtensa => intel}/intel_adsp/common/soc.c | 0 soc/intel/intel_adsp/soc.yml | 10 + .../intel_adsp/tools/acetool.py | 2 + .../intel_adsp/tools/cavstool.py | 2 + .../intel_adsp/tools/cavstool_client.py | 0 .../intel_adsp/tools/cavstwist.sh | 10 +- .../intel_adsp/tools/remote-fw-service.py | 2 + soc/{x86 => intel}/intel_ish/CMakeLists.txt | 0 soc/intel/intel_ish/Kconfig | 15 + soc/intel/intel_ish/Kconfig.defconfig | 26 + soc/intel/intel_ish/Kconfig.soc | 13 + .../intel_ish/doc/supported_features.txt | 0 soc/intel/intel_ish/intel_ish5/CMakeLists.txt | 15 + .../intel_ish5/Kconfig.defconfig.series | 10 + soc/intel/intel_ish/intel_ish5/Kconfig.soc | 27 + .../intel_ish/intel_ish5/linker.ld | 0 .../intel_ish/intel_ish5/pm/CMakeLists.txt | 0 .../intel_ish/intel_ish5/pm/Kconfig.pm | 0 .../intel_ish/intel_ish5/pm/power.c | 0 soc/{x86 => intel}/intel_ish/intel_ish5/soc.c | 0 soc/{x86 => intel}/intel_ish/intel_ish5/soc.h | 0 soc/intel/intel_ish/soc.yml | 8 + .../intel_ish/utils/build_ish_firmware.cmake | 0 .../intel_ish/utils/build_ish_firmware.py | 0 soc/intel/intel_niosv/CMakeLists.txt | 6 + soc/intel/intel_niosv/Kconfig | 10 + soc/intel/intel_niosv/Kconfig.defconfig | 10 + soc/intel/intel_niosv/Kconfig.soc | 12 + .../intel_niosv/niosv/CMakeLists.txt | 0 soc/intel/intel_niosv/niosv/Kconfig | 22 + .../niosv/Kconfig.defconfig.series | 19 + soc/intel/intel_niosv/niosv/Kconfig.soc | 28 + .../intel_niosv/niosv/linker.ld | 0 soc/intel/intel_niosv/soc.yml | 7 + .../intel_socfpga/CMakeLists.txt | 0 soc/intel/intel_socfpga/Kconfig | 8 + soc/intel/intel_socfpga/Kconfig.defconfig | 8 + soc/intel/intel_socfpga/Kconfig.soc | 10 + .../intel_socfpga/agilex/CMakeLists.txt | 0 soc/intel/intel_socfpga/agilex/Kconfig | 6 + .../agilex/Kconfig.defconfig.agilex | 5 +- .../agilex/Kconfig.defconfig.series | 8 + soc/intel/intel_socfpga/agilex/Kconfig.soc | 20 + .../intel_socfpga/agilex/mmu_regions.c | 0 .../intel_socfpga/agilex5/CMakeLists.txt | 0 soc/intel/intel_socfpga/agilex5/Kconfig | 6 + .../agilex5/Kconfig.defconfig.agilex5 | 5 +- .../agilex5/Kconfig.defconfig.series | 8 + soc/intel/intel_socfpga/agilex5/Kconfig.soc | 20 + .../intel_socfpga/agilex5/mmu_regions.c | 0 .../intel_socfpga/common/CMakeLists.txt | 0 .../intel_socfpga/common/socfpga_handoff.h | 0 .../common/socfpga_system_manager.h | 0 soc/intel/intel_socfpga/soc.yml | 9 + soc/intel/intel_socfpga_std/CMakeLists.txt | 4 + soc/intel/intel_socfpga_std/Kconfig | 8 + soc/intel/intel_socfpga_std/Kconfig.defconfig | 8 + soc/intel/intel_socfpga_std/Kconfig.soc | 10 + .../intel_socfpga_std/cyclonev/CMakeLists.txt | 7 + soc/intel/intel_socfpga_std/cyclonev/Kconfig | 8 + .../cyclonev/Kconfig.defconfig.cyclonev | 14 + .../cyclonev/Kconfig.defconfig.series | 8 + .../intel_socfpga_std/cyclonev/Kconfig.soc | 20 + .../intel_socfpga_std/cyclonev/soc.c | 0 .../intel_socfpga_std/cyclonev/soc.h | 0 soc/intel/intel_socfpga_std/soc.yml | 6 + soc/intel/lakemont/CMakeLists.txt | 9 + soc/intel/lakemont/Kconfig | 13 + soc/intel/lakemont/Kconfig.defconfig | 20 + soc/intel/lakemont/Kconfig.soc | 8 + soc/{x86/atom => intel/lakemont}/linker.ld | 0 soc/{x86 => intel}/lakemont/soc.h | 0 soc/intel/lakemont/soc.yml | 4 + soc/intel/raptor_lake/CMakeLists.txt | 7 + soc/intel/raptor_lake/Kconfig | 11 + soc/intel/raptor_lake/Kconfig.defconfig | 15 + soc/intel/raptor_lake/Kconfig.soc | 8 + .../raptor_lake/doc/supported_features.txt | 0 soc/{x86 => intel}/raptor_lake/linker.ld | 0 soc/{x86 => intel}/raptor_lake/soc.h | 0 soc/intel/raptor_lake/soc.yml | 4 + soc/{x86 => intel}/raptor_lake/soc_gpio.h | 0 soc/{riscv/ite_ec => ite/ec}/CMakeLists.txt | 0 soc/ite/ec/Kconfig | 8 + soc/ite/ec/Kconfig.defconfig | 8 + soc/ite/ec/Kconfig.soc | 10 + .../ite_ec => ite/ec}/common/CMakeLists.txt | 0 .../ite_ec => ite/ec}/common/check_regs.c | 0 .../ite_ec => ite/ec}/common/chip_chipregs.h | 0 .../ite_ec => ite/ec}/common/pinctrl_soc.h | 0 soc/{riscv/ite_ec => ite/ec}/common/policy.c | 0 soc/{riscv/ite_ec => ite/ec}/common/power.c | 0 .../ite_ec => ite/ec}/common/soc_common.h | 0 .../ite_ec => ite/ec}/common/soc_common_irq.c | 0 soc/{riscv/ite_ec => ite/ec}/common/soc_dt.h | 0 .../ite_ec => ite/ec}/common/soc_espi.h | 0 soc/{riscv/ite_ec => ite/ec}/common/soc_irq.S | 0 soc/{riscv/ite_ec => ite/ec}/common/vector.S | 0 soc/ite/ec/it8xxx2/CMakeLists.txt | 9 + soc/ite/ec/it8xxx2/Kconfig | 154 +++ .../ec}/it8xxx2/Kconfig.defconfig.it81202bx | 3 - .../ec}/it8xxx2/Kconfig.defconfig.it81202cx | 3 - .../ec}/it8xxx2/Kconfig.defconfig.it81302bx | 3 - .../ec}/it8xxx2/Kconfig.defconfig.it81302cx | 3 - .../ec}/it8xxx2/Kconfig.defconfig.it82002aw | 3 - .../ec}/it8xxx2/Kconfig.defconfig.it82202ax | 3 - soc/ite/ec/it8xxx2/Kconfig.defconfig.series | 56 + soc/ite/ec/it8xxx2/Kconfig.soc | 52 + .../ite_ec => ite/ec}/it8xxx2/__arithmetic.S | 0 soc/{riscv/ite_ec => ite/ec}/it8xxx2/ilm.c | 0 soc/{riscv/ite_ec => ite/ec}/it8xxx2/ilm.h | 0 .../ite_ec => ite/ec}/it8xxx2/linker.ld | 0 soc/{riscv/ite_ec => ite/ec}/it8xxx2/soc.c | 0 soc/{riscv/ite_ec => ite/ec}/it8xxx2/soc.h | 0 soc/ite/ec/soc.yml | 12 + soc/litex/litex_vexriscv/CMakeLists.txt | 14 + soc/litex/litex_vexriscv/Kconfig | 20 + soc/litex/litex_vexriscv/Kconfig.defconfig | 12 + soc/litex/litex_vexriscv/Kconfig.soc | 10 + soc/{riscv => litex}/litex_vexriscv/soc.h | 0 soc/litex/litex_vexriscv/soc.yml | 2 + .../opentitan/CMakeLists.txt | 0 soc/lowrisc/opentitan/Kconfig | 21 + soc/lowrisc/opentitan/Kconfig.defconfig | 24 + soc/lowrisc/opentitan/Kconfig.soc | 8 + soc/{riscv => lowrisc}/opentitan/rom_header.S | 0 .../opentitan/rom_header.ld | 0 soc/{riscv => lowrisc}/opentitan/soc.c | 0 soc/lowrisc/opentitan/soc.yml | 2 + .../mec}/CMakeLists.txt | 0 soc/microchip/mec/Kconfig | 226 ++++ soc/microchip/mec/Kconfig.defconfig | 8 + soc/microchip/mec/Kconfig.soc | 12 + soc/microchip/mec/common/CMakeLists.txt | 27 + .../mec}/common/pinctrl_soc.h | 0 .../mec}/common/reg/mec_acpi_ec.h | 0 .../mec}/common/reg/mec_adc.h | 0 .../mec}/common/reg/mec_global_cfg.h | 0 .../mec}/common/reg/mec_gpio.h | 0 .../mec}/common/reg/mec_kbc.h | 0 .../mec}/common/reg/mec_keyscan.h | 0 .../mec}/common/reg/mec_peci.h | 0 .../mec}/common/reg/mec_ps2.h | 0 .../mec}/common/reg/mec_pwm.h | 0 .../mec}/common/reg/mec_tach.h | 0 .../mec}/common/reg/mec_tfdp.h | 0 .../mec}/common/reg/mec_timers.h | 0 .../mec}/common/reg/mec_uart.h | 0 .../mec}/common/reg/mec_vci.h | 0 .../mec}/common/reg/mec_wdt.h | 0 .../mec}/common/soc_dt.h | 0 .../mec}/common/soc_espi_channels.h | 0 .../mec}/common/soc_gpio.h | 0 .../mec}/common/soc_i2c.c | 2 +- .../mec}/common/soc_i2c.h | 0 .../mec}/common/soc_pcr.h | 0 .../mec}/common/soc_pins.h | 0 .../mec}/common/spigen/mec_spi_gen.py | 8 +- soc/microchip/mec/mec15xx/CMakeLists.txt | 24 + soc/microchip/mec/mec15xx/Kconfig | 101 ++ .../mec/mec15xx}/Kconfig.defconfig.mec1501hsz | 3 - .../mec/mec15xx/Kconfig.defconfig.series | 29 + soc/microchip/mec/mec15xx/Kconfig.soc | 20 + .../mec/mec15xx}/device_power.c | 0 .../mec/mec15xx}/device_power.h | 0 .../mec1501 => microchip/mec/mec15xx}/power.c | 0 .../mec1501 => microchip/mec/mec15xx}/soc.c | 0 .../mec1501 => microchip/mec/mec15xx}/soc.h | 0 .../mec/mec15xx}/soc_espi_saf_v1.h | 0 .../mec/mec15xx}/timing.c | 0 soc/microchip/mec/mec172x/CMakeLists.txt | 24 + soc/microchip/mec/mec172x/Kconfig | 76 ++ .../mec}/mec172x/Kconfig.defconfig.mec172xnlj | 3 - .../mec}/mec172x/Kconfig.defconfig.mec172xnsz | 3 - .../mec/mec172x/Kconfig.defconfig.series | 33 + soc/microchip/mec/mec172x/Kconfig.soc | 25 + .../mec}/mec172x/device_power.c | 0 .../mec}/mec172x/device_power.h | 0 .../mec}/mec172x/power.c | 0 .../mec}/mec172x/reg/gpio_pkg_lj.h | 0 .../mec}/mec172x/reg/gpio_pkg_sz.h | 0 .../mec}/mec172x/reg/mec172x_defs.h | 0 .../mec}/mec172x/reg/mec172x_ecia.h | 0 .../mec}/mec172x/reg/mec172x_ecs.h | 0 .../mec}/mec172x/reg/mec172x_emi.h | 0 .../mec}/mec172x/reg/mec172x_espi_iom.h | 0 .../mec}/mec172x/reg/mec172x_espi_saf.h | 0 .../mec}/mec172x/reg/mec172x_espi_vw.h | 0 .../mec}/mec172x/reg/mec172x_gpio.h | 0 .../mec}/mec172x/reg/mec172x_i2c_smb.h | 0 .../mec}/mec172x/reg/mec172x_p80bd.h | 0 .../mec}/mec172x/reg/mec172x_pcr.h | 0 .../mec}/mec172x/reg/mec172x_qspi.h | 0 .../mec}/mec172x/reg/mec172x_vbat.h | 0 .../mec}/mec172x/soc.c | 0 .../mec}/mec172x/soc.h | 0 .../mec}/mec172x/soc_espi_saf_v2.h | 0 .../mec}/mec172x/soc_power_debug.h | 0 .../mec}/mec172x/timing.c | 0 soc/microchip/mec/soc.yml | 10 + .../gd_gd32 => microchip/miv}/CMakeLists.txt | 0 soc/microchip/miv/Kconfig | 8 + soc/microchip/miv/Kconfig.defconfig | 8 + soc/microchip/miv/Kconfig.soc | 10 + soc/microchip/miv/miv/CMakeLists.txt | 6 + soc/microchip/miv/miv/Kconfig | 18 + soc/microchip/miv/miv/Kconfig.defconfig | 27 + soc/microchip/miv/miv/Kconfig.soc | 22 + .../miv/polarfire}/CMakeLists.txt | 0 soc/microchip/miv/polarfire/Kconfig | 28 + soc/microchip/miv/polarfire/Kconfig.defconfig | 29 + soc/microchip/miv/polarfire/Kconfig.soc | 22 + soc/microchip/miv/soc.yml | 9 + soc/mips/CMakeLists.txt | 5 - soc/mips/qemu_malta/CMakeLists.txt | 19 - soc/mips/qemu_malta/Kconfig.defconfig | 16 - soc/mips/qemu_malta/Kconfig.soc | 7 - soc/native/inf_clock/CMakeLists.txt | 18 + soc/native/inf_clock/Kconfig | 57 + soc/native/inf_clock/Kconfig.soc | 17 + .../inf_clock/native_tasks.c | 0 .../inf_clock/posix_board_if.h | 0 .../inf_clock/posix_native_task.h | 0 soc/{posix => native}/inf_clock/posix_soc.h | 0 soc/{posix => native}/inf_clock/soc.c | 0 soc/{posix => native}/inf_clock/soc.h | 0 soc/native/inf_clock/soc.yml | 4 + soc/{posix => native}/inf_clock/soc_irq.h | 0 soc/{riscv => }/neorv32/CMakeLists.txt | 0 soc/neorv32/Kconfig | 35 + soc/neorv32/Kconfig.defconfig | 26 + soc/neorv32/Kconfig.soc | 22 + soc/{riscv => }/neorv32/linker.ld | 0 soc/{riscv => }/neorv32/reset.S | 0 soc/{riscv => }/neorv32/soc.c | 0 soc/{riscv => }/neorv32/soc.h | 0 soc/neorv32/soc.yml | 2 + soc/{riscv => }/neorv32/soc_irq.S | 0 soc/nios2/nios2-qemu/CMakeLists.txt | 4 - soc/nios2/nios2-qemu/Kconfig.defconfig | 11 - soc/nios2/nios2-qemu/Kconfig.soc | 8 - soc/nios2/nios2f-zephyr/CMakeLists.txt | 5 - soc/nios2/nios2f-zephyr/Kconfig.defconfig | 26 - soc/nios2/nios2f-zephyr/Kconfig.soc | 7 - soc/nordic/CMakeLists.txt | 38 + soc/nordic/Kconfig | 174 +++ soc/nordic/Kconfig.defconfig | 45 + soc/nordic/Kconfig.soc | 59 + soc/nordic/common/CMakeLists.txt | 19 + soc/nordic/common/Kconfig | 4 + soc/nordic/common/Kconfig.defconfig | 8 + .../common}/Kconfig.peripherals | 0 .../common}/pinctrl_soc.h | 0 .../nordic_nrf => nordic}/common/poweroff.c | 0 .../common/soc_nrf_common.S | 0 .../common/soc_nrf_common.h | 0 .../nordic_nrf => nordic}/common/soc_secure.c | 0 .../nordic_nrf => nordic}/common/soc_secure.h | 0 soc/nordic/common/vpr/CMakeLists.txt | 8 + .../nordic_nrf => nordic}/common/vpr/Kconfig | 0 .../common/vpr/Kconfig.defconfig | 0 .../common/vpr/soc_context.h | 0 .../common/vpr/soc_irq.S | 0 .../common/vpr/soc_irq.c | 0 .../common/vpr/soc_isr_stacking.h | 0 .../common/vpr/soc_offsets.h | 0 .../nordic_nrf => nordic}/common/vpr/vector.S | 0 soc/nordic/nrf51/CMakeLists.txt | 4 + soc/nordic/nrf51/Kconfig | 13 + soc/nordic/nrf51/Kconfig.defconfig | 16 + soc/nordic/nrf51/Kconfig.soc | 24 + soc/{arm/nordic_nrf => nordic}/nrf51/soc.c | 0 soc/{arm/nordic_nrf => nordic}/nrf51/soc.h | 0 soc/nordic/nrf52/CMakeLists.txt | 16 + soc/nordic/nrf52/Kconfig | 106 ++ soc/nordic/nrf52/Kconfig.defconfig | 14 + .../nrf52/Kconfig.defconfig.nrf52805_CAAA | 3 - .../nrf52/Kconfig.defconfig.nrf52810_QFAA | 3 - .../nrf52/Kconfig.defconfig.nrf52811_QFAA | 3 - .../nrf52/Kconfig.defconfig.nrf52820_QDAA | 4 - .../nrf52/Kconfig.defconfig.nrf52832_CIAA | 3 - .../nrf52/Kconfig.defconfig.nrf52832_QFAA | 3 - .../nrf52/Kconfig.defconfig.nrf52832_QFAB | 3 - .../nrf52/Kconfig.defconfig.nrf52833_QDAA | 4 - .../nrf52/Kconfig.defconfig.nrf52833_QIAA | 4 - .../nrf52/Kconfig.defconfig.nrf52840_QFAA | 3 - .../nrf52/Kconfig.defconfig.nrf52840_QIAA | 3 - soc/nordic/nrf52/Kconfig.soc | 90 ++ soc/{arm/nordic_nrf => nordic}/nrf52/soc.c | 0 soc/{arm/nordic_nrf => nordic}/nrf52/soc.h | 0 soc/nordic/nrf53/CMakeLists.txt | 18 + soc/nordic/nrf53/Kconfig | 227 ++++ soc/nordic/nrf53/Kconfig.defconfig | 14 + .../Kconfig.defconfig.nrf5340_CPUAPP_QKAA | 3 - .../Kconfig.defconfig.nrf5340_CPUNET_QKAA | 3 - soc/nordic/nrf53/Kconfig.soc | 29 + .../nrf53/Kconfig.sync_rtc | 0 .../nrf53/Kconfig.sync_rtc_ipm | 0 soc/{arm/nordic_nrf => nordic}/nrf53/soc.c | 0 soc/{arm/nordic_nrf => nordic}/nrf53/soc.h | 0 .../nrf53/soc_cpu_idle.h | 0 .../nordic_nrf => nordic}/nrf53/sync_rtc.c | 0 soc/nordic/nrf54h/CMakeLists.txt | 11 + soc/nordic/nrf54h/Kconfig | 41 + soc/nordic/nrf54h/Kconfig.defconfig | 36 + .../Kconfig.defconfig.nrf54h20_enga_cpuapp | 14 + .../Kconfig.defconfig.nrf54h20_enga_cpuppr | 3 - .../Kconfig.defconfig.nrf54h20_enga_cpurad | 14 + soc/nordic/nrf54h/Kconfig.soc | 31 + .../nordic_nrf => nordic}/nrf54h/align.ld | 0 soc/{arm/nordic_nrf => nordic}/nrf54h/soc.c | 0 soc/{arm/nordic_nrf => nordic}/nrf54h/soc.h | 0 soc/nordic/nrf54l/CMakeLists.txt | 12 + soc/nordic/nrf54l/Kconfig | 66 + soc/nordic/nrf54l/Kconfig.defconfig | 16 + .../Kconfig.defconfig.nrf54l15_enga_cpuapp | 4 - soc/nordic/nrf54l/Kconfig.soc | 25 + soc/{arm/nordic_nrf => nordic}/nrf54l/soc.c | 0 soc/{arm/nordic_nrf => nordic}/nrf54l/soc.h | 0 soc/nordic/nrf91/CMakeLists.txt | 4 + soc/nordic/nrf91/Kconfig | 37 + soc/nordic/nrf91/Kconfig.defconfig | 14 + .../nrf91/Kconfig.defconfig.nrf9131_LACA | 3 - .../nrf91/Kconfig.defconfig.nrf9151_LACA | 3 - .../nrf91/Kconfig.defconfig.nrf9160_SICA | 3 - .../nrf91/Kconfig.defconfig.nrf9161_LACA | 3 - soc/nordic/nrf91/Kconfig.soc | 47 + soc/{arm/nordic_nrf => nordic}/nrf91/soc.c | 0 soc/{arm/nordic_nrf => nordic}/nrf91/soc.h | 0 soc/nordic/soc.yml | 39 + soc/{arm/nordic_nrf => nordic}/timing.c | 0 .../validate_base_addresses.c | 3 +- .../validate_enabled_instances.c | 0 .../validate_rram_partitions.c | 0 .../npcx}/CMakeLists.txt | 0 soc/nuvoton/npcx/Kconfig | 189 +++ soc/nuvoton/npcx/Kconfig.defconfig | 10 + soc/nuvoton/npcx/Kconfig.soc | 12 + soc/nuvoton/npcx/common/CMakeLists.txt | 48 + .../npcx}/common/ecst/ecst.py | 0 .../npcx}/common/ecst/ecst_args.py | 0 .../npcx}/common/pinctrl_soc.h | 0 .../npcx}/common/power.c | 0 .../npcx}/common/reg/reg_access.h | 0 .../npcx}/common/reg/reg_def.h | 0 .../npcx}/common/registers.c | 0 .../npcx}/common/scfg.c | 0 .../npcx}/common/soc_clock.h | 0 .../npcx}/common/soc_dbg.h | 0 .../npcx}/common/soc_dt.h | 0 .../npcx}/common/soc_espi.h | 0 .../npcx}/common/soc_espi_taf.h | 0 .../npcx}/common/soc_gpio.h | 0 .../npcx}/common/soc_host.h | 0 .../npcx}/common/soc_miwu.h | 0 .../npcx}/common/soc_pins.h | 0 .../npcx}/common/soc_power.h | 0 soc/nuvoton/npcx/npcx4/CMakeLists.txt | 12 + soc/nuvoton/npcx/npcx4/Kconfig | 12 + soc/nuvoton/npcx/npcx4/Kconfig.defconfig | 18 + soc/nuvoton/npcx/npcx4/Kconfig.soc | 29 + .../nuvoton_npcx => nuvoton/npcx}/npcx4/soc.c | 0 .../nuvoton_npcx => nuvoton/npcx}/npcx4/soc.h | 0 soc/nuvoton/npcx/npcx7/CMakeLists.txt | 17 + soc/nuvoton/npcx/npcx7/Kconfig | 13 + soc/nuvoton/npcx/npcx7/Kconfig.defconfig | 14 + soc/nuvoton/npcx/npcx7/Kconfig.soc | 36 + .../npcx}/npcx7/mpu_regions.c | 0 .../nuvoton_npcx => nuvoton/npcx}/npcx7/soc.c | 0 .../nuvoton_npcx => nuvoton/npcx}/npcx7/soc.h | 0 soc/nuvoton/npcx/npcx9/CMakeLists.txt | 8 + soc/nuvoton/npcx/npcx9/Kconfig | 13 + soc/nuvoton/npcx/npcx9/Kconfig.defconfig | 14 + soc/nuvoton/npcx/npcx9/Kconfig.soc | 43 + .../nuvoton_npcx => nuvoton/npcx}/npcx9/soc.h | 0 soc/nuvoton/npcx/soc.yml | 18 + .../numaker}/CMakeLists.txt | 0 soc/nuvoton/numaker/Kconfig | 12 + soc/nuvoton/numaker/Kconfig.defconfig | 12 + soc/nuvoton/numaker/Kconfig.soc | 11 + .../numaker}/common/pinctrl_soc.h | 0 soc/nuvoton/numaker/m46x/CMakeLists.txt | 9 + soc/nuvoton/numaker/m46x/Kconfig | 14 + soc/nuvoton/numaker/m46x/Kconfig.defconfig | 9 + .../numaker}/m46x/Kconfig.defconfig.m467 | 0 soc/nuvoton/numaker/m46x/Kconfig.soc | 19 + .../numaker}/m46x/soc.c | 0 .../numaker}/m46x/soc.h | 0 soc/nuvoton/numaker/soc.yml | 6 + .../numicro}/CMakeLists.txt | 0 soc/nuvoton/numicro/Kconfig | 13 + soc/nuvoton/numicro/Kconfig.defconfig | 10 + soc/nuvoton/numicro/Kconfig.soc | 12 + .../numicro}/common/pinctrl_soc.h | 0 soc/nuvoton/numicro/m48x/CMakeLists.txt | 10 + soc/nuvoton/numicro/m48x/Kconfig | 14 + soc/nuvoton/numicro/m48x/Kconfig.defconfig | 10 + .../numicro}/m48x/Kconfig.defconfig.m487 | 0 soc/nuvoton/numicro/m48x/Kconfig.soc | 20 + .../numicro}/m48x/soc.c | 0 .../numicro}/m48x/soc.h | 0 soc/nuvoton/numicro/soc.yml | 6 + soc/nxp/imx/CMakeLists.txt | 9 + soc/nxp/imx/Kconfig | 13 + soc/nxp/imx/Kconfig.defconfig | 10 + soc/nxp/imx/Kconfig.soc | 10 + soc/nxp/imx/imx6sx/CMakeLists.txt | 14 + soc/nxp/imx/imx6sx/Kconfig | 18 + soc/nxp/imx/imx6sx/Kconfig.defconfig | 18 + .../imx/imx6sx/Kconfig.defconfig.mcimx6x_m4 | 11 + soc/nxp/imx/imx6sx/Kconfig.soc | 83 ++ .../imx/imx6sx}/pinctrl_soc.h | 0 .../mcimx6x_m4 => nxp/imx/imx6sx}/soc.c | 0 .../mcimx6x_m4 => nxp/imx/imx6sx}/soc.h | 0 .../imx/imx6sx}/soc_clk_freq.c | 0 .../imx/imx6sx}/soc_clk_freq.h | 0 soc/nxp/imx/imx7d/CMakeLists.txt | 14 + soc/nxp/imx/imx7d/Kconfig | 16 + soc/nxp/imx/imx7d/Kconfig.defconfig | 18 + .../imx/imx7d/Kconfig.defconfig.mcimx7d_m4 | 14 + soc/nxp/imx/imx7d/Kconfig.soc | 40 + .../mcimx7_m4 => nxp/imx/imx7d}/pinctrl_soc.h | 0 .../nxp_imx/mcimx7_m4 => nxp/imx/imx7d}/soc.c | 0 .../nxp_imx/mcimx7_m4 => nxp/imx/imx7d}/soc.h | 0 .../imx/imx7d}/soc_clk_freq.c | 0 .../imx/imx7d}/soc_clk_freq.h | 0 soc/nxp/imx/imx8/CMakeLists.txt | 27 + soc/nxp/imx/imx8/Kconfig | 15 + soc/nxp/imx/imx8/Kconfig.defconfig | 45 + soc/nxp/imx/imx8/Kconfig.soc | 32 + soc/nxp/imx/imx8/adsp/CMakeLists.txt | 6 + .../imx/imx8/adsp}/_soc_inthandlers.h | 0 .../imx/imx8/adsp}/include/adsp/cache.h | 0 .../imx/imx8/adsp}/include/adsp/io.h | 0 .../imx/imx8/adsp}/include/soc.h | 0 .../imx8 => nxp/imx/imx8/adsp}/linker.ld | 0 .../include => nxp/imx/imx8/adsp}/memory.h | 0 .../imx8 => nxp/imx/imx8/adsp}/pinctrl_soc.h | 0 soc/nxp/imx/imx8m/CMakeLists.txt | 52 + soc/nxp/imx/imx8m/Kconfig | 98 ++ soc/nxp/imx/imx8m/Kconfig.defconfig | 8 + .../imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 | 53 + .../imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp | 48 + .../imx/imx8m/Kconfig.defconfig.mimx8mm.a53 | 27 + .../imx/imx8m/Kconfig.defconfig.mimx8mm.m4 | 26 + .../imx/imx8m/Kconfig.defconfig.mimx8mn.a53 | 27 + .../imx/imx8m/Kconfig.defconfig.mimx8mp.a53 | 27 + .../imx/imx8m/Kconfig.defconfig.mimx8mq.m4 | 22 + soc/nxp/imx/imx8m/Kconfig.soc | 115 ++ .../imx/imx8m/a53}/mmu_regions.c | 0 .../imx/imx8m/a53}/pinctrl_soc.h | 0 soc/nxp/imx/imx8m/adsp/CMakeLists.txt | 6 + .../imx/imx8m/adsp}/_soc_inthandlers.h | 0 soc/nxp/imx/imx8m/adsp/include/adsp/cache.h | 12 + soc/nxp/imx/imx8m/adsp/include/adsp/io.h | 41 + soc/nxp/imx/imx8m/adsp/include/soc.h | 33 + .../imx8m => nxp/imx/imx8m/adsp}/linker.ld | 0 .../include => nxp/imx/imx8m/adsp}/memory.h | 0 .../imx/imx8m/adsp}/pinctrl_soc.h | 0 soc/nxp/imx/imx8m/m4_mini/CMakeLists.txt | 19 + .../imx/imx8m/m4_mini}/linker.ld | 0 .../imx/imx8m/m4_mini}/pinctrl_soc.h | 0 .../imx/imx8m/m4_mini}/soc.c | 0 .../imx/imx8m/m4_mini}/soc.h | 0 soc/nxp/imx/imx8m/m4_quad/CMakeLists.txt | 13 + .../imx/imx8m/m4_quad}/pinctrl_soc.h | 0 .../imx/imx8m/m4_quad}/soc.c | 0 .../imx/imx8m/m4_quad}/soc.h | 0 soc/nxp/imx/imx8m/m7/CMakeLists.txt | 21 + .../imx/imx8m/m7}/linker.ld | 0 .../imx/imx8m/m7}/mpu_regions.c | 0 .../imx/imx8m/m7}/pinctrl_soc.h | 0 .../mimx8ml8_m7 => nxp/imx/imx8m/m7}/soc.c | 0 .../mimx8ml8_m7 => nxp/imx/imx8m/m7}/soc.h | 0 soc/nxp/imx/imx8ulp/CMakeLists.txt | 23 + soc/nxp/imx/imx8ulp/Kconfig | 11 + soc/nxp/imx/imx8ulp/Kconfig.defconfig | 45 + soc/nxp/imx/imx8ulp/Kconfig.soc | 26 + soc/nxp/imx/imx8ulp/adsp/CMakeLists.txt | 6 + .../imx/imx8ulp/adsp}/_soc_inthandlers.h | 0 soc/nxp/imx/imx8ulp/adsp/include/adsp/cache.h | 12 + soc/nxp/imx/imx8ulp/adsp/include/adsp/io.h | 41 + soc/nxp/imx/imx8ulp/adsp/include/soc.h | 33 + .../imx/imx8ulp/adsp}/linker.ld | 0 .../include => nxp/imx/imx8ulp/adsp}/memory.h | 0 soc/nxp/imx/imx8x/CMakeLists.txt | 27 + soc/nxp/imx/imx8x/Kconfig | 15 + soc/nxp/imx/imx8x/Kconfig.defconfig | 45 + soc/nxp/imx/imx8x/Kconfig.soc | 36 + soc/nxp/imx/imx8x/adsp/CMakeLists.txt | 6 + soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h | 177 +++ soc/nxp/imx/imx8x/adsp/include/adsp/cache.h | 12 + soc/nxp/imx/imx8x/adsp/include/adsp/io.h | 41 + soc/nxp/imx/imx8x/adsp/include/soc.h | 33 + soc/nxp/imx/imx8x/adsp/linker.ld | 517 ++++++++ soc/nxp/imx/imx8x/adsp/memory.h | 162 +++ soc/nxp/imx/imx8x/adsp/pinctrl_soc.h | 41 + soc/nxp/imx/imx9/CMakeLists.txt | 10 + soc/nxp/imx/imx9/Kconfig | 13 + soc/nxp/imx/imx9/Kconfig.defconfig | 8 + soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.a55 | 27 + soc/nxp/imx/imx9/Kconfig.soc | 32 + .../mimx9 => nxp/imx/imx9/a55}/linker.ld | 0 .../mimx9 => nxp/imx/imx9/a55}/mmu_regions.c | 0 .../mimx9 => nxp/imx/imx9}/pinctrl_soc.h | 0 soc/nxp/imx/soc.yml | 62 + soc/nxp/imxrt/CMakeLists.txt | 42 + soc/nxp/imxrt/Kconfig | 190 +++ soc/nxp/imxrt/Kconfig.defconfig | 152 +++ soc/nxp/imxrt/Kconfig.soc | 10 + soc/nxp/imxrt/boot_header.ld | 21 + .../rt => nxp/imxrt}/flexspi_nor_config.h | 2 +- soc/nxp/imxrt/imxrt10xx/CMakeLists.txt | 27 + soc/nxp/imxrt/imxrt10xx/Kconfig | 150 +++ soc/nxp/imxrt/imxrt10xx/Kconfig.defconfig | 28 + soc/nxp/imxrt/imxrt10xx/Kconfig.soc | 238 ++++ .../imxrt/imxrt10xx/flexspi.c} | 0 soc/nxp/imxrt/imxrt10xx/linker.ld | 21 + .../rt => nxp/imxrt/imxrt10xx}/lpm_rt1064.c | 20 +- .../imxrt/imxrt10xx/pinctrl_soc.h} | 0 soc/nxp/imxrt/imxrt10xx/power.c | 276 +++++ .../imxrt/imxrt10xx/power.h} | 0 soc/nxp/imxrt/imxrt10xx/soc.c | 344 ++++++ soc/nxp/imxrt/imxrt10xx/soc.h | 48 + soc/nxp/imxrt/imxrt11xx/CMakeLists.txt | 19 + soc/nxp/imxrt/imxrt11xx/Kconfig | 75 ++ soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig | 35 + soc/nxp/imxrt/imxrt11xx/Kconfig.soc | 95 ++ .../imxrt/imxrt11xx/flexspi.c} | 0 soc/nxp/imxrt/imxrt11xx/linker.ld | 21 + .../imxrt/imxrt11xx/pinctrl_soc.h} | 0 .../imxrt/imxrt11xx/power.c} | 0 .../imxrt/imxrt11xx/power.h} | 0 soc/nxp/imxrt/imxrt11xx/soc.c | 728 +++++++++++ soc/nxp/imxrt/imxrt11xx/soc.h | 48 + soc/nxp/imxrt/imxrt5xx/CMakeLists.txt | 11 + soc/nxp/imxrt/imxrt5xx/Kconfig | 85 ++ soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig | 119 ++ soc/nxp/imxrt/imxrt5xx/Kconfig.soc | 60 + soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt | 29 + .../imxrt/imxrt5xx/cm33}/flash_clock_setup.c | 0 .../imxrt/imxrt5xx/cm33}/flash_clock_setup.h | 0 .../imxrt/imxrt5xx/cm33}/linker.ld | 0 .../imxrt/imxrt5xx/cm33}/pinctrl_soc.h | 0 .../rt5xx => nxp/imxrt/imxrt5xx/cm33}/power.c | 0 .../imxrt/imxrt5xx/cm33}/poweroff.c | 0 soc/nxp/imxrt/imxrt5xx/cm33/soc.c | 544 +++++++++ .../rt5xx => nxp/imxrt/imxrt5xx/cm33}/soc.h | 0 .../rt5xx => nxp/imxrt/imxrt5xx/cm33}/usb.ld | 0 soc/nxp/imxrt/imxrt5xx/f1/CMakeLists.txt | 23 + .../imxrt5xx/f1}/include/_soc_inthandlers.h | 0 .../imxrt/imxrt5xx/f1/include/adsp/cache.h | 12 + soc/nxp/imxrt/imxrt5xx/f1/include/adsp/io.h | 41 + soc/nxp/imxrt/imxrt5xx/f1/include/soc.h | 33 + .../imxrt/imxrt5xx/f1}/include/soc/memory.h | 0 .../rt5xx => nxp/imxrt/imxrt5xx/f1}/linker.ld | 0 soc/nxp/imxrt/imxrt6xx/CMakeLists.txt | 26 + soc/nxp/imxrt/imxrt6xx/Kconfig | 65 + soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig | 113 ++ soc/nxp/imxrt/imxrt6xx/Kconfig.soc | 33 + .../imxrt/imxrt6xx}/flash_clock_setup.c | 0 .../imxrt/imxrt6xx}/flash_clock_setup.h | 0 .../imxrt/imxrt6xx}/pinctrl_soc.h | 0 .../rt6xx => nxp/imxrt/imxrt6xx}/power.c | 0 soc/nxp/imxrt/imxrt6xx/soc.c | 395 ++++++ .../rt6xx => nxp/imxrt/imxrt6xx}/soc.h | 0 .../nxp_imx/rt => nxp/imxrt}/mpu_regions.c | 0 soc/nxp/imxrt/soc.yml | 34 + soc/{arm/nxp_imx/rt6xx => nxp/imxrt}/usb.ld | 2 +- .../kinetis}/CMakeLists.txt | 0 soc/nxp/kinetis/Kconfig | 156 +++ soc/nxp/kinetis/Kconfig.defconfig | 16 + soc/nxp/kinetis/Kconfig.soc | 10 + .../kinetis}/common/pinctrl_soc.h | 0 .../kinetis}/flash_config.ld | 0 .../kinetis}/flash_configuration.c | 0 soc/nxp/kinetis/k2x/CMakeLists.txt | 19 + soc/nxp/kinetis/k2x/Kconfig | 47 + soc/nxp/kinetis/k2x/Kconfig.defconfig | 26 + soc/nxp/kinetis/k2x/Kconfig.soc | 40 + .../kinetis}/k2x/nxp_mpu_regions.c | 0 .../nxp_kinetis => nxp/kinetis}/k2x/soc.c | 0 .../nxp_kinetis => nxp/kinetis}/k2x/soc.h | 0 soc/nxp/kinetis/k6x/CMakeLists.txt | 13 + soc/nxp/kinetis/k6x/Kconfig | 59 + soc/nxp/kinetis/k6x/Kconfig.defconfig | 22 + soc/nxp/kinetis/k6x/Kconfig.soc | 70 ++ .../kinetis}/k6x/README.txt | 0 .../kinetis}/k6x/nxp_mpu_regions.c | 0 .../nxp_kinetis => nxp/kinetis}/k6x/soc.c | 0 .../nxp_kinetis => nxp/kinetis}/k6x/soc.h | 0 soc/nxp/kinetis/k8x/CMakeLists.txt | 13 + soc/nxp/kinetis/k8x/Kconfig | 61 + soc/nxp/kinetis/k8x/Kconfig.defconfig | 23 + soc/nxp/kinetis/k8x/Kconfig.soc | 42 + .../kinetis}/k8x/nxp_mpu_regions.c | 0 .../nxp_kinetis => nxp/kinetis}/k8x/soc.c | 0 .../nxp_kinetis => nxp/kinetis}/k8x/soc.h | 0 soc/nxp/kinetis/ke1xf/CMakeLists.txt | 17 + soc/nxp/kinetis/ke1xf/Kconfig | 68 ++ soc/nxp/kinetis/ke1xf/Kconfig.defconfig | 37 + soc/nxp/kinetis/ke1xf/Kconfig.soc | 79 ++ .../kinetis}/ke1xf/nxp_mpu_regions.c | 0 .../nxp_kinetis => nxp/kinetis}/ke1xf/power.c | 0 .../nxp_kinetis => nxp/kinetis}/ke1xf/soc.c | 0 .../nxp_kinetis => nxp/kinetis}/ke1xf/soc.h | 0 soc/nxp/kinetis/kl2x/CMakeLists.txt | 7 + soc/nxp/kinetis/kl2x/Kconfig | 23 + soc/nxp/kinetis/kl2x/Kconfig.defconfig | 11 + soc/nxp/kinetis/kl2x/Kconfig.soc | 68 ++ .../nxp_kinetis => nxp/kinetis}/kl2x/soc.c | 0 .../nxp_kinetis => nxp/kinetis}/kl2x/soc.h | 0 soc/nxp/kinetis/kv5x/CMakeLists.txt | 9 + soc/nxp/kinetis/kv5x/Kconfig | 24 + soc/nxp/kinetis/kv5x/Kconfig.defconfig | 16 + soc/nxp/kinetis/kv5x/Kconfig.soc | 58 + .../nxp_kinetis => nxp/kinetis}/kv5x/soc.c | 0 .../nxp_kinetis => nxp/kinetis}/kv5x/soc.h | 0 .../nxp_kinetis => nxp/kinetis}/kv5x/wdog.S | 0 soc/nxp/kinetis/kwx/CMakeLists.txt | 10 + soc/nxp/kinetis/kwx/Kconfig | 62 + soc/nxp/kinetis/kwx/Kconfig.defconfig | 34 + soc/nxp/kinetis/kwx/Kconfig.soc | 55 + .../nxp_kinetis => nxp/kinetis}/kwx/soc.h | 0 .../kinetis}/kwx/soc_kw2xd.c | 0 .../kinetis}/kwx/soc_kw4xz.c | 0 soc/nxp/kinetis/soc.yml | 31 + .../layerscape}/CMakeLists.txt | 0 soc/nxp/layerscape/Kconfig | 11 + soc/nxp/layerscape/Kconfig.defconfig | 11 + soc/nxp/layerscape/Kconfig.soc | 13 + .../layerscape}/ls1046a/CMakeLists.txt | 0 soc/nxp/layerscape/ls1046a/Kconfig | 10 + soc/nxp/layerscape/ls1046a/Kconfig.defconfig | 19 + soc/nxp/layerscape/ls1046a/Kconfig.soc | 31 + .../layerscape}/ls1046a/mmu_regions.c | 0 soc/nxp/layerscape/soc.yml | 6 + soc/{arm/nxp_lpc => nxp/lpc}/CMakeLists.txt | 0 soc/nxp/lpc/Kconfig | 12 + soc/nxp/lpc/Kconfig.defconfig | 14 + soc/nxp/lpc/Kconfig.soc | 10 + soc/nxp/lpc/lpc11u6x/CMakeLists.txt | 9 + soc/nxp/lpc/lpc11u6x/Kconfig | 14 + soc/nxp/lpc/lpc11u6x/Kconfig.defconfig | 15 + soc/nxp/lpc/lpc11u6x/Kconfig.soc | 55 + soc/{arm/nxp_lpc => nxp/lpc}/lpc11u6x/iap.h | 0 .../lpc}/lpc11u6x/pinctrl_soc.h | 0 soc/{arm/nxp_lpc => nxp/lpc}/lpc11u6x/soc.h | 0 soc/nxp/lpc/lpc51u68/CMakeLists.txt | 18 + soc/nxp/lpc/lpc51u68/Kconfig | 21 + soc/nxp/lpc/lpc51u68/Kconfig.defconfig | 17 + soc/nxp/lpc/lpc51u68/Kconfig.soc | 29 + .../nxp_lpc => nxp/lpc}/lpc51u68/linker.ld | 0 .../lpc}/lpc51u68/pinctrl_soc.h | 0 soc/{arm/nxp_lpc => nxp/lpc}/lpc51u68/soc.c | 0 soc/{arm/nxp_lpc => nxp/lpc}/lpc51u68/soc.h | 0 soc/nxp/lpc/lpc54xxx/CMakeLists.txt | 25 + soc/nxp/lpc/lpc54xxx/Kconfig | 69 ++ soc/nxp/lpc/lpc54xxx/Kconfig.defconfig | 15 + soc/nxp/lpc/lpc54xxx/Kconfig.soc | 38 + .../lpc}/lpc54xxx/gcc/startup_LPC54114_cm4.S | 0 .../nxp_lpc => nxp/lpc}/lpc54xxx/linker.ld | 0 .../lpc}/lpc54xxx/pinctrl_soc.h | 0 soc/{arm/nxp_lpc => nxp/lpc}/lpc54xxx/soc.c | 0 soc/{arm/nxp_lpc => nxp/lpc}/lpc54xxx/soc.h | 0 soc/nxp/lpc/lpc55xxx/CMakeLists.txt | 29 + soc/nxp/lpc/lpc55xxx/Kconfig | 114 ++ soc/nxp/lpc/lpc55xxx/Kconfig.defconfig | 114 ++ soc/nxp/lpc/lpc55xxx/Kconfig.soc | 74 ++ .../nxp_lpc => nxp/lpc}/lpc55xxx/linker.ld | 0 .../lpc}/lpc55xxx/pinctrl_soc.h | 0 soc/{arm/nxp_lpc => nxp/lpc}/lpc55xxx/soc.c | 0 soc/{arm/nxp_lpc => nxp/lpc}/lpc55xxx/soc.h | 0 soc/{arm/nxp_lpc => nxp/lpc}/lpc55xxx/usb.ld | 0 soc/nxp/lpc/soc.yml | 27 + soc/{arm/nxp_s32 => nxp/s32}/CMakeLists.txt | 0 soc/nxp/s32/Kconfig | 31 + soc/nxp/s32/Kconfig.defconfig | 8 + soc/nxp/s32/Kconfig.soc | 10 + soc/nxp/s32/common/CMakeLists.txt | 6 + .../s32}/common/cmsis_rtos_v2_adapt.h | 0 soc/{arm/nxp_s32 => nxp/s32}/common/osif.c | 2 +- .../nxp_s32 => nxp/s32}/common/pinctrl_soc.h | 0 .../nxp_s32 => nxp/s32}/common/power_soc.c | 2 +- soc/nxp/s32/s32k1/CMakeLists.txt | 12 + soc/nxp/s32/s32k1/Kconfig | 124 ++ soc/nxp/s32/s32k1/Kconfig.defconfig | 30 + soc/nxp/s32/s32k1/Kconfig.soc | 371 ++++++ .../nxp_s32 => nxp/s32}/s32k1/flash_config.ld | 0 .../s32}/s32k1/flash_configuration.c | 0 .../s32}/s32k1/nxp_mpu_regions.c | 2 +- .../nxp_s32 => nxp/s32}/s32k1/pinctrl_soc.h | 0 soc/nxp/s32/s32k1/soc.c | 78 ++ soc/{arm/nxp_s32 => nxp/s32}/s32k1/soc.h | 0 soc/nxp/s32/s32k3/CMakeLists.txt | 13 + soc/nxp/s32/s32k3/Kconfig | 60 + soc/nxp/s32/s32k3/Kconfig.defconfig | 38 + soc/nxp/s32/s32k3/Kconfig.soc | 24 + soc/{arm/nxp_s32 => nxp/s32}/s32k3/linker.ld | 0 .../nxp_s32 => nxp/s32}/s32k3/mpu_regions.c | 0 .../s32}/s32k3/s32k3xx_startup.S | 0 .../nxp_s32 => nxp/s32}/s32k3/sections.ld | 0 soc/{arm/nxp_s32 => nxp/s32}/s32k3/soc.c | 0 soc/{arm/nxp_s32 => nxp/s32}/s32k3/soc.h | 0 soc/nxp/s32/s32ze/CMakeLists.txt | 12 + soc/nxp/s32/s32ze/Kconfig | 30 + soc/nxp/s32/s32ze/Kconfig.defconfig | 40 + soc/nxp/s32/s32ze/Kconfig.soc | 32 + .../nxp_s32 => nxp/s32}/s32ze/mpu_regions.c | 0 soc/{arm/nxp_s32 => nxp/s32}/s32ze/soc.c | 0 soc/nxp/s32/s32ze/soc.h | 74 ++ soc/nxp/s32/soc.yml | 22 + soc/openisa/rv32m1/CMakeLists.txt | 26 + soc/openisa/rv32m1/Kconfig | 22 + soc/openisa/rv32m1/Kconfig.defconfig | 122 ++ soc/openisa/rv32m1/Kconfig.soc | 24 + .../rv32m1}/linker.ld | 0 .../rv32m1}/pinctrl_soc.h | 0 .../openisa_rv32m1 => openisa/rv32m1}/soc.c | 0 .../openisa_rv32m1 => openisa/rv32m1}/soc.h | 0 soc/openisa/rv32m1/soc.yml | 5 + .../rv32m1}/soc_context.h | 0 .../rv32m1}/soc_irq.S | 0 .../rv32m1}/soc_offsets.h | 0 .../rv32m1}/soc_ri5cy.h | 0 .../rv32m1}/soc_zero_riscy.h | 0 .../rv32m1}/vector.S | 0 .../rv32m1}/vector_table.ld | 0 .../openisa_rv32m1 => openisa/rv32m1}/wdog.S | 0 soc/posix/CMakeLists.txt | 8 - soc/posix/inf_clock/CMakeLists.txt | 17 - soc/posix/inf_clock/Kconfig | 49 - soc/posix/inf_clock/Kconfig.defconfig | 6 - soc/posix/inf_clock/Kconfig.soc | 15 - soc/qemu_malta/CMakeLists.txt | 21 + soc/qemu_malta/Kconfig | 6 + soc/qemu_malta/Kconfig.defconfig | 13 + soc/qemu_malta/Kconfig.soc | 9 + soc/{mips => }/qemu_malta/soc.h | 0 soc/qemu_malta/soc.yml | 2 + soc/{mips => }/qemu_malta/vector.S | 0 soc/quicklogic/eos_s3/CMakeLists.txt | 10 + soc/quicklogic/eos_s3/Kconfig | 10 + soc/quicklogic/eos_s3/Kconfig.defconfig | 19 + soc/quicklogic/eos_s3/Kconfig.soc | 10 + .../eos_s3}/pinctrl_soc.h | 0 .../eos_s3}/soc.c | 0 .../eos_s3}/soc.h | 0 soc/quicklogic/eos_s3/soc.yml | 2 + .../eos_s3}/soc_pinmap.h | 0 .../bcm_vk => raspberrypi}/CMakeLists.txt | 0 soc/raspberrypi/Kconfig | 11 + soc/raspberrypi/Kconfig.defconfig | 13 + soc/raspberrypi/Kconfig.soc | 12 + soc/raspberrypi/rp2xxx/CMakeLists.txt | 10 + soc/raspberrypi/rp2xxx/Kconfig | 53 + soc/raspberrypi/rp2xxx/Kconfig.defconfig | 14 + .../rp2xxx}/Kconfig.defconfig.rp2040 | 4 - soc/raspberrypi/rp2xxx/Kconfig.soc | 19 + .../rp2 => raspberrypi/rp2xxx}/linker.ld | 0 .../rp2 => raspberrypi/rp2xxx}/pinctrl_soc.h | 0 .../rpi_pico/rp2 => raspberrypi/rp2xxx}/soc.c | 0 .../rpi_pico/rp2 => raspberrypi/rp2xxx}/soc.h | 0 soc/raspberrypi/soc.yml | 6 + .../renesas_ra => renesas/ra}/CMakeLists.txt | 0 soc/renesas/ra/Kconfig | 11 + soc/renesas/ra/Kconfig.defconfig | 8 + soc/renesas/ra/Kconfig.soc | 10 + .../ra}/common/pinctrl_ra.h | 0 .../ra}/common/ra_common_soc.h | 0 soc/renesas/ra/ra4m1/CMakeLists.txt | 6 + soc/renesas/ra/ra4m1/Kconfig | 11 + soc/renesas/ra/ra4m1/Kconfig.defconfig | 9 + soc/renesas/ra/ra4m1/Kconfig.soc | 20 + .../ra}/ra4m1/pinctrl_soc.h | 0 .../renesas_ra => renesas/ra}/ra4m1/soc.h | 0 soc/renesas/ra/soc.yml | 6 + .../rcar}/CMakeLists.txt | 0 soc/renesas/rcar/Kconfig | 9 + soc/renesas/rcar/Kconfig.defconfig | 8 + soc/renesas/rcar/Kconfig.soc | 11 + .../rcar}/common/pinctrl_rcar.h | 0 soc/renesas/rcar/rcar_gen3/CMakeLists.txt | 18 + soc/renesas/rcar/rcar_gen3/Kconfig | 26 + soc/renesas/rcar/rcar_gen3/Kconfig.defconfig | 15 + soc/renesas/rcar/rcar_gen3/Kconfig.soc | 31 + .../rcar/rcar_gen3/a57}/pinctrl_soc.h | 0 .../rcar/rcar_gen3}/mmu_regions.c | 0 .../rcar/rcar_gen3}/pfc_r8a77951.c | 0 .../rcar/rcar_gen3}/pfc_r8a77961.c | 0 .../rcar/rcar_gen3/r7}/pinctrl_soc.h | 0 .../gen3 => renesas/rcar/rcar_gen3/r7}/soc.c | 0 .../gen3 => renesas/rcar/rcar_gen3/r7}/soc.h | 0 soc/renesas/rcar/rcar_gen4/CMakeLists.txt | 6 + soc/renesas/rcar/rcar_gen4/Kconfig | 10 + soc/renesas/rcar/rcar_gen4/Kconfig.defconfig | 10 + .../rcar_gen4}/Kconfig.defconfig.r8a779f0 | 3 - soc/renesas/rcar/rcar_gen4/Kconfig.soc | 18 + .../rcar/rcar_gen4}/pfc_r8a779f0.c | 0 .../rcar/rcar_gen4}/pinctrl_soc.h | 0 .../gen4 => renesas/rcar/rcar_gen4}/soc.h | 0 soc/renesas/rcar/soc.yml | 13 + soc/renesas/rzt2m/CMakeLists.txt | 8 + soc/renesas/rzt2m/Kconfig | 11 + soc/renesas/rzt2m/Kconfig.defconfig | 21 + soc/renesas/rzt2m/Kconfig.soc | 14 + .../renesas_rzt2m => renesas/rzt2m}/linker.ld | 0 .../rzt2m}/pinctrl_soc.h | 0 .../renesas_rzt2m => renesas/rzt2m}/soc.c | 0 .../renesas_rzt2m => renesas/rzt2m}/soc.h | 0 soc/renesas/rzt2m/soc.yml | 2 + .../smartbond}/CMakeLists.txt | 0 soc/renesas/smartbond/Kconfig | 8 + soc/renesas/smartbond/Kconfig.defconfig | 11 + soc/renesas/smartbond/Kconfig.soc | 10 + soc/renesas/smartbond/da1469x/CMakeLists.txt | 12 + soc/renesas/smartbond/da1469x/Kconfig | 13 + .../smartbond/da1469x/Kconfig.defconfig | 27 + soc/renesas/smartbond/da1469x/Kconfig.soc | 27 + .../smartbond}/da1469x/intvect_reserved.ld | 0 .../smartbond}/da1469x/pinctrl_soc.h | 0 .../smartbond}/da1469x/soc.c | 0 .../smartbond}/da1469x/soc.h | 0 soc/renesas/smartbond/soc.yml | 7 + .../riscv_virtual}/CMakeLists.txt | 0 soc/renode/riscv_virtual/Kconfig | 15 + soc/renode/riscv_virtual/Kconfig.defconfig | 39 + soc/renode/riscv_virtual/Kconfig.soc | 10 + soc/renode/riscv_virtual/soc.yml | 2 + soc/riscv/CMakeLists.txt | 9 - soc/riscv/andes_v5/Kconfig | 15 - soc/riscv/andes_v5/Kconfig.defconfig | 4 - soc/riscv/andes_v5/Kconfig.soc | 4 - .../andes_v5/ae350/Kconfig.defconfig.series | 42 - soc/riscv/andes_v5/ae350/Kconfig.series | 11 - soc/riscv/andes_v5/ae350/Kconfig.soc | 124 -- soc/riscv/common/CMakeLists.txt | 1 - soc/riscv/common/Kconfig | 4 - soc/riscv/efinix_sapphire/Kconfig.defconfig | 23 - soc/riscv/efinix_sapphire/Kconfig.soc | 15 - soc/riscv/espressif_esp32/CMakeLists.txt | 5 - soc/riscv/espressif_esp32/Kconfig | 16 - soc/riscv/espressif_esp32/Kconfig.defconfig | 5 - soc/riscv/espressif_esp32/Kconfig.soc | 4 - .../espressif_esp32/common/CMakeLists.txt | 2 - .../common/Kconfig.defconfig.series | 52 - soc/riscv/espressif_esp32/common/Kconfig.soc | 15 - .../espressif_esp32/esp32c3/CMakeLists.txt | 101 -- .../esp32c3/Kconfig.defconfig.series | 21 - .../espressif_esp32/esp32c3/Kconfig.series | 21 - soc/riscv/espressif_esp32/esp32c3/Kconfig.soc | 99 -- soc/riscv/gd_gd32/Kconfig | 15 - soc/riscv/gd_gd32/Kconfig.defconfig | 4 - soc/riscv/gd_gd32/Kconfig.soc | 4 - soc/riscv/gd_gd32/gd32vf103/CMakeLists.txt | 9 - .../gd32vf103/Kconfig.defconfig.series | 11 - soc/riscv/gd_gd32/gd32vf103/Kconfig.series | 20 - soc/riscv/gd_gd32/gd32vf103/Kconfig.soc | 19 - soc/riscv/gd_gd32/gd32vf103/pinctrl_soc.h | 17 - soc/riscv/intel_niosv/Kconfig | 15 - soc/riscv/intel_niosv/Kconfig.defconfig | 4 - soc/riscv/intel_niosv/Kconfig.soc | 4 - .../niosv/Kconfig.defconfig.series | 21 - soc/riscv/intel_niosv/niosv/Kconfig.series | 10 - soc/riscv/intel_niosv/niosv/Kconfig.soc | 27 - soc/riscv/ite_ec/Kconfig | 17 - soc/riscv/ite_ec/Kconfig.defconfig | 4 - soc/riscv/ite_ec/Kconfig.soc | 4 - soc/riscv/ite_ec/it8xxx2/CMakeLists.txt | 9 - .../it8xxx2/Kconfig.defconfig.it82302ax | 9 - .../ite_ec/it8xxx2/Kconfig.defconfig.series | 59 - soc/riscv/ite_ec/it8xxx2/Kconfig.series | 13 - soc/riscv/ite_ec/it8xxx2/Kconfig.soc | 173 --- soc/riscv/litex_vexriscv/CMakeLists.txt | 12 - soc/riscv/litex_vexriscv/Kconfig.defconfig | 15 - soc/riscv/litex_vexriscv/Kconfig.soc | 21 - soc/riscv/microchip_miv/CMakeLists.txt | 4 - soc/riscv/microchip_miv/Kconfig | 15 - soc/riscv/microchip_miv/Kconfig.defconfig | 4 - soc/riscv/microchip_miv/Kconfig.soc | 4 - .../miv/Kconfig.defconfig.series | 29 - soc/riscv/microchip_miv/miv/Kconfig.series | 13 - soc/riscv/microchip_miv/miv/Kconfig.soc | 20 - .../microchip_miv/polarfire/CMakeLists.txt | 5 - .../polarfire/Kconfig.defconfig.series | 32 - .../microchip_miv/polarfire/Kconfig.series | 13 - soc/riscv/microchip_miv/polarfire/Kconfig.soc | 30 - soc/riscv/neorv32/Kconfig.defconfig | 29 - soc/riscv/neorv32/Kconfig.soc | 50 - soc/riscv/nordic_nrf/Kconfig | 18 - soc/riscv/nordic_nrf/Kconfig.defconfig | 16 - soc/riscv/nordic_nrf/Kconfig.soc | 4 - soc/riscv/nordic_nrf/common/CMakeLists.txt | 4 - soc/riscv/nordic_nrf/common/Kconfig | 4 - soc/riscv/nordic_nrf/common/Kconfig.defconfig | 8 - .../nordic_nrf/common/vpr/CMakeLists.txt | 9 - soc/riscv/nordic_nrf/nrf54h/CMakeLists.txt | 6 - .../nrf54h/Kconfig.defconfig.series | 19 - soc/riscv/nordic_nrf/nrf54h/Kconfig.series | 10 - soc/riscv/nordic_nrf/nrf54h/Kconfig.soc | 19 - soc/riscv/nordic_nrf/nrf54h/align.ld | 10 - soc/riscv/openisa_rv32m1/CMakeLists.txt | 24 - soc/riscv/openisa_rv32m1/Kconfig | 25 - soc/riscv/openisa_rv32m1/Kconfig.defconfig | 125 -- soc/riscv/openisa_rv32m1/Kconfig.soc | 29 - soc/riscv/opentitan/Kconfig.defconfig | 27 - soc/riscv/opentitan/Kconfig.soc | 22 - soc/riscv/qemu_virt_riscv/CMakeLists.txt | 5 + soc/riscv/qemu_virt_riscv/Kconfig | 18 + soc/riscv/qemu_virt_riscv/Kconfig.defconfig | 31 + soc/riscv/qemu_virt_riscv/Kconfig.soc | 10 + .../qemu_virt_riscv/common/CMakeLists.txt | 4 + .../{virt => qemu_virt_riscv/common}/soc.c | 0 .../qemu_virt_riscv/qemu_virt_riscv32/Kconfig | 8 + .../qemu_virt_riscv32/Kconfig.soc | 9 + .../qemu_virt_riscv32e/Kconfig | 8 + .../qemu_virt_riscv32e/Kconfig.soc | 9 + .../qemu_virt_riscv/qemu_virt_riscv64/Kconfig | 9 + .../qemu_virt_riscv64/Kconfig.soc | 9 + soc/riscv/qemu_virt_riscv/soc.yml | 6 + soc/riscv/renode_virt/Kconfig.defconfig | 42 - soc/riscv/renode_virt/Kconfig.soc | 16 - soc/riscv/sifive_freedom/CMakeLists.txt | 5 - soc/riscv/sifive_freedom/Kconfig | 15 - soc/riscv/sifive_freedom/Kconfig.defconfig | 4 - soc/riscv/sifive_freedom/Kconfig.soc | 4 - soc/riscv/sifive_freedom/e300/CMakeLists.txt | 5 - .../e300/Kconfig.defconfig.e340 | 5 - .../e300/Kconfig.defconfig.series | 32 - soc/riscv/sifive_freedom/e300/Kconfig.series | 13 - soc/riscv/sifive_freedom/e300/Kconfig.soc | 20 - soc/riscv/sifive_freedom/u500/CMakeLists.txt | 5 - .../u500/Kconfig.defconfig.series | 32 - .../u500/Kconfig.defconfig.u540 | 5 - soc/riscv/sifive_freedom/u500/Kconfig.series | 13 - soc/riscv/sifive_freedom/u500/Kconfig.soc | 22 - soc/riscv/sifive_freedom/u700/CMakeLists.txt | 5 - .../u700/Kconfig.defconfig.series | 32 - .../u700/Kconfig.defconfig.u740 | 5 - soc/riscv/sifive_freedom/u700/Kconfig.series | 13 - soc/riscv/sifive_freedom/u700/Kconfig.soc | 22 - soc/riscv/starfive_jh71xx/CMakeLists.txt | 4 - soc/riscv/starfive_jh71xx/Kconfig | 15 - soc/riscv/starfive_jh71xx/Kconfig.defconfig | 4 - soc/riscv/starfive_jh71xx/Kconfig.soc | 4 - .../jh71xx/Kconfig.defconfig.jh7100 | 5 - .../jh71xx/Kconfig.defconfig.series | 29 - .../starfive_jh71xx/jh71xx/Kconfig.series | 10 - soc/riscv/starfive_jh71xx/jh71xx/Kconfig.soc | 19 - soc/riscv/telink_tlsr/CMakeLists.txt | 4 - soc/riscv/telink_tlsr/Kconfig | 15 - soc/riscv/telink_tlsr/Kconfig.defconfig | 4 - soc/riscv/telink_tlsr/Kconfig.soc | 4 - soc/riscv/telink_tlsr/tlsr951x/CMakeLists.txt | 18 - .../tlsr951x/Kconfig.defconfig.series | 53 - .../tlsr951x/Kconfig.defconfig.tlsr9518 | 5 - soc/riscv/telink_tlsr/tlsr951x/Kconfig.series | 21 - soc/riscv/telink_tlsr/tlsr951x/Kconfig.soc | 23 - soc/riscv/virt/CMakeLists.txt | 5 - soc/riscv/virt/Kconfig.defconfig | 33 - soc/riscv/virt/Kconfig.soc | 13 - soc/rockchip/CMakeLists.txt | 7 + soc/rockchip/Kconfig | 11 + soc/rockchip/Kconfig.defconfig | 11 + soc/rockchip/Kconfig.soc | 13 + .../rockchip/rk3399/CMakeLists.txt | 0 soc/rockchip/rk3399/Kconfig | 13 + soc/rockchip/rk3399/Kconfig.defconfig | 11 + .../rockchip/rk3399/Kconfig.defconfig.rk3399 | 3 - soc/rockchip/rk3399/Kconfig.soc | 19 + soc/{arm64 => }/rockchip/rk3399/mmu_regions.c | 0 soc/rockchip/rk3568/CMakeLists.txt | 5 + soc/rockchip/rk3568/Kconfig | 12 + soc/rockchip/rk3568/Kconfig.defconfig | 9 + .../rockchip/rk3568/Kconfig.defconfig.rk3568 | 3 - soc/rockchip/rk3568/Kconfig.soc | 17 + soc/{arm64 => }/rockchip/rk3568/mmu_regions.c | 0 soc/rockchip/soc.yml | 9 + .../sifive_freedom}/CMakeLists.txt | 0 soc/sifive/sifive_freedom/Kconfig | 9 + soc/sifive/sifive_freedom/Kconfig.defconfig | 9 + soc/sifive/sifive_freedom/Kconfig.soc | 11 + .../sifive_freedom/common/CMakeLists.txt | 0 .../sifive_freedom/common/pinctrl_soc.h | 0 .../sifive_freedom/fe300/CMakeLists.txt | 6 + soc/sifive/sifive_freedom/fe300/Kconfig | 19 + .../sifive_freedom/fe300/Kconfig.defconfig | 28 + soc/sifive/sifive_freedom/fe300/Kconfig.soc | 16 + .../sifive_freedom/fe300}/clock.c | 0 .../sifive_freedom/fe300}/prci.h | 0 .../sifive_freedom/fe300}/soc.h | 0 .../sifive_freedom/fu500/CMakeLists.txt | 6 + soc/sifive/sifive_freedom/fu500/Kconfig | 20 + .../sifive_freedom/fu500/Kconfig.defconfig | 28 + soc/sifive/sifive_freedom/fu500/Kconfig.soc | 16 + .../sifive_freedom/fu500}/clock.c | 0 .../sifive_freedom/fu500}/prci.h | 0 .../sifive_freedom/fu500}/soc.h | 0 .../sifive_freedom/fu700/CMakeLists.txt | 6 + soc/sifive/sifive_freedom/fu700/Kconfig | 19 + .../sifive_freedom/fu700/Kconfig.defconfig | 27 + soc/sifive/sifive_freedom/fu700/Kconfig.soc | 16 + .../sifive_freedom/fu700}/clock.c | 0 .../sifive_freedom/fu700}/prci.h | 0 .../sifive_freedom/fu700}/soc.h | 0 soc/sifive/sifive_freedom/soc.yml | 12 + soc/silabs/CMakeLists.txt | 5 + soc/silabs/Kconfig | 325 +++++ soc/silabs/Kconfig.defconfig | 22 + soc/silabs/Kconfig.soc | 12 + .../common/CMakeLists.txt | 0 soc/silabs/common/pinctrl_soc.h | 95 ++ .../common/sl_device_init_hfxo_config.h | 0 soc/silabs/common/soc.c | 247 ++++ soc/silabs/common/soc_gpio.h | 32 + .../common/soc_power.c | 0 .../common/soc_power_pmgr.c | 0 soc/silabs/silabs_s0/Kconfig.soc | 8 + soc/silabs/silabs_s0/efm32hg/Kconfig | 17 + .../silabs_s0/efm32hg/Kconfig.defconfig | 13 + soc/silabs/silabs_s0/efm32hg/Kconfig.soc | 23 + .../silabs_s0}/efm32hg/soc.h | 0 .../silabs_s0}/efm32hg/soc_pinmap.h | 0 soc/silabs/silabs_s0/efm32wg/Kconfig | 18 + .../silabs_s0/efm32wg/Kconfig.defconfig | 12 + soc/silabs/silabs_s0/efm32wg/Kconfig.soc | 23 + .../silabs_s0}/efm32wg/soc.h | 0 .../silabs_s0}/efm32wg/soc_pinmap.h | 0 soc/silabs/silabs_s1/Kconfig.soc | 8 + soc/silabs/silabs_s1/efm32gg11b/Kconfig | 21 + .../silabs_s1/efm32gg11b/Kconfig.defconfig | 17 + soc/silabs/silabs_s1/efm32gg11b/Kconfig.soc | 29 + .../silabs_s1}/efm32gg11b/soc.h | 0 .../silabs_s1}/efm32gg11b/soc_pinmap.h | 0 soc/silabs/silabs_s1/efm32gg12b/Kconfig | 20 + .../silabs_s1/efm32gg12b/Kconfig.defconfig | 16 + soc/silabs/silabs_s1/efm32gg12b/Kconfig.soc | 22 + .../silabs_s1}/efm32gg12b/soc.h | 0 .../silabs_s1}/efm32gg12b/soc_pinmap.h | 0 soc/silabs/silabs_s1/efm32jg12b/Kconfig | 21 + .../silabs_s1/efm32jg12b/Kconfig.defconfig | 12 + soc/silabs/silabs_s1/efm32jg12b/Kconfig.soc | 23 + .../silabs_s1}/efm32jg12b/soc.h | 0 .../silabs_s1}/efm32jg12b/soc_pinmap.h | 0 soc/silabs/silabs_s1/efm32pg12b/Kconfig | 24 + .../silabs_s1/efm32pg12b/Kconfig.defconfig | 12 + soc/silabs/silabs_s1/efm32pg12b/Kconfig.soc | 23 + .../silabs_s1}/efm32pg12b/soc.h | 0 .../silabs_s1}/efm32pg12b/soc_pinmap.h | 0 soc/silabs/silabs_s1/efm32pg1b/Kconfig | 22 + .../silabs_s1/efm32pg1b/Kconfig.defconfig | 12 + soc/silabs/silabs_s1/efm32pg1b/Kconfig.soc | 23 + .../silabs_s1}/efm32pg1b/soc.h | 0 .../silabs_s1}/efm32pg1b/soc_pinmap.h | 0 soc/silabs/silabs_s1/efr32bg13p/Kconfig | 22 + .../silabs_s1/efr32bg13p/Kconfig.defconfig | 12 + soc/silabs/silabs_s1/efr32bg13p/Kconfig.soc | 23 + .../silabs_s1}/efr32bg13p/soc.h | 0 .../silabs_s1}/efr32bg13p/soc_pinmap.h | 0 soc/silabs/silabs_s1/efr32fg13p/Kconfig | 23 + .../silabs_s1/efr32fg13p/Kconfig.defconfig | 12 + soc/silabs/silabs_s1/efr32fg13p/Kconfig.soc | 23 + .../silabs_s1}/efr32fg13p/soc.h | 0 .../silabs_s1}/efr32fg13p/soc_pinmap.h | 0 soc/silabs/silabs_s1/efr32fg1p/Kconfig | 23 + .../silabs_s1/efr32fg1p/Kconfig.defconfig | 12 + soc/silabs/silabs_s1/efr32fg1p/Kconfig.soc | 23 + .../silabs_s1}/efr32fg1p/soc.h | 0 .../silabs_s1}/efr32fg1p/soc_pinmap.h | 0 soc/silabs/silabs_s1/efr32mg12p/Kconfig | 24 + .../silabs_s1/efr32mg12p/Kconfig.defconfig | 12 + soc/silabs/silabs_s1/efr32mg12p/Kconfig.soc | 35 + .../silabs_s1}/efr32mg12p/soc.h | 0 .../silabs_s1}/efr32mg12p/soc_pinmap.h | 0 soc/silabs/silabs_s2/Kconfig.soc | 8 + soc/silabs/silabs_s2/efr32bg22/Kconfig | 25 + .../silabs_s2/efr32bg22/Kconfig.defconfig | 19 + soc/silabs/silabs_s2/efr32bg22/Kconfig.soc | 23 + .../silabs_s2}/efr32bg22/soc.h | 0 soc/silabs/silabs_s2/efr32bg27/Kconfig | 24 + .../silabs_s2/efr32bg27/Kconfig.defconfig | 18 + soc/silabs/silabs_s2/efr32bg27/Kconfig.soc | 23 + .../silabs_s2}/efr32bg27/soc.h | 0 soc/silabs/silabs_s2/efr32mg21/Kconfig | 24 + .../silabs_s2/efr32mg21/Kconfig.defconfig | 17 + soc/silabs/silabs_s2/efr32mg21/Kconfig.soc | 23 + soc/silabs/silabs_s2/efr32mg21/soc.h | 28 + soc/silabs/silabs_s2/efr32mg21/soc_pinmap.h | 22 + soc/silabs/silabs_s2/efr32mg24/Kconfig | 26 + .../silabs_s2/efr32mg24/Kconfig.defconfig | 22 + soc/silabs/silabs_s2/efr32mg24/Kconfig.soc | 29 + soc/silabs/silabs_s2/efr32mg24/soc.h | 30 + soc/silabs/silabs_s2/efr32mg24/soc_pinmap.h | 22 + soc/silabs/soc.yml | 56 + soc/sparc/Kconfig | 8 - soc/sparc/gr716a/CMakeLists.txt | 5 - soc/sparc/gr716a/Kconfig.defconfig | 29 - soc/sparc/gr716a/Kconfig.soc | 8 - soc/sparc/leon3/CMakeLists.txt | 5 - soc/sparc/leon3/Kconfig.defconfig | 12 - soc/sparc/leon3/Kconfig.soc | 7 - soc/st/stm32/CMakeLists.txt | 5 + soc/st/stm32/Kconfig | 84 ++ soc/st/stm32/Kconfig.defconfig | 63 + soc/st/stm32/Kconfig.soc | 12 + soc/st/stm32/common/CMakeLists.txt | 13 + soc/{arm/st_stm32 => st/stm32}/common/ccm.ld | 0 .../stm32}/common/pinctrl_soc.h | 0 .../st_stm32 => st/stm32}/common/soc_config.c | 0 .../stm32}/common/stm32_backup_sram.c | 0 .../stm32}/common/stm32_backup_sram.ld | 0 .../st_stm32 => st/stm32}/common/stm32_hsem.h | 0 .../stm32}/common/stm32cube_hal.c | 0 soc/st/stm32/soc.yml | 192 +++ soc/st/stm32/stm32c0x/CMakeLists.txt | 10 + soc/st/stm32/stm32c0x/Kconfig | 12 + soc/st/stm32/stm32c0x/Kconfig.defconfig | 10 + .../stm32c0x}/Kconfig.defconfig.stm32c031xx | 3 - soc/st/stm32/stm32c0x/Kconfig.soc | 18 + .../stm32c0 => st/stm32/stm32c0x}/soc.c | 0 .../stm32c0 => st/stm32/stm32c0x}/soc.h | 0 soc/st/stm32/stm32f0x/CMakeLists.txt | 14 + soc/st/stm32/stm32f0x/Kconfig | 11 + soc/st/stm32/stm32f0x/Kconfig.defconfig | 20 + .../stm32f0x/Kconfig.defconfig.stm32f030x4 | 9 + .../stm32f0x}/Kconfig.defconfig.stm32f030x6 | 3 - .../stm32f0x}/Kconfig.defconfig.stm32f030x8 | 3 - .../stm32f0x}/Kconfig.defconfig.stm32f030xc | 3 - .../stm32f0x}/Kconfig.defconfig.stm32f031x6 | 3 - .../stm32f0x}/Kconfig.defconfig.stm32f042x6 | 3 - .../stm32f0x}/Kconfig.defconfig.stm32f051x8 | 3 - .../stm32f0x}/Kconfig.defconfig.stm32f070xb | 3 - .../stm32f0x}/Kconfig.defconfig.stm32f072xx | 3 - .../stm32f0x}/Kconfig.defconfig.stm32f091xc | 3 - .../stm32f0x}/Kconfig.defconfig.stm32f098xx | 3 - soc/st/stm32/stm32f0x/Kconfig.soc | 73 ++ .../stm32f0 => st/stm32/stm32f0x}/soc.c | 0 .../stm32f0 => st/stm32/stm32f0x}/soc.h | 0 .../stm32/stm32f0x}/sram_vector_table.ld | 0 soc/st/stm32/stm32f1x/CMakeLists.txt | 10 + soc/st/stm32/stm32f1x/Kconfig | 11 + soc/st/stm32/stm32f1x/Kconfig.defconfig | 17 + .../stm32f1x}/Kconfig.defconfig.stm32f100xx | 0 .../stm32f1x}/Kconfig.defconfig.stm32f103xx | 6 - .../stm32f1x}/Kconfig.defconfig.stm32f105xx | 4 - .../stm32f1x}/Kconfig.defconfig.stm32f107xc | 3 - soc/st/stm32/stm32f1x/Kconfig.soc | 76 ++ .../stm32f1 => st/stm32/stm32f1x}/soc.c | 0 .../stm32f1 => st/stm32/stm32f1x}/soc.h | 0 soc/st/stm32/stm32f2x/CMakeLists.txt | 10 + soc/st/stm32/stm32f2x/Kconfig | 12 + soc/st/stm32/stm32f2x/Kconfig.defconfig | 12 + .../stm32f2x/Kconfig.defconfig.stm32f205xx | 11 + .../stm32f2x/Kconfig.defconfig.stm32f207xx | 11 + soc/st/stm32/stm32f2x/Kconfig.soc | 23 + .../stm32f2 => st/stm32/stm32f2x}/soc.c | 0 .../stm32f2 => st/stm32/stm32f2x}/soc.h | 0 soc/st/stm32/stm32f3x/CMakeLists.txt | 10 + soc/st/stm32/stm32f3x/Kconfig | 12 + soc/st/stm32/stm32f3x/Kconfig.defconfig | 12 + .../stm32f3x/Kconfig.defconfig.stm32f302x8 | 11 + .../stm32f3x/Kconfig.defconfig.stm32f302xc | 14 + .../Kconfig.defconfig.stm32f303x(b-c) | 8 +- .../stm32f3x}/Kconfig.defconfig.stm32f303x8 | 5 +- .../stm32f3x/Kconfig.defconfig.stm32f303xe | 14 + .../stm32f3x/Kconfig.defconfig.stm32f334x8 | 11 + .../stm32f3x/Kconfig.defconfig.stm32f373xc | 14 + soc/st/stm32/stm32f3x/Kconfig.soc | 53 + .../stm32f3 => st/stm32/stm32f3x}/soc.c | 0 .../stm32f3 => st/stm32/stm32f3x}/soc.h | 0 soc/st/stm32/stm32f4x/CMakeLists.txt | 14 + soc/st/stm32/stm32f4x/Kconfig | 14 + soc/st/stm32/stm32f4x/Kconfig.defconfig | 30 + .../stm32f4x}/Kconfig.defconfig.stm32f401xc | 3 - .../stm32f4x}/Kconfig.defconfig.stm32f401xe | 3 - .../stm32f4x/Kconfig.defconfig.stm32f405xx | 11 + .../stm32f4x/Kconfig.defconfig.stm32f407xx | 11 + .../stm32f4x}/Kconfig.defconfig.stm32f410xx | 3 - .../stm32f4x}/Kconfig.defconfig.stm32f411xe | 3 - .../stm32f4x}/Kconfig.defconfig.stm32f412rx | 3 - .../stm32f4x/Kconfig.defconfig.stm32f412xx | 11 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| 3 - .../stm32f7x}/Kconfig.defconfig.stm32f756xx | 3 - .../stm32f7x}/Kconfig.defconfig.stm32f765xx | 8 +- .../stm32f7x}/Kconfig.defconfig.stm32f767xx | 6 +- .../stm32f7x}/Kconfig.defconfig.stm32f769xx | 6 +- soc/st/stm32/stm32f7x/Kconfig.soc | 61 + .../stm32f7 => st/stm32/stm32f7x}/soc.c | 0 .../stm32f7 => st/stm32/stm32f7x}/soc.h | 0 soc/st/stm32/stm32g0x/CMakeLists.txt | 15 + soc/st/stm32/stm32g0x/Kconfig | 14 + soc/st/stm32/stm32g0x/Kconfig.defconfig | 12 + .../stm32g0x}/Kconfig.defconfig.stm32g030xx | 3 - .../stm32g0x}/Kconfig.defconfig.stm32g031xx | 3 - .../stm32g0x}/Kconfig.defconfig.stm32g041xx | 3 - .../stm32g0x}/Kconfig.defconfig.stm32g050xx | 3 - .../stm32g0x}/Kconfig.defconfig.stm32g051xx | 3 - .../stm32g0x}/Kconfig.defconfig.stm32g061xx | 3 - .../stm32g0x}/Kconfig.defconfig.stm32g070xx | 3 - .../stm32g0x}/Kconfig.defconfig.stm32g071xx | 3 - .../stm32g0x}/Kconfig.defconfig.stm32g081xx | 3 - .../stm32g0x}/Kconfig.defconfig.stm32g0b0xx | 3 - .../stm32g0x}/Kconfig.defconfig.stm32g0b1xx | 3 - .../stm32g0x}/Kconfig.defconfig.stm32g0c1xx | 3 - soc/st/stm32/stm32g0x/Kconfig.soc | 75 ++ .../stm32g0 => st/stm32/stm32g0x}/power.c | 0 .../stm32g0 => st/stm32/stm32g0x}/soc.c | 0 .../stm32g0 => st/stm32/stm32g0x}/soc.h | 0 soc/st/stm32/stm32g4x/CMakeLists.txt | 13 + soc/st/stm32/stm32g4x/Kconfig | 15 + soc/st/stm32/stm32g4x/Kconfig.defconfig | 18 + .../stm32g4x/Kconfig.defconfig.stm32g431xx | 11 + .../stm32g4x}/Kconfig.defconfig.stm32g441xx | 3 - .../stm32g4x}/Kconfig.defconfig.stm32g473xx | 3 - .../stm32g4x/Kconfig.defconfig.stm32g474xx | 11 + .../stm32g4x}/Kconfig.defconfig.stm32g483xx | 3 - .../stm32g4x}/Kconfig.defconfig.stm32g484xx | 3 - .../stm32g4x}/Kconfig.defconfig.stm32g491xx | 3 - .../stm32g4x}/Kconfig.defconfig.stm32g4a1xx | 3 - soc/st/stm32/stm32g4x/Kconfig.soc | 53 + .../stm32g4 => st/stm32/stm32g4x}/power.c | 0 soc/st/stm32/stm32g4x/soc.c | 48 + .../stm32g4 => st/stm32/stm32g4x}/soc.h | 0 soc/st/stm32/stm32h5x/CMakeLists.txt | 10 + soc/st/stm32/stm32h5x/Kconfig | 16 + soc/st/stm32/stm32h5x/Kconfig.defconfig | 13 + .../stm32h5x}/Kconfig.defconfig.stm32h503xx | 3 - .../stm32h5x}/Kconfig.defconfig.stm32h562xx | 3 - .../stm32h5x}/Kconfig.defconfig.stm32h563xx | 3 - .../stm32h5x}/Kconfig.defconfig.stm32h573xx | 3 - soc/st/stm32/stm32h5x/Kconfig.soc | 33 + .../stm32h5 => st/stm32/stm32h5x}/soc.c | 0 .../stm32h5 => st/stm32/stm32h5x}/soc.h | 0 soc/st/stm32/stm32h7x/CMakeLists.txt | 13 + soc/st/stm32/stm32h7x/Kconfig | 82 ++ soc/st/stm32/stm32h7x/Kconfig.defconfig | 17 + .../stm32h7x}/Kconfig.defconfig.stm32h723xx | 3 - .../stm32h7x}/Kconfig.defconfig.stm32h725xx | 3 - .../stm32h7x}/Kconfig.defconfig.stm32h730xx | 4 - .../stm32h7x}/Kconfig.defconfig.stm32h735xx | 3 - .../stm32h7x}/Kconfig.defconfig.stm32h743xx | 3 - .../stm32h7x/Kconfig.defconfig.stm32h745xx | 14 + .../stm32h7x/Kconfig.defconfig.stm32h747xx | 14 + .../stm32h7x}/Kconfig.defconfig.stm32h750xx | 3 - .../stm32h7x}/Kconfig.defconfig.stm32h753xx | 3 - .../stm32h7x/Kconfig.defconfig.stm32h7a3xx | 11 + .../stm32h7x/Kconfig.defconfig.stm32h7b0xx | 11 + .../stm32h7x/Kconfig.defconfig.stm32h7b3xx | 11 + soc/st/stm32/stm32h7x/Kconfig.soc | 103 ++ .../stm32/stm32h7x}/mpu_regions.c | 0 .../stm32h7 => st/stm32/stm32h7x}/sections.ld | 0 .../stm32h7 => st/stm32/stm32h7x}/soc.h | 0 .../stm32h7 => st/stm32/stm32h7x}/soc_m4.c | 0 .../stm32h7 => st/stm32/stm32h7x}/soc_m7.c | 0 soc/st/stm32/stm32l0x/CMakeLists.txt | 14 + soc/st/stm32/stm32l0x/Kconfig | 30 + soc/st/stm32/stm32l0x/Kconfig.defconfig | 17 + .../stm32l0x}/Kconfig.defconfig.stm32l010x4 | 3 - .../stm32l0x}/Kconfig.defconfig.stm32l010x6 | 3 - .../stm32l0x}/Kconfig.defconfig.stm32l010x8 | 3 - .../stm32l0x}/Kconfig.defconfig.stm32l010xb | 3 - .../stm32l0x}/Kconfig.defconfig.stm32l011xx | 3 - .../stm32l0x}/Kconfig.defconfig.stm32l031xx | 3 - .../stm32l0x}/Kconfig.defconfig.stm32l051xx | 3 - .../stm32l0x}/Kconfig.defconfig.stm32l053xx | 3 - .../stm32l0x}/Kconfig.defconfig.stm32l071xx | 3 - .../stm32l0x}/Kconfig.defconfig.stm32l072xx | 3 - .../stm32l0x}/Kconfig.defconfig.stm32l073xx | 3 - .../stm32l0x}/Kconfig.defconfig.stm32l081xx | 3 - soc/st/stm32/stm32l0x/Kconfig.soc | 76 ++ .../stm32l0 => st/stm32/stm32l0x}/power.c | 0 .../stm32l0 => st/stm32/stm32l0x}/soc.c | 0 .../stm32l0 => st/stm32/stm32l0x}/soc.h | 0 soc/st/stm32/stm32l1x/CMakeLists.txt | 8 + soc/st/stm32/stm32l1x/Kconfig | 12 + soc/st/stm32/stm32l1x/Kconfig.defconfig | 15 + .../stm32l1x/Kconfig.defconfig.stm32l151xb | 11 + .../stm32l1x/Kconfig.defconfig.stm32l151xba | 11 + .../stm32l1x/Kconfig.defconfig.stm32l151xc | 12 + .../stm32l1x/Kconfig.defconfig.stm32l152xc | 12 + .../stm32l1x}/Kconfig.defconfig.stm32l152xe | 4 - soc/st/stm32/stm32l1x/Kconfig.soc | 38 + .../stm32l1 => st/stm32/stm32l1x}/soc.c | 0 .../stm32l1 => st/stm32/stm32l1x}/soc.h | 0 soc/st/stm32/stm32l4x/CMakeLists.txt | 16 + soc/st/stm32/stm32l4x/Kconfig | 16 + soc/st/stm32/stm32l4x/Kconfig.defconfig | 13 + .../stm32l4x}/Kconfig.defconfig.stm32l412xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l422xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l431xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l432xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l433xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l451xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l452xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l462xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l471xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l475xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l476xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l486xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l496xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l4a6xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l4p5xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l4q5xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l4r5xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l4r9xx | 3 - .../stm32l4x}/Kconfig.defconfig.stm32l4s5xx | 3 - soc/st/stm32/stm32l4x/Kconfig.soc | 111 ++ .../stm32l4 => st/stm32/stm32l4x}/power.c | 0 .../stm32l4 => st/stm32/stm32l4x}/poweroff.c | 0 .../stm32l4 => st/stm32/stm32l4x}/soc.c | 0 .../stm32l4 => st/stm32/stm32l4x}/soc.h | 0 soc/st/stm32/stm32l5x/CMakeLists.txt | 14 + soc/st/stm32/stm32l5x/Kconfig | 16 + soc/st/stm32/stm32l5x/Kconfig.defconfig | 13 + .../stm32l5x}/Kconfig.defconfig.stm32l552xx | 3 - .../stm32l5x}/Kconfig.defconfig.stm32l562xx | 3 - soc/st/stm32/stm32l5x/Kconfig.soc | 23 + .../stm32l5 => st/stm32/stm32l5x}/power.c | 0 .../stm32l5 => st/stm32/stm32l5x}/soc.c | 0 .../stm32l5 => st/stm32/stm32l5x}/soc.h | 0 soc/st/stm32/stm32mp1x/CMakeLists.txt | 12 + soc/st/stm32/stm32mp1x/Kconfig | 13 + soc/st/stm32/stm32mp1x/Kconfig.defconfig | 10 + .../stm32mp1x/Kconfig.defconfig.stm32mp15_m4 | 11 + soc/st/stm32/stm32mp1x/Kconfig.soc | 18 + .../stm32mp1 => st/stm32/stm32mp1x}/linker.ld | 0 .../stm32mp1 => st/stm32/stm32mp1x}/soc.c | 0 .../stm32mp1 => st/stm32/stm32mp1x}/soc.h | 0 soc/st/stm32/stm32u5x/CMakeLists.txt | 13 + soc/st/stm32/stm32u5x/Kconfig | 17 + soc/st/stm32/stm32u5x/Kconfig.defconfig | 13 + .../stm32u5x}/Kconfig.defconfig.stm32u575xx | 3 - .../stm32u5x}/Kconfig.defconfig.stm32u585xx | 3 - .../stm32u5x}/Kconfig.defconfig.stm32u595xx | 3 - .../stm32u5x}/Kconfig.defconfig.stm32u599xx | 3 - .../stm32u5x}/Kconfig.defconfig.stm32u5a5xx | 3 - .../stm32u5x}/Kconfig.defconfig.stm32u5a9xx | 3 - soc/st/stm32/stm32u5x/Kconfig.soc | 45 + .../stm32u5 => st/stm32/stm32u5x}/power.c | 0 .../stm32u5 => st/stm32/stm32u5x}/poweroff.c | 0 .../stm32u5 => st/stm32/stm32u5x}/soc.c | 0 .../stm32u5 => st/stm32/stm32u5x}/soc.h | 0 soc/st/stm32/stm32wbax/CMakeLists.txt | 24 + soc/st/stm32/stm32wbax/Kconfig | 17 + soc/st/stm32/stm32wbax/Kconfig.defconfig | 61 + .../stm32wbax}/Kconfig.defconfig.stm32wba52xx | 3 - .../stm32wbax}/Kconfig.defconfig.stm32wba55xx | 3 - soc/st/stm32/stm32wbax/Kconfig.soc | 23 + .../stm32/stm32wbax}/hci_if/bleplat.c | 0 .../stm32/stm32wbax}/hci_if/host_stack_if.c | 0 .../stm32/stm32wbax}/hci_if/linklayer_plat.c | 0 .../stm32wbax}/hci_if/linklayer_plat_local.h | 0 .../stm32/stm32wbax}/hci_if/ll_sys_if.c | 0 .../stm32/stm32wbax}/hci_if/stm32_timer.c | 0 .../stm32wba => st/stm32/stm32wbax}/power.c | 0 .../stm32wba => st/stm32/stm32wbax}/soc.c | 0 .../stm32wba => st/stm32/stm32wbax}/soc.h | 0 soc/st/stm32/stm32wbx/CMakeLists.txt | 19 + soc/st/stm32/stm32wbx/Kconfig | 15 + soc/st/stm32/stm32wbx/Kconfig.defconfig | 13 + .../stm32wbx}/Kconfig.defconfig.stm32wb55xx | 3 - soc/st/stm32/stm32wbx/Kconfig.soc | 18 + .../stm32wb => st/stm32/stm32wbx}/ipm.ld | 0 .../stm32wb => st/stm32/stm32wbx}/power.c | 0 .../stm32wb => st/stm32/stm32wbx}/poweroff.c | 0 .../stm32wb => st/stm32/stm32wbx}/soc.c | 0 .../stm32wb => st/stm32/stm32wbx}/soc.h | 0 soc/st/stm32/stm32wlx/CMakeLists.txt | 14 + soc/st/stm32/stm32wlx/Kconfig | 14 + soc/st/stm32/stm32wlx/Kconfig.defconfig | 10 + .../stm32wlx}/Kconfig.defconfig.stm32wl54xx | 3 - .../stm32wlx}/Kconfig.defconfig.stm32wl55xx | 3 - .../stm32wlx}/Kconfig.defconfig.stm32wle4xx | 3 - .../stm32wlx}/Kconfig.defconfig.stm32wle5xx | 3 - soc/st/stm32/stm32wlx/Kconfig.soc | 33 + .../stm32wl => st/stm32/stm32wlx}/power.c | 0 .../stm32wl => st/stm32/stm32wlx}/poweroff.c | 0 .../stm32wl => st/stm32/stm32wlx}/soc.c | 0 .../stm32wl => st/stm32/stm32wlx}/soc.h | 0 .../jh71xx/CMakeLists.txt | 0 soc/starfive/jh71xx/Kconfig | 17 + soc/starfive/jh71xx/Kconfig.defconfig | 24 + soc/starfive/jh71xx/Kconfig.soc | 19 + soc/starfive/jh71xx/soc.yml | 4 + .../arc_iot}/CMakeLists.txt | 0 soc/synopsys/arc_iot/Kconfig | 8 + soc/synopsys/arc_iot/Kconfig.defconfig | 34 + soc/synopsys/arc_iot/Kconfig.soc | 11 + .../arc_iot}/linker.ld | 0 .../snps_arc_iot => synopsys/arc_iot}/soc.c | 0 soc/synopsys/arc_iot/soc.yml | 4 + .../arc_iot}/sysconf.c | 0 .../arc_iot}/sysconf.h | 0 soc/synopsys/emsdp/CMakeLists.txt | 24 + soc/synopsys/emsdp/Kconfig | 32 + soc/synopsys/emsdp/Kconfig.defconfig | 13 + .../emsdp}/Kconfig.defconfig.em11d | 0 .../emsdp}/Kconfig.defconfig.em4 | 0 .../emsdp}/Kconfig.defconfig.em5d | 0 .../emsdp}/Kconfig.defconfig.em6 | 0 .../emsdp}/Kconfig.defconfig.em7d | 0 .../emsdp}/Kconfig.defconfig.em7d_esp | 0 .../emsdp}/Kconfig.defconfig.em9d | 0 soc/synopsys/emsdp/Kconfig.soc | 59 + .../snps_emsdp => synopsys/emsdp}/linker.ld | 0 .../emsdp}/pinctrl_soc.h | 0 soc/synopsys/emsdp/soc.yml | 10 + soc/synopsys/emsk/CMakeLists.txt | 12 + soc/synopsys/emsk/Kconfig | 15 + soc/synopsys/emsk/Kconfig.defconfig | 9 + .../emsk}/Kconfig.defconfig.em11d | 4 +- soc/synopsys/emsk/Kconfig.defconfig.em7d | 55 + .../emsk}/Kconfig.defconfig.em9d | 4 +- soc/synopsys/emsk/Kconfig.soc | 34 + .../snps_emsk => synopsys/emsk}/linker.ld | 0 soc/synopsys/emsk/soc.yml | 6 + .../snps_emsk => synopsys/emsk}/soc_config.c | 0 .../hsdk}/CMakeLists.txt | 0 soc/synopsys/hsdk/Kconfig | 6 + soc/synopsys/hsdk/Kconfig.defconfig | 46 + soc/synopsys/hsdk/Kconfig.soc | 8 + .../snps_arc_hsdk => synopsys/hsdk}/linker.ld | 0 soc/synopsys/hsdk/soc.yml | 4 + soc/synopsys/hsdk4xd/CMakeLists.txt | 20 + soc/synopsys/hsdk4xd/Kconfig | 7 + soc/synopsys/hsdk4xd/Kconfig.defconfig | 53 + soc/synopsys/hsdk4xd/Kconfig.soc | 10 + .../hsdk4xd}/linker.ld | 0 soc/synopsys/hsdk4xd/soc.yml | 4 + .../hsdk4xd}/soc_ctrl.h | 1 - .../hsdk4xd}/tune_build_ops.cmake | 0 .../nsim}/CMakeLists.txt | 0 soc/synopsys/nsim/Kconfig | 32 + soc/synopsys/nsim/Kconfig.defconfig | 11 + .../nsim}/Kconfig.defconfig.em | 0 .../nsim}/Kconfig.defconfig.em11d | 0 .../nsim}/Kconfig.defconfig.em7d_v22 | 0 .../nsim}/Kconfig.defconfig.hs | 0 .../nsim}/Kconfig.defconfig.hs5x | 0 .../nsim}/Kconfig.defconfig.hs5x_smp | 0 .../nsim}/Kconfig.defconfig.hs6x | 0 .../nsim}/Kconfig.defconfig.hs6x_smp | 0 .../nsim}/Kconfig.defconfig.hs_mpuv6 | 0 .../nsim}/Kconfig.defconfig.hs_smp | 0 .../nsim}/Kconfig.defconfig.sem | 0 .../nsim}/Kconfig.defconfig.vpx5 | 0 soc/synopsys/nsim/Kconfig.soc | 94 ++ .../snps_nsim => synopsys/nsim}/linker.ld | 0 soc/synopsys/nsim/soc.yml | 15 + soc/synopsys/qemu_arc/CMakeLists.txt | 20 + soc/synopsys/qemu_arc/Kconfig | 18 + soc/synopsys/qemu_arc/Kconfig.defconfig | 29 + soc/synopsys/qemu_arc/Kconfig.soc | 30 + .../snps_qemu => synopsys/qemu_arc}/linker.ld | 0 soc/synopsys/qemu_arc/soc.yml | 7 + .../tlsr}/CMakeLists.txt | 0 soc/telink/tlsr/Kconfig | 8 + soc/telink/tlsr/Kconfig.defconfig | 8 + soc/telink/tlsr/Kconfig.soc | 10 + soc/telink/tlsr/soc.yml | 6 + soc/telink/tlsr/tlsr951x/CMakeLists.txt | 20 + soc/telink/tlsr/tlsr951x/Kconfig | 31 + soc/telink/tlsr/tlsr951x/Kconfig.defconfig | 47 + soc/telink/tlsr/tlsr951x/Kconfig.soc | 20 + .../tlsr}/tlsr951x/init.ld | 0 .../tlsr}/tlsr951x/linker.ld | 0 .../tlsr}/tlsr951x/pinctrl_soc.h | 0 .../tlsr}/tlsr951x/soc.c | 0 .../tlsr}/tlsr951x/soc.h | 0 .../tlsr}/tlsr951x/soc_context.h | 0 .../tlsr}/tlsr951x/soc_irq.S | 0 .../tlsr}/tlsr951x/soc_offsets.h | 0 .../tlsr}/tlsr951x/start.S | 0 soc/ti/k3/CMakeLists.txt | 4 + soc/ti/k3/Kconfig | 8 + soc/ti/k3/Kconfig.defconfig | 8 + soc/ti/k3/Kconfig.soc | 10 + soc/ti/k3/am6x/CMakeLists.txt | 21 + soc/ti/k3/am6x/Kconfig | 23 + soc/ti/k3/am6x/Kconfig.defconfig | 45 + soc/ti/k3/am6x/Kconfig.soc | 32 + .../am6x => ti/k3/am6x/a53}/mmu_regions.c | 0 .../am62x_m4 => ti/k3/am6x/m4}/linker.ld | 0 .../ti_k3/am62x_m4 => ti/k3/am6x/m4}/soc.c | 0 .../ti_k3/am62x_m4 => ti/k3/am6x/m4}/soc.h | 0 soc/{arm64/ti_k3 => ti/k3/am6x}/pinctrl_soc.h | 0 soc/ti/k3/soc.yml | 9 + soc/ti/lm3s6965/CMakeLists.txt | 18 + soc/ti/lm3s6965/Kconfig | 7 + soc/ti/lm3s6965/Kconfig.defconfig | 29 + soc/ti/lm3s6965/Kconfig.soc | 16 + soc/{arm/ti_lm3s6965 => ti/lm3s6965}/reboot.S | 0 soc/{arm/ti_lm3s6965 => ti/lm3s6965}/soc.h | 0 soc/ti/lm3s6965/soc.yml | 2 + .../ti_lm3s6965 => ti/lm3s6965}/soc_config.c | 0 .../lm3s6965}/sys_arch_reboot.c | 0 soc/ti/simplelink/CMakeLists.txt | 4 + soc/ti/simplelink/Kconfig | 15 + soc/ti/simplelink/Kconfig.defconfig | 8 + soc/ti/simplelink/Kconfig.soc | 11 + .../simplelink/cc13x2_cc26x2/CMakeLists.txt | 16 + soc/ti/simplelink/cc13x2_cc26x2/Kconfig | 62 + .../cc13x2_cc26x2/Kconfig.defconfig | 41 + soc/ti/simplelink/cc13x2_cc26x2/Kconfig.soc | 43 + .../simplelink}/cc13x2_cc26x2/ccfg.c | 0 .../simplelink}/cc13x2_cc26x2/ccfg.ld | 0 .../simplelink}/cc13x2_cc26x2/pinctrl_soc.h | 0 .../simplelink}/cc13x2_cc26x2/power.c | 0 .../simplelink}/cc13x2_cc26x2/poweroff.c | 0 .../simplelink}/cc13x2_cc26x2/soc.c | 0 .../simplelink}/cc13x2_cc26x2/soc.h | 0 .../cc13x2x7_cc26x2x7/CMakeLists.txt | 15 + soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig | 69 ++ .../cc13x2x7_cc26x2x7/Kconfig.defconfig | 41 + .../simplelink/cc13x2x7_cc26x2x7/Kconfig.soc | 42 + .../simplelink}/cc13x2x7_cc26x2x7/ccfg.c | 0 .../simplelink}/cc13x2x7_cc26x2x7/ccfg.ld | 0 .../cc13x2x7_cc26x2x7/pinctrl_soc.h | 0 .../simplelink}/cc13x2x7_cc26x2x7/power.c | 0 .../simplelink}/cc13x2x7_cc26x2x7/soc.c | 0 .../simplelink}/cc13x2x7_cc26x2x7/soc.h | 0 soc/ti/simplelink/cc32xx/CMakeLists.txt | 11 + soc/ti/simplelink/cc32xx/Kconfig | 25 + soc/ti/simplelink/cc32xx/Kconfig.defconfig | 9 + .../cc32xx/Kconfig.defconfig.cc3220sf | 7 +- .../cc32xx/Kconfig.defconfig.cc3235sf | 6 +- soc/ti/simplelink/cc32xx/Kconfig.soc | 28 + .../simplelink}/cc32xx/README | 0 .../simplelink}/cc32xx/cc32xx_debug.ld | 0 .../simplelink}/cc32xx/pinctrl_soc.h | 0 .../simplelink}/cc32xx/soc.c | 0 .../simplelink}/cc32xx/soc.h | 0 soc/ti/simplelink/msp432p4xx/CMakeLists.txt | 7 + soc/ti/simplelink/msp432p4xx/Kconfig | 14 + .../simplelink/msp432p4xx/Kconfig.defconfig | 9 + .../msp432p4xx/Kconfig.defconfig.msp432p401r | 4 - soc/ti/simplelink/msp432p4xx/Kconfig.soc | 21 + .../simplelink}/msp432p4xx/soc.c | 0 .../simplelink}/msp432p4xx/soc.h | 0 soc/ti/simplelink/soc.yml | 22 + soc/x86/alder_lake/CMakeLists.txt | 10 - soc/x86/alder_lake/Kconfig.defconfig | 19 - soc/x86/alder_lake/Kconfig.soc | 11 - soc/x86/apollo_lake/CMakeLists.txt | 10 - soc/x86/apollo_lake/Kconfig.defconfig | 29 - soc/x86/apollo_lake/Kconfig.soc | 12 - soc/x86/atom/CMakeLists.txt | 3 - soc/x86/atom/Kconfig.defconfig | 14 - soc/x86/atom/Kconfig.soc | 9 - soc/x86/atom/soc.h | 60 - soc/x86/elkhart_lake/CMakeLists.txt | 10 - soc/x86/elkhart_lake/Kconfig.defconfig | 19 - soc/x86/elkhart_lake/Kconfig.soc | 11 - soc/x86/ia32/CMakeLists.txt | 3 - soc/x86/ia32/Kconfig.defconfig | 14 - soc/x86/ia32/Kconfig.soc | 9 - soc/x86/ia32/soc.h | 58 - soc/x86/intel_ish/Kconfig | 16 - soc/x86/intel_ish/Kconfig.defconfig | 30 - soc/x86/intel_ish/Kconfig.soc | 8 - soc/x86/intel_ish/intel_ish5/CMakeLists.txt | 13 - .../intel_ish5/Kconfig.defconfig.series | 20 - soc/x86/intel_ish/intel_ish5/Kconfig.series | 8 - soc/x86/intel_ish/intel_ish5/Kconfig.soc | 19 - soc/x86/lakemont/CMakeLists.txt | 7 - soc/x86/lakemont/Kconfig.defconfig | 23 - soc/x86/lakemont/Kconfig.soc | 14 - soc/x86/lakemont/linker.ld | 8 - soc/x86/raptor_lake/CMakeLists.txt | 5 - soc/x86/raptor_lake/Kconfig.defconfig | 18 - soc/x86/raptor_lake/Kconfig.soc | 11 - soc/{arm64/xenvm => xen}/CMakeLists.txt | 0 soc/xen/Kconfig | 7 + soc/xen/Kconfig.defconfig | 19 + soc/xen/Kconfig.soc | 8 + soc/{arm64/xenvm => xen}/mmu_regions.c | 0 soc/xen/soc.yml | 4 + .../zynq7000}/CMakeLists.txt | 0 soc/xlnx/zynq7000/Kconfig | 10 + soc/xlnx/zynq7000/Kconfig.defconfig | 27 + soc/xlnx/zynq7000/Kconfig.soc | 12 + .../zynq7000}/common/pinctrl_soc.h | 0 soc/xlnx/zynq7000/soc.yml | 18 + soc/xlnx/zynq7000/xc7zxxx/CMakeLists.txt | 10 + soc/xlnx/zynq7000/xc7zxxx/Kconfig | 12 + soc/xlnx/zynq7000/xc7zxxx/Kconfig.defconfig | 12 + soc/xlnx/zynq7000/xc7zxxx/Kconfig.soc | 80 ++ .../zynq7000}/xc7zxxx/soc.c | 0 .../zynq7000}/xc7zxxx/soc.h | 0 soc/xlnx/zynq7000/xc7zxxxs/CMakeLists.txt | 10 + soc/xlnx/zynq7000/xc7zxxxs/Kconfig | 12 + soc/xlnx/zynq7000/xc7zxxxs/Kconfig.defconfig | 11 + soc/xlnx/zynq7000/xc7zxxxs/Kconfig.soc | 44 + .../zynq7000}/xc7zxxxs/soc.c | 0 .../zynq7000}/xc7zxxxs/soc.h | 0 soc/xlnx/zynqmp/CMakeLists.txt | 17 + soc/xlnx/zynqmp/Kconfig | 10 + soc/xlnx/zynqmp/Kconfig.defconfig | 28 + soc/xlnx/zynqmp/Kconfig.soc | 18 + .../zynqmp}/arm_mpu_regions.c | 0 .../zynqmp}/pinctrl_soc.h | 0 soc/{arm/xilinx_zynqmp => xlnx/zynqmp}/soc.c | 0 soc/{arm/xilinx_zynqmp => xlnx/zynqmp}/soc.h | 0 soc/xlnx/zynqmp/soc.yml | 4 + soc/xtensa/CMakeLists.txt | 7 - soc/xtensa/dc233c/Kconfig.defconfig | 32 - soc/xtensa/dc233c/Kconfig.soc | 15 - soc/xtensa/espressif_esp32/CMakeLists.txt | 5 - soc/xtensa/espressif_esp32/Kconfig | 16 - soc/xtensa/espressif_esp32/Kconfig.defconfig | 5 - soc/xtensa/espressif_esp32/Kconfig.soc | 4 - .../espressif_esp32/common/CMakeLists.txt | 4 - .../common/Kconfig.defconfig.series | 44 - soc/xtensa/espressif_esp32/common/Kconfig.soc | 215 ---- .../espressif_esp32/esp32/CMakeLists.txt | 123 -- .../esp32/Kconfig.defconfig.series | 49 - .../espressif_esp32/esp32/Kconfig.series | 33 - soc/xtensa/espressif_esp32/esp32/Kconfig.soc | 281 ----- soc/xtensa/espressif_esp32/esp32/default.ld | 583 --------- soc/xtensa/espressif_esp32/esp32/soc.c | 266 ---- .../espressif_esp32/esp32s2/CMakeLists.txt | 101 -- .../esp32s2/Kconfig.defconfig.series | 30 - .../espressif_esp32/esp32s2/Kconfig.series | 18 - .../espressif_esp32/esp32s2/Kconfig.soc | 259 ---- .../espressif_esp32/esp32s3/CMakeLists.txt | 122 -- .../esp32s3/Kconfig.defconfig.series | 27 - .../espressif_esp32/esp32s3/Kconfig.series | 28 - .../espressif_esp32/esp32s3/Kconfig.soc | 332 ----- soc/xtensa/espressif_esp32/esp32s3/default.ld | 693 ----------- soc/xtensa/espressif_esp32/esp32s3/soc.c | 322 ----- soc/xtensa/intel_adsp/CMakeLists.txt | 13 - soc/xtensa/intel_adsp/Kconfig | 138 --- soc/xtensa/intel_adsp/Kconfig.defconfig | 44 - soc/xtensa/intel_adsp/Kconfig.soc | 6 - soc/xtensa/intel_adsp/ace/CMakeLists.txt | 22 - .../ace/Kconfig.defconfig.ace15_mtpm | 14 - .../ace/Kconfig.defconfig.ace20_lnl | 14 - .../intel_adsp/ace/Kconfig.defconfig.series | 73 -- soc/xtensa/intel_adsp/ace/Kconfig.series | 16 - soc/xtensa/intel_adsp/ace/Kconfig.soc | 23 - soc/xtensa/intel_adsp/cavs/CMakeLists.txt | 22 - .../intel_adsp/cavs/Kconfig.defconfig.series | 50 - soc/xtensa/intel_adsp/cavs/Kconfig.series | 16 - soc/xtensa/intel_adsp/cavs/Kconfig.soc | 13 - soc/xtensa/intel_adsp/common/CMakeLists.txt | 149 --- soc/xtensa/nxp_adsp/CMakeLists.txt | 27 - soc/xtensa/nxp_adsp/Kconfig | 20 - soc/xtensa/nxp_adsp/Kconfig.defconfig | 33 - soc/xtensa/nxp_adsp/Kconfig.soc | 6 - soc/xtensa/nxp_adsp/common/CMakeLists.txt | 6 - .../nxp_adsp/imx8/Kconfig.defconfig.imx8qm | 9 - .../nxp_adsp/imx8/Kconfig.defconfig.imx8qxp | 9 - .../nxp_adsp/imx8/Kconfig.defconfig.series | 28 - soc/xtensa/nxp_adsp/imx8/Kconfig.series | 15 - soc/xtensa/nxp_adsp/imx8/Kconfig.soc | 28 - soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qm | 17 - soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qxp | 21 - .../nxp_adsp/imx8m/Kconfig.defconfig.series | 37 - soc/xtensa/nxp_adsp/imx8m/Kconfig.series | 15 - soc/xtensa/nxp_adsp/imx8m/Kconfig.soc | 38 - .../nxp_adsp/imx8ulp/Kconfig.defconfig.series | 30 - soc/xtensa/nxp_adsp/imx8ulp/Kconfig.series | 15 - soc/xtensa/nxp_adsp/imx8ulp/Kconfig.soc | 11 - .../nxp_adsp/rt5xx/Kconfig.defconfig.series | 46 - soc/xtensa/nxp_adsp/rt5xx/Kconfig.series | 12 - soc/xtensa/nxp_adsp/rt5xx/Kconfig.soc | 10 - .../sample_controller/Kconfig.defconfig | 16 - soc/xtensa/sample_controller/Kconfig.soc | 8 - submanifests/optional.yaml | 4 +- subsys/bluetooth/controller/CMakeLists.txt | 4 +- subsys/bluetooth/controller/Kconfig | 6 +- .../bluetooth/controller/Kconfig.ll_sw_split | 4 +- subsys/bluetooth/controller/hci/hci_driver.c | 4 +- .../controller/ll_sw/nordic/hal/nrf5/debug.h | 2 +- .../controller/ll_sw/openisa/lll/lll_conn.c | 4 +- subsys/bluetooth/host/hci_core.c | 1 - subsys/testsuite/Kconfig | 6 +- subsys/testsuite/arch/Kconfig.v1 | 4 + .../unit_testing/unit_testing/Kconfig.board | 0 .../unit_testing/Kconfig.defconfig | 0 .../unit_testing/unit_testing_defconfig | 0 .../unit_testing/unit_testing/Kconfig.soc | 0 .../code_relocation/testcase.yaml | 4 +- tests/arch/arc/arc_dsp_sharing/testcase.yaml | 4 +- .../src/arm_irq_vector_table.c | 17 +- .../arm_irq_zero_latency_levels/testcase.yaml | 6 +- .../arm/arm_no_multithreading/testcase.yaml | 12 +- .../arm/arm_sw_vector_relay/testcase.yaml | 2 +- ...=> nucleo_l552ze_q_stm32l552xx_ns.overlay} | 0 .../arch/arm/arm_thread_swap_tz/testcase.yaml | 12 +- tests/arch/arm/arm_tz_wrap_func/testcase.yaml | 2 +- tests/arch/arm64/arm64_smc_call/testcase.yaml | 2 +- ...rty_a7_designstart_fpga_cortex_m1.overlay} | 0 tests/benchmarks/app_kernel/testcase.yaml | 8 +- .../cmsis_dsp/basicmath/testcase.yaml | 8 +- tests/benchmarks/footprints/testcase.yaml | 6 +- .../{atsame54_xpro.conf => same54_xpro.conf} | 0 .../benchmarks/latency_measure/testcase.yaml | 6 +- tests/benchmarks/sched/testcase.yaml | 2 +- tests/bluetooth/adv/testcase.yaml | 6 +- tests/bluetooth/ctrl_user_ext/CMakeLists.txt | 2 +- .../df/connection_cte_req/CMakeLists.txt | 2 +- .../connection_cte_tx_params/CMakeLists.txt | 2 +- .../df/connectionless_cte_rx/CMakeLists.txt | 2 +- .../df/connectionless_cte_tx/CMakeLists.txt | 2 +- tests/bluetooth/init/testcase.yaml | 292 ++--- tests/bluetooth/mesh/basic/testcase.yaml | 18 +- tests/bluetooth/mesh_shell/testcase.yaml | 4 +- tests/bluetooth/shell/testcase.yaml | 10 +- tests/bluetooth/tester/testcase.yaml | 6 +- .../espressif_esp32/cache_coex/testcase.yaml | 4 +- tests/boards/intel_adsp/cache/testcase.yaml | 4 +- tests/boards/intel_adsp/hda/testcase.yaml | 4 +- tests/boards/intel_adsp/mm/testcase.yaml | 2 +- tests/boards/intel_adsp/smoke/testcase.yaml | 4 +- tests/boards/intel_adsp/ssp/testcase.yaml | 4 +- tests/boards/nrf52_bsim/egu/testcase.yaml | 2 +- tests/boot/mcuboot_data_sharing/testcase.yaml | 2 +- .../mcuboot_recovery_retention/testcase.yaml | 4 +- tests/boot/test_mcuboot/testcase.yaml | 14 +- tests/boot/with_mcumgr/README.rst | 4 +- tests/boot/with_mcumgr/testcase.yaml | 8 +- tests/crypto/rand32/testcase.yaml | 2 +- tests/crypto/tinycrypt/testcase.yaml | 4 +- ...rduino_nano_33_ble_nrf52840_sense.overlay} | 0 ...r_k64.overlay => hexiwear_mk64f12.overlay} | 0 ...kw40z.overlay => hexiwear_mkw40z4.overlay} | 0 ...> mimxrt1170_evk_mimxrt1176_cm7_A.overlay} | 0 ...> mimxrt1170_evk_mimxrt1176_cm7_B.overlay} | 0 ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 ...dk_nrf51422.conf => nrf51dk_nrf51822.conf} | 0 ...51422.overlay => nrf51dk_nrf51822.overlay} | 0 ...co_w.overlay => rpi_pico_rp2040_w.overlay} | 0 .../adc/adc_api/boards/sam4e_xpro.overlay | 25 + ...lay => sam_e70_xplained_same70q21.overlay} | 0 ...ay => sam_e70_xplained_same70q21b.overlay} | 0 ...overlay => sam_v71_xult_samv71q21.overlay} | 0 ...verlay => sam_v71_xult_samv71q21b.overlay} | 0 ...c21n_xpro.overlay => samc21n_xpro.overlay} | 0 ...amd20_xpro.overlay => samd20_xpro.overlay} | 0 ...amd21_xpro.overlay => samd21_xpro.overlay} | 0 ...ame54_xpro.overlay => same54_xpro.overlay} | 0 ...aml21_xpro.overlay => saml21_xpro.overlay} | 0 ...amr21_xpro.overlay => samr21_xpro.overlay} | 0 ...amr34_xpro.overlay => samr34_xpro.overlay} | 0 ...verlay => xiao_ble_nrf52840_sense.overlay} | 0 ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 tests/drivers/audio/dmic_api/testcase.yaml | 2 +- tests/drivers/build_all/adc/testcase.yaml | 8 +- ...rty_a7_designstart_fpga_cortex_m1.overlay} | 0 tests/drivers/build_all/counter/testcase.yaml | 2 +- ...amd21_xpro.overlay => samd21_xpro.overlay} | 0 tests/drivers/build_all/dac/testcase.yaml | 2 +- tests/drivers/build_all/gpio/testcase.yaml | 2 +- .../build_all/ieee802154/testcase.yaml | 2 +- ...rty_a7_designstart_fpga_cortex_m1.overlay} | 0 tests/drivers/build_all/pwm/testcase.yaml | 24 +- tests/drivers/can/api/testcase.yaml | 8 +- .../drivers/charger/sbs_charger/testcase.yaml | 12 +- .../clock_control/adsp_clock/testcase.yaml | 4 +- .../clock_control_api/testcase.yaml | 18 +- .../nrf_clock_calibration/testcase.yaml | 8 +- .../nrf_lf_clock_start/testcase.yaml | 116 +- .../nrf_onoff_and_bt/testcase.yaml | 8 +- .../drivers/clock_control/onoff/testcase.yaml | 10 +- ...overlay => mimxrt685_evk_rtc_1khz.overlay} | 0 ...51422.overlay => nrf51dk_nrf51822.overlay} | 0 ...verlay => s32z2xxdc2_s32z270_rtu0.overlay} | 0 ...verlay => s32z2xxdc2_s32z270_rtu1.overlay} | 0 ...> stm32h747i_disco_stm32h747xx_m7.overlay} | 0 .../counter/counter_basic_api/testcase.yaml | 6 +- .../counter_nrf_rtc/fixed_top/testcase.yaml | 2 +- ...51422.overlay => nrf51dk_nrf51822.overlay} | 0 tests/drivers/dac/dac_api/src/test_dac.c | 2 +- tests/drivers/dac/dac_loopback/src/test_dac.c | 4 +- tests/drivers/dac/dac_loopback/testcase.yaml | 2 +- .../disk/disk_performance/testcase.yaml | 2 +- .../boards/mimxrt1160_evk_mimxrt1166_cm4.conf | 3 + .../mimxrt1160_evk_mimxrt1166_cm4.overlay | 14 + ...onf => mimxrt1160_evk_mimxrt1166_cm7.conf} | 0 ... => mimxrt1160_evk_mimxrt1166_cm7.overlay} | 0 .../boards/mimxrt1170_evk_mimxrt1176_cm4.conf | 4 + .../mimxrt1170_evk_mimxrt1176_cm4.overlay | 14 + .../mimxrt1170_evk_mimxrt1176_cm4_B.conf | 3 + .../mimxrt1170_evk_mimxrt1176_cm4_B.overlay | 14 + .../mimxrt1170_evk_mimxrt1176_cm7_A.conf | 3 + .../mimxrt1170_evk_mimxrt1176_cm7_A.overlay | 14 + ...onf => mimxrt595_evk_mimxrt595s_cm33.conf} | 0 ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 ...c21n_xpro.overlay => samc21n_xpro.overlay} | 0 ...amd21_xpro.overlay => samd21_xpro.overlay} | 0 ...aml21_xpro.overlay => saml21_xpro.overlay} | 0 ...amr34_xpro.overlay => samr34_xpro.overlay} | 0 ... => mimxrt1160_evk_mimxrt1166_cm7.overlay} | 0 .../mimxrt1170_evk_mimxrt1176_cm7_A.overlay | 7 + .../dma/chan_link_transfer/testcase.yaml | 8 +- ...lay => longan_nano_gd32vf103_lite.overlay} | 0 .../boards/mimxrt1160_evk_mimxrt1166_cm4.conf | 3 + .../mimxrt1160_evk_mimxrt1166_cm4.overlay | 14 + ...onf => mimxrt1160_evk_mimxrt1166_cm7.conf} | 0 ... => mimxrt1160_evk_mimxrt1166_cm7.overlay} | 0 .../boards/mimxrt1170_evk_mimxrt1176_cm4.conf | 3 + .../mimxrt1170_evk_mimxrt1176_cm4.overlay | 14 + .../mimxrt1170_evk_mimxrt1176_cm4_B.conf | 3 + .../mimxrt1170_evk_mimxrt1176_cm4_B.overlay | 14 + .../mimxrt1170_evk_mimxrt1176_cm7_A.conf | 3 + .../mimxrt1170_evk_mimxrt1176_cm7_A.overlay | 14 + .../mimxrt1170_evk_mimxrt1176_cm7_B.conf | 3 + ...> mimxrt1170_evk_mimxrt1176_cm7_B.overlay} | 0 ...onf => mimxrt595_evk_mimxrt595s_cm33.conf} | 0 ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 ...c21n_xpro.overlay => samc21n_xpro.overlay} | 0 ...amd21_xpro.overlay => samd21_xpro.overlay} | 0 ...aml21_xpro.overlay => saml21_xpro.overlay} | 0 ...amr34_xpro.overlay => samr34_xpro.overlay} | 0 ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 .../drivers/dma/scatter_gather/testcase.yaml | 4 +- ... => b_u585i_iot02a_stm32u585xx_ns.overlay} | 0 ...onf => mimxrt595_evk_mimxrt595s_cm33.conf} | 0 .../common/boards/nrf52840_flash_qspi.conf | 2 +- .../common/boards/nrf52840_flash_soc.conf | 2 +- tests/drivers/flash/common/testcase.yaml | 36 +- .../drivers/flash/erase_blocks/testcase.yaml | 6 +- tests/drivers/flash/stm32/testcase.yaml | 2 +- .../fuel_gauge/sbs_gauge/testcase.yaml | 12 +- ...verlay => s32z2xxdc2_s32z270_rtu0.overlay} | 0 ...verlay => s32z2xxdc2_s32z270_rtu1.overlay} | 0 .../drivers/gpio/gpio_api_1pin/testcase.yaml | 5 +- ...rlay => bl5340_dvk_nrf5340_cpuapp.overlay} | 0 ...1_revb.overlay => hifive1_fe310_B.overlay} | 0 ...ay => lpcxpresso54114_lpc54114_m4.overlay} | 0 ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 ...verlay => s32z2xxdc2_s32z270_rtu0.overlay} | 0 ...verlay => s32z2xxdc2_s32z270_rtu1.overlay} | 0 ...lay => sam_e70_xplained_same70q21.overlay} | 0 ...amd21_xpro.overlay => samd21_xpro.overlay} | 0 ...> stm32h747i_disco_stm32h747xx_m7.overlay} | 0 ...erlay => udoo_neo_full_mcimx6x_m4.overlay} | 0 tests/drivers/gpio/gpio_basic_api/src/main.c | 4 +- .../drivers/gpio/gpio_basic_api/testcase.yaml | 2 +- ...verlay => s32z2xxdc2_s32z270_rtu0.overlay} | 0 ...verlay => s32z2xxdc2_s32z270_rtu1.overlay} | 0 .../gpio/gpio_get_direction/testcase.yaml | 4 +- ...verlay => s32z2xxdc2_s32z270_rtu0.overlay} | 0 ...verlay => s32z2xxdc2_s32z270_rtu1.overlay} | 0 tests/drivers/gpio/gpio_hogs/testcase.yaml | 8 +- .../gpio/gpio_ite_it8xxx2_v2/CMakeLists.txt | 4 +- .../include/chip_chipregs.h | 2 +- ...> mimxrt1170_evk_mimxrt1176_cm4_B.overlay} | 0 .../mimxrt1170_evk_mimxrt1176_cm7_B.overlay | 25 + tests/drivers/i2c/i2c_tca954x/testcase.yaml | 2 +- ...> mimxrt1170_evk_mimxrt1176_cm7_A.overlay} | 0 ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 ...lay => sam_e70_xplained_same70q21.overlay} | 0 ...overlay => sam_v71_xult_samv71q21.overlay} | 0 tests/drivers/i2s/i2s_api/testcase.yaml | 8 +- ...f => mimxrt1170_evk_mimxrt1176_cm7_A.conf} | 0 ...> mimxrt1170_evk_mimxrt1176_cm7_A.overlay} | 0 .../boards/mimxrt1170_evk_rt1176_cm7.conf | 25 + ...onf => mimxrt595_evk_mimxrt595s_cm33.conf} | 0 ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 tests/drivers/mbox/mbox_data/CMakeLists.txt | 8 +- tests/drivers/mbox/mbox_data/Kconfig.sysbuild | 8 +- ...onf => lpcxpresso55s69_lpc55s69_cpu0.conf} | 0 ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 .../boards/mimxrt1160_evk_mimxrt1166_cm7.conf | 3 + ... => mimxrt1160_evk_mimxrt1166_cm7.overlay} | 0 .../mimxrt1170_evk_mimxrt1176_cm7_A.conf | 3 + .../mimxrt1170_evk_mimxrt1176_cm7_A.overlay | 29 + .../mimxrt1170_evk_mimxrt1176_cm7_B.conf | 3 + .../mimxrt1170_evk_mimxrt1176_cm7_B.overlay | 29 + .../mbox/mbox_data/remote/CMakeLists.txt | 8 +- ...onf => lpcxpresso55s69_lpc55s69_cpu1.conf} | 0 ... => lpcxpresso55s69_lpc55s69_cpu1.overlay} | 0 .../boards/mimxrt1160_evk_mimxrt1166_cm4.conf | 4 + .../mimxrt1160_evk_mimxrt1166_cm4.overlay | 54 + .../boards/mimxrt1170_evk_mimxrt1176_cm4.conf | 4 + .../mimxrt1170_evk_mimxrt1176_cm4.overlay | 54 + .../mimxrt1170_evk_mimxrt1176_cm4_B.conf | 4 + .../mimxrt1170_evk_mimxrt1176_cm4_B.overlay | 55 + tests/drivers/mbox/mbox_data/sysbuild.cmake | 6 +- tests/drivers/mbox/mbox_data/testcase.yaml | 12 +- tests/drivers/mm/sys_mm_drv_api/testcase.yaml | 2 +- .../drivers/mm/sys_mm_drv_bank/testcase.yaml | 2 +- ...verlay => rcar_h3ulcb_r8a77951_r7.overlay} | 0 tests/drivers/pwm/pwm_api/src/test_pwm.c | 4 +- tests/drivers/regulator/fixed/testcase.yaml | 12 +- ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 tests/drivers/regulator/voltage/testcase.yaml | 4 +- tests/drivers/retained_mem/api/testcase.yaml | 4 +- tests/drivers/sensor/generic/testcase.yaml | 2 +- ...s.overlay => qemu_arc_qemu_arc_hs.overlay} | 0 tests/drivers/sensor/sbs_gauge/testcase.yaml | 2 +- ...arbon.conf => 96b_carbon_stm32f401xe.conf} | 0 ...overlay => 96b_carbon_stm32f401xe.overlay} | 0 ...> arty_a7_designstart_fpga_cortex_m1.conf} | 0 ...rty_a7_designstart_fpga_cortex_m1.overlay} | 0 ...lay => longan_nano_gd32vf103_lite.overlay} | 0 ...ay => lpcxpresso54114_lpc54114_m4.overlay} | 0 ...> mimxrt1170_evk_mimxrt1176_cm4_B.overlay} | 0 ...f => mimxrt1170_evk_mimxrt1176_cm7_A.conf} | 0 ...> mimxrt1170_evk_mimxrt1176_cm7_A.overlay} | 0 ...> mimxrt1170_evk_mimxrt1176_cm7_B.overlay} | 0 ...onf => mimxrt595_evk_mimxrt595s_cm33.conf} | 0 ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 ...51422.overlay => nrf51dk_nrf51822.overlay} | 0 .../{tdk_robokit1.conf => robokit1.conf} | 0 ...{tdk_robokit1.overlay => robokit1.overlay} | 0 ... rv32m1_vega_openisa_rv32m1_ri5cy.overlay} | 0 ...verlay => s32z2xxdc2_s32z270_rtu0.overlay} | 0 ...verlay => s32z2xxdc2_s32z270_rtu1.overlay} | 0 ...lay => sam_e70_xplained_same70q21.overlay} | 0 ...overlay => sam_v71_xult_samv71q21.overlay} | 0 .../{atsamd21_xpro.conf => samd21_xpro.conf} | 0 ...amd21_xpro.overlay => samd21_xpro.overlay} | 0 ...ame54_xpro.overlay => same54_xpro.overlay} | 0 .../{atsamr21_xpro.conf => samr21_xpro.conf} | 0 ...amr21_xpro.overlay => samr21_xpro.overlay} | 0 tests/drivers/spi/spi_loopback/testcase.yaml | 18 +- .../drivers/timer/nrf_rtc_timer/testcase.yaml | 12 +- .../mimxrt1160_evk_mimxrt1166_cm4.overlay | 7 + ... => mimxrt1160_evk_mimxrt1166_cm7.overlay} | 0 .../mimxrt1170_evk_mimxrt1176_cm4.overlay | 7 + .../mimxrt1170_evk_mimxrt1176_cm7_A.overlay | 13 + ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 ...=> nucleo_l552ze_q_stm32l552xx_ns.overlay} | 0 ...c21n_xpro.overlay => samc21n_xpro.overlay} | 0 ...amd21_xpro.overlay => samd21_xpro.overlay} | 0 ...ame54_xpro.overlay => same54_xpro.overlay} | 0 ...aml21_xpro.overlay => saml21_xpro.overlay} | 0 ...amr21_xpro.overlay => samr21_xpro.overlay} | 0 ...amr34_xpro.overlay => samr34_xpro.overlay} | 0 ...y => stm32l562e_dk_stm32l562xx_ns.overlay} | 0 .../drivers/uart/uart_async_api/testcase.yaml | 20 +- .../drivers/uart/uart_basic_api/testcase.yaml | 6 +- .../uart/uart_mix_fifo_poll/src/main.c | 6 +- .../uart/uart_mix_fifo_poll/testcase.yaml | 8 +- tests/drivers/uart/uart_pm/testcase.yaml | 2 +- tests/drivers/udc/testcase.yaml | 2 +- tests/drivers/w1/w1_api/testcase.yaml | 4 +- .../watchdog/wdt_basic_api/testcase.yaml | 22 +- .../wdt_basic_reset_none/testcase.yaml | 8 +- tests/kernel/cache/testcase.yaml | 12 +- tests/kernel/fatal/exception/testcase.yaml | 4 +- .../fatal/no-multithreading/testcase.yaml | 20 +- ....conf => lpcxpresso54114_lpc54114_m4.conf} | 0 tests/kernel/gen_isr_table/testcase.yaml | 6 +- .../mbox_api/boards/qemu_x86_tiny_768.conf | 5 - ... qemu_cortex_a53_qemu_cortex_a53_smp.conf} | 0 .../mem_map/boards/qemu_x86_tiny_768.overlay | 3 - ... qemu_cortex_a53_qemu_cortex_a53_smp.conf} | 0 .../mem_protect/mem_protect/testcase.yaml | 8 +- .../stackprot/boards/qemu_x86_tiny_768.conf | 5 - .../kernel/mem_protect/syscalls/testcase.yaml | 2 +- ... => mimxrt595_evk_mimxrt595s_cm33.overlay} | 0 ...evk_cm33.overlay => mimxrt685_evk.overlay} | 0 .../mem_protect/userspace/testcase.yaml | 8 +- tests/kernel/mem_slab/mslab_api/testcase.yaml | 20 +- tests/kernel/obj_core/obj_core/testcase.yaml | 2 +- .../obj_core/obj_core_stats/testcase.yaml | 2 +- .../obj_core/obj_core_stats_api/testcase.yaml | 2 +- tests/kernel/poll/testcase.yaml | 12 +- .../profiling/profiling_api/testcase.yaml | 10 +- tests/kernel/sched/metairq/testcase.yaml | 2 +- tests/kernel/sched/preempt/testcase.yaml | 2 +- ... qemu_cortex_a53_qemu_cortex_a53_smp.conf} | 0 ...mu_cortex_a53_qemu_cortex_a53_smp.overlay} | 0 tests/kernel/smp_boot_delay/testcase.yaml | 4 +- .../dynamic_thread_stack/testcase.yaml | 6 +- .../threads/no-multithreading/testcase.yaml | 28 +- .../kernel/threads/thread_stack/testcase.yaml | 4 +- .../tickless/tickless_concept/testcase.yaml | 6 +- tests/kernel/timer/timer_api/testcase.yaml | 26 +- .../timer/timer_monotonic/testcase.yaml | 6 +- .../usage/thread_runtime_stats/testcase.yaml | 2 +- tests/kernel/workq/critical/testcase.yaml | 6 +- tests/kernel/xip/testcase.yaml | 8 +- tests/lib/c_lib/common/testcase.yaml | 2 +- tests/lib/cmsis_dsp/bayes/testcase.yaml | 8 +- tests/lib/cmsis_dsp/complexmath/testcase.yaml | 8 +- tests/lib/cmsis_dsp/distance/testcase.yaml | 8 +- tests/lib/cmsis_dsp/fastmath/testcase.yaml | 8 +- tests/lib/cmsis_dsp/filtering/testcase.yaml | 32 +- .../lib/cmsis_dsp/interpolation/testcase.yaml | 8 +- tests/lib/cmsis_dsp/matrix/testcase.yaml | 96 +- .../cmsis_dsp/quaternionmath/testcase.yaml | 8 +- tests/lib/cmsis_dsp/statistics/testcase.yaml | 8 +- tests/lib/cmsis_dsp/support/testcase.yaml | 8 +- tests/lib/cmsis_dsp/svm/testcase.yaml | 8 +- tests/lib/cmsis_dsp/transform/testcase.yaml | 50 +- tests/lib/cmsis_nn/testcase.yaml | 4 +- tests/lib/cpp/cxx/testcase.yaml | 8 +- tests/lib/cpp/libcxx/testcase.yaml | 6 +- tests/lib/heap/src/main.c | 2 +- tests/lib/heap/testcase.yaml | 1 - tests/lib/heap_align/testcase.yaml | 2 +- tests/lib/mpsc_pbuf/testcase.yaml | 4 +- tests/lib/multi_heap/testcase.yaml | 18 +- tests/lib/newlib/heap_listener/testcase.yaml | 2 +- tests/lib/newlib/thread_safety/testcase.yaml | 2 +- tests/lib/shared_multi_heap/testcase.yaml | 2 +- tests/lib/sprintf/testcase.yaml | 2 +- tests/lib/time/testcase.yaml | 2 +- tests/misc/test_build/testcase.yaml | 14 +- tests/modules/thrift/ThriftTest/testcase.yaml | 2 +- tests/net/lib/dns_sd/prj-no-ipv6.conf | 2 +- tests/net/lib/dns_sd/prj.conf | 2 +- tests/net/ptp/clock/testcase.yaml | 2 +- tests/net/socket/poll/testcase.yaml | 4 +- .../socket/reuseaddr_reuseport/testcase.yaml | 4 +- tests/net/socket/select/testcase.yaml | 4 +- tests/net/socket/service/testcase.yaml | 4 +- tests/net/socket/socketpair/testcase.yaml | 8 +- tests/net/socket/tcp/testcase.yaml | 4 +- tests/net/socket/tls/testcase.yaml | 4 +- tests/posix/common/testcase.yaml | 14 +- tests/posix/pthread_pressure/testcase.yaml | 2 +- tests/subsys/bindesc/definition/testcase.yaml | 8 +- tests/subsys/debug/coredump/src/main.c | 1 - .../debug/coredump_backends/testcase.yaml | 6 +- tests/subsys/dfu/img_util/testcase.yaml | 4 +- tests/subsys/dfu/mcuboot/testcase.yaml | 4 +- tests/subsys/dfu/mcuboot_multi/testcase.yaml | 4 +- tests/subsys/dsp/basicmath/testcase.yaml | 10 +- tests/subsys/fs/ext2/testcase.yaml | 4 +- ...dk_nrf51422.conf => nrf51dk_nrf51822.conf} | 0 tests/subsys/fs/fcb/testcase.yaml | 8 +- tests/subsys/fs/littlefs/testcase.yaml | 4 +- tests/subsys/llext/hello_world/testcase.yaml | 6 +- .../logging/log_backend_fs/testcase.yaml | 2 +- .../logging/log_switch_format/testcase.yaml | 6 +- tests/subsys/logging/log_syst/testcase.yaml | 4 +- .../mgmt/mcumgr/all_options/testcase.yaml | 2 +- ...> qemu_riscv32_qemu_virt_riscv32_smp.conf} | 0 ...> qemu_riscv64_qemu_virt_riscv64_smp.conf} | 0 .../mcumgr/cb_notifications/testcase.yaml | 2 +- ...> qemu_riscv32_qemu_virt_riscv32_smp.conf} | 0 ...> qemu_riscv64_qemu_virt_riscv64_smp.conf} | 0 .../fs_mgmt_hash_supported/testcase.yaml | 24 +- .../mgmt/mcumgr/handler_demo/testcase.yaml | 8 +- ...overlay => qemu_arc_qemu_arc_hs6x.overlay} | 0 ...> qemu_riscv64_qemu_virt_riscv64_smp.conf} | 0 ...emu_riscv64_qemu_virt_riscv64_smp.overlay} | 0 .../mcumgr/os_mgmt_datetime/testcase.yaml | 4 +- ...> qemu_riscv32_qemu_virt_riscv32_smp.conf} | 0 ...> qemu_riscv64_qemu_virt_riscv64_smp.conf} | 0 ...> qemu_riscv32_qemu_virt_riscv32_smp.conf} | 0 ...> qemu_riscv64_qemu_virt_riscv64_smp.conf} | 0 .../mgmt/mcumgr/os_mgmt_info/testcase.yaml | 6 +- .../mgmt/mcumgr/settings_mgmt/testcase.yaml | 2 +- ...> qemu_riscv32_qemu_virt_riscv32_smp.conf} | 0 ...> qemu_riscv64_qemu_virt_riscv64_smp.conf} | 0 .../subsys/modem/backends/uart/testcase.yaml | 2 +- tests/subsys/pm/power_mgmt_soc/testcase.yaml | 2 +- tests/subsys/sd/mmc/testcase.yaml | 2 +- tests/subsys/settings/fcb/testcase.yaml | 6 +- tests/subsys/settings/fcb_init/testcase.yaml | 6 +- tests/subsys/settings/file/testcase.yaml | 2 +- .../settings/functional/fcb/testcase.yaml | 6 +- .../settings/functional/file/testcase.yaml | 4 +- .../settings/functional/nvs/testcase.yaml | 6 +- tests/subsys/storage/flash_map/testcase.yaml | 12 +- .../storage/stream/stream_flash/testcase.yaml | 4 +- tests/subsys/zbus/dyn_channel/testcase.yaml | 2 +- .../zbus/hlp_priority_boost/testcase.yaml | 2 +- tests/subsys/zbus/integration/testcase.yaml | 2 +- tests/subsys/zbus/unittests/testcase.yaml | 4 +- tests/subsys/zbus/user_data/testcase.yaml | 2 +- tests/ztest/busy_sim/testcase.yaml | 4 +- west.yml | 18 +- 13315 files changed, 159271 insertions(+), 157405 deletions(-) create mode 100644 arch/Kconfig.v1 create mode 100644 arch/Kconfig.v2 create mode 100644 arch/archs.yml rename boards/{arm/96b_aerocore2 => 96boards/aerocore2}/96b_aerocore2.dts (100%) rename boards/{arm/96b_aerocore2 => 96boards/aerocore2}/96b_aerocore2.yaml (94%) rename boards/{arm/96b_aerocore2 => 96boards/aerocore2}/96b_aerocore2_defconfig (86%) create mode 100644 boards/96boards/aerocore2/Kconfig.96b_aerocore2 rename boards/{arm/96b_aerocore2 => 96boards/aerocore2}/board.cmake (100%) create mode 100644 boards/96boards/aerocore2/board.yml rename boards/{arm/96b_aerocore2 => 96boards/aerocore2}/doc/img/96b_aerocore2.jpg (100%) create mode 100644 boards/96boards/aerocore2/doc/index.rst rename boards/{arm/96b_argonkey => 96boards/argonkey}/96b_argonkey.dts (100%) rename boards/{arm/96b_argonkey => 96boards/argonkey}/96b_argonkey.yaml (100%) rename boards/{arm/96b_argonkey => 96boards/argonkey}/96b_argonkey_defconfig (85%) create mode 100644 boards/96boards/argonkey/Kconfig.96b_argonkey create mode 100644 boards/96boards/argonkey/Kconfig.defconfig create mode 100644 boards/96boards/argonkey/board.yml rename boards/{arm/96b_argonkey => 96boards/argonkey}/doc/img/96b_argonkey.jpg (100%) create mode 100644 boards/96boards/argonkey/doc/index.rst rename boards/{arm/96b_avenger96 => 96boards/avenger96}/96b_avenger96.dts (100%) rename boards/{arm/96b_avenger96 => 96boards/avenger96}/96b_avenger96.yaml (94%) rename boards/{arm/96b_avenger96 => 96boards/avenger96}/96b_avenger96_defconfig (89%) create mode 100644 boards/96boards/avenger96/Kconfig.96b_avenger96 rename boards/{arm/96b_avenger96 => 96boards/avenger96}/board.cmake (100%) create mode 100644 boards/96boards/avenger96/board.yml rename boards/{arm/96b_avenger96 => 96boards/avenger96}/doc/img/96b_avenger96.jpg (100%) create mode 100644 boards/96boards/avenger96/doc/index.rst rename boards/{arm/96b_carbon_nrf51/96b_carbon_nrf51-pinctrl.dtsi => 96boards/carbon/96b_carbon_nrf51822-pinctrl.dtsi} (100%) create mode 100644 boards/96boards/carbon/96b_carbon_nrf51822.dts create mode 100644 boards/96boards/carbon/96b_carbon_nrf51822.yaml create mode 100644 boards/96boards/carbon/96b_carbon_nrf51822_defconfig rename boards/{arm/96b_carbon/96b_carbon.dts => 96boards/carbon/96b_carbon_stm32f401xe.dts} (100%) create mode 100644 boards/96boards/carbon/96b_carbon_stm32f401xe.yaml create mode 100644 boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig rename boards/{arm/96b_carbon => 96boards/carbon}/96b_lscon.dtsi (100%) create mode 100644 boards/96boards/carbon/Kconfig.96b_carbon create mode 100644 boards/96boards/carbon/Kconfig.defconfig create mode 100644 boards/96boards/carbon/board.cmake create mode 100644 boards/96boards/carbon/board.yml rename boards/{arm/96b_carbon => 96boards/carbon}/doc/img/96b_carbon.jpg (100%) rename boards/{arm/96b_carbon_nrf51 => 96boards/carbon}/doc/img/96b_carbon_nrf51.jpg (100%) create mode 100644 boards/96boards/carbon/doc/nrf51822.rst create mode 100644 boards/96boards/carbon/doc/stm32f401xe.rst create mode 100644 boards/96boards/carbon/pre_dt_board.cmake create mode 100644 boards/96boards/index.rst rename boards/{arm/96b_meerkat96 => 96boards/meerkat96}/96b_meerkat96-pinctrl.dtsi (100%) rename boards/{arm/96b_meerkat96/96b_meerkat96.dts => 96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts} (100%) create mode 100644 boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml create mode 100644 boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig create mode 100644 boards/96boards/meerkat96/Kconfig.96b_meerkat96 create mode 100644 boards/96boards/meerkat96/Kconfig.defconfig create mode 100644 boards/96boards/meerkat96/board.yml rename boards/{arm/96b_meerkat96 => 96boards/meerkat96}/doc/img/96b_meerkat96.jpg (100%) create mode 100644 boards/96boards/meerkat96/doc/index.rst rename boards/{arm/96b_neonkey => 96boards/neonkey}/96b_neonkey.dts (100%) rename boards/{arm/96b_neonkey => 96boards/neonkey}/96b_neonkey.yaml (100%) rename boards/{arm/96b_neonkey => 96boards/neonkey}/96b_neonkey_defconfig (85%) create mode 100644 boards/96boards/neonkey/Kconfig.96b_neonkey create mode 100644 boards/96boards/neonkey/Kconfig.defconfig create mode 100644 boards/96boards/neonkey/board.yml rename boards/{arm/96b_neonkey => 96boards/neonkey}/doc/img/96b_neonkey.jpg (100%) create mode 100644 boards/96boards/neonkey/doc/index.rst rename boards/{arm/96b_nitrogen => 96boards/nitrogen}/96b_lscon.dtsi (100%) rename boards/{arm/96b_nitrogen => 96boards/nitrogen}/96b_nitrogen-pinctrl.dtsi (100%) rename boards/{arm/96b_nitrogen => 96boards/nitrogen}/96b_nitrogen.dts (100%) rename boards/{arm/96b_nitrogen => 96boards/nitrogen}/96b_nitrogen.yaml (100%) rename boards/{arm/96b_nitrogen => 96boards/nitrogen}/96b_nitrogen_defconfig (77%) create mode 100644 boards/96boards/nitrogen/Kconfig.96b_nitrogen create mode 100644 boards/96boards/nitrogen/Kconfig.defconfig rename boards/{arm/96b_nitrogen => 96boards/nitrogen}/board.cmake (100%) create mode 100644 boards/96boards/nitrogen/board.yml rename boards/{arm/96b_nitrogen => 96boards/nitrogen}/doc/img/96b_nitrogen.jpg (100%) create mode 100644 boards/96boards/nitrogen/doc/index.rst rename boards/{arm/96b_nitrogen => 96boards/nitrogen}/pre_dt_board.cmake (100%) rename boards/{arm/96b_stm32_sensor_mez => 96boards/stm32_sensor_mez}/96b_stm32_sensor_mez.dts (100%) rename boards/{arm/96b_stm32_sensor_mez => 96boards/stm32_sensor_mez}/96b_stm32_sensor_mez.yaml (100%) rename boards/{arm/96b_stm32_sensor_mez => 96boards/stm32_sensor_mez}/96b_stm32_sensor_mez_defconfig (84%) create mode 100644 boards/96boards/stm32_sensor_mez/Kconfig.96b_stm32_sensor_mez create mode 100644 boards/96boards/stm32_sensor_mez/Kconfig.defconfig rename boards/{arm/96b_stm32_sensor_mez => 96boards/stm32_sensor_mez}/board.cmake (100%) create mode 100644 boards/96boards/stm32_sensor_mez/board.yml rename boards/{arm/96b_stm32_sensor_mez => 96boards/stm32_sensor_mez}/doc/img/96b_stm32_sensor_mez.jpg (100%) create mode 100644 boards/96boards/stm32_sensor_mez/doc/index.rst rename boards/{arm/96b_stm32_sensor_mez => 96boards/stm32_sensor_mez}/support/openocd.cfg (100%) rename boards/{arm/96b_wistrio => 96boards/wistrio}/96b_lscon.dtsi (100%) rename boards/{arm/96b_wistrio => 96boards/wistrio}/96b_wistrio.dts (100%) rename boards/{arm/96b_wistrio => 96boards/wistrio}/96b_wistrio.yaml (100%) rename boards/{arm/96b_wistrio => 96boards/wistrio}/96b_wistrio_defconfig (83%) rename boards/{arm/96b_wistrio => 96boards/wistrio}/CMakeLists.txt (100%) create mode 100644 boards/96boards/wistrio/Kconfig.96b_wistrio create mode 100644 boards/96boards/wistrio/Kconfig.defconfig rename boards/{arm/96b_wistrio => 96boards/wistrio}/board.cmake (100%) create mode 100644 boards/96boards/wistrio/board.yml rename boards/{arm/96b_wistrio => 96boards/wistrio}/doc/96b_wistrio.rst (97%) rename boards/{arm/96b_wistrio => 96boards/wistrio}/doc/img/96b-wistrio.jpg (100%) rename boards/{arm/96b_wistrio => 96boards/wistrio}/dts/bindings/qorvo,rfsw8001.yaml (100%) rename boards/{arm/96b_wistrio => 96boards/wistrio}/rf.c (100%) create mode 100644 boards/Kconfig.v1 create mode 100644 boards/Kconfig.v2 create mode 100644 boards/aconno/acn52832/Kconfig.acn52832 create mode 100644 boards/aconno/acn52832/Kconfig.defconfig rename boards/{arm => aconno}/acn52832/acn52832-pinctrl.dtsi (100%) rename boards/{arm => aconno}/acn52832/acn52832.dts (100%) rename boards/{arm => aconno}/acn52832/acn52832.yaml (100%) create mode 100644 boards/aconno/acn52832/acn52832_defconfig rename boards/{arm => aconno}/acn52832/board.cmake (100%) create mode 100644 boards/aconno/acn52832/board.yml rename boards/{arm => aconno}/acn52832/doc/index.rst (100%) rename boards/{arm => aconno}/acn52832/pre_dt_board.cmake (100%) create mode 100644 boards/aconno/index.rst rename boards/{x86 => acrn}/acrn/CMakeLists.txt (100%) create mode 100644 boards/acrn/acrn/Kconfig create mode 100644 boards/acrn/acrn/Kconfig.acrn create mode 100644 boards/acrn/acrn/Kconfig.acrn_ehl_crb create mode 100644 boards/acrn/acrn/Kconfig.defconfig rename boards/{x86 => acrn}/acrn/acrn.dts (95%) rename boards/{x86 => acrn}/acrn/acrn.yaml (100%) rename boards/{x86 => acrn}/acrn/acrn_defconfig (88%) rename boards/{x86 => acrn}/acrn/acrn_ehl_crb.dts (100%) rename boards/{x86 => acrn}/acrn/acrn_ehl_crb.yaml (100%) rename boards/{x86 => acrn}/acrn/acrn_ehl_crb_defconfig (90%) rename boards/{x86 => acrn}/acrn/board.cmake (100%) create mode 100644 boards/acrn/acrn/board.yml rename boards/{x86 => acrn}/acrn/board_acrn.c (100%) rename boards/{x86 => acrn}/acrn/doc/ACRN-Hybrid.jpg (100%) create mode 100644 boards/acrn/acrn/doc/index.rst create mode 100644 boards/acrn/index.rst create mode 100644 boards/actinius/icarus/CMakeLists.txt create mode 100644 boards/actinius/icarus/Kconfig.actinius_icarus create mode 100644 boards/actinius/icarus/Kconfig.defconfig rename boards/{arm/actinius_icarus => actinius/icarus}/actinius_icarus_common-pinctrl.dtsi (100%) rename boards/{arm/actinius_icarus => actinius/icarus}/actinius_icarus_common.dtsi (100%) rename boards/{arm/actinius_icarus => actinius/icarus}/actinius_icarus_common_1_4_0.dtsi (100%) rename boards/{arm/actinius_icarus => actinius/icarus}/actinius_icarus_common_2_0_0.dtsi (100%) create mode 100644 boards/actinius/icarus/actinius_icarus_defconfig rename boards/{arm/actinius_icarus/actinius_icarus.dts => actinius/icarus/actinius_icarus_nrf9160.dts} (100%) create mode 100644 boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.overlay create mode 100644 boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.yaml create mode 100644 boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.overlay create mode 100644 boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.yaml rename boards/{arm/actinius_icarus/actinius_icarus_ns.dts => actinius/icarus/actinius_icarus_nrf9160_ns.dts} (100%) create mode 100644 boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.overlay create mode 100644 boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.yaml create mode 100644 boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.overlay create mode 100644 boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.yaml create mode 100644 boards/actinius/icarus/actinius_icarus_nrf9160_ns_defconfig rename boards/{arm/actinius_icarus => actinius/icarus}/actinius_icarus_partition_conf.dtsi (100%) rename boards/{arm/actinius_icarus => actinius/icarus}/board.cmake (100%) create mode 100644 boards/actinius/icarus/board.yml rename boards/{arm/actinius_icarus => actinius/icarus}/doc/img/Icarus_front.jpg (100%) rename boards/{arm/actinius_icarus => actinius/icarus}/doc/img/Icarus_pinouts.jpg (100%) create mode 100644 boards/actinius/icarus/doc/index.rst rename boards/{arm/actinius_icarus => actinius/icarus}/dts/bindings/actinius-charger-enable.yaml (100%) rename boards/{arm/actinius_icarus => actinius/icarus}/dts/bindings/actinius-sim-select.yaml (100%) rename boards/{arm/actinius_icarus => actinius/icarus}/feather_connector.dtsi (100%) rename boards/{arm/actinius_icarus => actinius/icarus}/pre_dt_board.cmake (100%) create mode 100644 boards/actinius/icarus_bee/CMakeLists.txt create mode 100644 boards/actinius/icarus_bee/Kconfig.actinius_icarus_bee create mode 100644 boards/actinius/icarus_bee/Kconfig.defconfig rename boards/{arm/actinius_icarus_bee => actinius/icarus_bee}/actinius_icarus_bee_common-pinctrl.dtsi (100%) rename boards/{arm/actinius_icarus_bee => actinius/icarus_bee}/actinius_icarus_bee_common.dtsi (100%) create mode 100644 boards/actinius/icarus_bee/actinius_icarus_bee_defconfig rename boards/{arm/actinius_icarus_bee/actinius_icarus_bee.dts => actinius/icarus_bee/actinius_icarus_bee_nrf9160.dts} (100%) create mode 100644 boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.yaml rename boards/{arm/actinius_icarus_bee/actinius_icarus_bee_ns.dts => actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.dts} (100%) create mode 100644 boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.yaml create mode 100644 boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns_defconfig rename boards/{arm/actinius_icarus_bee => actinius/icarus_bee}/actinius_icarus_bee_partition_conf.dtsi (100%) rename boards/{arm/actinius_icarus_bee => actinius/icarus_bee}/board.cmake (100%) create mode 100644 boards/actinius/icarus_bee/board.yml rename boards/{arm/actinius_icarus_bee => actinius/icarus_bee}/doc/img/icarus-bee-external-pins.jpg (100%) rename boards/{arm/actinius_icarus_bee => actinius/icarus_bee}/doc/img/icarus-bee-peripherals-pins.jpg (100%) rename boards/{arm/actinius_icarus_bee => actinius/icarus_bee}/doc/img/icarus-bee.jpg (100%) create mode 100644 boards/actinius/icarus_bee/doc/index.rst rename boards/{arm/actinius_icarus_bee => actinius/icarus_bee}/dts/bindings/actinius-sim-select.yaml (100%) rename boards/{arm/actinius_icarus_bee => actinius/icarus_bee}/pre_dt_board.cmake (100%) create mode 100644 boards/actinius/icarus_som/CMakeLists.txt create mode 100644 boards/actinius/icarus_som/Kconfig.actinius_icarus_som create mode 100644 boards/actinius/icarus_som/Kconfig.defconfig rename boards/{arm/actinius_icarus_som => actinius/icarus_som}/actinius_icarus_som_common-pinctrl.dtsi (100%) rename boards/{arm/actinius_icarus_som => actinius/icarus_som}/actinius_icarus_som_common.dtsi (100%) create mode 100644 boards/actinius/icarus_som/actinius_icarus_som_defconfig rename boards/{arm/actinius_icarus_som/actinius_icarus_som.dts => actinius/icarus_som/actinius_icarus_som_nrf9160.dts} (100%) create mode 100644 boards/actinius/icarus_som/actinius_icarus_som_nrf9160.yaml rename boards/{arm/actinius_icarus_som/actinius_icarus_som_ns.dts => actinius/icarus_som/actinius_icarus_som_nrf9160_ns.dts} (100%) create mode 100644 boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.yaml create mode 100644 boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns_defconfig rename boards/{arm/actinius_icarus_som => actinius/icarus_som}/actinius_icarus_som_partition_conf.dtsi (100%) rename boards/{arm/actinius_icarus_som => actinius/icarus_som}/board.cmake (100%) create mode 100644 boards/actinius/icarus_som/board.yml rename boards/{arm/actinius_icarus_som => actinius/icarus_som}/doc/img/icarus-som-external-pins.jpg (100%) rename boards/{arm/actinius_icarus_som => actinius/icarus_som}/doc/img/icarus-som-peripherals-pins.jpg (100%) rename boards/{arm/actinius_icarus_som => actinius/icarus_som}/doc/img/icarus-som.jpg (100%) create mode 100644 boards/actinius/icarus_som/doc/index.rst rename boards/{arm/actinius_icarus_som => actinius/icarus_som}/dts/bindings/actinius-sim-select.yaml (100%) rename boards/{arm/actinius_icarus_som => actinius/icarus_som}/pre_dt_board.cmake (100%) create mode 100644 boards/actinius/icarus_som_dk/CMakeLists.txt create mode 100644 boards/actinius/icarus_som_dk/Kconfig.actinius_icarus_som_dk create mode 100644 boards/actinius/icarus_som_dk/Kconfig.defconfig rename boards/{arm/actinius_icarus_som_dk => actinius/icarus_som_dk}/actinius_icarus_som_dk_common-pinctrl.dtsi (100%) rename boards/{arm/actinius_icarus_som_dk => actinius/icarus_som_dk}/actinius_icarus_som_dk_common.dtsi (100%) create mode 100644 boards/actinius/icarus_som_dk/actinius_icarus_som_dk_defconfig rename boards/{arm/actinius_icarus_som_dk/actinius_icarus_som_dk.dts => actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.dts} (100%) create mode 100644 boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.yaml rename boards/{arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns.dts => actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.dts} (100%) create mode 100644 boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.yaml create mode 100644 boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns_defconfig rename boards/{arm/actinius_icarus_som_dk => actinius/icarus_som_dk}/actinius_icarus_som_dk_partition_conf.dtsi (100%) rename boards/{arm/actinius_icarus_som_dk => actinius/icarus_som_dk}/arduino_connector.dtsi (100%) rename boards/{arm/actinius_icarus_som_dk => actinius/icarus_som_dk}/board.cmake (100%) create mode 100644 boards/actinius/icarus_som_dk/board.yml rename boards/{arm/actinius_icarus_som_dk => actinius/icarus_som_dk}/doc/img/icarus-som-dk-block-diagram.jpg (100%) rename boards/{arm/actinius_icarus_som_dk => actinius/icarus_som_dk}/doc/img/icarus-som-dk.jpg (100%) create mode 100644 boards/actinius/icarus_som_dk/doc/index.rst rename boards/{arm/actinius_icarus_som_dk => actinius/icarus_som_dk}/dts/bindings/actinius-sim-select.yaml (100%) rename boards/{arm/actinius_icarus_som_dk => actinius/icarus_som_dk}/pre_dt_board.cmake (100%) create mode 100644 boards/actinius/index.rst create mode 100644 boards/adafruit/feather/Kconfig create mode 100644 boards/adafruit/feather/Kconfig.adafruit_feather create mode 100644 boards/adafruit/feather/Kconfig.defconfig rename boards/{arm/adafruit_feather_nrf52840 => adafruit/feather}/adafruit_feather_nrf52840-pinctrl.dtsi (100%) rename boards/{arm/adafruit_feather_nrf52840 => adafruit/feather}/adafruit_feather_nrf52840.dts (100%) rename boards/{arm/adafruit_feather_nrf52840 => adafruit/feather}/adafruit_feather_nrf52840.yaml (86%) create mode 100644 boards/adafruit/feather/adafruit_feather_nrf52840_defconfig rename boards/{arm/adafruit_feather_nrf52840 => adafruit/feather}/board.cmake (100%) create mode 100644 boards/adafruit/feather/board.yml rename boards/{arm/adafruit_feather_nrf52840 => adafruit/feather}/doc/img/adafruit_feather_nrf52840.jpg (100%) create mode 100644 boards/adafruit/feather/doc/index.rst rename boards/{arm/adafruit_feather_nrf52840 => adafruit/feather}/feather_connector.dtsi (100%) rename boards/{arm/adafruit_feather_nrf52840 => adafruit/feather}/pre_dt_board.cmake (100%) create mode 100644 boards/adafruit/feather_m0_basic_proto/Kconfig.adafruit_feather_m0_basic_proto rename boards/{arm/adafruit_feather_m0_basic_proto => adafruit/feather_m0_basic_proto}/adafruit_feather_m0_basic_proto-pinctrl.dtsi (100%) rename boards/{arm/adafruit_feather_m0_basic_proto => adafruit/feather_m0_basic_proto}/adafruit_feather_m0_basic_proto.dts (100%) rename boards/{arm/adafruit_feather_m0_basic_proto => adafruit/feather_m0_basic_proto}/adafruit_feather_m0_basic_proto.yaml (100%) create mode 100644 boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig rename boards/{arm/adafruit_feather_m0_basic_proto => adafruit/feather_m0_basic_proto}/board.cmake (100%) create mode 100644 boards/adafruit/feather_m0_basic_proto/board.yml rename boards/{arm/adafruit_feather_m0_basic_proto => adafruit/feather_m0_basic_proto}/doc/img/adafruit_feather_m0_basic_proto.jpg (100%) create mode 100644 boards/adafruit/feather_m0_basic_proto/doc/index.rst rename boards/{arm/adafruit_feather_m0_basic_proto => adafruit/feather_m0_basic_proto}/feather_connector.dtsi (100%) rename boards/{arm/adafruit_feather_m0_basic_proto => adafruit/feather_m0_basic_proto}/pre_dt_board.cmake (100%) create mode 100644 boards/adafruit/feather_m0_lora/Kconfig.adafruit_feather_m0_lora rename boards/{arm/adafruit_feather_m0_lora => adafruit/feather_m0_lora}/adafruit_feather_m0_lora-pinctrl.dtsi (100%) rename boards/{arm/adafruit_feather_m0_lora => adafruit/feather_m0_lora}/adafruit_feather_m0_lora.dts (100%) rename boards/{arm/adafruit_feather_m0_lora => adafruit/feather_m0_lora}/adafruit_feather_m0_lora.yaml (100%) create mode 100644 boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora_defconfig rename boards/{arm/adafruit_feather_m0_lora => adafruit/feather_m0_lora}/board.cmake (100%) create mode 100644 boards/adafruit/feather_m0_lora/board.yml rename boards/{arm/adafruit_feather_m0_lora => adafruit/feather_m0_lora}/doc/img/adafruit_feather_m0_lora.jpg (100%) create mode 100644 boards/adafruit/feather_m0_lora/doc/index.rst rename boards/{arm/adafruit_feather_m0_lora => adafruit/feather_m0_lora}/feather_connector.dtsi (100%) rename boards/{arm/adafruit_feather_m0_lora => adafruit/feather_m0_lora}/pre_dt_board.cmake (100%) create mode 100644 boards/adafruit/feather_stm32f405/Kconfig.adafruit_feather_stm32f405 rename boards/{arm/adafruit_feather_stm32f405 => adafruit/feather_stm32f405}/adafruit_feather_stm32f405.dts (100%) rename boards/{arm/adafruit_feather_stm32f405 => adafruit/feather_stm32f405}/adafruit_feather_stm32f405.yaml (100%) rename boards/{arm/adafruit_feather_stm32f405 => adafruit/feather_stm32f405}/adafruit_feather_stm32f405_defconfig (84%) rename boards/{arm/adafruit_feather_stm32f405 => adafruit/feather_stm32f405}/board.cmake (100%) create mode 100644 boards/adafruit/feather_stm32f405/board.yml rename boards/{arm/adafruit_feather_stm32f405 => adafruit/feather_stm32f405}/doc/img/adafruit_feather_stm32f405.jpg (100%) rename boards/{arm/adafruit_feather_stm32f405 => adafruit/feather_stm32f405}/doc/index.rst (100%) rename boards/{arm/adafruit_feather_stm32f405 => adafruit/feather_stm32f405}/feather_connector.dtsi (100%) rename boards/{arm/adafruit_feather_stm32f405 => adafruit/feather_stm32f405}/support/openocd.cfg (100%) create mode 100644 boards/adafruit/grand_central_m4_express/Kconfig.adafruit_grand_central_m4_express rename boards/{arm/adafruit_grand_central_m4_express => adafruit/grand_central_m4_express}/adafruit_grand_central_m4_express-pinctrl.dtsi (100%) rename boards/{arm/adafruit_grand_central_m4_express => adafruit/grand_central_m4_express}/adafruit_grand_central_m4_express.dts (100%) rename boards/{arm/adafruit_grand_central_m4_express => adafruit/grand_central_m4_express}/adafruit_grand_central_m4_express.yaml (100%) create mode 100644 boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express_defconfig rename boards/{arm/adafruit_grand_central_m4_express => adafruit/grand_central_m4_express}/board.cmake (100%) create mode 100644 boards/adafruit/grand_central_m4_express/board.yml rename boards/{arm/adafruit_grand_central_m4_express => adafruit/grand_central_m4_express}/doc/img/adafruit_grand_central_m4_express.webp (100%) create mode 100644 boards/adafruit/grand_central_m4_express/doc/index.rst rename boards/{arm/adafruit_grand_central_m4_express => adafruit/grand_central_m4_express}/support/openocd.cfg (100%) create mode 100644 boards/adafruit/index.rst create mode 100644 boards/adafruit/itsybitsy/Kconfig create mode 100644 boards/adafruit/itsybitsy/Kconfig.adafruit_itsybitsy create mode 100644 boards/adafruit/itsybitsy/Kconfig.defconfig rename boards/{arm/adafruit_itsybitsy_nrf52840 => adafruit/itsybitsy}/adafruit_itsybitsy_nrf52840-pinctrl.dtsi (100%) rename boards/{arm/adafruit_itsybitsy_nrf52840 => adafruit/itsybitsy}/adafruit_itsybitsy_nrf52840.dts (100%) rename boards/{arm/adafruit_itsybitsy_nrf52840 => adafruit/itsybitsy}/adafruit_itsybitsy_nrf52840.yaml (86%) create mode 100644 boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840_defconfig rename boards/{arm/adafruit_itsybitsy_nrf52840 => adafruit/itsybitsy}/board.cmake (100%) create mode 100644 boards/adafruit/itsybitsy/board.yml rename boards/{arm/adafruit_itsybitsy_nrf52840 => adafruit/itsybitsy}/doc/img/adafruit_itsybitsy_nrf52840.jpeg (100%) create mode 100644 boards/adafruit/itsybitsy/doc/index.rst rename boards/{arm/adafruit_itsybitsy_nrf52840 => adafruit/itsybitsy}/pre_dt_board.cmake (100%) create mode 100644 boards/adafruit/itsybitsy_m4_express/Kconfig.adafruit_itsybitsy_m4_express rename boards/{arm/adafruit_itsybitsy_m4_express => adafruit/itsybitsy_m4_express}/adafruit_itsybitsy_m4_express-pinctrl.dtsi (100%) rename boards/{arm/adafruit_itsybitsy_m4_express => adafruit/itsybitsy_m4_express}/adafruit_itsybitsy_m4_express.dts (100%) rename boards/{arm/adafruit_itsybitsy_m4_express => adafruit/itsybitsy_m4_express}/adafruit_itsybitsy_m4_express.yaml (100%) create mode 100644 boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig rename boards/{arm/adafruit_itsybitsy_m4_express => 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arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts} (100%) create mode 100644 boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml create mode 100644 boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense_defconfig rename boards/{arm/arduino_nano_33_ble => arduino/nano_33_ble}/arduino_nano_r3_connector.dtsi (100%) rename boards/{arm/arduino_nano_33_ble => arduino/nano_33_ble}/board.c (100%) rename boards/{arm/arduino_nano_33_ble => arduino/nano_33_ble}/board.cmake (100%) create mode 100644 boards/arduino/nano_33_ble/board.yml rename boards/{arm/arduino_nano_33_ble => arduino/nano_33_ble}/doc/img/arduino_nano_33_ble_sense.jpg (100%) rename boards/{arm/arduino_nano_33_ble => arduino/nano_33_ble}/doc/img/nano_33_ble_swd.jpg (100%) rename boards/{arm/arduino_nano_33_ble => arduino/nano_33_ble}/doc/index.rst (100%) rename boards/{arm/arduino_nicla_sense_me => arduino/nano_33_ble}/pre_dt_board.cmake (100%) rename boards/{arm/arduino_nano_33_ble => arduino/nano_33_ble}/support/debug.cmm (100%) rename boards/{arm/arduino_nano_33_ble => arduino/nano_33_ble}/support/startup.cmm (100%) create mode 100644 boards/arduino/nano_33_iot/Kconfig.arduino_nano_33_iot rename boards/{arm/arduino_nano_33_iot => arduino/nano_33_iot}/arduino_nano_33_iot-pinctrl.dtsi (100%) rename boards/{arm/arduino_nano_33_iot => arduino/nano_33_iot}/arduino_nano_33_iot.dts (100%) rename boards/{arm/arduino_nano_33_iot => arduino/nano_33_iot}/arduino_nano_33_iot.yaml (100%) create mode 100644 boards/arduino/nano_33_iot/arduino_nano_33_iot_defconfig rename boards/{arm/arduino_nano_33_iot => arduino/nano_33_iot}/arduino_nano_r3_connector.dtsi (100%) rename boards/{arm/arduino_nano_33_iot => arduino/nano_33_iot}/board.cmake (100%) create mode 100644 boards/arduino/nano_33_iot/board.yml rename boards/{arm/arduino_nano_33_iot => arduino/nano_33_iot}/doc/img/nano_33_iot.jpg (100%) create mode 100644 boards/arduino/nano_33_iot/doc/index.rst rename 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boards/beagle/beagleconnect_freedom/Kconfig create mode 100644 boards/beagle/beagleconnect_freedom/Kconfig.beagleconnect_freedom rename boards/{arm/beagle_bcf => beagle/beagleconnect_freedom}/beagleconnect_freedom-pinctrl.dtsi (100%) rename boards/{arm/beagle_bcf => beagle/beagleconnect_freedom}/beagleconnect_freedom.dts (100%) rename boards/{arm/beagle_bcf => beagle/beagleconnect_freedom}/beagleconnect_freedom.yaml (100%) rename boards/{arm/beagle_bcf => beagle/beagleconnect_freedom}/beagleconnect_freedom_defconfig (87%) rename boards/{arm/beagle_bcf => beagle/beagleconnect_freedom}/board.cmake (100%) create mode 100644 boards/beagle/beagleconnect_freedom/board.yml rename boards/{arm/beagle_bcf => beagle/beagleconnect_freedom}/board_antenna.c (100%) rename boards/{arm/beagle_bcf => beagle/beagleconnect_freedom}/doc/img/beagleconnect_freedom.webp (100%) rename boards/{arm/beagle_bcf => beagle/beagleconnect_freedom}/doc/img/beagleconnect_freedom_back_annotated.webp (100%) rename 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blue_clover/plt_demo_v2}/Kconfig (100%) create mode 100644 boards/blue_clover/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 create mode 100644 boards/blue_clover/plt_demo_v2/Kconfig.defconfig rename boards/{arm/blueclover_plt_demo_v2_nrf52832 => blue_clover/plt_demo_v2}/blueclover_plt_demo_v2_nrf52832-pinctrl.dtsi (100%) rename boards/{arm/blueclover_plt_demo_v2_nrf52832 => blue_clover/plt_demo_v2}/blueclover_plt_demo_v2_nrf52832.dts (100%) rename boards/{arm/blueclover_plt_demo_v2_nrf52832 => blue_clover/plt_demo_v2}/blueclover_plt_demo_v2_nrf52832.yaml (85%) rename boards/{arm/blueclover_plt_demo_v2_nrf52832 => blue_clover/plt_demo_v2}/blueclover_plt_demo_v2_nrf52832_defconfig (75%) rename boards/{arm/blueclover_plt_demo_v2_nrf52832 => blue_clover/plt_demo_v2}/board.cmake (100%) create mode 100644 boards/blue_clover/plt_demo_v2/board.yml rename boards/{arm/blueclover_plt_demo_v2_nrf52832 => blue_clover/plt_demo_v2}/doc/img/blueclover_plt_demo_v2.jpg (100%) create mode 100644 boards/blue_clover/plt_demo_v2/doc/index.rst rename boards/{arm/bl654_dvk => blue_clover/plt_demo_v2}/pre_dt_board.cmake (100%) create mode 100644 boards/blues/index.rst rename boards/{arm/nrf52840dongle_nrf52840 => blues/swan_r5}/CMakeLists.txt (100%) create mode 100644 boards/blues/swan_r5/Kconfig.defconfig create mode 100644 boards/blues/swan_r5/Kconfig.swan_r5 rename boards/{arm => blues}/swan_r5/board.c (100%) rename boards/{arm => blues}/swan_r5/board.cmake (100%) create mode 100644 boards/blues/swan_r5/board.yml rename boards/{arm => blues}/swan_r5/doc/img/swan.jpg (100%) create mode 100644 boards/blues/swan_r5/doc/index.rst rename boards/{arm => blues}/swan_r5/feather_connector.dtsi (100%) rename boards/{arm/nucleo_l476rg => blues/swan_r5}/support/openocd.cfg (100%) rename boards/{arm => blues}/swan_r5/swan_r5.dts (100%) rename boards/{arm => blues}/swan_r5/swan_r5.yaml (100%) rename boards/{arm => blues}/swan_r5/swan_r5_defconfig (86%) rename boards/{arm => brcm}/bcm958401m2/CMakeLists.txt (100%) create mode 100644 boards/brcm/bcm958401m2/Kconfig.bcm958401m2 rename boards/{arm => brcm}/bcm958401m2/bcm958401m2.dts (100%) rename boards/{arm => brcm}/bcm958401m2/bcm958401m2.yaml (100%) create mode 100644 boards/brcm/bcm958401m2/bcm958401m2_defconfig rename boards/{arm => brcm}/bcm958401m2/board.cmake (100%) create mode 100644 boards/brcm/bcm958401m2/board.yml create mode 100644 boards/brcm/bcm958401m2/doc/index.rst rename boards/{arm/bcm958402m2_m7 => brcm/bcm958402m2}/CMakeLists.txt (100%) create mode 100644 boards/brcm/bcm958402m2/Kconfig.bcm958402m2 rename boards/{arm64/bcm958402m2_a72/bcm958402m2_a72.dts => brcm/bcm958402m2/bcm958402m2_bcm58402_a72.dts} (100%) create mode 100644 boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72.yaml create mode 100644 boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72_defconfig rename boards/{arm/bcm958402m2_m7/bcm958402m2_m7.dts => brcm/bcm958402m2/bcm958402m2_bcm58402_m7.dts} (100%) create mode 100644 boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7.yaml create mode 100644 boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7_defconfig rename boards/{arm/bcm958402m2_m7 => brcm/bcm958402m2}/board.cmake (100%) create mode 100644 boards/brcm/bcm958402m2/board.yml create mode 100644 boards/brcm/bcm958402m2/doc/a72.rst create mode 100644 boards/brcm/bcm958402m2/doc/m7.rst create mode 100644 boards/brcm/index.rst create mode 100644 boards/cdns/index.rst create mode 100644 boards/cdns/xt-sim/Kconfig.defconfig create mode 100644 boards/cdns/xt-sim/Kconfig.xt-sim rename boards/{xtensa => cdns}/xt-sim/board.cmake (100%) create mode 100644 boards/cdns/xt-sim/board.yml rename boards/{xtensa => cdns}/xt-sim/doc/img/xt-sim.jpg (100%) rename boards/{xtensa => cdns}/xt-sim/doc/index.rst (100%) rename boards/{xtensa => cdns}/xt-sim/xt-sim.dts (100%) rename boards/{xtensa => cdns}/xt-sim/xt-sim.yaml (100%) rename boards/{xtensa => cdns}/xt-sim/xt-sim_defconfig (77%) create mode 100644 boards/circuit_dojo/feather/Kconfig.circuitdojo_feather create mode 100644 boards/circuit_dojo/feather/Kconfig.defconfig rename boards/{arm/circuitdojo_feather_nrf9160 => circuit_dojo/feather}/board.cmake (100%) create mode 100644 boards/circuit_dojo/feather/board.yml rename boards/{arm/circuitdojo_feather_nrf9160 => circuit_dojo/feather}/circuitdojo_feather_nrf9160.dts (100%) rename boards/{arm/circuitdojo_feather_nrf9160 => circuit_dojo/feather}/circuitdojo_feather_nrf9160.yaml (81%) rename boards/{arm/circuitdojo_feather_nrf9160 => circuit_dojo/feather}/circuitdojo_feather_nrf9160_common-pinctrl.dtsi (100%) rename boards/{arm/circuitdojo_feather_nrf9160 => circuit_dojo/feather}/circuitdojo_feather_nrf9160_common.dtsi (100%) create mode 100644 boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_defconfig rename boards/{arm/circuitdojo_feather_nrf9160 => circuit_dojo/feather}/circuitdojo_feather_nrf9160_ns.dts (100%) rename boards/{arm/circuitdojo_feather_nrf9160 => circuit_dojo/feather}/circuitdojo_feather_nrf9160_ns.yaml (80%) create mode 100644 boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns_defconfig rename boards/{arm/circuitdojo_feather_nrf9160 => circuit_dojo/feather}/circuitdojo_feather_nrf9160_partition_conf.dtsi (100%) rename boards/{arm/circuitdojo_feather_nrf9160 => circuit_dojo/feather}/doc/img/circuitdojo_feather_nrf9160.jpg (100%) rename boards/{arm/circuitdojo_feather_nrf9160 => circuit_dojo/feather}/doc/img/nrf9160-feather-v31-features.jpg (100%) create mode 100644 boards/circuit_dojo/feather/doc/index.rst rename boards/{arm/circuitdojo_feather_nrf9160 => circuit_dojo/feather}/pre_dt_board.cmake (100%) create mode 100644 boards/circuit_dojo/index.rst create mode 100644 boards/contextual_electronics/abc/Kconfig create mode 100644 boards/contextual_electronics/abc/Kconfig.contextualelectronics_abc create mode 100644 boards/contextual_electronics/abc/Kconfig.defconfig create mode 100644 boards/contextual_electronics/abc/board.cmake create mode 100644 boards/contextual_electronics/abc/board.yml rename boards/{arm/contextualelectronics_abc => contextual_electronics/abc}/contextualelectronics_abc-pinctrl.dtsi (100%) rename boards/{arm/contextualelectronics_abc => contextual_electronics/abc}/contextualelectronics_abc.dts (100%) rename boards/{arm/contextualelectronics_abc => contextual_electronics/abc}/contextualelectronics_abc.yaml (100%) rename boards/{arm/contextualelectronics_abc => contextual_electronics/abc}/contextualelectronics_abc_defconfig (75%) rename boards/{arm/contextualelectronics_abc => contextual_electronics/abc}/doc/img/contextualelectronics_abc.jpg (100%) rename boards/{arm/contextualelectronics_abc => contextual_electronics/abc}/doc/index.rst (100%) rename boards/{arm/bl654_sensor_board => contextual_electronics/abc}/pre_dt_board.cmake (100%) create mode 100644 boards/contextual_electronics/index.rst create mode 100644 boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble create mode 100644 boards/cypress/cy8ckit_062_ble/board.cmake create mode 100644 boards/cypress/cy8ckit_062_ble/board.yml rename boards/{arm => cypress}/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi (100%) rename boards/{arm/cy8ckit_062_ble/cy8ckit_062_ble_m0.dts => cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts} (100%) rename boards/{arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_0_0_0.overlay => cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay} (100%) create mode 100644 boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml rename boards/{arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_1_0_0.overlay => cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay} (100%) create mode 100644 boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml create mode 100644 boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig rename boards/{arm/cy8ckit_062_ble/cy8ckit_062_ble_m4.dts => cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts} (100%) rename boards/{arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_0_0_0.overlay => cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay} (100%) create mode 100644 boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml create mode 100644 boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml create mode 100644 boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig rename boards/{arm => cypress}/cy8ckit_062_ble/doc/img/cy8ckit-062-ble.jpg (100%) create mode 100644 boards/cypress/cy8ckit_062_ble/doc/index.rst rename boards/{arm => cypress}/cy8ckit_062_ble/support/openocd.cfg (100%) create mode 100644 boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt rename boards/{arm => cypress}/cy8ckit_062_wifi_bt/board.cmake (100%) create mode 100644 boards/cypress/cy8ckit_062_wifi_bt/board.yml rename boards/{arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0.dts => cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts} (100%) create mode 100644 boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml create mode 100644 boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig rename boards/{arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4.dts => cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts} (100%) create mode 100644 boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml create mode 100644 boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig rename boards/{arm => cypress}/cy8ckit_062_wifi_bt/doc/img/cy8ckit_062_wifi_bt_m0.jpg (100%) create mode 100644 boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst rename boards/{arm => cypress}/cy8ckit_062_wifi_bt/support/openocd.cfg (100%) create mode 100644 boards/cypress/cy8ckit_062s4/Kconfig.cy8ckit_062s4 rename boards/{arm => cypress}/cy8ckit_062s4/board.cmake (100%) create mode 100644 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cypress}/cy8cproto_063_ble/doc/img/cy8cproto-063-ble.jpg (100%) create mode 100644 boards/cypress/cy8cproto_063_ble/doc/index.rst rename boards/{arm => cypress}/cy8cproto_063_ble/support/openocd.cfg (100%) create mode 100644 boards/cypress/index.rst create mode 100644 boards/digilent/arty_a7/CMakeLists.txt create mode 100644 boards/digilent/arty_a7/Kconfig create mode 100644 boards/digilent/arty_a7/Kconfig.arty_a7 create mode 100644 boards/digilent/arty_a7/Kconfig.defconfig rename boards/{arm/arty/arty_a7_arm_designstart_m1.dts => digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.dts} (100%) create mode 100644 boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml create mode 100644 boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1_defconfig rename boards/{arm/arty/arty_a7_arm_designstart_m3.dts => digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.dts} (100%) create mode 100644 boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml create mode 100644 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ebyte/e73_tbb}/board.cmake (100%) create mode 100644 boards/ebyte/e73_tbb/board.yml rename boards/{arm/ebyte_e73_tbb_nrf52832 => ebyte/e73_tbb}/doc/img/ebyte_e73_tbb_nrf52832.jpg (100%) create mode 100644 boards/ebyte/e73_tbb/doc/index.rst rename boards/{arm/ebyte_e73_tbb_nrf52832 => ebyte/e73_tbb}/ebyte_e73_tbb_nrf52832-pinctrl.dtsi (100%) rename boards/{arm/ebyte_e73_tbb_nrf52832 => ebyte/e73_tbb}/ebyte_e73_tbb_nrf52832.dts (100%) rename boards/{arm/ebyte_e73_tbb_nrf52832 => ebyte/e73_tbb}/ebyte_e73_tbb_nrf52832.yaml (85%) rename boards/{arm/ebyte_e73_tbb_nrf52832 => ebyte/e73_tbb}/ebyte_e73_tbb_nrf52832_defconfig (76%) create mode 100644 boards/ebyte/index.rst create mode 100644 boards/efinix/index.rst create mode 100644 boards/efinix/titanium_ti60_f225/Kconfig.titanium_ti60_f225 create mode 100644 boards/efinix/titanium_ti60_f225/board.yml rename boards/{riscv => efinix}/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg (100%) rename boards/{riscv => efinix}/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg (100%) rename boards/{riscv => efinix}/titanium_ti60_f225/doc/index.rst (100%) rename boards/{riscv => efinix}/titanium_ti60_f225/titanium_ti60_f225.dts (100%) rename boards/{riscv => efinix}/titanium_ti60_f225/titanium_ti60_f225.yaml (100%) rename boards/{riscv => efinix}/titanium_ti60_f225/titanium_ti60_f225_defconfig (78%) create mode 100644 boards/electronut_labs/index.rst rename boards/{arm => electronut_labs}/nrf52840_blip/Kconfig (100%) create mode 100644 boards/electronut_labs/nrf52840_blip/Kconfig.defconfig create mode 100644 boards/electronut_labs/nrf52840_blip/Kconfig.nrf52840_blip rename boards/{arm => electronut_labs}/nrf52840_blip/board.cmake (100%) create mode 100644 boards/electronut_labs/nrf52840_blip/board.yml rename boards/{arm => electronut_labs}/nrf52840_blip/doc/img/nrf52840_blip.jpg (100%) create mode 100644 boards/electronut_labs/nrf52840_blip/doc/index.rst rename boards/{arm => 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create mode 100644 boards/element14/warp7/warp7_mcimx7d_m4_defconfig create mode 100644 boards/enclustra/mercury_xu/CMakeLists.txt create mode 100644 boards/enclustra/mercury_xu/Kconfig.defconfig create mode 100644 boards/enclustra/mercury_xu/Kconfig.mercury_xu rename boards/{arm => enclustra}/mercury_xu/board.c (100%) create mode 100644 boards/enclustra/mercury_xu/board.yml rename boards/{arm => enclustra}/mercury_xu/mercury_xu-pinctrl.dtsi (100%) rename boards/{arm => enclustra}/mercury_xu/mercury_xu.dts (100%) rename boards/{arm => enclustra}/mercury_xu/mercury_xu.yaml (100%) create mode 100644 boards/enclustra/mercury_xu/mercury_xu_defconfig create mode 100644 boards/enjoy_digital/index.rst create mode 100644 boards/enjoy_digital/litex_vexriscv/Kconfig.defconfig create mode 100644 boards/enjoy_digital/litex_vexriscv/Kconfig.litex_vexriscv create mode 100644 boards/enjoy_digital/litex_vexriscv/board.yml rename boards/{riscv => enjoy_digital}/litex_vexriscv/doc/img/litex_vexriscv.jpg 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boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover rename boards/{riscv/esp32c3_luatos_core => espressif/esp32_devkitc_wrover}/Kconfig.sysbuild (100%) rename boards/{xtensa => espressif}/esp32_devkitc_wrover/board.cmake (100%) create mode 100644 boards/espressif/esp32_devkitc_wrover/board.yml rename boards/{xtensa => espressif}/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg (100%) create mode 100644 boards/espressif/esp32_devkitc_wrover/doc/index.rst rename boards/{xtensa => espressif}/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi (100%) create mode 100644 boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.dts create mode 100644 boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.yaml create mode 100644 boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu_defconfig create mode 100644 boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.dts create mode 100644 boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.yaml create mode 100644 boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu_defconfig rename boards/{xtensa => espressif}/esp32_devkitc_wrover/support/openocd.cfg (100%) rename boards/{xtensa => espressif}/esp32_ethernet_kit/CMakeLists.txt (100%) create mode 100644 boards/espressif/esp32_ethernet_kit/Kconfig create mode 100644 boards/espressif/esp32_ethernet_kit/Kconfig.defconfig create mode 100644 boards/espressif/esp32_ethernet_kit/Kconfig.esp32_ethernet_kit rename boards/{riscv/icev_wireless => espressif/esp32_ethernet_kit}/Kconfig.sysbuild (100%) rename boards/{riscv/esp32c3_devkitm => espressif/esp32_ethernet_kit}/board.cmake (100%) create mode 100644 boards/espressif/esp32_ethernet_kit/board.yml rename boards/{xtensa => espressif}/esp32_ethernet_kit/board_init.c (100%) rename boards/{xtensa => espressif}/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-a-v1.2-layout.jpg (100%) rename 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100644 boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig create mode 100644 boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.dts create mode 100644 boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.yaml create mode 100644 boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu_defconfig rename boards/{xtensa => espressif}/esp32_ethernet_kit/support/openocd.cfg (100%) create mode 100644 boards/espressif/esp32c3_devkitm/Kconfig.defconfig create mode 100644 boards/espressif/esp32c3_devkitm/Kconfig.esp32c3_devkitm rename boards/{riscv/stamp_c3 => espressif/esp32c3_devkitm}/Kconfig.sysbuild (100%) rename boards/{riscv/icev_wireless => espressif/esp32c3_devkitm}/board.cmake (100%) create mode 100644 boards/espressif/esp32c3_devkitm/board.yml create mode 100644 boards/espressif/esp32c3_devkitm/doc/index.rst rename boards/{riscv => espressif}/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi (100%) rename boards/{riscv => espressif}/esp32c3_devkitm/esp32c3_devkitm.dts (98%) rename boards/{riscv => espressif}/esp32c3_devkitm/esp32c3_devkitm.yaml (100%) create mode 100644 boards/espressif/esp32c3_devkitm/esp32c3_devkitm_defconfig rename boards/{riscv => espressif}/esp32c3_devkitm/support/openocd.cfg (100%) create mode 100644 boards/espressif/esp32s2_saola/Kconfig.defconfig create mode 100644 boards/espressif/esp32s2_saola/Kconfig.esp32s2_saola rename boards/{riscv/xiao_esp32c3 => espressif/esp32s2_saola}/Kconfig.sysbuild (100%) rename boards/{riscv/stamp_c3 => espressif/esp32s2_saola}/board.cmake (100%) create mode 100644 boards/espressif/esp32s2_saola/board.yml create mode 100644 boards/espressif/esp32s2_saola/doc/index.rst rename boards/{xtensa => espressif}/esp32s2_saola/esp32s2_saola-pinctrl.dtsi (100%) rename boards/{xtensa => espressif}/esp32s2_saola/esp32s2_saola.dts (98%) rename boards/{xtensa => espressif}/esp32s2_saola/esp32s2_saola.yaml (100%) create mode 100644 boards/espressif/esp32s2_saola/esp32s2_saola_defconfig rename boards/{xtensa/esp32s2_franzininho => espressif/esp32s2_saola}/support/openocd.cfg (100%) create mode 100644 boards/espressif/esp32s3_devkitm/Kconfig create mode 100644 boards/espressif/esp32s3_devkitm/Kconfig.defconfig create mode 100644 boards/espressif/esp32s3_devkitm/Kconfig.esp32s3_devkitm rename boards/{xtensa/esp32_devkitc_wroom => espressif/esp32s3_devkitm}/Kconfig.sysbuild (100%) rename boards/{riscv/xiao_esp32c3 => espressif/esp32s3_devkitm}/board.cmake (100%) create mode 100644 boards/espressif/esp32s3_devkitm/board.yml create mode 100644 boards/espressif/esp32s3_devkitm/doc/index.rst rename boards/{xtensa => espressif}/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi (100%) create mode 100644 boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.dts create mode 100644 boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.yaml create mode 100644 boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig create mode 100644 boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu.dts create mode 100644 boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_.yaml create mode 100644 boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_defconfig rename boards/{xtensa => espressif}/esp32s3_devkitm/support/openocd.cfg (100%) create mode 100644 boards/espressif/esp_wrover_kit/Kconfig create mode 100644 boards/espressif/esp_wrover_kit/Kconfig.defconfig create mode 100644 boards/espressif/esp_wrover_kit/Kconfig.esp_wrover_kit rename boards/{xtensa/esp32_devkitc_wrover => espressif/esp_wrover_kit}/Kconfig.sysbuild (100%) rename boards/{xtensa/esp32_ethernet_kit => espressif/esp_wrover_kit}/board.cmake (100%) create mode 100644 boards/espressif/esp_wrover_kit/board.yml rename boards/{xtensa => espressif}/esp_wrover_kit/doc/img/esp-wrover-kit-block-diagram.jpg (100%) rename boards/{xtensa => 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mode 100644 boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig create mode 100644 boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.dts create mode 100644 boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.yaml create mode 100644 boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu_defconfig rename boards/{xtensa => espressif}/esp_wrover_kit/support/openocd.cfg (100%) create mode 100644 boards/espressif/index.rst create mode 100644 boards/fanke/fk7b0m1_vbt6/Kconfig.fk7b0m1_vbt6 rename boards/{arm => fanke}/fk7b0m1_vbt6/board.cmake (100%) create mode 100644 boards/fanke/fk7b0m1_vbt6/board.yml rename boards/{arm => fanke}/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6.webp (100%) rename boards/{arm => fanke}/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6_pins.webp (100%) create mode 100644 boards/fanke/fk7b0m1_vbt6/doc/index.rst rename boards/{arm => fanke}/fk7b0m1_vbt6/fk7b0m1_vbt6.dts (100%) rename boards/{arm => fanke}/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml (100%) rename boards/{arm => fanke}/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig (87%) rename boards/{arm => fanke}/fk7b0m1_vbt6/support/openocd.cfg (100%) create mode 100644 boards/fanke/index.rst create mode 100644 boards/firefly/index.rst rename boards/{arm/frdm_k64f => firefly/roc_rk3568_pc}/CMakeLists.txt (100%) create mode 100644 boards/firefly/roc_rk3568_pc/Kconfig.roc_rk3568_pc rename boards/{arm/google_kukui => firefly/roc_rk3568_pc}/board.cmake (100%) create mode 100644 boards/firefly/roc_rk3568_pc/board.yml create mode 100644 boards/firefly/roc_rk3568_pc/doc/index.rst rename boards/{arm64 => firefly}/roc_rk3568_pc/roc_rk3568_pc.dts (100%) rename boards/{arm64 => firefly}/roc_rk3568_pc/roc_rk3568_pc.yaml (100%) rename boards/{arm64 => firefly}/roc_rk3568_pc/roc_rk3568_pc_defconfig (85%) rename boards/{arm64/roc_rk3568_pc/roc_rk3568_pc_smp.dts => firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.dts} (100%) create mode 100644 boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.yaml create mode 100644 boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig create mode 100644 boards/franzininho/esp32s2_franzininho/Kconfig.defconfig create mode 100644 boards/franzininho/esp32s2_franzininho/Kconfig.esp32s2_franzininho rename boards/{xtensa/esp32_ethernet_kit => franzininho/esp32s2_franzininho}/Kconfig.sysbuild (100%) rename boards/{xtensa => franzininho}/esp32s2_franzininho/board.cmake (100%) create mode 100644 boards/franzininho/esp32s2_franzininho/board.yml rename boards/{xtensa => franzininho}/esp32s2_franzininho/doc/img/esp32_s2_franzininho.jpg (100%) create mode 100644 boards/franzininho/esp32s2_franzininho/doc/index.rst rename boards/{xtensa => franzininho}/esp32s2_franzininho/esp32s2_franzininho-pinctrl.dtsi (100%) rename boards/{xtensa => franzininho}/esp32s2_franzininho/esp32s2_franzininho.dts (98%) rename boards/{xtensa => franzininho}/esp32s2_franzininho/esp32s2_franzininho.yaml (92%) create mode 100644 boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig rename boards/{xtensa/esp32s2_lolin_mini => franzininho/esp32s2_franzininho}/support/openocd.cfg (100%) create mode 100644 boards/franzininho/index.rst create mode 100644 boards/gaisler/generic_leon3/Kconfig.defconfig create mode 100644 boards/gaisler/generic_leon3/Kconfig.generic_leon3 rename boards/{sparc => gaisler}/generic_leon3/board.cmake (100%) create mode 100644 boards/gaisler/generic_leon3/board.yml rename boards/{sparc => gaisler}/generic_leon3/doc/index.rst (100%) rename boards/{sparc => gaisler}/generic_leon3/generic_leon3.dts (100%) rename boards/{sparc => gaisler}/generic_leon3/generic_leon3.yaml (100%) create mode 100644 boards/gaisler/generic_leon3/generic_leon3_defconfig create mode 100644 boards/gaisler/gr716a_mini/Kconfig.defconfig create mode 100644 boards/gaisler/gr716a_mini/Kconfig.gr716a_mini rename boards/{sparc => gaisler}/gr716a_mini/board.cmake (100%) create mode 100644 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boards/google/twinkie_v2/doc/index.rst rename boards/{arm/google_twinkie_v2 => google/twinkie_v2}/google_twinkie_v2.dts (100%) rename boards/{arm/google_twinkie_v2 => google/twinkie_v2}/google_twinkie_v2.yaml (100%) rename boards/{arm/google_twinkie_v2 => google/twinkie_v2}/google_twinkie_v2_defconfig (80%) create mode 100644 boards/hardkernel/index.rst create mode 100644 boards/hardkernel/odroid_go/Kconfig create mode 100644 boards/hardkernel/odroid_go/Kconfig.defconfig create mode 100644 boards/hardkernel/odroid_go/Kconfig.odroid_go rename boards/{xtensa/esp32s2_franzininho => hardkernel/odroid_go}/Kconfig.sysbuild (100%) rename boards/{xtensa/heltec_wifi_lora32_v2 => hardkernel/odroid_go}/board.cmake (100%) create mode 100644 boards/hardkernel/odroid_go/board.yml rename boards/{xtensa => hardkernel}/odroid_go/doc/img/odroid_go.jpg (100%) create mode 100644 boards/hardkernel/odroid_go/doc/index.rst rename boards/{xtensa => hardkernel}/odroid_go/odroid_go-pinctrl.dtsi (100%) create mode 100644 boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.dts create mode 100644 boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.yaml create mode 100644 boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig create mode 100644 boards/hardkernel/odroid_go/odroid_go_esp32_procpu.dts create mode 100644 boards/hardkernel/odroid_go/odroid_go_esp32_procpu.yaml create mode 100644 boards/hardkernel/odroid_go/odroid_go_esp32_procpu_defconfig rename boards/{xtensa => heltec}/heltec_wifi_lora32_v2/CMakeLists.txt (100%) create mode 100644 boards/heltec/heltec_wifi_lora32_v2/Kconfig create mode 100644 boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig create mode 100644 boards/heltec/heltec_wifi_lora32_v2/Kconfig.heltec_wifi_lora32_v2 rename boards/{xtensa/esp32s2_saola => heltec/heltec_wifi_lora32_v2}/Kconfig.sysbuild (100%) rename boards/{xtensa/odroid_go => heltec/heltec_wifi_lora32_v2}/board.cmake (100%) create mode 100644 boards/heltec/heltec_wifi_lora32_v2/board.yml rename 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boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.dts create mode 100644 boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.yaml create mode 100644 boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig create mode 100644 boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.dts create mode 100644 boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.yaml create mode 100644 boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu_defconfig rename boards/{xtensa/esp32s3_luatos_core => heltec/heltec_wireless_stick_lite_v3}/support/openocd.cfg (100%) create mode 100644 boards/heltec/index.rst create mode 100644 boards/holyiot/index.rst create mode 100644 boards/holyiot/yj16019/Kconfig.defconfig create mode 100644 boards/holyiot/yj16019/Kconfig.holyiot_yj16019 rename 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rename boards/{arm => infineon}/xmc47_relax_kit/doc/index.rst (100%) rename boards/{arm => infineon}/xmc47_relax_kit/doc/xmc47_relax_kit.jpg (100%) rename boards/{arm => infineon}/xmc47_relax_kit/xmc47_relax_kit-pinctrl.dtsi (100%) rename boards/{arm => infineon}/xmc47_relax_kit/xmc47_relax_kit.dts (100%) rename boards/{arm => infineon}/xmc47_relax_kit/xmc47_relax_kit.yaml (100%) create mode 100644 boards/infineon/xmc47_relax_kit/xmc47_relax_kit_defconfig create mode 100644 boards/innblue/index.rst create mode 100644 boards/innblue/innblue21/Kconfig.defconfig create mode 100644 boards/innblue/innblue21/Kconfig.innblue21 rename boards/{arm/nrf9160_innblue21 => innblue/innblue21}/board.cmake (100%) create mode 100644 boards/innblue/innblue21/board.yml rename boards/{arm/nrf9160_innblue21 => innblue/innblue21}/doc/img/nrf9160_innblue21.jpg (100%) create mode 100644 boards/innblue/innblue21/doc/index.rst rename boards/{arm/nrf9160_innblue21/nrf9160_innblue21_common-pinctrl.dtsi => innblue/innblue21/innblue21_common-pinctrl.dtsi} (100%) create mode 100644 boards/innblue/innblue21/innblue21_common.dtsi create mode 100644 boards/innblue/innblue21/innblue21_nrf9160.dts create mode 100644 boards/innblue/innblue21/innblue21_nrf9160.yaml create mode 100644 boards/innblue/innblue21/innblue21_nrf9160_defconfig create mode 100644 boards/innblue/innblue21/innblue21_nrf9160_ns.dts create mode 100644 boards/innblue/innblue21/innblue21_nrf9160_ns.yaml create mode 100644 boards/innblue/innblue21/innblue21_nrf9160_ns_defconfig rename boards/{arm/nrf9160_innblue21/nrf9160_innblue21_partition_conf.dtsi => innblue/innblue21/innblue21_partition_conf.dtsi} (100%) rename boards/{arm/nrf9131ek_nrf9131 => innblue/innblue21}/pre_dt_board.cmake (100%) create mode 100644 boards/innblue/innblue22/Kconfig.defconfig create mode 100644 boards/innblue/innblue22/Kconfig.innblue22 rename boards/{arm/nrf9160_innblue22 => innblue/innblue22}/board.cmake (100%) create mode 100644 boards/innblue/innblue22/board.yml rename boards/{arm/nrf9160_innblue22 => innblue/innblue22}/doc/img/nrf9160_innblue22.jpg (100%) create mode 100644 boards/innblue/innblue22/doc/index.rst rename boards/{arm/nrf9160_innblue22/nrf9160_innblue22_common-pinctrl.dtsi => innblue/innblue22/innblue22_common-pinctrl.dtsi} (100%) create mode 100644 boards/innblue/innblue22/innblue22_common.dtsi create mode 100644 boards/innblue/innblue22/innblue22_nrf9160.dts create mode 100644 boards/innblue/innblue22/innblue22_nrf9160.yaml create mode 100644 boards/innblue/innblue22/innblue22_nrf9160_defconfig create mode 100644 boards/innblue/innblue22/innblue22_nrf9160_ns.dts create mode 100644 boards/innblue/innblue22/innblue22_nrf9160_ns.yaml create mode 100644 boards/innblue/innblue22/innblue22_nrf9160_ns_defconfig rename boards/{arm/nrf9160_innblue22/nrf9160_innblue22_partition_conf.dtsi => innblue/innblue22/innblue22_partition_conf.dtsi} (100%) rename boards/{arm/nrf9151dk_nrf9151 => innblue/innblue22}/pre_dt_board.cmake (100%) create mode 100644 boards/intel/adl/CMakeLists.txt create mode 100644 boards/intel/adl/Kconfig.defconfig create mode 100644 boards/intel/adl/Kconfig.intel_adl_crb create mode 100644 boards/intel/adl/Kconfig.intel_adl_rvp rename boards/{x86/intel_adl => intel/adl}/board.cmake (100%) create mode 100644 boards/intel/adl/board.yml create mode 100644 boards/intel/adl/doc/index.rst rename boards/{x86/intel_adl => intel/adl}/intel_adl.dts (100%) rename boards/{x86/intel_adl => intel/adl}/intel_adl_crb.dts (100%) rename boards/{x86/intel_adl => intel/adl}/intel_adl_crb.yaml (100%) rename boards/{x86/intel_adl => intel/adl}/intel_adl_crb_defconfig (81%) rename boards/{x86/intel_adl => intel/adl}/intel_adl_rvp.dts (100%) rename boards/{x86/intel_adl => intel/adl}/intel_adl_rvp.yaml (100%) rename boards/{x86/intel_adl => intel/adl}/intel_adl_rvp_defconfig (81%) create mode 100644 boards/intel/adsp/Kconfig.defconfig create mode 100644 boards/intel/adsp/Kconfig.intel_adsp create mode 100644 boards/intel/adsp/board.cmake create mode 100644 boards/intel/adsp/board.yml rename boards/{xtensa/intel_adsp_cavs25 => intel/adsp}/doc/chromebooks_adsp.rst (98%) create mode 100644 boards/intel/adsp/doc/index.rst rename boards/{xtensa/intel_adsp_ace15_mtpm/doc/index.rst => intel/adsp/doc/intel_adsp_ace15_mtpm.rst} (100%) rename boards/{xtensa/intel_adsp_cavs25/doc/index.rst => intel/adsp/doc/intel_adsp_cavs25.rst} (100%) rename boards/{xtensa/intel_adsp_cavs25 => intel/adsp}/doc/intel_adsp_generic.rst (90%) rename boards/{xtensa/intel_adsp_ace15_mtpm => intel/adsp}/intel_adsp_ace15_mtpm.dts (100%) rename boards/{xtensa/intel_adsp_ace15_mtpm => intel/adsp}/intel_adsp_ace15_mtpm.yaml (84%) create mode 100644 boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig rename boards/{xtensa/intel_adsp_ace20_lnl => intel/adsp}/intel_adsp_ace20_lnl.dts (100%) rename boards/{xtensa/intel_adsp_ace20_lnl => intel/adsp}/intel_adsp_ace20_lnl.yaml (85%) create mode 100644 boards/intel/adsp/intel_adsp_ace20_lnl_defconfig rename boards/{xtensa/intel_adsp_cavs25 => intel/adsp}/intel_adsp_cavs25.dts (100%) rename boards/{xtensa/intel_adsp_cavs25 => intel/adsp}/intel_adsp_cavs25.yaml (87%) rename boards/{xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.dts => intel/adsp/intel_adsp_cavs25_cavs25_tgph.dts} (100%) rename boards/{xtensa/intel_adsp_cavs25 => intel/adsp}/intel_adsp_cavs25_defconfig (76%) rename boards/{xtensa/intel_adsp_cavs25 => intel/adsp}/intel_adsp_cavs25_tgph.yaml (86%) create mode 100644 boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig create mode 100644 boards/intel/adsp/pre_dt_board.cmake rename boards/{x86 => intel}/common/efi_boot.rst (100%) rename boards/{x86 => intel}/common/net_boot.rst (100%) rename boards/{x86 => intel}/common/scripts/build_grub.sh (100%) create mode 100644 boards/intel/ehl/CMakeLists.txt create mode 100644 boards/intel/ehl/Kconfig.defconfig create mode 100644 boards/intel/ehl/Kconfig.intel_ehl_crb rename boards/{x86/intel_ehl => intel/ehl}/board.cmake (100%) create mode 100644 boards/intel/ehl/board.yml create mode 100644 boards/intel/ehl/doc/index.rst rename boards/{x86/intel_ehl => intel/ehl}/intel_ehl_crb.dts (100%) rename boards/{x86/intel_ehl => intel/ehl}/intel_ehl_crb.yaml (100%) rename boards/{x86/intel_ehl => intel/ehl}/intel_ehl_crb_defconfig (80%) rename boards/{x86/intel_ehl => intel/ehl}/intel_ehl_crb_sbl.dts (100%) rename boards/{x86/intel_ehl => intel/ehl}/intel_ehl_crb_sbl.yaml (78%) rename boards/{x86/intel_ehl => intel/ehl}/intel_ehl_crb_sbl_defconfig (75%) create mode 100644 boards/intel/index.rst create mode 100644 boards/intel/ish/Kconfig.defconfig create mode 100644 boards/intel/ish/Kconfig.intel_ish_5_4_1 create mode 100644 boards/intel/ish/Kconfig.intel_ish_5_6_0 create mode 100644 boards/intel/ish/Kconfig.intel_ish_5_8_0 create mode 100644 boards/intel/ish/board.yml create mode 100644 boards/intel/ish/doc/index.rst rename boards/{x86/intel_ish => intel/ish}/intel_ish_5_4_1.dts (100%) rename boards/{x86/intel_ish => intel/ish}/intel_ish_5_4_1.yaml (100%) create mode 100644 boards/intel/ish/intel_ish_5_4_1_defconfig rename boards/{x86/intel_ish => intel/ish}/intel_ish_5_6_0.dts (100%) rename boards/{x86/intel_ish => intel/ish}/intel_ish_5_6_0.yaml (100%) create mode 100644 boards/intel/ish/intel_ish_5_6_0_defconfig rename boards/{x86/intel_ish => intel/ish}/intel_ish_5_8_0.dts (100%) rename boards/{x86/intel_ish => intel/ish}/intel_ish_5_8_0.yaml (100%) create mode 100644 boards/intel/ish/intel_ish_5_8_0_defconfig create mode 100644 boards/intel/niosv_g/Kconfig.niosv_g create mode 100644 boards/intel/niosv_g/board.yml rename boards/{riscv => intel}/niosv_g/doc/index.rst (100%) rename boards/{riscv => intel}/niosv_g/niosv_g.dts (100%) rename boards/{riscv => intel}/niosv_g/niosv_g.yaml (100%) create mode 100644 boards/intel/niosv_g/niosv_g_defconfig create mode 100644 boards/intel/niosv_m/Kconfig.niosv_m create mode 100644 boards/intel/niosv_m/board.yml rename boards/{riscv => intel}/niosv_m/doc/index.rst (100%) rename boards/{riscv => intel}/niosv_m/niosv_m.dts (100%) rename boards/{riscv => intel}/niosv_m/niosv_m.yaml (100%) create mode 100644 boards/intel/niosv_m/niosv_m_defconfig create mode 100644 boards/intel/rpl/CMakeLists.txt create mode 100644 boards/intel/rpl/Kconfig.defconfig create mode 100644 boards/intel/rpl/Kconfig.intel_rpl_p_crb create mode 100644 boards/intel/rpl/Kconfig.intel_rpl_s_crb rename boards/{x86/intel_rpl => intel/rpl}/board.cmake (100%) create mode 100644 boards/intel/rpl/board.yml create mode 100644 boards/intel/rpl/doc/index.rst rename boards/{x86/intel_rpl => intel/rpl}/intel_rpl_p_crb.dts (100%) rename boards/{x86/intel_rpl => intel/rpl}/intel_rpl_p_crb.yaml (100%) rename boards/{x86/intel_rpl => intel/rpl}/intel_rpl_p_crb_defconfig (82%) rename boards/{x86/intel_rpl => intel/rpl}/intel_rpl_s_crb.dts (100%) rename boards/{x86/intel_rpl => intel/rpl}/intel_rpl_s_crb.yaml (100%) rename boards/{x86/intel_rpl => intel/rpl}/intel_rpl_s_crb_defconfig (82%) create mode 100644 boards/intel/socfpga/agilex5_socdk/Kconfig.defconfig create mode 100644 boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk create mode 100644 boards/intel/socfpga/agilex5_socdk/board.yml create mode 100644 boards/intel/socfpga/agilex5_socdk/doc/index.rst rename boards/{arm64/intel_socfpga_agilex5_socdk => intel/socfpga/agilex5_socdk}/intel_socfpga_agilex5_socdk.dts (100%) rename boards/{arm64/intel_socfpga_agilex5_socdk => intel/socfpga/agilex5_socdk}/intel_socfpga_agilex5_socdk.yaml (100%) rename boards/{arm64/intel_socfpga_agilex5_socdk => intel/socfpga/agilex5_socdk}/intel_socfpga_agilex5_socdk_defconfig (84%) create mode 100644 boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk create mode 100644 boards/intel/socfpga/agilex_socdk/board.yml create mode 100644 boards/intel/socfpga/agilex_socdk/doc/index.rst rename boards/{arm64/intel_socfpga_agilex_socdk => intel/socfpga/agilex_socdk}/intel_socfpga_agilex_socdk.dts (100%) rename boards/{arm64/intel_socfpga_agilex_socdk => intel/socfpga/agilex_socdk}/intel_socfpga_agilex_socdk.yaml (100%) rename boards/{arm64/intel_socfpga_agilex_socdk => intel/socfpga/agilex_socdk}/intel_socfpga_agilex_socdk_defconfig (77%) create mode 100644 boards/intel/socfpga_std/cyclonev_socdk/Kconfig.cyclonev_socdk create mode 100644 boards/intel/socfpga_std/cyclonev_socdk/Kconfig.defconfig create mode 100644 boards/intel/socfpga_std/cyclonev_socdk/board.cmake create mode 100644 boards/intel/socfpga_std/cyclonev_socdk/board.yml rename boards/{arm => intel/socfpga_std}/cyclonev_socdk/cyclonev_socdk.dts (92%) rename boards/{arm => intel/socfpga_std}/cyclonev_socdk/cyclonev_socdk.yaml (100%) create mode 100644 boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk_defconfig rename boards/{arm => intel/socfpga_std}/cyclonev_socdk/doc/img/cv_soc_board.jpg (100%) rename boards/{arm => intel/socfpga_std}/cyclonev_socdk/doc/img/cyclonev_blinky.jpg (100%) rename boards/{arm => intel/socfpga_std}/cyclonev_socdk/doc/img/cyclonev_westflash.jpg (100%) create mode 100644 boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst rename boards/{arm => intel/socfpga_std}/cyclonev_socdk/support/altera-usb-blaster2-cyclonev.cfg (100%) rename boards/{arm => intel/socfpga_std}/cyclonev_socdk/support/appli_debug_cmd.gdb (100%) rename boards/{arm => intel/socfpga_std}/cyclonev_socdk/support/appli_dl_cmd.gdb (100%) rename boards/{arm => intel/socfpga_std}/cyclonev_socdk/support/blaster_6810.hex (100%) create mode 100644 boards/intel/socfpga_std/cyclonev_socdk/support/download_all.gdb rename boards/{arm => intel/socfpga_std}/cyclonev_socdk/support/openocd.cfg (100%) create mode 100644 boards/intel/socfpga_std/cyclonev_socdk/support/preloader_dl_cmd.txt create mode 100644 boards/ite/index.rst create mode 100644 boards/ite/it82xx2_evb/Kconfig.defconfig create mode 100644 boards/ite/it82xx2_evb/Kconfig.it82xx2_evb create mode 100644 boards/ite/it82xx2_evb/board.yml rename boards/{riscv => ite}/it82xx2_evb/doc/WinFlashTool_P1.jpg (100%) rename boards/{riscv => ite}/it82xx2_evb/doc/WinFlashTool_P2.jpg (100%) rename boards/{riscv => ite}/it82xx2_evb/doc/WinFlashTool_P3.jpg (100%) rename boards/{riscv => ite}/it82xx2_evb/doc/WinFlashTool_P4.jpg (100%) create mode 100644 boards/ite/it82xx2_evb/doc/index.rst rename boards/{riscv => ite}/it82xx2_evb/doc/it82xx2_evb_and_debug_card.jpg (100%) rename boards/{riscv => ite}/it82xx2_evb/doc/it82xx2_evb_wiring.jpg (100%) rename boards/{riscv => ite}/it82xx2_evb/it82xx2_evb.dts (100%) rename boards/{riscv => ite}/it82xx2_evb/it82xx2_evb.yaml (100%) rename boards/{riscv => ite}/it82xx2_evb/it82xx2_evb_defconfig (81%) create mode 100644 boards/ite/it8xxx2_evb/Kconfig.defconfig create mode 100644 boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb rename boards/{riscv => ite}/it8xxx2_evb/board.cmake (100%) create mode 100644 boards/ite/it8xxx2_evb/board.yml rename boards/{riscv => ite}/it8xxx2_evb/doc/WinFlashTool_P1.jpg (100%) rename boards/{riscv => ite}/it8xxx2_evb/doc/WinFlashTool_P2.jpg (100%) rename boards/{riscv => ite}/it8xxx2_evb/doc/WinFlashTool_P3.jpg (100%) rename boards/{riscv => ite}/it8xxx2_evb/doc/WinFlashTool_P4.jpg (100%) create mode 100644 boards/ite/it8xxx2_evb/doc/index.rst rename boards/{riscv => ite}/it8xxx2_evb/doc/it8xxx2_evb_and_debug_card.jpg (100%) rename boards/{riscv => ite}/it8xxx2_evb/doc/it8xxx2_evb_wiring.jpg (100%) rename boards/{riscv => ite}/it8xxx2_evb/it8xxx2_evb.dts (100%) rename boards/{riscv => ite}/it8xxx2_evb/it8xxx2_evb.yaml (100%) rename boards/{riscv => ite}/it8xxx2_evb/it8xxx2_evb_defconfig (83%) rename boards/{riscv => ite}/it8xxx2_evb/support/it8xxx2_evb.resc (100%) rename boards/{arm/frdm_k82f => khadas/edgev}/CMakeLists.txt (100%) create mode 100644 boards/khadas/edgev/Kconfig.khadas_edgev rename boards/{arm64/khadas_edgev => khadas/edgev}/board.cmake (100%) create mode 100644 boards/khadas/edgev/board.yml create mode 100644 boards/khadas/edgev/doc/index.rst rename boards/{arm64/khadas_edgev => khadas/edgev}/khadas_edgev.dts (100%) rename boards/{arm64/khadas_edgev => khadas/edgev}/khadas_edgev.yaml (100%) rename boards/{arm64/khadas_edgev => khadas/edgev}/khadas_edgev_defconfig (81%) create mode 100644 boards/khadas/index.rst create mode 100644 boards/kincony/index.rst create mode 100644 boards/kincony/kincony_kc868_a32/Kconfig create mode 100644 boards/kincony/kincony_kc868_a32/Kconfig.defconfig create mode 100644 boards/kincony/kincony_kc868_a32/Kconfig.kincony_kc868_a32 rename boards/{xtensa => kincony}/kincony_kc868_a32/Kconfig.sysbuild (100%) rename boards/{xtensa => kincony}/kincony_kc868_a32/board.cmake (100%) create mode 100644 boards/kincony/kincony_kc868_a32/board.yml rename boards/{xtensa => kincony}/kincony_kc868_a32/doc/img/kincony_kc868_a32.jpg (100%) create mode 100644 boards/kincony/kincony_kc868_a32/doc/index.rst rename boards/{xtensa => kincony}/kincony_kc868_a32/kincony_kc868_a32-pinctrl.dtsi (100%) create mode 100644 boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.dts create mode 100644 boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.yaml create mode 100644 boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig create mode 100644 boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.dts create mode 100644 boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.yaml create mode 100644 boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu_defconfig rename boards/{xtensa => kincony}/kincony_kc868_a32/support/openocd.cfg (100%) create mode 100644 boards/lairdconnect/bl5340_dvk/CMakeLists.txt create mode 100644 boards/lairdconnect/bl5340_dvk/Kconfig create mode 100644 boards/lairdconnect/bl5340_dvk/Kconfig.bl5340_dvk create mode 100644 boards/lairdconnect/bl5340_dvk/Kconfig.defconfig create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml rename boards/{arm/bl5340_dvk/bl5340_dvk_cpuapp_common-pinctrl.dtsi => lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi} (100%) create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi rename boards/{arm/bl5340_dvk/bl5340_dvk_cpunet-pinctrl.dtsi => lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi} (100%) create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi create mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig rename boards/{arm/bl5340_dvk/bl5340_dvk_cpunet_reset.c => lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c} (100%) rename boards/{arm/frdm_kl25z/CMakeLists.txt => lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_defconfig} (100%) rename boards/{arm/bl5340_dvk/bl5340_dvk_shared_sram_planning_conf.dtsi => lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi} (100%) create mode 100644 boards/lairdconnect/bl5340_dvk/board.cmake create mode 100644 boards/lairdconnect/bl5340_dvk/board.yml rename boards/{arm => lairdconnect}/bl5340_dvk/doc/img/bl5340_dvk_top.jpg (100%) create mode 100644 boards/lairdconnect/bl5340_dvk/doc/index.rst rename boards/{arm => lairdconnect}/bl5340_dvk/pre_dt_board.cmake (100%) rename boards/{arm => lairdconnect}/bl652_dvk/Kconfig (100%) create mode 100644 boards/lairdconnect/bl652_dvk/Kconfig.bl652_dvk create mode 100644 boards/lairdconnect/bl652_dvk/Kconfig.defconfig rename boards/{arm => lairdconnect}/bl652_dvk/bl652_dvk-pinctrl.dtsi (100%) rename boards/{arm => lairdconnect}/bl652_dvk/bl652_dvk.dts (100%) rename boards/{arm => lairdconnect}/bl652_dvk/bl652_dvk.yaml (100%) rename boards/{arm => lairdconnect}/bl652_dvk/bl652_dvk_defconfig (81%) rename boards/{arm => lairdconnect}/bl652_dvk/board.cmake (100%) create mode 100644 boards/lairdconnect/bl652_dvk/board.yml rename boards/{arm => lairdconnect}/bl652_dvk/doc/bl652_dvk.rst (99%) rename boards/{arm => lairdconnect}/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg (100%) rename boards/{arm => lairdconnect}/bl652_dvk/doc/img/bl652_dvk.jpg (100%) rename boards/{arm/bt610 => lairdconnect/bl652_dvk}/pre_dt_board.cmake (100%) rename boards/{arm => lairdconnect}/bl653_dvk/Kconfig (100%) create mode 100644 boards/lairdconnect/bl653_dvk/Kconfig.bl653_dvk create mode 100644 boards/lairdconnect/bl653_dvk/Kconfig.defconfig rename boards/{arm => lairdconnect}/bl653_dvk/bl653_dvk-pinctrl.dtsi (100%) rename boards/{arm => lairdconnect}/bl653_dvk/bl653_dvk.dts (100%) rename boards/{arm => lairdconnect}/bl653_dvk/bl653_dvk.yaml (100%) rename boards/{arm => lairdconnect}/bl653_dvk/bl653_dvk_defconfig (80%) rename boards/{arm => lairdconnect}/bl653_dvk/board.cmake (100%) create mode 100644 boards/lairdconnect/bl653_dvk/board.yml rename boards/{arm => lairdconnect}/bl653_dvk/doc/bl653_dvk.rst (99%) rename boards/{arm => lairdconnect}/bl653_dvk/doc/img/bl653_dvk.jpg (100%) rename boards/{arm/contextualelectronics_abc => lairdconnect/bl653_dvk}/pre_dt_board.cmake (100%) rename boards/{arm => lairdconnect}/bl654_dvk/Kconfig (100%) create mode 100644 boards/lairdconnect/bl654_dvk/Kconfig.bl654_dvk create mode 100644 boards/lairdconnect/bl654_dvk/Kconfig.defconfig rename boards/{arm => lairdconnect}/bl654_dvk/bl654_dvk-pinctrl.dtsi (100%) rename boards/{arm => lairdconnect}/bl654_dvk/bl654_dvk.dts (100%) rename boards/{arm => lairdconnect}/bl654_dvk/bl654_dvk.yaml (100%) rename boards/{arm => lairdconnect}/bl654_dvk/bl654_dvk_defconfig (81%) rename boards/{arm => lairdconnect}/bl654_dvk/board.cmake (100%) create mode 100644 boards/lairdconnect/bl654_dvk/board.yml rename boards/{arm => lairdconnect}/bl654_dvk/doc/bl654_dvk.rst (98%) rename boards/{arm => lairdconnect}/bl654_dvk/doc/img/455-00001_BoxContents.jpg (100%) rename boards/{arm => lairdconnect}/bl654_dvk/doc/img/bl654_dvk.jpg (100%) rename boards/{arm/decawave_dwm1001_dev => lairdconnect/bl654_dvk}/pre_dt_board.cmake (100%) rename boards/{arm => lairdconnect}/bl654_sensor_board/Kconfig (100%) create mode 100644 boards/lairdconnect/bl654_sensor_board/Kconfig.bl654_sensor_board create mode 100644 boards/lairdconnect/bl654_sensor_board/Kconfig.defconfig rename boards/{arm => lairdconnect}/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi (100%) rename boards/{arm => lairdconnect}/bl654_sensor_board/bl654_sensor_board.dts (100%) rename boards/{arm => lairdconnect}/bl654_sensor_board/bl654_sensor_board.yaml (100%) rename boards/{arm => lairdconnect}/bl654_sensor_board/bl654_sensor_board_defconfig (77%) rename boards/{arm => lairdconnect}/bl654_sensor_board/board.cmake (100%) create mode 100644 boards/lairdconnect/bl654_sensor_board/board.yml rename boards/{arm => lairdconnect}/bl654_sensor_board/doc/bl654_sensor_board.rst (99%) rename boards/{arm => lairdconnect}/bl654_sensor_board/doc/img/bl654_sensor_board.jpg (100%) rename boards/{arm => lairdconnect}/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg (100%) rename boards/{arm/degu_evk => lairdconnect/bl654_sensor_board}/pre_dt_board.cmake (100%) rename boards/{arm => lairdconnect}/bl654_usb/Kconfig (100%) create mode 100644 boards/lairdconnect/bl654_usb/Kconfig.bl654_usb create mode 100644 boards/lairdconnect/bl654_usb/Kconfig.defconfig rename boards/{arm => lairdconnect}/bl654_usb/bl654_usb-pinctrl.dtsi (100%) rename boards/{arm => lairdconnect}/bl654_usb/bl654_usb.dts (100%) rename boards/{arm => lairdconnect}/bl654_usb/bl654_usb.yaml (100%) rename boards/{arm => lairdconnect}/bl654_usb/bl654_usb_defconfig (79%) create mode 100644 boards/lairdconnect/bl654_usb/board.yml rename boards/{arm => lairdconnect}/bl654_usb/doc/bl654_usb.rst (95%) rename boards/{arm => lairdconnect}/bl654_usb/doc/img/bl654_usb.jpg (100%) rename boards/{arm => lairdconnect}/bl654_usb/doc/img/bl654_usb_pcb.jpg (100%) rename boards/{arm => lairdconnect}/bl654_usb/doc/img/bl654_usb_reset.jpg (100%) rename boards/{arm/holyiot_yj16019 => lairdconnect/bl654_usb}/pre_dt_board.cmake (100%) rename boards/{arm => lairdconnect}/bt510/Kconfig (100%) create mode 100644 boards/lairdconnect/bt510/Kconfig.bt510 create mode 100644 boards/lairdconnect/bt510/Kconfig.defconfig rename boards/{arm => lairdconnect}/bt510/board.cmake (100%) create mode 100644 boards/lairdconnect/bt510/board.yml rename boards/{arm => lairdconnect}/bt510/bt510-pinctrl.dtsi (100%) rename boards/{arm => lairdconnect}/bt510/bt510.dts (100%) rename boards/{arm => lairdconnect}/bt510/bt510.yaml (100%) rename boards/{arm => lairdconnect}/bt510/bt510_defconfig (79%) rename boards/{arm => lairdconnect}/bt510/doc/bt510.rst (99%) rename boards/{arm => lairdconnect}/bt510/doc/img/bt510.jpg (100%) rename boards/{arm => lairdconnect}/bt510/doc/img/bt510_back.jpg (100%) rename boards/{arm => lairdconnect}/bt510/doc/img/bt510_prog.jpg (100%) rename boards/{arm/mg100 => lairdconnect/bt510}/pre_dt_board.cmake (100%) rename boards/{arm => lairdconnect}/bt610/Kconfig (100%) create mode 100644 boards/lairdconnect/bt610/Kconfig.bt610 create mode 100644 boards/lairdconnect/bt610/Kconfig.defconfig rename boards/{arm => lairdconnect}/bt610/board.cmake (100%) create mode 100644 boards/lairdconnect/bt610/board.yml rename boards/{arm => lairdconnect}/bt610/bt610-pinctrl.dtsi (100%) rename boards/{arm => lairdconnect}/bt610/bt610.dts (100%) rename boards/{arm => lairdconnect}/bt610/bt610.yaml (100%) rename boards/{arm => lairdconnect}/bt610/bt610_defconfig (82%) rename boards/{arm => lairdconnect}/bt610/doc/bt610.rst (99%) rename boards/{arm => lairdconnect}/bt610/doc/img/bt610_back.jpg (100%) rename boards/{arm => lairdconnect}/bt610/doc/img/bt610_board.jpg (100%) rename boards/{arm => lairdconnect}/bt610/doc/img/bt610_front.jpg (100%) rename boards/{arm/nrf21540dk_nrf52840 => lairdconnect/bt610}/pre_dt_board.cmake (100%) create mode 100644 boards/lairdconnect/index.rst rename boards/{arm => lairdconnect}/mg100/Kconfig (100%) create mode 100644 boards/lairdconnect/mg100/Kconfig.defconfig create mode 100644 boards/lairdconnect/mg100/Kconfig.mg100 rename boards/{arm => lairdconnect}/mg100/board.cmake (100%) create mode 100644 boards/lairdconnect/mg100/board.yml rename boards/{arm => lairdconnect}/mg100/doc/img/mg100.jpg (100%) create mode 100644 boards/lairdconnect/mg100/doc/index.rst rename boards/{arm => lairdconnect}/mg100/mg100-pinctrl.dtsi (100%) rename boards/{arm => lairdconnect}/mg100/mg100.dts (100%) rename boards/{arm => lairdconnect}/mg100/mg100.yaml (100%) rename boards/{arm => lairdconnect}/mg100/mg100_defconfig (81%) rename boards/{arm/nrf52832_mdk => lairdconnect/mg100}/pre_dt_board.cmake (100%) rename boards/{arm => lairdconnect}/pinnacle_100_dvk/Kconfig (100%) create mode 100644 boards/lairdconnect/pinnacle_100_dvk/Kconfig.defconfig create mode 100644 boards/lairdconnect/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk rename boards/{arm => lairdconnect}/pinnacle_100_dvk/board.cmake (100%) create mode 100644 boards/lairdconnect/pinnacle_100_dvk/board.yml rename boards/{arm => lairdconnect}/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg (100%) create mode 100644 boards/lairdconnect/pinnacle_100_dvk/doc/index.rst rename boards/{arm => lairdconnect}/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi (100%) rename boards/{arm => lairdconnect}/pinnacle_100_dvk/pinnacle_100_dvk.dts (100%) rename boards/{arm => lairdconnect}/pinnacle_100_dvk/pinnacle_100_dvk.yaml (100%) rename boards/{arm => lairdconnect}/pinnacle_100_dvk/pinnacle_100_dvk_defconfig (81%) rename boards/{arm/nrf52833dk_nrf52820 => lairdconnect/pinnacle_100_dvk}/pre_dt_board.cmake (100%) create mode 100644 boards/lairdconnect/rm1xx_dvk/Kconfig.defconfig create mode 100644 boards/lairdconnect/rm1xx_dvk/Kconfig.rm1xx_dvk rename boards/{arm => lairdconnect}/rm1xx_dvk/board.cmake (100%) create mode 100644 boards/lairdconnect/rm1xx_dvk/board.yml rename boards/{arm => lairdconnect}/rm1xx_dvk/doc/img/RM186-DVK.jpg (100%) rename boards/{arm => lairdconnect}/rm1xx_dvk/doc/img/RM186-SM.jpg (100%) rename boards/{arm => lairdconnect}/rm1xx_dvk/doc/index.rst (100%) rename boards/{arm/bbc_microbit => lairdconnect/rm1xx_dvk}/pre_dt_board.cmake (100%) rename boards/{arm => lairdconnect}/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi (100%) rename boards/{arm => lairdconnect}/rm1xx_dvk/rm1xx_dvk.dts (100%) rename boards/{arm => lairdconnect}/rm1xx_dvk/rm1xx_dvk.yaml (100%) create mode 100644 boards/lairdconnect/rm1xx_dvk/rm1xx_dvk_defconfig create mode 100644 boards/lowrisc/index.rst create mode 100644 boards/lowrisc/opentitan_earlgrey/Kconfig.opentitan_earlgrey create mode 100644 boards/lowrisc/opentitan_earlgrey/board.yml rename boards/{riscv => lowrisc}/opentitan_earlgrey/doc/index.rst (100%) rename boards/{riscv => lowrisc}/opentitan_earlgrey/opentitan_earlgrey.dts (100%) rename boards/{riscv => lowrisc}/opentitan_earlgrey/opentitan_earlgrey.yaml (100%) create mode 100644 boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey_defconfig create mode 100644 boards/luatos/esp32c3_luatos_core/Kconfig.defconfig create mode 100644 boards/luatos/esp32c3_luatos_core/Kconfig.esp32c3_luatos_core rename boards/{xtensa/esp32s3_luatos_core => luatos/esp32c3_luatos_core}/Kconfig.sysbuild (100%) rename boards/{riscv => luatos}/esp32c3_luatos_core/board.cmake (100%) create mode 100644 boards/luatos/esp32c3_luatos_core/board.yml rename boards/{riscv => luatos}/esp32c3_luatos_core/doc/img/esp32c3_luatos_core.jpg (100%) rename boards/{riscv => luatos}/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_pinfunc.jpg (100%) rename boards/{riscv => luatos}/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_usb.jpg (100%) create mode 100644 boards/luatos/esp32c3_luatos_core/doc/index.rst rename boards/{riscv => luatos}/esp32c3_luatos_core/esp32c3_luatos_core-pinctrl.dtsi (100%) rename boards/{riscv => luatos}/esp32c3_luatos_core/esp32c3_luatos_core.dts (100%) rename boards/{riscv => luatos}/esp32c3_luatos_core/esp32c3_luatos_core.dtsi (98%) rename boards/{riscv => luatos}/esp32c3_luatos_core/esp32c3_luatos_core.yaml (80%) create mode 100644 boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig rename boards/{riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb.dts => luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.dts} (100%) create mode 100644 boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml create mode 100644 boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig rename boards/{riscv => luatos}/esp32c3_luatos_core/support/openocd.cfg (100%) create mode 100644 boards/luatos/esp32s3_luatos_core/Kconfig create mode 100644 boards/luatos/esp32s3_luatos_core/Kconfig.defconfig create mode 100644 boards/luatos/esp32s3_luatos_core/Kconfig.esp32s3_luatos_core rename boards/{xtensa/esp_wrover_kit => luatos/esp32s3_luatos_core}/Kconfig.sysbuild (100%) rename boards/{xtensa/esp32s2_saola => luatos/esp32s3_luatos_core}/board.cmake (100%) create mode 100644 boards/luatos/esp32s3_luatos_core/board.yml rename boards/{xtensa => luatos}/esp32s3_luatos_core/doc/img/esp32s3_luatos_core.jpg (100%) rename boards/{xtensa => luatos}/esp32s3_luatos_core/doc/img/esp32s3_luatos_core_pinout.jpg (100%) create mode 100644 boards/luatos/esp32s3_luatos_core/doc/index.rst rename boards/{xtensa => luatos}/esp32s3_luatos_core/esp32s3_luatos_core-pinctrl.dtsi (100%) rename boards/{xtensa => luatos}/esp32s3_luatos_core/esp32s3_luatos_core.dtsi (100%) create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.dts create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.yaml create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_defconfig create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.dts create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.yaml create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.dts create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.yaml create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_defconfig create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.dts create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.yaml create mode 100644 boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb_defconfig rename boards/{xtensa/heltec_wireless_stick_lite_v3 => luatos/esp32s3_luatos_core}/support/openocd.cfg (100%) create mode 100644 boards/luatos/index.rst create mode 100644 boards/m5stack/index.rst create mode 100644 boards/m5stack/m5stack_atoms3/Kconfig create mode 100644 boards/m5stack/m5stack_atoms3/Kconfig.defconfig create mode 100644 boards/m5stack/m5stack_atoms3/Kconfig.m5stack_atoms3 rename boards/{xtensa/heltec_wifi_lora32_v2 => m5stack/m5stack_atoms3}/Kconfig.sysbuild (100%) rename boards/{xtensa/esp32s3_devkitm => m5stack/m5stack_atoms3}/board.cmake (100%) create mode 100644 boards/m5stack/m5stack_atoms3/board.yml rename boards/{xtensa => m5stack}/m5stack_atoms3/doc/img/m5stack_atoms3.webp (100%) create mode 100644 boards/m5stack/m5stack_atoms3/doc/index.rst rename boards/{xtensa => m5stack}/m5stack_atoms3/grove_connectors.dtsi (100%) rename boards/{xtensa => m5stack}/m5stack_atoms3/m5stack_atoms3-pinctrl.dtsi (100%) create mode 100644 boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.dts create mode 100644 boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.yaml create mode 100644 boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig create mode 100644 boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.dts create mode 100644 boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.yaml create mode 100644 boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu_defconfig create mode 100644 boards/m5stack/m5stack_atoms3_lite/Kconfig create mode 100644 boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig create mode 100644 boards/m5stack/m5stack_atoms3_lite/Kconfig.m5stack_atoms3_lite rename boards/{xtensa/heltec_wireless_stick_lite_v3 => m5stack/m5stack_atoms3_lite}/Kconfig.sysbuild (100%) rename boards/{xtensa/esp32s3_luatos_core => m5stack/m5stack_atoms3_lite}/board.cmake (100%) create mode 100644 boards/m5stack/m5stack_atoms3_lite/board.yml rename boards/{xtensa => m5stack}/m5stack_atoms3_lite/doc/img/m5stack_atoms3_lite.webp (100%) create mode 100644 boards/m5stack/m5stack_atoms3_lite/doc/index.rst rename boards/{xtensa => m5stack}/m5stack_atoms3_lite/grove_connectors.dtsi (100%) rename boards/{xtensa => m5stack}/m5stack_atoms3_lite/m5stack_atoms3_lite-pinctrl.dtsi (100%) create mode 100644 boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.dts create mode 100644 boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.yaml create mode 100644 boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu_defconfig create mode 100644 boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.dts create mode 100644 boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.yaml create mode 100644 boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu_defconfig create mode 100644 boards/m5stack/m5stack_core2/Kconfig create mode 100644 boards/m5stack/m5stack_core2/Kconfig.defconfig create mode 100644 boards/m5stack/m5stack_core2/Kconfig.m5stack_core2 rename boards/{xtensa/esp_wrover_kit => m5stack/m5stack_core2}/board.cmake (100%) create mode 100644 boards/m5stack/m5stack_core2/board.yml rename boards/{xtensa => m5stack}/m5stack_core2/doc/img/m5stack_core2.webp (100%) create mode 100644 boards/m5stack/m5stack_core2/doc/index.rst rename boards/{xtensa => m5stack}/m5stack_core2/grove_connectors.dtsi (100%) rename boards/{xtensa => m5stack}/m5stack_core2/m5stack_core2-pinctrl.dtsi (100%) create mode 100644 boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.dts create mode 100644 boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.yaml create mode 100644 boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig create mode 100644 boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.dts create mode 100644 boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.yaml create mode 100644 boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu_defconfig rename boards/{xtensa => m5stack}/m5stack_core2/m5stack_mbus_connectors.dtsi (100%) rename boards/{xtensa => m5stack}/m5stack_core2/support/openocd.cfg (100%) create mode 100644 boards/m5stack/m5stack_stamps3/Kconfig create mode 100644 boards/m5stack/m5stack_stamps3/Kconfig.defconfig create mode 100644 boards/m5stack/m5stack_stamps3/Kconfig.m5stack_stamps3 rename boards/{xtensa/heltec_wireless_stick_lite_v3 => m5stack/m5stack_stamps3}/board.cmake (100%) create mode 100644 boards/m5stack/m5stack_stamps3/board.yml rename boards/{xtensa => m5stack}/m5stack_stamps3/doc/img/m5stack_stamps3.webp (100%) rename boards/{xtensa => m5stack}/m5stack_stamps3/doc/img/m5stack_stamps3_header.webp (100%) create mode 100644 boards/m5stack/m5stack_stamps3/doc/index.rst rename boards/{xtensa => m5stack}/m5stack_stamps3/m5stack_stamps3-pinctrl.dtsi (100%) rename boards/{xtensa => m5stack}/m5stack_stamps3/m5stack_stamps3_connectors.dtsi (100%) create mode 100644 boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.dts create mode 100644 boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.yaml create mode 100644 boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig create mode 100644 boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.dts create mode 100644 boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.yaml create mode 100644 boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu_defconfig create mode 100644 boards/m5stack/m5stickc_plus/Kconfig create mode 100644 boards/m5stack/m5stickc_plus/Kconfig.defconfig create mode 100644 boards/m5stack/m5stickc_plus/Kconfig.m5stickc_plus rename boards/{xtensa/m5stack_atoms3_lite => m5stack/m5stickc_plus}/Kconfig.sysbuild (100%) rename boards/{xtensa => m5stack}/m5stickc_plus/board.cmake (100%) create mode 100644 boards/m5stack/m5stickc_plus/board.yml create mode 100644 boards/m5stack/m5stickc_plus/doc/index.rst rename boards/{xtensa => m5stack}/m5stickc_plus/m5stickc_plus-pinctrl.dtsi (100%) create mode 100644 boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.dts create mode 100644 boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.yaml create mode 100644 boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig create mode 100644 boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.dts create mode 100644 boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.yaml create mode 100644 boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu_defconfig rename boards/{xtensa => m5stack}/m5stickc_plus/support/openocd.cfg (100%) create mode 100644 boards/m5stack/stamp_c3/Kconfig.defconfig create mode 100644 boards/m5stack/stamp_c3/Kconfig.stamp_c3 rename boards/{xtensa/m5stickc_plus => m5stack/stamp_c3}/Kconfig.sysbuild (100%) rename boards/{xtensa/m5stack_atoms3 => m5stack/stamp_c3}/board.cmake (100%) create mode 100644 boards/m5stack/stamp_c3/board.yml create mode 100644 boards/m5stack/stamp_c3/doc/index.rst rename boards/{riscv => m5stack}/stamp_c3/stamp_c3-pinctrl.dtsi (100%) rename boards/{riscv => m5stack}/stamp_c3/stamp_c3.dts (100%) rename boards/{riscv => m5stack}/stamp_c3/stamp_c3.yaml (100%) create mode 100644 boards/m5stack/stamp_c3/stamp_c3_defconfig rename boards/{riscv => m5stack}/stamp_c3/support/openocd.cfg (100%) create mode 100644 boards/madmachine/index.rst create mode 100644 boards/madmachine/mm_feather/CMakeLists.txt create mode 100644 boards/madmachine/mm_feather/Kconfig.defconfig create mode 100644 boards/madmachine/mm_feather/Kconfig.mm_feather rename boards/{arm => madmachine}/mm_feather/board.cmake (100%) create mode 100644 boards/madmachine/mm_feather/board.yml rename boards/{arm => madmachine}/mm_feather/doc/index.rst (100%) rename boards/{arm => madmachine}/mm_feather/doc/mm_feather.jpg (100%) create mode 100644 boards/madmachine/mm_feather/flexspi_nor_config.c rename boards/{arm => madmachine}/mm_feather/mm_feather-pinctrl.dtsi (100%) rename boards/{arm => madmachine}/mm_feather/mm_feather.dts (100%) rename boards/{arm => madmachine}/mm_feather/mm_feather.yaml (100%) rename boards/{arm => madmachine}/mm_feather/mm_feather_defconfig (83%) rename boards/{arm => madmachine}/mm_feather/mmfeather_sdram_ini_dcd.c (100%) create mode 100644 boards/madmachine/mm_swiftio/CMakeLists.txt create mode 100644 boards/madmachine/mm_swiftio/Kconfig.defconfig create mode 100644 boards/madmachine/mm_swiftio/Kconfig.mm_swiftio rename boards/{arm => madmachine}/mm_swiftio/board.cmake (100%) create mode 100644 boards/madmachine/mm_swiftio/board.yml rename boards/{arm => madmachine}/mm_swiftio/doc/index.rst (100%) rename boards/{arm => madmachine}/mm_swiftio/doc/mm_swiftio.jpg (100%) create mode 100644 boards/madmachine/mm_swiftio/flexspi_nor_config.c rename boards/{arm => madmachine}/mm_swiftio/mm_swiftio-pinctrl.dtsi (100%) rename boards/{arm => madmachine}/mm_swiftio/mm_swiftio.dts (100%) rename boards/{arm => madmachine}/mm_swiftio/mm_swiftio.yaml (100%) rename boards/{arm => madmachine}/mm_swiftio/mm_swiftio_defconfig (83%) rename boards/{arm => madmachine}/mm_swiftio/mmswiftio_sdram_ini_dcd.c (100%) create mode 100644 boards/maker_diary/index.rst rename boards/{arm => maker_diary}/nrf52832_mdk/Kconfig (100%) create mode 100644 boards/maker_diary/nrf52832_mdk/Kconfig.defconfig create mode 100644 boards/maker_diary/nrf52832_mdk/Kconfig.nrf52832_mdk rename boards/{arm => maker_diary}/nrf52832_mdk/board.cmake (100%) create mode 100644 boards/maker_diary/nrf52832_mdk/board.yml rename boards/{arm => maker_diary}/nrf52832_mdk/doc/index.rst (100%) rename boards/{arm => maker_diary}/nrf52832_mdk/nrf52832_mdk-pinctrl.dtsi (100%) rename boards/{arm => maker_diary}/nrf52832_mdk/nrf52832_mdk.dts (100%) rename boards/{arm => maker_diary}/nrf52832_mdk/nrf52832_mdk.yaml (100%) create mode 100644 boards/maker_diary/nrf52832_mdk/nrf52832_mdk_defconfig rename boards/{arm/nrf52833dk_nrf52833 => maker_diary/nrf52832_mdk}/pre_dt_board.cmake (100%) rename boards/{arm => maker_diary}/nrf52840_mdk/Kconfig (100%) create mode 100644 boards/maker_diary/nrf52840_mdk/Kconfig.defconfig create mode 100644 boards/maker_diary/nrf52840_mdk/Kconfig.nrf52840_mdk rename boards/{arm => maker_diary}/nrf52840_mdk/board.cmake (100%) create mode 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boards/nordic/nrf51dongle/Kconfig.defconfig create mode 100644 boards/nordic/nrf51dongle/Kconfig.nrf51dongle rename boards/{arm/nrf51dongle_nrf51422 => nordic/nrf51dongle}/board.cmake (100%) create mode 100644 boards/nordic/nrf51dongle/board.yml rename boards/{arm/nrf51dongle_nrf51422/doc/img/nrf51dongle_nrf51422.jpg => nordic/nrf51dongle/doc/img/nrf51dongle_nrf51822.jpg} (100%) create mode 100644 boards/nordic/nrf51dongle/doc/index.rst rename boards/{arm/nrf51_blenano/nrf51_blenano-pinctrl.dtsi => nordic/nrf51dongle/nrf51dongle_nrf51822-pinctrl.dtsi} (100%) create mode 100644 boards/nordic/nrf51dongle/nrf51dongle_nrf51822.dts create mode 100644 boards/nordic/nrf51dongle/nrf51dongle_nrf51822.yaml create mode 100644 boards/nordic/nrf51dongle/nrf51dongle_nrf51822_defconfig rename boards/{arm/nrf51_blenano => nordic/nrf51dongle}/pre_dt_board.cmake (100%) create mode 100644 boards/nordic/nrf52833dk/CMakeLists.txt create mode 100644 boards/nordic/nrf52833dk/Kconfig create mode 100644 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nordic/nrf54h20pdk}/nrf54h20pdk_nrf54h20_cpurad.yaml (84%) create mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad_defconfig rename boards/{riscv/nrf54h20pdk_nrf54h20 => nordic/nrf54h20pdk}/pre_dt_board.cmake (100%) create mode 100644 boards/nordic/nrf54l15pdk/Kconfig.defconfig create mode 100644 boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk rename boards/{arm/nrf54l15pdk_nrf54l15 => nordic/nrf54l15pdk}/board.cmake (100%) create mode 100644 boards/nordic/nrf54l15pdk/board.yml rename boards/{arm/nrf54l15pdk_nrf54l15 => nordic/nrf54l15pdk}/doc/img/nrf54l15pdk_nrf54l15.webp (100%) create mode 100644 boards/nordic/nrf54l15pdk/doc/index.rst rename boards/{arm/nrf54l15pdk_nrf54l15 => nordic/nrf54l15pdk}/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi (100%) rename boards/{arm/nrf54l15pdk_nrf54l15 => nordic/nrf54l15pdk}/nrf54l15pdk_nrf54l15_cpuapp.dts (100%) rename boards/{arm/nrf54l15pdk_nrf54l15 => nordic/nrf54l15pdk}/nrf54l15pdk_nrf54l15_cpuapp.yaml (87%) rename boards/{arm/nrf54l15pdk_nrf54l15 => nordic/nrf54l15pdk}/nrf54l15pdk_nrf54l15_cpuapp_defconfig (85%) rename boards/{arm/hexiwear_kw40z/CMakeLists.txt => nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_defconfig} (100%) rename boards/{arm/nrf54l15pdk_nrf54l15 => nordic/nrf54l15pdk}/revision.cmake (100%) create mode 100644 boards/nordic/nrf9131ek/Kconfig.defconfig create mode 100644 boards/nordic/nrf9131ek/Kconfig.nrf9131ek rename boards/{arm/nrf9131ek_nrf9131 => nordic/nrf9131ek}/board.cmake (100%) create mode 100644 boards/nordic/nrf9131ek/board.yml rename boards/{arm/nrf9131ek_nrf9131 => nordic/nrf9131ek}/doc/img/nrf9131ek_nrf9131.webp (100%) create mode 100644 boards/nordic/nrf9131ek/doc/index.rst rename boards/{arm/nrf9131ek_nrf9131 => nordic/nrf9131ek}/nrf9131ek_nrf9131.dts (100%) rename boards/{arm/nrf9131ek_nrf9131 => nordic/nrf9131ek}/nrf9131ek_nrf9131.yaml (85%) rename boards/{arm/nrf9131ek_nrf9131 => nordic/nrf9131ek}/nrf9131ek_nrf9131_common-pinctrl.dtsi (100%) rename boards/{arm/nrf9131ek_nrf9131 => nordic/nrf9131ek}/nrf9131ek_nrf9131_common.dtsi (100%) create mode 100644 boards/nordic/nrf9131ek/nrf9131ek_nrf9131_defconfig rename boards/{arm/nrf9131ek_nrf9131 => nordic/nrf9131ek}/nrf9131ek_nrf9131_ns.dts (100%) rename boards/{arm/nrf9131ek_nrf9131 => nordic/nrf9131ek}/nrf9131ek_nrf9131_ns.yaml (84%) create mode 100644 boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns_defconfig rename boards/{arm/nrf9131ek_nrf9131 => nordic/nrf9131ek}/nrf9131ek_nrf9131_partition_conf.dtsi (100%) rename boards/{arm/nrf9160_innblue21 => nordic/nrf9131ek}/pre_dt_board.cmake (100%) create mode 100644 boards/nordic/nrf9151dk/Kconfig.defconfig create mode 100644 boards/nordic/nrf9151dk/Kconfig.nrf9151dk rename boards/{arm/nrf9151dk_nrf9151 => nordic/nrf9151dk}/board.cmake (100%) create mode 100644 boards/nordic/nrf9151dk/board.yml create mode 100644 boards/nordic/nrf9151dk/doc/index.rst rename boards/{arm/nrf9151dk_nrf9151 => nordic/nrf9151dk}/dts/bindings/nordic,nrf9151dk-nrf5340-reset.yaml (100%) rename boards/{arm/nrf9151dk_nrf9151 => nordic/nrf9151dk}/dts/nrf9151dk_buttons_on_io_expander.dtsi (100%) rename boards/{arm/nrf9151dk_nrf9151 => nordic/nrf9151dk}/dts/nrf9151dk_leds_on_io_expander.dtsi (100%) rename boards/{arm/nrf9151dk_nrf9151 => nordic/nrf9151dk}/nrf9151dk_nrf9151.dts (100%) rename boards/{arm/nrf9151dk_nrf9151 => nordic/nrf9151dk}/nrf9151dk_nrf9151.yaml (89%) rename boards/{arm/nrf9151dk_nrf9151 => nordic/nrf9151dk}/nrf9151dk_nrf9151_common-pinctrl.dtsi (100%) rename boards/{arm/nrf9151dk_nrf9151 => nordic/nrf9151dk}/nrf9151dk_nrf9151_common.dtsi (100%) create mode 100644 boards/nordic/nrf9151dk/nrf9151dk_nrf9151_defconfig rename boards/{arm/nrf9151dk_nrf9151 => nordic/nrf9151dk}/nrf9151dk_nrf9151_ns.dts (100%) rename boards/{arm/nrf9151dk_nrf9151 => nordic/nrf9151dk}/nrf9151dk_nrf9151_ns.yaml (88%) create mode 100644 boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns_defconfig rename boards/{arm/nrf9151dk_nrf9151 => nordic/nrf9151dk}/nrf9151dk_nrf9151_partition_conf.dtsi (100%) rename boards/{arm/nrf9160_innblue22 => nordic/nrf9151dk}/pre_dt_board.cmake (100%) create mode 100644 boards/nordic/nrf9160dk/CMakeLists.txt create mode 100644 boards/nordic/nrf9160dk/Kconfig create mode 100644 boards/nordic/nrf9160dk/Kconfig.defconfig create mode 100644 boards/nordic/nrf9160dk/Kconfig.nrf9160dk rename boards/{arm/nrf9160dk_nrf52840 => nordic/nrf9160dk}/board.c (100%) create mode 100644 boards/nordic/nrf9160dk/board.cmake create mode 100644 boards/nordic/nrf9160dk/board.yml rename boards/{arm/nrf9160dk_nrf9160 => nordic/nrf9160dk}/doc/img/nrf9160dk_nrf9160.jpg (100%) create mode 100644 boards/nordic/nrf9160dk/doc/index.rst rename boards/{arm/nrf9160dk_nrf52840 => nordic/nrf9160dk}/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml (100%) rename boards/{arm/nrf9160dk_nrf52840 => nordic/nrf9160dk}/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml (100%) rename boards/{arm/nrf9160dk_nrf52840 => nordic/nrf9160dk}/dts/bindings/nordic,nrf9160dk-optional-routing.yaml (100%) rename boards/{arm/nrf9160dk_nrf52840/dts => nordic/nrf9160dk/dts/nrf52840}/nrf9160dk_buttons_on_io_expander.dtsi (100%) rename boards/{arm/nrf9160dk_nrf52840/dts => nordic/nrf9160dk/dts/nrf52840}/nrf9160dk_leds_on_io_expander.dtsi (100%) rename boards/{arm/nrf9160dk_nrf52840/dts => nordic/nrf9160dk/dts/nrf52840}/nrf9160dk_nrf52840_reset_on_if5.dtsi (100%) rename boards/{arm/nrf9160dk_nrf52840/dts => nordic/nrf9160dk/dts/nrf52840}/nrf9160dk_nrf52840_reset_on_if9.dtsi (100%) rename boards/{arm/nrf9160dk_nrf52840/dts => nordic/nrf9160dk/dts/nrf52840}/nrf9160dk_uart1_on_if0_3.dtsi (100%) rename boards/{arm/nrf9160dk_nrf9160/dts => nordic/nrf9160dk/dts/nrf9160}/nrf9160dk_buttons_on_io_expander.dtsi (100%) rename boards/{arm/nrf9160dk_nrf9160/dts => nordic/nrf9160dk/dts/nrf9160}/nrf9160dk_leds_on_io_expander.dtsi (100%) rename boards/{arm/nrf9160dk_nrf9160/dts => nordic/nrf9160dk/dts/nrf9160}/nrf9160dk_nrf52840_reset_on_if5.dtsi (100%) rename boards/{arm/nrf9160dk_nrf9160/dts => nordic/nrf9160dk/dts/nrf9160}/nrf9160dk_nrf52840_reset_on_if9.dtsi (100%) rename boards/{arm/nrf9160dk_nrf9160/dts => nordic/nrf9160dk/dts/nrf9160}/nrf9160dk_uart1_on_if0_3.dtsi (100%) rename boards/{arm/nrf9160dk_nrf9160 => nordic/nrf9160dk}/nrf52840_reset.c (100%) rename boards/{arm/nrf9160dk_nrf52840 => nordic/nrf9160dk}/nrf9160dk_nrf52840-pinctrl.dtsi (100%) rename boards/{arm/nrf9160dk_nrf52840 => nordic/nrf9160dk}/nrf9160dk_nrf52840.dts (100%) rename boards/{arm/nrf9160dk_nrf52840 => nordic/nrf9160dk}/nrf9160dk_nrf52840_0_14_0.overlay (100%) create mode 100644 boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_14_0.yaml create mode 100644 boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_7_0.yaml create mode 100644 boards/nordic/nrf9160dk/nrf9160dk_nrf52840_defconfig rename boards/{arm/nrf9160dk_nrf9160 => nordic/nrf9160dk}/nrf9160dk_nrf9160.dts (100%) rename boards/{arm/nrf9160dk_nrf9160 => nordic/nrf9160dk}/nrf9160dk_nrf9160_0_14_0.overlay (100%) create mode 100644 boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.yaml create mode 100644 boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_7_0.yaml rename boards/{arm/nrf9160dk_nrf9160 => nordic/nrf9160dk}/nrf9160dk_nrf9160_common-pinctrl.dtsi (100%) rename boards/{arm/nrf9160dk_nrf9160 => nordic/nrf9160dk}/nrf9160dk_nrf9160_common.dtsi (100%) rename boards/{arm/nrf9160dk_nrf9160 => nordic/nrf9160dk}/nrf9160dk_nrf9160_common_0_14_0.dtsi (100%) create mode 100644 boards/nordic/nrf9160dk/nrf9160dk_nrf9160_defconfig rename boards/{arm/nrf9160dk_nrf9160 => nordic/nrf9160dk}/nrf9160dk_nrf9160_ns.dts (100%) rename boards/{arm/nrf9160dk_nrf9160 => nordic/nrf9160dk}/nrf9160dk_nrf9160_ns_0_14_0.overlay (100%) create mode 100644 boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.yaml create mode 100644 boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_7_0.yaml create mode 100644 boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_defconfig rename boards/{arm/nrf9160dk_nrf9160 => nordic/nrf9160dk}/nrf9160dk_nrf9160_partition_conf.dtsi (100%) rename boards/{arm/nrf52_blenano2 => nordic/nrf9160dk}/pre_dt_board.cmake (100%) create mode 100644 boards/nordic/nrf9161dk/Kconfig.defconfig create mode 100644 boards/nordic/nrf9161dk/Kconfig.nrf9161dk rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/board.cmake (100%) create mode 100644 boards/nordic/nrf9161dk/board.yml create mode 100644 boards/nordic/nrf9161dk/doc/index.rst rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/dts/bindings/nordic,nrf9161dk-nrf5340-reset.yaml (100%) rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/dts/nrf9161dk_buttons_on_io_expander.dtsi (100%) rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/dts/nrf9161dk_leds_on_io_expander.dtsi (100%) rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/nrf9161dk_nrf9161.dts (100%) rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/nrf9161dk_nrf9161_0_7_0.overlay (100%) create mode 100644 boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.yaml create mode 100644 boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_9_0.yaml rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/nrf9161dk_nrf9161_common-pinctrl.dtsi (100%) rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/nrf9161dk_nrf9161_common.dtsi (100%) rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/nrf9161dk_nrf9161_common_0_7_0.dtsi (100%) create mode 100644 boards/nordic/nrf9161dk/nrf9161dk_nrf9161_defconfig rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/nrf9161dk_nrf9161_ns.dts (100%) rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/nrf9161dk_nrf9161_ns_0_7_0.overlay (100%) create mode 100644 boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.yaml create mode 100644 boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_9_0.yaml create mode 100644 boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_defconfig rename boards/{arm/nrf9161dk_nrf9161 => nordic/nrf9161dk}/nrf9161dk_nrf9161_partition_conf.dtsi (100%) rename boards/{arm/nrf9160dk_nrf9160 => nordic/nrf9161dk}/pre_dt_board.cmake (100%) create mode 100644 boards/nordic/thingy52/CMakeLists.txt create mode 100644 boards/nordic/thingy52/Kconfig create mode 100644 boards/nordic/thingy52/Kconfig.defconfig create mode 100644 boards/nordic/thingy52/Kconfig.thingy52 rename boards/{arm/thingy52_nrf52832 => nordic/thingy52}/board.c (100%) rename boards/{arm/thingy52_nrf52832 => nordic/thingy52}/board.cmake (100%) create mode 100644 boards/nordic/thingy52/board.yml rename boards/{arm/thingy52_nrf52832 => nordic/thingy52}/doc/img/thingy52_nrf52832.jpg (100%) create mode 100644 boards/nordic/thingy52/doc/index.rst rename boards/{arm/nrf52_sparkfun => nordic/thingy52}/pre_dt_board.cmake (100%) rename boards/{arm/thingy52_nrf52832 => nordic/thingy52}/thingy52_nrf52832-pinctrl.dtsi (100%) rename boards/{arm/thingy52_nrf52832 => nordic/thingy52}/thingy52_nrf52832.dts (100%) rename boards/{arm/thingy52_nrf52832 => nordic/thingy52}/thingy52_nrf52832.yaml (84%) create mode 100644 boards/nordic/thingy52/thingy52_nrf52832_defconfig create mode 100644 boards/nordic/thingy53/CMakeLists.txt create mode 100644 boards/nordic/thingy53/Kconfig create mode 100644 boards/nordic/thingy53/Kconfig.defconfig create mode 100644 boards/nordic/thingy53/Kconfig.thingy53 rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/board.c (100%) create mode 100644 boards/nordic/thingy53/board.cmake create mode 100644 boards/nordic/thingy53/board.yml create mode 100644 boards/nordic/thingy53/doc/index.rst rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => nordic/thingy53}/pre_dt_board.cmake (100%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_common-pinctrl.dtsi (100%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_common.dtsi (100%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_cpuapp.dts (100%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_cpuapp.yaml (86%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_cpuapp_defconfig (82%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_cpuapp_ns.dts (100%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_cpuapp_ns.yaml (86%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_cpuapp_ns_defconfig (84%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_cpunet-pinctrl.dtsi (100%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_cpunet.dts (100%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_cpunet.yaml (82%) create mode 100644 boards/nordic/thingy53/thingy53_nrf5340_cpunet_defconfig rename boards/{arm/rddrone_fmuk66/CMakeLists.txt => nordic/thingy53/thingy53_nrf5340_defconfig} (100%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_partition_conf.dtsi (100%) rename boards/{arm/thingy53_nrf5340 => nordic/thingy53}/thingy53_nrf5340_shared_sram_planning_conf.dtsi (100%) create mode 100644 boards/nuvoton/index.rst create mode 100644 boards/nuvoton/npcx4m8f_evb/Kconfig.defconfig create mode 100644 boards/nuvoton/npcx4m8f_evb/Kconfig.npcx4m8f_evb rename boards/{arm => nuvoton}/npcx4m8f_evb/board.cmake (100%) create mode 100644 boards/nuvoton/npcx4m8f_evb/board.yml create mode 100644 boards/nuvoton/npcx4m8f_evb/doc/index.rst rename boards/{arm => nuvoton}/npcx4m8f_evb/doc/npcx4m8f_evb.jpg (100%) rename boards/{arm => nuvoton}/npcx4m8f_evb/npcx4m8f_evb-pinctrl.dtsi (100%) rename boards/{arm => nuvoton}/npcx4m8f_evb/npcx4m8f_evb.dts (100%) rename boards/{arm => nuvoton}/npcx4m8f_evb/npcx4m8f_evb.yaml (100%) rename boards/{arm => nuvoton}/npcx4m8f_evb/npcx4m8f_evb_defconfig (88%) rename boards/{arm => nuvoton}/npcx4m8f_evb/support/openocd.cfg (100%) create mode 100644 boards/nuvoton/npcx7m6fb_evb/Kconfig.defconfig create mode 100644 boards/nuvoton/npcx7m6fb_evb/Kconfig.npcx7m6fb_evb rename boards/{arm => nuvoton}/npcx7m6fb_evb/board.cmake (100%) create mode 100644 boards/nuvoton/npcx7m6fb_evb/board.yml create mode 100644 boards/nuvoton/npcx7m6fb_evb/doc/index.rst rename boards/{arm => nuvoton}/npcx7m6fb_evb/doc/npcx7m6fb_evb.jpg (100%) rename boards/{arm => nuvoton}/npcx7m6fb_evb/npcx7m6fb_evb-pinctrl.dtsi (100%) rename boards/{arm => nuvoton}/npcx7m6fb_evb/npcx7m6fb_evb.dts (100%) rename boards/{arm => nuvoton}/npcx7m6fb_evb/npcx7m6fb_evb.yaml (100%) rename boards/{arm => nuvoton}/npcx7m6fb_evb/npcx7m6fb_evb_defconfig (88%) rename boards/{arm => nuvoton}/npcx7m6fb_evb/support/openocd.cfg (100%) create mode 100644 boards/nuvoton/npcx9m6f_evb/Kconfig.defconfig create mode 100644 boards/nuvoton/npcx9m6f_evb/Kconfig.npcx9m6f_evb rename boards/{arm => nuvoton}/npcx9m6f_evb/board.cmake (100%) create mode 100644 boards/nuvoton/npcx9m6f_evb/board.yml create mode 100644 boards/nuvoton/npcx9m6f_evb/doc/index.rst rename boards/{arm => nuvoton}/npcx9m6f_evb/doc/npcx9m6f_evb.jpg (100%) rename boards/{arm => nuvoton}/npcx9m6f_evb/npcx9m6f_evb-pinctrl.dtsi (100%) rename boards/{arm => nuvoton}/npcx9m6f_evb/npcx9m6f_evb.dts (100%) rename boards/{arm => nuvoton}/npcx9m6f_evb/npcx9m6f_evb.yaml (100%) rename boards/{arm => nuvoton}/npcx9m6f_evb/npcx9m6f_evb_defconfig (88%) rename boards/{arm => nuvoton}/npcx9m6f_evb/support/openocd.cfg (100%) create mode 100644 boards/nuvoton/numaker_pfm_m467/Kconfig create mode 100644 boards/nuvoton/numaker_pfm_m467/Kconfig.defconfig create mode 100644 boards/nuvoton/numaker_pfm_m467/Kconfig.numaker_pfm_m467 create mode 100644 boards/nuvoton/numaker_pfm_m467/board.cmake create mode 100644 boards/nuvoton/numaker_pfm_m467/board.yml rename boards/{arm => nuvoton}/numaker_pfm_m467/doc/index.rst (100%) rename boards/{arm => nuvoton}/numaker_pfm_m467/doc/pfm_m467.jpeg (100%) rename boards/{arm => nuvoton}/numaker_pfm_m467/numaker_pfm_m467-pinctrl.dtsi (100%) rename boards/{arm => nuvoton}/numaker_pfm_m467/numaker_pfm_m467.dts (100%) rename boards/{arm => nuvoton}/numaker_pfm_m467/numaker_pfm_m467.yaml (100%) rename boards/{arm => nuvoton}/numaker_pfm_m467/numaker_pfm_m467_defconfig (78%) rename boards/{arm => nuvoton}/numaker_pfm_m467/support/openocd.cfg (100%) create mode 100644 boards/nuvoton/numaker_pfm_m487/Kconfig.numaker_pfm_m487 rename boards/{arm/nuvoton_pfm_m487 => nuvoton/numaker_pfm_m487}/board.cmake (100%) create mode 100644 boards/nuvoton/numaker_pfm_m487/board.yml create mode 100644 boards/nuvoton/numaker_pfm_m487/doc/index.rst rename boards/{arm/nuvoton_pfm_m487 => nuvoton/numaker_pfm_m487}/doc/pfm_m487.jpg (100%) rename boards/{arm/nuvoton_pfm_m487/nuvoton_pfm_m487-pinctrl.dtsi => nuvoton/numaker_pfm_m487/numaker_pfm_m487-pinctrl.dtsi} (100%) create mode 100644 boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.dts create mode 100644 boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.yaml create mode 100644 boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487_defconfig rename boards/{arm/nuvoton_pfm_m487 => nuvoton/numaker_pfm_m487}/support/openocd.cfg (100%) rename boards/{arm => nxp}/frdm_k22f/CMakeLists.txt (100%) create mode 100644 boards/nxp/frdm_k22f/Kconfig.defconfig create mode 100644 boards/nxp/frdm_k22f/Kconfig.frdm_k22f rename boards/{arm => nxp}/frdm_k22f/board.cmake (100%) create mode 100644 boards/nxp/frdm_k22f/board.yml rename boards/{arm => nxp}/frdm_k22f/doc/frdm_k22f.jpg (100%) create mode 100644 boards/nxp/frdm_k22f/doc/index.rst rename boards/{arm => nxp}/frdm_k22f/frdm_k22f-pinctrl.dtsi (100%) rename boards/{arm => nxp}/frdm_k22f/frdm_k22f.dts (100%) rename boards/{arm => nxp}/frdm_k22f/frdm_k22f.yaml (100%) rename boards/{arm => nxp}/frdm_k22f/frdm_k22f_defconfig (84%) rename boards/{arm => nxp}/frdm_k22f/support/openocd.cfg (100%) rename boards/{arm/segger_trb_stm32f407 => nxp/frdm_k64f}/CMakeLists.txt (100%) create mode 100644 boards/nxp/frdm_k64f/Kconfig.defconfig create mode 100644 boards/nxp/frdm_k64f/Kconfig.frdm_k64f rename boards/{arm => nxp}/frdm_k64f/board.cmake (100%) create mode 100644 boards/nxp/frdm_k64f/board.yml rename boards/{arm => nxp}/frdm_k64f/doc/frdm_k64f.jpg (100%) create mode 100644 boards/nxp/frdm_k64f/doc/index.rst rename boards/{arm => nxp}/frdm_k64f/dts/nxp,enet-experimental.overlay (100%) rename boards/{arm => nxp}/frdm_k64f/frdm_k64f-pinctrl.dtsi (100%) rename boards/{arm => nxp}/frdm_k64f/frdm_k64f.dts (100%) rename boards/{arm => nxp}/frdm_k64f/frdm_k64f.yaml (100%) rename boards/{arm => nxp}/frdm_k64f/frdm_k64f_defconfig (82%) rename boards/{arm => nxp}/frdm_k64f/support/openocd.cfg (100%) rename boards/{arm/twr_kv58f220m => nxp/frdm_k82f}/CMakeLists.txt (100%) create mode 100644 boards/nxp/frdm_k82f/Kconfig.defconfig create mode 100644 boards/nxp/frdm_k82f/Kconfig.frdm_k82f rename boards/{arm => nxp}/frdm_k82f/board.cmake (100%) create mode 100644 boards/nxp/frdm_k82f/board.yml rename boards/{arm => nxp}/frdm_k82f/doc/frdm_k82f.jpg (100%) create mode 100644 boards/nxp/frdm_k82f/doc/index.rst rename boards/{arm => nxp}/frdm_k82f/frdm_k82f-pinctrl.dtsi (100%) rename boards/{arm => nxp}/frdm_k82f/frdm_k82f.dts (100%) rename boards/{arm => nxp}/frdm_k82f/frdm_k82f.yaml (100%) rename boards/{arm => nxp}/frdm_k82f/frdm_k82f_defconfig (83%) rename boards/{arm/usb_kw24d512 => nxp/frdm_kl25z}/CMakeLists.txt (100%) create mode 100644 boards/nxp/frdm_kl25z/Kconfig.defconfig create mode 100644 boards/nxp/frdm_kl25z/Kconfig.frdm_kl25z rename boards/{arm => nxp}/frdm_kl25z/board.cmake (100%) create mode 100644 boards/nxp/frdm_kl25z/board.yml rename boards/{arm => nxp}/frdm_kl25z/doc/frdm_kl25z.jpg (100%) create mode 100644 boards/nxp/frdm_kl25z/doc/index.rst rename boards/{arm => nxp}/frdm_kl25z/frdm_kl25z-pinctrl.dtsi (100%) rename boards/{arm => nxp}/frdm_kl25z/frdm_kl25z.dts (100%) rename boards/{arm => nxp}/frdm_kl25z/frdm_kl25z.yaml (100%) rename boards/{arm => nxp}/frdm_kl25z/frdm_kl25z_defconfig (85%) rename boards/{arm64/bcm958402m2_a72 => nxp/frdm_kw41z}/CMakeLists.txt (100%) create mode 100644 boards/nxp/frdm_kw41z/Kconfig.defconfig create mode 100644 boards/nxp/frdm_kw41z/Kconfig.frdm_kw41z rename boards/{arm => nxp}/frdm_kw41z/board.cmake (100%) create mode 100644 boards/nxp/frdm_kw41z/board.yml rename boards/{arm => nxp}/frdm_kw41z/doc/frdm_kw41z.jpg (100%) create mode 100644 boards/nxp/frdm_kw41z/doc/index.rst rename boards/{arm => nxp}/frdm_kw41z/frdm_kw41z-pinctrl.dtsi (100%) rename boards/{arm => nxp}/frdm_kw41z/frdm_kw41z.dts (100%) rename boards/{arm => nxp}/frdm_kw41z/frdm_kw41z.yaml (100%) rename boards/{arm => nxp}/frdm_kw41z/frdm_kw41z_defconfig (78%) create mode 100644 boards/nxp/hexiwear/Kconfig.defconfig create mode 100644 boards/nxp/hexiwear/Kconfig.hexiwear create mode 100644 boards/nxp/hexiwear/board.cmake create mode 100644 boards/nxp/hexiwear/board.yml rename boards/{arm/hexiwear_k64 => nxp/hexiwear}/doc/hexiwear_k64.jpg (100%) create mode 100644 boards/nxp/hexiwear/doc/index.rst rename boards/{arm/hexiwear_k64/hexiwear_k64-pinctrl.dtsi => nxp/hexiwear/hexiwear_mk64f12-pinctrl.dtsi} (100%) create mode 100644 boards/nxp/hexiwear/hexiwear_mk64f12.dts create mode 100644 boards/nxp/hexiwear/hexiwear_mk64f12.yaml create mode 100644 boards/nxp/hexiwear/hexiwear_mk64f12_defconfig rename boards/{arm/hexiwear_kw40z/hexiwear_kw40z-pinctrl.dtsi => nxp/hexiwear/hexiwear_mkw40z4-pinctrl.dtsi} (100%) create mode 100644 boards/nxp/hexiwear/hexiwear_mkw40z4.dts create mode 100644 boards/nxp/hexiwear/hexiwear_mkw40z4.yaml create mode 100644 boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig create mode 100644 boards/nxp/imx8mm_evk/Kconfig.defconfig create mode 100644 boards/nxp/imx8mm_evk/Kconfig.imx8mm_evk create mode 100644 boards/nxp/imx8mm_evk/board.cmake create mode 100644 boards/nxp/imx8mm_evk/board.yml create mode 100644 boards/nxp/imx8mm_evk/doc/index.rst rename boards/{arm64/mimx8mm_evk/mimx8mm_evk-pinctrl.dtsi => nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi} (100%) create mode 100644 boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts create mode 100644 boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml create mode 100644 boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig create mode 100644 boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts create mode 100644 boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml create mode 100644 boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig create mode 100644 boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts create mode 100644 boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml create mode 100644 boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig create mode 100644 boards/nxp/imx8mn_evk/Kconfig.imx8mn_evk rename boards/{arm64/mimx8mm_evk => nxp/imx8mn_evk}/board.cmake (100%) create mode 100644 boards/nxp/imx8mn_evk/board.yml create mode 100644 boards/nxp/imx8mn_evk/doc/index.rst rename boards/{arm64/mimx8mn_evk/mimx8mn_evk-pinctrl.dtsi => nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi} (100%) create mode 100644 boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts create mode 100644 boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml create mode 100644 boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig create mode 100644 boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts create mode 100644 boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml create mode 100644 boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig rename boards/{arm64/khadas_edgev => nxp/imx8mp_evk}/CMakeLists.txt (100%) create mode 100644 boards/nxp/imx8mp_evk/Kconfig.defconfig create mode 100644 boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk create mode 100644 boards/nxp/imx8mp_evk/board.cmake create mode 100644 boards/nxp/imx8mp_evk/board.yml create mode 100644 boards/nxp/imx8mp_evk/doc/index.rst rename boards/{arm64/mimx8mp_evk/mimx8mp_evk-pinctrl.dtsi => nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi} (100%) create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.yaml create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.dts create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.yaml create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp_defconfig create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig create mode 100644 boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig create mode 100644 boards/nxp/imx8mq_evk/Kconfig.defconfig create mode 100644 boards/nxp/imx8mq_evk/Kconfig.imx8mq_evk rename boards/{arm/mimx8mq_evk => nxp/imx8mq_evk}/board.cmake (100%) create mode 100644 boards/nxp/imx8mq_evk/board.yml rename boards/{arm/mimx8mq_evk => nxp/imx8mq_evk}/doc/img/mimx8mq_evk.jpg (100%) create mode 100644 boards/nxp/imx8mq_evk/doc/index.rst rename boards/{arm/mimx8mq_evk/mimx8mq_evk-pinctrl.dtsi => nxp/imx8mq_evk/imx8mq_evk-pinctrl.dtsi} (100%) create mode 100644 boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts create mode 100644 boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml create mode 100644 boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig create mode 100644 boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek create mode 100644 boards/nxp/imx8qm_mek/board.cmake create mode 100644 boards/nxp/imx8qm_mek/board.yml rename boards/{xtensa/nxp_adsp_imx8/nxp_adsp_imx8-pinctrl.dtsi => nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi} (100%) create mode 100644 boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts create mode 100644 boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.yaml create mode 100644 boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig create mode 100644 boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek create mode 100644 boards/nxp/imx8qxp_mek/board.cmake create mode 100644 boards/nxp/imx8qxp_mek/board.yml rename boards/{xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x-pinctrl.dtsi => nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi} (100%) create mode 100644 boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts create mode 100644 boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.yaml create mode 100644 boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig create mode 100644 boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk create mode 100644 boards/nxp/imx8ulp_evk/board.cmake create mode 100644 boards/nxp/imx8ulp_evk/board.yml create mode 100644 boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.dts create mode 100644 boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.yaml create mode 100644 boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp_defconfig rename boards/{arm64/mimx8mp_evk => nxp/imx93_evk}/CMakeLists.txt (100%) create mode 100644 boards/nxp/imx93_evk/Kconfig.imx93_evk rename boards/{arm64/mimx8mn_evk => nxp/imx93_evk}/board.cmake (100%) create mode 100644 boards/nxp/imx93_evk/board.yml create mode 100644 boards/nxp/imx93_evk/doc/index.rst rename boards/{arm64/mimx93_evk/mimx93_evk-pinctrl.dtsi => nxp/imx93_evk/imx93_evk-pinctrl.dtsi} (100%) create mode 100644 boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts create mode 100644 boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml create mode 100644 boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig create mode 100644 boards/nxp/index.rst rename boards/{arm => nxp}/lpcxpresso11u68/CMakeLists.txt (100%) create mode 100644 boards/nxp/lpcxpresso11u68/Kconfig.lpcxpresso11u68 rename boards/{arm => nxp}/lpcxpresso11u68/board.cmake (100%) create mode 100644 boards/nxp/lpcxpresso11u68/board.yml rename boards/{arm => nxp}/lpcxpresso11u68/doc/index.rst (100%) rename boards/{arm => nxp}/lpcxpresso11u68/doc/lpcxpresso11u68.jpg (100%) rename boards/{arm => nxp}/lpcxpresso11u68/lpcxpresso11u68-pinctrl.dtsi (100%) rename boards/{arm => nxp}/lpcxpresso11u68/lpcxpresso11u68.dts (100%) rename boards/{arm => nxp}/lpcxpresso11u68/lpcxpresso11u68.yaml (100%) rename boards/{arm => nxp}/lpcxpresso11u68/lpcxpresso11u68_defconfig (94%) rename boards/{arm/faze => nxp/lpcxpresso11u68}/pre_dt_board.cmake (100%) rename boards/{arm => nxp}/lpcxpresso11u68/support/openocd.cfg (100%) create mode 100644 boards/nxp/lpcxpresso51u68/Kconfig.lpcxpresso51u68 rename boards/{arm => nxp}/lpcxpresso51u68/board.cmake (100%) create mode 100644 boards/nxp/lpcxpresso51u68/board.yml rename boards/{arm => nxp}/lpcxpresso51u68/doc/index.rst (100%) rename boards/{arm => nxp}/lpcxpresso51u68/doc/lpcxpresso51u68.jpg (100%) rename boards/{arm => nxp}/lpcxpresso51u68/lpcxpresso51u68-pinctrl.dtsi (100%) rename boards/{arm => nxp}/lpcxpresso51u68/lpcxpresso51u68.dts (100%) rename boards/{arm => nxp}/lpcxpresso51u68/lpcxpresso51u68.yaml (100%) create mode 100644 boards/nxp/lpcxpresso51u68/lpcxpresso51u68_defconfig rename boards/{arm => nxp}/lpcxpresso51u68/pre_dt_board.cmake (100%) create mode 100644 boards/nxp/lpcxpresso54114/Kconfig.defconfig create mode 100644 boards/nxp/lpcxpresso54114/Kconfig.lpcxpresso54114 create mode 100644 boards/nxp/lpcxpresso54114/board.cmake create mode 100644 boards/nxp/lpcxpresso54114/board.yml create mode 100644 boards/nxp/lpcxpresso54114/doc/index.rst rename boards/{arm => nxp}/lpcxpresso54114/doc/lpcxpresso54114_m4.jpg (100%) rename boards/{arm => nxp}/lpcxpresso54114/lpcxpresso54114-pinctrl.dtsi (100%) rename boards/{arm => nxp}/lpcxpresso54114/lpcxpresso54114.dtsi (100%) rename boards/{arm/lpcxpresso54114/lpcxpresso54114_m0.dts => nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.dts} (100%) create mode 100644 boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml create mode 100644 boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig rename boards/{arm/lpcxpresso54114/lpcxpresso54114_m4.dts => nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts} (100%) create mode 100644 boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml create mode 100644 boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig rename boards/{arm => nxp}/lpcxpresso54114/pre_dt_board.cmake (100%) create mode 100644 boards/nxp/lpcxpresso55s06/Kconfig.defconfig create mode 100644 boards/nxp/lpcxpresso55s06/Kconfig.lpcxpresso55s06 rename boards/{arm => nxp}/lpcxpresso55s06/board.cmake (100%) create mode 100644 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(100%) rename boards/{arm => nxp}/lpcxpresso55s16/lpcxpresso55s16-pinctrl.dtsi (100%) rename boards/{arm => nxp}/lpcxpresso55s16/lpcxpresso55s16.dts (100%) rename boards/{arm => nxp}/lpcxpresso55s16/lpcxpresso55s16.yaml (100%) rename boards/{arm => nxp}/lpcxpresso55s16/lpcxpresso55s16_common.dtsi (100%) rename boards/{arm => nxp}/lpcxpresso55s16/lpcxpresso55s16_defconfig (76%) rename boards/{arm => nxp}/lpcxpresso55s16/pre_dt_board.cmake (100%) create mode 100644 boards/nxp/lpcxpresso55s28/Kconfig.defconfig create mode 100644 boards/nxp/lpcxpresso55s28/Kconfig.lpcxpresso55s28 rename boards/{arm => nxp}/lpcxpresso55s28/board.cmake (100%) create mode 100644 boards/nxp/lpcxpresso55s28/board.yml rename boards/{arm => nxp}/lpcxpresso55s28/doc/LPC55S28-EVK.jpg (100%) rename boards/{arm => nxp}/lpcxpresso55s28/doc/index.rst (100%) rename boards/{arm => nxp}/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi (100%) rename boards/{arm => nxp}/lpcxpresso55s28/lpcxpresso55s28.dts (100%) rename boards/{arm => nxp}/lpcxpresso55s28/lpcxpresso55s28.yaml (100%) rename boards/{arm => nxp}/lpcxpresso55s28/lpcxpresso55s28_common.dtsi (100%) rename boards/{arm => nxp}/lpcxpresso55s28/lpcxpresso55s28_defconfig (78%) rename boards/{arm => nxp}/lpcxpresso55s28/pre_dt_board.cmake (100%) rename boards/{arm => nxp}/lpcxpresso55s36/Kconfig.defconfig (100%) create mode 100644 boards/nxp/lpcxpresso55s36/Kconfig.lpcxpresso55s36 rename boards/{arm => nxp}/lpcxpresso55s36/board.cmake (100%) create mode 100644 boards/nxp/lpcxpresso55s36/board.yml rename boards/{arm => nxp}/lpcxpresso55s36/doc/index.rst (100%) rename boards/{arm => nxp}/lpcxpresso55s36/doc/lpcxpresso55S36.jpg (100%) rename boards/{arm => nxp}/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi (100%) rename boards/{arm => nxp}/lpcxpresso55s36/lpcxpresso55s36.dts (100%) rename boards/{arm => nxp}/lpcxpresso55s36/lpcxpresso55s36.yaml (100%) create mode 100644 boards/nxp/lpcxpresso55s36/lpcxpresso55s36_defconfig rename boards/{arm => nxp}/lpcxpresso55s36/pre_dt_board.cmake (100%) rename boards/{arm => nxp}/lpcxpresso55s69/CMakeLists.txt (100%) create mode 100644 boards/nxp/lpcxpresso55s69/Kconfig.defconfig create mode 100644 boards/nxp/lpcxpresso55s69/Kconfig.lpcxpresso55s69 create mode 100644 boards/nxp/lpcxpresso55s69/board.cmake create mode 100644 boards/nxp/lpcxpresso55s69/board.yml create mode 100644 boards/nxp/lpcxpresso55s69/doc/index.rst rename boards/{arm => nxp}/lpcxpresso55s69/doc/lpcxpresso55s69.jpg (100%) rename boards/{arm => nxp}/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi (100%) rename boards/{arm => nxp}/lpcxpresso55s69/lpcxpresso55s69.dtsi (100%) create mode 100644 boards/nxp/lpcxpresso55s69/lpcxpresso55s69_defconfig rename boards/{arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts => nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts} (100%) create mode 100644 boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml create mode 100644 boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig rename boards/{arm/lpcxpresso55s69/lpcxpresso55s69_ns.dts => nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts} (100%) create mode 100644 boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml create mode 100644 boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig rename boards/{arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.dts => nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.dts} (100%) create mode 100644 boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml rename boards/{arm => nxp}/lpcxpresso55s69/pinmux.c (100%) rename boards/{arm => nxp}/lpcxpresso55s69/pre_dt_board.cmake (100%) rename boards/{arm64/mimx93_evk => nxp/ls1046ardb}/CMakeLists.txt (100%) create mode 100644 boards/nxp/ls1046ardb/Kconfig.ls1046ardb rename boards/{arm64/mimx8mp_evk => nxp/ls1046ardb}/board.cmake (100%) create mode 100644 boards/nxp/ls1046ardb/board.yml create mode 100644 boards/nxp/ls1046ardb/doc/index.rst rename boards/{arm64/nxp_ls1046ardb/nxp_ls1046ardb.dts => nxp/ls1046ardb/ls1046ardb_ls1046a.dts} (100%) create mode 100644 boards/nxp/ls1046ardb/ls1046ardb_ls1046a.yaml create mode 100644 boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig rename boards/{arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores.dts => nxp/ls1046ardb/ls1046ardb_ls1046a_smp.dts} (100%) create mode 100644 boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.yaml rename boards/{arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores.dts => nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.dts} (100%) create mode 100644 boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.yaml create mode 100644 boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig create mode 100644 boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig create mode 100644 boards/nxp/mimxrt1010_evk/CMakeLists.txt create mode 100644 boards/nxp/mimxrt1010_evk/Kconfig.mimxrt1010_evk rename boards/{arm => nxp}/mimxrt1010_evk/board.cmake (100%) create mode 100644 boards/nxp/mimxrt1010_evk/board.yml rename boards/{arm => nxp}/mimxrt1010_evk/doc/index.rst (100%) rename boards/{arm => nxp}/mimxrt1010_evk/doc/mimxrt1010_evk.jpg (100%) rename boards/{arm => nxp}/mimxrt1010_evk/init.c (88%) rename boards/{arm => nxp}/mimxrt1010_evk/mimxrt1010_evk-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mimxrt1010_evk/mimxrt1010_evk.dts (100%) rename boards/{arm => nxp}/mimxrt1010_evk/mimxrt1010_evk.yaml (100%) rename boards/{arm => nxp}/mimxrt1010_evk/mimxrt1010_evk_defconfig (79%) create mode 100644 boards/nxp/mimxrt1015_evk/CMakeLists.txt create mode 100644 boards/nxp/mimxrt1015_evk/Kconfig.mimxrt1015_evk rename boards/{arm => nxp}/mimxrt1015_evk/board.cmake (100%) create mode 100644 boards/nxp/mimxrt1015_evk/board.yml rename boards/{arm => nxp}/mimxrt1015_evk/doc/index.rst (100%) rename boards/{arm => nxp}/mimxrt1015_evk/doc/mimxrt1015_evk.jpg (100%) rename boards/{arm => nxp}/mimxrt1015_evk/mimxrt1015_evk-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mimxrt1015_evk/mimxrt1015_evk.dts (100%) rename boards/{arm => nxp}/mimxrt1015_evk/mimxrt1015_evk.yaml (100%) rename boards/{arm => nxp}/mimxrt1015_evk/mimxrt1015_evk_defconfig (79%) create mode 100644 boards/nxp/mimxrt1020_evk/CMakeLists.txt create mode 100644 boards/nxp/mimxrt1020_evk/Kconfig.defconfig create mode 100644 boards/nxp/mimxrt1020_evk/Kconfig.mimxrt1020_evk rename boards/{arm => nxp}/mimxrt1020_evk/board.cmake (100%) create mode 100644 boards/nxp/mimxrt1020_evk/board.yml rename boards/{arm => nxp}/mimxrt1020_evk/doc/index.rst (100%) rename boards/{arm => nxp}/mimxrt1020_evk/doc/mimxrt1020_evk.jpg (100%) rename boards/{arm => nxp}/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mimxrt1020_evk/mimxrt1020_evk.dts (100%) rename boards/{arm => nxp}/mimxrt1020_evk/mimxrt1020_evk.yaml (100%) rename boards/{arm => nxp}/mimxrt1020_evk/mimxrt1020_evk_defconfig (79%) create mode 100644 boards/nxp/mimxrt1024_evk/CMakeLists.txt create mode 100644 boards/nxp/mimxrt1024_evk/Kconfig.defconfig create mode 100644 boards/nxp/mimxrt1024_evk/Kconfig.mimxrt1024_evk rename boards/{arm => nxp}/mimxrt1024_evk/board.cmake (100%) create mode 100644 boards/nxp/mimxrt1024_evk/board.yml rename boards/{arm => nxp}/mimxrt1024_evk/doc/index.rst (100%) rename boards/{arm => nxp}/mimxrt1024_evk/doc/mimxrt1024_evk.jpg (100%) rename boards/{arm => nxp}/mimxrt1024_evk/dts/nxp,enet-experimental.overlay (100%) rename boards/{arm => nxp}/mimxrt1024_evk/mimxrt1024_evk-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mimxrt1024_evk/mimxrt1024_evk.dts (100%) rename boards/{arm => nxp}/mimxrt1024_evk/mimxrt1024_evk.yaml (100%) rename boards/{arm => nxp}/mimxrt1024_evk/mimxrt1024_evk_defconfig (79%) create mode 100644 boards/nxp/mimxrt1040_evk/CMakeLists.txt create mode 100644 boards/nxp/mimxrt1040_evk/Kconfig.defconfig create mode 100644 boards/nxp/mimxrt1040_evk/Kconfig.mimxrt1040_evk rename boards/{arm => nxp}/mimxrt1040_evk/board.cmake (100%) create mode 100644 boards/nxp/mimxrt1040_evk/board.yml create mode 100644 boards/nxp/mimxrt1040_evk/doc/index.rst rename boards/{arm => nxp}/mimxrt1040_evk/doc/mimxrt1040_evk.jpg (100%) rename boards/{arm => nxp}/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mimxrt1040_evk/mimxrt1040_evk.dts (100%) rename boards/{arm => nxp}/mimxrt1040_evk/mimxrt1040_evk.yaml (100%) create mode 100644 boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig create mode 100644 boards/nxp/mimxrt1050_evk/CMakeLists.txt create mode 100644 boards/nxp/mimxrt1050_evk/Kconfig.defconfig create mode 100644 boards/nxp/mimxrt1050_evk/Kconfig.mimxrt1050_evk create mode 100644 boards/nxp/mimxrt1050_evk/board.cmake create mode 100644 boards/nxp/mimxrt1050_evk/board.yml create mode 100644 boards/nxp/mimxrt1050_evk/doc/index.rst rename boards/{arm => nxp}/mimxrt1050_evk/doc/mimxrt1050_evk.jpg (100%) rename boards/{arm => nxp}/mimxrt1050_evk/dts/nxp,enet-experimental.overlay (100%) rename boards/{arm => nxp}/mimxrt1050_evk/mimxrt1050_evk-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mimxrt1050_evk/mimxrt1050_evk.dts (77%) create mode 100644 boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig create mode 100644 boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay rename boards/{arm/mimxrt1050_evk/mimxrt1050_evk.yaml => nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml} (100%) create mode 100644 boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay create mode 100644 boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml create mode 100644 boards/nxp/mimxrt1050_evk/revision.cmake create mode 100644 boards/nxp/mimxrt1060_evk/CMakeLists.txt create mode 100644 boards/nxp/mimxrt1060_evk/Kconfig.defconfig create mode 100644 boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evk create mode 100644 boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evkb create mode 100644 boards/nxp/mimxrt1060_evk/board.cmake create mode 100644 boards/nxp/mimxrt1060_evk/board.yml create mode 100644 boards/nxp/mimxrt1060_evk/doc/index.rst rename boards/{arm => nxp}/mimxrt1060_evk/doc/mimxrt1060_evk.jpg (100%) rename boards/{arm => nxp}/mimxrt1060_evk/dts/nxp,enet-experimental.overlay (100%) rename boards/{arm => nxp}/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mimxrt1060_evk/mimxrt1060_evk.dts (82%) create mode 100644 boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig create mode 100644 boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay create mode 100644 boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml create mode 100644 boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay rename boards/{arm/mimxrt1060_evk/mimxrt1060_evk.yaml => nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml} (100%) rename boards/{arm => nxp}/mimxrt1060_evk/mimxrt1060_evkb.dts (84%) rename boards/{arm => nxp}/mimxrt1060_evk/mimxrt1060_evkb.yaml (100%) create mode 100644 boards/nxp/mimxrt1060_evk/mimxrt1060_evkb_defconfig create mode 100644 boards/nxp/mimxrt1060_evk/revision.cmake create mode 100644 boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt create mode 100644 boards/nxp/mimxrt1062_fmurt6/Kconfig.defconfig create mode 100644 boards/nxp/mimxrt1062_fmurt6/Kconfig.mimxrt1062_fmurt6 rename boards/{arm => nxp}/mimxrt1062_fmurt6/board.cmake (100%) create mode 100644 boards/nxp/mimxrt1062_fmurt6/board.yml rename boards/{arm => nxp}/mimxrt1062_fmurt6/doc/index.rst (100%) rename boards/{arm => nxp}/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg (100%) rename boards/{arm => nxp}/mimxrt1062_fmurt6/mimxrt1062_fmurt6-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts (100%) rename boards/{arm => nxp}/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml (100%) rename boards/{arm => nxp}/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig (76%) create mode 100644 boards/nxp/mimxrt1064_evk/CMakeLists.txt create mode 100644 boards/nxp/mimxrt1064_evk/Kconfig.defconfig create mode 100644 boards/nxp/mimxrt1064_evk/Kconfig.mimxrt1064_evk rename boards/{arm => nxp}/mimxrt1064_evk/board.cmake (100%) create mode 100644 boards/nxp/mimxrt1064_evk/board.yml create mode 100644 boards/nxp/mimxrt1064_evk/doc/index.rst rename boards/{arm => nxp}/mimxrt1064_evk/doc/mimxrt1064_evk.jpg (100%) rename boards/{arm => nxp}/mimxrt1064_evk/dts/nxp,enet-experimental.overlay (100%) rename boards/{arm => nxp}/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mimxrt1064_evk/mimxrt1064_evk.dts (100%) rename boards/{arm => nxp}/mimxrt1064_evk/mimxrt1064_evk.yaml (100%) rename boards/{arm => nxp}/mimxrt1064_evk/mimxrt1064_evk_defconfig (79%) create mode 100644 boards/nxp/mimxrt1160_evk/CMakeLists.txt create mode 100644 boards/nxp/mimxrt1160_evk/Kconfig.defconfig create mode 100644 boards/nxp/mimxrt1160_evk/Kconfig.mimxrt1160_evk rename boards/{arm => nxp}/mimxrt1160_evk/board.cmake (100%) create mode 100644 boards/nxp/mimxrt1160_evk/board.yml create mode 100644 boards/nxp/mimxrt1160_evk/doc/index.rst rename boards/{arm => nxp}/mimxrt1160_evk/doc/mimxrt1160_evk.jpg (100%) rename boards/{arm => nxp}/mimxrt1160_evk/dts/nxp,enet-experimental.overlay (100%) rename boards/{arm => nxp}/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mimxrt1160_evk/mimxrt1160_evk.dtsi (100%) rename boards/{arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts => nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts} (100%) create mode 100644 boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml create mode 100644 boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig rename boards/{arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts => nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts} (100%) create mode 100644 boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml create mode 100644 boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig create mode 100644 boards/nxp/mimxrt1170_evk/CMakeLists.txt create mode 100644 boards/nxp/mimxrt1170_evk/Kconfig.defconfig create mode 100644 boards/nxp/mimxrt1170_evk/Kconfig.mimxrt1170_evk create mode 100644 boards/nxp/mimxrt1170_evk/board.cmake create mode 100644 boards/nxp/mimxrt1170_evk/board.yml create mode 100644 boards/nxp/mimxrt1170_evk/doc/index.rst rename boards/{arm => nxp}/mimxrt1170_evk/doc/mimxrt1170_evk.jpg (100%) rename boards/{arm => nxp}/mimxrt1170_evk/dts/nxp,enet-experimental.overlay (100%) rename boards/{arm => nxp}/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mimxrt1170_evk/mimxrt1170_evk.dtsi (100%) rename boards/{arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts => nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts} (100%) create mode 100644 boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml create mode 100644 boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay create mode 100644 boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml create mode 100644 boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig rename boards/{arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts => nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts} (100%) create mode 100644 boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml create mode 100644 boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay create mode 100644 boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml create mode 100644 boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig create mode 100644 boards/nxp/mimxrt595_evk/CMakeLists.txt create mode 100644 boards/nxp/mimxrt595_evk/Kconfig create mode 100644 boards/nxp/mimxrt595_evk/Kconfig.defconfig create mode 100644 boards/nxp/mimxrt595_evk/Kconfig.mimxrt595_evk rename boards/{arm => nxp}/mimxrt595_evk/board.c (100%) rename boards/{arm => nxp}/mimxrt595_evk/board.cmake (100%) rename boards/{arm => nxp}/mimxrt595_evk/board.h (100%) create mode 100644 boards/nxp/mimxrt595_evk/board.yml rename boards/{arm => nxp}/mimxrt595_evk/dc_ram.ld (100%) create mode 100644 boards/nxp/mimxrt595_evk/doc/index.rst rename boards/{arm => nxp}/mimxrt595_evk/doc/mimxrt595_evk.jpg (100%) rename boards/{arm/mimxrt595_evk/mimxrt595_evk_cm33-pinctrl.dtsi => nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi} (100%) create mode 100644 boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts create mode 100644 boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml create mode 100644 boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig rename boards/{xtensa/nxp_adsp_rt595/nxp_adsp_rt595.dts => nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.dts} (100%) create mode 100644 boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml create mode 100644 boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1_defconfig rename boards/{arm => nxp}/mimxrt595_evk/pre_dt_board.cmake (100%) create mode 100644 boards/nxp/mimxrt685_evk/CMakeLists.txt rename boards/{arm => nxp}/mimxrt685_evk/Kconfig (100%) create mode 100644 boards/nxp/mimxrt685_evk/Kconfig.defconfig create mode 100644 boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk rename boards/{arm => nxp}/mimxrt685_evk/board.cmake (100%) create mode 100644 boards/nxp/mimxrt685_evk/board.yml create mode 100644 boards/nxp/mimxrt685_evk/doc/index.rst rename boards/{arm => nxp}/mimxrt685_evk/doc/mimxrt685_evk.jpg (100%) rename boards/{arm => nxp}/mimxrt685_evk/init.c (100%) rename boards/{arm/mimxrt685_evk/mimxrt685_evk_cm33-pinctrl.dtsi => nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi} (100%) create mode 100644 boards/nxp/mimxrt685_evk/mimxrt685_evk.dts create mode 100644 boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml create mode 100644 boards/nxp/mimxrt685_evk/mimxrt685_evk_defconfig rename boards/{arm => nxp}/mimxrt685_evk/pre_dt_board.cmake (100%) create mode 100644 boards/nxp/mr_canhubk3/Kconfig.defconfig create mode 100644 boards/nxp/mr_canhubk3/Kconfig.mr_canhubk3 rename boards/{arm => nxp}/mr_canhubk3/board.cmake (100%) create mode 100644 boards/nxp/mr_canhubk3/board.yml rename boards/{arm => nxp}/mr_canhubk3/doc/img/mr_canhubk3_top.jpg (100%) create mode 100644 boards/nxp/mr_canhubk3/doc/index.rst rename boards/{arm => nxp}/mr_canhubk3/mr_canhubk3-pinctrl.dtsi (100%) rename boards/{arm => nxp}/mr_canhubk3/mr_canhubk3.dts (100%) rename boards/{arm => nxp}/mr_canhubk3/mr_canhubk3.yaml (100%) rename boards/{arm => nxp}/mr_canhubk3/mr_canhubk3_defconfig (79%) rename boards/{arm => nxp}/mr_canhubk3/support/debug.cmm (100%) rename boards/{arm => nxp}/mr_canhubk3/support/flash.cmm (100%) rename boards/{arm => nxp}/mr_canhubk3/support/startup.cmm (100%) rename boards/{arm64/nxp_ls1046ardb => nxp/rddrone_fmuk66}/CMakeLists.txt (100%) create mode 100644 boards/nxp/rddrone_fmuk66/Kconfig.defconfig create mode 100644 boards/nxp/rddrone_fmuk66/Kconfig.rddrone_fmuk66 rename boards/{arm => nxp}/rddrone_fmuk66/board.cmake (100%) create mode 100644 boards/nxp/rddrone_fmuk66/board.yml create mode 100644 boards/nxp/rddrone_fmuk66/doc/index.rst rename boards/{arm => nxp}/rddrone_fmuk66/doc/rddrone_fmuk66.jpg (100%) rename boards/{arm => nxp}/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi (100%) rename boards/{arm => nxp}/rddrone_fmuk66/rddrone_fmuk66.dts (100%) rename boards/{arm => nxp}/rddrone_fmuk66/rddrone_fmuk66.yaml (100%) rename boards/{arm => nxp}/rddrone_fmuk66/rddrone_fmuk66_defconfig (86%) create mode 100644 boards/nxp/s32z2xxdc2/Kconfig.defconfig create mode 100644 boards/nxp/s32z2xxdc2/Kconfig.s32z2xxdc2 rename boards/{arm/s32z270dc2_r52 => nxp/s32z2xxdc2}/board.cmake (100%) create mode 100644 boards/nxp/s32z2xxdc2/board.yml create mode 100644 boards/nxp/s32z2xxdc2/doc/index.rst create mode 100644 boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi rename boards/{arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl-common.dtsi => nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi} (100%) create mode 100644 boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts create mode 100644 boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml rename boards/{arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_B.overlay => nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_B.overlay} (100%) rename boards/{arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.overlay => nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.overlay} (100%) create mode 100644 boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml create mode 100644 boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig create mode 100644 boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts create mode 100644 boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml rename boards/{arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_B.overlay => nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_B.overlay} (100%) rename boards/{arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.overlay => nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.overlay} (100%) create mode 100644 boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml create mode 100644 boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig rename boards/{arm/s32z270dc2_r52 => nxp/s32z2xxdc2}/support/debug.cmm (77%) rename boards/{arm/s32z270dc2_r52 => nxp/s32z2xxdc2}/support/flash.cmm (77%) rename boards/{arm/s32z270dc2_r52 => nxp/s32z2xxdc2}/support/startup.cmm (100%) rename boards/{arm => nxp}/twr_ke18f/CMakeLists.txt (100%) rename boards/{arm => nxp}/twr_ke18f/Kconfig (100%) create mode 100644 boards/nxp/twr_ke18f/Kconfig.defconfig create mode 100644 boards/nxp/twr_ke18f/Kconfig.twr_ke18f rename boards/{arm => nxp}/twr_ke18f/board.cmake (100%) create mode 100644 boards/nxp/twr_ke18f/board.yml rename boards/{arm => nxp}/twr_ke18f/doc/TWR-KE18F-DEVICE.jpg (100%) create mode 100644 boards/nxp/twr_ke18f/doc/index.rst rename boards/{arm => nxp}/twr_ke18f/dts/bindings/nxp,flexio.yaml (100%) rename boards/{arm => nxp}/twr_ke18f/dts/lpspi0_pcs2.overlay (100%) rename boards/{arm => nxp}/twr_ke18f/dts/lpspi1_pcs0.overlay (100%) rename boards/{arm => nxp}/twr_ke18f/dts/lpspi1_pcs0_pcs2.overlay (100%) rename boards/{arm => nxp}/twr_ke18f/dts/lpspi1_pcs2.overlay (100%) rename boards/{arm => nxp}/twr_ke18f/pinmux.c (100%) rename boards/{arm => nxp}/twr_ke18f/twr_ke18f-pinctrl.dtsi (100%) rename boards/{arm => nxp}/twr_ke18f/twr_ke18f.dts (100%) rename boards/{arm => nxp}/twr_ke18f/twr_ke18f.yaml (100%) create mode 100644 boards/nxp/twr_ke18f/twr_ke18f_defconfig rename boards/{arm64/roc_rk3568_pc => nxp/twr_kv58f220m}/CMakeLists.txt (100%) create mode 100644 boards/nxp/twr_kv58f220m/Kconfig.defconfig create mode 100644 boards/nxp/twr_kv58f220m/Kconfig.twr_kv58f220m rename boards/{arm => nxp}/twr_kv58f220m/board.cmake (100%) create mode 100644 boards/nxp/twr_kv58f220m/board.yml create mode 100644 boards/nxp/twr_kv58f220m/doc/index.rst rename boards/{arm => nxp}/twr_kv58f220m/doc/twr_kv58f220m.jpg (100%) rename boards/{arm => nxp}/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi (100%) rename boards/{arm => nxp}/twr_kv58f220m/twr_kv58f220m.dts (100%) rename boards/{arm => nxp}/twr_kv58f220m/twr_kv58f220m.yaml (100%) rename boards/{arm => nxp}/twr_kv58f220m/twr_kv58f220m_defconfig (75%) create mode 100644 boards/nxp/ucans32k1sic/Kconfig.defconfig create mode 100644 boards/nxp/ucans32k1sic/Kconfig.ucans32k1sic rename boards/{arm => nxp}/ucans32k1sic/board.cmake (100%) create mode 100644 boards/nxp/ucans32k1sic/board.yml rename boards/{arm => nxp}/ucans32k1sic/doc/img/ucans32k1sic_top.webp (100%) create mode 100644 boards/nxp/ucans32k1sic/doc/index.rst rename boards/{arm => nxp}/ucans32k1sic/support/debug.cmm (100%) rename boards/{arm => nxp}/ucans32k1sic/support/flash.cmm (100%) rename boards/{arm => nxp}/ucans32k1sic/support/startup.cmm (100%) rename boards/{arm => nxp}/ucans32k1sic/ucans32k1sic-pinctrl.dtsi (100%) rename boards/{arm => nxp}/ucans32k1sic/ucans32k1sic.dts (100%) rename boards/{arm => nxp}/ucans32k1sic/ucans32k1sic.yaml (100%) create mode 100644 boards/nxp/ucans32k1sic/ucans32k1sic_defconfig rename boards/{arm64/rpi_4b => nxp/usb_kw24d512}/CMakeLists.txt (100%) create mode 100644 boards/nxp/usb_kw24d512/Kconfig.defconfig create mode 100644 boards/nxp/usb_kw24d512/Kconfig.usb_kw24d512 rename boards/{arm => nxp}/usb_kw24d512/board.cmake (100%) create mode 100644 boards/nxp/usb_kw24d512/board.yml create mode 100644 boards/nxp/usb_kw24d512/doc/index.rst rename boards/{arm => nxp}/usb_kw24d512/usb_kw24d512-pinctrl.dtsi (100%) rename boards/{arm => nxp}/usb_kw24d512/usb_kw24d512.dts (100%) rename boards/{arm => nxp}/usb_kw24d512/usb_kw24d512.yaml (100%) create mode 100644 boards/nxp/usb_kw24d512/usb_kw24d512_defconfig create mode 100644 boards/nxp/vmu_rt1170/CMakeLists.txt create mode 100644 boards/nxp/vmu_rt1170/Kconfig.defconfig create mode 100644 boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 rename boards/{arm => nxp}/vmu_rt1170/board.cmake (100%) create mode 100644 boards/nxp/vmu_rt1170/board.yml rename boards/{arm => nxp}/vmu_rt1170/doc/index.rst (100%) rename boards/{arm => nxp}/vmu_rt1170/doc/vmu_rt1170.jpg (100%) create mode 100644 boards/nxp/vmu_rt1170/flexspi_nor_config.c rename boards/{arm => nxp}/vmu_rt1170/vmu_rt1170-pinctrl.dtsi (100%) rename boards/{arm => nxp}/vmu_rt1170/vmu_rt1170.dts (100%) rename boards/{arm => nxp}/vmu_rt1170/vmu_rt1170.dtsi (100%) rename boards/{arm => nxp}/vmu_rt1170/vmu_rt1170.yaml (89%) rename boards/{arm => nxp}/vmu_rt1170/vmu_rt1170_defconfig (86%) create mode 100644 boards/olimex/index.rst create mode 100644 boards/olimex/lora_stm32wl_devkit/Kconfig.olimex_lora_stm32wl_devkit rename boards/{arm/olimex_lora_stm32wl_devkit => olimex/lora_stm32wl_devkit}/board.cmake (100%) create mode 100644 boards/olimex/lora_stm32wl_devkit/board.yml rename boards/{arm/olimex_lora_stm32wl_devkit => olimex/lora_stm32wl_devkit}/doc/olimex-stm32wl-devkit.jpg (100%) rename boards/{arm/olimex_lora_stm32wl_devkit => olimex/lora_stm32wl_devkit}/doc/olimex_lora_stm32wl_devkit.rst (95%) rename boards/{arm/olimex_lora_stm32wl_devkit => olimex/lora_stm32wl_devkit}/olimex_lora_stm32wl_devkit.dts (100%) rename boards/{arm/olimex_lora_stm32wl_devkit => olimex/lora_stm32wl_devkit}/olimex_lora_stm32wl_devkit_C.conf (100%) rename boards/{arm/olimex_lora_stm32wl_devkit => olimex/lora_stm32wl_devkit}/olimex_lora_stm32wl_devkit_C.overlay (100%) rename boards/{arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.yaml => olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.yaml} (100%) rename boards/{arm/olimex_lora_stm32wl_devkit => olimex/lora_stm32wl_devkit}/olimex_lora_stm32wl_devkit_D.conf (100%) rename boards/{arm/olimex_lora_stm32wl_devkit => olimex/lora_stm32wl_devkit}/olimex_lora_stm32wl_devkit_D.overlay (100%) create mode 100644 boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml rename boards/{arm/olimex_lora_stm32wl_devkit => olimex/lora_stm32wl_devkit}/olimex_lora_stm32wl_devkit_defconfig (83%) create mode 100644 boards/olimex/olimex_esp32_evb/Kconfig create mode 100644 boards/olimex/olimex_esp32_evb/Kconfig.defconfig create mode 100644 boards/olimex/olimex_esp32_evb/Kconfig.olimex_esp32_evb rename boards/{xtensa/odroid_go => olimex/olimex_esp32_evb}/Kconfig.sysbuild (100%) rename boards/{xtensa/m5stack_atoms3_lite => olimex/olimex_esp32_evb}/board.cmake (100%) create mode 100644 boards/olimex/olimex_esp32_evb/board.yml rename boards/{xtensa => olimex}/olimex_esp32_evb/doc/ESP32-EVB.jpg (100%) create mode 100644 boards/olimex/olimex_esp32_evb/doc/index.rst rename boards/{xtensa => olimex}/olimex_esp32_evb/olimex_esp32_evb-pinctrl.dtsi (100%) create mode 100644 boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.dts create mode 100644 boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.yaml create mode 100644 boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig rename boards/{xtensa/olimex_esp32_evb/olimex_esp32_evb.dts => olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.dts} (100%) create mode 100644 boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.yaml create mode 100644 boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu_defconfig rename boards/{xtensa => olimex}/olimex_esp32_evb/support/openocd.cfg (100%) create mode 100644 boards/olimex/olimexino_stm32/Kconfig.defconfig create mode 100644 boards/olimex/olimexino_stm32/Kconfig.olimexino_stm32 rename boards/{arm => olimex}/olimexino_stm32/board.cmake (100%) create mode 100644 boards/olimex/olimexino_stm32/board.yml rename boards/{arm => olimex}/olimexino_stm32/doc/img/olimexino-stm32-front.jpg (100%) rename boards/{arm => olimex}/olimexino_stm32/doc/img/olimexino_stm32.jpg (100%) rename boards/{arm => olimex}/olimexino_stm32/doc/index.rst (100%) rename boards/{arm => olimex}/olimexino_stm32/olimexino_stm32.dts (100%) rename boards/{arm => olimex}/olimexino_stm32/olimexino_stm32.yaml (100%) rename boards/{arm => olimex}/olimexino_stm32/olimexino_stm32_defconfig (85%) rename boards/{arm => olimex}/olimexino_stm32/support/openocd.cfg (100%) create mode 100644 boards/olimex/stm32_e407/Kconfig.olimex_stm32_e407 rename boards/{arm/black_f407zg_pro => olimex/stm32_e407}/board.cmake (100%) create mode 100644 boards/olimex/stm32_e407/board.yml rename boards/{arm/olimex_stm32_e407 => olimex/stm32_e407}/doc/img/olimex-stm32-e407-front.jpg (100%) rename boards/{arm/olimex_stm32_e407 => olimex/stm32_e407}/doc/img/olimex_stm32_e407.jpg (100%) rename boards/{arm/olimex_stm32_e407 => olimex/stm32_e407}/doc/index.rst (100%) rename boards/{arm/olimex_stm32_e407 => olimex/stm32_e407}/olimex_stm32_e407.dts (100%) rename boards/{arm/olimex_stm32_e407 => olimex/stm32_e407}/olimex_stm32_e407.yaml (100%) rename boards/{arm/olimex_stm32_e407 => olimex/stm32_e407}/olimex_stm32_e407_defconfig (84%) rename boards/{arm/olimex_stm32_e407 => olimex/stm32_e407}/support/openocd.cfg (100%) create mode 100644 boards/olimex/stm32_h103/Kconfig.olimex_stm32_h103 rename boards/{arm/olimex_stm32_h103 => olimex/stm32_h103}/board.cmake (100%) create mode 100644 boards/olimex/stm32_h103/board.yml rename boards/{arm/olimex_stm32_h103 => olimex/stm32_h103}/doc/img/olimex_stm32_h103_bottom.jpg (100%) rename boards/{arm/olimex_stm32_h103 => olimex/stm32_h103}/doc/img/olimex_stm32_h103_top.jpg (100%) rename boards/{arm/olimex_stm32_h103 => olimex/stm32_h103}/doc/index.rst (100%) rename boards/{arm/olimex_stm32_h103 => olimex/stm32_h103}/olimex_stm32_h103.dts (100%) rename boards/{arm/olimex_stm32_h103 => olimex/stm32_h103}/olimex_stm32_h103.yaml (100%) rename boards/{arm/olimex_stm32_h103 => olimex/stm32_h103}/olimex_stm32_h103_defconfig (81%) rename boards/{arm/olimex_stm32_h103 => olimex/stm32_h103}/support/openocd.cfg (100%) rename boards/{arm/olimex_stm32_h103 => olimex/stm32_h103}/support/openocd_olimex_jtag.cfg (100%) rename boards/{arm/olimex_stm32_h103 => olimex/stm32_h103}/support/openocd_stlink.cfg (100%) create mode 100644 boards/olimex/stm32_h405/Kconfig.olimex_stm32_h405 rename boards/{arm/olimex_stm32_h405 => olimex/stm32_h405}/board.cmake (100%) create mode 100644 boards/olimex/stm32_h405/board.yml rename boards/{arm/olimex_stm32_h405 => olimex/stm32_h405}/doc/index.rst (100%) rename boards/{arm/olimex_stm32_h405 => olimex/stm32_h405}/doc/olimex_stm32_h405_bottom.jpg (100%) rename boards/{arm/olimex_stm32_h405 => olimex/stm32_h405}/doc/olimex_stm32_h405_top.jpg (100%) rename boards/{arm/olimex_stm32_h405 => olimex/stm32_h405}/olimex_stm32_h405.dts (100%) rename boards/{arm/olimex_stm32_h405 => olimex/stm32_h405}/olimex_stm32_h405.yaml (100%) rename boards/{arm/olimex_stm32_h405 => olimex/stm32_h405}/olimex_stm32_h405_defconfig (84%) rename boards/{arm/olimex_stm32_h405 => olimex/stm32_h405}/support/openocd.cfg (100%) create mode 100644 boards/olimex/stm32_h407/Kconfig.olimex_stm32_h407 rename boards/{arm/olimex_stm32_e407 => olimex/stm32_h407}/board.cmake (100%) create mode 100644 boards/olimex/stm32_h407/board.yml rename boards/{arm/olimex_stm32_h407 => olimex/stm32_h407}/doc/img/olimex-stm32-h407-front.jpg (100%) rename boards/{arm/olimex_stm32_h407 => olimex/stm32_h407}/doc/img/olimex_stm32_h407.jpg (100%) rename boards/{arm/olimex_stm32_h407 => olimex/stm32_h407}/doc/index.rst (100%) rename boards/{arm/olimex_stm32_h407 => olimex/stm32_h407}/olimex_stm32_h407.dts (100%) rename boards/{arm/olimex_stm32_h407 => olimex/stm32_h407}/olimex_stm32_h407.yaml (100%) rename boards/{arm/olimex_stm32_h407 => olimex/stm32_h407}/olimex_stm32_h407_defconfig (84%) rename boards/{arm/olimex_stm32_h407 => olimex/stm32_h407}/support/openocd.cfg (100%) create mode 100644 boards/olimex/stm32_p405/Kconfig.olimex_stm32_p405 rename boards/{arm/olimex_stm32_p405 => olimex/stm32_p405}/board.cmake (100%) create mode 100644 boards/olimex/stm32_p405/board.yml rename boards/{arm/olimex_stm32_p405 => olimex/stm32_p405}/doc/img/olimex-stm32-p405-front.jpg (100%) rename boards/{arm/olimex_stm32_p405 => olimex/stm32_p405}/doc/img/olimex_stm32_p405.jpg (100%) rename boards/{arm/olimex_stm32_p405 => olimex/stm32_p405}/doc/index.rst (100%) rename boards/{arm/olimex_stm32_p405 => olimex/stm32_p405}/olimex_stm32_p405.dts (100%) rename boards/{arm/olimex_stm32_p405 => olimex/stm32_p405}/olimex_stm32_p405.yaml (100%) rename boards/{arm/olimex_stm32_p405 => olimex/stm32_p405}/olimex_stm32_p405_defconfig (85%) rename boards/{arm/olimex_stm32_p405 => olimex/stm32_p405}/support/openocd.cfg (100%) create mode 100644 boards/openisa/index.rst create mode 100644 boards/openisa/rv32m1_vega/Kconfig.defconfig create mode 100644 boards/openisa/rv32m1_vega/Kconfig.rv32m1_vega create mode 100644 boards/openisa/rv32m1_vega/board.cmake create mode 100644 boards/openisa/rv32m1_vega/board.yml create mode 100644 boards/openisa/rv32m1_vega/doc/index.rst rename boards/{riscv => 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openisa}/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg (100%) create mode 100644 boards/others/black_f407ve/Kconfig.black_f407ve create mode 100644 boards/others/black_f407ve/Kconfig.defconfig rename boards/{arm => others}/black_f407ve/black_f407ve.dts (100%) rename boards/{arm => others}/black_f407ve/black_f407ve.yaml (100%) rename boards/{arm => others}/black_f407ve/black_f407ve_defconfig (85%) rename boards/{arm => others}/black_f407ve/board.cmake (100%) create mode 100644 boards/others/black_f407ve/board.yml rename boards/{arm => others}/black_f407ve/doc/img/black_f407ve.jpg (100%) rename boards/{arm => others}/black_f407ve/doc/img/stm32f407vet6_left02.jpg (100%) rename boards/{arm => others}/black_f407ve/doc/img/stm32f407vet6_right01.jpg (100%) rename boards/{arm => others}/black_f407ve/doc/img/stm32f407vet6_st-link02.jpg (100%) create mode 100644 boards/others/black_f407ve/doc/index.rst rename boards/{arm => others}/black_f407ve/support/openocd.cfg (100%) create mode 100644 boards/others/black_f407zg_pro/Kconfig.black_f407zg_pro create mode 100644 boards/others/black_f407zg_pro/Kconfig.defconfig rename boards/{arm => others}/black_f407zg_pro/black_f407zg_pro.dts (100%) rename boards/{arm => others}/black_f407zg_pro/black_f407zg_pro.yaml (100%) rename boards/{arm => others}/black_f407zg_pro/black_f407zg_pro_defconfig (85%) rename boards/{arm/olimex_stm32_h407 => others/black_f407zg_pro}/board.cmake (100%) create mode 100644 boards/others/black_f407zg_pro/board.yml rename boards/{arm => others}/black_f407zg_pro/doc/img/black_f407zg_pro.jpg (100%) create mode 100644 boards/others/black_f407zg_pro/doc/index.rst rename boards/{arm => others}/black_f407zg_pro/support/openocd.cfg (100%) create mode 100644 boards/others/icev_wireless/Kconfig.defconfig create mode 100644 boards/others/icev_wireless/Kconfig.icev_wireless rename boards/{xtensa/olimex_esp32_evb => others/icev_wireless}/Kconfig.sysbuild (100%) rename boards/{xtensa/m5stack_core2 => others/icev_wireless}/board.cmake (100%) create mode 100644 boards/others/icev_wireless/board.yml rename boards/{riscv => others}/icev_wireless/doc/img/icev_wireless.jpg (100%) rename boards/{riscv => others}/icev_wireless/doc/img/icev_wireless_back.jpg (100%) rename boards/{riscv => others}/icev_wireless/doc/img/icev_wireless_pinout.jpg (100%) create mode 100644 boards/others/icev_wireless/doc/index.rst rename boards/{riscv => others}/icev_wireless/icev_wireless-pinctrl.dtsi (100%) rename boards/{riscv => others}/icev_wireless/icev_wireless.dts (98%) rename boards/{riscv => others}/icev_wireless/icev_wireless.yaml (100%) create mode 100644 boards/others/icev_wireless/icev_wireless_defconfig rename boards/{riscv => others}/icev_wireless/support/openocd.cfg (100%) create mode 100644 boards/others/index.rst rename boards/{riscv => others}/neorv32/CMakeLists.txt (100%) create mode 100644 boards/others/neorv32/Kconfig create mode 100644 boards/others/neorv32/Kconfig.neorv32 rename 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boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml create mode 100644 boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp_defconfig create mode 100644 boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts create mode 100644 boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml create mode 100644 boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet_defconfig rename boards/{arm/pan1783/pan1783_cpuapp_common-pinctrl.dtsi => panasonic/pan1783/pan1783_nrf5340_cpuapp_common-pinctrl.dtsi} (100%) create mode 100644 boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi create mode 100644 boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_partition_conf.dtsi rename boards/{arm/pan1783/pan1783_cpunet-pinctrl.dtsi => panasonic/pan1783/pan1783_nrf5340_cpunet-pinctrl.dtsi} (100%) create mode 100644 boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi create mode 100644 boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c rename 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boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml create mode 100644 boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet_defconfig rename boards/{arm => panasonic}/pan1783/pre_dt_board.cmake (100%) rename boards/{arm/particle_argon => particle/argon}/CMakeLists.txt (100%) rename boards/{arm/particle_argon => particle/argon}/Kconfig (100%) create mode 100644 boards/particle/argon/Kconfig.defconfig create mode 100644 boards/particle/argon/Kconfig.particle_argon rename boards/{arm/particle_argon => particle/argon}/board.c (100%) rename boards/{arm/particle_argon => particle/argon}/board.cmake (100%) create mode 100644 boards/particle/argon/board.yml rename boards/{arm/particle_argon => particle/argon}/doc/img/particle_argon.jpg (100%) rename boards/{arm/particle_argon => particle/argon}/doc/index.rst (100%) rename boards/{arm/particle_argon => particle/argon}/dts/mesh_feather-pinctrl.dtsi (100%) rename boards/{arm/particle_argon => particle/argon}/dts/mesh_feather.dtsi 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particle/nrf51_blenano/nrf51_blenano-pinctrl.dtsi} (100%) rename boards/{arm => particle}/nrf51_blenano/nrf51_blenano.dts (100%) rename boards/{arm => particle}/nrf51_blenano/nrf51_blenano.yaml (100%) create mode 100644 boards/particle/nrf51_blenano/nrf51_blenano_defconfig rename boards/{arm/nrf51_vbluno51 => particle/nrf51_blenano}/pre_dt_board.cmake (100%) create mode 100644 boards/particle/nrf52_blenano2/Kconfig.defconfig create mode 100644 boards/particle/nrf52_blenano2/Kconfig.nrf52_blenano2 rename boards/{arm => particle}/nrf52_blenano2/board.cmake (100%) create mode 100644 boards/particle/nrf52_blenano2/board.yml rename boards/{arm => particle}/nrf52_blenano2/doc/dap.jpg (100%) rename boards/{arm => particle}/nrf52_blenano2/doc/index.rst (100%) rename boards/{arm => particle}/nrf52_blenano2/doc/nrf52_blenano2.jpg (100%) rename boards/{arm => particle}/nrf52_blenano2/nrf52_blenano2-pinctrl.dtsi (100%) rename boards/{arm => particle}/nrf52_blenano2/nrf52_blenano2.dts (100%) rename boards/{arm => particle}/nrf52_blenano2/nrf52_blenano2.yaml (100%) create mode 100644 boards/particle/nrf52_blenano2/nrf52_blenano2_defconfig rename boards/{arm/nrf9160dk_nrf52840 => particle/nrf52_blenano2}/pre_dt_board.cmake (100%) rename boards/{arm/particle_xenon => particle/xenon}/CMakeLists.txt (100%) rename boards/{arm/particle_xenon => particle/xenon}/Kconfig (100%) create mode 100644 boards/particle/xenon/Kconfig.defconfig create mode 100644 boards/particle/xenon/Kconfig.particle_xenon rename boards/{arm/particle_xenon => particle/xenon}/board.c (100%) rename boards/{arm/particle_xenon => particle/xenon}/board.cmake (100%) create mode 100644 boards/particle/xenon/board.yml rename boards/{arm/particle_xenon => particle/xenon}/doc/img/particle_xenon.jpg (100%) rename boards/{arm/particle_xenon => particle/xenon}/doc/index.rst (100%) rename boards/{arm/particle_xenon => particle/xenon}/dts/mesh_feather-pinctrl.dtsi (100%) rename boards/{arm/particle_xenon => particle/xenon}/dts/mesh_feather.dtsi (100%) rename boards/{arm/particle_xenon => particle/xenon}/dts/mesh_feather_i2c1_twi1.dtsi (100%) rename boards/{arm/particle_xenon => particle/xenon}/dts/mesh_feather_spi1_spi3.dtsi (100%) rename boards/{arm/particle_xenon => particle/xenon}/dts/mesh_feather_spi_spi1.dtsi (100%) rename boards/{arm/particle_xenon => particle/xenon}/dts/mesh_feather_spi_spi3.dtsi (100%) rename boards/{arm/particle_xenon => particle/xenon}/dts/mesh_feather_uart1_rtscts.dtsi (100%) rename boards/{arm/particle_xenon => particle/xenon}/dts/mesh_xenon_uart2.dtsi (100%) rename boards/{arm/particle_xenon => particle/xenon}/particle_xenon-pinctrl.dtsi (100%) rename boards/{arm/particle_xenon => particle/xenon}/particle_xenon.dts (100%) rename boards/{arm/particle_xenon => particle/xenon}/particle_xenon.yaml (100%) create mode 100644 boards/particle/xenon/particle_xenon_defconfig rename boards/{arm/particle_argon => particle/xenon}/pre_dt_board.cmake (100%) create mode 100644 boards/phytec/index.rst create mode 100644 boards/phytec/mimx8mm_phyboard_polis/Kconfig.defconfig create mode 100644 boards/phytec/mimx8mm_phyboard_polis/Kconfig.mimx8mm_phyboard_polis rename boards/{arm/mimx8mm_evk => phytec/mimx8mm_phyboard_polis}/board.cmake (100%) create mode 100644 boards/phytec/mimx8mm_phyboard_polis/board.yml rename boards/{arm => phytec}/mimx8mm_phyboard_polis/doc/img/PEB-EVAL-01.jpg (100%) rename boards/{arm => phytec}/mimx8mm_phyboard_polis/doc/img/phyBOARD-Polis.jpg (100%) create mode 100644 boards/phytec/mimx8mm_phyboard_polis/doc/index.rst rename boards/{arm => phytec}/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi (100%) rename boards/{arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.dts => phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.dts} (100%) create mode 100644 boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.yaml create mode 100644 boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig create mode 100644 boards/phytec/mimx8mp_phyboard_pollux/Kconfig.defconfig create mode 100644 boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux rename boards/{arm => phytec}/mimx8mp_phyboard_pollux/board.cmake (100%) create mode 100644 boards/phytec/mimx8mp_phyboard_pollux/board.yml rename boards/{arm => phytec}/mimx8mp_phyboard_pollux/doc/img/PEB-EVAL-01.jpg (100%) rename boards/{arm => phytec}/mimx8mp_phyboard_pollux/doc/img/Phyboard_Pollux.jpg (100%) create mode 100644 boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst rename boards/{arm => phytec}/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux-pinctrl.dtsi (100%) rename boards/{arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux.dts => phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.dts} (100%) create mode 100644 boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.yaml create mode 100644 boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig create mode 100644 boards/phytec/phyboard_lyra_am62x/Kconfig.phyboard_lyra_am62x create mode 100644 boards/phytec/phyboard_lyra_am62x/board.yml rename boards/{arm/am62x_m4 => phytec/phyboard_lyra_am62x}/doc/img/phyCORE-AM62x_Lyra_frontside.webp (100%) create mode 100644 boards/phytec/phyboard_lyra_am62x/doc/index.rst rename boards/{arm/am62x_m4/am62x_m4_phyboard_lyra.dts => phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.dts} (100%) create mode 100644 boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.yaml create mode 100644 boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4_defconfig create mode 100644 boards/phytec/phycore_am62x/Kconfig.phycore_am62x create mode 100644 boards/phytec/phycore_am62x/board.yml create mode 100644 boards/phytec/phycore_am62x/doc/index.rst rename boards/{arm64/phycore_am62x_a53/phycore_am62x_a53.dts => phytec/phycore_am62x/phycore_am62x_am6234_a53.dts} (100%) create mode 100644 boards/phytec/phycore_am62x/phycore_am62x_am6234_a53.yaml create mode 100644 boards/phytec/phycore_am62x/phycore_am62x_am6234_a53_defconfig rename boards/{arm => phytec}/reel_board/CMakeLists.txt (100%) create mode 100644 boards/phytec/reel_board/Kconfig create mode 100644 boards/phytec/reel_board/Kconfig.defconfig create mode 100644 boards/phytec/reel_board/Kconfig.reel_board rename boards/{arm => phytec}/reel_board/board.c (100%) rename boards/{arm => phytec}/reel_board/board.cmake (100%) create mode 100644 boards/phytec/reel_board/board.yml rename boards/{arm => phytec}/reel_board/doc/img/link_board_base.jpg (100%) rename boards/{arm => phytec}/reel_board/doc/img/rb_lb_shield.jpg (100%) rename boards/{arm => phytec}/reel_board/doc/img/reel_board.jpg (100%) rename boards/{arm => phytec}/reel_board/doc/img/reel_board_debug.jpg (100%) rename boards/{arm => phytec}/reel_board/doc/img/reel_board_descr_back.jpg (100%) rename boards/{arm => phytec}/reel_board/doc/img/reel_board_excon.jpg (100%) rename boards/{arm => phytec}/reel_board/doc/img/reel_board_tp.jpg (100%) create mode 100644 boards/phytec/reel_board/doc/index.rst rename boards/{arm => phytec}/reel_board/dts/reel_board-pinctrl.dtsi (100%) rename boards/{arm => phytec}/reel_board/dts/reel_board.dtsi (100%) rename boards/{arm/particle_boron => phytec/reel_board}/pre_dt_board.cmake (100%) rename boards/{arm => phytec}/reel_board/reel_board-pinctrl.dtsi (100%) rename boards/{arm => phytec}/reel_board/reel_board.dts (100%) rename boards/{arm/reel_board/reel_board.yaml => phytec/reel_board/reel_board_1.yaml} (100%) create mode 100644 boards/phytec/reel_board/reel_board_defconfig rename boards/{arm/reel_board/reel_board_v2-pinctrl.dtsi => phytec/reel_board/reel_board_nrf52840_2-pinctrl.dtsi} (100%) create mode 100644 boards/phytec/reel_board/reel_board_nrf52840_2.overlay create mode 100644 boards/phytec/reel_board/reel_board_nrf52840_2.yaml rename boards/{arm => phytec}/reel_board/support/pyocd.yaml (100%) create mode 100644 boards/pine64/index.rst create mode 100644 boards/pine64/pinetime_devkit0/Kconfig.defconfig create mode 100644 boards/pine64/pinetime_devkit0/Kconfig.pinetime_devkit0 rename boards/{arm => pine64}/pinetime_devkit0/board.cmake (100%) create mode 100644 boards/pine64/pinetime_devkit0/board.yml rename boards/{arm => pine64}/pinetime_devkit0/doc/img/PineTime_DevKit0.jpg (100%) rename boards/{arm => pine64}/pinetime_devkit0/doc/img/PineTime_SWD_location.jpg (100%) rename boards/{arm => pine64}/pinetime_devkit0/doc/img/PineTime_leaflet.jpg (100%) rename boards/{arm => pine64}/pinetime_devkit0/doc/index.rst (100%) rename boards/{arm => pine64}/pinetime_devkit0/pinetime_devkit0-pinctrl.dtsi (100%) rename boards/{arm => pine64}/pinetime_devkit0/pinetime_devkit0.dts (100%) rename boards/{arm => pine64}/pinetime_devkit0/pinetime_devkit0.yaml (100%) create mode 100644 boards/pine64/pinetime_devkit0/pinetime_devkit0_defconfig rename boards/{arm/particle_xenon => pine64/pinetime_devkit0}/pre_dt_board.cmake (100%) create mode 100644 boards/pjrc/index.rst create mode 100644 boards/pjrc/teensy4/CMakeLists.txt create mode 100644 boards/pjrc/teensy4/Kconfig.defconfig create mode 100644 boards/pjrc/teensy4/Kconfig.teensy40 create mode 100644 boards/pjrc/teensy4/Kconfig.teensy41 create mode 100644 boards/pjrc/teensy4/board.yml rename boards/{arm => pjrc}/teensy4/doc/index.rst (100%) rename boards/{arm => pjrc}/teensy4/doc/teensy40.jpg (100%) rename boards/{arm => pjrc}/teensy4/doc/teensy41.jpg (100%) create mode 100644 boards/pjrc/teensy4/flexspi_nor_config.c rename boards/{arm => pjrc}/teensy4/teensy4-pinctrl.dtsi (100%) rename boards/{arm => pjrc}/teensy4/teensy40.dts (100%) rename boards/{arm => pjrc}/teensy4/teensy40.yaml (100%) rename boards/{arm => pjrc}/teensy4/teensy40_defconfig (79%) rename boards/{arm => pjrc}/teensy4/teensy41.dts (100%) rename boards/{arm => pjrc}/teensy4/teensy41.yaml (100%) rename boards/{arm => pjrc}/teensy4/teensy41_defconfig (79%) delete mode 100644 boards/posix/native_posix/CMakeLists.txt delete mode 100644 boards/posix/native_posix/Kconfig delete mode 100644 boards/posix/native_posix/Kconfig.board delete mode 100644 boards/posix/native_posix/Kconfig.defconfig delete mode 100644 boards/posix/native_posix/native_posix_64_defconfig delete mode 100644 boards/posix/native_posix/native_posix_defconfig delete mode 100644 boards/posix/native_sim/CMakeLists.txt delete mode 100644 boards/posix/native_sim/Kconfig delete mode 100644 boards/posix/native_sim/Kconfig.board delete mode 100644 boards/posix/native_sim/Kconfig.defconfig delete mode 100644 boards/posix/native_sim/board.cmake delete mode 100644 boards/posix/native_sim/native_sim_64_defconfig delete mode 100644 boards/posix/native_sim/native_sim_defconfig delete mode 100644 boards/posix/nrf_bsim/CMakeLists.txt delete mode 100644 boards/posix/nrf_bsim/Kconfig delete mode 100644 boards/posix/nrf_bsim/Kconfig.board delete mode 100644 boards/posix/nrf_bsim/Kconfig.defconfig delete mode 100644 boards/posix/nrf_bsim/board.cmake delete mode 100644 boards/posix/nrf_bsim/nrf52_bsim_defconfig delete mode 100644 boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig delete mode 100644 boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig delete mode 100644 boards/posix/nrf_bsim/pre_dt_board.cmake delete mode 100644 boards/posix/nrf_bsim/soc/pinctrl_soc.h rename boards/{arc/iotdk => qemu/arc}/CMakeLists.txt (100%) create mode 100644 boards/qemu/arc/Kconfig create mode 100644 boards/qemu/arc/Kconfig.defconfig create mode 100644 boards/qemu/arc/Kconfig.qemu_arc rename boards/{arc/qemu_arc => qemu/arc}/arc_mpu_regions.c (100%) create mode 100644 boards/qemu/arc/board.cmake create mode 100644 boards/qemu/arc/board.yml create mode 100644 boards/qemu/arc/doc/index.rst rename boards/{arc/qemu_arc => qemu/arc}/qemu_arc.dtsi (100%) rename boards/{arc/qemu_arc/qemu_arc_em.dts => qemu/arc/qemu_arc_qemu_arc_em.dts} (100%) create mode 100644 boards/qemu/arc/qemu_arc_qemu_arc_em.yaml create mode 100644 boards/qemu/arc/qemu_arc_qemu_arc_em_defconfig rename boards/{arc/qemu_arc/qemu_arc_hs.dts => qemu/arc/qemu_arc_qemu_arc_hs.dts} (100%) create mode 100644 boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml rename boards/{arc/qemu_arc/qemu_arc_hs5x.dts => qemu/arc/qemu_arc_qemu_arc_hs5x.dts} (100%) create mode 100644 boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml create mode 100644 boards/qemu/arc/qemu_arc_qemu_arc_hs5x_defconfig rename boards/{arc/qemu_arc/qemu_arc_hs6x.dts => qemu/arc/qemu_arc_qemu_arc_hs6x.dts} (100%) create mode 100644 boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml create mode 100644 boards/qemu/arc/qemu_arc_qemu_arc_hs6x_defconfig create mode 100644 boards/qemu/arc/qemu_arc_qemu_arc_hs_defconfig rename boards/{arc/qemu_arc/qemu_arc_hs_xip.dts => qemu/arc/qemu_arc_qemu_arc_hs_xip.dts} (100%) create mode 100644 boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml create mode 100644 boards/qemu/arc/qemu_arc_qemu_arc_hs_xip_defconfig create mode 100644 boards/qemu/cortex_a53/Kconfig create mode 100644 boards/qemu/cortex_a53/Kconfig.defconfig create mode 100644 boards/qemu/cortex_a53/Kconfig.qemu_cortex_a53 create mode 100644 boards/qemu/cortex_a53/board.cmake create mode 100644 boards/qemu/cortex_a53/board.yml rename boards/{arm64/qemu_cortex_a53 => qemu/cortex_a53}/doc/index.rst (100%) rename boards/{arm64/qemu_cortex_a53 => qemu/cortex_a53}/qemu_cortex_a53.dts (100%) rename boards/{arm64/qemu_cortex_a53 => qemu/cortex_a53}/qemu_cortex_a53.yaml (100%) create mode 100644 boards/qemu/cortex_a53/qemu_cortex_a53_defconfig rename boards/{arm64/qemu_cortex_a53/qemu_cortex_a53_smp.dts => qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.dts} (100%) create mode 100644 boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml create mode 100644 boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp_defconfig rename boards/{arm64/qemu_cortex_a53/qemu_cortex_a53_xip.dts => qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.dts} (100%) create mode 100644 boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml create mode 100644 boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip_defconfig create mode 100644 boards/qemu/cortex_a9/Kconfig create mode 100644 boards/qemu/cortex_a9/Kconfig.defconfig create mode 100644 boards/qemu/cortex_a9/Kconfig.qemu_cortex_a9 create mode 100644 boards/qemu/cortex_a9/board.cmake create mode 100644 boards/qemu/cortex_a9/board.yml rename boards/{arm/qemu_cortex_a9 => qemu/cortex_a9}/fdt-zynq7000s.dtb (100%) rename boards/{arm/qemu_cortex_a9 => qemu/cortex_a9}/qemu_cortex_a9.dts (100%) rename boards/{arm/qemu_cortex_a9 => qemu/cortex_a9}/qemu_cortex_a9.yaml (100%) rename boards/{arm/qemu_cortex_a9 => qemu/cortex_a9}/qemu_cortex_a9_defconfig (82%) rename boards/{arm/qemu_cortex_m0 => qemu/cortex_m0}/CMakeLists.txt (100%) create mode 100644 boards/qemu/cortex_m0/Kconfig create mode 100644 boards/qemu/cortex_m0/Kconfig.defconfig create mode 100644 boards/qemu/cortex_m0/Kconfig.qemu_cortex_m0 rename boards/{arm/qemu_cortex_m0 => qemu/cortex_m0}/board.cmake (100%) create mode 100644 boards/qemu/cortex_m0/board.yml rename boards/{arm/qemu_cortex_m0 => qemu/cortex_m0}/doc/index.rst (100%) rename boards/{arm/qemu_cortex_m0 => qemu/cortex_m0}/nrf_timer_timer.c (100%) rename boards/{arm/nrf51dk_nrf51422 => qemu/cortex_m0}/pre_dt_board.cmake (100%) rename boards/{arm/qemu_cortex_m0 => qemu/cortex_m0}/qemu_cortex_m0-pinctrl.dtsi (100%) rename boards/{arm/qemu_cortex_m0 => qemu/cortex_m0}/qemu_cortex_m0.dts (100%) rename boards/{arm/qemu_cortex_m0 => qemu/cortex_m0}/qemu_cortex_m0.yaml (100%) create mode 100644 boards/qemu/cortex_m0/qemu_cortex_m0_defconfig create mode 100644 boards/qemu/cortex_m3/Kconfig create mode 100644 boards/qemu/cortex_m3/Kconfig.defconfig create mode 100644 boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 create mode 100644 boards/qemu/cortex_m3/board.cmake create mode 100644 boards/qemu/cortex_m3/board.yml rename boards/{arm/qemu_cortex_m3 => qemu/cortex_m3}/doc/index.rst (100%) rename boards/{arm/qemu_cortex_m3 => qemu/cortex_m3}/qemu_cortex_m3.dts (95%) rename boards/{arm/qemu_cortex_m3 => qemu/cortex_m3}/qemu_cortex_m3.yaml (100%) rename boards/{arm/qemu_cortex_m3 => qemu/cortex_m3}/qemu_cortex_m3_defconfig (77%) create mode 100644 boards/qemu/cortex_r5/Kconfig create mode 100644 boards/qemu/cortex_r5/Kconfig.defconfig create mode 100644 boards/qemu/cortex_r5/Kconfig.qemu_cortex_r5 create mode 100644 boards/qemu/cortex_r5/board.cmake create mode 100644 boards/qemu/cortex_r5/board.yml rename boards/{arm/qemu_cortex_r5 => qemu/cortex_r5}/doc/index.rst (100%) rename boards/{arm/qemu_cortex_r5 => qemu/cortex_r5}/fdt-single_arch-zcu102-arm.dtb (100%) rename boards/{arm/qemu_cortex_r5 => qemu/cortex_r5}/qemu_cortex_r5.dts (100%) rename boards/{arm/qemu_cortex_r5 => qemu/cortex_r5}/qemu_cortex_r5.yaml (100%) rename boards/{arm/qemu_cortex_r5 => qemu/cortex_r5}/qemu_cortex_r5_defconfig (79%) create mode 100644 boards/qemu/index.rst create mode 100644 boards/qemu/kvm_arm64/Kconfig create mode 100644 boards/qemu/kvm_arm64/Kconfig.defconfig create mode 100644 boards/qemu/kvm_arm64/Kconfig.qemu_kvm_arm64 rename boards/{arm64/qemu_kvm_arm64 => qemu/kvm_arm64}/board.cmake (100%) create mode 100644 boards/qemu/kvm_arm64/board.yml rename boards/{arm64/qemu_kvm_arm64 => qemu/kvm_arm64}/doc/index.rst (100%) rename boards/{arm64/qemu_kvm_arm64 => qemu/kvm_arm64}/qemu_kvm_arm64.dts (100%) rename boards/{arm64/qemu_kvm_arm64 => qemu/kvm_arm64}/qemu_kvm_arm64.yaml (100%) rename boards/{arm64/qemu_kvm_arm64 => qemu/kvm_arm64}/qemu_kvm_arm64_defconfig (83%) create mode 100644 boards/qemu/leon3/Kconfig create mode 100644 boards/qemu/leon3/Kconfig.defconfig create mode 100644 boards/qemu/leon3/Kconfig.qemu_leon3 rename boards/{sparc/qemu_leon3 => qemu/leon3}/board.cmake (100%) create mode 100644 boards/qemu/leon3/board.yml rename boards/{sparc/qemu_leon3 => qemu/leon3}/doc/index.rst (100%) rename boards/{sparc/qemu_leon3 => qemu/leon3}/qemu_leon3.dts (100%) rename boards/{sparc/qemu_leon3 => qemu/leon3}/qemu_leon3.yaml (100%) rename boards/{sparc/qemu_leon3 => qemu/leon3}/qemu_leon3_defconfig (77%) create mode 100644 boards/qemu/malta/Kconfig create mode 100644 boards/qemu/malta/Kconfig.defconfig create mode 100644 boards/qemu/malta/Kconfig.qemu_malta rename boards/{mips/qemu_malta => qemu/malta}/board.cmake (100%) create mode 100644 boards/qemu/malta/board.yml create mode 100644 boards/qemu/malta/doc/index.rst rename boards/{mips/qemu_malta => qemu/malta}/qemu_malta.dts (100%) rename boards/{mips/qemu_malta => qemu/malta}/qemu_malta.yaml (100%) create mode 100644 boards/qemu/malta/qemu_malta_defconfig rename boards/{mips/qemu_malta/qemu_malta_be.dts => qemu/malta/qemu_malta_qemu_malta_be.dts} (100%) create mode 100644 boards/qemu/malta/qemu_malta_qemu_malta_be.yaml create mode 100644 boards/qemu/malta/qemu_malta_qemu_malta_be_defconfig create mode 100644 boards/qemu/nios2/Kconfig create mode 100644 boards/qemu/nios2/Kconfig.defconfig create mode 100644 boards/qemu/nios2/Kconfig.qemu_nios2 create mode 100644 boards/qemu/nios2/board.cmake create mode 100644 boards/qemu/nios2/board.yml rename boards/{nios2/qemu_nios2 => qemu/nios2}/doc/index.rst (100%) rename boards/{nios2/qemu_nios2 => qemu/nios2}/qemu_nios2.dts (100%) rename boards/{nios2/qemu_nios2 => qemu/nios2}/qemu_nios2.yaml (100%) rename boards/{nios2/qemu_nios2 => qemu/nios2}/qemu_nios2_defconfig (80%) create mode 100644 boards/qemu/riscv32/Kconfig create mode 100644 boards/qemu/riscv32/Kconfig.defconfig create mode 100644 boards/qemu/riscv32/Kconfig.qemu_riscv32 create mode 100644 boards/qemu/riscv32/board.cmake create mode 100644 boards/qemu/riscv32/board.yml rename boards/{riscv/qemu_riscv32 => qemu/riscv32}/doc/index.rst (100%) rename boards/{riscv/qemu_riscv32 => qemu/riscv32}/qemu_riscv32.dts (100%) rename boards/{riscv/qemu_riscv32 => qemu/riscv32}/qemu_riscv32.yaml (100%) create mode 100644 boards/qemu/riscv32/qemu_riscv32_defconfig create mode 100644 boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml create mode 100644 boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig create mode 100644 boards/qemu/riscv32_xip/Kconfig create mode 100644 boards/qemu/riscv32_xip/Kconfig.defconfig create mode 100644 boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip create mode 100644 boards/qemu/riscv32_xip/board.cmake create mode 100644 boards/qemu/riscv32_xip/board.yml create mode 100644 boards/qemu/riscv32_xip/doc/index.rst rename boards/{riscv/qemu_riscv32 => qemu/riscv32_xip}/qemu_riscv32_xip-pinctrl.dtsi (100%) rename boards/{riscv/qemu_riscv32 => qemu/riscv32_xip}/qemu_riscv32_xip.dts (100%) rename boards/{riscv/qemu_riscv32 => qemu/riscv32_xip}/qemu_riscv32_xip.yaml (100%) create mode 100644 boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig create mode 100644 boards/qemu/riscv32e/Kconfig create mode 100644 boards/qemu/riscv32e/Kconfig.defconfig create mode 100644 boards/qemu/riscv32e/Kconfig.qemu_riscv32e rename boards/{riscv/qemu_riscv32e => qemu/riscv32e}/board.cmake (100%) create mode 100644 boards/qemu/riscv32e/board.yml rename boards/{riscv/qemu_riscv32e => qemu/riscv32e}/doc/index.rst (100%) rename boards/{riscv/qemu_riscv32e => qemu/riscv32e}/qemu_riscv32e.dts (100%) rename boards/{riscv/qemu_riscv32e => qemu/riscv32e}/qemu_riscv32e.yaml (100%) rename boards/{riscv/qemu_riscv32e => qemu/riscv32e}/qemu_riscv32e_defconfig (76%) create mode 100644 boards/qemu/riscv64/Kconfig create mode 100644 boards/qemu/riscv64/Kconfig.defconfig create mode 100644 boards/qemu/riscv64/Kconfig.qemu_riscv64 rename boards/{riscv/qemu_riscv64 => qemu/riscv64}/board.cmake (100%) create mode 100644 boards/qemu/riscv64/board.yml rename boards/{riscv/qemu_riscv64 => qemu/riscv64}/doc/index.rst (100%) rename boards/{riscv/qemu_riscv64 => qemu/riscv64}/qemu_riscv64.dts (100%) rename boards/{riscv/qemu_riscv64 => qemu/riscv64}/qemu_riscv64.yaml (100%) create mode 100644 boards/qemu/riscv64/qemu_riscv64_defconfig create mode 100644 boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml create mode 100644 boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig create mode 100644 boards/qemu/x86/CMakeLists.txt create mode 100644 boards/qemu/x86/Kconfig create mode 100644 boards/qemu/x86/Kconfig.defconfig create mode 100644 boards/qemu/x86/Kconfig.qemu_x86 create mode 100644 boards/qemu/x86/Kconfig.qemu_x86_64 create mode 100644 boards/qemu/x86/Kconfig.qemu_x86_lakemont create mode 100644 boards/qemu/x86/Kconfig.qemu_x86_tiny create mode 100644 boards/qemu/x86/board.cmake create mode 100644 boards/qemu/x86/board.yml rename boards/{x86/qemu_x86 => qemu/x86}/doc/index.rst (100%) rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86.dts (97%) rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86.yaml (100%) rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86_64.dts (100%) rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86_64.yaml (100%) rename boards/{x86/qemu_x86/qemu_x86_64_nokpti.dts => qemu/x86/qemu_x86_64_atom_nokpti.dts} (100%) create mode 100644 boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml create mode 100644 boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86_64_defconfig (88%) rename boards/{x86/qemu_x86/qemu_x86_nokpti.dts => qemu/x86/qemu_x86_atom_nokpti.dts} (100%) create mode 100644 boards/qemu/x86/qemu_x86_atom_nokpti.yaml create mode 100644 boards/qemu/x86/qemu_x86_atom_nokpti_defconfig create mode 100644 boards/qemu/x86/qemu_x86_atom_nommu.dts create mode 100644 boards/qemu/x86/qemu_x86_atom_nommu.yaml create mode 100644 boards/qemu/x86/qemu_x86_atom_nommu_defconfig rename boards/{x86/qemu_x86/qemu_x86_nopae.dts => qemu/x86/qemu_x86_atom_nopae.dts} (100%) create mode 100644 boards/qemu/x86/qemu_x86_atom_nopae.yaml create mode 100644 boards/qemu/x86/qemu_x86_atom_nopae_defconfig rename boards/{x86/qemu_x86/qemu_x86_virt.dts => qemu/x86/qemu_x86_atom_virt.dts} (100%) create mode 100644 boards/qemu/x86/qemu_x86_atom_virt.yaml create mode 100644 boards/qemu/x86/qemu_x86_atom_virt_defconfig rename boards/{x86/qemu_x86/qemu_x86_xip.dts => qemu/x86/qemu_x86_atom_xip.dts} (100%) create mode 100644 boards/qemu/x86/qemu_x86_atom_xip.yaml create mode 100644 boards/qemu/x86/qemu_x86_atom_xip_defconfig rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86_defconfig (88%) rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86_lakemont.dts (100%) rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86_lakemont.yaml (100%) rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86_lakemont_defconfig (85%) rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86_tiny.dts (100%) rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86_tiny.ld (100%) rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86_tiny.yaml (100%) rename boards/{x86/qemu_x86 => qemu/x86}/qemu_x86_tiny_defconfig (93%) create mode 100644 boards/qemu/xtensa/Kconfig create mode 100644 boards/qemu/xtensa/Kconfig.defconfig create mode 100644 boards/qemu/xtensa/Kconfig.qemu_xtensa create mode 100644 boards/qemu/xtensa/board.cmake create mode 100644 boards/qemu/xtensa/board.yml rename boards/{xtensa/qemu_xtensa => qemu/xtensa}/doc/index.rst (100%) rename boards/{xtensa/qemu_xtensa => qemu/xtensa}/qemu_xtensa.dts (100%) rename boards/{xtensa/qemu_xtensa => qemu/xtensa}/qemu_xtensa.yaml (100%) rename boards/{xtensa/qemu_xtensa/qemu_xtensa_mmu.dts => qemu/xtensa/qemu_xtensa_dc233c_mmu.dts} (100%) create mode 100644 boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml create mode 100644 boards/qemu/xtensa/qemu_xtensa_dc233c_mmu_defconfig rename boards/{xtensa/qemu_xtensa => qemu/xtensa}/qemu_xtensa_defconfig (82%) rename boards/{arm => qorvo}/decawave_dwm1001_dev/Kconfig (100%) create mode 100644 boards/qorvo/decawave_dwm1001_dev/Kconfig.decawave_dwm1001_dev create mode 100644 boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig rename boards/{arm => qorvo}/decawave_dwm1001_dev/board.cmake (100%) create mode 100644 boards/qorvo/decawave_dwm1001_dev/board.yml rename boards/{arm => qorvo}/decawave_dwm1001_dev/decawave_dwm1001_dev-pinctrl.dtsi (100%) rename boards/{arm => qorvo}/decawave_dwm1001_dev/decawave_dwm1001_dev.dts (100%) rename boards/{arm => qorvo}/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml (100%) create mode 100644 boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig rename boards/{arm => qorvo}/decawave_dwm1001_dev/doc/index.rst (100%) rename boards/{arm/pinetime_devkit0 => qorvo/decawave_dwm1001_dev}/pre_dt_board.cmake (100%) create mode 100644 boards/qorvo/index.rst create mode 100644 boards/quicklogic/index.rst rename boards/{arm => quicklogic}/qomu/Kconfig (100%) create mode 100644 boards/quicklogic/qomu/Kconfig.qomu create mode 100644 boards/quicklogic/qomu/board.yml rename boards/{arm => quicklogic}/qomu/doc/img/qomu-board.png (100%) rename boards/{arm => quicklogic}/qomu/doc/index.rst (100%) rename boards/{arm => quicklogic}/qomu/qomu.dts (100%) rename boards/{arm => quicklogic}/qomu/qomu.yaml (100%) rename boards/{arm => quicklogic}/qomu/qomu_defconfig (88%) rename boards/{arm => quicklogic}/quick_feather/Kconfig (100%) create mode 100644 boards/quicklogic/quick_feather/Kconfig.quick_feather create mode 100644 boards/quicklogic/quick_feather/board.yml rename boards/{arm => quicklogic}/quick_feather/doc/img/feather-board.jpg (100%) create mode 100644 boards/quicklogic/quick_feather/doc/index.rst rename boards/{arm => quicklogic}/quick_feather/quick_feather.dts (100%) rename boards/{arm => quicklogic}/quick_feather/quick_feather.yaml (100%) rename boards/{arm => quicklogic}/quick_feather/quick_feather_defconfig (86%) create mode 100644 boards/rak/index.rst create mode 100644 boards/rak/rak4631/Kconfig.defconfig create mode 100644 boards/rak/rak4631/Kconfig.rak4631 rename boards/{arm/rak4631_nrf52840 => rak/rak4631}/board.cmake (100%) create mode 100644 boards/rak/rak4631/board.yml rename boards/{arm/rak4631_nrf52840 => rak/rak4631}/doc/img/rak4631-front-parts.jpg (100%) create mode 100644 boards/rak/rak4631/doc/index.rst rename boards/{arm/pinnacle_100_dvk => rak/rak4631}/pre_dt_board.cmake (100%) rename boards/{arm/rak4631_nrf52840 => rak/rak4631}/rak4631_nrf52840-pinctrl.dtsi (100%) rename boards/{arm/rak4631_nrf52840 => rak/rak4631}/rak4631_nrf52840.dts (100%) rename boards/{arm/rak4631_nrf52840 => rak/rak4631}/rak4631_nrf52840.yaml (89%) rename boards/{arm/rak4631_nrf52840 => rak/rak4631}/rak4631_nrf52840_defconfig (77%) create mode 100644 boards/rak/rak5010/Kconfig.defconfig create mode 100644 boards/rak/rak5010/Kconfig.rak5010 rename boards/{arm/rak5010_nrf52840 => rak/rak5010}/board.cmake (100%) create mode 100644 boards/rak/rak5010/board.yml rename boards/{arm/rak5010_nrf52840 => rak/rak5010}/doc/img/rak5010-front-parts.jpg (100%) create mode 100644 boards/rak/rak5010/doc/index.rst rename boards/{arm/rak4631_nrf52840 => rak/rak5010}/pre_dt_board.cmake (100%) rename boards/{arm/rak5010_nrf52840 => rak/rak5010}/rak5010_nrf52840-pinctrl.dtsi (100%) rename boards/{arm/rak5010_nrf52840 => rak/rak5010}/rak5010_nrf52840.dts (100%) rename boards/{arm/rak5010_nrf52840 => rak/rak5010}/rak5010_nrf52840.yaml (88%) rename boards/{arm/rak5010_nrf52840 => rak/rak5010}/rak5010_nrf52840_defconfig (77%) create mode 100644 boards/raspberrypi/index.rst rename boards/{arm64/mimx93_evk/board.cmake => raspberrypi/rpi_4b/CMakeLists.txt} (100%) create mode 100644 boards/raspberrypi/rpi_4b/Kconfig.defconfig create mode 100644 boards/raspberrypi/rpi_4b/Kconfig.rpi_4b rename boards/{arm64/nxp_ls1046ardb => raspberrypi/rpi_4b}/board.cmake (100%) create mode 100644 boards/raspberrypi/rpi_4b/board.yml create mode 100644 boards/raspberrypi/rpi_4b/doc/index.rst rename boards/{arm64 => raspberrypi}/rpi_4b/rpi_4b.dts (100%) rename boards/{arm64 => raspberrypi}/rpi_4b/rpi_4b.yaml (100%) rename boards/{arm64 => raspberrypi}/rpi_4b/rpi_4b_defconfig (90%) create mode 100644 boards/raspberrypi/rpi_pico/Kconfig.defconfig create mode 100644 boards/raspberrypi/rpi_pico/Kconfig.rpi_pico rename boards/{arm => raspberrypi}/rpi_pico/board.cmake (100%) create mode 100644 boards/raspberrypi/rpi_pico/board.yml rename boards/{arm => raspberrypi}/rpi_pico/doc/img/rpi_pico.jpg (100%) rename boards/{arm => raspberrypi}/rpi_pico/doc/img/rpi_pico_w.jpg (100%) rename boards/{arm => raspberrypi}/rpi_pico/doc/index.rst (100%) rename boards/{arm => raspberrypi}/rpi_pico/rpi_pico-common.dtsi (100%) rename boards/{arm => raspberrypi}/rpi_pico/rpi_pico-pinctrl.dtsi (100%) rename boards/{arm => raspberrypi}/rpi_pico/rpi_pico.dts (75%) rename boards/{arm => raspberrypi}/rpi_pico/rpi_pico.yaml (100%) rename boards/{arm => raspberrypi}/rpi_pico/rpi_pico_defconfig (78%) rename boards/{arm/rpi_pico/rpi_pico_w.dts => raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts} (100%) create mode 100644 boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml create mode 100644 boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig rename boards/{arm => raspberrypi}/rpi_pico/support/openocd.cfg (100%) create mode 100644 boards/raytac/index.rst create mode 100644 boards/raytac/mdbt50q_db_33/Kconfig create mode 100644 boards/raytac/mdbt50q_db_33/Kconfig.defconfig create mode 100644 boards/raytac/mdbt50q_db_33/Kconfig.raytac_mdbt50q_db_33 rename boards/{arm/raytac_mdbt50q_db_33_nrf52833 => raytac/mdbt50q_db_33}/board.cmake (100%) create mode 100644 boards/raytac/mdbt50q_db_33/board.yml rename boards/{arm/raytac_mdbt50q_db_33_nrf52833 => raytac/mdbt50q_db_33}/doc/img/mdbt50q_db_33.jpg (100%) create mode 100644 boards/raytac/mdbt50q_db_33/doc/index.rst rename boards/{arm/rak5010_nrf52840 => raytac/mdbt50q_db_33}/pre_dt_board.cmake (100%) rename boards/{arm/raytac_mdbt50q_db_33_nrf52833 => raytac/mdbt50q_db_33}/raytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi (100%) rename boards/{arm/raytac_mdbt50q_db_33_nrf52833 => raytac/mdbt50q_db_33}/raytac_mdbt50q_db_33_nrf52833.dts (100%) rename boards/{arm/raytac_mdbt50q_db_33_nrf52833 => raytac/mdbt50q_db_33}/raytac_mdbt50q_db_33_nrf52833.yaml (89%) rename boards/{arm/raytac_mdbt50q_db_33_nrf52833 => raytac/mdbt50q_db_33}/raytac_mdbt50q_db_33_nrf52833_defconfig (79%) create mode 100644 boards/raytac/mdbt50q_db_40/Kconfig create mode 100644 boards/raytac/mdbt50q_db_40/Kconfig.defconfig create mode 100644 boards/raytac/mdbt50q_db_40/Kconfig.raytac_mdbt50q_db_40 rename boards/{arm/raytac_mdbt50q_db_40_nrf52840 => raytac/mdbt50q_db_40}/board.cmake (100%) create mode 100644 boards/raytac/mdbt50q_db_40/board.yml rename boards/{arm/raytac_mdbt50q_db_40_nrf52840 => raytac/mdbt50q_db_40}/doc/img/mdbt50q_db_40.jpg (100%) create mode 100644 boards/raytac/mdbt50q_db_40/doc/index.rst rename boards/{arm/raytac_mdbt50q_db_33_nrf52833 => raytac/mdbt50q_db_40}/pre_dt_board.cmake (100%) rename boards/{arm/raytac_mdbt50q_db_40_nrf52840 => raytac/mdbt50q_db_40}/raytac_mdbt50q_db_40_nrf52840-pinctrl.dtsi (100%) rename boards/{arm/raytac_mdbt50q_db_40_nrf52840 => raytac/mdbt50q_db_40}/raytac_mdbt50q_db_40_nrf52840.dts (100%) rename boards/{arm/raytac_mdbt50q_db_40_nrf52840 => raytac/mdbt50q_db_40}/raytac_mdbt50q_db_40_nrf52840.yaml (90%) rename boards/{arm/raytac_mdbt50q_db_40_nrf52840 => raytac/mdbt50q_db_40}/raytac_mdbt50q_db_40_nrf52840_defconfig (79%) create mode 100644 boards/raytac/mdbt53_db_40/CMakeLists.txt create mode 100644 boards/raytac/mdbt53_db_40/Kconfig create mode 100644 boards/raytac/mdbt53_db_40/Kconfig.defconfig create mode 100644 boards/raytac/mdbt53_db_40/Kconfig.raytac_mdbt53_db_40 create mode 100644 boards/raytac/mdbt53_db_40/board.cmake create mode 100644 boards/raytac/mdbt53_db_40/board.yml rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/doc/img/MDBT53-DB-40.jpg (100%) create mode 100644 boards/raytac/mdbt53_db_40/doc/index.rst rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53_db_40}/pre_dt_board.cmake (100%) rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpuapp.dts (100%) rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml (85%) rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi (100%) rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts (100%) create mode 100644 boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts (100%) rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml (84%) create mode 100644 boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts (100%) rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpunet-pinctrl.dtsi (100%) rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpunet.dts (100%) rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpunet.yaml (87%) rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts (100%) create mode 100644 boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c (100%) rename boards/{arm64/roc_rk3568_pc/board.cmake => raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_defconfig} (100%) rename boards/{arm/raytac_mdbt53_db_40_nrf5340 => raytac/mdbt53_db_40}/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts (100%) create mode 100644 boards/raytac/mdbt53v_db_40/CMakeLists.txt create mode 100644 boards/raytac/mdbt53v_db_40/Kconfig create mode 100644 boards/raytac/mdbt53v_db_40/Kconfig.defconfig create mode 100644 boards/raytac/mdbt53v_db_40/Kconfig.raytac_mdbt53v_db_40 create mode 100644 boards/raytac/mdbt53v_db_40/board.cmake create mode 100644 boards/raytac/mdbt53v_db_40/board.yml rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/doc/img/MDBT53V-DB-40.jpg (100%) rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/doc/index.rst (100%) rename boards/{arm/thingy53_nrf5340 => raytac/mdbt53v_db_40}/pre_dt_board.cmake (100%) rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts (100%) rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml (83%) rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi (100%) rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts (100%) create mode 100644 boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts (100%) rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml (81%) create mode 100644 boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts (100%) rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi (100%) rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpunet.dts (100%) rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml (86%) rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts (100%) create mode 100644 boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c (100%) rename boards/{arm64/rpi_4b/board.cmake => raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_defconfig} (100%) rename boards/{arm/raytac_mdbt53v_db_40_nrf5340 => raytac/mdbt53v_db_40}/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts (100%) create mode 100644 boards/renesas/da14695_dk_usb/Kconfig.da14695_dk_usb rename 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boards/{arm/efr32_radio/efr32_radio_brd4255a.dts => silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.dts} (100%) create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.yaml create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig rename boards/{arm/efr32_radio/efr32_radio_brd4250b.dts => silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.dts} (100%) create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.yaml create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig rename boards/{arm/efr32_radio/efr32_radio_brd4161a.dts => silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.dts} (100%) create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.yaml create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig rename boards/{arm/efr32_radio/efr32_radio_brd4170a.dts => silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.dts} (100%) create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.yaml create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig rename boards/{arm/efr32_radio/efr32_radio_brd4180a-pinctrl.dtsi => silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32-pinctrl.dtsi} (100%) create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.dts create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.yaml create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig rename boards/{arm/efr32_radio/efr32_radio_brd4187c-pinctrl.dtsi => silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48-pinctrl.dtsi} (100%) create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.dts create mode 100644 boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.yaml create mode 100644 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silabs}/efr32xg24_dk2601b/pre_dt_board.cmake (100%) create mode 100644 boards/silabs/index.rst create mode 100644 boards/sipeed/index.rst create mode 100644 boards/sipeed/longan_nano/Kconfig.defconfig create mode 100644 boards/sipeed/longan_nano/Kconfig.longan_nano rename boards/{riscv => sipeed}/longan_nano/board.cmake (100%) create mode 100644 boards/sipeed/longan_nano/board.yml rename boards/{riscv => sipeed}/longan_nano/doc/img/longan_nano.jpg (100%) rename boards/{riscv => sipeed}/longan_nano/doc/index.rst (100%) rename boards/{riscv => sipeed}/longan_nano/longan_nano-common.dtsi (100%) rename boards/{riscv => sipeed}/longan_nano/longan_nano-pinctrl.dtsi (100%) rename boards/{riscv => sipeed}/longan_nano/longan_nano.dts (100%) rename boards/{riscv => sipeed}/longan_nano/longan_nano.yaml (100%) rename boards/{riscv => sipeed}/longan_nano/longan_nano_defconfig (78%) rename boards/{riscv/longan_nano/longan_nano_lite.dts => sipeed/longan_nano/longan_nano_gd32vf103_lite.dts} (100%) create mode 100644 boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml rename boards/{riscv => sipeed}/longan_nano/support/openocd.cfg (100%) delete mode 100644 boards/sparc/generic_leon3/Kconfig.board delete mode 100644 boards/sparc/generic_leon3/Kconfig.defconfig delete mode 100644 boards/sparc/generic_leon3/generic_leon3_defconfig delete mode 100644 boards/sparc/gr716a_mini/Kconfig.board delete mode 100644 boards/sparc/gr716a_mini/Kconfig.defconfig delete mode 100644 boards/sparc/gr716a_mini/gr716a_mini_defconfig delete mode 100644 boards/sparc/index.rst delete mode 100644 boards/sparc/qemu_leon3/Kconfig.board delete mode 100644 boards/sparc/qemu_leon3/Kconfig.defconfig create mode 100644 boards/sparkfun/index.rst create mode 100644 boards/sparkfun/nrf52_sparkfun/Kconfig.defconfig create mode 100644 boards/sparkfun/nrf52_sparkfun/Kconfig.nrf52_sparkfun rename boards/{arm => sparkfun}/nrf52_sparkfun/board.cmake (100%) create mode 100644 boards/sparkfun/nrf52_sparkfun/board.yml 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st}/nucleo_l412rb_p/support/openocd.cfg (100%) create mode 100644 boards/st/nucleo_l432kc/Kconfig.defconfig create mode 100644 boards/st/nucleo_l432kc/Kconfig.nucleo_l432kc rename boards/{arm => st}/nucleo_l432kc/board.cmake (100%) create mode 100644 boards/st/nucleo_l432kc/board.yml rename boards/{arm => st}/nucleo_l432kc/doc/img/nucleo_l432kc.jpg (100%) rename boards/{arm => st}/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.jpg (100%) create mode 100644 boards/st/nucleo_l432kc/doc/index.rst rename boards/{arm => st}/nucleo_l432kc/nucleo_l432kc.dts (100%) rename boards/{arm => st}/nucleo_l432kc/nucleo_l432kc.yaml (100%) rename boards/{arm => st}/nucleo_l432kc/nucleo_l432kc_defconfig (85%) rename boards/{arm => st}/nucleo_l432kc/support/openocd.cfg (100%) create mode 100644 boards/st/nucleo_l433rc_p/Kconfig.defconfig create mode 100644 boards/st/nucleo_l433rc_p/Kconfig.nucleo_l433rc_p rename boards/{arm => st}/nucleo_l433rc_p/arduino_r3_connector.dtsi (100%) rename boards/{arm => st}/nucleo_l433rc_p/board.cmake (100%) create mode 100644 boards/st/nucleo_l433rc_p/board.yml rename boards/{arm => st}/nucleo_l433rc_p/doc/img/nucleo_l433rc_p.jpg (100%) rename boards/{arm => st}/nucleo_l433rc_p/doc/img/nucleo_l433rc_p_pinout.jpg (100%) create mode 100644 boards/st/nucleo_l433rc_p/doc/index.rst rename boards/{arm => st}/nucleo_l433rc_p/nucleo_l433rc_p.dts (100%) rename boards/{arm => st}/nucleo_l433rc_p/nucleo_l433rc_p.yaml (100%) rename boards/{arm => st}/nucleo_l433rc_p/nucleo_l433rc_p_defconfig (85%) rename boards/{arm => st}/nucleo_l433rc_p/support/openocd.cfg (100%) create mode 100644 boards/st/nucleo_l452re/Kconfig.defconfig create mode 100644 boards/st/nucleo_l452re/Kconfig.nucleo_l452re rename boards/{arm => st}/nucleo_l452re/arduino_r3_connector.dtsi (100%) rename boards/{arm => st}/nucleo_l452re/board.cmake (100%) create mode 100644 boards/st/nucleo_l452re/board.yml rename boards/{arm => st}/nucleo_l452re/doc/img/nucleo_l452re_p.jpg (100%) rename boards/{arm => st}/nucleo_l452re/doc/img/nucleo_l452re_p_pinout.jpg (100%) rename boards/{arm => st}/nucleo_l452re/doc/img/nucleo_l452re_pinout.jpg (100%) create mode 100644 boards/st/nucleo_l452re/doc/index.rst rename boards/{arm => st}/nucleo_l452re/nucleo_l452re.dts (100%) rename boards/{arm => st}/nucleo_l452re/nucleo_l452re.yaml (100%) rename boards/{arm => st}/nucleo_l452re/nucleo_l452re_common.dtsi (100%) rename boards/{arm => st}/nucleo_l452re/nucleo_l452re_defconfig (85%) rename boards/{arm/nucleo_l452re/nucleo_l452re_p.dts => st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.dts} (100%) create mode 100644 boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml create mode 100644 boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig rename boards/{arm => st}/nucleo_l452re/st_morpho_connector.dtsi (100%) rename boards/{arm => st}/nucleo_l452re/support/openocd.cfg (100%) create mode 100644 boards/st/nucleo_l476rg/Kconfig.defconfig create mode 100644 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st}/nucleo_l552ze_q/nucleo_l552ze_q.yaml (100%) rename boards/{arm => st}/nucleo_l552ze_q/nucleo_l552ze_q_defconfig (85%) rename boards/{arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.dts => st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.dts} (100%) create mode 100644 boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.yaml create mode 100644 boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig rename boards/{arm => st}/nucleo_l552ze_q/support/openocd.cfg (100%) rename boards/{arm => st}/nucleo_u575zi_q/CMakeLists.txt (100%) create mode 100644 boards/st/nucleo_u575zi_q/Kconfig.nucleo_u575zi_q rename boards/{arm => st}/nucleo_u575zi_q/arduino_r3_connector.dtsi (100%) rename boards/{arm => st}/nucleo_u575zi_q/board.cmake (100%) create mode 100644 boards/st/nucleo_u575zi_q/board.yml create mode 100644 boards/st/nucleo_u575zi_q/doc/index.rst rename boards/{arm => st}/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi (100%) rename boards/{arm => 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(100%) create mode 100644 boards/st/nucleo_wb55rg/Kconfig.defconfig create mode 100644 boards/st/nucleo_wb55rg/Kconfig.nucleo_wb55rg rename boards/{arm => st}/nucleo_wb55rg/arduino_r3_connector.dtsi (100%) rename boards/{arm => st}/nucleo_wb55rg/board.cmake (100%) create mode 100644 boards/st/nucleo_wb55rg/board.yml rename boards/{arm => st}/nucleo_wb55rg/doc/img/nucleowb55rg.jpg (100%) rename boards/{arm => st}/nucleo_wb55rg/doc/nucleo_wb55rg.rst (99%) rename boards/{arm => st}/nucleo_wb55rg/nucleo_wb55rg.dts (100%) rename boards/{arm => st}/nucleo_wb55rg/nucleo_wb55rg.yaml (100%) rename boards/{arm => st}/nucleo_wb55rg/nucleo_wb55rg_defconfig (83%) rename boards/{arm => st}/nucleo_wb55rg/support/openocd.cfg (100%) create mode 100644 boards/st/nucleo_wba52cg/Kconfig.defconfig create mode 100644 boards/st/nucleo_wba52cg/Kconfig.nucleo_wba52cg rename boards/{arm => st}/nucleo_wba52cg/arduino_r3_connector.dtsi (100%) rename boards/{arm => st}/nucleo_wba52cg/board.cmake (100%) create mode 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=> st}/steval_fcu001v1/support/openocd.cfg (100%) create mode 100644 boards/st/stm3210c_eval/Kconfig.stm3210c_eval rename boards/{arm => st}/stm3210c_eval/board.cmake (100%) create mode 100644 boards/st/stm3210c_eval/board.yml rename boards/{arm => st}/stm3210c_eval/doc/img/stm3210c_eval.jpg (100%) rename boards/{arm => st}/stm3210c_eval/doc/img/stm3210c_eval_connectors.jpg (100%) create mode 100644 boards/st/stm3210c_eval/doc/index.rst rename boards/{arm => st}/stm3210c_eval/stm3210c_eval.dts (100%) rename boards/{arm => st}/stm3210c_eval/stm3210c_eval.yaml (100%) create mode 100644 boards/st/stm3210c_eval/stm3210c_eval_defconfig rename boards/{arm => st}/stm3210c_eval/support/openocd.cfg (100%) create mode 100644 boards/st/stm32373c_eval/Kconfig.stm32373c_eval rename boards/{arm => st}/stm32373c_eval/board.cmake (100%) create mode 100644 boards/st/stm32373c_eval/board.yml rename boards/{arm => st}/stm32373c_eval/doc/img/stm32373c_eval.jpg (100%) rename boards/{arm => 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rename boards/{arm => st}/stm32l1_disco/stm32l1_disco.yaml (100%) rename boards/{arm => st}/stm32l1_disco/stm32l1_disco_defconfig (81%) rename boards/{arm => st}/stm32l1_disco/support/openocd.cfg (100%) create mode 100644 boards/st/stm32l476g_disco/Kconfig.stm32l476g_disco rename boards/{arm => st}/stm32l476g_disco/board.cmake (100%) create mode 100644 boards/st/stm32l476g_disco/board.yml rename boards/{arm => st}/stm32l476g_disco/doc/img/stm32l476g_disco.jpg (100%) create mode 100644 boards/st/stm32l476g_disco/doc/index.rst rename boards/{arm => st}/stm32l476g_disco/stm32l476g_disco.dts (100%) rename boards/{arm => st}/stm32l476g_disco/stm32l476g_disco.yaml (100%) rename boards/{arm => st}/stm32l476g_disco/stm32l476g_disco_defconfig (85%) rename boards/{arm => st}/stm32l476g_disco/support/openocd.cfg (100%) rename boards/{arm => st}/stm32l496g_disco/CMakeLists.txt (100%) create mode 100644 boards/st/stm32l496g_disco/Kconfig.defconfig create mode 100644 boards/st/stm32l496g_disco/Kconfig.stm32l496g_disco rename boards/{arm => st}/stm32l496g_disco/arduino_r3_connector.dtsi (100%) rename boards/{arm => st}/stm32l496g_disco/board.cmake (100%) create mode 100644 boards/st/stm32l496g_disco/board.yml rename boards/{arm => st}/stm32l496g_disco/board_adc_vref.c (100%) rename boards/{arm => st}/stm32l496g_disco/doc/img/stm32l496g_disco.jpg (100%) create mode 100644 boards/st/stm32l496g_disco/doc/index.rst rename boards/{arm => st}/stm32l496g_disco/stm32l496g_disco.dts (100%) rename boards/{arm => st}/stm32l496g_disco/stm32l496g_disco.yaml (100%) rename boards/{arm => st}/stm32l496g_disco/stm32l496g_disco_defconfig (85%) rename boards/{arm => st}/stm32l496g_disco/support/openocd.cfg (100%) create mode 100644 boards/st/stm32l4r9i_disco/Kconfig.stm32l4r9i_disco rename boards/{arm => st}/stm32l4r9i_disco/arduino_r3_connector.dtsi (100%) rename boards/{arm => st}/stm32l4r9i_disco/board.cmake (100%) create mode 100644 boards/st/stm32l4r9i_disco/board.yml rename boards/{arm => st}/stm32l4r9i_disco/doc/img/stm32l4r9i_disco.jpg (100%) create mode 100644 boards/st/stm32l4r9i_disco/doc/index.rst rename boards/{arm => st}/stm32l4r9i_disco/stm32l4r9i_disco.dts (100%) rename boards/{arm => st}/stm32l4r9i_disco/stm32l4r9i_disco.yaml (100%) rename boards/{arm => st}/stm32l4r9i_disco/stm32l4r9i_disco_defconfig (85%) rename boards/{arm => st}/stm32l4r9i_disco/support/openocd.cfg (100%) rename boards/{arm => st}/stm32l562e_dk/CMakeLists.txt (100%) create mode 100644 boards/st/stm32l562e_dk/Kconfig.defconfig create mode 100644 boards/st/stm32l562e_dk/Kconfig.stm32l562e_dk rename boards/{arm => st}/stm32l562e_dk/arduino_r3_connector.dtsi (100%) rename boards/{arm => st}/stm32l562e_dk/board.cmake (100%) create mode 100644 boards/st/stm32l562e_dk/board.yml rename boards/{arm => st}/stm32l562e_dk/doc/img/stm32l562e_dk.jpg (100%) create mode 100644 boards/st/stm32l562e_dk/doc/index.rst rename boards/{arm => st}/stm32l562e_dk/stm32l562e_dk.dts (100%) rename boards/{arm => st}/stm32l562e_dk/stm32l562e_dk.yaml (100%) rename boards/{arm => st}/stm32l562e_dk/stm32l562e_dk_common.dtsi (100%) rename boards/{arm => st}/stm32l562e_dk/stm32l562e_dk_defconfig (85%) rename boards/{arm/stm32l562e_dk/stm32l562e_dk_ns.dts => st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.dts} (100%) create mode 100644 boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.yaml create mode 100644 boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig rename boards/{arm => st}/stm32l562e_dk/support/openocd.cfg (100%) create mode 100644 boards/st/stm32mp157c_dk2/Kconfig.defconfig create mode 100644 boards/st/stm32mp157c_dk2/Kconfig.stm32mp157c_dk2 rename boards/{arm => st}/stm32mp157c_dk2/arduino_r3_connector.dtsi (100%) rename boards/{arm => st}/stm32mp157c_dk2/board.cmake (100%) create mode 100644 boards/st/stm32mp157c_dk2/board.yml rename boards/{arm => st}/stm32mp157c_dk2/doc/img/en.stm32mp157c-dk2.jpg (100%) rename boards/{arm => st}/stm32mp157c_dk2/doc/stm32mp157_dk2.rst (98%) rename boards/{arm => st}/stm32mp157c_dk2/stm32mp157c_dk2.dts (100%) rename boards/{arm => st}/stm32mp157c_dk2/stm32mp157c_dk2.yaml (100%) rename boards/{arm => st}/stm32mp157c_dk2/stm32mp157c_dk2_defconfig (89%) rename boards/{arm => st}/stm32mp157c_dk2/support/openocd.cfg (100%) create mode 100644 boards/st/stm32u5a9j_dk/Kconfig.stm32u5a9j_dk rename boards/{arm => st}/stm32u5a9j_dk/board.cmake (100%) create mode 100644 boards/st/stm32u5a9j_dk/board.yml rename boards/{arm => st}/stm32u5a9j_dk/doc/img/bottom_view.jpg (100%) rename boards/{arm => st}/stm32u5a9j_dk/doc/img/top_view.jpg (100%) create mode 100644 boards/st/stm32u5a9j_dk/doc/index.rst rename boards/{arm => st}/stm32u5a9j_dk/stm32u5a9j_dk.dts (100%) rename boards/{arm => st}/stm32u5a9j_dk/stm32u5a9j_dk.yaml (100%) rename boards/{arm => st}/stm32u5a9j_dk/stm32u5a9j_dk_defconfig (80%) rename boards/{arm => st}/stm32u5a9j_dk/support/openocd.cfg (100%) create mode 100644 boards/st/stm32vl_disco/Kconfig.stm32vl_disco rename boards/{arm => st}/stm32vl_disco/board.cmake (100%) create mode 100644 boards/st/stm32vl_disco/board.yml rename boards/{arm => st}/stm32vl_disco/doc/img/stm32vl_disco.jpg (100%) create mode 100644 boards/st/stm32vl_disco/doc/index.rst rename boards/{arm => st}/stm32vl_disco/stm32vl_disco.dts (100%) rename boards/{arm => st}/stm32vl_disco/stm32vl_disco.yaml (100%) rename boards/{arm => st}/stm32vl_disco/stm32vl_disco_defconfig (80%) rename boards/{arm => st}/stm32vl_disco/support/openocd.cfg (100%) create mode 100644 boards/st/stm32wb5mm_dk/Kconfig.defconfig create mode 100644 boards/st/stm32wb5mm_dk/Kconfig.stm32wb5mm_dk rename boards/{arm => st}/stm32wb5mm_dk/board.cmake (100%) create mode 100644 boards/st/stm32wb5mm_dk/board.yml rename boards/{arm => st}/stm32wb5mm_dk/doc/img/STM32WB5MM_DK.jpg (100%) rename boards/{arm => st}/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst (99%) rename boards/{arm => st}/stm32wb5mm_dk/stm32wb5mm_dk.dts (100%) rename boards/{arm => st}/stm32wb5mm_dk/stm32wb5mm_dk.yaml (100%) rename boards/{arm => st}/stm32wb5mm_dk/stm32wb5mm_dk_defconfig (83%) rename boards/{arm => st}/stm32wb5mm_dk/support/openocd.cfg (100%) create mode 100644 boards/st/stm32wb5mmg/Kconfig.defconfig create mode 100644 boards/st/stm32wb5mmg/Kconfig.stm32wb5mmg rename boards/{arm => st}/stm32wb5mmg/board.cmake (100%) create mode 100644 boards/st/stm32wb5mmg/board.yml rename boards/{arm => st}/stm32wb5mmg/doc/img/STM32WB5MMG.jpg (100%) rename boards/{arm => st}/stm32wb5mmg/doc/stm32wb5mmg.rst (99%) rename boards/{arm => st}/stm32wb5mmg/stm32wb5mmg.dts (100%) rename boards/{arm => st}/stm32wb5mmg/stm32wb5mmg.yaml (100%) rename boards/{arm => st}/stm32wb5mmg/stm32wb5mmg_defconfig (83%) rename boards/{arm => st}/stm32wb5mmg/support/openocd.cfg (100%) create mode 100644 boards/synopsys/em_starterkit/CMakeLists.txt create mode 100644 boards/synopsys/em_starterkit/Kconfig.defconfig create mode 100644 boards/synopsys/em_starterkit/Kconfig.em_starterkit rename boards/{arc => synopsys}/em_starterkit/arc_mpu_regions.c (100%) create mode 100644 boards/synopsys/em_starterkit/board.cmake create mode 100644 boards/synopsys/em_starterkit/board.dtsi create mode 100644 boards/synopsys/em_starterkit/board.yml rename boards/{arc => synopsys}/em_starterkit/doc/em_starterkit.jpg (100%) create mode 100644 boards/synopsys/em_starterkit/doc/index.rst create mode 100644 boards/synopsys/em_starterkit/em_starterkit_defconfig create mode 100644 boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.dts create mode 100644 boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.yaml create mode 100644 boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.dts create mode 100644 boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.yaml rename boards/{arc/em_starterkit/em_starterkit_em7d_v22.dts => synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.overlay} (100%) create mode 100644 boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.yaml rename boards/{arc/em_starterkit/em_starterkit_em7d.dts => synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3.overlay} (100%) create mode 100644 boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig create mode 100644 boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_defconfig create mode 100644 boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.dts create mode 100644 boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.yaml rename boards/{arc => synopsys}/em_starterkit/em_starterkit_r22.dtsi (100%) rename boards/{arc => synopsys}/em_starterkit/em_starterkit_r23.dtsi (96%) rename boards/{arc => synopsys}/em_starterkit/pmodmux.c (100%) rename boards/{arc => synopsys}/em_starterkit/support/openocd.cfg (100%) rename boards/{arc => synopsys}/emsdp/CMakeLists.txt (100%) create mode 100644 boards/synopsys/emsdp/Kconfig.defconfig create mode 100644 boards/synopsys/emsdp/Kconfig.emsdp rename boards/{arc => synopsys}/emsdp/arc_mpu_regions.c (100%) rename boards/{arc/em_starterkit => synopsys/emsdp}/board.cmake (100%) rename boards/{arc => synopsys}/emsdp/board.dtsi (100%) create mode 100644 boards/synopsys/emsdp/board.yml rename boards/{arc => synopsys}/emsdp/doc/emsdp.jpg (100%) create mode 100644 boards/synopsys/emsdp/doc/index.rst rename boards/{arc => synopsys}/emsdp/emsdp-pinctrl.dtsi (100%) rename boards/{arc => synopsys}/emsdp/emsdp_defconfig (76%) rename boards/{arc/emsdp/emsdp.dts => synopsys/emsdp/emsdp_emsdp_em11d.dts} (100%) create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em11d.yaml create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em11d_defconfig rename boards/{arc/emsdp/emsdp_em4.dts => synopsys/emsdp/emsdp_emsdp_em4.dts} (100%) create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em4.yaml rename boards/{arc/emsdp/emsdp_em5d.dts => synopsys/emsdp/emsdp_emsdp_em5d.dts} (100%) create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em5d.yaml create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em5d_defconfig rename boards/{arc/emsdp/emsdp_em6.dts => synopsys/emsdp/emsdp_emsdp_em6.dts} (100%) create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em6.yaml create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em6_defconfig rename boards/{arc/emsdp/emsdp_em7d.dts => synopsys/emsdp/emsdp_emsdp_em7d.dts} (100%) create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em7d.yaml rename boards/{arc/emsdp/emsdp_em7d_esp.dts => synopsys/emsdp/emsdp_emsdp_em7d_esp.dts} (100%) create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em7d_esp.yaml create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em7d_esp_defconfig rename boards/{arc/emsdp/emsdp_em9d.dts => synopsys/emsdp/emsdp_emsdp_em9d.dts} (100%) create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em9d.yaml create mode 100644 boards/synopsys/emsdp/emsdp_emsdp_em9d_defconfig rename boards/{arc => synopsys}/emsdp/platform.c (100%) rename boards/{arc => synopsys}/emsdp/support/openocd.cfg (100%) rename boards/{arc => synopsys}/hsdk/CMakeLists.txt (100%) create mode 100644 boards/synopsys/hsdk/Kconfig.defconfig create mode 100644 boards/synopsys/hsdk/Kconfig.hsdk create mode 100644 boards/synopsys/hsdk/board.cmake create mode 100644 boards/synopsys/hsdk/board.yml rename boards/{arc => synopsys}/hsdk/doc/arduino_shield_interface.jpg (100%) rename boards/{arc => synopsys}/hsdk/doc/hsdk.jpg (100%) rename boards/{arc => synopsys}/hsdk/doc/index.rst (100%) rename boards/{arc => synopsys}/hsdk/doc/mikrobus_header.jpg (100%) rename boards/{arc => synopsys}/hsdk/doc/pinout_diagram_of_the_pmod.jpg (100%) rename boards/{arc => synopsys}/hsdk/hsdk.dts (100%) rename boards/{arc => synopsys}/hsdk/hsdk.dtsi (100%) rename boards/{arc => synopsys}/hsdk/hsdk.yaml (100%) rename boards/{arc/hsdk/hsdk_2cores.dts => synopsys/hsdk/hsdk_arc_hsdk_2cores.dts} (100%) create mode 100644 boards/synopsys/hsdk/hsdk_arc_hsdk_2cores.yaml create mode 100644 boards/synopsys/hsdk/hsdk_arc_hsdk_2cores_defconfig rename boards/{arc => synopsys}/hsdk/hsdk_defconfig (87%) rename boards/{arc => synopsys}/hsdk/platform.c (100%) rename boards/{arc => synopsys}/hsdk/support/openocd-2-cores.cfg (100%) rename boards/{arc => synopsys}/hsdk/support/openocd.cfg (100%) rename boards/{arc => synopsys}/hsdk4xd/CMakeLists.txt (100%) create mode 100644 boards/synopsys/hsdk4xd/Kconfig.hsdk4xd create mode 100644 boards/synopsys/hsdk4xd/board.cmake create mode 100644 boards/synopsys/hsdk4xd/board.yml rename boards/{arc => synopsys}/hsdk4xd/doc/arduino_shield_interface.jpg (100%) rename boards/{arc => synopsys}/hsdk4xd/doc/hsdk4xd.jpg (100%) create mode 100644 boards/synopsys/hsdk4xd/doc/index.rst rename boards/{arc => synopsys}/hsdk4xd/doc/mikrobus_header.jpg (100%) rename boards/{arc => synopsys}/hsdk4xd/doc/pinout_diagram_of_the_pmod.jpg (100%) create mode 100644 boards/synopsys/hsdk4xd/hsdk4xd.dts rename boards/{arc => synopsys}/hsdk4xd/hsdk4xd.yaml (100%) rename boards/{arc => synopsys}/hsdk4xd/hsdk4xd_defconfig (86%) rename boards/{arc => synopsys}/hsdk4xd/support/openocd.cfg (100%) create mode 100644 boards/synopsys/index.rst rename boards/{arc/qemu_arc => synopsys/iotdk}/CMakeLists.txt (100%) create mode 100644 boards/synopsys/iotdk/Kconfig.iotdk rename boards/{arc => synopsys}/iotdk/arc_mpu_regions.c (100%) rename boards/{arc/emsdp => synopsys/iotdk}/board.cmake (100%) create mode 100644 boards/synopsys/iotdk/board.yml rename boards/{arc => synopsys}/iotdk/doc/index.rst (100%) rename boards/{arc => synopsys}/iotdk/doc/iotdk.jpg (100%) rename boards/{arc => synopsys}/iotdk/iotdk.dts (96%) rename boards/{arc => synopsys}/iotdk/iotdk.yaml (100%) rename boards/{arc => synopsys}/iotdk/iotdk_defconfig (86%) rename boards/{arc => synopsys}/iotdk/support/openocd.cfg (100%) rename boards/{arc => synopsys}/nsim/CMakeLists.txt (100%) create mode 100644 boards/synopsys/nsim/Kconfig create mode 100644 boards/synopsys/nsim/Kconfig.nsim rename boards/{arc => synopsys}/nsim/arc_mpu_regions.c (100%) rename boards/{arc => synopsys}/nsim/board.cmake (100%) create mode 100644 boards/synopsys/nsim/board.yml create mode 100644 boards/synopsys/nsim/doc/index.rst rename boards/{arc => synopsys}/nsim/haps_arcv3_init.c (100%) rename boards/{arc => synopsys}/nsim/nsim-ccm-mem.dtsi (100%) rename boards/{arc => synopsys}/nsim/nsim-flash-sram-mem.dtsi (100%) rename boards/{arc => synopsys}/nsim/nsim-flat-mem.dtsi (100%) rename boards/{arc => synopsys}/nsim/nsim-smp.dtsi (100%) rename boards/{arc => synopsys}/nsim/nsim-uart-hostlink.dtsi (100%) rename boards/{arc => synopsys}/nsim/nsim-uart-ns16550.dtsi (100%) rename boards/{arc => synopsys}/nsim/nsim.dtsi (100%) rename boards/{arc => synopsys}/nsim/nsim_em-sec.dtsi (100%) rename boards/{arc => synopsys}/nsim/nsim_em.dtsi (100%) rename boards/{arc/nsim/nsim_em.dts => synopsys/nsim/nsim_nsim_em.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_em.yaml rename boards/{arc/nsim/nsim_em11d.dts => synopsys/nsim/nsim_nsim_em11d.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_em11d.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_em11d_defconfig rename boards/{arc/nsim/nsim_em7d_v22.dts => synopsys/nsim/nsim_nsim_em7d_v22.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_em7d_v22.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_em7d_v22_defconfig create mode 100644 boards/synopsys/nsim/nsim_nsim_em_defconfig rename boards/{arc/nsim/nsim_hs.dts => synopsys/nsim/nsim_nsim_hs.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs.yaml rename boards/{arc/nsim/nsim_hs5x.dts => synopsys/nsim/nsim_nsim_hs5x.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs5x.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_hs5x_defconfig rename boards/{arc/nsim/nsim_hs5x_smp.dts => synopsys/nsim/nsim_nsim_hs5x_smp.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs5x_smp.yaml rename boards/{arc/nsim/nsim_hs5x_smp_12cores.dts => synopsys/nsim/nsim_nsim_hs5x_smp_12cores.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores_defconfig create mode 100644 boards/synopsys/nsim/nsim_nsim_hs5x_smp_defconfig rename boards/{arc/nsim/nsim_hs6x.dts => synopsys/nsim/nsim_nsim_hs6x.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs6x.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_hs6x_defconfig rename boards/{arc/nsim/nsim_hs6x_smp.dts => synopsys/nsim/nsim_nsim_hs6x_smp.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs6x_smp.yaml rename boards/{arc/nsim/nsim_hs6x_smp_12cores.dts => synopsys/nsim/nsim_nsim_hs6x_smp_12cores.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores_defconfig create mode 100644 boards/synopsys/nsim/nsim_nsim_hs6x_smp_defconfig create mode 100644 boards/synopsys/nsim/nsim_nsim_hs_defconfig rename boards/{arc/nsim/nsim_hs_flash_xip.dts => synopsys/nsim/nsim_nsim_hs_flash_xip.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs_flash_xip.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_hs_flash_xip_defconfig rename boards/{arc/nsim/nsim_hs3x_hostlink.dts => synopsys/nsim/nsim_nsim_hs_hostlink.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs_hostlink.yaml rename boards/{arc/nsim/nsim_hs_mpuv6.dts => synopsys/nsim/nsim_nsim_hs_mpuv6.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs_mpuv6.yaml rename boards/{arc/nsim/nsim_hs_smp.dts => synopsys/nsim/nsim_nsim_hs_smp.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs_smp.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_hs_smp_defconfig rename boards/{arc/nsim/nsim_hs_sram.dts => synopsys/nsim/nsim_nsim_hs_sram.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_hs_sram.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_hs_sram_defconfig rename boards/{arc/nsim/nsim_sem.dts => synopsys/nsim/nsim_nsim_sem.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_sem.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_sem_defconfig rename boards/{arc/nsim/nsim_sem_mpu_stack_guard.dts => synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig rename boards/{arc/nsim/nsim_vpx5.dts => synopsys/nsim/nsim_nsim_vpx5.dts} (100%) create mode 100644 boards/synopsys/nsim/nsim_nsim_vpx5.yaml create mode 100644 boards/synopsys/nsim/nsim_nsim_vpx5_defconfig rename boards/{arc => synopsys}/nsim/support/mdb_em.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_em11d.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_em7d_v22.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs3x_hostlink.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs5x.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs5x_smp.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs5x_smp_12cores.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs6x.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs6x_smp.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs6x_smp_12cores.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs_flash_xip.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs_mpuv6.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs_smp.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_hs_sram.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_sem.args (100%) rename boards/{arc => synopsys}/nsim/support/mdb_vpx5.args (100%) rename boards/{arc => synopsys}/nsim/support/nsim_em.props (100%) rename boards/{arc => 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(100%) rename boards/{arm => ti}/cc1352r1_launchxl/support/openocd.cfg (100%) create mode 100644 boards/ti/cc1352r_sensortag/Kconfig.cc1352r_sensortag create mode 100644 boards/ti/cc1352r_sensortag/Kconfig.defconfig rename boards/{arm => ti}/cc1352r_sensortag/board.cmake (100%) create mode 100644 boards/ti/cc1352r_sensortag/board.yml rename boards/{arm => ti}/cc1352r_sensortag/cc1352r_sensortag-pinctrl.dtsi (100%) rename boards/{arm => ti}/cc1352r_sensortag/cc1352r_sensortag.dts (100%) rename boards/{arm => ti}/cc1352r_sensortag/cc1352r_sensortag.yaml (100%) rename boards/{arm => ti}/cc1352r_sensortag/cc1352r_sensortag_defconfig (84%) rename boards/{arm => ti}/cc1352r_sensortag/doc/img/cc1352r_sensortag.jpg (100%) rename boards/{arm => ti}/cc1352r_sensortag/doc/img/launchpad-lpstk-debug.jpg (100%) rename boards/{arm => ti}/cc1352r_sensortag/doc/index.rst (100%) rename boards/{arm => ti}/cc1352r_sensortag/support/openocd.cfg (100%) create mode 100644 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100644 boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig rename boards/{arm => ti}/msp_exp432p401r_launchxl/support/openocd.cfg (100%) create mode 100644 boards/ti/sk_am62/Kconfig.sk_am62 create mode 100644 boards/ti/sk_am62/board.yml rename boards/{arm/am62x_m4 => ti/sk_am62}/doc/img/sk_am62_angled.webp (100%) create mode 100644 boards/ti/sk_am62/doc/index.rst rename boards/{arm/am62x_m4/am62x_m4_sk.dts => ti/sk_am62/sk_am62_am6234_m4.dts} (100%) create mode 100644 boards/ti/sk_am62/sk_am62_am6234_m4.yaml create mode 100644 boards/ti/sk_am62/sk_am62_am6234_m4_defconfig create mode 100644 boards/toradex/colibri_imx7d/Kconfig.colibri_imx7d create mode 100644 boards/toradex/colibri_imx7d/Kconfig.defconfig create mode 100644 boards/toradex/colibri_imx7d/board.yml rename boards/{arm/colibri_imx7d_m4/colibri_imx7d_m4-pinctrl.dtsi => toradex/colibri_imx7d/colibri_imx7d-pinctrl.dtsi} (100%) create mode 100644 boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.dts create mode 100644 boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml create mode 100644 boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig rename boards/{arm/colibri_imx7d_m4/doc/colibri_imx7d_m4.jpg => toradex/colibri_imx7d/doc/colibri_imx7d.jpg} (100%) create mode 100644 boards/toradex/colibri_imx7d/doc/index.rst create mode 100644 boards/toradex/index.rst create mode 100644 boards/toradex/verdin_imx8mp/Kconfig.defconfig create mode 100644 boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp rename boards/{arm/verdin_imx8mp_m7 => toradex/verdin_imx8mp}/board.cmake (100%) create mode 100644 boards/toradex/verdin_imx8mp/board.yml create mode 100644 boards/toradex/verdin_imx8mp/doc/index.rst rename boards/{arm/verdin_imx8mp_m7 => toradex/verdin_imx8mp}/doc/verdin_imx8mp_front.jpg (100%) rename boards/{arm/verdin_imx8mp_m7/verdin_imx8mp_m7-pinctrl.dtsi => toradex/verdin_imx8mp/verdin_imx8mp-pinctrl.dtsi} (100%) create mode 100644 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rename boards/{arm/ubx_bmd340eval_nrf52840 => u-blox/ubx_bmd340eval}/board.cmake (100%) create mode 100644 boards/u-blox/ubx_bmd340eval/board.yml rename boards/{arm/ubx_bmd340eval_nrf52840 => u-blox/ubx_bmd340eval}/doc/img/BMD-34-38-EVAL.jpg (100%) rename boards/{arm/ubx_bmd340eval_nrf52840 => u-blox/ubx_bmd340eval}/doc/img/bmd-340-eval_pin_out.jpg (100%) create mode 100644 boards/u-blox/ubx_bmd340eval/doc/index.rst rename boards/{arm/ubx_bmd330eval_nrf52810 => u-blox/ubx_bmd340eval}/pre_dt_board.cmake (100%) rename boards/{arm/ubx_bmd340eval_nrf52840 => u-blox/ubx_bmd340eval}/ubx_bmd340eval_nrf52840-pinctrl.dtsi (100%) rename boards/{arm/ubx_bmd340eval_nrf52840 => u-blox/ubx_bmd340eval}/ubx_bmd340eval_nrf52840.dts (100%) rename boards/{arm/ubx_bmd340eval_nrf52840 => u-blox/ubx_bmd340eval}/ubx_bmd340eval_nrf52840.yaml (90%) rename boards/{arm/ubx_bmd340eval_nrf52840 => u-blox/ubx_bmd340eval}/ubx_bmd340eval_nrf52840_defconfig (79%) create mode 100644 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boards/{arm/ubx_bmd345eval_nrf52840 => u-blox/ubx_bmd345eval}/ubx_bmd345eval_nrf52840_defconfig (79%) create mode 100644 boards/u-blox/ubx_bmd360eval/Kconfig create mode 100644 boards/u-blox/ubx_bmd360eval/Kconfig.defconfig create mode 100644 boards/u-blox/ubx_bmd360eval/Kconfig.ubx_bmd360eval rename boards/{arm/ubx_bmd360eval_nrf52811 => u-blox/ubx_bmd360eval}/board.cmake (100%) create mode 100644 boards/u-blox/ubx_bmd360eval/board.yml rename boards/{arm/ubx_bmd360eval_nrf52811 => u-blox/ubx_bmd360eval}/doc/img/BMD-30-33-35-36-EVAL.jpg (100%) rename boards/{arm/ubx_bmd360eval_nrf52811 => u-blox/ubx_bmd360eval}/doc/img/bmd-300-eval_pin_out.jpg (100%) create mode 100644 boards/u-blox/ubx_bmd360eval/doc/index.rst rename boards/{arm/ubx_bmd345eval_nrf52840 => u-blox/ubx_bmd360eval}/pre_dt_board.cmake (100%) rename boards/{arm/ubx_bmd360eval_nrf52811 => u-blox/ubx_bmd360eval}/ubx_bmd360eval_nrf52811-pinctrl.dtsi (100%) rename boards/{arm/ubx_bmd360eval_nrf52811 => u-blox/ubx_bmd360eval}/ubx_bmd360eval_nrf52811.dts (100%) rename boards/{arm/ubx_bmd360eval_nrf52811 => u-blox/ubx_bmd360eval}/ubx_bmd360eval_nrf52811.yaml (88%) rename boards/{arm/ubx_bmd360eval_nrf52811 => u-blox/ubx_bmd360eval}/ubx_bmd360eval_nrf52811_defconfig (79%) create mode 100644 boards/u-blox/ubx_bmd380eval/Kconfig create mode 100644 boards/u-blox/ubx_bmd380eval/Kconfig.defconfig create mode 100644 boards/u-blox/ubx_bmd380eval/Kconfig.ubx_bmd380eval rename boards/{arm/ubx_bmd380eval_nrf52840 => u-blox/ubx_bmd380eval}/board.cmake (100%) create mode 100644 boards/u-blox/ubx_bmd380eval/board.yml rename boards/{arm/ubx_bmd380eval_nrf52840 => u-blox/ubx_bmd380eval}/doc/img/BMD-34-38-EVAL.jpg (100%) rename boards/{arm/ubx_bmd380eval_nrf52840 => u-blox/ubx_bmd380eval}/doc/img/bmd-340-eval_pin_out.jpg (100%) create mode 100644 boards/u-blox/ubx_bmd380eval/doc/index.rst rename boards/{arm/ubx_bmd360eval_nrf52811 => u-blox/ubx_bmd380eval}/pre_dt_board.cmake (100%) rename boards/{arm/ubx_bmd380eval_nrf52840 => u-blox/ubx_bmd380eval}/ubx_bmd380eval_nrf52840-pinctrl.dtsi (100%) rename boards/{arm/ubx_bmd380eval_nrf52840 => u-blox/ubx_bmd380eval}/ubx_bmd380eval_nrf52840.dts (100%) rename boards/{arm/ubx_bmd380eval_nrf52840 => u-blox/ubx_bmd380eval}/ubx_bmd380eval_nrf52840.yaml (88%) rename boards/{arm/ubx_bmd380eval_nrf52840 => u-blox/ubx_bmd380eval}/ubx_bmd380eval_nrf52840_defconfig (82%) create mode 100644 boards/u-blox/ubx_evkannab1/Kconfig create mode 100644 boards/u-blox/ubx_evkannab1/Kconfig.defconfig create mode 100644 boards/u-blox/ubx_evkannab1/Kconfig.ubx_evkannab1 rename boards/{arm/ubx_evkannab1_nrf52832 => u-blox/ubx_evkannab1}/board.cmake (100%) create mode 100644 boards/u-blox/ubx_evkannab1/board.yml rename boards/{arm/ubx_evkannab1_nrf52832 => u-blox/ubx_evkannab1}/doc/img/EVK-ANNA-B112.jpg (100%) create mode 100644 boards/u-blox/ubx_evkannab1/doc/index.rst rename boards/{arm/ubx_bmd380eval_nrf52840 => u-blox/ubx_evkannab1}/pre_dt_board.cmake (100%) rename boards/{arm/ubx_evkannab1_nrf52832 => u-blox/ubx_evkannab1}/ubx_evkannab1_nrf52832-pinctrl.dtsi (100%) rename boards/{arm/ubx_evkannab1_nrf52832 => u-blox/ubx_evkannab1}/ubx_evkannab1_nrf52832.dts (100%) rename boards/{arm/ubx_evkannab1_nrf52832 => u-blox/ubx_evkannab1}/ubx_evkannab1_nrf52832.yaml (88%) rename boards/{arm/ubx_evkannab1_nrf52832 => u-blox/ubx_evkannab1}/ubx_evkannab1_nrf52832_defconfig (79%) create mode 100644 boards/u-blox/ubx_evkninab1/Kconfig create mode 100644 boards/u-blox/ubx_evkninab1/Kconfig.defconfig create mode 100644 boards/u-blox/ubx_evkninab1/Kconfig.ubx_evkninab1 rename boards/{arm/ubx_evkninab1_nrf52832 => u-blox/ubx_evkninab1}/board.cmake (100%) create mode 100644 boards/u-blox/ubx_evkninab1/board.yml rename boards/{arm/ubx_evkninab1_nrf52832 => u-blox/ubx_evkninab1}/doc/img/EVK-NINA-B1.jpg (100%) create mode 100644 boards/u-blox/ubx_evkninab1/doc/index.rst rename boards/{arm/ubx_evkannab1_nrf52832 => u-blox/ubx_evkninab1}/pre_dt_board.cmake (100%) rename boards/{arm/ubx_evkninab1_nrf52832 => u-blox/ubx_evkninab1}/ubx_evkninab1_nrf52832-pinctrl.dtsi (100%) rename boards/{arm/ubx_evkninab1_nrf52832 => u-blox/ubx_evkninab1}/ubx_evkninab1_nrf52832.dts (100%) rename boards/{arm/ubx_evkninab1_nrf52832 => u-blox/ubx_evkninab1}/ubx_evkninab1_nrf52832.yaml (87%) rename boards/{arm/ubx_evkninab1_nrf52832 => u-blox/ubx_evkninab1}/ubx_evkninab1_nrf52832_defconfig (79%) create mode 100644 boards/u-blox/ubx_evkninab3/Kconfig create mode 100644 boards/u-blox/ubx_evkninab3/Kconfig.defconfig create mode 100644 boards/u-blox/ubx_evkninab3/Kconfig.ubx_evkninab3 rename boards/{arm/ubx_evkninab3_nrf52840 => u-blox/ubx_evkninab3}/board.cmake (100%) create mode 100644 boards/u-blox/ubx_evkninab3/board.yml rename boards/{arm/ubx_evkninab3_nrf52840 => u-blox/ubx_evkninab3}/doc/img/EVK-NINA-B3.jpg (100%) create mode 100644 boards/u-blox/ubx_evkninab3/doc/index.rst rename boards/{arm/ubx_evkninab1_nrf52832 => u-blox/ubx_evkninab3}/pre_dt_board.cmake (100%) rename boards/{arm/ubx_evkninab3_nrf52840 => u-blox/ubx_evkninab3}/ubx_evkninab3_nrf52840-pinctrl.dtsi (100%) rename boards/{arm/ubx_evkninab3_nrf52840 => u-blox/ubx_evkninab3}/ubx_evkninab3_nrf52840.dts (100%) rename boards/{arm/ubx_evkninab3_nrf52840 => u-blox/ubx_evkninab3}/ubx_evkninab3_nrf52840.yaml (89%) rename boards/{arm/ubx_evkninab3_nrf52840 => u-blox/ubx_evkninab3}/ubx_evkninab3_nrf52840_defconfig (79%) create mode 100644 boards/u-blox/ubx_evkninab4/Kconfig create mode 100644 boards/u-blox/ubx_evkninab4/Kconfig.defconfig create mode 100644 boards/u-blox/ubx_evkninab4/Kconfig.ubx_evkninab4 rename boards/{arm/ubx_evkninab4_nrf52833 => u-blox/ubx_evkninab4}/board.cmake (100%) create mode 100644 boards/u-blox/ubx_evkninab4/board.yml rename boards/{arm/ubx_evkninab4_nrf52833 => u-blox/ubx_evkninab4}/doc/img/EVK-NINA-B406_Top_web.jpg (100%) create mode 100644 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boards/{arm/udoo_neo_full_m4/udoo_neo_full_m4-pinctrl.dtsi => udoo/udoo_neo_full/udoo_neo_full-pinctrl.dtsi} (100%) create mode 100644 boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.dts create mode 100644 boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml create mode 100644 boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig create mode 100644 boards/up/index.rst create mode 100644 boards/up/up_squared/CMakeLists.txt create mode 100644 boards/up/up_squared/Kconfig.defconfig create mode 100644 boards/up/up_squared/Kconfig.up_squared create mode 100644 boards/up/up_squared/board.cmake rename boards/{x86 => up}/up_squared/board.h (100%) create mode 100644 boards/up/up_squared/board.yml rename boards/{x86 => up}/up_squared/doc/img/up_squared.jpg (100%) create mode 100644 boards/up/up_squared/doc/index.rst rename boards/{x86 => up}/up_squared/up_squared.dts (100%) rename boards/{x86 => up}/up_squared/up_squared.yaml (100%) rename boards/{x86 => up}/up_squared/up_squared_defconfig (83%) create mode 100644 boards/up/up_squared_pro_7000/CMakeLists.txt create mode 100644 boards/up/up_squared_pro_7000/Kconfig.defconfig create mode 100644 boards/up/up_squared_pro_7000/Kconfig.up_squared_pro_7000 rename boards/{x86/up_squared => up/up_squared_pro_7000}/board.cmake (100%) create mode 100644 boards/up/up_squared_pro_7000/board.yml rename boards/{x86/intel_adl => up/up_squared_pro_7000}/doc/up_squared_pro_7000.rst (95%) rename boards/{x86/intel_adl => up/up_squared_pro_7000}/up_squared_pro_7000.dts (87%) rename boards/{x86/intel_adl => up/up_squared_pro_7000}/up_squared_pro_7000.yaml (100%) rename boards/{x86/intel_adl => up/up_squared_pro_7000}/up_squared_pro_7000_defconfig (79%) create mode 100644 boards/vcc-gnd/index.rst create mode 100644 boards/vcc-gnd/yd_esp32/Kconfig create mode 100644 boards/vcc-gnd/yd_esp32/Kconfig.defconfig create mode 100644 boards/vcc-gnd/yd_esp32/Kconfig.sysbuild create mode 100644 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dts/arm/intel_socfpga_std/{socfpga_cyclone5.dtsi => socfpga_cyclonev.dtsi} (100%) rename dts/arm/{seeed => seeed_studio}/lora-e5.dtsi (100%) rename dts/x86/intel/{ia32.dtsi => atom.dtsi} (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/CMakeLists.txt (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/include/RTE_Device.h (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/include/device_cfg.h (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/include/tfm_ioctl_api.h (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/include/tfm_peripherals_config.h (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/include/tfm_read_ranges.h (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/include/util/array.h (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf5340_cpuapp/CMakeLists.txt (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf5340_cpuapp/config.cmake (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf5340_cpuapp/cpuarch.cmake (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf5340_cpuapp/ns/cpuarch_ns.cmake (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf9120/CMakeLists.txt (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf9120/config.cmake (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf9120/cpuarch.cmake (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf9120/ns/cpuarch_ns.cmake (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf9160/CMakeLists.txt (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf9160/config.cmake (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf9160/cpuarch.cmake (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/nrf9160/ns/cpuarch_ns.cmake (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/ns/CMakeLists.txt (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/src/tfm_hal_platform.c (100%) rename modules/trusted-firmware-m/{nordic_nrf => nordic}/src/tfm_platform_system.c (100%) rename samples/basic/blinky_pwm/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename samples/basic/blinky_pwm/boards/{rcar_h3ulcb_cr7.overlay => rcar_h3ulcb_r8a77951_r7.overlay} (100%) rename samples/bluetooth/beacon/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/broadcaster/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/central/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/central_hr/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/eddystone/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/hci_spi/boards/{nrf51dk_nrf51422.overlay => nrf51dk_nrf51822.overlay} (100%) rename samples/bluetooth/hci_uart/boards/{nrf51dk_nrf51422.conf => nrf51dk_nrf51822.conf} (100%) rename samples/bluetooth/hci_uart/boards/{nrf51dk_nrf51422.overlay => nrf51dk_nrf51822.overlay} (100%) rename samples/bluetooth/hci_uart/boards/{nrf51dongle_nrf51422.conf => nrf51dongle_nrf51822.conf} (100%) rename samples/bluetooth/hci_uart/boards/{nrf51dongle_nrf51422.overlay => nrf51dongle_nrf51822.overlay} (100%) rename samples/bluetooth/hci_uart/boards/{rv32m1_vega_ri5cy.conf => rv32m1_vega_openisa_rv32m1_ri5cy.conf} (100%) rename samples/bluetooth/hci_uart/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/ibeacon/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/ipsp/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/mesh/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/mesh_demo/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/observer/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/peripheral/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/peripheral_csc/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/peripheral_dis/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/peripheral_esp/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/peripheral_hids/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/peripheral_hr/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/peripheral_ht/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/peripheral_sc_only/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename samples/bluetooth/scan_adv/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) create mode 100644 samples/boards/mimxrt595_evk/system_off/CMakeLists.txt rename samples/boards/{mimxrt595_evk_cm33 => mimxrt595_evk}/system_off/Kconfig (100%) rename samples/boards/{mimxrt595_evk_cm33 => mimxrt595_evk}/system_off/README.rst (98%) rename samples/boards/{mimxrt595_evk_cm33 => mimxrt595_evk}/system_off/app.overlay (100%) rename samples/boards/{mimxrt595_evk_cm33 => mimxrt595_evk}/system_off/prj.conf (100%) create mode 100644 samples/boards/mimxrt595_evk/system_off/sample.yaml rename samples/boards/{mimxrt595_evk_cm33 => mimxrt595_evk}/system_off/src/main.c (100%) delete mode 100644 samples/boards/mimxrt595_evk_cm33/system_off/CMakeLists.txt delete mode 100644 samples/boards/mimxrt595_evk_cm33/system_off/sample.yaml rename samples/boards/stm32/h7_dual_core/boards/{stm32h747i_disco_m4.overlay => stm32h747i_disco_stm32h747xx_m4.overlay} (100%) rename samples/boards/stm32/h7_dual_core/boards/{stm32h747i_disco_m7.overlay => stm32h747i_disco_stm32h747xx_m7.overlay} (100%) rename samples/drivers/adc/boards/{longan_nano_lite.overlay => longan_nano_gd32vf103_lite.overlay} (100%) create mode 100644 samples/drivers/adc/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay rename samples/drivers/adc/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_A.overlay} (100%) rename samples/drivers/adc/boards/{mimxrt1170_evkb_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_B.overlay} (100%) rename samples/drivers/adc/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename samples/drivers/adc/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename samples/drivers/adc/boards/{nrf51dk_nrf51422.overlay => nrf51dk_nrf51822.overlay} (100%) rename samples/drivers/adc/boards/{tdk_robokit1.overlay => robokit1.overlay} (100%) rename samples/drivers/adc/boards/{sam_e70_xplained.overlay => sam_e70_xplained_same70q21.overlay} (100%) rename samples/drivers/adc/boards/{sam_v71_xult.overlay => sam_v71_xult_samv71q21.overlay} (100%) rename samples/drivers/adc/boards/{atsamc21n_xpro.overlay => samc21n_xpro.overlay} (100%) rename samples/drivers/adc/boards/{atsamd21_xpro.overlay => samd21_xpro.overlay} (100%) rename samples/drivers/adc/boards/{atsame54_xpro.overlay => same54_xpro.overlay} (100%) rename samples/drivers/adc/boards/{atsaml21_xpro.overlay => saml21_xpro.overlay} (100%) rename samples/drivers/adc/boards/{atsamr21_xpro.overlay => samr21_xpro.overlay} (100%) rename samples/drivers/adc/boards/{atsamr34_xpro.overlay => samr34_xpro.overlay} (100%) rename samples/drivers/audio/dmic/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename samples/drivers/counter/alarm/boards/{bl5340_dvk_cpuapp.conf => bl5340_dvk_nrf5340_cpuapp.conf} (100%) rename samples/drivers/counter/alarm/boards/{bl5340_dvk_cpuapp.overlay => bl5340_dvk_nrf5340_cpuapp.overlay} (100%) rename samples/drivers/counter/alarm/boards/{nrf51dk_nrf51422.overlay => nrf51dk_nrf51822.overlay} (100%) rename samples/drivers/counter/alarm/boards/{s32z270dc2_rtu0_r52.overlay => s32z2xxdc2_s32z270_rtu0.overlay} (100%) rename samples/drivers/counter/alarm/boards/{s32z270dc2_rtu1_r52.overlay => s32z2xxdc2_s32z270_rtu1.overlay} (100%) rename samples/drivers/counter/alarm/boards/{sam_e70_xplained.overlay => sam_e70_xplained_same70q21.overlay} (100%) rename samples/drivers/counter/alarm/boards/{sam_e70b_xplained.overlay => sam_e70_xplained_same70q21b.overlay} (100%) rename samples/drivers/counter/alarm/boards/{sam_v71_xult.overlay => sam_v71_xult_samv71q21.overlay} (100%) rename samples/drivers/counter/alarm/boards/{sam_v71b_xult.overlay => sam_v71_xult_samv71q21b.overlay} (100%) rename samples/drivers/counter/alarm/boards/{stm32l562e_dk_ns.conf => stm32l562e_dk_stm32l562xx_ns.conf} (100%) rename samples/drivers/counter/maxim_ds3231/boards/{nrf51dk_nrf51422.overlay => nrf51dk_nrf51822.overlay} (100%) rename samples/drivers/dac/boards/{bl5340_dvk_cpuapp.overlay => bl5340_dvk_nrf5340_cpuapp.overlay} (100%) rename samples/drivers/dac/boards/{longan_nano_lite.overlay => longan_nano_gd32vf103_lite.overlay} (100%) rename samples/drivers/dac/boards/{sam_e70_xplained.overlay => sam_e70_xplained_same70q21.overlay} (100%) rename samples/drivers/dac/boards/{sam_e70b_xplained.overlay => sam_e70_xplained_same70q21b.overlay} (100%) rename samples/drivers/dac/boards/{sam_v71_xult.overlay => sam_v71_xult_samv71q21.overlay} (100%) rename samples/drivers/dac/boards/{sam_v71b_xult.overlay => sam_v71_xult_samv71q21b.overlay} (100%) rename samples/drivers/display/boards/{mimxrt1170_evk_cm7.conf => mimxrt1170_evk_mimxrt1176_cm7_A.conf} (100%) create mode 100644 samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf rename samples/drivers/display/boards/{mimxrt595_evk_cm33.conf => mimxrt595_evk_mimxrt595s_cm33.conf} (100%) delete mode 100644 samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom.conf rename samples/drivers/ipm/ipm_esp32/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_esp32_procpu.overlay} (100%) delete mode 100644 samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover.conf rename samples/drivers/ipm/ipm_esp32/boards/{esp32_devkitc_wrover.overlay => esp32_devkitc_wrover_esp32_procpu.overlay} (100%) delete mode 100644 samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm.conf rename samples/drivers/ipm/ipm_esp32/boards/{esp32s3_devkitm.overlay => esp32s3_devkitm_esp32s3_procpu.overlay} (100%) rename samples/drivers/ipm/ipm_esp32/boards/{yd_esp32.overlay => yd_esp32_esp32_procpu.overlay} (100%) delete mode 100644 samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wroom_appcpu.overlay delete mode 100644 samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wrover_appcpu.overlay delete mode 100644 samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32s3_dekvitm_appcpu.overlay rename samples/drivers/ipm/ipm_mcux/boards/{lpcxpresso54114_m4.conf => lpcxpresso54114_lpc54114_m4.conf} (100%) rename samples/drivers/led_lpd8806/boards/{96b_carbon.conf => 96b_carbon_stm32f401xe.conf} (100%) rename samples/drivers/led_lpd8806/boards/{96b_carbon.overlay => 96b_carbon_stm32f401xe.overlay} (100%) rename samples/drivers/led_ws2812/boards/{nrf51dk_nrf51422.conf => nrf51dk_nrf51822.conf} (100%) rename samples/drivers/led_ws2812/boards/{nrf51dk_nrf51422.overlay => nrf51dk_nrf51822.overlay} (100%) rename samples/drivers/mbox/boards/{lpcxpresso55s69_cpu0.conf => lpcxpresso55s69_lpc55s69_cpu0.conf} (100%) rename samples/drivers/mbox/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) rename samples/drivers/mbox/boards/{mimxrt1170_evk_cm7.conf => mimxrt1160_evk_mimxrt1166_cm7.conf} (100%) rename samples/drivers/mbox/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1160_evk_mimxrt1166_cm7.overlay} (100%) rename samples/drivers/{mbox_data/boards/mimxrt1170_evk_cm7.conf => mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf} (100%) rename samples/drivers/mbox/boards/{mimxrt1170_evkb_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_A.overlay} (100%) create mode 100644 samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf create mode 100644 samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay rename samples/drivers/mbox/remote/boards/{lpcxpresso55s69_cpu1.conf => lpcxpresso55s69_lpc55s69_cpu1.conf} (100%) rename samples/drivers/mbox/remote/boards/{lpcxpresso55s69_cpu1.overlay => lpcxpresso55s69_lpc55s69_cpu1.overlay} (100%) create mode 100644 samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf create mode 100644 samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay create mode 100644 samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf create mode 100644 samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay create mode 100644 samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf create mode 100644 samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay rename samples/drivers/mbox_data/boards/{lpcxpresso55s69_cpu0.conf => lpcxpresso55s69_lpc55s69_cpu0.conf} (100%) rename samples/drivers/mbox_data/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) rename tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_cm7.conf => samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf (100%) rename samples/drivers/mbox_data/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1160_evk_mimxrt1166_cm7.overlay} (100%) create mode 100644 samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf rename samples/drivers/mbox_data/boards/{mimxrt1170_evkb_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_A.overlay} (100%) create mode 100644 samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf rename tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_cm7.overlay => samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay (100%) rename samples/drivers/mbox_data/remote/boards/{lpcxpresso55s69_cpu1.conf => lpcxpresso55s69_lpc55s69_cpu1.conf} (100%) rename samples/drivers/mbox_data/remote/boards/{lpcxpresso55s69_cpu1.overlay => lpcxpresso55s69_lpc55s69_cpu1.overlay} (100%) create mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf create mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay create mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf create mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay create mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf create mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay rename samples/drivers/memc/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename samples/modules/lvgl/demos/boards/{mimxrt1170_evk_cm7.conf => mimxrt1170_evk_mimxrt1176_cm7_A.conf} (100%) rename samples/net/gptp/boards/{sam_e70_xplained.conf => sam_e70_xplained_same70q21.conf} (100%) delete mode 100644 samples/net/ipv4_autoconf/boards/sam_e70_xplained.conf create mode 100644 samples/net/ipv4_autoconf/boards/sam_e70_xplained_same70q21.conf rename samples/net/sockets/echo_client/boards/{atsamr21_xpro.conf => samr21_xpro.conf} (100%) rename samples/net/sockets/echo_server/boards/{atsamr21_xpro.conf => samr21_xpro.conf} (100%) rename samples/net/zperf/boards/{mimxrt1170_evk_cm7.conf => mimxrt1170_evk_mimxrt1176_cm7_A.conf} (100%) rename samples/sensor/die_temp_polling/boards/{nrf51dk_nrf51422.overlay => nrf51dk_nrf51822.overlay} (100%) rename samples/sensor/fxos8700/boards/{mimxrt1170_evk_cm7.conf => mimxrt1160_evk_mimxrt1166_cm4.conf} (100%) create mode 100644 samples/sensor/fxos8700/boards/mimxrt1160_evk_mimxrt1166_cm7.conf create mode 100644 samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm4.conf create mode 100644 samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf rename samples/sensor/lps22hh_i3c/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename samples/sensor/lsm6dso_i2c_on_i3c/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename samples/sensor/max30101/boards/{hexiwear_k64.overlay => hexiwear_mk64f12.overlay} (100%) rename samples/sensor/mcux_acmp/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm4.overlay} (100%) create mode 100644 samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay rename samples/sensor/sensor_shell/boards/{tdk_robokit1.conf => robokit1.conf} (100%) delete mode 100644 samples/subsys/display/cfb/boards/reel_board_v2.conf rename samples/subsys/display/lvgl/boards/{mimxrt1170_evk_cm7.conf => mimxrt1170_evk_mimxrt1176_cm7_A.conf} (100%) rename samples/subsys/fs/fs_sample/boards/{stm32h747i_disco_m7.conf => stm32h747i_disco_stm32h747xx_m7.conf} (100%) rename samples/subsys/fs/fs_sample/boards/{stm32h747i_disco_m7.overlay => stm32h747i_disco_stm32h747xx_m7.overlay} (100%) rename samples/subsys/fs/littlefs/boards/{lpcxpresso55s69_cpu0.conf => lpcxpresso55s69_lpc55s69_cpu0.conf} (100%) rename samples/subsys/fs/littlefs/boards/{stm32h747i_disco_m7.conf => stm32h747i_disco_stm32h747xx_m7.conf} (100%) rename samples/subsys/fs/littlefs/boards/{stm32h747i_disco_m7.overlay => stm32h747i_disco_stm32h747xx_m7.overlay} (100%) rename samples/subsys/ipc/openamp/boards/{lpcxpresso54114_m4.conf => lpcxpresso54114_lpc54114_m4.conf} (100%) rename samples/subsys/ipc/openamp/boards/{lpcxpresso54114_m4.overlay => lpcxpresso54114_lpc54114_m4.overlay} (100%) rename samples/subsys/ipc/openamp/boards/{lpcxpresso55s69_cpu0.conf => lpcxpresso55s69_lpc55s69_cpu0.conf} (100%) rename samples/subsys/ipc/openamp/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) rename samples/subsys/ipc/openamp/boards/{mimxrt1170_evk_cm7.conf => mimxrt1160_evk_mimxrt1166_cm7.conf} (100%) rename samples/subsys/ipc/openamp/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1160_evk_mimxrt1166_cm7.overlay} (100%) create mode 100644 samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf create mode 100644 samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay create mode 100644 samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf rename samples/subsys/ipc/openamp/boards/{mimxrt1170_evkb_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_B.overlay} (100%) rename samples/subsys/ipc/openamp/remote/boards/{lpcxpresso54114_m0.conf => lpcxpresso54114_lpc54114_m0.conf} (100%) rename samples/subsys/ipc/openamp/remote/boards/{lpcxpresso54114_m0.overlay => lpcxpresso54114_lpc54114_m0.overlay} (100%) rename samples/subsys/ipc/openamp/remote/boards/{lpcxpresso55s69_cpu1.conf => lpcxpresso55s69_lpc55s69_cpu1.conf} (100%) rename samples/subsys/ipc/openamp/remote/boards/{lpcxpresso55s69_cpu1.overlay => lpcxpresso55s69_lpc55s69_cpu1.overlay} (100%) create mode 100644 samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf create mode 100644 samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay create mode 100644 samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf create mode 100644 samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay create mode 100644 samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf create mode 100644 samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay rename samples/subsys/ipc/openamp/remote/boards/{mps2_an521_remote.overlay => mps2_an521_cpu1.overlay} (100%) rename samples/subsys/ipc/openamp/remote/boards/{v2m_musca_b1_ns.overlay => v2m_musca_b1_musca_b1_ns.overlay} (100%) rename samples/subsys/ipc/openamp_rsc_table/boards/{nxp_adsp_imx8m.conf => imx8mp_evk_mimx8ml8_adsp.conf} (100%) rename samples/subsys/ipc/openamp_rsc_table/boards/{nxp_adsp_imx8m.overlay => imx8mp_evk_mimx8ml8_adsp.overlay} (100%) rename samples/subsys/ipc/rpmsg_service/boards/{bl5340_dvk_cpuapp.conf => bl5340_dvk_nrf5340_cpuapp.conf} (100%) rename samples/subsys/ipc/rpmsg_service/remote/boards/{mps2_an521_remote.overlay => mps2_an521_cpu1.overlay} (100%) rename samples/subsys/ipc/rpmsg_service/remote/boards/{v2m_musca_b1_ns.overlay => v2m_musca_b1_musca_b1_ns.overlay} (100%) rename samples/subsys/usb/mass/boards/{stm32l562e_dk_ns.conf => stm32l562e_dk_stm32l562xx_ns.conf} (100%) rename samples/subsys/zbus/remote_mock/boards/{hifive1_revb.conf => hifive1_fe310_B.conf} (100%) rename samples/subsys/zbus/remote_mock/boards/{hifive1_revb.overlay => hifive1_fe310_B.overlay} (100%) rename samples/subsys/zbus/uart_bridge/boards/{hifive1_revb.conf => hifive1_fe310_B.conf} (100%) rename samples/subsys/zbus/uart_bridge/boards/{hifive1_revb.overlay => hifive1_fe310_B.overlay} (100%) rename samples/tfm_integration/tfm_ipc/boards/{nucleo_l552ze_q_ns.overlay => nucleo_l552ze_q_stm32l552xx_ns.overlay} (100%) rename samples/tfm_integration/tfm_regression_test/boards/{nucleo_l552ze_q_ns.overlay => nucleo_l552ze_q_stm32l552xx_ns.overlay} (100%) create mode 100644 scripts/ci/Kconfig.board.v2 create mode 100755 scripts/list_hardware.py create mode 100644 scripts/pylib/twister/boards/unit/unit_testing/board.yml create mode 100644 scripts/pylib/twister/soc/unit/unit_testing/soc.yml create mode 100644 scripts/schemas/arch-schema.yml create mode 100644 scripts/schemas/board-schema.yml create mode 100644 scripts/schemas/soc-schema.yml create mode 100644 scripts/utils/board_v1_to_v2.py rename snippets/xen_dom0/boards/{rcar_h3ulcb_ca57.overlay => rcar_h3ulcb_r8a77951_a57.overlay} (100%) rename snippets/xen_dom0/boards/{rcar_salvator_xs_m3.overlay => rcar_salvator_xs.overlay} (100%) create mode 100644 soc/Kconfig.v1 create mode 100644 soc/Kconfig.v1.choice create mode 100644 soc/Kconfig.v2 create mode 100644 soc/altr/qemu_nios2/CMakeLists.txt create mode 100644 soc/altr/qemu_nios2/Kconfig create mode 100644 soc/altr/qemu_nios2/Kconfig.defconfig create mode 100644 soc/altr/qemu_nios2/Kconfig.soc rename soc/{nios2/nios2-qemu => altr/qemu_nios2}/include/layout.h (100%) rename soc/{nios2/nios2-qemu => altr/qemu_nios2}/include/linker.h (100%) rename soc/{nios2/nios2-qemu => altr/qemu_nios2}/include/system.h (100%) rename soc/{nios2/nios2-qemu => altr/qemu_nios2}/linker.ld (100%) rename soc/{nios2/nios2-qemu => altr/qemu_nios2}/soc.h (100%) create mode 100644 soc/altr/qemu_nios2/soc.yml create mode 100644 soc/altr/zephyr_nios2f/CMakeLists.txt create mode 100644 soc/altr/zephyr_nios2f/Kconfig create mode 100644 soc/altr/zephyr_nios2f/Kconfig.defconfig create mode 100644 soc/altr/zephyr_nios2f/Kconfig.soc rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/cpu/README (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/cpu/ghrd_10m50da.qpf (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/cpu/ghrd_10m50da.qsf (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/cpu/ghrd_10m50da.qsys (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/cpu/ghrd_10m50da.sof (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/cpu/ghrd_10m50da.sopcinfo (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/cpu/ghrd_10m50da_top.v (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/cpu/ghrd_timing.sdc (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/include/layout.h (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/include/linker.h (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/include/system.h (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/linker.ld (100%) rename soc/{nios2/nios2f-zephyr => altr/zephyr_nios2f}/soc.h (100%) create mode 100644 soc/altr/zephyr_nios2f/soc.yml rename soc/{arm => }/ambiq/CMakeLists.txt (100%) create mode 100644 soc/ambiq/Kconfig create mode 100644 soc/ambiq/Kconfig.defconfig create mode 100644 soc/ambiq/Kconfig.soc create mode 100644 soc/ambiq/apollo4x/CMakeLists.txt create mode 100644 soc/ambiq/apollo4x/Kconfig create mode 100644 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100644 soc/atmel/sam0/samr21/Kconfig.defconfig create mode 100644 soc/atmel/sam0/samr21/Kconfig.soc create mode 100644 soc/atmel/sam0/samr21/soc.h create mode 100644 soc/atmel/sam0/samr34/CMakeLists.txt create mode 100644 soc/atmel/sam0/samr34/Kconfig create mode 100644 soc/atmel/sam0/samr34/Kconfig.defconfig create mode 100644 soc/atmel/sam0/samr34/Kconfig.soc create mode 100644 soc/atmel/sam0/samr34/soc.h create mode 100644 soc/atmel/sam0/samr35/CMakeLists.txt create mode 100644 soc/atmel/sam0/samr35/Kconfig create mode 100644 soc/atmel/sam0/samr35/Kconfig.defconfig create mode 100644 soc/atmel/sam0/samr35/Kconfig.soc create mode 100644 soc/atmel/sam0/samr35/soc.h create mode 100644 soc/atmel/sam0/soc.yml rename soc/{arm64 => brcm}/bcm2711/CMakeLists.txt (100%) create mode 100644 soc/brcm/bcm2711/Kconfig create mode 100644 soc/brcm/bcm2711/Kconfig.defconfig create mode 100644 soc/brcm/bcm2711/Kconfig.soc rename soc/{arm64 => brcm}/bcm2711/mmu_regions.c (100%) create mode 100644 soc/brcm/bcm2711/soc.yml rename soc/{arm/arm => brcm/bcmvk}/CMakeLists.txt (100%) create mode 100644 soc/brcm/bcmvk/Kconfig create mode 100644 soc/brcm/bcmvk/Kconfig.defconfig create mode 100644 soc/brcm/bcmvk/Kconfig.soc create mode 100644 soc/brcm/bcmvk/soc.yml create mode 100644 soc/brcm/bcmvk/valkyrie/CMakeLists.txt create mode 100644 soc/brcm/bcmvk/valkyrie/Kconfig create mode 100644 soc/brcm/bcmvk/valkyrie/Kconfig.defconfig create mode 100644 soc/brcm/bcmvk/valkyrie/Kconfig.soc rename soc/{arm/bcm_vk => brcm/bcmvk}/valkyrie/soc.h (100%) create mode 100644 soc/brcm/bcmvk/viper/CMakeLists.txt create mode 100644 soc/brcm/bcmvk/viper/Kconfig create mode 100644 soc/brcm/bcmvk/viper/Kconfig.defconfig rename soc/{arm64/bcm_vk => brcm/bcmvk}/viper/Kconfig.defconfig.viper_bcm58402_a72 (83%) rename soc/{arm/bcm_vk => brcm/bcmvk}/viper/Kconfig.defconfig.viper_bcm58402_m7 (84%) create mode 100644 soc/brcm/bcmvk/viper/Kconfig.soc rename soc/{arm64/bcm_vk/viper => brcm/bcmvk/viper/a72}/mmu_regions.c (100%) rename soc/{arm64/bcm_vk/viper => brcm/bcmvk/viper/a72}/plat_core.c (100%) rename soc/{arm64/bcm_vk/viper => brcm/bcmvk/viper/a72}/soc.c (100%) rename soc/{arm64/bcm_vk/viper => brcm/bcmvk/viper/a72}/soc.h (100%) rename soc/{arm/bcm_vk/viper => brcm/bcmvk/viper/m7}/soc.c (100%) rename soc/{arm/bcm_vk/viper => brcm/bcmvk/viper/m7}/soc.h (100%) rename soc/{xtensa => cdns}/dc233c/CMakeLists.txt (100%) create mode 100644 soc/cdns/dc233c/Kconfig create mode 100644 soc/cdns/dc233c/Kconfig.defconfig create mode 100644 soc/cdns/dc233c/Kconfig.soc rename soc/{xtensa => cdns}/dc233c/include/_soc_inthandlers.h (100%) rename soc/{xtensa => cdns}/dc233c/include/backtrace_helpers.h (100%) rename soc/{xtensa => cdns}/dc233c/include/xtensa-dc233c.ld (100%) rename soc/{xtensa => cdns}/dc233c/mmu.c (100%) create mode 100644 soc/cdns/dc233c/soc.yml rename soc/{xtensa/sample_controller => cdns/xtensa_sample_controller}/CMakeLists.txt (100%) create mode 100644 soc/cdns/xtensa_sample_controller/Kconfig create mode 100644 soc/cdns/xtensa_sample_controller/Kconfig.soc rename soc/{xtensa/sample_controller => cdns/xtensa_sample_controller}/include/_soc_inthandlers.h (100%) rename soc/{xtensa/sample_controller => cdns/xtensa_sample_controller}/include/xtensa-sample-controller.ld (100%) create mode 100644 soc/cdns/xtensa_sample_controller/soc.yml create mode 100644 soc/common/Kconfig delete mode 100644 soc/common/nordic_nrf/CMakeLists.txt rename soc/{riscv => }/common/riscv-privileged/CMakeLists.txt (100%) rename soc/{riscv => }/common/riscv-privileged/Kconfig (100%) rename soc/{riscv => }/common/riscv-privileged/soc_common_irq.c (100%) rename soc/{riscv => }/common/riscv-privileged/soc_irq.S (100%) rename soc/{riscv => }/common/riscv-privileged/vector.S (100%) create mode 100644 soc/cypress/CMakeLists.txt create mode 100644 soc/cypress/Kconfig create mode 100644 soc/cypress/Kconfig.defconfig create mode 100644 soc/cypress/Kconfig.soc create mode 100644 soc/cypress/psoc6/CMakeLists.txt create mode 100644 soc/cypress/psoc6/Kconfig create mode 100644 soc/cypress/psoc6/Kconfig.defconfig create mode 100644 soc/cypress/psoc6/Kconfig.soc create mode 100644 soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_01 create mode 100644 soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_02 create mode 100644 soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_04 rename soc/{arm/infineon_cat1 => cypress/psoc6/new}/common/pinctrl_soc.h (100%) rename soc/{arm/infineon_cat1/psoc6 => cypress/psoc6/new}/noinit.ld (100%) rename soc/{arm/infineon_cat1/psoc6 => cypress/psoc6/new}/ram_cm0image.ld (100%) rename soc/{arm/infineon_cat1/psoc6 => cypress/psoc6/new}/ram_func.ld (100%) rename soc/{arm/infineon_cat1/psoc6 => cypress/psoc6/new}/rom.ld (100%) rename soc/{arm/infineon_cat1/psoc6 => cypress/psoc6/new}/rom_cm0image.ld (100%) rename soc/{arm/infineon_cat1/psoc6 => cypress/psoc6/new}/soc.c (100%) rename soc/{arm/infineon_cat1/psoc6 => cypress/psoc6/new}/soc.h (100%) create mode 100644 soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m0 create mode 100644 soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m4 rename soc/{arm/cypress => cypress/psoc6/old}/common/CMakeLists.txt (100%) rename soc/{arm/cypress => cypress/psoc6/old}/common/cypress_psoc6_dt.h (100%) rename soc/{arm/cypress => cypress/psoc6/old}/common/soc_gpio.c (100%) rename soc/{arm/cypress => cypress/psoc6/old}/common/soc_gpio.h (100%) rename soc/{arm/cypress/psoc6 => cypress/psoc6/old}/noinit.ld (100%) rename soc/{arm/cypress/psoc6 => cypress/psoc6/old}/rwdata.ld (100%) rename soc/{arm/cypress/psoc6 => cypress/psoc6/old}/soc.c (100%) rename soc/{arm/cypress/psoc6 => cypress/psoc6/old}/soc.h (100%) create mode 100644 soc/cypress/soc.yml rename soc/{riscv/efinix_sapphire => efinix/sapphire}/CMakeLists.txt (100%) create mode 100644 soc/efinix/sapphire/Kconfig create mode 100644 soc/efinix/sapphire/Kconfig.defconfig create mode 100644 soc/efinix/sapphire/Kconfig.soc create mode 100644 soc/efinix/sapphire/soc.yml create mode 100644 soc/espressif/CMakeLists.txt create mode 100644 soc/espressif/Kconfig create mode 100644 soc/espressif/Kconfig.defconfig create mode 100644 soc/espressif/Kconfig.soc create mode 100644 soc/espressif/common/CMakeLists.txt create mode 100644 soc/espressif/common/Kconfig create mode 100644 soc/espressif/common/Kconfig.defconfig rename soc/{xtensa/espressif_esp32 => espressif}/common/include/_soc_inthandlers.h (100%) rename soc/{xtensa/espressif_esp32 => espressif}/common/include/gdbstub/soc.h (100%) create mode 100644 soc/espressif/esp32/CMakeLists.txt create mode 100644 soc/espressif/esp32/Kconfig create mode 100644 soc/espressif/esp32/Kconfig.defconfig create mode 100644 soc/espressif/esp32/Kconfig.soc create mode 100644 soc/espressif/esp32/default.ld rename soc/{xtensa/espressif_esp32 => espressif}/esp32/default_appcpu.ld (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32/esp32-mp.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32/gdbstub.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32/loader.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32/mcuboot.ld (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32/newlib_fix.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32/pinctrl_soc.h (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32/power.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32/poweroff.c (100%) create mode 100644 soc/espressif/esp32/soc.c rename soc/{xtensa/espressif_esp32 => espressif}/esp32/soc.h (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32/soc_appcpu.c (100%) create mode 100644 soc/espressif/esp32c3/CMakeLists.txt create mode 100644 soc/espressif/esp32c3/Kconfig create mode 100644 soc/espressif/esp32c3/Kconfig.defconfig create mode 100644 soc/espressif/esp32c3/Kconfig.soc rename soc/{riscv/espressif_esp32 => espressif}/esp32c3/default.ld (100%) rename soc/{riscv/espressif_esp32 => espressif}/esp32c3/loader.c (100%) rename soc/{riscv/espressif_esp32 => espressif}/esp32c3/mcuboot.ld (100%) rename soc/{riscv/espressif_esp32 => espressif}/esp32c3/pinctrl_soc.h (100%) rename soc/{riscv/espressif_esp32 => espressif}/esp32c3/power.c (100%) rename soc/{riscv/espressif_esp32 => espressif}/esp32c3/poweroff.c (100%) rename soc/{riscv/espressif_esp32 => espressif}/esp32c3/soc.c (100%) rename soc/{riscv/espressif_esp32 => espressif}/esp32c3/soc.h (100%) rename soc/{riscv/espressif_esp32 => espressif}/esp32c3/soc_irq.S (100%) rename soc/{riscv/espressif_esp32 => espressif}/esp32c3/soc_irq.c (100%) rename soc/{riscv/espressif_esp32 => espressif}/esp32c3/vectors.S (100%) create mode 100644 soc/espressif/esp32s2/CMakeLists.txt create mode 100644 soc/espressif/esp32s2/Kconfig create mode 100644 soc/espressif/esp32s2/Kconfig.defconfig create mode 100644 soc/espressif/esp32s2/Kconfig.defconfig.series create mode 100644 soc/espressif/esp32s2/Kconfig.soc rename soc/{xtensa/espressif_esp32 => espressif}/esp32s2/default.ld (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s2/loader.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s2/mcuboot.ld (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s2/newlib_fix.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s2/pinctrl_soc.h (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s2/power.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s2/poweroff.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s2/soc.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s2/soc.h (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s2/soc_cache.c (100%) create mode 100644 soc/espressif/esp32s3/CMakeLists.txt create mode 100644 soc/espressif/esp32s3/Kconfig create mode 100644 soc/espressif/esp32s3/Kconfig.defconfig create mode 100644 soc/espressif/esp32s3/Kconfig.soc create mode 100644 soc/espressif/esp32s3/default.ld rename soc/{xtensa/espressif_esp32 => espressif}/esp32s3/default_appcpu.ld (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s3/esp32s3-mp.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s3/loader.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s3/mcuboot.ld (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s3/newlib_fix.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s3/pinctrl_soc.h (100%) create mode 100644 soc/espressif/esp32s3/soc.c rename soc/{xtensa/espressif_esp32 => espressif}/esp32s3/soc.h (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s3/soc_appcpu.c (100%) rename soc/{xtensa/espressif_esp32 => espressif}/esp32s3/soc_cache.c (100%) create mode 100644 soc/espressif/soc.yml create mode 100644 soc/gaisler/Kconfig create mode 100644 soc/gaisler/Kconfig.soc create mode 100644 soc/gaisler/gr716a/CMakeLists.txt create mode 100644 soc/gaisler/gr716a/Kconfig create mode 100644 soc/gaisler/gr716a/Kconfig.defconfig create mode 100644 soc/gaisler/gr716a/Kconfig.soc rename soc/{sparc => gaisler}/gr716a/linker.ld (100%) rename soc/{sparc => gaisler}/gr716a/soc.h (100%) create mode 100644 soc/gaisler/gr716a/soc.yml create mode 100644 soc/gaisler/leon3/CMakeLists.txt create mode 100644 soc/gaisler/leon3/Kconfig create mode 100644 soc/gaisler/leon3/Kconfig.defconfig create mode 100644 soc/gaisler/leon3/Kconfig.soc rename soc/{sparc => gaisler}/leon3/idle.c (100%) rename soc/{sparc => gaisler}/leon3/linker.ld (100%) rename soc/{sparc => gaisler}/leon3/soc.h (100%) create mode 100644 soc/gaisler/leon3/soc.yml rename soc/{arm/gd_gd32 => gd/gd32}/CMakeLists.txt (100%) create mode 100644 soc/gd/gd32/Kconfig create mode 100644 soc/gd/gd32/Kconfig.defconfig create mode 100644 soc/gd/gd32/Kconfig.soc rename soc/{arm/gd_gd32 => gd/gd32}/common/CMakeLists.txt (100%) rename include/zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h => soc/gd/gd32/common/pinctrl_soc.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32a50x/CMakeLists.txt (100%) create mode 100644 soc/gd/gd32/gd32a50x/Kconfig rename soc/{arm/gd_gd32 => gd/gd32}/gd32a50x/Kconfig.defconfig.gd32a503 (85%) create mode 100644 soc/gd/gd32/gd32a50x/Kconfig.defconfig.series create mode 100644 soc/gd/gd32/gd32a50x/Kconfig.soc rename soc/{arm/gd_gd32 => gd/gd32}/gd32a50x/gd32_regs.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32a50x/soc.c (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32a50x/soc.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32e10x/CMakeLists.txt (100%) create mode 100644 soc/gd/gd32/gd32e10x/Kconfig rename soc/{arm/gd_gd32 => gd/gd32}/gd32e10x/Kconfig.defconfig.gd32e103 (85%) create mode 100644 soc/gd/gd32/gd32e10x/Kconfig.defconfig.series create mode 100644 soc/gd/gd32/gd32e10x/Kconfig.soc rename soc/{arm/gd_gd32 => gd/gd32}/gd32e10x/gd32_regs.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32e10x/soc.c (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32e10x/soc.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32e50x/CMakeLists.txt (100%) create mode 100644 soc/gd/gd32/gd32e50x/Kconfig rename soc/{arm/gd_gd32 => gd/gd32}/gd32e50x/Kconfig.defconfig.gd32e507 (88%) create mode 100644 soc/gd/gd32/gd32e50x/Kconfig.defconfig.series create mode 100644 soc/gd/gd32/gd32e50x/Kconfig.soc rename soc/{arm/gd_gd32 => gd/gd32}/gd32e50x/gd32_regs.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32e50x/soc.c (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32e50x/soc.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f3x0/CMakeLists.txt (100%) create mode 100644 soc/gd/gd32/gd32f3x0/Kconfig rename soc/{arm/gd_gd32 => gd/gd32}/gd32f3x0/Kconfig.defconfig.gd32f350 (83%) create mode 100644 soc/gd/gd32/gd32f3x0/Kconfig.defconfig.series create mode 100644 soc/gd/gd32/gd32f3x0/Kconfig.soc rename soc/{arm/gd_gd32 => gd/gd32}/gd32f3x0/gd32_regs.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f3x0/soc.c (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f3x0/soc.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f403/CMakeLists.txt (100%) create mode 100644 soc/gd/gd32/gd32f403/Kconfig rename soc/{arm/gd_gd32 => gd/gd32}/gd32f403/Kconfig.defconfig.gd32f403 (84%) create mode 100644 soc/gd/gd32/gd32f403/Kconfig.defconfig.series create mode 100644 soc/gd/gd32/gd32f403/Kconfig.soc rename soc/{arm/gd_gd32 => gd/gd32}/gd32f403/gd32_regs.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f403/soc.c (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f403/soc.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f4xx/CMakeLists.txt (100%) create mode 100644 soc/gd/gd32/gd32f4xx/Kconfig rename soc/{arm/gd_gd32 => gd/gd32}/gd32f4xx/Kconfig.defconfig.gd32f405 (88%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f4xx/Kconfig.defconfig.gd32f407 (89%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f4xx/Kconfig.defconfig.gd32f450 (88%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f4xx/Kconfig.defconfig.gd32f470 (87%) create mode 100644 soc/gd/gd32/gd32f4xx/Kconfig.defconfig.series create mode 100644 soc/gd/gd32/gd32f4xx/Kconfig.soc rename soc/{arm/gd_gd32 => gd/gd32}/gd32f4xx/gd32_regs.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f4xx/soc.c (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32f4xx/soc.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32l23x/CMakeLists.txt (100%) create mode 100644 soc/gd/gd32/gd32l23x/Kconfig rename soc/{arm/gd_gd32 => gd/gd32}/gd32l23x/Kconfig.defconfig.gd32l233 (83%) create mode 100644 soc/gd/gd32/gd32l23x/Kconfig.defconfig.series create mode 100644 soc/gd/gd32/gd32l23x/Kconfig.soc rename soc/{arm/gd_gd32 => gd/gd32}/gd32l23x/gd32_regs.h (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32l23x/soc.c (100%) rename soc/{arm/gd_gd32 => gd/gd32}/gd32l23x/soc.h (100%) create mode 100644 soc/gd/gd32/gd32vf103/CMakeLists.txt create mode 100644 soc/gd/gd32/gd32vf103/Kconfig rename soc/{riscv/gd_gd32 => gd/gd32}/gd32vf103/Kconfig.defconfig.gd32vf103 (86%) create mode 100644 soc/gd/gd32/gd32vf103/Kconfig.defconfig.series create mode 100644 soc/gd/gd32/gd32vf103/Kconfig.soc rename soc/{riscv/gd_gd32 => gd/gd32}/gd32vf103/entry.S (100%) rename soc/{riscv/gd_gd32 => gd/gd32}/gd32vf103/gd32_regs.h (100%) rename soc/{riscv/gd_gd32 => gd/gd32}/gd32vf103/init.ld (100%) rename soc/{riscv/gd_gd32 => gd/gd32}/gd32vf103/nuclei_csr.h (100%) rename soc/{riscv/gd_gd32 => gd/gd32}/gd32vf103/soc.c (100%) create mode 100644 soc/gd/gd32/soc.yml rename soc/{arm/infineon_xmc => infineon/xmc}/CMakeLists.txt (100%) create mode 100644 soc/infineon/xmc/Kconfig create mode 100644 soc/infineon/xmc/Kconfig.defconfig create mode 100644 soc/infineon/xmc/Kconfig.soc create mode 100644 soc/infineon/xmc/soc.yml create mode 100644 soc/infineon/xmc/xmc4xxx/CMakeLists.txt create mode 100644 soc/infineon/xmc/xmc4xxx/Kconfig create mode 100644 soc/infineon/xmc/xmc4xxx/Kconfig.defconfig rename soc/{arm/infineon_xmc/4xxx => infineon/xmc/xmc4xxx}/Kconfig.defconfig.xmc4500 (90%) rename soc/{arm/infineon_xmc/4xxx => infineon/xmc/xmc4xxx}/Kconfig.defconfig.xmc4700 (89%) create mode 100644 soc/infineon/xmc/xmc4xxx/Kconfig.soc rename soc/{arm/infineon_xmc/4xxx => infineon/xmc/xmc4xxx}/noinit.ld (100%) rename soc/{arm/infineon_xmc/4xxx => infineon/xmc/xmc4xxx}/pinctrl_soc.h (100%) rename soc/{arm/infineon_xmc/4xxx => infineon/xmc/xmc4xxx}/soc.c (100%) rename soc/{arm/infineon_xmc/4xxx => infineon/xmc/xmc4xxx}/soc.h (100%) create mode 100644 soc/intel/alder_lake/CMakeLists.txt create mode 100644 soc/intel/alder_lake/Kconfig create mode 100644 soc/intel/alder_lake/Kconfig.defconfig create mode 100644 soc/intel/alder_lake/Kconfig.soc rename soc/{x86 => intel}/alder_lake/cpu.c (100%) rename soc/{x86 => intel}/alder_lake/doc/supported_features.txt (100%) rename soc/{x86 => intel}/alder_lake/linker.ld (100%) rename soc/{x86 => intel}/alder_lake/soc.h (100%) create mode 100644 soc/intel/alder_lake/soc.yml rename soc/{x86 => intel}/alder_lake/soc_gpio.h (100%) create mode 100644 soc/intel/apollo_lake/CMakeLists.txt create mode 100644 soc/intel/apollo_lake/Kconfig create mode 100644 soc/intel/apollo_lake/Kconfig.defconfig create mode 100644 soc/intel/apollo_lake/Kconfig.soc rename soc/{x86 => intel}/apollo_lake/cpu.c (100%) rename soc/{x86 => intel}/apollo_lake/doc/supported_features.txt (100%) rename soc/{x86 => intel}/apollo_lake/linker.ld (100%) rename soc/{x86 => intel}/apollo_lake/soc.h (100%) create mode 100644 soc/intel/apollo_lake/soc.yml rename soc/{x86 => intel}/apollo_lake/soc_gpio.h (100%) create mode 100644 soc/intel/atom/CMakeLists.txt create mode 100644 soc/intel/atom/Kconfig create mode 100644 soc/intel/atom/Kconfig.defconfig create mode 100644 soc/intel/atom/Kconfig.soc rename soc/{x86/ia32 => intel/atom}/linker.ld (100%) create mode 100644 soc/intel/atom/soc.yml create mode 100644 soc/intel/elkhart_lake/CMakeLists.txt create mode 100644 soc/intel/elkhart_lake/Kconfig create mode 100644 soc/intel/elkhart_lake/Kconfig.defconfig create mode 100644 soc/intel/elkhart_lake/Kconfig.soc rename soc/{x86 => intel}/elkhart_lake/cpu.c (100%) rename soc/{x86 => intel}/elkhart_lake/doc/supported_features.txt (100%) rename soc/{x86 => intel}/elkhart_lake/linker.ld (100%) rename soc/{x86 => intel}/elkhart_lake/soc.h (100%) create mode 100644 soc/intel/elkhart_lake/soc.yml rename soc/{x86 => intel}/elkhart_lake/soc_gpio.h (100%) create mode 100644 soc/intel/intel_adsp/CMakeLists.txt create mode 100644 soc/intel/intel_adsp/Kconfig create mode 100644 soc/intel/intel_adsp/Kconfig.defconfig create mode 100644 soc/intel/intel_adsp/Kconfig.soc create mode 100644 soc/intel/intel_adsp/ace/CMakeLists.txt create mode 100644 soc/intel/intel_adsp/ace/Kconfig create mode 100644 soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm create mode 100644 soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl create mode 100644 soc/intel/intel_adsp/ace/Kconfig.defconfig.series create mode 100644 soc/intel/intel_adsp/ace/Kconfig.soc rename soc/{xtensa => intel}/intel_adsp/ace/_soc_inthandlers.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/ace-link.ld (100%) rename soc/{xtensa => intel}/intel_adsp/ace/asm_memory_management.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/boot.c (100%) rename soc/{xtensa => intel}/intel_adsp/ace/comm_widget.c (100%) rename soc/{xtensa => intel}/intel_adsp/ace/comm_widget.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/comm_widget_messages.c (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/adsp_imr_layout.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/adsp_timestamp.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/dmic_regs.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace15_mtpm/adsp_comm_widget.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace15_mtpm/adsp_interrupt.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace15_mtpm/adsp_ipc_regs.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace15_mtpm/adsp_watchdog.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace15_mtpm/dmic_regs_ace1x.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace20_lnl/adsp_boot.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace20_lnl/adsp_interrupt.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace20_lnl/adsp_ipc_regs.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory_regions.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace20_lnl/adsp_shim.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/include/intel_ace20_lnl/dmic_regs_ace2x.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/irq.c (100%) rename soc/{xtensa => intel}/intel_adsp/ace/linker.ld (100%) rename soc/{xtensa => intel}/intel_adsp/ace/multiprocessing.c (100%) rename soc/{xtensa => intel}/intel_adsp/ace/pmc_interface.h (100%) rename soc/{xtensa => intel}/intel_adsp/ace/power.c (100%) rename soc/{xtensa => intel}/intel_adsp/ace/power_down.S (100%) rename soc/{xtensa => intel}/intel_adsp/ace/sram.c (100%) rename soc/{xtensa => intel}/intel_adsp/ace/timestamp.c (100%) create mode 100644 soc/intel/intel_adsp/cavs/CMakeLists.txt create mode 100644 soc/intel/intel_adsp/cavs/Kconfig rename soc/{xtensa => intel}/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 (88%) create mode 100644 soc/intel/intel_adsp/cavs/Kconfig.defconfig.series create mode 100644 soc/intel/intel_adsp/cavs/Kconfig.soc rename soc/{xtensa/intel_adsp/common/include => intel/intel_adsp/cavs}/_soc_inthandlers.h (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/asm_ldo_management.h (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/asm_memory_management.h (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/include/adsp_interrupt.h (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/include/intel_tgl_adsp/adsp_imr_layout.h (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/include/intel_tgl_adsp/adsp_ipc_regs.h (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/include/xtensa-cavs-linker.ld (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/irq.c (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/multiprocessing.c (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/power.c (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/power_down_cavs.S (100%) rename soc/{xtensa => intel}/intel_adsp/cavs/sram.c (100%) create mode 100644 soc/intel/intel_adsp/common/CMakeLists.txt rename soc/{xtensa => intel}/intel_adsp/common/boot.c (98%) rename soc/{xtensa => intel}/intel_adsp/common/boot_complete.c (100%) rename soc/{xtensa => intel}/intel_adsp/common/clk.c (96%) rename soc/{xtensa => intel}/intel_adsp/common/include/adsp-vectors.h (95%) rename soc/{xtensa => intel}/intel_adsp/common/include/adsp_clk.h (98%) rename soc/{xtensa => intel}/intel_adsp/common/include/adsp_debug_window.h (100%) rename soc/{xtensa => intel}/intel_adsp/common/include/cavs-idc.h (100%) rename soc/{xtensa => intel}/intel_adsp/common/include/cavstool.h (100%) rename soc/{xtensa => intel}/intel_adsp/common/include/cpu_init.h (100%) rename soc/{xtensa => intel}/intel_adsp/common/include/debug_helpers.h (100%) rename soc/{xtensa => intel}/intel_adsp/common/include/intel_adsp_hda.h (99%) rename soc/{xtensa => intel}/intel_adsp/common/include/intel_adsp_ipc.h (100%) rename soc/{xtensa => intel}/intel_adsp/common/include/intel_adsp_ipc_devtree.h (100%) rename soc/{xtensa => intel}/intel_adsp/common/include/manifest.h (100%) rename soc/{xtensa => intel}/intel_adsp/common/include/mem_window.h (100%) rename soc/{xtensa => intel}/intel_adsp/common/include/soc.h (100%) rename soc/{xtensa => intel}/intel_adsp/common/include/soc_util.h (100%) rename soc/{xtensa => intel}/intel_adsp/common/ipc.c (98%) rename soc/{xtensa => intel}/intel_adsp/common/mem_window.c (100%) rename soc/{xtensa => intel}/intel_adsp/common/multiprocessing.c (100%) rename soc/{xtensa => intel}/intel_adsp/common/rimage_modules.c (100%) rename soc/{xtensa => intel}/intel_adsp/common/soc.c (100%) create mode 100644 soc/intel/intel_adsp/soc.yml rename soc/{xtensa => intel}/intel_adsp/tools/acetool.py (99%) rename soc/{xtensa => intel}/intel_adsp/tools/cavstool.py (99%) rename soc/{xtensa => intel}/intel_adsp/tools/cavstool_client.py (100%) rename soc/{xtensa => intel}/intel_adsp/tools/cavstwist.sh (94%) rename soc/{xtensa => intel}/intel_adsp/tools/remote-fw-service.py (99%) rename soc/{x86 => intel}/intel_ish/CMakeLists.txt (100%) create mode 100644 soc/intel/intel_ish/Kconfig create mode 100644 soc/intel/intel_ish/Kconfig.defconfig create mode 100644 soc/intel/intel_ish/Kconfig.soc rename soc/{x86 => intel}/intel_ish/doc/supported_features.txt (100%) create mode 100644 soc/intel/intel_ish/intel_ish5/CMakeLists.txt create mode 100644 soc/intel/intel_ish/intel_ish5/Kconfig.defconfig.series create mode 100644 soc/intel/intel_ish/intel_ish5/Kconfig.soc rename soc/{x86 => intel}/intel_ish/intel_ish5/linker.ld (100%) rename soc/{x86 => intel}/intel_ish/intel_ish5/pm/CMakeLists.txt (100%) rename soc/{x86 => intel}/intel_ish/intel_ish5/pm/Kconfig.pm (100%) rename soc/{x86 => intel}/intel_ish/intel_ish5/pm/power.c (100%) rename soc/{x86 => intel}/intel_ish/intel_ish5/soc.c (100%) rename soc/{x86 => intel}/intel_ish/intel_ish5/soc.h (100%) create mode 100644 soc/intel/intel_ish/soc.yml rename soc/{x86 => intel}/intel_ish/utils/build_ish_firmware.cmake (100%) rename soc/{x86 => intel}/intel_ish/utils/build_ish_firmware.py (100%) create mode 100644 soc/intel/intel_niosv/CMakeLists.txt create mode 100644 soc/intel/intel_niosv/Kconfig create mode 100644 soc/intel/intel_niosv/Kconfig.defconfig create mode 100644 soc/intel/intel_niosv/Kconfig.soc rename soc/{riscv => intel}/intel_niosv/niosv/CMakeLists.txt (100%) create mode 100644 soc/intel/intel_niosv/niosv/Kconfig create mode 100644 soc/intel/intel_niosv/niosv/Kconfig.defconfig.series create mode 100644 soc/intel/intel_niosv/niosv/Kconfig.soc rename soc/{riscv => intel}/intel_niosv/niosv/linker.ld (100%) create mode 100644 soc/intel/intel_niosv/soc.yml rename soc/{arm64 => intel}/intel_socfpga/CMakeLists.txt (100%) create mode 100644 soc/intel/intel_socfpga/Kconfig create mode 100644 soc/intel/intel_socfpga/Kconfig.defconfig create mode 100644 soc/intel/intel_socfpga/Kconfig.soc rename soc/{arm64 => intel}/intel_socfpga/agilex/CMakeLists.txt (100%) create mode 100644 soc/intel/intel_socfpga/agilex/Kconfig rename soc/{arm64 => intel}/intel_socfpga/agilex/Kconfig.defconfig.agilex (77%) create mode 100644 soc/intel/intel_socfpga/agilex/Kconfig.defconfig.series create mode 100644 soc/intel/intel_socfpga/agilex/Kconfig.soc rename soc/{arm64 => intel}/intel_socfpga/agilex/mmu_regions.c (100%) rename soc/{arm64 => intel}/intel_socfpga/agilex5/CMakeLists.txt (100%) create mode 100644 soc/intel/intel_socfpga/agilex5/Kconfig rename soc/{arm64 => intel}/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 (77%) create mode 100644 soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.series create mode 100644 soc/intel/intel_socfpga/agilex5/Kconfig.soc rename soc/{arm64 => intel}/intel_socfpga/agilex5/mmu_regions.c (100%) rename soc/{arm64 => intel}/intel_socfpga/common/CMakeLists.txt (100%) rename soc/{arm64 => intel}/intel_socfpga/common/socfpga_handoff.h (100%) rename soc/{arm64 => intel}/intel_socfpga/common/socfpga_system_manager.h (100%) create mode 100644 soc/intel/intel_socfpga/soc.yml create mode 100644 soc/intel/intel_socfpga_std/CMakeLists.txt create mode 100644 soc/intel/intel_socfpga_std/Kconfig create mode 100644 soc/intel/intel_socfpga_std/Kconfig.defconfig create mode 100644 soc/intel/intel_socfpga_std/Kconfig.soc create mode 100644 soc/intel/intel_socfpga_std/cyclonev/CMakeLists.txt create mode 100644 soc/intel/intel_socfpga_std/cyclonev/Kconfig create mode 100644 soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev create mode 100644 soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.series create mode 100644 soc/intel/intel_socfpga_std/cyclonev/Kconfig.soc rename soc/{arm => intel}/intel_socfpga_std/cyclonev/soc.c (100%) rename soc/{arm => intel}/intel_socfpga_std/cyclonev/soc.h (100%) create mode 100644 soc/intel/intel_socfpga_std/soc.yml create mode 100644 soc/intel/lakemont/CMakeLists.txt create mode 100644 soc/intel/lakemont/Kconfig create mode 100644 soc/intel/lakemont/Kconfig.defconfig create mode 100644 soc/intel/lakemont/Kconfig.soc rename soc/{x86/atom => intel/lakemont}/linker.ld (100%) rename soc/{x86 => intel}/lakemont/soc.h (100%) create mode 100644 soc/intel/lakemont/soc.yml create mode 100644 soc/intel/raptor_lake/CMakeLists.txt create mode 100644 soc/intel/raptor_lake/Kconfig create mode 100644 soc/intel/raptor_lake/Kconfig.defconfig create mode 100644 soc/intel/raptor_lake/Kconfig.soc rename soc/{x86 => intel}/raptor_lake/doc/supported_features.txt (100%) rename soc/{x86 => intel}/raptor_lake/linker.ld (100%) rename soc/{x86 => intel}/raptor_lake/soc.h (100%) create mode 100644 soc/intel/raptor_lake/soc.yml rename soc/{x86 => intel}/raptor_lake/soc_gpio.h (100%) rename soc/{riscv/ite_ec => ite/ec}/CMakeLists.txt (100%) create mode 100644 soc/ite/ec/Kconfig create mode 100644 soc/ite/ec/Kconfig.defconfig create mode 100644 soc/ite/ec/Kconfig.soc rename soc/{riscv/ite_ec => ite/ec}/common/CMakeLists.txt (100%) rename soc/{riscv/ite_ec => ite/ec}/common/check_regs.c (100%) rename soc/{riscv/ite_ec => ite/ec}/common/chip_chipregs.h (100%) rename soc/{riscv/ite_ec => ite/ec}/common/pinctrl_soc.h (100%) rename soc/{riscv/ite_ec => ite/ec}/common/policy.c (100%) rename soc/{riscv/ite_ec => ite/ec}/common/power.c (100%) rename soc/{riscv/ite_ec => ite/ec}/common/soc_common.h (100%) rename soc/{riscv/ite_ec => ite/ec}/common/soc_common_irq.c (100%) rename soc/{riscv/ite_ec => ite/ec}/common/soc_dt.h (100%) rename soc/{riscv/ite_ec => ite/ec}/common/soc_espi.h (100%) rename soc/{riscv/ite_ec => ite/ec}/common/soc_irq.S (100%) rename soc/{riscv/ite_ec => ite/ec}/common/vector.S (100%) create mode 100644 soc/ite/ec/it8xxx2/CMakeLists.txt create mode 100644 soc/ite/ec/it8xxx2/Kconfig rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/Kconfig.defconfig.it81202bx (83%) rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/Kconfig.defconfig.it81202cx (83%) rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/Kconfig.defconfig.it81302bx (83%) rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/Kconfig.defconfig.it81302cx (83%) rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/Kconfig.defconfig.it82002aw (83%) rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/Kconfig.defconfig.it82202ax (83%) create mode 100644 soc/ite/ec/it8xxx2/Kconfig.defconfig.series create mode 100644 soc/ite/ec/it8xxx2/Kconfig.soc rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/__arithmetic.S (100%) rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/ilm.c (100%) rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/ilm.h (100%) rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/linker.ld (100%) rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/soc.c (100%) rename soc/{riscv/ite_ec => ite/ec}/it8xxx2/soc.h (100%) create mode 100644 soc/ite/ec/soc.yml create mode 100644 soc/litex/litex_vexriscv/CMakeLists.txt create mode 100644 soc/litex/litex_vexriscv/Kconfig create mode 100644 soc/litex/litex_vexriscv/Kconfig.defconfig create mode 100644 soc/litex/litex_vexriscv/Kconfig.soc rename soc/{riscv => litex}/litex_vexriscv/soc.h (100%) create mode 100644 soc/litex/litex_vexriscv/soc.yml rename soc/{riscv => lowrisc}/opentitan/CMakeLists.txt (100%) create mode 100644 soc/lowrisc/opentitan/Kconfig create mode 100644 soc/lowrisc/opentitan/Kconfig.defconfig create mode 100644 soc/lowrisc/opentitan/Kconfig.soc rename soc/{riscv => lowrisc}/opentitan/rom_header.S (100%) rename soc/{riscv => lowrisc}/opentitan/rom_header.ld (100%) rename soc/{riscv => lowrisc}/opentitan/soc.c (100%) create mode 100644 soc/lowrisc/opentitan/soc.yml rename soc/{arm/microchip_mec => microchip/mec}/CMakeLists.txt (100%) create mode 100644 soc/microchip/mec/Kconfig create mode 100644 soc/microchip/mec/Kconfig.defconfig create mode 100644 soc/microchip/mec/Kconfig.soc create mode 100644 soc/microchip/mec/common/CMakeLists.txt rename soc/{arm/microchip_mec => microchip/mec}/common/pinctrl_soc.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_acpi_ec.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_adc.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_global_cfg.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_gpio.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_kbc.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_keyscan.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_peci.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_ps2.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_pwm.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_tach.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_tfdp.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_timers.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_uart.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_vci.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/reg/mec_wdt.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/soc_dt.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/soc_espi_channels.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/soc_gpio.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/soc_i2c.c (99%) rename soc/{arm/microchip_mec => microchip/mec}/common/soc_i2c.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/soc_pcr.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/soc_pins.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/common/spigen/mec_spi_gen.py (99%) create mode 100644 soc/microchip/mec/mec15xx/CMakeLists.txt create mode 100644 soc/microchip/mec/mec15xx/Kconfig rename soc/{arm/microchip_mec/mec1501 => microchip/mec/mec15xx}/Kconfig.defconfig.mec1501hsz (88%) create mode 100644 soc/microchip/mec/mec15xx/Kconfig.defconfig.series create mode 100644 soc/microchip/mec/mec15xx/Kconfig.soc rename soc/{arm/microchip_mec/mec1501 => microchip/mec/mec15xx}/device_power.c (100%) rename soc/{arm/microchip_mec/mec1501 => microchip/mec/mec15xx}/device_power.h (100%) rename soc/{arm/microchip_mec/mec1501 => microchip/mec/mec15xx}/power.c (100%) rename soc/{arm/microchip_mec/mec1501 => microchip/mec/mec15xx}/soc.c (100%) rename soc/{arm/microchip_mec/mec1501 => microchip/mec/mec15xx}/soc.h (100%) rename soc/{arm/microchip_mec/mec1501 => microchip/mec/mec15xx}/soc_espi_saf_v1.h (100%) rename soc/{arm/microchip_mec/mec1501 => microchip/mec/mec15xx}/timing.c (100%) create mode 100644 soc/microchip/mec/mec172x/CMakeLists.txt create mode 100644 soc/microchip/mec/mec172x/Kconfig rename soc/{arm/microchip_mec => microchip/mec}/mec172x/Kconfig.defconfig.mec172xnlj (89%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/Kconfig.defconfig.mec172xnsz (84%) create mode 100644 soc/microchip/mec/mec172x/Kconfig.defconfig.series create mode 100644 soc/microchip/mec/mec172x/Kconfig.soc rename soc/{arm/microchip_mec => microchip/mec}/mec172x/device_power.c (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/device_power.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/power.c (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/gpio_pkg_lj.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/gpio_pkg_sz.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_defs.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_ecia.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_ecs.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_emi.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_espi_iom.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_espi_saf.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_espi_vw.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_gpio.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_i2c_smb.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_p80bd.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_pcr.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_qspi.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/reg/mec172x_vbat.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/soc.c (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/soc.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/soc_espi_saf_v2.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/soc_power_debug.h (100%) rename soc/{arm/microchip_mec => microchip/mec}/mec172x/timing.c (100%) create mode 100644 soc/microchip/mec/soc.yml rename soc/{riscv/gd_gd32 => microchip/miv}/CMakeLists.txt (100%) create mode 100644 soc/microchip/miv/Kconfig create mode 100644 soc/microchip/miv/Kconfig.defconfig create mode 100644 soc/microchip/miv/Kconfig.soc create mode 100644 soc/microchip/miv/miv/CMakeLists.txt create mode 100644 soc/microchip/miv/miv/Kconfig create mode 100644 soc/microchip/miv/miv/Kconfig.defconfig create mode 100644 soc/microchip/miv/miv/Kconfig.soc rename soc/{riscv/microchip_miv/miv => microchip/miv/polarfire}/CMakeLists.txt (100%) create mode 100644 soc/microchip/miv/polarfire/Kconfig create mode 100644 soc/microchip/miv/polarfire/Kconfig.defconfig create mode 100644 soc/microchip/miv/polarfire/Kconfig.soc create mode 100644 soc/microchip/miv/soc.yml delete mode 100644 soc/mips/CMakeLists.txt delete mode 100644 soc/mips/qemu_malta/CMakeLists.txt delete mode 100644 soc/mips/qemu_malta/Kconfig.defconfig delete mode 100644 soc/mips/qemu_malta/Kconfig.soc create mode 100644 soc/native/inf_clock/CMakeLists.txt create mode 100644 soc/native/inf_clock/Kconfig create mode 100644 soc/native/inf_clock/Kconfig.soc rename soc/{posix => native}/inf_clock/native_tasks.c (100%) rename soc/{posix => native}/inf_clock/posix_board_if.h (100%) rename soc/{posix => native}/inf_clock/posix_native_task.h (100%) rename soc/{posix => native}/inf_clock/posix_soc.h (100%) rename soc/{posix => native}/inf_clock/soc.c (100%) rename soc/{posix => native}/inf_clock/soc.h (100%) create mode 100644 soc/native/inf_clock/soc.yml rename soc/{posix => native}/inf_clock/soc_irq.h (100%) rename soc/{riscv => }/neorv32/CMakeLists.txt (100%) create mode 100644 soc/neorv32/Kconfig create mode 100644 soc/neorv32/Kconfig.defconfig create mode 100644 soc/neorv32/Kconfig.soc rename soc/{riscv => }/neorv32/linker.ld (100%) rename soc/{riscv => }/neorv32/reset.S (100%) rename soc/{riscv => }/neorv32/soc.c (100%) rename soc/{riscv => }/neorv32/soc.h (100%) create mode 100644 soc/neorv32/soc.yml rename soc/{riscv => }/neorv32/soc_irq.S (100%) delete mode 100644 soc/nios2/nios2-qemu/CMakeLists.txt delete mode 100644 soc/nios2/nios2-qemu/Kconfig.defconfig delete mode 100644 soc/nios2/nios2-qemu/Kconfig.soc delete mode 100644 soc/nios2/nios2f-zephyr/CMakeLists.txt delete mode 100644 soc/nios2/nios2f-zephyr/Kconfig.defconfig delete mode 100644 soc/nios2/nios2f-zephyr/Kconfig.soc create mode 100644 soc/nordic/CMakeLists.txt create mode 100644 soc/nordic/Kconfig create mode 100644 soc/nordic/Kconfig.defconfig create mode 100644 soc/nordic/Kconfig.soc create mode 100644 soc/nordic/common/CMakeLists.txt create mode 100644 soc/nordic/common/Kconfig create mode 100644 soc/nordic/common/Kconfig.defconfig rename soc/{common/nordic_nrf => nordic/common}/Kconfig.peripherals (100%) rename soc/{common/nordic_nrf => nordic/common}/pinctrl_soc.h (100%) rename soc/{arm/nordic_nrf => nordic}/common/poweroff.c (100%) rename soc/{arm/nordic_nrf => nordic}/common/soc_nrf_common.S (100%) rename soc/{arm/nordic_nrf => nordic}/common/soc_nrf_common.h (100%) rename soc/{arm/nordic_nrf => nordic}/common/soc_secure.c (100%) rename soc/{arm/nordic_nrf => nordic}/common/soc_secure.h (100%) create mode 100644 soc/nordic/common/vpr/CMakeLists.txt rename soc/{riscv/nordic_nrf => nordic}/common/vpr/Kconfig (100%) rename soc/{riscv/nordic_nrf => nordic}/common/vpr/Kconfig.defconfig (100%) rename soc/{riscv/nordic_nrf => nordic}/common/vpr/soc_context.h (100%) rename soc/{riscv/nordic_nrf => nordic}/common/vpr/soc_irq.S (100%) rename soc/{riscv/nordic_nrf => nordic}/common/vpr/soc_irq.c (100%) rename soc/{riscv/nordic_nrf => nordic}/common/vpr/soc_isr_stacking.h (100%) rename soc/{riscv/nordic_nrf => nordic}/common/vpr/soc_offsets.h (100%) rename soc/{riscv/nordic_nrf => nordic}/common/vpr/vector.S (100%) create mode 100644 soc/nordic/nrf51/CMakeLists.txt create mode 100644 soc/nordic/nrf51/Kconfig create mode 100644 soc/nordic/nrf51/Kconfig.defconfig create mode 100644 soc/nordic/nrf51/Kconfig.soc rename soc/{arm/nordic_nrf => nordic}/nrf51/soc.c (100%) rename soc/{arm/nordic_nrf => nordic}/nrf51/soc.h (100%) create mode 100644 soc/nordic/nrf52/CMakeLists.txt create mode 100644 soc/nordic/nrf52/Kconfig create mode 100644 soc/nordic/nrf52/Kconfig.defconfig rename soc/{arm/nordic_nrf => nordic}/nrf52/Kconfig.defconfig.nrf52805_CAAA (84%) rename soc/{arm/nordic_nrf => nordic}/nrf52/Kconfig.defconfig.nrf52810_QFAA (84%) rename soc/{arm/nordic_nrf => nordic}/nrf52/Kconfig.defconfig.nrf52811_QFAA (84%) rename soc/{arm/nordic_nrf => nordic}/nrf52/Kconfig.defconfig.nrf52820_QDAA (81%) rename soc/{arm/nordic_nrf => nordic}/nrf52/Kconfig.defconfig.nrf52832_CIAA (87%) rename soc/{arm/nordic_nrf => nordic}/nrf52/Kconfig.defconfig.nrf52832_QFAA (87%) rename soc/{arm/nordic_nrf => nordic}/nrf52/Kconfig.defconfig.nrf52832_QFAB (87%) rename soc/{arm/nordic_nrf => nordic}/nrf52/Kconfig.defconfig.nrf52833_QDAA (81%) rename soc/{arm/nordic_nrf => nordic}/nrf52/Kconfig.defconfig.nrf52833_QIAA (81%) rename soc/{arm/nordic_nrf => nordic}/nrf52/Kconfig.defconfig.nrf52840_QFAA (84%) rename soc/{arm/nordic_nrf => nordic}/nrf52/Kconfig.defconfig.nrf52840_QIAA (84%) create mode 100644 soc/nordic/nrf52/Kconfig.soc rename soc/{arm/nordic_nrf => nordic}/nrf52/soc.c (100%) rename soc/{arm/nordic_nrf => nordic}/nrf52/soc.h (100%) create mode 100644 soc/nordic/nrf53/CMakeLists.txt create mode 100644 soc/nordic/nrf53/Kconfig create mode 100644 soc/nordic/nrf53/Kconfig.defconfig rename soc/{arm/nordic_nrf => nordic}/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA (91%) rename soc/{arm/nordic_nrf => nordic}/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA (90%) create mode 100644 soc/nordic/nrf53/Kconfig.soc rename soc/{arm/nordic_nrf => nordic}/nrf53/Kconfig.sync_rtc (100%) rename soc/{arm/nordic_nrf => nordic}/nrf53/Kconfig.sync_rtc_ipm (100%) rename soc/{arm/nordic_nrf => nordic}/nrf53/soc.c (100%) rename soc/{arm/nordic_nrf => nordic}/nrf53/soc.h (100%) rename soc/{arm/nordic_nrf => nordic}/nrf53/soc_cpu_idle.h (100%) rename soc/{arm/nordic_nrf => nordic}/nrf53/sync_rtc.c (100%) create mode 100644 soc/nordic/nrf54h/CMakeLists.txt create mode 100644 soc/nordic/nrf54h/Kconfig create mode 100644 soc/nordic/nrf54h/Kconfig.defconfig create mode 100644 soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp rename soc/{riscv/nordic_nrf => nordic}/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr (83%) create mode 100644 soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad create mode 100644 soc/nordic/nrf54h/Kconfig.soc rename soc/{arm/nordic_nrf => nordic}/nrf54h/align.ld (100%) rename soc/{arm/nordic_nrf => nordic}/nrf54h/soc.c (100%) rename soc/{arm/nordic_nrf => nordic}/nrf54h/soc.h (100%) create mode 100644 soc/nordic/nrf54l/CMakeLists.txt create mode 100644 soc/nordic/nrf54l/Kconfig create mode 100644 soc/nordic/nrf54l/Kconfig.defconfig rename soc/{arm/nordic_nrf => nordic}/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp (84%) create mode 100644 soc/nordic/nrf54l/Kconfig.soc rename soc/{arm/nordic_nrf => nordic}/nrf54l/soc.c (100%) rename soc/{arm/nordic_nrf => nordic}/nrf54l/soc.h (100%) create mode 100644 soc/nordic/nrf91/CMakeLists.txt create mode 100644 soc/nordic/nrf91/Kconfig create mode 100644 soc/nordic/nrf91/Kconfig.defconfig rename soc/{arm/nordic_nrf => nordic}/nrf91/Kconfig.defconfig.nrf9131_LACA (84%) rename soc/{arm/nordic_nrf => nordic}/nrf91/Kconfig.defconfig.nrf9151_LACA (84%) rename soc/{arm/nordic_nrf => nordic}/nrf91/Kconfig.defconfig.nrf9160_SICA (84%) rename soc/{arm/nordic_nrf => nordic}/nrf91/Kconfig.defconfig.nrf9161_LACA (84%) create mode 100644 soc/nordic/nrf91/Kconfig.soc rename soc/{arm/nordic_nrf => nordic}/nrf91/soc.c (100%) rename soc/{arm/nordic_nrf => nordic}/nrf91/soc.h (100%) create mode 100644 soc/nordic/soc.yml rename soc/{arm/nordic_nrf => nordic}/timing.c (100%) rename soc/{arm/nordic_nrf => nordic}/validate_base_addresses.c (99%) rename soc/{arm/nordic_nrf => nordic}/validate_enabled_instances.c (100%) rename soc/{arm/nordic_nrf => nordic}/validate_rram_partitions.c (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/CMakeLists.txt (100%) create mode 100644 soc/nuvoton/npcx/Kconfig create mode 100644 soc/nuvoton/npcx/Kconfig.defconfig create mode 100644 soc/nuvoton/npcx/Kconfig.soc create mode 100644 soc/nuvoton/npcx/common/CMakeLists.txt rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/ecst/ecst.py (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/ecst/ecst_args.py (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/pinctrl_soc.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/power.c (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/reg/reg_access.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/reg/reg_def.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/registers.c (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/scfg.c (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/soc_clock.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/soc_dbg.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/soc_dt.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/soc_espi.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/soc_espi_taf.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/soc_gpio.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/soc_host.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/soc_miwu.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/soc_pins.h (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/common/soc_power.h (100%) create mode 100644 soc/nuvoton/npcx/npcx4/CMakeLists.txt create mode 100644 soc/nuvoton/npcx/npcx4/Kconfig create mode 100644 soc/nuvoton/npcx/npcx4/Kconfig.defconfig create mode 100644 soc/nuvoton/npcx/npcx4/Kconfig.soc rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/npcx4/soc.c (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/npcx4/soc.h (100%) create mode 100644 soc/nuvoton/npcx/npcx7/CMakeLists.txt create mode 100644 soc/nuvoton/npcx/npcx7/Kconfig create mode 100644 soc/nuvoton/npcx/npcx7/Kconfig.defconfig create mode 100644 soc/nuvoton/npcx/npcx7/Kconfig.soc rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/npcx7/mpu_regions.c (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/npcx7/soc.c (100%) rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/npcx7/soc.h (100%) create mode 100644 soc/nuvoton/npcx/npcx9/CMakeLists.txt create mode 100644 soc/nuvoton/npcx/npcx9/Kconfig create mode 100644 soc/nuvoton/npcx/npcx9/Kconfig.defconfig create mode 100644 soc/nuvoton/npcx/npcx9/Kconfig.soc rename soc/{arm/nuvoton_npcx => nuvoton/npcx}/npcx9/soc.h (100%) create mode 100644 soc/nuvoton/npcx/soc.yml rename soc/{arm/nuvoton_numaker => nuvoton/numaker}/CMakeLists.txt (100%) create mode 100644 soc/nuvoton/numaker/Kconfig create mode 100644 soc/nuvoton/numaker/Kconfig.defconfig create mode 100644 soc/nuvoton/numaker/Kconfig.soc rename soc/{arm/nuvoton_numaker => nuvoton/numaker}/common/pinctrl_soc.h (100%) create mode 100644 soc/nuvoton/numaker/m46x/CMakeLists.txt create mode 100644 soc/nuvoton/numaker/m46x/Kconfig create mode 100644 soc/nuvoton/numaker/m46x/Kconfig.defconfig rename soc/{arm/nuvoton_numaker => nuvoton/numaker}/m46x/Kconfig.defconfig.m467 (100%) create mode 100644 soc/nuvoton/numaker/m46x/Kconfig.soc rename soc/{arm/nuvoton_numaker => nuvoton/numaker}/m46x/soc.c (100%) rename soc/{arm/nuvoton_numaker => nuvoton/numaker}/m46x/soc.h (100%) create mode 100644 soc/nuvoton/numaker/soc.yml rename soc/{arm/nuvoton_numicro => nuvoton/numicro}/CMakeLists.txt (100%) create mode 100644 soc/nuvoton/numicro/Kconfig create mode 100644 soc/nuvoton/numicro/Kconfig.defconfig create mode 100644 soc/nuvoton/numicro/Kconfig.soc rename soc/{arm/nuvoton_numicro => nuvoton/numicro}/common/pinctrl_soc.h (100%) create mode 100644 soc/nuvoton/numicro/m48x/CMakeLists.txt create mode 100644 soc/nuvoton/numicro/m48x/Kconfig create mode 100644 soc/nuvoton/numicro/m48x/Kconfig.defconfig rename soc/{arm/nuvoton_numicro => nuvoton/numicro}/m48x/Kconfig.defconfig.m487 (100%) create mode 100644 soc/nuvoton/numicro/m48x/Kconfig.soc rename soc/{arm/nuvoton_numicro => nuvoton/numicro}/m48x/soc.c (100%) rename soc/{arm/nuvoton_numicro => nuvoton/numicro}/m48x/soc.h (100%) create mode 100644 soc/nuvoton/numicro/soc.yml create mode 100644 soc/nxp/imx/CMakeLists.txt create mode 100644 soc/nxp/imx/Kconfig create mode 100644 soc/nxp/imx/Kconfig.defconfig create mode 100644 soc/nxp/imx/Kconfig.soc create mode 100644 soc/nxp/imx/imx6sx/CMakeLists.txt create mode 100644 soc/nxp/imx/imx6sx/Kconfig create mode 100644 soc/nxp/imx/imx6sx/Kconfig.defconfig create mode 100644 soc/nxp/imx/imx6sx/Kconfig.defconfig.mcimx6x_m4 create mode 100644 soc/nxp/imx/imx6sx/Kconfig.soc rename soc/{arm/nxp_imx/mcimx6x_m4 => nxp/imx/imx6sx}/pinctrl_soc.h (100%) rename soc/{arm/nxp_imx/mcimx6x_m4 => nxp/imx/imx6sx}/soc.c (100%) rename soc/{arm/nxp_imx/mcimx6x_m4 => nxp/imx/imx6sx}/soc.h (100%) rename soc/{arm/nxp_imx/mcimx6x_m4 => nxp/imx/imx6sx}/soc_clk_freq.c (100%) rename soc/{arm/nxp_imx/mcimx6x_m4 => nxp/imx/imx6sx}/soc_clk_freq.h (100%) create mode 100644 soc/nxp/imx/imx7d/CMakeLists.txt create mode 100644 soc/nxp/imx/imx7d/Kconfig create mode 100644 soc/nxp/imx/imx7d/Kconfig.defconfig create mode 100644 soc/nxp/imx/imx7d/Kconfig.defconfig.mcimx7d_m4 create mode 100644 soc/nxp/imx/imx7d/Kconfig.soc rename soc/{arm/nxp_imx/mcimx7_m4 => nxp/imx/imx7d}/pinctrl_soc.h (100%) rename soc/{arm/nxp_imx/mcimx7_m4 => nxp/imx/imx7d}/soc.c (100%) rename soc/{arm/nxp_imx/mcimx7_m4 => nxp/imx/imx7d}/soc.h (100%) rename soc/{arm/nxp_imx/mcimx7_m4 => nxp/imx/imx7d}/soc_clk_freq.c (100%) rename soc/{arm/nxp_imx/mcimx7_m4 => nxp/imx/imx7d}/soc_clk_freq.h (100%) create mode 100644 soc/nxp/imx/imx8/CMakeLists.txt create mode 100644 soc/nxp/imx/imx8/Kconfig create mode 100644 soc/nxp/imx/imx8/Kconfig.defconfig create mode 100644 soc/nxp/imx/imx8/Kconfig.soc create mode 100644 soc/nxp/imx/imx8/adsp/CMakeLists.txt rename soc/{xtensa/nxp_adsp/imx8/include => nxp/imx/imx8/adsp}/_soc_inthandlers.h (100%) rename soc/{xtensa/nxp_adsp/common => nxp/imx/imx8/adsp}/include/adsp/cache.h (100%) rename soc/{xtensa/nxp_adsp/common => nxp/imx/imx8/adsp}/include/adsp/io.h (100%) rename soc/{xtensa/nxp_adsp/common => nxp/imx/imx8/adsp}/include/soc.h (100%) rename soc/{xtensa/nxp_adsp/imx8 => nxp/imx/imx8/adsp}/linker.ld (100%) rename soc/{xtensa/nxp_adsp/imx8/include => nxp/imx/imx8/adsp}/memory.h (100%) rename soc/{xtensa/nxp_adsp/imx8 => nxp/imx/imx8/adsp}/pinctrl_soc.h (100%) create mode 100644 soc/nxp/imx/imx8m/CMakeLists.txt create mode 100644 soc/nxp/imx/imx8m/Kconfig create mode 100644 soc/nxp/imx/imx8m/Kconfig.defconfig create mode 100644 soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 create mode 100644 soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp create mode 100644 soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.a53 create mode 100644 soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.m4 create mode 100644 soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn.a53 create mode 100644 soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mp.a53 create mode 100644 soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4 create mode 100644 soc/nxp/imx/imx8m/Kconfig.soc rename soc/{arm64/nxp_imx/mimx8m => nxp/imx/imx8m/a53}/mmu_regions.c (100%) rename soc/{arm64/nxp_imx/mimx8m => nxp/imx/imx8m/a53}/pinctrl_soc.h (100%) create mode 100644 soc/nxp/imx/imx8m/adsp/CMakeLists.txt rename soc/{xtensa/nxp_adsp/imx8m/include => nxp/imx/imx8m/adsp}/_soc_inthandlers.h (100%) create mode 100644 soc/nxp/imx/imx8m/adsp/include/adsp/cache.h create mode 100644 soc/nxp/imx/imx8m/adsp/include/adsp/io.h create mode 100644 soc/nxp/imx/imx8m/adsp/include/soc.h rename soc/{xtensa/nxp_adsp/imx8m => nxp/imx/imx8m/adsp}/linker.ld (100%) rename soc/{xtensa/nxp_adsp/imx8m/include => nxp/imx/imx8m/adsp}/memory.h (100%) rename soc/{xtensa/nxp_adsp/imx8m/include => nxp/imx/imx8m/adsp}/pinctrl_soc.h (100%) create mode 100644 soc/nxp/imx/imx8m/m4_mini/CMakeLists.txt rename soc/{arm/nxp_imx/mimx8mm6_m4 => nxp/imx/imx8m/m4_mini}/linker.ld (100%) rename soc/{arm/nxp_imx/mimx8mm6_m4 => nxp/imx/imx8m/m4_mini}/pinctrl_soc.h (100%) rename soc/{arm/nxp_imx/mimx8mm6_m4 => nxp/imx/imx8m/m4_mini}/soc.c (100%) rename soc/{arm/nxp_imx/mimx8mm6_m4 => nxp/imx/imx8m/m4_mini}/soc.h (100%) create mode 100644 soc/nxp/imx/imx8m/m4_quad/CMakeLists.txt rename soc/{arm/nxp_imx/mimx8mq6_m4 => nxp/imx/imx8m/m4_quad}/pinctrl_soc.h (100%) rename soc/{arm/nxp_imx/mimx8mq6_m4 => nxp/imx/imx8m/m4_quad}/soc.c (100%) rename soc/{arm/nxp_imx/mimx8mq6_m4 => nxp/imx/imx8m/m4_quad}/soc.h (100%) create mode 100644 soc/nxp/imx/imx8m/m7/CMakeLists.txt rename soc/{arm/nxp_imx/mimx8ml8_m7 => nxp/imx/imx8m/m7}/linker.ld (100%) rename soc/{arm/nxp_imx/mimx8ml8_m7 => nxp/imx/imx8m/m7}/mpu_regions.c (100%) rename soc/{arm/nxp_imx/mimx8ml8_m7 => nxp/imx/imx8m/m7}/pinctrl_soc.h (100%) rename soc/{arm/nxp_imx/mimx8ml8_m7 => nxp/imx/imx8m/m7}/soc.c (100%) rename soc/{arm/nxp_imx/mimx8ml8_m7 => nxp/imx/imx8m/m7}/soc.h (100%) create mode 100644 soc/nxp/imx/imx8ulp/CMakeLists.txt create mode 100644 soc/nxp/imx/imx8ulp/Kconfig create mode 100644 soc/nxp/imx/imx8ulp/Kconfig.defconfig create mode 100644 soc/nxp/imx/imx8ulp/Kconfig.soc create mode 100644 soc/nxp/imx/imx8ulp/adsp/CMakeLists.txt rename soc/{xtensa/nxp_adsp/imx8ulp/include => nxp/imx/imx8ulp/adsp}/_soc_inthandlers.h (100%) create mode 100644 soc/nxp/imx/imx8ulp/adsp/include/adsp/cache.h create mode 100644 soc/nxp/imx/imx8ulp/adsp/include/adsp/io.h create mode 100644 soc/nxp/imx/imx8ulp/adsp/include/soc.h rename soc/{xtensa/nxp_adsp/imx8ulp => nxp/imx/imx8ulp/adsp}/linker.ld (100%) rename soc/{xtensa/nxp_adsp/imx8ulp/include => nxp/imx/imx8ulp/adsp}/memory.h (100%) create mode 100644 soc/nxp/imx/imx8x/CMakeLists.txt create mode 100644 soc/nxp/imx/imx8x/Kconfig create mode 100644 soc/nxp/imx/imx8x/Kconfig.defconfig create mode 100644 soc/nxp/imx/imx8x/Kconfig.soc create mode 100644 soc/nxp/imx/imx8x/adsp/CMakeLists.txt create mode 100644 soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h create mode 100644 soc/nxp/imx/imx8x/adsp/include/adsp/cache.h create mode 100644 soc/nxp/imx/imx8x/adsp/include/adsp/io.h create mode 100644 soc/nxp/imx/imx8x/adsp/include/soc.h create mode 100644 soc/nxp/imx/imx8x/adsp/linker.ld create mode 100644 soc/nxp/imx/imx8x/adsp/memory.h create mode 100644 soc/nxp/imx/imx8x/adsp/pinctrl_soc.h create mode 100644 soc/nxp/imx/imx9/CMakeLists.txt create mode 100644 soc/nxp/imx/imx9/Kconfig create mode 100644 soc/nxp/imx/imx9/Kconfig.defconfig create mode 100644 soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.a55 create mode 100644 soc/nxp/imx/imx9/Kconfig.soc rename soc/{arm64/nxp_imx/mimx9 => nxp/imx/imx9/a55}/linker.ld (100%) rename soc/{arm64/nxp_imx/mimx9 => nxp/imx/imx9/a55}/mmu_regions.c (100%) rename soc/{arm64/nxp_imx/mimx9 => nxp/imx/imx9}/pinctrl_soc.h (100%) create mode 100644 soc/nxp/imx/soc.yml create mode 100644 soc/nxp/imxrt/CMakeLists.txt create mode 100644 soc/nxp/imxrt/Kconfig create mode 100644 soc/nxp/imxrt/Kconfig.defconfig create mode 100644 soc/nxp/imxrt/Kconfig.soc create mode 100644 soc/nxp/imxrt/boot_header.ld rename soc/{arm/nxp_imx/rt => nxp/imxrt}/flexspi_nor_config.h (99%) create mode 100644 soc/nxp/imxrt/imxrt10xx/CMakeLists.txt create mode 100644 soc/nxp/imxrt/imxrt10xx/Kconfig create mode 100644 soc/nxp/imxrt/imxrt10xx/Kconfig.defconfig create mode 100644 soc/nxp/imxrt/imxrt10xx/Kconfig.soc rename soc/{arm/nxp_imx/rt/flexspi_rt10xx.c => nxp/imxrt/imxrt10xx/flexspi.c} (100%) create mode 100644 soc/nxp/imxrt/imxrt10xx/linker.ld rename soc/{arm/nxp_imx/rt => nxp/imxrt/imxrt10xx}/lpm_rt1064.c (96%) rename soc/{arm/nxp_imx/rt/pinctrl_rt10xx.h => nxp/imxrt/imxrt10xx/pinctrl_soc.h} (100%) create mode 100644 soc/nxp/imxrt/imxrt10xx/power.c rename soc/{arm/nxp_imx/rt/power_rt10xx.h => nxp/imxrt/imxrt10xx/power.h} (100%) create mode 100644 soc/nxp/imxrt/imxrt10xx/soc.c create mode 100644 soc/nxp/imxrt/imxrt10xx/soc.h create mode 100644 soc/nxp/imxrt/imxrt11xx/CMakeLists.txt create mode 100644 soc/nxp/imxrt/imxrt11xx/Kconfig create mode 100644 soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig create mode 100644 soc/nxp/imxrt/imxrt11xx/Kconfig.soc rename soc/{arm/nxp_imx/rt/flexspi_rt11xx.c => nxp/imxrt/imxrt11xx/flexspi.c} (100%) create mode 100644 soc/nxp/imxrt/imxrt11xx/linker.ld rename soc/{arm/nxp_imx/rt/pinctrl_rt11xx.h => nxp/imxrt/imxrt11xx/pinctrl_soc.h} (100%) rename soc/{arm/nxp_imx/rt/power_rt11xx.c => nxp/imxrt/imxrt11xx/power.c} (100%) rename soc/{arm/nxp_imx/rt/power_rt11xx.h => nxp/imxrt/imxrt11xx/power.h} (100%) create mode 100644 soc/nxp/imxrt/imxrt11xx/soc.c create mode 100644 soc/nxp/imxrt/imxrt11xx/soc.h create mode 100644 soc/nxp/imxrt/imxrt5xx/CMakeLists.txt create mode 100644 soc/nxp/imxrt/imxrt5xx/Kconfig create mode 100644 soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig create mode 100644 soc/nxp/imxrt/imxrt5xx/Kconfig.soc create mode 100644 soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt rename soc/{arm/nxp_imx/rt5xx => nxp/imxrt/imxrt5xx/cm33}/flash_clock_setup.c (100%) rename soc/{arm/nxp_imx/rt5xx => nxp/imxrt/imxrt5xx/cm33}/flash_clock_setup.h (100%) rename soc/{arm/nxp_imx/rt5xx => nxp/imxrt/imxrt5xx/cm33}/linker.ld (100%) rename soc/{arm/nxp_imx/rt5xx => nxp/imxrt/imxrt5xx/cm33}/pinctrl_soc.h (100%) rename soc/{arm/nxp_imx/rt5xx => nxp/imxrt/imxrt5xx/cm33}/power.c (100%) rename soc/{arm/nxp_imx/rt5xx => nxp/imxrt/imxrt5xx/cm33}/poweroff.c (100%) create mode 100644 soc/nxp/imxrt/imxrt5xx/cm33/soc.c rename soc/{arm/nxp_imx/rt5xx => nxp/imxrt/imxrt5xx/cm33}/soc.h (100%) rename soc/{arm/nxp_imx/rt5xx => nxp/imxrt/imxrt5xx/cm33}/usb.ld (100%) create mode 100644 soc/nxp/imxrt/imxrt5xx/f1/CMakeLists.txt rename soc/{xtensa/nxp_adsp/rt5xx => nxp/imxrt/imxrt5xx/f1}/include/_soc_inthandlers.h (100%) create mode 100644 soc/nxp/imxrt/imxrt5xx/f1/include/adsp/cache.h create mode 100644 soc/nxp/imxrt/imxrt5xx/f1/include/adsp/io.h create mode 100644 soc/nxp/imxrt/imxrt5xx/f1/include/soc.h rename soc/{xtensa/nxp_adsp/rt5xx => nxp/imxrt/imxrt5xx/f1}/include/soc/memory.h (100%) rename soc/{xtensa/nxp_adsp/rt5xx => nxp/imxrt/imxrt5xx/f1}/linker.ld (100%) create mode 100644 soc/nxp/imxrt/imxrt6xx/CMakeLists.txt create mode 100644 soc/nxp/imxrt/imxrt6xx/Kconfig create mode 100644 soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig create mode 100644 soc/nxp/imxrt/imxrt6xx/Kconfig.soc rename soc/{arm/nxp_imx/rt6xx => nxp/imxrt/imxrt6xx}/flash_clock_setup.c (100%) rename soc/{arm/nxp_imx/rt6xx => nxp/imxrt/imxrt6xx}/flash_clock_setup.h (100%) rename soc/{arm/nxp_imx/rt6xx => nxp/imxrt/imxrt6xx}/pinctrl_soc.h (100%) rename soc/{arm/nxp_imx/rt6xx => nxp/imxrt/imxrt6xx}/power.c (100%) create mode 100644 soc/nxp/imxrt/imxrt6xx/soc.c rename soc/{arm/nxp_imx/rt6xx => nxp/imxrt/imxrt6xx}/soc.h (100%) rename soc/{arm/nxp_imx/rt => nxp/imxrt}/mpu_regions.c (100%) create mode 100644 soc/nxp/imxrt/soc.yml rename soc/{arm/nxp_imx/rt6xx => nxp/imxrt}/usb.ld (91%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/CMakeLists.txt (100%) create mode 100644 soc/nxp/kinetis/Kconfig create mode 100644 soc/nxp/kinetis/Kconfig.defconfig create mode 100644 soc/nxp/kinetis/Kconfig.soc rename soc/{arm/nxp_kinetis => nxp/kinetis}/common/pinctrl_soc.h (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/flash_config.ld (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/flash_configuration.c (100%) create mode 100644 soc/nxp/kinetis/k2x/CMakeLists.txt create mode 100644 soc/nxp/kinetis/k2x/Kconfig create mode 100644 soc/nxp/kinetis/k2x/Kconfig.defconfig create mode 100644 soc/nxp/kinetis/k2x/Kconfig.soc rename soc/{arm/nxp_kinetis => nxp/kinetis}/k2x/nxp_mpu_regions.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/k2x/soc.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/k2x/soc.h (100%) create mode 100644 soc/nxp/kinetis/k6x/CMakeLists.txt create mode 100644 soc/nxp/kinetis/k6x/Kconfig create mode 100644 soc/nxp/kinetis/k6x/Kconfig.defconfig create mode 100644 soc/nxp/kinetis/k6x/Kconfig.soc rename soc/{arm/nxp_kinetis => nxp/kinetis}/k6x/README.txt (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/k6x/nxp_mpu_regions.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/k6x/soc.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/k6x/soc.h (100%) create mode 100644 soc/nxp/kinetis/k8x/CMakeLists.txt create mode 100644 soc/nxp/kinetis/k8x/Kconfig create mode 100644 soc/nxp/kinetis/k8x/Kconfig.defconfig create mode 100644 soc/nxp/kinetis/k8x/Kconfig.soc rename soc/{arm/nxp_kinetis => nxp/kinetis}/k8x/nxp_mpu_regions.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/k8x/soc.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/k8x/soc.h (100%) create mode 100644 soc/nxp/kinetis/ke1xf/CMakeLists.txt create mode 100644 soc/nxp/kinetis/ke1xf/Kconfig create mode 100644 soc/nxp/kinetis/ke1xf/Kconfig.defconfig create mode 100644 soc/nxp/kinetis/ke1xf/Kconfig.soc rename soc/{arm/nxp_kinetis => nxp/kinetis}/ke1xf/nxp_mpu_regions.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/ke1xf/power.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/ke1xf/soc.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/ke1xf/soc.h (100%) create mode 100644 soc/nxp/kinetis/kl2x/CMakeLists.txt create mode 100644 soc/nxp/kinetis/kl2x/Kconfig create mode 100644 soc/nxp/kinetis/kl2x/Kconfig.defconfig create mode 100644 soc/nxp/kinetis/kl2x/Kconfig.soc rename soc/{arm/nxp_kinetis => nxp/kinetis}/kl2x/soc.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/kl2x/soc.h (100%) create mode 100644 soc/nxp/kinetis/kv5x/CMakeLists.txt create mode 100644 soc/nxp/kinetis/kv5x/Kconfig create mode 100644 soc/nxp/kinetis/kv5x/Kconfig.defconfig create mode 100644 soc/nxp/kinetis/kv5x/Kconfig.soc rename soc/{arm/nxp_kinetis => nxp/kinetis}/kv5x/soc.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/kv5x/soc.h (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/kv5x/wdog.S (100%) create mode 100644 soc/nxp/kinetis/kwx/CMakeLists.txt create mode 100644 soc/nxp/kinetis/kwx/Kconfig create mode 100644 soc/nxp/kinetis/kwx/Kconfig.defconfig create mode 100644 soc/nxp/kinetis/kwx/Kconfig.soc rename soc/{arm/nxp_kinetis => nxp/kinetis}/kwx/soc.h (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/kwx/soc_kw2xd.c (100%) rename soc/{arm/nxp_kinetis => nxp/kinetis}/kwx/soc_kw4xz.c (100%) create mode 100644 soc/nxp/kinetis/soc.yml rename soc/{arm64/nxp_layerscape => nxp/layerscape}/CMakeLists.txt (100%) create mode 100644 soc/nxp/layerscape/Kconfig create mode 100644 soc/nxp/layerscape/Kconfig.defconfig create mode 100644 soc/nxp/layerscape/Kconfig.soc rename soc/{arm64/nxp_layerscape => nxp/layerscape}/ls1046a/CMakeLists.txt (100%) create mode 100644 soc/nxp/layerscape/ls1046a/Kconfig create mode 100644 soc/nxp/layerscape/ls1046a/Kconfig.defconfig create mode 100644 soc/nxp/layerscape/ls1046a/Kconfig.soc rename soc/{arm64/nxp_layerscape => nxp/layerscape}/ls1046a/mmu_regions.c (100%) create mode 100644 soc/nxp/layerscape/soc.yml rename soc/{arm/nxp_lpc => nxp/lpc}/CMakeLists.txt (100%) create mode 100644 soc/nxp/lpc/Kconfig create mode 100644 soc/nxp/lpc/Kconfig.defconfig create mode 100644 soc/nxp/lpc/Kconfig.soc create mode 100644 soc/nxp/lpc/lpc11u6x/CMakeLists.txt create mode 100644 soc/nxp/lpc/lpc11u6x/Kconfig create mode 100644 soc/nxp/lpc/lpc11u6x/Kconfig.defconfig create mode 100644 soc/nxp/lpc/lpc11u6x/Kconfig.soc rename soc/{arm/nxp_lpc => nxp/lpc}/lpc11u6x/iap.h (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc11u6x/pinctrl_soc.h (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc11u6x/soc.h (100%) create mode 100644 soc/nxp/lpc/lpc51u68/CMakeLists.txt create mode 100644 soc/nxp/lpc/lpc51u68/Kconfig create mode 100644 soc/nxp/lpc/lpc51u68/Kconfig.defconfig create mode 100644 soc/nxp/lpc/lpc51u68/Kconfig.soc rename soc/{arm/nxp_lpc => nxp/lpc}/lpc51u68/linker.ld (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc51u68/pinctrl_soc.h (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc51u68/soc.c (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc51u68/soc.h (100%) create mode 100644 soc/nxp/lpc/lpc54xxx/CMakeLists.txt create mode 100644 soc/nxp/lpc/lpc54xxx/Kconfig create mode 100644 soc/nxp/lpc/lpc54xxx/Kconfig.defconfig create mode 100644 soc/nxp/lpc/lpc54xxx/Kconfig.soc rename soc/{arm/nxp_lpc => nxp/lpc}/lpc54xxx/gcc/startup_LPC54114_cm4.S (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc54xxx/linker.ld (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc54xxx/pinctrl_soc.h (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc54xxx/soc.c (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc54xxx/soc.h (100%) create mode 100644 soc/nxp/lpc/lpc55xxx/CMakeLists.txt create mode 100644 soc/nxp/lpc/lpc55xxx/Kconfig create mode 100644 soc/nxp/lpc/lpc55xxx/Kconfig.defconfig create mode 100644 soc/nxp/lpc/lpc55xxx/Kconfig.soc rename soc/{arm/nxp_lpc => nxp/lpc}/lpc55xxx/linker.ld (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc55xxx/pinctrl_soc.h (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc55xxx/soc.c (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc55xxx/soc.h (100%) rename soc/{arm/nxp_lpc => nxp/lpc}/lpc55xxx/usb.ld (100%) create mode 100644 soc/nxp/lpc/soc.yml rename soc/{arm/nxp_s32 => nxp/s32}/CMakeLists.txt (100%) create mode 100644 soc/nxp/s32/Kconfig create mode 100644 soc/nxp/s32/Kconfig.defconfig create mode 100644 soc/nxp/s32/Kconfig.soc create mode 100644 soc/nxp/s32/common/CMakeLists.txt rename soc/{arm/nxp_s32 => nxp/s32}/common/cmsis_rtos_v2_adapt.h (100%) rename soc/{arm/nxp_s32 => nxp/s32}/common/osif.c (94%) rename soc/{arm/nxp_s32 => nxp/s32}/common/pinctrl_soc.h (100%) rename soc/{arm/nxp_s32 => nxp/s32}/common/power_soc.c (98%) create mode 100644 soc/nxp/s32/s32k1/CMakeLists.txt create mode 100644 soc/nxp/s32/s32k1/Kconfig create mode 100644 soc/nxp/s32/s32k1/Kconfig.defconfig create mode 100644 soc/nxp/s32/s32k1/Kconfig.soc rename soc/{arm/nxp_s32 => nxp/s32}/s32k1/flash_config.ld (100%) rename soc/{arm/nxp_s32 => nxp/s32}/s32k1/flash_configuration.c (100%) rename soc/{arm/nxp_s32 => nxp/s32}/s32k1/nxp_mpu_regions.c (94%) rename soc/{arm/nxp_s32 => nxp/s32}/s32k1/pinctrl_soc.h (100%) create mode 100644 soc/nxp/s32/s32k1/soc.c rename soc/{arm/nxp_s32 => nxp/s32}/s32k1/soc.h (100%) create mode 100644 soc/nxp/s32/s32k3/CMakeLists.txt create mode 100644 soc/nxp/s32/s32k3/Kconfig create mode 100644 soc/nxp/s32/s32k3/Kconfig.defconfig create mode 100644 soc/nxp/s32/s32k3/Kconfig.soc rename soc/{arm/nxp_s32 => nxp/s32}/s32k3/linker.ld (100%) rename soc/{arm/nxp_s32 => nxp/s32}/s32k3/mpu_regions.c (100%) rename soc/{arm/nxp_s32 => nxp/s32}/s32k3/s32k3xx_startup.S (100%) rename soc/{arm/nxp_s32 => nxp/s32}/s32k3/sections.ld (100%) rename soc/{arm/nxp_s32 => nxp/s32}/s32k3/soc.c (100%) rename soc/{arm/nxp_s32 => nxp/s32}/s32k3/soc.h (100%) create mode 100644 soc/nxp/s32/s32ze/CMakeLists.txt create mode 100644 soc/nxp/s32/s32ze/Kconfig create mode 100644 soc/nxp/s32/s32ze/Kconfig.defconfig create mode 100644 soc/nxp/s32/s32ze/Kconfig.soc rename soc/{arm/nxp_s32 => nxp/s32}/s32ze/mpu_regions.c (100%) rename soc/{arm/nxp_s32 => nxp/s32}/s32ze/soc.c (100%) create mode 100644 soc/nxp/s32/s32ze/soc.h create mode 100644 soc/nxp/s32/soc.yml create mode 100644 soc/openisa/rv32m1/CMakeLists.txt create mode 100644 soc/openisa/rv32m1/Kconfig create mode 100644 soc/openisa/rv32m1/Kconfig.defconfig create mode 100644 soc/openisa/rv32m1/Kconfig.soc rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/linker.ld (100%) rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/pinctrl_soc.h (100%) rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/soc.c (100%) rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/soc.h (100%) create mode 100644 soc/openisa/rv32m1/soc.yml rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/soc_context.h (100%) rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/soc_irq.S (100%) rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/soc_offsets.h (100%) rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/soc_ri5cy.h (100%) rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/soc_zero_riscy.h (100%) rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/vector.S (100%) rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/vector_table.ld (100%) rename soc/{riscv/openisa_rv32m1 => openisa/rv32m1}/wdog.S (100%) delete mode 100644 soc/posix/CMakeLists.txt delete mode 100644 soc/posix/inf_clock/CMakeLists.txt delete mode 100644 soc/posix/inf_clock/Kconfig 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soc/{arm/bcm_vk => raspberrypi}/CMakeLists.txt (100%) create mode 100644 soc/raspberrypi/Kconfig create mode 100644 soc/raspberrypi/Kconfig.defconfig create mode 100644 soc/raspberrypi/Kconfig.soc create mode 100644 soc/raspberrypi/rp2xxx/CMakeLists.txt create mode 100644 soc/raspberrypi/rp2xxx/Kconfig create mode 100644 soc/raspberrypi/rp2xxx/Kconfig.defconfig rename soc/{arm/rpi_pico/rp2 => raspberrypi/rp2xxx}/Kconfig.defconfig.rp2040 (84%) create mode 100644 soc/raspberrypi/rp2xxx/Kconfig.soc rename soc/{arm/rpi_pico/rp2 => raspberrypi/rp2xxx}/linker.ld (100%) rename soc/{arm/rpi_pico/rp2 => raspberrypi/rp2xxx}/pinctrl_soc.h (100%) rename soc/{arm/rpi_pico/rp2 => raspberrypi/rp2xxx}/soc.c (100%) rename soc/{arm/rpi_pico/rp2 => raspberrypi/rp2xxx}/soc.h (100%) create mode 100644 soc/raspberrypi/soc.yml rename soc/{arm/renesas_ra => renesas/ra}/CMakeLists.txt (100%) create mode 100644 soc/renesas/ra/Kconfig create mode 100644 soc/renesas/ra/Kconfig.defconfig create mode 100644 soc/renesas/ra/Kconfig.soc rename soc/{arm/renesas_ra => renesas/ra}/common/pinctrl_ra.h (100%) rename soc/{arm/renesas_ra => renesas/ra}/common/ra_common_soc.h (100%) create mode 100644 soc/renesas/ra/ra4m1/CMakeLists.txt create mode 100644 soc/renesas/ra/ra4m1/Kconfig create mode 100644 soc/renesas/ra/ra4m1/Kconfig.defconfig create mode 100644 soc/renesas/ra/ra4m1/Kconfig.soc rename soc/{arm/renesas_ra => renesas/ra}/ra4m1/pinctrl_soc.h (100%) rename soc/{arm/renesas_ra => renesas/ra}/ra4m1/soc.h (100%) create mode 100644 soc/renesas/ra/soc.yml rename soc/{arm/renesas_rcar => renesas/rcar}/CMakeLists.txt (100%) create mode 100644 soc/renesas/rcar/Kconfig create mode 100644 soc/renesas/rcar/Kconfig.defconfig create mode 100644 soc/renesas/rcar/Kconfig.soc rename soc/{arm/renesas_rcar => renesas/rcar}/common/pinctrl_rcar.h (100%) create mode 100644 soc/renesas/rcar/rcar_gen3/CMakeLists.txt create mode 100644 soc/renesas/rcar/rcar_gen3/Kconfig create mode 100644 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}/rockchip/rk3568/Kconfig.defconfig.rk3568 (90%) create mode 100644 soc/rockchip/rk3568/Kconfig.soc rename soc/{arm64 => }/rockchip/rk3568/mmu_regions.c (100%) create mode 100644 soc/rockchip/soc.yml rename soc/{riscv/nordic_nrf => sifive/sifive_freedom}/CMakeLists.txt (100%) create mode 100644 soc/sifive/sifive_freedom/Kconfig create mode 100644 soc/sifive/sifive_freedom/Kconfig.defconfig create mode 100644 soc/sifive/sifive_freedom/Kconfig.soc rename soc/{riscv => sifive}/sifive_freedom/common/CMakeLists.txt (100%) rename soc/{riscv => sifive}/sifive_freedom/common/pinctrl_soc.h (100%) create mode 100644 soc/sifive/sifive_freedom/fe300/CMakeLists.txt create mode 100644 soc/sifive/sifive_freedom/fe300/Kconfig create mode 100644 soc/sifive/sifive_freedom/fe300/Kconfig.defconfig create mode 100644 soc/sifive/sifive_freedom/fe300/Kconfig.soc rename soc/{riscv/sifive_freedom/e300 => sifive/sifive_freedom/fe300}/clock.c (100%) rename soc/{riscv/sifive_freedom/e300 => sifive/sifive_freedom/fe300}/prci.h (100%) rename soc/{riscv/sifive_freedom/e300 => sifive/sifive_freedom/fe300}/soc.h (100%) create mode 100644 soc/sifive/sifive_freedom/fu500/CMakeLists.txt create mode 100644 soc/sifive/sifive_freedom/fu500/Kconfig create mode 100644 soc/sifive/sifive_freedom/fu500/Kconfig.defconfig create mode 100644 soc/sifive/sifive_freedom/fu500/Kconfig.soc rename soc/{riscv/sifive_freedom/u500 => sifive/sifive_freedom/fu500}/clock.c (100%) rename soc/{riscv/sifive_freedom/u500 => sifive/sifive_freedom/fu500}/prci.h (100%) rename soc/{riscv/sifive_freedom/u500 => sifive/sifive_freedom/fu500}/soc.h (100%) create mode 100644 soc/sifive/sifive_freedom/fu700/CMakeLists.txt create mode 100644 soc/sifive/sifive_freedom/fu700/Kconfig create mode 100644 soc/sifive/sifive_freedom/fu700/Kconfig.defconfig create mode 100644 soc/sifive/sifive_freedom/fu700/Kconfig.soc rename soc/{riscv/sifive_freedom/u700 => sifive/sifive_freedom/fu700}/clock.c (100%) rename soc/{riscv/sifive_freedom/u700 => sifive/sifive_freedom/fu700}/prci.h (100%) rename soc/{riscv/sifive_freedom/u700 => sifive/sifive_freedom/fu700}/soc.h (100%) create mode 100644 soc/sifive/sifive_freedom/soc.yml create mode 100644 soc/silabs/CMakeLists.txt create mode 100644 soc/silabs/Kconfig create mode 100644 soc/silabs/Kconfig.defconfig create mode 100644 soc/silabs/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs}/common/CMakeLists.txt (100%) create mode 100644 soc/silabs/common/pinctrl_soc.h rename soc/{arm/silabs_exx32 => silabs}/common/sl_device_init_hfxo_config.h (100%) create mode 100644 soc/silabs/common/soc.c create mode 100644 soc/silabs/common/soc_gpio.h rename soc/{arm/silabs_exx32 => silabs}/common/soc_power.c (100%) rename soc/{arm/silabs_exx32 => silabs}/common/soc_power_pmgr.c (100%) create mode 100644 soc/silabs/silabs_s0/Kconfig.soc create mode 100644 soc/silabs/silabs_s0/efm32hg/Kconfig create mode 100644 soc/silabs/silabs_s0/efm32hg/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s0/efm32hg/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s0}/efm32hg/soc.h (100%) rename soc/{arm/silabs_exx32 => silabs/silabs_s0}/efm32hg/soc_pinmap.h (100%) create mode 100644 soc/silabs/silabs_s0/efm32wg/Kconfig create mode 100644 soc/silabs/silabs_s0/efm32wg/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s0/efm32wg/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s0}/efm32wg/soc.h (100%) rename soc/{arm/silabs_exx32 => silabs/silabs_s0}/efm32wg/soc_pinmap.h (100%) create mode 100644 soc/silabs/silabs_s1/Kconfig.soc create mode 100644 soc/silabs/silabs_s1/efm32gg11b/Kconfig create mode 100644 soc/silabs/silabs_s1/efm32gg11b/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s1/efm32gg11b/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efm32gg11b/soc.h (100%) rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efm32gg11b/soc_pinmap.h (100%) create mode 100644 soc/silabs/silabs_s1/efm32gg12b/Kconfig create mode 100644 soc/silabs/silabs_s1/efm32gg12b/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s1/efm32gg12b/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efm32gg12b/soc.h (100%) rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efm32gg12b/soc_pinmap.h (100%) create mode 100644 soc/silabs/silabs_s1/efm32jg12b/Kconfig create mode 100644 soc/silabs/silabs_s1/efm32jg12b/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s1/efm32jg12b/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efm32jg12b/soc.h (100%) rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efm32jg12b/soc_pinmap.h (100%) create mode 100644 soc/silabs/silabs_s1/efm32pg12b/Kconfig create mode 100644 soc/silabs/silabs_s1/efm32pg12b/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s1/efm32pg12b/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efm32pg12b/soc.h (100%) rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efm32pg12b/soc_pinmap.h (100%) create mode 100644 soc/silabs/silabs_s1/efm32pg1b/Kconfig create mode 100644 soc/silabs/silabs_s1/efm32pg1b/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s1/efm32pg1b/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efm32pg1b/soc.h (100%) rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efm32pg1b/soc_pinmap.h (100%) create mode 100644 soc/silabs/silabs_s1/efr32bg13p/Kconfig create mode 100644 soc/silabs/silabs_s1/efr32bg13p/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s1/efr32bg13p/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efr32bg13p/soc.h (100%) rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efr32bg13p/soc_pinmap.h (100%) create mode 100644 soc/silabs/silabs_s1/efr32fg13p/Kconfig create mode 100644 soc/silabs/silabs_s1/efr32fg13p/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s1/efr32fg13p/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efr32fg13p/soc.h (100%) rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efr32fg13p/soc_pinmap.h (100%) create mode 100644 soc/silabs/silabs_s1/efr32fg1p/Kconfig create mode 100644 soc/silabs/silabs_s1/efr32fg1p/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s1/efr32fg1p/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efr32fg1p/soc.h (100%) rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efr32fg1p/soc_pinmap.h (100%) create mode 100644 soc/silabs/silabs_s1/efr32mg12p/Kconfig create mode 100644 soc/silabs/silabs_s1/efr32mg12p/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s1/efr32mg12p/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efr32mg12p/soc.h (100%) rename soc/{arm/silabs_exx32 => silabs/silabs_s1}/efr32mg12p/soc_pinmap.h (100%) create mode 100644 soc/silabs/silabs_s2/Kconfig.soc create mode 100644 soc/silabs/silabs_s2/efr32bg22/Kconfig create mode 100644 soc/silabs/silabs_s2/efr32bg22/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s2/efr32bg22/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s2}/efr32bg22/soc.h (100%) create mode 100644 soc/silabs/silabs_s2/efr32bg27/Kconfig create mode 100644 soc/silabs/silabs_s2/efr32bg27/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s2/efr32bg27/Kconfig.soc rename soc/{arm/silabs_exx32 => silabs/silabs_s2}/efr32bg27/soc.h (100%) create mode 100644 soc/silabs/silabs_s2/efr32mg21/Kconfig create mode 100644 soc/silabs/silabs_s2/efr32mg21/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s2/efr32mg21/Kconfig.soc create mode 100644 soc/silabs/silabs_s2/efr32mg21/soc.h create mode 100644 soc/silabs/silabs_s2/efr32mg21/soc_pinmap.h create mode 100644 soc/silabs/silabs_s2/efr32mg24/Kconfig create mode 100644 soc/silabs/silabs_s2/efr32mg24/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s2/efr32mg24/Kconfig.soc create mode 100644 soc/silabs/silabs_s2/efr32mg24/soc.h create mode 100644 soc/silabs/silabs_s2/efr32mg24/soc_pinmap.h create mode 100644 soc/silabs/soc.yml delete mode 100644 soc/sparc/Kconfig delete mode 100644 soc/sparc/gr716a/CMakeLists.txt delete mode 100644 soc/sparc/gr716a/Kconfig.defconfig delete mode 100644 soc/sparc/gr716a/Kconfig.soc delete mode 100644 soc/sparc/leon3/CMakeLists.txt delete mode 100644 soc/sparc/leon3/Kconfig.defconfig delete mode 100644 soc/sparc/leon3/Kconfig.soc create mode 100644 soc/st/stm32/CMakeLists.txt create mode 100644 soc/st/stm32/Kconfig create mode 100644 soc/st/stm32/Kconfig.defconfig create mode 100644 soc/st/stm32/Kconfig.soc create mode 100644 soc/st/stm32/common/CMakeLists.txt rename soc/{arm/st_stm32 => st/stm32}/common/ccm.ld (100%) rename soc/{arm/st_stm32 => st/stm32}/common/pinctrl_soc.h (100%) rename soc/{arm/st_stm32 => st/stm32}/common/soc_config.c (100%) rename soc/{arm/st_stm32 => st/stm32}/common/stm32_backup_sram.c (100%) rename soc/{arm/st_stm32 => st/stm32}/common/stm32_backup_sram.ld (100%) rename soc/{arm/st_stm32 => st/stm32}/common/stm32_hsem.h (100%) rename soc/{arm/st_stm32 => st/stm32}/common/stm32cube_hal.c (100%) create mode 100644 soc/st/stm32/soc.yml create mode 100644 soc/st/stm32/stm32c0x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32c0x/Kconfig create mode 100644 soc/st/stm32/stm32c0x/Kconfig.defconfig rename soc/{arm/st_stm32/stm32c0 => st/stm32/stm32c0x}/Kconfig.defconfig.stm32c031xx (86%) create mode 100644 soc/st/stm32/stm32c0x/Kconfig.soc rename soc/{arm/st_stm32/stm32c0 => st/stm32/stm32c0x}/soc.c (100%) rename soc/{arm/st_stm32/stm32c0 => st/stm32/stm32c0x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32f0x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32f0x/Kconfig create mode 100644 soc/st/stm32/stm32f0x/Kconfig.defconfig create mode 100644 soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x4 rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/Kconfig.defconfig.stm32f030x6 (83%) rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/Kconfig.defconfig.stm32f030x8 (84%) rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/Kconfig.defconfig.stm32f030xc (82%) rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/Kconfig.defconfig.stm32f031x6 (86%) rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/Kconfig.defconfig.stm32f042x6 (84%) rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/Kconfig.defconfig.stm32f051x8 (84%) rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/Kconfig.defconfig.stm32f070xb (84%) rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/Kconfig.defconfig.stm32f072xx (86%) rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/Kconfig.defconfig.stm32f091xc (84%) rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/Kconfig.defconfig.stm32f098xx (84%) create mode 100644 soc/st/stm32/stm32f0x/Kconfig.soc rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/soc.c (100%) rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/soc.h (100%) rename soc/{arm/st_stm32/stm32f0 => st/stm32/stm32f0x}/sram_vector_table.ld (100%) create mode 100644 soc/st/stm32/stm32f1x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32f1x/Kconfig create mode 100644 soc/st/stm32/stm32f1x/Kconfig.defconfig rename soc/{arm/st_stm32/stm32f1 => st/stm32/stm32f1x}/Kconfig.defconfig.stm32f100xx (100%) rename soc/{arm/st_stm32/stm32f1 => st/stm32/stm32f1x}/Kconfig.defconfig.stm32f103xx (81%) rename soc/{arm/st_stm32/stm32f1 => st/stm32/stm32f1x}/Kconfig.defconfig.stm32f105xx (84%) rename soc/{arm/st_stm32/stm32f1 => st/stm32/stm32f1x}/Kconfig.defconfig.stm32f107xc (84%) create mode 100644 soc/st/stm32/stm32f1x/Kconfig.soc rename soc/{arm/st_stm32/stm32f1 => st/stm32/stm32f1x}/soc.c (100%) rename soc/{arm/st_stm32/stm32f1 => st/stm32/stm32f1x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32f2x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32f2x/Kconfig create mode 100644 soc/st/stm32/stm32f2x/Kconfig.defconfig create mode 100644 soc/st/stm32/stm32f2x/Kconfig.defconfig.stm32f205xx create mode 100644 soc/st/stm32/stm32f2x/Kconfig.defconfig.stm32f207xx create mode 100644 soc/st/stm32/stm32f2x/Kconfig.soc rename soc/{arm/st_stm32/stm32f2 => st/stm32/stm32f2x}/soc.c (100%) rename soc/{arm/st_stm32/stm32f2 => st/stm32/stm32f2x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32f3x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32f3x/Kconfig create mode 100644 soc/st/stm32/stm32f3x/Kconfig.defconfig create mode 100644 soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302x8 create mode 100644 soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302xc rename soc/{arm/st_stm32/stm32f3 => st/stm32/stm32f3x}/Kconfig.defconfig.stm32f303x(b-c) (80%) rename soc/{arm/st_stm32/stm32f3 => st/stm32/stm32f3x}/Kconfig.defconfig.stm32f303x8 (78%) create mode 100644 soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303xe create mode 100644 soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f334x8 create mode 100644 soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f373xc create mode 100644 soc/st/stm32/stm32f3x/Kconfig.soc rename soc/{arm/st_stm32/stm32f3 => st/stm32/stm32f3x}/soc.c (100%) rename soc/{arm/st_stm32/stm32f3 => st/stm32/stm32f3x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32f4x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32f4x/Kconfig create mode 100644 soc/st/stm32/stm32f4x/Kconfig.defconfig rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f401xc (84%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f401xe (84%) create mode 100644 soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f405xx create mode 100644 soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f407xx rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f410xx (84%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f411xe (84%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f412rx (84%) create mode 100644 soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412xx rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f413xx (85%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f415xx (85%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f417xx (84%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f423xx (84%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f427xx (84%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f429xx (84%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f437xx (86%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f446xx (84%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/Kconfig.defconfig.stm32f469xx (84%) create mode 100644 soc/st/stm32/stm32f4x/Kconfig.soc rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/power.c (100%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/soc.c (100%) rename soc/{arm/st_stm32/stm32f4 => st/stm32/stm32f4x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32f7x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32f7x/Kconfig create mode 100644 soc/st/stm32/stm32f7x/Kconfig.defconfig rename soc/{arm/st_stm32/stm32f7 => st/stm32/stm32f7x}/Kconfig.defconfig.stm32f722xx (84%) rename soc/{arm/st_stm32/stm32f7 => st/stm32/stm32f7x}/Kconfig.defconfig.stm32f723xx (84%) rename soc/{arm/st_stm32/stm32f7 => st/stm32/stm32f7x}/Kconfig.defconfig.stm32f745xx (85%) rename soc/{arm/st_stm32/stm32f7 => st/stm32/stm32f7x}/Kconfig.defconfig.stm32f746xx (84%) rename soc/{arm/st_stm32/stm32f7 => st/stm32/stm32f7x}/Kconfig.defconfig.stm32f750xx (84%) rename soc/{arm/st_stm32/stm32f7 => st/stm32/stm32f7x}/Kconfig.defconfig.stm32f756xx (84%) rename soc/{arm/st_stm32/stm32f7 => st/stm32/stm32f7x}/Kconfig.defconfig.stm32f765xx (75%) rename soc/{arm/st_stm32/stm32f7 => st/stm32/stm32f7x}/Kconfig.defconfig.stm32f767xx (80%) rename soc/{arm/st_stm32/stm32f7 => st/stm32/stm32f7x}/Kconfig.defconfig.stm32f769xx (80%) create mode 100644 soc/st/stm32/stm32f7x/Kconfig.soc rename soc/{arm/st_stm32/stm32f7 => st/stm32/stm32f7x}/soc.c (100%) rename soc/{arm/st_stm32/stm32f7 => st/stm32/stm32f7x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32g0x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32g0x/Kconfig create mode 100644 soc/st/stm32/stm32g0x/Kconfig.defconfig rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g030xx (84%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g031xx (83%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g041xx (84%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g050xx (84%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g051xx (84%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g061xx (84%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g070xx (84%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g071xx (87%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g081xx (86%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g0b0xx (84%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g0b1xx (90%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/Kconfig.defconfig.stm32g0c1xx (84%) create mode 100644 soc/st/stm32/stm32g0x/Kconfig.soc rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/power.c (100%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/soc.c (100%) rename soc/{arm/st_stm32/stm32g0 => st/stm32/stm32g0x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32g4x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32g4x/Kconfig create mode 100644 soc/st/stm32/stm32g4x/Kconfig.defconfig create mode 100644 soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g431xx rename soc/{arm/st_stm32/stm32g4 => st/stm32/stm32g4x}/Kconfig.defconfig.stm32g441xx (84%) rename soc/{arm/st_stm32/stm32g4 => st/stm32/stm32g4x}/Kconfig.defconfig.stm32g473xx (84%) create mode 100644 soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g474xx rename soc/{arm/st_stm32/stm32g4 => st/stm32/stm32g4x}/Kconfig.defconfig.stm32g483xx (84%) rename soc/{arm/st_stm32/stm32g4 => st/stm32/stm32g4x}/Kconfig.defconfig.stm32g484xx (84%) rename soc/{arm/st_stm32/stm32g4 => st/stm32/stm32g4x}/Kconfig.defconfig.stm32g491xx (84%) rename soc/{arm/st_stm32/stm32g4 => st/stm32/stm32g4x}/Kconfig.defconfig.stm32g4a1xx (84%) create mode 100644 soc/st/stm32/stm32g4x/Kconfig.soc rename soc/{arm/st_stm32/stm32g4 => st/stm32/stm32g4x}/power.c (100%) create mode 100644 soc/st/stm32/stm32g4x/soc.c rename soc/{arm/st_stm32/stm32g4 => st/stm32/stm32g4x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32h5x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32h5x/Kconfig create mode 100644 soc/st/stm32/stm32h5x/Kconfig.defconfig rename soc/{arm/st_stm32/stm32h5 => st/stm32/stm32h5x}/Kconfig.defconfig.stm32h503xx (84%) rename soc/{arm/st_stm32/stm32h5 => st/stm32/stm32h5x}/Kconfig.defconfig.stm32h562xx (84%) rename soc/{arm/st_stm32/stm32h5 => st/stm32/stm32h5x}/Kconfig.defconfig.stm32h563xx (84%) rename soc/{arm/st_stm32/stm32h5 => st/stm32/stm32h5x}/Kconfig.defconfig.stm32h573xx (84%) create mode 100644 soc/st/stm32/stm32h5x/Kconfig.soc rename soc/{arm/st_stm32/stm32h5 => st/stm32/stm32h5x}/soc.c (100%) rename soc/{arm/st_stm32/stm32h5 => st/stm32/stm32h5x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32h7x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32h7x/Kconfig create mode 100644 soc/st/stm32/stm32h7x/Kconfig.defconfig rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/Kconfig.defconfig.stm32h723xx (86%) rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/Kconfig.defconfig.stm32h725xx (84%) rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/Kconfig.defconfig.stm32h730xx (75%) rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/Kconfig.defconfig.stm32h735xx (85%) rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/Kconfig.defconfig.stm32h743xx (85%) create mode 100644 soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h745xx create mode 100644 soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h747xx rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/Kconfig.defconfig.stm32h750xx (85%) rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/Kconfig.defconfig.stm32h753xx (85%) create mode 100644 soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7a3xx create mode 100644 soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b0xx create mode 100644 soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b3xx create mode 100644 soc/st/stm32/stm32h7x/Kconfig.soc rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/mpu_regions.c (100%) rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/sections.ld (100%) rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/soc.h (100%) rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/soc_m4.c (100%) rename soc/{arm/st_stm32/stm32h7 => st/stm32/stm32h7x}/soc_m7.c (100%) create mode 100644 soc/st/stm32/stm32l0x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32l0x/Kconfig create mode 100644 soc/st/stm32/stm32l0x/Kconfig.defconfig rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l010x4 (84%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l010x6 (84%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l010x8 (84%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l010xb (86%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l011xx (84%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l031xx (85%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l051xx (83%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l053xx (85%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l071xx (85%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l072xx (85%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l073xx (85%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/Kconfig.defconfig.stm32l081xx (86%) create mode 100644 soc/st/stm32/stm32l0x/Kconfig.soc rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/power.c (100%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/soc.c (100%) rename soc/{arm/st_stm32/stm32l0 => st/stm32/stm32l0x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32l1x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32l1x/Kconfig create mode 100644 soc/st/stm32/stm32l1x/Kconfig.defconfig create mode 100644 soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xb create mode 100644 soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xba create mode 100644 soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xc create mode 100644 soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xc rename soc/{arm/st_stm32/stm32l1 => st/stm32/stm32l1x}/Kconfig.defconfig.stm32l152xe (83%) create mode 100644 soc/st/stm32/stm32l1x/Kconfig.soc rename soc/{arm/st_stm32/stm32l1 => st/stm32/stm32l1x}/soc.c (100%) rename soc/{arm/st_stm32/stm32l1 => st/stm32/stm32l1x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32l4x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32l4x/Kconfig create mode 100644 soc/st/stm32/stm32l4x/Kconfig.defconfig rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l412xx (84%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l422xx (84%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l431xx (83%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l432xx (86%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l433xx (84%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l451xx (85%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l452xx (84%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l462xx (84%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l471xx (84%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l475xx (84%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l476xx (86%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l486xx (88%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l496xx (88%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l4a6xx (89%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l4p5xx (84%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l4q5xx (84%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l4r5xx (84%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l4r9xx (84%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/Kconfig.defconfig.stm32l4s5xx (84%) create mode 100644 soc/st/stm32/stm32l4x/Kconfig.soc rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/power.c (100%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/poweroff.c (100%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/soc.c (100%) rename soc/{arm/st_stm32/stm32l4 => st/stm32/stm32l4x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32l5x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32l5x/Kconfig create mode 100644 soc/st/stm32/stm32l5x/Kconfig.defconfig rename soc/{arm/st_stm32/stm32l5 => st/stm32/stm32l5x}/Kconfig.defconfig.stm32l552xx (84%) rename soc/{arm/st_stm32/stm32l5 => st/stm32/stm32l5x}/Kconfig.defconfig.stm32l562xx (84%) create mode 100644 soc/st/stm32/stm32l5x/Kconfig.soc rename soc/{arm/st_stm32/stm32l5 => st/stm32/stm32l5x}/power.c (100%) rename soc/{arm/st_stm32/stm32l5 => st/stm32/stm32l5x}/soc.c (100%) rename soc/{arm/st_stm32/stm32l5 => st/stm32/stm32l5x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32mp1x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32mp1x/Kconfig create mode 100644 soc/st/stm32/stm32mp1x/Kconfig.defconfig create mode 100644 soc/st/stm32/stm32mp1x/Kconfig.defconfig.stm32mp15_m4 create mode 100644 soc/st/stm32/stm32mp1x/Kconfig.soc rename soc/{arm/st_stm32/stm32mp1 => st/stm32/stm32mp1x}/linker.ld (100%) rename soc/{arm/st_stm32/stm32mp1 => st/stm32/stm32mp1x}/soc.c (100%) rename soc/{arm/st_stm32/stm32mp1 => st/stm32/stm32mp1x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32u5x/CMakeLists.txt create mode 100644 soc/st/stm32/stm32u5x/Kconfig create mode 100644 soc/st/stm32/stm32u5x/Kconfig.defconfig rename soc/{arm/st_stm32/stm32u5 => st/stm32/stm32u5x}/Kconfig.defconfig.stm32u575xx (84%) rename soc/{arm/st_stm32/stm32u5 => st/stm32/stm32u5x}/Kconfig.defconfig.stm32u585xx (84%) rename soc/{arm/st_stm32/stm32u5 => st/stm32/stm32u5x}/Kconfig.defconfig.stm32u595xx (84%) rename soc/{arm/st_stm32/stm32u5 => st/stm32/stm32u5x}/Kconfig.defconfig.stm32u599xx (84%) rename soc/{arm/st_stm32/stm32u5 => st/stm32/stm32u5x}/Kconfig.defconfig.stm32u5a5xx (84%) rename soc/{arm/st_stm32/stm32u5 => st/stm32/stm32u5x}/Kconfig.defconfig.stm32u5a9xx (84%) create mode 100644 soc/st/stm32/stm32u5x/Kconfig.soc rename soc/{arm/st_stm32/stm32u5 => st/stm32/stm32u5x}/power.c (100%) rename soc/{arm/st_stm32/stm32u5 => st/stm32/stm32u5x}/poweroff.c (100%) rename soc/{arm/st_stm32/stm32u5 => st/stm32/stm32u5x}/soc.c (100%) rename soc/{arm/st_stm32/stm32u5 => st/stm32/stm32u5x}/soc.h (100%) create mode 100644 soc/st/stm32/stm32wbax/CMakeLists.txt create mode 100644 soc/st/stm32/stm32wbax/Kconfig create mode 100644 soc/st/stm32/stm32wbax/Kconfig.defconfig rename soc/{arm/st_stm32/stm32wba => st/stm32/stm32wbax}/Kconfig.defconfig.stm32wba52xx (84%) rename soc/{arm/st_stm32/stm32wba => st/stm32/stm32wbax}/Kconfig.defconfig.stm32wba55xx (84%) create mode 100644 soc/st/stm32/stm32wbax/Kconfig.soc rename soc/{arm/st_stm32/stm32wba => st/stm32/stm32wbax}/hci_if/bleplat.c (100%) rename soc/{arm/st_stm32/stm32wba => st/stm32/stm32wbax}/hci_if/host_stack_if.c (100%) rename soc/{arm/st_stm32/stm32wba => st/stm32/stm32wbax}/hci_if/linklayer_plat.c (100%) rename soc/{arm/st_stm32/stm32wba => st/stm32/stm32wbax}/hci_if/linklayer_plat_local.h (100%) rename soc/{arm/st_stm32/stm32wba => st/stm32/stm32wbax}/hci_if/ll_sys_if.c (100%) rename soc/{arm/st_stm32/stm32wba => st/stm32/stm32wbax}/hci_if/stm32_timer.c (100%) rename soc/{arm/st_stm32/stm32wba => st/stm32/stm32wbax}/power.c (100%) rename soc/{arm/st_stm32/stm32wba => st/stm32/stm32wbax}/soc.c (100%) rename soc/{arm/st_stm32/stm32wba => st/stm32/stm32wbax}/soc.h (100%) create mode 100644 soc/st/stm32/stm32wbx/CMakeLists.txt create mode 100644 soc/st/stm32/stm32wbx/Kconfig create mode 100644 soc/st/stm32/stm32wbx/Kconfig.defconfig rename soc/{arm/st_stm32/stm32wb => st/stm32/stm32wbx}/Kconfig.defconfig.stm32wb55xx (84%) create mode 100644 soc/st/stm32/stm32wbx/Kconfig.soc rename soc/{arm/st_stm32/stm32wb => st/stm32/stm32wbx}/ipm.ld (100%) rename soc/{arm/st_stm32/stm32wb => st/stm32/stm32wbx}/power.c (100%) rename soc/{arm/st_stm32/stm32wb => st/stm32/stm32wbx}/poweroff.c (100%) rename soc/{arm/st_stm32/stm32wb => st/stm32/stm32wbx}/soc.c (100%) rename soc/{arm/st_stm32/stm32wb => st/stm32/stm32wbx}/soc.h (100%) create mode 100644 soc/st/stm32/stm32wlx/CMakeLists.txt create mode 100644 soc/st/stm32/stm32wlx/Kconfig create mode 100644 soc/st/stm32/stm32wlx/Kconfig.defconfig rename soc/{arm/st_stm32/stm32wl => st/stm32/stm32wlx}/Kconfig.defconfig.stm32wl54xx (84%) rename soc/{arm/st_stm32/stm32wl => st/stm32/stm32wlx}/Kconfig.defconfig.stm32wl55xx (84%) rename soc/{arm/st_stm32/stm32wl => st/stm32/stm32wlx}/Kconfig.defconfig.stm32wle4xx (84%) rename soc/{arm/st_stm32/stm32wl => st/stm32/stm32wlx}/Kconfig.defconfig.stm32wle5xx (84%) create mode 100644 soc/st/stm32/stm32wlx/Kconfig.soc rename soc/{arm/st_stm32/stm32wl => st/stm32/stm32wlx}/power.c (100%) rename soc/{arm/st_stm32/stm32wl => st/stm32/stm32wlx}/poweroff.c (100%) rename soc/{arm/st_stm32/stm32wl => st/stm32/stm32wlx}/soc.c (100%) rename soc/{arm/st_stm32/stm32wl => st/stm32/stm32wlx}/soc.h (100%) rename soc/{riscv/starfive_jh71xx => starfive}/jh71xx/CMakeLists.txt (100%) create mode 100644 soc/starfive/jh71xx/Kconfig create mode 100644 soc/starfive/jh71xx/Kconfig.defconfig create mode 100644 soc/starfive/jh71xx/Kconfig.soc create mode 100644 soc/starfive/jh71xx/soc.yml rename soc/{arc/snps_arc_iot => synopsys/arc_iot}/CMakeLists.txt (100%) create mode 100644 soc/synopsys/arc_iot/Kconfig create mode 100644 soc/synopsys/arc_iot/Kconfig.defconfig create mode 100644 soc/synopsys/arc_iot/Kconfig.soc rename soc/{arc/snps_arc_iot => synopsys/arc_iot}/linker.ld (100%) rename soc/{arc/snps_arc_iot => synopsys/arc_iot}/soc.c (100%) create mode 100644 soc/synopsys/arc_iot/soc.yml rename soc/{arc/snps_arc_iot => synopsys/arc_iot}/sysconf.c (100%) rename soc/{arc/snps_arc_iot => synopsys/arc_iot}/sysconf.h (100%) create mode 100644 soc/synopsys/emsdp/CMakeLists.txt create mode 100644 soc/synopsys/emsdp/Kconfig create mode 100644 soc/synopsys/emsdp/Kconfig.defconfig rename soc/{arc/snps_emsdp => synopsys/emsdp}/Kconfig.defconfig.em11d (100%) rename soc/{arc/snps_emsdp => synopsys/emsdp}/Kconfig.defconfig.em4 (100%) rename soc/{arc/snps_emsdp => synopsys/emsdp}/Kconfig.defconfig.em5d (100%) rename soc/{arc/snps_emsdp => synopsys/emsdp}/Kconfig.defconfig.em6 (100%) rename soc/{arc/snps_emsdp => synopsys/emsdp}/Kconfig.defconfig.em7d (100%) rename soc/{arc/snps_emsdp => synopsys/emsdp}/Kconfig.defconfig.em7d_esp (100%) rename soc/{arc/snps_emsdp => synopsys/emsdp}/Kconfig.defconfig.em9d (100%) create mode 100644 soc/synopsys/emsdp/Kconfig.soc rename soc/{arc/snps_emsdp => synopsys/emsdp}/linker.ld (100%) rename soc/{arc/snps_emsdp => synopsys/emsdp}/pinctrl_soc.h (100%) create mode 100644 soc/synopsys/emsdp/soc.yml create mode 100644 soc/synopsys/emsk/CMakeLists.txt create mode 100644 soc/synopsys/emsk/Kconfig create mode 100644 soc/synopsys/emsk/Kconfig.defconfig rename soc/{arc/snps_emsk => synopsys/emsk}/Kconfig.defconfig.em11d (87%) create mode 100644 soc/synopsys/emsk/Kconfig.defconfig.em7d rename soc/{arc/snps_emsk => synopsys/emsk}/Kconfig.defconfig.em9d (86%) create mode 100644 soc/synopsys/emsk/Kconfig.soc rename soc/{arc/snps_emsk => synopsys/emsk}/linker.ld (100%) create mode 100644 soc/synopsys/emsk/soc.yml rename soc/{arc/snps_emsk => synopsys/emsk}/soc_config.c (100%) rename soc/{arc/snps_arc_hsdk => synopsys/hsdk}/CMakeLists.txt (100%) create mode 100644 soc/synopsys/hsdk/Kconfig create mode 100644 soc/synopsys/hsdk/Kconfig.defconfig create mode 100644 soc/synopsys/hsdk/Kconfig.soc rename soc/{arc/snps_arc_hsdk => synopsys/hsdk}/linker.ld (100%) create mode 100644 soc/synopsys/hsdk/soc.yml create mode 100644 soc/synopsys/hsdk4xd/CMakeLists.txt create mode 100644 soc/synopsys/hsdk4xd/Kconfig create mode 100644 soc/synopsys/hsdk4xd/Kconfig.defconfig create mode 100644 soc/synopsys/hsdk4xd/Kconfig.soc rename soc/{arc/snps_arc_hsdk4xd => synopsys/hsdk4xd}/linker.ld (100%) create mode 100644 soc/synopsys/hsdk4xd/soc.yml rename soc/{arc/snps_arc_hsdk4xd => synopsys/hsdk4xd}/soc_ctrl.h (99%) rename soc/{arc/snps_arc_hsdk4xd => synopsys/hsdk4xd}/tune_build_ops.cmake (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/CMakeLists.txt (100%) create mode 100644 soc/synopsys/nsim/Kconfig create mode 100644 soc/synopsys/nsim/Kconfig.defconfig rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.em (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.em11d (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.em7d_v22 (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.hs (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.hs5x (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.hs5x_smp (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.hs6x (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.hs6x_smp (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.hs_mpuv6 (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.hs_smp (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.sem (100%) rename soc/{arc/snps_nsim => synopsys/nsim}/Kconfig.defconfig.vpx5 (100%) create mode 100644 soc/synopsys/nsim/Kconfig.soc rename soc/{arc/snps_nsim => synopsys/nsim}/linker.ld (100%) create mode 100644 soc/synopsys/nsim/soc.yml create mode 100644 soc/synopsys/qemu_arc/CMakeLists.txt create mode 100644 soc/synopsys/qemu_arc/Kconfig create mode 100644 soc/synopsys/qemu_arc/Kconfig.defconfig create mode 100644 soc/synopsys/qemu_arc/Kconfig.soc rename soc/{arc/snps_qemu => synopsys/qemu_arc}/linker.ld (100%) create mode 100644 soc/synopsys/qemu_arc/soc.yml rename soc/{riscv/intel_niosv => telink/tlsr}/CMakeLists.txt (100%) create mode 100644 soc/telink/tlsr/Kconfig create mode 100644 soc/telink/tlsr/Kconfig.defconfig create mode 100644 soc/telink/tlsr/Kconfig.soc create mode 100644 soc/telink/tlsr/soc.yml create mode 100644 soc/telink/tlsr/tlsr951x/CMakeLists.txt create mode 100644 soc/telink/tlsr/tlsr951x/Kconfig create mode 100644 soc/telink/tlsr/tlsr951x/Kconfig.defconfig create mode 100644 soc/telink/tlsr/tlsr951x/Kconfig.soc rename soc/{riscv/telink_tlsr => telink/tlsr}/tlsr951x/init.ld (100%) rename soc/{riscv/telink_tlsr => telink/tlsr}/tlsr951x/linker.ld (100%) rename soc/{riscv/telink_tlsr => telink/tlsr}/tlsr951x/pinctrl_soc.h (100%) rename soc/{riscv/telink_tlsr => telink/tlsr}/tlsr951x/soc.c (100%) rename soc/{riscv/telink_tlsr => telink/tlsr}/tlsr951x/soc.h (100%) rename soc/{riscv/telink_tlsr => telink/tlsr}/tlsr951x/soc_context.h (100%) rename soc/{riscv/telink_tlsr => telink/tlsr}/tlsr951x/soc_irq.S (100%) rename soc/{riscv/telink_tlsr => telink/tlsr}/tlsr951x/soc_offsets.h (100%) rename soc/{riscv/telink_tlsr => telink/tlsr}/tlsr951x/start.S (100%) create mode 100644 soc/ti/k3/CMakeLists.txt create mode 100644 soc/ti/k3/Kconfig create mode 100644 soc/ti/k3/Kconfig.defconfig create mode 100644 soc/ti/k3/Kconfig.soc create mode 100644 soc/ti/k3/am6x/CMakeLists.txt create mode 100644 soc/ti/k3/am6x/Kconfig create mode 100644 soc/ti/k3/am6x/Kconfig.defconfig create mode 100644 soc/ti/k3/am6x/Kconfig.soc rename soc/{arm64/ti_k3/am6x => ti/k3/am6x/a53}/mmu_regions.c (100%) rename soc/{arm/ti_k3/am62x_m4 => ti/k3/am6x/m4}/linker.ld (100%) rename soc/{arm/ti_k3/am62x_m4 => ti/k3/am6x/m4}/soc.c (100%) rename soc/{arm/ti_k3/am62x_m4 => ti/k3/am6x/m4}/soc.h (100%) rename soc/{arm64/ti_k3 => ti/k3/am6x}/pinctrl_soc.h (100%) create mode 100644 soc/ti/k3/soc.yml create mode 100644 soc/ti/lm3s6965/CMakeLists.txt create mode 100644 soc/ti/lm3s6965/Kconfig create mode 100644 soc/ti/lm3s6965/Kconfig.defconfig create mode 100644 soc/ti/lm3s6965/Kconfig.soc rename soc/{arm/ti_lm3s6965 => ti/lm3s6965}/reboot.S (100%) rename soc/{arm/ti_lm3s6965 => ti/lm3s6965}/soc.h (100%) create mode 100644 soc/ti/lm3s6965/soc.yml rename soc/{arm/ti_lm3s6965 => ti/lm3s6965}/soc_config.c (100%) rename soc/{arm/ti_lm3s6965 => ti/lm3s6965}/sys_arch_reboot.c (100%) create mode 100644 soc/ti/simplelink/CMakeLists.txt create mode 100644 soc/ti/simplelink/Kconfig create mode 100644 soc/ti/simplelink/Kconfig.defconfig create mode 100644 soc/ti/simplelink/Kconfig.soc create mode 100644 soc/ti/simplelink/cc13x2_cc26x2/CMakeLists.txt create mode 100644 soc/ti/simplelink/cc13x2_cc26x2/Kconfig create mode 100644 soc/ti/simplelink/cc13x2_cc26x2/Kconfig.defconfig create mode 100644 soc/ti/simplelink/cc13x2_cc26x2/Kconfig.soc rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2_cc26x2/ccfg.c (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2_cc26x2/ccfg.ld (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2_cc26x2/pinctrl_soc.h (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2_cc26x2/power.c (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2_cc26x2/poweroff.c (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2_cc26x2/soc.c (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2_cc26x2/soc.h (100%) create mode 100644 soc/ti/simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt create mode 100644 soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig create mode 100644 soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig create mode 100644 soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.soc rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2x7_cc26x2x7/ccfg.c (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2x7_cc26x2x7/ccfg.ld (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2x7_cc26x2x7/pinctrl_soc.h (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2x7_cc26x2x7/power.c (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2x7_cc26x2x7/soc.c (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc13x2x7_cc26x2x7/soc.h (100%) create mode 100644 soc/ti/simplelink/cc32xx/CMakeLists.txt create mode 100644 soc/ti/simplelink/cc32xx/Kconfig create mode 100644 soc/ti/simplelink/cc32xx/Kconfig.defconfig rename soc/{arm/ti_simplelink => ti/simplelink}/cc32xx/Kconfig.defconfig.cc3220sf (88%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc32xx/Kconfig.defconfig.cc3235sf (93%) create mode 100644 soc/ti/simplelink/cc32xx/Kconfig.soc rename soc/{arm/ti_simplelink => ti/simplelink}/cc32xx/README (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc32xx/cc32xx_debug.ld (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc32xx/pinctrl_soc.h (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc32xx/soc.c (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/cc32xx/soc.h (100%) create mode 100644 soc/ti/simplelink/msp432p4xx/CMakeLists.txt create mode 100644 soc/ti/simplelink/msp432p4xx/Kconfig create mode 100644 soc/ti/simplelink/msp432p4xx/Kconfig.defconfig rename soc/{arm/ti_simplelink => ti/simplelink}/msp432p4xx/Kconfig.defconfig.msp432p401r (86%) create mode 100644 soc/ti/simplelink/msp432p4xx/Kconfig.soc rename soc/{arm/ti_simplelink => ti/simplelink}/msp432p4xx/soc.c (100%) rename soc/{arm/ti_simplelink => ti/simplelink}/msp432p4xx/soc.h (100%) create mode 100644 soc/ti/simplelink/soc.yml delete mode 100644 soc/x86/alder_lake/CMakeLists.txt delete mode 100644 soc/x86/alder_lake/Kconfig.defconfig delete mode 100644 soc/x86/alder_lake/Kconfig.soc delete mode 100644 soc/x86/apollo_lake/CMakeLists.txt delete mode 100644 soc/x86/apollo_lake/Kconfig.defconfig delete mode 100644 soc/x86/apollo_lake/Kconfig.soc delete mode 100644 soc/x86/atom/CMakeLists.txt delete mode 100644 soc/x86/atom/Kconfig.defconfig delete mode 100644 soc/x86/atom/Kconfig.soc delete mode 100644 soc/x86/atom/soc.h delete mode 100644 soc/x86/elkhart_lake/CMakeLists.txt delete mode 100644 soc/x86/elkhart_lake/Kconfig.defconfig delete mode 100644 soc/x86/elkhart_lake/Kconfig.soc delete mode 100644 soc/x86/ia32/CMakeLists.txt delete mode 100644 soc/x86/ia32/Kconfig.defconfig delete mode 100644 soc/x86/ia32/Kconfig.soc delete mode 100644 soc/x86/ia32/soc.h delete mode 100644 soc/x86/intel_ish/Kconfig delete mode 100644 soc/x86/intel_ish/Kconfig.defconfig delete mode 100644 soc/x86/intel_ish/Kconfig.soc delete mode 100644 soc/x86/intel_ish/intel_ish5/CMakeLists.txt delete mode 100644 soc/x86/intel_ish/intel_ish5/Kconfig.defconfig.series delete mode 100644 soc/x86/intel_ish/intel_ish5/Kconfig.series delete mode 100644 soc/x86/intel_ish/intel_ish5/Kconfig.soc delete mode 100644 soc/x86/lakemont/CMakeLists.txt delete mode 100644 soc/x86/lakemont/Kconfig.defconfig delete mode 100644 soc/x86/lakemont/Kconfig.soc delete mode 100644 soc/x86/lakemont/linker.ld delete mode 100644 soc/x86/raptor_lake/CMakeLists.txt delete mode 100644 soc/x86/raptor_lake/Kconfig.defconfig delete mode 100644 soc/x86/raptor_lake/Kconfig.soc rename soc/{arm64/xenvm => xen}/CMakeLists.txt (100%) create mode 100644 soc/xen/Kconfig create mode 100644 soc/xen/Kconfig.defconfig create mode 100644 soc/xen/Kconfig.soc rename soc/{arm64/xenvm => xen}/mmu_regions.c (100%) create mode 100644 soc/xen/soc.yml rename soc/{arm/xilinx_zynq7000 => xlnx/zynq7000}/CMakeLists.txt (100%) create mode 100644 soc/xlnx/zynq7000/Kconfig create mode 100644 soc/xlnx/zynq7000/Kconfig.defconfig create mode 100644 soc/xlnx/zynq7000/Kconfig.soc rename soc/{arm/xilinx_zynq7000 => xlnx/zynq7000}/common/pinctrl_soc.h (100%) create mode 100644 soc/xlnx/zynq7000/soc.yml create mode 100644 soc/xlnx/zynq7000/xc7zxxx/CMakeLists.txt create mode 100644 soc/xlnx/zynq7000/xc7zxxx/Kconfig create mode 100644 soc/xlnx/zynq7000/xc7zxxx/Kconfig.defconfig create mode 100644 soc/xlnx/zynq7000/xc7zxxx/Kconfig.soc rename soc/{arm/xilinx_zynq7000 => xlnx/zynq7000}/xc7zxxx/soc.c (100%) rename soc/{arm/xilinx_zynq7000 => xlnx/zynq7000}/xc7zxxx/soc.h (100%) create mode 100644 soc/xlnx/zynq7000/xc7zxxxs/CMakeLists.txt create mode 100644 soc/xlnx/zynq7000/xc7zxxxs/Kconfig create mode 100644 soc/xlnx/zynq7000/xc7zxxxs/Kconfig.defconfig create mode 100644 soc/xlnx/zynq7000/xc7zxxxs/Kconfig.soc rename soc/{arm/xilinx_zynq7000 => xlnx/zynq7000}/xc7zxxxs/soc.c (100%) rename soc/{arm/xilinx_zynq7000 => xlnx/zynq7000}/xc7zxxxs/soc.h (100%) create mode 100644 soc/xlnx/zynqmp/CMakeLists.txt create mode 100644 soc/xlnx/zynqmp/Kconfig create mode 100644 soc/xlnx/zynqmp/Kconfig.defconfig create mode 100644 soc/xlnx/zynqmp/Kconfig.soc rename soc/{arm/xilinx_zynqmp => xlnx/zynqmp}/arm_mpu_regions.c (100%) rename soc/{arm/xilinx_zynqmp => xlnx/zynqmp}/pinctrl_soc.h (100%) rename soc/{arm/xilinx_zynqmp => xlnx/zynqmp}/soc.c (100%) rename soc/{arm/xilinx_zynqmp => xlnx/zynqmp}/soc.h (100%) create mode 100644 soc/xlnx/zynqmp/soc.yml delete mode 100644 soc/xtensa/CMakeLists.txt delete mode 100644 soc/xtensa/dc233c/Kconfig.defconfig delete mode 100644 soc/xtensa/dc233c/Kconfig.soc delete mode 100644 soc/xtensa/espressif_esp32/CMakeLists.txt delete mode 100644 soc/xtensa/espressif_esp32/Kconfig delete mode 100644 soc/xtensa/espressif_esp32/Kconfig.defconfig delete mode 100644 soc/xtensa/espressif_esp32/Kconfig.soc delete mode 100644 soc/xtensa/espressif_esp32/common/CMakeLists.txt delete mode 100644 soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series delete mode 100644 soc/xtensa/espressif_esp32/common/Kconfig.soc delete mode 100644 soc/xtensa/espressif_esp32/esp32/CMakeLists.txt delete mode 100644 soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series delete mode 100644 soc/xtensa/espressif_esp32/esp32/Kconfig.series delete mode 100644 soc/xtensa/espressif_esp32/esp32/Kconfig.soc delete mode 100644 soc/xtensa/espressif_esp32/esp32/default.ld delete mode 100644 soc/xtensa/espressif_esp32/esp32/soc.c delete mode 100644 soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt delete mode 100644 soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig.series delete mode 100644 soc/xtensa/espressif_esp32/esp32s2/Kconfig.series delete mode 100644 soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc delete mode 100644 soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt delete mode 100644 soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig.series delete mode 100644 soc/xtensa/espressif_esp32/esp32s3/Kconfig.series delete mode 100644 soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc delete mode 100644 soc/xtensa/espressif_esp32/esp32s3/default.ld delete mode 100644 soc/xtensa/espressif_esp32/esp32s3/soc.c delete mode 100644 soc/xtensa/intel_adsp/CMakeLists.txt delete mode 100644 soc/xtensa/intel_adsp/Kconfig delete mode 100644 soc/xtensa/intel_adsp/Kconfig.defconfig delete mode 100644 soc/xtensa/intel_adsp/Kconfig.soc delete mode 100644 soc/xtensa/intel_adsp/ace/CMakeLists.txt delete mode 100644 soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm delete mode 100644 soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace20_lnl delete mode 100644 soc/xtensa/intel_adsp/ace/Kconfig.defconfig.series delete mode 100644 soc/xtensa/intel_adsp/ace/Kconfig.series delete mode 100644 soc/xtensa/intel_adsp/ace/Kconfig.soc delete mode 100644 soc/xtensa/intel_adsp/cavs/CMakeLists.txt delete mode 100644 soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series delete mode 100644 soc/xtensa/intel_adsp/cavs/Kconfig.series delete mode 100644 soc/xtensa/intel_adsp/cavs/Kconfig.soc delete mode 100644 soc/xtensa/intel_adsp/common/CMakeLists.txt delete mode 100644 soc/xtensa/nxp_adsp/CMakeLists.txt delete mode 100644 soc/xtensa/nxp_adsp/Kconfig delete mode 100644 soc/xtensa/nxp_adsp/Kconfig.defconfig delete mode 100644 soc/xtensa/nxp_adsp/Kconfig.soc delete mode 100644 soc/xtensa/nxp_adsp/common/CMakeLists.txt delete mode 100644 soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qm delete mode 100644 soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qxp delete mode 100644 soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.series delete mode 100644 soc/xtensa/nxp_adsp/imx8/Kconfig.series delete mode 100644 soc/xtensa/nxp_adsp/imx8/Kconfig.soc delete mode 100644 soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qm delete mode 100644 soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qxp delete mode 100644 soc/xtensa/nxp_adsp/imx8m/Kconfig.defconfig.series delete mode 100644 soc/xtensa/nxp_adsp/imx8m/Kconfig.series delete mode 100644 soc/xtensa/nxp_adsp/imx8m/Kconfig.soc delete mode 100644 soc/xtensa/nxp_adsp/imx8ulp/Kconfig.defconfig.series delete mode 100644 soc/xtensa/nxp_adsp/imx8ulp/Kconfig.series delete mode 100644 soc/xtensa/nxp_adsp/imx8ulp/Kconfig.soc delete mode 100644 soc/xtensa/nxp_adsp/rt5xx/Kconfig.defconfig.series delete mode 100644 soc/xtensa/nxp_adsp/rt5xx/Kconfig.series delete mode 100644 soc/xtensa/nxp_adsp/rt5xx/Kconfig.soc delete mode 100644 soc/xtensa/sample_controller/Kconfig.defconfig delete mode 100644 soc/xtensa/sample_controller/Kconfig.soc create mode 100644 subsys/testsuite/arch/Kconfig.v1 rename subsys/testsuite/boards/{ => boards_legacy}/unit_testing/unit_testing/Kconfig.board (100%) rename subsys/testsuite/boards/{ => boards_legacy}/unit_testing/unit_testing/Kconfig.defconfig (100%) rename subsys/testsuite/boards/{ => boards_legacy}/unit_testing/unit_testing/unit_testing_defconfig (100%) rename subsys/testsuite/soc/{ => soc_legacy}/unit_testing/unit_testing/Kconfig.soc (100%) rename tests/arch/arm/arm_thread_swap_tz/boards/{nucleo_l552ze_q_ns.overlay => nucleo_l552ze_q_stm32l552xx_ns.overlay} (100%) rename tests/arch/common/ramfunc/boards/{arty_a7_arm_designstart_m1.overlay => arty_a7_designstart_fpga_cortex_m1.overlay} (100%) rename tests/benchmarks/latency_measure/boards/{atsame54_xpro.conf => same54_xpro.conf} (100%) rename tests/drivers/adc/adc_api/boards/{arduino_nano_33_ble_sense.overlay => arduino_nano_33_ble_nrf52840_sense.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{hexiwear_k64.overlay => hexiwear_mk64f12.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{hexiwear_kw40z.overlay => hexiwear_mkw40z4.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_A.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{mimxrt1170_evkb_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_B.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{nrf51dk_nrf51422.conf => nrf51dk_nrf51822.conf} (100%) rename tests/drivers/adc/adc_api/boards/{nrf51dk_nrf51422.overlay => nrf51dk_nrf51822.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{rpi_pico_w.overlay => rpi_pico_rp2040_w.overlay} (100%) create mode 100644 tests/drivers/adc/adc_api/boards/sam4e_xpro.overlay rename tests/drivers/adc/adc_api/boards/{sam_e70_xplained.overlay => sam_e70_xplained_same70q21.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{sam_e70b_xplained.overlay => sam_e70_xplained_same70q21b.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{sam_v71_xult.overlay => sam_v71_xult_samv71q21.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{sam_v71b_xult.overlay => sam_v71_xult_samv71q21b.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{atsamc21n_xpro.overlay => samc21n_xpro.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{atsamd20_xpro.overlay => samd20_xpro.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{atsamd21_xpro.overlay => samd21_xpro.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{atsame54_xpro.overlay => same54_xpro.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{atsaml21_xpro.overlay => saml21_xpro.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{atsamr21_xpro.overlay => samr21_xpro.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{atsamr34_xpro.overlay => samr34_xpro.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{xiao_ble_sense.overlay => xiao_ble_nrf52840_sense.overlay} (100%) rename tests/drivers/audio/dmic_api/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename tests/drivers/build_all/counter/boards/{arty_a7_arm_designstart_m1.overlay => arty_a7_designstart_fpga_cortex_m1.overlay} (100%) rename tests/drivers/build_all/dac/boards/{atsamd21_xpro.overlay => samd21_xpro.overlay} (100%) rename tests/drivers/build_all/pwm/boards/{arty_a7_arm_designstart_m1.overlay => arty_a7_designstart_fpga_cortex_m1.overlay} (100%) rename tests/drivers/counter/counter_basic_api/boards/{mimxrt685_evk_cm33_rtc_1khz.overlay => mimxrt685_evk_rtc_1khz.overlay} (100%) rename tests/drivers/counter/counter_basic_api/boards/{nrf51dk_nrf51422.overlay => nrf51dk_nrf51822.overlay} (100%) rename tests/drivers/counter/counter_basic_api/boards/{s32z270dc2_rtu0_r52.overlay => s32z2xxdc2_s32z270_rtu0.overlay} (100%) rename tests/drivers/counter/counter_basic_api/boards/{s32z270dc2_rtu1_r52.overlay => s32z2xxdc2_s32z270_rtu1.overlay} (100%) rename tests/drivers/counter/counter_basic_api/boards/{stm32h747i_disco_m7.overlay => stm32h747i_disco_stm32h747xx_m7.overlay} (100%) rename tests/drivers/counter/maxim_ds3231_api/boards/{nrf51dk_nrf51422.overlay => nrf51dk_nrf51822.overlay} (100%) create mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf create mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay rename tests/drivers/dma/chan_blen_transfer/boards/{mimxrt1170_evk_cm7.conf => mimxrt1160_evk_mimxrt1166_cm7.conf} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1160_evk_mimxrt1166_cm7.overlay} (100%) create mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf create mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay create mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf create mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay create mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf create mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay rename tests/drivers/dma/chan_blen_transfer/boards/{mimxrt595_evk_cm33.conf => mimxrt595_evk_mimxrt595s_cm33.conf} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{atsamc21n_xpro.overlay => samc21n_xpro.overlay} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{atsamd21_xpro.overlay => samd21_xpro.overlay} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{atsaml21_xpro.overlay => saml21_xpro.overlay} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{atsamr34_xpro.overlay => samr34_xpro.overlay} (100%) rename tests/drivers/dma/chan_link_transfer/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1160_evk_mimxrt1166_cm7.overlay} (100%) create mode 100644 tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay rename tests/drivers/dma/loop_transfer/boards/{longan_nano_lite.overlay => longan_nano_gd32vf103_lite.overlay} (100%) create mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf create mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay rename tests/drivers/dma/loop_transfer/boards/{mimxrt1170_evk_cm7.conf => mimxrt1160_evk_mimxrt1166_cm7.conf} (100%) rename tests/drivers/dma/loop_transfer/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1160_evk_mimxrt1166_cm7.overlay} (100%) create mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf create mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay create mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf create mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay create mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf create mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay create mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf rename tests/drivers/dma/loop_transfer/boards/{mimxrt1170_evkb_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_B.overlay} (100%) rename tests/drivers/dma/loop_transfer/boards/{mimxrt595_evk_cm33.conf => mimxrt595_evk_mimxrt595s_cm33.conf} (100%) rename tests/drivers/dma/loop_transfer/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename tests/drivers/dma/loop_transfer/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename tests/drivers/dma/loop_transfer/boards/{atsamc21n_xpro.overlay => samc21n_xpro.overlay} (100%) rename tests/drivers/dma/loop_transfer/boards/{atsamd21_xpro.overlay => samd21_xpro.overlay} (100%) rename tests/drivers/dma/loop_transfer/boards/{atsaml21_xpro.overlay => saml21_xpro.overlay} (100%) rename tests/drivers/dma/loop_transfer/boards/{atsamr34_xpro.overlay => samr34_xpro.overlay} (100%) rename tests/drivers/dma/scatter_gather/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename tests/drivers/dma/scatter_gather/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename tests/drivers/flash/common/boards/{b_u585i_iot02a_ns.overlay => b_u585i_iot02a_stm32u585xx_ns.overlay} (100%) rename tests/drivers/flash/common/boards/{mimxrt595_evk_cm33.conf => mimxrt595_evk_mimxrt595s_cm33.conf} (100%) rename tests/drivers/gpio/gpio_api_1pin/boards/{s32z270dc2_rtu0_r52.overlay => s32z2xxdc2_s32z270_rtu0.overlay} (100%) rename tests/drivers/gpio/gpio_api_1pin/boards/{s32z270dc2_rtu1_r52.overlay => s32z2xxdc2_s32z270_rtu1.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{bl5340_dvk_cpuapp.overlay => bl5340_dvk_nrf5340_cpuapp.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{hifive1_revb.overlay => hifive1_fe310_B.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{lpcxpresso54114_m4.overlay => lpcxpresso54114_lpc54114_m4.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{s32z270dc2_rtu0_r52.overlay => s32z2xxdc2_s32z270_rtu0.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{s32z270dc2_rtu1_r52.overlay => s32z2xxdc2_s32z270_rtu1.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{sam_e70_xplained.overlay => sam_e70_xplained_same70q21.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{atsamd21_xpro.overlay => samd21_xpro.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{stm32h747i_disco_m7.overlay => stm32h747i_disco_stm32h747xx_m7.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{udoo_neo_full_m4.overlay => udoo_neo_full_mcimx6x_m4.overlay} (100%) rename tests/drivers/gpio/gpio_get_direction/boards/{s32z270dc2_rtu0_r52.overlay => s32z2xxdc2_s32z270_rtu0.overlay} (100%) rename tests/drivers/gpio/gpio_get_direction/boards/{s32z270dc2_rtu1_r52.overlay => s32z2xxdc2_s32z270_rtu1.overlay} (100%) rename tests/drivers/gpio/gpio_hogs/boards/{s32z270dc2_rtu0_r52.overlay => s32z2xxdc2_s32z270_rtu0.overlay} (100%) rename tests/drivers/gpio/gpio_hogs/boards/{s32z270dc2_rtu1_r52.overlay => s32z2xxdc2_s32z270_rtu1.overlay} (100%) rename tests/drivers/i2c/i2c_target_api/boards/{mimxrt1170_evkb_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm4_B.overlay} (100%) create mode 100644 tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay rename tests/drivers/i2s/i2s_api/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_A.overlay} (100%) rename tests/drivers/i2s/i2s_api/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename tests/drivers/i2s/i2s_api/boards/{sam_e70_xplained.overlay => sam_e70_xplained_same70q21.overlay} (100%) rename tests/drivers/i2s/i2s_api/boards/{sam_v71_xult.overlay => sam_v71_xult_samv71q21.overlay} (100%) rename tests/drivers/i2s/i2s_speed/boards/{mimxrt1170_evk_cm7.conf => mimxrt1170_evk_mimxrt1176_cm7_A.conf} (100%) rename tests/drivers/i2s/i2s_speed/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_A.overlay} (100%) create mode 100644 tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_rt1176_cm7.conf rename tests/drivers/i2s/i2s_speed/boards/{mimxrt595_evk_cm33.conf => mimxrt595_evk_mimxrt595s_cm33.conf} (100%) rename tests/drivers/i2s/i2s_speed/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename tests/drivers/i2s/i2s_speed/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename tests/drivers/mbox/mbox_data/boards/{lpcxpresso55s69_cpu0.conf => lpcxpresso55s69_lpc55s69_cpu0.conf} (100%) rename tests/drivers/mbox/mbox_data/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) create mode 100644 tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf rename tests/drivers/mbox/mbox_data/boards/{mimxrt1170_evkb_cm7.overlay => mimxrt1160_evk_mimxrt1166_cm7.overlay} (100%) create mode 100644 tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf create mode 100644 tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay create mode 100644 tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf create mode 100644 tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay rename tests/drivers/mbox/mbox_data/remote/boards/{lpcxpresso55s69_cpu1.conf => lpcxpresso55s69_lpc55s69_cpu1.conf} (100%) rename tests/drivers/mbox/mbox_data/remote/boards/{lpcxpresso55s69_cpu1.overlay => lpcxpresso55s69_lpc55s69_cpu1.overlay} (100%) create mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf create mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay create mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf create mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay create mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf create mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay rename tests/drivers/pwm/pwm_api/boards/{rcar_h3ulcb_cr7.overlay => rcar_h3ulcb_r8a77951_r7.overlay} (100%) rename tests/drivers/regulator/voltage/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename tests/drivers/sensor/sbs_gauge/boards/{qemu_arc_hs.overlay => qemu_arc_qemu_arc_hs.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{96b_carbon.conf => 96b_carbon_stm32f401xe.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{96b_carbon.overlay => 96b_carbon_stm32f401xe.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{arty_a7_arm_designstart_m1.conf => arty_a7_designstart_fpga_cortex_m1.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{arty_a7_arm_designstart_m1.overlay => arty_a7_designstart_fpga_cortex_m1.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{longan_nano_lite.overlay => longan_nano_gd32vf103_lite.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{lpcxpresso54114_m4.overlay => lpcxpresso54114_lpc54114_m4.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{mimxrt1170_evkb_cm4.overlay => mimxrt1170_evk_mimxrt1176_cm4_B.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{mimxrt1170_evk_cm7.conf => mimxrt1170_evk_mimxrt1176_cm7_A.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_A.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{mimxrt1170_evkb_cm7.overlay => mimxrt1170_evk_mimxrt1176_cm7_B.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{mimxrt595_evk_cm33.conf => mimxrt595_evk_mimxrt595s_cm33.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{nrf51dk_nrf51422.overlay => nrf51dk_nrf51822.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{tdk_robokit1.conf => robokit1.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{tdk_robokit1.overlay => robokit1.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{rv32m1_vega_ri5cy.overlay => rv32m1_vega_openisa_rv32m1_ri5cy.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{s32z270dc2_rtu0_r52.overlay => s32z2xxdc2_s32z270_rtu0.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{s32z270dc2_rtu1_r52.overlay => s32z2xxdc2_s32z270_rtu1.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{sam_e70_xplained.overlay => sam_e70_xplained_same70q21.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{sam_v71_xult.overlay => sam_v71_xult_samv71q21.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{atsamd21_xpro.conf => samd21_xpro.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{atsamd21_xpro.overlay => samd21_xpro.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{atsame54_xpro.overlay => same54_xpro.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{atsamr21_xpro.conf => samr21_xpro.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{atsamr21_xpro.overlay => samr21_xpro.overlay} (100%) create mode 100644 tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay rename tests/drivers/uart/uart_async_api/boards/{mimxrt1170_evk_cm7.overlay => mimxrt1160_evk_mimxrt1166_cm7.overlay} (100%) create mode 100644 tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay create mode 100644 tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay rename tests/drivers/uart/uart_async_api/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{nucleo_l552ze_q_ns.overlay => nucleo_l552ze_q_stm32l552xx_ns.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{atsamc21n_xpro.overlay => samc21n_xpro.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{atsamd21_xpro.overlay => samd21_xpro.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{atsame54_xpro.overlay => same54_xpro.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{atsaml21_xpro.overlay => saml21_xpro.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{atsamr21_xpro.overlay => samr21_xpro.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{atsamr34_xpro.overlay => samr34_xpro.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{stm32l562e_dk_ns.overlay => stm32l562e_dk_stm32l562xx_ns.overlay} (100%) rename tests/kernel/gen_isr_table/boards/{lpcxpresso54114_m4.conf => lpcxpresso54114_lpc54114_m4.conf} (100%) delete mode 100644 tests/kernel/mbox/mbox_api/boards/qemu_x86_tiny_768.conf rename tests/kernel/mem_protect/mem_map/boards/{qemu_cortex_a53_smp.conf => qemu_cortex_a53_qemu_cortex_a53_smp.conf} (100%) delete mode 100644 tests/kernel/mem_protect/mem_map/boards/qemu_x86_tiny_768.overlay rename tests/kernel/mem_protect/mem_protect/boards/{qemu_cortex_a53_smp.conf => qemu_cortex_a53_qemu_cortex_a53_smp.conf} (100%) delete mode 100644 tests/kernel/mem_protect/stackprot/boards/qemu_x86_tiny_768.conf rename tests/kernel/mem_protect/userspace/boards/{mimxrt595_evk_cm33.overlay => mimxrt595_evk_mimxrt595s_cm33.overlay} (100%) rename tests/kernel/mem_protect/userspace/boards/{mimxrt685_evk_cm33.overlay => mimxrt685_evk.overlay} (100%) rename tests/kernel/smp/boards/{qemu_cortex_a53_smp.conf => qemu_cortex_a53_qemu_cortex_a53_smp.conf} (100%) rename tests/kernel/smp/boards/{qemu_cortex_a53_smp.overlay => qemu_cortex_a53_qemu_cortex_a53_smp.overlay} (100%) rename tests/subsys/fs/fcb/boards/{nrf51dk_nrf51422.conf => nrf51dk_nrf51822.conf} (100%) rename tests/subsys/mgmt/mcumgr/cb_notifications/boards/{qemu_riscv32_smp.conf => qemu_riscv32_qemu_virt_riscv32_smp.conf} (100%) rename tests/subsys/mgmt/mcumgr/cb_notifications/boards/{qemu_riscv64_smp.conf => qemu_riscv64_qemu_virt_riscv64_smp.conf} (100%) rename tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/{qemu_riscv32_smp.conf => qemu_riscv32_qemu_virt_riscv32_smp.conf} (100%) rename tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/{qemu_riscv64_smp.conf => qemu_riscv64_qemu_virt_riscv64_smp.conf} (100%) rename tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/{qemu_arc_hs6x.overlay => qemu_arc_qemu_arc_hs6x.overlay} (100%) rename tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/{qemu_riscv64_smp.conf => qemu_riscv64_qemu_virt_riscv64_smp.conf} (100%) rename tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/{qemu_riscv64_smp.overlay => qemu_riscv64_qemu_virt_riscv64_smp.overlay} (100%) rename tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/{qemu_riscv32_smp.conf => qemu_riscv32_qemu_virt_riscv32_smp.conf} (100%) rename tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/{qemu_riscv64_smp.conf => qemu_riscv64_qemu_virt_riscv64_smp.conf} (100%) rename tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/{qemu_riscv32_smp.conf => qemu_riscv32_qemu_virt_riscv32_smp.conf} (100%) rename tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/{qemu_riscv64_smp.conf => qemu_riscv64_qemu_virt_riscv64_smp.conf} (100%) rename tests/subsys/mgmt/mcumgr/smp_version/boards/{qemu_riscv32_smp.conf => qemu_riscv32_qemu_virt_riscv32_smp.conf} (100%) rename tests/subsys/mgmt/mcumgr/smp_version/boards/{qemu_riscv64_smp.conf => qemu_riscv64_qemu_virt_riscv64_smp.conf} (100%) diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 7888529ee40..0b3755c7d9e 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -20,7 +20,7 @@ jobs: strategy: fail-fast: false matrix: - platform: ["mps2_an385", "native_sim", "qemu_x86", "unit_testing"] + platform: ["mps2/an385", "native_sim", "qemu_x86", "unit_testing"] steps: - name: Apply container owner mismatch workaround run: | diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 219fbfae607..5e6e2cff9a6 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -57,6 +57,8 @@ jobs: # debug ls -la git log --pretty=oneline | head -n 10 + # Increase rename limit to allow for large PRs + git config diff.renameLimit 10000 ./scripts/ci/check_compliance.py --annotate -e KconfigBasic \ -c origin/${BASE_REF}.. diff --git a/.gitignore b/.gitignore index 13c99731c52..15636eaaeac 100644 --- a/.gitignore +++ b/.gitignore @@ -68,14 +68,17 @@ tags # from check_compliance.py BinaryFiles.txt +BoardYml.txt Checkpatch.txt DevicetreeBindings.txt +GitDiffCheck.txt Gitlint.txt Identity.txt ImageSize.txt Kconfig.txt KconfigBasic.txt KconfigBasicNoModules.txt +KconfigHWMv2.txt KeepSorted.txt MaintainersFormat.txt ModulesMaintainers.txt diff --git a/CMakeLists.txt b/CMakeLists.txt index a229c06413e..131a7fc8a5e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -118,7 +118,7 @@ zephyr_include_directories( include(${ZEPHYR_BASE}/cmake/linker_script/${ARCH}/linker.cmake OPTIONAL) -zephyr_include_directories(${SOC_DIR}/${ARCH}/${SOC_PATH}) +zephyr_include_directories(${SOC_FULL_DIR}) # Don't inherit compiler flags from the environment foreach(var AFLAGS CFLAGS CXXFLAGS CPPFLAGS LDFLAGS) diff --git a/CODEOWNERS b/CODEOWNERS index df8b4cb4d42..bd6bbf17e86 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -19,13 +19,7 @@ # entries that are not covered by the MAINTAINERS file. /soc/arm/aspeed/ @aspeeddylan -/soc/arm/atmel_sam/common/*_sam4l_*.c @nandojve -/soc/arm/atmel_sam/sam3x/ @ioannisg -/soc/arm/atmel_sam/sam4e/ @nandojve -/soc/arm/atmel_sam/sam4l/ @nandojve -/soc/arm/atmel_sam/sam4s/ @fallrisk -/soc/arm/atmel_sam/same70/ @nandojve -/soc/arm/atmel_sam/samv71/ @nandojve +/soc/atmel/ @nandojve /soc/arm/bcm*/ @sbranden /soc/arm/infineon_cat1/ @ifyall @npal-cy /soc/arm/infineon_xmc/ @parthitce @@ -101,11 +95,7 @@ /boards/arm/rpi_pico/ @yonsch /boards/arm/ronoth_lodev/ @NorthernDean /boards/arm/xmc45_relax_kit/ @parthitce -/boards/arm/sam4e_xpro/ @nandojve -/boards/arm/sam4l_ek/ @nandojve -/boards/arm/sam4s_xplained/ @fallrisk -/boards/arm/sam_e70_xplained/ @nandojve -/boards/arm/sam_v71_xult/ @nandojve +/boards/atmel/ @nandojve /boards/arm/scobc_module1/ @yashi /boards/arm/v2m_beetle/ @fvincenzo /boards/arm/olimexino_stm32/ @ydamigos @@ -411,13 +401,7 @@ /dts/arc/ @abrodkin @ruuddw @iriszzw @evgeniy-paltsev /dts/arm/acsip/ @NorthernDean /dts/arm/aspeed/ @aspeeddylan -/dts/arm/atmel/sam4e* @nandojve -/dts/arm/atmel/sam4l* @nandojve -/dts/arm/atmel/samr21.dtsi @benpicco -/dts/arm/atmel/sam*5*.dtsi @benpicco -/dts/arm/atmel/same70* @nandojve -/dts/arm/atmel/samv71* @nandojve -/dts/arm/atmel/ @galak +/dts/arm/atmel/ @galak @nandojve /dts/arm/broadcom/ @sbranden /dts/arm/cypress/ @ifyall @npal-cy /dts/arm/gd/ @nandojve @@ -428,7 +412,7 @@ /dts/arm64/nxp/ @JiafeiPan /dts/arm64/renesas/ @lorc @xakep-amatop /dts/arm/quicklogic/ @fkokosinski @kgugala -/dts/arm/seeed/ @str4t0m +/dts/arm/seeed_studio/ @str4t0m /dts/arm/st/ @erwango /dts/arm/st/h7/*stm32h735* @benediktibk /dts/arm/st/l4/*stm32l451* @benediktibk @@ -475,6 +459,7 @@ /dts/bindings/counter/snps,dw-timers.yaml @pbalsundar /dts/bindings/wifi/*esp-at.yaml @mniestroj /dts/bindings/*/*gd32* @nandojve +/dts/bindings/*/*sam* @nandojve /dts/bindings/*/*npcx* @MulinChao @ChiHuaL /dts/bindings/*/*psoc6* @ifyall @npal-cy /dts/bindings/*/*infineon*cat1* @ifyall @npal-cy diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 5ad2fb2bf85..eb4399c297f 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -21,12 +21,11 @@ osource "$(KCONFIG_BINARY_DIR)/Kconfig.shield.defconfig" # This loads Zephyr base shield defconfigs source "boards/shields/*/Kconfig.defconfig" -source "$(BOARD_DIR)/Kconfig.defconfig" +osource "$(BOARD_DIR)/Kconfig.defconfig" + +# This loads Zephyr specific SoC root defconfigs +source "$(KCONFIG_BINARY_DIR)/soc/Kconfig.defconfig" -# This loads custom SoC root defconfigs -osource "$(KCONFIG_BINARY_DIR)/Kconfig.soc.defconfig" -# This loads Zephyr base SoC root defconfigs -osource "soc/$(ARCH)/*/Kconfig.defconfig" # This loads the toolchain defconfigs osource "$(TOOLCHAIN_KCONFIG_DIR)/Kconfig.defconfig" # This loads the testsuite defconfig @@ -644,7 +643,7 @@ config BUILD_OUTPUT_UF2_FAMILY_ID default "0x1c5f21b0" if SOC_SERIES_ESP32 default "0x621e937a" if SOC_NRF52833_QIAA default "0xada52840" if SOC_NRF52840_QIAA - default "0x4fb2d5bd" if SOC_SERIES_IMX_RT + default "0x4fb2d5bd" if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX default "0x2abc77ec" if SOC_SERIES_LPC55XXX default "0xe48bff56" if SOC_SERIES_RP2XXX default "0x68ed2b88" if SOC_SERIES_SAMD21 @@ -906,7 +905,7 @@ config BOOTLOADER_SRAM_SIZE_DEPRECATED config BOOTLOADER_ESP_IDF bool "ESP-IDF bootloader support" - depends on SOC_FAMILY_ESP32 && !BOOTLOADER_MCUBOOT && !MCUBOOT + depends on SOC_FAMILY_ESPRESSIF_ESP32 && !BOOTLOADER_MCUBOOT && !MCUBOOT default y help This option will trigger the compilation of the ESP-IDF bootloader diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index d8f9047277d..2d59af46304 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -166,9 +166,7 @@ ARM arch: - include/zephyr/arch/arm/ - tests/arch/arm/ - doc/hardware/arch/arm_cortex_m.rst - - boards/arm/qemu_cortex_m3/ - - boards/arm/qemu_cortex_m0/ - - soc/arm/* + - boards/qemu/cortex_m0/ labels: - "area: ARM" tests: @@ -186,9 +184,9 @@ ARM64 arch: - arch/arm64/ - include/zephyr/arch/arm64/ - tests/arch/arm64/ - - soc/arm64/ - - boards/arm64/ - dts/arm64/ + - boards/qemu/kvm_arm64/ + - boards/qemu/cortex_a53/ labels: - "area: ARM64" tests: @@ -198,8 +196,11 @@ ARM Platforms: status: odd fixes files: - boards/arm/mps*/ - - soc/arm/arm/ - boards/arm/v2m_*/ + - soc/arm/mps*/ + - soc/arm/musca/ + - soc/arm/beetle/ + - soc/arm/fvp_aemv8r/aarch32/ - dts/arm/armv*.dtsi labels: - "platform: ARM" @@ -207,7 +208,7 @@ ARM Platforms: ASPEED Platforms: status: odd fixes files: - - soc/arm/aspeed/ + - soc/aspeed/ - dts/arm/aspeed/ - drivers/*/*_ast10x0.c - drivers/*/Kconfig.aspeed @@ -230,10 +231,9 @@ ARM SiP SVC: MIPS arch: status: odd fixes files: - - soc/mips/ - arch/mips/ - include/zephyr/arch/mips/ - - boards/mips/ + - boards/qemu/malta/ labels: - "area: MIPS" tests: @@ -249,8 +249,8 @@ Ambiq Platforms: - aaronyegx - RichardSWheatley files: - - soc/arm/ambiq/ - - boards/arm/apollo*/ + - soc/ambiq/ + - boards/ambiq/apollo*/ - dts/arm/ambiq/ - dts/bindings/*/ambiq,* - drivers/*/*ambiq* @@ -268,8 +268,7 @@ BeagleBoard Platforms: - con-pax - vaishnavachath files: - - boards/arm/beagle*/ - - boards/riscv/beagle*/ + - boards/beagle/ labels: - "platform: BeagleBoard" @@ -524,7 +523,7 @@ Board/SoC configuration: - nordicjm - "57300" files: - - soc/Kconfig + - soc/Kconfig* - boards/Kconfig labels: - "area: Board/SoC configuration" @@ -2011,8 +2010,8 @@ Xen Platform: - include/zephyr/xen/ - drivers/xen/ - arch/arm64/core/xen/ - - soc/arm64/xenvm/ - - boards/arm64/xenvm/ + - soc/xen/ + - boards/xen/ labels: - "area: Xen Platform" @@ -2070,7 +2069,7 @@ Google Platforms: - fabiobaltieri - keith-zephyr files: - - boards/*/google_*/ + - boards/google/ - samples/boards/google_*/ Hash Utilities: @@ -2303,12 +2302,7 @@ Laird Connectivity platforms: collaborators: - greg-leach files: - - boards/arm/bl5340_dvk/ - - boards/arm/bl65*/ - - boards/arm/bt510/ - - boards/arm/bt610/ - - boards/arm/pinnacle_100_dvk/ - - boards/arm/mg100/ + - boards/lairdconnect/ labels: - "platform: Laird Connectivity" @@ -2513,10 +2507,10 @@ Native POSIX/Sim and POSIX arch: - aescolar files: - arch/posix/ - - boards/posix/common/ - - boards/posix/native_*/ - - boards/posix/doc/ - - boards/posix/*.rst + - boards/native/common/ + - boards/native/native_*/ + - boards/native/doc/ + - boards/native/*.rst - drivers/*/*posix* - drivers/*/*native* - drivers/*/*/*posix* @@ -2525,7 +2519,7 @@ Native POSIX/Sim and POSIX arch: - include/zephyr/arch/posix/ - scripts/native_simulator/ - scripts/valgrind.supp - - soc/posix/ + - soc/native/ - tests/boards/native_sim/ labels: - "area: native port" @@ -2769,11 +2763,11 @@ NIOS-2 arch: - arch/nios2/ - dts/nios2/intel/ - boards/common/nios2.board.cmake - - boards/nios2/ - - soc/nios2/ + - soc/altr/*nios2*/ - include/zephyr/arch/nios2/ - tests/boards/altera_max10/ - - boards/nios2/qemu_nios2/ + - boards/qemu/nios2/ + - boards/altr/max10/ - scripts/support/quartus-flash.py labels: - "area: NIOS2" @@ -2785,7 +2779,7 @@ nRF BSIM: maintainers: - aescolar files: - - boards/posix/nrf_bsim/ + - boards/native/nrf_bsim/ - tests/boards/nrf52_bsim/ - tests/bsim/ files-exclude: @@ -2846,7 +2840,7 @@ Power management: "Quicklogic Platform": status: odd fixes files: - - soc/arm/quicklogic_eos_s3/ + - soc/quicklogic/ - dts/arm/quicklogic/ labels: - "platform: Quicklogic" @@ -2865,10 +2859,14 @@ RISCV arch: - npitre files: - arch/riscv/ - - boards/riscv/ + - boards/qemu/riscv*/ + - boards/sifive/ + - boards/sparkfun/red_v_things_plus/ - dts/bindings/riscv/ - dts/riscv/ - include/zephyr/arch/riscv/ + - soc/common/riscv-privileged/ + - soc/sifive/ - soc/riscv/ - tests/arch/riscv/ - doc/hardware/arch/risc-v.rst @@ -3009,9 +3007,19 @@ SPARC arch: files: - arch/sparc/ - include/zephyr/arch/sparc/ - - soc/sparc/ - - boards/sparc/ - dts/sparc/ + - boards/qemu/leon3/ + labels: + - "area: SPARC" + +Gaisler Platforms: + status: odd fixes + collaborators: + - julius-barendt + files: + - dts/sparc/gaisler/ + - soc/gaisler/ + - boards/gaisler/ labels: - "area: SPARC" @@ -3039,7 +3047,7 @@ ADI Platforms: - galak - microbuilder files: - - boards/arm/adi_*/ + - boards/adi/ - drivers/*/max* - drivers/*/*max*/ - drivers/dac/dac_ltc* @@ -3058,8 +3066,8 @@ Broadcom Platforms: status: odd fixes files: - dts/arm/broadcom/ - - soc/arm/bcm_vk/ - - boards/arm/bcm95840*/ + - soc/brcm/ + - boards/brcm/ GD32 Platforms: status: maintained @@ -3070,14 +3078,12 @@ GD32 Platforms: - gmarull - soburi files: - - boards/arm/gd32*/ - - boards/riscv/gd32*/ - - boards/riscv/longan_nano/ + - boards/gd/ - drivers/*/*gd32* - dts/*/gd/ - dts/bindings/*/*gd32* - - soc/*/gd_gd32/ - scripts/west_commands/*/*gd32* + - soc/gd/gd32/ labels: - "platform: GD32" description: >- @@ -3093,8 +3099,8 @@ Synopsys Platforms: - evgeniy-paltsev - IRISZZW files: - - soc/arc/ - - boards/arc/ + - soc/synopsys/ + - boards/synopsys/ - samples/boards/arc_secure_services/ labels: - "platform: Synopsys" @@ -3112,8 +3118,8 @@ Nuvoton NPCX Platforms: - jackrosenthal - fabiobaltieri files: - - soc/arm/nuvoton_npcx/ - - boards/arm/npcx*/ + - soc/nuvoton/npcx/ + - boards/nuvoton/npcx*/ - dts/arm/nuvoton/ - dts/bindings/*/*npcx* - drivers/*/*_npcx*.c @@ -3127,10 +3133,9 @@ Nuvoton Numicro Numaker Platforms: collaborators: - ssekar15 files: - - soc/arm/nuvoton_numicro/ - - soc/arm/nuvoton_numaker/ - - boards/arm/nuvoton_pfm*/ - - boards/arm/numaker_*/ + - soc/nuvoton/numaker/ + - soc/nuvoton/numicro/ + - boards/nuvoton/numaker*/ - dts/arm/nuvoton/ - dts/bindings/*/*numicro* - dts/bindings/*/*numaker* @@ -3146,15 +3151,15 @@ Raspberry Pi Pico Platforms: collaborators: - soburi files: - - boards/arm/rpi_pico/ - - boards/arm/adafruit_kb2040/ - - boards/arm/sparkfun_pro_micro_rp2040/ + - boards/raspberrypi/ + - boards/adafruit/kb2040/ + - boards/sparkfun/pro_micro_rp2040/ - dts/arm/rpi_pico/ - dts/bindings/*/raspberrypi,pico* - drivers/*/*rpi_pico - drivers/*/*rpi_pico*/ - drivers/*/*rpi_pico*.c - - soc/arm/rpi_pico/ + - soc/raspberrypi/ labels: - "platform: Raspberry Pi Pico" @@ -3165,8 +3170,8 @@ SiLabs Platforms: collaborators: - tgorochowik files: - - soc/arm/silabs_*/ - - boards/arm/ef*/ + - soc/silabs/ + - boards/silabs/ - dts/arm/silabs/ - dts/bindings/*/silabs* - drivers/*/*_gecko* @@ -3181,9 +3186,13 @@ Intel Platforms (X86): - tbursztyka - laurenmurphyx64 files: - - boards/x86/ + - boards/intel/adl/ + - boards/intel/ehl/ + - boards/intel/rpl/ - dts/x86/intel/ - - soc/x86/ + - soc/intel/atom/ + - soc/intel/lakemont/ + - soc/intel/*_lake/ - samples/boards/up_squared/ labels: - "platform: X86" @@ -3205,8 +3214,8 @@ Intel Platforms (Xtensa): - jxstelter - marcinszkudlinski files: - - boards/xtensa/intel_*/ - - soc/xtensa/intel_*/ + - boards/intel/adsp/ + - soc/intel/intel_adsp/ - dts/xtensa/intel/ - tests/boards/intel_adsp/ - samples/boards/intel_adsp/ @@ -3223,8 +3232,8 @@ Intel Platforms (ISH): - teburd - likongintel files: - - boards/x86/intel_ish/ - - soc/x86/intel_ish/ + - boards/intel/ish/ + - soc/intel/intel_ish/ - dts/x86/intel/intel_ish* - dts/bindings/*/intel,sedi* - drivers/*/*sedi* @@ -3239,8 +3248,8 @@ Intel Platforms (Agilex): - nbalabak - teikheng files: - - boards/arm64/intel_*/ - - soc/arm64/intel_*/ + - boards/intel/socfpga/ + - soc/intel/intel_socfpga/ - dts/arm64/intel/ - dts/bindings/*/intel,agilex* - dts/arm/intel_socfpga_std/ @@ -3272,17 +3281,13 @@ NXP Drivers: - include/zephyr/drivers/*/*mcux* - arch/arm/core/mpu/nxp_mpu.c - dts/bindings/*/nxp* - files-exclude: - - drivers/*/*s32* - - drivers/misc/*/*s32* - - include/zephyr/dt-bindings/*/*s32* - - include/zephyr/drivers/*/*s32* - - dts/bindings/*/*s32* + files-regex-exclude: + - .*s32.* labels: - "platform: NXP Drivers" description: NXP Drivers -NXP Platforms (MCUX): +NXP Platforms (MCU): status: maintained maintainers: - dleach02 @@ -3294,23 +3299,21 @@ NXP Platforms (MCUX): - EmilioCBen - decsny files: - - boards/arm/mimx*/ - - boards/arm/frdm*/ - - boards/arm/lpcxpress*/ - - boards/arm/twr_*/ - - boards/arm/vmu*/ - - soc/arm/nxp_imx/ - - soc/arm/nxp_kinetis/ - - soc/arm/nxp_lpc/ + - boards/nxp/mimxrt*/ + - boards/nxp/frdm*/ + - boards/nxp/lpcxpress*/ + - boards/nxp/twr_*/ + - boards/nxp/vmu*/ + - soc/nxp/imxrt/ + - soc/nxp/kinetis/ + - soc/nxp/lpc/ - dts/arm/nxp/ - samples/boards/nxp*/ - files-exclude: - - boards/arm/*s32*/ - - dts/arm/nxp/*s32* - - samples/boards/nxp_s32/ + files-regex-exclude: + - .*s32.* labels: - "platform: NXP" - description: NXP Platforms supported by MCUXpresso suite + description: NXP MCU Platforms supported by MCUXpresso suite NXP Platforms (S32): status: maintained @@ -3321,11 +3324,11 @@ NXP Platforms (S32): - bperseghetti - Dat-NguyenDuy files: - - boards/arm/s32*/ - - boards/arm/mr_canhubk3/ - - boards/arm/ucans32k1sic/ + - boards/nxp/s32*/ + - boards/nxp/mr_canhubk3/ + - boards/nxp/ucans32k1sic/ - boards/common/*nxp_s32* - - soc/arm/nxp_s32/ + - soc/nxp/s32/ - drivers/*/*nxp_s32* - drivers/misc/*nxp_s32*/ - dts/bindings/*/nxp,s32* @@ -3338,6 +3341,26 @@ NXP Platforms (S32): - "platform: NXP S32" description: NXP S32 platforms and S32-specific drivers +NXP Platforms (MPU): + status: maintained + maintainers: + - dleach + collaborators: + - JiafeiPan + - dbaluta + - iuliana-prodan + - danieldegrasse + - decsny + - yvanderv + files: + - soc/nxp/imx/ + - soc/nxp/layerscape/ + files-regex: + - boards/nxp/m?imx[^(rt)].*/ + labels: + - "platform: NXP MPU" + description: NXP MPU platforms + NXP Platforms (Xtensa): status: maintained maintainers: @@ -3345,10 +3368,10 @@ NXP Platforms (Xtensa): collaborators: - iuliana-prodan files: - - soc/xtensa/nxp_adsp/ - - boards/xtensa/nxp_adsp_*/ + - soc/nxp/imx/*/adsp/ + - soc/nxp/imxrt/imxrt5xx/f1/ labels: - - "platform: NXP ADSP" + - "platform: NXP Xtensa" description: NXP Xtensa platforms Microchip MEC Platforms: @@ -3359,9 +3382,9 @@ Microchip MEC Platforms: - VenkatKotakonda - albertofloyd files: - - boards/arm/mec*/ + - boards/microchip/mec*/ - dts/arm/microchip/ - - soc/arm/microchip_mec/ + - soc/microchip/mec/ - drivers/*/*mchp*.c - tests/boards/mec15xxevb_assy6853/ - tests/boards/mec172xevb_assy6906/ @@ -3379,10 +3402,9 @@ Microchip SAM Platforms: - mnkp - stephanosio files: - - boards/arm/atsam*/ - - boards/arm/sam*/ + - boards/atmel/ - dts/arm/atmel/ - - soc/arm/atmel_sam*/ + - soc/atmel/ - drivers/*/*sam*.c - dts/bindings/*/atmel,* labels: @@ -3393,9 +3415,9 @@ nRF Platforms: maintainers: - anangl files: - - boards/arm/*nrf*/ + - boards/nordic/ - drivers/*/*nrfx*.c - - soc/arm/nordic_nrf/ + - soc/nordic/ - samples/boards/nrf/ - dts/arm/nordic/ - dts/bindings/*/nordic,* @@ -3409,11 +3431,11 @@ Renesas SmartBond Platforms: - andrzej-kaczmarek - blauret files: - - boards/arm/da14*/ + - boards/renesas/da14*/ - drivers/*/*smartbond* - dts/arm/renesas/smartbond/ - dts/bindings/*/renesas,smartbond* - - soc/arm/renesas_smartbond/ + - soc/renesas/smartbond/ labels: - "platform: Renesas SmartBond" description: >- @@ -3425,11 +3447,11 @@ Renesas RA Platforms: maintainers: - soburi files: - - boards/arm/arduino_uno_r4/ + - boards/arduino/uno_r4_minima/ - drivers/*/*renesas_ra* - dts/arm/renesas/ra/ - dts/bindings/*/*renesas,ra* - - soc/arm/renesas_ra/ + - soc/renesas/ra/ labels: - "platforms: Renesas RA" description: >- @@ -3441,11 +3463,11 @@ Renesas RZ Platforms: maintainers: - tgorochowik files: - - boards/arm/rzt2m_*/ + - boards/renesas/rzt2m_*/ - drivers/*/*rzt2m* - dts/arm/renesas/rz/ - dts/bindings/*/*rzt2m* - - soc/arm/renesas_rzt2m/ + - soc/renesas/rzt2m/ labels: - "platforms: Renesas RZ" description: >- @@ -3461,15 +3483,13 @@ Renesas R-Car Platforms: - xakep-amatop files: - dts/arm/renesas/rcar/ - - boards/arm/rcar_*/ - - boards/arm64/rcar_*/ + - boards/renesas/rcar_*/ - drivers/*/*rcar* - drivers/clock_control/*cpg_mssr* - dts/arm/renesas/rcar/ - dts/arm64/renesas/ - dts/bindings/*/*rcar* - - soc/arm/renesas_rcar/ - - soc/arm64/renesas_rcar/ + - soc/renesas/rcar/ labels: - "platform: Renesas R-Car" description: >- @@ -3488,11 +3508,7 @@ STM32 Platforms: - Desvauxm-st - GeorgeCGV files: - - boards/arm/b_*/ - - boards/arm/nucleo_*/ - - boards/arm/stm32*_disco/ - - boards/arm/stm32*_dk*/ - - boards/arm/stm32*_eval/ + - boards/st/ - drivers/*/*stm32*/ - drivers/*/*stm32*.c - drivers/*/*stm32*.h @@ -3500,7 +3516,7 @@ STM32 Platforms: - drivers/*/*stm32* - dts/arm/st/ - dts/bindings/*/*stm32* - - soc/arm/st_stm32/ + - soc/st/stm32/ - samples/boards/stm32/ labels: - "platform: STM32" @@ -3518,16 +3534,14 @@ Espressif Platforms: - uLipe files: - drivers/*/*esp32*.c - - boards/xtensa/esp32*/ - - soc/xtensa/espressif_esp32*/ - - boards/riscv/esp32*/ - - soc/riscv/espressif_esp32*/ + - boards/espressif/ + - soc/espressif/ - dts/xtensa/espressif/ - dts/riscv/espressif/ - dts/bindings/*/*esp32* - samples/boards/esp32*/ - tests/boards/espressif_esp32/ - - drivers/wifi/esp32/ + - drivers/*/*esp32*/ labels: - "platform: ESP32" @@ -3543,13 +3557,13 @@ ITE Platforms: - brockus-zephyr - sjg20 files: - - boards/riscv/it8*_evb/ + - boards/ite/ - drivers/*/*/*it8xxx2*.c - drivers/*/*it8xxx2*.c - drivers/*/*_ite_* - dts/bindings/*/*ite* - dts/riscv/ite/ - - soc/riscv/ite_ec/ + - soc/ite/ labels: - "platform: ITE" @@ -3560,17 +3574,15 @@ TI SimpleLink Platforms: collaborators: - vanti files: - - boards/arm/cc13*/ - - boards/arm/cc26*/ - - boards/arm/cc32*/ - - boards/*/msp*/ + - boards/ti/cc*/ + - boards/ti/msp*/ - drivers/*/*cc13* - drivers/*/*cc25* - drivers/*/*cc26* - drivers/*/*cc32* - dts/arm/ti/ - dts/bindings/*/ti,* - - soc/arm/ti_simplelink/ + - soc/ti/simplelink/ - dts/bindings/*/ti,* - modules/Kconfig.simplelink labels: @@ -3583,18 +3595,18 @@ TI K3 Platforms: collaborators: - gramsay0 files: - - boards/*/*phycore_am6*/ - - boards/*/am6*/ + - boards/phytec/*am62*/ + - boards/ti/*am62*/ - drivers/*/*ti_k3* - dts/bindings/*/ti,k3* - - soc/*/ti_k3/ + - soc/ti/k3/ labels: - "platform: TI K3" TI Platforms: status: odd fixes files: - - soc/arm/ti_lm3s6965/ + - soc/ti/lm3s6965/ - dts/arm/ti/lm3s6965.dtsi labels: - "platform: TI" @@ -3609,7 +3621,7 @@ Xilinx Platforms: - dts/*/xilinx/ - dts/bindings/*/*xlnx* - include/zephyr/*/*/*xlnx* - - soc/arm/xilinx*/ + - soc/xlnx/ labels: - "platform: Xilinx" @@ -3621,18 +3633,17 @@ Infineon Platforms: - npal-cy - talih0 files: - - boards/arm/cy8ckit_*/ - - boards/arm/cy8cproto_*/ - - boards/arm/xmc*_relax*/ + - boards/cypress/ + - boards/infineon/ - drivers/*/*ifx_cat1* - drivers/*/*xmc*/ - drivers/*/*xmc*.c - drivers/*/*/*xmc* - dts/arm/infineon/ - dts/arm/cypress/ - - soc/arm/cypress/ + - soc/cypress/ - dts/bindings/*/*infineon* - - soc/arm/infineon_*/ + - soc/infineon/ labels: - "platform: Infineon" description: >- @@ -3644,7 +3655,7 @@ Panasonic Platforms: maintainers: - pideu-sj files: - - boards/arm/pan17*/ + - boards/panasonic/ labels: - "platform: Panasonic" @@ -4588,11 +4599,11 @@ Xtensa arch: - arch/xtensa/ - include/zephyr/arch/xtensa/ - dts/xtensa/ - - boards/xtensa/qemu_xtensa/ - - boards/xtensa/xt-sim/ - - soc/xtensa/dc233c/ - - soc/xtensa/sample_controller/ - - soc/xtensa/CMakeLists.txt + - boards/qemu/xtensa/ + - boards/cdns/xt-sim/ + - soc/cdns/dc233c/ + - soc/cdns/dc233c/ + - soc/cdns/xtensa_sample_controller/ labels: - "area: Xtensa" @@ -4698,8 +4709,8 @@ Testing with Renode: - fkokosinski files: - cmake/emu/renode.cmake - - boards/*/*/support/*.repl - - boards/*/*/support/*.resc + - boards/**/*/support/*.repl + - boards/**/*/support/*.resc labels: - "area: Renode" diff --git a/arch/Kconfig b/arch/Kconfig index 1e28103509f..4a90eb395d3 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -8,8 +8,10 @@ # Include these first so that any properties (e.g. defaults) below can be # overridden (by defining symbols in multiple locations) -# Note: $ARCH might be a glob pattern -source "$(ARCH_DIR)/$(ARCH)/Kconfig" +source "$(ARCH_DIR)/Kconfig.$(HWM_SCHEME)" + +# ToDo: Generate a Kconfig.arch for loading of additional arch in HWMv2. +osource "$(KCONFIG_BINARY_DIR)/Kconfig.arch" # Architecture symbols # @@ -1019,27 +1021,6 @@ config ARCH help System architecture string. -config SOC - string - help - SoC name which can be found under soc//. - This option holds the directory name used by the build system to locate - the correct linker and header files for the SoC. - -config SOC_SERIES - string - help - SoC series name which can be found under soc///. - This option holds the directory name used by the build system to locate - the correct linker and header files. - -config SOC_FAMILY - string - help - SoC family name which can be found under soc//. - This option holds the directory name used by the build system to locate - the correct linker and header files. - config TOOLCHAIN_HAS_BUILTIN_FFS bool default y if !(64BIT && RISCV) diff --git a/arch/Kconfig.v1 b/arch/Kconfig.v1 new file mode 100644 index 00000000000..d76acba59a3 --- /dev/null +++ b/arch/Kconfig.v1 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Note: $ARCH might be a glob pattern +source "$(ARCH_DIR)/$(ARCH)/Kconfig" diff --git a/arch/Kconfig.v2 b/arch/Kconfig.v2 new file mode 100644 index 00000000000..19db8d46246 --- /dev/null +++ b/arch/Kconfig.v2 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +source "$(KCONFIG_BINARY_DIR)/arch/Kconfig" diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 5dee9d76b84..8a3bd5b1b3c 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -9,7 +9,6 @@ menu "ARC Options" config ARCH default "arc" - config CPU_ARCEM bool select ATOMIC_OPERATIONS_C @@ -380,8 +379,6 @@ config ARC_EARLY_SOC_INIT (before C runtime initialization). Setup code is called in form of soc_early_asm_init_percpu assembler macro. -endmenu - config MAIN_STACK_SIZE default 4096 if 64BIT @@ -408,3 +405,5 @@ config CMSIS_V2_THREAD_MAX_STACK_SIZE config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE default 2048 if 64BIT + +endmenu diff --git a/arch/archs.yml b/arch/archs.yml new file mode 100644 index 00000000000..e07d10ffe80 --- /dev/null +++ b/arch/archs.yml @@ -0,0 +1,21 @@ +archs: + - name: arc + path: arc + - name: arm + path: arm + - name: arm64 + path: arm64 + - name: mips + path: mips + - name: nios2 + path: nios2 + - name: posix + path: posix + - name: riscv + path: riscv + - name: sparc + path: sparc + - name: xtensa + path: xtensa + - name: x86 + path: x86 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8b0d53ec3cf..3f5f3075777 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -82,4 +82,47 @@ config ARM_ON_EXIT_CPU_IDLE rsource "core/Kconfig" rsource "core/Kconfig.vfp" +# General options signifying CPU capabilities of ARM SoCs +config CPU_HAS_ARM_MPU + bool + select CPU_HAS_MPU + help + This option is enabled when the CPU has a Memory Protection Unit (MPU) + in ARM flavor. + +config CPU_HAS_NXP_MPU + bool + select CPU_HAS_MPU + help + This option is enabled when the CPU has a Memory Protection Unit (MPU) + in NXP flavor. + +config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + bool "Custom fixed SoC MPU region definition" + help + If enabled, this option signifies that the SoC will + define and configure its own fixed MPU regions in the + SoC definition. These fixed MPU regions are currently + used to set Flash and SRAM default access policies and + they are programmed at boot time. + +config CPU_HAS_ARM_SAU + bool + select CPU_HAS_TEE + help + MCU implements the ARM Security Attribution Unit (SAU). + +config CPU_HAS_NRF_IDAU + bool + select CPU_HAS_TEE + help + MCU implements the nRF (vendor-specific) Security Attribution Unit. + (IDAU: "Implementation-Defined Attribution Unit", in accordance with + ARM terminology). + +config HAS_SWO + bool + help + When enabled, indicates that SoC has an SWO output + endmenu diff --git a/arch/arm/core/cortex_m/timing.c b/arch/arm/core/cortex_m/timing.c index 861f1a9995a..3b847af02ac 100644 --- a/arch/arm/core/cortex_m/timing.c +++ b/arch/arm/core/cortex_m/timing.c @@ -28,8 +28,8 @@ */ static inline uint64_t z_arm_dwt_freq_get(void) { -#if defined(CONFIG_SOC_FAMILY_NRF) || \ - defined(CONFIG_SOC_SERIES_IMX_RT6XX) +#if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) || \ + defined(CONFIG_SOC_SERIES_IMXRT6XX) /* * DWT frequency is taken directly from the * System Core clock (CPU) frequency, if the @@ -77,7 +77,7 @@ static inline uint64_t z_arm_dwt_freq_get(void) } return dwt_frequency; -#endif /* CONFIG_SOC_FAMILY_NRF */ +#endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */ } void arch_timing_init(void) diff --git a/arch/common/CMakeLists.txt b/arch/common/CMakeLists.txt index 409c378f620..78fc6396ed6 100644 --- a/arch/common/CMakeLists.txt +++ b/arch/common/CMakeLists.txt @@ -71,7 +71,7 @@ zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY # Only ARM, X86 and OPENISA_RV32M1_RISCV32 use ROM_START_OFFSET. if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64 - OR DEFINED CONFIG_SOC_OPENISA_RV32M1_RISCV32) + OR DEFINED CONFIG_SOC_OPENISA_RV32M1) # Exclamation mark is printable character with lowest number in ASCII table. # We are sure that this file will be included as a first. zephyr_linker_sources(ROM_START SORT_KEY ! rom_start_address.ld) diff --git a/arch/riscv/core/fatal.c b/arch/riscv/core/fatal.c index 36457a23de7..d0f789a328d 100644 --- a/arch/riscv/core/fatal.c +++ b/arch/riscv/core/fatal.c @@ -163,7 +163,7 @@ void _Fault(z_arch_esf_t *esf) __asm__ volatile("csrr %0, mcause" : "=r" (mcause)); -#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32 +#ifndef CONFIG_SOC_OPENISA_RV32M1 unsigned long mtval; __asm__ volatile("csrr %0, mtval" : "=r" (mtval)); #endif @@ -171,7 +171,7 @@ void _Fault(z_arch_esf_t *esf) mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK; LOG_ERR(""); LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause)); -#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32 +#ifndef CONFIG_SOC_OPENISA_RV32M1 LOG_ERR(" mtval: %lx", mtval); #endif diff --git a/arch/x86/core/early_serial.c b/arch/x86/core/early_serial.c index 3a0bc7465e1..a2abafbf05e 100644 --- a/arch/x86/core/early_serial.c +++ b/arch/x86/core/early_serial.c @@ -8,7 +8,6 @@ #include #include #include -#include #if DT_PROP_OR(DT_CHOSEN(zephyr_console), io_mapped, 0) != 0 diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index db0909bb4f8..e9271d4982f 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -53,7 +53,7 @@ file(WRITE ${CORE_ISA_IN} "#include \n") add_custom_command(OUTPUT ${CORE_ISA_DM} COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__ -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} - -I${SOC_DIR}/${ARCH}/${SOC_PATH} + -I${SOC_FULL_DIR} ${CORE_ISA_IN} -o ${CORE_ISA_DM}) # Generates a list of device-specific scratch register choices diff --git a/boards/arm/96b_aerocore2/96b_aerocore2.dts b/boards/96boards/aerocore2/96b_aerocore2.dts similarity index 100% rename from boards/arm/96b_aerocore2/96b_aerocore2.dts rename to boards/96boards/aerocore2/96b_aerocore2.dts diff --git a/boards/arm/96b_aerocore2/96b_aerocore2.yaml b/boards/96boards/aerocore2/96b_aerocore2.yaml similarity index 94% rename from boards/arm/96b_aerocore2/96b_aerocore2.yaml rename to boards/96boards/aerocore2/96b_aerocore2.yaml index b066c364322..6e704190fdd 100644 --- a/boards/arm/96b_aerocore2/96b_aerocore2.yaml +++ b/boards/96boards/aerocore2/96b_aerocore2.yaml @@ -19,4 +19,4 @@ supported: - adc ram: 256 flash: 2048 -vendor: gumstix +vendor: 96boards diff --git a/boards/arm/96b_aerocore2/96b_aerocore2_defconfig b/boards/96boards/aerocore2/96b_aerocore2_defconfig similarity index 86% rename from boards/arm/96b_aerocore2/96b_aerocore2_defconfig rename to boards/96boards/aerocore2/96b_aerocore2_defconfig index 8cd955fe1cb..490ce68a742 100644 --- a/boards/arm/96b_aerocore2/96b_aerocore2_defconfig +++ b/boards/96boards/aerocore2/96b_aerocore2_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2020 Linaro Limited # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F427XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/aerocore2/Kconfig.96b_aerocore2 b/boards/96boards/aerocore2/Kconfig.96b_aerocore2 new file mode 100644 index 00000000000..dae093b174b --- /dev/null +++ b/boards/96boards/aerocore2/Kconfig.96b_aerocore2 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_AEROCORE2 + select SOC_STM32F427XX diff --git a/boards/arm/96b_aerocore2/board.cmake b/boards/96boards/aerocore2/board.cmake similarity index 100% rename from boards/arm/96b_aerocore2/board.cmake rename to boards/96boards/aerocore2/board.cmake diff --git a/boards/96boards/aerocore2/board.yml b/boards/96boards/aerocore2/board.yml new file mode 100644 index 00000000000..42c4b7cae96 --- /dev/null +++ b/boards/96boards/aerocore2/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_aerocore2 + vendor: 96boards + socs: + - name: stm32f427xx diff --git a/boards/arm/96b_aerocore2/doc/img/96b_aerocore2.jpg b/boards/96boards/aerocore2/doc/img/96b_aerocore2.jpg similarity index 100% rename from boards/arm/96b_aerocore2/doc/img/96b_aerocore2.jpg rename to boards/96boards/aerocore2/doc/img/96b_aerocore2.jpg diff --git a/boards/96boards/aerocore2/doc/index.rst b/boards/96boards/aerocore2/doc/index.rst new file mode 100644 index 00000000000..ca12b694950 --- /dev/null +++ b/boards/96boards/aerocore2/doc/index.rst @@ -0,0 +1,349 @@ +.. _96b_aerocore2_board: + +96Boards Aerocore2 +################## + +Overview +******** + +The 96Boards Aerocore2 Mezzanine is based on the STMicroelectronics +STM32F427VIT6 Cortex-M4 CPU primarily designed for use in drones. +This board acts as a mezzanine platform for all 96Boards CE compliant +boards. It can also be used as a standalone board. + + +.. figure:: img/96b_aerocore2.jpg + :align: center + :alt: 96Boards Aerocore2 + + 96Boards Aerocore2 + +Hardware +******** + +96Boards Aerocore2 provides the following hardware components: + +- STM32F427VIT6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 168 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 2048 KB Flash +- 256 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 16 channels +- RTC +- Advanced-control Timers (2) +- General Purpose Timers (10) +- Watchdog Timers (2) +- USART/UART (4) +- I2C (3) +- SPI (3) +- SDIO +- USB 2.0 OTG FS +- DMA Controller + +More information about STM32F427VIT6 can be found here: + - `STM32F427 on www.st.com`_ + +Supported Features +================== + +The Zephyr 96b_aerocore2 board configuration supports the following hardware +features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| PWM | on-chip | timers / pwm | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ + +More details about the board can be found at `96Boards website`_. + +The default configuration can be found in +:zephyr_file:`boards/96boards/aerocore2/96b_aerocore2_defconfig` + +Connections and IOs +=================== + +LED +--- + +- LED1 / User1 LED = PE10 +- LED2 / User2 LED = PE9 + +External Connectors +------------------- + +Octal PWM Header (J1) + ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | Pin # | Signal Name | ++=======+=============+=========================+=======+=============+=======+=============+ +| 1 | PWM4_CH1 | PD12 | 2 | 5.0v | 3 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 4 | PWM4_CH2 | PD13 | 5 | 5.0v | 6 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 7 | PWM4_CH3 | PD14 | 8 | 5.0v | 9 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 10 | PWM4_CH4 | PD15 | 11 | 5.0v | 12 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 13 | PWM5_CH1 | PA0 | 14 | 5.0v | 15 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 16 | PWM5_CH2 | PA1 | 17 | 5.0v | 18 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 19 | PWM5_CH3 | PA2 | 20 | 5.0v | 21 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 22 | PWM5_CH4 | PA3 | 23 | 5.0v | 24 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ + + +IO Header J11 + ++-------+-------------+-------+-------------+ +| PIN # | Signal Name | PIN # | Signal Name | ++=======+=============+=======+=============+ +| 1 | PB9 | 2 | PB8* | ++-------+-------------+-------+-------------+ +| 3 | PC9 | 4 | PB0 | ++-------+-------------+-------+-------------+ +| 5 | PE5 | 6 | NA | ++-------+-------------+-------+-------------+ +| 7 | PE6 | 8 | NA | ++-------+-------------+-------+-------------+ +| 9 | PC6 | 10 | NA | ++-------+-------------+-------+-------------+ +| 11 | PC7 | 12 | NA | ++-------+-------------+-------+-------------+ +| 13 | PC8 | 14 | NA | ++-------+-------------+-------+-------------+ +| 15 | PA8 | 16 | GND | ++-------+-------------+-------+-------------+ +| 17 | PA9 | 18 | 3v3 | ++-------+-------------+-------+-------------+ +| 19 | PA10 | 20 | GND | ++-------+-------------+-------+-------------+ + +* PB8 is connected to a watchdog buzzer, It needs to be pulsed every 10 seconds to keep the buzzer silent. + +IO Header J5 + ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | STM32F427 Functions Pin | ++=======+=============+=========================+=======+=============+=========================+ +| 1 | AGND | AGND | 2 | ADC1_13 | PC3 | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 3 | ADC1_12 | PC2 | 4 | ADC1_11 | PC1 | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 5 | I2C_SDA | PB11 | 6 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 7 | I2C_SCL | PB10 | 8 | VCC 3v3 | VCC 3v3 | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 9 | NC | NC | 10 | NC | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 11 | NC | NC | 12 | NC | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 13 | UART_TX 7 | PE8 | 14 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 15 | UART_RX 7 | PE7 | 16 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 17 | UART_TX 2 | PD5 | 18 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 19 | UART_TX 2 | PD6 | 20 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 21 | NC | NC | 10 | NC | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 23 | NC | NC | 10 | NC | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 25 | SPI1_NIRQ | PC5 | 26 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 27 | SPI1_CLK | PA5 | 28 | SPI1_MISO | PA6 | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 29 | SPI1_CS0 | PA4 | 30 | SPI1_MOSI | PA7 | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 31 | CAN_TX | PD1 | 32 | CANH | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 33 | CAN_RX | PD0 | 34 | CANL | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ + + +GPS connector J15 + ++-------+-------------+-------------------------+ +| PIN # | Signal Name | STM32F427 Functions Pin | ++=======+=============+=========================+ +| 1 | V_OUT 5v | NC | ++-------+-------------+-------------------------+ +| 2 | UART1_TX | PB6 | ++-------+-------------+-------------------------+ +| 3 | UART1_RX | PB7 | ++-------+-------------+-------------------------+ +| 4 | VCC 3v3 | NC | ++-------+-------------+-------------------------+ +| 5 | GND | GND | ++-------+-------------+-------------------------+ + + +Spektrum connector J3 + ++-------+-------------+-------------------------+ +| PIN # | Signal Name | STM32F427 Functions Pin | ++=======+=============+=========================+ +| 1 | VCC 3v3 | NC | ++-------+-------------+-------------------------+ +| 2 | GND | GND | ++-------+-------------+-------------------------+ +| 3 | UART8_RX | PE0 | ++-------+-------------+-------------------------+ + + +External Clock Sources +---------------------- + +STM32F4 has one external oscillator. The frequency of the clock is +32.768 kHz. The internal 16MHz clock is used as the main clock. + +Serial Port +----------- + +96Boards Aerocore2 board has up to 4 U(S)ARTs. The Zephyr console output is +assigned to USART7. Default settings are 115200 8N1. + +I2C +--- + +96Boards Aerocore2 board has 1 I2C port. The default I2C mapping for Zephyr is: + +- I2C1_SCL : PB10 +- I2C1_SDA : PB11 + +SPI +--- + +96Boards Aerocore2 board has 1 SPI port. The default SPI mapping for Zephyr is: + +- SPI1_CS0 : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 + +USB +=== + +96Boards Aerocore2 board has a USB OTG dual-role device (DRD) controller that +supports both device and host functions through its mini "OTG" USB connector. +Only USB device functions are supported in Zephyr at the moment. + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. The ROM bootloader +supports flashing via USB (DFU), UART, I2C and SPI. You can read more about +how to enable and use the ROM bootloader by checking the application +note `AN2606`_, page 109. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +Flashing an Application to 96Boards Aerocore2 +--------------------------------------------- + +Connect the micro-USB cable to the USB OTG/STM_CONSOLE Aerocore2 port and to your computer. +The board should power ON. Force the board into DFU mode by keeping the BOOT0 +switch pressed while pressing and releasing the RST switch. + +The BOOT button is located at the back-side of the PCB. + +Confirm that the board is in DFU mode: + +.. code-block:: console + + $ sudo dfu-util -l + dfu-util 0.8 + Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. + Copyright 2010-2014 Tormod Volden and Stefan Schmidt + This program is Free Software and has ABSOLUTELY NO WARRANTY + Please report bugs to dfu-util@lists.gnumonks.org + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", serial="3574364C3034" + Found Runtime: [05ac:8290] ver=0104, devnum=2, cfg=1, intf=5, alt=0, name="UNKNOWN", serial="UNKNOWN" + +You should see following confirmation on your Linux host: + +.. code-block:: console + + $ dmesg + usb 1-2.1: new full-speed USB device number 14 using xhci_hcd + usb 1-2.1: New USB device found, idVendor=0483, idProduct=df11 + usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 + usb 1-2.1: Product: STM32 BOOTLOADER + usb 1-2.1: Manufacturer: STMicroelectronics + usb 1-2.1: SerialNumber: 3574364C3034 + +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_aerocore2 + :goals: build flash + +Connect a USB-TTL dongle to the UART_7 header port and to your computer. +Run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board 96Boards Aerocore2 +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. +The ``-b`` option sets baud rate ignoring the value from config. + +Press the Reset button and you should see the following message in your +terminal: + +.. code-block:: console + + Hello World! arm + +.. _96Boards website: + https://www.96boards.org/product/aerocore2/ + +.. _STM32F427 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32f427vi.html + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _AN2606: + https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf diff --git a/boards/arm/96b_argonkey/96b_argonkey.dts b/boards/96boards/argonkey/96b_argonkey.dts similarity index 100% rename from boards/arm/96b_argonkey/96b_argonkey.dts rename to boards/96boards/argonkey/96b_argonkey.dts diff --git a/boards/arm/96b_argonkey/96b_argonkey.yaml b/boards/96boards/argonkey/96b_argonkey.yaml similarity index 100% rename from boards/arm/96b_argonkey/96b_argonkey.yaml rename to boards/96boards/argonkey/96b_argonkey.yaml diff --git a/boards/arm/96b_argonkey/96b_argonkey_defconfig b/boards/96boards/argonkey/96b_argonkey_defconfig similarity index 85% rename from boards/arm/96b_argonkey/96b_argonkey_defconfig rename to boards/96boards/argonkey/96b_argonkey_defconfig index 76869d63345..82ee7285d52 100644 --- a/boards/arm/96b_argonkey/96b_argonkey_defconfig +++ b/boards/96boards/argonkey/96b_argonkey_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F412CX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/argonkey/Kconfig.96b_argonkey b/boards/96boards/argonkey/Kconfig.96b_argonkey new file mode 100644 index 00000000000..6795385fa40 --- /dev/null +++ b/boards/96boards/argonkey/Kconfig.96b_argonkey @@ -0,0 +1,5 @@ +# Copyright (c) 2018 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_ARGONKEY + select SOC_STM32F412CX diff --git a/boards/96boards/argonkey/Kconfig.defconfig b/boards/96boards/argonkey/Kconfig.defconfig new file mode 100644 index 00000000000..fd35e508696 --- /dev/null +++ b/boards/96boards/argonkey/Kconfig.defconfig @@ -0,0 +1,23 @@ +# 96Boards Argonkey Board Configuration + +# Copyright (c) 2018 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_ARGONKEY + +if LSM6DSL + +choice LSM6DSL_TRIGGER_MODE + default LSM6DSL_TRIGGER_GLOBAL_THREAD +endchoice + +config LSM6DSL_SENSORHUB + default y + +choice LSM6DSL_EXTERNAL_SENSOR_0 + default LSM6DSL_EXT0_LIS2MDL +endchoice + +endif # LSM6DSL + +endif # BOARD_96B_ARGONKEY diff --git a/boards/96boards/argonkey/board.yml b/boards/96boards/argonkey/board.yml new file mode 100644 index 00000000000..9e78ee2394a --- /dev/null +++ b/boards/96boards/argonkey/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_argonkey + vendor: 96boards + socs: + - name: stm32f412cx diff --git a/boards/arm/96b_argonkey/doc/img/96b_argonkey.jpg b/boards/96boards/argonkey/doc/img/96b_argonkey.jpg similarity index 100% rename from boards/arm/96b_argonkey/doc/img/96b_argonkey.jpg rename to boards/96boards/argonkey/doc/img/96b_argonkey.jpg diff --git a/boards/96boards/argonkey/doc/index.rst b/boards/96boards/argonkey/doc/index.rst new file mode 100644 index 00000000000..810ab2e5781 --- /dev/null +++ b/boards/96boards/argonkey/doc/index.rst @@ -0,0 +1,239 @@ +.. _96b_argonkey: + +96Boards Argonkey +################# + +Overview +******** + +96Boards Argonkey board is based on the ST Microelectronics STM32F412CG +Cortex M4 CPU. + +This board acts as a sensor hub platform for all 96Boards compliant +family products. It can also be used as a standalone board. + +.. figure:: img/96b_argonkey.jpg + :align: center + :alt: 96Boards Argonkey + + 96Boards Argonkey + +Hardware +******** + +96Boards Argonkey provides the following hardware components: + +- STM32F412CG in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 100 MHz max CPU frequency +- 1.8V work voltage +- 1024 KB Flash +- 256 KB SRAM +- On board sensors: + + - Humidity: STMicro HTS221 + - Temperature/Pressure: STMicro LPS22HB + - ALS: Intersil ISL29034 + - Proximity: STMicro VL53L0X + - Accelerometer/Gyroscope: STMicro LSM6DSL + - Geomagnetic: STMicro LIS2MDL + - AMR Hall sensor: MRMS501A + - Microphone: STMicro MP34DT05 + +- 2 User LEDs +- 16 General purpose LEDs +- GPIO with external interrupt capability +- UART +- I2C (3) +- SPI (1) +- I2S (1) + +Supported Features +================== + +The Zephyr 96b_argonkey board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +More information about the board can be found at the +`ARGONKEY website`_. + +The default board configuration can be found in +:zephyr_file:`boards/96boards/argonkey/96b_argonkey_defconfig` + +Connections and IOs +=================== + +LED +--- + +- LED1 / User1 LED = PB2 +- LED2 / User2 LED = PC13 + +Push buttons +------------ + +- BUTTON = RST (BT1) +- BUTTON = USR (BT2) + +System Clock +============ + +96Boards Argonkey can be driven by an internal oscillator as well as the main +PLL clock. In default board configuration, the 16MHz external oscillator is +used to drive the main PLL clock to generate a System Clock (SYSCLK) at 84MHz. +On the bus side, AHB clock runs at 84MHz, while APB1/APB2 clock runs at 42MHz. + +Serial Port +=========== + +On 96Boards Argonkey, Zephyr console output is assigned to USART1. +Default settings are 115200 8N1. + +I2C +--- + +96Boards Argonkey board has up to 3 I2Cs. The default I2C mapping is: + +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PB9 +- I2C3_SCL : PA8 +- I2C3_SCL : PB4 + +I2C3 goes to the P2 connector and can be used to attach external sensors. +It goes to 100Kbit maximum. + +SPI +--- +96Boards Argonkey board has 2 SPIs. SPI1 is used in slave mode as the communication +bus with the AP. SPI2 is used in master mode to control the LSM6DSL sensor. +The default SPI mapping is: + +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 + +Programming and Debugging +************************* + +Building +======== + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_argonkey + :goals: build + +Flashing +======== + +96Boards Argonkey can be flashed by two methods, one using the ROM +bootloader and another using the SWD debug port (which requires additional +hardware). + +Flashing using the ROM bootloader requires a special activation pattern, +which can be triggered by using the BOOT0 pin. The ROM bootloader supports +flashing via USB (DFU), UART, I2C and SPI, but this document describes the +UART case only. You can read more about how to enable and use the ROM +bootloader by checking the application note `AN2606`_ . + +Using ROM bootloader: +--------------------- + +Hereafter the documents describes basic steps to perform ArgonKey firmware +flashing on a Linux PC using UART as communication channel. + +1. Connect ArgonKey UART to your Linux PC using, for example, a USB-TTL serial + cable. The flashing procedure has been tested using a `TTL-232RG`_ cable with + FTDI chip. The UART pins on ArgonKey can be found on the P3 low speed + expansion connector on the back of the board. + + - GND (black) to ArgonKey GND (P3.1) + - TXD (orange) to ArgonKey UART0_TXD (P3.5) + - RXD (yellow) to ArgonKey UART0_RXD (P3.7) + + When the USB cable is inserted to the Linux PC the following device will be + created: /dev/ttyUSBx (x is usually '0'). + +2. Force STM32F412CG to enter in Bootloader mode + + - Connect BOOT0 to 1V8 (link P2.1 to P3.30) + - Press and release the RST button + +3. Use stm32flash utility to flash the ArgonKey: + +.. code-block:: console + + $ stm32flash -w zephyr.bin -v -g 0x08000000 /dev/ttyUSB0 + +See References section for more info on `stm32flash`_. + +Using SWD debugger: +------------------- + +Select a commercial JTAG/SWD h/w tool and connect it to ArgonKey P4 connector. + +The ArgonKey has been tested using the `ST-LINK/V2`_ tool. Once that the tool +is connected to the PC through USB, it presents itself as a USB composite +device with mass storage capability. The device can be then mounted in linux +and the f/w can be actually copied there and will be automatically flashed by +the ST-LINK onto the ArgonKey. + +Example: + +.. code-block:: console + + $ mount /dev/sdb /mnt + $ cp zephyr.bin /mnt + $ umount /mnt + +Debugging +========= + +References +********** + +.. target-notes:: + +.. _ARGONKEY website: + https://www.st.com/en/evaluation-tools/steval-mki187v1.html + +.. _AN2606: + https://www.st.com/resource/en/application_note/cd00167594.pdf + +.. _stm32flash: + https://sourceforge.net/p/stm32flash/wiki/Home/ + +.. _ST-LINK/V2: + https://www.st.com/en/development-tools/st-link-v2.html + +.. _TTL-232RG: + http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232RG_CABLES.pdf diff --git a/boards/arm/96b_avenger96/96b_avenger96.dts b/boards/96boards/avenger96/96b_avenger96.dts similarity index 100% rename from boards/arm/96b_avenger96/96b_avenger96.dts rename to boards/96boards/avenger96/96b_avenger96.dts diff --git a/boards/arm/96b_avenger96/96b_avenger96.yaml b/boards/96boards/avenger96/96b_avenger96.yaml similarity index 94% rename from boards/arm/96b_avenger96/96b_avenger96.yaml rename to boards/96boards/avenger96/96b_avenger96.yaml index e1e21e4d4c7..5d50bcd6943 100644 --- a/boards/arm/96b_avenger96/96b_avenger96.yaml +++ b/boards/96boards/avenger96/96b_avenger96.yaml @@ -22,4 +22,4 @@ testing: - nfc ram: 256 flash: 64 -vendor: arrow +vendor: 96boards diff --git a/boards/arm/96b_avenger96/96b_avenger96_defconfig b/boards/96boards/avenger96/96b_avenger96_defconfig similarity index 89% rename from boards/arm/96b_avenger96/96b_avenger96_defconfig rename to boards/96boards/avenger96/96b_avenger96_defconfig index 05be01fbb36..11db7ac995f 100644 --- a/boards/arm/96b_avenger96/96b_avenger96_defconfig +++ b/boards/96boards/avenger96/96b_avenger96_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32MP1X=y -CONFIG_SOC_STM32MP15_M4=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/avenger96/Kconfig.96b_avenger96 b/boards/96boards/avenger96/Kconfig.96b_avenger96 new file mode 100644 index 00000000000..9c891b2cf4f --- /dev/null +++ b/boards/96boards/avenger96/Kconfig.96b_avenger96 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_AVENGER96 + select SOC_STM32MP15_M4 diff --git a/boards/arm/96b_avenger96/board.cmake b/boards/96boards/avenger96/board.cmake similarity index 100% rename from boards/arm/96b_avenger96/board.cmake rename to boards/96boards/avenger96/board.cmake diff --git a/boards/96boards/avenger96/board.yml b/boards/96boards/avenger96/board.yml new file mode 100644 index 00000000000..042bb6a472f --- /dev/null +++ b/boards/96boards/avenger96/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_avenger96 + vendor: 96boards + socs: + - name: stm32mp157cxx diff --git a/boards/arm/96b_avenger96/doc/img/96b_avenger96.jpg b/boards/96boards/avenger96/doc/img/96b_avenger96.jpg similarity index 100% rename from boards/arm/96b_avenger96/doc/img/96b_avenger96.jpg rename to boards/96boards/avenger96/doc/img/96b_avenger96.jpg diff --git a/boards/96boards/avenger96/doc/index.rst b/boards/96boards/avenger96/doc/index.rst new file mode 100644 index 00000000000..b451a51ea02 --- /dev/null +++ b/boards/96boards/avenger96/doc/index.rst @@ -0,0 +1,279 @@ +.. _96b_avenger96: + +96Boards Avenger96 +################## + +Overview +******** + +96Boards Avenger96 board is based on ST Microelectronics STM32MP157A +multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4 +core. Zephyr OS is ported to run on the Cortex®-M4 core. + +- Board features: + + - PMIC: STPMIC1A + - RAM: 1024 Mbyte @ 533MHz + - Storage: + + - eMMC: v4.51: 8 Gbyte + - QSPI: 2Mbyte + - EEPROM: 128 byte + - microSD Socket: UHS-1 v3.01 + - Ethernet: 10/100/1000 Mbit/s, IEEE 802.3 Compliant + - Wireless: + + - WiFi: 5 GHz & 2.4GHz IEEE 802.11a/b/g/n/ac + - Bluetooth: v4.2 (BR/EDR/BLE) + - USB: + + - Host - 2x type A, 2.0 high-speed + - OTG: - 1x type micro-AB, 2.0 high-speed + - HDMI: WXGA (1366x768)@ 60 fps, HDMI 1.4 + - Connectors: + + - 40-Pin Low Speed Header + - 60-Pin High Speed Header + - LEDs: + + - 4x Green user LEDs + - 1x Blue Bluetooth LED + - 1x Yellow WiFi LED + - 1x Red power supply LED + +.. image:: img/96b_avenger96.jpg + :align: center + :alt: 96Boards Avenger96 + +More information about the board can be found at the +`96Boards website`_. + +Hardware +******** + +The STM32MP157A SoC provides the following hardware capabilities: + +- Core: + + - 32-bit dual-core Arm® Cortex®-A7 + + - L1 32-Kbyte I / 32-Kbyte D for each core + - 256-Kbyte unified level 2 cache + - Arm® NEON™ + + - 32-bit Arm® Cortex®-M4 with FPU/MPU + + - Up to 209 MHz (Up to 703 CoreMark®) + +- Memories: + + - External DDR memory up to 1 Gbyte. + - 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM + + 64 KB of AHB SRAM in backup domain. + - Dual mode Quad-SPI memory interface + - Flexible external memory controller with up to 16-bit data bus + +- Clock management: + + - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz + LSI oscillator + - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator + - 6 × PLLs with fractional mode + +- General-purpose input/outputs: + + - Up to 176 I/O ports with interrupt capability + +- Interconnect matrix + +- 3 DMA controllers + +- Communication peripherals: + + - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus) + - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) + - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy) + - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx) + - SPDIF Rx with 4 inputs + - HDMI-CEC interface + - MDIO Slave interface + - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO) + - 2 × CAN controllers supporting CAN FD protocol, TTCAN capability + - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously + - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI) + - 8- to 14-bit camera interface up to 140 Mbyte/s + - 6 analog peripherals + - 2 × ADCs with 16-bit max. resolution. + - 1 × temperature sensor + - 2 × 12-bit D/A converters (1 MHz) + - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6 + filters + - Internal or external ADC/DAC reference VREF+ + +- Graphics: + + - 3D GPU: Vivante® - OpenGL® ES 2.0 + - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps + - MIPI® DSI 2 data lanes up to 1 GHz each + +- Timers: + + - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature + (incremental) encoder input + - 2 × 16-bit advanced motor control timers + - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM) + - 5 × 16-bit low-power timers + - RTC with sub-second accuracy and hardware calendar + - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor) + - 1 × SysTick Cortex®-M4 timer + +- Hardware acceleration: + + - HASH (MD5, SHA-1, SHA224, SHA256), HMAC + - 2 × true random number generator (3 oscillators each) + - 2 × CRC calculation unit + +- Debug mode: + + - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces + - 8-Kbyte embedded trace buffer + - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user + +More information about STM32P157A can be found here: + +- `STM32MP157A on www.st.com`_ +- `STM32MP157A reference manual`_ + +Supported Features +================== + +The Zephyr 96b_avenger96 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/96boards/avenger96/96b_avenger96_defconfig` + + +Connections and IOs +=================== + +96Boards Avenger96 Board schematic is available here: +`Avenger96 board schematics`_. + + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_7 TX/RX/RTS/CTS : PE8/PE7/PE9/PE10 (UART console) +- UART_4 TX/RX : PD1/PB2 + +System Clock +------------ + +The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value +must match the configured mlhclk_ck frequency. + +Serial Port +----------- + +96Boards Avenger96 board has 3 U(S)ARTs. The Zephyr console output is assigned +by default to the RAM console to be dumped by the Linux Remoteproc Framework +on Cortex®-A7 core. Alternatively, Zephyr console output can be assigned to +UART7 which is disabled by default. UART console can be enabled through +board's devicetree and 96b_avenger96_defconfig board file (or prj.conf +project files), and will disable existing RAM console output. Default UART +console settings are 115200 8N1. + +Programming and Debugging +************************* + +The STM32MP157A doesn't have QSPI flash for the Cortex®-M4 and it needs to be +started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the +Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset. +The Cortex®-A7 can perform these steps at bootloader level or after the Linux +system has booted. + +The Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at +address 0x00000000 (RETRAM), the vector table should be loaded at this address +These are the memory mappings for Cortex®-A7 and Cortex®-M4: + ++------------+-----------------------+------------------------+----------------+ +| Region | Cortex®-A7 | Cortex®-M4 | Size | ++============+=======================+========================+================+ +| RETRAM | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF | 64KB | ++------------+-----------------------+------------------------+----------------+ +| MCUSRAM | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF | 384KB | ++------------+-----------------------+------------------------+----------------+ +| DDR | 0xC0000000-0xFFFFFFFF | | up to 1 GB | ++------------+-----------------------+------------------------+----------------+ + + +Refer to `stm32mp157 boot Cortex-M4 firmware`_ wiki page for instruction +to load and start the Cortex-M4 firmware. + +Debugging +========= + +You can debug an application using OpenOCD and GDB. The Solution proposed below +is based on the Linux STM32MP1 SDK OpenOCD and is available only for a Linux +environment. The firmware must first be loaded by the Cortex®-A7. Developer +then attaches the debugger to the running Zephyr using OpenOCD. + +Prerequisite +------------ +install `stm32mp1 developer package`_. + +1) start OpenOCD in a dedicated terminal + + - Start up the sdk environment:: + + source /environment-setup-cortexa7hf-neon-vfpv4-openstlinux_weston-linux-gnueabi + + - Start OpenOCD:: + + ${OECORE_NATIVE_SYSROOT}/usr/bin/openocd -s ${OECORE_NATIVE_SYSROOT}/usr/share/openocd/scripts -f board/stm32mp15x_ev1_jlink_jtag.cfg + +2) run gdb in Zephyr environment + + .. code-block:: console + + # On Linux + cd $ZEPHYR_BASE/samples/hello_world + mkdir -p build && cd build + + # Use cmake to configure a Ninja-based build system: + cmake -GNinja -DBOARD=96b_avenger96 .. + + # Now run ninja on the generated build system: + ninja debug + +.. _96Boards website: + https://www.96boards.org/product/avenger96/ + +.. _STM32MP157A on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp157/stm32mp157a.html + +.. _STM32MP157A reference manual: + https://www.st.com/resource/en/reference_manual/DM00327659.pdf + +.. _Avenger96 board schematics: + https://www.96boards.org/documentation/consumer/avenger96/hardware-docs/files/avenger96-schematics.pdf + +.. _stm32mp1 developer package: + https://wiki.st.com/stm32mpu/index.php/STM32MP1_Developer_Package#Installing_the_SDK + +.. _stm32mp157 boot Cortex-M4 firmware: + https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework diff --git a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51-pinctrl.dtsi b/boards/96boards/carbon/96b_carbon_nrf51822-pinctrl.dtsi similarity index 100% rename from boards/arm/96b_carbon_nrf51/96b_carbon_nrf51-pinctrl.dtsi rename to boards/96boards/carbon/96b_carbon_nrf51822-pinctrl.dtsi diff --git a/boards/96boards/carbon/96b_carbon_nrf51822.dts b/boards/96boards/carbon/96b_carbon_nrf51822.dts new file mode 100644 index 00000000000..98ccd264fdf --- /dev/null +++ b/boards/96boards/carbon/96b_carbon_nrf51822.dts @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "96b_carbon_nrf51822-pinctrl.dtsi" + +/ { + model = "Seeed Studio Carbon nRF51 96board"; + compatible = "seeed,carbon_nrf51"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + aliases { + watchdog0 = &wdt0; + }; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi1 { + compatible = "nordic,nrf-spis"; + status = "okay"; + def-char = <0x00>; + + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + bt-hci@0 { + compatible = "zephyr,bt-hci-spi-slave"; + reg = <0>; + irq-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + }; +}; diff --git a/boards/96boards/carbon/96b_carbon_nrf51822.yaml b/boards/96boards/carbon/96b_carbon_nrf51822.yaml new file mode 100644 index 00000000000..135d5aa461b --- /dev/null +++ b/boards/96boards/carbon/96b_carbon_nrf51822.yaml @@ -0,0 +1,13 @@ +identifier: 96b_carbon/nrf51822 +name: 96Boards Carbon (nRF51) +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - ble +vendor: seeed diff --git a/boards/96boards/carbon/96b_carbon_nrf51822_defconfig b/boards/96boards/carbon/96b_carbon_nrf51822_defconfig new file mode 100644 index 00000000000..0a45ef65e11 --- /dev/null +++ b/boards/96boards/carbon/96b_carbon_nrf51822_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/96b_carbon/96b_carbon.dts b/boards/96boards/carbon/96b_carbon_stm32f401xe.dts similarity index 100% rename from boards/arm/96b_carbon/96b_carbon.dts rename to boards/96boards/carbon/96b_carbon_stm32f401xe.dts diff --git a/boards/96boards/carbon/96b_carbon_stm32f401xe.yaml b/boards/96boards/carbon/96b_carbon_stm32f401xe.yaml new file mode 100644 index 00000000000..4b0c56dc5a4 --- /dev/null +++ b/boards/96boards/carbon/96b_carbon_stm32f401xe.yaml @@ -0,0 +1,18 @@ +identifier: 96b_carbon/stm32f401xe +name: 96Boards Carbon +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - ble + - i2c + - counter + - spi + - usb_device +ram: 96 +flash: 512 +vendor: 96boards diff --git a/boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig b/boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig new file mode 100644 index 00000000000..c729b83e3d0 --- /dev/null +++ b/boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/96b_carbon/96b_lscon.dtsi b/boards/96boards/carbon/96b_lscon.dtsi similarity index 100% rename from boards/arm/96b_carbon/96b_lscon.dtsi rename to boards/96boards/carbon/96b_lscon.dtsi diff --git a/boards/96boards/carbon/Kconfig.96b_carbon b/boards/96boards/carbon/Kconfig.96b_carbon new file mode 100644 index 00000000000..6db6af8cf3d --- /dev/null +++ b/boards/96boards/carbon/Kconfig.96b_carbon @@ -0,0 +1,6 @@ +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_CARBON + select SOC_STM32F401XE if BOARD_96B_CARBON_STM32F401XE + select SOC_NRF51822_QFAC if BOARD_96B_CARBON_NRF51822 diff --git a/boards/96boards/carbon/Kconfig.defconfig b/boards/96boards/carbon/Kconfig.defconfig new file mode 100644 index 00000000000..fe90a4fdd4c --- /dev/null +++ b/boards/96boards/carbon/Kconfig.defconfig @@ -0,0 +1,61 @@ +# 96boards Carbon board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_CARBON_STM32F401XE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +endif # BT + +if NETWORKING + +# Re-create the NET_L2_BT dependencies here +config BT + default y + +config BT_PERIPHERAL + default BT + +config BT_CENTRAL + default BT + +config BT_SMP + default BT + +config BT_L2CAP_DYNAMIC_CHANNEL + default BT + +# BT is the only onboard network iface, so use it for IP networking +# if it's enabled + +config NET_L2_BT + depends on NET_IPV6 + default BT + +config NET_L2_BT_ZEP1656 + depends on NET_IPV6 + default BT + +endif # NETWORKING + +endif # BOARD_96B_CARBON_STM32F401XE + +if BOARD_96B_CARBON_NRF51822 + +config BT_CTLR + default BT + +endif # BOARD_96B_CARBON_NRF51822 diff --git a/boards/96boards/carbon/board.cmake b/boards/96boards/carbon/board.cmake new file mode 100644 index 00000000000..19e4554022e --- /dev/null +++ b/boards/96boards/carbon/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_96B_CARBON_STM32F401XE) + board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") + + include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +endif() diff --git a/boards/96boards/carbon/board.yml b/boards/96boards/carbon/board.yml new file mode 100644 index 00000000000..79101f957be --- /dev/null +++ b/boards/96boards/carbon/board.yml @@ -0,0 +1,6 @@ +board: + name: 96b_carbon + vendor: 96boards + socs: + - name: stm32f401xe + - name: nrf51822 diff --git a/boards/arm/96b_carbon/doc/img/96b_carbon.jpg b/boards/96boards/carbon/doc/img/96b_carbon.jpg similarity index 100% rename from boards/arm/96b_carbon/doc/img/96b_carbon.jpg rename to boards/96boards/carbon/doc/img/96b_carbon.jpg diff --git a/boards/arm/96b_carbon_nrf51/doc/img/96b_carbon_nrf51.jpg b/boards/96boards/carbon/doc/img/96b_carbon_nrf51.jpg similarity index 100% rename from boards/arm/96b_carbon_nrf51/doc/img/96b_carbon_nrf51.jpg rename to boards/96boards/carbon/doc/img/96b_carbon_nrf51.jpg diff --git a/boards/96boards/carbon/doc/nrf51822.rst b/boards/96boards/carbon/doc/nrf51822.rst new file mode 100644 index 00000000000..072c0e2157f --- /dev/null +++ b/boards/96boards/carbon/doc/nrf51822.rst @@ -0,0 +1,170 @@ +.. _96b_carbon_nrf51_board: + +96Boards Carbon nRF51 +##################### + +Overview +******** + +This is the secondary nRF51822 chip on the 96Boards Carbon and provides +Bluetooth functionality to the main STM32F401RET chip via SPI. + +.. note:: + + If you're looking to reprogram the main STMicro part, see + :ref:`96b_carbon_board`. Users should not use this configuration + unless they want to reprogram the secondary chip which provides + Bluetooth connectivity. + + +Hardware +******** + +The 96Boards Carbon nRF51 has two external oscillators. The frequency +of the slow clock is 32.768 kHz. The frequency of the main clock is 16 +MHz. + +See :ref:`96b_carbon_board` for other general information about the +board; that configuration is for the same physical board, just a +different chip. + +Supported Features +================== + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| SPIS | on-chip | SPI slave | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/96boards/carbon/96b_carbon_nrf51822_defconfig` + +Connections and IOs +=================== + +SPI +--- + +96Boards Carbon nRF51 has one SPI, which for providing Bluetooth +communication. The default SPI mapping for Zephyr is: + +- SPI1_NSS : P0.25 +- SPI1_SCK : P0.07 +- SPI1_MISO : P0.30 +- SPI1_MOSI : P0.00 + +The SWD debug pins are broken out to an external header; all other +connected pins are to the main STM32F401RET chip. + +.. _96b_carbon_nrf51_programming: + +Programming and Debugging +************************* + +Flashing +======== + +The 96Boards Carbon nRF51 can be flashed using an external SWD +debugger, via the debug header labeled "BLE" on the board's +silkscreen. The header is not populated; 0.1" male header must be +soldered on first. + +.. figure:: img/96b_carbon_nrf51.jpg + :align: center + :alt: 96Boards Carbon nRF51 Debug + + 96Boards Carbon nRF51 Debug + +The following example assumes a Zephyr binary ``zephyr.elf`` will be +flashed to the board. + +It uses the `Black Magic Debug Probe`_ as an SWD programmer, which can +be connected to the BLE debug header using flying leads and its 20 Pin +JTAG Adapter Board Kit. When plugged into your host PC, the Black +Magic Debug Probe enumerates as a USB serial device as documented on +its `Getting started page`_. + +It also uses the GDB binary provided with the Zephyr SDK, +``arm-zephyr-eabi-gdb``. Other GDB binaries, such as the GDB from GCC +ARM Embedded, can be used as well. + +.. code-block:: console + + $ arm-zephyr-eabi-gdb -q zephyr.elf + (gdb) target extended-remote /dev/ttyACM0 + Remote debugging using /dev/ttyACM0 + (gdb) monitor swdp_scan + Target voltage: 3.3V + Available Targets: + No. Att Driver + 1 nRF51 + (gdb) attach 1 + Attaching to Remote target + 0xabcdef12 in ?? () + (gdb) load + +Debugging +========= + +After you've flashed the chip, you can keep debugging using the same +GDB instance. To reattach, just follow the same steps above, but don't +run "load". You can then debug as usual with GDB. In particular, type +"run" at the GDB prompt to restart the program you've flashed. + +As an aid to debugging, this board configuration directs a console +output to a currently unused pin connected to the STM32F401RET. Users +who are experienced in electronics rework can remove a resistor (R22) +on the board and attach a wire to the nRF51822's UART output. + +.. _96b_carbon_nrf51_bluetooth: + +Providing Bluetooth to 96b_carbon +********************************* + +This ``96b_carbon/nrf51822`` Zephyr board configuration can be used to provide +Bluetooth functionality from the secondary nRF51822 chip to the +primary STM32F401RE chip on the :ref:`96b_carbon_board`. + +To do this, build the ``samples/bluetooth/hci_spi/`` application +provided with Zephyr with ``BOARD=96b_carbon/nrf51822``, then flash it to +the nRF51822 chip using the instructions :ref:`above +<96b_carbon_nrf51_programming>`. (For instructions on how to build a +Zephyr application, see :ref:`build_an_application`.) + +.. warning:: + + Be sure to flash the hci_spi application to the nRF51822 chip and + not to the main STM32F401RET chip. While both chips are supported + by Zephyr, the hci_spi application providing Bluetooth support will + only run on the nRF51822 chip. + +References +********** + +- `Board documentation from 96Boards`_ +- `nRF51822 information from Nordic Semiconductor`_ + +.. _Black Magic Debug Probe: + https://github.com/blacksphere/blackmagic/wiki + +.. _Getting started page: + https://github.com/blacksphere/blackmagic/wiki/Getting-Started + +.. _Board documentation from 96Boards: + http://www.96boards.org/product/carbon/ + +.. _nRF51822 information from Nordic Semiconductor: + https://www.nordicsemi.com/eng/Products/Bluetooth-low-energy/nRF51822 diff --git a/boards/96boards/carbon/doc/stm32f401xe.rst b/boards/96boards/carbon/doc/stm32f401xe.rst new file mode 100644 index 00000000000..e025a12ff32 --- /dev/null +++ b/boards/96boards/carbon/doc/stm32f401xe.rst @@ -0,0 +1,383 @@ +.. _96b_carbon_board: + +96Boards Carbon +############### + +Overview +******** + +The 96Boards is based on the STMicroelectronics STM32F401RET Cortex-M4 CPU and +also contains a nRF51822 chip connected over SPI for BLE connectivity. + +The 96Boards Carbon board is built with two chips: an STMicroelectronics +STM32F401RET Cortex-M4 CPU and an nRF51822 chip connected to +the Cortex-M4 CPU over SPI for Bluetooth LE connectivity. Even though +both chips exist on the same physical board, they must be programmed +separately: + +- The ``96b_carbon/stm32f401xe`` configuration is used when developing programs for + the main chip on the board, the STM32F401RET. Users will likely want to + write applications targeting this chip, using the ``96b_carbon`` + configuration, since it is connected to all of the breakout + I/O headers. + +- The ``96b_carbon/nrf51822`` configuration should be used for programming + the secondary nRF51822 chip. Most users will likely not develop + applications for this chip, since Zephyr already provides a + sample application that can be flashed onto the nRF51822 + to provide Bluetooth functionality to applications on the main + STM32F401RET chip. + +For instructions on how to set up the nRF51822 to develop Bluetooth +applications, see :ref:`96b_carbon_nrf51_bluetooth`. + +After you have flashed your nRF51, you can perform basic validation +of this Bluetooth setup using the instructions +:ref:`below <96b_carbon_verify_bluetooth>`. + +.. figure:: img/96b_carbon.jpg + :align: center + :alt: 96Boards Carbon + + 96Boards Carbon + +Hardware +******** + +96Boards Carbon provides the following hardware components: + +- STM32F401RET6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 84 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 96 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 16 channels +- RTC +- Advanced-control Timer +- General Purpose Timers (7) +- Watchdog Timers (2) +- USART/UART (4) +- I2C (3) +- SPI (3) +- SDIO +- USB 2.0 OTG FS +- DMA Controller +- Bluetooth LE over SPI, provided by nRF51822 + +More information about STM32F401RE can be found here: + - `STM32F401RE on www.st.com`_ + - `STM32F401 reference manual`_ + +Supported Features +================== + +The Zephyr ``96b_carbon/stm32f401xe`` board configuration supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ + +More details about the board can be found at `96Boards website`_. + +The default configuration can be found in +:zephyr_file:`boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig` + +Connections and IOs +=================== + +LED +--- + +- LED1 / User1 LED = PD2 +- LED2 / User2 LED = PA15 +- LED3 / BT LED = PB5 +- LED4 / Power LED = VCC + +Push buttons +------------ + +- BUTTON = BOOT0 (SW1) +- BUTTON = RST + +External Connectors +------------------- + +Low Speed Header + ++--------+-------------+----------------------+ +| PIN # | Signal Name | STM32F401 Functions | ++========+=============+======================+ +| 1 | UART2_CTS | PA0 | ++--------+-------------+----------------------+ +| 3 | UART2_TX | PA2 | ++--------+-------------+----------------------+ +| 5 | UART2_RX | PA3 | ++--------+-------------+----------------------+ +| 7 | UART2_RTS | PA1 | ++--------+-------------+----------------------+ +| 9 | GND | GND | ++--------+-------------+----------------------+ +| 11 | USB5V | USB5V | ++--------+-------------+----------------------+ +| 13 | AIN12 | PC2 | ++--------+-------------+----------------------+ +| 15 | AIN14 | PC4 | ++--------+-------------+----------------------+ +| 17 | UART6_TX | PC6 | ++--------+-------------+----------------------+ +| 19 | GPIO | PC8 | ++--------+-------------+----------------------+ +| 21 | I2C1_SCL | PB6 | ++--------+-------------+----------------------+ +| 23 | I2C1_SCA | PB7 | ++--------+-------------+----------------------+ +| 25 | I2C2_SCA | PB3 | ++--------+-------------+----------------------+ +| 27 | I2C2_SCL | PB10 | ++--------+-------------+----------------------+ +| 29 | RST_BTN | RST_BTN | ++--------+-------------+----------------------+ + ++--------+-------------+----------------------+ +| PIN # | Signal Name | STM32F401 Functions | ++========+=============+======================+ +| 2 | SPI2_SS | PB12 | ++--------+-------------+----------------------+ +| 4 | SPI2_MOSI | PB15 | ++--------+-------------+----------------------+ +| 6 | SPI2_MISO | PB14 | ++--------+-------------+----------------------+ +| 8 | SPI2_SCK | PB13 | ++--------+-------------+----------------------+ +| 10 | GND | GND | ++--------+-------------+----------------------+ +| 12 | VCC2 | VCC2 | ++--------+-------------+----------------------+ +| 14 | AIN13 | PC3 | ++--------+-------------+----------------------+ +| 16 | AIN15 | PC5 | ++--------+-------------+----------------------+ +| 18 | UART6_RX | PC7 | ++--------+-------------+----------------------+ +| 20 | GPIO | PC9 | ++--------+-------------+----------------------+ +| 22 | I2C1_SCL | PB8 | ++--------+-------------+----------------------+ +| 24 | I2C1_SDA | PB9 | ++--------+-------------+----------------------+ +| 26 | AIN10 | PC0 | ++--------+-------------+----------------------+ +| 28 | AIN11 | PC1 | ++--------+-------------+----------------------+ +| 30 | NC | NC | ++--------+-------------+----------------------+ + +More detailed information about the connectors can be found in +`96Boards IE Specification`_. + +External Clock Sources +---------------------- + +STM32F4 has two external oscillators. The frequency of the slow clock is +32.768 kHz. The frequency of the main clock is 16 MHz. + +Serial Port +----------- + +96Boards Carbon board has up to 4 U(S)ARTs. The Zephyr console output is +assigned to USART1. Default settings are 115200 8N1. + +I2C +--- + +96Boards Carbon board has up to 2 I2Cs. The default I2C mapping for Zephyr is: + +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PB3 + +SPI +--- + +96Boards Carbon board has up to 2 SPIs. SPI1 is used for Bluetooth communication +over HCI. The default SPI mapping for Zephyr is: + +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 + +USB +=== + +96Boards Carbon board has a USB OTG dual-role device (DRD) controller that +supports both device and host functions through its mini "OTG" USB connector. +Only USB device functions are supported in Zephyr at the moment. + +- USB_DM : PA11 +- USB_DP : PA12 + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. The ROM bootloader +supports flashing via USB (DFU), UART, I2C and SPI. You can read more about +how to enable and use the ROM bootloader by checking the application +note `AN2606`_, page 109. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +Flashing an Application to 96Boards Carbon +------------------------------------------ + +Connect the micro-USB cable to the USB OTG Carbon port and to your computer. +The board should power ON. Force the board into DFU mode by keeping the BOOT0 +switch pressed while pressing and releasing the RST switch. + +Confirm that the board is in DFU mode: + +.. code-block:: console + + $ sudo dfu-util -l + dfu-util 0.8 + Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. + Copyright 2010-2014 Tormod Volden and Stefan Schmidt + This program is Free Software and has ABSOLUTELY NO WARRANTY + Please report bugs to dfu-util@lists.gnumonks.org + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", serial="3574364C3034" + Found Runtime: [05ac:8290] ver=0104, devnum=2, cfg=1, intf=5, alt=0, name="UNKNOWN", serial="UNKNOWN" + +You should see following confirmation on your Linux host: + +.. code-block:: console + + $ dmesg + usb 1-2.1: new full-speed USB device number 14 using xhci_hcd + usb 1-2.1: New USB device found, idVendor=0483, idProduct=df11 + usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 + usb 1-2.1: Product: STM32 BOOTLOADER + usb 1-2.1: Manufacturer: STMicroelectronics + usb 1-2.1: SerialNumber: 3574364C3034 + +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_carbon/stm32f401xe + :goals: build flash + +Connect the micro-USB cable to the USB UART (FTDI) port and to your computer. +Run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board 96Boards Carbon +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. +The ``-b`` option sets baud rate ignoring the value from config. + +Press the Reset button and you should see the following message in your +terminal: + +.. code-block:: console + + Hello World! arm + +.. _96b_carbon_verify_bluetooth: + +Verifying Bluetooth Functionality +--------------------------------- + +This section contains instructions for verifying basic Bluetooth +functionality on the board. For help on Zephyr applications +in general, see :ref:`build_an_application`. + +1. Flash the nRF51 with the hci_spi sample application as described in + :ref:`96b_carbon_nrf51_bluetooth`. + +#. Install the dfu-util flashing app, as described above. + +#. Build and flash the ``samples/bluetooth/ipsp`` application for + 96b_carbon. See the instructions above for how to put your board + into DFU mode if you haven't done this before: + + .. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/ipsp + :board: 96b_carbon/stm32f401xe + :goals: build flash + +#. Refer to the instructions in :ref:`bluetooth-ipsp-sample` for how + to verify functionality. + +Congratulations! Your 96Boards Carbon now has Bluetooth +connectivity. Refer to :ref:`bluetooth` for additional information on +further Bluetooth application development. + +Debugging +========= + +The ``96b_carbon/stm32f401xe`` board can be debugged by installing a 100 mil (0.1 inch) header +into the header at the bottom right hand side of the board, and +attaching an SWD debugger to the 3V3 (3.3V), GND, CLK, DIO, and RST +pins on that header. Then apply power to the 96Boards Carbon via one +of its USB connectors. You can now attach your debugger to the +STM32F401RET using an SWD scan. + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _AN2606: + https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf + +.. _96Boards website: + http://www.96boards.org/documentation + +.. _STM32F401RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f401re.html + +.. _STM32F401 reference manual: + https://www.st.com/resource/en/reference_manual/dm00096844.pdf + +.. _96Boards IE Specification: + https://linaro.co/ie-specification diff --git a/boards/96boards/carbon/pre_dt_board.cmake b/boards/96boards/carbon/pre_dt_board.cmake new file mode 100644 index 00000000000..2b6fc0edc87 --- /dev/null +++ b/boards/96boards/carbon/pre_dt_board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2022 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +if("${BOARD_IDENTIFIER}" STREQUAL "/nrf51822") + # Suppress "unique_unit_address_if_enabled" to handle the following overlaps: + # - power@40000000 & clock@40000000 & nrf-mpu@40000000 + list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") +endif() diff --git a/boards/96boards/index.rst b/boards/96boards/index.rst new file mode 100644 index 00000000000..9778649e7d9 --- /dev/null +++ b/boards/96boards/index.rst @@ -0,0 +1,10 @@ +.. _boards-96boards: + +96Boards +######## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/96b_meerkat96/96b_meerkat96-pinctrl.dtsi b/boards/96boards/meerkat96/96b_meerkat96-pinctrl.dtsi similarity index 100% rename from boards/arm/96b_meerkat96/96b_meerkat96-pinctrl.dtsi rename to boards/96boards/meerkat96/96b_meerkat96-pinctrl.dtsi diff --git a/boards/arm/96b_meerkat96/96b_meerkat96.dts b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts similarity index 100% rename from boards/arm/96b_meerkat96/96b_meerkat96.dts rename to boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts diff --git a/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml new file mode 100644 index 00000000000..39f57323369 --- /dev/null +++ b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml @@ -0,0 +1,24 @@ +# +# Copyright (c) 2019, Linaro Ltd. +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: 96b_meerkat96/mcimx7d/m4 +name: 96Boards Meerkat96 +type: mcu +arch: arm +ram: 32 +flash: 32 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - shell +testing: + ignore_tags: + - net + - bluetooth +vendor: novtech diff --git a/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig new file mode 100644 index 00000000000..90dfb85138a --- /dev/null +++ b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig @@ -0,0 +1,18 @@ +# +# Copyright (c) 2019, Linaro Ltd. +# +# SPDX-License-Identifier: Apache-2.0 +# + +# enable uart driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# pinctrl +CONFIG_PINCTRL=y + +CONFIG_XIP=y diff --git a/boards/96boards/meerkat96/Kconfig.96b_meerkat96 b/boards/96boards/meerkat96/Kconfig.96b_meerkat96 new file mode 100644 index 00000000000..9c5ce686496 --- /dev/null +++ b/boards/96boards/meerkat96/Kconfig.96b_meerkat96 @@ -0,0 +1,7 @@ +# Copyright (c) 2019, Linaro Ltd. +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_MEERKAT96 + select SOC_PART_NUMBER_MCIMX7D5EVM10SC + select SOC_MCIMX7D_M4 if BOARD_96B_MEERKAT96_MCIMX7D_M4 diff --git a/boards/96boards/meerkat96/Kconfig.defconfig b/boards/96boards/meerkat96/Kconfig.defconfig new file mode 100644 index 00000000000..a401b7ecb89 --- /dev/null +++ b/boards/96boards/meerkat96/Kconfig.defconfig @@ -0,0 +1,15 @@ +# 96Boards Meerkat96 board + +# Copyright (c) 2019, Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_MEERKAT96 + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_96B_MEERKAT96 diff --git a/boards/96boards/meerkat96/board.yml b/boards/96boards/meerkat96/board.yml new file mode 100644 index 00000000000..48d60ae6888 --- /dev/null +++ b/boards/96boards/meerkat96/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_meerkat96 + vendor: 96boards + socs: + - name: mcimx7d diff --git a/boards/arm/96b_meerkat96/doc/img/96b_meerkat96.jpg b/boards/96boards/meerkat96/doc/img/96b_meerkat96.jpg similarity index 100% rename from boards/arm/96b_meerkat96/doc/img/96b_meerkat96.jpg rename to boards/96boards/meerkat96/doc/img/96b_meerkat96.jpg diff --git a/boards/96boards/meerkat96/doc/index.rst b/boards/96boards/meerkat96/doc/index.rst new file mode 100644 index 00000000000..c76229de75b --- /dev/null +++ b/boards/96boards/meerkat96/doc/index.rst @@ -0,0 +1,325 @@ +.. _96b_meerkat96: + +96Boards Meerkat96 +################## + +Overview +******** + +96Boards Meerkat96 board is based on NXP i.MX7 Hybrid multi-core processor, +composed of a dual Cortex®-A7 and a single Cortex®-M4 core. +Zephyr OS is ported to run on the Cortex®-M4 core. + +- Board features: + + - RAM: 512 Mbyte + - Storage: + + - microSD Socket + - Wireless: + + - WiFi: 2.4GHz IEEE 802.11b/g/n + - Bluetooth: v4.1 (BR/EDR) + - USB: + + - Host - 2x type A + - OTG: - 1x type micro-B + - HDMI + - Connectors: + + - 40-Pin Low Speed Header + - 60-Pin High Speed Header + - LEDs: + + - 4x Green user LEDs + - 1x Blue Bluetooth LED + - 1x Yellow WiFi LED + +.. image:: img/96b_meerkat96.jpg + :align: center + :alt: 96Boards Meerkat96 + +More information about the board can be found at the +`96Boards website`_. + +Hardware +******** + +The i.MX7 SoC provides the following hardware capabilities: + +- Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core + +- Memory + + - External DDR memory up to 1 Gbyte + - Internal RAM -> A7: 256KB SRAM + - Internal RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) + +- Display + + - RGB 1920x1080x24bpp + - 4-wire Resistive touch + +- Multimedia + + - 1x Camera Parallel Interface + - 1x Analog Audio Line in (Stereo) + - 1x Analog Audio Mic in (Mono) + - 1x Analog Audio Headphone out (Stereo) + +- Connectivity + + - USB 2.0 OTG (High Speed) + - USB 2.0 host (High Speed) + - 10/100 Mbit/s Ethernet PHY + - 4x I2C + - 4x SPI + - 7x UART + - 1x IrDA + - 20x PWM + - Up to 125 GPIO + - 4x Analog Input (12 Bit) + - 2x SDIO/SD/MMC (8 Bit) + - 2x CAN + +More information about the i.MX7 SoC can be found here: + +- `i.MX 7 Series Website`_ +- `i.MX 7 Dual Datasheet`_ +- `i.MX 7 Dual Reference Manual`_ + +Supported Features +================== + +The Zephyr 96b_meerkat96 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +96Boards Meerkat96 board was tested with the following pinmux controller +configuration. + ++---------------+-----------------+---------------------------+ +| Board Name | SoC Name | Usage | ++===============+=================+===========================+ +| UART_1 RXD | UART1_TXD | UART Console | ++---------------+-----------------+---------------------------+ +| UART_1 TXD | UART1_RXD | UART Console | ++---------------+-----------------+---------------------------+ +| LED_R1 | GPIO1_IO04 | LED0 | ++---------------+-----------------+---------------------------+ +| LED_R2 | GPIO1_IO05 | LED1 | ++---------------+-----------------+---------------------------+ +| LED_R3 | GPIO1_IO06 | LED2 | ++---------------+-----------------+---------------------------+ +| LED_R4 | GPIO1_IO07 | LED3 | ++---------------+-----------------+---------------------------+ + +System Clock +============ + +The M4 Core is configured to run at a 200 MHz clock speed. + +Serial Port +=========== + +The iMX7D SoC has seven UARTs. UART_1 is configured for the console and +the remaining are not used/tested. + +Programming and Debugging +************************* + +The 96Boards Meerkat96 board doesn't have QSPI flash for the M4 and it needs +to be started by the A7 core. The A7 core is responsible to load the M4 binary +application into the RAM, put the M4 in reset, set the M4 Program Counter and +Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at +bootloader level or after the Linux system has booted. + +The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: + ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=======================+========================+=======================+======================+ +| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 7 Dual Reference Manual`_ (section 2.1.2 and 2.1.3), and the +`Toradex Wiki`_. + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file :zephyr_file:`boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts` +with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. +The available configurations are: + +.. code-block:: none + + "zephyr,flash" + - &ddr_code + - &tcml_code + - &ocram_code + - &ocram_s_code + - &ocram_pxp_code + - &ocram_epdc_code + + "zephyr,sram" + - &ddr_sys + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + - &ocram_pxp_sys + - &ocram_epdc_sys + + +Below you will find the instructions to load and run Zephyr on M4 from +A7 using u-boot. + +Copy the compiled zephyr.bin to the first FAT partition of the SD card and +plug into the board. Power it up and stop the u-boot execution. +Set the u-boot environment variables and run the zephyr.bin from the +appropriated memory configured in the Zephyr compilation: + +.. code-block:: console + + setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' + # TCML + setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' + setenv bootm4tcml 'run m4tcml && run bootm4' + run bootm4tcml + # TCMU + setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' + setenv bootm4tcmu 'run m4tcmu && run bootm4' + run bootm4tcmu + # OCRAM + setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' + setenv bootm4ocram 'run m4ocram && run bootm4' + run bootm4ocram + # OCRAM_S + setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' + setenv bootm4ocrams 'run m4ocrams && run bootm4' + run bootm4ocrams + # DDR + setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' + setenv bootm4ddr 'run m4ddr && run bootm4' + run bootm4ddr + +Debugging +========= + +96Boards Meerkat96 board can be debugged by connecting an external JLink +JTAG debugger to the J4 debug connector. Then download and install +`J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. + +To run Zephyr Binary using J-Link create the following script in order to +get the Program Counter and Stack Pointer from zephyr.bin. + +get-pc-sp.sh: +.. code-block:: console + + #!/bin/sh + + firmware=$1 + + pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') + sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') + + echo pc=$pc + echo sp=$sp + + +Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` +.. code-block:: console + + pc=00900f01 + sp=00905020 + +Plug in the J-Link into the board and PC and run the J-Link command line tool: + +.. code-block:: console + + /usr/bin/JLinkExe -device Cortex-M4 -if JTAG -speed 4000 -autoconnect 1 -jtagconf -1,-1 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript + +The following steps are necessary to run the zephyr.bin: + +1. Put the M4 core in reset +2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) +3. Set PC (Program Counter) +4. Set SP (Stack Pointer) +5. Get the M4 core out of reset + +Issue the following commands inside J-Link commander: + +.. code-block:: console + + w4 0x3039000C 0xAC + loadfile zephyr.bin,0x00900000 + w4 0x00180000 00900f01 + w4 0x00180004 00905020 + w4 0x3039000C 0xAA + +With these mechanisms, applications for the ``96b_meerkat96`` board +configuration can be built and debugged in the usual way (see +:ref:`build_an_application` and :ref:`application_run` for more details). + +References +========== + +- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ +- `J-Link iMX7D Instructions`_ + +.. _96Boards website: + https://www.96boards.org/product/imx7-96/ + +.. _i.MX 7 Series Website: + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 + +.. _i.MX 7 Dual Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf + +.. _i.MX 7 Dual Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX7DRM + +.. _J-Link Tools: + https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack + +.. _NXP iMX7D Connect CortexM4.JLinkScript: + https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript + +.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: + https://www.nxp.com/docs/en/application-note/AN5317.pdf + +.. _J-Link iMX7D Instructions: + https://wiki.segger.com/IMX7D + +.. _Toradex Wiki: + https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/96b_neonkey/96b_neonkey.dts b/boards/96boards/neonkey/96b_neonkey.dts similarity index 100% rename from boards/arm/96b_neonkey/96b_neonkey.dts rename to boards/96boards/neonkey/96b_neonkey.dts diff --git a/boards/arm/96b_neonkey/96b_neonkey.yaml b/boards/96boards/neonkey/96b_neonkey.yaml similarity index 100% rename from boards/arm/96b_neonkey/96b_neonkey.yaml rename to boards/96boards/neonkey/96b_neonkey.yaml diff --git a/boards/arm/96b_neonkey/96b_neonkey_defconfig b/boards/96boards/neonkey/96b_neonkey_defconfig similarity index 85% rename from boards/arm/96b_neonkey/96b_neonkey_defconfig rename to boards/96boards/neonkey/96b_neonkey_defconfig index 1b51c0cc14a..82ee7285d52 100644 --- a/boards/arm/96b_neonkey/96b_neonkey_defconfig +++ b/boards/96boards/neonkey/96b_neonkey_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F411XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/neonkey/Kconfig.96b_neonkey b/boards/96boards/neonkey/Kconfig.96b_neonkey new file mode 100644 index 00000000000..63d01784688 --- /dev/null +++ b/boards/96boards/neonkey/Kconfig.96b_neonkey @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_NEONKEY + select SOC_STM32F411XE diff --git a/boards/96boards/neonkey/Kconfig.defconfig b/boards/96boards/neonkey/Kconfig.defconfig new file mode 100644 index 00000000000..ac39b66107e --- /dev/null +++ b/boards/96boards/neonkey/Kconfig.defconfig @@ -0,0 +1,12 @@ +# 96Boards Neonkey Board Configuration + +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_NEONKEY + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_96B_NEONKEY diff --git a/boards/96boards/neonkey/board.yml b/boards/96boards/neonkey/board.yml new file mode 100644 index 00000000000..214cdc883bb --- /dev/null +++ b/boards/96boards/neonkey/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_neonkey + vendor: 96boards + socs: + - name: stm32f411xe diff --git a/boards/arm/96b_neonkey/doc/img/96b_neonkey.jpg b/boards/96boards/neonkey/doc/img/96b_neonkey.jpg similarity index 100% rename from boards/arm/96b_neonkey/doc/img/96b_neonkey.jpg rename to boards/96boards/neonkey/doc/img/96b_neonkey.jpg diff --git a/boards/96boards/neonkey/doc/index.rst b/boards/96boards/neonkey/doc/index.rst new file mode 100644 index 00000000000..96308784941 --- /dev/null +++ b/boards/96boards/neonkey/doc/index.rst @@ -0,0 +1,232 @@ +.. _96b_neonkey: + +96Boards Neonkey +################ + +Overview +******** + +96Boards Neonkey board is based on the STMicroelectronics STM32F411CE +Cortex M4 CPU. + +.. figure:: img/96b_neonkey.jpg + :align: center + :alt: 96Boards Neonkey + + 96Boards Neonkey + +This board acts as a sensor hub platform for all 96Boards compliant +family products. It can also be used as a standalone board. + +Hardware +******** + +96Boards Neonkey provides the following hardware components: + +- STM32F411CE in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 84 MHz max CPU frequency +- 1.8V work voltage +- 512 KB Flash +- 128 KB SRAM +- On board sensors: + + - Temperature/Humidity: SI7034-A10 + - Pressure: BMP280 + - ALS/Proximity: RPR-0521RS + - Geomagnetic: BMM150 + - Accelerometer/Gyroscope: BMI160 + - AMR Hall sensor: MRMS501A + - Microphone: SPK0415HM4H-B + +- 4 User LEDs +- 15 General purpose LEDs +- GPIO with external interrupt capability +- I2C (3) +- SPI (1) +- I2S (1) + +Supported Features +================== + +The Zephyr 96b_neonkey board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +More details about the board can be found at `96Boards website`_. + +The default board configuration can be found in +:zephyr_file:`boards/96boards/neonkey/96b_neonkey_defconfig` + +Connections and IOs +=================== + +LED +--- + +- LED1 / User1 LED = PB12 +- LED2 / User2 LED = PB13 +- LED3 / User3 LED = PB14 +- LED4 / User4 LED = PB15 + +Push buttons +------------ + +- BUTTON = RST (SW1) +- BUTTON = USR (SW2) + +System Clock +============ + +96Boards Neonkey can be driven by an internal oscillator as well as the main +PLL clock. By default System clock is sourced by PLL clock at 84MHz, driven +by internal oscillator. + +Serial Port +=========== + +On 96Boards Neonkey Zephyr console output is assigned to USART1. +Default settings are 115200 8N1. + +I2C +--- + +96Boards Neonkey board has up to 3 I2Cs. The default I2C mapping for Zephyr is: + +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PB3 +- I2C3_SCL : PA8 +- I2C3_SCL : PB4 + +SPI +--- + +96Boards Neonkey board has one SPI. The default SPI mapping for Zephyr is: + +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 + +Programming and Debugging +************************* + +Building +======== + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_neonkey + :goals: build + +Flashing +======== + +96Boards Neonkey can be flashed by two methods, one using the ROM +bootloader and another using the SWD debug port (which requires additional +hardware). + +Using ROM bootloader: +--------------------- + +ROM bootloader can be triggered by the following pattern: + +1. Connect BOOT0 to VDD (link JTAG pins 1 and 5 on P4 header) +2. Press and hold the USR button +3. Press and release the RST button + +More detailed information on activating the ROM bootloader can be found in +Chapter 29 of Application note `AN2606`_. The ROM bootloader supports flashing +via UART, I2C and SPI protocols. + +For flashing, `stm32flash`_ command line utility can be used. The following +command will flash the ``zephyr.bin`` binary to the Neonkey board using UART +and starts its execution: + +.. code-block:: console + + $ stm32flash -w zephyr.bin -v -g 0x08000000 /dev/ttyS0 + +.. note:: + The above command assumes that Neonkey board is connected to + serial port ``/dev/ttyS0``. + +Using SWD debugger: +------------------- + +For flashing via SWD debug port, 0.1" male header must be soldered at P4 +header available at the bottom of the board, near RST button. + +Use the `Black Magic Debug Probe`_ as an SWD programmer, which can +be connected to the P4 header using its flying leads and its 20 Pin +JTAG Adapter Board Kit. When plugged into your host PC, the Black +Magic Debug Probe enumerates as a USB serial device as documented on +its `Getting started page`_. + +It also uses the GDB binary provided with the Zephyr SDK, +``arm-zephyr-eabi-gdb``. Other GDB binaries, such as the GDB from GCC +ARM Embedded, can be used as well. + +.. code-block:: console + + $ arm-zephyr-eabi-gdb -q zephyr.elf + (gdb) target extended-remote /dev/ttyACM0 + Remote debugging using /dev/ttyACM0 + (gdb) monitor swdp_scan + Target voltage: 1.8V + Available Targets: + No. Att Driver + 1 STM32F4xx + (gdb) attach 1 + Attaching to Remote target + 0x080005d0 in ?? () + (gdb) load + +Debugging +========= + +After flashing 96Boards Neonkey, it can be debugged using the same +GDB instance. To reattach, just follow the same steps above, till +"attach 1". You can then debug as usual with GDB. In particular, type +"run" at the GDB prompt to restart the program you've flashed. + +References +********** + +.. _96Boards website: + https://www.96boards.org/product/neonkey/ + +.. _AN2606: + https://www.st.com/resource/en/application_note/cd00167594.pdf + +.. _stm32flash: + https://sourceforge.net/p/stm32flash/wiki/Home/ + +.. _Black Magic Debug Probe: + https://github.com/blacksphere/blackmagic/wiki + +.. _Getting started page: + https://github.com/blacksphere/blackmagic/wiki/Getting-Started diff --git a/boards/arm/96b_nitrogen/96b_lscon.dtsi b/boards/96boards/nitrogen/96b_lscon.dtsi similarity index 100% rename from boards/arm/96b_nitrogen/96b_lscon.dtsi rename to boards/96boards/nitrogen/96b_lscon.dtsi diff --git a/boards/arm/96b_nitrogen/96b_nitrogen-pinctrl.dtsi b/boards/96boards/nitrogen/96b_nitrogen-pinctrl.dtsi similarity index 100% rename from boards/arm/96b_nitrogen/96b_nitrogen-pinctrl.dtsi rename to boards/96boards/nitrogen/96b_nitrogen-pinctrl.dtsi diff --git a/boards/arm/96b_nitrogen/96b_nitrogen.dts b/boards/96boards/nitrogen/96b_nitrogen.dts similarity index 100% rename from boards/arm/96b_nitrogen/96b_nitrogen.dts rename to boards/96boards/nitrogen/96b_nitrogen.dts diff --git a/boards/arm/96b_nitrogen/96b_nitrogen.yaml b/boards/96boards/nitrogen/96b_nitrogen.yaml similarity index 100% rename from boards/arm/96b_nitrogen/96b_nitrogen.yaml rename to boards/96boards/nitrogen/96b_nitrogen.yaml diff --git a/boards/arm/96b_nitrogen/96b_nitrogen_defconfig b/boards/96boards/nitrogen/96b_nitrogen_defconfig similarity index 77% rename from boards/arm/96b_nitrogen/96b_nitrogen_defconfig rename to boards/96boards/nitrogen/96b_nitrogen_defconfig index b8565973eb1..7167aca850a 100644 --- a/boards/arm/96b_nitrogen/96b_nitrogen_defconfig +++ b/boards/96boards/nitrogen/96b_nitrogen_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/nitrogen/Kconfig.96b_nitrogen b/boards/96boards/nitrogen/Kconfig.96b_nitrogen new file mode 100644 index 00000000000..7ae2b0710fb --- /dev/null +++ b/boards/96boards/nitrogen/Kconfig.96b_nitrogen @@ -0,0 +1,7 @@ +# 96Boards NITROGEN board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_NITROGEN + select SOC_NRF52832_QFAA diff --git a/boards/96boards/nitrogen/Kconfig.defconfig b/boards/96boards/nitrogen/Kconfig.defconfig new file mode 100644 index 00000000000..c1686a82539 --- /dev/null +++ b/boards/96boards/nitrogen/Kconfig.defconfig @@ -0,0 +1,11 @@ +# 96Boards NITROGEN board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_NITROGEN + +config BT_CTLR + default BT + +endif # BOARD_96B_NITROGEN diff --git a/boards/arm/96b_nitrogen/board.cmake b/boards/96boards/nitrogen/board.cmake similarity index 100% rename from boards/arm/96b_nitrogen/board.cmake rename to boards/96boards/nitrogen/board.cmake diff --git a/boards/96boards/nitrogen/board.yml b/boards/96boards/nitrogen/board.yml new file mode 100644 index 00000000000..279d2c63a66 --- /dev/null +++ b/boards/96boards/nitrogen/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_nitrogen + vendor: 96boards + socs: + - name: nrf52832 diff --git a/boards/arm/96b_nitrogen/doc/img/96b_nitrogen.jpg b/boards/96boards/nitrogen/doc/img/96b_nitrogen.jpg similarity index 100% rename from boards/arm/96b_nitrogen/doc/img/96b_nitrogen.jpg rename to boards/96boards/nitrogen/doc/img/96b_nitrogen.jpg diff --git a/boards/96boards/nitrogen/doc/index.rst b/boards/96boards/nitrogen/doc/index.rst new file mode 100644 index 00000000000..952f11237bf --- /dev/null +++ b/boards/96boards/nitrogen/doc/index.rst @@ -0,0 +1,329 @@ +.. _96b_nitrogen_board: + +96Boards Nitrogen +################# + +Overview +******** + +The 96Boards Nitrogen hardware provides support for the Nordic Semiconductor +nRF52832 ARM Cortex-M4F CPU. + +.. figure:: img/96b_nitrogen.jpg + :align: center + :alt: 96Boards Nitrogen + + 96Boards Nitrogen + +More information about the board can be found at the `seeed BLE Nitrogen`_ +website. The `Nordic Semiconductor Infocenter`_ contains the processor's +information and the datasheet. + +Hardware +******** + +96Boards Nitrogen provides the following hardware components: + +- nRF52832 microcontroller with 512kB Flash, 64kB RAM +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- Bluetooth LE +- NFC +- LPC11U35 on board SWD debugger + + - SWD debugger firmware + - USB to UART + - Drag and Drop firmware upgrade + +- 7 LEDs + + - USR1, BT, PWR, CDC, DAP, MSD, Battery charge + +- SWD debug connectors + + - nRF52832 SWD connector + - nRF52832 Uart connector + +- On board chip antenna +- 1.8V work voltage +- 2x20pin 2.0mm pitch Low speed connector + +Supported Features +================== + +The Zephyr 96b_nitrogen board configuration supports the following hardware +features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| NVIC | on-chip | nested vectored interrupt controller | ++-----------+------------+--------------------------------------+ +| RTC | on-chip | system clock | ++-----------+------------+--------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+--------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+--------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+--------------------------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+--------------------------------------+ +| RTT | on-chip | console | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. +See `Nordic Semiconductor Infocenter`_ for a complete list of nRF52-based +board hardware features. + +The default configuration can be found in +:zephyr_file:`boards/96boards/nitrogen/96b_nitrogen_defconfig` + +Pin Mapping +=========== + +LED +--- + +- LED1 / User LED (green) = P0.29 +- LED2 / BT LED (blue) = P0.28 + +Push buttons +------------ + +- BUTTON = SW1 = P0.27 + +External Connectors +------------------- + +Low Speed Header + ++--------+-------------+----------------------+ +| PIN # | Signal Name | nRF52832 Functions | ++========+=============+======================+ +| 1 | GND | GND | ++--------+-------------+----------------------+ +| 3 | UART CTS | P.014 / TRACEDATA[3] | ++--------+-------------+----------------------+ +| 5 | UART TX | P0.13 | ++--------+-------------+----------------------+ +| 7 | UART RX | P0.15 / TRACEDATA[2] | ++--------+-------------+----------------------+ +| 9 | UART RTS | P0.12 | ++--------+-------------+----------------------+ +| 11 | UART TX | P0.13 | ++--------+-------------+----------------------+ +| 13 | UART RX | P0.15 / TRACEDATA[2] | ++--------+-------------+----------------------+ +| 15 | P0.22 | P0.22 | ++--------+-------------+----------------------+ +| 17 | P0.20 | P0.20 | ++--------+-------------+----------------------+ +| 19 | N/A | N/A | ++--------+-------------+----------------------+ +| 21 | N/A | N/A | ++--------+-------------+----------------------+ +| 23 | P0.02 | P0.02 | ++--------+-------------+----------------------+ +| 25 | P0.04 | P0.04 | ++--------+-------------+----------------------+ +| 27 | P0.06 | P0.06 | ++--------+-------------+----------------------+ +| 29 | P0.08 | P0.08 | ++--------+-------------+----------------------+ +| 31 | P0.16 | P0.16 | ++--------+-------------+----------------------+ +| 33 | P0.18 | P0.18 | ++--------+-------------+----------------------+ +| 35 | VCC | | ++--------+-------------+----------------------+ +| 37 | USB5V | | ++--------+-------------+----------------------+ +| 39 | GND | GND | ++--------+-------------+----------------------+ + ++--------+-------------+----------------------+ +| PIN # | Signal Name | nRF52832 Functions | ++========+=============+======================+ +| 2 | GND | GND | ++--------+-------------+----------------------+ +| 4 | PWR BTN | | ++--------+-------------+----------------------+ +| 6 | RST BTN | P0.21 / RESET | ++--------+-------------+----------------------+ +| 8 | P0.26 | P0.26 | ++--------+-------------+----------------------+ +| 10 | P0.25 | P0.25 | ++--------+-------------+----------------------+ +| 12 | P0.24 | P0.24 | ++--------+-------------+----------------------+ +| 14 | P0.23 | P0.23 | ++--------+-------------+----------------------+ +| 16 | N/A | N/A | ++--------+-------------+----------------------+ +| 18 | N/A | PC7 | ++--------+-------------+----------------------+ +| 20 | N/A | PC9 | ++--------+-------------+----------------------+ +| 22 | N/A | PB8 | ++--------+-------------+----------------------+ +| 24 | P0.03 | P0.03 | ++--------+-------------+----------------------+ +| 26 | P0.05 | P0.05 | ++--------+-------------+----------------------+ +| 28 | P0.07 | P0.07 | ++--------+-------------+----------------------+ +| 30 | P0.11 | P0.11 | ++--------+-------------+----------------------+ +| 32 | P0.17 | P0.17 | ++--------+-------------+----------------------+ +| 34 | P0.19 | P0.19 | ++--------+-------------+----------------------+ +| 36 | NC | | ++--------+-------------+----------------------+ +| 38 | NC | | ++--------+-------------+----------------------+ +| 40 | GND | GND | ++--------+-------------+----------------------+ + +More detailed information about the connectors can be found in +`96Boards IE Specification`_. + +System Clock +============ + +nRF52 has two external oscillators. The frequency of the slow clock is +32.768 kHz. The frequency of the main clock is 32 MHz. + +Serial Port +----------- + +96Boards Nitrogen has one UART, which is used as Zephyr console. +Default settings is 115200 8N1. + +I2C +--- + +96Boards Nitrogen has one I2C. The default I2C mapping for Zephyr is: + +- I2C0_SCL : P0.22 +- I2C0_SDA : P0.20 + +SPI +--- + +96Boards Nitrogen has one SPI. The default SPI mapping for Zephyr is: + +- SPI0_NSS : P0.24 +- SPI0_SCK : P0.26 +- SPI0_MISO : P0.25 +- SPI0_MOSI : P0.23 + +Flashing Zephyr onto 96Boards Nitrogen +************************************** + +The 96Boards Nitrogen board can be flashed via the `CMSIS DAP`_ interface, +which is provided by the micro USB interface to the LPC11U35 chip. + +Using the CMSIS-DAP interface, the board can be flashed via the USB storage +interface (drag-and-drop) and also via `pyOCD`_. + +To use ``pyOCD``, install the :ref:`pyocd-debug-host-tools` and make sure they +are in your search path. + +Common Errors +============= + +No connected boards +------------------- + +If you don't use sudo when invoking pyocd-flashtool, you might get any of the +following errors: + +.. code-block:: console + + No available boards are connected + +.. code-block:: console + + No connected boards + +.. code-block:: console + + Error: There is no board connected. + +To fix the permission issue, simply add the following udev rule for the +NXP LPC1768 interface: + +.. code-block:: console + + $ echo 'ATTR{idProduct}=="0204", ATTR{idVendor}=="0d28", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-cmsis-dap.rules + +Finally, unplug and plug the board again. + +ValueError: The device has no langid +------------------------------------ + +As described by `pyOCD issue 259`_, you might get the +:code:`ValueError: The device has no langid` error when not running +pyOCD as root (e.g. sudo). + +To fix the above error, add the udev rule shown in the previous section +and install a more recent version of pyOCD. + +Flashing an Application to 96Boards Nitrogen +============================================ + +Here is an example for the :ref:`hello_world` application. This +requires installing the :ref:`pyocd-debug-host-tools`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_nitrogen + :goals: build flash + +Run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board 96Boards Nitrogen +can be found. For example, under Linux, :code:`/dev/ttyACM0`. +The ``-b`` option sets baud rate ignoring the value from config. + +Press the Reset button and you should see the following message in your +terminal: + +.. code-block:: console + + Hello World! arm + +Debugging with GDB +================== + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. This also requires pyOCD. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_nitrogen + :maybe-skip-config: + :goals: debug + +.. _pyOCD: + https://github.com/mbedmicro/pyOCD + +.. _CMSIS DAP: + https://developer.mbed.org/handbook/CMSIS-DAP + +.. _Nordic Semiconductor Infocenter: + http://infocenter.nordicsemi.com/ + +.. _seeed BLE Nitrogen: + http://wiki.seeed.cc/BLE_Nitrogen/ + +.. _pyOCD issue 259: + https://github.com/mbedmicro/pyOCD/issues/259 + +.. _96Boards IE Specification: + https://linaro.co/ie-specification diff --git a/boards/arm/96b_nitrogen/pre_dt_board.cmake b/boards/96boards/nitrogen/pre_dt_board.cmake similarity index 100% rename from boards/arm/96b_nitrogen/pre_dt_board.cmake rename to boards/96boards/nitrogen/pre_dt_board.cmake diff --git a/boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez.dts b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts similarity index 100% rename from boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez.dts rename to boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts diff --git a/boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez.yaml b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.yaml similarity index 100% rename from boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez.yaml rename to boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.yaml diff --git a/boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez_defconfig b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig similarity index 84% rename from boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez_defconfig rename to boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig index a9e0141c125..c729b83e3d0 100644 --- a/boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez_defconfig +++ b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F446XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/stm32_sensor_mez/Kconfig.96b_stm32_sensor_mez b/boards/96boards/stm32_sensor_mez/Kconfig.96b_stm32_sensor_mez new file mode 100644 index 00000000000..aa4bd5b97bb --- /dev/null +++ b/boards/96boards/stm32_sensor_mez/Kconfig.96b_stm32_sensor_mez @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_STM32_SENSOR_MEZ + select SOC_STM32F446XX diff --git a/boards/96boards/stm32_sensor_mez/Kconfig.defconfig b/boards/96boards/stm32_sensor_mez/Kconfig.defconfig new file mode 100644 index 00000000000..f6678ae9110 --- /dev/null +++ b/boards/96boards/stm32_sensor_mez/Kconfig.defconfig @@ -0,0 +1,12 @@ +# 96Boards STM32 Sensor Mezzanine board configuration + +# Copyright (c) 2018 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_STM32_SENSOR_MEZ + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_96B_STM32_SENSOR_MEZ diff --git a/boards/arm/96b_stm32_sensor_mez/board.cmake b/boards/96boards/stm32_sensor_mez/board.cmake similarity index 100% rename from boards/arm/96b_stm32_sensor_mez/board.cmake rename to boards/96boards/stm32_sensor_mez/board.cmake diff --git a/boards/96boards/stm32_sensor_mez/board.yml b/boards/96boards/stm32_sensor_mez/board.yml new file mode 100644 index 00000000000..e410dcc9e65 --- /dev/null +++ b/boards/96boards/stm32_sensor_mez/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_stm32_sensor_mez + vendor: st + socs: + - name: stm32f446xx diff --git a/boards/arm/96b_stm32_sensor_mez/doc/img/96b_stm32_sensor_mez.jpg b/boards/96boards/stm32_sensor_mez/doc/img/96b_stm32_sensor_mez.jpg similarity index 100% rename from boards/arm/96b_stm32_sensor_mez/doc/img/96b_stm32_sensor_mez.jpg rename to boards/96boards/stm32_sensor_mez/doc/img/96b_stm32_sensor_mez.jpg diff --git a/boards/96boards/stm32_sensor_mez/doc/index.rst b/boards/96boards/stm32_sensor_mez/doc/index.rst new file mode 100644 index 00000000000..350d4720a80 --- /dev/null +++ b/boards/96boards/stm32_sensor_mez/doc/index.rst @@ -0,0 +1,247 @@ +.. _96b_stm32_sensor_mez: + +96Boards STM32 Sensor Mezzanine +############################### + +Overview +******** + +96Boards STM32 Sensor Mezzanine is based on the ST Microelectronics +STM32F446VE Cortex M4 CPU. + +This board acts as a mezzanine platform for all 96Boards CE compliant +boards. It can also be used as a standalone board. + +.. figure:: img/96b_stm32_sensor_mez.jpg + :align: center + :alt: 96Boards STM32 Sensor Mezzanine + + 96Boards STM32 Sensor Mezzanine + +Hardware +******** + +96Boards STM32 Sensor Mezzanine provides the following hardware components: + +- STM32F446VE in LQFP100 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 180 MHz max CPU frequency +- 1.8V work voltage +- 512 KB Flash +- 128 KB SRAM +- On board sensors: + + - Temperature/Pressure: STMicro LPS22HB + - Accelerometer/Gyroscope: STMicro LSM6DS3H + - Magnetometer: STMicro LIS3MDL + - Microphone: STMicro MP34DT01 + +- 3User LEDs +- GPIO with external interrupt capability +- UART +- I2C (2) +- SPI (3) +- I2S (1) + +Supported Features +================== + +The Zephyr 96b_stm32_sensor_mez board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ + +The default board configuration can be found in +:zephyr_file:`boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig` + +Connections and IOs +=================== + +LED +--- + +- LED1 / User1 LED = PD10 +- LED2 / User2 LED = PD11 +- LED3 / User3 LED = PD12 + +Push buttons +------------ + +- BUTTON = RST (BT1) +- BUTTON = USR (BT2) + +System Clock +============ + +96Boards STM32 Sensor Mezzanine can be driven by an internal oscillator as +well as the main PLL clock. In default board configuration, the 16MHz external +oscillator is used to drive the main PLL clock to generate a System Clock +(SYSCLK) at 84MHz. On the bus side, AHB/APB2 clocks runs at 84MHz, while APB1 +clock runs at 42MHz. + +Serial Port +=========== + +On 96Boards STM32 Sensor Mezzanine, Zephyr console output is assigned to UART4 +exposed via on-board Micro USB connector. Default settings are 115200 8N1. + +The default USART mappings for the remaining ones are: + +- USART1: Connected to AP via UART0 on the 96Boards Low-Speed Header. + - TX: PA9 + - RX: PA10 + +- USART2: Connected to D0(RX) and D1(TX) on the Arduino Header. + - TX: PD5 + - RX: PD6 + +- USART3: Broken out to Grove connector J10. + - TX: PD8 + - RX: PD9 + +I2C +--- + +96Boards STM32 Sensor Mezzanine board has up to 3 I2Cs. The default I2C +mapping is: + +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PC12 + +I2C2 goes to the Groove connectors and can be used to attach external sensors. + +SPI +--- +96Boards STM32 Sensor Mezzanine board has 3 SPIs. SPI1 is used in slave mode +as the communication bus with the AP. SPI2 is used in master mode to control +the LSM6DS3H sensor. SPI4 is broken out to Grove Connector J5. +The default SPI mapping is: + +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB9 +- SPI2_SCK : PD3 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 +- SPI4_NSS : PE11 +- SPI4_SCK : PE12 +- SPI4_MISO : PE13 +- SPI4_MOSI : PE14 + +PWM +--- +96Boards STM32 Sensor Mezzanine board exposes 6 PWM channels on the Arduino +connector. The default PWM mapping is: + +- PWM3_CH1 : PB4 : D9 +- PWM3_CH3 : PC8 : D3 +- PWM4_CH3 : PD14 : D6 +- PWM4_CH4 : PD15 : D5 +- PWM9_CH1 : PE5 : D12 +- PWM9_CH2 : PE6 : D11 + +I2S +--- + +96Boards STM32 Sensor Mezzanine board exposes 1 I2S port which is connected +to the on-board ST MP34DT01 DMIC. The default I2S mapping is: + +- I2S2_SD : PC1 +- I2S2_CK : PC7 + +Programming and Debugging +************************* + +Building +======== + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_stm32_sensor_mez + :goals: build + +Flashing +======== + +96Boards STM32 Sensor Mezzanine board includes an ST-LINK/V2-1 embedded +debug tool interface. This interface is supported by the openocd version +included in the Zephyr SDK. + +Flashing an application to 96Boards STM32 Sensor Mezzanine +---------------------------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your 96Boards STM32 Sensor Mezzanine +board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_stm32_sensor_mez + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! 96b_stm32_sensor_mez + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_stm32_sensor_mez + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _96Boards STM32 Sensor Mezzanine website: + https://www.96boards.org/documentation/mezzanine/stm32/ + +.. _STM32F446VE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f446ve.html + +.. _STM32F446 reference manual: + https://www.st.com/resource/en/reference_manual/dm00135183.pdf diff --git a/boards/arm/96b_stm32_sensor_mez/support/openocd.cfg b/boards/96boards/stm32_sensor_mez/support/openocd.cfg similarity index 100% rename from boards/arm/96b_stm32_sensor_mez/support/openocd.cfg rename to boards/96boards/stm32_sensor_mez/support/openocd.cfg diff --git a/boards/arm/96b_wistrio/96b_lscon.dtsi b/boards/96boards/wistrio/96b_lscon.dtsi similarity index 100% rename from boards/arm/96b_wistrio/96b_lscon.dtsi rename to boards/96boards/wistrio/96b_lscon.dtsi diff --git a/boards/arm/96b_wistrio/96b_wistrio.dts b/boards/96boards/wistrio/96b_wistrio.dts similarity index 100% rename from boards/arm/96b_wistrio/96b_wistrio.dts rename to boards/96boards/wistrio/96b_wistrio.dts diff --git a/boards/arm/96b_wistrio/96b_wistrio.yaml b/boards/96boards/wistrio/96b_wistrio.yaml similarity index 100% rename from boards/arm/96b_wistrio/96b_wistrio.yaml rename to boards/96boards/wistrio/96b_wistrio.yaml diff --git a/boards/arm/96b_wistrio/96b_wistrio_defconfig b/boards/96boards/wistrio/96b_wistrio_defconfig similarity index 83% rename from boards/arm/96b_wistrio/96b_wistrio_defconfig rename to boards/96boards/wistrio/96b_wistrio_defconfig index 9520805e917..23d51e28afa 100644 --- a/boards/arm/96b_wistrio/96b_wistrio_defconfig +++ b/boards/96boards/wistrio/96b_wistrio_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32L1X=y -CONFIG_SOC_STM32L151XBA=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/96b_wistrio/CMakeLists.txt b/boards/96boards/wistrio/CMakeLists.txt similarity index 100% rename from boards/arm/96b_wistrio/CMakeLists.txt rename to boards/96boards/wistrio/CMakeLists.txt diff --git a/boards/96boards/wistrio/Kconfig.96b_wistrio b/boards/96boards/wistrio/Kconfig.96b_wistrio new file mode 100644 index 00000000000..f66f9ba9b5f --- /dev/null +++ b/boards/96boards/wistrio/Kconfig.96b_wistrio @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_WISTRIO + select SOC_STM32L151XBA diff --git a/boards/96boards/wistrio/Kconfig.defconfig b/boards/96boards/wistrio/Kconfig.defconfig new file mode 100644 index 00000000000..751ed00ab7e --- /dev/null +++ b/boards/96boards/wistrio/Kconfig.defconfig @@ -0,0 +1,11 @@ +# 96boards WisTrio board configuration + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_WISTRIO + +config REGULATOR + default y if LORA + +endif # BOARD_96B_WISTRIO diff --git a/boards/arm/96b_wistrio/board.cmake b/boards/96boards/wistrio/board.cmake similarity index 100% rename from boards/arm/96b_wistrio/board.cmake rename to boards/96boards/wistrio/board.cmake diff --git a/boards/96boards/wistrio/board.yml b/boards/96boards/wistrio/board.yml new file mode 100644 index 00000000000..508c590a6b5 --- /dev/null +++ b/boards/96boards/wistrio/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_wistrio + vendor: 96boards + socs: + - name: stm32l151xba diff --git a/boards/arm/96b_wistrio/doc/96b_wistrio.rst b/boards/96boards/wistrio/doc/96b_wistrio.rst similarity index 97% rename from boards/arm/96b_wistrio/doc/96b_wistrio.rst rename to boards/96boards/wistrio/doc/96b_wistrio.rst index 58bb3ee18b8..14f93e6bae1 100644 --- a/boards/arm/96b_wistrio/doc/96b_wistrio.rst +++ b/boards/96boards/wistrio/doc/96b_wistrio.rst @@ -70,9 +70,8 @@ features: | EEPROM | on-chip | eeprom | +-----------+------------+-------------------------------------+ -The default board configuration can be found in the defconfig file: - - ``boards/arm/96b_wistrio/96b_wistrio_defconfig`` +The default board configuration can be found in +:zephyr_file:`boards/96boards/wistrio/96b_wistrio_defconfig` Connections and IOs =================== diff --git a/boards/arm/96b_wistrio/doc/img/96b-wistrio.jpg b/boards/96boards/wistrio/doc/img/96b-wistrio.jpg similarity index 100% rename from boards/arm/96b_wistrio/doc/img/96b-wistrio.jpg rename to boards/96boards/wistrio/doc/img/96b-wistrio.jpg diff --git a/boards/arm/96b_wistrio/dts/bindings/qorvo,rfsw8001.yaml b/boards/96boards/wistrio/dts/bindings/qorvo,rfsw8001.yaml similarity index 100% rename from boards/arm/96b_wistrio/dts/bindings/qorvo,rfsw8001.yaml rename to boards/96boards/wistrio/dts/bindings/qorvo,rfsw8001.yaml diff --git a/boards/arm/96b_wistrio/rf.c b/boards/96boards/wistrio/rf.c similarity index 100% rename from boards/arm/96b_wistrio/rf.c rename to boards/96boards/wistrio/rf.c diff --git a/boards/Kconfig b/boards/Kconfig index f56c2cab04e..9268b7c0c9d 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -2,6 +2,8 @@ config BOARD string + # When using hw model v2, then the board is inherited from CMake. + default "$(BOARD)" if "$(HWM_SCHEME)" = "v2" help This option holds the name of the board and is used to locate the files related to the board in the source tree (under boards/). @@ -38,14 +40,7 @@ config NET_DRIVERS When building for a qemu target then NET_DRIVERS will be default enabled to allow for easy use of SLIP or PPP -# Note: $BOARD_DIR might be a glob pattern - -choice - prompt "Board Selection" - -source "$(BOARD_DIR)/Kconfig.board" - -endchoice +rsource "Kconfig.$(HWM_SCHEME)" # Parse shields references # Don't do it as a menuconfig, as shield selection is a CMake feature. diff --git a/boards/Kconfig.v1 b/boards/Kconfig.v1 new file mode 100644 index 00000000000..670e2f2376e --- /dev/null +++ b/boards/Kconfig.v1 @@ -0,0 +1,10 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Board Selection" + +source "$(BOARD_DIR)/Kconfig.board" + +endchoice diff --git a/boards/Kconfig.v2 b/boards/Kconfig.v2 new file mode 100644 index 00000000000..a2221dd04b9 --- /dev/null +++ b/boards/Kconfig.v2 @@ -0,0 +1,18 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +BOARD_STRING := $(sanitize_upper,$(BOARD)) +BOARD_FULL_STRING := $(sanitize_upper,$(BOARD)$(BOARD_IDENTIFIER)) + +config BOARD_$(BOARD_STRING) + def_bool y + help + Kconfig symbol identifying the board. + +config BOARD_$(BOARD_FULL_STRING) + def_bool y + help + Kconfig symbol identifying the board including full board identifier. + +osource "$(BOARD_DIR)/Kconfig.$(BOARD)" diff --git a/boards/aconno/acn52832/Kconfig.acn52832 b/boards/aconno/acn52832/Kconfig.acn52832 new file mode 100644 index 00000000000..ef035c30f9d --- /dev/null +++ b/boards/aconno/acn52832/Kconfig.acn52832 @@ -0,0 +1,7 @@ +# aconno acn52832 board configuration + +# Copyright (c) 2023 Sven Herrmann +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACN52832 + select SOC_NRF52832_QFAA diff --git a/boards/aconno/acn52832/Kconfig.defconfig b/boards/aconno/acn52832/Kconfig.defconfig new file mode 100644 index 00000000000..10c5ce95ed8 --- /dev/null +++ b/boards/aconno/acn52832/Kconfig.defconfig @@ -0,0 +1,11 @@ +# aconno acn52832 board configuration + +# Copyright (c) 2023 Sven Herrmann +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ACN52832 + +config BT_CTLR + default BT + +endif # BOARD_ACN52832 diff --git a/boards/arm/acn52832/acn52832-pinctrl.dtsi b/boards/aconno/acn52832/acn52832-pinctrl.dtsi similarity index 100% rename from boards/arm/acn52832/acn52832-pinctrl.dtsi rename to boards/aconno/acn52832/acn52832-pinctrl.dtsi diff --git a/boards/arm/acn52832/acn52832.dts b/boards/aconno/acn52832/acn52832.dts similarity index 100% rename from boards/arm/acn52832/acn52832.dts rename to boards/aconno/acn52832/acn52832.dts diff --git a/boards/arm/acn52832/acn52832.yaml b/boards/aconno/acn52832/acn52832.yaml similarity index 100% rename from boards/arm/acn52832/acn52832.yaml rename to boards/aconno/acn52832/acn52832.yaml diff --git a/boards/aconno/acn52832/acn52832_defconfig b/boards/aconno/acn52832/acn52832_defconfig new file mode 100644 index 00000000000..7167aca850a --- /dev/null +++ b/boards/aconno/acn52832/acn52832_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/acn52832/board.cmake b/boards/aconno/acn52832/board.cmake similarity index 100% rename from boards/arm/acn52832/board.cmake rename to boards/aconno/acn52832/board.cmake diff --git a/boards/aconno/acn52832/board.yml b/boards/aconno/acn52832/board.yml new file mode 100644 index 00000000000..179637e1ded --- /dev/null +++ b/boards/aconno/acn52832/board.yml @@ -0,0 +1,5 @@ +board: + name: acn52832 + vendor: aconno + socs: + - name: nrf52832 diff --git a/boards/arm/acn52832/doc/index.rst b/boards/aconno/acn52832/doc/index.rst similarity index 100% rename from boards/arm/acn52832/doc/index.rst rename to boards/aconno/acn52832/doc/index.rst diff --git a/boards/arm/acn52832/pre_dt_board.cmake b/boards/aconno/acn52832/pre_dt_board.cmake similarity index 100% rename from boards/arm/acn52832/pre_dt_board.cmake rename to boards/aconno/acn52832/pre_dt_board.cmake diff --git a/boards/aconno/index.rst b/boards/aconno/index.rst new file mode 100644 index 00000000000..4e79f407b98 --- /dev/null +++ b/boards/aconno/index.rst @@ -0,0 +1,10 @@ +.. _boards-aconno: + +Aconno +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/x86/acrn/CMakeLists.txt b/boards/acrn/acrn/CMakeLists.txt similarity index 100% rename from boards/x86/acrn/CMakeLists.txt rename to boards/acrn/acrn/CMakeLists.txt diff --git a/boards/acrn/acrn/Kconfig b/boards/acrn/acrn/Kconfig new file mode 100644 index 00000000000..7d7b97605a4 --- /dev/null +++ b/boards/acrn/acrn/Kconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2019-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACRN + bool + select CPU_HAS_FPU + select X86_64 + help + "ACRN User OS" + +config BOARD_ACRN_EHL_CRB + bool + select CPU_HAS_FPU + select X86_64 + help + "ACRN User OS on ElkhartLake CRB" diff --git a/boards/acrn/acrn/Kconfig.acrn b/boards/acrn/acrn/Kconfig.acrn new file mode 100644 index 00000000000..8d1e1db92b4 --- /dev/null +++ b/boards/acrn/acrn/Kconfig.acrn @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACRN + select SOC_ATOM diff --git a/boards/acrn/acrn/Kconfig.acrn_ehl_crb b/boards/acrn/acrn/Kconfig.acrn_ehl_crb new file mode 100644 index 00000000000..e28c959907d --- /dev/null +++ b/boards/acrn/acrn/Kconfig.acrn_ehl_crb @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACRN_EHL_CRB + select SOC_ATOM diff --git a/boards/acrn/acrn/Kconfig.defconfig b/boards/acrn/acrn/Kconfig.defconfig new file mode 100644 index 00000000000..678c8a5e378 --- /dev/null +++ b/boards/acrn/acrn/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2021-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config MP_MAX_NUM_CPUS + default 2 + +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 32768 + depends on ACPI diff --git a/boards/x86/acrn/acrn.dts b/boards/acrn/acrn/acrn.dts similarity index 95% rename from boards/x86/acrn/acrn.dts rename to boards/acrn/acrn/acrn.dts index ebf08b3f69b..dbd30373e34 100644 --- a/boards/x86/acrn/acrn.dts +++ b/boards/acrn/acrn/acrn.dts @@ -11,7 +11,7 @@ #define DT_DRAM_SIZE DT_SIZE_K(8192) #define DT_DRAM_BASE 0 -#include +#include / { model = "ACRN"; diff --git a/boards/x86/acrn/acrn.yaml b/boards/acrn/acrn/acrn.yaml similarity index 100% rename from boards/x86/acrn/acrn.yaml rename to boards/acrn/acrn/acrn.yaml diff --git a/boards/x86/acrn/acrn_defconfig b/boards/acrn/acrn/acrn_defconfig similarity index 88% rename from boards/x86/acrn/acrn_defconfig rename to boards/acrn/acrn/acrn_defconfig index 2f72c30dce8..0ec5c2b2564 100644 --- a/boards/x86/acrn/acrn_defconfig +++ b/boards/acrn/acrn/acrn_defconfig @@ -1,7 +1,7 @@ +# Copyright (c) 2019-2024 Intel Corporation +# # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_IA32=y -CONFIG_BOARD_ACRN=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_APIC_TSC_DEADLINE_TIMER=y diff --git a/boards/x86/acrn/acrn_ehl_crb.dts b/boards/acrn/acrn/acrn_ehl_crb.dts similarity index 100% rename from boards/x86/acrn/acrn_ehl_crb.dts rename to boards/acrn/acrn/acrn_ehl_crb.dts diff --git a/boards/x86/acrn/acrn_ehl_crb.yaml b/boards/acrn/acrn/acrn_ehl_crb.yaml similarity index 100% rename from boards/x86/acrn/acrn_ehl_crb.yaml rename to boards/acrn/acrn/acrn_ehl_crb.yaml diff --git a/boards/x86/acrn/acrn_ehl_crb_defconfig b/boards/acrn/acrn/acrn_ehl_crb_defconfig similarity index 90% rename from boards/x86/acrn/acrn_ehl_crb_defconfig rename to boards/acrn/acrn/acrn_ehl_crb_defconfig index 5e3af1f8be3..f7b256d2c84 100644 --- a/boards/x86/acrn/acrn_ehl_crb_defconfig +++ b/boards/acrn/acrn/acrn_ehl_crb_defconfig @@ -1,7 +1,7 @@ +# Copyright (c) 2019-2024 Intel Corporation +# # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_IA32=y -CONFIG_BOARD_ACRN=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_X2APIC=y diff --git a/boards/x86/acrn/board.cmake b/boards/acrn/acrn/board.cmake similarity index 100% rename from boards/x86/acrn/board.cmake rename to boards/acrn/acrn/board.cmake diff --git a/boards/acrn/acrn/board.yml b/boards/acrn/acrn/board.yml new file mode 100644 index 00000000000..4130a85b8f6 --- /dev/null +++ b/boards/acrn/acrn/board.yml @@ -0,0 +1,9 @@ +boards: + + - name: acrn + socs: + - name: atom + + - name: acrn_ehl_crb + socs: + - name: elkhart_lake diff --git a/boards/x86/acrn/board_acrn.c b/boards/acrn/acrn/board_acrn.c similarity index 100% rename from boards/x86/acrn/board_acrn.c rename to boards/acrn/acrn/board_acrn.c diff --git a/boards/x86/acrn/doc/ACRN-Hybrid.jpg b/boards/acrn/acrn/doc/ACRN-Hybrid.jpg similarity index 100% rename from boards/x86/acrn/doc/ACRN-Hybrid.jpg rename to boards/acrn/acrn/doc/ACRN-Hybrid.jpg diff --git a/boards/acrn/acrn/doc/index.rst b/boards/acrn/acrn/doc/index.rst new file mode 100644 index 00000000000..9251284106d --- /dev/null +++ b/boards/acrn/acrn/doc/index.rst @@ -0,0 +1,302 @@ +ACRN hypervisor +############### + +Zephyr's is capable of running as a guest under the x86 ACRN +hypervisor (see https://projectacrn.org/). The process for getting +this to work is somewhat involved, however. + +ACRN hypervisor supports a hybrid scenario where Zephyr runs in a so- +called "pre-launched" mode. This means Zephyr will access the ACRN +hypervisor directly without involving the SOS VM. This is the most +practical user scenario in the real world because Zephyr's real-time +and safety capability can be assured without influence from other +VMs. The following figure from ACRN's official documentation shows +how a hybrid scenario works: + +.. figure:: ACRN-Hybrid.jpg + :align: center + :alt: ACRN Hybrid User Scenario + :figclass: align-center + + ACRN Hybrid User Scenario + +In this tutorial, we will show you how to build a minimal running instance of Zephyr +and ACRN hypervisor to demonstrate that it works successfully. To learn more about +other features of ACRN, such as building and using the SOS VM or other guest VMs, +please refer to the Getting Started Guide for ACRN: +https://projectacrn.github.io/latest/tutorials/using_hybrid_mode_on_nuc.html + +Build your Zephyr App +********************* + +First, build the Zephyr application you want to run in ACRN as you +normally would, selecting an appropriate board: + + .. code-block:: console + + west build -b acrn_ehl_crb samples/hello_world + +In this tutorial, we will use the Intel Elkhart Lake Reference Board +(`EHL`_ CRB) since it is one of the suggested platforms for this +type of scenario. Use ``acrn_ehl_crb`` as the target board parameter. + +Note the kconfig output in ``build/zephyr/.config``, you will need to +reference that to configure ACRN later. + +The Zephyr build artifact you will need is ``build/zephyr/zephyr.bin``, +which is a raw memory image. Unlike other x86 targets, you do not +want to use ``zephyr.elf``! + +Configure and build ACRN +************************ + +First you need the source code, clone from: + + .. code-block:: console + + git clone https://github.com/projectacrn/acrn-hypervisor + +We suggest that you use versions v2.5.1 or later of the ACRN hypervisor +as they have better support for SMP in Zephyr. + +Like Zephyr, ACRN favors build-time configuration management instead +of runtime probing or control. Unlike Zephyr, ACRN has single large +configuration files instead of small easily-merged configuration +elements like kconfig defconfig files or devicetree includes. You +have to edit a big XML file to match your Zephyr configuration. +Choose an ACRN host config that matches your hardware ("ehl-crb-b" in +this case). Then find the relevant file in +``misc/config_tools/data//hybrid.xml``. + +First, find the list of ```` declarations. Each has an ``id=`` +attribute. For testing Zephyr, you will want to make sure that the +Zephyr image is ID zero. This allows you to launch ACRN with just one +VM image and avoids the need to needlessly copy large Linux blobs into +the boot filesystem. Under currently tested configurations, Zephyr +will always have a "vm_type" tag of "SAFETY_VM". + +Configure Zephyr Memory Layout +============================== + +Next, locate the load address of the Zephyr image and its entry point +address. These have to be configured manually in ACRN. Traditionally +Zephyr distributes itself as an ELF image where these addresses can be +automatically extracted, but ACRN does not know how to do that, it +only knows how to load a single contiguous region of data into memory +and jump to a specific address. + +Find the "..." tag that will look something like this: + + .. code-block:: xml + + + Zephyr + KERNEL_ZEPHYR + Zephyr_RawImage + + + 0x1000 + 0x1000 + + +The ``kern_load_addr`` tag must match the Zephyr LOCORE_BASE symbol +found in include/arch/x86/memory.ld. This is currently 0x1000 and +matches the default ACRN config. + +The ``kern_entry_addr`` tag must match the entry point in the built +``zephyr.elf`` file. You can find this with binutils, for example: + + .. code-block:: console + + $ objdump -f build/zephyr/zephyr.elf + + build/zephyr/zephyr.elf: file format elf64-x86-64 + architecture: i386:x86-64, flags 0x00000012: + EXEC_P, HAS_SYMS + start address 0x0000000000001000 + +By default this entry address is the same, at 0x1000. This has not +always been true of all configurations, however, and will likely +change in the future. + +Configure Zephyr CPUs +===================== + +Now you need to configure the CPU environment ACRN presents to the +guest. By default Zephyr builds in SMP mode, but ACRN's default +configuration gives it only one CPU. Find the value of +``CONFIG_MP_MAX_NUM_CPUS`` in the Zephyr .config file give the guest that +many CPUs in the ```` tag. For example: + + .. code-block:: xml + + + SAFETY_VM + ACRN PRE-LAUNCHED VM0 + + 0 + + + 0 + 1 + + ... + + 0 + 0 + + ... + + +To use SMP, we have to change the pcpu_id of VM0 to 0 and 1. +This configures ACRN to run Zephyr on CPU0 and CPU1. The ACRN hypervisor +and Zephyr application will not boot successfully without this change. +If you plan to run Zephyr with one CPU only, you can skip it. + +Since Zephyr is using CPU0 and CPU1, we also have to change +VM1's configuration so it runs on CPU2 and CPU3. If your ACRN setup has +additional VMs, you should change their configurations as well. + + .. code-block:: xml + + + SOS_VM + ACRN SOS VM + + 0 + + + 2 + 3 + + + 0 + 0 + + ... + + +Note that these indexes are physical CPUs on the host. When +configuring multiple guests, you probably don't want to overlap these +assignments with other guests. But for testing Zephyr simply using +CPUs 0 and 1 works fine. (Note that ehl-crb-b has four physical CPUs, +so configuring all of 0-3 will work fine too, but leave no space for +other guests to have dedicated CPUs). + +Build ACRN +========== + +Once configuration is complete, ACRN builds fairly cleanly: + + .. code-block:: console + + $ make -j BOARD=ehl-crb-b SCENARIO=hybrid + +The only build artifact you need is the ACRN multiboot image in +``build/hypervisor/acrn.bin`` + +Assemble EFI Boot Media +*********************** + +ACRN will boot on the hardware via the GNU GRUB bootloader, which is +itself launched from the EFI firmware. These need to be configured +correctly. + +Locate GRUB +=========== + +First, you will need a GRUB EFI binary that corresponds to your +hardware. In many cases, a simple upstream build from source or a +copy from a friendly Linux distribution will work. In some cases it +will not, however, and GRUB will need to be specially patched for +specific hardware. Contact your hardware support team (pause for +laughter) for clear instructions for how to build a working GRUB. In +practice you may just need to ask around and copy a binary from the +last test that worked for someone. + +Create EFI Boot Filesystem +========================== + +Now attach your boot media (e.g. a USB stick on /dev/sdb, your +hardware may differ!) to a Linux system and create an EFI boot +partition (type code 0xEF) large enough to store your boot artifacts. +This command feeds the relevant commands to fdisk directly, but you +can type them yourself if you like: + + .. code-block:: console + + # for i in n p 1 "" "" t ef w; do echo $i; done | fdisk /dev/sdb + ... + + +Now create a FAT filesystem in the new partition and mount it: + + .. code-block:: console + + # mkfs.vfat -n ACRN_ZEPHYR /dev/sdb1 + # mkdir -p /mnt/acrn + # mount /dev/sdb1 /mnt/acrn + +Copy Images and Configure GRUB +============================== + +ACRN does not have access to a runtime filesystem of its own. It +receives its guest VMs (i.e. zephyr.bin) as GRUB "multiboot" modules. +This means that we must rely on GRUB's filesystem driver. The three +files (GRUB, ACRN and Zephyr) all need to be copied into the +"/efi/boot" directory of the boot media. Note that GRUB must be named +"bootx64.efi" for the firmware to recognize it as the bootloader: + + .. code-block:: console + + # mkdir -p /mnt/acrn/efi/boot + # cp $PATH_TO_GRUB_BINARY /mnt/acrn/efi/boot/bootx64.efi + # cp $ZEPHYR_BASE/build/zephyr/zephyr.bin /mnt/acrn/efi/boot/ + # cp $PATH_TO_ACRN/build/hypervisor/acrn.bin /mnt/acrn/efi/boot/ + +At boot, GRUB will load a "efi/boot/grub.cfg" file for its runtime +configuration instructions (a feature, ironically, that both ACRN and +Zephyr lack!). This needs to load acrn.bin as the boot target and +pass it the zephyr.bin file as its first module (because Zephyr was +configured as ```` above). This minimal configuration will +work fine for all but the weirdest hardware (i.e. "hd0" is virtually +always the boot filesystem from which grub loaded), no need to fiddle +with GRUB plugins or menus or timeouts: + + .. code-block:: console + + # cat > /mnt/acrn/efi/boot/grub.cfg<vm_console 0 + + ----- Entering VM 0 Shell ----- + *** Booting Zephyr OS build v2.6.0-rc1-324-g1a03783861ad *** + Hello World! acrn + + +.. _EHL: https://www.intel.com/content/www/us/en/products/docs/processors/embedded/enhanced-for-iot-platform-brief.html diff --git a/boards/acrn/index.rst b/boards/acrn/index.rst new file mode 100644 index 00000000000..608717081c8 --- /dev/null +++ b/boards/acrn/index.rst @@ -0,0 +1,10 @@ +.. _boards-acrn: + +Project ACRN +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/actinius/icarus/CMakeLists.txt b/boards/actinius/icarus/CMakeLists.txt new file mode 100644 index 00000000000..9a434a4d73d --- /dev/null +++ b/boards/actinius/icarus/CMakeLists.txt @@ -0,0 +1,6 @@ +# +# Copyright (c) 2019-2022 Actinius +# +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/actinius/icarus/Kconfig.actinius_icarus b/boards/actinius/icarus/Kconfig.actinius_icarus new file mode 100644 index 00000000000..4c7d234bb63 --- /dev/null +++ b/boards/actinius/icarus/Kconfig.actinius_icarus @@ -0,0 +1,7 @@ +# Actinius Icarus board configuration + +# Copyright (c) 2019 Actinius +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACTINIUS_ICARUS + select SOC_NRF9160_SICA diff --git a/boards/actinius/icarus/Kconfig.defconfig b/boards/actinius/icarus/Kconfig.defconfig new file mode 100644 index 00000000000..80f8e6cab5d --- /dev/null +++ b/boards/actinius/icarus/Kconfig.defconfig @@ -0,0 +1,37 @@ +# Actinius Icarus board configuration + +# Copyright (c) 2019 Actinius +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ACTINIUS_ICARUS + +source "boards/common/actinius/Kconfig" + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_ACTINIUS_ICARUS_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_ACTINIUS_ICARUS_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_ACTINIUS_ICARUS_NRF9160_NS + +endif # BOARD_ACTINIUS_ICARUS diff --git a/boards/arm/actinius_icarus/actinius_icarus_common-pinctrl.dtsi b/boards/actinius/icarus/actinius_icarus_common-pinctrl.dtsi similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_common-pinctrl.dtsi rename to boards/actinius/icarus/actinius_icarus_common-pinctrl.dtsi diff --git a/boards/arm/actinius_icarus/actinius_icarus_common.dtsi b/boards/actinius/icarus/actinius_icarus_common.dtsi similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_common.dtsi rename to boards/actinius/icarus/actinius_icarus_common.dtsi diff --git a/boards/arm/actinius_icarus/actinius_icarus_common_1_4_0.dtsi b/boards/actinius/icarus/actinius_icarus_common_1_4_0.dtsi similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_common_1_4_0.dtsi rename to boards/actinius/icarus/actinius_icarus_common_1_4_0.dtsi diff --git a/boards/arm/actinius_icarus/actinius_icarus_common_2_0_0.dtsi b/boards/actinius/icarus/actinius_icarus_common_2_0_0.dtsi similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_common_2_0_0.dtsi rename to boards/actinius/icarus/actinius_icarus_common_2_0_0.dtsi diff --git a/boards/actinius/icarus/actinius_icarus_defconfig b/boards/actinius/icarus/actinius_icarus_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus/actinius_icarus.dts b/boards/actinius/icarus/actinius_icarus_nrf9160.dts similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus.dts rename to boards/actinius/icarus/actinius_icarus_nrf9160.dts diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.overlay b/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.overlay new file mode 100644 index 00000000000..69d500b69fa --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Actinius + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "actinius_icarus_common_1_4_0.dtsi" diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.yaml new file mode 100644 index 00000000000..1f3d3d9e0c0 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.yaml @@ -0,0 +1,23 @@ +identifier: actinius_icarus@1.4.0/nrf9160 +name: Actinius Icarus +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 256 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - feather_serial + - feather_i2c + - feather_spi + - arduino_i2c + - arduino_spi +vendor: actinius diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.overlay b/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.overlay new file mode 100644 index 00000000000..68c064cb1b5 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Actinius + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "actinius_icarus_common_2_0_0.dtsi" diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.yaml new file mode 100644 index 00000000000..d8bce888556 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.yaml @@ -0,0 +1,23 @@ +identifier: actinius_icarus@2.0.0/nrf9160 +name: Actinius Icarus +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 256 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - feather_serial + - feather_i2c + - feather_spi + - arduino_i2c + - arduino_spi +vendor: actinius diff --git a/boards/arm/actinius_icarus/actinius_icarus_ns.dts b/boards/actinius/icarus/actinius_icarus_nrf9160_ns.dts similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_ns.dts rename to boards/actinius/icarus/actinius_icarus_nrf9160_ns.dts diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.overlay b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.overlay new file mode 100644 index 00000000000..69d500b69fa --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Actinius + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "actinius_icarus_common_1_4_0.dtsi" diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.yaml new file mode 100644 index 00000000000..46005a7da10 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.yaml @@ -0,0 +1,23 @@ +identifier: actinius_icarus@1.4.0/nrf9160/ns +name: Actinius Icarus Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - feather_serial + - feather_i2c + - feather_spi + - arduino_i2c + - arduino_spi +vendor: actinius diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.overlay b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.overlay new file mode 100644 index 00000000000..68c064cb1b5 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Actinius + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "actinius_icarus_common_2_0_0.dtsi" diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.yaml new file mode 100644 index 00000000000..e8d9256f3f0 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.yaml @@ -0,0 +1,23 @@ +identifier: actinius_icarus@2.0.0/nrf9160/ns +name: Actinius Icarus Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - feather_serial + - feather_i2c + - feather_spi + - arduino_i2c + - arduino_spi +vendor: actinius diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_defconfig b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_defconfig new file mode 100644 index 00000000000..4baa62c55ef --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/actinius_icarus/actinius_icarus_partition_conf.dtsi b/boards/actinius/icarus/actinius_icarus_partition_conf.dtsi similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_partition_conf.dtsi rename to boards/actinius/icarus/actinius_icarus_partition_conf.dtsi diff --git a/boards/arm/actinius_icarus/board.cmake b/boards/actinius/icarus/board.cmake similarity index 100% rename from boards/arm/actinius_icarus/board.cmake rename to boards/actinius/icarus/board.cmake diff --git a/boards/actinius/icarus/board.yml b/boards/actinius/icarus/board.yml new file mode 100644 index 00000000000..69d6aa45707 --- /dev/null +++ b/boards/actinius/icarus/board.yml @@ -0,0 +1,13 @@ +board: + name: actinius_icarus + vendor: actinius + socs: + - name: nrf9160 + variants: + - name: 'ns' + revision: + format: major.minor.patch + default: "2.0.0" + revisions: + - name: "1.4.0" + - name: "2.0.0" diff --git a/boards/arm/actinius_icarus/doc/img/Icarus_front.jpg b/boards/actinius/icarus/doc/img/Icarus_front.jpg similarity index 100% rename from boards/arm/actinius_icarus/doc/img/Icarus_front.jpg rename to boards/actinius/icarus/doc/img/Icarus_front.jpg diff --git a/boards/arm/actinius_icarus/doc/img/Icarus_pinouts.jpg b/boards/actinius/icarus/doc/img/Icarus_pinouts.jpg similarity index 100% rename from boards/arm/actinius_icarus/doc/img/Icarus_pinouts.jpg rename to boards/actinius/icarus/doc/img/Icarus_pinouts.jpg diff --git a/boards/actinius/icarus/doc/index.rst b/boards/actinius/icarus/doc/index.rst new file mode 100644 index 00000000000..8092c53c8c9 --- /dev/null +++ b/boards/actinius/icarus/doc/index.rst @@ -0,0 +1,238 @@ +.. _actinius_icarus: + +Actinius Icarus +############### + +Overview +******** + +.. figure:: img/Icarus_front.jpg + :align: center + :alt: Icarus IoT Dev Board + + Icarus IoT Dev Board (nRF9160 Feather) + +The Icarus is a cost-effective cellular IoT board in Adafruit's Feather/FeatherWing +form factor. It is built around Nordic Semi's nRF9160 modem and combines +LTE-M, NB-IoT, GPS, accelerometer, USB, LiPo charger as well as +an eSIM and a nano SIM connector. + +The main uController is the Nordic Semiconductor nRF9160, with +ARM Cortex-M33F CPU, ARMv8-M Security Extension and the +following devices (provided directly by Nordic): + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +Hardware +******** + +The detailed information about the on-board hardware can be found at the `Icarus Product Website`_. + +.. figure:: img/Icarus_pinouts.jpg + :align: center + :alt: Icarus IoT Dev Board w/ Pinouts + + Icarus IoT Dev Board w/ Pinouts + +Pin description +=============== + +External Pins available to user: + ++------------+----------------------------+----------------------------------------------+------------------+ +| Icarus pin | Function | Description | Device-tree node | ++============+============================+==============================================+==================+ +| RST | Reset | Active low reset with internal pullup | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| 3.3V | Power output | Main 3.3 V supply | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| NC | - | Not connected | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| GND | Power output | Ground | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| 14 / A1 | GPIO / Analog in | nRF9160 P0.14 / AIN1 | gpio0 / adc_1 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 15 / A2 | GPIO / Analog in | nRF9160 P0.15 / AIN2 | gpio0 / adc_2 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 16 / A3 | GPIO / Analog in | nRF9160 P0.16 / AIN3 | gpio0 / adc_3 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 17 / A4 | GPIO / Analog in | nRF9160 P0.17 / AIN4 | gpio0 / adc_4 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 18 / A5 | GPIO / Analog in | nRF9160 P0.18 / AIN5 | gpio0 / adc_5 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 19 / A6 | GPIO / Analog in | nRF9160 P0.19 / AIN6 | gpio0 / adc_6 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 20 / SCK | GPIO / SPI pin | nRF9160 P0.20 / SPI SCK pin | gpio0 / spi3 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 21 / MOSI | GPIO / SPI pin | nRF9160 P0.21 / SPI MOSI pin | gpio0 / spi3 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 22 / MISO | GPIO / SPI pin | nRF9160 P0.22 / SPI MISO pin | gpio0 / spi3 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 23 / RX | GPIO / UART pin | nRF9160 P0.23 / UART RX pin | gpio0 / uart1 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 24 / TX | GPIO / UART pin | nRF9160 P0.24 / UART TX pin | gpio0 / uart1 | ++------------+----------------------------+----------------------------------------------+------------------+ +| VIN | Power input | Voltage input (maximum 10.2 V) | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| VBAT | Power input | Battery voltage input | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| EN | Power enable | Power enable pin (pull low to disable power) | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| USB | Power input | USB voltage input | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 4 | GPIO | nRF9160 P0.04 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 3 | GPIO | nRF9160 P0.03 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 2 | GPIO | nRF9160 P0.02 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 1 | GPIO | nRF9160 P0.01 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 0 | GPIO | nRF9160 P0.00 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 30 | GPIO | nRF9160 P0.30 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 31 | GPIO | nRF9160 P0.31 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| SCL | GPIO / I2C pin | nRF9160 P0.26 / I2C SCL pin | gpio0 / i2c2 | ++------------+----------------------------+----------------------------------------------+------------------+ +| SDA | GPIO / I2C pin | nRF9160 P0.27 / I2C SDA pin | gpio0 / i2c2 | ++------------+----------------------------+----------------------------------------------+------------------+ + +nRF9160 pins connected internally: + ++--------------+---------------------------------------+----------------------+ +| nRF9160 pin | Function | Device-tree node | ++==============+=======================================+======================+ +| P0.05 | User button | button0 | ++--------------+---------------------------------------+----------------------+ +| P0.10 | Red LED | led0 / pwm-led0 | ++--------------+---------------------------------------+----------------------+ +| P0.11 | Green LED | led1 / pwm-led1 | ++--------------+---------------------------------------+----------------------+ +| P0.12 | Blue LED | led2 / pwm-led2 | ++--------------+---------------------------------------+----------------------+ +| P0.28 | Accelerometer Interrupt 1 | lis2dh12-accel | ++--------------+---------------------------------------+----------------------+ +| P0.29 | Accelerometer Interrupt 2 | lis2dh12-accel | ++--------------+---------------------------------------+----------------------+ +| P0.08 | SIM select pin | gpio0 | ++--------------+---------------------------------------+----------------------+ +| P0.13 / AIN0 | Battery voltage measurement | adc_0 | ++--------------+---------------------------------------+----------------------+ +| P0.06 | USB - FTDI serial RX | uart0 | ++--------------+---------------------------------------+----------------------+ +| P0.09 | USB - FTDI serial TX | uart0 | ++--------------+---------------------------------------+----------------------+ +| P0.07 | USB - FTDI serial RTS | uart0 | +| | Charger enable pin (Icarus v2.0) | gpio0 (Icarus v2.0) | ++--------------+---------------------------------------+----------------------+ +| P0.25 | USB - FTDI serial CTS | uart0 | +| | FLASH memory SPI CS pin (Icarus v2.0) | gpio0 (Icarus v2.0) | ++--------------+---------------------------------------+----------------------+ + +Supported Features +================== + +The actinius_icarus board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| ACCEL | st | lis2dh | ++-----------+------------+----------------------+ + +SIM Selection +============= + +The SIM choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting +the ``sim`` property in the ``sim_select`` node. + +Charger Enable/Disable +====================== + +Since hardware version 2.0 the charger can be disabled by adjusting the ``charger`` +property of the ``charger_enable`` device tree node. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus/ns``. +3. Merge the two binaries together. + +If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and +burned automatically, unless you have disabled the feature. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +More information can be found in the `Icarus "Get Started" Guide`_ or the +`Actinius Documentation Portal`_. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau + +.. _Icarus Product Website: + https://www.actinius.com/icarus + +.. _Icarus "Get Started" Guide: + https://www.actinius.com/get-started + +.. _Actinius Documentation Portal: + https://docs.actinius.com diff --git a/boards/arm/actinius_icarus/dts/bindings/actinius-charger-enable.yaml b/boards/actinius/icarus/dts/bindings/actinius-charger-enable.yaml similarity index 100% rename from boards/arm/actinius_icarus/dts/bindings/actinius-charger-enable.yaml rename to boards/actinius/icarus/dts/bindings/actinius-charger-enable.yaml diff --git a/boards/arm/actinius_icarus/dts/bindings/actinius-sim-select.yaml b/boards/actinius/icarus/dts/bindings/actinius-sim-select.yaml similarity index 100% rename from boards/arm/actinius_icarus/dts/bindings/actinius-sim-select.yaml rename to boards/actinius/icarus/dts/bindings/actinius-sim-select.yaml diff --git a/boards/arm/actinius_icarus/feather_connector.dtsi b/boards/actinius/icarus/feather_connector.dtsi similarity index 100% rename from boards/arm/actinius_icarus/feather_connector.dtsi rename to boards/actinius/icarus/feather_connector.dtsi diff --git a/boards/arm/actinius_icarus/pre_dt_board.cmake b/boards/actinius/icarus/pre_dt_board.cmake similarity index 100% rename from boards/arm/actinius_icarus/pre_dt_board.cmake rename to boards/actinius/icarus/pre_dt_board.cmake diff --git a/boards/actinius/icarus_bee/CMakeLists.txt b/boards/actinius/icarus_bee/CMakeLists.txt new file mode 100644 index 00000000000..7ddd62dbb2d --- /dev/null +++ b/boards/actinius/icarus_bee/CMakeLists.txt @@ -0,0 +1,6 @@ +# +# Copyright (c) 2021-2022 Actinius +# +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/actinius/icarus_bee/Kconfig.actinius_icarus_bee b/boards/actinius/icarus_bee/Kconfig.actinius_icarus_bee new file mode 100644 index 00000000000..6eb4e431f12 --- /dev/null +++ b/boards/actinius/icarus_bee/Kconfig.actinius_icarus_bee @@ -0,0 +1,7 @@ +# Actinius Icarus Bee board configuration + +# Copyright (c) 2021 Actinius +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACTINIUS_ICARUS_BEE + select SOC_NRF9160_SICA diff --git a/boards/actinius/icarus_bee/Kconfig.defconfig b/boards/actinius/icarus_bee/Kconfig.defconfig new file mode 100644 index 00000000000..3eaf7f5f1c6 --- /dev/null +++ b/boards/actinius/icarus_bee/Kconfig.defconfig @@ -0,0 +1,37 @@ +# Actinius Icarus Bee board configuration + +# Copyright (c) 2021 Actinius +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ACTINIUS_ICARUS_BEE + +source "boards/common/actinius/Kconfig" + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_ACTINIUS_ICARUS_BEE_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_ACTINIUS_ICARUS_BEE_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_ACTINIUS_ICARUS_BEE_NRF9160_NS + +endif # BOARD_ACTINIUS_ICARUS_BEE diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_common-pinctrl.dtsi b/boards/actinius/icarus_bee/actinius_icarus_bee_common-pinctrl.dtsi similarity index 100% rename from boards/arm/actinius_icarus_bee/actinius_icarus_bee_common-pinctrl.dtsi rename to boards/actinius/icarus_bee/actinius_icarus_bee_common-pinctrl.dtsi diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_common.dtsi b/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi similarity index 100% rename from boards/arm/actinius_icarus_bee/actinius_icarus_bee_common.dtsi rename to boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_defconfig b/boards/actinius/icarus_bee/actinius_icarus_bee_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee.dts b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.dts similarity index 100% rename from boards/arm/actinius_icarus_bee/actinius_icarus_bee.dts rename to boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.dts diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.yaml b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.yaml new file mode 100644 index 00000000000..8fd851899ba --- /dev/null +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.yaml @@ -0,0 +1,18 @@ +identifier: actinius_icarus_bee/nrf9160 +name: Actinius Icarus Bee +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 256 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: actinius diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns.dts b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.dts similarity index 100% rename from boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns.dts rename to boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.dts diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.yaml b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.yaml new file mode 100644 index 00000000000..89b21ece170 --- /dev/null +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.yaml @@ -0,0 +1,18 @@ +identifier: actinius_icarus_bee/nrf9160/ns +name: Actinius Icarus Bee Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: actinius diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns_defconfig b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns_defconfig new file mode 100644 index 00000000000..4baa62c55ef --- /dev/null +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_partition_conf.dtsi b/boards/actinius/icarus_bee/actinius_icarus_bee_partition_conf.dtsi similarity index 100% rename from boards/arm/actinius_icarus_bee/actinius_icarus_bee_partition_conf.dtsi rename to boards/actinius/icarus_bee/actinius_icarus_bee_partition_conf.dtsi diff --git a/boards/arm/actinius_icarus_bee/board.cmake b/boards/actinius/icarus_bee/board.cmake similarity index 100% rename from boards/arm/actinius_icarus_bee/board.cmake rename to boards/actinius/icarus_bee/board.cmake diff --git a/boards/actinius/icarus_bee/board.yml b/boards/actinius/icarus_bee/board.yml new file mode 100644 index 00000000000..653294a9cf5 --- /dev/null +++ b/boards/actinius/icarus_bee/board.yml @@ -0,0 +1,7 @@ +board: + name: actinius_icarus_bee + vendor: actinius + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/actinius_icarus_bee/doc/img/icarus-bee-external-pins.jpg b/boards/actinius/icarus_bee/doc/img/icarus-bee-external-pins.jpg similarity index 100% rename from boards/arm/actinius_icarus_bee/doc/img/icarus-bee-external-pins.jpg rename to boards/actinius/icarus_bee/doc/img/icarus-bee-external-pins.jpg diff --git a/boards/arm/actinius_icarus_bee/doc/img/icarus-bee-peripherals-pins.jpg b/boards/actinius/icarus_bee/doc/img/icarus-bee-peripherals-pins.jpg similarity index 100% rename from boards/arm/actinius_icarus_bee/doc/img/icarus-bee-peripherals-pins.jpg rename to boards/actinius/icarus_bee/doc/img/icarus-bee-peripherals-pins.jpg diff --git a/boards/arm/actinius_icarus_bee/doc/img/icarus-bee.jpg b/boards/actinius/icarus_bee/doc/img/icarus-bee.jpg similarity index 100% rename from boards/arm/actinius_icarus_bee/doc/img/icarus-bee.jpg rename to boards/actinius/icarus_bee/doc/img/icarus-bee.jpg diff --git a/boards/actinius/icarus_bee/doc/index.rst b/boards/actinius/icarus_bee/doc/index.rst new file mode 100644 index 00000000000..630d0aa07c7 --- /dev/null +++ b/boards/actinius/icarus_bee/doc/index.rst @@ -0,0 +1,137 @@ +.. _actinius_icarus_bee: + +Actinius Icarus Bee +################### + +Overview +******** + +.. figure:: img/icarus-bee.jpg + :align: center + :alt: Icarus Bee + + Icarus Bee (nRF9160 Bee) + +The Icarus Bee is a cellular IoT board in Bee/xBee form factor. +It is built around Nordic Semi's nRF9160 modem and combines +LTE-M, NB-IoT, GPS, accelerometer, SPI Flash, RGB LED, Button, +as well as an eSIM and a nano SIM connector. + +The main uController is the Nordic Semiconductor nRF9160, with +ARM Cortex-M33F CPU, ARMv8-M Security Extension and the +following devices (provided directly by Nordic): + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +.. figure:: img/icarus-bee-external-pins.jpg + :align: center + :alt: Icarus Bee w/ Pinouts + + Icarus Bee w/ Pinouts + +.. figure:: img/icarus-bee-peripherals-pins.jpg + :align: center + :alt: Icarus Bee + + Internal Pinouts + +Hardware +******** + +The detailed information about the on-board hardware can be found at the `Icarus Bee Product Website`_. + +Supported Features +================== + +The actinius_icarus_bee board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| ACCEL | st | lis2dh | ++-----------+------------+----------------------+ + +SIM selection +************* + +The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting +the ``sim`` property in the ``sim_select`` node. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_bee``. +2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_bee/ns``. +3. Merge the two binaries together. + +If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and +burned automatically, unless you have disabled the feature. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +More information can be found in the `Icarus Bee Product Website`_ or the +`Actinius Documentation Portal`_. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau + +.. _Icarus Bee Product Website: + https://www.actinius.com/icarus-bee + +.. _Actinius Documentation Portal: + https://docs.actinius.com diff --git a/boards/arm/actinius_icarus_bee/dts/bindings/actinius-sim-select.yaml b/boards/actinius/icarus_bee/dts/bindings/actinius-sim-select.yaml similarity index 100% rename from boards/arm/actinius_icarus_bee/dts/bindings/actinius-sim-select.yaml rename to boards/actinius/icarus_bee/dts/bindings/actinius-sim-select.yaml diff --git a/boards/arm/actinius_icarus_bee/pre_dt_board.cmake b/boards/actinius/icarus_bee/pre_dt_board.cmake similarity index 100% rename from boards/arm/actinius_icarus_bee/pre_dt_board.cmake rename to boards/actinius/icarus_bee/pre_dt_board.cmake diff --git a/boards/actinius/icarus_som/CMakeLists.txt b/boards/actinius/icarus_som/CMakeLists.txt new file mode 100644 index 00000000000..7ddd62dbb2d --- /dev/null +++ b/boards/actinius/icarus_som/CMakeLists.txt @@ -0,0 +1,6 @@ +# +# Copyright (c) 2021-2022 Actinius +# +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/actinius/icarus_som/Kconfig.actinius_icarus_som b/boards/actinius/icarus_som/Kconfig.actinius_icarus_som new file mode 100644 index 00000000000..a82ff7216b3 --- /dev/null +++ b/boards/actinius/icarus_som/Kconfig.actinius_icarus_som @@ -0,0 +1,7 @@ +# Actinius Icarus SoM board configuration + +# Copyright (c) 2021 Actinius +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACTINIUS_ICARUS_SOM + select SOC_NRF9160_SICA diff --git a/boards/actinius/icarus_som/Kconfig.defconfig b/boards/actinius/icarus_som/Kconfig.defconfig new file mode 100644 index 00000000000..43730eb6945 --- /dev/null +++ b/boards/actinius/icarus_som/Kconfig.defconfig @@ -0,0 +1,37 @@ +# Actinius Icarus SoM board configuration + +# Copyright (c) 2021 Actinius +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ACTINIUS_ICARUS_SOM + +source "boards/common/actinius/Kconfig" + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_ACTINIUS_ICARUS_SOM_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_ACTINIUS_ICARUS_SOM_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_ACTINIUS_ICARUS_SOM_NRF9160_NS + +endif # BOARD_ACTINIUS_ICARUS_SOM diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_common-pinctrl.dtsi b/boards/actinius/icarus_som/actinius_icarus_som_common-pinctrl.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som/actinius_icarus_som_common-pinctrl.dtsi rename to boards/actinius/icarus_som/actinius_icarus_som_common-pinctrl.dtsi diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_common.dtsi b/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som/actinius_icarus_som_common.dtsi rename to boards/actinius/icarus_som/actinius_icarus_som_common.dtsi diff --git a/boards/actinius/icarus_som/actinius_icarus_som_defconfig b/boards/actinius/icarus_som/actinius_icarus_som_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/actinius/icarus_som/actinius_icarus_som_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som.dts b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.dts similarity index 100% rename from boards/arm/actinius_icarus_som/actinius_icarus_som.dts rename to boards/actinius/icarus_som/actinius_icarus_som_nrf9160.dts diff --git a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.yaml b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.yaml new file mode 100644 index 00000000000..1eab5025340 --- /dev/null +++ b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.yaml @@ -0,0 +1,17 @@ +identifier: actinius_icarus_som/nrf9160 +name: Actinius Icarus SoM +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 256 +supported: + - gpio + - i2c + - pwm + - watchdog + - counter +vendor: actinius diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_ns.dts b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.dts similarity index 100% rename from boards/arm/actinius_icarus_som/actinius_icarus_som_ns.dts rename to boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.dts diff --git a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.yaml b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.yaml new file mode 100644 index 00000000000..0a6968beec2 --- /dev/null +++ b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.yaml @@ -0,0 +1,17 @@ +identifier: actinius_icarus_som/nrf9160/ns +name: Actinius Icarus SoM Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - gpio + - i2c + - pwm + - watchdog + - counter +vendor: actinius diff --git a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns_defconfig b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns_defconfig new file mode 100644 index 00000000000..4baa62c55ef --- /dev/null +++ b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_partition_conf.dtsi b/boards/actinius/icarus_som/actinius_icarus_som_partition_conf.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som/actinius_icarus_som_partition_conf.dtsi rename to boards/actinius/icarus_som/actinius_icarus_som_partition_conf.dtsi diff --git a/boards/arm/actinius_icarus_som/board.cmake b/boards/actinius/icarus_som/board.cmake similarity index 100% rename from boards/arm/actinius_icarus_som/board.cmake rename to boards/actinius/icarus_som/board.cmake diff --git a/boards/actinius/icarus_som/board.yml b/boards/actinius/icarus_som/board.yml new file mode 100644 index 00000000000..9acf3b4fa5e --- /dev/null +++ b/boards/actinius/icarus_som/board.yml @@ -0,0 +1,7 @@ +board: + name: actinius_icarus_som + vendor: actinius + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/actinius_icarus_som/doc/img/icarus-som-external-pins.jpg b/boards/actinius/icarus_som/doc/img/icarus-som-external-pins.jpg similarity index 100% rename from boards/arm/actinius_icarus_som/doc/img/icarus-som-external-pins.jpg rename to boards/actinius/icarus_som/doc/img/icarus-som-external-pins.jpg diff --git a/boards/arm/actinius_icarus_som/doc/img/icarus-som-peripherals-pins.jpg b/boards/actinius/icarus_som/doc/img/icarus-som-peripherals-pins.jpg similarity index 100% rename from boards/arm/actinius_icarus_som/doc/img/icarus-som-peripherals-pins.jpg rename to boards/actinius/icarus_som/doc/img/icarus-som-peripherals-pins.jpg diff --git a/boards/arm/actinius_icarus_som/doc/img/icarus-som.jpg b/boards/actinius/icarus_som/doc/img/icarus-som.jpg similarity index 100% rename from boards/arm/actinius_icarus_som/doc/img/icarus-som.jpg rename to boards/actinius/icarus_som/doc/img/icarus-som.jpg diff --git a/boards/actinius/icarus_som/doc/index.rst b/boards/actinius/icarus_som/doc/index.rst new file mode 100644 index 00000000000..f3206e63fe3 --- /dev/null +++ b/boards/actinius/icarus_som/doc/index.rst @@ -0,0 +1,137 @@ +.. _actinius_icarus_som: + +Actinius Icarus SoM +################### + +Overview +******** + +.. figure:: img/icarus-som.jpg + :align: center + :alt: Icarus SoM + + Icarus SoM (nRF9160) + +The Icarus SoM is a coin-sized, easy-to-solder cellular IoT Module +built around Nordic Semi's nRF9160 modem and combines +LTE-M, NB-IoT, GPS, accelerometer as well as an eSIM and option for +an external nano SIM connector. + +The main uController is the Nordic Semiconductor nRF9160, with +ARM Cortex-M33F CPU, ARMv8-M Security Extension and the +following devices (provided directly by Nordic): + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +.. figure:: img/icarus-som-external-pins.jpg + :align: center + :alt: Icarus SoM Pins + + Icarus SoM Pins + +.. figure:: img/icarus-som-peripherals-pins.jpg + :align: center + :alt: Icarus SoM + + Internal Pinouts + +Hardware +******** + +The detailed information about the on-board hardware can be found at the `Icarus SoM Product Website`_. + +Supported Features +================== + +The actinius_icarus_som board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| ACCEL | st | lis2dh | ++-----------+------------+----------------------+ + +SIM selection +************* + +The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting +the ``sim`` property in the ``sim_select`` node. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_som``. +2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_som/ns``. +3. Merge the two binaries together. + +If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and +burned automatically, unless you have disabled the feature. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +More information can be found in the `Icarus SoM Product Website`_ or the +`Actinius Documentation Portal`_. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau + +.. _Icarus SoM Product Website: + https://www.actinius.com/icarus-som + +.. _Actinius Documentation Portal: + https://docs.actinius.com diff --git a/boards/arm/actinius_icarus_som/dts/bindings/actinius-sim-select.yaml b/boards/actinius/icarus_som/dts/bindings/actinius-sim-select.yaml similarity index 100% rename from boards/arm/actinius_icarus_som/dts/bindings/actinius-sim-select.yaml rename to boards/actinius/icarus_som/dts/bindings/actinius-sim-select.yaml diff --git a/boards/arm/actinius_icarus_som/pre_dt_board.cmake b/boards/actinius/icarus_som/pre_dt_board.cmake similarity index 100% rename from boards/arm/actinius_icarus_som/pre_dt_board.cmake rename to boards/actinius/icarus_som/pre_dt_board.cmake diff --git a/boards/actinius/icarus_som_dk/CMakeLists.txt b/boards/actinius/icarus_som_dk/CMakeLists.txt new file mode 100644 index 00000000000..4e57b25bdf1 --- /dev/null +++ b/boards/actinius/icarus_som_dk/CMakeLists.txt @@ -0,0 +1,6 @@ +# +# Copyright (c) 2022 Actinius +# +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/actinius/icarus_som_dk/Kconfig.actinius_icarus_som_dk b/boards/actinius/icarus_som_dk/Kconfig.actinius_icarus_som_dk new file mode 100644 index 00000000000..4c4966e9839 --- /dev/null +++ b/boards/actinius/icarus_som_dk/Kconfig.actinius_icarus_som_dk @@ -0,0 +1,7 @@ +# Actinius Icarus SoM DK board configuration + +# Copyright (c) 2022 Actinius +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACTINIUS_ICARUS_SOM_DK + select SOC_NRF9160_SICA diff --git a/boards/actinius/icarus_som_dk/Kconfig.defconfig b/boards/actinius/icarus_som_dk/Kconfig.defconfig new file mode 100644 index 00000000000..62e848d3468 --- /dev/null +++ b/boards/actinius/icarus_som_dk/Kconfig.defconfig @@ -0,0 +1,37 @@ +# Actinius Icarus SoM DK board configuration + +# Copyright (c) 2022 Actinius +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ACTINIUS_ICARUS_SOM_DK + +source "boards/common/actinius/Kconfig" + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_ACTINIUS_ICARUS_SOM_DK_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_ACTINIUS_ICARUS_SOM_DK_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_ACTINIUS_ICARUS_SOM_DK_NRF9160_NS + +endif # BOARD_ACTINIUS_ICARUS_SOM_DK diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi rename to boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_common.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_common.dtsi rename to boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_defconfig b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk.dts b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.dts similarity index 100% rename from boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk.dts rename to boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.dts diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.yaml b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.yaml new file mode 100644 index 00000000000..3b7d7377caa --- /dev/null +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.yaml @@ -0,0 +1,22 @@ +identifier: actinius_icarus_som_dk/nrf9160 +name: Actinius Icarus SoM DK +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 256 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi +vendor: actinius diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns.dts b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.dts similarity index 100% rename from boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns.dts rename to boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.dts diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.yaml b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.yaml new file mode 100644 index 00000000000..b41972384ba --- /dev/null +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.yaml @@ -0,0 +1,22 @@ +identifier: actinius_icarus_som_dk/nrf9160/ns +name: Actinius Icarus SoM DK Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi +vendor: actinius diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns_defconfig b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns_defconfig new file mode 100644 index 00000000000..4baa62c55ef --- /dev/null +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_partition_conf.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_partition_conf.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_partition_conf.dtsi rename to boards/actinius/icarus_som_dk/actinius_icarus_som_dk_partition_conf.dtsi diff --git a/boards/arm/actinius_icarus_som_dk/arduino_connector.dtsi b/boards/actinius/icarus_som_dk/arduino_connector.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som_dk/arduino_connector.dtsi rename to boards/actinius/icarus_som_dk/arduino_connector.dtsi diff --git a/boards/arm/actinius_icarus_som_dk/board.cmake b/boards/actinius/icarus_som_dk/board.cmake similarity index 100% rename from boards/arm/actinius_icarus_som_dk/board.cmake rename to boards/actinius/icarus_som_dk/board.cmake diff --git a/boards/actinius/icarus_som_dk/board.yml b/boards/actinius/icarus_som_dk/board.yml new file mode 100644 index 00000000000..137f39705d1 --- /dev/null +++ b/boards/actinius/icarus_som_dk/board.yml @@ -0,0 +1,7 @@ +board: + name: actinius_icarus_som_dk + vendor: actinius + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/actinius_icarus_som_dk/doc/img/icarus-som-dk-block-diagram.jpg b/boards/actinius/icarus_som_dk/doc/img/icarus-som-dk-block-diagram.jpg similarity index 100% rename from boards/arm/actinius_icarus_som_dk/doc/img/icarus-som-dk-block-diagram.jpg rename to boards/actinius/icarus_som_dk/doc/img/icarus-som-dk-block-diagram.jpg diff --git a/boards/arm/actinius_icarus_som_dk/doc/img/icarus-som-dk.jpg b/boards/actinius/icarus_som_dk/doc/img/icarus-som-dk.jpg similarity index 100% rename from boards/arm/actinius_icarus_som_dk/doc/img/icarus-som-dk.jpg rename to boards/actinius/icarus_som_dk/doc/img/icarus-som-dk.jpg diff --git a/boards/actinius/icarus_som_dk/doc/index.rst b/boards/actinius/icarus_som_dk/doc/index.rst new file mode 100644 index 00000000000..c0d0a940339 --- /dev/null +++ b/boards/actinius/icarus_som_dk/doc/index.rst @@ -0,0 +1,245 @@ +.. _actinius_icarus_som_dk: + +Actinius Icarus SoM DK +###################### + +Overview +******** + +.. figure:: img/icarus-som-dk.jpg + :width: 450px + :align: center + :alt: Icarus SoM DK + + Icarus SoM Development Kit (nRF9160) + +The Icarus SoM DK is a single board development kit for +evaluation and development on the Icarus SoM (`Icarus SoM Docs`_). +The Icarus SoM features the nRF9160 SiP from Nordic Semiconductor, +a low-power 3-axis accelerometer and an on-board eSIM. +The development kit provides interfacing to the SoM through USB-C, +a set of user LEDs, a reset and a user button, a battery charging port, +and a external nano SIM connector. +The board is also Arduino Uno Rev3 compatible which makes +using external shields possible. + +The main uController is the Nordic Semiconductor nRF9160, with +ARM Cortex-M33F CPU, ARMv8-M Security Extension and the +following devices (provided directly by Nordic): + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +.. figure:: img/icarus-som-dk-block-diagram.jpg + :width: 450px + :align: center + :alt: Icarus SoM DK Block Diagram + + Icarus SoM DK Block Diagram + +Hardware +******** + +The detailed information about the on-board hardware can be found at the `Icarus SoM Product Website`_ +and the `Icarus SoM DK Product Website`_. + +Pin description +=============== + +External Pins available to user: + ++----+-------+------------------------------------+------------------+ +| # | Label | Description | Device-tree node | ++====+=======+====================================+==================+ +| 1 | NC | Not Connected | - | ++----+-------+------------------------------------+------------------+ +| 2 | IOREF | I/O reference, connected to 3.3V | - | ++----+-------+------------------------------------+------------------+ +| 3 | RST | Reset of the nRF9160 | - | ++----+-------+------------------------------------+------------------+ +| 4 | 3.3V | 3.3V Power output | - | ++----+-------+------------------------------------+------------------+ +| 5 | 4.4V | Power output between Vbat and 4.4V | - | ++----+-------+------------------------------------+------------------+ +| 6 | GND | Ground pin | - | ++----+-------+------------------------------------+------------------+ +| 7 | GND | Ground pin | - | ++----+-------+------------------------------------+------------------+ +| 8 | VIN | Power input pin (4.35V to 10.5V) | - | ++----+-------+------------------------------------+------------------+ +| 9 | A2 | AIN2 / nRF9160 P0.15 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 10 | A3 | AIN3 / nRF9160 P0.16 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 11 | A4 | AIN4 / nRF9160 P0.17 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 12 | A5 | AIN5 / nRF9160 P0.18 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 13 | A6 | AIN6 / nRF9160 P0.19 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 14 | A7 | AIN7 / nRF9160 P0.20 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 15 | P4 | nRF9160 P0.04 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 16 | P5 | nRF9160 P0.05 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 17 | P2 | nRF9160 P0.02 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 18 | P1 | nRF9160 P0.01 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 19 | P23 | nRF9160 P0.23 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 20 | P0 | nRF9160 P0.00 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 21 | P26 | nRF9160 P0.26 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 22 | P27 | nRF9160 P0.27 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 23 | P30 | nRF9160 P0.30 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 24 | P31 | nRF9160 P0.31 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 25 | P7 | nRF9160 P0.07 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 26 | P13 | nRF9160 P0.13 or NC (Jumper-dependent) | gpio0 | ++----+-------+------------------------------------+------------------+ +| 27 | P14 | nRF9160 P0.14 or NC (Jumper-dependent) | gpio0 | ++----+-------+------------------------------------+------------------+ +| 28 | P3 | nRF9160 P0.03 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 29 | GND | Ground pin | - | ++----+-------+------------------------------------+------------------+ +| 30 | AREF | NC or AIN1 (Jumper-dependent) | gpio0 | ++----+-------+------------------------------------+------------------+ +| 31 | SDA | I2C SDA pin | i2c2 | ++----+-------+------------------------------------+------------------+ +| 32 | SCL | I2C SCL pin | i2c2 | ++----+-------+------------------------------------+------------------+ +| - | TS | Pin for optional battery thermistor| - | ++----+-------+------------------------------------+------------------+ +| - | CHG | Pin for battery charging indication| - | ++----+-------+------------------------------------+------------------+ +| - | CE | Pin for enabling/disabling charging| - | ++----+-------+------------------------------------+------------------+ + + +nRF9160 pins connected internally: + ++--------------+------------------------------+---------------------+ +| nRF9160 pin | Function | Device-tree node | ++==============+==============================+=====================+ +| P0.03 | Blue LED | led0 / pwm-led0 | ++--------------+------------------------------+---------------------+ +| P0.08 | NeoPixel RGB LED | spi1 | ++--------------+------------------------------+---------------------+ +| P0.12 | SIM select pin | gpio0 | ++--------------+------------------------------+---------------------+ +| P0.23 | Connected to the user button | gpio0 / button0 | ++--------------+------------------------------+---------------------+ +| P0.24 | SPI NOR Flash chip select | gpio0 / spi3 | ++--------------+------------------------------+---------------------+ +| P0.28 | Accelerometer Interrupt 2 | lis2dh12-accel | ++--------------+------------------------------+---------------------+ +| P0.29 | Accelerometer Interrupt 1 | lis2dh12-accel | ++--------------+------------------------------+---------------------+ + +Supported Features +================== + +The actinius_icarus_som_dk board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| ACCEL | st | lis2dh | ++-----------+------------+----------------------+ + +SIM selection +************* + +The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting +the ``sim`` property in the ``sim_select`` node. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_som_dk``. +2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_som_dk/ns``. +3. Merge the two binaries together. + +If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and +burned automatically, unless you have disabled the feature. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +More information can be found in the `Icarus SoM Product Website`_, +the `Icarus SoM DK Product Website`_ or the `Actinius Documentation Portal`_. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau + +.. _Icarus SoM Product Website: + https://www.actinius.com/icarus-som + +.. _Icarus SoM DK Product Website: + https://www.actinius.com/icarus-som-dk + +.. _Icarus SoM Docs: + https://docs.actinius.com/icarus-som/introduction + +.. _Actinius Documentation Portal: + https://docs.actinius.com diff --git a/boards/arm/actinius_icarus_som_dk/dts/bindings/actinius-sim-select.yaml b/boards/actinius/icarus_som_dk/dts/bindings/actinius-sim-select.yaml similarity index 100% rename from boards/arm/actinius_icarus_som_dk/dts/bindings/actinius-sim-select.yaml rename to boards/actinius/icarus_som_dk/dts/bindings/actinius-sim-select.yaml diff --git a/boards/arm/actinius_icarus_som_dk/pre_dt_board.cmake b/boards/actinius/icarus_som_dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/actinius_icarus_som_dk/pre_dt_board.cmake rename to boards/actinius/icarus_som_dk/pre_dt_board.cmake diff --git a/boards/actinius/index.rst b/boards/actinius/index.rst new file mode 100644 index 00000000000..045387a0c50 --- /dev/null +++ b/boards/actinius/index.rst @@ -0,0 +1,10 @@ +.. _boards-actinius: + +Actinius +######## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/adafruit/feather/Kconfig b/boards/adafruit/feather/Kconfig new file mode 100644 index 00000000000..e266540aa87 --- /dev/null +++ b/boards/adafruit/feather/Kconfig @@ -0,0 +1,10 @@ +# Adafruit Feather nRF52840 Express board configuration + +# Copyright (c) 2020 Tobias Svehagen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_ADAFRUIT_FEATHER diff --git a/boards/adafruit/feather/Kconfig.adafruit_feather b/boards/adafruit/feather/Kconfig.adafruit_feather new file mode 100644 index 00000000000..ed952670ce1 --- /dev/null +++ b/boards/adafruit/feather/Kconfig.adafruit_feather @@ -0,0 +1,7 @@ +# Adafruit Feather nRF52840 Express board configuration + +# Copyright (c) 2020 Tobias Svehagen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER + select SOC_NRF52840_QIAA diff --git a/boards/adafruit/feather/Kconfig.defconfig b/boards/adafruit/feather/Kconfig.defconfig new file mode 100644 index 00000000000..3ae6f23be55 --- /dev/null +++ b/boards/adafruit/feather/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Adafruit Feather nRF52840 Express board configuration + +# Copyright (c) 2020 Tobias Svehagen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_FEATHER + +config BT_CTLR + default BT + +endif # BOARD_ADAFRUIT_FEATHER diff --git a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840-pinctrl.dtsi b/boards/adafruit/feather/adafruit_feather_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840-pinctrl.dtsi rename to boards/adafruit/feather/adafruit_feather_nrf52840-pinctrl.dtsi diff --git a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.dts b/boards/adafruit/feather/adafruit_feather_nrf52840.dts similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.dts rename to boards/adafruit/feather/adafruit_feather_nrf52840.dts diff --git a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.yaml b/boards/adafruit/feather/adafruit_feather_nrf52840.yaml similarity index 86% rename from boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.yaml rename to boards/adafruit/feather/adafruit_feather_nrf52840.yaml index f626fd46a4a..487c78377a1 100644 --- a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.yaml +++ b/boards/adafruit/feather/adafruit_feather_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: adafruit_feather_nrf52840 +identifier: adafruit_feather/nrf52840 name: Adafruit Feather nRF52840 Express type: mcu arch: arm diff --git a/boards/adafruit/feather/adafruit_feather_nrf52840_defconfig b/boards/adafruit/feather/adafruit_feather_nrf52840_defconfig new file mode 100644 index 00000000000..7167aca850a --- /dev/null +++ b/boards/adafruit/feather/adafruit_feather_nrf52840_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/adafruit_feather_nrf52840/board.cmake b/boards/adafruit/feather/board.cmake similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/board.cmake rename to boards/adafruit/feather/board.cmake diff --git a/boards/adafruit/feather/board.yml b/boards/adafruit/feather/board.yml new file mode 100644 index 00000000000..f4ae7ce2d19 --- /dev/null +++ b/boards/adafruit/feather/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_feather + vendor: adafruit + socs: + - name: nrf52840 diff --git a/boards/arm/adafruit_feather_nrf52840/doc/img/adafruit_feather_nrf52840.jpg b/boards/adafruit/feather/doc/img/adafruit_feather_nrf52840.jpg similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/doc/img/adafruit_feather_nrf52840.jpg rename to boards/adafruit/feather/doc/img/adafruit_feather_nrf52840.jpg diff --git a/boards/adafruit/feather/doc/index.rst b/boards/adafruit/feather/doc/index.rst new file mode 100644 index 00000000000..241f11e7305 --- /dev/null +++ b/boards/adafruit/feather/doc/index.rst @@ -0,0 +1,146 @@ +.. _adafruit_feather_nrf52840: + +Adafruit Feather nRF52840 Express +################################# + +Overview +******** + +The Adafruit Feather nRF52840 provides support for the Nordic Semiconductor +nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/adafruit_feather_nrf52840.jpg + :align: center + :alt: Adafruit Feather nRF52840 Express + +Hardware +******** + +- nRF52840 ARM Cortex-M4F processor at 64 MHz +- 1 MB flash memory and 256 KB of SRAM +- Battery connector and charger for 3.7 V lithium polymer batteries +- Charging indicator LED +- 2 User LEDs +- 1 NeoPixel LED +- Reset button +- SWD connector + +Supported Features +================== + +The Adafruit Feather nRF52840 board configuration supports the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +The `Adafruit Feather nRF52840 Express Learn site`_ has detailed +information about the board including `pinouts`_ and the `schematic`_. + +LED +--- + +* LED0 (red) = P1.15 +* LED1 (blue) = P1.10 + +Push buttons +------------ + +* SWITCH = P1.02 +* RESET = P0.18 + +Programming and Debugging +************************* + +Applications for the ``adafruit_feather/nrf52840`` board configuration +can be built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + +Flashing +======== + +Flashing Zephyr onto the ``adafruit_feather_nrf52480`` board requires +an external programmer. The programmer is attached to the SWD header. + +Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application. + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather/nrf52840 + :goals: build + :compact: + +Flash the image. + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather/nrf52840 + :goals: flash + :compact: + +You should see the red LED blink. + +References +********** + +.. target-notes:: + +.. _Adafruit Feather nRF52840 Express Learn site: + https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/ + +.. _pinouts: + https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/pinouts + +.. _schematic: + https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/downloads diff --git a/boards/arm/adafruit_feather_nrf52840/feather_connector.dtsi b/boards/adafruit/feather/feather_connector.dtsi similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/feather_connector.dtsi rename to boards/adafruit/feather/feather_connector.dtsi diff --git a/boards/arm/adafruit_feather_nrf52840/pre_dt_board.cmake b/boards/adafruit/feather/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/pre_dt_board.cmake rename to boards/adafruit/feather/pre_dt_board.cmake diff --git a/boards/adafruit/feather_m0_basic_proto/Kconfig.adafruit_feather_m0_basic_proto b/boards/adafruit/feather_m0_basic_proto/Kconfig.adafruit_feather_m0_basic_proto new file mode 100644 index 00000000000..cd561180a01 --- /dev/null +++ b/boards/adafruit/feather_m0_basic_proto/Kconfig.adafruit_feather_m0_basic_proto @@ -0,0 +1,6 @@ +# Copyright (c) 2018 Henrik Brix Andersen +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_M0_BASIC_PROTO + select SOC_SAMD21G18A diff --git a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto-pinctrl.dtsi b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto-pinctrl.dtsi rename to boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto-pinctrl.dtsi diff --git a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts rename to boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts diff --git a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml rename to boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml diff --git a/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig new file mode 100644 index 00000000000..55aee7ced2d --- /dev/null +++ b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_USE_DT_CODE_PARTITION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/adafruit_feather_m0_basic_proto/board.cmake b/boards/adafruit/feather_m0_basic_proto/board.cmake similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/board.cmake rename to boards/adafruit/feather_m0_basic_proto/board.cmake diff --git a/boards/adafruit/feather_m0_basic_proto/board.yml b/boards/adafruit/feather_m0_basic_proto/board.yml new file mode 100644 index 00000000000..cf9353bf78c --- /dev/null +++ b/boards/adafruit/feather_m0_basic_proto/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_feather_m0_basic_proto + vendor: adafruit + socs: + - name: samd21g18a diff --git a/boards/arm/adafruit_feather_m0_basic_proto/doc/img/adafruit_feather_m0_basic_proto.jpg b/boards/adafruit/feather_m0_basic_proto/doc/img/adafruit_feather_m0_basic_proto.jpg similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/doc/img/adafruit_feather_m0_basic_proto.jpg rename to boards/adafruit/feather_m0_basic_proto/doc/img/adafruit_feather_m0_basic_proto.jpg diff --git a/boards/adafruit/feather_m0_basic_proto/doc/index.rst b/boards/adafruit/feather_m0_basic_proto/doc/index.rst new file mode 100644 index 00000000000..a9dc7f0c229 --- /dev/null +++ b/boards/adafruit/feather_m0_basic_proto/doc/index.rst @@ -0,0 +1,167 @@ +.. _adafruit_feather_m0_basic_proto: + +Adafruit Feather M0 Basic Proto +############################### + +Overview +******** + +The Adafruit Feather M0 Basic Proto is a thin, light ARM development +board with an onboard battery connector and charger for 3.7 V lithium +polymer batteries, charging status indicator and user LEDs, native USB +connector, 20 I/O pins, and a small prototyping area. + +.. image:: img/adafruit_feather_m0_basic_proto.jpg + :align: center + :alt: Adafruit Feather M0 Basic Proto + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- Battery connector and charger for 3.7 V lithium polymer batteries +- Charging indicator LED +- User LED +- Reset button +- Native USB port + +Supported Features +================== + +The adafruit_feather_m0_basic_proto board configuration supports the +following hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | Nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | Systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial port | ++-----------+------------+------------------------------------------+ +| I2C | on-chip | Inter-Integrated Circuit | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface port | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig`. + +Connections and IOs +=================== + +The `Adafruit Feather M0 Basic Proto Learn site`_ has detailed +information about the board including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 +Basic Proto, SERCOM0 is the Zephyr console and is available on pins 0 +(RX) and 1 (TX). + +I2C Port +======== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 +Basic Proto, SERCOM3 is available on pin 20 (SDA) and pin 21 (SCL). + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the Adafruit Feather M0 +Basic Proto, SERCOM4 is available on pin 22 (MISO), pin 23 (MOSI), and +pin 24 (SCK). + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +Programming and Debugging +************************* + +The Adafruit Feather M0 Basic Proto ships with a BOSSA compatible +SAM-BA bootloader. The bootloader can be entered by quickly tapping +the reset button twice. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m0_basic_proto + :goals: build + :compact: + +#. Connect the Adafruit Feather M0 Basic Proto to your host computer + using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m0_basic_proto + :goals: flash + :compact: + + You should see "Hello World! adafruit_feather_m0_basic_proto" in your terminal. + +References +********** + +.. target-notes:: + +.. _Adafruit Feather M0 Basic Proto Learn site: + https://learn.adafruit.com/adafruit-feather-m0-basic-proto/ + +.. _pinouts: + https://learn.adafruit.com/adafruit-feather-m0-basic-proto/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-feather-m0-basic-proto/downloads diff --git a/boards/arm/adafruit_feather_m0_basic_proto/feather_connector.dtsi b/boards/adafruit/feather_m0_basic_proto/feather_connector.dtsi similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/feather_connector.dtsi rename to boards/adafruit/feather_m0_basic_proto/feather_connector.dtsi diff --git a/boards/arm/adafruit_feather_m0_basic_proto/pre_dt_board.cmake b/boards/adafruit/feather_m0_basic_proto/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/pre_dt_board.cmake rename to boards/adafruit/feather_m0_basic_proto/pre_dt_board.cmake diff --git a/boards/adafruit/feather_m0_lora/Kconfig.adafruit_feather_m0_lora b/boards/adafruit/feather_m0_lora/Kconfig.adafruit_feather_m0_lora new file mode 100644 index 00000000000..17a1d5e49f3 --- /dev/null +++ b/boards/adafruit/feather_m0_lora/Kconfig.adafruit_feather_m0_lora @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Miguel Dardenne +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_M0_LORA + select SOC_SAMD21G18A diff --git a/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora-pinctrl.dtsi b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora-pinctrl.dtsi rename to boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora-pinctrl.dtsi diff --git a/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora.dts b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.dts similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora.dts rename to boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.dts diff --git a/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora.yaml b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.yaml similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora.yaml rename to boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.yaml diff --git a/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora_defconfig b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora_defconfig new file mode 100644 index 00000000000..55aee7ced2d --- /dev/null +++ b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_USE_DT_CODE_PARTITION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/adafruit_feather_m0_lora/board.cmake b/boards/adafruit/feather_m0_lora/board.cmake similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/board.cmake rename to boards/adafruit/feather_m0_lora/board.cmake diff --git a/boards/adafruit/feather_m0_lora/board.yml b/boards/adafruit/feather_m0_lora/board.yml new file mode 100644 index 00000000000..b720fc95ffe --- /dev/null +++ b/boards/adafruit/feather_m0_lora/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_feather_m0_lora + vendor: adafruit + socs: + - name: samd21g18a diff --git a/boards/arm/adafruit_feather_m0_lora/doc/img/adafruit_feather_m0_lora.jpg b/boards/adafruit/feather_m0_lora/doc/img/adafruit_feather_m0_lora.jpg similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/doc/img/adafruit_feather_m0_lora.jpg rename to boards/adafruit/feather_m0_lora/doc/img/adafruit_feather_m0_lora.jpg diff --git a/boards/adafruit/feather_m0_lora/doc/index.rst b/boards/adafruit/feather_m0_lora/doc/index.rst new file mode 100644 index 00000000000..3303c6e480c --- /dev/null +++ b/boards/adafruit/feather_m0_lora/doc/index.rst @@ -0,0 +1,176 @@ +.. _adafruit_feather_m0_lora: + +Adafruit Feather M0 LoRa +######################## + +Overview +******** + +The Adafruit Feather M0 Lora is a thin, light ARM development +boards with an onboard battery connector and charger for 3.7 V lithium +polymer batteries, charging status indicator and user LEDs, native USB +connector, 20 I/O pins, and a LoRa radio module from Semtech. + +.. image:: img/adafruit_feather_m0_lora.jpg + :align: center + :alt: Adafruit Feather M0 LoRa + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- Battery connector and charger for 3.7 V lithium polymer batteries +- Charging indicator LED +- User LED +- Reset button +- Native USB port +- SX127x LoRa radio + +Supported Features +================== + +The adafruit_feather_m0_lora board configuration supports the +following hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | Nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | Systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial port | ++-----------+------------+------------------------------------------+ +| I2C | on-chip | Inter-Integrated Circuit | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface port | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| RADIO | SPI | LoRa radio | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora_defconfig`. + +Connections and IOs +=================== + +The `Adafruit Feather M0 with LoRa radio module Learn site`_ has detailed +information about the board including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 +with LoRa, SERCOM0 is the Zephyr console and is available on pins 0 +(RX) and 1 (TX). + +I2C Port +======== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 +with LoRa, SERCOM3 is available on pin 20 (SDA) and pin 21 (SCL). + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the Adafruit Feather M0 +with LoRa, SERCOM4 is available on pin 22 (MISO), pin 23 (MOSI), and +pin 24 (SCK). + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +LoRa Radio +========== +The Semtech SX127x radio chip on the Adafruit Feather M0 with LoRa +is attached to the SPI port (SERCOM4). Depending on the hardware +version, 433MHz or 900MHz is supported. + +Programming and Debugging +************************* + +The Adafruit Feather M0 with LoRa ships with a BOSSA compatible +SAM-BA bootloader. The bootloader can be entered by quickly tapping +the reset button twice. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m0_lora + :goals: build + :compact: + +#. Connect the Adafruit Feather M0 with LoRa to your host computer + using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m0_lora + :goals: flash + :compact: + + You should see "Hello World! adafruit_feather_m0_lora" in your terminal. + +References +********** + +.. target-notes:: + +.. _Adafruit Feather M0 with LoRa radio module Learn site: + https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module + +.. _pinouts: + https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module/downloads diff --git a/boards/arm/adafruit_feather_m0_lora/feather_connector.dtsi b/boards/adafruit/feather_m0_lora/feather_connector.dtsi similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/feather_connector.dtsi rename to boards/adafruit/feather_m0_lora/feather_connector.dtsi diff --git a/boards/arm/adafruit_feather_m0_lora/pre_dt_board.cmake b/boards/adafruit/feather_m0_lora/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/pre_dt_board.cmake rename to boards/adafruit/feather_m0_lora/pre_dt_board.cmake diff --git a/boards/adafruit/feather_stm32f405/Kconfig.adafruit_feather_stm32f405 b/boards/adafruit/feather_stm32f405/Kconfig.adafruit_feather_stm32f405 new file mode 100644 index 00000000000..e26a99c90ce --- /dev/null +++ b/boards/adafruit/feather_stm32f405/Kconfig.adafruit_feather_stm32f405 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Lucian Copeland for Adafruit Industries +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_STM32F405 + select SOC_STM32F405XX diff --git a/boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405.dts b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405.dts rename to boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts diff --git a/boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405.yaml b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405.yaml rename to boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml diff --git a/boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405_defconfig b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405_defconfig similarity index 84% rename from boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405_defconfig rename to boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405_defconfig index ca015a21976..c729b83e3d0 100644 --- a/boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405_defconfig +++ b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F405XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/adafruit_feather_stm32f405/board.cmake b/boards/adafruit/feather_stm32f405/board.cmake similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/board.cmake rename to boards/adafruit/feather_stm32f405/board.cmake diff --git a/boards/adafruit/feather_stm32f405/board.yml b/boards/adafruit/feather_stm32f405/board.yml new file mode 100644 index 00000000000..e30f5c0cbcf --- /dev/null +++ b/boards/adafruit/feather_stm32f405/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_feather_stm32f405 + vendor: adafruit + socs: + - name: stm32f405xx diff --git a/boards/arm/adafruit_feather_stm32f405/doc/img/adafruit_feather_stm32f405.jpg b/boards/adafruit/feather_stm32f405/doc/img/adafruit_feather_stm32f405.jpg similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/doc/img/adafruit_feather_stm32f405.jpg rename to boards/adafruit/feather_stm32f405/doc/img/adafruit_feather_stm32f405.jpg diff --git a/boards/arm/adafruit_feather_stm32f405/doc/index.rst b/boards/adafruit/feather_stm32f405/doc/index.rst similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/doc/index.rst rename to boards/adafruit/feather_stm32f405/doc/index.rst diff --git a/boards/arm/adafruit_feather_stm32f405/feather_connector.dtsi b/boards/adafruit/feather_stm32f405/feather_connector.dtsi similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/feather_connector.dtsi rename to boards/adafruit/feather_stm32f405/feather_connector.dtsi diff --git a/boards/arm/adafruit_feather_stm32f405/support/openocd.cfg b/boards/adafruit/feather_stm32f405/support/openocd.cfg similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/support/openocd.cfg rename to boards/adafruit/feather_stm32f405/support/openocd.cfg diff --git a/boards/adafruit/grand_central_m4_express/Kconfig.adafruit_grand_central_m4_express b/boards/adafruit/grand_central_m4_express/Kconfig.adafruit_grand_central_m4_express new file mode 100644 index 00000000000..d761870a9af --- /dev/null +++ b/boards/adafruit/grand_central_m4_express/Kconfig.adafruit_grand_central_m4_express @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Lukas Jung +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_GRAND_CENTRAL_M4_EXPRESS + select SOC_SAMD51P20A diff --git a/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express-pinctrl.dtsi b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express-pinctrl.dtsi rename to boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express-pinctrl.dtsi diff --git a/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express.dts b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.dts similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express.dts rename to boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.dts diff --git a/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express.yaml b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.yaml similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express.yaml rename to boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.yaml diff --git a/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express_defconfig b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express_defconfig new file mode 100644 index 00000000000..82a151d53e8 --- /dev/null +++ b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD5X_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/adafruit_grand_central_m4_express/board.cmake b/boards/adafruit/grand_central_m4_express/board.cmake similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/board.cmake rename to boards/adafruit/grand_central_m4_express/board.cmake diff --git a/boards/adafruit/grand_central_m4_express/board.yml b/boards/adafruit/grand_central_m4_express/board.yml new file mode 100644 index 00000000000..92a48d1b2b3 --- /dev/null +++ b/boards/adafruit/grand_central_m4_express/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_grand_central_m4_express + vendor: adafruit + socs: + - name: samd51p20a diff --git a/boards/arm/adafruit_grand_central_m4_express/doc/img/adafruit_grand_central_m4_express.webp b/boards/adafruit/grand_central_m4_express/doc/img/adafruit_grand_central_m4_express.webp similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/doc/img/adafruit_grand_central_m4_express.webp rename to boards/adafruit/grand_central_m4_express/doc/img/adafruit_grand_central_m4_express.webp diff --git a/boards/adafruit/grand_central_m4_express/doc/index.rst b/boards/adafruit/grand_central_m4_express/doc/index.rst new file mode 100644 index 00000000000..ec8ab08afdf --- /dev/null +++ b/boards/adafruit/grand_central_m4_express/doc/index.rst @@ -0,0 +1,195 @@ +.. _adafruit_grand_central_m4_express: + +Adafruit Grand Central M4 Express +################################# + +Overview +******** + +The Adafruit Grand Central M4 Express is an ARM development board with the +form factor of an Arduino Mega. +It features 70 GPIO pins, a microSDHC slot and 8MiB of QSPI Flash. + +.. figure:: img/adafruit_grand_central_m4_express.webp + :width: 800px + :align: center + :alt: Adafruit Grand Central M4 Express + + Adafruit Grand Central M4 Express (Credit: Kattni Rembor / Adafruit) + +Hardware +******** + +- ATSAMD51P20A ARM Cortex-M4F processor at 120 MHz +- 1024 KiB of flash memory and 256 KiB of RAM +- 8 MiB of QSPI flash +- A red user LED +- A RGB "NeoPixel" / WS2812B LED +- A microSDHC slot (connected via SPI) +- Native USB port + +Supported Features +================== + +The adafruit_grand_central_m4_express board configuration supports the following +hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | Nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | SysTick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports, User LED | ++-----------+------------+------------------------------------------+ +| UART | on-chip | Serial ports, Console | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | SPI ports, microSDHC slot | ++-----------+------------+------------------------------------------+ +| TRNG | on-chip | True Random Number Generator | ++-----------+------------+------------------------------------------+ +| RTC | on-chip | Real-Time Counter | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog Timer | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express_defconfig`. + +Connections and IOs +=================== + +The `Adafruit Learning System`_ has detailed information about +the board including `pinouts`_ and the `schematics`_. + +System Clock +============ + +The SAMD51 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 120 MHz system clock. + +Serial Port +=========== + +The SAMD51 MCU has 8 SERCOM based UARTs. On the Grand Central, SERCOM0 is +the Zephyr console and is available on RX(PB25) and TX(PB24). + +SPI Port +======== + +The SAMD51 MCU has 8 SERCOM based SPIs. On the Grand Central, SERCOM7 has been +set into SPI mode to connect to devices over the SCK(PD09), MOSI(PD08), and MISO(PD11) pins. +Additionally SERCOM2 has been configured as SPI to access the microSDHC card. + +I2C Port +======== + +The SAMD51 MCU has 8 SERCOM based I2Cs. On the Grand Central, SERCOM3 has been +configured as I2C to connect to devices over the SCL(PB21) and SDA(PB20) pins. + +USB Device Port +=============== + +The SAMD51 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +Programming and Debugging +************************* + +The Grand Central ships with a BOSSA compatible UF2 bootloader. +The bootloader can be entered by quickly tapping the reset button twice. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_grand_central_m4_express + :goals: build + :compact: + +#. Connect the Grand Central to your host computer using USB. + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_grand_central_m4_express + :goals: flash + :compact: + + You should see "Hello World! adafruit_grand_central_m4_express" in your terminal. + +Debugging +========= + +In addition to the built-in bootloader, the Grand Central can be flashed and +debugged using a SWD probe such as the Segger J-Link. + +#. Connect the probe to the board using the 10-pin SWD interface. + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_grand_central_m4_express + :goals: flash + :flash-args: -r openocd + :compact: + +#. Start debugging: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_grand_central_m4_express + :goals: debug + :compact: + +References +********** + +.. target-notes:: + +.. _Adafruit Learning System: + https://learn.adafruit.com/adafruit-grand-central + +.. _pinouts: + https://learn.adafruit.com/adafruit-grand-central/pinouts + +.. _schematics: + https://learn.adafruit.com/adafruit-grand-central/downloads + +.. _J-Link: + https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/adafruit_grand_central_m4_express/support/openocd.cfg b/boards/adafruit/grand_central_m4_express/support/openocd.cfg similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/support/openocd.cfg rename to boards/adafruit/grand_central_m4_express/support/openocd.cfg diff --git a/boards/adafruit/index.rst b/boards/adafruit/index.rst new file mode 100644 index 00000000000..63e0385c8e5 --- /dev/null +++ b/boards/adafruit/index.rst @@ -0,0 +1,10 @@ +.. _boards-adafruit: + +Adafruit Industries LLC +####################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/adafruit/itsybitsy/Kconfig b/boards/adafruit/itsybitsy/Kconfig new file mode 100644 index 00000000000..e2c47273197 --- /dev/null +++ b/boards/adafruit/itsybitsy/Kconfig @@ -0,0 +1,15 @@ +# Adafruit ItsyBitsy nRF52840 Express board configuration + +# Copyright (c) 2022 Embla Flatlandsmo +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_ADAFRUIT_ITSYBITSY + +config BOARD_SERIAL_BACKEND_CDC_ACM + bool "USB CDC" + default y + depends on BOARD_ADAFRUIT_ITSYBITSY diff --git a/boards/adafruit/itsybitsy/Kconfig.adafruit_itsybitsy b/boards/adafruit/itsybitsy/Kconfig.adafruit_itsybitsy new file mode 100644 index 00000000000..6e64301cb46 --- /dev/null +++ b/boards/adafruit/itsybitsy/Kconfig.adafruit_itsybitsy @@ -0,0 +1,7 @@ +# Adafruit ItsyBitsy nRF52840 Express board configuration + +# Copyright (c) 2022 Embla Flatlandsmo +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_ITSYBITSY + select SOC_NRF52840_QIAA diff --git a/boards/adafruit/itsybitsy/Kconfig.defconfig b/boards/adafruit/itsybitsy/Kconfig.defconfig new file mode 100644 index 00000000000..b637497e148 --- /dev/null +++ b/boards/adafruit/itsybitsy/Kconfig.defconfig @@ -0,0 +1,53 @@ +# Adafruit ItsyBitsy nRF52840 Express board configuration + +# Copyright (c) 2022 Embla Flatlandsmo +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_ITSYBITSY + +config BT_CTLR + default BT + +if BOARD_SERIAL_BACKEND_CDC_ACM + +config USB_DEVICE_STACK + default y + +config USB_CDC_ACM + default SERIAL + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if CONSOLE + +config SHELL_BACKEND_SERIAL_CHECK_DTR + default SHELL + depends on UART_LINE_CTRL + +config UART_LINE_CTRL + default SHELL + +config USB_DEVICE_REMOTE_WAKEUP + default n + +if LOG + +# Logger cannot use itself to log +config USB_CDC_ACM_LOG_LEVEL + default 0 + +# Set USB log level to error only +config USB_DEVICE_LOG_LEVEL + default 1 + +# Wait 1500ms at startup for logging +config LOG_PROCESS_THREAD_STARTUP_DELAY_MS + default 1500 + +endif # LOG + +endif # BOARD_SERIAL_BACKEND_CDC_ACM + +endif # BOARD_ADAFRUIT_ITSYBITSY diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840-pinctrl.dtsi b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840-pinctrl.dtsi rename to boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840-pinctrl.dtsi diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.dts b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts similarity index 100% rename from boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.dts rename to boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.yaml b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml similarity index 86% rename from boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.yaml rename to boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml index a95f91e9b12..3e571954bf1 100644 --- a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.yaml +++ b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: adafruit_itsybitsy_nrf52840 +identifier: adafruit_itsybitsy/nrf52840 name: Adafruit ItsyBitsy nRF52840 Express type: mcu arch: arm diff --git a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840_defconfig b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840_defconfig new file mode 100644 index 00000000000..f136674fc14 --- /dev/null +++ b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Flashing +CONFIG_USE_DT_CODE_PARTITION=y +CONFIG_BUILD_OUTPUT_UF2=y diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/board.cmake b/boards/adafruit/itsybitsy/board.cmake similarity index 100% rename from boards/arm/adafruit_itsybitsy_nrf52840/board.cmake rename to boards/adafruit/itsybitsy/board.cmake diff --git a/boards/adafruit/itsybitsy/board.yml b/boards/adafruit/itsybitsy/board.yml new file mode 100644 index 00000000000..484a68e348b --- /dev/null +++ b/boards/adafruit/itsybitsy/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_itsybitsy + vendor: adafruit + socs: + - name: nrf52840 diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/doc/img/adafruit_itsybitsy_nrf52840.jpeg b/boards/adafruit/itsybitsy/doc/img/adafruit_itsybitsy_nrf52840.jpeg similarity index 100% rename from boards/arm/adafruit_itsybitsy_nrf52840/doc/img/adafruit_itsybitsy_nrf52840.jpeg rename to boards/adafruit/itsybitsy/doc/img/adafruit_itsybitsy_nrf52840.jpeg diff --git a/boards/adafruit/itsybitsy/doc/index.rst b/boards/adafruit/itsybitsy/doc/index.rst new file mode 100644 index 00000000000..f4d6259ff41 --- /dev/null +++ b/boards/adafruit/itsybitsy/doc/index.rst @@ -0,0 +1,192 @@ +.. _adafruit_itsybitsy_nrf52840: + +Adafruit ItsyBitsy nRF52840 +########################### + +Overview +******** + +The Adafruit ItsyBitsy nRF52840 Express is a small (36 mm x 18 mm) ARM +development board with an onboard RGB LED, USB port, 2 MB of QSPI flash, +and range of I/O broken out onto 21 GPIO pins. + +This development kit has the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`I2S (Inter-Integrated Sound)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. image:: img/adafruit_itsybitsy_nrf52840.jpeg + :align: center + :alt: Adafruit ItsyBitsy nRF52840 Express + +Hardware +******** +- nRF52840 ARM Cortex-M4F CPU at 64MHz +- 1 MB of flash memory and 256 KB of SRAM +- 2 MB of QSPI flash +- A user LED +- A user switch +- An RGB DotStar LED +- Native USB port +- One reset button + +Supported Features +================== + +The Adafruit ItsyBitsy nRF52840 board configuration supports the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| QSPI(M) | on-chip | nor | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +The `Adafruit ItsyBitsy nRF52840 Express Learn site`_ has detailed +information about the board including `pinouts`_ and the `schematic`_. + +LED +--- + +* LED0 (red) = P0.06 + +* LED1 (Adafruit DotStar) + + * DATA = P0.08 + + * CLK = P1.09 + +Push buttons +------------ + +* SWITCH = P0.29 + +* RESET = P0.18 + +Logging +------- + +Logging is done using the USB-CDC port. See the :zephyr:code-sample:`logging` sample +or the :zephyr:code-sample:`usb-cdc-acm-console` sample applications to see how this works. + +Testing LEDs and buttons on the Adafruit ItsyBitsy nRF52840 Express +******************************************************************* +The :zephyr:code-sample:`button` sample lets you test the buttons (switches) and the red LED. +The :zephyr:code-sample:`blinky` sample lets you test the red LED. + +The DotStar LED has been implemented as a SPI device and can be tested +with the :zephyr:code-sample:`led-apa102` sample application. + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts`. + +Programming and Debugging +************************* +The ItsyBitsy ships with the BOSSA compatible UF2 bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +First time setup +================ +Some versions of this board were shipped with a buggy bootloader. +Ensure that the bootloader is up to date by following the +`Adafruit UF2 Bootloader update`_ tutorial. Note that this tutorial +was made for the Adafruit Feather nRF52840, but the steps to update +the bootloader are the same for the ItsyBitsy. The files for the +ItsyBitsy bootloader can be found in the `Adafruit nRF52 Bootloader repo`_. + +The building and flashing of Zephyr applications have been tested with +release 0.7.0 of the UF2 bootloader. + +Flashing +======== +Flashing is done by dragging and dropping the built Zephyr UF2-file +into the :code:`ITSY840BOOT` drive. + +#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` + sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_itsybitsy/nrf52840 + :goals: build + :compact: + +#. Connect the ItsyBitsy to your host computer using USB + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + Drag and drop the file :code:`samples/basic/blinky/build/zephyr/zephyr.uf2` + into :code:`ITSY840BOOT` + +The device will disconnect and you should see the red LED blink. + +References +********** + +.. target-notes:: + +.. _Adafruit ItsyBitsy nRF52840 Express Learn site: + https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express + +.. _pinouts: + https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express/downloads + +.. _Adafruit UF2 Bootloader update: + https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/update-bootloader + +.. _Adafruit nRF52 Bootloader repo: + https://github.com/adafruit/Adafruit_nRF52_Bootloader/releases diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/pre_dt_board.cmake b/boards/adafruit/itsybitsy/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_itsybitsy_nrf52840/pre_dt_board.cmake rename to boards/adafruit/itsybitsy/pre_dt_board.cmake diff --git a/boards/adafruit/itsybitsy_m4_express/Kconfig.adafruit_itsybitsy_m4_express b/boards/adafruit/itsybitsy_m4_express/Kconfig.adafruit_itsybitsy_m4_express new file mode 100644 index 00000000000..79fa829dbee --- /dev/null +++ b/boards/adafruit/itsybitsy_m4_express/Kconfig.adafruit_itsybitsy_m4_express @@ -0,0 +1,6 @@ +# Copyright (c) 2020 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_ITSYBITSY_M4_EXPRESS + select SOC_SAMD51G19A diff --git a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express-pinctrl.dtsi b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express-pinctrl.dtsi rename to boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express-pinctrl.dtsi diff --git a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts rename to boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts diff --git a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml rename to boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml diff --git a/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig new file mode 100644 index 00000000000..32994801245 --- /dev/null +++ b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD5X_OSCULP32K_AS_MAIN=y + +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y + +CONFIG_ARM_MPU=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/adafruit_itsybitsy_m4_express/board.cmake b/boards/adafruit/itsybitsy_m4_express/board.cmake similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/board.cmake rename to boards/adafruit/itsybitsy_m4_express/board.cmake diff --git a/boards/adafruit/itsybitsy_m4_express/board.yml b/boards/adafruit/itsybitsy_m4_express/board.yml new file mode 100644 index 00000000000..7d295017fc9 --- /dev/null +++ b/boards/adafruit/itsybitsy_m4_express/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_itsybitsy_m4_express + vendor: adafruit + socs: + - name: samd51g19a diff --git a/boards/arm/adafruit_itsybitsy_m4_express/doc/img/adafruit_itsybitsy_m4_express.jpg b/boards/adafruit/itsybitsy_m4_express/doc/img/adafruit_itsybitsy_m4_express.jpg similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/doc/img/adafruit_itsybitsy_m4_express.jpg rename to boards/adafruit/itsybitsy_m4_express/doc/img/adafruit_itsybitsy_m4_express.jpg diff --git a/boards/adafruit/itsybitsy_m4_express/doc/index.rst b/boards/adafruit/itsybitsy_m4_express/doc/index.rst new file mode 100644 index 00000000000..a25df0bf2fa --- /dev/null +++ b/boards/adafruit/itsybitsy_m4_express/doc/index.rst @@ -0,0 +1,209 @@ +.. _adafruit_itsybitsy_m4_express: + +Adafruit ItsyBitsy M4 Express +############################# + +Overview +******** + +The Adafruit ItsyBitsy M4 express is a small (36 mm x 18 mm) ARM development +board with an onboard RGB LED, USB port, 2 MiB of SPI flash, and range of I/O +broken out onto 23 GPIO pins. + +.. image:: img/adafruit_itsybitsy_m4_express.jpg + :align: center + :alt: Adafruit ItsyBitsy M4 Express + +Hardware +******** + +- ATSAMD51G19A ARM Cortex-M4 processor at 120 MHz +- 512 KiB of flash memory and 192 KiB of RAM +- 2 MiB of SPI flash +- Internal trimmed 8 MHz oscillator +- A user LED +- An RGB DotStar LED +- Native USB port +- One reset button + +Supported Features +================== + +The adafruit_itsybitsy_m4_express board configuration supports the following +hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | Nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| TRNG | on-chip | True Random Number Generator | ++-----------+------------+------------------------------------------+ +| HWINFO | on-chip | Unique 128 bit serial number | ++-----------+------------+------------------------------------------+ +| RTC | on-chip | Real-Time Counter | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog Timer | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig`. + +Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. +To use the RTC, set :code:`CONFIG_CORTEX_M_SYSTICK=n` and set +:code:`CONFIG_SYS_CLOCK_TICKS_PER_SEC` to no more than 32 kHZ divided by 7, +i.e. no more than 4500. + +Connections and IOs +=================== + +The `Adafruit Learning System`_ has detailed information about +the board including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD51 MCU is configured to use the 32 kHz internal oscillator +with the on-chip PLL generating the 120 MHz system clock. + +Serial Port +=========== + +The SAMD51 MCU has 6 SERCOM based USARTs. On the ItsyBitsy, SERCOM3 is +the Zephyr console and is available on pins 0 (RX) and 1 (TX). + +SPI Port +======== + +The SAMD51 MCU has 6 SERCOM based SPIs. On the ItsyBitsy, SERCOM1 can be put +into SPI mode and used to connect to devices over the SCK (SCLK), MO (MOSI), and +MI (MISO) pins. + +PWM +=== + +The SAMD51 has three PWM generators with up to six channels each. :code:`TCC_0` +has a resolution of 24 bits and all other generators are 16 bit. :code:`TCC_1` +pin 2 is mapped to PA18 (D7) and pin 3 is mapped to PA19 (D9). + +USB Device Port +=============== + +The SAMD51 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +Programming and Debugging +************************* + +The ItsyBitsy ships with a the BOSSA compatible UF2 bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader +will be entered automatically when you run :code:`west flash`. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_itsybitsy_m4_express + :goals: build + :compact: + +#. Connect the ItsyBitsy to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_itsybitsy_m4_express + :goals: flash + :compact: + + You should see "Hello World! adafruit_itsybitsy_m4_express" in your terminal. + +Debugging +========= + +In addition to the built-in bootloader, the ItsyBitsy can be flashed and +debugged using a SWD probe such as the Segger J-Link. + +#. Connect the board to the probe by connecting the :code:`SWCLK`, + :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the + ItsyBitsy to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, :code:`GND`, + and :code:`VTref` pins on the `J-Link`_. + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_itsybitsy_m4_express + :goals: flash + :flash-args: -r openocd + :compact: + +#. Start debugging: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_itsybitsy_m4_express + :goals: debug + :compact: + +References +********** + +.. target-notes:: + +.. _Adafruit Learning System: + https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4 + +.. _pinouts: + https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4/pinouts + +.. _schematic: + https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4/downloads + +.. _J-Link: + https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/adafruit_itsybitsy_m4_express/pre_dt_board.cmake b/boards/adafruit/itsybitsy_m4_express/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/pre_dt_board.cmake rename to boards/adafruit/itsybitsy_m4_express/pre_dt_board.cmake diff --git a/boards/arm/adafruit_itsybitsy_m4_express/support/openocd.cfg b/boards/adafruit/itsybitsy_m4_express/support/openocd.cfg similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/support/openocd.cfg rename to boards/adafruit/itsybitsy_m4_express/support/openocd.cfg diff --git a/boards/adafruit/kb2040/Kconfig.adafruit_kb2040 b/boards/adafruit/kb2040/Kconfig.adafruit_kb2040 new file mode 100644 index 00000000000..669fddf899c --- /dev/null +++ b/boards/adafruit/kb2040/Kconfig.adafruit_kb2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Pete Johanson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_KB2040 + select SOC_RP2040 diff --git a/boards/adafruit/kb2040/Kconfig.defconfig b/boards/adafruit/kb2040/Kconfig.defconfig new file mode 100644 index 00000000000..e17682abac0 --- /dev/null +++ b/boards/adafruit/kb2040/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_KB2040 + +config RP2_FLASH_W25Q080 + default y + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_ADAFRUIT_KB2040 diff --git a/boards/arm/adafruit_kb2040/adafruit_kb2040-pinctrl.dtsi b/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_kb2040/adafruit_kb2040-pinctrl.dtsi rename to boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi diff --git a/boards/arm/adafruit_kb2040/adafruit_kb2040.dts b/boards/adafruit/kb2040/adafruit_kb2040.dts similarity index 100% rename from boards/arm/adafruit_kb2040/adafruit_kb2040.dts rename to boards/adafruit/kb2040/adafruit_kb2040.dts diff --git a/boards/arm/adafruit_kb2040/adafruit_kb2040.yaml b/boards/adafruit/kb2040/adafruit_kb2040.yaml similarity index 100% rename from boards/arm/adafruit_kb2040/adafruit_kb2040.yaml rename to boards/adafruit/kb2040/adafruit_kb2040.yaml diff --git a/boards/arm/adafruit_kb2040/adafruit_kb2040_defconfig b/boards/adafruit/kb2040/adafruit_kb2040_defconfig similarity index 79% rename from boards/arm/adafruit_kb2040/adafruit_kb2040_defconfig rename to boards/adafruit/kb2040/adafruit_kb2040_defconfig index 6ce0691032d..f2202a534b6 100644 --- a/boards/arm/adafruit_kb2040/adafruit_kb2040_defconfig +++ b/boards/adafruit/kb2040/adafruit_kb2040_defconfig @@ -1,16 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_ADAFRUIT_KB2040=y - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 -# enable uart driver +# Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/adafruit_kb2040/board.cmake b/boards/adafruit/kb2040/board.cmake similarity index 100% rename from boards/arm/adafruit_kb2040/board.cmake rename to boards/adafruit/kb2040/board.cmake diff --git a/boards/adafruit/kb2040/board.yml b/boards/adafruit/kb2040/board.yml new file mode 100644 index 00000000000..5fbe751090e --- /dev/null +++ b/boards/adafruit/kb2040/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_kb2040 + vendor: adafruit + socs: + - name: rp2040 diff --git a/boards/arm/adafruit_kb2040/doc/img/kb2040.jpg b/boards/adafruit/kb2040/doc/img/kb2040.jpg similarity index 100% rename from boards/arm/adafruit_kb2040/doc/img/kb2040.jpg rename to boards/adafruit/kb2040/doc/img/kb2040.jpg diff --git a/boards/arm/adafruit_kb2040/doc/index.rst b/boards/adafruit/kb2040/doc/index.rst similarity index 100% rename from boards/arm/adafruit_kb2040/doc/index.rst rename to boards/adafruit/kb2040/doc/index.rst diff --git a/boards/arm/adafruit_kb2040/sparkfun_pro_micro_connector.dtsi b/boards/adafruit/kb2040/sparkfun_pro_micro_connector.dtsi similarity index 100% rename from boards/arm/adafruit_kb2040/sparkfun_pro_micro_connector.dtsi rename to boards/adafruit/kb2040/sparkfun_pro_micro_connector.dtsi diff --git a/boards/arm/nrf52_adafruit_feather/Kconfig b/boards/adafruit/nrf52_adafruit_feather/Kconfig similarity index 100% rename from boards/arm/nrf52_adafruit_feather/Kconfig rename to boards/adafruit/nrf52_adafruit_feather/Kconfig diff --git a/boards/adafruit/nrf52_adafruit_feather/Kconfig.defconfig b/boards/adafruit/nrf52_adafruit_feather/Kconfig.defconfig new file mode 100644 index 00000000000..48cb9d7332d --- /dev/null +++ b/boards/adafruit/nrf52_adafruit_feather/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52 ADAFRUIT FEATHER board configuration + +# Copyright (c) 2018 LEDCity AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52_ADAFRUIT_FEATHER + +config BT_CTLR + default BT + +endif # BOARD_NRF52_ADAFRUIT_FEATHER diff --git a/boards/adafruit/nrf52_adafruit_feather/Kconfig.nrf52_adafruit_feather b/boards/adafruit/nrf52_adafruit_feather/Kconfig.nrf52_adafruit_feather new file mode 100644 index 00000000000..d2d1b26de92 --- /dev/null +++ b/boards/adafruit/nrf52_adafruit_feather/Kconfig.nrf52_adafruit_feather @@ -0,0 +1,7 @@ +# nRF52 ADAFRUIT FEATHER board configuration + +# Copyright (c) 2018 LEDCity AG. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_ADAFRUIT_FEATHER + select SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_adafruit_feather/board.cmake b/boards/adafruit/nrf52_adafruit_feather/board.cmake similarity index 100% rename from boards/arm/nrf52_adafruit_feather/board.cmake rename to boards/adafruit/nrf52_adafruit_feather/board.cmake diff --git a/boards/arm/nrf52_adafruit_feather/board.h b/boards/adafruit/nrf52_adafruit_feather/board.h similarity index 100% rename from boards/arm/nrf52_adafruit_feather/board.h rename to boards/adafruit/nrf52_adafruit_feather/board.h diff --git a/boards/adafruit/nrf52_adafruit_feather/board.yml b/boards/adafruit/nrf52_adafruit_feather/board.yml new file mode 100644 index 00000000000..a3d6b4274ce --- /dev/null +++ b/boards/adafruit/nrf52_adafruit_feather/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52_adafruit_feather + vendor: adafruit + socs: + - name: nrf52832 diff --git a/boards/arm/nrf52_adafruit_feather/doc/img/nrf52_adafruit_feather.jpg b/boards/adafruit/nrf52_adafruit_feather/doc/img/nrf52_adafruit_feather.jpg similarity index 100% rename from boards/arm/nrf52_adafruit_feather/doc/img/nrf52_adafruit_feather.jpg rename to boards/adafruit/nrf52_adafruit_feather/doc/img/nrf52_adafruit_feather.jpg diff --git a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst new file mode 100644 index 00000000000..0e7680e70b8 --- /dev/null +++ b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst @@ -0,0 +1,192 @@ +.. _nrf52_adafruit_feather: + +nRF52 Adafruit Feather +###################### + +Overview +******** + +The nRF52 Adafruit Bluefruit Feather hardware provides +support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`RTC (nRF RTC System Clock)` +* UART +* GPIO +* FLASH +* RADIO (Bluetooth Low Energy) +* Segger RTT (RTT Console) + +.. figure:: img/nrf52_adafruit_feather.jpg + :align: center + :alt: nRF52 Adafruit Feather Board + + nRF52 Adafruit Feather Board (Credit: Adafruit) + +More information about the board and its features can be found at the +`Adafruit Feather nRF52 Bluefruit Learning Guide`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + +Hardware +******** + +- nRF52832 ARM Cortex-M4F processor at 64 MHz +- 32.768 kHz crystal oscillator +- 512 KiB flash memory and 64 KiB of SRAM +- Battery connector and charger for 3.7 V lithium polymer batteries +- Charging indicator LED +- 2 User LEDs +- Reset button +- SWD connector +- USB serial converter + +Supported Features +================== + +The nRF52 Adafruit Feather board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| UART | on-chip | serial port | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTT | on-chip | console | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +The `Adafruit Feather nRF52 Bluefruit Learning Guide`_ has detailed +information about the board including `pinouts`_ and the `schematic`_. + +LED +--- + +* LED0 (red) = P0.17 +* LED1 (blue) = P0.19 + +Push buttons +------------ + +* DFU = SW0 = P0.20 +* RESET = SW1 = P0.21/reset + +Programming and Debugging +************************* + +The ``nrf52_adafruit_feather`` board is available in two different versions: + +- `Adafruit Feather nRF52 Pro with myNewt Bootloader`_ + This board version is the recommended one to use. It has the SWD header + already populated and comes with the Mynewt serial bootloader installed by + default. + +- `Adafruit Feather nRF52 Bluefruit LE`_ + This board is identical to the board above, but the SWD header is not + populated and ships with an Arduino friendly bootloader. To be able to work + with this version a 2*5pin 0.5" SWD header (e.g. `Adafruit SWD connector`_) + needs to be soldered. + +Applications for the ``nrf52_adafruit_feather`` board configuration can be +built, flashed, and debugged in the usual way. See :ref:`build_an_application` +and :ref:`application_run` for more details on building and running. + +Flashing +======== + +Flashing Zephyr onto the ``nrf52_adafruit_feather`` board requires an external +J-Link programmer. The programmer is attached to the X1 SWD header. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52_adafruit_feather + :goals: build + :compact: + +#. Connect the Adafruit nRF52 Feather to your host computer using USB + +#. Run your favorite terminal program to listen for output. + + .. code-block:: console + + $ minicom -D -b 115200 + + Replace :code:`` with the port where the nRF52 Adafruit Feather + board can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52_adafruit_feather + :goals: flash + :compact: + + You should see "Hello World! nrf52_adafruit_feather" in your terminal. + + +Debugging +========= + +The ``nrf52_adafruit_feather`` board does not have an on-board J-Link debug IC +as some nRF5x development boards, however, instructions from the +:ref:`nordic_segger` page also apply to this board, with the additional step +of connecting an external debugger. + + +Testing the LEDs and buttons on the nRF52 Adafruit Feather +********************************************************** + +There are several samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +- :zephyr:code-sample:`blinky` +- :zephyr:code-sample:`button` +- :zephyr:code-sample:`fade-led` +- :zephyr:code-sample:`pwm-blinky` +- :zephyr:code-sample:`multi-thread-blinky` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/adafruit/nrf52_adafruit_feather/board.h`. + + +References +********** + +.. target-notes:: + +.. _Adafruit Feather nRF52 Bluefruit Learning Guide: https://learn.adafruit.com/bluefruit-nrf52-feather-learning-guide/introduction +.. _schematic: https://learn.adafruit.com/assets/39913 +.. _pinouts: https://cdn-learn.adafruit.com/assets/assets/000/046/210/original/Feather_NRF52_Pinout_v1.2.pdf?1504807075 +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _Adafruit Feather nRF52 Bluefruit LE: https://www.adafruit.com/product/3406 +.. _Adafruit Feather nRF52 Pro with myNewt Bootloader: https://www.adafruit.com/product/3574 +.. _Adafruit SWD connector: https://www.adafruit.com/product/752 diff --git a/boards/arm/nrf52_adafruit_feather/feather_connector.dtsi b/boards/adafruit/nrf52_adafruit_feather/feather_connector.dtsi similarity index 100% rename from boards/arm/nrf52_adafruit_feather/feather_connector.dtsi rename to boards/adafruit/nrf52_adafruit_feather/feather_connector.dtsi diff --git a/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather-pinctrl.dtsi b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather-pinctrl.dtsi rename to boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather-pinctrl.dtsi diff --git a/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather.dts b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts similarity index 100% rename from boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather.dts rename to boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts diff --git a/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml similarity index 100% rename from boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml rename to boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml diff --git a/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig new file mode 100644 index 00000000000..7167aca850a --- /dev/null +++ b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arduino_nano_33_ble/pre_dt_board.cmake b/boards/adafruit/nrf52_adafruit_feather/pre_dt_board.cmake similarity index 100% rename from boards/arm/arduino_nano_33_ble/pre_dt_board.cmake rename to boards/adafruit/nrf52_adafruit_feather/pre_dt_board.cmake diff --git a/boards/adafruit/qt_py_rp2040/Kconfig.adafruit_qt_py_rp2040 b/boards/adafruit/qt_py_rp2040/Kconfig.adafruit_qt_py_rp2040 new file mode 100644 index 00000000000..7cde06cb166 --- /dev/null +++ b/boards/adafruit/qt_py_rp2040/Kconfig.adafruit_qt_py_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Kelly Lord +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_QT_PY_RP2040 + select SOC_RP2040 diff --git a/boards/adafruit/qt_py_rp2040/Kconfig.defconfig b/boards/adafruit/qt_py_rp2040/Kconfig.defconfig new file mode 100644 index 00000000000..22d40318634 --- /dev/null +++ b/boards/adafruit/qt_py_rp2040/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_QT_PY_RP2040 + +config RP2_FLASH_W25Q080 + default y + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif #I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_ADAFRUIT_QT_PY_RP2040 diff --git a/boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi rename to boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi diff --git a/boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040.dts b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040.dts rename to boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts diff --git a/boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040.yaml b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.yaml similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040.yaml rename to boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.yaml diff --git a/boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040_defconfig b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040_defconfig similarity index 78% rename from boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040_defconfig rename to boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040_defconfig index d0987d6025f..f2202a534b6 100644 --- a/boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040_defconfig +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040_defconfig @@ -1,16 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_ADAFRUIT_QT_PY_RP2040=y - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 -# enable uart driver +# Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/adafruit_qt_py_rp2040/board.cmake b/boards/adafruit/qt_py_rp2040/board.cmake similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/board.cmake rename to boards/adafruit/qt_py_rp2040/board.cmake diff --git a/boards/adafruit/qt_py_rp2040/board.yml b/boards/adafruit/qt_py_rp2040/board.yml new file mode 100644 index 00000000000..e07cab669c6 --- /dev/null +++ b/boards/adafruit/qt_py_rp2040/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_qt_py_rp2040 + vendor: adafruit + socs: + - name: rp2040 diff --git a/boards/arm/adafruit_qt_py_rp2040/doc/img/qtpy_rp2040.jpg b/boards/adafruit/qt_py_rp2040/doc/img/qtpy_rp2040.jpg similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/doc/img/qtpy_rp2040.jpg rename to boards/adafruit/qt_py_rp2040/doc/img/qtpy_rp2040.jpg diff --git a/boards/arm/adafruit_qt_py_rp2040/doc/index.rst b/boards/adafruit/qt_py_rp2040/doc/index.rst similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/doc/index.rst rename to boards/adafruit/qt_py_rp2040/doc/index.rst diff --git a/boards/arm/adafruit_qt_py_rp2040/seeed_xiao_connector.dtsi b/boards/adafruit/qt_py_rp2040/seeed_xiao_connector.dtsi similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/seeed_xiao_connector.dtsi rename to boards/adafruit/qt_py_rp2040/seeed_xiao_connector.dtsi diff --git a/boards/adafruit/trinket_m0/Kconfig.adafruit_trinket_m0 b/boards/adafruit/trinket_m0/Kconfig.adafruit_trinket_m0 new file mode 100644 index 00000000000..3bb90153059 --- /dev/null +++ b/boards/adafruit/trinket_m0/Kconfig.adafruit_trinket_m0 @@ -0,0 +1,6 @@ +# Copyright (c) 2018 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_TRINKET_M0 + select SOC_SAMD21E18A diff --git a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0-pinctrl.dtsi b/boards/adafruit/trinket_m0/adafruit_trinket_m0-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_trinket_m0/adafruit_trinket_m0-pinctrl.dtsi rename to boards/adafruit/trinket_m0/adafruit_trinket_m0-pinctrl.dtsi diff --git a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.dts b/boards/adafruit/trinket_m0/adafruit_trinket_m0.dts similarity index 100% rename from boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.dts rename to boards/adafruit/trinket_m0/adafruit_trinket_m0.dts diff --git a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.yaml b/boards/adafruit/trinket_m0/adafruit_trinket_m0.yaml similarity index 100% rename from boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.yaml rename to boards/adafruit/trinket_m0/adafruit_trinket_m0.yaml diff --git a/boards/adafruit/trinket_m0/adafruit_trinket_m0_defconfig b/boards/adafruit/trinket_m0/adafruit_trinket_m0_defconfig new file mode 100644 index 00000000000..dcbfbd007df --- /dev/null +++ b/boards/adafruit/trinket_m0/adafruit_trinket_m0_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_OSC8M=y +CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y + +CONFIG_USE_DT_CODE_PARTITION=y +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/adafruit_trinket_m0/board.cmake b/boards/adafruit/trinket_m0/board.cmake similarity index 100% rename from boards/arm/adafruit_trinket_m0/board.cmake rename to boards/adafruit/trinket_m0/board.cmake diff --git a/boards/adafruit/trinket_m0/board.yml b/boards/adafruit/trinket_m0/board.yml new file mode 100644 index 00000000000..6d7a783ae3e --- /dev/null +++ b/boards/adafruit/trinket_m0/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_trinket_m0 + vendor: adafruit + socs: + - name: samd21e18a diff --git a/boards/arm/adafruit_trinket_m0/doc/img/adafruit_trinket_m0.jpg b/boards/adafruit/trinket_m0/doc/img/adafruit_trinket_m0.jpg similarity index 100% rename from boards/arm/adafruit_trinket_m0/doc/img/adafruit_trinket_m0.jpg rename to boards/adafruit/trinket_m0/doc/img/adafruit_trinket_m0.jpg diff --git a/boards/adafruit/trinket_m0/doc/index.rst b/boards/adafruit/trinket_m0/doc/index.rst new file mode 100644 index 00000000000..4e23822b242 --- /dev/null +++ b/boards/adafruit/trinket_m0/doc/index.rst @@ -0,0 +1,170 @@ +.. _adafruit_trinket_m0: + +Adafruit Trinket M0 +################### + +Overview +******** + +The Adafruit Trinket M0 is a tiny (27 mm x 15 mm) ARM development +board with an onboard RGB LED, USB port, and range of I/O broken out +onto 5 pins. + +.. image:: img/adafruit_trinket_m0.jpg + :align: center + :alt: Adafruit Trinket M0 + +Hardware +******** + +- ATSAMD21E18A ARM Cortex-M0+ processor at 48 MHz +- 256 KiB flash memory and 32 KiB of RAM +- Internal trimmed 8 MHz oscillator +- A user LED +- An RGB DotStar LED +- Native USB port +- One reset button + +Supported Features +================== + +The adafruit_trinket_m0 board configuration supports the following hardware +features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/adafruit/trinket_m0/adafruit_trinket_m0_defconfig`. + +Connections and IOs +=================== + +The `Adafruit Trinket M0 Learn site`_ has detailed information about +the board including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD21 MCU is configured to use the 8 MHz internal oscillator +with the on-chip PLL generating the 48 MHz system clock. The internal +APB and GCLK unit are set up in the same way as the upstream Arduino +libraries. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the Trinket, SERCOM0 is +the Zephyr console and is available on pins 3 (RX) and 4 (TX). +SERCOM2 is available on pins 2 (RX) and 0 (TX). + +PWM +=== + +The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the Trinket, SERCOM1 is +used to drive the DotStar RGB LED. SERCOM0 can be put into SPI mode +and used to connect to devices over pin 2 (MISO), pin 4 (MOSI), and +pin 3 (SCK). + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +Programming and Debugging +************************* + +The Trinket M0 ships the BOSSA compatible UF2 bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader +will be entered automatically when you run :code:`west flash`. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_trinket_m0 + :goals: build + :compact: + +#. Connect the Trinket M0 to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_trinket_m0 + :goals: flash + :compact: + + You should see "Hello World! adafruit_trinket_m0" in your terminal. + +References +********** + +.. target-notes:: + +.. _Adafruit Trinket M0 Learn site: + https://learn.adafruit.com/adafruit-trinket-m0-circuitpython-arduino + +.. _pinouts: + https://learn.adafruit.com/assets/49778 + +.. _schematic: + https://learn.adafruit.com/assets/45723 diff --git a/boards/arm/adafruit_trinket_m0/pre_dt_board.cmake b/boards/adafruit/trinket_m0/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_trinket_m0/pre_dt_board.cmake rename to boards/adafruit/trinket_m0/pre_dt_board.cmake diff --git a/boards/adi/eval_adin1110ebz/Kconfig.adi_eval_adin1110ebz b/boards/adi/eval_adin1110ebz/Kconfig.adi_eval_adin1110ebz new file mode 100644 index 00000000000..366fff3086b --- /dev/null +++ b/boards/adi/eval_adin1110ebz/Kconfig.adi_eval_adin1110ebz @@ -0,0 +1,5 @@ +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADI_EVAL_ADIN1110EBZ + select SOC_STM32L4S5XX diff --git a/boards/adi/eval_adin1110ebz/Kconfig.defconfig b/boards/adi/eval_adin1110ebz/Kconfig.defconfig new file mode 100644 index 00000000000..9c33c1d288d --- /dev/null +++ b/boards/adi/eval_adin1110ebz/Kconfig.defconfig @@ -0,0 +1,30 @@ +# ADI EVAL-ADIN1110EBZ board configuration + +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADI_EVAL_ADIN1110EBZ + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +config MDIO_INIT_PRIORITY + default 81 + depends on MDIO + +config PHY_INIT_PRIORITY + default 82 + depends on NET_L2_ETHERNET && ETH_DRIVER + +config MEMC + default y + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_ADI_EVAL_ADIN1110EBZ diff --git a/boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz.dts b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz.dts rename to boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts diff --git a/boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz.yaml b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz.yaml rename to boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml diff --git a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig new file mode 100644 index 00000000000..c19a47618d1 --- /dev/null +++ b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/adi_eval_adin1110ebz/arduino_r3_connector.dtsi b/boards/adi/eval_adin1110ebz/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/arduino_r3_connector.dtsi rename to boards/adi/eval_adin1110ebz/arduino_r3_connector.dtsi diff --git a/boards/arm/adi_eval_adin1110ebz/board.cmake b/boards/adi/eval_adin1110ebz/board.cmake similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/board.cmake rename to boards/adi/eval_adin1110ebz/board.cmake diff --git a/boards/adi/eval_adin1110ebz/board.yml b/boards/adi/eval_adin1110ebz/board.yml new file mode 100644 index 00000000000..e5af49e3f35 --- /dev/null +++ b/boards/adi/eval_adin1110ebz/board.yml @@ -0,0 +1,5 @@ +board: + name: adi_eval_adin1110ebz + vendor: adi + socs: + - name: stm32l4s5xx diff --git a/boards/arm/adi_eval_adin1110ebz/doc/img/adi_eval_adin1110ebz.webp b/boards/adi/eval_adin1110ebz/doc/img/adi_eval_adin1110ebz.webp similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/doc/img/adi_eval_adin1110ebz.webp rename to boards/adi/eval_adin1110ebz/doc/img/adi_eval_adin1110ebz.webp diff --git a/boards/adi/eval_adin1110ebz/doc/index.rst b/boards/adi/eval_adin1110ebz/doc/index.rst new file mode 100644 index 00000000000..92b70f0c1c0 --- /dev/null +++ b/boards/adi/eval_adin1110ebz/doc/index.rst @@ -0,0 +1,183 @@ +.. _adi_eval_adin1110ebz: + +ADI EVAL-ADIN1110EVB Evaluation board +##################################### + +Overview +******** + +The EVAL-ADIN1110EBZ is a flexible platform enabling quick evaluation of the ADIN1110, robust, +low power 10BASE-T1L MAC-PHY. It provides 10Mbit per second Single Pair Ethernet (SPE) connections +with devices across 1.7km of cable. + +The evaluation board offers two modes of operation for maximum flexibility. Connected to a PC +via USB port, the full set of ADIN1110 register settings and features such as link quality +monitoring and diagnostics can be accessed over the USB using serial command interface. +The board also provides an Arduino interface. + +Alternatively, the board can operate in stand-alone mode where it is configured by setting hardware +configuration links and switches. On-board LEDs provide status indication. + +The SPI interface provides configuration and data access to the ADIN1110. + +A small prototyping area and test points are provided for experimentation with alternative cable +connection topologies including isolation transformers and/or power coupling inductors. + +.. figure:: img/adi_eval_adin1110ebz.webp + :align: center + :alt: ADI EVAL-ADIN1110EBZ + + ADI EVAL-ADIN1110EBZ (Credit: Analog Devices, Inc.) + +.. important:: + + S201 DIP switches are shipped in Open Alliance SPI mode. The current Zephyr + default board configuration is set to work as "Generic SPI, CRC enabled", + so the S201 DIP switches must be set as ``SPI_CFG0 OFF`` and ``SPI_CFG1 ON``. + An inconsistent S201 DIP switches configuration will halt the boot. + +Hardware +******** + +The ADI EVAL-ADIN1110EBZ hardware features list is available here: + +https://wiki.analog.com/resources/eval/user-guides/eval-adin1110ebz-user-guide + + +Supported Features +================== + +The ADI adi_eval_adin1110ebz board configuration supports the +following hardware features: + ++--------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++==============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++--------------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++--------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++--------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++--------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++--------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++--------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++--------------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++--------------+------------+-------------------------------------+ +| ADIN1110 | spi | adin1110 10BASE-T1L mac/phy | ++--------------+------------+-------------------------------------+ +| FT232 | uart | usb-uart | ++--------------+------------+-------------------------------------+ +| ADT7422 | i2c | temperature sensor | ++--------------+------------+-------------------------------------+ +| ISS66WVE4M16 | fmc | 8MB PSRAM | ++--------------+------------+-------------------------------------+ + + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig` + + +Connections and IOs +=================== + +ADI ADIN1110EBZ evaluation board has 7 GPIO controllers (from A to G). These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +For mode details please refer to `EVAL-ADIN1110EBZ User Guide `_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (UART to FT232) +- UART_4 TX/RX : PA0/PA1 (Arduino Serial) +- I2C1 SCL/SDA : PG14/PG13 (Arduino I2C) +- I2C3 SCL/SDA : PG7/PG8 (Sensor I2C bus) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Simple SPI to nor Flash) +- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 (ADIN1110) +- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (Arduino SPI) +- LD1 : PC13 (Green LED) +- LD2 : PE2 (Red LED) +- LD3 : PE6 (Yellow LED) +- LD4 : PG15 (Blue LED) +- PSRAM : PE0/PE1/PF0-PF15/PG0-PG5/PD11-PD13/PE3/PE4 + PD14/PD15/PD9/PD1/PE7-PE15/PD8-PD10 + + +System Clock +------------ + +EVAL-ADIN1110EBZ System Clock could be driven by an internal or external oscillator, as well as +the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, driven by the +16MHz high speed internal oscillator. + +Serial Port +----------- + +EVAL-ADIN1110EBZ has 2 U(S)ARTs. The Zephyr console output is assigned to UART1 that is connected +to a FT232, so available through Micro USB connector. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +EVAL-ADIN1110EBZ includes an ST-LINK/V2-1 JTAG/SWD 10 or 20 pin connector. This interface is +supported by the openocd version included in Zephyr SDK. + +Flashing an application to Discovery kit +----------------------------------------- + +Connect the EVAL-ADIN1110EBZ to your host computer using the USB port, then run a serial host +program to connect with your ADI board. For example: + +.. code-block:: console + + $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN1110EBZ_AVAS_XXXXXX-if00-port0 + +where XXXXXX is the serial number of the connected device. +Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adi_eval_adin1110ebz + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! adi_eval_adin1110ebz + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adi_eval_adin1110ebz + :maybe-skip-config: + :goals: debug + +.. _EVAL-ADIN1110EBZ evaluation board website: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adin1110.html + +.. _EVAL-ADIN1110EBZ board User Guide: + https://wiki.analog.com/resources/eval/user-guides/eval-adin1110ebz-user-guide + +.. _ADIN1110 Datasheet: + https://www.analog.com/media/en/technical-documentation/data-sheets/adin1110.pdf + +.. _STM32L4S5QII3P reference manual: + https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/adi_eval_adin1110ebz/pre_dt_board.cmake b/boards/adi/eval_adin1110ebz/pre_dt_board.cmake similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/pre_dt_board.cmake rename to boards/adi/eval_adin1110ebz/pre_dt_board.cmake diff --git a/boards/arm/adi_eval_adin1110ebz/support/openocd.cfg b/boards/adi/eval_adin1110ebz/support/openocd.cfg similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/support/openocd.cfg rename to boards/adi/eval_adin1110ebz/support/openocd.cfg diff --git a/boards/adi/eval_adin2111ebz/Kconfig.adi_eval_adin2111ebz b/boards/adi/eval_adin2111ebz/Kconfig.adi_eval_adin2111ebz new file mode 100644 index 00000000000..9b051ece984 --- /dev/null +++ b/boards/adi/eval_adin2111ebz/Kconfig.adi_eval_adin2111ebz @@ -0,0 +1,5 @@ +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADI_EVAL_ADIN2111EBZ + select SOC_STM32L4S5XX diff --git a/boards/adi/eval_adin2111ebz/Kconfig.defconfig b/boards/adi/eval_adin2111ebz/Kconfig.defconfig new file mode 100644 index 00000000000..ae255907083 --- /dev/null +++ b/boards/adi/eval_adin2111ebz/Kconfig.defconfig @@ -0,0 +1,34 @@ +# ADI EVAL-ADIN2111EBZ board configuration + +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADI_EVAL_ADIN2111EBZ + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +config MDIO_INIT_PRIORITY + default 81 + depends on MDIO + +config PHY_INIT_PRIORITY + default 82 + depends on NET_L2_ETHERNET && ETH_DRIVER + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_ADIN2111 + +config NET_IF_MAX_IPV4_COUNT + default 2 + +endif # ETH_ADIN2111 + +endif # NETWORKING + +endif # BOARD_ADI_EVAL_ADIN2111EBZ diff --git a/boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz.dts b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz.dts rename to boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts diff --git a/boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz.yaml b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz.yaml rename to boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml diff --git a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig new file mode 100644 index 00000000000..c19a47618d1 --- /dev/null +++ b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/adi_eval_adin2111ebz/board.cmake b/boards/adi/eval_adin2111ebz/board.cmake similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/board.cmake rename to boards/adi/eval_adin2111ebz/board.cmake diff --git a/boards/adi/eval_adin2111ebz/board.yml b/boards/adi/eval_adin2111ebz/board.yml new file mode 100644 index 00000000000..0151d544aca --- /dev/null +++ b/boards/adi/eval_adin2111ebz/board.yml @@ -0,0 +1,5 @@ +board: + name: adi_eval_adin2111ebz + vendor: adi + socs: + - name: stm32l4s5xx diff --git a/boards/arm/adi_eval_adin2111ebz/doc/img/adi_eval_adin2111ebz.webp b/boards/adi/eval_adin2111ebz/doc/img/adi_eval_adin2111ebz.webp similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/doc/img/adi_eval_adin2111ebz.webp rename to boards/adi/eval_adin2111ebz/doc/img/adi_eval_adin2111ebz.webp diff --git a/boards/adi/eval_adin2111ebz/doc/index.rst b/boards/adi/eval_adin2111ebz/doc/index.rst new file mode 100644 index 00000000000..c88e6d520ed --- /dev/null +++ b/boards/adi/eval_adin2111ebz/doc/index.rst @@ -0,0 +1,184 @@ +.. _adi_eval_adin2111ebz: + +ADI EVAL-ADIN2111EVB Evaluation board +##################################### + +Overview +******** + +The EVAL-ADIN2111EBZ is a flexible platform enabling quick evaluation of the ADIN2111, robust, +low power 10BASE-T1L 2-Port Ethernet switch. The evaluation board provides 2 10BASE-T1L channels +with 10Mbit per second Single Pair Ethernet (SPE) connections reaching up to 1.7km of link distance. + +The ADIN2111 internal switch can be configured in store and forward mode between the two 10BASE-T1L +channels and the SPI host. Cut through mode is also available between Port 1 and Port 2 and can +be used without the need of the SPI host (unmanaged configuration). + +The evaluation board offers two modes of operation for maximum flexibility: Connected to a PC +via USB port, the full set of ADIN2111 register settings and features such as link quality +monitoring and diagnostics can be accessed over the USB using the serial command interface +implemented in the evaluation firmware. + +Alternatively, the board can operate in cut-through mode between Port 1 and Port 2 (unmanaged +configuration without firmware) where the EVAL-ADIN2111EBZ acts as a network switch forwarding +packets between the 2x 10BASE-T1L ports. The 2x links are configured by setting the ADIN2111 +hardware configuration pins jumper and switches. The 2x On-board Activity LEDs provide Link +activity status indication for each port. + +Custom firmware can also be developed and the ADIN2111 driver support package includes simple +project examples to start a custom implementation. + +The SPI interface provides access to the management registers required for the switch configuration, +the 2 PHYs configuration and data exchange between SPI host and ports. + +.. important:: + + S1 DIP switches are shipped in Open Alliance SPI mode. The current Zephyr + default board configuration is set to work as "Generic SPI, CRC enabled", + so the S1 DIP switches must be set as ``SPI_CFG0 OFF and SPI_CFG1 OFF``. + An inconsistent S1 DIP switches configuration will halt the boot. + +.. figure:: img/adi_eval_adin2111ebz.webp + :align: center + :alt: ADI EVAL-ADIN2111EBZ + + ADI EVAL-ADIN2111EBZ (Credit: Analog Devices, Inc.) + +Hardware +******** + +The ADI EVAL-ADIN2111EBZ hardware features list is available here: + +https://wiki.analog.com/resources/eval/user-guides/eval-adin2111ebz-user-guide + + +Supported Features +================== + +The ADI adi_eval_adin2111ebz board configuration supports the +following hardware features: + ++--------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++==============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++--------------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++--------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++--------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++--------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++--------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++--------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++--------------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++--------------+------------+-------------------------------------+ +| ADIN2111 | spi | adin2111 10BASE-T1L mac/phy | ++--------------+------------+-------------------------------------+ +| FT232 | uart | usb-uart | ++--------------+------------+-------------------------------------+ + + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig` + + +Connections and IOs +=================== + +ADI ADIN2111EBZ evaluation board has 7 GPIO controllers (from A to G). +These controllers are responsible for pin muxing, input/output, pull-up, etc. + +For mode details please refer to `EVAL-ADIN2111EBZ User Guide `_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (UART to FT232, console) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (SPI to external nor flash IS25LP128) +- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 (SPI to external ADIN2111) +- LED1 : POWER (Green LED) +- UC_LED1 : PB6 (Blue LED) +- MOD LED1 : PE2 (SR LED) +- MOD LED2 : PE6 (BG LED) +- NET LED1 : PB10 (SR LED) +- NET LED2 : PB11 (BG LED) + + +System Clock +------------ + +EVAL-ADIN2111EBZ System Clock could be driven by an internal or external oscillator, as well as the +main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, driven by the +16MHz high speed internal oscillator. + +Serial Port +----------- + +EVAL-ADIN2111EBZ has 1 U(S)ART. The Zephyr console output is assigned to UART1 that is connected +to a FT232, available through Micro USB connector. Default settings are 115200 8N1. +Same UART1 TX and RX cmos signals are available before the FT232, at P9 connector. + + +Programming and Debugging +************************* + +Flashing +======== + +EVAL-ADIN2111EBZ includes an ST-LINK/V2-1 JTAG/SWD 10 or 20 pin connector. This interface is +supported by the openocd version included in Zephyr SDK. + +Flashing an application to Discovery kit +----------------------------------------- + +Connect the EVAL-ADIN2111EBZ to your host computer using the USB port, then run a serial host +program to connect with your ADI board. For example: + +.. code-block:: console + + $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN2111EBZ_XXXXXX-12-if00-port0 + +where XXXXXX is the serial number of the connected device. +Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adi_eval_adin2111ebz + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! adi_eval_adin2111ebz + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adi_eval_adin2111ebz + :maybe-skip-config: + :goals: debug + +.. _EVAL-ADIN2111EBZ evaluation board website: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adin2111.html + +.. _EVAL-ADIN2111EBZ board User Guide: + https://wiki.analog.com/resources/eval/user-guides/eval-adin2111ebz-user-guide + +.. _ADIN2111 Datasheet: + https://www.analog.com/media/en/technical-documentation/data-sheets/adin2111.pdf + +.. _STM32L4S5QII3P reference manual: + https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/adi_eval_adin2111ebz/pre_dt_board.cmake b/boards/adi/eval_adin2111ebz/pre_dt_board.cmake similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/pre_dt_board.cmake rename to boards/adi/eval_adin2111ebz/pre_dt_board.cmake diff --git a/boards/arm/adi_eval_adin2111ebz/support/openocd.cfg b/boards/adi/eval_adin2111ebz/support/openocd.cfg similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/support/openocd.cfg rename to boards/adi/eval_adin2111ebz/support/openocd.cfg diff --git a/boards/adi/index.rst b/boards/adi/index.rst new file mode 100644 index 00000000000..1627e65cb70 --- /dev/null +++ b/boards/adi/index.rst @@ -0,0 +1,10 @@ +.. _boards-adi: + +Analog Devices, Inc. +#################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/adi/sdp_k1/Kconfig.adi_sdp_k1 b/boards/adi/sdp_k1/Kconfig.adi_sdp_k1 new file mode 100644 index 00000000000..b48600e49fb --- /dev/null +++ b/boards/adi/sdp_k1/Kconfig.adi_sdp_k1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADI_SDP_K1 + select SOC_STM32F469XX diff --git a/boards/adi/sdp_k1/Kconfig.defconfig b/boards/adi/sdp_k1/Kconfig.defconfig new file mode 100644 index 00000000000..22cac53aa50 --- /dev/null +++ b/boards/adi/sdp_k1/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ADI SDP-K1 board configuration + +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADI_SDP_K1 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_ADI_SDP_K1 diff --git a/boards/arm/adi_sdp_k1/adi_sdp_k1.dts b/boards/adi/sdp_k1/adi_sdp_k1.dts similarity index 100% rename from boards/arm/adi_sdp_k1/adi_sdp_k1.dts rename to boards/adi/sdp_k1/adi_sdp_k1.dts diff --git a/boards/arm/adi_sdp_k1/adi_sdp_k1.yaml b/boards/adi/sdp_k1/adi_sdp_k1.yaml similarity index 100% rename from boards/arm/adi_sdp_k1/adi_sdp_k1.yaml rename to boards/adi/sdp_k1/adi_sdp_k1.yaml diff --git a/boards/arm/adi_sdp_k1/adi_sdp_k1_defconfig b/boards/adi/sdp_k1/adi_sdp_k1_defconfig similarity index 84% rename from boards/arm/adi_sdp_k1/adi_sdp_k1_defconfig rename to boards/adi/sdp_k1/adi_sdp_k1_defconfig index 94a8f52809e..c729b83e3d0 100644 --- a/boards/arm/adi_sdp_k1/adi_sdp_k1_defconfig +++ b/boards/adi/sdp_k1/adi_sdp_k1_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F469XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/adi_sdp_k1/arduino_r3_connector.dtsi b/boards/adi/sdp_k1/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/adi_sdp_k1/arduino_r3_connector.dtsi rename to boards/adi/sdp_k1/arduino_r3_connector.dtsi diff --git a/boards/arm/adi_sdp_k1/board.cmake b/boards/adi/sdp_k1/board.cmake similarity index 100% rename from boards/arm/adi_sdp_k1/board.cmake rename to boards/adi/sdp_k1/board.cmake diff --git a/boards/adi/sdp_k1/board.yml b/boards/adi/sdp_k1/board.yml new file mode 100644 index 00000000000..c659c3b14c8 --- /dev/null +++ b/boards/adi/sdp_k1/board.yml @@ -0,0 +1,5 @@ +board: + name: adi_sdp_k1 + vendor: adi + socs: + - name: stm32f469xx diff --git a/boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1.webp b/boards/adi/sdp_k1/doc/img/adi_sdp_k1.webp similarity index 100% rename from boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1.webp rename to boards/adi/sdp_k1/doc/img/adi_sdp_k1.webp diff --git a/boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1_120pin.webp b/boards/adi/sdp_k1/doc/img/adi_sdp_k1_120pin.webp similarity index 100% rename from boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1_120pin.webp rename to boards/adi/sdp_k1/doc/img/adi_sdp_k1_120pin.webp diff --git a/boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1_arduino.webp b/boards/adi/sdp_k1/doc/img/adi_sdp_k1_arduino.webp similarity index 100% rename from boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1_arduino.webp rename to boards/adi/sdp_k1/doc/img/adi_sdp_k1_arduino.webp diff --git a/boards/adi/sdp_k1/doc/index.rst b/boards/adi/sdp_k1/doc/index.rst new file mode 100644 index 00000000000..1f6f918e0a6 --- /dev/null +++ b/boards/adi/sdp_k1/doc/index.rst @@ -0,0 +1,183 @@ +.. _adi_sdp_k1: + +ADI SDP-K1 +########## + +Overview +******** + +The EVAL-SDP-CK1Z (SDP-K1) controller board is a system demonstration platform +(SDP) from Analog Devices designed to connect to evaluation shields containing +ADI components. + +- STM32 microcontroller in BGA216 package +- USB 2.0 device with USB-C connector +- USB debug interface supporting CMSIS-DAP through a NXP Freescale + microcontroller +- Flexible board power supply + - USB VBUS 5 V max. 500 mA + - 5.5mm DC power jack 7 - 12 V min. 300 mA + - VIN from Arduino* compatible connectors + - VIN from 120-pin connector 5 V min. 300 mA +- 3 color LEDs (green, orange, red) and 1 status LED +- One push-buttons: RESET +- 16MB SDRAM +- Arduino UNO and 120-pin SDP connectors + +.. figure:: img/adi_sdp_k1.webp + :align: center + :alt: ADI SDP-K1 + + ADI SDP-K1 (Credit: Analog Devices, Inc.) + +More information about the board can be found on the `ADI SDP-K1 website`_. + +Hardware +******** + +ADI SDP-K1 provides the following hardware components: + +- STM32F469NIH6 in BGA216 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 180 MHz max CPU frequency +- VDD of 1.8 V or 3.3 V +- 2 MB Flash +- 384 KB SRAM +- GPIO with external interrupt capability +- LCD parallel interface, 8080/6800 modes +- LCD TFT controller supporting up to XGA resolution +- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (8) +- I2C (3) +- SPI (6) +- 1xSAI (serial audio interface) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F469NI can be found here: + - `STM32F469NI product page`_ + - `STM32F469 reference manual`_ + +Supported Features +================== + +The Zephyr stm32f469i_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/adi/sdp_k1/adi_sdp_k1_defconfig` + +Pin Mapping +=========== + +For more details please refer to `EVAL-SDP-CK1Z User Guide`_. + +Arduino UNO headers +------------------- + +.. figure:: img/adi_sdp_k1_arduino.webp + :align: center + :alt: ADI SDP-K1 Arduino UNO headers pinout + + ADI SDP-K1 (Credit: Analog Devices, Inc.) + +120-pin SDP connector +--------------------- + +.. figure:: img/adi_sdp_k1_120pin.webp + :align: center + :alt: ADI SDP-K1 120-pin SDP connector pinout + + ADI SDP-K1 (Credit: Analog Devices, Inc.) + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_5 TX/RX : P2 (DAPLink USB-C) +- UART_5 TX/RX : P8 (DAPLink two position through hole) +- LED1 : DS6 (Red) +- LED2 : DS5 (Orange) +- LED3 : DS4 (Green) +- LED4 : DS4 (Status) + +Programming and Debugging +************************* + +The ADI SDP-K1 be programmed over USB using the DAPLink firmware running on an +embedded NXP Freescale microcontroller or a 10-pin ``DEBUG`` header connected +to a STLINK debugger. + +DAPLink exposes a storage device, as well as USB HID and CDC Endpoints, to the +host. For more details please refer to the `Official DAPLink website`_. + +Flashing +======== + +Flashing an application with a STLINK debugger +---------------------------------------------- + +First, connect the STLINK debugger to your host computer using the Micro-USB port. +Then attach the debugger to the 10-pin ``DEBUG`` header on the SDP-K1. Finally +connect the SDP-K1 to your host computer using the USB-C port. + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/serial/by-id/usb-ARM_DAPLink_CMSIS-DAP_<...> + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adi_sdp_k1 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! adi_sdp_k1 + +Debugging +========= + +.. _ADI SDP-K1 website: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/sdp-k1.html + +.. _EVAL-SDP-CK1Z User Guide: + https://www.analog.com/media/en/technical-documentation/user-guides/EVAL-SDP-CK1Z-UG-1539.pdf + +.. _STM32F469NI product page: + https://www.st.com/en/microcontrollers/stm32f469ni.html + +.. _STM32F469 reference manual: + https://www.st.com/resource/en/reference_manual/dm00127514.pdf + +.. _Official DAPLink website: + https://daplink.io/ diff --git a/boards/arm/adi_sdp_k1/revision.cmake b/boards/adi/sdp_k1/revision.cmake similarity index 100% rename from boards/arm/adi_sdp_k1/revision.cmake rename to boards/adi/sdp_k1/revision.cmake diff --git a/boards/arm/adi_sdp_k1/support/openocd.cfg b/boards/adi/sdp_k1/support/openocd.cfg similarity index 100% rename from boards/arm/adi_sdp_k1/support/openocd.cfg rename to boards/adi/sdp_k1/support/openocd.cfg diff --git a/boards/alientek/index.rst b/boards/alientek/index.rst new file mode 100644 index 00000000000..f124ce93459 --- /dev/null +++ b/boards/alientek/index.rst @@ -0,0 +1,10 @@ +.. _boards-alientek: + +Alientek +######## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/alientek/pandora_stm32l475/Kconfig.pandora_stm32l475 b/boards/alientek/pandora_stm32l475/Kconfig.pandora_stm32l475 new file mode 100644 index 00000000000..1d42c17a83d --- /dev/null +++ b/boards/alientek/pandora_stm32l475/Kconfig.pandora_stm32l475 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Tisilicon +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PANDORA_STM32L475 + select SOC_STM32L475XX diff --git a/boards/arm/pandora_stm32l475/board.cmake b/boards/alientek/pandora_stm32l475/board.cmake similarity index 100% rename from boards/arm/pandora_stm32l475/board.cmake rename to boards/alientek/pandora_stm32l475/board.cmake diff --git a/boards/alientek/pandora_stm32l475/board.yml b/boards/alientek/pandora_stm32l475/board.yml new file mode 100644 index 00000000000..725d13c5f30 --- /dev/null +++ b/boards/alientek/pandora_stm32l475/board.yml @@ -0,0 +1,5 @@ +board: + name: pandora_stm32l475 + vendor: alientek + socs: + - name: stm32l475xx diff --git a/boards/arm/pandora_stm32l475/doc/img/pandora_stm32l475.jpg b/boards/alientek/pandora_stm32l475/doc/img/pandora_stm32l475.jpg similarity index 100% rename from boards/arm/pandora_stm32l475/doc/img/pandora_stm32l475.jpg rename to boards/alientek/pandora_stm32l475/doc/img/pandora_stm32l475.jpg diff --git a/boards/alientek/pandora_stm32l475/doc/index.rst b/boards/alientek/pandora_stm32l475/doc/index.rst new file mode 100644 index 00000000000..cee292e1e56 --- /dev/null +++ b/boards/alientek/pandora_stm32l475/doc/index.rst @@ -0,0 +1,214 @@ +.. _pandora_stm32l475_board: + +Alientek STM32L475 Pandora +########################## + +Overview +******** + +The STM32L475 Pandora board features an ARM Cortex-M4 based STM32L475VE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the STM32L475 Pandora board: + + +- STM32L475Vx microcontroller featuring 1 Mbyte of Flash memory, 128 Kbytes of RAM in LQFP100 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- Three different interfaces supported on USB: + + - Virtual com port + - Mass storage + - Debug port + +- Pushbutton (reset) +- Four directions Joystick with selection +- USB OTG FS with micro-AB connector +- SAI Audio DAC, Stereo with output jack +- Digital microphone, accelerometer, magnetometer and gyroscope MEMS +- 128-Mbit Quad-SPI Flash memory +- MCU current ammeter with 4 ranges and auto-calibration +- Connector for external board or RF-EEPROM +- Four power supply options: + - ST-LINK/V2-1 + - USB FS connector + - External 5 V + - CR2032 battery (not provided) + +.. image:: img/pandora_stm32l475.jpg + :align: center + :alt: STM32L475 Pandora + +More information about the board can be found at the `STM32L475 Pandora website`_. + +Hardware +******** + +The STM32L475VE SoC provides the following hardware features: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC +- RTC with HW calendar, alarms and calibration +- 16x timers: + - 2x 16-bit advanced motor-control + - 2x 32-bit and 7x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer +- Up to 82 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 128 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators +- 18x communication interfaces + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +Supported Features +================== + +The Zephyr stm32l475ve_pandora board configuration supports the following hardware features: + ++-----------+------------+----------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==============================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+----------------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+----------------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+----------------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------------------------------+ +| I2C | on-chip | I2C-AHT10(Temperature and humidity sensor) | +| | | I2C-ICM2068(light environment sensor) | ++-----------+------------+----------------------------------------------+ +| I2S | on-chip | I2S-ES8388(Audio Decoder) | ++-----------+------------+----------------------------------------------+ +| USB | on-chip | I2S-OTG | ++-----------+------------+----------------------------------------------+ +| SDIO | on-chip | SDIO-AP6181(WIFI) | ++-----------+------------+----------------------------------------------+ +| SPI | on-chip | LCD-TFT | ++-----------+------------+----------------------------------------------+ +| QSPI NOR | on-chip | flash | ++-----------+------------+----------------------------------------------+ +| IR-RX/TX | on-board | Infrared Receiver(38Khz)/Transmitter | ++-----------+------------+----------------------------------------------+ +| STLINK-V2 | on-board | STLINK-V2 Debugger | ++-----------+------------+----------------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig` + + +Connections and IOs +=================== + +STM32L475 Pandora Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32L475 Pandora board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- LED_R : PE7 +- LED_G : PE8 +- LED_B : PE9 + +System Clock +------------ + +STM32L475 Pandora System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +STM32L475 Pandora board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +STM32L475 Pandora board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32L475 Pandora +-------------------------------------------- + +Connect the STM32L475 Pandora to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l475ve_pandora + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l475ve_pandora + :maybe-skip-config: + :goals: debug + +.. _STM32L475 Pandora website: + http://www.openedv.com/docs/boards/iot/zdyz_panduola.html + +.. _STM32L475 Pandora board User Manual: + http://www.openedv.com/thread-284556-1-1.html diff --git a/boards/arm/pandora_stm32l475/pandora_stm32l475.dts b/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts similarity index 100% rename from boards/arm/pandora_stm32l475/pandora_stm32l475.dts rename to boards/alientek/pandora_stm32l475/pandora_stm32l475.dts diff --git a/boards/arm/pandora_stm32l475/pandora_stm32l475.yaml b/boards/alientek/pandora_stm32l475/pandora_stm32l475.yaml similarity index 100% rename from boards/arm/pandora_stm32l475/pandora_stm32l475.yaml rename to boards/alientek/pandora_stm32l475/pandora_stm32l475.yaml diff --git a/boards/arm/pandora_stm32l475/pandora_stm32l475_defconfig b/boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig similarity index 85% rename from boards/arm/pandora_stm32l475/pandora_stm32l475_defconfig rename to boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig index 6b76862a311..82ee7285d52 100644 --- a/boards/arm/pandora_stm32l475/pandora_stm32l475_defconfig +++ b/boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L475XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/pandora_stm32l475/support/openocd.cfg b/boards/alientek/pandora_stm32l475/support/openocd.cfg similarity index 100% rename from boards/arm/pandora_stm32l475/support/openocd.cfg rename to boards/alientek/pandora_stm32l475/support/openocd.cfg diff --git a/boards/altr/index.rst b/boards/altr/index.rst new file mode 100644 index 00000000000..83220f8c905 --- /dev/null +++ b/boards/altr/index.rst @@ -0,0 +1,10 @@ +.. _boards-altera: + +Altera Corporation +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/altr/max10/Kconfig.altera_max10 b/boards/altr/max10/Kconfig.altera_max10 new file mode 100644 index 00000000000..b0b39da8448 --- /dev/null +++ b/boards/altr/max10/Kconfig.altera_max10 @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel + +config BOARD_ALTERA_MAX10 + select SOC_ZEPHYR_NIOS2F diff --git a/boards/altr/max10/Kconfig.defconfig b/boards/altr/max10/Kconfig.defconfig new file mode 100644 index 00000000000..d0617d44c33 --- /dev/null +++ b/boards/altr/max10/Kconfig.defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel + +if BOARD_ALTERA_MAX10 + +if FLASH + +config SOC_FLASH_NIOS2_QSPI + default y + +endif # FLASH + +endif # BOARD_ALTERA_MAX10 diff --git a/boards/nios2/altera_max10/altera_max10.dts b/boards/altr/max10/altera_max10.dts similarity index 95% rename from boards/nios2/altera_max10/altera_max10.dts rename to boards/altr/max10/altera_max10.dts index 9b258bda273..30c7e442505 100644 --- a/boards/nios2/altera_max10/altera_max10.dts +++ b/boards/altr/max10/altera_max10.dts @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright (c) 2018 Intel */ /dts-v1/; diff --git a/boards/nios2/altera_max10/altera_max10.yaml b/boards/altr/max10/altera_max10.yaml similarity index 100% rename from boards/nios2/altera_max10/altera_max10.yaml rename to boards/altr/max10/altera_max10.yaml diff --git a/boards/altr/max10/altera_max10_defconfig b/boards/altr/max10/altera_max10_defconfig new file mode 100644 index 00000000000..ac9a2e96e4d --- /dev/null +++ b/boards/altr/max10/altera_max10_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel + +CONFIG_HAS_ALTERA_HAL=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nios2/altera_max10/board.cmake b/boards/altr/max10/board.cmake similarity index 100% rename from boards/nios2/altera_max10/board.cmake rename to boards/altr/max10/board.cmake diff --git a/boards/altr/max10/board.yml b/boards/altr/max10/board.yml new file mode 100644 index 00000000000..976a0f83a80 --- /dev/null +++ b/boards/altr/max10/board.yml @@ -0,0 +1,5 @@ +board: + name: altera_max10 + vendor: altr + socs: + - name: zephyr_nios2f diff --git a/boards/nios2/altera_max10/doc/img/Altera_MAX10_switches.jpg b/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg similarity index 100% rename from boards/nios2/altera_max10/doc/img/Altera_MAX10_switches.jpg rename to boards/altr/max10/doc/img/Altera_MAX10_switches.jpg diff --git a/boards/nios2/altera_max10/doc/img/altera_max10.jpg b/boards/altr/max10/doc/img/altera_max10.jpg similarity index 100% rename from boards/nios2/altera_max10/doc/img/altera_max10.jpg rename to boards/altr/max10/doc/img/altera_max10.jpg diff --git a/boards/altr/max10/doc/index.rst b/boards/altr/max10/doc/index.rst new file mode 100644 index 00000000000..64d7f14257f --- /dev/null +++ b/boards/altr/max10/doc/index.rst @@ -0,0 +1,332 @@ +.. _altera_max10: + +Altera MAX10 +############ + +Overview +******** + + +The Zephyr kernel is supported on the Altera MAX10 Rev C development kit, using +the Nios II Gen 2 soft CPU. + +.. figure:: img/altera_max10.jpg + :align: center + :alt: Altera's MAX* 10 + + Altera's MAX* 10 (Credit: Altera) + +Hardware +******** + +DIP Switch settings +=================== + +There are two sets of switches on the back of the board. Of particular +importance is SW2: + +* Switch 2 (CONFIG_SEL) should be in the OFF (up) position so that the first + boot image is CFM0 +* Switch 3 (VTAP_BYPASS) needs to be in the ON (down) position or the flashing + scripts won't work +* Switch 4 (HSMC_BYPASSN) should be OFF (up) + +.. image:: img/Altera_MAX10_switches.jpg + :align: center + :alt: Altera's MAX* 10 Switches + +Other switches are user switches, their position is application-specific. + +Necessary Software +================== + +You will need the Altera Quartus SDK in order to work with this device. The +`Altera Lite Distribution`_ of Quartus may be obtained without +charge. + +For your convenience using the SDK tools (such as ``nios2-configure-sof``), +you should put the binaries provided by the SDK +in your path. Below is an example, adjust ALTERA_BASE to where you installed the +SDK: + +.. code-block:: console + + export ALTERA_BASE=/opt/altera_lite/16.0 + export PATH=$PATH:$ALTERA_BASE/quartus/bin:$ALTERA_BASE/nios2eds/bin + +You may need to adjust your udev rules so that you can talk to the USB Blaster +II peripheral, which is the built-in JTAG interface for this device. + +The following works for Fedora 23: + +.. code-block:: console + + # For Altera USB-Blaster permissions. + SUBSYSTEM=="usb",\ + ENV{DEVTYPE}=="usb_device",\ + ATTR{idVendor}=="09fb",\ + ATTR{idProduct}=="6010",\ + MODE="0666",\ + NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ + RUN+="/bin/chmod 0666 %c" + SUBSYSTEM=="usb",\ + ENV{DEVTYPE}=="usb_device",\ + ATTR{idVendor}=="09fb",\ + ATTR{idProduct}=="6810",\ + MODE="0666",\ + NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ + RUN+="/bin/chmod 0666 %c" + +You can test connectivity with the SDK jtagconfig tool, you should see something +like: + +.. code-block:: console + + $ jtagconfig + 1) USB-BlasterII [1-1.2] + 031050DD 10M50DA(.|ES)/10M50DC + 020D10DD VTAP10 + + +Reference CPU +============= + +A reference CPU design of a Nios II/f core is included in the Zephyr tree +in the :zephyr_file:`soc/altera/zephyr_nios2f/cpu` directory. + +Flash this CPU using the ``nios2-configure-sof`` SDK tool with the FPGA +configuration file +:zephyr_file:`soc/altera/zephyr_nios2f/cpu/ghrd_10m50da.sof`: + +.. code-block:: console + + $ nios2-configure-sof ghrd_10m50da.sof + +This CPU is a Nios II/F core with a 16550 UART, JTAG UART, and the Avalon Timer. +For any Nios II SOC definition, you can find out more details about the CPU +configuration by inspecting system.h in the SOC's include directory. + +Console Output +============== + +16550 UART +---------- + +By default, the kernel is configured to send console output to the 16550 UART. +You can monitor this on your workstation by connecting to the top right mini USB +port on the board (it will show up in /dev as a ttyUSB node), and then running +minicom with flow control disabled, 115200-8N1 settings. + +JTAG UART +--------- + +You can also have it send its console output to the JTAG UART. +Enable ``jtag_uart`` node in :file:`altera_max10.dts` or overlay file: + +.. code-block:: devicetree + + &jtag_uart { + status = "okay"; + current-speed = <115200>; + }; + +To view these messages on your local workstation, run the terminal application +in the SDK: + +.. code-block:: console + + $ nios2-terminal + +Programming and Debugging +************************* + +Flashing +======== + +Flashing Kernel into UFM +------------------------ + +The usual ``flash`` target will work with the ``altera_max10`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: altera_max10 + :goals: flash + +Refer to :ref:`build_an_application` and :ref:`application_run` for +more details. + +This provisions the Zephyr kernel and the CPU configuration onto the board, +using the scripts/support/quartus-flash.py script. After it completes the kernel +will immediately boot. + + +Flashing Kernel directly into RAM over JTAG +------------------------------------------- + +The SDK included the nios2-download tool which will let you flash a kernel +directly into RAM and then boot it from the __start symbol. + +In order for this to work, your entire kernel must be located in RAM. Make sure +the following config options are disabled: + +.. code-block:: console + + CONFIG_XIP=n + CONFIG_INCLUDE_RESET_VECTOR=n + +Then, after building your kernel, push it into device's RAM by running +this from the build directory: + +.. code-block:: console + + $ nios2-download --go zephyr/zephyr.elf + +If you have a console session running (either minicom or nios2-terminal) you +should see the application's output. There are additional arguments you can pass +to nios2-download so that it spawns a GDB server that you can connect to, +although it's typically simpler to just use nios2-gdb-server as described below. + +Debugging +========= + +The Altera SDK includes a GDB server which can be used to debug a MAX10 board. +You can either debug a running image that was flashed onto the device in User +Flash Memory (UFM), or load an image over the JTAG using GDB. + +Debugging With UFM Flashed Image +-------------------------------- + +You can debug an application in the usual way. Here is an example. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: altera_max10 + :goals: debug + +You will see output similar to the following: + +.. code-block:: console + + Nios II GDB server running on port 3335 + Ignoring --stop option because --tcpport also specified + GNU gdb (GDB) 7.11.0.20160511-git + Copyright (C) 2016 Free Software Foundation, Inc. + License GPLv3+: GNU GPL version 3 or later + This is free software: you are free to change and redistribute it. + There is NO WARRANTY, to the extent permitted by law. Type "show copying" + and "show warranty" for details. + This GDB was configured as "--host=x86_64-pokysdk-linux --target=nios2-zephyr-elf". + Type "show configuration" for configuration details. + For bug reporting instructions, please see: + . + Find the GDB manual and other documentation resources online at: + . + For help, type "help". + Type "apropos word" to search for commands related to "word"... + Reading symbols from /projects/zephyr/samples/hello_world/build/zephyr/zephyr.elf...done. + Remote debugging using :3335 + Using cable "USB-BlasterII [3-1.3]", device 1, instance 0x00 + Resetting and pausing target processor: OK + Listening on port 3335 for connection from GDB: accepted + isr_tables_syms () at /projects/zephyr/arch/common/isr_tables.c:63 + 63 GEN_ABSOLUTE_SYM(__ISR_LIST_SIZEOF, sizeof(struct _isr_list)); + (gdb) b z_prep_c + Breakpoint 1 at 0xdf0: file /projects/zephyr/arch/nios2/core/prep_c.c, line 36. + (gdb) b z_cstart + Breakpoint 2 at 0x1254: file /projects/zephyr/kernel/init.c, line 348. + (gdb) c + Continuing. + + Breakpoint 2, z_cstart () at /projects/zephyr/kernel/init.c:348 + 348 { + (gdb) + +To start debugging manually: + + +.. code-block:: console + + nios2-gdb-server --tcpport 1234 --stop --reset-target + +And then connect with GDB from the build directory: + + +.. code-block:: console + + nios2-poky-elf-gdb zephyr/zephyr.elf -ex "target remote :1234" + +Debugging With JTAG Flashed Image +--------------------------------- + +In order for this to work, execute-in-place must be disabled, since the GDB +'load' command can only put text and data in RAM. Ensure this is in your +configuration: + +.. code-block:: console + + CONFIG_XIP=n + +It is OK for this procedure to leave the reset vector enabled, unlike +nios2-download (which errors out if it finds sections outside of SRAM) it will +be ignored. + +In a terminal, launch the nios2 GDB server. It doesn't matter what kernel (if +any) is on the device, but you should have at least flashed a CPU using +nios2-configure-sof. You can leave this process running. + +.. code-block:: console + + $ nios2-gdb-server --tcpport 1234 --tcppersist --init-cache --reset-target + +Build your Zephyr kernel, and load it into a GDB built for Nios II (included in +the Zephyr SDK) from the build directory: + +.. code-block:: console + + $ nios2-poky-elf-gdb zephyr/zephyr.elf + +Then connect to the GDB server: + +.. code-block:: console + + (gdb) target remote :1234 + +And then load the kernel image over the wire. The CPU will not start from the +reset vector, instead it will boot from the __start symbol: + + +.. code-block:: console + + (gdb) load + Loading section reset, size 0xc lma 0x0 + Loading section exceptions, size 0x1b0 lma 0x400020 + Loading section text, size 0x8df0 lma 0x4001d0 + Loading section devconfig, size 0x30 lma 0x408fc0 + Loading section rodata, size 0x3f4 lma 0x408ff0 + Loading section datas, size 0x888 lma 0x4093e4 + Loading section initlevel, size 0x30 lma 0x409c6c + Loading section _k_task_list, size 0x58 lma 0x409c9c + Loading section _k_task_ptr, size 0x8 lma 0x409cf4 + Loading section _k_event_list, size 0x10 lma 0x409cfc + Start address 0x408f54, load size 40184 + Transfer rate: 417 KB/sec, 368 bytes/write. + After this is done you may set breakpoints and continue execution. If you ever want to reset the CPU, issue the 'load' command again. + + + +References +********** + +* `CPU Documentation `_ +* `Nios II Processor Booting Methods in MAX 10 FPGA Devices `_ +* `Embedded Peripherals IP User Guide `_ +* `MAX 10 FPGA Configuration User Guide `_ +* `MAX 10 FPGA Development Kit User Guide `_ +* `Nios II Command-Line Tools `_ +* `Quartus II Scripting Reference Manual `_ + + +.. _Altera Lite Distribution: https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.apollo4p_blue_kxr_evb b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.apollo4p_blue_kxr_evb new file mode 100644 index 00000000000..09de003fc14 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.apollo4p_blue_kxr_evb @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Ambiq Micro Inc. + +config BOARD_APOLLO4P_BLUE_KXR_EVB + select SOC_APOLLO4P_BLUE diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig new file mode 100644 index 00000000000..87e1c5a8764 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Ambiq Micro Inc. + +if BOARD_APOLLO4P_BLUE_KXR_EVB + +if BT + +config MAIN_STACK_SIZE + default 2048 + +choice BT_HCI_BUS_TYPE + default BT_AMBIQ_HCI +endchoice + +config BT_BUF_ACL_TX_COUNT + default 14 + +config BT_BUF_CMD_TX_SIZE + default 255 + +config BT_BUF_EVT_RX_SIZE + default 255 + +config BT_BUF_ACL_TX_SIZE + default 251 + +config BT_BUF_ACL_RX_SIZE + default 251 + +# L2CAP SDU/PDU TX MTU +# BT_L2CAP_RX_MTU = CONFIG_BT_BUF_ACL_RX_SIZE - BT_L2CAP_HDR_SIZE +config BT_L2CAP_TX_MTU + default 247 + +endif # BT + +endif # BOARD_APOLLO4P_BLUE_KXR_EVB diff --git a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi rename to boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi diff --git a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts similarity index 100% rename from boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts rename to boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts diff --git a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml similarity index 100% rename from boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml rename to boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml diff --git a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig similarity index 76% rename from boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig rename to boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig index 4c940d417fd..5f556803e52 100644 --- a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig @@ -2,8 +2,6 @@ # # Copyright (c) 2023 Ambiq Micro Inc. -CONFIG_SOC_SERIES_APOLLO4X=y -CONFIG_SOC_APOLLO4P_BLUE=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/apollo4p_blue_kxr_evb/board.cmake b/boards/ambiq/apollo4p_blue_kxr_evb/board.cmake similarity index 100% rename from boards/arm/apollo4p_blue_kxr_evb/board.cmake rename to boards/ambiq/apollo4p_blue_kxr_evb/board.cmake diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/board.yml b/boards/ambiq/apollo4p_blue_kxr_evb/board.yml new file mode 100644 index 00000000000..16a9a6cc979 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kxr_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: apollo4p_blue_kxr_evb + vendor: ambiq + socs: + - name: apollo4p_blue diff --git a/boards/arm/apollo4p_blue_kxr_evb/doc/apollo4-blue-plus-kxr-soc-eval-board.jpg b/boards/ambiq/apollo4p_blue_kxr_evb/doc/apollo4-blue-plus-kxr-soc-eval-board.jpg similarity index 100% rename from boards/arm/apollo4p_blue_kxr_evb/doc/apollo4-blue-plus-kxr-soc-eval-board.jpg rename to boards/ambiq/apollo4p_blue_kxr_evb/doc/apollo4-blue-plus-kxr-soc-eval-board.jpg diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst new file mode 100644 index 00000000000..214b5d4c2ef --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst @@ -0,0 +1,110 @@ +.. _apollo4p_blue_kxr_evb: + +Ambiq Apollo4 Blue Plus KXR EVB +############################### + +Apollo4 Blue Plus KXR EVB is a board by Ambiq featuring their ultra-low power Apollo4 Blue Plus SoC. + +.. image:: ./apollo4-blue-plus-kxr-soc-eval-board.jpg + :align: center + :alt: Apollo4 Blue Plus KXR EVB + +Hardware +******** + +- Apollo4 Blue Plus SoC with upto 192 MHz operating frequency +- ARM® Cortex® M4F core +- 64 kB 2-way Associative/Direct-Mapped Cache per core +- Up to 2 MB of non-volatile memory (NVM) for code/data +- Up to 2.75 MB of low leakage / low power RAM for code/data +- 384 kB Tightly Coupled RAM +- 384 kB Extended RAM +- Bluetooth 5.1 Low Energy + +For more information about the Apollo4 Blue Plus SoC and Apollo4 Blue Plus KXR EVB board: + +- `Apollo4 Blue Plus Website`_ +- `Apollo4 Blue Plus Datasheet`_ +- `Apollo4 Blue Plus KXR EVB Website`_ + +Supported Features +================== + +The Apollo4 Blue Plus KXR EVB board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| STIMER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | bluetooth | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig` + +Programming and Debugging +========================= + +Flashing an application +----------------------- + +Connect your device to your host computer using the JLINK USB port. +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application, then flash it to the device: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: apollo4p_blue_kxr_evb + :goals: flash + +.. note:: + `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + to be installed on you host computer. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! apollo4p_blue_kxr_evb + +.. _Apollo4 Blue Plus Website: + https://ambiq.com/apollo4-blue-plus/ + +.. _Apollo4 Blue Plus Datasheet: + https://contentportal.ambiq.com/documents/20123/388410/Apollo4-Blue-Plus-SoC-Datasheet.pdf + +.. _Apollo4 Blue Plus KXR EVB Website: + https://www.ambiq.top/en/apollo4-blue-plus-kxr-soc-eval-board + +.. _SEGGER J-Link software: + https://www.segger.com/downloads/jlink + +.. _pylink: + https://github.com/Square/pylink diff --git a/boards/ambiq/apollo4p_evb/Kconfig.apollo4p_evb b/boards/ambiq/apollo4p_evb/Kconfig.apollo4p_evb new file mode 100644 index 00000000000..0d77eae0c0b --- /dev/null +++ b/boards/ambiq/apollo4p_evb/Kconfig.apollo4p_evb @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro + +config BOARD_APOLLO4P_EVB + select SOC_APOLLO4P diff --git a/boards/arm/apollo4p_evb/apollo4p_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/apollo4p_evb/apollo4p_evb-pinctrl.dtsi rename to boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi diff --git a/boards/arm/apollo4p_evb/apollo4p_evb.dts b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts similarity index 100% rename from boards/arm/apollo4p_evb/apollo4p_evb.dts rename to boards/ambiq/apollo4p_evb/apollo4p_evb.dts diff --git a/boards/arm/apollo4p_evb/apollo4p_evb.yaml b/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml similarity index 100% rename from boards/arm/apollo4p_evb/apollo4p_evb.yaml rename to boards/ambiq/apollo4p_evb/apollo4p_evb.yaml diff --git a/boards/arm/apollo4p_evb/apollo4p_evb_connector.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi similarity index 100% rename from boards/arm/apollo4p_evb/apollo4p_evb_connector.dtsi rename to boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi diff --git a/boards/arm/apollo4p_evb/apollo4p_evb_defconfig b/boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig similarity index 85% rename from boards/arm/apollo4p_evb/apollo4p_evb_defconfig rename to boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig index e3c18add0df..1b05969a07d 100644 --- a/boards/arm/apollo4p_evb/apollo4p_evb_defconfig +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig @@ -2,7 +2,6 @@ # # Copyright (c) 2023 Antmicro -CONFIG_SOC_SERIES_APOLLO4X=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/apollo4p_evb/board.cmake b/boards/ambiq/apollo4p_evb/board.cmake similarity index 100% rename from boards/arm/apollo4p_evb/board.cmake rename to boards/ambiq/apollo4p_evb/board.cmake diff --git a/boards/ambiq/apollo4p_evb/board.yml b/boards/ambiq/apollo4p_evb/board.yml new file mode 100644 index 00000000000..023487c3ecd --- /dev/null +++ b/boards/ambiq/apollo4p_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: apollo4p_evb + vendor: ambiq + socs: + - name: apollo4p diff --git a/boards/arm/apollo4p_evb/doc/apollo4-plus-soc-eval-board.jpg b/boards/ambiq/apollo4p_evb/doc/apollo4-plus-soc-eval-board.jpg similarity index 100% rename from boards/arm/apollo4p_evb/doc/apollo4-plus-soc-eval-board.jpg rename to boards/ambiq/apollo4p_evb/doc/apollo4-plus-soc-eval-board.jpg diff --git a/boards/ambiq/apollo4p_evb/doc/index.rst b/boards/ambiq/apollo4p_evb/doc/index.rst new file mode 100644 index 00000000000..7c5cd174cf6 --- /dev/null +++ b/boards/ambiq/apollo4p_evb/doc/index.rst @@ -0,0 +1,105 @@ +.. _apollo4p_evb: + +Ambiq Apollo4P EVB +################## + +Apollo4P EVB is a board by Ambiq featuring their ultra-low power Apollo4 Plus SoC. + +.. image:: ./apollo4-plus-soc-eval-board.jpg + :align: center + :alt: Apollo4P EVB + +Hardware +******** + +- Apollo4 Plus SoC with upto 192 MHz operating frequency +- ARM® Cortex® M4F core +- 64 kB 2-way Associative/Direct-Mapped Cache per core +- Up to 2 MB of non-volatile memory (NVM) for code/data +- Up to 2.75 MB of low leakage / low power RAM for code/data +- 384 kB Tightly Coupled RAM +- 384 kB Extended RAM + +For more information about the Apollo4 Plus SoC and Apollo4P EVB board: + +- `Apollo4 Plus Website`_ +- `Apollo4 Plus Datasheet`_ +- `Apollo4P EVB Website`_ + +Supported Features +================== + +The Apollo4P EVB board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| STIMER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig` + +Programming and Debugging +========================= + +Flashing an application +----------------------- + +Connect your device to your host computer using the JLINK USB port. +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application, then flash it to the device: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: apollo4p_evb + :goals: flash + +.. note:: + `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + to be installed on you host computer. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! apollo4p_evb + +.. _Apollo4 Plus Website: + https://ambiq.com/apollo4-plus/ + +.. _Apollo4 Plus Datasheet: + https://contentportal.ambiq.com/documents/20123/388415/Apollo4-Plus-SoC-Datasheet.pdf + +.. _Apollo4P EVB Website: + https://www.ambiq.top/en/apollo4-plus-soc-eval-board + +.. _SEGGER J-Link software: + https://www.segger.com/downloads/jlink + +.. _pylink: + https://github.com/Square/pylink diff --git a/boards/ambiq/index.rst b/boards/ambiq/index.rst new file mode 100644 index 00000000000..9c202652c62 --- /dev/null +++ b/boards/ambiq/index.rst @@ -0,0 +1,10 @@ +.. _boards-ambiq: + +Ambiq +##### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/amd/index.rst b/boards/amd/index.rst new file mode 100644 index 00000000000..fc172e9e0f6 --- /dev/null +++ b/boards/amd/index.rst @@ -0,0 +1,10 @@ +.. _boards-amd: + +Advanced Micro Devices (AMD), Inc. +################################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/amd/kv260_r5/Kconfig.defconfig b/boards/amd/kv260_r5/Kconfig.defconfig new file mode 100644 index 00000000000..aa92cd2bb20 --- /dev/null +++ b/boards/amd/kv260_r5/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Linaro. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_KV260_R5 + +config BUILD_OUTPUT_BIN + default y + +if USERSPACE + +config COMPILER_ISA_THUMB2 + default n + +endif + +endif # BOARD_KV260_R5 diff --git a/boards/amd/kv260_r5/Kconfig.kv260_r5 b/boards/amd/kv260_r5/Kconfig.kv260_r5 new file mode 100644 index 00000000000..01327adf72a --- /dev/null +++ b/boards/amd/kv260_r5/Kconfig.kv260_r5 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Linaro. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KV260_R5 + select SOC_XILINX_ZYNQMP_RPU diff --git a/boards/arm/kv260_r5/board.cmake b/boards/amd/kv260_r5/board.cmake similarity index 100% rename from boards/arm/kv260_r5/board.cmake rename to boards/amd/kv260_r5/board.cmake diff --git a/boards/amd/kv260_r5/board.yml b/boards/amd/kv260_r5/board.yml new file mode 100644 index 00000000000..9e43962bfc3 --- /dev/null +++ b/boards/amd/kv260_r5/board.yml @@ -0,0 +1,5 @@ +board: + name: kv260_r5 + vendor: amd + socs: + - name: zynqmp_rpu diff --git a/boards/arm/kv260_r5/doc/index.rst b/boards/amd/kv260_r5/doc/index.rst similarity index 100% rename from boards/arm/kv260_r5/doc/index.rst rename to boards/amd/kv260_r5/doc/index.rst diff --git a/boards/arm/kv260_r5/doc/kv260-starter-kit.jpg b/boards/amd/kv260_r5/doc/kv260-starter-kit.jpg similarity index 100% rename from boards/arm/kv260_r5/doc/kv260-starter-kit.jpg rename to boards/amd/kv260_r5/doc/kv260-starter-kit.jpg diff --git a/boards/arm/kv260_r5/kv260_r5.dts b/boards/amd/kv260_r5/kv260_r5.dts similarity index 100% rename from boards/arm/kv260_r5/kv260_r5.dts rename to boards/amd/kv260_r5/kv260_r5.dts diff --git a/boards/arm/kv260_r5/kv260_r5.yaml b/boards/amd/kv260_r5/kv260_r5.yaml similarity index 100% rename from boards/arm/kv260_r5/kv260_r5.yaml rename to boards/amd/kv260_r5/kv260_r5.yaml diff --git a/boards/amd/kv260_r5/kv260_r5_defconfig b/boards/amd/kv260_r5/kv260_r5_defconfig new file mode 100644 index 00000000000..4b86de20d6b --- /dev/null +++ b/boards/amd/kv260_r5/kv260_r5_defconfig @@ -0,0 +1,17 @@ +CONFIG_XIP=n + +CONFIG_ISR_STACK_SIZE=512 +CONFIG_THREAD_STACK_INFO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_XLNX_PS=y + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_ARM_MPU=y diff --git a/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k b/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k new file mode 100644 index 00000000000..a1a3daffac8 --- /dev/null +++ b/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADP_XC7K + select SOC_ANDES_AE350 if BOARD_ADP_XC7K_AE350 diff --git a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.dts b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts similarity index 100% rename from boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.dts rename to boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts diff --git a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.yaml b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.yaml similarity index 90% rename from boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.yaml rename to boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.yaml index c837eda1ef1..69087b9ad9e 100644 --- a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.yaml +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.yaml @@ -1,4 +1,4 @@ -identifier: adp_xc7k_ae350 +identifier: adp_xc7k/ae350 name: Andes ADP-XC7K AE350 type: mcu arch: riscv diff --git a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig similarity index 90% rename from boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig rename to boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig index edbe7118c64..78a5b22ff6f 100644 --- a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_ANDES_AE350=y -CONFIG_SOC_ANDES_AE350=y -CONFIG_BOARD_ADP_XC7K_AE350=y CONFIG_XIP=n CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/andestech/adp_xc7k_ae350/board.yml b/boards/andestech/adp_xc7k_ae350/board.yml new file mode 100644 index 00000000000..09ade0170f3 --- /dev/null +++ b/boards/andestech/adp_xc7k_ae350/board.yml @@ -0,0 +1,5 @@ +board: + name: adp_xc7k + vendor: andestech + socs: + - name: ae350 diff --git a/boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k160.jpg b/boards/andestech/adp_xc7k_ae350/doc/img/adp_xc7k160.jpg similarity index 100% rename from boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k160.jpg rename to boards/andestech/adp_xc7k_ae350/doc/img/adp_xc7k160.jpg diff --git a/boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k410.jpg b/boards/andestech/adp_xc7k_ae350/doc/img/adp_xc7k410.jpg similarity index 100% rename from boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k410.jpg rename to boards/andestech/adp_xc7k_ae350/doc/img/adp_xc7k410.jpg diff --git a/boards/riscv/adp_xc7k_ae350/doc/img/connect_aice.jpg b/boards/andestech/adp_xc7k_ae350/doc/img/connect_aice.jpg similarity index 100% rename from boards/riscv/adp_xc7k_ae350/doc/img/connect_aice.jpg rename to boards/andestech/adp_xc7k_ae350/doc/img/connect_aice.jpg diff --git a/boards/andestech/adp_xc7k_ae350/doc/index.rst b/boards/andestech/adp_xc7k_ae350/doc/index.rst new file mode 100644 index 00000000000..ee7dc40d355 --- /dev/null +++ b/boards/andestech/adp_xc7k_ae350/doc/index.rst @@ -0,0 +1,334 @@ +.. _adp_xc7k_ae350: + +Andes ADP-XC7K AE350 +#################### + +Overview +******** + +ADP-XC7K AE350 board is for AndeShape AE350 platform on ADP-XC7K series +FPGA-based development boards. + +ADP-XC7K series are FPGA-based development and prototyping boards for evaluation of +variety of AndesCore processors and AndeShape SoC platform IPs. +AE350 is a RISC-V platform which can integrate AndesCore CPUs with a collection +of fundamental peripheral IPs. + +1st figure shows the green PCB is ADP-XC7K160 and 2nd figure shows the red PCB is ADP-XC7K410. + +.. image:: img/adp_xc7k160.jpg + :align: center + :alt: ADP-XC7K160 + +.. image:: img/adp_xc7k410.jpg + :align: center + :alt: ADP-XC7K410 + +More information can be found on `ADP-XC7K160/410`_ and `AndeShape AE350`_ websites. + +Hardware +******** + +The ADP-XC7K AE350 platform integrates 1 ~ 4 cores 32/64-bit 60MHz RISC-V CPUs, DSP, +1GB RAM, Cache, SPI flash memory, ethernet controller and other peripherals. + +The ADP-XC7K AE350 platform provides following hardware components: + +- 1 ~ 4 cores 32/64-bit 60MHz AndeStar v5 RISC-V CPUs +- 1GB on-board SDRAM +- 2MB SPI flash memory (1MB can be used for XIP) +- UART +- I2C +- SPI +- GPIO +- PWM +- DMA +- 10/100 Ethernet RJ45 port +- LCD module connector +- 16KB I2C EEPROM +- SD memory card slot +- MIC-in, Line-in, and Line-out with AC97 audio codec + +Supported Features +================== + +The ``adp_xc7k/ae350`` board configuration supports the following hardware features: + ++----------------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++================+============+======================+ +| PLIC | on-chip | interrupt_controller | ++----------------+------------+----------------------+ +| RISC-V Machine | on-chip | timer | +| Timer | | | ++----------------+------------+----------------------+ +| GPIO | on-chip | gpio | ++----------------+------------+----------------------+ +| UART | on-chip | serial | ++----------------+------------+----------------------+ +| COUNTER | on-chip | counter | ++----------------+------------+----------------------+ +| SPI | on-chip | spi | ++----------------+------------+----------------------+ +| I2C | on-chip | i2c | ++----------------+------------+----------------------+ +| EEPROM | on-chip | eeprom | ++----------------+------------+----------------------+ +| FLASH | on-chip | flash | ++----------------+------------+----------------------+ +| HWINFO | on-chip | syscon | ++----------------+------------+----------------------+ +| MAILBOX | on-chip | mbox | ++----------------+------------+----------------------+ +| DMA | on-chip | dma | ++----------------+------------+----------------------+ +| WATCHDOG | on-chip | wdt | ++----------------+------------+----------------------+ + +Other hardware features are not supported yet. + +Connections and IOs +=================== + +The ADP-XC7K AE350 platform has 1 GPIO controller. It providing 32 bits of IO. +It is responsible for pin input/output, pull-up, etc. + +Mapping from GPIO controller to the ADP-XC7K board pins: + ++--------------------+--------------------+ +| GPIO controller | Usage / Board pins | ++====================+====================+ +| **Push Buttons** | | ++--------------------+--------------------+ +| GPIO.0 | SW1 | ++--------------------+--------------------+ +| GPIO.1 | SW2 | ++--------------------+--------------------+ +| GPIO.2 | SW3 | ++--------------------+--------------------+ +| GPIO.3 | SW4 | ++--------------------+--------------------+ +| GPIO.4 | SW5 | ++--------------------+--------------------+ +| GPIO.5 | SW6 | ++--------------------+--------------------+ +| GPIO.6 | SW7 | ++--------------------+--------------------+ +| **7-Segment LED1** | | ++--------------------+--------------------+ +| GPIO.16 | 7SEG1.A | ++--------------------+--------------------+ +| GPIO.17 | 7SEG1.B | ++--------------------+--------------------+ +| GPIO.18 | 7SEG1.C | ++--------------------+--------------------+ +| GPIO.19 | 7SEG1.D | ++--------------------+--------------------+ +| GPIO.20 | 7SEG1.E | ++--------------------+--------------------+ +| GPIO.21 | 7SEG1.F | ++--------------------+--------------------+ +| GPIO.22 | 7SEG1.G | ++--------------------+--------------------+ +| GPIO.23 | 7SEG1.DP | ++--------------------+--------------------+ +| **7-Segment LED2** | | ++--------------------+--------------------+ +| GPIO.24 | 7SEG2.A | ++--------------------+--------------------+ +| GPIO.25 | 7SEG2.B | ++--------------------+--------------------+ +| GPIO.26 | 7SEG2.C | ++--------------------+--------------------+ +| GPIO.27 | 7SEG2.D | ++--------------------+--------------------+ +| GPIO.28 | 7SEG2.E | ++--------------------+--------------------+ +| GPIO.29 | 7SEG2.F | ++--------------------+--------------------+ +| GPIO.30 | 7SEG2.G | ++--------------------+--------------------+ +| GPIO.31 | 7SEG2.DP | ++--------------------+--------------------+ +| **GPIO pins** | | ++--------------------+--------------------+ +| GPIO.7 | IDE_CON1.4 | ++--------------------+--------------------+ +| GPIO.8 | IDE_CON1.6 | ++--------------------+--------------------+ +| GPIO.9 | IDE_CON1.8 | ++--------------------+--------------------+ +| GPIO.10 | IDE_CON1.10 | ++--------------------+--------------------+ +| GPIO.11 | IDE_CON1.11 | ++--------------------+--------------------+ +| GPIO.12 | IDE_CON1.12 | ++--------------------+--------------------+ +| GPIO.13 | IDE_CON1.13 | ++--------------------+--------------------+ +| GPIO.14 | IDE_CON1.14 | ++--------------------+--------------------+ +| GPIO.15 | IDE_CON1.15 | ++--------------------+--------------------+ + +Other peripheral mapping are listed below: + ++-------------+---------------------------------+ +| Peripherals | Usage / Board pins | ++=============+=================================+ +| SPI_1 | internal connected to SPI Flash | ++-------------+---------------------------------+ +| SPI_2_CS | IDE_CON1.37 | ++-------------+---------------------------------+ +| SPI_2_MOSI | IDE_CON1.36 | ++-------------+---------------------------------+ +| SPI_2_MISO | IDE_CON1.38 | ++-------------+---------------------------------+ +| SPI_2_SCLK | IDE_CON1.35 | ++-------------+---------------------------------+ +| I2C_SDA | J27.1 | ++-------------+---------------------------------+ +| I2C_SCL | J27.2 | ++-------------+---------------------------------+ + +System Clock +------------ + +The ADP-XC7K AE350 platform has 60MHz core clock. + +Serial Port +----------- + +The ADP-XC7K AE350 platform has 2 UARTs. +The Zephyr console output is by default assigned to UART2 and the default +settings are 115200 8N1. + +Programming and debugging +************************* + +For debugging zephyr applications or burning them into a flash, you will need to +connect Andes ICE from host computer to ADP-XC7K board and execute the +Andes ICE management software, ICEman, on this host computer. + +Connecting Andes ICE (AICE) +=========================== + +AICE is used for flashing and debugging the board. Please connect AICE to both +ADP-XC7K board and the host computer as shown in the figure. + +.. image:: img/connect_aice.jpg + :align: center + :alt: Connect AICE + +More information can be found on `AICE-MINI+`_, `AICE-MICRO`_ website + +Building +======== + +You can build applications in the usual way. Here is an example for +the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adp_xc7k/ae350 + :goals: build + +Flashing +======== + +Before flashing, you have to download ICEman (``ice.zip``) from the +`Andes Development Kit`_. +If you want to use XIP mode (``CONFIG_XIP=y``), you also need to download +the flash burner (``flash.zip``). + +At first, you should run ICEman when flashing and debugging program. + +.. code-block:: console + + # Enable execute file permission of ICEman + chmod a+x ./ICEman + + # Running the ICEman server + sudo ./ICEman -Z v5 + +.. note:: + + To run ICEman commands as a normal user, you will need to install the + :file:`70-ndsusb-v1.rules` udev rules file (usually by placing it in + :file:`/etc/udev/rules.d`, then unplugging and plugging the + AICE adapter in again via USB.). + +If ``CONFIG_XIP=n``, you can load the program (``zephyr.elf``) into RAM directly +and execute it. + +.. code-block:: console + + # Check the ICEman server is running + # Load the program into RAM and execute it + riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf + (gdb) target remote :1111 + (gdb) monitor reset halt + (gdb) load + (gdb) quit + +If ``CONFIG_XIP=y``, you need to burn the program (``zephyr.bin``) into flash memory +and execute it. + +.. code-block:: console + + # Check the ICEman server is running + # Burn the program into flash and execute it + /bin/target_burn_frontend \ + -P 4444 --unlock --verify --image=build/zephyr/zephyr.bin \ + --algorithm-bin=/target_bin/target_SPI_v5_[32|64].bin + + # Note: + # 1. Assume the flash burner is downloaded to directory + # 2. For algorithm-bin file, use target_SPI_v5_32.bin in RV32 platform and + # use target_SPI_v5_64.bin in RV64 platform + +Open a serial terminal with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +you should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.4.0 ***** + Hello World! adp_xc7k + +Debugging +========= + +.. code-block:: console + + # Check the ICEman server is running + # Load and debug program + ./riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf + (gdb) target remote :1111 + (gdb) monitor reset halt + (gdb) load + +If ``CONFIG_XIP=y``, please follow the flashing section to burn the program into +flash memory first. +Then, you can use GDB to debug program by above commands but do NOT execute ``load`` +command since the program has been placed in the flash memory. + +References +********** + +.. target-notes:: + +.. _ADP-XC7K160/410: http://www.andestech.com/en/products-solutions/andeshape-platforms/adp-xc7k160-410/ + +.. _AndeShape AE350: http://www.andestech.com/en/products-solutions/andeshape-platforms/ae350-axi-based-platform-pre-integrated-with-n25f-nx25f-a25-ax25/ + +.. _AICE-MINI+: http://www.andestech.com/en/products-solutions/andeshape-platforms/aice-mini-plus/ + +.. _AICE-MICRO: http://www.andestech.com/en/products-solutions/andeshape-platforms/aice-micro/ + +.. _Andes Development Kit: https://github.com/andestech/Andes-Development-Kit/releases diff --git a/boards/andestech/index.rst b/boards/andestech/index.rst new file mode 100644 index 00000000000..17618d8186e --- /dev/null +++ b/boards/andestech/index.rst @@ -0,0 +1,10 @@ +.. _boards-andes: + +Andes Technology +################ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arc/em_starterkit/CMakeLists.txt b/boards/arc/em_starterkit/CMakeLists.txt deleted file mode 100644 index 5b1b4b9b11b..00000000000 --- a/boards/arc/em_starterkit/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(pmodmux.c) -zephyr_sources_ifdef(CONFIG_ARC_MPU_ENABLE arc_mpu_regions.c) diff --git a/boards/arc/em_starterkit/Kconfig b/boards/arc/em_starterkit/Kconfig deleted file mode 100644 index 45cf1bd2431..00000000000 --- a/boards/arc/em_starterkit/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# DesignWare ARC EM Starter Kit board configuration options - -# Copyright (c) 2017 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Board Firmware Version" - default BOARD_EM_STARTERKIT_R23 - depends on BOARD_EM_STARTERKIT - - config BOARD_EM_STARTERKIT_R22 - bool "2.2" - - config BOARD_EM_STARTERKIT_R23 - bool "2.3" - -endchoice diff --git a/boards/arc/em_starterkit/Kconfig.board b/boards/arc/em_starterkit/Kconfig.board deleted file mode 100644 index dd7da9f0512..00000000000 --- a/boards/arc/em_starterkit/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# DesignWare ARC EM Starter Kit board configuration - -# Copyright (c) 2016 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EM_STARTERKIT - bool "ARC EM Starter Kit" - depends on SOC_EMSK - help - The DesignWare ARC EM Starter Kit board is a board - that can host up to 3 different SOC FPGA bit files. - Both version 2.2 and 2.3 firmware have EM7D, EM9D and EM11D configurations. - EM9D using CCM memories and is a Harvard Architecture. - EM7D and EM11D have access to 128MB DRAM and use i-cache and d-cache. - EM7D of EMSK 2.3 supports secure mode. diff --git a/boards/arc/em_starterkit/Kconfig.defconfig b/boards/arc/em_starterkit/Kconfig.defconfig deleted file mode 100644 index 7e9c5bc45d5..00000000000 --- a/boards/arc/em_starterkit/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EM_STARTERKIT - -config BOARD - default "em_starterkit" - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 100 - -endif # I2C_DW - -endif # BOARD_EM_STARTERKIT diff --git a/boards/arc/em_starterkit/board.dtsi b/boards/arc/em_starterkit/board.dtsi deleted file mode 100644 index e80ee0eea30..00000000000 --- a/boards/arc/em_starterkit/board.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include - -/ { - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - led3 = &led3; - led4 = &led4; - led5 = &led5; - led6 = &led6; - led7 = &led7; - led8 = &led8; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio1 0 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpio1 1 0>; - label = "LED 1"; - }; - led2: led_2 { - gpios = <&gpio1 2 0>; - label = "LED 2"; - }; - led3: led_3 { - gpios = <&gpio1 3 0>; - label = "LED 3"; - }; - led4: led_4 { - gpios = <&gpio1 4 0>; - label = "LED 4"; - }; - led5: led_5 { - gpios = <&gpio1 5 0>; - label = "LED 5"; - }; - led6: led_6 { - gpios = <&gpio1 6 0>; - label = "LED 6"; - }; - led7: led_7 { - gpios = <&gpio1 7 0>; - label = "LED 7"; - }; - led8: led_8 { - gpios = <&gpio1 8 0>; - label = "LED 8"; - }; - - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - label = "Push button switch 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - label = "Push button switch 1"; - zephyr,code = ; - }; - button2: button_2 { - /* gpio flags need validation */ - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - label = "Push button switch 2"; - zephyr,code = ; - }; - switch0: switch_0 { - /* gpio flags need validation */ - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - label = "DIP SW1 - Switch 1"; - zephyr,code = ; - }; - switch1: switch_1 { - /* gpio flags need validation */ - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - label = "DIP SW1 - Switch 2"; - zephyr,code = ; - }; - switch2: switch_2 { - /* gpio flags need validation */ - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - label = "DIP SW1 - Switch 3"; - zephyr,code = ; - }; - switch3: switch_3 { - /* gpio flags need validation */ - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - label = "DIP SW1 - Switch 4"; - zephyr,code = ; - }; - }; - -}; diff --git a/boards/arc/em_starterkit/doc/index.rst b/boards/arc/em_starterkit/doc/index.rst deleted file mode 100644 index 6e11af1b12d..00000000000 --- a/boards/arc/em_starterkit/doc/index.rst +++ /dev/null @@ -1,331 +0,0 @@ -.. _em_starterkit: - -DesignWare(R) ARC(R) EM Starter Kit -################################### - -Overview -******** - -The DesignWare(R) ARC(R) EM Starter Kit is a low-cost, versatile solution -enabling rapid software development and software debugging, and profiling -for the ARC EM Family of processors. The EM Family includes the EM4, EM6, -EM5D, EM7D, EM9D, and EM11D cores. The Zephyr RTOS can be used with the -EM Starter Kit. - -.. image:: em_starterkit.jpg - :align: center - :alt: DesignWare(R) ARC(R) EM Starter Kit (synopsys.com) - -The ARC EM Starter Kit consists of a hardware platform, including pre-installed -FPGA images of different ARC EM processor configurations with peripherals. -Documentation for this board can be found at `embARC website`_. - -See also this URL for details about the board: -`Designware ARC EM Starter Kit website`_ . - -The latest version of EM Starter Kit is 2.3, developer can upgrade from -2.0/2.1/2.2 to 2.3 using latest firmware. -The default configuration for EM Starter Kit boards can be found in -:zephyr_file:`boards/arc/em_starterkit/em_starterkit_defconfig`. - -The default SoC for this board supported in Zephyr is the EM9D. -This configuration is a Harvard Architecture, with a separate -instruction bus and data bus. Instruction memory is called ICCM -and data memory is called DCCM. The configuration file for EM9D -is found in :zephyr_file:`soc/arc/snps_emsk/Kconfig.defconfig.em9d`. - -If you have a larger program, you can select the EM7D or EM11D, which gives -access to 128KB DRAM with i-cache and d-cache. The configuration file for EM7D -is found in :zephyr_file:`soc/arc/snps_emsk/Kconfig.defconfig.em7d` and EM11D is -found in :zephyr_file:`soc/arc/snps_emsk/Kconfig.defconfig.em11d`. - - -Hardware -******** -Board Layout -============ - -The ARC EM Starter Kit main board has 6 Pmod connectors. These can be configured -to support attachment of GPIO, I2C, UART or SPI devices. - -The board also has a 16MB SPI-FLASH and an SDCard for storage. There are 9 LEDs, -3 buttons, and 4 dip switches that can be used with GPIO. - -The Xilinx Spartan(R)-6 LX150 FPGA can auto-load one of 3 FPGA SoC bit files -which have the EM7D, EM9D, or EM11D SoC. - -Documentation and general information for the board can be found at the -`embARC website`_, which also includes some free sample software. - - -Supported Firmware Versions -=========================== - -The EM Starter Kit has different versions, such as 1.0, 1.1, 2.0, 2.1, -2.2 and 2.3. -In Zephyr, only firmware versions 2.2 and 2.3 are supported. - -* For EM Starter Kit 2.2, EM7D, EM9D and EM11D core configurations are supported. - - * Use :kconfig:option:`CONFIG_BOARD_EM_STARTERKIT_R22` to select 2.2 version. - * Use :kconfig:option:`CONFIG_SOC_EMSK_EM7D`, :kconfig:option:`CONFIG_SOC_EMSK_EM9D` or - :kconfig:option:`CONFIG_SOC_EMSK_EM11D` to select EM7D or EM9D or EM11D. - -* For EM Starter Kit 2.3, EM7D, EM9D and EM11D core configurations are - supported. - - * Use :kconfig:option:`CONFIG_BOARD_EM_STARTERKIT_R23` to select 2.3 version. - * Use :kconfig:option:`CONFIG_SOC_EMSK_EM7D`, :kconfig:option:`CONFIG_SOC_EMSK_EM9D` or - :kconfig:option:`CONFIG_SOC_EMSK_EM11D` to select EM7D or EM9D or EM11D. - -Supported Features -================== - -The Zephyr kernel supports multiple hardware features on the EM Starter Kit -through the use of device drivers. - -The EM Starter Kit supports 6 Digilent Pmod(TM) Interfaces, which enables the -use of a large variety of pluggable modules for storage, communications, -sensors, displays, etc. With the Pmod interface, you can prototype your -applications using the Zephyr RTOS. - -The table below shows which drivers are supported and which functionality can -be found on which architectures: - -+-----------+------------+-----+-------+-----------------------+ -| Interface | Controller |EM9D | EM11D | Driver/Component | -+===========+============+=====+=======+=======================+ -| INT | on-chip | Y | Y | interrupt_controller | -+-----------+------------+-----+-------+-----------------------+ -| UART | usb + | Y | Y | serial port-polling; | -| | 2 Pmods | | | serial port-interrupt | -+-----------+------------+-----+-------+-----------------------+ -| SPI | 2 Pmods | Y | Y | spi | -+-----------+------------+-----+-------+-----------------------+ -| ADC | n/a | N | N | adc (can add via Pmod)| -+-----------+------------+-----+-------+-----------------------+ -| I2C | 2 Pmods | Y | Y | i2c | -+-----------+------------+-----+-------+-----------------------+ -| GPIO | 6 Pmods | Y | Y | gpio | -+-----------+------------+-----+-------+-----------------------+ -| PWM | n/a | N | N | pwm | -+-----------+------------+-----+-------+-----------------------+ - -The board has 3 (debounced and interrupting) buttons for use with GPIO, 4 dip -switches, 9 LEDs, SDCard on SPI, and a 16MB SPI-Flash memory. - -The SPI-FLASH driver is supported with sample, which can be found in -``samples/drivers/spi_flash``. - -The SPI-Flash also holds 3 (or 4) separate FPGA CPU bit files, selectable via -dip switch. - -The SPI-Flash is also programmed with a bootloader. The bootloader can copy a -program image from SPI-Flash into executable memory. Zephyr initialization will -copy the initialized data section to the data memory if CONFIG_XIP is used. - - -Programming and Debugging -************************* - -Required Hardware and Software -============================== - -To use Zephyr RTOS applications on the EM Starter Kit board, a few additional -pieces of hardware are required. - -* USB Cable (delivered as part of the ARC EM Starter Kit) - -* The USB cable provides power to the board; however, if the board is to run - standalone, the universal switching power adaptor (110-240V AC to 5V DC), - provided in the package, can be used to power the board. - -* :ref:`The Zephyr SDK ` - -* Terminal emulator software for use with the USB-UART. Suggestion: - `Putty Website`_. - -* (optional) A collection of Pmods. - See `Digilent Pmod Modules`_ or develop your custom interfaces to attach - to the Pmod connector. - -Set up the ARC EM Starter Kit -============================= - -To run Zephyr application on correct arc core of EM Starter Kit, you need to -setup the board correctly. - -* Connect the digilent usb cable from your host to the board. - -* Connect the 5V DC power supply to your board. - -* Select the core configuration of the board by choosing correct dip switch - SW1 settings, then press then FPGA configure button located above the letter - 'C' of the ARC logo on the board. - -* Then the board will be reconfigured with selected core configuration, you - can download and debug Zephyr application now. - -* If you want to know more about how to use this board, you can take a look - at the `ARC EM Starter Kit User Guide`_. - -Set up Zephyr Software -====================== - -Since there are different firmware versions of EM Starter Kit, you need to -choose the proper firmware version supported in Zephyr. - -Three different configurations exist for this board: - -* EM7D: em_starterkit_em7d_defconfig -* EM9D: em_starterkit_defconfig -* EM11D: em_starterkit_em11d_defconfig - - -Building Sample Applications -============================== - -You can try many of the sample applications or tests, but let us discuss -the one called :ref:`hello_world`. -It is found in :zephyr_file:`samples/hello_world`. - -Configuring ------------ - -You may need to write a prj_arc.conf file if the sample doesn't have one. -Next, you can use the menuconfig rule to configure the target. By -specifying ``em_starterkit`` as the board configuration, you can select the ARC -EM Starter Kit board support for Zephyr. - -.. zephyr-app-commands:: - :board: em_starterkit - :zephyr-app: samples/hello_world - :goals: menuconfig - -On this board you will also need to consider the "ARC SoC Selection" and set -it either to EM9D or EM11D. To boot up the EM9D on the board, all dip -switches should be UP except for switch 1. Other configuration choices -are made in the normal way. To boot up the EM11D on the board, -all dip switches should be UP except for switch 2. Next press the button -above the letter C in the "ARC" logo on the silkscreen. - -Building --------- - -You can build application in the usual way. Refer to -:ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :board: em_starterkit - :zephyr-app: samples/hello_world - :maybe-skip-config: - :goals: build - -Connecting Serial Output -========================= - -In the default configuration, Zephyr's EM Starter Kit images support -serial output via the UART1 on the board. To enable serial output: - -On your development environment, you will need to: - -* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) -* Specify the tty driver name, for example, on Linux this may be :file:`/dev/ttyUSB1` -* Set the communication settings to: - - -========= ===== -Parameter Value -========= ===== -Baud: 115200 -Data: 8 bits -Parity: None -Stopbits: 1 -========= ===== - -Debugging -========== - -Using the latest version of Zephyr SDK(>=0.9), you can debug and flash -EM Starterkit directly. - -One option is to build and debug the application using the usual -Zephyr build system commands. - -.. zephyr-app-commands:: - :board: em_starterkit - :app: - :goals: debug - -At this point you can do your normal debug session. Set breakpoints and then -'c' to continue into the program. - -The other option is to launch a debug server, as follows. - -.. zephyr-app-commands:: - :board: em_starterkit - :app: - :goals: debugserver - -Then connect to the debug server at the EM Starter Kit from a second -console, from the build directory containing the output :file:`zephyr.elf`. - -.. code-block:: console - - $ cd - $ $ZEPHYR_SDK_INSTALL_DIR/arc-zephyr-elf/bin/arc-zephyr-elf-gdb zephyr.elf - (gdb) target remote localhost:3333 - (gdb) load - (gdb) b main - (gdb) c - -Flashing -======== - -If you just want to download the application to the EM Starter Kit's CCM -or DDR and run, you can do so in the usual way. - -.. zephyr-app-commands:: - :board: em_starterkit - :goals: flash - -This command still uses openocd and gdb to load application elf file -to EM Starter Kit, but it will load application and then run immediately. -If power is lost, the application will also lost due to power loss. - -Most of the time you will not be flashing your program but will instead -debug it using openocd and gdb. The program can be download via the USB -cable into the code and data memories. - -When you are ready to deploy the program so that it boots up automatically -on reset or power-up, you can follow the steps to place the program on -SPI-FLASH. - -For instructions on how to write your program to SPI-FLASH, -refer to the documentation on the ARC EM Starter Kit at the -`embARC website`_, which includes instructions for how to place an -executable image onto the SPI-FLASH in such a way that it is understood -by the bootloader. - -Release Notes -************* - -The following is a list of TODO items: - -* ``GH-2647``: Zephyr needs i-cache API (all targets) -* ``GH-2230``: Zephyr ARC port doesn't yet support nested regular interrupts. -* pinmux driver: Possibly it can be written to configure PMods too. - -References -********** - -.. _embARC website: https://www.embarc.org - -.. _Designware ARC EM Starter Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit - -.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules - -.. _Putty website: http://www.putty.org - -.. _ARC EM Starter Kit User Guide: https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit diff --git a/boards/arc/em_starterkit/em_starterkit.dts b/boards/arc/em_starterkit/em_starterkit.dts deleted file mode 100644 index 7acf111e6c7..00000000000 --- a/boards/arc/em_starterkit/em_starterkit.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include "em_starterkit_r23.dtsi" -#include "board.dtsi" - -/ { - model = "em_starterkit-em9d"; - compatible = "snps,em_starterkit-em9d", "snps,em_starterkit"; - - aliases { - uart-0 = &uart0; - uart-1 = &uart1; - uart-2 = &uart2; - spi-flash0 = &w25q128bv; - }; - - chosen { - zephyr,sram = &dccm0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - }; - - iccm0: iccm@0 { - compatible = "arc,iccm"; - reg = <0x0 DT_SIZE_K(256)>; - }; - - dccm0: dccm@80000000 { - compatible = "arc,dccm"; - reg = <0x80000000 DT_SIZE_K(128)>; - }; - - xccm@c0000000 { - compatible = "arc,xccm"; - reg = <0xc0000000 DT_SIZE_K(8)>; - }; - - yccm@e0000000 { - compatible = "arc,yccm"; - reg = <0xe0000000 DT_SIZE_K(8)>; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; -}; diff --git a/boards/arc/em_starterkit/em_starterkit.yaml b/boards/arc/em_starterkit/em_starterkit.yaml deleted file mode 100644 index f489b0a28ac..00000000000 --- a/boards/arc/em_starterkit/em_starterkit.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: em_starterkit -name: EM Starterkit -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -supported: - - i2c - - spi - - gpio -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_defconfig b/boards/arc/em_starterkit/em_starterkit_defconfig deleted file mode 100644 index 3bc77c1b6f8..00000000000 --- a/boards/arc/em_starterkit/em_starterkit_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_EMSK=y -CONFIG_SOC_EMSK_EM9D=y -CONFIG_BOARD_EM_STARTERKIT=y -CONFIG_BOARD_EM_STARTERKIT_R23=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y diff --git a/boards/arc/em_starterkit/em_starterkit_em11d.dts b/boards/arc/em_starterkit/em_starterkit_em11d.dts deleted file mode 100644 index 618731c3d9a..00000000000 --- a/boards/arc/em_starterkit/em_starterkit_em11d.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include "em_starterkit_r23.dtsi" -#include "board.dtsi" - -/ { - model = "em_starterkit-em11d"; - compatible = "snps,em_starterkit-em11d", "snps,em_starterkit"; - - aliases { - uart-0 = &uart0; - uart-1 = &uart1; - uart-2 = &uart2; - spi-flash0 = &w25q128bv; - }; - - chosen { - zephyr,sram = &ddr0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - }; - - iccm0: iccm@0 { - compatible = "arc,iccm"; - reg = <0x0 DT_SIZE_K(64)>; - }; - - dccm0: dccm@80000000 { - compatible = "arc,dccm"; - reg = <0x80000000 DT_SIZE_K(64)>; - }; - - xccm@c0000000 { - compatible = "arc,xccm"; - reg = <0xc0000000 DT_SIZE_K(8)>; - }; - - yccm@e0000000 { - compatible = "arc,yccm"; - reg = <0xe0000000 DT_SIZE_K(8)>; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; -}; diff --git a/boards/arc/em_starterkit/em_starterkit_em11d.yaml b/boards/arc/em_starterkit/em_starterkit_em11d.yaml deleted file mode 100644 index f06dccbc8e7..00000000000 --- a/boards/arc/em_starterkit/em_starterkit_em11d.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: em_starterkit_em11d -name: EM Starterkit EM11D -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -supported: - - i2c - - spi - - gpio -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_em11d_defconfig b/boards/arc/em_starterkit/em_starterkit_em11d_defconfig deleted file mode 100644 index 7146e82d57b..00000000000 --- a/boards/arc/em_starterkit/em_starterkit_em11d_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_EMSK=y -CONFIG_SOC_EMSK_EM11D=y -CONFIG_BOARD_EM_STARTERKIT=y -CONFIG_BOARD_EM_STARTERKIT_R23=y -CONFIG_XIP=n -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y diff --git a/boards/arc/em_starterkit/em_starterkit_em7d.yaml b/boards/arc/em_starterkit/em_starterkit_em7d.yaml deleted file mode 100644 index d4ab57393b4..00000000000 --- a/boards/arc/em_starterkit/em_starterkit_em7d.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: em_starterkit_em7d -name: EM Starterkit EM7D -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -supported: - - i2c - - spi - - gpio -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_em7d_defconfig b/boards/arc/em_starterkit/em_starterkit_em7d_defconfig deleted file mode 100644 index 345776e14f1..00000000000 --- a/boards/arc/em_starterkit/em_starterkit_em7d_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_EMSK=y -CONFIG_SOC_EMSK_EM7D=y -CONFIG_BOARD_EM_STARTERKIT=y -CONFIG_BOARD_EM_STARTERKIT_R23=y -CONFIG_XIP=n -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_ARC_HAS_SECURE=y -CONFIG_TRUSTED_EXECUTION_SECURE=y -CONFIG_INIT_ARCH_HW_AT_BOOT=y diff --git a/boards/arc/em_starterkit/em_starterkit_em7d_v22.yaml b/boards/arc/em_starterkit/em_starterkit_em7d_v22.yaml deleted file mode 100644 index b7eb883286f..00000000000 --- a/boards/arc/em_starterkit/em_starterkit_em7d_v22.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: em_starterkit_em7d_v22 -name: EM Starterkit V22 EM7D -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -supported: - - i2c - - spi - - gpio -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_em7d_v22_defconfig b/boards/arc/em_starterkit/em_starterkit_em7d_v22_defconfig deleted file mode 100644 index 70af0aafedc..00000000000 --- a/boards/arc/em_starterkit/em_starterkit_em7d_v22_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_EMSK=y -CONFIG_SOC_EMSK_EM7D=y -CONFIG_BOARD_EM_STARTERKIT=y -CONFIG_BOARD_EM_STARTERKIT_R22=y -CONFIG_XIP=n -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/emsdp/Kconfig.board b/boards/arc/emsdp/Kconfig.board deleted file mode 100644 index c27a4d2c07b..00000000000 --- a/boards/arc/emsdp/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# DesignWare ARC EM Software Development Platform board configuration - -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EMSDP - bool "EM Software Development Platform" - depends on SOC_ARC_EMSDP - help - The ARC EM Software Development Platform (emsdp) is an FPGA based - development platform intended to support ARC licenses in developing - their software for the ARC EM processor family and ARC EM Subsystems. - It has the support for ARC EM4, EM5D, EM6, EM7D, EM9D and EM11D - processors. ARC EM Enhanced Security Package (ESP) and ARC EM - Subsystems (DFSS, SCSS, DSS) are also supported. diff --git a/boards/arc/emsdp/Kconfig.defconfig b/boards/arc/emsdp/Kconfig.defconfig deleted file mode 100644 index 98101cb3a28..00000000000 --- a/boards/arc/emsdp/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# DesignWare ARC EM Software Development Platform board configuration - -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EMSDP - -config BOARD - default "emsdp" - -if SPI - -config SPI_DW - default y - -endif # SPI - -endif # BOARD_EMSDP diff --git a/boards/arc/emsdp/doc/index.rst b/boards/arc/emsdp/doc/index.rst deleted file mode 100644 index b02c2539ef5..00000000000 --- a/boards/arc/emsdp/doc/index.rst +++ /dev/null @@ -1,286 +0,0 @@ -.. _emsdp: - -DesignWare(R) ARC(R) EM Software Development Platform -##################################################### - -Overview -******** - -The DesignWare® ARC® EM Software Development Platform (SDP) is a flexible platform -for rapid software development on ARC EM processor-based subsystems. It is intended -to accelerate software development and debug of ARC EM processors and subsystems for -a wide range of ultra-low power embedded applications such as IoT, sensor fusion, -and voice applications. - -.. image:: emsdp.jpg - :align: center - :alt: DesignWare(R) ARC(R) EM Software Development Platform (synopsys.com) - -For details about the board, see: `DesignWare ARC EM Software Development Platform -(EM SDP) `__ - - -Hardware -******** - -The EM Software Development Platform supports different core configurations, such as EM4, -EM5D, EM6, EM7D, EM9D, EM9D+ESP, EM11D, the default core configuration is EM11D. Use -:kconfig:option:`CONFIG_SOC_EMSDP_EM4`, :kconfig:option:`CONFIG_SOC_EMSDP_EM5D`, -:kconfig:option:`CONFIG_SOC_EMSDP_EM6`, :kconfig:option:`CONFIG_SOC_EMSDP_EM7D`, -:kconfig:option:`CONFIG_SOC_EMSDP_EM7D_ESP`, :kconfig:option:`CONFIG_SOC_EMSDP_EM9D` or -:kconfig:option:`CONFIG_SOC_EMSDP_EM11D` to select different core configuration. - -The following table shows the hardware features supported for different core configuration: - -+-----------+-----+-----+------+------+----------+------+-------+ -| Features | EM4 | EM6 | EM5D | EM7D | EM7D_ESP | EM9D | EM11D | -+===========+=====+=====+======+======+==========+======+=======+ -| Caches | N | Y | N | Y | Y | N | Y | -+-----------+-----+-----+------+------+----------+------+-------+ -| DSP | N | N | Y | Y | Y | Y | Y | -+-----------+-----+-----+------+------+----------+------+-------+ -| XY Memory | N | N | N | N | N | Y | Y | -+-----------+-----+-----+------+------+----------+------+-------+ -| Secure | N | N | N | N | Y | N | N | -+-----------+-----+-----+------+------+----------+------+-------+ - -The table below shows which drivers are currently available in Zephyr. - -+-----------+------------+-------+-----------------------+ -| Interface | Controller | EMSDP | Driver/Component | -+===========+============+=======+=======================+ -| SDIO | on-chip | N | SD-card controller | -+-----------+------------+-------+-----------------------+ -| UART | Arduino + | Y | serial port-polling; | -| | 3 Pmods | | serial port-interrupt | -+-----------+------------+-------+-----------------------+ -| SPI | Arduino + | Y | spi | -| | Pmod + adc | | | -+-----------+------------+-------+-----------------------+ -| ADC | 1 Pmod | N | adc (via spi) | -+-----------+------------+-------+-----------------------+ -| I2C | Arduino + | N | i2c | -| | Pmod | | | -+-----------+------------+-------+-----------------------+ -| GPIO | Arduino + | Y | gpio | -| | Pmod + Pin | | | -+-----------+------------+-------+-----------------------+ -| PWM | Arduino + | N | pwm | -| | Pmod | | | -+-----------+------------+-------+-----------------------+ -| I2S | on-chip | N | Audio interface | -+-----------+------------+-------+-----------------------+ - -Support two 32 MByte Quad-SPI Flash memory, one only contains FPGA image, the other -one is user SPI-FLASH, which is connected via SPI bus and its sample can be found in -``samples/drivers/spi_flash``. - -To configure the FPGA, The ARC EM SDP offers a single USB 2.0 host port, which is -both used to access the FPGAs configuration memory and as a DEBUG/ UART port. - -When connected using the USB cable to a PC, the ARC EM SDP presents itself as a mass -storage device. This allows an FPGA configuration bitstream to be dragged and dropped into -the configuration memory. The FPGA bitstream is automatically loaded into the FPGA device -upon power-on reset, or when the configuration button is pressed. - -For hardware feature details, refer to : `ARC EM Software Development Platform -`__ - -Peripheral driver test and sample -================================= - -``tests/drivers/spi/spi_loopback``: verify DesignWare SPI driver. No need to connect -MISO with MOSI, DW SPI register is configured to internally connect them. This test -use two different speed to verify data transfer with asynchronous functionality. -Note: DW SPI only available on SPI0 and SPI1. - -``samples/drivers/spi_flash``: Verfiy DW SPI and SPI-FLASH on SPI1. First erase the -whole flash then write 4 byte data to the flash. Read from the flash and compare the -result with buffer to check functionality. - -Pinmux interface -================ - -The following pinmux peripheral module standards are supported: - -* Digilent Pmod (3x) - -The ARC EM SDP features three 12-pin Pmod connectors: Pmod_A, Pmod_B, and Pmod_C. -The functionality of the Pmod connectors is programmable and includes GPIO, UART, SPI, -I2C, and PWM (Note: support two type UART Pmod interface: UARTA is newer version). -Multiplexing is controlled by software using the PMOD_MUX_CTRL register. - -* Arduino (1x) - -The ARC EM SDP provides an Arduino shield interface. Multiplexing is controlled by software -using the ARDUINO_MUX_CTRL register. Note: some IO must be programmed in group and can't be -set individually, for details see Table 9 in `EM Software Development Platform user guide`_. - -* MikroBUS (1x) - -Note that since the controllers that are mapped to the MikroBUS are shared with the Arduino -controllers, and therefore the MikroBUS functions are only available when the Arduino -multiplexer ARDUINO_MUX_CTRL is in the default mode (GPIO). - -Programming and Debugging -************************* - -Required Hardware and Software -============================== - -To use Zephyr RTOS applications on the EM Software Development Platform board, -a few additional pieces of hardware are required. - -* A micro USB cable to connect the computer. - -* A universal switching power adaptor (110-240V AC to 12 DC), - provided in the package, which used to power the board. - -* :ref:`The Zephyr SDK ` - -* Terminal emulator software for use with the USB-UART. Suggestion: - `Putty Website`_. - -* (optional) A collection of Pmods, Arduino modules, or Mikro modules. - See `Digilent Pmod Modules`_ or develop your custom interfaces to attach - to the Pmod connector. - -Set up the EM Software Development Platform -=========================================== - -To run Zephyr application on EM Software Development Platform, you need to -setup the board correctly. - -* Connect the 12V DC power supply to your board. - -* Connect the digilent usb cable from your host to the board. - -Set up Zephyr Software -====================== - -Building Sample Applications -============================== - -You can try many of the sample applications or tests, but let us discuss -the one called :ref:`hello_world`. -It is found in :zephyr_file:`samples/hello_world`. - -Configuring ------------ - -You may need to write a prj_arc.conf file if the sample doesn't have one. -Next, you can use the menuconfig rule to configure the target. By specifying -``emsdp`` as the board configuration, you can select the ARC EM Software -Development Platform board support for Zephyr. - -.. zephyr-app-commands:: - :board: emsdp - :zephyr-app: samples/hello_world - :goals: menuconfig - - -Building --------- - -You can build an application in the usual way. Refer to -:ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :board: emsdp - :zephyr-app: samples/hello_world - :maybe-skip-config: - :goals: build - -Connecting Serial Output -========================= - -In the default configuration, Zephyr's EM Software Development Platform images -support serial output via the USB-UART on the board. To enable serial output: - -* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) - -* Specify the tty driver name, for example, on Linux this may be - :file:`/dev/ttyUSB0` - -* Set the communication settings to: - - -========= ===== -Parameter Value -========= ===== -Baud: 115200 -Data: 8 bits -Parity: None -Stopbits: 1 -========= ===== - -Debugging -========== - -Using the latest version of Zephyr SDK(>=0.9), you can debug and flash IoT -Development Kit directly. - -One option is to build and debug the application using the usual -Zephyr build system commands. - -.. zephyr-app-commands:: - :board: emsdp - :app: - :goals: debug - -At this point you can do your normal debug session. Set breakpoints and then -'c' to continue into the program. - -The other option is to launch a debug server, as follows. - -.. zephyr-app-commands:: - :board: emsdp - :app: - :goals: debugserver - -Then connect to the debug server at the EM Software Development Platform from a -second console, from the build directory containing the output :file:`zephyr.elf`. - -.. code-block:: console - - $ cd - $ $ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/ \ - arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf - (gdb) target remote localhost:3333 - (gdb) load - (gdb) b main - (gdb) c - -Flashing -======== - -If you just want to download the application to the EM Software Development -Platform's CCM and run, you can do so in the usual way. - -.. zephyr-app-commands:: - :board: emsdp - :app: - :goals: flash - -This command still uses openocd and gdb to load the application elf file to EM -Software Development Platform, but it will load the application and immediately run. -If power is removed, the application will be lost since it wasn't written to flash. - -Most of the time you will not be flashing your program but will instead debug -it using openocd and gdb. The program can be download via the USB cable into -the code and data memories. - -References -********** - -.. target-notes:: - -.. _EM Software Development Platform user guide: - https://www.synopsys.com/dw/ipdir.php?ds=arc-em-software-development-platform - -.. _Digilent Pmod Modules: - http://store.digilentinc.com/pmod-modules - -.. _Putty website: - http://www.putty.org diff --git a/boards/arc/emsdp/emsdp.yaml b/boards/arc/emsdp/emsdp.yaml deleted file mode 100644 index c5a9afc8da4..00000000000 --- a/boards/arc/emsdp/emsdp.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: emsdp -name: EM Software Development Platform (EM11D) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -supported: - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em4.yaml b/boards/arc/emsdp/emsdp_em4.yaml deleted file mode 100644 index 9be5bbca31b..00000000000 --- a/boards/arc/emsdp/emsdp_em4.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: emsdp_em4 -name: EM Software Development Platform (EM4) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em4_defconfig b/boards/arc/emsdp/emsdp_em4_defconfig deleted file mode 100644 index 40c816b1db4..00000000000 --- a/boards/arc/emsdp/emsdp_em4_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM4=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y diff --git a/boards/arc/emsdp/emsdp_em5d.yaml b/boards/arc/emsdp/emsdp_em5d.yaml deleted file mode 100644 index 80cbc08e066..00000000000 --- a/boards/arc/emsdp/emsdp_em5d.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: emsdp_em5d -name: EM Software Development Platform (EM5D) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em5d_defconfig b/boards/arc/emsdp/emsdp_em5d_defconfig deleted file mode 100644 index 2d117c7f42d..00000000000 --- a/boards/arc/emsdp/emsdp_em5d_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM5D=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y -CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em6.yaml b/boards/arc/emsdp/emsdp_em6.yaml deleted file mode 100644 index ce15754d7be..00000000000 --- a/boards/arc/emsdp/emsdp_em6.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: emsdp_em6 -name: EM Software Development Platform (EM6) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -supported: - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em6_defconfig b/boards/arc/emsdp/emsdp_em6_defconfig deleted file mode 100644 index 7bcaa11ecb0..00000000000 --- a/boards/arc/emsdp/emsdp_em6_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM6=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y -CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em7d.yaml b/boards/arc/emsdp/emsdp_em7d.yaml deleted file mode 100644 index e3591d300f5..00000000000 --- a/boards/arc/emsdp/emsdp_em7d.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: emsdp_em7d -name: EM Software Development Platform (EM7D) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em7d_defconfig b/boards/arc/emsdp/emsdp_em7d_defconfig deleted file mode 100644 index 5c10716fe75..00000000000 --- a/boards/arc/emsdp/emsdp_em7d_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM7D=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y diff --git a/boards/arc/emsdp/emsdp_em7d_esp.yaml b/boards/arc/emsdp/emsdp_em7d_esp.yaml deleted file mode 100644 index 2b8cc296bb8..00000000000 --- a/boards/arc/emsdp/emsdp_em7d_esp.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: emsdp_em7d_esp -name: EM Software Development Platform (EM7D_ESP) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -supported: - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em7d_esp_defconfig b/boards/arc/emsdp/emsdp_em7d_esp_defconfig deleted file mode 100644 index b67dca68179..00000000000 --- a/boards/arc/emsdp/emsdp_em7d_esp_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM7D_ESP=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y -CONFIG_ARC_HAS_SECURE=y -CONFIG_TRUSTED_EXECUTION_SECURE=y -CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em9d.yaml b/boards/arc/emsdp/emsdp_em9d.yaml deleted file mode 100644 index f20f29d18d0..00000000000 --- a/boards/arc/emsdp/emsdp_em9d.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: emsdp_em9d -name: EM Software Development Platform (EM9D) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -supported: - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em9d_defconfig b/boards/arc/emsdp/emsdp_em9d_defconfig deleted file mode 100644 index 5a7342f67b2..00000000000 --- a/boards/arc/emsdp/emsdp_em9d_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM9D=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y -CONFIG_SPI=y diff --git a/boards/arc/hsdk/Kconfig.board b/boards/arc/hsdk/Kconfig.board deleted file mode 100644 index 975d2f5ab24..00000000000 --- a/boards/arc/hsdk/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# DesignWare ARC HS Development Kit board configuration - -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HSDK - bool "ARC HS Development Kit" - depends on SOC_ARC_HSDK - help - The DesignWare ARC HS Development Kit is a ready-to-use platform for - rapid software development on the ARC HS3x family of processors. It - supports single- and multi-core ARC HS34, HS36 and HS38 processors - and offers a wide range of interfaces diff --git a/boards/arc/hsdk/Kconfig.defconfig b/boards/arc/hsdk/Kconfig.defconfig deleted file mode 100644 index c6ba3652de5..00000000000 --- a/boards/arc/hsdk/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HSDK - -config BOARD - default "hsdk" - -if SPI_DW - -config SPI_DW_ACCESS_WORD_ONLY - default y - -endif # SPI_DW - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 200 - -endif #I2C_DW - -endif # BOARD_HSDK diff --git a/boards/arc/hsdk/board.cmake b/boards/arc/hsdk/board.cmake deleted file mode 100644 index 40d4c22d3b5..00000000000 --- a/boards/arc/hsdk/board.cmake +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd "--use-elf") - -if(${CONFIG_MP_MAX_NUM_CPUS} EQUAL 2) -board_runner_args(openocd "--config=${CMAKE_CURRENT_LIST_DIR}/support/openocd-2-cores.cfg") -endif() - -board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/arc/hsdk/hsdk_2cores.yaml b/boards/arc/hsdk/hsdk_2cores.yaml deleted file mode 100644 index d21fa765887..00000000000 --- a/boards/arc/hsdk/hsdk_2cores.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: hsdk_2cores -name: HS Development Kit(2 cores) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools - - arcmwdt -supported: - - smp -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/hsdk/hsdk_2cores_defconfig b/boards/arc/hsdk/hsdk_2cores_defconfig deleted file mode 100644 index ccc920e7103..00000000000 --- a/boards/arc/hsdk/hsdk_2cores_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_HSDK=y -CONFIG_BOARD_HSDK=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 diff --git a/boards/arc/hsdk4xd/Kconfig.board b/boards/arc/hsdk4xd/Kconfig.board deleted file mode 100644 index 76819350da3..00000000000 --- a/boards/arc/hsdk4xd/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# DesignWare ARC HSDK4XD Development Kit board configuration - -# Copyright (c) 2023 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HSDK4XD - bool "ARC HSDK4XD Development Kit" - depends on SOC_ARC_HSDK4XD - help - The ARC HS4x/4xD Development Kit is a ready-to-use software development - platform for the ARC HS4x/4xD family of processor IP. It includes - a multicore ARC HS4x/HS4xD-based chip and integrates a wide range - of interfaces. diff --git a/boards/arc/hsdk4xd/Kconfig.defconfig b/boards/arc/hsdk4xd/Kconfig.defconfig deleted file mode 100644 index cabe258f68f..00000000000 --- a/boards/arc/hsdk4xd/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HSDK4XD - -config BOARD - default "hsdk4xd" - -endif #BOARD_HSDK4XD diff --git a/boards/arc/hsdk4xd/board.cmake b/boards/arc/hsdk4xd/board.cmake deleted file mode 100644 index 04fb70c5dad..00000000000 --- a/boards/arc/hsdk4xd/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd "--use-elf") - -board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/arc/hsdk4xd/doc/index.rst b/boards/arc/hsdk4xd/doc/index.rst deleted file mode 100644 index ee59fe32d2c..00000000000 --- a/boards/arc/hsdk4xd/doc/index.rst +++ /dev/null @@ -1,557 +0,0 @@ -.. _hsdk4xd: - -DesignWare(R) ARC(R) HS4x/HS4xD Development Kit -############################################### - -Overview -******** - -The ARC HS4x/HS4xD Development Kit is the next revision of :ref:`Synopsys HSDK board `. -It includes a multicore ARC HS4xD-based chip that integrates a wide range of interfaces -including Ethernet, HDMI, WiFi, Bluetooth, USB, SDIO, I2C, SPI, UART, I2S, ADC, PWM and GPIO, -as well as a Think Silicon GPU. - -.. image:: hsdk4xd.jpg - :align: center - :alt: DesignWare(R) ARC(R) HS4x/HS4xD Development Kit (synopsys.com) - -For details about the board, see: `ARC HS4x/HS4xD Development Kit -(HSDK4xD) `__ - -Hardware -******** - -The ARC HSDK4xD has 24 general GPIOs, which divided into 8 groups named from ``GPIO_SEL_0`` to ``GPIO_SEL_7``. -Each sel can configured for different functions, such as: GPIO, UART, SPI, I2C and PWM. We can program -``CREG_GPIO_MUX`` register to do configuration for each sel. Tables below show the bit definition for -``CREG_GPIO_MUX`` register and the details configuration for each pin. - -+--------+-------------+---------+--------------+---------------------------------+ -| Bit | Name | Access | Reset value | Description | -+--------+-------------+---------+--------------+---------------------------------+ -| 2:0 | GPIO_SEL_0 | RW | 0x0 | GPIO mux select for gpio[3:0] | -+--------+-------------+---------+--------------+---------------------------------+ -| 5:3 | GPIO_SEL_1 | RW | 0x0 | GPIO mux select for gpio[7:4] | -+--------+-------------+---------+--------------+---------------------------------+ -| 8:6 | GPIO_SEL_2 | RW | 0x0 | GPIO mux select for gpio[11:8] | -+--------+-------------+---------+--------------+---------------------------------+ -| 11:9 | GPIO_SEL_3 | RW | 0x0 | GPIO mux select for gpio[15:12] | -+--------+-------------+---------+--------------+---------------------------------+ -| 14:12 | GPIO_SEL_4 | RW | 0x0 | GPIO mux select for gpio[17:16] | -+--------+-------------+---------+--------------+---------------------------------+ -| 17:15 | GPIO_SEL_5 | RW | 0x0 | GPIO mux select for gpio[19:18] | -+--------+-------------+---------+--------------+---------------------------------+ -| 20:18 | GPIO_SEL_6 | RW | 0x0 | GPIO mux select for gpio[21:20] | -+--------+-------------+---------+--------------+---------------------------------+ -| 23:21 | GPIO_SEL_7 | RW | 0x0 | GPIO mux select for gpio[23:22] | -+--------+-------------+---------+--------------+---------------------------------+ - -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SELS | GPIO PINS | FUN0 | FUN1 | FUN2 | FUN3 | FUN4 | FUN5 | FUN6 | FUN7 | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL0 | 0 | gpio[0] | uart0_cts | spi1_cs[0] | gpio[0] | gpio[0] | pwm_ch[6] | pwm_ch[6] | pwm_ch[1] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 1 | gpio[1] | uart0_txd | spi1_mosi | gpio[1] | pwm_ch[0] | gpio[1] | pwm_ch[0] | pwm_ch[0] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 2 | gpio[2] | uart0_rxd | spi1 _miso | i2c1_scl | gpio[2] | gpio[2] | gpio[2] | gpio[2] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 3 | gpio[3] | uart0_rts | spi1_clk | i2c1_sda | gpio[3] | gpio[3] | gpio[3] | gpio[3] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL1 | 4 | gpio[4] | uart1_cts | spi2_cs[0] | gpio[4] | gpio[4] | pwm_ch[4] | pwm_ch[4] | pwm_ch[3] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 5 | gpio[5] | uart1_txd | spi2_mosi | gpio[5] | pwm_ch[2] | gpio[5] | pwm_ch[2] | pwm_ch[2] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 6 | gpio[6] | uart1_rxd | spi2_miso | i2c2_scl | gpio[6] | gpio[6] | gpio[6] | gpio[6] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 7 | gpio[7] | uart1_rts | spi2_clk | i2c2_sda | gpio[7] | gpio[7] | gpio[7] | gpio[7] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL2 | 8 | gpio[8] | uart2_cts | spi1_cs[1] | gpio[8] | gpio[8] | pwm_ch[2] | pwm_ch[2] | pwm_ch[5] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 9 | gpio[9] | uart2_txd | spi1_mosi | gpio[9] | pwm_ch[4] | gpio[9] | pwm_ch[4] | pwm_ch[4] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 10 | gpio[10] | uart2_rxd | spi1_miso | i2c1_scl | gpio[10] | gpio[10] | gpio[10] | gpio[10] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 11 | gpio[11] | uart2_rts | spi1_clk | i2c1_sda | gpio[11] | gpio[11] | gpio[11] | gpio[11] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL3 | 12 | gpio[12] | uart0_cts | spi2_cs[1] | gpio[12] | gpio[12] | pwm_ch[0] | pwm_ch[0] | pwm_ch[7] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 13 | gpio[13] | uart0_txd | spi2_mosi | gpio[13] | pwm_ch[6] | gpio[13] | pwm_ch[6] | pwm_ch[6] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 14 | gpio[14] | uart0_rxd | spi2_miso | i2c2_scl | gpio[14] | gpio[14] | gpio[14] | gpio[14] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 15 | gpio[15] | uart0_rts | spi2_clk | i2c2_sda | gpio[15] | gpio[15] | gpio[15] | gpio[15] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL4 | 16 | gpio[16] | uart1_txd | spi1_cs[2] | i2c1_scl | gpio[16] | pwm_fault_0 | gpio[16] | pwm_fault_0 | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 17 | gpio[17] | uart1_rxd | spi1_mosi | i2c1_sda | pwm_ch[0] | pwm_ch[0] | pwm_ch[5] | pwm_ch[5] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL5 | 18 | gpio[18] | uart2_txd | spi1_miso | i2c2_scl | gpio[18] | gpio[18] | gpio[18] | gpio[18] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 19 | gpio[19] | uart2_rxd | spi1_clk | i2c2_sda | gpio[19] | gpio[19] | gpio[19] | gpio[19] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL6 | 20 | gpio[20] | uart0_txd | spi2_cs[2] | i2c1_scl | gpio[20] | pwm_fault_1 | gpio[20] | pwm_fault_1 | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 21 | gpio[21] | uart0_rxd | spi2_mosi | i2c1_sda | pwm_ch[6] | pwm_ch[6] | pwm_ch[3] | pwm_ch[3] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL7 | 22 | gpio[22] | uart2_txd | spi2_miso | i2c2_scl | gpio[22] | gpio[22] | gpio[22] | gpio[22] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 23 | gpio[23] | uart2_rxd | spi2_clk | i2c2_sda | gpio[23] | gpio[23] | gpio[23] | gpio[23] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ - -Digilent Pmod -============= - -The ARC HSDK4xD features two 12-pin Pmod connectors ``Pmod_A`` and ``Pmod_B`` and one 6-pin Pmod connector ``Pmod_C``. -The functionality of the Pmod connectors is programmable and includes GPIO, UART, SPI, I2C and PWM. -The location of the pins on the Pmod connectors is shown in Figure below. Detailed pin descriptions -depending on the pin multiplexer settings are provided in the subsequent sections. - -.. image:: pinout_diagram_of_the_pmod.jpg - :align: center - :alt: Pinout Diagram of the Pmod - -Pmod_A Connector ----------------- - -Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_A`` -connector. The GPIO column is the default assignment after Reset. - -+------+-----------+------------+-------------+-----------+------------+-----------+ -| Pin | GPIO | UART | SPI | I2C | PWM_1 | PWM_2 | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A1 | gpio[8] | uart2_cts | spi1_cs[1] | gpio[8] | gpio[8] | pwm_ch[2] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A2 | gpio[9] | uart2_txd | spi1_mosi | gpio[9] | pwm_ch[4] | gpio[9] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A3 | gpio[10] | uart2_rxd | spi1_miso | i2c1_scl | gpio[10] | gpio[10] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A4 | gpio[11] | uart2_rts | spi1_clk | i2c1_sda | gpio[11] | gpio[11] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A5 | GND | GND | GND | GND | GND | GND | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A7 | gpio[20] | gpio[20] | gpio[20] | gpio[20] | gpio[20] | gpio[20] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A8 | gpio[21] | gpio[21] | gpio[21] | gpio[21] | gpio[21] | gpio[21] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A9 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A10 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A11 | GND | GND | GND | GND | GND | GND | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A12 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | -+------+-----------+------------+-------------+-----------+------------+-----------+ - -Pmod_B Connector ----------------- - -Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_B`` -connector. The GPIO column is the default assignment after Reset. - -+------+-----------+------------+-------------+-----------+------------+-----------+ -| Pin | GPIO | UART | SPI | I2C | PWM_1 | PWM_2 | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B1 | gpio[12] | uart0_cts | spi2_cs[1] | gpio[12] | gpio[12] | pwm_ch[0] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B2 | gpio[13] | uart0_txd | spi2_mosi | gpio[13] | pwm_ch[6] | gpio[13] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B3 | gpio[14] | uart0_rxd | spi2_miso | i2c2_scl | gpio[14] | gpio[14] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B4 | gpio[15] | uart0_rts | spi2_clk | i2c2_sda | gpio[15] | gpio[15] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B5 | GND | GND | GND | GND | GND | GND | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B7 | gpio[22] | gpio[22] | gpio[22] | gpio[22] | gpio[22] | gpio[22] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B8 | gpio[23] | gpio[23] | gpio[23] | gpio[23] | gpio[23] | gpio[23] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B9 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B10 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B11 | GND | GND | GND | GND | GND | GND | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B12 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | -+------+-----------+------------+-------------+-----------+------------+-----------+ - -Pmod_C Connector ----------------- - -Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_C`` -connector. The GPIO column is the default assignment after Reset. - -+------+-----------+------------+-------------+-----------+-----------+ -| Pin | GPIO | UART | SPI | I2C | PWM | -+------+-----------+------------+-------------+-----------+-----------+ -| C1 | gpio[16] | uart1_txd | spi1_cs[2] | i2c1_scl | gpio[16] | -+------+-----------+------------+-------------+-----------+-----------+ -| C2 | gpio[17] | uart1_rxd | spi1_mosi | i2c1_sda | pwm_ch[0] | -+------+-----------+------------+-------------+-----------+-----------+ -| C3 | gpio[18] | uart2_txd | spi1_miso | i2c2_scl | gpio[18] | -+------+-----------+------------+-------------+-----------+-----------+ -| C4 | gpio[19] | uart2_rxd | spi1_clk | i2c2_sda | gpio[19] | -+------+-----------+------------+-------------+-----------+-----------+ -| C5 | GND | GND | GND | GND | GND | -+------+-----------+------------+-------------+-----------+-----------+ -| C6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | -+------+-----------+------------+-------------+-----------+-----------+ - -Mikrobus -======== - -The ARC HSDK4xD features a set of MikroBUS headers. Figure below shows the relevant function assignments, -fully compatible with the MikroBUS standard. Table below shows the pin assignment on the I/O Multiplexer. - -.. image:: mikrobus_header.jpg - :align: center - :alt: mikrobus header - -+-------+-----------------+------+-----------+ -| Pin | I/O | Pin | I/O | -+-------+-----------------+------+-----------+ -| AN | ADC VIN6* | PWM | pwm_ch[0] | -+-------+-----------------+------+-----------+ -| RST | GPX_Port0_bit1 | INT | gpio[16] | -+-------+-----------------+------+-----------+ -| CS | spi2_cs[1] | RX | uart2_rxd | -+-------+-----------------+------+-----------+ -| SCK | spi2_clk | TX | uart2_txd | -+-------+-----------------+------+-----------+ -| MISO | spi2_miso | SCL | i2c2_scl | -+-------+-----------------+------+-----------+ -| MOSI | spi2_mosi | SDA | i2c2_sda | -+-------+-----------------+------+-----------+ - -.. note:: - ADC VIN6 is available through the on-board ADC and is - read though SPI0 using SPI chip select 1. - -Arduino -======= - -The ARC HSDK4xD provides an Arduino shield interface. Figure below shows the relevant -function assignments. The Arduino shield interface is compatible with the Arduino UNO -R3 with the following exceptions: 5 Volt shields are not supported, the IOREF voltage on -the ARC HSDK4xD board is fixed to 3V3. Note that the ICSP header is also not available. Most -shields do not require this ICSP header as the SPI master interface on this ICSP header -is also available on the ``IO10`` to ``IO13`` pins. - -.. image:: arduino_shield_interface.jpg - :align: center - :alt: arduino shield interface - -Table below shows the pin assignment on the I/O Multiplexer. Multiplexing is controlled by software -using the ``CREG_GPIO_MUX`` register (see Pinmux ). After a reset, all ports are configured as GPIO inputs. - -+-------+------------+-----------------+------------+ -| Pin | I/O-1 | I/O-2 | I/O-3 | -+-------+------------+-----------------+------------+ -| AD0 | ADC VIN0* | GPX_port0_bit2 | - | -+-------+------------+-----------------+------------+ -| AD1 | ADC VIN1* | GPX_port0_bit3 | - | -+-------+------------+-----------------+------------+ -| AD2 | ADC VIN2* | GPX_port0_bit4 | - | -+-------+------------+-----------------+------------+ -| AD3 | ADC VIN3* | GPX_port0_bit5 | - | -+-------+------------+-----------------+------------+ -| AD4 | ADC VIN4* | gpio[18] | i2c2_sda | -+-------+------------+-----------------+------------+ -| AD5 | ADC VIN5* | gpio[19] | i2c2_scl | -+-------+------------+-----------------+------------+ -| IO0 | gpio[23] | uart2_rxd | - | -+-------+------------+-----------------+------------+ -| IO1 | gpio[22] | uart2_txd | - | -+-------+------------+-----------------+------------+ -| IO2 | gpio[16] | - | - | -+-------+------------+-----------------+------------+ -| IO3 | gpio[17] | pwm_ch[5] | - | -+-------+------------+-----------------+------------+ -| IO4 | gpio[11] | - | | -+-------+------------+-----------------+------------+ -| IO5 | gpio[9] | pwm_ch[4] | - | -+-------+------------+-----------------+------------+ -| IO6 | gpio[21] | pwm_ch[3] | - | -+-------+------------+-----------------+------------+ -| IO7 | gpio[20] | - | - | -+-------+------------+-----------------+------------+ -| IO8 | gpio[10] | - | - | -+-------+------------+-----------------+------------+ -| IO9 | gpio[8] | pwm_ch[2] | - | -+-------+------------+-----------------+------------+ -| IO10 | gpio[12] | pwm_ch[0] | spi2_cs[1] | -+-------+------------+-----------------+------------+ -| IO11 | gpio[13] | pwm_ch[6] | spi2_mosi | -+-------+------------+-----------------+------------+ -| IO12 | gpio[14] | - | spi2_miso | -+-------+------------+-----------------+------------+ -| IO13 | gpio[15] | - | spi2_clk | -+-------+------------+-----------------+------------+ - -I/O expander -============ - -The ARC HSDK4xD board includes a CY8C9520A I/O expander from `Cypress CY8C9520A -`__. The I/O -expander offers additional GPIO signals and board control signals and can be accessed -through the on-board I2C bus, we have implemented a basic driver for it. -Tables below shows an overview of relevant I/O signals. - -+------------+---------------------------------------------+ -| Pins | Usage | -+------------+---------------------------------------------+ -| port0_bit0 | RS9113 Bluetooth I2S RX enable (active low) | -+------------+---------------------------------------------+ -| port0_bit1 | mikroBUS Reset (active low) | -+------------+---------------------------------------------+ -| port0_bit2 | GPIO for Arduino AD0 | -+------------+---------------------------------------------+ -| port0_bit3 | GPIO for Arduino AD1 | -+------------+---------------------------------------------+ -| port0_bit4 | GPIO for Arduino AD2 | -+------------+---------------------------------------------+ -| port0_bit5 | GPIO for Arduino AD3 | -+------------+---------------------------------------------+ -| port1_bit4 | On-board user LED0 | -+------------+---------------------------------------------+ -| port1_bit5 | On-board user LED1 | -+------------+---------------------------------------------+ -| port1_bit6 | On-board user LED2 | -+------------+---------------------------------------------+ -| port1_bit7 | On-board user LED3 | -+------------+---------------------------------------------+ - -On-board user LEDS -================== - -The ARC HSDK4xD includes 4 user LEDs(active high), which can be controlled through the I/O expander pins. - -+-------+-----------------+ -| LEDs | PINs | -+-------+-----------------+ -| LED0 | GPX_port1_bit4 | -+-------+-----------------+ -| LED1 | GPX_port1_bit5 | -+-------+-----------------+ -| LED2 | GPX_port1_bit6 | -+-------+-----------------+ -| LED3 | GPX_port1_bit7 | -+-------+-----------------+ - -For hardware feature details, refer to : `Designware HS4x/HS4xD Development Kit website -`__. - -Programming and Debugging -************************* - -Required Hardware and Software -============================== - -To use Zephyr RTOS applications on the HS4x/HS4xD Development Kit board, a few -additional pieces of hardware are required. - -* A micro USB cable provides USB-JTAG debug and USB-UART communication - to the board - -* A universal switching power adaptor (110-240V - AC to 12V DC), provided in the package, provides power to the board. - -* :ref:`The Zephyr SDK ` - -* Terminal emulator software for use with the USB-UART. Suggestion: - `Putty Website`_. - -* (optional) A collection of Pmods, Arduino modules, or Mikro modules. - See `Digilent Pmod Modules`_ or develop your custom interfaces to attach - to the Pmod connector. - -Set up the ARC HS4x/HS4xD Development Kit -========================================= - -To run Zephyr application on ARC HS4x/HS4xD Development Kit, you need to -set up the board correctly. - -* Connect the digilent USB cable from your host to the board. - -* Connect the 12V DC power supply to your board - -Set up Zephyr Software -====================== - -Building Sample Applications -============================== - -You can try many of the :ref:`sample applications and demos -`. We'll use :ref:`hello_world`, found in -:zephyr_file:`samples/hello_world` as an example. - -Configuring ------------ - -You may need to write a ``prj_arc.conf`` file if the sample doesn't have one. -Next, you can use the menuconfig rule to configure the target. By specifying -``hsdk4xd`` as the board configuration, you can select the ARC HS4x/HS4xD Development -Kit board support for Zephyr. - -.. zephyr-app-commands:: - :board: hsdk4xd - :zephyr-app: samples/hello_world - :goals: menuconfig - - -Building --------- - -You can build an application in the usual way. Refer to -:ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :board: hsdk4xd - :zephyr-app: samples/hello_world - :maybe-skip-config: - :goals: build - - -Connecting Serial Output -========================= - -In the default configuration, Zephyr's HS4x/HS4xD Development Kit images support -serial output via the USB-UART on the board. To enable serial output: - -* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) - -* Specify the tty driver name, for example, on Linux this may be - :file:`/dev/ttyUSB0` - -* Set the communication settings to: - - -========= ===== -Parameter Value -========= ===== -Baud: 115200 -Data: 8 bits -Parity: None -Stopbits: 1 -========= ===== - -Debugging -========== - -Using the latest version of Zephyr SDK(>=0.15.2), you can debug and -flash (run) HS4x/HS4xD Development Kit directly. - -One option is to build and debug the application using the usual -Zephyr build system commands. - -.. zephyr-app-commands:: - :board: hsdk4xd - :app: - :goals: debug - -At this point you can do your normal debug session. Set breakpoints and then -:kbd:`c` to continue into the program. - -The other option is to launch a debug server, as follows. - -.. zephyr-app-commands:: - :board: hsdk4xd - :app: - :goals: debugserver - -Then connect to the debug server at the HS4x/HS4xD Development Kit from a second -console, from the build directory containing the output :file:`zephyr.elf`. - -.. code-block:: console - - $ cd - $ $ZEPHYR_SDK_INSTALL_DIR/arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf - (gdb) target remote localhost:3333 - (gdb) load - (gdb) b main - (gdb) c - -Flashing -======== - -If you just want to download the application to the HS4x/HS4xD Development Kit's DDR -and run, you can do so in the usual way. - -.. zephyr-app-commands:: - :board: hsdk4xd - :app: - :goals: flash - -This command still uses openocd and gdb to load the application elf file to -HS4x/HS4xD Development Kit, but it will load the application and immediately run. If -power is removed, the application will be lost since it wasn't written to flash. - -Most of the time you will not be flashing your program but will instead debug -it using openocd and gdb. The program can be download via the USB cable into -the code and data memories. - -The HS4x/HS4xD Development Kit also supports flashing the Zephyr application -with the U-Boot bootloader, a powerful and flexible tool for loading -an executable from different sources and running it on the target platform. - -The U-Boot implementation for the HS4x/HS4xD Development Kit was further extended with -additional functionality that allows users to better manage the broad -configurability of the HS4x/HS4xD Development Kit - -When you are ready to deploy the program so that it boots up automatically on -reset or power-up, you can follow the steps to place the program on SD card. - -For details, see: `Uboot-HS4x/HS4xD-Command-Reference -`__ - -Supported peripheral -==================== - -The following list indicates the state of HS4x/HS4xD Development Kit peripherals’ support - -+------------+---------+ -| Peripheral | Support | -+------------+---------+ -| ADC | No | -+------------+---------+ -| Bluetooth | No | -+------------+---------+ -| Ethernet | No | -+------------+---------+ -| GPIO | No | -+------------+---------+ -| GPU | No | -+------------+---------+ -| HDMI | No | -+------------+---------+ -| I2C | No | -+------------+---------+ -| I2S | No | -+------------+---------+ -| PWM | No | -+------------+---------+ -| SDIO | No | -+------------+---------+ -| SPI | No | -+------------+---------+ -| UART | Yes | -+------------+---------+ -| USB | No | -+------------+---------+ -| WiFi | No | -+------------+---------+ - -References -********** - -.. _embARC website: https://www.embarc.org - -.. _Designware HS Development Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit - -.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules - -.. _Putty website: http://www.putty.org diff --git a/boards/arc/hsdk4xd/hsdk4xd.dts b/boards/arc/hsdk4xd/hsdk4xd.dts deleted file mode 100644 index e58b349c362..00000000000 --- a/boards/arc/hsdk4xd/hsdk4xd.dts +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2023, Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include "hsdk4xd.dtsi" - -/ { - model = "hsdk4xd"; - compatible = "snps,hsdk4xd"; -}; diff --git a/boards/arc/hsdk4xd/hsdk4xd.dtsi b/boards/arc/hsdk4xd/hsdk4xd.dtsi deleted file mode 100644 index 1e0fa062b98..00000000000 --- a/boards/arc/hsdk4xd/hsdk4xd.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2023, Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - - aliases { - uart-dbg = &uart_dbg; - }; - - chosen { - zephyr,sram = &ddr0; - zephyr,console = &uart_dbg; - zephyr,shell-uart = &uart_dbg; - }; - -}; - -arduino_spi: &spi2 {}; - -&uart_dbg { - status = "okay"; - current-speed = <115200>; -}; - -&creg_gpio { - status = "okay"; -}; diff --git a/boards/arc/index.rst b/boards/arc/index.rst deleted file mode 100644 index 816048df0ac..00000000000 --- a/boards/arc/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-arc: - -ARC Boards -########## - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/arc/iotdk/Kconfig.board b/boards/arc/iotdk/Kconfig.board deleted file mode 100644 index a92c55ec740..00000000000 --- a/boards/arc/iotdk/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# DesignWare ARC IoT Development Kit board configuration - -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_IOTDK - bool "ARC IoT Development Kit" - depends on SOC_ARC_IOT - help - The DesignWare ARC IoT Development Kit board is a versatile platform that includes the necessary hardware and software to accelerate software development and debugging of sensor fusion, voice recognition and face detection designs. It includes a silicon implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on SMIC's 55-nm ultra-low power process, and a rich set of peripherals commonly used in IoT designs such as USB, UART, SPI, I2C, PWM, SDIO and ADCs. diff --git a/boards/arc/iotdk/Kconfig.defconfig b/boards/arc/iotdk/Kconfig.defconfig deleted file mode 100644 index 93f707a0afb..00000000000 --- a/boards/arc/iotdk/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "iotdk" - depends on BOARD_IOTDK diff --git a/boards/arc/iotdk/board.cmake b/boards/arc/iotdk/board.cmake deleted file mode 100644 index 292253eb64e..00000000000 --- a/boards/arc/iotdk/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(openocd "--use-elf") -board_runner_args(mdb-hw "--jtag=digilent") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/arc/iotdk/board.dtsi b/boards/arc/iotdk/board.dtsi deleted file mode 100644 index 0f1a02d0213..00000000000 --- a/boards/arc/iotdk/board.dtsi +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - diff --git a/boards/arc/nsim/Kconfig.board b/boards/arc/nsim/Kconfig.board deleted file mode 100644 index 6bec8088323..00000000000 --- a/boards/arc/nsim/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# DesignWare ARC nSIM simulated platform configuration - -# Copyright (c) 2016, 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NSIM - bool "ARC nSIM simulator" - depends on SOC_NSIM - select HAS_COVERAGE_SUPPORT - help - The DesignWare ARC nSIM board is a virtual board based on - the ARC nSIM simulator. It demonstrates the ARC core features - and a console based on the ns16550 UART model. diff --git a/boards/arc/nsim/Kconfig.defconfig b/boards/arc/nsim/Kconfig.defconfig deleted file mode 100644 index 1f1e19ee38a..00000000000 --- a/boards/arc/nsim/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NSIM - -config BOARD - default "nsim" - -endif # BOARD_NSIM diff --git a/boards/arc/nsim/doc/index.rst b/boards/arc/nsim/doc/index.rst deleted file mode 100644 index 4e7054fc43b..00000000000 --- a/boards/arc/nsim/doc/index.rst +++ /dev/null @@ -1,339 +0,0 @@ -.. _nsim: - -DesignWare ARC nSIM and HAPS FPGA boards -######################################## - -Overview -******** - -This platform can be used to run Zephyr RTOS on the widest possible range of ARC processors in -simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The -platform includes the following features: - -* ARC processor core, which implements ARCv2 or ARCv3 ISA, please refer to - :ref:`here ` for a complete list of ARC processor families which - currently supported -* Virtual serial console (a standard ``ns16550`` UART model) - -ARC processors are known for being highly customizable and some but not all of the configurations -are currently supported in the Zephyr RTOS for ARC, again please refer to -:ref:`here ` for a complete list of supported features. - -There are multiple supported sub-configurations for that platform. Some but not all of currently -available configurations are listed below: - -* ``nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and - XY-memory -* ``nsim_em_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's -* ``nsim_em_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options and - XY-memory -* ``nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4 -* ``nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3 -* ``nsim_hs_smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3 -* ``nsim_vpx5`` - ARCv2 VPX5 core, close to vpx5_integer_full template -* ``nsim_hs5x`` - 32-bit ARCv3 HS core with rich set of options -* ``nsim_hs6x`` - 64-bit ARCv3 HS core with rich set of options -* ``nsim_hs5x_smp_12cores`` - SMP 12 cores 32-bit ARCv3 HS platform -* ``nsim_hs6x_smp_12cores`` - SMP 12 cores 64-bit ARCv3 HS platform - -.. _board_arc_nsim_prop_args_files: - -It is recommended to look at precise description of a particular sub-configuration in either -``.props`` or ``.args`` files in :zephyr_file:`boards/arc/nsim/support/` directory to understand -which options are configured and so will be used on invocation of the simulator. - -In case of single-core configurations it would be ``.props`` file which contains configuration -for nSIM simulator and ``.args`` file which contains configuration for MetaWare debugger (MDB). -Note that these files contain identical HW configuration and meant to be used with the corresponding -tool: ``.props`` file for nSIM simulator and ``.args`` file for MDB (which internally uses nSIM for -simulation anyway). - -.. hint:: - If different behavior is observed during execution or debugging of a particular application - (especially after creation of a new board or modification of the existing one) make sure features - defined in ``.props`` and ``.args`` are semantically identical (unfortunately options of - nSIM & MDB don't exactly match, so care should be taken). - -I.e. for the single-core ``nsim_hs5x`` platform there are -:zephyr_file:`boards/arc/nsim/support/nsim_hs5x.props` and -:zephyr_file:`boards/arc/nsim/support/mdb_hs5x.args`. - -For the multi-core configurations there is only ``.args`` file as the multi-core configuration -can only be instantiated with help of MDB. - -I.e. for the multi-core ``nsim_hs5x_smp`` platform there is only -:zephyr_file:`boards/arc/nsim/support/mdb_hs5x_smp.args`. - -.. warning:: - All nSIM/MDB configurations are used for demo and testing purposes. They are not meant to - represent any real system and so might be renamed, removed or modified at any point. - -Programming and Debugging -************************* - -Required Hardware and Software -============================== - -To run single-core Zephyr RTOS applications in simulation on this board, -either `DesignWare ARC nSIM`_ or `DesignWare ARC Free nSIM`_ is required. - -To run multi-core Zephyr RTOS applications in simulation on this board, -`DesignWare ARC nSIM`_ and MetaWare Debugger from `ARC MWDT`_ are required. - -To run Zephyr RTOS applications on FPGA-based `HAPS`_ platform, -MetaWare Debugger from `ARC MWDT`_ is required as well as the HAPS platform itself. - -Building & Running Sample Applications -====================================== - -Most board sub-configurations support building with both GNU and ARC MWDT toolchains, however -there might be exceptions from that, especially for newly added targets. You can check supported -toolchains for the sub-configurations in the corresponding ``.yaml`` file. - -I.e. for the ``nsim_hs5x`` board we can check :zephyr_file:`boards/arc/nsim/nsim_hs5x.yaml` - -The supported toolchains are listed in ``toolchain:`` array in ``.yaml`` file, where we can find: - -* **zephyr** - implies ARC GNU toolchain from Zephyr SDK. You can find more information about - Zephyr SDK :ref:`here `. -* **cross-compile** - implies ARC GNU cross toolchain, which is not a part of Zephyr SDK. Note that - some (especially new) sub-configurations may declare ``cross-compile`` toolchain support without - ``zephyr`` toolchain support because corresponding target CPU support hasn't been added to Zephyr - SDK yet. You can find more information about its usage here: :ref:`here `. -* **arcmwdt** - implies proprietary ARC MWDT toolchain. You can find more information about its - usage here: :ref:`here `. - -.. note:: - Note that even if both GNU and MWDT toolchain support is declared for the target some tests or - samples can be only built with either GNU or MWDT toolchain due to some features limited to a - particular toolchain. - -Use this configuration to run basic Zephyr applications and kernel tests in -nSIM, for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: nsim_em - :goals: flash - -This will build an image with the synchronization sample app, boot it using -nSIM, and display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.2.0-3948-gd351a024dc87 *** - thread_a: Hello World from cpu 0 on nsim! - thread_b: Hello World from cpu 0 on nsim! - thread_a: Hello World from cpu 0 on nsim! - thread_b: Hello World from cpu 0 on nsim! - thread_a: Hello World from cpu 0 on nsim! - - -.. note:: - To exit the simulator, use :kbd:`Ctrl+]`, then :kbd:`Ctrl+c` - -.. _board_arc_nsim_verbose_build: - -.. tip:: - You can get more details about the building process by running build in verbose mode. It can be - done by passing ``-v`` flag to the west: ``west -v build -b nsim_hs samples/synchronization`` - -You can run applications built for ``nsim`` board not only on nSIM simulation itself, but also on -FPGA based HW platform `HAPS`_. To run previously built application on HAPS do: - -.. code-block:: console - - west flash --runner mdb-hw - -.. note:: - To run on HAPS, in addition to proper build and flash Zephyr image, you need setup HAPS itself - as well as flash proper built FPGA image (aka .bit-file). This instruction doesn't cover those - steps, so you need to follow HAPS manual. - -Debugging -========= - -.. _board_arc_nsim_debugging_mwdt: - -Debugging with MDB ------------------- - -.. note:: - We strongly recommend to debug with MetaWare debugger (MDB) because it: - - * Supports wider range of ARC hardware features - * Allows to debug both single-core and multi-core ``nsim`` targets. - * Allows to debug on `HAPS`_ platform. - -You can use the following command to start GUI debugging when running application on nSIM simulator -(regardless if single- or multi-core configuration is used): - -.. code-block:: console - - west debug --runner mdb-nsim - -You can use the following command to start GUI debugging when running application on `HAPS`_ -platform: - -.. code-block:: console - - west debug --runner mdb-hw - -.. tip:: - The ``west debug`` (as well as ``west flash``) is just a wrapper script and so it's possible to - extract the exact commands which are called in it by running it in verbose mode. For that you - need to pass ``-v`` flag to the wrapper. For example, if you run the following command: - - .. code-block:: console - - west -v debug --runner mdb-nsim - - it will produce the following output (the ``nsim_hs5x_smp`` configuration was used for that - example): - - .. code-block:: console - - < *snip* > - -- west debug: using runner mdb-nsim - runners.mdb-nsim: mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf - runners.mdb-nsim: mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf - runners.mdb-nsim: mdb -multifiles=core1,core0 -OKN - - From that output it's possible to extract MDB commands used for setting-up the GUI debugging - session: - - .. code-block:: console - - mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf - mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf - mdb -multifiles=core1,core0 -OKN - - Then it's possible to use them directly or in some machinery if required. - - .. warning:: - It is strongly recommended to not rely on the mdb command line options listed above but - extract it yourself for your configuration. - - .. note:: - In case of execution or debugging with MDB on multi-core configuration on nSIM - simulator without ``west flash`` and ``west debug`` wrappers it's necessary to - set :envvar:`NSIM_MULTICORE` environment variable to ``1``. If you are using ``west flash`` or - ``west debug`` it's done automatically by wrappers. - - Without :envvar:`NSIM_MULTICORE` environment variable set to 1, MDB will simulate 2 separate - ARC cores which don't share any memory regions with each other and so SMP-enabled code won't - work as expected. - -Debugging with GDB ------------------- - -.. note:: - Debugging on nSIM via GDB is only supported on single-core configurations (which use standalone - nSIM). However if it's possible to launch application on multi-core nsim target that means you - can simply :ref:`debug with MDB debugger `. - It's the nSIM with ARC GDB restriction, real HW multi-core ARC targets can be debugged with ARC - GDB. - -.. note:: - Currently debugging with GDB is not supported on `HAPS`_ platform. - -.. note:: - The normal ``west debug`` command won't work for debugging applications using nsim boards - because both the nSIM simulator and the debugger (either GDB or MDB) use the same console for - input / output. - In case of GDB debugger it's possible to use a separate terminal windows for GDB and nSIM to - avoid intermixing their output. For the MDB debugger simply use GUI mode. - -After building your application, open two terminal windows. In terminal one, use nSIM to start a GDB -server and wait for a remote connection with following command: - -.. code-block:: console - - west debugserver --runner arc-nsim - -In terminal two, connect to the GDB server using ARC GDB. You can find it in Zephyr SDK: - -* for the ARCv2 targets you should use :file:`arc-zephyr-elf-gdb` -* for the ARCv3 targets you should use :file:`arc64-zephyr-elf-gdb` - -This command loads the symbol table from the elf binary file, for example the -:file:`build/zephyr/zephyr.elf` file: - -.. code-block:: console - - arc-zephyr-elf-gdb -ex 'target remote localhost:3333' -ex load build/zephyr/zephyr.elf - -Now the debug environment has been set up, and it's possible to debug the application with gdb -commands. - -Modifying the configuration -*************************** - -If modification of existing nsim configuration is required or even there's a need in creation of a -new one it's required to maintain alignment between - -* Zephyr OS configuration -* nSIM & MDB configuration -* GNU & MWDT toolchain compiler options - -.. note:: - The ``.tcf`` configuration files are not supported by Zephyr directly. There are multiple - reasons for that. ``.tcf`` perfectly suits building of bare-metal single-thread application - - in that case all the compiler options from ``.tcf`` are passed to the compiler, so all the HW - features are used by the application and optimal code is being generated. - The situation is completely different when multi-thread feature-rich operation system is - considered. Of course it is still possible to build all the code with all the - options from ``.tcf`` - but that may be far from optimal solution. For example, such approach - require so save & restore full register context for all tasks (and sometimes even for - interrupts). And for DSP-enabled or for FPU-enabled systems that leads to dozens of extra - registers save and restore even if the most of the user and kernel tasks don't actually use - DSP or FPU. Instead we prefer to fine-tune the HW features usage which (with all its pros) - require us to maintain them separately from ``.tcf`` configuration. - - -Zephyr OS configuration -======================= - -Zephyr OS configuration is defined via Kconfig and Device tree. These are non ARC-specific -mechanisms which are described in :ref:`board porting guide `. - -It is advised to look for ``_defconfig``, ``.dts`` and -``.yaml`` as an entry point for board configuration. - -nSIM configuration -================== - -nSIM configuration is defined in :ref:`props and args files `. -Generally they are identical to the values from corresponding ``.tcf`` configuration with few -exceptions: - -* The UART model is added (to both ``.props`` and ``.args`` files). -* Options to fine-tuned MDB behavior are added (to ``.args`` files only) to disable MDB profiling - and fine-tune MDB behavior on multi-core systems. - -GNU & MWDT toolchain compiler options -===================================== - -The hardware-specific compiler options are set in corresponding SoC cmake file. For ``nsim`` board -it is :zephyr_file:`soc/arc/snps_nsim/CMakeLists.txt`. - -For the GNU toolchain the basic configuration is set via ``-mcpu`` which is defined in generic code -and based on the selected CPU model via Kconfig. It still can be forcefully set to required value -on SoC level. - -For the MWDT toolchain all hardware-specific compiler options are set directly in SoC -``CMakeLists.txt``. - -.. note:: - The non hardware-specific compiler options like optimizations, library selections, C / C++ - language options are still set in Zephyr generic code. It could be observed by - :ref:`running build in verbose mode `. - -References -********** - -.. _Designware ARC nSIM: https://www.synopsys.com/dw/ipdir.php?ds=sim_nsim -.. _DesignWare ARC Free nSIM: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi -.. _HAPS: https://www.synopsys.com/verification/prototyping/haps.html -.. _ARC MWDT: https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware diff --git a/boards/arc/nsim/nsim_em.yaml b/boards/arc/nsim/nsim_em.yaml deleted file mode 100644 index 9eb0c88ad50..00000000000 --- a/boards/arc/nsim/nsim_em.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_em -name: EM Nsim simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_em11d.yaml b/boards/arc/nsim/nsim_em11d.yaml deleted file mode 100644 index a37c9c3888d..00000000000 --- a/boards/arc/nsim/nsim_em11d.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_em11d -name: EM11D Nsim simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_em11d_defconfig b/boards/arc/nsim/nsim_em11d_defconfig deleted file mode 100644 index 494ff760838..00000000000 --- a/boards/arc/nsim/nsim_em11d_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_EM11D=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/arc/nsim/nsim_em7d_v22.yaml b/boards/arc/nsim/nsim_em7d_v22.yaml deleted file mode 100644 index bd2069c8359..00000000000 --- a/boards/arc/nsim/nsim_em7d_v22.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nsim_em7d_v22 -name: EM nSIM simulator (EM7D_v22) -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_em7d_v22_defconfig b/boards/arc/nsim/nsim_em7d_v22_defconfig deleted file mode 100644 index 0a6d7ad5e4c..00000000000 --- a/boards/arc/nsim/nsim_em7d_v22_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_EM7D_V22=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/arc/nsim/nsim_em_defconfig b/boards/arc/nsim/nsim_em_defconfig deleted file mode 100644 index 263c5b27af5..00000000000 --- a/boards/arc/nsim/nsim_em_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_EM=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/arc/nsim/nsim_hs.yaml b/boards/arc/nsim/nsim_hs.yaml deleted file mode 100644 index 18f2a71039a..00000000000 --- a/boards/arc/nsim/nsim_hs.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs -name: HS nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs3x_hostlink.yaml b/boards/arc/nsim/nsim_hs3x_hostlink.yaml deleted file mode 100644 index f23cdc18501..00000000000 --- a/boards/arc/nsim/nsim_hs3x_hostlink.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs3x_hostlink -name: HS3x nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs3x_hostlink_defconfig b/boards/arc/nsim/nsim_hs3x_hostlink_defconfig deleted file mode 100644 index eddd5076c65..00000000000 --- a/boards/arc/nsim/nsim_hs3x_hostlink_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/nsim/nsim_hs5x.yaml b/boards/arc/nsim/nsim_hs5x.yaml deleted file mode 100644 index 14d6cf03f8e..00000000000 --- a/boards/arc/nsim/nsim_hs5x.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs5x -name: HS5x nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - arcmwdt - - cross-compile -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs5x_defconfig b/boards/arc/nsim/nsim_hs5x_defconfig deleted file mode 100644 index 03c5f678869..00000000000 --- a/boards/arc/nsim/nsim_hs5x_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS5X=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arc/nsim/nsim_hs5x_smp.yaml b/boards/arc/nsim/nsim_hs5x_smp.yaml deleted file mode 100644 index 21015ecee69..00000000000 --- a/boards/arc/nsim/nsim_hs5x_smp.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: nsim_hs5x_smp -name: Multi-core HS5x nSIM simulator -type: sim -simulation: mdb-nsim -simulation_exec: mdb -arch: arc -toolchain: - - zephyr - - arcmwdt - - cross-compile -supported: - - smp -testing: - timeout_multiplier: 1.5 - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs5x_smp_12cores.yaml b/boards/arc/nsim/nsim_hs5x_smp_12cores.yaml deleted file mode 100644 index f7f9fa1ec72..00000000000 --- a/boards/arc/nsim/nsim_hs5x_smp_12cores.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: nsim_hs5x_smp_12cores -name: Multi-core HS5x nSIM simulator (12 cores) -type: sim -simulation: mdb-nsim -simulation_exec: mdb -arch: arc -toolchain: - - zephyr - - arcmwdt - - cross-compile -supported: - - smp -testing: - timeout_multiplier: 4 - ignore_tags: - - net - - bluetooth diff --git a/boards/arc/nsim/nsim_hs5x_smp_12cores_defconfig b/boards/arc/nsim/nsim_hs5x_smp_12cores_defconfig deleted file mode 100644 index c27e5d81ede..00000000000 --- a/boards/arc/nsim/nsim_hs5x_smp_12cores_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS5X_SMP=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=12 -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs5x_smp_defconfig b/boards/arc/nsim/nsim_hs5x_smp_defconfig deleted file mode 100644 index ac6baba1858..00000000000 --- a/boards/arc/nsim/nsim_hs5x_smp_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS5X_SMP=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs6x.yaml b/boards/arc/nsim/nsim_hs6x.yaml deleted file mode 100644 index 08b881eb743..00000000000 --- a/boards/arc/nsim/nsim_hs6x.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs6x -name: HS6x nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - arcmwdt - - cross-compile - - zephyr -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs6x_defconfig b/boards/arc/nsim/nsim_hs6x_defconfig deleted file mode 100644 index dfb41bf2215..00000000000 --- a/boards/arc/nsim/nsim_hs6x_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS6X=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arc/nsim/nsim_hs6x_smp.yaml b/boards/arc/nsim/nsim_hs6x_smp.yaml deleted file mode 100644 index d05faa51b29..00000000000 --- a/boards/arc/nsim/nsim_hs6x_smp.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: nsim_hs6x_smp -name: Multi-core HS6x nSIM simulator -type: sim -simulation: mdb-nsim -simulation_exec: mdb -arch: arc -toolchain: - - cross-compile - - zephyr - - arcmwdt -supported: - - smp -testing: - timeout_multiplier: 1.5 - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs6x_smp_12cores.yaml b/boards/arc/nsim/nsim_hs6x_smp_12cores.yaml deleted file mode 100644 index 9abea29aabc..00000000000 --- a/boards/arc/nsim/nsim_hs6x_smp_12cores.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: nsim_hs6x_smp_12cores -name: Multi-core HS6x nSIM simulator (12 cores) -type: sim -simulation: mdb-nsim -simulation_exec: mdb -arch: arc -toolchain: - - cross-compile - - zephyr - - arcmwdt -supported: - - smp -testing: - timeout_multiplier: 4 - ignore_tags: - - net - - bluetooth diff --git a/boards/arc/nsim/nsim_hs6x_smp_12cores_defconfig b/boards/arc/nsim/nsim_hs6x_smp_12cores_defconfig deleted file mode 100644 index 2e14a87ed40..00000000000 --- a/boards/arc/nsim/nsim_hs6x_smp_12cores_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS6X_SMP=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=12 -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs6x_smp_defconfig b/boards/arc/nsim/nsim_hs6x_smp_defconfig deleted file mode 100644 index c34a380d1d0..00000000000 --- a/boards/arc/nsim/nsim_hs6x_smp_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS6X_SMP=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs_defconfig b/boards/arc/nsim/nsim_hs_defconfig deleted file mode 100644 index eddd5076c65..00000000000 --- a/boards/arc/nsim/nsim_hs_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/nsim/nsim_hs_flash_xip.yaml b/boards/arc/nsim/nsim_hs_flash_xip.yaml deleted file mode 100644 index eabe0c9cd84..00000000000 --- a/boards/arc/nsim/nsim_hs_flash_xip.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs_flash_xip -name: HS nSIM simulator (FLASH XIP) -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs_flash_xip_defconfig b/boards/arc/nsim/nsim_hs_flash_xip_defconfig deleted file mode 100644 index e4124a3ed69..00000000000 --- a/boards/arc/nsim/nsim_hs_flash_xip_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_HARVARD=n -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/nsim/nsim_hs_mpuv6.yaml b/boards/arc/nsim/nsim_hs_mpuv6.yaml deleted file mode 100644 index cf1fdba06a7..00000000000 --- a/boards/arc/nsim/nsim_hs_mpuv6.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: nsim_hs_mpuv6 -name: HS (with MPU v6) nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs_mpuv6_defconfig b/boards/arc/nsim/nsim_hs_mpuv6_defconfig deleted file mode 100644 index 4f57122f208..00000000000 --- a/boards/arc/nsim/nsim_hs_mpuv6_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS_MPUV6=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arc/nsim/nsim_hs_smp.yaml b/boards/arc/nsim/nsim_hs_smp.yaml deleted file mode 100644 index ccc1fab694d..00000000000 --- a/boards/arc/nsim/nsim_hs_smp.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: nsim_hs_smp -name: Multi-core HS nSIM simulator -type: sim -simulation: mdb-nsim -simulation_exec: mdb -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -supported: - - smp -testing: - timeout_multiplier: 1.5 - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs_smp_defconfig b/boards/arc/nsim/nsim_hs_smp_defconfig deleted file mode 100644 index 1b0d663da8d..00000000000 --- a/boards/arc/nsim/nsim_hs_smp_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS_SMP=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs_sram.yaml b/boards/arc/nsim/nsim_hs_sram.yaml deleted file mode 100644 index cfbf02d6023..00000000000 --- a/boards/arc/nsim/nsim_hs_sram.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs_sram -name: HS nSIM simulator (SRAM) -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs_sram_defconfig b/boards/arc/nsim/nsim_hs_sram_defconfig deleted file mode 100644 index 8c4032b2054..00000000000 --- a/boards/arc/nsim/nsim_hs_sram_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_HARVARD=n -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/nsim/nsim_sem.yaml b/boards/arc/nsim/nsim_sem.yaml deleted file mode 100644 index 13afb56ca69..00000000000 --- a/boards/arc/nsim/nsim_sem.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: nsim_sem -name: SEM Nsim simulator -type: sim -arch: arc -simulation: nsim -simulation_exec: nsimdrv -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_sem_defconfig b/boards/arc/nsim/nsim_sem_defconfig deleted file mode 100644 index c6be9e45d58..00000000000 --- a/boards/arc/nsim/nsim_sem_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_SEM=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arc/nsim/nsim_sem_mpu_stack_guard.yaml b/boards/arc/nsim/nsim_sem_mpu_stack_guard.yaml deleted file mode 100644 index 13a48179fd5..00000000000 --- a/boards/arc/nsim/nsim_sem_mpu_stack_guard.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_sem_mpu_stack_guard -name: SEM nSIM simulator (stack guard) -type: sim -arch: arc -simulation: nsim -simulation_exec: nsimdrv -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_sem_mpu_stack_guard_defconfig b/boards/arc/nsim/nsim_sem_mpu_stack_guard_defconfig deleted file mode 100644 index 4f846b18d61..00000000000 --- a/boards/arc/nsim/nsim_sem_mpu_stack_guard_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_SEM=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arc/nsim/nsim_vpx5.yaml b/boards/arc/nsim/nsim_vpx5.yaml deleted file mode 100644 index 4d5a3c8e96e..00000000000 --- a/boards/arc/nsim/nsim_vpx5.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: nsim_vpx5 -name: VPX5 nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_vpx5_defconfig b/boards/arc/nsim/nsim_vpx5_defconfig deleted file mode 100644 index 83fdaa12a7d..00000000000 --- a/boards/arc/nsim/nsim_vpx5_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_VPX5=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arc/qemu_arc/Kconfig.board b/boards/arc/qemu_arc/Kconfig.board deleted file mode 100644 index 1ea1a6bd77e..00000000000 --- a/boards/arc/qemu_arc/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Synopsys, Inc. All rights reserved. -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_ARC - bool "ARC QEMU for EM & HS cores" - depends on SOC_QEMU_ARC - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT diff --git a/boards/arc/qemu_arc/Kconfig.defconfig b/boards/arc/qemu_arc/Kconfig.defconfig deleted file mode 100644 index 54319f18bf3..00000000000 --- a/boards/arc/qemu_arc/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2020,2021 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_ARC - -config BOARD - default "qemu_arc" - -if NETWORKING - - config NET_L2_ETHERNET - default y - - # Required to satisfy dependency of networking stack on RNG - config TEST_RANDOM_GENERATOR - default y - -endif # NETWORKING - -endif diff --git a/boards/arc/qemu_arc/board.cmake b/boards/arc/qemu_arc/board.cmake deleted file mode 100644 index be83feb1637..00000000000 --- a/boards/arc/qemu_arc/board.cmake +++ /dev/null @@ -1,44 +0,0 @@ -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_CPU_TYPE_${ARCH} arc) - -if(${CONFIG_SOC_QEMU_ARC_EM}) -set(QEMU_CPU_TYPE_${ARCH} arcem) -set(QEMU_FLAGS_${ARCH} -cpu arcem) -elseif(${CONFIG_SOC_QEMU_ARC_HS}) -set(QEMU_CPU_TYPE_${ARCH} archs) -set(QEMU_FLAGS_${ARCH} -cpu archs) -elseif(${CONFIG_SOC_QEMU_ARC_HS5X}) -set(QEMU_ARCH arc) -set(QEMU_CPU_TYPE_${ARCH} hs5x) -set(QEMU_FLAGS_${ARCH} -cpu hs5x) -elseif(${CONFIG_SOC_QEMU_ARC_HS6X}) -set(QEMU_ARCH arc64) -set(QEMU_CPU_TYPE_${ARCH} hs6x) -set(QEMU_FLAGS_${ARCH} -cpu hs6x) -endif() - -# For old QEMU we had 'simhs' qemu board, however we are going to rename it -# to 'virt' board. It will be renamed in ARC QEMU in the nearest Zephyr SDK -# (where ARCv3 HS6x support will be added to QEMU) -# Let's rely on the QEMU defaults instead of specifying exact board name, -# until the updated Zephyr SDK will be set as default. By that we keep both SDKs -# (old and new) working for ARCv2. -# After that we can specify board explicitly with '-M virt' option. -list(APPEND QEMU_FLAGS_${ARCH} - -m 8M - -nographic - -no-reboot - -monitor none - -global cpu.firq=false - -global cpu.num-irqlevels=15 - -global cpu.num-irq=25 - -global cpu.ext-irq=20 - -global cpu.freq_hz=10000000 - -global cpu.timer0=true - -global cpu.timer1=true - -global cpu.has-mpu=true - -global cpu.mpu-numreg=16 - ) - -set(BOARD_DEBUG_RUNNER qemu) diff --git a/boards/arc/qemu_arc/doc/index.rst b/boards/arc/qemu_arc/doc/index.rst deleted file mode 100644 index 5a0857edc41..00000000000 --- a/boards/arc/qemu_arc/doc/index.rst +++ /dev/null @@ -1,102 +0,0 @@ -.. _qemu_arc: - -ARCv2 & ARCv3 Emulation (QEMU) -############################### - -Overview -******** - -This board configuration will use QEMU to emulate set of generic -ARCv2 and ARCv3 hardware platforms. - -The following features of ARC ISA cores are currently supported: - -* CPU: - * ARCv2 EM - * ARCv2 HS3x - * ARCv3 HS5x - * ARCv3 HS6x -* Only little-endian configurations -* Full 32 register set -* ARC core free-running timers/counters Timer0 & Timer1 -* ARC core interrupt controller with multiple priority levels -* DW UART -* 5 slots for MMIO Virtio devices - -Hardware -******** -Supported Features -================== - -The following hardware features are supported: - -+--------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+==============+============+======================+ -| ARCv2 INTC | on-chip | interrupt controller | -+--------------+------------+----------------------+ -| DW UART | on-chip | serial port | -+--------------+------------+----------------------+ -| ARC TIMER0 | on-chip | system clock | -+--------------+------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 1 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -DesignWare UART. - -Known Problems or Limitations -============================== - -The following platform features are unsupported: - -* Memory-protection unit (MPU) -* MMIO Virtio Ethernet - -Programming and Debugging -************************* - -Use this configuration to run basic Zephyr applications and kernel tests in the QEMU -emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample -(note you may use ``qemu_arc_em``, ``qemu_arc_hs``, ``qemu_arc_hs5x`` or -``qemu_arc_hs6x`` depending on target CPU): - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: qemu_arc_em - :goals: run - -This will build an image with the synchronization sample app, boot it using -QEMU, and display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.2.0-2486-g7dbfcf4bab57 *** - threadA: Hello World from qemu_arc! - threadB: Hello World from qemu_arc! - threadA: Hello World from qemu_arc! - threadB: Hello World from qemu_arc! - -Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. - -Debugging -========= - -Refer to the detailed overview about :ref:`application_debugging`. - -References -********** - -1.`Programmer’s Reference Manual for ARC HS - `_ diff --git a/boards/arc/qemu_arc/qemu_arc_em.yaml b/boards/arc/qemu_arc/qemu_arc_em.yaml deleted file mode 100644 index 2c1db9ed374..00000000000 --- a/boards/arc/qemu_arc/qemu_arc_em.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_arc_em -name: QEMU Emulation for ARC EM -type: qemu -simulation: qemu -arch: arc -toolchain: - - zephyr - - cross-compile -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_em_defconfig b/boards/arc/qemu_arc/qemu_arc_em_defconfig deleted file mode 100644 index 0d6f4052e64..00000000000 --- a/boards/arc/qemu_arc/qemu_arc_em_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_SOC_QEMU_ARC=y -CONFIG_SOC_QEMU_ARC_EM=y -CONFIG_XIP=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/qemu_arc/qemu_arc_hs.yaml b/boards/arc/qemu_arc/qemu_arc_hs.yaml deleted file mode 100644 index 468b3a05215..00000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: qemu_arc_hs -name: QEMU Emulation for ARC HS -type: qemu -simulation: qemu -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_hs5x.yaml b/boards/arc/qemu_arc/qemu_arc_hs5x.yaml deleted file mode 100644 index 0abe51e0472..00000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs5x.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_arc_hs5x -name: QEMU Emulation for ARC HS5x -type: qemu -simulation: qemu -arch: arc -toolchain: - - zephyr - - cross-compile -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_hs5x_defconfig b/boards/arc/qemu_arc/qemu_arc_hs5x_defconfig deleted file mode 100644 index f8e50bcf3f8..00000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs5x_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_ISA_ARCV3=y -CONFIG_SOC_QEMU_ARC=y -CONFIG_SOC_QEMU_ARC_HS5X=y -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/arc/qemu_arc/qemu_arc_hs6x.yaml b/boards/arc/qemu_arc/qemu_arc_hs6x.yaml deleted file mode 100644 index ed5425cc565..00000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs6x.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_arc_hs6x -name: QEMU Emulation for ARC HS6x -type: qemu -simulation: qemu -arch: arc -toolchain: - - cross-compile - - zephyr -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_hs6x_defconfig b/boards/arc/qemu_arc/qemu_arc_hs6x_defconfig deleted file mode 100644 index 8ab0d4ae0f0..00000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs6x_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_ISA_ARCV3=y -CONFIG_SOC_QEMU_ARC=y -CONFIG_SOC_QEMU_ARC_HS6X=y -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/arc/qemu_arc/qemu_arc_hs_defconfig b/boards/arc/qemu_arc/qemu_arc_hs_defconfig deleted file mode 100644 index 911702aab21..00000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_SOC_QEMU_ARC=y -CONFIG_SOC_QEMU_ARC_HS=y -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/qemu_arc/qemu_arc_hs_xip.yaml b/boards/arc/qemu_arc/qemu_arc_hs_xip.yaml deleted file mode 100644 index 4f7b9cee45d..00000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs_xip.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_arc_hs_xip -name: QEMU Emulation for ARC HS (XIP) -type: qemu -simulation: qemu -arch: arc -toolchain: - - zephyr - - cross-compile -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_hs_xip_defconfig b/boards/arc/qemu_arc/qemu_arc_hs_xip_defconfig deleted file mode 100644 index bec83e7c5ae..00000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs_xip_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_SOC_QEMU_ARC=y -CONFIG_SOC_QEMU_ARC_HS=y -CONFIG_XIP=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arduino/due/Kconfig.arduino_due b/boards/arduino/due/Kconfig.arduino_due new file mode 100644 index 00000000000..0e9cc38393c --- /dev/null +++ b/boards/arduino/due/Kconfig.arduino_due @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Justin Watson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_DUE + select SOC_SAM3X8E diff --git a/boards/arm/arduino_due/arduino_due-pinctrl.dtsi b/boards/arduino/due/arduino_due-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_due/arduino_due-pinctrl.dtsi rename to boards/arduino/due/arduino_due-pinctrl.dtsi diff --git a/boards/arm/arduino_due/arduino_due.dts b/boards/arduino/due/arduino_due.dts similarity index 100% rename from boards/arm/arduino_due/arduino_due.dts rename to boards/arduino/due/arduino_due.dts diff --git a/boards/arm/arduino_due/arduino_due.yaml b/boards/arduino/due/arduino_due.yaml similarity index 100% rename from boards/arm/arduino_due/arduino_due.yaml rename to boards/arduino/due/arduino_due.yaml index 779271c0e12..21a71527ffe 100644 --- a/boards/arm/arduino_due/arduino_due.yaml +++ b/boards/arduino/due/arduino_due.yaml @@ -2,14 +2,14 @@ identifier: arduino_due name: Arduino Due type: mcu arch: arm -ram: 96 -flash: 512 toolchain: - zephyr - gnuarmemb - xtools +flash: 512 +ram: 96 supported: - - watchdog - - gpio - arduino_i2c + - gpio + - watchdog vendor: arduino diff --git a/boards/arduino/due/arduino_due_defconfig b/boards/arduino/due/arduino_due_defconfig new file mode 100644 index 00000000000..fb11f348f48 --- /dev/null +++ b/boards/arduino/due/arduino_due_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/arduino_due/board.cmake b/boards/arduino/due/board.cmake similarity index 100% rename from boards/arm/arduino_due/board.cmake rename to boards/arduino/due/board.cmake diff --git a/boards/arduino/due/board.yml b/boards/arduino/due/board.yml new file mode 100644 index 00000000000..351bc719a15 --- /dev/null +++ b/boards/arduino/due/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_due + vendor: arduino + socs: + - name: sam3x8e diff --git a/boards/arm/arduino_due/doc/img/arduino_due.jpg b/boards/arduino/due/doc/img/arduino_due.jpg similarity index 100% rename from boards/arm/arduino_due/doc/img/arduino_due.jpg rename to boards/arduino/due/doc/img/arduino_due.jpg diff --git a/boards/arduino/due/doc/index.rst b/boards/arduino/due/doc/index.rst new file mode 100644 index 00000000000..5d984027534 --- /dev/null +++ b/boards/arduino/due/doc/index.rst @@ -0,0 +1,214 @@ +.. _arduino_due: + +Arduino Due +########### + +Overview +******** + +The arduino_due board configuration is used by Zephyr applications +that run on the Arduino Due board. It provides support for the Atmel +SAM3X8E ARM Cortex-M3 CPU and the following devices: + +* Nested Vectored Interrupt Controller (NVIC) + +* System Tick System Clock (SYSTICK) + +* Serial Port over USB (ATMEL_SAM3) + +More information about the board can be found at the `Arduino Due website`_. +The `Atmel SAM3X8E Datasheet`_ has the information and the datasheet about +the processor. + +.. note:: + This configuration is not supported by Arduino. + +.. image:: img/arduino_due.jpg + :align: center + :alt: Arduino Due + +Hardware +******** +Supported Features +================== + +The arduino_due board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+----------------------+ +| UART | on-chip | serial port | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features are not currently supported by the Zephyr kernel. +See `Arduino Due website`_ and `Atmel SAM3X8E Datasheet`_ for a complete +list of Arduino Due board hardware features. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/arduino/due/arduino_due_defconfig`. + +.. note:: + For I2C, pull-up resistors are required for using SCL1 and SDA1 (near IO13). + +Interrupt Controller +==================== + +There are 15 fixed exceptions including exceptions 12 (debug monitor) and 15 +(SYSTICK) that behave more as interrupts than exceptions. In addition, there can +be a variable number of IRQs. Exceptions 7-10 and 13 are reserved. They don't +need handlers. + +A Cortex-M3/4-based board uses vectored exceptions. This means each exception +calls a handler directly from the vector table. + +Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here +identifies the handlers used for each exception. + ++------+------------+----------------+-----------------------+ +| Exc# | Name | Remarks | Used by Zephyr Kernel | ++======+============+================+=======================+ +| 1 | Reset | | system initialization | ++------+------------+----------------+-----------------------+ +| 2 | NMI | | system fatal error | ++------+------------+----------------+-----------------------+ +| 3 | Hard fault | | system fatal error | ++------+------------+----------------+-----------------------+ +| 4 | MemManage | MPU fault | system fatal error | ++------+------------+----------------+-----------------------+ +| 5 | Bus | | system fatal error | ++------+------------+----------------+-----------------------+ +| 6 | Usage | undefined | system fatal error | +| | fault | instruction, | | +| | | or switch | | +| | | attempt to ARM | | +| | | mode | | ++------+------------+----------------+-----------------------+ +| 11 | SVC | | system calls, kernel | +| | | | run-time exceptions, | +| | | | and IRQ offloading | ++------+------------+----------------+-----------------------+ +| 12 | Debug | | system fatal error | +| | monitor | | | ++------+------------+----------------+-----------------------+ +| 14 | PendSV | | context switch | ++------+------------+----------------+-----------------------+ +| 15 | SYSTICK | | system clock | ++------+------------+----------------+-----------------------+ + +.. note:: + After a reset, all exceptions have a priority of 0. Interrupts cannot run + at priority 0 for the interrupt locking mechanism and exception handling + to function properly. + +System Clock +============ + +Arduino Due has two external oscillators/resonators. The slow clock is +32.768 kHz, and the main clock is 12 MHz. The processor can set up PLL to drive +the master clock, which can be set as high as 84 MHz. + +Serial Port +=========== + +The Atmel SAM3X8E processor has a single UART that is used by the SAM-BA +bootloader. This UART has only two wires for RX/TX and does not have flow +control (CTS/RTS) or FIFO. The RX/TX pins are connected to the ATmega16U2, +which provides USB-to-TTL serial function. The Zephyr console output, by +default, is utilizing this controller. + + +Programming and Debugging +************************* + +Flashing +======== + +BOSSA Tool +---------- + +Flashing the Zephyr kernel onto Arduino Due requires the `bossa tool`_. + +There are GUI and command line versions of the bossa tool. The following +section provides the steps to build the command line version. Please +refer to the bossa tool's README file on how to build the GUI version. + +To build the bossa tool, follow these steps: + +#. Checkout the bossa tool's code from the repository. + + .. code-block:: console + + $ git clone https://github.com/shumatech/BOSSA.git + $ cd BOSSA + +#. Checkout the arduino branch. The code on the master branch does not + work with Arduino Due. + + .. code-block:: console + + $ git checkout arduino + +#. Build the command line version of the bossa tool. + + .. code-block:: console + + $ make bin/bossac + +#. The resulting binary is available at :file:`bin/bossac`. + + +Flashing an Application to Arduino Due +-------------------------------------- + +Applications for the ``arduino_due`` board configuration can be built +and flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. After +building the application, press the Reset button before running the +flash command, so the board will boot into the SAM-BA bootloader and +be prepared to receive the new program. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_due + :goals: build flash + +After flashing the application, run your favorite terminal program to +listen for output. For example, under Linux, the terminal should be +:code:`/dev/ttyACM0`. For example: + +.. code-block:: console + + $ sudo minicom -D /dev/ttyACM0 -o + +The -o option tells minicom not to send the modem initialization +string. + +Now press the Reset button and you should see "Hello World! arduino_due" in your terminal. + +.. note:: + Make sure your terminal program is closed before flashing the binary image, + or it will interfere with the flashing process. + +References +********** + +.. _Arduino Due website: https://www.arduino.cc/en/Main/ArduinoBoardDue + +.. _Atmel SAM3X8E Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf + +.. _bossa tool: https://github.com/shumatech/BOSSA + +.. _bossa arduino branch: https://github.com/shumatech/BOSSA/tree/arduino diff --git a/boards/arduino/giga_r1/Kconfig.arduino_giga_r1 b/boards/arduino/giga_r1/Kconfig.arduino_giga_r1 new file mode 100644 index 00000000000..6eb5d937b84 --- /dev/null +++ b/boards/arduino/giga_r1/Kconfig.arduino_giga_r1 @@ -0,0 +1,6 @@ +# Copyright 2023 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_GIGA_R1 + select SOC_STM32H747XX_M7 if BOARD_ARDUINO_GIGA_R1_STM32H747XX_M7 + select SOC_STM32H747XX_M4 if BOARD_ARDUINO_GIGA_R1_STM32H747XX_M4 diff --git a/boards/arduino/giga_r1/Kconfig.defconfig b/boards/arduino/giga_r1/Kconfig.defconfig new file mode 100644 index 00000000000..0d20cf3c341 --- /dev/null +++ b/boards/arduino/giga_r1/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright 2023 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARDUINO_GIGA_R1 + +if BT + +choice AIROC_PART + default CYW4343W +endchoice + +choice CYW4343W_MODULE + default CYW4343W_MURATA_1DX +endchoice + +endif # BT + +endif # BOARD_ARDUINO_GIGA_R1 diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1.dtsi b/boards/arduino/giga_r1/arduino_giga_r1.dtsi similarity index 100% rename from boards/arm/arduino_giga_r1/arduino_giga_r1.dtsi rename to boards/arduino/giga_r1/arduino_giga_r1.dtsi diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m4.dts b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.dts similarity index 100% rename from boards/arm/arduino_giga_r1/arduino_giga_r1_m4.dts rename to boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.dts diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.yaml b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.yaml new file mode 100644 index 00000000000..3917682bd21 --- /dev/null +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.yaml @@ -0,0 +1,19 @@ +identifier: arduino_giga_r1/stm32h747xx/m4 +name: Arduino GIGA R1 WiFi (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 288 +flash: 1024 +supported: + - arduino_gpio + - gpio +testing: + ignore_tags: + - mpu + - nfc + - net +vendor: arduino diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4_defconfig b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4_defconfig new file mode 100644 index 00000000000..c7a9e88969b --- /dev/null +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4_defconfig @@ -0,0 +1,24 @@ +# Copyright 2023 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Clock configuration +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable uart driver +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.dts b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts similarity index 100% rename from boards/arm/arduino_giga_r1/arduino_giga_r1_m7.dts rename to boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml new file mode 100644 index 00000000000..cdcaeba7c77 --- /dev/null +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml @@ -0,0 +1,19 @@ +identifier: arduino_giga_r1/stm32h747xx/m7 +name: Arduino GIGA R1 WiFi (M7) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 1024 +supported: + - arduino_gpio + - gpio + - arduino_spi + - spi + - memc + - usb_cdc + - usb_device +vendor: arduino diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7_defconfig b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7_defconfig new file mode 100644 index 00000000000..0bd7546e26a --- /dev/null +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7_defconfig @@ -0,0 +1,30 @@ +# Copyright 2023 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +# Disable the internal SMPS regulator +CONFIG_POWER_SUPPLY_DIRECT_SMPS=n + +# Enable GPIO +CONFIG_GPIO=y + +# Enable clocks +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable uart driver +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable pin controller +CONFIG_PINCTRL=y + +# Use zephyr,code-partition as flash offset +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/arduino_giga_r1/arduino_r3_connector.dtsi b/boards/arduino/giga_r1/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/arduino_giga_r1/arduino_r3_connector.dtsi rename to boards/arduino/giga_r1/arduino_r3_connector.dtsi diff --git a/boards/arduino/giga_r1/board.cmake b/boards/arduino/giga_r1/board.cmake new file mode 100644 index 00000000000..f02ceaf2c3d --- /dev/null +++ b/boards/arduino/giga_r1/board.cmake @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_ARDUINO_GIGA_R1_STM32H747XX_M7) +board_runner_args(jlink "--device=STM32H747XI_M7" "--speed=4000") +board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_arduino_giga_r1_m7.cfg") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +elseif(CONFIG_BOARD_ARDUINO_GIGA_R1_STM32H747XX_M4) +board_runner_args(jlink "--device=STM32H747XI_M4" "--speed=4000") +board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_arduino_giga_r1_m4.cfg") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) +endif() +board_runner_args(dfu-util "--pid=2341:0366" "--alt=0" "--dfuse") +board_runner_args(blackmagicprobe "--connect-rst") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arduino/giga_r1/board.yml b/boards/arduino/giga_r1/board.yml new file mode 100644 index 00000000000..3079c2f0d5c --- /dev/null +++ b/boards/arduino/giga_r1/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_giga_r1 + vendor: arduino + socs: + - name: stm32h747xx diff --git a/boards/arm/arduino_giga_r1/doc/img/arduino_giga_r1.jpg b/boards/arduino/giga_r1/doc/img/arduino_giga_r1.jpg similarity index 100% rename from boards/arm/arduino_giga_r1/doc/img/arduino_giga_r1.jpg rename to boards/arduino/giga_r1/doc/img/arduino_giga_r1.jpg diff --git a/boards/arduino/giga_r1/doc/index.rst b/boards/arduino/giga_r1/doc/index.rst new file mode 100644 index 00000000000..0e95653edfa --- /dev/null +++ b/boards/arduino/giga_r1/doc/index.rst @@ -0,0 +1,186 @@ +.. _arduino_giga_r1_board: + +Arduino GIGA R1 WiFi +#################### + +Overview +******** + +Arduino GIGA R1 WiFi is a development board by Arduino based on the +STM32H747XI, a dual core ARM Cortex-M7 + Cortex-M4 MCU, with 2MBytes of Flash +memory and 1MB SRAM. + +The board features: + +- RGB LED +- Reset and Boot buttons +- USB-C device +- USB Host +- 16MB external QSPI flash +- 8MB external SDRAM +- Murata Type 1DX Bluetooth + WiFi module (CYW4343W based) +- Audio jack +- ATECC608A secure element + +.. image:: img/arduino_giga_r1.jpg + :align: center + :alt: Arduino GIGA R1 WiFi + +More information about the board, including the datasheet, pinout and +schematics, can be found at the `Arduino GIGA website`_. + +More information about STM32H747XIH6 can be found here: + +- `STM32H747XI on www.st.com`_ +- `STM32H747xx reference manual`_ +- `STM32H747xx datasheet`_ + +Supported Features +================== + +The current Zephyr ``arduino_giga_r1_m7`` board configuration supports the +following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| IPM | on-chip | virtual mailbox based on HSEM | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| QSPI | on-chip | QSPI flash | ++-----------+------------+-------------------------------------+ +| RADIO | Murata 1DX | WiFi and Bluetooth module | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr port. + +Fetch Binary Blobs +****************** + +The board Bluetooth/WiFi module requires fetching some binary blob files, to do +that run the command: + +.. code-block:: console + + west blobs fetch hal_infineon + +.. note:: Only Bluetooth functionality is currently supported. + +Resources sharing +================= + +The dual core nature of STM32H747 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Programming and Debugging +************************* + +Applications for the ``arduino_giga_r1`` board should be built per core target, +using either ``arduino_giga_r1/stm32h747xx/m7`` or ``arduino_giga_r1/stm32h747xx/m4`` as the target. + +See :ref:`build_an_application` for more information about application builds. + +Flashing +======== + +This board can be flashed either using dfu-util, or with an external debugging +probe, such as a J-Link or Black Magic Probe, connected to the on board MIPI-10 +SWD port marked as "JTAG". + +.. note:: + + The board ships with a custom Arduino bootloader programmed in the first + flash page that can be triggered by double clicking the ``RST`` button. This + bootloader is USB-DFU compatible and supports programming both the internal + and external flash and is the one used by ``west flash`` by default. The + internal STM32 ROM bootloader can also be used by pressing ``RST`` while + holding the ``BOOT0`` button, this also supports USB-DFU but can only + program the internal flash and can overwrite the Arduino bootloader. More + details can be found in the "Boot0" section of the `Arduino GIGA Cheat + Sheet`_. + +First, connect the Arduino GIGA R1 board to your host computer using the USB +port to prepare it for flashing. Double click the ``RST`` button to put the +board into the Arduino Bootloader mode. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_giga_r1/stm32h747xx/m7 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arduino_giga_r1 + +Similarly, you can build and flash samples on the M4 target. + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: arduino_giga_r1/stm32h747xx/m4 + :goals: build flash + +Debugging +========= + +Debugging is supported by using ``west debug`` with an external probe such as a +J-Link or Black Magic Probe, connected to the on board MIPI-10 SWD port marked +as "JTAG". For example:: + + west debug -r jlink + +.. _Arduino GIGA website: + https://docs.arduino.cc/hardware/giga-r1-wifi + +.. _Arduino GIGA Cheat Sheet: + https://docs.arduino.cc/tutorials/giga-r1-wifi/cheat-sheet + +.. _STM32H747XI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html + +.. _STM32H747xx reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879.pdf + +.. _STM32H747xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h747xi.pdf + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html diff --git a/boards/arm/arduino_giga_r1/support/openocd_arduino_giga_r1_m4.cfg b/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m4.cfg similarity index 100% rename from boards/arm/arduino_giga_r1/support/openocd_arduino_giga_r1_m4.cfg rename to boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m4.cfg diff --git a/boards/arm/arduino_giga_r1/support/openocd_arduino_giga_r1_m7.cfg b/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m7.cfg similarity index 100% rename from boards/arm/arduino_giga_r1/support/openocd_arduino_giga_r1_m7.cfg rename to boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m7.cfg diff --git a/boards/arduino/index.rst b/boards/arduino/index.rst new file mode 100644 index 00000000000..a8877f1a3a2 --- /dev/null +++ b/boards/arduino/index.rst @@ -0,0 +1,10 @@ +.. _boards-arduino: + +Arduino +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arduino/mkrzero/Kconfig.arduino_mkrzero b/boards/arduino/mkrzero/Kconfig.arduino_mkrzero new file mode 100644 index 00000000000..9958bc8555d --- /dev/null +++ b/boards/arduino/mkrzero/Kconfig.arduino_mkrzero @@ -0,0 +1,6 @@ +# Copyright (c) 2022 TOKITA Hiroshi +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_MKRZERO + select SOC_SAMD21G18A diff --git a/boards/arduino/mkrzero/Kconfig.defconfig b/boards/arduino/mkrzero/Kconfig.defconfig new file mode 100644 index 00000000000..6d5f9448b9e --- /dev/null +++ b/boards/arduino/mkrzero/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Arduino MKR Zero board configuration + +# Copyright (c) 2022 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if DISK_DRIVERS + +config DISK_DRIVER_SDMMC + default y + +config SPI + default y + +config GPIO + default y + +endif # DISK_DRIVERS diff --git a/boards/arm/arduino_mkrzero/arduino_mkr_connector.dtsi b/boards/arduino/mkrzero/arduino_mkr_connector.dtsi similarity index 100% rename from boards/arm/arduino_mkrzero/arduino_mkr_connector.dtsi rename to boards/arduino/mkrzero/arduino_mkr_connector.dtsi diff --git a/boards/arm/arduino_mkrzero/arduino_mkrzero-pinctrl.dtsi b/boards/arduino/mkrzero/arduino_mkrzero-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_mkrzero/arduino_mkrzero-pinctrl.dtsi rename to boards/arduino/mkrzero/arduino_mkrzero-pinctrl.dtsi diff --git a/boards/arm/arduino_mkrzero/arduino_mkrzero.dts b/boards/arduino/mkrzero/arduino_mkrzero.dts similarity index 100% rename from boards/arm/arduino_mkrzero/arduino_mkrzero.dts rename to boards/arduino/mkrzero/arduino_mkrzero.dts diff --git a/boards/arm/arduino_mkrzero/arduino_mkrzero.yaml b/boards/arduino/mkrzero/arduino_mkrzero.yaml similarity index 100% rename from boards/arm/arduino_mkrzero/arduino_mkrzero.yaml rename to boards/arduino/mkrzero/arduino_mkrzero.yaml diff --git a/boards/arduino/mkrzero/arduino_mkrzero_defconfig b/boards/arduino/mkrzero/arduino_mkrzero_defconfig new file mode 100644 index 00000000000..ab658e1e5d6 --- /dev/null +++ b/boards/arduino/mkrzero/arduino_mkrzero_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ARDUINO=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/arduino_mkrzero/board.cmake b/boards/arduino/mkrzero/board.cmake similarity index 100% rename from boards/arm/arduino_mkrzero/board.cmake rename to boards/arduino/mkrzero/board.cmake diff --git a/boards/arduino/mkrzero/board.yml b/boards/arduino/mkrzero/board.yml new file mode 100644 index 00000000000..a53c04cbd18 --- /dev/null +++ b/boards/arduino/mkrzero/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_mkrzero + vendor: arduino + socs: + - name: samd21g18a diff --git a/boards/arm/arduino_mkrzero/doc/img/arduino_mkrzero.jpg b/boards/arduino/mkrzero/doc/img/arduino_mkrzero.jpg similarity index 100% rename from boards/arm/arduino_mkrzero/doc/img/arduino_mkrzero.jpg rename to boards/arduino/mkrzero/doc/img/arduino_mkrzero.jpg diff --git a/boards/arduino/mkrzero/doc/index.rst b/boards/arduino/mkrzero/doc/index.rst new file mode 100644 index 00000000000..b6fe37ddd16 --- /dev/null +++ b/boards/arduino/mkrzero/doc/index.rst @@ -0,0 +1,183 @@ +.. _arduino_mkrzero: + +Arduino MKR Zero +#################### + +Overview +******** + +The Arduino MKR Zero built with smaller MKR form factor and powered by Atmel's SAMD21 MCU. +This board come with microSD card holder that allows you to play with music files with no extra hardware. + +.. image:: img/arduino_mkrzero.jpg + :align: center + :alt: Arduino MKR Zero + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- One user LEDs +- One reset button +- microSD card slot +- ATECC508A secure element + +Supported Features +================== + +The arduino_mkrzero board configuration supports the following hardware +features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| ADC | on-chip | Analog to digital converter | ++-----------+------------+------------------------------------------+ +| COUNTER | on-chip | Pulse counter | ++-----------+------------+------------------------------------------+ +| DMA | on-chip | Direct memory access unit | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| HWINFO | on-chip | Hardware info and serial number | ++-----------+------------+------------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| I2C | on-chip | Inter-Integrated Circuit ports | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ + + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/arduino/mkrzero/arduino_mkrzero_defconfig`. + +Connections and IOs +=================== + +The `Arduino store`_ has detailed information about board +connections. Download the `Arduino MKR Zero Schematic`_ for more detail. + +System Clock +============ + +The SAMD21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. The internal +APB and GCLK unit are set up in the same way as the upstream Arduino +libraries. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. SERCOM5 is available on pins 13(PA23) and 14(PA22). + +PWM +=== + +The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the Arduino MKR Zero, SERCOM1 +is available on pin 8, 9, and 10. +SERCOM2 connect to microSD card slot as SPI interface. + +I2C Port +======== + +The SAMD21 MCU has 6 SERCOM based I2Cs. SERCOM0 is available on pin 11(PA08) and 12(PA09). +This I2C bus also available as ESLOV(JST SH 5pin) socket. +ATECC508A secure element is connect to this I2C bus. + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +DAC +=== + +The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On the +Arduino MKR Zero, the DAC is available on pin A0. + +Programming and Debugging +************************* + +The Arduino MKR Zero ships the BOSSA compatible bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_mkrzero + :goals: build + :compact: + +#. Connect the MKR Zero to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_mkrzero + :goals: flash + :compact: + + You should see "Hello World! arduino_mkrzero" in your terminal. + +References +********** + +.. target-notes:: + +.. _Arduino Store: + https://store.arduino.cc/collections/boards/products/arduino-mkr-zero-i2s-bus-sd-for-sound-music-digital-audio-data + +.. _Arduino MKR Zero Schematic: + https://www.arduino.cc/en/uploads/Main/ArduinoMKRZero-schematic.pdf diff --git a/boards/arm/arduino_mkrzero/pre_dt_board.cmake b/boards/arduino/mkrzero/pre_dt_board.cmake similarity index 100% rename from boards/arm/arduino_mkrzero/pre_dt_board.cmake rename to boards/arduino/mkrzero/pre_dt_board.cmake diff --git a/boards/arm/arduino_nano_33_ble/CMakeLists.txt b/boards/arduino/nano_33_ble/CMakeLists.txt similarity index 100% rename from boards/arm/arduino_nano_33_ble/CMakeLists.txt rename to boards/arduino/nano_33_ble/CMakeLists.txt diff --git a/boards/arduino/nano_33_ble/Kconfig.arduino_nano_33_ble b/boards/arduino/nano_33_ble/Kconfig.arduino_nano_33_ble new file mode 100644 index 00000000000..7fafc189aa4 --- /dev/null +++ b/boards/arduino/nano_33_ble/Kconfig.arduino_nano_33_ble @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Jefferson Lee. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_NANO_33_BLE + select SOC_NRF52840_QIAA diff --git a/boards/arduino/nano_33_ble/Kconfig.defconfig b/boards/arduino/nano_33_ble/Kconfig.defconfig new file mode 100644 index 00000000000..73bd7e9c32d --- /dev/null +++ b/boards/arduino/nano_33_ble/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2020 Jefferson Lee. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARDUINO_NANO_33_BLE + +config BT_CTLR + default BT + +config REGULATOR + default y if SENSOR + +endif # BOARD_ARDUINO_NANO_33_BLE diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble-common.dtsi b/boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble-common.dtsi rename to boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble-pinctrl.dtsi b/boards/arduino/nano_33_ble/arduino_nano_33_ble-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble-pinctrl.dtsi rename to boards/arduino/nano_33_ble/arduino_nano_33_ble-pinctrl.dtsi diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.dts b/boards/arduino/nano_33_ble/arduino_nano_33_ble.dts similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.dts rename to boards/arduino/nano_33_ble/arduino_nano_33_ble.dts diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.yaml b/boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.yaml rename to boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_defconfig b/boards/arduino/nano_33_ble/arduino_nano_33_ble_defconfig similarity index 77% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_defconfig rename to boards/arduino/nano_33_ble/arduino_nano_33_ble_defconfig index 49b2009f744..9e62deccc4d 100644 --- a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_defconfig +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_ARDUINO_NANO_33_BLE=y - # Enable MPU CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense.dts b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense.dts rename to boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml new file mode 100644 index 00000000000..b8741e66b35 --- /dev/null +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml @@ -0,0 +1,20 @@ +identifier: arduino_nano_33_ble//sense +name: Arduino Nano 33 BLE Sense +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - ble + - i2c + - pwm + - serial + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: arduino diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense_defconfig b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense_defconfig new file mode 100644 index 00000000000..9e62deccc4d --- /dev/null +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# enable peripherals +CONFIG_GPIO=y +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable sam-ba bootloader on legacy mode +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_LEGACY=y diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_r3_connector.dtsi b/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_r3_connector.dtsi rename to boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi diff --git a/boards/arm/arduino_nano_33_ble/board.c b/boards/arduino/nano_33_ble/board.c similarity index 100% rename from boards/arm/arduino_nano_33_ble/board.c rename to boards/arduino/nano_33_ble/board.c diff --git a/boards/arm/arduino_nano_33_ble/board.cmake b/boards/arduino/nano_33_ble/board.cmake similarity index 100% rename from boards/arm/arduino_nano_33_ble/board.cmake rename to boards/arduino/nano_33_ble/board.cmake diff --git a/boards/arduino/nano_33_ble/board.yml b/boards/arduino/nano_33_ble/board.yml new file mode 100644 index 00000000000..919864839ed --- /dev/null +++ b/boards/arduino/nano_33_ble/board.yml @@ -0,0 +1,7 @@ +board: + name: arduino_nano_33_ble + vendor: arduino + socs: + - name: nrf52840 + variants: + - name: 'sense' diff --git a/boards/arm/arduino_nano_33_ble/doc/img/arduino_nano_33_ble_sense.jpg b/boards/arduino/nano_33_ble/doc/img/arduino_nano_33_ble_sense.jpg similarity index 100% rename from boards/arm/arduino_nano_33_ble/doc/img/arduino_nano_33_ble_sense.jpg rename to boards/arduino/nano_33_ble/doc/img/arduino_nano_33_ble_sense.jpg diff --git a/boards/arm/arduino_nano_33_ble/doc/img/nano_33_ble_swd.jpg b/boards/arduino/nano_33_ble/doc/img/nano_33_ble_swd.jpg similarity index 100% rename from boards/arm/arduino_nano_33_ble/doc/img/nano_33_ble_swd.jpg rename to boards/arduino/nano_33_ble/doc/img/nano_33_ble_swd.jpg diff --git a/boards/arm/arduino_nano_33_ble/doc/index.rst b/boards/arduino/nano_33_ble/doc/index.rst similarity index 100% rename from boards/arm/arduino_nano_33_ble/doc/index.rst rename to boards/arduino/nano_33_ble/doc/index.rst diff --git a/boards/arm/arduino_nicla_sense_me/pre_dt_board.cmake b/boards/arduino/nano_33_ble/pre_dt_board.cmake similarity index 100% rename from boards/arm/arduino_nicla_sense_me/pre_dt_board.cmake rename to boards/arduino/nano_33_ble/pre_dt_board.cmake diff --git a/boards/arm/arduino_nano_33_ble/support/debug.cmm b/boards/arduino/nano_33_ble/support/debug.cmm similarity index 100% rename from boards/arm/arduino_nano_33_ble/support/debug.cmm rename to boards/arduino/nano_33_ble/support/debug.cmm diff --git a/boards/arm/arduino_nano_33_ble/support/startup.cmm b/boards/arduino/nano_33_ble/support/startup.cmm similarity index 100% rename from boards/arm/arduino_nano_33_ble/support/startup.cmm rename to boards/arduino/nano_33_ble/support/startup.cmm diff --git a/boards/arduino/nano_33_iot/Kconfig.arduino_nano_33_iot b/boards/arduino/nano_33_iot/Kconfig.arduino_nano_33_iot new file mode 100644 index 00000000000..55021a63b2f --- /dev/null +++ b/boards/arduino/nano_33_iot/Kconfig.arduino_nano_33_iot @@ -0,0 +1,6 @@ +# Copyright (c) 2020 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_NANO_33_IOT + select SOC_SAMD21G18A diff --git a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi b/boards/arduino/nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi rename to boards/arduino/nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi diff --git a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.dts b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts similarity index 100% rename from boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.dts rename to boards/arduino/nano_33_iot/arduino_nano_33_iot.dts diff --git a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.yaml b/boards/arduino/nano_33_iot/arduino_nano_33_iot.yaml similarity index 100% rename from boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.yaml rename to boards/arduino/nano_33_iot/arduino_nano_33_iot.yaml diff --git a/boards/arduino/nano_33_iot/arduino_nano_33_iot_defconfig b/boards/arduino/nano_33_iot/arduino_nano_33_iot_defconfig new file mode 100644 index 00000000000..051825bb751 --- /dev/null +++ b/boards/arduino/nano_33_iot/arduino_nano_33_iot_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_OSC8M=y +CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y + +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ARDUINO=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/arduino_nano_33_iot/arduino_nano_r3_connector.dtsi b/boards/arduino/nano_33_iot/arduino_nano_r3_connector.dtsi similarity index 100% rename from boards/arm/arduino_nano_33_iot/arduino_nano_r3_connector.dtsi rename to boards/arduino/nano_33_iot/arduino_nano_r3_connector.dtsi diff --git a/boards/arm/arduino_nano_33_iot/board.cmake b/boards/arduino/nano_33_iot/board.cmake similarity index 100% rename from boards/arm/arduino_nano_33_iot/board.cmake rename to boards/arduino/nano_33_iot/board.cmake diff --git a/boards/arduino/nano_33_iot/board.yml b/boards/arduino/nano_33_iot/board.yml new file mode 100644 index 00000000000..63b7dab7992 --- /dev/null +++ b/boards/arduino/nano_33_iot/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_nano_33_iot + vendor: arduino + socs: + - name: samd21g18a diff --git a/boards/arm/arduino_nano_33_iot/doc/img/nano_33_iot.jpg b/boards/arduino/nano_33_iot/doc/img/nano_33_iot.jpg similarity index 100% rename from boards/arm/arduino_nano_33_iot/doc/img/nano_33_iot.jpg rename to boards/arduino/nano_33_iot/doc/img/nano_33_iot.jpg diff --git a/boards/arduino/nano_33_iot/doc/index.rst b/boards/arduino/nano_33_iot/doc/index.rst new file mode 100644 index 00000000000..5b87fb52c18 --- /dev/null +++ b/boards/arduino/nano_33_iot/doc/index.rst @@ -0,0 +1,171 @@ +.. _arduino_nano_33_iot: + +Arduino Nano 33 IOT +################### + +Overview +******** + +The Arduino Nano 33 IOT is a small form factor development board with USB, +Wifi, Bluetooth, a 6 axis IMU, and secure element. + +.. image:: img/nano_33_iot.jpg + :align: center + :alt: Arduino Nano 33 IOT + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 256 KiB flash memory and 32 KiB of RAM +- One user LED +- One reset button +- Native USB port +- Wifi and Bluetooth via a u-blox NINA-W102 +- ATECC608A secure element +- LSM6DS3 six axis accelerometer and gyro + +Supported Features +================== + +The arduino_nano_33_iot board configuration supports the following hardware +features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| ADC | on-chip | Analog to digital converter | ++-----------+------------+------------------------------------------+ +| COUNTER | on-chip | Pulse counter | ++-----------+------------+------------------------------------------+ +| DMA | on-chip | Direct memory access unit | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| HWINFO | on-chip | Hardware info and serial number | ++-----------+------------+------------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/arduino/nano_33_iot/arduino_nano_33_iot_defconfig`. + +Connections and IOs +=================== + +The `Arduino store`_ has detailed information about board +connections. Download the `schematic`_ for more detail. + +System Clock +============ + +The SAMD21 MCU is configured to use the 8 MHz internal oscillator +with the on-chip PLL generating the 48 MHz system clock. The internal +APB and GCLK unit are set up in the same way as the upstream Arduino +libraries. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. SERCOM5 is available on pins 1 and 2. + +PWM +=== + +The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC2 instead of by GPIO. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. SERCOM1 is available on pins 1, 14, +and 15. + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +Programming and Debugging +************************* + +The Nano 33 IOT ships the BOSSA compatible UF2 bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader +will be entered automatically when you run :code:`west flash`. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_nano_33_iot + :goals: build + :compact: + +#. Connect the Nano 33 IOT to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_nano_33_iot + :goals: flash + :compact: + + You should see "Hello World! arduino_nano_33_iot" in your terminal. + +References +********** + +.. target-notes:: + +.. _Arduino Store: + https://store.arduino.cc/arduino-nano-33-iot + +.. _schematic: + https://content.arduino.cc/assets/NANO33IoTV2.0_sch.pdf diff --git a/boards/arm/arduino_nano_33_iot/pre_dt_board.cmake b/boards/arduino/nano_33_iot/pre_dt_board.cmake similarity index 100% rename from boards/arm/arduino_nano_33_iot/pre_dt_board.cmake rename to boards/arduino/nano_33_iot/pre_dt_board.cmake diff --git a/boards/arduino/nicla_sense_me/Kconfig.arduino_nicla_sense_me b/boards/arduino/nicla_sense_me/Kconfig.arduino_nicla_sense_me new file mode 100644 index 00000000000..e79b67a84b3 --- /dev/null +++ b/boards/arduino/nicla_sense_me/Kconfig.arduino_nicla_sense_me @@ -0,0 +1,7 @@ +# Arduino Nicla Sense ME board configuration + +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_NICLA_SENSE_ME + select SOC_NRF52832_QFAA diff --git a/boards/arduino/nicla_sense_me/Kconfig.defconfig b/boards/arduino/nicla_sense_me/Kconfig.defconfig new file mode 100644 index 00000000000..b1e6a59d7d3 --- /dev/null +++ b/boards/arduino/nicla_sense_me/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Arduino Nicla Sense ME board configuration + +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARDUINO_NICLA_SENSE_ME + +config BT_CTLR + default BT + +endif # BOARD_ARDUINO_NICLA_SENSE_ME diff --git a/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me-pinctrl.dtsi b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me-pinctrl.dtsi rename to boards/arduino/nicla_sense_me/arduino_nicla_sense_me-pinctrl.dtsi diff --git a/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me.dts b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts similarity index 100% rename from boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me.dts rename to boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts diff --git a/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me.yaml b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.yaml similarity index 100% rename from boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me.yaml rename to boards/arduino/nicla_sense_me/arduino_nicla_sense_me.yaml diff --git a/boards/arduino/nicla_sense_me/arduino_nicla_sense_me_defconfig b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me_defconfig new file mode 100644 index 00000000000..f8691d1c1ce --- /dev/null +++ b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/arduino_nicla_sense_me/board.cmake b/boards/arduino/nicla_sense_me/board.cmake similarity index 100% rename from boards/arm/arduino_nicla_sense_me/board.cmake rename to boards/arduino/nicla_sense_me/board.cmake diff --git a/boards/arduino/nicla_sense_me/board.yml b/boards/arduino/nicla_sense_me/board.yml new file mode 100644 index 00000000000..0a470e79ce5 --- /dev/null +++ b/boards/arduino/nicla_sense_me/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_nicla_sense_me + vendor: arduino + socs: + - name: nrf52832 diff --git a/boards/arm/arduino_nicla_sense_me/doc/arduino_nicla_sense_me.jpg b/boards/arduino/nicla_sense_me/doc/arduino_nicla_sense_me.jpg similarity index 100% rename from boards/arm/arduino_nicla_sense_me/doc/arduino_nicla_sense_me.jpg rename to boards/arduino/nicla_sense_me/doc/arduino_nicla_sense_me.jpg diff --git a/boards/arm/arduino_nicla_sense_me/doc/arduino_nicla_sense_me_pinout.jpg b/boards/arduino/nicla_sense_me/doc/arduino_nicla_sense_me_pinout.jpg similarity index 100% rename from boards/arm/arduino_nicla_sense_me/doc/arduino_nicla_sense_me_pinout.jpg rename to boards/arduino/nicla_sense_me/doc/arduino_nicla_sense_me_pinout.jpg diff --git a/boards/arm/arduino_nicla_sense_me/doc/index.rst b/boards/arduino/nicla_sense_me/doc/index.rst similarity index 100% rename from boards/arm/arduino_nicla_sense_me/doc/index.rst rename to boards/arduino/nicla_sense_me/doc/index.rst diff --git a/boards/arm/bbc_microbit_v2/pre_dt_board.cmake b/boards/arduino/nicla_sense_me/pre_dt_board.cmake similarity index 100% rename from boards/arm/bbc_microbit_v2/pre_dt_board.cmake rename to boards/arduino/nicla_sense_me/pre_dt_board.cmake diff --git a/boards/arduino/opta/Kconfig.arduino_opta b/boards/arduino/opta/Kconfig.arduino_opta new file mode 100644 index 00000000000..d591283a6ff --- /dev/null +++ b/boards/arduino/opta/Kconfig.arduino_opta @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_OPTA + select SOC_STM32H747XX_M4 diff --git a/boards/arm/arduino_opta_m4/arduino_opta_m4.dts b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts similarity index 100% rename from boards/arm/arduino_opta_m4/arduino_opta_m4.dts rename to boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m4.yaml b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.yaml new file mode 100644 index 00000000000..e7495a72ea1 --- /dev/null +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.yaml @@ -0,0 +1,21 @@ +identifier: arduino_opta/stm32h747xx/m4 +name: ARDUINO OPTA (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 288 +flash: 512 +supported: + - gpio +testing: + ignore_tags: + - mpu + - nfc + - net + - flash + - input + - mcumgr +vendor: arduino diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig b/boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig new file mode 100644 index 00000000000..f9f3e39d9c7 --- /dev/null +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2023 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# clock configuration +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable pin controller +CONFIG_PINCTRL=y + +# Use zephyr,code-partition as flash offset +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/arduino_opta_m4/board.cmake b/boards/arduino/opta/board.cmake similarity index 100% rename from boards/arm/arduino_opta_m4/board.cmake rename to boards/arduino/opta/board.cmake diff --git a/boards/arduino/opta/board.yml b/boards/arduino/opta/board.yml new file mode 100644 index 00000000000..c572627b348 --- /dev/null +++ b/boards/arduino/opta/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_opta + vendor: arduino + socs: + - name: stm32h747xx diff --git a/boards/arm/arduino_opta_m4/doc/img/arduino_opta.jpeg b/boards/arduino/opta/doc/img/arduino_opta.jpeg similarity index 100% rename from boards/arm/arduino_opta_m4/doc/img/arduino_opta.jpeg rename to boards/arduino/opta/doc/img/arduino_opta.jpeg diff --git a/boards/arduino/opta/doc/index.rst b/boards/arduino/opta/doc/index.rst new file mode 100644 index 00000000000..c50c7e27ec9 --- /dev/null +++ b/boards/arduino/opta/doc/index.rst @@ -0,0 +1,177 @@ +.. _arduino_opta_m4_board: + +Arduino OPTA M4-Core +#################### + +Overview +******** + +The Arduino™ Opta® is a secure micro Programmable Logic Controller (PLC) +with Industrial Internet of Things (IoT) capabilities. + +Developed in partnership with Finder®, this device supports both the Arduino +programming language and standard IEC-61131-3 PLC programming languages, +such as Ladder Diagram (LD), Sequential Function Chart (SFC), +Function Block Diagram (FBD), Structured Text (ST), and Instruction List (IL), +making it an ideal device for automation engineers. + +For Zephyr RTOS, only the M4 is supported for now, making the M7 run the PLC +tasks while the M4 core under Zephyr acts as a coprocessor. + +Additionally, the device features: + +- Ethernet compliant with IEEE802.3-2002 +- 16MB QSPI Flash +- 4 x green color status LEDs +- 1 x user push-button +- 1 x reset push-button accessible via pinhole +- 8 x analog inputs +- 4 x isolated relay outputs + +.. image:: img/arduino_opta.jpeg + :align: center + :alt: ARDUINO-OPTA + +More information about the board can be found at the `ARDUINO-OPTA website`_. +More information about STM32H747XIH6 can be found here: + +- `STM32H747XI on www.st.com`_ +- `STM32H747xx reference manual`_ +- `STM32H747xx datasheet`_ + +Supported Features +================== + +The current Zephyr arduino_opta_m4 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| IPM | on-chip | virtual mailbox based on HSEM | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration per core can be found in the defconfig file: +:zephyr_file:`boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig` + +Pin Mapping +=========== + +ARDUINO OPTA M4 has access to the 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `ARDUINO-OPTA website`_. + +Default Zephyr Peripheral Mapping +--------------------------------- + +- Status LED1 : PI0 +- Status LED2 : PI1 +- Status LED3 : PI3 +- Status LED4 : PH15 +- User button : PE4 + +System Clock +============ + +The STM32H747I System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the CPU2 (Cortex-M4) System clock +is driven at 240MHz. PLL clock is fed by a 25MHz high speed external clock. + +Resources sharing +================= + +The dual core nature of STM32H747 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Programming and Debugging +************************* + +Applications for the ``arduino_opta`` use the regular Zephyr build commands. +See :ref:`build_an_application` for more information about application builds. + +Flashing +======== + +Flashing operation will depend on the target to be flashed and the SoC +option bytes configuration. The OPTA has a DFU capable bootloader which +can be accessed by connecting the device to the USB, and then pressing +the RESET button shortly twice, the RESET-LED on the board will fade +indicating the board is in bootloader mode. + +By default: + + - CPU2 (Cortex-M4) boot address is set to 0x08180000 (OB: BOOT_CM4_ADD0) + +Zephyr flash configuration has been set to meet these default settings. + +Flashing an application to ARDUINO OPTA M4 +------------------------------------------ + +First, connect the device to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: arduino_opta/stm32h747xx/m4 + :goals: build flash + +Starting the application on the ARDUINO OPTA M4 +----------------------------------------------- + +Make sure the option bytes are set to prevent the M4 from auto-starting, and +that the M7 side starts the M4 at the correct Flash address. + +This can be done by selecting in the Arduino IDE's "Tools" / "Flash Split" +menu the "1.5MB M7 + 0.5MB M4" option, and loading a sketch that contains +at least the following code: + + .. code-block:: cpp + + #include + + void setup() { + RPC.begin(); + } + + void loop() { } + +Debugging +========= + +Debugging is not yet supported by this board, since the debug port does +not have an easy access. + +.. _ARDUINO-OPTA website: + https://docs.arduino.cc/hardware/opta + +.. _STM32H747XI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html + +.. _STM32H747xx reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879.pdf + +.. _STM32H747xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h747xi.pdf diff --git a/boards/arduino/portenta_h7/CMakeLists.txt b/boards/arduino/portenta_h7/CMakeLists.txt new file mode 100644 index 00000000000..526629d7110 --- /dev/null +++ b/boards/arduino/portenta_h7/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_ARDUINO_PORTENTA_H7_STM32H747XX_M7) + +zephyr_library() +zephyr_library_sources(board.c) + +endif() diff --git a/boards/arduino/portenta_h7/Kconfig.arduino_portenta_h7 b/boards/arduino/portenta_h7/Kconfig.arduino_portenta_h7 new file mode 100644 index 00000000000..fa3b247b922 --- /dev/null +++ b/boards/arduino/portenta_h7/Kconfig.arduino_portenta_h7 @@ -0,0 +1,8 @@ +# Arduino Portenta H7 board configuration + +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_PORTENTA_H7 + select SOC_STM32H747XX_M7 if BOARD_ARDUINO_PORTENTA_H7_STM32H747XX_M7 + select SOC_STM32H747XX_M4 if BOARD_ARDUINO_PORTENTA_H7_STM32H747XX_M4 diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7-common.dtsi b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi similarity index 100% rename from boards/arm/arduino_portenta_h7/arduino_portenta_h7-common.dtsi rename to boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts similarity index 100% rename from boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4.dts rename to boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml new file mode 100644 index 00000000000..afbca313573 --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml @@ -0,0 +1,17 @@ +identifier: arduino_portenta_h7/stm32h747xx/m4 +name: Arduino Portenta H7 (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 288 +flash: 1024 +supported: + - gpio +testing: + ignore_tags: + - mpu + - nfc +vendor: arduino diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig new file mode 100644 index 00000000000..4929eecabb7 --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Clock configuration +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable pin controller +CONFIG_PINCTRL=y + +# Enable uart driver +# CONFIG_SERIAL=y + +# By default CONSOLE is assigned to m7 +# CONFIG_CONSOLE=y +# CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts similarity index 100% rename from boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7.dts rename to boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml new file mode 100644 index 00000000000..ee73966dbfe --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml @@ -0,0 +1,13 @@ +identifier: arduino_portenta_h7/stm32h747xx/m7 +name: Arduino Portenta H7 (M7) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 1024 +supported: + - gpio +vendor: arduino diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig new file mode 100644 index 00000000000..18f533bf91d --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig @@ -0,0 +1,36 @@ +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +# Enable the internal SMPS regulator +CONFIG_POWER_SUPPLY_DIRECT_SMPS=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable clocks +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable pin controller +CONFIG_PINCTRL=y + +# Use zephyr,code-partition as flash offset +CONFIG_USE_DT_CODE_PARTITION=y + +# Disable following to assign serial ports to m4 core + +# Enable uart driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable regulator +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED=y diff --git a/boards/arm/arduino_portenta_h7/board.c b/boards/arduino/portenta_h7/board.c similarity index 100% rename from boards/arm/arduino_portenta_h7/board.c rename to boards/arduino/portenta_h7/board.c diff --git a/boards/arm/arduino_portenta_h7/board.cmake b/boards/arduino/portenta_h7/board.cmake similarity index 100% rename from boards/arm/arduino_portenta_h7/board.cmake rename to boards/arduino/portenta_h7/board.cmake diff --git a/boards/arduino/portenta_h7/board.yml b/boards/arduino/portenta_h7/board.yml new file mode 100644 index 00000000000..be2ba58da96 --- /dev/null +++ b/boards/arduino/portenta_h7/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_portenta_h7 + vendor: arduino + socs: + - name: stm32h747xx diff --git a/boards/arm/arduino_portenta_h7/doc/img/arduino_portenta_h7.jpeg b/boards/arduino/portenta_h7/doc/img/arduino_portenta_h7.jpeg similarity index 100% rename from boards/arm/arduino_portenta_h7/doc/img/arduino_portenta_h7.jpeg rename to boards/arduino/portenta_h7/doc/img/arduino_portenta_h7.jpeg diff --git a/boards/arduino/portenta_h7/doc/index.rst b/boards/arduino/portenta_h7/doc/index.rst new file mode 100644 index 00000000000..87b7aefdfe5 --- /dev/null +++ b/boards/arduino/portenta_h7/doc/index.rst @@ -0,0 +1,144 @@ +.. _arduino_portenta_h7_board: + +Arduino Portenta H7 +################### + +Overview +******** + +The Portenta H7 enables a wide diversity of applications taking benefit +from Computer Vision, PLCs, Robotics controller, High-end industrial machinery +and high-speed booting computation (ms). + +The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU, +with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, +large set of peripherals, SMPS, and MIPI-DSI. + +Additionally, the board features: +- USB OTG FS +- 3 color user LEDs + +.. image:: img/arduino_portenta_h7.jpeg + :width: 500px + :align: center + :height: 325px + :alt: ARDUINO_PORTENTA_H7 + +More information about the board can be found at the `ARDUINO_PORTENTA_H7 website`_. +More information about STM32H747XIH6 can be found here: + +- `STM32H747XI on www.st.com`_ +- `STM32H747xx reference manual`_ +- `STM32H747xx datasheet`_ + +Supported Features +================== + +The current Zephyr arduino_portenta_h7 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| IPM | on-chip | virtual mailbox based on HSEM | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +Resources sharing +================= + +The dual core nature of STM32H747 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Building and Flashing +************************* + +Applications for the ``arduino_portenta_h7`` board should be built per core target, +using either ``arduino_portenta_h7_m7`` or ``arduino_portenta_h7_m4`` as the target. +See :ref:`build_an_application` for more information about application builds. + + +Flashing +======== + +Installing dfu-util +------------------- + +This board requires dfu-utils for flashing. It is recommended to use at least +v0.8 of `dfu-util`_. The package available in debian/ubuntu can be quite old, so you might +have to build dfu-util from source. + +Flashing an application to STM32H747I M7 Core +--------------------------------------------- + +First, connect the Arduino Portenta H7 board to your host computer using +the USB port to prepare it for flashing. Double tap the button to put the board +into the Arduino Bootloader mode. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_portenta_h7/stm32h747xx/m7 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arduino_portenta_h7 + +Similarly, you can build and flash samples on the M4 target. For this, please +take care of the resource sharing (UART port used for console for instance). + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: arduino_portenta_h7/stm32h747xx/m4 + :goals: build flash + +.. _ARDUINO_PORTENTA_H7 website: + https://docs.arduino.cc/hardware/portenta-h7 + +.. _STM32H747XI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html + +.. _STM32H747xx reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879.pdf + +.. _STM32H747xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h747xi.pdf + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html diff --git a/boards/arduino/uno_r4_minima/Kconfig.arduino_uno_r4_minima b/boards/arduino/uno_r4_minima/Kconfig.arduino_uno_r4_minima new file mode 100644 index 00000000000..2fae481238c --- /dev/null +++ b/boards/arduino/uno_r4_minima/Kconfig.arduino_uno_r4_minima @@ -0,0 +1,5 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_UNO_R4_MINIMA + select SOC_R7FA4M1AB3CFM diff --git a/boards/arm/arduino_uno_r4/arduino_uno_r4_common.dtsi b/boards/arduino/uno_r4_minima/arduino_uno_r4_common.dtsi similarity index 100% rename from boards/arm/arduino_uno_r4/arduino_uno_r4_common.dtsi rename to boards/arduino/uno_r4_minima/arduino_uno_r4_common.dtsi diff --git a/boards/arm/arduino_uno_r4/arduino_uno_r4_minima-pinctrl.dtsi b/boards/arduino/uno_r4_minima/arduino_uno_r4_minima-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_uno_r4/arduino_uno_r4_minima-pinctrl.dtsi rename to boards/arduino/uno_r4_minima/arduino_uno_r4_minima-pinctrl.dtsi diff --git a/boards/arm/arduino_uno_r4/arduino_uno_r4_minima.dts b/boards/arduino/uno_r4_minima/arduino_uno_r4_minima.dts similarity index 100% rename from boards/arm/arduino_uno_r4/arduino_uno_r4_minima.dts rename to boards/arduino/uno_r4_minima/arduino_uno_r4_minima.dts diff --git a/boards/arm/arduino_uno_r4/arduino_uno_r4_minima.yaml b/boards/arduino/uno_r4_minima/arduino_uno_r4_minima.yaml similarity index 100% rename from boards/arm/arduino_uno_r4/arduino_uno_r4_minima.yaml rename to boards/arduino/uno_r4_minima/arduino_uno_r4_minima.yaml diff --git a/boards/arm/arduino_uno_r4/arduino_uno_r4_minima_defconfig b/boards/arduino/uno_r4_minima/arduino_uno_r4_minima_defconfig similarity index 76% rename from boards/arm/arduino_uno_r4/arduino_uno_r4_minima_defconfig rename to boards/arduino/uno_r4_minima/arduino_uno_r4_minima_defconfig index 57abb934998..bcd05338d44 100644 --- a/boards/arm/arduino_uno_r4/arduino_uno_r4_minima_defconfig +++ b/boards/arduino/uno_r4_minima/arduino_uno_r4_minima_defconfig @@ -1,22 +1,19 @@ # Copyright (c) 2023 TOKITA Hiroshi # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_RA4M1=y -CONFIG_SOC_R7FA4M1AB3CFM=y - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 CONFIG_BUILD_OUTPUT_HEX=y -# enable uart driver +# Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y CONFIG_PINCTRL=y diff --git a/boards/arm/arduino_uno_r4/board.cmake b/boards/arduino/uno_r4_minima/board.cmake similarity index 100% rename from boards/arm/arduino_uno_r4/board.cmake rename to boards/arduino/uno_r4_minima/board.cmake diff --git a/boards/arduino/uno_r4_minima/board.yml b/boards/arduino/uno_r4_minima/board.yml new file mode 100644 index 00000000000..f4dc7b8467b --- /dev/null +++ b/boards/arduino/uno_r4_minima/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_uno_r4_minima + vendor: arduino + socs: + - name: r7fa4m1ab3cfm diff --git a/boards/arm/arduino_uno_r4/doc/index.rst b/boards/arduino/uno_r4_minima/doc/index.rst similarity index 100% rename from boards/arm/arduino_uno_r4/doc/index.rst rename to boards/arduino/uno_r4_minima/doc/index.rst diff --git a/boards/arduino/zero/Kconfig.arduino_zero b/boards/arduino/zero/Kconfig.arduino_zero new file mode 100644 index 00000000000..ade23a1229f --- /dev/null +++ b/boards/arduino/zero/Kconfig.arduino_zero @@ -0,0 +1,6 @@ +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_ZERO + select SOC_SAMD21G18A diff --git a/boards/arm/arduino_zero/arduino_zero-pinctrl.dtsi b/boards/arduino/zero/arduino_zero-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_zero/arduino_zero-pinctrl.dtsi rename to boards/arduino/zero/arduino_zero-pinctrl.dtsi diff --git a/boards/arm/arduino_zero/arduino_zero.dts b/boards/arduino/zero/arduino_zero.dts similarity index 100% rename from boards/arm/arduino_zero/arduino_zero.dts rename to boards/arduino/zero/arduino_zero.dts diff --git a/boards/arm/arduino_zero/arduino_zero.yaml b/boards/arduino/zero/arduino_zero.yaml similarity index 100% rename from boards/arm/arduino_zero/arduino_zero.yaml rename to boards/arduino/zero/arduino_zero.yaml diff --git a/boards/arduino/zero/arduino_zero_defconfig b/boards/arduino/zero/arduino_zero_defconfig new file mode 100644 index 00000000000..c7f66b36c36 --- /dev/null +++ b/boards/arduino/zero/arduino_zero_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/arduino_zero/board.cmake b/boards/arduino/zero/board.cmake similarity index 100% rename from boards/arm/arduino_zero/board.cmake rename to boards/arduino/zero/board.cmake diff --git a/boards/arduino/zero/board.yml b/boards/arduino/zero/board.yml new file mode 100644 index 00000000000..86d4a97c112 --- /dev/null +++ b/boards/arduino/zero/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_zero + vendor: arduino + socs: + - name: samd21g18a diff --git a/boards/arm/arduino_zero/doc/img/arduino_zero.jpg b/boards/arduino/zero/doc/img/arduino_zero.jpg similarity index 100% rename from boards/arm/arduino_zero/doc/img/arduino_zero.jpg rename to boards/arduino/zero/doc/img/arduino_zero.jpg diff --git a/boards/arduino/zero/doc/index.rst b/boards/arduino/zero/doc/index.rst new file mode 100644 index 00000000000..46eb837040c --- /dev/null +++ b/boards/arduino/zero/doc/index.rst @@ -0,0 +1,166 @@ +.. _arduino_zero: + +Arduino/Genuino Zero +#################### + +Overview +******** + +The Arduino Zero is a maker-friendly development board with +Atmel’s Embedded Debugger (EDBG), which provides a full +debug interface without the need for additional hardware. + +.. image:: img/arduino_zero.jpg + :align: center + :alt: Arduino Zero + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- 3 user LEDs +- One reset button +- On-board USB based EDBG unit with serial console +- Native USB port + +Supported Features +================== + +The arduino_zero board configuration supports the following hardware +features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| DAC | on-chip | Digital to analogue converter | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/arduino/zero/arduino_zero_defconfig`. + +Connections and IOs +=================== + +The `Arduino store`_ has detailed information about board +connections. Download the `Arduino Zero Schematic`_ for more detail. + +System Clock +============ + +The SAMD21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. The internal +APB and GCLK unit are set up in the same way as the upstream Arduino +libraries. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. One of the USARTs +(SERCOM5) is connected to the onboard Atmel Embedded Debugger (EDBG). +SERCOM0 is available on the D0/D1 pins. + +PWM +=== + +The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC2 instead of by GPIO. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the Arduino Zero, SERCOM4 +is available on the 6 pin connector at the edge of the board. + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +DAC +=== + +The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On the +Arduino Zero, the DAC is available on pin A0. + +Programming and Debugging +************************* + +The Arduino Zero comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMD21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_zero + :goals: build + :compact: + +#. Connect the Arduino Zero to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_zero + :goals: flash + :compact: + + You should see "Hello World! arduino_zero" in your terminal. + +References +********** + +.. target-notes:: + +.. _Arduino Store: + https://store.arduino.cc/genuino-zero + +.. _Arduino Zero Schematic: + https://www.arduino.cc/en/uploads/Main/Zero_V1.0.pdf diff --git a/boards/arm/arduino_zero/pre_dt_board.cmake b/boards/arduino/zero/pre_dt_board.cmake similarity index 100% rename from boards/arm/arduino_zero/pre_dt_board.cmake rename to boards/arduino/zero/pre_dt_board.cmake diff --git a/boards/arm/arduino_zero/support/openocd.cfg b/boards/arduino/zero/support/openocd.cfg similarity index 100% rename from boards/arm/arduino_zero/support/openocd.cfg rename to boards/arduino/zero/support/openocd.cfg diff --git a/boards/arm/96b_aerocore2/Kconfig.board b/boards/arm/96b_aerocore2/Kconfig.board deleted file mode 100644 index 55d8a706d1b..00000000000 --- a/boards/arm/96b_aerocore2/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_AEROCORE2 - bool "96Boards AEROCORE2 (STM32F427)" - depends on SOC_STM32F427XX diff --git a/boards/arm/96b_aerocore2/Kconfig.defconfig b/boards/arm/96b_aerocore2/Kconfig.defconfig deleted file mode 100644 index 02d82f6f25a..00000000000 --- a/boards/arm/96b_aerocore2/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_AEROCORE2 - -config BOARD - default "96b_aerocore2" - -endif # BOARD_96B_AEROCORE2 diff --git a/boards/arm/96b_aerocore2/doc/index.rst b/boards/arm/96b_aerocore2/doc/index.rst deleted file mode 100644 index 6d56911c2f1..00000000000 --- a/boards/arm/96b_aerocore2/doc/index.rst +++ /dev/null @@ -1,350 +0,0 @@ -.. _96b_aerocore2_board: - -96Boards Aerocore2 -################## - -Overview -******** - -The 96Boards Aerocore2 Mezzanine is based on the STMicroelectronics -STM32F427VIT6 Cortex-M4 CPU primarily designed for use in drones. -This board acts as a mezzanine platform for all 96Boards CE compliant -boards. It can also be used as a standalone board. - - -.. figure:: img/96b_aerocore2.jpg - :align: center - :alt: 96Boards Aerocore2 - - 96Boards Aerocore2 - -Hardware -******** - -96Boards Aerocore2 provides the following hardware components: - -- STM32F427VIT6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 168 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 2048 KB Flash -- 256 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 16 channels -- RTC -- Advanced-control Timers (2) -- General Purpose Timers (10) -- Watchdog Timers (2) -- USART/UART (4) -- I2C (3) -- SPI (3) -- SDIO -- USB 2.0 OTG FS -- DMA Controller - -More information about STM32F427VIT6 can be found here: - - `STM32F427 on www.st.com`_ - -Supported Features -================== - -The Zephyr 96b_aerocore2 board configuration supports the following hardware -features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| PWM | on-chip | timers / pwm | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ - -More details about the board can be found at `96Boards website`_. - -The default configuration can be found in the defconfig file: - - ``boards/arm/96b_aerocore2/96b_aerocore2_defconfig`` - -Connections and IOs -=================== - -LED ---- - -- LED1 / User1 LED = PE10 -- LED2 / User2 LED = PE9 - -External Connectors -------------------- - -Octal PWM Header (J1) - -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | Pin # | Signal Name | -+=======+=============+=========================+=======+=============+=======+=============+ -| 1 | PWM4_CH1 | PD12 | 2 | 5.0v | 3 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 4 | PWM4_CH2 | PD13 | 5 | 5.0v | 6 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 7 | PWM4_CH3 | PD14 | 8 | 5.0v | 9 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 10 | PWM4_CH4 | PD15 | 11 | 5.0v | 12 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 13 | PWM5_CH1 | PA0 | 14 | 5.0v | 15 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 16 | PWM5_CH2 | PA1 | 17 | 5.0v | 18 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 19 | PWM5_CH3 | PA2 | 20 | 5.0v | 21 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 22 | PWM5_CH4 | PA3 | 23 | 5.0v | 24 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ - - -IO Header J11 - -+-------+-------------+-------+-------------+ -| PIN # | Signal Name | PIN # | Signal Name | -+=======+=============+=======+=============+ -| 1 | PB9 | 2 | PB8* | -+-------+-------------+-------+-------------+ -| 3 | PC9 | 4 | PB0 | -+-------+-------------+-------+-------------+ -| 5 | PE5 | 6 | NA | -+-------+-------------+-------+-------------+ -| 7 | PE6 | 8 | NA | -+-------+-------------+-------+-------------+ -| 9 | PC6 | 10 | NA | -+-------+-------------+-------+-------------+ -| 11 | PC7 | 12 | NA | -+-------+-------------+-------+-------------+ -| 13 | PC8 | 14 | NA | -+-------+-------------+-------+-------------+ -| 15 | PA8 | 16 | GND | -+-------+-------------+-------+-------------+ -| 17 | PA9 | 18 | 3v3 | -+-------+-------------+-------+-------------+ -| 19 | PA10 | 20 | GND | -+-------+-------------+-------+-------------+ - -* PB8 is connected to a watchdog buzzer, It needs to be pulsed every 10 seconds to keep the buzzer silent. - -IO Header J5 - -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | STM32F427 Functions Pin | -+=======+=============+=========================+=======+=============+=========================+ -| 1 | AGND | AGND | 2 | ADC1_13 | PC3 | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 3 | ADC1_12 | PC2 | 4 | ADC1_11 | PC1 | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 5 | I2C_SDA | PB11 | 6 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 7 | I2C_SCL | PB10 | 8 | VCC 3v3 | VCC 3v3 | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 9 | NC | NC | 10 | NC | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 11 | NC | NC | 12 | NC | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 13 | UART_TX 7 | PE8 | 14 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 15 | UART_RX 7 | PE7 | 16 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 17 | UART_TX 2 | PD5 | 18 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 19 | UART_TX 2 | PD6 | 20 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 21 | NC | NC | 10 | NC | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 23 | NC | NC | 10 | NC | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 25 | SPI1_NIRQ | PC5 | 26 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 27 | SPI1_CLK | PA5 | 28 | SPI1_MISO | PA6 | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 29 | SPI1_CS0 | PA4 | 30 | SPI1_MOSI | PA7 | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 31 | CAN_TX | PD1 | 32 | CANH | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 33 | CAN_RX | PD0 | 34 | CANL | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ - - -GPS connector J15 - -+-------+-------------+-------------------------+ -| PIN # | Signal Name | STM32F427 Functions Pin | -+=======+=============+=========================+ -| 1 | V_OUT 5v | NC | -+-------+-------------+-------------------------+ -| 2 | UART1_TX | PB6 | -+-------+-------------+-------------------------+ -| 3 | UART1_RX | PB7 | -+-------+-------------+-------------------------+ -| 4 | VCC 3v3 | NC | -+-------+-------------+-------------------------+ -| 5 | GND | GND | -+-------+-------------+-------------------------+ - - -Spektrum connector J3 - -+-------+-------------+-------------------------+ -| PIN # | Signal Name | STM32F427 Functions Pin | -+=======+=============+=========================+ -| 1 | VCC 3v3 | NC | -+-------+-------------+-------------------------+ -| 2 | GND | GND | -+-------+-------------+-------------------------+ -| 3 | UART8_RX | PE0 | -+-------+-------------+-------------------------+ - - -External Clock Sources ----------------------- - -STM32F4 has one external oscillator. The frequency of the clock is -32.768 kHz. The internal 16MHz clock is used as the main clock. - -Serial Port ------------ - -96Boards Aerocore2 board has up to 4 U(S)ARTs. The Zephyr console output is -assigned to USART7. Default settings are 115200 8N1. - -I2C ---- - -96Boards Aerocore2 board has 1 I2C port. The default I2C mapping for Zephyr is: - -- I2C1_SCL : PB10 -- I2C1_SDA : PB11 - -SPI ---- - -96Boards Aerocore2 board has 1 SPI port. The default SPI mapping for Zephyr is: - -- SPI1_CS0 : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 - -USB -=== - -96Boards Aerocore2 board has a USB OTG dual-role device (DRD) controller that -supports both device and host functions through its mini "OTG" USB connector. -Only USB device functions are supported in Zephyr at the moment. - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. The ROM bootloader -supports flashing via USB (DFU), UART, I2C and SPI. You can read more about -how to enable and use the ROM bootloader by checking the application -note `AN2606`_, page 109. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -Flashing an Application to 96Boards Aerocore2 ---------------------------------------------- - -Connect the micro-USB cable to the USB OTG/STM_CONSOLE Aerocore2 port and to your computer. -The board should power ON. Force the board into DFU mode by keeping the BOOT0 -switch pressed while pressing and releasing the RST switch. - -The BOOT button is located at the back-side of the PCB. - -Confirm that the board is in DFU mode: - -.. code-block:: console - - $ sudo dfu-util -l - dfu-util 0.8 - Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. - Copyright 2010-2014 Tormod Volden and Stefan Schmidt - This program is Free Software and has ABSOLUTELY NO WARRANTY - Please report bugs to dfu-util@lists.gnumonks.org - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", serial="3574364C3034" - Found Runtime: [05ac:8290] ver=0104, devnum=2, cfg=1, intf=5, alt=0, name="UNKNOWN", serial="UNKNOWN" - -You should see following confirmation on your Linux host: - -.. code-block:: console - - $ dmesg - usb 1-2.1: new full-speed USB device number 14 using xhci_hcd - usb 1-2.1: New USB device found, idVendor=0483, idProduct=df11 - usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 - usb 1-2.1: Product: STM32 BOOTLOADER - usb 1-2.1: Manufacturer: STMicroelectronics - usb 1-2.1: SerialNumber: 3574364C3034 - -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_aerocore2 - :goals: build flash - -Connect a USB-TTL dongle to the UART_7 header port and to your computer. -Run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board 96Boards Aerocore2 -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. -The ``-b`` option sets baud rate ignoring the value from config. - -Press the Reset button and you should see the following message in your -terminal: - -.. code-block:: console - - Hello World! arm - -.. _96Boards website: - https://www.96boards.org/product/aerocore2/ - -.. _STM32F427 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32f427vi.html - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _AN2606: - https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf diff --git a/boards/arm/96b_argonkey/Kconfig.board b/boards/arm/96b_argonkey/Kconfig.board deleted file mode 100644 index e259d3b23f2..00000000000 --- a/boards/arm/96b_argonkey/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards Argonkey Board Configuration - -# Copyright (c) 2018 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_ARGONKEY - bool "96Boards Argonkey" - depends on SOC_STM32F412CX diff --git a/boards/arm/96b_argonkey/Kconfig.defconfig b/boards/arm/96b_argonkey/Kconfig.defconfig deleted file mode 100644 index 7ee85442eae..00000000000 --- a/boards/arm/96b_argonkey/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# 96Boards Argonkey Board Configuration - -# Copyright (c) 2018 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_ARGONKEY - -config BOARD - default "96b_argonkey" - -if LSM6DSL - -choice LSM6DSL_TRIGGER_MODE - default LSM6DSL_TRIGGER_GLOBAL_THREAD -endchoice - -config LSM6DSL_SENSORHUB - default y - -choice LSM6DSL_EXTERNAL_SENSOR_0 - default LSM6DSL_EXT0_LIS2MDL -endchoice - -endif # LSM6DSL - -endif # BOARD_96B_ARGONKEY diff --git a/boards/arm/96b_argonkey/doc/index.rst b/boards/arm/96b_argonkey/doc/index.rst deleted file mode 100644 index 6221adee72c..00000000000 --- a/boards/arm/96b_argonkey/doc/index.rst +++ /dev/null @@ -1,240 +0,0 @@ -.. _96b_argonkey: - -96Boards Argonkey -################# - -Overview -******** - -96Boards Argonkey board is based on the ST Microelectronics STM32F412CG -Cortex M4 CPU. - -This board acts as a sensor hub platform for all 96Boards compliant -family products. It can also be used as a standalone board. - -.. figure:: img/96b_argonkey.jpg - :align: center - :alt: 96Boards Argonkey - - 96Boards Argonkey - -Hardware -******** - -96Boards Argonkey provides the following hardware components: - -- STM32F412CG in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 100 MHz max CPU frequency -- 1.8V work voltage -- 1024 KB Flash -- 256 KB SRAM -- On board sensors: - - - Humidity: STMicro HTS221 - - Temperature/Pressure: STMicro LPS22HB - - ALS: Intersil ISL29034 - - Proximity: STMicro VL53L0X - - Accelerometer/Gyroscope: STMicro LSM6DSL - - Geomagnetic: STMicro LIS2MDL - - AMR Hall sensor: MRMS501A - - Microphone: STMicro MP34DT05 - -- 2 User LEDs -- 16 General purpose LEDs -- GPIO with external interrupt capability -- UART -- I2C (3) -- SPI (1) -- I2S (1) - -Supported Features -================== - -The Zephyr 96b_argonkey board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ - -More information about the board can be found at the -`ARGONKEY website`_. - -The default board configuration can be found in the defconfig file: - - ``boards/arm/96b_argonkey/96b_argonkey_defconfig`` - -Connections and IOs -=================== - -LED ---- - -- LED1 / User1 LED = PB2 -- LED2 / User2 LED = PC13 - -Push buttons ------------- - -- BUTTON = RST (BT1) -- BUTTON = USR (BT2) - -System Clock -============ - -96Boards Argonkey can be driven by an internal oscillator as well as the main -PLL clock. In default board configuration, the 16MHz external oscillator is -used to drive the main PLL clock to generate a System Clock (SYSCLK) at 84MHz. -On the bus side, AHB clock runs at 84MHz, while APB1/APB2 clock runs at 42MHz. - -Serial Port -=========== - -On 96Boards Argonkey, Zephyr console output is assigned to USART1. -Default settings are 115200 8N1. - -I2C ---- - -96Boards Argonkey board has up to 3 I2Cs. The default I2C mapping is: - -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PB9 -- I2C3_SCL : PA8 -- I2C3_SCL : PB4 - -I2C3 goes to the P2 connector and can be used to attach external sensors. -It goes to 100Kbit maximum. - -SPI ---- -96Boards Argonkey board has 2 SPIs. SPI1 is used in slave mode as the communication -bus with the AP. SPI2 is used in master mode to control the LSM6DSL sensor. -The default SPI mapping is: - -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 - -Programming and Debugging -************************* - -Building -======== - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_argonkey - :goals: build - -Flashing -======== - -96Boards Argonkey can be flashed by two methods, one using the ROM -bootloader and another using the SWD debug port (which requires additional -hardware). - -Flashing using the ROM bootloader requires a special activation pattern, -which can be triggered by using the BOOT0 pin. The ROM bootloader supports -flashing via USB (DFU), UART, I2C and SPI, but this document describes the -UART case only. You can read more about how to enable and use the ROM -bootloader by checking the application note `AN2606`_ . - -Using ROM bootloader: ---------------------- - -Hereafter the documents describes basic steps to perform ArgonKey firmware -flashing on a Linux PC using UART as communication channel. - -1. Connect ArgonKey UART to your Linux PC using, for example, a USB-TTL serial - cable. The flashing procedure has been tested using a `TTL-232RG`_ cable with - FTDI chip. The UART pins on ArgonKey can be found on the P3 low speed - expansion connector on the back of the board. - - - GND (black) to ArgonKey GND (P3.1) - - TXD (orange) to ArgonKey UART0_TXD (P3.5) - - RXD (yellow) to ArgonKey UART0_RXD (P3.7) - - When the USB cable is inserted to the Linux PC the following device will be - created: /dev/ttyUSBx (x is usually '0'). - -2. Force STM32F412CG to enter in Bootloader mode - - - Connect BOOT0 to 1V8 (link P2.1 to P3.30) - - Press and release the RST button - -3. Use stm32flash utility to flash the ArgonKey: - -.. code-block:: console - - $ stm32flash -w zephyr.bin -v -g 0x08000000 /dev/ttyUSB0 - -See References section for more info on `stm32flash`_. - -Using SWD debugger: -------------------- - -Select a commercial JTAG/SWD h/w tool and connect it to ArgonKey P4 connector. - -The ArgonKey has been tested using the `ST-LINK/V2`_ tool. Once that the tool -is connected to the PC through USB, it presents itself as a USB composite -device with mass storage capability. The device can be then mounted in linux -and the f/w can be actually copied there and will be automatically flashed by -the ST-LINK onto the ArgonKey. - -Example: - -.. code-block:: console - - $ mount /dev/sdb /mnt - $ cp zephyr.bin /mnt - $ umount /mnt - -Debugging -========= - -References -********** - -.. target-notes:: - -.. _ARGONKEY website: - https://www.st.com/en/evaluation-tools/steval-mki187v1.html - -.. _AN2606: - https://www.st.com/resource/en/application_note/cd00167594.pdf - -.. _stm32flash: - https://sourceforge.net/p/stm32flash/wiki/Home/ - -.. _ST-LINK/V2: - https://www.st.com/en/development-tools/st-link-v2.html - -.. _TTL-232RG: - http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232RG_CABLES.pdf diff --git a/boards/arm/96b_avenger96/Kconfig.board b/boards/arm/96b_avenger96/Kconfig.board deleted file mode 100644 index 78012ba940c..00000000000 --- a/boards/arm/96b_avenger96/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards Avenger96 board configuration - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_AVENGER96 - bool "96Boards Avenger96 Board" - depends on SOC_STM32MP15_M4 diff --git a/boards/arm/96b_avenger96/Kconfig.defconfig b/boards/arm/96b_avenger96/Kconfig.defconfig deleted file mode 100644 index b5cf5e03d49..00000000000 --- a/boards/arm/96b_avenger96/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# 96Boards Avenger96 board configuration - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_AVENGER96 - -config BOARD - default "96b_avenger96" - -endif # BOARD_96B_AVENGER96 diff --git a/boards/arm/96b_avenger96/doc/index.rst b/boards/arm/96b_avenger96/doc/index.rst deleted file mode 100644 index de7e1393182..00000000000 --- a/boards/arm/96b_avenger96/doc/index.rst +++ /dev/null @@ -1,279 +0,0 @@ -.. _96b_avenger96: - -96Boards Avenger96 -################## - -Overview -******** - -96Boards Avenger96 board is based on ST Microelectronics STM32MP157A -multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4 -core. Zephyr OS is ported to run on the Cortex®-M4 core. - -- Board features: - - - PMIC: STPMIC1A - - RAM: 1024 Mbyte @ 533MHz - - Storage: - - - eMMC: v4.51: 8 Gbyte - - QSPI: 2Mbyte - - EEPROM: 128 byte - - microSD Socket: UHS-1 v3.01 - - Ethernet: 10/100/1000 Mbit/s, IEEE 802.3 Compliant - - Wireless: - - - WiFi: 5 GHz & 2.4GHz IEEE 802.11a/b/g/n/ac - - Bluetooth: v4.2 (BR/EDR/BLE) - - USB: - - - Host - 2x type A, 2.0 high-speed - - OTG: - 1x type micro-AB, 2.0 high-speed - - HDMI: WXGA (1366x768)@ 60 fps, HDMI 1.4 - - Connectors: - - - 40-Pin Low Speed Header - - 60-Pin High Speed Header - - LEDs: - - - 4x Green user LEDs - - 1x Blue Bluetooth LED - - 1x Yellow WiFi LED - - 1x Red power supply LED - -.. image:: img/96b_avenger96.jpg - :align: center - :alt: 96Boards Avenger96 - -More information about the board can be found at the -`96Boards website`_. - -Hardware -******** - -The STM32MP157A SoC provides the following hardware capabilities: - -- Core: - - - 32-bit dual-core Arm® Cortex®-A7 - - - L1 32-Kbyte I / 32-Kbyte D for each core - - 256-Kbyte unified level 2 cache - - Arm® NEON™ - - - 32-bit Arm® Cortex®-M4 with FPU/MPU - - - Up to 209 MHz (Up to 703 CoreMark®) - -- Memories: - - - External DDR memory up to 1 Gbyte. - - 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM + - 64 KB of AHB SRAM in backup domain. - - Dual mode Quad-SPI memory interface - - Flexible external memory controller with up to 16-bit data bus - -- Clock management: - - - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz - LSI oscillator - - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator - - 6 × PLLs with fractional mode - -- General-purpose input/outputs: - - - Up to 176 I/O ports with interrupt capability - -- Interconnect matrix - -- 3 DMA controllers - -- Communication peripherals: - - - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus) - - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) - - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy) - - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx) - - SPDIF Rx with 4 inputs - - HDMI-CEC interface - - MDIO Slave interface - - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO) - - 2 × CAN controllers supporting CAN FD protocol, TTCAN capability - - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously - - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI) - - 8- to 14-bit camera interface up to 140 Mbyte/s - - 6 analog peripherals - - 2 × ADCs with 16-bit max. resolution. - - 1 × temperature sensor - - 2 × 12-bit D/A converters (1 MHz) - - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6 - filters - - Internal or external ADC/DAC reference VREF+ - -- Graphics: - - - 3D GPU: Vivante® - OpenGL® ES 2.0 - - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps - - MIPI® DSI 2 data lanes up to 1 GHz each - -- Timers: - - - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature - (incremental) encoder input - - 2 × 16-bit advanced motor control timers - - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM) - - 5 × 16-bit low-power timers - - RTC with sub-second accuracy and hardware calendar - - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor) - - 1 × SysTick Cortex®-M4 timer - -- Hardware acceleration: - - - HASH (MD5, SHA-1, SHA224, SHA256), HMAC - - 2 × true random number generator (3 oscillators each) - - 2 × CRC calculation unit - -- Debug mode: - - - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces - - 8-Kbyte embedded trace buffer - - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user - -More information about STM32P157A can be found here: - -- `STM32MP157A on www.st.com`_ -- `STM32MP157A reference manual`_ - -Supported Features -================== - -The Zephyr 96b_avenger96 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/96b_avenger96/96b_avenger96_defconfig`` - - -Connections and IOs -=================== - -96Boards Avenger96 Board schematic is available here: -`Avenger96 board schematics`_. - - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_7 TX/RX/RTS/CTS : PE8/PE7/PE9/PE10 (UART console) -- UART_4 TX/RX : PD1/PB2 - -System Clock ------------- - -The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value -must match the configured mlhclk_ck frequency. - -Serial Port ------------ - -96Boards Avenger96 board has 3 U(S)ARTs. The Zephyr console output is assigned -by default to the RAM console to be dumped by the Linux Remoteproc Framework -on Cortex®-A7 core. Alternatively, Zephyr console output can be assigned to -UART7 which is disabled by default. UART console can be enabled through -board's devicetree and 96b_avenger96_defconfig board file (or prj.conf -project files), and will disable existing RAM console output. Default UART -console settings are 115200 8N1. - -Programming and Debugging -************************* - -The STM32MP157A doesn't have QSPI flash for the Cortex®-M4 and it needs to be -started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the -Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset. -The Cortex®-A7 can perform these steps at bootloader level or after the Linux -system has booted. - -The Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at -address 0x00000000 (RETRAM), the vector table should be loaded at this address -These are the memory mappings for Cortex®-A7 and Cortex®-M4: - -+------------+-----------------------+------------------------+----------------+ -| Region | Cortex®-A7 | Cortex®-M4 | Size | -+============+=======================+========================+================+ -| RETRAM | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF | 64KB | -+------------+-----------------------+------------------------+----------------+ -| MCUSRAM | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF | 384KB | -+------------+-----------------------+------------------------+----------------+ -| DDR | 0xC0000000-0xFFFFFFFF | | up to 1 GB | -+------------+-----------------------+------------------------+----------------+ - - -Refer to `stm32mp157 boot Cortex-M4 firmware`_ wiki page for instruction -to load and start the Cortex-M4 firmware. - -Debugging -========= - -You can debug an application using OpenOCD and GDB. The Solution proposed below -is based on the Linux STM32MP1 SDK OpenOCD and is available only for a Linux -environment. The firmware must first be loaded by the Cortex®-A7. Developer -then attaches the debugger to the running Zephyr using OpenOCD. - -Prerequisite ------------- -install `stm32mp1 developer package`_. - -1) start OpenOCD in a dedicated terminal - - - Start up the sdk environment:: - - source /environment-setup-cortexa7hf-neon-vfpv4-openstlinux_weston-linux-gnueabi - - - Start OpenOCD:: - - ${OECORE_NATIVE_SYSROOT}/usr/bin/openocd -s ${OECORE_NATIVE_SYSROOT}/usr/share/openocd/scripts -f board/stm32mp15x_ev1_jlink_jtag.cfg - -2) run gdb in Zephyr environment - - .. code-block:: console - - # On Linux - cd $ZEPHYR_BASE/samples/hello_world - mkdir -p build && cd build - - # Use cmake to configure a Ninja-based build system: - cmake -GNinja -DBOARD=96b_avenger96 .. - - # Now run ninja on the generated build system: - ninja debug - -.. _96Boards website: - https://www.96boards.org/product/avenger96/ - -.. _STM32MP157A on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp157/stm32mp157a.html - -.. _STM32MP157A reference manual: - https://www.st.com/resource/en/reference_manual/DM00327659.pdf - -.. _Avenger96 board schematics: - https://www.96boards.org/documentation/consumer/avenger96/hardware-docs/files/avenger96-schematics.pdf - -.. _stm32mp1 developer package: - https://wiki.st.com/stm32mpu/index.php/STM32MP1_Developer_Package#Installing_the_SDK - -.. _stm32mp157 boot Cortex-M4 firmware: - https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework diff --git a/boards/arm/96b_carbon/96b_carbon.yaml b/boards/arm/96b_carbon/96b_carbon.yaml deleted file mode 100644 index 3b465d9e676..00000000000 --- a/boards/arm/96b_carbon/96b_carbon.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: 96b_carbon -name: 96Boards Carbon -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio - - ble - - i2c - - counter - - spi - - usb_device -ram: 96 -flash: 512 -vendor: seeed diff --git a/boards/arm/96b_carbon/96b_carbon_defconfig b/boards/arm/96b_carbon/96b_carbon_defconfig deleted file mode 100644 index 92cb9c88b9d..00000000000 --- a/boards/arm/96b_carbon/96b_carbon_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/96b_carbon/Kconfig.board b/boards/arm/96b_carbon/Kconfig.board deleted file mode 100644 index fc9e1d5df41..00000000000 --- a/boards/arm/96b_carbon/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96boards Carbon STMF401RE board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_CARBON - bool "96Boards Carbon (STM32F401)" - depends on SOC_STM32F401XE diff --git a/boards/arm/96b_carbon/Kconfig.defconfig b/boards/arm/96b_carbon/Kconfig.defconfig deleted file mode 100644 index e7d7a1bd3f8..00000000000 --- a/boards/arm/96b_carbon/Kconfig.defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# 96boards Carbon board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_CARBON - -config BOARD - default "96b_carbon" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -endif # BT - -if NETWORKING - -# Re-create the NET_L2_BT dependencies here -config BT - default y - -config BT_PERIPHERAL - default BT - -config BT_CENTRAL - default BT - -config BT_SMP - default BT - -config BT_L2CAP_DYNAMIC_CHANNEL - default BT - -# BT is the only onboard network iface, so use it for IP networking -# if it's enabled - -config NET_L2_BT - depends on NET_IPV6 - default BT - -config NET_L2_BT_ZEP1656 - depends on NET_IPV6 - default BT - -endif # NETWORKING - -endif # BOARD_96B_CARBON diff --git a/boards/arm/96b_carbon/doc/index.rst b/boards/arm/96b_carbon/doc/index.rst deleted file mode 100644 index 7b63bb20de9..00000000000 --- a/boards/arm/96b_carbon/doc/index.rst +++ /dev/null @@ -1,384 +0,0 @@ -.. _96b_carbon_board: - -96Boards Carbon -############### - -Overview -******** - -The 96Boards is based on the STMicroelectronics STM32F401RET Cortex-M4 CPU and -also contains a nRF51822 chip connected over SPI for BLE connectivity. - -The 96Boards Carbon board is built with two chips: an STMicroelectronics -STM32F401RET Cortex-M4 CPU and an nRF51822 chip connected to -the Cortex-M4 CPU over SPI for Bluetooth LE connectivity. Even though -both chips exist on the same physical board, they must be programmed -separately: - -- The ``96b_carbon`` configuration is used when developing programs for - the main chip on the board, the STM32F401RET. Users will likely want to - write applications targeting this chip, using the ``96b_carbon`` - configuration, since it is connected to all of the breakout - I/O headers. - -- The ``96b_carbon_nrf51`` configuration should be used for programming - the secondary nRF51822 chip. Most users will likely not develop - applications for this chip, since Zephyr already provides a - sample application that can be flashed onto the nRF51822 - to provide Bluetooth functionality to applications on the main - STM32F401RET chip. - -For instructions on how to set up the nRF51822 to develop Bluetooth -applications, see :ref:`96b_carbon_nrf51_bluetooth`. - -After you have flashed your nRF51, you can perform basic validation -of this Bluetooth setup using the instructions -:ref:`below <96b_carbon_verify_bluetooth>`. - -.. figure:: img/96b_carbon.jpg - :align: center - :alt: 96Boards Carbon - - 96Boards Carbon - -Hardware -******** - -96Boards Carbon provides the following hardware components: - -- STM32F401RET6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 84 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 96 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 16 channels -- RTC -- Advanced-control Timer -- General Purpose Timers (7) -- Watchdog Timers (2) -- USART/UART (4) -- I2C (3) -- SPI (3) -- SDIO -- USB 2.0 OTG FS -- DMA Controller -- Bluetooth LE over SPI, provided by nRF51822 - -More information about STM32F401RE can be found here: - - `STM32F401RE on www.st.com`_ - - `STM32F401 reference manual`_ - -Supported Features -================== - -The Zephyr 96b_carbon board configuration supports the following hardware -features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ - -More details about the board can be found at `96Boards website`_. - -The default configuration can be found in the defconfig file: - - ``boards/arm/96b_carbon/96b_carbon_defconfig`` - -Connections and IOs -=================== - -LED ---- - -- LED1 / User1 LED = PD2 -- LED2 / User2 LED = PA15 -- LED3 / BT LED = PB5 -- LED4 / Power LED = VCC - -Push buttons ------------- - -- BUTTON = BOOT0 (SW1) -- BUTTON = RST - -External Connectors -------------------- - -Low Speed Header - -+--------+-------------+----------------------+ -| PIN # | Signal Name | STM32F401 Functions | -+========+=============+======================+ -| 1 | UART2_CTS | PA0 | -+--------+-------------+----------------------+ -| 3 | UART2_TX | PA2 | -+--------+-------------+----------------------+ -| 5 | UART2_RX | PA3 | -+--------+-------------+----------------------+ -| 7 | UART2_RTS | PA1 | -+--------+-------------+----------------------+ -| 9 | GND | GND | -+--------+-------------+----------------------+ -| 11 | USB5V | USB5V | -+--------+-------------+----------------------+ -| 13 | AIN12 | PC2 | -+--------+-------------+----------------------+ -| 15 | AIN14 | PC4 | -+--------+-------------+----------------------+ -| 17 | UART6_TX | PC6 | -+--------+-------------+----------------------+ -| 19 | GPIO | PC8 | -+--------+-------------+----------------------+ -| 21 | I2C1_SCL | PB6 | -+--------+-------------+----------------------+ -| 23 | I2C1_SCA | PB7 | -+--------+-------------+----------------------+ -| 25 | I2C2_SCA | PB3 | -+--------+-------------+----------------------+ -| 27 | I2C2_SCL | PB10 | -+--------+-------------+----------------------+ -| 29 | RST_BTN | RST_BTN | -+--------+-------------+----------------------+ - -+--------+-------------+----------------------+ -| PIN # | Signal Name | STM32F401 Functions | -+========+=============+======================+ -| 2 | SPI2_SS | PB12 | -+--------+-------------+----------------------+ -| 4 | SPI2_MOSI | PB15 | -+--------+-------------+----------------------+ -| 6 | SPI2_MISO | PB14 | -+--------+-------------+----------------------+ -| 8 | SPI2_SCK | PB13 | -+--------+-------------+----------------------+ -| 10 | GND | GND | -+--------+-------------+----------------------+ -| 12 | VCC2 | VCC2 | -+--------+-------------+----------------------+ -| 14 | AIN13 | PC3 | -+--------+-------------+----------------------+ -| 16 | AIN15 | PC5 | -+--------+-------------+----------------------+ -| 18 | UART6_RX | PC7 | -+--------+-------------+----------------------+ -| 20 | GPIO | PC9 | -+--------+-------------+----------------------+ -| 22 | I2C1_SCL | PB8 | -+--------+-------------+----------------------+ -| 24 | I2C1_SDA | PB9 | -+--------+-------------+----------------------+ -| 26 | AIN10 | PC0 | -+--------+-------------+----------------------+ -| 28 | AIN11 | PC1 | -+--------+-------------+----------------------+ -| 30 | NC | NC | -+--------+-------------+----------------------+ - -More detailed information about the connectors can be found in -`96Boards IE Specification`_. - -External Clock Sources ----------------------- - -STM32F4 has two external oscillators. The frequency of the slow clock is -32.768 kHz. The frequency of the main clock is 16 MHz. - -Serial Port ------------ - -96Boards Carbon board has up to 4 U(S)ARTs. The Zephyr console output is -assigned to USART1. Default settings are 115200 8N1. - -I2C ---- - -96Boards Carbon board has up to 2 I2Cs. The default I2C mapping for Zephyr is: - -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PB3 - -SPI ---- - -96Boards Carbon board has up to 2 SPIs. SPI1 is used for Bluetooth communication -over HCI. The default SPI mapping for Zephyr is: - -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 - -USB -=== - -96Boards Carbon board has a USB OTG dual-role device (DRD) controller that -supports both device and host functions through its mini "OTG" USB connector. -Only USB device functions are supported in Zephyr at the moment. - -- USB_DM : PA11 -- USB_DP : PA12 - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. The ROM bootloader -supports flashing via USB (DFU), UART, I2C and SPI. You can read more about -how to enable and use the ROM bootloader by checking the application -note `AN2606`_, page 109. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -Flashing an Application to 96Boards Carbon ------------------------------------------- - -Connect the micro-USB cable to the USB OTG Carbon port and to your computer. -The board should power ON. Force the board into DFU mode by keeping the BOOT0 -switch pressed while pressing and releasing the RST switch. - -Confirm that the board is in DFU mode: - -.. code-block:: console - - $ sudo dfu-util -l - dfu-util 0.8 - Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. - Copyright 2010-2014 Tormod Volden and Stefan Schmidt - This program is Free Software and has ABSOLUTELY NO WARRANTY - Please report bugs to dfu-util@lists.gnumonks.org - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", serial="3574364C3034" - Found Runtime: [05ac:8290] ver=0104, devnum=2, cfg=1, intf=5, alt=0, name="UNKNOWN", serial="UNKNOWN" - -You should see following confirmation on your Linux host: - -.. code-block:: console - - $ dmesg - usb 1-2.1: new full-speed USB device number 14 using xhci_hcd - usb 1-2.1: New USB device found, idVendor=0483, idProduct=df11 - usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 - usb 1-2.1: Product: STM32 BOOTLOADER - usb 1-2.1: Manufacturer: STMicroelectronics - usb 1-2.1: SerialNumber: 3574364C3034 - -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_carbon - :goals: build flash - -Connect the micro-USB cable to the USB UART (FTDI) port and to your computer. -Run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board 96Boards Carbon -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. -The ``-b`` option sets baud rate ignoring the value from config. - -Press the Reset button and you should see the following message in your -terminal: - -.. code-block:: console - - Hello World! arm - -.. _96b_carbon_verify_bluetooth: - -Verifying Bluetooth Functionality ---------------------------------- - -This section contains instructions for verifying basic Bluetooth -functionality on the board. For help on Zephyr applications -in general, see :ref:`build_an_application`. - -1. Flash the nRF51 with the hci_spi sample application as described in - :ref:`96b_carbon_nrf51_bluetooth`. - -#. Install the dfu-util flashing app, as described above. - -#. Build and flash the ``samples/bluetooth/ipsp`` application for - 96b_carbon. See the instructions above for how to put your board - into DFU mode if you haven't done this before: - - .. zephyr-app-commands:: - :zephyr-app: samples/bluetooth/ipsp - :board: 96b_carbon - :goals: build flash - -#. Refer to the instructions in :ref:`bluetooth-ipsp-sample` for how - to verify functionality. - -Congratulations! Your 96Boards Carbon now has Bluetooth -connectivity. Refer to :ref:`bluetooth` for additional information on -further Bluetooth application development. - -Debugging -========= - -The 96b_carbon can be debugged by installing a 100 mil (0.1 inch) header -into the header at the bottom right hand side of the board, and -attaching an SWD debugger to the 3V3 (3.3V), GND, CLK, DIO, and RST -pins on that header. Then apply power to the 96Boards Carbon via one -of its USB connectors. You can now attach your debugger to the -STM32F401RET using an SWD scan. - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _AN2606: - https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf - -.. _96Boards website: - http://www.96boards.org/documentation - -.. _STM32F401RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f401re.html - -.. _STM32F401 reference manual: - https://www.st.com/resource/en/reference_manual/dm00096844.pdf - -.. _96Boards IE Specification: - https://linaro.co/ie-specification diff --git a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.dts b/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.dts deleted file mode 100644 index f4cd9310023..00000000000 --- a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.dts +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2017 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "96b_carbon_nrf51-pinctrl.dtsi" - -/ { - model = "Seeed Studio Carbon nRF51 96board"; - compatible = "seeed,carbon_nrf51"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - aliases { - watchdog0 = &wdt0; - }; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_default>; - pinctrl-1 = <&i2c0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart0 { - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi1 { - compatible = "nordic,nrf-spis"; - status = "okay"; - def-char = <0x00>; - - pinctrl-0 = <&spi1_default>; - pinctrl-names = "default"; - bt-hci@0 { - compatible = "zephyr,bt-hci-spi-slave"; - reg = <0>; - irq-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; - }; -}; diff --git a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.yaml b/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.yaml deleted file mode 100644 index 5ae43e121c7..00000000000 --- a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: 96b_carbon_nrf51 -name: 96Boards Carbon (nRF51) -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - ble -vendor: seeed diff --git a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51_defconfig b/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51_defconfig deleted file mode 100644 index e53e9565e4a..00000000000 --- a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/96b_carbon_nrf51/Kconfig.board b/boards/arm/96b_carbon_nrf51/Kconfig.board deleted file mode 100644 index 71833ec87c8..00000000000 --- a/boards/arm/96b_carbon_nrf51/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards Carbon nRF51 board configuration - -# Copyright (c) 2016, 2017 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_CARBON_NRF51 - bool "96Boards Carbon (nRF51)" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/96b_carbon_nrf51/Kconfig.defconfig b/boards/arm/96b_carbon_nrf51/Kconfig.defconfig deleted file mode 100644 index 87875314cd3..00000000000 --- a/boards/arm/96b_carbon_nrf51/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# 96Boards Carbon nRF51 board default configuration - -# Copyright (c) 2016, 2017 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_CARBON_NRF51 - -config BOARD - default "96b_carbon_nrf51" - -config BT_CTLR - default BT - -endif # BOARD_96B_CARBON_NRF51 diff --git a/boards/arm/96b_carbon_nrf51/doc/index.rst b/boards/arm/96b_carbon_nrf51/doc/index.rst deleted file mode 100644 index 5a17733d35f..00000000000 --- a/boards/arm/96b_carbon_nrf51/doc/index.rst +++ /dev/null @@ -1,171 +0,0 @@ -.. _96b_carbon_nrf51_board: - -96Boards Carbon nRF51 -##################### - -Overview -******** - -This is the secondary nRF51822 chip on the 96Boards Carbon and provides -Bluetooth functionality to the main STM32F401RET chip via SPI. - -.. note:: - - If you're looking to reprogram the main STMicro part, see - :ref:`96b_carbon_board`. Users should not use this configuration - unless they want to reprogram the secondary chip which provides - Bluetooth connectivity. - - -Hardware -******** - -The 96Boards Carbon nRF51 has two external oscillators. The frequency -of the slow clock is 32.768 kHz. The frequency of the main clock is 16 -MHz. - -See :ref:`96b_carbon_board` for other general information about the -board; that configuration is for the same physical board, just a -different chip. - -Supported Features -================== - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| SPIS | on-chip | SPI slave | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/96b_carbon_nrf51/96b_carbon_nrf51_defconfig`` - -Connections and IOs -=================== - -SPI ---- - -96Boards Carbon nRF51 has one SPI, which for providing Bluetooth -communication. The default SPI mapping for Zephyr is: - -- SPI1_NSS : P0.25 -- SPI1_SCK : P0.07 -- SPI1_MISO : P0.30 -- SPI1_MOSI : P0.00 - -The SWD debug pins are broken out to an external header; all other -connected pins are to the main STM32F401RET chip. - -.. _96b_carbon_nrf51_programming: - -Programming and Debugging -************************* - -Flashing -======== - -The 96Boards Carbon nRF51 can be flashed using an external SWD -debugger, via the debug header labeled "BLE" on the board's -silkscreen. The header is not populated; 0.1" male header must be -soldered on first. - -.. figure:: img/96b_carbon_nrf51.jpg - :align: center - :alt: 96Boards Carbon nRF51 Debug - - 96Boards Carbon nRF51 Debug - -The following example assumes a Zephyr binary ``zephyr.elf`` will be -flashed to the board. - -It uses the `Black Magic Debug Probe`_ as an SWD programmer, which can -be connected to the BLE debug header using flying leads and its 20 Pin -JTAG Adapter Board Kit. When plugged into your host PC, the Black -Magic Debug Probe enumerates as a USB serial device as documented on -its `Getting started page`_. - -It also uses the GDB binary provided with the Zephyr SDK, -``arm-zephyr-eabi-gdb``. Other GDB binaries, such as the GDB from GCC -ARM Embedded, can be used as well. - -.. code-block:: console - - $ arm-zephyr-eabi-gdb -q zephyr.elf - (gdb) target extended-remote /dev/ttyACM0 - Remote debugging using /dev/ttyACM0 - (gdb) monitor swdp_scan - Target voltage: 3.3V - Available Targets: - No. Att Driver - 1 nRF51 - (gdb) attach 1 - Attaching to Remote target - 0xabcdef12 in ?? () - (gdb) load - -Debugging -========= - -After you've flashed the chip, you can keep debugging using the same -GDB instance. To reattach, just follow the same steps above, but don't -run "load". You can then debug as usual with GDB. In particular, type -"run" at the GDB prompt to restart the program you've flashed. - -As an aid to debugging, this board configuration directs a console -output to a currently unused pin connected to the STM32F401RET. Users -who are experienced in electronics rework can remove a resistor (R22) -on the board and attach a wire to the nRF51822's UART output. - -.. _96b_carbon_nrf51_bluetooth: - -Providing Bluetooth to 96b_carbon -********************************* - -This 96b_carbon_nrf51 Zephyr configuration can be used to provide -Bluetooth functionality from the secondary nRF51822 chip to the -primary STM32F401RE chip on the :ref:`96b_carbon_board`. - -To do this, build the ``samples/bluetooth/hci_spi/`` application -provided with Zephyr with ``BOARD=96b_carbon_nrf51``, then flash it to -the nRF51822 chip using the instructions :ref:`above -<96b_carbon_nrf51_programming>`. (For instructions on how to build a -Zephyr application, see :ref:`build_an_application`.) - -.. warning:: - - Be sure to flash the hci_spi application to the nRF51822 chip and - not to the main STM32F401RET chip. While both chips are supported - by Zephyr, the hci_spi application providing Bluetooth support will - only run on the nRF51822 chip. - -References -********** - -- `Board documentation from 96Boards`_ -- `nRF51822 information from Nordic Semiconductor`_ - -.. _Black Magic Debug Probe: - https://github.com/blacksphere/blackmagic/wiki - -.. _Getting started page: - https://github.com/blacksphere/blackmagic/wiki/Getting-Started - -.. _Board documentation from 96Boards: - http://www.96boards.org/product/carbon/ - -.. _nRF51822 information from Nordic Semiconductor: - https://www.nordicsemi.com/eng/Products/Bluetooth-low-energy/nRF51822 diff --git a/boards/arm/96b_meerkat96/96b_meerkat96.yaml b/boards/arm/96b_meerkat96/96b_meerkat96.yaml deleted file mode 100644 index b06b2ef5268..00000000000 --- a/boards/arm/96b_meerkat96/96b_meerkat96.yaml +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (c) 2019, Linaro Ltd. -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: 96b_meerkat96 -name: 96Boards Meerkat96 -type: mcu -arch: arm -ram: 32 -flash: 32 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio - - shell -testing: - ignore_tags: - - net - - bluetooth -vendor: novtech diff --git a/boards/arm/96b_meerkat96/96b_meerkat96_defconfig b/boards/arm/96b_meerkat96/96b_meerkat96_defconfig deleted file mode 100644 index 0bed95b7b32..00000000000 --- a/boards/arm/96b_meerkat96/96b_meerkat96_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (c) 2019, Linaro Ltd. -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX7_M4=y -CONFIG_SOC_MCIMX7_M4=y -CONFIG_BOARD_96B_MEERKAT96=y - -# enable uart driver -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# pinctrl -CONFIG_PINCTRL=y - -CONFIG_XIP=y diff --git a/boards/arm/96b_meerkat96/Kconfig.board b/boards/arm/96b_meerkat96/Kconfig.board deleted file mode 100644 index 85c6c55a322..00000000000 --- a/boards/arm/96b_meerkat96/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# 96Boards Meerkat96 board - -# Copyright (c) 2019, Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_MEERKAT96 - bool "96Boards Meerkat96 board" - depends on SOC_SERIES_IMX7_M4 - select SOC_PART_NUMBER_MCIMX7D5EVM10SC diff --git a/boards/arm/96b_meerkat96/Kconfig.defconfig b/boards/arm/96b_meerkat96/Kconfig.defconfig deleted file mode 100644 index 7e758a53fa3..00000000000 --- a/boards/arm/96b_meerkat96/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# 96Boards Meerkat96 board - -# Copyright (c) 2019, Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_MEERKAT96 - -config BOARD - default "96b_meerkat96" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_96B_MEERKAT96 diff --git a/boards/arm/96b_meerkat96/doc/index.rst b/boards/arm/96b_meerkat96/doc/index.rst deleted file mode 100644 index d060076842c..00000000000 --- a/boards/arm/96b_meerkat96/doc/index.rst +++ /dev/null @@ -1,325 +0,0 @@ -.. _96b_meerkat96: - -96Boards Meerkat96 -################## - -Overview -******** - -96Boards Meerkat96 board is based on NXP i.MX7 Hybrid multi-core processor, -composed of a dual Cortex®-A7 and a single Cortex®-M4 core. -Zephyr OS is ported to run on the Cortex®-M4 core. - -- Board features: - - - RAM: 512 Mbyte - - Storage: - - - microSD Socket - - Wireless: - - - WiFi: 2.4GHz IEEE 802.11b/g/n - - Bluetooth: v4.1 (BR/EDR) - - USB: - - - Host - 2x type A - - OTG: - 1x type micro-B - - HDMI - - Connectors: - - - 40-Pin Low Speed Header - - 60-Pin High Speed Header - - LEDs: - - - 4x Green user LEDs - - 1x Blue Bluetooth LED - - 1x Yellow WiFi LED - -.. image:: img/96b_meerkat96.jpg - :align: center - :alt: 96Boards Meerkat96 - -More information about the board can be found at the -`96Boards website`_. - -Hardware -******** - -The i.MX7 SoC provides the following hardware capabilities: - -- Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core - -- Memory - - - External DDR memory up to 1 Gbyte - - Internal RAM -> A7: 256KB SRAM - - Internal RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) - -- Display - - - RGB 1920x1080x24bpp - - 4-wire Resistive touch - -- Multimedia - - - 1x Camera Parallel Interface - - 1x Analog Audio Line in (Stereo) - - 1x Analog Audio Mic in (Mono) - - 1x Analog Audio Headphone out (Stereo) - -- Connectivity - - - USB 2.0 OTG (High Speed) - - USB 2.0 host (High Speed) - - 10/100 Mbit/s Ethernet PHY - - 4x I2C - - 4x SPI - - 7x UART - - 1x IrDA - - 20x PWM - - Up to 125 GPIO - - 4x Analog Input (12 Bit) - - 2x SDIO/SD/MMC (8 Bit) - - 2x CAN - -More information about the i.MX7 SoC can be found here: - -- `i.MX 7 Series Website`_ -- `i.MX 7 Dual Datasheet`_ -- `i.MX 7 Dual Reference Manual`_ - -Supported Features -================== - -The Zephyr 96b_meerkat96 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/96b_meerkat96/96b_meerkat96_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -96Boards Meerkat96 board was tested with the following pinmux controller -configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART_1 RXD | UART1_TXD | UART Console | -+---------------+-----------------+---------------------------+ -| UART_1 TXD | UART1_RXD | UART Console | -+---------------+-----------------+---------------------------+ -| LED_R1 | GPIO1_IO04 | LED0 | -+---------------+-----------------+---------------------------+ -| LED_R2 | GPIO1_IO05 | LED1 | -+---------------+-----------------+---------------------------+ -| LED_R3 | GPIO1_IO06 | LED2 | -+---------------+-----------------+---------------------------+ -| LED_R4 | GPIO1_IO07 | LED3 | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 200 MHz clock speed. - -Serial Port -=========== - -The iMX7D SoC has seven UARTs. UART_1 is configured for the console and -the remaining are not used/tested. - -Programming and Debugging -************************* - -The 96Boards Meerkat96 board doesn't have QSPI flash for the M4 and it needs -to be started by the A7 core. The A7 core is responsible to load the M4 binary -application into the RAM, put the M4 in reset, set the M4 Program Counter and -Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at -bootloader level or after the Linux system has booted. - -The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: - -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=======================+========================+=======================+======================+ -| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 7 Dual Reference Manual`_ (section 2.1.2 and 2.1.3), and the -`Toradex Wiki`_. - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/96b_meerkat96/96b_meerkat96.dts`` -with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. -The available configurations are: - -.. code-block:: none - - "zephyr,flash" - - &ddr_code - - &tcml_code - - &ocram_code - - &ocram_s_code - - &ocram_pxp_code - - &ocram_epdc_code - - "zephyr,sram" - - &ddr_sys - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - - &ocram_pxp_sys - - &ocram_epdc_sys - - -Below you will find the instructions to load and run Zephyr on M4 from -A7 using u-boot. - -Copy the compiled zephyr.bin to the first FAT partition of the SD card and -plug into the board. Power it up and stop the u-boot execution. -Set the u-boot environment variables and run the zephyr.bin from the -appropriated memory configured in the Zephyr compilation: - -.. code-block:: console - - setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' - # TCML - setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' - setenv bootm4tcml 'run m4tcml && run bootm4' - run bootm4tcml - # TCMU - setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' - setenv bootm4tcmu 'run m4tcmu && run bootm4' - run bootm4tcmu - # OCRAM - setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' - setenv bootm4ocram 'run m4ocram && run bootm4' - run bootm4ocram - # OCRAM_S - setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' - setenv bootm4ocrams 'run m4ocrams && run bootm4' - run bootm4ocrams - # DDR - setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' - setenv bootm4ddr 'run m4ddr && run bootm4' - run bootm4ddr - -Debugging -========= - -96Boards Meerkat96 board can be debugged by connecting an external JLink -JTAG debugger to the J4 debug connector. Then download and install -`J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. - -To run Zephyr Binary using J-Link create the following script in order to -get the Program Counter and Stack Pointer from zephyr.bin. - -get-pc-sp.sh: -.. code-block:: console - - #!/bin/sh - - firmware=$1 - - pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') - sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') - - echo pc=$pc - echo sp=$sp - - -Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` -.. code-block:: console - - pc=00900f01 - sp=00905020 - -Plug in the J-Link into the board and PC and run the J-Link command line tool: - -.. code-block:: console - - /usr/bin/JLinkExe -device Cortex-M4 -if JTAG -speed 4000 -autoconnect 1 -jtagconf -1,-1 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript - -The following steps are necessary to run the zephyr.bin: - -1. Put the M4 core in reset -2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) -3. Set PC (Program Counter) -4. Set SP (Stack Pointer) -5. Get the M4 core out of reset - -Issue the following commands inside J-Link commander: - -.. code-block:: console - - w4 0x3039000C 0xAC - loadfile zephyr.bin,0x00900000 - w4 0x00180000 00900f01 - w4 0x00180004 00905020 - w4 0x3039000C 0xAA - -With these mechanisms, applications for the ``96b_meerkat96`` board -configuration can be built and debugged in the usual way (see -:ref:`build_an_application` and :ref:`application_run` for more details). - -References -========== - -- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ -- `J-Link iMX7D Instructions`_ - -.. _96Boards website: - https://www.96boards.org/product/imx7-96/ - -.. _i.MX 7 Series Website: - https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 - -.. _i.MX 7 Dual Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf - -.. _i.MX 7 Dual Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX7DRM - -.. _J-Link Tools: - https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack - -.. _NXP iMX7D Connect CortexM4.JLinkScript: - https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript - -.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: - https://www.nxp.com/docs/en/application-note/AN5317.pdf - -.. _J-Link iMX7D Instructions: - https://wiki.segger.com/IMX7D - -.. _Toradex Wiki: - https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/96b_neonkey/Kconfig.board b/boards/arm/96b_neonkey/Kconfig.board deleted file mode 100644 index 2246b448ec9..00000000000 --- a/boards/arm/96b_neonkey/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards Neonkey Board Configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_NEONKEY - bool "96Boards Neonkey" - depends on SOC_STM32F411XE diff --git a/boards/arm/96b_neonkey/Kconfig.defconfig b/boards/arm/96b_neonkey/Kconfig.defconfig deleted file mode 100644 index 54371886f73..00000000000 --- a/boards/arm/96b_neonkey/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# 96Boards Neonkey Board Configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_NEONKEY - -config BOARD - default "96b_neonkey" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_96B_NEONKEY diff --git a/boards/arm/96b_neonkey/doc/index.rst b/boards/arm/96b_neonkey/doc/index.rst deleted file mode 100644 index 8f0311259e1..00000000000 --- a/boards/arm/96b_neonkey/doc/index.rst +++ /dev/null @@ -1,233 +0,0 @@ -.. _96b_neonkey: - -96Boards Neonkey -################ - -Overview -******** - -96Boards Neonkey board is based on the STMicroelectronics STM32F411CE -Cortex M4 CPU. - -.. figure:: img/96b_neonkey.jpg - :align: center - :alt: 96Boards Neonkey - - 96Boards Neonkey - -This board acts as a sensor hub platform for all 96Boards compliant -family products. It can also be used as a standalone board. - -Hardware -******** - -96Boards Neonkey provides the following hardware components: - -- STM32F411CE in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 84 MHz max CPU frequency -- 1.8V work voltage -- 512 KB Flash -- 128 KB SRAM -- On board sensors: - - - Temperature/Humidity: SI7034-A10 - - Pressure: BMP280 - - ALS/Proximity: RPR-0521RS - - Geomagnetic: BMM150 - - Accelerometer/Gyroscope: BMI160 - - AMR Hall sensor: MRMS501A - - Microphone: SPK0415HM4H-B - -- 4 User LEDs -- 15 General purpose LEDs -- GPIO with external interrupt capability -- I2C (3) -- SPI (1) -- I2S (1) - -Supported Features -================== - -The Zephyr 96b_neonkey board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ - -More details about the board can be found at `96Boards website`_. - -The default board configuration can be found in the defconfig file: - - ``boards/arm/96b_neonkey/96b_neonkey_defconfig`` - -Connections and IOs -=================== - -LED ---- - -- LED1 / User1 LED = PB12 -- LED2 / User2 LED = PB13 -- LED3 / User3 LED = PB14 -- LED4 / User4 LED = PB15 - -Push buttons ------------- - -- BUTTON = RST (SW1) -- BUTTON = USR (SW2) - -System Clock -============ - -96Boards Neonkey can be driven by an internal oscillator as well as the main -PLL clock. By default System clock is sourced by PLL clock at 84MHz, driven -by internal oscillator. - -Serial Port -=========== - -On 96Boards Neonkey Zephyr console output is assigned to USART1. -Default settings are 115200 8N1. - -I2C ---- - -96Boards Neonkey board has up to 3 I2Cs. The default I2C mapping for Zephyr is: - -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PB3 -- I2C3_SCL : PA8 -- I2C3_SCL : PB4 - -SPI ---- - -96Boards Neonkey board has one SPI. The default SPI mapping for Zephyr is: - -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 - -Programming and Debugging -************************* - -Building -======== - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_neonkey - :goals: build - -Flashing -======== - -96Boards Neonkey can be flashed by two methods, one using the ROM -bootloader and another using the SWD debug port (which requires additional -hardware). - -Using ROM bootloader: ---------------------- - -ROM bootloader can be triggered by the following pattern: - -1. Connect BOOT0 to VDD (link JTAG pins 1 and 5 on P4 header) -2. Press and hold the USR button -3. Press and release the RST button - -More detailed information on activating the ROM bootloader can be found in -Chapter 29 of Application note `AN2606`_. The ROM bootloader supports flashing -via UART, I2C and SPI protocols. - -For flashing, `stm32flash`_ command line utility can be used. The following -command will flash the ``zephyr.bin`` binary to the Neonkey board using UART -and starts its execution: - -.. code-block:: console - - $ stm32flash -w zephyr.bin -v -g 0x08000000 /dev/ttyS0 - -.. note:: - The above command assumes that Neonkey board is connected to - serial port ``/dev/ttyS0``. - -Using SWD debugger: -------------------- - -For flashing via SWD debug port, 0.1" male header must be soldered at P4 -header available at the bottom of the board, near RST button. - -Use the `Black Magic Debug Probe`_ as an SWD programmer, which can -be connected to the P4 header using its flying leads and its 20 Pin -JTAG Adapter Board Kit. When plugged into your host PC, the Black -Magic Debug Probe enumerates as a USB serial device as documented on -its `Getting started page`_. - -It also uses the GDB binary provided with the Zephyr SDK, -``arm-zephyr-eabi-gdb``. Other GDB binaries, such as the GDB from GCC -ARM Embedded, can be used as well. - -.. code-block:: console - - $ arm-zephyr-eabi-gdb -q zephyr.elf - (gdb) target extended-remote /dev/ttyACM0 - Remote debugging using /dev/ttyACM0 - (gdb) monitor swdp_scan - Target voltage: 1.8V - Available Targets: - No. Att Driver - 1 STM32F4xx - (gdb) attach 1 - Attaching to Remote target - 0x080005d0 in ?? () - (gdb) load - -Debugging -========= - -After flashing 96Boards Neonkey, it can be debugged using the same -GDB instance. To reattach, just follow the same steps above, till -"attach 1". You can then debug as usual with GDB. In particular, type -"run" at the GDB prompt to restart the program you've flashed. - -References -********** - -.. _96Boards website: - https://www.96boards.org/product/neonkey/ - -.. _AN2606: - https://www.st.com/resource/en/application_note/cd00167594.pdf - -.. _stm32flash: - https://sourceforge.net/p/stm32flash/wiki/Home/ - -.. _Black Magic Debug Probe: - https://github.com/blacksphere/blackmagic/wiki - -.. _Getting started page: - https://github.com/blacksphere/blackmagic/wiki/Getting-Started diff --git a/boards/arm/96b_nitrogen/Kconfig b/boards/arm/96b_nitrogen/Kconfig deleted file mode 100644 index acaec810c79..00000000000 --- a/boards/arm/96b_nitrogen/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards NITROGEN board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_NITROGEN - -endif # BOARD_96B_NITROGEN diff --git a/boards/arm/96b_nitrogen/Kconfig.board b/boards/arm/96b_nitrogen/Kconfig.board deleted file mode 100644 index a771ff27019..00000000000 --- a/boards/arm/96b_nitrogen/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards NITROGEN board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_NITROGEN - bool "96Boards Nitrogen" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/96b_nitrogen/Kconfig.defconfig b/boards/arm/96b_nitrogen/Kconfig.defconfig deleted file mode 100644 index 00ff29cb2bc..00000000000 --- a/boards/arm/96b_nitrogen/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# 96Boards NITROGEN board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_NITROGEN - -config BOARD - default "96b_nitrogen" - -config BT_CTLR - default BT - -endif # BOARD_96B_NITROGEN diff --git a/boards/arm/96b_nitrogen/doc/index.rst b/boards/arm/96b_nitrogen/doc/index.rst deleted file mode 100644 index ea971f093a8..00000000000 --- a/boards/arm/96b_nitrogen/doc/index.rst +++ /dev/null @@ -1,330 +0,0 @@ -.. _96b_nitrogen_board: - -96Boards Nitrogen -################# - -Overview -******** - -The 96Boards Nitrogen hardware provides support for the Nordic Semiconductor -nRF52832 ARM Cortex-M4F CPU. - -.. figure:: img/96b_nitrogen.jpg - :align: center - :alt: 96Boards Nitrogen - - 96Boards Nitrogen - -More information about the board can be found at the `seeed BLE Nitrogen`_ -website. The `Nordic Semiconductor Infocenter`_ contains the processor's -information and the datasheet. - -Hardware -******** - -96Boards Nitrogen provides the following hardware components: - -- nRF52832 microcontroller with 512kB Flash, 64kB RAM -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- Bluetooth LE -- NFC -- LPC11U35 on board SWD debugger - - - SWD debugger firmware - - USB to UART - - Drag and Drop firmware upgrade - -- 7 LEDs - - - USR1, BT, PWR, CDC, DAP, MSD, Battery charge - -- SWD debug connectors - - - nRF52832 SWD connector - - nRF52832 Uart connector - -- On board chip antenna -- 1.8V work voltage -- 2x20pin 2.0mm pitch Low speed connector - -Supported Features -================== - -The Zephyr 96b_nitrogen board configuration supports the following hardware -features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| NVIC | on-chip | nested vectored interrupt controller | -+-----------+------------+--------------------------------------+ -| RTC | on-chip | system clock | -+-----------+------------+--------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+--------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+--------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+--------------------------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+--------------------------------------+ -| RTT | on-chip | console | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. -See `Nordic Semiconductor Infocenter`_ for a complete list of nRF52-based -board hardware features. - -The default configuration can be found in the defconfig file: - - ``boards/arm/96b_nitrogen/96b_nitrogen_defconfig`` - -Pin Mapping -=========== - -LED ---- - -- LED1 / User LED (green) = P0.29 -- LED2 / BT LED (blue) = P0.28 - -Push buttons ------------- - -- BUTTON = SW1 = P0.27 - -External Connectors -------------------- - -Low Speed Header - -+--------+-------------+----------------------+ -| PIN # | Signal Name | nRF52832 Functions | -+========+=============+======================+ -| 1 | GND | GND | -+--------+-------------+----------------------+ -| 3 | UART CTS | P.014 / TRACEDATA[3] | -+--------+-------------+----------------------+ -| 5 | UART TX | P0.13 | -+--------+-------------+----------------------+ -| 7 | UART RX | P0.15 / TRACEDATA[2] | -+--------+-------------+----------------------+ -| 9 | UART RTS | P0.12 | -+--------+-------------+----------------------+ -| 11 | UART TX | P0.13 | -+--------+-------------+----------------------+ -| 13 | UART RX | P0.15 / TRACEDATA[2] | -+--------+-------------+----------------------+ -| 15 | P0.22 | P0.22 | -+--------+-------------+----------------------+ -| 17 | P0.20 | P0.20 | -+--------+-------------+----------------------+ -| 19 | N/A | N/A | -+--------+-------------+----------------------+ -| 21 | N/A | N/A | -+--------+-------------+----------------------+ -| 23 | P0.02 | P0.02 | -+--------+-------------+----------------------+ -| 25 | P0.04 | P0.04 | -+--------+-------------+----------------------+ -| 27 | P0.06 | P0.06 | -+--------+-------------+----------------------+ -| 29 | P0.08 | P0.08 | -+--------+-------------+----------------------+ -| 31 | P0.16 | P0.16 | -+--------+-------------+----------------------+ -| 33 | P0.18 | P0.18 | -+--------+-------------+----------------------+ -| 35 | VCC | | -+--------+-------------+----------------------+ -| 37 | USB5V | | -+--------+-------------+----------------------+ -| 39 | GND | GND | -+--------+-------------+----------------------+ - -+--------+-------------+----------------------+ -| PIN # | Signal Name | nRF52832 Functions | -+========+=============+======================+ -| 2 | GND | GND | -+--------+-------------+----------------------+ -| 4 | PWR BTN | | -+--------+-------------+----------------------+ -| 6 | RST BTN | P0.21 / RESET | -+--------+-------------+----------------------+ -| 8 | P0.26 | P0.26 | -+--------+-------------+----------------------+ -| 10 | P0.25 | P0.25 | -+--------+-------------+----------------------+ -| 12 | P0.24 | P0.24 | -+--------+-------------+----------------------+ -| 14 | P0.23 | P0.23 | -+--------+-------------+----------------------+ -| 16 | N/A | N/A | -+--------+-------------+----------------------+ -| 18 | N/A | PC7 | -+--------+-------------+----------------------+ -| 20 | N/A | PC9 | -+--------+-------------+----------------------+ -| 22 | N/A | PB8 | -+--------+-------------+----------------------+ -| 24 | P0.03 | P0.03 | -+--------+-------------+----------------------+ -| 26 | P0.05 | P0.05 | -+--------+-------------+----------------------+ -| 28 | P0.07 | P0.07 | -+--------+-------------+----------------------+ -| 30 | P0.11 | P0.11 | -+--------+-------------+----------------------+ -| 32 | P0.17 | P0.17 | -+--------+-------------+----------------------+ -| 34 | P0.19 | P0.19 | -+--------+-------------+----------------------+ -| 36 | NC | | -+--------+-------------+----------------------+ -| 38 | NC | | -+--------+-------------+----------------------+ -| 40 | GND | GND | -+--------+-------------+----------------------+ - -More detailed information about the connectors can be found in -`96Boards IE Specification`_. - -System Clock -============ - -nRF52 has two external oscillators. The frequency of the slow clock is -32.768 kHz. The frequency of the main clock is 32 MHz. - -Serial Port ------------ - -96Boards Nitrogen has one UART, which is used as Zephyr console. -Default settings is 115200 8N1. - -I2C ---- - -96Boards Nitrogen has one I2C. The default I2C mapping for Zephyr is: - -- I2C0_SCL : P0.22 -- I2C0_SDA : P0.20 - -SPI ---- - -96Boards Nitrogen has one SPI. The default SPI mapping for Zephyr is: - -- SPI0_NSS : P0.24 -- SPI0_SCK : P0.26 -- SPI0_MISO : P0.25 -- SPI0_MOSI : P0.23 - -Flashing Zephyr onto 96Boards Nitrogen -************************************** - -The 96Boards Nitrogen board can be flashed via the `CMSIS DAP`_ interface, -which is provided by the micro USB interface to the LPC11U35 chip. - -Using the CMSIS-DAP interface, the board can be flashed via the USB storage -interface (drag-and-drop) and also via `pyOCD`_. - -To use ``pyOCD``, install the :ref:`pyocd-debug-host-tools` and make sure they -are in your search path. - -Common Errors -============= - -No connected boards -------------------- - -If you don't use sudo when invoking pyocd-flashtool, you might get any of the -following errors: - -.. code-block:: console - - No available boards are connected - -.. code-block:: console - - No connected boards - -.. code-block:: console - - Error: There is no board connected. - -To fix the permission issue, simply add the following udev rule for the -NXP LPC1768 interface: - -.. code-block:: console - - $ echo 'ATTR{idProduct}=="0204", ATTR{idVendor}=="0d28", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-cmsis-dap.rules - -Finally, unplug and plug the board again. - -ValueError: The device has no langid ------------------------------------- - -As described by `pyOCD issue 259`_, you might get the -:code:`ValueError: The device has no langid` error when not running -pyOCD as root (e.g. sudo). - -To fix the above error, add the udev rule shown in the previous section -and install a more recent version of pyOCD. - -Flashing an Application to 96Boards Nitrogen -============================================ - -Here is an example for the :ref:`hello_world` application. This -requires installing the :ref:`pyocd-debug-host-tools`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_nitrogen - :goals: build flash - -Run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board 96Boards Nitrogen -can be found. For example, under Linux, :code:`/dev/ttyACM0`. -The ``-b`` option sets baud rate ignoring the value from config. - -Press the Reset button and you should see the following message in your -terminal: - -.. code-block:: console - - Hello World! arm - -Debugging with GDB -================== - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. This also requires pyOCD. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_nitrogen - :maybe-skip-config: - :goals: debug - -.. _pyOCD: - https://github.com/mbedmicro/pyOCD - -.. _CMSIS DAP: - https://developer.mbed.org/handbook/CMSIS-DAP - -.. _Nordic Semiconductor Infocenter: - http://infocenter.nordicsemi.com/ - -.. _seeed BLE Nitrogen: - http://wiki.seeed.cc/BLE_Nitrogen/ - -.. _pyOCD issue 259: - https://github.com/mbedmicro/pyOCD/issues/259 - -.. _96Boards IE Specification: - https://linaro.co/ie-specification diff --git a/boards/arm/96b_stm32_sensor_mez/Kconfig.board b/boards/arm/96b_stm32_sensor_mez/Kconfig.board deleted file mode 100644 index 3d17d091ae4..00000000000 --- a/boards/arm/96b_stm32_sensor_mez/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards STM32 Sensor Mezzanine board configuration - -# Copyright (c) 2018 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_STM32_SENSOR_MEZ - bool "96Boards STM32 Sensor Mezzanine Board" - depends on SOC_STM32F446XX diff --git a/boards/arm/96b_stm32_sensor_mez/Kconfig.defconfig b/boards/arm/96b_stm32_sensor_mez/Kconfig.defconfig deleted file mode 100644 index bfe0f730222..00000000000 --- a/boards/arm/96b_stm32_sensor_mez/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# 96Boards STM32 Sensor Mezzanine board configuration - -# Copyright (c) 2018 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_STM32_SENSOR_MEZ - -config BOARD - default "96b_stm32_sensor_mez" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_96B_STM32_SENSOR_MEZ diff --git a/boards/arm/96b_stm32_sensor_mez/doc/index.rst b/boards/arm/96b_stm32_sensor_mez/doc/index.rst deleted file mode 100644 index 95d11d2bacc..00000000000 --- a/boards/arm/96b_stm32_sensor_mez/doc/index.rst +++ /dev/null @@ -1,248 +0,0 @@ -.. _96b_stm32_sensor_mez: - -96Boards STM32 Sensor Mezzanine -############################### - -Overview -******** - -96Boards STM32 Sensor Mezzanine is based on the ST Microelectronics -STM32F446VE Cortex M4 CPU. - -This board acts as a mezzanine platform for all 96Boards CE compliant -boards. It can also be used as a standalone board. - -.. figure:: img/96b_stm32_sensor_mez.jpg - :align: center - :alt: 96Boards STM32 Sensor Mezzanine - - 96Boards STM32 Sensor Mezzanine - -Hardware -******** - -96Boards STM32 Sensor Mezzanine provides the following hardware components: - -- STM32F446VE in LQFP100 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 180 MHz max CPU frequency -- 1.8V work voltage -- 512 KB Flash -- 128 KB SRAM -- On board sensors: - - - Temperature/Pressure: STMicro LPS22HB - - Accelerometer/Gyroscope: STMicro LSM6DS3H - - Magnetometer: STMicro LIS3MDL - - Microphone: STMicro MP34DT01 - -- 3User LEDs -- GPIO with external interrupt capability -- UART -- I2C (2) -- SPI (3) -- I2S (1) - -Supported Features -================== - -The Zephyr 96b_stm32_sensor_mez board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ - -The default board configuration can be found in the defconfig file: - - ``boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez_defconfig`` - -Connections and IOs -=================== - -LED ---- - -- LED1 / User1 LED = PD10 -- LED2 / User2 LED = PD11 -- LED3 / User3 LED = PD12 - -Push buttons ------------- - -- BUTTON = RST (BT1) -- BUTTON = USR (BT2) - -System Clock -============ - -96Boards STM32 Sensor Mezzanine can be driven by an internal oscillator as -well as the main PLL clock. In default board configuration, the 16MHz external -oscillator is used to drive the main PLL clock to generate a System Clock -(SYSCLK) at 84MHz. On the bus side, AHB/APB2 clocks runs at 84MHz, while APB1 -clock runs at 42MHz. - -Serial Port -=========== - -On 96Boards STM32 Sensor Mezzanine, Zephyr console output is assigned to UART4 -exposed via on-board Micro USB connector. Default settings are 115200 8N1. - -The default USART mappings for the remaining ones are: - -- USART1: Connected to AP via UART0 on the 96Boards Low-Speed Header. - - TX: PA9 - - RX: PA10 - -- USART2: Connected to D0(RX) and D1(TX) on the Arduino Header. - - TX: PD5 - - RX: PD6 - -- USART3: Broken out to Grove connector J10. - - TX: PD8 - - RX: PD9 - -I2C ---- - -96Boards STM32 Sensor Mezzanine board has up to 3 I2Cs. The default I2C -mapping is: - -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PC12 - -I2C2 goes to the Groove connectors and can be used to attach external sensors. - -SPI ---- -96Boards STM32 Sensor Mezzanine board has 3 SPIs. SPI1 is used in slave mode -as the communication bus with the AP. SPI2 is used in master mode to control -the LSM6DS3H sensor. SPI4 is broken out to Grove Connector J5. -The default SPI mapping is: - -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB9 -- SPI2_SCK : PD3 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 -- SPI4_NSS : PE11 -- SPI4_SCK : PE12 -- SPI4_MISO : PE13 -- SPI4_MOSI : PE14 - -PWM ---- -96Boards STM32 Sensor Mezzanine board exposes 6 PWM channels on the Arduino -connector. The default PWM mapping is: - -- PWM3_CH1 : PB4 : D9 -- PWM3_CH3 : PC8 : D3 -- PWM4_CH3 : PD14 : D6 -- PWM4_CH4 : PD15 : D5 -- PWM9_CH1 : PE5 : D12 -- PWM9_CH2 : PE6 : D11 - -I2S ---- - -96Boards STM32 Sensor Mezzanine board exposes 1 I2S port which is connected -to the on-board ST MP34DT01 DMIC. The default I2S mapping is: - -- I2S2_SD : PC1 -- I2S2_CK : PC7 - -Programming and Debugging -************************* - -Building -======== - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_stm32_sensor_mez - :goals: build - -Flashing -======== - -96Boards STM32 Sensor Mezzanine board includes an ST-LINK/V2-1 embedded -debug tool interface. This interface is supported by the openocd version -included in the Zephyr SDK. - -Flashing an application to 96Boards STM32 Sensor Mezzanine ----------------------------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your 96Boards STM32 Sensor Mezzanine -board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_stm32_sensor_mez - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! 96b_stm32_sensor_mez - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_stm32_sensor_mez - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _96Boards STM32 Sensor Mezzanine website: - https://www.96boards.org/documentation/mezzanine/stm32/ - -.. _STM32F446VE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f446ve.html - -.. _STM32F446 reference manual: - https://www.st.com/resource/en/reference_manual/dm00135183.pdf diff --git a/boards/arm/96b_wistrio/Kconfig.board b/boards/arm/96b_wistrio/Kconfig.board deleted file mode 100644 index ac527a671b7..00000000000 --- a/boards/arm/96b_wistrio/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96boards WisTrio board configuration - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_WISTRIO - bool "96boards WisTrio Development Board" - depends on SOC_STM32L151XBA diff --git a/boards/arm/96b_wistrio/Kconfig.defconfig b/boards/arm/96b_wistrio/Kconfig.defconfig deleted file mode 100644 index 0bb9b83220d..00000000000 --- a/boards/arm/96b_wistrio/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# 96boards WisTrio board configuration - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_WISTRIO - -config BOARD - default "96b_wistrio" - -config REGULATOR - default y if LORA - -endif # BOARD_96B_WISTRIO diff --git a/boards/arm/acn52832/Kconfig.board b/boards/arm/acn52832/Kconfig.board deleted file mode 100644 index 6e19e79560a..00000000000 --- a/boards/arm/acn52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# aconno acn52832 board configuration - -# Copyright (c) 2023 Sven Herrmann -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ACN52832 - bool "aconno ACN52832" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/acn52832/Kconfig.defconfig b/boards/arm/acn52832/Kconfig.defconfig deleted file mode 100644 index e389aadf6e7..00000000000 --- a/boards/arm/acn52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# aconno acn52832 board configuration - -# Copyright (c) 2023 Sven Herrmann -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACN52832 - -config BOARD - default "acn52832" - -config BT_CTLR - default BT - -endif # BOARD_ACN52832 diff --git a/boards/arm/acn52832/acn52832_defconfig b/boards/arm/acn52832/acn52832_defconfig deleted file mode 100644 index d35096cdd6e..00000000000 --- a/boards/arm/acn52832/acn52832_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_ACN52832=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus/CMakeLists.txt b/boards/arm/actinius_icarus/CMakeLists.txt deleted file mode 100644 index a747a3fdffa..00000000000 --- a/boards/arm/actinius_icarus/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2019-2022 Actinius -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/arm/actinius_icarus/Kconfig.board b/boards/arm/actinius_icarus/Kconfig.board deleted file mode 100644 index bdf4d8e2c36..00000000000 --- a/boards/arm/actinius_icarus/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Actinius Icarus board configuration - -# Copyright (c) 2019 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_ACTINIUS_ICARUS - bool "Actinius Icarus" - -config BOARD_ACTINIUS_ICARUS_NS - bool "Actinius Icarus Non-Secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/actinius_icarus/Kconfig.defconfig b/boards/arm/actinius_icarus/Kconfig.defconfig deleted file mode 100644 index 6994aac280d..00000000000 --- a/boards/arm/actinius_icarus/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Actinius Icarus board configuration - -# Copyright (c) 2019 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACTINIUS_ICARUS || BOARD_ACTINIUS_ICARUS_NS - -config BOARD - default "actinius_icarus" - -source "boards/common/actinius/Kconfig" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_ACTINIUS_ICARUS && TRUSTED_EXECUTION_SECURE - -if BOARD_ACTINIUS_ICARUS_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_ACTINIUS_ICARUS_NS - -endif # BOARD_ACTINIUS_ICARUS || BOARD_ACTINIUS_ICARUS_NS diff --git a/boards/arm/actinius_icarus/actinius_icarus.yaml b/boards/arm/actinius_icarus/actinius_icarus.yaml deleted file mode 100644 index d547560af6f..00000000000 --- a/boards/arm/actinius_icarus/actinius_icarus.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: actinius_icarus -name: Actinius Icarus -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 256 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter - - feather_serial - - feather_i2c - - feather_spi - - arduino_i2c - - arduino_spi -vendor: actinius diff --git a/boards/arm/actinius_icarus/actinius_icarus_1_4_0.overlay b/boards/arm/actinius_icarus/actinius_icarus_1_4_0.overlay deleted file mode 100644 index 07190f7553f..00000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_1_4_0.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - - #include "actinius_icarus_common_1_4_0.dtsi" diff --git a/boards/arm/actinius_icarus/actinius_icarus_2_0_0.overlay b/boards/arm/actinius_icarus/actinius_icarus_2_0_0.overlay deleted file mode 100644 index 79e7c3ff28d..00000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_2_0_0.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - - #include "actinius_icarus_common_2_0_0.dtsi" diff --git a/boards/arm/actinius_icarus/actinius_icarus_defconfig b/boards/arm/actinius_icarus/actinius_icarus_defconfig deleted file mode 100644 index 58d15739a95..00000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus/actinius_icarus_ns.yaml b/boards/arm/actinius_icarus/actinius_icarus_ns.yaml deleted file mode 100644 index 7fe1ea2ef47..00000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_ns.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: actinius_icarus_ns -name: Actinius Icarus Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter - - feather_serial - - feather_i2c - - feather_spi - - arduino_i2c - - arduino_spi -vendor: actinius diff --git a/boards/arm/actinius_icarus/actinius_icarus_ns_1_4_0.overlay b/boards/arm/actinius_icarus/actinius_icarus_ns_1_4_0.overlay deleted file mode 100644 index 07190f7553f..00000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_ns_1_4_0.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - - #include "actinius_icarus_common_1_4_0.dtsi" diff --git a/boards/arm/actinius_icarus/actinius_icarus_ns_2_0_0.overlay b/boards/arm/actinius_icarus/actinius_icarus_ns_2_0_0.overlay deleted file mode 100644 index 79e7c3ff28d..00000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_ns_2_0_0.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - - #include "actinius_icarus_common_2_0_0.dtsi" diff --git a/boards/arm/actinius_icarus/actinius_icarus_ns_defconfig b/boards/arm/actinius_icarus/actinius_icarus_ns_defconfig deleted file mode 100644 index e2e6e11584b..00000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus/doc/index.rst b/boards/arm/actinius_icarus/doc/index.rst deleted file mode 100644 index 7f040e6630e..00000000000 --- a/boards/arm/actinius_icarus/doc/index.rst +++ /dev/null @@ -1,238 +0,0 @@ -.. _actinius_icarus: - -Actinius Icarus -############### - -Overview -******** - -.. figure:: img/Icarus_front.jpg - :align: center - :alt: Icarus IoT Dev Board - - Icarus IoT Dev Board (nRF9160 Feather) - -The Icarus is a cost-effective cellular IoT board in Adafruit's Feather/FeatherWing -form factor. It is built around Nordic Semi's nRF9160 modem and combines -LTE-M, NB-IoT, GPS, accelerometer, USB, LiPo charger as well as -an eSIM and a nano SIM connector. - -The main uController is the Nordic Semiconductor nRF9160, with -ARM Cortex-M33F CPU, ARMv8-M Security Extension and the -following devices (provided directly by Nordic): - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -Hardware -******** - -The detailed information about the on-board hardware can be found at the `Icarus Product Website`_. - -.. figure:: img/Icarus_pinouts.jpg - :align: center - :alt: Icarus IoT Dev Board w/ Pinouts - - Icarus IoT Dev Board w/ Pinouts - -Pin description -=============== - -External Pins available to user: - -+------------+----------------------------+----------------------------------------------+------------------+ -| Icarus pin | Function | Description | Device-tree node | -+============+============================+==============================================+==================+ -| RST | Reset | Active low reset with internal pullup | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| 3.3V | Power output | Main 3.3 V supply | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| NC | - | Not connected | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| GND | Power output | Ground | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| 14 / A1 | GPIO / Analog in | nRF9160 P0.14 / AIN1 | gpio0 / adc_1 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 15 / A2 | GPIO / Analog in | nRF9160 P0.15 / AIN2 | gpio0 / adc_2 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 16 / A3 | GPIO / Analog in | nRF9160 P0.16 / AIN3 | gpio0 / adc_3 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 17 / A4 | GPIO / Analog in | nRF9160 P0.17 / AIN4 | gpio0 / adc_4 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 18 / A5 | GPIO / Analog in | nRF9160 P0.18 / AIN5 | gpio0 / adc_5 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 19 / A6 | GPIO / Analog in | nRF9160 P0.19 / AIN6 | gpio0 / adc_6 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 20 / SCK | GPIO / SPI pin | nRF9160 P0.20 / SPI SCK pin | gpio0 / spi3 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 21 / MOSI | GPIO / SPI pin | nRF9160 P0.21 / SPI MOSI pin | gpio0 / spi3 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 22 / MISO | GPIO / SPI pin | nRF9160 P0.22 / SPI MISO pin | gpio0 / spi3 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 23 / RX | GPIO / UART pin | nRF9160 P0.23 / UART RX pin | gpio0 / uart1 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 24 / TX | GPIO / UART pin | nRF9160 P0.24 / UART TX pin | gpio0 / uart1 | -+------------+----------------------------+----------------------------------------------+------------------+ -| VIN | Power input | Voltage input (maximum 10.2 V) | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| VBAT | Power input | Battery voltage input | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| EN | Power enable | Power enable pin (pull low to disable power) | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| USB | Power input | USB voltage input | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 4 | GPIO | nRF9160 P0.04 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 3 | GPIO | nRF9160 P0.03 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 2 | GPIO | nRF9160 P0.02 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 1 | GPIO | nRF9160 P0.01 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 0 | GPIO | nRF9160 P0.00 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 30 | GPIO | nRF9160 P0.30 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 31 | GPIO | nRF9160 P0.31 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| SCL | GPIO / I2C pin | nRF9160 P0.26 / I2C SCL pin | gpio0 / i2c2 | -+------------+----------------------------+----------------------------------------------+------------------+ -| SDA | GPIO / I2C pin | nRF9160 P0.27 / I2C SDA pin | gpio0 / i2c2 | -+------------+----------------------------+----------------------------------------------+------------------+ - -nRF9160 pins connected internally: - -+--------------+---------------------------------------+----------------------+ -| nRF9160 pin | Function | Device-tree node | -+==============+=======================================+======================+ -| P0.05 | User button | button0 | -+--------------+---------------------------------------+----------------------+ -| P0.10 | Red LED | led0 / pwm-led0 | -+--------------+---------------------------------------+----------------------+ -| P0.11 | Green LED | led1 / pwm-led1 | -+--------------+---------------------------------------+----------------------+ -| P0.12 | Blue LED | led2 / pwm-led2 | -+--------------+---------------------------------------+----------------------+ -| P0.28 | Accelerometer Interrupt 1 | lis2dh12-accel | -+--------------+---------------------------------------+----------------------+ -| P0.29 | Accelerometer Interrupt 2 | lis2dh12-accel | -+--------------+---------------------------------------+----------------------+ -| P0.08 | SIM select pin | gpio0 | -+--------------+---------------------------------------+----------------------+ -| P0.13 / AIN0 | Battery voltage measurement | adc_0 | -+--------------+---------------------------------------+----------------------+ -| P0.06 | USB - FTDI serial RX | uart0 | -+--------------+---------------------------------------+----------------------+ -| P0.09 | USB - FTDI serial TX | uart0 | -+--------------+---------------------------------------+----------------------+ -| P0.07 | USB - FTDI serial RTS | uart0 | -| | Charger enable pin (Icarus v2.0) | gpio0 (Icarus v2.0) | -+--------------+---------------------------------------+----------------------+ -| P0.25 | USB - FTDI serial CTS | uart0 | -| | FLASH memory SPI CS pin (Icarus v2.0) | gpio0 (Icarus v2.0) | -+--------------+---------------------------------------+----------------------+ - -Supported Features -================== - -The actinius_icarus board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| ACCEL | st | lis2dh | -+-----------+------------+----------------------+ - -SIM Selection -============= - -The SIM choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting -the ``sim`` property in the ``sim_select`` node. - -Charger Enable/Disable -====================== - -Since hardware version 2.0 the charger can be disabled by adjusting the ``charger`` -property of the ``charger_enable`` device tree node. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_ns``. -3. Merge the two binaries together. - -If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and -burned automatically, unless you have disabled the feature. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -More information can be found in the `Icarus "Get Started" Guide`_ or the -`Actinius Documentation Portal`_. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau - -.. _Icarus Product Website: - https://www.actinius.com/icarus - -.. _Icarus "Get Started" Guide: - https://www.actinius.com/get-started - -.. _Actinius Documentation Portal: - https://docs.actinius.com diff --git a/boards/arm/actinius_icarus/revision.cmake b/boards/arm/actinius_icarus/revision.cmake deleted file mode 100644 index d63947b74bf..00000000000 --- a/boards/arm/actinius_icarus/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Actinius -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT MAJOR.MINOR.PATCH - DEFAULT_REVISION 2.0.0 - VALID_REVISIONS 1.4.0 2.0.0 -) diff --git a/boards/arm/actinius_icarus_bee/CMakeLists.txt b/boards/arm/actinius_icarus_bee/CMakeLists.txt deleted file mode 100644 index b54029984d1..00000000000 --- a/boards/arm/actinius_icarus_bee/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021-2022 Actinius -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/arm/actinius_icarus_bee/Kconfig.board b/boards/arm/actinius_icarus_bee/Kconfig.board deleted file mode 100644 index 39081152558..00000000000 --- a/boards/arm/actinius_icarus_bee/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Actinius Icarus Bee board configuration - -# Copyright (c) 2021 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_ACTINIUS_ICARUS_BEE - bool "Actinius Icarus Bee" - -config BOARD_ACTINIUS_ICARUS_BEE_NS - bool "Actinius Icarus Bee Non-Secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/actinius_icarus_bee/Kconfig.defconfig b/boards/arm/actinius_icarus_bee/Kconfig.defconfig deleted file mode 100644 index 309a45a61d4..00000000000 --- a/boards/arm/actinius_icarus_bee/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Actinius Icarus Bee board configuration - -# Copyright (c) 2021 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACTINIUS_ICARUS_BEE || BOARD_ACTINIUS_ICARUS_BEE_NS - -config BOARD - default "actinius_icarus_bee" - -source "boards/common/actinius/Kconfig" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_ACTINIUS_ICARUS_BEE && TRUSTED_EXECUTION_SECURE - -if BOARD_ACTINIUS_ICARUS_BEE_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_ACTINIUS_ICARUS_BEE_NS - -endif # BOARD_ACTINIUS_ICARUS_BEE || BOARD_ACTINIUS_ICARUS_BEE_NS diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee.yaml b/boards/arm/actinius_icarus_bee/actinius_icarus_bee.yaml deleted file mode 100644 index 87052c0a149..00000000000 --- a/boards/arm/actinius_icarus_bee/actinius_icarus_bee.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: actinius_icarus_bee -name: Actinius Icarus Bee -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 256 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter -vendor: actinius diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_defconfig b/boards/arm/actinius_icarus_bee/actinius_icarus_bee_defconfig deleted file mode 100644 index 64de49c899b..00000000000 --- a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_BEE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns.yaml b/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns.yaml deleted file mode 100644 index 6255c80c010..00000000000 --- a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: actinius_icarus_bee_ns -name: Actinius Icarus Bee Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter -vendor: actinius diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns_defconfig b/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns_defconfig deleted file mode 100644 index 7e0d1c6e2df..00000000000 --- a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_BEE_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_bee/doc/index.rst b/boards/arm/actinius_icarus_bee/doc/index.rst deleted file mode 100644 index b6d166900aa..00000000000 --- a/boards/arm/actinius_icarus_bee/doc/index.rst +++ /dev/null @@ -1,137 +0,0 @@ -.. _actinius_icarus_bee: - -Actinius Icarus Bee -################### - -Overview -******** - -.. figure:: img/icarus-bee.jpg - :align: center - :alt: Icarus Bee - - Icarus Bee (nRF9160 Bee) - -The Icarus Bee is a cellular IoT board in Bee/xBee form factor. -It is built around Nordic Semi's nRF9160 modem and combines -LTE-M, NB-IoT, GPS, accelerometer, SPI Flash, RGB LED, Button, -as well as an eSIM and a nano SIM connector. - -The main uController is the Nordic Semiconductor nRF9160, with -ARM Cortex-M33F CPU, ARMv8-M Security Extension and the -following devices (provided directly by Nordic): - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -.. figure:: img/icarus-bee-external-pins.jpg - :align: center - :alt: Icarus Bee w/ Pinouts - - Icarus Bee w/ Pinouts - -.. figure:: img/icarus-bee-peripherals-pins.jpg - :align: center - :alt: Icarus Bee - - Internal Pinouts - -Hardware -******** - -The detailed information about the on-board hardware can be found at the `Icarus Bee Product Website`_. - -Supported Features -================== - -The actinius_icarus_bee board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| ACCEL | st | lis2dh | -+-----------+------------+----------------------+ - -SIM selection -************* - -The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting -the ``sim`` property in the ``sim_select`` node. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_bee``. -2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_bee_ns``. -3. Merge the two binaries together. - -If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and -burned automatically, unless you have disabled the feature. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -More information can be found in the `Icarus Bee Product Website`_ or the -`Actinius Documentation Portal`_. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau - -.. _Icarus Bee Product Website: - https://www.actinius.com/icarus-bee - -.. _Actinius Documentation Portal: - https://docs.actinius.com diff --git a/boards/arm/actinius_icarus_som/CMakeLists.txt b/boards/arm/actinius_icarus_som/CMakeLists.txt deleted file mode 100644 index b54029984d1..00000000000 --- a/boards/arm/actinius_icarus_som/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021-2022 Actinius -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/arm/actinius_icarus_som/Kconfig.board b/boards/arm/actinius_icarus_som/Kconfig.board deleted file mode 100644 index e661fb2a00b..00000000000 --- a/boards/arm/actinius_icarus_som/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Actinius Icarus SoM board configuration - -# Copyright (c) 2021 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_ACTINIUS_ICARUS_SOM - bool "Actinius Icarus SoM" - -config BOARD_ACTINIUS_ICARUS_SOM_NS - bool "Actinius Icarus SoM Non-Secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/actinius_icarus_som/Kconfig.defconfig b/boards/arm/actinius_icarus_som/Kconfig.defconfig deleted file mode 100644 index 473acfea29f..00000000000 --- a/boards/arm/actinius_icarus_som/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Actinius Icarus SoM board configuration - -# Copyright (c) 2021 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACTINIUS_ICARUS_SOM || BOARD_ACTINIUS_ICARUS_SOM_NS - -config BOARD - default "actinius_icarus_som" - -source "boards/common/actinius/Kconfig" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_ACTINIUS_ICARUS_SOM && TRUSTED_EXECUTION_SECURE - -if BOARD_ACTINIUS_ICARUS_SOM_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_ACTINIUS_ICARUS_SOM_NS - -endif # BOARD_ACTINIUS_ICARUS_SOM || BOARD_ACTINIUS_ICARUS_SOM_NS diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som.yaml b/boards/arm/actinius_icarus_som/actinius_icarus_som.yaml deleted file mode 100644 index db7c14011b5..00000000000 --- a/boards/arm/actinius_icarus_som/actinius_icarus_som.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: actinius_icarus_som -name: Actinius Icarus SoM -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 256 -supported: - - gpio - - i2c - - pwm - - watchdog - - counter -vendor: actinius diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_defconfig b/boards/arm/actinius_icarus_som/actinius_icarus_som_defconfig deleted file mode 100644 index b2bbfdba52d..00000000000 --- a/boards/arm/actinius_icarus_som/actinius_icarus_som_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_SOM=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_ns.yaml b/boards/arm/actinius_icarus_som/actinius_icarus_som_ns.yaml deleted file mode 100644 index 6f4d731867d..00000000000 --- a/boards/arm/actinius_icarus_som/actinius_icarus_som_ns.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: actinius_icarus_som_ns -name: Actinius Icarus SoM Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - gpio - - i2c - - pwm - - watchdog - - counter -vendor: actinius diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_ns_defconfig b/boards/arm/actinius_icarus_som/actinius_icarus_som_ns_defconfig deleted file mode 100644 index 81712f3aa1f..00000000000 --- a/boards/arm/actinius_icarus_som/actinius_icarus_som_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_SOM_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som/doc/index.rst b/boards/arm/actinius_icarus_som/doc/index.rst deleted file mode 100644 index 6c22d627e11..00000000000 --- a/boards/arm/actinius_icarus_som/doc/index.rst +++ /dev/null @@ -1,137 +0,0 @@ -.. _actinius_icarus_som: - -Actinius Icarus SoM -################### - -Overview -******** - -.. figure:: img/icarus-som.jpg - :align: center - :alt: Icarus SoM - - Icarus SoM (nRF9160) - -The Icarus SoM is a coin-sized, easy-to-solder cellular IoT Module -built around Nordic Semi's nRF9160 modem and combines -LTE-M, NB-IoT, GPS, accelerometer as well as an eSIM and option for -an external nano SIM connector. - -The main uController is the Nordic Semiconductor nRF9160, with -ARM Cortex-M33F CPU, ARMv8-M Security Extension and the -following devices (provided directly by Nordic): - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -.. figure:: img/icarus-som-external-pins.jpg - :align: center - :alt: Icarus SoM Pins - - Icarus SoM Pins - -.. figure:: img/icarus-som-peripherals-pins.jpg - :align: center - :alt: Icarus SoM - - Internal Pinouts - -Hardware -******** - -The detailed information about the on-board hardware can be found at the `Icarus SoM Product Website`_. - -Supported Features -================== - -The actinius_icarus_som board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| ACCEL | st | lis2dh | -+-----------+------------+----------------------+ - -SIM selection -************* - -The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting -the ``sim`` property in the ``sim_select`` node. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_som``. -2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_som_ns``. -3. Merge the two binaries together. - -If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and -burned automatically, unless you have disabled the feature. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -More information can be found in the `Icarus SoM Product Website`_ or the -`Actinius Documentation Portal`_. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau - -.. _Icarus SoM Product Website: - https://www.actinius.com/icarus-som - -.. _Actinius Documentation Portal: - https://docs.actinius.com diff --git a/boards/arm/actinius_icarus_som_dk/CMakeLists.txt b/boards/arm/actinius_icarus_som_dk/CMakeLists.txt deleted file mode 100644 index 1fff4c1e76c..00000000000 --- a/boards/arm/actinius_icarus_som_dk/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2022 Actinius -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/arm/actinius_icarus_som_dk/Kconfig.board b/boards/arm/actinius_icarus_som_dk/Kconfig.board deleted file mode 100644 index d3d1bcacfd0..00000000000 --- a/boards/arm/actinius_icarus_som_dk/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Actinius Icarus SoM DK board configuration - -# Copyright (c) 2022 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_ACTINIUS_ICARUS_SOM_DK - bool "Actinius Icarus SoM DK" - -config BOARD_ACTINIUS_ICARUS_SOM_DK_NS - bool "Actinius Icarus SoM DK Non-Secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/actinius_icarus_som_dk/Kconfig.defconfig b/boards/arm/actinius_icarus_som_dk/Kconfig.defconfig deleted file mode 100644 index 00024ae99ca..00000000000 --- a/boards/arm/actinius_icarus_som_dk/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Actinius Icarus SoM DK board configuration - -# Copyright (c) 2022 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACTINIUS_ICARUS_SOM_DK || BOARD_ACTINIUS_ICARUS_SOM_DK_NS - -config BOARD - default "actinius_icarus_som_dk" - -source "boards/common/actinius/Kconfig" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_ACTINIUS_ICARUS_SOM_DK && TRUSTED_EXECUTION_SECURE - -if BOARD_ACTINIUS_ICARUS_SOM_DK_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_ACTINIUS_ICARUS_SOM_DK_NS - -endif # BOARD_ACTINIUS_ICARUS_SOM_DK || BOARD_ACTINIUS_ICARUS_SOM_DK_NS diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk.yaml b/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk.yaml deleted file mode 100644 index aea5ef27753..00000000000 --- a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: actinius_icarus_som_dk -name: Actinius Icarus SoM DK -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 256 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi -vendor: actinius diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_defconfig b/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_defconfig deleted file mode 100644 index 2542dbb901e..00000000000 --- a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_SOM_DK=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns.yaml b/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns.yaml deleted file mode 100644 index 2ecf72e7a57..00000000000 --- a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: actinius_icarus_som_dk_ns -name: Actinius Icarus SoM DK Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi -vendor: actinius diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns_defconfig b/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns_defconfig deleted file mode 100644 index 212dd785cd2..00000000000 --- a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_SOM_DK_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som_dk/doc/index.rst b/boards/arm/actinius_icarus_som_dk/doc/index.rst deleted file mode 100644 index 94cda9e5c02..00000000000 --- a/boards/arm/actinius_icarus_som_dk/doc/index.rst +++ /dev/null @@ -1,245 +0,0 @@ -.. _actinius_icarus_som_dk: - -Actinius Icarus SoM DK -###################### - -Overview -******** - -.. figure:: img/icarus-som-dk.jpg - :width: 450px - :align: center - :alt: Icarus SoM DK - - Icarus SoM Development Kit (nRF9160) - -The Icarus SoM DK is a single board development kit for -evaluation and development on the Icarus SoM (`Icarus SoM Docs`_). -The Icarus SoM features the nRF9160 SiP from Nordic Semiconductor, -a low-power 3-axis accelerometer and an on-board eSIM. -The development kit provides interfacing to the SoM through USB-C, -a set of user LEDs, a reset and a user button, a battery charging port, -and a external nano SIM connector. -The board is also Arduino Uno Rev3 compatible which makes -using external shields possible. - -The main uController is the Nordic Semiconductor nRF9160, with -ARM Cortex-M33F CPU, ARMv8-M Security Extension and the -following devices (provided directly by Nordic): - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -.. figure:: img/icarus-som-dk-block-diagram.jpg - :width: 450px - :align: center - :alt: Icarus SoM DK Block Diagram - - Icarus SoM DK Block Diagram - -Hardware -******** - -The detailed information about the on-board hardware can be found at the `Icarus SoM Product Website`_ -and the `Icarus SoM DK Product Website`_. - -Pin description -=============== - -External Pins available to user: - -+----+-------+------------------------------------+------------------+ -| # | Label | Description | Device-tree node | -+====+=======+====================================+==================+ -| 1 | NC | Not Connected | - | -+----+-------+------------------------------------+------------------+ -| 2 | IOREF | I/O reference, connected to 3.3V | - | -+----+-------+------------------------------------+------------------+ -| 3 | RST | Reset of the nRF9160 | - | -+----+-------+------------------------------------+------------------+ -| 4 | 3.3V | 3.3V Power output | - | -+----+-------+------------------------------------+------------------+ -| 5 | 4.4V | Power output between Vbat and 4.4V | - | -+----+-------+------------------------------------+------------------+ -| 6 | GND | Ground pin | - | -+----+-------+------------------------------------+------------------+ -| 7 | GND | Ground pin | - | -+----+-------+------------------------------------+------------------+ -| 8 | VIN | Power input pin (4.35V to 10.5V) | - | -+----+-------+------------------------------------+------------------+ -| 9 | A2 | AIN2 / nRF9160 P0.15 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 10 | A3 | AIN3 / nRF9160 P0.16 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 11 | A4 | AIN4 / nRF9160 P0.17 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 12 | A5 | AIN5 / nRF9160 P0.18 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 13 | A6 | AIN6 / nRF9160 P0.19 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 14 | A7 | AIN7 / nRF9160 P0.20 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 15 | P4 | nRF9160 P0.04 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 16 | P5 | nRF9160 P0.05 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 17 | P2 | nRF9160 P0.02 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 18 | P1 | nRF9160 P0.01 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 19 | P23 | nRF9160 P0.23 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 20 | P0 | nRF9160 P0.00 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 21 | P26 | nRF9160 P0.26 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 22 | P27 | nRF9160 P0.27 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 23 | P30 | nRF9160 P0.30 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 24 | P31 | nRF9160 P0.31 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 25 | P7 | nRF9160 P0.07 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 26 | P13 | nRF9160 P0.13 or NC (Jumper-dependent) | gpio0 | -+----+-------+------------------------------------+------------------+ -| 27 | P14 | nRF9160 P0.14 or NC (Jumper-dependent) | gpio0 | -+----+-------+------------------------------------+------------------+ -| 28 | P3 | nRF9160 P0.03 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 29 | GND | Ground pin | - | -+----+-------+------------------------------------+------------------+ -| 30 | AREF | NC or AIN1 (Jumper-dependent) | gpio0 | -+----+-------+------------------------------------+------------------+ -| 31 | SDA | I2C SDA pin | i2c2 | -+----+-------+------------------------------------+------------------+ -| 32 | SCL | I2C SCL pin | i2c2 | -+----+-------+------------------------------------+------------------+ -| - | TS | Pin for optional battery thermistor| - | -+----+-------+------------------------------------+------------------+ -| - | CHG | Pin for battery charging indication| - | -+----+-------+------------------------------------+------------------+ -| - | CE | Pin for enabling/disabling charging| - | -+----+-------+------------------------------------+------------------+ - - -nRF9160 pins connected internally: - -+--------------+------------------------------+---------------------+ -| nRF9160 pin | Function | Device-tree node | -+==============+==============================+=====================+ -| P0.03 | Blue LED | led0 / pwm-led0 | -+--------------+------------------------------+---------------------+ -| P0.08 | NeoPixel RGB LED | spi1 | -+--------------+------------------------------+---------------------+ -| P0.12 | SIM select pin | gpio0 | -+--------------+------------------------------+---------------------+ -| P0.23 | Connected to the user button | gpio0 / button0 | -+--------------+------------------------------+---------------------+ -| P0.24 | SPI NOR Flash chip select | gpio0 / spi3 | -+--------------+------------------------------+---------------------+ -| P0.28 | Accelerometer Interrupt 2 | lis2dh12-accel | -+--------------+------------------------------+---------------------+ -| P0.29 | Accelerometer Interrupt 1 | lis2dh12-accel | -+--------------+------------------------------+---------------------+ - -Supported Features -================== - -The actinius_icarus_som_dk board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| ACCEL | st | lis2dh | -+-----------+------------+----------------------+ - -SIM selection -************* - -The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting -the ``sim`` property in the ``sim_select`` node. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_som_dk``. -2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_som_dk_ns``. -3. Merge the two binaries together. - -If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and -burned automatically, unless you have disabled the feature. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -More information can be found in the `Icarus SoM Product Website`_, -the `Icarus SoM DK Product Website`_ or the `Actinius Documentation Portal`_. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau - -.. _Icarus SoM Product Website: - https://www.actinius.com/icarus-som - -.. _Icarus SoM DK Product Website: - https://www.actinius.com/icarus-som-dk - -.. _Icarus SoM Docs: - https://docs.actinius.com/icarus-som/introduction - -.. _Actinius Documentation Portal: - https://docs.actinius.com diff --git a/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.board b/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.board deleted file mode 100644 index 9f33d8c05b7..00000000000 --- a/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather M0 Basic Proto board configuration - -# Copyright (c) 2018 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_FEATHER_M0_BASIC_PROTO - bool "Adafruit Feather M0 Basic Proto" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.defconfig b/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.defconfig deleted file mode 100644 index 834c8c14cea..00000000000 --- a/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather M0 Basic Proto board configuration - -# Copyright (c) 2018 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adafruit_feather_m0_basic_proto" - depends on BOARD_ADAFRUIT_FEATHER_M0_BASIC_PROTO diff --git a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig b/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig deleted file mode 100644 index 5d8166f71e9..00000000000 --- a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_ADAFRUIT_FEATHER_M0_BASIC_PROTO=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/adafruit_feather_m0_basic_proto/doc/index.rst b/boards/arm/adafruit_feather_m0_basic_proto/doc/index.rst deleted file mode 100644 index 4b1af3d8d49..00000000000 --- a/boards/arm/adafruit_feather_m0_basic_proto/doc/index.rst +++ /dev/null @@ -1,167 +0,0 @@ -.. _adafruit_feather_m0_basic_proto: - -Adafruit Feather M0 Basic Proto -############################### - -Overview -******** - -The Adafruit Feather M0 Basic Proto is a thin, light ARM development -board with an onboard battery connector and charger for 3.7 V lithium -polymer batteries, charging status indicator and user LEDs, native USB -connector, 20 I/O pins, and a small prototyping area. - -.. image:: img/adafruit_feather_m0_basic_proto.jpg - :align: center - :alt: Adafruit Feather M0 Basic Proto - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- Battery connector and charger for 3.7 V lithium polymer batteries -- Charging indicator LED -- User LED -- Reset button -- Native USB port - -Supported Features -================== - -The adafruit_feather_m0_basic_proto board configuration supports the -following hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | Systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial port | -+-----------+------------+------------------------------------------+ -| I2C | on-chip | Inter-Integrated Circuit | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface port | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig`. - -Connections and IOs -=================== - -The `Adafruit Feather M0 Basic Proto Learn site`_ has detailed -information about the board including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 -Basic Proto, SERCOM0 is the Zephyr console and is available on pins 0 -(RX) and 1 (TX). - -I2C Port -======== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 -Basic Proto, SERCOM3 is available on pin 20 (SDA) and pin 21 (SCL). - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the Adafruit Feather M0 -Basic Proto, SERCOM4 is available on pin 22 (MISO), pin 23 (MOSI), and -pin 24 (SCK). - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -Programming and Debugging -************************* - -The Adafruit Feather M0 Basic Proto ships with a BOSSA compatible -SAM-BA bootloader. The bootloader can be entered by quickly tapping -the reset button twice. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_feather_m0_basic_proto - :goals: build - :compact: - -#. Connect the Adafruit Feather M0 Basic Proto to your host computer - using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_feather_m0_basic_proto - :goals: flash - :compact: - - You should see "Hello World! adafruit_feather_m0_basic_proto" in your terminal. - -References -********** - -.. target-notes:: - -.. _Adafruit Feather M0 Basic Proto Learn site: - https://learn.adafruit.com/adafruit-feather-m0-basic-proto/ - -.. _pinouts: - https://learn.adafruit.com/adafruit-feather-m0-basic-proto/pinouts - -.. _schematic: - https://learn.adafruit.com/adafruit-feather-m0-basic-proto/downloads diff --git a/boards/arm/adafruit_feather_m0_lora/Kconfig.board b/boards/arm/adafruit_feather_m0_lora/Kconfig.board deleted file mode 100644 index 002cf289f7a..00000000000 --- a/boards/arm/adafruit_feather_m0_lora/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather M0 LoRa board configuration - -# Copyright (c) 2022 Miguel Dardenne -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_FEATHER_M0_LORA - bool "Adafruit Feather M0 LoRa" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/adafruit_feather_m0_lora/Kconfig.defconfig b/boards/arm/adafruit_feather_m0_lora/Kconfig.defconfig deleted file mode 100644 index 08a3c802d43..00000000000 --- a/boards/arm/adafruit_feather_m0_lora/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather M0 LoRa board configuration - -# Copyright (c) 2022 Miguel Dardenne -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adafruit_feather_m0_lora" - depends on BOARD_ADAFRUIT_FEATHER_M0_LORA diff --git a/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora_defconfig b/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora_defconfig deleted file mode 100644 index 20bed381bb9..00000000000 --- a/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_ADAFRUIT_FEATHER_M0_LORA=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/adafruit_feather_m0_lora/doc/index.rst b/boards/arm/adafruit_feather_m0_lora/doc/index.rst deleted file mode 100644 index 154feb14539..00000000000 --- a/boards/arm/adafruit_feather_m0_lora/doc/index.rst +++ /dev/null @@ -1,176 +0,0 @@ -.. _adafruit_feather_m0_lora: - -Adafruit Feather M0 LoRa -######################## - -Overview -******** - -The Adafruit Feather M0 Lora is a thin, light ARM development -boards with an onboard battery connector and charger for 3.7 V lithium -polymer batteries, charging status indicator and user LEDs, native USB -connector, 20 I/O pins, and a LoRa radio module from Semtech. - -.. image:: img/adafruit_feather_m0_lora.jpg - :align: center - :alt: Adafruit Feather M0 LoRa - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- Battery connector and charger for 3.7 V lithium polymer batteries -- Charging indicator LED -- User LED -- Reset button -- Native USB port -- SX127x LoRa radio - -Supported Features -================== - -The adafruit_feather_m0_lora board configuration supports the -following hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | Systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial port | -+-----------+------------+------------------------------------------+ -| I2C | on-chip | Inter-Integrated Circuit | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface port | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| RADIO | SPI | LoRa radio | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora_defconfig`. - -Connections and IOs -=================== - -The `Adafruit Feather M0 with LoRa radio module Learn site`_ has detailed -information about the board including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 -with LoRa, SERCOM0 is the Zephyr console and is available on pins 0 -(RX) and 1 (TX). - -I2C Port -======== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 -with LoRa, SERCOM3 is available on pin 20 (SDA) and pin 21 (SCL). - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the Adafruit Feather M0 -with LoRa, SERCOM4 is available on pin 22 (MISO), pin 23 (MOSI), and -pin 24 (SCK). - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -LoRa Radio -========== -The Semtech SX127x radio chip on the Adafruit Feather M0 with LoRa -is attached to the SPI port (SERCOM4). Depending on the hardware -version, 433MHz or 900MHz is supported. - -Programming and Debugging -************************* - -The Adafruit Feather M0 with LoRa ships with a BOSSA compatible -SAM-BA bootloader. The bootloader can be entered by quickly tapping -the reset button twice. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_feather_m0_lora - :goals: build - :compact: - -#. Connect the Adafruit Feather M0 with LoRa to your host computer - using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_feather_m0_lora - :goals: flash - :compact: - - You should see "Hello World! adafruit_feather_m0_lora" in your terminal. - -References -********** - -.. target-notes:: - -.. _Adafruit Feather M0 with LoRa radio module Learn site: - https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module - -.. _pinouts: - https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module/pinouts - -.. _schematic: - https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module/downloads diff --git a/boards/arm/adafruit_feather_nrf52840/Kconfig b/boards/arm/adafruit_feather_nrf52840/Kconfig deleted file mode 100644 index 4398595868f..00000000000 --- a/boards/arm/adafruit_feather_nrf52840/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Adafruit Feather nRF52840 Express board configuration - -# Copyright (c) 2020 Tobias Svehagen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_ADAFRUIT_FEATHER_NRF52840 diff --git a/boards/arm/adafruit_feather_nrf52840/Kconfig.board b/boards/arm/adafruit_feather_nrf52840/Kconfig.board deleted file mode 100644 index 4e37d05303a..00000000000 --- a/boards/arm/adafruit_feather_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather nRF52840 Express board configuration - -# Copyright (c) 2020 Tobias Svehagen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_FEATHER_NRF52840 - bool "Adafruit Feather nRF52840 Express" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/adafruit_feather_nrf52840/Kconfig.defconfig b/boards/arm/adafruit_feather_nrf52840/Kconfig.defconfig deleted file mode 100644 index f2d04d6cc48..00000000000 --- a/boards/arm/adafruit_feather_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Adafruit Feather nRF52840 Express board configuration - -# Copyright (c) 2020 Tobias Svehagen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADAFRUIT_FEATHER_NRF52840 - -config BOARD - default "adafruit_feather_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_ADAFRUIT_FEATHER_NRF52840 diff --git a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840_defconfig b/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840_defconfig deleted file mode 100644 index 74b11931eb8..00000000000 --- a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_ADAFRUIT_FEATHER_NRF52840=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/adafruit_feather_nrf52840/doc/index.rst b/boards/arm/adafruit_feather_nrf52840/doc/index.rst deleted file mode 100644 index 6d4af8ca296..00000000000 --- a/boards/arm/adafruit_feather_nrf52840/doc/index.rst +++ /dev/null @@ -1,146 +0,0 @@ -.. _adafruit_feather_nrf52840: - -Adafruit Feather nRF52840 Express -################################# - -Overview -******** - -The Adafruit Feather nRF52840 provides support for the Nordic Semiconductor -nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/adafruit_feather_nrf52840.jpg - :align: center - :alt: Adafruit Feather nRF52840 Express - -Hardware -******** - -- nRF52840 ARM Cortex-M4F processor at 64 MHz -- 1 MB flash memory and 256 KB of SRAM -- Battery connector and charger for 3.7 V lithium polymer batteries -- Charging indicator LED -- 2 User LEDs -- 1 NeoPixel LED -- Reset button -- SWD connector - -Supported Features -================== - -The Adafruit Feather nRF52840 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -The `Adafruit Feather nRF52840 Express Learn site`_ has detailed -information about the board including `pinouts`_ and the `schematic`_. - -LED ---- - -* LED0 (red) = P1.15 -* LED1 (blue) = P1.10 - -Push buttons ------------- - -* SWITCH = P1.02 -* RESET = P0.18 - -Programming and Debugging -************************* - -Applications for the ``adafruit_feather_nrf52840`` board configuration -can be built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - -Flashing -======== - -Flashing Zephyr onto the ``adafruit_feather_nrf52480`` board requires -an external programmer. The programmer is attached to the SWD header. - -Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application. - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: adafruit_feather_nrf52840 - :goals: build - :compact: - -Flash the image. - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: adafruit_feather_nrf52840 - :goals: flash - :compact: - -You should see the red LED blink. - -References -********** - -.. target-notes:: - -.. _Adafruit Feather nRF52840 Express Learn site: - https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/ - -.. _pinouts: - https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/pinouts - -.. _schematic: - https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/downloads diff --git a/boards/arm/adafruit_feather_stm32f405/Kconfig.board b/boards/arm/adafruit_feather_stm32f405/Kconfig.board deleted file mode 100644 index 8f563963fee..00000000000 --- a/boards/arm/adafruit_feather_stm32f405/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather STM32F405 Express board configuration - -# Copyright (c) 2020 Lucian Copeland for Adafruit Industries -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_FEATHER_STM32F405 - bool "Feather STM32F405 Express Board" - depends on SOC_STM32F405XG diff --git a/boards/arm/adafruit_feather_stm32f405/Kconfig.defconfig b/boards/arm/adafruit_feather_stm32f405/Kconfig.defconfig deleted file mode 100644 index 1e7e3593d34..00000000000 --- a/boards/arm/adafruit_feather_stm32f405/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Adafruit Feather STM32F405 Express board configuration - -# Copyright (c) 2020 Lucian Copeland for Adafruit Industries. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADAFRUIT_FEATHER_STM32F405 - -config BOARD - default "adafruit_feather_stm32f405" - -endif # BOARD_ADAFRUIT_FEATHER_STM32F405 diff --git a/boards/arm/adafruit_grand_central_m4_express/Kconfig.board b/boards/arm/adafruit_grand_central_m4_express/Kconfig.board deleted file mode 100644 index 4ca7a712697..00000000000 --- a/boards/arm/adafruit_grand_central_m4_express/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Grand Central M4 Express board configuration - -# Copyright (c) 2023 Lukas Jung -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_GRAND_CENTRAL_M4_EXPRESS - bool "Adafruit Grand Central M4 Express" - depends on SOC_PART_NUMBER_SAMD51P20A diff --git a/boards/arm/adafruit_grand_central_m4_express/Kconfig.defconfig b/boards/arm/adafruit_grand_central_m4_express/Kconfig.defconfig deleted file mode 100644 index 72266e97bac..00000000000 --- a/boards/arm/adafruit_grand_central_m4_express/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Grand Central M4 Express board configuration - -# Copyright (c) 2023 Lukas Jung -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adafruit_grand_central_m4_express" - depends on BOARD_ADAFRUIT_GRAND_CENTRAL_M4_EXPRESS diff --git a/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express_defconfig b/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express_defconfig deleted file mode 100644 index b5bfafe5b18..00000000000 --- a/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD51=y -CONFIG_SOC_PART_NUMBER_SAMD51P20A=y -CONFIG_BOARD_ADAFRUIT_GRAND_CENTRAL_M4_EXPRESS=y -CONFIG_SOC_ATMEL_SAMD5X_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_GPIO=y - -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y -CONFIG_BUILD_OUTPUT_UF2=y -CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/adafruit_grand_central_m4_express/doc/index.rst b/boards/arm/adafruit_grand_central_m4_express/doc/index.rst deleted file mode 100644 index a5dba70f617..00000000000 --- a/boards/arm/adafruit_grand_central_m4_express/doc/index.rst +++ /dev/null @@ -1,195 +0,0 @@ -.. _adafruit_grand_central_m4_express: - -Adafruit Grand Central M4 Express -################################# - -Overview -******** - -The Adafruit Grand Central M4 Express is an ARM development board with the -form factor of an Arduino Mega. -It features 70 GPIO pins, a microSDHC slot and 8MiB of QSPI Flash. - -.. figure:: img/adafruit_grand_central_m4_express.webp - :width: 800px - :align: center - :alt: Adafruit Grand Central M4 Express - - Adafruit Grand Central M4 Express (Credit: Kattni Rembor / Adafruit) - -Hardware -******** - -- ATSAMD51P20A ARM Cortex-M4F processor at 120 MHz -- 1024 KiB of flash memory and 256 KiB of RAM -- 8 MiB of QSPI flash -- A red user LED -- A RGB "NeoPixel" / WS2812B LED -- A microSDHC slot (connected via SPI) -- Native USB port - -Supported Features -================== - -The adafruit_grand_central_m4_express board configuration supports the following -hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | SysTick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports, User LED | -+-----------+------------+------------------------------------------+ -| UART | on-chip | Serial ports, Console | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | SPI ports, microSDHC slot | -+-----------+------------+------------------------------------------+ -| TRNG | on-chip | True Random Number Generator | -+-----------+------------+------------------------------------------+ -| RTC | on-chip | Real-Time Counter | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog Timer | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express_defconfig`. - -Connections and IOs -=================== - -The `Adafruit Learning System`_ has detailed information about -the board including `pinouts`_ and the `schematics`_. - -System Clock -============ - -The SAMD51 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 120 MHz system clock. - -Serial Port -=========== - -The SAMD51 MCU has 8 SERCOM based UARTs. On the Grand Central, SERCOM0 is -the Zephyr console and is available on RX(PB25) and TX(PB24). - -SPI Port -======== - -The SAMD51 MCU has 8 SERCOM based SPIs. On the Grand Central, SERCOM7 has been -set into SPI mode to connect to devices over the SCK(PD09), MOSI(PD08), and MISO(PD11) pins. -Additionally SERCOM2 has been configured as SPI to access the microSDHC card. - -I2C Port -======== - -The SAMD51 MCU has 8 SERCOM based I2Cs. On the Grand Central, SERCOM3 has been -configured as I2C to connect to devices over the SCL(PB21) and SDA(PB20) pins. - -USB Device Port -=============== - -The SAMD51 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -Programming and Debugging -************************* - -The Grand Central ships with a BOSSA compatible UF2 bootloader. -The bootloader can be entered by quickly tapping the reset button twice. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_grand_central_m4_express - :goals: build - :compact: - -#. Connect the Grand Central to your host computer using USB. - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyUSB0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_grand_central_m4_express - :goals: flash - :compact: - - You should see "Hello World! adafruit_grand_central_m4_express" in your terminal. - -Debugging -========= - -In addition to the built-in bootloader, the Grand Central can be flashed and -debugged using a SWD probe such as the Segger J-Link. - -#. Connect the probe to the board using the 10-pin SWD interface. - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_grand_central_m4_express - :goals: flash - :flash-args: -r openocd - :compact: - -#. Start debugging: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_grand_central_m4_express - :goals: debug - :compact: - -References -********** - -.. target-notes:: - -.. _Adafruit Learning System: - https://learn.adafruit.com/adafruit-grand-central - -.. _pinouts: - https://learn.adafruit.com/adafruit-grand-central/pinouts - -.. _schematics: - https://learn.adafruit.com/adafruit-grand-central/downloads - -.. _J-Link: - https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.board b/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.board deleted file mode 100644 index 79fd1eb6293..00000000000 --- a/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit ItsyBitsy M4 Express board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_ITSYBITSY_M4_EXPRESS - bool "Adafruit ItsyBitsy M4 Express" - depends on SOC_PART_NUMBER_SAMD51G19A diff --git a/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.defconfig b/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.defconfig deleted file mode 100644 index 922a2ab58bd..00000000000 --- a/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit ItsyBitsy M4 Express board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adafruit_itsybitsy_m4_express" - depends on BOARD_ADAFRUIT_ITSYBITSY_M4_EXPRESS diff --git a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig b/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig deleted file mode 100644 index 9a06333e117..00000000000 --- a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD51=y -CONFIG_SOC_PART_NUMBER_SAMD51G19A=y -CONFIG_BOARD_ADAFRUIT_ITSYBITSY_M4_EXPRESS=y -CONFIG_SOC_ATMEL_SAMD5X_OSCULP32K_AS_MAIN=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y diff --git a/boards/arm/adafruit_itsybitsy_m4_express/doc/index.rst b/boards/arm/adafruit_itsybitsy_m4_express/doc/index.rst deleted file mode 100644 index 401e28d6669..00000000000 --- a/boards/arm/adafruit_itsybitsy_m4_express/doc/index.rst +++ /dev/null @@ -1,209 +0,0 @@ -.. _adafruit_itsybitsy_m4_express: - -Adafruit ItsyBitsy M4 Express -############################# - -Overview -******** - -The Adafruit ItsyBitsy M4 express is a small (36 mm x 18 mm) ARM development -board with an onboard RGB LED, USB port, 2 MiB of SPI flash, and range of I/O -broken out onto 23 GPIO pins. - -.. image:: img/adafruit_itsybitsy_m4_express.jpg - :align: center - :alt: Adafruit ItsyBitsy M4 Express - -Hardware -******** - -- ATSAMD51G19A ARM Cortex-M4 processor at 120 MHz -- 512 KiB of flash memory and 192 KiB of RAM -- 2 MiB of SPI flash -- Internal trimmed 8 MHz oscillator -- A user LED -- An RGB DotStar LED -- Native USB port -- One reset button - -Supported Features -================== - -The adafruit_itsybitsy_m4_express board configuration supports the following -hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| TRNG | on-chip | True Random Number Generator | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Unique 128 bit serial number | -+-----------+------------+------------------------------------------+ -| RTC | on-chip | Real-Time Counter | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog Timer | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig`. - -Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. -To use the RTC, set :code:`CONFIG_CORTEX_M_SYSTICK=n` and set -:code:`CONFIG_SYS_CLOCK_TICKS_PER_SEC` to no more than 32 kHZ divided by 7, -i.e. no more than 4500. - -Connections and IOs -=================== - -The `Adafruit Learning System`_ has detailed information about -the board including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD51 MCU is configured to use the 32 kHz internal oscillator -with the on-chip PLL generating the 120 MHz system clock. - -Serial Port -=========== - -The SAMD51 MCU has 6 SERCOM based USARTs. On the ItsyBitsy, SERCOM3 is -the Zephyr console and is available on pins 0 (RX) and 1 (TX). - -SPI Port -======== - -The SAMD51 MCU has 6 SERCOM based SPIs. On the ItsyBitsy, SERCOM1 can be put -into SPI mode and used to connect to devices over the SCK (SCLK), MO (MOSI), and -MI (MISO) pins. - -PWM -=== - -The SAMD51 has three PWM generators with up to six channels each. :code:`TCC_0` -has a resolution of 24 bits and all other generators are 16 bit. :code:`TCC_1` -pin 2 is mapped to PA18 (D7) and pin 3 is mapped to PA19 (D9). - -USB Device Port -=============== - -The SAMD51 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -Programming and Debugging -************************* - -The ItsyBitsy ships with a the BOSSA compatible UF2 bootloader. The -bootloader can be entered by quickly tapping the reset button twice. - -Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader -will be entered automatically when you run :code:`west flash`. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_itsybitsy_m4_express - :goals: build - :compact: - -#. Connect the ItsyBitsy to your host computer using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyUSB0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_itsybitsy_m4_express - :goals: flash - :compact: - - You should see "Hello World! adafruit_itsybitsy_m4_express" in your terminal. - -Debugging -========= - -In addition to the built-in bootloader, the ItsyBitsy can be flashed and -debugged using a SWD probe such as the Segger J-Link. - -#. Connect the board to the probe by connecting the :code:`SWCLK`, - :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the - ItsyBitsy to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, :code:`GND`, - and :code:`VTref` pins on the `J-Link`_. - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_itsybitsy_m4_express - :goals: flash - :flash-args: -r openocd - :compact: - -#. Start debugging: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_itsybitsy_m4_express - :goals: debug - :compact: - -References -********** - -.. target-notes:: - -.. _Adafruit Learning System: - https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4 - -.. _pinouts: - https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4/pinouts - -.. _schematic: - https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4/downloads - -.. _J-Link: - https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig b/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig deleted file mode 100644 index c01ef570cd5..00000000000 --- a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Adafruit ItsyBitsy nRF52840 Express board configuration - -# Copyright (c) 2022 Embla Flatlandsmo -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_ADAFRUIT_ITSYBITSY_NRF52840 - -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "USB CDC" - default y diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.board b/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.board deleted file mode 100644 index f0a4444fd91..00000000000 --- a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit ItsyBitsy nRF52840 Express board configuration - -# Copyright (c) 2022 Embla Flatlandsmo -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_ITSYBITSY_NRF52840 - bool "Adafruit ItsyBitsy nRF52840 Express" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.defconfig b/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.defconfig deleted file mode 100644 index a31f72aa40d..00000000000 --- a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# Adafruit ItsyBitsy nRF52840 Express board configuration - -# Copyright (c) 2022 Embla Flatlandsmo -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADAFRUIT_ITSYBITSY_NRF52840 - -config BOARD - default "adafruit_itsybitsy_nrf52840" - -config BT_CTLR - default BT - -if BOARD_SERIAL_BACKEND_CDC_ACM - -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default SERIAL - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if CONSOLE - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -config USB_DEVICE_REMOTE_WAKEUP - default n - -if LOG - -# Logger cannot use itself to log -config USB_CDC_ACM_LOG_LEVEL - default 0 - -# Set USB log level to error only -config USB_DEVICE_LOG_LEVEL - default 1 - -# Wait 1500ms at startup for logging -config LOG_PROCESS_THREAD_STARTUP_DELAY_MS - default 1500 - -endif # LOG - -endif # BOARD_SERIAL_BACKEND_CDC_ACM - -endif # BOARD_ADAFRUIT_ITSYBITSY_NRF52840 diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840_defconfig b/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840_defconfig deleted file mode 100644 index a88657578f3..00000000000 --- a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_ADAFRUIT_ITSYBITSY_NRF52840=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Flashing -CONFIG_USE_DT_CODE_PARTITION=y -CONFIG_BUILD_OUTPUT_UF2=y diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/doc/index.rst b/boards/arm/adafruit_itsybitsy_nrf52840/doc/index.rst deleted file mode 100644 index aa28cb501c3..00000000000 --- a/boards/arm/adafruit_itsybitsy_nrf52840/doc/index.rst +++ /dev/null @@ -1,192 +0,0 @@ -.. _adafruit_itsybitsy_nrf52840: - -Adafruit ItsyBitsy nRF52840 -########################### - -Overview -******** - -The Adafruit ItsyBitsy nRF52840 Express is a small (36 mm x 18 mm) ARM -development board with an onboard RGB LED, USB port, 2 MB of QSPI flash, -and range of I/O broken out onto 21 GPIO pins. - -This development kit has the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`I2S (Inter-Integrated Sound)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. image:: img/adafruit_itsybitsy_nrf52840.jpeg - :align: center - :alt: Adafruit ItsyBitsy nRF52840 Express - -Hardware -******** -- nRF52840 ARM Cortex-M4F CPU at 64MHz -- 1 MB of flash memory and 256 KB of SRAM -- 2 MB of QSPI flash -- A user LED -- A user switch -- An RGB DotStar LED -- Native USB port -- One reset button - -Supported Features -================== - -The Adafruit ItsyBitsy nRF52840 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| QSPI(M) | on-chip | nor | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -The `Adafruit ItsyBitsy nRF52840 Express Learn site`_ has detailed -information about the board including `pinouts`_ and the `schematic`_. - -LED ---- - -* LED0 (red) = P0.06 - -* LED1 (Adafruit DotStar) - - * DATA = P0.08 - - * CLK = P1.09 - -Push buttons ------------- - -* SWITCH = P0.29 - -* RESET = P0.18 - -Logging -------- - -Logging is done using the USB-CDC port. See the :zephyr:code-sample:`logging` sample -or the :zephyr:code-sample:`usb-cdc-acm-console` sample applications to see how this works. - -Testing LEDs and buttons on the Adafruit ItsyBitsy nRF52840 Express -******************************************************************* -The :zephyr:code-sample:`button` sample lets you test the buttons (switches) and the red LED. -The :zephyr:code-sample:`blinky` sample lets you test the red LED. - -The DotStar LED has been implemented as a SPI device and can be tested -with the :zephyr:code-sample:`led-apa102` sample application. - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.dts`. - -Programming and Debugging -************************* -The ItsyBitsy ships with the BOSSA compatible UF2 bootloader. The -bootloader can be entered by quickly tapping the reset button twice. - -First time setup -================ -Some versions of this board were shipped with a buggy bootloader. -Ensure that the bootloader is up to date by following the -`Adafruit UF2 Bootloader update`_ tutorial. Note that this tutorial -was made for the Adafruit Feather nRF52840, but the steps to update -the bootloader are the same for the ItsyBitsy. The files for the -ItsyBitsy bootloader can be found in the `Adafruit nRF52 Bootloader repo`_. - -The building and flashing of Zephyr applications have been tested with -release 0.7.0 of the UF2 bootloader. - -Flashing -======== -Flashing is done by dragging and dropping the built Zephyr UF2-file -into the :code:`ITSY840BOOT` drive. - -#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` - sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: adafruit_itsybitsy_nrf52840 - :goals: build - :compact: - -#. Connect the ItsyBitsy to your host computer using USB - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - Drag and drop the file :code:`samples/basic/blinky/build/zephyr/zephyr.uf2` - into :code:`ITSY840BOOT` - -The device will disconnect and you should see the red LED blink. - -References -********** - -.. target-notes:: - -.. _Adafruit ItsyBitsy nRF52840 Express Learn site: - https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express - -.. _pinouts: - https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express/pinouts - -.. _schematic: - https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express/downloads - -.. _Adafruit UF2 Bootloader update: - https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/update-bootloader - -.. _Adafruit nRF52 Bootloader repo: - https://github.com/adafruit/Adafruit_nRF52_Bootloader/releases diff --git a/boards/arm/adafruit_kb2040/Kconfig.board b/boards/arm/adafruit_kb2040/Kconfig.board deleted file mode 100644 index 3b1b1ab5f00..00000000000 --- a/boards/arm/adafruit_kb2040/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Pete Johanson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_KB2040 - bool "Adafruit KB2040 Board" - depends on SOC_RP2040 diff --git a/boards/arm/adafruit_kb2040/Kconfig.defconfig b/boards/arm/adafruit_kb2040/Kconfig.defconfig deleted file mode 100644 index 026c8952018..00000000000 --- a/boards/arm/adafruit_kb2040/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2022 Peter Johanson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADAFRUIT_KB2040 - -config BOARD - default "adafruit_kb2040" - -config RP2_FLASH_W25Q080 - default y - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 125 - -endif #I2C_DW - -config USB_SELF_POWERED - default n - -endif # BOARD_ADAFRUIT_KB2040 diff --git a/boards/arm/adafruit_qt_py_rp2040/Kconfig.board b/boards/arm/adafruit_qt_py_rp2040/Kconfig.board deleted file mode 100644 index f2c8db2c341..00000000000 --- a/boards/arm/adafruit_qt_py_rp2040/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Kelly Lord -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_QT_PY_RP2040 - bool "Adafruit QT Py RP2040 Board" - depends on SOC_RP2040 diff --git a/boards/arm/adafruit_qt_py_rp2040/Kconfig.defconfig b/boards/arm/adafruit_qt_py_rp2040/Kconfig.defconfig deleted file mode 100644 index 705a49ac152..00000000000 --- a/boards/arm/adafruit_qt_py_rp2040/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2022 Peter Johanson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADAFRUIT_QT_PY_RP2040 - -config BOARD - default "adafruit_qt_py_rp2040" - -config RP2_FLASH_W25Q080 - default y - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 125 - -endif #I2C_DW - -config USB_SELF_POWERED - default n - -endif # BOARD_ADAFRUIT_QT_PY_RP2040 diff --git a/boards/arm/adafruit_trinket_m0/Kconfig.board b/boards/arm/adafruit_trinket_m0/Kconfig.board deleted file mode 100644 index 302a0da3feb..00000000000 --- a/boards/arm/adafruit_trinket_m0/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Trinket M0 board configuration - -# Copyright (c) 2018 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_TRINKET_M0 - bool "Adafruit Trinket M0" - depends on SOC_PART_NUMBER_SAMD21E18A diff --git a/boards/arm/adafruit_trinket_m0/Kconfig.defconfig b/boards/arm/adafruit_trinket_m0/Kconfig.defconfig deleted file mode 100644 index 31c97cb7dc2..00000000000 --- a/boards/arm/adafruit_trinket_m0/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Trinket M0 board configuration - -# Copyright (c) 2018 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adafruit_trinket_m0" - depends on BOARD_ADAFRUIT_TRINKET_M0 diff --git a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0_defconfig b/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0_defconfig deleted file mode 100644 index 86fa3a35e00..00000000000 --- a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21E18A=y -CONFIG_BOARD_ADAFRUIT_TRINKET_M0=y -CONFIG_SOC_ATMEL_SAMD_OSC8M=y -CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_USE_DT_CODE_PARTITION=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y diff --git a/boards/arm/adafruit_trinket_m0/doc/index.rst b/boards/arm/adafruit_trinket_m0/doc/index.rst deleted file mode 100644 index 2512df3fd56..00000000000 --- a/boards/arm/adafruit_trinket_m0/doc/index.rst +++ /dev/null @@ -1,170 +0,0 @@ -.. _adafruit_trinket_m0: - -Adafruit Trinket M0 -################### - -Overview -******** - -The Adafruit Trinket M0 is a tiny (27 mm x 15 mm) ARM development -board with an onboard RGB LED, USB port, and range of I/O broken out -onto 5 pins. - -.. image:: img/adafruit_trinket_m0.jpg - :align: center - :alt: Adafruit Trinket M0 - -Hardware -******** - -- ATSAMD21E18A ARM Cortex-M0+ processor at 48 MHz -- 256 KiB flash memory and 32 KiB of RAM -- Internal trimmed 8 MHz oscillator -- A user LED -- An RGB DotStar LED -- Native USB port -- One reset button - -Supported Features -================== - -The adafruit_trinket_m0 board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/adafruit_trinket_m0/adafruit_trinket_m0_defconfig`. - -Connections and IOs -=================== - -The `Adafruit Trinket M0 Learn site`_ has detailed information about -the board including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD21 MCU is configured to use the 8 MHz internal oscillator -with the on-chip PLL generating the 48 MHz system clock. The internal -APB and GCLK unit are set up in the same way as the upstream Arduino -libraries. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the Trinket, SERCOM0 is -the Zephyr console and is available on pins 3 (RX) and 4 (TX). -SERCOM2 is available on pins 2 (RX) and 0 (TX). - -PWM -=== - -The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the Trinket, SERCOM1 is -used to drive the DotStar RGB LED. SERCOM0 can be put into SPI mode -and used to connect to devices over pin 2 (MISO), pin 4 (MOSI), and -pin 3 (SCK). - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -Programming and Debugging -************************* - -The Trinket M0 ships the BOSSA compatible UF2 bootloader. The -bootloader can be entered by quickly tapping the reset button twice. - -Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader -will be entered automatically when you run :code:`west flash`. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_trinket_m0 - :goals: build - :compact: - -#. Connect the Trinket M0 to your host computer using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_trinket_m0 - :goals: flash - :compact: - - You should see "Hello World! adafruit_trinket_m0" in your terminal. - -References -********** - -.. target-notes:: - -.. _Adafruit Trinket M0 Learn site: - https://learn.adafruit.com/adafruit-trinket-m0-circuitpython-arduino - -.. _pinouts: - https://learn.adafruit.com/assets/49778 - -.. _schematic: - https://learn.adafruit.com/assets/45723 diff --git a/boards/arm/adi_eval_adin1110ebz/Kconfig.board b/boards/arm/adi_eval_adin1110ebz/Kconfig.board deleted file mode 100644 index 29f1e3b8dbc..00000000000 --- a/boards/arm/adi_eval_adin1110ebz/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# ADI EVAL-ADIN1110EBZ board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADI_EVAL_ADIN1110EBZ - bool "ADI EVAL-ADIN1110EBZ evaulation board" - depends on SOC_STM32L4S5XX diff --git a/boards/arm/adi_eval_adin1110ebz/Kconfig.defconfig b/boards/arm/adi_eval_adin1110ebz/Kconfig.defconfig deleted file mode 100644 index 79e309af4cd..00000000000 --- a/boards/arm/adi_eval_adin1110ebz/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# ADI EVAL-ADIN1110EBZ board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADI_EVAL_ADIN1110EBZ - -config BOARD - default "adi_eval_adin1110ebz" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -config MDIO_INIT_PRIORITY - default 81 - depends on MDIO - -config PHY_INIT_PRIORITY - default 82 - depends on NET_L2_ETHERNET && ETH_DRIVER - -config MEMC - default y - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_ADI_EVAL_ADIN1110EBZ diff --git a/boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz_defconfig b/boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz_defconfig deleted file mode 100644 index 15174238c66..00000000000 --- a/boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ADI_EVAL_ADIN1110EBZ=y -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4S5XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/adi_eval_adin1110ebz/doc/index.rst b/boards/arm/adi_eval_adin1110ebz/doc/index.rst deleted file mode 100644 index 3bcc3167596..00000000000 --- a/boards/arm/adi_eval_adin1110ebz/doc/index.rst +++ /dev/null @@ -1,183 +0,0 @@ -.. _adi_eval_adin1110ebz: - -ADI EVAL-ADIN1110EVB Evaluation board -##################################### - -Overview -******** - -The EVAL-ADIN1110EBZ is a flexible platform enabling quick evaluation of the ADIN1110, robust, -low power 10BASE-T1L MAC-PHY. It provides 10Mbit per second Single Pair Ethernet (SPE) connections -with devices across 1.7km of cable. - -The evaluation board offers two modes of operation for maximum flexibility. Connected to a PC -via USB port, the full set of ADIN1110 register settings and features such as link quality -monitoring and diagnostics can be accessed over the USB using serial command interface. -The board also provides an Arduino interface. - -Alternatively, the board can operate in stand-alone mode where it is configured by setting hardware -configuration links and switches. On-board LEDs provide status indication. - -The SPI interface provides configuration and data access to the ADIN1110. - -A small prototyping area and test points are provided for experimentation with alternative cable -connection topologies including isolation transformers and/or power coupling inductors. - -.. figure:: img/adi_eval_adin1110ebz.webp - :align: center - :alt: ADI EVAL-ADIN1110EBZ - - ADI EVAL-ADIN1110EBZ (Credit: Analog Devices, Inc.) - -.. important:: - - S201 DIP switches are shipped in Open Alliance SPI mode. The current Zephyr - default board configuration is set to work as "Generic SPI, CRC enabled", - so the S201 DIP switches must be set as ``SPI_CFG0 OFF`` and ``SPI_CFG1 ON``. - An inconsistent S201 DIP switches configuration will halt the boot. - -Hardware -******** - -The ADI EVAL-ADIN1110EBZ hardware features list is available here: - -https://wiki.analog.com/resources/eval/user-guides/eval-adin1110ebz-user-guide - - -Supported Features -================== - -The ADI adi_eval_adin1110ebz board configuration supports the -following hardware features: - -+--------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+==============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+--------------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+--------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+--------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+--------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+--------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+--------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+--------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+--------------+------------+-------------------------------------+ -| ADIN1110 | spi | adin1110 10BASE-T1L mac/phy | -+--------------+------------+-------------------------------------+ -| FT232 | uart | usb-uart | -+--------------+------------+-------------------------------------+ -| ADT7422 | i2c | temperature sensor | -+--------------+------------+-------------------------------------+ -| ISS66WVE4M16 | fmc | 8MB PSRAM | -+--------------+------------+-------------------------------------+ - - -The default configuration can be found in the defconfig file: - - ``boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz_defconfig`` - - -Connections and IOs -=================== - -ADI ADIN1110EBZ evaluation board has 7 GPIO controllers (from A to G). These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -For mode details please refer to `EVAL-ADIN1110EBZ User Guide `_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (UART to FT232) -- UART_4 TX/RX : PA0/PA1 (Arduino Serial) -- I2C1 SCL/SDA : PG14/PG13 (Arduino I2C) -- I2C3 SCL/SDA : PG7/PG8 (Sensor I2C bus) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Simple SPI to nor Flash) -- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 (ADIN1110) -- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (Arduino SPI) -- LD1 : PC13 (Green LED) -- LD2 : PE2 (Red LED) -- LD3 : PE6 (Yellow LED) -- LD4 : PG15 (Blue LED) -- PSRAM : PE0/PE1/PF0-PF15/PG0-PG5/PD11-PD13/PE3/PE4 - PD14/PD15/PD9/PD1/PE7-PE15/PD8-PD10 - - -System Clock ------------- - -EVAL-ADIN1110EBZ System Clock could be driven by an internal or external oscillator, as well as -the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, driven by the -16MHz high speed internal oscillator. - -Serial Port ------------ - -EVAL-ADIN1110EBZ has 2 U(S)ARTs. The Zephyr console output is assigned to UART1 that is connected -to a FT232, so available through Micro USB connector. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -EVAL-ADIN1110EBZ includes an ST-LINK/V2-1 JTAG/SWD 10 or 20 pin connector. This interface is -supported by the openocd version included in Zephyr SDK. - -Flashing an application to Discovery kit ------------------------------------------ - -Connect the EVAL-ADIN1110EBZ to your host computer using the USB port, then run a serial host -program to connect with your ADI board. For example: - -.. code-block:: console - - $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN1110EBZ_AVAS_XXXXXX-if00-port0 - -where XXXXXX is the serial number of the connected device. -Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adi_eval_adin1110ebz - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! adi_eval_adin1110ebz - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adi_eval_adin1110ebz - :maybe-skip-config: - :goals: debug - -.. _EVAL-ADIN1110EBZ evaluation board website: - https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adin1110.html - -.. _EVAL-ADIN1110EBZ board User Guide: - https://wiki.analog.com/resources/eval/user-guides/eval-adin1110ebz-user-guide - -.. _ADIN1110 Datasheet: - https://www.analog.com/media/en/technical-documentation/data-sheets/adin1110.pdf - -.. _STM32L4S5QII3P reference manual: - https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/adi_eval_adin2111ebz/Kconfig.board b/boards/arm/adi_eval_adin2111ebz/Kconfig.board deleted file mode 100644 index f173947c39b..00000000000 --- a/boards/arm/adi_eval_adin2111ebz/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# ADI EVAL-ADIN2111EBZ board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADI_EVAL_ADIN2111EBZ - bool "ADI EVAL-ADIN2111EBZ evaulation board" - depends on SOC_STM32L4S5XX diff --git a/boards/arm/adi_eval_adin2111ebz/Kconfig.defconfig b/boards/arm/adi_eval_adin2111ebz/Kconfig.defconfig deleted file mode 100644 index 41dd579738c..00000000000 --- a/boards/arm/adi_eval_adin2111ebz/Kconfig.defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# ADI EVAL-ADIN2111EBZ board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADI_EVAL_ADIN2111EBZ - -config BOARD - default "adi_eval_adin2111ebz" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -config MDIO_INIT_PRIORITY - default 81 - depends on MDIO - -config PHY_INIT_PRIORITY - default 82 - depends on NET_L2_ETHERNET && ETH_DRIVER - -if NETWORKING - -config NET_L2_ETHERNET - default y - -if ETH_ADIN2111 - -config NET_IF_MAX_IPV4_COUNT - default 2 - -endif # ETH_ADIN2111 - -endif # NETWORKING - -endif # BOARD_ADI_EVAL_ADIN2111EBZ diff --git a/boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz_defconfig b/boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz_defconfig deleted file mode 100644 index f7e4d9c4ab3..00000000000 --- a/boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ADI_EVAL_ADIN2111EBZ=y -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4S5XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/adi_eval_adin2111ebz/doc/index.rst b/boards/arm/adi_eval_adin2111ebz/doc/index.rst deleted file mode 100644 index ac9d33aa285..00000000000 --- a/boards/arm/adi_eval_adin2111ebz/doc/index.rst +++ /dev/null @@ -1,184 +0,0 @@ -.. _adi_eval_adin2111ebz: - -ADI EVAL-ADIN2111EVB Evaluation board -##################################### - -Overview -******** - -The EVAL-ADIN2111EBZ is a flexible platform enabling quick evaluation of the ADIN2111, robust, -low power 10BASE-T1L 2-Port Ethernet switch. The evaluation board provides 2 10BASE-T1L channels -with 10Mbit per second Single Pair Ethernet (SPE) connections reaching up to 1.7km of link distance. - -The ADIN2111 internal switch can be configured in store and forward mode between the two 10BASE-T1L -channels and the SPI host. Cut through mode is also available between Port 1 and Port 2 and can -be used without the need of the SPI host (unmanaged configuration). - -The evaluation board offers two modes of operation for maximum flexibility: Connected to a PC -via USB port, the full set of ADIN2111 register settings and features such as link quality -monitoring and diagnostics can be accessed over the USB using the serial command interface -implemented in the evaluation firmware. - -Alternatively, the board can operate in cut-through mode between Port 1 and Port 2 (unmanaged -configuration without firmware) where the EVAL-ADIN2111EBZ acts as a network switch forwarding -packets between the 2x 10BASE-T1L ports. The 2x links are configured by setting the ADIN2111 -hardware configuration pins jumper and switches. The 2x On-board Activity LEDs provide Link -activity status indication for each port. - -Custom firmware can also be developed and the ADIN2111 driver support package includes simple -project examples to start a custom implementation. - -The SPI interface provides access to the management registers required for the switch configuration, -the 2 PHYs configuration and data exchange between SPI host and ports. - -.. important:: - - S1 DIP switches are shipped in Open Alliance SPI mode. The current Zephyr - default board configuration is set to work as "Generic SPI, CRC enabled", - so the S1 DIP switches must be set as ``SPI_CFG0 OFF and SPI_CFG1 OFF``. - An inconsistent S1 DIP switches configuration will halt the boot. - -.. figure:: img/adi_eval_adin2111ebz.webp - :align: center - :alt: ADI EVAL-ADIN2111EBZ - - ADI EVAL-ADIN2111EBZ (Credit: Analog Devices, Inc.) - -Hardware -******** - -The ADI EVAL-ADIN2111EBZ hardware features list is available here: - -https://wiki.analog.com/resources/eval/user-guides/eval-adin2111ebz-user-guide - - -Supported Features -================== - -The ADI adi_eval_adin2111ebz board configuration supports the -following hardware features: - -+--------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+==============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+--------------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+--------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+--------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+--------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+--------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+--------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+--------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+--------------+------------+-------------------------------------+ -| ADIN2111 | spi | adin2111 10BASE-T1L mac/phy | -+--------------+------------+-------------------------------------+ -| FT232 | uart | usb-uart | -+--------------+------------+-------------------------------------+ - - -The default configuration can be found in the defconfig file: - - ``boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz_defconfig`` - - -Connections and IOs -=================== - -ADI ADIN2111EBZ evaluation board has 7 GPIO controllers (from A to G). -These controllers are responsible for pin muxing, input/output, pull-up, etc. - -For mode details please refer to `EVAL-ADIN2111EBZ User Guide `_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (UART to FT232, console) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (SPI to external nor flash IS25LP128) -- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 (SPI to external ADIN2111) -- LED1 : POWER (Green LED) -- UC_LED1 : PB6 (Blue LED) -- MOD LED1 : PE2 (SR LED) -- MOD LED2 : PE6 (BG LED) -- NET LED1 : PB10 (SR LED) -- NET LED2 : PB11 (BG LED) - - -System Clock ------------- - -EVAL-ADIN2111EBZ System Clock could be driven by an internal or external oscillator, as well as the -main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, driven by the -16MHz high speed internal oscillator. - -Serial Port ------------ - -EVAL-ADIN2111EBZ has 1 U(S)ART. The Zephyr console output is assigned to UART1 that is connected -to a FT232, available through Micro USB connector. Default settings are 115200 8N1. -Same UART1 TX and RX cmos signals are available before the FT232, at P9 connector. - - -Programming and Debugging -************************* - -Flashing -======== - -EVAL-ADIN2111EBZ includes an ST-LINK/V2-1 JTAG/SWD 10 or 20 pin connector. This interface is -supported by the openocd version included in Zephyr SDK. - -Flashing an application to Discovery kit ------------------------------------------ - -Connect the EVAL-ADIN2111EBZ to your host computer using the USB port, then run a serial host -program to connect with your ADI board. For example: - -.. code-block:: console - - $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN2111EBZ_XXXXXX-12-if00-port0 - -where XXXXXX is the serial number of the connected device. -Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adi_eval_adin2111ebz - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! adi_eval_adin2111ebz - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adi_eval_adin2111ebz - :maybe-skip-config: - :goals: debug - -.. _EVAL-ADIN2111EBZ evaluation board website: - https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adin2111.html - -.. _EVAL-ADIN2111EBZ board User Guide: - https://wiki.analog.com/resources/eval/user-guides/eval-adin2111ebz-user-guide - -.. _ADIN2111 Datasheet: - https://www.analog.com/media/en/technical-documentation/data-sheets/adin2111.pdf - -.. _STM32L4S5QII3P reference manual: - https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/adi_sdp_k1/Kconfig.board b/boards/arm/adi_sdp_k1/Kconfig.board deleted file mode 100644 index 8aa4b969d61..00000000000 --- a/boards/arm/adi_sdp_k1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# ADI SDP-K1 board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADI_SDP_K1 - bool "ADI SDP-K1 Controller Board" - depends on SOC_STM32F469XX diff --git a/boards/arm/adi_sdp_k1/Kconfig.defconfig b/boards/arm/adi_sdp_k1/Kconfig.defconfig deleted file mode 100644 index 03e3bd4cdeb..00000000000 --- a/boards/arm/adi_sdp_k1/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# ADI SDP-K1 board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADI_SDP_K1 - -config BOARD - default "adi_sdp_k1" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_ADI_SDP_K1 diff --git a/boards/arm/adi_sdp_k1/doc/index.rst b/boards/arm/adi_sdp_k1/doc/index.rst deleted file mode 100644 index 177f7bf3550..00000000000 --- a/boards/arm/adi_sdp_k1/doc/index.rst +++ /dev/null @@ -1,184 +0,0 @@ -.. _adi_sdp_k1: - -ADI SDP-K1 -########## - -Overview -******** - -The EVAL-SDP-CK1Z (SDP-K1) controller board is a system demonstration platform -(SDP) from Analog Devices designed to connect to evaluation shields containing -ADI components. - -- STM32 microcontroller in BGA216 package -- USB 2.0 device with USB-C connector -- USB debug interface supporting CMSIS-DAP through a NXP Freescale - microcontroller -- Flexible board power supply - - USB VBUS 5 V max. 500 mA - - 5.5mm DC power jack 7 - 12 V min. 300 mA - - VIN from Arduino* compatible connectors - - VIN from 120-pin connector 5 V min. 300 mA -- 3 color LEDs (green, orange, red) and 1 status LED -- One push-buttons: RESET -- 16MB SDRAM -- Arduino UNO and 120-pin SDP connectors - -.. figure:: img/adi_sdp_k1.webp - :align: center - :alt: ADI SDP-K1 - - ADI SDP-K1 (Credit: Analog Devices, Inc.) - -More information about the board can be found on the `ADI SDP-K1 website`_. - -Hardware -******** - -ADI SDP-K1 provides the following hardware components: - -- STM32F469NIH6 in BGA216 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 180 MHz max CPU frequency -- VDD of 1.8 V or 3.3 V -- 2 MB Flash -- 384 KB SRAM -- GPIO with external interrupt capability -- LCD parallel interface, 8080/6800 modes -- LCD TFT controller supporting up to XGA resolution -- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (8) -- I2C (3) -- SPI (6) -- 1xSAI (serial audio interface) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F469NI can be found here: - - `STM32F469NI product page`_ - - `STM32F469 reference manual`_ - -Supported Features -================== - -The Zephyr stm32f469i_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/adi_sdp_k1/adi_sdp_k1_defconfig`` - -Pin Mapping -=========== - -For more details please refer to `EVAL-SDP-CK1Z User Guide`_. - -Arduino UNO headers -------------------- - -.. figure:: img/adi_sdp_k1_arduino.webp - :align: center - :alt: ADI SDP-K1 Arduino UNO headers pinout - - ADI SDP-K1 (Credit: Analog Devices, Inc.) - -120-pin SDP connector ---------------------- - -.. figure:: img/adi_sdp_k1_120pin.webp - :align: center - :alt: ADI SDP-K1 120-pin SDP connector pinout - - ADI SDP-K1 (Credit: Analog Devices, Inc.) - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_5 TX/RX : P2 (DAPLink USB-C) -- UART_5 TX/RX : P8 (DAPLink two position through hole) -- LED1 : DS6 (Red) -- LED2 : DS5 (Orange) -- LED3 : DS4 (Green) -- LED4 : DS4 (Status) - -Programming and Debugging -************************* - -The ADI SDP-K1 be programmed over USB using the DAPLink firmware running on an -embedded NXP Freescale microcontroller or a 10-pin ``DEBUG`` header connected -to a STLINK debugger. - -DAPLink exposes a storage device, as well as USB HID and CDC Endpoints, to the -host. For more details please refer to the `Official DAPLink website`_. - -Flashing -======== - -Flashing an application with a STLINK debugger ----------------------------------------------- - -First, connect the STLINK debugger to your host computer using the Micro-USB port. -Then attach the debugger to the 10-pin ``DEBUG`` header on the SDP-K1. Finally -connect the SDP-K1 to your host computer using the USB-C port. - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/serial/by-id/usb-ARM_DAPLink_CMSIS-DAP_<...> - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adi_sdp_k1 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! adi_sdp_k1 - -Debugging -========= - -.. _ADI SDP-K1 website: - https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/sdp-k1.html - -.. _EVAL-SDP-CK1Z User Guide: - https://www.analog.com/media/en/technical-documentation/user-guides/EVAL-SDP-CK1Z-UG-1539.pdf - -.. _STM32F469NI product page: - https://www.st.com/en/microcontrollers/stm32f469ni.html - -.. _STM32F469 reference manual: - https://www.st.com/resource/en/reference_manual/dm00127514.pdf - -.. _Official DAPLink website: - https://daplink.io/ diff --git a/boards/arm/am62x_m4/Kconfig.board b/boards/arm/am62x_m4/Kconfig.board deleted file mode 100644 index 963b5c6133d..00000000000 --- a/boards/arm/am62x_m4/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_AM62X_M4_SK - bool "TI AM62x M4 Starter Kit (SK) Evaluation Module (EVM)" - depends on SOC_SERIES_AM62X_M4 - -config BOARD_AM62X_M4_PHYBOARD_LYRA - bool "PHYTEC AM62x M4 phyBOARD-Lyra" - depends on SOC_SERIES_AM62X_M4 diff --git a/boards/arm/am62x_m4/Kconfig.defconfig b/boards/arm/am62x_m4/Kconfig.defconfig deleted file mode 100644 index 7b6182aa040..00000000000 --- a/boards/arm/am62x_m4/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_AM62X_M4_SK - -config BOARD - default "am62x_m4_sk" - -endif # BOARD_AM62X_M4_SK - -if BOARD_AM62X_M4_PHYBOARD_LYRA - -config BOARD - default "am62x_m4_phyboard_lyra" - -endif # BOARD_AM62X_M4_PHYBOARD_LYRA diff --git a/boards/arm/am62x_m4/am62x_m4_phyboard_lyra.yaml b/boards/arm/am62x_m4/am62x_m4_phyboard_lyra.yaml deleted file mode 100644 index b77fb449347..00000000000 --- a/boards/arm/am62x_m4/am62x_m4_phyboard_lyra.yaml +++ /dev/null @@ -1,8 +0,0 @@ -identifier: am62x_m4_phyboard_lyra -name: PHYTEC AM62x M4 phyBOARD-Lyra -type: mcu -arch: arm -toolchain: - - zephyr -ram: 192 -vendor: phytec diff --git a/boards/arm/am62x_m4/am62x_m4_phyboard_lyra_defconfig b/boards/arm/am62x_m4/am62x_m4_phyboard_lyra_defconfig deleted file mode 100644 index 822222a8900..00000000000 --- a/boards/arm/am62x_m4/am62x_m4_phyboard_lyra_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# PHYTEC AM62x M4 phyBOARD-Lyra -# -# Copyright (C) 2023 PHYTEC Messtechnik GmbH -# Author: Daniel Schultz -# -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_AM62X_M4=y -CONFIG_SOC_AM62x_M4=y -CONFIG_BOARD_AM62X_M4_PHYBOARD_LYRA=y -CONFIG_CORTEX_M_SYSTICK=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Enable Pinctrl -CONFIG_PINCTRL=y - -# Serial Driver -CONFIG_SERIAL=y - -# GPIO Driver -CONFIG_GPIO=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/am62x_m4/am62x_m4_sk.yaml b/boards/arm/am62x_m4/am62x_m4_sk.yaml deleted file mode 100644 index ef07d5a99d9..00000000000 --- a/boards/arm/am62x_m4/am62x_m4_sk.yaml +++ /dev/null @@ -1,8 +0,0 @@ -identifier: am62x_m4_sk -name: TI AM62X M4 Starter Kit (SK) -type: mcu -arch: arm -toolchain: - - zephyr -ram: 192 -vendor: ti diff --git a/boards/arm/am62x_m4/am62x_m4_sk_defconfig b/boards/arm/am62x_m4/am62x_m4_sk_defconfig deleted file mode 100644 index 561463888c0..00000000000 --- a/boards/arm/am62x_m4/am62x_m4_sk_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_AM62X_M4=y -CONFIG_SOC_AM62x_M4=y -CONFIG_BOARD_AM62X_M4_SK=y -CONFIG_CORTEX_M_SYSTICK=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Enable Pinctrl -CONFIG_PINCTRL=y - -# Serial Driver -CONFIG_SERIAL=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/am62x_m4/doc/am62x_m4_phyboard_lyra.rst b/boards/arm/am62x_m4/doc/am62x_m4_phyboard_lyra.rst deleted file mode 100644 index 189710b5e48..00000000000 --- a/boards/arm/am62x_m4/doc/am62x_m4_phyboard_lyra.rst +++ /dev/null @@ -1,148 +0,0 @@ -.. _am62x_m4_phyboard_lyra: - -AM62x phyBOARD-Lyra M4F Core -############################ - -Overview -******** - -The AM62x phyBOARD-Lyra board configuration is used by Zephyr applications -that run on the TI AM62x platform. The board configuration provides support -for the ARM Cortex-M4F MCU core and the following features: - -- Nested Vector Interrupt Controller (NVIC) -- System Tick System Clock (SYSTICK) - -The board configuration also enables support for the semihosting debugging console. - -See the `PHYTEC AM62x Product Page`_ for details. - -.. figure:: img/phyCORE-AM62x_Lyra_frontside.webp - :align: center - :alt: AM62x phyBOARD-Lyra - - PHYTEC phyBOARD-Lyra with the phyCORE-AM62x SoM - -Hardware -******** -The AM62x phyBOARD-Lyra kit features the AM62x SoC, which is composed of a -quad Cortex-A53 cluster and a single Cortex-M4 core in the MCU domain. Zephyr -is ported to run on the M4F core and the following listed hardware -specifications are used: - -- Low-power ARM Cortex-M4F -- Memory - - - 256KB of SRAM - - 2GB of DDR4 - -- Debug - - - XDS110 based JTAG - -Supported Features -================== - -The am62x_m4_phyboard_lyra configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINCTRL | on-chip | pinctrl | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 400 MHz. - -DDR RAM -------- - -The board has 2GB of DDR RAM available. This board configuration -allocates Zephyr 4kB of RAM (only for resource table: 0x9CC00000 to 0x9CC00400). - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -MCU domain UART (MCU_UART0). - -SD Card -******* - -Download PHYTEC's official `WIC`_ as well as `BMAP`_ and flash the WIC file with -an etching software onto an SD-card. This will boot Linux on the A53 application -cores of the SoM. These cores will then load the zephyr binary on the M4 core -using remoteproc. - -The default configuration can be found in the defconfig file: - -.. code-block:: console - - boards/arm/am62x_m4/am62x_m4_phyboard_lyra_defconfig - -Flashing -******** - -The Linux running on the A53 uses the remoteproc framework to manage the M4F co-processor. -Therefore, the testing requires the binary to be copied to the SD card to allow the A53 cores to -load it while booting using remoteproc. - -To test the M4F core, we build the `hello_world` sample with the following command. - -.. code-block:: console - - # From the root of the Zephyr repository - west build -p -b am62x_m4_phyboard_lyra samples/hello_world - -This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. - -We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. - -.. code-block:: console - - # Mount the SD card at sdcard for example - sudo mount /dev/sdX sdcard - # copy the elf to the /lib/firmware directory - sudo cp --remove-destination zephyr.elf sdcard/lib/firmware/am62-mcu-m4f0_0-fw - -The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot. - -To allow the board to boot using the SD card, set the boot pins to the SD Card boot mode. Refer to `phyBOARD SD Card Booting Essentials`_. - -After changing the boot mode, stop in U-Boot to enable the M4F co-processor. - -.. code-block:: console - - setenv overlays k3-am62-phyboard-lyra-rpmsg.dtbo - # Save the overlays variable permanently - saveenv - boot - -The board should boot into Linux and the binary will run and print Hello world to the MCU_UART0 -port. - - - -.. _PHYTEC AM62x Product Page: - https://www.phytec.com/product/phycore-am62x/ - -.. _WIC: - https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz - -.. _BMAP: - https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.bmap - -.. _phyBOARD SD Card Booting Essentials: - https://docs.phytec.com/latest/phycore-am62x/bootingessentials/sdcard.html diff --git a/boards/arm/am62x_m4/doc/am62x_m4_sk.rst b/boards/arm/am62x_m4/doc/am62x_m4_sk.rst deleted file mode 100644 index e789c33d5f8..00000000000 --- a/boards/arm/am62x_m4/doc/am62x_m4_sk.rst +++ /dev/null @@ -1,141 +0,0 @@ -.. _am62x_m4_sk: - -AM62x-SK M4F Core -################# - -Overview -******** - -The AM62x-SK board configuration is used by Zephyr applications that run on -the TI AM62x platform. The board configuration provides support for the ARM -Cortex-M4F MCU core and the following features: - -- Nested Vector Interrupt Controller (NVIC) -- System Tick System Clock (SYSTICK) - -The board configuration also enables support for the semihosting debugging console. - -See the `TI AM62X Product Page`_ for details. - -.. figure:: img/sk_am62_angled.webp - :align: center - :alt: TI AM62x-SK EVM - - Texas Instruments AM62x SK EVM - -Hardware -******** -The AM62x-SK EVM features the AM62x SoC, which is composed of a quad Cortex-A53 -cluster and a single Cortex-M4 core in the MCU domain. Zephyr is ported to run on -the M4F core and the following listed hardware specifications are used: - -- Low-power ARM Cortex-M4F -- Memory - - - 256KB of SRAM - - 2GB of DDR4 - -- Debug - - - XDS110 based JTAG - -Supported Features -================== - -The am62x_m4_sk configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINCTRL | on-chip | pinctrl | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 400 MHz. - -DDR RAM -------- - -The board has 2GB of DDR RAM available. This board configuration -allocates Zephyr 4kB of RAM (only for resource table: 0x9CC00000 to 0x9CC00400). - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -MCU domain UART (MCU_UART0). - -SD Card -******* - -Download TI's official `WIC`_ and flash the WIC file with an etching software -onto an SD-card. This will boot Linux on the A53 application cores of the EVM. -These cores will then load the zephyr binary on the M4 core using remoteproc. - -The default configuration can be found in the defconfig file: - -.. code-block:: console - - boards/arm/am62x_m4/am62x_m4_sk_defconfig - -Flashing -******** - -The board can using remoteproc, and uses the OpenAMP resource table to accomplish this. - -The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. - -To test the M4F core, we build the `hello_world` sample with the following command. - -.. code-block:: console - - # From the root of the Zephyr repository - west build -p -b am62x_m4_sk samples/hello_world - -This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. - -We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. - -.. code-block:: console - - # Mount the SD card at sdcard for example - sudo mount /dev/sdX sdcard - # copy the elf to the /lib/firmware directory - sudo cp --remove-destination zephyr.elf sdcard/lib/firmware/am62-mcu-m4f0_0-fw - -The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot. - -To allow the board to boot using the SD card, set the boot pins to the SD Card boot mode. Refer to `EVM Setup Page`_. - -After changing the boot mode, the board should go through the boot sequence on powering up. -The binary will run and print Hello world to the MCU_UART0 port. - -References -********** - -AM62x SK EVM TRM: - https://www.ti.com/lit/ug/spruiv7/spruiv7.pdf - -.. _TI AM62X Product Page: - https://www.ti.com/product/AM625 - -.. _WIC: - https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-PvdSyIiioq/08.06.00.42/tisdk-default-image-am62xx-evm.wic.xz - -.. _AM62x SK EVM TRM: - https://www.ti.com/lit/ug/spruiv7/spruiv7.pdf - -.. _EVM Setup Page: - https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/08_06_00_18/exports/docs/api_guide_am62x/EVM_SETUP_PAGE.html diff --git a/boards/arm/am62x_m4/doc/index.rst b/boards/arm/am62x_m4/doc/index.rst deleted file mode 100644 index c542113e962..00000000000 --- a/boards/arm/am62x_m4/doc/index.rst +++ /dev/null @@ -1,38 +0,0 @@ -.. _am62x_m4: - -AM62x M4F Core -############## - -Overview -******** - -The Texas Instrument AM62x SoC contains a quad Cortex-A53 cluster and a single -Cortex-M4F core in the MCU domain. This chapter describes all boards with support -for the M4F subsystem. - -Currently the following hardware platforms are supported: - -.. toctree:: - :maxdepth: 1 - - am62x_m4_sk.rst - am62x_m4_phyboard_lyra.rst - -Supported Features -================== - -The AM62x M4F platform supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINCTRL | on-chip | pinctrl | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. diff --git a/boards/arm/apollo4p_blue_kxr_evb/Kconfig.board b/boards/arm/apollo4p_blue_kxr_evb/Kconfig.board deleted file mode 100644 index 0ae2283f97d..00000000000 --- a/boards/arm/apollo4p_blue_kxr_evb/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Ambiq Micro Inc. - -config BOARD_APOLLO4P_BLUE_KXR_EVB - bool "Ambiq Apollo4 Blue Plus KXR Evaluation Board" - depends on SOC_APOLLO4P_BLUE diff --git a/boards/arm/apollo4p_blue_kxr_evb/Kconfig.defconfig b/boards/arm/apollo4p_blue_kxr_evb/Kconfig.defconfig deleted file mode 100644 index 1edc7b5581b..00000000000 --- a/boards/arm/apollo4p_blue_kxr_evb/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Ambiq Micro Inc. - -config BOARD - default "apollo4p_blue_kxr_evb" - depends on BOARD_APOLLO4P_BLUE_KXR_EVB - -if BT - -config MAIN_STACK_SIZE - default 2048 - -choice BT_HCI_BUS_TYPE - default BT_AMBIQ_HCI -endchoice - -config BT_BUF_ACL_TX_COUNT - default 14 - -config BT_BUF_CMD_TX_SIZE - default 255 - -config BT_BUF_EVT_RX_SIZE - default 255 - -config BT_BUF_ACL_TX_SIZE - default 251 - -config BT_BUF_ACL_RX_SIZE - default 251 - -# L2CAP SDU/PDU TX MTU -# BT_L2CAP_RX_MTU = CONFIG_BT_BUF_ACL_RX_SIZE - BT_L2CAP_HDR_SIZE -config BT_L2CAP_TX_MTU - default 247 - -endif # BT diff --git a/boards/arm/apollo4p_blue_kxr_evb/doc/index.rst b/boards/arm/apollo4p_blue_kxr_evb/doc/index.rst deleted file mode 100644 index 75aa74ac34e..00000000000 --- a/boards/arm/apollo4p_blue_kxr_evb/doc/index.rst +++ /dev/null @@ -1,110 +0,0 @@ -.. _apollo4p_blue_kxr_evb: - -Ambiq Apollo4 Blue Plus KXR EVB -############################### - -Apollo4 Blue Plus KXR EVB is a board by Ambiq featuring their ultra-low power Apollo4 Blue Plus SoC. - -.. image:: ./apollo4-blue-plus-kxr-soc-eval-board.jpg - :align: center - :alt: Apollo4 Blue Plus KXR EVB - -Hardware -******** - -- Apollo4 Blue Plus SoC with upto 192 MHz operating frequency -- ARM® Cortex® M4F core -- 64 kB 2-way Associative/Direct-Mapped Cache per core -- Up to 2 MB of non-volatile memory (NVM) for code/data -- Up to 2.75 MB of low leakage / low power RAM for code/data -- 384 kB Tightly Coupled RAM -- 384 kB Extended RAM -- Bluetooth 5.1 Low Energy - -For more information about the Apollo4 Blue Plus SoC and Apollo4 Blue Plus KXR EVB board: - -- `Apollo4 Blue Plus Website`_ -- `Apollo4 Blue Plus Datasheet`_ -- `Apollo4 Blue Plus KXR EVB Website`_ - -Supported Features -================== - -The Apollo4 Blue Plus KXR EVB board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| STIMER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | bluetooth | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig``. - -Programming and Debugging -========================= - -Flashing an application ------------------------ - -Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application, then flash it to the device: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: apollo4p_blue_kxr_evb - :goals: flash - -.. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module - to be installed on you host computer. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! apollo4p_blue_kxr_evb - -.. _Apollo4 Blue Plus Website: - https://ambiq.com/apollo4-blue-plus/ - -.. _Apollo4 Blue Plus Datasheet: - https://contentportal.ambiq.com/documents/20123/388410/Apollo4-Blue-Plus-SoC-Datasheet.pdf - -.. _Apollo4 Blue Plus KXR EVB Website: - https://www.ambiq.top/en/apollo4-blue-plus-kxr-soc-eval-board - -.. _SEGGER J-Link software: - https://www.segger.com/downloads/jlink - -.. _pylink: - https://github.com/Square/pylink diff --git a/boards/arm/apollo4p_evb/Kconfig.board b/boards/arm/apollo4p_evb/Kconfig.board deleted file mode 100644 index f6c5256a98d..00000000000 --- a/boards/arm/apollo4p_evb/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -config BOARD_APOLLO4P_EVB - bool "Ambiq Apollo4 Plus Evaluation Board" - depends on SOC_APOLLO4P diff --git a/boards/arm/apollo4p_evb/Kconfig.defconfig b/boards/arm/apollo4p_evb/Kconfig.defconfig deleted file mode 100644 index 0e3d55bc8f8..00000000000 --- a/boards/arm/apollo4p_evb/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -config BOARD - default "apollo4p_evb" - depends on BOARD_APOLLO4P_EVB diff --git a/boards/arm/apollo4p_evb/doc/index.rst b/boards/arm/apollo4p_evb/doc/index.rst deleted file mode 100644 index 42f0f360329..00000000000 --- a/boards/arm/apollo4p_evb/doc/index.rst +++ /dev/null @@ -1,105 +0,0 @@ -.. _apollo4p_evb: - -Ambiq Apollo4P EVB -################## - -Apollo4P EVB is a board by Ambiq featuring their ultra-low power Apollo4 Plus SoC. - -.. image:: ./apollo4-plus-soc-eval-board.jpg - :align: center - :alt: Apollo4P EVB - -Hardware -******** - -- Apollo4 Plus SoC with upto 192 MHz operating frequency -- ARM® Cortex® M4F core -- 64 kB 2-way Associative/Direct-Mapped Cache per core -- Up to 2 MB of non-volatile memory (NVM) for code/data -- Up to 2.75 MB of low leakage / low power RAM for code/data -- 384 kB Tightly Coupled RAM -- 384 kB Extended RAM - -For more information about the Apollo4 Plus SoC and Apollo4P EVB board: - -- `Apollo4 Plus Website`_ -- `Apollo4 Plus Datasheet`_ -- `Apollo4P EVB Website`_ - -Supported Features -================== - -The Apollo4P EVB board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| STIMER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/apollo4p_evb/apollo4p_evb_defconfig``. - -Programming and Debugging -========================= - -Flashing an application ------------------------ - -Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application, then flash it to the device: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: apollo4p_evb - :goals: flash - -.. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module - to be installed on you host computer. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! apollo4p_evb - -.. _Apollo4 Plus Website: - https://ambiq.com/apollo4-plus/ - -.. _Apollo4 Plus Datasheet: - https://contentportal.ambiq.com/documents/20123/388415/Apollo4-Plus-SoC-Datasheet.pdf - -.. _Apollo4P EVB Website: - https://www.ambiq.top/en/apollo4-plus-soc-eval-board - -.. _SEGGER J-Link software: - https://www.segger.com/downloads/jlink - -.. _pylink: - https://github.com/Square/pylink diff --git a/boards/arm/arduino_due/Kconfig.board b/boards/arm/arduino_due/Kconfig.board deleted file mode 100644 index 8e0a7ae81b0..00000000000 --- a/boards/arm/arduino_due/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Due Board configuration - -# Copyright (c) 2017 Justin Watson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_DUE - bool "Arduino Due Board" - depends on SOC_PART_NUMBER_SAM3X8E diff --git a/boards/arm/arduino_due/Kconfig.defconfig b/boards/arm/arduino_due/Kconfig.defconfig deleted file mode 100644 index 13c6fdf5722..00000000000 --- a/boards/arm/arduino_due/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Arduino Due Board configuration - -# Copyright (c) 2017 Justin Watson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_DUE - -config BOARD - default "arduino_due" - -endif # BOARD_ARDUINO_DUE diff --git a/boards/arm/arduino_due/arduino_due_defconfig b/boards/arm/arduino_due/arduino_due_defconfig deleted file mode 100644 index 32fa49bd002..00000000000 --- a/boards/arm/arduino_due/arduino_due_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAM3X=y -CONFIG_SOC_PART_NUMBER_SAM3X8E=y -CONFIG_BOARD_ARDUINO_DUE=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/arduino_due/doc/index.rst b/boards/arm/arduino_due/doc/index.rst deleted file mode 100644 index cbb5ce62ca5..00000000000 --- a/boards/arm/arduino_due/doc/index.rst +++ /dev/null @@ -1,214 +0,0 @@ -.. _arduino_due: - -Arduino Due -########### - -Overview -******** - -The arduino_due board configuration is used by Zephyr applications -that run on the Arduino Due board. It provides support for the Atmel -SAM3X8E ARM Cortex-M3 CPU and the following devices: - -* Nested Vectored Interrupt Controller (NVIC) - -* System Tick System Clock (SYSTICK) - -* Serial Port over USB (ATMEL_SAM3) - -More information about the board can be found at the `Arduino Due website`_. -The `Atmel SAM3X8E Datasheet`_ has the information and the datasheet about -the processor. - -.. note:: - This configuration is not supported by Arduino. - -.. image:: img/arduino_due.jpg - :align: center - :alt: Arduino Due - -Hardware -******** -Supported Features -================== - -The arduino_due board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features are not currently supported by the Zephyr kernel. -See `Arduino Due website`_ and `Atmel SAM3X8E Datasheet`_ for a complete -list of Arduino Due board hardware features. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/arduino_due/arduino_due_defconfig`. - -.. note:: - For I2C, pull-up resistors are required for using SCL1 and SDA1 (near IO13). - -Interrupt Controller -==================== - -There are 15 fixed exceptions including exceptions 12 (debug monitor) and 15 -(SYSTICK) that behave more as interrupts than exceptions. In addition, there can -be a variable number of IRQs. Exceptions 7-10 and 13 are reserved. They don't -need handlers. - -A Cortex-M3/4-based board uses vectored exceptions. This means each exception -calls a handler directly from the vector table. - -Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here -identifies the handlers used for each exception. - -+------+------------+----------------+-----------------------+ -| Exc# | Name | Remarks | Used by Zephyr Kernel | -+======+============+================+=======================+ -| 1 | Reset | | system initialization | -+------+------------+----------------+-----------------------+ -| 2 | NMI | | system fatal error | -+------+------------+----------------+-----------------------+ -| 3 | Hard fault | | system fatal error | -+------+------------+----------------+-----------------------+ -| 4 | MemManage | MPU fault | system fatal error | -+------+------------+----------------+-----------------------+ -| 5 | Bus | | system fatal error | -+------+------------+----------------+-----------------------+ -| 6 | Usage | undefined | system fatal error | -| | fault | instruction, | | -| | | or switch | | -| | | attempt to ARM | | -| | | mode | | -+------+------------+----------------+-----------------------+ -| 11 | SVC | | system calls, kernel | -| | | | run-time exceptions, | -| | | | and IRQ offloading | -+------+------------+----------------+-----------------------+ -| 12 | Debug | | system fatal error | -| | monitor | | | -+------+------------+----------------+-----------------------+ -| 14 | PendSV | | context switch | -+------+------------+----------------+-----------------------+ -| 15 | SYSTICK | | system clock | -+------+------------+----------------+-----------------------+ - -.. note:: - After a reset, all exceptions have a priority of 0. Interrupts cannot run - at priority 0 for the interrupt locking mechanism and exception handling - to function properly. - -System Clock -============ - -Arduino Due has two external oscillators/resonators. The slow clock is -32.768 kHz, and the main clock is 12 MHz. The processor can set up PLL to drive -the master clock, which can be set as high as 84 MHz. - -Serial Port -=========== - -The Atmel SAM3X8E processor has a single UART that is used by the SAM-BA -bootloader. This UART has only two wires for RX/TX and does not have flow -control (CTS/RTS) or FIFO. The RX/TX pins are connected to the ATmega16U2, -which provides USB-to-TTL serial function. The Zephyr console output, by -default, is utilizing this controller. - - -Programming and Debugging -************************* - -Flashing -======== - -BOSSA Tool ----------- - -Flashing the Zephyr kernel onto Arduino Due requires the `bossa tool`_. - -There are GUI and command line versions of the bossa tool. The following -section provides the steps to build the command line version. Please -refer to the bossa tool's README file on how to build the GUI version. - -To build the bossa tool, follow these steps: - -#. Checkout the bossa tool's code from the repository. - - .. code-block:: console - - $ git clone https://github.com/shumatech/BOSSA.git - $ cd BOSSA - -#. Checkout the arduino branch. The code on the master branch does not - work with Arduino Due. - - .. code-block:: console - - $ git checkout arduino - -#. Build the command line version of the bossa tool. - - .. code-block:: console - - $ make bin/bossac - -#. The resulting binary is available at :file:`bin/bossac`. - - -Flashing an Application to Arduino Due --------------------------------------- - -Applications for the ``arduino_due`` board configuration can be built -and flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. After -building the application, press the Reset button before running the -flash command, so the board will boot into the SAM-BA bootloader and -be prepared to receive the new program. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_due - :goals: build flash - -After flashing the application, run your favorite terminal program to -listen for output. For example, under Linux, the terminal should be -:code:`/dev/ttyACM0`. For example: - -.. code-block:: console - - $ sudo minicom -D /dev/ttyACM0 -o - -The -o option tells minicom not to send the modem initialization -string. - -Now press the Reset button and you should see "Hello World! arduino_due" in your terminal. - -.. note:: - Make sure your terminal program is closed before flashing the binary image, - or it will interfere with the flashing process. - -References -********** - -.. _Arduino Due website: https://www.arduino.cc/en/Main/ArduinoBoardDue - -.. _Atmel SAM3X8E Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf - -.. _bossa tool: https://github.com/shumatech/BOSSA - -.. _bossa arduino branch: https://github.com/shumatech/BOSSA/tree/arduino diff --git a/boards/arm/arduino_giga_r1/Kconfig.board b/boards/arm/arduino_giga_r1/Kconfig.board deleted file mode 100644 index c810f6f31fc..00000000000 --- a/boards/arm/arduino_giga_r1/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright 2023 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_GIGA_R1_M7 - bool "Arduino GIGA R1 WiFi Board (M7)" - depends on SOC_STM32H747XX - select CPU_CORTEX_M7 - -config BOARD_ARDUINO_GIGA_R1_M4 - bool "Arduino GIGA R1 WiFi Board (M4)" - depends on SOC_STM32H747XX - select CPU_CORTEX_M4 diff --git a/boards/arm/arduino_giga_r1/Kconfig.defconfig b/boards/arm/arduino_giga_r1/Kconfig.defconfig deleted file mode 100644 index e72fb499055..00000000000 --- a/boards/arm/arduino_giga_r1/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright 2023 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_GIGA_R1_M7 || BOARD_ARDUINO_GIGA_R1_M4 - -config BOARD - default "arduino_giga_r1_m7" if BOARD_ARDUINO_GIGA_R1_M7 - default "arduino_giga_r1_m4" if BOARD_ARDUINO_GIGA_R1_M4 - -if BT - -choice AIROC_PART - default CYW4343W -endchoice - -choice CYW4343W_MODULE - default CYW4343W_MURATA_1DX -endchoice - -endif # BT - -endif # BOARD_ARDUINO_GIGA_R1_M7 || BOARD_ARDUINO_GIGA_R1_M4 diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m4.yaml b/boards/arm/arduino_giga_r1/arduino_giga_r1_m4.yaml deleted file mode 100644 index 58b71369e12..00000000000 --- a/boards/arm/arduino_giga_r1/arduino_giga_r1_m4.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: arduino_giga_r1_m4 -name: Arduino GIGA R1 WiFi (M4) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 288 -flash: 1024 -supported: - - arduino_gpio - - gpio -testing: - ignore_tags: - - mpu - - nfc - - net -vendor: arduino diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m4_defconfig b/boards/arm/arduino_giga_r1/arduino_giga_r1_m4_defconfig deleted file mode 100644 index 1ab438cb15a..00000000000 --- a/boards/arm/arduino_giga_r1/arduino_giga_r1_m4_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2023 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_ARDUINO_GIGA_R1_M4=y - -# Enable GPIO -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable uart driver -CONFIG_SERIAL=y - -# Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.yaml b/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.yaml deleted file mode 100644 index 2e844a14804..00000000000 --- a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: arduino_giga_r1_m7 -name: Arduino GIGA R1 WiFi (M7) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 512 -flash: 1024 -supported: - - arduino_gpio - - gpio - - arduino_spi - - spi - - memc - - usb_cdc - - usb_device -vendor: arduino diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7_defconfig b/boards/arm/arduino_giga_r1/arduino_giga_r1_m7_defconfig deleted file mode 100644 index 8f4491908e6..00000000000 --- a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# Copyright 2023 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_ARDUINO_GIGA_R1_M7=y - -# Disable the internal SMPS regulator -CONFIG_POWER_SUPPLY_DIRECT_SMPS=n - -# Enable GPIO -CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable uart driver -CONFIG_SERIAL=y - -# Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable pin controller -CONFIG_PINCTRL=y - -# Use zephyr,code-partition as flash offset -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/arduino_giga_r1/board.cmake b/boards/arm/arduino_giga_r1/board.cmake deleted file mode 100644 index 849f9f933f1..00000000000 --- a/boards/arm/arduino_giga_r1/board.cmake +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_ARDUINO_GIGA_R1_M7) -board_runner_args(jlink "--device=STM32H747XI_M7" "--speed=4000") -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_arduino_giga_r1_m7.cfg") -board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) -elseif(CONFIG_BOARD_ARDUINO_GIGA_R1_M4) -board_runner_args(jlink "--device=STM32H747XI_M4" "--speed=4000") -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_arduino_giga_r1_m4.cfg") -board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) -endif() -board_runner_args(dfu-util "--pid=2341:0366" "--alt=0" "--dfuse") -board_runner_args(blackmagicprobe "--connect-rst") - -include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) -include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/arduino_giga_r1/doc/index.rst b/boards/arm/arduino_giga_r1/doc/index.rst deleted file mode 100644 index 2e2b03917cc..00000000000 --- a/boards/arm/arduino_giga_r1/doc/index.rst +++ /dev/null @@ -1,186 +0,0 @@ -.. _arduino_giga_r1_board: - -Arduino GIGA R1 WiFi -#################### - -Overview -******** - -Arduino GIGA R1 WiFi is a development board by Arduino based on the -STM32H747XI, a dual core ARM Cortex-M7 + Cortex-M4 MCU, with 2MBytes of Flash -memory and 1MB SRAM. - -The board features: - -- RGB LED -- Reset and Boot buttons -- USB-C device -- USB Host -- 16MB external QSPI flash -- 8MB external SDRAM -- Murata Type 1DX Bluetooth + WiFi module (CYW4343W based) -- Audio jack -- ATECC608A secure element - -.. image:: img/arduino_giga_r1.jpg - :align: center - :alt: Arduino GIGA R1 WiFi - -More information about the board, including the datasheet, pinout and -schematics, can be found at the `Arduino GIGA website`_. - -More information about STM32H747XIH6 can be found here: - -- `STM32H747XI on www.st.com`_ -- `STM32H747xx reference manual`_ -- `STM32H747xx datasheet`_ - -Supported Features -================== - -The current Zephyr ``arduino_giga_r1_m7`` board configuration supports the -following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| QSPI | on-chip | QSPI flash | -+-----------+------------+-------------------------------------+ -| RADIO | Murata 1DX | WiFi and Bluetooth module | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr port. - -Fetch Binary Blobs -****************** - -The board Bluetooth/WiFi module requires fetching some binary blob files, to do -that run the command: - -.. code-block:: console - - west blobs fetch hal_infineon - -.. note:: Only Bluetooth functionality is currently supported. - -Resources sharing -================= - -The dual core nature of STM32H747 SoC requires sharing HW resources between the -two cores. This is done in 3 ways: - -- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only - has access to bus clock activation and deactivation. -- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in - devicetree before compilation. The user must ensure peripherals are not assigned - to both cores at the same time. -- **Run time protection**: Interrupt-controller and GPIO configurations could be - accessed by both cores at run time. Accesses are protected by a hardware semaphore - to avoid potential concurrent access issues. - -Programming and Debugging -************************* - -Applications for the ``arduino_giga_r1`` board should be built per core target, -using either ``arduino_giga_r1_m7`` or ``arduino_giga_r1_m4`` as the target. - -See :ref:`build_an_application` for more information about application builds. - -Flashing -======== - -This board can be flashed either using dfu-util, or with an external debugging -probe, such as a J-Link or Black Magic Probe, connected to the on board MIPI-10 -SWD port marked as "JTAG". - -.. note:: - - The board ships with a custom Arduino bootloader programmed in the first - flash page that can be triggered by double clicking the ``RST`` button. This - bootloader is USB-DFU compatible and supports programming both the internal - and external flash and is the one used by ``west flash`` by default. The - internal STM32 ROM bootloader can also be used by pressing ``RST`` while - holding the ``BOOT0`` button, this also supports USB-DFU but can only - program the internal flash and can overwrite the Arduino bootloader. More - details can be found in the "Boot0" section of the `Arduino GIGA Cheat - Sheet`_. - -First, connect the Arduino GIGA R1 board to your host computer using the USB -port to prepare it for flashing. Double click the ``RST`` button to put the -board into the Arduino Bootloader mode. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_giga_r1_m7 - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arduino_giga_r1_m7 - -Similarly, you can build and flash samples on the M4 target. - -Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: arduino_giga_r1_m4 - :goals: build flash - -Debugging -========= - -Debugging is supported by using ``west debug`` with an external probe such as a -J-Link or Black Magic Probe, connected to the on board MIPI-10 SWD port marked -as "JTAG". For example:: - - west debug -r jlink - -.. _Arduino GIGA website: - https://docs.arduino.cc/hardware/giga-r1-wifi - -.. _Arduino GIGA Cheat Sheet: - https://docs.arduino.cc/tutorials/giga-r1-wifi/cheat-sheet - -.. _STM32H747XI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html - -.. _STM32H747xx reference manual: - https://www.st.com/resource/en/reference_manual/dm00176879.pdf - -.. _STM32H747xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h747xi.pdf - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html diff --git a/boards/arm/arduino_mkrzero/Kconfig.board b/boards/arm/arduino_mkrzero/Kconfig.board deleted file mode 100644 index aa80faec588..00000000000 --- a/boards/arm/arduino_mkrzero/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino MKR Zero Board configuration - -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_MKRZERO - bool "Arduino MKR Zero" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/arduino_mkrzero/Kconfig.defconfig b/boards/arm/arduino_mkrzero/Kconfig.defconfig deleted file mode 100644 index 988edd82f1b..00000000000 --- a/boards/arm/arduino_mkrzero/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Arduino MKR Zero board configuration - -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "arduino_mkrzero" - depends on BOARD_ARDUINO_MKRZERO - -if DISK_DRIVERS - -config DISK_DRIVER_SDMMC - default y - -config SPI - default y - -config GPIO - default y - -endif # DISK_DRIVERS diff --git a/boards/arm/arduino_mkrzero/arduino_mkrzero_defconfig b/boards/arm/arduino_mkrzero/arduino_mkrzero_defconfig deleted file mode 100644 index 2101e5a8332..00000000000 --- a/boards/arm/arduino_mkrzero/arduino_mkrzero_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_ARDUINO_MKRZERO=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ARDUINO=y -CONFIG_GPIO=y diff --git a/boards/arm/arduino_mkrzero/doc/index.rst b/boards/arm/arduino_mkrzero/doc/index.rst deleted file mode 100644 index a64a9248bd0..00000000000 --- a/boards/arm/arduino_mkrzero/doc/index.rst +++ /dev/null @@ -1,183 +0,0 @@ -.. _arduino_mkrzero: - -Arduino MKR Zero -#################### - -Overview -******** - -The Arduino MKR Zero built with smaller MKR form factor and powered by Atmel's SAMD21 MCU. -This board come with microSD card holder that allows you to play with music files with no extra hardware. - -.. image:: img/arduino_mkrzero.jpg - :align: center - :alt: Arduino MKR Zero - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- One user LEDs -- One reset button -- microSD card slot -- ATECC508A secure element - -Supported Features -================== - -The arduino_mkrzero board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| ADC | on-chip | Analog to digital converter | -+-----------+------------+------------------------------------------+ -| COUNTER | on-chip | Pulse counter | -+-----------+------------+------------------------------------------+ -| DMA | on-chip | Direct memory access unit | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Hardware info and serial number | -+-----------+------------+------------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| I2C | on-chip | Inter-Integrated Circuit ports | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ - - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/arduino_mkrzero/arduino_mkrzero_defconfig`. - -Connections and IOs -=================== - -The `Arduino store`_ has detailed information about board -connections. Download the `Arduino MKR Zero Schematic`_ for more detail. - -System Clock -============ - -The SAMD21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. The internal -APB and GCLK unit are set up in the same way as the upstream Arduino -libraries. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. SERCOM5 is available on pins 13(PA23) and 14(PA22). - -PWM -=== - -The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the Arduino MKR Zero, SERCOM1 -is available on pin 8, 9, and 10. -SERCOM2 connect to microSD card slot as SPI interface. - -I2C Port -======== - -The SAMD21 MCU has 6 SERCOM based I2Cs. SERCOM0 is available on pin 11(PA08) and 12(PA09). -This I2C bus also available as ESLOV(JST SH 5pin) socket. -ATECC508A secure element is connect to this I2C bus. - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -DAC -=== - -The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On the -Arduino MKR Zero, the DAC is available on pin A0. - -Programming and Debugging -************************* - -The Arduino MKR Zero ships the BOSSA compatible bootloader. The -bootloader can be entered by quickly tapping the reset button twice. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_mkrzero - :goals: build - :compact: - -#. Connect the MKR Zero to your host computer using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_mkrzero - :goals: flash - :compact: - - You should see "Hello World! arduino_mkrzero" in your terminal. - -References -********** - -.. target-notes:: - -.. _Arduino Store: - https://store.arduino.cc/collections/boards/products/arduino-mkr-zero-i2s-bus-sd-for-sound-music-digital-audio-data - -.. _Arduino MKR Zero Schematic: - https://www.arduino.cc/en/uploads/Main/ArduinoMKRZero-schematic.pdf diff --git a/boards/arm/arduino_nano_33_ble/Kconfig.board b/boards/arm/arduino_nano_33_ble/Kconfig.board deleted file mode 100644 index 2492aea4c91..00000000000 --- a/boards/arm/arduino_nano_33_ble/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2020 Jefferson Lee. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_NANO_33_BLE - bool "Arduino Nano 33 BLE board" - depends on SOC_NRF52840_QIAA - -config BOARD_ARDUINO_NANO_33_BLE_SENSE - bool "Arduino Nano 33 BLE Sense board" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/arduino_nano_33_ble/Kconfig.defconfig b/boards/arm/arduino_nano_33_ble/Kconfig.defconfig deleted file mode 100644 index 382e71f7e9f..00000000000 --- a/boards/arm/arduino_nano_33_ble/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2020 Jefferson Lee. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_NANO_33_BLE || BOARD_ARDUINO_NANO_33_BLE_SENSE - -config BOARD - default "arduino_nano_33_ble" if BOARD_ARDUINO_NANO_33_BLE - default "arduino_nano_33_ble_sense" if BOARD_ARDUINO_NANO_33_BLE_SENSE - -config BT_CTLR - default BT - -config REGULATOR - default y if SENSOR - -endif # BOARD_ARDUINO_NANO_33_BLE || BOARD_ARDUINO_NANO_33_BLE_SENSE diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense.yaml b/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense.yaml deleted file mode 100644 index cdd9ead370c..00000000000 --- a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: arduino_nano_33_ble_sense -name: Arduino Nano 33 BLE Sense -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - ble - - i2c - - pwm - - serial - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: arduino diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense_defconfig b/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense_defconfig deleted file mode 100644 index 024c659ad37..00000000000 --- a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_ARDUINO_NANO_33_BLE_SENSE=y - -# Enable MPU -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -# enable peripherals -CONFIG_GPIO=y -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable sam-ba bootloader on legacy mode -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_LEGACY=y diff --git a/boards/arm/arduino_nano_33_iot/Kconfig.board b/boards/arm/arduino_nano_33_iot/Kconfig.board deleted file mode 100644 index 87c65a0f142..00000000000 --- a/boards/arm/arduino_nano_33_iot/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Nano 33 IOT board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_NANO_33_IOT - bool "Arduino Nano 33 IOT" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/arduino_nano_33_iot/Kconfig.defconfig b/boards/arm/arduino_nano_33_iot/Kconfig.defconfig deleted file mode 100644 index b4fc2bbc21f..00000000000 --- a/boards/arm/arduino_nano_33_iot/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Nano 33 IOT board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "arduino_nano_33_iot" - depends on BOARD_ARDUINO_NANO_33_IOT diff --git a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot_defconfig b/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot_defconfig deleted file mode 100644 index 3bc5a6370aa..00000000000 --- a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_ARDUINO_NANO_33_IOT=y -CONFIG_SOC_ATMEL_SAMD_OSC8M=y -CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ARDUINO=y diff --git a/boards/arm/arduino_nano_33_iot/doc/index.rst b/boards/arm/arduino_nano_33_iot/doc/index.rst deleted file mode 100644 index 62353ecbe1e..00000000000 --- a/boards/arm/arduino_nano_33_iot/doc/index.rst +++ /dev/null @@ -1,171 +0,0 @@ -.. _arduino_nano_33_iot: - -Arduino Nano 33 IOT -################### - -Overview -******** - -The Arduino Nano 33 IOT is a small form factor development board with USB, -Wifi, Bluetooth, a 6 axis IMU, and secure element. - -.. image:: img/nano_33_iot.jpg - :align: center - :alt: Arduino Nano 33 IOT - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 256 KiB flash memory and 32 KiB of RAM -- One user LED -- One reset button -- Native USB port -- Wifi and Bluetooth via a u-blox NINA-W102 -- ATECC608A secure element -- LSM6DS3 six axis accelerometer and gyro - -Supported Features -================== - -The arduino_nano_33_iot board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| ADC | on-chip | Analog to digital converter | -+-----------+------------+------------------------------------------+ -| COUNTER | on-chip | Pulse counter | -+-----------+------------+------------------------------------------+ -| DMA | on-chip | Direct memory access unit | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Hardware info and serial number | -+-----------+------------+------------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/arduino_nano_33_iot/arduino_nano_33_iot_defconfig`. - -Connections and IOs -=================== - -The `Arduino store`_ has detailed information about board -connections. Download the `schematic`_ for more detail. - -System Clock -============ - -The SAMD21 MCU is configured to use the 8 MHz internal oscillator -with the on-chip PLL generating the 48 MHz system clock. The internal -APB and GCLK unit are set up in the same way as the upstream Arduino -libraries. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. SERCOM5 is available on pins 1 and 2. - -PWM -=== - -The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC2 instead of by GPIO. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. SERCOM1 is available on pins 1, 14, -and 15. - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -Programming and Debugging -************************* - -The Nano 33 IOT ships the BOSSA compatible UF2 bootloader. The -bootloader can be entered by quickly tapping the reset button twice. - -Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader -will be entered automatically when you run :code:`west flash`. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_nano_33_iot - :goals: build - :compact: - -#. Connect the Nano 33 IOT to your host computer using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_nano_33_iot - :goals: flash - :compact: - - You should see "Hello World! arduino_nano_33_iot" in your terminal. - -References -********** - -.. target-notes:: - -.. _Arduino Store: - https://store.arduino.cc/arduino-nano-33-iot - -.. _schematic: - https://content.arduino.cc/assets/NANO33IoTV2.0_sch.pdf diff --git a/boards/arm/arduino_nicla_sense_me/Kconfig.board b/boards/arm/arduino_nicla_sense_me/Kconfig.board deleted file mode 100644 index 47e9aabfbb2..00000000000 --- a/boards/arm/arduino_nicla_sense_me/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Nicla Sense ME board configuration - -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_NICLA_SENSE_ME - bool "Arduino Nicla Sense ME" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/arduino_nicla_sense_me/Kconfig.defconfig b/boards/arm/arduino_nicla_sense_me/Kconfig.defconfig deleted file mode 100644 index c0293cec5c9..00000000000 --- a/boards/arm/arduino_nicla_sense_me/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Arduino Nicla Sense ME board configuration - -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_NICLA_SENSE_ME - -config BOARD - default "arduino_nicla_sense_me" - -config BT_CTLR - default BT - -endif # BOARD_ARDUINO_NICLA_SENSE_ME diff --git a/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me_defconfig b/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me_defconfig deleted file mode 100644 index c2f2b95cc72..00000000000 --- a/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_ARDUINO_NICLA_SENSE_ME=y - -# Enable MPU -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/arduino_opta_m4/Kconfig.board b/boards/arm/arduino_opta_m4/Kconfig.board deleted file mode 100644 index cce1cd6337a..00000000000 --- a/boards/arm/arduino_opta_m4/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Felipe Neves -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_OPTA_M4 - bool "Arduino OPTA Programmable Logic Controller M4 Core" - depends on SOC_STM32H747XX - select CPU_CORTEX_M4 diff --git a/boards/arm/arduino_opta_m4/Kconfig.defconfig b/boards/arm/arduino_opta_m4/Kconfig.defconfig deleted file mode 100644 index be17c009555..00000000000 --- a/boards/arm/arduino_opta_m4/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Felipe Neves -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_OPTA_M4 - -config BOARD - default "arduino_opta_m4" - -endif # BOARD_ARDUINO_OPTA_M4 diff --git a/boards/arm/arduino_opta_m4/arduino_opta_m4.yaml b/boards/arm/arduino_opta_m4/arduino_opta_m4.yaml deleted file mode 100644 index 4030cb402f6..00000000000 --- a/boards/arm/arduino_opta_m4/arduino_opta_m4.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: arduino_opta_m4 -name: ARDUINO OPTA (M4) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 288 -flash: 512 -supported: - - gpio -testing: - ignore_tags: - - mpu - - nfc - - net - - flash - - input - - mcumgr -vendor: arduino diff --git a/boards/arm/arduino_opta_m4/arduino_opta_m4_defconfig b/boards/arm/arduino_opta_m4/arduino_opta_m4_defconfig deleted file mode 100644 index bcf01ccabfb..00000000000 --- a/boards/arm/arduino_opta_m4/arduino_opta_m4_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2023 Felipe Neves -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -CONFIG_BOARD_ARDUINO_OPTA_M4=y - -# enable GPIO -CONFIG_GPIO=y - -# clock configuration -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y - -# Use zephyr,code-partition as flash offset -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/arduino_opta_m4/doc/index.rst b/boards/arm/arduino_opta_m4/doc/index.rst deleted file mode 100644 index 90f9497db33..00000000000 --- a/boards/arm/arduino_opta_m4/doc/index.rst +++ /dev/null @@ -1,177 +0,0 @@ -.. _arduino_opta_m4_board: - -Arduino OPTA M4-Core -####################### - -Overview -******** - -The Arduino™ Opta® is a secure micro Programmable Logic Controller (PLC) -with Industrial Internet of Things (IoT) capabilities. - -Developed in partnership with Finder®, this device supports both the Arduino -programming language and standard IEC-61131-3 PLC programming languages, -such as Ladder Diagram (LD), Sequential Function Chart (SFC), -Function Block Diagram (FBD), Structured Text (ST), and Instruction List (IL), -making it an ideal device for automation engineers. - -For Zephyr RTOS, only the M4 is supported for now, making the M7 run the PLC -tasks while the M4 core under Zephyr acts as a coprocessor. - -Additionally, the device features: - -- Ethernet compliant with IEEE802.3-2002 -- 16MB QSPI Flash -- 4 x green color status LEDs -- 1 x user push-button -- 1 x reset push-button accessible via pinhole -- 8 x analog inputs -- 4 x isolated relay outputs - -.. image:: img/arduino_opta.jpeg - :align: center - :alt: ARDUINO-OPTA - -More information about the board can be found at the `ARDUINO-OPTA website`_. -More information about STM32H747XIH6 can be found here: - -- `STM32H747XI on www.st.com`_ -- `STM32H747xx reference manual`_ -- `STM32H747xx datasheet`_ - -Supported Features -================== - -The current Zephyr arduino_opta_m4 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration per core can be found in the defconfig files: -``boards/arm/arduino_opta_m4/arduino_opta_m4_defconfig`` - -Pin Mapping -=========== - -ARDUINO OPTA M4 has access to the 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `ARDUINO-OPTA website`_. - -Default Zephyr Peripheral Mapping ---------------------------------- - -- Status LED1 : PI0 -- Status LED2 : PI1 -- Status LED3 : PI3 -- Status LED4 : PH15 -- User button : PE4 - -System Clock -============ - -The STM32H747I System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the CPU2 (Cortex-M4) System clock -is driven at 240MHz. PLL clock is fed by a 25MHz high speed external clock. - -Resources sharing -================= - -The dual core nature of STM32H747 SoC requires sharing HW resources between the -two cores. This is done in 3 ways: - -- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only - has access to bus clock activation and deactivation. -- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in - devicetree before compilation. The user must ensure peripherals are not assigned - to both cores at the same time. -- **Run time protection**: Interrupt-controller and GPIO configurations could be - accessed by both cores at run time. Accesses are protected by a hardware semaphore - to avoid potential concurrent access issues. - -Programming and Debugging -************************* - -Applications for the ``arduino_opta_m4`` use the regular Zephyr build commands. -See :ref:`build_an_application` for more information about application builds. - -Flashing -======== - -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. The OPTA has a DFU capable bootloader which -can be accessed by connecting the device to the USB, and then pressing -the RESET button shortly twice, the RESET-LED on the board will fade -indicating the board is in bootloader mode. - -By default: - - - CPU2 (Cortex-M4) boot address is set to 0x08180000 (OB: BOOT_CM4_ADD0) - -Zephyr flash configuration has been set to meet these default settings. - -Flashing an application to ARDUINO OPTA M4 ------------------------------------------- - -First, connect the device to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: arduino_opta_m4 - :goals: build flash - -Starting the application on the ARDUINO OPTA M4 ------------------------------------------------ - -Make sure the option bytes are set to prevent the M4 from auto-starting, and -that the M7 side starts the M4 at the correct Flash address. - -This can be done by selecting in the Arduino IDE's "Tools" / "Flash Split" -menu the "1.5MB M7 + 0.5MB M4" option, and loading a sketch that contains -at least the following code: - - .. code-block:: cpp - - #include - - void setup() { - RPC.begin(); - } - - void loop() { } - -Debugging -========= - -Debugging is not yet supported by this board, since the debug port does -not have an easy access. - -.. _ARDUINO-OPTA website: - https://docs.arduino.cc/hardware/opta - -.. _STM32H747XI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html - -.. _STM32H747xx reference manual: - https://www.st.com/resource/en/reference_manual/dm00176879.pdf - -.. _STM32H747xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h747xi.pdf diff --git a/boards/arm/arduino_portenta_h7/CMakeLists.txt b/boards/arm/arduino_portenta_h7/CMakeLists.txt deleted file mode 100644 index 6aaa80fcf41..00000000000 --- a/boards/arm/arduino_portenta_h7/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_ARDUINO_PORTENTA_H7_M7) - -zephyr_library() -zephyr_library_sources(board.c) - -endif() diff --git a/boards/arm/arduino_portenta_h7/Kconfig.board b/boards/arm/arduino_portenta_h7/Kconfig.board deleted file mode 100644 index 75e401c5d4b..00000000000 --- a/boards/arm/arduino_portenta_h7/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Arduino Portenta H7 board configuration - -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_PORTENTA_H7_M7 - bool "Arduino Portenta H7 Board" - depends on SOC_STM32H747XX - select CPU_CORTEX_M7 - -config BOARD_ARDUINO_PORTENTA_H7_M4 - bool "Arduino Portenta H7 Board" - depends on SOC_STM32H747XX - select CPU_CORTEX_M4 diff --git a/boards/arm/arduino_portenta_h7/Kconfig.defconfig b/boards/arm/arduino_portenta_h7/Kconfig.defconfig deleted file mode 100644 index 7b537a6e466..00000000000 --- a/boards/arm/arduino_portenta_h7/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Arduino Portenta H7 board configuration - -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_PORTENTA_H7_M7 || BOARD_ARDUINO_PORTENTA_H7_M4 - -config BOARD - default "arduino_portenta_h7_m7" if BOARD_ARDUINO_PORTENTA_H7_M7 - default "arduino_portenta_h7_m4" if BOARD_ARDUINO_PORTENTA_H7_M4 - -endif # BOARD_ARDUINO_PORTENTA_H7_M7 || BOARD_ARDUINO_PORTENTA_H7_M4 diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4.yaml b/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4.yaml deleted file mode 100644 index b84e35835c6..00000000000 --- a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: arduino_portenta_h7_m4 -name: Arduino Portenta H7 (M4) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 288 -flash: 1024 -supported: - - gpio -testing: - ignore_tags: - - mpu - - nfc -vendor: arduino diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4_defconfig b/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4_defconfig deleted file mode 100644 index bb6c8c99951..00000000000 --- a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_ARDUINO_PORTENTA_H7_M4=y - -# Enable GPIO -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable pin controller -CONFIG_PINCTRL=y - -# Enable uart driver -# CONFIG_SERIAL=y - -# By default CONSOLE is assigned to m7 -# CONFIG_CONSOLE=y -# CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7.yaml b/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7.yaml deleted file mode 100644 index af23aee83d4..00000000000 --- a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: arduino_portenta_h7_m7 -name: Arduino Portenta H7 (M7) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 512 -flash: 1024 -supported: - - gpio -vendor: arduino diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7_defconfig b/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7_defconfig deleted file mode 100644 index f7e1a108631..00000000000 --- a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_ARDUINO_PORTENTA_H7_M7=y - -# Enable the internal SMPS regulator -CONFIG_POWER_SUPPLY_DIRECT_SMPS=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y - -# Use zephyr,code-partition as flash offset -CONFIG_USE_DT_CODE_PARTITION=y - -# Disable following to assign serial ports to m4 core - -# Enable uart driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable regulator -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED=y diff --git a/boards/arm/arduino_portenta_h7/doc/index.rst b/boards/arm/arduino_portenta_h7/doc/index.rst deleted file mode 100644 index 999a659f773..00000000000 --- a/boards/arm/arduino_portenta_h7/doc/index.rst +++ /dev/null @@ -1,144 +0,0 @@ -.. _arduino_portenta_h7_board: - -Arduino Portenta H7 -####################### - -Overview -******** - -The Portenta H7 enables a wide diversity of applications taking benefit -from Computer Vision, PLCs, Robotics controller, High-end industrial machinery -and high-speed booting computation (ms). - -The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU, -with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, -large set of peripherals, SMPS, and MIPI-DSI. - -Additionally, the board features: -- USB OTG FS -- 3 color user LEDs - -.. image:: img/arduino_portenta_h7.jpeg - :width: 500px - :align: center - :height: 325px - :alt: ARDUINO_PORTENTA_H7 - -More information about the board can be found at the `ARDUINO_PORTENTA_H7 website`_. -More information about STM32H747XIH6 can be found here: - -- `STM32H747XI on www.st.com`_ -- `STM32H747xx reference manual`_ -- `STM32H747xx datasheet`_ - -Supported Features -================== - -The current Zephyr arduino_portenta_h7 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -Resources sharing -================= - -The dual core nature of STM32H747 SoC requires sharing HW resources between the -two cores. This is done in 3 ways: - -- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only - has access to bus clock activation and deactivation. -- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in - devicetree before compilation. The user must ensure peripherals are not assigned - to both cores at the same time. -- **Run time protection**: Interrupt-controller and GPIO configurations could be - accessed by both cores at run time. Accesses are protected by a hardware semaphore - to avoid potential concurrent access issues. - -Building and Flashing -************************* - -Applications for the ``arduino_portenta_h7`` board should be built per core target, -using either ``arduino_portenta_h7_m7`` or ``arduino_portenta_h7_m4`` as the target. -See :ref:`build_an_application` for more information about application builds. - - -Flashing -======== - -Installing dfu-util -------------------- - -This board requires dfu-utils for flashing. It is recommended to use at least -v0.8 of `dfu-util`_. The package available in debian/ubuntu can be quite old, so you might -have to build dfu-util from source. - -Flashing an application to STM32H747I M7 Core ---------------------------------------------- - -First, connect the Arduino Portenta H7 board to your host computer using -the USB port to prepare it for flashing. Double tap the button to put the board -into the Arduino Bootloader mode. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_portenta_h7_m7 - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arduino_portenta_m7 - -Similarly, you can build and flash samples on the M4 target. For this, please -take care of the resource sharing (UART port used for console for instance). - -Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: arduino_portenta_h7_m4 - :goals: build flash - -.. _ARDUINO_PORTENTA_H7 website: - https://docs.arduino.cc/hardware/portenta-h7 - -.. _STM32H747XI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html - -.. _STM32H747xx reference manual: - https://www.st.com/resource/en/reference_manual/dm00176879.pdf - -.. _STM32H747xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h747xi.pdf - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html diff --git a/boards/arm/arduino_uno_r4/Kconfig.board b/boards/arm/arduino_uno_r4/Kconfig.board deleted file mode 100644 index d56eff75387..00000000000 --- a/boards/arm/arduino_uno_r4/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_UNO_R4_MINIMA - bool "Arduino Uno R4 Minima board" - depends on SOC_R7FA4M1AB3CFM diff --git a/boards/arm/arduino_uno_r4/Kconfig.defconfig b/boards/arm/arduino_uno_r4/Kconfig.defconfig deleted file mode 100644 index 2d483f3bb38..00000000000 --- a/boards/arm/arduino_uno_r4/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_UNO_R4_MINIMA - -config BOARD - default "arduino_uno_r4_minima" if BOARD_ARDUINO_UNO_R4_MINIMA - -endif # BOARD_ARDUINO_UNO_R4_MINIMA diff --git a/boards/arm/arduino_zero/Kconfig.board b/boards/arm/arduino_zero/Kconfig.board deleted file mode 100644 index 646e4020e42..00000000000 --- a/boards/arm/arduino_zero/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Zero Board configuration - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_ZERO - bool "Arduino Zero" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/arduino_zero/Kconfig.defconfig b/boards/arm/arduino_zero/Kconfig.defconfig deleted file mode 100644 index 9cd148585cb..00000000000 --- a/boards/arm/arduino_zero/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Zero board configuration - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "arduino_zero" - depends on BOARD_ARDUINO_ZERO diff --git a/boards/arm/arduino_zero/arduino_zero_defconfig b/boards/arm/arduino_zero/arduino_zero_defconfig deleted file mode 100644 index 2448a6a65d0..00000000000 --- a/boards/arm/arduino_zero/arduino_zero_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_ARDUINO_ZERO=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y diff --git a/boards/arm/arduino_zero/doc/index.rst b/boards/arm/arduino_zero/doc/index.rst deleted file mode 100644 index 4c686daff5e..00000000000 --- a/boards/arm/arduino_zero/doc/index.rst +++ /dev/null @@ -1,166 +0,0 @@ -.. _arduino_zero: - -Arduino/Genuino Zero -#################### - -Overview -******** - -The Arduino Zero is a maker-friendly development board with -Atmel’s Embedded Debugger (EDBG), which provides a full -debug interface without the need for additional hardware. - -.. image:: img/arduino_zero.jpg - :align: center - :alt: Arduino Zero - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- 3 user LEDs -- One reset button -- On-board USB based EDBG unit with serial console -- Native USB port - -Supported Features -================== - -The arduino_zero board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| DAC | on-chip | Digital to analogue converter | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/arduino_zero/arduino_zero_defconfig`. - -Connections and IOs -=================== - -The `Arduino store`_ has detailed information about board -connections. Download the `Arduino Zero Schematic`_ for more detail. - -System Clock -============ - -The SAMD21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. The internal -APB and GCLK unit are set up in the same way as the upstream Arduino -libraries. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. One of the USARTs -(SERCOM5) is connected to the onboard Atmel Embedded Debugger (EDBG). -SERCOM0 is available on the D0/D1 pins. - -PWM -=== - -The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC2 instead of by GPIO. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the Arduino Zero, SERCOM4 -is available on the 6 pin connector at the edge of the board. - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -DAC -=== - -The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On the -Arduino Zero, the DAC is available on pin A0. - -Programming and Debugging -************************* - -The Arduino Zero comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMD21 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_zero - :goals: build - :compact: - -#. Connect the Arduino Zero to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_zero - :goals: flash - :compact: - - You should see "Hello World! arduino_zero" in your terminal. - -References -********** - -.. target-notes:: - -.. _Arduino Store: - https://store.arduino.cc/genuino-zero - -.. _Arduino Zero Schematic: - https://www.arduino.cc/en/uploads/Main/Zero_V1.0.pdf diff --git a/boards/arm/arty/CMakeLists.txt b/boards/arm/arty/CMakeLists.txt deleted file mode 100644 index 1c060b9bbac..00000000000 --- a/boards/arm/arty/CMakeLists.txt +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(board.c) - -if((CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M1) AND (CONFIG_BUILD_OUTPUT_BIN)) - # Generate zephyr.mem verilog memory hex dump file for initialising ITCM in - # Xilinx Vivado. - # - # This ought to be done using the objcopy verilog bfd, but it contains a bug - # affecting endianness: https://sourceware.org/bugzilla/show_bug.cgi?id=25202 - # - # Instead we use bin2hex from the SiFive elf2hex package, if available. - # https://github.com/sifive/elf2hex - find_program(BIN2HEX ${CROSS_COMPILE_TARGET}-bin2hex) - - if(NOT ${BIN2HEX} STREQUAL BIN2HEX-NOTFOUND) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${BIN2HEX} - ARGS --bit-width 32 - ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin - ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.mem - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} - ) - message(STATUS "Verilog memory hex dump will be written to: ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.mem") - else() - message(STATUS "The bin2hex (${CROSS_COMPILE_TARGET}-bin2hex) utility was not found, verilog memory hex dump file cannot be generated") - endif() -endif() diff --git a/boards/arm/arty/Kconfig b/boards/arm/arty/Kconfig deleted file mode 100644 index 78b1d148b51..00000000000 --- a/boards/arm/arty/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Digilent Arty board configuration - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INIT_PRIORITY - int "Board initialization priority" - default 50 - depends on BOARD_ARTY_A7_ARM_DESIGNSTART_M1 || BOARD_ARTY_A7_ARM_DESIGNSTART_M3 - depends on "$(dt_nodelabel_enabled,daplink_qspi_mux)" - help - Board initialization priority. The board initialization must take - place after the GPIO driver is initialized. diff --git a/boards/arm/arty/Kconfig.board b/boards/arm/arty/Kconfig.board deleted file mode 100644 index 17a6e659748..00000000000 --- a/boards/arm/arty/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Digilent Arty board configuration - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARTY_A7_ARM_DESIGNSTART_M1 - bool "Digilent Arty A7 ARM DesignStart Cortex-M1" - depends on SOC_SERIES_ARM_DESIGNSTART - -config BOARD_ARTY_A7_ARM_DESIGNSTART_M3 - bool "Digilent Arty A7 ARM DesignStart Cortex-M3" - depends on SOC_SERIES_ARM_DESIGNSTART diff --git a/boards/arm/arty/Kconfig.defconfig b/boards/arm/arty/Kconfig.defconfig deleted file mode 100644 index c298a64aaf3..00000000000 --- a/boards/arm/arty/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# Digilent Arty board configuration - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARTY_A7_ARM_DESIGNSTART_M1 || BOARD_ARTY_A7_ARM_DESIGNSTART_M3 - -config BOARD - default "arty_a7_arm_designstart_m1" if BOARD_ARTY_A7_ARM_DESIGNSTART_M1 - default "arty_a7_arm_designstart_m3" if BOARD_ARTY_A7_ARM_DESIGNSTART_M3 - -config CPU_CORTEX_M_HAS_SYSTICK - default y - -config CPU_HAS_ARM_MPU - default y if BOARD_ARTY_A7_ARM_DESIGNSTART_M3 - -config NUM_IRQS - default 7 - -config GPIO - default y if "$(dt_nodelabel_enabled,daplink_qspi_mux)" - -endif # BOARD_ARTY_A7_ARM_DESIGNSTART_M1 || BOARD_ARTY_A7_ARM_DESIGNSTART_M3 diff --git a/boards/arm/arty/arty_a7_arm_designstart_m1.yaml b/boards/arm/arty/arty_a7_arm_designstart_m1.yaml deleted file mode 100644 index 22068def690..00000000000 --- a/boards/arm/arty/arty_a7_arm_designstart_m1.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: arty_a7_arm_designstart_m1 -name: Digilent Arty A7 ARM DesignStart Cortex-M1 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32 -flash: 64 -supported: - - flash - - spi - - gpio diff --git a/boards/arm/arty/arty_a7_arm_designstart_m1_defconfig b/boards/arm/arty/arty_a7_arm_designstart_m1_defconfig deleted file mode 100644 index a3ad6770d45..00000000000 --- a/boards/arm/arty/arty_a7_arm_designstart_m1_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ARM_DESIGNSTART=y -CONFIG_SOC_ARM_DESIGNSTART_FPGA_CORTEX_M1=y -CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M1=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 - -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arty/arty_a7_arm_designstart_m3.yaml b/boards/arm/arty/arty_a7_arm_designstart_m3.yaml deleted file mode 100644 index 3ea0ebbe1b0..00000000000 --- a/boards/arm/arty/arty_a7_arm_designstart_m3.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: arty_a7_arm_designstart_m3 -name: Digilent Arty A7 ARM DesignStart Cortex-M3 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32 -flash: 32 -supported: - - flash - - spi - - gpio diff --git a/boards/arm/arty/arty_a7_arm_designstart_m3_defconfig b/boards/arm/arty/arty_a7_arm_designstart_m3_defconfig deleted file mode 100644 index 3753680a072..00000000000 --- a/boards/arm/arty/arty_a7_arm_designstart_m3_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ARM_DESIGNSTART=y -CONFIG_SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3=y -CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M3=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=50000000 -CONFIG_ARM_MPU=y - -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arty/board.cmake b/boards/arm/arty/board.cmake deleted file mode 100644 index 529c142aa28..00000000000 --- a/boards/arm/arty/board.cmake +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M1) - board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m1.cfg") - board_runner_args(jlink "--device=Cortex-M1" "--reset-after-load") - - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -elseif(CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M3) - board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m3.cfg") - board_runner_args(jlink "--device=Cortex-M3" "--reset-after-load") - - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -endif() diff --git a/boards/arm/arty/doc/index.rst b/boards/arm/arty/doc/index.rst deleted file mode 100644 index 58f0e467f6c..00000000000 --- a/boards/arm/arty/doc/index.rst +++ /dev/null @@ -1,228 +0,0 @@ -.. _arty: - -Digilent Arty -############# - -Overview -******** - -The `Digilent Arty`_ is a line of FPGA-based development boards aimed for makers -and hobbyists. The Arty is available in several configurations, each with a -different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series). - -Each board is equipped with on-board JTAG for FPGA programming and debugging, -LEDs, switches, buttons, DDR3 RAM, and QSPI flash for storing the FPGA -bitstream. - -.. figure:: arty_a7-35.jpg - :align: center - :alt: Digilent Arty A7-35 - - Digilent Arty A7-35 (Credit: Digilent Inc) - -The Spartan-7 and Artix-7 based Arty board do not contain a CPU, but require a -so-called soft processor to be instantiated within the FPGA in order to run -Zephyr. The Zynq-7000 based Arty boards are not yet supported by Zephyr. - -ARM Cortex-M1/M3 DesignStart FPGA -********************************* - -One way of instantiating soft processors on the Arty is using the `ARM -DesignStart FPGA`_ Xilinx edition reference designs from ARM. Zephyr supports -both the Cortex-M1 and the Cortex-M3 reference designs. The Cortex-M1 design -targets either the Spartan-7 or Artix-7 based Arty boards, whereas the Cortex-M3 -design only targets the Artix-7 based boards. Zephyr only supports the Artix-7 -targeted designs for now. - -For more information about the ARM Cortex-M1/M3 DesignStart FPGA, see the -following websites: - -- `Technical Resources for DesignStart FPGA`_ -- `Technical Resources for DesignStart FPGA on Xilinx`_ -- `ARM DesignStart FPGA Xilinx FAQs`_ - -Supported Features -================== - -The ``arty_a7_arm_designstart_m1`` board configuration supports the following -hardware features of the Cortex-M1 reference design: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio, non-interrupt | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| QSPI | on-chip | QSPI flash | -+-----------+------------+-------------------------------------+ - -The default configuration for the Cortex-M1 can be found in the defconfig file: -:file:`boards/arm/arty/arty_a7_arm_designstart_m1_defconfig`. - -In addition to the above, the ``arty_a7_arm_designstart_m3`` board configuration -supports the following hardware features of the Cortex-M3 reference design: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | Memory Protection Unit | -+-----------+------------+-------------------------------------+ - -The default configuration for the Cortex-M3 can be found in the defconfig file: -:file:`boards/arm/arty/arty_a7_arm_designstart_m3_defconfig`. - -Other hardware features are not currently supported by the port. - -System Clock -============ - -The Cortex-M1 reference design is configured to use the 100 MHz external -oscillator on the board as CPU system clock whereas the Cortex-M3 reference -design is configured for 50MHz CPU system clock. - -Serial Port -=========== - -The reference design contains one Xilinx UART Lite. This UART is configured as -console and is accessible through the on-board JTAG adapter via USB connector -``J10``. - -Connecting the Debug Probes -=========================== - -Two different debug probes are needed in order to program the board; the -on-board Digilent JTAG connected to the FPGA, and an external Serial Wire Debug -(SWD) capable debug probe connected to the ARM Cortex-M1 CPU. - -The on-board JTAG is used for configuring and debugging the Xilinx FPGA -itself. It is available on USB connector ``J10``. - -The external SWD debug probe can be connected to connector ``J4`` (``nSRST`` on -``IO39``, ``SWDIO`` on ``IO40``, and ``SWCLK`` on ``IO41``). Another option is -to use the dedicated :ref:`v2c_daplink_shield`. - -Programming and Debugging -************************* - -First, configure the FPGA with the selected reference design FPGA bitstream -using Xilinx Vivado as described in the ARM Cortex-M1/Cortex-M3 DesignStart FPGA -Xilinx edition user guide (available as part of the reference design download -from `Technical Resources for DesignStart FPGA on Xilinx`_). - -Another option for configuring the FPGA with the reference design bitstream is -to use the :ref:`openocd-debug-host-tools`: - -.. code-block:: console - - openocd -f board/arty_s7.cfg -c "init;\ - pld load 0 m1_for_arty_a7_reference.bit;\ - shutdown" - -or: - -.. code-block:: console - - openocd -f board/arty_s7.cfg -c "init;\ - pld load 0 m3_for_arty_a7_reference.bit;\ - shutdown" - -.. note:: - - The pre-built FPGA bitstream only works for Arty boards equipped with an - Artix-35T FPGA. For other Arty variants (e.g. the Arty A7-100) the bitstream - must be rebuilt. - -Next, build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Console -===================== - -The UART console is available via the on-board JTAG on USB connector -``J10``. The on-board JTAG will enumerate as two USB serial ports. The UART is -typically available on the second serial port. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for building and flashing the :ref:`hello_world` application -for the Cortex-M1 reference design: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arty_a7_arm_designstart_m1 - :goals: flash - -After flashing, you should see message similar to the following in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.3.99 *** - Hello World! arty_a7_arm_designstart_m1 - -The same procedure can be used for the Cortex-M3 reference design. - -Note, however, that the application was not persisted in flash memory by the -above steps. It was merely written to internal block RAM in the FPGA. It will -revert to the application stored in the block RAM within the FPGA bitstream -the next time the FPGA is configured. - -The steps to persist the application within the FPGA bitstream are covered by -the ARM Cortex-M1/M3 DesignStart FPGA Xilinx edition user guide. If the -:kconfig:option:`CONFIG_BUILD_OUTPUT_BIN` is enabled and the `SiFive elf2hex`_ package -is available, the build system will automatically generate a Verilog memory hex -dump :file:`zephyr.mem` file suitable for initialising the block RAM using -`Xilinx Vivado`_. - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arty_a7_arm_designstart_m1 - :goals: debug - -Step through the application in your debugger, and you should see a message -similar to the following in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.3.99 *** - Hello World! arty_a7_arm_designstart_m1 - -.. _Digilent Arty: - https://store.digilentinc.com/arty - -.. _ARM DesignStart FPGA: - https://www.arm.com/resources/designstart/designstart-fpga - -.. _Technical Resources for DesignStart FPGA: - https://developer.arm.com/ip-products/designstart/fpga - -.. _Technical Resources for DesignStart FPGA on Xilinx: - https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx - -.. _ARM DesignStart FPGA Xilinx FAQs: - https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx-faqs - -.. _SiFive elf2hex: - https://github.com/sifive/elf2hex - -.. _Xilinx Vivado: - https://www.xilinx.com/products/design-tools/vivado.html diff --git a/boards/arm/ast1030_evb/Kconfig.board b/boards/arm/ast1030_evb/Kconfig.board deleted file mode 100644 index 464e3f93705..00000000000 --- a/boards/arm/ast1030_evb/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Aspeed AST1030 evaluation board configuration -# -# Copyright (c) 2021 Aspeed Technology Inc. - -config BOARD_AST1030_EVB - bool "ASPEED AST1030 Evaluation Board" - depends on SOC_AST1030 diff --git a/boards/arm/ast1030_evb/Kconfig.defconfig b/boards/arm/ast1030_evb/Kconfig.defconfig deleted file mode 100644 index 9402846fdad..00000000000 --- a/boards/arm/ast1030_evb/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Aspeed AST1030 evaluation board configuration -# -# Copyright (c) 2021 Aspeed Technology Inc. - -if BOARD_AST1030_EVB -config BOARD - default "ast1030_evb" -endif # BOARD_AST1030_EVB diff --git a/boards/arm/ast1030_evb/doc/index.rst b/boards/arm/ast1030_evb/doc/index.rst deleted file mode 100644 index 0e00488b727..00000000000 --- a/boards/arm/ast1030_evb/doc/index.rst +++ /dev/null @@ -1,93 +0,0 @@ -.. _ast1030_evb: - -AST1030_EVB -################### - -Overview -******** - -The AST1030_EVB kit is a development platform to evaluate the -Aspeed AST10x0 series SOCs. This board needs to be mated with -part number AST1030. - -.. image:: ast1030_evb.jpg - :align: center - :alt: AST1030 Evaluation Board - -Hardware -******** - -- ARM Cortex-M4F Processor -- 768 KB on-chip SRAM for instruction and data memory -- 1 MB on-chip Flash memory for boot ROM and data storage -- SPI interface -- UART interface -- I2C/I3C interface -- FAN PWM interface -- ADC interface -- JTAG interface -- USB interface -- LPC interface -- eSPI interface - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the defconfig file: -``boards/arm/ast1030_evb/ast1030_evb_defconfig`` - - -Connections and IOs -=================== - -Aspeed to provide the schematic for this board. - -System Clock -============ - -The AST1030 SOC is configured to use external 25MHz clock input to generate 200Mhz system clock by -the on-chip PLL. - -Serial Port -=========== - -UART5 is configured for serial logs. The default serial setup is 115200 8N1. - - -Programming and Debugging -************************* - -This board comes with a JTAG port which facilitates debugging using a single physical connection. - -Flashing -======== - -Build application as usual for the ``ast1030_evb`` board, and flash -using SF100 SPI Flash programmer. See the -`Aspeed Zephyr SDK User Guide`_ for more information. - - -Debugging -========= - -Use JTAG or SWD with a J-Link - -References -********** -.. target-notes:: - -.. _Aspeed Zephyr SDK User Guide: - https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.01.03/Aspeed_Zephy_SDK_User_Guide_v00.01.03.pdf diff --git a/boards/arm/atsamc21n_xpro/Kconfig.board b/boards/arm/atsamc21n_xpro/Kconfig.board deleted file mode 100644 index ee0ee41e596..00000000000 --- a/boards/arm/atsamc21n_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM C21N Xplained Pro Board configuration - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAMC21N_XPRO - bool "SAM C21N Xplained Pro" - depends on SOC_PART_NUMBER_SAMC21N18A diff --git a/boards/arm/atsamc21n_xpro/Kconfig.defconfig b/boards/arm/atsamc21n_xpro/Kconfig.defconfig deleted file mode 100644 index 8827f5c67a8..00000000000 --- a/boards/arm/atsamc21n_xpro/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SAM C21N Xplained Pro board configuration - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "atsamc21n_xpro" - depends on BOARD_ATSAMC21N_XPRO diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts b/boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts deleted file mode 100644 index da657b5788b..00000000000 --- a/boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2022 Kamil Serwus - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include "atsamc21n_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM C21N Xplained Pro"; - compatible = "atsamc21n,xpro", "atmel,samc21n18a", "atmel,samc21"; - - chosen { - zephyr,console = &sercom4; - zephyr,shell-uart = &sercom4; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,canbus = &can0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &user_button; - i2c-0 = &sercom1; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&portc 05 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc2 1 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&portb 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "User Button"; - zephyr,code = ; - }; - }; - -}; - -&cpu0 { - clock-frequency = <48000000>; -}; - -&adc0 { - status = "okay"; - pinctrl-0 = <&adc0_default>; - pinctrl-names = "default"; -}; - -&adc1 { - pinctrl-0 = <&adc1_default>; - pinctrl-names = "default"; -}; - -&tcc2 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - prescaler = <256>; - #pwm-cells = <2>; - - pinctrl-0 = <&pwm_default>; - pinctrl-names = "default"; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <9600>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom0_uart_default>; - pinctrl-names = "default"; -}; - -&sercom1 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom1_i2c_default>; - pinctrl-names = "default"; -}; - -&sercom2 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom2_uart_default>; - pinctrl-names = "default"; -}; - -&sercom4 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <3>; - txpo = <1>; - - pinctrl-0 = <&sercom4_uart_default>; - pinctrl-names = "default"; -}; - -&sercom5 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom5_spi_default>; - pinctrl-names = "default"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * The final 16 KiB is reserved for the application. - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@3c000 { - label = "storage"; - reg = <0x0003c000 0x00004000>; - }; - }; -}; - -&can0 { - status = "okay"; - - pinctrl-0 = <&can0_default>; - pinctrl-names = "default"; - - bus-speed = <125000>; - bus-speed-data = <1000000>; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; - -&can1 { - pinctrl-0 = <&can1_default>; - pinctrl-names = "default"; - - bus-speed = <125000>; - bus-speed-data = <1000000>; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml b/boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml deleted file mode 100644 index 16420223b24..00000000000 --- a/boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 -identifier: atsamc21n_xpro -name: SAM C21N Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - can - - dma - - gpio - - i2c - - pwm - - spi - - uart -vendor: atmel diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig b/boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig deleted file mode 100644 index 7205b28aaad..00000000000 --- a/boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_SAMC21=y -CONFIG_SOC_PART_NUMBER_SAMC21N18A=y -CONFIG_BOARD_ATSAMC21N_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y diff --git a/boards/arm/atsamc21n_xpro/doc/index.rst b/boards/arm/atsamc21n_xpro/doc/index.rst deleted file mode 100644 index e7d7d2d5852..00000000000 --- a/boards/arm/atsamc21n_xpro/doc/index.rst +++ /dev/null @@ -1,194 +0,0 @@ -.. _atsamc21n_xpro: - -SAM C21N Xplained Pro Evaluation Kit -#################################### - -Overview -******** - -The SAM C21N Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM C21N Cortex®-M0+ processor-based -microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -.. image:: img/atsamc21n_xpro.jpg - :align: center - :alt: ATSAMC21N-XPRO - -Hardware -******** - -- ATSAMC21N18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory, 32 KiB of RAM, 8KB RRW flash -- One yellow user LED -- One mechanical user push button -- One reset button -- One QTouch® button -- On-board USB based EDBG unit with serial console -- Two CAN transceivers - -Supported Features -================== - -The atsamc21n_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - CAN - - on-chip - - CAN ports - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM C21N Xplained Pro evaluation kit has 4 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM C21 Family Datasheet`_ and the `SAM C21N -Xplained Pro Schematic`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- ADC0 : PB09 -- ADC1 : PA08 -- CAN0 TX : PA24 -- CAN0 RX : PA25 -- CAN1 TX : PB14 -- CAN1 RX : PB15 -- SERCOM0 USART TX : PB24 -- SERCOM0 USART RX : PB25 -- SERCOM1 I2C SDA : PA16 -- SERCOM1 I2C SCL : PA17 -- SERCOM2 USART TX : PA12 -- SERCOM2 USART RX : PA13 -- SERCOM4 USART TX : PB10 -- SERCOM4 USART RX : PB11 -- SERCOM5 SPI MISO : PB00 -- SERCOM5 SPI MOSI : PB02 -- SERCOM5 SPI SCK : PB01 -- GPIO/PWM LED0 : PC05 - -System Clock -============ - -The SAMC21 MCU is configured to use the 32.768 kHz internal oscillator -with the on-chip internal oscillator generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMC21 MCU has eight SERCOM based USARTs with three configured as USARTs in -this BSP. SERCOM4 is the default Zephyr console. - -- SERCOM0 9600 8n1 -- SERCOM2 115200 8n1 -- SERCOM4 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) - -PWM -=== - -The SAMC21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC2 instead of by GPIO. - -Programming and Debugging -************************* - -The SAM C21N Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMC21 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the ``hello_world`` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamc21n_xpro - :goals: build - :compact: - -#. Connect the SAM C21N Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamc21n_xpro - :goals: flash - :compact: - - You should see "Hello World! atsamc21n_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip website: - https://www.microchip.com/en-us/development-tool/ATSAMC21N-XPRO - -.. _SAM C21 Family Datasheet: - https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/DataSheets/SAM-C20-C21-Family-Data-Sheet-DS60001479J.pdf - -.. _SAM C21N Xplained Pro Schematic: - https://ww1.microchip.com/downloads/en/DeviceDoc/ATSAMC21N_Xplained_Pro_Design_Files.zip diff --git a/boards/arm/atsamd20_xpro/Kconfig.board b/boards/arm/atsamd20_xpro/Kconfig.board deleted file mode 100644 index f63891d49ac..00000000000 --- a/boards/arm/atsamd20_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM D20 Xplained Pro Board configuration - -# Copyright (c) 2018 Sean Nyekjaer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAMD20_XPRO - bool "SAM D20 Xplained Pro" - depends on SOC_PART_NUMBER_SAMD20J18 diff --git a/boards/arm/atsamd20_xpro/Kconfig.defconfig b/boards/arm/atsamd20_xpro/Kconfig.defconfig deleted file mode 100644 index ec29acbf76f..00000000000 --- a/boards/arm/atsamd20_xpro/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SAM D20 Xplained Pro board configuration - -# Copyright (c) 2018 Sean Nyekjaer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "atsamd20_xpro" - depends on BOARD_ATSAMD20_XPRO diff --git a/boards/arm/atsamd20_xpro/atsamd20_xpro.dts b/boards/arm/atsamd20_xpro/atsamd20_xpro.dts deleted file mode 100644 index 778d76b6017..00000000000 --- a/boards/arm/atsamd20_xpro/atsamd20_xpro.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2018 Sean Nyekjaer - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include -#include "atsamd20_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM D20 Xplained Pro"; - compatible = "atsamd20,xpro", "atmel,samd20j18", "atmel,samd20"; - - chosen { - zephyr,console = &sercom3; - zephyr,shell-uart = &sercom3; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &yellow_led; - sw0 = &user_button; - i2c-0 = &sercom2; - }; - - leds { - compatible = "gpio-leds"; - yellow_led: led_0 { - gpios = <&porta 14 GPIO_ACTIVE_LOW>; - label = "LED0"; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&porta 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <1>; - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&porta 5 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&sercom0_spi_default>; - pinctrl-names = "default"; -}; - -&sercom2 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom2_i2c_default>; - pinctrl-names = "default"; -}; - -&sercom3 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <3>; - txpo = <1>; - - pinctrl-0 = <&sercom3_uart_default>; - pinctrl-names = "default"; -}; - -&sercom4 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom4_uart_default>; - pinctrl-names = "default"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * The final 16 KiB is reserved for the application. - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@3c000 { - label = "storage"; - reg = <0x0003c000 0x00004000>; - }; - }; -}; diff --git a/boards/arm/atsamd20_xpro/atsamd20_xpro.yaml b/boards/arm/atsamd20_xpro/atsamd20_xpro.yaml deleted file mode 100644 index 4138e137100..00000000000 --- a/boards/arm/atsamd20_xpro/atsamd20_xpro.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: atsamd20_xpro -name: SAM D20 Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - flash - - gpio - - i2c - - spi - - uart - - watchdog -vendor: atmel diff --git a/boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig b/boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig deleted file mode 100644 index 54946deee39..00000000000 --- a/boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD20=y -CONFIG_SOC_PART_NUMBER_SAMD20J18=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAMD20_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamd20_xpro/doc/index.rst b/boards/arm/atsamd20_xpro/doc/index.rst deleted file mode 100644 index b5b6d96eb03..00000000000 --- a/boards/arm/atsamd20_xpro/doc/index.rst +++ /dev/null @@ -1,161 +0,0 @@ -.. _atsamd20_xpro: - -SAM D20 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM D20 Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM D20 Cortex®-M0+ processor-based -microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -.. figure:: img/atsamd20_xpro.jpg - :width: 500px - :align: center - :alt: ATSAMD20-XPRO - - ATSAMD20-XPRO (Credit: `Microchip Technology`_) - -Hardware -******** - -- ATSAMD20J18 ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console - -Supported Features -================== - -The atsamd20_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig`. - -Connections and IOs -=================== - -The `Microchip website`_ has detailed information about board -connections. Download the `SAM D20 Xplained Pro Schematic`_ for more detail. - -System Clock -============ - -The SAMD20 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMD20 MCU has 6 SERCOM based USARTs. One of the USARTs -(SERCOM3) is connected to the onboard Atmel Embedded Debugger (EDBG). -SERCOM4 is available on the EXT1 connector. - -SPI Port -======== - -The SAMD20 MCU has 6 SERCOM based SPIs. On the SAM D20 Xplained Pro, -SERCOM0 is available on the EXT1 connector. - -Programming and Debugging -************************* - -The SAM D20 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMD20 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamd20_xpro - :goals: build - :compact: - -#. Connect the SAM D20 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamd20_xpro - :goals: flash - :compact: - - You should see "Hello World! atsamd20_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip Technology: - https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD20-XPRO - -.. _Microchip website: - https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD20-XPRO - -.. _SAM D20 Xplained Pro Schematic: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD20-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsamd21_xpro/Kconfig.board b/boards/arm/atsamd21_xpro/Kconfig.board deleted file mode 100644 index 4070442f3ca..00000000000 --- a/boards/arm/atsamd21_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM D21 Xplained Pro Board configuration - -# Copyright (c) 2018 Bryan O'Donoghue -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAMD21_XPRO - bool "SAM D21 Xplained Pro" - depends on SOC_PART_NUMBER_SAMD21J18A diff --git a/boards/arm/atsamd21_xpro/Kconfig.defconfig b/boards/arm/atsamd21_xpro/Kconfig.defconfig deleted file mode 100644 index 6ebc627dd1b..00000000000 --- a/boards/arm/atsamd21_xpro/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SAM D21 Xplained Pro board configuration - -# Copyright (c) 2018 Bryan O'Donoghue -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "atsamd21_xpro" - depends on BOARD_ATSAMD21_XPRO diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro.dts b/boards/arm/atsamd21_xpro/atsamd21_xpro.dts deleted file mode 100644 index d65d773a66f..00000000000 --- a/boards/arm/atsamd21_xpro/atsamd21_xpro.dts +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2018 Bryan O'Donoghue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include -#include "atsamd21_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM D21 Xplained Pro"; - compatible = "atsamd21,xpro", "atmel,samd21j18a", "atmel,samd21"; - - chosen { - zephyr,console = &sercom3; - zephyr,shell-uart = &sercom3; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &user_button; - i2c-0 = &sercom2; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&portb 30 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc0 0 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&porta 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&tcc0 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - /* Gives a maximum period of 1.4s */ - prescaler = <4>; - #pwm-cells = <2>; - - pinctrl-0 = <&pwm_default>; - pinctrl-names = "default"; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <9600>; - rxpo = <3>; - txpo = <1>; - - pinctrl-0 = <&sercom0_uart_default>; - pinctrl-names = "default"; -}; - -&sercom1 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <3>; - txpo = <0>; - - pinctrl-0 = <&sercom1_uart_default>; - pinctrl-names = "default"; -}; - -&sercom2 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom2_i2c_default>; - pinctrl-names = "default"; -}; - -&sercom3 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom3_uart_default>; - pinctrl-names = "default"; -}; - -&sercom5 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom5_spi_default>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usb0 { - status = "okay"; - - pinctrl-0 = <&usb_dc_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml b/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml deleted file mode 100644 index 5eebbdfe813..00000000000 --- a/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2018 Bryan O'Donoghue -# SPDX-License-Identifier: Apache-2.0 -identifier: atsamd21_xpro -name: SAM D21 Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - counter - - dma - - gpio - - i2c - - pwm - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: atmel diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig b/boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig deleted file mode 100644 index d7ceba5171d..00000000000 --- a/boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2018 Bryan O'Donoghue -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21J18A=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAMD21_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamd21_xpro/doc/index.rst b/boards/arm/atsamd21_xpro/doc/index.rst deleted file mode 100644 index 78ed6da63ff..00000000000 --- a/boards/arm/atsamd21_xpro/doc/index.rst +++ /dev/null @@ -1,202 +0,0 @@ -.. _atsamd21_xpro: - -SAM D21 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM D21 Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM D21 Cortex®-M0+ processor-based -microcontrollers. The kit includes Atmel's Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -.. figure:: img/atsamd21_xpro.jpg - :width: 500px - :align: center - :alt: ATSAMD21-XPRO - - ATSAMD21-XPRO (Credit: `Microchip Technology`_) - -Hardware -******** - -- ATSAMD21J18 ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console - -Supported Features -================== - -The atsamd21_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - USB - - on-chip - - Universal Serial Bus device ports - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM D21 Xplained Pro evaluation kit has 3 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM D21 Family Datasheet`_ and the `SAM D21 -Xplained Pro Schematic`_. - -.. image:: img/ATSAMD21-XPRO-pinout.jpg - :align: center - :alt: ATSAMD21-XPRO-pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- -- SERCOM0 USART TX : PA10 -- SERCOM0 USART RX : PA11 -- SERCOM1 USART TX : PA16 -- SERCOM1 USART RX : PA19 -- SERCOM2 I2C SDA : PA08 -- SERCOM2 I2C SCL : PA09 -- SERCOM3 USART TX : PA22 -- SERCOM3 USART RX : PA23 -- SERCOM5 SPI MISO : PB16 -- SERCOM5 SPI MOSI : PB22 -- SERCOM5 SPI SCK : PB23 -- USB DP : PA25 -- USB DM : PA24 -- GPIO SPI CS : PB17 -- GPIO/PWM LED0 : PB30 - -System Clock -============ - -The SAMD21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMD21 MCU has six SERCOM based USARTs with three configured as USARTs in -this BSP. SERCOM3 is the default Zephyr console. - -- SERCOM0 9600 8n1 -- SERCOM1 115200 8n1 -- SERCOM3 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) - -PWM -=== - -The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the SAM D21 Xplained Pro, -SERCOM5 is connected to an 8 megabit SPI flash. - -Programming and Debugging -************************* - -The SAM D21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMD21 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the ``hello_world`` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamd21_xpro - :goals: build - :compact: - -#. Connect the SAM D21 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamd21_xpro - :goals: flash - :compact: - - You should see "Hello World! atsamd21_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip Technology: - http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD21-XPRO - -.. _SAM D21 Family Datasheet: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAM-D21-Family-Datasheet-DS40001882C.pdf - -.. _SAM D21 Xplained Pro Schematic: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsame54_xpro/Kconfig.board b/boards/arm/atsame54_xpro/Kconfig.board deleted file mode 100644 index 2d451f1afef..00000000000 --- a/boards/arm/atsame54_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM E54 Xplained Pro Board configuration -# -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAME54_XPRO - bool "SAM E54 Xplained Pro" - depends on SOC_PART_NUMBER_SAME54P20A diff --git a/boards/arm/atsame54_xpro/Kconfig.defconfig b/boards/arm/atsame54_xpro/Kconfig.defconfig deleted file mode 100644 index c955d11d5f6..00000000000 --- a/boards/arm/atsame54_xpro/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# SAM E54 Xplained Pro board configuration -# -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ATSAME54_XPRO - -config BOARD - default "atsame54_xpro" - -if ETH_SAM_GMAC - -# Read MAC address from AT24MAC402 EEPROM - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS - default 0x9A - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE - default 1 - -config ETH_SAM_GMAC_MAC_I2C_EEPROM - default y - select I2C - -endif # ETH_SAM_GMAC - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_ATSAME54_XPRO diff --git a/boards/arm/atsame54_xpro/atsame54_xpro.dts b/boards/arm/atsame54_xpro/atsame54_xpro.dts deleted file mode 100644 index a9bc92ad8a7..00000000000 --- a/boards/arm/atsame54_xpro/atsame54_xpro.dts +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2019 Benjamin Valentin - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "atsame54_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM E54 Xplained Pro"; - compatible = "atsame54,xpro", "atmel,same54p20a", "atmel,same54"; - - chosen { - zephyr,console = &sercom2; - zephyr,shell-uart = &sercom2; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &button0; - i2c-0 = &sercom7; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&portc 18 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc0 2 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&portb 31 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; -}; - -&tcc0 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - /* Gives a maximum period of 1.1s for 120MHz main clock */ - prescaler = <8>; - #pwm-cells = <2>; - - pinctrl-0 = <&pwm_default>; - pinctrl-names = "default"; -}; - -&sercom2 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom2_uart_default>; - pinctrl-names = "default"; -}; - -&sercom4 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <3>; - dopo = <0>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom4_spi_default>; - pinctrl-names = "default"; -}; - -&sercom7 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom7_i2c_default>; - pinctrl-names = "default"; - - eeprom: eeprom@5e { - compatible = "atmel,24mac402"; - reg = <0x5e>; - }; -}; - -&adc0 { - status = "okay"; -}; - -zephyr_udc0: &usb0 { - status = "okay"; - - pinctrl-0 = <&usb_dc_default>; - pinctrl-names = "default"; -}; - -&gmac { - status = "okay"; - - pinctrl-0 = <&gmac_rmii>; - pinctrl-names = "default"; - - mac-eeprom = <&eeprom>; - phy-handle = <&phy>; -}; - -&mdio { - status = "okay"; - - pinctrl-0 = <&mdio_default>; - pinctrl-names = "default"; - - phy: ethernet-phy@0 { - compatible = "ethernet-phy"; - status = "okay"; - reg = <0>; - }; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * The final 16 KiB is reserved for the application. - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@fc000 { - label = "storage"; - reg = <0x000fc000 0x00004000>; - }; - }; -}; diff --git a/boards/arm/atsame54_xpro/atsame54_xpro.yaml b/boards/arm/atsame54_xpro/atsame54_xpro.yaml deleted file mode 100644 index f23ef379363..00000000000 --- a/boards/arm/atsame54_xpro/atsame54_xpro.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 -identifier: atsame54_xpro -name: SAM E54 Xplained Pro -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - flash - - gpio - - pwm - - spi - - i2c - - uart - - usb_device - - netif:eth -vendor: atmel diff --git a/boards/arm/atsame54_xpro/atsame54_xpro_defconfig b/boards/arm/atsame54_xpro/atsame54_xpro_defconfig deleted file mode 100644 index 1fc88370a44..00000000000 --- a/boards/arm/atsame54_xpro/atsame54_xpro_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAME54=y -CONFIG_SOC_PART_NUMBER_SAME54P20A=y -CONFIG_SOC_ATMEL_SAMD5X_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAME54_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsame54_xpro/doc/index.rst b/boards/arm/atsame54_xpro/doc/index.rst deleted file mode 100644 index b6cfd928645..00000000000 --- a/boards/arm/atsame54_xpro/doc/index.rst +++ /dev/null @@ -1,230 +0,0 @@ -.. _atsame54_xpro: - -SAM E54 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM E54 Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM E54 Cortex®-M4F processor-based -microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -.. image:: img/atsame54_xpro.jpg - :align: center - :alt: ATSAME54-XPRO - -Hardware -******** - -- ATSAME54P20A ARM Cortex-M4F processor at 120 MHz -- 32.768 kHz crystal oscillator -- 12 MHz crystal oscillator -- 1024 KiB flash memory and 256 KiB of RAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console -- One QTouch® PTC button -- 32 MiB QSPI Flash -- ATECC508 CryptoAuthentication™ device -- AT24MAC402 serial EEPROM with EUI-48™ MAC address -- Ethernet - - - RJ45 connector with built-in magnetics - - KSZ8091RNA PHY - - 10Base-T/100Base-TX IEE 802.3 compliant Ethernet transceiver - -- USB interface, host, and device -- SD/SDIO card connector - -Supported Features -================== - -The atsame54_xpro board configuration supports the following hardware -features: - -+---------------+------------+----------------------------+ -| Interface | Controller | Driver/Component | -+===============+============+============================+ -| ADC | on-chip | adc | -+---------------+------------+----------------------------+ -| DAC | on-chip | dac | -+---------------+------------+----------------------------+ -| DMAC | on-chip | dma | -+---------------+------------+----------------------------+ -| EEPROM | i2c | eeprom, EUI-48 MAC Address | -+---------------+------------+----------------------------+ -| EIC | on-chip | interrupt_controller | -+---------------+------------+----------------------------+ -| GMAC | on-chip | ethernet, mdio | -+---------------+------------+----------------------------+ -| GPIO | on-chip | gpio | -+---------------+------------+----------------------------+ -| MPU | on-chip | arch/arm | -+---------------+------------+----------------------------+ -| NVIC | on-chip | arch/arm | -+---------------+------------+----------------------------+ -| NVMCTRL | on-chip | flash | -+---------------+------------+----------------------------+ -| PORT | on-chip | pinctrl | -+---------------+------------+----------------------------+ -| RTC | on-chip | timer | -+---------------+------------+----------------------------+ -| SERCOM I2C | on-chip | i2c | -+---------------+------------+----------------------------+ -| SERCOM SPI | on-chip | spi | -+---------------+------------+----------------------------+ -| SERCOM USART | on-chip | serial, console | -+---------------+------------+----------------------------+ -| Serial Number | on-chip | hwinfo | -+---------------+------------+----------------------------+ -| SYSTICK | on-chip | timer | -+---------------+------------+----------------------------+ -| TC | on-chip | counter | -+---------------+------------+----------------------------+ -| TCC | on-chip | counter, pwm | -+---------------+------------+----------------------------+ -| TRNG | on-chip | entropy | -+---------------+------------+----------------------------+ -| USB | on-chip | usb | -+---------------+------------+----------------------------+ -| WDT | on-chip | watchdog | -+---------------+------------+----------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsame54_xpro/atsame54_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM E54 Xplained Pro evaluation kit has 4 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM D5x/E5x Family Datasheet`_ and the `SAM E54 -Xplained Pro Schematic`_. - -.. image:: img/ATSAME54-XPRO-pinout.jpg - :align: center - :alt: ATSAME54-XPRO-pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- -- SERCOM2 USART TX : PB24 -- SERCOM2 USART RX : PB25 -- GPIO/PWM LED0 : PC18 -- GPIO SW0 : PB31 -- GMAC RMII REFCK : PA14 -- GMAC RMII TXEN : PA17 -- GMAC RMII TXD0 : PA18 -- GMAC RMII TXD1 : PA19 -- GMAC RMII CRSDV : PC20 -- GMAC RMII RXD0 : PA13 -- GMAC RMII RXD1 : PA12 -- GMAC RMII RXER : PA15 -- GMAC MDIO MDC : PC11 -- GMAC MDIO MDIO : PC12 -- SERCOM4 SPI SCK : PB26 -- SERCOM4 SPI MOSI : PB27 -- SERCOM4 SPI MISO : PB29 -- SERCOM7 I2C SDA : PD08 -- SERCOM7 I2C SCL : PD09 -- USB DP : PA25 -- USB DM : PA24 - -System Clock -============ - -The SAME54 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAME54 MCU has 8 SERCOM based USARTs with one configured as USARTs in -this BSP. SERCOM2 is the default Zephyr console. - -- SERCOM2 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) - -PWM -=== - -The SAME54 MCU has 5 TCC based PWM units with up to 6 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAME54 MCU has 8 SERCOM based SPIs. - -I2C Port -======== - -The SAME54 MCU has 8 SERCOM based I2Cs. On the SAM E54 Xplained Pro, -SERCOM7 is connected to a AT24MAC402 EEPROM and a ATECC508A Crypto -Authentication device. - -Programming and Debugging -************************* - -The SAM E54 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAME54 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the ``hello_world`` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsame54_xpro - :goals: build - :compact: - -#. Connect the SAM E54 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsame54_xpro - :goals: flash - :compact: - - You should see "Hello World! atsame54_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip website: - http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAME54-XPRO - -.. _SAM D5x/E5x Family Datasheet: - http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf - -.. _SAM E54 Xplained Pro Schematic: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAME54-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsaml21_xpro/Kconfig.board b/boards/arm/atsaml21_xpro/Kconfig.board deleted file mode 100644 index a06c9e3d20a..00000000000 --- a/boards/arm/atsaml21_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM L21 Xplained Pro board configuration - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAML21_XPRO - bool "SAM L21 Xplained Pro" - depends on SOC_PART_NUMBER_SAML21J18B diff --git a/boards/arm/atsaml21_xpro/Kconfig.defconfig b/boards/arm/atsaml21_xpro/Kconfig.defconfig deleted file mode 100644 index 3c35f327bb2..00000000000 --- a/boards/arm/atsaml21_xpro/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SAM L21 Xplained Pro board configuration - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "atsaml21_xpro" - depends on BOARD_ATSAML21_XPRO diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro.dts b/boards/arm/atsaml21_xpro/atsaml21_xpro.dts deleted file mode 100644 index ee800d7ae95..00000000000 --- a/boards/arm/atsaml21_xpro/atsaml21_xpro.dts +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2021 Argentum Systems Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "atsaml21_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM L21 Xplained Pro"; - compatible = "atsaml21,xpro", "atmel,saml21j18b", "atmel,saml21"; - - chosen { - zephyr,console = &sercom3; - zephyr,shell-uart = &sercom3; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &user_button; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&portb 10 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc0 0 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&porta 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = <48000000>; -}; - -&adc { - status = "okay"; -}; - -&tcc0 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - /* Gives a maximum period of 1.4s */ - prescaler = <4>; - #pwm-cells = <2>; - - pinctrl-0 = <&tcc0_default>; - pinctrl-names = "default"; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom0_default>; - pinctrl-names = "default"; -}; - -&sercom1 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <3>; - txpo = <0>; - - pinctrl-0 = <&sercom1_default>; - pinctrl-names = "default"; -}; - -&sercom2 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom2_default>; - pinctrl-names = "default"; -}; - -&sercom3 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom3_default>; - pinctrl-names = "default"; -}; - -&sercom4 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom4_default>; - pinctrl-names = "default"; -}; - -&sercom5 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom5_default>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usb0 { - status = "okay"; - - pinctrl-0 = <&usb0_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro.yaml b/boards/arm/atsaml21_xpro/atsaml21_xpro.yaml deleted file mode 100644 index 03c5c226209..00000000000 --- a/boards/arm/atsaml21_xpro/atsaml21_xpro.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 -identifier: atsaml21_xpro -name: SAM L21 Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - counter - - dma - - gpio - - i2c - - pwm - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: atmel diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig b/boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig deleted file mode 100644 index 13ee4a48190..00000000000 --- a/boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAML21=y -CONFIG_SOC_PART_NUMBER_SAML21J18B=y -CONFIG_SOC_ATMEL_SAML_XOSC32K=y -CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAML21_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsaml21_xpro/doc/index.rst b/boards/arm/atsaml21_xpro/doc/index.rst deleted file mode 100644 index 5c55f23d587..00000000000 --- a/boards/arm/atsaml21_xpro/doc/index.rst +++ /dev/null @@ -1,198 +0,0 @@ - .. _atsaml21_xpro: - -SAM L21 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM L21 Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM L21 Cortex®-M0+ processor-based -microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -.. image:: img/atsaml21-xpro.jpg - :align: center - :alt: ATSAML21-XPRO - -Hardware -******** - -- ATSAML21J18 ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console - -Supported Features -================== - -The atsaml21_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - TRNG - - on-chip - - True Random Number Generator - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM L21 Xplained Pro evaluation kit has 2 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM L21 Family Datasheet`_ and the `SAM L21 -Xplained Pro Schematic`_. - -.. image:: img/atsaml21-xpro-pinout.jpg - :align: center - :alt: ATSAML21-XPRO-pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- -- SERCOM0 SPI MISO : PA04 -- SERCOM0 SPI MOSI : PA06 -- SERCOM0 SPI SCK : PA07 -- SERCOM1 USART TX : PA18 -- SERCOM1 USART RX : PA19 -- SERCOM2 I2C SDA : PA08 -- SERCOM2 I2C SCL : PA09 -- SERCOM3 USART TX : PA22 -- SERCOM3 USART RX : PA23 -- SERCOM4 USART TX : PB08 -- SERCOM4 USART RX : PB09 -- SERCOM5 SPI MISO : PB16 -- SERCOM5 SPI MOSI : PB22 -- SERCOM5 SPI SCK : PB23 -- USB DP : PA25 -- USB DM : PA24 -- GPIO SPI CS : PB17 -- GPIO/PWM LED0 : PB10 - -System Clock -============ - -The SAML21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAML21 MCU has six SERCOM based USARTs with two configured as USARTs in -this BSP. SERCOM3 is the default Zephyr console. - -- SERCOM1 115200 8n1 - connected to EXT2 and EXT3 -- SERCOM3 115200 8n1 - connected to the onboard Atmel Embedded Debugger (EDBG) -- SERCOM4 115200 8n1 - connected to EXT1 - -PWM -=== - -The SAML21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAML21 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. - -- SERCOM0 - connected to EXT1 -- SERCOM5 - connected to EXT2 and EXT3 - -Programming and Debugging -************************* - -The SAM L21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAML21 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the ``hello_world`` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsaml21_xpro - :goals: build - :compact: - -#. Connect the SAM L21 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ picocom -b 115200 /dev/ttyACM0 - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsaml21_xpro - :goals: flash - :compact: - - You should see "Hello World! atsaml21_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip website: - https://www.microchip.com/en-us/development-tool/atsaml21-xpro-b - -.. _SAM L21 Family Datasheet: - https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_L21_Family_DataSheet_DS60001477C.pdf - -.. _SAM L21 Xplained Pro Schematic: - https://ww1.microchip.com/downloads/en/DeviceDoc/SAML21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsamr21_xpro/Kconfig.board b/boards/arm/atsamr21_xpro/Kconfig.board deleted file mode 100644 index 0293b0416f0..00000000000 --- a/boards/arm/atsamr21_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM R21 Xplained Pro Board configuration - -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAMR21_XPRO - bool "SAM R21 Xplained Pro" - depends on SOC_PART_NUMBER_SAMR21G18A diff --git a/boards/arm/atsamr21_xpro/Kconfig.defconfig b/boards/arm/atsamr21_xpro/Kconfig.defconfig deleted file mode 100644 index 4f0b72b150b..00000000000 --- a/boards/arm/atsamr21_xpro/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SAM R21 Xplained Pro board configuration - -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ATSAMR21_XPRO - -config BOARD - default "atsamr21_xpro" - -endif # BOARD_ATSAMR21_XPRO diff --git a/boards/arm/atsamr21_xpro/atsamr21_xpro.dts b/boards/arm/atsamr21_xpro/atsamr21_xpro.dts deleted file mode 100644 index 86981d86cfe..00000000000 --- a/boards/arm/atsamr21_xpro/atsamr21_xpro.dts +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2019 Benjamin Valentin - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "atsamr21_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM R21 Xplained Pro"; - compatible = "atsamr21,xpro", "atmel,samr21g18a", "atmel,samr21"; - - chosen { - zephyr,console = &sercom0; - zephyr,shell-uart = &sercom0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,ieee802154 = &ieee802154; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &user_button; - i2c-0 = &sercom1; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&porta 19 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc0 3 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&porta 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; - - ext1_header: xplained-pro-connector1 { - compatible = "atmel-xplained-pro-header"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &porta 6 0>, /* ADC6 */ - <1 0 &porta 7 0>, /* ADC7 */ - <2 0 &porta 13 0>, /* GPIO */ - <3 0 &porta 28 0>, /* GPIO */ - <4 0 &porta 18 0>, /* PWM_T0_W2 */ - <5 0 &porta 19 0>, /* PWM_T0_W3 */ - <6 0 &porta 22 0>, /* GPIO */ - <7 0 &porta 23 0>, /* GPIO */ - <8 0 &porta 16 0>, /* TWD1 EXT2 */ - <9 0 &porta 17 0>, /* TWCK1 EXT2 */ - <10 0 &porta 5 0>, /* RXD0 */ - <11 0 &porta 4 0>, /* TXD0 */ - <12 0 &portb 3 0>, /* SPI5(SS) */ - <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ - <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ - <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ - }; - - ext2_header: xplained-pro-connector2 { - compatible = "atmel-xplained-pro-header"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = /*<0 0 - - 0>, - */ - /*<1 0 - - 0>, - */ - <2 0 &porta 15 0>, /* GPIO */ - /*<3 0 - - 0>, - */ - /*<4 0 - - 0>, - */ - /*<5 0 - - 0>, - */ - /*<6 0 - - 0>, - */ - <7 0 &porta 8 0>, /* GPIO */ - <8 0 &porta 16 0>, /* TWD1 EXT1 */ - <9 0 &porta 17 0>, /* TWCK1 EXT1 */ - /*<11 0 - - 0>, - */ - /*<12 0 - - 0>, - */ - <12 0 &porta 14 0>, /* GPIO */ - <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ - <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ - <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ - }; -}; - -&cpu0 { - clock-frequency = <48000000>; -}; - -&tcc0 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - prescaler = <4>; - #pwm-cells = <2>; - - pinctrl-0 = <&pwm_default>; - pinctrl-names = "default"; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom0_uart_default>; - pinctrl-names = "default"; -}; - -&sercom1 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom1_i2c_default>; - pinctrl-names = "default"; -}; - -&sercom4 { - status = "okay"; - compatible = "atmel,sam0-spi"; - /* - * CS-PB31; MOSI-PB30; MISO-PC19; SCLK-PC18 - * PAD[1]; PAD[2]; PAD[0]; PAD[3] - */ - dipo = <0>; - dopo = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom4_spi_default>; - pinctrl-names = "default"; - - cs-gpios = <&portb 31 GPIO_ACTIVE_LOW>; - - ieee802154: rf2xx@0 { - compatible = "atmel,rf2xx"; - reg = <0x0>; - spi-max-frequency = <6000000>; - irq-gpios = <&portb 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; - reset-gpios = <&portb 15 GPIO_ACTIVE_LOW>; - slptr-gpios = <&porta 20 GPIO_ACTIVE_HIGH>; - dig2-gpios = <&portb 17 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; - status = "okay"; - tx-pwr-min = [01 11]; /* -17.0 dBm */ - tx-pwr-max = [00 04]; /* 4.0 dBm */ - tx-pwr-table = [00 01 03 04 05 05 06 06 - 07 07 07 08 08 09 09 0a - 0a 0a 0b 0b 0b 0b 0c 0c - 0c 0c 0d 0d 0d 0d 0d 0d - 0d 0d 0e 0e 0e 0e 0e 0e - 0e 0e 0e 0e 0e 0e 0f 0f]; - }; -}; - -&sercom5 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom5_spi_default>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usb0 { - status = "okay"; - - pinctrl-0 = <&usb_dc_default>; - pinctrl-names = "default"; -}; - -ext1_spi: &sercom5 { -}; - -ext1_i2c: &sercom1 { -}; - -ext1_serial: &sercom0 { -}; - -ext2_spi: &sercom5 { -}; - -ext2_i2c: &sercom1 { -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * The final 16 KiB is reserved for the application. - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@3c000 { - label = "storage"; - reg = <0x0003c000 0x00004000>; - }; - }; -}; diff --git a/boards/arm/atsamr21_xpro/atsamr21_xpro.yaml b/boards/arm/atsamr21_xpro/atsamr21_xpro.yaml deleted file mode 100644 index 04608ed2afb..00000000000 --- a/boards/arm/atsamr21_xpro/atsamr21_xpro.yaml +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2019-2020 Gerson Fernando Budke -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 -identifier: atsamr21_xpro -name: SAM R21 Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - flash - - gpio - - i2c - - netif - - pwm - - spi - - uart - - usb_device - - xpro_gpio - - xpro_i2c - - xpro_serial - - xpro_spi -vendor: atmel diff --git a/boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig b/boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig deleted file mode 100644 index 7437bfc1ca0..00000000000 --- a/boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2019 Benjamin Valentin -# Copyright (c) 2019 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMR21=y -CONFIG_SOC_PART_NUMBER_SAMR21G18A=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAMR21_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamr21_xpro/doc/index.rst b/boards/arm/atsamr21_xpro/doc/index.rst deleted file mode 100644 index 60d2c36ea32..00000000000 --- a/boards/arm/atsamr21_xpro/doc/index.rst +++ /dev/null @@ -1,225 +0,0 @@ -.. _atsamr21_xpro: - -SAM R21 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM R21 Xplained Pro is a compact evaluation board by Atmel featuring a -ATSAMR21G18A SoC. The SoC includes a SAMR21 ARM Cortex-M0+ micro-controller -bundled with Atmel's AT86RF233, a 2.4GHz IEEE802.15.4 compatible radio. -The kit includes Atmel’s Embedded Debugger (EDBG), which provides a full -debug interface without the need for additional hardware. - -.. image:: img/atsamr21_xpro.jpg - :align: center - :alt: ATSAMR21-XPRO - -Hardware -******** - -- ATSAMR21G18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console - -Supported Features -================== - -The atsamr21_xpro board configuration supports the following hardware -features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+--------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+--------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+--------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+--------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+--------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+--------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+--------------------------------------+ -| I2C | on-chip | I2C Peripheral Interface ports | -+-----------+------------+--------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM R21 Xplained Pro evaluation kit has 3 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM R21 Family Datasheet`_ and the `SAM R21 -Xplained Pro Schematic`_. - -.. image:: img/ATSAMR21-XPRO-pinout.jpg - :align: center - :alt: ATSAMR21-XPRO-pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- -- SERCOM0 USART TX : PA5 -- SERCOM0 USART RX : PA4 -- SERCOM1 I2C SDA : PA16 -- SERCOM1 I2C SCL : PA17 -- SERCOM5 SPI MISO : PB02 -- SERCOM5 SPI MOSI : PB22 -- SERCOM5 SPI SCK : PB23 -- GPIO SPI CS : PB03 -- GPIO/PWM LED0 : PA19 - -System Clock -============ - -The SAMR21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMR21 MCU has six SERCOM based USARTs with two configured as USARTs in -this BSP. SERCOM0 is the default Zephyr console. - -- SERCOM0 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) - -PWM -=== - -The SAMR21 MCU has 3 TCC based PWM units with up to 4 outputs each and a -period of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then -LED0 is driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAMR21 MCU has 6 SERCOM based SPIs. - -- SERCOM5 is exposed via Xplained Pro Standard Extension Header - -I2C Port -======== - -When connecting an I2C device and a logic analyzer to an I2C port at the same -time, the internal pull-up resistors are not sufficient for stable bus -operation. You probably have to connect external pull-ups to both bus lines. 10K -is a good value to start with. - -- SERCOM1 is exposed via Xplained Pro Standard Extension Header - -Radio -===== - -The SAMR21 SoC includes an on-chip AT86RF233 radio. It is internally -connected via SPI and some GPIO pins and behaves the same way as -externally connected SPI devices. - -+-------------+------------------------------------------------------------------------------------------+ -| Sensor | AT86RF233 | -+=============+==========================================================================================+ -| Type | 2.4GHz IEEE802.15.4 radio | -+-------------+------------------------------------------------------------------------------------------+ -| Vendor | Atmel | -+-------------+------------------------------------------------------------------------------------------+ -| Datasheet |`Datasheet `_| -+-------------+------------------------------------------------------------------------------------------+ -| connected to| SPI_0 | -+-------------+------------------------------------------------------------------------------------------+ -| Pin Config: | -+-------------+------------------------------------------------------------------------------------------+ -| Device | SERCOM4 | -+-------------+------------------------------------------------------------------------------------------+ -| MOSI | PB30 (OUT, SPI MOSI) | -+-------------+------------------------------------------------------------------------------------------+ -| MISO | PC19 (IN, SPI MISO) | -+-------------+------------------------------------------------------------------------------------------+ -| SCLK | PC18 (OUT, SPI SCLK) | -+-------------+------------------------------------------------------------------------------------------+ -| CS | PB31 (OUT, GPIO output) | -+-------------+------------------------------------------------------------------------------------------+ -| IRQ | PB00 (IN, GPIO external interrupt) | -+-------------+------------------------------------------------------------------------------------------+ -| RSTN | PB15 (OUT, GPIO output) | -+-------------+------------------------------------------------------------------------------------------+ -| SLP_TR | PA20 (OUT, GPIO output) | -+-------------+------------------------------------------------------------------------------------------+ - -Zephyr provide several samples that can use this technology. You can check -:zephyr:code-sample:`wpan-usb` and :zephyr:code-sample:`wpan-serial` examples as starting -points. Another good test can be done with IPv6 by using the server/client -echo demo. More information at :zephyr:code-sample:`sockets-echo-server` and -:zephyr:code-sample:`sockets-echo-client`. - -Programming and Debugging -************************* - -The SAM R21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMR21 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamr21_xpro - :goals: build - :compact: - -#. Connect the SAM R21 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamr21_xpro - :goals: flash - :compact: - - You should see "Hello World! atsamr21_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip website: - http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMR21-XPRO - -.. _SAM R21 Family Datasheet: - http://ww1.microchip.com/downloads/en/devicedoc/sam-r21_datasheet.pdf - -.. _SAM R21 Xplained Pro Schematic: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAMR21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsamr34_xpro/Kconfig.board b/boards/arm/atsamr34_xpro/Kconfig.board deleted file mode 100644 index d586efcbc7e..00000000000 --- a/boards/arm/atsamr34_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM R34 Xplained Pro board configuration - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAMR34_XPRO - bool "SAM R34 Xplained Pro" - depends on SOC_PART_NUMBER_SAMR34J18B diff --git a/boards/arm/atsamr34_xpro/Kconfig.defconfig b/boards/arm/atsamr34_xpro/Kconfig.defconfig deleted file mode 100644 index e327820655a..00000000000 --- a/boards/arm/atsamr34_xpro/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SAM R34 Xplained Pro board configuration - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "atsamr34_xpro" - depends on BOARD_ATSAMR34_XPRO diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro.dts b/boards/arm/atsamr34_xpro/atsamr34_xpro.dts deleted file mode 100644 index fe0ae80ae35..00000000000 --- a/boards/arm/atsamr34_xpro/atsamr34_xpro.dts +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2021 Argentum Systems Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "atsamr34_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM R34 Xplained Pro"; - compatible = "atmel,atsamr34xpro", "atmel,samr34j18b", "atmel,samr34"; - - chosen { - zephyr,console = &sercom0; - zephyr,shell-uart = &sercom0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &user_button; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&porta 19 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc0 3 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&porta 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = <48000000>; -}; - -&adc { - status = "okay"; -}; - -&tcc0 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - /* Gives a maximum period of 1.4s */ - prescaler = <4>; - #pwm-cells = <2>; - - pinctrl-0 = <&tcc0_default>; - pinctrl-names = "default"; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom0_default>; - pinctrl-names = "default"; -}; - -&sercom1 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom1_default>; - pinctrl-names = "default"; -}; - -/* SERCOM4 is used for the internal LoRa radio */ -&sercom4 { - status = "okay"; -}; - -&lora { - status = "okay"; - - tcxo-power-gpios = <&porta 9 GPIO_ACTIVE_HIGH>; /* TCXO_PWR */ - tcxo-power-startup-delay-ms = <5>; - rfi-enable-gpios = <&porta 13 GPIO_ACTIVE_HIGH>; /* BAND_SEL */ - rfo-enable-gpios = <&porta 13 GPIO_ACTIVE_HIGH>; /* BAND_SEL */ -}; - -&sercom5 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom5_default>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usb0 { - status = "okay"; - - pinctrl-0 = <&usb0_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro.yaml b/boards/arm/atsamr34_xpro/atsamr34_xpro.yaml deleted file mode 100644 index fb5c574b321..00000000000 --- a/boards/arm/atsamr34_xpro/atsamr34_xpro.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 -identifier: atsamr34_xpro -name: SAM R34 Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - counter - - dma - - gpio - - i2c - - pwm - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: atmel diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig b/boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig deleted file mode 100644 index ca12a0ed69e..00000000000 --- a/boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMR34=y -CONFIG_SOC_PART_NUMBER_SAMR34J18B=y -CONFIG_SOC_ATMEL_SAML_XOSC32K=y -CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAMR34_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamr34_xpro/doc/index.rst b/boards/arm/atsamr34_xpro/doc/index.rst deleted file mode 100644 index 6347b50dedb..00000000000 --- a/boards/arm/atsamr34_xpro/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ - .. _atsamr34_xpro: - -SAM R34 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM R34 Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM R34 Cortex®-M0+ processor-based -microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -The SAMR34 and SAMR35 parts are produced as a System-in-Package (SiP), -including both a SAML21 die, and a Semtech SX1276 LoRa radio die. - -This board is also referred to as DM320111. - -.. image:: img/atsamr34-xpro.jpg - :align: center - :alt: ATSAMR34-XPRO - -Hardware -******** - -- ATSAMR34J18 ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console - -Supported Features -================== - -The atsamr34_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - TRNG - - on-chip - - True Random Number Generator - -The following hardware features are supported by Zephyr, but not yet fully -supported by the SOC: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - LoRa Radio - - on-chip - - Internal SX1276 LoRa Radio - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM R34 Xplained Pro evaluation kit has 3 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM R34 Family Datasheet`_ and the `SAM R34 -Xplained Pro Schematic`_. - -.. image:: img/atsamr34-xpro-pinout.jpg - :align: center - :alt: ATSAMR34-XPRO-pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- -- SERCOM0 UART TX : PA04 -- SERCOM0 UART RX : PA05 -- SERCOM1 I2C SDA : PA16 -- SERCOM1 I2C SCL : PA17 -- SERCOM4 SPI MISO : PC19 -- SERCOM4 SPI MOSI : PB30 -- SERCOM4 SPI SCK : PC18 -- SERCOM4 GPIO CS : PB31 -- SERCOM5 SPI MISO : PB02 -- SERCOM5 SPI MOSI : PB22 -- SERCOM5 SPI SCK : PB23 -- SERCOM5 GPIO CS0 : PA23 -- SERCOM5 GPIO CS1 : PA14 -- USB DP : PA25 -- USB DM : PA24 -- GPIO/PWM LED0 : PA19 - -System Clock -============ - -The SAMR34 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMR34 MCU has six SERCOM based USARTs with one configured as USART in -this BSP. SERCOM0 is the default Zephyr console. - -- SERCOM0 115200 8n1 - connected to the onboard Atmel Embedded Debugger (EDBG) - -PWM -=== - -The SAMR34 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAMR34 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. - -- SERCOM4 - connected to the internal LoRa radio -- SERCOM5 - connected to EXT1 and EXT3 - -Programming and Debugging -************************* - -The SAM R34 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMR34 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the ``hello_world`` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamr34_xpro - :goals: build - :compact: - -#. Connect the SAM R34 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ picocom -b 115200 /dev/ttyACM0 - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamr34_xpro - :goals: flash - :compact: - - You should see "Hello World! atsamr34_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip website: - https://www.microchip.com/en-us/development-tool/dm320111 - -.. _SAM L21 Family Datasheet: - https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_L21_Family_DataSheet_DS60001477C.pdf - -.. _SAM R34 Family Datasheet: - https://ww1.microchip.com/downloads/en/DeviceDoc/SAM-R34-R35-Low-Power-LoRa-Sub-GHz-SiP-Data-Sheet-DS70005356C.pdf - -.. _SAM R34 Xplained Pro Schematic: - https://ww1.microchip.com/downloads/Secure/en/DeviceDoc/SAMR34_SiP_Reference_Design_Package_V3.0.exe - -.. _Semtech SX1276: - https://www.semtech.com/products/wireless-rf/lora-transceivers/sx1276 diff --git a/boards/arm/az3166_iotdevkit/Kconfig.board b/boards/arm/az3166_iotdevkit/Kconfig.board deleted file mode 100644 index 4750477ac43..00000000000 --- a/boards/arm/az3166_iotdevkit/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# MXChip AZ3166 DevKit board configuration - -# Copyright (c) 2023 Benjamin Cabé -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_AZ3166_DEVKIT - bool "MXChip AZ3166 DevKit" - depends on SOC_STM32F412RX diff --git a/boards/arm/az3166_iotdevkit/Kconfig.defconfig b/boards/arm/az3166_iotdevkit/Kconfig.defconfig deleted file mode 100644 index af040b8a58d..00000000000 --- a/boards/arm/az3166_iotdevkit/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# MXChip AZ3166 DevKit board configuration - -# Copyright (c) 2023 Benjamin Cabé -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_AZ3166_DEVKIT - -config BOARD - default "az3166_devkit" - -choice HTS221_TRIGGER_MODE - default HTS221_TRIGGER_NONE -endchoice - -endif # BOARD_AZ3166_DEVKIT diff --git a/boards/arm/b_g474e_dpow1/Kconfig.board b/boards/arm/b_g474e_dpow1/Kconfig.board deleted file mode 100644 index 405ce71cb7b..00000000000 --- a/boards/arm/b_g474e_dpow1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# B-G474E-DPOW1 Discovery board configuration - -# Copyright 2022 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_B_G474E_DPOW1 - bool "B-G474E-DPOW1 Discovery Board" - depends on SOC_STM32G474XX diff --git a/boards/arm/b_g474e_dpow1/Kconfig.defconfig b/boards/arm/b_g474e_dpow1/Kconfig.defconfig deleted file mode 100644 index 88bcf769528..00000000000 --- a/boards/arm/b_g474e_dpow1/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# B-G474E-DPOW1 Discovery board configuration - -# Copyright 2022 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_B_G474E_DPOW1 - -config BOARD - default "b_g474e_bpow1" - -endif # BOARD_B_G474E_DPOW1 diff --git a/boards/arm/b_g474e_dpow1/doc/index.rst b/boards/arm/b_g474e_dpow1/doc/index.rst deleted file mode 100644 index 75d99572fbf..00000000000 --- a/boards/arm/b_g474e_dpow1/doc/index.rst +++ /dev/null @@ -1,159 +0,0 @@ -.. _b_g474e_dpow1_board: - -ST B-G474E-DPOW1 Discovery -########################## - -Overview -******** -The B-G474E-DPOW1 Discovery kit is a digital power solution and a complete -demonstration and development platform for the STMicroelectronics STM32G474RET6 -microcontroller. Leveraging the new HRTimer-oriented features, 96 Kbytes of -embedded RAM, math accelerator functions and USB-PD 3.0 offered by STM32G474RET6, -the B-G474E-DPOW1 Discovery kit, based on the USB 2.0 FS Type-C™ connector -interface, helps the user to prototype applications with digital power such as a -buck-boost converter, RGB power LED lighting or a class-D audio amplifier. The -B-G474E-DPOW1 Discovery kit does not require any separate probe, as it integrates -the STLINK-V3E debugger and programmer. - -- STM32G474RET6 Arm® Cortex®-M4 core-based microcontroller, featuring 512 Kbytes - of Flash memory and 128 Kbytes of SRAM, in LQFP64 package -- USB Type-C™ with USB 2.0 FS interface compatible with USB-PD 3.0 -- RGB power LED for a bright lighting -- Digital power buck-boost converter with internal or external Input voltage and - with onboard resistor loads -- Audio Class-D amplifier capable -- 4 user LEDs -- 3 LEDs for power and ST-LINK communication -- 4-direction joystick with a selection button -- Reset push-button -- Board connectors: - - USB Type-C™ - - USB Micro-B - - 2 x 32-pin header, 2.54 mm pitch, daughterboard extension connector for breadboard connection -- Flexible power-supply options: ST-LINK USB VBUS or USB Type-C™ VBUS or external source -- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: mass storage, - Virtual COM port, and debug port - -.. image:: img/b_g474e_dpow1.jpg - :align: center - :alt: B-G474E-DPOW1 - -More information about the board can be found at the `B-G474E-DPOW1 website`_. - - -More information about STM32G474RE can be found here: -- `G474RE on www.st.com`_ -- `STM32G4 reference manual`_ - - -Supported Features -================== - -The Zephyr b_g474e_dpow1 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| UCPD | on-chip | ucpd | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/b_g474e_dpow1/b_g474e_dpow1_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) -- BUTTON (JOY_SEL) : PC13 -- BUTTON (JOY_LEFT) : PC4 -- BUTTON (JOY_DOWN) : PC5 -- BUTTON (JOY_RIGHT) : PB2 -- BUTTON (JOY_UP) : PB10 -- LED (DOWN BLUE) : PA15 -- LED (LEFT ORANGE) : PB1 -- LED (UP RED) : PB5 -- LED (RIGHT GREEN) : PB7 -- USB DM : PA11 -- USB DP : PA12 -- UCPD CC2 : PB4 -- UCPD CC1 : PB6 - -For more details please refer to `B-G474E-DPOW1 Discovery board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``b_g474e_dpow1`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -The B-G474E-DPOW1 Discovery board includes an ST-LINK/V3E embedded debug tool interface. - -.. code-block:: console - - $ west flash - -Flashing an application to the B_G474E_DPOW1 --------------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: b_g474e_dpow1 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_g474e_dpow1 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _B-G474E-DPOW1 website: - https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html - -.. _STM32G4 reference manual: - https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _B-G474E-DPOW1 Discovery board User Manual: - https://www.st.com/resource/en/user_manual/um2577-discovery-kit-with-stm32g474re-mcu-stmicroelectronics.pdf - -.. _G474RE on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32g474re.html diff --git a/boards/arm/b_l072z_lrwan1/Kconfig.board b/boards/arm/b_l072z_lrwan1/Kconfig.board deleted file mode 100644 index 27f6dfe2bd2..00000000000 --- a/boards/arm/b_l072z_lrwan1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STMicroelectronics B-L072Z-LRWAN1 Discovery board configuration - -# Copyright (c) 2018 Aleksandr Makarov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_B_L072Z_LRWAN1 - bool "STMicroelectronics B-L072Z-LRWAN1 Discovery kit" - depends on SOC_STM32L072XX diff --git a/boards/arm/b_l072z_lrwan1/Kconfig.defconfig b/boards/arm/b_l072z_lrwan1/Kconfig.defconfig deleted file mode 100644 index 9e221e7d7f6..00000000000 --- a/boards/arm/b_l072z_lrwan1/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STMicroelectronics B-L072Z-LRWAN1 Discovery board configuration - -# Copyright (c) 2018 Aleksandr Makarov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_B_L072Z_LRWAN1 - -config BOARD - default "b_l072z_lrwan1" - -endif # BOARD_B_L072Z_LRWAN1 diff --git a/boards/arm/b_l072z_lrwan1/b_l072z_lrwan1_defconfig b/boards/arm/b_l072z_lrwan1/b_l072z_lrwan1_defconfig deleted file mode 100644 index cd14c09d3a6..00000000000 --- a/boards/arm/b_l072z_lrwan1/b_l072z_lrwan1_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L072XX=y -CONFIG_BOARD_B_L072Z_LRWAN1=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/b_l072z_lrwan1/doc/index.rst b/boards/arm/b_l072z_lrwan1/doc/index.rst deleted file mode 100644 index a45ead85652..00000000000 --- a/boards/arm/b_l072z_lrwan1/doc/index.rst +++ /dev/null @@ -1,250 +0,0 @@ -.. _b_l072z_lrwan1_board: - -ST B-L072Z-LRWAN1 Discovery kit -############################### - -Overview -******** - -This Discovery kit features an all-in-one open module CMWX1ZZABZ-091 (by Murata). -The module is powered by an STM32L072CZ and an SX1276 transceiver. - -This kit provides: - -- CMWX1ZZABZ-091 LoRa* / Sigfox* module (Murata) - - - Embedded ultra-low-power STM32L072CZ Series MCUs, based on - Arm* Cortex* -M0+ core, with 192 Kbytes of Flash - memory, 20 Kbytes of RAM, 6 Kbytes of EEPROM - - Frequency range: 860 MHz - 930 MHz - - USB 2.0 FS - - 4-channel,12-bit ADC, 2xDAC - - 6-bit timers, LP-UART, I2C and SPI - - Embedded SX1276 transceiver - - LoRa* , FSK, GFSK, MSK, GMSK and OOK modulations (+ Sigfox* compatibility) - - +14 dBm or +20 dBm selectable output power - - 157 dB maximum link budget - - Programmable bit rate up to 300 kbit/s - - High sensitivity: down to -137 dBm - - Bullet-proof front end: IIP3 = -12.5 dBm - - 89 dB blocking immunity - - Low Rx current of 10 mA, 200 nA register retention - - Fully integrated synthesizer with a resolution of 61 Hz - - Built-in bit synchronizer for clock recovery - - Sync word recognition - - Preamble detection - - 127 dB+ dynamic range RSSI - -- SMA and U.FL RF interface connectors -- Including 50 ohm SMA RF antenna -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability - -- USB ST-LINK functions: -- Board power supply: - - - Through USB bus or external VIN/3.3 V supply voltage or batteries -- 3xAAA-type-battery holder for standalone operation -- 7 LEDs: - - - 4 general-purpose LEDs - - A 5 V-power LED - - An ST-LINK-communication LED - - A fault-power LED - - 2 push-buttons (user and reset) -- Arduino* Uno V3 connectors - -.. image:: img/b_l072z_lrwan1.jpg - :align: center - :alt: B-L072Z-LRWAN1 - -More information about the board can be found at the `B-L072Z-LRWAN1 website`_. - -Hardware -******** - -The STM32L072CZ SoC provides the following hardware IPs: - -- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) -- Core: ARM* 32-bit Cortex*-M0+ CPU, frequency up to 32 MHz -- Clock Sources: - - - 1 to 32 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 37 kHz RC ( |plusminus| 5%) - - Internal multispeed low-power 65 kHz to 4.2 MHz RC -- RTC with HW calendar, alarms and calibration -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 11x timers: - - - 2x 16-bit with up to 4 channels - - 2x 16-bit with up to 2 channels - - 1x 16-bit ultra-low-power timer - - 1x SysTick - - 1x RTC - - 2x 16-bit basic for DAC - - 2x watchdogs (independent/window) -- Up to 84 fast I/Os, most 5 V-tolerant. -- Memories - - - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 20 KB of SRAM - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 1.14 MSPS - - 2x 12-bit DAC - - 2x ultra-low-power comparators -- 11x communication interfaces - - - USB 2.0 full-speed device, LPM and BCD - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 6x SPIs (4x SPIs with the Quad SPI) -- 7-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32L072CZ can be found here: - -- `STM32L072CZ on www.st.com`_ -- `STM32L0x2 reference manual`_ - -Supported Features -================== - -The Zephyr B-L072Z-LRWAN1 Discovery board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | true random number generator | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| LoRa | on-module | sx1276 | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/b_l072z_lrwan1/b_l072z_lrwan1_defconfig`` - - -Connections and IOs -=================== - -B-L072Z-LRWAN1 Discovery kit has GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- - -For detailed information about available pins please refer to `B-L072Z-LRWAN1 website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX/RX: PA9/PA10 (Arduino Serial) -- UART_2_TX/RX: PA2/PA3 (ST-Link Virtual COM Port) -- SPI1 NSS/SCK/MISO/MOSI: PA15/PB3/PA6/PA7 (Semtech SX1276 LoRa* Transceiver) -- SPI2 NSS/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 (Arduino SPI) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) - -System Clock ------------- - -B-L072Z-LRWAN1 Discovery board System Clock is at 32MHz. - -Serial Port ------------ - -B-L072Z-LRWAN1 Discovery board has 2 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - -USB device ----------- - -B-L072Z-LRWAN1 Discovery board has 1 USB device controller. However, -the USB data lines are not connected to the MCU by default. To connect -the USB data lines to the MCU, short solder bridges SB15 and SB16. - -Programming and Debugging -************************* - -Applications for the ``b_l072z_lrwan1`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -B-L072Z-LRWAN1 Discovery board includes an ST-LINK/V2-1 embedded debug -tool interface. This interface is supported by the openocd version included -in the Zephyr SDK since v0.9.2. - - -Flashing an application to B-L072Z-LRWAN1 Discovery board ---------------------------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Connect the B-L072Z-LRWAN1 Discovery board to a STLinkV2 to your host computer using the USB port, then -run a serial host program to connect with your board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_l072z_lrwan1 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_l072z_lrwan1 - :maybe-skip-config: - :goals: debug - -.. _B-L072Z-LRWAN1 website: - https://www.st.com/en/evaluation-tools/b-l072z-lrwan1.html - -.. _STM32L072CZ on www.st.com: - https://www.st.com/en/microcontrollers/stm32l072cz.html - -.. _STM32L0x2 reference manual: - https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/b_l4s5i_iot01a/Kconfig.board b/boards/arm/b_l4s5i_iot01a/Kconfig.board deleted file mode 100644 index 927b683f71e..00000000000 --- a/boards/arm/b_l4s5i_iot01a/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# B_L4S5I_IOT01A discovery kit configuration - -# Copyright (c) 2020 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_B_L4S5I_IOT01A - bool "STM32L4S5I IOT Discovery kit" - depends on SOC_STM32L4S5XX diff --git a/boards/arm/b_l4s5i_iot01a/Kconfig.defconfig b/boards/arm/b_l4s5i_iot01a/Kconfig.defconfig deleted file mode 100644 index 059f36907a2..00000000000 --- a/boards/arm/b_l4s5i_iot01a/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# B_L4S5I_IOT01A discovery kit board configuration - -# Copyright (c) 2020 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_B_L4S5I_IOT01A - -config BOARD - default "b_l4s5i_iot01a" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -choice LIS3MDL_TRIGGER_MODE - default LIS3MDL_TRIGGER_NONE -endchoice - -choice HTS221_TRIGGER_MODE - default HTS221_TRIGGER_NONE -endchoice - -choice LSM6DSL_TRIGGER_MODE - default LSM6DSL_TRIGGER_GLOBAL_THREAD - depends on LSM6DSL -endchoice - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -config BT_BLUENRG_ACI - default y -# Disable Flow control -config BT_HCI_ACL_FLOW_CONTROL - default n -config BT_HCI_VS_EXT - default n - -endif # BT - -endif # BOARD_B_L4S5I_IOT01A diff --git a/boards/arm/b_l4s5i_iot01a/doc/index.rst b/boards/arm/b_l4s5i_iot01a/doc/index.rst deleted file mode 100644 index d5b11c8b30b..00000000000 --- a/boards/arm/b_l4s5i_iot01a/doc/index.rst +++ /dev/null @@ -1,233 +0,0 @@ -.. _b_l4s5i_iot01a_board: - -ST B_L4S5I_IOT01A Discovery kit -############################### - -Overview -******** - -The B_L4S5I_IOT01A Discovery kit features an ARM Cortex-M4 based STM32L4S5VI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the B_L4S5I_IOT01A Discovery kit: - - -- STM32L4S5VIT6 microcontroller featuring 2 Mbyte of Flash memory, 640 Kbytes of RAM in LQFP100 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- Three different interfaces supported on USB: - - - Virtual com port - - Mass storage - - Debug port - -- ARDUINO ® Uno V3 and Pmod TM expansion connector -- 4 LEDs (2 for user, wifi, BLE) -- 2 push-buttons (user and reset) -- USB OTG FS with micro-AB connector -- Dynamic NFC tag -- 2 digital omnidirectional microphones -- Capacitive digital sensor for relative humidity and temperature -- Time-of-flight and gesture-detection sensors -- High-performance 3-axis magnetometer -- 3D accelerometer and 3D gyroscope -- 64-Mbit Quad-SPI Flash memory -- Bluetooth ® 4.1 module -- 802.11 b/g/n compliant Wi‐Fi ® module -- MCU current ammeter with 4 ranges and auto-calibration - -- Flexible power supply options: - - ST-LINK/V2-1 - - USB FS connector - - External 5 V - - -.. image:: img/b-l4s5i_iot01a.jpg - :align: center - :alt: B_L4S5I_IOT01A Discovery kit - -More information about the board can be found at the `B L4S5I IOT01A Discovery kit website`_. - -Hardware -******** - -The STM32L4S5VI SoC provides the following hardware features: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 120 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC -- RTC with HW calendar, alarms and calibration -- Up to 21 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - 2x 16-bit advanced control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer -- Up to 83 fast I/Os, most 5 V-tolerant -- Memories - - Up to 2 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 640 KB of SRAM including 32 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Octo SPI memory interface -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators -- 18x communication interfaces - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (4x SPIs with the Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SDMMC I/F - - DCMI camera interface -- 14-channel DMA controller with multiplex request router -- True random number generator -- CRC calculation unit, 96-bit unique ID -- AES and HASH hardware accelerators -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L4S5VI can be found here: - - `STM32L4S5VI on www.st.com`_ - - `STM32L4S5 reference manual`_ - - -Supported Features -================== - -The Zephyr b_l4s5i_iot01a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| BLE | module | bluetooth | -+-----------+------------+-------------------------------------+ -| WIFI | module | es-wifi | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig`` - - -Connections and IOs -=================== - -B_L4S5I_IOT01A Discovery kit has 9 GPIO controllers (from A to I). These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `B L47S5I IOT01A board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 (ST-Link Virtual Port Com) -- UART_4 TX/RX : PA0/PA1 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PB10/PB11 (Sensor I2C bus) -- SPI1 NSS/SCK/MISO/MOSI : PA2/PA5/PA6/PA7 (Arduino SPI) -- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (BT SPI bus) -- PWM_2_CH1 : PA15 -- LD1 : PA5 -- LD2 : PB14 -- user button : PC13 - -System Clock ------------- - -B_L4S5I_IOT01A Discovery System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -B_L4S5I_IOT01A Discovery kit has 4 U(S)ARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -B_L4S5I_IOT01A Discovery kit includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to B_L4S5I_IOT01A Discovery kit -------------------------------------------------------- - -Connect the B_L4S5I_IOT01A Discovery kit to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_l4s5i_iot01a - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_l4s5i_iot01a - :maybe-skip-config: - :goals: debug - -.. _B L4S5I IOT01A Discovery kit website: - https://www.st.com/en/evaluation-tools/b-l4s5i-iot01a.html - -.. _B L47S5I IOT01A board User Manual: - https://www.st.com/resource/en/user_manual/dm00698410.pdf - -.. _STM32L4S5VI on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l4s5vi.html - -.. _STM32L4S5 reference manual: - https://www.st.com/resource/en/reference_manual/dm00310109.pdf diff --git a/boards/arm/b_u585i_iot02a/Kconfig.board b/boards/arm/b_u585i_iot02a/Kconfig.board deleted file mode 100644 index 2ef452a9fa5..00000000000 --- a/boards/arm/b_u585i_iot02a/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# B_U585I_IOT02A discovery kit configuration - -# Copyright (c) 2021 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_B_U585I_IOT02A - bool "STM32U585I IOT Discovery kit" - depends on SOC_STM32U585XX diff --git a/boards/arm/b_u585i_iot02a/Kconfig.defconfig b/boards/arm/b_u585i_iot02a/Kconfig.defconfig deleted file mode 100644 index bc10deca7a2..00000000000 --- a/boards/arm/b_u585i_iot02a/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# B_U585I_IOT02A discovery kit board configuration - -# Copyright (c) 2021 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_B_U585I_IOT02A - -config BOARD - default "b_u585i_iot02a" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -# Get flash configuration for NS image from dts flash partition -config USE_DT_CODE_PARTITION - default y if TRUSTED_EXECUTION_NONSECURE - -if BUILD_WITH_TFM - -# Initial Attestation key provisioned by the BL1 bootloader -config TFM_INITIAL_ATTESTATION_KEY - default y - -config TFM_DUMMY_PROVISIONING - default n - -endif # BUILD_WITH_TFM - -# Disable Flow control -if BT - -config BT_HCI_ACL_FLOW_CONTROL - default n - -endif # BT - -endif # BOARD_B_U585I_IOT02A diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns.yaml b/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns.yaml deleted file mode 100644 index 0867becc701..00000000000 --- a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: b_u585i_iot02a_ns -name: ST B_U585I_IOT02A Discovery kit non secure target -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 786 -flash: 512 -vendor: st diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns_defconfig b/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns_defconfig deleted file mode 100644 index 4b6f6ba7f5c..00000000000 --- a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U585XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y - -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/b_u585i_iot02a/doc/index.rst b/boards/arm/b_u585i_iot02a/doc/index.rst deleted file mode 100644 index 3121cfc5471..00000000000 --- a/boards/arm/b_u585i_iot02a/doc/index.rst +++ /dev/null @@ -1,439 +0,0 @@ -.. _b_u585i_iot02a_board: - -ST B_U585I_IOT02A Discovery kit -############################### - -Overview -******** - -The B_U585I_IOT02A Discovery kit features an ARM Cortex-M33 based STM32U585AI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the B_U585I_IOT02A Discovery kit: - - -- STM32U585AII6Q microcontroller featuring 2 Mbyte of Flash memory, 786 Kbytes of RAM in UFBGA169 package -- 512-Mbit octal-SPI Flash memory, 64-Mbit octal-SPI PSRAM, 256-Kbit I2C EEPROM -- USB FS, Sink and Source power, 2.5 W power capability -- 802.11 b/g/n compliant Wi-Fi® module from MXCHIP -- Bluetooth Low Energy from STMicroelectronics -- MEMS sensors from STMicroelectronics - - - 2 digital microphones - - Relative humidity and temperature sensor - - 3-axis magnetometer - - 3D accelerometer and 3D gyroscope - - Pressure sensor, 260-1260 hPa absolute digital output barometer - - Time-of-flight and gesture-detection sensor - - Ambient-light sensor - -- 2 push-buttons (user and reset) -- 2 user LEDs - -- Flexible power supply options: - - ST-LINK/V3 - - USB Vbus - - External sources - - -.. image:: img/b-u585i-iot02a.jpg - :align: center - :alt: B_U585I_IOT02A Discovery kit - -More information about the board can be found at the `B U585I IOT02A Discovery kit website`_. - -Hardware -******** - -The STM32U585xx devices are an ultra-low-power microcontrollers family (STM32U5 -Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. -They operate at a frequency of up to 160 MHz. - -- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 1.5 DMPIS/MHz (Drystone 2.1) - - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) - -- Security and cryptography - - - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals - - Flexible life cycle scheme with RDP (readout protection) and password protected debug - - Root of trust thanks to unique boot entry and secure hide protection area (HDP) - - Secure Firmware Installation thanks to embedded Root Secure Services - - Secure data storage with hardware unique key (HUK) - - Secure Firmware Update support with TF-M - - 2 AES coprocessors including one with DPA resistance - - Public key accelerator, DPA resistant - - On-the-fly decryption of Octo-SPI external memories - - HASH hardware accelerator - - Active tampers - - True Random Number Generator NIST SP800-90B compliant - - 96-bit unique ID - - 512-byte One-Time Programmable for user data - - Active tampers - -- Clock management: - - - 4 to 50 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - - Internal 48 MHz with clock recovery - -- Power management - - - Embedded regulator (LDO) - - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling - -- RTC with HW calendar and calibration -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- Up to 17 timers and 2 watchdogs - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5 x 16-bit general purpose - - 4x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- ART accelerator - - - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and - external memories: up to 160 MHz, MPU, 240 DMIPS and DSP - - 4-Kbyte data cache for external memories - -- Memories - - - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles - - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON - - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories - - 2 Octo-SPI memory interfaces - -- Rich analog peripherals (independent supply) - - - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling - - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode - - 12-bit DAC, low-power sample and hold - - 2 operational amplifiers with built-in PGA - - 2 ultra-low-power comparators - -- Up to 22 communication interfaces - - - USB Type-C / USB power delivery controller - - USB OTG 2.0 full-speed controller - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) - - 1x FDCAN - - 2x SDMMC interface - - 16- and 4-channel DMA controllers, functional in Stop mode - - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with - sound-activity detection - -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| -- True Random Number Generator (RNG) - -- Graphic features - - - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation - - 1 digital camera interface - -- Mathematical co-processor - - - CORDIC for trigonometric functions acceleration - - FMAC (filter mathematical accelerator) - - - -More information about STM32U585AI can be found here: - -- `STM32U585 on www.st.com`_ -- `STM32U585 reference manual`_ - - -Supported Features -================== - -The Zephyr b_u585i_iot02a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-----------+------------+-------------------------------------+ -| BKP SRAM | on-chip | Backup SRAM | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ -| AES | on-chip | crypto | -+-----------+------------+-------------------------------------+ -| RADIO | STM32WB5MMG| Bluetooth Low Energy (BLE) | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig`` - -Zephyr board options -==================== - -The STM32U585i is an SoC with Cortex-M33 architecture. Zephyr provides support -for building for both Secure and Non-Secure firmware. - -The BOARD options are summarized below: - -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| b_u585i_iot02a | For building Secure (or Secure-only) firmware | -+----------------------+-----------------------------------------------+ -| b_u585i_iot02a_ns | For building Non-Secure firmware | -+----------------------+-----------------------------------------------+ - -Here are the instructions to build Zephyr with a non-secure configuration, -using `tfm_ipc_` sample: - - .. code-block:: bash - - $ west build -b b_u585i_iot02a_ns samples/tfm_integration/tfm_ipc/ - -Once done, before flashing, you need to first run a generated script that -will set platform option bytes config and erase platform (among others, -option bit TZEN will be set). - - .. code-block:: bash - - $ ./build/tfm/regression.sh - $ west flash - -Please note that, after having run a TFM sample on the board, you will need to -run `./build/tfm/regression.sh` once more to clean up the board from secure -options and get back the platform back to a "normal" state and be able to run -usual, non-TFM, binaries. -Also note that, even then, TZEN will remain set, and you will need to use -STM32CubeProgrammer_ to disable it fully, if required. - -Connections and IOs -=================== - -B_U585I_IOT02A Discovery kit has 9 GPIO controllers (from A to I). These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `B U585I IOT02A board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) -- LD1 : PH7 -- LD2 : PH6 -- user button : PC13 -- SPI1 NSS/SCK/MISO/MOSI : PE12/P13/P14/P15 (Arduino SPI) -- I2C_1 SDA/SDL : PB9/PB8 (Arduino I2C) -- I2C_2 SDA/SDL : PH5/PH4 -- DAC1 CH1 : PA4 (STMOD+1) -- ADC1_IN15 : PB0 -- USB OTG : PA11/PA12 -- PWM4 : CN14 PB6 -- PWM3 : CN4 PE4 - -System Clock ------------- - -B_U585I_IOT02A Discovery System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -B_U585I_IOT02A Discovery kit has 4 U(S)ARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB6`` jumper on the back side of the board. - - -Programming and Debugging -************************* - -B_U585I_IOT02A Discovery kit includes an ST-LINK/V3 embedded debug tool interface. -This probe allows to flash the board using various tools. - - -Flashing -======== - -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. - -Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be -used to flash and debug the board if west is told to use it as runner, -using ``-r openocd``. - -Connect the B_U585I_IOT02A Discovery kit to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_u585i_iot02a - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -Default flasher for this board is openocd. It could be used in the usual way. -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: b_u585i_iot02a - :goals: debug - -Building a secure/non-secure with Arm |reg| TrustZone |reg| -=========================================================== - -The TF-M applications can be run on this board, thanks to its Arm |reg| TrustZone |reg| -support. -In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image -can be generated using ``b_u585i_iot02a_ns`` as build target. - -.. code-block:: bash - - $ west build -b b_u585i_iot02a_ns path/to/source/directory - -Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script -is run automatically in a post-build step to make some required flash layout changes. - -Once the build is completed, run the following script to initialize the option bytes. - -.. code-block:: bash - - $ build/tfm/api_ns/regression.sh - -Finally, to flash the board, run: - -.. code-block:: bash - - $ west flash - - -Disabling TrustZone |reg| on the board -====================================== - -If you have flashed a sample to the board that enables TrustZone, you will need -to disable it before you can flash and run a new non-TrustZone sample on the -board. - -To disable TrustZone, it's necessary to change AT THE SAME TIME the ``TZEN`` -and ``RDP`` bits. ``TZEN`` needs to get set from 1 to 0 and ``RDP``, -needs to be set from ``DC`` to ``AA`` (step 3 below). - -This is docummented in the `AN5347, in section 9`_, "TrustZone deactivation". - -However, it's possible that the ``RDP`` bit is not yet set to ``DC``, so you -first need to set it to ``DC`` (step 2). - -Finally you need to set the "Write Protection 1 & 2" bytes properly, otherwise -some memory regions won't be erasable and mass erase will fail (step 4). - -The following command sequence will fully deactivate TZ: - -Step 1: - -Ensure U23 BOOT0 switch is set to 1 (switch is on the left, assuming you read -"BOOT0" silkscreen label from left to right). You need to press "Reset" (B2 RST -switch) after changing the switch to make the change effective. - -Step 2: - -.. code-block:: console - - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob rdp=0xDC - -Step 3: - -.. code-block:: console - - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -tzenreg - -Step 4: - -.. code-block:: console - - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1a_pstrt=0x7f - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1a_pend=0x0 - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1b_pstrt=0x7f - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1b_pend=0x0 - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2a_pstrt=0x7f - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2a_pend=0x0 - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2b_pstrt=0x7f - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2b_pend=0x0 - - -.. _B U585I IOT02A Discovery kit website: - https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html - -.. _B U585I IOT02A board User Manual: - https://www.st.com/resource/en/user_manual/um2839-discovery-kit-for-iot-node-with-stm32u5-series-stmicroelectronics.pdf - -.. _STM32U585 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html - -.. _STM32U585 reference manual: - https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _STMicroelectronics customized version of OpenOCD: - https://github.com/STMicroelectronics/OpenOCD - -.. _AN5347, in section 9: - https://www.st.com/resource/en/application_note/dm00625692-stm32l5-series-trustzone-features-stmicroelectronics.pdf diff --git a/boards/arm/bbc_microbit/Kconfig.board b/boards/arm/bbc_microbit/Kconfig.board deleted file mode 100644 index 758673ff32c..00000000000 --- a/boards/arm/bbc_microbit/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51 BBC_MICROBIT board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BBC_MICROBIT - bool "BBC MICRO:BIT" - depends on SOC_NRF51822_QFAA diff --git a/boards/arm/bbc_microbit/Kconfig.defconfig b/boards/arm/bbc_microbit/Kconfig.defconfig deleted file mode 100644 index 17decdb0abe..00000000000 --- a/boards/arm/bbc_microbit/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# nRF51 BBC_MICROBIT board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BBC_MICROBIT - -config BOARD - default "bbc_microbit" - -config BT_CTLR - default BT - -if FXOS8700 - -choice FXOS8700_MODE - default FXOS8700_MODE_ACCEL -endchoice - -endif # FXOS8700 - -endif # BOARD_BBC_MICROBIT diff --git a/boards/arm/bbc_microbit/bbc_microbit_defconfig b/boards/arm/bbc_microbit/bbc_microbit_defconfig deleted file mode 100644 index 8396a17b16f..00000000000 --- a/boards/arm/bbc_microbit/bbc_microbit_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAA=y -CONFIG_BOARD_BBC_MICROBIT=y - -# enable GPIO -CONFIG_GPIO=y - -# clock control -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bbc_microbit_v2/Kconfig.board b/boards/arm/bbc_microbit_v2/Kconfig.board deleted file mode 100644 index 8a4457c0d45..00000000000 --- a/boards/arm/bbc_microbit_v2/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 BBC_MICROBIT_V2 board configuration - -# Copyright (c) 2020 Lingao Meng -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BBC_MICROBIT_V2 - bool "BBC MICRO:BIT_V2" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/bbc_microbit_v2/Kconfig.defconfig b/boards/arm/bbc_microbit_v2/Kconfig.defconfig deleted file mode 100644 index 4e1288c17d1..00000000000 --- a/boards/arm/bbc_microbit_v2/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 BBC_MICROBIT_V2 board configuration - -# Copyright (c) 2020 Lingao Meng -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BBC_MICROBIT_V2 - -config BOARD - default "bbc_microbit_v2" - -config BT_CTLR - default BT - -endif # BOARD_BBC_MICROBIT_V2 diff --git a/boards/arm/bbc_microbit_v2/bbc_microbit_v2_defconfig b/boards/arm/bbc_microbit_v2/bbc_microbit_v2_defconfig deleted file mode 100644 index f4d34eb3599..00000000000 --- a/boards/arm/bbc_microbit_v2/bbc_microbit_v2_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_BBC_MICROBIT_V2=y - -# enable GPIO -CONFIG_GPIO=y - -# clock control -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bcm958401m2/Kconfig.board b/boards/arm/bcm958401m2/Kconfig.board deleted file mode 100644 index d7545481fc8..00000000000 --- a/boards/arm/bcm958401m2/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -config BOARD_VALKYRIE_BCM958401M2 - bool "Broadcom Valkyrie BCM958401M2" - depends on SOC_BCM58400 diff --git a/boards/arm/bcm958401m2/Kconfig.defconfig b/boards/arm/bcm958401m2/Kconfig.defconfig deleted file mode 100644 index 87f3c72e589..00000000000 --- a/boards/arm/bcm958401m2/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. - -config BOARD - default "bcm958401m2" - depends on BOARD_VALKYRIE_BCM958401M2 diff --git a/boards/arm/bcm958401m2/bcm958401m2_defconfig b/boards/arm/bcm958401m2/bcm958401m2_defconfig deleted file mode 100644 index bba050319cd..00000000000 --- a/boards/arm/bcm958401m2/bcm958401m2_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_VALKYRIE=y -CONFIG_SOC_BCM58400=y -CONFIG_BOARD_VALKYRIE_BCM958401M2=y -CONFIG_XIP=n -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0x0 diff --git a/boards/arm/bcm958401m2/doc/index.rst b/boards/arm/bcm958401m2/doc/index.rst deleted file mode 100644 index a1c1a705c5d..00000000000 --- a/boards/arm/bcm958401m2/doc/index.rst +++ /dev/null @@ -1,58 +0,0 @@ -.. _bcm958401m2: - -Broadcom BCM958401M2 -#################### - -Overview -******** -The Broadcom BCM958401M2 board utilizes the Valkyrie BCM58400 SoC to -provide support for PCIe offload engine functionality. - -Hardware -******** -The BCM958401M2 is a PCIe card with the following physical features: - -* PCIe Gen3 interface -* RS232 UART (optionally populated) -* JTAG (optionally populated) - -Supported Features -================== -The Broadcom BCM958401M2 board configuration supports the following hardware -features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| NVIC | on-chip | nested vectored interrupt controller | -+-----------+------------+--------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm/bcm958401m2/bcm958401m2_defconfig`` - -Connections and IOs -=================== - - -Programming and Debugging -************************* - -Flashing -======== - -The flash on board is not supported by Zephyr at this time. -Board is booted over PCIe interface. - -Debugging -========= -The bcm958401m2 board includes pads for soldering a JTAG connector. -Zephyr applications running on the M7 core can also be tested by observing UART console output. - - -References -********** diff --git a/boards/arm/bcm958402m2_m7/Kconfig.board b/boards/arm/bcm958402m2_m7/Kconfig.board deleted file mode 100644 index ad1491abea8..00000000000 --- a/boards/arm/bcm958402m2_m7/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BCM958402M2_M7 - bool "Broadcom Viper BCM958402M2_M7" - depends on SOC_BCM58402_M7 diff --git a/boards/arm/bcm958402m2_m7/Kconfig.defconfig b/boards/arm/bcm958402m2_m7/Kconfig.defconfig deleted file mode 100644 index ce3b9eec627..00000000000 --- a/boards/arm/bcm958402m2_m7/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "bcm958402m2_m7" - depends on BOARD_BCM958402M2_M7 diff --git a/boards/arm/bcm958402m2_m7/bcm958402m2_m7.yaml b/boards/arm/bcm958402m2_m7/bcm958402m2_m7.yaml deleted file mode 100644 index 21c94f61721..00000000000 --- a/boards/arm/bcm958402m2_m7/bcm958402m2_m7.yaml +++ /dev/null @@ -1,8 +0,0 @@ -identifier: bcm958402m2_m7 -name: Broadcom BCM958402M2_M7 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -vendor: brcm diff --git a/boards/arm/bcm958402m2_m7/bcm958402m2_m7_defconfig b/boards/arm/bcm958402m2_m7/bcm958402m2_m7_defconfig deleted file mode 100644 index 19d83a9afd6..00000000000 --- a/boards/arm/bcm958402m2_m7/bcm958402m2_m7_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_VIPER=y -CONFIG_SOC_BCM58402_M7=y -CONFIG_BOARD_BCM958402M2_M7=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0x0 - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable PCIe EP -CONFIG_PCIE_ENDPOINT=y -CONFIG_PCIE_EP_IPROC=y -CONFIG_PCIE_EP_IPROC_V2=y - -# Enable DMA -CONFIG_DMA=y -CONFIG_DMA_64BIT=y diff --git a/boards/arm/bcm958402m2_m7/doc/index.rst b/boards/arm/bcm958402m2_m7/doc/index.rst deleted file mode 100644 index 7b7cab9e727..00000000000 --- a/boards/arm/bcm958402m2_m7/doc/index.rst +++ /dev/null @@ -1,51 +0,0 @@ -.. _bcm958402m2_m7: - -Broadcom BCM958402M2 (Cortex-M7) -################################ - -Overview -******** -The Broadcom bcm958402m2_m7 board utilizes the Viper BCM58402_M7 SoC to -provide support for PCIe offload engine functionality. - -Hardware -******** -The bcm958402m2_m7 is a PCIe card with the following physical features: - -* PCIe Gen4 interface -* RS232 UART (optionally populated) -* JTAG (optionally populated) - -Supported Features -================== -The Broadcom bcm958402m2_m7 board configuration supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| NVIC | on-chip | nested vectored interrupt controller | -+-----------+------------+--------------------------------------+ -| UART | on-chip | Compatible with UART NS16550 | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm/bcm958402m2_m7/bcm958402m2_m7_defconfig`` - -Programming and Debugging -************************* - -Flashing -======== - -The flash on board is not supported by Zephyr at this time. -Board is booted over PCIe interface. - -Debugging -========= -The bcm958402m2_m7 board includes pads for soldering a JTAG connector. -Zephyr applications running on the M7 core can also be tested -by observing UART console output. diff --git a/boards/arm/beagle_bcf/Kconfig.board b/boards/arm/beagle_bcf/Kconfig.board deleted file mode 100644 index f56ad623fa4..00000000000 --- a/boards/arm/beagle_bcf/Kconfig.board +++ /dev/null @@ -1,21 +0,0 @@ -# BeagleConnect Freedom board configuration - -# Copyright (c) 2020 Erik Larson -# Copyright (c) 2021 Jason Kridner, BeagleBoard.org Foundation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BEAGLECONNECT_FREEDOM - bool "BeagleConnect Freedom" - depends on SOC_CC1352P7 - -if BOARD_BEAGLECONNECT_FREEDOM - -config BOARD_ANTENNA_INIT_PRIO - int "Board antenna switch initialization priority" - default 70 - help - Set the priority for board init, must be greater than - KERNEL_INIT_PRIORITY_DEVICE but smaller than - IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO. - -endif # BOARD_BEAGLECONNECT_FREEDOM diff --git a/boards/arm/beagle_bcf/Kconfig.defconfig b/boards/arm/beagle_bcf/Kconfig.defconfig deleted file mode 100644 index 6dcf6a6824d..00000000000 --- a/boards/arm/beagle_bcf/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# BeagleConnect Freedom board configuration - -# Copyright (c) 2020 Erik Larson -# Copyright (c) 2020 Jason Kridner, BeagleBoard.org Foundation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BEAGLECONNECT_FREEDOM - -config BOARD - default "beagleconnect_freedom" - -endif # BOARD_BEAGLECONNECT_FREEDOM diff --git a/boards/arm/bl5340_dvk/CMakeLists.txt b/boards/arm/bl5340_dvk/CMakeLists.txt deleted file mode 100644 index 863c8bb599e..00000000000 --- a/boards/arm/bl5340_dvk/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA. -# Copyright (c) 2021-2023 Laird Connectivity. -# SPDX-License-Identifier: Apache-2.0 - -if ((CONFIG_BOARD_BL5340_DVK_CPUAPP OR CONFIG_BOARD_BL5340_DVK_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) -zephyr_library() -zephyr_library_sources(bl5340_dvk_cpunet_reset.c) - -if (CONFIG_BUILD_WITH_TFM) - zephyr_library_include_directories( - $/api_ns/interface/include - ) -endif() - -endif() diff --git a/boards/arm/bl5340_dvk/Kconfig b/boards/arm/bl5340_dvk/Kconfig deleted file mode 100644 index 365da6269e1..00000000000 --- a/boards/arm/bl5340_dvk/Kconfig +++ /dev/null @@ -1,62 +0,0 @@ -# BL5340-DVK board configuration - -# Copyright (c) 2019-2021 Nordic Semiconductor ASA -# Copyright (c) 2021-2023 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "bl5340_dvk_cpunet" if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the bl5340_dvk_cpunet for - Bluetooth applications. - -endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -if BOARD_BL5340_DVK_CPUNET - -config DOMAIN_CPUAPP_BOARD - string - default "bl5340_dvk_cpuapp" if BOARD_BL5340_DVK_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - -endif # BOARD_BL5340_DVK_CPUNET diff --git a/boards/arm/bl5340_dvk/Kconfig.board b/boards/arm/bl5340_dvk/Kconfig.board deleted file mode 100644 index b969ee535fa..00000000000 --- a/boards/arm/bl5340_dvk/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# BL5340-DVK board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_BL5340_DVK_CPUAPP - bool "BL5340-DVK (nRF5340) Application MCU" - -config BOARD_BL5340_DVK_CPUAPP_NS - bool "BL5340-DVK (nRF5340) Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -config BOARD_BL5340_DVK_CPUNET - bool "BL5340-DVK (nRF5340) Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/bl5340_dvk/Kconfig.defconfig b/boards/arm/bl5340_dvk/Kconfig.defconfig deleted file mode 100644 index d87d6d75f37..00000000000 --- a/boards/arm/bl5340_dvk/Kconfig.defconfig +++ /dev/null @@ -1,131 +0,0 @@ -# BL5340-DVK board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# Copyright (c) 2021-2023 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -config BOARD - default "bl5340_dvk_cpuapp" if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - - -config I2C - default GPIO || DAC - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_BL5340_DVK_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_BL5340_DVK_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_BL5340_DVK_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_BL5340_DVK_CPUAPP_NS - -endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -config BOARD - default "bl5340_dvk_cpunet" if BOARD_BL5340_DVK_CPUNET - -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -config BT_HCI_VS - default y if BT - -# 2.8" TFT Touch Shield for Arduino w/Capacitive Touch Screen Module -# is mounted to the DVK using standoffs. -# https://www.buydisplay.com/2-8-inch-tft-touch-shield-for-arduino-w-capacitive-touch-screen-module -if DISPLAY - -config INPUT_FT5336_INTERRUPT - default y - - -if LVGL - -config LV_Z_VDB_SIZE - default 64 - -config LV_Z_BITS_PER_PIXEL - default 16 - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -config LV_COLOR_16_SWAP - default y - -config INPUT - default y - -endif # LVGL - -endif # DISPLAY - -endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -if BOARD_BL5340_DVK_CPUNET - -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT - -config BT_ECC - default y if BT - -endif # BOARD_BL5340_DVK_CPUNET diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts deleted file mode 100644 index 6052502552e..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2021 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "bl5340_dvk_cpuapp_common.dtsi" - -/ { - model = "Laird Connectivity BL5340 (nRF5340) Application"; - compatible = "lairdconnect,bl5340-dvk-cpuapp"; - - chosen { - zephyr,sram = &sram0_image; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,sram-secure-partition = &sram0_s; - zephyr,sram-non-secure-partition = &sram0_ns; - }; -}; - -zephyr_udc0: &usbd { - compatible = "nordic,nrf-usbd"; - status = "okay"; -}; diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.yaml b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.yaml deleted file mode 100644 index 10ade88c8b1..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: bl5340_dvk_cpuapp -name: BL5340-DVK-application-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 448 -flash: 1024 -supported: - - counter - - gpio - - i2c - - pwm - - qspi - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: lairdconnect diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dtsi b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dtsi deleted file mode 100644 index 7b51c398c9f..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dtsi +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2019-2023 Nordic Semiconductor ASA - * Copyright (c) 2021-2023 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "bl5340_dvk_cpuapp_common-pinctrl.dtsi" -#include - -/ { - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,display = &ili9340; - zephyr,bt-hci-ipc = &ipc0; - }; - - /* Main LEDs and buttons are on an I2C TCA9538 GPIO port expander */ - /* Note TCA9538 does not have configurable internal pull ups/ downs */ - buttons { - compatible = "gpio-keys"; - boot_button0: boot_button { - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - label = "Bootloader button (S4)"; - zephyr,code = ; - }; - - button1: button_1 { - gpios = <&gpio_exp0 0 GPIO_ACTIVE_LOW>; - label = "Push button switch 1 (S1)"; - zephyr,code = ; - }; - - button2: button_2 { - gpios = <&gpio_exp0 1 GPIO_ACTIVE_LOW>; - label = "Push button switch 2 (S2)"; - zephyr,code = ; - }; - - button3: button_3 { - gpios = <&gpio_exp0 2 GPIO_ACTIVE_LOW>; - label = "Push button switch 3 (S9)"; - zephyr,code = ; - }; - - button4: button_4 { - gpios = <&gpio_exp0 3 GPIO_ACTIVE_LOW>; - label = "Push button switch 4 (S10)"; - zephyr,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - led1: led_1 { - gpios = <&gpio_exp0 4 GPIO_ACTIVE_LOW>; - label = "Blue LED 1"; - }; - led2: led_2 { - gpios = <&gpio_exp0 5 GPIO_ACTIVE_LOW>; - label = "Blue LED 2"; - }; - led3: led_3 { - gpios = <&gpio_exp0 6 GPIO_ACTIVE_LOW>; - label = "Blue LED 3"; - }; - led4: led_4 { - gpios = <&gpio_exp0 7 GPIO_ACTIVE_LOW>; - label = "Blue LED 4"; - }; - }; - - lvgl_pointer { - compatible = "zephyr,lvgl-pointer-input"; - input = <&ft5336>; - swap-xy; - invert-x; - invert-y; - }; - - gpio_fwd: nrf-gpio-forwarder { - compatible = "nordic,nrf-gpio-forwarder"; - status = "okay"; - uart { - gpios = <&gpio1 8 0>, <&gpio1 10 0>, <&gpio1 7 0>, <&gpio1 9 0>; - }; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led1; - led1 = &led2; - led2 = &led3; - led3 = &led4; - sw0 = &button1; - sw1 = &button2; - sw2 = &button3; - sw3 = &button4; - mcuboot-button0 = &button1; - mcuboot-led0 = &led1; - sdhc0 = &sdhc0; - watchdog0 = &wdt0; - accel0 = &lis3dh; - bbram0 = &extrtc0; - spi-flash0 = &mx25r64; - }; - - mipi_dbi { - compatible = "zephyr,mipi-dbi-spi"; - reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - dc-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - spi-dev = <&spi2>; - write-only; - #address-cells = <1>; - #size-cells = <0>; - - ili9340: ili9340@0 { - compatible = "ilitek,ili9340"; - reg = <0>; - mipi-max-frequency = <32000000>; - rotation = <270>; - width = <320>; - height = <240>; - }; - }; -}; - -&adc { - status = "okay"; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c1 { - compatible = "nordic,nrf-twim"; - status = "okay"; - - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - pinctrl-names = "default", "sleep"; - at24c256@50 { - compatible = "atmel,at24"; - reg = <0x50>; - size = <32768>; - pagesize = <64>; - address-width = <16>; - timeout = <10>; - }; - - lis3dh: lis3dh@18 { - compatible = "st,lis2dh"; - reg = <0x18>; - irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>, <&gpio0 24 GPIO_ACTIVE_HIGH>; - }; - - ft5336: ft5336@38 { - compatible = "focaltech,ft5336"; - reg = <0x38>; - int-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - }; - - bme680@76 { - compatible = "bosch,bme680"; - reg = <0x76>; - }; - - dac0: mcp4725@60 { - compatible = "microchip,mcp4725"; - reg = <0x60>; - #io-channel-cells = <1>; - }; - - extrtc0: mcp7940n@6f { - compatible = "microchip,mcp7940n"; - reg = <0x6f>; - status = "okay"; - }; - - gpio_exp0: tca9538@70 { - compatible = "ti,tca9538"; - reg = <0x70>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - nint-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; -}; - -&spi2 { - compatible = "nordic,nrf-spim"; - status = "okay"; - cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&spi2_default>; - pinctrl-1 = <&spi2_sleep>; - pinctrl-names = "default", "sleep"; - enc424j600@0 { - compatible = "microchip,enc424j600"; - reg = <0>; - spi-max-frequency = <8000000>; - int-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - }; -}; - -&spi3 { - compatible = "nordic,nrf-spim"; - status = "okay"; - cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&spi3_default>; - pinctrl-1 = <&spi3_sleep>; - pinctrl-names = "default", "sleep"; - sdhc0: sdhc@0 { - reg = <0>; - compatible = "zephyr,sdhc-spi-slot"; - status = "okay"; - spi-max-frequency = <8000000>; - mmc { - compatible = "zephyr,sdmmc-disk"; - status = "okay"; - }; - }; -}; - -&spi4 { - compatible = "nordic,nrf-spim"; - status = "okay"; - cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&spi4_default>; - pinctrl-1 = <&spi4_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_default>; - pinctrl-1 = <&pwm0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&qspi { - status = "okay"; - pinctrl-0 = <&qspi_default>; - pinctrl-1 = <&qspi_sleep>; - pinctrl-names = "default", "sleep"; - mx25r64: mx25r6435f@0 { - compatible = "nordic,qspi-nor"; - reg = <0>; - /* MX25R64 supports only pp and pp4io */ - writeoc = "pp4io"; - /* MX25R64 supports all readoc options */ - readoc = "read4io"; - sck-frequency = <8000000>; - jedec-id = [c2 28 17]; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; - size = <67108864>; - has-dpd; - t-enter-dpd = <10000>; - t-exit-dpd = <35000>; - }; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* 64K */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - }; - /* 640K */ - slot0_partition: partition@10000 { - label = "image-0"; - }; - /* 256K */ - slot0_ns_partition: partition@b0000 { - label = "image-0-nonsecure"; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/NVS - * if enabled. 32K - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -&mx25r64 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* 640K */ - slot1_partition: partition@0 { - label = "image-1"; - }; - /* 256K */ - slot1_ns_partition: partition@A0000 { - label = "image-1-nonsecure"; - }; - /* 128K */ - scratch_partition: partition@e0000 { - label = "image-scratch"; - reg = <0x000e0000 0x00020000>; - }; - /* 7MB */ - lfs_partition: partition@100000 { - label = "lfs_storage"; - reg = <0x00100000 0x00700000>; - }; - }; -}; - -/ { - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - }; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_ns: image_ns@20040000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "bl5340_dvk_cpuapp_partition_conf.dtsi" diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig deleted file mode 100644 index 6c21af3695a..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_BL5340_DVK_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Setup clocks -CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y -CONFIG_SOC_LFXO_CAP_INT_7PF=y -CONFIG_SOC_HFXO_CAP_INTERNAL=y -CONFIG_SOC_HFXO_CAP_INT_VALUE_X2=27 diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.dts b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.dts deleted file mode 100644 index 9fdcba5f0e3..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2021 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "bl5340_dvk_cpuapp_common.dtsi" - -/ { - model = "Laird Connectivity BL5340 (nRF5340) Application"; - compatible = "lairdconnect,bl5340-dvk-cpuapp"; - - chosen { - zephyr,sram = &sram0_ns; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_ns_partition; - }; -}; - -zephyr_udc0: &usbd { - compatible = "nordic,nrf-usbd"; - status = "okay"; -}; diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.yaml b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.yaml deleted file mode 100644 index 5d94e8e7629..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: bl5340_dvk_cpuapp_ns -name: BL5340-DVK-application-MCU-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 192 -flash: 192 -supported: - - counter - - gpio - - i2c - - pwm - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: lairdconnect diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns_defconfig b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns_defconfig deleted file mode 100644 index 27af7678a34..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_BL5340_DVK_CPUAPP_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_partition_conf.dtsi b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_partition_conf.dtsi deleted file mode 100644 index b9bd8c73f77..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_partition_conf.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2019-2020 Nordic Semiconductor ASA - * Copyright (c) 2021 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for bl5340_dvk CPUAPP (Application MCU). - * - * Zephyr build for BL5340 with ARM TrustZone-M support - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0xa0000>; -}; - -&slot0_ns_partition { - reg = <0x000b0000 0x40000>; -}; - -&slot1_partition { - reg = <0x00000000 0xa0000>; -}; - -&slot1_ns_partition { - reg = <0x000a0000 0x40000>; -}; - -/* Default SRAM planning when building for nRF5340 with - * ARM TrustZone-M support - * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) - * - Middle 192 kB allocated to Non-Secure image (sram0_ns) - * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) - * (see bl5340_dvk_shared_sram_planning_conf.dtsi) - */ -&sram0_image { - reg = <0x20000000 DT_SIZE_K(448)>; -}; - -&sram0_s { - reg = <0x20000000 0x40000>; -}; - -&sram0_ns { - reg = <0x20040000 0x30000>; -}; - -/* Include shared RAM configuration file */ -#include "bl5340_dvk_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.dts b/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.dts deleted file mode 100644 index 2b3eb053283..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.dts +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2021-2023 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "bl5340_dvk_cpunet-pinctrl.dtsi" -#include "bl5340_dvk_cpunet_common.dtsi" - -/ { - model = "Laird Connectivity BL5340 (nRF5340) Network"; - compatible = "lairdconnect,bl5340-dvk-cpunet"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram1; - zephyr,flash = &flash1; - zephyr,code-partition = &slot0_partition; - zephyr,bt-hci-ipc = &ipc0; - }; - - aliases { - watchdog0 = &wdt0; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.yaml b/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.yaml deleted file mode 100644 index d8a17394be7..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: bl5340_dvk_cpunet -name: BL5340-DVK-network-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - counter - - gpio - - i2c - - spi - - uart - - watchdog -vendor: lairdconnect diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_common.dtsi b/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_common.dtsi deleted file mode 100644 index b7bb765444c..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_common.dtsi +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2021-2023 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&flash1 { - /* - * For more information, see: - * http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* 48K */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0xc000>; - }; - /* 88K */ - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x16000>; - }; - /* 88K */ - slot1_partition: partition@22000 { - label = "image-1"; - reg = <0x00022000 0x16000>; - }; - /* 32K */ - storage_partition: partition@38000 { - label = "storage"; - reg = <0x00038000 0x8000>; - }; - }; -}; - -/* Include shared RAM configuration file */ -#include "bl5340_dvk_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_defconfig b/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_defconfig deleted file mode 100644 index c68fdfc9312..00000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_BL5340_DVK_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bl5340_dvk/board.cmake b/boards/arm/bl5340_dvk/board.cmake deleted file mode 100644 index 398b454e4a8..00000000000 --- a/boards/arm/bl5340_dvk/board.cmake +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_BL5340_DVK_CPUAPP_NS) - set(TFM_PUBLIC_KEY_FORMAT "full") -endif() - -if(CONFIG_BOARD_BL5340_DVK_CPUAPP OR CONFIG_BOARD_BL5340_DVK_CPUAPP_NS) -board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_TFM_FLASH_MERGED_BINARY) - set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) -endif() - -if(CONFIG_BOARD_BL5340_DVK_CPUNET) -board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/bl5340_dvk/doc/index.rst b/boards/arm/bl5340_dvk/doc/index.rst deleted file mode 100644 index 544250baa84..00000000000 --- a/boards/arm/bl5340_dvk/doc/index.rst +++ /dev/null @@ -1,436 +0,0 @@ -.. _bl5340_dvk: - -Laird Connectivity BL5340 DVK -############################# - -Overview -******** -The BL5340 Development Kit provides support for the Laird Connectivity -BL5340 module which is powered by a dual-core Nordic Semiconductor -nRF5340 ARM Cortex-M33F CPU. The nRF5340 inside the BL5340 module is a -dual-core SoC based on the Arm® Cortex®-M33 architecture, with: - -* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and - Armv8-M Security Extension, running at up to 128 MHz, referred to as - the **application core** -* a secondary Arm Cortex-M33 core, with a reduced feature set, running - at a fixed 64 MHz, referred to as the **network core**. - -The bl5340_dvk_cpuapp build target provides support for the application -core on the BL5340 module. The bl5340_dvk_cpunet build target provides -support for the network core on the BL5340 module. If ARM TrustZone is -used then the bl5340_dvk_cpuapp build target provides support for the -non-secure partition of the application core on the BL5340 module. - -This development kit has the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`I2S (Inter-Integrated Sound)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/bl5340_dvk_top.jpg - :align: center - :alt: BL5340 DVK - - BL5340 DVK (Credit: Laird Connectivity) - -More information about the module can be found on the -`BL5340 homepage`_. - -The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - -Hardware -******** - -The BL5340 DVK has two external oscillators. The frequency of -the slow clock is 32.768KHz. The frequency of the main clock -is 32MHz. - -Supported Features -================== - -The bl5340_dvk_cpuapp board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| QSPI(M) | on-chip | nor | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The bl5340_dvk_cpunet board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `Nordic Semiconductor Infocenter`_ -for a complete list of hardware features. - -Connections and IOs -=================== - -An eight-pin GPIO port expander is used to provide additional inputs -and outputs to the BL5340 module. - -Refer to the `TI TCA9538 datasheet`_ for further details. - -LEDs ----- - -* LED1 (blue) = via TCA9538 port expander channel P4 (active low) -* LED2 (blue) = via TCA9538 port expander channel P5 (active low) -* LED3 (blue) = via TCA9538 port expander channel P6 (active low) -* LED4 (blue) = via TCA9538 port expander channel P7 (active low) - -Push buttons ------------- - -* BUTTON1 = SW1 = via TCA9538 port expander channel P0 (active low) -* BUTTON2 = SW2 = via TCA9538 port expander channel P1 (active low) -* BUTTON3 = SW3 = via TCA9538 port expander channel P2 (active low) -* BUTTON4 = SW4 = via TCA9538 port expander channel P3 (active low) -* BOOT = boot (active low) - -External Memory -=============== - -Several external memory sources are available for the BL5340 DVK. These -are described as follows. - -Flash Memory ------------- - -A Macronix MX25R6435FZNIL0 8MB external QSPI Flash memory part is -incorporated for application image storage and large datasets. - -Refer to the `Macronix MX25R6435FZNIL0 datasheet`_ for further details. - -EEPROM Memory -------------- - -A 32KB Giantec GT24C256C-2GLI-TR EEPROM is available via I2C for -storage of infrequently updated data and small datasets. - -Refer to the `Giantec GT24C256C-2GLI-TR datasheet`_ for further details. - -External Memory ---------------- - -An on-board micro SD card slot is available for use with micro SD cards. - -Sensors -======= - -The BL5340 DVK incorporates two sensors for user application testing. -These are described as follows. - -Temperature, Pressure, Humidity & Air Quality Sensor ----------------------------------------------------- - -A Bosch BME680 Temperature, Pressure, Humidity & Air Quality sensor is -available via I2C for environmental measurement applications. - -Refer to the `Bosch BME680 datasheet`_ for further details. - -3-Axis Accelerometer --------------------- - -An ST Microelectronics LIS3DH 3-Axis Accelerometer is available via I2C -for vibration and motion detection applications. - -Refer to the `ST Microelectronics LIS3DH datasheet`_ for further details. - -Ethernet -======== - -Cabled 10/100 Base-T Ethernet Connectivity is available via a Microchip -ENC424J600 Ethernet controller. - -Refer to the `Microchip ENC424J600 datasheet`_ for further details. - -TFT Display & Capacitive Touch Screen Controller -================================================ - -A 2.8 inch, 240 x 320 pixel TFT display with capacitive touch -controller is included with the BL5340 DVK for user interface -application features. - -Refer to the `ER_TFTM028_4 datasheet`_ for a high level overview of the -display. - -An ILI9341 TFT controller is incorporated in the TFT module and -acts as the main controller, controlled via SPI. - -Refer to the `ILI9341 datasheet`_ for further details. - -An FT6206 Capacitive Touch Controller, controlled via I2C is -also incorporated in the TFT module. - -Refer to the `FT6206 datasheet`_ for further details. - -Real-Time Clock -=============== - -A real-time clock is available for accurate time data availability. - -Refer to the `Microchip MCP7940N datasheet`_ for further details. - -DAC -=== - -A 10-bit Digital to Analog Converter is incorporated for generation of -variable voltages. - -Refer to the `Microchip MCP4725 datasheet`_ for further details. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_) on the application - core. The IDAU is implemented with the System Protection Unit and is - used to define secure and non-secure memory maps. By default, all of - the memory space (Flash, SRAM, and peripheral address space) is - defined to be secure accessible only. -- Secure boot. - -Programming and Debugging -************************* - -The BL5340's application core supports the Armv8-M Security Extension. -Applications built for the bl5340_dvk_cpuapp board by default -boot in the Secure state. - -The BL5340's network core does not support the Armv8-M Security -Extension. The IDAU may configure bus accesses by the network core to -have Secure attribute set; the latter allows to build and run Secure -only applications on the BL5340 module. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -Applications on the BL5340 module may contain a Secure and a Non-Secure -firmware image for the application core. The Secure image can be built -using either Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure -firmware images are always built using Zephyr. The two alternatives are -described below. - -.. note:: - - By default the Secure image for BL5340's application core is - built using TF-M. - -Building the Secure firmware with TF-M --------------------------------------- - -The process to build the Secure firmware image using TF-M and the -Non-Secure firmware image using Zephyr requires the following steps: - -1. Build the Non-Secure Zephyr application - for the application core using ``-DBOARD=bl5340_dvk_cpuapp_ns``. - To invoke the building of TF-M the Zephyr build system requires the - Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by - default when building Zephyr as a Non-Secure application. - The Zephyr build system will perform the following steps automatically: - - * Build the Non-Secure firmware image as a regular Zephyr application - * Build a TF-M (secure) firmware image - * Merge the output image binaries together - * Optionally build a bootloader image (MCUboot) - -.. note:: - - Depending on the TF-M configuration, an application DTS overlay may - be required, to adjust the Non-Secure image Flash and SRAM starting - address and sizes. - -2. Build the application firmware for the network core using - ``-DBOARD=bl5340_dvk_cpunet``. - -Building the Secure firmware using Zephyr ------------------------------------------ - -The process to build the Secure and the Non-Secure firmware images -using Zephyr requires the following steps: - -1. Build the Secure Zephyr application for the application core - using ``-DBOARD=bl5340_dvk_cpuapp`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` - in the application project configuration file. -2. Build the Non-Secure Zephyr application for the application core - using ``-DBOARD=bl5340_dvk_cpuapp_ns``. -3. Merge the two binaries together. -4. Build the application firmware for the network core using - ``-DBOARD=bl5340_dvk_cpunet``. - -When building a Secure/Non-Secure application for the BL5340's -application core, the Secure application will have to set the IDAU -(SPU) configuration to allow Non-Secure access to all CPU resources -utilized by the Non-Secure application firmware. SPU configuration -shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=bl5340_dvk_cpuapp`` for -the firmware running on the BL5340's application core, and using -``-DBOARD=bl5340_dvk_cpunet`` for the firmware running -on the BL5340's network core. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then you can build and flash -applications as usual (:ref:`build_an_application` and -:ref:`application_run` for more details). - -.. warning:: - - The BL5340 has a flash read-back protection feature. When flash - read-back protection is active, you will need to recover the chip - before reflashing. If you are flashing with - :ref:`west `, run this command for more - details on the related ``--recover`` option: - - .. code-block:: console - - west flash -H -r nrfjprog --skip-rebuild - -.. note:: - - Flashing and debugging applications on the BL5340 DVK requires - upgrading the nRF Command Line Tools to version 10.12.0 or newer. - Further information on how to install the nRF Command Line Tools can - be found in :ref:`nordic_segger_flashing`. - -Here is an example for the :ref:`hello_world` application running on the -BL5340's application core. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the BL5340 DVK board -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: bl5340_dvk_cpuapp - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -boards with a Segger IC. - -Testing Bluetooth on the BL5340 DVK -*********************************** -Many of the Bluetooth examples will work on the BL5340 DVK. -Try them out: - -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _BL5340 homepage: https://www.lairdconnect.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl5340-series-multi-core-bluetooth-52-802154-nfc-modules -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _TI TCA9538 datasheet: https://www.ti.com/lit/gpn/TCA9538 -.. _Macronix MX25R6435FZNIL0 datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.6.pdf -.. _Giantec GT24C256C-2GLI-TR datasheet: https://www.giantec-semi.com/juchen1123/uploads/pdf/GT24C256C_DS_Cu.pdf -.. _Bosch BME680 datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme680-ds001.pdf -.. _ST Microelectronics LIS3DH datasheet: https://www.st.com/resource/en/datasheet/lis3dh.pdf -.. _Microchip ENC424J600 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf -.. _ER_TFTM028_4 datasheet: https://www.buydisplay.com/download/manual/ER-TFTM028-4_Datasheet.pdf -.. _ILI9341 datasheet: https://www.buydisplay.com/download/ic/ILI9341.pdf -.. _FT6206 datasheet: https://www.buydisplay.com/download/ic/FT6206.pdf -.. _Microchip MCP7940N datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/20005010H.pdf -.. _Microchip MCP4725 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22039d.pdf -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/bl652_dvk/Kconfig.board b/boards/arm/bl652_dvk/Kconfig.board deleted file mode 100644 index e5c2bf8bd4c..00000000000 --- a/boards/arm/bl652_dvk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BL652 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BL652_DVK - bool "BL652 DVK" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/bl652_dvk/Kconfig.defconfig b/boards/arm/bl652_dvk/Kconfig.defconfig deleted file mode 100644 index 56dbfebfca9..00000000000 --- a/boards/arm/bl652_dvk/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# BL652 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL652_DVK - -config BOARD - default "bl652_dvk" - -config BT_CTLR - default BT - -if DAC - -config I2C - default y - -endif # DAC - -endif # BOARD_BL652_DVK diff --git a/boards/arm/bl653_dvk/Kconfig.board b/boards/arm/bl653_dvk/Kconfig.board deleted file mode 100644 index 4a6ca61c3e6..00000000000 --- a/boards/arm/bl653_dvk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BL653 DVK board configuration - -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BL653_DVK - bool "BL653 DVK" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/bl653_dvk/Kconfig.defconfig b/boards/arm/bl653_dvk/Kconfig.defconfig deleted file mode 100644 index e4f82f99c33..00000000000 --- a/boards/arm/bl653_dvk/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# BL653 DVK board configuration - -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL653_DVK - -config BOARD - default "bl653_dvk" - -config BT_CTLR - default BT - -if DAC - -config I2C - default y - -endif # DAC - -endif # BOARD_BL653_DVK diff --git a/boards/arm/bl654_dvk/Kconfig.board b/boards/arm/bl654_dvk/Kconfig.board deleted file mode 100644 index 4c666d5aaba..00000000000 --- a/boards/arm/bl654_dvk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BL654 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BL654_DVK - bool "BL654 DVK" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/bl654_dvk/Kconfig.defconfig b/boards/arm/bl654_dvk/Kconfig.defconfig deleted file mode 100644 index 53bf5238687..00000000000 --- a/boards/arm/bl654_dvk/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# BL654 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL654_DVK - -config BOARD - default "bl654_dvk" - -config BT_CTLR - default BT - -if DAC - -config I2C - default y - -endif # DAC - -endif # BOARD_BL654_DVK diff --git a/boards/arm/bl654_sensor_board/Kconfig.board b/boards/arm/bl654_sensor_board/Kconfig.board deleted file mode 100644 index 6e68f886c43..00000000000 --- a/boards/arm/bl654_sensor_board/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BL654 Sensor Board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BL654_SENSOR_BOARD - bool "BL654 Sensor Board" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/bl654_sensor_board/Kconfig.defconfig b/boards/arm/bl654_sensor_board/Kconfig.defconfig deleted file mode 100644 index 4ca294e8990..00000000000 --- a/boards/arm/bl654_sensor_board/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# BL654 Sensor Board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL654_SENSOR_BOARD - -config BOARD - default "bl654_sensor_board" - -config BT_CTLR - default BT - -endif # BOARD_BL654_SENSOR_BOARD diff --git a/boards/arm/bl654_usb/Kconfig.board b/boards/arm/bl654_usb/Kconfig.board deleted file mode 100644 index 49f4dc67fad..00000000000 --- a/boards/arm/bl654_usb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BL654 USB adapter board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BL654_USB - bool "BL654 USB" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/bl654_usb/Kconfig.defconfig b/boards/arm/bl654_usb/Kconfig.defconfig deleted file mode 100644 index 573746037f8..00000000000 --- a/boards/arm/bl654_usb/Kconfig.defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# BL654 USB adapter board configuration - -# Copyright (c) 2021-2022 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL654_USB - -config BOARD - default "bl654_usb" - -# To let the nRF5 bootloader load an application, the application -# must be linked after Nordic MBR, that is factory-programmed on the board. - -# Nordic nRF5 bootloader exists outside of the partitions specified in the -# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application -# correctly, after Nordic MBR, and limit the maximum size to not protude into -# the bootloader at the end of flash. - -# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION -# which will make it link into the correct partition specified in DTS file, -# so no override or limit is necessary. - -config FLASH_LOAD_OFFSET - default 0x1000 - depends on !USE_DT_CODE_PARTITION - -config FLASH_LOAD_SIZE - default 0xdf000 - depends on !USE_DT_CODE_PARTITION - -config USB_CDC_ACM - default n if USB_DEVICE_BLUETOOTH - -if BL654_USB_SERIAL_BACKEND_CDCACM - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if !MCUBOOT - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -# Logger cannot use itself to log -config USB_CDC_ACM_LOG_LEVEL - default 0 - -# Set USB log level to error only -config USB_DEVICE_LOG_LEVEL - default 1 - -endif #BL654_USB_SERIAL_BACKEND_CDCACM - -config BT_CTLR - default BT - -endif # BOARD_BL654_USB diff --git a/boards/arm/black_f407ve/Kconfig.board b/boards/arm/black_f407ve/Kconfig.board deleted file mode 100644 index c4711fb2c49..00000000000 --- a/boards/arm/black_f407ve/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# black_f407ve board configuration - -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BLACK_F407VE - bool "Black F407VE Development Board" - depends on SOC_STM32F407XE diff --git a/boards/arm/black_f407ve/Kconfig.defconfig b/boards/arm/black_f407ve/Kconfig.defconfig deleted file mode 100644 index ebc572bea39..00000000000 --- a/boards/arm/black_f407ve/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# black_f407ve board configuration - -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BLACK_F407VE - -config BOARD - default "black_f407ve" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_BLACK_F407VE diff --git a/boards/arm/black_f407ve/doc/index.rst b/boards/arm/black_f407ve/doc/index.rst deleted file mode 100644 index 4862514d480..00000000000 --- a/boards/arm/black_f407ve/doc/index.rst +++ /dev/null @@ -1,244 +0,0 @@ -.. _black_f407ve_board: - -Black STM32 F407VE Development Board -#################################### - -Overview -******** - -The BLACK_F407VE board features an ARM Cortex-M4 based STM32F407xx MCU -with a wide range of connectivity support and configurations. There are -multiple version of this board like ``black_f407ve``. -Here are some highlights of the BLACK_F407VE board: - -- STM32 microcontroller in LQFP100 package -- Extension header for all LQFP100 I/Os for quick connection to prototyping - board and easy probing -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V) - - Power management access point - -- Three LEDs: - - - 3.3 V power on (LD0) - - Two user LEDs: green (LD1), green (LD2) - -- Four push-buttons: RESET, K0, K1 and WK_UP -- Mini-AB connector - -.. image:: img/black_f407ve.jpg - :align: center - :alt: BLACK_F407VE - -See also board descriptions at `STM32-base website`_, -`STM32F407VET6 black board`_ and `MCUDev Black STM32F407VET6`_ - -.. warning:: The +5V pins on this board are directly connected to the +5V pin - of the USB connector. There is no protection in place. Do not - power this board through USB and an external power supply at - the same time. - - -Hardware -******** - -BLACK_F407VE board provides the following hardware components: - -- STM32F407VET6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 168 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 8MHz system crystal -- 32.768KHz RTC crystal -- JTAG/SWD header -- 512 kB Flash -- 192+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC battery CR1220 -- Advanced-control Timer (2) -- General Purpose Timers (12) -- Watchdog Timers (2) -- USART (3), UART (2) -- I2C (3) -- I2S (2) -- SPI (3) -- SDIO (1) -- CAN (2) -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- CRC calculation unit -- True random number generator -- DMA Controller -- Micro SD -- 1x 10/100 Ethernet MAC -- 1x 8 to 12-bit Parallel Camera interface -- Micro USB for power and comms -- 2x jumpers for bootloader selection -- 2x16 FMSC LCD Interface -- NRF24L01 socket -- Dimensions: 85.1mm x 72.45mm - -More information about STM32F407VE SOC can be found here: - - `STM32F407VE on www.st.com`_ - -Supported Features -================== - -The Zephyr black_f407ve board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver. - Zephyr default configuration uses CAN_2 exclusively, as - simultaneous use of CAN_1 and CAN_2 is not yet supported. - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/black_f407_generic/black_f407ve_defconfig`` - - -Pin Mapping -=========== - -BLACK_F407VE has 5 GPIO controllers. These controllers are responsible for pin -muxing, input/output, pull-up, etc. - -.. image:: img/stm32f407vet6_left02.jpg - :align: center - :alt: left pins - -.. image:: img/stm32f407vet6_right01.jpg - :align: center - :alt: right pins - -.. image:: img/stm32f407vet6_st-link02.jpg - :align: center - :alt: bottom and top pins - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- USER_PB : PA0 -- LD3 : PD13 -- LD4 : PD12 -- LD5 : PD14 -- LD6 : PD15 -- USB DM : PA11 -- USB DP : PA12 -- CAN1_RX : PD0 -- CAN1_TX : PD1 -- CAN2_RX : PB12 -- CAN2_TX : PB13 -- SPI1 MISO : PB4 -- SPI1 MOSI : PB5 -- SPI1 SCK : PB3 -- SPI1 Flash CS : PB0 -- SPI2 MISO : PC2 -- SPI2 MOSI : PC3 -- SPI2 SCK : PB10 - -System Clock -============ - -BLACK_F407VE System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock -at 168MHz, driven by 8MHz high speed external clock. - -Serial Port -=========== - -BLACK_F407VE has up to 6 UARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. -Please note that ST-Link Virtual Com Port is not wired to chip serial port. -In order to enable console output you should use a serial cable and connect -it to UART1 pins (PA9/PA10). - - -Programming and Debugging -************************* - -Applications for the ``black_f407ve`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -BLACK_F407VE board includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to BLACK_F407VE ---------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: black_f407ve - :goals: build flash - -You should see user led "LD1" blinking. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: black_f407ve - :maybe-skip-config: - :goals: debug - -.. _STM32-base website: - https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0.html - -.. _STM32F407VE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f407ve.html - -.. _STM32F407VET6 black board: - https://os.mbed.com/users/hudakz/code/STM32F407VET6_Hello/ - -.. _MCUDev Black STM32F407VET6: - https://github.com/mcauser/BLACK_F407VE diff --git a/boards/arm/black_f407zg_pro/Kconfig.board b/boards/arm/black_f407zg_pro/Kconfig.board deleted file mode 100644 index 8322175e4ba..00000000000 --- a/boards/arm/black_f407zg_pro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# black_f407zg board configuration - -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BLACK_F407ZG_PRO - bool "Black F407ZG Pro Development Board" - depends on SOC_STM32F407XG diff --git a/boards/arm/black_f407zg_pro/Kconfig.defconfig b/boards/arm/black_f407zg_pro/Kconfig.defconfig deleted file mode 100644 index bdfcf331443..00000000000 --- a/boards/arm/black_f407zg_pro/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# black_f407zg board configuration - -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BLACK_F407ZG_PRO - -config BOARD - default "black_f407zg_pro" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_BLACK_F407ZG_PRO diff --git a/boards/arm/black_f407zg_pro/doc/index.rst b/boards/arm/black_f407zg_pro/doc/index.rst deleted file mode 100644 index 4646149a71e..00000000000 --- a/boards/arm/black_f407zg_pro/doc/index.rst +++ /dev/null @@ -1,217 +0,0 @@ -.. _black_f407zg_pro_board: - -Black STM32 F407ZG Pro Development Board -######################################## - -Overview -******** - -The BLACK_F407ZG_PRO board features an ARM Cortex-M4 based STM32F407zg MCU -with a wide range of connectivity support and configurations. There are -multiple version of this board like ``black_f407ve``. -Here are some highlights of the BLACK_F407ZG_PRO board: - -- STM32 microcontroller in LQFP144 package -- Extension header for all LQFP144 I/Os for quick connection to prototyping - board and easy probing -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V) - - Power management access point - -- Three LEDs: - - - 3.3 V power on (LD0) - - Two user LEDs: green (LD1), green (LD2) - -- Four push-buttons: RESET, K0, K1 and WK_UP -- Mini-AB connector - -.. image:: img/black_f407zg_pro.jpg - :align: center - :alt: BLACK_F407ZG_PRO - -.. warning:: The +5V pins on this board are directly connected to the +5V pin - of the USB connector. There is no protection in place. Do not - power this board through USB and an external power supply at - the same time. - - -Hardware -******** - -BLACK_F407ZG_PRO board provides the following hardware components: - -- STM32F407ZGT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 168 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 8MHz system crystal -- 32.768KHz RTC crystal -- JTAG/SWD header -- 1024 kB Flash -- 192+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC battery CR1220 -- Advanced-control Timer (2) -- General Purpose Timers (12) -- Watchdog Timers (2) -- USART (3), UART (2) -- I2C (3) -- I2S (2) -- SPI (3) -- SDIO (1) -- CAN (2) -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- CRC calculation unit -- True random number generator -- DMA Controller -- Micro SD -- 1x 10/100 Ethernet MAC -- 1x 8 to 12-bit Parallel Camera interface -- Micro USB for power and comms -- 2x jumpers for bootloader selection -- 2x16 FMSC LCD Interface -- NRF24L01 socket -- Dimensions: 102.5mm x 74.56mm - -More information about STM32F407ZG SOC can be found here: - - `STM32F407ZG on www.st.com`_ - -Supported Features -================== - -The Zephyr black_f407zg_pro board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver. - Zephyr default configuration uses CAN_2 exclusively, as - simultaneous use of CAN_1 and CAN_2 is not yet supported. - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/black_f407_generic/black_f407zg_pro_defconfig`` - - -Pin Mapping -=========== - -BLACK_F407ZG_PRO has 7 GPIO controllers. These controllers are responsible for pin -muxing, input/output, pull-up, etc. - - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- USER_PB : PA0 -- LD3 : PD13 -- LD4 : PD12 -- LD5 : PD14 -- LD6 : PD15 -- USB DM : PA11 -- USB DP : PA12 -- CAN1_RX : PD0 -- CAN1_TX : PD1 -- CAN2_RX : PB12 -- CAN2_TX : PB13 -- SPI2 MISO : PC2 -- SPI2 MOSI : PC3 -- SPI2 SCK : PB10 - -System Clock -============ - -BLACK_F407ZG_PRO System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock -at 168MHz, driven by 8MHz high speed external clock. - -Serial Port -=========== - -BLACK_F407ZG_PRO has up to 6 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. -Please note that ST-Link Virtual Com Port is not wired to chip serial port. -In order to enable console output you should use a serial cable and connect -it to UART2 pins (PA2/PA3). - - -Programming and Debugging -************************* - -Applications for the ``black_f407zg_pro`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -BLACK_F407ZG_PRO board includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to BLACK_F407ZG_PRO -------------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: black_f407zg_pro - :goals: build flash - -You should see user led "LD1" blinking. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: black_f407zg_pro - :maybe-skip-config: - :goals: debug - -.. _STM32F407ZG on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32f407zg.html diff --git a/boards/arm/blackpill_f401cc/Kconfig.board b/boards/arm/blackpill_f401cc/Kconfig.board deleted file mode 100644 index cb4004e248a..00000000000 --- a/boards/arm/blackpill_f401cc/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# STM32F401CC based Black Pill V3.0+ board configuration - -config BOARD_BLACKPILL_F401CC - bool "WeAct Studio Black Pill V3.0+ Board" - depends on SOC_STM32F401XC diff --git a/boards/arm/blackpill_f401cc/Kconfig.defconfig b/boards/arm/blackpill_f401cc/Kconfig.defconfig deleted file mode 100644 index fb31f4eff61..00000000000 --- a/boards/arm/blackpill_f401cc/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# F401CE based Black Pill V3.0+ board board configuration - -if BOARD_BLACKPILL_F401CC - -config BOARD - default "blackpill_f401cc" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_BLACKPILL_F401CC diff --git a/boards/arm/blackpill_f401cc/doc/index.rst b/boards/arm/blackpill_f401cc/doc/index.rst deleted file mode 100644 index 8c662a11fda..00000000000 --- a/boards/arm/blackpill_f401cc/doc/index.rst +++ /dev/null @@ -1,174 +0,0 @@ -.. _blackpill_f401cc: - -WeAct Studio Black Pill V1.2 -############################ - -Overview -******** - -The WeAct Black Pill V1.2 Board is an extremely low cost and bare-bones -development board featuring the STM32F401CC, see `STM32F401CC website`_. -This is the 48-pin variant of the STM32F401x series, -see `STM32F401x reference manual`_. More info about the board available -`here `_ and on `WeAct Github`_. - -.. image:: img/blackpill-v3.jpg - :align: center - :alt: Black Pill V3.0+ - -Hardware -******** - -The STM32F401CC based Black Pill V3.0+ Board provides the following -hardware components: - -- STM32F401CCU6 in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 84 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 256 KB Flash -- 64 KB SRAM -- GPIO with external interrupt capability -- 1x12-bit, 2.4 MSPS ADC with 16 channels -- DMA Controller -- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) -- USART/UART (3) -- I2C (3) -- SPI/I2S (5) -- SDIO -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- CRC calculation unit -- 96-bit unique ID -- RTC - -Supported Features -================== - -The Zephyr blackpill_f401ce board configuration supports the following -hardware features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/blackpill_f401ce/blackpill_f401ce_defconfig`` - -Pin Mapping -=========== - -Available pins: ---------------- -.. image:: img/Blackpill_Pinout.jpg - :align: center - :alt: Black Pill V1.2 Pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- I2C1 SCL/SDA : PB8/PB9 -- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) -- PWM_4_CH1 : PB6 -- PWM_4_CH2 : PB7 -- ADC_1 : PA1 -- USER_PB : PA0 -- USER_LED : PC13 - -Clock Sources -------------- - -The board has two external oscillators. The frequency of the slow clock (LSE) is -32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. - -The default configuration sources the system clock from the PLL, which is -derived from HSE, and is set at 84MHz, which is the maximum possible frequency -to achieve a stable USB clock (42MHz). - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -There is also a Windows version which works, but you may have to install the -right USB drivers with a tool like `Zadig`_. - -Flashing an Application ------------------------ - -Connect a USB-C cable and the board should power ON. Force the board into DFU mode -by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. - -The dfu-util runner is supported on this board and so a sample can be built and -tested easily. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: blackpill_f401cc - :goals: build flash - -Debugging -========= - -The board can be debugged by installing the included 100 mil (0.1 inch) header, -and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO -pins on that header. - -References -********** - -.. target-notes:: - -.. _board release notes: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md - -.. _Zadig: - https://zadig.akeo.ie/ - -.. _WeAct Github: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 - -.. _stm32-base-board-page: - https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2.html - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _STM32F401CC website: - https://www.st.com/en/microcontrollers/stm32f401cc.html - -.. _STM32F401x reference manual: - https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/blackpill_f401ce/Kconfig.board b/boards/arm/blackpill_f401ce/Kconfig.board deleted file mode 100644 index 666a12a157d..00000000000 --- a/boards/arm/blackpill_f401ce/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2020 Kalyan Sriram -# SPDX-License-Identifier: Apache-2.0 - -# STM32F401CE based Black Pill V3.0+ board configuration - -config BOARD_BLACKPILL_F401CE - bool "WeAct Studio Black Pill V3.0+ Board" - depends on SOC_STM32F401XE diff --git a/boards/arm/blackpill_f401ce/Kconfig.defconfig b/boards/arm/blackpill_f401ce/Kconfig.defconfig deleted file mode 100644 index 739c5512170..00000000000 --- a/boards/arm/blackpill_f401ce/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2020 Kalyan Sriram -# SPDX-License-Identifier: Apache-2.0 - -# F401CE based Black Pill V3.0+ board board configuration - -if BOARD_BLACKPILL_F401CE - -config BOARD - default "blackpill_f401ce" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_BLACKPILL_F401CE diff --git a/boards/arm/blackpill_f401ce/doc/index.rst b/boards/arm/blackpill_f401ce/doc/index.rst deleted file mode 100644 index 265d0fd038e..00000000000 --- a/boards/arm/blackpill_f401ce/doc/index.rst +++ /dev/null @@ -1,179 +0,0 @@ -.. _blackpill_f401ce: - -WeAct Studio Black Pill V3.0 -############################ - -Overview -******** - -The WeAct Black Pill V3.0 Board is an extremely low cost and bare-bones -development board featuring the STM32F401CE, see `STM32F401CE website`_. -This is the 48-pin variant of the STM32F401x series, -see `STM32F401x reference manual`_. More info about the board available -`here `_ and on `WeAct Github`_. - -.. image:: img/blackpill-v3.jpg - :align: center - :alt: Black Pill V3.0+ - -Hardware -******** - -The STM32F401CE based Black Pill V3.0+ Board provides the following -hardware components: - -- STM32F401CEU6 in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 84 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 96 KB SRAM -- GPIO with external interrupt capability -- 1x12-bit, 2.4 MSPS ADC with 16 channels -- DMA Controller -- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) -- USART/UART (3) -- I2C (3) -- SPI/I2S (5) -- SDIO -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- CRC calculation unit -- 96-bit unique ID -- RTC - -Supported Features -================== - -The Zephyr blackpill_f401ce board configuration supports the following -hardware features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/blackpill_f401ce/blackpill_f401ce_defconfig`` - -Pin Mapping -=========== - -Available pins: ---------------- -.. image:: img/Blackpill_Pinout.jpg - :align: center - :alt: Black Pill V3.0+ Pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- I2C1 SCL/SDA : PB8/PB9 -- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) -- PWM_4_CH1 : PB6 -- PWM_4_CH2 : PB7 -- ADC_1 : PA1 -- USER_PB : PA0 -- USER_LED : PC13 - -Note on SPI pin mapping: According to the `board release notes`_, there was a brief -change for V2.0 specifically where MISO was routed to PB4 for the flash footprint. -This was reverted for V2.1+ so that the flash DO pin was routed back to PA6. If using -V2.0 and en external flash, the pinmux will need to be modified accordingly. - -Clock Sources -------------- - -The board has two external oscillators. The frequency of the slow clock (LSE) is -32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. - -The default configuration sources the system clock from the PLL, which is -derived from HSE, and is set at 84MHz, which is the maximum possible frequency -to achieve a stable USB clock (42MHz). - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -There is also a Windows version which works, but you may have to install the -right USB drivers with a tool like `Zadig`_. - -Flashing an Application ------------------------ - -Connect a USB-C cable and the board should power ON. Force the board into DFU mode -by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. - -The dfu-util runner is supported on this board and so a sample can be built and -tested easily. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: blackpill_f401ce - :goals: build flash - -Debugging -========= - -The board can be debugged by installing the included 100 mil (0.1 inch) header, -and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO -pins on that header. - -References -********** - -.. target-notes:: - -.. _board release notes: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md - -.. _Zadig: - https://zadig.akeo.ie/ - -.. _WeAct Github: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 - -.. _stm32-base-board-page: - https://stm32-base.org/boards/STM32F401CEU6-WeAct-Black-Pill-V3.0.html - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _STM32F401CE website: - https://www.st.com/en/microcontrollers/stm32f401ce.html - -.. _STM32F401x reference manual: - https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/blackpill_f411ce/Kconfig.board b/boards/arm/blackpill_f411ce/Kconfig.board deleted file mode 100644 index c636f2af74a..00000000000 --- a/boards/arm/blackpill_f411ce/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2020 Brian Bradley -# SPDX-License-Identifier: Apache-2.0 - -# STM32F411CE based Black Pill V2.0+ board configuration - -config BOARD_BLACKPILL_F411CE - bool "WeAct Studio Black Pill V2.0+ Board" - depends on SOC_STM32F411XE diff --git a/boards/arm/blackpill_f411ce/Kconfig.defconfig b/boards/arm/blackpill_f411ce/Kconfig.defconfig deleted file mode 100644 index e54fc87004e..00000000000 --- a/boards/arm/blackpill_f411ce/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2020 Brian Bradley -# SPDX-License-Identifier: Apache-2.0 - -# F411CE based Black Pill V2.0+ board board configuration - -if BOARD_BLACKPILL_F411CE - -config BOARD - default "blackpill_f411ce" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_BLACKPILL_F411CE diff --git a/boards/arm/blackpill_f411ce/doc/index.rst b/boards/arm/blackpill_f411ce/doc/index.rst deleted file mode 100644 index 4d3023b462c..00000000000 --- a/boards/arm/blackpill_f411ce/doc/index.rst +++ /dev/null @@ -1,179 +0,0 @@ -.. _blackpill_f411ce: - -WeAct Studio Black Pill V2.0 -############################ - -Overview -******** - -The WeAct Black Pill V2.0 Board is an extremely low cost and bare-bones -development board featuring the STM32F411CE, see `STM32F411CE website`_. -This is the 48-pin variant of the STM32F411x series, -see `STM32F411x reference manual`_. More info about the board available -`here `_ and on `WeAct Github`_. - -.. image:: img/blackpill-v2.jpg - :align: center - :alt: Black Pill V2.0+ - -Hardware -******** - -The STM32F411CE based Black Pill V2.0+ Board provides the following -hardware components: - -- STM32F411CEU6 in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 128 KB SRAM -- GPIO with external interrupt capability -- 1x12-bit, 2.4 MSPS ADC with 16 channels -- DMA Controller -- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) -- USART/UART (3) -- I2C (3) -- SPI/I2S (5) -- SDIO -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- CRC calculation unit -- 96-bit unique ID -- RTC - -Supported Features -================== - -The Zephyr blackpill_f411ce board configuration supports the following -hardware features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32_blackpill_v2/stm32_blackpill_v2_defconfig`` - -Pin Mapping -=========== - -Available pins: ---------------- -.. image:: img/Blackpill_Pinout.jpg - :align: center - :alt: Black Pill V2.0+ Pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- I2C1 SCL/SDA : PB8/PB9 -- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) -- PWM_4_CH1 : PB6 -- PWM_4_CH2 : PB7 -- ADC_1 : PA1 -- USER_PB : PA0 -- USER_LED : PC13 - -Note on SPI pin mapping: According to the `board release notes`_, there was a brief -change for V2.0 specifically where MISO was routed to PB4 for the flash footprint. -This was reverted for V2.1+ so that the flash DO pin was routed back to PA6. If using -V2.0 and en external flash, the pinmux will need to be modified accordingly. - -Clock Sources -------------- - -The board has two external oscillators. The frequency of the slow clock (LSE) is -32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. - -The default configuration sources the system clock from the PLL, which is -derived from HSE, and is set at 96MHz, which is the maximum possible frequency -to achieve a stable USB clock (48MHz). - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -There is also a Windows version which works, but you may have to install the -right USB drivers with a tool like `Zadig`_. - -Flashing an Application ------------------------ - -Connect a USB-C cable and the board should power ON. Force the board into DFU mode -by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. - -The dfu-util runner is supported on this board and so a sample can be built and -tested easily. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: blackpill_f411ce - :goals: build flash - -Debugging -========= - -The board can be debugged by installing the included 100 mil (0.1 inch) header, -and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO -pins on that header. - -References -********** - -.. target-notes:: - -.. _board release notes: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md - -.. _Zadig: - https://zadig.akeo.ie/ - -.. _WeAct Github: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 - -.. _stm32-base-board-page: - https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0.html - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _STM32F411CE website: - https://www.st.com/en/microcontrollers/stm32f411ce.html - -.. _STM32F411x reference manual: - https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.board b/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.board deleted file mode 100644 index a4a2f1fab18..00000000000 --- a/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Blue Clover PLT Demo V2 Configuration - -# Copyright (c) 2021 Blue Clover -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 - bool "Blue Clover PLT Demo Board V2" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.defconfig b/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.defconfig deleted file mode 100644 index d1d96ca9fb0..00000000000 --- a/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Blue Clover PLT Demo V2 Configuration - -# Copyright (c) 2021 Blue Clover -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 - -config BOARD - default "blueclover_plt_demo_v2_nrf52832" - -config BT_CTLR - default BT - -config I2C - default SENSOR - -endif # BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/doc/index.rst b/boards/arm/blueclover_plt_demo_v2_nrf52832/doc/index.rst deleted file mode 100644 index 7a41d95e647..00000000000 --- a/boards/arm/blueclover_plt_demo_v2_nrf52832/doc/index.rst +++ /dev/null @@ -1,153 +0,0 @@ -.. _blueclover_plt_demo_v2_nrf52832: - -Blue Clover PLT Demo V2 nRF52832 -################################ - -Overview -******** - -The Blue Clover PLT Demo V2 is an open source (OSWHA certified) hardware -product, featuring the Nordic Semiconductor nRF52832 ARM Cortex-M4F MCU -and several useful external peripherals. - -The Nordic Semiconductor nRF52832 ARM Cortex-M4F MCU features the following: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/blueclover_plt_demo_v2.jpg - :align: center - :alt: Blue Clover PLT Demo V2 nRF52832 - -Hardware -******** - -- nRF52832 ARM Cortex-M4F processor at 64 MHz -- 512 KB flash memory and 64 KB of SRAM -- Bosch BMI270 IMU -- Sensiron SHT30 Humidity and Temperature sensor -- Murata PKLCS1212E4001R1 Piezo Buzzer -- Battery connector and charger for 3.7 V lithium polymer batteries -- 4 APA102C Addressable LEDs -- Reset button (can be configured as user button) -- 1 User button -- Tag-Connect TC2030-FP 6-pin Debug Connector - -Supported Features -================== - -The Blue Clover PLT Demo V2 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -Push buttons ------------- - -* RESET = P0.21 -* STATUS = P0.26 - -UART ----- - -* TXD = P0.06 -* RXD = P0.08 - -Power ------ - -* USB-C Connector -* JST-PH Battery Connector - -NFC ---- - -* U.FL Connector, on NFC1/P0.09, NFC2/P0.10 - -Programming and Debugging -************************* - -Applications for the ``blueclover_plt_demo_v2_nrf52832`` board configuration -can be built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - -Flashing -======== - -Flashing Zephyr onto the ``blueclover_plt_demo_v2_nrf52832`` board requires -an external programmer. The programmer is attached to the SWD header. - -Build the Zephyr kernel and the :zephyr:code-sample:`led-apa102` sample application. - - .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_apa102 - :board: blueclover_plt_demo_v2_nrf52832 - :goals: build - :compact: - -Flash the image. - - .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_apa102 - :board: blueclover_plt_demo_v2_nrf52832 - :goals: flash - :compact: - -References -********** - -.. target-notes:: - -.. _Blue Clover PLT Demo V2 Product site: - https://bcdevices.com/products/plt-demo-board - -.. _Blue Clover PLT Demo V2 OSWHA Certification: - https://certification.oshwa.org/us002054.html - -.. _Schematic, layout, and gerbers: - https://github.com/bcdevices/plt-docs/tree/master/PLT-DEMOv2 diff --git a/boards/arm/bt510/Kconfig.board b/boards/arm/bt510/Kconfig.board deleted file mode 100644 index e1654936f5f..00000000000 --- a/boards/arm/bt510/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BT510 DVK board configuration - -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BT510 - bool "BT510" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/bt510/Kconfig.defconfig b/boards/arm/bt510/Kconfig.defconfig deleted file mode 100644 index dc622170dd1..00000000000 --- a/boards/arm/bt510/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# BT510 Sensor configuration - -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BT510 - -config BOARD - default "bt510" - -config BT_CTLR - default BT - -config I2C - default SENSOR - -endif # BOARD_BT510 diff --git a/boards/arm/bt610/Kconfig.board b/boards/arm/bt610/Kconfig.board deleted file mode 100644 index cee1953cf31..00000000000 --- a/boards/arm/bt610/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BT610 board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BT610 - bool "BT610" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/bt610/Kconfig.defconfig b/boards/arm/bt610/Kconfig.defconfig deleted file mode 100644 index 34620afc27f..00000000000 --- a/boards/arm/bt610/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# BT6X0 Sensor configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BT610 - -config BOARD - default "bt610" - -config BT_CTLR - default BT - -config I2C - default $(dt_compat_on_bus,$(DT_COMPAT_TI_TCA9538),i2c) - -endif # BOARD_BT610 diff --git a/boards/arm/cc1352p1_launchxl/CMakeLists.txt b/boards/arm/cc1352p1_launchxl/CMakeLists.txt deleted file mode 100644 index 4c3dbf723e6..00000000000 --- a/boards/arm/cc1352p1_launchxl/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources( - board_antenna.c - ) diff --git a/boards/arm/cc1352p1_launchxl/Kconfig.board b/boards/arm/cc1352p1_launchxl/Kconfig.board deleted file mode 100644 index d6a880aa47a..00000000000 --- a/boards/arm/cc1352p1_launchxl/Kconfig.board +++ /dev/null @@ -1,20 +0,0 @@ -# TI CC1352R LaunchXL board - -# Copyright (c) 2021 Florin Stancu -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC1352P1_LAUNCHXL - bool "TI CC1352P1 LaunchXL" - depends on SOC_CC1352P - -if BOARD_CC1352P1_LAUNCHXL - -config BOARD_ANTENNA_INIT_PRIO - int "Board antenna switch initialization priority" - default 70 - help - Set the priority for board init, must be greater than - KERNEL_INIT_PRIORITY_DEVICE but smaller than - IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO. - -endif # BOARD_CC1352P1_LAUNCHXL diff --git a/boards/arm/cc1352p1_launchxl/Kconfig.defconfig b/boards/arm/cc1352p1_launchxl/Kconfig.defconfig deleted file mode 100644 index 907daaf0010..00000000000 --- a/boards/arm/cc1352p1_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# TI CC1352P1 LaunchXL board - -# Copyright (c) 2021 Florin Stancu -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC1352P1_LAUNCHXL - -config BOARD - default "cc1352p1_launchxl" - -endif # BOARD_CC1352P1_LAUNCHXL diff --git a/boards/arm/cc1352r1_launchxl/Kconfig.board b/boards/arm/cc1352r1_launchxl/Kconfig.board deleted file mode 100644 index 3c874a13962..00000000000 --- a/boards/arm/cc1352r1_launchxl/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# TI CC1352R LaunchXL board - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC1352R1_LAUNCHXL - bool "TI CC1352R1 LaunchXL" - depends on SOC_CC1352R diff --git a/boards/arm/cc1352r1_launchxl/Kconfig.defconfig b/boards/arm/cc1352r1_launchxl/Kconfig.defconfig deleted file mode 100644 index 8bee2c9aed2..00000000000 --- a/boards/arm/cc1352r1_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# TI CC1352R LaunchXL board - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC1352R1_LAUNCHXL - -config BOARD - default "cc1352r1_launchxl" - -endif # BOARD_CC1352R1_LAUNCHXL diff --git a/boards/arm/cc1352r_sensortag/Kconfig.board b/boards/arm/cc1352r_sensortag/Kconfig.board deleted file mode 100644 index 6364142ac0b..00000000000 --- a/boards/arm/cc1352r_sensortag/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# TI CC1352R SensorTag board - -# Copyright (c) 2019 Brett Witherspoon -# Copyright (c) 2020 Friedt Professional Engineering Services, Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC1352R_SENSORTAG - bool "TI CC1352R SensorTag" - depends on SOC_CC1352R diff --git a/boards/arm/cc1352r_sensortag/Kconfig.defconfig b/boards/arm/cc1352r_sensortag/Kconfig.defconfig deleted file mode 100644 index 41bf913bb99..00000000000 --- a/boards/arm/cc1352r_sensortag/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# TI CC1352R SensorTag board - -# Copyright (c) 2019 Brett Witherspoon -# Copyright (c) 2020 Friedt Professional Engineering Services, Inc -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC1352R_SENSORTAG - -config BOARD - default "cc1352r_sensortag" - -config SPI - default SENSOR - -endif # BOARD_CC1352R_SENSORTAG diff --git a/boards/arm/cc26x2r1_launchxl/Kconfig.board b/boards/arm/cc26x2r1_launchxl/Kconfig.board deleted file mode 100644 index cfc9da276fb..00000000000 --- a/boards/arm/cc26x2r1_launchxl/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# TI CC26x2R1 LaunchXL board - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC26X2R1_LAUNCHXL - bool "TI CC26x2R1 LaunchXL" - depends on SOC_CC2652R diff --git a/boards/arm/cc26x2r1_launchxl/Kconfig.defconfig b/boards/arm/cc26x2r1_launchxl/Kconfig.defconfig deleted file mode 100644 index 33d6541f47d..00000000000 --- a/boards/arm/cc26x2r1_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# TI CC26x2R1 LaunchXL board - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC26X2R1_LAUNCHXL - -config BOARD - default "cc26x2r1_launchxl" - -endif # BOARD_CC26X2R1_LAUNCHXL diff --git a/boards/arm/cc3220sf_launchxl/Kconfig.board b/boards/arm/cc3220sf_launchxl/Kconfig.board deleted file mode 100644 index c03cae76d68..00000000000 --- a/boards/arm/cc3220sf_launchxl/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# TI SimpleLink CC3220SF LaunchXL Board - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC3220SF_LAUNCHXL - bool "TI CC3220SF LAUNCHXL" - depends on SOC_CC3220SF diff --git a/boards/arm/cc3220sf_launchxl/Kconfig.defconfig b/boards/arm/cc3220sf_launchxl/Kconfig.defconfig deleted file mode 100644 index 2b2f801ed68..00000000000 --- a/boards/arm/cc3220sf_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# TI CC3220SF LaunchXL board configuration - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC3220SF_LAUNCHXL - -config BOARD - default "cc3220sf_launchxl" - -endif # BOARD_CC3220SF_LAUNCHXL diff --git a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig b/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig deleted file mode 100644 index ac49971fa14..00000000000 --- a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_CC3220SF_LAUNCHXL=y -CONFIG_SOC_SERIES_CC32XX=y -CONFIG_SOC_CC3220SF=y -CONFIG_BUILD_OUTPUT_HEX=y - - -#enable GPIO driver -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/cc3220sf_launchxl/doc/index.rst b/boards/arm/cc3220sf_launchxl/doc/index.rst deleted file mode 100644 index 4e941cef91e..00000000000 --- a/boards/arm/cc3220sf_launchxl/doc/index.rst +++ /dev/null @@ -1,325 +0,0 @@ -.. _cc3220sf_launchxl: - -CC3220SF LaunchXL -################# - -Overview -******** -The SimpleLink Wi-Fi CC3220SF LaunchPad development kit (CC3220SF-LAUNCHXL) -highlights CC3220SF, a single-chip wireless microcontroller (MCU) with -1MB internal flash, 4MB external serial flash, 256KB of RAM and enhanced -security features. - -See the `TI CC3220 Product Page`_ for details. - -Features: -========= - -* Two separate execution environments: a user application dedicated ARM - Cortex-M4 MCU and a network processor MCU to run all Wi-Fi and - internet logical layers -* 40-pin LaunchPad standard leveraging the BoosterPack ecosystem -* On-board accelerometer and temperature sensor -* Two buttons and three LEDs for user interaction -* UART through USB to PC -* BoosterPack plug-in module for adding graphical displays, audio - codecs, antenna selection, environmental sensing, and more -* Power from USB for the LaunchPad and optional external BoosterPack -* XDS110-based JTAG emulation with serial port for flash programming - -Details on the CC3220SF LaunchXL development board can be found in the -`CC3220SF LaunchPad Dev Kit Hardware User's Guide`_. - -Hardware -******** - -The CC3220SF SoC has two MCUs: - -#. Applications MCU - an ARM |reg| Cortex |reg|-M4 Core at 80 MHz, with 256Kb RAM, - and access to external serial 4MB flash with bootloader and peripheral - drivers in ROM. - -#. Network Coprocessor (NWP) - a dedicated ARM MCU, which completely - offloads Wi-Fi and internet protocols from the application MCU. - -Complete details of the CC3220SF SoC can be found in the `CC3220 TRM`_. - -Supported Features -================== - -Zephyr has been ported to the Applications MCU, with basic peripheral -driver support. - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| UART | on-chip | serial port-interrupt | -+-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-----------------------+ -| SPI_0 | on-chip | Wi-Fi host driver | -+-----------+------------+-----------------------+ - -.. note:: - - For consistency with TI SimpleLink SDK and BoosterPack examples, - the I2C driver defaults to I2C_BITRATE_FAST mode (400 kHz) bus speed - on bootup. - -The accelerometer, temperature sensors, or other peripherals -accessible through the BoosterPack, are not currently supported. - -Connections and IOs -==================== - -Peripherals on the CC3220SF LaunchXL are mapped to the following pins in -the file :zephyr_file:`boards/arm/cc3220sf_launchxl/pinmux.c`. - -+------------+-------+-------+ -| Function | PIN | GPIO | -+============+=======+=======+ -| UART0_TX | 55 | N/A | -+------------+-------+-------+ -| UART0_RX | 57 | N/A | -+------------+-------+-------+ -| LED D7 (R) | 64 | 9 | -+------------+-------+-------+ -| LED D6 (O) | 01 | 10 | -+------------+-------+-------+ -| LED D5 (G) | 02 | 11 | -+------------+-------+-------+ -| Switch SW2 | 15 | 22 | -+------------+-------+-------+ -| Switch SW3 | 04 | 13 | -+------------+-------+-------+ - -The default configuration can be found in the Kconfig file at -:zephyr_file:`boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig`. - - -Programming and Debugging -************************* - -TI officially supports development on the CC3220SF using the TI -`CC3220 SDK`_ on Windows and Linux using TI tools: Code Composer -Studio for debugging and `UniFlash`_ for flashing. - -For Windows developers, see the `CC3220 Getting Started Guide`_ for -instructions on installation of tools, and how to flash the board using -UniFlash. - -Note that zephyr.bin produced by the Zephyr SDK may not load via -UniFlash tool. If encountering difficulties, use the zephyr.elf -file and openocd instead (see below). - -The following instructions are geared towards Linux developers who -prefer command line tools to an IDE. - -Before flashing and debugging the board, there are a few one-time board -setup steps to follow. - -Prerequisites: -============== - -#. Download and install the latest version of `UniFlash`_. -#. Jumper SOP[2..0] (J15) to [010], and connect the USB cable to the PC. - - This should result in a new device "Texas Instruments XDS110 Embed - with CMSIS-DAP" appearing at /dev/ttyACM1 and /dev/ttyACM0. - -#. Update the service pack, and place the board in "Development Mode". - - Setting "Development Mode" enables the JTAG interface, necessary - for subsequent use of OpenOCD and updating XDS110 firmware. - - Follow the instructions in Section 2.4 "Download the Application", - in the `CC3220 Getting Started Guide`_, except for steps 5 and 6 in - Section 2.4.1 which select an MCU image. - -#. Ensure the XDS-110 emulation firmware is updated. - - Download and install the latest `XDS-110 emulation package`_. - - Follow these `xds110 firmware update directions - `_ - - Note that the emulation package install may place the xdsdfu utility - in ``/ccs_base/common/uscif/xds110/``. - -#. Switch Jumper SOP[2..0] (J15) back to [001]. - - Remove power from the board (disconnect USB cable) before switching jumpers. - -#. Install OpenOCD - - You can obtain OpenOCD by following these - :ref:`installing the latest Zephyr SDK instructions `. - - After the installation, add the directory containing the OpenOCD executable - to your environment's PATH variable. For example, use this command in Linux: - - .. code-block:: console - - export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH - - If you had previously installed TI OpenOCD, you can simply switch to use - the one in the Zephyr SDK. If for some reason you wish to continue to use - your TI OpenOCD installation, you can set the OPENOCD and - OPENOCD_DEFAULT_PATH variables in - :zephyr_file:`boards/arm/cc3220sf_launchxl/board.cmake` to point the build - to the paths of the OpenOCD binary and its scripts, before - including the common openocd.board.cmake file: - - .. code-block:: cmake - - set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) - set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - -#. Ensure CONFIG_XIP=y (default) is set. - - This locates the program into flash, and sets CONFIG_CC3220SF_DEBUG=y, - which prepends a debug header enabling the flash to persist over - subsequent reboots, bypassing the bootloader flash signature - verification. - - See Section 21.10 "Debugging Flash User Application Using JTAG" of the - `CC3220 TRM`_ for details on the secure flash boot process. - - -Once the above prerequisites are met, applications for the ``_cc3220sf_launchxl`` -board can be built, flashed, and debugged with openocd and gdb per the Zephyr -Application Development Primer (see :ref:`build_an_application` and -:ref:`application_run`). - -Flashing -======== - -To build and flash an application, execute the following commands for : - -.. zephyr-app-commands:: - :zephyr-app: - :board: cc3220sf_launchxl - :goals: flash - -This will load the image into flash. - -To see program output from UART0, connect a separate terminal window: - -.. code-block:: console - - % screen /dev/ttyACM0 115200 8N1 - -Then press the reset button (SW1) on the board to run the program. - -When using OpenOCD from Zephyr SDK to flash the device, you may notice -the program hangs when starting the network processor on the device, if the -program uses it. There is a known issue with how that version of OpenOCD -resets the network processor. You would need to manually hit the reset button -on the board to properly reset the device after flashing. - -Debugging -========= - -To debug a previously flashed image, after resetting the board, use the 'debug' -build target: - -.. zephyr-app-commands:: - :zephyr-app: - :board: cc3220sf_launchxl - :maybe-skip-config: - :goals: debug - - -Wi-Fi Support -************* - -The SimpleLink Host Driver, imported from the SimpleLink SDK, has been ported -to Zephyr, and communicates over a dedicated SPI to the network co-processor. -It is available as a Zephyr Wi-Fi device driver in -:zephyr_file:`drivers/wifi/simplelink`. - -Usage: -====== - -Set :kconfig:option:`CONFIG_WIFI_SIMPLELINK` and :kconfig:option:`CONFIG_WIFI` to ``y`` -to enable Wi-Fi. -See :zephyr_file:`samples/net/wifi/boards/cc3220sf_launchxl.conf`. - -Provisioning: -============= - -SimpleLink provides a few rather sophisticated Wi-Fi provisioning methods. -To keep it simple for Zephyr development and demos, the SimpleLink -"Fast Connect" policy is enabled, with one-shot scanning. -This enables the cc3220sf_launchxl to automatically reconnect to the last -good known access point (AP), without having to restart a scan, and -re-specify the SSID and password. - -To connect to an AP, first run the Zephyr Wi-Fi shell sample application, -and connect to a known AP with SSID and password. - -See :zephyr:code-sample:`wifi-shell` - -Once the connection succeeds, the network co-processor keeps the AP identity in -its persistent memory. Newly loaded Wi-Fi applications then need not explicitly -execute any Wi-Fi scan or connect operations, until the need to change to a new AP. - -Secure Socket Offload -********************* - -The SimpleLink Wi-Fi driver provides socket operations to the Zephyr socket -offload point, enabling Zephyr BSD socket API calls to be directed to the -SimpleLink Wi-Fi driver, by setting :kconfig:option:`CONFIG_NET_SOCKETS_OFFLOAD` -to ``y``. - -Secure socket (TLS) communication is handled as part of the socket APIs, -and enabled by: - -- setting both :kconfig:option:`CONFIG_NET_SOCKETS_SOCKOPT_TLS` - and :kconfig:option:`CONFIG_TLS_CREDENTIAL_FILENAMES` to ``y``, -- using the TI Uniflash tool to program the required certificates and - keys to the secure flash filesystem, and enabling the TI Trusted - Root-Certificate Catalog. - -See :zephyr:code-sample:`sockets-http-get` and -:zephyr_file:`samples/net/sockets/http_get/boards/cc3220sf_launchxl.conf` for an -example. - -See the document `Simplelink Wi-Fi Certificates Handling`_ for details on -using the TI UniFlash tool for certificate programming. - -References -********** - -CC32xx Wiki: - http://processors.wiki.ti.com/index.php/CC31xx_%26_CC32xx - -.. _TI CC3220 Product Page: - http://www.ti.com/product/cc3220 - -.. _CC3220 TRM: - http://www.ti.com/lit/pdf/swru465 - -.. _CC3220 Programmer's Guide: - http://www.ti.com/lit/pdf/swru464 - -.. _CC3220 Getting Started Guide: - http://www.ti.com/lit/pdf/swru461 - -.. _UniFlash: - http://processors.wiki.ti.com/index.php/Category:CCS_UniFlash - -.. _CC3220 SDK: - http://www.ti.com/tool/download/SIMPLELINK-CC3220-SDK - -.. _CC3220SF LaunchPad Dev Kit Hardware User's Guide: - http://www.ti.com/lit/pdf/swru463 - -.. _XDS-110 emulation package: - http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download - -.. _Simplelink Wi-Fi Certificates Handling: - http://www.ti.com/lit/pdf/swpu332 diff --git a/boards/arm/cc3235sf_launchxl/CMakeLists.txt b/boards/arm/cc3235sf_launchxl/CMakeLists.txt deleted file mode 100644 index 750f93d4af9..00000000000 --- a/boards/arm/cc3235sf_launchxl/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(dbghdr.c) diff --git a/boards/arm/cc3235sf_launchxl/Kconfig.board b/boards/arm/cc3235sf_launchxl/Kconfig.board deleted file mode 100644 index b119bc17456..00000000000 --- a/boards/arm/cc3235sf_launchxl/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# TI SimpleLink CC3235SF LaunchXL Board - -# Copyright (c) 2019, Texas Instruments Incorporated -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC3235SF_LAUNCHXL - bool "TI CC3235SF LAUNCHXL" - depends on SOC_CC3235SF diff --git a/boards/arm/cc3235sf_launchxl/Kconfig.defconfig b/boards/arm/cc3235sf_launchxl/Kconfig.defconfig deleted file mode 100644 index 36537918865..00000000000 --- a/boards/arm/cc3235sf_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# TI CC3235SF LaunchXL board configuration - -# Copyright (c) 2019, Texas Instruments Incorporated -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC3235SF_LAUNCHXL - -config BOARD - default "cc3235sf_launchxl" - -endif # BOARD_CC3235SF_LAUNCHXL diff --git a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl_defconfig b/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl_defconfig deleted file mode 100644 index a233de474a7..00000000000 --- a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_CC3235SF_LAUNCHXL=y -CONFIG_SOC_SERIES_CC32XX=y -CONFIG_SOC_CC3235SF=y -CONFIG_BUILD_OUTPUT_HEX=y - - -#enable GPIO driver -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/cc3235sf_launchxl/doc/index.rst b/boards/arm/cc3235sf_launchxl/doc/index.rst deleted file mode 100644 index 80a4fb3c0e9..00000000000 --- a/boards/arm/cc3235sf_launchxl/doc/index.rst +++ /dev/null @@ -1,325 +0,0 @@ -.. _cc3235sf_launchxl: - -CC3235SF LaunchXL -################# - -Overview -******** -The SimpleLink Wi-Fi CC3235SF LaunchPad development kit (CC3235SF-LAUNCHXL) -highlights CC3235SF, a single-chip wireless microcontroller (MCU) with -1MB internal flash, 4MB external serial flash, 256KB of RAM, and enhanced -security features. It supports 802.11 a/b/g/n, both 2.4 GHz and 5 GHz. - -See the `TI CC3235 Product Page`_ for details. - -Features: -========= - -* Two separate execution environments: a user application dedicated ARM - Cortex-M4 MCU and a network processor MCU to run all Wi-Fi and - internet logical layers -* 40-pin LaunchPad standard leveraging the BoosterPack ecosystem -* On-board accelerometer and temperature sensor -* Two buttons and a RGB LED for user interaction -* UART through USB to PC -* BoosterPack plug-in module for adding graphical displays, audio - codecs, antenna selection, environmental sensing, and more -* Power from USB for the LaunchPad and optional external BoosterPack -* XDS110-based JTAG emulation with serial port for flash programming - -Details on the CC3235SF LaunchXL development board can be found in the -`CC3235SF LaunchPad Dev Kit Hardware User's Guide`_. - -Hardware -******** - -The CC3235SF SoC has two MCUs: - -#. Applications MCU - an ARM |reg| Cortex |reg|-M4 Core at 80 MHz, with 256Kb RAM, - and access to external serial 4MB flash with bootloader and peripheral - drivers in ROM. - -#. Network Coprocessor (NWP) - a dedicated ARM MCU, which completely - offloads Wi-Fi and internet protocols from the application MCU. - -Complete details of the CC3235SF SoC can be found in the `CC3235 TRM`_. - -Supported Features -================== - -Zephyr has been ported to the Applications MCU, with basic peripheral -driver support. - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| UART | on-chip | serial port-interrupt | -+-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-----------------------+ -| SPI_0 | on-chip | Wi-Fi host driver | -+-----------+------------+-----------------------+ - -.. note:: - - For consistency with TI SimpleLink SDK and BoosterPack examples, - the I2C driver defaults to I2C_BITRATE_FAST mode (400 kHz) bus speed - on bootup. - -The accelerometer, temperature sensors, or other peripherals -accessible through the BoosterPack, are not currently supported. - -Connections and IOs -==================== - -Peripherals on the CC3235SF LaunchXL are mapped to the following pins in -the file :zephyr_file:`boards/arm/cc3235sf_launchxl/pinmux.c`. - -+------------+-------+-------+ -| Function | PIN | GPIO | -+============+=======+=======+ -| UART0_TX | 55 | N/A | -+------------+-------+-------+ -| UART0_RX | 57 | N/A | -+------------+-------+-------+ -| LED D7 (R) | 64 | 9 | -+------------+-------+-------+ -| LED D6 (O) | 01 | 10 | -+------------+-------+-------+ -| LED D5 (G) | 02 | 11 | -+------------+-------+-------+ -| Switch SW2 | 15 | 22 | -+------------+-------+-------+ -| Switch SW3 | 04 | 13 | -+------------+-------+-------+ - -The default configuration can be found in the Kconfig file at -:zephyr_file:`boards/arm/cc3235sf_launchxl/cc3235sf_launchxl_defconfig`. - - -Programming and Debugging -************************* - -TI officially supports development on the CC3235SF using the TI -`CC32xx SDK`_ on Windows and Linux using TI tools: Code Composer -Studio for debugging and `UniFlash`_ for flashing. - -For Windows developers, see the `CC32xx Quick Start Guide`_ for -instructions on installation of tools, and how to flash the board using -UniFlash. - -Note that ``zephyr.bin`` produced by the Zephyr SDK may not load via -UniFlash tool. If encountering difficulties, use the ``zephyr.elf`` -file and openocd instead (see below). - -The following instructions are geared towards Linux developers who -prefer command line tools to an IDE. - -Before flashing and debugging the board, there are a few one-time board -setup steps to follow. - -Prerequisites: -============== - -#. Download and install the latest version of `UniFlash`_. -#. Jumper SOP[2..0] (J15) to [010], and connect the USB cable to the PC. - - This should result in a new device "Texas Instruments XDS110 Embed - with CMSIS-DAP" appearing at /dev/ttyACM1 and /dev/ttyACM0. - -#. Update the service pack, and place the board in "Development Mode". - - Setting "Development Mode" enables the JTAG interface, necessary - for subsequent use of OpenOCD and updating XDS110 firmware. - - Follow the instructions in Section 2.4 "Download the Application", - in the `CC32xx Quick Start Guide`_, except for steps 5 and 6 in - Section 2.4.1 which select an MCU image. - -#. Ensure the XDS-110 emulation firmware is updated. - - Download and install the latest `XDS-110 emulation package`_. - - Follow these `xds110 firmware update directions - `_ - - Note that the emulation package install may place the xdsdfu utility - in ``/ccs_base/common/uscif/xds110/``. - -#. Switch Jumper SOP[2..0] (J15) back to [001]. - - Remove power from the board (disconnect USB cable) before switching jumpers. - -#. Install OpenOCD - - You can obtain OpenOCD by following these - :ref:`installing the latest Zephyr SDK instructions `. - - After the installation, add the directory containing the OpenOCD executable - to your environment's PATH variable. For example, use this command in Linux: - - .. code-block:: console - - export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH - - If you had previously installed TI OpenOCD, you can simply switch to use - the one in the Zephyr SDK. If for some reason you wish to continue to use - your TI OpenOCD installation, you can set the OPENOCD and - OPENOCD_DEFAULT_PATH variables in - :zephyr_file:`boards/arm/cc3220sf_launchxl/board.cmake` to point the build - to the paths of the OpenOCD binary and its scripts, before - including the common openocd.board.cmake file: - - .. code-block:: cmake - - set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) - set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - -#. Ensure CONFIG_XIP=y (default) is set. - - This locates the program into flash, and sets CONFIG_CC3235SF_DEBUG=y, - which prepends a debug header enabling the flash to persist over - subsequent reboots, bypassing the bootloader flash signature - verification. - - See Section 21.10 "Debugging Flash User Application Using JTAG" of the - `CC3235 TRM`_ for details on the secure flash boot process. - - -Once the above prerequisites are met, applications for the ``_cc3235sf_launchxl`` -board can be built, flashed, and debugged with openocd and gdb per the Zephyr -Application Development Primer (see :ref:`build_an_application` and -:ref:`application_run`). - -Flashing -======== - -To build and flash an application, execute the following commands for : - -.. zephyr-app-commands:: - :zephyr-app: - :board: cc3235sf_launchxl - :goals: flash - -This will load the image into flash. - -To see program output from UART0, connect a separate terminal window: - -.. code-block:: console - - % screen /dev/ttyACM0 115200 8N1 - -Then press the reset button (SW1) on the board to run the program. - -When using OpenOCD from Zephyr SDK to flash the device, you may notice -the program hangs when starting the network processor on the device, if the -program uses it. There is a known issue with how that version of OpenOCD -resets the network processor. You would need to manually hit the reset button -on the board to properly reset the device after flashing. - -Debugging -========= - -To debug a previously flashed image, after resetting the board, use the 'debug' -build target: - -.. zephyr-app-commands:: - :zephyr-app: - :board: cc3235sf_launchxl - :maybe-skip-config: - :goals: debug - - -Wi-Fi Support -************* - -The SimpleLink Host Driver, imported from the SimpleLink SDK, has been ported -to Zephyr, and communicates over a dedicated SPI to the network co-processor. -It is available as a Zephyr Wi-Fi device driver in -:zephyr_file:`drivers/wifi/simplelink`. - -Usage: -====== - -Set :kconfig:option:`CONFIG_WIFI_SIMPLELINK` and :kconfig:option:`CONFIG_WIFI` to ``y`` -to enable Wi-Fi. -See :zephyr_file:`samples/net/wifi/boards/cc3235sf_launchxl.conf`. - -Provisioning: -============= - -SimpleLink provides a few rather sophisticated Wi-Fi provisioning methods. -To keep it simple for Zephyr development and demos, the SimpleLink -"Fast Connect" policy is enabled, with one-shot scanning. -This enables the cc3235sf_launchxl to automatically reconnect to the last -good known access point (AP), without having to restart a scan, and -re-specify the SSID and password. - -To connect to an AP, first run the Zephyr Wi-Fi shell sample application, -and connect to a known AP with SSID and password. - -See :zephyr:code-sample:`wifi-shell` - -Once the connection succeeds, the network co-processor keeps the AP identity in -its persistent memory. Newly loaded Wi-Fi applications then need not explicitly -execute any Wi-Fi scan or connect operations, until the need to change to a new AP. - -Secure Socket Offload -********************* - -The SimpleLink Wi-Fi driver provides socket operations to the Zephyr socket -offload point, enabling Zephyr BSD socket API calls to be directed to the -SimpleLink Wi-Fi driver, by setting :kconfig:option:`CONFIG_NET_SOCKETS_OFFLOAD` -to ``y``. - -Secure socket (TLS) communication is handled as part of the socket APIs, -and enabled by: - -- setting both :kconfig:option:`CONFIG_NET_SOCKETS_SOCKOPT_TLS` - and :kconfig:option:`CONFIG_TLS_CREDENTIAL_FILENAMES` to ``y``, -- using the TI Uniflash tool to program the required certificates and - keys to the secure flash filesystem, and enabling the TI Trusted - Root-Certificate Catalog. - -See :zephyr:code-sample:`sockets-http-get` and -:zephyr_file:`samples/net/sockets/http_get/boards/cc3235sf_launchxl.conf` for an -example. - -See the document `Simplelink Wi-Fi Certificates Handling`_ for details on -using the TI UniFlash tool for certificate programming. - -References -********** - -TI SimpleLink MCUs: - http://www.ti.com/microcontrollers/simplelink-mcus/overview.html - -.. _TI CC3235 Product Page: - http://www.ti.com/product/cc3235SF - -.. _CC3235 TRM: - http://www.ti.com/lit/pdf/swru543 - -.. _CC3x20/CC3x35 SimpleLink Wi-Fi and IoT Network Processor Programmer's Guide: - http://www.ti.com/lit/pdf/swru455 - -.. _CC32xx Quick Start Guide: - http://dev.ti.com/tirex/content/simplelink_cc32xx_sdk_2_40_01_01/docs/simplelink_mcu_sdk/Quick_Start_Guide.html - -.. _UniFlash: - http://processors.wiki.ti.com/index.php/Category:CCS_UniFlash - -.. _CC32xx SDK: - http://www.ti.com/tool/download/SIMPLELINK-CC32xx-SDK/2.40.01.01 - -.. _CC3235SF LaunchPad Dev Kit Hardware User's Guide: - http://www.ti.com/lit/pdf/swru539 - -.. _XDS-110 emulation package: - http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download - -.. _Simplelink Wi-Fi Certificates Handling: - http://www.ti.com/lit/pdf/swpu332 diff --git a/boards/arm/circuitdojo_feather_nrf9160/Kconfig b/boards/arm/circuitdojo_feather_nrf9160/Kconfig deleted file mode 100644 index 78e7bbd4530..00000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Circuit Dojo nRF9160 Feather configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/circuitdojo_feather_nrf9160/Kconfig.board b/boards/arm/circuitdojo_feather_nrf9160/Kconfig.board deleted file mode 100644 index d69bc53f557..00000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Circuit Dojo nRF9160 Feather configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_CIRCUITDOJO_FEATHER_NRF9160 - bool "Circuit Dojo nRF9160 Feather" - -config BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS - bool "Circuit Dojo nRF9160 Feather non-secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/circuitdojo_feather_nrf9160/Kconfig.defconfig b/boards/arm/circuitdojo_feather_nrf9160/Kconfig.defconfig deleted file mode 100644 index 73648be3ef1..00000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Circuit Dojo nRF9160 Feather configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CIRCUITDOJO_FEATHER_NRF9160 || BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS - -config BOARD - default "circuitdojo_feather_nrf9160" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_CIRCUITDOJO_FEATHER_NRF9160 && TRUSTED_EXECUTION_SECURE - -if BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS - -endif # BOARD_CIRCUITDOJO_FEATHER_NRF9160 || BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_defconfig b/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_defconfig deleted file mode 100644 index f3dc6d6155c..00000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_CIRCUITDOJO_FEATHER_NRF9160=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# Hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# required to enable 3V3 power rail -CONFIG_REGULATOR=y diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns_defconfig b/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns_defconfig deleted file mode 100644 index 9f25a5dda67..00000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# Hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# required to enable 3V3 power rail -CONFIG_REGULATOR=y diff --git a/boards/arm/circuitdojo_feather_nrf9160/doc/index.rst b/boards/arm/circuitdojo_feather_nrf9160/doc/index.rst deleted file mode 100644 index f089c468e0d..00000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/doc/index.rst +++ /dev/null @@ -1,161 +0,0 @@ -.. _circuitdojo_feather_nrf9160: - -nRF9160 Feather -############### - -.. figure:: img/circuitdojo_feather_nrf9160.jpg - :align: center - :alt: Circuit Dojo nRF9160 Feather - - nRF9160 Feather (Credit: Circuit Dojo) - -Overview -******** - -The nRF9160 Feather by Circuit Dojo is a single-board development -for bringing your LTE-M and NB-IoT applications to life. The circuitdojo_feather_nrf9160 -board configuration leverages the pre-existing support for the Nordic Semiconductor -nRF9160. Supported nRF9160 peripherals include: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -More information about the board can be found at the -`nRF9160 Feather Documentation`_. - - -Hardware -******** - -.. figure:: img/nrf9160-feather-v31-features.jpg - :align: center - :alt: nRF9160 Feather Features - -Connections and IOs -=================== - -The nRF9160 Feather has everything you know and love about -the Feather platform. Here are some of the highlights: - -LED ---- - -* D7 (blue) = P0.03 - -Push buttons and Switches -------------------------- - -* MODE = P0.12 -* RESET - -USB ---- - -Contains a USB/UART connection for both debugging and loading new -code using a UART Enabled MCUBoot. - -Standard Battery Connection ----------------------------- - -The nRF9160 Feather has a 2 pin battery connector on board. Lithium Polymer batteries > -300mA required. - -Nano SIM Holder ---------------- - -The nRF9160 Feather has a built-in nano SIM (4FF) holder located -on the bottom side. - - -Programming and Debugging -************************* - -circuitdojo_feather_nrf9160 has a Tag Connect TC2030-CTX-NL. It can be used -by most programmers like: - -* J-Link (the nRF53-DK is recommended) -* CMSIS-DAP based programmers - -Check out `Getting Started`_ for more info. - -Building an application -======================= - -In most cases you'll want to use the ``ns`` target with any of the Zephyr -or Nordic based examples. - -.. note:: - Trusted Firmware-M (TF-M) and building the ``ns`` target is not supported for this board. - -Some of the examples do not use secure mode, so they do not require the -``ns`` suffix. A great example of this is the `hello_world` below. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ screen /dev/ 115200 - -Replace :code:`` with the port where the nRF9160 Feather -can be found. In most cases (On Linux/Mac) it will be: :code:`/dev/tty.SLAB_USBtoUART`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: circuitdojo_feather_nrf9160 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons on the nRF9160 Feather -*************************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common.dtsi`. - -References -********** - -.. target-notes:: - -**Side note** This page was based on the documentation for the nRF9160 DK. Thanks to Nordic for -developing a great platform! - -.. _nRF9160 Feather Documentation: https://docs.jaredwolff.com/nrf9160-introduction.html -.. _Getting Started: https://docs.jaredwolff.com/nrf9160-getting-started.html diff --git a/boards/arm/colibri_imx7d_m4/Kconfig.board b/boards/arm/colibri_imx7d_m4/Kconfig.board deleted file mode 100644 index 016ebca5eff..00000000000 --- a/boards/arm/colibri_imx7d_m4/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Colibri iMX7D M4 board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_COLIBRI_IMX7D_M4 - bool "Toradex Colibri iMX7 Dual" - depends on SOC_SERIES_IMX7_M4 - select SOC_PART_NUMBER_MCIMX7D5EVM10SC diff --git a/boards/arm/colibri_imx7d_m4/Kconfig.defconfig b/boards/arm/colibri_imx7d_m4/Kconfig.defconfig deleted file mode 100644 index 59253032e0a..00000000000 --- a/boards/arm/colibri_imx7d_m4/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Colibri iMX7D M4 board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_COLIBRI_IMX7D_M4 - -config BOARD - default "colibri_imx7d_m4" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - - -endif # BOARD_COLIBRI_IMX7D_M4 diff --git a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts b/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts deleted file mode 100644 index fc78324c803..00000000000 --- a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2017,2019 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "colibri_imx7d_m4-pinctrl.dtsi" -#include - -/ { - model = "TORADEX Colibri IMX7D board"; - compatible = "nxp,mcimx7d_m4"; - - aliases { - led0 = &green_led; - sw0 = &user_switch_1; - }; - - chosen { - zephyr,flash = &tcml_code; - zephyr,sram = &tcmu_sys; - zephyr,console = &uart2; - zephyr,shell-uart = &uart2; - }; - - leds { - compatible = "gpio-leds"; - green_led: led_0 { - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - label = "User LED1"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_switch_1: user_sw_1 { - gpios = <&gpio2 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "User SW1"; - zephyr,code = ; - }; - }; -}; - -&uart2 { - status = "okay"; - current-speed = <115200>; - modem-mode = <64>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_default>; - pinctrl-names = "default"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_default>; - pinctrl-names = "default"; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm1 { - pinctrl-0 = <&pwm1_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm2 { - pinctrl-0 = <&pwm2_default>; - pinctrl-names = "default"; -}; - -&pwm3 { - pinctrl-0 = <&pwm3_default>; - pinctrl-names = "default"; -}; - -&pwm4 { - pinctrl-0 = <&pwm4_default>; - pinctrl-names = "default"; -}; - -&mub { - status = "okay"; -}; diff --git a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.yaml b/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.yaml deleted file mode 100644 index ce87d91e4cd..00000000000 --- a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: colibri_imx7d_m4 -name: TORADEX Colibri IMX7D -type: mcu -arch: arm -ram: 32 -flash: 32 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -supported: - - pwm -vendor: nxp diff --git a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4_defconfig b/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4_defconfig deleted file mode 100644 index 7ffa3899880..00000000000 --- a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX7_M4=y -CONFIG_SOC_MCIMX7_M4=y -CONFIG_BOARD_COLIBRI_IMX7D_M4=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/arm/colibri_imx7d_m4/doc/index.rst b/boards/arm/colibri_imx7d_m4/doc/index.rst deleted file mode 100644 index f8de598f794..00000000000 --- a/boards/arm/colibri_imx7d_m4/doc/index.rst +++ /dev/null @@ -1,324 +0,0 @@ -.. _colibri_imx7d_m4: - -NXP i.MX 7 Computer on Module - Colibri iMX7 -############################################ - -Overview -******** - -The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7 -core and Single Cortex M4 core. -Zephyr was ported to run on the M4 core. In a later release, it will also -communicate with the A7 core (running Linux) via RPmsg. - - -.. image:: colibri_imx7d_m4.jpg - :align: center - :alt: Colibri-iMX7 - -Hardware -******** - -- i.MX7 Single/Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core - -- Memory - - - RAM -> A7: 256MB, 512MB and 1GB - - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) - - Flash -> A7: 4Gb eMMC and 512Mb NAND - -- Display - - - RGB 1920x1080x24bpp - - 4-wire Resistive touch - -- Multimedia - - - 1x Camera Parallel Interface - - 1x Analog Audio Line in (Stereo) - - 1x Analog Audio Mic in (Mono) - - 1x Analog Audio Headphone out (Stereo) - -- Connectivity - - - USB 2.0 OTG (High Speed) - - USB 2.0 host (High Speed) - - 10/100 Mbit/s Ethernet PHY - - 4x I2C - - 4x SPI - - 7x UART - - 1x IrDA - - 20x PWM - - Up to 125 GPIO - - 4x Analog Input (12 Bit) - - 2x SDIO/SD/MMC (8 Bit) - - 2x CAN - -For more information about the i.MX 7 SoC, Colibri iMX7 Computer on Module -and Colibri Evaluation Board, see these references: - -- `i.MX 7 Series Website`_ -- `i.MX 7 Dual Datasheet`_ -- `i.MX 7 Dual Reference Manual`_ -- `Colibri iMX7 Website`_ -- `Colibri iMX7 User Guide`_ -- `Colibri iMX7 Datasheet`_ -- `Colibri Evaluation Board Website`_ -- `Colibri Evaluation Board Datasheet`_ - -Supported Features -================== - -The Colibri iMX7D Computer on Module with Colibri Evaluation Board configuration -supports the following hardware features on the Cortex M4 Core: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/colibri_imx7d_m4/colibri_imx7d_m4_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The Colibri iMX7D Computer on Module with Colibri Evaluation Board -was tested with the following pinmux controller configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART_B RXD | UART2_TXD | UART Console | -+---------------+-----------------+---------------------------+ -| UART_B TXD | UART2_RXD | UART Console | -+---------------+-----------------+---------------------------+ -| SODIMM_135 | GPIO1_IO02 | LED0 | -+---------------+-----------------+---------------------------+ -| SODIMM_133 | GPIO2_IO26 | SW0 | -+---------------+-----------------+---------------------------+ -| SODIMM_194 | I2C4_SDA | I2C_SDA | -+---------------+-----------------+---------------------------+ -| SODIMM_196 | I2C4_SCL | I2C_SCL | -+---------------+-----------------+---------------------------+ -| SODIMM_59 | PWM1/GPIO1_IO08 | PWM | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 200 MHz clock speed. - -Serial Port -=========== - -The iMX7D SoC has seven UARTs. The number 2 is configured for the console and -the remaining are not used/tested. - -Programming and Debugging -************************* - -The Colibri iMX7D doesn't have QSPI flash for the M4 and it needs to be started by -the A7 core. The A7 core is responsible to load the M4 binary application into the -RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get -the M4 out of reset. -The A7 can perform these steps at bootloader level or after the Linux system has -booted. - -The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: - -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=======================+========================+=======================+======================+ -| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ - - -References -========== - -- `i.MX 7 Dual Reference Manual`_ from page 190 (section 2.1.2 and 2.1.3) -- `Toradex Wiki`_ - - -At compilation time you have to choose which RAM will be used. This configuration is -done in the file ``boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts`` with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" -properties. The available configurations are: - -.. code-block:: none - - "zephyr,flash" - - &ddr_code - - &tcml_code - - &ocram_code - - &ocram_s_code - - &ocram_pxp_code - - &ocram_epdc_code - - "zephyr,sram" - - &ddr_sys - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - - &ocram_pxp_sys - - &ocram_epdc_sys - - -Below you will find the instructions to load and run Zephyr on M4 from A7 using u-boot. - -Copy the compiled zephyr.bin to the first EXT partition of the SD card and plug into the -board. Power it up and stop the u-boot execution. -Set the u-boot environment variables and run the zephyr.bin from the appropriated memory -configured in the Zephyr compilation: - -.. code-block:: console - - setenv bootm4 'ext4load mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' - # TCML - setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' - setenv bootm4tcml 'run m4tcml && run bootm4' - run bootm4tcml - # TCMU - setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' - setenv bootm4tcmu 'run m4tcmu && run bootm4' - run bootm4tcmu - # OCRAM - setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' - setenv bootm4ocram 'run m4ocram && run bootm4' - run bootm4ocram - # OCRAM_S - setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' - setenv bootm4ocrams 'run m4ocrams && run bootm4' - run bootm4ocrams - # DDR - setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' - setenv bootm4ddr 'run m4ddr && run bootm4' - run bootm4ddr - - -Debugging -========= - -Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. - -To run Zephyr Binary using J-Link create the following script in order to -get the Program Counter and Stack Pointer from zephyr.bin. - -get-pc-sp.sh: - -.. code-block:: console - - #!/bin/sh - - firmware=$1 - - pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') - sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') - - echo pc=$pc - echo sp=$sp - - -Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` - -.. code-block:: console - - pc=00900f01 - sp=00905020 - -Plug in the J-Link into the board and PC and run the J-Link command line tool: - -.. code-block:: console - - /usr/bin/JLinkExe -device Cortex-M4 -if JTAG -speed 4000 -autoconnect 1 -jtagconf -1,-1 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript - -The following steps are necessary to run the zephyr.bin: -1. Put the M4 core in reset -2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) -3. Set PC (Program Counter) -4. Set SP (Stack Pointer) -5. Get the M4 core out of reset - -Issue the following commands inside J-Link commander: - -.. code-block:: console - - w4 0x3039000C 0xAC - loadfile zephyr.bin,0x00900000 - w4 0x00180000 00900f01 - w4 0x00180004 00905020 - w4 0x3039000C 0xAA - -With these mechanisms, applications for the ``colibri_imx7d_m4`` board -configuration can be built and debugged in the usual way (see -:ref:`build_an_application` and :ref:`application_run` for more details). - -References -========== - -- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ -- `J-Link iMX7D Instructions`_ - -.. _Colibri Evaluation Board Website: - https://www.toradex.com/products/carrier-board/colibri-evaluation-carrier-board - -.. _Colibri Evaluation Board Datasheet: - https://docs.toradex.com/102284-colibri-evaluation-board-datasheet.pdf - -.. _Colibri iMX7 Website: - https://www.toradex.com/computer-on-modules/colibri-arm-family/nxp-freescale-imx7 - -.. _Colibri iMX7 User Guide: - https://developer.toradex.com/products/colibri-imx7 - -.. _Colibri iMX7 Datasheet: - https://docs.toradex.com/103125-colibri-arm-som-imx7-datasheet.pdf - -.. _i.MX 7 Series Website: - https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 - -.. _i.MX 7 Dual Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf - -.. _i.MX 7 Dual Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX7DRM - -.. _J-Link Tools: - https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack - -.. _NXP iMX7D Connect CortexM4.JLinkScript: - https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript - -.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: - https://www.nxp.com/docs/en/application-note/AN5317.pdf - -.. _J-Link iMX7D Instructions: - https://wiki.segger.com/IMX7D - -.. _Toradex Wiki: - https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/contextualelectronics_abc/Kconfig b/boards/arm/contextualelectronics_abc/Kconfig deleted file mode 100644 index 26558cc557c..00000000000 --- a/boards/arm/contextualelectronics_abc/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# ABC board configuration - -# Copyright (c) 2020 Analog Life LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_CONTEXTELEC_ABC diff --git a/boards/arm/contextualelectronics_abc/Kconfig.board b/boards/arm/contextualelectronics_abc/Kconfig.board deleted file mode 100644 index f1dc7ce2fec..00000000000 --- a/boards/arm/contextualelectronics_abc/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# ABC board configuration - -# Copyright (c) 2020 Analog Life LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CONTEXTELEC_ABC - bool "nRF52840 based Advanced BLE Cell" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/contextualelectronics_abc/Kconfig.defconfig b/boards/arm/contextualelectronics_abc/Kconfig.defconfig deleted file mode 100644 index da35c9e482a..00000000000 --- a/boards/arm/contextualelectronics_abc/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52840 BLE Cell board configuration - -# Copyright (c) 2020 Bilal Wasim -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CONTEXTELEC_ABC - -config BOARD - default "nrf52840_ble_cell" - -config BT_CTLR - default BT - -endif # BOARD_CONTEXTELEC_ABC diff --git a/boards/arm/contextualelectronics_abc/board.cmake b/boards/arm/contextualelectronics_abc/board.cmake deleted file mode 100644 index 720d557c48d..00000000000 --- a/boards/arm/contextualelectronics_abc/board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set (OPENOCD_NRF5_SUBFAMILY "nrf52") -board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") -board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/cy8ckit_062_ble/Kconfig.board b/boards/arm/cy8ckit_062_ble/Kconfig.board deleted file mode 100644 index 6b7dd89566f..00000000000 --- a/boards/arm/cy8ckit_062_ble/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# PSoC6 BLE Pioneer Kit configuration - -# Copyright (c) 2018 Cypress -# Copyright (c) 2020 ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CY8CKIT_062_BLE_M0 - bool "PSoC6 BLE Pioneer Kit [M0 CPU0]" - depends on SOC_PART_NUMBER_CY8C6347BZI_BLD53 - -config BOARD_CY8CKIT_062_BLE_M4 - bool "PSoC6 BLE Pioneer Kit [M4 CPU1]" - depends on SOC_PART_NUMBER_CY8C6347BZI_BLD53 diff --git a/boards/arm/cy8ckit_062_ble/Kconfig.defconfig b/boards/arm/cy8ckit_062_ble/Kconfig.defconfig deleted file mode 100644 index 52da0daab3b..00000000000 --- a/boards/arm/cy8ckit_062_ble/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# PSoC6 BLE Pioneer Kit configuration - -# Copyright (c) 2018 Cypress -# Copyright (c) 2020 ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CY8CKIT_062_BLE_M0 || \ - BOARD_CY8CKIT_062_BLE_M4 - -config BOARD - default "cy8ckit_062_ble_m0" if BOARD_CY8CKIT_062_BLE_M0 - default "cy8ckit_062_ble_m4" if BOARD_CY8CKIT_062_BLE_M4 - -endif # BOARD_CY8CKIT_062_BLE_M0 || \ - # BOARD_CY8CKIT_062_BLE_M4 diff --git a/boards/arm/cy8ckit_062_ble/board.cmake b/boards/arm/cy8ckit_062_ble/board.cmake deleted file mode 100644 index f04a18a6697..00000000000 --- a/boards/arm/cy8ckit_062_ble/board.cmake +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_BOARD_CY8CKIT_062_BLE_M0) -board_runner_args(jlink "--device=CY8C6xx7_CM0p" "--speed=2000") -endif() -if(CONFIG_BOARD_CY8CKIT_062_BLE_M4) -board_runner_args(jlink "--device=CY8C6xx7_CM4" "--speed=2000") -endif() - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0.yaml b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0.yaml deleted file mode 100644 index ee63e4356a5..00000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020-2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: cy8ckit_062_ble_m0 -name: Cypress PSoC6 BLE Pioneer Kit (M0) -type: mcu -arch: arm -ram: 288 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - arduino_gpio - - arduino_spi - - gpio - - spi -vendor: cypress diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_0_0_0.conf b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_0_0_0.conf deleted file mode 100644 index 4b132fd5509..00000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_0_0_0.conf +++ /dev/null @@ -1,5 +0,0 @@ -# -# Copyright (c) 2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_1_0_0.conf b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_1_0_0.conf deleted file mode 100644 index 4b132fd5509..00000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_1_0_0.conf +++ /dev/null @@ -1,5 +0,0 @@ -# -# Copyright (c) 2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_defconfig b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_defconfig deleted file mode 100644 index c01d1a64400..00000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_PSOC63=y -CONFIG_SOC_PSOC6_M0=y -CONFIG_SOC_PART_NUMBER_CY8C6347BZI_BLD53=y -CONFIG_BOARD_CY8CKIT_062_BLE_M0=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_BUILD_OUTPUT_HEX=y - -# UART driver -CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4.yaml b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4.yaml deleted file mode 100644 index b490c8f3fbe..00000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020-2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: cy8ckit_062_ble_m4 -name: Cypress PSoC6 BLE Pioneer Kit (M4) -type: mcu -arch: arm -ram: 288 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - arduino_gpio - - gpio -vendor: cypress diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_0_0_0.conf b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_0_0_0.conf deleted file mode 100644 index 4b132fd5509..00000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_0_0_0.conf +++ /dev/null @@ -1,5 +0,0 @@ -# -# Copyright (c) 2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_defconfig b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_defconfig deleted file mode 100644 index 34478a7c553..00000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_PSOC63=y -CONFIG_SOC_PSOC6_M4=y -CONFIG_SOC_PART_NUMBER_CY8C6347BZI_BLD53=y -CONFIG_BOARD_CY8CKIT_062_BLE_M4=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_BUILD_OUTPUT_HEX=y - -# UART driver -CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_ble/doc/index.rst b/boards/arm/cy8ckit_062_ble/doc/index.rst deleted file mode 100644 index 7bf45437ca7..00000000000 --- a/boards/arm/cy8ckit_062_ble/doc/index.rst +++ /dev/null @@ -1,305 +0,0 @@ -.. _cy8ckit_062_ble: - -INFINEON PSoC63 BLE Pioneer Kit -############################### - -Overview -******** - -The PSoC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) is a hardware platform that -enables design and debug of the Cypress PSoC 63 BLE MCU. - -The PSoC 6 BLE Pioneer Kit features the PSoC 63 MCU: a dual-core MCU, with a -150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm -Cortex-M0+ that supports low-power operations, 1MB of Flash, 288KB of SRAM, -an integrated BLE 4.2 radio, 78 GPIO, 7 programmable analog blocks, 12 -programmable digital blocks, and capacitive-sensing with CapSense. - -The PSoC 6 BLE Pioneer board offers compatibility with Arduino shields, a -512-Mb NOR flash, onboard programmer/debugger (KitProg2), USB Type-C power -delivery system (EZ-PD™ CCG3), 5-segment CapSense slider, two CapSense -buttons, one CapSense proximity sensing header, an RGB LED, two user LEDs, -and one push button. - -The CY8CKIT-062-BLE package includes a CY8CKIT-028-EPD E-INK Display Shield -that contains a 2.7-inch E-INK display, a motion sensor, a thermistor, and a -PDM microphone. The kit package also contains a CY5677 CySmart BLE 4.2 USB -Dongle that is factory-programmed to emulate a BLE GAP Central device, -enabling you to emulate a BLE host on your computer. - -The Cortex-M0+ is a primary core on the board's SoC. It starts first and -enables the CM4 core. - -.. image:: img/cy8ckit-062-ble.jpg - :align: center - :alt: CY8CKIT_062_BLE - -1. Battery charging indicator (LED6) -2. USB PD output voltage availability indicator (LED7) -3. KitProg2 USB Type-C connector (J10) -4. Cypress EZ-PD™ CCG3 Type-C Port Controller with PD (CYPD3125-40LQXI, U3) -5. KitProg2 programming mode selection button (SW3) -6. KitProg2 I/O header (J6)1 -7. KitProg2 programming/custom application header (J7)1 -8. External power supply connector (J9) -9. PSoC 6 BLE user button (SW2) -10. KitProg2 application selection button (SW4) -11. Digilent® Pmod™ compatible I/O header (J14)1 -12. Power LED (LED4) -13. KitProg2 status LEDs (LED1, LED2, and LED3) -14. PSoC 6 reset button (SW1) -15. PSoC 6 I/O header (J18, J19 and J20) -16. Arduino™ Uno R3 compatible power header (J1) -17. PSoC 6 debug and trace header (J12) -18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4) -19. PSoC 6 program and debug header (J11) -20. KitProg2 programming target selection switch (SW6) -21. CapSense slider and buttons -22. CapSense proximity header (J13) -23. PSoC 6 BLE VDD selection switch (SW5) -24. PSoC 6 BLE power monitoring jumper (J8)2 -25. Arduino Uno R3 compatible ICSP header (J5)1 -26. PSoC 6 user LEDs (LED8 and LED9) -27. RGB LED (LED5) -28. Cypress 512-Mbit serial NOR Flash memory (S25FL512S, U4) -29. Cypress serial Ferroelectric RAM (U5)1 -30. VBACKUP and PMIC control selection switch (SW7)2 -31. Cypress PSoC 6 BLE (CY8C6347BZI-BLD53, U1) -32. BLE Antenna -33. U.FL connector for external antenna (J17)1 -34. Cypress main voltage regulator (MB39C022G, U6) -35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) -36. Battery connector (J15)1,2 -37. USB PD output voltage (9V/12V) connector (J16) - -Hardware -******** - -For more information about the PSoC 63 BLE MCU SoC and CY8CKIT-062-BLE board: - -- `PSoC 63 BLE MCU SoC Website`_ -- `PSoC 63 BLE MCU Datasheet`_ -- `PSoC 63 BLE MCU Architecture Reference Manual`_ -- `PSoC 63 BLE MCU Register Reference Manual`_ -- `CY8CKIT-062-BLE Website`_ -- `CY8CKIT-062-BLE User Guide`_ -- `CY8CKIT-062-BLE Schematics`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-----------------------+ -| PINCTRL | on-chip | pin control | -+-----------+------------+-----------------------+ -| SPI | on-chip | spi | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ - - -The default configurations can be found in the Kconfig -:zephyr_file:`boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_defconfig` for -Cortex-M0+ and on the Kconfig -:zephyr_file:`boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_defconfig` for -Cortex-M4 - -System Clock -============ - -The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for -the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the -system clock are provided in the SOC, depending on your system requirements. - -Serial Port -=========== - -The PSoC 63 BLE MCU SoC has 8 SCB blocks and each one can be configured as -UART/SPI/I2C interfaces for serial communication. At the moment UART5 on SCB5 -and UART6 on SCB6 are configured. SCB5 is connected to the onboard KitProg2's -USB-UART Bridge working as a serial console interface. SCB6 to P13_0, P13_1 -pins on the J3 of the Arduino Uno R3 compatible PSoC6 I/O header for general -purposes. - -OpenOCD Installation -==================== - -To get the OpenOCD package, it is required that you - -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd - -Programming and Debugging -************************* - -The CY8CKIT-062-BLE includes an onboard programmer/debugger (KitProg2) with -mass storage programming to provide debugging, flash programming, and serial -communication over USB. There are also PSoC 6 program and debug headers J11 -and J12 that can be used with Segger J-Link [default]. -A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and -Cy_WDT_Disable(). - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cy8ckit_062_ble_m0 - :goals: build - :compact: - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cy8ckit_062_ble_m0 - :goals: flash - :compact: - - You should see "Hello World! cy8ckit_062_ble_m0" in your terminal. - -Running on Dual Core -******************** - -#. Build the Zephyr kernel and the :zephyr:code-sample:`button` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: cy8ckit_062_ble_m4 - :goals: build - :compact: - -#. If you have a USB-Serial adapter, you can connect SBC[UART]-6 on Arduino - header. Schematic should be checked for connections. Run your favorite - terminal program again now listen for another output. Under Linux the - terminal should be :code:`/dev/ttyUSB0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: cy8ckit_062_ble_m4 - :goals: flash - :compact: - -#. Configure Cortex-M0+ to enable Cortex-M4: - - The last step flash the M4 image on the flash. However, Cortex-M0 by default - doesn't start the M4 and nothing will happen. To enable Cortex-M4 CPU, - repeat the steps on programming and debug and add the following parameter - when performing the build process. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cy8ckit_062_ble_m0 - :goals: build flash - :gen-args: -DCONFIG_SOC_PSOC6_M0_ENABLES_M4=y - :compact: - - Now you can press button SW-2 and see LED-9 blink at same time you have the - "Hello World! cy8ckit_062_ble_m0" in the your terminal. - -Board Revision -************** - -The CY8CKIT-062-BLE KitProg2 shares connections with Arduino-R3 header. This -connections may not allow the correct use of shields. The default board -revision (0.0.0) allows use of default connections. The use of Arduino headers -are only possible after rework the board and using the revision 1.0.0. - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application for - board revision 1.0.0: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cy8ckit_062_ble_m0@1.0.0 - :goals: build - :compact: - -#. The differences from version 0.0.0 to 1.0.0: - -+-------------+------------+------------+ -| Connection | 0.0.0 | 1.0.0 | -+=============+============+============+ -| CDC-COM RX | P5_0 | P9_0 | -+-------------+------------+------------+ -| CDC-COM TX | P5_1 | P9_1 | -+-------------+------------+------------+ -| R77 | X | | -+-------------+------------+------------+ -| R78 | | X | -+-------------+------------+------------+ - - -The P9 pins are available at J2. Those signals should be routed to J6. - -J2-2 to J6-14 -J2-4 to J6-13 - -The most complex part is short circuit pins 14 and 15 from U13. That connect -UART_RTS with UART_CTS from KitProg2. - -References -********** - -.. _PSoC 63 BLE MCU SoC Website: - https://www.cypress.com/products/32-bit-arm-cortex-m4-cortex-m0-psoc-63-connectivity-line - -.. _PSoC 63 BLE MCU Datasheet: - https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-63-ble-datasheet-programmable-system-chip-psoc - -.. _PSoC 63 BLE MCU Architecture Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-63-ble-architecture-technical-reference - -.. _PSoC 63 BLE MCU Register Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-cy8c63x6-cy8c63x7-cy8c63x6-cy8c63x7-registers - -.. _CY8CKIT-062-BLE Website: - https://www.cypress.com/documentation/development-kitsboards/psoc-6-ble-pioneer-kit-cy8ckit-062-ble - -.. _CY8CKIT-062-BLE User Guide: - https://www.cypress.com/file/390496/download - -.. _CY8CKIT-062-BLE Schematics: - https://www.cypress.com/file/417021/download diff --git a/boards/arm/cy8ckit_062_ble/revision.cmake b/boards/arm/cy8ckit_062_ble/revision.cmake deleted file mode 100644 index c9c8841d61e..00000000000 --- a/boards/arm/cy8ckit_062_ble/revision.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_check_revision(FORMAT MAJOR.MINOR.PATCH DEFAULT_REVISION 0.0.0) diff --git a/boards/arm/cy8ckit_062_wifi_bt/Kconfig.board b/boards/arm/cy8ckit_062_wifi_bt/Kconfig.board deleted file mode 100644 index 62f30b443d2..00000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# PSoC6 WiFi-BT Pioneer Kit configuration - -# Copyright (c) 2018 Cypress -# Copyright (c) 2020 ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CY8CKIT_062_WIFI_BT_M0 - bool "PSoC6 WiFi-BT Pioneer Kit M0" - depends on SOC_PART_NUMBER_CY8C6247BZI_D54 - -config BOARD_CY8CKIT_062_WIFI_BT_M4 - bool "PSoC6 WiFi-BT Pioneer Kit M4" - depends on SOC_PART_NUMBER_CY8C6247BZI_D54 diff --git a/boards/arm/cy8ckit_062_wifi_bt/Kconfig.defconfig b/boards/arm/cy8ckit_062_wifi_bt/Kconfig.defconfig deleted file mode 100644 index d30250160d6..00000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# PSoC6 WiFi-BT Pioneer Kit configuration - -# Copyright (c) 2020 ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CY8CKIT_062_WIFI_BT_M0 || \ - BOARD_CY8CKIT_062_WIFI_BT_M4 - -config BOARD - default "cy8ckit_062_wifi_bt_m0" if BOARD_CY8CKIT_062_WIFI_BT_M0 - default "cy8ckit_062_wifi_bt_m4" if BOARD_CY8CKIT_062_WIFI_BT_M4 - -endif # BOARD_CY8CKIT_062_WIFI_BT_M0 || \ - # BOARD_CY8CKIT_062_WIFI_BT_M4 diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0.yaml b/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0.yaml deleted file mode 100644 index a639fc9b700..00000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: cy8ckit_062_wifi_bt_m0 -name: Cypress PSoC6 WiFi-BT Pioneer Kit (M0) -type: mcu -arch: arm -ram: 288 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio -vendor: cypress diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0_defconfig b/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0_defconfig deleted file mode 100644 index 0518f65026b..00000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_PSOC62=y -CONFIG_SOC_PSOC6_M0=y -CONFIG_SOC_PART_NUMBER_CY8C6247BZI_D54=y -CONFIG_BOARD_CY8CKIT_062_WIFI_BT_M0=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_BUILD_OUTPUT_HEX=y - -# UART driver -CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4.yaml b/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4.yaml deleted file mode 100644 index 70c6db96740..00000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: cy8ckit_062_wifi_bt_m4 -name: Cypress PSoC6 WiFi-BT Pioneer Kit (M4) -type: mcu -arch: arm -ram: 288 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio -vendor: cypress diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4_defconfig b/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4_defconfig deleted file mode 100644 index 37cf0025685..00000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_PSOC62=y -CONFIG_SOC_PSOC6_M4=y -CONFIG_SOC_PART_NUMBER_CY8C6247BZI_D54=y -CONFIG_BOARD_CY8CKIT_062_WIFI_BT_M4=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_BUILD_OUTPUT_HEX=y - -# UART driver -CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_wifi_bt/doc/index.rst b/boards/arm/cy8ckit_062_wifi_bt/doc/index.rst deleted file mode 100644 index e1d6d16ef0a..00000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/doc/index.rst +++ /dev/null @@ -1,208 +0,0 @@ -.. _cy8ckit_062_wifi_bt: - -INFINEON PSoC6 WiFi-BT Pioneer Kit -################################## - -Overview -******** - -The PSoC 6 WiFi-BT Pioneer Kit (CY8CKIT-062-WiFi-BT) is a low-cost hardware -platform that enables design and debug of the PSoC 62 MCU and the Murata -LBEE5KL1DX Module (CYW4343W WiFi + Bluetooth Combo Chip). - -The PSoC 6 WiFi-BT Pioneer Kit features the PSoC 62 MCU: a -dual-core MCU, with a 150-MHz Arm Cortex-M4 as the primary application -processor and a 100-MHz Arm Cortex-M0+ that supports low-power operations, -1MB of Flash, 288KB of SRAM, 104 GPIO, 7 programmable analog blocks, -56 programmable digital blocks, Full-Speed USB, a serial memory interface, -a PDM-PCM digital microphone interface, and industry-leading capacitive-sensing -with CapSense. - -The PSoC 6 WiFi-BT Pioneer board offers compatibility with Arduino shields. - -The Cortex-M0+ is a primary core on the board's SoC. It starts first and -enables the CM4 core. - -.. image:: img/cy8ckit_062_wifi_bt_m0.jpg - :align: center - :alt: CY8CKIT_062_WIFI_BT - -1. USB PD output voltage availability indicator (LED7) -2. Battery charging indicator (LED6) -3. KitProg2 USB Type-C connector (J10) -4. Cypress EZ-PD™ CCG3 Type-C Port Controller with PD (CYPD3125-40LQXI, U3) -5. KitProg2 programming mode selection button (SW3) -6. KitProg2 I/O header (J6)1 -7. KitProg2 programming/custom application header (J7)1 -8. External power supply connector (J9) -9. PSoC 6 user button (SW2) -10. KitProg2 application selection button (SW4) -11. Digilent® Pmod™ compatible I/O header (J14)1 -12. Power LED (LED4) -13. KitProg2 status LEDs (LED1, LED2, and LED3) -14. PSoC 6 reset button (SW1) -15. PSoC 6 I/O header (J18, J19 and J20) -16. Arduino™ Uno R3 compatible power header (J1) -17. PSoC 6 debug and trace header (J12) -18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4) -19. PSoC 6 program and debug header (J11) -20. CapSense proximity header (J13) -21. CapSense slider and buttons -22. PSoC 6 VDD selection switch (SW5) -23. Cypress 512-Mbit serial NOR Flash memory (S25-FL512S, U4) -24. PSoC 6 user LEDs (LED8 and LED9) -25. RGB LED (LED5) -26. WiFi/BT module (LBEE5KL 1DX, U6) -27. Cypress serial Ferroelectric RAM (U5)1 -28. WiFi-BT Antenna -29. VBACKUP and PMIC control selection switch (SW7)2 -30. PSoC 6 USB device Type-C connector (J28) -31. Cypress PSoC 6 (CY8C6247BZI-D54, U1) -32. PSoC 6 USB Host Type-A connector (J27) -33. Arduino Uno R3 compatible ICSP header (J5)1 -34. PSoC 6 power monitoring jumper (J8)2 -35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) -36. Battery connector (J15)1,2 -37. USB PD output voltage (9V/12V) connector (J16) - -Hardware -******** - -For more information about the PSoC 62 MCU SoC and CY8CKIT-062-WiFi-BT board: - -- `PSoC 62 MCU SoC Website`_ -- `PSoC 62 MCU Datasheet`_ -- `PSoC 62 MCU Architecture Reference Manual`_ -- `PSoC 62 MCU Register Reference Manual`_ -- `CY8CKIT-062-WiFi-BT Website`_ -- `CY8CKIT-062-WiFi-BT User Guide`_ -- `CY8CKIT-062-WiFi-BT Schematics`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| PINCTRL | on-chip | pin control | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ - - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0_defconfig`. - - -System Clock -============ - -The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for -the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the -system clock are provided in the SOC, depending on your system requirements. - -Serial Port -=========== - -The PSoC 62 MCU SoC has 9 SCB blocks 8 of each can be configured as UART -interfaces for serial communication. At the moment UART5 on SCB5 and UART6 on -SCB6 are configured. SCB5 is connected to the onboard KitProg2's USB-UART -Bridge, SCB6 to P12_0, P12_1 pins on the J3 of the Arduino Uno R3 compatible -PSoC6 I/O header. - -OpenOCD Installation -==================== - -To get the OpenOCD package, it is required that you - -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd - - -Programming and Debugging -************************* - -The CY8CKIT-062-WiFi-BT includes an onboard programmer/debugger (KitProg2) with -mass storage programming to provide debugging, flash programming, and serial -communication over USB. There are also PSoC 6 program and debug headers J11 -and J12 that can be used with Segger J-Link. -A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and -Cy_WDT_Disable(). - -Only the CM0+ core starts by default after the MCU reset. In order to have -CM4 core working FW for both cores should be written into Flash. CM0+ FW -should starts the CM4 core at one point using -Cy_SysEnableCM4(CM4_START_ADDRESS); call. CM4_START_ADDRESS is 0x10060000 in -the current configuration. The CM0+/CM4 Flash/SRAM areas are defined in -:zephyr_file:`dts/arm/cypress/psoc6.dtsi`. - -Build the project for CM0+ - -.. zephyr-app-commands:: - :board: cy8ckit_062_wifi_bt_m0 - :goals: build - -Switch the DevKit into CMSIS-DAP mode using SW3 (LED2 should blink) and flash -the board: - -.. code-block:: console - - $\bin\openocd -c "source [find interface/cmsis-dap.cfg]" \ - -c "transport select swd" -c "source [find target/psoc6.cfg]" \ - -c "if [catch {program {\samples\hello_world\build\zephyr\zephyr.elf}} ] \ - { echo {** Program operation failed **} } \ - else { echo {** Program operation completed successfully **} }" \ - -c "reset_config srst_only;reset run;psoc6.dap dpreg 0x04 0x00;shutdown" - -Switch the DevKit back using SW3. Open a serial terminal (minicom, putty, -etc.) and connect to the board with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and the following message will appear on the corresponding -serial port: - -.. code-block:: console - - ***** Booting Zephyr OS zephyr-v1.13.0-1877-g9d14874db1 ***** - Hello World! cy8ckit_062_wifi_bt_m0 - - -References -********** - -.. _PSoC 62 MCU SoC Website: - https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 - -.. _PSoC 62 MCU Datasheet: - https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-62-datasheet-programmable-system-chip-psoc-preliminary - -.. _PSoC 62 MCU Architecture Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-architecture-technical-reference-manual - -.. _PSoC 62 MCU Register Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-register-technical-reference-manual-trm - -.. _CY8CKIT-062-WiFi-BT Website: - https://www.cypress.com/documentation/development-kitsboards/psoc-6-wifi-bt-pioneer-kit - -.. _CY8CKIT-062-WiFi-BT User Guide: - https://www.cypress.com/file/407731/download - -.. _CY8CKIT-062-WiFi-BT Schematics: - https://www.cypress.com/file/420846/download diff --git a/boards/arm/cy8ckit_062s4/Kconfig.board b/boards/arm/cy8ckit_062s4/Kconfig.board deleted file mode 100644 index ab9cc0284e6..00000000000 --- a/boards/arm/cy8ckit_062s4/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 David Ullmann -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CY8CKIT_062S4_M4 - bool "PSoC 62S4 pioneer kit" - depends on SOC_CY8C6244LQI_S4D92 diff --git a/boards/arm/cy8ckit_062s4/Kconfig.defconfig b/boards/arm/cy8ckit_062s4/Kconfig.defconfig deleted file mode 100644 index 616fc65bb13..00000000000 --- a/boards/arm/cy8ckit_062s4/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 David Ullmann -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CY8CKIT_062S4_M4 - -config BOARD - default "cy8ckit_062s4_m4" if BOARD_CY8CKIT_062S4_M4 - - -endif #BOARD_CY8CKIT_062S4_M4 diff --git a/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.yaml b/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.yaml deleted file mode 100644 index 19391fa39c4..00000000000 --- a/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2023 David Ullmann - -identifier: cy8ckit_062s4_m4 -name: CY8CKIT-062S4 PSoC 62S4 -type: mcu -arch: arm -ram: 128 -flash: 256 -toolchain: - - zephyr - - gnuarmemb -supported: - - gpio -vendor: cypress diff --git a/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4_defconfig b/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4_defconfig deleted file mode 100644 index 875c7f83f55..00000000000 --- a/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2023 David Ullmann -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_PSOC_62=y -CONFIG_BOARD_CY8CKIT_062S4_M4=y -CONFIG_SOC_CY8C6244LQI_S4D92=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_PINCTRL=y -CONFIG_SOC_PSOC6_CM0P_IMAGE_SLEEP=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CORTEX_M_SYSTICK=y -CONFIG_XIP=y diff --git a/boards/arm/cy8ckit_062s4/doc/index.rst b/boards/arm/cy8ckit_062s4/doc/index.rst deleted file mode 100644 index 4e2cad8a0f1..00000000000 --- a/boards/arm/cy8ckit_062s4/doc/index.rst +++ /dev/null @@ -1,115 +0,0 @@ -.. _cy8ckit_062s4: - -[INFINEON PSoC 62S4 Pioneer Kit] -################################ - -Overview -******** -The PSOC 62S4 Pioneer kit has a CY8C62x4 MCU, which is an ultra-low-power PSoC device specifically designed for battery-operated analog -sensing applications. It includes a 150-MHz Arm® Cortex®-M4 CPU as the primary application processor, a 100-MHz Arm® Cortex®-M0+ CPU that -supports low-power operations, up to 256 KB Flash and 128 KB SRAM, programmable analog sensing, -CapSense™ touch-sensing, and programmable digital peripherals. - -The board features an onboard -programmer/debugger (KitProg3), a 512-Mbit Quad SPI NOR flash, a micro-B connector for USB device -interface, a thermistor, an ambient light sensor, a 5-segment CapSense™ slider, two CapSense™ buttons, two -user LEDs, and a push button. The board supports operating voltages from 1.8 V to 3.3 V for PSoC™ 6 MCU. - -.. figure::img/cy8ckit_062s4.png - :width: 800px - :align: center - :alt: Board Name - - Board Name (Credit: ) - -Hardware -******** - -`CY8CKIT 062S4 Pioneer Kit Website`_ -`CY8CKIT 062S4 Pioneer Kit Guide`_ -`CY8CKIT 062S4 Pioneer Kit Schematic`_ -`CY8CKIT 062S4 Pioneer Kit Technical Reference Manual`_ -`CY8CKIT 062S4 Pioneer Kit Datasheet`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| PINCTRL | on-chip | pin control | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -+-----------+------------+-----------------------+ - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4_defconfig`. - -Clock Configuration -=================== - -+-----------+------------+-----------------------+ -| Clock | Source | Output Frequency | -+===========+============+=======================+ -| FLL | IMO | 100.0 MHz | -+-----------+------------+-----------------------+ -| PLL | IMO | 48.0 MHz | -+-----------+------------+-----------------------+ -| CLK_HF0 | CLK_PATH0 | 100.0 MHz | -+-----------+------------+-----------------------+ - -Fetch Binary Blobs -================== - -.. code-block:: console - - west blobs fetch hal_infineon - - -Build and flash hello world sample -********************************** - - -.. code-block:: console - - cd zephyr/samples/hello_world - west build -p auto -b cy8ckit_062s4_m4 --pristine - west flash - picocom /dev/ttyACM0 -b 115200 - -OpenOCD Installation -==================== - -To get the OpenOCD package, it is required that you - -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd - -References -********** - -.. _CY8CKIT 062S4 Pioneer Kit Guide: - https://www.infineon.com/dgdl/Infineon-CY8CKIT_062S4_PSoC62S4_pioneer_kit_guide-UserManual-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017e962f98992207 - -.. _CY8CKIT 062S4 Pioneer Kit Website: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8ckit-062s4/?redirId=VL1508&utm_medium=referral&utm_source=cypress&utm_campaign=202110_globe_en_all_integration-dev_kit - -.. _CY8CKIT 062S4 Pioneer Kit Schematic: - https://www.infineon.com/dgdl/Infineon-CY8CKIT-062S4_PSoC_62S4_Pioneer_Kit_Schematic-PCBDesignData-v01_00-EN.pdf?fileId=8ac78c8c7d710014017d7153484d2081 - -.. _CY8CKIT 062S4 Pioneer Kit Technical Reference Manual: - https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C61X4CY8C62X4_REGISTERS_TECHNICAL_REFERENCE_MANUAL_(TRM)_PSOC_61_PSOC_62_MCU-AdditionalTechnicalInformation-v03_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0fb34f0627a7 - -.. _CY8CKIT 062S4 Pioneer Kit Datasheet: - https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_CY8C62X4-DataSheet-v12_00-EN.pdf?fileId=8ac78c8c7ddc01d7017ddd026d585901 diff --git a/boards/arm/cy8cproto_062_4343w/Kconfig.board b/boards/arm/cy8cproto_062_4343w/Kconfig.board deleted file mode 100644 index ab708cfb438..00000000000 --- a/boards/arm/cy8cproto_062_4343w/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit - -# Copyright (c) 2021 Cypress Semiconductor Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CY8CPROTO_062_4343W - bool "CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit" diff --git a/boards/arm/cy8cproto_062_4343w/Kconfig.defconfig b/boards/arm/cy8cproto_062_4343w/Kconfig.defconfig deleted file mode 100644 index 0ed2d372835..00000000000 --- a/boards/arm/cy8cproto_062_4343w/Kconfig.defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit configuration - -# Copyright (c) 2021 Cypress Semiconductor Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CY8CPROTO_062_4343W - -config BOARD - default "cy8cproto_062_4343w" - -if WIFI || BT - -# Select AIROC part and module -choice AIROC_PART - default CYW4343W -endchoice - -choice CYW4343W_MODULE - default CYW4343W_MURATA_1DX -endchoice - -endif # WIFI || BT - -if WIFI - -config WIFI_AIROC - default y - -# Enable L2 Ethernet -config NET_L2_ETHERNET - default y - -endif # WIFI - -if BT - -# Select HCI components -config UART - bool - default y - -config BT_UART - default y - -choice BT_HCI_BUS_TYPE - default BT_H4 -endchoice - -endif # BT - -# Heap Pool Size -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 15000 if WIFI - default 4096 - -endif # BOARD_CY8CPROTO_062_4343W diff --git a/boards/arm/cy8cproto_062_4343w/doc/index.rst b/boards/arm/cy8cproto_062_4343w/doc/index.rst deleted file mode 100644 index 9cf9c942591..00000000000 --- a/boards/arm/cy8cproto_062_4343w/doc/index.rst +++ /dev/null @@ -1,184 +0,0 @@ -.. _cy8cproto_062_4343w: - -INFINEON CY8CPROTO-062-4343W -############################ - -Overview -******** - -The CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Prototyping Kit is a low-cost hardware -platform that enables design and debug of PSoC 6 MCUs. It comes with a Murata -LBEE5KL1DX module, based on the CYW4343W combo device, industry-leading CAPSENSE -for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD -card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone, and a thermistor. - -This kit is designed with a snap-away form-factor, allowing the user to separate -the different components and features that come with this kit and use independently. -In addition, support for Digilent's Pmod interface is also provided with this kit. - -.. image:: img/board.jpg - :align: center - :alt: CY8CPROTO-062-4343W - -Hardware -******** - -For more information about the PSoC 62 MCU SoC and CY8CPROTO-062-4343W board: - -- `PSoC 62 MCU SoC Website`_ -- `PSoC 62 MCU Datasheet`_ -- `PSoC 62 MCU Architecture Reference Manual`_ -- `PSoC 62 MCU Register Reference Manual`_ -- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Website`_ -- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT User Guide`_ -- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Schematics`_ - -Kit Features: -============= - -- Support of up to 2MB Flash and 1MB SRAM -- Dedicated SDHC to interface with WICED wireless devices. -- Delivers dual-cores, with a 150-MHz Arm Cortex-M4 as the primary - application processor and a 100-MHz Arm Cortex-M0+ as the secondary - processor for low-power operations. -- Supports Full-Speed USB, capacitive-sensing with CAPSENSE, a PDM-PCM - digital microphone interface, a Quad-SPI interface, 13 serial communication - blocks, 7 programmable analog blocks, and 56 programmable digital blocks. - -Kit Contents: -============= - -- PSoC 6 Wi-Fi BT Prototyping Board -- USB Type-A to Micro-B cable -- Quick Start Guide - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| GPIO | on-chip | GPIO | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ - - -The default configuration can be found in the Kconfig - -:zephyr_file:`boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig` - - -System Clock -============ - -The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for -the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the -system clock are provided in the SOC, depending on your system requirements. - - -Fetch Binary Blobs -****************** - -cy8cproto_062_4343w board requires fetch binary files -(e.g WIFI/Bluetooth chip firmware, CM0p prebuilt images, etc). - -To fetch Binary Blobs: - -.. code-block:: console - - west blobs fetch hal_infineon - - -Build blinking led sample -************************* - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. code-block:: console - - cd zephyr - west build -p auto -b cy8cproto_062_4343w samples/basic/blink - -OpenOCD Installation -==================== - -To get the OpenOCD package, it is required that you - -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd - - -Programming and Debugging -************************* - -The CY8CPROTO-062-4343W includes an onboard programmer/debugger (KitProg2) with -mass storage programming to provide debugging, flash programming, and serial -communication over USB. Flash and debug commands must be pointed to the Cypress -OpenOCD you downloaded above. - -On Windows: - -.. code-block:: console - - west flash --openocd path/to/infineon/openocd/bin/openocd.exe - west debug --openocd path/to/infineon/openocd/bin/openocd.exe - -On Linux: - -.. code-block:: console - - west flash --openocd path/to/infineon/openocd/bin/openocd - west debug --openocd path/to/infineon/openocd/bin/openocd - -Once the gdb console starts after executing the west debug command, you may -now set breakpoints and perform other standard GDB debugging on the PSoC 6 CM4 core. - -Errata -====== - -+------------------------------------------------+----------------------------------------+ -| Problem | Solution | -+================================================+========================================+ -| The GPIO_INT_TRIG_BOTH interrupt is not raised | This will be fixed in a future release.| -| when the associated GPIO is asserted. | | -+------------------------------------------------+----------------------------------------+ -| GDB experiences a timeout error connecting to | This will be fixed in a future release.| -| a server instance started by west debugserver. | | -+------------------------------------------------+----------------------------------------+ - -.. _PSoC 62 MCU SoC Website: - https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 - -.. _PSoC 62 MCU Datasheet: - https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-62-datasheet-programmable-system-chip-psoc-preliminary - -.. _PSoC 62 MCU Architecture Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-architecture-technical-reference-manual - -.. _PSoC 62 MCU Register Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-register-technical-reference-manual-trm - -.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Website: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/ - -.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT User Guide: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/#!?fileId=8ac78c8c7d0d8da4017d0f0118571844 - -.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Schematics: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/#!?fileId=8ac78c8c7d0d8da4017d0f01126b183f - -.. _Infineon OpenOCD: - https://github.com/infineon/openocd/releases/tag/release-v4.3.0 diff --git a/boards/arm/cy8cproto_063_ble/Kconfig.board b/boards/arm/cy8cproto_063_ble/Kconfig.board deleted file mode 100644 index f4fd16cef11..00000000000 --- a/boards/arm/cy8cproto_063_ble/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit -# -# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CY8CPROTO_063_BLE - bool "CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit with single CPU" diff --git a/boards/arm/cy8cproto_063_ble/Kconfig.defconfig b/boards/arm/cy8cproto_063_ble/Kconfig.defconfig deleted file mode 100644 index d6e691e3f02..00000000000 --- a/boards/arm/cy8cproto_063_ble/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit - -# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CY8CPROTO_063_BLE - -config BOARD - default "cy8cproto_063_ble" - -choice BT_HCI_BUS_TYPE - default BT_PSOC6_BLESS if BT -endchoice - -endif # BOARD_CY8CPROTO_063_BLE diff --git a/boards/arm/cy8cproto_063_ble/doc/index.rst b/boards/arm/cy8cproto_063_ble/doc/index.rst deleted file mode 100644 index 58ac2a98183..00000000000 --- a/boards/arm/cy8cproto_063_ble/doc/index.rst +++ /dev/null @@ -1,145 +0,0 @@ -.. _cy8cproto_063_ble: - -INFINEON CY8CPROTO-063-BLE -########################### - -Overview -******** - -The PSoC 6 BLE Proto Kit (CY8CPROTO-063-BLE) is a hardware platform that -enables design and debug of the Cypress PSoC 63 BLE MCU. - -.. image:: img/cy8cproto-063-ble.jpg - :align: center - :alt: CY8CPROTO-063-BLE - -Hardware -******** - -For more information about the PSoC 63 BLE MCU SoC and CY8CPROTO-063-BLE board: - -- `PSoC 63 BLE MCU SoC Website`_ -- `PSoC 63 BLE MCU Datasheet`_ -- `PSoC 63 BLE MCU Architecture Reference Manual`_ -- `PSoC 63 BLE MCU Register Reference Manual`_ -- `CY8CPROTO-063-BLE Website`_ -- `CY8CPROTO-063-BLE User Guide`_ -- `CY8CPROTO-063-BLE Schematics`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-----------------------+ -| PINCTRL | on-chip | pin control | -+-----------+------------+-----------------------+ -| SPI | on-chip | spi | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ -| I2C | on-chip | I2C | -+-----------+------------+-----------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-----------------------+ -| Counter | on-chip | Counter | -+-----------+------------+-----------------------+ -| Bluetooth | on-chip | Bluetooth | -+-----------+------------+-----------------------+ - - -The default configurations can be found in the Kconfig - -:zephyr_file:`boards/arm/cy8cproto_063_ble/cy8cproto_063_ble_defconfig` - -System Clock -============ - -The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for -the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the -system clock are provided in the SOC, depending on your system requirements. - - -OpenOCD Installation -==================== - -To get the OpenOCD package, it is required that you - -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd - - -Fetch Binary Blobs -****************** - -cy8cproto_063_ble board requires fetch binary files -(e.g Bluetooth controller firmware, CM0p prebuilt images, etc). - -To fetch Binary Blobs: - -.. code-block:: console - - west blobs fetch hal_infineon - -Programming and Debugging -************************* - -The CY8CPROTO-063-BLE includes an onboard programmer/debugger (KitProg3) with -mass storage programming to provide debugging, flash programming, and serial -communication over USB. Flash and debug commands must be pointed to the Cypress -OpenOCD you downloaded above. - -On Windows: - -.. code-block:: console - - west flash --openocd path/to/infineon/openocd/bin/openocd.exe - west debug --openocd path/to/infineon/openocd/bin/openocd.exe - -On Linux: - -.. code-block:: console - - west flash --openocd path/to/infineon/openocd/bin/openocd - west debug --openocd path/to/infineon/openocd/bin/openocd - -References -********** - -.. _PSoC 63 BLE MCU SoC Website: - https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 - -.. _PSoC 63 BLE MCU Datasheet: - https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_PSoC_63_with_BLE_Datasheet_Programmable_System-on-Chip_(PSoC)-DataSheet-v16_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee4efe46c37&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files - -.. _PSoC 63 BLE MCU Architecture Reference Manual: - https://documentation.infineon.com/html/psoc6/zrs1651212645947.html - -.. _PSoC 63 BLE MCU Register Reference Manual: - https://documentation.infineon.com/html/psoc6/bnm1651211483724.html - -.. _CY8CPROTO-063-BLE Website: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/ - -.. _CY8CPROTO-063-BLE User Guide: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/#!?fileId=8ac78c8c7d0d8da4017d0f00d7eb1812 - -.. _CY8CPROTO-063-BLE Schematics: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/#!?fileId=8ac78c8c7d0d8da4017d0f00ea3c1821 - -.. _Infineon OpenOCD: - https://github.com/infineon/openocd/releases/tag/release-v4.3.0 diff --git a/boards/arm/cyclonev_socdk/Kconfig.board b/boards/arm/cyclonev_socdk/Kconfig.board deleted file mode 100644 index 9743baf1cc5..00000000000 --- a/boards/arm/cyclonev_socdk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Cyclone V SoC development kit configuration option - -config BOARD_CVSXDEVKIT - bool "Intel Cyclone V Development Kit" - depends on SOC_CYCLONE5 diff --git a/boards/arm/cyclonev_socdk/Kconfig.defconfig b/boards/arm/cyclonev_socdk/Kconfig.defconfig deleted file mode 100644 index 240a8575380..00000000000 --- a/boards/arm/cyclonev_socdk/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC DevKit - -if BOARD_CVSXDEVKIT - -config BOARD - default "cyclonev_socdk" -depends on BOARD_CVSXDEVKIT - -if I2C_DW -config I2C_DW_CLOCK_SPEED - default 200 -endif # I2C_DW - -if USB_DEVICE_STACK -config USB_DW_USB_2_0 - default y -config USB_DEVICE_DRIVER - default y -endif # USB_DEVICE_STACK - -if NETWORKING - -config NET_L2_ETHERNET - default y -config TEST_RANDOM_GENERATOR - default y - -endif # NETWORKING - -endif # BOARD_CVSXDEVKIT diff --git a/boards/arm/cyclonev_socdk/board.cmake b/boards/arm/cyclonev_socdk/board.cmake deleted file mode 100644 index fe4c06d5484..00000000000 --- a/boards/arm/cyclonev_socdk/board.cmake +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Cmake file for the OpenOCD runner for Cyclone V SoC DevKit - -board_set_flasher_ifnset(intel_cyclonev) -board_set_debugger_ifnset(intel_cyclonev) - -if(OPENOCD_USE_LOAD_IMAGE) - set_ifndef(OPENOCD_FLASH load_image) -else() - set_ifndef(OPENOCD_FLASH "flash write_image erase") -endif() - -set(OPENOCD_CMD_LOAD_DEFAULT "${OPENOCD_FLASH}") -set(OPENOCD_CMD_VERIFY_DEFAULT "verify_image") - -board_finalize_runner_args(intel_cyclonev - --cmd-load "${OPENOCD_CMD_LOAD_DEFAULT}" - --cmd-verify "${OPENOCD_CMD_VERIFY_DEFAULT}" - ) - diff --git a/boards/arm/cyclonev_socdk/cyclonev_socdk_defconfig b/boards/arm/cyclonev_socdk/cyclonev_socdk_defconfig deleted file mode 100644 index 110a703d4a1..00000000000 --- a/boards/arm/cyclonev_socdk/cyclonev_socdk_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Cyclone V SoC Development Kit Board configuration file - -CONFIG_SOC_SERIES_CYCLONE5=y -CONFIG_SOC_CYCLONE5=y -CONFIG_BOARD_CVSXDEVKIT=y -CONFIG_ARM_ARCH_TIMER=y - -CONFIG_SYSCON=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_NS16550_VARIANT_NS16950=y - -#Config Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -#Flash not used. -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0x0 - -# GPIOs -CONFIG_GPIO=y diff --git a/boards/arm/cyclonev_socdk/doc/index.rst b/boards/arm/cyclonev_socdk/doc/index.rst deleted file mode 100644 index 1f51e20650c..00000000000 --- a/boards/arm/cyclonev_socdk/doc/index.rst +++ /dev/null @@ -1,359 +0,0 @@ -.. _cyclonev_socdk: - -Intel® Cyclone® V SoC Development Kit -##################################### - -Overview -******** - - -The Zephyr kernel is supported on the Intel® Cyclone® V SoC Development Kit, -using its Hard Processor System (HPS) CPU. - -.. figure:: img/cv_soc_board.jpg - :align: center - :alt: Intel's Cyclone® V SoC FPGA DevKit - - Intel®'s Cyclone® V SoC FPGA DevKit (Credit: Intel®) - -Hardware -******** - -Jumpers and DIP Switch settings -=============================== - -Recommended board settings are the same as the GSRD for Cyclone® V -SoC Development Board. - -There are two sets of switches on the back of the board. Of particular -importance is SW2. First, the board jumpers need to be configured as follows: - -* J5 : Open -* J6 : Short -* J7 : Short -* J9 : Open -* J13: Short -* J16: Open -* J26: Short pins 1-2 -* J27: Short pins 2-3 -* J28: Short pins 1-2 -* J29: Short pins 2-3 -* J30: Short pins 1-2 -* J31: Open - -Then, the board switches need to be configured as follows: - -* SW1: All OFF -* SW2: All OFF -* SW3: ON-OFF-ON-OFF-ON-ON -* SW4: OFF-OFF-ON-ON - -Other switches are user switches, their position is application-specific. -Refer to the development kit user manual for specifics about jumpers and switches - -Necessary Software -================== - -You will need the Intel® Quartus® Prime SDK in order to work with this device. The -`Intel® Quartus® Prime Lite Edition `_ -for Linux may be obtained without charge. - -For your convenience using the SDK tools (such as ``quartus_pgm``), -you should put the binaries provided by the SDK -in your path. Below is an example, adjust ALTERA_BASE to where you installed the -SDK: - -.. code-block:: console - - export QUARTUS_ROOTDIR=/opt/intelFPGA_lite/21.1 - export PATH=$PATH:$QUARTUS_ROOTDIR/quartus/bin:$QUARTUS_ROOTDIR/programmer/bin - -You may need to adjust your udev rules so that you can talk to the USB Blaster -II peripheral, which is the built-in JTAG interface for this device. - -The following works for Ubuntu: - -.. code-block:: console - - # For Altera USB-Blaster permissions. - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6010",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6810",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - -You can test connectivity with the SDK jtagconfig tool, you should see something -like: - -.. code-block:: console - - $ jtagconfig - 1) USB-BlasterII [1-5] - 4ba00477 SOCVHPS - 02D020DD 5ZSEBA6(.|ES)/5CSEMA6/.. - - -Golden Reference Design -======================= - -The Golden System Reference Design (GSRD) provides a set of essential hardware -and software system componets that can be used as a starting point for various -custom user designs. - -The Zephyr support for Cyclone® V SoC Development Kit is based on GSRD hardware. -Please refer to `Intel® Cyclone® V SoC GSRD `_ - -The hardware use for this release is based on Intel® Quartus® version 21.1 -the hardware files can be found `here `_ - -The directory "cv_soc_devkit_ghrd" contains the necessary files to create -a Intel® Quartus® project: - -* ghrd_top.v : top level Verilog (HDL) file for the GSRD -* soc_system.qpf : Quartus® Prime Project File -* soc_system.qsf : Quartus® Prime Settings File -* soc_system.qsys : Platform Designer file (contains the SoC system) -* soc_system.sopcinfo : SOPC Information file contains details about modules instantiated in the project, parameter names and values. -* soc_system_timing.sdc : Synopsys Desing Constraint FILE. -* output_files/soc_system.sof : FPGA configuration file. - - -Flash this FPGA file (.sof) using the ``quartus_pgm`` SDK tool with the FPGA -configuration file soc_system.sof: - -.. code-block:: console - - $ quartus_pgm -m jtag -o "p;path/to/soc_system.sof" - -This system is composed by the HPS, ARM Cortex-A9. In this example the UART, timer, -USB, I2C, DDR memory are exposed. Please double check the peripheral you intend to -use have its corresponding driver support. -You can find more information of the Cyclone® V SoC Devkit GSRD in RocketBoards -or consult the "Cyclone® V Hard Processor System Technical Reference Manual" - - -Console Output -============== - -16550 UART ----------- - -By default, the kernel is configured to send console output to the 16550 UART. -You can monitor this on your workstation by connecting to the top right mini USB -port on the board (J8/UART) (it will show up in /dev as a ttyUSB node), and then running -minicom/PuTTy with flow control disabled, 115200-8N1 settings. - - -Programming and Debugging -************************* - -Flashing -======== - -Flashing Kernel into the board ------------------------------- - -The usual ``flash`` target will work with the ``cyclonev_socdk`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -``Important!!!`` : Before flashing the board a ``preloader`` is required, -you can download `cv_soc_devkit_ghrd.tar.gz `_, -extract the file and copy ``cv_soc_devkit_ghrd/software/preloader/uboot-socfpga/spl/u-boot-spl`` -to ``boards/arm/cyclonev_socdk/support/`` - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cyclonev_socdk - :goals: flash - -Refer to :ref:`build_an_application` and :ref:`application_run` for -more details. - -This provisions the Zephyr kernel and the CPU configuration onto the board, -using the customized OpenOCD runner script :zephyr_file:`scripts/west_commands/runners/intel_cyclonev.py` -After it completes the kernel will immediately boot using the GSRD preloader. -Notice that there a lot of helper files to ``flash`` the application with -OpenOCD and GDB Debbuger (Zephyr SDK must be installed in your machine). -This files should be located in :zephyr_file:`boards/arm/cyclonev_socdk/support/` including: - -* blaster_6810.hex : USB-BlasterII firmware -* tmp_preloader_dl_cmd.txt : GDB helper file to load the preloader -* tmp_appli_dl_cmd.gdb : GDB helper file to load the zephyr.elf file -* tmp_appli_debug_cmd.gdb : GDB helper file to load the zephyr.elf file while debugging -* openocd.cfg : sources configuration files for OpenOCD -* download_all.gdb : GDB helper file to load the preloader -* u-boot-spl : Cyclone® V SoC DevKit GSRD preloader (copied from GSRD: cv_soc_devkit_ghrd.tar.gz) - -The following image shows the expected output (UART) after executing "west flash" using -the "hello world" sample design: - -.. figure:: img/cyclonev_westflash.jpg - :align: center - :alt: UART output after "west flash" example - - UART output after "west flash" example (Credit: Intel®) - -Debugging -========= - -The Zephyr SDK includes a GDB server which can be used to debug a Cyclone® V -SoC Development Kit board. -You can either debug a running image that was flashed onto the device in User -Flash Memory (UFM), or load an image over the JTAG using GDB. - -Debugging With Flashed Image ----------------------------- - -You can debug an application in the usual way. Here is an example. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cyclonev_socdk - :goals: debug - -You will see output similar to the following: - -.. code-block:: console - - -- west debug: rebuilding - ninja: no work to do. - -- west debug: using runner intel_cyclonev - -- runners.intel_cyclonev: OpenOCD GDB server running on port 3333; no thread info available - Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) - Licensed under GNU GPL v2 - For bug reports, read http://openocd.org/doc/doxygen/bugs.html - Info : only one transport option; autoselect 'jtag' - cycv_dbginit - Info : Listening on port 6666 for tcl connections - Info : Listening on port 4444 for telnet connections - Info : Altera USB-Blaster II (uninitialized) found - Info : Loading firmware... - Info : Waiting for reenumerate... - Info : Waiting for reenumerate... - Info : Altera USB-Blaster II found (Firm. rev. = 1.39) - Info : This adapter doesn't support configurable speed - Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) - Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) - Info : DAP transaction stalled (WAIT) - slowing down - Info : DAP transaction stalled (WAIT) - slowing down - Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints - Info : starting gdb server for fpgasoc.cpu.0 on 3333 - Info : Listening on port 3333 for gdb connections - Info : accepting 'gdb' connection on tcp/3333 - Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 - Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT - target halted in ARM state due to debug-request, current mode: Supervisor - cpsr: 0x600001d3 pc: 0x00002fa4 - MMU: disabled, D-Cache: disabled, I-Cache: enabled - warning: No executable has been specified and target does not support - determining executable automatically. Try using the "file" command. - 0x00002fa4 in ?? () - Restoring section .text (0xffff0000 to 0xffff6f84) - Info : DAP transaction stalled (WAIT) - slowing down - Warn : keep_alive() was not invoked in the 1000 ms timelimit. GDB alive packet not sent! (1469 ms). Workaround: increase "set remotetimeout" in GDB - Restoring section .rodata (0xffff6f84 to 0xffff8af9) - Restoring section .data (0xffff8b00 to 0xffff99d4) - Info : DAP transaction stalled (WAIT) - slowing down - Hardware assisted breakpoint 1 at 0xffff147e - Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 - fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 - - Temporary breakpoint 1, 0xffff147e in spl_boot_device () - [Inferior 1 (Remote target) detached] - Info : dropped 'gdb' connection - shutdown command invoked - Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) - Licensed under GNU GPL v2 - For bug reports, read http://openocd.org/doc/doxygen/bugs.html - Info : only one transport option; autoselect 'jtag' - cycv_dbginit - Info : Listening on port 6666 for tcl connections - Info : Listening on port 4444 for telnet connections - Info : Altera USB-Blaster II found (Firm. rev. = 1.39) - Info : This adapter doesn't support configurable speed - Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) - Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) - Info : DAP transaction stalled (WAIT) - slowing down - Info : DAP transaction stalled (WAIT) - slowing down - Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints - Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 - Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT - Info : starting gdb server for fpgasoc.cpu.0 on 3333 - Info : Listening on port 3333 for gdb connections - Info : accepting 'gdb' connection on tcp/3333 - warning: No executable has been specified and target does not support - determining executable automatically. Try using the "file" command. - 0xffff147c in ?? () - warning: /home/demo/zephyrproject/zephyr/boards/arm/cvsxdevkit/support/tmp_appli_debug_cmd.gdb: No such file or directory - [Inferior 1 (Remote target) detached] - Info : dropped 'gdb' connection - shutdown command invoked - Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) - Licensed under GNU GPL v2 - For bug reports, read http://openocd.org/doc/doxygen/bugs.html - Info : only one transport option; autoselect 'jtag' - cycv_dbginit - Info : Listening on port 6666 for tcl connections - Info : Listening on port 4444 for telnet connections - Info : Altera USB-Blaster II found (Firm. rev. = 1.39) - Info : This adapter doesn't support configurable speed - Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) - Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) - Info : DAP transaction stalled (WAIT) - slowing down - Info : DAP transaction stalled (WAIT) - slowing down - Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints - Reading symbols from /home/demo/zephyrproject/zephyr/build/zephyr/zephyr.elf... - Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 - Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT - Info : starting gdb server for fpgasoc.cpu.0 on 3333 - Info : Listening on port 3333 for gdb connections - Remote debugging using :3333 - Info : accepting 'gdb' connection on tcp/3333 - main () at /home/demo/zephyrproject/zephyr/samples/hello_world/src/main.c:11 - 11 printk("Hello World! %s\n", CONFIG_BOARD); - (gdb) - - -Try other examples -================== -There are varios examples that can be downloaded to the Cyclone® V SoC FPGA -Development Kit Board. Try to ``blink`` an LED from the HPS side of the chip: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: cyclonev_socdk - :goals: flash - -.. figure:: img/cyclonev_blinky.jpg - :align: center - :alt: HPS LED0 blinking example - - HPS LED0 blinking example (Credit: Intel®) - -Try writing characters to the LCD display connected to the i2c bus: - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/lcd_cyclonev_socdk - :board: cyclonev_socdk - :goals: flash - - -References -********** - -* `Cyclone® V Hard Processor System Technical Reference Manual `_ -* `Cyclone® V SoC Development Kit and Intel® SoC FPGA Embedded Development Suite `_ -* `Cyclone® V SoC GSRD in RocketBoards.org `_ -* `Intel® FPGA Software Download Center `_ -* `Embedded Peripherals IP User Guide `_ -* `Quartus II Scripting Reference Manual `_ diff --git a/boards/arm/cyclonev_socdk/support/download_all.gdb b/boards/arm/cyclonev_socdk/support/download_all.gdb deleted file mode 100644 index a1c7a9a4760..00000000000 --- a/boards/arm/cyclonev_socdk/support/download_all.gdb +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Download preloader and .elf using GDB commands - -set confirm off -set pagination off - -#Download and Run preloader -source boards/arm/cyclonev_socdk/support/preloader_dl_cmd.txt - -#Stop watchdog timer -#permodrst Reg , reset watch dog timer -set $permodrst = (int *)0xffd05014 -set *$permodrst = (*$permodrst) | (1<<6) -set *$permodrst = (*$permodrst) & ~(1<<6) - -quit diff --git a/boards/arm/cyclonev_socdk/support/preloader_dl_cmd.txt b/boards/arm/cyclonev_socdk/support/preloader_dl_cmd.txt deleted file mode 100644 index 3a10f686902..00000000000 --- a/boards/arm/cyclonev_socdk/support/preloader_dl_cmd.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Helper file to download the GSRD preloader to the board before the application - -restore boards/arm/cyclonev_socdk/support/u-boot-spl -symbol-file -readnow boards/arm/cyclonev_socdk/support/u-boot-spl -thbreak spl_boot_device -jump _start diff --git a/boards/arm/da14695_dk_usb/Kconfig b/boards/arm/da14695_dk_usb/Kconfig deleted file mode 100644 index 38ccd826507..00000000000 --- a/boards/arm/da14695_dk_usb/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# DA14695 Development Kit USB board configuration - -# Copyright (c) 2023 Renesas Electronics Corporation and/or its affiliates -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/da14695_dk_usb/Kconfig.board b/boards/arm/da14695_dk_usb/Kconfig.board deleted file mode 100644 index 67dbe731ffa..00000000000 --- a/boards/arm/da14695_dk_usb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# DA14695 Development Kit USB board configuration - -# Copyright (c) 2023 Renesas Electronics Corporation and/or its affiliates -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DA14695_DK_USB - bool "DA14695 Development Kit USB board" - depends on SOC_SERIES_DA1469X diff --git a/boards/arm/da14695_dk_usb/Kconfig.defconfig b/boards/arm/da14695_dk_usb/Kconfig.defconfig deleted file mode 100644 index 8208a705bd8..00000000000 --- a/boards/arm/da14695_dk_usb/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# DA14695 Development Kit USB board configuration - -# Copyright (c) 2023 Renesas Electronics Corporation and/or its affiliates -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DA14695_DK_USB - -config BOARD - default "da14695_dk_usb" - -endif # BOARD_DA14695_DK_USB diff --git a/boards/arm/da1469x_dk_pro/Kconfig b/boards/arm/da1469x_dk_pro/Kconfig deleted file mode 100644 index 0bca6654e15..00000000000 --- a/boards/arm/da1469x_dk_pro/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# DA1469x series Development Kit Pro board configuration - -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/da1469x_dk_pro/Kconfig.board b/boards/arm/da1469x_dk_pro/Kconfig.board deleted file mode 100644 index 0c7f9e23b2f..00000000000 --- a/boards/arm/da1469x_dk_pro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# DA1469x series Development Kit Pro board configuration - -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DA1469X_DK_PRO - bool "DA1469x series Development Kit Pro board" - depends on SOC_SERIES_DA1469X diff --git a/boards/arm/da1469x_dk_pro/Kconfig.defconfig b/boards/arm/da1469x_dk_pro/Kconfig.defconfig deleted file mode 100644 index b0a50f80d54..00000000000 --- a/boards/arm/da1469x_dk_pro/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# DA1469x series Development Kit Pro board configuration - -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DA1469X_DK_PRO - -config BOARD - default "da1469x_dk_pro" - -endif # BOARD_DA1469X_DK_PRO diff --git a/boards/arm/da1469x_dk_pro/da1469x_dk_pro_defconfig b/boards/arm/da1469x_dk_pro/da1469x_dk_pro_defconfig deleted file mode 100644 index c0f0e461d2b..00000000000 --- a/boards/arm/da1469x_dk_pro/da1469x_dk_pro_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_DA1469X=y -CONFIG_SOC_DA14699=y -CONFIG_BOARD_DA1469X_DK_PRO=y - -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_GPIO=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_BUILD_OUTPUT_HEX=n - -CONFIG_I2C=y -CONFIG_I2C_CALLBACK=y diff --git a/boards/arm/decawave_dwm1001_dev/Kconfig.board b/boards/arm/decawave_dwm1001_dev/Kconfig.board deleted file mode 100644 index ebfd2c581bc..00000000000 --- a/boards/arm/decawave_dwm1001_dev/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# DecaWave DWM1001 board configuration - -# Copyright (c) 2019 Stéphane D'Alu -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DECAWAVE_DWM1001_DEV - bool "Decawave DWM1001-DEV" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/decawave_dwm1001_dev/Kconfig.defconfig b/boards/arm/decawave_dwm1001_dev/Kconfig.defconfig deleted file mode 100644 index c64fe40b645..00000000000 --- a/boards/arm/decawave_dwm1001_dev/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# DecaWave DWM1001 board configuration - -# Copyright (c) 2019 Stéphane D'Alu -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DECAWAVE_DWM1001_DEV - -config BOARD - default "decawave_dwm1001_dev" - -config BT_CTLR - default BT - -config I2C - default SENSOR - -config SPI - default y - depends on IEEE802154 - -endif # BOARD_DECAWAVE_DWM1001_DEV diff --git a/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig b/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig deleted file mode 100644 index b77b8937a77..00000000000 --- a/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_DECAWAVE_DWM1001_DEV=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable RTT -CONFIG_USE_SEGGER_RTT=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_RTT_CONSOLE=y diff --git a/boards/arm/degu_evk/Kconfig.board b/boards/arm/degu_evk/Kconfig.board deleted file mode 100644 index 99c579690e1..00000000000 --- a/boards/arm/degu_evk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Degu Evaluation Kit configuration - -# Copyright (c) 2019 Atmark Techno, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DEGU_EVK - bool "DEGU_EVK" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/degu_evk/Kconfig.defconfig b/boards/arm/degu_evk/Kconfig.defconfig deleted file mode 100644 index cad67382531..00000000000 --- a/boards/arm/degu_evk/Kconfig.defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# Degu Evaluation Kit configuration - -# Copyright (c) 2019 Atmark Techno, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DEGU_EVK - -config BOARD - default "degu_evk" - -if USB_DEVICE_STACK - -config USB_DEVICE_PRODUCT - default "Degu Evaluation Kit" - -config UART_INTERRUPT_DRIVEN - default y - -config UART_LINE_CTRL - default y - -endif # USB_DEVICE_STACK - -if LOG - -# Logger cannot use itself to log -config USB_CDC_ACM_LOG_LEVEL - default 0 - -# Set USB log level to error only -config USB_DEVICE_LOG_LEVEL - default 1 - -endif # LOG - -endif # BOARD_DEGU_EVK diff --git a/boards/arm/degu_evk/degu_evk_defconfig b/boards/arm/degu_evk/degu_evk_defconfig deleted file mode 100644 index 6123f6c756e..00000000000 --- a/boards/arm/degu_evk/degu_evk_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_DEGU_EVK=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable USB (for CDC ACM console) -CONFIG_USB_DEVICE_STACK=y - -# additional board options -CONFIG_GPIO=y - -# required to enable 3V3 power rail and Vin1 monitor -CONFIG_REGULATOR=y diff --git a/boards/arm/disco_l475_iot1/Kconfig.board b/boards/arm/disco_l475_iot1/Kconfig.board deleted file mode 100644 index 98e8d291782..00000000000 --- a/boards/arm/disco_l475_iot1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Discovery IoT L475 board configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DISCO_L475_IOT1 - bool "Discovery IoT L475 Development Board" - depends on SOC_STM32L475XX diff --git a/boards/arm/disco_l475_iot1/Kconfig.defconfig b/boards/arm/disco_l475_iot1/Kconfig.defconfig deleted file mode 100644 index 3a53147decf..00000000000 --- a/boards/arm/disco_l475_iot1/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# Discovery IoT L475 board configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DISCO_L475_IOT1 - -config BOARD - default "disco_l475_iot1" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -choice LIS3MDL_TRIGGER_MODE - default LIS3MDL_TRIGGER_NONE -endchoice - -choice HTS221_TRIGGER_MODE - default HTS221_TRIGGER_NONE -endchoice - -choice LSM6DSL_TRIGGER_MODE - default LSM6DSL_TRIGGER_GLOBAL_THREAD - depends on LSM6DSL -endchoice - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -config BT_BLUENRG_ACI - default y -# Disable Flow control -config BT_HCI_ACL_FLOW_CONTROL - default n -config BT_HCI_VS_EXT - default n - -endif # BT - -endif # BOARD_DISCO_L475_IOT1 diff --git a/boards/arm/disco_l475_iot1/doc/index.rst b/boards/arm/disco_l475_iot1/doc/index.rst deleted file mode 100644 index 906729fcf8e..00000000000 --- a/boards/arm/disco_l475_iot1/doc/index.rst +++ /dev/null @@ -1,248 +0,0 @@ -.. _disco_l475_iot1_board: - -ST Disco L475 IOT01 (B-L475E-IOT01A) -#################################### - -Overview -******** - -The B-L475E-IOT01A Discovery kit for IoT node allows users to develop -applications with direct connection to cloud servers. -The Discovery kit enables a wide diversity of applications by exploiting -low-power communication, multiway sensing and ARM |reg| Cortex |reg|-M4 core-based -STM32L4 Series features. - -This kit provides: - -- 64-Mbit Quad-SPI (Macronix) Flash memory -- Bluetooth |reg| V4.1 module (SPBTLE-RF) -- Sub-GHz (868 or 915 MHz) low-power-programmable RF module (SPSGRF-868 or SPSGRF-915) -- Wi-Fi |reg| module Inventek ISM43362-M3G-L44 (802.11 b/g/n compliant) -- Dynamic NFC tag based on M24SR with its printed NFC antenna -- 2 digital omni-directional microphones (MP34DT01) -- Capacitive digital sensor for relative humidity and temperature (HTS221) -- High-performance 3-axis magnetometer (LIS3MDL) -- 3D accelerometer and 3D gyroscope (LSM6DSL) -- 260-1260 hPa absolute digital output barometer (LPS22HB) -- Time-of-Flight and gesture-detection sensor (VL53L0X) -- 2 push-buttons (user and reset) -- USB OTG FS with Micro-AB connector -- Expansion connectors: - - Arduino |trade| Uno V3 - - PMOD -- Flexible power-supply options: - - ST LINK USB VBUS or external sources -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: - - mass storage, virtual COM port and debug port - - -.. image:: img/disco_l475_iot1.jpg - :align: center - :alt: Disco L475 IoT1 - -More information about the board can be found at the `Disco L475 IoT1 website`_. - -Hardware -******** - -The STM32L475VG SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 120 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC -- RTC with HW calendar, alarms and calibration -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer -- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 128 KB of SRAM including 32 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators -- 18x communication interfaces - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (4x SPIs with the Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L475VG can be found here: - - `STM32L475VG on www.st.com`_ - - `STM32L475 reference manual`_ - -Supported Features -================== - -The Zephyr Disco L475 IoT board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig`` - - -Connections and IOs -=================== - -Disco L475 IoT Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- - -For detailed information about available pins please refer to `STM32 Disco L475 IoT1 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 (ST-Link Virtual Port Com) -- UART_4 TX/RX : PA0/PA1 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PB10/PB11 (Sensor I2C bus) -- I2C3 SCL/SDA : PC0/PC1 -- SPI1 NSS/SCK/MISO/MOSI : PA2/PA5/PA6/PA7 (Arduino SPI) -- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (BT SPI bus) -- PWM_2_CH1 : PA15 -- USER_PB : PC13 -- LD2 : PA5 -- ADC12_IN5 : PA0 -- ADC123_IN3 : PC2 -- ADC123_IN4 : PC3 -- ADC12_IN13 : PC4 -- ADC12_IN14 : PC5 -- DAC1_OUT1 : PA4 - -System Clock ------------- - -Disco L475 IoT System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Disco L475 IoT board has 6 U(S)ARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``disco_l475_iot1`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Disco L475 IoT board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Disco L475 IoT ------------------------------------------ - -Here is an example for the :ref:`hello_world` application. - -Connect the Disco L475 IoT to your host computer using the USB port, then -run a serial host program to connect with your Nucleo board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: disco_l475_iot1 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: disco_l475_iot1 - :maybe-skip-config: - :goals: debug - -.. _Disco L475 IoT1 website: - https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-discovery-kits/b-l475e-iot01a.html - -.. _STM32 Disco L475 IoT1 board User Manual: - https://www.st.com/resource/en/user_manual/dm00347848.pdf - -.. _STM32L475VG on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l475vg.html - -.. _STM32L475 reference manual: - https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/dragino_lsn50/Kconfig.board b/boards/arm/dragino_lsn50/Kconfig.board deleted file mode 100644 index ba1b1277140..00000000000 --- a/boards/arm/dragino_lsn50/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Dragino LSN50 LoRA Sensor Node board configuration - -# Copyright (c) 2018 Endre Karlson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DRAGINO_LSN50 - bool "Dragino LSN50 Sensor Node" - depends on SOC_STM32L072XX diff --git a/boards/arm/dragino_lsn50/Kconfig.defconfig b/boards/arm/dragino_lsn50/Kconfig.defconfig deleted file mode 100644 index 05f7b5fd549..00000000000 --- a/boards/arm/dragino_lsn50/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Dragino LSN50 LoRA Sensor Node board configuration - -# Copyright (c) 2018 Endre Karlson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DRAGINO_LSN50 - -config BOARD - default "dragino_lsn50" - -endif # BOARD_DRAGINO_LSN50 diff --git a/boards/arm/dragino_lsn50/doc/index.rst b/boards/arm/dragino_lsn50/doc/index.rst deleted file mode 100644 index 732e0ec1394..00000000000 --- a/boards/arm/dragino_lsn50/doc/index.rst +++ /dev/null @@ -1,194 +0,0 @@ -.. _dragino_lsn50_board: - -Dragino LSN50 LoRA Sensor Node -############################## - -Overview -******** - -The Dragino LSN50 LoRA Sensor Node for IoT allows users to develop -applications with LoraWAN connectivity via the HopeRF / SX1276/SX1278. -Dragino LSN50 enables a wide diversity of applications by exploiting -low-power communication, ARM |reg| Cortex |reg|-M0 core-based -STM32L0 Series features. - -This kit provides: - -- STM32L072CZ MCU -- SX1276/SX1278 LoRa Transceiver -- Expansion connectors: - - - PMOD -- Li/SOCI2 Unchargable Battery -- GPIOs exposed via screw terminals on the carrier board -- Housing - -.. image:: img/dragino_lsn50.jpg - :align: center - :alt: Dragino LSN50 - -More information about the board can be found at the `Dragino LSN50 website`_. - -Hardware -******** - -The STM32L072CZ SoC provides the following hardware IPs: - -- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz -- Clock Sources: - - - 1 to 32 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 37 kHz RC ( |plusminus| 5%) - - Internal multispeed low-power 65 kHz to 4.2 MHz RC -- RTC with HW calendar, alarms and calibration -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 11x timers: - - - 2x 16-bit with up to 4 channels - - 2x 16-bit with up to 2 channels - - 1x 16-bit ultra-low-power timer - - 1x SysTick - - 1x RTC - - 2x 16-bit basic for DAC - - 2x watchdogs (independent/window) -- Up to 84 fast I/Os, most 5 V-tolerant. -- Memories - - - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 20 KB of SRAM - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 1.14 MSPS - - 2x 12-bit DAC - - 2x ultra-low-power comparators -- 11x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 6x SPIs (4x SPIs with the Quad SPI) -- 7-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L072CZ can be found here: - - - `STM32L072CZ on www.st.com`_ - - `STM32L0x2 reference manual`_ - -Supported Features -================== - -The Zephyr Dragino LSN50 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/dragino_lsn50/dragino_lsn50_defconfig`` - - -Connections and IOs -=================== - -Dragino LSN50 Board has GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- - -For detailed information about available pins please refer to `Dragino LSN50 website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 - -System Clock ------------- - -Dragino LSN50 System Clock is at 32MHz, - -Serial Port ------------ - -Dragino LSN50 board has 2 U(S)ARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``dragino_lsn50`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Dragino LSN50 board requires an external debugger. - -Flashing an application to Dragino LSN50 ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Connect the Dragino LSN50 to a STLinkV2 to your host computer using the USB port, then -run a serial host program to connect with your board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: dragino_lsn50 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: dragino_lsn50 - :maybe-skip-config: - :goals: debug - -.. _Dragino LSN50 website: - https://www.dragino.com/products/lora-lorawan-end-node/item/128-lsn50.html - -.. _STM32L072CZ on www.st.com: - https://www.st.com/en/microcontrollers/stm32l072cz.html - -.. _STM32L0x2 reference manual: - https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/dragino_lsn50/dragino_lsn50_defconfig b/boards/arm/dragino_lsn50/dragino_lsn50_defconfig deleted file mode 100644 index 7b6c7e6409d..00000000000 --- a/boards/arm/dragino_lsn50/dragino_lsn50_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L072XX=y -CONFIG_BOARD_DRAGINO_LSN50=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/dragino_nbsn95/Kconfig.board b/boards/arm/dragino_nbsn95/Kconfig.board deleted file mode 100644 index e308ae65287..00000000000 --- a/boards/arm/dragino_nbsn95/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Dragino NBSN95 NB-IoT Sensor Node board configuration - -# Copyright (c) 2021 Next Big Thing AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DRAGINO_NBSN95 - bool "Dragino NBSN95 Sensor Node" - depends on SOC_STM32L072XX diff --git a/boards/arm/dragino_nbsn95/Kconfig.defconfig b/boards/arm/dragino_nbsn95/Kconfig.defconfig deleted file mode 100644 index 0dbadb732d0..00000000000 --- a/boards/arm/dragino_nbsn95/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Dragino NBSN95 NB-IoT Sensor Node board configuration - -# Copyright (c) 2021 Next Big Thing AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DRAGINO_NBSN95 - -config BOARD - default "dragino_nbsn95" - -endif # BOARD_DRAGINO_NBSN95 diff --git a/boards/arm/dragino_nbsn95/doc/index.rst b/boards/arm/dragino_nbsn95/doc/index.rst deleted file mode 100644 index ca0b3d8cc1d..00000000000 --- a/boards/arm/dragino_nbsn95/doc/index.rst +++ /dev/null @@ -1,193 +0,0 @@ -.. _dragino_nbsn95_board: - -Dragino NBSN95 NB-IoT Sensor Node -################################# - -Overview -******** - -The Dragino NBSN95 NB-IoT Sensor Node for IoT allows users to develop -applications with NB-IoT connectivity via the Quectel BC95-G. -Dragino NBSN95 enables a wide diversity of applications by exploiting -low-power communication, ARM |reg| Cortex |reg|-M0 core-based -STM32L0 Series features. - -This kit provides: - -- STM32L072CZ MCU -- Quectel BC95-G NB-IoT -- Expansion connectors: - - PMOD -- Li/SOCI2 Unchargable Battery -- GPIOs exposed via screw terminals on the carrier board -- Housing - -.. image:: img/dragino_nbsn95.jpg - :align: center - :alt: Dragino NBSN95 - -More information about the board can be found at the `Dragino NBSN95 website`_. - -Hardware -******** - -The STM32L072CZ SoC provides the following hardware IPs: - -- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz -- Clock Sources: - - - 1 to 32 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 37 kHz RC ( |plusminus| 5%) - - Internal multispeed low-power 65 kHz to 4.2 MHz RC -- RTC with HW calendar, alarms and calibration -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 11x timers: - - - 2x 16-bit with up to 4 channels - - 2x 16-bit with up to 2 channels - - 1x 16-bit ultra-low-power timer - - 1x SysTick - - 1x RTC - - 2x 16-bit basic for DAC - - 2x watchdogs (independent/window) -- Up to 84 fast I/Os, most 5 V-tolerant. -- Memories - - - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 20 KB of SRAM - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 1.14 MSPS - - 2x 12-bit DAC - - 2x ultra-low-power comparators -- 11x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 6x SPIs (4x SPIs with the Quad SPI) -- 7-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L072CZ can be found here: - - - `STM32L072CZ on www.st.com`_ - - `STM32L0x2 reference manual`_ - -Supported Features -================== - -The Zephyr Dragino NBSN95 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig`` - - -Connections and IOs -=================== - -Dragino NBSN95 Board has GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- - -For detailed information about available pins please refer to `Dragino NBSN95 website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 - -System Clock ------------- - -Dragino NBSN95 System Clock is at 32MHz, - -Serial Port ------------ - -Dragino NBSN95 board has 2 U(S)ARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``dragino_nbsn95`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Dragino NBSN95 board requires an external debugger. - -Flashing an application to Dragino NBSN95 ------------------------------------------ - -Here is an example for the :ref:`hello_world` application. - -Connect the Dragino NBSN95 to a STLinkV2 to your host computer using the USB port, then -run a serial host program to connect with your board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: dragino_nbsn95 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! dragino_nbsn95 - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: dragino_nbsn95 - :maybe-skip-config: - :goals: debug - -.. _Dragino NBSN95 website: - https://www.dragino.com/products/nb-iot/item/163-nbsn95.html - -.. _STM32L072CZ on www.st.com: - https://www.st.com/en/microcontrollers/stm32l072cz.html - -.. _STM32L0x2 reference manual: - https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig b/boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig deleted file mode 100644 index 20b5025cc57..00000000000 --- a/boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L072XX=y -CONFIG_BOARD_DRAGINO_NBSN95=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.board b/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.board deleted file mode 100644 index 5c69a63bb09..00000000000 --- a/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# EBYTE-TBB board configuration - -# Copyright (c) 2021 Michal Morsisko -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EBYTE_E73_TBB_NRF52832 - bool "EBYTE E73-TBB NRF52832" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.defconfig b/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.defconfig deleted file mode 100644 index 3638e0b0b4b..00000000000 --- a/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# EBYTE E73-TBB NRF52832 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# Copyright (c) 2021 Michal Morsisko -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EBYTE_E73_TBB_NRF52832 - -config BOARD - default "ebyte_e73_tbb_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_EBYTE_E73_TBB_NRF52832 diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/doc/index.rst b/boards/arm/ebyte_e73_tbb_nrf52832/doc/index.rst deleted file mode 100644 index 5b0f88f88a6..00000000000 --- a/boards/arm/ebyte_e73_tbb_nrf52832/doc/index.rst +++ /dev/null @@ -1,222 +0,0 @@ -.. _ebyte_e73_tbb_nrf52832: - -EBYTE E73-TBB -############# - -Overview -******** - -The EBYTE E73-TBB hardware provides -support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/ebyte_e73_tbb_nrf52832.jpg - :align: center - :alt: EBYTE E73-TBB - - EBYTE E73-TBB (Credit: EBYTE) - -More information about the board can be found at the -`E73-TBB website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -E73-TBB has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. Additionally the board features CH340 USB-UART converter. -It is possible to connect external BT antenna using U.FL socket -and solder NFC antenna using NFC_ANT connector. - -Supported Features -================== - -The ebyte_e73_tbb_nrf52832 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features are not supported by the Zephyr kernel. -See `E73-TBB website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF52832 hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.17 -* LED1 (red) = P0.18 - -Push buttons ------------- - -* BUTTON0 = SW1 = P0.14 -* BUTTON1 = SW2 = P0.13 - -External Connectors -------------------- - -P1 Header - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | GND | -+-------+--------------+ -| 2 | 3.3V | -+-------+--------------+ -| 3 | P0.04 | -+-------+--------------+ -| 4 | P0.03 | -+-------+--------------+ -| 5 | P0.02 | -+-------+--------------+ -| 6 | P0.31 | -+-------+--------------+ -| 7 | P0.30 | -+-------+--------------+ -| 8 | P0.29 | -+-------+--------------+ -| 9 | P0.28 | -+-------+--------------+ -| 10 | P0.27 | -+-------+--------------+ -| 11 | P0.26 | -+-------+--------------+ -| 12 | P0.25 | -+-------+--------------+ - -P2 Header - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | P0.24 | -+-------+--------------+ -| 2 | P0.23 | -+-------+--------------+ -| 3 | P0.22 | -+-------+--------------+ -| 4 | SWDIO | -+-------+--------------+ -| 5 | SWDCLK | -+-------+--------------+ -| 6 | P0.21/RST | -+-------+--------------+ -| 7 | P0.20 | -+-------+--------------+ -| 8 | P0.19 | -+-------+--------------+ -| 9 | P0.16 | -+-------+--------------+ -| 10 | P0.15 | -+-------+--------------+ -| 11 | P0.12 | -+-------+--------------+ -| 12 | P0.11 | -+-------+--------------+ - -NFC_ANT - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | P0.10 | -+-------+--------------+ -| 2 | P0.09 | -+-------+--------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. -To flash the board connect pins: SWDIO, SWDCLK, RST, GND from E73-TBB -to corresponding pins on your J-Link device, then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: ebyte_e73_tbb_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic chips with a -Segger IC. - - -Testing the LEDs and buttons in the E73-TBB -******************************************* - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - :zephyr:code-sample:`blinky` - :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.dts`. - -References -********** - -.. target-notes:: - -.. _E73-TBB website: https://www.ebyte.com/en/product-view-news.html?id=889 -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/efm32gg_sltb009a/Kconfig.board b/boards/arm/efm32gg_sltb009a/Kconfig.board deleted file mode 100644 index ae0968a1993..00000000000 --- a/boards/arm/efm32gg_sltb009a/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32GG SLTB009A board configuration -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32GG_SLTB009A - bool "SiLabs EFM32GG-SLTB009A (Giant Gecko 12)" - depends on SOC_SERIES_EFM32GG12B - select SOC_PART_NUMBER_EFM32GG12B810F1024GM64 diff --git a/boards/arm/efm32gg_sltb009a/Kconfig.defconfig b/boards/arm/efm32gg_sltb009a/Kconfig.defconfig deleted file mode 100644 index 055b4925e78..00000000000 --- a/boards/arm/efm32gg_sltb009a/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# EFM32GG SLTB009A default board configuration -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32GG_SLTB009A - -config BOARD - string - default "efm32gg_sltb009a" - -config CMU_HFXO_FREQ - default 50000000 - -config CMU_HFRCO_FREQ - default 72000000 - -config CMU_LFXO_FREQ - default 32768 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -endif # BOARD_EFM32GG_SLTB009A diff --git a/boards/arm/efm32gg_sltb009a/doc/index.rst b/boards/arm/efm32gg_sltb009a/doc/index.rst deleted file mode 100644 index a3f54c65025..00000000000 --- a/boards/arm/efm32gg_sltb009a/doc/index.rst +++ /dev/null @@ -1,167 +0,0 @@ -.. _efm32gg_sltb009a: - -EFM32GG12 Thunderboard Kit -########################## - -Overview -******** - -The EFM32GG12 Thunderboard Kit (SLTB009A) is an evaluation platform for the EFM32GG12 GiantGecko Microcontroller, -featuring an ARM Cortex-M4 with FPU, 1024kB flash, and 192kB RAM. - -.. figure:: efm32gg12-thunderboard-kit.jpg - :align: center - :alt: SLTB009A - - SLTB009A (Credit: Silicon Labs) - -Hardware -******** - -- PDM stereo microphones -- USB connectivity -- On-board Segger J-Link USB debugger -- 2 user buttons and 2 LEDs -- USB C connector - -For more information about the WGM160P and SLTB009A board: - -- `SLTB009A Website`_ -- `SLTB009A User Guide`_ -- `EFM32GG12 Datasheet`_ -- `EFM32GG12 Reference Manual`_ - -Supported Features -================== - -The efm32gg_sltb009a board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32gg_sltb009a/efm32gg_sltb009a_defconfig`` - - -Connections and IOs -=================== - -The EFM32GG12 MCU has six GPIO controllers (PORTA to PORTF), all of which are -currently enabled for the SLTB009A board. - -In the following table, the column **Name** contains pin names. For example, PE1 -means pin number 1 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PE12 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PA13 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PD5 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PD8 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | -+-------+-------------+-------------------------------------+ -| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | -+-------+-------------+-------------------------------------+ -| PC0 | I2C_SDA | SENSOR_I2C_SDA I2C0_SDA #1 | -+-------+-------------+-------------------------------------+ -| PC1 | I2C_SCL | SENSOR_I2C_SCL I2C0_SCL #1 | -+-------+-------------+-------------------------------------+ -| PC4 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | -+-------+-------------+-------------------------------------+ -| PC5 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32GG12 MCU is configured to work at 72 MHz. - -Serial Port -=========== - -The EFM32GG12 SoC has five USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The SLTB009A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to SLTB009A --------------------------------------- - -Connect the SLTB009A to your host computer using the USB port. - -Here is an example to build and flash the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32gg_stb009a - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efm32gg_sltb009a - -.. _SLTB009A Website: - https://www.silabs.com/development-tools/thunderboard/thunderboard-gg12-kit - -.. _SLTB009A User Guide: - https://www.silabs.com/documents/public/user-guides/ug371-sltb009a-user-guide.pdf - -.. _EFM32GG12 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32gg12-datasheet.pdf - -.. _EFM32GG12 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32gg12-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32gg_slwstk6121a/Kconfig.board b/boards/arm/efm32gg_slwstk6121a/Kconfig.board deleted file mode 100644 index e15929d5a0a..00000000000 --- a/boards/arm/efm32gg_slwstk6121a/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# EFM32GG SLWSTK6121A board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# Copyright (c) 2020 Thorvald Natvig -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32GG_SLWSTK6121A - bool "SiLabs EFM32GG-SLWSTK6121A (WGM160P)" - depends on SOC_SERIES_EFM32GG11B - select SOC_PART_NUMBER_EFM32GG11B820F2048GM64 diff --git a/boards/arm/efm32gg_slwstk6121a/Kconfig.defconfig b/boards/arm/efm32gg_slwstk6121a/Kconfig.defconfig deleted file mode 100644 index 28139ff4b1a..00000000000 --- a/boards/arm/efm32gg_slwstk6121a/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# EFM32GG SLWSTK6121A default board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# Copyright (c) 2020 Thorvald Natvig -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32GG_SLWSTK6121A - -config BOARD - string - default "efm32gg_slwstk6121a" - -config CMU_HFXO_FREQ - default 50000000 - -config CMU_HFRCO_FREQ - default 72000000 - -config CMU_LFXO_FREQ - default 32768 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_EFM32GG_SLWSTK6121A diff --git a/boards/arm/efm32gg_slwstk6121a/doc/index.rst b/boards/arm/efm32gg_slwstk6121a/doc/index.rst deleted file mode 100644 index be1f25efdaa..00000000000 --- a/boards/arm/efm32gg_slwstk6121a/doc/index.rst +++ /dev/null @@ -1,187 +0,0 @@ -.. _efm32gg_slwstk6121a: - -WGM160P Starter Kit -################### - -Overview -******** - -The WGM160P Starter Kit SLWSTK6121A comes with the BRD4321A radio board. -This radio boards contains a WGM160P module, which combines the WF200 Wi-Fi -transceiver with an EFM32GG11 microcontroller. - -.. figure:: wgm160p-starter-kit.jpg - :align: center - :alt: SLWSTK6121A - - SLWSTK6121A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel color Memory-LCD -- 2 user buttons and 2 LEDs -- Si7021 Humidity and Temperature Sensor -- On-board Segger J-Link USB and Ethernet debugger -- 10/100Base-TX ethernet PHY and RJ-45 jack (on included expansion board) -- MicroSD card slot -- USB Micro-AB connector - -For more information about the WGM160P and SLWSTK6121A board: - -- `WGM160P Website`_ -- `WGM160P Datasheet`_ -- `SLWSTK6121A Website`_ -- `SLWSTK6121A User Guide`_ -- `EFM32GG11 Datasheet`_ -- `EFM32GG11 Reference Manual`_ -- `WF200 Datasheet`_ - -Supported Features -================== - -The efm32gg_slwstk6121a board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig`` - -Other hardware features, including the WF200 WiFi transceiver, are -currently not supported by the port. - -Connections and IOs -=================== - -The WGM160P's EFM32GG11 SoC has six GPIO controllers (PORTA to PORTF), all of which are -currently enabled for the SLWSTK6121A board. - -In the following table, the column **Name** contains pin names. For example, PE1 -means pin number 1 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PA4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PA5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PD6 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PD8 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | -+-------+-------------+-------------------------------------+ -| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | -+-------+-------------+-------------------------------------+ -| PB11 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | -+-------+-------------+-------------------------------------+ -| PB12 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32GG11 SoC has four USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The SLWSTK6121A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to SLWSTK6121A --------------------------------------- - -Connect the SLWSTK6121A to your host computer using the USB port. - -Here is an example to build and flash the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32gg_slwstk6121a - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efm32gg_slwstk6121a - -.. _WGM160P Website: - https://www.silabs.com/wireless/wi-fi/wfm160-series-1-modules - -.. _WGM160P Datasheet: - https://www.silabs.com/documents/public/data-sheets/wgm160p-datasheet.pdf - -.. _SLWSTK6121A Website: - https://www.silabs.com/development-tools/wireless/wi-fi/wgm160p-wifi-module-starter-kit - -.. _SLWSTK6121A User Guide: - https://www.silabs.com/documents/public/user-guides/ug351-brd4321a-user-guide.pdf - -.. _EFM32GG11 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf - -.. _EFM32GG11 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf - -.. _WF200 Datasheet: - https://www.silabs.com/documents/public/data-sheets/wf200-datasheet.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32gg_stk3701a/Kconfig.board b/boards/arm/efm32gg_stk3701a/Kconfig.board deleted file mode 100644 index cbab0c8d3ff..00000000000 --- a/boards/arm/efm32gg_stk3701a/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFM32GG STK3701A board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32GG_STK3701A - bool "SiLabs EFM32GG-STK3701A (Giant Gecko 11)" - depends on SOC_SERIES_EFM32GG11B - select SOC_PART_NUMBER_EFM32GG11B820F2048GL192 diff --git a/boards/arm/efm32gg_stk3701a/Kconfig.defconfig b/boards/arm/efm32gg_stk3701a/Kconfig.defconfig deleted file mode 100644 index 620efea317a..00000000000 --- a/boards/arm/efm32gg_stk3701a/Kconfig.defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# EFM32GG STK3701A default board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32GG_STK3701A - -config BOARD - string - default "efm32gg_stk3701a" - -config CMU_HFXO_FREQ - default 50000000 - -config CMU_HFRCO_FREQ - default 72000000 - -config CMU_LFXO_FREQ - default 32768 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_EFM32GG_STK3701A diff --git a/boards/arm/efm32gg_stk3701a/doc/index.rst b/boards/arm/efm32gg_stk3701a/doc/index.rst deleted file mode 100644 index 50b3d9cd785..00000000000 --- a/boards/arm/efm32gg_stk3701a/doc/index.rst +++ /dev/null @@ -1,201 +0,0 @@ -.. _efm32gg_stk3701a: - -EFM32 Giant Gecko GG11 Starter Kit -################################## - -Overview -******** - -The EFM32 Giant Gecko Starter Kit EFM32GG-STK3701A contains an MCU from the -EFM32GG Series 1 family built on an ARM® Cortex®-M4F processor with excellent -low power capabilities. - -.. figure:: efm32gg_stk3701a.jpg - :align: center - :alt: EFM32GG-SLSTK3701A - - EFM32GG-SLSTK3701A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel color Memory-LCD -- 2 user buttons, 2 LEDs and a touch slider -- Relative humidity, magnetic Hall Effect and inductive-capacitive metal sensor -- USB interface for Host/Device/OTG -- 32 Mb Quad-SPI Flash memory -- SD card slot -- RJ-45 Ethernet jack -- 2 digital microphones -- On-board Segger J-Link USB debugger - -For more information about the EFM32GG11 SoC and EFM32GG-STK3701A board: - -- `EFM32GG Series 1 Website`_ -- `EFM32GG11 Datasheet`_ -- `EFM32GG11 Reference Manual`_ -- `EFM32GG-STK3701A Website`_ -- `EFM32GG-STK3701A User Guide`_ -- `EFM32GG-STK3701A Schematics`_ - -Supported Features -================== - -The efm32gg_stk3701a board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig`` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32GG11 SoC has nine GPIO controllers (PORTA to PORTI), all of which are -currently enabled for the EFM32GG-STK3701A board. - -In the following table, the column **Name** contains pin names. For example, PE1 -means pin number 1 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PH10 | GPIO | LED0 red | -+-------+-------------+-------------------------------------+ -| PH11 | GPIO | LED0 green | -+-------+-------------+-------------------------------------+ -| PH12 | GPIO | LED0 blue | -+-------+-------------+-------------------------------------+ -| PH13 | GPIO | LED1 red | -+-------+-------------+-------------------------------------+ -| PH14 | GPIO | LED1 green | -+-------+-------------+-------------------------------------+ -| PH15 | GPIO | LED1 blue | -+-------+-------------+-------------------------------------+ -| PC8 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PC9 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PE1 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PH4 | UART_TX | UART TX Console VCOM_TX US0_TX #4 | -+-------+-------------+-------------------------------------+ -| PH5 | UART_RX | UART RX Console VCOM_RX US0_RX #4 | -+-------+-------------+-------------------------------------+ -| PI4 | I2C_SDA | SENSOR_I2C_SDA I2C2_SDA #7 | -+-------+-------------+-------------------------------------+ -| PI5 | I2C_SCL | SENSOR_I2C_SCL I2C2_SCL #7 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32GG11 SoC has six USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART4 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32GG-STK3701A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a mass storage device and a - USB serial port. -- A serial flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to EFM32GG-STK3701A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32gg_stk3701a - :goals: build - -Connect the EFM32GG-STK3701A to your host computer using the USB port and you -should see a USB connection which exposes a mass storage device(STK3701A) and -a USB Serial Port. Copy the generated zephyr.bin to the STK3701A drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efm32gg_stk3701a - - -.. _EFM32GG-STK3701A Website: - https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-giant-gecko-gg11-starter-kit - -.. _EFM32GG-STK3701A User Guide: - https://www.silabs.com/documents/public/user-guides/ug287-stk3701.pdf - -.. _EFM32GG-STK3701A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD2204A-B00-schematic.pdf - -.. _EFM32GG Series 1 Website: - https://www.silabs.com/products/mcu/32-bit/efm32-giant-gecko-s1 - -.. _EFM32GG11 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf - -.. _EFM32GG11 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32hg_slstk3400a/Kconfig.board b/boards/arm/efm32hg_slstk3400a/Kconfig.board deleted file mode 100644 index eb3ca8af2cc..00000000000 --- a/boards/arm/efm32hg_slstk3400a/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFM32HG SLSTK3400A board - -# Copyright (c) 2018, Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32HG_SLSTK3400A - bool "SiLabs EFM32HG-SLSTK3400A (Happy Gecko)" - depends on SOC_SERIES_EFM32HG - select SOC_PART_NUMBER_EFM32HG322F64 diff --git a/boards/arm/efm32hg_slstk3400a/Kconfig.defconfig b/boards/arm/efm32hg_slstk3400a/Kconfig.defconfig deleted file mode 100644 index 08b75e0857f..00000000000 --- a/boards/arm/efm32hg_slstk3400a/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# EFM32HG SLSTK3400A board - -# Copyright (c) 2018, Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32HG_SLSTK3400A - -config BOARD - default "efm32hg_slstk3400a" - -config CMU_HFXO_FREQ - default 24000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFM32HG_SLSTK3400A diff --git a/boards/arm/efm32hg_slstk3400a/doc/index.rst b/boards/arm/efm32hg_slstk3400a/doc/index.rst deleted file mode 100644 index 9db17c59acf..00000000000 --- a/boards/arm/efm32hg_slstk3400a/doc/index.rst +++ /dev/null @@ -1,176 +0,0 @@ -.. _efm32hg_slstk3400a: - -EFM32HG-SLSTK3400A -################## - -Overview -******** - -The EFM32 Happy Gecko Starter Kit EFM32HG-SLSTK3400A contains a MCU from the -EFM32HG family built on ARM® Cortex®-M0+ processor with excellent low -power capabilities. - -.. figure:: efm32hg_slstk3400a.jpg - :align: center - :alt: EFM32HG-SLSTK3400A - - EFM32HG-SLSTK3400A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring system for precise current tracking -- Real-time energy and power profiling -- ARM Cortex M0+ with 64 kB Flash and 8 kB RAM -- 128 X 128 pixel Memory LCD -- 2 user buttons, 2 user LEDs and 2 touch buttons -- 20 pin expansion header -- Silicon Labs Si7021 Relative Humidity/Temperature sensor -- USB device interface -- Integrated SEGGER J-Link USB debugger/emulator with debug out functionality - - -See these documents for more information - -- `EFM32HG Website`_ -- `EFM32HG Datasheet`_ -- `EFM32HG Reference Manual`_ -- `EFM32HG-SLSTK3400A Website`_ -- `EFM32HG-SLSTK3400A User Guide`_ -- `EFM32HG-SLSTK3400A Schematics`_ - -Supported Features -================== - -The efm32hg_slstk3400 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig`` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32HG SoC has six GPIO controllers (PORTA to PORTF), but only three are -currently enabled (PORTB, PORTE and PORTF) for the EFM32HG-SLSTK3400A board. - -In the following table, the column Name contains Pin names. For example, PF4 -means Pin number 4 on PORTF, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PF4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PF5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PC9 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PC10 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PF2 | USART0_TX | USART Console EFM_BC_TX U0_TX #4 | -+-------+-------------+-------------------------------------+ -| PA9 | USART0_RX | USART Console EFM_BC_RX U0_RX #4 | -+-------+-------------+-------------------------------------+ - -System Clock -============ - -The EFM32HG SoC is configured to use the 24 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32HG SoC has two USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART1 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32HG-SLSTK3400 includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a Mass Storage and a - USB Serial Port. -- A Serial Flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB Serial port. - -Flashing an application to EFM32-SLSTK3400A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32hg_slstk3400a - :goals: build - -Connect the EFM32HG-SLSTK3400A to your host computer using the USB port and -you should see a USB connection that exposes a mass storage device (STK3400) -and a USB Serial Port. Copy the generated ``zephyr.bin`` in the STK3400 drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you will see this message written to the serial port: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32HG-SLSTK3400A Website: - https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-happy-gecko-starter-kit - -.. _EFM32HG-SLSTK3400A User Guide: - https://www.silabs.com/documents/public/user-guides/ug255-stk3400-user-guide.pdf - -.. _EFM32HG-SLSTK3400A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD2012A-B01-schematic.pdf - -.. _EFM32HG Website: - https://www.silabs.com/products/mcu/32-bit/efm32-happy-gecko - -.. _EFM32HG Datasheet: - https://www.silabs.com/documents/public/data-sheets/EFM32HG322.pdf - -.. _EFM32HG Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/EFM32HG-RM.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32pg_stk3401a/Kconfig.board b/boards/arm/efm32pg_stk3401a/Kconfig.board deleted file mode 100644 index 8c2222a9871..00000000000 --- a/boards/arm/efm32pg_stk3401a/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFM32PG STK3401A board - -# Copyright (c) 2020, Rafael Dias Menezes -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32PG_STK3401A - bool "SiLabs EFM32PG-STK3401A (Pearl Gecko)" - depends on SOC_SERIES_EFM32PG1B - select SOC_PART_NUMBER_EFM32PG1B200F256GM48 diff --git a/boards/arm/efm32pg_stk3401a/Kconfig.defconfig b/boards/arm/efm32pg_stk3401a/Kconfig.defconfig deleted file mode 100644 index 33fe600d96f..00000000000 --- a/boards/arm/efm32pg_stk3401a/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# EFM32PG STK3401A board - -# Copyright (c) 2020, Rafael Dias Menezes -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32PG_STK3401A - -config BOARD - default "efm32pg_stk3401a" if BOARD_EFM32PG_STK3401A - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFM32PG_STK3401A diff --git a/boards/arm/efm32pg_stk3401a/doc/index.rst b/boards/arm/efm32pg_stk3401a/doc/index.rst deleted file mode 100644 index 4d646060f25..00000000000 --- a/boards/arm/efm32pg_stk3401a/doc/index.rst +++ /dev/null @@ -1,189 +0,0 @@ -.. _efm32pg_stk3401a: - -EFM32 Pearl Gecko Starter Kit -############################# - -Overview -******** - -The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3401A contains an MCU from the -EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low -power capabilities. - -.. figure:: efm32pg_stk3401a.jpg - :align: center - :alt: EFM32PG-SLSTK3401A - - EFM32PG-SLSTK3401A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel Memory-LCD -- 2 user buttons, 2 LEDs and 2 capacitive buttons -- Humidity and temperature sensor -- On-board Segger J-Link USB debugger - -For more information about the EFM32PG SoC and EFM32PG-STK3401A board: - -- `EFM32PG Website`_ -- `EFM32PG1 Datasheet`_ -- `EFM32PG1 Reference Manual`_ -- `EFM32PG-STK3401A Website`_ -- `EFM32PG-STK3401A User Guide`_ - -Supported Features -================== - -The efm32pg_stk3401a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_defconfig`` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32PG1 SoC has five GPIO controllers (PORTA to PORTD and PORTF) and -all are enabled for the EFM32PG-STK3401A board. - -In the following table, the column **Name** contains pin names. For example, PF4 -means pin number 4 on PORTF, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PF4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PF5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PF6 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PA5 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | -+-------+-------------+-------------------------------------+ -| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | -+-------+-------------+-------------------------------------+ -| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | -+-------+-------------+-------------------------------------+ -| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | -+-------+-------------+-------------------------------------+ -| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | -+-------+-------------+-------------------------------------+ -| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32PG SoC is configured to use the 40 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32PG SoC has two USARTs and one Low Energy UART (LEUART). - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32PG-STK3401A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a mass storage device and a - USB serial port. -- A serial flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to EFM32PG-STK3401A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32pg_stk3401a - :goals: build - -Connect the EFM32PG-STK3401A to your host computer using the USB port and you -should see a USB connection which exposes a mass storage device(STK3401A). -Copy the generated zephyr.bin to the STK3401A drive. - -Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the -expansion header. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32PG-STK3401A Website: - https://www.silabs.com/development-tools/mcu/32-bit/efm32pg1-starter-kit - -.. _EFM32PG-STK3401A User Guide: - https://www.silabs.com/documents/public/user-guides/ug154-stk3401-user-guide.pdf - -.. _EFM32PG Website: - https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko - -.. _EFM32PG1 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32pg1-datasheet.pdf - -.. _EFM32PG1 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32pg1-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32pg_stk3402a/Kconfig.board b/boards/arm/efm32pg_stk3402a/Kconfig.board deleted file mode 100644 index dfb65d48086..00000000000 --- a/boards/arm/efm32pg_stk3402a/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# EFM32PG STK3402A board - -# Copyright (c) 2018, Christian Taedcke -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32PG_STK3402A - bool "SiLabs EFM32PG-STK3402A (Pearl Gecko)" - depends on SOC_SERIES_EFM32PG12B - select SOC_PART_NUMBER_EFM32PG12B500F1024GL125 - -config BOARD_EFM32PG_STK3402A_JG - bool "SiLabs EFM32PG-STK3402A (Jade Gecko)" - depends on SOC_SERIES_EFM32JG12B - select SOC_PART_NUMBER_EFM32JG12B500F1024GL125 diff --git a/boards/arm/efm32pg_stk3402a/Kconfig.defconfig b/boards/arm/efm32pg_stk3402a/Kconfig.defconfig deleted file mode 100644 index 5f298e584c3..00000000000 --- a/boards/arm/efm32pg_stk3402a/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# EFM32PG STK3402A board - -# Copyright (c) 2018, Christian Taedcke -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32PG_STK3402A || BOARD_EFM32PG_STK3402A_JG - -config BOARD - default "efm32pg_stk3402a" if BOARD_EFM32PG_STK3402A - default "efm32pg_stk3402a_jg" if BOARD_EFM32PG_STK3402A_JG - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFM32PG_STK3402A || BOARD_EFM32PG_STK3402A_JG diff --git a/boards/arm/efm32pg_stk3402a/doc/index.rst b/boards/arm/efm32pg_stk3402a/doc/index.rst deleted file mode 100644 index ca7ffe8471e..00000000000 --- a/boards/arm/efm32pg_stk3402a/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _efm32pg_stk3402a: - -EFM32 Pearl Gecko Starter Kit -############################# - -Overview -******** - -The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3402A contains an MCU from the -EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low -power capabilities. - -.. figure:: efm32pg_stk3402a.jpg - :align: center - :alt: EFM32PG-SLSTK3402A - - EFM32PG-SLSTK3402A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel Memory-LCD -- 2 user buttons, 2 LEDs and a touch slider -- Humidity, temperature, and inductive-capacitive metal sensor -- On-board Segger J-Link USB debugger - -For more information about the EFM32PG SoC and EFM32PG-STK3402A board: - -- `EFM32PG Website`_ -- `EFM32PG12 Datasheet`_ -- `EFM32PG12 Reference Manual`_ -- `EFM32PG-STK3402A Website`_ -- `EFM32PG-STK3402A User Guide`_ -- `EFM32PG-STK3402A Schematics`_ - -Supported Features -================== - -The efm32pg_stk3402a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | true random number generator | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_defconfig`` - -The default configuration when building for this EFM32JG12B SoC can be found in -another defconfig file: - - ``boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_defconfig_jg`` - -Other hardware features are currently not supported by the port. - -EFM32 Jade Gecko SoC --------------------- - -The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3402A can also be used to evaluate -the EFM32 Jade Gecko SoC (EFM32JG12B). The only difference between the Pearl -Gecko and the Jade Gecko is their core. The Pearl Gecko contains an ARM® -Cortex®-M4F core, and the Jade Gecko an ARM® Cortex®-M3 core. Other features -such as memory and peripherals are the same. - -Code that is built for the Jade Gecko also runs on an equivalent Pearl Gecko. - -To build firmware for the Jade Gecko and run it on the EFM32 Pearl Gecko Starter -Kit, use the board ``efm32pg_stk3402a_jg`` instead of ``efm32pg_stk3402a``. - -Connections and IOs -=================== - -The EFM32PG12 SoC has twelve GPIO controllers (PORTA to PORTL), but only four -are currently enabled (PORTA, PORTB, PORTD and PORTF) for the EFM32PG-STK3402A -board. - -In the following table, the column **Name** contains pin names. For example, PE2 -means pin number 2 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PF4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PF5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PF6 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PA5 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | -+-------+-------------+-------------------------------------+ -| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | -+-------+-------------+-------------------------------------+ -| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | -+-------+-------------+-------------------------------------+ -| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | -+-------+-------------+-------------------------------------+ -| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | -+-------+-------------+-------------------------------------+ -| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32PG SoC is configured to use the 40 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32PG SoC has four USARTs and one Low Energy UART (LEUART). - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32PG-STK3402A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a mass storage device and a - USB serial port. -- A serial flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to EFM32PG-STK3402A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32pg_stk3402a - :goals: build - -Connect the EFM32PG-STK3402A to your host computer using the USB port and you -should see a USB connection which exposes a mass storage device(STK3402A). -Copy the generated zephyr.bin to the STK3402A drive. - -Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the -expansion header. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32PG-STK3402A Website: - https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-pearl-gecko-pg12-starter-kit - -.. _EFM32PG-STK3402A User Guide: - https://www.silabs.com/documents/public/user-guides/ug257-stk3402-usersguide.pdf - -.. _EFM32PG-STK3402A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD2501A-A01-schematic.pdf - -.. _EFM32PG Website: - https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko - -.. _EFM32PG12 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32pg12-datasheet.pdf - -.. _EFM32PG12 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32pg12-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a.yaml b/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a.yaml deleted file mode 100644 index ebfe95c91ba..00000000000 --- a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: efm32pg_stk3402a -name: EFM32PG-STK3402A -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - i2c - - gpio - - nvs - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_defconfig b/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_defconfig deleted file mode 100644 index d3805477749..00000000000 --- a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFM32PG12B=y -CONFIG_BOARD_EFM32PG_STK3402A=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 -CONFIG_CMU_HFCLK_HFXO=y diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg.yaml b/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg.yaml deleted file mode 100644 index 8d7e590e393..00000000000 --- a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: efm32pg_stk3402a_jg -name: EFM32PG-STK3402A-JG -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - i2c - - gpio - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg_defconfig b/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg_defconfig deleted file mode 100644 index 36c92f45d2e..00000000000 --- a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFM32JG12B=y -CONFIG_BOARD_EFM32PG_STK3402A_JG=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 -CONFIG_CMU_HFCLK_HFXO=y diff --git a/boards/arm/efm32wg_stk3800/Kconfig.board b/boards/arm/efm32wg_stk3800/Kconfig.board deleted file mode 100644 index d75311cbe14..00000000000 --- a/boards/arm/efm32wg_stk3800/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFM32WG STK3800 board - -# Copyright (c) 2017, Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32WG_STK3800 - bool "SiLabs EFM32WG-STK3800 (Wonder Gecko)" - depends on SOC_SERIES_EFM32WG - select SOC_PART_NUMBER_EFM32WG990F256 diff --git a/boards/arm/efm32wg_stk3800/Kconfig.defconfig b/boards/arm/efm32wg_stk3800/Kconfig.defconfig deleted file mode 100644 index 90450ad0244..00000000000 --- a/boards/arm/efm32wg_stk3800/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# EFM32WG STK3800 board - -# Copyright (c) 2017, Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32WG_STK3800 - -config BOARD - default "efm32wg_stk3800" - -config CMU_HFXO_FREQ - default 48000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFM32WG_STK3800 diff --git a/boards/arm/efm32wg_stk3800/doc/index.rst b/boards/arm/efm32wg_stk3800/doc/index.rst deleted file mode 100644 index d624619d83f..00000000000 --- a/boards/arm/efm32wg_stk3800/doc/index.rst +++ /dev/null @@ -1,178 +0,0 @@ -.. _efm32wg_stk3800: - -EFM32WG-STK3800 -############### - -Overview -******** - -The EFM32 Wonder Gecko Starter Kit EFM32WG-STK3800 contains a MCU from the -EFM32WG family built on ARM® Cortex®-M4F processor with excellent low -power capabilities. - -.. figure:: efm32wg_stk3800.jpg - :align: center - :alt: EFM32WG-STK3800 - - EFM32WG-STK3800 (image courtesy of Silicon Labs) - - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- 32MByte parallel NAND Flash -- 160 segment Energy Micro LCD -- 2 user buttons, 2 LEDs and a touch slider -- Ambient Light Sensor and Inductive-capacitive metal sensor -- On-board Segger J-Link USB debugger - -For more information about the EFM32WG SoC and EFM32WG-STK3800 board: - -- `EFM32WG Website`_ -- `EFM32WG Datasheet`_ -- `EFM32WG Reference Manual`_ -- `EFM32WG-STK3800 Website`_ -- `EFM32WG-STK3800 User Guide`_ -- `EFM32WG-STK3800 Schematics`_ - -Supported Features -================== - -The efm32wg_stk3800 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32wg_stk3800/efm32wg_stk3800_defconfig`` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32WG SoC has six gpio controllers (PORTA to PORTF), but only three are -currently enabled (PORTB, PORTE and PORTF) for the EFM32WG-STK3800 board. - -In the following table, the column Name contains Pin names. For example, PE2 -means Pin number 2 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PE2 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PE3 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PB9 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PB10 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PE0 | UART0_TX | UART Console EFM_BC_TX U0_TX #1 | -+-------+-------------+-------------------------------------+ -| PE1 | UART0_RX | UART Console EFM_BC_RX U0_RX #1 | -+-------+-------------+-------------------------------------+ - -System Clock -============ - -The EFM32WG SoC is configured to use the 48 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32WG SoC has three USARTs, two UARTs and two Low Energy UARTs (LEUART). -UART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32WG-STK3800 includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a Mass Storage and a - USB Serial Port. -- A Serial Flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB Serial port. - -Flashing an application to EFM32-STK3800 ----------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32wg_stk3800 - :goals: build - -Connect the EFM32WG-STK3800 to your host computer using the USB port and you -should see a USB connection which exposes a Mass Storage (STK3800) and a -USB Serial Port. Copy the generated zephyr.bin in the STK3800 drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32WG-STK3800 Website: - http://www.silabs.com/products/development-tools/mcu/32-bit/efm32-wonder-gecko-starter-kit - -.. _EFM32WG-STK3800 User Guide: - http://www.silabs.com/documents/public/user-guides/efm32wg-stk3800-ug.pdf - -.. _EFM32WG-STK3800 Schematics: - http://www.silabs.com/documents/public/schematic-files/BRD2400A_A00.pdf - -.. _EFM32WG Website: - http://www.silabs.com/products/mcu/32-bit/efm32-wonder-gecko - -.. _EFM32WG Datasheet: - http://www.silabs.com/documents/public/data-sheets/EFM32WG990.pdf - -.. _EFM32WG Reference Manual: - http://www.silabs.com/documents/public/reference-manuals/EFM32WG-RM.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efr32_radio/Kconfig b/boards/arm/efr32_radio/Kconfig deleted file mode 100644 index 9de639f91bd..00000000000 --- a/boards/arm/efr32_radio/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# EFR32 radio board configuration - -# Copyright (c) 2020 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32_RADIO - bool diff --git a/boards/arm/efr32_radio/Kconfig.board b/boards/arm/efr32_radio/Kconfig.board deleted file mode 100644 index bbae554ae69..00000000000 --- a/boards/arm/efr32_radio/Kconfig.board +++ /dev/null @@ -1,48 +0,0 @@ -# EFR32BG13 BRD4104A / EFR32MG21 BRD4180A / -# EFR32FG1P BRD4250B / EFR32FG13P BRD4255A board - -# Copyright (c) 2020 Piotr Mienkowski -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32_RADIO_BRD4104A - bool "Silicon Labs BRD4104A (Blue Gecko Radio Board)" - depends on SOC_SERIES_EFR32BG13P - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32BG13P632F512GM48 - -config BOARD_EFR32_RADIO_BRD4170A - bool "Silicon Labs BRD4170A (Mighty Gecko Radio Board)" - depends on SOC_SERIES_EFR32MG12P - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32MG12P433F1024GM68 - -config BOARD_EFR32_RADIO_BRD4161A - bool "Silicon Labs BRD4161A (Mighty Gecko Radio Board)" - depends on SOC_SERIES_EFR32MG12P - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32MG12P432F1024GL125 - -config BOARD_EFR32_RADIO_BRD4250B - bool "Silicon Labs BRD4250B (Flex Gecko Radio Board)" - depends on SOC_SERIES_EFR32FG1P - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32FG1P133F256GM48 - -config BOARD_EFR32_RADIO_BRD4180A - bool "Silicon Labs BRD4180A (Mighty Gecko Radio Board)" - depends on SOC_SERIES_EFR32MG21 - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32MG21A020F1024IM32 - -config BOARD_EFR32_RADIO_BRD4187C - bool "Silicon Labs BRD4187C (Mighty Gecko Radio Board)" - depends on SOC_SERIES_EFR32MG24 - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32MG24B220F1536IM48 - -config BOARD_EFR32_RADIO_BRD4255A - bool "Silicon Labs BRD4255A (Flex Gecko Radio Board)" - depends on SOC_SERIES_EFR32FG13P - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32FG13P233F512GM48 diff --git a/boards/arm/efr32_radio/Kconfig.defconfig b/boards/arm/efr32_radio/Kconfig.defconfig deleted file mode 100644 index b91aa627b70..00000000000 --- a/boards/arm/efr32_radio/Kconfig.defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# EFR32 radio board - -# Copyright (c) 2020 Piotr Mienkowski -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32_RADIO - -config BOARD - default "efr32_radio_brd4104a" if BOARD_EFR32_RADIO_BRD4104A - default "efr32_radio_brd4170a" if BOARD_EFR32_RADIO_BRD4170A - default "efr32_radio_brd4161a" if BOARD_EFR32_RADIO_BRD4161A - default "efr32_radio_brd4250b" if BOARD_EFR32_RADIO_BRD4250B - default "efr32_radio_brd4180a" if BOARD_EFR32_RADIO_BRD4180A - default "efr32_radio_brd4187c" if BOARD_EFR32_RADIO_BRD4187C - default "efr32_radio_brd4255a" if BOARD_EFR32_RADIO_BRD4255A - -config CMU_HFXO_FREQ - default 39000000 if BOARD_EFR32_RADIO_BRD4187C - default 38400000 - -config CMU_LFXO_FREQ - default 32768 - -config FLASH_BASE_ADDRESS - hex - default 0x08000000 if BOARD_EFR32_RADIO_BRD4187C - default 0x0 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -if SOC_GECKO_USE_RAIL - -config FPU - default n if SOC_GECKO_SERIES1 - default y - -endif # SOC_GECKO_USE_RAIL - -if BT - -config FPU - default y - -config MINIMAL_LIBC_MALLOC_ARENA_SIZE - default 8192 - -config MAIN_STACK_SIZE - default 3072 if PM - default 2304 - -choice BT_HCI_BUS_TYPE - default BT_SILABS_HCI -endchoice - -endif # BT - -endif # BOARD_EFR32_RADIO diff --git a/boards/arm/efr32_radio/board.cmake b/boards/arm/efr32_radio/board.cmake deleted file mode 100644 index d684946143e..00000000000 --- a/boards/arm/efr32_radio/board.cmake +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(openocd) - -if(CONFIG_BOARD_EFR32_RADIO_BRD4104A) -board_runner_args(jlink "--device=EFR32BG13PxxxF512") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4250B) -board_runner_args(jlink "--device=EFR32FG1PxxxF256") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4170A) -board_runner_args(jlink "--device=EFR32MG12PxxxF1024") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4161A) -board_runner_args(jlink "--device=EFR32MG12PxxxF1024") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4180A) -board_runner_args(jlink "--device=EFR32MG21AxxxF1024") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4187C) -board_runner_args(jlink "--device=EFR32MG24BxxxF1536") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4255A) -board_runner_args(jlink "--device=EFR32FG13PxxxF512") -endif() - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/efr32_radio/efr32_radio_brd4104a.yaml b/boards/arm/efr32_radio/efr32_radio_brd4104a.yaml deleted file mode 100644 index 62e253011c7..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4104a.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: efr32_radio_brd4104a -name: BRD4104A -type: mcu -arch: arm -ram: 64 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4104a_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4104a_defconfig deleted file mode 100644 index 00991a6e4cd..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4104a_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32BG13P=y -CONFIG_BOARD_EFR32_RADIO_BRD4104A=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4161a.yaml b/boards/arm/efr32_radio/efr32_radio_brd4161a.yaml deleted file mode 100644 index 108d6f16c0f..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4161a.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio_brd4161a -name: BRD4161A -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4161a_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4161a_defconfig deleted file mode 100644 index fbf7cf38325..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4161a_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32MG12P=y -CONFIG_BOARD_EFR32_RADIO_BRD4161A=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4170a.yaml b/boards/arm/efr32_radio/efr32_radio_brd4170a.yaml deleted file mode 100644 index 88ed4089379..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4170a.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio_brd4170a -name: BRD4170A -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4170a_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4170a_defconfig deleted file mode 100644 index 32222b89b31..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4170a_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32MG12P=y -CONFIG_BOARD_EFR32_RADIO_BRD4170A=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4180a.dts b/boards/arm/efr32_radio/efr32_radio_brd4180a.dts deleted file mode 100644 index 43f4290ff84..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4180a.dts +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efr32_radio_brd4180a-pinctrl.dtsi" - -/ { - model = "Silicon Labs BRD4180A (Mighty Gecko Radio Board)"; - compatible = "silabs,efr32mg21_brd4180a", "silabs,efr32mg21"; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpiob 0 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpiob 1 0>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpiod 2 GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpiod 3 GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; - -}; - -&cpu0 { - clock-frequency = <38400000>; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rtcc0 { - prescaler = <1>; - status = "okay"; -}; - -&gpio { - status = "okay"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; - - board-controller-enable { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&wdog0 { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 48 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x0000c000>; - read-only; - }; - - /* Reserve 464 kB for the application in slot 0 */ - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000c000 0x00074000>; - }; - - /* Reserve 464 kB for the application in slot 1 */ - slot1_partition: partition@80000 { - label = "image-1"; - reg = <0x00080000 0x00074000>; - }; - - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@f4000 { - label = "image-scratch"; - reg = <0x000f4000 0x00008000>; - }; - - /* Set 16Kb of storage at the end of the 1024Kb of flash */ - storage_partition: partition@fc000 { - label = "storage"; - reg = <0x000fc000 0x00004000>; - }; - - }; -}; diff --git a/boards/arm/efr32_radio/efr32_radio_brd4180a.yaml b/boards/arm/efr32_radio/efr32_radio_brd4180a.yaml deleted file mode 100644 index ea286ce3c65..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4180a.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio_brd4180a -name: BRD4180A -type: mcu -arch: arm -ram: 96 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4180a_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4180a_defconfig deleted file mode 100644 index 0db69e5d9e1..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4180a_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFR32MG21=y -CONFIG_BOARD_EFR32_RADIO_BRD4180A=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_PINCTRL=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4187c.dts b/boards/arm/efr32_radio/efr32_radio_brd4187c.dts deleted file mode 100644 index 6e8703fabbe..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4187c.dts +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2023 Fr. Sauter AG - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efr32_radio_brd4187c-pinctrl.dtsi" - -/ { - model = "Silicon Labs BRD4187C (Mighty Gecko Radio Board)"; - compatible = "silabs,efr32mg24_brd4187c", "silabs,efr32mg24"; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_HIGH>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; - -}; - -&cpu0 { - clock-frequency = <39000000>; -}; - -&pstate_em3 { - status = "disabled"; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&gpio { - location-swo = <0>; - status = "okay"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; - - board-controller-enable { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&wdog0 { - status = "okay"; -}; - -&burtc0 { - status = "okay"; -}; - -&stimer0 { - status = "okay"; -}; - -&se { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 48 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 DT_SIZE_K(48)>; - read-only; - }; - - /* Reserve 720 kB for the application in slot 0 */ - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000c000 0x000B4000>; - }; - - /* Reserve 720 kB for the application in slot 1 */ - slot1_partition: partition@C0000 { - label = "image-1"; - reg = <0x000C0000 0x000B4000>; - }; - - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@174000 { - label = "image-scratch"; - reg = <0x00174000 DT_SIZE_K(32)>; - }; - - /* Set 16 kB of storage at the end of the 1536 kB of flash */ - storage_partition: partition@17c000 { - label = "storage"; - reg = <0x0017c000 DT_SIZE_K(16)>; - }; - }; -}; diff --git a/boards/arm/efr32_radio/efr32_radio_brd4187c.yaml b/boards/arm/efr32_radio/efr32_radio_brd4187c.yaml deleted file mode 100644 index a5602114a36..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4187c.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio_brd4187c -name: BRD4187C -type: mcu -arch: arm -ram: 256 -flash: 1536 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth - - pm - - hwinfo -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4187c_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4187c_defconfig deleted file mode 100644 index 046f8acfaed..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4187c_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFR32MG24=y -CONFIG_BOARD_EFR32_RADIO_BRD4187C=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=78000000 -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y -CONFIG_PINCTRL=y - -# Use BURTC as system clock source -CONFIG_GECKO_BURTC_TIMER=y -CONFIG_CMU_BURTCCLK_LFXO=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1024 diff --git a/boards/arm/efr32_radio/efr32_radio_brd4250b.yaml b/boards/arm/efr32_radio/efr32_radio_brd4250b.yaml deleted file mode 100644 index 0d45527eced..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4250b.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: efr32_radio_brd4250b -name: BRD4250B -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4250b_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4250b_defconfig deleted file mode 100644 index d9be04bc9cd..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4250b_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFR32FG1P=y -CONFIG_BOARD_EFR32_RADIO_BRD4250B=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4255a.yaml b/boards/arm/efr32_radio/efr32_radio_brd4255a.yaml deleted file mode 100644 index a5b7fc7cb90..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4255a.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: efr32_radio_brd4255a -name: BRD4255A -type: mcu -arch: arm -ram: 64 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4255a_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4255a_defconfig deleted file mode 100644 index 8d409047b75..00000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4255a_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFR32FG13P=y -CONFIG_BOARD_EFR32_RADIO_BRD4255A=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_thunderboard/Kconfig.board b/boards/arm/efr32_thunderboard/Kconfig.board deleted file mode 100644 index de6124d9e49..00000000000 --- a/boards/arm/efr32_thunderboard/Kconfig.board +++ /dev/null @@ -1,19 +0,0 @@ -# EFR32BG SLTB010A board - -# Copyright (c) 2021, Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32BG22_BRD4184A - bool "SiLabs EFR32BG22-BRD4184A (Thunderboard EFR32BG22)" - depends on SOC_SERIES_EFR32BG22 - select SOC_PART_NUMBER_EFR32BG22C224F512IM40 - -config BOARD_EFR32BG22_BRD4184B - bool "SiLabs EFR32BG22-BRD4184B (Thunderboard EFR32BG22)" - depends on SOC_SERIES_EFR32BG22 - select SOC_PART_NUMBER_EFR32BG22C224F512IM40 - -config BOARD_EFR32BG27_BRD2602A - bool "SiLabs EFR32BG27-BRD2602A (EFR32BG27 +8 dBm Dev Kit Board)" - depends on SOC_SERIES_EFR32BG27 - select SOC_PART_NUMBER_EFR32BG27C140F768IM40 diff --git a/boards/arm/efr32_thunderboard/Kconfig.defconfig b/boards/arm/efr32_thunderboard/Kconfig.defconfig deleted file mode 100644 index 71f5800df5e..00000000000 --- a/boards/arm/efr32_thunderboard/Kconfig.defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# Thunderboard-style boards - -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32BG22_BRD4184A - -config BOARD - default "efr32bg22_brd4184a" - -endif # BOARD_EFR32BG22_BRD4184A - -if BOARD_EFR32BG22_BRD4184B - -config BOARD - default "efr32bg22_brd4184b" - -endif # BOARD_EFR32BG22_BRD4184B - -if BOARD_EFR32BG27_BRD2602A - -config BOARD - default "efr32bg27_brd2602a" - -endif # BOARD_EFR32BG27_BRD2602A - -config CMU_HFXO_FREQ - default 38400000 - -config CMU_LFXO_FREQ - default 32768 - -if SOC_GECKO_USE_RAIL - -config FPU - default y - -endif # SOC_GECKO_USE_RAIL - -if BT - -config FPU - default y - -config COMMON_LIBC_MALLOC_ARENA_SIZE - default 8192 - -config MAIN_STACK_SIZE - default 3072 if PM - default 2304 - -choice BT_HCI_BUS_TYPE - default BT_SILABS_HCI -endchoice - -endif # BT - -config REGULATOR - default y if SI7210 diff --git a/boards/arm/efr32_thunderboard/board.cmake b/boards/arm/efr32_thunderboard/board.cmake deleted file mode 100644 index cc0f48cee82..00000000000 --- a/boards/arm/efr32_thunderboard/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_EFR32BG22_BRD4184A OR CONFIG_BOARD_EFR32BG22_BRD4184B) -board_runner_args(jlink "--device=EFR32BG22C224F512IM40" "--reset-after-load") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) - -elseif(CONFIG_BOARD_EFR32BG27_BRD2602A) -board_runner_args(silabs_commander "--device=EFR32BG27C140F768IM40") -include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) - -endif() diff --git a/boards/arm/efr32mg_sltb004a/Kconfig.board b/boards/arm/efr32mg_sltb004a/Kconfig.board deleted file mode 100644 index 8e884faf35f..00000000000 --- a/boards/arm/efr32mg_sltb004a/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFR32MG SLTB004A board - -# Copyright (c) 2018, Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32MG_SLTB004A - bool "SiLabs EFR32MG-SLTB004A (Thunderboard Sense 2)" - depends on SOC_SERIES_EFR32MG12P - select SOC_PART_NUMBER_EFR32MG12P332F1024GL125 diff --git a/boards/arm/efr32mg_sltb004a/Kconfig.defconfig b/boards/arm/efr32mg_sltb004a/Kconfig.defconfig deleted file mode 100644 index d8939cda5d6..00000000000 --- a/boards/arm/efr32mg_sltb004a/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# EFR32MG SLTB004A board - -# Copyright (c) 2018, Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32MG_SLTB004A - -config BOARD - default "efr32mg_sltb004a" - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFR32MG_SLTB004A diff --git a/boards/arm/efr32mg_sltb004a/doc/index.rst b/boards/arm/efr32mg_sltb004a/doc/index.rst deleted file mode 100644 index a918a181be5..00000000000 --- a/boards/arm/efr32mg_sltb004a/doc/index.rst +++ /dev/null @@ -1,220 +0,0 @@ -.. _efr32mg_sltb004a: - -EFR32MG-SLTB004A -################ - -Overview -******** - -The EFR32™ Mighty Gecko Starter Kit EFR32MG-SLTB004A (a.k.a Thunderboard -Sense 2) contains a MCU from the EFR32MG family built on ARM® Cortex®-M4F -processor with low power capabilities. - -.. image:: efr32mg_sltb004a.jpg - :align: center - :alt: EFR32MG-SLTB004A - -Hardware -******** - -- EFR32MG12 Mighty Gecko Wireless SoC with 38.4 MHz operating frequency -- ARM® Cortex® M4 core with 256 kB RAM and 1024 kB Flash -- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F) -- 2.4 GHz ceramic antenna for wireless transmission -- Silicon Labs Si7021 relative humidity and temperature sensor -- Silicon Labs Si1133 UV index and ambient light sensor -- Silicon Labs Si7210 hall effect sensor -- Bosch Sensortec BMP280 barometric pressure sensor -- ams CCS811 indoor air quality gas sensor -- TDK InvenSense ICM-20648 6-axis inertial sensor -- TDK InvenSense ICS-43434 MEMS microphone -- Four high brightness RGB LEDs from Broadcom Limited (ASMT-YTB7-0AA02) -- One bi-color LED and two push buttons -- Power enable signals for fine grained power-control -- On-board SEGGER J-Link debugger for easy programming and debugging, which - includes a USB virtual COM port -- Mini Simplicity connector for access to energy profiling and advanced wireless - network debugging -- Breakout pads for GPIO access and connection to external hardware -- Reset button -- Automatic switch-over between USB and battery power -- CR2032 coin cell holder and external battery connector - -For more information about the EFR32MG SoC and Thunderboard Sense 2 -(EFR32MG-SLTB004A) board: - -- `EFR32MG Website`_ -- `EFR32MG Datasheet`_ -- `EFR32MG Reference Manual`_ -- `EFR32MG-SLTB004A Website`_ -- `EFR32MG-SLTB004A User Guide`_ -- `EFR32MG-SLTB004A Schematics`_ - -Supported Features -================== - -The efr32mg_sltb004a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi port-polling | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | true random number generator | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/efr32mg_sltb004a/efr32mg_sltb004a_defconfig``. - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFR32MG SoC has eight gpio controllers (PORTA, PORTB, PORTC, PORTD, -PORTF, PORTI, PORTJ and PORTK). - -In the following table, the column Name contains Pin names. For example, PE2 -means Pin number 2 on PORTE and #27 represents the location bitfield , as used -in the board's and microcontroller's datasheets and manuals. - -+------+-------------+-----------------------------------+ -| Name | Function | Usage | -+======+=============+===================================+ -| PD8 | GPIO | LED0 (RED) | -+------+-------------+-----------------------------------+ -| PD9 | GPIO | LED1 (GREEN) | -+------+-------------+-----------------------------------+ -| PD14 | GPIO | SW0 Push Button PB0 | -+------+-------------+-----------------------------------+ -| PD15 | GPIO | Push Button PB1 | -+------+-------------+-----------------------------------+ -| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | -+------+-------------+-----------------------------------+ -| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | -+------+-------------+-----------------------------------+ -| PF3 | UART_TX | EXP12_UART_TX LEU0_TX #27 | -+------+-------------+-----------------------------------+ -| PF4 | UART_RX | EXP14_UART_RX LEU0_RX #27 | -+------+-------------+-----------------------------------+ -| PC10 | I2C_SDA | EXP16_I2C_SDA I2C0_SDA #15 | -+------+-------------+-----------------------------------+ -| PC11 | I2C_SCL | EXP15_I2C_SCL I2C0_SCL #15 | -+------+-------------+-----------------------------------+ -| PB6 | I2C_SDA | CCS811_I2C_SDA I2C1_SDA #6 | -+------+-------------+-----------------------------------+ -| PB7 | I2C_SCL | CCS811_I2C_SCL I2C1_SCL #6 | -+------+-------------+-----------------------------------+ -| PK0 | SPI_MOSI | Flash MOSI US2_TX #29 | -+------+-------------+-----------------------------------+ -| PK2 | SPI_MISO | Flash MISO US2_RX #30 | -+------+-------------+-----------------------------------+ -| PF7 | SPI_SCLK | Flash SCLK US2_CLK #18 | -+------+-------------+-----------------------------------+ -| PK1 | SPI_CS | Flash Chip Select (GPIO) | -+------+-------------+-----------------------------------+ - -System Clock -============ - -The EFR32MG SoC is configured to use the 38.4 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32MG SoC has four USARTs and one Low Energy UARTs (LEUART with 9600 -maximum baudrate). USART0 is configured as the Zephyr console and is connected -to the On-Board J-Link Debugger that presents a virtual COM port for general -purpose application serial data transfer with this interface. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFR32MG-SLTB004A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a Mass Storage and a - USB Serial Port. -- A Serial Flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB Serial port. - -Flashing an application to EFR32-SLTB004A ------------------------------------------ - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32mg_sltb004a - :goals: build - -Connect the EFR32MG-SLTB004A to your host computer using the USB port and you -should see a USB connection which exposes a Mass Storage (TB004) and a -USB Serial Port. Copy the generated zephyr.bin in the SLTB004A drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! arm - - -.. _EFR32MG-SLTB004A Website: - https://www.silabs.com/products/development-tools/thunderboard/thunderboard-sense-two-kit - -.. _EFR32MG-SLTB004A User Guide: - https://www.silabs.com/documents/public/user-guides/ug309-sltb004a-user-guide.pdf - -.. _EFR32MG-SLTB004A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD4166A-D00-schematic.pdf - -.. _EFR32MG Website: - https://www.silabs.com/products/wireless/mesh-networking/efr32mg-mighty-gecko-zigbee-thread-soc - -.. _EFR32MG Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32mg12-datasheet.pdf - -.. _EFR32MG Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg12-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efr32xg24_dk2601b/Kconfig.board b/boards/arm/efr32xg24_dk2601b/Kconfig.board deleted file mode 100644 index 9b205615852..00000000000 --- a/boards/arm/efr32xg24_dk2601b/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFR32XG24 DK2601B board - -# Copyright (c) 2021, Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32XG24_DK2601B - bool "Silicon Labs BRD2601B (Mighty Gecko Radio Board)" - depends on SOC_SERIES_EFR32MG24 - select SOC_PART_NUMBER_EFR32MG24B310F1536IM48 diff --git a/boards/arm/efr32xg24_dk2601b/Kconfig.defconfig b/boards/arm/efr32xg24_dk2601b/Kconfig.defconfig deleted file mode 100644 index 0f0cf9aa163..00000000000 --- a/boards/arm/efr32xg24_dk2601b/Kconfig.defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# EFR32XG24 DK2601B board - -# Copyright (c) 2021, Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32XG24_DK2601B - -config BOARD - default "efr32xg24_dk2601b" - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -config FLASH_BASE_ADDRESS - hex - default 0x08000000 - -if SOC_GECKO_USE_RAIL - -config FPU - default y - -endif # SOC_GECKO_USE_RAIL - -if BT - -config FPU - default y - -config MINIMAL_LIBC_MALLOC_ARENA_SIZE - default 8192 - -config MAIN_STACK_SIZE - default 2304 - -choice BT_HCI_BUS_TYPE - default BT_SILABS_HCI -endchoice - -endif # BT - -endif # BOARD_EFR32XG24_DK2601B diff --git a/boards/arm/efr32xg24_dk2601b/doc/index.rst b/boards/arm/efr32xg24_dk2601b/doc/index.rst deleted file mode 100644 index dc9766ed67c..00000000000 --- a/boards/arm/efr32xg24_dk2601b/doc/index.rst +++ /dev/null @@ -1,185 +0,0 @@ -.. _efr32mg24_dk2601b: - -xG24-DK2601B -########################### - -Overview -******** - -The EFR32MG24 Mighty Gecko Board dev kit contains -a Wireless System-On-Chip from the EFR32MG24 family built on an -ARM Cortex®-M33F processor with excellent low power capabilities. - -.. figure:: ./img/efr32xg24_dk2601b.jpg - :height: 260px - :align: center - :alt: SLWRB4180A Mighty Gecko Radio Board - - xG24-DK2601B (image courtesy of Silicon Labs) - -Hardware -******** - -- EFR32MG24B310F1536IM48-B Mighty Gecko SoC -- CPU core: ARM Cortex®-M33 with FPU -- Flash memory: 1536 kB -- RAM: 256 kB -- Transmit power: up to +20 dBm -- Operation frequency: 2.4 GHz -- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). -- On board sensors: - - - Silicon Labs Si7021 relative humidity & temperature sensor - - Silicon Labs Si7210 hall effect sensor - - 2x TDK InvenSense ICS-43434 MEMS microphones with I2S output - - TDK InvenSense ICM-20689 6-axis inertial measurement sensor - - Vishay VEML6035 ambient light sensor - - Bosch BMP384 pressure sensor with internal temperature sensor - -For more information about the EFR32MG24 SoC and BRD2601B board, refer to these -documents: - -- `EFR32MG24 Website`_ -- `EFR32MG24 Datasheet`_ -- `EFR32xG24 Reference Manual`_ -- `BRD2601B User Guide`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | semailbox | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| I2C(M/S) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | bluetooth | -+-----------+------------+-------------------------------------+ - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -In the following table, the column **Name** contains Pin names. For example, PA2 -means Pin number 2 on PORTA, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PA4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PB0 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PB2 | GPIO | Push Button 0 | -+-------+-------------+-------------------------------------+ -| PB3 | GPIO | Push Button 1 | -+-------+-------------+-------------------------------------+ -| PA5 | USART0_TX | UART Console EFM_BC_TX US0_TX | -+-------+-------------+-------------------------------------+ -| PA6 | USART0_RX | UART Console EFM_BC_RX US0_RX | -+-------+-------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig`` - -System Clock -============ - -The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32MG24 SoC has one USART and two EUSARTs. -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32xg24_dk2601b - :goals: build - -Connect the efr32xg24_dk2601b to your host computer using the USB port and you -should see a USB connection. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efr32xg24_dk2601b - -Bluetooth -========= - -To use the BLE function, run the command below to retrieve necessary binary -blobs from the SiLabs HAL repository. - -.. code-block:: console - - west blobs fetch silabs - -Then build the Zephyr kernel and a Bluetooth sample with the following -command. The :ref:`bluetooth-observer-sample` sample application is used in -this example. - -.. zephyr-app-commands:: - :zephyr-app: samples/bluetooth/observer - :board: efr32xg24_dk2601b - :goals: build - -.. _EFR32MG24 Website: - https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-socs# - -.. _EFR32MG24 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf - -.. _EFR32xG24 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg24-rm.pdf - -.. _BRD2601B User Guide: - https://www.silabs.com/documents/public/user-guides/ug524-brd2601b-user-guide.pdf - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/ev11l78a/Kconfig.board b/boards/arm/ev11l78a/Kconfig.board deleted file mode 100644 index 629eb3c6247..00000000000 --- a/boards/arm/ev11l78a/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Microchip EV11L78A Board configuration - -# Copyright (c) 2023 Meta Platforms, Inc. and its affiliates. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EV11L78A - bool "Microchip EV11L78A" - depends on SOC_PART_NUMBER_SAMD20E16 diff --git a/boards/arm/ev11l78a/Kconfig.defconfig b/boards/arm/ev11l78a/Kconfig.defconfig deleted file mode 100644 index 54b74107814..00000000000 --- a/boards/arm/ev11l78a/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Microchip EV11L78A Board configuration - -# Copyright (c) 2023 Meta Platforms, Inc. and its affiliates. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "ev11l78a" - depends on BOARD_EV11L78A diff --git a/boards/arm/ev11l78a/doc/index.rst b/boards/arm/ev11l78a/doc/index.rst deleted file mode 100644 index cfa4f075eee..00000000000 --- a/boards/arm/ev11l78a/doc/index.rst +++ /dev/null @@ -1,105 +0,0 @@ -.. _ev11l78a: - -UPD301C Basic Sink Application Example -###################################### - -Overview -******** - -The UPD301C Basic Sink Application Example Evaluation Kit (EV11L78A) -is a low-cost evaluation platform for Microchip's UPD301C Standalone -Programmable USB Power Delivery (PD) Controller. This RoHS-compliant -evaluation platform comes in a small form factor and adheres to the -USB Type-C™ Connector Specification and USB PD 3.0 specification. - -.. figure:: img/ev11l78a.jpg - :width: 500px - :align: center - :alt: EV11L78A - - UPD301C Basic Sink Application Example (Credit: `Microchip Technology`_) - -Hardware -******** - -- ATSAMD20E16 ARM Cortex-M0+ processor at 48 MHz -- UPD301C combines a SAMD20 core and a UPD350 USB-PD controller -- Sink PDO Selector Switch -- Onboard LED Voltmeter - -Supported Features -================== - -The ev11l78a board configuration supports the following hardware -features: - - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - -Other hardware features are not currently supported by Zephyr. - -Refer to the `EV11L78A Schematics`_ for a detailed hardware diagram. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/ev11l78a/ev11l78a_defconfig`. - -Serial Port -=========== - -The SAMD20 MCU has 6 SERCOM based USARTs. One of the USARTs -(SERCOM1) is available on the Debug/Status header. - -SPI Port -======== - -The SAMD20 MCU has 6 SERCOM based SPIs. One of the SPIs (SERCOM0) -is internally connected between the SAMD20 core and the UPD350. - -I²C Port -======== - -The SAMD20 MCU has 6 SERCOM based I2Cs. One of the I2Cs (SERCOM3) -is available on the Debug/Status header. - -References -********** - -.. target-notes:: - -.. _Microchip Technology: - https://www.microchip.com/en-us/development-tool/ev11l78a - -.. _EV11L78A Schematics: - https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/SupportingCollateral/03-00056-R1.0.PDF diff --git a/boards/arm/ev11l78a/ev11l78a_defconfig b/boards/arm/ev11l78a/ev11l78a_defconfig deleted file mode 100644 index 5d9a8a9d651..00000000000 --- a/boards/arm/ev11l78a/ev11l78a_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD20=y -CONFIG_SOC_PART_NUMBER_SAMD20E16=y -CONFIG_SOC_ATMEL_SAMD_OSC8M=y -CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y -CONFIG_BOARD_EV11L78A=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Kernel Options due to Low Memory (4k) -CONFIG_LOG_BUFFER_SIZE=256 -CONFIG_MAIN_STACK_SIZE=640 -CONFIG_IDLE_STACK_SIZE=200 -CONFIG_ISR_STACK_SIZE=512 -CONFIG_USBC_STACK_SIZE=512 -# Prevent Interrupt Vector Table in RAM -CONFIG_SRAM_VECTOR_TABLE=n - -# This board only supports the sink role, so -# no need to ever implement source for it. -CONFIG_USBC_CSM_SINK_ONLY=y diff --git a/boards/arm/faze/Kconfig.board b/boards/arm/faze/Kconfig.board deleted file mode 100644 index 22f5bc769c1..00000000000 --- a/boards/arm/faze/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Seagate FireCuda Gaming SSD (FaZe) board - -# Copyright (c) 2020, Seagate Technology LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FAZE - bool "Seagate FireCuda Gaming SSD (FaZe)" - depends on SOC_SERIES_LPC11U6X - select SOC_PART_NUMBER_LPC11U67JBD48 diff --git a/boards/arm/faze/Kconfig.defconfig b/boards/arm/faze/Kconfig.defconfig deleted file mode 100644 index 39135dabeb8..00000000000 --- a/boards/arm/faze/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Seagate FireCuda Gaming SSD (FaZe) board - -# Copyright (c) 2020, Seagate Technology LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FAZE - -config BOARD - default "faze" - -endif # BOARD_FAZE diff --git a/boards/arm/fk7b0m1_vbt6/Kconfig.board b/boards/arm/fk7b0m1_vbt6/Kconfig.board deleted file mode 100644 index 0b46551e95e..00000000000 --- a/boards/arm/fk7b0m1_vbt6/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H7B0VBT FK7B0M1_VBT6 board - -# Copyright (c) 2023 Charles Dias -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FK7B0M1_VBT6 - bool "FANKE FK7B0M1-VBT6 board" - depends on SOC_STM32H7B0XX diff --git a/boards/arm/fk7b0m1_vbt6/Kconfig.defconfig b/boards/arm/fk7b0m1_vbt6/Kconfig.defconfig deleted file mode 100644 index 39de99eb5f8..00000000000 --- a/boards/arm/fk7b0m1_vbt6/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32H7B0VBT board configuration - -# Copyright (c) Charles Dias -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FK7B0M1_VBT6 - -config BOARD - default "fk7b0m1_vbt6" - -endif # BOARD_FK7B0M1_VBT6 diff --git a/boards/arm/fk7b0m1_vbt6/doc/index.rst b/boards/arm/fk7b0m1_vbt6/doc/index.rst deleted file mode 100644 index 2af182bc041..00000000000 --- a/boards/arm/fk7b0m1_vbt6/doc/index.rst +++ /dev/null @@ -1,179 +0,0 @@ -.. _fk7b0m1_vbt6: - -FANKE FK7B0M1-VBT6 -################## - -Overview -******** - -The FK7B0M1-VBT6 core board by FANKE Technology Co., Ltd. is an advanced microcontroller -platform based on the STMicroelectronics Arm® Cortex®-M7 core STM32H7B0VBT6 microcontroller. -This board is an ideal solution for developers looking to create high-performance -applications, especially in the field of Human-Machine Interface (HMI), leveraging its -robust capabilities and support for sophisticated display and touch technologies. - -The FK7B0M1-VBT6 is designed as a reference design for user application development before -transitioning to the final product, significantly simplifying the development process. -Its wide range of hardware features, including advanced display and touch capabilities, -make it exceptionally suitable for HMI applications, allowing for comprehensive evaluation -and testing of peripherals and functionalities. - -.. figure:: img/fk7b0m1_vbt6.webp - :width: 600px - :align: center - :alt: FK7B0M1-VBT6 - - FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd) - -Hardware -******** - -FK7B0M1-VBT6 provides the following hardware components: - -- STM32H7B6VB in LQFP100 package -- ARM 32-bit Cortex-M7 CPU with FPU -- 280 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 128 KB Flash -- ~1.4 MB SRAM max (1.18 Mbytes user SRAM + 64 Kbytes ITCM RAM + 128 Kbytes DTCM RAM + 4 Kbytes SRAM in Backup domain) -- Main clock: External 25MHz crystal oscillator. -- RTC: 32.768kHz crystal oscillator. -- 32-bit timers(2) -- 16-bit timers(12) -- 1 reset button, 1 user button, and 1 BOOT button -- 1 user LED -- External 64-Mbit QSPI (W25Q64) NOR Flash memory. -- External 64-Mbit SPI (W25Q64) NOR Flash memory. -- USB OTG Full Speed and High Speed(1) -- 1 micro SD card -- 1 RGB LCD interface -- SWD and serial port accessibility through a pin header -- Bring out 39 IO ports - -More information about STM32H7B0VB can be found here: - -- `STM32H7B0VB on www.st.com`_ - -Supported Features -================== - -The Zephyr nucleo_h723zg board configuration supports the following hardware -features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration per core can be found in the defconfig files: -``boards/arm/fk7b0m1-vbt6/fk7b0m1_vbt6_defconfig`` - -Connections and IOs -=================== - -Available pins: ---------------- - -Nucleo FK7B0M1-VBT6 board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -.. figure:: img/fk7b0m1_vbt6_pins.webp - :width: 600px - :align: center - :alt: FK7B0M1-VBT6 - - FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd) - -LED ---- - -- User LED (blue) = PC1 - -Push buttons -------------------------- - -- BOOT = SW1 = BOOT0 -- RESET = SW2 = NRST -- User button = SW3 = PC13 - -UART ------ - -- TX device = USART1 PA9 -- RX device = USART1 PA10 - -USB ---- - -- USB D- = PA11 -- USB D+ = PA12 - -System Clock -============ - -The FK7B0M1-VBT6 System Clock could be driven by an internal or external oscillator, -as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 280MHz, -driven by an 25MHz external crystal oscillator. - -Serial Port -=========== - -The Zephyr console output is assigned to UART1. The default communication settings are 115200 8N1. - -Programming and Debugging -************************* - -The FK7B0M1-VBT6 board does not include an on-board debugger. As a result, it requires -an external debugger, such as ST-Link, for programming and debugging purposes. - -The board provides header pins for the Serial Wire Debug (SWD) interface. - -Flashing -======== - -To begin, connect the ST-Link Debug Programmer to the FK7B0M1-VBT6 board using the SWD -interface. Next, connect the ST-Link to your host computer via a USB port. -Once this setup is complete, you can proceed to build and flash your application to the board - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: fk7b0m1_vbt6 - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 -b 115200 - -Then, press the RESET button, you should see the following message: - -.. code-block:: console - - Hello World! fk7b0m1_vbt6 - -Debugging -========= - -This current Zephyr port does not support debugging. - -References -********** - -.. target-notes:: -.. _STM32H7B0VB on www.st.com: https://www.st.com/en/microcontrollers/stm32h7b0vb.html diff --git a/boards/arm/frdm_k22f/Kconfig.board b/boards/arm/frdm_k22f/Kconfig.board deleted file mode 100644 index 343dda21e42..00000000000 --- a/boards/arm/frdm_k22f/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# FRDM-K22F board - -# Copyright (c) 2018, Prevas A/S -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_K22F - bool "NXP FRDM-K22F" - depends on SOC_SERIES_KINETIS_K2X - select SOC_PART_NUMBER_MK22FN512VLH12 diff --git a/boards/arm/frdm_k22f/Kconfig.defconfig b/boards/arm/frdm_k22f/Kconfig.defconfig deleted file mode 100644 index 1f262619929..00000000000 --- a/boards/arm/frdm_k22f/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# FRDM-K22F board - -# Copyright (c) 2018 Prevas A/S -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FRDM_K22F - -config BOARD - default "frdm_k22f" - -config OSC_XTAL0_FREQ - default 8000000 - -config MCG_PRDIV0 - default 0x3 - -config MCG_VDIV0 - default 0xc - -config MCG_FCRDIV - default 0 - -endif # BOARD_FRDM_K22F diff --git a/boards/arm/frdm_k22f/doc/index.rst b/boards/arm/frdm_k22f/doc/index.rst deleted file mode 100644 index bdd34cc25f1..00000000000 --- a/boards/arm/frdm_k22f/doc/index.rst +++ /dev/null @@ -1,298 +0,0 @@ -.. _frdm_k22f: - -NXP FRDM-K22F -############## - -Overview -******** - -The Freedom-K22F is an ultra-low-cost development platform for Kinetis K22 -MCUs. - -- Form-factor compatible with the Arduino R3 pin layout -- Peripherals enable rapid prototyping, including a 6-axis digital - accelerometer and magnetometer to create full eCompass capabilities, a - tri-colored LED and 2 user push-buttons for direct interaction, a optional - microSD card slot, and headers for use with Bluetooth* and 2.4 GHz radio - add-on modules -- OpenSDAv2, the NXP open source hardware embedded serial and debug adapter - running an open source bootloader, offers options for serial communication, - flash programming, and run-control debugging - -.. image:: frdm_k22f.jpg - :align: center - :alt: FRDM-K22F - -Hardware -******** - -- MK22FN512VLH12 (120 MHz, 1 MB flash memory, 256 KB RAM, low-power, - crystal-less USB, and 64 pin Low profile Quad Flat Package (LQFP)) -- Dual role USB interface with micro-B USB connector -- RGB LED -- FXOS8700CQ accelerometer and magnetometer -- Two user push buttons -- Flexible power supply option - OpenSDAv2 USB, Kinetis K22 USB, and external source -- Easy access to MCU input/output through Arduino* R3 compatible I/O connectors -- Programmable OpenSDAv2 debug circuit supporting the CMSIS-DAP Interface - software that provides: - - - Mass storage device (MSD) flash programming interface - - CMSIS-DAP debug interface over a driver-less USB HID connection providing - run-control debugging and compatibility with IDE tools - - Virtual serial port interface - - Open source CMSIS-DAP software project - -- Optional SDHC - -For more information about the K22F SoC and FRDM-K22F board: - -- `K22F Website`_ -- `K22F Datasheet`_ -- `K22F Reference Manual`_ -- `FRDM-K22F Website`_ -- `FRDM-K22F User Guide`_ -- `FRDM-K22F Schematics`_ - -Supported Features -================== - -The frdm_k22f board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the frdm_k64f board may have additional features -already supported, which can also be re-used on this frdm_k22f board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger | -+-----------+------------+-------------------------------------+ -| RNGA | on-chip | entropy; | -| | | random | -+-----------+------------+-------------------------------------+ -| FTFE | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - -:zephyr_file:`boards/arm/frdm_k22f/frdm_k22f_defconfig` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The K22F SoC has five pairs of pinmux/gpio controllers. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTA1 | GPIO | Red LED | -+-------+-----------------+---------------------------+ -| PTA2 | GPIO | Green LED | -+-------+-----------------+---------------------------+ -| PTD5 | GPIO | Blue LED | -+-------+-----------------+---------------------------+ -| PTC1 | GPIO | SW2 | -+-------+-----------------+---------------------------+ -| PTD0 | GPIO | FXOS8700 INT1 | -+-------+-----------------+---------------------------+ -| PTD1 | GPIO | FXOS8700 INT2 | -+-------+-----------------+---------------------------+ -| PTB17 | GPIO | SW3 | -+-------+-----------------+---------------------------+ -| PTE1 | UART1_RX | UART Console | -+-------+-----------------+---------------------------+ -| PTE0 | UART1_TX | UART Console | -+-------+-----------------+---------------------------+ -| PTD2 | UART2_RX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTD3 | UART2_TX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTC4 | SPI0_PCS0 | SPI | -+-------+-----------------+---------------------------+ -| PTD1 | SPI0_SCK | SPI | -+-------+-----------------+---------------------------+ -| PTD2 | SPI0_SOUT | SPI | -+-------+-----------------+---------------------------+ -| PTD3 | SPI0_SIN | SPI | -+-------+-----------------+---------------------------+ -| PTB2 | I2C0_SCL | I2C / FXOS8700 | -+-------+-----------------+---------------------------+ -| PTB3 | I2C0_SDA | I2C / FXOS8700 | -+-------+-----------------+---------------------------+ - -System Clock -============ - -The K22F SoC is configured to use the 8 MHz crystal oscillator on the board -with the on-chip PLL to generate a 72 MHz system clock in its RUN mode. This -clock was selected to allow for the maximum number of peripherals to be used -with the crystal and PLL clocks. Other clock configurations are possible -through NXP SDK currently. - -Serial Port -=========== - -The K22F SoC has three UARTs. One is configured for the console, another for BT -HCI, and the remaining are not used. - -USB -=== - -The K22F SoC has a USB OTG (USBOTG) controller that supports both -device and host functions through its micro USB connector (K22F USB). -Only USB device function is supported in Zephyr at the moment. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Early versions of this board have an outdated version of the OpenSDA bootloader -and require an update. Please see the `DAPLink Bootloader Update`_ page for -instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. - -Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) ------------------------------------------------------------------- - -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program -the `OpenSDA DAPLink FRDM-K22F Firmware`_. - -Option 2: :ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `Segger J-Link OpenSDA V2.1 Firmware`_. Note that Segger -does provide an OpenSDA J-Link Board-Specific Firmware for this board, however -it is not compatible with the DAPLink bootloader. - -Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and -``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the -default runner from pyOCD to J-Link: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k22f - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J26. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k22f - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.0.0 ***** - Hello World! frdm_k22f - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k22f - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.0.0 ***** - Hello World! frdm_k22f - -.. _FRDM-K22F Website: - https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/freedom-development-boards/mcu-boards/nxp-freedom-development-platform-for-kinetis-k22-mcus:FRDM-K22F - -.. _FRDM-K22F User Guide: - https://www.nxp.com/webapp/Download?colCode=FRDMK22FUG - -.. _FRDM-K22F Schematics: - https://www.nxp.com/webapp/Download?colCode=FRDM-K22F-SCH - -.. _K22F Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k2x-usb/kinetis-k22-120-mhz-cost-effective-full-speed-usb-microcontrollers-mcus-based-on-arm-cortex-m4-core:K22_120 - -.. _K22F Datasheet: - https://www.nxp.com/docs/en/data-sheet/K22P121M120SF7.pdf - -.. _K22F Reference Manual: - https://www.nxp.com/docs/en/reference-manual/K22P121M120SF7RM.pdf - -.. _OpenSDA DAPLink FRDM-K22F Firmware: - https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk22f_if_crc_legacy_0x8000.bin - -.. _DAPLink Bootloader Update: - https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ - -.. _Segger J-Link OpenSDA V2.1 Firmware: - https://www.segger.com/downloads/jlink/OpenSDA_V2_1.bin diff --git a/boards/arm/frdm_k64f/Kconfig.board b/boards/arm/frdm_k64f/Kconfig.board deleted file mode 100644 index d57ffc90708..00000000000 --- a/boards/arm/frdm_k64f/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_K64F - bool "Freescale FRDM-K64F" - depends on SOC_SERIES_KINETIS_K6X - select SOC_PART_NUMBER_MK64FN1M0VLL12 diff --git a/boards/arm/frdm_k64f/Kconfig.defconfig b/boards/arm/frdm_k64f/Kconfig.defconfig deleted file mode 100644 index f4ccc456eab..00000000000 --- a/boards/arm/frdm_k64f/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# FRDM-K64F board - -# Copyright (c) 2016, Freescale Semiconductor, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FRDM_K64F - -config BOARD - default "frdm_k64f" - -config OSC_XTAL0_FREQ - default 50000000 - -config MCG_PRDIV0 - default 0x13 - -config MCG_VDIV0 - default 0x18 - -config MCG_FCRDIV - default 1 - -config TEST_EXTRA_STACK_SIZE - default 128 - -if NETWORKING - -config NET_L2_ETHERNET - default y if !MODEM - -endif # NETWORKING - -endif # BOARD_FRDM_K64F diff --git a/boards/arm/frdm_k64f/doc/index.rst b/boards/arm/frdm_k64f/doc/index.rst deleted file mode 100644 index acbf2260561..00000000000 --- a/boards/arm/frdm_k64f/doc/index.rst +++ /dev/null @@ -1,402 +0,0 @@ -.. _frdm_k64f: - -NXP FRDM-K64F -############## - -Overview -******** - -The Freedom-K64F is an ultra-low-cost development platform for Kinetis K64, -K63, and K24 MCUs. - -- Form-factor compatible with the Arduino R3 pin layout -- Peripherals enable rapid prototyping, including a 6-axis digital - accelerometer and magnetometer to create full eCompass capabilities, a - tri-colored LED and 2 user push-buttons for direct interaction, a microSD - card slot, and connectivity using onboard Ethernet port and headers for use - with Bluetooth* and 2.4 GHz radio add-on modules -- OpenSDAv2, the NXP open source hardware embedded serial and debug adapter - running an open source bootloader, offers options for serial communication, - flash programming, and run-control debugging - -.. image:: frdm_k64f.jpg - :align: center - :alt: FRDM-K64F - -Hardware -******** - -- MK64FN1M0VLL12 MCU (120 MHz, 1 MB flash memory, 256 KB RAM, low-power, - crystal-less USB, and 100 Low profile Quad Flat Package (LQFP)) -- Dual role USB interface with micro-B USB connector -- RGB LED -- FXOS8700CQ accelerometer and magnetometer -- Two user push buttons -- Flexible power supply option - OpenSDAv2 USB, Kinetis K64 USB, and external source -- Easy access to MCU input/output through Arduino* R3 compatible I/O connectors -- Programmable OpenSDAv2 debug circuit supporting the CMSIS-DAP Interface - software that provides: - - - Mass storage device (MSD) flash programming interface - - CMSIS-DAP debug interface over a driver-less USB HID connection providing - run-control debugging and compatibility with IDE tools - - Virtual serial port interface - - Open source CMSIS-DAP software project - -- Ethernet -- SDHC - -For more information about the K64F SoC and FRDM-K64F board: - -- `K64F Website`_ -- `K64F Datasheet`_ -- `K64F Reference Manual`_ -- `FRDM-K64F Website`_ -- `FRDM-K64F User Guide`_ -- `FRDM-K64F Schematics`_ - -Supported Features -================== - -NXP considers the FRDM-K64F as the superset board for the Kinetis K -series of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire Kinetis K series. NXP prioritizes enabling -this board with new support for Zephyr features. The frdm_k64f board -configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| RNGA | on-chip | entropy; | -| | | random | -+-----------+------------+-------------------------------------+ -| FTFE | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/frdm_k64f/frdm_k64f_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The K64F SoC has five pairs of pinmux/gpio controllers. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTB22 | GPIO | Red LED | -+-------+-----------------+---------------------------+ -| PTE26 | GPIO | Green LED | -+-------+-----------------+---------------------------+ -| PTB21 | GPIO | Blue LED | -+-------+-----------------+---------------------------+ -| PTC6 | GPIO | SW2 / FXOS8700 INT1 | -+-------+-----------------+---------------------------+ -| PTC13 | GPIO | FXOS8700 INT2 | -+-------+-----------------+---------------------------+ -| PTA4 | GPIO | SW3 | -+-------+-----------------+---------------------------+ -| PTB10 | ADC | ADC1 channel 14 | -+-------+-----------------+---------------------------+ -| PTB16 | UART0_RX | UART Console | -+-------+-----------------+---------------------------+ -| PTB17 | UART0_TX | UART Console | -+-------+-----------------+---------------------------+ -| PTB18 | CAN0_TX | CAN TX | -+-------+-----------------+---------------------------+ -| PTB19 | CAN0_RX | CAN RX | -+-------+-----------------+---------------------------+ -| PTC8 | PWM | PWM_3 channel 4 | -+-------+-----------------+---------------------------+ -| PTC9 | PWM | PWM_3 channel 5 | -+-------+-----------------+---------------------------+ -| PTC16 | UART3_RX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTC17 | UART3_TX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTD0 | SPI0_PCS0 | SPI | -+-------+-----------------+---------------------------+ -| PTD1 | SPI0_SCK | SPI | -+-------+-----------------+---------------------------+ -| PTD2 | SPI0_SOUT | SPI | -+-------+-----------------+---------------------------+ -| PTD3 | SPI0_SIN | SPI | -+-------+-----------------+---------------------------+ -| PTE24 | I2C0_SCL | I2C / FXOS8700 | -+-------+-----------------+---------------------------+ -| PTE25 | I2C0_SDA | I2C / FXOS8700 | -+-------+-----------------+---------------------------+ -| PTA5 | MII0_RXER | Ethernet | -+-------+-----------------+---------------------------+ -| PTA12 | MII0_RXD1 | Ethernet | -+-------+-----------------+---------------------------+ -| PTA13 | MII0_RXD0 | Ethernet | -+-------+-----------------+---------------------------+ -| PTA14 | MII0_RXDV | Ethernet | -+-------+-----------------+---------------------------+ -| PTA15 | MII0_TXEN | Ethernet | -+-------+-----------------+---------------------------+ -| PTA16 | MII0_TXD0 | Ethernet | -+-------+-----------------+---------------------------+ -| PTA17 | MII0_TXD1 | Ethernet | -+-------+-----------------+---------------------------+ -| PTA28 | MII0_TXER | Ethernet | -+-------+-----------------+---------------------------+ -| PTB0 | MII0_MDIO | Ethernet | -+-------+-----------------+---------------------------+ -| PTB1 | MII0_MDC | Ethernet | -+-------+-----------------+---------------------------+ -| PTC16 | ENET0_1588_TMR0 | Ethernet | -+-------+-----------------+---------------------------+ -| PTC17 | ENET0_1588_TMR1 | Ethernet | -+-------+-----------------+---------------------------+ -| PTC18 | ENET0_1588_TMR2 | Ethernet | -+-------+-----------------+---------------------------+ -| PTC19 | ENET0_1588_TMR3 | Ethernet | -+-------+-----------------+---------------------------+ - -.. note:: - Do not enable Ethernet and UART BT HCI simultaneously because they conflict - on PTC16-17. - -System Clock -============ - -The K64F SoC is configured to use the 50 MHz external oscillator on the board -with the on-chip PLL to generate a 120 MHz system clock. - -Serial Port -=========== - -The K64F SoC has six UARTs. One is configured for the console, another for BT -HCI, and the remaining are not used. - -USB -=== - -The K64F SoC has a USB OTG (USBOTG) controller that supports both -device and host functions through its micro USB connector (K64F USB). -Only USB device function is supported in Zephyr at the moment. - -CAN -=== - -The FRDM-K64F board does not come with an onboard CAN transceiver. In order to -use the CAN bus, an external CAN bus transceiver must be connected to ``PTB18`` -(``CAN0_TX``) and ``PTB19`` (``CAN0_RX``). - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Early versions of this board have an outdated version of the OpenSDA bootloader -and require an update. Please see the `DAPLink Bootloader Update`_ page for -instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. - -.. tabs:: - - .. group-tab:: OpenSDA DAPLink Onboard (Recommended) - - Install the :ref:`linkserver-debug-host-tools` and make sure they are in your - search path. LinkServer works with the default CMSIS-DAP firmware included in - the on-board debugger. - - Linkserver is the default for this board, ``west flash`` and ``west debug`` will - call the linkserver runner. - - .. code-block:: console - - west flash - - Alternatively, pyOCD can be used to flash and debug the board by using the - ``-r pyocd`` option with West. pyOCD is installed when you complete the - :ref:`gs_python_deps` step in the Getting Started Guide. The runners supported - by NXP are LinkServer and JLink. pyOCD is another potential option, but NXP - does not test or support the pyOCD runner. - - - .. group-tab:: OpenSDA JLink Onboard - - Install the :ref:`jlink-debug-host-tools` and make sure they are in your search - path. - - The version of J-Link firmware to program to the board depends on the version - of the DAPLink bootloader. Refer to `OpenSDA Serial and Debug Adapter`_ for - more details. On this page, change the pull-down menu for "Choose your board to - start" to FRDM-K64F, and review the section "To update your board with OpenSDA - applications". Note that Segger does provide an OpenSDA J-Link Board-Specific - Firmware for this board, however it is not compatible with the DAPLink - bootloader. After downloading the appropriate J-Link firmware, follow the - instructions in :ref:`opensda-jlink-onboard-debug-probe` to program to the - board. - - Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and - ``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the - default runner to J-Link: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k64f - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J26. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k64f - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_k64f - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k64f - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_k64f - -Troubleshooting -=============== - -If pyocd raises an uncaught ``DAPAccessIntf.TransferFaultError()`` exception -when you try to flash or debug, it's possible that the K64F flash may have been -locked by a corrupt application. You can unlock it with the following sequence -of pyocd commands: - -.. code-block:: console - - $ pyocd cmd - 0001915:WARNING:target_kinetis:Forcing halt on connect in order to gain control of device - Connected to K64F [Halted]: 0240000026334e450028400d5e0e000e4eb1000097969900 - >>> unlock - 0016178:WARNING:target_kinetis:K64F secure state: unlocked successfully - >>> reinit - 0034584:WARNING:target_kinetis:Forcing halt on connect in order to gain control of device - >>> load build/zephyr/zephyr.bin - [====================] 100% - >>> reset - Resetting target - >>> quit - -.. _FRDM-K64F Website: - https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F - -.. _FRDM-K64F User Guide: - https://www.nxp.com/webapp/Download?colCode=FRDMK64FUG - -.. _FRDM-K64F Schematics: - https://www.nxp.com/webapp/Download?colCode=FRDM-K64F-SCH-E4 - -.. _K64F Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k6x-ethernet/kinetis-k64-120-mhz-256kb-sram-microcontrollers-mcus-based-on-arm-cortex-m4-core:K64_120 - -.. _K64F Datasheet: - https://www.nxp.com/docs/en/data-sheet/K64P144M120SF5.pdf - -.. _K64F Reference Manual: - https://www.nxp.com/docs/en/reference-manual/K64P144M120SF5RM.pdf - -.. _DAPLink Bootloader Update: - https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ - -.. _OpenSDA DAPLink FRDM-K64F Firmware: - https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk64f_if_crc_legacy_0x5000.bin - -.. _OpenSDA Serial and Debug Adapter: - https://www.nxp.com/design/microcontrollers-developer-resources/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA#FRDM-K64F - -Experimental ENET Driver -======================== - -Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new -driver with binding `nxp,enet`, which is experimental and undergoing development, but will have -enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. - -To build for this EVK with the new driver, include the experimental overlay to west build with -the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/frdm_k82f/Kconfig.board b/boards/arm/frdm_k82f/Kconfig.board deleted file mode 100644 index 2c18f441b53..00000000000 --- a/boards/arm/frdm_k82f/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# FRDM-K82F board configuration - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_K82F - bool "NXP FRDM-K82F" - depends on SOC_SERIES_KINETIS_K8X - select SOC_PART_NUMBER_MK82FN256VLL15 diff --git a/boards/arm/frdm_k82f/Kconfig.defconfig b/boards/arm/frdm_k82f/Kconfig.defconfig deleted file mode 100644 index 377b08c1be4..00000000000 --- a/boards/arm/frdm_k82f/Kconfig.defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# FRDM-K82F board - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FRDM_K82F - -config BOARD - default "frdm_k82f" - -config OSC_XTAL0_FREQ - default 12000000 - -config MCG_PRDIV0 - default 0x0 - -config MCG_VDIV0 - default 0x4 - -config MCG_FCRDIV - default 1 - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -endif # BOARD_FRDM_K82F diff --git a/boards/arm/frdm_k82f/doc/index.rst b/boards/arm/frdm_k82f/doc/index.rst deleted file mode 100644 index 239201f2a6c..00000000000 --- a/boards/arm/frdm_k82f/doc/index.rst +++ /dev/null @@ -1,254 +0,0 @@ -.. _frdm_k82f: - -NXP FRDM-K82F -############## - -Overview -******** - -The FRDM-K82F is a low-cost development platform for Kinetis K80, K81, -and K82 MCUs. - -- Form-factor compatible with the Arduino R3 pin layout -- Peripherals enable rapid prototyping, including a six-axis digital - accelerometer and magnetometer to create full eCompass capabilities, a - tri-colored LED and two user push-buttons for direct interaction, 2x32 Mb - QuadSPI external flash, FlexIO camera header, touchpads and headers for use - with Bluetooth and 2.4 GHz radio add-on modules -- OpenSDAv2.1, the NXP open source hardware embedded serial and debug adapter - running an open source bootloader, offers options for serial communication, - flash programming, and run-control debugging - -.. image:: frdm_k82f.jpg - :align: center - :alt: FRDM-K82F - -Hardware -******** - -- MK82FN256VLL15 MCU (150 MHz, 256 KB flash memory, 256 KB RAM, low-power, - crystal-less USB, and 100 Low profile Quad Flat Package (LQFP)) -- Dual role USB interface with micro-B USB connector -- RGB LED -- FXOS8700CQ accelerometer and magnetometer -- Two user push buttons -- 2x 32 Mb QSPI flash -- Flexible power supply option - OpenSDAv2.1 USB, Kinetis K82 USB, and external source -- Easy access to MCU input/output through Arduino R3 compatible I/O connectors -- Programmable OpenSDAv2.1 debug circuit supporting the CMSIS-DAP Interface - software that provides: - - - Mass storage device (MSD) flash programming interface - - CMSIS-DAP debug interface over a driver-less USB HID connection providing - run-control debugging and compatibility with IDE tools - - Virtual serial port interface - - Open source CMSIS-DAP software project - -- FlexIO header - -For more information about the K82F SoC and FRDM-K82F board: - -- `K82F Website`_ -- `K82F Datasheet`_ -- `K82F Reference Manual`_ -- `FRDM-K82F Website`_ -- `FRDM-K82F User Guide`_ -- `FRDM-K82F Schematics`_ - -Supported Features -================== - -The frdm_k82f board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the frdm_k64f board may have additional features -already supported, which can also be re-used on this frdm_k82f board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| FLASH | off-chip | QSPI flash | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FTFA | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/frdm_k82f/frdm_k82f_defconfig`` - -Other hardware features are not currently supported by the port. - -System Clock -============ - -The K82F SoC is configured to use the 12 MHz external oscillator on the board -with the on-chip PLL to generate a 120 MHz system clock. - -Serial Port -=========== - -The K82F SoC has five UARTs. One is configured for the console, the remaining -ones are not used. - -USB -=== - -The K82F SoC has a USB OTG (USBOTG) controller that supports both -device and host functions through its micro USB connector (J11). -Only USB device function is supported in Zephyr at the moment. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Early versions of this board have an outdated version of the OpenSDA bootloader -and require an update. Please see the `DAPLink Bootloader Update`_ page for -instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. - -Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) ------------------------------------------------------------------- - -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program -the `OpenSDA DAPLink FRDM-K82F Firmware`_. - -Option 2: :ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Firmware for FRDM-K82F`_. - -Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and -``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the -default runner from pyOCD to J-Link: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k82f - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J5. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k82f - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! frdm_k82f - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k82f - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! frdm_k82f - -.. _FRDM-K82F Website: - https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k82-k81-and-k80-mcus:FRDM-K82F - -.. _FRDM-K82F User Guide: - https://www.nxp.com/webapp/Download?colCode=FRDMK82FUG - -.. _FRDM-K82F Schematics: - https://www.nxp.com/downloads/en/schematics/FRDM-K82F-SCH.pdf - -.. _K82F Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k8x-secure/kinetis-k82-150-mhz-hw-cryptographic-co-processor-quadspi-microcontrollers-mcus-based-on-arm-cortex-m4-core:K82_150 - -.. _K82F Datasheet: - https://www.nxp.com/docs/en/data-sheet/K82P121M150SF5.pdf - -.. _K82F Reference Manual: - https://www.nxp.com/webapp/Download?colCode=K82P121M150SF5RM - -.. _DAPLink Bootloader Update: - https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ - -.. _OpenSDA DAPLink FRDM-K82F Firmware: - https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk82f_if_crc_legacy_0x8000.bin - -.. _OpenSDA J-Link Firmware for FRDM-K82F: - https://www.segger.com/downloads/jlink/OpenSDA_FRDM-K82F diff --git a/boards/arm/frdm_kl25z/Kconfig.board b/boards/arm/frdm_kl25z/Kconfig.board deleted file mode 100644 index 9a2a4184115..00000000000 --- a/boards/arm/frdm_kl25z/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# FRDM-KL25Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_KL25Z - bool "NXP FRDM-KL25Z" - depends on SOC_SERIES_KINETIS_KL2X - select SOC_PART_NUMBER_MKL25Z128VLK4 diff --git a/boards/arm/frdm_kl25z/Kconfig.defconfig b/boards/arm/frdm_kl25z/Kconfig.defconfig deleted file mode 100644 index c759787a219..00000000000 --- a/boards/arm/frdm_kl25z/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# FRDM-KL25Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FRDM_KL25Z - -config BOARD - default "frdm_kl25z" - -config OSC_XTAL0_FREQ - default 8000000 - -config MCG_PRDIV0 - default 0x01 - -config MCG_VDIV0 - default 0x00 - -config MCG_FRDIV - default 5 - -config MCG_FCRDIV - default 0 - -if FXOS8700 - -choice FXOS8700_MODE - default FXOS8700_MODE_ACCEL -endchoice - -endif # FXOS8700 - -endif # BOARD_FRDM_KL25Z diff --git a/boards/arm/frdm_kl25z/doc/index.rst b/boards/arm/frdm_kl25z/doc/index.rst deleted file mode 100644 index 22261a26e57..00000000000 --- a/boards/arm/frdm_kl25z/doc/index.rst +++ /dev/null @@ -1,251 +0,0 @@ -.. _frdm_kl25z: - -NXP FRDM-KL25Z -############## - -Overview -******** - -The Freedom KL25Z is an ultra-low-cost development platform for -Kinetis |reg| L Series KL1x (KL14/15) and KL2x (KL24/25) MCUs built -on ARM |reg| Cortex |reg|-M0+ processor. - -The FRDM-KL25Z features include easy access to MCU I/O, battery-ready, -low-power operation, a standard-based form factor with expansion board -options and a built-in debug interface for flash programming and run-control. - - -.. image:: frdm_kl25z.jpg - :align: center - :alt: FRDM-KL25Z - -Hardware -******** - -- MKL25Z128VLK4 MCU @ 48 MHz, 128 KB flash, 16 KB SRAM, USB OTG (FS), 80LQFP -- On board capacitive touch "slider", MMA8451Q accelerometer, and tri-color LED -- OpenSDA debug interface - -For more information about the KL25Z SoC and FRDM-KL25Z board: - -- `KL25Z Website`_ -- `KL25Z Datasheet`_ -- `KL25Z Reference Manual`_ -- `FRDM-KL25Z Website`_ -- `FRDM-KL25Z User Guide`_ -- `FRDM-KL25Z Schematics`_ - -Supported Features -================== - -The frdm_kl25z board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/frdm_kl25z/frdm_kl25z_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The KL25Z SoC has five pairs of pinmux/gpio controllers, and all are currently enabled -(PORTA/GPIOA, PORTB/GPIOB, PORTC/GPIOC, PORTD/GPIOD, and PORTE/GPIOE) for the FRDM-KL25Z board. - -+-------+-------------+---------------------------+ -| Name | Function | Usage | -+=======+=============+===========================+ -| PTB2 | ADC | ADC0 channel 12 | -+-------+-------------+---------------------------+ -| PTB18 | GPIO | Red LED | -+-------+-------------+---------------------------+ -| PTB19 | GPIO | Green LED | -+-------+-------------+---------------------------+ -| PTD1 | GPIO | Blue LED | -+-------+-------------+---------------------------+ -| PTA1 | UART0_RX | UART Console | -+-------+-------------+---------------------------+ -| PTA2 | UART0_TX | UART Console | -+-------+-------------+---------------------------+ -| PTE24 | I2C0_SCL | I2C | -+-------+-------------+---------------------------+ -| PTE25 | I2C0_SDA | I2C | -+-------+-------------+---------------------------+ - - -System Clock -============ - -The KL25Z SoC is configured to use the 8 MHz external oscillator on the board -with the on-chip FLL to generate a 48 MHz system clock. - -Serial Port -=========== - -The KL25Z UART0 is used for the console. - -USB -=== - -The KL25Z SoC has a USB OTG (USBOTG) controller that supports both -device and host functions through its mini USB connector (USB KL25Z). -Only USB device function is supported in Zephyr at the moment. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Early versions of this board have an outdated version of the OpenSDA bootloader -and require an update. Please see the `DAPLink Bootloader Update`_ page for -instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. - -Option 1: Linkserver: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) ------------------------------------------------------------------------------- - - Install the :ref:`linkserver-debug-host-tools` and make sure they are in your - search path. LinkServer works with the CMSIS-DAP debug firmware. Please follow the - instructions on :ref:`opensda-daplink-onboard-debug-probe` and select the latest revision - of the firmware image. - - Linkserver is the default for this board, ``west flash`` and ``west debug`` will - call the linkserver runner. - - .. code-block:: console - - west flash - west debug - -Option 2: :ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link FRDM-KL25Z Firmware`_. - -Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and -``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the -default runner from pyOCD to J-Link: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kl25z - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Note: ------ - -The runners supported by NXP are LinkServer and JLink. pyOCD is another potential option, -but NXP does not test or support the pyOCD runner. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J7. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kl25z - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_kl25z - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kl25z - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_kl25z - -.. _FRDM-KL25Z Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/l-seriesultra-low-powerm0-plus/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z - -.. _FRDM-KL25Z User Guide: - https://www.nxp.com/webapp/Download?colCode=FRDMKL25ZUM - -.. _FRDM-KL25Z Schematics: - https://www.nxp.com/downloads/en/schematics/FRDM-KL25Z_SCH_REV_E.pdf - -.. _KL25Z Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/l-seriesultra-low-powerm0-plus/kinetis-kl2x-72-96mhz-usb-ultra-low-power-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KL2x?&l - -.. _KL25Z Datasheet: - https://www.nxp.com/docs/en/data-sheet/KL25P80M48SF0.pdf - -.. _KL25Z Reference Manual: - https://www.nxp.com/webapp/Download?colCode=KL25P80M48SF0RM - -.. _DAPLink Bootloader Update: - https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ - -.. _OpenSDA DAPLink FRDM-KL25Z Firmware: - https://www.nxp.com/downloads/en/ide-debug-compile-build-tools/OpenSDAv2.2_DAPLink_frdmkl25z_rev0242.zip - -.. _OpenSDA J-Link FRDM-KL25Z Firmware: - https://www.segger.com/downloads/jlink/OpenSDA_FRDM-KL25Z diff --git a/boards/arm/frdm_kw41z/Kconfig.board b/boards/arm/frdm_kw41z/Kconfig.board deleted file mode 100644 index 7d4a5849f8b..00000000000 --- a/boards/arm/frdm_kw41z/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# FRDM-KW41Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_KW41Z - bool "NXP FRDM-KW41Z" - depends on SOC_SERIES_KINETIS_KWX - select SOC_PART_NUMBER_MKW41Z512VHT4 diff --git a/boards/arm/frdm_kw41z/Kconfig.defconfig b/boards/arm/frdm_kw41z/Kconfig.defconfig deleted file mode 100644 index 82f086cd7a5..00000000000 --- a/boards/arm/frdm_kw41z/Kconfig.defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# FRDM-KW41Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FRDM_KW41Z - -config BOARD - default "frdm_kw41z" - -config OSC_XTAL0_FREQ - default 32000000 - -config MCG_FRDIV - default 5 - -config MCG_FCRDIV - default 0 - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -choice ADC_MCUX_ADC16_VREF - default ADC_MCUX_ADC16_VREF_ALTERNATE -endchoice - -endif # BOARD_FRDM_KW41Z diff --git a/boards/arm/frdm_kw41z/doc/index.rst b/boards/arm/frdm_kw41z/doc/index.rst deleted file mode 100644 index cf1557b136b..00000000000 --- a/boards/arm/frdm_kw41z/doc/index.rst +++ /dev/null @@ -1,260 +0,0 @@ -.. _frdm_kw41z: - -NXP FRDM-KW41Z -############## - -Overview -******** - -The FRDM-KW41Z is a development kit enabled by the Kinetis |reg| W series -KW41Z/31Z/21Z (KW41Z) family built on ARM |reg| Cortex |reg|-M0+ processor with -integrated 2.4 GHz transceiver supporting Bluetooth |reg| Smart/Bluetooth -|reg| Low Energy -(BLE) v4.2, Generic FSK, IEEE |reg| 802.15.4 and Thread. - -The FRDM-KW41Z kit contains two Freedom boards that can be used as a -development board or a shield to connect to a host processor. The FRDM-KW41Z is -form-factor compatible with the Arduino |trade| R3 pin layout for more expansion -options. - -The FRDM-KW41Z highly-sensitive, optimized 2.4 GHz radio features a PCB -F-antenna which can be bypassed to test via SMA connection, multiple power -supply options, push/capacitive touch buttons, switches, LEDs and integrated -sensors. - -.. image:: frdm_kw41z.jpg - :align: center - :alt: FRDM-KW41Z - -Hardware -******** - -- Can be configured as Host or Shield for connection to Host Processor -- Supports all DC-DC configurations (Buck, Boost, Bypass) -- PCB inverted F-type antenna -- SMA RF Connector -- RF regulatory certified -- Serial Flash for OTA firmware upgrades -- On board NXP FXOS8700CQ digital sensor, 3D Accelerometer ( |plusminus| 2g/ - |plusminus| 4g/ |plusminus| 8g) + 3D - Magnetometer -- OpenSDA and JTAG debug - -For more information about the KW41Z SoC and FRDM-KW41Z board: - -- `KW41Z Website`_ -- `KW41Z Datasheet`_ -- `KW41Z Reference Manual`_ -- `FRDM-KW41Z Website`_ -- `FRDM-KW41Z User Guide`_ -- `FRDM-KW41Z Schematics`_ - -Supported Features -================== - -The frdm_kw41z board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling: | -| | | fxos8700 trigger | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | tpm | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FTFA | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/frdm_kw41z/frdm_kw41z_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The KW41Z SoC has three pairs of pinmux/gpio controllers, but only two are -currently enabled (PORTA/GPIOA and PORTC/GPIOC) for the FRDM-KW41Z board. - -+-------+-------------+---------------------------+ -| Name | Function | Usage | -+=======+=============+===========================+ -| PTC1 | GPIO | Red LED / FXOS8700 INT1 | -+-------+-------------+---------------------------+ -| PTA19 | GPIO | Green LED | -+-------+-------------+---------------------------+ -| PTA18 | GPIO | Blue LED | -+-------+-------------+---------------------------+ -| PTB2 | ADC | ADC0 channel 3 | -+-------+-------------+---------------------------+ -| PTC2 | I2C1_SCL | I2C / FXOS8700 | -+-------+-------------+---------------------------+ -| PTC3 | I2C1_SDA | I2C / FXOS8700 | -+-------+-------------+---------------------------+ -| PTC4 | GPIO | SW3 | -+-------+-------------+---------------------------+ -| PTC5 | GPIO | SW4 | -+-------+-------------+---------------------------+ -| PTC6 | LPUART0_RX | UART Console | -+-------+-------------+---------------------------+ -| PTC7 | LPUART0_TX | UART Console | -+-------+-------------+---------------------------+ -| PTC16 | SPI0_SCK | SPI | -+-------+-------------+---------------------------+ -| PTC17 | SPI0_SOUT | SPI | -+-------+-------------+---------------------------+ -| PTC18 | SPI0_SIN | SPI | -+-------+-------------+---------------------------+ -| PTC19 | SPI0_PCS0 | SPI | -+-------+-------------+---------------------------+ - -System Clock -============ - -The KW41Z SoC is configured to use the 32 MHz external oscillator on the board -with the on-chip FLL to generate a 40 MHz system clock. - -Serial Port -=========== - -The KW41Z SoC has one UART, which is used for the console. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) ------------------------------------------------------------------- - -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program -the `OpenSDA DAPLink FRDM-KW41Z Firmware`_. - -Option 2: :ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link FRDM-KW41Z Firmware`_. - -Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and -``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the -default runner from pyOCD to J-Link: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kw41z - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J6. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kw41z - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_kw41z - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kw41z - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_kw41z - -.. _FRDM-KW41Z Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/freedom-development-kit-for-kinetis-kw41z-31z-21z-mcus:FRDM-KW41Z - -.. _FRDM-KW41Z User Guide: - https://www.nxp.com/webapp/Download?colCode=FRDMKW41ZUG - -.. _FRDM-KW41Z Schematics: - https://www.nxp.com/webapp/Download?colCode=FRDM-KW41Z-SCH - -.. _KW41Z Website: - https://www.nxp.com/products/wireless/zigbee/kinetis-kw41z-2.4-ghz-dual-mode-bluetooth-low-energy-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW41Z - -.. _KW41Z Datasheet: - https://www.nxp.com/docs/en/data-sheet/MKW41Z512.pdf - -.. _KW41Z Reference Manual: - https://www.nxp.com/webapp/Download?colCode=MKW41Z512RM - -.. _OpenSDA DAPLink FRDM-KW41Z Firmware: - https://www.nxp.com/downloads/en/reference-applications/OpenSDAv2.2_DAPLink_frdmkw41z_rev0241.zip - -.. _OpenSDA J-Link FRDM-KW41Z Firmware: - https://www.segger.com/downloads/jlink/OpenSDA_FRDM-KW41Z diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig b/boards/arm/fvp_base_revc_2xaemv8a/Kconfig similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/Kconfig rename to boards/arm/fvp_base_revc_2xaemv8a/Kconfig diff --git a/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.defconfig b/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.defconfig new file mode 100644 index 00000000000..3f1e48df8cc --- /dev/null +++ b/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2021 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FVP_BASE_REVC_2XAEMV8A + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_FVP_BASE_REVC_2XAEMV8A diff --git a/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.fvp_base_revc_2xaemv8a b/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.fvp_base_revc_2xaemv8a new file mode 100644 index 00000000000..874f1dba015 --- /dev/null +++ b/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.fvp_base_revc_2xaemv8a @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FVP_BASE_REVC_2XAEMV8A + select SOC_SERIES_FVP_AEMV8A + select SOC_FVP_BASE_REVC_2XAEMV8A diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/board.cmake b/boards/arm/fvp_base_revc_2xaemv8a/board.cmake similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/board.cmake rename to boards/arm/fvp_base_revc_2xaemv8a/board.cmake diff --git a/boards/arm/fvp_base_revc_2xaemv8a/board.yml b/boards/arm/fvp_base_revc_2xaemv8a/board.yml new file mode 100644 index 00000000000..8c881c9d86a --- /dev/null +++ b/boards/arm/fvp_base_revc_2xaemv8a/board.yml @@ -0,0 +1,9 @@ +board: + name: fvp_base_revc_2xaemv8a + vendor: arm + socs: + - name: fvp_base_revc_2xaemv8a + variants: + - name: smp + variants: + - name: ns diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/doc/index.rst b/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/doc/index.rst rename to boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts rename to boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml rename to boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig similarity index 77% rename from boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig rename to boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig index 159682f9295..07b3195104a 100644 --- a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig +++ b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2021 Carlo Caione # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_FVP_AEMV8A=y -CONFIG_SOC_FVP_BASE_REVC_2XAEMV8A=y -CONFIG_BOARD_FVP_BASE_REVC_2XAEMV8A=y - CONFIG_XIP=n CONFIG_THREAD_STACK_INFO=y diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns.dts b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.dts similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns.dts rename to boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.dts diff --git a/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.yaml b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.yaml new file mode 100644 index 00000000000..e64ed9f8e7c --- /dev/null +++ b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +identifier: fvp_base_revc_2xaemv8a//smp/ns +name: FVP Emulation FVP_Base_RevC-2xAEMvA (SMP) +arch: arm64 +type: sim +toolchain: + - zephyr + - cross-compile +ram: 2048 +flash: 64 +vendor: arm diff --git a/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns_defconfig b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns_defconfig new file mode 100644 index 00000000000..31973c6ff16 --- /dev/null +++ b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns_defconfig @@ -0,0 +1,33 @@ +# Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_THREAD_STACK_INFO=y + +# Enable Timer and Sys clock +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_ARM_ARCH_TIMER=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable TFA +CONFIG_ARMV8_A_NS=y +CONFIG_BUILD_WITH_TFA=y + +# Enable SMP +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 +CONFIG_CACHE_MANAGEMENT=y +CONFIG_TIMEOUT_64BIT=y +CONFIG_ARM64_SET_VMPIDR_EL2=y +CONFIG_MAX_THREAD_BYTES=3 + +# PSCI is supported +CONFIG_PM_CPU_OPS=y diff --git a/boards/arm/fvp_baser_aemv8r/Kconfig.defconfig b/boards/arm/fvp_baser_aemv8r/Kconfig.defconfig new file mode 100644 index 00000000000..980b88283d4 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FVP_BASER_AEMV8R + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_FVP_BASER_AEMV8R diff --git a/boards/arm/fvp_baser_aemv8r/Kconfig.fvp_baser_aemv8r b/boards/arm/fvp_baser_aemv8r/Kconfig.fvp_baser_aemv8r new file mode 100644 index 00000000000..059a4ba6948 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/Kconfig.fvp_baser_aemv8r @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FVP_BASER_AEMV8R + select SOC_FVP_AEMV8R_AARCH64 if BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64 || BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64_SMP + select SOC_FVP_AEMV8R_AARCH32 if BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32 || BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32_SMP diff --git a/boards/arm/fvp_baser_aemv8r/board.cmake b/boards/arm/fvp_baser_aemv8r/board.cmake new file mode 100644 index 00000000000..f7753bc5099 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/board.cmake @@ -0,0 +1,74 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS armfvp) +set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R) +set(ARMFVP_MIN_VERSION 11.16.16) + +if(CONFIG_BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64) + set(ARMFVP_FLAGS + -C cluster0.has_aarch64=1 + -C cluster0.VMSA_supported=0 + -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS} + -C cluster0.gicv3.cpuintf-mmap-access-level=2 + -C cluster0.gicv3.SRE-enable-action-on-mmap=2 + -C cluster0.gicv3.SRE-EL2-enable-RAO=1 + -C cluster0.gicv3.extended-interrupt-range-support=1 + -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1 + -C gic_distributor.has-two-security-states=0 + -C bp.refcounter.non_arch_start_at_default=1 + # UART0 config + -C bp.pl011_uart0.out_file=- + -C bp.pl011_uart0.unbuffered_output=1 + -C bp.terminal_0.start_telnet=0 + # UART1 config + -C bp.pl011_uart1.out_file=- + -C bp.pl011_uart1.unbuffered_output=1 + -C bp.terminal_1.start_telnet=0 + # UART2 config + -C bp.pl011_uart2.out_file=- + -C bp.pl011_uart2.unbuffered_output=1 + -C bp.terminal_2.start_telnet=0 + # UART3 config + -C bp.pl011_uart3.out_file=- + -C bp.pl011_uart3.unbuffered_output=1 + -C bp.terminal_3.start_telnet=0 + + -C bp.vis.disable_visualisation=1 + -C bp.vis.rate_limit-enable=0 + -C cache_state_modelled=1 + ) +elseif(CONFIG_BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32) + set(ARMFVP_FLAGS + -C cluster0.has_aarch64=0 + -C cluster0.VMSA_supported=0 + -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS} + -C cluster0.gicv3.cpuintf-mmap-access-level=2 + -C cluster0.gicv3.SRE-enable-action-on-mmap=2 + -C cluster0.gicv3.SRE-EL2-enable-RAO=1 + -C cluster0.gicv3.extended-interrupt-range-support=1 + -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1 + -C gic_distributor.has-two-security-states=0 + -C bp.refcounter.non_arch_start_at_default=1 + # UART0 config + -C bp.pl011_uart0.out_file=- + -C bp.pl011_uart0.unbuffered_output=1 + -C bp.terminal_0.start_telnet=0 + # UART1 config + -C bp.pl011_uart1.out_file=- + -C bp.pl011_uart1.unbuffered_output=1 + -C bp.terminal_1.start_telnet=0 + # UART2 config + -C bp.pl011_uart2.out_file=- + -C bp.pl011_uart2.unbuffered_output=1 + -C bp.terminal_2.start_telnet=0 + # UART3 config + -C bp.pl011_uart3.out_file=- + -C bp.pl011_uart3.unbuffered_output=1 + -C bp.terminal_3.start_telnet=0 + + -C bp.vis.disable_visualisation=1 + -C bp.vis.rate_limit-enable=0 + -C cache_state_modelled=0 + ) +endif() diff --git a/boards/arm/fvp_baser_aemv8r/board.yml b/boards/arm/fvp_baser_aemv8r/board.yml new file mode 100644 index 00000000000..f80eb3a6ed0 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/board.yml @@ -0,0 +1,10 @@ +board: + name: fvp_baser_aemv8r + vendor: arm + socs: + - name: fvp_aemv8r_aarch64 + variants: + - name: 'smp' + - name: fvp_aemv8r_aarch32 + variants: + - name: 'smp' diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/doc/index.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst similarity index 100% rename from boards/arm/fvp_baser_aemv8r_aarch32/doc/index.rst rename to boards/arm/fvp_baser_aemv8r/doc/aarch32.rst diff --git a/boards/arm64/fvp_baser_aemv8r/doc/index.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/index.rst rename to boards/arm/fvp_baser_aemv8r/doc/aarch64.rst diff --git a/boards/arm64/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst b/boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst rename to boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst diff --git a/boards/arm64/fvp_baser_aemv8r/doc/images/DS-debug-working.jpg b/boards/arm/fvp_baser_aemv8r/doc/images/DS-debug-working.jpg similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/images/DS-debug-working.jpg rename to boards/arm/fvp_baser_aemv8r/doc/images/DS-debug-working.jpg diff --git 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a/boards/arm64/fvp_baser_aemv8r/doc/images/create-new-model-configuration.jpg b/boards/arm/fvp_baser_aemv8r/doc/images/create-new-model-configuration.jpg similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/images/create-new-model-configuration.jpg rename to boards/arm/fvp_baser_aemv8r/doc/images/create-new-model-configuration.jpg diff --git a/boards/arm64/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-path.jpg b/boards/arm/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-path.jpg similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-path.jpg rename to boards/arm/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-path.jpg diff --git a/boards/arm64/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-use-V8R64-Generic.jpg b/boards/arm/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-use-V8R64-Generic.jpg similarity index 100% rename from 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similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/images/version-info.jpg rename to boards/arm/fvp_baser_aemv8r/doc/images/version-info.jpg diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.dts b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.dts similarity index 100% rename from boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.dts rename to boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.dts diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml new file mode 100644 index 00000000000..0f7b38d648c --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# Copyright (c) 2022 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch32 +name: FVP Emulation FVP_BaseR_AEMv8R AArch32 +arch: arm +type: sim +toolchain: + - zephyr + - cross-compile +ram: 2048 +flash: 64 +testing: + timeout_multiplier: 15 diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_defconfig b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_defconfig new file mode 100644 index 00000000000..bf9d919c6a3 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# Copyright (c) 2022 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y + +CONFIG_ISR_STACK_SIZE=1024 +CONFIG_THREAD_STACK_INFO=y + +# Enable Timer and Sys clock +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_ARM_ARCH_TIMER=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE=n diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.dts b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.dts new file mode 100644 index 00000000000..b33ad9ca128 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.dts @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "fvp_baser_aemv8r_fvp_aemv8r_aarch32.dts" diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml new file mode 100644 index 00000000000..d056a315af6 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp +name: FVP Emulation FVP_BaseR_AEMv8R AArch32 (SMP) +arch: arm +type: sim +toolchain: + - zephyr + - cross-compile +ram: 2048 +flash: 64 +testing: + timeout_multiplier: 25 diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig new file mode 100644 index 00000000000..a320c3486f7 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_USE_SWITCH=y +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.dts similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts rename to boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.dts diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml new file mode 100644 index 00000000000..501a6b89374 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch64 +name: FVP Emulation FVP_BaseR_AEMv8R +arch: arm64 +type: sim +toolchain: + - zephyr + - cross-compile +ram: 2048 +flash: 64 +testing: + timeout_multiplier: 8 +vendor: arm diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_defconfig b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_defconfig new file mode 100644 index 00000000000..fb029e44ab5 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +CONFIG_THREAD_STACK_INFO=y + +# Enable Timer and Sys clock +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_ARM_ARCH_TIMER=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.dts b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.dts new file mode 100644 index 00000000000..6e57c4d83bc --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.dts @@ -0,0 +1,6 @@ +/* + * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "fvp_baser_aemv8r_fvp_aemv8r_aarch64.dts" diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml new file mode 100644 index 00000000000..fa1baf892d9 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch64/smp +name: FVP Emulation FVP_BaseR_AEMv8R (SMP) +arch: arm64 +type: sim +toolchain: + - zephyr + - cross-compile +ram: 2048 +flash: 64 +supported: + - smp +testing: + timeout_multiplier: 20 +vendor: arm diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig new file mode 100644 index 00000000000..286fc28d189 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# Enable simulated CPU power management +CONFIG_SOC_FVP_AEMV8R_SIMULATE_CPU_PM=y +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=n +CONFIG_ARM64_SET_VMPIDR_EL2=y + +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 + +CONFIG_MAX_THREAD_BYTES=3 diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.board b/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.board deleted file mode 100644 index da1b202a128..00000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FVP_BASER_AEMV8R_AARCH32 - bool "FVP BaseR AEMv8R AArch32 simulation board" - depends on SOC_FVP_AEMV8R_AARCH32 diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.defconfig b/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.defconfig deleted file mode 100644 index 26231365882..00000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FVP_BASER_AEMV8R_AARCH32 - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "fvp_baser_aemv8r_aarch32" - -endif # BOARD_FVP_BASER_AEMV8R_AARCH32 diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/board.cmake b/boards/arm/fvp_baser_aemv8r_aarch32/board.cmake deleted file mode 100644 index 2007c20e5ca..00000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/board.cmake +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS armfvp) -set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R) - -set(ARMFVP_FLAGS - -C cluster0.has_aarch64=0 - -C cluster0.VMSA_supported=0 - -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS} - -C cluster0.gicv3.cpuintf-mmap-access-level=2 - -C cluster0.gicv3.SRE-enable-action-on-mmap=2 - -C cluster0.gicv3.SRE-EL2-enable-RAO=1 - -C cluster0.gicv3.extended-interrupt-range-support=1 - -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1 - -C gic_distributor.has-two-security-states=0 - -C bp.refcounter.non_arch_start_at_default=1 - # UART0 config - -C bp.pl011_uart0.out_file=- - -C bp.pl011_uart0.unbuffered_output=1 - -C bp.terminal_0.start_telnet=0 - # UART1 config - -C bp.pl011_uart1.out_file=- - -C bp.pl011_uart1.unbuffered_output=1 - -C bp.terminal_1.start_telnet=0 - # UART2 config - -C bp.pl011_uart2.out_file=- - -C bp.pl011_uart2.unbuffered_output=1 - -C bp.terminal_2.start_telnet=0 - # UART3 config - -C bp.pl011_uart3.out_file=- - -C bp.pl011_uart3.unbuffered_output=1 - -C bp.terminal_3.start_telnet=0 - - -C bp.vis.disable_visualisation=1 - -C bp.vis.rate_limit-enable=0 - -C cache_state_modelled=0 - ) diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.yaml b/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.yaml deleted file mode 100644 index 23fc5a434c2..00000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -identifier: fvp_baser_aemv8r_aarch32 -name: FVP Emulation FVP_BaseR_AEMv8R AArch32 -arch: arm -type: sim -toolchain: - - zephyr - - cross-compile -ram: 2048 -flash: 64 -testing: - timeout_multiplier: 15 diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_defconfig b/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_defconfig deleted file mode 100644 index 034a1ed5014..00000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_FVP_AEMV8R_AARCH32=y -CONFIG_SOC_FVP_AEMV8R_AARCH32=y -CONFIG_BOARD_FVP_BASER_AEMV8R_AARCH32=y -CONFIG_ARM_MPU=y - -CONFIG_ISR_STACK_SIZE=1024 -CONFIG_THREAD_STACK_INFO=y - -# Enable Timer and Sys clock -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_ARM_ARCH_TIMER=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE=n diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.dts b/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.dts deleted file mode 100644 index cdc0a933ba3..00000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include "fvp_baser_aemv8r_aarch32.dts" diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.yaml b/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.yaml deleted file mode 100644 index 0ecd14f9076..00000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -identifier: fvp_baser_aemv8r_aarch32_smp -name: FVP Emulation FVP_BaseR_AEMv8R AArch32 (SMP) -arch: arm -type: sim -toolchain: - - zephyr - - cross-compile -ram: 2048 -flash: 64 -testing: - timeout_multiplier: 25 diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp_defconfig b/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp_defconfig deleted file mode 100644 index 3f7f981b46e..00000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_FVP_AEMV8R_AARCH32=y -CONFIG_SOC_FVP_AEMV8R_AARCH32=y -CONFIG_BOARD_FVP_BASER_AEMV8R_AARCH32=y -CONFIG_ARM_MPU=y - -CONFIG_ISR_STACK_SIZE=1024 -CONFIG_THREAD_STACK_INFO=y - -# Enable Timer and Sys clock -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_ARM_ARCH_TIMER=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CACHE_MANAGEMENT=y - -CONFIG_USE_SWITCH=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=4 - -CONFIG_DCACHE=n diff --git a/boards/arm/gd32a503v_eval/Kconfig.board b/boards/arm/gd32a503v_eval/Kconfig.board deleted file mode 100644 index 827b0b4dcb8..00000000000 --- a/boards/arm/gd32a503v_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32A503V_EVAL - bool "GigaDevice GD32A503V-EVAL" - depends on SOC_GD32A503 diff --git a/boards/arm/gd32a503v_eval/Kconfig.defconfig b/boards/arm/gd32a503v_eval/Kconfig.defconfig deleted file mode 100644 index 7c0c1ad2b70..00000000000 --- a/boards/arm/gd32a503v_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32A503V_EVAL - -config BOARD - default "gd32a503v_eval" - -endif # BOARD_GD32A503V_EVAL diff --git a/boards/arm/gd32a503v_eval/gd32a503v_eval_defconfig b/boards/arm/gd32a503v_eval/gd32a503v_eval_defconfig deleted file mode 100644 index dfcc85ee1e1..00000000000 --- a/boards/arm/gd32a503v_eval/gd32a503v_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32A50X=y -CONFIG_SOC_GD32A503=y -CONFIG_BOARD_GD32A503V_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32e103v_eval/Kconfig.board b/boards/arm/gd32e103v_eval/Kconfig.board deleted file mode 100644 index 848f4d82a6a..00000000000 --- a/boards/arm/gd32e103v_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021, YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32E103V_EVAL - bool "GigaDevice GD32E103V Evaluation Kit" - depends on SOC_GD32E103 diff --git a/boards/arm/gd32e103v_eval/Kconfig.defconfig b/boards/arm/gd32e103v_eval/Kconfig.defconfig deleted file mode 100644 index 4681d2b2464..00000000000 --- a/boards/arm/gd32e103v_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32E103V_EVAL - -config BOARD - default "gd32e103v_eval" - -endif # BOARD_GD32E103V_EVAL diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval_defconfig b/boards/arm/gd32e103v_eval/gd32e103v_eval_defconfig deleted file mode 100644 index 6af9eba773f..00000000000 --- a/boards/arm/gd32e103v_eval/gd32e103v_eval_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021, YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32E10X=y -CONFIG_SOC_GD32E103=y -CONFIG_BOARD_GD32E103V_EVAL=y - -CONFIG_GD32_HXTAL_8MHZ=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/gd32e507v_start/Kconfig.board b/boards/arm/gd32e507v_start/Kconfig.board deleted file mode 100644 index 427e3c414ac..00000000000 --- a/boards/arm/gd32e507v_start/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32E507V_START - bool "GigaDevice GD32E507V-START" - depends on SOC_GD32E507 diff --git a/boards/arm/gd32e507v_start/Kconfig.defconfig b/boards/arm/gd32e507v_start/Kconfig.defconfig deleted file mode 100644 index c5ca16fd25b..00000000000 --- a/boards/arm/gd32e507v_start/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32E507V_START - -config BOARD - default "gd32e507v_start" - -endif # BOARD_GD32E507V_START diff --git a/boards/arm/gd32e507v_start/gd32e507v_start_defconfig b/boards/arm/gd32e507v_start/gd32e507v_start_defconfig deleted file mode 100644 index 581cdd712b1..00000000000 --- a/boards/arm/gd32e507v_start/gd32e507v_start_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32E50X=y -CONFIG_SOC_GD32E507=y -CONFIG_BOARD_GD32E507V_START=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32e507z_eval/Kconfig.board b/boards/arm/gd32e507z_eval/Kconfig.board deleted file mode 100644 index 0b9208ff8b7..00000000000 --- a/boards/arm/gd32e507z_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32E507Z_EVAL - bool "GigaDevice GD32E507Z-EVAL" - depends on SOC_GD32E507 diff --git a/boards/arm/gd32e507z_eval/Kconfig.defconfig b/boards/arm/gd32e507z_eval/Kconfig.defconfig deleted file mode 100644 index 39e067ed59e..00000000000 --- a/boards/arm/gd32e507z_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32E507Z_EVAL - -config BOARD - default "gd32e507z_eval" - -endif # BOARD_GD32E507Z_EVAL diff --git a/boards/arm/gd32e507z_eval/gd32e507z_eval_defconfig b/boards/arm/gd32e507z_eval/gd32e507z_eval_defconfig deleted file mode 100644 index c6b1f6ad32c..00000000000 --- a/boards/arm/gd32e507z_eval/gd32e507z_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32E50X=y -CONFIG_SOC_GD32E507=y -CONFIG_BOARD_GD32E507Z_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f350r_eval/Kconfig.board b/boards/arm/gd32f350r_eval/Kconfig.board deleted file mode 100644 index b4fbc6635f7..00000000000 --- a/boards/arm/gd32f350r_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F350R_EVAL - bool "GigaDevice GD32F350R Evaluation Kit" - depends on SOC_GD32F350 diff --git a/boards/arm/gd32f350r_eval/Kconfig.defconfig b/boards/arm/gd32f350r_eval/Kconfig.defconfig deleted file mode 100644 index 1de5675fb9c..00000000000 --- a/boards/arm/gd32f350r_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F350R_EVAL - -config BOARD - default "gd32f350r_eval" - -endif # BOARD_GD32F350R_EVAL diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval_defconfig b/boards/arm/gd32f350r_eval/gd32f350r_eval_defconfig deleted file mode 100644 index dfb61c38eb2..00000000000 --- a/boards/arm/gd32f350r_eval/gd32f350r_eval_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F3X0=y -CONFIG_SOC_GD32F350=y -CONFIG_BOARD_GD32F350R_EVAL=y - - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/gd32f403z_eval/Kconfig.board b/boards/arm/gd32f403z_eval/Kconfig.board deleted file mode 100644 index 97273a13f99..00000000000 --- a/boards/arm/gd32f403z_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F403Z_EVAL - bool "GigaDevice GD32F403Z Evaluation Kit" - depends on SOC_GD32F403 diff --git a/boards/arm/gd32f403z_eval/Kconfig.defconfig b/boards/arm/gd32f403z_eval/Kconfig.defconfig deleted file mode 100644 index 39f1df8e537..00000000000 --- a/boards/arm/gd32f403z_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F403Z_EVAL - -config BOARD - default "gd32f403z_eval" - -endif # BOARD_GD32F403Z_EVAL diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig b/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig deleted file mode 100644 index 759c53a00ad..00000000000 --- a/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F403=y -CONFIG_SOC_GD32F403=y -CONFIG_BOARD_GD32F403Z_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f407v_start/Kconfig.board b/boards/arm/gd32f407v_start/Kconfig.board deleted file mode 100644 index 541f1642e93..00000000000 --- a/boards/arm/gd32f407v_start/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F407V_START - bool "GigaDevice GD32F407V-START" - depends on SOC_GD32F407 diff --git a/boards/arm/gd32f407v_start/Kconfig.defconfig b/boards/arm/gd32f407v_start/Kconfig.defconfig deleted file mode 100644 index 888179c2f62..00000000000 --- a/boards/arm/gd32f407v_start/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022, TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F407V_START - -config BOARD - default "gd32f407v_start" - -endif # BOARD_GD32F407V_START diff --git a/boards/arm/gd32f407v_start/gd32f407v_start_defconfig b/boards/arm/gd32f407v_start/gd32f407v_start_defconfig deleted file mode 100644 index 1b9e3ff5e18..00000000000 --- a/boards/arm/gd32f407v_start/gd32f407v_start_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F4XX=y -CONFIG_SOC_GD32F407=y -CONFIG_BOARD_GD32F407V_START=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f450i_eval/Kconfig.board b/boards/arm/gd32f450i_eval/Kconfig.board deleted file mode 100644 index 257da26fd03..00000000000 --- a/boards/arm/gd32f450i_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F450I_EVAL - bool "GigaDevice GD32F450I-EVAL" - depends on SOC_GD32F450 diff --git a/boards/arm/gd32f450i_eval/Kconfig.defconfig b/boards/arm/gd32f450i_eval/Kconfig.defconfig deleted file mode 100644 index 3d7624c751e..00000000000 --- a/boards/arm/gd32f450i_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F450I_EVAL - -config BOARD - default "gd32f450i_eval" - -endif # BOARD_GD32F450I_EVAL diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig b/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig deleted file mode 100644 index 57db7c521eb..00000000000 --- a/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F4XX=y -CONFIG_SOC_GD32F450=y -CONFIG_BOARD_GD32F450I_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f450v_start/Kconfig.board b/boards/arm/gd32f450v_start/Kconfig.board deleted file mode 100644 index 7bd8cfbab73..00000000000 --- a/boards/arm/gd32f450v_start/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F450V_START - bool "GigaDevice GD32F450V-START" - depends on SOC_GD32F450 diff --git a/boards/arm/gd32f450v_start/Kconfig.defconfig b/boards/arm/gd32f450v_start/Kconfig.defconfig deleted file mode 100644 index 3db890ec9d4..00000000000 --- a/boards/arm/gd32f450v_start/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F450V_START - -config BOARD - default "gd32f450v_start" - -endif # BOARD_GD32F450V_START diff --git a/boards/arm/gd32f450v_start/gd32f450v_start_defconfig b/boards/arm/gd32f450v_start/gd32f450v_start_defconfig deleted file mode 100644 index 0767cf26db1..00000000000 --- a/boards/arm/gd32f450v_start/gd32f450v_start_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F4XX=y -CONFIG_SOC_GD32F450=y -CONFIG_BOARD_GD32F450V_START=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f450z_eval/Kconfig.board b/boards/arm/gd32f450z_eval/Kconfig.board deleted file mode 100644 index 70ced416110..00000000000 --- a/boards/arm/gd32f450z_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F450Z_EVAL - bool "GigaDevice GD32F450Z-EVAL" - depends on SOC_GD32F450 diff --git a/boards/arm/gd32f450z_eval/Kconfig.defconfig b/boards/arm/gd32f450z_eval/Kconfig.defconfig deleted file mode 100644 index 5c2ecc08b51..00000000000 --- a/boards/arm/gd32f450z_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F450Z_EVAL - -config BOARD - default "gd32f450z_eval" - -endif # BOARD_GD32F450Z_EVAL diff --git a/boards/arm/gd32f450z_eval/gd32f450z_eval_defconfig b/boards/arm/gd32f450z_eval/gd32f450z_eval_defconfig deleted file mode 100644 index 59bc8e32ded..00000000000 --- a/boards/arm/gd32f450z_eval/gd32f450z_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F4XX=y -CONFIG_SOC_GD32F450=y -CONFIG_BOARD_GD32F450Z_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f470i_eval/Kconfig.board b/boards/arm/gd32f470i_eval/Kconfig.board deleted file mode 100644 index e860b81a403..00000000000 --- a/boards/arm/gd32f470i_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F470I_EVAL - bool "GigaDevice GD32F470I-EVAL" - depends on SOC_GD32F470 diff --git a/boards/arm/gd32f470i_eval/Kconfig.defconfig b/boards/arm/gd32f470i_eval/Kconfig.defconfig deleted file mode 100644 index 89cf5c68842..00000000000 --- a/boards/arm/gd32f470i_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F470I_EVAL - -config BOARD - default "gd32f470i_eval" - -endif # BOARD_GD32F470I_EVAL diff --git a/boards/arm/gd32f470i_eval/gd32f470i_eval_defconfig b/boards/arm/gd32f470i_eval/gd32f470i_eval_defconfig deleted file mode 100644 index 9a6f3a893d6..00000000000 --- a/boards/arm/gd32f470i_eval/gd32f470i_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F4XX=y -CONFIG_SOC_GD32F470=y -CONFIG_BOARD_GD32F470I_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32l233r_eval/Kconfig.board b/boards/arm/gd32l233r_eval/Kconfig.board deleted file mode 100644 index 9ef6680e915..00000000000 --- a/boards/arm/gd32l233r_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32L233R_EVAL - bool "GigaDevice GD32L233R Evaluation Kit" - depends on SOC_GD32L233 diff --git a/boards/arm/gd32l233r_eval/Kconfig.defconfig b/boards/arm/gd32l233r_eval/Kconfig.defconfig deleted file mode 100644 index 2d25f793d38..00000000000 --- a/boards/arm/gd32l233r_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32L233R_EVAL - -config BOARD - default "gd32l233r_eval" - -endif # BOARD_GD32L233R_EVAL diff --git a/boards/arm/gd32l233r_eval/gd32l233r_eval_defconfig b/boards/arm/gd32l233r_eval/gd32l233r_eval_defconfig deleted file mode 100644 index 866f00cfabb..00000000000 --- a/boards/arm/gd32l233r_eval/gd32l233r_eval_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32L23X=y -CONFIG_SOC_GD32L233=y -CONFIG_BOARD_GD32L233R_EVAL=y - -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/google_dragonclaw/Kconfig.board b/boards/arm/google_dragonclaw/Kconfig.board deleted file mode 100644 index 6a558693dcf..00000000000 --- a/boards/arm/google_dragonclaw/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GOOGLE_DRAGONCLAW - bool "Google Dragonclaw Development Board" - depends on SOC_STM32F412CX diff --git a/boards/arm/google_dragonclaw/Kconfig.defconfig b/boards/arm/google_dragonclaw/Kconfig.defconfig deleted file mode 100644 index 646e28fd70b..00000000000 --- a/boards/arm/google_dragonclaw/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GOOGLE_DRAGONCLAW - -config BOARD - default "google_dragonclaw" - -endif # BOARD_GOOGLE_DRAGONCLAW diff --git a/boards/arm/google_kukui/Kconfig.board b/boards/arm/google_kukui/Kconfig.board deleted file mode 100644 index d3585a6bc2b..00000000000 --- a/boards/arm/google_kukui/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Google Kukui EC - -# Copyright 2019 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GOOGLE_KUKUI - bool "Google Kukui EC" - depends on SOC_STM32F098XX - help - This is the EC (Embedded Controller) inside a Lenovo Chromebook - Duet and 10e Chromebook Tablet. The EC handles battery charging, - keyboard scanning, USB Power Delivery and sensors. - - So far for Zephyr only a simple serial console and I2C are supported. diff --git a/boards/arm/google_kukui/Kconfig.defconfig b/boards/arm/google_kukui/Kconfig.defconfig deleted file mode 100644 index dc735470a35..00000000000 --- a/boards/arm/google_kukui/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Google Kukui EC - -# Copyright 2019 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GOOGLE_KUKUI - -config BOARD - default "google_kukui" - -endif # BOARD_GOOGLE_KUKUI diff --git a/boards/arm/google_kukui/doc/index.rst b/boards/arm/google_kukui/doc/index.rst deleted file mode 100644 index 434541c4f6a..00000000000 --- a/boards/arm/google_kukui/doc/index.rst +++ /dev/null @@ -1,88 +0,0 @@ -.. _google_kukui_board: - -Google Kukui EC -############### - -Overview -******** - -Kukui is a reference board for Chromium OS-based devices Krane and -Kodama. These are known as the Lenovo Chromebook Duet and 10e Chromebook -Tablet, respectively. - -Zephyr has support for the STM32-based embedded controller (EC) on-board. - -Hardware -******** - -- STM32F098RCH6 -- MT6370 battery charger -- BMM150 compass -- BMM160 gyroscope -- Connections to the MediaTek AP - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other features (such as I2C) are not available in Zephyr. - -The default configuration can be found in the defconfig file: -``boards/arm/google_kukui/google_kukui_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output -(push-pull or open-drain), as input (with or without pull-up or -pull-down), or as peripheral alternate function. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA10/PA9 -- I2C_1 SCL/SDA : PB8/PB9 -- I2C_2 SCL/SDA : PA11/PA12 -- Volume down : GPIOB pin 11 -- Volume up : GPIOB pin 10 -- Power : GPIOA pin 0 - -Programming and Debugging -************************* - -Build application as usual for the ``google_kukui`` board, and flash -using Servo V2, μServo, or Servo V4 (CCD). See the -`Chromium EC Flashing Documentation`_ for more information. - -Debugging -========= - -Use SWD with a J-Link or ST-Link. - -References -********** - -.. target-notes:: - -.. _Chromium EC Flashing Documentation: - https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/google_kukui/google_kukui_defconfig b/boards/arm/google_kukui/google_kukui_defconfig deleted file mode 100644 index 3390acdaec5..00000000000 --- a/boards/arm/google_kukui/google_kukui_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F098XX=y -CONFIG_BOARD_GOOGLE_KUKUI=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/google_twinkie_v2/Kconfig.board b/boards/arm/google_twinkie_v2/Kconfig.board deleted file mode 100644 index 45f571ca2b0..00000000000 --- a/boards/arm/google_twinkie_v2/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2023 The ChromiumOS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GOOGLE_TWINKIE_V2 - bool "Google Twinkie V2 Board" - depends on SOC_STM32G0B1XX diff --git a/boards/arm/google_twinkie_v2/Kconfig.defconfig b/boards/arm/google_twinkie_v2/Kconfig.defconfig deleted file mode 100644 index 16350500a23..00000000000 --- a/boards/arm/google_twinkie_v2/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2023 The ChromiumOS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GOOGLE_TWINKIE_V2 - -config BOARD - default "google_twinkie_v2" - -endif # BOARD_GOOGLE_TWINKIE_V2 diff --git a/boards/arm/google_twinkie_v2/doc/index.rst b/boards/arm/google_twinkie_v2/doc/index.rst deleted file mode 100644 index 216e5747b7f..00000000000 --- a/boards/arm/google_twinkie_v2/doc/index.rst +++ /dev/null @@ -1,57 +0,0 @@ -.. _google_twinkie_v2_board: - -Google Twinkie V2 -################# - -Overview -******** - -Google Twinkie V2 is a reference board for the google power delivery analyzer -(PDA) Twinkie V2. - -Hardware -******** - -- STM32G0B1REI6 - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/google_twinkie_v2/google_twinkie_v2_defconfig`` - -Pin Mapping -=========== - -Default Zephyr Peripheral Mapping: ----------------------------------- -- CC1_BUF : PA1 -- CC2_BUF : PA3 -- VBUS_READ_BUF : PB11 -- CSA_VBUS : PC4 -- CSA_CC2 : PC5 - -Programming and Debugging -************************* - -Build application as usual for the ``google_twinkie_v2`` board, and flash -using dfu-util or J-Link. - -Debugging -========= - -Use SWD with a J-Link or ST-Link. diff --git a/boards/arm/hexiwear_k64/Kconfig.board b/boards/arm/hexiwear_k64/Kconfig.board deleted file mode 100644 index 664294d51ad..00000000000 --- a/boards/arm/hexiwear_k64/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Hexiwear K64 board - -# Copyright (c) 2016, Freescale Semiconductor, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HEXIWEAR_K64 - bool "NXP Hexiwear K64" - depends on SOC_SERIES_KINETIS_K6X - select SOC_PART_NUMBER_MK64FN1M0VDC12 diff --git a/boards/arm/hexiwear_k64/Kconfig.defconfig b/boards/arm/hexiwear_k64/Kconfig.defconfig deleted file mode 100644 index 8c00ebed8fc..00000000000 --- a/boards/arm/hexiwear_k64/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Hexiwear K64 board - -# Copyright (c) 2016, Freescale Semiconductor, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HEXIWEAR_K64 - -config BOARD - default "hexiwear_k64" - -config OSC_XTAL0_FREQ - default 12000000 - -config MCG_PRDIV0 - default 0x02 - -config MCG_VDIV0 - default 0x06 - -config MCG_FCRDIV - default 1 - -config REGULATOR - default y if ADC || SENSOR - -endif # BOARD_HEXIWEAR_K64 diff --git a/boards/arm/hexiwear_k64/board.cmake b/boards/arm/hexiwear_k64/board.cmake deleted file mode 100644 index 487cfeb0d0d..00000000000 --- a/boards/arm/hexiwear_k64/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(pyocd "--target=k64f") -board_runner_args(jlink "--device=MK64FN1M0xxx12") - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/arm/hexiwear_k64/doc/index.rst b/boards/arm/hexiwear_k64/doc/index.rst deleted file mode 100644 index c9a9d03044a..00000000000 --- a/boards/arm/hexiwear_k64/doc/index.rst +++ /dev/null @@ -1,336 +0,0 @@ -.. _hexiwear_k64: - -Hexiwear -######## - -Overview -******** - -Hexiwear is powered by a Kinetis K64 microcontroller based on the ARM Cortex-M4 -core. Another Kinetis wireless MCU, the KW40Z, provides Bluetooth Low Energy -connectivity. Hexiwear also integrates a wide variety of sensors, as well as a -user interface consisting of a 1.1" 96px x 96px full color OLED display and six -capacitive buttons with haptic feedback. - -- Eye-catching Smart Watch form factor with powerful, low power Kinetis K6x MCU - and 6 on-board sensors. -- Designed for wearable applications with the onboard rechargeable battery, - OLED screen and onboard sensors such as optical heart rate, accelerometer, - magnetometer and gyroscope. -- Designed for IoT end node applications with the onboard sensor's such as - temperature, pressure, humidity and ambient light. -- Flexibility to let you add the sensors of your choice nearly 200 additional - sensors through click boards. - -.. image:: hexiwear_k64.jpg - :align: center - :alt: Hexiwear - -Hardware -******** - -- Main MCU: NXP Kinetis K64x (ARM Cortex-M4, 120 MHz, 1M Flash, 256K SRAM) -- Wireless MCU: NXP Kinetis KW4x (ARM Cortex-M0+, Bluetooth Low Energy & - 802.15.4 radio) -- 6-axis combo Accelerometer and Magnetometer NXP FXOS8700 -- 3-Axis Gyroscope: NXP FXAS21002 -- Absolute Pressure sensor NXP MPL3115 -- Li-Ion/Li-Po Battery Charger NXP MC34671 -- Optical heart rate sensor Maxim MAX30101 -- Ambient Light sensor, Humidity and Temperature sensor -- 1.1" full color OLED display -- Haptic feedback engine -- 190 mAh 2C Li-Po battery -- Capacitive touch interface -- RGB LED - -For more information about the K64F SoC and Hexiwear board: - -- `K64F Website`_ -- `K64F Datasheet`_ -- `K64F Reference Manual`_ -- `Hexiwear Website`_ -- `Hexiwear Fact Sheet`_ -- `Hexiwear Schematics`_ - -Supported Features -================== - -The hexiwear_k64 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger; | -| | | fxas21002 polling; | -| | | fxas21002 trigger; | -| | | max30101 polling | -+-----------+------------+-------------------------------------+ -| RNGA | on-chip | entropy; | -| | | random | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/hexiwear_k64/hexiwear_k64_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The K64F SoC has five pairs of pinmux/gpio controllers. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTA29 | GPIO | LDO_EN | -+-------+-----------------+---------------------------+ -| PTB0 | I2C0_SCL | I2C / MAX30101 | -+-------+-----------------+---------------------------+ -| PTB1 | I2C0_SDA | I2C / MAX30101 | -+-------+-----------------+---------------------------+ -| PTB12 | GPIO | 3V3B EN | -+-------+-----------------+---------------------------+ -| PTB16 | UART0_RX | UART Console | -+-------+-----------------+---------------------------+ -| PTB17 | UART0_TX | UART Console | -+-------+-----------------+---------------------------+ -| PTC8 | GPIO / PWM | Red LED | -+-------+-----------------+---------------------------+ -| PTC9 | GPIO / PWM | Green LED | -+-------+-----------------+---------------------------+ -| PTC10 | I2C1_SCL | I2C / FXOS8700 / FXAS21002| -+-------+-----------------+---------------------------+ -| PTC11 | I2C1_SDA | I2C / FXOS8700 / FXAS21002| -+-------+-----------------+---------------------------+ -| PTC14 | GPIO | Battery sense enable | -+-------+-----------------+---------------------------+ -| PTC18 | GPIO | FXAS21002 INT2 | -+-------+-----------------+---------------------------+ -| PTD0 | GPIO / PWM | Blue LED | -+-------+-----------------+---------------------------+ -| PTD13 | GPIO | FXOS8700 INT2 | -+-------+-----------------+---------------------------+ -| PTE24 | UART4_RX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTE25 | UART4_TX | UART BT HCI | -+-------+-----------------+---------------------------+ - -.. note:: - - To enable battery sensing, you will need to enable the ``en_bat_sens`` - regulator in Devicetree. Similarly, to enable devices connected to the 1V8 - or 3V3 power rails (sensors), you will need to enable the ``en_ldo`` - and ``en_3v3b`` regulators in Devicetree. - -System Clock -============ - -The K64F SoC is configured to use the 12 MHz external oscillator on the board -with the on-chip PLL to generate a 120 MHz system clock. - -Serial Port -=========== - -The K64F SoC has six UARTs. One is configured for the console, another for BT -HCI, and the remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -but because Segger RTT is required for a console on KW40Z, we recommend that -you reconfigure the board for the :ref:`opensda-jlink-onboard-debug-probe`. - -.. note:: - OpenSDA is shared between the K64 and the KW40Z via switches, therefore only - one SoC can be flashed, debugged, or have an open console at a time. - -Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended) ----------------------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches -SW1 and SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals -are connected to the OpenSDA microcontroller. - -Option 2: :ref:`opensda-daplink-onboard-debug-probe` ----------------------------------------------------- - -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to -program the `OpenSDA DAPLink Hexiwear Firmware`_. Check that switches SW1 and -SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals are -connected to the OpenSDA microcontroller. - -Add the arguments ``-DBOARD_FLASH_RUNNER=pyocd`` and -``-DBOARD_DEBUG_RUNNER=pyocd`` when you invoke ``west build`` to override the -default runner from J-Link to pyOCD: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_k64 - :gen-args: -DBOARD_FLASH_RUNNER=pyocd -DBOARD_DEBUG_RUNNER=pyocd - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to CN1. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_k64 - :goals: flash - -Open a serial terminal, reset the board (press the T4 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear_k64 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_k64 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear_k64 - -Using Bluetooth -*************** - -Configure the KW40Z as a Bluetooth controller -============================================= - -The K64 can support Zephyr Bluetooth host applications when you configure the -KW40Z as a Bluetooth controller. - -#. Download and install the `KW40Z Connectivity Software`_. This package - contains Bluetooth controller application for the KW40Z. -#. Flash the file ``tools/binaries/BLE_HCI_Modem.bin`` to the KW40Z. - -Now you can build and run the sample Zephyr Bluetooth host applications on the -K64. You do not need to repeat this step each time you flash a new Bluetooth -host application to the K64. - -Peripheral Heart Rate Sensor -============================ - -Navigate to the Zephyr ``samples/bluetooth/peripheral_hr`` sample -application, then build and flash it to the Hexiwear K64. Make sure -the OpenSDA switches on the docking station are configured for the -K64. - -.. zephyr-app-commands:: - :zephyr-app: samples/bluetooth/peripheral_hr - :board: hexiwear_k64 - :goals: build flash - -Reset the KW40Z and the K64 using the push buttons on the docking station. - -Install the Kinetis BLE Toolbox on your smartphone: - -- `Kinetis BLE Toolbox for iOS`_ -- `Kinetis BLE Toolbox for Android`_ - -Open the app, tap the **Heart Rate** feature, and you should see a **Zephyr -Heartrate Sensor** device. Tap the **Zephyr Heartrate Sensor** device and you -will then see a plot of the heart rate data that updates once per second. - - -.. _Hexiwear Website: - https://www.mikroe.com/hexiwear - -.. _Hexiwear Fact Sheet: - https://www.nxp.com/docs/en/fact-sheet/HEXIWEAR-FS.pdf - -.. _Hexiwear Schematics: - http://cdn-docs.mikroe.com/images/c/c0/Sch_Hexiwear_MainBoard_v106c.pdf - -.. _K64F Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k6x-ethernet/kinetis-k64-120-mhz-256kb-sram-microcontrollers-mcus-based-on-arm-cortex-m4-core:K64_120 - -.. _K64F Datasheet: - https://www.nxp.com/docs/en/data-sheet/K64P144M120SF5.pdf - -.. _K64F Reference Manual: - https://www.nxp.com/docs/en/reference-manual/K64P144M120SF5RM.pdf - -.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: - https://www.segger.com/downloads/jlink/OpenSDA_V2_1 - -.. _OpenSDA DAPLink Hexiwear Firmware: - https://github.com/MikroElektronika/HEXIWEAR/blob/master/HW/HEXIWEAR_DockingStation/HEXIWEAR_DockingStation_DAPLINK_FW.bin - -.. _KW40Z Connectivity Software: - https://www.nxp.com/webapp/Download?colCode=KW40Z-CONNECTIVITY-SOFTWARE&appType=license&location=null&fpsp=1&WT_TYPE=Protocol%20Stacks&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=exe&WT_ASSET=Downloads&fileExt=.exe&Parent_nodeId=1432854896956716810497&Parent_pageType=product - -.. _Kinetis BLE Toolbox for iOS: - https://itunes.apple.com/us/app/kinetis-ble-toolbox/id1049036961?mt=8 - -.. _Kinetis BLE Toolbox for Android: - https://play.google.com/store/apps/details?id=com.freescale.kinetisbletoolbox diff --git a/boards/arm/hexiwear_k64/hexiwear_k64.dts b/boards/arm/hexiwear_k64/hexiwear_k64.dts deleted file mode 100644 index 133acf81b4c..00000000000 --- a/boards/arm/hexiwear_k64/hexiwear_k64.dts +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include -#include -#include "hexiwear_k64-pinctrl.dtsi" - -/ { - model = "Hexiwear K64 board"; - compatible = "nxp,hexiwear", "nxp,k64f", "nxp,k6x"; - - aliases { - led0 = &green_led; - led1 = &blue_led; - led2 = &red_led; - pwm-led0 = &green_pwm_led; - red-pwm-led = &red_pwm_led; - green-pwm-led = &green_pwm_led; - blue-pwm-led = &blue_pwm_led; - magn0 = &fxos8700; - accel0 = &fxos8700; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,bt-uart = &uart4; - }; - - leds { - compatible = "gpio-leds"; - red_led: led_0 { - gpios = <&gpioc 8 GPIO_ACTIVE_LOW>; - label = "User LD1"; - }; - green_led: led_1 { - gpios = <&gpiod 0 GPIO_ACTIVE_LOW>; - label = "User LD2"; - }; - blue_led: led_2 { - gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; - label = "User LD3"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - red_pwm_led: red_pwm_led { - pwms = <&ftm3 4 15625000 PWM_POLARITY_INVERTED>; - }; - green_pwm_led: green_pwm_led { - pwms = <&ftm3 0 15625000 PWM_POLARITY_INVERTED>; - }; - blue_pwm_led: blue_pwm_led { - pwms = <&ftm3 5 15625000 PWM_POLARITY_INVERTED>; - }; - }; - - en_bat_sens: enable-battery-sense { - compatible = "regulator-fixed"; - regulator-name = "en_bat_sens"; - enable-gpios = <&gpioc 14 GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; - - en_ldo: enable-ldo { - compatible = "regulator-fixed"; - regulator-name = "en_ldo"; - enable-gpios = <&gpioa 29 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - en_3v3b: enable-3v3b { - compatible = "regulator-fixed"; - regulator-name = "en_3v3b"; - enable-gpios = <&gpiob 12 GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; -}; - -&sim { - pllfll-select = ; - er32k-select = ; -}; - -&cpu0 { - clock-frequency = <120000000>; -}; - -&adc0 { - status = "okay"; -}; - -&adc1 { - status = "okay"; -}; - -&ftm3 { - status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; - #pwm-cells = <3>; - pinctrl-0 = <&ftm3_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - - max30101@57 { - status = "disabled"; - compatible = "maxim,max30101"; - reg = <0x57>; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; - - fxos8700: fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - int1-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; - int2-gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; - }; - - fxas21002@20 { - compatible = "nxp,fxas21002"; - reg = <0x20>; - int1-gpios = <&gpiod 1 GPIO_ACTIVE_LOW>; - int2-gpios = <&gpioc 18 GPIO_ACTIVE_LOW>; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&gpioe { - status = "okay"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* - * The flash starting at 0x00010000 and ending at - * 0x0001ffff (sectors 16-31) is reserved for use - * by the application. - */ - - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 0x00060000>; - }; - slot1_partition: partition@80000 { - label = "image-1"; - reg = <0x00080000 0x00060000>; - }; - scratch_partition: partition@e0000 { - label = "image-scratch"; - reg = <0x000e0000 0x00020000>; - }; - }; -}; diff --git a/boards/arm/hexiwear_k64/hexiwear_k64.yaml b/boards/arm/hexiwear_k64/hexiwear_k64.yaml deleted file mode 100644 index c14e75c35da..00000000000 --- a/boards/arm/hexiwear_k64/hexiwear_k64.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: hexiwear_k64 -name: Hexiwear -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - ble - - gpio - - i2c - - pwm - - watchdog -vendor: nxp diff --git a/boards/arm/hexiwear_k64/hexiwear_k64_defconfig b/boards/arm/hexiwear_k64/hexiwear_k64_defconfig deleted file mode 100644 index 6a9303f32be..00000000000 --- a/boards/arm/hexiwear_k64/hexiwear_k64_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_MK64F12=y -CONFIG_SOC_SERIES_KINETIS_K6X=y -CONFIG_BOARD_HEXIWEAR_K64=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 -CONFIG_OSC_LOW_POWER=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/hexiwear_kw40z/Kconfig.board b/boards/arm/hexiwear_kw40z/Kconfig.board deleted file mode 100644 index 10b0a98a443..00000000000 --- a/boards/arm/hexiwear_kw40z/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Hexiwear KW40Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HEXIWEAR_KW40Z - bool "Hexiwear KW40Z" - depends on SOC_SERIES_KINETIS_KWX - select SOC_PART_NUMBER_MKW40Z160VHT4 diff --git a/boards/arm/hexiwear_kw40z/Kconfig.defconfig b/boards/arm/hexiwear_kw40z/Kconfig.defconfig deleted file mode 100644 index ef4f65381a8..00000000000 --- a/boards/arm/hexiwear_kw40z/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Hexiwear KW40Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HEXIWEAR_KW40Z - -config BOARD - default "hexiwear_kw40z" - -config OSC_XTAL0_FREQ - default 32000000 - -config MCG_FRDIV - default 5 - -config MCG_FCRDIV - default 0 - -endif # BOARD_HEXIWEAR_KW40Z diff --git a/boards/arm/hexiwear_kw40z/board.cmake b/boards/arm/hexiwear_kw40z/board.cmake deleted file mode 100644 index a93baa325e6..00000000000 --- a/boards/arm/hexiwear_kw40z/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=MKW40Z160xxx4") -board_runner_args(pyocd "--target=kw40z4") - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/arm/hexiwear_kw40z/doc/index.rst b/boards/arm/hexiwear_kw40z/doc/index.rst deleted file mode 100644 index 269f1b93124..00000000000 --- a/boards/arm/hexiwear_kw40z/doc/index.rst +++ /dev/null @@ -1,182 +0,0 @@ -.. _hexiwear_kw40z: - -Hexiwear KW40Z -############## - -Overview -******** - -See :ref:`hexiwear_k64` for a general overview of the Hexiwear board and the -main application SoC, the K64. The KW40Z is a secondary SoC on the board that -provides wireless connectivity with a multimode BLE and 802.15.4 radio. - -For more information about the KW40Z SoC: - -- `KW40Z Website`_ -- `KW40Z Datasheet`_ -- `KW40Z Reference Manual`_ - -Supported Features -================== - -The hexiwear_kw40z board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| RTT | on-chip | console | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/hexiwear_kw40z/hexiwear_kw40z_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The KW40Z SoC has three pairs of pinmux/gpio controllers, but only one is -currently enabled (PORTC/GPIOC) for the hexiwear_kw40z board. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTB1 | ADC | ADC0 channel 1 | -+-------+-----------------+---------------------------+ -| PTC6 | UART0_RX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTC7 | UART0_TX | UART BT HCI | -+-------+-----------------+---------------------------+ - -System Clock -============ - -The KW40Z SoC is configured to use the 32 MHz external oscillator on the board -with the on-chip FLL to generate a 40 MHz system clock. - -Serial Port -=========== - -The KW40Z SoC has one UART, which is used for BT HCI. There is no UART -available for a console. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -but because Segger RTT is required for a console, you must reconfigure the -board for one of the following debug probes instead. - -:ref:`opensda-jlink-onboard-debug-probe` ----------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches -SW1 and SW2 are **off**, and SW3 and SW4 are **on** to ensure KW40Z SWD signals -are connected to the OpenSDA microcontroller. - -Configuring a Console -===================== - -The console is available using `Segger RTT`_. - -Connect a USB cable from your PC to CN1. - -Once you have started a debug session, run telnet: - -.. code-block:: console - - $ telnet localhost 19021 - Trying 127.0.0.1... - Connected to localhost. - Escape character is '^]'. - SEGGER J-Link V6.44 - Real time terminal output - J-Link OpenSDA 2 compiled Feb 28 2017 19:27:57 V1.0, SN=621000000 - Process: JLinkGDBServerCLExe - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_kw40z - :goals: flash - -The Segger RTT console is only available during a debug session. Use ``attach`` -to start one: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_kw40z - :goals: attach - -Run telnet as shown earlier, and you should see the following message in the -terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear_kw40z - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_kw40z - :goals: debug - -Run telnet as shown earlier, step through the application in your debugger, and -you should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear_kw40z - -.. _KW40Z Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/kinetis-kw40z-2.4-ghz-dual-mode-ble-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW40Z - -.. _KW40Z Datasheet: - https://www.nxp.com/docs/en/data-sheet/MKW40Z160.pdf - -.. _KW40Z Reference Manual: - https://www.nxp.com/webapp/Download?colCode=MKW40Z160RM - -.. _Segger RTT: - https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/ - -.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: - https://www.segger.com/downloads/jlink/OpenSDA_V2_1 diff --git a/boards/arm/hexiwear_kw40z/hexiwear_kw40z.dts b/boards/arm/hexiwear_kw40z/hexiwear_kw40z.dts deleted file mode 100644 index 2b64e0bafd5..00000000000 --- a/boards/arm/hexiwear_kw40z/hexiwear_kw40z.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include -#include "hexiwear_kw40z-pinctrl.dtsi" - -/ { - model = "Hexiwear KW40 board"; - compatible = "nxp,kw40z", "nxp,mkw40z4"; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; -}; - -&sim { - pllfll-select = ; - er32k-select = ; -}; - -&adc0 { - status = "okay"; - pinctrl-0 = <&adc0_default>; - pinctrl-names = "default"; -}; - -&lpuart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&lpuart0_default>; - pinctrl-names = "default"; -}; - -&gpioa { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; diff --git a/boards/arm/hexiwear_kw40z/hexiwear_kw40z.yaml b/boards/arm/hexiwear_kw40z/hexiwear_kw40z.yaml deleted file mode 100644 index 0e5b4935673..00000000000 --- a/boards/arm/hexiwear_kw40z/hexiwear_kw40z.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: hexiwear_kw40z -name: Hexiwear KW40Z -type: mcu -arch: arm -ram: 16 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net -vendor: nxp diff --git a/boards/arm/hexiwear_kw40z/hexiwear_kw40z_defconfig b/boards/arm/hexiwear_kw40z/hexiwear_kw40z_defconfig deleted file mode 100644 index e7bb17ffa8e..00000000000 --- a/boards/arm/hexiwear_kw40z/hexiwear_kw40z_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_MKW40Z4=y -CONFIG_SOC_SERIES_KINETIS_KWX=y -CONFIG_BOARD_HEXIWEAR_KW40Z=y -CONFIG_CONSOLE=y -CONFIG_RTT_CONSOLE=y -CONFIG_USE_SEGGER_RTT=y -CONFIG_PINCTRL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 -CONFIG_OSC_EXTERNAL=y diff --git a/boards/arm/holyiot_yj16019/Kconfig b/boards/arm/holyiot_yj16019/Kconfig deleted file mode 100644 index c6c54fa5a00..00000000000 --- a/boards/arm/holyiot_yj16019/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Holyiot YJ-16019 board configuration - -# Copyright (c) 2019 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/holyiot_yj16019/Kconfig.board b/boards/arm/holyiot_yj16019/Kconfig.board deleted file mode 100644 index e49ebf90873..00000000000 --- a/boards/arm/holyiot_yj16019/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Holyiot YJ-16019 board configuration - -# Copyright (c) 2019 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HOLYIOT_YJ16019 - bool "Holyiot YJ-16019" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/holyiot_yj16019/Kconfig.defconfig b/boards/arm/holyiot_yj16019/Kconfig.defconfig deleted file mode 100644 index de2d63ad7c8..00000000000 --- a/boards/arm/holyiot_yj16019/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Holyiot YJ-16019 board configuration - -# Copyright (c) 2019 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HOLYIOT_YJ16019 - -config BOARD - default "holyiot_yj16019" - -config BT_CTLR - default BT - -endif # BOARD_HOLYIOT_YJ16019 diff --git a/boards/arm/holyiot_yj16019/doc/index.rst b/boards/arm/holyiot_yj16019/doc/index.rst deleted file mode 100644 index 57990be93a1..00000000000 --- a/boards/arm/holyiot_yj16019/doc/index.rst +++ /dev/null @@ -1,147 +0,0 @@ -.. _holyiot_yj16019: - -Holyiot YJ-16019 -################ - -Overview -******** - -The `Holyiot`_ YJ-16019 hardware provides support for the Nordic -Semiconductor nRF52832 ARM Cortex-M4 CPU and the following devices: - -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/holyiot_yj16019_front.jpg - :align: center - :alt: Holyiot YJ-16019 - - Holyiot YJ-16019 (Credit: Holyiot) - -The board is equipped with one LED, one push button, and is powered by -a CR2032 coin cell. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - -Hardware -******** - -The nRF52832 of the Holyiot YJ-16019 is clocked by an external crystal with a frequency of 32 MHz -(Y1). The 32.768 kHz crystal (Y2) shown on the board schematics is not mounted. - -Supported Features -================== - -The holyiot_yj16019 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -LED and push button -------------------- - -* Push button = P0.28 -* LED = P0.29 - -Programming and Debugging -************************* - -Applications for the ``holyiot_yj16019`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); however, an external -Segger J-Link is required since the board does not have any on-board -debug IC. - -The following pins of the Segger J-Link must be connected to the following test -pads on the PCB (see image): - -* VTref = VCC -* GND = GND -* SWDIO = SDO -* SWCLK = SCK - -.. figure:: img/holyiot_yj16019_pcb.jpg - :align: center - :alt: Holyiot YJ-16019 PCB - - Holyiot YJ-16019 PCB (Credit: Holyiot) - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: holyiot_yj16019 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic -nRF52x-based boards with a Segger debugger. - - -Testing the LED and button on the Holyiot YJ-16019 -************************************************** - -There are 2 samples that allow you to test that the button and LED on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found -in :zephyr_file:`boards/arm/holyiot_yj16019/holyiot_yj16019.dts`. - -References -********** - -.. target-notes:: - -.. _Holyiot: http://www.holyiot.com -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/holyiot_yj16019/holyiot_yj16019_defconfig b/boards/arm/holyiot_yj16019/holyiot_yj16019_defconfig deleted file mode 100644 index 7a5c82fbdc8..00000000000 --- a/boards/arm/holyiot_yj16019/holyiot_yj16019_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_HOLYIOT_YJ16019=y - -# 32kHz clock source -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable RTT -CONFIG_USE_SEGGER_RTT=y - -# Enable GPIO -CONFIG_GPIO=y diff --git a/boards/arm/index.rst b/boards/arm/index.rst index baeeffe8ae7..a9e114281f1 100644 --- a/boards/arm/index.rst +++ b/boards/arm/index.rst @@ -1,7 +1,7 @@ .. _boards-arm: -ARM Boards -########## +ARM Ltd. +######## .. toctree:: :maxdepth: 1 diff --git a/boards/arm/ip_k66f/Kconfig.board b/boards/arm/ip_k66f/Kconfig.board deleted file mode 100644 index ec73f2a88b1..00000000000 --- a/boards/arm/ip_k66f/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2020 DENX Software Engineering GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_IP_K66F - bool "Segger IP-K66F" - depends on SOC_SERIES_KINETIS_K6X - select SOC_PART_NUMBER_MK66FN2M0VMD18 diff --git a/boards/arm/ip_k66f/Kconfig.defconfig b/boards/arm/ip_k66f/Kconfig.defconfig deleted file mode 100644 index 2543e52684a..00000000000 --- a/boards/arm/ip_k66f/Kconfig.defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# IP-K66F board - -# Copyright (c) 2020 DENX Software Engineering GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_IP_K66F - -config BOARD - default "ip_k66f" - -config OSC_XTAL0_FREQ - default 12000000 - -config MCG_PRDIV0 - default 0x0 - -config MCG_VDIV0 - default 0xe - -config MCG_FCRDIV - default 1 - -if NETWORKING - -config NET_L2_ETHERNET - default y - -config ETH_MCUX_RMII_EXT_CLK - default y if ETH_MCUX - -config ETH_MCUX_NO_PHY_SMI - default y if ETH_MCUX - -endif # NETWORKING - -endif # BOARD_IP_K66F diff --git a/boards/arm/ip_k66f/doc/index.rst b/boards/arm/ip_k66f/doc/index.rst deleted file mode 100644 index eb8ee3b3e99..00000000000 --- a/boards/arm/ip_k66f/doc/index.rst +++ /dev/null @@ -1,175 +0,0 @@ -.. _ip_k66f: - -SEGGER IP Switch Board -###################### - -Overview -******** - -The Segger IP Switch Board is a Evaluation board based on NXP Kinetis K66 MCU. -It comes with Micrel/Microchip KSZ8794CNX integrated 4-port 10/100 managed -Ethernet switch with Gigabit RGMII/MII/RMII interface. - -- KSZ8794CNX enables evaluation for switch functions -- On-board debug probe J-Link-OB for programming - -.. image:: ip_k66f.jpg - :align: center - :alt: IP-K66F - -Hardware -******** - -- MK66FN2M0VMD18 MCU (180 MHz, 2 MB flash memory, 256 KB RAM, low-power, - crystal-less USB -- Dual role USB interface with micro-B USB connector -- 2 User LED -- On-board debug probe J-Link-OB for programming -- Micrel/Microchip Ethernet Switch KSZ8794CNX with 3 RJ45 connectors - -For more information about the K66F SoC and IP-K66F board: - -- `K66F Website`_ -- `K66F Datasheet`_ -- `K66F Reference Manual`_ -- `IP-K66F Website`_ -- `IP-K66F User Guide`_ -- `IP-K66F Schematics`_ - -Supported Features -================== - -The ip_k66f board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/ip_k66f/ip_k66f_defconfig`` - -Micrel/Microchip KSZ8794CNX Ethernet Switch is not currently -supported. - -Connections and IOs -=================== - -The K66F SoC has five pairs of pinmux/gpio controllers. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTA8 | GPIO | Red LED | -+-------+-----------------+---------------------------+ -| PTA10 | GPIO | RED LED | -+-------+-----------------+---------------------------+ - -System Clock -============ - -The K66F SoC is configured to use the 12 MHz low gain crystal oscillator on the -board with the on-chip PLL to generate a 180 MHz system clock. - -Serial Port -=========== - -The K66F SoC has six UARTs. None of them are used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-jlink-onboard-debug-probe`. - -:ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Generic Firmware for V3.2 Bootloader`_. Note that Segger -does provide an OpenSDA J-Link Board-Specific Firmware for this board, however -it is not compatible with the DAPLink bootloader. - -The default flasher is ``jlink`` using the built-in SEGGER Jlink interface. - -Flashing -======== - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: ip_k66f - :goals: flash - -Red LED0 should blink at 1 second delay. - -Debugging -========= - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: ip_k66f - :goals: debug - -Step through the application in your debugger. - -.. _IP-K66F Website: - https://www.segger.com/evaluate-our-software/segger/embosip-switch-board/ - -.. _IP-K66F User Guide: - https://www.segger.com/downloads/emnet/UM06002 - -.. _IP-K66F Schematics: - https://www.segger.com/downloads/emnet/embOSIP_SwitchBoard_V2.0_WEB_Schematic.pdf - -.. _K66F Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k6x-ethernet/kinetis-k66-180-mhz-dual-high-speed-full-speed-usbs-2mb-flash-microcontrollers-mcus-based-on-arm-cortex-m4-core:K66_180 - -.. _K66F Datasheet: - https://www.nxp.com/docs/en/data-sheet/K66P144M180SF5V2.pdf - -.. _K66F Reference Manual: - https://www.nxp.com/webapp/Download?colCode=K66P144M180SF5RMV2 - -.. _OpenSDA J-Link Generic Firmware for V3.2 Bootloader: - https://www.segger.com/downloads/jlink/OpenSDA_V3_2 - -Serial console -============== - -The ``ip_k66f`` board only uses Segger's RTT console for providing serial -console. There is no physical serial port available. - -- To communicate with this board one needs in one console: - -``/opt/SEGGER/JLink_V664/JLinkRTTLogger -Device MK66FN2M0XXX18 -RTTChannel 1 -if SWD -Speed 4000 ~/rtt.log`` - -- In another one: - -``nc localhost 19021`` diff --git a/boards/arm/kv260_r5/Kconfig.board b/boards/arm/kv260_r5/Kconfig.board deleted file mode 100644 index 8bd28d7f10f..00000000000 --- a/boards/arm/kv260_r5/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Linaro. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_KV260_R5 - bool "Xilinx KV260 development board R5-core" - depends on SOC_XILINX_ZYNQMP_RPU diff --git a/boards/arm/kv260_r5/Kconfig.defconfig b/boards/arm/kv260_r5/Kconfig.defconfig deleted file mode 100644 index a9df885cc1a..00000000000 --- a/boards/arm/kv260_r5/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2022 Linaro. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_KV260_R5 - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "board_kv260_r5" - -if USERSPACE - -config COMPILER_ISA_THUMB2 - default n - -endif - -endif # BOARD_KV260_R5 diff --git a/boards/arm/kv260_r5/kv260_r5_defconfig b/boards/arm/kv260_r5/kv260_r5_defconfig deleted file mode 100644 index 6eb51f3849d..00000000000 --- a/boards/arm/kv260_r5/kv260_r5_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_SOC_XILINX_ZYNQMP_RPU=y -CONFIG_BOARD_KV260_R5=y -CONFIG_XIP=n - -CONFIG_ISR_STACK_SIZE=512 -CONFIG_THREAD_STACK_INFO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable serial port -CONFIG_UART_XLNX_PS=y - -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_ARM_MPU=y diff --git a/boards/arm/legend/Kconfig.board b/boards/arm/legend/Kconfig.board deleted file mode 100644 index 6820a8c0dcd..00000000000 --- a/boards/arm/legend/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Legend board family configuration - -# Copyright (c) 2021 Seagate Technology -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LEGEND - bool "Legend board" - depends on SOC_STM32F070XB diff --git a/boards/arm/legend/Kconfig.defconfig b/boards/arm/legend/Kconfig.defconfig deleted file mode 100644 index 06c47f232fd..00000000000 --- a/boards/arm/legend/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Legend board family configuration - -# Copyright (c) 2021, Seagate Technology LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LEGEND - -config BOARD - default "legend" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_LEGEND diff --git a/boards/arm/legend/legend.yaml b/boards/arm/legend/legend.yaml deleted file mode 100644 index 1762e786318..00000000000 --- a/boards/arm/legend/legend.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: legend -name: Legend -type: mcu -arch: arm -ram: 16 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio - - i2c - - pwm - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: seagate diff --git a/boards/arm/legend/legend_defconfig b/boards/arm/legend/legend_defconfig deleted file mode 100644 index 1ab444cc39b..00000000000 --- a/boards/arm/legend/legend_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F070XB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock Control -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/lora_e5_dev_board/Kconfig.board b/boards/arm/lora_e5_dev_board/Kconfig.board deleted file mode 100644 index 78fd5de63cd..00000000000 --- a/boards/arm/lora_e5_dev_board/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# LoRa-E5 Dev board configuration - -# Copyright (c) 2021 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LORA_E5_DEV_BOARD - bool "LoRa E5 Development Board" - depends on SOC_STM32WLE5XX diff --git a/boards/arm/lora_e5_dev_board/Kconfig.defconfig b/boards/arm/lora_e5_dev_board/Kconfig.defconfig deleted file mode 100644 index 857cd45e684..00000000000 --- a/boards/arm/lora_e5_dev_board/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# LoRa-E5 Dev board configuration - -# Copyright (c) 2021 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LORA_E5_DEV_BOARD - -config BOARD - default "lora_e5_dev_board" - -endif # BOARD_LORA_E5_DEV_BOARD diff --git a/boards/arm/lora_e5_dev_board/lora_e5_dev_board_defconfig b/boards/arm/lora_e5_dev_board/lora_e5_dev_board_defconfig deleted file mode 100644 index 912493764e2..00000000000 --- a/boards/arm/lora_e5_dev_board/lora_e5_dev_board_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_SOC_SERIES_STM32WLX=y -CONFIG_SOC_STM32WLE5XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable regulator for the power-rails -CONFIG_REGULATOR=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/lora_e5_mini/Kconfig.board b/boards/arm/lora_e5_mini/Kconfig.board deleted file mode 100644 index 1b4e30a54c4..00000000000 --- a/boards/arm/lora_e5_mini/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# LoRa-E5 mini configuration - -# Copyright (c) 2023 Marcin Niestroj -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LORA_E5_MINI - bool "LoRa E5 mini" - depends on SOC_STM32WLE5XX diff --git a/boards/arm/lora_e5_mini/Kconfig.defconfig b/boards/arm/lora_e5_mini/Kconfig.defconfig deleted file mode 100644 index ca35c4321a0..00000000000 --- a/boards/arm/lora_e5_mini/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# LoRa-E5 mini configuration - -# Copyright (c) 2023 Marcin Niestroj -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LORA_E5_MINI - -config BOARD - default "lora_e5_mini" - -endif # BOARD_LORA_E5_MINI diff --git a/boards/arm/lora_e5_mini/board.cmake b/boards/arm/lora_e5_mini/board.cmake deleted file mode 100644 index ac24f811559..00000000000 --- a/boards/arm/lora_e5_mini/board.cmake +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(pyocd "--target=stm32wle5jcix") -board_runner_args(pyocd "--flash-opt=-O reset_type=hw") -board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") -board_runner_args(jlink "--device=STM32WLE5JC" "--speed=4000" "--reset-after-load") -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") -board_runner_args(blackmagicprobe "--connect-rst") - -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) diff --git a/boards/arm/lora_e5_mini/doc/index.rst b/boards/arm/lora_e5_mini/doc/index.rst deleted file mode 100644 index 6e6be186dd7..00000000000 --- a/boards/arm/lora_e5_mini/doc/index.rst +++ /dev/null @@ -1,226 +0,0 @@ -.. _lora_e5_mini: - -Seeed Studio LoRa-E5 mini -######################### - -Overview -******** - -LoRa-E5 mini is a compacted-sized development board suitable for the rapid -testing and building of small-sized LoRa device, exposing all capabilities of -Seeed Studio LoRa-E5 STM32WLE5JC module. - -.. image:: img/lora_e5_mini.jpg - :align: center - :alt: LoRa-E5 mini - -Hardware -******** - -The boards' LoRa-E5 Module packages a STM32WLE5JC SOC, a 32MHz TCXO, -and a 32.768kHz crystal oscillator in a 28-pin SMD package. -This STM32WLEJC SOC is powered by ARM Cortex-M4 core and integrates Semtech -SX126X LoRa IP to support (G)FSK, BPSK, (G)MSK, and LoRa modulations. - -- LoRa-E5 STM32WLE5JC Module with STM32WLE5JC multiprotocol LPWAN single-core - 32-bit microcontroller (Arm® Cortex®-M4 at 48 MHz) in 28-pin SMD package - featuring: - - - Ultra-low-power MCU - - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®, - (G)FSK, (G)MSK, and BPSK modulations - - 256-Kbyte Flash memory and 64-Kbyte SRAM - - Hardware encryption AES256-bit and a True random number generator - -- 1 user LED -- 2 serial communication (RX/TX) LEDs -- 1 boot/user and 1 reset push-button -- 32.768 kHz LSE crystal oscillator -- 32 MHz HSE oscillator -- Board connectors: - - - USB Type-C connector - - +/- (battery) power input pins (3-5V) - - SMA-K and IPEX antenna connectors - -- Delivered with SMA antenna (per default IPEX connector is disconnected) -- Flexible power-supply options: USB Type C or 3-5V battery soldered to +/- pins -- Suitable for rapid prototyping of end nodes based on LoRaWAN, Sigfox, wM-Bus, - and many other proprietary protocols -- All GPIOs led out from the LoRa-E5 STM32WLE5JC module -- 4x M2 mounting holes - -More information about the board can be found at the `LoRa-E5 mini Wiki`_. - -More information about LoRa-E5 STM32WLE5JC Module can be found here: - -- `LoRa-E5 STM32WLE5JC Module Wiki`_ -- `LoRa-E5 STM32WLE5JC Module datasheet`_ -- `STM32WLE5JC datasheet`_ -- `STM32WLE5JC reference manual`_ -- `STM32WLE5JC on www.st.com`_ - -Supported Features -================== - -The Zephyr LoRa-E5 mini configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| AES | on-chip | crypto | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | LoRa | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig and dts files: - -- :zephyr_file:`boards/arm/lora_e5_mini/lora_e5_mini_defconfig` -- :zephyr_file:`boards/arm/lora_e5_mini/lora_e5_mini.dts` - - -Connections and IOs -=================== - -LoRa-E5 mini has 4 GPIO controllers. These controllers are responsible for pin -muxing, input/output, pull-up, etc. - -Available pins: ---------------- - -.. image:: img/lora_e5_mini_pinout.jpg - :align: center - :alt: LoRa-E5 mini Pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- USART_1 TX : PB6 -- USART_1 RX : PB7 -- I2C_2_SCL : PB15 -- I2C_2_SDA : PA15 -- BOOT_PB : PB13 -- LED_1 : PB5 - -System Clock ------------- - -LoRa-E5 mini board System Clock could be driven by the low-power internal (MSI), -High-speed internal (HSI) or High-speed external (HSE) oscillator, as well as -main PLL clock. By default System clock is driven by the MSI clock at 48MHz. - -Programming and Debugging -************************* - -Applications for the ``lora_e5_mini`` board configuration can be built the -usual way (see :ref:`build_an_application`). - -In the factory the module is flashed with an DFU bootloader, an AT command -firmware, and the read protection level 1 is enabled. -So before you can program a Zephyr application to the module for the first time -you have to reset the read protection to level 0. -In case you use an st-link debugger you can use the STM32CubeProgrammer GUI to -set the RDP option byte to ``AA``, -or use the STM32_Programmer_CLI passing the ``--readunprotect`` command -to perform this read protection regression. -The RDP level 1 to RDP level 0 regression will erase the factory programmed AT -firmware, from which seeed has neither released the source code nor a binary. -Also, note that on the module the ``BOOT0`` pin of the SOC is not accessible, -so the system bootloader will only be executed if configured in the option bytes. - -Flashing -======== - -The LoRa-E5 mini does not include a on-board debug probe. -But the module can be debugged by connecting an external debug probe to the -2.54mm header. -Depending on the external probe used, ``openocd``, the ``stm32cubeprogrammer``, -``pyocd``, ``blackmagic``, or ``jlink`` runner can be used to flash the board. -Additional notes: - -- Pyocd: For STM32WL support Pyocd needs additional target information, which - can be installed by adding "pack" support with the following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32wl - -Flashing an application to LoRa-E5 mini ---------------------------------------- - -Connect the LoRa-E5 to your host computer using the external debug probe. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your board: -Per default the console on ``usart1`` is available on the USB Type C connector -via the built-in USB to UART converter. - -.. code-block:: console - - $ picocom --baud 115200 /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lora_e5_mini - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: lora_e5_mini - :maybe-skip-config: - :goals: debug - -.. _LoRa-E5 mini Wiki: - https://wiki.seeedstudio.com/LoRa_E5_mini/ - -.. _LoRa-E5 STM32WLE5JC Module Wiki: - https://wiki.seeedstudio.com/LoRa-E5_STM32WLE5JC_Module/ - -.. _LoRa-E5 STM32WLE5JC Module datasheet: - https://files.seeedstudio.com/products/317990687/res/LoRa-E5%20module%20datasheet_V1.0.pdf - -.. _STM32WLE5JC on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32wle5jc.html - -.. _STM32WLE5JC datasheet: - https://www.st.com/resource/en/datasheet/stm32wle5jc.pdf - -.. _STM32WLE5JC reference manual: - https://www.st.com/resource/en/reference_manual/dm00530369-stm32wlex-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf diff --git a/boards/arm/lpcxpresso11u68/Kconfig.board b/boards/arm/lpcxpresso11u68/Kconfig.board deleted file mode 100644 index 721104975a2..00000000000 --- a/boards/arm/lpcxpresso11u68/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso11U68 board - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO11U68 - bool "NXP LPCXPRESSO-11U68" - depends on SOC_SERIES_LPC11U6X - select SOC_PART_NUMBER_LPC11U68JBD100 diff --git a/boards/arm/lpcxpresso11u68/Kconfig.defconfig b/boards/arm/lpcxpresso11u68/Kconfig.defconfig deleted file mode 100644 index da0fd7aacac..00000000000 --- a/boards/arm/lpcxpresso11u68/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# LPCXpresso11U68 board - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO11U68 - -config BOARD - default "lpcxpresso11u68" - -endif # BOARD_LPCXPRESSO11U68 diff --git a/boards/arm/lpcxpresso51u68/Kconfig.board b/boards/arm/lpcxpresso51u68/Kconfig.board deleted file mode 100644 index 21ae8f8571a..00000000000 --- a/boards/arm/lpcxpresso51u68/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso51U68 board - -# Copyright (c) 2021 metraTec GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO51U68 - bool "NXP LPCXPRESSO-51U68" - depends on SOC_SERIES_LPC51U68 - select SOC_PART_NUMBER_LPC51U68JBD64 diff --git a/boards/arm/lpcxpresso51u68/Kconfig.defconfig b/boards/arm/lpcxpresso51u68/Kconfig.defconfig deleted file mode 100644 index 6d8144da692..00000000000 --- a/boards/arm/lpcxpresso51u68/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# LPCXpresso51U68 board - -# Copyright (c) 2021 metraTec GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO51U68 - -config BOARD - default "lpcxpresso51u68" - -endif # BOARD_LPCXPRESSO51U68 diff --git a/boards/arm/lpcxpresso51u68/lpcxpresso51u68_defconfig b/boards/arm/lpcxpresso51u68/lpcxpresso51u68_defconfig deleted file mode 100644 index dd287658c06..00000000000 --- a/boards/arm/lpcxpresso51u68/lpcxpresso51u68_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_SOC_SERIES_LPC51U68=y -CONFIG_SOC_LPC51U68=y -CONFIG_BOARD_LPCXPRESSO51U68=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000 diff --git a/boards/arm/lpcxpresso54114/Kconfig.board b/boards/arm/lpcxpresso54114/Kconfig.board deleted file mode 100644 index ad0e5f55a61..00000000000 --- a/boards/arm/lpcxpresso54114/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# LPCXpresso54114 board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO54114_M4 - bool "NXP LPCXPRESSO-54114 M4" - depends on SOC_SERIES_LPC54XXX - select SOC_PART_NUMBER_LPC54114J256BD64 - -config BOARD_LPCXPRESSO54114_M0 - bool "NXP LPCXPRESSO-54114 M0" - depends on SOC_SERIES_LPC54XXX - select SOC_PART_NUMBER_LPC54114J256BD64 diff --git a/boards/arm/lpcxpresso54114/Kconfig.defconfig b/boards/arm/lpcxpresso54114/Kconfig.defconfig deleted file mode 100644 index 956e9da1528..00000000000 --- a/boards/arm/lpcxpresso54114/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# LPCXpresso54114 board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO54114_M4 || BOARD_LPCXPRESSO54114_M0 - -config BOARD - default "lpcxpresso54114_m4" if BOARD_LPCXPRESSO54114_M4 - default "lpcxpresso54114_m0" if BOARD_LPCXPRESSO54114_M0 - -# Place size restrictions on first image if dual core is enabled -if SECOND_CORE_MCUX && BOARD_LPCXPRESSO54114_M4 - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # SECOND_CORE_MCUX && BOARD_LPCXPRESSO54114_M4 - -endif # BOARD_LPCXPRESSO54114_M4 || BOARD_LPCXPRESSO54114_M0 diff --git a/boards/arm/lpcxpresso54114/board.cmake b/boards/arm/lpcxpresso54114/board.cmake deleted file mode 100644 index f76bdf6a16c..00000000000 --- a/boards/arm/lpcxpresso54114/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_BOARD_LPCXPRESSO54114_M4 OR CONFIG_SECOND_CORE_MCUX) -board_runner_args(jlink "--device=LPC54114J256_M4" "--reset-after-load") -elseif(CONFIG_BOARD_LPCXPRESSO54114_M0) -board_runner_args(jlink "--device=LPC54114J256_M0" "--reset-after-load") -endif() - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/lpcxpresso54114/doc/index.rst b/boards/arm/lpcxpresso54114/doc/index.rst deleted file mode 100644 index e0d38c663ac..00000000000 --- a/boards/arm/lpcxpresso54114/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ -.. _lpcxpresso54114: - -NXP LPCXPRESSO54114 -################### - -Overview -******** - -The LPCXpresso54114 board has been developed by NXP to enable evaluation of and -prototyping with the low-power LPC54110 family of MCUs. LPCXpresso* is a -low-cost development platform available from NXP supporting NXP's ARM-based -microcontrollers. LPCXpresso is an end-to-end solution enabling embedded -engineers to develop their applications from initial evaluation to final -production. - -.. image:: lpcxpresso54114_m4.jpg - :align: center - :alt: LPCXPRESSO54114 - -Hardware -******** - -- LPC54114 dual-core (M4F and dual M0) MCU running at up to 100 MHz -- On-board high-speed USB based debug probe with CMSIS-DAP and J-Link protocol - support, can debug the on-board LPC54114 or an external target -- External debug probe option -- Tri-color LED, target Reset, ISP & interrupt/user buttons for easy testing of - software functionality -- Expansion options based on Arduino UNO and Pmod™, plus additional expansion - port pins -- On-board 1.8 V and 3.3 V regulators plus external power supply option -- 8 Mb Macronix MX25R SPI flash -- Built-in MCU power consumption and supply voltage measurement -- UART, I²C and SPI port bridging from LPC54114 target to USB via the on-board - debug probe -- FTDI UART connector - -For more information about the LPC54114 SoC and LPCXPRESSO54114 board: - -- `LPC54114 SoC Website`_ -- `LPC54114 Datasheet`_ -- `LPC54114 Reference Manual`_ -- `LPCXPRESSO54114 Website`_ -- `LPCXPRESSO54114 User Guide`_ -- `LPCXPRESSO54114 Schematics`_ - -Supported Features -================== - -The lpcxpresso54114 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| IOCON | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port-polling | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| IAP | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration for each core can be found in the defconfig files: - - ``boards/arm/lpcxpresso54114/lpcxpresso54114_m4_defconfig`` - ``boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The LPC54114 SoC has IOCON registers, which can be used to configure the -functionality of a pin. - -+---------+-----------------+----------------------------+ -| Name | Function | Usage | -+=========+=================+============================+ -| PIO0_0 | USART | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_1 | USART | USART TX | -+---------+-----------------+----------------------------+ -| PIO0_18 | SPI | SPI MISO | -+---------+-----------------+----------------------------+ -| PIO0_19 | SPI | SPI SCK | -+---------+-----------------+----------------------------+ -| PIO0_20 | SPI | SPI MOSI | -+---------+-----------------+----------------------------+ -| PIO0_25 | I2C | I2C SCL | -+---------+-----------------+----------------------------+ -| PIO0_26 | I2C | I2C SDA | -+---------+-----------------+----------------------------+ -| PIO0_29 | GPIO | RED LED | -+---------+-----------------+----------------------------+ -| PIO1_1 | SPI | SPI SSEL2 | -+---------+-----------------+----------------------------+ -| PIO1_9 | GPIO | BLUE_LED | -+---------+-----------------+----------------------------+ -| PIO1_10 | GPIO | GREEN LED | -+---------+-----------------+----------------------------+ - -System Clock -============ - -The LPC54114 SoC is configured to use the internal FRO at 48MHz as a source for -the system clock. Other sources for the system clock are provided in the SOC, -depending on your system requirements. - -Serial Port -=========== - -The LPC54114 SoC has 8 FLEXCOMM interfaces for serial communication. One is -configured as USART for the console and the remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe, -however the :ref:`pyocd-debug-host-tools` do not support this probe so you must -reconfigure the board for one of the following debug probes instead. - -:ref:`lpclink2-jlink-onboard-debug-probe` ------------------------------------------ - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program -the J-Link firmware. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the LPC-Link2 -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J5 - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lpcxpresso54114_m4 - :goals: flash - -Open a serial terminal, reset the board (press the SW4 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! lpcxpresso54114_m4 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lpcxpresso54114_m4 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! lpcxpresso54114_m4 - -.. _LPC54114 SoC Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc54000-series-cortex-m4-mcus/low-power-microcontrollers-mcus-based-on-arm-cortex-m4-cores-with-optional-cortex-m0-plus-co-processor:LPC541XX - -.. _LPC54114 Datasheet: - https://www.nxp.com/docs/en/data-sheet/LPC5411X.pdf - -.. _LPC54114 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=UM10914 - -.. _LPCXPRESSO54114 Website: - https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso54114-board:OM13089 - -.. _LPCXPRESSO54114 User Guide: - https://www.nxp.com/webapp/Download?colCode=UM10973 - -.. _LPCXPRESSO54114 Schematics: - https://www.nxp.com/downloads/en/design-support/LPCX5411x_Schematic_Rev_A1.pdf diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0.yaml b/boards/arm/lpcxpresso54114/lpcxpresso54114_m0.yaml deleted file mode 100644 index 4fea41d5526..00000000000 --- a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: lpcxpresso54114_m0 -name: NXP LPCXpresso54114 M0 -type: mcu -arch: arm -ram: 32 -flash: 64 -testing: - ignore_tags: - - net -toolchain: - - xtools - - zephyr - - gnuarmemb -vendor: nxp diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig b/boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig deleted file mode 100644 index a6a7ebc28a1..00000000000 --- a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_LPC54114_M0=y -CONFIG_SOC_SERIES_LPC54XXX=y -CONFIG_BOARD_LPCXPRESSO54114_M0=y -CONFIG_USE_SEGGER_RTT=y -CONFIG_SERIAL=n -CONFIG_GPIO=n -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 -CONFIG_PINCTRL=y diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m4.yaml b/boards/arm/lpcxpresso54114/lpcxpresso54114_m4.yaml deleted file mode 100644 index d8410a51893..00000000000 --- a/boards/arm/lpcxpresso54114/lpcxpresso54114_m4.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: lpcxpresso54114_m4 -name: NXP LPCXpresso54114 M4 -type: mcu -arch: arm -ram: 64 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - arduino_i2c - - arduino_spi - - gpio - - i2c - - spi -vendor: nxp diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m4_defconfig b/boards/arm/lpcxpresso54114/lpcxpresso54114_m4_defconfig deleted file mode 100644 index 3749cbba716..00000000000 --- a/boards/arm/lpcxpresso54114/lpcxpresso54114_m4_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_LPC54114_M4=y -CONFIG_SOC_SERIES_LPC54XXX=y -CONFIG_BOARD_LPCXPRESSO54114_M4=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/lpcxpresso55s06/Kconfig.board b/boards/arm/lpcxpresso55s06/Kconfig.board deleted file mode 100644 index 516f098775c..00000000000 --- a/boards/arm/lpcxpresso55s06/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso55S06 board - -# Copyright (c) 2022 metraTec -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO55S06 - bool "NXP LPCXPRESSO-55S06" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S06JBD64 diff --git a/boards/arm/lpcxpresso55s06/Kconfig.defconfig b/boards/arm/lpcxpresso55s06/Kconfig.defconfig deleted file mode 100644 index 48340c5f589..00000000000 --- a/boards/arm/lpcxpresso55s06/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# LPCXpresso55S06 board - -# Copyright (c) 2022 metraTec -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO55S06 - -config BOARD - default "lpcxpresso55s06" - -if BOOTLOADER_MCUBOOT -choice MCUBOOT_BOOTLOADER_MODE - # Board only supports MCUBoot via "upgrade only" method: - default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY -endchoice -endif #BOOTLOADER_MCUBOOT - -endif # BOARD_LPCXPRESSO55S06 diff --git a/boards/arm/lpcxpresso55s06/lpcxpresso55s06_defconfig b/boards/arm/lpcxpresso55s06/lpcxpresso55s06_defconfig deleted file mode 100644 index a743b67e2fd..00000000000 --- a/boards/arm/lpcxpresso55s06/lpcxpresso55s06_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2022 metraTec -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S06=y -CONFIG_BOARD_LPCXPRESSO55S06=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_ARM_MPU=y - -CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s16/Kconfig.board b/boards/arm/lpcxpresso55s16/Kconfig.board deleted file mode 100644 index 0a39989427f..00000000000 --- a/boards/arm/lpcxpresso55s16/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso55S16 board - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO55S16 - bool "NXP LPCXPRESSO-55S16" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S16JBD100 diff --git a/boards/arm/lpcxpresso55s16/Kconfig.defconfig b/boards/arm/lpcxpresso55s16/Kconfig.defconfig deleted file mode 100644 index 2979ac8808d..00000000000 --- a/boards/arm/lpcxpresso55s16/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# LPCXpresso55S16 board - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO55S16 - -config BOARD - default "lpcxpresso55S16" - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -if BOOTLOADER_MCUBOOT -choice MCUBOOT_BOOTLOADER_MODE - # Board only supports MCUBoot via "upgrade only" method: - default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY -endchoice -endif #BOOTLOADER_MCUBOOT - -endif # BOARD_LPCXPRESSO55S16 diff --git a/boards/arm/lpcxpresso55s28/Kconfig.board b/boards/arm/lpcxpresso55s28/Kconfig.board deleted file mode 100644 index 871dd381a1f..00000000000 --- a/boards/arm/lpcxpresso55s28/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso55S28 board - -# Copyright (c) 2020 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO55S28 - bool "NXP LPCXPRESSO-55S28" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S28JBD100 diff --git a/boards/arm/lpcxpresso55s28/Kconfig.defconfig b/boards/arm/lpcxpresso55s28/Kconfig.defconfig deleted file mode 100644 index ee3fd9685c4..00000000000 --- a/boards/arm/lpcxpresso55s28/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# LPCXpresso55S28 board - -# Copyright (c) 2020 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO55S28 - -config BOARD - default "lpcxpresso55S28" - -if FXOS8700 - -choice FXOS8700_MODE - default FXOS8700_MODE_ACCEL -endchoice - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -endif # FXOS8700 - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_LPCXPRESSO55S28 && TRUSTED_EXECUTION_SECURE - -if BOOTLOADER_MCUBOOT -choice MCUBOOT_BOOTLOADER_MODE - # Board only supports MCUBoot via "upgrade only" method: - default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY -endchoice -endif #BOOTLOADER_MCUBOOT - -endif # BOARD_LPCXPRESSO55S28 diff --git a/boards/arm/lpcxpresso55s36/Kconfig.board b/boards/arm/lpcxpresso55s36/Kconfig.board deleted file mode 100644 index afa4f113385..00000000000 --- a/boards/arm/lpcxpresso55s36/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso55S36 board - -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO55S36 - bool "NXP LPCXPRESSO-55S36" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S36JBD100 diff --git a/boards/arm/lpcxpresso55s36/lpcxpresso55s36_defconfig b/boards/arm/lpcxpresso55s36/lpcxpresso55s36_defconfig deleted file mode 100644 index 4bf154138af..00000000000 --- a/boards/arm/lpcxpresso55s36/lpcxpresso55s36_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S36=y -CONFIG_BOARD_LPCXPRESSO55S36=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_ARM_MPU=y - -CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s69/Kconfig.board b/boards/arm/lpcxpresso55s69/Kconfig.board deleted file mode 100644 index afdf017e36b..00000000000 --- a/boards/arm/lpcxpresso55s69/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# LPCXpresso55S69 board - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO55S69_CPU0 - bool "NXP LPCXPRESSO-55S69 [CPU0]" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S69JBD100 - -config BOARD_LPCXPRESSO55S69_CPU1 - bool "NXP LPCXPRESSO-55S69 [CPU1]" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S69JBD100 diff --git a/boards/arm/lpcxpresso55s69/Kconfig.defconfig b/boards/arm/lpcxpresso55s69/Kconfig.defconfig deleted file mode 100644 index c8bc5421e09..00000000000 --- a/boards/arm/lpcxpresso55s69/Kconfig.defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# LPCXpresso55S69 board - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO55S69_CPU0 || BOARD_LPCXPRESSO55S69_CPU1 - -config BOARD - default "lpcxpresso55S69_cpu0" if BOARD_LPCXPRESSO55S69_CPU0 - default "lpcxpresso55S69_cpu1" if BOARD_LPCXPRESSO55S69_CPU1 - -if FXOS8700 - -choice FXOS8700_MODE - default FXOS8700_MODE_ACCEL -endchoice - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -endif # FXOS8700 - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_LPCXPRESSO55S69_CPU0 && TRUSTED_EXECUTION_SECURE - -if TRUSTED_EXECUTION_NONSECURE || BOARD_LPCXPRESSO55S69_CPU1 - -config FLASH_LOAD_OFFSET - default 0x50000 if (!TFM_BL2 && BUILD_WITH_TFM) - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default 0x40000 if (!TFM_BL2 && BUILD_WITH_TFM) - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # TRUSTED_EXECUTION_NONSECURE || BOARD_LPCXPRESSO55S69_CPU1 - -choice TFM_PROFILE_TYPE - depends on BUILD_WITH_TFM - default TFM_PROFILE_TYPE_MEDIUM -endchoice - -if BOOTLOADER_MCUBOOT -choice MCUBOOT_BOOTLOADER_MODE - # Board only supports MCUBoot via "upgrade only" method: - default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY -endchoice -endif #BOOTLOADER_MCUBOOT - -endif # BOARD_LPCXPRESSO55S69_CPU0 || BOARD_LPCXPRESSO55S69_CPU1 diff --git a/boards/arm/lpcxpresso55s69/board.cmake b/boards/arm/lpcxpresso55s69/board.cmake deleted file mode 100644 index ed9aedf4f4e..00000000000 --- a/boards/arm/lpcxpresso55s69/board.cmake +++ /dev/null @@ -1,28 +0,0 @@ -# -# Copyright 2019, 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - - -## DAP Link implementation in pyocd is underway, -## until then jlink can be used or copy image to storage - -if(CONFIG_BOARD_LPCXPRESSO55S69_CPU0 OR CONFIG_SECOND_CORE_MCUX) -board_runner_args(jlink "--device=LPC55S69_M33_0") -board_runner_args(linkserver "--device=LPC55S69:LPCXpresso55S69") -board_runner_args(linkserver "--override=/device/memory/0/flash-driver=LPC55xx_S.cfx") -board_runner_args(linkserver "--override=/device/memory/0/location=0x10000000") -elseif(CONFIG_BOARD_LPCXPRESSO55S69_CPU1) -board_runner_args(jlink "--device=LPC55S69_M33_1") -endif() - -board_runner_args(pyocd "--target=lpc55s69") - -if(CONFIG_BUILD_WITH_TFM) - set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) -endif() - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/arm/lpcxpresso55s69/doc/index.rst b/boards/arm/lpcxpresso55s69/doc/index.rst deleted file mode 100644 index 1f8d46cef48..00000000000 --- a/boards/arm/lpcxpresso55s69/doc/index.rst +++ /dev/null @@ -1,413 +0,0 @@ -.. _lpcxpresso55s69: - -NXP LPCXPRESSO55S69 -################### - -Overview -******** - -The LPCXpresso55S69 development board provides the ideal platform for evaluation -of and development with the LPC55S6x MCU based on the Arm® Cortex®-M33 -architecture. The board includes a high performance onboard debug probe, audio -subsystem, and accelerometer, with several options for adding off-the-shelf -add-on boards for networking, sensors, displays, and other interfaces. - -.. image:: lpcxpresso55s69.jpg - :align: center - :alt: LPCXPRESSO55S69 - -Hardware -******** - -- LPC55S69 dual core Arm Cortex-M33 microcontroller running at up to 100 MHz -- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER J-Link - protocol options -- UART and SPI port bridging from LPC55S69 target to USB via the onboard debug - probe -- Hardware support for external debug probe -- 3 x user LEDs, plus Reset, ISP (3) and user buttons -- Micro SD card slot (4-bit SDIO) -- NXP MMA8652FCR1 accelerometer -- Stereo audio codec with line in/out -- High and full speed USB ports with micro A/B connector for host or device - functionality -- MikroEletronika Click expansion option -- LPCXpresso-V3 expansion option compatible with Arduino UNO -- PMod compatible expansion / host connector - -For more information about the LPC55S69 SoC and LPCXPRESSO55S69 board, see: - -- `LPC55S69 SoC Website`_ -- `LPC55S69 Datasheet`_ -- `LPC55S69 Reference Manual`_ -- `LPCXPRESSO55S69 Website`_ -- `LPCXPRESSO55S69 User Guide`_ -- `LPCXPRESSO55S69 Schematics`_ -- `LPCXPRESSO55S69 Debug Firmware`_ - -Supported Features -================== - -NXP considers the LPCXpresso55S69 as the superset board for the LPC55xx -series of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire LPC55xx series. NXP prioritizes enabling -this board with new support for Zephyr features. The lpcxpresso55s69 board -configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| IOCON | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WWDT | on-chip | windowed watchdog timer | -+-----------+------------+-------------------------------------+ -| TrustZone | on-chip | Trusted Firmware-M | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| MAILBOX | on-chip | ipm | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| USB HS | on-chip | USB High Speed device | -+-----------+------------+-------------------------------------+ -| USB FS | on-chip | USB Full Speed device | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | entropy; | -| | | random | -+-----------+------------+-------------------------------------+ -| IAP | on-chip | flash programming | -+-----------+------------+-------------------------------------+ -| SDIF | on-chip | sdhc | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma (on CPU0) | -+-----------+------------+-------------------------------------+ - -Targets available -================== - -The default configuration file -``boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0_defconfig`` -only enables the first core. -CPU0 is the only target that can run standalone. - -- *lpcxpresso55s69_cpu0* secure (S) address space for CPU0 -- *lpcxpresso55s69_ns* non-secure (NS) address space for CPU0 -- *lpcxpresso55s69_cpu1* CPU1 target, no security extensions - -NS target for CPU0 does not work correctly without a secure image to configure -the system, then hand execution over to the NS environment. To enable a secure -image, run any of the ``tfm_integration`` samples. When using the NS target -``CONFIG_BUILD_WITH_TFM`` is always enabled to ensure that a valid S image is -included during the build process. - -CPU1 does not work without CPU0 enabling it. -To enable it, run one of the following samples in ``subsys\ipc``: -- ``ipm_mcux`` -- ``openamp`` - -Connections and IOs -=================== - -The LPC55S69 SoC has IOCON registers, which can be used to configure the -functionality of a pin. - -+---------+-----------------+----------------------------+ -| Name | Function | Usage | -+=========+=================+============================+ -| PIO0_26 | SPI | SPI MOSI | -+---------+-----------------+----------------------------+ -| PIO0_27 | USART | USART TX | -+---------+-----------------+----------------------------+ -| PIO0_29 | USART | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_30 | USART | USART TX | -+---------+-----------------+----------------------------+ -| PIO1_1 | SPI | SPI SSEL | -+---------+-----------------+----------------------------+ -| PIO1_2 | SPI | SPI SCK | -+---------+-----------------+----------------------------+ -| PIO1_3 | SPI | SPI MISO | -+---------+-----------------+----------------------------+ -| PIO1_4 | GPIO | RED LED | -+---------+-----------------+----------------------------+ -| PIO1_6 | GPIO | BLUE_LED | -+---------+-----------------+----------------------------+ -| PIO1_7 | GPIO | GREEN LED | -+---------+-----------------+----------------------------+ -| PIO1_20 | I2C | I2C SCL | -+---------+-----------------+----------------------------+ -| PIO1_21 | I2C | I2C SDA | -+---------+-----------------+----------------------------+ -| PIO1_24 | USART | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_20 | I2S | I2S DATAOUT | -+---------+-----------------+----------------------------+ -| PIO0_19 | I2S | I2S TX WS | -+---------+-----------------+----------------------------+ -| PIO0_21 | I2S | I2S TX SCK | -+---------+-----------------+----------------------------+ -| PIO1_13 | I2S | I2S DATAIN | -+---------+-----------------+----------------------------+ -| PIO0_15 | SCT0_OUT2 | PWM | -+---------+-----------------+----------------------------+ -| PIO0_24 | SD0_D0 | SDHC | -+---------+-----------------+----------------------------+ -| PIO0_25 | SD0_D1 | SDHC | -+---------+-----------------+----------------------------+ -| PIO0_31 | SD0_D2 | SDHC | -+---------+-----------------+----------------------------+ -| PIO0_7 | SD0_CLK | SDHC | -+---------+-----------------+----------------------------+ -| PIO0_8 | SD0_CMD | SDHC | -+---------+-----------------+----------------------------+ -| PIO0_9 | SD0_POW_EN | SDHC | -+---------+-----------------+----------------------------+ -| PIO1_0 | SD0_D3 | SDHC | -+---------+-----------------+----------------------------+ - -Memory mappings -=============== - -There are multiple memory configurations, they all start from the -MCUboot partitioning which looks like the table below - -+----------+------------------+---------------------------------+ -| Name | Address[Size] | Comment | -+==========+==================+=================================+ -| boot | 0x00000000[32K] | Bootloader | -+----------+------------------+---------------------------------+ -| slot0 | 0x00008000[160k] | Image that runs after boot | -+----------+------------------+---------------------------------+ -| slot0_ns | 0x00030000[96k] | Second image, core 1 or NS | -+----------+------------------+---------------------------------+ -| slot1 | 0x00048000[160k] | Updates slot0 image | -+----------+------------------+---------------------------------+ -| slot1_ns | 0x00070000[96k] | Updates slot0_ns image | -+----------+------------------+---------------------------------+ -| storage | 0x00088000[50k] | File system, persistent storage | -+----------+------------------+---------------------------------+ - -See below examples of how this partitioning is used - -Trusted Execution -***************** - -+-----------+------------------+--------------------+ -| Memory | Address[Size] | Comment | -+===========+==================+====================+ -| MCUboot | 0x00000000[32K] | Secure bootloader | -+-----------+------------------+--------------------+ -| TFM_S | 0x00008000[160k] | Secure image | -+-----------+------------------+--------------------+ -| Zephyr_NS | 0x00030000[96k] | Non-Secure image | -+-----------+------------------+--------------------+ -| storage | 0x00088000[50k] | Persistent storage | -+-----------+------------------+--------------------+ - -+----------------+------------------+-------------------+ -| RAM | Address[Size] | Comment | -+================+==================+===================+ -| secure_ram | 0x20000000[136k] | Secure memory | -+----------------+------------------+-------------------+ -| non_secure_ram | 0x20022000[136k] | Non-Secure memory | -+----------------+------------------+-------------------+ - -Dual Core samples -***************** - -+--------+------------------+----------------------------+ -| Memory | Address[Size] | Comment | -+========+==================+============================+ -| CPU0 | 0x00000000[630K] | CPU0, can access all flash | -+--------+------------------+----------------------------+ -| CPU1 | 0x00030000[96k] | CPU1, has no MPU | -+--------+------------------+----------------------------+ - -+-------+------------------+-----------------------+ -| RAM | Address[Size] | Comment | -+=======+==================+=======================+ -| sram0 | 0x20000000[64k] | CPU0 memory | -+-------+------------------+-----------------------+ -| sram3 | 0x20030000[64k] | CPU1 memory | -+-------+------------------+-----------------------+ -| sram4 | 0x20040000[16k] | Mailbox/shared memory | -+-------+------------------+-----------------------+ - -System Clock -============ - -The LPC55S69 SoC is configured to use PLL1 clocked from the external 16MHz -crystal, running at 144MHz as a source for the system clock. When the flash -controller is enabled, the core clock will be reduced to 96MHz. The application -may reconfigure clocks after initialization, provided that the core clock is -always set to 96MHz when flash programming operations are performed. - -Serial Port -=========== - -The LPC55S69 SoC has 8 FLEXCOMM interfaces for serial communication. One is -configured as USART for the console and the remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe, -however the :ref:`pyocd-debug-host-tools` does not yet support this probe so you -must reconfigure the board for one of the following debug probes instead. - -:ref:`lpclink2-jlink-onboard-debug-probe` ------------------------------------------ - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program -the J-Link firmware. Please make sure you have the latest firmware for this -board. - -:ref:`lpclink2-cmsis-onboard-debug-probe` ------------------------------------------ - - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware` - -:ref:`opensda-daplink-onboard-debug-probe` ------------------------------------------- - -PyOCD support for this board is ongoing and not yet available. -To use DAPLink's flash memory programming on this board, follow the instructions -for `updating LPCXpresso firmware`_. - -Configuring a Console -===================== - -Connect a USB cable from your PC to P6, and use the serial terminal of your choice -(minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`jlink-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lpcxpresso55s69_cpu0 - :goals: flash - -Open a serial terminal, reset the board (press the RESET button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0 ***** - Hello World! lpcxpresso55s69_cpu0 - -Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| ----------------------------------------------------------------------- -The TF-M integration samples can be run using the ``lpcxpresso55s69_ns`` target. -To run we need to manually flash the resulting image (``tfm_merged.hex``) with -a J-Link as follows (reset and erase are for recovering a locked core): - - .. code-block:: console - - JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1 - J-Link>r - J-Link>erase - J-Link>loadfile build/zephyr/tfm_merged.hex - -We need to reset the board manually after flashing the image to run this code. - -Building a dual-core image --------------------------- -The dual-core samples are run using ``lpcxpresso55s69_cpu0`` target, -``lpcxpresso55s69_cpu1`` will be automatically built and merged in a single -image when ``SECOND_CORE_MCUX`` is selected. -To run we need to manually flash the resulting image (``multicore.bin``) with a -J-Link as follows (reset and erase are for recovering a locked core): - - .. code-block:: console - - JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1 - J-Link>r - J-Link>erase - J-Link>loadfile build/multicore.bin - -We need to reset the board manually after flashing the image to run this code. - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`jlink-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lpcxpresso55s69_cpu0 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS zephyr-v1.14.0 ***** - Hello World! lpcxpresso55s69_cpu0 - -.. _LPC55S69 SoC Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/high-efficiency-arm-cortex-m33-based-microcontroller-family:LPC55S6x - -.. _LPC55S69 Datasheet: - https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf - -.. _LPC55S69 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=UM11126 - -.. _LPCXPRESSO55S69 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/lpcxpresso55s69-development-board:LPC55S69-EVK - -.. _LPCXPRESSO55S69 User Guide: - https://www.nxp.com/webapp/Download?colCode=UM11158 - -.. _LPCXPRESSO55S69 Debug Firmware: - https://www.nxp.com/docs/en/application-note/AN13206.pdf - -.. _LPCXPRESSO55S69 Schematics: - https://www.nxp.com/webapp/Download?colCode=LPC55S69-SCH - -.. _updating LPCXpresso firmware: - https://os.mbed.com/teams/NXP/wiki/Updating-LPCXpresso-firmware diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml deleted file mode 100644 index d0bafc9cd4b..00000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: lpcxpresso55s69_cpu0 -name: NXP LPCXpresso55S69 (CPU0) -type: mcu -arch: arm -ram: 64 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - arduino_i2c - - arduino_serial - - arduino_spi - - counter - - gpio - - i2c - - i2s - - spi - - sdhc - - usb_device - - watchdog -vendor: nxp diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0_defconfig b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0_defconfig deleted file mode 100644 index ece94dd0b6f..00000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S69_CPU0=y -CONFIG_BOARD_LPCXPRESSO55S69_CPU0=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y - -# Enable TrustZone-M -CONFIG_TRUSTED_EXECUTION_SECURE=y -CONFIG_ARM_TRUSTZONE_M=y - -CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.yaml b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.yaml deleted file mode 100644 index 818d29535fa..00000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: lpcxpresso55s69_cpu1 -name: NXP LPCXpresso55S69 (CPU1) -type: mcu -arch: arm -ram: 64 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio -vendor: nxp diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1_defconfig b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1_defconfig deleted file mode 100644 index d93ccd89329..00000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S69_CPU1=y -CONFIG_BOARD_LPCXPRESSO55S69_CPU1=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y - -CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.yaml b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.yaml deleted file mode 100644 index d7333e026d7..00000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: lpcxpresso55s69_ns -name: NXP LPCXpresso55S69 (Non-Secure) -type: mcu -arch: arm -ram: 136 -flash: 96 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - arduino_spi - - counter - - dma - - gpio - - spi - - watchdog -vendor: nxp diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns_defconfig b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns_defconfig deleted file mode 100644 index 451a92a74a6..00000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S69_CPU0=y -CONFIG_BOARD_LPCXPRESSO55S69_CPU0=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y - -# TFM sets up MPU_NS, can't correctly change this configuration yet -CONFIG_ARM_MPU=n - -# Enable TrustZone-M -CONFIG_TRUSTED_EXECUTION_NONSECURE=y -CONFIG_RUNTIME_NMI=y -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_BUILD_WITH_TFM=y - -CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/mec1501modular_assy6885/Kconfig.board b/boards/arm/mec1501modular_assy6885/Kconfig.board deleted file mode 100644 index 0e9b720abb7..00000000000 --- a/boards/arm/mec1501modular_assy6885/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MEC1501MODULAR_ASSY6885 - bool "Microchip MEC1501 Modular ASSY 6885 Development board" - depends on SOC_MEC1501_HSZ diff --git a/boards/arm/mec1501modular_assy6885/Kconfig.defconfig b/boards/arm/mec1501modular_assy6885/Kconfig.defconfig deleted file mode 100644 index b22c410d8a3..00000000000 --- a/boards/arm/mec1501modular_assy6885/Kconfig.defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (c) 2019 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MEC1501MODULAR_ASSY6885 - -config BOARD - default "mec1501modular_assy6885" - -#PS/2 driver is compiled in terms of this flag. -config ESPI_PERIPHERAL_8042_KBC - default y - depends on ESPI_XEC - -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 -# The driver requires tickless mode and ticks per -# second to be 32768 for accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 48MHz divided by -# SOC_MEC1501_PROC_CLK_DIV. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -if ESPI - -config ESPI_PERIPHERAL_UART_SOC_MAPPING - default 1 - -endif # ESPI - -endif # RTOS_TIMER - -endif # BOARD_MEC1501MODULAR_ASSY6885 diff --git a/boards/arm/mec1501modular_assy6885/doc/index.rst b/boards/arm/mec1501modular_assy6885/doc/index.rst deleted file mode 100644 index cd1f8ef8b25..00000000000 --- a/boards/arm/mec1501modular_assy6885/doc/index.rst +++ /dev/null @@ -1,321 +0,0 @@ -.. _mec1501modular_assy6885: - -Microchip MEC1501 Modular card ASSY6885 -####################################### - -Overview -******** - -The MEC1501 Modular card ASSY6885 is a development board to evaluate the Microchip -MEC152X series microcontrollers. This board can work standalone or be mated with -any platform that complies with MECC specification. - -.. image:: mec1501modular_assy6885.jpg - :align: center - :alt: MEC1501 Modular ASSY 6885 - -Hardware -******** - -- MEC1521HA0SZ ARM Cortex-M4 Processor -- 256 KB RAM and 64 KB boot ROM -- GPIO headers -- UART1 using microUSB -- PECI interface 3.0 -- 10 SMBUS instances -- FAN, PMW and TACHO pins -- VCI interface -- Independent Hardware Driven PS/2 Ports - -At difference from MEC15xx evaluation board, modular MEC1521 exposes the pins -in 2 different ways: - -1) Standalone mode via headers - - - GPIOs - - PWM5 - - JTAG/SWD, ETM and MCHP Trace ports - - eSPI bus - - SMB0 - -2) Mated mode with another platform that has a high density MECC connector. - - - FAN0, PWM0, SMB0, SMB1, SMB4 and SMB5 - - eSPI bus - - Breathing/Blinking LEDs - -The board is powered through the +5V USB Micro A connector or from the MECC connector. - - -For more information about the SOC please see the `MEC152x Reference Manual`_ - -Supported Features -================== - -The mec1501modular_assy6885 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ESPI | on-chip | espi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| RTOS | on-chip | timer | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| PS2 | on-chip | ps2 | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the -:zephyr_file:`boards/arm/mec1501modular_assy6885/mec1501modular_assy6885_defconfig` -Kconfig file. - -Connections and IOs -=================== - -This evaluation board kit is comprised of the following HW blocks: - -- MEC1501 Modular Card ASSY 6885 Rev A0 `MEC1501 Modular EC Card - Assy_6885 Rev A0p1`_ - -System Clock -============ - -The MEC1501 MCU is configured to use the 48Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock -control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in -the references at the end of this document. - -Serial Port -=========== -UART1 is configured for serial logs. - -Jumper settings -*************** - -Please follow the jumper settings below to properly demo this -board. Advanced users may deviate from this recommendation. - -Jumper setting for MEC1501 Modular Assy 6885 Rev A1p0 -===================================================== - -Power-related jumpers ---------------------- - -If you wish to power from type A/B connector ``P10`` set the jumper ``JP35 1-2``. - -If you wish to power through MECC connector ``P1`` and mate to external platform, -set the jumper to ``JP35 3-4``. - -.. note:: A single jumper is required in JP35. - -+------+---------+---------+------+------+------+----------+ -| JP30 | JP31 | JP32 | JP33 | JP34 | JP40 | JP21 | -| VTR3 | VTR_PLL | VTR_REG | VTR1 | VTR2 | 3.3V | VREF_ADC | -+======+=========+=========+======+======+======+==========+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+------+---------+---------+------+------+------+----------+ - - -+------+------------+------+----------+ -| JP6 | JP36 | JP27 | JP4 | -| VBAT | VTR_ANALOG | PECI | VREF_VTT | -+======+============+======+==========+ -| 2-3 | 1-2 | 2-3 | open | -+------+------------+------+----------+ - -These jumpers configure nRESETI and JTAG_STRAP respectively. - -+-----------+---------------+ -| JP22 | JP29 | -| (nRESETI) | (JTAG_STRAP) | -+===========+===============+ -| 11-12 | 1-2 | -+-----------+---------------+ - -Boot-ROM Straps ---------------- - -These jumpers configure MEC1501 Boot-ROM straps. - -+-------------+------------+--------------+-------------+ -| JP37 | J6 | JP41 | JP23 | -| (CMP_STRAP) | (CR_STRAP) | (VTR2_STRAP) | (BSS_STRAP) | -+=============+============+==============+=============+ -| 1-2 | 1-2 | 1-2 | 3-4 | -+-------------+------------+--------------+-------------+ - - -``JP23 3-4`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples -SHD SPI CS0# and if high, it loads code from SHD SPI. -This is the recommended setup. - -+-------------+------------+----------------------------+ -| CR_STRAP | BSS_STRAP | SOURCE | -+-------------+------------+----------------------------+ -| 0 | X | Use 3.3V Private SPI | -+-------------+------------+----------------------------+ -| 1 | 0 | Use eSPI Flash channel | -+-------------+------------+----------------------------+ -| | 1 | Use 3.3V Shared channel(R)| -+-------------+------------+----------------------------+ - -Power management ----------------- -``JP20 2-3`` is required so all GPIOs powered by VTR3 rail worked at 1.8V. - -.. note:: External 1.8V needs to be connected to JP13.1 - -+-------------------+-----------------+ -| JP20 | JP13 | -| (VTR3 selection) | (1.8V source) | -+===================+=================+ -| 2-3 | 1.8V to pin 1 | -+-------------------+-----------------+ - - -Jumper location map -------------------- - -.. code-block:: none - - +--------------------------------------------------------------------------------------+ - | |------------| +----------+ J10 || | - | [BT1] + +------------+ J50 ++ ++ || | - | | JP38 JP43 ++ || || | - | + + + +-+ JP4 + + JP26 || || | - | JP6 + + + + + + + + || || | - | JP31 ++ JP32 JP36 +-+ JP27 + + + + J6 || | - | JP18 JP37 JP41 JP42 ++ | - | ++ + + +--------+ J48 | - | || JP21 + + +--------+ JP22 +----------+ | - | J2 || + JP34 JP30 J11 ++ | - | ++ + J44 || | - | ++ +----------------+ || | - | +---------------+ || + JP24 |----------------| ++ | - | |---------------| ++ + +----------+ +----------------+ J47 | - | JP20 +---------------+ JP23 JP40 +----------+ ++ | - | + ++ JP29 || | - | + + +----------+ + || | - | J52+---------------+ + + +----------+ J5 +-------------+ ++ | - | J45+---------------+ JP33 TP57 JP25 +-------------+ J4 J49 | - | | - | ++ TP4 +----------+ ++ | - | ++ + + + + + + TP61 +----------+ ++ | - | JP28 + + + + + TP65 + TP60 J51 JP35 | - | TP58 JP16 JP11 JP13 JP15 JP10 | - | TP5 | - | TP6 TP1 | - +--------------------------------------------------------------------------------------+ - - -Programming and Debugging -************************* - -Setup -===== - -#. Clone the `MEC152x SPI Image Gen`_ repository or download the files within - that directory. For the pre-production MEC150x use the `MEC150x SPI Image Gen`_ - repository. - -#. Make the image generation available for Zephyr, by making the tool - searchable by path, or by setting an environment variable - ``EVERGLADES_SPI_GEN``, for example: - - .. code-block:: console - - export EVERGLADES_SPI_GEN=/everglades_spi_gen_RomE - - Note that the tools for Linux and Windows have different file names. - For the pre-production MEC1501 SOC use everglades_spi_gen_lin64. - -#. If needed, a custom SPI image configuration file can be specified - to override the default one. - - .. code-block:: console - - export EVERGLADES_SPI_CFG=custom_spi_cfg.txt - - -Building -========== -#. Build :ref:`hello_world` application as you would normally do. - -#. Once you have ``zephyr.bin``, use the `MEC152x SPI Image Gen`_ microchip tool - to create the final binary. You need the output from this tool to flash - in the SHD SPI memory. - -Flashing -======== - -#. Connect Dediprog into header ``J2``. - -#. Flash the SPI NOR ``U3`` at offset 0x0 using Dediprog SF100 - or a similar tool for flashing SPI chips. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the MEC1501MODULAR_ASSY6885 board to your host computer using the - UART1 port and apply power. - - You should see ``"Hello World! mec1501modular_assy6885"`` in your terminal. - -Debugging -========= -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG only sessions. - -HW Issues -========= -In case you don't see your application running, please make sure ``LED1`` is lit. -If is off, then check the power related jumpers again. - -References -********** -.. target-notes:: - -.. _MEC152x Preliminary Data Sheet: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf -.. _MEC152x Reference Manual: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf -.. _MEC1501 Modular EC Card - Assy_6885 Rev A0p1: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501%20Modular%20EC%20Card%20-%20Assy_6885%20Rev%20A0p1%20-%20SCH.pdf -.. _MEC152x SPI Image Gen: - https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC152x/SPI_image_gen -.. _MEC150x SPI Image Gen: - https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC1501/SPI_image_gen diff --git a/boards/arm/mec15xxevb_assy6853/Kconfig.board b/boards/arm/mec15xxevb_assy6853/Kconfig.board deleted file mode 100644 index fb7158fb795..00000000000 --- a/boards/arm/mec15xxevb_assy6853/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MEC15XXEVB_ASSY6853 - bool "Microchip MEC15XX EVB ASSY 6853 Development board" - depends on SOC_MEC1501_HSZ diff --git a/boards/arm/mec15xxevb_assy6853/Kconfig.defconfig b/boards/arm/mec15xxevb_assy6853/Kconfig.defconfig deleted file mode 100644 index 99c5fbeb1dd..00000000000 --- a/boards/arm/mec15xxevb_assy6853/Kconfig.defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2019 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MEC15XXEVB_ASSY6853 - -config BOARD - default "mec15xxevb_assy6853" - -config ESPI_XEC - default y - depends on ESPI - -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 -# The driver requires tickless mode and ticks per -# second to be 32768 for accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 48MHz divided by -# SOC_MEC1501_PROC_CLK_DIV. -# - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -endif # RTOS_TIMER - -endif # BOARD_MEC15XXEVB_ASSY6853 diff --git a/boards/arm/mec15xxevb_assy6853/doc/index.rst b/boards/arm/mec15xxevb_assy6853/doc/index.rst deleted file mode 100644 index 8497c286096..00000000000 --- a/boards/arm/mec15xxevb_assy6853/doc/index.rst +++ /dev/null @@ -1,467 +0,0 @@ -.. _mec15xxevb_assy6853: - -Microchip MEC15xxEVB ASSY6853 -############################# - -Overview -******** - -The MEC15xxEVB_ASSY6853 kit is a future development platform to evaluate the -Microchip MEC15XX series microcontrollers. This board needs to be mated with -part number MEC1501 144WFBA SOLDER DC ASSY 6860(cpu board) in order to operate. -The MEC152x has superseded the MEC1501 in production. MEC152x is identical to -MEC150x except for an enhanced Boot-ROM SPI loader. The SPI image format has -been updated requiring a new SPI image tool. MEC1501 and MEC152x SPI image -formats are not compatible with each other. Evaluation and cpu boards are -compatible. - -.. image:: mec15xxevb_assy6853.jpg - :align: center - :alt: MEC15XX EVB ASSY 6853 - -Hardware -******** - -- MEC1521HA0SZ ARM Cortex-M4 Processor -- 256 KB RAM and 64 KB boot ROM -- Keyboard interface -- ADC & GPIO headers -- UART0, UART1, and UART2 -- FAN0, FAN1, FAN2 headers -- FAN PWM interface -- JTAG/SWD, ETM and MCHP Trace ports -- PECI interface 3.0 -- I2C voltage translator -- 10 SMBUS headers -- 4 SGPIO headers -- VCI interface -- 5 independent Hardware Driven PS/2 Ports -- eSPI header -- 3 Breathing/Blinking LEDs -- 2 Sockets for SPI NOR chips -- One reset and VCC_PWRDGD pushbuttons -- One external PCA9555 I/O port with jumper selectable I2C address. -- One external LTC2489 delta-sigma ADC with jumper selectable I2C address. -- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector. - -For more information about the SOC's please see `MEC152x Reference Manual`_ - -Supported Features -================== - -The mec15xxevb_assy6853 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PS/2 | on-chip | ps2 | -+-----------+------------+-------------------------------------+ -| KSCAN | on-chip | kscan | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer | -+-----------+------------+-------------------------------------+ - - - - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the -:zephyr_file:`boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig` Kconfig file. - -Connections and IOs -=================== - -This evaluation board kit is comprised of the following HW blocks: - -- MEC15xx EVB ASSY 6853 Rev A `MEC15xx EVB Schematic`_ -- MEC1501 144WFBA SOLDER DC ASSY 6883 with MEC152x silicon `MEC1501 Daughter Card Schematic`_ -- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_ - -System Clock -============ - -The MEC1521 MCU is configured to use the 48Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock -control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in -the references at the end of this document. - -Serial Port -=========== - -UART2 is configured for serial logs. - -Jumper settings -*************** - -Please follow the jumper settings below to properly demo this -board. Advanced users may deviate from this recommendation. - -Jumper setting for MEC15xx EVB Assy 6853 Rev A1p0 -================================================= - -Power-related jumpers ---------------------- - -If you wish to power from +5V power brick, then connect to barrel connector ``P11`` -(5.5mm OD, 2.1mm ID) and move the jumper to ``JP88 5-6``. - -If you wish to power from micro-USB type A/B connector ``P12``, move the -jumper to ``JP88 7-8``. - - -.. note:: A single jumper is required in JP88. - -+-------+------+------+------+------+------+------+------+------+------+------+ -| JP22 | JP32 | JP33 | JP37 | JP43 | JP47 | JP54 | JP56 | JP58 | JP64 | JP65 | -+=======+======+======+======+======+======+======+======+======+======+======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+-------+------+------+------+------+------+------+------+------+------+------+ - -+------+------+------+------+------+------+------+------+------+------+ -| JP72 | JP73 | JP76 | JP79 | JP80 | JP81 | JP82 | JP84 | JP87 | JP89 | -+======+======+======+======+======+======+======+======+======+======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+------+------+------+------+------+------+------+------+------+------+ - -+------+------+-------+-------+-------+ -| JP90 | JP91 | JP100 | JP101 | JP118 | -+======+======+=======+=======+=======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 2-3 | -+------+------+-------+-------+-------+ - -These jumpers configure VCC Power good, nRESETI and JTAG_STRAP respectively. - -+------------------+-----------+--------------+ -| JP5 | JP4 | JP45 | -| (VCC Power good) | (nRESETI) | (JTAG_STRAP) | -+==================+===========+==============+ -| 1-2 | 1-2 | 2-3 | -+------------------+-----------+--------------+ - -Boot-ROM Straps. ----------------- - -These jumpers configure MEC1501 Boot-ROM straps. - -+-------------+------------+--------------+-------------+ -| JP93 | JP11 | JP46 | JP96 | -| (CMP_STRAP) | (CR_STRAP) | (VTR2_STRAP) | (BSS_STRAP) | -+=============+============+==============+=============+ -| 2-3 | 1-2 | 2-3 | 1-2 | -+-------------+------------+--------------+-------------+ - -``JP96 1-2`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples -SHD SPI CS0# and if high, it loads code from SHD SPI. - -Peripheral Routing Jumpers --------------------------- - -Each column of the following table illustrates how to enable UART2, SWD, -PVT SPI, SHD SPI and LED0-2 respectively. - -+----------+----------+--------+-----------+----------+---------+ -| JP48 | JP9 | JP9 | JP38 | JP98 | JP41 | -| (UART2) | (UART2) | (SWD) | (PVT SPI) | (SHD SPI)| (LED0-2)| -+==========+==========+========+===========+==========+=========+ -| 1-2 | | 2-3 | 2-3 | 2-3 | 1-2 | -+----------+----------+--------+-----------+----------+---------+ -| 4-5 | 4-5 | | 5-6 | 5-6 | 3-4 | -+----------+----------+--------+-----------+----------+---------+ -| 7-8 | | 8-9 | 8-9 | 8-9 | 5-6 | -+----------+----------+--------+-----------+----------+---------+ -| 10-11 | 10-11 | | 11-12 | 11-12 | | -+----------+----------+--------+-----------+----------+---------+ -| | | | 14-15 | 14-15 | | -+----------+----------+--------+-----------+----------+---------+ -| | | | 17-18 | 20-21 | | -+----------+----------+--------+-----------+----------+---------+ - -.. note:: For UART2 make sure JP39 have jumpers connected 1-2, 3-4. - -To receive UART2 serial output, please refer to the picture below -to make sure that JP9 configured for UART2 output. - -.. image:: mec15xxevb_assy6853_jp9_1.jpg - :align: center - :alt: JP9 header Assy6853 - -Jumper settings for MEC1501 144WFBGA Socket DC Assy 6883 Rev B1p0 -================================================================= - -The jumper configuration explained above covers the base board. The ASSY -6883 MEC1501 CPU board provides capability for an optional, external 32KHz -clock source. The card includes a 32KHz crystal oscillator. The card can -also be configured to use an external 50% duty cycle 32KHz source on the -XTAL2/32KHZ_IN pin. Note, firmware must set the MEC15xx clock enable -register to select the external source matching the jumper settings. If -using the MEC15xx internal silicon oscillator then the 32K jumper settings -are don't cares. ``JP1`` is for scoping test clock outputs. Please refer to -the schematic in reference section below. - -Parallel 32KHz crystal configuration ------------------------------------- -+-------+-------+ -| JP2 | JP3 | -+=======+=======+ -| 1-2 | 2-3 | -+-------+-------+ - -External 32KHz 50% duty cycle configuration -------------------------------------------- -+-------+-------+ -| JP2 | JP3 | -+=======+=======+ -| NC | 1-2 | -+-------+-------+ - - -Jumper settings for MEC1503 144WFBGA Socket DC Assy 6856 Rev B1p0 -================================================================= - -The MEC1503 ASSY 6856 CPU card does not include an onboard external -32K crystal or oscillator. The one jumper block ``JP1`` is for scoping -test clock outputs not for configuration. Please refer to schematic -in reference section below. - -Programming and Debugging -************************* - -Setup -===== -#. If you use Dediprog SF100 programmer, then setup it. - - Windows version can be found at the `SF100 Product page`_. - - Linux version source code can be found at `SF100 Linux GitHub`_. - Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer. - For Linux please make sure that you copied ``60-dediprog.rules`` - from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d) - then restart service using: - - .. code-block:: console - - $ udevadm control --reload - - Add directory with program ``dpcmd`` (on Linux) - or ``dpcmd.exe`` (on Windows) to your ``PATH``. - -#. Clone the `MEC152x SPI Image Gen`_ repository or download the files within - that directory. For the pre-production MEC150x use `MEC150x SPI Image Gen`_ - repository. - -#. Make the image generation available for Zephyr, by making the tool - searchable by path, or by setting an environment variable - ``EVERGLADES_SPI_GEN``, for example: - - .. code-block:: console - - export EVERGLADES_SPI_GEN=/everglades_spi_gen_RomE - - Note that the tools for Linux and Windows have different file names. - For the pre-production MEC1501 SOC use everglades_spi_gen_lin64. - -#. If needed, a custom SPI image configuration file can be specified - to override the default one. - - .. code-block:: console - - export EVERGLADES_SPI_CFG=custom_spi_cfg.txt - -Wiring -======== -#. Connect the SPI Dongle ASSY 6791 to ``J44`` in the EVB. - - .. image:: spidongle_assy6791_view1.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - -#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip ``U3`` - Make sure that your programmer's offset is 0x0. - For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips. - - .. list-table:: Microchip board wiring - :align: center - - * - - .. image:: spidongle_assy6791.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 - - - - .. image:: spidongle_assy6791_view2.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 view 2 - - | - - .. image:: dediprog_connector_2.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - - - .. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers! - Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board. - Wiring connection is described in the table below. - - +------------+---------------+ - | Dediprog | Assy6791 | - | Connector | J6 Connector | - +============+===============+ - | VCC | 1 | - +------------+---------------+ - | GND | 2 | - +------------+---------------+ - | CS | 3 | - +------------+---------------+ - | CLK | 4 | - +------------+---------------+ - | MISO | 6 | - +------------+---------------+ - | MOSI | 5 | - +------------+---------------+ - -#. Connect UART2 port of the MEC15xxEVB_ASSY_6853 board - to your host computer using the RS232 cable. - -#. Apply power to the board via a micro-USB cable. - Configure this option by using a jumper between ``JP88 7-8``. - - .. image:: jp88_power_options.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - -#. Final wiring for the board should look like this: - - .. image:: mec_board_setup.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - -Building -======== -#. Build :ref:`hello_world` application as you would normally do. - -#. The file :file:`spi_image.bin` will be created if the build system - can find the image generation tool. This binary image can be used - to flash the SPI chip. - -Flashing -======== -#. Run your favorite terminal program to listen for output. - Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. - - For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Flash your board using ``west`` from the second terminal window. - Split first and second terminal windows to view both of them. - - .. code-block:: console - - $ west flash - - .. note:: When west process started press Reset button and do not release it - till the whole west process will not be finished successfully. - - .. image:: reset_button_1.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - - - .. note:: If you don't want to press Reset button every time, you can disconnect - SPI Dongle ASSY 6791 from the EVB during the west flash programming. - Then connect it back to the ``J44`` header and apply power to the EVB. - Result will be the same. - - -#. You should see ``"Hello World! mec15xxevb_assy6853"`` in the first terminal window. - If you don't see this message, press the Reset button and the message should appear. - -Debugging -========= -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG only sessions. - -Troubleshooting -=============== -#. In case you don't see your application running, please make sure ``LED7``, ``LED8``, and ``LED1`` - are lit. If one of these is off, then check the power-related jumpers again. - -#. If you can't program the board using Dediprog, disconnect the Assy6791 - from the main board Assy6853 and try again. - -#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again. - -Notes -===== -#. To enable PCA9555PW and test the I2C on mec15xxevb_assy6853, additional works are needed: - - As the I2C slave device NXP pca95xx on mec15xxevb_assy6853 is connected to I2C00 port, - however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log, - so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use - I2C01 port by making some jumpers setting as below: - - * JP99 1-2 Connected Connect I2C01_SDA from CPU to header J5 - * JP99 13-14 Connected Connect I2C01_SCL from CPU to header J5 - * JP25 21-22 Connected External pull-up for I2C01_SDA - * JP25 23-24 Connected External pull-up for I2C01_SCL - * - * JP44.1 J5.1 Connected Connect NXP PCA95xx to I2C01 - * JP44.3 J5.3 Connected Connect NXP PCA95xx to I2C01 - - -References -********** -.. target-notes:: - -.. _MEC1501 Preliminary Data Sheet: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501_Datasheet.pdf -.. _MEC1501 Reference Manual: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501_Datasheet.pdf -.. _MEC152x Preliminary Data Sheet: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf -.. _MEC152x Reference Manual: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf -.. _MEC15xx EVB Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/Everglades%20EVB%20-%20Assy_6853%20Rev%20A1p1%20-%20SCH.pdf -.. _MEC1501 Daughter Card Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501%20Socket%20DC%20for%20EVERGLADES%20EVB%20-%20Assy_6883%20Rev%20A0p1%20-%20SCH.pdf -.. _MEC1503 Daughter Card Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1503%20Socket%20DC%20for%20EVERGLADES%20EVB%20-%20Assy_6856%20Rev%20A1p0%20-%20SCH.pdf -.. _SPI Dongle Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/SPI%20Dongles%20and%20Aardvark%20Interposer%20Assy%206791%20Rev%20A1p1%20-%20SCH.pdf -.. _MEC152x SPI Image Gen: - https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC152x/SPI_image_gen -.. _MEC150x SPI Image Gen: - https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC1501/SPI_image_gen -.. _SF100 Linux GitHub: - https://github.com/DediProgSW/SF100Linux -.. _SF100 Product page: - https://www.dediprog.com/product/SF100 -.. _SF100 Linux manual: - https://www.dediprog.com/download/save/727.pdf diff --git a/boards/arm/mec172xevb_assy6906/Kconfig.board b/boards/arm/mec172xevb_assy6906/Kconfig.board deleted file mode 100644 index df628d000ee..00000000000 --- a/boards/arm/mec172xevb_assy6906/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021, Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MEC172XEVB_ASSY6906 - bool "Microchip MEC172X EVB ASSY 6906 Development board" - depends on SOC_MEC172X_NSZ diff --git a/boards/arm/mec172xevb_assy6906/Kconfig.defconfig b/boards/arm/mec172xevb_assy6906/Kconfig.defconfig deleted file mode 100644 index 8b23b520e1f..00000000000 --- a/boards/arm/mec172xevb_assy6906/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2021 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MEC172XEVB_ASSY6906 - -config BOARD - default "mec172xevb_assy6906" - -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 Hz. -# The driver requires tickless mode and ticks per second to be 32768 for -# accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR -# processor clock divider register. We assume PCR processor clock divider -# is set to 1. Refer to SOC_MEC172X_PROC_CLK_DIV -# - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 96000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -endif # RTOS_TIMER - -endif # BOARD_MEC172XEVB_ASSY6906 diff --git a/boards/arm/mec172xevb_assy6906/doc/index.rst b/boards/arm/mec172xevb_assy6906/doc/index.rst deleted file mode 100644 index b42aba76310..00000000000 --- a/boards/arm/mec172xevb_assy6906/doc/index.rst +++ /dev/null @@ -1,479 +0,0 @@ -.. _mec172xevb_assy6906: - -Microchip MEC172xEVB ASSY6906 -############################# - -Overview -******** - -The MEC172xEVB_ASSY6906 kit is a future development platform to evaluate the -Microchip MEC172X series microcontrollers. This board needs to be mated with -part number MEC172x 144WFBGA SOLDER DC ASSY 6914 (cpu board) in order to operate. -MEC172x and MEC152x SPI image formats are not compatible with each other. - -.. image:: mec172xevb_assy6906.jpg - :align: center - :alt: MEC172X EVB ASSY 6906 - -Hardware -******** - -- MEC172x ARM Cortex-M4 Processor -- 416 KB RAM and 128 KB boot ROM -- Keyboard interface -- ADC & GPIO headers -- UART0 and UART1 -- FAN0, FAN1, FAN2 headers -- FAN PWM interface -- JTAG/SWD, ETM and MCHP Trace ports -- PECI interface 3.0 -- I2C voltage translator -- 10 SMBUS headers -- VCI interface -- 1 Hardware Driven PS/2 Port -- eSPI header -- 2 Sockets for SPI NOR chips -- One reset and VCC_PWRDGD pushbuttons -- One external PCA9555 I/O port with jumper selectable I2C address. -- One external LTC2489 delta-sigma ADC with jumper selectable I2C address. -- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector. - -For more information about the SOC's please see `MEC172x Reference Manual`_ - -Supported Features -================== - -The mec172xevb_assy6906 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PS/2 | on-chip | ps2 | -+-----------+------------+-------------------------------------+ -| KSCAN | on-chip | kscan | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer | -+-----------+------------+-------------------------------------+ -| RPMFAN | on-chip | Fan speed controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the -:zephyr_file:`boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig` Kconfig file. - -Connections and IOs -=================== - -This evaluation board kit is comprised of the following HW blocks: - -- MEC172x EVB ASSY 6906 Rev A `MEC172x EVB Schematic`_ -- MEC172x 144WFBGA SOLDER DC ASSY 6914 with MEC172x silicon `MEC172x Daughter Card Schematic`_ -- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_ - -System Clock -============ - -The MEC1723 MCU is configured to use the 96Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock -control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in -the references at the end of this document. - -Serial Port -=========== - -UART1 is configured for serial logs. - -Jumper settings -*************** - -Please follow the jumper settings below to properly demo this -board. Advanced users may deviate from this recommendation. - -Jumper setting for MEC172x EVB Assy 6906 Rev A1p0 -================================================= - -Power-related jumpers ---------------------- - -If you wish to power from +5V power brick, then connect to barrel connector ``P1`` -(5.5mm OD, 2.1mm ID) and move the jumper to ``JP30 5-6``. - -If you wish to power from micro-USB type A/B connector ``P2``, move the -jumper to ``JP30 7-8``. - - -.. note:: A single jumper is required in ``JP30``. - -+------+-------+-------+------+------+ -| JP31 | JP158 | JP159 | JP40 | JP42 | -+======+=======+=======+======+======+ -| 2-3 | 2-3 | 2-3 | 1-2 | 1-2 | -+------+-------+-------+------+------+ - -+------+------+------+------+------+------+------+ -| JP36 | JP37 | JP38 | JP39 | JP41 | JP43 | JP44 | -+======+======+======+======+======+======+======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+------+------+------+------+------+------+------+ - -+------+------+------+------+------+------+------+------+------+ -| JP45 | JP46 | JP47 | JP50 | JP51 | JP52 | JP55 | JP56 | JP57 | -+======+======+======+======+======+======+======+======+======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+------+------+------+------+------+------+------+------+------+ - -+------+------+------+------+------+------+------+ -| JP59 | JP60 | JP61 | JP62 | JP63 | JP65 | JP66 | -+======+======+======+======+======+======+======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+------+------+------+------+------+------+------+ - -These jumpers configure VCC Power good and nRESET_IN. - -+------------------+-------------+ -| JP32 | JP33 | -| (VCC Power good) | (nRESET_IN) | -+==================+=============+ -| 1-2 | 1-2 | -+------------------+-------------+ - -Boot-ROM Straps ---------------- - -These jumpers configure MEC172x Boot-ROM straps. - -+------------+--------------+-------------+-------------+---------------+ -| JP1 | JP2 | JP3 | JP7 | JP160 | -| (CR_STRAP) | (JTAG_STRAP) | (CMP_STRAP) | (BSS_STRAP) | (UART_BSTRAP) | -+============+==============+=============+=============+===============+ -| 1-2 | 2-3 | 2-3 | 1-2 | 1-2 | -+------------+--------------+-------------+-------------+---------------+ - -``JP7 1-2`` pulls SHD SPI CS0# up to VTR2. MEC172x Boot-ROM samples -SHD SPI CS0# and if high, it loads code from SHD SPI. - -Peripheral Routing Jumpers --------------------------- - -Each column of the following table illustrates how to enable UART0, UART1, SHD SPI -and SWD, respectively. - -+-------+-------+------+------+------+------+------+ -| UART0 (P11) | -+-------+-------+------+------+------+------+------+ -| JP13 | JP17 | JP19 | JP22 | JP88 | JP89 | JP93 | -+=======+=======+======+======+======+======+======+ -| 2-3 | 2-3 | 1-2 | 1-2 | 2-3 | 2-3 | 1-3 | -+-------+-------+------+------+------+------+------+ -| 5-6 | 5-6 | 4-5 | 4-5 | | | 2-4 | -+-------+-------+------+------+------+------+------+ -| 8-9 | 8-9 | | | | | | -+-------+-------+------+------+------+------+------+ -| 11-12 | 11-12 | | | | | | -+-------+-------+------+------+------+------+------+ -| 14-15 | 14-15 | | | | | | -+-------+-------+------+------+------+------+------+ -| 17-18 | 17-18 | | | | | | -+-------+-------+------+------+------+------+------+ -| | 20-21 | | | | | | -+-------+-------+------+------+------+------+------+ -| | 23-24 | | | | | | -+-------+-------+------+------+------+------+------+ - -+------+------+-------+-------+------+------+-------+-----+--------+------+------+------+-------+ -| UART1 | -+---------------------------------------------------+-------------------------------------------+ -| (P12) | (P2) | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| JP11 | JP14 | JP19 | JP24 | JP90 | JP94 | JP157 | JP11 | JP19 | JP24 | JP90 | JP94 | JP157 | -+======+======+=======+=======+======+======+=======+======+=======+======+======+======+=======+ -| 1-2 | 1-2 | 20-21 | 2-3 | 2-3 | 1-3 | 1-2 | 1-2 | 11-12 | 5-6 | 2-3 | 1-3 | 1-3 | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| 4-5 | | | 5-6 | | 2-4 | 4-5 | 4-5 | | 8-9 | | 2-4 | 4-6 | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| 8-9 | | | 8-9 | | | 7-8 | | |17-18 | | | 7-9 | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| | | | 11-12 | | | 10-11 | | |23-24 | | | 10-12 | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| | | | 14-15 | | | | | | | | | | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| | | | 17-18 | | | | | | | | | | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ - -NOTE: The "Hello World" example outputs at ``UART1 P12`` . - -+----------------------+-------+--------+ -| SHD_SPI | SWD | LED4-5 | -+-------+------+-------+-------+--------+ -| JP23 | JP25 | JP156 | J18 | JP21 | -+=======+======+=======+=======+========+ -| 2-3 | 1-2 | 1-2 | 8-9 | 4-5 | -+-------+------+-------+-------+--------+ -| 8-9 | | | 11-12 | 16-17 | -+-------+------+-------+-------+--------+ -| 14-15 | | | | | -+-------+------+-------+-------+--------+ -| 17-18 | | | | | -+-------+------+-------+-------+--------+ - -Jumper settings for MEC172x 144WFBGA Socket DC Assy 6914 Rev A0p1 -================================================================= - -The jumper configuration explained above covers the base board. The ASSY -6914 MEC172x CPU board provides capability for an optional, external 32KHz -clock source. The card includes a 32KHz crystal oscillator. The card can -also be configured to use an external 50% duty cycle 32KHz source on the -XTAL2/32KHZ_IN pin. Note, firmware must set the MEC172x clock enable -register to select the external source matching the jumper settings. If -using the MEC172x internal silicon oscillator then the 32K jumper settings -are don't cares. ``JP1`` on DC is for scoping test clock outputs. Please -refer to the schematic in reference section below. - -Parallel 32KHz crystal configuration ------------------------------------- - -+-------+-------+ -| JP1 | JP2 | -+=======+=======+ -| 1-2 | 2-3 | -+-------+-------+ - -External 32KHz 50% duty cycle configuration -------------------------------------------- - -+-------+-------+ -| JP2 | JP3 | -+=======+=======+ -| NC | 1-2 | -+-------+-------+ - -NOTE: ``JP121 3-4`` on base board also needs to be loaded. - - -Programming and Debugging -************************* - -Setup -===== - -#. If you use Dediprog SF100 programmer, then setup it. - - Windows version can be found at the `SF100 Product page`_. - - Linux version source code can be found at `SF100 Linux GitHub`_. - Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer. - For Linux please make sure that you copied ``60-dediprog.rules`` - from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d) - then restart service using: - - .. code-block:: console - - $ udevadm control --reload - - Add directory with program ``dpcmd`` (on Linux) - or ``dpcmd.exe`` (on Windows) to your ``PATH``. - -#. Clone the `MEC172x SPI Image Gen`_ repository or download the files within - that directory. - -#. Make the image generation available for Zephyr, by making the tool - searchable by path, or by setting an environment variable - ``MEC172X_SPI_GEN``, for example: - - .. code-block:: console - - export MEC172X_SPI_GEN=/mec172x_spi_gen_lin_x86_64 - - Note that the tools for Linux and Windows have different file names. - -#. The default MEC172X_SPI_CFG file is spi_cfg.txt located in ${BOARD_DIR}/support. - If needed, a custom SPI image configuration file can be specified to override the - default one. - - .. code-block:: console - - export MEC172X_SPI_CFG=custom_spi_cfg.txt - -Wiring -======== - -#. Connect the SPI Dongle ASSY 6791 to ``J34`` in the EVB. - - .. image:: spidongle_assy6791.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - -#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip - ``U3``. Make sure that your programmer's offset is 0x0. - For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips. - - .. image:: dediprog_connector.jpg - :align: center - :alt: SF100 Connected - - - .. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers! - Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board. - Wiring connection is described in the table below. - - +------------+---------------+ - | Dediprog | Assy6791 | - | Connector | J6 Connector | - +============+===============+ - | VCC | 1 | - +------------+---------------+ - | GND | 2 | - +------------+---------------+ - | CS | 3 | - +------------+---------------+ - | CLK | 4 | - +------------+---------------+ - | MISO | 6 | - +------------+---------------+ - | MOSI | 5 | - +------------+---------------+ - -#. Connect UART1 port of the MEC17xxEVB_ASSY_6906 board - to your host computer using the RS232 cable. - -#. Apply power to the board via a micro-USB cable. - Configure this option by using a jumper between ``JP30 7-8``. - - .. image:: jp30_power_options.jpg - :align: center - :alt: Power Connection - -Building -======== - -#. Build :ref:`hello_world` application as you would normally do. - -#. The file :file:`spi_image.bin` will be created if the build system - can find the image generation tool. This binary image can be used - to flash the SPI chip. - -Flashing -======== - -#. Run your favorite terminal program to listen for output. - Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. - - For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Flash your board using ``west`` from the second terminal window. - Split first and second terminal windows to view both of them. - - .. code-block:: console - - $ west flash - - .. note:: When west process started press Reset button ``S2`` and do not release it - till the whole west process will not be finished successfully. - - .. image:: Reset_Button.jpg - :align: center - :alt: Reset Button - - .. note:: If you don't want to press Reset button every time, you can disconnect - SPI Dongle ASSY 6791 from the EVB during the west flash programming. - Then connect it back to the ``J34`` header and apply power to the EVB. - Result will be the same. - - -#. You should see ``"Hello World! mec172xevb_assy6906"`` in the first terminal window. - If you don't see this message, press the Reset button and the message should appear. - -Debugging -========= - -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG only sessions. - -Troubleshooting -=============== - -#. In case you don't see your application running, please make sure ``LED1`` and ``LED2`` - are lit. If one of these is off, then check the power-related jumpers again. - -#. If you can't program the board using Dediprog, disconnect the Assy6791 - from the main board Assy6906 and try again. - -#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again. - -PCA9555 Enabling -================ -#. To enable PCA9555PW and test the I2C on mec172xevb_assy6906, additional works are needed: - - As the I2C slave device NXP pca95xx on mec172xevb_assy6906 is connected to I2C00 port, - however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log, - so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use - I2C01 port by making some jumpers setting as below: - - +---------+---------+------------------------------------------+ - | Pin 1 | Pin 2 | Comment | - +=========+=========+==========================================+ - | JP49.1 | JP49.2 | Connect PCA9555 VCC to +3.3V_STBY | - +---------+---------+------------------------------------------+ - | JP53.1 | JP53.2 | Select address 0100b, which means 0x26 | - +---------+---------+------------------------------------------+ - | JP12.13 | JP12.14 | Connect I2C01_SDA from CPU to header J20 | - +---------+---------+------------------------------------------+ - | JP12.4 | JP12.5 | Connect I2C01_SCL from CPU to header J20 | - +---------+---------+------------------------------------------+ - | JP77.7 | JP77.8 | External pull-up for I2C01_SDA | - +---------+---------+------------------------------------------+ - | JP77.9 | JP77.10 | External pull-up for I2C01_SCL | - +---------+---------+------------------------------------------+ - | JP58.1 | JP20.1 | Connect NXP PCA9555 SCL to I2C01 | - +---------+---------+------------------------------------------+ - | JP58.3 | JP20.3 | Connect NXP PCA9555 SDA to I2C01 | - +---------+---------+------------------------------------------+ - -References -********** - -.. target-notes:: - -.. _MEC172x Reference Manual: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172x-Data-Sheet.pdf -.. _MEC172x EVB Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-EVB-Assy_6906-A1p0-SCH.pdf -.. _MEC172x Daughter Card Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-144WFBGA-Socket-DC-Assy6914-Rev-A-SCH.pdf -.. _SPI Dongle Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/SPI%20Dongles%20and%20Aardvark%20Interposer%20Assy%206791%20Rev%20A1p1%20-%20SCH.pdf -.. _MEC172x SPI Image Gen: - https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC172x/SPI_image_gen -.. _SF100 Linux GitHub: - https://github.com/DediProgSW/SF100Linux -.. _SF100 Product page: - https://www.dediprog.com/product/SF100 -.. _SF100 Linux manual: - https://www.dediprog.com/download/save/727.pdf diff --git a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig b/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig deleted file mode 100644 index 63e6a6be73b..00000000000 --- a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2021, Microchip Technology Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MEC172X_NSZ=y -CONFIG_SOC_SERIES_MEC172X=y -CONFIG_BOARD_MEC172XEVB_ASSY6906=y -CONFIG_RTOS_TIMER=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/mec172xmodular_assy6930/Kconfig.board b/boards/arm/mec172xmodular_assy6930/Kconfig.board deleted file mode 100644 index bfcfda0bcc3..00000000000 --- a/boards/arm/mec172xmodular_assy6930/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MEC172XMODULAR_ASSY6930 - bool "Microchip MEC172X MODULAR ASSY 6930 Development board" - depends on SOC_MEC172X_NSZ diff --git a/boards/arm/mec172xmodular_assy6930/Kconfig.defconfig b/boards/arm/mec172xmodular_assy6930/Kconfig.defconfig deleted file mode 100644 index 347f4efdd6b..00000000000 --- a/boards/arm/mec172xmodular_assy6930/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2022 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MEC172XMODULAR_ASSY6930 - -config BOARD - default "mec172xmodular_assy6930" - -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 Hz. -# The driver requires tickless mode and ticks per second to be 32768 for -# accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR -# processor clock divider register. We assume PCR processor clock divider -# is set to 1. Refer to SOC_MEC172X_PROC_CLK_DIV -# - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 96000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -endif # RTOS_TIMER - -endif # BOARD_MEC172XMODULAR_ASSY6930 diff --git a/boards/arm/mercury_xu/CMakeLists.txt b/boards/arm/mercury_xu/CMakeLists.txt deleted file mode 100644 index 191e22a607b..00000000000 --- a/boards/arm/mercury_xu/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2020, Antmicro -# SPDX-License-Identifier: Apache-2.0 -zephyr_library() -zephyr_library_sources(board.c) diff --git a/boards/arm/mercury_xu/Kconfig.board b/boards/arm/mercury_xu/Kconfig.board deleted file mode 100644 index 929cf6db518..00000000000 --- a/boards/arm/mercury_xu/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2020, Antmicro -# SPDX-License-Identifier: Apache-2.0 -config BOARD_MERCURY_XU - bool "Mercury XU Board" - depends on SOC_XILINX_ZYNQMP_RPU diff --git a/boards/arm/mercury_xu/Kconfig.defconfig b/boards/arm/mercury_xu/Kconfig.defconfig deleted file mode 100644 index 856e4d2ac01..00000000000 --- a/boards/arm/mercury_xu/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2020, Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MERCURY_XU - -config BOARD - default "mercury_xu" - -config FLASH_SIZE - int - default 64 - -config FLASH_BASE_ADDRESS - default 0x08000000 - -endif diff --git a/boards/arm/mercury_xu/mercury_xu_defconfig b/boards/arm/mercury_xu/mercury_xu_defconfig deleted file mode 100644 index d01d7082f94..00000000000 --- a/boards/arm/mercury_xu/mercury_xu_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2020, Antmicro -CONFIG_SOC_XILINX_ZYNQMP_RPU=y -CONFIG_BOARD_MERCURY_XU=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable timer -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 - -CONFIG_PINCTRL=y diff --git a/boards/arm/mg100/Kconfig.board b/boards/arm/mg100/Kconfig.board deleted file mode 100644 index 59779d555c5..00000000000 --- a/boards/arm/mg100/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MG100 - bool "MG100" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/mg100/Kconfig.defconfig b/boards/arm/mg100/Kconfig.defconfig deleted file mode 100644 index 46091ee3b47..00000000000 --- a/boards/arm/mg100/Kconfig.defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright (c) 2022 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MG100 - -config BOARD - default "mg100" - -config MODEM - default NETWORKING - -config MODEM_HL7800 - default NETWORKING - -config NORDIC_QSPI_NOR - default BOOTLOADER_MCUBOOT - -config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE - default 4096 if NORDIC_QSPI_NOR - -config REGULATOR - default DISK_DRIVER_SDMMC - -config BT_CTLR - default BT - -endif # BOARD_MG100 diff --git a/boards/arm/mg100/doc/index.rst b/boards/arm/mg100/doc/index.rst deleted file mode 100644 index 6e1ef2bfe53..00000000000 --- a/boards/arm/mg100/doc/index.rst +++ /dev/null @@ -1,249 +0,0 @@ -.. _mg100: - -Laird Connectivity Sentrius™ MG100 Gateway -########################################## - -Overview -******** -The Sentrius™ MG100 Gateway offers a compact, out of box Bluetooth to low power cellular gateway -solution. - -Based on the Pinnacle 100 socket modem, the Sentrius™ MG100 gateway captures data from any -Bluetooth 5 modules or devices and sends it to the cloud via a global low power cellular -(LTE-M/NB-IoT) connection. The MG100 seamlessly incorporates a powerful Cortex M4F controller, -full Bluetooth 5 connectivity, and dual-mode LTE-M/NB-IoT capabilities. The MG100 has full regulatory -and network certifications and End Device carrier approvals. - -Develop your application directly on the integrated Cortex M4F microcontroller using Zephyr RTOS, -enabling your application development with a secure, open source RTOS with more than just kernel -services. Remotely debug your fleet of devices with the `Memfault Platform`_. Take advantage of the -Zephyr community and Laird Connectivity’s multi featured Out of Box (OOB) sample source code -covering all aspects of the product's capabilities and hardware interfaces. The MG100 also delivers -complete antenna flexibility with internal or external antenna options available, and the optional -battery backup provides uninterrupted reporting of remote Bluetooth sensor data. - -More information about the board can be found at the `MG100 website`_. - -The MG100 hardware provides support for the Nordic Semiconductor `nRF52840`_ ARM Cortex-M4F CPU, -`Sierra Wireless HL7800`_ -and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* :abbr:`LIS3DH (ST Micro 3-axis MEMS accelerometer)` -* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` -* :abbr:`SD Card` - -.. figure:: img/mg100.jpg - :align: center - :alt: MG100 - - MG100 (450-00054-K1) - -Hardware -******** - -Supported Features -================== - -The MG100 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ -| QSPI | on-chip | qspi/MX25R64(8MB) | -+-----------+------------+----------------------+ -| LIS3DH | I2C(M) | sensor/lis3dh | -+-----------+------------+----------------------+ -| HL7800 | UART | HL7800 modem driver | -+-----------+------------+----------------------+ -| SDMMC | SPI(M) | SD Card via SPI | -+-----------+------------+----------------------+ - -See `MG100 website`_ for a complete list -of MG100 hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P1.7 -* LED2 (blue) = P1.6 -* LED3 (green) = P1.5 - -Push buttons ------------- - -* BUTTON1 = P0.3 - -External flash memory ---------------------- - -A 64Mbit external flash memory part is available for storage of application -images and data. Refer to the `Macronix MX25R6435F datasheet`_ for further -details. - -The flash memory is connected to the on-board QSPI device controller. - -* MX25R64 = QSPI - -SCK = P0.19 -IO0 = P0.20 -IO1 = P0.21 -IO2 = P0.22 -IO3 = P0.23 -CSN = P0.17 - -LIS3DH Motion Sensor --------------------- - -Motion sensor to detect if the gateway moves. - -IRQ IO = P0.28 -I2C SDA = P0.26 -I2C SCL = P0.27 - -SD Card -------- - -SD card used to store large amounts of data. - -SPI CS = P0.29 -SPI SCK = P1.09 -SPI MOSI = P0.11 -SPI MISO = P0.12 - -Programming and Debugging -************************* - -Applications for the ``mg100`` board configuration can be -built and flashed in the usual way. (see :ref:`build_an_application` -and :ref:`application_run` for more details) - -The `Laird Connectivity USB-SWD Programming Kit`_ contains all the necessary -hardware to enable programming and debugging an MG100. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. note:: On the MG100, - the USB connector should be used to access the UART console. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board MG100 -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mg100 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -Software -******** - -MG100 Out-of-Box Demo Software -============================== -The MG100 ships with an out of the box software demo. -Check out the `BLE Gateway OOB Demo`_ source code and documentation. - -Testing Bluetooth on the MG100 -============================== -Many of the Bluetooth examples will work on the MG100. -Try them out: - -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` - -Testing the LEDs and buttons in the MG100 -==================================================== - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/mg100/mg100.dts`. - -References -********** - -.. target-notes:: - -.. _MG100 website: https://www.lairdconnect.com/iot-devices/iot-gateways/sentrius-mg100-gateway-lte-mnb-iot-and-bluetooth-5 -.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf -.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _BLE Gateway OOB Demo: https://github.com/LairdCP/Pinnacle-100-Firmware-Manifest -.. _Macronix MX25R6435F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7913/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.5.pdf -.. _Laird Connectivity USB-SWD Programming Kit: https://www.lairdconnect.com/wireless-modules/programming-kits/usb-swd-programming-kit -.. _Memfault Platform: https://docs.memfault.com/docs/mcu/pinnacle-100-guide -.. _nRF52840: https://www.nordicsemi.com/products/nrf52840 diff --git a/boards/arm/mikroe_clicker_2/Kconfig.board b/boards/arm/mikroe_clicker_2/Kconfig.board deleted file mode 100644 index 81e95e3fd3b..00000000000 --- a/boards/arm/mikroe_clicker_2/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# MikroE Clicker 2 board configuration - -# Copyright (c) 2020 Trifork -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIKROE_CLICKER_2 - bool "MikroE Clicker 2 for STM32 board" - depends on SOC_STM32F407XG diff --git a/boards/arm/mikroe_clicker_2/Kconfig.defconfig b/boards/arm/mikroe_clicker_2/Kconfig.defconfig deleted file mode 100644 index 08a87aeca76..00000000000 --- a/boards/arm/mikroe_clicker_2/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# MikroE Clicker 2 board configuration - -# Copyright (c) 2020 Trifork -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIKROE_CLICKER_2 - -config BOARD - default "mikroe_clicker_2" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif #BOARD_MIKROE_CLICKER_2 diff --git a/boards/arm/mikroe_clicker_2/mikroe_clicker_2_defconfig b/boards/arm/mikroe_clicker_2/mikroe_clicker_2_defconfig deleted file mode 100644 index 15ade5bcf58..00000000000 --- a/boards/arm/mikroe_clicker_2/mikroe_clicker_2_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_BOARD_MIKROE_CLICKER_2=y -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XG=y - -# Enable MPU -CONFIG_ARM_MPU=y - -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.board b/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.board deleted file mode 100644 index 5680d9a0846..00000000000 --- a/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Mikroe MINI-M4 for STM32 board configuration - -# Copyright (c) 2019, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIKROE_MINI_M4_FOR_STM32 - bool "Mikroe MINI-M4 for STM32 Board" - depends on SOC_STM32F415XX diff --git a/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.defconfig b/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.defconfig deleted file mode 100644 index 3a2bbe8f5d4..00000000000 --- a/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Mikroe MINI-M4 for STM32 board configuration - -# Copyright (c) 2019, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIKROE_MINI_M4_FOR_STM32 - -config BOARD - default "mikroe_mini_m4_for_stm32" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_MIKROE_MINI_M4_FOR_STM32 diff --git a/boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig b/boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig deleted file mode 100644 index 3f0ccc9cca7..00000000000 --- a/boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_BOARD_MIKROE_MINI_M4_FOR_STM32=y -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F415XX=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/mimx8mm_evk/Kconfig.board b/boards/arm/mimx8mm_evk/Kconfig.board deleted file mode 100644 index 0e7c9865cf1..00000000000 --- a/boards/arm/mimx8mm_evk/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# MIMX8MM EVK board - -# Copyright (c) 2020, Manivannan Sadhasivam -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MM_EVK - bool "NXP i.MX8M Mini EVK" - depends on SOC_SERIES_IMX8MM_M4 - select SOC_PART_NUMBER_MIMX8MM6DVTLZ diff --git a/boards/arm/mimx8mm_evk/Kconfig.defconfig b/boards/arm/mimx8mm_evk/Kconfig.defconfig deleted file mode 100644 index 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-NXP MIMX8MM EVK -############### - -Overview -******** - -i.MX8M Mini LPDDR4 EVK board is based on NXP i.MX8M Mini applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. -Zephyr OS is ported to run on the Cortex®-M4 core. - -- Board features: - - - RAM: 2GB LPDDR4 - - Storage: - - - SanDisk 16GB eMMC5.1 - - Micron 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11b/g/n - - Bluetooth: v4.1 - - USB: - - - OTG - 2x type C - - Ethernet - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M4 - -.. image:: img/mimx8mm_evk.jpg - :align: center - :alt: MIMX8MM EVK - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mm_evk board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/mimx8mm_evk/mimx8mm_evk_defconfig`. - -It is recommended to disable peripherals used by the M4 core on the Linux host. - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -MIMX8MM EVK board was tested with the following pinmux controller -configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART4 RXD | UART4_TXD | UART Console | -+---------------+-----------------+---------------------------+ -| UART4 TXD | UART4_RXD | UART Console | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 400 MHz clock speed. - -Serial Port -=========== - -The i.MX8M Mini SoC has four UARTs. UART_4 is configured for the console and -the remaining are not used/tested. - -Programming and Debugging -************************* - -The MIMX8MM EVK board doesn't have QSPI flash for the M4 and it needs -to be started by the A53 core. The A53 core is responsible to load the M4 binary -application into the RAM, put the M4 in reset, set the M4 Program Counter and -Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at -bootloader level or after the Linux system has booted. - -The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/mimx8mm_evk/mimx8mm_evk.dts`` -with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. -The available configurations are: - -.. code-block:: none - - "zephyr,flash" - - &tcml_code - - &ocram_code - - &ocram_s_code - - "zephyr,sram" - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - -Load and run Zephyr on M4 from A53 using u-boot by copying the compiled -``zephyr.bin`` to the first FAT partition of the SD card and plug the SD -card into the board. Power it up and stop the u-boot execution at prompt. - -Load the M4 binary onto the desired memory and start its execution using: - -.. code-block:: console - - fatload mmc 0:1 0x7e0000 zephyr.bin;bootaux 0x7e0000 - -Debugging -========= - -MIMX8MM EVK board can be debugged by connecting an external JLink -JTAG debugger to the J902 debug connector and to the PC. Then -the application can be debugged using the usual way. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimx8mm_evk - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS build zephyr-v2.0.0-1859-g292afe8533c0 ***** - Hello World! mimx8mm_evk - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/evaluation-kit-for-thebr-i.mx-8m-mini-applications-processor:8MMINILPD4-EVK - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MMRM diff --git a/boards/arm/mimx8mm_evk/mimx8mm_evk-pinctrl.dtsi b/boards/arm/mimx8mm_evk/mimx8mm_evk-pinctrl.dtsi deleted file mode 100644 index c7b1943810e..00000000000 --- a/boards/arm/mimx8mm_evk/mimx8mm_evk-pinctrl.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2022, NXP - * SPDX-License-Identifier: Apache-2.0 - * - * Note: File generated by gen_board_pinctrl.py - * from MIMX8MM-EVK-REV-C.mex - */ - -#include - -&pinctrl { - uart4_default: uart4_default { - group0 { - pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, - <&iomuxc_uart4_txd_uart_tx_uart4_tx>; - slew-rate = "fast"; - drive-strength = "40-ohm"; - }; - }; - -}; diff --git a/boards/arm/mimx8mm_evk/mimx8mm_evk.dts b/boards/arm/mimx8mm_evk/mimx8mm_evk.dts deleted file mode 100644 index e0711636f55..00000000000 --- a/boards/arm/mimx8mm_evk/mimx8mm_evk.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2020, Manivannan Sadhasivam - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -#include "mimx8mm_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8M Mini EVK board"; - compatible = "nxp,mimx8mm_evk"; - - aliases { - uart-4 = &uart4; - }; - - chosen { - zephyr,flash = &tcml_code; - zephyr,sram = &tcmu_sys; - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/arm/mimx8mm_evk/mimx8mm_evk.yaml b/boards/arm/mimx8mm_evk/mimx8mm_evk.yaml deleted file mode 100644 index 4c1779778ba..00000000000 --- a/boards/arm/mimx8mm_evk/mimx8mm_evk.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2020, Manivannan Sadhasivam -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mm_evk -name: NXP i.MX8M Mini EVK -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -vendor: nxp diff --git a/boards/arm/mimx8mm_evk/mimx8mm_evk_defconfig b/boards/arm/mimx8mm_evk/mimx8mm_evk_defconfig deleted file mode 100644 index f51c8ac2b10..00000000000 --- a/boards/arm/mimx8mm_evk/mimx8mm_evk_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2020, Manivannan Sadhasivam -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8MM_M4=y -CONFIG_SOC_MIMX8MM6=y -CONFIG_BOARD_MIMX8MM_EVK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimx8mm_phyboard_polis/Kconfig.board b/boards/arm/mimx8mm_phyboard_polis/Kconfig.board deleted file mode 100644 index c7079f5d912..00000000000 --- a/boards/arm/mimx8mm_phyboard_polis/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# MIMX8MM_PHYBOARD_POLIS board configuration - -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MM_PHYBOARD_POLIS - bool "Phytec Phyboard Polis i.MX8M Mini" - depends on SOC_SERIES_IMX8MM_M4 - select SOC_PART_NUMBER_MIMX8MM6DVTLZ diff --git a/boards/arm/mimx8mm_phyboard_polis/Kconfig.defconfig b/boards/arm/mimx8mm_phyboard_polis/Kconfig.defconfig deleted file mode 100644 index 1e0191ff7ba..00000000000 --- a/boards/arm/mimx8mm_phyboard_polis/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# MIMX8MM_PHYBOARD_POLIS board defconfig -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MM_PHYBOARD_POLIS - -config BOARD - default "mimx8mm_phyboard_polis" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_MIMX8MM_PHYBOARD_POLIS diff --git a/boards/arm/mimx8mm_phyboard_polis/board.cmake b/boards/arm/mimx8mm_phyboard_polis/board.cmake deleted file mode 100644 index 3b202648575..00000000000 --- a/boards/arm/mimx8mm_phyboard_polis/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2020, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_set_debugger_ifnset(jlink) -board_set_flasher_ifnset(jlink) - -board_runner_args(jlink "--device=MIMX8MD6_M4") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/mimx8mm_phyboard_polis/doc/index.rst b/boards/arm/mimx8mm_phyboard_polis/doc/index.rst deleted file mode 100644 index 3d44ddcc87a..00000000000 --- a/boards/arm/mimx8mm_phyboard_polis/doc/index.rst +++ /dev/null @@ -1,342 +0,0 @@ -.. _mimx8mm_phyboard_polis: - -PhyBOARD Polis (NXP i.MX8M Mini) -################################ - -Overview -******** - -The phyBOARD-Polis, either a development platform for the -phyCORE-i.MX 8M Mini/Nano, or a powerful, industry-compatible single-board -computer for immediate implementation of your product idea. As a development -platform, the phyBOARD-Polis serves as reference design for your -customer-specific application and enables parallel development of the software -and carrier board for the phyCORE-i.MX 8M Mini/Nano. - - -As a powerful, industrial single-board computer (SBC), the phyBOARD-Polis is -equipped with a variety of standard interfaces which are available on standard -or socket/pin header connectors, while interesting extensions of the -phyCORE-i.MX 8M Mini/Nano features such as CAN FD, WLAN and an integrated -TPM chip further extend the range of applications that can be developed with -the phyCORE-i.MX 8M Mini/Nano. - -- Board features: - - - RAM: 512MB - 4GB (LPDDR4) - - Storage: - - - 4GB - 128GB eMMC - - 8MB - 128MB SPI NOR Flash - - microSD Interfacce - - 4kB EEPROM - - Wireless: - - - WiFi: 802.11 b/g/n (ac) 2,4 GHz / 5 GHz - - BLE 4.2 - - USB: - - - 1x USB2.0 OTG - - 1x USB2.0 - - Ethernet: 1x 10/100/1000BASE-T - - Interfaces: - - 1x RS232 / RS485 - - 2x UART - - 3x I²C - - 2x SPI - - Up to 4x PWM - - 4x SAI - - 1x MIPI CSI-2 - - 1x MIPI DSI-2 - - 2x MMC/SD/SDIO - - 1x PCIe (mini PCIE) - - LEDs: - - - 1x Status LED (3 Color LED) - - 1x Debug UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M4 - -.. image:: img/phyBOARD-Polis.jpg - :align: center - :alt: PhyBOARD Polis - :width: 500 - -More information about the board can be found at the -`PHYTEC website`_. - -Supported Features -================== - -The Zephyr mimx8mm_phyboard_polis board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_defconfig`. - -It is recommended to disable peripherals used by the M4 core on the Linux host. - -Other hardware features are not currently supported with Zephyr on the -M4-Core. - -Connections and IOs -=================== - -The following components are tested and working correctly. - -UART: ------ - -Zephyr is configured to use UART4 on the PhyBoard Polis by default to minimize -problems with the A53-Core because UART4 is only accessible from the M4-Core. - -+---------------+-----------------+-----------------------------------+ -| Board Name | SoM Name | Usage | -+===============+=================+===================================+ -| RS232/485 | UART1 | RS232 / RS485 with flow-control | -+---------------+-----------------+-----------------------------------+ -| To WiFi Module| UART2 | UART to WiFi/BLE Module | -+---------------+-----------------+-----------------------------------+ -| Debug USB(A53)| UART3 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ -| Debug USB(M4) | UART4 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ - -.. note:: - Please note, that the to UART2 connected Wifi/BLE Module isn't working with - Zephyr yet. - -.. warning:: - On Boards with the version number 1532.1 UART4 isn't connected to the Debug - USB. UART4 connects to pin 10(RX) and 12(TX) on the X8 pinheader. - - -LEDs: ------ - -Zephyr has the 3-color status LED configured. The led0 alias (the standard -Zephyr led) is configured to be the blue led. The LED can also light up in red -and green. - -GPIO: ------ - -The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mm devicetree -created by NXP. You can find it here: - -:zephyr_file:`dts/arm/nxp/nxp_imx8m_m4.dtsi`. - -The Pinout of the PhyBOARD Polis can be found here: - -`PHYTEC website`_ - -System Clock -============ - -The M4 Core is configured to run at a 400 MHz clock speed. - - -Programming and Debugging -************************* - -The i.MX8MM does not have a separate flash for the M4-Core. Because of this -the A53-Core has to load the program for the M4-Core to the right memory -address, set the PC and start the processor. -This can be done with U-Boot or Phytec's Linux BSP via remoteproc. - -Because remoteproc in Phytec's BSP only writes to the TCM memory area, -everything was tested in this memory area. - -You can read more about remoteproc in Phytec's BSP here: `Remoteproc BSP`_ - -These are the memory mapping for A53 and M4: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/mimx8mm_evk/mimx8mm_evk.dts`` -with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. -The available configurations are: - -If you don't want to use the TCM memory area, you can either overwrite the -boards devicetree in your program or edit the board devicetree located here: - -:zephyr_file:`boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.dts` - -You also have to set XIP=n or edit the boards defconfig file, if you don't want -the TCM memory area to be used. You can find the defconf file here: - -:zephyr_file:`boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_defconfig`. - -The following configurations are possible for the flash and sram chosen nodes -to change the used memory area: - -.. code-block:: none - - "zephyr,flash" - - &tcml_code - - &ocram_code - - &ocram_s_code - - "zephyr,sram" - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - - -Starting the M4-Core via U-Boot -=============================== - -Load the compiled zephyr.bin to memory address 0x4800000. -This should output something like this: - -.. code-block:: console - - u-boot=> tftp 0x48000000 192.168.3.10:zyphr.bin - Using ethernet@30be0000 device - TFTP from server 192.168.3.10; our IP address is 192.168.3.11 - Filename 'zepyhr.bin'. - Load address: 0x48000000 - Loading: ## - 2 KiB/s - done - Bytes transferred = 27240 (6a68 hex) - -Because it's not possible to load directly to the TCM memory area you have to -copy the binaries. The last argument given is the size of the file in bytes, -you can copy it from the output of the last command. - -.. code-block:: console - - u-boot=> cp.b 0x48000000 0x7e0000 27240 - -And finaly starting the M4-Core at the right memory address: - -.. code-block:: console - - u-boot=> bootaux 0x7e0000 - ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905... - - -Starting the M4-Core via remoteproc -=================================== - -Copy the zepyhr.elf to ``/lib/firmware`` on the target. Maybe a Zephyr sample -will be included in a future BSP release. - -.. note:: - In order to use remoteproc you have to add ``imx8mm-phycore-rpmsg.dtbo`` at - the end of the line in the ``/boot/bootenv.txt``, then reboot the target. - -.. warning:: - Remoteproc only reads firmware files from the ``/lib/firmware`` directory! - If you try to load a binary from another location unexpected errors will - occur! - -To load and start a firmware use this commands: - -.. code-block:: console - - target$ echo /lib/firmware/zepyhr.elf > /sys/class/remoteproc/remoteproc0/firmware - target$ echo start > /sys/class/remoteproc/remoteproc0/state - [ 90.700611] remoteproc remoteproc0: powering up imx-rproc - [ 90.706114] remoteproc remoteproc0: Direct firmware load for /lib/firmware/zepyhr.elf failed w2 - [ 90.716571] remoteproc remoteproc0: Falling back to sysfs fallback for: /lib/firmware/zepyhr.elf - [ 90.739280] remoteproc remoteproc0: Booting fw image /lib/firmware/zepyhr.elf, size 599356 - [ 90.804448] remoteproc remoteproc0: remote processor imx-rproc is now up - - -The M4-Core is now started up and running. You can see the output from Zephyr -on UART4. - -Debugging -========= - -The PhyBOARD Polis can be debugged using a JTAG Debugger. -The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's -``PEB-EVAL-01`` Shield, which can be directly connected to the JLink. -You can find the JLink Software package here: `JLink Software`_ - -.. figure:: img/PEB-EVAL-01.jpg - :alt: PEB-EVAL-01 - :width: 350 - - PEB-EVAL-01 - -To debug efficiently you should use multiple terminals: - -(But its also possible to use ``west debug``) - -After connecting everything and building with west use this command while in -the directory of the program you build earlier to start a debug server: - -.. code-block:: console - - host$ west debugserver - -West automatically connects via the JLink to the Target. And keeps open a -debug server. - -Use another terminal, start gdb, connect to target and load Zephyr on the -target: - -.. code-block:: console - - host$ gdb-multiarch build/zephyr/zephyr.elf -tui - (gdb) targ rem :2331 - Remote debugging using :2331 - 0x1ffe0008 in _vector_table () - (gdb) mon halt - (gdb) mon reset - (gdb) c - Continuing. - -The program can be debugged using standard gdb techniques. - -.. _PHYTEC website: - https://www.phytec.de/produkte/single-board-computer/phyboard-polis-imx8m-mini/ - -.. _PhyBOARD Polis pinout: - https://download.phytec.de/Products/phyBOARD-Polis-iMX8M_Mini/TechData/phyCORE-i.MX8M_MINI_Pin_Muxing_Table.A1.xlsx?_ga=2.237582016.1177557183.1660563641-1900651135.1634193918 - -.. _Remoteproc BSP: - https://wiki.phytec.com/pages/releaseview.action?pageId=472257137#L1002e.A3i.MX8MMini/NanoBSPManual-RunningExamplesfromLinuxusingRemoteproc - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MMRM - -.. _JLink Software: - https://www.segger.com/downloads/jlink/ diff --git a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.yaml b/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.yaml deleted file mode 100644 index 399336291f9..00000000000 --- a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2020 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mm_phyboard_polis -name: Phyboard Polis i.MX8M Mini -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -vendor: nxp diff --git a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_defconfig b/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_defconfig deleted file mode 100644 index 5b307dafaec..00000000000 --- a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8MM_M4=y -CONFIG_SOC_MIMX8MM6=y -CONFIG_BOARD_MIMX8MM_PHYBOARD_POLIS=y -CONFIG_CORTEX_M_SYSTICK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_PINCTRL=y -CONFIG_GPIO=y diff --git a/boards/arm/mimx8mp_evk/Kconfig.board b/boards/arm/mimx8mp_evk/Kconfig.board deleted file mode 100644 index 1595301fa29..00000000000 --- a/boards/arm/mimx8mp_evk/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# MIMX8MP EVK board - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MP_EVK - bool "NXP i.MX8M Plus EVK" - depends on SOC_SERIES_IMX8ML_M7 - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm/mimx8mp_evk/Kconfig.defconfig b/boards/arm/mimx8mp_evk/Kconfig.defconfig deleted file mode 100644 index 41d7a120fd1..00000000000 --- a/boards/arm/mimx8mp_evk/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# MIMX8MP EVK board defconfig - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MP_EVK - -config BOARD - default "mimx8mp_evk" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_MIMX8MP_EVK diff --git a/boards/arm/mimx8mp_evk/board.cmake b/boards/arm/mimx8mp_evk/board.cmake deleted file mode 100644 index d773ef92919..00000000000 --- a/boards/arm/mimx8mp_evk/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_set_debugger_ifnset(jlink) -board_set_flasher_ifnset(jlink) - -board_runner_args(jlink "--device=MIMX8ML8_M7") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) \ No newline at end of file diff --git a/boards/arm/mimx8mp_evk/doc/img/I.MX8MPLUS-PLUS-EVK-TOP.jpg b/boards/arm/mimx8mp_evk/doc/img/I.MX8MPLUS-PLUS-EVK-TOP.jpg deleted file mode 100644 index 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zuso9&57O_Gn~~efUk{6yzlzetwTY%u0T45=mAmkG=Ax+Er0c?oYbC@K?+B6Zp1v%} zFgD0ap6@y7q2-T$E;VSWbiHbFv`cWa3$+jkPnA@35|F+vA&2!M26R9>P(!FS5@N_* zM$5Vmy*5pU1R3__3cu#DN#u-cGG%-?ugsR|il_1@Efy{}72s-fQyGR!Ki-V4l z{0Fy@@;cg?<)Ct4#H7=Ha;RFRq3DaS+S_cp z-N}tHxlPFnn)1JehIl`|qo-lrHW2R-9MEE+JY}`{Dc6Z0 zo=rs>OEq6cN!=+Ud&Lf6Z`CSidVc6t_dxrE^*C&am?ftkE%A&un%DG1bFP&49w|W5 z=w5~YO%A+Z;(ty)^rjcqHit>N)X7|B8ZcC&nl_%zlS3Kl70c)=p0 z{REA(H|+6#rAwc#{fXT-hz-aR6lpIKpP^8DH9}D-nj?wQvqkCnaoEFR$?+vv@>WH& zLvwtf+(s>O*D)c0(a0SWFzJ}r2`rXA221YkJTE&s&%pwTrY0uL!iMb+{l|1)|F>pz z9Q2U`CXH^y9#tjr<&}v!m`0_pb5>w2pi|6V_I5hQh1;)IHvufhR|uBoTzs-YVnLh- zq`^^*9MAt&{#XtV!vg - -&pinctrl { - uart4_default: uart4_default { - group0 { - pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, - <&iomuxc_uart4_txd_uart_tx_uart4_tx>; - bias-pull-up; - slew-rate = "slow"; - drive-strength = "x1"; - }; - }; - -}; diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.dts b/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.dts deleted file mode 100644 index 0179f811eb9..00000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.dts +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2021, Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mp_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8M Plus EVK board"; - compatible = "nxp,mimx8mp_evk"; - - chosen { - /* DDR */ - zephyr,flash = &ddr_code; - zephyr,sram = &ddr_sys; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.yaml b/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.yaml deleted file mode 100644 index 7e4b407380b..00000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mp_evk_ddr -name: NXP i.MX8M Plus EVK (DDR) -type: mcu -arch: arm -ram: 2048 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -supported: - - uart -vendor: nxp diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr_defconfig b/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr_defconfig deleted file mode 100644 index 4a77ad558c2..00000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_MIMX8MP_EVK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_DDR=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.dts b/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.dts deleted file mode 100644 index 2d3f171339e..00000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.dts +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2021, Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mp_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8M Plus EVK board"; - compatible = "nxp,mimx8mp_evk"; - - chosen { - /* TCM */ - zephyr,flash = &itcm; - zephyr,sram = &dtcm; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.yaml b/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.yaml deleted file mode 100644 index 66c3c9b553d..00000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mp_evk_itcm -name: NXP i.MX8M Plus EVK (ITCM) -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -supported: - - uart -vendor: nxp diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm_defconfig b/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm_defconfig deleted file mode 100644 index 8b2a3b77054..00000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_MIMX8MP_EVK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_ITCM=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimx8mp_phyboard_pollux/Kconfig.board b/boards/arm/mimx8mp_phyboard_pollux/Kconfig.board deleted file mode 100644 index af7975bc3c9..00000000000 --- a/boards/arm/mimx8mp_phyboard_pollux/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# MIMX8MP PhyBOARD Pollux (i.MX8MP) - -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MP_PHYBOARD_POLLUX - bool "PhyBOARD Pollux (i.MX8MP)" - depends on SOC_SERIES_IMX8ML_M7 - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm/mimx8mp_phyboard_pollux/Kconfig.defconfig b/boards/arm/mimx8mp_phyboard_pollux/Kconfig.defconfig deleted file mode 100644 index 889b2b24dfa..00000000000 --- a/boards/arm/mimx8mp_phyboard_pollux/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# PhyBOARD Pollux (i.MX8MP) defconfig - -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MP_PHYBOARD_POLLUX - -config BOARD - default "mimx8mp_phyboard_pollux" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_MIMX8MP_PHYBOARD_POLLUX diff --git a/boards/arm/mimx8mp_phyboard_pollux/doc/index.rst b/boards/arm/mimx8mp_phyboard_pollux/doc/index.rst deleted file mode 100644 index 04da62c18ed..00000000000 --- a/boards/arm/mimx8mp_phyboard_pollux/doc/index.rst +++ /dev/null @@ -1,272 +0,0 @@ -.. _mimx8mp_phyboard_pollux: - -PhyBOARD Pollux (NXP i.MX8M Plus) -################################# - -Overview -******** - -The PhyBOARD Pollux is based upon the PhyCore-i.MX8M Plus SOM which is based on -the NXP i.MX8M Plus SoC. The SoC includes four Coretex-A53 cores and one -Coretex-M7 core for real time applications like Zephyr. The PhyBOARD Pollux -can be used for various applications like SmartHomes, Industry 4.0, IoT etc. -It features a lots of interfaces and computing capacity. It can be used as -a reference, to develop or in the final product too. - - -Board features: - -- Memory: - - - RAM: 256MB - 8GB LPDDR4 - - EEPROM: 4kB - 32kB - - eMMC: 4GB - 64GB (eMMC 5.1) - - SPI NOR Flash: 4MB - 256MB -- Interfaces: - - - Ethernet: 2x 10/100/1000BASE-T (1x TSN Support) - - USB: 2x 3.0 Host - - Serial: 1x RS232 / RS485 Full Duplex / Half Duplex - - CAN: 2x CAN FD - - Digital I/O: via Expansion Connector - - PCIe: 1x miniPCIe - - MMX/SD/SDIO: microSD slot - - Display: LVDS(1x4 or 1x8), MIPI DSI(1x4), HDMI - - Audio: SAI - - Camera: 2x MIPI CSI-2 (PhyCAM-M) - - Expansion Bus: I2C, SPI, SDIO, UART, USB - - JTAG: via PEB-EVAL-01 -- LEDs: - - - 1x Multicolor Status LED via I2C - - -.. image:: img/Phyboard_Pollux.jpg - :width: 720px - :align: center - :height: 405px - :alt: PhyBOARD Pollux - -More information about the board can be found at the -`PHYTEC website`_. - -Supported Features -================== - -The Zephyr mimx8mp_phyboard_polis board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_defconfig`. - -It's recommended to disable peripherals used by the M7-Core on the host running -on the Linux host. - -Other hardware features are not currently supported with Zephyr on the -M7-Core. - -Connections and IOs -=================== - -The following Compontens are tested and working correctly. - -UART ----- - -+---------------+-----------------+-----------------------------------+ -| Board Name | SoM Name | Usage | -+===============+=================+===================================+ -| Debug USB(A53)| UART1 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ -| Wo WiFi Module| UART3 | UART to WiFi/BLE Module | -+---------------+-----------------+-----------------------------------+ -| Debug USB(M4) | UART4 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ - -.. note:: - Please note, that the, to UART3 connected, Wifi/BLE Module isn't working with - Zephyr yet. UART3 can also be used through pin 31(RX) and 33(TX) of the - X6 Connector. - -GPIO ----- - -The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mp devicetree -created by NXP. You can find it here: - -:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. - -The Pinout of the PhyBOARD Polis can be found here: - -`PHYTEC website`_ - -Programming and Debugging -************************* - -The i.MX8MP does not have a separate flash for the M7-Core. Because of this -the A53-Core has to load the program for the M7-Core to the right memory -address, set the PC and start the processor. -This can only by done with u-boot at the moment. We are working on our BSP to -enable remoteproc support. - -The M7 can use up to 3 different RAMs (currently, only two configurations are -supported: ITCM and DDR). These are the memory mapping for A53 and M7: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3) - -At compilation time you have to choose which memory region will be used. This -configuration is done in the devicetree and the defconfig / the config of your -program. - -**By default Zephyr will use the TCM memory region.** You can configure it like -this for the DDR region: - -In the devicetree overwrite the following nodes like this: - -.. code-block:: DTS - - chosen { - /* TCM */ - zephyr,flash = &itcm; - zephyr,sram = &dtcm; - }; - -change it to - -.. code-block:: DTS - - chosen { - /* DDR */ - zephyr,flash = &ddr_code; - zephyr,sram = &ddr_sys; - }; - - -In your prj.conf overwrite the configuration like this for the **DDR** memory -region: - -.. code-block:: console - - CONFIG_CODE_DDR=y - CONFIG_CODE_ITCM=n - - -Starting the M7-Core via U-Boot -=============================== - -Load the compiled zephyr.bin to memory address 0x4800000. -This should output something like this: - -.. code-block:: console - - u-boot=> tftp 0x48000000 192.168.3.10:zyphr.bin - Using ethernet@30be0000 device - TFTP from server 192.168.3.10; our IP address is 192.168.3.11 - Filename 'zepyhr.bin'. - Load address: 0x48000000 - Loading: ## - 2 KiB/s - done - Bytes transferred = 27240 (6a68 hex) - -Because it's not possible to load directly to the TCM memory area you have to -copy the binaries. The last argument given is the size of the file in bytes, -you can copy it from the output of the last command. - -.. code-block:: console - - u-boot=> cp.b 0x48000000 0x7e0000 27240 - -And finaly starting the M7-Core at the right memory address: - -.. code-block:: console - - u-boot=> bootaux 0x7e0000 - ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905... - -Debugging -========= - -The PhyBOARD Polis can be debugged using a JTAG Debugger. -The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's -``PEB-EVAL-01`` Shield, which can be directly connected to the JLink. -You can find the JLink Software package here: `JLink Software`_ - -.. figure:: img/PEB-EVAL-01.jpg - :alt: PEB-EVAL-01 - :width: 350 - - PEB-EVAL-01 - -To debug efficiently you have to use multiple terminals: - -After connecting everything and building with west use this command while in -the directory of the program you build earlier to start a debug server: - -.. code-block:: console - - host$ west debugserver - -West automatically connects via the JLink to the Target and keeps open a -debug server. - -Use another terminal, start gdb, connect to target and load Zephyr on the -target: - -.. code-block:: console - - host$ gdb-multiarch build/zephyr/zephyr.elf -tui - (gdb) targ rem :2331 - Remote debugging using :2331 - 0x1ffe0008 in _vector_table () - (gdb) mon halt - (gdb) mon reset - (gdb) c - Continuing. - -The program can be debugged using standard gdb techniques. - -References -========== - -.. _PHYTEC website: - https://www.phytec.de/produkte/single-board-computer/phyboard-pollux/ - -.. _i.MX 8M Plus Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MPRM - -.. _JLink Software: - https://www.segger.com/downloads/jlink/ diff --git a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux.yaml b/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux.yaml deleted file mode 100644 index c696532393d..00000000000 --- a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux.yaml +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mp_phyboard_pollux -name: PhyBOARD Pollux (i.MX8MP) -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -supported: - - uart - - gpio -vendor: nxp diff --git a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_defconfig b/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_defconfig deleted file mode 100644 index 9c2fae84c13..00000000000 --- a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_MIMX8MP_PHYBOARD_POLLUX=y -CONFIG_CORTEX_M_SYSTICK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y - -# y for TCM memory space -CONFIG_CODE_ITCM=y - -# y for DDR memory space -CONFIG_CODE_DDR=n - -CONFIG_PINCTRL=y diff --git a/boards/arm/mimx8mq_evk/Kconfig.board b/boards/arm/mimx8mq_evk/Kconfig.board deleted file mode 100644 index 7f0533f7053..00000000000 --- a/boards/arm/mimx8mq_evk/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# MIMX8MQ EVK board - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MQ_EVK_CM4 - bool "NXP i.MX8MQ EVK" - depends on SOC_SERIES_IMX8MQ_M4 - select SOC_PART_NUMBER_MIMX8MQ6DVAJZ diff --git a/boards/arm/mimx8mq_evk/Kconfig.defconfig b/boards/arm/mimx8mq_evk/Kconfig.defconfig deleted file mode 100644 index fa66b520e6e..00000000000 --- a/boards/arm/mimx8mq_evk/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# MIMX8MQ EVK board defconfig - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MQ_EVK_CM4 - -config BOARD - default "mimx8mq_evk_cm4" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_MIMX8MQ_EVK_CM4 diff --git a/boards/arm/mimx8mq_evk/doc/index.rst b/boards/arm/mimx8mq_evk/doc/index.rst deleted file mode 100644 index 486bf298fec..00000000000 --- a/boards/arm/mimx8mq_evk/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _mimx8mq_evk: - -NXP MIMX8MQ EVK -############### - -Overview -******** - -i.MX8MQ EVK board is based on NXP i.MX8MQ applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. -Zephyr OS is ported to run on the Cortex®-M4 core. - -- Board features: - - - RAM: 3GB LPDDR4 - - Storage: - - - 16GB eMMC5.0 - - 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11 a/b/g/n/ac - - Bluetooth: v4.1 - - USB: - - - OTG - 1x type C - - HOST - 1x type A - - Ethernet - - PCI-E M.2 - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG 10-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M4 - -.. image:: img/mimx8mq_evk.jpg - :align: center - :alt: MIMX8MQ EVK - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mq_evk board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/mimx8mq_evk/mimx8mq_evk_cm4_defconfig`. - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -MIMX8MQ EVK board was tested with the following pinmux controller -configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART2 RXD | UART2_TXD | UART Console | -+---------------+-----------------+---------------------------+ -| UART2 TXD | UART2_RXD | UART Console | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 266 MHz clock speed. - -Serial Port -=========== - -The i.MX8MQ SoC has four UARTs. UART_2 is configured for the console and -the remaining are not used/tested. - -Programming and Debugging -************************* - -The MIMX8MQ EVK board doesn't have QSPI flash for the M4 and it needs -to be started by the A53 core. The A53 core is responsible to load the M4 binary -application into the RAM, put the M4 in reset, set the M4 Program Counter and -Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at -bootloader level or after the Linux system has booted. - -The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.dts`` -with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. -The available configurations are: - -.. code-block:: none - - "zephyr,flash" - - &tcml_code - - &ocram_code - - &ocram_s_code - - "zephyr,sram" - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - -Load and run Zephyr on M4 from A53 using u-boot. - -.. tabs:: - - .. group-tab:: From an SD card - Copy the compiled ``zephyr.bin`` to the first FAT partition of the - SD card and plug the SD card into the board. Power it up and stop the u-boot - execution at prompt. - - Load the M4 binary onto the desired memory and start its execution using: - - .. code-block:: console - - fatload mmc 0:1 0x40480000 zephyr.bin - cp.b 0x40480000 0x7e0000 0x8000 - bootaux 0x7e0000 - - .. group-tab:: From serial - This procedure requires ``screen`` and ``lrzsz`` to be installed. - - Start ``screen``, power up the board, and stop the u-boot execution at prompt: - - .. code-block:: console - - screen 115200 - - Start ``loadx`` with offset ``7e0000``: - - .. code-block:: console - - loadx 7e0000 115200 - - Send the compiled ``zephyr.bin`` with ``sx`` by pressing :kbd:`Ctrl-a` followed by :kbd:`:` - and write: - - .. code-block:: console - - exec !! sx - - Start execution: - - .. code-block:: console - - bootaux 0x7e0000 - -Debugging -========= - -MIMX8MQ EVK board can be debugged by connecting an external JLink -JTAG debugger to the J401 debug connector and to the PC. Then -the application can be debugged using the usual way. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimx8mq_evk_cm4 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS build zephyr-v2.6.99-30942-g6ee70bd22058 ***** - Hello World! mimx8mq_evk_cm4 - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-applications-processor:MCIMX8M-EVK - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM diff --git a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.dts b/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.dts deleted file mode 100644 index 9197477e8ea..00000000000 --- a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2021, Kwon Tae-young - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mq_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MQ EVK board"; - compatible = "nxp,mimx8mq_evk"; - - aliases { - uart-2 = &uart2; - }; - - chosen { - zephyr,flash = &tcml_code; - zephyr,sram = &tcmu_sys; - zephyr,console = &uart2; - zephyr,shell-uart = &uart2; - }; -}; - -&uart2 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.yaml b/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.yaml deleted file mode 100644 index f5fee9cea2f..00000000000 --- a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2021, Kwon Tae-young -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mq_evk_cm4 -name: NXP i.MX8MQ EVK CM4 -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -vendor: nxp diff --git a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4_defconfig b/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4_defconfig deleted file mode 100644 index d1b9de332f6..00000000000 --- a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2021, Kwon Tae-young -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8MQ_M4=y -CONFIG_SOC_MIMX8MQ6=y -CONFIG_BOARD_MIMX8MQ_EVK_CM4=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1010_evk/CMakeLists.txt b/boards/arm/mimxrt1010_evk/CMakeLists.txt deleted file mode 100644 index 53422e1b030..00000000000 --- a/boards/arm/mimxrt1010_evk/CMakeLists.txt +++ /dev/null @@ -1,33 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_library() -zephyr_library_sources(init.c) - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - if(NOT DEFINED CONFIG_BOARD_MIMXRT1010_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1010-EVK, but targeting a custom board. You may need to " - "update your flash configuration data blocks") - endif() - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1010 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT1010_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1010") - zephyr_library_sources(${RT1010_BOARD_DIR}/xip/evkmimxrt1010_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1010_BOARD_DIR}/xip) - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1010_evk/Kconfig.board b/boards/arm/mimxrt1010_evk/Kconfig.board deleted file mode 100644 index 7ccc2051073..00000000000 --- a/boards/arm/mimxrt1010_evk/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_MIMXRT1010_EVK - bool "NXP MIMXRT1010-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1011DAE5A diff --git a/boards/arm/mimxrt1010_evk/Kconfig.defconfig b/boards/arm/mimxrt1010_evk/Kconfig.defconfig deleted file mode 100644 index da98cdf9ffa..00000000000 --- a/boards/arm/mimxrt1010_evk/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# MIMXRT1010-EVK board - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1010_EVK - -config BOARD - default "mimxrt1010_evk" if BOARD_MIMXRT1010_EVK - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -endif # BOARD_MIMXRT1010_EVK diff --git a/boards/arm/mimxrt1015_evk/CMakeLists.txt b/boards/arm/mimxrt1015_evk/CMakeLists.txt deleted file mode 100644 index 005b4f2398d..00000000000 --- a/boards/arm/mimxrt1015_evk/CMakeLists.txt +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT DEFINED CONFIG_BOARD_MIMXRT1015_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1015-EVK, but targeting a custom board. You may need to " - "update your flash configuration data blocks") - endif() - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1015 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT1015_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1015") - zephyr_library_sources(${RT1015_BOARD_DIR}/xip/evkmimxrt1015_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1015_BOARD_DIR}/xip) - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1015_evk/Kconfig.board b/boards/arm/mimxrt1015_evk/Kconfig.board deleted file mode 100644 index a5dee5762f8..00000000000 --- a/boards/arm/mimxrt1015_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1015_EVK - bool "NXP MIMXRT1015-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1015DAF5A diff --git a/boards/arm/mimxrt1015_evk/Kconfig.defconfig b/boards/arm/mimxrt1015_evk/Kconfig.defconfig deleted file mode 100644 index 215f75a827e..00000000000 --- a/boards/arm/mimxrt1015_evk/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# MIMXRT1015-EVK board - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1015_EVK - -config BOARD - default "mimxrt1015_evk" if BOARD_MIMXRT1015_EVK - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -endif # BOARD_MIMXRT1015_EVK diff --git a/boards/arm/mimxrt1020_evk/CMakeLists.txt b/boards/arm/mimxrt1020_evk/CMakeLists.txt deleted file mode 100644 index 09e7641d928..00000000000 --- a/boards/arm/mimxrt1020_evk/CMakeLists.txt +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT DEFINED CONFIG_BOARD_MIMXRT1020_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1020-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - set(RT1020_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1020") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1020 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1020_BOARD_DIR}/xip/evkmimxrt1020_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1020_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1020 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1020_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1020_evk/Kconfig.board b/boards/arm/mimxrt1020_evk/Kconfig.board deleted file mode 100644 index e8ac44ef192..00000000000 --- a/boards/arm/mimxrt1020_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1020_EVK - bool "NXP MIMXRT1020-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1021DAG5A diff --git a/boards/arm/mimxrt1020_evk/Kconfig.defconfig b/boards/arm/mimxrt1020_evk/Kconfig.defconfig deleted file mode 100644 index 4ecf9c39c1d..00000000000 --- a/boards/arm/mimxrt1020_evk/Kconfig.defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# MIMXRT1020-EVK board - -# Copyright 2018,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1020_EVK - -config BOARD - default "mimxrt1020_evk" if BOARD_MIMXRT1020_EVK - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -if NETWORKING - -config NET_L2_ETHERNET - default y - -config ETH_MCUX_PHY_RESET - default y - -endif # NETWORKING - -endif # BOARD_MIMXRT1020_EVK diff --git a/boards/arm/mimxrt1024_evk/CMakeLists.txt b/boards/arm/mimxrt1024_evk/CMakeLists.txt deleted file mode 100644 index b7e94224cc7..00000000000 --- a/boards/arm/mimxrt1024_evk/CMakeLists.txt +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT DEFINED CONFIG_BOARD_MIMXRT1024_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1024-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - set(RT1024_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1024") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1024 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1024_BOARD_DIR}/xip/evkmimxrt1024_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1024_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1024 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1024_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1024_evk/Kconfig.board b/boards/arm/mimxrt1024_evk/Kconfig.board deleted file mode 100644 index e3468871e2a..00000000000 --- a/boards/arm/mimxrt1024_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1024_EVK - bool "NXP MIMXRT1024-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1024DAG5A diff --git a/boards/arm/mimxrt1024_evk/Kconfig.defconfig b/boards/arm/mimxrt1024_evk/Kconfig.defconfig deleted file mode 100644 index db0a2eb1fed..00000000000 --- a/boards/arm/mimxrt1024_evk/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# MIMXRT1024-EVK board - -# Copyright 2020,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1024_EVK - -config BOARD - default "mimxrt1024_evk" if BOARD_MIMXRT1024_EVK - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -config I2C_MCUX_LPI2C_BUS_RECOVERY - default y - depends on I2C_MCUX_LPI2C && PINCTRL - -if NETWORKING - -config NET_L2_ETHERNET - default y - -if ETH_MCUX - -config ETH_MCUX_PHY_RESET - default y - -endif # ETH_MCUX - -endif # NETWORKING - -endif # BOARD_MIMXRT1024_EVK diff --git a/boards/arm/mimxrt1040_evk/CMakeLists.txt b/boards/arm/mimxrt1040_evk/CMakeLists.txt deleted file mode 100644 index 98ff54d4bc2..00000000000 --- a/boards/arm/mimxrt1040_evk/CMakeLists.txt +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT DEFINED CONFIG_BOARD_MIMXRT1040_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1040-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - set(RT1040_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1040") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1040 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1040_BOARD_DIR}/xip/evkmimxrt1040_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1040_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1040 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1040_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1040_evk/Kconfig.board b/boards/arm/mimxrt1040_evk/Kconfig.board deleted file mode 100644 index d8374b6bfad..00000000000 --- a/boards/arm/mimxrt1040_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2023, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1040_EVK - bool "NXP MIMXRT1040-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1042XJM5B diff --git a/boards/arm/mimxrt1040_evk/Kconfig.defconfig b/boards/arm/mimxrt1040_evk/Kconfig.defconfig deleted file mode 100644 index 683da9279ed..00000000000 --- a/boards/arm/mimxrt1040_evk/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2023, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1040_EVK - -config BOARD - default "mimxrt1040_evk" if BOARD_MIMXRT1040_EVK - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -endif # BOARD_MIMXRT1040_EVK diff --git a/boards/arm/mimxrt1040_evk/doc/index.rst b/boards/arm/mimxrt1040_evk/doc/index.rst deleted file mode 100644 index 651a0aebff9..00000000000 --- a/boards/arm/mimxrt1040_evk/doc/index.rst +++ /dev/null @@ -1,372 +0,0 @@ -.. _mimxrt1040_evk: - -NXP MIMXRT1040-EVK -################## - -Overview -******** - -i.MX RT1040 crossover MCUs add additional flexibility with new packages and an -extended temperature range up to 125° C. The i.MX RT1040 MCU has a compact -9x9 mm package, as well as the 11x11 mm package that supports implementing a -2-layer PCB design. The i.MX RT1040 MCUs run on the Arm® Cortex®-M7 core at -600 MHz. - -.. image:: mimxrt1040_evk.jpg - :align: center - :alt: MIMXRT1040-EVK - -Hardware -******** - -- MIMXRT1042XJM5B MCU (600 MHz, 512 KB TCM) - -- Memory - - - 256 MBit SDRAM (Winbond W9825G6KH) - - 64 Mbit QSPI Flash (Winbond W25Q64JVSSIQ) - -- Display - - - LCD connector - - Touch connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - OpenSDA with DAPLink - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1040 SoC and MIMXRT1040-EVK board, see -these references: - -- `i.MX RT1040 Website`_ -- `i.MX RT1040 Datasheet`_ -- `i.MX RT1040 Reference Manual`_ -- `MIMXRT1040-EVK Website`_ -- `MIMXRT1040-EVK User Guide`_ -- `MIMXRT1040-EVK Design Files`_ - -External Memory -=============== - -This platform has the following external memories: - -+----------------+------------+-------------------------------------+ -| Device | Controller | Status | -+================+============+=====================================+ -| W9825G6KH | SEMC | Enabled via device configuration | -| | | data block, which sets up SEMC at | -| | | boot time | -+----------------+------------+-------------------------------------+ -| W25Q64JVSSIQ | FLEXSPI | Enabled via flash configurationn | -| | | block, which sets up FLEXSPI at | -| | | boot time. Supported for XIP only. | -+----------------+------------+-------------------------------------+ - -Supported Features -================== - -The mimxrt1040_evk board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the mimxrt1064_evk board may have additional features -already supported, which can also be re-used on this mimxrt1040_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/mimxrt1040_evk/mimxrt1040_evk_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The MIMXRT1040 SoC has five pairs of pinmux/gpio controllers. - -+---------------+-----------------+---------------------------+ -| Name | Function | Usage | -+===============+=================+===========================+ -| GPIO_AD_B0_12 | LPUART1_TX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_13 | LPUART1_RX | UART Console | -+---------------+-----------------+---------------------------+ -| WAKEUP | GPIO | SW0 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_08 | GPIO | User LD1 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | FLEXPWM1 PWM3A | PWM Output | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_14 | ADC0 IN3 | ADC0 Input | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_15 | ADC0 IN4 | ADC0 Input | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_02 | LPSPI1_SDO | SPI Output | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_03 | LPSPI1_SDI | SPI Input | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_00 | LPSPI1_SCK | SPI Clock | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_00 | LPSPI1_SCK | SPI Clock | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_00 | LPI2C1_SCL | I2C Clock | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_01 | LPI2C1_SDA | I2C Data | -+---------------+-----------------+---------------------------+ - -.. note:: - In order to use the SPI peripheral on this board, resistors R350, R346, - and R360 must be populated with zero ohm resistors. - -System Clock -============ - -The MIMXRT1040 SoC is configured to use SysTick as the system clock source, -running at 600MHz. - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - -Serial Port -=========== - -The MIMXRT1040 SoC has eight UARTs. ``LPUART1`` is configured for the console, -and the remaining UARTs are not used. - - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended) ----------------------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Check that jumpers J9 and J10 are **on** to ensure SWD signals are connected to -the OpenSDA microcontroller. Then, follow the instructions in `NXP AN13206`_ to -program a JLink based firmware to the LPC4322 based debugger on this board. - -Once the JLink based firmware is present on this board, the SOC will no longer -be powered via the USB connection to J1. Move J40 to short pins 3 and 4 in -order to use J48 for USB power, and connect another USB cable to power the SoC. -LED D16 should illuminate to indicate the board is powered, and it should now be -possible to program the SoC. - -Option 2: :ref:`jlink-external-debug-probe` -------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -The board can be programmed using the :ref:`jlink-external-debug-probe`, -provided the onboard debug circuit's SWD signals are isolated from the MCU. -To do so, ensure that jumpers J9 and J10 are **off** (they are on by default -when the board ships from the factory). The external probe's 20 pin connector -can then be connected to J2 to program the SOC. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. Check that -jumpers J11 and J13 are **on** (they are on by default when boards ship from -the factory) to connect UART signals to the OpenSDA microcontroller. - -Connect a USB cable from your PC to J1. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1040_evk - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS Booting Zephyr OS build v3.3.0-rc3-66 ***** - Hello World! mimxrt1040_evk - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1040_evk - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS Booting Zephyr OS build v3.3.0-rc3-66 ***** - Hello World! mimxrt1040_evk - -Troubleshooting -=============== - -USER_LED D8 ------------ -The MIMXRT1040-EVK board ships with the wireless module in the M.2 connector, -and with jumper J80 shorted. This causes a conflict with the USER_LED D8, -and the LED will not turn off. Samples and applications using USER_LED D8, -like blinky, require removal of J80 jumper. - -Boot Header ------------ - -If the debug probe fails to connect with the following error, it's possible -that the boot header in QSPI is invalid or corrupted. The boot header is -configured by :kconfig:option:`CONFIG_NXP_IMX_RT_BOOT_HEADER`. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the QSPI with the following -steps: - -#. Set the SW4 DIP switches to OFF-OFF-OFF-ON to boot into the ROM bootloader. - -#. Reset by pressing SW1 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application. - -#. Set the SW4 DIP switches to OFF-OFF-ON-OFF to boot from QSPI. - -#. Reset by pressing SW1 - - -WiFi Module ------------ - -If the debugger fails to connect with the following error, it's possible -the M.2 WiFi module is interfering with the debug signals - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -To resolve this, you may remove the M.2 WiFi module from the board when -flashing or debugging it, or remove jumper J80. - - -.. _MIMXRT1040-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1040-evaluation-kit:MIMXRT1040-EVK - -.. _MIMXRT1040-EVK User Guide: - https://www.nxp.com/webapp/Download?colCode=MIMXRT1040-EVKUM - -.. _MIMXRT1040-EVK Design Files: - https://www.nxp.com/webapp/Download?colCode=MIMXRT1040-EVK-DESIGNFILES - -.. _i.MX RT1040 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1040-crossover-mcu-with-arm-cortex-m7-core:i.MX-RT1040 - -.. _i.MX RT1040 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT1040CEC.pdf - -.. _i.MX RT1040 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT1040RM - -.. _NXP AN13206: - https://www.nxp.com/docs/en/application-note/AN13206.pdf diff --git a/boards/arm/mimxrt1040_evk/mimxrt1040_evk_defconfig b/boards/arm/mimxrt1040_evk/mimxrt1040_evk_defconfig deleted file mode 100644 index 94b11471e04..00000000000 --- a/boards/arm/mimxrt1040_evk/mimxrt1040_evk_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1042=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1040_EVK=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1050_evk/CMakeLists.txt b/boards/arm/mimxrt1050_evk/CMakeLists.txt deleted file mode 100644 index 9a136bb8d82..00000000000 --- a/boards/arm/mimxrt1050_evk/CMakeLists.txt +++ /dev/null @@ -1,55 +0,0 @@ -# -# Copyright 2017-2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if (CONFIG_DISPLAY) -message(WARNING " -CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board -") -endif() - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(CONFIG_BOARD_MIMXRT1050_EVK) - set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) - elseif(CONFIG_BOARD_MIMXRT1050_EVK_QSPI) - set(FLASH_CONF evkbimxrt1050_flexspi_nor_qspi_config.c) - else() - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1050-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - # Default EVK configuration uses hyperflash, so use that file - set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) - endif() - set(RT1050_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkbimxrt1050") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1050 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1050_BOARD_DIR}/xip/${FLASH_CONF}) - zephyr_library_include_directories(${RT1050_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1050 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1050_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1050_evk/Kconfig.board b/boards/arm/mimxrt1050_evk/Kconfig.board deleted file mode 100644 index 9627ee20319..00000000000 --- a/boards/arm/mimxrt1050_evk/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1050_EVK - bool "NXP MIMXRT1050-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1052DVL6A - -config BOARD_MIMXRT1050_EVK_QSPI - bool "NXP MIMXRT1050-EVK-QSPI" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1052DVL6A diff --git a/boards/arm/mimxrt1050_evk/Kconfig.defconfig b/boards/arm/mimxrt1050_evk/Kconfig.defconfig deleted file mode 100644 index 79660c08e78..00000000000 --- a/boards/arm/mimxrt1050_evk/Kconfig.defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# MIMXRT1050-EVK board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1050_EVK || BOARD_MIMXRT1050_EVK_QSPI - -config BOARD - default "mimxrt1050_evk" if BOARD_MIMXRT1050_EVK - default "mimxrt1050_evk_qspi" if BOARD_MIMXRT1050_EVK_QSPI - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -if FLASH - -config FLASH_MCUX_FLEXSPI_HYPERFLASH - default y if BOARD_MIMXRT1050_EVK - default n if BOARD_MIMXRT1050_EVK_QSPI - -config FLASH_MCUX_FLEXSPI_NOR - default y if BOARD_MIMXRT1050_EVK_QSPI - default n if BOARD_MIMXRT1050_EVK - -endif #FLASH - -config INPUT - default y if LVGL - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - -if NETWORKING - -config NET_L2_ETHERNET - default y - -if ETH_MCUX - -config ETH_MCUX_PHY_RESET - default y - -endif # ETH_MCUX - -endif # NETWORKING - -if LVGL - -config LV_Z_VDB_SIZE - default 16 - -config LV_DPI_DEF - default 128 - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -endif # LVGL - -endif # BOARD_MIMXRT1050_EVK || BOARD_MIMXRT1050_EVK_QSPI diff --git a/boards/arm/mimxrt1050_evk/board.cmake b/boards/arm/mimxrt1050_evk/board.cmake deleted file mode 100644 index 265ce1cd5f8..00000000000 --- a/boards/arm/mimxrt1050_evk/board.cmake +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# -board_runner_args(jlink "--device=MCIMXRT1052") - -if(${CONFIG_BOARD_MIMXRT1050_EVK_QSPI}) - board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") - board_runner_args(pyocd "--target=mimxrt1050_quadspi") -else() - board_runner_args(pyocd "--target=mimxrt1050_hyperflash") - board_runner_args(linkserver "--device=MIMXRT1052xxxxB:EVKB-IMXRT1050") - include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) -endif() - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/arm/mimxrt1050_evk/doc/index.rst b/boards/arm/mimxrt1050_evk/doc/index.rst deleted file mode 100644 index de225ae56f3..00000000000 --- a/boards/arm/mimxrt1050_evk/doc/index.rst +++ /dev/null @@ -1,499 +0,0 @@ -.. _mimxrt1050_evk: - -NXP MIMXRT1050-EVK -################## - -Overview -******** - -The i.MX RT1050 is a new processor family featuring NXP's advanced -implementation of the ARM Cortex-M7 Core. It provides high CPU performance and -real-time response. - -The i.MX RT1050 provides various memory interfaces, including SDRAM, Raw NAND -FLASH, NOR FLASH, SD/eMMC, Quad SPI, HyperBus and a wide range of other -interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, displays, -and camera sensors. As with other i.MX processors, i.MX RT1050 also has rich -audio and video features, including LCD display, basic 2D graphics, camera -interface, SPDIF, and I2S audio interface. - -The following document refers to the discontinued MIMXRT1050-EVK board. For the -MIMXRT1050-EVKB board, refer to `Board Revisions`_ section. - -.. image:: mimxrt1050_evk.jpg - :align: center - :alt: MIMXRT1050-EVK - -Hardware -******** - -- MIMXRT1052DVL6A MCU (600 MHz, 512 KB TCM) - -- Memory - - - 256 KB SDRAM - - 64 Mbit QSPI Flash - - 512 Mbit Hyper Flash - -- Display - - - LCD connector - - Touch connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - - USB 2.0 host connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - - Left and right speaker out connectors - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - OpenSDA with DAPLink - -- Sensor - - - FXOS8700CQ 6-axis e-compass - - CMOS camera sensor interface - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1050 SoC and MIMXRT1050-EVK board, see -these references: - -- `i.MX RT1050 Website`_ -- `i.MX RT1050 Datasheet`_ -- `i.MX RT1050 Reference Manual`_ -- `MIMXRT1050-EVK Website`_ -- `MIMXRT1050-EVK User Guide`_ -- `MIMXRT1050-EVK Schematics`_ - -External Memory -=============== - -This platform has the following external memories: - -+--------------------+------------+-------------------------------------+ -| Device | Controller | Status | -+====================+============+=====================================+ -| IS42S16160J | SEMC | Enabled via device configuration | -| | | data block, which sets up SEMC at | -| | | boot time | -+--------------------+------------+-------------------------------------+ -| S26KS512SDPBHI020 | FLEXSPI | Enabled via flash configurationn | -| | | block, which sets up FLEXSPI at | -| | | boot time. | -+--------------------+------------+-------------------------------------+ - -Supported Features -================== - -The mimxrt1050_evk board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the mimxrt1064_evk board may have additional features -already supported, which can also be re-used on this mimxrt1050_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | display | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SDHC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| ENET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| GPT | on-chip | gpt | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The MIMXRT1050 SoC has five pairs of pinmux/gpio controllers. - -+---------------+-----------------+---------------------------+ -| Name | Function | Usage | -+===============+=================+===========================+ -| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_05 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | GPIO/ENET_RST | LED | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_11 | GPIO | Touch Interrupt | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_12 | LPUART1_TX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_13 | LPUART1_RX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_00 | LPI2C1_SCL | I2C | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_01 | LPI2C1_SDA | I2C | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_11 | ADC | ADC1 channel 0 | -+---------------+-----------------+---------------------------+ -| WAKEUP | GPIO | SW0 | -+---------------+-----------------+---------------------------+ -| GPIO_B0_00 | LCD_CLK | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_01 | LCD_ENABLE | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_02 | LCD_HSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_03 | LCD_VSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_04 | LCD_DATA00 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_05 | LCD_DATA01 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_06 | LCD_DATA02 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_07 | LCD_DATA03 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_08 | LCD_DATA04 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_09 | LCD_DATA05 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_10 | LCD_DATA06 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_11 | LCD_DATA07 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_12 | LCD_DATA08 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_13 | LCD_DATA09 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_14 | LCD_DATA10 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_15 | LCD_DATA11 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_00 | LCD_DATA12 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_01 | LCD_DATA13 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_02 | LCD_DATA14 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_03 | LCD_DATA15 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_06 | ENET_RX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_09 | ENET_TX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_10 | ENET_REF_CLK | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_11 | ENET_RX_ER | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_12 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_14 | USDHC1_VSELECT | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_40 | ENET_MDC | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_41 | ENET_MDIO | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | ENET_RST | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | ENET_INT | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_02 | 1588_EVENT2_OUT | 1588 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_03 | 1588_EVENT2_IN | 1588 | -+---------------+-----------------+---------------------------+ - -.. note:: - In order to use the SPI peripheral on this board, resistors R278, - R279, R280, and R281 must be populated with zero ohm resistors - -System Clock -============ - -The MIMXRT1050 SoC is configured to use SysTick as the system clock source, -running at 600MHz. - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - -Serial Port -=========== - -The MIMXRT1050 SoC has eight UARTs. ``LPUART1`` is configured for the console, -``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the -remaining are not used. - -USB -=== - -The RT1050 SoC has two USB OTG (USBOTG) controllers that supports both -device and host functions through its micro USB connectors. -Only USB device function is supported in Zephyr at the moment. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -Using LinkServer ----------------- - -Install the :ref:`linkserver-debug-host-tools` and make sure they are in your -search path. LinkServer works with the default CMSIS-DAP firmware included in -the on-board debugger. - -Linkserver is the default runner. You may also se the ``-r linkserver`` option -with West to use the LinkServer runner. - -.. code-block:: console - - west flash - west debug - -JLink (on-board): :ref:`opensda-jlink-onboard-debug-probe` ----------------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link MIMXRT1050-EVK-Hyperflash Firmware`_. Check that jumpers -J32 and J33 are **on** (they are on by default when boards ship from the -factory) to ensure SWD signals are connected to the OpenSDA microcontroller. - -Follow the instructions in `Enable QSPI flash support in SEGGER JLink`_ -in order to support your EVK if you have modified it to boot from QSPI NOR -flash as specified by NXP AN12108. - -External JLink :ref:`jlink-external-debug-probe` ------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Attach a J-Link 20-pin connector to J21. Check that jumpers J32 and J33 are -**off** (they are on by default when boards ship from the factory) to ensure -SWD signals are disconnected from the OpenSDA microcontroller. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. Check that -jumpers J30 and J31 are **on** (they are on by default when boards ship from -the factory) to connect UART signals to the OpenSDA microcontroller. - -Connect a USB cable from your PC to J28. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1050_evk - :goals: flash - -Open a serial terminal, reset the board (press the SW4 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1050_evk - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1050_evk - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1050_evk - -Troubleshooting -=============== - -If the debug probe fails to connect with the following error, it's possible -that the boot header in HyperFlash is invalid or corrupted. The boot header is -configured by :kconfig:option:`CONFIG_NXP_IMX_RT_BOOT_HEADER`. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the HyperFlash with the following -steps: - -#. Set the SW7 DIP switches to ON-ON-ON-OFF to prevent booting from HyperFlash. - -#. Reset by pressing SW4 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application. - -#. Set the SW7 DIP switches to OFF-ON-ON-OFF to boot from HyperFlash. - -#. Reset by pressing SW4 - -Board Revisions -*************** - -The original MIMXRT1050-EVK (rev A0) board was updated with a newer -MIMXRT1050-EVKB (rev A1) board, with these major hardware differences: - -- SoC changed from MIMXRT1052DVL6\ **A** to MIMXRT1052DVL6\ **B** -- Hardware bug fixes for: power, interfaces, and memory -- Arduino headers included - -For more details, please see the following `NXP i.MXRT1050 A0 to A1 Migration Guide`_. - -Current Zephyr build supports the new MIMXRT1050-EVKB - -.. _MIMXRT1050-EVK Website: - https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK - -.. _MIMXRT1050-EVK User Guide: - https://www.nxp.com/webapp/Download?colCode=IMXRT1050EVKBHUG - -.. _MIMXRT1050-EVK Schematics: - https://www.nxp.com/webapp/Download?colCode=MIMXRT1050-EVK-DESIGNFILES - -.. _i.MX RT1050 Website: - https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1050 - -.. _i.MX RT1050 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT1050CEC.pdf - -.. _i.MX RT1050 Reference Manual: - https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf - -.. _OpenSDA J-Link MIMXRT1050-EVK-Hyperflash Firmware: - https://www.segger.com/downloads/jlink/OpenSDA_MIMXRT1050-EVK-Hyperflash - -.. _NXP i.MXRT1050 A0 to A1 Migration Guide: - https://www.nxp.com/docs/en/nxp/application-notes/AN12146.pdf - -.. _Enable QSPI flash support in SEGGER JLink: - https://wiki.segger.com/i.MXRT1050#QSPI_flash - -Experimental ENET Driver -======================== - -Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new -driver with binding `nxp,enet`, which is experimental and undergoing development, but will have -enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. - -To build for this EVK with the new driver, include the experimental overlay to west build with -the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig deleted file mode 100644 index 0c3fd3485d8..00000000000 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1052=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1050_EVK=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.dts b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.dts deleted file mode 100644 index 27542b88bfd..00000000000 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.dts +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2017, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "mimxrt1050_evk.dts" - -/delete-node/ &s26ks512s0; - -/ { - chosen { - zephyr,flash-controller = &is25wp064; - zephyr,flash = &is25wp064; - zephyr,code-partition = &slot0_partition; - }; -}; - -&flexspi { - status = "okay"; - ahb-prefetch; - ahb-read-addr-opt; - rx-clock-source = <1>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; - is25wp064: is25wp064@0 { - compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; - reg = <0>; - spi-max-frequency = <133000000>; - status = "okay"; - jedec-id = [9d 70 17]; - erase-block-size = <4096>; - write-block-size = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; - }; - slot1_partition: partition@311000 { - label = "image-1"; - reg = <0x00311000 DT_SIZE_M(3)>; - }; - storage_partition: partition@611000 { - label = "storage"; - reg = <0x00611000 DT_SIZE_K(1980)>; - }; - }; - }; -}; diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.yaml b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.yaml deleted file mode 100644 index baadda8c061..00000000000 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.yaml +++ /dev/null @@ -1,31 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1050_evk_qspi -name: NXP MIMXRT1050-EVK-QSPI -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32768 -flash: 8192 -supported: - - arduino_gpio - - arduino_serial - - counter - - display - - dma - - gpio - - i2c - - netif:eth - - sdhc - - spi - - usb_device - - watchdog - - adc -vendor: nxp diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig deleted file mode 100644 index 5ad5307db8c..00000000000 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1052=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1050_EVK_QSPI=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1060_evk/CMakeLists.txt b/boards/arm/mimxrt1060_evk/CMakeLists.txt deleted file mode 100644 index 84e3812e9a0..00000000000 --- a/boards/arm/mimxrt1060_evk/CMakeLists.txt +++ /dev/null @@ -1,64 +0,0 @@ -# -# Copyright 2018-2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if (CONFIG_DISPLAY) -message(WARNING " -CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board -") -endif() - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(CONFIG_BOARD_MIMXRT1060_EVK) - set(FLASH_CONF evkmimxrt1060_flexspi_nor_config.c) - set(BOARD_NAME evkmimxrt1060) - elseif(CONFIG_BOARD_MIMXRT1060_EVK_HYPERFLASH) - # No flash configuration block exists for the RT1060 with HyperFlash in - # the SDK, but we can reuse the block for the RT1050 as both boards use - # the same HyperFlash chip - set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) - set(BOARD_NAME evkbimxrt1050) - elseif(CONFIG_BOARD_MIMXRT1060_EVKB) - set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c) - set(BOARD_NAME evkbmimxrt1060) - else() - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1060-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - # Default EVK configuration uses qspi, so use that file - set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c) - set(BOARD_NAME evkbmimxrt1060) - endif() - set(RT1060_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${BOARD_NAME}") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1060 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1060_BOARD_DIR}/xip/${FLASH_CONF}) - zephyr_library_include_directories(${RT1060_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1060 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1060_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1060_evk/Kconfig.board b/boards/arm/mimxrt1060_evk/Kconfig.board deleted file mode 100644 index d075c432477..00000000000 --- a/boards/arm/mimxrt1060_evk/Kconfig.board +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1060_EVK - bool "NXP MIMXRT1060-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A - -config BOARD_MIMXRT1060_EVK_HYPERFLASH - bool "NXP MIMXRT1060-EVK-HYPERFLASH" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A - -config BOARD_MIMXRT1060_EVKB - bool "NXP MIMXRT1060-EVKB" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/arm/mimxrt1060_evk/Kconfig.defconfig b/boards/arm/mimxrt1060_evk/Kconfig.defconfig deleted file mode 100644 index b3b325805fa..00000000000 --- a/boards/arm/mimxrt1060_evk/Kconfig.defconfig +++ /dev/null @@ -1,96 +0,0 @@ -# MIMXRT1060-EVK board - -# Copyright 2018,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVK_HYPERFLASH || BOARD_MIMXRT1060_EVKB - -config BOARD - default "mimxrt1060_evk" if BOARD_MIMXRT1060_EVK - default "mimxrt1060_evk_hyperflash" if BOARD_MIMXRT1060_EVK_HYPERFLASH - default "mimxrt1060_evkb" if BOARD_MIMXRT1060_EVKB - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -if FLASH - -config FLASH_MCUX_FLEXSPI_NOR - default y if BOARD_MIMXRT1060_EVK - default y if BOARD_MIMXRT1060_EVKB - default n if BOARD_MIMXRT1060_EVK_HYPERFLASH - -config FLASH_MCUX_FLEXSPI_HYPERFLASH - default y if BOARD_MIMXRT1060_EVK_HYPERFLASH - default n if BOARD_MIMXRT1060_EVK - default n if BOARD_MIMXRT1060_EVKB - -endif #FLASH - -config INPUT - default y if LVGL - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - -if NETWORKING - -config NET_L2_ETHERNET - default y - -if ETH_MCUX - -config ETH_MCUX_PHY_RESET - default y - -endif # ETH_MCUX - -endif # NETWORKING - -if LVGL - -# LVGL should allocate buffers equal to size of display -config LV_Z_VDB_SIZE - default 100 - -# Enable double buffering -config LV_Z_DOUBLE_VDB - default y - -# Force full refresh. This prevents memory copy associated with partial -# display refreshes, which is not necessary for the eLCDIF driver -config LV_Z_FULL_REFRESH - default y - -config LV_DPI_DEF - default 128 - -config LV_Z_BITS_PER_PIXEL - default 16 - -# Force display buffers to be aligned to cache line size (32 bytes) -config LV_Z_VDB_ALIGN - default 32 - -# Use offloaded render thread -config LV_Z_FLUSH_THREAD - default y - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -endif # LVGL - -endif # BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVK_HYPERFLASH || BOARD_MIMXRT1060_EVKB diff --git a/boards/arm/mimxrt1060_evk/board.cmake b/boards/arm/mimxrt1060_evk/board.cmake deleted file mode 100644 index d3031f1542e..00000000000 --- a/boards/arm/mimxrt1060_evk/board.cmake +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2018, 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_runner_args(pyocd "--target=mimxrt1060") -board_runner_args(jlink "--device=MIMXRT1062xxx6A") -board_runner_args(linkserver "--device=MIMXRT1062xxxxA:EVK-MIMXRT1060") - -if ((${CONFIG_BOARD_MIMXRT1060_EVK}) OR (${CONFIG_BOARD_MIMXRT1060_EVKB})) - board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") -elseif (${CONFIG_BOARD_MIMXRT1060_EVK_HYPERFLASH}) - board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=HyperFlash") -endif() - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/arm/mimxrt1060_evk/doc/index.rst b/boards/arm/mimxrt1060_evk/doc/index.rst deleted file mode 100644 index cfd546e5b37..00000000000 --- a/boards/arm/mimxrt1060_evk/doc/index.rst +++ /dev/null @@ -1,484 +0,0 @@ -.. _mimxrt1060_evk: - -NXP MIMXRT1060-EVK -################## - -Overview -******** - -The i.MX RT1060 adds to the industry's first crossover -processor series and expands the i.MX RT series to three scalable families. - -The i.MX RT1060 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin -compatibility with i.MX RT1050. This series introduces additional features -ideal for real-time applications such as High-Speed GPIO, CAN FD, and -synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1060 runs on the -Arm® Cortex-M7® core up to 600 MHz. - -.. image:: mimxrt1060_evk.jpg - :align: center - :alt: MIMXRT1060-EVK - -Hardware -******** - -- MIMXRT1062DVL6A MCU (600 MHz, 1024 KB on-chip memory) - -- Memory - - - 256 Mbit SDRAM - - 64 Mbit QSPI Flash - - 512 Mbit Hyper Flash - - TF socket for SD card - -- Display - - - LCD connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - - USB 2.0 host connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - - Left and right speaker out connectors - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - OpenSDA with DAPLink - -- Sensor - - - FXOS8700CQ 6-axis e-compass - - CMOS camera sensor interface - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1060 SoC and MIMXRT1060-EVK board, see -these references: - -- `i.MX RT1060 Website`_ -- `i.MX RT1060 Datasheet`_ -- `i.MX RT1060 Reference Manual`_ -- `MIMXRT1060-EVK Website`_ -- `MIMXRT1060-EVK User Guide`_ -- `MIMXRT1060-EVK Schematics`_ -- `MIMXRT1060-EVK Debug Firmware`_ - -External Memory -=============== - -This platform has the following external memories: - -+--------------------+------------+-------------------------------------+ -| Device | Controller | Status | -+====================+============+=====================================+ -| IS25WP064AJBLE | SEMC | Enabled via device configuration | -| | | data block, which sets up SEMC at | -| | | boot time | -+--------------------+------------+-------------------------------------+ -| IS42S16160J | FLEXSPI | Enabled via flash configurationn | -| | | block, which sets up FLEXSPI at | -| | | boot time. | -+--------------------+------------+-------------------------------------+ - -Supported Features -================== - -The mimxrt1060_evk board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the mimxrt1064_evk board may have additional features -already supported, which can also be re-used on this mimxrt1060_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | display | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | QSPI flash | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SDHC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| ENET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| SAI | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| GPT | on-chip | gpt | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and I/Os -==================== - -The MIMXRT1060 SoC has five pairs of pinmux/gpio controllers. - -+---------------+-----------------+---------------------------+ -| Name | Function | Usage | -+===============+=================+===========================+ -| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_05 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | GPIO/ENET_RST | LED | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_11 | GPIO | Touch Interrupt | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_12 | LPUART1_TX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_13 | LPUART1_RX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_00 | LPI2C1_SCL | I2C | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_01 | LPI2C1_SDA | I2C | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI | -+---------------+-----------------+---------------------------+ -| WAKEUP | GPIO | SW0 | -+---------------+-----------------+---------------------------+ -| GPIO_B0_00 | LCD_CLK | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_01 | LCD_ENABLE | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_02 | LCD_HSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_03 | LCD_VSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_04 | LCD_DATA00 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_05 | LCD_DATA01 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_06 | LCD_DATA02 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_07 | LCD_DATA03 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_08 | LCD_DATA04 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_09 | LCD_DATA05 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_10 | LCD_DATA06 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_11 | LCD_DATA07 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_12 | LCD_DATA08 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_13 | LCD_DATA09 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_14 | LCD_DATA10 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_15 | LCD_DATA11 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_00 | LCD_DATA12 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_01 | LCD_DATA13 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_02 | LCD_DATA14 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_03 | LCD_DATA15 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_06 | ENET_RX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_09 | ENET_TX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_10 | ENET_REF_CLK | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_11 | ENET_RX_ER | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_12 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_14 | USDHC1_VSELECT | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_40 | ENET_MDC | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_41 | ENET_MDIO | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | ENET_RST | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | ENET_INT | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_11 | ADC | ADC1 Channel 0 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_10 | ADC | ADC1 Channel 15 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_09 | SAI1_MCLK | I2S | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_12 | SAI1_RX | I2S | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_13 | SAI1_TX | I2S | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_14 | SAI1_TX_BCLK | I2S | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_15 | SAI1_TX_SYNC | I2S | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_02 | 1588_EVENT2_OUT | 1588 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_03 | 1588_EVENT2_IN | 1588 | -+---------------+-----------------+---------------------------+ - -.. note:: - In order to use the SPI peripheral on this board, resistors R278, R279, - R280 and R281 must be populated with zero ohm resistors. - -System Clock -============ - -The MIMXRT1060 SoC is configured to use SysTick as the system clock source, -running at 600MHz. - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - - -Serial Port -=========== - -The MIMXRT1060 SoC has eight UARTs. ``LPUART1`` is configured for the console, -``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the -remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -.. _Using LinkServer: - - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `MIMXRT1060-EVK Debug Firmware` - -.. _Using J-Link RT1060: - -Using J-Link ---------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -There are two options: the onboard debug circuit can be updated with Segger -J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the -EVK. See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ or -`Using J-Link with MIMXRT1060-EVKB`_ for more details. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. Check that -jumpers J45 and J46 are **on** (they are on by default when boards ship from -the factory) to connect UART signals to the OpenSDA microcontroller. - -Connect a USB cable from your PC to J41. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Using SWO ---------- -SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``. -Your SWO viewer should be configured with a CPU frequency of 132MHz, and -SWO frequency of 7500KHz. - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1060_evk - :goals: flash - -Open a serial terminal, reset the board (press the SW9 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1060_evk - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1060_evk - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1060_evk - -Troubleshooting -=============== - -If the debug probe fails to connect with the following error, it's possible -that the boot header in QSPI flash is invalid or corrupted. The boot header is -configured by :kconfig:option:`CONFIG_NXP_IMX_RT_BOOT_HEADER`. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the QSPI flash with the following -steps: - -#. Set the SW7 DIP switches to ON-OFF-ON-OFF to prevent booting from QSPI flash. - -#. Reset by pressing SW9 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application. - -#. Set the SW7 DIP switches to OFF-OFF-ON-OFF to boot from QSPI flash. - -#. Reset by pressing SW9 - -If the west flash or debug commands fail, and the command hangs while executing -runners.jlink, confirm the J-Link debug probe is configured, powered, and -connected to the EVK properly. See :ref:`Using J-Link RT1060` for more details. - -.. _MIMXRT1060-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1060-evaluation-kit:MIMXRT1060-EVKB - -.. _MIMXRT1060-EVK User Guide: - https://www.nxp.com/webapp/Download?colCode=MIMXRT10601064EKBHUG - -.. _MIMXRT1060-EVK Debug Firmware: - https://www.nxp.com/docs/en/application-note/AN13206.pdf - -.. _MIMXRT1060-EVK Schematics: - https://www.nxp.com/webapp/Download?colCode=MIMXRT1060-EVK-DESIGNFILE-A3 - -.. _i.MX RT1060 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060 - -.. _i.MX RT1060 Datasheet: - https://www.nxp.com/docs/en/nxp/data-sheets/IMXRT1060CEC.pdf - -.. _i.MX RT1060 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT1060RM - -.. _Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVK-or-MIMXRT1064-EVK/ta-p/1281149 - -.. _Using J-Link with MIMXRT1060-EVKB: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVKB/ta-p/1452717 - -Experimental ENET Driver -======================== - -Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new -driver with binding `nxp,enet`, which is experimental and undergoing development, but will have -enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. - -To build for this EVK with the new driver, include the experimental overlay to west build with -the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig b/boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig deleted file mode 100644 index 40d615261b3..00000000000 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1060_EVK=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.dts b/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.dts deleted file mode 100644 index efdf5e2ff22..00000000000 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2018, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "mimxrt1060_evk.dts" - -/delete-node/ &is25wp064; - -/ { - chosen { - zephyr,flash-controller = &s26ks512s0; - zephyr,flash = &s26ks512s0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&flexspi { - status = "okay"; - ahb-prefetch; - ahb-read-addr-opt; - ahb-bufferable; - ahb-cacheable; - sck-differential-clock; - combination-mode; - rx-clock-source = <3>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; - s26ks512s0: s26ks512s@0 { - compatible = "nxp,imx-flexspi-hyperflash"; - size = ; - reg = <0>; - spi-max-frequency = <166000000>; - word-addressable; - cs-interval-unit = <1>; - cs-interval = <2>; - cs-hold-time = <0>; - cs-setup-time = <3>; - data-valid-time = <1>; - column-space = <3>; - ahb-write-wait-unit = <2>; - ahb-write-wait-interval = <20>; - status = "okay"; - erase-block-size = <4096>; - write-block-size = <16>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(256)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@40000 { - label = "image-0"; - reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; - }; - slot1_partition: partition@341000 { - label = "image-1"; - reg = <0x00341000 DT_SIZE_M(3)>; - }; - storage_partition: partition@641000 { - label = "storage"; - reg = <0x00641000 (DT_SIZE_M(57) + DT_SIZE_K(764))>; - }; - }; - }; -}; diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.yaml b/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.yaml deleted file mode 100644 index fa29bdfaa14..00000000000 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.yaml +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1060_evk_hyperflash -name: NXP MIMXRT1060-EVK-HYPERFLASH -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32768 -flash: 65536 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - counter - - display - - dma - - gpio - - i2c - - netif:eth - - sdhc - - spi - - usb_device - - watchdog -vendor: nxp diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash_defconfig b/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash_defconfig deleted file mode 100644 index 418a8293e11..00000000000 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1060_EVK_HYPERFLASH=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evkb_defconfig b/boards/arm/mimxrt1060_evk/mimxrt1060_evkb_defconfig deleted file mode 100644 index bb1a6edb668..00000000000 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evkb_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2022, Whisper.ai -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1060_EVKB=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1062_fmurt6/CMakeLists.txt b/boards/arm/mimxrt1062_fmurt6/CMakeLists.txt deleted file mode 100644 index 29f92cc83c6..00000000000 --- a/boards/arm/mimxrt1062_fmurt6/CMakeLists.txt +++ /dev/null @@ -1,40 +0,0 @@ -# -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2023 NXP -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(CONFIG_BOARD_MIMXRT1062_FMURT6) - # No flash configuration block exists for the RT1060 with HyperFlash in - # the SDK, but we can reuse the block for the RT1050 as FMURT6 also uses - # the same HyperFlash chip - set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) - set(BOARD_NAME evkbimxrt1050) - endif() - set(RT1062_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${BOARD_NAME}") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1050 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1062_BOARD_DIR}/xip/${FLASH_CONF}) - zephyr_library_include_directories(${RT1062_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1050 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1062_BOARD_DIR}/dcd.c) - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1062_fmurt6/Kconfig.board b/boards/arm/mimxrt1062_fmurt6/Kconfig.board deleted file mode 100644 index 97c653e75f2..00000000000 --- a/boards/arm/mimxrt1062_fmurt6/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright 2023 NXP - -config BOARD_MIMXRT1062_FMURT6 - bool "NXP MIMXRT1062-FMURT6" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/arm/mimxrt1062_fmurt6/Kconfig.defconfig b/boards/arm/mimxrt1062_fmurt6/Kconfig.defconfig deleted file mode 100644 index 8e349eb07ed..00000000000 --- a/boards/arm/mimxrt1062_fmurt6/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# MIMXRT1062-FMURT6 board - -# SPDX-License-Identifier: Apache-2.0 -# Copyright 2023 NXP - -if BOARD_MIMXRT1062_FMURT6 - -config BOARD - default "mimxrt1062_fmurt6" if BOARD_MIMXRT1062_FMURT6 - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - - -endif # BOARD_MIMXRT1062_FMURT6 diff --git a/boards/arm/mimxrt1064_evk/CMakeLists.txt b/boards/arm/mimxrt1064_evk/CMakeLists.txt deleted file mode 100644 index 630fac7d67d..00000000000 --- a/boards/arm/mimxrt1064_evk/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# -# Copyright 2018-2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if (CONFIG_DISPLAY) -message(WARNING " -CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board -") -endif() - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT DEFINED CONFIG_BOARD_MIMXRT1064_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1064-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - set(RT1064_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1064") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1064 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1064_BOARD_DIR}/xip/evkmimxrt1064_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1064_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1064 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1064_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1064_evk/Kconfig.board b/boards/arm/mimxrt1064_evk/Kconfig.board deleted file mode 100644 index 0ce09d06fd4..00000000000 --- a/boards/arm/mimxrt1064_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1064_EVK - bool "NXP MIMXRT1064-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1064DVL6A diff --git a/boards/arm/mimxrt1064_evk/Kconfig.defconfig b/boards/arm/mimxrt1064_evk/Kconfig.defconfig deleted file mode 100644 index e0604d39621..00000000000 --- a/boards/arm/mimxrt1064_evk/Kconfig.defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# MIMXRT1064-EVK board - -# Copyright 2018,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1064_EVK - -config BOARD - default "mimxrt1064_evk" - -choice CODE_LOCATION - default CODE_FLEXSPI2 -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -config INPUT - default y if LVGL - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - -if NETWORKING - -config NET_L2_ETHERNET - default y - -if ETH_MCUX - -config ETH_MCUX_PHY_RESET - default y - -endif # ETH_MCUX - -endif # NETWORKING - -if LVGL - -config LV_Z_VDB_SIZE - default 16 - -config LV_DPI_DEF - default 128 - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -endif # LVGL - -endif # BOARD_MIMXRT1064_EVK diff --git a/boards/arm/mimxrt1064_evk/doc/index.rst b/boards/arm/mimxrt1064_evk/doc/index.rst deleted file mode 100644 index 24abf5ca76f..00000000000 --- a/boards/arm/mimxrt1064_evk/doc/index.rst +++ /dev/null @@ -1,477 +0,0 @@ -.. _mimxrt1064_evk: - -NXP MIMXRT1064-EVK -################## - -Overview -******** - -The i.MX RT1064 adds to the industry's first crossover -processor series and expands the i.MX RT series to three scalable families. -The i.MX RT1064 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin -compatibility with i.MX RT1050. This series introduces additional features -ideal for real-time applications such as High-Speed GPIO, CAN FD, and -synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1064 runs on the -Arm® Cortex-M7® core up to 600 MHz. - -.. image:: mimxrt1064_evk.jpg - :align: center - :alt: MIMXRT1064-EVK - -Hardware -******** - -- MIMXRT1064DVL6A MCU (600 MHz, 1024 KB on-chip memory, 4096KB on-chip QSPI - flash) - -- Memory - - - 256 Mbit SDRAM - - 64 Mbit QSPI Flash - - 512 Mbit Hyper Flash - - TF socket for SD card - -- Display - - - LCD connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - - USB 2.0 host connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - - Left and right speaker out connectors - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - OpenSDA with DAPLink - -- Sensor - - - FXOS8700CQ 6-axis e-compass - - CMOS camera sensor interface - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1064 SoC and MIMXRT1064-EVK board, see -these references: - -- `i.MX RT1064 Website`_ -- `i.MX RT1064 Datasheet`_ -- `i.MX RT1064 Reference Manual`_ -- `MIMXRT1064-EVK Website`_ -- `MIMXRT1064-EVK Quick Reference Guide`_ -- `MIMXRT1064-EVK User Guide`_ -- `MIMXRT1064-EVK Schematics`_ -- `MIMXRT1064-EVK Debug Firmware`_ - -External Memory -=============== - -This platform has the following external memories: - -+--------------------+------------+-------------------------------------+ -| Device | Controller | Status | -+====================+============+=====================================+ -| MT48LC16M16A2 | SEMC | Enabled via device configuration | -| | | data block, which sets up SEMC at | -| | | boot time | -+--------------------+------------+-------------------------------------+ - -Supported Features -================== - -NXP considers the MIMXRT1064-EVK as the superset board for the i.MX RT10xx -family of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire RT10xx family. NXP prioritizes enabling -this board with new support for Zephyr features. The mimxrt1064_evk board -configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | display | -+-----------+------------+-------------------------------------+ -| VIDEO | on-chip | video, using CSI | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | QSPI flash | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SDHC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| ENET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| GPT | on-chip | gpt | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and I/Os -==================== - -The MIMXRT1064 SoC has four pairs of pinmux/gpio controllers. - -+---------------+-----------------+---------------------------+ -| Name | Function | Usage | -+===============+=================+===========================+ -| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_05 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | GPIO/ENET_RST | LED/Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_11 | GPIO | Touch Interrupt | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_12 | LPUART1_TX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_13 | LPUART1_RX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_06 | LPUART3_TX | UART Arduino | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_07 | LPUART3_RX | UART Arduino | -+---------------+-----------------+---------------------------+ -| WAKEUP | GPIO | SW0 | -+---------------+-----------------+---------------------------+ -| GPIO_B0_00 | LCD_CLK | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_01 | LCD_ENABLE | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_02 | LCD_HSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_03 | LCD_VSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_04 | LCD_DATA00 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_05 | LCD_DATA01 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_06 | LCD_DATA02 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_07 | LCD_DATA03 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_08 | LCD_DATA04 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_09 | LCD_DATA05 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_10 | LCD_DATA06 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_11 | LCD_DATA07 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_12 | LCD_DATA08 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_13 | LCD_DATA09 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_14 | LCD_DATA10 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_15 | LCD_DATA11 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_00 | LCD_DATA12 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_01 | LCD_DATA13 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_02 | LCD_DATA14 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_03 | LCD_DATA15 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_06 | ENET_RX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_09 | ENET_TX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_10 | ENET_REF_CLK | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_11 | ENET_RX_ER | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_12 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_14 | USDHC1_VSELECT | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_40 | ENET_MDC | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_41 | ENET_MDIO | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | ENET_RST | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | ENET_INT | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_05 | FLEXSPIA_DQS | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_06 | FLEXSPIA_SS0_B | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_07 | FLEXSPIA_SCLK | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_08 | FLEXSPIA_DATA00 | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_09 | FLEXSPIA_DATA01 | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_10 | FLEXSPIA_DATA02 | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_11 | FLEXSPIA_DATA03 | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_11 | ADC | ADC1 Channel 0 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_10 | ADC | ADC1 Channel 1 | -+---------------+-----------------+---------------------------+ - -.. note:: - In order to use the SPI peripheral on this board, resistors R278, R279, - R280 and R281 must be populated with zero ohm resistors - -System Clock -============ - -The MIMXRT1064 SoC is configured to use SysTick as the system clock source, -running at 600MHz. - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - -Serial Port -=========== - -The MIMXRT1064 SoC has eight UARTs. ``LPUART1`` is configured for the console -and the remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -.. note:: - When the device transitions into low power states, the debugger may be - unable to access the chip. Use caution when enabling ``CONFIG_PM``, and - if the debugger cannot flash the part, see :ref:`Troubleshooting RT1064` - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -.. _Using LinkServer: - - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `MIMXRT1064-EVK Debug Firmware` - -.. _Using J-Link RT1064: - -Using J-Link ---------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -There are two options: the onboard debug circuit can be updated with Segger -J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the -EVK. See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ for more -details. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. Check that -jumpers J45 and J46 are **on** (they are on by default when boards ship from -the factory) to connect UART signals to the OpenSDA microcontroller. - -Connect a USB cable from your PC to J41. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Using SWO ---------- -SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``. -Your SWO viewer should be configured with a CPU frequency of 132MHz, and -SWO frequency of 7500KHz. - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1064_evk - :goals: flash - -Open a serial terminal, reset the board (press the SW9 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1064_evk - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1064_evk - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1064_evk - - -.. _Troubleshooting RT1064: - -Troubleshooting -=============== - -If the debug probe fails to connect with the following error, it's possible -that the boot header in QSPI flash is invalid or corrupted. The boot header is -configured by :kconfig:option:`CONFIG_NXP_IMX_RT_BOOT_HEADER`. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the QSPI flash with the following -steps: - -#. Set the SW7 DIP switches to ON-OFF-ON-OFF to prevent booting from QSPI flash. - -#. Reset by pressing SW9 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application. - -#. Set the SW7 DIP switches to OFF-OFF-ON-OFF to boot from QSPI flash. - -#. Reset by pressing SW9 - -If the west flash or debug commands fail, and the command hangs while executing -runners.jlink, confirm the J-Link debug probe is configured, powered, and -connected to the EVK properly. See :ref:`Using J-Link RT1064` for more -details. - -.. _MIMXRT1064-EVK Website: - https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK - -.. _MIMXRT1064-EVK Quick Reference Guide: - https://www.nxp.com/webapp/Download?colCode=IMXRT1064QSG - -.. _MIMXRT1064-EVK User Guide: - https://www.nxp.com/docs/en/data-sheet/MIMXRT10601064EKBHUG.pdf - -.. _MIMXRT1064-EVK Debug Firmware: - https://www.nxp.com/docs/en/application-note/AN13206.pdf - -.. _MIMXRT1064-EVK Schematics: - https://www.nxp.com/webapp/Download?colCode=i.MXRT160EVKDS&Parent_nodeId=1537930933174731284155&Parent_pageType=product - -.. _i.MX RT1064 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1064-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1064 - -.. _i.MX RT1064 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT1064CEC.pdf - -.. _i.MX RT1064 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT1064RM - -.. _Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVK-or-MIMXRT1064-EVK/ta-p/1281149 diff --git a/boards/arm/mimxrt1160_evk/CMakeLists.txt b/boards/arm/mimxrt1160_evk/CMakeLists.txt deleted file mode 100644 index 62d5ed6a61c..00000000000 --- a/boards/arm/mimxrt1160_evk/CMakeLists.txt +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT (DEFINED CONFIG_BOARD_MIMXRT1160_EVK_CM7) - OR (DEFINED CONFIG_BOARD_MIMXRT1160_EVK_CM4)) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1160-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - set(RT1160_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1160") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1160 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1160_BOARD_DIR}/xip/evkmimxrt1160_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1160_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1160 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1160_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1160_evk/Kconfig.board b/boards/arm/mimxrt1160_evk/Kconfig.board deleted file mode 100644 index 2f7b3533bf7..00000000000 --- a/boards/arm/mimxrt1160_evk/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1160_EVK_CM7 - bool "NXP MIMXRT1160-EVK CM7" - depends on SOC_MIMXRT1166_CM7 - select SOC_PART_NUMBER_MIMXRT1166DVM6A - -config BOARD_MIMXRT1160_EVK_CM4 - bool "NXP MIMXRT1160-EVK CM4" - depends on SOC_MIMXRT1166_CM4 - select SOC_PART_NUMBER_MIMXRT1166DVM6A diff --git a/boards/arm/mimxrt1160_evk/Kconfig.defconfig b/boards/arm/mimxrt1160_evk/Kconfig.defconfig deleted file mode 100644 index 9f7f09e84c2..00000000000 --- a/boards/arm/mimxrt1160_evk/Kconfig.defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# MIMXRT1160-EVK board - -# Copyright 2021,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4 - -config BOARD - default "mimxrt1160_evk_cm7" if BOARD_MIMXRT1160_EVK_CM7 - default "mimxrt1160_evk_cm4" if BOARD_MIMXRT1160_EVK_CM4 - -choice CODE_LOCATION - default CODE_FLEXSPI if BOARD_MIMXRT1160_EVK_CM7 - default CODE_OCRAM if BOARD_MIMXRT1160_EVK_CM4 && SECOND_CORE_MCUX - default CODE_SRAM0 if BOARD_MIMXRT1160_EVK_CM4 -endchoice - -# Only use DCD when booting primary core (M7) -config DEVICE_CONFIGURATION_DATA - default y if CPU_CORTEX_M7 - -config NXP_IMX_EXTERNAL_SDRAM - default y if CPU_CORTEX_M7 - -if SECOND_CORE_MCUX && BOARD_MIMXRT1160_EVK_CM4 - -config BUILD_OUTPUT_INFO_HEADER - default y - -DT_CHOSEN_IMAGE_M4 = nxp,m4-partition - -# Adjust the offset of the output image if building for RT11xx SOC -config BUILD_OUTPUT_ADJUST_LMA - default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \ - $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \ - $(dt_node_reg_addr_hex,/soc/ocram@20200000)" - -endif - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 240000000 if BOARD_MIMXRT1160_EVK_CM4 && CORTEX_M_SYSTICK - default 600000000 if BOARD_MIMXRT1160_EVK_CM7 && CORTEX_M_SYSTICK - -if FLASH - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 -endchoice - -endif #FLASH - -if NETWORKING - -config NET_L2_ETHERNET - default y if CPU_CORTEX_M7 # No cache memory support is required for driver - -config ETH_MCUX_PHY_RESET - default y - -endif # NETWORKING - -endif # BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4 diff --git a/boards/arm/mimxrt1160_evk/doc/index.rst b/boards/arm/mimxrt1160_evk/doc/index.rst deleted file mode 100644 index 2449429a891..00000000000 --- a/boards/arm/mimxrt1160_evk/doc/index.rst +++ /dev/null @@ -1,366 +0,0 @@ -.. _mimxrt1160_evk: - -NXP MIMXRT1160-EVK -################## - -Overview -******** - -The dual core i.MX RT1160 runs on the Cortex-M7 core at 600 MHz and on the -Cortex-M4 at 240 MHz. The i.MX RT1160 MCU offers support over a wide -temperature range and is qualified for consumer, industrial and automotive -markets. - -.. image:: mimxrt1160_evk.jpg - :align: center - :alt: MIMXRT1160-EVK - -Hardware -******** - -- MIMXRT1166DVM6A MCU - - - 600MHz Cortex-M7 & 240Mhz Cortex-M4 - - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 - -- Memory - - - 512 Mbit SDRAM - - 128 Mbit QSPI Flash - - 512 Mbit Octal Flash - - TF socket for SD card - -- Display - - - MIPI LCD connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - - 10/100/1000 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - - USB 2.0 host connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - - Left and right speaker out connectors - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - OpenSDA with DAPLink - -- Sensor - - - MIPI camera sensor connector - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1160 SoC and MIMXRT1160-EVK board, see -these references: - -- `i.MX RT1160 Website`_ -- `i.MX RT1160 Datasheet`_ -- `i.MX RT1160 Reference Manual`_ -- `MIMXRT1160-EVK Website`_ -- `MIMXRT1160-EVK Board Hardware User's Guide`_ - -External Memory -=============== - -This platform has the following external memories: - -+--------------------+------------+-------------------------------------+ -| Device | Controller | Status | -+====================+============+=====================================+ -| W9825G6KH | SEMC | Enabled via device configuration | -| | | data block, which sets up SEMC at | -| | | boot time | -+--------------------+------------+-------------------------------------+ -| IS25WP128 | FLEXSPI | Enabled via flash configurationn | -| | | block, which sets up FLEXSPI at | -| | | boot time. | -+--------------------+------------+-------------------------------------+ - -Supported Features -================== - -The mimxrt1160_evk board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1170_evk` , which is the superset board in NXP's i.MX RT11xx family. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the mimxrt1170_evk board may have additional features -already supported, which can also be re-used on this mimxrt1160_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | flexcan | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| GPT | on-chip | gpt | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB Device | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| CAAM RNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig`` - -Other hardware features are not currently supported by the port. - - -Connections and I/Os -==================== - -The MIMXRT1160 SoC has six pairs of pinmux/gpio controllers. - -+---------------+-----------------+---------------------------+ -| Name | Function | Usage | -+===============+=================+===========================+ -| WAKEUP | GPIO | SW7 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_04 | GPIO | LED | -+---------------+-----------------+---------------------------+ -| GPIO_AD_24 | LPUART1_TX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_25 | LPUART1_RX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_LPSR_00 | CAN3_TX | flexcan | -+---------------+-----------------+---------------------------+ -| GPIO_LPSR_01 | CAN3_RX | flexcan | -+---------------+-----------------+---------------------------+ -| GPIO_AD_29 | SPI1_CS0 | spi | -+---------------+-----------------+---------------------------+ -| GPIO_AD_28 | SPI1_CLK | spi | -+---------------+-----------------+---------------------------+ -| GPIO_AD_30 | SPI1_SDO | spi | -+---------------+-----------------+---------------------------+ -| GPIO_AD_31 | SPI1_SDI | spi | -+---------------+-----------------+---------------------------+ -| GPIO_AD_08 | LPI2C1_SCL | i2c | -+---------------+-----------------+---------------------------+ -| GPIO_AD_09 | LPI2C1_SDA | i2c | -+---------------+-----------------+---------------------------+ -| GPIO_LPSR_05 | LPI2C5_SCL | i2c | -+---------------+-----------------+---------------------------+ -| GPIO_LPSR_04 | LPI2C5_SDA | i2c | -+---------------+-----------------+---------------------------+ -| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm | -+---------------+-----------------+---------------------------+ - - -Dual Core samples -***************** - -+-----------+------------------+----------------------------+ -| Core | Boot Address | Comment | -+===========+==================+============================+ -| Cortex M7 | 0x30000000[630K] | primary core | -+-----------+------------------+----------------------------+ -| Cortex M4 | 0x20020000[96k] | boots from OCRAM | -+-----------+------------------+----------------------------+ - -+----------+------------------+-----------------------+ -| Memory | Address[Size] | Comment | -+==========+==================+=======================+ -| flexspi1 | 0x30000000[16M] | Cortex M7 flash | -+----------+------------------+-----------------------+ -| sdram0 | 0x80030000[64M] | Cortex M7 ram | -+----------+------------------+-----------------------+ -| ocram | 0x20020000[512K] | Cortex M4 "flash" | -+----------+------------------+-----------------------+ -| sram1 | 0x20000000[128K] | Cortex M4 ram | -+----------+------------------+-----------------------+ -| ocram2 | 0x200C0000[512K] | Mailbox/shared memory | -+----------+------------------+-----------------------+ - -Only the first 16K of ocram2 has the correct MPU region attributes set to be -used as shared memory - -System Clock -============ - -The MIMXRT1160 SoC is configured to use SysTick as the system clock source, -running at 600MHz. When targeting the M4 core, SysTick will also be used, -running at 240MHz - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - -Serial Port -=========== - -The MIMXRT1160 SoC has 12 UARTs. One is configured for the console and the -remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Building a Dual-Core Image -========================== -Dual core samples load the M4 core image from flash into the shared ``ocram`` -region. The M7 core then sets the M4 boot address to this region. The only -sample currently enabled for dual core builds is the ``openamp`` sample. -To flash a dual core sample, the M4 image must be flashed first, so that it is -written to flash. Then, the M7 image must be flashed. The openamp sysbuild -sample will do this automatically by setting the image order. - -The secondary core can be debugged normally in single core builds -(where the target is ``mimxrt1160_evk_cm4``). For dual core builds, the -secondary core should be placed into a loop, then a debugger can be attached -(see `AN13264`_, section 4.2.3 for more information) - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -.. _Using J-Link RT1160: - -Using J-Link ---------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -There are two options: the onboard debug circuit can be updated with Segger -J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the -EVK. See `Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK`_ for more details. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. Check that -jumpers J5 and J8 are **on** (they are on by default when boards ship from -the factory) to connect UART signals to the OpenSDA microcontroller. - -Connect a USB cable from your PC to J11. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -Before power on the board, make sure SW1 is set to 0001b - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1160_evk_cm7 - :goals: flash - -Power off the board, and change SW1 to 0010b. Then power on the board and -open a serial terminal, reset the board (press the SW4 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.6.0-xxxx-xxxxxxxxxxxxx ***** - Hello World! mimxrt1160_evk_cm7 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1160_evk_cm7 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.4.0-xxxx-xxxxxxxxxxxxx ***** - Hello World! mimxrt1160_evk_cm7 - -.. _MIMXRT1160-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1160-evaluation-kit:MIMXRT1160-EVK - -.. _MIMXRT1160-EVK Board Hardware User's Guide: - https://www.nxp.com/webapp/Download?colCode=UM11617 - -.. _i.MX RT1160 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1160-crossover-mcu-family-high-performance-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1160 - -.. _i.MX RT1160 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT1160CEC.pdf - -.. _i.MX RT1160 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT1160RM - -.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760 - -.. _AN13264: - https://www.nxp.com/docs/en/application-note/AN13264.pdf - -Experimental ENET Driver -======================== - -Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new -driver with binding `nxp,enet`, which is experimental and undergoing development, but will have -enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. - -To build for this EVK with the new driver, include the experimental overlay to west build with -the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.yaml b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.yaml deleted file mode 100644 index 8d0d041c14f..00000000000 --- a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1160_evk_cm4 -name: NXP MIMXRT1160-EVK CM4 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 128 -flash: 128 -supported: - - dma - - i2c - - gpio - - pwm - - uart -vendor: nxp diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4_defconfig b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4_defconfig deleted file mode 100644 index ac3f4bf5b93..00000000000 --- a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1166_CM4=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.yaml b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.yaml deleted file mode 100644 index 48e4f372355..00000000000 --- a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.yaml +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1160_evk_cm7 -name: NXP MIMXRT1160-EVK CM7 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 256 -flash: 16384 -supported: - - counter - - can - - dma - - gpio - - hwinfo - - i2c - - netif:eth - - pwm - - spi - - usb_device - - watchdog -vendor: nxp diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig deleted file mode 100644 index 7cdde24c5a0..00000000000 --- a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1166_CM7=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1170_evk/CMakeLists.txt b/boards/arm/mimxrt1170_evk/CMakeLists.txt deleted file mode 100644 index 48cec3f9786..00000000000 --- a/boards/arm/mimxrt1170_evk/CMakeLists.txt +++ /dev/null @@ -1,53 +0,0 @@ -# -# Copyright 2022-2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT ((DEFINED CONFIG_BOARD_MIMXRT1170_EVK_CM7) - OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVK_CM4) - OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVKB_CM7) - OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVKB_CM4))) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1170-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - if ((DEFINED CONFIG_BOARD_MIMXRT1170_EVK_CM7) - OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVK_CM4)) - set(RT1170_BOARD_NAME "evkmimxrt1170") - elseif((DEFINED CONFIG_BOARD_MIMXRT1170_EVKB_CM7) - OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVKB_CM4)) - set(RT1170_BOARD_NAME "evkbmimxrt1170") - endif() - set(RT1170_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${RT1170_BOARD_NAME}") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1170 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1170_BOARD_DIR}/xip/${RT1170_BOARD_NAME}_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1170_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1170 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1170_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1170_evk/Kconfig.board b/boards/arm/mimxrt1170_evk/Kconfig.board deleted file mode 100644 index b3b5a6e78f8..00000000000 --- a/boards/arm/mimxrt1170_evk/Kconfig.board +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright 2021,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1170_EVK_CM7 - bool "NXP MIMXRT1170-EVK CM7" - depends on SOC_MIMXRT1176_CM7 - select SOC_PART_NUMBER_MIMXRT1176DVMAA - -config BOARD_MIMXRT1170_EVK_CM4 - bool "NXP MIMXRT1170-EVK CM4" - depends on SOC_MIMXRT1176_CM4 - select SOC_PART_NUMBER_MIMXRT1176DVMAA - -config BOARD_MIMXRT1170_EVKB_CM7 - bool "NXP MIMXRT1170-EVKB CM7" - depends on SOC_MIMXRT1176_CM7 - select SOC_PART_NUMBER_MIMXRT1176DVMAA - -config BOARD_MIMXRT1170_EVKB_CM4 - bool "NXP MIMXRT1170-EVKB CM4" - depends on SOC_MIMXRT1176_CM4 - select SOC_PART_NUMBER_MIMXRT1176DVMAA diff --git a/boards/arm/mimxrt1170_evk/Kconfig.defconfig b/boards/arm/mimxrt1170_evk/Kconfig.defconfig deleted file mode 100644 index 867999f701c..00000000000 --- a/boards/arm/mimxrt1170_evk/Kconfig.defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# MIMXRT1170-EVK board - -# Copyright 2021,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1170_EVK_CM7 || BOARD_MIMXRT1170_EVK_CM4 || \ - BOARD_MIMXRT1170_EVKB_CM7 || BOARD_MIMXRT1170_EVKB_CM4 - -config BOARD - default "mimxrt1170_evk_cm7" if BOARD_MIMXRT1170_EVK_CM7 - default "mimxrt1170_evk_cm4" if BOARD_MIMXRT1170_EVK_CM4 - default "mimxrt1170_evkb_cm7" if BOARD_MIMXRT1170_EVKB_CM7 - default "mimxrt1170_evkb_cm4" if BOARD_MIMXRT1170_EVKB_CM4 - -choice CODE_LOCATION - default CODE_FLEXSPI if CPU_CORTEX_M7 - default CODE_OCRAM if CPU_CORTEX_M4 && SECOND_CORE_MCUX - default CODE_SRAM0 if CPU_CORTEX_M4 -endchoice - -# Only use DCD when booting primary core (M7) -config DEVICE_CONFIGURATION_DATA - default y if CPU_CORTEX_M7 - -config NXP_IMX_EXTERNAL_SDRAM - default y if CPU_CORTEX_M7 - -if SECOND_CORE_MCUX && CPU_CORTEX_M4 - -config BUILD_OUTPUT_INFO_HEADER - default y - -DT_CHOSEN_IMAGE_M4 = nxp,m4-partition - -# Adjust the offset of the output image if building for RT11xx SOC -config BUILD_OUTPUT_ADJUST_LMA - default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \ - $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \ - $(dt_node_reg_addr_hex,/soc/ocram@20200000)" - -endif - -if DISK_DRIVERS - -config IMX_USDHC_DAT3_PWR_TOGGLE - default y - -endif # DISK_DRIVERS - -if FLASH - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 -endchoice - -endif #FLASH - -if NETWORKING - -config NET_L2_ETHERNET - default y if CPU_CORTEX_M7 # No cache memory support is required for driver - -config ETH_MCUX_PHY_RESET - default y - -endif # NETWORKING - -endif diff --git a/boards/arm/mimxrt1170_evk/board.cmake b/boards/arm/mimxrt1170_evk/board.cmake deleted file mode 100644 index d543dce8821..00000000000 --- a/boards/arm/mimxrt1170_evk/board.cmake +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_SOC_MIMXRT1176_CM7 OR CONFIG_SECOND_CORE_MCUX) - board_runner_args(pyocd "--target=mimxrt1170_cm7") - board_runner_args(jlink "--device=MIMXRT1176xxxA_M7" "--reset-after-load") - - if(CONFIG_BOARD_MIMXRT1170_EVK_CM7) - board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") - elseif(CONFIG_BOARD_MIMXRT1170_EVKB_CM7) - board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVKB") - endif() - - board_runner_args(linkserver "--core=cm7") -elseif(CONFIG_SOC_MIMXRT1176_CM4) - board_runner_args(pyocd "--target=mimxrt1170_cm4") - # Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core) - board_runner_args(jlink "--device=MIMXRT1176xxxA_M4") - if(CONFIG_BOARD_MIMXRT1170_EVK_CM4) - board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") - elseif(CONFIG_BOARD_MIMXRT1170_EVKB_CM4) - board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVKB") - endif() - board_runner_args(linkserver "--core=cm4") -endif() - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/arm/mimxrt1170_evk/doc/index.rst b/boards/arm/mimxrt1170_evk/doc/index.rst deleted file mode 100644 index faff1975ca8..00000000000 --- a/boards/arm/mimxrt1170_evk/doc/index.rst +++ /dev/null @@ -1,454 +0,0 @@ -.. _mimxrt1170_evk: - -NXP MIMXRT1170-EVK/EVKB -####################### - -Overview -******** - -The dual core i.MX RT1170 runs on the Cortex-M7 core at 1 GHz and on the Cortex-M4 -at 400 MHz. The i.MX RT1170 MCU offers support over a wide temperature range -and is qualified for consumer, industrial and automotive markets. Zephyr -supports the initial revision of this EVK, as well as rev EVKB. - -.. image:: mimxrt1170_evk.jpg - :align: center - :alt: MIMXRT1170-EVK - -Hardware -******** - -- MIMXRT1176DVMAA MCU - - - 1GHz Cortex-M7 & 400Mhz Cortex-M4 - - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 - -- Memory - - - 512 Mbit SDRAM - - 128 Mbit QSPI Flash - - 512 Mbit Octal Flash - - 2 Gbit raw NAND flash - - 64 Mbit LPSPI flash - - TF socket for SD card - -- Display - - - MIPI LCD connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - - 10/100/1000 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - - USB 2.0 host connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - - Left and right speaker out connectors - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - on-board debugger - -- Sensor - - - FXOS8700CQ 6-axis e-compass - - MIPI camera sensor connector - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1170 SoC and MIMXRT1170-EVK board, see -these references: - -- `i.MX RT1170 Website`_ -- `i.MX RT1170 Datasheet`_ -- `i.MX RT1170 Reference Manual`_ -- `MIMXRT1170-EVK Website`_ -- `MIMXRT1170-EVK Board Hardware User's Guide`_ - -External Memory -=============== - -This platform has the following external memories: - -+--------------------+------------+-------------------------------------+ -| Device | Controller | Status | -+====================+============+=====================================+ -| W9825G6KH | SEMC | Enabled via device configuration | -| SDRAM | | data (DCD) block, which sets up | -| | | the SEMC at boot time | -+--------------------+------------+-------------------------------------+ -| IS25WP128 | FLEXSPI | Enabled via flash configuration | -| QSPI flash | | block (FCB), which sets up the | -| (RT1170 EVK) | | FLEXSPI at boot time. | -+--------------------+------------+-------------------------------------+ -| W25Q512NWEIQ | FLEXSPI | Enabled via flash configuration | -| QSPI flash | | block (FCB), which sets up the | -| (RT1170 EVKB) | | FLEXSPI at boot time. Supported for | -| | | XIP only. | -+--------------------+------------+-------------------------------------+ - -Supported Features -================== - -NXP considers the MIMXRT1170-EVK as the superset board for the i.MX RT11xx -family of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire RT11xx family. NXP prioritizes enabling -this board with new support for Zephyr features. Note that this table -covers two boards: the RT1170 EVK (`mimxrt1170_evk_cm7/cm4`), and -RT1170 EVKB (`mimxrt1170_evkb_cm7/cm4`) - -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| Interface | Controller | Driver/Component | RT1170 EVK | RT1170 EVKB | -+===========+============+=====================================+=================+=================+ -| NVIC | on-chip | nested vector interrupt controller | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| SYSTICK | on-chip | systick | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| GPIO | on-chip | gpio | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| COUNTER | on-chip | gpt | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| TIMER | on-chip | gpt | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| CAN | on-chip | flexcan | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| SPI | on-chip | spi | Supported (M7) | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| I2C | on-chip | i2c | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| PWM | on-chip | pwm | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| ADC | on-chip | adc | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| UART | on-chip | serial port-polling; | Supported | Supported | -| | | serial port-interrupt; | | | -| | | serial port-async | | | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| DMA | on-chip | dma | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| WATCHDOG | on-chip | watchdog | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| ENET | on-chip | ethernet - 10/100M (ENET_QOS or | Supported (M7) | No support | -| ENET1G | | GigE not supported yet) | | | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| SAI | on-chip | i2s | Supported | No support | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| USB | on-chip | USB Device | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| HWINFO | on-chip | Unique device serial number | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| DISPLAY | on-chip | eLCDIF; MIPI-DSI. Tested with | Supported (M7) | Supported (M7) | -| | | :ref:`rk055hdmipi4m`, | | | -| | | :ref:`rk055hdmipi4ma0`, | | | -| | | and :ref:`g1120b0mipi` shields | | | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| ACMP | on-chip | analog comparator | Supported | No support | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| CAAM RNG | on-chip | entropy | Supported (M7) | No support | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| FLEXSPI | on-chip | flash programming | Supported (M7) | No support | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| SDHC | on-chip | SD host controller | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ - -The default configuration can be found in the defconfig files: -``boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig`` -``boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7_defconfig`` - -Connections and I/Os -==================== - -The MIMXRT1170 SoC has six pairs of pinmux/gpio controllers. - -+---------------------------+----------------+------------------+ -| Name | Function | Usage | -+---------------------------+----------------+------------------+ -| WAKEUP | GPIO | SW7 | -+---------------------------+----------------+------------------+ -| GPIO_AD_04 | GPIO | LED | -+---------------------------+----------------+------------------+ -| GPIO_AD_24 | LPUART1_TX | UART Console | -+---------------------------+----------------+------------------+ -| GPIO_AD_25 | LPUART1_RX | UART Console | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_00 | CAN3_TX | flexcan | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_01 | CAN3_RX | flexcan | -+---------------------------+----------------+------------------+ -| GPIO_AD_29 | SPI1_CS0 | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_28 | SPI1_CLK | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_30 | SPI1_SDO | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_31 | SPI1_SDI | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_08 | LPI2C1_SCL | i2c | -+---------------------------+----------------+------------------+ -| GPIO_AD_09 | LPI2C1_SDA | i2c | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_05 | LPI2C5_SCL | i2c | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_04 | LPI2C5_SDA | i2c | -+---------------------------+----------------+------------------+ -| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm | -+---------------------------+----------------+------------------+ -| GPIO_AD_32 | ENET_MDC | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_AD_33 | ENET_MDIO | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_02 | ENET_TX_DATA00 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_03 | ENET_TX_DATA01 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_04 | ENET_TX_EN | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_05 | ENET_REF_CLK | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_06 | ENET_RX_DATA00 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_07 | ENET_RX_DATA01 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_08 | ENET_RX_EN | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_09 | ENET_RX_ER | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_AD_17_SAI1_MCLK | SAI_MCLK | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_21_SAI1_TX_DATA00 | SAI1_TX_DATA | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_22_SAI1_TX_BCLK | SAI1_TX_BCLK | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_23_SAI1_TX_SYNC | SAI1_TX_SYNC | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_17_SAI1_MCLK | SAI1_MCLK | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_20_SAI1_RX_DATA00 | SAI1_RX_DATA00 | SAI | -+---------------------------+----------------+------------------+ - -Dual Core samples -***************** - -+-----------+------------------+----------------------------+ -| Core | Boot Address | Comment | -+===========+==================+============================+ -| Cortex M7 | 0x30000000[630K] | primary core | -+-----------+------------------+----------------------------+ -| Cortex M4 | 0x20020000[96k] | boots from OCRAM | -+-----------+------------------+----------------------------+ - -+----------+------------------+-----------------------+ -| Memory | Address[Size] | Comment | -+==========+==================+=======================+ -| flexspi1 | 0x30000000[16M] | Cortex M7 flash | -+----------+------------------+-----------------------+ -| sdram0 | 0x80030000[64M] | Cortex M7 ram | -+----------+------------------+-----------------------+ -| ocram | 0x20020000[512K] | Cortex M4 "flash" | -+----------+------------------+-----------------------+ -| sram1 | 0x20000000[128K] | Cortex M4 ram | -+----------+------------------+-----------------------+ -| ocram2 | 0x200C0000[512K] | Mailbox/shared memory | -+----------+------------------+-----------------------+ - -Only the first 16K of ocram2 has the correct MPU region attributes set to be -used as shared memory - -System Clock -============ - -The MIMXRT1170 SoC is configured to use SysTick as the system clock source, -running at 996MHz. When targeting the M4 core, SysTick will also be used, -running at 400MHz - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - -Serial Port -=========== - -The MIMXRT1170 SoC has 12 UARTs. One is configured for the console and the -remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Building a Dual-Core Image -========================== -Dual core samples load the M4 core image from flash into the shared ``ocram`` -region. The M7 core then sets the M4 boot address to this region. The only -sample currently enabled for dual core builds is the ``openamp`` sample. -To flash a dual core sample, the M4 image must be flashed first, so that it is -written to flash. Then, the M7 image must be flashed. The openamp sysbuild -sample will do this automatically by setting the image order. - -The secondary core can be debugged normally in single core builds -(where the target is ``mimxrt1170_evk_cm4``). For dual core builds, the -secondary core should be placed into a loop, then a debugger can be attached -(see `AN13264`_, section 4.2.3 for more information) - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. The on-board -debugger listed below works with the LinkServer runner by default, or can be -reprogrammed with JLink firmware. -- MIMXRT1170-EVKB: :ref:`mcu-link-cmsis-onboard-debug-probe` -- MIMXRT1170-EVK: :ref:`opensda-daplink-onboard-debug-probe` - -Using J-Link ------------- - -JLink is the default runner for this board. Install the -:ref:`jlink-debug-host-tools` and make sure they are in your search path. - -There are two options: the onboard debug circuit can be updated with Segger -J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the -EVK. See `Using J-Link with MIMXRT1170-EVKB`_ or -`Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK`_ for more details. - -Using LinkServer ----------------- - -Known limitations with LinkServer and these boards include: -- ``west debug`` does not yet work correctly, and the application image is not -properly written to the memory. `NXP MCUXpresso for Visual Studio Code`_ -can be used to debug Zephyr applications with LinkServer. -- ``west flash`` will not write images to non-flash locations. The flash -command only works when all data in the image is written to flash memory -regions. - -Install the :ref:`linkserver-debug-host-tools` and make sure they are in your -search path. LinkServer works with the default CMSIS-DAP firmware included in -the on-board debugger. - -Use the ``-r linkserver`` option with West to use the LinkServer runner. - -.. code-block:: console - - west flash -r linkserver - -Alternatively, pyOCD can be used to flash and debug the board by using the -``-r pyocd`` option with West. pyOCD is installed when you complete the -:ref:`gs_python_deps` step in the Getting Started Guide. The runners supported -by NXP are LinkServer and JLink. pyOCD is another potential option, but NXP -does not test or support the pyOCD runner. - -Configuring a Console -===================== - -We will use the on-board debugger -microcontroller as a usb-to-serial adapter for the serial console. The following -jumper settings are default on these boards, and are required to connect the -UART signals to the USB bridge circuit: -- MIMXRT1170-EVKB: JP2 open (default) -- MIMXRT1170-EVK: J31 and J32 shorted (default) - -Connect a USB cable from your PC to the on-board debugger USB port: -- MIMXRT1170-EVKB: J86 -- MIMXRT1170-EVK: J11 - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -Before powering the board, make sure SW1 is set to 0001b - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1170_evk_cm7 - :goals: flash - -Power off the board, and change SW1 to 0010b. Then power on the board and -open a serial terminal, reset the board (press the SW4 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx ***** - Hello World! mimxrt1170_evk_cm7 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1170_evk_cm7 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx ***** - Hello World! mimxrt1170_evk_cm7 - -.. _MIMXRT1170-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVK - -.. _MIMXRT1170-EVK Board Hardware User's Guide: - https://www.nxp.com/webapp/Download?colCode=MIMXRT1170EVKHUG - -.. _i.MX RT1170 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1170-crossover-mcu-family-first-ghz-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1170 - -.. _i.MX RT1170 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT1170CEC.pdf - -.. _i.MX RT1170 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT1170RM - -.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760 - -.. _Using J-Link with MIMXRT1170-EVKB: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1170-EVKB/ta-p/1715138 - -.. _AN13264: - https://www.nxp.com/docs/en/application-note/AN13264.pdf - -.. _NXP MCUXpresso for Visual Studio Code: - https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-for-visual-studio-code:MCUXPRESSO-VSC - -Experimental ENET Driver -======================== - -Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new -driver with binding `nxp,enet`, which is experimental and undergoing development, but will have -enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. - -To build for this EVK with the new driver, include the experimental overlay to west build with -the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.yaml b/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.yaml deleted file mode 100644 index 69232196b62..00000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.yaml +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1170_evk_cm4 -name: NXP MIMXRT1170-EVK CM4 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 128 -flash: 128 -supported: - - dma - - gpio - - i2c - - pwm -vendor: nxp diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4_defconfig b/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4_defconfig deleted file mode 100644 index dacbbf3e1d2..00000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright 2021,2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_BOARD_MIMXRT1170_EVK_CM4=y -CONFIG_SOC_MIMXRT1176_CM4=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.yaml b/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.yaml deleted file mode 100644 index ba3ae1b201b..00000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.yaml +++ /dev/null @@ -1,31 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1170_evk_cm7 -name: NXP MIMXRT1170-EVK CM7 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 256 -flash: 16384 -supported: - - adc - - counter - - can - - dma - - gpio - - hwinfo - - i2c - - mipi_dsi - - netif:eth - - pwm - - spi - - usb_device - - watchdog -vendor: nxp diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig b/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig deleted file mode 100644 index db4c2d5c5a8..00000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2021,2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_BOARD_MIMXRT1170_EVK_CM7=y -CONFIG_SOC_MIMXRT1176_CM7=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.dts b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.dts deleted file mode 100644 index 79725d1ac35..00000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.dts +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "mimxrt1170_evk_cm4.dts" - -/ { - chosen { - /delete-property/ zephyr,flash-controller; - /delete-property/ zephyr,code-partition; - }; - - aliases { - /delete-property/ magn0; - /delete-property/ accel0; - }; -}; - -&flexspi { - /* RT1170 EVKB uses a different QSPI flash chip */ - /delete-node/ is25wp128@0; - status = "okay"; - reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; - w25q512nw:w25q512nw@0 { - /* IS25WP128 flash chip not currently enabled */ - compatible = "nxp,imx-flexspi-nor"; - size = ; - reg = <0>; - spi-max-frequency = <133000000>; - status = "okay"; - jedec-id = [ef 60 20]; - erase-block-size = <4096>; - write-block-size = <1>; - - /* - * Partitions are present to support dual core operation. - * as flash write is not supported, MCUBoot is not enabled. - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 0x301000>; - }; - slot1_partition: partition@321000 { - label = "image-1"; - reg = <0x00321000 0x300000>; - }; - storage_partition: partition@621000 { - label = "storage"; - reg = <0x00621000 DT_SIZE_K(1984)>; - }; - }; - }; -}; - -&lpspi1 { - dmas = <&edma_lpsr0 0 36>, <&edma_lpsr0 1 37>; - dma-names = "rx", "tx"; - status = "okay"; -}; - -&lpi2c5 { - /* FXOS accelerometer is not present in this board */ - /delete-node/ fxos8700@1f; -}; - -/* Disable ethernet, as PHY is not supported */ -&enet { - status = "disabled"; -}; diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.yaml b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.yaml deleted file mode 100644 index 77a684f23ed..00000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1170_evkb_cm4 -name: NXP MIMXRT1170-EVKB CM4 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 128 -flash: 128 -supported: - - dma - - gpio - - i2c - - spi - - pwm -vendor: nxp diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4_defconfig b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4_defconfig deleted file mode 100644 index b1dd310aa4b..00000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_BOARD_MIMXRT1170_EVKB_CM4=y -CONFIG_SOC_MIMXRT1176_CM4=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.dts b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.dts deleted file mode 100644 index feceb9eaa30..00000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "mimxrt1170_evk_cm7.dts" - -/ { - chosen { - zephyr,flash = &w25q512nw; - /delete-property/ zephyr,flash-controller; - /delete-property/ zephyr,code-partition; - }; - - aliases { - /delete-property/ magn0; - /delete-property/ accel0; - }; -}; - -&flexspi { - /* RT1170 EVKB uses a different QSPI flash chip */ - /delete-node/ is25wp128@0; - status = "okay"; - reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; - w25q512nw:w25q512nw@0 { - /* IS25WP128 flash chip not currently enabled */ - compatible = "nxp,imx-flexspi-nor"; - size = ; - reg = <0>; - spi-max-frequency = <133000000>; - status = "okay"; - jedec-id = [ef 60 20]; - erase-block-size = <4096>; - write-block-size = <1>; - - /* - * Partitions are present to support dual core operation. - * as flash write is not supported, MCUBoot is not enabled. - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 0x301000>; - }; - slot1_partition: partition@321000 { - label = "image-1"; - reg = <0x00321000 0x300000>; - }; - storage_partition: partition@621000 { - label = "storage"; - reg = <0x00621000 DT_SIZE_K(1984)>; - }; - }; - }; -}; - -&lpi2c5 { - /* FXOS accelerometer is not present in this board */ - /delete-node/ fxos8700@1f; -}; - -/* Disable ethernet, as PHY is not supported */ -&enet { - status = "disabled"; -}; diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.yaml b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.yaml deleted file mode 100644 index 03376fd15c3..00000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.yaml +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1170_evkb_cm7 -name: NXP MIMXRT1170-EVKB CM7 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 65536 -flash: 65536 -supported: - - adc - - counter - - can - - dma - - gpio - - hwinfo - - i2c - - mipi_dsi - - spi - - usb_device - - watchdog -vendor: nxp diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7_defconfig b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7_defconfig deleted file mode 100644 index a59d2e39e47..00000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_BOARD_MIMXRT1170_EVKB_CM7=y -CONFIG_SOC_MIMXRT1176_CM7=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt595_evk/CMakeLists.txt b/boards/arm/mimxrt595_evk/CMakeLists.txt deleted file mode 100644 index 002c6976545..00000000000 --- a/boards/arm/mimxrt595_evk/CMakeLists.txt +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2022-2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_library() -zephyr_library_sources(board.c) -zephyr_library_include_directories(.) - -if(CONFIG_NXP_IMX_RT5XX_BOOT_HEADER) - if(NOT DEFINED CONFIG_BOARD_MIMXRT595_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT595-EVK, but targeting a custom board. You may need to " - "update your flash configuration block data") - endif() - # Include flash configuration block for R595 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN13304 for more information. - zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT595_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt595") - zephyr_library_sources(${RT595_BOARD_DIR}/flash_config/flash_config.c) - zephyr_library_include_directories(${RT595_BOARD_DIR}/flash_config) -endif() - -# Add custom linker section to relocate framebuffers to PSRAM -zephyr_linker_sources_ifdef(CONFIG_LV_Z_VBD_CUSTOM_SECTION - SECTIONS dc_ram.ld) diff --git a/boards/arm/mimxrt595_evk/Kconfig b/boards/arm/mimxrt595_evk/Kconfig deleted file mode 100644 index dcd15490773..00000000000 --- a/boards/arm/mimxrt595_evk/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2022, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INIT_PRIORITY - int "Board initialization priority" - default 45 - help - Board initialization priority. diff --git a/boards/arm/mimxrt595_evk/Kconfig.board b/boards/arm/mimxrt595_evk/Kconfig.board deleted file mode 100644 index 3716c5ec334..00000000000 --- a/boards/arm/mimxrt595_evk/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT595_EVK - bool "NXP MIMXRT595-EVK" - depends on SOC_SERIES_IMX_RT5XX - select CODE_DATA_RELOCATION_SRAM - select SOC_PART_NUMBER_MIMXRT595SFFOC - select NXP_IMX_RT5XX_BOOT_HEADER if !BOOTLOADER_MCUBOOT diff --git a/boards/arm/mimxrt595_evk/Kconfig.defconfig b/boards/arm/mimxrt595_evk/Kconfig.defconfig deleted file mode 100644 index 96779115e14..00000000000 --- a/boards/arm/mimxrt595_evk/Kconfig.defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# MIMXRT595-EVK board - -# Copyright 2022-2023, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT595_EVK - -config BOARD - default "mimxrt595_evk_cm33" - -config FLASH_MCUX_FLEXSPI_MX25UM51345G - default y if FLASH - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM -endchoice - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -if DMA_MCUX_LPC - -# Memory from the heap pool is used to allocate DMA descriptors for -# channels that use multiple blocks for a DMA transfer. -# Adjust HEAP_MEM_POOL_MIN_SIZE in case you need more memory. -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 - -endif # DMA_MCUX_LPC - -# Turn on Device Level Power Management as we wish -# to reconfigure the FlexSPI pins for power savings -# when transitioning the SoC to Deep Low Power modes. -config PM_DEVICE - default y if PM - -config REGULATOR - default y if PM || POWEROFF - -endif # BOARD_MIMXRT595_EVK diff --git a/boards/arm/mimxrt595_evk/doc/index.rst b/boards/arm/mimxrt595_evk/doc/index.rst deleted file mode 100644 index 8bdbd864a4e..00000000000 --- a/boards/arm/mimxrt595_evk/doc/index.rst +++ /dev/null @@ -1,334 +0,0 @@ -.. _mimxrt595_evk: - -NXP MIMXRT595-EVK -################## - -Overview -******** - -i.MX RT500 crossover MCUs are part of the edge computing family and are optimized -for low-power HMI applications by combining a graphics engine and a streamlined -Cadence Tensilica Fusion F1 DSP core with a next-generation Arm Cortex-M33 -core. These devices are designed to unlock the potential of display-based applications -with a secure, power-optimized embedded processor. - -i.MX RT500 MCUs provides up to 5MB of on-chip SRAM and several high-bandwidth interfaces -to access off-chip flash, including an Octal/Quad SPI interface with an on-the-fly -decryption engine. - -.. image:: mimxrt595_evk.jpg - :align: center - :alt: MIMXRT595-EVK - -Hardware -******** - -- MIMXRT595SFFOC Cortex-M33 (275 MHz) core processor with Cadence Tensilica Fusion F1 DSP -- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug only) -- USB2.0 high-speed host and device with micro USB connector and external crystal -- Octal/Quad/pSRAM external memories via FlexSPI -- 5 MB system SRAM -- Full size SD card slot (SDIO) -- On-board eMMC chip -- On-board 5 V inputs NXP PCA9420UK PMIC providing 1.2 V, 1.8 V, 3.3 V -- User LEDs -- Reset and User buttons -- MIPI-DSI connector -- Single row headers for ARDUINO signals and MikroBus connector -- FlexIO connector for MikroElektronica TFT Proto 5 inch capacitive touch display -- One motion sensor combo accelero-/magneto-meter NXP FXOS8700CQ -- Stereo audio codec with line-In/ line-Out/ and Microphone -- Pmod/host expansion connector -- NXP TFA9896 audio digital amplifier -- Support for up to eight off-board digital microphones via 12-pin header -- Two on-board digital microphones - -For more information about the MIMXRT595 SoC and MIMXRT595-EVK board, see -these references: - -- `i.MX RT595 Website`_ -- `i.MX RT595 Datasheet`_ -- `i.MX RT595 Reference Manual`_ -- `MIMXRT595-EVK Website`_ -- `MIMXRT595-EVK User Guide`_ -- `MIMXRT595-EVK Schematics`_ -- `MIMXRT595-EVK Debug Firmware`_ - -Supported Features -================== - -NXP considers the MIMXRT595-EVK as a superset board for the i.MX RT5xx -family of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire RT5xx family. NXP prioritizes enabling -this board with new support for Zephyr features. The mimxrt595_evk board -configuration supports the hardware features below. Another very similar -board is the :ref:`mimxrt685_evk`, and that board may have additional features -already supported, which can also be re-used on this mimxrt595_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| OS_TIMER | on-chip | os timer | -+-----------+------------+-------------------------------------+ -| IOCON | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CTIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | OctalSPI Flash | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PM | on-chip | power management; uses SoC sleep, | -| | | deep sleep and deep-powerdown modes | -+-----------+------------+-------------------------------------+ -| SDHC | on-chip | disk access (works with eMMC & SD) | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | LCDIF; MIPI-DSI. Tested with | -| | | :ref:`rk055hdmipi4m`, | -| | | :ref:`rk055hdmipi4ma0`, and | -| | | :ref:`g1120b0mipi` display shields | -+-----------+------------+-------------------------------------+ -| DMIC | on-chip | dmic | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/mimxrt595_evk/mimxrt595_evk_cm33_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The MIMXRT595 SoC has IOCON registers, which can be used to configure the -functionality of a pin. - -+---------+-----------------+----------------------------+ -| Name | Function | Usage | -+=========+=================+============================+ -| PIO0_2 | USART0 | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_1 | USART0 | USART TX | -+---------+-----------------+----------------------------+ -| PIO0_14 | GPIO | GREEN LED | -+---------+-----------------+----------------------------+ -| PIO0_25 | GPIO | SW0 | -+---------+-----------------+----------------------------+ -| PIO0_10 | GPIO | SW1 | -+---------+-----------------+----------------------------+ -| PIO4_30 | USART12 | USART TX | -+---------+-----------------+----------------------------+ -| PIO4_31 | USART12 | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_29 | I2C | I2C SCL | -+---------+-----------------+----------------------------+ -| PIO0_30 | I2C | I2C SDA | -+---------+-----------------+----------------------------+ -| PIO0_22 | GPIO | FXOS8700 TRIGGER | -+---------+-----------------+----------------------------+ -| PIO1_5 | SPI | SPI MOSI | -+---------+-----------------+----------------------------+ -| PIO1_4 | SPI | SPI MISO | -+---------+-----------------+----------------------------+ -| PIO1_3 | SPI | SPI SCK | -+---------+-----------------+----------------------------+ -| PIO1_6 | SPI | SPI SSEL | -+---------+-----------------+----------------------------+ -| PIO0_5 | SCT0 | SCT0 GPI0 | -+---------+-----------------+----------------------------+ -| PIO0_6 | SCT0 | SCT0 GPI1 | -+---------+-----------------+----------------------------+ - -System Clock -============ - -The MIMXRT595 EVK is configured to use the OS Event timer -as a source for the system clock. - -Serial Port -=========== - -The MIMXRT595 SoC has 13 FLEXCOMM interfaces for serial communication. One is -configured as USART for the console and the remaining are not used. - -Fusion F1 DSP Core -================== - -You can build a Zephyr application for the RT500 DSP core using nxp_adsp_rt595 -board. Xtensa toolchain supporting RT500 DSP core is included in Zephyr SDK. -To build the hello_world sample for the RT500 DSP core: - -.. code-block:: shell - - $ west build -b nxp_adsp_rt595 samples/hello_world - -For detailed instructions on how to debug DSP firmware, please refer to -this document: `Getting Started with Xplorer for EVK-MIMXRT595`_ - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the LPC-Link2. - -.. tabs:: - - .. group-tab:: LPCLink2 JLink Onboard - - - 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. - 2. To connect the SWD signals to onboard debug circuit, install jumpers JP17, JP18 and JP19, - if not already done (these jumpers are installed by default). - 3. Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program the - J-Link firmware. Please make sure you have the latest firmware for this board. - - .. group-tab:: JLink External - - - 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. - - 2. To disconnect the SWD signals from onboard debug circuit, **remove** jumpers J17, J18, - and J19 (these are installed by default). - - 3. Connect the J-Link probe to J2 10-pin header. - - See :ref:`jlink-external-debug-probe` for more information. - - .. group-tab:: Linkserver - - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `MIMXRT595-EVK Debug Firmware` - -Configuring a Console -===================== - -Connect a USB cable from your PC to J40, and use the serial terminal of your choice -(minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`jlink-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt595_evk_cm33 - :goals: flash - -Open a serial terminal, reset the board (press the RESET button), and you should -see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS v2.7 *** - Hello World! mimxrt595_evk_cm33 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`jlink-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt595_evk_cm33 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS v2.7 *** - Hello World! mimxrt595_evk_cm33 - -Troubleshooting -=============== - -If the debug probe fails to connect with the following error, it's possible -that the image in flash is interfering and causing this issue. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the flash with the following -steps: - -#. Set the SW7 DIP switches to ON-ON-ON to prevent booting from flash. - -#. Reset by pressing SW3 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application (example "Hello World"). - -#. Set the SW5 DIP switches to OFF-OFF-ON to boot from flash. - -#. Reset by pressing SW3 - -.. _MIMXRT595-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK - -.. _MIMXRT595-EVK User Guide: - https://www.nxp.com/webapp/Download?colCode=MIMXRT595EVKHUG - -.. _MIMXRT595-EVK Debug Firmware: - https://www.nxp.com/docs/en/application-note/AN13206.pdf - -.. _MIMXRT595-EVK Schematics: - https://www.nxp.com/downloads/en/schematics/MIMXRT595-EVK-DESIGN-FILES.zip - -.. _i.MX RT595 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt500-crossover-mcu-with-arm-cortex-m33-dsp-and-gpu-cores:i.MX-RT500 - -.. _i.MX RT595 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT500EC.pdf - -.. _i.MX RT595 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT500RM - -.. _Getting Started with Xplorer for EVK-MIMXRT595: - https://www.nxp.com/docs/en/supporting-information/GSXEVKMIMXRT595.pdf diff --git a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts b/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts deleted file mode 100644 index f32420304df..00000000000 --- a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts +++ /dev/null @@ -1,512 +0,0 @@ -/* - * Copyright 2022-2023, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include - -#include "mimxrt595_evk_cm33-pinctrl.dtsi" - - -/ { - model = "NXP MIMXRT595-EVK board"; - compatible = "nxp,mimxrt595"; - - aliases { - sw0 = &user_button_1; - sw1 = &user_button_2; - led0 = &green_led; - led1 = &blue_led; - led2 = &red_led; - usart-0 = &flexcomm0; - watchdog0 = &wwdt0; - magn0 = &fxos8700; - accel0 = &fxos8700; - sdhc0 = &usdhc0; - pwm-0 = &sc_timer; - dmic-dev = &dmic0; - }; - - chosen { - zephyr,flash-controller = &mx25um51345g; - zephyr,flash = &mx25um51345g; - zephyr,code-partition = &slot0_partition; - zephyr,sram = &sram0; - zephyr,console = &flexcomm0; - zephyr,shell-uart = &flexcomm0; - zephyr,display = &lcdif; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_1: button_0 { - label = "User SW1"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_2: button_1 { - label = "User SW2"; - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - green_led: led_1 { - gpios = <&gpio1 0 0>; - label = "User LED_GREEN"; - }; - blue_led: led_2 { - gpios = <&gpio3 17 0>; - label = "User LED_BLUE"; - }; - red_led: led_3 { - gpios = <&gpio0 14 0>; - label = "User LED_RED"; - }; - }; - - arduino_header: arduino-connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 5 0>, /* A0 */ - <1 0 &gpio0 6 0>, /* A1 */ - <2 0 &gpio0 19 0>, /* A2 */ - <3 0 &gpio0 13 0>, /* A3 */ - <4 0 &gpio4 22 0>, /* A4 */ - <5 0 &gpio4 21 0>, /* A5 */ - <6 0 &gpio4 31 0>, /* D0 */ - <7 0 &gpio4 30 0>, /* D1 */ - <8 0 &gpio4 20 0>, /* D2 */ - <9 0 &gpio4 23 0>, /* D3 */ - <10 0 &gpio4 24 0>, /* D4 */ - <11 0 &gpio4 25 0>, /* D5 */ - <12 0 &gpio4 26 0>, /* D6 */ - <13 0 &gpio4 27 0>, /* D7 */ - <14 0 &gpio4 28 0>, /* D8 */ - <15 0 &gpio4 29 0>, /* D9 */ - <16 0 &gpio5 0 0>, /* D10 */ - <17 0 &gpio5 1 0>, /* D11 */ - <18 0 &gpio5 2 0>, /* D12 */ - <19 0 &gpio5 3 0>, /* D13 */ - <20 0 &gpio4 22 0>, /* D14 */ - <21 0 &gpio4 21 0>; /* D15 */ - }; - - /* - * This node describes the GPIO pins of the MIPI FPC interface, - * J44 on the EVK. This interface is standard to several - * NXP EVKs, and is used with several MIPI displays - * (available as zephyr shields) - */ - nxp_mipi_connector: mipi-connector { - compatible = "gpio-nexus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 12 0>, /* Pin 1, LEDK */ - <21 0 &gpio3 21 0>, /* Pin 21, RESET */ - <22 0 &gpio3 18 0>, /* Pin 22, LPTE */ - <26 0 &gpio0 30 0>, /* Pin 26, CTP_I2C SDA */ - <27 0 &gpio0 29 0>, /* Pin 27, CTP_I2C SCL */ - <28 0 &gpio4 4 0>, /* Pin 28, CTP_RST */ - <29 0 &gpio3 19 0>, /* Pin 29, CTP_INT */ - <32 0 &gpio3 15 0>, /* Pin 32, PWR_EN */ - <34 0 &gpio0 12 0>; /* Pin 34, BL_PWM */ - }; - - en_mipi_display: enable-mipi-display { - compatible = "regulator-fixed"; - regulator-name = "en_mipi_display"; - enable-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; -}; - -/* - * RT595 EVK board uses OS timer as the kernel timer - * In case we need to switch to SYSTICK timer, then - * replace &os_timer with &systick - */ -&os_timer { - status = "okay"; - wakeup-source; -}; - -&rtc { - status = "okay"; -}; - -&flexcomm0 { - compatible = "nxp,lpc-usart"; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm0_usart>; - pinctrl-names = "default"; - dmas = <&dma0 0>, <&dma0 1>; - dma-names = "rx", "tx"; -}; - -arduino_i2c: &flexcomm4 { - compatible = "nxp,lpc-i2c"; - status = "okay"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pinmux_flexcomm4_i2c>; - pinctrl-names = "default"; - - fxos8700: fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - int1-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; -}; - -nxp_mipi_i2c: &arduino_i2c {}; - -zephyr_mipi_dsi: &mipi_dsi {}; - -zephyr_lcdif: &lcdif {}; - - -hs_spi1: &hs_lspi1 { - compatible = "nxp,lpc-spi"; - pinctrl-0 = <&pinmux_flexcomm16_spi>; - pinctrl-names = "default"; - dmas = <&dma0 28>, <&dma0 29>; - dma-names = "rx", "tx"; - status = "okay"; -}; - -/* I2S RX */ -i2s0: &flexcomm1 { - compatible = "nxp,lpc-i2s"; - pinctrl-0 = <&pinmux_flexcomm1_i2s>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma0 2>; - dma-names = "rx"; - status = "disabled"; -}; - -/* I2S TX */ -i2s1: &flexcomm3 { - compatible = "nxp,lpc-i2s"; - pinctrl-0 = <&pinmux_flexcomm3_i2s>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma0 7>; - dma-names = "tx"; - status = "disabled"; -}; - -arduino_serial: &flexcomm12 { - compatible = "nxp,lpc-usart"; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm12_usart>; - pinctrl-names = "default"; - dmas = <&dma0 34>, <&dma0 35>; - dma-names = "rx", "tx"; -}; - -/* PCA9420 PMIC */ -&pmic_i2c { - status = "okay"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pinmux_pmic_i2c>; - pinctrl-names = "default"; - - pca9420: pca9420@61 { - compatible = "nxp,pca9420"; - reg = <0x61>; - nxp,enable-modesel-pins; - - pca9420_sw1: BUCK1 { - regulator-boot-on; - nxp,mode0-microvolt = <1100000>; - nxp,mode1-microvolt = <600000>; - nxp,mode2-microvolt = <900000>; - nxp,mode3-microvolt = <800000>; - }; - - pca9420_sw2: BUCK2 { - regulator-boot-on; - nxp,mode0-microvolt = <1800000>; - nxp,mode1-microvolt = <1800000>; - nxp,mode2-microvolt = <1800000>; - nxp,mode3-microvolt = <1800000>; - }; - - pca9420_ldo1: LDO1 { - regulator-boot-on; - nxp,mode0-microvolt = <1800000>; - nxp,mode1-microvolt = <1800000>; - nxp,mode2-microvolt = <1800000>; - nxp,mode3-microvolt = <1800000>; - }; - - pca9420_ldo2: LDO2 { - regulator-boot-on; - nxp,mode0-microvolt = <3300000>; - nxp,mode1-microvolt = <3300000>; - nxp,mode2-microvolt = <3300000>; - nxp,mode3-microvolt = <3300000>; - }; - }; -}; - -&lpadc0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpadc0>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -/* - * GPIO module interrupts are shared between all GPIO devices on this - * SOC, but Zephyr does not currently support sharing interrupts between - * devices. The user can select GPIO modules to support interrupts by - * setting the appropriate `int-source` and `interrupt` property for - * a given module. On this board, GPIO3 and GPIO4 are configured to support - * interrupts. - */ -&gpio3 { - status = "okay"; - int-source = "int-a"; - interrupts = <2 0>; -}; - -&gpio4 { - status = "okay"; - int-source = "int-b"; - interrupts = <3 0>; -}; - -&gpio5 { - status = "okay"; -}; - -&gpio6 { - status = "okay"; -}; - -&user_button_1 { - status = "okay"; -}; - -&user_button_2 { - status = "okay"; -}; - -&green_led { - status = "okay"; -}; - -&blue_led { - status = "okay"; -}; - -&red_led { - status = "okay"; -}; - -&dma0 { - status = "okay"; -}; - -zephyr_udc0: &usbhs { - status = "okay"; -}; - -&ctimer0 { - status = "okay"; -}; - -&ctimer1 { - status = "okay"; -}; - -&ctimer2 { - status = "okay"; -}; - -&ctimer3 { - status = "okay"; -}; - -&ctimer4 { - status = "okay"; -}; - -&usdhc0 { - status = "okay"; - pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - mmc { - compatible = "zephyr,mmc-disk"; - status = "okay"; - }; - pinctrl-0 = <&pinmux_usdhc>; - pinctrl-names = "default"; - mmc-hs200-1_8v; - mmc-hs400-1_8v; -}; - -&wwdt0 { - status = "okay"; -}; - -&flexspi { - status = "okay"; - pinctrl-0 = <&pinmux_flexspi>; - pinctrl-1 = <&pinmux_flexspi_sleep>; - pinctrl-names = "default", "sleep"; - - mx25um51345g: mx25um51345g@0 { - compatible = "nxp,imx-flexspi-mx25um51345g"; - /* MX25UM51245G is 64MB, 512MBit flash part */ - size = ; - reg = <0>; - spi-max-frequency = <200000000>; - status = "okay"; - jedec-id = [c2 81 3a]; - erase-block-size = <4096>; - write-block-size = <16>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 DT_SIZE_K(3076)>; - }; - slot1_partition: partition@321000 { - label = "image-1"; - reg = <0x00321000 DT_SIZE_K(3072)>; - }; - storage_partition: partition@621000 { - label = "storage"; - reg = <0x00621000 DT_SIZE_M(57)>; - }; - }; - }; -}; - -&flexspi2 { - status = "okay"; - pinctrl-0 = <&pinmux_flexspi2>; - pinctrl-names = "default"; - rx-clock-source = <3>; - ahb-prefetch; - ahb-bufferable; - ahb-cacheable; - ahb-read-addr-opt; - aps6408l: aps6408l@0 { - compatible = "nxp,imx-flexspi-aps6408l"; - /* APS6408L is 8MB, 64MBit pSRAM */ - size = ; - reg = <0>; - spi-max-frequency = <198000000>; - status = "okay"; - cs-interval-unit = <1>; - cs-interval = <5>; - cs-hold-time = <3>; - cs-setup-time = <3>; - data-valid-time = <1>; - column-space = <0>; - ahb-write-wait-unit = <2>; - ahb-write-wait-interval = <0>; - }; -}; - -&sc_timer { - pinctrl-0 = <&pinmux_sctimer_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i3c0 { - pinctrl-0 = <&pinmux_i3c>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&mbox { - status = "okay"; -}; - -/* Disable this node if not using USB and need another MPU region */ -&sram1 { - status = "okay"; -}; - -/* Enable smartDMA controller */ -&smartdma { - status = "okay"; -}; - -/* Add smartDMA to mipi DSI */ -&mipi_dsi { - dmas = <&smartdma>; - dma-names = "smartdma"; -}; - -&dmic0 { - status = "okay"; - pinctrl-0 = <&pinmux_dmic0>; - pinctrl-names = "default"; - use2fs; -}; - -/* Configure pdm channels 0 and 1 with gain, and cutoff settings - * appropriate for the attached MEMS microphones. - */ -&pdmc0 { - status = "okay"; - gainshift = <3>; - dc-cutoff = "155hz"; - dc-gain = <1>; -}; - -&pdmc1 { - status = "okay"; - gainshift = <3>; - dc-cutoff = "155hz"; - dc-gain = <1>; -}; - -&mrt_channel0 { - status = "okay"; -}; diff --git a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml b/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml deleted file mode 100644 index 95b17cb059f..00000000000 --- a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright (c) 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt595_evk_cm33 -name: NXP MIMXRT595-EVK -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 4608 -flash: 65536 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - counter - - dma - - gpio - - i2c - - spi - - usb_device - - watchdog - - sdhc - - pwm - - i2s - - dmic -vendor: nxp diff --git a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33_defconfig b/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33_defconfig deleted file mode 100644 index 054e0f21913..00000000000 --- a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT595S_CM33=y -CONFIG_SOC_SERIES_IMX_RT5XX=y -CONFIG_BOARD_MIMXRT595_EVK=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_PINCTRL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -# Enable TrustZone-M -CONFIG_TRUSTED_EXECUTION_SECURE=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/mimxrt685_evk/CMakeLists.txt b/boards/arm/mimxrt685_evk/CMakeLists.txt deleted file mode 100644 index 35c6f881ff7..00000000000 --- a/boards/arm/mimxrt685_evk/CMakeLists.txt +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright 2020-2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_library() -zephyr_library_sources(init.c) - -if(CONFIG_NXP_IMX_RT6XX_BOOT_HEADER) - if(NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT685-EVK, but targeting a custom board. You may need to " - "update your flash configuration block data") - endif() - # Include flash configuration block for R685 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN13386 for more information. - zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT685_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt685") - zephyr_library_sources(${RT685_BOARD_DIR}/flash_config/flash_config.c) - zephyr_library_include_directories(${RT685_BOARD_DIR}/flash_config) -endif() diff --git a/boards/arm/mimxrt685_evk/Kconfig.board b/boards/arm/mimxrt685_evk/Kconfig.board deleted file mode 100644 index e1223fa03f3..00000000000 --- a/boards/arm/mimxrt685_evk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT685_EVK - bool "NXP MIMXRT685-EVK" - depends on SOC_SERIES_IMX_RT6XX - select SOC_PART_NUMBER_MIMXRT685SFVKB - select NXP_IMX_RT6XX_BOOT_HEADER if !BOOTLOADER_MCUBOOT diff --git a/boards/arm/mimxrt685_evk/Kconfig.defconfig b/boards/arm/mimxrt685_evk/Kconfig.defconfig deleted file mode 100644 index db2679a3d4d..00000000000 --- a/boards/arm/mimxrt685_evk/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# MIMXRT685-EVK board - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT685_EVK - -config BOARD - default "mimxrt685_evk_cm33" - -config XTAL_SYS_CLK_HZ - default 24000000 - -config SYSOSC_SETTLING_US - default 260 - -choice FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_MODE - default FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_STR -endchoice - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM -endchoice - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -endif # BOARD_MIMXRT685_EVK diff --git a/boards/arm/mimxrt685_evk/doc/index.rst b/boards/arm/mimxrt685_evk/doc/index.rst deleted file mode 100644 index 579cd1e4087..00000000000 --- a/boards/arm/mimxrt685_evk/doc/index.rst +++ /dev/null @@ -1,370 +0,0 @@ -.. _mimxrt685_evk: - -NXP MIMXRT685-EVK -################## - -Overview -******** - -The i.MX RT600 is a crossover MCU family optimized for 32-bit immersive audio -playback and voice user interface applications combining a high-performance -Cadence Tensilica HiFi 4 audio DSP core with a next-generation Cortex-M33 -core. The i.MX RT600 family of crossover MCUs is designed to unlock the -potential of voice-assisted end nodes with a secure, power-optimized embedded -processor. - -The i.MX RT600 family provides up to 4.5MB of on-chip SRAM and several -high-bandwidth interfaces to access off-chip flash, including an Octal/Quad SPI -interface with an on-the-fly decryption engine. - -.. image:: mimxrt685_evk.jpg - :align: center - :alt: MIMXRT685-EVK - -Hardware -******** - -- MIMXRT685SFVKB Cortex-M33 (300 MHz, 128 KB TCM) core processor with Cadence Xtensa HiFi4 DSP -- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug only) -- High speed USB port with micro A/B connector for the host or device functionality -- UART, I2C and SPI port bridging from i.MX RT685 target to USB via the on-board debug probe -- 512 MB Macronix Octal SPI Flash operating at 1.8 V -- 4.5 MB Apmemory PSRAM -- Full size SD card slot (SDIO) -- NXP PCA9420UK PMIC -- User LEDs -- Reset and User buttons -- Arduino and PMod/Host expansion connectors -- NXP FXOS8700CQ accelerometer -- Stereo audio codec with line in/out and electret microphone -- Stereo NXP TFA9894 digital amplifiers, with option for external +5V power for higher performance speakers -- Support for up to eight off-board digital microphones via 12-pin header -- Two on-board DMICS - -For more information about the MIMXRT685 SoC and MIMXRT685-EVK board, see -these references: - -- `i.MX RT685 Website`_ -- `i.MX RT685 Datasheet`_ -- `i.MX RT685 Reference Manual`_ -- `MIMXRT685-EVK Website`_ -- `MIMXRT685-EVK User Guide`_ -- `MIMXRT685-EVK Schematics`_ - -Supported Features -================== - -NXP considers the MIMXRT685-EVK as a superset board for the i.MX RT6xx -family of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire RT6xx family. NXP prioritizes enabling -this board with new support for Zephyr features. The mimxrt685_evk board -configuration supports the hardware features below. Another very similar -board is the :ref:`mimxrt595_evk`, and that board may have additional features -already supported, which can also be re-used on this mimxrt685_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| OS_TIMER | on-chip | os timer | -+-----------+------------+-------------------------------------+ -| IOCON | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | OctalSPI Flash | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SDHC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| CTIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/mimxrt685_evk/mimxrt685_evk_cm33_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The MIMXRT685 SoC has IOCON registers, which can be used to configure the -functionality of a pin. - -+---------+-----------------+----------------------------+ -| Name | Function | Usage | -+=========+=================+============================+ -| PIO0_2 | USART | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_1 | USART | USART TX | -+---------+-----------------+----------------------------+ -| PIO0_14 | GPIO | GREEN LED | -+---------+-----------------+----------------------------+ -| PIO1_1 | GPIO | SW0 | -+---------+-----------------+----------------------------+ -| PIO0_17 | I2C | I2C SDA | -+---------+-----------------+----------------------------+ -| PIO0_18 | I2C | I2C SCL | -+---------+-----------------+----------------------------+ -| PIO1_5 | GPIO | FXOS8700 TRIGGER | -+---------+-----------------+----------------------------+ -| PIO1_5 | SPI | SPI MOSI | -+---------+-----------------+----------------------------+ -| PIO1_4 | SPI | SPI MISO | -+---------+-----------------+----------------------------+ -| PIO1_3 | SPI | SPI SCK | -+---------+-----------------+----------------------------+ -| PIO1_6 | SPI | SPI SSEL | -+---------+-----------------+----------------------------+ -| PIO0_23 | I2S | I2S DATAOUT | -+---------+-----------------+----------------------------+ -| PIO0_22 | I2S | I2S TX WS | -+---------+-----------------+----------------------------+ -| PIO0_21 | I2S | I2S TX SCK | -+---------+-----------------+----------------------------+ -| PIO0_9 | I2S | I2S DATAIN | -+---------+-----------------+----------------------------+ -| PIO0_29 | USART | USART TX | -+---------+-----------------+----------------------------+ -| PIO0_30 | USART | USART RX | -+---------+-----------------+----------------------------+ -| PIO1_11 | FLEXSPI0B_DATA0 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO1_12 | FLEXSPI0B_DATA1 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO1_13 | FLEXSPI0B_DATA2 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO1_14 | FLEXSPI0B_DATA3 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO1_29 | FLEXSPI0B_SCLK | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_12 | PIO2_12 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_17 | FLEXSPI0B_DATA4 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_18 | FLEXSPI0B_DATA5 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_19 | FLEXSPI0B_SS0_N | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_22 | FLEXSPI0B_DATA6 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_23 | FLEXSPI0B_DATA7 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO0_27 | SCT0_OUT7 | PWM | -+---------+-----------------+----------------------------+ -| PIO1_30 | SD0_CLK | SD card | -+---------+-----------------+----------------------------+ -| PIO1_31 | SD0_CMD | SD card | -+---------+-----------------+----------------------------+ -| PIO2_0 | SD0_D0 | SD card | -+---------+-----------------+----------------------------+ -| PIO2_1 | SD0_D1 | SD card | -+---------+-----------------+----------------------------+ -| PIO2_2 | SD0_D2 | SD card | -+---------+-----------------+----------------------------+ -| PIO2_3 | SD0_D3 | SD card | -+---------+-----------------+----------------------------+ -| PIO2_4 | SD0_WR_PRT | SD card | -+---------+-----------------+----------------------------+ -| PIO2_9 | SD0_CD | SD card | -+---------+-----------------+----------------------------+ -| PIO2_10 | SD0_RST | SD card | -+---------+-----------------+----------------------------+ - -System Clock -============ - -The MIMXRT685 EVK is configured to use the OS Event timer -as a source for the system clock. - -Serial Port -=========== - -The MIMXRT685 SoC has 8 FLEXCOMM interfaces for serial communication. One is -configured as USART for the console and the remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the LPC-Link2. - -.. tabs:: - - .. group-tab:: LinkServer CMSIS-DAP - - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your - search path. LinkServer works with the default CMSIS-DAP firmware included in - the on-board debugger. - 2. Make sure the jumpers JP17, JP18 and JP19 are installed. - - linkserver is the default runner for this board - - .. code-block:: console - - west flash - west debug - - .. group-tab:: LPCLink2 JLink Onboard - - - 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. - 2. To connect the SWD signals to onboard debug circuit, install jumpers JP17, JP18 and JP19, - if not already done (these jumpers are installed by default). - 3. Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program the - J-Link firmware. Please make sure you have the latest firmware for this board. - - .. code-block:: console - - west flash -r jlink - west debug -r jlink - - .. group-tab:: JLink External - - - 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. - - 2. To disconnect the SWD signals from onboard debug circuit, **remove** jumpers J17, J18, - and J19 (these are installed by default). - - 3. Connect the J-Link probe to J2 10-pin header. - - See :ref:`jlink-external-debug-probe` for more information. - - .. code-block:: console - - west flash -r jlink - west debug -r jlink - -Configuring a Console -===================== - -Connect a USB cable from your PC to J16, and use the serial terminal of your choice -(minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`linkserver-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt685_evk_cm33 - :goals: flash - -Open a serial terminal, reset the board (press the RESET button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0 ***** - Hello World! mimxrt685_evk_cm33 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`linkserver-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt685_evk_cm33 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS zephyr-v2.3.0 ***** - Hello World! mimxrt685_evk_cm33 - -Troubleshooting -=============== - -If the debug probe fails to connect with the following error, it's possible -that the image in flash is interfering and causing this issue. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the flash with the following -steps: - -#. Set the SW5 DIP switches to ON-ON-ON to prevent booting from flash. - -#. Reset by pressing SW3 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application (example "Hello World"). - -#. Set the SW5 DIP switches to ON-OFF-ON to boot from flash. - -#. Reset by pressing SW3 - -.. _MIMXRT685-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK - -.. _MIMXRT685-EVK User Guide: - https://www.nxp.com/webapp/Download?colCode=UM11159 - -.. _MIMXRT685-EVK Schematics: - https://www.nxp.com/downloads/en/design-support/RT685-DESIGNFILES.zip - -.. _i.MX RT685 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt600-crossover-mcu-with-arm-cortex-m33-and-dsp-cores:i.MX-RT600 - -.. _i.MX RT685 Datasheet: - https://www.nxp.com/docs/en/data-sheet/DS-RT600.pdf - -.. _i.MX RT685 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=UM11147 diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts deleted file mode 100644 index 245e9833c3e..00000000000 --- a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts +++ /dev/null @@ -1,387 +0,0 @@ -/* - * Copyright (c) 2020-2023, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include - -#include "mimxrt685_evk_cm33-pinctrl.dtsi" - -/ { - model = "NXP MIMXRT685-EVK board"; - compatible = "nxp,mimxrt685"; - - aliases { - sw0 = &user_button_1; - sw1 = &user_button_2; - led0 = &green_led; - led1 = &blue_led; - led2 = &red_led; - usart-0 = &flexcomm0; - /* For pwm test suites */ - pwm-0 = &sc_timer; - pwm-led0 = &green_pwm_led; - green-pwm-led = &green_pwm_led; - blue-pwm-led = &blue_pwm_led; - red-pwm-led = &red_pwm_led; - watchdog0 = &wwdt0; - magn0 = &fxos8700; - accel0 = &fxos8700; - sdhc0 = &usdhc0; - }; - - chosen { - zephyr,flash-controller = &mx25um51345g; - zephyr,flash = &mx25um51345g; - zephyr,code-partition = &slot0_partition; - zephyr,sram = &sram0; - zephyr,console = &flexcomm0; - zephyr,shell-uart = &flexcomm0; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_1: button_0 { - label = "User SW1"; - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_2: button_1 { - label = "User SW2"; - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - green_led: led_1 { - gpios = <&gpio0 14 0>; - label = "User LED_GREEN"; - }; - blue_led: led_2 { - gpios = <&gpio0 26 0>; - label = "User LED_BLUE"; - }; - red_led: led_3 { - gpios = <&gpio0 31 0>; - label = "User LED_RED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - green_pwm_led: green_pwm_led { - pwms = <&sc_timer 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "Green PWM LED"; - status = "okay"; - }; - blue_pwm_led: blue_pwm_led { - pwms = <&sc_timer 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "Blue PWM LED"; - status = "okay"; - }; - red_pwm_led: red_pwm_led { - pwms = <&sc_timer 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "Red PWM LED"; - status = "disabled"; - }; - }; - - arduino_header: arduino-connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 5 0>, /* A0 */ - <1 0 &gpio0 6 0>, /* A1 */ - <2 0 &gpio0 19 0>, /* A2 */ - <3 0 &gpio0 20 0>, /* A3 */ - <4 0 &gpio0 17 0>, /* A4 */ - <5 0 &gpio0 18 0>, /* A5 */ - <6 0 &gpio0 30 0>, /* D0 */ - <7 0 &gpio0 29 0>, /* D1 */ - <8 0 &gpio0 28 0>, /* D2 */ - <9 0 &gpio0 27 0>, /* D3 */ - <10 0 &gpio1 0 0>, /* D4 */ - <11 0 &gpio1 10 0>, /* D5 */ - <12 0 &gpio1 2 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio1 9 0>, /* D8 */ - <15 0 &gpio1 7 0>, /* D9 */ - <16 0 &gpio1 6 0>, /* D10 */ - <17 0 &gpio1 5 0>, /* D11 */ - <18 0 &gpio1 4 0>, /* D12 */ - <19 0 &gpio1 3 0>, /* D13 */ - <20 0 &gpio0 17 0>, /* D14 */ - <21 0 &gpio0 18 0>; /* D15 */ - }; -}; - -/* - * RT600 EVK board uses OS timer as the kernel timer - * In case we need to switch to SYSTICK timer, then - * replace &os_timer with &systick - */ -&os_timer { - status = "okay"; - wakeup-source; -}; - -&rtc { - status = "okay"; -}; - -&flexcomm0 { - compatible = "nxp,lpc-usart"; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm0_usart>; - pinctrl-names = "default"; - dmas = <&dma0 0>, <&dma0 1>; - dma-names = "rx", "tx"; -}; - -arduino_i2c: &flexcomm2 { - compatible = "nxp,lpc-i2c"; - status = "okay"; - pinctrl-0 = <&pinmux_flexcomm2_i2c>; - pinctrl-names = "default"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - fxos8700: fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - int1-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; -}; - -arduino_serial: &flexcomm4 { - compatible = "nxp,lpc-usart"; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm4_usart>; - pinctrl-names = "default"; - dmas = <&dma0 8>, <&dma0 9>; - dma-names = "rx", "tx"; -}; - -arduino_spi: &flexcomm5 { - compatible = "nxp,lpc-spi"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma0 10>, <&dma0 11>; - dma-names = "rx", "tx"; - pinctrl-0 = <&pinmux_flexcomm5_spi>; - pinctrl-names = "default"; -}; - -/* I2S receive channel */ -i2s0: &flexcomm1 { - status = "okay"; - compatible = "nxp,lpc-i2s"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma0 2>; - dma-names = "rx"; - pinctrl-0 = <&pinmux_flexcomm1_i2s>; - pinctrl-names = "default"; -}; - -/* I2S transmit channel */ -i2s1: &flexcomm3 { - status = "okay"; - compatible = "nxp,lpc-i2s"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma0 7>; - dma-names = "tx"; - pinctrl-0 = <&pinmux_flexcomm3_i2s>; - pinctrl-names = "default"; -}; - -/* PCA9420 PMIC */ -&pmic_i2c { - status = "okay"; - compatible = "nxp,lpc-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pinmux_pmic_i2c>; - pinctrl-names = "default"; - - pca9420: pca9420@61 { - compatible = "nxp,pca9420"; - reg = <0x61>; - nxp,enable-modesel-pins; - - buck1: BUCK1 { - regulator-boot-on; - }; - - buck2: BUCK2 { - regulator-boot-on; - }; - - ldo1: LDO1 { - regulator-boot-on; - }; - - ldo2: LDO2 { - regulator-boot-on; - }; - - - }; -}; - -&flexspi { - pinctrl-0 = <&pinmux_flexspi>; - pinctrl-names = "default"; - status = "okay"; - mx25um51345g: mx25um51345g@2 { - compatible = "nxp,imx-flexspi-mx25um51345g"; - /* MX25UM51245G is 64MB, 512MBit flash part */ - size = ; - reg = <2>; - spi-max-frequency = <200000000>; - status = "okay"; - jedec-id = [c2 81 3a]; - erase-block-size = <4096>; - write-block-size = <16>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 DT_SIZE_K(3076)>; - }; - slot1_partition: partition@321000 { - label = "image-1"; - reg = <0x00321000 DT_SIZE_K(3072)>; - }; - storage_partition: partition@621000 { - label = "storage"; - reg = <0x00621000 DT_SIZE_M(57)>; - }; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&dma0 { - status = "okay"; -}; - -&wwdt0 { - status = "okay"; -}; - -&user_button_1 { - status = "okay"; -}; - -&user_button_2 { - status = "okay"; -}; - -&green_led { - status = "okay"; -}; - -&blue_led { - status = "okay"; -}; - -&red_led { - status = "okay"; -}; - -&sc_timer { - status = "okay"; - pinctrl-0 = <&pinmux_sctimer>; - pinctrl-names = "default"; -}; - -&usdhc0 { - status = "okay"; - /* Quick fix for 1.8V SD cards on RT600- disable 1.8V negotiation */ - no-1-8-v; - pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - sdmmc { - compatible = "zephyr,sdmmc-disk"; - status = "okay"; - }; - pinctrl-0 = <&pinmux_usdhc>; - pinctrl-names = "default"; -}; - -&lpadc0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpadc0>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usbhs { - status = "okay"; -}; - -&ctimer0 { - status = "okay"; -}; - -&ctimer1 { - status = "okay"; -}; - -&ctimer2 { - status = "okay"; -}; - -&ctimer3 { - status = "okay"; -}; - -&ctimer4 { - status = "okay"; -}; - -&i3c0 { - pinctrl-0 = <&pinmux_i3c>; - pinctrl-names = "default"; - - status = "okay"; -}; - -/* Disable this node if not using USB and need another MPU region */ -&sram1 { - status = "okay"; -}; diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml deleted file mode 100644 index d940cbe35f8..00000000000 --- a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml +++ /dev/null @@ -1,34 +0,0 @@ -# -# Copyright (c) 2020, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt685_evk_cm33 -name: NXP MIMXRT685-EVK -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 4608 -flash: 65536 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - counter - - dma - - pwm - - gpio - - hwinfo - - i2c - - i3c - - i2s - - sdhc - - spi - - watchdog - - usb_device -vendor: nxp diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33_defconfig b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33_defconfig deleted file mode 100644 index 05673abdd6b..00000000000 --- a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# -# Copyright (c) 2020, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT685S_CM33=y -CONFIG_SOC_SERIES_IMX_RT6XX=y -CONFIG_BOARD_MIMXRT685_EVK=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_PINCTRL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -# Enable TrustZone-M -CONFIG_TRUSTED_EXECUTION_SECURE=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/mm_feather/CMakeLists.txt b/boards/arm/mm_feather/CMakeLists.txt deleted file mode 100644 index e20be4b42e0..00000000000 --- a/boards/arm/mm_feather/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2021 MADMACHINE LIMITED -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR flexspi_nor_config.c) - zephyr_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA mmfeather_sdram_ini_dcd.c) -endif() diff --git a/boards/arm/mm_feather/Kconfig.board b/boards/arm/mm_feather/Kconfig.board deleted file mode 100644 index c003514fdab..00000000000 --- a/boards/arm/mm_feather/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) 2021, MADMACHINE LIMITED -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_MM_FEATHER - bool "MM MM-FEATHER" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/arm/mm_feather/Kconfig.defconfig b/boards/arm/mm_feather/Kconfig.defconfig deleted file mode 100644 index 80201fdcb86..00000000000 --- a/boards/arm/mm_feather/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# MM-FEATHER board - -# Copyright (c) 2021, MADMACHINE LIMITED -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MM_FEATHER - -config BOARD - default "mm_feather" - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_MM_FEATHER diff --git a/boards/arm/mm_feather/flexspi_nor_config.c b/boards/arm/mm_feather/flexspi_nor_config.c deleted file mode 100644 index 647dac001c9..00000000000 --- a/boards/arm/mm_feather/flexspi_nor_config.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2019, MADMACHINE LIMITED - * - * refer to hal_nxp board file - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -const struct flexspi_nor_config_t Qspiflash_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = - kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = 8u * 1024u * 1024u, - .lookupTable = { - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0xEB, RADDR_SDR, - FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, - 0x06, READ_SDR, - FLEXSPI_4PAD, 0x04), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 256u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */ diff --git a/boards/arm/mm_swiftio/CMakeLists.txt b/boards/arm/mm_swiftio/CMakeLists.txt deleted file mode 100644 index 8fb1964f320..00000000000 --- a/boards/arm/mm_swiftio/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 20179 MADMACHINE LIMITED -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR flexspi_nor_config.c) - zephyr_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA mmswiftio_sdram_ini_dcd.c) -endif() diff --git a/boards/arm/mm_swiftio/Kconfig.board b/boards/arm/mm_swiftio/Kconfig.board deleted file mode 100644 index 65352dfdc01..00000000000 --- a/boards/arm/mm_swiftio/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) 2019, MADMACHINE LIMITED -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_MM_SWIFTIO - bool "MM MM-SWIFTIO" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1052DVL6A diff --git a/boards/arm/mm_swiftio/Kconfig.defconfig b/boards/arm/mm_swiftio/Kconfig.defconfig deleted file mode 100644 index 95fe8e06d9c..00000000000 --- a/boards/arm/mm_swiftio/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# MM-SWIFTIO board - -# Copyright (c) 2019, MADMACHINE LIMITED -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MM_SWIFTIO - -config BOARD - default "mm_swiftio" - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_MM_SWIFTIO diff --git a/boards/arm/mm_swiftio/flexspi_nor_config.c b/boards/arm/mm_swiftio/flexspi_nor_config.c deleted file mode 100644 index 647dac001c9..00000000000 --- a/boards/arm/mm_swiftio/flexspi_nor_config.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2019, MADMACHINE LIMITED - * - * refer to hal_nxp board file - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -const struct flexspi_nor_config_t Qspiflash_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = - kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = 8u * 1024u * 1024u, - .lookupTable = { - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0xEB, RADDR_SDR, - FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, - 0x06, READ_SDR, - FLEXSPI_4PAD, 0x04), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 256u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */ diff --git a/boards/arm/mps2/CMakeLists.txt b/boards/arm/mps2/CMakeLists.txt new file mode 100644 index 00000000000..2f6cea861c6 --- /dev/null +++ b/boards/arm/mps2/CMakeLists.txt @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(pinmux.c) + +if(CONFIG_BOARD_MPS2_AN521_CPU1 AND NOT CONFIG_OPENAMP) + # Building a firmware image for CPU1: this requires a binary + # for CPU0, which will boot the device and wake up CPU1. + # However, if building with OPENAMP, there is no need to build + # any binary for CPU0, as this is built by the dual core sample. + set(CPU0_BINARY_DIR ${BOARD_DIR}/empty_cpu0-prefix/src/empty-cpu0-build/zephyr) + + include(ExternalProject) + + ExternalProject_Add( + empty_cpu0 + SOURCE_DIR ${BOARD_DIR}/empty_cpu0 + INSTALL_COMMAND "" + CMAKE_CACHE_ARGS -DBOARD:STRING=${BOARD}/an521/cpu0 + BUILD_BYPRODUCTS "${CPU0_BINARY_DIR}/${KERNEL_BIN_NAME}" + BUILD_ALWAYS True + ) +endif() diff --git a/boards/arm/mps2/Kconfig b/boards/arm/mps2/Kconfig new file mode 100644 index 00000000000..4beda641d53 --- /dev/null +++ b/boards/arm/mps2/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPS2 + select QEMU_TARGET + select HAS_COVERAGE_SUPPORT diff --git a/boards/arm/mps2/Kconfig.defconfig b/boards/arm/mps2/Kconfig.defconfig new file mode 100644 index 00000000000..b14613b4880 --- /dev/null +++ b/boards/arm/mps2/Kconfig.defconfig @@ -0,0 +1,60 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MPS2_AN385 + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +endif # SERIAL + +config ZTEST_STACK_SIZE + default 4096 if ZTEST + +if COVERAGE_GCOV + +config MAIN_STACK_SIZE + default 4096 + +config IDLE_STACK_SIZE + default 4096 + +config PRIVILEGED_STACK_SIZE + default 4096 + +config ISR_STACK_SIZE + default 4096 + +config TEST_EXTRA_STACK_SIZE + default 4096 + +endif # COVERAGE_GCOV + +endif + +if BOARD_MPS2_AN521_CPU0 || BOARD_MPS2_AN521_CPU0_NS || BOARD_MPS2_AN521_CPU1 + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped but QEMU +# will still permit bus access. +choice NULL_POINTER_EXCEPTION_DETECTION + bool + default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET + +endchoice + +# By default, if we build for a Non-Secure version of the board, +# force building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y if TRUSTED_EXECUTION_NONSECURE + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +endif # SERIAL + +endif diff --git a/boards/arm/mps2/Kconfig.mps2 b/boards/arm/mps2/Kconfig.mps2 new file mode 100644 index 00000000000..0731c5d2855 --- /dev/null +++ b/boards/arm/mps2/Kconfig.mps2 @@ -0,0 +1,8 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPS2 + select SOC_MPS2_AN385 if BOARD_MPS2_AN385 + select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0 + select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0_NS + select SOC_MPS2_AN521_CPU1 if BOARD_MPS2_AN521_CPU1 diff --git a/boards/arm/mps2/board.cmake b/boards/arm/mps2/board.cmake new file mode 100644 index 00000000000..21d98c39bfa --- /dev/null +++ b/boards/arm/mps2/board.cmake @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) + +if(CONFIG_BOARD_MPS2_AN385) + set(QEMU_CPU_TYPE_${ARCH} cortex-m3) + set(QEMU_FLAGS_${ARCH} + -cpu ${QEMU_CPU_TYPE_${ARCH}} + -machine mps2-an385 + -nographic + -vga none + ) +elseif(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOARD_MPS2_AN521_CPU1) + set(QEMU_CPU_TYPE_${ARCH} cortex-m33) + set(QEMU_FLAGS_${ARCH} + -cpu ${QEMU_CPU_TYPE_${ARCH}} + -machine mps2-an521 + -nographic + -m 16 + -vga none + ) +endif() + +board_set_debugger_ifnset(qemu) + +if(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOARD_MPS2_AN521_CPU1) + # To enable a host tty switch between serial and pty + # -chardev serial,path=/dev/ttyS0,id=hostS0 + list(APPEND QEMU_EXTRA_FLAGS -chardev pty,id=hostS0 -serial chardev:hostS0) + + if(CONFIG_BUILD_WITH_TFM) + # Override the binary used by qemu, to use the combined + # TF-M (Secure) & Zephyr (Non Secure) image (when running + # in-tree tests). + set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex") + elseif(CONFIG_OPENAMP) + set(QEMU_EXTRA_FLAGS "-device;loader,file=${REMOTE_ZEPHYR_DIR}/zephyr.elf") + elseif(CONFIG_BOARD_MPS2_AN521_CPU1) + set(CPU0_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}/zephyr/boards/arm/mps2/empty_cpu0-prefix/src/empty_cpu0-build/zephyr) + set(QEMU_KERNEL_OPTION "-device;loader,file=${CPU0_BINARY_DIR}/zephyr.elf") + list(APPEND QEMU_EXTRA_FLAGS "-device;loader,file=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}") + endif() +endif() diff --git a/boards/arm/mps2/board.yml b/boards/arm/mps2/board.yml new file mode 100644 index 00000000000..a069852c1c6 --- /dev/null +++ b/boards/arm/mps2/board.yml @@ -0,0 +1,9 @@ +board: + name: mps2 + vendor: arm + socs: + - name: an385 + - name: an521 + variants: + - name: ns + cpucluster: cpu0 diff --git a/boards/arm/mps2_an385/doc/img/mps2_an385.jpg b/boards/arm/mps2/doc/img/mps2_an385.jpg similarity index 100% rename from boards/arm/mps2_an385/doc/img/mps2_an385.jpg rename to boards/arm/mps2/doc/img/mps2_an385.jpg diff --git a/boards/arm/mps2_an521/doc/img/mps2_an521.jpg b/boards/arm/mps2/doc/img/mps2_an521.jpg similarity index 100% rename from boards/arm/mps2_an521/doc/img/mps2_an521.jpg rename to boards/arm/mps2/doc/img/mps2_an521.jpg diff --git a/boards/arm/mps2/doc/mps2_an385.rst b/boards/arm/mps2/doc/mps2_an385.rst new file mode 100644 index 00000000000..ffd8942dbfd --- /dev/null +++ b/boards/arm/mps2/doc/mps2_an385.rst @@ -0,0 +1,281 @@ +.. _mps2_an385_board: + +ARM V2M MPS2 +############ + +Overview +******** + +The mps2/an385 board configuration is used by Zephyr applications that run on +the V2M MPS2 board. It provides support for the ARM Cortex-M3 (AN385) CPU and +the following devices: + +- Nested Vectored Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) +- Cortex-M System Design Kit UART + +.. image:: img/mps2_an385.jpg + :align: center + :alt: ARM V2M MPS2 + +In addition to enabling actual hardware usage, this board configuration can +also use QEMU to emulate the AN385 platform running on the MPS2+. + +More information about the board can be found at the `V2M MPS2 Website`_. + +The Application Note AN385 can be found at `Application Note AN385`_. + +.. note:: + This board configuration makes no claims about its suitability for use + with actual MPS2 hardware systems using AN385, or any other hardware + system. It has been tested on actual hardware, but its primary purpose is + for use with QEMU and unit tests. + +Hardware +******** + +ARM V2M MPS2 provides the following hardware components: + +- ARM Cortex-M3 (AN385) +- ARM IoT Subsystem for Cortex-M +- Form factor: 140x120cm +- ZBTSRAM: 8MB single cycle SRAM, 16MB PSRAM +- Video: QSVGA touch screen panel, 4bit RGB VGA connector +- Audio: Audio Codec +- Debug: + + - ARM JTAG20 connector + - ARM parallel trace connector (MICTOR38) + - 20 pin Cortex debug connector + - 10 pin Cortex debug connector + - ILA connector for FPGA debug + +- Expansion + + - GPIO + - SPI + +.. note:: + 4 MB of flash memory (in ZBTSRAM 1, starting at address 0x00400000) and 4 MB of RAM + (in ZBTSRAM 2 & 3, starting at address 0x20000000) are available. + +Supported Features +================== + +The mps2/an385 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| DUALTIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. +See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware +features. + +The default configuration can be found in +:zephyr_file:`boards/arm/mps2/mps2_an385_defconfig` + +Interrupt Controller +==================== + +MPS2 is a Cortex-M3 based SoC and has 15 fixed exceptions and 45 IRQs. + +A Cortex-M3/4-based board uses vectored exceptions. This means each exception +calls a handler directly from the vector table. + +Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here +identifies the handlers used for each exception. + ++------+------------+----------------+--------------------------+ +| Exc# | Name | Remarks | Used by Zephyr Kernel | ++======+============+================+==========================+ +| 1 | Reset | | system initialization | ++------+------------+----------------+--------------------------+ +| 2 | NMI | | system fatal error | ++------+------------+----------------+--------------------------+ +| 3 | Hard fault | | system fatal error | ++------+------------+----------------+--------------------------+ +| 4 | MemManage | MPU fault | system fatal error | ++------+------------+----------------+--------------------------+ +| 5 | Bus | | system fatal error | ++------+------------+----------------+--------------------------+ +| 6 | Usage | undefined | system fatal error | +| | fault | instruction, | | +| | | or switch | | +| | | attempt to ARM | | +| | | mode | | ++------+------------+----------------+--------------------------+ +| 11 | SVC | | system calls, kernel | +| | | | run-time exceptions, | +| | | | and IRQ offloading | ++------+------------+----------------+--------------------------+ +| 12 | Debug | | system fatal error | +| | monitor | | | ++------+------------+----------------+--------------------------+ +| 14 | PendSV | | context switch | ++------+------------+----------------+--------------------------+ +| 15 | SYSTICK | | system clock | ++------+------------+----------------+--------------------------+ + +Pin Mapping +=========== + +The ARM V2M MPS2 Board has 4 GPIO controllers. These controllers are responsible +for pin muxing, input/output, pull-up, etc. + +All GPIO controller pins are exposed via the following sequence of pin numbers: + +- Pins 0 - 15 are for GPIO 0 +- Pins 16 - 31 are for GPIO 1 +- Pins 32 - 47 are for GPIO 2 +- Pins 48 - 51 are for GPIO 3 + +Mapping from the ARM MPS2 Board pins to GPIO controllers: + +.. rst-class:: rst-columns + + - D0 : EXT_0 + - D1 : EXT_4 + - D2 : EXT_2 + - D3 : EXT_3 + - D4 : EXT_1 + - D5 : EXT_6 + - D6 : EXT_7 + - D7 : EXT_8 + - D8 : EXT_9 + - D9 : EXT_10 + - D10 : EXT_12 + - D11 : EXT_13 + - D12 : EXT_14 + - D13 : EXT_11 + - D14 : EXT_15 + - D15 : EXT_5 + - D16 : EXT_16 + - D17 : EXT_17 + - D18 : EXT_18 + - D19 : EXT_19 + - D20 : EXT_20 + - D21 : EXT_21 + - D22 : EXT_22 + - D23 : EXT_23 + - D24 : EXT_24 + - D25 : EXT_25 + - D26 : EXT_26 + - D27 : EXT_30 + - D28 : EXT_28 + - D29 : EXT_29 + - D30 : EXT_27 + - D31 : EXT_32 + - D32 : EXT_33 + - D33 : EXT_34 + - D34 : EXT_35 + - D35 : EXT_36 + - D36 : EXT_38 + - D37 : EXT_39 + - D38 : EXT_40 + - D39 : EXT_44 + - D40 : EXT_41 + - D41 : EXT_31 + - D42 : EXT_37 + - D43 : EXT_42 + - D44 : EXT_43 + - D45 : EXT_45 + - D46 : EXT_46 + - D47 : EXT_47 + - D48 : EXT_48 + - D49 : EXT_49 + - D50 : EXT_50 + - D51 : EXT_51 + +Peripheral Mapping: + +.. rst-class:: rst-columns + + - UART_3_RX : D0 + - UART_3_TX : D1 + - SPI_3_CS : D10 + - SPI_3_MOSI : D11 + - SPI_3_MISO : D12 + - SPI_3_SCLK : D13 + - I2C_3_SDA : D14 + - I2C_3_SCL : D15 + - UART_4_RX : D26 + - UART_4_TX : D30 + - SPI_4_CS : D36 + - SPI_4_MOSI : D37 + - SPI_4_MISO : D38 + - SPI_4_SCK : D39 + - I2C_4_SDA : D40 + - I2C_4_SCL : D41 + +For more details please refer to `MPS2 Technical Reference Manual (TRM)`_. + +System Clock +============ + +The V2M MPS2 main clock is 24 MHz. + +Serial Port +=========== + +The V2M MPS2 processor has five UARTs. Both the UARTs have only two wires for +RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by +default, is utilizing UART0. + +Programming and Debugging +************************* + +Flashing +======== + +V2M MPS2 provides: + +- A USB connection to the host computer, which exposes a Mass Storage and an + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +Flashing an application to V2M MPS2 +----------------------------------- + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mps2/an385 + :goals: build + +Connect the V2M MPS2 to your host computer using the USB port and you should +see a USB connection which exposes a Mass Storage and a USB Serial Port. +Copy the generated zephyr.bin in the exposed drive. +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! arm + + +.. _V2M MPS2 Website: + https://developer.mbed.org/platforms/ARM-MPS2/ + +.. _MPS2 Technical Reference Manual (TRM): + http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_05_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_05_en.pdf + +.. _Application Note AN385: + http://infocenter.arm.com/help/topic/com.arm.doc.dai0385c/DAI0385C_cortex_m3_on_v2m_mps2.pdf diff --git a/boards/arm/mps2/doc/mps2_an521.rst b/boards/arm/mps2/doc/mps2_an521.rst new file mode 100644 index 00000000000..7149902b0db --- /dev/null +++ b/boards/arm/mps2/doc/mps2_an521.rst @@ -0,0 +1,574 @@ +.. _mps2_an521_board: + +ARM MPS2+ AN521 +############### + +Overview +******** + +The mps2/an521 board configuration is used by Zephyr applications that run +on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33 +CPU and the following devices: + +- Nested Vectored Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) +- Cortex-M System Design Kit GPIO +- Cortex-M System Design Kit UART + +.. image:: img/mps2_an521.jpg + :align: center + :alt: ARM MPS2+ AN521 + +In addition to enabling actual hardware usage, this board configuration can +also use QEMU to emulate the AN521 platform running on the MPS2+. + +More information about the board can be found at the `MPS2 FPGA Website`_. + +.. note:: + This board configuration makes no claims about its suitability for use + with actual MPS2 hardware systems using AN521, or any other hardware + system. It has been tested on actual hardware, but its primary purpose is + for use with QEMU and unit tests for the ARM Cortex-M33. + + +Zephyr board options +==================== + +The MPS2+ AN521 is a dual core SoC with Cortex-M33 architecture on both cores +(CPU0 and CPU1). Zephyr provides support for building firmware +images for both CPU0 and CPU1. For CPU0 supporting ARM Security Extensions +both Secure and Non-Secure firmware images may be built. + +The BOARD options are summarized below: + ++----------------------+-------------------------------------------------------+ +| BOARD | Description | ++======================+=======================================================+ +| mps2/an521/cpu0 | For building Secure (or Secure-only) firmware on CPU0 | ++----------------------+-------------------------------------------------------+ +| mps2/an521/cpu0/ns | For building Non-Secure firmware for CPU0 | ++----------------------+-------------------------------------------------------+ +| mps2/an521/cpu1 | For building firmware on CPU1 | ++----------------------+-------------------------------------------------------+ + +Memory Partitioning +=================== + +The AN521 has 4MB allocated for code space, and 4MB for SRAM. These memory +regions are shared across both cores, and are aliased in both secure and +non-secure regions, where the secure memory alias has an offset of +0x10000000 relative to non-secure. + +The following memory map and partitioning schemes are used by default, where +the offset value is the offset from the base of the 4MB code or SRAM block, +ignoring the S/NS alias difference. + ++-------------------------+-----+----------------+----------------+------------+ +| Board | CPU | Code (Offset) | SRAM (Offset) | S/NS Alias | ++=========================+=====+================+================+============+ +| mps2/an521/cpu0 | 0 | 4MB (0) | 4MB (0) | S | ++-------------------------+-----+----------------+----------------+------------+ +| mps2/an521/cpu0/ns | 0 | 512KB (1MB) | 512KB (1MB) | NS | ++-------------------------+-----+----------------+----------------+------------+ +| mps2/an521/cpu1 | 1 | 468KB (3628KB) | 512KB (1.5MB) | NS | ++-------------------------+-----+----------------+----------------+------------+ + +The ``mps2/an521/cpu0/ns`` board target is intended to be used with TF-M, with the +Zephyr memory map matching the AN521 memory map defined upstream in TF-M. TF-M +boots the secure processing environment before initialising Zephyr in the +non-secure processing environment. The non-secure Zephyr image is offset to +make room for the secure bootloader, and the secure firmware (TF-M), resulting +in a starting address of 0x00100000. SRAM begins with a 1MB offset at +0x28100000. + +The ``mps2/an521/cpu1`` board target is setup for the second core on the +AN521, using the final 468KB code memory in the 4MB code block. This value +is chosen to maintain compatibility with TF-M, which marks that final 468KB +code region as ``Unused``. Code memory thus starts with an offset of +3628KB (address 0x0038B000), and sram starts with an offset of 1.5MB +(address 0x28180000). + +This memory map enables the two alternative board targets to be used together +if required, at the cost of reducing the amount of code memory available on +the second core to the worst-case scenario from TF-M. + +When using one of the alternative board targets (``mps2/an521/cpu0/ns`` or +``mps2/an521/cpu1``), care needs to be taken with the amount of code or +SRAM memory used on the primary board target (``mps2/an521``) since there is +some overlap in the memory maps. + +Hardware +******** + +ARM MPS2+ AN521 provides the following hardware components: + +- Dual core ARM Cortex-M33 +- Soft Macro Model (SMM) implementation of SSE-200 subsystem +- Memory + + - 4MB of code memory (SSRAM1) + - 4MB of SRAM (SSRAM2 and SSRAM3) + - 16MB of parallel SRAM (PSRAM, non-secure only) + - 8KB of NVM code + +- Debug + + - P-JTAG, SWD & 16-bit TRACE + - UART port + +- Interface + + - AHB GPIO connected to the EXP port + - UART + - SPI + - I2C + - I2S + - Color LCD serial interface + - Ethernet + - VGA + +- On-board Peripherals + + - Color LCD + - 8 LEDs + - 8 Switches + - External SSRAM1, SSRAM2 & SSRAM3 + - SMSC9220 + - CS42L52 + + +User push buttons +================= + +The mps2/an521 board provides the following user push buttons: + +- ON power on +- nSRST: Cortex-M33 system reset and CoreSight debug reset +- USERPB0 and USERPB1: User defined buttons + + +Supported Features +=================== + +The mps2/an521 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TIMER | on-chip | timer | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. +See the `MPS2 FPGA Website`_ for a complete list of MPS2+ AN521 board hardware +features. + +The default configuration can be found in +:zephyr_file:`boards/arm/mps2/mps2_an521_cpu0_defconfig`. + +Interrupt Controller +==================== + +MPS2+ AN521 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs. + +A Cortex-M33-based board uses vectored exceptions. This means each exception +calls a handler directly from the vector table. + +Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed +in the following table: + ++------+------------+----------------+--------------------------+ +| Exc# | Name | Remarks | Used by Zephyr Kernel | ++======+============+================+==========================+ +| 1 | Reset | | system initialization | ++------+------------+----------------+--------------------------+ +| 2 | NMI | | system fatal error | ++------+------------+----------------+--------------------------+ +| 3 | Hard fault | | system fatal error | ++------+------------+----------------+--------------------------+ +| 4 | MemManage | MPU fault | system fatal error | ++------+------------+----------------+--------------------------+ +| 5 | Bus | | system fatal error | ++------+------------+----------------+--------------------------+ +| 6 | Usage | Undefined | system fatal error | +| | fault | instruction, | | +| | | or switch | | +| | | attempt to ARM | | +| | | mode | | ++------+------------+----------------+--------------------------+ +| 7 | SecureFault| Unauthorized | system fatal error | +| | | access to | | +| | | secure region | | +| | | from ns space | | ++------+------------+----------------+--------------------------+ +| 8 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 9 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 10 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 11 | SVC | | system calls, kernel | +| | | | run-time exceptions, | +| | | | and IRQ offloading | ++------+------------+----------------+--------------------------+ +| 12 | Debug | | system fatal error | +| | monitor | | | ++------+------------+----------------+--------------------------+ +| 13 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 14 | PendSV | | context switch | ++------+------------+----------------+--------------------------+ +| 15 | SYSTICK | | system clock | ++------+------------+----------------+--------------------------+ +| 16 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 17 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 18 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ + +Pin Mapping +=========== + +The ARM MPS2+ AN521 Board has 4 CMSDK AHB GPIO controllers. Each providing 16 +bits of IO. These controllers are responsible for pin-muxing, input/output, +pull-up, etc. + +All GPIO controller pins are exposed via the following sequence of pin numbers: + +- Pins 0 - 15 are for GPIO0 +- Pins 16 - 31 are for GPIO1 +- Pins 32 - 47 are for GPIO2 +- Pins 48 - 51 are for GPIO3 + +Mapping from the ARM MPS2+ AN521 Board pins to GPIO controllers: + +.. rst-class:: rst-columns + + - D0 : EXT_0 + - D1 : EXT_4 + - D2 : EXT_2 + - D3 : EXT_3 + - D4 : EXT_1 + - D5 : EXT_6 + - D6 : EXT_7 + - D7 : EXT_8 + - D8 : EXT_9 + - D9 : EXT_10 + - D10 : EXT_12 + - D11 : EXT_13 + - D12 : EXT_14 + - D13 : EXT_11 + - D14 : EXT_15 + - D15 : EXT_5 + - D16 : EXT_16 + - D17 : EXT_17 + - D18 : EXT_18 + - D19 : EXT_19 + - D20 : EXT_20 + - D21 : EXT_21 + - D22 : EXT_22 + - D23 : EXT_23 + - D24 : EXT_24 + - D25 : EXT_25 + - D26 : EXT_26 + - D27 : EXT_30 + - D28 : EXT_28 + - D29 : EXT_29 + - D30 : EXT_27 + - D31 : EXT_32 + - D32 : EXT_33 + - D33 : EXT_34 + - D34 : EXT_35 + - D35 : EXT_36 + - D36 : EXT_38 + - D37 : EXT_39 + - D38 : EXT_40 + - D39 : EXT_44 + - D40 : EXT_41 + - D41 : EXT_31 + - D42 : EXT_37 + - D43 : EXT_42 + - D44 : EXT_43 + - D45 : EXT_45 + - D46 : EXT_46 + - D47 : EXT_47 + - D48 : EXT_48 + - D49 : EXT_49 + - D50 : EXT_50 + - D51 : EXT_51 + +Peripheral Mapping: + +.. rst-class:: rst-columns + + - UART_3_RX : D0 + - UART_3_TX : D1 + - SPI_3_CS : D10 + - SPI_3_MOSI : D11 + - SPI_3_MISO : D12 + - SPI_3_SCLK : D13 + - I2C_3_SDA : D14 + - I2C_3_SCL : D15 + - UART_4_RX : D26 + - UART_4_TX : D30 + - SPI_4_CS : D36 + - SPI_4_MOSI : D37 + - SPI_4_MISO : D38 + - SPI_4_SCK : D39 + - I2C_4_SDA : D40 + - I2C_4_SCL : D41 + +For more details refer to `MPS2+ AN521 Technical Reference Manual (TRM)`_. + +LED +============ + +MPS2+ has 8 built-in LEDs connected to Serial Configuration Controller (SCC). + +.. note:: The SCC register CFG_REG1 Bits [7:0] for LEDa, 0 = OFF 1 = ON. + +System Clock +============ + +MPS2+ AN521 has several clocks connected: + +.. rst-class:: rst-columns + + - MAINCLK : 20MHz + - SYSCLK : 20MHz + - S32KCLK : 32kHz + - TRACECLK : 20MHz + - SWCLKTCK : 20MHz + - TRACECLKIN : 20MHz + +Serial Port +=========== + +The MPS2+ AN521 has five UARTs. The Zephyr console output by default, uses +UART0, which is J10 on the board. + +UART2 is reserved. And UART 1, 3 and 4 are alt-functions on the EXP ports. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is used to define + secure and non-secure memory maps. By default, all of the memory space is + defined to be secure accessible only +- Secure and Non-secure peripherals via the Peripheral Protection Controller + (PPC). Peripherals can be assigned as secure or non-secure accessible +- Secure boot +- Secure `AMBA®`_ interconnect + +Serial Configuration Controller (SCC) +===================================== + +The MPS2+ AN521 implements a Serial Configuration Control (SCC) register. +The purpose of this register is to allow individual control of clocks, +reset-signals and interrupts to peripherals, and pin-muxing, and the LEDs and +switches. + +Programming and Debugging +************************* + +MPS2+ AN521 (CPU0) supports the Armv8m Security Extension. +Applications built for the mps2/an521 board by default +boot in the Secure state. + +MPS2+ AN521 (CPU1) does not support the Armv8m Security Extension. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the MPS2+ AN521 (CPU0) may contain a Secure and a Non-Secure +firmware image. The Secure image can be built using either Zephyr +or `Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built +using Zephyr. The two alternatives are described below. + +.. note:: + + By default the Secure image for the MPS2+ AN521 (CPU0) is built + using TF-M. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the Non-Secure +firmware image using Zephyr requires the following steps: + +1. Build the Non-Secure Zephyr application + for MPS2+ AN521 (CPU0) using ``-DBOARD=mps2/an521/cpu0/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output image binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may be + required, to adjust the Non-Secure image Flash and SRAM starting address + and sizes. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process to build the Secure and the Non-Secure firmware images +using Zephyr requires the following steps: + +1. Build the Secure Zephyr application for MPS2+ AN521 (CPU0) + using ``-DBOARD=mps2/an521`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` + in the application project configuration file. +2. Build the Non-Secure Zephyr application for MPS2+ AN521 (CPU0) + using ``-DBOARD=mps2/an521/cpu0/ns``. +3. Merge the two binaries together. + +Building a Secure only application on MPS2+ AN521 (CPU0) +======================================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=mps2/an521`` for +the firmware running on the MPS2+ AN521 (CPU0). + +When building a Secure/Non-Secure application for the MPS2+ AN521 (CPU0), +the Secure application will have to set the SAU/IDAU configuration to allow +Non-Secure access to all CPU resources utilized by the Non-Secure application +firmware. SAU/IDAU configuration shall take place before jumping to the +Non-Secure application. + +The following system components are required to be properly configured during the +secure firmware: + +- AHB5 TrustZone Memory Protection Controller (MPC) +- AHB5 TrustZone Peripheral Protection Controller (PPC) +- Implementation-Defined Attribution Unit (IDAU) + +For more details refer to `Corelink SSE-200 Subsystem`_. + + + +Building standalone applications on MPS2+ AN521 CPU1 +==================================================== + +Applications may be built for the second Cortex-M33 +(remote) core of MPS2+ AN521. The core is referred to as CPU1. + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=mps2/an521/cpu1`` for +the firmware running on the MPS2+ AN521 (CPU1). + +The Zephyr build will automatically trigger building a minimal (empty) +secure-only firmware for CPU0, which will be used to boot the remote +core (CPU1). + + +Flashing +======== + +MPS2+ AN521 provides: + +- A USB connection to the host computer, which exposes a Mass Storage +- A Serial Port which is J10 on MPS2+ board + +Build applications as described above. +Here is an example for the :ref:`hello_world` application built as +a secure-only application for CPU0. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mps2/an521 + :goals: build + + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board, and you should see the following message on the corresponding +serial port: + +.. code-block:: console + + Hello World! mps2_an521 + + +Uploading an application to MPS2+ AN521 +--------------------------------------- + +Applications can be in elf, hex or bin format. The binaries are flashed when +the board boots up, using files stored on the on-board Micro SD card. The +Motherboard Configuration Controller (MCC) is responsible for loading the FPGA +image and binaries. + +Connect the MPS2+ to your host computer using the USB port. You should see a +USB connection exposing a Mass Storage (``V2M_MPS2`` by default). + +The update requires 3 steps: + +1. Copy application files to ``/SOFTWARE/``. +2. Open ``/MB/HBI0263C/AN521/images.txt``. +3. Update the ``AN521/images.txt`` file as follows: + +.. code-block:: bash + + TITLE: Versatile Express Images Configuration File + + [IMAGES] + TOTALIMAGES: 1 ;Number of Images (Max: 32) + + IMAGE0ADDRESS: 0x10000000 ;Please select the required executable program + + IMAGE0FILE: \SOFTWARE\zephyr.bin + + +Reset the board, and you should see the following message on the corresponding +serial port: + +.. code-block:: console + + Hello World! mps2_an521 + +.. note:: Refer to the tfm_integration sample for more details about integrating with TF-M and multiple images scenario. + + +.. _MPS2 FPGA Website: + https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps2 + +.. _MPS2+ AN521 Technical Reference Manual (TRM): + https://developer.arm.com/documentation/dai0521/latest/ + +.. _Cortex M33 Generic User Guide: + https://developer.arm.com/documentation/100235/latest/ + +.. _Trusted Firmware M: + https://tf-m-user-guide.trustedfirmware.org/building/tfm_build_instruction.html + +.. _Corelink SSE-200 Subsystem: + https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200 + +.. _IDAU: + https://developer.arm.com/documentation/100690/latest/Attribution-units--SAU-and-IDAU- + +.. _AMBA®: + https://developer.arm.com/products/architecture/system-architectures/amba diff --git a/boards/arm/mps2_an521/empty_cpu0/CMakeLists.txt b/boards/arm/mps2/empty_cpu0/CMakeLists.txt similarity index 100% rename from boards/arm/mps2_an521/empty_cpu0/CMakeLists.txt rename to boards/arm/mps2/empty_cpu0/CMakeLists.txt diff --git a/boards/arm/mps2_an521/empty_cpu0/prj.conf b/boards/arm/mps2/empty_cpu0/prj.conf similarity index 100% rename from boards/arm/mps2_an521/empty_cpu0/prj.conf rename to boards/arm/mps2/empty_cpu0/prj.conf diff --git a/boards/arm/mps2_an521/empty_cpu0/src/main.c b/boards/arm/mps2/empty_cpu0/src/main.c similarity index 100% rename from boards/arm/mps2_an521/empty_cpu0/src/main.c rename to boards/arm/mps2/empty_cpu0/src/main.c diff --git a/boards/arm/mps2_an385/mps2_an385.dts b/boards/arm/mps2/mps2_an385.dts similarity index 100% rename from boards/arm/mps2_an385/mps2_an385.dts rename to boards/arm/mps2/mps2_an385.dts diff --git a/boards/arm/mps2_an385/mps2_an385.yaml b/boards/arm/mps2/mps2_an385.yaml similarity index 89% rename from boards/arm/mps2_an385/mps2_an385.yaml rename to boards/arm/mps2/mps2_an385.yaml index 0236f2a137d..7ad92b98996 100644 --- a/boards/arm/mps2_an385/mps2_an385.yaml +++ b/boards/arm/mps2/mps2_an385.yaml @@ -1,4 +1,4 @@ -identifier: mps2_an385 +identifier: mps2/an385 name: ARM V2M MPS2 type: mcu arch: arm diff --git a/boards/arm/mps2_an385/mps2_an385_defconfig b/boards/arm/mps2/mps2_an385_defconfig similarity index 75% rename from boards/arm/mps2_an385/mps2_an385_defconfig rename to boards/arm/mps2/mps2_an385_defconfig index a3233418953..1d55b8fe949 100644 --- a/boards/arm/mps2_an385/mps2_an385_defconfig +++ b/boards/arm/mps2/mps2_an385_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_MPS2=y -CONFIG_SOC_MPS2_AN385=y -CONFIG_BOARD_MPS2_AN385=y CONFIG_RUNTIME_NMI=y CONFIG_QEMU_ICOUNT_SHIFT=7 diff --git a/boards/arm/mps2_an521/mps2_an521-common.dtsi b/boards/arm/mps2/mps2_an521-common.dtsi similarity index 100% rename from boards/arm/mps2_an521/mps2_an521-common.dtsi rename to boards/arm/mps2/mps2_an521-common.dtsi diff --git a/boards/arm/mps2_an521/mps2_an521.dts b/boards/arm/mps2/mps2_an521_cpu0.dts similarity index 100% rename from boards/arm/mps2_an521/mps2_an521.dts rename to boards/arm/mps2/mps2_an521_cpu0.dts diff --git a/boards/arm/mps2/mps2_an521_cpu0.yaml b/boards/arm/mps2/mps2_an521_cpu0.yaml new file mode 100644 index 00000000000..e5247a292e5 --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu0.yaml @@ -0,0 +1,21 @@ +identifier: mps2/an521/cpu0 +name: ARM V2M MPS2-AN521 +type: mcu +arch: arm +ram: 4096 +flash: 4096 +simulation: qemu +toolchain: + - gnuarmemb + - zephyr + - xtools +supported: + - gpio +testing: + default: true + ignore_tags: + - drivers + - bluetooth + - net + - timer +vendor: arm diff --git a/boards/arm/mps2/mps2_an521_cpu0_defconfig b/boards/arm/mps2/mps2_an521_cpu0_defconfig new file mode 100644 index 00000000000..413c8cdc5c3 --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu0_defconfig @@ -0,0 +1,21 @@ +# +# Copyright (c) 2018-2019 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y +CONFIG_QEMU_ICOUNT_SHIFT=7 + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arm/mps2_an521/mps2_an521_ns.dts b/boards/arm/mps2/mps2_an521_cpu0_ns.dts similarity index 100% rename from boards/arm/mps2_an521/mps2_an521_ns.dts rename to boards/arm/mps2/mps2_an521_cpu0_ns.dts diff --git a/boards/arm/mps2/mps2_an521_cpu0_ns.yaml b/boards/arm/mps2/mps2_an521_cpu0_ns.yaml new file mode 100644 index 00000000000..b5dcadf7fe9 --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu0_ns.yaml @@ -0,0 +1,19 @@ +identifier: mps2/an521/cpu0/ns +name: ARM V2M MPS2-AN521_ns +type: mcu +arch: arm +ram: 512 +flash: 512 +simulation: qemu +toolchain: + - gnuarmemb + - zephyr + - xtools +testing: + default: true + only_tags: + - arm + - kernel + - tfm + - userspace + - trusted-firmware-m diff --git a/boards/arm/mps2/mps2_an521_cpu0_ns_defconfig b/boards/arm/mps2/mps2_an521_cpu0_ns_defconfig new file mode 100644 index 00000000000..7c02187aaef --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu0_ns_defconfig @@ -0,0 +1,11 @@ +# +# Copyright (c) 2018-2019 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_QEMU_ICOUNT_SHIFT=6 + +# Build a non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/mps2_an521/mps2_an521_remote.dts b/boards/arm/mps2/mps2_an521_cpu1.dts similarity index 100% rename from boards/arm/mps2_an521/mps2_an521_remote.dts rename to boards/arm/mps2/mps2_an521_cpu1.dts diff --git a/boards/arm/mps2/mps2_an521_cpu1.yaml b/boards/arm/mps2/mps2_an521_cpu1.yaml new file mode 100644 index 00000000000..29bd722157b --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu1.yaml @@ -0,0 +1,16 @@ +identifier: mps2/an521/cpu1 +name: ARM V2M MPS2-AN521_cpu1 +type: mcu +arch: arm +ram: 512 +flash: 468 +simulation: qemu +toolchain: + - gnuarmemb + - zephyr + - xtools +testing: + default: true + only_tags: + - arm + - fpu diff --git a/boards/arm/mps2/mps2_an521_cpu1_defconfig b/boards/arm/mps2/mps2_an521_cpu1_defconfig new file mode 100644 index 00000000000..0c8740a2fb9 --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu1_defconfig @@ -0,0 +1,18 @@ +# +# Copyright (c) 2018-2019 Linaro Limited +# Copyright (c) 2021 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_MPU=y +CONFIG_QEMU_ICOUNT_SHIFT=7 + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/mps2_an385/pinmux.c b/boards/arm/mps2/pinmux.c similarity index 100% rename from boards/arm/mps2_an385/pinmux.c rename to boards/arm/mps2/pinmux.c diff --git a/boards/arm/mps2_an385/CMakeLists.txt b/boards/arm/mps2_an385/CMakeLists.txt deleted file mode 100644 index 9bc25bae4c6..00000000000 --- a/boards/arm/mps2_an385/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(pinmux.c) diff --git a/boards/arm/mps2_an385/Kconfig.board b/boards/arm/mps2_an385/Kconfig.board deleted file mode 100644 index f2f9be26f50..00000000000 --- a/boards/arm/mps2_an385/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MPS2_AN385 - bool "ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)" - depends on SOC_MPS2_AN385 - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT diff --git a/boards/arm/mps2_an385/Kconfig.defconfig b/boards/arm/mps2_an385/Kconfig.defconfig deleted file mode 100644 index 114e5d6dbf3..00000000000 --- a/boards/arm/mps2_an385/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MPS2_AN385 - -config BOARD - default "mps2_an385" - -if SERIAL - -config UART_INTERRUPT_DRIVEN - default y - -endif # SERIAL - -config ZTEST_STACK_SIZE - default 4096 if ZTEST - -if COVERAGE_GCOV - -config MAIN_STACK_SIZE - default 4096 - -config IDLE_STACK_SIZE - default 4096 - -config PRIVILEGED_STACK_SIZE - default 4096 - -config ISR_STACK_SIZE - default 4096 - -config TEST_EXTRA_STACK_SIZE - default 4096 - -endif # COVERAGE_GCOV - -endif diff --git a/boards/arm/mps2_an385/board.cmake b/boards/arm/mps2_an385/board.cmake deleted file mode 100644 index 1f2d4957d66..00000000000 --- a/boards/arm/mps2_an385/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_CPU_TYPE_${ARCH} cortex-m3) -set(QEMU_FLAGS_${ARCH} - -cpu ${QEMU_CPU_TYPE_${ARCH}} - -machine mps2-an385 - -nographic - -vga none - ) - -board_set_debugger_ifnset(qemu) diff --git a/boards/arm/mps2_an385/doc/index.rst b/boards/arm/mps2_an385/doc/index.rst deleted file mode 100644 index ac27e70e593..00000000000 --- a/boards/arm/mps2_an385/doc/index.rst +++ /dev/null @@ -1,284 +0,0 @@ -.. _mps2_an385_board: - -ARM V2M MPS2 -############ - -Overview -******** - -The mps2_an385 board configuration is used by Zephyr applications that run on -the V2M MPS2 board. It provides support for the ARM Cortex-M3 (AN385) CPU and -the following devices: - -- Nested Vectored Interrupt Controller (NVIC) -- System Tick System Clock (SYSTICK) -- Cortex-M System Design Kit UART - -.. image:: img/mps2_an385.jpg - :align: center - :alt: ARM V2M MPS2 - -In addition to enabling actual hardware usage, this board configuration can -also use QEMU to emulate the AN385 platform running on the MPS2+. - -More information about the board can be found at the `V2M MPS2 Website`_. - -The Application Note AN385 can be found at `Application Note AN385`_. - -.. note:: - This board configuration makes no claims about its suitability for use - with actual MPS2 hardware systems using AN385, or any other hardware - system. It has been tested on actual hardware, but its primary purpose is - for use with QEMU and unit tests. - -Hardware -******** - -ARM V2M MPS2 provides the following hardware components: - -- ARM Cortex-M3 (AN385) -- ARM IoT Subsystem for Cortex-M -- Form factor: 140x120cm -- ZBTSRAM: 8MB single cycle SRAM, 16MB PSRAM -- Video: QSVGA touch screen panel, 4bit RGB VGA connector -- Audio: Audio Codec -- Debug: - - - ARM JTAG20 connector - - ARM parallel trace connector (MICTOR38) - - 20 pin Cortex debug connector - - 10 pin Cortex debug connector - - ILA connector for FPGA debug - -- Expansion - - - GPIO - - SPI - -.. note:: - 4 MB of flash memory (in ZBTSRAM 1, starting at address 0x00400000) and 4 MB of RAM - (in ZBTSRAM 2 & 3, starting at address 0x20000000) are available. - -Supported Features -================== - -The mps2_an385 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| DUALTIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware -features. - -The default configuration can be found in the defconfig file: - -.. code-block:: console - - boards/arm/mps2_an385/mps2_an385_defconfig - -Interrupt Controller -==================== - -MPS2 is a Cortex-M3 based SoC and has 15 fixed exceptions and 45 IRQs. - -A Cortex-M3/4-based board uses vectored exceptions. This means each exception -calls a handler directly from the vector table. - -Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here -identifies the handlers used for each exception. - -+------+------------+----------------+--------------------------+ -| Exc# | Name | Remarks | Used by Zephyr Kernel | -+======+============+================+==========================+ -| 1 | Reset | | system initialization | -+------+------------+----------------+--------------------------+ -| 2 | NMI | | system fatal error | -+------+------------+----------------+--------------------------+ -| 3 | Hard fault | | system fatal error | -+------+------------+----------------+--------------------------+ -| 4 | MemManage | MPU fault | system fatal error | -+------+------------+----------------+--------------------------+ -| 5 | Bus | | system fatal error | -+------+------------+----------------+--------------------------+ -| 6 | Usage | undefined | system fatal error | -| | fault | instruction, | | -| | | or switch | | -| | | attempt to ARM | | -| | | mode | | -+------+------------+----------------+--------------------------+ -| 11 | SVC | | system calls, kernel | -| | | | run-time exceptions, | -| | | | and IRQ offloading | -+------+------------+----------------+--------------------------+ -| 12 | Debug | | system fatal error | -| | monitor | | | -+------+------------+----------------+--------------------------+ -| 14 | PendSV | | context switch | -+------+------------+----------------+--------------------------+ -| 15 | SYSTICK | | system clock | -+------+------------+----------------+--------------------------+ - -Pin Mapping -=========== - -The ARM V2M MPS2 Board has 4 GPIO controllers. These controllers are responsible -for pin muxing, input/output, pull-up, etc. - -All GPIO controller pins are exposed via the following sequence of pin numbers: - -- Pins 0 - 15 are for GPIO 0 -- Pins 16 - 31 are for GPIO 1 -- Pins 32 - 47 are for GPIO 2 -- Pins 48 - 51 are for GPIO 3 - -Mapping from the ARM MPS2 Board pins to GPIO controllers: - -.. rst-class:: rst-columns - - - D0 : EXT_0 - - D1 : EXT_4 - - D2 : EXT_2 - - D3 : EXT_3 - - D4 : EXT_1 - - D5 : EXT_6 - - D6 : EXT_7 - - D7 : EXT_8 - - D8 : EXT_9 - - D9 : EXT_10 - - D10 : EXT_12 - - D11 : EXT_13 - - D12 : EXT_14 - - D13 : EXT_11 - - D14 : EXT_15 - - D15 : EXT_5 - - D16 : EXT_16 - - D17 : EXT_17 - - D18 : EXT_18 - - D19 : EXT_19 - - D20 : EXT_20 - - D21 : EXT_21 - - D22 : EXT_22 - - D23 : EXT_23 - - D24 : EXT_24 - - D25 : EXT_25 - - D26 : EXT_26 - - D27 : EXT_30 - - D28 : EXT_28 - - D29 : EXT_29 - - D30 : EXT_27 - - D31 : EXT_32 - - D32 : EXT_33 - - D33 : EXT_34 - - D34 : EXT_35 - - D35 : EXT_36 - - D36 : EXT_38 - - D37 : EXT_39 - - D38 : EXT_40 - - D39 : EXT_44 - - D40 : EXT_41 - - D41 : EXT_31 - - D42 : EXT_37 - - D43 : EXT_42 - - D44 : EXT_43 - - D45 : EXT_45 - - D46 : EXT_46 - - D47 : EXT_47 - - D48 : EXT_48 - - D49 : EXT_49 - - D50 : EXT_50 - - D51 : EXT_51 - -Peripheral Mapping: - -.. rst-class:: rst-columns - - - UART_3_RX : D0 - - UART_3_TX : D1 - - SPI_3_CS : D10 - - SPI_3_MOSI : D11 - - SPI_3_MISO : D12 - - SPI_3_SCLK : D13 - - I2C_3_SDA : D14 - - I2C_3_SCL : D15 - - UART_4_RX : D26 - - UART_4_TX : D30 - - SPI_4_CS : D36 - - SPI_4_MOSI : D37 - - SPI_4_MISO : D38 - - SPI_4_SCK : D39 - - I2C_4_SDA : D40 - - I2C_4_SCL : D41 - -For more details please refer to `MPS2 Technical Reference Manual (TRM)`_. - -System Clock -============ - -The V2M MPS2 main clock is 24 MHz. - -Serial Port -=========== - -The V2M MPS2 processor has five UARTs. Both the UARTs have only two wires for -RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by -default, is utilizing UART0. - -Programming and Debugging -************************* - -Flashing -======== - -V2M MPS2 provides: - -- A USB connection to the host computer, which exposes a Mass Storage and an - USB Serial Port. -- A Serial Flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB Serial port. - -Flashing an application to V2M MPS2 ------------------------------------ - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mps2_an385 - :goals: build - -Connect the V2M MPS2 to your host computer using the USB port and you should -see a USB connection which exposes a Mass Storage and a USB Serial Port. -Copy the generated zephyr.bin in the exposed drive. -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! arm - - -.. _V2M MPS2 Website: - https://developer.mbed.org/platforms/ARM-MPS2/ - -.. _MPS2 Technical Reference Manual (TRM): - http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_05_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_05_en.pdf - -.. _Application Note AN385: - http://infocenter.arm.com/help/topic/com.arm.doc.dai0385c/DAI0385C_cortex_m3_on_v2m_mps2.pdf diff --git a/boards/arm/mps2_an521/CMakeLists.txt b/boards/arm/mps2_an521/CMakeLists.txt deleted file mode 100644 index 7f691784274..00000000000 --- a/boards/arm/mps2_an521/CMakeLists.txt +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright (c) 2019,2020 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_library() -zephyr_library_sources(pinmux.c) - -if(CONFIG_SOC_MPS2_AN521_CPU1 AND NOT CONFIG_OPENAMP) -# Building a firmware image for CPU1: this requires a binary -# for CPU0, which will boot the device and wake up CPU1. -# However, if building with OPENAMP, there is no need to build -# any binary for CPU0, as this is built by the dual core sample. - - set(CPU0_BINARY_DIR ${BOARD_DIR}/empty_cpu0-prefix/src/empty-cpu0-build/zephyr) - - include(ExternalProject) - - ExternalProject_Add( - empty_cpu0 - SOURCE_DIR ${BOARD_DIR}/empty_cpu0 - INSTALL_COMMAND "" - CMAKE_CACHE_ARGS -DBOARD:STRING=mps2_an521 - BUILD_BYPRODUCTS "${CPU0_BINARY_DIR}/${KERNEL_BIN_NAME}" - BUILD_ALWAYS True - ) - -endif() diff --git a/boards/arm/mps2_an521/Kconfig.board b/boards/arm/mps2_an521/Kconfig.board deleted file mode 100644 index 6fff4bd21f5..00000000000 --- a/boards/arm/mps2_an521/Kconfig.board +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2018-2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MPS2_AN521_CPU0 - bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) (CPU0)" - depends on SOC_MPS2_AN521_CPU0 - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - -config BOARD_MPS2_AN521_CPU0_NS - bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) (CPU0 Non-Secure)" - depends on SOC_MPS2_AN521_CPU0 - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - -config BOARD_MPS2_AN521_CPU1 - bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) CPU1" - depends on SOC_MPS2_AN521_CPU1 - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT diff --git a/boards/arm/mps2_an521/Kconfig.defconfig b/boards/arm/mps2_an521/Kconfig.defconfig deleted file mode 100644 index ff999de1841..00000000000 --- a/boards/arm/mps2_an521/Kconfig.defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2018-2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MPS2_AN521_CPU0 || BOARD_MPS2_AN521_CPU0_NS || BOARD_MPS2_AN521_CPU1 - -# MPU-based null-pointer dereferencing detection cannot -# be applied as the (0x0 - 0x400) is unmapped but QEMU -# will still permit bus access. -choice NULL_POINTER_EXCEPTION_DETECTION - bool - default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET -endchoice - -config BOARD - default "mps2_an521_ns" if TRUSTED_EXECUTION_NONSECURE - default "mps2_an521_remote" if BOARD_MPS2_AN521_CPU1 - default "mps2_an521" - -# By default, if we build for a Non-Secure version of the board, -# force building with TF-M as the Secure Execution Environment. -config BUILD_WITH_TFM - default y if TRUSTED_EXECUTION_NONSECURE - - -if SERIAL - -config UART_INTERRUPT_DRIVEN - default y - -endif # SERIAL - -endif diff --git a/boards/arm/mps2_an521/board.cmake b/boards/arm/mps2_an521/board.cmake deleted file mode 100644 index 51e09ba282d..00000000000 --- a/boards/arm/mps2_an521/board.cmake +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_CPU_TYPE_${ARCH} cortex-m33) -set(QEMU_FLAGS_${ARCH} - -cpu ${QEMU_CPU_TYPE_${ARCH}} - -machine mps2-an521 - -nographic - -m 16 - -vga none - ) -board_set_debugger_ifnset(qemu) - -board_runner_args(pyocd "--target=mps2_an521") - -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) - # To enable a host tty switch between serial and pty - # -chardev serial,path=/dev/ttyS0,id=hostS0 -list(APPEND QEMU_EXTRA_FLAGS -chardev pty,id=hostS0 -serial chardev:hostS0) - -if (CONFIG_BUILD_WITH_TFM) - # Override the binary used by qemu, to use the combined - # TF-M (Secure) & Zephyr (Non Secure) image (when running - # in-tree tests). - set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex") -elseif(CONFIG_OPENAMP) - set(QEMU_EXTRA_FLAGS "-device;loader,file=${REMOTE_ZEPHYR_DIR}/zephyr.elf") -elseif (CONFIG_SOC_MPS2_AN521_CPU1) - set(CPU0_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}/zephyr/boards/arm/mps2_an521/empty_cpu0-prefix/src/empty_cpu0-build/zephyr) - set(QEMU_KERNEL_OPTION "-device;loader,file=${CPU0_BINARY_DIR}/zephyr.elf") - list(APPEND QEMU_EXTRA_FLAGS "-device;loader,file=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}") -endif() diff --git a/boards/arm/mps2_an521/doc/index.rst b/boards/arm/mps2_an521/doc/index.rst deleted file mode 100644 index e8789e72e18..00000000000 --- a/boards/arm/mps2_an521/doc/index.rst +++ /dev/null @@ -1,574 +0,0 @@ -.. _mps2_an521_board: - -ARM MPS2+ AN521 -############### - -Overview -******** - -The mps2_an521 board configuration is used by Zephyr applications that run -on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33 -CPU and the following devices: - -- Nested Vectored Interrupt Controller (NVIC) -- System Tick System Clock (SYSTICK) -- Cortex-M System Design Kit GPIO -- Cortex-M System Design Kit UART - -.. image:: img/mps2_an521.jpg - :align: center - :alt: ARM MPS2+ AN521 - -In addition to enabling actual hardware usage, this board configuration can -also use QEMU to emulate the AN521 platform running on the MPS2+. - -More information about the board can be found at the `MPS2 FPGA Website`_. - -.. note:: - This board configuration makes no claims about its suitability for use - with actual MPS2 hardware systems using AN521, or any other hardware - system. It has been tested on actual hardware, but its primary purpose is - for use with QEMU and unit tests for the ARM Cortex-M33. - - -Zephyr board options -==================== - -The MPS2+ AN521 is a dual core SoC with Cortex-M33 architecture on both cores -(CPU0 and CPU1). Zephyr provides support for building firmware -images for both CPU0 and CPU1. For CPU0 supporting ARM Security Extensions -both Secure and Non-Secure firmware images may be built. - -The BOARD options are summarized below: - -+----------------------+-------------------------------------------------------+ -| BOARD | Description | -+======================+=======================================================+ -| mps2_an521 | For building Secure (or Secure-only) firmware on CPU0 | -+----------------------+-------------------------------------------------------+ -| mps2_an521_ns | For building Non-Secure firmware for CPU0 | -+----------------------+-------------------------------------------------------+ -| mps2_an521_remote | For building firmware on CPU1 | -+----------------------+-------------------------------------------------------+ - -Memory Partitioning -=================== - -The AN521 has 4MB allocated for code space, and 4MB for SRAM. These memory -regions are shared across both cores, and are aliased in both secure and -non-secure regions, where the secure memory alias has an offset of -0x10000000 relative to non-secure. - -The following memory map and partitioning schemes are used by default, where -the offset value is the offset from the base of the 4MB code or SRAM block, -ignoring the S/NS alias difference. - -+-------------------+-----+----------------+----------------+------------+ -| Board | CPU | Code (Offset) | SRAM (Offset) | S/NS Alias | -+===================+=====+================+================+============+ -| mps2_an521 | 0 | 4MB (0) | 4MB (0) | S | -+-------------------+-----+----------------+----------------+------------+ -| mps2_an521_ns | 0 | 512KB (1MB) | 512KB (1MB) | NS | -+-------------------+-----+----------------+----------------+------------+ -| mps2_an521_remote | 1 | 468KB (3628KB) | 512KB (1.5MB) | NS | -+-------------------+-----+----------------+----------------+------------+ - -The ``mps2_an521_ns`` board target is intended to be used with TF-M, with the -Zephyr memory map matching the AN521 memory map defined upstream in TF-M. TF-M -boots the secure processing environment before initialising Zephyr in the -non-secure processing environment. The non-secure Zephyr image is offset to -make room for the secure bootloader, and the secure firmware (TF-M), resulting -in a starting address of 0x00100000. SRAM begins with a 1MB offset at -0x28100000. - -The ``mps2_an521_remote`` board target is setup for the second core on the -AN521, using the final 468KB code memory in the 4MB code block. This value -is chosen to maintain compatibility with TF-M, which marks that final 468KB -code region as ``Unused``. Code memory thus starts with an offset of -3628KB (address 0x0038B000), and sram starts with an offset of 1.5MB -(address 0x28180000). - -This memory map enables the two alternative board targets to be used together -if required, at the cost of reducing the amount of code memory available on -the second core to the worst-case scenario from TF-M. - -When using one of the alternative board targets (``mps2_an521_ns`` or -``mps2_an521_remote``), care needs to be taken with the amount of code or -SRAM memory used on the primary board target (``mps2_an521``) since there is -some overlap in the memory maps. - -Hardware -******** - -ARM MPS2+ AN521 provides the following hardware components: - -- Dual core ARM Cortex-M33 -- Soft Macro Model (SMM) implementation of SSE-200 subsystem -- Memory - - - 4MB of code memory (SSRAM1) - - 4MB of SRAM (SSRAM2 and SSRAM3) - - 16MB of parallel SRAM (PSRAM, non-secure only) - - 8KB of NVM code - -- Debug - - - P-JTAG, SWD & 16-bit TRACE - - UART port - -- Interface - - - AHB GPIO connected to the EXP port - - UART - - SPI - - I2C - - I2S - - Color LCD serial interface - - Ethernet - - VGA - -- On-board Peripherals - - - Color LCD - - 8 LEDs - - 8 Switches - - External SSRAM1, SSRAM2 & SSRAM3 - - SMSC9220 - - CS42L52 - - -User push buttons -================= - -The mps2_an521 board provides the following user push buttons: - -- ON power on -- nSRST: Cortex-M33 system reset and CoreSight debug reset -- USERPB0 and USERPB1: User defined buttons - - -Supported Features -=================== - -The mps2_an521 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | timer | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `MPS2 FPGA Website`_ for a complete list of MPS2+ AN521 board hardware -features. - -The default configuration can be found in the defconfig file: -``boards/arm/mps2_an521/mps2_an521_defconfig``. - -Interrupt Controller -==================== - -MPS2+ AN521 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs. - -A Cortex-M33-based board uses vectored exceptions. This means each exception -calls a handler directly from the vector table. - -Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed -in the following table: - -+------+------------+----------------+--------------------------+ -| Exc# | Name | Remarks | Used by Zephyr Kernel | -+======+============+================+==========================+ -| 1 | Reset | | system initialization | -+------+------------+----------------+--------------------------+ -| 2 | NMI | | system fatal error | -+------+------------+----------------+--------------------------+ -| 3 | Hard fault | | system fatal error | -+------+------------+----------------+--------------------------+ -| 4 | MemManage | MPU fault | system fatal error | -+------+------------+----------------+--------------------------+ -| 5 | Bus | | system fatal error | -+------+------------+----------------+--------------------------+ -| 6 | Usage | Undefined | system fatal error | -| | fault | instruction, | | -| | | or switch | | -| | | attempt to ARM | | -| | | mode | | -+------+------------+----------------+--------------------------+ -| 7 | SecureFault| Unauthorized | system fatal error | -| | | access to | | -| | | secure region | | -| | | from ns space | | -+------+------------+----------------+--------------------------+ -| 8 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 9 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 10 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 11 | SVC | | system calls, kernel | -| | | | run-time exceptions, | -| | | | and IRQ offloading | -+------+------------+----------------+--------------------------+ -| 12 | Debug | | system fatal error | -| | monitor | | | -+------+------------+----------------+--------------------------+ -| 13 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 14 | PendSV | | context switch | -+------+------------+----------------+--------------------------+ -| 15 | SYSTICK | | system clock | -+------+------------+----------------+--------------------------+ -| 16 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 17 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 18 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ - -Pin Mapping -=========== - -The ARM MPS2+ AN521 Board has 4 CMSDK AHB GPIO controllers. Each providing 16 -bits of IO. These controllers are responsible for pin-muxing, input/output, -pull-up, etc. - -All GPIO controller pins are exposed via the following sequence of pin numbers: - -- Pins 0 - 15 are for GPIO0 -- Pins 16 - 31 are for GPIO1 -- Pins 32 - 47 are for GPIO2 -- Pins 48 - 51 are for GPIO3 - -Mapping from the ARM MPS2+ AN521 Board pins to GPIO controllers: - -.. rst-class:: rst-columns - - - D0 : EXT_0 - - D1 : EXT_4 - - D2 : EXT_2 - - D3 : EXT_3 - - D4 : EXT_1 - - D5 : EXT_6 - - D6 : EXT_7 - - D7 : EXT_8 - - D8 : EXT_9 - - D9 : EXT_10 - - D10 : EXT_12 - - D11 : EXT_13 - - D12 : EXT_14 - - D13 : EXT_11 - - D14 : EXT_15 - - D15 : EXT_5 - - D16 : EXT_16 - - D17 : EXT_17 - - D18 : EXT_18 - - D19 : EXT_19 - - D20 : EXT_20 - - D21 : EXT_21 - - D22 : EXT_22 - - D23 : EXT_23 - - D24 : EXT_24 - - D25 : EXT_25 - - D26 : EXT_26 - - D27 : EXT_30 - - D28 : EXT_28 - - D29 : EXT_29 - - D30 : EXT_27 - - D31 : EXT_32 - - D32 : EXT_33 - - D33 : EXT_34 - - D34 : EXT_35 - - D35 : EXT_36 - - D36 : EXT_38 - - D37 : EXT_39 - - D38 : EXT_40 - - D39 : EXT_44 - - D40 : EXT_41 - - D41 : EXT_31 - - D42 : EXT_37 - - D43 : EXT_42 - - D44 : EXT_43 - - D45 : EXT_45 - - D46 : EXT_46 - - D47 : EXT_47 - - D48 : EXT_48 - - D49 : EXT_49 - - D50 : EXT_50 - - D51 : EXT_51 - -Peripheral Mapping: - -.. rst-class:: rst-columns - - - UART_3_RX : D0 - - UART_3_TX : D1 - - SPI_3_CS : D10 - - SPI_3_MOSI : D11 - - SPI_3_MISO : D12 - - SPI_3_SCLK : D13 - - I2C_3_SDA : D14 - - I2C_3_SCL : D15 - - UART_4_RX : D26 - - UART_4_TX : D30 - - SPI_4_CS : D36 - - SPI_4_MOSI : D37 - - SPI_4_MISO : D38 - - SPI_4_SCK : D39 - - I2C_4_SDA : D40 - - I2C_4_SCL : D41 - -For more details refer to `MPS2+ AN521 Technical Reference Manual (TRM)`_. - -LED -============ - -MPS2+ has 8 built-in LEDs connected to Serial Configuration Controller (SCC). - -.. note:: The SCC register CFG_REG1 Bits [7:0] for LEDa, 0 = OFF 1 = ON. - -System Clock -============ - -MPS2+ AN521 has several clocks connected: - -.. rst-class:: rst-columns - - - MAINCLK : 20MHz - - SYSCLK : 20MHz - - S32KCLK : 32kHz - - TRACECLK : 20MHz - - SWCLKTCK : 20MHz - - TRACECLKIN : 20MHz - -Serial Port -=========== - -The MPS2+ AN521 has five UARTs. The Zephyr console output by default, uses -UART0, which is J10 on the board. - -UART2 is reserved. And UART 1, 3 and 4 are alt-functions on the EXP ports. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is used to define - secure and non-secure memory maps. By default, all of the memory space is - defined to be secure accessible only -- Secure and Non-secure peripherals via the Peripheral Protection Controller - (PPC). Peripherals can be assigned as secure or non-secure accessible -- Secure boot -- Secure `AMBA®`_ interconnect - -Serial Configuration Controller (SCC) -===================================== - -The MPS2+ AN521 implements a Serial Configuration Control (SCC) register. -The purpose of this register is to allow individual control of clocks, -reset-signals and interrupts to peripherals, and pin-muxing, and the LEDs and -switches. - -Programming and Debugging -************************* - -MPS2+ AN521 (CPU0) supports the Armv8m Security Extension. -Applications built for the mps2_an521 board by default -boot in the Secure state. - -MPS2+ AN521 (CPU1) does not support the Armv8m Security Extension. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -Applications on the MPS2+ AN521 (CPU0) may contain a Secure and a Non-Secure -firmware image. The Secure image can be built using either Zephyr -or `Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built -using Zephyr. The two alternatives are described below. - -.. note:: - - By default the Secure image for the MPS2+ AN521 (CPU0) is built - using TF-M. - -Building the Secure firmware with TF-M --------------------------------------- - -The process to build the Secure firmware image using TF-M and the Non-Secure -firmware image using Zephyr requires the following steps: - -1. Build the Non-Secure Zephyr application - for MPS2+ AN521 (CPU0) using ``-DBOARD=mps2_an521_ns``. - To invoke the building of TF-M the Zephyr build system requires the - Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by - default when building Zephyr as a Non-Secure application. - The Zephyr build system will perform the following steps automatically: - - * Build the Non-Secure firmware image as a regular Zephyr application - * Build a TF-M (secure) firmware image - * Merge the output image binaries together - * Optionally build a bootloader image (MCUboot) - -.. note:: - - Depending on the TF-M configuration, an application DTS overlay may be - required, to adjust the Non-Secure image Flash and SRAM starting address - and sizes. - -Building the Secure firmware using Zephyr ------------------------------------------ - -The process to build the Secure and the Non-Secure firmware images -using Zephyr requires the following steps: - -1. Build the Secure Zephyr application for MPS2+ AN521 (CPU0) - using ``-DBOARD=mps2_an521`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` - in the application project configuration file. -2. Build the Non-Secure Zephyr application for MPS2+ AN521 (CPU0) - using ``-DBOARD=mps2_an521_ns``. -3. Merge the two binaries together. - -Building a Secure only application on MPS2+ AN521 (CPU0) -======================================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=mps2_an521`` for -the firmware running on the MPS2+ AN521 (CPU0). - -When building a Secure/Non-Secure application for the MPS2+ AN521 (CPU0), -the Secure application will have to set the SAU/IDAU configuration to allow -Non-Secure access to all CPU resources utilized by the Non-Secure application -firmware. SAU/IDAU configuration shall take place before jumping to the -Non-Secure application. - -The following system components are required to be properly configured during the -secure firmware: - -- AHB5 TrustZone Memory Protection Controller (MPC) -- AHB5 TrustZone Peripheral Protection Controller (PPC) -- Implementation-Defined Attribution Unit (IDAU) - -For more details refer to `Corelink SSE-200 Subsystem`_. - - - -Building standalone applications on MPS2+ AN521 CPU1 -==================================================== - -Applications may be built for the second Cortex-M33 -(remote) core of MPS2+ AN521. The core is referred to as CPU1. - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=mps2_an521_remote`` for -the firmware running on the MPS2+ AN521 (CPU1). - -The Zephyr build will automatically trigger building a minimal (empty) -secure-only firmware for CPU0, which will be used to boot the remote -core (CPU1). - - -Flashing -======== - -MPS2+ AN521 provides: - -- A USB connection to the host computer, which exposes a Mass Storage -- A Serial Port which is J10 on MPS2+ board - -Build applications as described above. -Here is an example for the :ref:`hello_world` application built as -a secure-only application for CPU0. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mps2_an521 - :goals: build - - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board, and you should see the following message on the corresponding -serial port: - -.. code-block:: console - - Hello World! mps2_an521 - - -Uploading an application to MPS2+ AN521 ---------------------------------------- - -Applications can be in elf, hex or bin format. The binaries are flashed when -the board boots up, using files stored on the on-board Micro SD card. The -Motherboard Configuration Controller (MCC) is responsible for loading the FPGA -image and binaries. - -Connect the MPS2+ to your host computer using the USB port. You should see a -USB connection exposing a Mass Storage (``V2M_MPS2`` by default). - -The update requires 3 steps: - -1. Copy application files to ``/SOFTWARE/``. -2. Open ``/MB/HBI0263C/AN521/images.txt``. -3. Update the ``AN521/images.txt`` file as follows: - -.. code-block:: bash - - TITLE: Versatile Express Images Configuration File - - [IMAGES] - TOTALIMAGES: 1 ;Number of Images (Max: 32) - - IMAGE0ADDRESS: 0x10000000 ;Please select the required executable program - - IMAGE0FILE: \SOFTWARE\zephyr.bin - - -Reset the board, and you should see the following message on the corresponding -serial port: - -.. code-block:: console - - Hello World! mps2_an521 - -.. note:: Refer to the tfm_integration sample for more details about integrating with TF-M and multiple images scenario. - - -.. _MPS2 FPGA Website: - https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps2 - -.. _MPS2+ AN521 Technical Reference Manual (TRM): - https://developer.arm.com/documentation/dai0521/latest/ - -.. _Cortex M33 Generic User Guide: - https://developer.arm.com/documentation/100235/latest/ - -.. _Trusted Firmware M: - https://tf-m-user-guide.trustedfirmware.org/building/tfm_build_instruction.html - -.. _Corelink SSE-200 Subsystem: - https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200 - -.. _IDAU: - https://developer.arm.com/documentation/100690/latest/Attribution-units--SAU-and-IDAU- - -.. _AMBA®: - https://developer.arm.com/products/architecture/system-architectures/amba diff --git a/boards/arm/mps2_an521/mps2_an521.yaml b/boards/arm/mps2_an521/mps2_an521.yaml deleted file mode 100644 index acc2d95127b..00000000000 --- a/boards/arm/mps2_an521/mps2_an521.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: mps2_an521 -name: ARM V2M MPS2-AN521 -type: mcu -arch: arm -ram: 4096 -flash: 4096 -simulation: qemu -toolchain: - - gnuarmemb - - zephyr - - xtools -supported: - - gpio -testing: - default: true - ignore_tags: - - drivers - - bluetooth - - net - - timer -vendor: arm diff --git a/boards/arm/mps2_an521/mps2_an521_defconfig b/boards/arm/mps2_an521/mps2_an521_defconfig deleted file mode 100644 index 032f9bad9d1..00000000000 --- a/boards/arm/mps2_an521/mps2_an521_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (c) 2018-2019 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_MPS2=y -CONFIG_SOC_MPS2_AN521_CPU0=y -CONFIG_BOARD_MPS2_AN521_CPU0=y -CONFIG_RUNTIME_NMI=y -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_ARM_MPU=y -CONFIG_QEMU_ICOUNT_SHIFT=7 - -# GPIOs -CONFIG_GPIO=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -# Build a Secure firmware image -CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arm/mps2_an521/mps2_an521_ns.yaml b/boards/arm/mps2_an521/mps2_an521_ns.yaml deleted file mode 100644 index bf8d5edc243..00000000000 --- a/boards/arm/mps2_an521/mps2_an521_ns.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: mps2_an521_ns -name: ARM V2M MPS2-AN521_ns -type: mcu -arch: arm -ram: 512 -flash: 512 -simulation: qemu -toolchain: - - gnuarmemb - - zephyr - - xtools -testing: - default: true - only_tags: - - arm - - kernel - - tfm - - userspace - - trusted-firmware-m diff --git a/boards/arm/mps2_an521/mps2_an521_ns_defconfig b/boards/arm/mps2_an521/mps2_an521_ns_defconfig deleted file mode 100644 index 780fdaf097f..00000000000 --- a/boards/arm/mps2_an521/mps2_an521_ns_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (c) 2018-2019 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_MPS2=y -CONFIG_SOC_MPS2_AN521_CPU0=y -CONFIG_BOARD_MPS2_AN521_CPU0_NS=y -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y -CONFIG_ARM_MPU=y -CONFIG_QEMU_ICOUNT_SHIFT=6 - -# GPIOs -CONFIG_GPIO=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/mps2_an521/mps2_an521_remote.yaml b/boards/arm/mps2_an521/mps2_an521_remote.yaml deleted file mode 100644 index 1371fd01cad..00000000000 --- a/boards/arm/mps2_an521/mps2_an521_remote.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: mps2_an521_remote -name: ARM V2M MPS2-AN521_remote -type: mcu -arch: arm -ram: 512 -flash: 468 -simulation: qemu -toolchain: - - gnuarmemb - - zephyr - - xtools -testing: - default: true - only_tags: - - arm - - fpu diff --git a/boards/arm/mps2_an521/mps2_an521_remote_defconfig b/boards/arm/mps2_an521/mps2_an521_remote_defconfig deleted file mode 100644 index 9bc7f496873..00000000000 --- a/boards/arm/mps2_an521/mps2_an521_remote_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2018-2019 Linaro Limited -# Copyright (c) 2021 Nordic Semiconductor ASA -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_MPS2=y -CONFIG_SOC_MPS2_AN521_CPU1=y -CONFIG_BOARD_MPS2_AN521_CPU1=y -CONFIG_RUNTIME_NMI=y -CONFIG_ARM_MPU=y -CONFIG_QEMU_ICOUNT_SHIFT=7 - -# GPIOs -CONFIG_GPIO=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/mps2_an521/pinmux.c b/boards/arm/mps2_an521/pinmux.c deleted file mode 100644 index bc92dc747d1..00000000000 --- a/boards/arm/mps2_an521/pinmux.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (c) 2018-2019 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include - -/** - * @brief Pinmux driver for ARM MPS2 AN521 Board - * - * The ARM MPS2 AN521 Board has 4 GPIO controllers. These controllers - * are responsible for pin muxing, input/output, pull-up, etc. - * - * All GPIO controller pins are exposed via the following sequence of pin - * numbers: - * Pins 0 - 15 are for GPIO0 - * Pins 16 - 31 are for GPIO1 - * Pins 32 - 47 are for GPIO2 - * Pins 48 - 51 are for GPIO3 - * - * For the GPIO controllers configuration ARM MPS2 AN521 Board follows the - * Arduino compliant pin out. - */ - -#define CMSDK_AHB_GPIO0_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio0))) -#define CMSDK_AHB_GPIO1_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio1))) -#define CMSDK_AHB_GPIO2_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio2))) -#define CMSDK_AHB_GPIO3_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio3))) - -/* - * This is the mapping from the ARM MPS2 AN521 Board pins to GPIO - * controllers. - * - * D0 : EXT_0 - * D1 : EXT_4 - * D2 : EXT_2 - * D3 : EXT_3 - * D4 : EXT_1 - * D5 : EXT_6 - * D6 : EXT_7 - * D7 : EXT_8 - * D8 : EXT_9 - * D9 : EXT_10 - * D10 : EXT_12 - * D11 : EXT_13 - * D12 : EXT_14 - * D13 : EXT_11 - * D14 : EXT_15 - * D15 : EXT_5 - * D16 : EXT_16 - * D17 : EXT_17 - * D18 : EXT_18 - * D19 : EXT_19 - * D20 : EXT_20 - * D21 : EXT_21 - * D22 : EXT_22 - * D23 : EXT_23 - * D24 : EXT_24 - * D25 : EXT_25 - * D26 : EXT_26 - * D27 : EXT_30 - * D28 : EXT_28 - * D29 : EXT_29 - * D30 : EXT_27 - * D31 : EXT_32 - * D32 : EXT_33 - * D33 : EXT_34 - * D34 : EXT_35 - * D35 : EXT_36 - * D36 : EXT_38 - * D37 : EXT_39 - * D38 : EXT_40 - * D39 : EXT_44 - * D40 : EXT_41 - * D41 : EXT_31 - * D42 : EXT_37 - * D43 : EXT_42 - * D44 : EXT_43 - * D45 : EXT_45 - * D46 : EXT_46 - * D47 : EXT_47 - * D48 : EXT_48 - * D49 : EXT_49 - * D50 : EXT_50 - * D51 : EXT_51 - * - * UART_3_RX : D0 - * UART_3_TX : D1 - * SPI_3_CS : D10 - * SPI_3_MOSI : D11 - * SPI_3_MISO : D12 - * SPI_3_SCLK : D13 - * I2C_3_SDA : D14 - * I2C_3_SCL : D15 - * UART_4_RX : D26 - * UART_4_TX : D30 - * SPI_4_CS : D36 - * SPI_4_MOSI : D37 - * SPI_4_MISO : D38 - * SPI_4_SCK : D39 - * I2C_4_SDA : D40 - * I2C_4_SCL : D41 - * - */ -static void arm_mps2_pinmux_defaults(void) -{ - uint32_t gpio_0 = 0; - uint32_t gpio_1 = 0; - uint32_t gpio_2 = 0; - - /* Set GPIO Alternate Functions */ - - gpio_0 = (1<<0) /* Shield 0 UART 3 RXD */ - | (1<<4) /* Shield 0 UART 3 TXD */ - | (1<<5) /* Shield 0 I2C SCL SBCON2 */ - | (1<<15) /* Shield 0 I2C SDA SBCON2 */ - | (1<<11) /* Shield 0 SPI 3 SCK */ - | (1<<12) /* Shield 0 SPI 3 SS */ - | (1<<13) /* Shield 0 SPI 3 MOSI */ - | (1<<14); /* Shield 0 SPI 3 MISO */ - - CMSDK_AHB_GPIO0_DEV->altfuncset = gpio_0; - - gpio_1 = (1<<10) /* Shield 1 UART 4 RXD */ - | (1<<14) /* Shield 1 UART 4 TXD */ - | (1<<15) /* Shield 1 I2C SCL SBCON3 */ - | (1<<0) /* ADC SPI 2 SS */ - | (1<<1) /* ADC SPI 2 MISO */ - | (1<<2) /* ADC SPI 2 MOSI */ - | (1<<3) /* ADC SPI 2 SCK */ - | (1<<5) /* USER BUTTON 0 */ - | (1<<6); /* USER BUTTON 1 */ - - CMSDK_AHB_GPIO1_DEV->altfuncset = gpio_1; - - gpio_2 = (1<<9) /* Shield 1 I2C SDA SBCON3 */ - | (1<<6) /* Shield 1 SPI 4 SS */ - | (1<<7) /* Shield 1 SPI 4 MOSI */ - | (1<<8) /* Shield 1 SPI 4 MISO */ - | (1<<12); /* Shield 1 SPI 4 SCK */ - - CMSDK_AHB_GPIO2_DEV->altfuncset = gpio_2; -} - -static int arm_mps2_pinmux_init(void) -{ - - arm_mps2_pinmux_defaults(); - - return 0; -} - -SYS_INIT(arm_mps2_pinmux_init, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/boards/arm/mps3/Kconfig b/boards/arm/mps3/Kconfig new file mode 100644 index 00000000000..019f22aae49 --- /dev/null +++ b/boards/arm/mps3/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPS3 + select QEMU_TARGET diff --git a/boards/arm/mps3/Kconfig.defconfig b/boards/arm/mps3/Kconfig.defconfig new file mode 100644 index 00000000000..078012e46a7 --- /dev/null +++ b/boards/arm/mps3/Kconfig.defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2018-2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MPS3_AN547 + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped but QEMU +# will still permit bus access. +choice NULL_POINTER_EXCEPTION_DETECTION + bool + default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET +endchoice + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +endif # SERIAL + +endif diff --git a/boards/arm/mps3/Kconfig.mps3 b/boards/arm/mps3/Kconfig.mps3 new file mode 100644 index 00000000000..84dd3fff095 --- /dev/null +++ b/boards/arm/mps3/Kconfig.mps3 @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPS3 + select SOC_SERIES_MPS3 + select SOC_MPS3_AN547 diff --git a/boards/arm/mps3_an547/board.cmake b/boards/arm/mps3/board.cmake similarity index 100% rename from boards/arm/mps3_an547/board.cmake rename to boards/arm/mps3/board.cmake diff --git a/boards/arm/mps3/board.yml b/boards/arm/mps3/board.yml new file mode 100644 index 00000000000..5ee7ed7c037 --- /dev/null +++ b/boards/arm/mps3/board.yml @@ -0,0 +1,7 @@ +board: + name: mps3 + vendor: arm + socs: + - name: 'an547' + variants: + - name: 'ns' diff --git a/boards/arm/mps3_an547/doc/img/mps3_an547.jpg b/boards/arm/mps3/doc/img/mps3_an547.jpg similarity index 100% rename from boards/arm/mps3_an547/doc/img/mps3_an547.jpg rename to boards/arm/mps3/doc/img/mps3_an547.jpg diff --git a/boards/arm/mps3/doc/index.rst b/boards/arm/mps3/doc/index.rst new file mode 100644 index 00000000000..530999206d4 --- /dev/null +++ b/boards/arm/mps3/doc/index.rst @@ -0,0 +1,245 @@ +.. _mps3_an547_board: + +ARM MPS3 AN547 +############### + +Overview +******** + +The mps3_an547 board configuration is used by Zephyr applications that run +on the MPS3 AN547 board. It provides support for the MPS3 AN547 ARM Cortex-M55 +CPU and the following devices: + +- Nested Vectored Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) +- Cortex-M System Design Kit GPIO +- Cortex-M System Design Kit UART +- Ethos-U55 NPU + +.. image:: img/mps3_an547.jpg + :align: center + :alt: ARM MPS3 AN547 + +This board configuration also supports using the `Corstone-300 FVP`_ to emulate +a MPS3 AN547 hardware platform. + +The Corstone-300 FVP (Fixed Virtual Platform) is a complete simulation of the +Arm system, including processor, memory and peripherals. It is a available free +of charge for Linux and Windows systems. The FVP has been selected for +simulation since it provides access to the Ethos-U55 NPU, which is unavailable +in QEMU or other simulation platforms. + +To run the Fixed Virtual Platform simulation tool you must download "FVP model +for the Corstone-300 MPS3" from Arm and install it on your host PC. This board +has been tested with version 11.12.57 (Nov 2 2020). + +Zephyr board options +==================== + +The MPS3+ AN547 is an SoC with Cortex-M55 architecture. Zephyr provides support +for building for both Secure and Non-Secure firmware. + +The BOARD options are summarized below: + ++----------------------+-----------------------------------------------+ +| BOARD | Description | ++======================+===============================================+ +| ``mps3/an547`` | For building Secure (or Secure-only) firmware | ++----------------------+-----------------------------------------------+ +| ``mps3/an547/ns`` | For building Non-Secure firmware | ++----------------------+-----------------------------------------------+ + +Hardware +******** + +ARM MPS3 AN547 provides the following hardware components: + +- ARM Cortex-M55 +- Soft Macro Model (SMM) implementation of SSE-300 subsystem +- Memory + + - 8MB BRAM + - 4GB DDR4 SODIMM (by default, upgradeable to 8GB) + - 16GB eMMC + - 8MB QSPI Flash + +- Debug + + - P‐JTAG, F-JTAG, SWD, 4-bit trace, 16-bit trace + - Four serial ports over USB + +- Interface + + - AHB GPIO + - UART + - SPI + - I2C + - I2S + - Color LCD serial interface + - Ethernet + - VGA + +- On-board Peripherals + + - Color LCD + - 10 LEDs + - 8 Switches + - 2 user push buttons + +Supported Features +=================== + +The ``mps3/an547`` board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. +See the `MPS3 FPGA Website`_ for a complete list of MPS3 AN547 board hardware +features. + +The default configuration can be found in +:zephyr_file:`boards/arm/mps3/mps3_an547_defconfig`. + +For more details refer to `MPS3 AN547 Technical Reference Manual (TRM)`_. + +Serial Port +=========== + +The MPS3 AN547 has six UARTs. The Zephyr console output by default, uses +UART0, which is exposed over the Debug USB interface (J8). + +Serial port 0 on the Debug USB interface is the MCC board control console. + +Serial port 1 on the Debug USB interface is connected to UART 0. + +Serial port 2 on the Debug USB interface is connected to UART 1. + +Serial port 3 on the Debug USB interface is connected to UART 2. + +Programming and Debugging +************************* + +Flashing +======== + +MPS3 AN547 provides: + +- A USB connection to the host computer, which exposes Mass Storage and + CMSIS-DAP, and serial ports. + +Building an application +----------------------- + +You can build applications in the usual way. Here is an example for +the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mps3/an547 + :goals: build + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board, and you should see the following message on the corresponding +serial port: + +.. code-block:: console + + Hello World! mps3 + +Uploading an application to MPS3 AN547 +--------------------------------------- + +Applications can be in elf, hex or bin format. The binaries are flashed when +the board boots up, using files stored on the on-board Micro SD card. The +Motherboard Configuration Controller (MCC) is responsible for loading the FPGA +image and binaries. + +Connect the MPS3 to your host computer using the USB port. You should see a +USB connection exposing a Mass Storage (``V2M-MPS3`` by default). + +The update requires 3 steps: + +1. Copy application files to ``/SOFTWARE/``. +2. Open ``/MB/HBI0309C/AN547/images.txt``. +3. Update the ``AN547/images.txt`` file as follows: + +.. code-block:: bash + + TITLE: Versatile Express Images Configuration File + + [IMAGES] + TOTALIMAGES: 1 ;Number of Images (Max: 32) + + IMAGE0ADDRESS: 0x01000000 ;Please select the required executable program + + IMAGE0FILE: \SOFTWARE\zephyr.elf + + +Reset the board, and you should see the following message on the corresponding +serial port: + +.. code-block:: console + + Hello World! mps3 + + +FVP Usage +========= + +To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before +using it. Then you can run it with ``west build -t run``. + +.. code-block:: bash + + export ARMFVP_BIN_PATH=/path/to/fvp/directory + west build -t run + + +QEMU Usage +========== + +To run with QEMU instead of the default FVP, override the emulator selection +at build time via: + +.. code-block:: bash + + $ west build -b mps3_an547 samples/hello_world -DEMU_PLATFORM=qemu -t run + + +Note, however, that the Ethos-U55 NPU is not available in QEMU. If you require +the use of the NPU, please use the default FVP for device emulation. + +.. _Corstone-300 FVP: + https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps + +.. _MPS3 FPGA Website: + https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps3 + +.. _MPS3 AN547 Technical Reference Manual (TRM): + https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf + +.. _MPS3 FPGA Prototyping Board Technical Reference Manual (TRM): + https://developer.arm.com/documentation/100765/latest + +.. _Cortex M55 Generic User Guide: + https://developer.arm.com/documentation/101051/latest + +.. _Corelink SSE-300 Example Subsystem: + https://developer.arm.com/documentation/101772/latest diff --git a/boards/arm/mps3_an547/mps3_an547-common.dtsi b/boards/arm/mps3/mps3_an547-common.dtsi similarity index 100% rename from boards/arm/mps3_an547/mps3_an547-common.dtsi rename to boards/arm/mps3/mps3_an547-common.dtsi diff --git a/boards/arm/mps3_an547/mps3_an547.dts b/boards/arm/mps3/mps3_an547.dts similarity index 100% rename from boards/arm/mps3_an547/mps3_an547.dts rename to boards/arm/mps3/mps3_an547.dts diff --git a/boards/arm/mps3_an547/mps3_an547.yaml b/boards/arm/mps3/mps3_an547.yaml similarity index 93% rename from boards/arm/mps3_an547/mps3_an547.yaml rename to boards/arm/mps3/mps3_an547.yaml index 3ade98161c8..538fa24db67 100644 --- a/boards/arm/mps3_an547/mps3_an547.yaml +++ b/boards/arm/mps3/mps3_an547.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: mps3_an547 +identifier: mps3/an547 name: Arm MPS3-AN547 type: mcu arch: arm diff --git a/boards/arm/mps3_an547/mps3_an547_defconfig b/boards/arm/mps3/mps3_an547_defconfig similarity index 81% rename from boards/arm/mps3_an547/mps3_an547_defconfig rename to boards/arm/mps3/mps3_an547_defconfig index ec0c9fccc33..90c9b6a9f8e 100644 --- a/boards/arm/mps3_an547/mps3_an547_defconfig +++ b/boards/arm/mps3/mps3_an547_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_MPS3=y -CONFIG_SOC_MPS3_AN547=y -CONFIG_BOARD_MPS3_AN547=y CONFIG_RUNTIME_NMI=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_ARM_MPU=y diff --git a/boards/arm/mps3_an547/mps3_an547_ns.dts b/boards/arm/mps3/mps3_an547_ns.dts similarity index 100% rename from boards/arm/mps3_an547/mps3_an547_ns.dts rename to boards/arm/mps3/mps3_an547_ns.dts diff --git a/boards/arm/mps3_an547/mps3_an547_ns.yaml b/boards/arm/mps3/mps3_an547_ns.yaml similarity index 91% rename from boards/arm/mps3_an547/mps3_an547_ns.yaml rename to boards/arm/mps3/mps3_an547_ns.yaml index 665962c62ec..3852415834f 100644 --- a/boards/arm/mps3_an547/mps3_an547_ns.yaml +++ b/boards/arm/mps3/mps3_an547_ns.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: mps3_an547_ns +identifier: mps3/an547/ns name: Arm MPS3-AN547_ns type: mcu arch: arm diff --git a/boards/arm/mps3_an547/mps3_an547_ns_defconfig b/boards/arm/mps3/mps3_an547_ns_defconfig similarity index 80% rename from boards/arm/mps3_an547/mps3_an547_ns_defconfig rename to boards/arm/mps3/mps3_an547_ns_defconfig index f782f9f8623..ccc25c35019 100644 --- a/boards/arm/mps3_an547/mps3_an547_ns_defconfig +++ b/boards/arm/mps3/mps3_an547_ns_defconfig @@ -4,12 +4,8 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_MPS3=y -CONFIG_SOC_MPS3_AN547=y -CONFIG_BOARD_MPS3_AN547=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y CONFIG_ARM_MPU=y CONFIG_QEMU_ICOUNT_SHIFT=6 @@ -20,3 +16,7 @@ CONFIG_GPIO=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y + +# Build a Non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/mps3_an547/Kconfig.board b/boards/arm/mps3_an547/Kconfig.board deleted file mode 100644 index f8e755f12ed..00000000000 --- a/boards/arm/mps3_an547/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MPS3_AN547 - bool "Arm Cortex-M55 (Corstone-300, SSE-300 w/Ethos-U55) on MPS3 (AN547)" - depends on SOC_MPS3_AN547 - select QEMU_TARGET diff --git a/boards/arm/mps3_an547/Kconfig.defconfig b/boards/arm/mps3_an547/Kconfig.defconfig deleted file mode 100644 index a318d14aefe..00000000000 --- a/boards/arm/mps3_an547/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2018-2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MPS3_AN547 - -config BOARD - default "mps3_an547" - -# MPU-based null-pointer dereferencing detection cannot -# be applied as the (0x0 - 0x400) is unmapped but QEMU -# will still permit bus access. -choice NULL_POINTER_EXCEPTION_DETECTION - bool - default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET -endchoice - -if SERIAL - -config UART_INTERRUPT_DRIVEN - default y - -endif # SERIAL - -endif diff --git a/boards/arm/mps3_an547/doc/index.rst b/boards/arm/mps3_an547/doc/index.rst deleted file mode 100644 index b5f383d546a..00000000000 --- a/boards/arm/mps3_an547/doc/index.rst +++ /dev/null @@ -1,245 +0,0 @@ -.. _mps3_an547_board: - -ARM MPS3 AN547 -############### - -Overview -******** - -The mps3_an547 board configuration is used by Zephyr applications that run -on the MPS3 AN547 board. It provides support for the MPS3 AN547 ARM Cortex-M55 -CPU and the following devices: - -- Nested Vectored Interrupt Controller (NVIC) -- System Tick System Clock (SYSTICK) -- Cortex-M System Design Kit GPIO -- Cortex-M System Design Kit UART -- Ethos-U55 NPU - -.. image:: img/mps3_an547.jpg - :align: center - :alt: ARM MPS3 AN547 - -This board configuration also supports using the `Corstone-300 FVP`_ to emulate -a MPS3 AN547 hardware platform. - -The Corstone-300 FVP (Fixed Virtual Platform) is a complete simulation of the -Arm system, including processor, memory and peripherals. It is a available free -of charge for Linux and Windows systems. The FVP has been selected for -simulation since it provides access to the Ethos-U55 NPU, which is unavailable -in QEMU or other simulation platforms. - -To run the Fixed Virtual Platform simulation tool you must download "FVP model -for the Corstone-300 MPS3" from Arm and install it on your host PC. This board -has been tested with version 11.12.57 (Nov 2 2020). - -Zephyr board options -==================== - -The MPS3+ AN547 is an SoC with Cortex-M55 architecture. Zephyr provides support -for building for both Secure and Non-Secure firmware. - -The BOARD options are summarized below: - -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| mps3_an547 | For building Secure (or Secure-only) firmware | -+----------------------+-----------------------------------------------+ -| mps3_an547_ns | For building Non-Secure firmware | -+----------------------+-----------------------------------------------+ - -Hardware -******** - -ARM MPS3 AN547 provides the following hardware components: - -- ARM Cortex-M55 -- Soft Macro Model (SMM) implementation of SSE-300 subsystem -- Memory - - - 8MB BRAM - - 4GB DDR4 SODIMM (by default, upgradeable to 8GB) - - 16GB eMMC - - 8MB QSPI Flash - -- Debug - - - P‐JTAG, F-JTAG, SWD, 4-bit trace, 16-bit trace - - Four serial ports over USB - -- Interface - - - AHB GPIO - - UART - - SPI - - I2C - - I2S - - Color LCD serial interface - - Ethernet - - VGA - -- On-board Peripherals - - - Color LCD - - 10 LEDs - - 8 Switches - - 2 user push buttons - -Supported Features -=================== - -The mps3_an547 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `MPS3 FPGA Website`_ for a complete list of MPS3 AN547 board hardware -features. - -The default configuration can be found in the defconfig file: -``boards/arm/mps3_an547/mps3_an547_defconfig``. - -For more details refer to `MPS3 AN547 Technical Reference Manual (TRM)`_. - -Serial Port -=========== - -The MPS3 AN547 has six UARTs. The Zephyr console output by default, uses -UART0, which is exposed over the Debug USB interface (J8). - -Serial port 0 on the Debug USB interface is the MCC board control console. - -Serial port 1 on the Debug USB interface is connected to UART 0. - -Serial port 2 on the Debug USB interface is connected to UART 1. - -Serial port 3 on the Debug USB interface is connected to UART 2. - -Programming and Debugging -************************* - -Flashing -======== - -MPS3 AN547 provides: - -- A USB connection to the host computer, which exposes Mass Storage and - CMSIS-DAP, and serial ports. - -Building an application ------------------------ - -You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mps3_an547 - :goals: build - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board, and you should see the following message on the corresponding -serial port: - -.. code-block:: console - - Hello World! mps3_an547 - -Uploading an application to MPS3 AN547 ---------------------------------------- - -Applications can be in elf, hex or bin format. The binaries are flashed when -the board boots up, using files stored on the on-board Micro SD card. The -Motherboard Configuration Controller (MCC) is responsible for loading the FPGA -image and binaries. - -Connect the MPS3 to your host computer using the USB port. You should see a -USB connection exposing a Mass Storage (``V2M-MPS3`` by default). - -The update requires 3 steps: - -1. Copy application files to ``/SOFTWARE/``. -2. Open ``/MB/HBI0309C/AN547/images.txt``. -3. Update the ``AN547/images.txt`` file as follows: - -.. code-block:: bash - - TITLE: Versatile Express Images Configuration File - - [IMAGES] - TOTALIMAGES: 1 ;Number of Images (Max: 32) - - IMAGE0ADDRESS: 0x01000000 ;Please select the required executable program - - IMAGE0FILE: \SOFTWARE\zephyr.elf - - -Reset the board, and you should see the following message on the corresponding -serial port: - -.. code-block:: console - - Hello World! mps3_an547 - - -FVP Usage -========= - -To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before -using it. Then you can run it with ``west build -t run``. - -.. code-block:: bash - - export ARMFVP_BIN_PATH=/path/to/fvp/directory - west build -t run - - -QEMU Usage -========== - -To run with QEMU instead of the default FVP, override the emulator selection -at build time via: - -.. code-block:: bash - - $ west build -b mps3_an547 samples/hello_world -DEMU_PLATFORM=qemu -t run - - -Note, however, that the Ethos-U55 NPU is not available in QEMU. If you require -the use of the NPU, please use the default FVP for device emulation. - -.. _Corstone-300 FVP: - https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps - -.. _MPS3 FPGA Website: - https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps3 - -.. _MPS3 AN547 Technical Reference Manual (TRM): - https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf - -.. _MPS3 FPGA Prototyping Board Technical Reference Manual (TRM): - https://developer.arm.com/documentation/100765/latest - -.. _Cortex M55 Generic User Guide: - https://developer.arm.com/documentation/101051/latest - -.. _Corelink SSE-300 Example Subsystem: - https://developer.arm.com/documentation/101772/latest diff --git a/boards/arm/mr_canhubk3/Kconfig.board b/boards/arm/mr_canhubk3/Kconfig.board deleted file mode 100644 index af9a09391cd..00000000000 --- a/boards/arm/mr_canhubk3/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MR_CANHUBK3 - bool "mr_canhubk3" - depends on SOC_SERIES_S32K3XX - select SOC_PART_NUMBER_PS32K344EHVPBS diff --git a/boards/arm/mr_canhubk3/Kconfig.defconfig b/boards/arm/mr_canhubk3/Kconfig.defconfig deleted file mode 100644 index 53e554da88f..00000000000 --- a/boards/arm/mr_canhubk3/Kconfig.defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MR_CANHUBK3 - -config BOARD - default "mr_canhubk3" - -if SERIAL - -config UART_CONSOLE - default y - -endif # SERIAL - -if SPI - -config SPI_INIT_PRIORITY - default 50 - -if WDT_NXP_FS26 - -config WDT_NXP_FS26_INIT_PRIORITY - default 51 - -endif # WDT_NXP_FS26 -endif # SPI - -if CAN - -config GPIO - default y - -endif # CAN - -if NETWORKING - -config NET_L2_ETHERNET - default y if !NET_LOOPBACK && !NET_TEST - -config MDIO - default y if NET_L2_ETHERNET - -endif # NETWORKING - -endif # BOARD_MR_CANHUBK3 diff --git a/boards/arm/mr_canhubk3/doc/index.rst b/boards/arm/mr_canhubk3/doc/index.rst deleted file mode 100644 index 711ee43a0ca..00000000000 --- a/boards/arm/mr_canhubk3/doc/index.rst +++ /dev/null @@ -1,339 +0,0 @@ -.. _mr_canhubk3: - -NXP MR-CANHUBK3 -############### - -Overview -******** - -`NXP MR-CANHUBK3`_ is an evaluation board for mobile robotics applications such -as autonomous mobile robots (AMR) and automated guided vehicles (AGV). It -features an `NXP S32K344`_ general-purpose automotive microcontroller based on -an Arm Cortex-M7 core (Lock-Step). - -.. image:: img/mr_canhubk3_top.jpg - :align: center - :alt: NXP MR-CANHUBK3 (TOP) - -Hardware -******** - -- NXP S32K344 - - Arm Cortex-M7 (Lock-Step), 160 MHz (Max.) - - 4 MB of program flash, with ECC - - 320 KB RAM, with ECC - - Ethernet 100 Mbps, CAN FD, FlexIO, QSPI - - 12-bit 1 Msps ADC, 16-bit eMIOS timer - -- `NXP FS26 Safety System Basis Chip`_ - -- Interfaces: - - Console UART - - 6x CAN FD - - 100Base-T1 Ethernet - - JST-GH connectors and I/O headers for I2C, SPI, GPIO, - PWM, etc. - -More information about the hardware and design resources can be found at -`NXP MR-CANHUBK3`_ website. - -Supported Features -================== - -The ``mr_canhubk3`` board configuration supports the following hardware features: - -============ ========== ================================ -Interface Controller Driver/Component -============ ========== ================================ -SIUL2 on-chip | pinctrl - | gpio - | external interrupt controller -WKPU on-chip interrupt controller -LPUART on-chip serial -QSPI on-chip flash -FLEXCAN on-chip can -LPI2C on-chip i2c -ADC SAR on-chip adc -LPSPI on-chip spi -WDT FS26 SBC watchdog -EMAC on-chip ethernet - mdio -eMIOS on-chip pwm -EDMA on-chip dma -============ ========== ================================ - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/mr_canhubk3/mr_canhubk3_defconfig`. - -Connections and IOs -=================== - -Each GPIO port is divided into two banks: low bank, from pin 0 to 15, and high -bank, from pin 16 to 31. For example, ``PTA2`` is the pin 2 of ``gpioa_l`` (low -bank), and ``PTA20`` is the pin 4 of ``gpioa_h`` (high bank). - -The GPIO controller provides the option to route external input pad interrupts -to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC. -By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller, -unless they are explicity configured to be directed to the WKPU interrupt -controller, as outlined in :zephyr_file:`dts/bindings/gpio/nxp,s32-gpio.yaml`. - -To find information about which GPIOs are compatible with each interrupt -controller, refer to the device reference manual. - -.. note:: - - It is important to highlight that the current board configuration lacks - support for wake-up events and power-management features. WKPU functionality - is restricted solely to serving as an interrupt controller. - -LEDs ----- - -The MR-CANHUBK3 board has one user RGB LED: - -======================= ===== ===== =================================== -Devicetree node Color Pin Pin Functions -======================= ===== ===== =================================== -led0 / user_led1_red Red PTE14 FXIO D7 / EMIOS0 CH19 -led1 / user_led1_green Green PTA27 FXIO D5 / EMIOS1 CH10 / EMIOS2 CH10 -led2 / user_led1_blue Blue PTE12 FXIO D8 / EMIOS1 CH5 -======================= ===== ===== =================================== - -The user can control the LEDs in any way. An output of ``0`` illuminates the LED. - -Buttons -------- - -The MR-CANHUBK3 board has two user buttons: - -======================= ===== ===== ============== -Devicetree node Label Pin Pin Functions -======================= ===== ===== ============== -sw0 / user_button_1 SW1 PTD15 EIRQ31 -sw0 / user_button_2 SW2 PTA25 EIRQ5 / WKPU34 -======================= ===== ===== ============== - -System Clock -============ - -The Arm Cortex-M7 (Lock-Step) are configured to run at 160 MHz. - -Serial Console -============== - -By default, the serial console is provided through ``lpuart2`` on the 7-pin -DCD-LZ debug connector ``P6``. - -========= ===== ============ -Connector Pin Pin Function -========= ===== ============ -P6.2 PTA9 LPUART2_TX -P6.3 PTA8 LPUART2_RX -========= ===== ============ - -CAN -=== - -CAN is provided through FLEXCAN interface with 6 instances. - -=============== ======= =============== ============= -Devicetree node Pin Pin Function Bus Connector -=============== ======= =============== ============= -flexcan0 | PTA6 | PTA6_CAN0_RX P12/P13 - | PTA7 | PTA7_CAN0_TX -flexcan1 | PTC9 | PTC9_CAN0_RX P14/P15 - | PTC8 | PTC8_CAN0_TX -flexcan2 | PTE25 | PTE25_CAN0_RX P16/P17 - | PTE24 | PTE24_CAN0_TX -flexcan3 | PTC29 | PTC29_CAN0_RX P18/019 - | PTC28 | PTC28_CAN0_TX -flexcan4 | PTC31 | PTC31_CAN0_RX P20/P21 - | PTC30 | PTC30_CAN0_TX -flexcan5 | PTC11 | PTC11_CAN0_RX P22/P23 - | PTC10 | PTC10_CAN0_TX -=============== ======= =============== ============= - -.. note:: - There is limitation by HAL SDK, so CAN only has support maximum 64 message buffers (MBs) - and support maximum 32 message buffers for concurrent active instances with 8 bytes - payload. We need to pay attention to configuration options: - - 1. :kconfig:option:`CONFIG_CAN_MAX_MB` must be less or equal than the - maximum number of message buffers that is according to the table below. - - 2. :kconfig:option:`CONFIG_CAN_MAX_FILTER` must be less or equal than - :kconfig:option:`CONFIG_CAN_MAX_MB`. - -=============== ========== ================ ================ -Devicetree node Payload Hardware support Software support -=============== ========== ================ ================ -flexcan0 | 8 bytes | 96 MBs | 64 MBs - | 16 bytes | 63 MBs | 42 MBs - | 32 bytes | 36 MBs | 24 MBs - | 64 bytes | 21 MBs | 14 MBs -flexcan1 | 8 bytes | 64 MBs | 64 MBs - | 16 bytes | 42 MBs | 42 MBs - | 32 bytes | 24 MBs | 24 MBs - | 64 bytes | 14 MBs | 14 MBs -flexcan2 | 8 bytes | 64 MBs | 64 MBs - | 16 bytes | 42 MBs | 42 MBs - | 32 bytes | 24 MBs | 24 MBs - | 64 bytes | 14 MBs | 14 MBs -flexcan3 | 8 bytes | 32 MBs | 32 MBs - | 16 bytes | 21 MBs | 21 MBs - | 32 bytes | 12 MBs | 12 MBs - | 64 bytes | 7 MBs | 7 MBs -flexcan4 | 8 bytes | 32 MBs | 32 MBs - | 16 bytes | 21 MBs | 21 MBs - | 32 bytes | 12 MBs | 12 MBs - | 64 bytes | 7 MBs | 7 MBs -flexcan5 | 8 bytes | 32 MBs | 32 MBs - | 16 bytes | 21 MBs | 21 MBs - | 32 bytes | 12 MBs | 12 MBs - | 64 bytes | 7 MBs | 7 MBs -=============== ========== ================ ================ - -.. note:: - A CAN bus usually requires 60 Ohm termination at both ends of the bus. This may be - accomplished using one of the included CAN termination boards. For more details, refer - to the section ``6.3 CAN Connectors`` in the Hardware User Manual of `NXP MR-CANHUBK3`_. - -I2C -=== - -I2C is provided through LPI2C interface with 2 instances ``lpi2c0`` and ``lpi2c1`` -on corresponding connectors ``P4``, ``P3``. - -========= ===== ============ -Connector Pin Pin Function -========= ===== ============ -P3.2 PTD9 LPI2C1_SCL -P3.3 PTD8 LPI2C1_SDA -P4.3 PTD14 LPI2C0_SCL -P4.4 PTD13 LPI2C0_SDA -========= ===== ============ - -ADC -=== - -ADC is provided through ADC SAR controller with 3 instances. ADC channels are divided into -3 groups (precision, standard and external). - -.. note:: - All channels of an instance only run on 1 group channel at the same time. - -FS26 SBC Watchdog -================= - -On normal operation after the board is powered on, there is a window of 256 ms -on which the FS26 watchdog must be serviced with a good token refresh, otherwise -the watchdog will signal a reset to the MCU. This board configuration enables -the FS26 watchdog driver that handles this initialization. - -.. note:: - - The FS26 can also be started in debug mode (watchdog disabled) following - these steps: - - 1. Power off the board. - 2. Remove the jumper ``JP1`` (pins 1-2 open), which is connected by default. - 3. Power on the board. - 4. Reconnect the jumper ``JP1`` (pins 1-2 shorted). - -External Flash -============== - -The on-board MX25L6433F 64M-bit multi-I/O Serial NOR Flash memory is connected -to the QSPI controller port A1. This board configuration selects it as the -default flash controller. - -Ethernet -======== - -This board has a single instance of Ethernet Media Access Controller (EMAC) -interfacing with a `NXP TJA1103`_ 100Base-T1 Ethernet PHY. Currently, there is -limited driver for this PHY that allows for overiding the default pin strapping configuration for -the PHY (RMII, master, autonomous mode enabled, polarity correction enabled) -to slave mode. - -The 100Base-T1 signals are available in connector ``P9`` and can be converted to -100Base-T using a Ethernet media converter such as `RDDRONE-T1ADAPT`_. - -Programming and Debugging -************************* - -Applications for the ``mr_canhubk3`` board can be built in the usual way as -documented in :ref:`build_an_application`. - -This board configuration supports `Lauterbach TRACE32`_ and `SEGGER J-Link`_ -West runners for flashing and debugging applications. Follow the steps described -in :ref:`lauterbach-trace32-debug-host-tools` and :ref:`jlink-debug-host-tools`, -to setup the flash and debug host tools for these runners, respectively. The -default runner is J-Link. - -Flashing -======== - -Run the ``west flash`` command to flash the application using SEGGER J-Link. -Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32. - -The Lauterbach TRACE32 runner supports additional options that can be passed -through command line: - -.. code-block:: console - - west flash -r trace32 --startup-args elfFile= loadTo= - eraseFlash= verifyFlash= - -Where: - -- ```` is the path to the Zephyr application ELF in the output - directory -- ``loadTo=flash`` loads the application to the SoC internal program flash - (:kconfig:option:`CONFIG_XIP` must be set), and ``loadTo=sram`` load the - application to SRAM. Default is ``flash``. -- ``eraseFlash=yes`` erases the whole content of SoC internal flash before the - application is downloaded to either Flash or SRAM. This routine takes time to - execute. Default is ``no``. -- ``verifyFlash=yes`` verify the SoC internal flash content after programming - (use together with ``loadTo=flash``). Default is ``no``. - -For example, to erase and verify flash content: - -.. code-block:: console - - west flash -r trace32 --startup-args elfFile=build/zephyr/zephyr.elf loadTo=flash eraseFlash=yes verifyFlash=yes - -Debugging -========= - -Run the ``west debug`` command to start a GDB session using SEGGER J-Link. -Alternatively, run ``west debug -r trace32`` to launch the Lauterbach TRACE32 -software debugging interface. - -References -********** - -.. target-notes:: - -.. _NXP MR-CANHUBK3: - https://www.nxp.com/design/development-boards/automotive-development-platforms/s32k-mcu-platforms/s32k344-evaluation-board-for-mobile-robotics-incorporating-100baset1-and-six-can-fd:MR-CANHUBK344 - -.. _NXP S32K344: - https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k3-microcontrollers-for-automotive-general-purpose:S32K3 - -.. _NXP FS26 Safety System Basis Chip: - https://www.nxp.com/products/power-management/pmics-and-sbcs/safety-sbcs/safety-system-basis-chip-with-low-power-fit-for-asil-d:FS26 - -.. _NXP TJA1103: - https://www.nxp.com/products/interfaces/ethernet-/automotive-ethernet-phys/asil-b-compliant-100base-t1-ethernet-phy:TJA1103 - -.. _RDDRONE-T1ADAPT: - https://www.nxp.com/products/interfaces/ethernet-/automotive-ethernet-phys/ethernet-media-converter-for-drones-rovers-mobile-robotics-and-automotive:RDDRONE-T1ADAPT - -.. _Lauterbach TRACE32: - https://www.lauterbach.com - -.. _SEGGER J-Link: - https://wiki.segger.com/NXP_S32K3xx diff --git a/boards/arm/msp_exp432p401r_launchxl/Kconfig b/boards/arm/msp_exp432p401r_launchxl/Kconfig deleted file mode 100644 index 13d6b2ad41a..00000000000 --- a/boards/arm/msp_exp432p401r_launchxl/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# TI MSP-EXP432P401R LaunchXL configuration - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MSP_EXP432P401R_LAUNCHXL - -endif # BOARD_MSP_EXP432P401R_LAUNCHXL diff --git a/boards/arm/msp_exp432p401r_launchxl/Kconfig.board b/boards/arm/msp_exp432p401r_launchxl/Kconfig.board deleted file mode 100644 index 3a15e56a5d4..00000000000 --- a/boards/arm/msp_exp432p401r_launchxl/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# TI SimpleLink MSP-EXP432P401R LaunchXL Development Board - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MSP_EXP432P401R_LAUNCHXL - bool "TI MSP-EXP432P401R LAUNCHXL" - depends on SOC_MSP432P401R diff --git a/boards/arm/msp_exp432p401r_launchxl/Kconfig.defconfig b/boards/arm/msp_exp432p401r_launchxl/Kconfig.defconfig deleted file mode 100644 index f3a70f2bb6b..00000000000 --- a/boards/arm/msp_exp432p401r_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# TI MSP-EXP432P401R LaunchXL development board configuration - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "msp_exp432p401r_launchxl" - depends on BOARD_MSP_EXP432P401R_LAUNCHXL diff --git a/boards/arm/msp_exp432p401r_launchxl/board.cmake b/boards/arm/msp_exp432p401r_launchxl/board.cmake deleted file mode 100644 index cbeaea2e456..00000000000 --- a/boards/arm/msp_exp432p401r_launchxl/board.cmake +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/msp_exp432p401r_launchxl/doc/index.rst b/boards/arm/msp_exp432p401r_launchxl/doc/index.rst deleted file mode 100644 index d2a2e12153a..00000000000 --- a/boards/arm/msp_exp432p401r_launchxl/doc/index.rst +++ /dev/null @@ -1,152 +0,0 @@ -.. _msp_exp432p401r_launchxl: - -MSP-EXP432P401R LaunchXL -######################## - -Overview -******** - -The SimpleLink MSP‐EXP432P401R LaunchPad development kit is an easy-to-use evaluation -module for the SimpleLink MSP432P401R microcontroller. It contains everything needed to start -developing on the SimpleLink MSP432 low-power + performance ARM |reg| 32-bit Cortex |reg|-M4F -microcontroller (MCU). - -.. figure:: img/msp_exp432p401r_launchxl.jpg - :align: center - :alt: MSP-EXP432P401R LaunchXL development board - -Features: -========= - -* Low-power ARM Cortex-M4F MSP432P401R -* 40-pin LaunchPad development kit standard that leverages the BoosterPack plug-in module ecosystem -* XDS110-ET, an open-source onboard debug probe featuring EnergyTrace+ technology and application - UART -* Two buttons and two LEDs for user interaction -* Backchannel UART through USB to PC - -Details on the MSP-EXP432P401R LaunchXL development board can be found in the -MSP-EXP432P401R LaunchXL User's Guide. - -Supported Features -================== - -* The on-board 32-kHz crystal allows for lower LPM3 sleep currents and a higher-precision clock source than the - default internal 32-kHz REFOCLK. Therefore, the presence of the crystal allows the full range of low- - power modes to be used. -* The on-board 48-MHz crystal allows the device to run at its maximum operating speed for MCLK and HSMCLK. - -The MSP-EXP432P401R LaunchXL development board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port | -+-----------+------------+-----------------------+ - -More details about the supported peripherals are available in MSP432P4XX TRM -Other hardware features are not currently supported by the Zephyr kernel. - -Building and Flashing -********************* - -Prerequisites: -============== - -#. Ensure the XDS-110 emulation firmware is updated. - - Download and install the latest `XDS-110 emulation package`_. - - Follow these `xds110 firmware update directions - `_ - - Note that the emulation package install may place the xdsdfu utility - in ``/ccs_base/common/uscif/xds110/``. - -#. Install OpenOCD - - You can obtain OpenOCD by following these - :ref:`installing the latest Zephyr SDK instructions `. - - After the installation, add the directory containing the OpenOCD executable - to your environment's PATH variable. For example, use this command in Linux: - - .. code-block:: console - - export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH - - If you had previously installed TI OpenOCD, you can simply switch to use - the one in the Zephyr SDK. If for some reason you wish to continue to use - your TI OpenOCD installation, you can set the OPENOCD and - OPENOCD_DEFAULT_PATH variables in - :zephyr_file:`boards/arm/msp_exp432p401r_launchxl/board.cmake` to point the build - to the paths of the OpenOCD binary and its scripts, before - including the common openocd.board.cmake file: - - .. code-block:: cmake - - set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) - set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - -Flashing -======== - -Follow the :ref:`getting_started` instructions for Zephyr application -development. - -For example, to build and flash the :ref:`hello_world` application for the -MSP-EXP432P401R LaunchXL: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: msp_exp432p401r_launchxl - :goals: flash - -This will load the image into flash. - -To see program output from UART0, connect a separate terminal window: - -.. code-block:: console - - % screen /dev/ttyACM0 115200 8N1 - -Then press the reset button (S3) on the board to run the program. - -Debugging -========= - -To debug a previously flashed image, after resetting the board, use the 'debug' -build target: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: msp_exp432p401r_launchxl - :maybe-skip-config: - :goals: debug - -References -********** - -TI MSP432 Wiki: - https://en.wikipedia.org/wiki/TI_MSP432 - -TI MSP432P401R Product Page: - http://www.ti.com/product/msp432p401r - -TI MSP432 SDK: - http://www.ti.com/tool/SIMPLELINK-MSP432-SDK - -.. _UniFlash: - http://processors.wiki.ti.com/index.php/UniFlash_v4_Quick_Guide#Command_Line_Interface - -.. _CCS IDE: - http://www.ti.com/tool/ccstudio - -.. _XDS-110 emulation package: - http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download diff --git a/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig b/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig deleted file mode 100644 index 01559c8be94..00000000000 --- a/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_MSP_EXP432P401R_LAUNCHXL=y -CONFIG_SOC_SERIES_MSP432P4XX=y -CONFIG_SOC_MSP432P401R=y -CONFIG_BUILD_OUTPUT_HEX=y - -# Floating point options -CONFIG_FPU=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/npcx4m8f_evb/Kconfig.board b/boards/arm/npcx4m8f_evb/Kconfig.board deleted file mode 100644 index 093faa1cade..00000000000 --- a/boards/arm/npcx4m8f_evb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NPCX4M8F_EVB - bool "Nuvoton NPCX4M8F EVB Development board" - depends on SOC_NPCX4M8F diff --git a/boards/arm/npcx4m8f_evb/Kconfig.defconfig b/boards/arm/npcx4m8f_evb/Kconfig.defconfig deleted file mode 100644 index ae6ce213595..00000000000 --- a/boards/arm/npcx4m8f_evb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NPCX4M8F_EVB - -config BOARD - default "npcx4m8f_evb" - -endif # BOARD_NPCX4M8F_EVB - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config INPUT - default y if KSCAN diff --git a/boards/arm/npcx4m8f_evb/doc/index.rst b/boards/arm/npcx4m8f_evb/doc/index.rst deleted file mode 100644 index a73d65d33da..00000000000 --- a/boards/arm/npcx4m8f_evb/doc/index.rst +++ /dev/null @@ -1,131 +0,0 @@ -.. _npcx4m8f_evb: - -Nuvoton NPCX4M8F_EVB -#################### - -Overview -******** - -The NPCX4M8F_EVB kit is a development platform to evaluate the -Nuvoton NPCX4 series microcontrollers. This board needs to be mated with -part number NPCX498F. - -.. image:: npcx4m8f_evb.jpg - :align: center - :alt: NPCX4M8F Evaluation Board - -Hardware -******** - -- ARM Cortex-M4F Processor -- 512 KB RAM and 64 KB boot ROM -- ADC & GPIO headers -- UART0 and UART1 -- FAN PWM interface -- Jtag interface -- Intel Modular Embedded Controller Card (MECC) headers - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc controller | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port/controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PM | on-chip | power management | -+-----------+------------+-------------------------------------+ -| PSL | on-chip | power switch logic | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pulse width modulator | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer sensor | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the defconfig file: -``boards/arm/npcx4m8f_evb/npcx4m8f_evb_defconfig`` - - -Connections and IOs -=================== - -Nuvoton to provide the schematic for this board. - -System Clock -============ - -The NPCX4M8F MCU is configured to use the 120Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock -control register (chapter 4 in user manual) - -Serial Port -=========== - -UART1 is configured for serial logs. - -Programming and Debugging -************************* - -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG-only sessions. - -Flashing -======== - -If the correct headers are installed, this board supports both J-TAG and also -the ChromiumOS servo. - -To flash using Servo V2, μServo, or Servo V4 (CCD), see the -`Chromium EC Flashing Documentation`_ for more information. - -To flash with J-TAG, install the drivers for your programmer, for example: -SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ - -The openocd from Zephyr SDK 0.16.1 doesn't include npcx4 support, so build openocd from source.:: - - sudo apt-get install libftdi-dev libusb-1.0.0-dev - git clone https://git.code.sf.net/p/openocd/code ~/openocd - cd ~/openocd - ./bootstrap - ./configure --enable-jlink --enable-ftdi - make clean - make - sudo make install - -Build and flash the blinky sample.:: - - west build -t clean && \ - west build -c -p auto -b npcx4m8f_evb samples/basic/blinky && \ - west flash --openocd /usr/local/bin/openocd - -Debugging -========= - -Use JTAG/SWD with a J-Link - -References -********** -.. target-notes:: - -.. _Chromium EC Flashing Documentation: - https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/npcx7m6fb_evb/Kconfig.board b/boards/arm/npcx7m6fb_evb/Kconfig.board deleted file mode 100644 index 84b39c5a9ae..00000000000 --- a/boards/arm/npcx7m6fb_evb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NPCX7M6FB_EVB - bool "Nuvoton NPCX7M6FB EVB Development board" - depends on SOC_NPCX7M6FB diff --git a/boards/arm/npcx7m6fb_evb/Kconfig.defconfig b/boards/arm/npcx7m6fb_evb/Kconfig.defconfig deleted file mode 100644 index 70a12bbdcb0..00000000000 --- a/boards/arm/npcx7m6fb_evb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NPCX7M6FB_EVB - -config BOARD - default "npcx7m6fb_evb" - -endif # BOARD_NPCX7M6FB_EVB - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config INPUT - default y if KSCAN diff --git a/boards/arm/npcx7m6fb_evb/doc/index.rst b/boards/arm/npcx7m6fb_evb/doc/index.rst deleted file mode 100644 index 7222aac1ebb..00000000000 --- a/boards/arm/npcx7m6fb_evb/doc/index.rst +++ /dev/null @@ -1,107 +0,0 @@ -.. _npcx7m6fb_evb: - -Nuvoton NPCX7M6FB_EVB -##################### - -Overview -******** - -The NPCX7M6FB_EVB kit is a development platform to evaluate the -Nuvoton NPCX7 series microcontrollers. This board needs to be mated with -part number NPCX796FB. - -.. image:: npcx7m6fb_evb.jpg - :align: center - :alt: NPCX7M6FB Evaluation Board - -Hardware -******** - -- ARM Cortex-M4F Processor -- 256 KB RAM and 64 KB boot ROM -- ADC & GPIO headers -- UART0 and UART1 -- FAN PWM interface -- Jtag interface -- Intel Modular Embedded Controller Card (MECC) headers - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the defconfig file: -``boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig`` - - -Connections and IOs -=================== - -Nuvoton to provide the schematic for this board. - -System Clock -============ - -The NPCX7M6FB MCU is configured to use the 90Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock -control register (chapter 4 in user manual) - -Serial Port -=========== - -UART1 is configured for serial logs. - - -Programming and Debugging -************************* - -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG only sessions. - -Flashing -======== - -If the correct IDC headers are installed, this board supports both J-TAG and -also the ChromiumOS servo. - -To flash using Servo V2, μServo, or Servo V4 (CCD), see the -`Chromium EC Flashing Documentation`_ for more information. - -To flash with J-TAG, install the drivers for your programmer, for example: -SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: npcx7m6fb_evb - :maybe-skip-config: - :goals: build flash - -Debugging -========= - -Use JTAG/SWD with a J-Link - -References -********** -.. target-notes:: - -.. _Chromium EC Flashing Documentation: - https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/npcx9m6f_evb/Kconfig.board b/boards/arm/npcx9m6f_evb/Kconfig.board deleted file mode 100644 index a652be619d0..00000000000 --- a/boards/arm/npcx9m6f_evb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NPCX9M6F_EVB - bool "Nuvoton NPCX9M6F EVB Development board" - depends on SOC_NPCX9M6F diff --git a/boards/arm/npcx9m6f_evb/Kconfig.defconfig b/boards/arm/npcx9m6f_evb/Kconfig.defconfig deleted file mode 100644 index d5953dd04fe..00000000000 --- a/boards/arm/npcx9m6f_evb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NPCX9M6F_EVB - -config BOARD - default "npcx9m6f_evb" - -endif # BOARD_NPCX9M6F_EVB - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config INPUT - default y if KSCAN diff --git a/boards/arm/npcx9m6f_evb/doc/index.rst b/boards/arm/npcx9m6f_evb/doc/index.rst deleted file mode 100644 index 898f3051220..00000000000 --- a/boards/arm/npcx9m6f_evb/doc/index.rst +++ /dev/null @@ -1,121 +0,0 @@ -.. _npcx9m6f_evb: - -Nuvoton NPCX9M6F_EVB -#################### - -Overview -******** - -The NPCX9M6F_EVB kit is a development platform to evaluate the -Nuvoton NPCX9 series microcontrollers. This board needs to be mated with -part number NPCX996F. - -.. image:: npcx9m6f_evb.jpg - :align: center - :alt: NPCX9M6F Evaluation Board - -Hardware -******** - -- ARM Cortex-M4F Processor -- 256 KB RAM and 64 KB boot ROM -- ADC & GPIO headers -- UART0 and UART1 -- FAN PWM interface -- Jtag interface -- Intel Modular Embedded Controller Card (MECC) headers - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc controller | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port/controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PM | on-chip | power management | -+-----------+------------+-------------------------------------+ -| PSL | on-chip | power switch logic | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pulse width modulator | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer sensor | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the defconfig file: -``boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig`` - - -Connections and IOs -=================== - -Nuvoton to provide the schematic for this board. - -System Clock -============ - -The NPCX9M6F MCU is configured to use the 90Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock -control register (chapter 4 in user manual) - -Serial Port -=========== - -UART1 is configured for serial logs. - - -Programming and Debugging -************************* - -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG-only sessions. - -Flashing -======== - -If the correct IDC headers are installed, this board supports both J-TAG and -also the ChromiumOS servo. - -To flash using Servo V2, μServo, or Servo V4 (CCD), see the -`Chromium EC Flashing Documentation`_ for more information. - -To flash with J-TAG, install the drivers for your programmer, for example: -SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: npcx9m6f_evb - :maybe-skip-config: - :goals: build flash - -Debugging -========= - -Use JTAG/SWD with a J-Link - -References -********** -.. target-notes:: - -.. _Chromium EC Flashing Documentation: - https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/nrf21540dk_nrf52840/Kconfig b/boards/arm/nrf21540dk_nrf52840/Kconfig deleted file mode 100644 index 67b25837390..00000000000 --- a/boards/arm/nrf21540dk_nrf52840/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF21540 DK NRF52840 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF21540DK_NRF52840 diff --git a/boards/arm/nrf21540dk_nrf52840/Kconfig.board b/boards/arm/nrf21540dk_nrf52840/Kconfig.board deleted file mode 100644 index b2c9c86d53e..00000000000 --- a/boards/arm/nrf21540dk_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF21540 DK NRF52840 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF21540DK_NRF52840 - bool "nRF21540 DK NRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf21540dk_nrf52840/Kconfig.defconfig b/boards/arm/nrf21540dk_nrf52840/Kconfig.defconfig deleted file mode 100644 index 71cb76615ed..00000000000 --- a/boards/arm/nrf21540dk_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF21540 DK NRF52840 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF21540DK_NRF52840 - -config BOARD - default "nrf21540dk_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_NRF21540DK_NRF52840 diff --git a/boards/arm/nrf21540dk_nrf52840/doc/index.rst b/boards/arm/nrf21540dk_nrf52840/doc/index.rst deleted file mode 100644 index 617f240b0a9..00000000000 --- a/boards/arm/nrf21540dk_nrf52840/doc/index.rst +++ /dev/null @@ -1,236 +0,0 @@ -.. _nrf21540dk_nrf52840: - -nRF21540 DK -########### - -Overview -******** -The nRF21540 DK (PCA10112) shows possibility of the Nordic Semiconductor -nRF21540 Front End Module connected with nRF52840 ARM Cortex-M4F CPU. -The CPU provides support for the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf21540dk_nrf52840.jpg - :align: center - :alt: nRF21540 DK - - nRF21540 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the `nRF21540 website`_. -The `Nordic Semiconductor Infocenter`_ contains the processor's and front end -module's information and the datasheet. - -Hardware -******** - -The nRF52840 on the nRF21540 DK has two external oscillators. The frequency -of the slow clock is 32.768 kHz. The frequency of the main clock is 32 MHz. - -Supported Features -================== - -The nrf21540dk_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF52840 Product Specification`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF21540 Development Kit board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (green) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -Front End Module ----------------- - -* MOSI = P1.13 -* MISO = P1.14 -* CLOCK = P1.15 -* CHIP SELECT = P0.21 -* PDN = P0.23 -* MODE = P0.17 -* RXEN = P0.19 -* ANTSEL = P0.20 -* TXEN = P0.22 - -Programming and Debugging -************************* - -Applications for the ``nrf21540dk_nrf52840`` board configuration can be built, -flashed, and debugged in the usual way. See :ref:`build_an_application` and -:ref:`application_run` for more details on building and running. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF21540 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf21540dk_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF21540 DK -*********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.dts`. - -Changing UART1 pins -******************* - -The following approach can be used when an application needs to use another set -of pins for UART1: - -1. Add devicetree overlay file to the main directory of your application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default_alt: uart1_default_alt { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep_alt: uart1_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - pinctrl-0 = <&uart1_default_alt>; - /* if sleep state is not used, use /delete-property/ pinctrl-1; and - * skip the "sleep" entry. - */ - pinctrl-1 = <&uart1_sleep_alt>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX - -See :ref:`set-devicetree-overlays` for further details. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the `nRF52840 Product Specification`_, chapter 7 'Hardware and Layout'. -In the table 7.1.1 'aQFN73 ball assignments' select the pins marked -'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used -in under-10KHz applications. They are not suitable for 115200 speed of UART. - -References -********** - -.. target-notes:: - -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _nRF21540 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF21540 -.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf -.. _nRF21540 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF21540_PS_v1.0.pdf diff --git a/boards/arm/nrf51_ble400/Kconfig.board b/boards/arm/nrf51_ble400/Kconfig.board deleted file mode 100644 index 111b359355b..00000000000 --- a/boards/arm/nrf51_ble400/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51 BLE400 board configuration - -# Copyright (c) 2018 Roman Tataurov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF51_BLE400 - bool "nRF51 BLE400" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51_ble400/Kconfig.defconfig b/boards/arm/nrf51_ble400/Kconfig.defconfig deleted file mode 100644 index 7f453a497bd..00000000000 --- a/boards/arm/nrf51_ble400/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF51 BLE400 board configuration - -# Copyright (c) 2018 Roman Tataurov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF51_BLE400 - -config BOARD - default "nrf51_ble400" - -config BT_CTLR - default BT - -endif # BOARD_NRF51_BLE400 diff --git a/boards/arm/nrf51_ble400/doc/index.rst b/boards/arm/nrf51_ble400/doc/index.rst deleted file mode 100644 index d746806faa1..00000000000 --- a/boards/arm/nrf51_ble400/doc/index.rst +++ /dev/null @@ -1,223 +0,0 @@ -.. _nrf51_ble400: - -Waveshare BLE400 -################# - -Overview -******** - -BLE400 is a motherboard designed for BLE Bluetooth 2.4G Wireless Module. Used together with core board -- Core51822. - -Supported Features -================== - -Motherboard ------------- - -- Onboard battery holder, multi power supplies are available -- All the IOs are accessible for easy expansion -- Integrates CP2102 for debugging -- LEDs and user keys, compatible with other official boards, easy to use - -Core board ----------- - -- Onboard chip: nRF51822 -- Communication distance (open outdoor 1M data rate): 30m -- Frequency range: 2.4GHz -- Operating voltage: 2.0V ~ 3.6V -- Operating temperature: -40℃ ~ 85℃ -- Expansion pinheader: all the I/Os except P0.26 and P0.27 -- Pinheader pitch: 2.00mm -- Antenna: onboard antenna - -Features -======== - -- 2.4 GHz multiprotocol RF transceiver -- ARM® Cortex™-M0 32 bit processor -- 128 bit AES HW encryption -- 256kB flash & 32kB RAM -- Programmable Peripheral Interconnect (PPI) -- Digital interfaces: SPI, I2C, UART -- 10 bit ADC -- Programmable output power: -20 to +4 dBm -- Independent application development and protocol stack -- Fully compatible with NRF24L series -- Pinout compatible with NRF51xxx series -- Global separate power management -- Operating voltage: 1.8 V ~ 3.6 V - -Revision History -================ - -Core board ----------- - -In June of 2015, Core51822 and its variant, Core51822 (B), upgraded the onboard chip to Rev3 (nRF51822_QFAC) that features 32kB RAM. - -.. image:: img/Core51822-Compare.jpg - :align: center - :alt: Compare - -Top: Core51822 -Bottom: Core51822 (B) - -Connections and IOs -==================== - -Motherboard ------------- - -.. image:: img/nrf51_ble400.jpg - :align: center - :alt: BLE400 - -1. Wireless module connector: for easily connecting modules like Core51822 -2. MCU pins expansion connector -3. I2C interface -4. SPI interface -5. 5V/3.3V power input/output: usually used as power output, also common-grounding with other user board -6. USB connector: USB TO UART via onboard converter CP2102 -7. Debugging interface -8. UART interface -9. Battery holder -10. User LEDs -11. User keys -12. Reset button -13. CP2102 -14. USB TO UART jumper -15. LEDs & Keys jumper - -Core board ----------- - -.. image:: img/Core51822-pin.jpg - :align: center - :alt: Core board pinout - -BLE400 dimensions -================= - -.. image:: img/BLE400-size.jpg - :align: center - :alt: BLE400 size - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.18 -* LED1 (red) = P0.19 -* LED2 (red) = P0.20 -* LED3 (red) = P0.21 -* LED4 (red) = P0.22 -* SUSPEND = SUSPEND -* RXD1 = P0.9 -* TXD1 = P0.11 - -Push buttons ------------- - -* KEY1 = P0.16 -* KEY2 = P0.17 -* RESET = SWDIO - -I2C ---- - -* SMBA = P0.02 -* SCL = P0.01 -* SDA = P0.00 - -SPI ---- - -* NSS = P0.30 -* SCK = P0.25 -* MOSI = P0.24 -* MISO = P0.23 - -USART1 ------- - -* RX = P0.05 -* TX = P0.06 -* CTS = P0.07 -* RTS = P0.12 - -UART (USB) ----------- - -* RX = P0.9 -* TX = P0.11 -* CTS = P0.8 -* RTS = P0.10 - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF51 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf51_ble400 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF51 DK -******************************************** - -There are samples below that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -- :zephyr:code-sample:`blinky` -- :zephyr:code-sample:`button` -- :zephyr:code-sample:`fade-led` -- :zephyr:code-sample:`multi-thread-blinky` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf51_ble400/nrf51_ble400.dts`. - -References -********** - -.. target-notes:: - -.. _nRF51 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF51-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Waveshare Wiki BLE400: https://www.waveshare.com/wiki/BLE400 -.. _Waveshare WiKi Core51822: https://www.waveshare.com/wiki/Core51822 -.. _User manual: https://www.waveshare.com/w/upload/b/b7/NRF51822-Eval-Kit-UserManual-EN.pdf -.. _Schematic: https://www.waveshare.com/w/upload/1/1b/BLE400-Schematic.pdf -.. _Code samples: https://www.waveshare.com/w/upload/5/53/NRF51822-Code.7z -.. _Core board schematics: https://www.waveshare.com/w/upload/5/57/Core51822-Schematic.pdf diff --git a/boards/arm/nrf51_ble400/nrf51_ble400_defconfig b/boards/arm/nrf51_ble400/nrf51_ble400_defconfig deleted file mode 100644 index 34fd08c47d5..00000000000 --- a/boards/arm/nrf51_ble400/nrf51_ble400_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y -CONFIG_BOARD_NRF51_BLE400=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51_blenano/Kconfig.board b/boards/arm/nrf51_blenano/Kconfig.board deleted file mode 100644 index a708a1ac5df..00000000000 --- a/boards/arm/nrf51_blenano/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51 BLENANO board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF51_BLENANO - bool "nRF51 BLENANO" - depends on SOC_NRF51822_QFAA diff --git a/boards/arm/nrf51_blenano/Kconfig.defconfig b/boards/arm/nrf51_blenano/Kconfig.defconfig deleted file mode 100644 index 57a6b286d4d..00000000000 --- a/boards/arm/nrf51_blenano/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF51 BLENANO board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF51_BLENANO - -config BOARD - default "nrf51_blenano" - -config BT_CTLR - default BT - -endif # BOARD_NRF51_BLENANO diff --git a/boards/arm/nrf51_blenano/nrf51_blenano_defconfig b/boards/arm/nrf51_blenano/nrf51_blenano_defconfig deleted file mode 100644 index 7bd3f7c6736..00000000000 --- a/boards/arm/nrf51_blenano/nrf51_blenano_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAA=y -CONFIG_BOARD_NRF51_BLENANO=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51_vbluno51/Kconfig.board b/boards/arm/nrf51_vbluno51/Kconfig.board deleted file mode 100644 index d0e686662a4..00000000000 --- a/boards/arm/nrf51_vbluno51/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51-VBLUNO51 board configuration - -# Copyright (c) 2017 VNG IoT Lab Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF51_VBLUNO51 - bool "nRF51 VBLUno51 BLE" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51_vbluno51/Kconfig.defconfig b/boards/arm/nrf51_vbluno51/Kconfig.defconfig deleted file mode 100644 index bcb1c0d2160..00000000000 --- a/boards/arm/nrf51_vbluno51/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF51 VBLUno51 board configuration - -# Copyright (c) 2017 VNG IoT Lab Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF51_VBLUNO51 - -config BOARD - default "nrf51_vbluno51" - -config BT_CTLR - default BT - -endif # BOARD_NRF51_VBLUNO51 diff --git a/boards/arm/nrf51_vbluno51/nrf51_vbluno51_defconfig b/boards/arm/nrf51_vbluno51/nrf51_vbluno51_defconfig deleted file mode 100644 index 09836ecc779..00000000000 --- a/boards/arm/nrf51_vbluno51/nrf51_vbluno51_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y -CONFIG_BOARD_NRF51_VBLUNO51=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51dk_nrf51422/Kconfig.board b/boards/arm/nrf51dk_nrf51422/Kconfig.board deleted file mode 100644 index 0d93e231820..00000000000 --- a/boards/arm/nrf51dk_nrf51422/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51 DK NRF51422 board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF51DK_NRF51422 - bool "nRF51 DK NRF51422" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51dk_nrf51422/Kconfig.defconfig b/boards/arm/nrf51dk_nrf51422/Kconfig.defconfig deleted file mode 100644 index 54d65d88a5e..00000000000 --- a/boards/arm/nrf51dk_nrf51422/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF51 DK NRF51422 board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF51DK_NRF51422 - -config BOARD - default "nrf51dk_nrf51422" - -config BT_CTLR - default BT - -endif # BOARD_NRF51DK_NRF51422 diff --git a/boards/arm/nrf51dk_nrf51422/doc/index.rst b/boards/arm/nrf51dk_nrf51422/doc/index.rst deleted file mode 100644 index 5a3b11bf17a..00000000000 --- a/boards/arm/nrf51dk_nrf51422/doc/index.rst +++ /dev/null @@ -1,159 +0,0 @@ -.. _nrf51dk_nrf51422: - -nRF51 DK -######## - -Overview -******** - -The nRF51 Development Kit (PCA10028) hardware provides support for the Nordic -Semiconductor nRF51422 ARM Cortex-M0 CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf51dk_nrf51422.jpg - :align: center - :alt: nRF51 DK - - nRF51 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the -`nRF51 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF51 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 16 MHz. - -Supported Features -================== - -The nrf51dk_nrf51422 board configuration supports the following nRF51 -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF51 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF51 Development Kit board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.21 -* LED2 (green) = P0.22 -* LED3 (green) = P0.23 -* LED4 (green) = P0.24 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.17 -* BUTTON2 = SW2 = P0.18 -* BUTTON3 = SW3 = P0.19 -* BUTTON4 = SW4 = P0.20 -* BOOT = SW5 = boot/reset - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF51 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf51dk_nrf51422 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF51 DK -******************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.dts`. - -References -********** - -.. target-notes:: - -.. _nRF51 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF51-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.dts b/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.dts deleted file mode 100644 index cf18877f017..00000000000 --- a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.dts +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2017 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf51dk_nrf51422-pinctrl.dtsi" -#include - -/ { - model = "Nordic nRF51 DK NRF51422"; - compatible = "nordic,nrf51-dk-nrf51422"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - label = "Green LED 0"; - }; - led1: led_1 { - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - label = "Green LED 1"; - }; - led2: led_2 { - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - label = "Green LED 2"; - }; - led3: led_3 { - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - label = "Green LED 3"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 17 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 0"; - zephyr,code = ; - }; - button1: button_1 { - gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 1"; - zephyr,code = ; - }; - button2: button_2 { - gpios = <&gpio0 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 2"; - zephyr,code = ; - }; - button3: button_3 { - gpios = <&gpio0 20 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 3"; - zephyr,code = ; - }; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - led3 = &led3; - pwm-led0 = &pwm_led0; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - sw3 = &button3; - bootloader-led0 = &led0; - mcuboot-button0 = &button0; - mcuboot-led0 = &led0; - watchdog0 = &wdt0; - }; -}; - -&sw_pwm { - status ="okay"; - channel-gpios = <&gpio0 21 PWM_POLARITY_INVERTED>; - clock-prescaler = <8>; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&uart0 { - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_default>; - pinctrl-1 = <&i2c0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&i2c1 { - /* Cannot be used together with spi1. */ - /* status = "okay"; */ - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi0 { - /* Cannot be used together with i2c0. */ - /* status = "okay"; */ - pinctrl-0 = <&spi0_default>; - pinctrl-1 = <&spi0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi1 { - compatible = "nordic,nrf-spi"; - status = "okay"; - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x8000>; - }; - slot0_partition: partition@8000 { - label = "image-0"; - reg = <0x00008000 0x1b000>; - }; - slot1_partition: partition@23000 { - label = "image-1"; - reg = <0x00023000 0x1b000>; - }; - storage_partition: partition@3e000 { - label = "storage"; - reg = <0x0003e000 0x00002000>; - }; - }; -}; diff --git a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.yaml b/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.yaml deleted file mode 100644 index 8b521b57d90..00000000000 --- a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.yaml +++ /dev/null @@ -1,24 +0,0 @@ -identifier: nrf51dk_nrf51422 -name: nRF51-DK-NRF51422 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32 -flash: 256 -supported: - - adc - - ble - - counter - - gpio - - i2c - - nvs - - pwm - - spi - - watchdog -testing: - ignore_tags: - - net -vendor: nordic diff --git a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422_defconfig b/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422_defconfig deleted file mode 100644 index 7cd29568889..00000000000 --- a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y -CONFIG_BOARD_NRF51DK_NRF51422=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51dongle_nrf51422/Kconfig.board b/boards/arm/nrf51dongle_nrf51422/Kconfig.board deleted file mode 100644 index 733c12ea3a6..00000000000 --- a/boards/arm/nrf51dongle_nrf51422/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51 Dongle NRF51422 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF51DONGLE_NRF51422 - bool "nRF51 Dongle NRF51422" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51dongle_nrf51422/Kconfig.defconfig b/boards/arm/nrf51dongle_nrf51422/Kconfig.defconfig deleted file mode 100644 index baad053baca..00000000000 --- a/boards/arm/nrf51dongle_nrf51422/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF51 Dongle NRF51422 board configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF51DONGLE_NRF51422 - -config BOARD - default "nrf51dongle_nrf51422" - -config BT_CTLR - default BT - -endif # BOARD_NRF51DONGLE_NRF51422 diff --git a/boards/arm/nrf51dongle_nrf51422/doc/index.rst b/boards/arm/nrf51dongle_nrf51422/doc/index.rst deleted file mode 100644 index 1f73d1f9e08..00000000000 --- a/boards/arm/nrf51dongle_nrf51422/doc/index.rst +++ /dev/null @@ -1,144 +0,0 @@ -.. _nrf51dongle_nrf51422: - -nRF51 Dongle -############ - -Overview -******** - -The nRF51 Dongle (PCA10031) hardware provides support for the Nordic -Semiconductor nRF51822 ARM Cortex-M0 CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf51dongle_nrf51422.jpg - :align: center - :alt: nRF51 Dongle - - nRF51 Dongle (Credit: Nordic Semiconductor) - -More information about the board can be found at the -`nRF51 Dongle website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF51 Dongle has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 16 MHz. - -Supported Features -================== - -The nrf51dongle_nrf51422 board configuration supports the following nRF51 -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF51 Dongle website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF51 Dongle hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.21 -* LED1 (green) = P0.22 -* LED1 (blue) = P0.23 - -Push buttons ------------- - -* BOOT = SW1 = boot/reset - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF51 Dongle -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf51dongle_nrf51422 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -Testing the LEDs on the nRF51 Dongle -************************************ - -Build and flash the :zephyr:code-sample:`blinky` sample to test that the onboard LED -is working properly with Zephyr. - -References -********** - -.. target-notes:: - -.. _nRF51 Dongle website: http://www.nordicsemi.com/eng/Products/nRF51-Dongle -.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.dts b/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.dts deleted file mode 100644 index 59751e80840..00000000000 --- a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.dts +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2018 Nordic Semiconductor ASA. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf51dongle_nrf51422-pinctrl.dtsi" - -/ { - model = "Nordic nRF51 Dongle NRF51422"; - compatible = "nordic,nrf51-dongle-nrf51422"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - led0_red: led_0 { - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - label = "Red LED 0"; - }; - led0_green: led_1 { - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - label = "Green LED 0"; - }; - led0_blue: led_2 { - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - label = "Blue LED 0"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0_red; - led1 = &led0_green; - led2 = &led0_blue; - pwm-led0 = &pwm_led0; - watchdog0 = &wdt0; - }; -}; - -&sw_pwm { - status ="okay"; - channel-gpios = <&gpio0 21 PWM_POLARITY_INVERTED>; - clock-prescaler = <8>; -}; - -&gpiote { - status ="okay"; -}; - -&gpio0 { - status ="okay"; -}; - -&adc { - status ="okay"; -}; - -&uart0 { - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x8000>; - }; - slot0_partition: partition@8000 { - label = "image-0"; - reg = <0x00008000 0x1b000>; - }; - slot1_partition: partition@23000 { - label = "image-1"; - reg = <0x00023000 0x1b000>; - }; - storage_partition: partition@3e000 { - label = "storage"; - reg = <0x0003e000 0x00002000>; - }; - }; -}; diff --git a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.yaml b/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.yaml deleted file mode 100644 index 906fce5febf..00000000000 --- a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf51dongle_nrf51422 -name: nRF51-Dongle-nRF51422 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32 -flash: 256 -supported: - - ble - - nvs -vendor: nordic diff --git a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422_defconfig b/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422_defconfig deleted file mode 100644 index c937ab159c8..00000000000 --- a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y -CONFIG_BOARD_NRF51DONGLE_NRF51422=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52832_mdk/Kconfig.board b/boards/arm/nrf52832_mdk/Kconfig.board deleted file mode 100644 index 1707bf29216..00000000000 --- a/boards/arm/nrf52832_mdk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52832-MDK board configuration - -# Copyright (c) 2018 makerdiary.com. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52832_MDK - bool "nRF52832-MDK" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52832_mdk/Kconfig.defconfig b/boards/arm/nrf52832_mdk/Kconfig.defconfig deleted file mode 100644 index 0e5c3fd7817..00000000000 --- a/boards/arm/nrf52832_mdk/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52832-MDK board configuration - -# Copyright (c) 2018 makerdiary.com. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52832_MDK - -config BOARD - default "nrf52832_mdk" - -config BT_CTLR - default BT - -endif # BOARD_NRF52832_MDK diff --git a/boards/arm/nrf52832_mdk/nrf52832_mdk_defconfig b/boards/arm/nrf52832_mdk/nrf52832_mdk_defconfig deleted file mode 100644 index 732b02a3610..00000000000 --- a/boards/arm/nrf52832_mdk/nrf52832_mdk_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52832_MDK=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52833dk_nrf52820/CMakeLists.txt b/boards/arm/nrf52833dk_nrf52820/CMakeLists.txt deleted file mode 100644 index 413dee8fe2a..00000000000 --- a/boards/arm/nrf52833dk_nrf52820/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# The nrf52833dk_nrf52820 board mirrors the nRF52833 DK hardware. This -# needs to be considered by certain system initialization functionality -# residing in system_nrf52820.c and SoC dependent routines in nrfx_coredep.h. -zephyr_compile_definitions(DEVELOP_IN_NRF52833) -zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) diff --git a/boards/arm/nrf52833dk_nrf52820/Kconfig b/boards/arm/nrf52833dk_nrf52820/Kconfig deleted file mode 100644 index 03f71c60aea..00000000000 --- a/boards/arm/nrf52833dk_nrf52820/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52833DK nRF52820 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52833DK_NRF52820 diff --git a/boards/arm/nrf52833dk_nrf52820/Kconfig.board b/boards/arm/nrf52833dk_nrf52820/Kconfig.board deleted file mode 100644 index 5be8867d804..00000000000 --- a/boards/arm/nrf52833dk_nrf52820/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52833DK nRF52820 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52833DK_NRF52820 - bool "nRF52833 DK NRF52820" - depends on SOC_NRF52820_QDAA diff --git a/boards/arm/nrf52833dk_nrf52820/Kconfig.defconfig b/boards/arm/nrf52833dk_nrf52820/Kconfig.defconfig deleted file mode 100644 index 705821fa71d..00000000000 --- a/boards/arm/nrf52833dk_nrf52820/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52833DK nRF52820 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52833DK_NRF52820 - -config BOARD - default "nrf52833dk_nrf52820" - -config BT_CTLR - default BT - -endif # BOARD_NRF52833DK_NRF52820 diff --git a/boards/arm/nrf52833dk_nrf52820/board.cmake b/boards/arm/nrf52833dk_nrf52820/board.cmake deleted file mode 100644 index f7046fc0a1f..00000000000 --- a/boards/arm/nrf52833dk_nrf52820/board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=nRF52833_xxAA" "--speed=4000") -board_runner_args(pyocd "--target=nrf52820" "--frequency=4000000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/nrf52833dk_nrf52820/doc/index.rst b/boards/arm/nrf52833dk_nrf52820/doc/index.rst deleted file mode 100644 index e652e8735eb..00000000000 --- a/boards/arm/nrf52833dk_nrf52820/doc/index.rst +++ /dev/null @@ -1,23 +0,0 @@ -.. _nrf52833dk_nrf52820: - -nRF52820 emulation on nRF52833 DK -################################# - -Overview -******** - -The nrf52833dk_nrf52820 board is a modified version of the -:ref:`nrf52833dk_nrf52833` that enforces the limitations imposed by the nRF52820 -IC, which is a variant of the original nRF52833. Since Nordic does not offer a -development kit for the nRF52820 you can use this board to develop for this IC -while using the nRF52833 Development Kit (PCA10100). - -See :ref:`nrf52833dk_nrf52833` for more information about the development board -and `nRF52820 website`_ for the official reference on the IC itself. - -References -********** - -.. target-notes:: - -.. _nRF52820 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52820 diff --git a/boards/arm/nrf52833dk_nrf52833/Kconfig b/boards/arm/nrf52833dk_nrf52833/Kconfig deleted file mode 100644 index 4b620ad5557..00000000000 --- a/boards/arm/nrf52833dk_nrf52833/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52833 DK NRF52833 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52833DK_NRF52833 diff --git a/boards/arm/nrf52833dk_nrf52833/Kconfig.board b/boards/arm/nrf52833dk_nrf52833/Kconfig.board deleted file mode 100644 index 11ab4befc97..00000000000 --- a/boards/arm/nrf52833dk_nrf52833/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52833 DK NRF52833 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52833DK_NRF52833 - bool "NRF52833 DK NRF52833" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/nrf52833dk_nrf52833/Kconfig.defconfig b/boards/arm/nrf52833dk_nrf52833/Kconfig.defconfig deleted file mode 100644 index 6ec17b78864..00000000000 --- a/boards/arm/nrf52833dk_nrf52833/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52833 DK NRF52833 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52833DK_NRF52833 - -config BOARD - default "nrf52833dk_nrf52833" - -config BT_CTLR - default BT - -endif # BOARD_NRF52833DK_NRF52833 diff --git a/boards/arm/nrf52833dk_nrf52833/doc/index.rst b/boards/arm/nrf52833dk_nrf52833/doc/index.rst deleted file mode 100644 index 126b1266d52..00000000000 --- a/boards/arm/nrf52833dk_nrf52833/doc/index.rst +++ /dev/null @@ -1,217 +0,0 @@ -.. _nrf52833dk_nrf52833: - -nRF52833 DK -########### - -Overview -******** - -The nRF52833 Development Kit (PCA10100) hardware provides -support for the Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -More information about the board can be found at the -`nRF52833 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF52833 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf52833dk_nrf52833 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF52833 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF52833 Development Kit board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (green) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -Programming and Debugging -************************* - -Applications for the ``nrf52833dk_nrf52833`` board configuration can be built, -flashed, and debugged in the usual way. See :ref:`build_an_application` and -:ref:`application_run` for more details on building and running. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF52 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52833dk_nrf52833 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF52833 DK -*********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.dts`. - -Changing UART1 pins -******************* - -The following approach can be used when an application needs to use another set -of pins for UART1: - -1. Add devicetree overlay file to the main directory of your application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default_alt: uart1_default_alt { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep_alt: uart1_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - pinctrl-0 = <&uart1_default_alt>; - /* if sleep state is not used, use /delete-property/ pinctrl-1; and - * skip the "sleep" entry. - */ - pinctrl-1 = <&uart1_sleep_alt>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX - -See :ref:`set-devicetree-overlays` for further details. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the `nRF52833 Product Specification`_, chapter 7 'Hardware and Layout'. -In the table 7.1.1 'aQFN73 ball assignments' select the pins marked -'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used -in under-10KHz applications. They are not suitable for 115200 speed of UART. - -References -********** - -.. target-notes:: - -.. _nRF52833 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _nRF52833 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52833_OPS_v0.7.pdf diff --git a/boards/arm/nrf52840_blip/Kconfig.board b/boards/arm/nrf52840_blip/Kconfig.board deleted file mode 100644 index 12236998c6d..00000000000 --- a/boards/arm/nrf52840_blip/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Electronut Labs Blip board configuration - -# Copyright (c) 2018 Electronut Labs -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840_BLIP - bool "Electronut Labs Blip" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_blip/Kconfig.defconfig b/boards/arm/nrf52840_blip/Kconfig.defconfig deleted file mode 100644 index ab5424a1dd0..00000000000 --- a/boards/arm/nrf52840_blip/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Electronut Labs Blip board configuration - -# Copyright (c) 2018 Electronut Labs -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840_BLIP - -config BOARD - default "nrf52840_blip" - -config BT_CTLR - default BT - -endif # BOARD_NRF52840_BLIP diff --git a/boards/arm/nrf52840_blip/doc/index.rst b/boards/arm/nrf52840_blip/doc/index.rst deleted file mode 100644 index e9dc8ad939b..00000000000 --- a/boards/arm/nrf52840_blip/doc/index.rst +++ /dev/null @@ -1,196 +0,0 @@ -.. _nrf52840_blip: - -Electronut Labs Blip -#################### - -Overview -******** - -The Electronut Labs Blip hardware provides support for the Nordic Semiconductor -nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf52840_blip.jpg - :align: center - :alt: Electronut Labs Blip - - Electronut Labs Blip (Credit: Electronut Labs) - -More information about the board is available at https://github.com/electronut/ElectronutLabs-blip. - -Hardware -******** - -Blip has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf52840_blip board configuration supports the following -hardware features currently: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (red) = P0.14 -* LED3 (blue) = P0.15 - -Push buttons ------------- - -* BUTTON1 = SW1 = P1.07 -* Reset = SW5 = P0.18 (can be used as GPIO also) - -UART ----- - -BMP does not support hardware flow control, so only RX/TX pins are connected. - -* TX = P0.6 -* RX = P0.8 - -I2C ---- - -I2C pins connected to onboard sensors: - -* SDA = P0.12 -* SCL = P0.11 - -SPI ---- - -* SCK = P0.25 -* MOSI = P1.02 -* MISO = P0.24 - -MicroSD is connected to these pins, and CS pin is connected to P0.17. - -Programming and Debugging -************************* - -Applications for the ``nrf52840_blip`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); The onboard Black Magic -Probe debugger presents itself as two USB-serial ports. On Linux, -they may come up as ``/dev/ttyACM0`` and ``/dev/ttyACM1``. The first -one of these (``/dev/ttyACM0`` here) is the debugger port. -GDB can directly connect to this port without requiring a GDB server by specifying -``target external /dev/ttyACM0``. The second port acts as a -serial port, connected to the SoC. - -Flashing -======== - -Applications are flashed and run as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the serial port of Black Magic Probe. -For example, under Linux, :code:`/dev/ttyACM1`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52840_blip - :goals: build flash - -Debugging -========= - -Debug and attach configurations are available using Black Magic Probe, and -``ninja debug``, or ``ninja attach`` (or with ``make``) are available. - -NOTE: You may need to press the reset button once after using ``ninja flash`` -to start executing the code. (not required with ``debug`` or ``attach``) - - -Testing the LEDs and buttons in the nRF52840 PDK -************************************************ - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52840_blip/nrf52840_blip.dts`. - - -References -********** - -.. target-notes:: - -.. _Electronut Labs website: https://electronut.in -.. _Store link: https://www.tindie.com/stores/ElectronutLabs/ -.. _Blip website: https://github.com/electronut/ElectronutLabs-blip -.. _Schematic: https://github.com/electronut/ElectronutLabs-blip/blob/master/blip_v0.3_schematic.pdf -.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ -.. _Black Magic Probe website: https://github.com/blacksphere/blackmagic diff --git a/boards/arm/nrf52840_blip/nrf52840_blip_defconfig b/boards/arm/nrf52840_blip/nrf52840_blip_defconfig deleted file mode 100644 index 526283ef3d4..00000000000 --- a/boards/arm/nrf52840_blip/nrf52840_blip_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840_BLIP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52840_mdk/Kconfig.board b/boards/arm/nrf52840_mdk/Kconfig.board deleted file mode 100644 index 81f9b3a88f7..00000000000 --- a/boards/arm/nrf52840_mdk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52840-MDK board configuration - -# Copyright (c) 2018 makerdiary.com -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840_MDK - bool "NRF52840-MDK" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_mdk/Kconfig.defconfig b/boards/arm/nrf52840_mdk/Kconfig.defconfig deleted file mode 100644 index 8c321634996..00000000000 --- a/boards/arm/nrf52840_mdk/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52840-MDK board configuration - -# Copyright (c) 2018 makerdiary.com -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840_MDK - -config BOARD - default "nrf52840_mdk" - -config BT_CTLR - default BT - -endif # BOARD_NRF52840_MDK diff --git a/boards/arm/nrf52840_mdk/nrf52840_mdk_defconfig b/boards/arm/nrf52840_mdk/nrf52840_mdk_defconfig deleted file mode 100644 index 76c73a15a04..00000000000 --- a/boards/arm/nrf52840_mdk/nrf52840_mdk_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840_MDK=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.board b/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.board deleted file mode 100644 index 975e4bd9e9e..00000000000 --- a/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# nRF52840 MDK USB Dongle board configuration - -# Copyright (c) 2022 Nikola Trifunovic -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840_MDK_USB_DONGLE - bool "nRF52840 MDK USB DONGLE" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.defconfig b/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.defconfig deleted file mode 100644 index 7fb8a5fde94..00000000000 --- a/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# nRF52840 MDK USB Dongle board configuration -# -# Copyright (c) 2018 Nordic Semiconductor ASA -# -# Copyright (c) 2022 Nikola Trifunovic -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840_MDK_USB_DONGLE - -config BOARD - default "nrf52840_mdk_usb_dongle" - -# To let the nRF5 bootloader load an application, the application -# must be linked after Nordic MBR, that is factory-programmed on the board. - -# Nordic nRF5 bootloader exists outside of the partitions specified in the -# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application -# correctly, after Nordic MBR. - -# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION -# which will make it link into the correct partition specified in DTS file, -# so no override is necessary. - -config FLASH_LOAD_OFFSET - default 0x1000 - depends on BOARD_HAS_NRF5_BOOTLOADER && !USE_DT_CODE_PARTITION - -if USB_DEVICE_STACK - -# Enable UART driver, needed for CDC ACM -config SERIAL - default y - -endif # USB_DEVICE_STACK - -config BT_CTLR - default BT - -endif # BOARD_NRF52840_MDK_USB_DONGLE diff --git a/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig b/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig deleted file mode 100644 index 63decf69707..00000000000 --- a/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840_MDK_USB_DONGLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Console -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y diff --git a/boards/arm/nrf52840_papyr/Kconfig.board b/boards/arm/nrf52840_papyr/Kconfig.board deleted file mode 100644 index 574b885163e..00000000000 --- a/boards/arm/nrf52840_papyr/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Electronut Labs Papyr board configuration - -# Copyright (c) 2018 Electronut Labs -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840_PAPYR - bool "NRF52840 PAPYR" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_papyr/Kconfig.defconfig b/boards/arm/nrf52840_papyr/Kconfig.defconfig deleted file mode 100644 index 339d481404b..00000000000 --- a/boards/arm/nrf52840_papyr/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Electronut Labs Papyr board configuration - -# Copyright (c) 2018 Electronut Labs -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840_PAPYR - -config BOARD - default "nrf52840_papyr" - -config BT_CTLR - default BT - -endif # BOARD_NRF52840_PAPYR diff --git a/boards/arm/nrf52840_papyr/nrf52840_papyr_defconfig b/boards/arm/nrf52840_papyr/nrf52840_papyr_defconfig deleted file mode 100644 index 9d0226eed01..00000000000 --- a/boards/arm/nrf52840_papyr/nrf52840_papyr_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840_PAPYR=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52840dk_nrf52811/CMakeLists.txt b/boards/arm/nrf52840dk_nrf52811/CMakeLists.txt deleted file mode 100644 index d07679ce3f4..00000000000 --- a/boards/arm/nrf52840dk_nrf52811/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA - -# SPDX-License-Identifier: Apache-2.0 - -# The nrf52840dk_nrf52811 board mirrors the nRF52840 DK hardware. This -# needs to be considered by certain system initialization functionality -# residing in system_nrf52811.c and SoC dependent routines in nrfx_coredep.h. -zephyr_compile_definitions(DEVELOP_IN_NRF52840) -zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) diff --git a/boards/arm/nrf52840dk_nrf52811/Kconfig b/boards/arm/nrf52840dk_nrf52811/Kconfig deleted file mode 100644 index 5d25d66f11e..00000000000 --- a/boards/arm/nrf52840dk_nrf52811/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52840 DK NRF52811 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52840DK_NRF52811 diff --git a/boards/arm/nrf52840dk_nrf52811/Kconfig.board b/boards/arm/nrf52840dk_nrf52811/Kconfig.board deleted file mode 100644 index 5eefb967cd7..00000000000 --- a/boards/arm/nrf52840dk_nrf52811/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52840 DK NRF52811 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840DK_NRF52811 - bool "nRF52840 DK NRF52811" - depends on SOC_NRF52811_QFAA diff --git a/boards/arm/nrf52840dk_nrf52811/Kconfig.defconfig b/boards/arm/nrf52840dk_nrf52811/Kconfig.defconfig deleted file mode 100644 index 2d933bf12b3..00000000000 --- a/boards/arm/nrf52840dk_nrf52811/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52840 DK NRF52811 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840DK_NRF52811 - -config BOARD - default "nrf52840dk_nrf52811" - -config BT_CTLR - default BT - -endif # BOARD_NRF52840DK_NRF52811 diff --git a/boards/arm/nrf52840dk_nrf52811/board.cmake b/boards/arm/nrf52840dk_nrf52811/board.cmake deleted file mode 100644 index af01781dd29..00000000000 --- a/boards/arm/nrf52840dk_nrf52811/board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA - -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/nrf52840dk_nrf52811/doc/index.rst b/boards/arm/nrf52840dk_nrf52811/doc/index.rst deleted file mode 100644 index b33d1caea4e..00000000000 --- a/boards/arm/nrf52840dk_nrf52811/doc/index.rst +++ /dev/null @@ -1,24 +0,0 @@ -.. _nrf52840dk_nrf52811: - -nRF52811 emulation on nRF52840 DK -################################# - -Overview -******** - -The nrf52840dk_nrf52811 board is a modified version of the -:ref:`nrf52840dk_nrf52840` that enforces the limitations imposed by the nRF52811 -IC, which is a variant of the original nRF52840. Since Nordic does not offer a -development kit for the nRF52811 you can use this board to develop for this IC -while using the nRF52840 Development Kit (PCA10056). - -See :ref:`nrf52840dk_nrf52840` for more information about the development board -and `nRF52811 website`_ for the official reference on the IC itself. - - -References -********** - -.. target-notes:: - -.. _nRF52811 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52811 diff --git a/boards/arm/nrf52840dk_nrf52840/Kconfig b/boards/arm/nrf52840dk_nrf52840/Kconfig deleted file mode 100644 index 037d1dc9216..00000000000 --- a/boards/arm/nrf52840dk_nrf52840/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# nRF52840 DK NRF52840 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840DK_NRF52840 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_NRF52840DK_NRF52840 diff --git a/boards/arm/nrf52840dk_nrf52840/Kconfig.board b/boards/arm/nrf52840dk_nrf52840/Kconfig.board deleted file mode 100644 index dcfdb550a43..00000000000 --- a/boards/arm/nrf52840dk_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52840 DK NRF52840 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840DK_NRF52840 - bool "nRF52840 DK NRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840dk_nrf52840/Kconfig.defconfig b/boards/arm/nrf52840dk_nrf52840/Kconfig.defconfig deleted file mode 100644 index 31850c65937..00000000000 --- a/boards/arm/nrf52840dk_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52840 DK NRF52840 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840DK_NRF52840 - -config BOARD - default "nrf52840dk_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_NRF52840DK_NRF52840 diff --git a/boards/arm/nrf52840dk_nrf52840/doc/index.rst b/boards/arm/nrf52840dk_nrf52840/doc/index.rst deleted file mode 100644 index 9734af91e7f..00000000000 --- a/boards/arm/nrf52840dk_nrf52840/doc/index.rst +++ /dev/null @@ -1,224 +0,0 @@ -.. _nrf52840dk_nrf52840: - -nRF52840 DK -########### - -Overview -******** - -The nRF52840 Development Kit (PCA10056) hardware provides support for the -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf52840dk_nrf52840.jpg - :align: center - :alt: nRF52840 DK - - nRF52840 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the `nRF52840 DK website`_. -The `Nordic Semiconductor Infocenter`_ contains the processor's information -and the datasheet. - - -Hardware -******** - -nRF52840 DK has two external oscillators. The frequency of the slow clock -is 32.768 kHz. The frequency of the main clock is 32 MHz. - -Supported Features -================== - -The nrf52840dk_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF52840 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF52840 Development Kit board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (green) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -Programming and Debugging -************************* - -Applications for the ``nrf52840dk_nrf52840`` board configuration can be -built, flashed, and debugged in the usual way. See -:ref:`build_an_application` and :ref:`application_run` for more details on -building and running. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF52840 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52840dk_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF52840 DK -*********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts`. - -Changing UART1 pins -******************* - -The following approach can be used when an application needs to use another set -of pins for UART1: - -1. Add devicetree overlay file to the main directory of your application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default_alt: uart1_default_alt { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep_alt: uart1_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - pinctrl-0 = <&uart1_default_alt>; - /* if sleep state is not used, use /delete-property/ pinctrl-1; and - * skip the "sleep" entry. - */ - pinctrl-1 = <&uart1_sleep_alt>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX - -See :ref:`set-devicetree-overlays` for further details. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the `nRF52840 Product Specification`_, chapter 7 'Hardware and Layout'. -In the table 7.1.1 'aQFN73 ball assignments' select the pins marked -'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used -in under-10KHz applications. They are not suitable for 115200 speed of UART. - -References -********** - -.. target-notes:: - -.. _nRF52840 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf diff --git a/boards/arm/nrf52840dongle_nrf52840/Kconfig b/boards/arm/nrf52840dongle_nrf52840/Kconfig deleted file mode 100644 index d07ac16faef..00000000000 --- a/boards/arm/nrf52840dongle_nrf52840/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -# nRF52840 Dongle NRF52840 board configuration - -# Copyright (c) 2018-2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840DONGLE_NRF52840 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -config BOARD_HAS_NRF5_BOOTLOADER - bool "Board has nRF5 bootloader" - default y - help - If selected, applications are linked so that they can be loaded by Nordic - nRF5 bootloader. - -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "USB CDC" - default y - -endif # BOARD_NRF52840DONGLE_NRF52840 diff --git a/boards/arm/nrf52840dongle_nrf52840/Kconfig.board b/boards/arm/nrf52840dongle_nrf52840/Kconfig.board deleted file mode 100644 index 463bd53b381..00000000000 --- a/boards/arm/nrf52840dongle_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52840 Dongle NRF52840 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840DONGLE_NRF52840 - bool "nRF52840 DONGLE NRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig b/boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig deleted file mode 100644 index 76c7559be8d..00000000000 --- a/boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,86 +0,0 @@ -# nRF52840 Dongle NRF52840 board configuration -# -# Copyright (c) 2018-2023 Nordic Semiconductor ASA -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840DONGLE_NRF52840 - -config BOARD - default "nrf52840dongle_nrf52840" - -# To let the nRF5 bootloader load an application, the application -# must be linked after Nordic MBR, that is factory-programmed on the board. - -# Nordic nRF5 bootloader exists outside of the partitions specified in the -# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application -# correctly, after Nordic MBR. - -# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION -# which will make it link into the correct partition specified in DTS file, -# the offset is applied here so that the full partition size can be used when -# the bootloader Kconfig option has been disabled. - -config FLASH_LOAD_OFFSET - default 0x1000 - depends on BOARD_HAS_NRF5_BOOTLOADER && (MCUBOOT || !USE_DT_CODE_PARTITION) - -if BOARD_SERIAL_BACKEND_CDC_ACM - -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default SERIAL - -config CONSOLE - default y - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if !MCUBOOT && CONSOLE - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -config USB_DEVICE_REMOTE_WAKEUP - default n - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -# Set USB log level to error only -choice USB_DEVICE_LOG_LEVEL_CHOICE - default USB_DEVICE_LOG_LEVEL_ERR -endchoice - -# Wait 4000ms at startup for logging -config LOG_PROCESS_THREAD_STARTUP_DELAY_MS - default 4000 - -endif # LOG - -if USB_DEVICE_STACK - -# Enable UART driver, needed for CDC ACM -config SERIAL - default y - -endif # USB_DEVICE_STACK - -endif # BOARD_SERIAL_BACKEND_CDC_ACM - -config BT_CTLR - default BT - -endif # BOARD_NRF52840DONGLE_NRF52840 diff --git a/boards/arm/nrf52840dongle_nrf52840/doc/index.rst b/boards/arm/nrf52840dongle_nrf52840/doc/index.rst deleted file mode 100644 index 6cfe7329d2c..00000000000 --- a/boards/arm/nrf52840dongle_nrf52840/doc/index.rst +++ /dev/null @@ -1,348 +0,0 @@ -.. _nrf52840dongle_nrf52840: - -nRF52840 Dongle -############### - -Overview -******** - -The nRF52840 Dongle (PCA10059) hardware provides support for the Nordic -Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf52840dongle_nrf52840.jpg - :align: center - :alt: nRF52840 Dongle - - nRF52840 Dongle - -More information about the board can be found at the -`nRF52840 Dongle website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -The ``nrf52840dongle_nrf52840`` has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The ``nrf52840dongle_nrf52840`` board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF52840 Dongle website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF52840 Dongle board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (green) = P0.6 -* LED1 (red) = P0.8 -* LED1 (green) = P1.9 -* LED1 (blue) = P0.12 - -Push buttons ------------- - -* BUTTON1 = SW1 = P1.6 -* RESET = SW2 = P0.18 - -Programming and Debugging -************************* - -Applications for the ``nrf52840dongle_nrf52840`` board configuration can be -built in the usual way (see :ref:`build_an_application` for more details). - -Flashing -======== - -The board supports the following programming options: - -1. Using the built-in bootloader only -2. Using MCUboot in serial recovery mode -3. Using an external :ref:`debug probe ` - -These instructions use the :ref:`west ` tool and assume you are in the -root directory of your :term:`west installation`. - -Option 1: Using the Built-In Bootloader Only --------------------------------------------- - -The board is factory-programmed with Nordic's bootloader from Nordic's nRF5 -SDK. With this option, you'll use Nordic's `nrfutil`_ program to create -firmware packages supported by this bootloader and flash them to the -device. Make sure ``nrfutil`` is installed before proceeding. - -#. Reset the board into the Nordic bootloader by pressing the RESET button. - - The push button is on the far side of the board from the USB connector. Note - that the button does not face up. You will have to push it from the outside - in, towards the USB connector: - - .. image:: img/nRF52840_dongle_press_reset.svg - :alt: Location of RESET button and direction of push - - The red LED should start a fade pattern, signalling the bootloader is - running. - -#. Compile a Zephyr application; we'll use :zephyr:code-sample:`blinky`. - - .. zephyr-app-commands:: - :app: zephyr/samples/basic/blinky - :board: nrf52840dongle_nrf52840 - :goals: build - -#. Package the application for the bootloader using ``nrfutil``: - - .. code-block:: console - - nrfutil pkg generate --hw-version 52 --sd-req=0x00 \ - --application build/zephyr/zephyr.hex \ - --application-version 1 blinky.zip - -#. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be - something like ``COMx`` on Windows, and something else on macOS. - - .. code-block:: console - - nrfutil dfu usb-serial -pkg blinky.zip -p /dev/ttyACM0 - - When this command exits, observe the green LED on the board blinking, - instead of the red LED used by the bootloader. - -For more information, see `Nordic Semiconductor USB DFU`_. - -Option 2: Using MCUboot in Serial Recovery Mode ------------------------------------------------ - -It is also possible to use the MCUboot bootloader with this board to flash -Zephyr applications. You need to do some one-time set-up to build and flash -MCUboot on your board. From that point on, you can build and flash other Zephyr -applications using MCUboot's serial recovery mode. This process does not -overwrite the built-in Nordic bootloader, so you can always go back to using -Option 1 later. - -Install `nrfutil`_ and `mcumgr`_ first, and make sure MCUboot's ``imgtool`` is -available for signing your binary for MCUboot as described on :ref:`west-sign`. - -Next, do the **one-time setup** to flash MCUboot. We'll assume you've cloned -the `MCUboot`_ repository into the directory ``mcuboot``, and that it is next -to the zephyr repository on your computer. - -#. Reset the board into the Nordic bootloader as described above. - -#. Compile MCUboot as a Zephyr application. - - .. zephyr-app-commands:: - :app: mcuboot/boot/zephyr - :board: nrf52840dongle_nrf52840 - :build-dir: mcuboot - :goals: build - -#. Package the application for the bootloader using ``nrfutil``: - - .. code-block:: console - - nrfutil pkg generate --hw-version 52 --sd-req=0x00 \ - --application build/mcuboot/zephyr/zephyr.hex \ - --application-version 1 mcuboot.zip - -#. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be - something like ``COMx`` on Windows, and something else on macOS. - - .. code-block:: console - - nrfutil dfu usb-serial -pkg mcuboot.zip -p /dev/ttyACM0 - -You can now flash a Zephyr application to the board using MCUboot's serial -recovery mode. We'll use the :zephyr:code-sample:`smp-svr` sample since it's ready to be -compiled for chain-loading by MCUboot (and itself supports firmware updates -over Bluetooth). - -#. Boot into MCUboot serial recovery mode by plugging the board in with the SW1 - button pressed down. See above for a picture showing where SW1 is. - - **Do not press RESET**; that will run the Nordic bootloader, which is - different than MCUboot. - - A serial port will enumerate on your board. On Windows, "MCUBOOT" should - appear under "Other Devices" in the Device Manager (in addition to the usual - ``COMx`` device). On Linux, something like - :file:`/dev/serial/by-id/usb-ZEPHYR_MCUBOOT_0.01-if00` should be created. - - If no serial port appears, try plugging it in again, making sure SW1 is - pressed. If it still doesn't appear, retry the one-time MCUboot setup. - -#. Compile ``smp_svr``. - - .. zephyr-app-commands:: - :app: zephyr/samples/subsys/mgmt/mcumgr/smp_svr - :board: nrf52840dongle_nrf52840 - :build-dir: smp_svr - :goals: build - -#. Sign ``smp_svr`` for chain-loading by MCUboot. - - .. code-block:: console - - west sign -t imgtool --bin --no-hex -d build/smp_svr \ - -B smp_svr.signed.bin -- --key mcuboot/root-rsa-2048.pem - -#. Flash the application to the MCUboot serial port using ``mcumgr``: - - .. code-block:: console - - mcumgr --conntype=serial --connstring='dev=/dev/ttyACM0,baud=115200' \ - image upload -e smp_svr.signed.bin - -#. Reset the device: - - .. code-block:: console - - mcumgr --conntype=serial --connstring='dev=/dev/ttyACM0,baud=115200' reset - -You should now be able to scan for Bluetooth devices using a smartphone or -computer. The device you just flashed will be listed with ``Zephyr`` in its -name. - -.. note:: - - This board supports building other Zephyr applications for flashing with - MCUboot in this way also. Just make sure :kconfig:option:`CONFIG_BOOTLOADER_MCUBOOT` - is set when building your application. For example, to compile blinky for - loading by MCUboot, use this: - - .. zephyr-app-commands:: - :app: zephyr/samples/basic/blinky - :board: nrf52840dongle_nrf52840 - :build-dir: blinky - :goals: build - :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y - - You can then sign and flash it using the steps above. - -Option 3: Using an External Debug Probe ---------------------------------------- - -If you have one, you can also use an external :ref:`debug probe ` -to flash and debug Zephyr applications, but you need to solder an SWD header -onto the back side of the board. - -For Segger J-Link debug probes, follow the instructions in the -:ref:`nordic_segger` page to install and configure all the necessary -software. Further information can be found in :ref:`nordic_segger_flashing`. - -Locate the DTS file for the board under: boards/arm/nrf52840dongle_nrf52840. -This file requires a small modification to use a different partition table. -Edit the include directive to include "fstab-debugger" instead of "fstab-stock". - -In addition, the Kconfig file in the same directory must be modified by setting -``BOARD_HAS_NRF5_BOOTLOADER`` to be default ``n``, otherwise the code will be -flashed with an offset. - -Then build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nrf52840dongle_nrf52840 - :goals: build flash - -Observe the LED on the board blinking. - -Debugging -========= - -The ``nrf52840dongle_nrf52840`` board does not have an on-board J-Link debug IC -as some nRF5x development boards, however, instructions from the -:ref:`nordic_segger` page also apply to this board, with the additional step -of connecting an external debugger. - -Testing the LEDs and buttons on the nRF52840 Dongle -*************************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` - -You can build and program the examples to make sure Zephyr is running correctly -on your board. - - -References -********** - -.. target-notes:: - -.. _nRF52840 Dongle website: - https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle -.. _Nordic Semiconductor Infocenter: - https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: - https://www.segger.com/jlink-software.html -.. _Nordic Semiconductor USB DFU: - https://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.sdk5.v15.2.0%2Fsdk_app_serial_dfu_bootloader.html -.. _nrfutil: - https://github.com/NordicSemiconductor/pc-nrfutil -.. _MCUboot: - https://github.com/JuulLabs-OSS/mcuboot -.. _mcumgr: - https://github.com/apache/mynewt-mcumgr-cli diff --git a/boards/arm/nrf52_adafruit_feather/Kconfig.board b/boards/arm/nrf52_adafruit_feather/Kconfig.board deleted file mode 100644 index 0f629d853df..00000000000 --- a/boards/arm/nrf52_adafruit_feather/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 ADAFRUIT FEATHER board configuration - -# Copyright (c) 2018 LEDCity AG. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52_ADAFRUIT_FEATHER - bool "nRF52 ADAFRUIT FEATHER" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_adafruit_feather/Kconfig.defconfig b/boards/arm/nrf52_adafruit_feather/Kconfig.defconfig deleted file mode 100644 index c75ff94e520..00000000000 --- a/boards/arm/nrf52_adafruit_feather/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 ADAFRUIT FEATHER board configuration - -# Copyright (c) 2018 LEDCity AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52_ADAFRUIT_FEATHER - -config BOARD - default "nrf52_adafruit_feather" - -config BT_CTLR - default BT - -endif # BOARD_NRF52_ADAFRUIT_FEATHER diff --git a/boards/arm/nrf52_adafruit_feather/doc/index.rst b/boards/arm/nrf52_adafruit_feather/doc/index.rst deleted file mode 100644 index 3555803b449..00000000000 --- a/boards/arm/nrf52_adafruit_feather/doc/index.rst +++ /dev/null @@ -1,192 +0,0 @@ -.. _nrf52_adafruit_feather: - -nRF52 Adafruit Feather -###################### - -Overview -******** - -The nRF52 Adafruit Bluefruit Feather hardware provides -support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`RTC (nRF RTC System Clock)` -* UART -* GPIO -* FLASH -* RADIO (Bluetooth Low Energy) -* Segger RTT (RTT Console) - -.. figure:: img/nrf52_adafruit_feather.jpg - :align: center - :alt: nRF52 Adafruit Feather Board - - nRF52 Adafruit Feather Board (Credit: Adafruit) - -More information about the board and its features can be found at the -`Adafruit Feather nRF52 Bluefruit Learning Guide`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - -Hardware -******** - -- nRF52832 ARM Cortex-M4F processor at 64 MHz -- 32.768 kHz crystal oscillator -- 512 KiB flash memory and 64 KiB of SRAM -- Battery connector and charger for 3.7 V lithium polymer batteries -- Charging indicator LED -- 2 User LEDs -- Reset button -- SWD connector -- USB serial converter - -Supported Features -================== - -The nRF52 Adafruit Feather board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTT | on-chip | console | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -The `Adafruit Feather nRF52 Bluefruit Learning Guide`_ has detailed -information about the board including `pinouts`_ and the `schematic`_. - -LED ---- - -* LED0 (red) = P0.17 -* LED1 (blue) = P0.19 - -Push buttons ------------- - -* DFU = SW0 = P0.20 -* RESET = SW1 = P0.21/reset - -Programming and Debugging -************************* - -The ``nrf52_adafruit_feather`` board is available in two different versions: - -- `Adafruit Feather nRF52 Pro with myNewt Bootloader`_ - This board version is the recommended one to use. It has the SWD header - already populated and comes with the Mynewt serial bootloader installed by - default. - -- `Adafruit Feather nRF52 Bluefruit LE`_ - This board is identical to the board above, but the SWD header is not - populated and ships with an Arduino friendly bootloader. To be able to work - with this version a 2*5pin 0.5" SWD header (e.g. `Adafruit SWD connector`_) - needs to be soldered. - -Applications for the ``nrf52_adafruit_feather`` board configuration can be -built, flashed, and debugged in the usual way. See :ref:`build_an_application` -and :ref:`application_run` for more details on building and running. - -Flashing -======== - -Flashing Zephyr onto the ``nrf52_adafruit_feather`` board requires an external -J-Link programmer. The programmer is attached to the X1 SWD header. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52_adafruit_feather - :goals: build - :compact: - -#. Connect the Adafruit nRF52 Feather to your host computer using USB - -#. Run your favorite terminal program to listen for output. - - .. code-block:: console - - $ minicom -D -b 115200 - - Replace :code:`` with the port where the nRF52 Adafruit Feather - board can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52_adafruit_feather - :goals: flash - :compact: - - You should see "Hello World! nrf52_adafruit_feather" in your terminal. - - -Debugging -========= - -The ``nrf52_adafruit_feather`` board does not have an on-board J-Link debug IC -as some nRF5x development boards, however, instructions from the -:ref:`nordic_segger` page also apply to this board, with the additional step -of connecting an external debugger. - - -Testing the LEDs and buttons on the nRF52 Adafruit Feather -********************************************************** - -There are several samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -- :zephyr:code-sample:`blinky` -- :zephyr:code-sample:`button` -- :zephyr:code-sample:`fade-led` -- :zephyr:code-sample:`pwm-blinky` -- :zephyr:code-sample:`multi-thread-blinky` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52_adafruit_feather/board.h`. - - -References -********** - -.. target-notes:: - -.. _Adafruit Feather nRF52 Bluefruit Learning Guide: https://learn.adafruit.com/bluefruit-nrf52-feather-learning-guide/introduction -.. _schematic: https://learn.adafruit.com/assets/39913 -.. _pinouts: https://cdn-learn.adafruit.com/assets/assets/000/046/210/original/Feather_NRF52_Pinout_v1.2.pdf?1504807075 -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _Adafruit Feather nRF52 Bluefruit LE: https://www.adafruit.com/product/3406 -.. _Adafruit Feather nRF52 Pro with myNewt Bootloader: https://www.adafruit.com/product/3574 -.. _Adafruit SWD connector: https://www.adafruit.com/product/752 diff --git a/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig b/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig deleted file mode 100644 index b434b22401d..00000000000 --- a/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52_ADAFRUIT_FEATHER=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52_blenano2/Kconfig.board b/boards/arm/nrf52_blenano2/Kconfig.board deleted file mode 100644 index 05fe6ab53d5..00000000000 --- a/boards/arm/nrf52_blenano2/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 BLENANO 2 board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52_BLENANO2 - bool "nRF52 BLENANO2" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_blenano2/Kconfig.defconfig b/boards/arm/nrf52_blenano2/Kconfig.defconfig deleted file mode 100644 index b5a7184c1a8..00000000000 --- a/boards/arm/nrf52_blenano2/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 BLENANO 2 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52_BLENANO2 - -config BOARD - default "nrf52_blenano2" - -config BT_CTLR - default BT - -endif # BOARD_NRF52_BLENANO2 diff --git a/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig b/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig deleted file mode 100644 index 318b8de6922..00000000000 --- a/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52_BLENANO2=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52_sparkfun/Kconfig.board b/boards/arm/nrf52_sparkfun/Kconfig.board deleted file mode 100644 index 3f290f593cf..00000000000 --- a/boards/arm/nrf52_sparkfun/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Sparkfun nRF52832 breakout board configuration - -# Copyright (c) 2017 Shawn Nock -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52_SPARKFUN - bool "nRF52 SPARKFUN" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_sparkfun/Kconfig.defconfig b/boards/arm/nrf52_sparkfun/Kconfig.defconfig deleted file mode 100644 index 7629db89439..00000000000 --- a/boards/arm/nrf52_sparkfun/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Sparkfun nRF52832 breakout board configuration - -# Copyright (c) 2017 Shawn Nock -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52_SPARKFUN - -config BOARD - default "nrf52_sparkfun" - -config BT_CTLR - default BT - -endif # BOARD_NRF52_SPARKFUN diff --git a/boards/arm/nrf52_sparkfun/nrf52_sparkfun_defconfig b/boards/arm/nrf52_sparkfun/nrf52_sparkfun_defconfig deleted file mode 100644 index 3c893c08bc7..00000000000 --- a/boards/arm/nrf52_sparkfun/nrf52_sparkfun_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52_SPARKFUN=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52_vbluno52/Kconfig b/boards/arm/nrf52_vbluno52/Kconfig deleted file mode 100644 index 026b4b301a7..00000000000 --- a/boards/arm/nrf52_vbluno52/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 VBLUno52 board configuration - -# Copyright (c) 2017 VNG IoT Lab -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52_VBLUNO52 - -endif # BOARD_NRF52_VBLUNO52 diff --git a/boards/arm/nrf52_vbluno52/Kconfig.board b/boards/arm/nrf52_vbluno52/Kconfig.board deleted file mode 100644 index bb1c223f480..00000000000 --- a/boards/arm/nrf52_vbluno52/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 VBLUno52 board configuration -# Copyright (c) 2017 VNG IoT Lab - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52_VBLUNO52 - bool "nRF52 VBLUno52" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_vbluno52/Kconfig.defconfig b/boards/arm/nrf52_vbluno52/Kconfig.defconfig deleted file mode 100644 index 28f61496367..00000000000 --- a/boards/arm/nrf52_vbluno52/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 VBLUno52 board configuration - -# Copyright (c) 2017 VNG IoT Lab -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52_VBLUNO52 - -config BOARD - default "nrf52_vbluno52" - -config BT_CTLR - default BT - -endif # BOARD_NRF52_VBLUNO52 diff --git a/boards/arm/nrf52_vbluno52/nrf52_vbluno52_defconfig b/boards/arm/nrf52_vbluno52/nrf52_vbluno52_defconfig deleted file mode 100644 index 074355f29a1..00000000000 --- a/boards/arm/nrf52_vbluno52/nrf52_vbluno52_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52_VBLUNO52=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52dk_nrf52805/CMakeLists.txt b/boards/arm/nrf52dk_nrf52805/CMakeLists.txt deleted file mode 100644 index d708ea8ca21..00000000000 --- a/boards/arm/nrf52dk_nrf52805/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# The nrf52dk_nrf52805 board mirrors the nRF52 DK hardware. This needs -# to be considered by certain system initialization functionality residing -# in system_nrf52805.c and SoC dependent routines in nrfx_coredep.h. -zephyr_compile_definitions(DEVELOP_IN_NRF52832) -zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) diff --git a/boards/arm/nrf52dk_nrf52805/Kconfig b/boards/arm/nrf52dk_nrf52805/Kconfig deleted file mode 100644 index 89f210e7e37..00000000000 --- a/boards/arm/nrf52dk_nrf52805/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52 DK nRF52805 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52DK_NRF52805 diff --git a/boards/arm/nrf52dk_nrf52805/Kconfig.board b/boards/arm/nrf52dk_nrf52805/Kconfig.board deleted file mode 100644 index cf5fede2872..00000000000 --- a/boards/arm/nrf52dk_nrf52805/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 DK nRF52805 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52DK_NRF52805 - bool "nRF52 DK NRF52805" - depends on SOC_NRF52805_CAAA diff --git a/boards/arm/nrf52dk_nrf52805/Kconfig.defconfig b/boards/arm/nrf52dk_nrf52805/Kconfig.defconfig deleted file mode 100644 index 6fa1686219e..00000000000 --- a/boards/arm/nrf52dk_nrf52805/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 DK nRF52805 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52DK_NRF52805 - -config BOARD - default "nrf52dk_nrf52805" - -config BT_CTLR - default BT - -endif # BOARD_NRF52DK_NRF52805 diff --git a/boards/arm/nrf52dk_nrf52805/board.cmake b/boards/arm/nrf52dk_nrf52805/board.cmake deleted file mode 100644 index e3f77214027..00000000000 --- a/boards/arm/nrf52dk_nrf52805/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/nrf52dk_nrf52805/doc/index.rst b/boards/arm/nrf52dk_nrf52805/doc/index.rst deleted file mode 100644 index 121d1d508d0..00000000000 --- a/boards/arm/nrf52dk_nrf52805/doc/index.rst +++ /dev/null @@ -1,23 +0,0 @@ -.. _nrf52dk_nrf52805: - -nRF52805 emulation on nRF52 DK -############################## - -Overview -******** - -The nrf52dk_nrf52805 board is a modified version of the :ref:`nrf52dk_nrf52832` -that enforces the limitations imposed by the nRF52805 IC, which is a -cost-reduced variant of the original nRF52832. Since Nordic does not offer a -development kit for the nRF52805, you can use this board to develop for this -IC while using the nRF52 Development Kit (PCA10040). - -See :ref:`nrf52dk_nrf52832` for more information about the development board and -`nRF52805 website`_ for the official reference on the IC itself. - -References -********** - -.. target-notes:: - -.. _nRF52805 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52805 diff --git a/boards/arm/nrf52dk_nrf52810/CMakeLists.txt b/boards/arm/nrf52dk_nrf52810/CMakeLists.txt deleted file mode 100644 index a36a95351a1..00000000000 --- a/boards/arm/nrf52dk_nrf52810/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# The nrf52dk_nrf52810 board mirrors the nRF52832 DK hardware. This -# needs to be considered by certain system initialization functionality -# residing in system_nrf52810.c and SoC dependent routines in nrfx_coredep.h. -zephyr_compile_definitions(DEVELOP_IN_NRF52832) -zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) diff --git a/boards/arm/nrf52dk_nrf52810/Kconfig b/boards/arm/nrf52dk_nrf52810/Kconfig deleted file mode 100644 index 4bb3d0a20cc..00000000000 --- a/boards/arm/nrf52dk_nrf52810/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# nRF52 DK nRF52810 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52DK_NRF52810 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT - -endif # BOARD_NRF52DK_NRF52810 diff --git a/boards/arm/nrf52dk_nrf52810/Kconfig.board b/boards/arm/nrf52dk_nrf52810/Kconfig.board deleted file mode 100644 index 03004863b14..00000000000 --- a/boards/arm/nrf52dk_nrf52810/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 DK nRF52810 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52DK_NRF52810 - bool "nRF52 DK NRF52810" - depends on SOC_NRF52810_QFAA diff --git a/boards/arm/nrf52dk_nrf52810/Kconfig.defconfig b/boards/arm/nrf52dk_nrf52810/Kconfig.defconfig deleted file mode 100644 index d98b71c5e61..00000000000 --- a/boards/arm/nrf52dk_nrf52810/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# nRF52 DK nRF52810 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52DK_NRF52810 - -config BOARD - default "nrf52dk_nrf52810" - -endif # BOARD_NRF52DK_NRF52810 diff --git a/boards/arm/nrf52dk_nrf52810/board.cmake b/boards/arm/nrf52dk_nrf52810/board.cmake deleted file mode 100644 index e3f77214027..00000000000 --- a/boards/arm/nrf52dk_nrf52810/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/nrf52dk_nrf52810/doc/index.rst b/boards/arm/nrf52dk_nrf52810/doc/index.rst deleted file mode 100644 index 8a767ca1b5b..00000000000 --- a/boards/arm/nrf52dk_nrf52810/doc/index.rst +++ /dev/null @@ -1,24 +0,0 @@ -.. _nrf52dk_nrf52810: - -nRF52810 emulation on nRF52 DK -############################## - -Overview -******** - -The nrf52dk_nrf52810 board is a modified version of the :ref:`nrf52dk_nrf52832` -that enforces the limitations imposed by the nRF52810 IC, which is a -cost-reduced variant of the original nRF52832. Since Nordic does not offer a -development kit for the nRF52810 you can use this board to develop for this -IC while using the nRF52 Development Kit (PCA10040). - -See :ref:`nrf52dk_nrf52832` for more information about the development board and -`nRF52810 website`_ for the official reference on the IC itself. - - -References -********** - -.. target-notes:: - -.. _nRF52810 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52810 diff --git a/boards/arm/nrf52dk_nrf52832/Kconfig b/boards/arm/nrf52dk_nrf52832/Kconfig deleted file mode 100644 index 3ed080aa6d1..00000000000 --- a/boards/arm/nrf52dk_nrf52832/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52 DK board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52DK_NRF52832 diff --git a/boards/arm/nrf52dk_nrf52832/Kconfig.board b/boards/arm/nrf52dk_nrf52832/Kconfig.board deleted file mode 100644 index b853f2023b8..00000000000 --- a/boards/arm/nrf52dk_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 DK NRF52832 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52DK_NRF52832 - bool "nRF52 DK NRF52832" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52dk_nrf52832/Kconfig.defconfig b/boards/arm/nrf52dk_nrf52832/Kconfig.defconfig deleted file mode 100644 index 648ea4de83d..00000000000 --- a/boards/arm/nrf52dk_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 DK NRF52832 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52DK_NRF52832 - -config BOARD - default "nrf52dk_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_NRF52DK_NRF52832 diff --git a/boards/arm/nrf52dk_nrf52832/doc/index.rst b/boards/arm/nrf52dk_nrf52832/doc/index.rst deleted file mode 100644 index 77bf7df995b..00000000000 --- a/boards/arm/nrf52dk_nrf52832/doc/index.rst +++ /dev/null @@ -1,406 +0,0 @@ -.. _nrf52dk_nrf52832: - -nRF52 DK -######## - -Overview -******** - -The nRF52 Development Kit (PCA10040) hardware provides -support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf52dk_nrf52832.jpg - :align: center - :alt: nRF52 DK - - nRF52 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the -`nRF52 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF52 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf52dk_nrf52832 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF52 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF52 Development Kit board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.17 -* LED2 (green) = P0.18 -* LED3 (green) = P0.19 -* LED4 (green) = P0.20 -* LD5 (red/green) = OB LED 1/2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.13 -* BUTTON2 = SW2 = P0.14 -* BUTTON3 = SW3 = P0.15 -* BUTTON4 = SW4 = P0.16 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -J-Link Prog Connector - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - -Debug IN - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | VDD | N/A | -+-------+--------------+-------------------------+ -| 2 | SWDIO | SWDIO | -+-------+--------------+-------------------------+ -| 3 | GND | N/A | -+-------+--------------+-------------------------+ -| 4 | SWDCLK | SWDCLK | -+-------+--------------+-------------------------+ -| 5 | GND | N/A | -+-------+--------------+-------------------------+ -| 6 | P0.18 | P0.18 / TRACEDATA[0] / | -| | | SWO | -+-------+--------------+-------------------------+ -| 7 | Cut off | N/A | -+-------+--------------+-------------------------+ -| 8 | Cut off | N/A | -+-------+--------------+-------------------------+ -| 9 | GND | N/A | -+-------+--------------+-------------------------+ -| 10 | P0.21 | P0.21 / RESET | -+-------+--------------+-------------------------+ - -Debug OUT - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -| | | -+-------+----------------+ -| 7 | Cut off | -+-------+----------------+ -| 8 | Cut off | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - -Shield Debug and Current measurement - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | VDD_nRF | -+-------+----------------+ -| 2 | VDD | -+-------+----------------+ -| 3 | SH_VTG | -+-------+----------------+ -| 4 | SH_SWDIO | -+-------+----------------+ -| 5 | SH_SWDCLK | -+-------+----------------+ -| 6 | SH_SWO | -+-------+----------------+ -| 7 | SH_RESET | -+-------+----------------+ -| 8 | SH_GND_DETECT | -+-------+----------------+ - -Auxiliary - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | P0.00 | P0.00 / XL1 | -+-------+--------------+-------------------------+ -| 2 | P0.01 | P0.01 / XL2 | -+-------+--------------+-------------------------+ -| 3 | P0.21 | P0.21 / RESET | -+-------+--------------+-------------------------+ -| 4 | P0.05_C | P0.05 / AIN3 | -+-------+--------------+-------------------------+ -| 5 | P0.06_C | P0.06 | -+-------+--------------+-------------------------+ -| 6 | P0.07_C | P0.07 | -+-------+--------------+-------------------------+ -| 7 | P0.08_C | P0.08 | -+-------+--------------+-------------------------+ -| 8 | P0.09 | P0.09 / NFC1 | -+-------+--------------+-------------------------+ -| 9 | P0.10 | P0.10 / NFC2 | -+-------+--------------+-------------------------+ - -Arduino Headers ---------------- - -P1/P7 Power - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | VDD | N/A | -+-------+--------------+-------------------------+ -| 2 | VDD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.21 / RESET | -+-------+--------------+-------------------------+ -| 4 | VDD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | VIN | N/A | -+-------+--------------+-------------------------+ - -P2/P8 Analog in - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -P3/P9 Digital I/O - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | D0 (RX) | P0.11 | -+-------+--------------+-------------------------+ -| 2 | D1 (TX) | P0.12 | -+-------+--------------+-------------------------+ -| 3 | D2 | P0.13 | -+-------+--------------+-------------------------+ -| 4 | D3 | P0.14 / TRACEDATA[3] | -+-------+--------------+-------------------------+ -| 5 | D4 | P0.15 / TRACEDATA[2] | -+-------+--------------+-------------------------+ -| 6 | D5 | P0.16 / TRACEDATA[1] | -+-------+--------------+-------------------------+ -| 7 | D6 | P0.17 | -+-------+--------------+-------------------------+ -| 8 | D7 | P0.18 / TRACEDATA[3] / | -| | | SWO | -+-------+--------------+-------------------------+ - -P4/P10 Digital I/O - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | D8 | P0.19 | -+-------+--------------+-------------------------+ -| 2 | D9 | P0.20 / TRACECLK | -+-------+--------------+-------------------------+ -| 3 | D10 (SS) | P0.22 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 5 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 6 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 9 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 10 | SCL | P0.27 | -+-------+--------------+-------------------------+ - -P5/P11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF52 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52dk_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF52 DK -******************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.dts`. - -References -********** - -.. target-notes:: - -.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/CMakeLists.txt b/boards/arm/nrf5340_audio_dk_nrf5340/CMakeLists.txt deleted file mode 100644 index fa1c1ba14d9..00000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -if ((CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) - zephyr_library() - zephyr_library_sources(nrf5340_audio_dk_cpunet_reset.c) - - if (CONFIG_BUILD_WITH_TFM) - zephyr_library_include_directories( - $/api_ns/interface/include - ) - endif() - -endif() diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig b/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig deleted file mode 100644 index 00e48c60542..00000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# nRF5340 Audio DK board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "nRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "nrf5340_audio_dk_nrf5340_cpunet" - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -config DOMAIN_CPUAPP_BOARD - string - default "nrf5340_audio_dk_nrf5340_cpuapp" - depends on BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.board b/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.board deleted file mode 100644 index 5b407f03564..00000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# nRF5340 Audio DK board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP - bool "nrf5340 Audio DK nRF5340 Application MCU" - -config BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - bool "nrf5340 Audio DK nRF5340 Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -config BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET - bool "nrf5340 Audio DK NRF5340 Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.defconfig b/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.defconfig deleted file mode 100644 index 685ebc49b63..00000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# nRF5340 Audio DK board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -config BOARD - default "nrf5340_audio_dk_nrf5340_cpuapp" if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -config BOARD - default "nrf5340_audio_dk_nrf5340_cpunet" if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET - -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET - -config BT_CTLR - default y if BT - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/board.cmake b/boards/arm/nrf5340_audio_dk_nrf5340/board.cmake deleted file mode 100644 index 4a0cab6c11e..00000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/board.cmake +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) - set(TFM_PUBLIC_KEY_FORMAT "full") -endif() - -if(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) - board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET) - board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/doc/index.rst b/boards/arm/nrf5340_audio_dk_nrf5340/doc/index.rst deleted file mode 100644 index 3d8d2413e91..00000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/doc/index.rst +++ /dev/null @@ -1,109 +0,0 @@ -.. _nrf5340_audio_dk_nrf5340: - -nRF5340 Audio DK -################ - -Overview -******** - -The nRF5340 Audio DK (PCA10121) is designed for showcasing, developing and experimenting -with Bluetooth® LE Audio. - -You can use this board for developing LE-Audio-compatible applications that support Auracast™, -connected isochronous streams (CIS) and broadcast isochronous streams (BIS), -and offer support for acting as a audio source, audio sink and source + sink. - -Zephyr uses the nrf5340_audio_dk_nrf5340 board configuration for building -for the nRF5340 Audio DK. - -Hardware -******** - -The nRF5340 Audio DK comes with the following hardware features: - -* nRF5340 dual-core SoC based on the Arm® Cortex®-M33 architecture -* CS47L63 Low-Power Audio DSP with mono differential headphone driver -* nPM1100 Ultra-small form-factor Power Management IC -* On-board digital microphone -* On-board power measurement -* SD card slot -* Built-in debugger -* Stereo analog input using 3.5 mm jack -* USB soundcard capability - -.. figure:: img/nrf5340_audio_dk.jpg - :align: center - :alt: nRF5340 DK - -More information about the board can be found at the `nRF5340 Audio DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - -nRF5340 SoC -=========== - -The nRF5340 Audio DK is built around the nRF5340 SoC, which has the following characteristics: - -* A full-featured Arm Cortex-M33F core with DSP instructions, - FPU, and Armv8-M Security Extension, running at up to 128 MHz, - referred to as the **application core**. -* A secondary Arm Cortex-M33 core, with a reduced feature set, - running at a fixed 64 MHz, referred to as the **network core**. - -The nrf5340_audio_dk_nrf5340_cpuapp build target provides support for the application -core on the nRF5340 SoC. The nrf5340_audio_dk_nrf5340_cpunet build target provides -support for the network core on the nRF5340 SoC. - -The `Nordic Semiconductor Infocenter`_ contains the processor's information and -the datasheet. - -Supported Features -================== - -See :ref:`nrf5340dk_nrf5340` and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF5340 Audio DK board hardware features. - - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then you can build and flash -applications as usual (:ref:`build_an_application` and -:ref:`application_run` for more details). - -.. warning:: - - The nRF5340 has a flash read-back protection feature. When flash read-back - protection is active, you will need to recover the chip before reflashing. - If you are flashing with :ref:`west `, run - this command for more details on the related ``--recover`` option: - - .. code-block:: console - - west flash -H -r nrfjprog --skip-rebuild - -.. note:: - - Flashing and debugging applications on the nRF5340 Audio DK requires - upgrading the nRF Command Line Tools to version 10.12.0. Further - information on how to install the nRF Command Line Tools can be - found in :ref:`nordic_segger_flashing`. - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic -boards with a Segger IC. - -References -********** - -.. target-notes:: - -.. _nRF5340 Audio DK website: - https://www.nordicsemi.com/Products/Development-hardware/nrf5340-audio-dk -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_defconfig b/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_defconfig deleted file mode 100644 index 2e7ac0ea3cc..00000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP=y - -CONFIG_ARM_MPU=y - -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_ARM_TRUSTZONE_M=y - -CONFIG_GPIO=y - -CONFIG_SERIAL=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_REGULATOR=y diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig b/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig deleted file mode 100644 index 425ae718426..00000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS=y - -CONFIG_ARM_MPU=y - -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -CONFIG_GPIO=y - -CONFIG_SERIAL=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_REGULATOR=y diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet_defconfig b/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet_defconfig deleted file mode 100644 index d0844088568..00000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf5340dk_nrf5340/Kconfig b/boards/arm/nrf5340dk_nrf5340/Kconfig deleted file mode 100644 index 518328e57e8..00000000000 --- a/boards/arm/nrf5340dk_nrf5340/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# nRF5340 DK board configuration - -# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "nrf5340dk_nrf5340_cpunet" - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config DOMAIN_CPUAPP_BOARD - string - default "nrf5340dk_nrf5340_cpuapp" - depends on BOARD_NRF5340DK_NRF5340_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/arm/nrf5340dk_nrf5340/Kconfig.board b/boards/arm/nrf5340dk_nrf5340/Kconfig.board deleted file mode 100644 index e73cb122d80..00000000000 --- a/boards/arm/nrf5340dk_nrf5340/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# nRF5340 DK NRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_NRF5340DK_NRF5340_CPUAPP - bool "nRF5340 DK nRF5340 Application MCU" - -config BOARD_NRF5340DK_NRF5340_CPUAPP_NS - bool "nRF5340 DK nRF5340 Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -config BOARD_NRF5340DK_NRF5340_CPUNET - bool "nRF5340 DK NRF5340 Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/nrf5340dk_nrf5340/Kconfig.defconfig b/boards/arm/nrf5340dk_nrf5340/Kconfig.defconfig deleted file mode 100644 index 84f19365cc5..00000000000 --- a/boards/arm/nrf5340dk_nrf5340/Kconfig.defconfig +++ /dev/null @@ -1,84 +0,0 @@ -# nRF5340 DK nRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config BOARD - default "nrf5340dk_nrf5340_cpuapp" if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_NRF5340DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_NRF5340DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config BOARD - default "nrf5340dk_nrf5340_cpunet" if BOARD_NRF5340DK_NRF5340_CPUNET - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -if BOARD_NRF5340DK_NRF5340_CPUNET - -config BT_CTLR - default y if BT - -endif # BOARD_NRF5340DK_NRF5340_CPUNET diff --git a/boards/arm/nrf5340dk_nrf5340/doc/index.rst b/boards/arm/nrf5340dk_nrf5340/doc/index.rst deleted file mode 100644 index 984090f3879..00000000000 --- a/boards/arm/nrf5340dk_nrf5340/doc/index.rst +++ /dev/null @@ -1,330 +0,0 @@ -.. _nrf5340dk_nrf5340: - -nRF5340 DK -########## - -Overview -******** - -The nRF5340 DK (PCA10095) is a single-board development kit for evaluation -and development on the Nordic nRF5340 System-on-Chip (SoC). - -The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with: - -* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and - Armv8-M Security Extension, running at up to 128 MHz, referred to as - the **application core** -* a secondary Arm Cortex-M33 core, with a reduced feature set, running at - a fixed 64 MHz, referred to as the **network core**. - -The nrf5340dk_nrf5340_cpuapp build target provides support for the application -core on the nRF5340 SoC. The nrf5340dk_nrf5340_cpunet build target provides -support for the network core on the nRF5340 SoC. - -nRF5340 SoC provides support for the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf5340dk.jpg - :align: center - :alt: nRF5340 DK - - nRF5340 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the -`nRF5340 DK website`_. -The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF5340 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf5340dk_nrf5340_cpuapp board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The nrf5340dk_nrf5340_cpunet board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `Nordic Semiconductor Infocenter`_ -for a complete list of nRF5340 DK board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.28 -* LED2 (green) = P0.29 -* LED3 (green) = P0.30 -* LED4 (green) = P0.31 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.23 -* BUTTON2 = SW2 = P0.24 -* BUTTON3 = SW3 = P0.8 -* BUTTON4 = SW4 = P0.9 -* BOOT = SW5 = boot/reset - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_) on the application core. - The IDAU is implemented with the System Protection Unit and is used to - define secure and non-secure memory maps. By default, all of the memory - space (Flash, SRAM, and peripheral address space) is defined to be secure - accessible only. -- Secure boot. - -Programming and Debugging -************************* - -nRF5340 application core supports the Armv8-M Security Extension. -Applications built for the nrf5340dk_nrf5340_cpuapp board by default -boot in the Secure state. - -nRF5340 network core does not support the Armv8-M Security Extension. -nRF5340 IDAU may configure bus accesses by the nRF5340 network core -to have Secure attribute set; the latter allows to build and run -Secure only applications on the nRF5340 SoC. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -Applications on the nRF5340 may contain a Secure and a Non-Secure firmware -image for the application core. The Secure image can be built using either -Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure firmware -images are always built using Zephyr. The two alternatives are described below. - -.. note:: - - By default the Secure image for nRF5340 application core is built - using TF-M. - - -Building the Secure firmware with TF-M --------------------------------------- - -The process to build the Secure firmware image using TF-M and the Non-Secure -firmware image using Zephyr requires the following steps: - -1. Build the Non-Secure Zephyr application - for the application core using ``-DBOARD=nrf5340dk_nrf5340_cpuapp_ns``. - To invoke the building of TF-M the Zephyr build system requires the - Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by - default when building Zephyr as a Non-Secure application. - The Zephyr build system will perform the following steps automatically: - - * Build the Non-Secure firmware image as a regular Zephyr application - * Build a TF-M (secure) firmware image - * Merge the output image binaries together - * Optionally build a bootloader image (MCUboot) - -.. note:: - - Depending on the TF-M configuration, an application DTS overlay may be - required, to adjust the Non-Secure image Flash and SRAM starting address - and sizes. - -2. Build the application firmware for the network core using - ``-DBOARD=nrf5340dk_nrf5340_cpunet``. - - -Building the Secure firmware using Zephyr ------------------------------------------ - -The process to build the Secure and the Non-Secure firmware images -using Zephyr requires the following steps: - -1. Build the Secure Zephyr application for the application core - using ``-DBOARD=nrf5340dk_nrf5340_cpuapp`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` - in the application project configuration file. -2. Build the Non-Secure Zephyr application for the application core - using ``-DBOARD=nrf5340dk_nrf5340_cpuapp_ns``. -3. Merge the two binaries together. -4. Build the application firmware for the network core using - ``-DBOARD=nrf5340dk_nrf5340_cpunet``. - - -When building a Secure/Non-Secure application for the nRF5340 application core, -the Secure application will have to set the IDAU (SPU) configuration to allow -Non-Secure access to all CPU resources utilized by the Non-Secure application -firmware. SPU configuration shall take place before jumping to the Non-Secure -application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf5340dk_nrf5340_cpuapp`` for -the firmware running on the nRF5340 application core, and using -``-DBOARD=nrf5340dk_nrf5340_cpunet`` for the firmware running -on the nRF5340 network core. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then you can build and flash -applications as usual (:ref:`build_an_application` and -:ref:`application_run` for more details). - -.. warning:: - - The nRF5340 has a flash read-back protection feature. When flash read-back - protection is active, you will need to recover the chip before reflashing. - If you are flashing with :ref:`west `, run - this command for more details on the related ``--recover`` option: - - .. code-block:: console - - west flash -H -r nrfjprog --skip-rebuild - -.. note:: - - Flashing and debugging applications on the nRF5340 DK requires - upgrading the nRF Command Line Tools to version 10.12.0. Further - information on how to install the nRF Command Line Tools can be - found in :ref:`nordic_segger_flashing`. - -Here is an example for the :ref:`hello_world` application running on the -nRF5340 application core. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF5340 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf5340dk_nrf5340_cpuapp - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic -boards with a Segger IC. - - -Testing the LEDs and buttons in the nRF5340 DK -********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and -LEDs on the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common.dtsi`. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _nRF5340 DK website: - https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF5340-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet_defconfig b/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet_defconfig deleted file mode 100644 index 47f7b157d06..00000000000 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_NRF5340DK_NRF5340_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board b/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board deleted file mode 100644 index b76cfce6800..00000000000 --- a/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF54H20PDK_NRF54H20_CPUAPP - bool "nRF54H20 PDK nRF54H20 Application MCU" - depends on SOC_NRF54H20_ENGA_CPUAPP - -config BOARD_NRF54H20PDK_NRF54H20_CPURAD - bool "nRF54H20 PDK nRF54H20 Radio MCU" - depends on SOC_NRF54H20_ENGA_CPURAD diff --git a/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig b/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig deleted file mode 100644 index 954276ec829..00000000000 --- a/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "nrf54h20pdk_nrf54h20_cpuapp" if BOARD_NRF54H20PDK_NRF54H20_CPUAPP - default "nrf54h20pdk_nrf54h20_cpurad" if BOARD_NRF54H20PDK_NRF54H20_CPURAD - -if BOARD_NRF54H20PDK_NRF54H20_CPUAPP || BOARD_NRF54H20PDK_NRF54H20_CPURAD - -# Data cache is disabled due to a HW issue in the EngA SoC revision. -config DCACHE - default n - -endif # BOARD_NRF54H20PDK_NRF54H20_CPUAPP || BOARD_NRF54H20PDK_NRF54H20_CPURAD diff --git a/boards/arm/nrf54h20pdk_nrf54h20/doc/index.rst b/boards/arm/nrf54h20pdk_nrf54h20/doc/index.rst deleted file mode 100644 index 3ac79bc791e..00000000000 --- a/boards/arm/nrf54h20pdk_nrf54h20/doc/index.rst +++ /dev/null @@ -1,153 +0,0 @@ -.. _nrf54h20pdk_nrf54h20: - -nRF54H20 PDK -############ - -Overview -******** - -.. note:: - - All software for the nRF54H20 SoC is experimental and hardware availability - is restricted to the participants in the limited sampling program. - -The nRF54H20 PDK is a single-board preview development kit for evaluation -and development on the Nordic nRF54H20 System-on-Chip (SoC). - -The nRF54H20 is a multicore SoC with: - -* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security - Extensions, running at up to 320 MHz, referred to as the **application core** -* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security - Extensions, running at up to 256 MHz, referred to as the **radio core**. - -The ``nrf54h20pdk_nrf54h20_cpuapp`` build target provides support for -the application core on the nRF54H20 SoC. -The ``nrf54h20pdk_nrf54h20_cpurad`` build target provides support for -the radio core on the nRF54H20 SoC. - -nRF54H20 SoC provides support for the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`GPIOTE (General Purpose Input Output tasks and events)` -* :abbr:`GRTC (Global real-time counter)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* MRAM -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf54h20pdk_nrf54h20.webp - :align: center - :alt: nRF54H20 PDK - - nRF54H20 PDK (Credit: Nordic Semiconductor) - -Hardware -******** - -nRF54H20 PDK has two crystal oscillators: - -* High-frequency 32 MHz crystal oscillator (HFXO) -* Low-frequency 32.768 kHz crystal oscillator (LFXO) - -Supported Features -================== - -The nrf54h20pdk_nrf54h20_cpuapp board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GPIOTE | on-chip | gpio | -+-----------+------------+----------------------+ -| GRTC | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ - -The nrf54h20pdk_nrf54h20_cpurad board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GPIOTE | on-chip | gpio | -+-----------+------------+----------------------+ -| GRTC | on-chip | system clock | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -LEDs ----- - -* LED1 (green) = P9.0 -* LED2 (green) = P9.1 -* LED3 (green) = P9.2 -* LED4 (green) = P9.3 - -Push buttons ------------- - -* BUTTON1 = P0.8 -* BUTTON2 = P0.9 -* BUTTON3 = P0.10 -* BUTTON4 = P0.11 -* RESET (SW1) - -Programming and Debugging -************************* - -Applications for both the ``nrf54h20pdk_nrf54h20_cpuapp`` and -``nrf54h20pdk_nrf54h20_cpurad`` targets can be built, flashed, -and debugged in the usual way. See :ref:`build_an_application` -and :ref:`application_run` for more details on building and running. - -Flashing -======== - -As an example, this section shows how to build and flash the :ref:`hello_world` -application. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. - -To build and program the sample to the nRF54H20 PDK, complete the following steps: - -First, connect the nRF54H20 PDK to you computer using the IMCU USB port on the PDK. -Next, build the sample by running the following command: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf54h20pdk_nrf54h20_cpuapp - :goals: build flash - -Testing the LEDs and buttons in the nRF54H20 PDK -************************************************ - -There are 2 samples that allow you to test that the buttons (switches) and LEDs -on the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts`. diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp_defconfig b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp_defconfig deleted file mode 100644 index 1f7ef38a7fc..00000000000 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF54HX=y -CONFIG_SOC_NRF54H20=y -CONFIG_SOC_NRF54H20_ENGA_CPUAPP=y -CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPUAPP=y - -CONFIG_USE_DT_CODE_PARTITION=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# MPU-based null-pointer dereferencing detection cannot be applied -# as the (0x0 - 0x400) region is unmapped for this target. -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y - -# Enable cache -CONFIG_CACHE_MANAGEMENT=y -CONFIG_EXTERNAL_CACHE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad_defconfig b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad_defconfig deleted file mode 100644 index 254d8656e61..00000000000 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF54HX=y -CONFIG_SOC_NRF54H20=y -CONFIG_SOC_NRF54H20_ENGA_CPURAD=y -CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPURAD=y - -CONFIG_USE_DT_CODE_PARTITION=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# MPU-based null-pointer dereferencing detection cannot be applied -# as the (0x0 - 0x400) region is unmapped for this target. -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y - -# Enable cache -CONFIG_CACHE_MANAGEMENT=y -CONFIG_EXTERNAL_CACHE=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.board b/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.board deleted file mode 100644 index d95fe51009f..00000000000 --- a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF54L15PDK_NRF54L15_CPUAPP - bool "nRF54L15 PDK nRF54L15 Application MCU" - depends on SOC_NRF54L15_ENGA_CPUAPP diff --git a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig b/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig deleted file mode 100644 index 532ea07c859..00000000000 --- a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF54L15PDK_NRF54L15_CPUAPP - -config BOARD - default "nrf54l15pdk_nrf54l15_cpuapp" - -config BT_CTLR - default BT - -endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP diff --git a/boards/arm/nrf54l15pdk_nrf54l15/doc/index.rst b/boards/arm/nrf54l15pdk_nrf54l15/doc/index.rst deleted file mode 100644 index dce1c841b1c..00000000000 --- a/boards/arm/nrf54l15pdk_nrf54l15/doc/index.rst +++ /dev/null @@ -1,139 +0,0 @@ -.. _nrf54l15pdk_nrf54l15: - -nRF54L15 PDK -############ - -Overview -******** - -.. note:: - - All software for the nRF54L15 SoC is experimental and hardware availability - is restricted to the participants in the limited sampling program. - -The nRF54L15 Preview Development Kit hardware provides -support for the Nordic Semiconductor nRF54L15 Arm Cortex-M33 CPU and -the following devices: - -* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)` -* CLOCK -* RRAM -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`GRTC (Global real-time counter)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf54l15pdk_nrf54l15.webp - :align: center - :alt: nRF54L15 PDK - - nRF54L15 PDK (Credit: Nordic Semiconductor) - -Hardware -******** - -nRF54L15 PDK has two crystal oscillators: - -* High-frequency 32 MHz crystal oscillator (HFXO) -* Low-frequency 32.768 kHz crystal oscillator (LFXO) - -The crystal oscillators can be configured to use either -internal or external capacitors. - -Supported Features -================== - -The nrf54l15pdk_nrf54l15 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| SAADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| RRAM | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| TWIM | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| GRTC | on-chip | counter | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Programming and Debugging -************************* - -Applications for the ``nrf54l15pdk_nrf54l15_cpuapp`` board can be -built, flashed, and debugged in the usual way. See -:ref:`build_an_application` and :ref:`application_run` for more details on -building and running. - -Flashing -======== - -As an example, this section shows how to build and flash the :ref:`hello_world` -application. - -.. warning:: - - When programming the device, you might get an error similar to the following message:: - - ERROR: The operation attempted is unavailable due to readback protection in - ERROR: your device. Please use --recover to unlock the device. - - This error occurs when readback protection is enabled. - To disable the readback protection, you must *recover* your device. - - Enter the following command to recover the core:: - - west flash --recover - - The ``--recover`` command erases the flash memory and then writes a small binary into - the recovered flash memory. - This binary prevents the readback protection from enabling itself again after a pin - reset or power cycle. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. - -To build and program the sample to the nRF54L15 PDK, complete the following steps: - -First, connect the nRF54L15 PDK to you computer using the IMCU USB port on the PDK. -Next, build the sample by running the following command: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf54l15pdk_nrf54l15_cpuapp - :goals: build flash - -Testing the LEDs and buttons in the nRF54L15 PDK -************************************************ - -Test the nRF54L15 PDK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/arm/nrf9131ek_nrf9131/Kconfig.board b/boards/arm/nrf9131ek_nrf9131/Kconfig.board deleted file mode 100644 index 4a237e3fb61..00000000000 --- a/boards/arm/nrf9131ek_nrf9131/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9131-EK board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9131_LACA - -config BOARD_NRF9131EK_NRF9131 - bool "nRF9131 EK NRF9131" - -config BOARD_NRF9131EK_NRF9131_NS - bool "nRF9131 EK NRF9131 non-secure" - -endif # SOC_NRF9131_LACA diff --git a/boards/arm/nrf9131ek_nrf9131/Kconfig.defconfig b/boards/arm/nrf9131ek_nrf9131/Kconfig.defconfig deleted file mode 100644 index 0ece4f9a2ac..00000000000 --- a/boards/arm/nrf9131ek_nrf9131/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# nRF9131 EK NRF9131 board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9131EK_NRF9131 || BOARD_NRF9131EK_NRF9131_NS - -config BOARD - default "nrf9131ek_nrf9131" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_NRF9131EK_NRF9131 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9131EK_NRF9131_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9131EK_NRF9131_NS - -endif # BOARD_NRF9131EK_NRF9131 || BOARD_NRF9131EK_NRF9131_NS diff --git a/boards/arm/nrf9131ek_nrf9131/doc/index.rst b/boards/arm/nrf9131ek_nrf9131/doc/index.rst deleted file mode 100644 index 57473c631ed..00000000000 --- a/boards/arm/nrf9131ek_nrf9131/doc/index.rst +++ /dev/null @@ -1,229 +0,0 @@ -.. _nrf9131ek_nrf9131: - -nRF9131 EK -########## - -Overview -******** - -The nRF9131 EK (PCA10165) is a single-board evaluation kit for the nRF9131 SiP -for DECT NR+ and LTE-M/NB-IoT with GNSS. -The nrf9131ek_nrf9131 board configuration provides support for the Nordic Semiconductor nRF9131 ARM -Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -.. figure:: img/nrf9131ek_nrf9131.webp - :align: center - :alt: nRF9131 EK - - nRF9131 EK (Credit: Nordic Semiconductor) - -The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF9131 EK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf9131ek_nrf9131 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -LED ---- - -* LED (red) = P0.29 -* LED (green) = P0.30 -* LED (blue) = P0.31 - -Push buttons and Switches -------------------------- - -* BUTTON = P0.28 -* RESET - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - - -Programming and Debugging -************************* - -nrf9131ek_nrf9131 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -Applications on the nRF9131 may contain a Secure and a Non-Secure firmware -image. The Secure image can be built using either Zephyr or -`Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built -using Zephyr. The two alternatives are described below. - -.. note:: - - By default the Secure image for nRF9131 is built using TF-M. - -Building the Secure firmware using Zephyr ------------------------------------------ - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9131ek_nrf9131`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9131ek_nrf9131_ns``. -3. Merge the two binaries together. - -Building the Secure firmware with TF-M --------------------------------------- - -The process to build the Secure firmware image using TF-M and the Non-Secure -firmware image using Zephyr requires the following action: - -1. Build the Non-Secure Zephyr application - using ``-DBOARD=nrf9131ek_nrf9131_ns``. - To invoke the building of TF-M the Zephyr build system requires the - Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by - default when building Zephyr as a Non-Secure application. - The Zephyr build system will perform the following steps automatically: - - * Build the Non-Secure firmware image as a regular Zephyr application - * Build a TF-M (secure) firmware image - * Merge the output binaries together - * Optionally build a bootloader image (MCUboot) - -.. note:: - - Depending on the TF-M configuration, an application DTS overlay may be - required, to adjust the Non-Secure image Flash and SRAM starting address - and sizes. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9131ek_nrf9131``. - - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9131 EK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9131ek_nrf9131 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF9131 EK -********************************************** - -There are 2 samples that allow you to test that the button and LED on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_common.dtsi`. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_defconfig b/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_defconfig deleted file mode 100644 index fc77ffe0d13..00000000000 --- a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9131_LACA=y -CONFIG_BOARD_NRF9131EK_NRF9131=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_PINCTRL=y diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns_defconfig b/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns_defconfig deleted file mode 100644 index 83af1cf6b74..00000000000 --- a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns_defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9131_LACA=y -CONFIG_BOARD_NRF9131EK_NRF9131_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_PINCTRL=y - -# enable PMIC -CONFIG_I2C=y -CONFIG_REGULATOR=y -CONFIG_SENSOR=y -CONFIG_NPM1300_CHARGER=y diff --git a/boards/arm/nrf9151dk_nrf9151/Kconfig.board b/boards/arm/nrf9151dk_nrf9151/Kconfig.board deleted file mode 100644 index 92352ddc16f..00000000000 --- a/boards/arm/nrf9151dk_nrf9151/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9151 DK NRF9151 board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9151_LACA - -config BOARD_NRF9151DK_NRF9151 - bool "nRF9151 DK NRF9151" - -config BOARD_NRF9151DK_NRF9151_NS - bool "nRF9151 DK NRF9151 non-secure" - -endif # SOC_NRF9151_LACA diff --git a/boards/arm/nrf9151dk_nrf9151/Kconfig.defconfig b/boards/arm/nrf9151dk_nrf9151/Kconfig.defconfig deleted file mode 100644 index 3cbff101d63..00000000000 --- a/boards/arm/nrf9151dk_nrf9151/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# nRF9151 DK NRF9151 board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9151DK_NRF9151 || BOARD_NRF9151DK_NRF9151_NS - -config BOARD - default "nrf9151dk_nrf9151" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_NRF9151DK_NRF9151 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9151DK_NRF9151_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9151DK_NRF9151_NS - -config BT_HCI_VS - default y if BT - -config BT_WAIT_NOP - default BT && $(dt_nodelabel_enabled,nrf5340_reset) - -config I2C - default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) - -endif # BOARD_NRF9151DK_NRF9151 || BOARD_NRF9151DK_NRF9151_NS diff --git a/boards/arm/nrf9151dk_nrf9151/doc/index.rst b/boards/arm/nrf9151dk_nrf9151/doc/index.rst deleted file mode 100644 index 4c02e7ed372..00000000000 --- a/boards/arm/nrf9151dk_nrf9151/doc/index.rst +++ /dev/null @@ -1,203 +0,0 @@ -.. _nrf9151dk_nrf9151: - -nRF9151 DK -########## - -Overview -******** - -The nRF9151 DK (PCA10171) is a single-board development kit for evaluation and -development on the nRF9151 SiP for DECT NR+ and LTE-M/NB-IoT with GNSS. The nrf9151dk_nrf9151 -board configuration provides support for the Nordic Semiconductor nRF9151 ARM -Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -More information about the board can be found at the -`nRF9151 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF9151 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf9151dk_nrf9151 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| FLASH | external | spi | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GPIO | external | i2c | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | nRF53 | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - - -.. _nrf9151dk_additional_hardware: - -Other hardware features have not been enabled yet for this board. -See `nRF9151 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF9151 DK board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.0 -* LED2 (green) = P0.1 -* LED3 (green) = P0.4 -* LED4 (green) = P0.5 - -Push buttons and Switches -------------------------- - -* BUTTON1 = P0.8 -* BUTTON2 = P0.9 -* SWITCH1 = P0.18 -* SWITCH2 = P0.19 -* BOOT = SW5 = boot/reset - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - - -Programming and Debugging -************************* - -nrf9151dk_nrf9151 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9151dk_nrf9151`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9151dk_nrf9151_ns``. -3. Merge the two binaries together. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9151dk_nrf9151``. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9151 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9151dk_nrf9151 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF9151 DK -********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_common.dtsi`. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _nRF9151 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9151-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_defconfig b/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_defconfig deleted file mode 100644 index 7afe5ac7aa9..00000000000 --- a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9151_LACA=y -CONFIG_BOARD_NRF9151DK_NRF9151=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns_defconfig b/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns_defconfig deleted file mode 100644 index 949ef39f856..00000000000 --- a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9151_LACA=y -CONFIG_BOARD_NRF9151DK_NRF9151_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue21/Kconfig.board b/boards/arm/nrf9160_innblue21/Kconfig.board deleted file mode 100644 index af6b5478f9e..00000000000 --- a/boards/arm/nrf9160_innblue21/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9160 innblue V2.1 board configuration - -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_NRF9160_INNBLUE21 - bool "nRF9160 innblue v2.1" - -config BOARD_NRF9160_INNBLUE21_NS - bool "nRF9160 innblue v2.1 non-secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/nrf9160_innblue21/Kconfig.defconfig b/boards/arm/nrf9160_innblue21/Kconfig.defconfig deleted file mode 100644 index 08d0409c9af..00000000000 --- a/boards/arm/nrf9160_innblue21/Kconfig.defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# nRF9160 innblue V2.1 board configuration - -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9160_INNBLUE21 || BOARD_NRF9160_INNBLUE21_NS - -config BOARD - default "nrf9160_innblue21" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -if BOARD_NRF9160_INNBLUE21 && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9160_INNBLUE21 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9160_INNBLUE21_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9160_INNBLUE21_NS - -config BT_HCI_VS - default y if BT - -config REGULATOR - default y if SENSOR - -endif # BOARD_NRF9160_INNBLUE21 || BOARD_NRF9160_INNBLUE21_NS diff --git a/boards/arm/nrf9160_innblue21/doc/index.rst b/boards/arm/nrf9160_innblue21/doc/index.rst deleted file mode 100644 index c0f9e33cd75..00000000000 --- a/boards/arm/nrf9160_innblue21/doc/index.rst +++ /dev/null @@ -1,144 +0,0 @@ -.. _nrf9160_innblue21: - -nRF9160 INNBLUE21 -################# - -Overview -******** - -The nRF9160 innblue21 is a cellular IoT sensor development board, which -is based on the nRF9160 SiP, and features NB-IoT and LTE-M connectivity. - -.. figure:: img/nrf9160_innblue21.jpg - :align: center - :alt: nRF9160 innblue21 - - nRF9160 innblue21 (Credit: innblue) - -Hardware -******** - -The following parts are built into the board: - -* Accelerometer: ST LIS2DH12 -* CryptoElement: Atmel ATECC608a -* Humidity Sensor: ST HTS221 -* Qi charger: TI BQ51013 -* Battery fuel gauge: TI BQ27421 - -Supported Features -================== - -The nrf9160_innblue21 board configuration supports the following -hardware (as of nRF9160) features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -LED ---- - -* LED1 ( red ) = P0.7 -* LED2 (green) = P0.6 -* LED3 ( blue) = P0.5 -* LED4 ( red ) = P0.4 - -Push buttons and Switches -------------------------- - -* BUTTON1 = P0.31 - -Security components -=================== - -- Implementation Defined Attribution Unit. The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Programming and Debugging -************************* - -nrf9160_innblue21 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9160_innblue21`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9160_innblue21_ns``. -3. Merge the two binaries together. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9160_innblue21``. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9160 innblue21 -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9160_innblue21 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21.dts b/boards/arm/nrf9160_innblue21/nrf9160_innblue21.dts deleted file mode 100644 index af9e3a2e784..00000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf9160_innblue21_common.dtsi" - -/ { - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21.yaml b/boards/arm/nrf9160_innblue21/nrf9160_innblue21.yaml deleted file mode 100644 index 3c5100852c9..00000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf9160_innblue21 -name: nRF9160-INNBLUE21 -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - i2c - - pwm - - watchdog diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_common.dtsi b/boards/arm/nrf9160_innblue21/nrf9160_innblue21_common.dtsi deleted file mode 100644 index 0ec5de5dfb1..00000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_common.dtsi +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "nrf9160_innblue21_common-pinctrl.dtsi" -#include - -/ { - model = "innblue v21 Dev Kit"; - compatible = "innblue,innblue21"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - }; - - leds { - compatible = "gpio-leds"; - red_led: led_1 { - gpios = <&gpio0 7 0>; - label = "RGB red channel"; - }; - green_led: led_2 { - gpios = <&gpio0 6 0>; - label = "RGB green channel"; - }; - blue_led: led_3 { - gpios = <&gpio0 5 0>; - label = "RGB blue channel"; - }; - - mode_led: led_4 { - gpios = <&gpio0 4 0>; - label = "mode red channel"; - }; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio0 31 GPIO_PULL_UP>; - label = "Button 0"; - zephyr,code = ; - }; - }; - - en_3v3_sensor: enable-3v3-sensor { - compatible = "regulator-fixed"; - regulator-name = "en_3v3_sensor"; - enable-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - startup-delay-us = <10000>; - regulator-boot-on; - }; - - en_5v0_boost: enable-5v0-boost { - compatible = "regulator-fixed"; - regulator-name = "en_5v0_boost"; - enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - startup-delay-us = <10000>; - regulator-boot-on; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &red_led; - led1 = &green_led; - led2 = &blue_led; - led3 = &mode_led; - sw0 = &button0; - rgb-pwm = &pwm0; - mode-pwm = &pwm1; - watchdog0 = &wdt0; - accel0 = &lis2dh12_accel; - }; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-1 = <&uart2_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&i2c2 { - compatible = "nordic,nrf-twim"; - status = "okay"; - - clock-frequency = ; - - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; - pinctrl-names = "default", "sleep"; - lis2dh12_accel: lis2dh12-accel@19 { - compatible = "st,lis2dh"; - reg = <0x19>; - irq-gpios = <&gpio0 0 0>, <&gpio0 1 0>; - }; - - hts221@5f { - compatible = "st,hts221"; - reg = <0x5f>; - drdy-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - }; - - lps22hb-press@5c { - compatible = "st,lps22hb-press"; - reg = <0x5c>; - }; - - ccs811: ccs811@5a { - compatible = "ams,ccs811"; - reg = <0x5a>; - }; - - bme680@76 { - compatible = "bosch,bme680"; - reg = <0x76>; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_default>; - pinctrl-1 = <&pwm0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm1 { - status = "okay"; - pinctrl-0 = <&pwm1_default>; - pinctrl-1 = <&pwm1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -/ { - /* SRAM allocated and used by the BSD library */ - sram0_bsd: memory@20010000 { - compatible = "mmio-sram"; - }; - - /* SRAM allocated to the Non-Secure image */ - sram0_ns: memory@20020000 { - compatible = "mmio-sram"; - }; -}; - -/* Include partition configuration file */ -#include "nrf9160_innblue21_partition_conf.dtsi" diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_defconfig b/boards/arm/nrf9160_innblue21/nrf9160_innblue21_defconfig deleted file mode 100644 index 7c0e84c1abd..00000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -# SOC / Board -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160_INNBLUE21=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.dts b/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.dts deleted file mode 100644 index 8343318db22..00000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf9160_innblue21_common.dtsi" - -/ { - chosen { - zephyr,flash = &flash0; - zephyr,sram = &sram0_ns; - zephyr,code-partition = &slot0_ns_partition; - }; -}; diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.yaml b/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.yaml deleted file mode 100644 index 4584ad0e6a4..00000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf9160_innblue21_ns -name: nRF9160-INNBLUE21-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - i2c - - pwm - - watchdog diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns_defconfig b/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns_defconfig deleted file mode 100644 index 4f5410848bc..00000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -# SOC / Board -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160_INNBLUE21_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue22/Kconfig.board b/boards/arm/nrf9160_innblue22/Kconfig.board deleted file mode 100644 index e805798790a..00000000000 --- a/boards/arm/nrf9160_innblue22/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9160 innblue V2.2 board configuration - -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_NRF9160_INNBLUE22 - bool "nRF9160 innblue v2.2" - -config BOARD_NRF9160_INNBLUE22_NS - bool "nRF9160 innblue V2.2 non-secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/nrf9160_innblue22/Kconfig.defconfig b/boards/arm/nrf9160_innblue22/Kconfig.defconfig deleted file mode 100644 index d50bdcc9d97..00000000000 --- a/boards/arm/nrf9160_innblue22/Kconfig.defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# nRF9160 innblue V2.2 board configuration - -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9160_INNBLUE22 || BOARD_NRF9160_INNBLUE22_NS - -config BOARD - default "nrf9160_innblue22" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -if BOARD_NRF9160_INNBLUE22 && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9160_INNBLUE22 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9160_INNBLUE22_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9160_INNBLUE22_NS - -config BT_HCI_VS - default y if BT - -config REGULATOR - default y if SENSOR - -endif # BOARD_NRF9160_INNBLUE22 || BOARD_NRF9160_INNBLUE22_NS diff --git a/boards/arm/nrf9160_innblue22/doc/index.rst b/boards/arm/nrf9160_innblue22/doc/index.rst deleted file mode 100644 index 0f2f83bcfe1..00000000000 --- a/boards/arm/nrf9160_innblue22/doc/index.rst +++ /dev/null @@ -1,144 +0,0 @@ -.. _nrf9160_innblue22: - -nRF9160 INNBLUE22 -################# - -Overview -******** - -The nRF9160 innblue22 is a cellular IoT sensor development board, which -is based on the nRF9160 SiP, and features NB-IoT and LTE-M connectivity. - -.. figure:: img/nrf9160_innblue22.jpg - :align: center - :alt: nRF9160 innblue22 - - nRF9160 innblue22 (Credit: innblue) - -Hardware -******** - -The following parts are built into the board: - -* Accelerometer: ST LIS2DH12 -* CryptoElement: Atmel ATECC608a -* Humidity Sensor: ST HTS221 -* Qi charger: TI BQ51013 -* Battery fuel gauge: TI BQ27421 - -Supported Features -================== - -The nrf9160_innblue22 board configuration supports the following -hardware (as of nRF9160) features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -LED ---- - -* LED1 ( red ) = P0.7 -* LED2 (green) = P0.6 -* LED3 ( blue) = P0.5 -* LED4 ( red ) = P0.4 - -Push buttons and Switches -------------------------- - -* BUTTON1 = P0.31 - -Security components -=================== - -- Implementation Defined Attribution Unit. The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Programming and Debugging -************************* - -nrf9160_innblue22 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9160_innblue22`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9160_innblue22_ns``. -3. Merge the two binaries together. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9160_innblue22``. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9160 innblue22 -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9160_innblue22 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22.dts b/boards/arm/nrf9160_innblue22/nrf9160_innblue22.dts deleted file mode 100644 index 61c376e61e7..00000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf9160_innblue22_common.dtsi" - -/ { - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22.yaml b/boards/arm/nrf9160_innblue22/nrf9160_innblue22.yaml deleted file mode 100644 index a4ec1d1266e..00000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf9160_innblue22 -name: nRF9160-INNBLUE22 -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - i2c - - pwm - - watchdog diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_common.dtsi b/boards/arm/nrf9160_innblue22/nrf9160_innblue22_common.dtsi deleted file mode 100644 index 4738dd84a63..00000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_common.dtsi +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "nrf9160_innblue22_common-pinctrl.dtsi" -#include - -/ { - model = "innblue v22 Dev Kit"; - compatible = "innblue,innblue22"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - }; - - leds { - compatible = "gpio-leds"; - red_led: led_1 { - gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - label = "RGB red channel"; - }; - green_led: led_2 { - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - label = "RGB green channel"; - }; - blue_led: led_3 { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "RGB blue channel"; - }; - - mode_led: led_4 { - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - label = "mode red channel"; - }; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio0 31 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Button 0"; - zephyr,code = ; - }; - }; - - en_5v0_boost: enable-5v0-boost { - compatible = "regulator-fixed"; - regulator-name = "en_5v0_boost"; - enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - startup-delay-us = <10000>; - regulator-boot-on; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &red_led; - led1 = &green_led; - led2 = &blue_led; - led3 = &mode_led; - sw0 = &button0; - rgb-pwm = &pwm0; - mode-pwm = &pwm1; - watchdog0 = &wdt0; - accel0 = &lis2dh12_accel; - }; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-1 = <&uart2_sleep>; - pinctrl-names = "default", "sleep"; -}; - - -&i2c2 { - compatible = "nordic,nrf-twim"; - status = "okay"; - - clock-frequency = ; - - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; - pinctrl-names = "default", "sleep"; - bq27421@55 { - compatible = "ti,bq274xx"; - reg = <0x55>; - design-voltage = <3700>; - design-capacity = <1800>; - taper-current = <45>; - terminate-voltage = <3000>; - }; - - lis2dh12_accel: lis2dh12-accel@19 { - compatible = "st,lis2dh"; - reg = <0x19>; - irq-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>; - }; - - hts221@5f { - compatible = "st,hts221"; - reg = <0x5f>; - drdy-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - }; - - lps22hb-press@5c { - compatible = "st,lps22hb-press"; - reg = <0x5c>; - }; - - ccs811: ccs811@5a { - compatible = "ams,ccs811"; - reg = <0x5a>; - }; - - bme680@76 { - compatible = "bosch,bme680"; - reg = <0x76>; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_default>; - pinctrl-1 = <&pwm0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm1 { - status = "okay"; - pinctrl-0 = <&pwm1_default>; - pinctrl-1 = <&pwm1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -/ { - /* SRAM allocated and used by the BSD library */ - sram0_bsd: memory@20010000 { - compatible = "mmio-sram"; - }; - - /* SRAM allocated to the Non-Secure image */ - sram0_ns: memory@20020000 { - compatible = "mmio-sram"; - }; -}; - -/* Include partition configuration file */ -#include "nrf9160_innblue22_partition_conf.dtsi" diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_defconfig b/boards/arm/nrf9160_innblue22/nrf9160_innblue22_defconfig deleted file mode 100644 index ae9e2e2413e..00000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -# SOC / Board -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160_INNBLUE22=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.dts b/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.dts deleted file mode 100644 index f68b3505925..00000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf9160_innblue22_common.dtsi" - -/ { - chosen { - zephyr,flash = &flash0; - zephyr,sram = &sram0_ns; - zephyr,code-partition = &slot0_ns_partition; - }; -}; diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.yaml b/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.yaml deleted file mode 100644 index 0186c26a377..00000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf9160_innblue22_ns -name: nRF9160-INNBLUE22-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - i2c - - pwm - - watchdog diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns_defconfig b/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns_defconfig deleted file mode 100644 index e956d4d8b75..00000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -# SOC / Board -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160_INNBLUE22_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf52840/Kconfig b/boards/arm/nrf9160dk_nrf52840/Kconfig deleted file mode 100644 index c126d2509cb..00000000000 --- a/boards/arm/nrf9160dk_nrf52840/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# nRF9160 DK NRF52840 board configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9160DK_NRF52840 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -module = BOARD_NRF9160DK -module-str = Board Control -source "subsys/logging/Kconfig.template.log_config" - -endif # BOARD_NRF52840_NRF9160DK diff --git a/boards/arm/nrf9160dk_nrf52840/Kconfig.board b/boards/arm/nrf9160dk_nrf52840/Kconfig.board deleted file mode 100644 index b4a46cc9eca..00000000000 --- a/boards/arm/nrf9160dk_nrf52840/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# nRF9160 DK NRF52840 board configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF9160DK_NRF52840 - bool "NRF9160 DK NRF52840" - depends on SOC_NRF52840_QIAA - # The GPIO driver is required by this board's initialization code - # (board.c), so it is forced here to be enabled always, not only - # enabled by default (in defconfig). - select GPIO diff --git a/boards/arm/nrf9160dk_nrf52840/Kconfig.defconfig b/boards/arm/nrf9160dk_nrf52840/Kconfig.defconfig deleted file mode 100644 index dc3c3c3caae..00000000000 --- a/boards/arm/nrf9160dk_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# nRF9160 DK NRF52840 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9160DK_NRF52840 - -config BOARD - default "nrf9160dk_nrf52840" - -config BT_CTLR - default BT - -config BT_WAIT_NOP - default BT && $(dt_nodelabel_enabled,reset_input) - -endif # BOARD_NRF9160DK_NRF52840 diff --git a/boards/arm/nrf9160dk_nrf52840/board.cmake b/boards/arm/nrf9160dk_nrf52840/board.cmake deleted file mode 100644 index f505d2c380e..00000000000 --- a/boards/arm/nrf9160dk_nrf52840/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/nrf9160dk_nrf52840/doc/index.rst b/boards/arm/nrf9160dk_nrf52840/doc/index.rst deleted file mode 100644 index e16d6bc30e4..00000000000 --- a/boards/arm/nrf9160dk_nrf52840/doc/index.rst +++ /dev/null @@ -1,266 +0,0 @@ -.. _nrf9160dk_nrf52840: - -nRF9160 DK - nRF52840 -##################### - -Overview -******** - -The nRF52840 SoC on the nRF9160 DK (PCA10090) hardware provides support for the -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: - -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -The nRF52840 SoC does not have any connection to the any of the LEDs, -buttons, switches, and Arduino pin headers on the nRF9160 DK board. It is, -however, possible to route some of the pins of the nRF52840 SoC to the nRF9160 -SiP. - -More information about the board can be found at -the `Nordic Low power cellular IoT`_ website. -The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -The nRF9160 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf9160dk_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Programming and Debugging -************************* - -Applications for the ``nrf9160dk_nrf52840`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - -Make sure that the PROG/DEBUG switch on the DK is set to nRF52. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Remember to set the PROG/DEBUG switch on the DK to nRF52. - -See the following example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF52840 SoC is connected -to. Usually, under Linux it will be ``/dev/ttyACM1``. The ``/dev/ttyACM0`` -port is connected to the nRF9160 SiP on the board. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9160dk_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards -with a Segger IC. - -Remember to set the PROG/DEBUG switch on the DK to nRF52. - -.. _nrf9160dk_board_controller_firmware: - -Board controller firmware -************************* - -The board controller firmware is a small snippet of code that takes care of -routing specific pins of the nRF9160 SiP to different components on the DK, -such as LEDs and buttons, UART interfaces (VCOMx) of the interface MCU, and -specific nRF52840 SoC pins. - -.. note:: - In nRF9160 DK revisions earlier than v0.14.0, nRF9160 signals routed to - other components on the DK are not simultaneously available on the DK - connectors. - -When compiling a project for nrf9160dk_nrf52840, the board controller firmware -will be compiled and run automatically after the Kernel has been initialized. - -By default, the board controller firmware will route the following: - -+--------------------------------+----------------------------------+ -| nRF9160 pins | Routed to | -+================================+==================================+ -| P0.26, P0.27, P0.28, and P0.29 | VCOM0 | -+--------------------------------+----------------------------------+ -| P0.01, P0.00, P0.15, and P0.14 | VCOM2 | -+--------------------------------+----------------------------------+ -| P0.02 | LED1 | -+--------------------------------+----------------------------------+ -| P0.03 | LED2 | -+--------------------------------+----------------------------------+ -| P0.04 | LED3 | -+--------------------------------+----------------------------------+ -| P0.05 | LED4 | -+--------------------------------+----------------------------------+ -| P0.08 | Switch 1 | -+--------------------------------+----------------------------------+ -| P0.09 | Switch 2 | -+--------------------------------+----------------------------------+ -| P0.06 | Button 1 | -+--------------------------------+----------------------------------+ -| P0.07 | Button 2 | -+--------------------------------+----------------------------------+ -| P0.17, P0.18, and P0.19 | Arduino pin headers | -+--------------------------------+----------------------------------+ -| P0.21, P0.22, and P0.23 | Trace interface | -+--------------------------------+----------------------------------+ -| COEX0, COEX1, and COEX2 | COEX interface | -+--------------------------------+----------------------------------+ - -For a complete list of all the routing options available, -see the `nRF9160 DK board control section in the nRF9160 DK User Guide`_. - -If you want to route some of the above pins differently or enable any of the -other available routing options, enable or disable the devicetree node that -represents the analog switch that provides the given routing. - -The following devicetree nodes are defined for the analog switches present -on the nRF9160 DK: - -+------------------------------------+------------------------------+ -| Devicetree node label | Analog switch name | -+====================================+==============================+ -| ``vcom0_pins_routing`` | nRF91_UART1 (nRF91_APP1) | -+------------------------------------+------------------------------+ -| ``vcom2_pins_routing`` | nRF91_UART2 (nRF91_APP2) | -+------------------------------------+------------------------------+ -| ``led1_pin_routing`` | nRF91_LED1 | -+------------------------------------+------------------------------+ -| ``led2_pin_routing`` | nRF91_LED2 | -+------------------------------------+------------------------------+ -| ``led3_pin_routing`` | nRF91_LED3 | -+------------------------------------+------------------------------+ -| ``led4_pin_routing`` | nRF91_LED4 | -+------------------------------------+------------------------------+ -| ``switch1_pin_routing`` | nRF91_SWITCH1 | -+------------------------------------+------------------------------+ -| ``switch2_pin_routing`` | nRF91_SWITCH2 | -+------------------------------------+------------------------------+ -| ``button1_pin_routing`` | nRF91_BUTTON1 | -+------------------------------------+------------------------------+ -| ``button2_pin_routing`` | nRF91_BUTTON2 | -+------------------------------------+------------------------------+ -| ``nrf_interface_pins_0_2_routing`` | nRF_IF0-2_CTRL (nRF91_GPIO) | -+------------------------------------+------------------------------+ -| ``nrf_interface_pins_3_5_routing`` | nRF_IF3-5_CTRL (nRF91_TRACE) | -+------------------------------------+------------------------------+ -| ``nrf_interface_pins_6_8_routing`` | nRF_IF6-8_CTRL (nRF91_COEX) | -+------------------------------------+------------------------------+ - -When building for the DK revision 0.14.0 or later, you can use the following -additional nodes (see :ref:`application_board_version` for information how to -build for specific revisions of the board): - -+------------------------------------+------------------------------+ -| Devicetree node label | Analog switch name | -+====================================+==============================+ -| ``nrf_interface_pin_9_routing`` | nRF_IF9_CTRL | -+------------------------------------+------------------------------+ -| ``io_expander_pins_routing`` | IO_EXP_EN | -+------------------------------------+------------------------------+ -| ``external_flash_pins_routing`` | EXT_MEM_CTRL | -+------------------------------------+------------------------------+ - -For example, if you want to enable the optional routing for the nRF9160 pins -P0.17, P0.18, and P0.19 so that they are routed to nRF52840 pins P0.17, P0.20, -and P0.15, respectively, add the following in the devicetree overlay in your -application: - -.. code-block:: devicetree - - &nrf_interface_pins_0_2_routing { - status = "okay"; - }; - -And if you want to, for example, disable routing for the VCOM2 pins, add the -following: - -.. code-block:: devicetree - - &vcom2_pins_routing { - status = "disabled"; - }; - -A few helper .dtsi files are provided in the directories -:zephyr_file:`boards/arm/nrf9160dk_nrf52840/dts` and -:zephyr_file:`boards/arm/nrf9160dk_nrf9160/dts`. They can serve as examples of -how to configure and use the above routings. You can also include them from -respective devicetree overlay files in your applications to conveniently -configure the signal routing between nRF9160 and nRF52840 on the nRF9160 DK. -For example, to use ``uart1`` on both these chips for communication between -them, add the following line in the overlays for applications on both sides: - -.. code-block:: devicetree - - #include - -References -********** - -.. target-notes:: -.. _Nordic Low power cellular IoT: https://www.nordicsemi.com/Products/Low-power-cellular-IoT -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _nRF9160 DK board control section in the nRF9160 DK User Guide: https://infocenter.nordicsemi.com/topic/ug_nrf91_dk/UG/nrf91_DK/board_controller.html diff --git a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.yaml b/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.yaml deleted file mode 100644 index 4b9ffc34035..00000000000 --- a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf9160dk_nrf52840 -name: nRF9160-DK-NRF52840 -type: mcu -arch: arm -ram: 64 -flash: 512 -toolchain: - - zephyr - - gnuarmemb -supported: - - ble - - netif:openthread - - gpio -vendor: nordic diff --git a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840_defconfig b/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840_defconfig deleted file mode 100644 index 58f290ba271..00000000000 --- a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF9160DK_NRF52840=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf52840/revision.cmake b/boards/arm/nrf9160dk_nrf52840/revision.cmake deleted file mode 100644 index 585aae3dfdb..00000000000 --- a/boards/arm/nrf9160dk_nrf52840/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT MAJOR.MINOR.PATCH - DEFAULT_REVISION 0.14.0 - VALID_REVISIONS 0.7.0 0.14.0 -) diff --git a/boards/arm/nrf9160dk_nrf9160/CMakeLists.txt b/boards/arm/nrf9160dk_nrf9160/CMakeLists.txt deleted file mode 100644 index 75fa51e564c..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(nrf52840_reset.c) diff --git a/boards/arm/nrf9160dk_nrf9160/Kconfig.board b/boards/arm/nrf9160dk_nrf9160/Kconfig.board deleted file mode 100644 index 180d60b18d8..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9160 DK NRF9160 board configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_NRF9160DK_NRF9160 - bool "nRF9160 DK NRF9160" - -config BOARD_NRF9160DK_NRF9160_NS - bool "nRF9160 DK NRF9160 non-secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/nrf9160dk_nrf9160/Kconfig.defconfig b/boards/arm/nrf9160dk_nrf9160/Kconfig.defconfig deleted file mode 100644 index 7d9046f63b5..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# nRF9160 DK NRF9160 board configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS - -config BOARD - default "nrf9160dk_nrf9160" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_NRF9160DK_NRF9160 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9160DK_NRF9160_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9160DK_NRF9160_NS - -config BT_HCI_VS - default y if BT - -config BT_WAIT_NOP - default BT && $(dt_nodelabel_enabled,nrf52840_reset) - -config I2C - default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) - -endif # BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS diff --git a/boards/arm/nrf9160dk_nrf9160/board.cmake b/boards/arm/nrf9160dk_nrf9160/board.cmake deleted file mode 100644 index fb5779f2967..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/board.cmake +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_NRF9160DK_NRF9160_NS) - set(TFM_PUBLIC_KEY_FORMAT "full") -endif() - -if(CONFIG_TFM_FLASH_MERGED_BINARY) - set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) -endif() - -board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/nrf9160dk_nrf9160/doc/index.rst b/boards/arm/nrf9160dk_nrf9160/doc/index.rst deleted file mode 100644 index 8deb4848255..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/doc/index.rst +++ /dev/null @@ -1,264 +0,0 @@ -.. _nrf9160dk_nrf9160: - -nRF9160 DK -########## - -Overview -******** - -The nRF9160 DK (PCA10090) is a single-board development kit for evaluation and -development on the nRF9160 SiP for LTE-M and NB-IoT. The nrf9160dk_nrf9160 -board configuration provides support for the Nordic Semiconductor nRF9160 ARM -Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -.. figure:: img/nrf9160dk_nrf9160.jpg - :align: center - :alt: nRF9160 DK - - nRF9160 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the -`nRF9160 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF9160 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf9160dk_nrf9160 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -.. _nrf9160dk_additional_hardware: - -Additional hardware in v0.14.0+ -------------------------------- - -Starting from v0.14.0, additional hardware is available on the DK: - -* External flash memory (MX25R6435F, 64 Mb) -* I/O expander (PCAL6408A) that can be used to interface LEDs, slide switches, - and buttons - -To use this additional hardware, specify the revision of the board that -should be used when building your application (for more information, see -:ref:`application_board_version`). For example, to build for nRF9160 DK v1.0.0: - -.. zephyr-app-commands:: - :tool: all - :cd-into: - :board: nrf9160dk_nrf9160@1.0.0 - :goals: build - :compact: - -Remember to also enable routing for this additional hardware in the firmware for -:ref:`nrf9160dk_nrf52840` (see :ref:`nrf9160dk_board_controller_firmware`). - -Other hardware features have not been enabled yet for this board. -See `nRF9160 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF9160 DK board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.2 -* LED2 (green) = P0.3 -* LED3 (green) = P0.4 -* LED4 (green) = P0.5 - -Push buttons and Switches -------------------------- - -* BUTTON1 = P0.6 -* BUTTON2 = P0.7 -* SWITCH1 = P0.8 -* SWITCH2 = P0.9 -* BOOT = SW5 = boot/reset - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - - -Programming and Debugging -************************* - -nrf9160dk_nrf9160 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -Applications on the nRF9160 may contain a Secure and a Non-Secure firmware -image. The Secure image can be built using either Zephyr or -`Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built -using Zephyr. The two alternatives are described below. - -.. note:: - - By default the Secure image for nRF9160 is built using TF-M. - -Building the Secure firmware using Zephyr ------------------------------------------ - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9160dk_nrf9160`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9160dk_nrf9160_ns``. -3. Merge the two binaries together. - -Building the Secure firmware with TF-M --------------------------------------- - -The process to build the Secure firmware image using TF-M and the Non-Secure -firmware image using Zephyr requires the following action: - -1. Build the Non-Secure Zephyr application - using ``-DBOARD=nrf9160dk_nrf9160_ns``. - To invoke the building of TF-M the Zephyr build system requires the - Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by - default when building Zephyr as a Non-Secure application. - The Zephyr build system will perform the following steps automatically: - - * Build the Non-Secure firmware image as a regular Zephyr application - * Build a TF-M (secure) firmware image - * Merge the output binaries together - * Optionally build a bootloader image (MCUboot) - -.. note:: - - Depending on the TF-M configuration, an application DTS overlay may be - required, to adjust the Non-Secure image Flash and SRAM starting address - and sizes. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9160dk_nrf9160``. - - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9160 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9160dk_nrf9160 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF9160 DK -********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common.dtsi`. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _nRF9160 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9160-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml b/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml deleted file mode 100644 index 4b58b15317a..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# NOTE: This file is replicated in nrf9160dk_nrf9160 and nrf9160dk_nrf52840. -# Any changes should be done in both instances. - -description: | - nRF9160 DK GPIO interface between nRF9160 and nRF52840 - - This interface can be used for inter-SoC communication on the DK. - The connections are as follows: - - | nRF9160 | | nRF52840 | - | P0.17 | -- nRF interface line 0 -- | P0.17 | - | P0.18 | -- nRF interface line 1 -- | P0.20 | - | P0.19 | -- nRF interface line 2 -- | P0.15 | - | P0.21 | -- nRF interface line 3 -- | P0.22 | - | P0.22 | -- nRF interface line 4 -- | P1.04 | - | P0.23 | -- nRF interface line 5 -- | P1.02 | - | COEX0 | -- nRF interface line 6 -- | P1.13 | - | COEX1 | -- nRF interface line 7 -- | P1.11 | - | COEX2 | -- nRF interface line 8 -- | P1.15 | - | P0.24 | -- nRF interface line 9 -- | P0.18 (nRESET) | (in v0.14.0 or later) - - Before particular lines of this interface can be used, the corresponding - analog switches that control the routing of involved nRF9160 pins must be - configured to provide the optional routing (i.e. to nRF52840). To achieve - this, set the status of respective devicetree nodes in the firmware for - the nrf9160dk_nrf52840 board to "okay": - - `nrf_interface_pins_0_2_routing` to enable lines 0-2 - - `nrf_interface_pins_3_5_routing` to enable lines 3-5 - - `nrf_interface_pins_6_8_routing` to enable lines 6-8 - - `nrf_interface_pin_9_routing` to enable line 9 (this line is only - available in nRF9160 DK v0.14.0 or later) - - NOTE: In nRF9160 DK revisions earlier than v0.14.0, when the above signals - from nRF9160 are routed to nRF52840, they are not available on the DK - connectors. - -compatible: "nordic,nrf9160dk-nrf52840-interface" - -include: [gpio-nexus.yaml, base.yaml] diff --git a/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml b/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml deleted file mode 100644 index 1804fc51d4a..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# NOTE: This file is replicated in nrf9160dk_nrf9160 and nrf9160dk_nrf52840. -# Any changes should be done in both instances. - -description: GPIO used to reset nRF52840 on nRF9160 DK - -compatible: "nordic,nrf9160dk-nrf52840-reset" - -include: base.yaml - -properties: - status: - required: true - - gpios: - type: phandle-array - required: true - description: | - GPIO to use as nRF52840 reset line: output in nRF9160, input in nRF52840. diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160.yaml b/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160.yaml deleted file mode 100644 index 7a6d3362b23..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: nrf9160dk_nrf9160 -name: nRF9160-DK-NRF9160 -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 1024 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - gpio - - i2c - - pwm - - spi - - watchdog - - counter -vendor: nordic diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_defconfig b/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_defconfig deleted file mode 100644 index aa61cc4ca35..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160DK_NRF9160=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns.yaml b/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns.yaml deleted file mode 100644 index c2a98dcad05..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: nrf9160dk_nrf9160_ns -name: nRF9160-DK-NRF9160-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - i2c - - pwm - - watchdog - - netif:modem - - gpio -vendor: nordic diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns_defconfig b/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns_defconfig deleted file mode 100644 index 93343cc0264..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160DK_NRF9160_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf9160/revision.cmake b/boards/arm/nrf9160dk_nrf9160/revision.cmake deleted file mode 100644 index 585aae3dfdb..00000000000 --- a/boards/arm/nrf9160dk_nrf9160/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT MAJOR.MINOR.PATCH - DEFAULT_REVISION 0.14.0 - VALID_REVISIONS 0.7.0 0.14.0 -) diff --git a/boards/arm/nrf9161dk_nrf9161/Kconfig.board b/boards/arm/nrf9161dk_nrf9161/Kconfig.board deleted file mode 100644 index 15bcdb167b3..00000000000 --- a/boards/arm/nrf9161dk_nrf9161/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9161 DK NRF9161 board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9161_LACA - -config BOARD_NRF9161DK_NRF9161 - bool "nRF9161 DK NRF9161" - -config BOARD_NRF9161DK_NRF9161_NS - bool "nRF9161 DK NRF9161 non-secure" - -endif # SOC_NRF9161_LACA diff --git a/boards/arm/nrf9161dk_nrf9161/Kconfig.defconfig b/boards/arm/nrf9161dk_nrf9161/Kconfig.defconfig deleted file mode 100644 index ea7150ede5f..00000000000 --- a/boards/arm/nrf9161dk_nrf9161/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# nRF9161 DK NRF9161 board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9161DK_NRF9161 || BOARD_NRF9161DK_NRF9161_NS - -config BOARD - default "nrf9161dk_nrf9161" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_NRF9161DK_NRF9161 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9161DK_NRF9161_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9161DK_NRF9161_NS - -config BT_HCI_VS - default y if BT - -config BT_WAIT_NOP - default BT && $(dt_nodelabel_enabled,nrf5340_reset) - -config I2C - default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) - -endif # BOARD_NRF9161DK_NRF9161 || BOARD_NRF9161DK_NRF9161_NS diff --git a/boards/arm/nrf9161dk_nrf9161/doc/index.rst b/boards/arm/nrf9161dk_nrf9161/doc/index.rst deleted file mode 100644 index 18b214a7fde..00000000000 --- a/boards/arm/nrf9161dk_nrf9161/doc/index.rst +++ /dev/null @@ -1,203 +0,0 @@ -.. _nrf9161dk_nrf9161: - -nRF9161 DK -########## - -Overview -******** - -The nRF9161 DK (PCA10153) is a single-board development kit for evaluation and -development on the nRF9161 SiP for DECT NR+ and LTE-M/NB-IoT with GNSS. The nrf9161dk_nrf9161 -board configuration provides support for the Nordic Semiconductor nRF9161 ARM -Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -More information about the board can be found at the -`nRF9161 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF9161 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf9161dk_nrf9161 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| FLASH | external | spi | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GPIO | external | i2c | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | nRF53 | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - - -.. _nrf9161dk_additional_hardware: - -Other hardware features have not been enabled yet for this board. -See `nRF9161 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF9161 DK board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.0 -* LED2 (green) = P0.1 -* LED3 (green) = P0.4 -* LED4 (green) = P0.5 - -Push buttons and Switches -------------------------- - -* BUTTON1 = P0.8 -* BUTTON2 = P0.9 -* SWITCH1 = P0.18 -* SWITCH2 = P0.19 -* BOOT = SW5 = boot/reset - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - - -Programming and Debugging -************************* - -nrf9161dk_nrf9161 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9161dk_nrf9161`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9161dk_nrf9161_ns``. -3. Merge the two binaries together. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9161dk_nrf9161``. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9161 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9161dk_nrf9161 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF9161 DK -********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common.dtsi`. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _nRF9161 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9161-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161.yaml b/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161.yaml deleted file mode 100644 index af076428810..00000000000 --- a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: nrf9161dk_nrf9161 -name: nRF9161-DK-NRF9161 -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 1024 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - gpio - - i2c - - pwm - - spi - - watchdog - - counter -vendor: nordic diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_defconfig b/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_defconfig deleted file mode 100644 index 1e04a544d95..00000000000 --- a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9161_LACA=y -CONFIG_BOARD_NRF9161DK_NRF9161=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns.yaml b/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns.yaml deleted file mode 100644 index 2d2da2026f4..00000000000 --- a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: nrf9161dk_nrf9161_ns -name: nRF9161-DK-NRF9161-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - i2c - - pwm - - watchdog - - netif:modem -vendor: nordic diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns_defconfig b/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns_defconfig deleted file mode 100644 index 97649b3d4d8..00000000000 --- a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9161_LACA=y -CONFIG_BOARD_NRF9161DK_NRF9161_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9161dk_nrf9161/pre_dt_board.cmake b/boards/arm/nrf9161dk_nrf9161/pre_dt_board.cmake deleted file mode 100644 index c8267afd1b4..00000000000 --- a/boards/arm/nrf9161dk_nrf9161/pre_dt_board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - flash-controller@39000 & kmu@39000 -# - power@5000 & clock@5000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/nrf9161dk_nrf9161/revision.cmake b/boards/arm/nrf9161dk_nrf9161/revision.cmake deleted file mode 100644 index 2a899f61a83..00000000000 --- a/boards/arm/nrf9161dk_nrf9161/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT MAJOR.MINOR.PATCH - DEFAULT_REVISION 0.9.0 - VALID_REVISIONS 0.7.0 0.9.0 -) diff --git a/boards/arm/nucleo_c031c6/Kconfig.board b/boards/arm/nucleo_c031c6/Kconfig.board deleted file mode 100644 index 7cc97754755..00000000000 --- a/boards/arm/nucleo_c031c6/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32C031C6 MCU configuration - -# Copyright (c) 2023 Benjamin Björnsson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_C031C6 - bool "NUCLEO-64 C031C6 Development Board" - depends on SOC_STM32C031XX diff --git a/boards/arm/nucleo_c031c6/Kconfig.defconfig b/boards/arm/nucleo_c031c6/Kconfig.defconfig deleted file mode 100644 index acaa8c977eb..00000000000 --- a/boards/arm/nucleo_c031c6/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Nucleo-64 development board with STM32C031C6 MCU - -# Copyright (c) 2023 Benjamin Björnsson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_C031C6 - -config BOARD - default "nucleo_c031c6" - -endif # BOARD_NUCLEO_C031C6 diff --git a/boards/arm/nucleo_c031c6/doc/index.rst b/boards/arm/nucleo_c031c6/doc/index.rst deleted file mode 100644 index 3e28230cba2..00000000000 --- a/boards/arm/nucleo_c031c6/doc/index.rst +++ /dev/null @@ -1,151 +0,0 @@ -.. _nucleo_c031c6_board: - -ST Nucleo C031C6 -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32C031C6 MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_c031c6.jpg - :align: center - :alt: Nucleo C031C6 - -More information about the board can be found at the `Nucleo C031C6 website`_. - -Hardware -******** -Nucleo C031C6 provides the following hardware components: - -- STM32 microcontroller in 48-pin package featuring 32 Kbytes of Flash memory - and 12 Kbytes of SRAM. -- Extension resource: - - - Arduino* Uno V3 connectivity - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Current consumption measurement (IDD) - -- Four LEDs: - - - USB communication (LD1), USB power fault LED (LD2), power LED (LD3), - user LED (LD4) - -- Two push-button: USER and RESET - -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -More information about STM32C031C6 can be found here: -`STM32C0x1 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_c031c6 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| IWDG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| WWDG | on-chip | window watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_c031c6/nucleo_c031c6_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- LD4 : PA5 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_c031c6`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo C031C6 board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo C031C6 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_c031c6 - :goals: build flash - -You will see the LED blinking every second. - -References -********** - -.. target-notes:: - -.. _Nucleo C031C6 website: - https://www.st.com/en/evaluation-tools/nucleo-c031c6.html - -.. _STM32C0x1 reference manual: - https://www.st.com/resource/en/reference_manual/rm0490-stm32c0x1-advanced-armbased-64bit-mcus-stmicroelectronics.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/um2953-stm32c0-nucleo64-board-mb1717-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_c031c6/nucleo_c031c6_defconfig b/boards/arm/nucleo_c031c6/nucleo_c031c6_defconfig deleted file mode 100644 index c955a55e0e4..00000000000 --- a/boards/arm/nucleo_c031c6/nucleo_c031c6_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32C0X=y - -# Platform Configuration -CONFIG_SOC_STM32C031XX=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f030r8/Kconfig.board b/boards/arm/nucleo_f030r8/Kconfig.board deleted file mode 100644 index 39bd7c786d8..00000000000 --- a/boards/arm/nucleo_f030r8/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F030R8 MCU configuration - -# Copyright (c) 2017 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F030R8 - bool "NUCLEO-64 F030R8 Development Board" - depends on SOC_STM32F030X8 diff --git a/boards/arm/nucleo_f030r8/Kconfig.defconfig b/boards/arm/nucleo_f030r8/Kconfig.defconfig deleted file mode 100644 index 7b5331693fe..00000000000 --- a/boards/arm/nucleo_f030r8/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F030R8 MCU - -# Copyright (c) 2017 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F030R8 - -config BOARD - default "nucleo_f030r8" - -endif # BOARD_NUCLEO_F030R8 diff --git a/boards/arm/nucleo_f030r8/doc/index.rst b/boards/arm/nucleo_f030r8/doc/index.rst deleted file mode 100644 index a6f104398c7..00000000000 --- a/boards/arm/nucleo_f030r8/doc/index.rst +++ /dev/null @@ -1,217 +0,0 @@ -.. _nucleo_f030r8_board: - -ST Nucleo F030R8 -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32F030R8 MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f030r8.jpg - :align: center - :alt: Nucleo F030R8 - -More information about the board can be found at the `Nucleo F030R8 website`_. - -Hardware -******** -Nucleo F030R8 provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32F030R8 can be found here: - -- `STM32F030 reference manual`_ -- `STM32F030 data sheet`_ - -Supported Features -================== - -The Zephyr nucleo_f030r8 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f030r8/nucleo_f030r8_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_f030r8_connectors.jpg - :align: center - :alt: Nucleo F030R8 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PB10/PB11 -- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- USER_PB : PC13 -- LD1 : PA5 -- ADC : PA0 - - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f030r8`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. _nucleo-f030r8-flashing: - -Flashing -======== - -Nucleo F030R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F030R8 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f030r8 - :goals: build flash - -You will see the LED blinking every second. - -If using the C-01 board, select revision '1' that supports the board. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f030r8@1 - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f030r8 - :maybe-skip-config: - :goals: debug - -Again you have to use the adapted command for C-01. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f030r8@1 - :maybe-skip-config: - :goals: debug - -Board Revisions -*************** - -Nucleo F030R8 has some version of board variants. -`STM32 Nucleo-64 board User Manual`_ mentions to Nucleo board variants. - - | *The board version MB1136 C-01 or MB1136 C-02 is mentioned on the sticker, placed on the bottom side of the PCB.* - | *The board marking MB1136 C-01 corresponds to a board, configured as HSE not used.* - | *The board marking MB1136 C-02 (or higher) corresponds to a board, configured to use ST-LINK MCO as the clock input.* - -Using revision **2** adapted for C-02(or higher) as default when not explicitly selecting revisions. -If using the C-01 board, select revision **1**. -Please see :ref:`Flashing ` section. - -References -********** - -.. target-notes:: - -.. _Nucleo F030R8 website: - https://www.st.com/en/evaluation-tools/nucleo-f030r8.html - -.. _STM32F030 reference manual: - https://www.st.com/resource/en/reference_manual/dm00091010.pdf - -.. _STM32F030 data sheet: - https://www.st.com/resource/en/datasheet/stm32f030r8.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8_1.conf b/boards/arm/nucleo_f030r8/nucleo_f030r8_1.conf deleted file mode 100644 index 39cc277d78d..00000000000 --- a/boards/arm/nucleo_f030r8/nucleo_f030r8_1.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8_2.conf b/boards/arm/nucleo_f030r8/nucleo_f030r8_2.conf deleted file mode 100644 index 39cc277d78d..00000000000 --- a/boards/arm/nucleo_f030r8/nucleo_f030r8_2.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/nucleo_f030r8/revision.cmake b/boards/arm/nucleo_f030r8/revision.cmake deleted file mode 100644 index 7e5ddf37782..00000000000 --- a/boards/arm/nucleo_f030r8/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2022 TOKITA Hiroshi -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_check_revision(FORMAT NUMBER - DEFAULT_REVISION 2) diff --git a/boards/arm/nucleo_f031k6/Kconfig.board b/boards/arm/nucleo_f031k6/Kconfig.board deleted file mode 100644 index d0095535765..00000000000 --- a/boards/arm/nucleo_f031k6/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-32 development board with STM32F031K6 MCU configuration - -# Copyright (c) 2021 Sebastian Schwabe -# SPDX -License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F031K6 - bool "NUCLEO-32 F031K6 Development Board" - depends on SOC_STM32F031X6 diff --git a/boards/arm/nucleo_f031k6/Kconfig.defconfig b/boards/arm/nucleo_f031k6/Kconfig.defconfig deleted file mode 100644 index 6120548e9e2..00000000000 --- a/boards/arm/nucleo_f031k6/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Nucleo-32 development board with STM32F031K6 MCU - -# Copyright (c) 2021 Sebastian Schwabe -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F031K6 - -config BOARD - default "nucleo_f031k6" - -endif # BOARD_NUCLEO_F031K6 diff --git a/boards/arm/nucleo_f031k6/doc/index.rst b/boards/arm/nucleo_f031k6/doc/index.rst deleted file mode 100644 index ccfb1540f26..00000000000 --- a/boards/arm/nucleo_f031k6/doc/index.rst +++ /dev/null @@ -1,155 +0,0 @@ -.. _nucleo_f031k6_board: - -ST Nucleo F031K6 -################ - -Overview -******** -The STM32 Nucleo-32 development board with STM32F031K6 MCU, supports Arduino nano connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f031k6.jpg - :align: center - :alt: Nucleo F031k6 - -More information about the board can be found at the `Nucleo F031K6 website`_. - -Hardware -******** -Nucleo F031K6 provides the following hardware components: - -- STM32 microcontroller in LQFP32 package - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- reset push button - -More information about STM32F031K6 can be found here: - -- `STM32F031 reference manual`_ -- `STM32F031 data sheet`_ - -Supported Features -================== - -The Zephyr nucleo_f031k6 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f031k6/nucleo_f031k6_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. - -Board connectors: ------------------ -.. image:: img/nucleo_f031k6_connectors.jpg - :align: center - :alt: Nucleo F031K6 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA2/PA15 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB6/PB7 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) -- LD2 : PB3 - - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f031k6`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F030R8 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f031k6 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f031k6 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F031K6 website: - https://www.st.com/en/evaluation-tools/nucleo-f031k6.html - -.. _STM32F031 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32F031 data sheet: - https://www.st.com/resource/en/datasheet/stm32f031k6.pdf - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_f042k6/Kconfig.board b/boards/arm/nucleo_f042k6/Kconfig.board deleted file mode 100644 index e9663d72e0a..00000000000 --- a/boards/arm/nucleo_f042k6/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# STM32 Nucleo-32 development board with STM32F031K6 MCU configuration - -# Copyright (c) 2023 STMicroelectronics - -# SPDX -License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F042K6 - bool "NUCLEO-32 F042K6 Development Board" - depends on SOC_STM32F042X6 diff --git a/boards/arm/nucleo_f042k6/Kconfig.defconfig b/boards/arm/nucleo_f042k6/Kconfig.defconfig deleted file mode 100644 index dab2333ef37..00000000000 --- a/boards/arm/nucleo_f042k6/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# STM32 Nucleo-32 development board with STM32F042K6 MCU - -# Copyright (c) 2023 STMicroelectronics - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F042K6 - -config BOARD - default "nucleo_f042k6" - -endif # BOARD_NUCLEO_F042K6 diff --git a/boards/arm/nucleo_f042k6/doc/index.rst b/boards/arm/nucleo_f042k6/doc/index.rst deleted file mode 100644 index 66ad80adeed..00000000000 --- a/boards/arm/nucleo_f042k6/doc/index.rst +++ /dev/null @@ -1,155 +0,0 @@ -.. _nucleo_f042k6_board: - -ST Nucleo F042K6 -################ - -Overview -******** -The STM32 Nucleo-32 development board with STM32F042K6 MCU, supports Arduino nano connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f042k6.jpg - :align: center - :alt: Nucleo F042k6 - -More information about the board can be found at the `Nucleo F042K6 website`_. - -Hardware -******** -Nucleo F042K6 provides the following hardware components: - -- STM32 microcontroller in LQFP32 package - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- reset push button - -More information about STM32F042K6 can be found here: - -- `STM32F042 reference manual`_ -- `STM32F042 data sheet`_ - -Supported Features -================== - -The Zephyr nucleo_f042k6 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f042k6/nucleo_f042k6_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. - -Board connectors: ------------------ -.. image:: img/nucleo_f042k6_connectors.jpg - :align: center - :alt: Nucleo F042K6 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA2/PA15 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB6/PB7 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) -- LD2 : PB3 - - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f042k6`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F042K6 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F042K6 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f042k6 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f042k6 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F042K6 website: - https://www.st.com/en/evaluation-tools/nucleo-f042k6.html - -.. _STM32F042 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32F042 data sheet: - https://www.st.com/resource/en/datasheet/stm32f042k6.pdf - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_f042k6/nucleo_f042k6_defconfig b/boards/arm/nucleo_f042k6/nucleo_f042k6_defconfig deleted file mode 100644 index 0f69a1be64c..00000000000 --- a/boards/arm/nucleo_f042k6/nucleo_f042k6_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F042X6=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f070rb/Kconfig.board b/boards/arm/nucleo_f070rb/Kconfig.board deleted file mode 100644 index 2745ba2a20c..00000000000 --- a/boards/arm/nucleo_f070rb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO_F070RB board configuration - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F070RB - bool "NUCLEO-64 F070RB Development Board" - depends on SOC_STM32F070XB diff --git a/boards/arm/nucleo_f070rb/Kconfig.defconfig b/boards/arm/nucleo_f070rb/Kconfig.defconfig deleted file mode 100644 index 970df859b36..00000000000 --- a/boards/arm/nucleo_f070rb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# NUCLEO_F070RB board configuration - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F070RB - -config BOARD - default "nucleo_f070rb" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F070RB diff --git a/boards/arm/nucleo_f070rb/doc/index.rst b/boards/arm/nucleo_f070rb/doc/index.rst deleted file mode 100644 index 50a96e3fed4..00000000000 --- a/boards/arm/nucleo_f070rb/doc/index.rst +++ /dev/null @@ -1,180 +0,0 @@ -.. _nucleo_f070rb_board: - -ST Nucleo F070RB -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32F070RB MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f070rb.jpg - :align: center - :alt: Nucleo F070RB - -More information about the board can be found at the `Nucleo F070RB website`_. - -Hardware -******** -Nucleo F070RB provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32F070RB can be found in -the `STM32F070 reference manual`_ . - - -Supported Features -================== - -The Zephyr nucleo_f070rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | SPI controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_f070rb_connectors.jpg - :align: center - :alt: Nucleo F070RB connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PB10/PB11 -- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 -- USER_PB : PC13 -- LD1 : PA5 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f070rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F070RB board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F070RB ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f070rb - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f070rb - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F070RB website: - https://www.st.com/en/evaluation-tools/nucleo-f070rb.html - -.. _STM32F070 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig b/boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig deleted file mode 100644 index 088920775b4..00000000000 --- a/boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F070XB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f091rc/Kconfig.board b/boards/arm/nucleo_f091rc/Kconfig.board deleted file mode 100644 index d109e7c4898..00000000000 --- a/boards/arm/nucleo_f091rc/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F091RC MCU configuration - -# Copyright (c) 2017 Bobby Noelte -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F091RC - bool "NUCLEO-64 F091RC Development Board" - depends on SOC_STM32F091XC diff --git a/boards/arm/nucleo_f091rc/Kconfig.defconfig b/boards/arm/nucleo_f091rc/Kconfig.defconfig deleted file mode 100644 index bd4fedf1b5a..00000000000 --- a/boards/arm/nucleo_f091rc/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F091RC MCU - -# Copyright (c) 2017 Bobby Noelte -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F091RC - -config BOARD - default "nucleo_f091rc" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F091RC diff --git a/boards/arm/nucleo_f091rc/doc/index.rst b/boards/arm/nucleo_f091rc/doc/index.rst deleted file mode 100644 index 9ff09e28770..00000000000 --- a/boards/arm/nucleo_f091rc/doc/index.rst +++ /dev/null @@ -1,197 +0,0 @@ -.. _nucleo_f091rc_board: - -ST Nucleo F091RC -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32F091RC MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f091rc.jpg - :align: center - :alt: Nucleo F091RC - -More information about the board can be found at the `Nucleo F091RC website`_. - -Hardware -******** -Nucleo F091RC provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32F091RC can be found in the -`STM32F091 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_f091rc board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | SPI controller | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC controller | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC controller | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f091rc/nucleo_f091rc_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_f091rc_connectors.jpg - :align: center - :alt: Nucleo F091RC connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PA11/PA12 (disabled by default, uses same pins as CAN) -- CAN RX/TX : PA11/PA12 -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) -- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 -- USER_PB : PC13 -- LD2 : PA5 -- DAC_OUT1 : PA4 -- PWM_2_CH1 : PA5 (might conflict with SPI1) - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f091rc`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F091RC board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F091RC ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f091rc - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f091rc - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F091RC website: - https://www.st.com/en/evaluation-tools/nucleo-f091rc.html - -.. _STM32F091 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f091rc/nucleo_f091rc_defconfig b/boards/arm/nucleo_f091rc/nucleo_f091rc_defconfig deleted file mode 100644 index c166772f8e3..00000000000 --- a/boards/arm/nucleo_f091rc/nucleo_f091rc_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F091XC=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f103rb/Kconfig.board b/boards/arm/nucleo_f103rb/Kconfig.board deleted file mode 100644 index e175a30e368..00000000000 --- a/boards/arm/nucleo_f103rb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-64 F103RB board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F103RB - bool "NUCLEO-64 F103RB Development Board" - depends on SOC_STM32F103XB diff --git a/boards/arm/nucleo_f103rb/Kconfig.defconfig b/boards/arm/nucleo_f103rb/Kconfig.defconfig deleted file mode 100644 index 3d4c0581a96..00000000000 --- a/boards/arm/nucleo_f103rb/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# NUCLEO-64 F103RB board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F103RB - -config BOARD - default "nucleo_f103rb" - -endif # BOARD_NUCLEO_F103RB diff --git a/boards/arm/nucleo_f103rb/doc/index.rst b/boards/arm/nucleo_f103rb/doc/index.rst deleted file mode 100644 index 8f67b04ad62..00000000000 --- a/boards/arm/nucleo_f103rb/doc/index.rst +++ /dev/null @@ -1,190 +0,0 @@ -.. _nucleo_f103rb_board: - -ST Nucleo F103RB -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32F103RB MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f103rb.jpg - :align: center - :alt: Nucleo F103RB - -More information about the board can be found at the `Nucleo F103RB website`_. - -Hardware -******** -Nucleo F103RB provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32F103RB can be found here: - -- `STM32F103 reference manual`_ -- `STM32F103 data sheet`_ - -Supported Features -================== - -The Zephyr nucleo_f103rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_f103rb_connectors.jpg - :align: center - :alt: Nucleo F103RB connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) -- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- SPI2 SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- I2C1 SDA/SCL: PB9/PB8 (Arduino I2C) -- PWM1_CH1: PA8 -- USER_PB : PC13 -- LD1 : PA5 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f103rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F103RB board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F103RB ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f103rb - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f103rb - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F103RB website: - https://www.st.com/en/evaluation-tools/nucleo-f103rb.html - -.. _STM32F103 reference manual: - https://www.st.com/resource/en/reference_manual/cd00171190.pdf - -.. _STM32F103 data sheet: - https://www.st.com/resource/en/datasheet/stm32f103rb.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f207zg/Kconfig.board b/boards/arm/nucleo_f207zg/Kconfig.board deleted file mode 100644 index b3054d4ae34..00000000000 --- a/boards/arm/nucleo_f207zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-144 F207ZG board configuration - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F207ZG - bool "NUCLEO-144 F207ZG Development Board" - depends on SOC_STM32F207XX diff --git a/boards/arm/nucleo_f207zg/Kconfig.defconfig b/boards/arm/nucleo_f207zg/Kconfig.defconfig deleted file mode 100644 index b3b48232483..00000000000 --- a/boards/arm/nucleo_f207zg/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# NUCLEO-144 F207ZG board configuration - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F207ZG - -config BOARD - default "nucleo_f207zg" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F207ZG diff --git a/boards/arm/nucleo_f207zg/doc/index.rst b/boards/arm/nucleo_f207zg/doc/index.rst deleted file mode 100644 index e9696365b1c..00000000000 --- a/boards/arm/nucleo_f207zg/doc/index.rst +++ /dev/null @@ -1,206 +0,0 @@ -.. _nucleo_f207zg_board: - -ST Nucleo F207ZG -################ - -Overview -******** - -The Nucleo F207ZG board features an ARM Cortex-M3 based STM32F207ZG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F207ZG board: - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 -- Two types of extension resources: - - - ST Zio connector including: support for Arduino* Uno V3 connectivity - (A0 to A5, D0 to D15) and additional signals exposing a wide range of - peripherals - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- Three user LEDs -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f207zg.jpg - :align: center - :alt: Nucleo F207ZG - -More information about the board can be found at the `Nucleo F207ZG website`_. - -Hardware -******** - -Nucleo F207ZG provides the following hardware components: - -- STM32F207ZGT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M3 CPU -- 120 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1 MB Flash -- 128 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 24 channels -- RTC -- 17 General purpose timers -- 2 watchdog timers (independent and window) -- SysTick timer -- USART/UART (6) -- I2C (3) -- SPI (3) -- SDIO -- USB 2.0 OTG FS -- DMA Controller -- 10/100 Ethernet MAC with dedicated DMA -- CRC calculation unit -- True random number generator - -More information about STM32F207ZG can be found here: - -- `STM32F207ZG on www.st.com`_ -- `STM32F207 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_207zg board configuration supports the following hardware features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| ETHERNET | on-chip | Ethernet | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-------------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | PWM | -+-------------+------------+-------------------------------------+ -| RNG | on-chip | Random Number Generator | -+-------------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-------------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f207zg/nucleo_f207zg_defconfig`` - - -Connections and IOs -=================== - -Nucleo F207ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f207zg_zio_left.jpg - :align: center - :alt: Nucleo F207ZG ZIO connectors (left) -.. image:: img/nucleo_f207zg_zio_right.jpg - :align: center - :alt: Nucleo F207ZG ZIO connectors (right) -.. image:: img/nucleo_f207zg_morpho_left.jpg - :align: center - :alt: Nucleo F207ZG Morpho connectors (left) -.. image:: img/nucleo_f207zg_morpho_right.jpg - :align: center - :alt: Nucleo F207ZG Morpho connectors (right) - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- USB_DM : PA11 -- USB_DP : PA12 -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- DAC: PA4 -- ADC: PA0 -- PWM_1_CH1 : PE9 - -System Clock ------------- - -Nucleo F207ZG System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 120MHz, -driven by 8MHz high speed external clock. - -Serial Port ------------ - -Nucleo F207ZG board has 4 UARTs. The Zephyr console output is assigned to UART3. -Default settings are 115200 8N1. - -Network interface ------------------ - -Ethernet configured as the default network interface - -USB ---- -Nucleo F207ZG board has a USB OTG dual-role device (DRD) controller that -supports both device and host functions through its micro USB connector -(USB USER). Only USB device function is supported in Zephyr at the moment. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB156`` jumper on the back side of the board. - -Programming and Debugging -************************* - -Nucleo F207ZG board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F207ZG website: - https://www.st.com/en/evaluation-tools/nucleo-f207zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32F207ZG on www.st.com: - https://www.st.com/en/microcontrollers/stm32f207zg.html - -.. _STM32F207 reference manual: - https://www.st.com/resource/en/reference_manual/cd00225773.pdf diff --git a/boards/arm/nucleo_f302r8/Kconfig.board b/boards/arm/nucleo_f302r8/Kconfig.board deleted file mode 100644 index cc238c11040..00000000000 --- a/boards/arm/nucleo_f302r8/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-64 F302R8 board configuration - -# Copyright (c) 2018 Seitz & Associates -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F302R8 - bool "NUCLEO-64 F302R8 Development Board" - depends on SOC_STM32F302X8 diff --git a/boards/arm/nucleo_f302r8/Kconfig.defconfig b/boards/arm/nucleo_f302r8/Kconfig.defconfig deleted file mode 100644 index abf1484c1b6..00000000000 --- a/boards/arm/nucleo_f302r8/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# NUCLEO-64 F302R8 board configuration - -# Copyright (c) 2018 Seitz & Associates -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F302R8 - -config BOARD - default "nucleo_f302r8" - -endif # BOARD_NUCLEO_F302R8 diff --git a/boards/arm/nucleo_f302r8/doc/index.rst b/boards/arm/nucleo_f302r8/doc/index.rst deleted file mode 100644 index e554549a6fe..00000000000 --- a/boards/arm/nucleo_f302r8/doc/index.rst +++ /dev/null @@ -1,168 +0,0 @@ -.. _nucleo_f302r8_board: - -ST Nucleo F302R8 -################ - -Overview -******** - -The Nucleo F302R8 board features an ARM Cortex-M4 based STM32F302R8 -mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. -Here are some highlights of the Nucleo F302R8 board: - -- STM32 microcontroller in LQFP64 package -- LSE crystal: 32.768 kHz crystal oscillator -- Two types of extension resources: - - - Arduino* Uno V3 connectors - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- One user LED -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f302r8.jpg - :align: center - :alt: Nucleo F302R8 - -More information about the board can be found at the `Nucleo F302R8 website`_, -and in the `STM32 Nucleo-64 board User Manual`_. - -Hardware -******** - -The Nucleo F302R8 provides the following hardware components: - -- STM32F302R8T6 in QFP64 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 72 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 64 MB Flash -- 16 KB SRAM -- RTC -- Advanced-control Timer -- General Purpose Timers (4) -- Basic Timer -- Watchdog Timers (2) -- PWM channels (18) -- SPI/I2S (2) -- I2C (3) -- USART/UART (3/3) -- USB 2.0 FS with on-chip PHY -- CAN (2) -- GPIO with external interrupt capability -- DMA channels (7) -- Capacitive sensing channels (18) -- 12-bit ADC with 15 channels -- 12-bit D/A converter -- Analog comparator (3) -- Op amp - - -More information about the STM32F302R8 can be found here: - -- `STM32F302R8 on www.st.com`_ -- `STM32F302R8 reference manual`_ -- `STM32F302R8 datasheet`_ - -Supported Features -================== - -The Zephyr nucleo_f302r8 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f302r8/nucleo_f302r8_defconfig`` - -Connections and IOs -=================== - -The Nucleo F302R8 Board has 5 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -Board connectors: ------------------ -.. image:: img/nucleo_f302r8_connectors.jpg - :align: center - :alt: Nucleo F302R8 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F302R8 board features an Arduino Uno V3 connector and a ST -morpho connector. Board is configured as follows: - -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- UART_3 TX/RX : PC10/PC11 -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI2 CS/SCK/MISO/MOSI : PB6/PB13/PB14/P15 (Arduino SPI) -- PWM_2_CH2 : PA0 -- USER_PB : PC13 -- LD2 : PB13 - -System Clock ------------- - -The Nucleo F302R8 System Clock can be driven by an internal or -external oscillator, as well as by the main PLL clock. By default the -System Clock is driven by the PLL clock at 72 MHz. The input to the -PLL is an 8 MHz external clock supplied by the processor of the -on-board ST-LINK/V2-1 debugger/programmer. - -Serial Port ------------ - -The Nucleo F302R8 board has 3 UARTs. The Zephyr console output is assigned -to UART2. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -The Nucleo F302R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F302R8 website: - https://www.st.com/en/evaluation-tools/nucleo-f302r8.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F302R8 on www.st.com: - https://www.st.com/en/microcontrollers/stm32f302r8.html - -.. _STM32F302R8 reference manual: - https://www.st.com/resource/en/reference_manual/dm00094349.pdf - -.. _STM32F302R8 datasheet: - https://www.st.com/resource/en/datasheet/stm32f302r8.pdf diff --git a/boards/arm/nucleo_f303k8/Kconfig.board b/boards/arm/nucleo_f303k8/Kconfig.board deleted file mode 100644 index 88b26aab9a3..00000000000 --- a/boards/arm/nucleo_f303k8/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# NUCLEO-32 F303k8 board configuration - -# Copyright (c) 2020 Sebastian Schwabe -# Fabian Paschke -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F303K8 - bool "NUCLEO-32 F303K8 Development Board" - depends on SOC_STM32F303X8 diff --git a/boards/arm/nucleo_f303k8/Kconfig.defconfig b/boards/arm/nucleo_f303k8/Kconfig.defconfig deleted file mode 100644 index c52e0887f31..00000000000 --- a/boards/arm/nucleo_f303k8/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# NUCLEO-32 F303k8 board configuration - -# Copyright (c) 2020 Sebastian Schwabe -# Fabian Paschke -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F303K8 - -config BOARD - default "nucleo_f303k8" - -endif # BOARD_NUCLEO_F303K8 diff --git a/boards/arm/nucleo_f303k8/doc/index.rst b/boards/arm/nucleo_f303k8/doc/index.rst deleted file mode 100644 index 5aab3540663..00000000000 --- a/boards/arm/nucleo_f303k8/doc/index.rst +++ /dev/null @@ -1,159 +0,0 @@ -.. _nucleo_f303k8_board: - -ST Nucleo F303K8 -################ - -Overview -******** - -The Nucleo F303K8 board features an ARM Cortex-M4 based STM32F303K8 -mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. -Here are some highlights of the Nucleo F303K8 board: - -- STM32 microcontroller in LQFP32 package -- one type of extension resources: - -- Arduino™ Nano V3 connectivity support - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - -- 5 V from ST-LINK/V2-1 USB VBUS -- External power sources: 3.3 V, 5V and 7 - 12 V - -- One user LED -- One push-buttons: RESET - -.. image:: img/nucleo_f303k8.jpg - :align: center - :alt: Nucleo F303K8 - -More information about the board can be found at the `Nucleo F303K8 website`_, -and in the `STM32 Nucleo-32 board User Manual`_. - -Hardware -******** - -The Nucleo F303K8 provides the following hardware components: - -- STM32F303K8T6 in LQFP32 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 72 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 64 MB Flash -- 12 KB SRAM -- RTC -- Advanced-control Timer -- General Purpose Timers (5) -- Basic Timer (2) -- Watchdog Timers (2) -- PWM channels (12) -- SPI/I2S (1) -- I2C (1) -- USART/UART (2) -- CAN (1) -- GPIO with external interrupt capability -- DMA channels (7) -- Capacitive sensing channels (18) -- 12-bit ADC with 21 channels -- 12-bit D/A converter -- Analog comparator (3) -- Op amp - - -More information about the STM32F303K8 can be found here: - -- `STM32F303K8 on www.st.com`_ -- `STM32F303K8 reference manual`_ -- `STM32F303K8 datasheet`_ - -Supported Features -================== - -The Zephyr nucleo_f303k8 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f303k8/nucleo_f303k8_defconfig`` - -Connections and IOs -=================== - -The Nucleo F303K8 Board has 1 GPIO controller. This controllers is responsible -for input/output, pull-up, etc. - -Board connectors: ------------------ -.. image:: img/nucleo_f303k8_pinout.jpg - :align: center - :alt: Nucleo F303K8 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F303K8 board features an Arduino Zero V3 connector. Board is configured as follows: - -- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB7/PB6 -- SPI1 CS/SCK/MISO/MOSI : PA_4/PA_5/PB_4/PA_7 -- LD2 : PB3 - -System Clock ------------- - -The Nucleo F303K8 System Clock can be driven by an internal or -external oscillator, as well as by the main PLL clock. By default the -System Clock is driven by the PLL clock at 72 MHz. The input to the -PLL is an 8 MHz internal clock supply. - -Serial Port ------------ - -The Nucleo F303K8 board has 2 UARTs. The Zephyr console output is assigned -to UART2. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -The Nucleo F303K8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F303K8 website: - https://www.st.com/en/evaluation-tools/nucleo-F303K8.html - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf - -.. _STM32F303K8 on www.st.com: - https://www.st.com/en/microcontrollers/stm32F303K8.html - -.. _STM32F303K8 reference manual: - https://www.st.com/resource/en/reference_manual/dm00043574-stm32f303xbcde-stm32f303x68-stm32f328x8-stm32f358xc-stm32f398xe-advanced-armbased-mcus-stmicroelectronics.pdf - -.. _STM32F303K8 datasheet: - https://www.st.com/resource/en/datasheet/stm32f303k8.pdf diff --git a/boards/arm/nucleo_f303re/Kconfig.board b/boards/arm/nucleo_f303re/Kconfig.board deleted file mode 100644 index 0b9bc11bf96..00000000000 --- a/boards/arm/nucleo_f303re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-64 F303RE board configuration - -# Copyright (c) 2020 Paul M. Bendixen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F303RE - bool "NUCLEO-64 F303RE Development Board" - depends on SOC_STM32F303XE diff --git a/boards/arm/nucleo_f303re/Kconfig.defconfig b/boards/arm/nucleo_f303re/Kconfig.defconfig deleted file mode 100644 index 97aa8100d72..00000000000 --- a/boards/arm/nucleo_f303re/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# NUCLEO-64 F302R8 board configuration - -# Copyright (c) 2020 Paul M. Bendixen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F303RE - -config BOARD - default "nucleo_f303re" - -endif # BOARD_NUCLEO_F303RE diff --git a/boards/arm/nucleo_f303re/doc/index.rst b/boards/arm/nucleo_f303re/doc/index.rst deleted file mode 100644 index 387a2bc28d2..00000000000 --- a/boards/arm/nucleo_f303re/doc/index.rst +++ /dev/null @@ -1,162 +0,0 @@ -.. _nucleo_f303re_board: - -ST Nucleo F303RE -################ - -Overview -******** - -The Nucleo F303RE board features an ARM Cortex-M4 based STM32F303RE -mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. -Here are some highlights of the Nucleo F303RE board: - -- STM32 microcontroller in LQFP64 package -- LSE crystal: 32.768 kHz crystal oscillator -- Two types of extension resources: - - - Arduino* Uno V3 connectors - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- One user LED -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f303re.jpg - :align: center - :alt: Nucleo F303RE - -More information about the board can be found at the `Nucleo F303RE website`_, -and in the `STM32 Nucleo-64 board User Manual`_. - -Hardware -******** - -The Nucleo F303RE provides the following hardware components: - -- STM32F303RET6 in QFP64 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 72 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 512 MB Flash -- 64 + 16 KB SRAM -- RTC -- Advanced-control Timer -- General Purpose Timers (4) -- Basic Timer -- Watchdog Timers (2) -- PWM channels (18) -- SPI/I2S (2) -- I2C (3) -- USART/UART (3/3) -- USB 2.0 FS with on-chip PHY -- CAN (2) -- GPIO with external interrupt capability -- DMA channels (12) -- Capacitive sensing channels (18) -- 12-bit ADC with 40 channels (4) -- 12-bit D/A converter with two channels -- Analog comparator (7) -- Op amp (4) -- Capacitive sensing 24 channels - - -More information about the STM32F303RE can be found here: - -- `STM32F303RE on www.st.com`_ -- `STM32F303RE reference manual`_ -- `STM32F303RE datasheet`_ - -Supported Features -================== - -The Zephyr nucleo_f303re board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f303re/nucleo_f303re_defconfig`` - -Connections and IOs -=================== - -The Nucleo F303RE Board has 5 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -Board connectors: ------------------ -.. image:: img/nucleo_connectors.jpg - :align: center - :alt: Nucleo F303RE connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F303RE board features an Arduino Uno V3 connector and a ST -morpho connector. Board is configured as follows: - -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD2 : PA5 - -System Clock ------------- - -The Nucleo F303RE System Clock can be driven by an internal or -external oscillator, as well as by the main PLL clock. By default the -System Clock is driven by the PLL clock at 72 MHz. The input to the -PLL is an 8 MHz external clock supplied by the processor of the -on-board ST-LINK/V2-1 debugger/programmer. - -Serial Port ------------ - -The Nucleo F303RE board has 2 UARTs. The Zephyr console output is assigned -to UART2. Default settings are 115200 8N1. - -Programming and Debugging -************************* - -The Nucleo F303RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F303RE website: - https://www.st.com/en/evaluation-tools/nucleo-f303re.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F303RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f303re.html - -.. _STM32F303RE reference manual: - https://www.st.com/resource/en/reference_manual/dm00043574.pdf - -.. _STM32F303RE datasheet: - https://www.st.com/resource/en/datasheet/stm32f303re.pdf diff --git a/boards/arm/nucleo_f334r8/Kconfig.board b/boards/arm/nucleo_f334r8/Kconfig.board deleted file mode 100644 index 2c2e312c837..00000000000 --- a/boards/arm/nucleo_f334r8/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F334R8 MCU configuration - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F334R8 - bool "NUCLEO-64 F334R8 Development Board" - depends on SOC_STM32F334X8 diff --git a/boards/arm/nucleo_f334r8/Kconfig.defconfig b/boards/arm/nucleo_f334r8/Kconfig.defconfig deleted file mode 100644 index ad4f0b8979f..00000000000 --- a/boards/arm/nucleo_f334r8/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F334R8 MCU - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F334R8 - -config BOARD - default "nucleo_f334r8" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F334R8 diff --git a/boards/arm/nucleo_f334r8/doc/index.rst b/boards/arm/nucleo_f334r8/doc/index.rst deleted file mode 100644 index 64824e787eb..00000000000 --- a/boards/arm/nucleo_f334r8/doc/index.rst +++ /dev/null @@ -1,179 +0,0 @@ -.. _nucleo_f334r8_board: - -ST Nucleo F334R8 -################ - -Overview -******** -STM32 Nucleo-64 development board with STM32F334R8 MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board does not require any separate probe as it integrates the ST-LINK/V2-1 -debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f334r8.jpg - :align: center - :alt: Nucleo F334R8 - -More information about the board can be found at the `Nucleo F334R8 website`_. - -Hardware -******** -Nucleo F334R8 provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32F334R8 can be found in the -`STM32F334 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_f334r8 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_f334r8_connectors.jpg - :align: center - :alt: Nucleo F334R8 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- UART_3 TX/RX : PB10/PB11 -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- PWM_1_CH1 : PA8 -- USER_PB : PC13 -- LD2 : PA5 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f334r8`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F334R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to Nucleo F334R8 ----------------------------------------- - -Connect the Nucleo F334R8 to your host computer using the USB port, -then build and flash an application. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f334r8 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for -the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f334r8 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F334R8 website: - https://www.st.com/en/evaluation-tools/nucleo-f334r8.html - -.. _STM32F334 reference manual: - https://www.st.com/resource/en/reference_manual/dm00093941.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig b/boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig deleted file mode 100644 index a7a22c2096d..00000000000 --- a/boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F3X=y - -# Platform Configuration -CONFIG_SOC_STM32F334X8=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable clock -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f401re/Kconfig.board b/boards/arm/nucleo_f401re/Kconfig.board deleted file mode 100644 index 21b9b7451a3..00000000000 --- a/boards/arm/nucleo_f401re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-64 F401RE board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F401RE - bool "NUCLEO-64 F401RE Development Board" - depends on SOC_STM32F401XE diff --git a/boards/arm/nucleo_f401re/Kconfig.defconfig b/boards/arm/nucleo_f401re/Kconfig.defconfig deleted file mode 100644 index a634aca6a73..00000000000 --- a/boards/arm/nucleo_f401re/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# NUCLEO-64 F401RE board configuration - -# Copyright (c) 2016 Linaro Limited. -# Copyright (c) 2019 Centaur Analytics, Inc -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F401RE - -config BOARD - default "nucleo_f401re" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F401RE diff --git a/boards/arm/nucleo_f401re/doc/index.rst b/boards/arm/nucleo_f401re/doc/index.rst deleted file mode 100644 index aa01b1ad3ad..00000000000 --- a/boards/arm/nucleo_f401re/doc/index.rst +++ /dev/null @@ -1,206 +0,0 @@ -.. _nucleo_f401re_board: - -ST Nucleo F401RE -################ - -Overview -******** - -The Nucleo F401RE board features an ARM Cortex-M4 based STM32F401RE MCU -with a wide range of connectivity support and configurations Here are -some highlights of the Nucleo F401RE board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f401re.jpg - :align: center - :alt: Nucleo F401RE - -More information about the board can be found at the `Nucleo F401RE website`_. - -Hardware -******** - -Nucleo F401RE provides the following hardware components: - -- STM32F401RET6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 84 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 96 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 16 channels -- RTC -- Advanced-control Timer -- General Purpose Timers (7) -- Watchdog Timers (2) -- USART/UART (3) -- I2C (3) -- SPI (4) -- SDIO -- USB 2.0 OTG FS -- DMA Controller - -More information about STM32F401RE can be found here: - -- `STM32F401RE on www.st.com`_ -- `STM32F401 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_401re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | System Window Watchdog | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f401re/nucleo_f401re_defconfig`` - - -Pin Mapping -=========== - -Nucleo F401RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f401re_arduino.jpg - :align: center - :alt: Nucleo F401RE Arduino connectors -.. image:: img/nucleo_f401re_morpho.jpg - :align: center - :alt: Nucleo F401RE Morpho connectors - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD2 : PA5 - -System Clock -============ - -Nucleo F401RE System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 84MHz, -driven by 8MHz high speed external clock. - -Serial Port -=========== - -Nucleo F401RE board has 3 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - -I2C -=== - -Nucleo F401RE board has up to 3 I2Cs. The default I2C mapping for Zephyr is: - -- I2C1_SCL : PB8 -- I2C1_SDA : PB9 - -Programming and Debugging -************************* - -Applications for the ``nucleo_f401re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F401RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to Nucleo F401RE ----------------------------------------- - -Connect the Nucleo F401RE to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f401re - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f401re - :maybe-skip-config: - :goals: debug - -.. _Nucleo F401RE website: - https://www.st.com/en/evaluation-tools/nucleo-f401re.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F401RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f401re.html - -.. _STM32F401 reference manual: - https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/nucleo_f410rb/Kconfig.board b/boards/arm/nucleo_f410rb/Kconfig.board deleted file mode 100644 index 8dcfa890169..00000000000 --- a/boards/arm/nucleo_f410rb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F410RB Nucleo board configuration - -# Copyright (c) 2020 Hans Unzner -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F410RB - bool "Nucleo F410RB Development Board" - depends on SOC_STM32F410RX diff --git a/boards/arm/nucleo_f410rb/Kconfig.defconfig b/boards/arm/nucleo_f410rb/Kconfig.defconfig deleted file mode 100644 index df64f4ca9d3..00000000000 --- a/boards/arm/nucleo_f410rb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32F410RB Nucleo board configuration - -# Copyright (c) 2020 Hans Unzner -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F410RB - -config BOARD - default "nucleo_f410rb" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F410RB diff --git a/boards/arm/nucleo_f410rb/doc/index.rst b/boards/arm/nucleo_f410rb/doc/index.rst deleted file mode 100644 index 23c979e49aa..00000000000 --- a/boards/arm/nucleo_f410rb/doc/index.rst +++ /dev/null @@ -1,212 +0,0 @@ -.. _nucleo_f410rb_board: - -ST Nucleo F410RB -################ - -Overview -******** - -The Nucleo F410RB board features an ARM Cortex-M4 based STM32F410RB MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F410RB board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f410rb.jpg - :align: center - :alt: Nucleo F410RB - -More information about the board can be found at the `Nucleo F410RB website`_. - -Hardware -******** - -Nucleo F410RB provides the following hardware components: - -- STM32F410RBT6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- Adaptive real-time accelerator (ART Accelerator) -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 128 KB Flash -- 32 KB SRAM -- General purpose timer (4) -- Low-power timer (1) -- Advanced-control timer (1) -- Random number generator (TRNG for HW entropy) -- SPI/I2S (3) -- I2C (3) -- USART (3) -- GPIO (50) with external interrupt capability -- 12-bit ADC with 16 channels -- 12-bit DAC with 1 channel -- RTC - - -More information about STM32F410RB can be found here: - -- `STM32F410RB on www.st.com`_ -- `STM32F410 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_f410rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | window & independent | -+-----------+------------+-------------------------------------+ - - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f410rb/nucleo_f410rb_defconfig`` - - -Connections and IOs -=================== - -Nucleo F410RB Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f410rb_arduino_top_left.jpg - :align: center - :alt: Nucleo F410RB Arduino connectors (top left) -.. image:: img/nucleo_f410rb_arduino_top_right.jpg - :align: center - :alt: Nucleo F410RB Arduino connectors (top right) -.. image:: img/nucleo_f410rb_morpho_top_left.jpg - :align: center - :alt: Nucleo F410RB Morpho connectors (top left) -.. image:: img/nucleo_f410rb_morpho_top_right.jpg - :align: center - :alt: Nucleo F410RB Morpho connectors (top right) - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- USER_PB : PC13 -- LD2 : PA5 -- I2C1_SDA : PB9 -- I2C1_SCL : PB8 -- I2C2_SDA : PB3 -- I2C2_SCL : PB10 - -System Clock ------------- - -Nucleo F410RB System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, -driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F410RB board has 3 USARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_f410rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F410RB board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F410RB ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f410rb - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f410rb - :maybe-skip-config: - :goals: debug - -.. _Nucleo F410RB website: - https://www.st.com/en/evaluation-tools/nucleo-F410RB.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F410RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32f410rb.html - -.. _STM32F410 reference manual: - https://www.st.com/resource/en/reference_manual/dm00180366.pdf diff --git a/boards/arm/nucleo_f411re/Kconfig.board b/boards/arm/nucleo_f411re/Kconfig.board deleted file mode 100644 index 8d14124ab07..00000000000 --- a/boards/arm/nucleo_f411re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-64 F411RE board configuration - -# Copyright (c) 2016 Matthias Boesl -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F411RE - bool "NUCLEO-64 F411RE Development Board" - depends on SOC_STM32F411XE diff --git a/boards/arm/nucleo_f411re/Kconfig.defconfig b/boards/arm/nucleo_f411re/Kconfig.defconfig deleted file mode 100644 index ca331991f94..00000000000 --- a/boards/arm/nucleo_f411re/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# NUCLEO-64 F411RE board configuration - -# Copyright (c) 2016 Matthias Boesl -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F411RE - -config BOARD - default "nucleo_f411re" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F411RE diff --git a/boards/arm/nucleo_f411re/doc/index.rst b/boards/arm/nucleo_f411re/doc/index.rst deleted file mode 100644 index 908dfbf9a2a..00000000000 --- a/boards/arm/nucleo_f411re/doc/index.rst +++ /dev/null @@ -1,200 +0,0 @@ -.. _nucleo_f411re_board: - -ST Nucleo F411RE -################ - -Overview -******** - -The Nucleo F411RE board features an ARM Cortex-M4 based STM32F411RE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F411RE board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f411re.jpg - :align: center - :alt: Nucleo F411RE - -More information about the board can be found at the `Nucleo F411RE website`_. - -Hardware -******** - -Nucleo F411RE provides the following hardware components: - -- STM32F411RET6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 128 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 16 channels, with FIFO and burst support -- RTC -- 8 General purpose timers -- 2 watchdog timers (independent and window) -- SysTick timer -- USART/UART (3) -- I2C (3) -- SPI/I2S (5) -- SDIO -- USB 2.0 OTG FS -- DMA Controller -- CRC calculation unit - -More information about STM32F411RE can be found here: - -- `STM32F411RE on www.st.com`_ -- `STM32F411 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_f411re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f411re/nucleo_f411re_defconfig`` - - -Connections and IOs -=================== - -Nucleo F411RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f411re_arduino.jpg - :align: center - :alt: Nucleo F411RE Arduino connectors -.. image:: img/nucleo_f411re_morpho.jpg - :align: center - :alt: Nucleo F411RE Morpho connectors - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PB10/PB3 -- I2C1 SCL/SDA : PA8/B4 -- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) -- I2S1 SCK/SD : PA5/PA7 (Arduino I2S) -- USER_PB : PC13 -- LD2 : PA5 - -.. note:: Please note that SPI1 and I2S1 are connected to the same mcu pins, as the h/w controller is the same one. - -System Clock ------------- - -Nucleo F411RE System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 84MHz, -driven by 8MHz high speed external clock. - -Serial Port ------------ - -Nucleo F411RE board has 3 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_f411re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F411RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to Nucleo F411RE ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f411re - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f411re - :maybe-skip-config: - :goals: debug - -.. _Nucleo F411RE website: - https://www.st.com/en/evaluation-tools/nucleo-f411re.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F411RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f411re.html - -.. _STM32F411 reference manual: - https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/nucleo_f412zg/Kconfig.board b/boards/arm/nucleo_f412zg/Kconfig.board deleted file mode 100644 index 4df2769a2a1..00000000000 --- a/boards/arm/nucleo_f412zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-144 F412ZG board configuration - -# Copyright (c) 2017 Florian Vaussard, HEIG-VD -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F412ZG - bool "NUCLEO-144 F412ZG Development Board" - depends on SOC_STM32F412ZX diff --git a/boards/arm/nucleo_f412zg/Kconfig.defconfig b/boards/arm/nucleo_f412zg/Kconfig.defconfig deleted file mode 100644 index 428368d5927..00000000000 --- a/boards/arm/nucleo_f412zg/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# NUCLEO-144 F412ZG board configuration - -# Copyright (c) 2017 Florian Vaussard, HEIG-VD -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F412ZG - -config BOARD - default "nucleo_f412zg" - -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_ECM - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F412ZG diff --git a/boards/arm/nucleo_f412zg/doc/index.rst b/boards/arm/nucleo_f412zg/doc/index.rst deleted file mode 100644 index 678971ecf1e..00000000000 --- a/boards/arm/nucleo_f412zg/doc/index.rst +++ /dev/null @@ -1,172 +0,0 @@ -.. _nucleo_f412zg_board: - -ST Nucleo F412ZG -################ - -Overview -******** - -The Nucleo F412ZG board features an ARM Cortex-M4 based STM32F412ZG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F412ZG board: - -- STM32 microcontroller in LQFP144 package -- Two types of extension resources: - - - ST Zio connector including: support for Arduino* Uno V3 connectivity - (A0 to A5, D0 to D15) and additional signals exposing a wide range of - peripherals - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- Three user LEDs -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f412zg.jpg - :align: center - :alt: Nucleo F412ZG - -More information about the board can be found at the `Nucleo F412ZG website`_. - -Hardware -******** - -Nucleo F412ZG provides the following hardware components: - -- STM32F412ZGT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1 MB Flash -- 256 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 16 channels, with FIFO and burst support -- RTC -- 14 General purpose timers -- 2 watchdog timers (independent and window) -- SysTick timer -- USART/UART (4) -- I2C (4) -- SPI (5) -- SDIO -- USB 2.0 OTG FS -- DMA Controller -- CRC calculation unit - -More information about STM32F412ZG can be found here: - -- `STM32F412ZG on www.st.com`_ -- `STM32F412 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_412zg board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f412zg/nucleo_f412zg_defconfig`` - - -Connections and IOs -=================== - -Nucleo F412ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f412zg_zio_left.jpg - :align: center - :alt: Nucleo F412ZG ZIO connectors (left) -.. image:: img/nucleo_f412zg_zio_right.jpg - :align: center - :alt: Nucleo F412ZG ZIO connectors (right) -.. image:: img/nucleo_f412zg_morpho_left.jpg - :align: center - :alt: Nucleo F412ZG Morpho connectors (left) -.. image:: img/nucleo_f412zg_morpho_right.jpg - :align: center - :alt: Nucleo F412ZG Morpho connectors (right) - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- USB DM : PA11 -- USB DP : PA12 - -System Clock ------------- - -Nucleo F412ZG System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz, -driven by 8MHz high speed external clock. - -Serial Port ------------ - -Nucleo F412ZG board has 4 UARTs. The Zephyr console output is assigned to UART3. -Default settings are 115200 8N1. - -Network interface ------------------ - -Ethernet over USB is configured as the default network interface - -Programming and Debugging -************************* - -Nucleo F412ZG board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F412ZG website: - https://www.st.com/en/evaluation-tools/nucleo-f412zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32F412ZG on www.st.com: - https://www.st.com/en/microcontrollers/stm32f412zg.html - -.. _STM32F412 reference manual: - https://www.st.com/resource/en/reference_manual/dm00180369.pdf diff --git a/boards/arm/nucleo_f413zh/Kconfig.board b/boards/arm/nucleo_f413zh/Kconfig.board deleted file mode 100644 index ae28485aeb6..00000000000 --- a/boards/arm/nucleo_f413zh/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-144 F413ZH board configuration - -# Copyright (c) 2017 Florian Vaussard, HEIG-VD -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F413ZH - bool "NUCLEO-144 F413ZH Development Board" - depends on SOC_STM32F413XX diff --git a/boards/arm/nucleo_f413zh/Kconfig.defconfig b/boards/arm/nucleo_f413zh/Kconfig.defconfig deleted file mode 100644 index e340a26c99d..00000000000 --- a/boards/arm/nucleo_f413zh/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# NUCLEO-144 F413ZH board configuration - -# Copyright (c) 2017 Florian Vaussard, HEIG-VD -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F413ZH - -config BOARD - default "nucleo_f413zh" - -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_ECM - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F413ZH diff --git a/boards/arm/nucleo_f413zh/doc/index.rst b/boards/arm/nucleo_f413zh/doc/index.rst deleted file mode 100644 index 7979171472e..00000000000 --- a/boards/arm/nucleo_f413zh/doc/index.rst +++ /dev/null @@ -1,174 +0,0 @@ -.. _nucleo_f413zh_board: - -ST Nucleo F413ZH -################ - -Overview -******** - -The Nucleo F413ZH board features an ARM Cortex-M4 based STM32F413ZH MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F413ZH board: - -- STM32 microcontroller in LQFP144 package -- Two types of extension resources: - - - ST Zio connector including: support for Arduino* Uno V3 connectivity - (A0 to A5, D0 to D15) and additional signals exposing a wide range of - peripherals - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- Three user LEDs -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f413zh.jpg - :align: center - :alt: Nucleo F413ZH - -More information about the board can be found at the `Nucleo F413ZH website`_. - -Hardware -******** - -Nucleo F413ZH provides the following hardware components: - -- STM32F413ZHT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1.5 MB Flash -- 320 KB SRAM -- GPIO with external interrupt capability -- 2 12-bit ADC with 16 channels, with FIFO and burst support -- RTC -- 14 General purpose timers -- 2 watchdog timers (independent and window) -- SysTick timer -- USART/UART (10) -- I2C (4) -- SPI (5) -- SDIO -- USB 2.0 OTG FS -- DMA Controller -- CRC calculation unit - -More information about STM32F413ZH can be found here: - -- `STM32F413ZH on www.st.com`_ -- `STM32F413/423 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_413zh board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f413zh/nucleo_f413zh_defconfig`` - - -Connections and IOs -=================== - -Nucleo F413ZH Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f413zh_zio_left.jpg - :align: center - :alt: Nucleo F413ZH ZIO connectors (left) -.. image:: img/nucleo_f413zh_zio_right.jpg - :align: center - :alt: Nucleo F413ZH ZIO connectors (right) -.. image:: img/nucleo_f413zh_morpho_left.jpg - :align: center - :alt: Nucleo F413ZH Morpho connectors (left) -.. image:: img/nucleo_f413zh_morpho_right.jpg - :align: center - :alt: Nucleo F413ZH Morpho connectors (right) - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) -- PWM_2_CH1 : PA0 -- USB_DM : PA11 -- USB_DP : PA12 -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 - -System Clock ------------- - -Nucleo F413ZH System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz, -driven by 8MHz high speed external clock. - -Serial Port ------------ - -Nucleo F413ZH board has 10 UARTs. The Zephyr console output is assigned to UART3. -Default settings are 115200 8N1. - -USB -=== -Nucleo F413ZH board has a USB OTG dual-role device (DRD) controller that -supports both device and host functions through its micro USB connector -(USB USER). Only USB device function is supported in Zephyr at the moment. - - -Programming and Debugging -************************* - -Nucleo F413ZH board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F413ZH website: - https://www.st.com/en/evaluation-tools/nucleo-f413zh.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32F413ZH on www.st.com: - https://www.st.com/en/microcontrollers/stm32f413zh.html - -.. _STM32F413/423 reference manual: - https://www.st.com/resource/en/reference_manual/dm00305666.pdf diff --git a/boards/arm/nucleo_f429zi/Kconfig.board b/boards/arm/nucleo_f429zi/Kconfig.board deleted file mode 100644 index b9e033f8622..00000000000 --- a/boards/arm/nucleo_f429zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-144 F429ZI board configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F429ZI - bool "NUCLEO-144 F429ZI Development Board" - depends on SOC_STM32F429XX diff --git a/boards/arm/nucleo_f429zi/Kconfig.defconfig b/boards/arm/nucleo_f429zi/Kconfig.defconfig deleted file mode 100644 index 99fdd74ade1..00000000000 --- a/boards/arm/nucleo_f429zi/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# NUCLEO-144 F429ZI board configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F429ZI - -config BOARD - default "nucleo_f429zi" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F429ZI diff --git a/boards/arm/nucleo_f429zi/doc/index.rst b/boards/arm/nucleo_f429zi/doc/index.rst deleted file mode 100644 index e65e9194ad4..00000000000 --- a/boards/arm/nucleo_f429zi/doc/index.rst +++ /dev/null @@ -1,217 +0,0 @@ -.. _nucleo_f429zi_board: - -ST Nucleo F429ZI -################ - -Overview -******** - -The Nucleo F429ZI board features an ARM Cortex-M4 based STM32F429ZI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F429ZI board: - -- STM32 microcontroller in LQFP144 package -- LSE crystal: 32.768 kHz crystal oscillator -- USB OTG -- Ethernet compliant with IEEE-802.3-2002 -- Two types of extension resources: - - - ST Zio connector including: support for Arduino* Uno V3 connectivity - (A0 to A5, D0 to D15) and additional signals exposing a wide range of - peripherals - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- Three user LEDs -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f429zi.jpg - :align: center - :alt: Nucleo F429ZI - -More information about the board can be found at the `Nucleo F429ZI website`_. - -Hardware -******** - -The Nucleo F429ZI provides the following hardware components: - -- STM32F429ZIT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 180 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 2 MB Flash -- 256+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (4/4) -- I2C (3) -- SPI (6) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F429ZI can be found here: - -- `STM32F429ZI on www.st.com`_ -- `STM32F429 reference manual`_ -- `STM32F429 datasheet`_ - -Supported Features -================== - -The Zephyr nucleo_f429zi board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | Ethernet | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig`` - - -Connections and IOs -=================== - -The Nucleo F429ZI Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f429zi_cn8.jpg - :align: center - :alt: Nucleo F429ZI ZIO connectors (left) -.. image:: img/nucleo_f429zi_cn7.jpg - :align: center - :alt: Nucleo F429ZI ZIO connectors (right) -.. image:: img/nucleo_f429zi_cn11.jpg - :align: center - :alt: Nucleo F429ZI Morpho connectors (left) -.. image:: img/nucleo_f429zi_cn12.jpg - :align: center - :alt: Nucleo F429ZI Morpho connectors (right) - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F429ZI board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) -- PWM_2_CH1 : PE13 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- USB DM : PA11 -- USB DP : PA12 -- ADC1 : PA0 - -System Clock ------------- - -The Nucleo F429ZI System Clock could be driven by an internal or external oscillator, -as well as by the main PLL clock. By default System clock is driven by PLL clock at 180MHz, -driven by an 8MHz high speed external clock. - -Serial Port ------------ - -The Nucleo F429ZI board has 8 UARTs. The Zephyr console output is assigned to UART3. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -The Nucleo F429ZI board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flash partitions for MCUBoot bootloader -*************************************** - -The on-board STM32F429ZI MCU has 2MBs of internal flash memory. To use `MCUboot`_, -define a :ref:`Zephyr partition table ` for the flash memory in -its devicetree file ``nucleo_f429zi.dts``. As a reference, a partition table for -MCUBoot is already defined in the devicetree file, with these settings: - -- `MCUBoot`_ bootloader partition takes 64K bytes. -- Zephyr settings partition takes 64K bytes. -- Application image takes 256K bytes in Slot 0 partition. -- Updating image takes another 256K bytes in Slot 1 partition. -- A scratch partition with 128K is required for image swap. - -A specific application can adjust each partition size based on its needs. - - -.. _Nucleo F429ZI website: - https://www.st.com/en/evaluation-tools/nucleo-f429zi.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32F429ZI on www.st.com: - https://www.st.com/en/microcontrollers/stm32f429zi.html - -.. _STM32F429 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031020.pdf - -.. _STM32F429 datasheet: - https://www.st.com/resource/en/datasheet/DM00071990.pdf - -.. _MCUBoot: - https://github.com/JuulLabs-OSS/mcuboot/blob/master/README.md diff --git a/boards/arm/nucleo_f446re/Kconfig.board b/boards/arm/nucleo_f446re/Kconfig.board deleted file mode 100644 index 71f63f7b8e1..00000000000 --- a/boards/arm/nucleo_f446re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F446RE Nucleo board configuration - -# Copyright (c) 2018 Philémon Jaermann -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F446RE - bool "Nucleo F446RE Development Board" - depends on SOC_STM32F446XX diff --git a/boards/arm/nucleo_f446re/Kconfig.defconfig b/boards/arm/nucleo_f446re/Kconfig.defconfig deleted file mode 100644 index 409b8bd5d47..00000000000 --- a/boards/arm/nucleo_f446re/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32F446RE Nucleo board configuration - -# Copyright (c) 2018 Philémon Jaermann -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F446RE - -config BOARD - default "nucleo_f446re" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F446RE diff --git a/boards/arm/nucleo_f446re/doc/index.rst b/boards/arm/nucleo_f446re/doc/index.rst deleted file mode 100644 index 37d62c04310..00000000000 --- a/boards/arm/nucleo_f446re/doc/index.rst +++ /dev/null @@ -1,226 +0,0 @@ -.. _nucleo_f446re_board: - -ST Nucleo F446RE -################ - -Overview -******** - -The Nucleo F446RE board features an ARM Cortex-M4 based STM32F446RE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F446RE board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f446re.jpg - :align: center - :alt: Nucleo F446RE - -More information about the board can be found at the `Nucleo F446RE website`_. - -Hardware -******** - -Nucleo F446RE provides the following hardware components: - -- STM32F446RET6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- Adaptive real-time accelerator (ART Accelerator) -- 180 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 128 KB SRAM -- 10 General purpose timers -- 2 Advanced control timers -- 2 basic timers -- SPI(4) -- I2C(3) -- USART(4) -- UART(2) -- USB OTG Full Speed and High Speed -- CAN(2) -- SAI(2) -- SPDIF_Rx(1) -- HDMI_CEC(1) -- Quad SPI(1) -- Camera Interface -- GPIO(50) with external interrupt capability -- 12-bit ADC(3) with 16 channels -- 12-bit DAC with 2 channels - -More information about STM32F446RE can be found here: - -- `STM32F446RE on www.st.com`_ -- `STM32F446 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_f446re board configuration supports the following hardware features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ -| CAN 1/2 | on-chip | Controller Area Network | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f446re/nucleo_f446re_defconfig`` - - -Connections and IOs -=================== - -Nucleo F446RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f446re_arduino_top_left.jpg - :align: center - :alt: Nucleo F446RE Arduino connectors (top left) -.. image:: img/nucleo_f446re_arduino_top_right.jpg - :align: center - :alt: Nucleo F446RE Arduino connectors (top right) -.. image:: img/nucleo_f446re_morpho_top_left.jpg - :align: center - :alt: Nucleo F446RE Morpho connectors (top left) -.. image:: img/nucleo_f446re_morpho_top_right.jpg - :align: center - :alt: Nucleo F446RE Morpho connectors (top right) - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- USER_PB : PC13 -- LD2 : PA5 -- I2C1_SDA : PB9 -- I2C1_SCL : PB8 -- I2C2_SDA : PB3 -- I2C2_SCL : PB10 -- I2C3_SDA : PB4 -- I2C3_SCL : PA8 - -System Clock ------------- - -Nucleo F446RE System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, -driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F446RE board has 2 UARTs and 4 USARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB45`` jumper on the back side of the board. - -Controller Area Network ------------------------ - -The TX/RX wires connected with D14/D15 of CN5 connector. Thus the board can be -used with `RS485 CAN Shield`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f446re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F446RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F446RE ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f446re - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f446re - :maybe-skip-config: - :goals: debug - -.. _Nucleo F446RE website: - https://www.st.com/en/evaluation-tools/nucleo-f446re.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F446RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f446re.html - -.. _STM32F446 reference manual: - https://www.st.com/resource/en/reference_manual/dm00135183.pdf - -.. _RS485 CAN Shield: - https://www.waveshare.com/wiki/RS485_CAN_Shield diff --git a/boards/arm/nucleo_f446ze/Kconfig.board b/boards/arm/nucleo_f446ze/Kconfig.board deleted file mode 100644 index f926632c73c..00000000000 --- a/boards/arm/nucleo_f446ze/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F446ZE Nucleo board configuration - -# Copyright (c) 2021 Tom Owen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F446ZE - bool "Nucleo F446ZE Development Board" - depends on SOC_STM32F446XX diff --git a/boards/arm/nucleo_f446ze/Kconfig.defconfig b/boards/arm/nucleo_f446ze/Kconfig.defconfig deleted file mode 100644 index a256cd1c42a..00000000000 --- a/boards/arm/nucleo_f446ze/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32F446ZE Nucleo board configuration - -# Copyright (c) 2021 Tom Owen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F446ZE - -config BOARD - default "nucleo_f446ze" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F446ZE diff --git a/boards/arm/nucleo_f446ze/doc/index.rst b/boards/arm/nucleo_f446ze/doc/index.rst deleted file mode 100644 index 697324e84fa..00000000000 --- a/boards/arm/nucleo_f446ze/doc/index.rst +++ /dev/null @@ -1,248 +0,0 @@ -.. _nucleo_f446ze_board: - -ST Nucleo F446ZE -################ - - -Overview -******** - -The Nucleo F446ZE board features an ARM Cortex-M4 based STM32F446ZE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F446ZE board: - -- STM32F446 microcontroller in QFP144 package -- Two types of extension resources: - - - ST zio support for Arduino™ Uno V3 connectivity (A0 to A5, D0 to D15) and additional signals exposing a wide range of peripherals - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- USB re-enumeration capability. Three different interfaces supported on USB: - - Virtual Com port - - Mass storage (USB Disk drive) for drag'n'drop programming - - Debug port -- Flexible board power supply: - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - - USB OTG - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f446ze.jpg - :align: center - :alt: Nucleo F446ZE - -More information about the board can be found at the `Nucleo F446ZE website`_. - -Hardware -******** - -Nucleo F446ZE provides the following hardware components: - -- STM32F446ZET6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- Adaptive real-time accelerator (ART Accelerator) -- 180 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 128 KB SRAM -- 10 General purpose timers -- 2 Advanced control timers -- 2 basic timers -- SPI(4) -- I2C(4) -- USART(4) -- UART(2) -- USB OTG Full Speed and High Speed -- CAN(2) -- SAI(2) -- SPDIF_Rx(1) -- HDMI_CEC(1) -- Quad SPI(1) -- Camera Interface -- GPIO(50) with external interrupt capability -- 12-bit ADC(3) with 16 channels -- 12-bit DAC with 2 channels - -More information about STM32F446ZE can be found here: - -- `STM32F446ZE on www.st.com`_ -- `STM32F446 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_f446ze board configuration supports the following hardware features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ -| CAN 1/2 | on-chip | Controller Area Network | -+-------------+------------+-------------------------------------+ -| ADC | on-chip | Analog Input | -+-------------+------------+-------------------------------------+ -| DAC | on-chip | Analog Output | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f446ze/nucleo_f446ze_defconfig`` - - -Connections and IOs -=================== - -Nucleo F446ZE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f446ze_zio_left_2019_8_29.jpg - :align: center - :alt: Nucleo F446ZE Zio/Arduino connectors (left) -.. image:: img/nucleo_f446ze_zio_right_2019_8_29.jpg - :align: center - :alt: Nucleo F446ZE Zio/Arduino connectors (right) -.. image:: img/nucleo_f446ze_morpho_left_2019_8_29.jpg - :align: center - :alt: Nucleo F446ZE Morpho connectors (left) -.. image:: img/nucleo_f446ze_morpho_right_2019_8_29.jpg - :align: center - :alt: Nucleo F446ZE Morpho connectors (right) - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- UART_3_TX : PD8 -- UART_3_RX : PD9 -- USER_PB : PC13 -- LD0 : PB0 -- LD1 : PB7 -- LD2 : PB14 -- I2C1_SDA : PB9 -- I2C1_SCL : PB8 -- I2C2_SDA : PF0 -- I2C2_SCL : PF1 -- SPI1_CS : PD14 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 -- CAN1_RX : PD0 -- CAN1_TX : PD1 -- USB_DP : PA11 -- USB_DM : PA12 -- ADC1_IN0 : PA0 -- DAC_OUT1 : PA4 - - -System Clock ------------- - -Nucleo F446ZE System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, -driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F446ZE board has 2 UARTs and 4 USARTs. The Zephyr console output is assigned to USART3. -Default settings are 115200 8N1. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB156`` jumper on the back side of the board. - -Controller Area Network ------------------------ - -The TX/RX wires are connected with pins 25/27 of CN9 connector. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f446ze`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F446ZE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F446ZE ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f446ze - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f446ze - :maybe-skip-config: - :goals: debug - -.. _Nucleo F446ZE website: - https://www.st.com/en/evaluation-tools/nucleo-f446ze.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/um1974-stm32-nucleo144-boards-mb1137-stmicroelectronics.pdf - -.. _STM32F446ZE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f446ze.html - -.. _STM32F446 reference manual: - https://www.st.com/resource/en/reference_manual/dm00135183.pdf diff --git a/boards/arm/nucleo_f722ze/Kconfig.board b/boards/arm/nucleo_f722ze/Kconfig.board deleted file mode 100644 index f15e218e161..00000000000 --- a/boards/arm/nucleo_f722ze/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F722ZE Nucleo board configuration - -# Copyright (c) 2023 Evan Perry Grove -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F722ZE - bool "Nucleo F722ZE Development Board" - depends on SOC_STM32F722XX diff --git a/boards/arm/nucleo_f722ze/Kconfig.defconfig b/boards/arm/nucleo_f722ze/Kconfig.defconfig deleted file mode 100644 index 1dfff0c9d44..00000000000 --- a/boards/arm/nucleo_f722ze/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32F722ZE Nucleo board configuration -# -# Copyright (c) 2023 Evan Perry Grove -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F722ZE - -config BOARD - default "nucleo_f722ze" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F722ZE diff --git a/boards/arm/nucleo_f746zg/Kconfig.board b/boards/arm/nucleo_f746zg/Kconfig.board deleted file mode 100644 index 1b533d6b8dd..00000000000 --- a/boards/arm/nucleo_f746zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F746ZG Nucleo board configuration - -# Copyright (c) 2018 AJ Palmer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F746ZG - bool "Nucleo F746ZG Development Board" - depends on SOC_STM32F746XX diff --git a/boards/arm/nucleo_f746zg/Kconfig.defconfig b/boards/arm/nucleo_f746zg/Kconfig.defconfig deleted file mode 100644 index 8e021fdf61a..00000000000 --- a/boards/arm/nucleo_f746zg/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32F746ZG Nucleo board configuration - -# Copyright (c) 2018 AJ Palmer -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F746ZG - -config BOARD - default "nucleo_f746zg" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F746ZG diff --git a/boards/arm/nucleo_f746zg/doc/index.rst b/boards/arm/nucleo_f746zg/doc/index.rst deleted file mode 100644 index 8bc083bcc3f..00000000000 --- a/boards/arm/nucleo_f746zg/doc/index.rst +++ /dev/null @@ -1,235 +0,0 @@ -.. _nucleo_f746zg_board: - -ST Nucleo F746ZG -################ - -Overview -******** - -The STM32 Nucleo-144 boards offer combinations of performance and power that -provide an affordable and flexible way for users to build prototypes and try -out new concepts. For compatible boards, the SMPS significantly reduces power -consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V2-1 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - Ethernet RJ45 (depending on STM32 support) - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_f746zg.jpg - :align: center - :alt: Nucleo F746ZG - -More information about the board can be found at the `Nucleo F746ZG website`_. - -Hardware -******** - -Nucleo F746ZG provides the following hardware components: - -- STM32F746ZG in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- ART Accelerator -- 216 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1 MB Flash -- 320 KB SRAM -- 16-bit timers(10) -- 32-bit timers(2) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO(up to 168) with external interrupt capability -- 12-bit ADC(3) with 24 channels / 2.4 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_f746zg board configuration supports the following hardware -features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-------------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-------------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-------------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f746zg/nucleo_f746zg_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F746ZG board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino UART) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- USB DM : PA11 -- USB DP : PA12 -- I2C : PB8, PB9 -- PWM : PE13 -- SPI : PD14, PA5, PA6, PA7 -- ADC1_IN0 : PA0 -- DAC1_OUT1 : PA4 - -Note. The Arduino Uno v3 specified SPI device conflicts with the on-board ETH -device on pin PA7. - -System Clock ------------- - -Nucleo F746ZG System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F746ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB156`` jumper on the back side of the board. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f746zg`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F746ZG board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo F746ZG ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f746zg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_f746zg - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f746zg - :maybe-skip-config: - :goals: debug - -.. _Nucleo F746ZG website: - https://www.st.com/en/evaluation-tools/nucleo-f746zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32F746ZG on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f746zg.html - -.. _STM32F746 reference manual: - https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/nucleo_f756zg/Kconfig.board b/boards/arm/nucleo_f756zg/Kconfig.board deleted file mode 100644 index 46f61135b86..00000000000 --- a/boards/arm/nucleo_f756zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F756ZG Nucleo board configuration - -# Copyright (c) 2018 AJ Palmer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F756ZG - bool "Nucleo F756ZG Development Board" - depends on SOC_STM32F756XX diff --git a/boards/arm/nucleo_f756zg/Kconfig.defconfig b/boards/arm/nucleo_f756zg/Kconfig.defconfig deleted file mode 100644 index d6b1759beb5..00000000000 --- a/boards/arm/nucleo_f756zg/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32F756ZG Nucleo board configuration - -# Copyright (c) 2018 AJ Palmer -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F756ZG - -config BOARD - default "nucleo_f756zg" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F756ZG diff --git a/boards/arm/nucleo_f756zg/doc/index.rst b/boards/arm/nucleo_f756zg/doc/index.rst deleted file mode 100644 index aa13ddb7f20..00000000000 --- a/boards/arm/nucleo_f756zg/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ -.. _nucleo_f756zg_board: - -ST Nucleo F756ZG -################ - -Overview -******** - -The STM32 Nucleo-144 boards offer combinations of performance and power that -provide an affordable and flexible way for users to build prototypes and try -out new concepts. For compatible boards, the SMPS significantly reduces power -consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V2-1 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - Ethernet RJ45 (depending on STM32 support) - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration - capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the -- STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_f756zg.jpg - :align: center - :alt: Nucleo F756ZG - -More information about the board can be found at the `Nucleo F756ZG website`_. - -Hardware -******** - -Nucleo F756ZG provides the following hardware components: - -- STM32F756ZG in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- ART Accelerator -- 216 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1 MB Flash -- 320 KB SRAM -- 16-bit timers(10) -- 32-bit timers(2) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO(up to 168) with external interrupt capability -- 12-bit ADC(3) with 24 channels / 2.4 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_f756zg board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f756zg/nucleo_f756zg_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F756ZG board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino UART) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- USB DM : PA11 -- USB DP : PA12 -- I2C : PB8, PB9 -- PWM : PE13 -- SPI : PD14, PA5, PA6, PA7 - -Note. The Arduino Uno v3 specified SPI device conflicts with the on-board ETH -device on pin PA7. - -System Clock ------------- - -Nucleo F756ZG System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F756ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_f756zg`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F756ZG board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo F756ZG ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f756zg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_f756zg - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f756zg - :maybe-skip-config: - :goals: debug - -.. _Nucleo F756ZG website: - https://www.st.com/en/evaluation-tools/nucleo-f756zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F756ZG on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f756zg.html - -.. _STM32F756 reference manual: - https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/nucleo_f767zi/Kconfig.board b/boards/arm/nucleo_f767zi/Kconfig.board deleted file mode 100644 index d76625a7e59..00000000000 --- a/boards/arm/nucleo_f767zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F767ZI Nucleo board configuration - -# Copyright (c) 2019 Roland Ma -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F767ZI - bool "Nucleo F767ZI Development Board" - depends on SOC_STM32F767XX diff --git a/boards/arm/nucleo_f767zi/Kconfig.defconfig b/boards/arm/nucleo_f767zi/Kconfig.defconfig deleted file mode 100644 index b53353b2b06..00000000000 --- a/boards/arm/nucleo_f767zi/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32F767ZI Nucleo board configuration - -# Copyright (c) 2019 Roland Ma -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F767ZI - -config BOARD - default "nucleo_f767zi" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F767ZI diff --git a/boards/arm/nucleo_f767zi/doc/index.rst b/boards/arm/nucleo_f767zi/doc/index.rst deleted file mode 100644 index 7eca2af1eda..00000000000 --- a/boards/arm/nucleo_f767zi/doc/index.rst +++ /dev/null @@ -1,236 +0,0 @@ -.. _nucleo_f767zi_board: - -ST Nucleo F767ZI -################ - -Overview -******** - -The STM32 Nucleo-144 F767ZI boards offer combinations of performance and -power that provide an affordable and flexible way for users to build -prototypes and try out new concepts. For compatible boards, the SMPS -significantly reduces power consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V2-1 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - Ethernet RJ45 (depending on STM32 support) - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_f767zi.jpg - :align: center - :alt: Nucleo F767ZI - -More information about the board can be found at the `Nucleo F767ZI website`_. - -Hardware -******** - -Nucleo F767ZI provides the following hardware components: - -- STM32F767ZI in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- ART Accelerator -- 216 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 2 MB Flash -- 512 KB SRAM -- 16-bit timers(10) -- 32-bit timers(2) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO(up to 168) with external interrupt capability -- 12-bit ADC(3) with 24 channels / 2.4 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_f767zi board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet (*) | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ - - -(*) nucleo_f767zi with soc cut-A (Device marking A) has some ethernet - instability (:github:`26519`). - Use of cut-Z is advised. - see restrictions errata: - https://www.st.com/content/ccc/resource/technical/document/errata_sheet/group0/23/a6/11/0b/30/24/46/a5/DM00257543/files/DM00257543.pdf/jcr:content/translations/en.DM00257543.pdf - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f767zi/nucleo_f767zi_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F767ZI board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino UART) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- USB DM : PA11 -- USB DP : PA12 -- I2C : PB8, PB9 -- PWM : PE13 -- SPI : PD14, PA5, PA6, PA7 - -.. note:: - The Arduino Uno v3 specified SPI device conflicts with the on-board ETH - device on pin PA7. - -System Clock ------------- - -Nucleo F767ZI System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F767ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_f767zi`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F767ZI board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo F767ZI ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f767zi - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_f767zi - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f767zi - :maybe-skip-config: - :goals: debug - -.. _Nucleo f767zi website: - https://www.st.com/en/evaluation-tools/nucleo-f767zi.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32f767zi on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x&/stm32f767zi.html - -.. _STM32F767 reference manual: - https://www.st.com/resource/en/reference_manual/DM00224583.pdf diff --git a/boards/arm/nucleo_g031k8/Kconfig.board b/boards/arm/nucleo_g031k8/Kconfig.board deleted file mode 100644 index 02133d33257..00000000000 --- a/boards/arm/nucleo_g031k8/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-32 development board with STM32G031K8 MCU configuration - -# Copyright (c) 2022 Joylab AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G031K8 - bool "NUCLEO-32 G031K8 Development Board" - depends on SOC_STM32G031XX diff --git a/boards/arm/nucleo_g031k8/Kconfig.defconfig b/boards/arm/nucleo_g031k8/Kconfig.defconfig deleted file mode 100644 index b448461f39e..00000000000 --- a/boards/arm/nucleo_g031k8/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-32 development board with STM32G031K8 MCU - -# Copyright (c) 2022 Joylab AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G031K8 - -config BOARD - default "nucleo_g031k8" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_G031K8 diff --git a/boards/arm/nucleo_g031k8/doc/index.rst b/boards/arm/nucleo_g031k8/doc/index.rst deleted file mode 100644 index 93a10b553ab..00000000000 --- a/boards/arm/nucleo_g031k8/doc/index.rst +++ /dev/null @@ -1,168 +0,0 @@ -.. _nucleo_g031k8_board: - -ST Nucleo G031K8 -################ - -Overview -******** -The STM32 Nucleo-32 board provides an affordable and flexible way for users to try -out new concepts and build prototypes by choosing from the various combinations of -performance and power consumption features, provided by the STM32 -microcontroller. - -The Arduino™ Nano V3 connectivity support allows the easy expansion of the -functionality of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo-32 board does not require any separate probe as it integrates the -ST-LINK debugger/programmer. - -The STM32 Nucleo-32 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - - -.. image:: img/nucleo_g031k8.jpg - :align: center - :alt: Nucleo G031K8 - -More information about the board can be found at the `Nucleo G031K8 website`_. - -Hardware -******** -Nucleo G031K8 provides the following hardware components: - -- STM32 microcontroller in 32-pin package featuring 64 Kbytes of Flash memory - and 8 Kbytes of SRAM. -- Extension resource: - - - Arduino* Nano V3 connectivity - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Current consumption measurement (IDD) - -- Four LEDs: - - - USB communication (LD1), power LED (LD2), user LED (LD3), - USB power fault LED (LD4) - -- One push-button: RESET - -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -More information about STM32G031K8 can be found in the -`STM32G0x1 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_g031k8 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g031k8/nucleo_g031k8_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C2 SCL/SDA : PA9/PA10 (Arduino I2C) -- SPI1 SCK/MISO/MOSI : PB3/PB4/PB5 (Arduino SPI) -- LD3 : PC6 - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g031k8`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G031K8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo G031K8 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_g031k8 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g031k8 - :maybe-skip-config: - :goals: debug - -Restriction -*********** - -On some boards, the board reset line is not used by the controller. -Therefore the reset button, reset-pin and the ST-Link reset have no effect. -To enable those functionalities, the option byte NRST_mode in the User -Configuration needs to be changed from 2 to 1 or 3 - depending on the -requirements. - -References -********** - -.. target-notes:: - -.. _Nucleo G031K8 website: - https://www.st.com/en/evaluation-tools/nucleo-g031k8.html - -.. _STM32G0x1 reference manual: - https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/um2591-stm32g0-nucleo32-board-mb1455-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_g070rb/Kconfig.board b/boards/arm/nucleo_g070rb/Kconfig.board deleted file mode 100644 index eb32da85a2e..00000000000 --- a/boards/arm/nucleo_g070rb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G070RB MCU configuration - -# Copyright (c) 2023 Marin Jurjević -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G070RB - bool "NUCLEO-64 G070RB Development Board" - depends on SOC_STM32G070XX diff --git a/boards/arm/nucleo_g070rb/Kconfig.defconfig b/boards/arm/nucleo_g070rb/Kconfig.defconfig deleted file mode 100644 index 7fd80219e44..00000000000 --- a/boards/arm/nucleo_g070rb/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G070RB MCU - -# Copyright (c) 2023 Marin Jurjević -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G070RB - -config BOARD - default "nucleo_g070rb" - -endif # BOARD_NUCLEO_G070RB diff --git a/boards/arm/nucleo_g070rb/doc/index.rst b/boards/arm/nucleo_g070rb/doc/index.rst deleted file mode 100644 index 8908ed5ce43..00000000000 --- a/boards/arm/nucleo_g070rb/doc/index.rst +++ /dev/null @@ -1,191 +0,0 @@ -.. _nucleo_g070rb_board: - -ST Nucleo G070RB -################ - -Overview -******** -The Nucleo G070RB board features an ARM Cortex-M0+ based STM32G070RB MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo G070RB board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_g070rb.jpg - :align: center - :alt: Nucleo G070RB - -More information about the board can be found at the `Nucleo G070RB website`_. - -Hardware -******** -Nucleo G070RB provides the following hardware components: - -- STM32 microcontroller in LQFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD4), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32G070RB can be found here: - -- `G070RB on www.st.com`_ - -Supported Features -================== - -The Zephyr nucleo_g070rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | arm memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g070rb/nucleo_g070rb_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PC4/PC5 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PA11/PA12 -- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) -- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- USER_PB : PC13 -- LD4 : PA5 -- PWM : PA6 -- ADC1 IN0 : PA0 -- ADC1 IN1 : PA1 -- DAC1_OUT1 : PA4 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g070rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G070RB board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo G070RB ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_g070rb - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g070rb - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo G070RB website: - https://www.st.com/en/evaluation-tools/nucleo-g070rb.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00452640.pdf - -.. _G070RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32g070rb.html diff --git a/boards/arm/nucleo_g071rb/Kconfig.board b/boards/arm/nucleo_g071rb/Kconfig.board deleted file mode 100644 index 97a74c8dfc5..00000000000 --- a/boards/arm/nucleo_g071rb/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G071RB MCU configuration - -# Copyright (c) 2019 Philippe Retornaz -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G071RB - bool "NUCLEO-64 G071RB Development Board" - depends on SOC_STM32G071XX diff --git a/boards/arm/nucleo_g071rb/Kconfig.defconfig b/boards/arm/nucleo_g071rb/Kconfig.defconfig deleted file mode 100644 index 9333f392112..00000000000 --- a/boards/arm/nucleo_g071rb/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G071RB MCU - -# Copyright (c) 2019 Philippe Retornaz -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G071RB - -config BOARD - default "nucleo_g071rb" - -endif # BOARD_NUCLEO_G071RB diff --git a/boards/arm/nucleo_g071rb/doc/index.rst b/boards/arm/nucleo_g071rb/doc/index.rst deleted file mode 100644 index 424f1ade9f7..00000000000 --- a/boards/arm/nucleo_g071rb/doc/index.rst +++ /dev/null @@ -1,198 +0,0 @@ -.. _nucleo_g071rb_board: - -ST Nucleo G071RB -################ - -Overview -******** -The Nucleo G071RB board features an ARM Cortex-M0+ based STM32G071RB MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo G071RB board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_g071rb.jpg - :align: center - :alt: Nucleo G071RB - -More information about the board can be found at the `Nucleo G071RB website`_. - -Hardware -******** -Nucleo G071RB provides the following hardware components: - -- STM32 microcontroller in LQFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD4), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32G071RB can be found here: - -- `G071RB on www.st.com`_ -- `STM32G071 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_g071rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | arm memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PC4/PC5 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PA11/PA12 -- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) -- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- USER_PB : PC13 -- LD4 : PA5 -- PWM : PA6 -- ADC1 IN0 : PA0 -- ADC1 IN1 : PA1 -- DAC1_OUT1 : PA4 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g071rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G071RB board includes an ST-LINK/V3 embedded debug tool interface. - -Flashing an application to Nucleo G071RB ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_g071rb - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g071rb - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo G071RB website: - https://www.st.com/en/evaluation-tools/nucleo-g071rb.html - -.. _STM32G071 reference manual: - https://www.st.com/resource/en/reference_manual/dm00371828.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00452640.pdf - -.. _G071RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32g071rb.html diff --git a/boards/arm/nucleo_g0b1re/Kconfig.board b/boards/arm/nucleo_g0b1re/Kconfig.board deleted file mode 100644 index cce6734f45d..00000000000 --- a/boards/arm/nucleo_g0b1re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G0B1RE MCU configuration - -# Copyright (c) 2019 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G0B1RE - bool "NUCLEO-64 G0B1RE Development Board" - depends on SOC_STM32G0B1XX diff --git a/boards/arm/nucleo_g0b1re/Kconfig.defconfig b/boards/arm/nucleo_g0b1re/Kconfig.defconfig deleted file mode 100644 index 92a2c028d30..00000000000 --- a/boards/arm/nucleo_g0b1re/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G0B1RE MCU - -# Copyright (c) 2020 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G0B1RE - -config BOARD - default "nucleo_g0b1re" - -endif # BOARD_NUCLEO_G0B1RE diff --git a/boards/arm/nucleo_g0b1re/doc/index.rst b/boards/arm/nucleo_g0b1re/doc/index.rst deleted file mode 100644 index 9627b094fc0..00000000000 --- a/boards/arm/nucleo_g0b1re/doc/index.rst +++ /dev/null @@ -1,211 +0,0 @@ -.. _nucleo_g0b1re_board: - -ST Nucleo G0B1RE -################ - -Overview -******** -The Nucleo G0B1RE board features an ARM Cortex-M0+ based STM32G0B1RE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo G0B1RE board: - -- STM32 microcontroller in QFP64 package -- Board connectors: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5V_USB_STLK from ST-Link USB connector - - VIN (7 - 12V) from ARDUINO connector or ST morpho connector - - E5V from ST morpho connector - - 5V_USB_CHG from ST-LINK USB connector - - 3.3V on ARDUINO connector or ST morpho connector - -- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) -- Two push-buttons: USER and RESET -- 32.768 kHz crystal oscillator - -.. image:: img/nucleo_g0b1re.jpg - :align: center - :alt: Nucleo G0B1RE - -More information about the board can be found at the `Nucleo G0B1RE website`_. - -Hardware -******** -Nucleo G0B1RE provides the following hardware components: - -- STM32G0B1RE in LQFP64 package -- ARM 32-bit Cortex-M0+ CPU -- 64 MHz max CPU frequency -- Voltage range from 1.7 V to 3.6 V -- 512 KB Flash -- 144 kB SRAM -- 32-bit timers(1) -- 16-bit timers(11) -- watchdogs(2) -- systick(1) -- Calendar RTC with alarm and periodic wakeup -- I2C(3) -- USART(6) -- LPUART(2) -- 32 Mbit/s SPI(3) multiplexed with I2S(2) -- HDMI_CEC(1) -- USB 2.0 FS device (crystal-less) and host controller(1) -- USB Type-C Power Delivery controller -- CAN FD(2) -- GPIO (up to 94) with external interrupt capability -- Tamper Pins(3) -- 12-bit ADC with 16 channels -- 12-bit DAC with 2 channels(2) -- Analog Comparator(3) -- 12-channel DMA - - -More information about STM32G0B1RE can be found here: - -- `G0B1RE on www.st.com`_ -- `STM32G0B1 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_g0b1re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | arm memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ -| FDCAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g0b1re/nucleo_g0b1re_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PC4/PC5 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PA11/PA12 -- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) -- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- USER_PB : PC13 -- LD4 : PA5 -- PWM : PA6 -- ADC1 IN0 : PA0 -- ADC1 IN1 : PA1 -- DAC1_OUT1 : PA4 -- FDCAN1 RX/TX: PA11/PA12 -- FDCAN2 RX/TX: PB0/PB1 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g0b1re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G0B1RE board includes an ST-LINK/V2-1 embedded debug tool interface. - -This interface is not yet supported by the openocd version included in the Zephyr SDK. -But JLink, STM32CubeProgrammer and Pyocd interfaces are supported. -Pyocd support is currently limited: As the stm32g0b1 target causes issues, -the stm32g071 target is used. For STM32G0 support pyocd needs additional target -information, which can be installed by adding "pack" support with the -following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32g0 - - -Flashing an application to Nucleo G0B1RE ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_g0b1re - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g0b1re - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo G0B1RE website: - https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html - -.. _STM32G0B1 reference manual: - https://www.st.com/resource/en/reference_manual/dm00371828.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00452640.pdf - -.. _G0B1RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32g0b1re.html diff --git a/boards/arm/nucleo_g431rb/Kconfig.board b/boards/arm/nucleo_g431rb/Kconfig.board deleted file mode 100644 index 27de2edbdad..00000000000 --- a/boards/arm/nucleo_g431rb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32G431RB Nucleo board configuration - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G431RB - bool "Nucleo G431RB Development Board" - depends on SOC_STM32G431XX diff --git a/boards/arm/nucleo_g431rb/Kconfig.defconfig b/boards/arm/nucleo_g431rb/Kconfig.defconfig deleted file mode 100644 index 62c8e061965..00000000000 --- a/boards/arm/nucleo_g431rb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32G431RB Nucleo board configuration - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G431RB - -config BOARD - default "nucleo_g431rb" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_G431RB diff --git a/boards/arm/nucleo_g431rb/doc/index.rst b/boards/arm/nucleo_g431rb/doc/index.rst deleted file mode 100644 index 0359a29b231..00000000000 --- a/boards/arm/nucleo_g431rb/doc/index.rst +++ /dev/null @@ -1,263 +0,0 @@ -.. _nucleo_g431rb_board: - -ST Nucleo G431RB -################ - -Overview -******** - -The Nucleo G431RB board features an ARM Cortex-M4 based STM32G431RB MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo G431RB board: - -- STM32 microcontroller in LQFP64 package -- Arduino Uno V3 connectivity -- On-board ST-LINK/V3E debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD2) -- Two push-buttons: RESET and USER - -.. image:: img/nucleo_g431rb.jpg - :align: center - :alt: Nucleo G431RB - -More information about the board can be found at the `Nucleo G431RB website`_. - -Hardware -******** - -The STM32G431RB SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 170 MHz -- Clock Sources: - - - 4 to 48 MHz crystal oscillator (HSE) - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - 2 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- 14x timers: - - - 1x 32-bit timer and 2x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - - 2x 16-bit 8-channel advanced motor control timers, with up to 8x PWM channels, dead time generation and emergency stop - - 1x 16-bit timer with 2x IC/OCs, one OCN/PWM, dead time generation and emergency stop - - 2x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop - - 2x watchdog timers (independent, window) - - 2x 16-bit basic timers - - SysTick timer - - 1x low-power timer - -- Up to 86 fast I/Os, most 5 V-tolerant -- Memories - - - Up to 128 KB single bank Flash, proprietary code readout protection - - Up to 22 KB of SRAM including 16 KB with hardware parity check - -- Rich analog peripherals (independent supply) - - - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 4x 12-bit DAC, low-power sample and hold - - 3x operational amplifiers with built-in PGA - - 4x ultra-fast rail-to-rail analog comparators - -- 16x communication interfaces - - - 1 x FDCAN controller supporting flexible data rate - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART - - 3x SPIs (2x with multiplexed half duplex I2S interface) - - 1x SAI (serial audio interface) - - USB 2.0 full-speed interface with LPM and BCD support - - IRTIM (Infrared interface) - - USB Type-C™ /USB power delivery controller (UCPD) - -- 12-channel DMA controller -- True random number generator (RNG) -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32G431RB can be found here: - -- `STM32G431RB on www.st.com`_ -- `STM32G4 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_g431rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | rng | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig`` - - -Connections and IOs -=================== - -Nucleo G431RB Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32G4 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PC4 -- UART_1_RX : PC5 -- LPUART_1_TX : PA2 -- LPUART_1_RX : PA3 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB9 -- SPI_1_NSS : PB6 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- SPI_2_NSS : PB12 -- SPI_2_SCK : PB13 -- SPI_2_MISO : PB14 -- SPI_2_MOSI : PB15 -- SPI_3_NSS : PA15 -- SPI_3_SCK : PC10 -- SPI_3_MISO : PC11 -- SPI_3_MOSI : PC12 -- PWM_3_CH1 : PB4 -- USER_PB : PC13 -- LD2 : PA5 -- DAC1_OUT1 : PA4 - -System Clock ------------- - -Nucleo G431RB System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 150MHz, -driven by 16MHz high speed internal oscillator. The clock can be boosted to 170MHz if boost mode -is selected. - -Serial Port ------------ - -Nucleo G431RB board has 3 U(S)ARTs and one LPUART. The Zephyr console output is assigned to LPUART1. -Default settings are 115200 8N1. - -Please note that LPUART1 baudrate is limited to 9600 if the MCU is clocked by LSE (32.768 kHz) in -low power mode. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g431rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G431RB board includes an ST-LINK/V3E embedded debug tool interface. - -This interface is not yet supported by the openocd version included in the Zephyr SDK. - -Instead, support can be enabled on pyocd by adding "pack" support with -the following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32g431rb - -Note: -To manually enable the openocd interface, You can still update, compile and install -a 'local' openocd from the official openocd repo http://openocd.zylin.com . -Then run the following openocd command where the '/usr/local/bin/openocd'is your path -for the freshly installed openocd, given by "$ which openocd" : - -.. code-block:: console - - $ west flash --openocd /usr/local/bin/openocd - -Flashing an application to Nucleo G431RB ----------------------------------------- - -Connect the Nucleo G431RB to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g431rb - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g431rb - :maybe-skip-config: - :goals: debug - -.. _Nucleo G431RB website: - https://www.st.com/en/evaluation-tools/nucleo-g431rb.html - -.. _STM32G4 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00556337.pdf - -.. _STM32G431RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32g431rb.html - -.. _STM32G4 reference manual: - https://www.st.com/resource/en/reference_manual/dm00355726.pdf diff --git a/boards/arm/nucleo_g474re/Kconfig.board b/boards/arm/nucleo_g474re/Kconfig.board deleted file mode 100644 index 157e93af1ec..00000000000 --- a/boards/arm/nucleo_g474re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32G474RE Nucleo board configuration - -# Copyright (c) 2019 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G474RE - bool "Nucleo G474RE Development Board" - depends on SOC_STM32G474XX diff --git a/boards/arm/nucleo_g474re/Kconfig.defconfig b/boards/arm/nucleo_g474re/Kconfig.defconfig deleted file mode 100644 index 5af458d2262..00000000000 --- a/boards/arm/nucleo_g474re/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32G474RE Nucleo board configuration - -# Copyright (c) 2019 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G474RE - -config BOARD - default "nucleo_g474re" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_G431RB diff --git a/boards/arm/nucleo_g474re/doc/index.rst b/boards/arm/nucleo_g474re/doc/index.rst deleted file mode 100644 index 87fca388905..00000000000 --- a/boards/arm/nucleo_g474re/doc/index.rst +++ /dev/null @@ -1,255 +0,0 @@ -.. _nucleo_g474re_board: - -ST Nucleo G474RE -################ - -Overview -******** - -The Nucleo G474RE board features an ARM Cortex-M4 based STM32G474RE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo G474RE board: - -- STM32 microcontroller in LQFP64 package -- Arduino Uno V3 connectivity -- On-board ST-LINK/V3E debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD2) -- Two push-buttons: RESET and USER - -.. image:: img/nucleo_g474re.jpg - :align: center - :alt: Nucleo G474RE - -More information about the board can be found at the `Nucleo G474RE website`_. - -Hardware -******** - -The STM32G474RE SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 170 MHz -- Clock Sources: - - - 4 to 48 MHz crystal oscillator (HSE) - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - 2 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- 14x timers: - - - 1x 32-bit timer and 2x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - - 2x 16-bit 8-channel advanced motor control timers, with up to 8x PWM channels, dead time generation and emergency stop - - 1x 16-bit timer with 2x IC/OCs, one OCN/PWM, dead time generation and emergency stop - - 2x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop - - 2x watchdog timers (independent, window) - - 2x 16-bit basic timers - - SysTick timer - - 1x low-power timer - -- Up to 86 fast I/Os, most 5 V-tolerant -- Memories - - - Up to 128 KB single bank Flash, proprietary code readout protection - - Up to 22 KB of SRAM including 16 KB with hardware parity check - -- Rich analog peripherals (independent supply) - - - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 4x 12-bit DAC, low-power sample and hold - - 3x operational amplifiers with built-in PGA - - 4x ultra-fast rail-to-rail analog comparators - -- 16x communication interfaces - - - 1 x FDCAN controller supporting flexible data rate - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART - - 3x SPIs (2x with multiplexed half duplex I2S interface) - - 1x SAI (serial audio interface) - - USB 2.0 full-speed interface with LPM and BCD support - - IRTIM (Infrared interface) - - USB Type-C™ /USB power delivery controller (UCPD) - -- 12-channel DMA controller -- True random number generator (RNG) -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32G474RE can be found here: - -- `STM32G474RE on www.st.com`_ -- `STM32G4 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_g474re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ -| FDCAN1 | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g474re/nucleo_g474re_defconfig`` - - -Connections and IOs -=================== - -Nucleo G474RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32G4 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PC4 -- UART_1_RX : PC5 -- LPUART_1_TX : PA2 -- LPUART_1_RX : PA3 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB9 -- SPI_1_NSS : PB6 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- SPI_2_NSS : PB12 -- SPI_2_SCK : PB13 -- SPI_2_MISO : PB14 -- SPI_2_MOSI : PB15 -- SPI_3_NSS : PA15 -- SPI_3_SCK : PC10 -- SPI_3_MISO : PC11 -- SPI_3_MOSI : PC12 -- PWM_2_CH1 : PA5 (might conflict with SPI1) -- PWM_3_CH1 : PB4 -- USER_PB : PC13 -- LD2 : PA5 -- ADC1_IN1 : PA0 -- DAC1_OUT1 : PA4 -- FDCAN1_RX: PA11 -- FDCAN1_TX: PA12 - -System Clock ------------- - -Nucleo G474RE System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 150MHz, -driven by 16MHz high speed internal oscillator. The clock can be boosted to 170MHz if boost mode -is selected. - -Serial Port ------------ - -Nucleo G474RE board has 3 U(S)ARTs. The Zephyr console output is assigned to LPUART1. -Default settings are 115200 8N1. - -Please note that LPUART1 baudrate is limited to 9600 if the MCU is clocked by LSE (32.768 kHz) in -low power mode. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g474re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G474RE board includes an ST-LINK/V3E embedded debug tool interface. - -Flashing an application to Nucleo G474RE ----------------------------------------- - -Connect the Nucleo G474RE to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g474re - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g474re - :maybe-skip-config: - :goals: debug - -.. _Nucleo G474RE website: - https://www.st.com/en/evaluation-tools/nucleo-g474re.html - -.. _STM32G4 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00556337.pdf - -.. _STM32G474RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32g474re.html - -.. _STM32G4 reference manual: - https://www.st.com/resource/en/reference_manual/dm00355726.pdf diff --git a/boards/arm/nucleo_h563zi/Kconfig.board b/boards/arm/nucleo_h563zi/Kconfig.board deleted file mode 100644 index debcb2a4ab8..00000000000 --- a/boards/arm/nucleo_h563zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H563ZI Nucleo board configuration - -# Copyright (c) 2023 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H563ZI - bool "Nucleo H563ZI Development Board" - depends on SOC_STM32H563XX diff --git a/boards/arm/nucleo_h563zi/Kconfig.defconfig b/boards/arm/nucleo_h563zi/Kconfig.defconfig deleted file mode 100644 index 4730fdb7a79..00000000000 --- a/boards/arm/nucleo_h563zi/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32H563ZI Nucleo board configuration - -# Copyright (c) 2023 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H563ZI - -config BOARD - default "nucleo_h563zi" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_H563ZI diff --git a/boards/arm/nucleo_h563zi/doc/index.rst b/boards/arm/nucleo_h563zi/doc/index.rst deleted file mode 100644 index 7d1ac5c5b5a..00000000000 --- a/boards/arm/nucleo_h563zi/doc/index.rst +++ /dev/null @@ -1,317 +0,0 @@ -.. _nucleo_h563zi_board: - -ST Nucleo H563ZI -################ - -Overview -******** - -The Nucleo H563ZI board is designed as an affordable development platform for -STMicroelectronics ARM |reg| Cortex |reg|-M33 core-based STM32H563ZIT6 -microcontroller with TrustZone |reg|. -Here are some highlights of the Nucleo H563ZI board: - -- STM32H563ZI microcontroller featuring 2 Mbytes of Flash memory and 640Kbyte of - SRAM in LQFP144 package -- Board connectors: - - - USB Type-C |trade| Sink device FS - - Ethernet RJ45 connector compliant with IEEE-802.3-2002 (depending on STM32 support) - - ST Zio expansion connector including Arduino Uno V3 connectivity (CN7, CN8, CN9, CN10) - - ST morpho extension connector (CN11, CN12) - -- Flexible board power supply: - - - 5V_USB_STLK from ST-Link USB connector - - VIN (7 - 12V, 0.8A) supplied via pin header CN8 pin 15 or CN11 pin 24 - - 5V_EXT on the ST morpho connector CN11 Pin 6 (5V, 1.3) - - CHGR from a USB charger via the ST-LINK USB connector - - USB_USER from the USB user connector (5V, 3A) - - 3V3_EXT supplied via a pin header CN8 pin 7 or CN11 pin 16 (3.3V, 1.3A) - -- On-board ST-LINK/V3EC debugger/programmer - - - mass storage - - Virtual COM port - - debug port - -- Three users LEDs -- Two push-buttons: USER and RESET -- 32.789 kHz crystal oscillator - -More information about the board can be found at the `NUCLEO_H563ZI website`_. - -.. image:: img/nucleo_h563zi.jpg - :align: center - :alt: NUCLEO H563ZI - -Hardware -******** - -The STM32H563xx devices are high-performance microcontrollers from the STM32H5 -Series based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. -They operate at a frequency of up to 250 MHz. - -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 375 DMPIS/MHz (Dhrystone 2.1) - -- Security - - - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension - - Up to 8 configurable SAU regions - - TrustZone |reg| aware and securable peripherals - - Flexible lifecycle scheme with secure debug authentication - - SFI (secure firmware installation) - - Secure firmware upgrade support with TF-M - - HASH hardware accelerator - - True random number generator, NIST SP800-90B compliant - - 96-bit unique ID - - Active tampers - -- Clock management: - - - 25 MHz crystal oscillator (HSE) - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 64 MHz (HSI) trimmable by software - - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) - - Internal 4 MHz oscillator (CSI), trimmable by software - - Internal 48 MHz (HSI48) with recovery system - - 3 PLLs for system clock, USB, audio, ADC - -- Power management - - - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry - - Embedded SMPS step-down converter - -- RTC with HW calendar, alarms and calibration -- Up to 139 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V -- Up to 16 timers and 2 watchdogs - - - 12x 16-bit - - 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - - 6x 16-bit low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- Memories - - - Up to 2 MB Flash, 2 banks read-while-write - - 1 Kbyte OTP (one-time programmable) - - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC - - 4 Kbytes of backup SRAM available in the lowest power modes - - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories - - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats - - 2x SD/SDIO/MMC interfaces - -- Rich analog peripherals (independent supply) - - - 2x 12-bit ADC with up to 5 MSPS in 12-bit - - 1x 12-bit D/A with 2 channels - - 1x Digital temperature sensor - -- 34x communication interfaces - - - 1x USB Type-C / USB power-delivery controller - - 1x USB 2.0 full-speed host and device - - 4x I2C FM+ interfaces (SMBus/PMBus) - - 1x I3C interface - - 12x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) - - 1x LP UART - - 6x SPIs including 3 muxed with full-duplex I2S - - 5x additional SPI from 5x USART when configured in Synchronous mode - - 2x SAI - - 2x FDCAN - - 1x SDMMC interface - - 2x 16 channel DMA controllers - - 1x 8- to 14- bit camera interface - - 1x HDMI-CEC - - 1x Ethernel MAC interface with DMA controller - - 1x 16-bit parallel slave synchronous-interface - -- CORDIC for trigonometric functions acceleration -- FMAC (filter mathematical accelerator) -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - -More information about STM32H563ZI can be found here: - -- `STM32H563ZI on www.st.com`_ -- `STM32H563 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_h563zi board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | Real Time Clock | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi bus | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB full-speed host/device bus | -+-----------+------------+-------------------------------------+ - - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig and dts files: - -- Secure target: - - - :zephyr_file:`boards/arm/nucleo_h563zi/nucleo_h563zi_defconfig` - - :zephyr_file:`boards/arm/nucleo_h563zi/nucleo_h563zi.dts` - -Zephyr board options -==================== - -The STM32H563 is an SoC with Cortex-M33 architecture. Zephyr provides support -for building for Secure firmware. - -The BOARD options are summarized below: - -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| nucleo_h563zi | For building Secure firmware | -+----------------------+-----------------------------------------------+ - -Connections and IOs -=================== - -Nucleo H563ZI Board has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32H5 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- ADC1 channel 3 input: PA6 -- ADC1 channel 15 input: PA3 -- DAC1 channel 2 output: PA5 -- LD1 (green): PB0 -- LD2 (yellow): PF4 -- LD3 (red): PG4 -- LPUART1 TX/RX : PB6/PB7 (Arduino LPUART1) -- SPI1 SCK/MISO/MOSI/CS: PA5/PG9/PB5/PD14 -- UART3 TX/RX : PD8/PD9 (VCP) -- USER_PB : PC13 - -System Clock ------------- - -Nucleo H563ZI System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at -240MHz, driven by 8MHz external clock provided from the STLINK-V3EC. - -Serial Port ------------ - -Nucleo H563ZI board has up to 12 U(S)ARTs. The Zephyr console output is assigned -to USART3. Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``nucleo_h563zi`` board can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo H563ZI board includes an ST-LINK/V3EC embedded debug tool interface. -This probe allows to flash the board using various tools. - -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. - -Alternatively, pyocd or jlink via an external probe can also be used to flash -and debug the board if west is told to use it as runner, which can be done by -passing either or ``-r pyocd``, or ``-r jlink``. - -For pyocd additional target information needs to be installed. -This can be done by executing the following commands. - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32h5 - - -Flashing an application to Nucleo H563ZI ------------------------------------------- - -Connect the Nucleo H563ZI to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h563zi - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! nucleo_h563zi - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_h563zi - :goals: debug - -.. _NUCLEO_H563ZI website: - https://www.st.com/en/evaluation-tools/nucleo-h563zi - -.. _STM32H5 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/um3115-stm32h5-nucleo144-board-mb1404-stmicroelectronics.pdf - -.. _STM32H563ZI on www.st.com: - https://www.st.com/en/microcontrollers/stm32h563zi.html - -.. _STM32H563 reference manual: - https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/nucleo_h723zg/Kconfig.board b/boards/arm/nucleo_h723zg/Kconfig.board deleted file mode 100644 index da658f90c6d..00000000000 --- a/boards/arm/nucleo_h723zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H723ZG Nucleo board configuration - -# Copyright (c) 2020 Alexander Kozhinov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H723ZG - bool "NUCLEO-H723ZG Development Board" - depends on SOC_STM32H723XX diff --git a/boards/arm/nucleo_h723zg/Kconfig.defconfig b/boards/arm/nucleo_h723zg/Kconfig.defconfig deleted file mode 100644 index 26f4491a7ad..00000000000 --- a/boards/arm/nucleo_h723zg/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# STM32H723ZG Nucleo board configuration - -# Copyright (c) 2020 Alexander Kozhinov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H723ZG - -config BOARD - default "nucleo_h723zg" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -config USB_DC_HAS_HS_SUPPORT - default y - depends on USB_DC_STM32 - -endif # BOARD_NUCLEO_H723ZG diff --git a/boards/arm/nucleo_h723zg/doc/index.rst b/boards/arm/nucleo_h723zg/doc/index.rst deleted file mode 100644 index 44a87bb5129..00000000000 --- a/boards/arm/nucleo_h723zg/doc/index.rst +++ /dev/null @@ -1,248 +0,0 @@ -.. _nucleo_h723zg_board: - -ST Nucleo H723ZG -################ - -Overview -******** - -The STM32 Nucleo-144 board provides an affordable and flexible way for users -to try out new concepts and build prototypes by choosing from the various combinations -of performance and power consumption features, provided by the STM32 microcontroller. -For the compatible boards, the internal or external SMPS significantly reduces power -consumption in Run mode. - -The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and -the ST morpho headers provide an easy means of expanding the functionality of the Nucleo -open development platform with a wide choice of specialized shields. -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK V3 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - Ethernet RJ45 (depending on STM32 support) - - SWDST Zio connector including Arduino* Uno V3ST - - ST morpho expansion - -- Flexible power-supply options: ST-LINK USB VBUS or external sources -- External or internal SMPS to generate Vcore logic supply -- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port -- USB OTG full speed or device only - -.. image:: img/nucleo_h723zg.jpg - :align: center - :alt: Nucleo H723ZG - -More information about the board can be found at the `Nucleo H723ZG website`_. - -Hardware -******** - -Nucleo H723ZG provides the following hardware components: - -- STM32H723ZG in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- Hardware JPEG Codec -- 550 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 1 MB Flash -- 562 kB SRAM max (376 kb used currently) -- High-resolution timer (2.1 ns) -- 32-bit timers(2) -- 16-bit timers(12) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN FD(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO (up to 114) with external interrupt capability -- 16-bit ADC(3) with 36 channels / 3.6 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_h723zg board configuration supports the following hardware -features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-------------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration per core can be found in the defconfig files: -``boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo H723ZG board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- I2C : PB8, PB9 -- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) - -System Clock ------------- - -Nucleo H723ZG System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 550MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo H723ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB52`` jumper on the back side of the board. - -Programming and Debugging -************************* - -Currently the ``nucleo_h723zg`` board supports stm32cubeprogrammer (default), OpenOCD and J-Link debuggers. - -.. note:: - - Official OpenOCD support for this board was added on October '20. - Make sure your openocd version is older than that. - Following links may be helpful: `OpenOCD installing Debug Version`_ - and `OpenOCD installing with ST-LINK V3 support`_ - -.. note:: - - Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeIDE`_ - -Flashing -======== - -Nucleo H723ZG board includes an ST-LINK/V3 embedded debug tool interface. - -First, connect the NUCLEO-H723ZG to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your NUCLEO-H723ZG board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -or use screen: - -.. code-block:: console - - $ screen /dev/ttyACM0 115200 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h723zg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_h723zg - -Blinky example can also be used: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_h723zg - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h723zg - :maybe-skip-config: - :goals: debug - -.. _Nucleo H723ZG website: - https://www.st.com/en/evaluation-tools/nucleo-h723zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00499160-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf - -.. _STM32H723ZG on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h723zg.html - -.. _STM32H723 reference manual: - https://www.st.com/resource/en/reference_manual/dm00603761-stm32h723733-stm32h725735-and-stm32h730-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _OpenOCD installing Debug Version: - https://github.com/zephyrproject-rtos/openocd - -.. _OpenOCD installing with ST-LINK V3 support: - https://mbd.kleier.net/integrating-st-link-v3.html - -.. _STM32CubeIDE: - https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/nucleo_h743zi/Kconfig.board b/boards/arm/nucleo_h743zi/Kconfig.board deleted file mode 100644 index 9417b98e670..00000000000 --- a/boards/arm/nucleo_h743zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H743ZI Nucleo board configuration - -# Copyright (c) 2020 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H743ZI - bool "Nucleo H743ZI Development Board" - depends on SOC_STM32H743XX diff --git a/boards/arm/nucleo_h743zi/Kconfig.defconfig b/boards/arm/nucleo_h743zi/Kconfig.defconfig deleted file mode 100644 index e426be48d7f..00000000000 --- a/boards/arm/nucleo_h743zi/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32H743ZI Nucleo board configuration - -# Copyright (c) 2020 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H743ZI - -config BOARD - default "nucleo_h743zi" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_H743ZI diff --git a/boards/arm/nucleo_h743zi/doc/index.rst b/boards/arm/nucleo_h743zi/doc/index.rst deleted file mode 100644 index e6cb6e242cd..00000000000 --- a/boards/arm/nucleo_h743zi/doc/index.rst +++ /dev/null @@ -1,246 +0,0 @@ -.. _nucleo_h743zi_board: - -ST Nucleo H743ZI -################ - -Overview -******** - -The STM32 Nucleo-144 boards offer combinations of performance and power that -provide an affordable and flexible way for users to build prototypes and try -out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) -significantly reduces power consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V2-1 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - Ethernet RJ45 (depending on STM32 support) - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_h743zi.jpg - :align: center - :alt: Nucleo H743ZI - -More information about the board can be found at the `Nucleo H743ZI website`_. - -Hardware -******** - -Nucleo H743ZI provides the following hardware components: - -- STM32H743ZI in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- Hardware JPEG Codec -- 480 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 2 MB Flash -- 1 MB SRAM -- High-resolution timer (2.1 ns) -- 32-bit timers(2) -- 16-bit timers(12) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN FD(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO (up to 114) with external interrupt capability -- 16-bit ADC(3) with 36 channels / 3.6 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_h743zi board configuration supports the following hardware -features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-------------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-------------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-------------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-------------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-------------+------------+-------------------------------------+ -| CAN/CANFD | on-chip | canbus | -+-------------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_h743zi/nucleo_h743zi_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo H743ZI board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- I2C : PB8, PB9 -- ADC1_INP15 : PA3 -- DAC1_OUT1 : PA4 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PB5 (Arduino SPI) -- CAN/CANFD : PD0, PD1 - -System Clock ------------- - -Nucleo H743ZI System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo H743ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB156`` jumper on the back side of the board. - -CAN, CANFD ----------- - -Requires an external CAN or CANFD transceiver. - -Programming and Debugging -************************* - -Applications for the ``nucleo_h743zi`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. note:: - - If using OpenOCD you will need a recent development version as the last - official release does not support H7 series yet. You can also choose the - ``stm32cubeprogrammer`` runner. - -Flashing -======== - -Nucleo H743ZI board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo H743ZI ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h743zi - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_h743zi - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h743zi - :maybe-skip-config: - :goals: debug - -.. _Nucleo H743ZI website: - https://www.st.com/en/evaluation-tools/nucleo-h743zi.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32H743ZI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h743-753/stm32h743zi.html - -.. _STM32H743 reference manual: - https://www.st.com/resource/en/reference_manual/dm00314099.pdf diff --git a/boards/arm/nucleo_h745zi_q/Kconfig.board b/boards/arm/nucleo_h745zi_q/Kconfig.board deleted file mode 100644 index 0b5c5728610..00000000000 --- a/boards/arm/nucleo_h745zi_q/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# STM32H745ZI Nucleo board configuration - -# Copyright (c) 2020 Alexander Kozhinov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H745ZI_Q_M7 - bool "NUCLEO-H745ZI-Q Development Board" - depends on SOC_STM32H745XX - select CPU_CORTEX_M7 - -config BOARD_NUCLEO_H745ZI_Q_M4 - bool "NUCLEO-H745ZI-Q Development Board" - depends on SOC_STM32H745XX - select CPU_CORTEX_M4 diff --git a/boards/arm/nucleo_h745zi_q/Kconfig.defconfig b/boards/arm/nucleo_h745zi_q/Kconfig.defconfig deleted file mode 100644 index 0d7f628f8ac..00000000000 --- a/boards/arm/nucleo_h745zi_q/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# STM32H745ZI Nucleo board configuration - -# Copyright (c) 2020 Alexander Kozhinov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H745ZI_Q_M7 || BOARD_NUCLEO_H745ZI_Q_M4 - -config BOARD - default "nucleo_h745zi_q_m7" if BOARD_NUCLEO_H745ZI_Q_M7 - default "nucleo_h745zi_q_m4" if BOARD_NUCLEO_H745ZI_Q_M4 - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_H745ZI_Q_M7 or BOARD_NUCLEO_H745ZI_Q_M4 diff --git a/boards/arm/nucleo_h745zi_q/board.cmake b/boards/arm/nucleo_h745zi_q/board.cmake deleted file mode 100644 index b5ca36713e8..00000000000 --- a/boards/arm/nucleo_h745zi_q/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=STM32H745ZI" "--speed=4000") -if(CONFIG_BOARD_NUCLEO_H745ZI_Q_M7) -board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) -elseif(CONFIG_BOARD_NUCLEO_H745ZI_Q_M4) -board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) -endif() - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/nucleo_h745zi_q/doc/index.rst b/boards/arm/nucleo_h745zi_q/doc/index.rst deleted file mode 100644 index 36c4b80bc58..00000000000 --- a/boards/arm/nucleo_h745zi_q/doc/index.rst +++ /dev/null @@ -1,290 +0,0 @@ -.. _nucleo_h745zi_q_board: - -ST Nucleo H745ZI-Q -################### - -Overview -******** - -The STM32 Nucleo-144 board provides an affordable and flexible way for users -to try out new concepts and build prototypes by choosing from the various combinations -of performance and power consumption features, provided by the STM32 microcontroller. -For the compatible boards, the internal or external SMPS significantly reduces power -consumption in Run mode. - -The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and -the ST morpho headers provide an easy means of expanding the functionality of the Nucleo -open development platform with a wide choice of specialized shields. -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK V3 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - Ethernet RJ45 (depending on STM32 support) - - SWDST Zio connector including Arduino* Uno V3ST - - ST morpho expansion - -- Flexible power-supply options: ST-LINK USB VBUS or external sources -- External or internal SMPS to generate Vcore logic supply -- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port -- USB OTG full speed or device only -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_h745zi_q.jpg - :align: center - :alt: Nucleo H745ZI-Q - -More information about the board can be found at the `Nucleo H745ZI-Q website`_. - -Hardware -******** - -Nucleo H745ZI-Q provides the following hardware components: - -- STM32H745ZI in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- ARM 32-bit Cortex-M4 CPU with FPU -- Chrom-ART Accelerator -- Hardware JPEG Codec -- 480 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 2 MB Flash -- 1 MB SRAM -- High-resolution timer (2.1 ns) -- 32-bit timers(2) -- 16-bit timers(12) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN FD(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO (up to 114) with external interrupt capability -- 16-bit ADC(3) with 36 channels / 3.6 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_h745zi_q board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration per core can be found in the defconfig files: -``boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7_defconfig`` and -``boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo H745ZI board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- I2C : PB8, PB9 - -System Clock ------------- - -Nucleo H745ZI-Q System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 480MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo H745ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - -Resources sharing ------------------ - -The dual core nature of STM32H745 SoC requires sharing HW resources between the -two cores. This is done in 3 ways: - -- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only - has access to bus clock activation and deactivation. -- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in - devicetree before compilation. The user must ensure peripherals are not assigned - to both cores at the same time. -- **Run time protection**: Interrupt-controller and GPIO configurations could be - accessed by both cores at run time. Accesses are protected by a hardware semaphore - to avoid potential concurrent access issues. - -Programming and Debugging -************************* - -Applications for the ``nucleo_h745zi_q`` board should be built per core target, -using either ``nucleo_h745zi_q_m7`` or ```nucleo_h745zi_q_m4`` as the target -(see :ref:`build_an_application` and :ref:`application_run` for more details). - -.. note:: - - If using OpenOCD you will need a recent development version as the last - official release does not support H7 series and ST-LINK V3 yet. - Following links may be helpful: `OpenOCD installing Debug Version`_ - and `OpenOCD installing with ST-LINK V3 support`_ - -.. note:: - - Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeIDE`_ - -Flashing -======== - -Nucleo H745ZI-Q board includes an ST-LINK/V3 embedded debug tool interface. - -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. - -By default: - - - CPU0 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0) - - CPU1 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0) - -Also, default out of the box board configuration enables CM7 and CM4 boot when -board is powered (Option bytes BCM7 and BCM4 are checked). -In that configuration, Kconfig boot option ``STM32H7_BOOT_CM4_CM7`` should be selected. -Zephyr flash configuration has been set to meet these default settings. - -Flashing an application to STM32H745ZI M7 Core ----------------------------------------------- -First, connect the NUCLEO-H745ZI-Q to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your NUCLEO-H745ZI-Q board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -or use screen: - -.. code-block:: console - - $ screen /dev/ttyACM0 115200 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h745zi_q_m7 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_h745zi_q_m7 - -.. note:: - Sometimes, flashing is not working. It is necessary to erase the flash - (with STM32CubeProgrammer for example) to make it work again. - -Similarly, you can build and flash samples on the M4 target. For this, please -take care of the resource sharing (UART port used for console for instance). - -Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_h745zi_q_m4 - :goals: build flash - -.. note:: - - Flashing both M4 and M7 and pushing RESTART button on the board leads - to LD1 and LD2 flashing simultaneously. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h745zi_q_m7 - :maybe-skip-config: - :goals: debug - -Debugging with west is currently not available on Cortex M4 side. -In order to debug a Zephyr application on Cortex M4 side, you can use -`STM32CubeIDE`_. - -.. _Nucleo H745ZI-Q website: - https://www.st.com/en/evaluation-tools/nucleo-h745zi-q.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00499171-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf - -.. _STM32H745ZI on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h745zi.html - -.. _STM32H745 reference manual: - https://www.st.com/resource/en/reference_manual/dm00176879-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _OpenOCD installing Debug Version: - https://github.com/zephyrproject-rtos/openocd - -.. _OpenOCD installing with ST-LINK V3 support: - https://mbd.kleier.net/integrating-st-link-v3.html - -.. _STM32CubeIDE: - https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.yaml b/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.yaml deleted file mode 100644 index 3299fb78496..00000000000 --- a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: nucleo_h745zi_q_m4 -name: ST Nucleo H745ZI-Q (M4) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 288 -flash: 1024 -supported: - - arduino_gpio - - gpio - - netif:eth -testing: - ignore_tags: - - mpu - - nfc -vendor: st diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4_defconfig b/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4_defconfig deleted file mode 100644 index b6233762bbd..00000000000 --- a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H745XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_NUCLEO_H745ZI_Q_M4=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable clock -CONFIG_CLOCK_CONTROL=y - -# By default SERIAL peripherals are assigned to m7 - -# Enable uart driver -#CONFIG_SERIAL=y - -# Console -#CONFIG_CONSOLE=y -#CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.yaml b/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.yaml deleted file mode 100644 index 8c124a0a906..00000000000 --- a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: nucleo_h745zi_q_m7 -name: ST Nucleo H745ZI-Q (M7) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 512 -flash: 1024 -supported: - - arduino_gpio - - arduino_i2c - - uart - - gpio - - counter - - i2c - - pwm - - netif:eth -vendor: st diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7_defconfig b/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7_defconfig deleted file mode 100644 index d57388f06ad..00000000000 --- a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H745XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_NUCLEO_H745ZI_Q_M7=y - -# Enable the internal SMPS regulator -CONFIG_POWER_SUPPLY_DIRECT_SMPS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable UART ( disable to assign to M4 core) -CONFIG_SERIAL=y - -# Console ( disable to assign to M4 core) -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable Clock -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_h753zi/Kconfig.board b/boards/arm/nucleo_h753zi/Kconfig.board deleted file mode 100644 index 15d573da300..00000000000 --- a/boards/arm/nucleo_h753zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H753ZI Nucleo board configuration - -# Copyright (c) 2021 Blue Clover Devices -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H753ZI - bool "Nucleo H753ZI Development Board" - depends on SOC_STM32H753XX diff --git a/boards/arm/nucleo_h753zi/Kconfig.defconfig b/boards/arm/nucleo_h753zi/Kconfig.defconfig deleted file mode 100644 index 60abed56e42..00000000000 --- a/boards/arm/nucleo_h753zi/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32H753ZI Nucleo board configuration - -# Copyright (c) 2021 Blue Clover Devices -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H753ZI - -config BOARD - default "nucleo_h753zi" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_H753ZI diff --git a/boards/arm/nucleo_h753zi/doc/index.rst b/boards/arm/nucleo_h753zi/doc/index.rst deleted file mode 100644 index eab88c9952a..00000000000 --- a/boards/arm/nucleo_h753zi/doc/index.rst +++ /dev/null @@ -1,233 +0,0 @@ -.. _nucleo_h753zi_board: - -ST Nucleo H753ZI -################ - -Overview -******** - -The STM32 Nucleo-144 boards offer combinations of performance and power that -provide an affordable and flexible way for users to build prototypes and try -out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) -significantly reduces power consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V2-1 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - Ethernet RJ45 (depending on STM32 support) - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_h753zi.jpg - :align: center - :alt: Nucleo H753ZI - -More information about the board can be found at the `Nucleo H753ZI website`_. - -Hardware -******** - -Nucleo H753ZI provides the following hardware components: - -- STM32H753ZI in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- Hardware JPEG Codec -- 480 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 2 MB Flash -- 1 MB SRAM -- High-resolution timer (2.1 ns) -- 32-bit timers(2) -- 16-bit timers(12) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN FD(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO (up to 114) with external interrupt capability -- 16-bit ADC(3) with 36 channels / 3.6 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution -- Cryptographic acceleration: AES 128, 192, 256, TDES, HASH (MD5, SHA-1, SHA-2), HMAC -- Secure firmware upgrade support, Secure access mode - -Supported Features -================== - -The Zephyr nucleo_h753zi board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-----------+------------+-------------------------------------+ -| CAN/CANFD | on-chip | canbus | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_h753zi/nucleo_h753zi_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo H753ZI board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- I2C : PB8, PB9 -- ADC1_INP15 : PA3 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) -- CAN/CANFD : PD0, PD1 - -System Clock ------------- - -Nucleo H753ZI System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo H753ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - -CAN, CANFD ----------- - -Requires an external CAN or CANFD transceiver. - -Programming and Debugging -************************* - -Applications for the ``nucleo_h753zi`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. note:: - - If using OpenOCD you will need a recent development version as the last - official release does not support H7 series yet. You can also choose the - ``stm32cubeprogrammer`` runner. - -Flashing -======== - -Nucleo H753ZI board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo H753ZI ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h753zi - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_h753zi - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h753zi - :maybe-skip-config: - :goals: debug - -.. _Nucleo H753ZI website: - https://www.st.com/en/evaluation-tools/nucleo-h753zi.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32H753ZI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h743-753/stm32h753zi.html - -.. _STM32H753 reference manual: - https://www.st.com/resource/en/reference_manual/dm00314099.pdf diff --git a/boards/arm/nucleo_h7a3zi_q/Kconfig.board b/boards/arm/nucleo_h7a3zi_q/Kconfig.board deleted file mode 100644 index 3d8317ac286..00000000000 --- a/boards/arm/nucleo_h7a3zi_q/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H7A3ZI-Q Nucleo board configuration - -# Copyright (c) 2021 Electrolance Solutions -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H7A3ZI_Q - bool "Nucleo H75A3ZI-Q Development Board" - depends on SOC_STM32H7A3XXQ diff --git a/boards/arm/nucleo_h7a3zi_q/Kconfig.defconfig b/boards/arm/nucleo_h7a3zi_q/Kconfig.defconfig deleted file mode 100644 index ec43ace7dcb..00000000000 --- a/boards/arm/nucleo_h7a3zi_q/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32H7A3ZI-Q Nucleo board configuration - -# Copyright (c) 2021 Electrolance Solutions -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H7A3ZI_Q - -config BOARD - default "nucleo_h7a3zi_q" - -config USB_DC_HAS_HS_SUPPORT - default y - depends on USB_DC_STM32 - -endif # BOARD_NUCLEO_H7A3ZI_Q diff --git a/boards/arm/nucleo_h7a3zi_q/doc/index.rst b/boards/arm/nucleo_h7a3zi_q/doc/index.rst deleted file mode 100644 index 1144f13e731..00000000000 --- a/boards/arm/nucleo_h7a3zi_q/doc/index.rst +++ /dev/null @@ -1,206 +0,0 @@ -.. _nucleo_h7a3zi_q_board: - -ST Nucleo H7A3ZI-Q -################## - -Overview -******** - -The STM32 Nucleo-144 boards offer combinations of performance and power that -provide an affordable and flexible way for users to build prototypes and try -out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) -significantly reduces power consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V3E debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V3E debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_h7a3zi_q.jpg - :align: center - :alt: Nucleo H7A3ZI-Q - -More information about the board can be found at the `Nucleo H7A3ZI-Q website`_. - -Hardware -******** - -Nucleo H7A3ZI-Q provides the following hardware components: - -- STM32H7A3ZI in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- Hardware JPEG Codec -- 280 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 2 MB Flash -- ~1.4 Mbytes SRAM -- 32-bit timers(2) -- 16-bit timers(15) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(5) -- UART(5) -- USB OTG Full Speed and High Speed(1) -- CAN FD(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO (up to 114) with external interrupt capability -- 16-bit ADC(2) with 24 channels / 3.6 MSPS -- 12-bit DAC with 1/2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_h7a3zi_q board configuration supports the following hardware -features: - -+-------------+------------+------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+------------------------------------+ -| ADC | on-chip | adc | -+-------------+------------+------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+------------------------------------+ -| USB OTG HS | on-chip | USB device | -+-------------+------------+------------------------------------+ -| RNG | on-chip | True Random number generator | -+-------------+------------+------------------------------------+ - - - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo H7A3ZI-Q board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- USART3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PE1 -- LD3 : PB14 -- ADC1_INP15 : PA3 (Arduino analog, A0) - -System Clock ------------- - -Nucleo H7A3ZI-Q System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo H7A3ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to USART3. Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``nucleo_h7a3zi_q`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo H7A3ZI-Q board includes an ST-LINK/V3E embedded debug tool interface. - -Flashing an application to Nucleo H7A3ZI-Q ------------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h7a3zi_q - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_h7a3zi_q - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h7a3zi_q - :maybe-skip-config: - :goals: debug - -.. _Nucleo H7A3ZI-Q website: - https://www.st.com/en/evaluation-tools/nucleo-h7a3zi-q.html#overview - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/um2408-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf - -.. _STM32H7A3ZI-Q on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3zi.html - -.. _STM32H7A3ZI-Q reference manual: - https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l011k4/Kconfig.board b/boards/arm/nucleo_l011k4/Kconfig.board deleted file mode 100644 index aa6401045f7..00000000000 --- a/boards/arm/nucleo_l011k4/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-32 development board with STM32L011K4 MCU configuration - -# Copyright (c) 2020 Steven Daglish -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L011K4 - bool "NUCLEO-32 L011K4 Development Board" - depends on SOC_STM32L011XX diff --git a/boards/arm/nucleo_l011k4/Kconfig.defconfig b/boards/arm/nucleo_l011k4/Kconfig.defconfig deleted file mode 100644 index 527a93140cb..00000000000 --- a/boards/arm/nucleo_l011k4/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-32 development board with STM32L011K4 MCU - -# Copyright (c) 2020 Steven Daglish -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L011K4 - -config BOARD - default "nucleo_l011k4" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L011K4 diff --git a/boards/arm/nucleo_l011k4/doc/index.rst b/boards/arm/nucleo_l011k4/doc/index.rst deleted file mode 100644 index 04fc12c53f3..00000000000 --- a/boards/arm/nucleo_l011k4/doc/index.rst +++ /dev/null @@ -1,167 +0,0 @@ -.. _nucleo_l011k4_board: - -ST Nucleo L011K4 -################ - -Overview -******** -The STM32 Nucleo-32 development board with STM32L011K4 MCU, supports Arduino Nano V3 connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Nano V3 connectivity support allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_l011k4.jpg - :align: center - :alt: Nucleo L011K4 - -More information about the board can be found at the `Nucleo L011K4 website`_. - -Hardware -******** -Nucleo L011K4 provides the following hardware components: - -- STM32 microcontroller in LQFP32 package -- Extension resource: - - - Arduino* Nano V3 connectivity - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- One push-button: RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32L011K4 can be found in the -`STM32L0x1 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_l011k4 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l011k4/nucleo_l011k4_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PA4/PA10 (Arduino I2C) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) -- LD2 : PB3 - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_l011k4`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L011K4 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo L011K4 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_l011k4 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l011k4 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo L011K4 website: - https://www.st.com/en/evaluation-tools/nucleo-l011k4.html - -.. _STM32L0x1 reference manual: - https://www.st.com/resource/en/reference_manual/dm00108282-ultralowpower-stm32l0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l031k6/Kconfig.board b/boards/arm/nucleo_l031k6/Kconfig.board deleted file mode 100644 index 43b52d42020..00000000000 --- a/boards/arm/nucleo_l031k6/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-32 development board with STM32L031K6 MCU configuration - -# Copyright (c) 2020 Steven Daglish -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L031K6 - bool "NUCLEO-32 L031K6 Development Board" - depends on SOC_STM32L031XX diff --git a/boards/arm/nucleo_l031k6/Kconfig.defconfig b/boards/arm/nucleo_l031k6/Kconfig.defconfig deleted file mode 100644 index 0c84a21c587..00000000000 --- a/boards/arm/nucleo_l031k6/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-32 development board with STM32L031K6 MCU - -# Copyright (c) 2020 Steven Daglish -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L031K6 - -config BOARD - default "nucleo_l031k6" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L031K6 diff --git a/boards/arm/nucleo_l031k6/doc/index.rst b/boards/arm/nucleo_l031k6/doc/index.rst deleted file mode 100644 index da0fcaa271e..00000000000 --- a/boards/arm/nucleo_l031k6/doc/index.rst +++ /dev/null @@ -1,160 +0,0 @@ -.. _nucleo_l031k6_board: - -ST Nucleo L031K6 -################ - -Overview -******** -The STM32 Nucleo-32 development board with STM32L031K6 MCU, supports Arduino Nano V3 connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Nano V3 connectivity support allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_l031k6.jpg - :align: center - :alt: Nucleo L031K6 - -More information about the board can be found at the `Nucleo L031K6 website`_. - -Hardware -******** -Nucleo L031K6 provides the following hardware components: - -- STM32 microcontroller in LQFP32 package -- Extension resource: - - - Arduino* Nano V3 connectivity - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- One push-button: RESET - -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -More information about STM32L031K6 can be found in the -`STM32L0x1 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l031k6 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l031k6/nucleo_l031k6_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PA9/PA10 (Arduino I2C) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) -- LD2 : PB3 - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_l031k6`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo L031K6 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_l031k6 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l031k6 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo L031K6 website: - https://www.st.com/en/evaluation-tools/nucleo-l031k6.html - -.. _STM32L0x1 reference manual: - https://www.st.com/resource/en/reference_manual/dm00108282-ultralowpower-stm32l0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l053r8/Kconfig.board b/boards/arm/nucleo_l053r8/Kconfig.board deleted file mode 100644 index 2500f89b00b..00000000000 --- a/boards/arm/nucleo_l053r8/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32L053R8 MCU configuration - -# Copyright (c) 2018 Anthony Kreft -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L053R8 - bool "NUCLEO-64 L053R8 Development Board" - depends on SOC_STM32L053XX diff --git a/boards/arm/nucleo_l053r8/Kconfig.defconfig b/boards/arm/nucleo_l053r8/Kconfig.defconfig deleted file mode 100644 index bcf55dcc95e..00000000000 --- a/boards/arm/nucleo_l053r8/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-64 development board with STM32L053R8 MCU - -# Copyright (c) 2018 Anthony Kreft -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L053R8 - -config BOARD - default "nucleo_l053r8" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L053R8 diff --git a/boards/arm/nucleo_l053r8/doc/index.rst b/boards/arm/nucleo_l053r8/doc/index.rst deleted file mode 100644 index ba448176fca..00000000000 --- a/boards/arm/nucleo_l053r8/doc/index.rst +++ /dev/null @@ -1,176 +0,0 @@ -.. _nucleo_l053r8_board: - -ST Nucleo L053R8 -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32L053R8 MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_l053r8.jpg - :align: center - :alt: Nucleo L053R8 - -More information about the board can be found at the `Nucleo L053R8 website`_. - -Hardware -******** -Nucleo L053R8 provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32L053R8 can be found in the -`STM32L0x3 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_l053r8 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l053r8/nucleo_l053r8_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_l053r8_connectors.jpg - :align: center - :alt: Nucleo L053R8 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) -- USER_PB : PC13 -- LD2 : PA5 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_l053r8`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L053R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo L053R8 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_l053r8 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l053r8 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo L053R8 website: - https://www.st.com/en/evaluation-tools/nucleo-l053r8.html - -.. _STM32L0x3 reference manual: - https://www.st.com/resource/en/reference_manual/dm00095744.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l073rz/Kconfig.board b/boards/arm/nucleo_l073rz/Kconfig.board deleted file mode 100644 index 4354ccf8433..00000000000 --- a/boards/arm/nucleo_l073rz/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32L073RZ MCU configuration - -# Copyright (c) 2018 Ilya Tagunov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L073RZ - bool "NUCLEO-64 L073RZ Development Board" - depends on SOC_STM32L073XX diff --git a/boards/arm/nucleo_l073rz/Kconfig.defconfig b/boards/arm/nucleo_l073rz/Kconfig.defconfig deleted file mode 100644 index 6a73209134a..00000000000 --- a/boards/arm/nucleo_l073rz/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-64 development board with STM32L073RZ MCU - -# Copyright (c) 2018 Ilya Tagunov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L073RZ - -config BOARD - default "nucleo_l073rz" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L073RZ diff --git a/boards/arm/nucleo_l073rz/doc/index.rst b/boards/arm/nucleo_l073rz/doc/index.rst deleted file mode 100644 index a828a5b70eb..00000000000 --- a/boards/arm/nucleo_l073rz/doc/index.rst +++ /dev/null @@ -1,190 +0,0 @@ -.. _nucleo_l073rz_board: - -ST Nucleo L073RZ -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32L073RZ MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_l073rz.jpg - :align: center - :alt: Nucleo L073RZ - -More information about the board can be found at the `Nucleo L073RZ website`_. - -Hardware -******** -Nucleo L073RZ provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32L073RZ can be found in the -`STM32L0x3 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_l073rz board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | Random Number Generator | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l073rz/nucleo_l073rz_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_l073rz_connectors.jpg - :align: center - :alt: Nucleo L073RZ connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) -- USER_PB : PC13 -- LD2 : PA5 -- DAC : PA4 -- PWM_2_CH1 : PA5 (might conflict with SPI1) - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_l073rz`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L073RZ board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo L073RZ ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_l073rz - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l073rz - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo L073RZ website: - https://www.st.com/en/evaluation-tools/nucleo-l073rz.html - -.. _STM32L0x3 reference manual: - https://www.st.com/resource/en/reference_manual/dm00095744.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l073rz/nucleo_l073rz_defconfig b/boards/arm/nucleo_l073rz/nucleo_l073rz_defconfig deleted file mode 100644 index 06c6cdfe5da..00000000000 --- a/boards/arm/nucleo_l073rz/nucleo_l073rz_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L073XX=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_l152re/Kconfig.board b/boards/arm/nucleo_l152re/Kconfig.board deleted file mode 100644 index c87af160801..00000000000 --- a/boards/arm/nucleo_l152re/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2019 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_NUCLEO_L152RE - bool "NUCLEO-64 L152RE Development Board" - depends on SOC_STM32L152XE diff --git a/boards/arm/nucleo_l152re/Kconfig.defconfig b/boards/arm/nucleo_l152re/Kconfig.defconfig deleted file mode 100644 index 70a209468fc..00000000000 --- a/boards/arm/nucleo_l152re/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2019 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_NUCLEO_L152RE - -config BOARD - default "nucleo_l152re" - -endif # BOARD_NUCLEO_L152RE diff --git a/boards/arm/nucleo_l152re/board.cmake b/boards/arm/nucleo_l152re/board.cmake deleted file mode 100644 index cbeaea2e456..00000000000 --- a/boards/arm/nucleo_l152re/board.cmake +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/nucleo_l152re/doc/index.rst b/boards/arm/nucleo_l152re/doc/index.rst deleted file mode 100644 index 020beb6583f..00000000000 --- a/boards/arm/nucleo_l152re/doc/index.rst +++ /dev/null @@ -1,187 +0,0 @@ -.. _nucleo_l152re_board: - -ST Nucleo L152RE -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32L152RE MCU, supports Arduino™ and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The Arduino Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_l152re.jpg - :align: center - :alt: NUCLEO-L152RE - -More information about the board can be found at the `Nucleo L152RE website`_. - -Hardware -******** -Nucleo L152RE provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: B1 (USER/blue) and B2 (RESET/black) -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -More information about STM32L152RE can be found here: - -- `STM32L152 reference manual`_ -- `STM32L152 data sheet`_ - -Supported Features -================== - -The Zephyr nucleo_l152re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l152re/nucleo_l152re_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_l152re_connectors.jpg - :align: center - :alt: Nucleo L152RE connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- B1 (USER/blue) : PC13 -- LD1 : PA5 -- DAC : PA4 -- PWM_3_CH1 : PA6 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_l152re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L152RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo L152RE ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_l152re - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l152re - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo L152RE website: - https://www.st.com/en/evaluation-tools/nucleo-l152re.html - -.. _STM32L152 reference manual: - https://www.st.com/resource/en/reference_manual/cd00240193.pdf - -.. _STM32L152 data sheet: - https://www.st.com/resource/en/datasheet/stm32l152re.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l412rb_p/Kconfig.board b/boards/arm/nucleo_l412rb_p/Kconfig.board deleted file mode 100644 index b81257b7eb7..00000000000 --- a/boards/arm/nucleo_l412rb_p/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L412RB Nucleo board configuration - -# Copyright (c) 2021 Guðni Már Gilbert -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L412RB_P - bool "Nucleo L412RB-P Development Board" - depends on SOC_STM32L412XX diff --git a/boards/arm/nucleo_l412rb_p/Kconfig.defconfig b/boards/arm/nucleo_l412rb_p/Kconfig.defconfig deleted file mode 100644 index 210607bd31d..00000000000 --- a/boards/arm/nucleo_l412rb_p/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32L412RB Nucleo board configuration - -# Copyright (c) 2021 Guðni Már Gilbert -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L412RB_P - -config BOARD - default "nucleo_l412rb_p" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L412RB_P diff --git a/boards/arm/nucleo_l412rb_p/doc/index.rst b/boards/arm/nucleo_l412rb_p/doc/index.rst deleted file mode 100644 index 3485d01cba1..00000000000 --- a/boards/arm/nucleo_l412rb_p/doc/index.rst +++ /dev/null @@ -1,269 +0,0 @@ -.. _nucleo_l412rb_p_board: - -ST Nucleo L412RB-P -################## - -Overview -******** - -The Nucleo L412RB board features an ARM Cortex-M4 based STM32L412RB MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L412RB board: - -- STM32 microcontroller in LQFP64 package -- 1 user LED shared with ARDUINO |reg| -- 1 user and 1 reset push-buttons -- 32.768 kHz crystal oscillator -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port and debug port -- Flexible power-supply options: ST-LINK, USB VBUS, or external sources - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Board specific features - - - External SMPS to generate Vcore logic supply - - 24 MHz HSE - - Board connectors: - - - External SMPS experimentation dedicated connector - - Micro-AB or Mini-AB USB connector for the ST-LINK - - MIPI® debug connector - - - Arm® Mbed Enabled |trade| compliant - -.. image:: img/nucleo_l412rb_p.jpg - :align: center - :alt: Nucleo L412RB - -More information about the board can be found at the `Nucleo L412RB-P website`_. - -Hardware -******** - -Nucleo L412RB-P provides the following hardware components: - -- STM32L412RBT6 in LQFP64 package -- Ultra-low-power with FlexPowerControl - - - 1.71 V to 3.6 V power supply - - -40 °C to 85/125 °C temperature range - - 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers - - 16 nA Shutdown mode (4 wakeup pins) - - 32 nA Standby mode (4 wakeup pins) - - 245 nA Standby mode with RTC - - 0.7 |micro| A Stop 2 mode, 0.95 |micro| A with RTC - - 79 |micro| A/MHz run mode (LDO Mode) - - 28 |micro| A/MHz run mode (@3.3 V SMPS Mode) - - Batch acquisition mode (BAM) - - 4 |micro| s wakeup from Stop mode - - Brown out reset (BOR) - - Interconnect matrix - -- Core: Arm |reg| 32-bit Cortex |reg| -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator |trade| ) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions -- Performance benchmark - - - 1.25 DMIPS/MHz (Drystone 2.1) - - 273.55 CoreMark |reg| (3.42 CoreMark/MHz @ 80 MHz) - -- Energy benchmark - - - 442 ULPMark-CP® - - 165 ULPMark-PP® - -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than |plusminus| 0.25 % accuracy) - - Internal 48 MHz with clock recovery - - PLL for system clock - -- Up to 52 fast I/Os, most 5 V-tolerant -- RTC with HW calendar, alarms and calibration -- Up to 12 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 10x timers: - - - 1x 16-bit advanced motor-control - - 1x 32-bit and 2x 16-bit general purpose - - 1x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Memories - - - 128 KB single bank Flash, proprietary code readout protection - - 40 KB of SRAM including 8 KB with hardware parity check - - Quad SPI memory interface with XIP capability - -- Rich analog peripherals (independent supply) - - - 2x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 |micro| A/Msps - - 2x operational amplifiers with built-in PGA - - 1x ultra-low-power comparator - - Accurate 2.5 V or 2.048 V reference voltage buffered output - -- 12x communication interfaces - - USB 2.0 full-speed crystal less solution with LPM and BCD - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 3x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART (Stop 2 wake-up) - - 2x SPIs (and 1x Quad SPI) - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| -- All packages are ECOPACK2 compliant - -Note: the current board revision is C. (MB1319C) - -More information about STM32L412RB can be found here: - -- `STM32L412RB on www.st.com`_ -- `STM32L412 reference manual`_ - -Supported Features -================== - -The Zephyr ``nucleo_l412rb_p`` board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l412rb_p/nucleo_l412rb_p_defconfig`` - - -Connections and IOs -=================== - -Nucleo L412RB-P Board has 5 GPIO controllers (Ports A, B, C, D and H). These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_l412rb_p_pinout.jpg - :align: center - :alt: Nucleo L412RB-P - -For more details please refer to `ST Nucleo L412RB-P User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- LPUART1 TX/RX : PA2/PA3 -- I2C1 SCL/SDA : PB8/PB7 (Arduino I2C) -- SPI2 CS/SCK/MISO/MOSI : PA11/PB13/PB14/PB15 (Arduino SPI) -- UART1 TX/RX : PA9/PA10 -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD4 : PB13 - -Note: SPI2 CS pin (PB12) is not located on the Arduino connector. - -System Clock ------------- - -Nucleo L412RB-P System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L412RB-P board has 3 U(S)ARTs and 1 LPUART. The Zephyr console output is assigned to LPUART1. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l412rb_p`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L412RB-P board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Nucleo L412RB-P ------------------------------------------- - -Connect the Nucleo L412RB-P to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l412rb_p - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_l412rb_p - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l412rb_p - :maybe-skip-config: - :goals: debug - -.. _Nucleo L412RB-P website: - https://www.st.com/en/evaluation-tools/nucleo-l412rb-p.html - -.. _ST Nucleo L412RB-P User Manual: - https://www.st.com/resource/en/user_manual/dm00387966-stm32-nucleo-64-p-boards-stmicroelectronics.pdf - -.. _STM32L412RB on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l412rb.html - -.. _STM32L412 reference manual: - https://www.st.com/resource/en/reference_manual/dm00151940-stm32l41xxx42xxx43xxx44xxx45xxx46xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l432kc/Kconfig.board b/boards/arm/nucleo_l432kc/Kconfig.board deleted file mode 100644 index 5340455df00..00000000000 --- a/boards/arm/nucleo_l432kc/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# STM32L432KC Nucleo board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L432KC - bool "Nucleo L432KC Development Board" - depends on SOC_STM32L432XX diff --git a/boards/arm/nucleo_l432kc/Kconfig.defconfig b/boards/arm/nucleo_l432kc/Kconfig.defconfig deleted file mode 100644 index d76ef2633af..00000000000 --- a/boards/arm/nucleo_l432kc/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32L432KC Nucleo board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L432KC - -config BOARD - default "nucleo_l432kc" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L432KC diff --git a/boards/arm/nucleo_l432kc/doc/index.rst b/boards/arm/nucleo_l432kc/doc/index.rst deleted file mode 100644 index b054c472f22..00000000000 --- a/boards/arm/nucleo_l432kc/doc/index.rst +++ /dev/null @@ -1,229 +0,0 @@ -.. _nucleo_l432kc_board: - -ST Nucleo L432KC -################ - -Overview -******** - -The Nucleo L432KC board features an ARM Cortex-M4 based STM32L432KC MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L432KC board: - -- STM32 microcontroller in UFQFPN32 package -- Arduino Uno V3 connectivity -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), power LED (LD2), user LED (LD3) -- One push-button: RESET - -.. image:: img/nucleo_l432kc.jpg - :align: center - :alt: Nucleo L432KC - -More information about the board can be found at the `Nucleo L432KC website`_. - -Hardware -******** - -The STM32L432KC SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, - 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 2 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 11x timers: - - - 1x 16-bit advanced motor-control - - 1x 32-bit and 2x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 26 fast I/Os, most 5 V-tolerant -- Memories - - - Up to 256 KB single bank Flash, proprietary code readout protection - - Up to 64 KB of SRAM including 16 KB with hardware parity check - - Quad SPI memory interface - -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 1x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 13x communication interfaces - - - USB OTG 2.0 full-speed crystal less solution with LPM and BCD - - 1x SAIs (serial audio interface) - - 2x I2C FM+(1 Mbit/s), SMBus/PMBus - - 3x USARTs (ISO 7816, LIN, IrDA, modem) - - 2x SPIs (3x SPIs with the Quad SPI) - - CAN (2.0B Active) - - SWPMI single wire protocol master I/F - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32L432KC can be found here: - -- `STM32L432KC on www.st.com`_ -- `STM32L432 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l432kc board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig`` - - -Connections and IOs -=================== - -Nucleo L432KC Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_l432kc_arduino_nano.jpg - :align: center - :alt: Nucleo L432KC Arduino connectors - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- I2C_1_SCL : PB6 -- I2C_1_SDA : PB7 -- PWM_2_CH1 : PA0 -- LD3 : PB3 - -System Clock ------------- - -Nucleo L432KC System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L432KC board has 3 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l432kc`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L432KC board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Nucleo L432KC ----------------------------------------- - -Connect the Nucleo L432KC to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l432kc - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l432kc - :maybe-skip-config: - :goals: debug - -.. _Nucleo L432KC website: - https://www.st.com/en/evaluation-tools/nucleo-l432kc.html - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744.pdf - -.. _STM32L432KC on www.st.com: - https://www.st.com/en/microcontrollers/stm32l432kc.html - -.. _STM32L432 reference manual: - https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l433rc_p/Kconfig.board b/boards/arm/nucleo_l433rc_p/Kconfig.board deleted file mode 100644 index 3a53d91bc25..00000000000 --- a/boards/arm/nucleo_l433rc_p/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L433RC Nucleo board configuration - -# Copyright (c) 2021 Matija Tudan -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L433RC_P - bool "Nucleo L433RC-P Development Board" - depends on SOC_STM32L433XX diff --git a/boards/arm/nucleo_l433rc_p/Kconfig.defconfig b/boards/arm/nucleo_l433rc_p/Kconfig.defconfig deleted file mode 100644 index 62136895033..00000000000 --- a/boards/arm/nucleo_l433rc_p/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32L433RC Nucleo board configuration - -# Copyright (c) 2021 Matija Tudan -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L433RC_P - -config BOARD - default "nucleo_l433rc_p" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L433RC_P diff --git a/boards/arm/nucleo_l433rc_p/doc/index.rst b/boards/arm/nucleo_l433rc_p/doc/index.rst deleted file mode 100644 index 6e86a44cee0..00000000000 --- a/boards/arm/nucleo_l433rc_p/doc/index.rst +++ /dev/null @@ -1,234 +0,0 @@ -.. _nucleo_l433rc_board: - -ST Nucleo L433RC -################ - -Overview -******** - -The Nucleo L433RC board features an ARM Cortex-M4 based STM32L433RC MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L433RC board: - -- STM32 microcontroller in LQFP64 package -- Arduino Uno V3 connectivity -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD4) -- One push-button: RESET - -.. image:: img/nucleo_l433rc_p.jpg - :align: center - :alt: Nucleo L433RC - -More information about the board can be found at the `Nucleo L433RC-P website`_. - -Hardware -******** - -The STM32L433RC SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, - 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 2 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- Up to 21 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 11x timers: - - - 1x 16-bit advanced motor-control - - 1x 32-bit and 2x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 83 fast I/Os, most 5 V-tolerant -- Memories - - - Up to 256 KB single bank Flash, proprietary code readout protection - - 64 KB of SRAM including 16 KB with hardware parity check - - Quad SPI memory interface - -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 2x 12-bit DAC output channels, low-power sample and hold - - 1x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 17x communication interfaces - - - USB 2.0 full-speed crystal less solution with LPM and BCD - - 1x SAI (serial audio interface) - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART (Stop 2 wake-up) - - 3x SPIs (and 1x Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32L433RC can be found here: - -- `STM32L433RC on www.st.com`_ -- `STM32L432 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l433rc_p board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l433rc_p/nucleo_l433rc_p_defconfig`` - - -Connections and IOs -=================== - -Nucleo L433RC-P Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_l433rc_p_pinout.jpg - :align: center - :alt: Nucleo L433RC-P - -For more details please refer to `ST Nucleo L433RC-P User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- LPUART_1_TX : PA2 -- LPUART_1_RX : PA3 -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- I2C_1_SCL : PB6 -- I2C_1_SDA : PB7 -- PWM_2_CH1 : PA0 -- LD4 : PB13 -- SPI_1: NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 -- SPI_2: NSS/SCK/MISO/MOSI : PA11/PB13/PB14/PB15 (Arduino SPI) - -System Clock ------------- - -Nucleo L433RC-P System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L433RC-P board has 4 U(S)ARTs and 1 LPUART. The Zephyr console output is assigned -to LPUART1. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l433rc_p`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L433RC-P board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Nucleo L433RC-P ------------------------------------------- - -Connect the Nucleo L433RC-P to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ picocom /dev/ttyACM0 -b 115200 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l433rc_p - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_l433rc_p - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l433rc_p - :maybe-skip-config: - :goals: debug - -.. _Nucleo L433RC-P website: - https://www.st.com/en/evaluation-tools/nucleo-l433rc-p.html - -.. _ST Nucleo L433RC-P User Manual: - https://www.st.com/resource/en/user_manual/dm00387966.pdf - -.. _STM32L433RC on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l433rc.html - -.. _STM32L432 reference manual: - https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l452re/Kconfig.board b/boards/arm/nucleo_l452re/Kconfig.board deleted file mode 100644 index ba69b24e6e6..00000000000 --- a/boards/arm/nucleo_l452re/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# STM32L452RE Nucleo board configuration -# -# Copyright (c) 2019 Libre Solar Technologies GmbH -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L452RE - bool "Nucleo L452RE Development Board" - depends on SOC_STM32L452XX - -config BOARD_NUCLEO_L452RE_P - bool "Nucleo L452RE-P Development Board" - depends on SOC_STM32L452XX diff --git a/boards/arm/nucleo_l452re/Kconfig.defconfig b/boards/arm/nucleo_l452re/Kconfig.defconfig deleted file mode 100644 index 3da8b18ec74..00000000000 --- a/boards/arm/nucleo_l452re/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# STM32L452RE Nucleo board configuration -# -# Copyright (c) 2019 Libre Solar Technologies GmbH -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L452RE || BOARD_NUCLEO_L452RE_P - -config BOARD - default "nucleo_l452re" if BOARD_NUCLEO_L452RE - default "nucleo_l452re_p" if BOARD_NUCLEO_L452RE_P - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L452RE || BOARD_NUCLEO_L452RE_P diff --git a/boards/arm/nucleo_l452re/doc/index.rst b/boards/arm/nucleo_l452re/doc/index.rst deleted file mode 100644 index 4b68d032be1..00000000000 --- a/boards/arm/nucleo_l452re/doc/index.rst +++ /dev/null @@ -1,256 +0,0 @@ -.. _nucleo_l452re_board: - -ST Nucleo L452RE -################ - -Overview -******** - -The Nucleo L452RE(-P) boards feature an ARM Cortex-M4 based STM32L452RE MCU -with a wide range of connectivity support and configurations. There are two variants: - -- ST Nucleo L452RE -- ST Nucleo L452RE-P - -Here some highlights of these boards: - -- STM32 microcontroller in LQFP64 package -- Arduino Uno V3 connectivity -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- One push-button: RESET - -.. image:: img/nucleo_l452re_p.jpg - :align: center - :alt: Nucleo L452RE-P - -The main difference between the ST Nucleo L452RE and the L452RE-P (note the missing -"-P" at the end) lays in the External Switched Mode Power Supply (SMPS) included in -the P series. - -More information about the boards can be found at the `Nucleo L452RE website`_ and -the `Nucleo L452RE-P website`_. - -Hardware -******** - -The STM32L452RE SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, - 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 2 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 12x timers: - - - 1x 16-bit advanced motor-control - - 1x 32-bit and 3x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 26 fast I/Os, most 5 V-tolerant -- Memories - - - Up to 512 KB single bank Flash, proprietary code readout protection - - 160 KB of SRAM including 32 KB with hardware parity check - - Quad SPI memory interface - -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 1x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 17x communication interfaces - - USB 2.0 full-speed crystal less solution with LPM and BCD - - 1x SAI (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 3x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x UART (LIN, IrDA, modem) - - 1x LPUART (Stop 2 wake-up) - - 3x SPIs (and 1x Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32L452RE can be found here: - -- `STM32L452RE on www.st.com`_ -- `STM32L452 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l452re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l452re/nucleo_l452re_defconfig`` - - -Connections and IOs -=================== - -Nucleo L452RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_l452re_pinout.jpg - :align: center - :alt: Nucleo L452RE Pinout - -.. image:: img/nucleo_l452re_p_pinout.jpg - :align: center - :alt: Nucleo L452RE-P Pinout - -For more details please refer to `ST Nucleo L452RE User Manual`_ or -`ST Nucleo L452RE-P User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB7 -- PWM_2_CH1 : PA0 -- SPI_NSS : PB6 -- SPI_SCK : PA5 -- SPI_MISO : PA6 -- SPI_MOSI : PA7 -- CAN_TX : PA11 -- CAN_RX : PA12 -- LD2 : PA5 - -System Clock ------------- - -Nucleo L452RE System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L452RE board has 3 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l452re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L452RE board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Nucleo L452RE ----------------------------------------- - -Connect the Nucleo L452RE to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l452re - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l452re - :maybe-skip-config: - :goals: debug - -.. _Nucleo L452RE website: - https://www.st.com/en/evaluation-tools/nucleo-l452re.html - -.. _Nucleo L452RE-P website: - https://www.st.com/en/evaluation-tools/nucleo-l452re-p.html - -.. _ST Nucleo L452RE User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _ST Nucleo L452RE-P User Manual: - https://www.st.com/resource/en/user_manual/dm00387966.pdf - -.. _STM32L452RE on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l452re.html - -.. _STM32L452 reference manual: - https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l452re/nucleo_l452re_p.yaml b/boards/arm/nucleo_l452re/nucleo_l452re_p.yaml deleted file mode 100644 index 7ca93a9c9bc..00000000000 --- a/boards/arm/nucleo_l452re/nucleo_l452re_p.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: nucleo_l452re_p -name: ST Nucleo L452RE-P -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 160 -flash: 512 -supported: - - nvs - - pwm - - can - - counter - - spi -vendor: st diff --git a/boards/arm/nucleo_l452re/nucleo_l452re_p_defconfig b/boards/arm/nucleo_l452re/nucleo_l452re_p_defconfig deleted file mode 100644 index 14b7ffdd209..00000000000 --- a/boards/arm/nucleo_l452re/nucleo_l452re_p_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L452XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_l476rg/Kconfig.board b/boards/arm/nucleo_l476rg/Kconfig.board deleted file mode 100644 index b83025518a2..00000000000 --- a/boards/arm/nucleo_l476rg/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# STM32L476RG Nucleo board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L476RG - bool "Nucleo L476RG Development Board" - depends on SOC_STM32L476XX diff --git a/boards/arm/nucleo_l476rg/Kconfig.defconfig b/boards/arm/nucleo_l476rg/Kconfig.defconfig deleted file mode 100644 index cbbef016161..00000000000 --- a/boards/arm/nucleo_l476rg/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32L476RG Nucleo board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L476RG - -config BOARD - default "nucleo_l476rg" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L476RG diff --git a/boards/arm/nucleo_l476rg/doc/index.rst b/boards/arm/nucleo_l476rg/doc/index.rst deleted file mode 100644 index 10dff333643..00000000000 --- a/boards/arm/nucleo_l476rg/doc/index.rst +++ /dev/null @@ -1,243 +0,0 @@ -.. _nucleo_l476rg_board: - -ST Nucleo L476RG -################ - -Overview -******** - -The Nucleo L476RG board features an ARM Cortex-M4 based STM32L476RG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L476RG board: - - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_l476rg.jpg - :align: center - :alt: Nucleo L476RG - -More information about the board can be found at the `Nucleo L476RG website`_. - -Hardware -******** - -The STM32L476RG SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- LCD 8 x 40 or 4 x 44 with step-up converter -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 128 KB of SRAM including 32 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface - -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 18x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (4x SPIs with the Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L476RG can be found here: - -- `STM32L476RG on www.st.com`_ -- `STM32L476 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l476rg board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig`` - - -Connections and IOs -=================== - -Nucleo L476RG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_l476rg_arduino.jpg - :align: center - :alt: Nucleo L476RG Arduino connectors -.. image:: img/nucleo_l476rg_morpho.jpg - :align: center - :alt: Nucleo L476RG Morpho connectors - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1 TX/RX : PA9/PA10 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- UART_3 TX/RX : PB10/PB11 -- I2C_1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C_3 SCL/SDA : PC0/PC1 -- SPI_1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- SPI_2 CS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- SPI_3 CS/SCK/MISO/MOSI : PA15/PC10/PC11/PC12 -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD2 : PA5 - -System Clock ------------- - -Nucleo L476RG System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L476RG board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l476rg`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L476RG board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Nucleo L476RG ----------------------------------------- - -Connect the Nucleo L476RG to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l476rg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l476rg - :maybe-skip-config: - :goals: debug - -.. _Nucleo L476RG website: - https://www.st.com/en/evaluation-tools/nucleo-l476rg.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32L476RG on www.st.com: - https://www.st.com/en/microcontrollers/stm32l476rg.html - -.. _STM32L476 reference manual: - https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/nucleo_l496zg/Kconfig.board b/boards/arm/nucleo_l496zg/Kconfig.board deleted file mode 100644 index 908385c5f53..00000000000 --- a/boards/arm/nucleo_l496zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L496ZG Nucleo board configuration - -# Copyright (c) 2018-2019 Centaur Analytics, Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L496ZG - bool "Nucleo L496ZG Development Board" - depends on SOC_STM32L496XX diff --git a/boards/arm/nucleo_l496zg/Kconfig.defconfig b/boards/arm/nucleo_l496zg/Kconfig.defconfig deleted file mode 100644 index 34fcc96575a..00000000000 --- a/boards/arm/nucleo_l496zg/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32L496ZG Nucleo board configuration - -# Copyright (c) 2018 Centaur Analytics, Inc -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L496ZG - -config BOARD - default "nucleo_l496zg" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L496ZG diff --git a/boards/arm/nucleo_l496zg/doc/index.rst b/boards/arm/nucleo_l496zg/doc/index.rst deleted file mode 100644 index 49d011b8846..00000000000 --- a/boards/arm/nucleo_l496zg/doc/index.rst +++ /dev/null @@ -1,244 +0,0 @@ -.. _nucleo_l496zg_board: - -ST Nucleo L496ZG -################ - -Overview -******** - -The Nucleo L496ZG board features an ARM Cortex-M4 based STM32L496ZG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L476ZG board: - - -- STM32 microcontroller in QFP144 package -- USB OTG FS with Micro-AB connector -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- 8 LEDs: user LEDs (LD1, LD2, LD3), communication LED (LD4), USB - power fault(LD5), power LED (LD6), USB FS OTG (LD7, LD8) -- 2 push buttons: USER and RESET - -.. image:: img/nucleo_l496zg.jpg - :align: center - :alt: Nucleo L496ZG - -More information about the board can be found at the `Nucleo L496ZG website`_. - -Hardware -******** - -The STM32L496ZG SoC provides the following hardware capabilities: - -- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- LCD 8 x 40 or 4 x 44 with step-up converter -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 320 KB of SRAM including 64 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface - -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 20x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 5x U(S)ARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART - - 3x SPIs (4x SPIs with the Quad SPI) - - 2x CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L496ZG can be found here: - -- `STM32L496ZG on www.st.com`_ -- `STM32L496 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l496zg board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | System Window Watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l496zg/nucleo_l496zg_defconfig`` - - -Connections and IOs -=================== - -Nucleo L496ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PD5/PD6 -- UART_3 TX/RX : PD8/PD9 -- LPUART_1 TX/RX : PG7/PG8 -- PWM_1_CH1: PE9 -- PWM_1_CH2: PE11 -- PWM_1_CH3: PE13 -- PWM_2_CH1: PA0 -- I2C_1_SCL: PB8 -- I2C_1_SDA: PB7 -- SPI_1_NSS: PD14 -- SPI_1_SCK: PA5 -- SPI_1_MISO: PA6 -- SPI_1_MOSI: PA7 -- USER_PB : PC13 -- LD1 : PC7 -- LD2 : PB7 -- LD3 : PB14 - -System Clock ------------- - -Nucleo L496ZG System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L496ZG board has 5 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l496zg`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L496ZG board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.5. - -Flashing an application to Nucleo L496ZG ----------------------------------------- - -Connect the Nucleo L496ZG to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyUSB0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l496zg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l496zg - :maybe-skip-config: - :goals: debug - -.. _Nucleo L496ZG website: - https://www.st.com/en/evaluation-tools/nucleo-l496zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00368330.pdf - -.. _STM32L496ZG on www.st.com: - https://www.st.com/en/microcontrollers/stm32l496zg.html - -.. _STM32L496 reference manual: - https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/nucleo_l4a6zg/Kconfig.board b/boards/arm/nucleo_l4a6zg/Kconfig.board deleted file mode 100644 index ad15c2540fd..00000000000 --- a/boards/arm/nucleo_l4a6zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L4A6ZG Nucleo board configuration - -# Copyright (c) 2022 Tomislav Milkovic -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L4A6ZG - bool "Nucleo L4A6ZG Development Board" - depends on SOC_STM32L4A6XX diff --git a/boards/arm/nucleo_l4a6zg/Kconfig.defconfig b/boards/arm/nucleo_l4a6zg/Kconfig.defconfig deleted file mode 100644 index c0865661295..00000000000 --- a/boards/arm/nucleo_l4a6zg/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32L4A6ZG Nucleo board configuration - -# Copyright (c) 2022 Tomislav Milkovic -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L4A6ZG - -config BOARD - default "nucleo_l4a6zg" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L4A6ZG diff --git a/boards/arm/nucleo_l4a6zg/doc/index.rst b/boards/arm/nucleo_l4a6zg/doc/index.rst deleted file mode 100644 index 7e61d9f8907..00000000000 --- a/boards/arm/nucleo_l4a6zg/doc/index.rst +++ /dev/null @@ -1,243 +0,0 @@ -.. _nucleo_l4a6zg_board: - -ST Nucleo L4A6ZG -################ - -Overview -******** - -The Nucleo L4A6ZG board features an ARM Cortex-M4 based STM32L4A6ZG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L4A6ZG board: - - -- STM32 microcontroller in QFP144 package -- USB OTG FS with Micro-AB connector -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- 8 LEDs: user LEDs (LD1, LD2, LD3), communication LED (LD4), USB - power fault(LD5), power LED (LD6), USB FS OTG (LD7, LD8) -- 2 push buttons: USER and RESET - -.. image:: ../../nucleo_l496zg/doc/img/nucleo_l496zg.jpg - :align: center - :alt: Nucleo L4A6ZG - -More information about the board can be found at the `Nucleo L4A6ZG website`_. - -Hardware -******** - -The STM32L4A6ZG SoC provides the following hardware capabilities: - -- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- LCD 8 x 40 or 4 x 44 with step-up converter -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 320 KB of SRAM including 64 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface - -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 20x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 5x U(S)ARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART - - 3x SPIs (4x SPIs with the Quad SPI) - - 2x CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- AES and HASH hardware accelerators -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L4A6ZG can be found here: - -- `STM32L4A6ZG on www.st.com`_ -- `STM32L4A6 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l4a6zg board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| AES | on-chip | crypto | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | System Window Watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l4a6zg/nucleo_l4a6zg_defconfig`` - - -Connections and IOs -=================== - -Nucleo L4A6ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- LPUART_1 TX/RX : PG7/PG8 (ST-Link Virtual COM Port) -- UART_3 TX/RX : PD8/PD9 (Arduino Serial) -- I2C_1 SCL/SDA : PB8/PB7 (Arduino I2C) -- SPI_1 SCK/MISO/MOSI/NSS : PA5/PA6/PA7/PD14 (Arduino SPI) -- USER_PB : PC13 -- PWM_15_CH1 : PB14 (Red LED) -- LD1 : PC7 (Green LED) -- LD2 : PB7 (Blue LED) -- LD3 : PB14 (Red LED) - -System Clock ------------- - -Nucleo L4A6ZG system clock could be driven by internal or external oscillator, -as well as main PLL clock. By default, system clock is driven by PLL at 80MHz, which is -driven by 16MHz high speed internal oscillator (HSI). High speed external oscillator -(HSE) is not soldered on the board, so it cannot be used to drive the PLL. - -Serial Port ------------ - -Nucleo L4A6ZG board has 5 UARTs. The Zephyr console output is assigned to LPUART1, -which is connected to the onboard ST-LINK/V2-1. Virtual COM port interface. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l4a6zg`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L4A6ZG board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the OpenOCD version -included in the Zephyr SDK since v0.9.5. - -Flashing an application to Nucleo L4A6ZG ----------------------------------------- - -Connect the Nucleo L4A6ZG to your host computer using the ST-LINK USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyUSB0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l4a6zg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! nucleo_l4a6zg - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l4a6zg - :maybe-skip-config: - :goals: debug - -.. _Nucleo L4A6ZG website: - https://www.st.com/en/evaluation-tools/nucleo-l4a6zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00368330.pdf - -.. _STM32L4A6ZG on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l4a6zg.html - -.. _STM32L4A6 reference manual: - https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/nucleo_l4r5zi/Kconfig.board b/boards/arm/nucleo_l4r5zi/Kconfig.board deleted file mode 100644 index aebd712289b..00000000000 --- a/boards/arm/nucleo_l4r5zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L4R5ZI Nucleo board configuration - -# Copyright (c) 2018 Pushpal Sidhu -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L4R5ZI - bool "Nucleo L4R5ZI Development Board" - depends on SOC_STM32L4R5XX diff --git a/boards/arm/nucleo_l4r5zi/Kconfig.defconfig b/boards/arm/nucleo_l4r5zi/Kconfig.defconfig deleted file mode 100644 index 5b3db7604cb..00000000000 --- a/boards/arm/nucleo_l4r5zi/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# STM32L4R5ZI Nucleo board configuration - -# Copyright (c) 2018 Pushpal Sidhu -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L4R5ZI - -config BOARD - default "nucleo_l4r5zi" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_EEM - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_L4R5ZI diff --git a/boards/arm/nucleo_l4r5zi/doc/index.rst b/boards/arm/nucleo_l4r5zi/doc/index.rst deleted file mode 100644 index b132403ce2a..00000000000 --- a/boards/arm/nucleo_l4r5zi/doc/index.rst +++ /dev/null @@ -1,275 +0,0 @@ -.. _nucleo_l4r5zi_board: - -ST Nucleo L4R5ZI -################ - -Overview -******** - -The Nucleo L4R5ZI board features an ARM Cortex-M4 based STM32L4R5ZI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L4R5ZI board: - - -- STM32 microcontroller in LQFP144 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three User LEDs: LD1 (Green), LD2 (Blue), LD3 (Red) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_l4r5zi.jpg - :align: center - :alt: Nucleo L4R5ZI - -More information about the board can be found at the `Nucleo L4R5ZI website`_. - -Hardware -******** - -The STM32L4R5ZI SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode - and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive - real-time accelerator (ART Accelerator) allowing 0-wait-state - execution from Flash memory, frequency up to 120 MHz, MPU, 150 - DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - Internal 48 MHz with clock recovery - - 3 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- Up to 24 capacitive sensing channels: support touchkey, linear and - rotary touch sensors -- Advanced graphics features - - - Chrom-ART Accelerator™ (DMA2D) for enhanced graphic content creation - - Chrom-GRC™ (GFXMMU) allowing up to 20% of graphic resources optimization - - MIPI® DSI Host controller with two DSI lanes running at up to 500 - Mbits/s each - - LCD-TFT controller - -- 16x timers - - - 2 x 16-bit advanced motor-control - - 2 x 32-bit and 5 x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with - independent supply down to 1.08 V -- Memories - - - 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection - - 640 Kbytes of SRAM including 64 Kbytes with hardware parity check - - External memory interface for static memories supporting SRAM, - PSRAM, NOR, NAND and FRAM memories - - 2 x OctoSPI memory interface - -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - - 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 μA/Msps - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 20x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (5x SPIs with the dual OctoSPI) - - CAN (2.0B Active) and SDMMC - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- 8- to 14-bit camera interface up to 32 MHz (black and white) or 10 MHz (color) -- Development support: serial wire debug (SWD), JTAG, Embedded Trace - Macrocell (ETM) - -More information about STM32L4R5ZI can be found here: - -- `STM32L4R5ZI on www.st.com`_ -- `STM32L4R5 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l4r5zi board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig`` - - -Connections and IOs -=================== - -Nucleo L4R5ZI Board has 8 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo144_layout.jpg - :align: center - :alt: Nucleo L4R5ZI Arduino connectors - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- UART_3_TX : PB10 -- UART_3_RX : PB11 -- I2C_1_SCL : PB6 -- I2C_1_SDA : PB7 -- SPI_1_NSS : PD14 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- SPI_2_NSS : PB12 -- SPI_2_SCK : PB13 -- SPI_2_MISO : PB14 -- SPI_2_MOSI : PB15 -- SPI_3_NSS : PB12 -- SPI_3_SCK : PC10 -- SPI_3_MISO : PC11 -- SPI_3_MOSI : PC12 -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD1 : PC7 -- LD2 : PB7 -- LD3 : PB14 -- USB DM : PA11 -- USB DP : PA12 -- ADC1 : PC0 - -System Clock ------------- - -Nucleo L4R5ZI System Clock could be driven by internal or external -oscillator, as well as main PLL clock. By default, the System clock is -driven by the PLL clock at 80MHz, driven by a 16MHz high speed -internal oscillator. The clock can be boosted to 120MHz if boost mode -is selected. - -Serial Port ------------ - -Nucleo L4R5ZI board has 5 U(S)ARTs. The Zephyr console output is -assigned to UART2. Default settings are 115200 8N1. - -Network interface ------------------ - -Ethernet over USB is configured as the default network interface (EEM) - -Programming and Debugging -************************* - -The NUCLEO-L4R5ZI board includes a ST-LINK/V2 embedded debug tool interface. - -The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, -so its installation is required to be able to flash the board. - -Alternatively, openocd (provided in Zephyr SDK) or JLink can also be used to -flash the board using the ``--runner`` (or ``-r``) option: - -.. code-block:: console - - $ west flash --runner openocd - $ west flash --runner jlink - -Connect the Nucleo L4R5ZI to your host computer using the USB port. -Then build and flash an application. - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l4r5zi - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -.. _Nucleo L4R5ZI website: - https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00368330.pdf - -.. _STM32L4R5ZI on www.st.com: - https://www.st.com/en/microcontrollers/stm32l4r5zi.html - -.. _STM32L4R5 reference manual: - https://www.st.com/resource/en/reference_manual/DM00310109.pdf - -.. _STM32 ST-LINK utility: - https://www.st.com/content/st_com/en/products/development-tools/software-development-tools/stm32-software-development-tools/stm32-programmers/stsw-link004.html - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/nucleo_l552ze_q/Kconfig.board b/boards/arm/nucleo_l552ze_q/Kconfig.board deleted file mode 100644 index a79e9274d0b..00000000000 --- a/boards/arm/nucleo_l552ze_q/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L552ZE Q Nucleo board configuration - -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L552ZE_Q - bool "Nucleo L552ZE Q Development Board" - depends on SOC_STM32L552XX diff --git a/boards/arm/nucleo_l552ze_q/Kconfig.defconfig b/boards/arm/nucleo_l552ze_q/Kconfig.defconfig deleted file mode 100644 index 3d832d33904..00000000000 --- a/boards/arm/nucleo_l552ze_q/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# STM32L552ZE Q Nucleo board configuration - -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L552ZE_Q - -config BOARD - default "nucleo_l552ze_q" - -if TRUSTED_EXECUTION_NONSECURE - -# Get flash configuration for NS image from dts flash partition -config USE_DT_CODE_PARTITION - default y - -endif # TRUSTED_EXECUTION_NONSECURE - -endif # BOARD_NUCLEO_L552ZE_Q diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.yaml b/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.yaml deleted file mode 100644 index 1eb62f85b96..00000000000 --- a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: nucleo_l552ze_q_ns -name: ST Nucleo L552ZE Q non secure -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - gpio - - dac -ram: 192 -flash: 328 -vendor: st diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns_defconfig b/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns_defconfig deleted file mode 100644 index 93f551efc34..00000000000 --- a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32L5X=y -CONFIG_SOC_STM32L552XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable clock -CONFIG_CLOCK_CONTROL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_u575zi_q/Kconfig.board b/boards/arm/nucleo_u575zi_q/Kconfig.board deleted file mode 100644 index 1f08c09447e..00000000000 --- a/boards/arm/nucleo_u575zi_q/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32U575ZI Q Nucleo board configuration - -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_U575ZI_Q - bool "Nucleo U575ZI Q Development Board" - depends on SOC_STM32U575XX diff --git a/boards/arm/nucleo_u575zi_q/Kconfig.defconfig b/boards/arm/nucleo_u575zi_q/Kconfig.defconfig deleted file mode 100644 index 901d86a2551..00000000000 --- a/boards/arm/nucleo_u575zi_q/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32U575ZI Q Nucleo board configuration - -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_U575ZI_Q - -config BOARD - default "nucleo_u575zi_q" - -endif # BOARD_NUCLEO_U575ZI_Q diff --git a/boards/arm/nucleo_u575zi_q/doc/index.rst b/boards/arm/nucleo_u575zi_q/doc/index.rst deleted file mode 100644 index bbb547130d8..00000000000 --- a/boards/arm/nucleo_u575zi_q/doc/index.rst +++ /dev/null @@ -1,343 +0,0 @@ -.. _nucleo_u575zi_q_board: - -ST Nucleo U575ZI Q -################## - -Overview -******** - -The Nucleo U575ZI Q board, featuring an ARM Cortex-M33 based STM32U575ZI MCU, -provides an affordable and flexible way for users to try out new concepts and -build prototypes by choosing from the various combinations of performance and -power consumption features. Here are some highlights of the Nucleo U575ZI Q -board: - - -- STM32U575ZI microcontroller in LQFP144 package -- Internal SMPS to generate V core logic supply -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V3E debugger/programmer -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - ST-Link V3E - -- Three users LEDs -- Two push-buttons: USER and RESET -- USB Type-C |trade| Sink device FS - -Hardware -******** - -The STM32U575xx devices are an ultra-low-power microcontrollers family (STM32U5 -Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. -They operate at a frequency of up to 160 MHz. - -- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 1.5 DMPIS/MHz (Drystone 2.1) - - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) - -- Security - - - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals - - Flexible life cycle scheme with RDP (readout protection) and password protected debug - - Root of trust thanks to unique boot entry and secure hide protection area (HDP) - - Secure Firmware Installation thanks to embedded Root Secure Services - - Secure Firmware Update support with TF-M - - HASH hardware accelerator - - Active tampers - - True Random Number Generator NIST SP800-90B compliant - - 96-bit unique ID - - 512-byte One-Time Programmable for user data - -- Clock management: - - - 4 to 50 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - - Internal 48 MHz with clock recovery - -- Power management - - - Embedded regulator (LDO) - - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling - -- RTC with HW calendar and calibration -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- Up to 17 timers and 2 watchdogs - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5 x 16-bit general purpose - - 4x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- ART accelerator - - - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and - external memories: up to 160 MHz, MPU, 240 DMIPS and DSP - - 4-Kbyte data cache for external memories - -- Memories - - - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles - - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON - - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories - - 2 Octo-SPI memory interfaces - -- Rich analog peripherals (independent supply) - - - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling - - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode - - 2 12-bit DAC, low-power sample and hold - - 2 operational amplifiers with built-in PGA - - 2 ultra-low-power comparators - -- Up to 22 communication interfaces - - - USB Type-C / USB power delivery controller - - USB OTG 2.0 full-speed controller - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) - - 1x FDCAN - - 2x SDMMC interface - - 16- and 4-channel DMA controllers, functional in Stop mode - - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with - sound-activity detection - -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| -- True Random Number Generator (RNG) - -- Graphic features - - - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation - - 1 digital camera interface - -- Mathematical co-processor - - - CORDIC for trigonometric functions acceleration - - FMAC (filter mathematical accelerator) - -More information about STM32U575ZI can be found here: - -- `STM32U575ZI on www.st.com`_ -- `STM32U575 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_u575zi_q board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| CAN/CANFD | on-chip | canbus | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| BKP SRAM | on-chip | Backup SRAM | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ - - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig`` - - -Connections and IOs -=================== - -Nucleo U575ZI Q Board has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - - -- CAN/CANFD_TX: PD1 -- CAN/CANFD_RX: PD0 -- DAC1_OUT1 : PA4 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB9 -- I2C_2_SCL : PF1 -- I2C_2_SDA : PF0 -- LD1 : PC7 -- LD2 : PB7 -- LD3 : PG2 -- LPUART_1_TX : PG7 -- LPUART_1_RX : PG8 -- SPI_1_NSS : PA4 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- USER_PB : PC13 - -System Clock ------------- - -Nucleo U575ZI Q System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at -160MHz, driven by 4MHz medium speed internal oscillator. - -Serial Port ------------ - -Nucleo U575ZI Q board has 6 U(S)ARTs. The Zephyr console output is assigned to -USART1. Default settings are 115200 8N1. - - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB50`` jumper on the back side of the board. - - -Programming and Debugging -************************* - -Nucleo U575ZI-Q board includes an ST-LINK/V3 embedded debug tool interface. -This probe allows to flash the board using various tools. - -Flashing -======== - -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. - -Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be -used to flash and debug the board if west is told to use it as runner, -which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``. - -For pyocd additional target information needs to be installed. -This can be done by executing the following commands. - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32u5 - - -Flashing an application to Nucleo U575ZI Q ------------------------------------------- - -Connect the Nucleo U575ZI Q to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_u575zi_q - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -Default flasher for this board is openocd. It could be used in the usual way. -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_u575zi_q - :goals: debug - -Building a secure/non-secure with Arm |reg| TrustZone |reg| -=========================================================== - -The TF-M applications can be run on this board, thanks to its Arm |reg| TrustZone |reg| -support. -In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image -can be generated using ``nucleo_u575zi_q_ns`` as build target. - -.. code-block:: bash - - $ west build -b nucleo_u575zi_q_ns path/to/source/directory - -Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script -is run automatically in a post-build step to make some required flash layout changes. - -Once the build is completed, run the following script to initialize the option bytes. - -.. code-block:: bash - - $ build/tfm/regression.sh - -Finally, to flash the board, run: - -.. code-block:: bash - - $ west flash - -Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts -(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` -(which is used for initialization) is available in the PATH. - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00615305.pdf - -.. _STM32U575ZI on www.st.com: - https://www.st.com/en/microcontrollers/stm32u575zi.html - -.. _STM32U575 reference manual: - https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _STMicroelectronics customized version of OpenOCD: - https://github.com/STMicroelectronics/OpenOCD diff --git a/boards/arm/nucleo_u5a5zj_q/Kconfig.board b/boards/arm/nucleo_u5a5zj_q/Kconfig.board deleted file mode 100644 index 2a1713e0b4f..00000000000 --- a/boards/arm/nucleo_u5a5zj_q/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32U5A5ZJ Q Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_U5A5ZJ_Q - bool "Nucleo U5A5ZJ Q Development Board" - depends on SOC_STM32U5A5XX diff --git a/boards/arm/nucleo_u5a5zj_q/Kconfig.defconfig b/boards/arm/nucleo_u5a5zj_q/Kconfig.defconfig deleted file mode 100644 index ab566327264..00000000000 --- a/boards/arm/nucleo_u5a5zj_q/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32U5A5ZJ Q Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_U5A5ZJ_Q - -config BOARD - default "nucleo_u5a5zj_q" - -endif # BOARD_NUCLEO_U5A5ZJ_Q diff --git a/boards/arm/nucleo_u5a5zj_q/doc/index.rst b/boards/arm/nucleo_u5a5zj_q/doc/index.rst deleted file mode 100644 index f6e96c63517..00000000000 --- a/boards/arm/nucleo_u5a5zj_q/doc/index.rst +++ /dev/null @@ -1,377 +0,0 @@ -.. _nucleo_u5a5zj_q_board: - -ST Nucleo U5A5ZJ Q -################## - -Overview -******** - -The Nucleo U5A5ZJ Q board, featuring an ARM Cortex-M33 based STM32U5A5ZJ MCU, -provides an affordable and flexible way for users to try out new concepts and -build prototypes by choosing from the various combinations of performance and -power consumption features. Here are some highlights of the Nucleo U5A5ZJ Q -board: - - -- STM32U5A5ZJ microcontroller in LQFP144 package -- Internal SMPS to generate V core logic supply -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V3E debugger/programmer -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - ST-Link V3E - -- Three users LEDs -- Two push-buttons: USER and RESET -- USB Type-C ™ Sink device FS - -Hardware -******** - -The STM32U5A5xx devices are an ultra-low-power microcontrollers family (STM32U5 -Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. -They operate at a frequency of up to 160 MHz. - -- Includes ST state-of-the-art patented technology -- Ultra-low-power with FlexPowerControl: - - - 1.71 V to 3.6 V power supply - - -40 °C to +85/125 °C temperature range - - Low-power background autonomous mode (LPBAM): autonomous peripherals with - DMA, functional down to Stop 2 mode - - VBAT mode: supply for RTC, 32 x 32-bit backup registers and 2-Kbyte backup SRAM - - 150 nA Shutdown mode (24 wake-up pins) - - 195 nA Standby mode (24 wake-up pins) - - 480 nA Standby mode with RTC - - 2 µA Stop 3 mode with 40-Kbyte SRAM - - 8.2 µA Stop 3 mode with 2.5-Mbyte SRAM - - 4.65 µA Stop 2 mode with 40-Kbyte SRAM - - 17.5 µA Stop 2 mode with 2.5-Mbyte SRAM - - 18.5 µA/MHz Run mode at 3.3 V - -- Core: - - - Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, - and FPU ART Accelerator - - 32-Kbyte ICACHE allowing 0-wait-state execution from flash and external - memories: frequency up to 160 MHz, 240 DMIPS - - 16-Kbyte DCACHE1 for external memories - -- Power management: - - - Embedded regulator (LDO) and SMPSstep-down converter supporting switch - on-the-fly and voltage scaling - -- Benchmarks: - - - 1.5 DMIPS/MHz (Drystone 2.1) - - 655 CoreMark® (4.09 CoreMark®/MHz) - - 369 ULPMark™-CP - - 89 ULPMark™-PP - - 47.2 ULPMark™-CM - - 120000 SecureMark™-TLS - -- Memories: - - - 4-Mbyte flash memory with ECC, 2 banks readwhile-write, including 512 Kbytes - with 100 kcycles - - With SRAM3 ECC off: 2514-Kbyte RAM including 66 Kbytes with ECC - - With SRAM3 ECC on: 2450-Kbyte RAMincluding 322 Kbytes with ECC - - External memory interface supporting SRAM,PSRAM, NOR, NAND, and FRAM memories - - 2 Octo-SPI memory interfaces - - 16-bit HSPI memory interface up to 160 MHz - -- Rich graphic features: - - - Neo-Chrom GPU (GPU2D) accelerating any angle rotation, scaling, and - perspective correct texture mapping - - 16-Kbyte DCACHE2 - - Chrom-ART Accelerator (DMA2D) for smoothmotion and transparency effects - - Chrom-GRC (GFXMMU) allowing up to 20 % of graphic resources optimization - - MIPI® DSI host controller with two DSI lanes running at up to 500 Mbit/s each - - LCD-TFT controller (LTDC) - - Digital camera interface - -- General-purpose input/outputs: - - - Up to 156 fast I/Os with interrupt capability most 5V-tolerant and - up to 14 I/Os with independent supply down to 1.08 V - -- Clock management: - - - 4 to 50 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC (± 1 %) - - Internal low-power 32 kHz RC (± 5 %) - - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one - autotrimmed by LSE (better than ± 0.25 % accuracy) - - Internal 48 MHz - - 5 PLLs for system clock, USB, audio, ADC, DSI - -- Security and cryptography: - - - SESIP3 and PSA Level 3 Certified Assurance Target - - Arm® TrustZone® and securable I/Os, memories, and peripherals - - Flexible life cycle scheme with RDP andpassword-protected debug - - Root of trust thanks to unique boot entry and secure hide-protection area (HDP) - - Secure firmware installation (SFI) thanks to embedded root secure services (RSS) - - Secure data storage with hardware unique key (HUK) - - Secure firmware upgrade support with TF-M - - 2 AES coprocessors including one with DPA resistance - - Public key accelerator, DPA resistant - - On-the-fly decryption of Octo-SPI external memories - - HASH hardware accelerator - - True random number generator, NIST SP800-90B compliant - - 96-bit unique ID - - 512-byte OTP (one-time programmable) - - Active tampers - -- Up to 17 timers, 2 watchdogs and RTC: - - - 19 timers: 2 16-bit advanced motor-control, 4 32-bit, 3 16-bit general - purpose, 2 16-bit basic, 4 low-power 16-bit (available in Stop mode), - 2 SysTick timers, and 2 watchdogs - - RTC with hardware calendar, alarms, and calibration - -- Up to 25 communication peripherals: - - - 1 USB Type-C®/USB power delivery controller - - 1 USB OTG high-speed with embedded PHY - - 2 SAIs (serial audio interface) - - 6 I2C FM+(1 Mbit/s), SMBus/PMBus™ - - 7 USARTs (ISO 7816, LIN, IrDA, modem) - - 3 SPIs (6x SPIs with OCTOSPI/HSPI) - - 1 CAN FD controller - - 2 SDMMC interfaces - - 1 multifunction digital filter (6 filters) + 1 audio digital filter - with sound-activity detection - - Parallel synchronous slave interface - -- Mathematical coprocessor: - - - CORDIC for trigonometric functions acceleration - - FMAC (filter mathematical accelerator) - -- Rich analog peripherals (independent supply): - - - 2 14-bit ADC 2.5-Msps with hardware oversampling - - 1 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode - - 12-bit DAC (2 channels), low-power sample, and hold, autonomous in Stop 2 mode - - 2 operational amplifiers with built-in PGA - - 2 ultra-low-power comparators - -- ECOPACK2 compliant packages - -More information about STM32U5A5ZJ can be found here: - -- `STM32U5A5ZJ on www.st.com`_ -- `STM32U5A5 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| CAN/CANFD | on-chip | canbus | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| BKP SRAM | on-chip | Backup SRAM | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ - - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig`` - - -Connections and IOs -=================== - -Nucleo U5A5ZJ Q Board has 10 GPIO controllers. These controllers are responsible -for pin muxing, input/output, pull-up, etc. - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - - -- CAN/CANFD_TX: PD1 -- CAN/CANFD_RX: PD0 -- DAC1_OUT1 : PA4 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB9 -- I2C_2_SCL : PF1 -- I2C_2_SDA : PF0 -- LD1 : PC7 -- LD2 : PB7 -- LD3 : PG2 -- LPUART_1_TX : PG7 -- LPUART_1_RX : PG8 -- SPI_1_NSS : PA4 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- USER_PB : PC13 - -System Clock ------------- - -Nucleo U5A5ZJ Q System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at -160MHz, driven by 4MHz medium speed internal oscillator. - -Serial Port ------------ - -Nucleo U5A5ZJ Q board has 6 U(S)ARTs. The Zephyr console output is assigned to -USART1. Default settings are 115200 8N1. - - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB50`` jumper on the back side of the board. - - -Programming and Debugging -************************* - -Nucleo U5A5ZJ-Q board includes an ST-LINK/V3 embedded debug tool interface. -This probe allows to flash the board using various tools. - -Flashing -======== - -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. - -Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be -used to flash and debug the board if west is told to use it as runner, -which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``. - -For pyocd additional target information needs to be installed. -This can be done by executing the following commands. - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32u5 - - -Flashing an application to Nucleo U5A5ZJ Q ------------------------------------------- - -Connect the Nucleo U5A5ZJ Q to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_u5a5zj_q - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -Default flasher for this board is openocd. It could be used in the usual way. -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_u5a5zj_q - :goals: debug - -Building a secure/non-secure with Arm ® TrustZone ® -=========================================================== - -The TF-M applications can be run on this board, thanks to its Arm ® TrustZone ® -support. -In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image -can be generated using ``nucleo_u5a5zj_q_ns`` as build target. - -.. code-block:: bash - - $ west build -b nucleo_u5a5zj_q_ns path/to/source/directory - -Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script -is run automatically in a post-build step to make some required flash layout changes. - -Once the build is completed, run the following script to initialize the option bytes. - -.. code-block:: bash - - $ build/tfm/regression.sh - -Finally, to flash the board, run: - -.. code-block:: bash - - $ west flash - -Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts -(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` -(which is used for initialization) is available in the PATH. - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/um2861-stm32u5-nucleo144-board-mb1549-stmicroelectronics.pdf - -.. _STM32U5A5ZJ on www.st.com: - https://www.st.com/en/microcontrollers/stm32u5a5zj.html - -.. _STM32U5A5 reference manual: - https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _STMicroelectronics customized version of OpenOCD: - https://github.com/STMicroelectronics/OpenOCD diff --git a/boards/arm/nucleo_wb55rg/Kconfig.board b/boards/arm/nucleo_wb55rg/Kconfig.board deleted file mode 100644 index a81009c1259..00000000000 --- a/boards/arm/nucleo_wb55rg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WB55RG Nucleo board configuration - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_WB55RG - bool "Nucleo WB55RG Development Board" - depends on SOC_STM32WB55XX diff --git a/boards/arm/nucleo_wb55rg/Kconfig.defconfig b/boards/arm/nucleo_wb55rg/Kconfig.defconfig deleted file mode 100644 index 66c77220d3a..00000000000 --- a/boards/arm/nucleo_wb55rg/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32LWB55RG Nucleo board configuration - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_WB55RG - -config BOARD - default "nucleo_wb55rg" - -choice BT_HCI_BUS_TYPE - default BT_STM32_IPM - depends on BT -endchoice - -endif # BOARD_NUCLEO_WB55RG diff --git a/boards/arm/nucleo_wba52cg/Kconfig.board b/boards/arm/nucleo_wba52cg/Kconfig.board deleted file mode 100644 index 819c5e1b1f0..00000000000 --- a/boards/arm/nucleo_wba52cg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WBA52CG Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_WBA52CG - bool "Nucleo WBA52CG Development Board" - depends on SOC_STM32WBA52XX diff --git a/boards/arm/nucleo_wba52cg/Kconfig.defconfig b/boards/arm/nucleo_wba52cg/Kconfig.defconfig deleted file mode 100644 index dfdac1bba98..00000000000 --- a/boards/arm/nucleo_wba52cg/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32WBA52CG Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_WBA52CG - -config BOARD - default "nucleo_wba52cg" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_WBA52CG diff --git a/boards/arm/nucleo_wba55cg/Kconfig.board b/boards/arm/nucleo_wba55cg/Kconfig.board deleted file mode 100644 index 44bb0e5dcd8..00000000000 --- a/boards/arm/nucleo_wba55cg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WBA55CG Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_WBA55CG - bool "Nucleo WBA55CG Development Board" - depends on SOC_STM32WBA55XX diff --git a/boards/arm/nucleo_wba55cg/Kconfig.defconfig b/boards/arm/nucleo_wba55cg/Kconfig.defconfig deleted file mode 100644 index ed24776ee4e..00000000000 --- a/boards/arm/nucleo_wba55cg/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32WBA52CG Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_WBA55CG - -config BOARD - default "nucleo_wba55cg" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_WBA55CG diff --git a/boards/arm/nucleo_wl55jc/Kconfig.board b/boards/arm/nucleo_wl55jc/Kconfig.board deleted file mode 100644 index ece57d57da0..00000000000 --- a/boards/arm/nucleo_wl55jc/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WL55JC Nucleo board configuration - -# Copyright (c) 2020 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_WL55JC - bool "Nucleo WL55JC Development Board" - depends on SOC_STM32WL55XX diff --git a/boards/arm/nucleo_wl55jc/Kconfig.defconfig b/boards/arm/nucleo_wl55jc/Kconfig.defconfig deleted file mode 100644 index 981e20f0306..00000000000 --- a/boards/arm/nucleo_wl55jc/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32WL55JC Nucleo board configuration - -# Copyright (c) 2020 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_WL55JC - -config BOARD - default "nucleo_wl55jc" - -endif # BOARD_NUCLEO_WL55JC diff --git a/boards/arm/numaker_pfm_m467/Kconfig.board b/boards/arm/numaker_pfm_m467/Kconfig.board deleted file mode 100644 index 8773aeeacc9..00000000000 --- a/boards/arm/numaker_pfm_m467/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Nuvoton PFM M467 board configuration -# -# Copyright (c) 2023 Nuvoton Technology Corporation. - -config BOARD_NUMAKER_PFM_M467 - bool "NUVOTON PFM M467 Development Board" - depends on SOC_M467 diff --git a/boards/arm/numaker_pfm_m467/Kconfig.defconfig b/boards/arm/numaker_pfm_m467/Kconfig.defconfig deleted file mode 100644 index 97024136df8..00000000000 --- a/boards/arm/numaker_pfm_m467/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Nuvoton PFM M467 board configuration -# -# Copyright (c) 2023 Nuvoton Technology Corporation. - -if BOARD_NUMAKER_PFM_M467 - -config BOARD - default "numaker_pfm_m467" - -if NETWORKING - -config NET_L2_ETHERNET - default y if !MODEM - -endif # NETWORKING - -endif # BOARD_NUMAKER_PFM_M467 diff --git a/boards/arm/numaker_pfm_m467/board.cmake b/boards/arm/numaker_pfm_m467/board.cmake deleted file mode 100644 index 73a61385fd6..00000000000 --- a/boards/arm/numaker_pfm_m467/board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(nulink "-f") -board_runner_args(pyocd "--target=m467hjhae") - -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nulink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/canopen.board.cmake) diff --git a/boards/arm/nuvoton_pfm_m487/Kconfig.board b/boards/arm/nuvoton_pfm_m487/Kconfig.board deleted file mode 100644 index ab31e205a3a..00000000000 --- a/boards/arm/nuvoton_pfm_m487/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Nuvoton PFM M487 board configuration -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -config BOARD_NUVOTON_PFM_M487 - bool "NUVOTON PFM MP487 Development Board" - depends on SOC_M487 diff --git a/boards/arm/nuvoton_pfm_m487/Kconfig.defconfig b/boards/arm/nuvoton_pfm_m487/Kconfig.defconfig deleted file mode 100644 index d9657b64fa4..00000000000 --- a/boards/arm/nuvoton_pfm_m487/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Nuvoton PFM M487 board configuration -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -if BOARD_NUVOTON_PFM_M487 - -config BOARD - default "nuvoton_pfm_m487" - -endif # BOARD_NUVOTON_PFM_M487 diff --git a/boards/arm/nuvoton_pfm_m487/doc/index.rst b/boards/arm/nuvoton_pfm_m487/doc/index.rst deleted file mode 100644 index e5d30c7b764..00000000000 --- a/boards/arm/nuvoton_pfm_m487/doc/index.rst +++ /dev/null @@ -1,98 +0,0 @@ -.. _nuvoton_pfm_m487: - -NUVOTON NUMAKER PFM M487 -######################## - -Overview -******** - -The NuMaker PFM M487 is an Internet of Things (IoT) application focused platform -specially developed by Nuvoton. The PFM-M487 is based on the NuMicro® M487 -Ethernet series MCU with ARM® -Cortex®-M4F core. - -.. image:: pfm_m487.jpg - :align: center - :alt: PFM-M487 - -Features: -========= -- 32-bit Arm Cortex®-M4 M487JIDAE MCU -- Core clock up to 192 MHz -- 512 KB embedded Dual Bank Flash and 160 KB SRAM -- Audio codec (NAU88L25) with Microphone In and Headphone Out -- Ethernet (IP101GR) for network application -- USB 2.0 High-Speed OTG / Host / Device -- USB 1.1 Full-Speed OTG / Host / Device -- External SPI Flash (Winbond W25Q20) which can be regarded as ROM module -- MicroSD Card slot for T-Flash -- M487 extended interface 4 connector with 36 pins each -- Arduino UNO compatible interface -- Three push-buttons: one is for reset and the other two are for user-defined -- Four LEDs: one is for power indication and the other three are for user-defined -- On-board NU-Link-Me ICE debugger/programmer with SWD connector - -More information about the board can be found at the `PFM M487 User Manual`_. - -Supported Features -================== - -* The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 192MHz. - -The development board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port | -+-----------+------------+-----------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -More details about the supported peripherals are available in `M480 TRM`_ -Other hardware features are not currently supported by the Zephyr kernel. - -Building and Flashing -********************* -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -On board debugger Nu-link-Me can emulate UART0 as a virtual COM port over usb, -To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. -Connect the PFM M487 IoT to your host computer using the USB port, then -run a serial host program to connect with your board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nuvoton_pfm_m487 - :goals: flash - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nuvoton_pfm_m487 - :goals: debug - -Step through the application in your debugger. - -References -********** - -.. _PFM M487 User Manual: - https://www.nuvoton.com/export/resource-files/UM_NuMaker-PFM-M487_User_Manual_EN_Rev1.01.pdf -.. _M480 TRM: - https://www.nuvoton.com/export/resource-files/TRM_M480_Series_EN_Rev2.02.pdf diff --git a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.dts b/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.dts deleted file mode 100644 index f9c537307b3..00000000000 --- a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.dts +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2020 Linumiz - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nuvoton_pfm_m487-pinctrl.dtsi" -#include - -/ { - model = "Nuvoton PFM M487 board"; - compatible = "nuvoton,pfm-m487", "nuvoton,m487"; - - aliases { - led0 = &red_led; - led1 = &yellow_led; - led2 = &green_led; - sw0 = &sw2; - sw1 = &sw3; - }; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - leds { - compatible = "gpio-leds"; - red_led: led_0 { - gpios = <&gpioh 0 GPIO_ACTIVE_LOW>; - label = "User LED Red"; - }; - yellow_led: led_1 { - gpios = <&gpioh 1 GPIO_ACTIVE_LOW>; - label = "User LED Yellow"; - }; - green_led: led_2 { - gpios = <&gpioh 2 GPIO_ACTIVE_LOW>; - label = "User LED Green"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - sw2: button_0 { - gpios = <&gpiog 15 GPIO_ACTIVE_LOW>; - label = "User SW2"; - zephyr,code = ; - }; - sw3: button_1 { - gpios = <&gpiof 11 GPIO_ACTIVE_LOW>; - label = "User SW3"; - zephyr,code = ; - }; - }; -}; - -&flash0 { - reg = <0x0 DT_SIZE_K(512)>; -}; - -&sram0 { - reg = <0x20000000 DT_SIZE_K(160)>; -}; - -&gpiob { - status = "okay"; -}; - -&gpiof { - status = "okay"; -}; - -&gpiog { - status = "okay"; -}; - -&gpioh { - status = "okay"; -}; - -&uart0 { - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.yaml b/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.yaml deleted file mode 100644 index c56fb1fd78e..00000000000 --- a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: nuvoton_pfm_m487 -name: NUVOTON-PFM-M487 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 160 -flash: 512 -vendor: nuvoton diff --git a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487_defconfig b/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487_defconfig deleted file mode 100644 index 7c800edd1ba..00000000000 --- a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_M48X=y -CONFIG_SOC_M487=y -CONFIG_BOARD_NUVOTON_PFM_M487=y - -# Enable MPU -CONFIG_ARM_MPU=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=192000000 - -# Enable GPIO and pinctrl drivers -CONFIG_GPIO=y -CONFIG_PINCTRL=y - -# enable uart driver -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.board b/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.board deleted file mode 100644 index ce50e16b3fb..00000000000 --- a/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Olimex LoRa STM32WL DevKit configuration - -# Copyright (c) 2022 Martin Jäger -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_LORA_STM32WL_DEVKIT - bool "Olimex LoRa STM32WL DevKit" - depends on SOC_STM32WLE5XX diff --git a/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.defconfig b/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.defconfig deleted file mode 100644 index 21efeea2fc7..00000000000 --- a/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Olimex LoRa STM32WL DevKit configuration - -# Copyright (c) 2022 Martin Jäger -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_LORA_STM32WL_DEVKIT - -config BOARD - default "olimex_lora_stm32wl_devkit" - -endif # BOARD_OLIMEX_LORA_STM32WL_DEVKIT diff --git a/boards/arm/olimex_lora_stm32wl_devkit/revision.cmake b/boards/arm/olimex_lora_stm32wl_devkit/revision.cmake deleted file mode 100644 index 96501fe7e0b..00000000000 --- a/boards/arm/olimex_lora_stm32wl_devkit/revision.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2023 Kenneth J. Miller -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_check_revision( - FORMAT LETTER - DEFAULT_REVISION B - VALID_REVISIONS A B C D -) diff --git a/boards/arm/olimex_stm32_e407/Kconfig.board b/boards/arm/olimex_stm32_e407/Kconfig.board deleted file mode 100644 index ff092708358..00000000000 --- a/boards/arm/olimex_stm32_e407/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEX-STM32-E407 board configuration - -# Copyright (c) 2017, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_STM32_E407 - bool "OLIMEX-STM32-E407 Development Board" - depends on SOC_STM32F407XG diff --git a/boards/arm/olimex_stm32_e407/Kconfig.defconfig b/boards/arm/olimex_stm32_e407/Kconfig.defconfig deleted file mode 100644 index 28fb1c3f76e..00000000000 --- a/boards/arm/olimex_stm32_e407/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# OLIMEX-STM32-E407 board configuration - -# Copyright (c) 2017, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_STM32_E407 - -config BOARD - default "olimex_stm32_e407" - -endif # BOARD_OLIMEX_STM32_E407 diff --git a/boards/arm/olimex_stm32_h103/Kconfig.board b/boards/arm/olimex_stm32_h103/Kconfig.board deleted file mode 100644 index d2f9e76ae4a..00000000000 --- a/boards/arm/olimex_stm32_h103/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEX-STM32-H103 board configuration - -# Copyright (c) 2020, Josep Puigdemont -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_STM32_H103 - bool "OLIMEX-STM32-H103 Development Board" - depends on SOC_STM32F103XB diff --git a/boards/arm/olimex_stm32_h103/Kconfig.defconfig b/boards/arm/olimex_stm32_h103/Kconfig.defconfig deleted file mode 100644 index 5dd2426b5f6..00000000000 --- a/boards/arm/olimex_stm32_h103/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# OLIMEX-STM32-H103 board configuration - -# Copyright (c) 2020, Josep Puigdemont -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_STM32_H103 - -config BOARD - default "olimex_stm32_h103" - -endif # BOARD_OLIMEX_STM32_H103 diff --git a/boards/arm/olimex_stm32_h405/Kconfig.board b/boards/arm/olimex_stm32_h405/Kconfig.board deleted file mode 100644 index 6559afd8b35..00000000000 --- a/boards/arm/olimex_stm32_h405/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEX-STM32-H405 board configuration - -# Copyright (c) 2020, 2021 Antony Pavlov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_STM32_H405 - bool "OLIMEX STM32-H405 Development Board" - depends on SOC_STM32F405XG diff --git a/boards/arm/olimex_stm32_h405/Kconfig.defconfig b/boards/arm/olimex_stm32_h405/Kconfig.defconfig deleted file mode 100644 index bd334c78807..00000000000 --- a/boards/arm/olimex_stm32_h405/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# OLIMEX-STM32-H405 board configuration - -# Copyright (c) 2020, Antony Pavlov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_STM32_H405 - -config BOARD - default "olimex_stm32_h405" - -endif # BOARD_OLIMEX_STM32_H405 diff --git a/boards/arm/olimex_stm32_h407/Kconfig.board b/boards/arm/olimex_stm32_h407/Kconfig.board deleted file mode 100644 index c08552cd65b..00000000000 --- a/boards/arm/olimex_stm32_h407/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEX-STM32-H407 board configuration - -# Copyright (c) 2018, Reto Schneider -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_STM32_H407 - bool "OLIMEX-STM32-H407 Development Board" - depends on SOC_STM32F407XG diff --git a/boards/arm/olimex_stm32_h407/Kconfig.defconfig b/boards/arm/olimex_stm32_h407/Kconfig.defconfig deleted file mode 100644 index 01a8e749d59..00000000000 --- a/boards/arm/olimex_stm32_h407/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# OLIMEX-STM32-H407 board configuration - -# Copyright (c) 2018, Reto Schneider -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_STM32_H407 - -config BOARD - default "olimex_stm32_h407" - -endif # BOARD_OLIMEX_STM32_H407 diff --git a/boards/arm/olimex_stm32_p405/Kconfig.board b/boards/arm/olimex_stm32_p405/Kconfig.board deleted file mode 100644 index fdc33309849..00000000000 --- a/boards/arm/olimex_stm32_p405/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEX-STM32-P405 board configuration - -# Copyright (c) 2017, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_STM32_P405 - bool "OLIMEX-STM32-P405 Development Board" - depends on SOC_STM32F405XG diff --git a/boards/arm/olimex_stm32_p405/Kconfig.defconfig b/boards/arm/olimex_stm32_p405/Kconfig.defconfig deleted file mode 100644 index 8dc0211bd7f..00000000000 --- a/boards/arm/olimex_stm32_p405/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# OLIMEX-STM32-P405 board configuration - -# Copyright (c) 2017, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_STM32_P405 - -config BOARD - default "olimex_stm32_p405" - -endif # BOARD_OLIMEX_STM32_P405 diff --git a/boards/arm/olimexino_stm32/Kconfig.board b/boards/arm/olimexino_stm32/Kconfig.board deleted file mode 100644 index 902efe68813..00000000000 --- a/boards/arm/olimexino_stm32/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEXINO-STM32 board configuration - -# Copyright (c) 2016, I-SENSE group of ICCS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEXINO_STM32 - bool "OLIMEXINO-STM32 Development Board" - depends on SOC_STM32F103XB diff --git a/boards/arm/olimexino_stm32/Kconfig.defconfig b/boards/arm/olimexino_stm32/Kconfig.defconfig deleted file mode 100644 index 1c90ddc74e2..00000000000 --- a/boards/arm/olimexino_stm32/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# OLIMEXINO-STM32 board configuration - -# Copyright (c) 2016, I-SENSE group of ICCS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEXINO_STM32 - -config BOARD - default "olimexino_stm32" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_OLIMEXINO_STM32 diff --git a/boards/arm/pan1770_evb/Kconfig.board b/boards/arm/pan1770_evb/Kconfig.board deleted file mode 100644 index af61b036701..00000000000 --- a/boards/arm/pan1770_evb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# PAN1770 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PAN1770_EVB - bool "pan1770-evb" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/pan1770_evb/Kconfig.defconfig b/boards/arm/pan1770_evb/Kconfig.defconfig deleted file mode 100644 index e4f718cfb04..00000000000 --- a/boards/arm/pan1770_evb/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# PAN1770 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1770_EVB - -config BOARD - default "pan1770_evb" - -config BT_CTLR - default BT - -endif # BOARD_PAN1770_EVB diff --git a/boards/arm/pan1780_evb/Kconfig.board b/boards/arm/pan1780_evb/Kconfig.board deleted file mode 100644 index 54e8be6cfc3..00000000000 --- a/boards/arm/pan1780_evb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# PAN1780 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PAN1780_EVB - bool "pan1780-evb" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/pan1780_evb/Kconfig.defconfig b/boards/arm/pan1780_evb/Kconfig.defconfig deleted file mode 100644 index 4ce48bcab59..00000000000 --- a/boards/arm/pan1780_evb/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# PAN1780 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1780_EVB - -config BOARD - default "pan1780_evb" - -config BT_CTLR - default BT - -endif # BOARD_PAN1780_EVB diff --git a/boards/arm/pan1781_evb/Kconfig.board b/boards/arm/pan1781_evb/Kconfig.board deleted file mode 100644 index 04c8680dba8..00000000000 --- a/boards/arm/pan1781_evb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# PAN1781 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PAN1781_EVB - bool "pan1781-evb" - depends on SOC_NRF52820_QDAA diff --git a/boards/arm/pan1781_evb/Kconfig.defconfig b/boards/arm/pan1781_evb/Kconfig.defconfig deleted file mode 100644 index 551d01ddd31..00000000000 --- a/boards/arm/pan1781_evb/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# PAN1781 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1781_EVB - -config BOARD - default "pan1781_evb" - -config BT_CTLR - default BT - -endif # BOARD_PAN1781_EVB diff --git a/boards/arm/pan1782_evb/Kconfig.board b/boards/arm/pan1782_evb/Kconfig.board deleted file mode 100644 index 734f1f5dfee..00000000000 --- a/boards/arm/pan1782_evb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# PAN1782 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PAN1782_EVB - bool "pan1782-evb" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/pan1782_evb/Kconfig.defconfig b/boards/arm/pan1782_evb/Kconfig.defconfig deleted file mode 100644 index 465794a8b21..00000000000 --- a/boards/arm/pan1782_evb/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# PAN1782 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1782_EVB - -config BOARD - default "pan1782_evb" - -config BT_CTLR - default BT - -endif # BOARD_PAN1782_EVB diff --git a/boards/arm/pan1783/CMakeLists.txt b/boards/arm/pan1783/CMakeLists.txt deleted file mode 100644 index a582b3cc819..00000000000 --- a/boards/arm/pan1783/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if((CONFIG_BOARD_PAN1783_EVB_CPUAPP OR CONFIG_BOARD_PAN1783A_EVB_CPUAPP OR CONFIG_BOARD_PAN1783A_PA_EVB_CPUAPP) AND (CONFIG_BOARD_ENABLE_CPUNET)) - zephyr_library() - zephyr_library_sources(pan1783_cpunet_reset.c) -endif() diff --git a/boards/arm/pan1783/Kconfig b/boards/arm/pan1783/Kconfig deleted file mode 100644 index e4f58398459..00000000000 --- a/boards/arm/pan1783/Kconfig +++ /dev/null @@ -1,56 +0,0 @@ -# PAN1783 EVB board configuration - -# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1783_EVB_CPUAPP || BOARD_PAN1783A_EVB_CPUAPP || BOARD_PAN1783A_PA_EVB_CPUAPP - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "pan1783_evb_cpunet" if BOARD_PAN1783_EVB_CPUAPP - default "pan1783a_evb_cpunet" if BOARD_PAN1783A_EVB_CPUAPP - default "pan1783a_pa_evb_cpunet" if BOARD_PAN1783A_PA_EVB_CPUAPP - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_PAN1783_EVB_CPUAPP || BOARD_PAN1783A_EVB_CPUAPP || BOARD_PAN1783A_PA_EVB_CPUAPP - -config DOMAIN_CPUAPP_BOARD - string - default "pan1783_evb_cpuapp" if BOARD_PAN1783_EVB_CPUNET - default "pan1783a_evb_cpuapp" if BOARD_PAN1783A_EVB_CPUNET - default "pan1783a_pa_evb_cpuapp" if BOARD_PAN1783A_PA_EVB_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/arm/pan1783/Kconfig.board b/boards/arm/pan1783/Kconfig.board deleted file mode 100644 index 3fcaaf39e56..00000000000 --- a/boards/arm/pan1783/Kconfig.board +++ /dev/null @@ -1,28 +0,0 @@ -# PAN1783 EVB board configuration - -# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PAN1783_EVB_CPUAPP - bool "PAN1783 EVB (nRF5340) Application MCU" - depends on SOC_NRF5340_CPUAPP_QKAA - -config BOARD_PAN1783A_EVB_CPUAPP - bool "PAN1783A EVB (nRF5340) Application MCU" - depends on SOC_NRF5340_CPUAPP_QKAA - -config BOARD_PAN1783A_PA_EVB_CPUAPP - bool "PAN1783A-PA EVB (nRF5340) Application MCU" - depends on SOC_NRF5340_CPUAPP_QKAA - -config BOARD_PAN1783_EVB_CPUNET - bool "PAN1783 EVB (NRF5340) Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA - -config BOARD_PAN1783A_EVB_CPUNET - bool "PAN1783A EVB (NRF5340) Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA - -config BOARD_PAN1783A_PA_EVB_CPUNET - bool "PAN1783A-PA EVB (NRF5340) Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/pan1783/Kconfig.defconfig b/boards/arm/pan1783/Kconfig.defconfig deleted file mode 100644 index 47c02a95b7f..00000000000 --- a/boards/arm/pan1783/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# PAN1783 EVB board configuration - -# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "pan1783_evb_cpuapp" if BOARD_PAN1783_EVB_CPUAPP - default "pan1783a_evb_cpuapp" if BOARD_PAN1783A_EVB_CPUAPP - default "pan1783a_pa_evb_cpuapp" if BOARD_PAN1783A_PA_EVB_CPUAPP - default "pan1783_evb_cpunet" if BOARD_PAN1783_EVB_CPUNET - default "pan1783a_evb_cpunet" if BOARD_PAN1783A_EVB_CPUNET - default "pan1783a_pa_evb_cpunet" if BOARD_PAN1783A_PA_EVB_CPUNET - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_PAN1783_EVB_CPUAPP || BOARD_PAN1783A_EVB_CPUAPP || BOARD_PAN1783A_PA_EVB_CPUAPP - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -endif # BOARD_PAN1783_EVB_CPUAPP || BOARD_PAN1783A_EVB_CPUAPP || BOARD_PAN1783A_PA_EVB_CPUAPP - -if BOARD_PAN1783_EVB_CPUNET || BOARD_PAN1783A_EVB_CPUNET || BOARD_PAN1783A_PA_EVB_CPUNET - -config BT_CTLR - default y if BT - -endif # BOARD_PAN1783_EVB_CPUNET || BOARD_PAN1783A_EVB_CPUNET || BOARD_PAN1783A_PA_EVB_CPUNET diff --git a/boards/arm/pan1783/board.cmake b/boards/arm/pan1783/board.cmake deleted file mode 100644 index e8a33e8c7bf..00000000000 --- a/boards/arm/pan1783/board.cmake +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_PAN1783_EVB_CPUAPP OR CONFIG_BOARD_PAN1783A_EVB_CPUAPP OR CONFIG_BOARD_PAN1783A_PA_EVB_CPUAPP) - board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_BOARD_PAN1783_EVB_CPUNET OR CONFIG_BOARD_PAN1783A_EVB_CPUNET OR CONFIG_BOARD_PAN1783A_PA_EVB_CPUNET) - board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/pan1783/pan1783_cpuapp_common.dtsi b/boards/arm/pan1783/pan1783_cpuapp_common.dtsi deleted file mode 100644 index 77d093a5d40..00000000000 --- a/boards/arm/pan1783/pan1783_cpuapp_common.dtsi +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "pan1783_cpuapp_common-pinctrl.dtsi" -#include - -/ { - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,bt-hci-ipc = &ipc0; - nordic,802154-spinel-ipc = &ipc0; - zephyr,ieee802154 = &ieee802154; - }; - - leds { - compatible = "gpio-leds"; - evb_led1: evb_led_1 { - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - label = "LED1 on EVB"; - }; - evb_led2: evb_led_2 { - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - label = "LED2 on EVB"; - }; - evb_led3: evb_led_3 { - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - label = "LED3 on EVB"; - }; - evb_led4: evb_led_4 { - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - label = "LED4 on EVB"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_evb_led1: pwm_evb_led_1 { - pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - }; - - buttons { - compatible = "gpio-keys"; - evb_sw1: evb_sw_1 { - gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW1 on EVB"; - zephyr,code = ; - }; - evb_sw2: evb_sw_2 { - gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW2 on EVB"; - zephyr,code = ; - }; - evb_sw3: evb_sw_3 { - gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW3 on EVB"; - zephyr,code = ; - }; - evb_sw4: evb_sw_4 { - gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW4 on EVB"; - zephyr,code = ; - }; - }; - - mikrobus_header: mikrobus-connector { - compatible = "mikro-bus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* AN */ - /* Not a GPIO*/ /* RST */ - <2 0 &gpio1 12 0>, /* CS */ - <3 0 &gpio1 15 0>, /* SCK */ - <4 0 &gpio1 14 0>, /* MISO */ - <5 0 &gpio1 13 0>, /* MOSI */ - /* +3.3V */ - /* GND */ - <6 0 &gpio1 7 0>, /* PWM */ - <7 0 &gpio1 4 0>, /* INT */ - <8 0 &gpio1 0 0>, /* RX */ - <9 0 &gpio1 1 0>, /* TX */ - <10 0 &gpio1 3 0>, /* SCL */ - <11 0 &gpio1 2 0>; /* SDA */ - /* +5V */ - /* GND */ - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 0 0>, /* D0 */ - <7 0 &gpio1 1 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 6 0>, /* D4 */ - <11 0 &gpio1 7 0>, /* D5 */ - <12 0 &gpio1 8 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ - }; - - arduino_adc: analog-connector { - compatible = "arduino,uno-adc"; - #io-channel-cells = <1>; - io-channel-map = <0 &adc 0>, /* A0 = P0.4 = AIN0 */ - <1 &adc 1>, /* A1 = P0.5 = AIN1 */ - <2 &adc 2>, /* A2 = P0.6 = AIN2 */ - <3 &adc 3>, /* A3 = P0.7 = AIN3 */ - <4 &adc 4>, /* A4 = P0.25 = AIN4 */ - <5 &adc 5>; /* A5 = P0.26 = AIN5 */ - }; - - gpio_fwd: nrf-gpio-forwarder { - compatible = "nordic,nrf-gpio-forwarder"; - status = "disabled"; - uart { - gpios = <&gpio0 20 0>, <&gpio0 22 0>, <&gpio0 11 0>, <&gpio0 10 0>; - }; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &evb_led1; - led1 = &evb_led2; - led2 = &evb_led3; - led3 = &evb_led4; - pwm-led0 = &pwm_evb_led1; - sw0 = &evb_sw1; - sw1 = &evb_sw2; - sw2 = &evb_sw3; - sw3 = &evb_sw4; - bootloader-led0 = &evb_led1; - mcuboot-button0 = &evb_sw1; - mcuboot-led0 = &evb_led1; - watchdog0 = &wdt0; - spi-flash0 = &mx25r64; - }; -}; - -&adc { - status = "okay"; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c1 { - compatible = "nordic,nrf-twim"; - status = "okay"; - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_default>; - pinctrl-1 = <&pwm0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&qspi { - status = "okay"; - pinctrl-0 = <&qspi_default>; - pinctrl-1 = <&qspi_sleep>; - pinctrl-names = "default", "sleep"; - mx25r64: mx25r6435f@0 { - compatible = "nordic,qspi-nor"; - reg = <0>; - /* MX25R64 supports only pp and pp4io */ - writeoc = "pp4io"; - /* MX25R64 supports all readoc options */ - readoc = "read4io"; - sck-frequency = <8000000>; - jedec-id = [ c2 28 17 ]; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; - size = <67108864>; - has-dpd; - t-enter-dpd = <10000>; - t-exit-dpd = <35000>; - }; -}; - -arduino_serial: &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -arduino_i2c: &i2c1 {}; - -arduino_spi: &spi4 { - compatible = "nordic,nrf-spim"; - status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ - pinctrl-0 = <&spi4_default>; - pinctrl-1 = <&spi4_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -&ieee802154 { - status = "okay"; -}; - -zephyr_udc0: &usbd { - compatible = "nordic,nrf-usbd"; - status = "okay"; -}; - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - }; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "pan1783_cpuapp_partition_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783_cpuapp_partition_conf.dtsi b/boards/arm/pan1783/pan1783_cpuapp_partition_conf.dtsi deleted file mode 100644 index 6eb6792c996..00000000000 --- a/boards/arm/pan1783/pan1783_cpuapp_partition_conf.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for pan1783_evb CPUAPP (Application MCU). - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -/* Default SRAM planning when building for nRF5340 - * - Lowest 448 kB SRAM allocated to Secure image (sram0_s) - * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) - * (see shared_sram_planning_conf.dtsi) - */ -&sram0_image { - reg = <0x20000000 DT_SIZE_K(448)>; -}; - -&sram0_s { - reg = <0x20000000 0x70000>; -}; - -/* Include shared RAM configuration file */ -#include "pan1783_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783_cpunet_common.dtsi b/boards/arm/pan1783/pan1783_cpunet_common.dtsi deleted file mode 100644 index 5b5e7735e4a..00000000000 --- a/boards/arm/pan1783/pan1783_cpunet_common.dtsi +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "pan1783_cpunet-pinctrl.dtsi" -#include - -/ { - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,bt-hci-ipc = &ipc0; - nordic,802154-spinel-ipc = &ipc0; - zephyr,ieee802154 = &ieee802154; - }; - - leds { - compatible = "gpio-leds"; - evb_led1: evb_led_1 { - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - label = "LED1 on EVB"; - }; - evb_led2: evb_led_2 { - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - label = "LED2 on EVB"; - }; - evb_led3: evb_led_3 { - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - label = "LED3 on EVB"; - }; - evb_led4: evb_led_4 { - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - label = "LED4 on EVB"; - }; - }; - - buttons { - compatible = "gpio-keys"; - evb_sw1: evb_sw_1 { - gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW1 on EVB"; - zephyr,code = ; - }; - evb_sw2: evb_sw_2 { - gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW2 on EVB"; - zephyr,code = ; - }; - evb_sw3: evb_sw_3 { - gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW3 on EVB"; - zephyr,code = ; - }; - evb_sw4: evb_sw_4 { - gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW4 on EVB"; - zephyr,code = ; - }; - }; - - mikrobus_header: mikrobus-connector { - compatible = "mikro-bus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* AN */ - /* Not a GPIO*/ /* RST */ - <2 0 &gpio1 12 0>, /* CS */ - <3 0 &gpio1 15 0>, /* SCK */ - <4 0 &gpio1 14 0>, /* MISO */ - <5 0 &gpio1 13 0>, /* MOSI */ - /* +3.3V */ - /* GND */ - <6 0 &gpio1 7 0>, /* PWM */ - <7 0 &gpio1 4 0>, /* INT */ - <8 0 &gpio1 0 0>, /* RX */ - <9 0 &gpio1 1 0>, /* TX */ - <10 0 &gpio1 3 0>, /* SCL */ - <11 0 &gpio1 2 0>; /* SDA */ - /* +5V */ - /* GND */ - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 0 0>, /* D0 */ - <7 0 &gpio1 1 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 6 0>, /* D4 */ - <11 0 &gpio1 7 0>, /* D5 */ - <12 0 &gpio1 8 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &evb_led1; - led1 = &evb_led2; - led2 = &evb_led3; - led3 = &evb_led4; - sw0 = &evb_sw1; - sw1 = &evb_sw2; - sw2 = &evb_sw3; - sw3 = &evb_sw4; - bootloader-led0 = &evb_led1; - mcuboot-button0 = &evb_sw1; - mcuboot-led0 = &evb_led1; - watchdog0 = &wdt0; - }; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&uart0 { - status = "disabled"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -arduino_serial: &uart0 {}; - -arduino_i2c: &i2c0 { - compatible = "nordic,nrf-twim"; - /* Cannot be used together with uart0. */ - /* status = "okay"; */ - pinctrl-0 = <&i2c0_default>; - pinctrl-1 = <&i2c0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -arduino_spi: &spi0 { - compatible = "nordic,nrf-spim"; - /* Cannot be used together with uart0. */ - /* status = "okay"; */ - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ - pinctrl-0 = <&spi0_default>; - pinctrl-1 = <&spi0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash1 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0xc000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x17000>; - }; - slot1_partition: partition@23000 { - label = "image-1"; - reg = <0x00023000 0x17000>; - }; - storage_partition: partition@3a000 { - label = "storage"; - reg = <0x0003a000 0x6000>; - }; - }; -}; - -&ieee802154 { - status = "okay"; -}; - -/* Include shared RAM configuration file */ -#include "pan1783_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783_cpunet_reset.c b/boards/arm/pan1783/pan1783_cpunet_reset.c deleted file mode 100644 index 529051ec629..00000000000 --- a/boards/arm/pan1783/pan1783_cpunet_reset.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include -#include - -#if defined(CONFIG_BOARD_PAN1783_EVB_CPUAPP) -LOG_MODULE_REGISTER(pan1783_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); -#elif defined(CONFIG_BOARD_PAN1783A_EVB_CPUAPP) -LOG_MODULE_REGISTER(pan1783a_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); -#elif defined(CONFIG_BOARD_PAN1783A_PA_EVB_CPUAPP) -LOG_MODULE_REGISTER(pan1783a_pa_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); -#else -#error "No board selected!" -#endif - -#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) -#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> -#else -#define DEBUG_SETUP() -#endif - -static void remoteproc_mgr_config(void) -{ - /* Route Bluetooth Controller Debug Pins */ - DEBUG_SETUP(); - - /* Retain nRF5340 Network MCU */ - NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; -} - -static int remoteproc_mgr_boot(void) -{ - /* Configure permissions for the Network MCU. */ - remoteproc_mgr_config(); - - /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); - - LOG_DBG("Network MCU released."); - - return 0; -} - -SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/arm/pan1783/pan1783_evb_cpuapp.dts b/boards/arm/pan1783/pan1783_evb_cpuapp.dts deleted file mode 100644 index 54f71dd87d5..00000000000 --- a/boards/arm/pan1783/pan1783_evb_cpuapp.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpuapp_common.dtsi" - -/ { - model = "Panasonic PAN1783 EVB (NRF5340) Application"; - compatible = "panasonic,pan1783-evb-cpuapp"; - - chosen { - zephyr,sram = &sram0_image; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,sram-secure-partition = &sram0_s; - }; -}; diff --git a/boards/arm/pan1783/pan1783_evb_cpuapp.yaml b/boards/arm/pan1783/pan1783_evb_cpuapp.yaml deleted file mode 100644 index a0242b83252..00000000000 --- a/boards/arm/pan1783/pan1783_evb_cpuapp.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: pan1783_evb_cpuapp -name: PAN1783-EVB-application-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 448 -flash: 1024 -supported: - - gpio - - i2c - - i2s - - pwm - - watchdog - - usb_cdc - - usb_device - - netif:openthread - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783_evb_cpuapp_defconfig b/boards/arm/pan1783/pan1783_evb_cpuapp_defconfig deleted file mode 100644 index b709d16dc54..00000000000 --- a/boards/arm/pan1783/pan1783_evb_cpuapp_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_PAN1783_EVB_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783_evb_cpunet.dts b/boards/arm/pan1783/pan1783_evb_cpunet.dts deleted file mode 100644 index 7063e53af46..00000000000 --- a/boards/arm/pan1783/pan1783_evb_cpunet.dts +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpunet_common.dtsi" - -/ { - model = "Panasonic PAN1783 EVB (NRF5340) Network"; - compatible = "panasonic,pan1783-evb-cpunet"; - - chosen { - zephyr,sram = &sram1; - zephyr,flash = &flash1; - zephyr,code-partition = &slot0_partition; - }; -}; - -/* Include shared RAM configuration file */ -#include "pan1783_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783_evb_cpunet.yaml b/boards/arm/pan1783/pan1783_evb_cpunet.yaml deleted file mode 100644 index 725fae94cc5..00000000000 --- a/boards/arm/pan1783/pan1783_evb_cpunet.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: pan1783_evb_cpunet -name: PAN1783-EVB-network-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - watchdog - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783_evb_cpunet_defconfig b/boards/arm/pan1783/pan1783_evb_cpunet_defconfig deleted file mode 100644 index f83ea000455..00000000000 --- a/boards/arm/pan1783/pan1783_evb_cpunet_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_PAN1783_EVB_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783a_evb_cpuapp.dts b/boards/arm/pan1783/pan1783a_evb_cpuapp.dts deleted file mode 100644 index 29f0dcb796c..00000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpuapp.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpuapp_common.dtsi" - -/ { - model = "Panasonic PAN1783A EVB (NRF5340) Application"; - compatible = "panasonic,pan1783a-evb-cpuapp"; - - chosen { - zephyr,sram = &sram0_image; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,sram-secure-partition = &sram0_s; - }; -}; diff --git a/boards/arm/pan1783/pan1783a_evb_cpuapp.yaml b/boards/arm/pan1783/pan1783a_evb_cpuapp.yaml deleted file mode 100644 index 2a89c3f1f37..00000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpuapp.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: pan1783a_evb_cpuapp -name: PAN1783A-EVB-application-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 448 -flash: 1024 -supported: - - gpio - - i2c - - i2s - - pwm - - watchdog - - usb_cdc - - usb_device - - netif:openthread - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783a_evb_cpuapp_defconfig b/boards/arm/pan1783/pan1783a_evb_cpuapp_defconfig deleted file mode 100644 index 2f624e1db0c..00000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpuapp_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_PAN1783A_EVB_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783a_evb_cpunet.dts b/boards/arm/pan1783/pan1783a_evb_cpunet.dts deleted file mode 100644 index 9cd0409a432..00000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpunet.dts +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpunet_common.dtsi" - -/ { - model = "Panasonic PAN1783A EVB (NRF5340) Network"; - compatible = "panasonic,pan1783a-evb-cpunet"; - - chosen { - zephyr,sram = &sram1; - zephyr,flash = &flash1; - zephyr,code-partition = &slot0_partition; - }; -}; - -/* Include shared RAM configuration file */ -#include "pan1783_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783a_evb_cpunet.yaml b/boards/arm/pan1783/pan1783a_evb_cpunet.yaml deleted file mode 100644 index 2dd985f61ff..00000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpunet.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: pan1783a_evb_cpunet -name: PAN1783A-EVB-network-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - watchdog - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783a_evb_cpunet_defconfig b/boards/arm/pan1783/pan1783a_evb_cpunet_defconfig deleted file mode 100644 index 3e44ff7338c..00000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpunet_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_PAN1783A_EVB_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.dts b/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.dts deleted file mode 100644 index aba6e9281e2..00000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpuapp_common.dtsi" - -/ { - model = "Panasonic PAN1783A-PA EVB (NRF5340) Application"; - compatible = "panasonic,pan1783a_pa-evb-cpuapp"; - - chosen { - zephyr,sram = &sram0_image; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,sram-secure-partition = &sram0_s; - }; -}; - -&gpio_fwd { - /delete-node/ uart; - - status = "okay"; - fem { - gpios = <&gpio0 19 0>, <&gpio0 21 0>; - }; -}; diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.yaml b/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.yaml deleted file mode 100644 index 0bc70dab273..00000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: pan1783a_pa_evb_cpuapp -name: PAN1783A-PA-EVB-application-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 448 -flash: 1024 -supported: - - gpio - - i2c - - i2s - - pwm - - watchdog - - usb_cdc - - usb_device - - netif:openthread - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp_defconfig b/boards/arm/pan1783/pan1783a_pa_evb_cpuapp_defconfig deleted file mode 100644 index f58bdce8bfc..00000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_PAN1783A_PA_EVB_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpunet.dts b/boards/arm/pan1783/pan1783a_pa_evb_cpunet.dts deleted file mode 100644 index 1b345aaa945..00000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpunet.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpunet_common.dtsi" - -/ { - model = "Panasonic PAN1783A-PA EVB (NRF5340) Network"; - compatible = "panasonic,pan1783a_pa-evb-cpunet"; - - chosen { - zephyr,sram = &sram1; - zephyr,flash = &flash1; - zephyr,code-partition = &slot0_partition; - }; - - nrf_radio_fem: fem_node { - compatible = "skyworks,sky66407-11", "generic-fem-two-ctrl-pins"; - ctx-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - crx-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; -}; - -&radio { - fem = <&nrf_radio_fem>; -}; - -/* Include shared RAM configuration file */ -#include "pan1783_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpunet.yaml b/boards/arm/pan1783/pan1783a_pa_evb_cpunet.yaml deleted file mode 100644 index 98a2f2908de..00000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpunet.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: pan1783a_pa_evb_cpunet -name: PAN1783A-PA-EVB-network-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - watchdog - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpunet_defconfig b/boards/arm/pan1783/pan1783a_pa_evb_cpunet_defconfig deleted file mode 100644 index 3ba18cd433a..00000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpunet_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_PAN1783A_PA_EVB_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pandora_stm32l475/Kconfig.board b/boards/arm/pandora_stm32l475/Kconfig.board deleted file mode 100644 index 89ba1c54b98..00000000000 --- a/boards/arm/pandora_stm32l475/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L475 Pandora board configuration - -# Copyright (c) 2023 Tisilicon -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PANDORA_STM32L475 - bool "STM32L475 Pandora Development Board" - depends on SOC_STM32L475XX diff --git a/boards/arm/pandora_stm32l475/Kconfig.defconfig b/boards/arm/pandora_stm32l475/Kconfig.defconfig deleted file mode 100644 index 2d0f4e8c456..00000000000 --- a/boards/arm/pandora_stm32l475/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32L475 Pandora board configuration - -# Copyright (c) 2023 Tisilicon -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PANDORA_STM32L475 - -config BOARD - default "pandora_stm32l475" - -endif # BOARD_PANDORA_STM32L475 diff --git a/boards/arm/pandora_stm32l475/doc/index.rst b/boards/arm/pandora_stm32l475/doc/index.rst deleted file mode 100644 index 76da038e9ec..00000000000 --- a/boards/arm/pandora_stm32l475/doc/index.rst +++ /dev/null @@ -1,214 +0,0 @@ -.. _stm32l475ve_pandora_board: - -Alientek STM32L475 Pandora -########################## - -Overview -******** - -The STM32L475 Pandora board features an ARM Cortex-M4 based STM32L475VE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the STM32L475 Pandora board: - - -- STM32L475Vx microcontroller featuring 1 Mbyte of Flash memory, 128 Kbytes of RAM in LQFP100 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- Three different interfaces supported on USB: - - - Virtual com port - - Mass storage - - Debug port - -- Pushbutton (reset) -- Four directions Joystick with selection -- USB OTG FS with micro-AB connector -- SAI Audio DAC, Stereo with output jack -- Digital microphone, accelerometer, magnetometer and gyroscope MEMS -- 128-Mbit Quad-SPI Flash memory -- MCU current ammeter with 4 ranges and auto-calibration -- Connector for external board or RF-EEPROM -- Four power supply options: - - ST-LINK/V2-1 - - USB FS connector - - External 5 V - - CR2032 battery (not provided) - -.. image:: img/pandora_stm32l475.jpg - :align: center - :alt: STM32L475 Pandora - -More information about the board can be found at the `STM32L475 Pandora website`_. - -Hardware -******** - -The STM32L475VE SoC provides the following hardware features: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC -- RTC with HW calendar, alarms and calibration -- 16x timers: - - 2x 16-bit advanced motor-control - - 2x 32-bit and 7x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer -- Up to 82 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 128 KB of SRAM including 32 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators -- 18x communication interfaces - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (4x SPIs with the Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -Supported Features -================== - -The Zephyr stm32l475ve_pandora board configuration supports the following hardware features: - -+-----------+------------+----------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==============================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+----------------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+----------------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+----------------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------------------------------+ -| I2C | on-chip | I2C-AHT10(Temperature and humidity sensor) | -| | | I2C-ICM2068(light environment sensor) | -+-----------+------------+----------------------------------------------+ -| I2S | on-chip | I2S-ES8388(Audio Decoder) | -+-----------+------------+----------------------------------------------+ -| USB | on-chip | I2S-OTG | -+-----------+------------+----------------------------------------------+ -| SDIO | on-chip | SDIO-AP6181(WIFI) | -+-----------+------------+----------------------------------------------+ -| SPI | on-chip | LCD-TFT | -+-----------+------------+----------------------------------------------+ -| QSPI NOR | on-chip | flash | -+-----------+------------+----------------------------------------------+ -| IR-RX/TX | on-board | Infrared Receiver(38Khz)/Transmitter | -+-----------+------------+----------------------------------------------+ -| STLINK-V2 | on-board | STLINK-V2 Debugger | -+-----------+------------+----------------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/pandora_stm32l475/pandora_stm32l475_defconfig`` - - -Connections and IOs -=================== - -STM32L475 Pandora Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32L475 Pandora board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- LED_R : PE7 -- LED_G : PE8 -- LED_B : PE9 - -System Clock ------------- - -STM32L475 Pandora System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -STM32L475 Pandora board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -STM32L475 Pandora board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32L475 Pandora --------------------------------------------- - -Connect the STM32L475 Pandora to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l475ve_pandora - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l475ve_pandora - :maybe-skip-config: - :goals: debug - -.. _STM32L475 Pandora website: - http://www.openedv.com/docs/boards/iot/zdyz_panduola.html - -.. _STM32L475 Pandora board User Manual: - http://www.openedv.com/thread-284556-1-1.html diff --git a/boards/arm/particle_argon/Kconfig.board b/boards/arm/particle_argon/Kconfig.board deleted file mode 100644 index 8b8aa29e3bc..00000000000 --- a/boards/arm/particle_argon/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Particle Argon configuration - -# Copyright (c) 2018 Matthias Boesl -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PARTICLE_ARGON - bool "Particle Argon Board" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/particle_argon/Kconfig.defconfig b/boards/arm/particle_argon/Kconfig.defconfig deleted file mode 100644 index df988c09cd8..00000000000 --- a/boards/arm/particle_argon/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Particle Argon board configuration - -# Copyright (c) 2018 Matthias Boesl -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PARTICLE_ARGON - -config BOARD - default "particle_argon" - -config BT_CTLR - default BT - -endif # BOARD_PARTICLE_ARGON diff --git a/boards/arm/particle_boron/Kconfig.board b/boards/arm/particle_boron/Kconfig.board deleted file mode 100644 index 17273fbf761..00000000000 --- a/boards/arm/particle_boron/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Particle Boron configuration - -# Copyright (c) 2018 Peter Bigot Consulting, LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PARTICLE_BORON - bool "Particle Boron Board" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/particle_boron/Kconfig.defconfig b/boards/arm/particle_boron/Kconfig.defconfig deleted file mode 100644 index 9352289086c..00000000000 --- a/boards/arm/particle_boron/Kconfig.defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# Particle Boron board configuration - -# Copyright (c) 2018 Peter Bigot Consulting, LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PARTICLE_BORON - -config BOARD - default "particle_boron" - -config BT_CTLR - default BT - -if MODEM - -config MODEM_UBLOX_SARA - default y - -choice MODEM_UBLOX_SARA_VARIANT - default MODEM_UBLOX_SARA_R4 -endchoice - -config UART_INTERRUPT_DRIVEN - default y - -endif # MODEM - -endif # BOARD_PARTICLE_BORON diff --git a/boards/arm/particle_xenon/Kconfig.board b/boards/arm/particle_xenon/Kconfig.board deleted file mode 100644 index 918ad23e8cd..00000000000 --- a/boards/arm/particle_xenon/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Particle Xenon configuration - -# Copyright (c) 2018 Endre Karlson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PARTICLE_XENON - bool "Particle Xenon Board" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/particle_xenon/Kconfig.defconfig b/boards/arm/particle_xenon/Kconfig.defconfig deleted file mode 100644 index 858a1230726..00000000000 --- a/boards/arm/particle_xenon/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Particle Xenon board configuration - -# Copyright (c) 2018 Endre Karlson -# Copyright (c) 2018 Peter Bigot Consulting, LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PARTICLE_XENON - -config BOARD - default "particle_xenon" - -config BT_CTLR - default BT - -endif # BOARD_PARTICLE_XENON diff --git a/boards/arm/particle_xenon/particle_xenon_defconfig b/boards/arm/particle_xenon/particle_xenon_defconfig deleted file mode 100644 index 8c7246fad1c..00000000000 --- a/boards/arm/particle_xenon/particle_xenon_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2018, Endre Karlson -# -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PARTICLE_XENON=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/pico_pi_m4/Kconfig.board b/boards/arm/pico_pi_m4/Kconfig.board deleted file mode 100644 index e980c3d1ec9..00000000000 --- a/boards/arm/pico_pi_m4/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Pico-Pi iMX7D M4 board - -# Copyright (c) 2019, Joris Offouga -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PICO_PI_M4 - bool "Pico-PI iMX7D Dual" - depends on SOC_SERIES_IMX7_M4 diff --git a/boards/arm/pico_pi_m4/Kconfig.defconfig b/boards/arm/pico_pi_m4/Kconfig.defconfig deleted file mode 100644 index fb3f7cd2f89..00000000000 --- a/boards/arm/pico_pi_m4/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Pico-Pi iMX7D M4 board - -# Copyright (c) 2019, Joris Offouga -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PICO_PI_M4 - -config BOARD - default "pico_pi_m4" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_PICO_PI_M4 diff --git a/boards/arm/pico_pi_m4/doc/index.rst b/boards/arm/pico_pi_m4/doc/index.rst deleted file mode 100644 index 8e3c4e832c8..00000000000 --- a/boards/arm/pico_pi_m4/doc/index.rst +++ /dev/null @@ -1,239 +0,0 @@ -.. _pico_pi_m4: - -Pico-Pi i.MX7D - Android Things IoT Development Platform -############################################################# - -Overview -******** - -The i.MX7D SoC is a Hybrid multi-core processor composed of Single Cortex A7 -core and Single Cortex M4 core. -Zephyr was ported to run on the M4 core. In a later release, it will also -communicate with the A7 core (running Linux) via RPmsg. - - -.. image:: pico_pi_m4.jpg - :align: center - :alt: Pico-Pi i.MX7D - -Hardware -******** - -The Pico-Pi Platform is composed of a CPU and IO board. - -Pico-Pi IO Board -================ -- S1 - On/Off (MX7_ONOFF signal) -- Board to board connector : Edison compatible connector (70 configurable pins) -- mikroBUS expansion connector ADC, GPIO, I²C, PWM, SPI, UART) -- 10-pin needle JTAG Connector -- Debug USB exposing One UART -- MIPI DSI 1 lane Connector -- LCD Touch Connector -- Audio Jack: Mic and Stereo Headphone - -Pico-Pi CPU Board -================= - -- CPU i.MX7 Dual with a Single Cortex A7 (1 GHz) core and - Single Cortex M4 (200MHz) core -- Memory - - - RAM -> A7: 4GB - - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) - - Flash -> A7: 8GB eMMC - -For more information about the i.MX7 SoC and Pico-Pi i.MX7D, see these references: - -- `i.MX 7 Series Website`_ -- `i.MX 7 Dual Datasheet`_ -- `i.MX 7 Dual Reference Manual`_ - -Supported Features -================== - -The Pico-Pi i.MX7D configuration supports the following hardware features on the -Cortex M4 Core: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/pico_pi_m4/pico_pi_m4_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The Pico-Pi board Board was tested with the following pinmux controller -configuration. - -+---------------+---------------------+--------------------------------+ -| Board Name | SoC Name | Usage | -+===============+=====================+================================+ -| UART_TX232 | UART1_TX | UART Console | -+---------------+---------------------+--------------------------------+ -| UART_RX232 | UART1_RX | UART Console | -+---------------+---------------------+--------------------------------+ -| RX_E | UART6_TX | UART (mikroBUS and Edison) | -+---------------+---------------------+--------------------------------+ -| TX_E | UART6_RX | UART (mikroBUS and Edison) | -+---------------+---------------------+--------------------------------+ -| I2CX_SDA_3V | I2C1_SDA | I2C (mikroBUS and Edison) | -+---------------+---------------------+--------------------------------+ -| I2CX_SCL_3V | I2C1_SCL | I2C (mikroBUS and Edison) | -+---------------+---------------------+--------------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 200 MHz clock speed. - -Serial Port -=========== - -The iMX7D SoC has seven UARTs. The number 6 is configured for the console and -the number 2 is used in the mikroBUS connector. - -Programming and Debugging -************************* - -The Pico-Pi i.MX7D doesn't have QSPI flash for the M4 and it needs to be started by -the A7 core. The A7 core is responsible to load the M4 binary application into -the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and -get the M4 out of reset. -The A7 can perform these steps at bootloader level or after the Linux system -has booted. - -The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and -M4: - -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=======================+========================+=======================+======================+ -| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ - -References -========== - -- `i.MX 7 Dual Reference Manual`_ from page 182 (section 2.1.2 and 2.1.3) -- `Toradex Wiki`_ - - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/pico_pi_m4/pico_pi_m4.dts`` with -"zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. The available -configurations are: - -.. code-block:: none - - "zephyr,flash" - - &ddr_code - - &tcml_code - - &ocram_code - - &ocram_s_code - - &ocram_pxp_code - - &ocram_epdc_code - - "zephyr,sram" - - &ddr_sys - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - - &ocram_pxp_sys - - &ocram_epdc_sys - - -Below you will find the instructions to load and run Zephyr on M4 from A7 using -u-boot. - -Connect both micro USB interfaces into the PC. This is the A7 console and the -UART6 in the Edison connector is M4 console for Zephyr with both configured to work at 115200 8N1. -The USB interface is used to power the CPU and IO boards and is connected -to the USB OTG interface of the i.MX7D. - -After powering up the platform stop the u-boot execution on the A7 core and -expose the eMMC as mass storage with the following command in the u-boot -prompt: ``ums 0 mmc 0``. Copy the compiled zephyr.bin to the first FAT -partition and remove the mounted device on the PC by issuing a "Ctrl+C" in the -u-boot prompt. -Set the u-boot environment variables and run the zephyr.bin from the -appropriated memory configured in the Zephyr compilation: - -.. code-block:: console - - setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' - # TCML - setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' - setenv bootm4tcml 'run m4tcml && run bootm4' - run bootm4tcml - # TCMU - setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' - setenv bootm4tcmu 'run m4tcmu && run bootm4' - run bootm4tcmu - # OCRAM - setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' - setenv bootm4ocram 'run m4ocram && run bootm4' - run bootm4ocram - # OCRAM_S - setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' - setenv bootm4ocrams 'run m4ocrams && run bootm4' - run bootm4ocrams - # DDR - setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' - setenv bootm4ddr 'run m4ddr && run bootm4' - run bootm4ddr - -:ref:`build_an_application` and :ref:`application_run` for more details). - -References -========== - -- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ -- `J-Link iMX7D Instructions`_ - -.. _i.MX 7 Series Website: - https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 - -.. _i.MX 7 Dual Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf - -.. _i.MX 7 Dual Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX7DRM - -.. _J-Link Tools: - https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack - -.. _NXP iMX7D Connect CortexM4.JLinkScript: - https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript - -.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: - https://www.nxp.com/docs/en/application-note/AN5317.pdf - -.. _J-Link iMX7D Instructions: - https://wiki.segger.com/IMX7D - -.. _Toradex Wiki: - https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/pico_pi_m4/pico_pi_m4.dts b/boards/arm/pico_pi_m4/pico_pi_m4.dts deleted file mode 100644 index ecc1b2d41d9..00000000000 --- a/boards/arm/pico_pi_m4/pico_pi_m4.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2019, Joris Offouga - * Copyright 2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "pico_pi_m4-pinctrl.dtsi" - -/ { - model = "Pico-Pi IMX7D board"; - compatible = "nxp,mcimx7d_m4"; - - aliases { - uart-6 = &uart6; - }; - - chosen { - zephyr,flash = &tcml_code; - zephyr,sram = &tcmu_sys; - zephyr,console = &uart6; - zephyr,shell-uart = &uart6; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&uart5 { - pinctrl-0 = <&uart5_default>; - pinctrl-names = "default"; -}; - -&uart6 { - status = "okay"; - current-speed = <115200>; - modem-mode = <0>; - pinctrl-0 = <&uart6_default>; - pinctrl-names = "default"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_default>; - pinctrl-names = "default"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_default>; - pinctrl-names = "default"; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/pico_pi_m4/pico_pi_m4.yaml b/boards/arm/pico_pi_m4/pico_pi_m4.yaml deleted file mode 100644 index 8cc013a4e36..00000000000 --- a/boards/arm/pico_pi_m4/pico_pi_m4.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2019, Joris Offouga -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: pico_pi_m4 -name: Pico-Pi IMX7D -type: mcu -arch: arm -ram: 32 -flash: 32 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -vendor: nxp diff --git a/boards/arm/pico_pi_m4/pico_pi_m4_defconfig b/boards/arm/pico_pi_m4/pico_pi_m4_defconfig deleted file mode 100644 index d2e77138089..00000000000 --- a/boards/arm/pico_pi_m4/pico_pi_m4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2019, Joris Offouga -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX7_M4=y -CONFIG_SOC_MCIMX7_M4=y -CONFIG_BOARD_PICO_PI_M4=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_GPIO=n -CONFIG_PINCTRL=y diff --git a/boards/arm/pinetime_devkit0/Kconfig.board b/boards/arm/pinetime_devkit0/Kconfig.board deleted file mode 100644 index 7b4cd93e718..00000000000 --- a/boards/arm/pinetime_devkit0/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# PineTime DevKit0 board configuration - -# Copyright (c) 2020 Stephane Dorre -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PINETIME_DEVKIT0 - bool "PineTime DevKit0" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/pinetime_devkit0/Kconfig.defconfig b/boards/arm/pinetime_devkit0/Kconfig.defconfig deleted file mode 100644 index a90333d54a7..00000000000 --- a/boards/arm/pinetime_devkit0/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# PineTime DevKit0 board configuration - -# Copyright (c) 2020 Stephane Dorre -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PINETIME_DEVKIT0 - -config BOARD - default "pinetime_devkit0" - -config BT_CTLR - default BT - -config INPUT - default y if LVGL - -if FLASH - -config SPI_NOR_FLASH_LAYOUT_PAGE_SIZE - default 4096 - -endif # FLASH - -endif # BOARD_PINETIME_DEVKIT0 diff --git a/boards/arm/pinetime_devkit0/pinetime_devkit0_defconfig b/boards/arm/pinetime_devkit0/pinetime_devkit0_defconfig deleted file mode 100644 index ce594faf969..00000000000 --- a/boards/arm/pinetime_devkit0/pinetime_devkit0_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_PINETIME_DEVKIT0=y - -CONFIG_ARM_MPU=y - -CONFIG_GPIO=y - -CONFIG_SERIAL=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/pinnacle_100_dvk/Kconfig.board b/boards/arm/pinnacle_100_dvk/Kconfig.board deleted file mode 100644 index adbb23e41d8..00000000000 --- a/boards/arm/pinnacle_100_dvk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Pinnacle(TM) 100 DVK board configuration -# -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PINNACLE_100_DVK - bool "Pinnacle 100 DVK" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/pinnacle_100_dvk/Kconfig.defconfig b/boards/arm/pinnacle_100_dvk/Kconfig.defconfig deleted file mode 100644 index e2496016997..00000000000 --- a/boards/arm/pinnacle_100_dvk/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Pinnacle(TM) 100 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PINNACLE_100_DVK - -config BOARD - default "pinnacle_100_dvk" - -config MODEM - default NETWORKING - -config MODEM_HL7800 - default NETWORKING - -config NORDIC_QSPI_NOR - default BOOTLOADER_MCUBOOT - -config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE - default 4096 if NORDIC_QSPI_NOR - -config BT_CTLR - default BT - -endif # BOARD_PINNACLE_100_DVK diff --git a/boards/arm/pinnacle_100_dvk/doc/index.rst b/boards/arm/pinnacle_100_dvk/doc/index.rst deleted file mode 100644 index 528b0f731f5..00000000000 --- a/boards/arm/pinnacle_100_dvk/doc/index.rst +++ /dev/null @@ -1,220 +0,0 @@ -.. _pinnacle_100_dvk: - -Laird Connectivity Pinnacle 100 DVK -################################### - -Overview -******** -The Pinnacle™ 100 cellular modem seamlessly incorporates a powerful Cortex M4F -controller, full Bluetooth 5 and LTE-M/NB-IoT capabilities – all with full -regulatory certifications and LTE carrier approvals. The Pinnacle 100 also -delivers complete antenna flexibility, with pre-integrated internal or external -antenna options such as the Revie Flex family of LTE and NB-IoT -internal antennas. - -Develop your application directly on the M4F controller using Zephyr RTOS to -cut BOM costs and power consumption. Take advantage of the Zephyr community, -Laird Connectivity’s sample code (cellular, Bluetooth) and hardware interfaces, -or use our hosted mode AT commands set firmware. - -Extremely power conscious, the Pinnacle 100 is ideal for battery-powered -devices operating at the edge of your IoT networks, seamlessly bridging the -cellular WAN to BLE. It’s never been easier to bridge wireless -Bluetooth 5 sensor data to cloud services like AWS IoT over a -low-power LTE connection. - -More information about the board can be found at the `Pinnacle 100 website`_. - -The Pinnacle 100 Development Kit (453-00010-K1 or 453-00011-K1) hardware -provides support for the -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU, `Sierra Wireless HL7800`_ (Altair ALT1250) -and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* :abbr:`BME680 (Bosch Sensortec BME680 environmental sensor)` -* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` - -.. figure:: img/pinnacle_100_dvk.jpg - :align: center - :alt: Pinnacle 100 DVK - - Pinnacle 100 DVK (453-00010-K1) - -Hardware -******** - -Supported Features -================== - -The Pinnacle 100 development board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ -| QSPI | on-chip | qspi/MX25R64(8MB) | -+-----------+------------+----------------------+ -| BME680 | I2C(M) | sensor/bme680 | -+-----------+------------+----------------------+ -| HL7800 | UART | HL7800 modem driver | -+-----------+------------+----------------------+ - -See `Pinnacle 100 website`_ for a complete list -of Pinnacle 100 Development Kit hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (blue) = P1.4 -* LED2 (green) = P1.5 -* LED3 (red) = P1.6 -* LED4 (green) = P1.7 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.31 -* BUTTON2 = SW2 = P0.3 -* BUTTON3 = SW3 = P0.4 -* BUTTON4 = SW4 = P0.2 -* NRF RESET = SW5 = reset - -Programming and Debugging -************************* - -Applications for the ``pinnacle_100_dvk`` board configuration can be -built and flashed in the usual way. (see :ref:`build_an_application` -and :ref:`application_run` for more details) - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. note:: On the Pinnacle 100 development board, - the FTDI USB should be used to access the UART console. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board Pinnacle 100 DVK -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: pinnacle_100_dvk - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -Software -******** - -Pinnacle 100 Out-of-Box Demo Software -===================================== -The Pinnacle 100 development kit ships with an out of the box software demo. -Check out the `Pinnacle 100 OOB Demo`_ source code and documentation. - -Sample Applications -=================== -`Pinnacle 100 Sample Applications`_ are available. - -Testing Bluetooth on the Pinnacle 100 DVK -========================================= -Many of the Bluetooth examples will work on the Pinnacle 100 DVK. -Try them out: - -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` - -Testing the LEDs and buttons in the Pinnacle 100 DVK -==================================================== - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.dts`. - -References -********** - -.. target-notes:: - -.. _Pinnacle 100 website: https://www.lairdconnect.com/wireless-modules/cellular-solutions/pinnacle-100-cellular-modem -.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf -.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _Pinnacle 100 OOB Demo: https://github.com/LairdCP/Pinnacle_100_oob_demo -.. _Pinnacle 100 Sample Applications: https://github.com/LairdCP/Pinnacle_100_Sample_Applications diff --git a/boards/arm/qemu_cortex_a9/Kconfig.board b/boards/arm/qemu_cortex_a9/Kconfig.board deleted file mode 100644 index c8fcdf1ccdb..00000000000 --- a/boards/arm/qemu_cortex_a9/Kconfig.board +++ /dev/null @@ -1,11 +0,0 @@ -# -# Kconfig - Cortex-A9 QEMU Emulation -# -# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_QEMU_CORTEX_A9 - bool "Cortex-A9 Emulation (QEMU)" - depends on SOC_XILINX_XC7Z007S - select QEMU_TARGET diff --git a/boards/arm/qemu_cortex_a9/Kconfig.defconfig b/boards/arm/qemu_cortex_a9/Kconfig.defconfig deleted file mode 100644 index 09c6afaae64..00000000000 --- a/boards/arm/qemu_cortex_a9/Kconfig.defconfig +++ /dev/null @@ -1,80 +0,0 @@ -# -# Kconfig - Cortex-A9 (Zynq-7000) QEMU Emulation -# -# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_QEMU_CORTEX_A9 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_cortex_a9" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 111111111 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -if LOG - - if LOG_PROCESS_THREAD - - config LOG_PROCESS_THREAD_STACK_SIZE - default 8192 - - endif # LOG_PROCESS_THREAD - -endif # LOG - -if NETWORKING - - config NET_L2_ETHERNET - default y - - config NET_TX_STACK_SIZE - default 8192 - - config NET_RX_STACK_SIZE - default 8192 - - if NET_TCP - - config NET_TCP_WORKQ_STACK_SIZE - default 8192 - - endif # NET_TCP - - if NET_MGMT_EVENT - - config NET_MGMT_EVENT_STACK_SIZE - default 8192 - - endif # NET_MGMT_EVENT - - config TEST_RANDOM_GENERATOR - default y - -endif # NETWORKING - -if QEMU_ICOUNT - - config QEMU_ICOUNT_SHIFT - default 3 - config QEMU_ICOUNT_SLEEP - default y - -endif # QEMU_ICOUNT - -if SHELL - - config SHELL_STACK_SIZE - default 8192 - -endif # SHELL - -endif # BOARD_QEMU_CORTEX_A9 diff --git a/boards/arm/qemu_cortex_a9/board.cmake b/boards/arm/qemu_cortex_a9/board.cmake deleted file mode 100644 index 3aad89a09ce..00000000000 --- a/boards/arm/qemu_cortex_a9/board.cmake +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -set(SUPPORTED_EMU_PLATFORMS qemu) -set(QEMU_ARCH xilinx-aarch64) - -set(QEMU_CPU_TYPE_${ARCH} cortex-a9) - -set(QEMU_FLAGS_${ARCH} - -nographic - -machine arm-generic-fdt-7series - -dtb ${ZEPHYR_BASE}/boards/${ARCH}/${BOARD}/fdt-zynq7000s.dtb - ) - -set(QEMU_KERNEL_OPTION - "-device;loader,file=\$,cpu-num=0" - ) - -board_set_debugger_ifnset(qemu) diff --git a/boards/arm/qemu_cortex_m0/Kconfig b/boards/arm/qemu_cortex_m0/Kconfig deleted file mode 100644 index 3dcbf4298dd..00000000000 --- a/boards/arm/qemu_cortex_m0/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config NRF_TIMER_TIMER - bool "nRF Timer Counter (NRF_TIMER0) Timer" - depends on CLOCK_CONTROL - depends on SOC_COMPATIBLE_NRF - depends on SYS_CLOCK_EXISTS - select TICKLESS_CAPABLE - default y - help - This module implements a kernel device driver for the nRF Timer - Counter NRF_TIMER0 and provides the standard "system clock driver" - interfaces. diff --git a/boards/arm/qemu_cortex_m0/Kconfig.board b/boards/arm/qemu_cortex_m0/Kconfig.board deleted file mode 100644 index 8a6473d8521..00000000000 --- a/boards/arm/qemu_cortex_m0/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# QEMU Cortex-M0 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_CORTEX_M0 - bool "Cortex-M0 Emulation (QEMU)" - depends on SOC_NRF51822_QFAA - select QEMU_TARGET diff --git a/boards/arm/qemu_cortex_m0/Kconfig.defconfig b/boards/arm/qemu_cortex_m0/Kconfig.defconfig deleted file mode 100644 index 3f203f2adbc..00000000000 --- a/boards/arm/qemu_cortex_m0/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# QEMU Cortex-M0 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_CORTEX_M0 - -config BOARD - default "qemu_cortex_m0" - -config NRF_RTC_TIMER - default n if SYS_CLOCK_EXISTS - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 100 - -endif # BOARD_QEMU_CORTEX_M0 diff --git a/boards/arm/qemu_cortex_m0/qemu_cortex_m0_defconfig b/boards/arm/qemu_cortex_m0/qemu_cortex_m0_defconfig deleted file mode 100644 index a169a86f8de..00000000000 --- a/boards/arm/qemu_cortex_m0/qemu_cortex_m0_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAA=y -CONFIG_BOARD_QEMU_CORTEX_M0=y -CONFIG_QEMU_ICOUNT_SHIFT=6 - -# enable GPIO -CONFIG_GPIO=y - -# clock control -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# icount is kinda broken when the NRF timer emulation is used -CONFIG_QEMU_ICOUNT=n diff --git a/boards/arm/qemu_cortex_m3/Kconfig.board b/boards/arm/qemu_cortex_m3/Kconfig.board deleted file mode 100644 index 6322724df89..00000000000 --- a/boards/arm/qemu_cortex_m3/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_CORTEX_M3 - bool "Cortex-M3 Emulation (QEMU)" - depends on SOC_TI_LM3S6965 - select QEMU_TARGET diff --git a/boards/arm/qemu_cortex_m3/Kconfig.defconfig b/boards/arm/qemu_cortex_m3/Kconfig.defconfig deleted file mode 100644 index bfbda98cb73..00000000000 --- a/boards/arm/qemu_cortex_m3/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_CORTEX_M3 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_cortex_m3" - -# DWT is not properly emulated in QEMU -choice NULL_POINTER_EXCEPTION_DETECTION - bool - default NULL_POINTER_EXCEPTION_DETECTION_NONE -endchoice - -endif # BOARD_QEMU_CORTEX_M3 diff --git a/boards/arm/qemu_cortex_m3/board.cmake b/boards/arm/qemu_cortex_m3/board.cmake deleted file mode 100644 index 51f04bfd2dc..00000000000 --- a/boards/arm/qemu_cortex_m3/board.cmake +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_CPU_TYPE_${ARCH} cortex-m3) -set(QEMU_FLAGS_${ARCH} - -cpu ${QEMU_CPU_TYPE_${ARCH}} - -machine lm3s6965evb - -nographic - -vga none - ) -board_set_debugger_ifnset(qemu) diff --git a/boards/arm/qemu_cortex_r5/Kconfig.board b/boards/arm/qemu_cortex_r5/Kconfig.board deleted file mode 100644 index 9824aeb5bc1..00000000000 --- a/boards/arm/qemu_cortex_r5/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_CORTEX_R5 - bool "Cortex-R5 Emulation (QEMU)" - depends on SOC_XILINX_ZYNQMP_RPU - select QEMU_TARGET diff --git a/boards/arm/qemu_cortex_r5/Kconfig.defconfig b/boards/arm/qemu_cortex_r5/Kconfig.defconfig deleted file mode 100644 index 9cac36e1ee6..00000000000 --- a/boards/arm/qemu_cortex_r5/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_CORTEX_R5 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_cortex_r5" - -if USERSPACE - -config COMPILER_ISA_THUMB2 - default n - -endif - -endif # BOARD_QEMU_CORTEX_R5 diff --git a/boards/arm/qemu_cortex_r5/board.cmake b/boards/arm/qemu_cortex_r5/board.cmake deleted file mode 100644 index 7ac21d345c9..00000000000 --- a/boards/arm/qemu_cortex_r5/board.cmake +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) -set(QEMU_ARCH xilinx-aarch64) - -set(QEMU_CPU_TYPE_${ARCH} cortex-r5) -set(QEMU_FLAGS_${ARCH} - -nographic - -machine arm-generic-fdt - -dtb ${ZEPHYR_BASE}/boards/${ARCH}/${BOARD}/fdt-single_arch-zcu102-arm.dtb - ) - -set(QEMU_KERNEL_OPTION - "-device;loader,file=\$,cpu-num=4" - "-device;loader,addr=0xff5e023c,data=0x80008fde,data-len=4" - "-device;loader,addr=0xff9a0000,data=0x80000218,data-len=4" - ) - -board_set_debugger_ifnset(qemu) diff --git a/boards/arm/qomu/Kconfig.board b/boards/arm/qomu/Kconfig.board deleted file mode 100644 index fd1caf385d2..00000000000 --- a/boards/arm/qomu/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# QuickLogic Qomu board - -# Copyright (c) 2022 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QOMU - bool "QuickLogic Qomu target" - depends on SOC_EOS_S3 diff --git a/boards/arm/qomu/Kconfig.defconfig b/boards/arm/qomu/Kconfig.defconfig deleted file mode 100644 index 31125f4f62f..00000000000 --- a/boards/arm/qomu/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# QuickLogic Qomu board - -# Copyright (c) 2022 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QOMU - -config BOARD - default "qomu" - -endif # BOARD_QOMU diff --git a/boards/arm/quick_feather/Kconfig.board b/boards/arm/quick_feather/Kconfig.board deleted file mode 100644 index e85b49bc4e4..00000000000 --- a/boards/arm/quick_feather/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Quick Feather board - -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QUICK_FEATHER - bool "QuickLogic Quick Feather target" - depends on SOC_EOS_S3 diff --git a/boards/arm/quick_feather/Kconfig.defconfig b/boards/arm/quick_feather/Kconfig.defconfig deleted file mode 100644 index cf328e50b1b..00000000000 --- a/boards/arm/quick_feather/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# QuickLogic Quick Feather board - -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QUICK_FEATHER - -config BOARD - default "quick_feather" - -endif # BOARD_QUICK_FEATHER diff --git a/boards/arm/quick_feather/doc/index.rst b/boards/arm/quick_feather/doc/index.rst deleted file mode 100644 index dd79c8c8f74..00000000000 --- a/boards/arm/quick_feather/doc/index.rst +++ /dev/null @@ -1,125 +0,0 @@ -.. _quickfeather: - -QuickFeather -############ - -Overview -******** - -The QuickFeather development board is a platform with an on-board QuickLogic -EOS S3 Sensor Processing Platform. - - -.. figure:: img/feather-board.jpg - :align: center - :alt: QuickFeather - - QuickFeather (Credit: QuickLogic) - -Hardware -******** - -- QuickLogic EOS S3 MCU Platform -- mCube MC3635 accelerometer -- Infineon DPS310 pressure sensor -- Infineon IM69D130 MEMS microphone -- 16 Mbit of on-board flash memory -- User button -- RGB LED -- Integrated battery charger - -Detailed information about the board can be found in a `QuickFeather repository`_. - -Supported Features -================== - -The QuickFeather configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/quick_feather/quick_feather_defconfig`. - -Connections and IOs -=================== - -Detailed information about pinouts is available in the `schematics document`_. - -Programming and Debugging -************************* - -Flashing -======== - -The QuickFeather platform by default boots from flash. Currently -the Zephyr port only enables loading the program directly to SRAM using either -OpenOCD and a SWD programmer or SEGGER JLink. - -OpenOCD -------- - -In order to connect to the target a SWD programmer supported in -OpenOCD is needed. To connect to the board run: - -.. code-block:: console - - openocd -f /path/to/swd-programmer.cfg -f tcl/board/quicklogic_quickfeather.cfg -c "init" -c "reset halt" - -`The QuickFeather OpenOCD config`_ can be found in the OpenOCD mainline repository. - -JLink ------ - -To connect to the QuickFeather board with JLink please follow instructions -in the `QuickFeather User Guide`_. - -Debugging -========= - -To debug the QuickFeather board please connect to the target with either -OpenOCD or JLink and use GDB distributed in Zephyr's SDK in *arm-zephyr-eabi/bin* -directory. - -To load basic sample via GDB: - -- Build the sample in an usual way: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: quick_feather - :goals: build - -- Connect to the target using either OpenOCD or JLink -- Connect via GDB and load an ELF file: - -.. code-block:: console - - /path/to/zephyr-sdk/arm-zephyr-eabi/bin/arm-zephyr-eabi-gdb - target remote - file - load - continue - -References -********** - -.. target-notes:: - -.. _QuickFeather repository: - https://github.com/QuickLogic-Corp/quick-feather-dev-board - -.. _schematics document: - https://github.com/QuickLogic-Corp/quick-feather-dev-board/blob/master/doc/quickfeather-board.pdf - -.. _The QuickFeather OpenOCD config: - https://sourceforge.net/p/openocd/code/ci/master/tree/tcl/board/quicklogic_quickfeather.cfg - -.. _QuickFeather User Guide: - https://github.com/QuickLogic-Corp/quick-feather-dev-board/blob/master/doc/QuickFeather_UserGuide.pdf diff --git a/boards/arm/rak4631_nrf52840/Kconfig.board b/boards/arm/rak4631_nrf52840/Kconfig.board deleted file mode 100644 index f5db0172189..00000000000 --- a/boards/arm/rak4631_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# RAKWIRELESS RAK4631 selection - -# Copyright (c) 2021 Guillaume Paquet -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RAK4631_NRF52840 - bool "RAK4631 DK NRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/rak4631_nrf52840/Kconfig.defconfig b/boards/arm/rak4631_nrf52840/Kconfig.defconfig deleted file mode 100644 index 10a6070f95b..00000000000 --- a/boards/arm/rak4631_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# RAKWIRELESS RAK4631 Board configuration - -# Copyright (c) 2021 Guillaume Paquet -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAK4631_NRF52840 - -config BOARD - default "rak4631_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_RAK4631_NRF52840 diff --git a/boards/arm/rak4631_nrf52840/doc/index.rst b/boards/arm/rak4631_nrf52840/doc/index.rst deleted file mode 100644 index e25593816d5..00000000000 --- a/boards/arm/rak4631_nrf52840/doc/index.rst +++ /dev/null @@ -1,155 +0,0 @@ -.. _rak4631_nrf52840: - -RAK4631 -####### - -Overview -******** - -RAK4631 is a WisBlock Core module for RAK WisBlock. -It extends the WisBlock series with a powerful -Nordic nRF52840 MCU that supports Bluetooth 5.0 -(Bluetooth Low Energy) and the newest LoRa transceiver -from Semtech, the SX1262. The Semtech SX1262 has compared -to the older SX127x series a lower power consumption at -the same TX power. This makes the RAK4631 an ultra-low -power communication solution. RAK4631 can be comfortably -programmed with ZephyrRTOS. - -.. image:: img/rak4631-front-parts.jpg - :align: center - :alt: RAK4631-NRF52840 - -Hardware -******** - -To use a RAK4631, you need at least a WisBlock Base -to plug the module in. WisBlock Base is the power -supply for the RAK4631 module and has the -programming/debug interface. - -- nRF52840 ARM Cortex-M4F Processor -- 64 MHz CPU clock -- 1 Micro-AB USB OTG host/device -- Semtech SX1262 low power high range LoRa transceiver -- iPEX connectors for the LORA antenna and BLE antenna. -- Multiple interfaces, I2C, UART, GPIO, ADC -- 2 user LEDs on RAK5005 mother Board -- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port - -Supported Features -================== - -The rak4631_nrf52840 board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RADIO | on-board | LoRa (SX1262) | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The default board configuration can be found in the defconfig file: - - ``boards/arm/rak4631_nrf52840/rak4631_nrf52840_defconfig`` - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P1.3 -* LED2 (blue) = P1.4 - -Programming and Debugging -************************* - -The RAK4631 board shall be connected to a Segger Embedded Debugger Unit -`J-Link OB `_. This provides a debug -interface to the NRF52840 chip. You can use JLink to communicate with -the NRF52840. - -Flashing -======== - -#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section - "J-Link Software and Documentation Pack" and install the "J-Link Software - and Documentation pack for Linux". The application JLinkExe needs to be - accessible from your path. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the RAK4631 board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak4631_nrf52840 - :goals: build flash - - You should see "Hello World! rak4631_nrf52840" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak4631_nrf52840 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _RAK4631 Product Description: - https://docs.rakwireless.com/Product-Categories/WisBlock/RAK4631/Datasheet/#overview - -.. _JLink Downloads Page: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/rak5010_nrf52840/Kconfig.board b/boards/arm/rak5010_nrf52840/Kconfig.board deleted file mode 100644 index c5a5ab2d3a1..00000000000 --- a/boards/arm/rak5010_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# RAKWIRELESS RAK5010 selection - -# Copyright (c) 2020 Guillaume Paquet -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RAK5010_NRF52840 - bool "RAK5010 DK NRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/rak5010_nrf52840/Kconfig.defconfig b/boards/arm/rak5010_nrf52840/Kconfig.defconfig deleted file mode 100644 index 2361185f0f7..00000000000 --- a/boards/arm/rak5010_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# RAKWIRELESS RAK5010 Board configuration - -# Copyright (c) 2020 Guillaume Paquet -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAK5010_NRF52840 - -config BOARD - default "rak5010_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_RAK5010_NRF52840 diff --git a/boards/arm/rak5010_nrf52840/doc/index.rst b/boards/arm/rak5010_nrf52840/doc/index.rst deleted file mode 100644 index 9ca09035d00..00000000000 --- a/boards/arm/rak5010_nrf52840/doc/index.rst +++ /dev/null @@ -1,159 +0,0 @@ -.. _rak5010_nrf52840: - -RAK5010 -####### - -Overview -******** - -WisTrio NB-IoT Tracker Pro (RAK5010) is a tracker -with integrated LTE CAT M1 & NB1, GPS, BLE, and sensors. -It is built on the Quectel BG96 LTE CAT M1 & NB1 module, -which has an integrated GPS receiver. The MCU running -the board is a Nordic nRF52840 controller. - -As it has both GPS and BLE it can be used for outdoor -and indoor scenarios, where location-based services need be present. - -The built-in sensors for RAK5010 are temperature and -humidity sensor, motion sensor, pressure sensor, and light sensor. -The extension IOs allow adding more sensors in addition to the on-board ones. - -This board is particularly suitable to be used as a -quick testing and prototyping tool for applications -requiring NB-IoT connectivity. Application development -supports the GCC environment. - -.. image:: img/rak5010-front-parts.jpg - :align: center - :alt: RAK5010-NRF52840 - -Hardware -******** - -- nRF52840 ARM Cortex-M4F Processor -- 32.768 kHz crystal oscillator -- 1 Micro-AB USB OTG host/device -- Quectel BG96, with LTE CAT M1, LTE NB1, and GNSS -- iPEX connectors for the LTE and GPS antenna and an on-board ceramic antenna for the BLE. -- nano-SIM and ESIM options. -- Multiple interfaces, I2C, UART, GPIO, ADC -- 1 user LED -- 1 SHTC3 Humidity and Temperature Sensor -- 1 OPT3001DNPR Ambient Light Sensor -- 1 LPS22HB Pressure Sensor -- 1 LIS3DH Motion Sensor -- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port - -Supported Features -================== - -The rak5010_nrf52840 board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -LED ---- - -* LED0 (green) = P0.12 - - -Programming and Debugging -************************* - -The RAK5010 board shall be connected to a Segger Embedded Debugger Unit -`J-Link OB `_. This provides a debug -interface to the NRF52840 chip. You can use JLink to communicate with -the NRF52840. - -Flashing -======== - -#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section - "J-Link Software and Documentation Pack" and install the "J-Link Software - and Documentation pack for Linux". The application JLinkExe needs to be - accessible from your path. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the RAK5010 board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak5010_nrf52840 - :goals: build flash - - You should see "Hello World! rak5010_nrf52840" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak5010_nrf52840 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _RAK5010 Product Description: - https://doc.rakwireless.com/datasheet/rakproducts/rak5010-wistrio-nb-iot-tracker-datasheet - -.. _JLink Downloads Page: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig b/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig deleted file mode 100644 index 2c11d6d2f79..00000000000 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Raytac MDBT50Q-DB-33 nRF52833 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_RAYTAC_MDBT50Q_DB_33_NRF52833 diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.board b/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.board deleted file mode 100644 index 9bea6b03f4f..00000000000 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Raytac MDBT50Q-DB-33 nRF52833 board configuration - -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RAYTAC_MDBT50Q_DB_33_NRF52833 - bool "Raytac MDBT50Q-DB-33 nRF52833" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.defconfig b/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.defconfig deleted file mode 100644 index ebb90a80bfa..00000000000 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Raytac MDBT50Q-DB-33 NRF52833 board configuration - -# Copyright (c) 2022 Raytac Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT50Q_DB_33_NRF52833 - -config BOARD - default "raytac_mdbt50q_db_33_nrf52833" - -config BT_CTLR - default BT - -endif diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/doc/index.rst b/boards/arm/raytac_mdbt50q_db_33_nrf52833/doc/index.rst deleted file mode 100644 index 84c241a799a..00000000000 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/doc/index.rst +++ /dev/null @@ -1,213 +0,0 @@ -.. _raytac_mdbt50q_db_33_nrf52833: - -Raytac MDBT50Q-DB-33 -#################### - -Overview -******** - -The Raytac MDBT50Q-DB-33 hardware provides support for the -Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/mdbt50q_db_33.jpg - :width: 442px - :align: center - :alt: MDBT50Q-DB-33 - -More information about the board can be found at the `MDBT50Q-DB-33 website`_. -The `MDBT50Q-DB-33 Specification`_ contains the demo board's datasheet. -The `MDBT50Q-DB-33 Schematic`_ contains the demo board's schematic. - -Hardware -******** -- Module Demo Board build by MDBT50Q-512K -- Nordic nRF52833 SoC Solution -- A recommnded 3rd-party module by Nordic Semiconductor. -- BT5.2&BT5.1&BT5 Bluetooth Specification Cerified -- Supports BT5 Long Range Features -- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC -- 32-bit ARM® Cortex™ M4F CPU -- 512kB Flash Memory/128kB RAM -- RoHs & Reach Compiant. -- 42 GPIO -- Chip Antenna -- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB -- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. -- 3 User LEDs -- 4 User buttons -- 1 Mini USB connector for power supply and USB communication -- SWD connector for FW programing -- J-Link interface for FW programing -- UART interface for UART communication - -Supported Features -================== - -The raytac_mdbt50q_db_33_nrf52833 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `MDBT50Q-DB-33 website`_ and `MDBT50Q-DB-33 Specification`_ -for a complete list of Raytac MDBT50Q-DB-33 board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (red) = P0.14 -* LED3 (blue) = P0.15 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 - -UART ----- -* RXD = P0.08 -* TXD = P0.06 -* RTS = P0.05 -* CTS = P0.07 - -Programming and Debugging -************************* - -Applications for the ``raytac_mdbt50q_db_33_nrf52833`` board configuration can be -built, flashed, and debugged in the usual way. See :ref:`build_an_application` and -:ref:`application_run` for more details on building and running. - -.. note:: - Flashing and Debugging Zephyr onto the raytac_mdbt50q_db_33_nrf52833 board - requires an external J-Link programmer. The programmer is attached to the J1 - or J9 SWD connector. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_33_nrf52833 -J10 connector. Then run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the USB to TTL converter -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: raytac_mdbt50q_db_33_nrf52833 - :goals: build flash - -Debugging -========= - -The ``raytac_mdbt50q_db_33_nrf52833`` board does not have an on-board-J-Link debug IC, -however, instructions from the :ref:`nordic_segger` page also apply to this board. -Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER -J-Link OB IF to debug. - -Testing the LEDs and buttons in the Raytac MDBT50Q-DB-33 -******************************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.dts`. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the `MDBT50Q-DB-33 Specification`_, chapter 2.5 'Pin Assignment'. -Select the pins marked 'General-purpose I/O'. Note that pins marked as 'low-frequency I/O -only' can only be used in under-10KHz applications. They are not suitable for SPI, I2C, -UART, and PWM. - -References -********** - -.. target-notes:: - -.. _MDBT50Q-DB-33 website: - https://www.raytac.com/product/ins.php?index_id=97 -.. _MDBT50Q-DB-33 Specification: - https://www.raytac.com/download/index.php?index_id=46 -.. _MDBT50Q-DB-33 Schematic: - https://www.raytac.com/upload/catalog_b/407c1150fa33511a47e8a2f85d106ff3.jpg -.. _J-Link Software and documentation pack: - https://www.segger.com/jlink-software.html diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig b/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig deleted file mode 100644 index bab7358485d..00000000000 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Raytac MDBT50Q-DB-40 nRF52840 board configuration - -# Copyright (c) 2022 Raytac Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT50Q_DB_40_NRF52840 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_RAYTAC_MDBT50Q_DB_40_NRF52840 diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.board b/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.board deleted file mode 100644 index 9384b2743c8..00000000000 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Raytac MDBT50Q-DB-40 nRF52840 board configuration - -# Copyright (c) 2022 Raytac Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RAYTAC_MDBT50Q_DB_40_NRF52840 - bool "Raytac MDBT50Q_DB_40_nRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.defconfig b/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.defconfig deleted file mode 100644 index 12044d8e485..00000000000 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Raytac MDBT50Q-DB-40 NRF52840 board configuration - -# Copyright (c) 2022 Raytac Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT50Q_DB_40_NRF52840 - -config BOARD - default "raytac_mdbt50q_db_40_nrf52840" - -config BT_CTLR - default BT - -endif diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/doc/index.rst b/boards/arm/raytac_mdbt50q_db_40_nrf52840/doc/index.rst deleted file mode 100644 index 99b57d22002..00000000000 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _raytac_mdbt50q_db_40_nrf52840: - -Raytac MDBT50Q-DB-40 -#################### - -Overview -******** - -The Raytac MDBT50Q-DB-40 hardware provides support for the -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/mdbt50q_db_40.jpg - :width: 442px - :align: center - :alt: MDBT50Q-DB-40 - -More information about the board can be found at the `MDBT50Q-DB-40 website`_. -The `MDBT50Q-DB-40 Specification`_ contains the demo board's datasheet. -The `MDBT50Q-DB-40 Schematic`_ contains the demo board's schematic. - -Hardware -******** -- Module Demo Board build by MDBT50Q-1MV2 -- Nordic nRF52840 SoC Solution Version: 2 -- A recommnded 3rd-party module by Nordic Semiconductor. -- BT5.2&BT5.1&BT5 Bluetooth Specification Cerified -- Supports BT5 Long Range Features -- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC -- 32-bit ARM® Cortex™ M4F CPU -- 1MB Flash Memory/256kB RAM -- RoHs & Reach Compiant. -- 48 GPIO -- Chip Antenna -- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB -- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. -- 3 User LEDs -- 4 User buttons -- 1 Mini USB connector for power supply and USB communication -- SWD connector for FW programing -- J-Link interface for FW programing -- UART interface for UART communication - -Supported Features -================== - -The raytac_mdbt50q_db_40_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| QSPI(M) | on-chip | qspi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `MDBT50Q-DB-40 website`_ and `MDBT50Q-DB-40 Specification`_ -for a complete list of Raytac MDBT50Q-DB-40 board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (red) = P0.14 -* LED3 (blue) = P0.15 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 - -UART ----- -* RXD = P0.08 -* TXD = P0.06 -* RTS = P0.05 -* CTS = P0.07 - -Programming and Debugging -************************* - -Applications for the ``raytac_mdbt50q_db_40_nrf52840`` board configuration can be -built, flashed, and debugged in the usual way. See :ref:`build_an_application` and -:ref:`application_run` for more details on building and running. - -.. note:: - Flashing and Debugging Zephyr onto the raytac_mdbt50q_db_40_nrf52840 board - requires an external J-Link programmer. The programmer is attached to the J1 - or J9 SWD connector. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_40_nrf52840 -J10 connector. Then run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the USB to TTL converter -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: raytac_mdbt50q_db_40_nrf52840 - :goals: build flash - -Debugging -========= - -The ``raytac_mdbt50q_db_40_nrf52840`` board does not have an on-board-J-Link debug IC, -however, instructions from the :ref:`nordic_segger` page also apply to this board. -Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER -J-Link OB IF to debug. - -Testing the LEDs and buttons in the MDBT50Q-DB-40 -************************************************* - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.dts`. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the `MDBT50Q-DB-40 Specification`_, chapter 2.5 'Pin Assignment'. -Select the pins marked 'General-purpose I/O'. Note that pins marked as 'low-frequency I/O -only' can only be used in under-10KHz applications. They are not suitable for SPI, I2C, -UART, and PWM. - -References -********** - -.. target-notes:: - -.. _MDBT50Q-DB-40 website: - https://www.raytac.com/product/ins.php?index_id=81 -.. _MDBT50Q-DB-40 Specification: - https://www.raytac.com/download/index.php?index_id=43 -.. _MDBT50Q-DB-40 Schematic: - https://www.raytac.com/upload/catalog_b/134ade06b5db3dd5803d27c5b17f22f3.jpg -.. _J-Link Software and documentation pack: - https://www.segger.com/jlink-software.html diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/CMakeLists.txt b/boards/arm/raytac_mdbt53_db_40_nrf5340/CMakeLists.txt deleted file mode 100644 index 6a13dbb534e..00000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if ((CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) - zephyr_library() - zephyr_library_sources(raytac_mdbt53_db_40_nrf5340_cpunet_reset.c) -endif() diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig b/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig deleted file mode 100644 index caf06f347d5..00000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# Ratac MDBT53-DB-40 nRF5340 board configuration - -# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "raytac_mdbt53_db_40_nrf5340_cpunet" - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -config DOMAIN_CPUAPP_BOARD - string - default "raytac_mdbt53_db_40_nrf5340_cpuapp" - depends on BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.board b/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.board deleted file mode 100644 index ff4b1ac6986..00000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# Raytac MDBT53-DB-40 NRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP - bool "Raytac MDBT53-DB-40 nRF5340 Application MCU" - -config BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - bool "Raytac MDBT53-DB-40 nRF5340 Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -config BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET - bool "Raytac MDBT53-DB-40 NRF5340 Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.defconfig b/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.defconfig deleted file mode 100644 index fb5a6b85630..00000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# Raytac MDBT53-DB-40 nRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -config BOARD - default "raytac_mdbt53_db_40_nrf5340_cpuapp" - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -config BOARD - default "raytac_mdbt53_dv_40_nrf5340_cpunet" if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET - -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET - -config BT_CTLR - default y if BT - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/board.cmake b/boards/arm/raytac_mdbt53_db_40_nrf5340/board.cmake deleted file mode 100644 index 8657aa50f1c..00000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS) - board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET) - board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/doc/index.rst b/boards/arm/raytac_mdbt53_db_40_nrf5340/doc/index.rst deleted file mode 100644 index bcff494f91b..00000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/doc/index.rst +++ /dev/null @@ -1,271 +0,0 @@ -.. _raytac_mdbt53_db_40_nrf5340: - -Raytac MDBT53-DB-40 -################### - -Overview -******** - -Raytac MDBT53-DB-40 demo board is a development board based on the Raytac MDBT53-1M module, -using Nordic Semiconductor nRF5340 ARM Cortex-M33 SoC. Its design concept is to connect all -of the module's pins to 2.54mm pin headers. It is convenient for developers to verify whether -the modules are connected to other peripheral devices or sensors as a tool for software development. - -The nRF5340 inside the MDBT53-1M module is a -dual-core SoC based on the Arm® Cortex®-M33 architecture, with: - -* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and - Armv8-M Security Extension, running at up to 128 MHz, referred to as - the **application core** -* a secondary Arm Cortex-M33 core, with a reduced feature set, running - at a fixed 64 MHz, referred to as the **network core**. - -The raytac_mdbt53_db_40_nrf5340_cpuapp build target provides support for the application -core on the nRF5340 SoC. The raytac_mdbt53_db_40_nrf5340_cpuapp build target provides -support for the network core on the nRF5340 SoC. - -nRF5340 SoC provides support for the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/MDBT53-DB-40.jpg - :width: 442px - :align: center - :alt: MDBT53-DB-40 - - MDBT53-DB-40 (Credit: Raytac Corporation) - -More information about the board can be found at the `MDBT53-DB-40 website`_. -The `MDBT53-DB-40 Specification`_ contains the demo board's datasheet. -The `MDBT53-DB-40 Schematic`_ contains the demo board's schematic. - -Hardware -******** -- Module Demo Board build by MDBT53-1M -- Nordic nRF5340 SoC Solution -- A recommnded 3rd-party module by Nordic Semiconductor. -- Dual-core Arm® Cortex® M33 -- 1MB/256KB Flash Memory; 512kB/ 64kB RAM -- Supports BT5 Long Range Features -- Bluetooth specification v5.2 -- Supports Bluetooth Direction Finding & Mesh -- Supports Bluetooth low energy audio -- Certifications: FCC, IC, CE, Telec (MIC), KC, SRRC, NCC, RCM, WPC -- RoHs & Reach Compiant. -- 48 GPIO -- Chip Antenna -- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB -- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. -- 4 User LEDs -- 4 User buttons -- 1 Mini USB connector for power supply -- SWD connector for FW programing -- J-Link interface for FW programing -- UART interface for UART communication - -Supported Features -================== - -The raytac_mdbt53_db_40_nrf52840_cpuapp board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| QSPI(M) | on-chip | nor | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The raytac_mdbt53_db_40_nrf5340_cpunet board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `MDBT53-DB-40 website`_ and `MDBT53-DB-40 Specification`_ -for a complete list of Raytac MDBT53-DB-40 board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.28 -* LED2 (red) = P0.30 -* LED3 = P0.31 -* LED4 = P0.29 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.24 -* BUTTON2 = SW2 = P0.08 -* BUTTON3 = SW3 = P0.23 -* BUTTON4 = SW4 = P0.09 - -UART ----- -* RX = P0.22 -* TX = P0.20 -* RTS = P0.19 -* CTS = P0.21 - - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_) on the application core. - The IDAU is implemented with the System Protection Unit and is used to - define secure and non-secure memory maps. By default, all of the memory - space (Flash, SRAM, and peripheral address space) is defined to be secure - accessible only. -- Secure boot. - -Programming and Debugging -************************* - -nRF5340 application core supports the Armv8-M Security Extension. -Applications built for the raytac_mdbt53_db_40_nrf5340_cpuapp board by -default boot in the Secure state. - -nRF5340 network core does not support the Armv8-M Security Extension. -nRF5340 IDAU may configure bus accesses by the nRF5340 network core -to have Secure attribute set; the latter allows to build and run -Secure only applications on the nRF5340 SoC. - -Applications for the ``raytac_mdbt53_db_40_nrf5340`` board configuration can be -built, flashed, and debugged in the usual way. See :ref:`build_an_application` and -:ref:`application_run` for more details on building and running. - -.. note:: - Flashing and Debugging Zephyr onto the raytac_mdbt53_db_40_nrf5340 board - requires an external J-Link programmer. The programmer is attached to the J1 - or J9 SWD connector. - - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. warning:: - - The nRF5340 has a flash read-back protection feature. When flash read-back - protection is active, you will need to recover the chip before reflashing. - If you are flashing with :ref:`west `, run - this command for more details on the related ``--recover`` option: - -Here is an example for the :ref:`hello_world` application. - -Use a USB to TTL converter to connect the computer and raytac_mdbt53_db_40_nrf5340 -J10 connector. Then run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the USB to TTL converter -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: raytac_mdbt53_db_40_nrf5340 - :goals: build flash - -Debugging -========= - -The ``raytac_mdbt53_db_40_nrf5340`` board does not have an on-board-J-Link debug IC, -however, instructions from the :ref:`nordic_segger` page also apply to this board. -Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER -J-Link OB IF to debug. - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic -boards with a Segger IC. - - -References -********** - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _MDBT53-DB-40 website: - https://www.raytac.com/product/ins.php?index_id=139 -.. _MDBT53-DB-40 Specification: - https://www.raytac.com/download/index.php?index_id=60 -.. _MDBT53-DB-40 Schematic: - https://www.raytac.com/upload/catalog_b/8b5e364600a9cc8c53a869733e97f07e.jpg -.. _J-Link Software and documentation pack: - https://www.segger.com/jlink-software.html diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig b/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig deleted file mode 100644 index cf048d3d213..00000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig b/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig deleted file mode 100644 index e0759063b9a..00000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig b/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig deleted file mode 100644 index 92b16601314..00000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/CMakeLists.txt b/boards/arm/raytac_mdbt53v_db_40_nrf5340/CMakeLists.txt deleted file mode 100644 index 556e084598c..00000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if ((CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) - zephyr_library() - zephyr_library_sources(raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c) -endif() diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig b/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig deleted file mode 100644 index 02b44de6198..00000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# Ratac MDBT53V-DB-40 nRF5340 board configuration - -# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "raytac_mdbt53v_db_40_nrf5340_cpunet" - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -config DOMAIN_CPUAPP_BOARD - string - default "raytac_mdbt53v_db_40_nrf5340_cpuapp" - depends on BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.board b/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.board deleted file mode 100644 index 69bb4b876ea..00000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# Raytac MDBT53-DB-40 NRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP - bool "Raytac MDBT53V-DB-40 nRF5340 Application MCU" - -config BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - bool "Raytac MDBT53V-DB-40 nRF5340 Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -config BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET - bool "Raytac MDBT53V-DB-40 NRF5340 Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.defconfig b/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.defconfig deleted file mode 100644 index fd3e5210d28..00000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# Raytac MDBT53V-DB-40 nRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -config BOARD - default "raytac_mdbt53v_db_40_nrf5340_cpuapp" if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -config BOARD - default "raytac_mdbt53v_dv_40_nrf5340_cpunet" if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET - -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET - -config BT_CTLR - default y if BT - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/board.cmake b/boards/arm/raytac_mdbt53v_db_40_nrf5340/board.cmake deleted file mode 100644 index 8662675aba3..00000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/board.cmake +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS) - board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET) - board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig b/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig deleted file mode 100644 index 6966d7d728c..00000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig b/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig deleted file mode 100644 index 44e16cd65ac..00000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig b/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig deleted file mode 100644 index 94f21fb4c98..00000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/rcar_h3_salvatorx/Kconfig.board b/boards/arm/rcar_h3_salvatorx/Kconfig.board deleted file mode 100644 index f0236267f08..00000000000 --- a/boards/arm/rcar_h3_salvatorx/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RCAR_H3_SALVATORX_CR7 - bool "Cortex-R7 for Renesas H3 Salvator-X" - depends on SOC_R8A77951 diff --git a/boards/arm/rcar_h3_salvatorx/Kconfig.defconfig b/boards/arm/rcar_h3_salvatorx/Kconfig.defconfig deleted file mode 100644 index ccc3ffa89a5..00000000000 --- a/boards/arm/rcar_h3_salvatorx/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RCAR_H3_SALVATORX_CR7 -config BOARD - default "rcar_h3_salvatorx_cr7" -endif # BOARD_RCAR_H3_SALVATORX_CR7 diff --git a/boards/arm/rcar_h3_salvatorx/doc/rcar_h3_salvatorx.rst b/boards/arm/rcar_h3_salvatorx/doc/rcar_h3_salvatorx.rst deleted file mode 100644 index d3b9b292867..00000000000 --- a/boards/arm/rcar_h3_salvatorx/doc/rcar_h3_salvatorx.rst +++ /dev/null @@ -1,183 +0,0 @@ -.. _rcar_h3_salvatorx_boards: - -Renesas R-Car H3 Salvator-X -########################### - -Overview -******** -- The H3 Salvator-X board is designed for evaluating the features and performance - of the R-CAR H3 device from Renesas Electronics and it is also used for developing - and evaluating application software for these R-CAR H3. - -- The H3 Salvator-X, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, - each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces - like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, - via 440pin connector on bottom side. - -.. figure:: img/rcar_h3_salvatorx.jpg - :align: center - :alt: R-Car Salvator-X kit - -More information about the board can be found at `Renesas R-Car Development Support website`_. - -Hardware -******** - -Hardware capabilities for the H3 Salvator-X for can be found on the `eLinux H3 Salvator-X page`_ -of the board. - -.. figure:: img/rcar_h3_features.jpg - :align: center - :alt: R-Car Salvator-X features - -.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. - -More information about the SoC that equips the board can be found here: - -- `Renesas R-Car H3 chip`_ - -Supported Features -================== - -Here is the current supported features when running Zephyr Project on the R-Car Salvator-X CR7: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINCTRL | pinctrl | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| GPIO | gpio | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+ + + + -| | FT232RQ / CP2102 | serial port-interrupt | -+-----------+------------------------------+--------------------------------+ -| CAN | can | normal mode | -+ + + + -| | TCAN332GDCNT | loopback mode | -+-----------+------------------------------+--------------------------------+ -| I2C | i2c | interrupt driven | -+-----------+------------------------------+--------------------------------+ - -It's also currently possible to write on the ram console. - -Connections and IOs -=================== - -.. figure:: img/r-car-h3-salvator-x-connections.jpg - :align: center - :alt: R-Car Salvator-X connections - -GPIO ----- - -By running Zephyr on H3 Salvator-X, the software readable push buttons 'SW20', -'SW21', 'SW22' can be used as input, and the software contollable LEDs 'LED4', -'LED5', 'LED6' can be used as output. - -UART ----- - -Salvator-X board is providing two serial ports: - -- one is for A53/A57 processors -- the other one is for CR7 - -Both ports are converted to USB through CP2102 converters and they are exposed -as follows: - -+-----------+-----------+ -| Connector | Processor | -+===========+===========+ -| CN25 | A53/A57 | -+-----------+-----------+ -| CN26 | CR7 | -+-----------+-----------+ - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Supported Debug Probe -===================== - -The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This -probe is supported by OpenOCD that is shipped with the Zephyr SDK. - -The "Olimex ARM-USB-OCD-H" probe needs to be connected to CN1 on Salvator-X. - -Configuring a Console -===================== - -Connect a USB cable from your PC to CN25 and/or CN26 then use the following -settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -First of all, open your serial terminal. - -Applications for the ``rcar_h3_salvatorx_cr7`` board configuration can be built -in the usual way (see :ref:`build_an_application` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3_salvatorx_cr7 - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3_salvatorx_cr7 - -Debugging -========= - -First of all, open your serial terminal. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3_salvatorx_cr7 - :goals: debug - -You will then get access to a GDB session for debug. - -By continuing the app, you should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3_salvatorx_cr7 - -References -********** - -- `Renesas R-Car H3 chip`_ -- `Renesas R-Car Development Support website`_ -- `eLinux H3 Salvator-X page`_ - -.. _Renesas R-Car H3 chip: - https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support - -.. _Renesas R-Car Development Support website: - https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support - -.. _eLinux H3 Salvator-X page: - https://elinux.org/R-Car/Boards/Salvator-X - -.. _Install a toolchain: - https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.dts b/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.dts deleted file mode 100644 index f953a93a4ed..00000000000 --- a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2022 BayLibre, SAS - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -/dts-v1/; -#include -#include "rcar_h3_salvatorx_cr7-pinctrl.dtsi" -#include - -/ { - model = "Renesas h3 Salvator-X board"; - compatible = "renesas,h3-salvatorx-cr7"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &scif1; - zephyr,shell-uart = &scif1; - zephyr,canbus = &can0; - }; - - leds { - compatible = "gpio-leds"; - user_led_0: led_4 { - gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; - label = "led4"; - }; - user_led_1: led_5 { - gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - label = "led5"; - }; - user_led_2: led_6 { - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - label = "led6"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_0: sw20 { - gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - label = "sw20"; - zephyr,code = ; - }; - user_button_1: sw21 { - gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; - label = "sw21"; - zephyr,code = ; - }; - user_button_2: sw22 { - gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; - label = "sw22"; - zephyr,code = ; - }; - }; - - aliases { - led0 = &user_led_1; - sw0 = &user_button_0; - }; -}; - -&cmt0 { - status = "okay"; - clock-frequency = <32000>; -}; - -&gpio6 { - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_data_a_tx_default &can0_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; - bus-speed = <125000>; -}; - -&scif1 { - pinctrl-0 = <&scif1_data_a_tx_default &scif1_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; diff --git a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.yaml b/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.yaml deleted file mode 100644 index f751adbcc47..00000000000 --- a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: rcar_h3_salvatorx_cr7 -name: Cortex r7 for Renesas H3 Salvator-X -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - i2c - - gpio - - clock_control - - uart -testing: - ignore_tags: - - isotp -vendor: renesas diff --git a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7_defconfig b/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7_defconfig deleted file mode 100644 index 3cf6bbaa0f2..00000000000 --- a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_SOC_R8A77951=y -CONFIG_SOC_SERIES_RCAR_GEN3=y -CONFIG_BOARD_RCAR_H3_SALVATORX_CR7=y -CONFIG_CLOCK_CONTROL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000 -CONFIG_CONSOLE=y -CONFIG_RAM_CONSOLE=y -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0 -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/rcar_h3ulcb/Kconfig.board b/boards/arm/rcar_h3ulcb/Kconfig.board deleted file mode 100644 index eec48844f2a..00000000000 --- a/boards/arm/rcar_h3ulcb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RCAR_H3ULCB_CR7 - bool "Cortex-R7 for Renesas H3ULCB" - depends on SOC_R8A77951 diff --git a/boards/arm/rcar_h3ulcb/Kconfig.defconfig b/boards/arm/rcar_h3ulcb/Kconfig.defconfig deleted file mode 100644 index 61504744fa1..00000000000 --- a/boards/arm/rcar_h3ulcb/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RCAR_H3ULCB_CR7 -config BOARD - default "rcar_h3ulcb_cr7" -endif # BOARD_RCAR_H3ULCB_CR7 diff --git a/boards/arm/rcar_h3ulcb/doc/rcar_h3ulcb.rst b/boards/arm/rcar_h3ulcb/doc/rcar_h3ulcb.rst deleted file mode 100644 index cf02569df83..00000000000 --- a/boards/arm/rcar_h3ulcb/doc/rcar_h3ulcb.rst +++ /dev/null @@ -1,276 +0,0 @@ -.. _rcar_h3ulcb_boards: - -Renesas R-Car H3ULCB -#################### - -Overview -******** -- The H3 Starter Kit board is designed for evaluating the features and performance of the R-CAR H3 device from Renesas Electronics and it is also used for developing and evaluating application software for these R-CAR H3. - -- The H3 Starter Kit, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, via 440pin connector on bottom side. - -It is possible to order 2 different types of H3 Starter Kit Boards, one with Ethernet connection onboard and one with Ethernet connection on ComExpress. - -.. figure:: img/rcar_h3ulcb_starter_kit.jpg - :align: center - :alt: R-Car starter kit - -.. note:: The H3ULCB board can be plugged on a Renesas Kingfisher Infotainment daughter board through COM Express connector in order to physically access more I/O. CAUTION: In this case, power supply is managed by the daughter board. - -More information about the board can be found at `Renesas R-Car Starter Kit website`_. - -Hardware -******** - -Hardware capabilities for the H3ULCB for can be found on the `eLinux H3SK page`_ of the board. - -.. figure:: img/rcar_h3ulcb_features.jpg - :align: center - :alt: R-Car starter kit features - -.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. - -More information about the SoC that equips the board can be found here: - -- `Renesas R-Car H3 chip`_ - -Supported Features -================== - -Here is the current supported features when running Zephyr Project on the R-Car ULCB CR7: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINMUX | pinmux | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| GPIO | gpio | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+ + + + -| | FT232RQ / CP2102 | serial port-interrupt | -+-----------+------------------------------+--------------------------------+ -| CAN | can | normal mode | -+ + + + -| | TCAN332GDCNT | loopback mode | -+-----------+------------------------------+--------------------------------+ -| I2C | i2c | interrupt driven | -+-----------+------------------------------+--------------------------------+ -| PWM | pwm | All channels | -+-----------+------------------------------+--------------------------------+ - -It's also currently possible to write on the ram console. - -More features will be supported soon. - -Connections and IOs -=================== - -H3ULCB Board ------------- - -Here are official IOs figures from eLinux for H3ULCB board: - -`H3SK top view`_ - -`H3SK bottom view`_ - -Kingfisher Infotainment daughter board --------------------------------------- - -When connected to Kingfisher Infotainment board through COMExpress connector, the board is exposing much more IOs. - -Here are official IOs figures from eLinux for Kingfisher Infotainment board: - -`Kingfisher top view`_ - -`Kingfisher bottom view`_ - -GPIO ----- - -By running Zephyr on H3ULCB, the software readable push button 'SW3' can be used as input, and the software controllable LED 'LED5' can be used as output. - -UART ----- - -H3ULCB board is providing two serial ports, only one is commonly available on the board, however, the second one can be made available either by welding components or by plugging the board on a Kingfisher Infotainment daughter board. - -Here is information about these serial ports: - -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| Physical Interface | Physical Location | Software Interface | Converter | Further Information | -+====================+===================+====================+===========+======================================+ -| CN12 DEBUG SERIAL | ULCB Board | SCIF2 | FT232RQ | Used by U-BOOT & Linux | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| CN10 DEBUG SERIAL | ULCB Board | SCIF1 | CP2102 | Non-welded | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| CN04 DEBUG SERIAL | Kingfisher | SCIF1 | | Secondary UART // Through ComExpress | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ - -.. note:: The Zephyr console output is assigned to SCIF1 (commonly used on Kingfisher daughter board) with settings 115200 8N1 without hardware flow control by default. - -Here is CN04 UART interface pinout (depending on your Kingfisher board version): - -+--------+----------+----------+ -| Signal | Pin KF03 | Pin KF04 | -+========+==========+==========+ -| RXD | 3 | 4 | -+--------+----------+----------+ -| TXD | 5 | 2 | -+--------+----------+----------+ -| RTS | 4 | 1 | -+--------+----------+----------+ -| CTS | 6 | 3 | -+--------+----------+----------+ -| GND | 9 | 6 | -+--------+----------+----------+ - -CAN ---- - -H3ULCB board provides two CAN interfaces. Both interfaces are available on the Kingfisher daughter board. - -+--------------------+--------------------+--------------+ -| Physical Interface | Software Interface | Transceiver | -+====================+====================+==============+ -| CN17 | CAN0 | TCAN332GDCNT | -+--------------------+--------------------+--------------+ -| CN18 | CAN1 | TCAN332GDCNT | -+--------------------+--------------------+--------------+ - -.. note:: Interfaces are set to 125 kbit/s by default. - -The following table lists CAN physical interfaces pinout: - -+-----+--------+ -| Pin | Signal | -+=====+========+ -| 1 | CANH | -+-----+--------+ -| 2 | CANL | -+-----+--------+ -| 3 | GND | -+-----+--------+ - -I2C ---- - -H3ULCB board provides two I2C buses. Unfortunately direct access to these buses is not available through connectors. - -I2C is mainly used to manage and power on multiple of onboard chips on the H3ULCB and Kingfisher daughter board. - -Embedded I2C devices and I/O expanders are not yet supported. The current I2C support therefore does not make any devices available to the user at this time. - -PWM ---- - -ULCB boards provide one PWM controller with a maximum of 7 channels [0..6]. H3ULCB does provide the pwm0 from test pin CP8 only. - -When plugged on a Kingfisher daughter board, pwm4 channel is available on CN7 LVDS connector. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Supported Debug Probe -===================== - -The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This probe is supported by OpenOCD that is shipped with the Zephyr SDK. - -The "Olimex ARM-USB-OCD-H" probe needs to be connected with a SICA20I2P adapter to CN3 on H3ULCB. - -.. note:: - See `eLinux Kingfisher page`_ "Known issues" section if you encounter problem with JTAG. - -Configuring a Console -===================== - -Connect a USB cable from your PC to CN04 of your Kingfisher daughter board. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -First of all, open your serial terminal. - -Applications for the ``rcar_h3ulcb_cr7`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3ulcb_cr7 - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3ulcb_cr7 - -Debugging -========= - -First of all, open your serial terminal. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3ulcb_cr7 - :goals: debug - -You will then get access to a GDB session for debug. - -By continuing the app, you should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3ulcb_cr7 - -References -********** - -- `Renesas R-Car Starter Kit website`_ -- `Renesas R-Car H3 chip`_ -- `eLinux H3SK page`_ -- `eLinux Kingfisher page`_ - -.. _Renesas R-Car Starter Kit website: - https://www.renesas.com/br/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-m3-starter-kit - -.. _Renesas R-Car H3 chip: - https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support - -.. _eLinux H3SK page: - https://elinux.org/R-Car/Boards/H3SK - -.. _H3SK top view: - https://elinux.org/images/1/1f/R-Car-H3-topview.jpg - -.. _H3SK bottom view: - https://elinux.org/images/c/c2/R-Car-H3-bottomview.jpg - -.. _eLinux Kingfisher page: - https://elinux.org/R-Car/Boards/Kingfisher - -.. _Kingfisher top view: - https://elinux.org/images/0/08/Kfisher_top_specs.png - -.. _Kingfisher bottom view: - https://elinux.org/images/0/06/Kfisher_bot_specs.png - -.. _Install a toolchain: - https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts deleted file mode 100644 index 073f89fadb2..00000000000 --- a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2021 IoT.bzh - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -/dts-v1/; -#include -#include "rcar_h3ulcb_cr7-pinctrl.dtsi" -#include - -/ { - model = "Renesas h3ulcb board"; - compatible = "renesas,h3ulcb-cr7"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &scif1; - zephyr,shell-uart = &scif1; - zephyr,canbus = &can0; - }; - - leds { - compatible = "gpio-leds"; - user_led: led_5 { - gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button: sw3 { - gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - label = "User switch"; - zephyr,code = ; - }; - }; - - aliases { - pwm-0 = &pwm0; - led0 = &user_led; - sw0 = &user_button; - }; -}; - -&cmt0 { - status = "okay"; - clock-frequency = <32000>; -}; - -&gpio6 { - status = "okay"; -}; - -&pwm0 { - pinctrl-0 = <&pwm0_default>; - pinctrl-names = "default"; -}; - -&can0 { - pinctrl-0 = <&can0_data_a_tx_default &can0_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; - bus-speed = <125000>; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; - -&scif1 { - pinctrl-0 = <&scif1_data_a_tx_default &scif1_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.yaml b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.yaml deleted file mode 100644 index 09d5ae1c93f..00000000000 --- a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: rcar_h3ulcb_cr7 -name: Cortex r7 for Renesas H3ULCB -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - i2c - - can - - gpio - - clock_control - - uart -testing: - ignore_tags: - - isotp -vendor: renesas diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7_defconfig b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7_defconfig deleted file mode 100644 index e4fb3c34a35..00000000000 --- a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_SOC_R8A77951=y -CONFIG_SOC_SERIES_RCAR_GEN3=y -CONFIG_BOARD_RCAR_H3ULCB_CR7=y -CONFIG_CLOCK_CONTROL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000 -CONFIG_CONSOLE=y -CONFIG_RAM_CONSOLE=y -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0 -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/rcar_h3ulcb/support/openocd.cfg b/boards/arm/rcar_h3ulcb/support/openocd.cfg deleted file mode 100644 index 0395cb3efeb..00000000000 --- a/boards/arm/rcar_h3ulcb/support/openocd.cfg +++ /dev/null @@ -1,88 +0,0 @@ -# Renesas R-Car Gen3 H3ULCB Cortex-R7 Board Config - -source [find interface/ftdi/olimex-arm-usb-ocd-h.cfg] -source [find target/renesas_rcar_reset_common.cfg] -set _CHIPNAME r8a77951 -set DAP_TAPID 0x5ba00477 -set CA57_0_DBGBASE 0x80410000 -set CA57_0_CTIBASE 0x80420000 -set CR7_DBGBASE 0x80910000 -set CR7_CTIBASE 0x80918000 - -adapter srst delay 1000 -adapter speed 20000 -global $_CHIPNAME -transport select jtag - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $DAP_TAPID -dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu - -cti create $_CHIPNAME.r7.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr $CR7_CTIBASE -target create $_CHIPNAME.r7 cortex_r4 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase $CR7_DBGBASE -defer-examine - -$_CHIPNAME.r7 configure -rtos auto - -cti create $_CHIPNAME.a57.0.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr $CA57_0_CTIBASE -target create $_CHIPNAME.a57.0 aarch64 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase $CA57_0_DBGBASE -cti $_CHIPNAME.a57.0.cti - -proc reset_cr7 { assert } { - global _CHIPNAME - if { $assert == 1 } { - # Software Reset Register 2 Bit(22) Arm Realtime core - $_CHIPNAME.a57.0 mww 0xe61500b0 0x00400000 - } else { - # Software Reset Clearing Register 2 Bit(22) Arm Realtime core - $_CHIPNAME.a57.0 mww 0xe6150948 0x00400000 - } -} - -# This function make use of A5x processor to: -# - Power on the CR7 (PWRONCR7) -# - Set the boot address (CR7BAR) -# - Halt the processor -# - Deassert the CR7 reset -proc start_cr7 { args } { - global _CHIPNAME - - targets $_CHIPNAME.a57.0 - $_CHIPNAME.a57.0 arp_halt - - # CR7BAR RBAR [31:18] BAREN bit(4) - $_CHIPNAME.a57.0 mww 0xe6160070 0x40040010 - - # PWRONCR7 - $_CHIPNAME.a57.0 mww 0xe618024c 1 - # Wait until power is on. Also possible to - # poll PWRSR7 and CR7PSTR register. - sleep 100 - - $_CHIPNAME.r7 arp_examine - catch { $_CHIPNAME.r7 arp_halt } - reset_cr7 0 - - # resume a5x processor or cmt timer will not run - resume - # set CR7 processor as default target for future commands - targets $_CHIPNAME.r7 -} - -$_CHIPNAME.r7 configure -event reset-end { - global _CHIPNAME - targets $_CHIPNAME.a57.0 - # Resume the A57 processor and gives - # enough time to A57 bootloaders to set-up dram - # clocks, power management, security groups - resume - sleep 500 - $_CHIPNAME.a57.0 arp_halt - $_CHIPNAME.a57.0 arp_poll - start_cr7 -} - -$_CHIPNAME.a57.0 configure -event examine-end { - start_cr7 -} - -$_CHIPNAME.r7 configure -event gdb-attach { - reset halt -} diff --git a/boards/arm/rcar_spider/Kconfig.board b/boards/arm/rcar_spider/Kconfig.board deleted file mode 100644 index 1ff4c7e794d..00000000000 --- a/boards/arm/rcar_spider/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RCAR_SPIDER_CR52 - bool "Cortex-R52 for Renesas Spider" - depends on SOC_R8A779F0 diff --git a/boards/arm/rcar_spider/Kconfig.defconfig b/boards/arm/rcar_spider/Kconfig.defconfig deleted file mode 100644 index b2a590250f9..00000000000 --- a/boards/arm/rcar_spider/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RCAR_SPIDER_CR52 - -config BOARD - default "rcar_spider_cr52" - -endif # BOARD_RCAR_SPIDER_CR52 diff --git a/boards/arm/rcar_spider/board.cmake b/boards/arm/rcar_spider/board.cmake deleted file mode 100644 index b106c562c54..00000000000 --- a/boards/arm/rcar_spider/board.cmake +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd "--use-elf") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/rcar_spider/rcar_spider_cr52.dts b/boards/arm/rcar_spider/rcar_spider_cr52.dts deleted file mode 100644 index 6d89b3ede94..00000000000 --- a/boards/arm/rcar_spider/rcar_spider_cr52.dts +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2023 IoT.bzh - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -/dts-v1/; -#include -#include "rcar_spider_cr52-pinctrl.dtsi" -#include - -/ { - model = "Renesas Spider board"; - compatible = "renesas,spider-cr52"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &scif0; - zephyr,shell-uart = &scif0; - }; - - leds { - compatible = "gpio-leds"; - user_led: led_8 { - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button: sw10 { - gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - label = "User switch"; - zephyr,code = ; - }; - }; - - aliases { - led0 = &user_led; - sw0 = &user_button; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_data_tx_default &scif0_data_rx_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; diff --git a/boards/arm/rcar_spider/rcar_spider_cr52.yaml b/boards/arm/rcar_spider/rcar_spider_cr52.yaml deleted file mode 100644 index 6dea2b344b7..00000000000 --- a/boards/arm/rcar_spider/rcar_spider_cr52.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: rcar_spider_cr52 -name: Cortex r52 for Renesas Spider -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - gpio - - clock_control - - uart diff --git a/boards/arm/rcar_spider/rcar_spider_cr52_defconfig b/boards/arm/rcar_spider/rcar_spider_cr52_defconfig deleted file mode 100644 index 7eea72fd80a..00000000000 --- a/boards/arm/rcar_spider/rcar_spider_cr52_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_SOC_R8A779F0=y -CONFIG_SOC_SERIES_RCAR_GEN4=y -CONFIG_BOARD_RCAR_SPIDER_CR52=y -CONFIG_CLOCK_CONTROL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12500000 -CONFIG_CONSOLE=y -CONFIG_RAM_CONSOLE=y -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0 -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y diff --git a/boards/arm/rddrone_fmuk66/Kconfig.board b/boards/arm/rddrone_fmuk66/Kconfig.board deleted file mode 100644 index b6a2829208e..00000000000 --- a/boards/arm/rddrone_fmuk66/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021, Electromaticus LLC, 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RDDRONE_FMUK66 - bool "NXP RDDRONE-FMUK66" - depends on SOC_SERIES_KINETIS_K6X - select SOC_PART_NUMBER_MK66FN2M0VLQ18 diff --git a/boards/arm/rddrone_fmuk66/Kconfig.defconfig b/boards/arm/rddrone_fmuk66/Kconfig.defconfig deleted file mode 100644 index 0e70ab80ea0..00000000000 --- a/boards/arm/rddrone_fmuk66/Kconfig.defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# RDDRONE-FMUK66 board - -# Copyright (c) 2021, Electromaticus LLC, 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RDDRONE_FMUK66 - -config BOARD - default "rddrone_fmuk66" - -config OSC_XTAL0_FREQ - default 16000000 - -config MCG_PRDIV0 - default 0x0 - -config MCG_VDIV0 - default 0x4 - -config MCG_FCRDIV - default 1 - -if NETWORKING - -config NET_L2_ETHERNET - default y if !MODEM - -endif # NETWORKING - -endif # BOARD_RDDRONE_FMUK66 diff --git a/boards/arm/rddrone_fmuk66/doc/index.rst b/boards/arm/rddrone_fmuk66/doc/index.rst deleted file mode 100644 index 7c348cc6e97..00000000000 --- a/boards/arm/rddrone_fmuk66/doc/index.rst +++ /dev/null @@ -1,203 +0,0 @@ -.. _rddrone_fmuk66: - -NXP RDDRONE-FMUK66 -################## - -Overview -******** - -The RDDRONE FMUK66 is an drone control board with commonly used peripheral -connectors and a Kinetis K66 on board. - -- Comes with a J-Link Edu Mini for programming and UART console. - -.. image:: rddrone_fmuk66.jpg - :align: center - :alt: RDDRONE-FMUK66 - -Hardware -******** - -- MK66FN2MOVLQ18 MCU (180 MHz, 2 MB flash memory, 256 KB RAM, low-power, - crystal-less USB, and 144 Low profile Quad Flat Package (LQFP)) -- Dual role USB interface with micro-B USB connector -- RGB LED -- FXOS8700CQ accelerometer and magnetometer -- FXAS21002CQ gyro -- BMM150 magnetometer -- ML3114A2 barometer -- BMP280 barometer -- Connector for PWM servo/motor controls -- Connector for UART GPS/GLONASS -- SDHC - -For more information about the K64F SoC and FRDM-K64F board: - -- `K66F Website`_ -- `K66F Datasheet`_ -- `K66F Reference Manual`_ -- `RDDRONE-FMUK66 Website`_ -- `RDDRONE-FMUK66 User Guide`_ -- `RDDRONE-FMUK66 Schematics`_ - -Supported Features -================== - -The rddrone-fmuk66 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig`` - -Other hardware features are not currently supported by the port. - -System Clock -============ - -The K66F SoC is configured to use the 16 MHz external oscillator on the board -with the on-chip PLL to generate a 160 MHz system clock. - -Serial Port -=========== - -The K66F SoC has six UARTs. LPUART0 is configured for the console, UART0 is labeled Serial 2, -UART2 is labeled GPS, UART4 is labeled Serial 1. Any of these UARTs may be used as the console by -overlaying the board device tree. - -USB -=== - -The K66F SoC has a USB OTG (USBOTG) controller that supports both -device and host functions through its micro USB connector (K66F USB). -Only USB device function is supported in Zephyr at the moment. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use jlink. The board package -with accessories comes with a jlink mini edu and cable specifically for this board -along with a usb to uart that connects directly to the jlink mini edu. This is the expected -default configuration for programming and getting a console. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rddrone-fmuk66 - :gen-args: - :goals: build - -Configuring a Console -===================== - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rddrone-fmuk66 - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.7.0 ***** - Hello World! rddrone-fmuk66 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rddrone-fmuk66 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.7.0 ***** - Hello World! rddrone-fmuk66 - -.. _RDDRONE-FMUK66 Website: - -https://www.nxp.com/design/designs/px4-robotic-drone-vehicle-flight-management-unit-vmu-fmu-rddrone-fmuk66:RDDRONE-FMUK66 - -.. _RDDRONE-FMUK66 User Guide: - -https://nxp.gitbook.io/hovergames/userguide/getting-started - -.. _RDDRONE-FMUK66 Schematics: - -https://www.nxp.com/webapp/Download?colCode=SPF-39053 - -.. _K66F Website: - -https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k6x-ethernet/kinetis-k66-180-mhz-dual-high-speed-full-speed-usbs-2mb-flash-microcontrollers-mcus-based-on-arm-cortex-m4-core:K66_180 - -.. _K66F Datasheet: - -https://www.nxp.com/docs/en/data-sheet/K66P144M180SF5V2.pdf - -.. _K66F Reference Manual: - -https://www.nxp.com/webapp/Download?colCode=K66P144M180SF5RMV2 diff --git a/boards/arm/reel_board/Kconfig b/boards/arm/reel_board/Kconfig deleted file mode 100644 index 9b9c32f4209..00000000000 --- a/boards/arm/reel_board/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# reel board configuration - -# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_REEL_BOARD || BOARD_REEL_BOARD_V2 diff --git a/boards/arm/reel_board/Kconfig.board b/boards/arm/reel_board/Kconfig.board deleted file mode 100644 index 552aa3f9b52..00000000000 --- a/boards/arm/reel_board/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# reel board configuration - -# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_REEL_BOARD - bool "reel board equipped with GDEH0213B1 display" - depends on SOC_NRF52840_QIAA - -config BOARD_REEL_BOARD_V2 - bool "reel board equipped with GDEH0213B72 display" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/reel_board/Kconfig.defconfig b/boards/arm/reel_board/Kconfig.defconfig deleted file mode 100644 index 5bacbb05c5d..00000000000 --- a/boards/arm/reel_board/Kconfig.defconfig +++ /dev/null @@ -1,44 +0,0 @@ -# reel board configuration - -# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_REEL_BOARD || BOARD_REEL_BOARD_V2 - -config BOARD - default "reel_board" if BOARD_REEL_BOARD - default "reel_board_v2" if BOARD_REEL_BOARD_V2 - -config I2C - default y - -config BT_CTLR - default y - depends on BT - -if FXOS8700 - -choice FXOS8700_MODE - default FXOS8700_MODE_ACCEL -endchoice - -endif # FXOS8700 - -if LVGL - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_1 -endchoice - -config LV_Z_BITS_PER_PIXEL - default 1 - -config LV_DPI_DEF - default 130 - -config LV_Z_VDB_SIZE - default 16 - -endif # LVGL - -endif # BOARD_REEL_BOARD || BOARD_REEL_BOARD_V2 diff --git a/boards/arm/reel_board/doc/index.rst b/boards/arm/reel_board/doc/index.rst deleted file mode 100644 index dec81bd88ec..00000000000 --- a/boards/arm/reel_board/doc/index.rst +++ /dev/null @@ -1,564 +0,0 @@ -.. _reel_board: - -reel board -########## - -Overview -******** - -`reel board`_ is a evaluation board based on the Nordic Semiconductor -nRF52840 SoC. The board was developed by PHYTEC Messtechnik GmbH in -cooperation with Zephyr Project for the Hackathon - "Get Connected". -The board has a built-in debug adapter based on the DAPLink interface -firmware and NXP MK20DX128VFM5 SoC. - -It is equipped with the Electrophoretic (electronic ink) Display (EPD), -environmental (temperature, humidity, light, accelerometer) sensors, and -Bluetooth connectivity making it easy to experiment and evaluate the -Zephyr OS in these kinds of use cases: - -* battery powered sensor node -* low-power, low-cost human-machine interface (HMI) for remote - control and environmental sensor monitoring -* temperature and humidity monitor on your table -* product, name or price tag -* interactive badge for meetings and conferences - -The board provides support for the Nordic Semiconductor nRF52840 ARM |reg| -Cortex |reg|-M4F SoC with an integrated 2.4 GHz transceiver supporting Bluetooth -|reg| Low Energy and IEEE |reg| 802.15.4. - -The schematic can be found on the `reel board website`_. - -Hardware -******** - -On the front of the board are RGB-LED, ADPS9960 and HDC1010 sensors, -and Electrophoretic Display. -The RGB-LED is controlled by the nRF52840 via GPIO pins. -Display is controlled by the nRF52840 via SPI and 3 GPIOs. - -On the back side of the board are all other components such as nRF52840, -a circuit for the Debug Adapter, On/Off and power source switch, battery holder, -buttons and the MMA8652FC (accelerometer) sensor. - -ADPS9960 is a Digital Proximity, Ambient Light, RGB and Gesture sensor. -HDC1010 is a digital humidity and temperature sensor. -MMA8652FC is a 12-bit Digital Accelerometer. -All sensors are connected to the I2C bus and one GPIO pin each, -which can be used as an interrupt source. - -.. figure:: img/reel_board.jpg - :align: center - :alt: reel board front - - reel board front (Credit: PHYTEC) - -.. figure:: img/reel_board_descr_back.jpg - :align: center - :alt: reel board back - - reel board back (Credit: PHYTEC) - -Since PCB version 1507.2, the nRF52840 SoC is not soldered directly to -the board but integrated as a module on a NOTM.2 adapter. -The wiring is identical for versions 1507.1 and 1507.2. - -.. _reel_board_display: - -Display -======= - -GDEH0213B1 is the display with which the board was introduced -in 2018. Unfortunately, this display has been discontinued. -Currently the board is delivered with the display GDEH0213B72. -It is expected that the display will be replaced over time -due the short product lifecycle of this type of displays. -The following table lists the displays used on the reel board. -The label on the ribbon cable can help to distinguish the displays. -According to the display type, the correct designation must be -used for building an application. - -+--------------+--------------------+----------------------+-------------------+ -| Display | Ribbon Cable Label | Controller / Driver | Board Designation | -+==============+====================+======================+===================+ -| Good Display | HINK-E0213 | SSD1673 / | reel_board | -| GDEH0213B1 | | ssd16xx | | -+--------------+--------------------+----------------------+-------------------+ -| Good Display | HINK-E0213A22 | SSD1675A / | reel_board_v2 | -| GDEH0213B72 | | ssd16xx | | -+--------------+--------------------+----------------------+-------------------+ - -Power supply -============ - -The board is optimized for low power applications and supports two -power source configurations, battery and micro USB connector. - -The On/Off switch can choose which power source is used. - -reel board uses a TPS610981 boost converter to generate supply voltage -for nRF52840 and peripherals (sensors and EPD). -The boost converter has two modes: - -* Active mode - supply voltages for nRF52840 and peripherals are on -* Low Power mode - only supply voltage for nRF52840 is on - -The mode is controlled by MODE pin (P1.00). - -.. note:: - Actually there is no possibility to reduce energy consumption by the - Low Power mode. Both voltages are always on, see: - :zephyr_file:`boards/arm/reel_board/board.c` - -Supported Features -================== - -The reel_board board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| SENSOR | off-chip | MMA8652FC polling: | -| | | ADPS9960 polling: | -| | | HDC1010 polling | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -Port P0 -------- - -+-------+----------------------------+---------------------------+ -| Name | Function | Usage | -+=======+============================+===========================+ -| P0.00 | XL1 | 32.768 kHz oscillator | -+-------+----------------------------+---------------------------+ -| P0.01 | XL2 | 32.768 kHz oscillator | -+-------+----------------------------+---------------------------+ -| P0.02 | expansion connector pin 30 | None | -+-------+----------------------------+---------------------------+ -| P0.03 | expansion connector pin 31 | None | -+-------+----------------------------+---------------------------+ -| P0.04 | expansion connector pin 19 | None | -+-------+----------------------------+---------------------------+ -| P0.05 | expansion connector pin 11 | None | -+-------+----------------------------+---------------------------+ -| P0.06 | UART0_TX | UART Console over USB | -+-------+----------------------------+---------------------------+ -| P0.07 | Button | user button (S5) | -+-------+----------------------------+---------------------------+ -| P0.08 | UART0_RX | UART Console over USB | -+-------+----------------------------+---------------------------+ -| P0.09 | expansion connector pin 27 | None | -+-------+----------------------------+---------------------------+ -| P0.10 | expansion connector pin 29 | None | -+-------+----------------------------+---------------------------+ -| P0.11 | RGB LED (red) | GPIO | -+-------+----------------------------+---------------------------+ -| P0.12 | RGB LED (green) | GPIO | -+-------+----------------------------+---------------------------+ -| P0.13 | PWM LED | Buzzer | GPIO | -+-------+----------------------------+---------------------------+ -| P0.14 | EPD Busy output | GPIO | -+-------+----------------------------+---------------------------+ -| P0.15 | EPD Reset input | GPIO | -+-------+----------------------------+---------------------------+ -| P0.16 | EPD DC input | GPIO | -+-------+----------------------------+---------------------------+ -| P0.17 | EPD SPI3_CS | SPI | -+-------+----------------------------+---------------------------+ -| P0.18 | CPU Reset | Reset (S4) | -+-------+----------------------------+---------------------------+ -| P0.19 | EPD SPI3_CLK | SPI | -+-------+----------------------------+---------------------------+ -| P0.20 | EPD SPI3_MOSI | SPI | -+-------+----------------------------+---------------------------+ -| P0.21 | SPI3_MISO | SPI (not connected) | -+-------+----------------------------+---------------------------+ -| P0.22 | HDC1010 DRDYn | GPIO | -+-------+----------------------------+---------------------------+ -| P0.23 | APDS9960 INT | GPIO | -+-------+----------------------------+---------------------------+ -| P0.24 | MMA8652FC INT1 | GPIO | -+-------+----------------------------+---------------------------+ -| P0.25 | MMA8652FC INT2 | GPIO | -+-------+----------------------------+---------------------------+ -| P0.26 | I2C_0 | I2C | -+-------+----------------------------+---------------------------+ -| P0.27 | I2C_0 | I2C | -+-------+----------------------------+---------------------------+ -| P0.28 | expansion connector pin 3 | None | -+-------+----------------------------+---------------------------+ -| P0.29 | expansion connector pin 52 | None | -+-------+----------------------------+---------------------------+ -| P0.30 | expansion connector pin 1 | None | -+-------+----------------------------+---------------------------+ -| P0.31 | expansion connector pin 37 | None | -+-------+----------------------------+---------------------------+ - -Port P1 -------- - -+-------+----------------------------+---------------------------+ -| Name | Function | Usage | -+=======+============================+===========================+ -| P1.00 | peripheral power on | GPIO | -+-------+----------------------------+---------------------------+ -| P1.01 | expansion connector pin 32 | None | -+-------+----------------------------+---------------------------+ -| P1.02 | expansion connector pin 34 | None | -+-------+----------------------------+---------------------------+ -| P1.03 | expansion connector pin 17 | None | -+-------+----------------------------+---------------------------+ -| P1.04 | expansion connector pin 15 | None | -+-------+----------------------------+---------------------------+ -| P1.05 | expansion connector pin 13 | None | -+-------+----------------------------+---------------------------+ -| P1.06 | expansion connector pin 33 | None | -+-------+----------------------------+---------------------------+ -| P1.07 | expansion connector pin 35 | None | -+-------+----------------------------+---------------------------+ -| P1.08 | expansion connector pin 45 | None | -+-------+----------------------------+---------------------------+ -| P1.09 | RGB LED (blue) | GPIO | -+-------+----------------------------+---------------------------+ -| P1.10 | expansion connector pin 47 | None | -+-------+----------------------------+---------------------------+ -| P1.11 | expansion connector pin 49 | None | -+-------+----------------------------+---------------------------+ -| P1.12 | expansion connector pin 51 | None | -+-------+----------------------------+---------------------------+ -| P1.13 | expansion connector pin 36 | None | -+-------+----------------------------+---------------------------+ -| P1.14 | expansion connector pin 48 | None | -+-------+----------------------------+---------------------------+ -| P1.15 | expansion connector pin 50 | None | -+-------+----------------------------+---------------------------+ - -Solder Jumper and Testpoints -============================ - -There are several labeled solder jumpers on the board. -These can be used to connect a logic analyzer to check the behavior of a -driver or to measure the voltage of a signal. - -.. figure:: img/reel_board_tp.jpg - :align: center - :alt: reel board Jumper and Testpoints - - reel board testpoints (Credit: PHYTEC) - -I2C bus and sensors testpoints ------------------------------- - -+-------+-----------------------+---------------------------+ -| Name | Type | Usage | -+=======+=======================+===========================+ -| J19 | closed solder jumper | testpoint I2C SDA | -+-------+-----------------------+---------------------------+ -| J20 | closed solder jumper | testpoint I2C SCL | -+-------+-----------------------+---------------------------+ -| J7 | closed solder jumper | testpoint INT1 MMA8652FC | -+-------+-----------------------+---------------------------+ -| J24 | closed solder jumper | testpoint INT2 MMA8652FC | -+-------+-----------------------+---------------------------+ -| J11 | closed solder jumper | testpoint INT APDS9960 | -+-------+-----------------------+---------------------------+ -| J12 | closed solder jumper | testpoint DRDYn HDC1010 | -+-------+-----------------------+---------------------------+ - -EPD testpoints --------------- - -+-------+-----------------------+---------------------------+ -| Name | Type | Usage | -+=======+=======================+===========================+ -| J13 | closed solder jumper | testpoint EPD Busy | -+-------+-----------------------+---------------------------+ -| J14 | closed solder jumper | testpoint EPD Reset | -+-------+-----------------------+---------------------------+ -| J15 | closed solder jumper | testpoint EPD DC | -+-------+-----------------------+---------------------------+ -| J16 | closed solder jumper | testpoint EPD SPI_CS | -+-------+-----------------------+---------------------------+ -| J17 | closed solder jumper | testpoint EPD SPI_CLK | -+-------+-----------------------+---------------------------+ -| J18 | closed solder jumper | testpoint EPD SPI_MOSI | -+-------+-----------------------+---------------------------+ - -Power supply testpoint ----------------------- - -+-------+-----------------------+-------------------------------------------+ -| Name | Type | Usage | -+=======+=======================+===========================================+ -| J21 | closed solder jumper | testpoint peripheral voltage on/off | -+-------+-----------------------+-------------------------------------------+ -| TP11 | testpoint | testpoint peripheral voltage | -+-------+-----------------------+-------------------------------------------+ -| TP12 | testpoint | testpoint nRF52840 supply voltage VDD_nRF | -+-------+-----------------------+-------------------------------------------+ -| TP13 | testpoint | testpoint boost converter input voltage | -+-------+-----------------------+-------------------------------------------+ - -Built-in Debug Adapter -====================== - -The debug adapter is based on the DAPLink interface firmware and -NXP MK20DX128VFM5 SoC. The adapter is powered via a micro USB connector and -is always on when the board is connected to the USB host. -reel board can be flashed and debugged, powered either from battery or USB. -If the Adapter is powered via USB, the Adapter circuit heats the board -slightly and the temperature sensor can output values up to 1.5 degrees higher. - -.. figure:: img/reel_board_debug.jpg - :align: center - :alt: reel board Debug Adapter - - reel board Debug Adapter overview (Credit: PHYTEC) - -Debug Adapter Firmware ----------------------- - -DAPLink firmware for the adapter can be found at `DAPLink reel board Firmware`_. -To update the firmware (if necessary), the adapter must be started in bootloader -mode. For this, the board should be disconnected from the USB host, -the J22 should be closed (use tweezers for this) and the board reconnected to -the USB host. - -Debug Adapter Jumper --------------------- - -+-------+-----------------------+----------------------------------------------+ -| Name | Type | Usage | -+=======+=======================+==============================================+ -| J3 | open solder jumper | close to pass UART TX to external adapter | -+-------+-----------------------+----------------------------------------------+ -| J4 | open solder jumper | close to pass UART RX to external adapter | -+-------+-----------------------+----------------------------------------------+ -| J22 | open solder jumper | close to start adapter in bootloader mode | -+-------+-----------------------+----------------------------------------------+ - -Adapter LEDs ------------- - -+-------+-----------------------+--------------------------------+ -| Name | Type | Usage | -+=======+=======================+================================+ -| D11 | green | flashes when adapter is active | -+-------+-----------------------+--------------------------------+ -| D14 | red | reserved | -+-------+-----------------------+--------------------------------+ -| D15 | yellow | reserved | -+-------+-----------------------+--------------------------------+ - -Expansion Connector -************************ - -The expansion connector has the same dimensions and similar pinout -as the BBC MicroBit edge connector. The expansion components that are -designed especially for the reel board are called link boards. - -.. figure:: img/reel_board_excon.jpg - :align: center - :alt: reel board Expansion Connector - - reel board Expansion Connector (Credit: PHYTEC) - -link board BASE -=============== - -link board BASE is a passive expansion board and allows other link boards or -third party shields in Arduino UNO R3 format to be connected to the reel board. -In addition, it includes a NOTM.2 connector and more powerful DCDC converter -then reel board. - -.. figure:: img/rb_lb_shield.jpg - :align: center - :alt: reel board and link board BASE - - reel board and link board BASE (Credit: PHYTEC) - -link board BASE can be used in combination with other link boards or -third party shields in two ways: - - As an adapter - reel board is plugged into the link board BASE. Both peripherals on - reel board and shields can be used as long as there is no conflict - between I2C devices. Care should be taken to provide enough power - to the complete circuit. - - Stand-alone - NOTM.2 adapter is removed from the reel board and - connected to NOTM.2 connector on the link board BASE. - The wiring to the shield connector is identical to the - configuration above and no software modifications for the shield - are necessary. - Stand-alone configuration is more suitable for applications where - peripherals on the reel board are not used or in conflict, - power provided by the reel board is not enough, - or for prototypes in the field. - -.. figure:: img/link_board_base.jpg - :align: center - :alt: link board BASE - - link board BASE (Credit: PHYTEC) - -Components on the link board BASE: - - reel board Connector: - 2x40 position edge connector. - - Micro USB Connector: - USB can be used as power source. USB data lines are wired - to NOTM.2 connector. - - NOTM.2 Connector: - Connector for NOTM.2 adapter. If the connector is used then - reel board should be removed from reel board connector. - - SWD Connector X11: - Wired to NOTM.2 connector. A debug probe can - be connected to program or debug MCU in Stand-alone configuration. - - Alternative Power Source X5 or X9: - Positive pin is closer to the + character. Nominal voltage is - 3.3V, there is no protection against reverse polarity or overvoltage. - Use it with care. - - Shield Connector: - Connector for link boards and third party shields in Arduino UNO R3 - format. Only shields designed for 3.3V supply voltage are supported. - -Meaning of the Power Source Switch positions: - - EXT - link board BASE is powered from Alternative Power Source Connector - X9 or X5. - - USB - link board BASE is powered from USB connector (via DCDC converter). - - RB - link board BASE is powered from reel board. The available power is - below 0.3W and depends on which source is used to power the reel board. - -Programming and Debugging -************************* - -Applications for the ``reel_board`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - -Flashing -======== - -If you use Linux, create a udev rule (as ``root``) to fix a permission issue -when not using root for flashing. - -.. code-block:: console - - # echo 'ATTR{idProduct}=="0204", ATTR{idVendor}=="0d28", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-cmsis-dap.rules - -Reload the rules and replug the device. - -.. code-block:: console - - $ sudo udevadm control --reload-rules - -Finally, unplug and plug the board again for the rules to take effect. - -Build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the reel board -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: reel_board - :goals: build flash - -.. note:: - Please use reel_board_v2 to build a application for the board equipped with - the GDEH0213B72, see :ref:`reel_board_display`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: reel_board_v2 - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: reel_board - :maybe-skip-config: - :goals: debug - - -Testing the LEDs and buttons -**************************** - -There are 2 samples that allow you to test that the buttons (switches) and -LEDs on the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. - -References -********** - -.. _reel board Website: - https://www.phytec.de/reelboard/ - -.. target-notes:: - -.. _reel board: - https://www.phytec.de/reelboard/ - -.. _DAPLink reel board Firmware: - https://github.com/PHYTEC-Messtechnik-GmbH/DAPLink/tree/reel-board diff --git a/boards/arm/reel_board/reel_board_defconfig b/boards/arm/reel_board/reel_board_defconfig deleted file mode 100644 index 8e88a3b3231..00000000000 --- a/boards/arm/reel_board/reel_board_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_REEL_BOARD=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/reel_board/reel_board_v2.dts b/boards/arm/reel_board/reel_board_v2.dts deleted file mode 100644 index 37c0f6c1397..00000000000 --- a/boards/arm/reel_board/reel_board_v2.dts +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH - * Copyright (c) 2017 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "reel_board.dtsi" -#include "reel_board_v2-pinctrl.dtsi" - -/ { - model = "reel board v2"; - compatible = "phytec,reel_board_v2"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,display = &ssd16xx; - }; - - aliases { - watchdog0 = &wdt0; - }; -}; - -&spi1 { - compatible = "nordic,nrf-spi"; - status = "okay"; - cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; - pinctrl-names = "default", "sleep"; - ssd16xx: ssd16xxfb@0 { - compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a"; - spi-max-frequency = <4000000>; - reg = <0>; - width = <250>; - height = <122>; - reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - dc-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - busy-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - - full { - gdv = [15]; - sdv = [41 a8 32]; - vcom = <0x26>; - border-waveform = <0x03>; - dummy-line = <0x30>; - gate-line-width = <0x0a>; - lut = [ - /* - * Waveform Composition - * - * There are 7 Voltage Source (VS) Level groups - * n = {0,1,2...6}, each group contains - * 4 phases x = {A,B,C,D}. - * 2 bits represent the voltage in a phase: - * 00 – VSS, 01 – VSH1, 10 – VSL, 11 - VSH2 - * - * For example 0x80 represents sequence VSL-VSS-VSS-VSS, - */ - 80 60 40 00 00 00 00 /* LUT0: BB: VS 0..6 */ - 10 60 20 00 00 00 00 /* LUT1: BW: VS 0..6 */ - 80 60 40 00 00 00 00 /* LUT2: WB: VS 0..6 */ - 10 60 20 00 00 00 00 /* LUT3: WW: VS 0..6 */ - 00 00 00 00 00 00 00 /* LUT4: VCOM: VS 0..6 */ - /* - * TPnx determines the length of each phase, - * and RPn repeat count of a sequence. - * TPnA, TPnB, TPnC, TPnD, RPn - * - * For example TP0A=3, TP0B=3, and RP0=2: - * VS sequence : VSL-VSS-VSS-VSS - * number of Gate Pulses (length) : 3 3 0 0 - * repeat count : 2 - */ - 03 03 00 00 02 /* TP0A TP0B TP0C TP0D RP0 */ - 09 09 00 00 02 /* TP1A TP1B TP1C TP1D RP1 */ - 03 03 00 00 02 /* TP2A TP2B TP2C TP2D RP2 */ - 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ - 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ - 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ - 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ - ]; - }; - - partial { - gdv = [15]; - sdv = [41 a8 32]; - vcom = <0x26>; - border-waveform = <0x01>; - dummy-line = <0x30>; - gate-line-width = <0x0a>; - lut = [ - 00 00 00 00 00 00 00 /* LUT0: BB: VS0..6 */ - 80 00 00 00 00 00 00 /* LUT1: BW: VS0..6 */ - 40 00 00 00 00 00 00 /* LUT2: WB: VS0..6 */ - 80 00 00 00 00 00 00 /* LUT3: WW: VS0..6 */ - 00 00 00 00 00 00 00 /* LUT4: VCOM: VS0..6 */ - 0A 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */ - 00 00 00 00 00 /* TP1A TP1B TP1C TP1D RP1 */ - 00 00 00 00 00 /* TP2A TP2B TP2C TP2D RP2 */ - 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ - 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ - 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ - 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ - ]; - }; - }; -}; diff --git a/boards/arm/reel_board/reel_board_v2.yaml b/boards/arm/reel_board/reel_board_v2.yaml deleted file mode 100644 index 2b27622e089..00000000000 --- a/boards/arm/reel_board/reel_board_v2.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: reel_board_v2 -name: reel-board-v2 -type: mcu -arch: arm -ram: 512 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - i2c - - spi - - gpio - - usb_device - - usb_cdc - - ble - - pwm - - arduino_i2c - - arduino_spi - - arduino_gpio -vendor: phytec diff --git a/boards/arm/reel_board/reel_board_v2_defconfig b/boards/arm/reel_board/reel_board_v2_defconfig deleted file mode 100644 index fcec54b6d0c..00000000000 --- a/boards/arm/reel_board/reel_board_v2_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_REEL_BOARD_V2=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/rm1xx_dvk/Kconfig.board b/boards/arm/rm1xx_dvk/Kconfig.board deleted file mode 100644 index f5c1f23b932..00000000000 --- a/boards/arm/rm1xx_dvk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# rm1xx_dvk board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RM1XX_DVK - bool "RM1XX_DVK" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/rm1xx_dvk/Kconfig.defconfig b/boards/arm/rm1xx_dvk/Kconfig.defconfig deleted file mode 100644 index 22a717477d2..00000000000 --- a/boards/arm/rm1xx_dvk/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# rm1xx_dvk board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RM1XX_DVK - -config BOARD - default "rm1xx_dvk" - -config BT_CTLR - default BT - -endif # BOARD_RM1XX_DVK diff --git a/boards/arm/rm1xx_dvk/pre_dt_board.cmake b/boards/arm/rm1xx_dvk/pre_dt_board.cmake deleted file mode 100644 index 5cdf5c021e8..00000000000 --- a/boards/arm/rm1xx_dvk/pre_dt_board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - power@40000000 & clock@40000000 & nrf-mpu@40000000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/rm1xx_dvk/rm1xx_dvk_defconfig b/boards/arm/rm1xx_dvk/rm1xx_dvk_defconfig deleted file mode 100644 index cee5bb0b4a0..00000000000 --- a/boards/arm/rm1xx_dvk/rm1xx_dvk_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y -CONFIG_BOARD_RM1XX_DVK=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_PINCTRL=y diff --git a/boards/arm/ronoth_lodev/Kconfig.board b/boards/arm/ronoth_lodev/Kconfig.board deleted file mode 100644 index c0135583575..00000000000 --- a/boards/arm/ronoth_lodev/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Ronoth LoDev board configuration -# Copyright (c) 2020/2021 Dean Weiten -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RONOTH_LODEV - bool "Ronoth LoDev" - depends on SOC_STM32L073XX diff --git a/boards/arm/ronoth_lodev/Kconfig.defconfig b/boards/arm/ronoth_lodev/Kconfig.defconfig deleted file mode 100644 index 5e3a44a811e..00000000000 --- a/boards/arm/ronoth_lodev/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Ronoth LoDev board configuration -# Copyright (c) 2020/2021 Dean Weiten -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RONOTH_LODEV - -config BOARD - default "ronoth_lodev" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_RONOTH_LODEV diff --git a/boards/arm/rpi_pico/Kconfig.board b/boards/arm/rpi_pico/Kconfig.board deleted file mode 100644 index e2c1318db67..00000000000 --- a/boards/arm/rpi_pico/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RPI_PICO - bool "Raspberry Pi Pico Board" - depends on SOC_RP2040 - -config BOARD_RPI_PICO_W - bool "Raspberry Pi Pico W Board" - depends on SOC_RP2040 diff --git a/boards/arm/rpi_pico/Kconfig.defconfig b/boards/arm/rpi_pico/Kconfig.defconfig deleted file mode 100644 index a664665480b..00000000000 --- a/boards/arm/rpi_pico/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RPI_PICO || BOARD_RPI_PICO_W - -config BOARD - default "rpi_pico" if BOARD_RPI_PICO - default "rpi_pico_w" if BOARD_RPI_PICO_W - -config RP2_FLASH_W25Q080 - default y - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 125 - -endif #I2C_DW - -config USB_SELF_POWERED - default n - -endif # BOARD_RPI_PICO || BOARD_RPI_PICO_W diff --git a/boards/arm/rpi_pico/rpi_pico_w.yaml b/boards/arm/rpi_pico/rpi_pico_w.yaml deleted file mode 100644 index d0acab19cc6..00000000000 --- a/boards/arm/rpi_pico/rpi_pico_w.yaml +++ /dev/null @@ -1,24 +0,0 @@ -identifier: rpi_pico_w -name: RaspberryPi-Pico-w -type: mcu -arch: arm -flash: 2048 -ram: 264 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - uart - - gpio - - adc - - i2c - - spi - - hwinfo - - watchdog - - pwm - - flash - - dma - - pio - - counter - - clock diff --git a/boards/arm/rpi_pico/rpi_pico_w_defconfig b/boards/arm/rpi_pico/rpi_pico_w_defconfig deleted file mode 100644 index 9b3868541d1..00000000000 --- a/boards/arm/rpi_pico/rpi_pico_w_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_RPI_PICO_W=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y -CONFIG_USE_DT_CODE_PARTITION=y -CONFIG_BUILD_OUTPUT_UF2=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_RESET=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/ruuvi_ruuvitag/Kconfig.board b/boards/arm/ruuvi_ruuvitag/Kconfig.board deleted file mode 100644 index 39a7af5dee9..00000000000 --- a/boards/arm/ruuvi_ruuvitag/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2020 Ruuvi Innovations Ltd (Oy) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RUUVI_RUUVITAG - bool "Ruuvi-RuuviTag" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/ruuvi_ruuvitag/Kconfig.defconfig b/boards/arm/ruuvi_ruuvitag/Kconfig.defconfig deleted file mode 100644 index fb5618995ff..00000000000 --- a/boards/arm/ruuvi_ruuvitag/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Ruuvi RuuviTag configuration - -# Copyright (c) 2020 Ruuvi Innovations Ltd (Oy) -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RUUVI_RUUVITAG - -config BOARD - default "ruuvi_ruuvitag" - -config SPI - default y - -config BT_CTLR - default BT - -endif # BOARD_RUUVI_RUUVITAG diff --git a/boards/arm/ruuvi_ruuvitag/doc/index.rst b/boards/arm/ruuvi_ruuvitag/doc/index.rst deleted file mode 100644 index 5ab0ea9cfc0..00000000000 --- a/boards/arm/ruuvi_ruuvitag/doc/index.rst +++ /dev/null @@ -1,184 +0,0 @@ -.. _ruuvi_ruuvitag: - -Ruuvi RuuviTag -############## - -Overview -******** - -RuuviTag is an advanced battery-operated open-source Bluetooth -enabled sensor beacon platform capable of sending temperature, humidity, -pressure, and motion information over Bluetooth Low Energy. - -.. figure:: img/ruuvitag.jpg - :align: center - :alt: RUUVI RuuviTag - - RUUVI RuuviTag (Credit: https://ruuvi.com/) - -More information about the board can be found at the -`ruuvitag website`_. - -Hardware -******** - -RuuviTag's have the following physical features: - -* Nordic Semiconductor nRF52832 System-on-Chip -* STMicroelectronics LIS2DH12 accelerometer -* Bosch BME 280 temperature + relative air humidity + air pressure sensor -* NFC™-A tag antenna -* 1000mAh CR2477 battery -* 2 buttons -* 1 Green LED -* 1 Red LED -* IP67 Enclosure -* Long range RF antenna - -Supported Features -================== - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ -| Humidity, | on-board | bme280 | -| Temp & Air| | | -| Pressure | | | -+-----------+------------+----------------------+ -| Acc | on-board | lis2dh12 | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.17 -* LED1 (green) = P0.19 - -Push buttons ------------- - -* BUTTON0 = SW1 = P0.13 - -Pin descriptions ----------------- - -.. figure:: img/pinout.jpg - :align: center - :alt: RUUVI Pinout - -* 2 = P0.29 = SPI_SCK -* 3 = P0.28 = SPI_MISO -* 10 = P0.04 = GPIO (can be used as a GPIO / ADC pin) -* 11 = P0.05 = GPIO (can be used as a GPIO / ADC pin) -* 12 = P0.25 = SPI_MOSI -* 13 = P0.19 = LED2 (green) / GPIO (can be used as a GPIO pin but the LED will blink) -* 14 = P0.17 = LED1 (red) / GPIO (can be used as a GPIO pin but the LED will blink) -* 15 = P0.13 = Button / GPIO (can be used as a GPIO pin) -* 16 = GND (Battery's negative contact) -* 17 = Battery's positive contact -* 18 = Battery's positive contact -* 19 = SWDIO -* 20 = SWDCLK -* 21 = P0.18 = SWO / GPIO (can be used as a GPIO pin) -* 22 = P0.21 = Reset / GPIO (can be used as a GPIO pin if no need to reset the device) -* 23 = GND (Battery's negative contact) -* 24 = P0.31 = GPIO (can be used as a GPIO / ADC pin) -* 25 = P0.30 = GPIO (can be used as a GPIO / ADC pin) - -GPIO = General Purpose Input Output pin - -P1 = Standard 10-pin ARM Cortex debug connector (on RuuviTag Rev.B1-B5) - -* 1 = VDD -* 2 = SWDIO -* 3 = GND (Battery's negative contact) -* 4 = SWDCLK -* 5 = GND (Battery's negative contact) -* 6 = SWO -* 7 = No Connect -* 8 = No Connect -* 9 = GND (Battery's negative contact) -* 10 = Reset - -P1 = TC2030 TagConnect (on RuuviTag Rev.B6) - -* 1 = Battery's positive contact -* 2 = SWDIO -* 3 = Reset -* 4 = SWDCLK -* 5 = GND (Battery's negative contact) -* 6 = SWO - - -Programming and Debugging -************************* - -Flashing -======== - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -The easiest way to flash Zephyr onto a RuuviTag requires an external Ruuvi DEVKIT. More information about the board can be found at the -`ruuvitag devkit`_. - -Once your tag is connected to the DEVKIT and connected to your PC, build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: ruuvi_ruuvitag - :goals: build flash - -Advanced users may want to program the RuuviTag without the DEVKIT, this can be achieved via the SWDIO and SWDCLK pins located on the back of the RuuviTag. - -Debugging -========= - -If using the Ruuvi DEVKIT refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -Testing the LEDs and buttons on the RuuviTag -******************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in :file:`boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag.dts`. - -References -********** - -.. target-notes:: - -.. _ruuvitag website: https://ruuvi.com -.. _ruuvitag datasheet: https://ruuvi.com/files/ruuvitag-tech-spec-2019-7.pdf -.. _ruuvitag devkit: https://lab.ruuvi.com/devshield/ diff --git a/boards/arm/rzt2m_starterkit/Kconfig.board b/boards/arm/rzt2m_starterkit/Kconfig.board deleted file mode 100644 index 9fddcf006a4..00000000000 --- a/boards/arm/rzt2m_starterkit/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RZT2M_STARTER_KIT - bool "RZ/T2M Starter Kit Board" - depends on SOC_RENESAS_RZT2M diff --git a/boards/arm/rzt2m_starterkit/Kconfig.defconfig b/boards/arm/rzt2m_starterkit/Kconfig.defconfig deleted file mode 100644 index 9699b23963c..00000000000 --- a/boards/arm/rzt2m_starterkit/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RZT2M_STARTER_KIT - -config BOARD - default "rzt2m_starter_kit" - -endif diff --git a/boards/arm/rzt2m_starterkit/rzt2m_starter_kit_defconfig b/boards/arm/rzt2m_starterkit/rzt2m_starter_kit_defconfig deleted file mode 100644 index 8b994e00082..00000000000 --- a/boards/arm/rzt2m_starterkit/rzt2m_starter_kit_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_RENESAS_RZT2M=y -CONFIG_BOARD_RZT2M_STARTER_KIT=y - -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/s32z270dc2_r52/Kconfig.board b/boards/arm/s32z270dc2_r52/Kconfig.board deleted file mode 100644 index 9e54998880d..00000000000 --- a/boards/arm/s32z270dc2_r52/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_S32Z270DC2_RTU0_R52 - bool "NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores" - depends on SOC_SERIES_S32ZE_R52 - select SOC_PART_NUMBER_S32Z27 - -config BOARD_S32Z270DC2_RTU1_R52 - bool "NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores" - depends on SOC_SERIES_S32ZE_R52 - select SOC_PART_NUMBER_S32Z27 diff --git a/boards/arm/s32z270dc2_r52/Kconfig.defconfig b/boards/arm/s32z270dc2_r52/Kconfig.defconfig deleted file mode 100644 index 6d32c923542..00000000000 --- a/boards/arm/s32z270dc2_r52/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_S32Z270DC2_RTU0_R52 || BOARD_S32Z270DC2_RTU1_R52 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "s32z270dc2_rtu0_r52" if BOARD_S32Z270DC2_RTU0_R52 - default "s32z270dc2_rtu1_r52" if BOARD_S32Z270DC2_RTU1_R52 - -config NXP_S32_RTU_INDEX - default 0 if BOARD_S32Z270DC2_RTU0_R52 - default 1 if BOARD_S32Z270DC2_RTU1_R52 - -if SERIAL - -config UART_INTERRUPT_DRIVEN - default y - -config UART_CONSOLE - default y - -endif # SERIAL - -if SHELL - -config SHELL_STACK_SIZE - default 4096 - -endif # SHELL - -endif # BOARD_S32Z270DC2_RTU0_R52 || BOARD_S32Z270DC2_RTU1_R52 diff --git a/boards/arm/s32z270dc2_r52/doc/index.rst b/boards/arm/s32z270dc2_r52/doc/index.rst deleted file mode 100644 index e940a144f1f..00000000000 --- a/boards/arm/s32z270dc2_r52/doc/index.rst +++ /dev/null @@ -1,311 +0,0 @@ -.. _s32z270dc2_r52: - -NXP X-S32Z27X-DC (DC2) -###################### - -Overview -******** - -The X-S32Z27X-DC (DC2) board is based on the NXP S32Z270 Real-Time Processor, -which includes two Real-Time Units (RTU) composed of four ARM Cortex-R52 cores -each, with flexible split/lock configurations. - -There is one Zephyr board per RTU: - -- ``s32z270dc2_rtu0_r52``, for RTU0 -- ``s32z270dc2_rtu1_r52``, for RTU1. - -Hardware -******** - -Information about the hardware and design resources can be found at -`NXP S32Z2 Real-Time Processors website`_. - -Supported Features -================== - -The boards support the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| Arm GIC | on-chip | interrupt_controller | -+-----------+------------+-------------------------------------+ -| Arm Timer | on-chip | timer | -+-----------+------------+-------------------------------------+ -| LINFlexD | on-chip | serial | -+-----------+------------+-------------------------------------+ -| MRU | on-chip | mbox | -+-----------+------------+-------------------------------------+ -| NETC | on-chip | ethernet | -| | | | -| | | mdio | -+-----------+------------+-------------------------------------+ -| SIUL2 | on-chip | pinctrl | -| | | | -| | | gpio | -| | | | -| | | external interrupt controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| SWT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| CANEXCEL | on-chip | can | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The SoC's pads are grouped into ports and pins for consistency with GPIO driver -and the HAL drivers used by this Zephyr port. The following table summarizes -the mapping between pads and ports/pins. This must be taken into account when -using GPIO driver or configuring the pinmuxing for the device drivers. - -+-------------------+-------------+ -| Pads | Port/Pins | -+===================+=============+ -| PAD_000 - PAD_015 | PA0 - PA15 | -+-------------------+-------------+ -| PAD_016 - PAD_030 | PB0 - PB14 | -+-------------------+-------------+ -| PAD_031 | PC15 | -+-------------------+-------------+ -| PAD_032 - PAD_047 | PD0 - PD15 | -+-------------------+-------------+ -| PAD_048 - PAD_063 | PE0 - PE15 | -+-------------------+-------------+ -| PAD_064 - PAD_079 | PF0 - PF15 | -+-------------------+-------------+ -| PAD_080 - PAD_091 | PG0 - PG11 | -+-------------------+-------------+ -| PAD_092 - PAD_095 | PH12 - PH15 | -+-------------------+-------------+ -| PAD_096 - PAD_111 | PI0 - PI15 | -+-------------------+-------------+ -| PAD_112 - PAD_127 | PJ0 - PJ15 | -+-------------------+-------------+ -| PAD_128 - PAD_143 | PK0 - PK15 | -+-------------------+-------------+ -| PAD_144 - PAD_145 | PL0 - PL1 | -+-------------------+-------------+ -| PAD_146 - PAD_159 | PM2 - PM15 | -+-------------------+-------------+ -| PAD_160 - PAD_169 | PN0 - PN9 | -+-------------------+-------------+ -| PAD_170 - PAD_173 | PO10 - PO13 | -+-------------------+-------------+ - -This board does not include user LED's or switches, which are needed for some -of the samples such as :zephyr:code-sample:`blinky` or :zephyr:code-sample:`button`. -Follow the steps described in the sample description to enable support for this -board. - -System Clock -============ - -The Cortex-R52 cores are configured to run at 800 MHz. - -Serial Port -=========== - -The SoC has 12 LINFlexD instances that can be used in UART mode. The console can -be accessed by default on the USB micro-B connector `J119`. - -Watchdog -======== - -The watchdog driver only supports triggering an interrupt upon timer expiration. -Zephyr is currently running from SRAM on this board, thus system reset is not -supported. - -Ethernet -======== - -NETC driver supports to manage the Physical Station Interface (PSI0) and/or a -single Virtual SI (VSI). The rest of the VSI's shall be assigned to different -cores of the system. Refer to :ref:`nxp_s32_netc-samples` to learn how to -configure the Ethernet network controller. - -Controller Area Network (CAN) -============================= - -Currently, the CANXL transceiver is not populated in this board. So CAN transceiver -connection is required for running external traffic. We can use any CAN transceiver, -which supports CAN 2.0 and CAN FD protocol. - -CAN driver supports classic (CAN 2.0) and CAN FD mode. Remote transmission request is -not supported as this feature is not available on NXP S32 CANXL HAL. - -Programming and Debugging -************************* - -Applications for the ``s32z270dc2_rtu0_r52`` and ``s32z270dc2_rtu1_r52`` boards -can be built in the usual way as documented in :ref:`build_an_application`. - -Currently is only possible to load and execute a Zephyr application binary on -this board from the core internal SRAM. - -This board supports West runners for the following debug tools: - -- :ref:`NXP S32 Debug Probe ` (default) -- :ref:`Lauterbach TRACE32 ` - -Follow the installation steps of the debug tool you plan to use before loading -your firmware. - -Set-up the Board -================ - -Connect the external debugger probe to the board's JTAG connector (``J134``) -and to the host computer via USB or Ethernet, as supported by the probe. - -For visualizing the serial output, connect the board's USB/UART port (``J119``) to -the host computer and run your favorite terminal program to listen for output. -For example, using the cross-platform `pySerial miniterm`_ terminal: - -.. code-block:: console - - python -m serial.tools.miniterm 115200 - -Replace ```` with the port where the board can be found. For example, -under Linux, ``/dev/ttyUSB0``. - -Debugging -========= - -You can build and debug the :ref:`hello_world` sample for the board -``s32z270dc2_rtu0_r52`` with: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52 - :goals: build debug - -In case you are using a newer PCB revision, you have to use an adapted board -definition as the default PCB revision is B. For example, if using revision D: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52@D - :goals: build debug - :compact: - -At this point you can do your normal debug session. Set breakpoints and then -:kbd:`c` to continue into the program. You should see the following message in -the terminal: - -.. code-block:: console - - Hello World! s32z270dc2_rtu0_r52 - -To debug with Lauterbach TRACE32 softare run instead: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52 - :goals: build debug -r trace32 - :compact: - -Flashing -======== - -Follow these steps if you just want to download the application to the board -SRAM and run. - -``flash`` command is supported only by the Lauterbach TRACE32 runner: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52 - :goals: build flash -r trace32 - :compact: - -.. note:: - Currently, the Lauterbach start-up scripts executed with ``flash`` and - ``debug`` commands perform the same steps to initialize the SoC and - load the application to SRAM. The difference is that ``flash`` hides the - Lauterbach TRACE32 interface, executes the application and exits. - -To imitate a similar behavior using NXP S32 Debug Probe runner, you can run the -``debug`` command with GDB in batch mode: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52 - :goals: build debug --tool-opt='--batch' - :compact: - -RTU and Core Configuration -========================== - -This Zephyr port can only run single core in any of the Cortex-R52 cores, -either in lock-step or split-lock mode. By default, Zephyr runs on the first -core of the RTU chosen and in lock-step mode (which is the reset -configuration). - -To build for split-lock mode, the :kconfig:option:`CONFIG_DCLS` must be -disabled from your application Kconfig file. - -By default the board configuration will set the runner arguments according to -the build configuration. To debug for a core different than the default use: - -.. tabs:: - - .. group-tab:: lockstep configuration - - .. code-block:: console - - west debug --core-name='R52___LS' - - .. group-tab:: split-lock configuration - - .. code-block:: console - - west debug --core-name='R52__' - -Where: - -- ```` is the zero-based RTU index (0 for ``s32z270dc2_rtu0_r52`` - and 1 for ``s32z270dc2_rtu1_r52``) -- ```` is the zero-based core index relative to the RTU on which to - run the Zephyr application (0, 1, 2 or 3) - -For example, to build the :ref:`hello_world` sample for the board -``s32z270dc2_rtu0_r52`` with split-lock core configuration: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52 - :goals: build - :gen-args: -DCONFIG_DCLS=n - :compact: - -To execute this sample in the second core of RTU0 in split-lock mode: - -.. code-block:: console - - west debug --core-name='R52_0_1' - -If using Lauterbach TRACE32, all runner parameters must be overridden from command -line: - -.. code-block:: console - - west debug --startup-args elfFile= rtu= core= lockstep= - -Where ```` is the path to the Zephyr application ELF in the output -directory. - -References -********** - -.. target-notes:: - -.. _NXP S32Z2 Real-Time Processors website: - https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32z-and-s32e-real-time-processors/s32z2-safe-and-secure-high-performance-real-time-processors:S32Z2 - -.. _pySerial miniterm: - https://pyserial.readthedocs.io/en/latest/tools.html#module-serial.tools.miniterm diff --git a/boards/arm/s32z270dc2_r52/revision.cmake b/boards/arm/s32z270dc2_r52/revision.cmake deleted file mode 100644 index 87399444b71..00000000000 --- a/boards/arm/s32z270dc2_r52/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT LETTER - DEFAULT_REVISION B - VALID_REVISIONS B D -) diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi b/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi deleted file mode 100644 index 884f1d802bb..00000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2022-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "s32z270dc2_r52-pinctrl-common.dtsi" - -&swt0 { - status = "okay"; -}; - -&emdio { - pinctrl-0 = <&emdio_default>; - pinctrl-names = "default"; - status = "okay"; - - phy0: ethernet-phy@7 { - compatible = "ethernet-phy"; - reg = <0x7>; - status = "okay"; - }; -}; - -&enetc_psi0 { - local-mac-address = [00 00 00 01 02 00]; - pinctrl-0 = <ð0_default>; - pinctrl-names = "default"; - clock-frequency = <300000000>; - phy-handle = <&phy0>; - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_default>; - pinctrl-names = "default"; - bus-speed = <125000>; - sample-point = <875>; - bus-speed-data = <1000000>; - sample-point-data = <875>; - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_default>; - pinctrl-names = "default"; - bus-speed = <125000>; - sample-point = <875>; - bus-speed-data = <1000000>; - sample-point-data = <875>; -}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts deleted file mode 100644 index a8650758089..00000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright 2022-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "s32z270dc2_r52.dtsi" - -/ { - model = "NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores"; - compatible = "nxp,s32z270"; - - chosen { - zephyr,sram = &sram0; - zephyr,canbus = &can0; - }; - - aliases { - watchdog0 = &swt0; - }; -}; - -&mru0 { - rx-channels = <1>; - status = "okay"; -}; - -&enetc_psi0 { - mboxes = <&mru0 0>; - mbox-names = "rx"; -}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml deleted file mode 100644 index 891f6b3cce5..00000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -identifier: s32z270dc2_rtu0_r52 -name: NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores -type: mcu -arch: arm -ram: 1024 -toolchain: - - zephyr -supported: - - uart - - gpio - - watchdog - - netif:eth - - can - - spi - - counter -vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.yaml deleted file mode 100644 index 481ce3e63b2..00000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -identifier: s32z270dc2_rtu0_r52@D -name: NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores (rev. D) -type: mcu -arch: arm -ram: 1024 -toolchain: - - zephyr -supported: - - uart - - gpio - - watchdog - - netif:eth - - can - - spi - - counter -vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_defconfig b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_defconfig deleted file mode 100644 index 24074439953..00000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_S32Z270DC2_RTU0_R52=y -CONFIG_SOC_SERIES_S32ZE_R52=y -CONFIG_SOC_S32Z27_R52=y -CONFIG_XIP=n -CONFIG_ISR_STACK_SIZE=512 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 -CONFIG_ARM_MPU=y -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts deleted file mode 100644 index 1f74fe4a3a9..00000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2022-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "s32z270dc2_r52.dtsi" - -/ { - model = "NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores"; - compatible = "nxp,s32z270"; - - chosen { - zephyr,sram = &sram1; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,canbus = &can0; - }; - - aliases { - watchdog0 = &swt0; - }; -}; - -&mru4 { - rx-channels = <1>; - status = "okay"; -}; - -&enetc_psi0 { - mboxes = <&mru4 0>; - mbox-names = "rx"; -}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml deleted file mode 100644 index de48e46091a..00000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -identifier: s32z270dc2_rtu1_r52 -name: NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores -type: mcu -arch: arm -ram: 1024 -toolchain: - - zephyr -supported: - - uart - - gpio - - watchdog - - netif:eth - - can - - spi - - counter -vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.yaml deleted file mode 100644 index 9f0a55547c1..00000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -identifier: s32z270dc2_rtu1_r52@D -name: NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores (rev. D) -type: mcu -arch: arm -ram: 1024 -toolchain: - - zephyr -supported: - - uart - - gpio - - watchdog - - netif:eth - - can - - spi - - counter -vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_defconfig b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_defconfig deleted file mode 100644 index e6c8aa46055..00000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_S32Z270DC2_RTU1_R52=y -CONFIG_SOC_SERIES_S32ZE_R52=y -CONFIG_SOC_S32Z27_R52=y -CONFIG_XIP=n -CONFIG_ISR_STACK_SIZE=512 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 -CONFIG_ARM_MPU=y -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y diff --git a/boards/arm/sam4e_xpro/Kconfig.board b/boards/arm/sam4e_xpro/Kconfig.board deleted file mode 100644 index e0e21446992..00000000000 --- a/boards/arm/sam4e_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Atmel SAM4E Xplained Pro Board selection - -# Copyright (c) 2019 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SAM4E_XPRO - bool "Atmel SAM4E Xplained Pro" - depends on SOC_PART_NUMBER_SAM4E16E diff --git a/boards/arm/sam4e_xpro/Kconfig.defconfig b/boards/arm/sam4e_xpro/Kconfig.defconfig deleted file mode 100644 index e11bd8b37ee..00000000000 --- a/boards/arm/sam4e_xpro/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Atmel SAM4E Xplained Pro Board configuration - -# Copyright (c) 2019 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SAM4E_XPRO - -config BOARD - default "sam4e_xpro" - -endif # BOARD_SAM4E_XPRO diff --git a/boards/arm/sam4e_xpro/doc/index.rst b/boards/arm/sam4e_xpro/doc/index.rst deleted file mode 100644 index dce8fc7a5c5..00000000000 --- a/boards/arm/sam4e_xpro/doc/index.rst +++ /dev/null @@ -1,191 +0,0 @@ -.. _sam4e_xpro: - -SAM4E Xplained Pro -################### - -Overview -******** - -The SAM4E Xplained Pro evaluation kit is a development platform to evaluate the -Atmel SAM4E series microcontrollers. - -.. image:: img/sam4e_xpro.jpg - :align: center - :alt: SAM4E Xplained Pro - -Hardware -******** - -- ATSAM4E16E ARM Cortex-M4F Processor -- 12 MHz crystal oscillator -- internal 32.768 kHz crystal oscillator -- 2 x IS61WV5128BLL 4Mb SRAM -- MT29F2G08ABAEAWP 2Gb NAND -- SD card connector -- CAN-bus (TLE7250GVIOXUMA1 CAN Transceiver) -- Ethernet port (KSZ8081MNXIA phy) -- Micro-AB USB device -- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data - Gateway Interface (DGI) -- One reset and one user pushbutton -- 1 yellow user LEDs - - -Supported Features -================== - -The sam4e_xpro board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/sam4e_xpro/sam4e_xpro_defconfig`. - -Connections and IOs -=================== - -The `SAM4E Xplained Pro User Guide`_ has detailed information about board -connections. Download the `SAM4E Xplained Pro documentation`_ for more detail. - -System Clock -============ - -The SAM4E MCU is configured to use the 12 MHz internal oscillator on the board -with the on-chip PLL to generate an 120 MHz system clock. - -Serial Port -=========== - -The ATSAM4E16E MCU has 2 UARTs and 2 USARTs. One of the UARTs (UART0) is -configured for the console and is available as a Virtual COM Port by EDBG USB -chip. - -Programming and Debugging -************************* - -Flashing the Zephyr project onto SAM4E MCU requires the `OpenOCD tool`_. -By default a factory new SAM4E chip will boot SAM-BA boot loader located in -the ROM, not the flashed image. This is determined by the value of GPNVM1 -(General-Purpose NVM bit 1). The flash procedure will ensure that GPNVM1 is -set to 1 changing the default behavior to boot from Flash. - -If your chip has a security bit GPNVM0 set you will be unable to program flash -memory or connect to it via a debug interface. The only way to clear GPNVM0 -is to perform a chip erase procedure that will erase all GPNVM bits and the full -contents of the SAM4E flash memory: - -- With the board power off, set a jumper on the J304 header. -- Turn the board power on. The jumper can be removed soon after the power is on - (flash erasing procedure is started when the erase line is asserted for at - least 230ms) - -Flashing -======== - -For flash the board Zephyr provides two paths. One uses the default OpenOCD -tool and the second one uses :ref:`atmel_sam_ba_bootloader`. - -Using OpenOCD -------------- - -#. Connect the SAM4E Xplained Pro board to your host computer using the USB - debug port. Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4e_xpro - :goals: build flash - -Using SAM-BA bootloader ------------------------ - -#. Close the ``ERASE`` jumper on the SAM4E Xplained Pro board. Power on the - board for 10s. - -#. Open the ``ERASE`` jumper. - -#. Connect the SAM4E Xplained Pro board to your host computer using the SoC - USB port. Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4e_xpro - :goals: build - - .. code-block:: console - - $ west flash -r bossac - -Visualizing the message ------------------------ - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Press reset button - - You should see "Hello World! sam4e_xpro" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4e_xpro - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _SAM4E Xplained Pro User Guide: - http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42216-SAM4E-Xplained-Pro_User-Guide.pdf - -.. _SAM4E Xplained Pro documentation: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAM4E-Xplained-Pro_Design-Documentation.zip - -.. _OpenOCD tool: - http://openocd.org/ - -.. _SAM-BA: - https://www.microchip.com/developmenttools/ProductDetails/PartNO/SAM-BA%20In-system%20Programmer diff --git a/boards/arm/sam4e_xpro/sam4e_xpro_defconfig b/boards/arm/sam4e_xpro/sam4e_xpro_defconfig deleted file mode 100644 index c5380342d78..00000000000 --- a/boards/arm/sam4e_xpro/sam4e_xpro_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAM4E=y -CONFIG_SOC_PART_NUMBER_SAM4E16E=y -CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK=y -CONFIG_BOARD_SAM4E_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam4l_ek/Kconfig.board b/boards/arm/sam4l_ek/Kconfig.board deleted file mode 100644 index 1c0987a045f..00000000000 --- a/boards/arm/sam4l_ek/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Atmel SAM4L-EK selection - -# Copyright (c) 2020 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SAM4L_EK - bool "Atmel SAM4L-EK" - depends on SOC_PART_NUMBER_SAM4LC4C diff --git a/boards/arm/sam4l_ek/Kconfig.defconfig b/boards/arm/sam4l_ek/Kconfig.defconfig deleted file mode 100644 index 315afa1b312..00000000000 --- a/boards/arm/sam4l_ek/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Atmel SAM4L-EK Board configuration - -# Copyright (c) 2020 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SAM4L_EK - -config BOARD - default "sam4l_ek" - -endif # BOARD_SAM4L_EK diff --git a/boards/arm/sam4l_ek/doc/index.rst b/boards/arm/sam4l_ek/doc/index.rst deleted file mode 100644 index ee5d7120171..00000000000 --- a/boards/arm/sam4l_ek/doc/index.rst +++ /dev/null @@ -1,172 +0,0 @@ -.. _sam4l_ek: - -SAM4L-EK -######## - -Overview -******** - -The SAM4L series embeds picoPower technology for ultra-low power consumption. -Combined power control techniques are used to bring active current consumption -down to 90μA/MHz. The device allows a wide range of configurations giving the -user the ability to balance between the lowest possible power consumption and -the feature set selected for the application. The WAIT and RETENTION modes -provide full logic and RAM retention, associated with fast wake-up capability -(<1.5μs) and a very low consumption of, respectively, 3 μA and 1.5 μA. In -addition, WAIT mode supports SleepWalking features. In BACKUP mode, CPU, -peripherals and RAM are powered off consuming less than 0.9μA with external -interrupt wake-up support. - -The SAM4L-EK is a full featured design to develop for Atmel SAM4L SoC series. -The kit is equipped with a rich set of peripherals that make the ATSAM4L-EK a -perfect evaluation platform. Download the `SAM4L-EK Online User Guide`_ for -more details. - -.. image:: img/atmel-sam4l-ek-callouts.jpg - :align: center - :alt: SAM4L-EK - -Hardware -******** - -- ATSAM4LC4C ARM Cortex-M4 Processor -- 12 MHz crystal oscillator -- 32.768 kHz crystal oscillator -- 1 Micro-AB USB OTG host/device -- 1 AT86RF2xx IEEE 802.15.4 transceiver connector -- 1 RS-485 full duplex interface -- 1 Sensor Xplained board connector -- 1 Audio Jack connector 3.5mm -- 1 Dedicated Board Monitor MCU - - - Power measurement (VDDIN, VDDIO, VDDANA) - - 1 OLED Display (128x64) - - 5 LEDs - - 1 Joystick - - 1 USART - - 1 TWI -- 1 40x4 LCD Segment Display -- 1 user touch button and One user pushbutton -- 1 user LED -- 1 QTouch Slider -- 1 QTouch Button -- 1 TEMT6000 Light Sensor -- 1 AT25DF641A Serial NOR Flash - -Supported Features -================== - -The sam4l_ek board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique 120 bit serial number | -+-----------+------------+-------------------------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | 32-bit True Random Number Generator | -+-----------+------------+-------------------------------------+ -| TWIM | on-chip | i2c master port-interrupt | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/sam4l_ek/sam4l_ek_defconfig`. - -Connections and IOs -=================== - -The `SAM4L-EK Design Documentation`_ has detailed information about board -connections. Download the `SAM4L-EK Design Documentation`_ for more details. - -System Clock -============ - -The SAM4L MCU is configured to use the 12 MHz internal oscillator on the board -with the on-chip PLL to generate an 48 MHz system clock. - -Serial Port -=========== - -The ATSAM4LC4C MCU has 4 USARTs. One of the USARTs (USART2) is connected on -the embedded debug unit and can works as a console. The USART0 is shared -between all others headers and RS-485 port. - -Programming and Debugging -************************* - -The SAM4L-EK board have a Segger Embedded Debugger Unit -`J-Link OB `_. This provides a debug -interface to the SAM4LC4C chip. You can use Ozone or JLink to communicate with -the SAM4LC4C. - -Flashing -======== - -#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section - "J-Link Software and Documentation Pack" and install the "J-Link Software - and Documentation pack for Linux". The application JLinkExe needs to be - accessible from your path. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the SAM4L-EK board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4l_ek - :goals: build flash - - You should see "Hello World! sam4l_ek" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4l_ek - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _SAM4L-EK Online User Guide: - http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42026-ATSAM4L-EK-User-Guide_ApplicationNote_AVR32850.pdf - -.. _SAM4L-EK Design Documentation: - http://ww1.microchip.com/downloads/en/DeviceDoc/doc42027_SAM4L-EK_Design_Documentation.PDF - -.. _JLink Downloads Page: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/sam4l_ek/sam4l_ek_defconfig b/boards/arm/sam4l_ek/sam4l_ek_defconfig deleted file mode 100644 index c5faaad1983..00000000000 --- a/boards/arm/sam4l_ek/sam4l_ek_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAM4L=y -CONFIG_SOC_PART_NUMBER_SAM4LC4C=y -CONFIG_BOARD_SAM4L_EK=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam4s_xplained/Kconfig.board b/boards/arm/sam4s_xplained/Kconfig.board deleted file mode 100644 index 65ec186370b..00000000000 --- a/boards/arm/sam4s_xplained/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Atmel SAM4S Xplained Board selection - -# Copyright (c) 2017 Justin Watson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SAM4S_XPLAINED - bool "Atmel SAM4S Xplained" - depends on SOC_PART_NUMBER_SAM4S16C diff --git a/boards/arm/sam4s_xplained/Kconfig.defconfig b/boards/arm/sam4s_xplained/Kconfig.defconfig deleted file mode 100644 index d201fa44209..00000000000 --- a/boards/arm/sam4s_xplained/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Atmel SAM4S Xplained Board configuration - -# Copyright (c) 2017 Justin Watson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SAM4S_XPLAINED - -config BOARD - default "sam4s_xplained" - -endif # BOARD_SAM4S_XPLAINED diff --git a/boards/arm/sam4s_xplained/doc/index.rst b/boards/arm/sam4s_xplained/doc/index.rst deleted file mode 100644 index 092079cb984..00000000000 --- a/boards/arm/sam4s_xplained/doc/index.rst +++ /dev/null @@ -1,187 +0,0 @@ -.. _sam4s_xplained: - -SAM4S Xplained -################ - -Overview -******** - -The SAM4S Xplained evaluation kit is a development platform to evaluate the -Atmel SAM4S series microcontrollers. - -.. image:: img/sam4s_xplained.jpg - :align: center - :alt: SAM4S Xplained - -Hardware -******** - -- ATSAM4S16C ARM Cortex-M4 Processor -- 12 MHz crystal oscillator -- internal 32.768 kHz crystal oscillator -- IS66WV51216DALL 8 Mb SRAM -- Micro-AB USB device -- Micro-AB USB debug interface supporting SEGGER OB and Virtual COM Port and - Data -- One reset and one user pushbutton -- 2 yellow user LEDs -- IC pads for external flash chip - -Supported Features -================== - -The sam4s_xplained board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| SMC | on-chip | memc (PSRAM) | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/sam4s_xplained/sam4s_xplained_defconfig`. - -Connections and IOs -=================== - -Download the `SAM4S Xplained Design Files`_ for more information. It has -full schematic and gerbers files. - -System Clock -============ - -The SAM4S MCU is configured to use the 12 MHz internal oscillator on the board -with the on-chip PLL to generate an 84 MHz system clock. - -Serial Port -=========== - -The ATSAM4S16C MCU has 2 UARTs and 2 USARTs. One of the UARTs (UART0) is -connected to the Segger J-Link OB chip (the AT91SAM3U4 is programmed to be -Segger J-Link OB). Segger J-Link OB brings the UART out as a virtual COM port. -The section flashing uses the UART from the Segger USB debug connection. - -Programming and Debugging -************************* - -The SAM4S Xplained board comes with Segger `J-Link OB `_. This provides a debug -interface to the SAM4S16C chip. You can use Ozone or JLink to communicate with -the SAM4S16C. - -Flashing -======== - -For flash the board Zephyr provides two paths. One uses the default JLink -tool and the second one uses :ref:`atmel_sam_ba_bootloader`. - -Using JLink -------------- - -#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section - "J-Link Software and Documentation Pack" and install the "J-Link Software - and Documentation pack for Linux". The application JLinkExe needs to be - accessible from your path. - -#. Connect the SAM4S Xplained board to your host computer using the USB debug - port. Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4s_xplained - :goals: build flash - - -Using SAM-BA bootloader ------------------------ - -#. Close the ``J25`` jumper on the SAM4S Xplained board. Power on the board - for 10s. - -#. Open the ``J25`` jumper. - -#. Connect the SAM4S Xplained board to your host computer using the SoC USB - port. Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4s_xplained - :goals: build - - .. code-block:: console - - $ west flash -r bossac - - -Visualizing the message ------------------------ - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Press reset button - - You should see "Hello World! sam4s_xplained" in your terminal. - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4s_xplained - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _SAM4S Xplained Online User Guide: - http://ww1.microchip.com/downloads/en/devicedoc/atmel-42075-sam4s-xplained-pro_user-guide.pdf - -.. _JLink Downloads Page: - https://www.segger.com/downloads/jlink - -.. _SAM4S Xplained Design Files: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAM4S-XPLD__KitsFiles.zip diff --git a/boards/arm/sam4s_xplained/sam4s_xplained_defconfig b/boards/arm/sam4s_xplained/sam4s_xplained_defconfig deleted file mode 100644 index 09f69d3220b..00000000000 --- a/boards/arm/sam4s_xplained/sam4s_xplained_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAM4S=y -CONFIG_SOC_PART_NUMBER_SAM4S16C=y -CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK=y -CONFIG_BOARD_SAM4S_XPLAINED=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_MEMC=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam_e70_xplained/Kconfig.board b/boards/arm/sam_e70_xplained/Kconfig.board deleted file mode 100644 index f7ff0b7c37d..00000000000 --- a/boards/arm/sam_e70_xplained/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Atmel SMART SAM E70 Xplained Board selection - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SAM_E70_XPLAINED - bool "Atmel SMART SAM E70 Xplained Board" - depends on SOC_PART_NUMBER_SAME70Q21 || SOC_PART_NUMBER_SAME70Q21B diff --git a/boards/arm/sam_e70_xplained/Kconfig.defconfig b/boards/arm/sam_e70_xplained/Kconfig.defconfig deleted file mode 100644 index ab33a8333f7..00000000000 --- a/boards/arm/sam_e70_xplained/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# Atmel SMART SAM E70 Xplained Board configuration - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SAM_E70_XPLAINED - -config BOARD - default "sam_e70_xplained" - -if ETH_SAM_GMAC - -# Read MAC address from AT24MAC402 EEPROM - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS - default 0x9A - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE - default 1 - -config ETH_SAM_GMAC_MAC_I2C_EEPROM - default y - select I2C - -endif # ETH_SAM_GMAC - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_SAM_E70_XPLAINED diff --git a/boards/arm/sam_e70_xplained/doc/index.rst b/boards/arm/sam_e70_xplained/doc/index.rst deleted file mode 100644 index c7abfac8cc8..00000000000 --- a/boards/arm/sam_e70_xplained/doc/index.rst +++ /dev/null @@ -1,187 +0,0 @@ -.. _sam_e70_xplained: - -SAM E70(B) Xplained -################### - -Overview -******** - -The SAM E70 Xplained evaluation kit is a development platform to evaluate the -Atmel SAM E70 series microcontrollers. The current version allows to use both -IC variations ATSAME70Q21A(B). - -.. image:: img/sam_e70_xplained.jpg - :align: center - :alt: SAM E70 Xplained - -Hardware -******** - -- ATSAME70Q21A(B) ARM Cortex-M7 Processor -- 12 MHz crystal oscillator -- 32.768 kHz crystal oscillator (not populated) -- AT24MAC402 EEPROM -- IS42S16100E 16 Mb SDRAM -- SD card connector -- Ethernet port -- Micro-AB USB device -- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data - Gateway Interface (DGI) -- JTAG interface connector -- One reset and one user pushbutton -- One green user LED - -Supported Features -================== - -The sam_e70_xplained board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC via AFEC | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | canbus | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig`. - -Connections and IOs -=================== - -The `SAME70-XPLD User Guide`_ has detailed information about board connections. - -System Clock -============ - -The SAM E70 MCU is configured to use the 12 MHz external oscillator on the board -with the on-chip PLL to generate a 300 MHz system clock. - -Serial Port -=========== - -The ATSAME70Q21 MCU has five UARTs and three USARTs. One of the USARTs is -configured for the console and is available as a Virtual COM Port via EDBG USB -chip. - -Programming and Debugging -************************* - -Flashing the Zephyr project onto SAM E70 MCU requires the `OpenOCD tool`_. -Support for Atmel SAM E microcontroller series was added in OpenOCD release -0.10.0, which was added in Zephyr SDK 0.9.2. - -By default a factory new SAM E70 chip will boot SAM-BA boot loader located in -the ROM, not the flashed image. This is determined by the value of GPNVM1 -(General-Purpose NVM bit 1). The flash procedure will ensure that GPNVM1 is -set to 1 changing the default behavior to boot from Flash. - -If your chip has a security bit GPNVM0 set you will be unable to program flash -memory or connect to it via a debug interface. The only way to clear GPNVM0 -is to perform a chip erase procedure that will erase all GPNVM bits and the full -contents of the SAM E70 flash memory: - -- With the board power off, set a jumper on the J200 header. -- Turn the board power on. The jumper can be removed soon after the power is on - (flash erasing procedure is started when the erase line is asserted for at - least 230ms) - -Flashing -======== - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the SAM E70 Xplained board to your host computer using the - USB debug port. Then build and flash the :ref:`hello_world` - application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_e70_xplained - :goals: build flash - - You should see "Hello World! sam_e70_xplained" in your terminal. - -#. To use the SoC variation B IC, you need type "sam_e70b_xplained". - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_e70b_xplained - :goals: build flash - - You should see "Hello World! sam_e70b_xplained" in your terminal. - -You can flash the image using an external debug adapter such as J-Link -or ULINK, connected to the 20-pin JTAG header. Supply the name of the -debug adapter (e.g., ``jlink``) via an OPENOCD_INTERFACE environment -variable. OpenOCD will look for the appropriate interface -configuration in an ``interface/$(OPENOCD_INTERFACE).cfg`` file on its -internal search path. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_e70_xplained - :maybe-skip-config: - :goals: debug - -References -********** - -SAM E70 Product Page: - http://www.atmel.com/products/microcontrollers/arm/sam-e.aspx - -.. _SAME70-XPLD User Guide: - http://www.atmel.com/Images/Atmel-44050-Cortex-M7-Microcontroller-SAM-E70-XPLD-Xplained_User-guide.pdf - -.. _OpenOCD tool: - http://openocd.org/ - -.. _SAM-BA: - http://www.atmel.com/tools/ATMELSAM-BAIN-SYSTEMPROGRAMMER.aspx diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained.dts b/boards/arm/sam_e70_xplained/sam_e70_xplained.dts deleted file mode 100644 index ee002c846fa..00000000000 --- a/boards/arm/sam_e70_xplained/sam_e70_xplained.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2017 Piotr Mienkowski - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2020-2023 Gerson Fernando Budke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "sam_e70_xplained-common.dtsi" - -/ { - model = "Atmel SAM E70 Xplained board"; - compatible = "atmel,sam_e70_xplained", "atmel,same70q21", "atmel,same70"; -}; - -&tc0 { - status = "okay"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc0_qdec_default>; - pinctrl-names = "default"; -}; - -&tc1 { - status = "disabled"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc1_qdec_default>; - pinctrl-names = "default"; -}; - -&tc2 { - status = "disabled"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc2_qdec_default>; - pinctrl-names = "default"; -}; - -&tc3 { - status = "disabled"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc3_qdec_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained.yaml b/boards/arm/sam_e70_xplained/sam_e70_xplained.yaml deleted file mode 100644 index 714795a2104..00000000000 --- a/boards/arm/sam_e70_xplained/sam_e70_xplained.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: sam_e70_xplained -name: SAM E70 Xplained -type: mcu -arch: arm -ram: 384 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - dma - - netif:eth - - adc - - i2s - - gpio - - spi - - watchdog - - usb_device - - pwm - - can - - hwinfo -vendor: atmel diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig b/boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig deleted file mode 100644 index 30cb50e4512..00000000000 --- a/boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAME70=y -CONFIG_SOC_PART_NUMBER_SAME70Q21=y -CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK=y -CONFIG_SOC_ATMEL_SAME70_PLLA_MULA=24 -CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA=1 -CONFIG_BOARD_SAM_E70_XPLAINED=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_CACHE_MANAGEMENT=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_USART_SAM=y diff --git a/boards/arm/sam_e70_xplained/sam_e70b_xplained.dts b/boards/arm/sam_e70_xplained/sam_e70b_xplained.dts deleted file mode 100644 index a26b519d4af..00000000000 --- a/boards/arm/sam_e70_xplained/sam_e70b_xplained.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2020 Stephanos Ioannidis - * Copyright (c) 2020 Gerson Fernando Budke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "sam_e70_xplained-common.dtsi" - -/ { - model = "Atmel SAM E70B Xplained board"; - compatible = "atmel,sam_e70b_xplained", "atmel,same70q21b", "atmel,same70b"; -}; diff --git a/boards/arm/sam_e70_xplained/sam_e70b_xplained.yaml b/boards/arm/sam_e70_xplained/sam_e70b_xplained.yaml deleted file mode 100644 index 8cd515dca40..00000000000 --- a/boards/arm/sam_e70_xplained/sam_e70b_xplained.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: sam_e70b_xplained -name: SAM E70 Xplained (Revision B) -type: mcu -arch: arm -ram: 384 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - netif:eth - - adc - - dac - - gpio - - spi - - watchdog - - usb_device - - pwm - - can - - hwinfo -vendor: atmel diff --git a/boards/arm/sam_e70_xplained/sam_e70b_xplained_defconfig b/boards/arm/sam_e70_xplained/sam_e70b_xplained_defconfig deleted file mode 100644 index 5aba40c4400..00000000000 --- a/boards/arm/sam_e70_xplained/sam_e70b_xplained_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAME70=y -CONFIG_SOC_PART_NUMBER_SAME70Q21B=y -CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK=y -CONFIG_SOC_ATMEL_SAME70_PLLA_MULA=24 -CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA=1 -CONFIG_BOARD_SAM_E70_XPLAINED=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_CACHE_MANAGEMENT=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_USART_SAM=y diff --git a/boards/arm/sam_v71_xult/Kconfig.board b/boards/arm/sam_v71_xult/Kconfig.board deleted file mode 100644 index 9ca0469360e..00000000000 --- a/boards/arm/sam_v71_xult/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Atmel SMART SAM V71 Xplained Board selection - -# Copyright (c) 2019 Gerson Fernando Budke -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SAM_V71_XULT - bool "Atmel SMART SAM V71 Xplained Ultra Board" - depends on SOC_PART_NUMBER_SAMV71Q21 || SOC_PART_NUMBER_SAMV71Q21B diff --git a/boards/arm/sam_v71_xult/Kconfig.defconfig b/boards/arm/sam_v71_xult/Kconfig.defconfig deleted file mode 100644 index dca80a82289..00000000000 --- a/boards/arm/sam_v71_xult/Kconfig.defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# Atmel SMART SAM V71 Xplained Board configuration - -# Copyright (c) 2019 Gerson Fernando Budke -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SAM_V71_XULT - -config BOARD - default "sam_v71_xult" - -if ETH_SAM_GMAC - -# Read MAC address from AT24MAC402 EEPROM - -config ETH_SAM_GMAC_MAC_I2C_EEPROM - default y - select I2C - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS - default 0x9A - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE - default 1 - -endif # ETH_SAM_GMAC - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_SAM_V71_XULT diff --git a/boards/arm/sam_v71_xult/doc/index.rst b/boards/arm/sam_v71_xult/doc/index.rst deleted file mode 100644 index a61fe887d6a..00000000000 --- a/boards/arm/sam_v71_xult/doc/index.rst +++ /dev/null @@ -1,190 +0,0 @@ -.. _sam_v71_xplained_ultra: - -SAM V71(B) Xplained Ultra -######################### - -Overview -******** - -The SAM V71 Xplained Ultra evaluation kit is a development platform to -evaluate the Atmel SAM V71 series microcontrollers. The current version -allows to use both IC variations ATSAMV71Q21A(B). - -.. image:: img/sam_v71_xult.jpg - :align: center - :alt: SAM V71 Xplained Ultra - -Hardware -******** - -- ATSAMV71Q21A(B) ARM Cortex-M7 Processor -- 12 MHz crystal oscillator -- 32.768 kHz crystal oscillator -- Supercap backup -- AT24MAC402 EEPROM -- IS42S16100E 16 Mb SDRAM -- S25FL116K 16 Mb QSPI -- WM8904 low power stereo audio codec -- ATA6561 CAN Transceiver -- SD card connector with SDIO support -- Camera interface connector -- MediaLB connector -- Ethernet port -- Micro-AB USB device -- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data - Gateway Interface (DGI) -- JTAG interface connector -- One reset and two user pushbuttons -- Two yellow user LEDs - -Supported Features -================== - -The sam_v71_xplained_ultra board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC via AFEC | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CAN FD | on-chip | can | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/sam_v71_xult/sam_v71_xult_defconfig`. - -Connections and IOs -=================== - -The `SAMV71-XULT User Guide`_ has detailed information about board -connections. - -System Clock -============ - -The SAM V71 MCU is configured to use the 12 MHz external oscillator on the -board with the on-chip PLL to generate a 300 MHz system clock. - -Serial Port -=========== - -The ATSAMV71Q21 MCU has five UARTs and three USARTs. USART1 is configured -for the console and is available as a Virtual COM Port via EDBG USB chip. - -Programming and Debugging -************************* - -Flashing the Zephyr project onto SAM V71 MCU requires the `OpenOCD tool`_. -By default a factory new SAM V71 chip will boot the `SAM-BA`_ boot loader -located in the ROM, not the flashed image. This is determined by the value -of GPNVM1 (General-Purpose NVM bit 1). The flash procedure will ensure that -GPNVM1 is set to 1 changing the default behavior to boot from Flash. - -If your chip has a security bit GPNVM0 set you will be unable to program flash -memory or connect to it via a debug interface. The only way to clear GPNVM0 -is to perform a chip erase procedure that will erase all GPNVM bits and the -full contents of the SAM V71 flash memory: - -- With the board power off, set a jumper on the J200 header. -- Turn the board power on. The jumper can be removed soon after the power is - on (flash erasing procedure is started when the erase line is asserted for - at least 230ms) - -Flashing -======== - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the SAM V71 Xplained Ultra board to your host computer using the - USB debug port. Then build and flash the :ref:`hello_world` - application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_v71_xult - :goals: build flash - - You should see "Hello World! sam_v71_xult" in your terminal. - -#. To use the SoC variation B IC, you need type "sam_v71b_xult". - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_v71b_xult - :goals: build flash - - You should see "Hello World! sam_v71b_xult" in your terminal. - -You can flash the image using an external debug adapter such as J-Link -or ULINK, connected to the 20-pin JTAG header. Supply the name of the -debug adapter (e.g., ``jlink``) via an OPENOCD_INTERFACE environment -variable. OpenOCD will look for the appropriate interface -configuration in an ``interface/$(OPENOCD_INTERFACE).cfg`` file on its -internal search path. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_v71_xult - :maybe-skip-config: - :goals: debug - -References -********** - -SAM V71 Product Page: - https://www.microchip.com/design-centers/32-bit/sam-32-bit-mcus/sam-v-mcus - -.. _SAMV71-XULT User Guide: - http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42408-SAMV71-Xplained-Ultra_User-Guide.pdf - -.. _OpenOCD tool: - http://openocd.org/ - -.. _SAM-BA: - https://www.microchip.com/developmenttools/ProductDetails/PartNO/SAM-BA%20In-system%20Programmer diff --git a/boards/arm/sam_v71_xult/sam_v71_xult.dts b/boards/arm/sam_v71_xult/sam_v71_xult.dts deleted file mode 100644 index 634da676e96..00000000000 --- a/boards/arm/sam_v71_xult/sam_v71_xult.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2017 Piotr Mienkowski - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2019-2020 Gerson Fernando Budke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "sam_v71_xult-common.dtsi" - -/ { - model = "Atmel SAM V71 Xplained Ultra board"; - compatible = "atmel,sam_v71_xult", "atmel,samv71q21", "atmel,samv71"; -}; diff --git a/boards/arm/sam_v71_xult/sam_v71_xult.yaml b/boards/arm/sam_v71_xult/sam_v71_xult.yaml deleted file mode 100644 index 01055202950..00000000000 --- a/boards/arm/sam_v71_xult/sam_v71_xult.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: sam_v71_xult -name: SAM V71 Xplained Ultra -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - dma - - netif:eth - - adc - - arduino_gpio - - arduino_i2c - - arduino_spi - - gpio - - spi - - watchdog - - usb_device - - pwm - - xpro_gpio - - xpro_i2c - - xpro_serial - - xpro_spi - - can - - hwinfo -vendor: atmel diff --git a/boards/arm/sam_v71_xult/sam_v71_xult_defconfig b/boards/arm/sam_v71_xult/sam_v71_xult_defconfig deleted file mode 100644 index 3c82428d40e..00000000000 --- a/boards/arm/sam_v71_xult/sam_v71_xult_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMV71=y -CONFIG_SOC_PART_NUMBER_SAMV71Q21=y -CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK=y -CONFIG_SOC_ATMEL_SAMV71_PLLA_MULA=24 -CONFIG_SOC_ATMEL_SAMV71_PLLA_DIVA=1 -CONFIG_BOARD_SAM_V71_XULT=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_CACHE_MANAGEMENT=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_USART_SAM=y diff --git a/boards/arm/sam_v71_xult/sam_v71b_xult.dts b/boards/arm/sam_v71_xult/sam_v71b_xult.dts deleted file mode 100644 index 8f16beb951f..00000000000 --- a/boards/arm/sam_v71_xult/sam_v71b_xult.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2020 Stephanos Ioannidis - * Copyright (c) 2020 Gerson Fernando Budke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "sam_v71_xult-common.dtsi" - -/ { - model = "Atmel SAM V71B Xplained Ultra board"; - compatible = "atmel,sam_v71b_xult", "atmel,samv71q21b", "atmel,samv71b"; -}; diff --git a/boards/arm/sam_v71_xult/sam_v71b_xult.yaml b/boards/arm/sam_v71_xult/sam_v71b_xult.yaml deleted file mode 100644 index 9dbb670075f..00000000000 --- a/boards/arm/sam_v71_xult/sam_v71b_xult.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: sam_v71b_xult -name: SAM V71 Xplained Ultra (Revision B) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - netif:eth - - adc - - arduino_gpio - - arduino_i2c - - arduino_spi - - dac - - gpio - - spi - - watchdog - - usb_device - - pwm - - xpro_gpio - - xpro_i2c - - xpro_serial - - xpro_spi - - can - - hwinfo -vendor: atmel diff --git a/boards/arm/sam_v71_xult/sam_v71b_xult_defconfig b/boards/arm/sam_v71_xult/sam_v71b_xult_defconfig deleted file mode 100644 index bf9eea03a5d..00000000000 --- a/boards/arm/sam_v71_xult/sam_v71b_xult_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMV71=y -CONFIG_SOC_PART_NUMBER_SAMV71Q21B=y -CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK=y -CONFIG_SOC_ATMEL_SAMV71_PLLA_MULA=24 -CONFIG_SOC_ATMEL_SAMV71_PLLA_DIVA=1 -CONFIG_BOARD_SAM_V71_XULT=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_CACHE_MANAGEMENT=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_USART_SAM=y diff --git a/boards/arm/scobc_module1/Kconfig.board b/boards/arm/scobc_module1/Kconfig.board deleted file mode 100644 index 4a74754fb18..00000000000 --- a/boards/arm/scobc_module1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Space Cubics OBC module 1 configuration - -# Copyright (c) 2021 Space Cubics, LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SCOBC_MODULE1 - bool "Space Cubics OBC Module 1" - depends on SOC_SERIES_ARM_DESIGNSTART diff --git a/boards/arm/scobc_module1/Kconfig.defconfig b/boards/arm/scobc_module1/Kconfig.defconfig deleted file mode 100644 index e80eb2226c8..00000000000 --- a/boards/arm/scobc_module1/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Space Cubics OBC module 1 - -# Copyright (c) 2021 Space Cubics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SCOBC_MODULE1 - -config BOARD - default "scobc_module1" - -config CPU_CORTEX_M_HAS_SYSTICK - default y - -config CPU_HAS_ARM_MPU - default y - -config NUM_IRQS - default 7 - -endif # BOARD_SCOBC_MODULE1 diff --git a/boards/arm/scobc_module1/board.cmake b/boards/arm/scobc_module1/board.cmake deleted file mode 100644 index 50979050e38..00000000000 --- a/boards/arm/scobc_module1/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_SCOBC_MODULE1) - board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd-ftdi.cfg") - - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -endif() diff --git a/boards/arm/scobc_module1/scobc_module1_defconfig b/boards/arm/scobc_module1/scobc_module1_defconfig deleted file mode 100644 index ecadcfc07bd..00000000000 --- a/boards/arm/scobc_module1/scobc_module1_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ARM_DESIGNSTART=y -CONFIG_SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3=y -CONFIG_BOARD_SCOBC_MODULE1=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 -CONFIG_ARM_MPU=n - -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_XIP=n -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0x0 diff --git a/boards/arm/seeeduino_xiao/Kconfig.board b/boards/arm/seeeduino_xiao/Kconfig.board deleted file mode 100644 index fb5a3d971b5..00000000000 --- a/boards/arm/seeeduino_xiao/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Seeeduino XIAO board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SEEEDUINO_XIAO - bool "Seeeduino XIAO" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/seeeduino_xiao/Kconfig.defconfig b/boards/arm/seeeduino_xiao/Kconfig.defconfig deleted file mode 100644 index fb8f07b2e9d..00000000000 --- a/boards/arm/seeeduino_xiao/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Seeedunio XIAO board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "seeeduino_xiao" - depends on BOARD_SEEEDUINO_XIAO diff --git a/boards/arm/seeeduino_xiao/doc/index.rst b/boards/arm/seeeduino_xiao/doc/index.rst deleted file mode 100644 index 22693fed2ab..00000000000 --- a/boards/arm/seeeduino_xiao/doc/index.rst +++ /dev/null @@ -1,176 +0,0 @@ -.. _seeeduino_xiao: - -Seeeduino XIAO -############## - -Overview -******** - -The Seeeduino XIAO is a tiny (20 mm x 17.5 mm) ARM development -board with onboard LEDs, USB port, and range of I/O broken out -onto 14 pins. - -.. image:: img/seeeduino_xiao.jpg - :align: center - :alt: Seeeduino XIAO - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 256 KiB flash memory and 32 KiB of RAM -- Three user LEDs -- Native USB port - -Supported Features -================== - -The seeeduino_xiao board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| DMA | on-chip | Direct memory access | -+-----------+------------+------------------------------------------+ -| DAC | on-chip | Digital to analogue converter | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Hardware info | -+-----------+------------+------------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| I2C | on-chip | Inter-Integrated Circuit | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/seeeduino_xiao/seeeduino_xiao_defconfig`. - -Connections and IOs -=================== - -The `Seeeduino XIAO wiki`_ has detailed information about -the board including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD21 MCU is configured to use the 32 kHz external crystal -with the on-chip PLL generating the 48 MHz system clock. The internal -APB and GCLK unit are set up in the same way as the upstream Arduino -libraries. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the XIAO, SERCOM0 can be put -into SPI mode and used to connect to devices over pin 9 (MISO), pin 10 -(MOSI), and pin 8 (SCK). - -I2C Port -======== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the XIAO, SERCOM2 is available on -pin 4 (SDA) and pin 5 (SCL). - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the XIAO, SERCOM4 is -the Zephyr console and is available on pins 7 (RX) and 6 (TX). - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -DAC -=== - -The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On -the XIAO, the DAC is available on pin 0. - -Programming and Debugging -************************* - -The XIAO ships the BOSSA compatible UF2 bootloader. The bootloader can be -entered by shorting the RST and GND pads twice. - -Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader -will be entered automatically when you run :code:`west flash`. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: seeeduino_xiao - :goals: build - :compact: - -#. Connect the XIAO to your host computer using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyUSB0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Short the RST and GND pads twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: seeeduino_xiao - :goals: flash - :compact: - - You should see "Hello World! seeeduino_xiao" in your terminal. - -References -********** - -.. target-notes:: - -.. _Seeeduino XIAO wiki: - https://wiki.seeedstudio.com/Seeeduino-XIAO/ - -.. _pinouts: - https://wiki.seeedstudio.com/Seeeduino-XIAO/#hardware-overview - -.. _schematic: - https://wiki.seeedstudio.com/Seeeduino-XIAO/#resourses diff --git a/boards/arm/segger_trb_stm32f407/Kconfig.board b/boards/arm/segger_trb_stm32f407/Kconfig.board deleted file mode 100644 index 2c1251e0bd6..00000000000 --- a/boards/arm/segger_trb_stm32f407/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SEGGER-TRB-STM32F407 board configuration - -# Copyright (c) 2020, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SEGGER_TRB_STM32F407 - bool "SEGGER STM32F407 Trace Reference Board" - depends on SOC_STM32F407XE diff --git a/boards/arm/segger_trb_stm32f407/Kconfig.defconfig b/boards/arm/segger_trb_stm32f407/Kconfig.defconfig deleted file mode 100644 index a519fbf853f..00000000000 --- a/boards/arm/segger_trb_stm32f407/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SEGGER-TRB-STM32F407 board configuration - -# Copyright (c) 2020, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SEGGER_TRB_STM32F407 - -config BOARD - default "segger_trb_stm32f407" - -endif # BOARD_SEGGER_TRB_STM32F407 diff --git a/boards/arm/sensortile_box/Kconfig.board b/boards/arm/sensortile_box/Kconfig.board deleted file mode 100644 index 5341a09871a..00000000000 --- a/boards/arm/sensortile_box/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SensorTile.box board configuration - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SENSORTILE_BOX - bool "SensorTile.box Development Board" - depends on SOC_STM32L4R9XX diff --git a/boards/arm/sensortile_box/Kconfig.defconfig b/boards/arm/sensortile_box/Kconfig.defconfig deleted file mode 100644 index 1f3d19b39ca..00000000000 --- a/boards/arm/sensortile_box/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# SensorTile.box board configuration - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SENSORTILE_BOX - -config BOARD - default "sensortile_box" - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -config BT_BLUENRG_ACI - default y -# Disable Flow control -config BT_HCI_ACL_FLOW_CONTROL - default n -config BT_HCI_VS_EXT - default n - -endif # BT - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_SENSORTILE_BOX diff --git a/boards/arm/sensortile_box/board.cmake b/boards/arm/sensortile_box/board.cmake deleted file mode 100644 index 2e222be114c..00000000000 --- a/boards/arm/sensortile_box/board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") - -include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) diff --git a/boards/arm/sensortile_box_pro/Kconfig.board b/boards/arm/sensortile_box_pro/Kconfig.board deleted file mode 100644 index 14429705999..00000000000 --- a/boards/arm/sensortile_box_pro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SENSORTILE_BOX_PRO board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SENSORTILE_BOX_PRO - bool "SENSORTILE_BOX_PRO Board" - depends on SOC_STM32U585XX diff --git a/boards/arm/sensortile_box_pro/Kconfig.defconfig b/boards/arm/sensortile_box_pro/Kconfig.defconfig deleted file mode 100644 index 48b55275be3..00000000000 --- a/boards/arm/sensortile_box_pro/Kconfig.defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# SENSORTILE_BOX_PRO board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SENSORTILE_BOX_PRO - -config BOARD - default "sensortile_box_pro" - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -config BT_BLUENRG_ACI - default y - -# Disable Flow control -config BT_HCI_ACL_FLOW_CONTROL - default n - -endif # BT - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -endif # LOG - -endif # BOARD_SENSORTILE_BOX_PRO diff --git a/boards/arm/sensortile_box_pro/doc/index.rst b/boards/arm/sensortile_box_pro/doc/index.rst deleted file mode 100644 index bba5a4cb288..00000000000 --- a/boards/arm/sensortile_box_pro/doc/index.rst +++ /dev/null @@ -1,386 +0,0 @@ -.. _sensortile_box_pro_board: - -ST SensorTile.box PRO -##################### - -Overview -******** - -The STEVAL-MKBOXPRO (SensorTile.box PRO) features an ARM Cortex-M33 based STM32U585AI MCU -and is a ready-to-use box kit for wireless IoT and wearable sensor platforms to help using -and developing apps based on remote motion and environmental sensor data. - -The SensorTile.box PRO board fits into a small plastic box with a long-life rechargeable -battery, and communicates with a standard smartphone through its Bluetooth interface, -providing data coming from the sensors. - -.. image:: img/sensortile_box_pro.jpg - :align: center - :alt: SensorTile.box PRO - -More information about the board can be found at the `SensorTile.box PRO website`_. - -Supported Features -****************** - -The SensorTile.box PRO provides motion, environmental, and audio -sensor data through either the BLE or USB protocols to a host application running -on a smartphone/PC to implement applications such as: - -- Pedometer optimized for belt positioning -- Baby crying detection with Cloud AI learning -- Barometer / environmental monitoring -- Vehicle / goods tracking -- Vibration monitoring -- Compass and inclinometer -- Sensor data logger - -(see `Motion and environmental sensors`_ section for the complete lists of available -sensors on board) - -Hardware -******** - -The STM32U585xx devices are an ultra-low-power microcontrollers family (STM32U5 -Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. -They operate at a frequency of up to 160 MHz. - -- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 1.5 DMPIS/MHz (Drystone 2.1) - - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) - -- Security and cryptography - - - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals - - Flexible life cycle scheme with RDP (readout protection) and password protected debug - - Root of trust thanks to unique boot entry and secure hide protection area (HDP) - - Secure Firmware Installation thanks to embedded Root Secure Services - - Secure data storage with hardware unique key (HUK) - - Secure Firmware Update support with TF-M - - 2 AES coprocessors including one with DPA resistance - - Public key accelerator, DPA resistant - - On-the-fly decryption of Octo-SPI external memories - - HASH hardware accelerator - - Active tampers - - True Random Number Generator NIST SP800-90B compliant - - 96-bit unique ID - - 512-byte One-Time Programmable for user data - - Active tampers - -- Clock management: - - - 4 to 50 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - - Internal 48 MHz with clock recovery - -- Power management - - - Embedded regulator (LDO) - - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling - -- RTC with HW calendar and calibration -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- Up to 17 timers and 2 watchdogs - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5 x 16-bit general purpose - - 4x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- ART accelerator - - - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and - external memories: up to 160 MHz, MPU, 240 DMIPS and DSP - - 4-Kbyte data cache for external memories - -- Memories - - - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles - - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON - - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories - - 2 Octo-SPI memory interfaces - -- Rich analog peripherals (independent supply) - - - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling - - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode - - 12-bit DAC, low-power sample and hold - - 2 operational amplifiers with built-in PGA - - 2 ultra-low-power comparators - -- Up to 22 communication interfaces - - - USB Type-C / USB power delivery controller - - USB OTG 2.0 full-speed controller - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) - - 1x FDCAN - - 2x SDMMC interface - - 16- and 4-channel DMA controllers, functional in Stop mode - - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with - sound-activity detection - -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| -- True Random Number Generator (RNG) - -- Graphic features - - - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation - - 1 digital camera interface - -- Mathematical co-processor - - - CORDIC for trigonometric functions acceleration - - FMAC (filter mathematical accelerator) - - -More information about STM32U585AI can be found here: - -- `STM32U585 on www.st.com`_ -- `STM32U585 reference manual`_ - -Motion and environmental sensors -================================ - - - **LSM6DSV16X** 6-axis inertial measurement unit - (`lsm6dsv16x datasheet`_) - - **LIS2MDL** 3-axis magnetometer - (`lis2mdl datasheet`_) - - **LPS22DF** Altimeter / pressure sensor - (`lps22df datasheet`_) - - **LIS2DU12** 3-axis accelerometer - (`lis2du12 datasheet`_) - - **HTS221** Humidity sensor - (`hts221 datasheet`_) - - **STTS22H** Digital temperature sensor - (`stts22hh datasheet`_) - - **MP23db01HP** Microphone / audio sensor - (`mp23db01hp datasheet`_) - -Connections and IOs -=================== - -- 4x user LEDs - - - **led0** (Green) - - **led1** (Red - shared with BLE) - - **led2** (Yellow) - - **led3** (Blue) - - -- 4x buttons/switch - - - **User BT1** button, available to user application - - **User BT2** / **boot0** button, available to user application - but useful to let the SensorTile.box PRO enter DFU mode - if found pressed after h/w reset (see **rst** button and - `Programming and Debugging`_ section) - - **rst** button, used to reset the board (not available on case) - - **power** switch, used to Power on/off the board - -System Clock -============ - -SensorTile.box PRO System Clock could be driven by internal or external -oscillator, as well as main PLL clock. By default, the System clock is -driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator. -The system clock can be boosted to 120MHz. -The internal AHB/APB1/APB2 AMBA buses are all clocked at 80MHz. - -Serial Port -=========== - -The SensorTile.box PRO has 4 U(S)ARTs. The UART4 is connected to JTAG/SWD connector -and may be used as console. - -USB interface -============= - -SensorTile.box PRO can be connected as a USB device to a PC host through its USB-C connector. -The final application may use it to declare SensorTile.box PRO device as belonging to a -certain standard or vendor class, e.g. a CDC, a mass storage or a composite device with both -functions. - -Console -======= - -There are two possible options for Zephyr console output: - -- through UART4 which is available on SWD connector (JP2). In this case a JTAG adapter - can be used to connect SensorTile.box PRO and have both SWD and console lines available. - - To enable console and shell over UART - - - switch the console lines from cdc_acm to uart4 - (:file:`boards/arm/sensortile_box_pro/sensortile_box_pro.dts`) - - - comment out the USB configuration macros - (:file:`boards/arm/sensortile_box_pro/sensortile_box_pro_defconfig`) - -.. code-block:: dts - :caption: boards/arm/sensortile_box_pro/sensortile_box_pro.dts - - / { - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - //zephyr,console = &cdc_acm_uart0; - //zephyr,shell-uart = &cdc_acm_uart0; - }; - }; - -.. code-block:: Kconfig - :caption: boards/arm/sensortile_box_pro/sensortile_box_pro_defconfig - - # Comment out following USB config lines when - # switching console to UART - #CONFIG_USB_DEVICE_STACK=y - #CONFIG_USB_DEVICE_VID=0x0483 - #CONFIG_USB_DEVICE_PID=0x1235 - #CONFIG_USB_DEVICE_PRODUCT="Zephyr CDC SensorTile.box PRO" - #CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - #CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n - - -- through USB as USB CDC/ACM class. This is the default case present in the board dts file. - -.. code-block:: dts - :caption: boards/arm/sensortile_box_pro/sensortile_box_pro.dts - - / { - chosen { - zephyr,console = &cdc_acm_uart0; - }; - }; - - &zephyr_udc0 { - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; - }; - }; - - - -Console default settings are 115200 8N1. - -Programming and Debugging -************************* - -There are two alternative methods of flashing ST Sensortile.box Pro board: - -1. Using DFU software tools - - This method requires to enter STM32U585 ROM bootloader DFU mode - by powering up (or reset) the board while keeping the BOOT0 button pressed. - No additional hardware is required except a USB-C cable. This method is fully - supported by :ref:`flash-debug-host-tools`. - You can read more about how to enable and use the ROM bootloader by checking - the application note `AN2606`_ (STM32U585xx section). - -2. Using SWD hardware tools - - This method requires to connect additional hardware, like a ST-LINK/V3 - embedded debug tool, to the board SWD connector. - -DFU flashing -============ - -Install dfu-util ----------------- - -It is recommended to use at least v0.9 of dfu-util. The package available in -Debian and Ubuntu can be quite old, so you might have to build dfu-util from source. -Information about how to get the source code and how to build it can be found -at the `DFU-UTIL website`_ - -Flash an Application to SensorTile.box PRO ------------------------------------------- - -While pressing the BOOT0 button, connect the USB-C cable to the USB OTG SensorTile.box PRO -port and to your computer. The board should be forced to enter DFU mode. - -Check that the board is indeed in DFU mode: - -.. code-block:: console - - $ sudo dfu-util -l - dfu-util 0.9 - - Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. - Copyright 2010-2019 Tormod Volden and Stefan Schmidt - This program is Free Software and has ABSOLUTELY NO WARRANTY - Please report bugs to http://sourceforge.net/p/dfu-util/tickets/ - - Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=2, name="@OTP Memory /0x1FFF7000/01*0001Ke", serial="204A325D574D" - Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=1, name="@Option Bytes /0x1FF00000/01*040 e/0x1FF01000/01*040 e", serial="204A325D574D" - Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=0, name="@Internal Flash /0x08000000/512*0004Kg", serial="204A325D574D" - -You should see following confirmation on your Linux host: - -.. code-block:: console - - $ dmesg - usb 2-2: new full-speed USB device number 74 using xhci_hcd - usb 2-2: New USB device found, idVendor=0483, idProduct=df11 - usb 2-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 - usb 2-2: Product: STM32 BOOTLOADER - usb 2-2: Manufacturer: STMicroelectronics - usb 2-2: SerialNumber: 204A325D574D - -You can build and flash the provided sample application -(:ref:`sensortile_box_pro_sample_sensors`) that reads sensors data and outputs -values on the console. - -References -********** - -.. target-notes:: - -.. _SensorTile.box PRO website: - https://www.st.com/en/evaluation-tools/steval-mkboxpro.html - -.. _STM32U585 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html - -.. _STM32U585 reference manual: - https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _lsm6dsv16x datasheet: - https://www.st.com/en/mems-and-sensors/lsm6dsv16x.html - -.. _lis2mdl datasheet: - https://www.st.com/en/mems-and-sensors/lis2mdl.html - -.. _lps22df datasheet: - https://www.st.com/en/mems-and-sensors/lps22df.html - -.. _lis2du12 datasheet: - https://www.st.com/en/mems-and-sensors/lis2du12.html - -.. _hts221 datasheet: - https://www.st.com/en/mems-and-sensors/hts221.html - -.. _stts22hh datasheet: - https://www.st.com/en/mems-and-sensors/stts22h.html - -.. _mp23db01hp datasheet: - https://www.st.com/en/mems-and-sensors/mp23db01hp.html - -.. _AN2606: - http://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf - -.. _DFU-UTIL website: - http://dfu-util.sourceforge.net/ diff --git a/boards/arm/serpente/Kconfig.board b/boards/arm/serpente/Kconfig.board deleted file mode 100644 index 5c2cb6dc83e..00000000000 --- a/boards/arm/serpente/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Serpente board configuration -# Copyright (c) 2020 Alexander Falb -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SERPENTE - bool "Serpente" - depends on SOC_PART_NUMBER_SAMD21E18A diff --git a/boards/arm/serpente/Kconfig.defconfig b/boards/arm/serpente/Kconfig.defconfig deleted file mode 100644 index 911f7021ff7..00000000000 --- a/boards/arm/serpente/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Serpente board configuration -# Copyright (c) 2020 Alexander Falb -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "serpente" - depends on BOARD_SERPENTE diff --git a/boards/arm/serpente/doc/index.rst b/boards/arm/serpente/doc/index.rst deleted file mode 100644 index c446103c712..00000000000 --- a/boards/arm/serpente/doc/index.rst +++ /dev/null @@ -1,125 +0,0 @@ -.. _serpente: - -Arturo182 Serpente -################## - -Overview -******** - -The Serpente is a very small low-cost development and prototyping -board equipped with 4MiB flash storage, a PWM enabled RGB led and 6 I/O pins. -The board comes with 3 different USB connector options: USB Type-C plug, -USB Type-C socket and USB Type-A plug. - -.. image:: img/serpente.jpg - :align: center - :alt: Serpente Boards - -Hardware -******** - -- ATSAMD21E18A ARM Cortex-M0+ processor at 48 MHz -- 256 KiB flash memory and 32 KiB of RAM -- Extra 4MiB SPI flash memory -- RGB User LED -- Reset button -- Native USB port - -Supported Features -================== - -The Serpente board configuration supports the -following hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/serpente/serpente_defconfig`. - -Connections and IOs -=================== - -The `Serpente documentation`_ has detailed information about the board -including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD21 MCU is configured to use the 8MHz internal oscillator -with the on-chip PLL generating the 48 MHz system clock. - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which prints "Hello World!" -to the host PC. - -Programming and Debugging -========================= - -The Serpente ships the BOSSA compatible UF2 bootloader. The bootloader -can be entered by quickly tapping the reset button twice. - -Flashing -======== - -#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: serpente - :goals: build - :compact: - -#. Connect the Serpente to your host computer using USB - - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: serpente - :goals: flash - :compact: - - You should see the User LED blink. - -References -********** - -.. target-notes:: - -.. _Serpente documentation: - https://www.solder.party/docs/serpente/r2/ - -.. _pinouts: - https://www.solder.party/docs/serpente/r2/pinout/ - -.. _schematic: - https://www.solder.party/docs/serpente/r2/downloads/ diff --git a/boards/arm/serpente/pre_dt_board.cmake b/boards/arm/serpente/pre_dt_board.cmake deleted file mode 100644 index 9be9a0b9771..00000000000 --- a/boards/arm/serpente/pre_dt_board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - /soc/pinmux@41004400 & /soc/gpio@41004400 -# - /soc/pinmux@41004480 & /soc/gpio@41004480 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/serpente/serpente_defconfig b/boards/arm/serpente/serpente_defconfig deleted file mode 100644 index b670a7b0476..00000000000 --- a/boards/arm/serpente/serpente_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21E18A=y -CONFIG_BOARD_SERPENTE=y -CONFIG_SOC_ATMEL_SAMD_OSC8M=y -CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y diff --git a/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.board b/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.board deleted file mode 100644 index c27c19c2812..00000000000 --- a/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Pete Johanson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SPARKFUN_PRO_MICRO_RP2040 - bool "Sparkfun Pro-Micro RP2040 Board" - depends on SOC_RP2040 diff --git a/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.defconfig b/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.defconfig deleted file mode 100644 index eb2066e98a9..00000000000 --- a/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2021 Pete Johanson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SPARKFUN_PRO_MICRO_RP2040 - -config BOARD - default "sparkfun_pro_micro_rp2040" - -config RP2_FLASH_W25Q080 - default y - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 125 - -endif #I2C_DW - -config USB_SELF_POWERED - default n - -endif # BOARD_SPARKFUN_PRO_MICRO_RP2040 diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig b/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig deleted file mode 100644 index 78e7bbd4530..00000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Circuit Dojo nRF9160 Feather configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.board b/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.board deleted file mode 100644 index 504107a7b2c..00000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.board +++ /dev/null @@ -1,23 +0,0 @@ -# Sparkfun nRF9160 Thing Plus configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_SPARKFUN_THING_PLUS_NRF9160 - bool "Sparkfun nRF9160 Thing Plus" - # The GPIO driver is required by this board's initialization code - # (board.c), so it is forced here to be enabled always, not only - # enabled by default (in defconfig). - select GPIO - -config BOARD_SPARKFUN_THING_PLUS_NRF9160_NS - bool "Sparkfun nRF9160 Thing Plus non-secure" - # The GPIO driver is required by this board's initialization code - # (board.c), so it is forced here to be enabled always, not only - # enabled by default (in defconfig). - select GPIO - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.defconfig b/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.defconfig deleted file mode 100644 index 8ae5b832d89..00000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Circuit Dojo nRF9160 Feather configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SPARKFUN_THING_PLUS_NRF9160 || BOARD_SPARKFUN_THING_PLUS_NRF9160_NS - -config BOARD - default "sparkfun_thing_plus_nrf9160" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_SPARKFUN_THING_PLUS_NRF9160 && TRUSTED_EXECUTION_SECURE - -if BOARD_SPARKFUN_THING_PLUS_NRF9160_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_SPARKFUN_THING_PLUS_NRF9160_NS - -endif # BOARD_SPARKFUN_THING_PLUS_NRF9160 || BOARD_SPARKFUN_THING_PLUS_NRF9160_NS diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/doc/index.rst b/boards/arm/sparkfun_thing_plus_nrf9160/doc/index.rst deleted file mode 100644 index 8ee7a38cb33..00000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/doc/index.rst +++ /dev/null @@ -1,153 +0,0 @@ -.. _sparkfun_thing_plus_nrf9160: - -nRF9160 Thing Plus -################## - -.. figure:: img/sparkfun_thing_plus_nrf9160.jpg - :align: center - :alt: Sparkfun nRF9160 Thing Plus - - nRF9160 Thing Plus (Credit: Sparkfun) - -Overview -******** - -The nRF9160 Thing Plus designed by Circuit Dojo is a single-board development -for bringing your LTE-M and NB-IoT applications to life. The sparkfun_thing_plus_nrf9160 -board configuration leverages the pre-existing support for the Nordic Semiconductor -nRF9160. Supported nRF9160 peripherals include: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -More information about the board can be found at the -`nRF9160 Thing Plus Documentation`_. - - -Hardware -******** - -Connections and IOs -=================== - -The nRF9160 Thing Plus has everything you know and love about -the Feather platform. Here are some of the highlights: - -LED ---- - -* D7 (blue) = P0.03 - -Push buttons and Switches -------------------------- - -* MODE = P0.12 -* RESET - -USB ---- - -Contains a USB/UART connection for both debugging and loading new -code using a UART Enabled MCUBoot. - -Standard Battery Connection ----------------------------- - -The nRF9160 Thing Plus has a 2 pin battery connector on board. Lithium Polymer batteries > -300mA required. - -Nano SIM Holder ---------------- - -The nRF9160 Thing Plus has a built-in nano SIM (4FF) holder located -on the bottom side. - - -Programming and Debugging -************************* - -sparkfun_thing_plus_nrf9160 can be used with most programmers like: - -* J-Link (the nRF53-DK is recommended) -* CMSIS-DAP based programmers - -Check out `Getting Started`_ for more info. - -Building an application -======================= - -In most cases you'll want to use the ``ns`` target with any of the Zephyr -or Nordic based examples. - -Some of the examples do not use secure mode, so they do not required the ``ns`` suffix. -A great example of this is the `hello_world` below. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ screen /dev/ 115200 - -Replace :code:`` with the port where the nRF9160 Thing Plus -can be found. In most cases (On Linux/Mac) it will be: :code:`/dev/tty.SLAB_USBtoUART`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sparkfun_thing_plus_nrf9160 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons on the nRF9160 Thing Plus -****************************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_common.dtsi`. - -References -********** - -.. target-notes:: - -**Side note** This page was based on the documentation for the nRF9160 DK. Thanks to Nordic for -developing a great platform! - -.. _nRF9160 Thing Plus Documentation: https://docs.jaredwolff.com/nrf9160-introduction.html -.. _Getting Started: https://docs.jaredwolff.com/nrf9160-getting-started.html diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_defconfig b/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_defconfig deleted file mode 100644 index 8748d5dd83c..00000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_SPARKFUN_THING_PLUS_NRF9160=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# Hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_REGULATOR=y diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns_defconfig b/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns_defconfig deleted file mode 100644 index 92818ef157b..00000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_SPARKFUN_THING_PLUS_NRF9160_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# Hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_REGULATOR=y diff --git a/boards/arm/steval_fcu001v1/Kconfig.board b/boards/arm/steval_fcu001v1/Kconfig.board deleted file mode 100644 index dc0b41e59e4..00000000000 --- a/boards/arm/steval_fcu001v1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Flight Controller Unit board configuration - -# Copyright (c) 2019 Linumiz -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STEVAL_FCU001V1 - bool "STM32 Flight Controller Unit" - depends on SOC_STM32F401XC diff --git a/boards/arm/steval_fcu001v1/Kconfig.defconfig b/boards/arm/steval_fcu001v1/Kconfig.defconfig deleted file mode 100644 index 6c4e715a676..00000000000 --- a/boards/arm/steval_fcu001v1/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Flight Controller Unit board configuration - -# Copyright (c) 2019 Linumiz -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STEVAL_FCU001V1 - -config BOARD - default "steval_fcu001v1" - -endif # BOARD_STEVAL_FCU001V1 diff --git a/boards/arm/steval_fcu001v1/doc/index.rst b/boards/arm/steval_fcu001v1/doc/index.rst deleted file mode 100644 index 823631dd120..00000000000 --- a/boards/arm/steval_fcu001v1/doc/index.rst +++ /dev/null @@ -1,158 +0,0 @@ -.. _steval_fcu001v1: - -ST STM32 Flight Controller Unit -############################### - -Overview -******** - -The STEVAL-FCU001V1 is a Cortex M4 MCU-based flight controller unit for toy quad-copter drones. - -.. figure:: img/steval_fcu001v1.jpg - :align: center - :alt: STM32 Flight Controller Unit - -Hardware -******** - -STM32 Flight Controller Unit provides the following hardware components: - -- STM32F401CC in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg|-M4 MCU with FPU -- 84MHz max MCU frequency -- VDD from 1.7 V to 3.6 V -- 256 KB FLASH -- 64 KB SRAM -- General Purpose Timers -- Watchdog Timers (2) -- On board sensors: - - - 3D Accelerometer and 3D Gyroscope: LSM6DSL - - 3D Magnetometer: LIS2MDL - - MEMS Pressure sensor: LPS22HD - -- 2 User LEDS -- USART/UART (1) -- I2C (1) -- Bluetooth LE over SPI - -More information about the STM32 Flight Controller Unit -can be found in these documents: - -- `STEVAL_FCU001V1 website`_ -- `STM32F401 reference manual`_ -- `STM32F401CC on www.st.com`_ - -Supported Features -================== - -The Zephyr steval_fcu001v1 board configuration supports the following hardware features: - -+-----------+------------+------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+------------------------------------+ - - -The default configuration can be found in the defconfig file: -``boards/arm/steval_fcu001v1/steval_fcu001v1_defconfig`` - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- I2C2 SCL/SDA : PB10/PB3 -- PWM_2_CH1 : PA0 -- LD1 : PB5 -- LD2 : PB4 - -System Clock -============ - -The steval_fcu001v1 system clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the system clock is driven by the PLL clock at 84MHz, -driven by a 16MHz high-speed external clock. - -Serial Port -=========== - -The steval_fcu001v1 board has one UART. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - -I2C -=== - -The steval_fcu001v1 board has one I2C. The default I2C mapping for Zephyr is: - -- I2C2_SCL : PB10 -- I2C2_SDA : PB3 - -Programming and Debugging -************************* - -Applications for the ``steval_fcu001v1`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Flashing Zephyr onto the steval_fcu001v1 board requires an external ST-LINK/V2-1 programmer. -The programmer is attached to the P8 programming header with ARM-JTAG-20-10-Plug-in Adapter. - -Flashing an application to STEVAL_FCU001V1 ------------------------------------------- - -Connect the FT232-to-USB port to host system, and RX, TX, Gnd pins to -the P7 header of the steval_fcu001v1 board. Then run a serial host -program to connect with your steval_fcu001v1 via the FT232 board: - -.. code-block:: console - - $ minicom -D /dev/ttyUSB0 - -Now build and flash an application. Here is an example for :ref:`hello_world` - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: steval_fcu001v1 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! steval_fcu001v1 - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: steval_fcu001v1 - :maybe-skip-config: - :goals: debug - -.. _STEVAL_FCU001V1 website: - https://www.st.com/en/evaluation-tools/steval-fcu001v1.html - -.. _STM32F401CC on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32f401cc.html - -.. _STM32F401 reference manual: - https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/stm3210c_eval/Kconfig.board b/boards/arm/stm3210c_eval/Kconfig.board deleted file mode 100644 index 8e55fc27f86..00000000000 --- a/boards/arm/stm3210c_eval/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM3210C-EVAL board configuration - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM3210C_EVAL - bool "STM3210C-EVAL Evaluation Board" - depends on SOC_STM32F107XC diff --git a/boards/arm/stm3210c_eval/Kconfig.defconfig b/boards/arm/stm3210c_eval/Kconfig.defconfig deleted file mode 100644 index 2f60b584274..00000000000 --- a/boards/arm/stm3210c_eval/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM3210C-EVAL board configuration - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM3210C_EVAL - -config BOARD - default "stm3210c_eval" - -endif # BOARD_STM3210C_EVAL diff --git a/boards/arm/stm3210c_eval/doc/index.rst b/boards/arm/stm3210c_eval/doc/index.rst deleted file mode 100644 index 9d9278e1614..00000000000 --- a/boards/arm/stm3210c_eval/doc/index.rst +++ /dev/null @@ -1,165 +0,0 @@ -.. _stm3210c_eval_board: - -ST STM3210C Evaluation -###################### - -Overview -******** -The STM3210C-EVAL evaluation board is a complete development platform for STMicroelectronic's -ARM Cortex-M3 core-based STM32F107VCT microcontroller. - -The range of hardware features on the board help you to evaluate all peripherals -(USB-OTG FS, ethernet, motor control, CAN, microSD CardTM, smartcard, USART, -audio DAC, MEMS, EEPROM and more) and develop your own applications. - -Extension headers make it easy to connect a daughterboard or wrapping board for your specific -application. - -.. image:: img/stm3210c_eval.jpg - :align: center - :alt: STM3210C-EVAL - -More information about the board can be found at the `STM3210C-EVAL website`_. - -Hardware -******** - -STM3210C-EVAL provides the following hardware components: - -- Three 5 V power supply options: - - Power jack - - USB connector - - daughterboard -- Boot from user Flash, system memory or SRAM. -- I2S audio DAC, stereo audio jack. -- 2 GByte (or more) microSD CardTM. -- Both type A and B smartcard support. -- I2C compatible serial interface 64 Kbit EEPROM, MEMS and I/O expander. -- RS-232 communication. -- IrDA transceiver. -- USB-OTG full speed, USB microAB connector. -- IEEE-802.3-2002 compliant ethernet connector. -- Two channels of CAN2.0A/B compliant connection. -- Inductor motor control connector. -- JTAG and trace debug support. -- 3.2" 240x320 TFT color LCD with touch screen. -- Joystick with 4-direction control and selector. -- Reset, Wakeup, Tamper and User button. -- 4 color LEDs. -- RTC with backup battery. -- MCU consumption measurement circuit. -- Extension connector for daughterboard or wrapping board. - -More information about STM32F107VCT can be found here: - - `STM32F107VCT reference manual`_ - - -Supported Features -================== - -The Zephyr stm3210c_eval board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file -:zephyr_file:`boards/arm/stm3210c_eval/stm3210c_eval_defconfig`. - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/stm3210c_eval_connectors.jpg - :align: center - :alt: STM3210C_EVAL connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- USER_PB : PB9 -- LED2 : PD13 - -Programming and Debugging -************************* - -Flashing -======== - -STM3210C-EVAL board includes an ST-LINK/V2-1 embedded debug tool interface. -At power-on, the board is in firmware-upgrade mode (also called DFU for -"Device Firmware Upgrade"), allowing the firmware to be updated through the USB. -This interface is supported by the openocd version included in Zephyr SDK. - -Applications for the ``stm3210c_eval`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing an application to STM3210C-EVAL ----------------------------------------- - -Connect the STM3210C-EVAL to your host computer using the USB port, then build -and flash an application in the usual way. - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm3210c_eval - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can run a serial host program to connect with your STM3210C-EVAL board. For -example, on Linux: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm3210c_eval - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM3210C-EVAL website: - https://www.st.com/en/evaluation-tools/stm3210c-eval.html - -.. _STM32F107VCT reference manual: - https://www.st.com/resource/en/reference_manual/CD00171190.pdf diff --git a/boards/arm/stm3210c_eval/stm3210c_eval_defconfig b/boards/arm/stm3210c_eval/stm3210c_eval_defconfig deleted file mode 100644 index c282e80fd58..00000000000 --- a/boards/arm/stm3210c_eval/stm3210c_eval_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F1X=y - -# Platform Configuration -CONFIG_SOC_STM32F107XC=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# RCC Controller -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32373c_eval/Kconfig.board b/boards/arm/stm32373c_eval/Kconfig.board deleted file mode 100644 index 5348461a9d3..00000000000 --- a/boards/arm/stm32373c_eval/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32373C-EVAL evaluation board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32373C_EVAL - bool "STM32373C_EVAL Evaluation Board" - depends on SOC_STM32F373XC diff --git a/boards/arm/stm32373c_eval/Kconfig.defconfig b/boards/arm/stm32373c_eval/Kconfig.defconfig deleted file mode 100644 index aa615e68bdb..00000000000 --- a/boards/arm/stm32373c_eval/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32373C-EVAL evaluation board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32373C_EVAL - -config BOARD - default "stm32373c_eval" - -endif # BOARD_STM32373C_EVAL diff --git a/boards/arm/stm32373c_eval/doc/index.rst b/boards/arm/stm32373c_eval/doc/index.rst deleted file mode 100644 index 9f6ed1d750b..00000000000 --- a/boards/arm/stm32373c_eval/doc/index.rst +++ /dev/null @@ -1,159 +0,0 @@ -.. _stm32373c_eval_board: - -ST STM32373C Evaluation -####################### - -Overview -******** -The STM32373C-EVAL evaluation board is designed as a complete demonstration and development platform for STMicroelectronics ARM Cortex-M4 core-based STM32F373VCT6 microcontroller. - -The full range of hardware features on the board can help the user evaluate all peripherals (USB FS, USART, audio DAC, microphone ADC, dot-matrix LCD, IrDA, LDR, MicroSD card, HDMI CEC, ECG, pressure sensor, CAN, IR transmitter and receiver, EEPROM, touch slider, temperature sensor, etc.) and develop their own applications. - -Extension headers make it possible to easily connect a daughter board or wrapping board for a specific application. - -.. image:: img/stm32373c_eval.jpg - :align: center - :alt: STM32373C-EVAL - -More information about the board can be found at the `STM32373C-EVAL website`_. - -Hardware -******** - -STM32373C-EVAL provides the following hardware components: - -- STM32F373VCT6 microcontroller -- Four 5 V power supply options: - - Power jack - - ST-LINK/V2 USB connector - - User USB connector - - Daughter board -- Audio jack connected to I2 S DAC -- Microphone connected to ADC through an amplifier -- 2-GByte (or more) MicroSD card on SPI -- Three components on I2 C bus: temperature sensor, EEPROM and dual interface RF EEPROM -- RS-232 communication configurable for communication of Flash loader -- IrDA transceiver -- 240x320 TFT color LCD connected to SPI interface -- Joystick with 4-direction control and selector -- Reset, Wakeup or Tamper, and Key buttons -- 4 color user LEDs -- 2 LEDs for MCU power range indicator -- ECG, pressure sensor and PT100 temperature sensor connected to the 16-bit Sigma Delta ADC of STM32F373VCT6 -- Extension connectors for daughter board or wrapping board -- MCU voltage: 3.3 V or adjustable 2.0 V - 3.6 V -- USB FS connector -- Touch slider -- RTC with backup battery -- CAN 2.0 A/B compliant connection -- Light dependent resistor (LDR) -- Two HDMI connectors with DDC and CEC -- IR transmitter and receiver -- Two ADC & DAC input and output signal connectors and one Sigma Delta ADC input signal connector -- Potentiometer -- JTAG/SWD and ETM trace debug support -- Embedded ST-LINK/V2 - -More information about STM32F373VCT6 can be found here: - - `STM32F373VCT6 reference manual`_ - - -Supported Features -================== - -The Zephyr stm32373c_eval board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file -:zephyr_file:`boards/arm/stm32373c_eval/stm32373c_eval_defconfig` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/stm32373c_eval_connectors.jpg - :align: center - :alt: STM32373C_EVAL connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- USER_PB : PA2 -- LED2 : PC1 - -Programming and Debugging -************************* - -Applications for the ``stm32373c_eval`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32373C-EVAL board includes an ST-LINK/V2-1 embedded debug tool interface. -At power-on, the board is in firmware-upgrade mode (also called DFU for -"Device Firmware Upgrade"), allowing the firmware to be updated through the USB. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32373C-EVAL ------------------------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32373c_eval - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32373c_eval - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32373C-EVAL website: - https://www.st.com/en/evaluation-tools/stm32373c-eval.html - -.. _STM32F373VCT6 reference manual: - https://www.st.com/resource/en/reference_manual/dm00041563.pdf diff --git a/boards/arm/stm32_min_dev/Kconfig.board b/boards/arm/stm32_min_dev/Kconfig.board deleted file mode 100644 index 3b648714ddb..00000000000 --- a/boards/arm/stm32_min_dev/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# STM32 Minimum Development Board Configuration - -# Copyright (c) 2017, embedjournal.com -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32_MIN_DEV_BLUE - bool "STM32 Minimum Development Board (Blue)" - depends on SOC_STM32F103X8 - -config BOARD_STM32_MIN_DEV_BLACK - bool "STM32 Minimum Development Board (Black)" - depends on SOC_STM32F103X8 diff --git a/boards/arm/stm32_min_dev/Kconfig.defconfig b/boards/arm/stm32_min_dev/Kconfig.defconfig deleted file mode 100644 index 6e38ec4db12..00000000000 --- a/boards/arm/stm32_min_dev/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# STM32 Minimum Development Board Configuration - -# Copyright (c) 2017, embedjournal.com -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32_MIN_DEV_BLUE || BOARD_STM32_MIN_DEV_BLACK - -config BOARD - default "stm32_min_dev_blue" if BOARD_STM32_MIN_DEV_BLUE - default "stm32_min_dev_black" if BOARD_STM32_MIN_DEV_BLACK - -endif # BOARD_STM32_MIN_DEV_BLUE || BOARD_STM32_MIN_DEV_BLACK diff --git a/boards/arm/stm32_min_dev/doc/index.rst b/boards/arm/stm32_min_dev/doc/index.rst deleted file mode 100644 index 6d83f0f7ec7..00000000000 --- a/boards/arm/stm32_min_dev/doc/index.rst +++ /dev/null @@ -1,186 +0,0 @@ -.. _stm32_min_dev: - -STM32 Minimum Development Board -############################### - -Overview -******** - -The STM32 Minimum Development Board, is a popular and inexpensive -breadboard-friendly breakout board for the `STM32F103x8`_ CPU. There -are two variants of the board: - -- Blue Pill Board -- Black Pill Board - -Zephyr applications can use the stm32_min_dev_blue or stm32_min_dev_black board -configuration to use these boards. - -.. figure:: img/stm32_min_dev.jpg - :align: center - :alt: STM32 Minimum Development Board - - STM32 Minimum Development Board - -As the name suggests, these boards have the bare minimum components required to -power on the CPU. For practical use, you'll need to add additional components -and circuits using a breadboard, for example. - -Pin Mapping -=========== - -This port is a starting point for your own customizations and not a complete -port for a specific board. Most of the GPIOs on the STM32 SoC has been exposed -in the external header with silk screen labels that match the SoC's pin names. - -Each board vendor has their own variations in pin mapping on their boards' -external connectors and placement of components. Many vendors use port PC13/PB12 -for connecting an LED, so only this device is supported by our Zephyr port. -Additional device support is left for the user to implement. - -More information on hooking up peripherals and lengthy how to articles can be -found at `EmbedJournal`_. - -The pinout diagram of STM32 Minimum Development Blue Pill board can be seen -below. The Black Pill's one is similar: - -.. figure:: img/stm32_min_dev_pinout_blue.jpg - :align: center - :alt: Pinout for STM32 Minimum Development Blue Pill Board - - Pinout for STM32 Minimum Development Blue Pill Board - - -STLinkV2 connection: -==================== - -The board can be flashed by using STLinkV2 with the following connections. - -+--------+---------------+ -| Pin | STLINKv2 | -+========+===============+ -| G | GND | -+--------+---------------+ -| CLK | Clock | -+--------+---------------+ -| IO | SW IO | -+--------+---------------+ -| V3 | VCC | -+--------+---------------+ - -Boot Configuration -================== - -The boot configuration for this board is configured through jumpers on B0 (Boot 0) -and B1 (Boot 1). The pins B0 and B1 are present in between logic 0 and 1 lines. The -silk screen on the PCB reads BX- or BX+ to indicate 0 and 1 logic lines for B0 and B1 -respectively. - -+--------+--------+-------------------+---------------------------------------------+ -| Boot 1 | Boot 0 | Boot Mode | Aliasing | -+========+========+===================+=============================================+ -| X | 0 | Main Flash Memory | Main flash memory is selected as boot space | -+--------+--------+-------------------+---------------------------------------------+ -| 0 | 1 | System Memory | System memory is selected as boot space | -+--------+--------+-------------------+---------------------------------------------+ -| 1 | 1 | Embedded SRAM | Embedded SRAM is selected as boot space | -+--------+--------+-------------------+---------------------------------------------+ - - -Supported Features -================== - -The stm32_min_dev board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| USB | on-chip | USB device | -+-----------+------------+----------------------+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX: PA9/PA10 -- UART_2 TX/RX: PA2/PA3 -- UART_3 TX/RX: PB10/PB11 -- I2C_1 SCL/SDA : PB6/PB7 -- I2C_2 SCL/SDA : PB10/PB11 -- PWM_1_CH1: PA8 -- SPI_1 NSS_OE/SCK/MISO/MOSI: PA4/PA5/PA6/PA7 -- SPI_2 NSS_OE/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 -- USB_DC DM/DP: PA11/PA12 -- ADC_1: PA0 - -System Clock ------------- - -The on-board 8Mhz crystal is used to produce a 72Mhz system clock with PLL. - -Serial Port ------------ - -STM32 Minimum Development Board has 3 U(S)ARTs. The Zephyr console output is -assigned to UART_1. Default settings are 115200 8N1. - -On-Board LEDs -------------- - -The board has one on-board LED that is connected to PB12/PC13 on the black/blue -variants respectively. - -Programming and Debugging -************************* - -Applications for the ``stm32_min_dev_(blue|black)`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32_min_dev_blue - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32_min_dev_blue - :maybe-skip-config: - :goals: debug - -.. _STM32F103x8: - https://www.st.com/resource/en/datasheet/stm32f103c8.pdf -.. _EmbedJournal: - https://embedjournal.com/tag/stm32-min-dev/ diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_black.dts b/boards/arm/stm32_min_dev/stm32_min_dev_black.dts deleted file mode 100644 index 80c283d24d9..00000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_black.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2019, embedjournal.com - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include "stm32_min_dev.dtsi" - -/ { - model = "STM32 Minimum Development Board (Black)"; - compatible = "stm32_min_dev_black", "st,stm32f103c8"; - - leds { - led: led { - gpios = <&gpiob 12 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_black.yaml b/boards/arm/stm32_min_dev/stm32_min_dev_black.yaml deleted file mode 100644 index 28739cf2b63..00000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_black.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: stm32_min_dev_black -name: STM32 Minimum Development Board (Black) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 20 -supported: - - i2c - - pwm - - spi - - adc - - gpio -vendor: st diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig b/boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig deleted file mode 100644 index 53876bb7d4b..00000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# STM32 Minimum Development Board Configuration -# -# Copyright (c) 2019, embedjournal.com -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103X8=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# enable clock control -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_blue.dts b/boards/arm/stm32_min_dev/stm32_min_dev_blue.dts deleted file mode 100644 index 8d0f3419b86..00000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_blue.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2017, embedjournal.com - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include "stm32_min_dev.dtsi" - -/ { - model = "STM32 Minimum Development Board (Blue)"; - compatible = "stm32_min_dev_blue", "st,stm32f103c8"; - - leds { - led: led { - gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_blue.yaml b/boards/arm/stm32_min_dev/stm32_min_dev_blue.yaml deleted file mode 100644 index ed907a960ce..00000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_blue.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: stm32_min_dev_blue -name: STM32 Minimum Development Board (Blue) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 20 -supported: - - i2c - - pwm - - spi - - adc -vendor: st diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig b/boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig deleted file mode 100644 index efc78388025..00000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103X8=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# enable clock control -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32f030_demo/Kconfig.board b/boards/arm/stm32f030_demo/Kconfig.board deleted file mode 100644 index 3a34ac75962..00000000000 --- a/boards/arm/stm32f030_demo/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 Antony Pavlov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F030_DEMO - bool "STM32F030 DEMO Board" - depends on SOC_STM32F030X4 diff --git a/boards/arm/stm32f030_demo/Kconfig.defconfig b/boards/arm/stm32f030_demo/Kconfig.defconfig deleted file mode 100644 index 86e0233adad..00000000000 --- a/boards/arm/stm32f030_demo/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019 Antony Pavlov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F030_DEMO - -config BOARD - default "stm32f030_demo" - -endif # BOARD_STM32F030_DEMO diff --git a/boards/arm/stm32f030_demo/doc/index.rst b/boards/arm/stm32f030_demo/doc/index.rst deleted file mode 100644 index a1f3ecd68e2..00000000000 --- a/boards/arm/stm32f030_demo/doc/index.rst +++ /dev/null @@ -1,123 +0,0 @@ -.. _stm32f030_demo: - -STM32F030 DEMO BOARD -#################### - -This board has the bare minimum components required to power on -the STM32F030F4P6 MCU. Most of the GPIOs on the STM32 SoC have -been exposed in the external headers with silk screen labels -that match the SoC's pin names. - -For practical use, you'll need to add additional components -and circuits using a breadboard, for example. - -.. image:: img/stm32f030_demo.jpg - :align: center - :alt: STM32F030 DEMO BOARD - -More information about the board can be found at the `stm32-base.org website`_. - -More information about STM32F030F4P6 can be found here: - -- `STM32F030 reference manual`_ -- `STM32F030 data sheet`_ - -Hardware -******** - -- STM32F030F4P6 ARM Cortex-M0 processor, frequency up to 48 MHz -- 16 KiB of flash memory and 4 KiB of RAM -- 8 MHz quartz crystal -- 1 user LED -- One reset button -- 2-way jumper (BOOT0) -- Serial (1x4 male dupont (2.54mm)) -- SWD (1x4 male dupont (2.54mm)) -- USB port (power only) - -Supported Features -================== - -The Zephyr stm32f030_demo board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f030_demo/stm32f030_demo_defconfig`` - -Pin Mapping -=========== - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- LED : PA4 - -Programming and Debugging -************************* - -Applications for the ``stm32f030_demo`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -The board can be flashed by using ST-LINKV2 in-circuit debugger and programmer. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to STM32F030 DEMO BOARD ------------------------------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f030_demo - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f030_demo - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _stm32-base.org website: - https://stm32-base.org/boards/STM32F030F4P6-STM32F030-DEMO-BOARD-V1.1 - -.. _STM32F030 reference manual: - https://www.st.com/resource/en/reference_manual/dm00091010.pdf - -.. _STM32F030 data sheet: - https://www.st.com/resource/en/datasheet/stm32f030f4.pdf diff --git a/boards/arm/stm32f072_eval/Kconfig.board b/boards/arm/stm32f072_eval/Kconfig.board deleted file mode 100644 index 9db08b5f96a..00000000000 --- a/boards/arm/stm32f072_eval/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F072-EVAL board configuration - -# Copyright (c) 2017 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F072_EVAL - bool "STM32F072-EVAL Development Board" - depends on SOC_STM32F072XB diff --git a/boards/arm/stm32f072_eval/Kconfig.defconfig b/boards/arm/stm32f072_eval/Kconfig.defconfig deleted file mode 100644 index fa23a88cf1a..00000000000 --- a/boards/arm/stm32f072_eval/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F072-EVAL board configuration - -# Copyright (c) 2017 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F072_EVAL - -config BOARD - default "stm32f072_eval" - -endif # BOARD_STM32F072_EVAL diff --git a/boards/arm/stm32f072_eval/doc/index.rst b/boards/arm/stm32f072_eval/doc/index.rst deleted file mode 100644 index 49b6577935c..00000000000 --- a/boards/arm/stm32f072_eval/doc/index.rst +++ /dev/null @@ -1,185 +0,0 @@ -.. _stm32f072_eval_board: - -ST STM32F072 Evaluation -####################### - -Overview -******** - -The STM32F072-EVAL Discovery kit features an ARM Cortex-M0 based STM32F072VBT6 MCU -with a wide range of connectivity support and configurations. -Here are some highlights of the STM32F072-EVAL board: - -- Four 5 V power supply options: power jack, ST-LINK/V2 USB connector, user USB connector, or daughter board -- Stereo audio jack, which supports a headset with microphone connected to DAC and ADC of STM32F072VBT6. -- 2G Byte (or more) SPI interface MicroSD card -- I2C compatible serial interface temperature sensor -- RF E2PROM -- RS232 and RS485 communication -- IrDA transceiver -- IR LED and IR receiver -- SWD debug support, ST-LINK/V2 embedded -- 240x320 TFT color LCD connected to SPI interface of STM32F072VBT6 -- Joystick with 4-direction control and selector -- Reset and tamper buttons -- Four color user LEDs and two LEDs as MCU low power alarm -- Extension connector for daughter board or wrapping board -- MCU voltage choice: fixed 3.3 V or adjustable from 1.65 V to 3.6 V -- USB full-speed connector -- Touch sensing buttons -- RTC with backup battery -- CAN2.0A/B compliant connector -- Light Dependent Resistor (LDR) -- Potentiometer -- Two HDMI connectors with DDC and CEC -- Smart Card slot -- Motor control connector - - -.. image:: img/stm32f072_eval.jpg - :align: center - :alt: STM32F072-EVAL - -Hardware -******** - -STM32F072-EVAL Discovery kit provides the following hardware components: - -- STM32F072VBT6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg| -M0 CPU -- 48 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 128 KB Flash -- 16 KB SRAM with HW parity -- GPIO with external interrupt capability -- one 12-bit ADC with 16 channels -- one 12-bit D/A converters with 2 channels -- RTC -- Advanced-control Timer -- General Purpose Timers (8) -- Watchdog Timers (2) -- USART (4) -- I2C (2) -- SPI (2) -- CAN -- USB 2.0 OTG FS with on-chip PHY -- CRC calculation unit -- DMA Controller -- HDMI CEC Controller -- 24 capacitive sensing channels for touchkey, linear, and rotary touch sensors -- Up to 87 fast I/Os: 68 I/Os with 5V tolerant capability and 19 with independent supply - -More information about STM32F072VB can be found here: - - `STM32F072VB on www.st.com`_ - - `STM32F072 reference manual`_ - -Supported Features -================== - -The Zephyr stm32f072_eval board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f072_eval/stm32f072_eval_defconfig`` - - -Pin Mapping -=========== - -STM32F072-EVAL Discovery kit has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to STM32F072-EVAL board User Manual. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- TAMPER_PB : PC13 -- JOYSTICK_RIGHT_PB : PE3 -- JOYSTICK_LEFT_PB : PF2 -- JOYSTICK_UP_PB : PF9 -- JOYSTICK_DOWN_PB : PF10 -- JOYSTICK_SEL_PB : PA0 -- LD1 : PD8 -- LD2 : PD9 -- LD3 : PD10 -- LD4 : PD11 - -System Clock -============ - -STM32F072-EVAL System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 48MHz, -driven by an 8MHz high speed internal clock. - -Serial Port -=========== - -STM32F072-EVAL Discovery kit has up to 4 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f072_eval`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F072-EVAL Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32F072-EVAL -------------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f072_eval - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f072_eval - :maybe-skip-config: - :goals: debug - - -.. _STM32F072VB on www.st.com: - https://www.st.com/en/microcontrollers/stm32f072vb.html - -.. _STM32F072 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936.pdf diff --git a/boards/arm/stm32f072_eval/stm32f072_eval_defconfig b/boards/arm/stm32f072_eval/stm32f072_eval_defconfig deleted file mode 100644 index b5a9b9a3768..00000000000 --- a/boards/arm/stm32f072_eval/stm32f072_eval_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F072XB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32f072b_disco/Kconfig.board b/boards/arm/stm32f072b_disco/Kconfig.board deleted file mode 100644 index 26be5a346e8..00000000000 --- a/boards/arm/stm32f072b_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F072B-DISCO board configuration - -# Copyright (c) 2017 Clage GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F072B_DISCO - bool "STM32F072B-DISCO Development Board" - depends on SOC_STM32F072XB diff --git a/boards/arm/stm32f072b_disco/Kconfig.defconfig b/boards/arm/stm32f072b_disco/Kconfig.defconfig deleted file mode 100644 index 75472bbad3d..00000000000 --- a/boards/arm/stm32f072b_disco/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32F072B-DISCO board configuration - -# Copyright (c) 2017 Clage GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F072B_DISCO - -config BOARD - default "stm32f072b_disco" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_STM32F072B_DISCO diff --git a/boards/arm/stm32f072b_disco/doc/index.rst b/boards/arm/stm32f072b_disco/doc/index.rst deleted file mode 100644 index a2c51e51cdd..00000000000 --- a/boards/arm/stm32f072b_disco/doc/index.rst +++ /dev/null @@ -1,219 +0,0 @@ -.. _stm32f072b_disco_board: - -ST STM32F072B Discovery -####################### - -Overview -******** - -The STM32F072B-DISCO Discovery kit features an ARM Cortex-M0 based STM32F072RB -MCU with everything required for beginners and experienced users to get -started quickly. Here are some highlights of the STM32F072B-DISCO board: - -- STM32 microcontroller in LQFP64 package -- Extension header for LQFP64 I/Os for a quick connection to the prototyping - board and easy probing -- On-board ST-LINK/V2, debugger/programmer with SWD connector -- Board power supply: through USB bus or from an external 5 V supply voltage -- External application power supply: 3 V and 5 V - -- Six LEDs: - - - LD1 (red/green) for USB communication - - LD2 (red) for 3.3 V power on - - Four user LEDs: LD3 (orange), LD4 (green), LD5 (red) and LD6 (blue) - -- Two push-buttons: USER and RESET -- USB USER with Mini-B connector -- L3GD20, ST MEMS motion sensor, 3-axis digital output gyroscope -- One linear touch sensor or four touch keys -- RF EEprom daughter board connector - -.. image:: img/stm32f072b_disco.jpg - :align: center - :alt: STM32F072B-DISCO - -More information about the board can be found at the -`STM32F072B-DISCO website`_. - -Hardware -******** - -STM32F072B-DISCO Discovery kit provides the following hardware components: - -- STM32F072RBTT6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg| -M0 CPU -- 48 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 128 KB Flash -- 16 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 39 channels -- 12-bit D/A converters -- RTC -- General Purpose Timers (12) -- USART/UART (4) -- I2C (2) -- SPI (2) -- CAN -- USB 2.0 full speed interface -- DMA Controller -- 24 capacitive sensing channels for touchkey, linear and rotary touch sensors - -More information about STM32F072RB can be found here: - - `STM32F072RB on www.st.com`_ - - `STM32F072xB reference manual`_ - -Supported Features -================== - -The Zephyr stm32f072b_disco board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | SPI controller | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_. - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f072b_disco/stm32f072b_disco_defconfig`` - - -Pin Mapping -=========== - -STM32F072B-DISCO Discovery kit has 6 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `STM32F072B-DISCO board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- I2C1_SCL : PB8 -- I2C1_SDA : PB9 -- I2C2_SCL : PB10 -- I2C2_SDA : PB11 -- SPI1_SCK : PB3 -- SPI1_MISO : PB4 -- SPI1_MOSI : PB5 -- USER_PB : PA0 -- LD3 : PC6 -- LD4 : PC8 -- LD5 : PC9 -- LD6 : PC7 -- CAN_RX : PB8 -- CAN_TX : PB9 - -System Clock -============ - -STM32F072B-DISCO System Clock could be driven by internal or external -oscillator, as well as main PLL clock. By default System clock is driven -by PLL clock at 72 MHz, driven by internal 8 MHz oscillator. - -Serial Port -=========== - -STM32F072B-DISCO Discovery kit has up to 4 UARTs. The Zephyr console output -is assigned to UART 1. Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f072b_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F072B-DISCO board includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - - -Flashing an application to STM32F072B-DISCO -------------------------------------------- - -First, connect the STM32F072B-DISCO Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f072b_disco - :goals: build flash - -Run a serial host program to connect with your board. A TTL(3.3V) serial -adapter is required. - -.. code-block:: console - - $ minicom -D /dev/ - -Replace with the port where the serial adapter can be found. -For example, under Linux, /dev/ttyUSB0. - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f072b_disco - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32F072B-DISCO website: - https://www.st.com/en/evaluation-tools/32f072bdiscovery.html - - -.. _STM32F072B-DISCO board User Manual: - https://www.st.com/resource/en/user_manual/dm00099401.pdf - -.. _STM32F072RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32f072rb.html - -.. _STM32F072xB reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936.pdf - -.. _SK Pang CAN breakout board: - https://www.skpang.co.uk/products/can-bus-can-fd-breakout-board-5v-supply-and-5v-logic diff --git a/boards/arm/stm32f072b_disco/stm32f072b_disco_defconfig b/boards/arm/stm32f072b_disco/stm32f072b_disco_defconfig deleted file mode 100644 index b5a9b9a3768..00000000000 --- a/boards/arm/stm32f072b_disco/stm32f072b_disco_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F072XB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32f0_disco/Kconfig.board b/boards/arm/stm32f0_disco/Kconfig.board deleted file mode 100644 index 82e26ac2b2d..00000000000 --- a/boards/arm/stm32f0_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F0DISCOVERY development board with STM32F051R8 MCU configuration - -# Copyright (c) 2018 Nathan Tsoi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F0_DISCO - bool "STM32F0DISCOVERY Development Board" - depends on SOC_STM32F051X8 diff --git a/boards/arm/stm32f0_disco/Kconfig.defconfig b/boards/arm/stm32f0_disco/Kconfig.defconfig deleted file mode 100644 index 638b4239522..00000000000 --- a/boards/arm/stm32f0_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F0 development board with STM32F051R8T6 MCU - -# Copyright (c) 2018 Nathan Tsoi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F0_DISCO - -config BOARD - default "stm32f0_disco" - -endif # BOARD_STM32F0_DISCO diff --git a/boards/arm/stm32f0_disco/doc/index.rst b/boards/arm/stm32f0_disco/doc/index.rst deleted file mode 100644 index daf0e1f06d3..00000000000 --- a/boards/arm/stm32f0_disco/doc/index.rst +++ /dev/null @@ -1,143 +0,0 @@ -.. _stm32f0_disco_board: - -ST STM32F0 Discovery -#################### - -Overview -******** - -The STM32F0 Discovery development board uses an STM32F051R8T6 MCU and -integrates the ST-LINK/V2-1 debugger and programmer. It also comes with a -comprehensive STM32 software HAL library and various packaged software -examples. - -.. image:: img/stm32f0_disco.jpg - :align: center - :alt: STM32F0DISCOVERY - -More information about the board can be found at the `STM32F0DISCOVERY website`_. - -Hardware -******** - -The STM32 Discovery board features: - -- STM32F051R8T6 microcontroller featuring 64 KB Flash memory, 8 KB RAM in an - LQFP64 package -- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone - ST-LINK/V2 (with SWD connector for programming and debugging) -- Board power supply: through USB bus or from an external 5 V supply voltage -- External application power supply: 3 V and 5 V -- Four LEDs: - - - LD1 (red) for 3.3 V power on - - LD2 (red/green) for USB communication - - LD3 (green) for PC9 output - - LD4 (blue) for PC8 output -- Two push buttons (user and reset) -- Extension header for all LQFP64 I/Os for quick connection to prototyping board - and easy probing -- An additional board is provided which can be connected to the extension - connector for even easier prototyping and probing. -- Comprehensive free software including a variety of examples, part of - STM32CubeF0 package or STSW-STM32049 for legacy Standard Libraries usage - -More information about STM32F051R8 can be found in the `STM32F0x8 reference manual`_. - -Supported Features -================== - -The Zephyr stm32f0_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f0_disco/stm32f0_disco_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 - -For more details please refer to `STM32F0DISCOVERY board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``stm32f0_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F0DISCOVERY board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F030R8 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f0_disco - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f0_disco - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32F0DISCOVERY website: - https://www.st.com/en/evaluation-tools/stm32f0discovery.html - -.. _STM32F0x8 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936.pdf - -.. _STM32F0DISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00050135.pdf diff --git a/boards/arm/stm32f103_mini/Kconfig.board b/boards/arm/stm32f103_mini/Kconfig.board deleted file mode 100644 index c719f989076..00000000000 --- a/boards/arm/stm32f103_mini/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F103RCT6 Mini board configuration - -# Copyright (c) 2020 WuhanStudio -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F103_MINI - bool "STM32F103RCT6 Mini Board" - depends on SOC_STM32F103XE diff --git a/boards/arm/stm32f103_mini/Kconfig.defconfig b/boards/arm/stm32f103_mini/Kconfig.defconfig deleted file mode 100644 index 294d123ccb1..00000000000 --- a/boards/arm/stm32f103_mini/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F103RCT6 Mini board configuration - -# Copyright (c) 2020 WuhanStudio -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F103_MINI - -config BOARD - default "stm32f103_mini" - -endif # BOARD_STM32F103_mini diff --git a/boards/arm/stm32f103_mini/doc/index.rst b/boards/arm/stm32f103_mini/doc/index.rst deleted file mode 100644 index 57e812d0c3a..00000000000 --- a/boards/arm/stm32f103_mini/doc/index.rst +++ /dev/null @@ -1,166 +0,0 @@ -.. _stm32f103_mini_board: - -STM32F103 Mini -################ - -Overview -******** - -The STM32F103_MINI board features an ARM Cortex-M3 based STM32F103RC MCU -with a wide range of connectivity support and configurations. There are -multiple version of this board like ``stm32f103_mini``. - -.. image:: img/stm32f103_mini_yellow.jpg - :align: center - :alt: STM32F103 Mini Yellow - -.. image:: img/stm32f103_mini_blue.jpg - :align: center - :alt: STM32F103 Mini Blue - -Hardware -******** -STM32F103 Mini provides the following hardware components: - -- STM32 microcontroller in QFP64 package - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Two LEDs: - - - User LED (LD1), power LED (LD2) - -- USB re-enumeration capability: - - - Mass storage - -More information about STM32F103RC can be found here: - -- `STM32F103 reference manual`_ -- `STM32F103 data sheet`_ - -Supported Features -================== - -The Zephyr stm32f103_mini board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f103_mini/stm32f103_mini_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/stm32f103_mini_pin.jpg - :align: center - :alt: Nucleo F103RB connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX: PA9/PA10 -- UART_2 TX/RX: PA2/PA3 (ST-Link Virtual COM Port) -- SPI1 NSS/SCK/MISO/MOSI: PA4/PA5/PA6/PA7 -- SPI2 NSS/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 -- I2C1 SDA/SCL: PB9/PB8 -- PWM1_CH1: PA8 -- USER_PB: PC13 -- LD1: PA5 -- USB_DC DM/DP: PA11/PA12 - -System Clock ------------- - -The on-board 8MHz crystal is used to produce a 72MHz system clock with PLL. - -Programming and Debugging -************************* - -Applications for the ``stm32f103_mini`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -There are 2 main entry points for flashing STM32F1X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware such as ST-Link). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. - -Flashing an application to stm32f103 mini ------------------------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f103_mini - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f103_mini - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32F103 reference manual: - https://www.st.com/resource/en/reference_manual/cd00171190.pdf - -.. _STM32F103 data sheet: - https://www.st.com/resource/en/datasheet/stm32f103rc.pdf diff --git a/boards/arm/stm32f3_disco/Kconfig.board b/boards/arm/stm32f3_disco/Kconfig.board deleted file mode 100644 index 280b48f7cb5..00000000000 --- a/boards/arm/stm32f3_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F3DISCOVERY board configuration - -# Copyright (c) 2017 I-SENSE group of ICCS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F3_DISCO - bool "STM32F3DISCOVERY Development Board" - depends on SOC_STM32F303XC diff --git a/boards/arm/stm32f3_disco/Kconfig.defconfig b/boards/arm/stm32f3_disco/Kconfig.defconfig deleted file mode 100644 index f2def331570..00000000000 --- a/boards/arm/stm32f3_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F3DISCOVERY board configuration - -# Copyright (c) 2017 I-SENSE group of ICCS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F3_DISCO - -config BOARD - default "stm32f3_disco" - -endif # BOARD_STM32F3_DISCO diff --git a/boards/arm/stm32f3_disco/doc/index.rst b/boards/arm/stm32f3_disco/doc/index.rst deleted file mode 100644 index 5a0dc214e06..00000000000 --- a/boards/arm/stm32f3_disco/doc/index.rst +++ /dev/null @@ -1,281 +0,0 @@ -.. _stm32f3_disco_board: - -ST STM32F3 Discovery -#################### - -Overview -******** - -The STM32F3DISCOVERY Discovery kit features an ARM Cortex-M4 based STM32F303VC -MCU with everything required for beginners and experienced users to get -started quickly. Here are some highlights of the STM32F3DISCOVERY board: - -- STM32 microcontroller in LQFP100 package -- Extension header for all LQFP100 I/Os for quick connection to prototyping - board and easy probing -- On-board, ST-LINK/V2 for PCB version A or B or ST-LINK/V2-B for PCB version - C and newer, debugger/programmer with SWD connector -- Board power supply: through USB bus or from an external 3 V or 5 V supply - voltage -- External application power supply: 3 V and 5 V - -- Ten LEDs: - - - 3.3 V power on (LD1) - - USB communication (LD2) - - Eight user LEDs: red (LD3/LD10), blue (LD4/LD9), orange (LD5/LD9) - and green (LD6/LD7) - -- Two push-buttons: USER and RESET -- USB USER with Mini-B connector -- L3GD20 or I3G4250D, ST MEMS motion sensor, 3-axis digital output gyroscope -- LSM303DLHC or LSM303AGR, ST MEMS system-in-package featuring a 3D digital linear - acceleration sensor and a 3D digital magnetic sensor; - -.. HINT:: - Recent PCB revisions (E and newer) are shipped with I3G4250D and LSM303AGR. - -.. image:: img/stm32f3_disco.jpg - :align: center - :alt: STM32F3DISCOVERY - -More information about the board can be found at the -`STM32F3DISCOVERY website`_. - -Hardware -******** - -STM32F3DISCOVERY Discovery kit provides the following hardware components: - -- STM32F303VCT6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 72 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 256 KB Flash -- 40 KB SRAM -- Routine booster: 8 Kbytes of SRAM on instruction and data bus -- GPIO with external interrupt capability -- 4x12-bit ADC with 39 channels -- 2x12-bit D/A converters -- RTC -- General Purpose Timers (13) -- USART/UART (5) -- I2C (2) -- SPI (3) -- CAN -- USB 2.0 full speed interface -- Infrared transmitter -- DMA Controller - -More information about STM32F303VC can be found here: - - `STM32F303VC on www.st.com`_ - - `STM32F303xC reference manual`_ - -Supported Features -================== - -The Zephyr stm32f3_disco board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN | -+-----------+------------+-------------------------------------+ -| IWDG | on-chip | Independent WatchDoG | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f3_disco/stm32f3_disco_defconfig`` - - -Pin Mapping -=========== - -STM32F3DISCOVERY Discovery kit has 6 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `STM32F3DISCOVERY board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PC4 -- UART_1_RX : PC5 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- UART_4_TX : PC10 -- UART_4_RX : PC11 -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PA9 -- I2C2_SDA : PA10 -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 -- CAN1_RX : PD0 -- CAN1_TX : PD1 -- USB_DM : PA11 -- USB_DP : PA12 -- USER_PB : PA0 -- LD3 : PE9 -- LD4 : PE8 -- LD5 : PE10 -- LD6 : PE15 -- LD7 : PE11 -- LD8 : PE14 -- LD9 : PE12 -- LD10 : PE13 -- PWM : PA8 -- ADC1 : PA0 -- DAC1 : PA4 - -System Clock -============ - -STM32F3DISCOVERY System Clock could be driven by internal or external -oscillator, as well as main PLL clock. By default System clock is driven -by PLL clock at 72 MHz, driven by 8 MHz MCO from the ST Link. - -Serial Port -=========== - -STM32F3DISCOVERY Discovery kit has up to 5 UARTs. The Zephyr console output -is assigned to UART1. Default settings are 115200 8N1. - -I2C -=== - -STM32F3DISCOVERY has up to 2 I2Cs. I2C1 is connected to the LSM303DLHC and is -an ultra-compact low-power system-in-package featuring a 3D digital linear -acceleration sensor and a 3D digital magnetic sensor. - -USB -=== -STM32F3DISCOVERY has a USB 2.0 full-speed device interface available through -its mini USB connector (USB USER). - -CAN -=== -The STM32F3DISCOVERY does not have an onboard CAN transceiver. In -order to use the CAN bus on the this board, an external CAN bus -transceiver must be connected to ``PD0`` (``CAN1_RX``) and ``PD1`` -(``CAN1_TX``). - -Programming and Debugging -************************* - -Flashing -======== - -STM32F3DISCOVERY Discovery kit includes a ST-LINK/V2 or ST-LINK/V2-B embedded -debug tool interface. - -Applications for the ``stm32f3_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing an application to STM32F3DISCOVERY -------------------------------------------- - -First, connect the STM32F3DISCOVERY Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f3_disco - :goals: build flash - - -In case you are using a recent PCB revision (E or newer), you have to use an -adapted board definition: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f3_disco@E - :goals: build flash - -Run a serial host program to connect with your board. For PCB version A or B a -TTL(3.3V) serial adapter is required. For PCB version C and newer a Virtual Com -Port (VCP) is available on the USB ST-LINK port. - -.. code-block:: console - - $ minicom -D /dev/ - -Replace with the port where the STM32F3DISCOVERY board can be -found. For example, under Linux, /dev/ttyUSB0. - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f3_disco - :goals: debug - -Again you have to use the adapted command for newer PCB revisions (E and newer): - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f3_disco@E - :goals: debug - -.. _STM32F3DISCOVERY website: - https://www.st.com/en/evaluation-tools/stm32f3discovery.html - -.. _STM32F3DISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00063382.pdf - -.. _STM32F303VC on www.st.com: - https://www.st.com/en/microcontrollers/stm32f303vc.html - -.. _STM32F303xC reference manual: - https://www.st.com/resource/en/reference_manual/dm00043574.pdf diff --git a/boards/arm/stm32f3_disco/revision.cmake b/boards/arm/stm32f3_disco/revision.cmake deleted file mode 100644 index 0bacf78187d..00000000000 --- a/boards/arm/stm32f3_disco/revision.cmake +++ /dev/null @@ -1,4 +0,0 @@ -board_check_revision( - FORMAT LETTER - DEFAULT_REVISION B -) \ No newline at end of file diff --git a/boards/arm/stm32f3_disco/stm32f3_disco.yaml b/boards/arm/stm32f3_disco/stm32f3_disco.yaml deleted file mode 100644 index 0d0aafdc5a2..00000000000 --- a/boards/arm/stm32f3_disco/stm32f3_disco.yaml +++ /dev/null @@ -1,24 +0,0 @@ -identifier: stm32f3_disco -name: ST STM32F3 Discovery -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 40 -supported: - - gpio - - i2c - - counter - - spi - - watchdog - - usb_device - - lsm303dlhc - - nvs - - can - - pwm - - adc - - dac - - dma -vendor: st diff --git a/boards/arm/stm32f3_disco/stm32f3_disco_B.conf b/boards/arm/stm32f3_disco/stm32f3_disco_B.conf deleted file mode 100644 index 039adb70c58..00000000000 --- a/boards/arm/stm32f3_disco/stm32f3_disco_B.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2021 Jonathan Hahn -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/stm32f3_disco/stm32f3_disco_E.conf b/boards/arm/stm32f3_disco/stm32f3_disco_E.conf deleted file mode 100644 index 039adb70c58..00000000000 --- a/boards/arm/stm32f3_disco/stm32f3_disco_E.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2021 Jonathan Hahn -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/stm32f3_disco/stm32f3_disco_E.yaml b/boards/arm/stm32f3_disco/stm32f3_disco_E.yaml deleted file mode 100644 index 596deb44834..00000000000 --- a/boards/arm/stm32f3_disco/stm32f3_disco_E.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: stm32f3_disco@E -name: ST STM32F3 Discovery rev E -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 40 -supported: - - gpio - - i2c - - counter - - spi - - watchdog - - usb_device - - i3g4250d - - nvs - - can - - pwm - - adc - - dac diff --git a/boards/arm/stm32f3_seco_d23/Kconfig.board b/boards/arm/stm32f3_seco_d23/Kconfig.board deleted file mode 100644 index 94536f8f05e..00000000000 --- a/boards/arm/stm32f3_seco_d23/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SECO SBC-3.5-PX30 board configuration - -# Copyright (c) 2022, SECO Spa -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F3_SECO_D23 - bool "SECO SBC-3.5-PX30 (STM32F302VC) Board" - depends on SOC_STM32F302XC diff --git a/boards/arm/stm32f3_seco_d23/Kconfig.defconfig b/boards/arm/stm32f3_seco_d23/Kconfig.defconfig deleted file mode 100644 index 4af3bbc0022..00000000000 --- a/boards/arm/stm32f3_seco_d23/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SECO SBC-3.5-PX30 board configuration - -# Copyright (c) 2022, SECO Spa -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F3_SECO_D23 - -config BOARD - default "stm32f3_seco_d23" - -endif # BOARD_STM32F3_SECO_D23 diff --git a/boards/arm/stm32f401_mini/Kconfig.board b/boards/arm/stm32f401_mini/Kconfig.board deleted file mode 100644 index f2dc8bdfa61..00000000000 --- a/boards/arm/stm32f401_mini/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Brian Bradley -# SPDX-License-Identifier: Apache-2.0 - -# STM32 Mini F401 Board - -config BOARD_STM32F401_MINI - bool "STM32 Mini F401 Board" - depends on SOC_STM32F401XC diff --git a/boards/arm/stm32f401_mini/Kconfig.defconfig b/boards/arm/stm32f401_mini/Kconfig.defconfig deleted file mode 100644 index 7279666dbcc..00000000000 --- a/boards/arm/stm32f401_mini/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022 Brian Bradley -# SPDX-License-Identifier: Apache-2.0 - -# STM32 Mini F401 board definitions - -if BOARD_STM32F401_MINI - -config BOARD - default "stm32f401_mini" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_STM32F401_MINI diff --git a/boards/arm/stm32f401_mini/doc/index.rst b/boards/arm/stm32f401_mini/doc/index.rst deleted file mode 100644 index 6465aec5ff5..00000000000 --- a/boards/arm/stm32f401_mini/doc/index.rst +++ /dev/null @@ -1,154 +0,0 @@ -.. _stm32f401_mini: - -STM32 Mini F401 -############### - -Overview -******** - -The STM32 Mini F401 is an extremely low cost and bare-bones -development board featuring the STM32F401CC, see `STM32F401CC website`_. -More info about the board with schematics available `here `_ - -.. image:: img/STM32_Mini_F401-1.jpg - :align: center - :alt: STM32 Mini F401 - -Hardware -******** - -The STM32F401CC based board provides the following -hardware components: - -- STM32F401CCU6 in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 84 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 256 KB Flash -- 64 KB SRAM -- GPIO with external interrupt capability -- 1x12-bit, 2.4 MSPS ADC with 16 channels -- DMA Controller -- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) -- USART/UART (3) -- I2C (3) -- SPI/I2S (4) -- SDIO -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- CRC calculation unit -- 96-bit unique ID -- RTC - -Supported Features -================== - -The Zephyr stm32f401_mini board configuration supports the following -hardware features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f401_mini/stm32f401_mini_defconfig`` - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- I2C1 SCL/SDA : PB8/PB9 -- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 -- PWM_4_CH1 : PB6 -- PWM_4_CH2 : PB7 -- ADC_1 : PA1 -- SW0 : PB2 (routed to BOOT1 dip switch) -- LED0 : PC13 - -Clock Sources -------------- - -The board has two external oscillators. The frequency of the slow clock (LSE) is -32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. - -The default configuration sources the system clock from the PLL, which is -derived from HSE, and is set at 84MHz. - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin, which on this board -is a dip switch. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -There is also a Windows version which works, but you may have to install the -right USB drivers with a tool like `Zadig`_. - -Flashing an Application ------------------------ - -Connect a USB-C cable and the board should power ON. Force the board into DFU mode -by setting the BOOT0 dip switch position to ON. Reset the board with the NRST button. - -The dfu-util runner is supported on this board and so a sample can be built and -tested easily. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f401_mini - :goals: build flash - -Debugging -========= - -The board can be debugged by installing the included 100 mil (0.1 inch) header, -and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO -pins on that header. - -References -********** - -.. target-notes:: - -.. _Zadig: - https://zadig.akeo.ie/ - -.. _stm32-base-board-page: - https://stm32-base.org/boards/STM32F401CCU6-STM32-Mini-F401 - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _STM32F401CC website: - https://www.st.com/en/microcontrollers-microprocessors/stm32f401cc.html diff --git a/boards/arm/stm32f411e_disco/Kconfig.board b/boards/arm/stm32f411e_disco/Kconfig.board deleted file mode 100644 index 20906de1171..00000000000 --- a/boards/arm/stm32f411e_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F411E-DISCO board configuration - -# Copyright (c) 2017 Fenix Engineering Solutions -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F411E_DISCO - bool "STM32F411E-DISCO Development Board" - depends on SOC_STM32F411XE diff --git a/boards/arm/stm32f411e_disco/Kconfig.defconfig b/boards/arm/stm32f411e_disco/Kconfig.defconfig deleted file mode 100644 index 28169b926e3..00000000000 --- a/boards/arm/stm32f411e_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F411E-DISCO board configuration - -# Copyright (c) 2017 Fenix Engineering Solutions -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F411E_DISCO - -config BOARD - default "stm32f411e_disco" - -endif # BOARD_STM32F411E_DISCO diff --git a/boards/arm/stm32f411e_disco/doc/index.rst b/boards/arm/stm32f411e_disco/doc/index.rst deleted file mode 100644 index 12a057ff1ad..00000000000 --- a/boards/arm/stm32f411e_disco/doc/index.rst +++ /dev/null @@ -1,188 +0,0 @@ -.. _stm32f411e_disco_board: - -ST STM32F411E Discovery -####################### - -Overview -******** - -The STM32F411E Discovery kit features an ARM Cortex-M4 based STM32F411VE MCU -with a wide range of connectivity support and configurations. -Here are some highlights of the STM32F411E-DISCO board: - -- STM32F411VET6 microcontroller featuring 512 KB of Flash memory, 128 KB of RAM in an LQFP100 package -- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone STLINK/V2 (with SWD connector for programming and debugging) -- Board power supply: through USB bus or from an external 5 V supply voltage -- External application power supply: 3 V and 5 V -- L3GD20(rev B) or I3G4250D(rev D): ST MEMS motion sensor, 3-axis digital output gyroscope. -- LSM303DLHC(rev B) or LSM303AGR(rev D): ST MEMS system-in-package featuring a 3D digital linear acceleration sensor and a 3D digital magnetic sensor. -- MP45DT02(rev B) or IMP34DT05(rev D), ST MEMS audio sensor, omnidirectional digital microphone -- CS43L22, audio DAC with integrated class D speaker driver -- Eight LEDs: - - LD1 (red/green) for USB communication - - LD2 (red) for 3.3 V power on - - Four user LEDs: - LD3 (orange), LD4 (green), LD5 (red) and LD6 (blue) - - Two USB OTG LEDs: - LD7 (green) VBus and LD8 (red) over-current -- Two pushbuttons (user and reset) -- USB OTG with micro-AB connector -- Extension header for LQFP100 I/Os for a quick connection to the prototyping board and an easy probing - -.. image:: img/stm32f411e_disco.jpg - :align: center - :alt: STM32F411E-DISCO - -More information about the board can be found at the `32F411EDISCOVERY website`_. - -Hardware -******** - -STM32F411E-DISCO Discovery kit provides the following hardware components: - -- STM32F411VET6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 128 KB SRAM -- GPIO with external interrupt capability -- 1x12-bit, 2.4 MSPS ADC with 16 channels -- DMA Controller -- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) -- USART/UART (3) -- I2C (3) -- SPI/I2S (5) -- SDIO -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- CRC calculation unit -- 96-bit unique ID -- RTC - -More information about STM32F411VE can be found here: - - `STM32F411VE website`_ - - `STM32F411x reference manual`_ - -Supported Features -================== - -The Zephyr stm32f411e_disco board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file -:zephyr_file:`boards/arm/stm32f411e_disco/stm32f411e_disco_defconfig` - - -Pin Mapping -=========== - -STM32F411E-DISCO Discovery kit has 5 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `32F411EDISCOVERY board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- LD3 : PD13 (PWM4 CH2) -- LD4 : PD12 (PWM4 CH1) -- LD5 : PD14 (PWM4 CH3) -- LD6 : PD15 (PWM4 CH4) - -System Clock -============ - -STM32F411E-DISCO System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 100MHz, driven by the internal oscillator. - -Serial Port -=========== - -The STM32F411G Discovery kit has up to 3 UARTs. The Zephyr console output is -assigned to UART2. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``stm32f411e_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F411E-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool -interface. This interface is supported by the openocd version included in -Zephyr SDK. - -Flashing an application to STM32F411E-DISCO -------------------------------------------- - -Connect the STM32F411E-DISCO Discovery kit to your host computer using the -USB port. Then build and flash an application. - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f411e_disco - :goals: build flash - -In case you are using PCB revision B, you have to use an -adapted board definition as the default PCB rev here is D: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f411e_disco@B - :goals: build flash - -You should see the orange led (LD3) blinking every second. - -Debugging -========= - -You can debug applications in the usual way. Here is an example for -the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f411e_disco - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _32F411EDISCOVERY website: - https://www.st.com/en/evaluation-tools/32f411ediscovery.html - -.. _32F411EDISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00148985.pdf - -.. _STM32F411VE website: - https://www.st.com/en/microcontrollers/stm32f411ve.html - -.. _STM32F411x reference manual: - https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/stm32f411e_disco/revision.cmake b/boards/arm/stm32f411e_disco/revision.cmake deleted file mode 100644 index 3a653a431a9..00000000000 --- a/boards/arm/stm32f411e_disco/revision.cmake +++ /dev/null @@ -1,4 +0,0 @@ -board_check_revision( - FORMAT LETTER - DEFAULT_REVISION D -) diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco_B.conf b/boards/arm/stm32f411e_disco/stm32f411e_disco_B.conf deleted file mode 100644 index a6756435b9c..00000000000 --- a/boards/arm/stm32f411e_disco/stm32f411e_disco_B.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco_D.conf b/boards/arm/stm32f411e_disco/stm32f411e_disco_D.conf deleted file mode 100644 index a6756435b9c..00000000000 --- a/boards/arm/stm32f411e_disco/stm32f411e_disco_D.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/stm32f412g_disco/Kconfig.board b/boards/arm/stm32f412g_disco/Kconfig.board deleted file mode 100644 index 1e0ba7aaae2..00000000000 --- a/boards/arm/stm32f412g_disco/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# STM32F412G-DISCO board configuration - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F412G_DISCO - bool "STM32F412G-DISCO Development Board" - depends on SOC_STM32F412ZX diff --git a/boards/arm/stm32f412g_disco/Kconfig.defconfig b/boards/arm/stm32f412g_disco/Kconfig.defconfig deleted file mode 100644 index d91c45fd1e8..00000000000 --- a/boards/arm/stm32f412g_disco/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# STM32F412G-DISCO board configuration - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F412G_DISCO - -config BOARD - default "stm32f412g_disco" - -endif # BOARD_STM32F412G_DISCO diff --git a/boards/arm/stm32f412g_disco/doc/index.rst b/boards/arm/stm32f412g_disco/doc/index.rst deleted file mode 100644 index 8bd0bd588f1..00000000000 --- a/boards/arm/stm32f412g_disco/doc/index.rst +++ /dev/null @@ -1,202 +0,0 @@ -.. _stm32f412g_disco_board: - -ST STM32F412G Discovery -####################### - -Overview -******** - -The STM32F412 Discovery kit features an ARM Cortex-M4 based STM32F412ZG MCU -with a wide range of connectivity support and configurations Here are -some highlights of the STM32F412G-DISCO board: - - -- STM32F412ZGT6 microcontroller featuring 1 Mbyte of Flash memory and 256 Kbytes of RAM in an LQFP144 package -- On-board ST-LINK/V2-1 SWD debugger supporting USB re-enumeration capability: - - - USB virtual COM port - - mass storage - - debug port - -- 1.54 inch 240x240 pixel TFT color LCD with parallel interface and capacitive touchscreen -- I2S Audio CODEC, with a stereo headset jack, including analog microphone input and a loudspeaker output -- Stereo digital MEMS microphones -- MicroSD card connector extension -- I2C extension connector -- 128 Mbit Quad-SPI Nor Flash -- Reset button and Joystick -- Four color user LEDs. -- USB OTG FS with Micro-AB connector -- Four power supply options: - - - ST-LINK/V2-1 USB connector - - User USB FS connector - - VIN from Arduino* connectors - - + 5 V from Arduino* connectors - -- Two power supplies for MCU: 2.0 V and 3.3 V -- Compatible with Arduino(tm) Uno revision 3 connectors -- Extension connector for direct access to various features of STM32F412ZGT6 MCU -- Comprehensive free software including a variety of examples, part of STM32Cube package - -.. image:: img/stm32f412g_disco.jpg - :align: center - :alt: STM32F412G-DISCO - -More information about the board can be found at the `32F412GDISCOVERY website`_. - -Hardware -******** - -STM32F469I-DISCO Discovery kit provides the following hardware components: - -- STM32F412ZGT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1 MB Flash -- 256 KB SRAM -- GPIO with external interrupt capability -- LCD parallel interface, 8080/6800 modes -- 1x12-bit ADC with 16 channels -- RTC -- Advanced-control Timer -- General Purpose Timers (12) -- Watchdog Timers (2) -- USART/UART (4) -- I2C (4) -- SPI (5) -- SDIO -- 2xCAN -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F412ZG can be found here: - - `STM32F412ZG on www.st.com`_ - - `STM32F412 reference manual`_ - -Supported Features -================== - -The Zephyr stm32f412g_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f412g_disco/stm32f412g_disco_defconfig`` - - -Pin Mapping -=========== - -STM32F412G-DISCO Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F412GDISCOVERY board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- LD1 : PE0 -- LD2 : PE1 -- LD3 : PE2 -- LD4 : PE3 - -System Clock -============ - -STM32F412G-DISCO System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 100MHz, -driven internal oscillator. - -Serial Port -=========== - -The STM32F412G Discovery kit has up to 4 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``stm32f412g_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F412G-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32F412G-DISCO -------------------------------------------- - -Connect the STM32F412G-DISCO Discovery kit to your host computer using -the USB port, then run a serial host program to connect with your -board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f412g_disco - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f412g_disco - :maybe-skip-config: - :goals: debug - -.. _32F412GDISCOVERY website: - https://www.st.com/en/evaluation-tools/32f412gdiscovery.html - -.. _32F412GDISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00275919.pdf - -.. _STM32F412ZG on www.st.com: - https://www.st.com/en/microcontrollers/stm32f412zg.html - -.. _STM32F412 reference manual: - https://www.st.com/resource/en/reference_manual/dm00180369.pdf diff --git a/boards/arm/stm32f429i_disc1/Kconfig.board b/boards/arm/stm32f429i_disc1/Kconfig.board deleted file mode 100644 index 07ecfb82b69..00000000000 --- a/boards/arm/stm32f429i_disc1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F4DISCOVERY board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F429I_DISC1 - bool "STM32F429I-DISC1 Development Board" - depends on SOC_STM32F429XX diff --git a/boards/arm/stm32f429i_disc1/Kconfig.defconfig b/boards/arm/stm32f429i_disc1/Kconfig.defconfig deleted file mode 100644 index b6e1113e010..00000000000 --- a/boards/arm/stm32f429i_disc1/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# STM32F4DISCOVERY board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F429I_DISC1 - -config BOARD - default "stm32f429i_disc1" - -config INPUT - default y if DISPLAY - -config MEMC - default y if DISPLAY - -endif # BOARD_STM32F429I_DISC1 diff --git a/boards/arm/stm32f429i_disc1/doc/index.rst b/boards/arm/stm32f429i_disc1/doc/index.rst deleted file mode 100644 index 9b90abf0dbb..00000000000 --- a/boards/arm/stm32f429i_disc1/doc/index.rst +++ /dev/null @@ -1,230 +0,0 @@ -.. _stm32f429i_disc1_board: - -ST STM32F429I Discovery -####################### - -Overview -******** - -The STM32F429I-DISC1 Discovery kit features an ARM Cortex-M4 based STM32F429ZI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the STM32F429I-DISC1 board: - -- STM32 microcontroller in LQFP144 package -- Extension header for all LQFP144 I/Os for quick connection to prototyping board and easy probing -- On-board ST-LINK/V2-B debugger/programmer with SWD connector -- Flexible board power supply: - - - ST-LINK/V2-1 USB connector - - User USB FS connector - - VIN from Arduino* compatible connectors - -- Two push-buttons: USER and RESET -- USB OTG FS with micro-AB connector -- 2.4-inch QVGA LCD with MIPI DSI interface and capacitive touch screen -- 64Mbit SDRAM -- L3GD20, ST-MEMS motion sensor 3-axis digital output gyroscope -- Six LEDs - - - LD1 (red/green) for USB communication - - LD2 (red) for 3.3 V power-on - - Two user LEDs: LD3 (green), LD4 (red) - - Two USB OTG LEDs: LD5 (green) VBUS and LD6 (red) OC (over-current) - -.. image:: img/stm32f429i_disc1.jpg - :align: center - :alt: STM32F429I-DISC1 - -More information about the board can be found at the `STM32F429I-DISC1 website`_. - -Hardware -******** - -The STM32F429I-DISC1 Discovery kit provides the following hardware components: - -- STM32F429ZIT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 180 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 2 MB Flash -- 256+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (4/4) -- I2C (3) -- SPI (6) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F429ZI can be found here: - - `STM32F429ZI on www.st.com`_ - - `STM32F429 Reference Manual`_ - -Supported Features -================== - -The Zephyr stm32f429i_disc1 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| OTG_HS | on-chip | usbotg_hs | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f429i_disc1/stm32f429i_disc1_defconfig`` - - -Pin Mapping -=========== - -The STM32F429I-DISC1 Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32F429I-DISC1 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- USER_PB : PA0 -- LD3 : PG13 -- LD4 : PG12 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB9 -- I2C_2_SCL : PB10 -- I2C_2_SDA : PB11 -- I2C_3_SCL : PA8 -- I2C_3_SDA : PC9 -- SPI_5_CS : PF6 -- SPI_5_SCK : PF7 -- SPI_5_MISO : PF8 -- SPI_5_MOSI : PF9 -- OTG_HS_ID : PB12 -- OTG_HS_DM : PB14 -- OTG_HS_DP : PB15 - -System Clock -============ - -The STM32F429I-DISC1 System Clock could be driven by an internal or external oscillator, -as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 168MHz, -driven by an 8MHz high speed external clock. - -Serial Port -=========== - -The STM32F429I-DISC1 Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1. -The default communication settings are 115200 8N1. - -USB Port -=========== - -The STM32F429I-DISC1 Discovery kit has a USB FS capable Micro-B port. It is connected to the on-chip -OTG_HS peripheral, but operates in FS mode only since no HS PHY is present. The board supports device -and host OTG operation, but only device mode has been tested with Zephyr at this time. - -Programming and Debugging -************************* - -Applications for the ``stm32f429i_disc1`` board configuration can be built -and flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -The STM32F429I-DISC1 Discovery kit includes a ST-LINK/V2-B embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32F429I-DISC1 -------------------------------------------- - -The board is configured to be flashed using west OpenOCD runner. -Alternatively, you can use `STM32CubeProgrammer`_ (after installing it) using the ``--runner`` -(or ``-r``) option: - -.. code-block:: console - - $ west flash --runner stm32cubeprogrammer - -First, connect the STM32F429I-DISC1 Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f429i_disc1 - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, press the RESET button (The black one), you should see the following message: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f429i_disc1 - :goals: debug - -.. _STM32F429I-DISC1 website: - https://www.st.com/en/evaluation-tools/32f429idiscovery.html - -.. _STM32F429I-DISC1 board User Manual: - https://www.st.com/web/en/resource/technical/document/user_manual/DM00097320.pdf - -.. _STM32F429ZI on www.st.com: - https://www.st.com/en/microcontrollers/stm32f429-439.html - -.. _STM32F429 Reference Manual: - https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32f469i_disco/Kconfig.board b/boards/arm/stm32f469i_disco/Kconfig.board deleted file mode 100644 index 5dc1cf80449..00000000000 --- a/boards/arm/stm32f469i_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F469I-DISCO board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F469I_DISCO - bool "STM32F469I-DISCO Development Board" - depends on SOC_STM32F469XX diff --git a/boards/arm/stm32f469i_disco/Kconfig.defconfig b/boards/arm/stm32f469i_disco/Kconfig.defconfig deleted file mode 100644 index 0afb292c333..00000000000 --- a/boards/arm/stm32f469i_disco/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32F469I-DISCO board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F469I_DISCO - -config BOARD - default "stm32f469i_disco" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - - -endif # BOARD_STM32F469I_DISCO diff --git a/boards/arm/stm32f469i_disco/doc/index.rst b/boards/arm/stm32f469i_disco/doc/index.rst deleted file mode 100644 index 658f2a7b75e..00000000000 --- a/boards/arm/stm32f469i_disco/doc/index.rst +++ /dev/null @@ -1,208 +0,0 @@ -.. _stm32f469i_disco_board: - -ST STM32F469I Discovery -####################### - -Overview -******** - -The STM32F469 Discovery kit features an ARM Cortex-M4 based STM32F469NI MCU -with a wide range of connectivity support and configurations Here are -some highlights of the STM32F469I-DISCO board: - - -- STM32 microcontroller in BGA216 package -- On-board ST-LINK/V2-1 debugger/programmer, supporting USB reenumeration capability -- Flexible board power supply: - - - ST-LINK/V2-1 USB connector - - User USB FS connector - - VIN from Arduino* compatible connectors - -- Four user LEDs -- Two push-buttons: USER and RESET -- USB OTG FS with micro-AB connector -- 4-inch 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive touch screen -- SAI Audio DAC, with a stereo headphone output jack -- Three MEMS microphones -- MicroSD card connector -- I2C extension connector -- 4Mx32bit SDRAM -- 128-Mbit Quad-SPI NOR Flash -- Expansion connectors and Arduino UNO V3 connectors - -.. image:: img/stm32f469i_disco.jpg - :align: center - :alt: STM32F469I-DISCO - -More information about the board can be found at the `32F469IDISCOVERY website`_. - -Hardware -******** - -STM32F469I-DISCO Discovery kit provides the following hardware components: - -- STM32F469NIH6 in BGA216 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 180 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 2 MB Flash -- 384+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- LCD parallel interface, 8080/6800 modes -- LCD TFT controller supporting up to XGA resolution -- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (8) -- I2C (3) -- SPI (6) -- 1xSAI (serial audio interface) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F469NI can be found here: - - `STM32F469NI on www.st.com`_ - - `STM32F469 reference manual`_ - -Supported Features -================== - -The Zephyr stm32f469i_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| SDIO | on-chip | SD-card controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f469i_disco/stm32f469i_disco_defconfig`` - - -Pin Mapping -=========== - -STM32F469I-DISCO Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F469IDISCOVERY board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_3 TX/RX : PB10/PB11 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI2 NSS/SCK/MISO/MOSI : PH6/PD3/PB14/PB15 (Arduino SPI) -- SDIO D0/D1/D2/D3/CLK/Detect : PC8/PC9/PC10/PC11/PC12/PG2 -- USB DM : PA11 -- USB DP : PA12 -- USER_PB : PA0 -- LD1 : PG6 -- LD2 : PD4 -- LD3 : PD5 -- LD4 : PK3 - -System Clock -============ - -STM32F469I-DISCO System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 180MHz, -driven by 8MHz high speed external clock. - -Serial Port -=========== - -The STM32F469 Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART3. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``stm32f469i_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F469I-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32F469I-DISCO -------------------------------------------- - -First, connect the STM32F469I-DISCO Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f469i_disco - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f469i_disco - :goals: debug - - -.. _32F469IDISCOVERY website: - https://www.st.com/en/evaluation-tools/32f469idiscovery.html - -.. _32F469IDISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00218846.pdf - -.. _STM32F469NI on www.st.com: - https://www.st.com/en/microcontrollers/stm32f469ni.html - -.. _STM32F469 reference manual: - https://www.st.com/resource/en/reference_manual/dm00127514.pdf diff --git a/boards/arm/stm32f4_disco/Kconfig.board b/boards/arm/stm32f4_disco/Kconfig.board deleted file mode 100644 index e3788007766..00000000000 --- a/boards/arm/stm32f4_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F4DISCOVERY board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F4_DISCO - bool "STM32F4DISCOVERY Development Board" - depends on SOC_STM32F407XG diff --git a/boards/arm/stm32f4_disco/Kconfig.defconfig b/boards/arm/stm32f4_disco/Kconfig.defconfig deleted file mode 100644 index 5d8c5341bbb..00000000000 --- a/boards/arm/stm32f4_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F4DISCOVERY board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F4_DISCO - -config BOARD - default "stm32f4_disco" - -endif # BOARD_STM32F4_DISCO diff --git a/boards/arm/stm32f4_disco/doc/index.rst b/boards/arm/stm32f4_disco/doc/index.rst deleted file mode 100644 index 15dadab7fbf..00000000000 --- a/boards/arm/stm32f4_disco/doc/index.rst +++ /dev/null @@ -1,214 +0,0 @@ -.. _stm32f4_disco_board: - -ST STM32F4 Discovery -#################### - -Overview -******** - -The STM32F4DISCOVERY Discovery kit features an ARM Cortex-M4 based STM32F407VG MCU -with a wide range of connectivity support and configurations Here are -some highlights of the STM32F4DISCOVERY board: - - -- STM32 microcontroller in LQFP100 package -- Extension header for all LQFP100 I/Os for quick connection to prototyping board and easy probing -- On-board ST-LINK/V2 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Eight LEDs: - - - USB communication (LD1) - - 3.3 V power on (LD2) - - Four user LEDs: orange (LD3), green (LD4), red (LD5), and blue (LD6) - - 2 USB OTG LEDs for VBUS (LD7) and over-current (LD8) - -- Two push-buttons: USER and RESET -- USB OTG FS with micro-AB connector -- LIS302DL or LIS3DSH ST MEMS 3-axis accelerometer -- MP45DT02 ST-MEMS audio sensor omni-directional digital microphone -- CS43L22 audio DAC with integrated class D speaker driver - -.. image:: img/stm32f4_disco.jpg - :align: center - :alt: STM32F4DISCOVERY - -More information about the board can be found at the `STM32F4DISCOVERY website`_. - -Hardware -******** - -STM32F4DISCOVERY Discovery kit provides the following hardware components: - -- STM32F407VGT6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 168 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 1 MB Flash -- 192+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (6) -- I2C (3) -- SPI (3) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F407VG can be found here: - - `STM32F407VG on www.st.com`_ - - `STM32F407 reference manual`_ - -Supported Features -================== - -The Zephyr stm32f4_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_. - Zephyr default configuration uses CAN_2 exclusively, as simultaneous use - of CAN_1 and CAN_2 is not yet supported. - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f4_disco/stm32f4_disco_defconfig`` - - -Pin Mapping -=========== - -STM32F4DISCOVERY Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32F4DISCOVERY board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- USER_PB : PA0 -- LD3 : PD13 -- LD4 : PD12 -- LD5 : PD14 -- LD6 : PD15 -- USB DM : PA11 -- USB DP : PA12 -- CAN1_RX : PB8 -- CAN1_TX : PB9 -- CAN2_RX : PB5 -- CAN2_TX : PB13 - -System Clock -============ - -STM32F4DISCOVERY System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 168MHz, -driven by 8MHz high speed external clock. - -Serial Port -=========== - -STM32F4DISCOVERY Discovery kit has up to 6 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. -Please note that ST-Link Virtual Com Port is not wired to chip serial port. In order to -enable console output you should use a serial cable and connect it to UART2 pins (PA2/PA3). - - -Programming and Debugging -************************* - -Applications for the ``stm32f4_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F4DISCOVERY Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32F4DISCOVERY -------------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f4_disco - :goals: build flash - -You should see user led "LD4" blinking. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f4_disco - :maybe-skip-config: - :goals: debug - -.. _STM32F4DISCOVERY website: - https://www.st.com/en/evaluation-tools/stm32f4discovery.html - -.. _STM32F4DISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00039084.pdf - -.. _STM32F407VG on www.st.com: - https://www.st.com/en/microcontrollers/stm32f407vg.html - -.. _STM32F407 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031020.pdf - -.. _SK Pang CAN breakout board: - https://www.skpang.co.uk/products/can-bus-can-fd-breakout-board-5v-supply-and-3-3v-logic diff --git a/boards/arm/stm32f723e_disco/Kconfig.board b/boards/arm/stm32f723e_disco/Kconfig.board deleted file mode 100644 index 87101062904..00000000000 --- a/boards/arm/stm32f723e_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F723E Discovery board configuration - -# Copyright (c) 2018 Aurelien Jarno -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F723E_DISCO - bool "STM32F723E Discovery Development Board" - depends on SOC_STM32F723XX diff --git a/boards/arm/stm32f723e_disco/Kconfig.defconfig b/boards/arm/stm32f723e_disco/Kconfig.defconfig deleted file mode 100644 index f8406381d3f..00000000000 --- a/boards/arm/stm32f723e_disco/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32F723E DISCOVERY board configuration - -# Copyright (c) 2018 Aurelien Jarno -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F723E_DISCO - -config BOARD - default "stm32f723e_disco" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - - -endif # BOARD_STM32F723E_DISCO diff --git a/boards/arm/stm32f723e_disco/doc/index.rst b/boards/arm/stm32f723e_disco/doc/index.rst deleted file mode 100644 index c6e34cbbe91..00000000000 --- a/boards/arm/stm32f723e_disco/doc/index.rst +++ /dev/null @@ -1,192 +0,0 @@ -.. _stm32f723e_disco_board: - -ST STM32F723E Discovery -####################### - -Overview -******** - -The discovery kit enables a wide diversity of applications taking benefit -from audio, multi-sensor support, graphics, security, security, video, -and high-speed connectivity features. Important board features include: - -- STM32F723IEK6 microcontroller featuring 512 Kbytes of Flash memory and 256+16+4 Kbytes of RAM, in BGA176 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- TFT LCD 240x240 pixels with touch panel -- SAI audio codec -- Audio line in and line out jack -- Stereo speaker outputs -- Four ST MEMS microphones -- Two pushbuttons (user and reset) -- 512-Mbit Quad-SPI Flash memory -- 8-Mbit external PSRAM -- USB OTG HS with Micro-AB connectors -- USB OTG FS with Micro-AB connectors - -.. image:: img/stm32f723e_disco.jpg - :align: center - :alt: STM32F723E-DISCO - -More information about the board can be found at the `32F723E-DISCO website`_. - -Hardware -******** - -The STM32F723E Discovery kit provides the following hardware components: - -- STM32F723IEK6 in BGA176 package -- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU -- 216 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 1 MB Flash -- 256+16+4 KB SRAM including 64KB of tightly coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer (2) -- General Purpose Timers (13) -- Watchdog Timers (2) -- USART/UART (8) -- I2C (3) -- SPI (5) -- 2xSAI (serial audio interface) -- SDIO (2) -- CAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and on-chip hi-speed PHY -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F723IEK6 can be found here: - -- `STM32F723IEK6 on www.st.com`_ -- `STM32F72xxx reference manual`_ - -Supported Features -================== - -The Zephyr stm32f723e_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f723e_disco/stm32f723e_disco_defconfig`` - -Pin Mapping -=========== - -STM32F723E Discovery kit has 7 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F723E-DISCO board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2 TX/RX : PA2/PA3 (Arduino Serial) -- UART_6 TX/RX : PC6/PC7 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 -- I2C2 SCL/SDA : PH4/PH5 (Arduino I2C) -- I2C3 SCL/SDA : PA8/PH8 -- SPI1 SCK/MISO/MOSI : PA5/PB4/PB5 (Arduino SPI) -- LD1 : PA5 -- LD5 : PA7 -- LD6 : PB1 -- OTG_FS_DM : PA11 -- OTG_FS_DP : PA12 - -System Clock -============ - -The STM32F723E System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven by the PLL -clock at 216MHz, driven by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32F723E Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART6 -which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication -settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f723e_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F723E Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to STM32F723E-DISCO -------------------------------------------- - -First, connect the STM32F723E Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f723e_disco - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f723e_disco - :goals: debug - - -.. _32F723E-DISCO website: - https://www.st.com/en/evaluation-tools/32f723ediscovery.html - -.. _32F723E-DISCO board User Manual: - https://www.st.com/resource/en/user_manual/dm00342318.pdf - -.. _STM32F723IEK6 on www.st.com: - https://www.st.com/en/microcontrollers/stm32f723ie.html - -.. _STM32F72xxx reference manual: - https://www.st.com/resource/en/reference_manual/dm00305990.pdf diff --git a/boards/arm/stm32f746g_disco/Kconfig.board b/boards/arm/stm32f746g_disco/Kconfig.board deleted file mode 100644 index b1916605531..00000000000 --- a/boards/arm/stm32f746g_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F746G Discovery board configuration - -# Copyright (c) 2018 Yurii Hamann -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F746G_DISCO - bool "STM32F746G Discovery Development Board" - depends on SOC_STM32F746XX diff --git a/boards/arm/stm32f746g_disco/Kconfig.defconfig b/boards/arm/stm32f746g_disco/Kconfig.defconfig deleted file mode 100644 index cd653cd18c9..00000000000 --- a/boards/arm/stm32f746g_disco/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# STM32F746G DISCOVERY board configuration - -# Copyright (c) 2018 Yurii Hamann -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F746G_DISCO - -config BOARD - default "stm32f746g_disco" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -config INPUT - default y if LVGL - -if DISPLAY - -# MEMC needs to be enabled in order to store -# display buffer to external SDRAM connected to FMC -config MEMC - default y - -endif # DISPLAY - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_STM32F746G_DISCO diff --git a/boards/arm/stm32f746g_disco/doc/index.rst b/boards/arm/stm32f746g_disco/doc/index.rst deleted file mode 100644 index 714a627ec4a..00000000000 --- a/boards/arm/stm32f746g_disco/doc/index.rst +++ /dev/null @@ -1,243 +0,0 @@ -.. _stm32f746g_disco_board: - -ST STM32F746G Discovery -####################### - -Overview -******** - -The discovery kit enables a wide diversity of applications taking benefit -from audio, multi-sensor support, graphics, security, security, video, -and high-speed connectivity features. Important board features include: - -- STM32F746NGH6 microcontroller featuring 1 Mbytes of Flash memory and 340 Kbytes of RAM, in BGA216 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- Five power supply options: - - - ST LINK/V2-1 - - USB FS connector - - USB HS connector - - VIN from Arduino connector - - External 5 V from connector - -- Two pushbuttons (user and reset) -- USB functions: virtual COM port, mass storage, debug port -- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen -- SAI audio codec -- Audio line in and line out jack -- Stereo speaker outputs -- Two ST MEMS microphones -- SPDIF RCA input connector -- 128-Mbit Quad-SPI Flash memory -- 128-Mbit SDRAM (64 Mbits accessible) -- Connector for microSD card -- USB OTG HS with Micro-AB connectors -- USB OTG FS with Micro-AB connectors -- Ethernet connector compliant with IEEE-802.3-2002 - -.. image:: img/stm32f746g_disco.jpg - :align: center - :alt: STM32F746G-DISCO - -More information about the board can be found at the `32F746G-DISCO website`_. - -Hardware -******** - -The STM32F746G Discovery kit provides the following hardware components: - -- STM32F746NGH6 in BGA216 package -- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU -- 216 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 2 MB Flash -- 384+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- LCD parallel interface, 8080/6800 modes -- LCD TFT controller supporting up to XGA resolution -- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (8) -- I2C (3) -- SPI (6) -- 1xSAI (serial audio interface) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F746NGH6 can be found here: - -- `STM32F746NGH6 on www.st.com`_ -- `STM32F74xxx reference manual`_ - -Supported Features -================== - -The Zephyr stm32f746g_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | Ethernet | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| LTDC | on-chip | display | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f746g_disco/stm32f746g_disco_defconfig`` - -Pin Mapping -=========== - -STM32F746G Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F746G-DISCO board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The STM32F746G Discovery kit features an Arduino Uno V3 connector. Board is -configured as follows - -- UART_1 TX/RX : PA9/PB7 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PC6/PC7 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SDMMC_1 D0/D1/D2/D3/CK/CD/CMD: PC8/PC9/PC10/PC11/PC12/PC13/PD2 -- SPI2 NSS/SCK/MISO/MOSI : PA8/PI1/PB14/PB15 (Arduino SPI) -- PWM_3_CH1 : PB4 -- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 -- USER_PB : PI11 -- LD1 : PI1 -- USB DM : PA11 -- USB DP : PA12 -- FMC SDRAM : - - - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 - - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 - - A14/A15 : PG4/PG5 - - SDNRAS/SDNCAS : PF11/PG15 - - NBL0/NBL1 : PE0/PE1 - - SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3 - -- LTDC : - - - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 - - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 - - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 - - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 - - -System Clock -============ - -The STM32F746G System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven by the PLL -clock at 216MHz, driven by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32F746G Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 -which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication -settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f746g_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F746G Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to STM32F746G -------------------------------------------- - -First, connect the STM32F746G Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f746g_disco - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f746g_disco - :goals: debug - - -.. _32F746G-DISCO website: - https://www.st.com/en/evaluation-tools/32f746gdiscovery.html - -.. _32F746G-DISCO board User Manual: - https://www.st.com/resource/en/user_manual/dm00190424.pdf - -.. _STM32F746NGH6 on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html - -.. _STM32F74xxx reference manual: - https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/stm32f7508_dk/Kconfig.board b/boards/arm/stm32f7508_dk/Kconfig.board deleted file mode 100644 index 5f6e707d522..00000000000 --- a/boards/arm/stm32f7508_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F7508-DK Discovery board configuration - -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F7508_DK - bool "STM32F7508-DK Discovery Kit" - depends on SOC_STM32F750XX diff --git a/boards/arm/stm32f7508_dk/Kconfig.defconfig b/boards/arm/stm32f7508_dk/Kconfig.defconfig deleted file mode 100644 index 7995c1fbae7..00000000000 --- a/boards/arm/stm32f7508_dk/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# STM32F7508-DK Discovery board configuration - -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F7508_DK - -config BOARD - default "stm32f7508_dk" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -if DISPLAY - -# MEMC needs to be enabled in order to store -# display buffer to external SDRAM connected to FMC -config MEMC - default y - -endif # DISPLAY - -config INPUT - default y if LVGL - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_STM32F7508_DK diff --git a/boards/arm/stm32f7508_dk/doc/index.rst b/boards/arm/stm32f7508_dk/doc/index.rst deleted file mode 100644 index 699285fcd90..00000000000 --- a/boards/arm/stm32f7508_dk/doc/index.rst +++ /dev/null @@ -1,238 +0,0 @@ -.. _stm32f7508_dk_board: - -ST STM32F7508-DK Discovery Kit -############################## - -Overview -******** - -The discovery kit enables a wide diversity of applications taking benefit -from audio, multi-sensor support, graphics, security, security, video, -and high-speed connectivity features. Important board features include: - -- STM32F750N8H6 microcontroller featuring 64 Kbytes of Flash memory and 340 Kbytes of RAM, in BGA216 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- Five power supply options: - - - ST LINK/V2-1 - - USB FS connector - - USB HS connector - - VIN from Arduino connector - - External 5 V from connector - -- Two pushbuttons (user and reset) -- USB functions: virtual COM port, mass storage, debug port -- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen -- SAI audio codec -- Audio line in and line out jack -- Two ST MEMS microphones -- SPDIF RCA input connector -- 128-Mbit Quad-SPI Flash memory -- 128-Mbit SDRAM (64 Mbits accessible) -- Connector for microSD card -- USB OTG HS with Micro-AB connectors -- USB OTG FS with Micro-AB connectors -- Ethernet connector compliant with IEEE-802.3-2002 - -.. image:: img/stm32f7508_dk.jpg - :align: center - :alt: STM32F7508-DK - -More information about the board can be found at the `32F7508-DK website`_. - -Hardware -******** - -The STM32F7508-DK Discovery kit provides the following hardware components: - -- STM32F750N8H6 in BGA216 package -- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU -- 216 MHz max CPU frequency -- 64 KB Flash -- 320+16+4 KB SRAM -- GPIO with external interrupt capability -- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen -- 3x12-bit ADC -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (8) -- I2C (4) -- SPI (6) -- 2xSAI (serial audio interface) -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F750x8 can be found here: - -- `STM32F750x8 on www.st.com`_ -- `STM32F74xxx reference manual`_ - -Supported Features -================== - -The Zephyr stm32f7508_dk board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | Ethernet | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| LTDC | on-chip | display | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f7508_dk/stm32f7508_dk_defconfig`` - -Pin Mapping -=========== - -STM32F7508-DK Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F7508-DK board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The STM32F7508 Discovery kit features an Arduino Uno V3 connector. Board is -configured as follows - -- UART_1 TX/RX : PA9/PB7 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PC6/PC7 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SDMMC_1 D0/D1/D2/D3/CK/CD/CMD: PC8/PC9/PC10/PC11/PC12/PC13/PD2 -- SPI2 NSS/SCK/MISO/MOSI : PA8/PI1/PB14/PB15 (Arduino SPI) -- PWM_3_CH1 : PB4 -- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 -- USER_PB : PI11 -- LD1 : PI1 -- USB DM : PA11 -- USB DP : PA12 -- FMC SDRAM : - - - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 - - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 - - A14/A15 : PG4/PG5 - - SDNRAS/SDNCAS : PF11/PG15 - - NBL0/NBL1 : PE0/PE1 - - SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3 - -- LTDC : - - - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 - - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 - - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 - - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 - - -System Clock -============ - -The STM32F7508 System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven by the PLL -clock at 216MHz, driven by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32F7508-DK Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 -which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication -settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f7508_dk`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F7508-DK Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to STM32F7508-DK -------------------------------------------- - -First, connect the STM32F746G Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f7508_dk - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f7508_dk - :goals: debug - - -.. _32F7508-DK website: - https://www.st.com/en/evaluation-tools/stm32f7508-dk.html - -.. _32F7508-DK board User Manual: - https://www.st.com/resource/en/user_manual/dm00537062-discovery-kit-for-stm32f7-series-with-stm32f750n8-mcu-stmicroelectronics.pdf - -.. _STM32F750x8 on www.st.com: - https://www.st.com/resource/en/datasheet/stm32f750z8.pdf - -.. _STM32F74xxx reference manual: - https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/stm32f769i_disco/Kconfig.board b/boards/arm/stm32f769i_disco/Kconfig.board deleted file mode 100644 index 80c1b3ef5cb..00000000000 --- a/boards/arm/stm32f769i_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F769I Discovery board configuration - -# Copyright (c) 2018 Yong Jin -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F769I_DISCO - bool "STM32F769I Discovery Development Board" - depends on SOC_STM32F769XX diff --git a/boards/arm/stm32f769i_disco/Kconfig.defconfig b/boards/arm/stm32f769i_disco/Kconfig.defconfig deleted file mode 100644 index 8689d03c656..00000000000 --- a/boards/arm/stm32f769i_disco/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# STM32F769I DISCOVERY board configuration - -# Copyright (c) 2018 Yong Jin -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F769I_DISCO - -config BOARD - default "stm32f769i_disco" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -config INPUT - default y if LVGL - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_STM32F769I_DISCO diff --git a/boards/arm/stm32f769i_disco/doc/index.rst b/boards/arm/stm32f769i_disco/doc/index.rst deleted file mode 100644 index 203beb6f48a..00000000000 --- a/boards/arm/stm32f769i_disco/doc/index.rst +++ /dev/null @@ -1,225 +0,0 @@ -.. _stm32f769i_disco_board: - -ST STM32F769I Discovery -####################### - -Overview -******** - -The discovery kit enables a wide diversity of applications taking benefit -from audio, multi-sensor support, graphics, security, security, video, -and high-speed connectivity features. Important board features include: - -- STM32F769NIH6 microcontroller featuring 2 Mbytes of Flash memory and 512 Kbytes of RAM, in BGA216 package -- On-board ST-LINK/V2-1 supporting USB reenumeration capability -- USB ST-LINK functions: virtual COM port, mass storage, debug port -- Five power supply options: - - - ST LINK/V2-1 - - USB HS connector - - 5 V from RJ45 (Power Over Ethernet) - - 5 V from Arduino™ or external connector - - USB charger - -- 4-inch capacitive touch LCD display with MIPI-DSI connector -- SAI audio codec -- Two audio line jacks, one for input and one for output -- Stereo speaker outputs -- Four ST MEMS microphones on DFSDM inputs -- Two SPDIF RCA input and output connectors -- Two push-buttons (user and reset) -- 512-Mbit Quad-SPI Flash memory -- 128-Mbit SDRAM -- Connector for microSD card -- Wi-Fi or Ext-EEP daughterboard connector -- USB OTG HS with Micro-AB connector -- Ethernet connector compliant with IEEE-802.3-2002 -- Power Over Ethernet based on IEEE 802.3af (Powered Device, 48 V to 5 V, 3 W) -- Power supply output for external applications: 3.3 V or 5 V -- Arduino Uno V3 connectors -- Comprehensive free software including a variety of examples, part of the STM32Cube package -- Supported by a wide choice of integrated development environments - -.. image:: img/stm32f769i_disco.jpg - :align: center - :alt: STM32F769I-DISCO - -More information about the board can be found at the `32F769I-DISCO website`_. - -Hardware -******** - -The STM32F769I Discovery kit provides the following hardware components: - -- STM32F769NIH6 in BGA216 package -- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU -- 216 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 2 MB Flash -- 512 + 16 + 4 KB SRAM -- Flexible external memory controller with up to 32-bit data bus -- Dual mode Quad-SPI -- Chrom-ART Accelerator(DMA2D), graphical hardware accelerator enabling enhanced graphical user interface -- Hardware JPEG codec -- LCD-TFT controller supporting up to XGA resolution -- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- DMA Controller -- General Purpose Timers (15) -- Watchdog Timers (2) -- I2C (4) -- USART/UART (8) -- SPI (6) -- SAI (2) -- CAN (3) -- SDMMC (2) -- SPDIFRX interface -- HDMI-CEC -- MDIO slave interface -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII -- 8- to 14-bit camera interface up to 54 Mbyte/s -- True random number generator -- CRC calculation unit -- RTC: sub-second accuracy, hardware calendar -- 96-bit unique ID - -More information about STM32F769NIH6 can be found here: - -- `STM32F769NIH6 on www.st.com`_ -- `STM32F76xxx reference manual`_ - -Supported Features -================== - -The Zephyr stm32f769i_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | Ethernet | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | flash | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| TOUCH | off-chip | ft5336(FT6202) | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f769i_disco/stm32f769i_disco_defconfig`` - -Pin Mapping -=========== - -STM32F769I Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F769I-DISCO board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PC6/PC7 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C4 SCL/SDA : PD12/PB7 (Touchscreen FT6202, PI13 Interrupt Pin) -- SPI2 SCK/MISO/MOSI : PA12/PB14/PB15 (Arduino SPI) -- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 -- LD1 : PJ13 -- LD2 : PJ5 -- LD3 : PA12 -- LD4 : PD4 - -System Clock -============ - -The STM32F769I System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven by the PLL -clock at 216MHz, driven by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32F769I Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 -which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication -settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f769i_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F769I Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to STM32F769I -------------------------------------------- - -First, connect the STM32F769I Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f769i_disco - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f769i_disco - :goals: debug - - -.. _32F769I-DISCO website: - https://www.st.com/en/evaluation-tools/32f769idiscovery.html - -.. _32F769I-DISCO board User Manual: - https://www.st.com/resource/en/user_manual/dm00276557.pdf - -.. _STM32F769NIH6 on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x9/stm32f769ni.html - -.. _STM32F76xxx reference manual: - https://www.st.com/resource/en/reference_manual/dm00224583.pdf diff --git a/boards/arm/stm32g0316_disco/Kconfig.board b/boards/arm/stm32g0316_disco/Kconfig.board deleted file mode 100644 index 3f00f126fe3..00000000000 --- a/boards/arm/stm32g0316_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32G0316 Discovery board configuration - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32G0316_DISCO - bool "STM32G0316 Discovery Development Board" - depends on SOC_STM32G031XX diff --git a/boards/arm/stm32g0316_disco/Kconfig.defconfig b/boards/arm/stm32g0316_disco/Kconfig.defconfig deleted file mode 100644 index 3016470eb56..00000000000 --- a/boards/arm/stm32g0316_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32G0316 Discovery board configuration - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32G0316_DISCO - -config BOARD - default "stm32g0316_disco" - -endif # BOARD_STM32G0316_DISCO diff --git a/boards/arm/stm32g0316_disco/doc/index.rst b/boards/arm/stm32g0316_disco/doc/index.rst deleted file mode 100644 index ed68a7b5dd4..00000000000 --- a/boards/arm/stm32g0316_disco/doc/index.rst +++ /dev/null @@ -1,134 +0,0 @@ -.. _stm32g0316_disco_board: - -ST STM32G0316 Discovery -####################### - -Overview -******** - -The STM32G0316-DISCO Discovery kit helps to discover features of STM32G0 in SO8 package. -This discovery kit offers an SO8 to DIL8 module designed with the STM32G031J6 microcontroller -and allows the user to develop applications. It includes an on-board ST-LINK/V2-1 to debug -and program the embedded STM32 microcontroller. - -.. image:: img/stm32g0316_disco.jpg - :align: center - :alt: STM32G0316-DISCO - -Hardware -******** - -- STM32G031J6 Arm |reg| Cortex |reg|-M0+ core-based microcontroller, - featuring 32 Kbytes of Flash memory and 8 Kbytes of SRAM, in an SO8 package -- 1 user LED -- 1 reset/user push-button -- Individual and breakable STM32 SO8 to DIL8 module -- ST-LINK Micro-B USB connector -- DIL8 socket to ease programming of the STM32 MCU -- On-board ST-LINK/V2-1 debugger/programmer - -For more information about the STM32G03x SoC and the STM32G0316-DISCO board, see these ST reference documents: - -- `STM32G031J6 website`_ -- `STM32G031 datasheet`_ -- `STM32G0x1 reference manual`_ -- `STM32G0316-DISCO website`_ - -Supported Features -================== - -The Zephyr stm32g0316_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32g0316_disco/stm32g0316_disco_defconfig`` - -Connections and IOs -=================== - -Due to the small number of I/O pins on the SO8 package, multiple die I/Os are bonded -to the same package pins to maximize the number of peripherals which can be used. -Care must be taken not to set two I/Os which are connected together to conflicting -states (e.g. both as outputs, one low, the other high). - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1 TX/RX : PA9/PB7 (pins 5/1) -- USER_PB : PA0 (pin 4) -- LD2 : PA12 (pin 6) - -Programming and Debugging -************************* - -Applications for the ``stm32g0316_disco`` board configuration can be built the -usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). - -Flashing -======== - -The STM32G0316-DISCO board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is not yet supported by the openocd version included in -the Zephyr SDK. Instead, support can be enabled on pyocd by adding "pack" support with -the following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32g031j6 - -Flashing an application to the STM32G0316-DISCO ------------------------------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32g0316_disco - :goals: build flash - -You should see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32g0316_disco - :maybe-skip-config: - :goals: debug - -.. _STM32G031J6 website: - https://www.st.com/en/microcontrollers-microprocessors/stm32g031j6.html - -.. _STM32G031 datasheet: - https://www.st.com/resource/en/datasheet/stm32g031j6.pdf - -.. _STM32G0x1 reference manual: - https://www.st.com/resource/en/reference_manual/dm00371828.pdf - -.. _STM32G0316-DISCO website: - https://www.st.com/en/evaluation-tools/stm32g0316-disco.html diff --git a/boards/arm/stm32g071b_disco/Kconfig.board b/boards/arm/stm32g071b_disco/Kconfig.board deleted file mode 100644 index 897dcce606d..00000000000 --- a/boards/arm/stm32g071b_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32G071B Discovery board configuration - -# Copyright 2021 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32G071B_DISCO - bool "STM32G071B Discovery Board" - depends on SOC_STM32G071XX diff --git a/boards/arm/stm32g071b_disco/Kconfig.defconfig b/boards/arm/stm32g071b_disco/Kconfig.defconfig deleted file mode 100644 index 195b8ecdf4f..00000000000 --- a/boards/arm/stm32g071b_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32G071B Discovery board configuration - -# Copyright 2021 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32G071B_DISCO - -config BOARD - default "stm32g071b_disco" - -endif # BOARD_STM32G071B_DISCO diff --git a/boards/arm/stm32g071b_disco/doc/index.rst b/boards/arm/stm32g071b_disco/doc/index.rst deleted file mode 100644 index 2c9cbea3176..00000000000 --- a/boards/arm/stm32g071b_disco/doc/index.rst +++ /dev/null @@ -1,169 +0,0 @@ -.. _stm32g071b_disco_board: - -ST STM32G071B Discovery -####################### - -Overview -******** -The STM32G071B-DISCO Discovery board is a demonstration and development platform -for the STMicroelectronics Arm® Cortex® -M0+ core-based STM32G071RB USB Type-C™ -and Power Delivery microcontroller. The STM32G071B-DISCO Discovery board is -presented with all necessary interfaces for easy connection and -interoperability with other USB Type-C™ devices. The STM32G071B-DISCO Discovery -board is intended for discovery and display of USB Type-C™ port characteristics -such as data role, power role, VBUS and IBUS monitoring. It offers an advanced -user mode when associated with the STM32CubeMonUCPD software GUI and can be used -as a USB Type-C™ and Power Delivery analyzer. - -- STM32G071RBT6 microcontroller featuring 128 Kbytes of Flash memory and - 32 Kbytes of RAM in LQFP64 package -- Plastic case -- 1” 128 x 64 pixels OLED LCD module with SPI interface -- USB Type-C™ interface plug cable and receptacle connector accessible by door - with reed sensor detection -- 3 bidirectional current and power monitors with I2C interface to measure VBUS, - CC1 and CC2 protected and isolated lines -- On-board DC/DC converter to sustain power supply with VBUS varying from 3 V to - 20 V (+/- 5 %) -- 4 user status LEDs about USB Type-C™ configuration -- 3 LEDs for power and ST-LINK communication -- 4-way joystick with selection button -- 1 reset push-button -- Board external connectors: - - USB Type-C™ plug cable - - USB Type-C™ receptacle connector - - 8-pin user extension connector including ADC, SPI, USART and - I2C communication signals - - USB with Micro-AB (ST-LINK) -- Board internal connectors: - - 2 x 8-pin GPIOs free pins from microcontroller - (accessible internally when case is removed) - - USB Type-C™ test points for main signals -- Flexible power-supply options: ST-LINK USB VBUS or USB Type-C™ VBUS -- On-board ST-LINK/V2-1 debugger/programmer with USB enumeration capability: - mass storage, Virtual COM port and debug port - -.. image:: img/stm32g071b_disco.jpg - :align: center - :alt: STM32G071B-DISCO - -More information about the board can be found at the `STM32G071B-DISCO website`_. - - -More information about STM32G071RB can be found here: -- `G071RB on www.st.com`_ -- `STM32G071 reference manual`_ - - -Supported Features -================== - -The Zephyr stm32g071b_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| UCPD | on-chip | ucpd | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32g071b_disco/stm32g071b_disco_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) -- UCPD1 : PA8/PB15 -- BUTTON (JOY_SEL) : PC0 -- BUTTON (JOY_LEFT) : PC1 -- BUTTON (JOY_DOWN) : PC2 -- BUTTON (JOY_RIGHT) : PC3 -- BUTTON (JOY_UP) : PC4 -- LED (TO_REC) : PD9 -- LED (TO_PLUG) : PD8 -- LED (SINK_SPY) : PD5 -- LED (SOURCE) : PC12 -- ENCC1 : PB10 (Enable CC1) -- ENCC2 : PB11 (Enable CC2) -- RDCC1 : PB12 (Enable Door Sense on CC1) - - -For more details please refer to `STM32G0 Discovery board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``stm32g071b_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -The STM32G071B Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. - -.. code-block:: console - - $ west flash - -Flashing an application to the STM32G071B_DISCO ------------------------------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32g071b_disco - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32g071b_disco - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32G071B-DISCO website: - https://www.st.com/en/evaluation-tools/stm32g071b-disco.html - -.. _STM32G071 reference manual: - https://www.st.com/resource/en/reference_manual/dm00371828.pdf - -.. _STM32G0 Discovery board User Manual: - https://www.st.com/resource/en/user_manual/dm00496511.pdf - -.. _G071RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32g071rb.html diff --git a/boards/arm/stm32g081b_eval/Kconfig.board b/boards/arm/stm32g081b_eval/Kconfig.board deleted file mode 100644 index 2f2299670f5..00000000000 --- a/boards/arm/stm32g081b_eval/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32G081B Evaluation board configuration - -# Copyright 2021 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32G081B_EVAL - bool "STM32G081B Evaluation Board" - depends on SOC_STM32G081XX diff --git a/boards/arm/stm32g081b_eval/Kconfig.defconfig b/boards/arm/stm32g081b_eval/Kconfig.defconfig deleted file mode 100644 index 548b4d75cc1..00000000000 --- a/boards/arm/stm32g081b_eval/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32G081B evaluation board configuration - -# Copyright 2021 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32G081B_EVAL - -config BOARD - default "stm32g081b_eval" - -endif # BOARD_STM32G081B_EVAL diff --git a/boards/arm/stm32g081b_eval/doc/index.rst b/boards/arm/stm32g081b_eval/doc/index.rst deleted file mode 100644 index 970ec32dd0a..00000000000 --- a/boards/arm/stm32g081b_eval/doc/index.rst +++ /dev/null @@ -1,207 +0,0 @@ -.. _stm32g081b_eval_board: - -ST STM32G081B Evaluation -######################## - -Overview -******** -The STM32G081B-EVAL Evaluation board is a high-end development platform, for -Arm Cortex-M0+ core-based STM32G081RBT6 microcontroller, with USB Type-C and -power delivery controller interfaces (UCPD), compliant with USB type-C r1.2 -and USB PD specification r3.0, two I2Cs, two SPIs, five USARTs, one LP UART, -one 12-bit ADC, two 12-bit DACs, two GP comparators, two LP timers, internal -32 KB SRAM and 128 KB Flash, CEC, SWD debugging support. The full range of -hardware features on the STM32G081B-EVAL Evaluation board includes a mother -board, a legacy peripheral daughterboard and a USB-C and Power Delivery -daughterboard, which help to evaluate all peripherals (USB Type-C connector -with USB PD, motor control connector, RS232, RS485, Audio DAC, microphone ADC, -TFT LCD, IrDA, IR LED, IR receiver, LDR, MicroSD card, CEC on two HDMI -connectors, smart card slot, RF E2PROM & Temperature sensor…), and to develop -applications. - -The board integrates an ST-LINK/V2-1 as an embedded in-circuit debugger and -programmer for the STM32 MCU. The daughterboard and extension connectors -provide an easy way to connect a daughterboard or wrapping board for the -user's specific applications. - -The USB-C and Power Delivery daughterboard -features two independent USB-C ports controlled by an STM32G0. USB-C port 1 -is dual role power (DRP) and can provide up-to 45 W. USB-C Port 2 is sink -only. Both support USB PD protocol and alternate mode functionality. - -Application firmware examples are provided to evaluate the USB-C technology -through various use cases. - - - -- Mother board - - STM32G081RBT6 microcontroller with 128 Kbytes of Flash memory and - 32 Kbytes of RAM in LQFP64 package - - MCU voltage choice fixed 3.3 V or adjustable from 1.65 V to 3.6 V - - I2C compatible serial interface - - RTC with backup battery - - 8-Gbyte or more SPI interface microSD card - - Potentiometer - - 4 color user LEDs and one LED as MCU low-power alarm - - Reset, Tamper and User buttons - - 4-direction control and selection joystick - - Board connectors: - - 5 V power jack - - RS-232 and RS485 communications - - Stereo audio jack including analog microphone input - - microSD card - - Extension I2C connector - - Motor-control connector - - Board extension connectors: - - Daughterboard connectors for legacy peripheral daughter board or - USB-C daughterboard - - Extension connectors for daughterboard or wire-wrap board - - Flexible power-supply options: - - 5 V power jack - - ST-LINK/V2-1 USB connector - - Daughterboard - - On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration - capability: mass storage, virtual COM port and debug port - - Legacy peripheral daughterboard - - IrDA transceiver - - IR LED and IR receiver - - Light dependent resistor (LDR) - - Temperature Sensor - - Board connectors: - - Two HDMI connectors with DDC and CEC - - Smart card slot - - USB-C and Power Delivery daughterboard - - Mux for USB3.1 Gen1 / DisplayPort input and Type-C port1 output - - Mux for Type-C port2 input and DisplayPort output / USB2.0 - - VCONN on Type-C port1 - - USB PD on Type-C port1 - - Board connectors: - - Type-C port1 DRP (dual-role port) - - Type-C port2 Sink - - DisplayPort input - - DisplayPort output - - USB 3.1 Gen1 Type-B receptacle - - USB2.0 Type-A receptacle - - 19 V power jack for USB PD - -.. image:: img/stm32g081b_eval.jpg - :align: center - :alt: STM32G081B-EVAL - -More information about the board can be found at the `STM32G081B-EVAL website`_. - - -More information about STM32G081RB can be found here: -- `G081RB on www.st.com`_ -- `STM32G081 reference manual`_ - - -Supported Features -================== - -The Zephyr stm32g081b_eval board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| UCPD | on-chip + ucpd | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32g081b_eval/stm32g081b_eval_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) -- UCPD2 : PD0/PD2 -- BUTTON (JOY_SEL) : PA0 -- BUTTON (JOY_LEFT) : PC8 -- BUTTON (JOY_DOWN) : PC3 -- BUTTON (JOY_RIGHT) : PC7 -- BUTTON (JOY_UP) : PC2 -- VBUS DISCHARGE : PB14 -- LED1 : PD5 -- LED2 : PD6 -- LED3 : PD8 -- LED4 : PD9 - -For more details please refer to `STM32G0 Evaluation board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``stm32g081b_eval`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -The STM32G081B Evaluation board includes an ST-LINK/V2-1 embedded debug tool interface. - -.. code-block:: console - - $ west flash - -Flashing an application to the STM32G081B_EVAL ----------------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32g081b_eval - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32g081b_eval - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32G081B-EVAL website: - https://www.st.com/en/evaluation-tools/stm32g081b-eval.html - -.. _STM32G081 reference manual: - https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32G0 Evaluation board User Manual: - https://www.st.com/resource/en/user_manual/um2403-evaluation-board-with-stm32g081rb-mcu-stmicroelectronics.pdf - -.. _G081RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32g081rb.html diff --git a/boards/arm/stm32h573i_dk/Kconfig.board b/boards/arm/stm32h573i_dk/Kconfig.board deleted file mode 100644 index adb46f39300..00000000000 --- a/boards/arm/stm32h573i_dk/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# STM32H573I-DK Discovery kit board configuration -# -# Copyright (c) 2023 STMicroelectronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_STM32H573I_DK - bool "STM32H573I-DK Discovery Development Board" - depends on SOC_STM32H573XX diff --git a/boards/arm/stm32h573i_dk/Kconfig.defconfig b/boards/arm/stm32h573i_dk/Kconfig.defconfig deleted file mode 100644 index d9bf4c72289..00000000000 --- a/boards/arm/stm32h573i_dk/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# STM32H573I DISCOVERY KIT board configuration -# -# Copyright (c) 2023 STMicroelectronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_STM32H573I_DK - -config BOARD - default "stm32h573i_dk" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_STM32H573I_DK diff --git a/boards/arm/stm32h573i_dk/doc/index.rst b/boards/arm/stm32h573i_dk/doc/index.rst deleted file mode 100644 index db83ec2f7a2..00000000000 --- a/boards/arm/stm32h573i_dk/doc/index.rst +++ /dev/null @@ -1,326 +0,0 @@ -.. _stm32h573i_dk_board: - -ST STM32H573I-DK Discovery -########################## - -Overview -******** - -The STM32H573I-DK Discovery kit is designed as a complete demonstration and -development platform for STMicroelectronics Arm |reg| Cortex |reg|-M33 core-based -STM32H573IIK3Q microcontroller with TrustZone |reg|. Here are some highlights of -the STM32H573I-DK Discovery board: - - -- STM32H573IIK3Q microcontroller featuring 2 Mbytes of Flash memory and 640 Kbytes of SRAM in 176-pin BGA package -- 1.54-inch 240x240 pixels TFT-LCD with LED backlight and touch panel -- USB Type-C |trade| Host and device with USB power-delivery controller -- SAI Audio DAC stereo with one audio jacks for input/output, -- ST MEMS digital microphone with PDM interface -- Octo-SPI interface connected to 512Mbit Octo-SPI NORFlash memory device (MX25LM51245GXDI00 from MACRONIX) -- 10/100-Mbit Ethernet, -- microSD |trade| -- A Wi‑Fi® add-on board -- Board connectors - - - STMod+ expansion connector with fan-out expansion board for Wi‑Fi |reg|, Grove and mikroBUS |trade| compatible connectors - - Pmod |trade| expansion connector - - Audio MEMS daughterboard expansion connector - - ARDUINO |reg| Uno V3 expansion connector - -- Flexible power-supply options - - - ST-LINK - - USB VBUS - - external sources - -- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: - - - mass storage - - Virtual COM port - - debug port - -- 4 user LEDs -- User and reset push-buttons - -.. image:: img/stm32h573i_dk.jpg - :align: center - :alt: STM32H573I-DK Discovery - -More information about the board can be found at the `STM32H573I-DK Discovery website`_. - -Hardware -******** - -The STM32H573xx devices are an high-performance microcontrollers family (STM32H5 -Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. -They operate at a frequency of up to 250 MHz. - -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 375 DMPIS/MHz (Dhrystone 2.1) - -- Security - - - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension - - Up to 8 configurable SAU regions - - TrustZone |reg| aware and securable peripherals - - Flexible lifecycle scheme with secure debug authentication - - Preconfigured immutable root of trust (ST-iROT) - - SFI (secure firmware installation) - - Secure data storage with hardware unique key (HUK) - - Secure firmware upgrade support with TF-M - - 2x AES coprocessors including one with DPA resistance - - Public key accelerator, DPA resistant - - On-the-fly decryption of Octo-SPI external memories - - HASH hardware accelerator - - True random number generator, NIST SP800-90B compliant - - 96-bit unique ID - - Active tampers - - True Random Number Generator (RNG) NIST SP800-90B compliant - -- Clock management: - - - 25 MHz crystal oscillator (HSE) - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 64 MHz (HSI) trimmable by software - - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) - - Internal 4 MHz oscillator (CSI), trimmable by software - - Internal 48 MHz (HSI48) with recovery system - - 3 PLLs for system clock, USB, audio, ADC - -- Power management - - - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry - - Embedded SMPS step-down converter - -- RTC with HW calendar, alarms and calibration -- Up to 139 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V -- Up to 16 timers and 2 watchdogs - - - 12x 16-bit - - 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - - 6x 16-bit low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- Memories - - - Up to 2 MB Flash, 2 banks read-while-write - - 1 Kbyte OTP (one-time programmable) - - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC - - 4 Kbytes of backup SRAM available in the lowest power modes - - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories - - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats - - 2x SD/SDIO/MMC interfaces - -- Rich analog peripherals (independent supply) - - - 2x 12-bit ADC with up to 5 MSPS in 12-bit - - 2x 12-bit D/A converters - - 1x Digital temperature sensor - -- 34x communication interfaces - - - 1x USB Type-C / USB power-delivery controller - - 1x USB 2.0 full-speed host and device - - 4x I2C FM+ interfaces (SMBus/PMBus) - - 1x I3C interface - - 12x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) - - 1x LP UART - - 6x SPIs including 3 muxed with full-duplex I2S - - 5x additional SPI from 5x USART when configured in Synchronous mode - - 2x SAI - - 2x FDCAN - - 1x SDMMC interface - - 2x 16 channel DMA controllers - - 1x 8- to 14- bit camera interface - - 1x HDMI-CEC - - 1x Ethernel MAC interface with DMA controller - - 1x 16-bit parallel slave synchronous-interface - -- CORDIC for trigonometric functions acceleration -- FMAC (filter mathematical accelerator) -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32H573 can be found here: - -- `STM32H573 on www.st.com`_ -- `STM32H573 reference manual`_ - -Supported Features -================== - -The Zephyr STM32H573I_DK board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | Real Time Clock | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi bus | -+-----------+------------+-------------------------------------+ -| OCTOSPI | on-chip | octospi | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can bus | -+-----------+------------+-------------------------------------+ -| AES | on-chip | crypto | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB full-speed host/device bus | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig and dts files: - -- Secure target: - - - :zephyr_file:`boards/arm/stm32h573i_dk/stm32h573i_dk_defconfig` - - :zephyr_file:`boards/arm/stm32h573i_dk/stm32h573i_dk.dts` - -Zephyr board options -==================== - -The STM32H573 is an SoC with Cortex-M33 architecture. Zephyr provides support -for building for Secure firmware. - -The BOARD options are summarized below: - -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| stm32h573i_dk | For building Secure firmware | -+----------------------+-----------------------------------------------+ - -Connections and IOs -=================== - -STM32H573I-DK Discovery Board has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32H573I-DK Discovery board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- USART_1 TX/RX : PA9/PA10 (VCP) -- USART_3 TX/RX : PB11/PB10 (Arduino USART3) -- USER_PB : PC13 -- LD1 (green) : PI9 -- DAC1 channel 1 output : PA4 -- ADC1 channel 6 input : PF12 - -System Clock ------------- - -STM32H573I-DK System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at -240MHz, driven by 25MHz external oscillator (HSE). - -Serial Port ------------ - -STM32H573I-DK Discovery board has 3 U(S)ARTs. The Zephyr console output is -assigned to USART1. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``stm32h573i_dk`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32H573I-DK Discovery board includes an ST-LINK/V3E embedded debug tool -interface. Support is available on STM32CubeProgrammer V2.13.0. - -Alternatively, this interface will be supported by a next openocd version. - -Flashing an application to STM32H573I-DK Discovery --------------------------------------------------- - -Connect the STM32H573I-DK Discovery to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h573i_dk - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! stm32h573i_dk - -Debugging -========= - -Waiting for openocd support, debugging could be performed with pyocd which -requires to enable "pack" support with the following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32h5 - -Once installed, you can debug an application in the usual way. Here is an -example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h573i_dk - :maybe-skip-config: - :goals: debug - -.. _STM32H573I-DK Discovery website: - https://www.st.com/en/evaluation-tools/stm32h573i-dk.html - -.. _STM32H573I-DK Discovery board User Manual: - https://www.st.com/en/evaluation-tools/stm32h573i-dk.html - -.. _STM32H573 on www.st.com: - https://www.st.com/en/microcontrollers/stm32h573ii.html - -.. _STM32H573 reference manual: - https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32h735g_disco/Kconfig.board b/boards/arm/stm32h735g_disco/Kconfig.board deleted file mode 100644 index 78a8af8bc01..00000000000 --- a/boards/arm/stm32h735g_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H735G Discovery board configuration - -# Copyright (c) 2021 SILA Embedded Solutions GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32H735G_DISCO - bool "STM32H735G Discovery Development Board" - depends on SOC_STM32H735XX diff --git a/boards/arm/stm32h735g_disco/Kconfig.defconfig b/boards/arm/stm32h735g_disco/Kconfig.defconfig deleted file mode 100644 index 72308958d7b..00000000000 --- a/boards/arm/stm32h735g_disco/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# STM32H735G DISCOVERY board configuration - -# Copyright (c) 2021 SILA Embedded Solutions GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32H735G_DISCO - -config BOARD - default "stm32h735g_disco" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_STM32H735G_DISCO diff --git a/boards/arm/stm32h735g_disco/doc/index.rst b/boards/arm/stm32h735g_disco/doc/index.rst deleted file mode 100644 index e4bf324650b..00000000000 --- a/boards/arm/stm32h735g_disco/doc/index.rst +++ /dev/null @@ -1,152 +0,0 @@ -.. _stm32h735g_disco_board: - -ST STM32H735G Discovery -####################### - -Overview -******** - -The STM32H735G-DK Discovery kit is a complete demonstration and development -platform for Arm® Cortex®-M7 core-based STM32H735IGK6U microcontroller, with -1 Mbyte of Flash memory and 564 Kbytes of SRAM. - -The STM32H735G-DK Discovery kit is used as a reference design for user -application development before porting to the final product, thus simplifying -the application development. - -The full range of hardware features available on the board helps users to enhance -their application development by an evaluation of all the peripherals (such as -USB OTG FS, Ethernet, microSD™ card, USART, CAN FD, SAI audio DAC stereo with -audio jack input and output, MEMS digital microphone, HyperRAM™, -Octo-SPI Flash memory, RGB interface LCD with capacitive touch panel, and others). -ARDUINO® Uno V3, Pmod™ and STMod+ connectors provide easy connection to extension -shields or daughterboards for specific applications. - -STLINK-V3E is integrated into the board, as the embedded in-circuit debugger and -programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H735G-DK board -comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive -software HAL library as well as various software examples. - -.. image:: img/stm32h735g_disco.jpg - :align: center - :alt: STM32H735G-DISCO - -More information about the board can be found at the `STM32H735G-DISCO website`_. -More information about STM32H735 can be found here: - -- `STM32H725/735 on www.st.com`_ -- `STM32H735xx reference manual`_ -- `STM32H735xx datasheet`_ - -Supported Features -================== - -The current Zephyr stm32h735g_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| FDCAN1 | on-chip | CAN-FD Controller | -+-----------+------------+-------------------------------------+ -| FDCAN2 | on-chip | CAN-FD Controller | -+-----------+------------+-------------------------------------+ -| FDCAN2 | on-chip | CAN-FD Controller (disabled by | -| | | default. Solder bridges SB29 and | -| | | SB30 need to be closed for FDCAN3 | -| | | to work) | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration per core can be found in the defconfig file: -``boards/arm/stm32h735g_disco/stm32h735g_disco_defconfig`` - -Pin Mapping -=========== - -For more details please refer to `STM32H735G-DISCO website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_7 TX/RX : PF7/PF6 (Arduino Serial) -- LD1 : PC2 -- LD2 : PC3 -- FDCAN1 : CAN - -System Clock -============ - -The STM32H735G System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock -is driven by the PLL clock at 550MHz. PLL clock is feed by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32H735G Discovery kit has up to 6 UARTs. -The Zephyr console output is assigned to UART3 which connected to the onboard ST-LINK/V3.0. Virtual -COM port interface. Default communication settings are 115200 8N1. - - -Programming and Debugging -************************* - -See :ref:`build_an_application` for more information about application builds. - - -Flashing -======== - -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. -It is advised to use `STM32CubeProgrammer`_ to check and update option bytes -configuration and flash the ``stm32h735g_disco`` target. - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h735g_disco - :goals: debug - - -.. _STM32H735G-DISCO website: - https://www.st.com/en/evaluation-tools/stm32h735g-dk.html - -.. _STM32H725/735 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h725-735.html - -.. _STM32H735xx reference manual: - https://www.st.com/resource/en/reference_manual/dm00603761-stm32h723733-stm32h725735-and-stm32h730-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32H735xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h735ag.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32h747i_disco/Kconfig.board b/boards/arm/stm32h747i_disco/Kconfig.board deleted file mode 100644 index 819e6f08a60..00000000000 --- a/boards/arm/stm32h747i_disco/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# STM32H747I Discovery board configuration - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32H747I_DISCO_M7 - bool "STM32H747I Discovery Development Board" - depends on SOC_STM32H747XX - select CPU_CORTEX_M7 - -config BOARD_STM32H747I_DISCO_M4 - bool "STM32H747I Discovery Development Board" - depends on SOC_STM32H747XX - select CPU_CORTEX_M4 diff --git a/boards/arm/stm32h747i_disco/Kconfig.defconfig b/boards/arm/stm32h747i_disco/Kconfig.defconfig deleted file mode 100644 index b9c3ba7161a..00000000000 --- a/boards/arm/stm32h747i_disco/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# STM32H747I DISCOVERY board configuration - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32H747I_DISCO_M7 || BOARD_STM32H747I_DISCO_M4 - -config BOARD - default "stm32h747i_disco_m7" if BOARD_STM32H747I_DISCO_M7 - default "stm32h747i_disco_m4" if BOARD_STM32H747I_DISCO_M4 - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_STM32H747I_DISCO_M7 diff --git a/boards/arm/stm32h747i_disco/board.cmake b/boards/arm/stm32h747i_disco/board.cmake deleted file mode 100644 index 00da755afb0..00000000000 --- a/boards/arm/stm32h747i_disco/board.cmake +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_STM32H747I_DISCO_M7) -board_runner_args(jlink "--device=STM32H747ZI_M7") -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m7.cfg") -board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) -elseif(CONFIG_BOARD_STM32H747I_DISCO_M4) -board_runner_args(jlink "--device=STM32H747ZI_M4") -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m4.cfg") -board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) -endif() -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/stm32h747i_disco/doc/index.rst b/boards/arm/stm32h747i_disco/doc/index.rst deleted file mode 100644 index fa668e964c7..00000000000 --- a/boards/arm/stm32h747i_disco/doc/index.rst +++ /dev/null @@ -1,313 +0,0 @@ -.. _stm32h747i_disco_board: - -ST STM32H747I Discovery -####################### - -Overview -******** - -The discovery kit enables a wide diversity of applications taking benefit -from audio, multi-sensor support, graphics, security, video, -and high-speed connectivity features. - -The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU, -with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, -large set of peripherals, SMPS, and MIPI-DSI. - -Additionally, the board features: - -- On-board ST-LINK/V3E supporting USB reenumeration capability -- USB ST-LINK functions: virtual COM port, mass storage, debug port -- Flexible power-supply options: - - - ST-LINK USB VBUS, USB OTG HS connector, or external sources - -- 4” capacitive touch LCD display module with MIPI® DSI interface -- Ethernet compliant with IEEE802.3-2002 -- USB OTG HS -- Stereo speaker outputs -- ST-MEMS digital microphones -- 2 x 512-Mbit QUAD-SPI NOR Flash memory -- 256-Mbit SDRAM -- 4 color user LEDs -- 1 user and reset push-button -- 4-direction joystick with selection button -- Arduino Uno V3 connectors - -.. image:: img/stm32h747i_disco.jpg - :align: center - :alt: STM32H747I-DISCO - -More information about the board can be found at the `STM32H747I-DISCO website`_. -More information about STM32H747XIH6 can be found here: - -- `STM32H747XI on www.st.com`_ -- `STM32H747xx reference manual`_ -- `STM32H747xx datasheet`_ - -Supported Features -================== - -The current Zephyr stm32h747i_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet (*) | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | MIPI DSI Host with shield (MP1166) | -| | | st_b_lcd40_dsi1_mb1166 | -+-----------+------------+-------------------------------------+ - -(*) From UM2411 Rev 4: - With the default setting, the Ethernet feature is not working because of - a conflict between ETH_MDC and SAI4_D1 of the MEMs digital microphone. - Make sure you have SB8 closed and SB21 open to get Ethernet working. - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration per core can be found in the defconfig files: -``boards/arm/stm32h747i_disco/stm32h747i_disco_defconfig_m7`` and -``boards/arm/stm32h747i_disco/stm32h747i_disco_defconfig_m4`` - -Pin Mapping -=========== - -STM32H747I Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32H747I-DISCO website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) -- UART_8 TX/RX : PJ8/PJ9 (Arduino Serial) -- SPI_5 NSS/SCK/MISO/MOSI : PK1/PK0/PJ11/PJ10 (Arduino SPI) -- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2 -- LD1 : PI12 -- LD2 : PI13 -- LD3 : PI14 -- LD4 : PI15 -- W-UP : PC13 -- J-CENTER : PK2 -- J-DOWN : PK3 -- J-LEFT : PK4 -- J-RIGHT : PK5 -- J-UP : PK6 - -System Clock -============ - -The STM32H747I System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the CPU1 (Cortex-M7) System clock -is driven by the PLL clock at 400MHz, and the CPU2 (Cortex-M4) System clock -is driven at 200MHz. PLL clock is feed by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32H747I Discovery kit has up to 8 UARTs. -Default configuration assigns USART1 and UART8 to the CPU1. The Zephyr console -output is assigned to UART1 which connected to the onboard ST-LINK/V3.0. Virtual -COM port interface. Default communication settings are 115200 8N1. - -Ethernet -======== - -**Disclaimer:** This section is mostly copy-paste of corresponding -`DISCO_H747I modifications for Ethernet`_ mbed blog post. The author of this -article sincerely allowed to use the images and his knowledge about necessary -HW modifications to get Ethernet working with this board. - -To get Ethernet working following HW modifications are required: - -- **SB21**, **SB45** and **R87** should be opened -- **SB22**, **SB44**, **SB17** and **SB8** should be closed - -Following two images shows necessary changes on the board marked: - -.. image:: img/disco_h747i_ethernet_modification_1.jpg - :align: center - :alt: STM32H747I-DISCO - Ethernet modification 1 (**SB44**, **SB45**) - -.. image:: img/disco_h747i_ethernet_modification_2.jpg - :align: center - :alt: STM32H747I-DISCO - Ethernet modification 2 (**SB21**, **R87**, **SB22**, **SB17** and **SB8**) - -Display -======= - -The STM32H747I Discovery kit has a dedicated DSI LCD connector **CN15**, where -the MB1166 (B-LCD40-DSI1) display extension board can be mounted. Enable display -support in Zephyr by adding the shield ``st_b_lcd40_dsi1_mb1166`` to your build -command, for example: - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/display - :board: stm32h747i_disco_m7 - :shield: st_b_lcd40_dsi1_mb1166 - :goals: build flash - -.. note:: - Currently only the older version MB1166-A03 is supported by Zephyr. - The newer version MB1166-A09 does not get initialized correctly (see :github:`60888`). - -Resources sharing -================= - -The dual core nature of STM32H747 SoC requires sharing HW resources between the -two cores. This is done in 3 ways: - -- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only - has access to bus clock activation and deactivation. -- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in - devicetree before compilation. The user must ensure peripherals are not assigned - to both cores at the same time. -- **Run time protection**: Interrupt-controller and GPIO configurations could be - accessed by both cores at run time. Accesses are protected by a hardware semaphore - to avoid potential concurrent access issues. - -Programming and Debugging -************************* - -Applications for the ``stm32h747i_disco`` board should be built per core target, -using either ``stm32h747i_disco_m7`` or ```stm32h747i_disco_m4`` as the target. -See :ref:`build_an_application` for more information about application builds. - -.. note:: - - If using OpenOCD you will need a recent development version as the last - official release does not support H7 dualcore yet. - Also, with OpenOCD, sometimes, flashing is not working. It is necessary to - erase the flash (with STM32CubeProgrammer for example) to make it work again. - Debugging with OpenOCD is currently working for this board only with Cortex M7, - not Cortex M4. - - -Flashing -======== - -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. -It is advised to use `STM32CubeProgrammer`_ to check and update option bytes -configuration and flash ``stm32h747i_disco_m7`` and ``stm32h747i_disco_m4`` targets. - -By default: - - - CPU1 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0) - - CPU2 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0) - -Also, default out of the box board configuration enables CM7 and CM4 boot when -board is powered (Option bytes BCM7 and BCM4 are checked). -It is possible to change Option Bytes so that CM7 boots first in stand alone, -and CM7 will wakeup CM4 after clock initialization. -Drivers are able to take into account both Option Bytes configurations -automatically. - -Zephyr flash configuration has been set to meet these default settings. - -Alternatively, west `STM32CubeProgrammer`_ runner can be used, after installing -it, to flash applications for both cores. The target core is detected automatically. - -.. code-block:: console - - $ west flash --runner stm32cubeprogrammer - -Flashing an application to STM32H747I M7 Core ---------------------------------------------- - -First, connect the STM32H747I Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h747i_disco_m7 - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! stm32h747i_disco_m7 - -.. note:: - Sometimes, flashing is not working. It is necessary to erase the flash - (with STM32CubeProgrammer for example) to make it work again. - -Similarly, you can build and flash samples on the M4 target. For this, please -take care of the resource sharing (UART port used for console for instance). - -Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32h747i_disco_m4 - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h747i_disco_m7 - :goals: debug - -Debugging with west is currently not available on Cortex M4 side. -In order to debug a Zephyr application on Cortex M4 side, you can use -`STM32CubeIDE`_. - -.. _STM32H747I-DISCO website: - https://www.st.com/en/evaluation-tools/stm32h747i-disco.html - -.. _STM32H747XI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html - -.. _STM32H747xx reference manual: - https://www.st.com/resource/en/reference_manual/dm00176879.pdf - -.. _STM32H747xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h747xi.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _DISCO_H747I modifications for Ethernet: - https://os.mbed.com/teams/ST/wiki/DISCO_H747I-modifications-for-Ethernet - -.. _STM32CubeIDE: - https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m4.yaml b/boards/arm/stm32h747i_disco/stm32h747i_disco_m4.yaml deleted file mode 100644 index e167c87f64d..00000000000 --- a/boards/arm/stm32h747i_disco/stm32h747i_disco_m4.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: stm32h747i_disco_m4 -name: ST STM32H747I Discovery (M4) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 288 -flash: 1024 -supported: - - arduino_gpio - - gpio -testing: - ignore_tags: - - mpu - - nfc - - net -vendor: st diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m4_defconfig b/boards/arm/stm32h747i_disco/stm32h747i_disco_m4_defconfig deleted file mode 100644 index 2f437301c85..00000000000 --- a/boards/arm/stm32h747i_disco/stm32h747i_disco_m4_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_STM32H747I_DISCO_M4=y - -# enable GPIO -CONFIG_GPIO=y - -# clock configuration -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable uart driver -CONFIG_SERIAL=y - -# By default CONSOLE is assigned to m7 -#CONFIG_CONSOLE=y -#CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.yaml b/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.yaml deleted file mode 100644 index 52e516cda95..00000000000 --- a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: stm32h747i_disco_m7 -name: ST STM32H747I Discovery (M7) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 512 -flash: 1024 -supported: - - arduino_gpio - - gpio - - arduino_spi - - spi - - netif:eth - - qspi - - memc - - usb_cdc - - usb_device -vendor: st diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7_defconfig b/boards/arm/stm32h747i_disco/stm32h747i_disco_m7_defconfig deleted file mode 100644 index c288ddfc5e4..00000000000 --- a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_STM32H747I_DISCO_M7=y - -# Enable the internal SMPS regulator -CONFIG_POWER_SUPPLY_DIRECT_SMPS=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Disable following to assign serial ports to m4 core - -# enable uart driver -CONFIG_SERIAL=y -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32h750b_dk/Kconfig.board b/boards/arm/stm32h750b_dk/Kconfig.board deleted file mode 100644 index afa01489528..00000000000 --- a/boards/arm/stm32h750b_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H735G Discovery board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32H750B_DK - bool "STM32H750B Discovery Kit" - depends on SOC_STM32H750XX diff --git a/boards/arm/stm32h750b_dk/Kconfig.defconfig b/boards/arm/stm32h750b_dk/Kconfig.defconfig deleted file mode 100644 index 48576f5706d..00000000000 --- a/boards/arm/stm32h750b_dk/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32H750B DK board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32H750B_DK - -config BOARD - default "stm32h750b_dk" - -endif # BOARD_STM32H750B_DK diff --git a/boards/arm/stm32h750b_dk/board.cmake b/boards/arm/stm32h750b_dk/board.cmake deleted file mode 100644 index 6500e7b1a4a..00000000000 --- a/boards/arm/stm32h750b_dk/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=STM32H735IG" "--speed=4000") -board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/stm32h750b_dk/doc/index.rst b/boards/arm/stm32h750b_dk/doc/index.rst deleted file mode 100644 index 6ac1aa15d34..00000000000 --- a/boards/arm/stm32h750b_dk/doc/index.rst +++ /dev/null @@ -1,145 +0,0 @@ -.. _stm32h750b_dk_board: - -ST STM32H750B Discovery Kit -########################### - -Overview -******** - -The STM32H750B-DK Discovery kit is a complete demonstration and development -platform for Arm® Cortex®-M7 core-based STM32H750XBH6 microcontroller, with -128Kbytes of Flash memory and 1 Mbytes of SRAM. - -The STM32H750B-DK Discovery kit is used as a reference design for user -application development before porting to the final product, thus simplifying -the application development. - -The full range of hardware features available on the board helps users to enhance -their application development by an evaluation of all the peripherals (such as -USB OTG FS, Ethernet, microSD™ card, USART, CAN FD, SAI audio DAC stereo with -audio jack input and output, MEMS digital microphone, HyperRAM™, -Octo-SPI Flash memory, RGB interface LCD with capacitive touch panel, and others). -ARDUINO® Uno V3, Pmod™ and STMod+ connectors provide easy connection to extension -shields or daughterboards for specific applications. - -STLINK-V3E is integrated into the board, as the embedded in-circuit debugger and -programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H750B-DK board -comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive -software HAL library as well as various software examples. - -.. image:: img/stm32h750b_dk.png - :align: center - :alt: STM32H750B-DK - -More information about the board can be found at the `STM32H750B-DK website`_. -More information about STM32H750 can be found here: - -- `STM32H750 on www.st.com`_ -- `STM32H750xx reference manual`_ -- `STM32H750xx datasheet`_ - -Supported Features -================== - -The current Zephyr stm32h750b_dk board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration per core can be found in the defconfig file: -``boards/arm/stm32h750b_dk/stm32h750b_dk_defconfig`` - -Pin Mapping -=========== - -For more details please refer to `STM32H750B-DK website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PB10/PB11 (ST-Link Virtual Port Com) -- LD1 : PJ2 -- LD2 : PI13 - -System Clock -============ - -The STM32H750B System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock -is driven by the PLL clock at 480MHz. PLL clock is feed by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32H750B Discovery kit has up to 6 UARTs. -The Zephyr console output is assigned to UART3 which connected to the onboard ST-LINK/V3.0. Virtual -COM port interface. Default communication settings are 115200 8N1. - - -Programming and Debugging -************************* - -See :ref:`build_an_application` for more information about application builds. - - -Flashing -======== - -Connect the STM32H750B-DK to your host computer using the ST-LINK -USB port, then run a serial host program to connect with the board. For example: - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -You can then build and flash applications in the usual way. -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h750b_dk - :goals: build flash - -You should see the following message in the serial host program: - -.. code-block:: console - - $ Hello World! stm32h750b_dk - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h750b_dk - :goals: debug - - -.. _STM32H750B-DK website: - https://www.st.com/en/evaluation-tools/stm32h750b-dk.html - -.. _STM32H750 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html - -.. _STM32H750xx reference manual: - https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32H750xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h750ib.pdf diff --git a/boards/arm/stm32h7b3i_dk/Kconfig.board b/boards/arm/stm32h7b3i_dk/Kconfig.board deleted file mode 100644 index c3912d786e0..00000000000 --- a/boards/arm/stm32h7b3i_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H7B3I Discovery kit board configuration - -# Copyright (c) 2022 Byte-Lab d.o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32H7B3I_DK - bool "STM32H7B3I Discovery Kit Development Board" - depends on SOC_STM32H7B3XXQ diff --git a/boards/arm/stm32h7b3i_dk/Kconfig.defconfig b/boards/arm/stm32h7b3i_dk/Kconfig.defconfig deleted file mode 100644 index 8a32fb1c68f..00000000000 --- a/boards/arm/stm32h7b3i_dk/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# STM32H7B3I DISCOVERY KIT board configuration - -# Copyright (c) 2022 Byte-Lab d.o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32H7B3I_DK - -config BOARD - default "stm32h7b3i_dk" - -config INPUT - default y if LVGL - -config INPUT_FT5336_INTERRUPT - default y if INPUT_FT5336 - -# MEMC needs to be enabled in order to store -# display buffer to external SDRAM connected to FMC -config MEMC - default y if DISPLAY - -endif # BOARD_STM32H7B3I_DK diff --git a/boards/arm/stm32h7b3i_dk/doc/index.rst b/boards/arm/stm32h7b3i_dk/doc/index.rst deleted file mode 100644 index 83d18858426..00000000000 --- a/boards/arm/stm32h7b3i_dk/doc/index.rst +++ /dev/null @@ -1,171 +0,0 @@ -.. _stm32h7b3i_dk_board: - -ST STM32H7B3I Discovery Kit -########################### - -Overview -******** - -The STM32H7B3I-DK Discovery kit is a complete demonstration and development -platform for STMicroelectronics Arm® Cortex®-M7 core-based STM32H7B3LIH6QU -microcontroller. - -The STM32H7B3I-DK Discovery kit is used as a reference design for user -application development before porting to the final product, thus simplifying -the application development. - -The full range of hardware features available on the board helps users enhance -their application development by an evaluation of almost all peripherals (such as -USB OTG_HS, microSD, USART, FDCAN, audio DAC stereo with audio jack input and output, -camera, SDRAM, Octo-SPI Flash memory and RGB interface LCD with capacitive touch -panel). ARDUINO® Uno V3 connectors provide easy connection to extension shields or -daughterboards for specific applications. - -STLINK-V3E is integrated into the board, as an embedded in-circuit debugger and -programmer for the STM32 MCU and the USB Virtual COM port bridge. The STM32H7B3I-DK -board comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive -software HAL library as well as various software examples. - -.. image:: img/stm32h7b3i_dk.jpg - :align: center - :alt: STM32H7B3I-DK - -More information about the board can be found at the `STM32H7B3I-DK website`_. -More information about STM32H7B3 can be found here: - -- `STM32H7A3/7B3 on www.st.com`_ -- `STM32H7A3/7B3/7B0 reference manual`_ -- `STM32H7B3xI datasheet`_ - -Supported Features -================== - -The current Zephyr stm32h7b3i_dk board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| LTDC | on-chip | display | -+-----------+------------+-------------------------------------+ -| CANFD | on-chip | can | -+-----------+------------+-------------------------------------+ - - -Other hardware features have not been enabled yet for this board. - -The default configuration per core can be found in the defconfig file: -``boards/arm/stm32h7b3i_dk/stm32h7b3i_dk_defconfig`` - -Pin Mapping -=========== - -For more details please refer to `STM32H7B3I-DK website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) -- UART_4 TX/RX : PH13/PH14 (Arduino Serial) -- I2C4 SCL/SDA : PD12/PD13 (Arduino I2C, Touchscreen FT5336 with PH2 Interrupt Pin) -- SPI2 SCK/MISO/MOSI/NSS : PA12/PB14/PB15/PI0 (Arduino SPI) -- LD1 : PG11 -- LD2 : PG2 -- USER_PB : PC13 -- SDMMC D0/D1/D2/D3/CK/CMD/CD : PC8/PC9/PC10/PC11/PC12/PD2/PI8 -- CANFD RX/TX/WAKE [#]_ : PA11/PA12/PH8 -- FMC SDRAM : - - - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 - - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 - - A14/A15 : PG4/PG5 - - SDNRAS/SDNCAS : PF11/PG15 - - NBL0/NBL1 : PE0/PE1 - - SDCLK/SDNWE/SDCKE1/SDNE1 : PG8/PH5/PH7/PH6 - -- LTDC : - - - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 - - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 - - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 - - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 - - -System Clock -============ - -The STM32H7B3I System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven -by the PLL clock at 280MHz. PLL clock is fed by a 24MHz high speed external clock. - -Serial Port -=========== - -The STM32H7B3I Discovery kit has up to 8 UARTs. -The Zephyr console output is assigned to UART1 which connected to the onboard -ST-LINK/V3.0. Virtual COM port interface. Default communication settings are -115200 8N1. - - -Programming and Debugging -************************* - -See :ref:`build_an_application` for more information about application builds. - - -Flashing -======== - -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. -It is advised to use `STM32CubeProgrammer`_ to check and update option bytes -configuration and flash the ``stm32h7b3i_dk`` target. - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h7b3i_dk - :goals: debug - - -.. _STM32H7B3I-DK website: - https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html - -.. _STM32H7A3/7B3 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3-7b3.html - -.. _STM32H7A3/7B3/7B0 reference manual: - https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32H7B3xI datasheet: - https://www.st.com/resource/en/datasheet/stm32h7b3ai.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _STM32H7B3I_DK board schematics: - https://www.st.com/resource/en/schematic_pack/mb1332-h7b3i-c02_schematic.pdf - -.. [#] To use CAN, solder bridges SB3, SB4 and SB5 need to be connected. - Take note that CANFD pins are shared with STMOD+ connector (P1), so please check - `STM32H7B3I_DK board schematics`_ for possible collisions if using that connector. diff --git a/boards/arm/stm32l1_disco/Kconfig.board b/boards/arm/stm32l1_disco/Kconfig.board deleted file mode 100644 index e9621b560b0..00000000000 --- a/boards/arm/stm32l1_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Board configuration - -# Copyright (c) 2019 eTactica ehf -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32L1_DISCO - bool "STM32L1DISCOVERY Development Board" - depends on SOC_STM32L151XB diff --git a/boards/arm/stm32l1_disco/Kconfig.defconfig b/boards/arm/stm32l1_disco/Kconfig.defconfig deleted file mode 100644 index 8159f9c1abb..00000000000 --- a/boards/arm/stm32l1_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Board configuration - -# Copyright (c) 2019 eTactica ehf -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32L1_DISCO - -config BOARD - default "stm32l1_disco" - -endif # BOARD_STM32L1_DISCO diff --git a/boards/arm/stm32l1_disco/doc/index.rst b/boards/arm/stm32l1_disco/doc/index.rst deleted file mode 100644 index a968cebc792..00000000000 --- a/boards/arm/stm32l1_disco/doc/index.rst +++ /dev/null @@ -1,179 +0,0 @@ -.. _stm32l1_disco_board: - -ST STM32L1 Discovery -#################### - -Overview -******** - -The two generations of the STM32L1 Discovery development boards come with -an integrated ST-LINK/V2 debugger and programmer. The boards have a -24-segment LCD and a touch slider, along with two user LEDs and a user button. -Support circuitry for measuring power consumption is also available. -It also comes with a comprehensive STM32 software HAL library and various -packaged software examples. - -There -are two variants of the board: - -- STM32LDISCOVERY targets STM32L152RBT6, with 128K flash, 16K RAM -- 32L152CDISCOVERY targets STM32L152RCT6, with 256K flash, 32K RAM - -The STM32LDISCOVERY is no longer sold, but was widely available. The current -configuration assumes only 128K flash and 16K RAM, so it builds and runs -on both variants out of the box. - -.. image:: img/stm32l1_disco.jpg - :align: center - :alt: STM32LDISCOVERY - -More information about the board can be found at the `STM32LDISCOVERY website`_. - -Hardware -******** - -The STM32 Discovery board features: - -- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone - ST-LINK/V2 (with SWD connector for programming and debugging) -- Board power supply: through USB bus or from an external 5 V supply voltage -- External application power supply: 3 V and 5 V -- Four LEDs: - - - LD1 (red) for 3.3 V power on - - LD2 (red/green) for USB communication - - LD3 (green) for PC9 output - - LD4 (blue) for PC8 output -- Two push buttons (user and reset) -- Extension header for all LQFP64 I/Os for quick connection to prototyping board - and easy probing - -More information about STM32L151x can be found in the `STM32L1x reference manual`_. - -Supported Features -================== - -The Zephyr stm32l1_disco board configuration supports the following hardware features: - -.. list-table:: Supported hardware - :header-rows: 1 - - * - Interface - - Controller - - Driver/component - * - NVIC - - on-chip - - nested vector interrupt controller - * - UART - - on-chip - - serial port-polling - serial port-interrupt - * - PINMUX - - on-chip - - pinmux - * - GPIO - - on-chip - - gpio - * - CLOCK - - on-chip - - reset and clock control - * - FLASH - - on-chip - - flash memory - * - WATCHDOG - - on-chip - - window watchdog - * - I2C - - on-chip - - i2c - * - SPI - - on-chip - - spi - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32l1_disco/stm32l1_disco_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PB11 -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 - -For more details please refer to `STM32L1DISCOVERY board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``stm32l1_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32L1DISCOVERY board includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application ------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32l1_disco - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32l1_disco - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32LDISCOVERY website: - https://www.st.com/en/evaluation-tools/32l152cdiscovery.html - -.. _STM32L1x reference manual: - https://www.st.com/resource/en/reference_manual/cd00240193.pdf - -.. _STM32L1DISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00027954.pdf diff --git a/boards/arm/stm32l476g_disco/Kconfig.board b/boards/arm/stm32l476g_disco/Kconfig.board deleted file mode 100644 index 2aa9ec78b19..00000000000 --- a/boards/arm/stm32l476g_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L476G Discovery board configuration - -# Copyright (c) 2017 Arthur Sfez -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32L476G_DISCO - bool "STM32L476G Discovery Development Board" - depends on SOC_STM32L476XX diff --git a/boards/arm/stm32l476g_disco/Kconfig.defconfig b/boards/arm/stm32l476g_disco/Kconfig.defconfig deleted file mode 100644 index 77e423642a3..00000000000 --- a/boards/arm/stm32l476g_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32L476G DISCOVERY board configuration - -# Copyright (c) 2017 Arthur Sfez -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32L476G_DISCO - -config BOARD - default "stm32l476g_disco" - -endif # BOARD_STM32L476G_DISCO diff --git a/boards/arm/stm32l476g_disco/doc/index.rst b/boards/arm/stm32l476g_disco/doc/index.rst deleted file mode 100644 index 65eef57c609..00000000000 --- a/boards/arm/stm32l476g_disco/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ -.. _stm32l476g_disco_board: - -ST STM32L476G Discovery -####################### - -Overview -******** - -The STM32L476G Discovery board features an ARM Cortex-M4 based STM32L476VG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the STM32L476G Discovery board: - - -- STM32L476VGT6 microcontroller featuring 1 Mbyte of Flash memory, 128 Kbytes of RAM in LQFP100 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- Three different interfaces supported on USB: - - - Virtual com port - - Mass storage - - Debug port - -- LCD 24 segments, 4 commons in DIP 28 package -- Seven LEDs: - - - LD1 (red/green) for USB communication - - LD2 (red) for 3.3 V power on - - LD3 Over current (red) - - LD4 (red), LD5 (green) two user LEDs - - LD6 (green), LD7 (red) USB OTG FS LEDs - -- Pushbutton (reset) -- Four directions Joystick with selection -- USB OTG FS with micro-AB connector -- SAI Audio DAC, Stereo with output jack -- Digital microphone, accelerometer, magnetometer and gyroscope MEMS -- 128-Mbit Quad-SPI Flash memory -- MCU current ammeter with 4 ranges and auto-calibration -- Connector for external board or RF-EEPROM -- Four power supply options: - - ST-LINK/V2-1 - - USB FS connector - - External 5 V - - CR2032 battery (not provided) - -.. image:: img/stm32l476g_disco.jpg - :align: center - :alt: STM32L476G Discovery - -More information about the board can be found at the `STM32L476G Discovery website`_. - -Hardware -******** - -The STM32L476VG SoC provides the following hardware features: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC -- RTC with HW calendar, alarms and calibration -- LCD 8 x 40 or 4 x 44 with step-up converter -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer -- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 128 KB of SRAM including 32 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators -- 18x communication interfaces - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (4x SPIs with the Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L476VG can be found here: - - `STM32L476VG on www.st.com`_ - - `STM32L476 reference manual`_ - - -Supported Features -================== - -The Zephyr stm32l476g_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32l476g_disco/stm32l476g_disco_defconfig`` - - -Connections and IOs -=================== - -STM32L476G Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32L476G Discovery board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- LD4 : PB2 -- LD5 : PE8 - -System Clock ------------- - -STM32L476G Discovery System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -STM32L476G Discovery board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -STM32L476G Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32L476G Discovery ------------------------------------------------ - -Connect the STM32L476G Discovery to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l476g_disco - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l476g_disco - :maybe-skip-config: - :goals: debug - -.. _STM32L476G Discovery website: - https://www.st.com/en/evaluation-tools/32l476gdiscovery.html - -.. _STM32L476G Discovery board User Manual: - https://www.st.com/resource/en/user_manual/dm00172179.pdf - -.. _STM32L476VG on www.st.com: - https://www.st.com/en/microcontrollers/stm32l476vg.html - -.. _STM32L476 reference manual: - https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/stm32l496g_disco/Kconfig.board b/boards/arm/stm32l496g_disco/Kconfig.board deleted file mode 100644 index 4d2e23204a8..00000000000 --- a/boards/arm/stm32l496g_disco/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# STM32L496G Discovery board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# Copyright (c) 2019 Centaur Analytics, Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32L496G_DISCO - bool "STM32L496G Discovery Development Board" - depends on SOC_STM32L496XX diff --git a/boards/arm/stm32l496g_disco/Kconfig.defconfig b/boards/arm/stm32l496g_disco/Kconfig.defconfig deleted file mode 100644 index 114aacf680d..00000000000 --- a/boards/arm/stm32l496g_disco/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# STM32L476G Nucleo board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32L496G_DISCO - -config BOARD - default "stm32l496g_disco" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_STM32L496G_DISCO diff --git a/boards/arm/stm32l496g_disco/doc/index.rst b/boards/arm/stm32l496g_disco/doc/index.rst deleted file mode 100644 index e8bc81f092b..00000000000 --- a/boards/arm/stm32l496g_disco/doc/index.rst +++ /dev/null @@ -1,259 +0,0 @@ -.. _stm32l496g_disco_board: - -ST STM32L496G Discovery -####################### - -Overview -******** - -The STM32L496G Discovery board features an ARM Cortex-M4 based STM32L496AG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the STM32L496G Discovery board: - - -- STM32L496AGI6 microcontroller featuring 1 Mbyte of Flash memory and 320 Kbytes of RAM in an UFBGA169 package -- 1.54 inch 240 x 240 pixel-TFT color LCD with parallel interface -- SAI Audio CODEC, with a stereo headset jack, including analog microphone input -- Stereo digital MEMS microphones -- microSD card connector (card included) -- Camera 8 bit-connector -- 8 Mbit-PSRAM -- IDD measurement -- 64 Mbit-Quad-SPI Flash -- USB OTG FS with Micro-AB connector -- Two types of extension resources: - - - STMod+ and PMOD connectors - - Compatible Arduino* Uno V3 connectors - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- 5 source options for power supply - - - ST-LINK/V2-1 USB connector - - User USB FS connector - - VIN from Arduino connector - - 5 V from Arduino connector - - USB charger - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- 8 LEDs -- Reset push button -- 4 direction-joystick with selection - -.. image:: img/stm32l496g_disco.jpg - :align: center - :alt: STM32L496G Discovery - -More information about the board can be found at the `STM32L496G Discovery website`_. - -Hardware -******** - -The STM32L496AG SoC provides the following hardware capabilities: - -- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, - 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - Internal 48 MHz with clock recovery - - 3 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- LCD 8 x 40 or 4 x 44 with step-up converter -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - 320 KB of SRAM including 64 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR, and NAND memories - - Quad SPI memory interface - -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 20x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 5x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART - - 3x SPIs (4x SPIs with the Quad SPI) - - 2x CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32L496AG can be found in: - -- `STM32L496AG on www.st.com`_ -- `STM32L496 reference manual`_ - -Supported Features -================== - -The Zephyr stm32l496g_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig`` - - -Connections and IOs -=================== - -STM32L496G Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32L496G Discovery board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PG10 -- UART_2 TX/RX : PA2/PD6 (ST-Link Virtual Port Com) -- LPUART_1 TX/RX : PG7/PG8 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB7 (Arduino I2C) -- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2 -- SPI1 NSS/SCK/MISO/MOSI : PA15/PA5/PB4/PB5 (Arduino SPI) -- USB DM/DP/ID : PA11/PA12/PA10 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB7 -- PWM_2_CH1 : PA0 -- LD2 : PB13 - -System Clock ------------- - -STM32L496G Discovery System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -STM32L496G Discovery board has 5 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -STM32L496G Discovery board includes an ST-LINK/V2-1 embedded debug -tool interface. This interface is supported by openocd version -v0.10.0, which has been available since Zephyr SDK v0.9.2. - -Applications for the ``stm32l496g_disco`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - -Flashing an application to STM32L496G Discovery ------------------------------------------------ - -Connect the STM32L496G Discovery to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l496g_disco - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l496g_disco - :maybe-skip-config: - :goals: debug - -.. _STM32L496G Discovery website: - https://www.st.com/en/evaluation-tools/32l496gdiscovery.html - -.. _STM32L496G Discovery board User Manual: - https://www.st.com/resource/en/user_manual/dm00353127.pdf - -.. _STM32L496AG on www.st.com: - https://www.st.com/en/microcontrollers/stm32l496ag.html - -.. _STM32L496 reference manual: - https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/stm32l4r9i_disco/Kconfig.board b/boards/arm/stm32l4r9i_disco/Kconfig.board deleted file mode 100644 index 57da0f65fdf..00000000000 --- a/boards/arm/stm32l4r9i_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L4R9I Discovery board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32L4R9I_DISCO - bool "STM32L4R9I Discovery Development Board" - depends on SOC_STM32L4R9XX diff --git a/boards/arm/stm32l4r9i_disco/Kconfig.defconfig b/boards/arm/stm32l4r9i_disco/Kconfig.defconfig deleted file mode 100644 index 82eafa62744..00000000000 --- a/boards/arm/stm32l4r9i_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32L4R9I Discovery board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32L4R9I_DISCO - -config BOARD - default "stm32l4r9i_disco" - -endif # BOARD_STM32L4R9I_DISCO diff --git a/boards/arm/stm32l4r9i_disco/doc/index.rst b/boards/arm/stm32l4r9i_disco/doc/index.rst deleted file mode 100644 index 0f651e2b9ff..00000000000 --- a/boards/arm/stm32l4r9i_disco/doc/index.rst +++ /dev/null @@ -1,150 +0,0 @@ -.. _stm32l4r9i_disco_board: - -ST STM32L4R9I Discovery -####################### - -Overview -******** - -The 32L4R9IDISCOVERY Discovery kit is a complete demonstration and development platform -for STMicroelectronics Arm® Cortex®-M4 core-based STM32L4R9AI microcontroller. - -Leveraging the innovative ultra-low-power oriented features, 640 Kbytes of embedded RAM, -graphics performance (Chrom-ART Accelerator), and DSI controller offered by the STM32L4R9AI, -the 32L4R9IDISCOVERY Discovery kit enables users to easily prototype applications with -state-of-the-art energy efficiency, as well as stunning audio and graphics rendering with direct -support for AMOLED DSI round LCD display. - -For even more user-friendliness, the on-board ST-LINK/V2-1 debugger provides out-of-the-box -programming and debugging capabilities. - -.. image:: img/stm32l4r9i_disco.jpg - :align: center - :alt: STM32L4R9I-DISCO - -More information about the board can be found at the `STM32L4R9I-DISCOVERY website`_. -More information about STM32L4R9 can be found here: - -- `STM32L4R9/S9 on www.st.com`_ -- `STM32L4+ Series reference manual`_ -- `STM32L4R5xx/R7xx/R9xx datasheet`_ - -Supported Features -================== - -The current Zephyr stm32l4r9i_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | on-chip flash memory; | -| | | external OctoSPI memory | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | Real Time Clock | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | sd/mmc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32l4r9i_disco/stm32l4r9i_disco_defconfig`` - - -Pin Mapping -=========== - -For more details, please refer to `STM32L4R9I-DISCOVERY website`_. - -System Clock -============ - -The STM32L4R9AI System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven by -the PLL clock at 120MHz. PLL clock is driven by a 4MHz medium speed internal clock. - -Serial Port -=========== - -The STM32L4R9I Discovery board has up to 6 U(S)ARTs. -The Zephyr console output is assigned to UART2, which is connected to the onboard -ST-LINK Virtual COM port interface. Default communication settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -The STM32L4R9I Discovery board includes an ST-LINK/V2-1 debug tool. - -Applications for the ``stm32l4r9i_disco`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - - -Flashing an application to STM32L4R9I Discovery ------------------------------------------------ - -Connect the STM32L4R9I Discovery to your host computer using the ST-LINK -USB port, then run a serial host program to connect with the board. For example: - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -You can then build and flash applications in the usual way. -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l4r9i_disco - :goals: build flash - -You should see the following message in the serial host program: - -.. code-block:: console - - $ Hello World! stm32l4r9i_disco - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l4r9i_disco - :goals: debug - -.. _STM32L4R9I-DISCOVERY website: - https://www.st.com/en/evaluation-tools/32l4r9idiscovery.html - -.. _STM32L4R9/S9 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l4r9-s9.html - -.. _STM32L4+ Series reference manual: - https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32L4R5xx/R7xx/R9xx datasheet: - https://www.st.com/resource/en/datasheet/stm32l4r5vi.pdf diff --git a/boards/arm/stm32l562e_dk/Kconfig.board b/boards/arm/stm32l562e_dk/Kconfig.board deleted file mode 100644 index 44cabce93d3..00000000000 --- a/boards/arm/stm32l562e_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L562E-DK Discovery board configuration - -# Copyright (c) 2020 Yestin Sun -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32L562E_DK - bool "STM32L562E-DK Discovery Development Board" - depends on SOC_STM32L562XX diff --git a/boards/arm/stm32l562e_dk/Kconfig.defconfig b/boards/arm/stm32l562e_dk/Kconfig.defconfig deleted file mode 100644 index 3a81889dc71..00000000000 --- a/boards/arm/stm32l562e_dk/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# STM32L562E-DK Discovery board configuration - -# Copyright (c) 2020 Yestin Sun -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32L562E_DK - -config BOARD - default "stm32l562e_dk" - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -config BT_BLUENRG_ACI - default y - -# Disable Flow control -config BT_HCI_ACL_FLOW_CONTROL - default n - -config BT_HCI_VS_EXT - default n - -endif # BT - -if TRUSTED_EXECUTION_NONSECURE - -# Get flash configuration for NS image from dts flash partition -config USE_DT_CODE_PARTITION - default y - -endif # TRUSTED_EXECUTION_NONSECURE - -endif # BOARD_STM32L562E_DK diff --git a/boards/arm/stm32l562e_dk/doc/index.rst b/boards/arm/stm32l562e_dk/doc/index.rst deleted file mode 100644 index 16af6cb242b..00000000000 --- a/boards/arm/stm32l562e_dk/doc/index.rst +++ /dev/null @@ -1,387 +0,0 @@ -.. _stm32l562e_dk_board: - -ST STM32L562E-DK Discovery -########################## - -Overview -******** - -The STM32L562E-DK Discovery kit is designed as a complete demonstration and -development platform for STMicroelectronics Arm |reg| Cortex |reg|-M33 core-based -STM32L562QEI6QU microcontroller with TrustZone |reg|. Here are some highlights of -the STM32L562E-DK Discovery board: - - -- STM32L562QEI6QU microcontroller featuring 512 Kbytes of Flash memory and 256 Kbytes of SRAM in BGA132 package -- 1.54" 240 x 240 pixel-262K color TFT LCD module with parallel interface and touch-control panel -- USB Type-C |trade| Sink device FS -- On-board energy meter: 300 nA to 150 mA measurement range with a dedicated USB interface -- SAI Audio CODEC -- MEMS digital microphones -- 512-Mbit Octal-SPI Flash memory -- Bluetooth |reg| V4.1 Low Energy module -- iNEMO 3D accelerometer and 3D gyroscope -- Board connectors - - - STMod+ expansion connector with fan-out expansion board for Wi‑Fi |reg|, Grove and mikroBUS |trade| compatible connectors - - Pmod |trade| expansion connector - - Audio MEMS daughterboard expansion connector - - ARDUINO |reg| Uno V3 expansion connector - -- Flexible power-supply options - - - ST-LINK - - USB VBUS - - external sources - -- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: - - - mass storage - - Virtual COM port - - debug port - -- 2 user LEDs -- User and reset push-buttons - -.. image:: img/stm32l562e_dk.jpg - :align: center - :alt: STM32L562E-DK Discovery - -More information about the board can be found at the `STM32L562E-DK Discovery website`_. - -Hardware -******** - -The STM32L562xx devices are an ultra-low-power microcontrollers family (STM32L5 -Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. -They operate at a frequency of up to 110 MHz. - -- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 62 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 1.5 DMPIS/MHz (Drystone 2.1) - - 442 CoreMark |reg| (4.02 CoreMark |reg| /MHZ) - -- Security - - - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals - - Flexible life cycle scheme with RDP (readout protection) - - Root of trust thanks to unique boot entry and hide protection area (HDP) - - Secure Firmware Installation thanks to embedded Root Secure Services - - Secure Firmware Update support with TF-M - - AES coprocessor - - Public key accelerator - - On-the-fly decryption of Octo-SPI external memories - - HASH hardware accelerator - - Active tamper and protection temperature, voltage and frequency attacks - - True Random Number Generator NIST SP800-90B compliant - - 96-bit unique ID - - 512-byte One-Time Programmable for user data - -- Clock management: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - -- Power management - - - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry - - Embedded SMPS step-down converter - - External SMPS support - -- RTC with HW calendar, alarms and calibration -- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Up to 22 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- Up to 16 timers and 2 watchdogs - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 3x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- Memories - - - Up to 512 MB Flash, 2 banks read-while-write - - 512 KB of SRAM including 64 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR, NAND and FRAM memories - - OCTOSPI memory interface - -- Rich analog peripherals (independent supply) - - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - - 4x digital filters for sigma delta modulator - -- 19x communication interfaces - - - USB Type-C / USB power delivery controller - - 2.0 full-speed crystal less solution, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (7x SPIs with USART and OCTOSPI in SPI mode) - - 1xFDCAN - - 1xSDMMC interface - - 2x 14 channel DMA controllers - -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L562QE can be found here: - -- `STM32L562QE on www.st.com`_ -- `STM32L562 reference manual`_ - -Supported Features -================== - -The Zephyr stm32l562e_dk board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| AES | on-chip | crypto | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | sd/mmc | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| TrustZone | on-chip | Trusted Firmware-M | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig and dts files: - -- Common: - - - :zephyr_file:`boards/arm/stm32l562e_dk/stm32l562e_dk_common.dtsi` - -- Secure target: - - - :zephyr_file:`boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig` - - :zephyr_file:`boards/arm/stm32l562e_dk/stm32l562e_dk.dts` - -- Non-Secure target: - - - :zephyr_file:`boards/arm/stm32l562e_dk/stm32l562e_dk_ns_defconfig` - - :zephyr_file:`boards/arm/stm32l562e_dk/stm32l562e_dk_ns.dts` - -Zephyr board options -==================== - -The STM32L562e is an SoC with Cortex-M33 architecture. Zephyr provides support -for building for both Secure and Non-Secure firmware. - -The BOARD options are summarized below: - -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| stm32l562e_dk | For building Secure (or Secure-only) firmware | -+----------------------+-----------------------------------------------+ -| stm32l562e_dk_ns | For building Non-Secure firmware | -+----------------------+-----------------------------------------------+ - -Here are the instructions to build Zephyr with a non-secure configuration, -using `tfm_ipc_` sample: - - .. code-block:: bash - - $ west build -b stm32l562e_dk_ns samples/tfm_integration/tfm_ipc/ - -Once done, before flashing, you need to first run a generated script that -will set platform option bytes config and erase platform (among others, -option bit TZEN will be set). - - .. code-block:: bash - - $ ./build/tfm/regression.sh - $ west flash - -Please note that, after having run a TFM sample on the board, you will need to -run `./build/tfm/regression.sh` once more to clean up the board from secure -options and get back the platform back to a "normal" state and be able to run -usual, non-TFM, binaries. -Also note that, even then, TZEN will remain set, and you will need to use -STM32CubeProgrammer_ to disable it fully, if required. - -Connections and IOs -=================== - -STM32L562E-DK Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32L562E-DK Discovery board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- USART_1 TX/RX : PA9/PA10 -- USART_3 TX/RX : PC10/PC11 -- I2C_1 SCL/SDA : PB6/PB7 -- SPI_1 SCK/MISO/MOSI : PG2/PG3/PG4 (BT SPI bus) -- SPI_3 NSS/SCK/MISO/MOSI : PE0/PG9/PB4/PB5 (Arduino SPI) -- USER_PB : PC13 -- LD10 : PG12 -- PWM_2_CH1 : PA0 -- DAC1 : PA4 -- ADC1 : PC4 - -System Clock ------------- - -STM32L562E-DK System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at -110MHz, driven by 4MHz medium speed internal oscillator. - -Serial Port ------------ - -STM32L562E-DK Discovery board has 6 U(S)ARTs. The Zephyr console output is -assigned to USART1. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``stm32l562e_dk`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32L562E-DK Discovery board includes an ST-LINK/V3E embedded debug tool -interface. Support can be enabled on pyocd by adding "pack" support with the -following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32l562qe - -Alternatively, this interface is supported by the openocd version -included in the Zephyr SDK since v0.13.1. - -Flashing an application to STM32L562E-DK Discovery --------------------------------------------------- - -Connect the STM32L562E-DK Discovery to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l562e_dk - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! stm32l562e_dk - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| ------------------------------------------------------------------------------ - -The TF-M integration sample :ref:`tfm_ipc` can be run on a ST STM32L562E-DK Discovery. -In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image -can be generated using ``stm32l562e_dk_ns`` as build target. - -.. code-block:: bash - - $ west build -b stm32l562e_dk_ns path/to/source/directory - -Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script -is run automatically in a post-build step to make some required flash layout changes. - -Once the build is completed, run the following script to initialize the option bytes. - -.. code-block:: bash - - $ build/tfm/regression.sh - -Finally, to flash the board, run: - -.. code-block:: bash - - $ west flash --hex-file build/tfm_merged.hex - -Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts -(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` -(which is used for initialization) is available in the PATH. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l562e_dk - :maybe-skip-config: - :goals: debug - -.. _STM32L562E-DK Discovery website: - https://www.st.com/en/evaluation-tools/stm32l562e-dk.html - -.. _STM32L562E-DK Discovery board User Manual: - https://www.st.com/resource/en/user_manual/dm00635554.pdf - -.. _STM32L562QE on www.st.com: - https://www.st.com/en/microcontrollers/stm32l562qe.html - -.. _STM32L562 reference manual: - https://www.st.com/resource/en/reference_manual/DM00346336.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_ns.yaml b/boards/arm/stm32l562e_dk/stm32l562e_dk_ns.yaml deleted file mode 100644 index 8d743536e74..00000000000 --- a/boards/arm/stm32l562e_dk/stm32l562e_dk_ns.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: stm32l562e_dk_ns -name: ST STM32L562E-DK Discovery non secure -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - counter - - gpio - - i2c - - lptim - - dac - - spi - - arduino_spi - - sdhc - - usb - - usb_device -ram: 192 -flash: 512 -vendor: st diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_ns_defconfig b/boards/arm/stm32l562e_dk/stm32l562e_dk_ns_defconfig deleted file mode 100644 index c28424d306a..00000000000 --- a/boards/arm/stm32l562e_dk/stm32l562e_dk_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32L5X=y -CONFIG_SOC_STM32L562XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32mp157c_dk2/Kconfig.board b/boards/arm/stm32mp157c_dk2/Kconfig.board deleted file mode 100644 index b020b97dd88..00000000000 --- a/boards/arm/stm32mp157c_dk2/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32MP157C Discovery board configuration - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32MP157C_DK2 - bool "STM32MP157C Discovery Development 2 Board" - depends on SOC_STM32MP15_M4 diff --git a/boards/arm/stm32mp157c_dk2/Kconfig.defconfig b/boards/arm/stm32mp157c_dk2/Kconfig.defconfig deleted file mode 100644 index 277a98e6de6..00000000000 --- a/boards/arm/stm32mp157c_dk2/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32MP157 discovery board configuration - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32MP157C_DK2 - -config BOARD - default "stm32mp157c_dk2" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -config CLOCK_STM32_HSE_CLOCK - default 24000000 - -endif # BOARD_STM32MP157_Dk2 diff --git a/boards/arm/stm32u5a9j_dk/Kconfig.board b/boards/arm/stm32u5a9j_dk/Kconfig.board deleted file mode 100644 index 8482aa58f04..00000000000 --- a/boards/arm/stm32u5a9j_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32U5A9J Discovery Kit board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32U5A9J_DK - bool "STM32U5A9J Discovery Kit Development Board" - depends on SOC_STM32U5A9XX diff --git a/boards/arm/stm32u5a9j_dk/Kconfig.defconfig b/boards/arm/stm32u5a9j_dk/Kconfig.defconfig deleted file mode 100644 index 8124e022740..00000000000 --- a/boards/arm/stm32u5a9j_dk/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32U5A9J DISCOVERY KIT board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32U5A9J_DK - -config BOARD - default "stm32u5a9j_dk" - -endif # BOARD_STM32U5A9J_DK diff --git a/boards/arm/stm32u5a9j_dk/doc/index.rst b/boards/arm/stm32u5a9j_dk/doc/index.rst deleted file mode 100644 index 23859666df7..00000000000 --- a/boards/arm/stm32u5a9j_dk/doc/index.rst +++ /dev/null @@ -1,198 +0,0 @@ -.. _stm32u5a9j_dk_board: - -ST STM32U5A9J Discovery Kit -########################### - -Overview -******** - -The STM32U5A9J-DK Discovery kit is a complete demonstration and development -platform for the STM32U5A9NJH6Q microcontroller, featuring an Arm® Cortex®-M33 -core with Arm® TrustZone®. - -Leveraging the innovative ultra-low-power oriented features, 2.5 Mbytes of -embedded SRAM, 4 Mbytes of embedded flash memory, and rich graphics features, -the STM32U5A9J-DK Discovery kit enables users to easily prototype applications -with state-of-the-art energy efficiency, as well as providing stunning and -optimized graphics rendering with the support of the 2.5D NeoChrom Accelerator, -Chrom-ART Accelerator, and Chrom-GRC™ MMU. - -The full range of hardware features available on the board helps users to -enhance their application development by an evaluation of all the peripherals -such as a 2.47-inch RGB 480x480 pixels TFT round LCD module with MIPI DSI® -interface and capacitive touch panel, USB Type-C® HS, Octo-SPI flash memory -device, Hexadeca-SPI PSRAM memory device, eMMC flash memory device, -Time-of-Flight and gesture detection sensor, temperature sensor, and two 2.54 mm -pitch double-row flexible expansion connectors for easy prototyping with -daughterboards for specific applications (USART, LPUART, two SPIs, SAI, three -I2C, SDMMC, ADCs, timers, and GPIOs). - -The STM32U5A9J-DK Discovery kit integrates an STLINK-V3E embedded in-circuit -debugger and programmer for the STM32 microcontroller with a USB Virtual COM -port bridge and comes with the STM32CubeU5 MCU Package, which provides an STM32 -comprehensive software HAL library as well as various software examples. - -.. image:: img/top_view.jpg - :align: center - :alt: STM32U5A9J-DK Top View - -.. image:: img/bottom_view.jpg - :align: center - :alt: STM32U5A9J-DK Bottom View - -More information about the board can be found at the `STM32U5A9J-DK website`_. -More information about STM32U5A9NJH6Q can be found here: - -- `STM32U5A9NJ on www.st.com`_ -- `STM32U5 Series reference manual`_ -- `STM32U5Axxx datasheet`_ - -Supported Features -================== - -The current Zephyr stm32u5a9j_dk board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| LPUART | on-chip | low power uart | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration per core can be found in the defconfig file: -``boards/arm/stm32u5a9j_dk/stm32u5a9j_dk_defconfig`` - -Pin Mapping -=========== - -For more details please refer to `STM32U5A9J-DK board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- USART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) -- LD3 : PE0 -- LD4 : PE1 -- User Button: PC13 -- USART_3 TX/RX : PB10/PB11 -- LPUART_1 TX/RX : PG7/PG8 -- I2C1 SCL/SDA : PG14/PG13 -- I2C2 SCL/SDA : PF1/PF0 -- I2C6 SCL/SDA : PD1/PD0 -- SPI2 SCK/MISO/MOSI/CS : PB13/PD3/PD4/PB12 -- SPI3 SCK/MISO/MOSI/CS : PG9/PG10/PG11/PG15 -- ADC1 : channel5 PA0, channel14 PC5 -- ADC2 : channel9 PA4 -- ADC4 : channel5 PF14 - -System Clock -============ - -The STM32U5A9J-DK Discovery kit relies on an HSE oscillator (16 MHz crystal) -and an LSE oscillator (32.768 kHz crystal) as clock references. -Using the HSE (instead of HSI) is mandatory to manage the DSI interface for -the LCD module and the USB high‑speed interface. - -Serial Port -=========== - -The STM32U5A9J Discovery kit has up to 4 USARTs, 2 UARTs, and 1 LPUART. -The Zephyr console output is assigned to USART1 which connected to the onboard -ST-LINK/V3.0. Virtual COM port interface. Default communication settings are -115200 8N1. - - -Programming and Debugging -************************* - -STM32U5A9J Discovery kit includes an ST-LINK/V3 embedded debug tool interface. -This probe allows to flash and debug the board using various tools. - -Flashing -======== - -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board., - -Connect the STM32U5A9J Discovery board to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 -b 115200 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32u5a9j_dk - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! stm32u5a9j_dk - -Debugging -========= - -Default debugger for this board is openocd. It could be used in the usual way -with "west debug" command. -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32u5a9j_dk - :goals: debug - - -.. _STM32U5A9J-DK website: - https://www.st.com/en/evaluation-tools/stm32u5a9j-dk.html - -.. _STM32U5A9J-DK board User Manual: - https://www.st.com/resource/en/user_manual/um2967-discovery-kit-with-stm32u5a9nj-mcu-stmicroelectronics.pdf - -.. _STM32U5A9NJ on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32u5a9nj.html - -.. _STM32U5 Series reference manual: - https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32U5Axxx datasheet: - https://www.st.com/resource/en/datasheet/stm32u5a9nj.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _STM32U5A9J_DK board schematics: - https://www.st.com/resource/en/schematic_pack/mb1829-u5a9njq-b01-schematic.pdf diff --git a/boards/arm/stm32vl_disco/Kconfig.board b/boards/arm/stm32vl_disco/Kconfig.board deleted file mode 100644 index 57a0e43e68e..00000000000 --- a/boards/arm/stm32vl_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Board configuration - -# Copyright (c) 2020 Jonas Eriksson, Up to Code AB -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32VL_DISCO - bool "STM32VLDISCOVERY Development Board" - depends on SOC_STM32F100XB diff --git a/boards/arm/stm32vl_disco/Kconfig.defconfig b/boards/arm/stm32vl_disco/Kconfig.defconfig deleted file mode 100644 index 1bdcdc36a0d..00000000000 --- a/boards/arm/stm32vl_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Board configuration - -# Copyright (c) 2020 Jonas Eriksson, Up to Code AB -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32VL_DISCO - -config BOARD - default "stm32vl_disco" - -endif # BOARD_STM32VL_DISCO diff --git a/boards/arm/stm32vl_disco/doc/index.rst b/boards/arm/stm32vl_disco/doc/index.rst deleted file mode 100644 index 7819200bafb..00000000000 --- a/boards/arm/stm32vl_disco/doc/index.rst +++ /dev/null @@ -1,188 +0,0 @@ -.. _stm32vl_disco_board: - -ST STM32VL Discovery -#################### - -Overview -******** - -The STM32 Discovery series comes in many varieties, in this case the "Value -Line" STM32F100x SoC series is showcased. Like other Discovery board, an -integrated ST-LINK debugger and programmer is included (V1), but the only -included I/O devices are two user LEDs and one user button. - -.. image:: img/stm32vl_disco.jpg - :align: center - :alt: STM32VLDISCOVERY - -More information about the board can be found at the `STM32VLDISCOVERY website`_. - -Hardware -******** - -The STM32 Discovery board features: - -- On-board ST-LINK/V1 with selection mode switch to use the kit as a standalone - ST-LINK/V1 (with SWD connector for programming and debugging) -- Board power supply: through USB bus or from an external 5 V supply voltage -- External application power supply: 3 V and 5 V -- Four LEDs: - - - LD1 (red) for 3.3 V power on - - LD2 (red/green) for USB communication - - LD3 (green) for PC9 output - - LD4 (blue) for PC8 output -- Two push buttons (user and reset) -- Extension header for all LQFP64 I/Os for quick connection to prototyping board - and easy probing - -More information about the STM32F100x can be found in the -`STM32F100x reference manual`_ and the `STM32F100x data sheet`_. - -Supported Features -================== - -The Zephyr stm32vl_disco board configuration supports the following hardware features: - -.. list-table:: Supported hardware - :header-rows: 1 - - * - Interface - - Controller - - Driver/component - * - NVIC - - on-chip - - nested vector interrupt controller - * - UART - - on-chip - - serial port-polling - serial port-interrupt - * - PINMUX - - on-chip - - pinmux - * - GPIO - - on-chip - - gpio - * - CLOCK - - on-chip - - reset and clock control - * - FLASH - - on-chip - - flash memory - * - WATCHDOG - - on-chip - - window watchdog - * - I2C - - on-chip - - i2c - * - SPI - - on-chip - - spi - * - ADC - - on-chip - - adc - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32vl_disco/stm32vl_disco_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- UART_3_TX : PB10 -- UART_3_RX : PB11 -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PB11 - -For more details please refer to `STM32VLDISCOVERY board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``stm32vl_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32VLDISCOVERY board includes an ST-LINK/V1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application ------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32vl_disco - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32vl_disco - :maybe-skip-config: - :goals: debug - -USB mass storage issues -======================= - -The ST-LINK/V1 includes a buggy USB mass storage gadget. To connect to the -ST-LINK from Linux, you might need to ignore the device using modprobe -configuration parameters: - -.. code-block:: shell - - $ echo "options usb-storage quirks=483:3744:i" | sudo tee /etc/modprobe.d/local.conf - $ sudo modprobe -r usb-storage - -References -********** - -.. target-notes:: - -.. _STM32VLDISCOVERY website: - https://www.st.com/en/evaluation-tools/stm32vldiscovery.html - -.. _STM32F100x reference manual: - https://www.st.com/resource/en/reference_manual/cd00246267.pdf - -.. _STM32F100x data sheet: - https://www.st.com/resource/en/datasheet/stm32f100cb.pdf - -.. _STM32VLDISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/cd00267113.pdf diff --git a/boards/arm/stm32wb5mm_dk/Kconfig.board b/boards/arm/stm32wb5mm_dk/Kconfig.board deleted file mode 100644 index 28ca74d81a9..00000000000 --- a/boards/arm/stm32wb5mm_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WB5MM-DK Discovery Development board configuration - -# Copyright (c) 2024 Javad Rahimipetroudi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32WB5MM_DK - bool "stm32wb5mm-dk Discovery Development Board" - depends on SOC_STM32WB55XX diff --git a/boards/arm/stm32wb5mm_dk/Kconfig.defconfig b/boards/arm/stm32wb5mm_dk/Kconfig.defconfig deleted file mode 100644 index 5ce31881bd0..00000000000 --- a/boards/arm/stm32wb5mm_dk/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32WB5MM-DK Discovery Development board configuration - -# Copyright (c) 2024 Javad Rahimipetroudi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32WB5MM_DK - -config BOARD - default "stm32wb5mm_dk" - -choice BT_HCI_BUS_TYPE - default BT_STM32_IPM - depends on BT -endchoice - -endif # BOARD_STM32WB5MM_DK diff --git a/boards/arm/stm32wb5mmg/Kconfig.board b/boards/arm/stm32wb5mmg/Kconfig.board deleted file mode 100644 index 4fe8c22fd7c..00000000000 --- a/boards/arm/stm32wb5mmg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WB5MMG Bluetooth module board configuration - -# Copyright (c) 2024 Javad Rahimipetroudi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32WB5MMG - bool "stm32wb5mmg ultra low power Bluetooth module" - depends on SOC_STM32WB55XX diff --git a/boards/arm/stm32wb5mmg/Kconfig.defconfig b/boards/arm/stm32wb5mmg/Kconfig.defconfig deleted file mode 100644 index cedb62395be..00000000000 --- a/boards/arm/stm32wb5mmg/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32WB5MMG Bluetooth module board configuration - -# Copyright (c) 2024 Javad Rahimipetroudi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32WB5MMG - -config BOARD - default "stm32wb5mmg" - -choice BT_HCI_BUS_TYPE - default BT_STM32_IPM - depends on BT -endchoice - -endif # BOARD_STM32WB5MMG diff --git a/boards/arm/swan_r5/CMakeLists.txt b/boards/arm/swan_r5/CMakeLists.txt deleted file mode 100644 index 218a0602483..00000000000 --- a/boards/arm/swan_r5/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(board.c) diff --git a/boards/arm/swan_r5/Kconfig.board b/boards/arm/swan_r5/Kconfig.board deleted file mode 100644 index f1f15cb8bd7..00000000000 --- a/boards/arm/swan_r5/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Blues Wireless Swan board configuration - -# Copyright (c) 2022 Blues Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SWAN_R5 - bool "Blues Wireless Swan Development Board" - depends on SOC_STM32L4R5XX diff --git a/boards/arm/swan_r5/Kconfig.defconfig b/boards/arm/swan_r5/Kconfig.defconfig deleted file mode 100644 index 0ab4dbfb0d0..00000000000 --- a/boards/arm/swan_r5/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Blues Wireless Swan board configuration - -# Copyright (c) 2022 Blues Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SWAN_R5 - -config BOARD - default "swan_r5" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_EEM - default y - -endif # NETWORKING - -endif # BOARD_SWAN_R5 diff --git a/boards/arm/swan_r5/doc/index.rst b/boards/arm/swan_r5/doc/index.rst deleted file mode 100644 index 8a70207bf58..00000000000 --- a/boards/arm/swan_r5/doc/index.rst +++ /dev/null @@ -1,232 +0,0 @@ -.. _swan_r5_board: - -Blues Wireless Swan -################### - -Overview -******** - -Swan is a low-cost embeddable STM32L4-based microcontroller designed to -accelerate the development and deployment of battery-powered solutions. -It is especially useful for applications requiring large memory or a high -degree of I/O expandability at an affordable cost, such as edge inferencing -and remote monitoring. - -Uniquely for Feather-compatible boards, Swan is designed to satisfy -developers' needs that span from early prototyping through high-volume -deployment. Developers may begin to use Swan in conjunction with -Adafruit's myriad sensors and FeatherWing-compatible carriers. -Due to its novel design, for high-volume deployment the low-cost Swan -can also be soldered directly to a parent PCB integrating those sensors, -utilizing the full range of Swan's I/O capabilities. - -The board has three independent power options-USB, Battery, or Line power- -and provides a software-switchable 2 Amp regulator for powering external -sensors. When operating in its low-power operating mode, the entire Swan -board commonly draws only about 8uA while retaining all of its memory, -making it quite suitable for battery-powered devices. - -The Swan board features an ARM Cortex-M4 based STM32L4R5ZI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the board: - -- STM32 microcontroller in WLCSP144 package -- 2MB of flash and 640KB of RAM -- Two types of extension resources: - - - Adafruit Feather-compatible connectivity - - Access to 36 additional STM32 pins (beyond the Feather pins) via 0.05" castellated edge headers - -- On-board ST-LINKV3 debugger/programmer with SWD connector - -- One Red User LED (LD1) -- Two push-buttons: USER and RESET - -- Castellated-edge access to 55 GPIO ports including: - - - 8 analog - - 16 digital - - 4x I2C, 3x SPI - - USB OTG full speed - - 1x 14-channel DMA - - tRNG - - 12-bit ADC, 2 x 12-bit DAC - - low-power RTC, and CRC calculation peripherals - -.. image:: img/swan.jpg - :align: center - :alt: Blues Wireless Swan - -More information about the board can be found at the `Swan Product Page`_. - -Hardware -******** - -The STM32L4R5ZI SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode - and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive - real-time accelerator (ART Accelerator) allowing 0-wait-state - execution from Flash memory, frequency up to 120 MHz, MPU, 150 - DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions - -- Memories - - - 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection - - 640 Kbytes of SRAM including 64 Kbytes with hardware parity check - - External memory interface for static memories supporting SRAM, - PSRAM, NOR, NAND and FRAM memories - - 2 x OctoSPI memory interface - -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace - Macrocell (ETM) - -More information about Swan can be found here: - -- `Swan Quickstart Guide`_ -- `Swan Datasheet`_ - -Supported Features -================== - -The Zephyr Swan board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/swan_r5/swan_r5_defconfig`` - - -Connections and IOs -=================== - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- A0 : PA3 -- A1 : PA1 -- A2 : PC3 -- A3 : PC1 -- A4 : PC4 -- A5 : PC5 -- D4 : PE3 -- D5 : PE11 -- D6 : PE9 -- D9 : PD15 -- D10 : PA4 -- D11 : PA7 -- D12 : PA6 -- D13 : PA5 -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PD6 -- UART_3_TX : PB10 -- UART_3_RX : PB11 -- LPUART_TX : PG7 -- LPUART_RX : PG8 -- I2C_1_SCL : PB6 -- I2C_1_SDA : PB7 -- I2C_2_SCL : PF1 -- I2C_2_SDA : PF0 -- I2C_3_SCL : PC0 -- I2C_3_SDA : PC9 -- SPI_1_NSS : PA4 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- SPI_2_NSS : PD0 -- SPI_2_SCK : PD1 -- SPI_2_MISO : PB14 -- SPI_2_MOSI : PB15 -- SPI_3_NSS : PA15 -- SPI_3_SCK : PC10 -- SPI_3_MISO : PC11 -- SPI_3_MOSI : PC12 -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD1 : PE2 -- USB DM : PA11 -- USB DP : PA12 -- ADC1 : PA1 - -System Clock ------------- - -Swan System Clock could be driven by internal or external -oscillator, as well as main PLL clock. By default, the System clock is -driven by the PLL clock at 80MHz, driven by a 16MHz high speed -internal oscillator. - -Serial Port ------------ - -Swan has 4 U(S)ARTs. The Zephyr console output is -assigned to LPUART. Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Connect Swan to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Swan: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: swan_r5 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -References -********** - -.. _Swan Product Page: - https://blues.io/products/swan - -.. _Swan Quickstart Guide: - https://dev.blues.io/start/swan/swan-quickstart - -.. _Swan Datasheet: - https://dev.blues.io/hardware/swan-datasheet/ diff --git a/boards/arm/tdk_robokit1/Kconfig.board b/boards/arm/tdk_robokit1/Kconfig.board deleted file mode 100644 index 16ea951fc20..00000000000 --- a/boards/arm/tdk_robokit1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# TDK RoboKit 1 Board Options - -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_TDK_ROBOKIT1 - bool "TDK RoboKit1 Board" - depends on SOC_PART_NUMBER_SAME70Q21 || SOC_PART_NUMBER_SAME70Q21B diff --git a/boards/arm/tdk_robokit1/Kconfig.defconfig b/boards/arm/tdk_robokit1/Kconfig.defconfig deleted file mode 100644 index eab856c9089..00000000000 --- a/boards/arm/tdk_robokit1/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# TDK RoboKit1 Configuration - -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_TDK_ROBOKIT1 - -config BOARD - default "tdk_robotkit1" - -endif # BOARD_TDK_ROBOKIT1 diff --git a/boards/arm/tdk_robokit1/board.cmake b/boards/arm/tdk_robokit1/board.cmake deleted file mode 100644 index 975b58dbcb1..00000000000 --- a/boards/arm/tdk_robokit1/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=ATSAME70Q21") -board_runner_args(openocd --cmd-post-verify "atsamv gpnvm set 1") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/tdk_robokit1/doc/index.rst b/boards/arm/tdk_robokit1/doc/index.rst deleted file mode 100644 index a34408c3baf..00000000000 --- a/boards/arm/tdk_robokit1/doc/index.rst +++ /dev/null @@ -1,184 +0,0 @@ -.. _tdk_robokit1: - -TDK RoboKit 1 -############# - -Overview -******** - -The TDK RoboKit1 is a development board for use primarily with ROS2 and provides a large -number of small ground robotics useful sensors including chirp sensors for time of flight -(e.g. ultrasonic obstacle detection). - -It pairs a 300MHz Cortex-M7 ATSAME70Q21 with an array of TDK sensors and pin headers useful for robotics. - -.. image:: img/tdk_robokit1.jpg - :align: center - :alt: TDK RoboKit1 - -Hardware -******** - -- ATSAME70Q21 ARM Cortex-M7 Processor -- 12 MHz crystal oscillator (Pres) -- 32.768 kHz crystal oscillator -- Micro-AB USB device -- Micro-AB USB debug (Microchip EDBG) interface supporting CMSIS-DAP, Virtual COM Port and Data -- JTAG interface connector -- One reset pushbutton -- One red user LED -- TDK ICM 42688-P 6-Axis 32KHz IMU -- TDK ICP-10111 Pressure Sensor -- TDK NTC Thermistor for Temperature -- AKM AK09918C Magnetometer -- 2 TDK HVCi-4223 Cortex-M3 Dedicated Motor Controller -- 3 TDK ICS-43434 Stereo Microphones -- Connector for Industrial Dual IMU (TDK IIM-46230) -- TDK CH101 Ultrasonic Range Sensor Array (9 Connectors, comes with 3) - -Supported Features -================== - -The TDK RoboKit1 board supports the following hardware -features: - -.. list-table:: - : header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - GPIO - - :kconfig:option:`CONFIG_GPIO_SAM` - - :dtcompatible:`atmel,sam-gpio` - * - USART - - :kconfig:option:`CONFIG_USART_SAM` - - :dtcompatible:`atmel,sam-usart` - * - UART - - :kconfig:option:`CONFIG_UART_SAM` - - :dtcompatible:`atmel,sam-uart` - * - SPI - - :kconfig:option:`CONFIG_SPI_SAM` - - :dtcompatible:`atmel,sam-spi` - * - I2C - - :kconfig:option:`CONFIG_I2C_SAM_TWIHS` - - :dtcompatible:`atmel,sam-i2c-twihs` - * - I2S - - :kconfig:option:`CONFIG_I2S_SAM_SSC` - - :dtcompatible:`atmel,sam-ssc` - * - ADC - - :kconfig:option:`CONFIG_ADC_SAM_AFEC` - - :dtcompatible:`atmel,sam-afec` - * - DAC - - :kconfig:option:`CONFIG_DAC_SAM` - - :dtcompatible:`atmel,sam-dac` - * - PWM - - :kconfig:option:`CONFIG_PWM_SAM` - - :dtcompatible:`atmel,sam-pwm` - * - CAN - - :kconfig:option:`CONFIG_CAN_SAM` - - :dtcompatible:`atmel,sam-can` - * - USB - - :kconfig:option:`CONFIG_USB_DC_SAM_USBHS` - - :dtcompatible:`atmel,sam-usbhs` - * - WATCHDOG - - :kconfig:option:`CONFIG_WDT_SAM` - - :dtcompatible:`atmel,sam-watchdog` - * - NVIC - - N/A - - :dtcompatible:`arm,v7m-nvic` - * - SYSTICK - - N/A - - N/A - * - COUNTER - - :kconfig:option:`CONFIG_COUNTER_SAM_TC` - - :dtcompatible:`atmel,sam-tc` - * - DMA - - :kconfig:option:`CONFIG_DMA_SAM_XDMAC` - - :dtcompatible:`atmel,sam-xdmac` - * - ENTROPY - - :kconfig:option:`CONFIG_ENTROPY_SAM_RNG` - - :dtcompatible:`atmel,sam-trng` - * - HWINFO (reset cause) - - :kconfig:option:`CONFIG_HWINFO_SAM_RSTC` - - :dtcompatible:`atmel,sam-rstc` - * - HWINFO (device id) - - :kconfig:option:`CONFIG_HWINFO_SAM` - - N/A - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/tdk_robokit1/tdk_robokit1_defconfig`. - -Connections and IOs -=================== - -The TDK RoboKit Hardware Guide has detailed information about board connections. - -System Clock -============ - -The SAM E70 MCU is configured to use the 12 MHz external oscillator on the board -with the on-chip PLL to generate a 300 MHz system clock. - -Serial Port -=========== - -The ATSAME70Q21 MCU has five UARTs and three USARTs. One of the UARTs is -configured for the console and is available as a Virtual COM Port via the USB2 connector. - -Programming and Debugging -************************* - -Flashing the Zephyr project onto SAM E70 MCU requires the `OpenOCD tool`_. -Both west flash and west debug commands should correctly work with both USB0 and USB1 -connected and the board powered. - -Flashing -======== - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the TDK RoboKit1 board to your host computer using the - USB debug port (USB1), USB2 for a serial console, and remaining micro USB for - power. Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: tdk_robokit1 - :goals: build flash - - You should see "Hello World! tdk_robokit1" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: tdk_robokit1 - :maybe-skip-config: - :goals: debug - -References -********** - -TDK RoboKit1 Product Page: - https://invensense.tdk.com/products/robokit1-dk/ - -.. _OpenOCD tool: - http://openocd.org/ diff --git a/boards/arm/tdk_robokit1/tdk_robokit1-common.dtsi b/boards/arm/tdk_robokit1/tdk_robokit1-common.dtsi deleted file mode 100644 index 5fc1bf4cb9f..00000000000 --- a/boards/arm/tdk_robokit1/tdk_robokit1-common.dtsi +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "tdk_robokit1-pinctrl.dtsi" - -/ { - aliases { - led0 = &led_0; - magn0 = &akm09918c; - accel0 = &icm42688; - die-temp0 = &icm42688; - ambient-temp0 = &temp_sensor; - }; - - chosen { - zephyr,console = &uart2; - zephyr,shell-uart = &uart2; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - led_0: led_0 { - gpios = <&pioa 11 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - led_1: led_1 { - gpios = <&pioa 12 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - led_2: led_2 { - gpios = <&pioa 13 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - led_3: led_3 { - gpios = <&pioa 14 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - }; - - temp_sensor: ambient_temp_sensor { - compatible = "epcos,b57861s0103a039"; - io-channels = <&spi_adc 0>; - pullup-uv = <3300000>; - pullup-ohm = <0>; - pulldown-ohm = <10000>; - connected-positive; - }; -}; - -&cpu0 { - clock-frequency = <300000000>; -}; - -&afec0 { - pinctrl-0 = <&afec0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&dacc { - status = "okay"; -}; - -&twihs0 { - pinctrl-0 = <&twihs0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&twihs1 { - pinctrl-0 = <&twihs1_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&twihs2 { - pinctrl-0 = <&twihs2_default>; - pinctrl-names = "default"; - status = "okay"; - akm09918c: akm09918c@c { - compatible = "asahi-kasei,akm09918c"; - reg = <0xc>; - }; -}; - -&spi0 { - pinctrl-0 = <&spi0_default>; - pinctrl-names = "default"; - dmas = <&xdmac 0 DMA_PERID_SPI0_TX>, <&xdmac 1 DMA_PERID_SPI0_RX>; - dma-names = "tx", "rx"; - cs-gpios =<&pioa 31 GPIO_ACTIVE_LOW>, - <&pioc 31 GPIO_ACTIVE_LOW>; - status = "okay"; - - icm42688: icm42688p@0 { - compatible = "invensense,icm42688"; - reg = <0>; - int-gpios = <&pioc 5 GPIO_ACTIVE_HIGH>; - spi-max-frequency = <24000000>; - accel-hz = <32000>; - accel-fs = <16>; - gyro-hz = <32000>; - gyro-fs = <2000>; - }; - spi_adc: adc@1 { - compatible = "ti,ads7052"; - reg = <1>; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <24000000>; - channel@0 { - reg = <0>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_VDD_1"; - zephyr,vref-mv = <3300>; - zephyr,acquisition-time = ; - zephyr,resolution = <14>; - }; - }; -}; - -&spi1 { - pinctrl-0 = <&spi1_default>; - pinctrl-names = "default"; - cs-gpios = <&pioc 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart0 { - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usart2 { - current-speed = <115200>; - pinctrl-0 = <&usart2_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -zephyr_udc0: &usbhs { - status = "okay"; -}; - -&mdio { - pinctrl-0 = <&mdio_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm0 { - pinctrl-0 = <&pwm_default>; - pinctrl-names = "default"; - status = "okay"; -}; - - -&xdmac { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * The first half of sector 0 (64 kbytes) - * is reserved for the bootloader - */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x00010000>; - read-only; - }; - - /* From sector 1 to sector 7 (included): slot0 (896 kbytes) */ - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 0x000e0000>; - }; - - /* From sector 8 to sector 14 (included): slot1 (896 kbytes) */ - slot1_partition: partition@100000 { - label = "image-1"; - reg = <0x00100000 0x000e0000>; - }; - - /* Sector 15: scratch (128 kbytes) */ - scratch_partition: partition@1e0000 { - label = "image-scratch"; - reg = <0x001e0000 0x00020000>; - }; - }; -}; diff --git a/boards/arm/tdk_robokit1/tdk_robokit1.dts b/boards/arm/tdk_robokit1/tdk_robokit1.dts deleted file mode 100644 index a8763609e9b..00000000000 --- a/boards/arm/tdk_robokit1/tdk_robokit1.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -#include "tdk_robokit1-common.dtsi" - -/ { - model = "TDK RoboKit1"; - compatible = "tdk,robokit1", "atmel,same70q21", "atmel,same70"; -}; diff --git a/boards/arm/tdk_robokit1/tdk_robokit1.yaml b/boards/arm/tdk_robokit1/tdk_robokit1.yaml deleted file mode 100644 index 4c4d8b19e13..00000000000 --- a/boards/arm/tdk_robokit1/tdk_robokit1.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: tdk_robokit1 -name: TDK RoboKit1 -type: mcu -arch: arm -ram: 384 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - dma - - i2c - - gpio - - spi - - watchdog - - usb_device - - pwm - - can - - hwinfo -vendor: tdk diff --git a/boards/arm/tdk_robokit1/tdk_robokit1_defconfig b/boards/arm/tdk_robokit1/tdk_robokit1_defconfig deleted file mode 100644 index f5df64df2a5..00000000000 --- a/boards/arm/tdk_robokit1/tdk_robokit1_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAME70=y -CONFIG_SOC_PART_NUMBER_SAME70Q21B=y -CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK=y -CONFIG_SOC_ATMEL_SAME70_PLLA_MULA=24 -CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA=1 -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_BOARD_TDK_ROBOKIT1=y -CONFIG_WDT_DISABLE_AT_BOOT=y -CONFIG_BUILD_OUTPUT_HEX=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/teensy4/CMakeLists.txt b/boards/arm/teensy4/CMakeLists.txt deleted file mode 100644 index 56f5eb005ab..00000000000 --- a/boards/arm/teensy4/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) 2020, Bernhard Kraemer -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_library() -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(flexspi_nor_config.c) - zephyr_library_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA teensy4_sdram_ini_dcd.c) -endif() diff --git a/boards/arm/teensy4/Kconfig.board b/boards/arm/teensy4/Kconfig.board deleted file mode 100644 index f0f5f55a8e0..00000000000 --- a/boards/arm/teensy4/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2020, Bernhard Kraemer -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_TEENSY40 - bool "PJRC TEENSY40" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A - -config BOARD_TEENSY41 - bool "PJRC TEENSY41" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVJ6A diff --git a/boards/arm/teensy4/Kconfig.defconfig b/boards/arm/teensy4/Kconfig.defconfig deleted file mode 100644 index 5e8eac0d0f0..00000000000 --- a/boards/arm/teensy4/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (c) 2020, Bernhard Kraemer -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_TEENSY40 || BOARD_TEENSY41 - -config BUILD_OUTPUT_HEX - bool - default y - -config BOARD - default "teensy40" if BOARD_TEENSY40 - default "teensy41" if BOARD_TEENSY41 - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_TEENSY40 || BOARD_TEENSY41 diff --git a/boards/arm/teensy4/flexspi_nor_config.c b/boards/arm/teensy4/flexspi_nor_config.c deleted file mode 100644 index 6420e446bd9..00000000000 --- a/boards/arm/teensy4/flexspi_nor_config.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2019, MADMACHINE LIMITED - * Copyright (c) 2021, Bernhard Kraemer - * - * refer to hal_nxp board file - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -const struct flexspi_nor_config_t Qspiflash_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = - kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = 8u * 1024u * 1024u, - .lookupTable = { - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0xEB, RADDR_SDR, - FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, - 0x06, READ_SDR, - FLEXSPI_4PAD, 0x04), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 256u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */ diff --git a/boards/arm/thingy52_nrf52832/CMakeLists.txt b/boards/arm/thingy52_nrf52832/CMakeLists.txt deleted file mode 100644 index 8faced71438..00000000000 --- a/boards/arm/thingy52_nrf52832/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_CCS811) -zephyr_library() -zephyr_library_sources(board.c) -endif() diff --git a/boards/arm/thingy52_nrf52832/Kconfig b/boards/arm/thingy52_nrf52832/Kconfig deleted file mode 100644 index 318d486efef..00000000000 --- a/boards/arm/thingy52_nrf52832/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Thingy52 NRF52832 board configuration - -# Copyright (c) 2018 Aapo Vienamo -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_THINGY52_NRF52832 - -config BOARD_CCS_VDD_PWR_CTRL_INIT_PRIORITY - int "CCS_VDD power rail init priority" - default 85 - depends on GPIO_SX1509B - help - Initialization priority for the CCS_VDD power rail. This powers the - CCS811 gas sensor. The value has to be greater than - BOARD_VDD_PWR_CTRL_INIT_PRIORITY, but smaller than SENSOR_INIT_PRIORITY. - -endif # BOARD_THINGY52_NRF52832 diff --git a/boards/arm/thingy52_nrf52832/Kconfig.board b/boards/arm/thingy52_nrf52832/Kconfig.board deleted file mode 100644 index c369b95554b..00000000000 --- a/boards/arm/thingy52_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Thingy52 NRF52832 board configuration - -# Copyright (c) 2018 Aapo Vienamo -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_THINGY52_NRF52832 - bool "Thingy52 NRF52832" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/thingy52_nrf52832/Kconfig.defconfig b/boards/arm/thingy52_nrf52832/Kconfig.defconfig deleted file mode 100644 index d0002ec5e91..00000000000 --- a/boards/arm/thingy52_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Thingy52 NRF52832 board configuration - -# Copyright (c) 2018 Aapo Vienamo -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_THINGY52_NRF52832 - -config BOARD - default "thingy52_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_THINGY52_NRF52832 diff --git a/boards/arm/thingy52_nrf52832/doc/index.rst b/boards/arm/thingy52_nrf52832/doc/index.rst deleted file mode 100644 index f90d38a399a..00000000000 --- a/boards/arm/thingy52_nrf52832/doc/index.rst +++ /dev/null @@ -1,388 +0,0 @@ -.. _thingy52_nrf52832: - -Thingy:52 -######### - -Overview -******** - -Zephyr uses the thingy52_nrf52832 (PCA20020) board configuration for building -for the Thingy:52 board. The board has the nRF52832 MCU with ARM Cortex-M4F -processor, a set of environmental sensors, a pushbutton, and two RGB LEDs. - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* Gas sensor -* :abbr:`GPIO (General Purpose Input Output)` -* GPIO Expander -* Humidity and temperature sensor -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* Pressure sensor -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* RGB LEDs -* :abbr:`RTC (nRF RTC System Clock)` -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/thingy52_nrf52832.jpg - :align: center - :alt: nRF52 Thingy:52 - - nRF52 Thingy:52 (Credit: Nordic Semiconductor) - -More information about the board can be found at the `nRF52 DK website`_. The -`Nordic Semiconductor Infocenter`_ contains the processor's information and the -datasheet. - - -Hardware -******** - -Thingy:52 has the following features: - -* Two RGB LEDs -* CO2 and TVOC sensor -* Humidity and temperature sensor -* Color sensor -* I2C GPIO expander -* Provisions for a pin header and I2C and serial connectors -* Bluetooth radio - -Supported Features -================== - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| Gas | on-board | ccs811 | -| Sensor | | | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GPIO Exp | on-board | sx1509b | -+-----------+------------+----------------------+ -| Humidity | on-board | hts221 | -| and Temp | | | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| Pressure | on-board | lps22hb_press | -| and Temp | | | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -Lightwell RGB LED ------------------ -The LED is driven by the SX1509B GPIO expander chip (device name GPIO_P0). - -+-------------------+-------------+ -| GPIO Expander Pin | LED Channel | -+===================+=============+ -| 5 | Green | -+-------------------+-------------+ -| 6 | Blue | -+-------------------+-------------+ -| 7 | Red | -+-------------------+-------------+ - -Button ------- - -Thingy:52 has a pushbutton, connected to the P0.11 SOC GPIO pin. - -Serial ------- - -By default the system UART has the following pin configuration: - -+---------+--------+ -| SOC Pin | Signal | -+=========+========+ -| P0.02 | TX | -+---------+--------+ -| P0.03 | RX | -+---------+--------+ - -The pins can be found on the P4 and P6 connectors. The system UART console -uses these pins by default. - -Internal I2C Bus ----------------- - -The internal I2C bus (I2C_0) is not routed to any of the external connectors, -but most of the on-board devices are accessed through it. The following pins -have been assigned to the bus: - -+---------+---------+ -| SOC Pin | Signal | -+=========+=========+ -| P0.07 | SDA | -+---------+---------+ -| P0.08 | SCL | -+---------+---------+ - -The following devices are attached to the bus. - -+----------+---------+ -| Device | Address | -+==========+=========+ -| SX1509B | 0x3e | -+----------+---------+ -| LPS22HB | 0x5c | -+----------+---------+ -| HTS221 | 0x5f | -+----------+---------+ -| CCS811 | 0x5a | -+----------+---------+ - -External I2C Bus ----------------- - -The external I2C bus (I2C_1) can be found on the P4 header and the P5 and P7 -connectors. - -+---------+---------+ -| SOC Pin | Signal | -+=========+=========+ -| P0.14 | SDA_EXT | -+---------+---------+ -| P0.15 | SCL_EXT | -+---------+---------+ - -Pin Header ----------- - -This is the pinout of the P4 pin header. Some of the SOC GPIO pins and I2C GPIO -expander pins are accessible through it. It also allows attaching external -devices to the four on-board N-channel MOSFET transistors. - -+-----+---------------+-----------------------+ -| Pin | Device | Signal / Device Pin | -+=====+===============+=======================+ -| 1 | SOC | SCL_EXT / P0.15 | -+-----+---------------+-----------------------+ -| 2 | SOC | SDA_EXT / P0.14 | -+-----+---------------+-----------------------+ -| 3 | SOC | ANA/DIG0 / P0.02 | -+-----+---------------+-----------------------+ -| 4 | SOC | ANA/DIG1 / P0.03 | -+-----+---------------+-----------------------+ -| 5 | SOC | ANA/DIG2 / P0.04 | -+-----+---------------+-----------------------+ -| 6 | | GND | -+-----+---------------+-----------------------+ -| 7 | GPIO Expander | Pin 0 | -+-----+---------------+-----------------------+ -| 8 | GPIO Expander | Pin 1 | -+-----+---------------+-----------------------+ -| 9 | GPIO Expander | Pin 2 | -+-----+---------------+-----------------------+ -| 10 | GPIO Expander | Pin 3 | -+-----+---------------+-----------------------+ -| 11 | MOSFET 1 | Drain | -+-----+---------------+-----------------------+ -| 12 | MOSFET 1 | Source | -+-----+---------------+-----------------------+ -| 13 | MOSFET 2 | Drain | -+-----+---------------+-----------------------+ -| 14 | MOSFET 2 | Source | -+-----+---------------+-----------------------+ -| 15 | MOSFET 3 | Drain | -+-----+---------------+-----------------------+ -| 16 | MOSFET 3 | Source | -+-----+---------------+-----------------------+ -| 17 | MOSFET 4 | Drain | -+-----+---------------+-----------------------+ -| 18 | MOSFET 4 | Source | -+-----+---------------+-----------------------+ -| 19 | | VDD | -+-----+---------------+-----------------------+ -| 20 | | GND | -+-----+---------------+-----------------------+ - -MOSFETs -~~~~~~~ - -The MOSFETs are attached to the following SOC GPIO pins: - -+----------+----------+ -| Device | Gate Pin | -+==========+==========+ -| MOSFET 1 | P0.18 | -+----------+----------+ -| MOSFET 2 | P0.19 | -+----------+----------+ -| MOSFET 3 | P0.20 | -+----------+----------+ -| MOSFET 4 | P0.21 | -+----------+----------+ - -Power Rails ------------ - -Thing:52 has multiple power rails. The necessary rails for the currently -supported devices are listed here. - -+---------+--------------+----------------------+ -| Name | Derived from | Controlled by | -+=========+==============+======================+ -| VREG | The battery | Always on | -+---------+--------------+----------------------+ -| VDD_nRF | VREG | Always on | -+---------+--------------+----------------------+ -| VDD | VREG | SOC pin P0.30 | -+---------+--------------+----------------------+ -| VDD_CCS | VDD | GPIO expander pin 10 | -+---------+--------------+----------------------+ - -Due to the dependencies of the power rails, multiple rails may need to be -powered for a given device to turn on. The correct order of powering up the -rails is the order of the rails down the dependency chain. For example, in order -to power the CCS811 gas sensor, VDD has to be turned on first and VDD_CCS after -it. Here's a list of the devices and their power rails: - -+----------+---------+ -| Device | Rail | -+==========+=========+ -| nRF52832 | VDD_nRF | -+----------+---------+ -| SX1509B | VDD | -+----------+---------+ -| LPS22HB | VDD | -+----------+---------+ -| HTS221 | VDD | -+----------+---------+ -| CCS811 | VDD_CCS | -+----------+---------+ - -Sensors -------- - -+----------+---------------------------------+-------+-------------+------------+ -| Device | Function | Bus | I2C Address | Power Rail | -+==========+=================================+=======+=============+============+ -| LPS22HB | Pressure and Temperature sensor | I2C_0 | 0x5c | VDD | -+----------+---------------------------------+-------+-------------+------------+ -| HTS221 | Humidity and Temperature sensor | I2C_0 | 0x5f | VDD | -+----------+---------------------------------+-------+-------------+------------+ -| CCS811 | Gas sensor | I2C_0 | 0x5a | VDD_CCS | -+----------+---------------------------------+-------+-------------+------------+ - -Misc. Device Pins ------------------ - -SX1509B -~~~~~~~ - -+---------------+-------------------+ -| Device Signal | SOC Pin | -+===============+===================+ -| SX_OSCIO | P0.05 | -+---------------+-------------------+ -| SX_RESET | P0.16 | -+---------------+-------------------+ - -LPS22HB -~~~~~~~ - -+---------------+-------------------+ -| Sensor Signal | SOC Pin | -+===============+===================+ -| LPS_INT | P0.23 | -+---------------+-------------------+ - -HTS221 -~~~~~~ - -+---------------+-------------------+ -| Sensor Signal | SOC Pin | -+===============+===================+ -| HTS_INT | P0.24 | -+---------------+-------------------+ - -CCS811 -~~~~~~ - -+---------------+-------------------+ -| Sensor Signal | GPIO Expander Pin | -+===============+===================+ -| CCS_RESET | 11 | -+---------------+-------------------+ -| CCS_WAKE | 12 | -+---------------+-------------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Flashing Zephyr onto Thingy:52 requires an external J-Link programmer. The -programmer is attached to the P9 programming header. - - -Debugging -========= - -Thingy:52 does not have an on-board J-Link debug IC as some other nRF5 -development boards, however, instructions from the :ref:`nordic_segger` page -also apply to this board, with the additional step of connecting an external -debugger. A development board with a Debug out connector such as the -:ref:`nrf52dk_nrf52832` can be used as a debugger with Thingy:52. - -Testing board features -********************** - -The green lightwell LED can be tested with the :zephyr:code-sample:`blinky` example. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: thingy52_nrf52832 - :goals: build flash - - - -Also the temperature and humidity sensor can be tested with the :ref:`hts221` -sample. - -.. zephyr-app-commands:: - :zephyr-app: samples/sensor/hts221 - :board: thingy52_nrf52832 - :goals: build flash - -References -********** - -.. target-notes:: - -.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/Nordic-Thingy-52 -.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/thingy52_nrf52832/thingy52_nrf52832_defconfig b/boards/arm/thingy52_nrf52832/thingy52_nrf52832_defconfig deleted file mode 100644 index 2bdadf855de..00000000000 --- a/boards/arm/thingy52_nrf52832/thingy52_nrf52832_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_THINGY52_NRF52832=y - -# Enable regulators -CONFIG_REGULATOR=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable RTT -CONFIG_USE_SEGGER_RTT=y - -# enable regulators (init priority adjusted so that they -# are turned before I2C GPIO expander) -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_INIT_PRIORITY=45 - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/thingy53_nrf5340/CMakeLists.txt b/boards/arm/thingy53_nrf5340/CMakeLists.txt deleted file mode 100644 index 6a52022fad7..00000000000 --- a/boards/arm/thingy53_nrf5340/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if (CONFIG_BOARD_THINGY53_NRF5340_CPUAPP OR CONFIG_BOARD_THINGY53_NRF5340_CPUAPP_NS) - zephyr_library() - zephyr_library_sources(board.c) -endif() diff --git a/boards/arm/thingy53_nrf5340/Kconfig b/boards/arm/thingy53_nrf5340/Kconfig deleted file mode 100644 index 116fd1c8edb..00000000000 --- a/boards/arm/thingy53_nrf5340/Kconfig +++ /dev/null @@ -1,74 +0,0 @@ -# Thingy53 NRF5340 board configuration - -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config THINGY53_INIT_PRIORITY - int "Init priority" - default 79 - help - Initialization priority of the Thingy:53. - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "USB CDC" - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "thingy53_nrf5340_cpunet" - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS - -if BOARD_THINGY53_NRF5340_CPUNET - -config DOMAIN_CPUAPP_BOARD - string - default "thingy53_nrf5340_cpuapp" - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - -endif # BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/arm/thingy53_nrf5340/Kconfig.board b/boards/arm/thingy53_nrf5340/Kconfig.board deleted file mode 100644 index 0e472778a32..00000000000 --- a/boards/arm/thingy53_nrf5340/Kconfig.board +++ /dev/null @@ -1,21 +0,0 @@ -# Thingy53 NRF5340 board configuration - -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_THINGY53_NRF5340_CPUAPP - bool "Thingy53 nRF5340 Application MCU" - -config BOARD_THINGY53_NRF5340_CPUAPP_NS - bool "Thingy53 nRF5340 Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -if SOC_NRF5340_CPUNET_QKAA - -config BOARD_THINGY53_NRF5340_CPUNET - bool "Thingy53 nRF5340 Network MCU" - -endif # SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/thingy53_nrf5340/Kconfig.defconfig b/boards/arm/thingy53_nrf5340/Kconfig.defconfig deleted file mode 100644 index 12f1e5bbdc9..00000000000 --- a/boards/arm/thingy53_nrf5340/Kconfig.defconfig +++ /dev/null @@ -1,152 +0,0 @@ -# Thingy53 NRF5340 board configuration - -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS - -config BOARD - default "thingy53_nrf5340_cpuapp" - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_THINGY53_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_THINGY53_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_THINGY53_NRF5340_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_THINGY53_NRF5340_CPUAPP_NS - -if !TRUSTED_EXECUTION_SECURE - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -config BT_HAS_HCI_VS - default BT - -config USB_NRFX_ATTACHED_EVENT_DELAY - default 700 if USB_DEVICE_DRIVER - -config I2C - default y - -config SPI - default y - -config REGULATOR - default y - -endif # !TRUSTED_EXECUTION_SECURE - -if BOARD_SERIAL_BACKEND_CDC_ACM - -config USB_DEVICE_PRODUCT - default "Thingy:53 Application" - -config USB_DEVICE_VID - default 0x1915 - -config USB_DEVICE_PID - default 0x530C - -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default y - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if !MCUBOOT - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -config USB_DEVICE_REMOTE_WAKEUP - default n - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -# Set USB log level to error only -choice USB_DEVICE_LOG_LEVEL_CHOICE - default USB_DEVICE_LOG_LEVEL_ERR -endchoice - -# Wait 4000ms at startup for logging -config LOG_PROCESS_THREAD_STARTUP_DELAY_MS - default 4000 - -endif # LOG - -endif # BOARD_SERIAL_BACKEND_CDC_ACM - -endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS - -if BOARD_THINGY53_NRF5340_CPUNET - -config BOARD - default "thingy53_nrf5340_cpunet" - -config BT_CTLR - default BT - -config BT_ECC - default BT - -endif # BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/arm/thingy53_nrf5340/board.cmake b/boards/arm/thingy53_nrf5340/board.cmake deleted file mode 100644 index 75edf877f10..00000000000 --- a/boards/arm/thingy53_nrf5340/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_THINGY53_NRF5340_CPUAPP OR CONFIG_BOARD_THINGY53_NRF5340_CPUAPP_NS) -board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_BOARD_THINGY53_NRF5340_CPUNET) -board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/thingy53_nrf5340/doc/index.rst b/boards/arm/thingy53_nrf5340/doc/index.rst deleted file mode 100644 index 4544ea7ed79..00000000000 --- a/boards/arm/thingy53_nrf5340/doc/index.rst +++ /dev/null @@ -1,51 +0,0 @@ -.. _thingy53_nrf5340: - -Thingy:53 -######### - -Overview -******** - -Zephyr uses the thingy53_nrf5340 board configuration for building -for the Thingy:53 board. The board has the nRF5340 MCU processor, a set of -environmental sensors, a pushbutton, and RGB LED. - -The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with: - -* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and - Armv8-M Security Extension, running at up to 128 MHz, referred to as - the **application core** -* a secondary Arm Cortex-M33 core, with a reduced feature set, running at - a fixed 64 MHz, referred to as the **network core**. - -The nrf5340dk_nrf5340_cpuapp build target provides support for the application -core on the nRF5340 SoC. The nrf5340dk_nrf5340_cpunet build target provides -support for the network core on the nRF5340 SoC. - -The `Nordic Semiconductor Infocenter`_ contains the processor's information and -the datasheet. - -Programming and Debugging -************************* - -Flashing -======== - -Flashing Zephyr onto Thingy:53 requires an external J-Link programmer. The -programmer is attached to the P9 programming header. - -Debugging -========= - -Thingy:53 does not have an on-board J-Link debug IC as some other nRF5 -development boards, however, instructions from the :ref:`nordic_segger` page -also apply to this board, with the additional step of connecting an external -debugger. A development board with a Debug out connector such as the -:ref:`nrf5340dk_nrf5340` can be used as a debugger with Thingy:53. - -References -********** - -.. target-notes:: - -.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet_defconfig b/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet_defconfig deleted file mode 100644 index 33dc6fbdedd..00000000000 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_THINGY53_NRF5340_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable GPIO -CONFIG_GPIO=y diff --git a/boards/arm/twr_ke18f/Kconfig.board b/boards/arm/twr_ke18f/Kconfig.board deleted file mode 100644 index 42713ad2c5f..00000000000 --- a/boards/arm/twr_ke18f/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# TWR-KE18F board configuration - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_TWR_KE18F - bool "NXP TWR-KE18F" - depends on SOC_SERIES_KINETIS_KE1XF - select SOC_PART_NUMBER_MKE18F512VLL16 diff --git a/boards/arm/twr_ke18f/Kconfig.defconfig b/boards/arm/twr_ke18f/Kconfig.defconfig deleted file mode 100644 index ddf4f9274eb..00000000000 --- a/boards/arm/twr_ke18f/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# TWR-KE18F board - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_TWR_KE18F - -config BOARD - default "twr_ke18f" - -config I2C_MCUX_LPI2C_BUS_RECOVERY - default y - depends on I2C_MCUX_LPI2C && PINCTRL - -# The KE1xF has 8 MPU regions, which is not enough for both HW stack protection -# and userspace. Only enable HW stack protection if userspace is not enabled. -config HW_STACK_PROTECTION - default y if !USERSPACE - -endif # BOARD_TWR_KE18F diff --git a/boards/arm/twr_ke18f/doc/index.rst b/boards/arm/twr_ke18f/doc/index.rst deleted file mode 100644 index 04aa94f0dfe..00000000000 --- a/boards/arm/twr_ke18f/doc/index.rst +++ /dev/null @@ -1,254 +0,0 @@ -.. _twr_ke18f: - -NXP TWR-KE18F -############# - -Overview -******** - -The TWR-KE18F is a development board for NXP Kinetis KE1xF 32-bit -MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, -running an open source bootloader, offers options for serial -communication, flash programming, and run-control debugging. - -.. figure:: TWR-KE18F-DEVICE.jpg - :align: center - :alt: TWR-KE18F - - TWR-KE18F (Credit: NXP) - -Hardware -******** - -- MKE18F512VLL16 MCU (up to 168 MHz, 512 KB flash memory, 64 KB RAM, - and 100 Low profile Quad Flat Package (LQFP)) -- 3.3 V or 5 V MCU operation -- 6-axis FXOS8700CQ digital accelerometer and magnetometer -- RGB LED -- Four user LEDs -- Two user push-buttons -- Potentiometer -- Thermistor -- Infrared port (IrDA) -- CAN pin header -- Flex I/O pin header - -For more information about the KE1xF SoC and the TWR-KE18F board, see -these NXP reference documents: - -- `KE1xF Website`_ -- `KE1xF Datasheet`_ -- `KE1xF Reference Manual`_ -- `TWR-KE18F Website`_ -- `TWR-KE18F User Guide`_ -- `TWR-KE18F Schematics`_ - -Supported Features -================== - -The twr_ke18f board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | trigger supported with H/W mods | -| | | explained below; | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| ACMP | on-chip | analog comparator | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/twr_ke18f/twr_ke18f_defconfig``. - -Other hardware features are not currently supported by the port. - -System Clock -============ - -The KE18 SoC is configured to use the 8 MHz external oscillator on the -board with the on-chip PLL to generate a 120 MHz system clock. - -Serial Port -=========== - -The KE18 SoC has three UARTs. UART0 is configured for the console. The -remaining UARTs are not used. - -Accelerometer and magnetometer -============================== - -The TWR-KE18F board by default only supports polling the FXOS8700 -accelerometer and magnetometer for sensor values -(``CONFIG_FXOS8700_TRIGGER_NONE=y``). - -In order to support FXOS8700 triggers (interrupts) the 0 ohm resistors -``R47`` and ``R57`` must be mounted on the TWR-KE18F board. The -devicetree must also be modified to describe the FXOS8700 interrupt -GPIOs: - -.. code-block:: devicetree - - /dts-v1/; - - &fxos8700 { - int1-gpios = <&gpioa 14 0>; - int2-gpios = <&gpioc 17 0>; - }; - -Finally, a trigger option must be enabled in Kconfig (either -``FXOS8700_TRIGGER_GLOBAL_THREAD=y`` or -``FXOS8700_TRIGGER_OWN_THREAD=y``). - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Early versions of this board have an outdated version of the OpenSDA bootloader -and require an update. Please see the `DAPLink Bootloader Update`_ page for -instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. - -Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) ------------------------------------------------------------------- - -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program -the `OpenSDA DAPLink TWR-KE18F Firmware`_. - -Option 2: :ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Firmware for TWR-KE18F`_. - -Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and -``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the -default runner from pyOCD to J-Link: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: twr_ke18f - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J2. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: twr_ke18f - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! twr_ke18f - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: twr_ke18f - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! twr_ke18f - -.. _TWR-KE18F Website: - https://www.nxp.com/TWR-KE18F - -.. _TWR-KE18F User Guide: - https://www.nxp.com/docs/en/user-guide/TWRKE18FUG.pdf - -.. _TWR-KE18F Schematics: - https://www.nxp.com/webapp/Download?colCode=TWR-KE18F-SCH-DESIGNFILES - -.. _KE1xF Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/e-series5v-robustm0-plus-m4/kinetis-ke1xf-168mhz-performance-with-can-5v-microcontrollers-based-on-arm-cortex-m4:KE1xF - -.. _KE1xF Datasheet: - https://www.nxp.com/docs/en/data-sheet/KE1xFP100M168SF0.pdf - -.. _KE1xF Reference Manual: - https://www.nxp.com/docs/en/reference-manual/KE1xFP100M168SF0RM.pdf - -.. _DAPLink Bootloader Update: - https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ - -.. _OpenSDA DAPLink TWR-KE18F Firmware: - https://www.nxp.com/support/developer-resources/run-time-software/kinetis-developer-resources/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA#TWR-KE18F - -.. _OpenSDA J-Link Firmware for TWR-KE18F: - https://www.segger.com/downloads/jlink/OpenSDA_TWR-KE18F diff --git a/boards/arm/twr_ke18f/twr_ke18f_defconfig b/boards/arm/twr_ke18f/twr_ke18f_defconfig deleted file mode 100644 index 05247818cab..00000000000 --- a/boards/arm/twr_ke18f/twr_ke18f_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_KINETIS_KE1XF=y -CONFIG_SOC_MKE18F16=y -CONFIG_BOARD_TWR_KE18F=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_PINCTRL=y -CONFIG_GPIO=y - -# Enable MPU -CONFIG_ARM_MPU=y diff --git a/boards/arm/twr_kv58f220m/Kconfig.board b/boards/arm/twr_kv58f220m/Kconfig.board deleted file mode 100644 index a5ee3947f3f..00000000000 --- a/boards/arm/twr_kv58f220m/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# TWR-KV58F220M board configuration - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_TWR_KV58F220M - bool "NXP TWR-KV58F220M" - depends on SOC_SERIES_KINETIS_KV5X - select SOC_PART_NUMBER_MKV58F1M0VLQ24 diff --git a/boards/arm/twr_kv58f220m/Kconfig.defconfig b/boards/arm/twr_kv58f220m/Kconfig.defconfig deleted file mode 100644 index d9545c8762d..00000000000 --- a/boards/arm/twr_kv58f220m/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# TWR-KV58F220M board - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_TWR_KV58F220M - -config BOARD - default "twr_kv58f220m" - -config OSC_XTAL0_FREQ - default 50000000 - -config MCG_PRDIV0 - default 0x3 - -config MCG_VDIV0 - default 0x16 - -config MCG_FCRDIV - default 1 - -endif # BOARD_TWR_KV58F220M diff --git a/boards/arm/twr_kv58f220m/doc/index.rst b/boards/arm/twr_kv58f220m/doc/index.rst deleted file mode 100644 index f29129ecd76..00000000000 --- a/boards/arm/twr_kv58f220m/doc/index.rst +++ /dev/null @@ -1,200 +0,0 @@ -.. _twr_kv58f220m: - -NXP TWR-KV58F220M -################# - -Overview -******** - -The TWR-KV58F220M is a development board for NXP Kinetis KV5x 32-bit -MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, -running an open source bootloader, offers options for serial -communication, flash programming, and run-control debugging. - -.. figure:: twr_kv58f220m.jpg - :align: center - :alt: TWR-KV58F220M - - TWR-KV58F220M (Credit: NXP) - -Hardware -******** - -- MKV58F1M0VLQ24 MCU (up to 240 MHz, 1 MB flash memory, 256 KB RAM, - and 144 Low profile Quad Flat Package (LQFP)) -- 1.8 V or 3.3 V MCU operation -- 6-axis FXOS8700CQ digital accelerometer and magnetometer -- Four user LEDs -- Four user push-buttons -- Potentiometer -- Two general purpose TWRPI headers -- Motor pin header - -For more information about the KV5x SoC and the TWR-KV58F220M board, see -these NXP reference documents: - -- `KV5x Website`_ -- `KV5x Datasheet`_ -- `KV5x Reference Manual`_ -- `TWR-KV58F220M Website`_ -- `TWR-KV58F220M User Guide`_ -- `TWR-KV58F220M Schematics`_ - -Supported Features -================== - -The twr_kv58f220m board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/twr_kv58f220m/twr_kv58f220m_defconfig``. - -Other hardware features are not currently supported by the port. - -System Clock -============ - -The KV58 SoC is configured to use the 50 MHz external oscillator on the -board with the on-chip PLL to generate a 237.5 MHz system clock. - -Serial Port -=========== - -The KV58 SoC has six UARTs. UART0 is configured for the console. The -remaining UARTs are not used. - -Accelerometer and magnetometer -============================== - -The TWR-KV58F220M board by default only supports polling the FXOS8700 -accelerometer and magnetometer for sensor values -(``CONFIG_FXOS8700_TRIGGER_NONE=y``). - -In order to support FXOS8700 triggers (interrupts), shunts must be placed on -the jumpers ``J2`` and ``J9``. A trigger option also must be enabled in Kconfig -(either ``CONFIG_FXOS8700_TRIGGER_GLOBAL_THREAD=y`` or -``CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y``). - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -This board integrates an OpenSDA debug probe. However, it can currently only be -used for flashing the KV58 SoC by copying the compiled firmware to the USB Mass -Storage Device. The board cannot be debugged using the OpenSDA probe, since -pyOCD does not support the target. The OpenSDA J-Link firmware (as of release -2019-06-03) also cannot be used, since the flash algorithm for the KV58 seems to -be broken at the time of writing. - -An external J-Link debug probe connected to the JTAG header J13 is used to debug -the target. - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :tool: all - :board: twr_kv58f220m - :goals: build - -Configuring a Console -===================== - -Even though the OpenSDA probe cannot be used for debugging, we will use it as a -USB-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J22. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: twr_kv58f220m - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! twr_kv58f220m - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: twr_kv58f220m - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! twr_kv58f220m - -.. _TWR-KV58F220M Website: - https://www.nxp.com/TWR-KV58F220M - -.. _TWR-KV58F220M User Guide: - https://www.nxp.com/webapp/Download?colCode=TWRKV58F220MUG - -.. _TWR-KV58F220M Schematics: - https://www.nxp.com/webapp/Download?colCode=TWR-KV58F220M-SCH - -.. _KV5x Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/general-purpose-mcus/kv-series-cortex-m4-m0-plus-m7/kinetis-kv5x-240-mhz-motor-control-and-power-conversion-ethernet-mcus-based-on-arm-cortex-m7:KV5x - -.. _KV5x Datasheet: - https://www.nxp.com/docs/en/data-sheet/KV5XP144M240.pdf - -.. _KV5x Reference Manual: - https://www.nxp.com/webapp/Download?colCode=KV5XP144M240RM diff --git a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig b/boards/arm/ubx_bmd300eval_nrf52832/Kconfig deleted file mode 100644 index 5794811ba64..00000000000 --- a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD300EVAL_NRF52832 diff --git a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.board b/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.board deleted file mode 100644 index cc5c009623b..00000000000 --- a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD300EVAL_NRF52832 - bool "u-blox BMD-300-EVAL" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.defconfig b/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.defconfig deleted file mode 100644 index 29b0576f3e1..00000000000 --- a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD300EVAL_NRF52832 - -config BOARD - default "ubx_bmd300eval_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_UBX_BMD300EVAL_NRF52832 diff --git a/boards/arm/ubx_bmd300eval_nrf52832/doc/index.rst b/boards/arm/ubx_bmd300eval_nrf52832/doc/index.rst deleted file mode 100644 index 4cf272153c0..00000000000 --- a/boards/arm/ubx_bmd300eval_nrf52832/doc/index.rst +++ /dev/null @@ -1,397 +0,0 @@ -.. _ubx_bmd300eval_nrf52832: - -u-blox EVK-BMD-30/35: BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL -################################################################## - -Overview -******** - -The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL hardware provides -support for the u-blox BMD-300, BMD-301, and BMD-350 Bluetooth 5 -modules, based on the Nordic Semiconductor nRF52832 ARM Cortex-M4F -CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/BMD-30-33-35-36-EVAL.jpg - :align: center - :alt: BMD-300-EVAL - - BMD-300-EVAL (Credit: u-blox AG) - -.. note:: - The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL share the same - pin headers and assignments. The boards are different only in - the module used on the board. The BMD-300 and BMD-301 modules - share the same footprint and differ only in the antenna. The - BMD-350 module utilizes the nRF52832 CIAA WLCSP package. - -More information about the BMD-300-EVAL, BMD-301-EVAL, and -BMD-350-EVAL and the respective modules can be found at the -`u-blox website`_. All of the Nordic Semiconductor examples for -the nRF52 DK (nrf52dk_nrf52832) may be used without modification. - -Hardware -******** - -The BMD-300/301/350 module on the board contains an internal -high-frequency oscillator at 32MHz. There is also a low frequency -(slow) oscillator of 32.768kHz. The module itself does not include -the slow crystal; however, the EVAL boards do. - -.. note:: - When targeting a custom design without a slow crystal, - be sure to modify code to utilize the internal RC - oscillator for the slow clock. - -Supported Features -================== - -The BMD-300/301/350-EVAL configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of -BMD-300/301/350-EVAL hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.17 -* LED2 (red) = P0.18 -* LED3 (green) = P0.19 -* LED4 (green) = P0.20 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.13 -* BUTTON2 = SW2 = P0.14 -* BUTTON3 = SW3 = P0.15 -* BUTTON4 = SW4 = P0.16 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-300-eval_pin_out.jpg - :align: center - :alt: BMD-300-EVAL pin-out - - BMD-300-EVAL pin-out (Credit: u-blox AG) - -.. note:: - The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL share - the same pin headers and assignments. - The BMD-300-EVAL is shown here. - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-300/301/350-EVAL - for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 | -+-------+----------------+ -| 2 | P0.09 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.21 / RESET | -+-------+----------------+ -| 8 | P0.01 / XL2 | -+-------+----------------+ -| 9 | P0.00 / XL1 | -+-------+----------------+ -| 10 | GND | -+-------+----------------+ - - -Arduino Headers ---------------- - - -Power (J5) - -+-------+--------------+---------------------------+ -| PIN # | Signal Name | BMD-300/301/350 Functions | -+=======+==============+===========================+ -| 1 | VSHLD | N/A | -+-------+--------------+---------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+---------------------------+ -| 3 | RESET | P0.21 / RESET | -+-------+--------------+---------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+---------------------------+ -| 5 | V5V | N/A | -+-------+--------------+---------------------------+ -| 6 | GND | N/A | -+-------+--------------+---------------------------+ -| 7 | GND | N/A | -+-------+--------------+---------------------------+ -| 8 | N/C | N/A | -+-------+--------------+---------------------------+ - - -Analog in (J8) - -+-------+--------------+---------------------------+ -| PIN # | Signal Name | BMD-300/301/350 Functions | -+=======+==============+===========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+---------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+---------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+---------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+---------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+---------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+---------------------------+ - - -Digital I/O (J7) - -+-------+--------------+---------------------------+ -| PIN # | Signal Name | BMD-300/301/350 Functions | -+=======+==============+===========================+ -| 1 | D7 | P0.18/TRACEDATA[0]/SWO | -+-------+--------------+---------------------------+ -| 2 | D6 | P0.17 | -+-------+--------------+---------------------------+ -| 3 | D5 | P0.16/TRACEDATA[1] | -+-------+--------------+---------------------------+ -| 4 | D4 | P0.15/TRACEDATA[2] | -+-------+--------------+---------------------------+ -| 5 | D3 | P0.14/TRACEDATA[3] | -+-------+--------------+---------------------------+ -| 6 | D2 | P0.13 | -+-------+--------------+---------------------------+ -| 7 | D1 (TX) | P0.12 | -+-------+--------------+---------------------------+ -| 8 | D0 (RX) | P0.11 | -+-------+--------------+---------------------------+ - - -Digital I/O (J6) - -+-------+--------------+---------------------------+ -| PIN # | Signal Name | BMD-300/301/350 Functions | -+=======+==============+===========================+ -| 1 | SCL | P0.27 | -+-------+--------------+---------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+---------------------------+ -| 3 | AREF | P0.02/AIN0 | -+-------+--------------+---------------------------+ -| 4 | GND | N/A | -+-------+--------------+---------------------------+ -| 5 | D13 (SCK) | P0.25 | -+-------+--------------+---------------------------+ -| 6 | D12 (MISO) | P0.24 | -+-------+--------------+---------------------------+ -| 7 | D11 (MOSI) | P0.23 | -+-------+--------------+---------------------------+ -| 8 | D10 (SS) | P0.22 | -+-------+--------------+---------------------------+ -| 9 | D9 | P0.20/TRACECLK | -+-------+--------------+---------------------------+ -| 10 | D8 | P0.19 | -+-------+--------------+---------------------------+ - - -J11 - -+-------+--------------+---------------------------+ -| PIN # | Signal Name | BMD-300/301/350 Functions | -+=======+==============+===========================+ -| 1 | D12 (MISO) | P0.24 | -+-------+--------------+---------------------------+ -| 2 | V5V | N/A | -+-------+--------------+---------------------------+ -| 3 | D13 (SCK) | P0.25 | -+-------+--------------+---------------------------+ -| 4 | D11 (MOSI) | P0.23 | -+-------+--------------+---------------------------+ -| 5 | RESET | N/A | -+-------+--------------+---------------------------+ -| 6 | N/A | N/A | -+-------+--------------+---------------------------+ - - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the -BMD-300/301/350-EVAL can be found. For example, under Linux, -:code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd300eval_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-330-EVAL -************************************************ - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is -running correctly on your board. The button and LED definitions -can be found in :zephyr_file:`boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.dts`. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/en/product/bmd-3035-series-open-cpu diff --git a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig b/boards/arm/ubx_bmd330eval_nrf52810/Kconfig deleted file mode 100644 index cb7241f9b71..00000000000 --- a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# BMD-330-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD330EVAL_NRF52810 - -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT diff --git a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.board b/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.board deleted file mode 100644 index fa39a7e9bff..00000000000 --- a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BMD-330-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD330EVAL_NRF52810 - bool "u-blox BMD-330-EVAL" - depends on SOC_NRF52810_QFAA diff --git a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.defconfig b/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.defconfig deleted file mode 100644 index 7168f408f39..00000000000 --- a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# BMD-330-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD330EVAL_NRF52810 - -config BOARD - default "ubx_bmd330eval_nrf52810" - -endif # BOARD_UBX_BMD330EVAL_NRF52810 diff --git a/boards/arm/ubx_bmd330eval_nrf52810/doc/index.rst b/boards/arm/ubx_bmd330eval_nrf52810/doc/index.rst deleted file mode 100644 index 56ede10d98b..00000000000 --- a/boards/arm/ubx_bmd330eval_nrf52810/doc/index.rst +++ /dev/null @@ -1,388 +0,0 @@ -.. _ubx_bmd330eval_nrf52810: - -u-blox EVK-BMD-330: BMD-330-EVAL -################################ - -Overview -******** - -The BMD-330-EVAL hardware provides support for the -u-blox BMD-330 Bluetooth 5 module, based on The -Nordic Semiconductor nRF52810 ARM Cortex-M4 CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/BMD-30-33-35-36-EVAL.jpg - :align: center - :alt: BMD-300-EVAL - - BMD-300-EVAL (Credit: u-blox AG) - -.. note:: - The BMD-330-EVAL shares the same pin headers and assignments as the - BMD-300-EVAL. The BMD-300-EVAL is shown here. - -More information about the BMD-330-EVAL and the BMD-330 module -can be found at the `u-blox website`_. All of the Nordic -Semiconductor examples for the nRF52 DK (nrf52dk_nrf52810) -may be used without modification. - -Hardware -******** - -The BMD-330 on the BMD-330-EVAL contains an internal -high-frequency oscillator at 32MHz. There is also a low frequency -(slow) oscillator of 32.768kHz. The BMD-330 itself does not include -the slow crystal; however, the BMD-330-EVAL does. - -.. note:: - When targeting a custom design without a slow crystal, - be sure to modify code to utilize the internal RC - oscillator for the slow clock. - -Supported Features -================== - -The BMD-330-EVAL configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of -BMD-330-EVAL hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.17 -* LED2 (red) = P0.18 -* LED3 (green) = P0.19 -* LED4 (green) = P0.20 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.13 -* BUTTON2 = SW2 = P0.14 -* BUTTON3 = SW3 = P0.15 -* BUTTON4 = SW4 = P0.16 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-300-eval_pin_out.jpg - :align: center - :alt: BMD-300-EVAL pin-out - - BMD-300-EVAL pin-out (Credit: u-blox AG) - -.. note:: - The BMD-330-EVAL shares the same pin headers and assignments - as the BMD-300-EVAL. The BMD-300-EVAL is shown here. - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-330-EVAL - for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 | -+-------+----------------+ -| 2 | P0.09 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.21 / RESET | -+-------+----------------+ -| 8 | P0.01 / XL2 | -+-------+----------------+ -| 9 | P0.00 / XL1 | -+-------+----------------+ -| 10 | GND | -+-------+----------------+ - - -Arduino Headers ---------------- - - -Power (J5) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-330 Functions | -+=======+==============+=========================+ -| 1 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.21 / RESET | -+-------+--------------+-------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ - -Analog in (J8) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-330 Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -Digital I/O (J7) - -+-------+--------------+----------------------------+ -| PIN # | Signal Name | BMD-330 Functions | -+=======+==============+============================+ -| 1 | D7 | P0.18 | -+-------+--------------+----------------------------+ -| 2 | D6 | P0.17 | -+-------+--------------+----------------------------+ -| 3 | D5 | P0.16 | -+-------+--------------+----------------------------+ -| 4 | D4 | P0.15 | -+-------+--------------+----------------------------+ -| 5 | D3 | P0.14 | -+-------+--------------+----------------------------+ -| 6 | D2 | P0.13 | -+-------+--------------+----------------------------+ -| 7 | D1 (TX) | P0.12 | -+-------+--------------+----------------------------+ -| 8 | D0 (RX) | P0.11 | -+-------+--------------+----------------------------+ - -Digital I/O (J6) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-330 Functions | -+=======+==============+=========================+ -| 1 | SCL | P0.27 | -+-------+--------------+-------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 3 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 4 | GND | N/A | -+-------+--------------+-------------------------+ -| 5 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 6 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 7 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 8 | D10 (SS) | P0.22 | -+-------+--------------+-------------------------+ -| 9 | D9 | P0.20 | -+-------+--------------+-------------------------+ -| 10 | D8 | P0.19 | -+-------+--------------+-------------------------+ - -J11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-330 Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the -BMD-330-EVAL can be found. For example, under Linux, -:code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd330eval_nrf52810 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-330-EVAL -************************************************ - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is -running correctly on your board. The button and LED definitions -can be found in :zephyr_file:`boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.dts`. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/en/product/bmd-330-open-cpu diff --git a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.yaml b/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.yaml deleted file mode 100644 index 3554db7451f..00000000000 --- a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: ubx_bmd330eval_nrf52810 -name: UBX_BMD330EVAL_NRF52810 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 24 -flash: 192 -supported: - - adc - - arduino_gpio - - arduino_i2c - - arduino_spi - - gpio - - counter - - nvs - - i2c - - pwm - - spi - - watchdog -vendor: u-blox diff --git a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig b/boards/arm/ubx_bmd340eval_nrf52840/Kconfig deleted file mode 100644 index 10df4b0cc46..00000000000 --- a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BMD-340-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD340EVAL_NRF52840 diff --git a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.board b/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.board deleted file mode 100644 index 538bd40ed3d..00000000000 --- a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BMD-340-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD340EVAL_NRF52840 - bool "u-blox BMD-340-EVAL" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.defconfig b/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.defconfig deleted file mode 100644 index f3113a62b3a..00000000000 --- a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# BMD-340-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD340EVAL_NRF52840 - -config BOARD - default "ubx_bmd340eval_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_UBX_BMD340EVAL_NRF52840 diff --git a/boards/arm/ubx_bmd340eval_nrf52840/doc/index.rst b/boards/arm/ubx_bmd340eval_nrf52840/doc/index.rst deleted file mode 100644 index 513f7dbdc8a..00000000000 --- a/boards/arm/ubx_bmd340eval_nrf52840/doc/index.rst +++ /dev/null @@ -1,521 +0,0 @@ -.. _ubx_bmd340eval_nrf52840: - -u-blox EVK-BMD-34/38: BMD-340-EVAL and BMD-341-EVAL -################################################### - -Overview -******** - -The BMD-340-EVAL and BMD-341-EVAL hardware provides support for the -u-blox BMD-340 and BMD-341 Bluetooth 5.0 modules, based on the -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU. the BMD-340 and -BMD-341 are identical in operation except for the antenna. The -BMD-340 has a PCB antenna while the BMD-341 has a U.FL connector. -Both support the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/BMD-34-38-EVAL.jpg - :align: center - :alt: BMD-340-EVAL - - BMD-340-EVAL (Credit: u-blox AG) - -More information about the BMD-340-EVAL, BMD-340 module, BMD-341-EVAL, -and BMD-341 module can be found at the `u-blox website`_. -All of the Nordic Semiconductor examples for the nRF52840 DK -(nrf52840dk_nrf52840) may be used without modification. - -..note:: - The BMD-340 and BMD-341 are identical except for the antenna. - Throughout this board support package, the filenames utilize - the ubx_bmd340eval_nrf52840. - -Hardware -******** - -The BMD-340 on the BMD-340-EVAL (or BMD-341 on the BMD-341-EVAL) -contains an internal high-frequency oscillator at 32MHz. -There is also a low frequency (slow) oscillator of 32.768kHz. -The BMD-340 and BMD-341 do not include the slow crystal; -however, the BMD-340-EVAL and BMD-341-EVAL do. - -.. note:: - - When targeting a custom design without a slow crystal, be sure - to modify code to utilize the internal RC oscillator for the - slow clock. - -Supported Features -================== - -The BMD-340-EVAL and BMD-341-EVAL board configuration supports -the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | IEEE 802.15.4 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of BMD-340-EVAL -and BMD-341-EVAL hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.13 -* LED2 (red) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-340-eval_pin_out.jpg - :align: center - :alt: BMD-340-EVAL pin-out - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-340-EVAL or - BMD-341-EVAL for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - -Debug IN (J26) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | BMD-340_VCC | -+-------+----------------+ -| 2 | BMD-340_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | BMD-340_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | BMD-340_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | GND | -+-------+----------------+ -| 10 | BMD-340_RESET | -+-------+----------------+ - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 / NFC2 | -+-------+----------------+ -| 2 | P0.09 / NFC1 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.01 / XL2 | -+-------+----------------+ -| 8 | P0.00 / XL1 | -+-------+----------------+ - -Auxiliary (J10) - -+-------+-------------------+ -| PIN # | Signal Name | -+=======+===================+ -| 1 | P0.11 / TRACED[2] | -+-------+-------------------+ -| 2 | P0.12 / TRACED[1] | -+-------+-------------------+ -| 3 | P0.13 | -+-------+-------------------+ -| 4 | P0.14 | -+-------+-------------------+ -| 5 | P0.15 | -+-------+-------------------+ -| 6 | P0.16 | -+-------+-------------------+ -| 7 | P0.17 / QSPI_CS | -+-------+-------------------+ -| 8 | P0.18 / RESET | -+-------+-------------------+ -| 9 | P0.19 / QSPI_CLK | -+-------+-------------------+ -| 10 | P0.20 / QSPI_D0 | -+-------+-------------------+ -| 11 | P0.21 / QSPI_D1 | -+-------+-------------------+ -| 12 | P0.22 / QSPI_D2 | -+-------+-------------------+ -| 13 | P0.23 / QSPI_D3 | -+-------+-------------------+ -| 14 | P0.24 | -+-------+-------------------+ -| 15 | P0.25 | -+-------+-------------------+ -| 16 | P1.00 / TRACED[0] | -+-------+-------------------+ -| 17 | P1.09 / TRACED[3] | -+-------+-------------------+ -| 18 | No connection | -+-------+-------------------+ - -Arduino Headers ---------------- - -Power (J5) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-34x Functions | -+=======+==============+=========================+ -| 1 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.18 / RESET | -+-------+--------------+-------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ - -Analog in (J8) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-34x Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -Digital I/O (J7) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-34x Functions | -+=======+==============+=========================+ -| 1 | D7 | P1.08 | -+-------+--------------+-------------------------+ -| 2 | D6 | P1.07 | -+-------+--------------+-------------------------+ -| 3 | D5 | P1.06 | -+-------+--------------+-------------------------+ -| 4 | D4 | P1.05 | -+-------+--------------+-------------------------+ -| 5 | D3 | P1.04 | -+-------+--------------+-------------------------+ -| 6 | D2 | P1.03 | -+-------+--------------+-------------------------+ -| 7 | D1 (TX) | P1.02 | -+-------+--------------+-------------------------+ -| 8 | D0 (RX) | P1.01 | -+-------+--------------+-------------------------+ - -Digital I/O (J6) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-34x Functions | -+=======+==============+=========================+ -| 1 | SCL | P0.27 | -+-------+--------------+-------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 3 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 4 | GND | N/A | -+-------+--------------+-------------------------+ -| 5 | D13 (SCK) | P1.15 | -+-------+--------------+-------------------------+ -| 6 | D12 (MISO) | P1.14 | -+-------+--------------+-------------------------+ -| 7 | D11 (MOSI) | P1.13 | -+-------+--------------+-------------------------+ -| 8 | D10 (SS) | P1.12 | -+-------+--------------+-------------------------+ -| 9 | D9 | P1.11 | -+-------+--------------+-------------------------+ -| 10 | D8 | P1.10 | -+-------+--------------+-------------------------+ - -J11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-34x Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.14 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.15 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.13 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Applications for the BMD-340-EVAL and BMD-341-EVAL board -configurations can be built and flashed in the usual way -(see :ref:`build_an_application` and :ref:`application_run` -for more details); however, the standard debugging targets -are not currently available. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the BMD-340-EVAL -or BMD-341-EVAL can be found. For example, under Linux, -:code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd340eval_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-340-EVAL and BMD-341-EVAL -***************************************************************** - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found -in -:zephyr_file:`boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts`. - -Using UART1 -*********** - -The following approach can be used when an application needs to use -more than one UART for connecting peripheral devices: - -1. Add device tree overlay file to the main directory of your - application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default: uart1_default { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep: uart1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is - used for TX - -2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` - -Overlay file naming -=================== - -The file has to be named ``.overlay`` and placed in the app -main directory to be picked up automatically by the device tree -compiler. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the data sheet for the BMD-340 at the `u-blox website`_, Section 2 -'Pin definition'. In the table 3 select the pins marked 'GPIO'. -Note that pins marked as 'Standard drive, low frequency I/O only -(<10 kH' can only be used in under-10KHz applications. -They are not suitable for 115200 speed of UART. - -.. note: - Pins are defined according to the "nRF52" pin number, not the module - pad number. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/docs/UBX-19033353 diff --git a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig b/boards/arm/ubx_bmd345eval_nrf52840/Kconfig deleted file mode 100644 index 5888e99eac4..00000000000 --- a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# BMD-345-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# Copyright (c) 2021 Linumiz -# SPDX-License-Identifier: Apache-2.0 - -# No special configuration is required. -# The BMD-345 does not include DCDC components diff --git a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.board b/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.board deleted file mode 100644 index 9f6b6acc0eb..00000000000 --- a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# BMD-340-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# Copyright (c) 2021 Linumiz -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD345EVAL_NRF52840 - bool "u-blox BMD-345-EVAL" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.defconfig b/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.defconfig deleted file mode 100644 index e66bae50d86..00000000000 --- a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# BMD-345-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# Copyright (c) 2021 Linumiz -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD345EVAL_NRF52840 - -config BOARD - default "ubx_bmd345eval_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_UBX_BMD345EVAL_NRF52840 diff --git a/boards/arm/ubx_bmd345eval_nrf52840/doc/index.rst b/boards/arm/ubx_bmd345eval_nrf52840/doc/index.rst deleted file mode 100644 index 7404ebd9053..00000000000 --- a/boards/arm/ubx_bmd345eval_nrf52840/doc/index.rst +++ /dev/null @@ -1,533 +0,0 @@ -.. _ubx_bmd345eval_nrf52840: - -u-blox EVK-BMD-34/38: BMD-345-EVAL -################################## - -Overview -******** - -The BMD-345-EVALhardware provides support for the u-blox BMD-345 -Bluetooth 5.0 modules, based on the Nordic Semiconductor nRF52840 -ARM Cortex-M4F CPU and Skyworks RFX2411 Front End Module (FEM), -also known as a Power Amplifier / Low Noise Amplifier (PA/LNA). -Both support the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/bmd-345-eval_features.jpg - :align: center - :alt: BMD 345 EVAL - - BMD-345-EVAL (Credit: ublox AG) - -More information about the BMD-345-EVAL and BMD-345 module can be -found at the `u-blox website`_. - - -Hardware -******** - -The BMD-345 on the BMD-345-EVAL contains an internal high-frequency -oscillator at 32MHz. There is also a low frequency (slow) -oscillator of 32.768kHz. The BMD-345 does not include the slow -crystal; however, the BMD-345-EVAL does. - -.. note:: - - When targeting a custom design without a slow crystal, be sure - to modify code to utilize the internal RC oscillator for the - slow clock. - -Front End Module -================ - -BMD-345 utilizes the Skyworks RFX2411 front end module (FEM). -The FEM provides higher output power and better sensitivity. - -FEM pin assignments -------------------- - -+-------------+--------------+----------+--------+----------+---------+ -| GPIO Number | Signal Name | Shutdown | Bypass | Transmit | Receive | -+=============+==============+==========+========+==========+=========+ -| P1.05 | TX_EN | Low | Low | High | Low | -+-------------+--------------+----------+--------+----------+---------+ -| P1.06 | RX_EN | Low | Low | Low | High | -+-------------+--------------+----------+--------+----------+---------+ -| P1.04 | MODE | Low | High | Low | Low | -+-------------+--------------+----------+--------+----------+---------+ -| P1.02 | A_SEL | Low | Low | Low | Low | -+-------------+--------------+----------+--------+----------+---------+ - -Supported Features -================== - -The BMD-345-EVAL board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | IEEE 802.15.4 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of BMD-345-EVAL -hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.13 -* LED2 (red) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-345-eval_pin_out.jpg - :align: center - :alt: BMD-345-EVAL pin-out - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-340-EVAL or - BMD-341-EVAL for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - -Debug IN (J26) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | BMD-340_VCC | -+-------+----------------+ -| 2 | BMD-340_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | BMD-340_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | BMD-340_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | GND | -+-------+----------------+ -| 10 | BMD-340_RESET | -+-------+----------------+ - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 / NFC2 | -+-------+----------------+ -| 2 | P0.09 / NFC1 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.01 / XL2 | -+-------+----------------+ -| 8 | P0.00 / XL1 | -+-------+----------------+ - -Auxiliary (J10) - -+-------+-------------------+ -| PIN # | Signal Name | -+=======+===================+ -| 1 | P0.11 / TRACED[2] | -+-------+-------------------+ -| 2 | P0.12 / TRACED[1] | -+-------+-------------------+ -| 3 | P0.13 | -+-------+-------------------+ -| 4 | P0.14 | -+-------+-------------------+ -| 5 | P0.15 | -+-------+-------------------+ -| 6 | P0.16 | -+-------+-------------------+ -| 7 | P0.17 / QSPI_CS | -+-------+-------------------+ -| 8 | P0.18 / RESET | -+-------+-------------------+ -| 9 | P0.19 / QSPI_CLK | -+-------+-------------------+ -| 10 | P0.20 / QSPI_D0 | -+-------+-------------------+ -| 11 | P0.21 / QSPI_D1 | -+-------+-------------------+ -| 12 | P0.22 / QSPI_D2 | -+-------+-------------------+ -| 13 | P0.23 / QSPI_D3 | -+-------+-------------------+ -| 14 | P0.24 | -+-------+-------------------+ -| 15 | P0.25 | -+-------+-------------------+ -| 16 | P1.00 / TRACED[0] | -+-------+-------------------+ -| 17 | P1.09 / TRACED[3] | -+-------+-------------------+ -| 18 | No connection | -+-------+-------------------+ - -Arduino Headers ---------------- - -Power (J5) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-345 Functions | -+=======+==============+=========================+ -| 1 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.18 / RESET | -+-------+--------------+-------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ - -Analog in (J8) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-345 Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -Digital I/O (J7) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-345 Functions | -+=======+==============+=========================+ -| 1 | D7 | P1.08 | -+-------+--------------+-------------------------+ -| 2 | D6 | P1.07 | -+-------+--------------+-------------------------+ -| 3 | N/C | N/A | -+-------+--------------+-------------------------+ -| 4 | N/C | N/A | -+-------+--------------+-------------------------+ -| 5 | N/C | N/A | -+-------+--------------+-------------------------+ -| 6 | D2 | P1.03 | -+-------+--------------+-------------------------+ -| 7 | N/C | N/A | -+-------+--------------+-------------------------+ -| 8 | D0 (RX) | P1.01 | -+-------+--------------+-------------------------+ - -Digital I/O (J6) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-345 Functions | -+=======+==============+=========================+ -| 1 | SCL | P0.27 | -+-------+--------------+-------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 3 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 4 | GND | N/A | -+-------+--------------+-------------------------+ -| 5 | D13 (SCK) | P1.15 | -+-------+--------------+-------------------------+ -| 6 | D12 (MISO) | P1.14 | -+-------+--------------+-------------------------+ -| 7 | D11 (MOSI) | P1.13 | -+-------+--------------+-------------------------+ -| 8 | D10 (SS) | P1.12 | -+-------+--------------+-------------------------+ -| 9 | D9 | P1.11 | -+-------+--------------+-------------------------+ -| 10 | D8 | P1.10 | -+-------+--------------+-------------------------+ - -J11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-345 Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.14 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.15 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.13 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Applications for the BMD-345-EVAL board -configurations can be built and flashed in the usual way -(see :ref:`build_an_application` and :ref:`application_run` -for more details); however, the standard debugging targets -are not currently available. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the BMD-345-EVAL -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd345eval_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-345-EVAL -***************************************************************** - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found -in -:zephyr_file:`boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd345eval_nrf52840.dts`. - -Using UART1 -*********** - -The following approach can be used when an application needs to use -more than one UART for connecting peripheral devices: - -1. Add device tree overlay file to the main directory of your - application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default: uart1_default { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep: uart1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is - used for TX - -2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` - -Overlay file naming -=================== - -The file has to be named ``.overlay`` and placed in the app -main directory to be picked up automatically by the device tree -compiler. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the data sheet for the BMD-345 at the `u-blox website`_, Section 2 -'Pin definition'. In the table 3 select the pins marked 'GPIO'. -Note that pins marked as 'Standard drive, low frequency I/O only -(<10 kH' can only be used in under-10KHz applications. -They are not suitable for 115200 speed of UART. - -.. note: - Pins are defined according to the "nRF52" pin number, not the module - pad number. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/en/product/bmd-34-series-open-cpu diff --git a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig b/boards/arm/ubx_bmd360eval_nrf52811/Kconfig deleted file mode 100644 index 53882dd3930..00000000000 --- a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -# BMD-360-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD360EVAL_NRF52811 -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT diff --git a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.board b/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.board deleted file mode 100644 index b041fc6a2c7..00000000000 --- a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BMD-360-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD360EVAL_NRF52811 - bool "u-blox BMD-360-EVAL" - depends on SOC_NRF52811_QFAA diff --git a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.defconfig b/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.defconfig deleted file mode 100644 index a604bf98cd4..00000000000 --- a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# BMD-360-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD360EVAL_NRF52811 - -config BOARD - default "ubx_bmd360eval_nrf52811" - -endif # BOARD_UBX_BMD360EVAL_NRF52811 diff --git a/boards/arm/ubx_bmd360eval_nrf52811/doc/index.rst b/boards/arm/ubx_bmd360eval_nrf52811/doc/index.rst deleted file mode 100644 index c81d8b4ab7e..00000000000 --- a/boards/arm/ubx_bmd360eval_nrf52811/doc/index.rst +++ /dev/null @@ -1,386 +0,0 @@ -.. _ubx_bmd360eval_nrf52811: - -u-blox EVK-BMD-360: BMD-360-EVAL -################################ - -Overview -******** - -The BMD-360-EVAL hardware provides support for the -u-blox BMD-360 Bluetooth 5 module, based on The -Nordic Semiconductor nRF52811 ARM Cortex-M4 CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/BMD-30-33-35-36-EVAL.jpg - :align: center - :alt: BMD-300-EVAL - - BMD-300-EVAL (Credit: u-blox AG) - -.. note:: - The BMD-360-EVAL shares the same pin headers and assignments as the - BMD-300-EVAL. The BMD-300-EVAL is shown here. - -More information about the BMD-360-EVAL and the BMD-360 module -can be found at the `u-blox website`_. - -Hardware -******** - -The BMD-360 on the BMD-360-EVAL contains an internal -high-frequency oscillator at 32MHz. There is also a low frequency -(slow) oscillator of 32.768kHz. The BMD-360 itself does not include -the slow crystal; however, the BMD-360-EVAL does. - -.. note:: - When targeting a custom design without a slow crystal, - be sure to modify code to utilize the internal RC - oscillator for the slow clock. - -Supported Features -================== - -The BMD-360-EVAL configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of -BMD-360-EVAL hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.17 -* LED2 (red) = P0.18 -* LED3 (green) = P0.19 -* LED4 (green) = P0.20 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.13 -* BUTTON2 = SW2 = P0.14 -* BUTTON3 = SW3 = P0.15 -* BUTTON4 = SW4 = P0.16 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-300-eval_pin_out.jpg - :align: center - :alt: BMD-300-EVAL pin-out - - BMD-300-EVAL pin-out (Credit: u-blox AG) - -.. note:: - The BMD-360-EVAL shares the same pin headers and assignments - as the BMD-300-EVAL. The BMD-300-EVAL is shown here. - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-360-EVAL - for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 | -+-------+----------------+ -| 2 | P0.09 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.21 / RESET | -+-------+----------------+ -| 8 | P0.01 / XL2 | -+-------+----------------+ -| 9 | P0.00 / XL1 | -+-------+----------------+ -| 10 | GND | -+-------+----------------+ - - -Arduino Headers ---------------- - - -Power (J5) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-360 Functions | -+=======+==============+=========================+ -| 1 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.21 / RESET | -+-------+--------------+-------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ - -Analog in (J8) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-360 Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -Digital I/O (J7) - -+-------+--------------+----------------------------+ -| PIN # | Signal Name | BMD-360 Functions | -+=======+==============+============================+ -| 1 | D7 | P0.18 | -+-------+--------------+----------------------------+ -| 2 | D6 | P0.17 | -+-------+--------------+----------------------------+ -| 3 | D5 | P0.16 | -+-------+--------------+----------------------------+ -| 4 | D4 | P0.15 | -+-------+--------------+----------------------------+ -| 5 | D3 | P0.14 | -+-------+--------------+----------------------------+ -| 6 | D2 | P0.13 | -+-------+--------------+----------------------------+ -| 7 | D1 (TX) | P0.12 | -+-------+--------------+----------------------------+ -| 8 | D0 (RX) | P0.11 | -+-------+--------------+----------------------------+ - -Digital I/O (J6) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-360 Functions | -+=======+==============+=========================+ -| 1 | SCL | P0.27 | -+-------+--------------+-------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 3 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 4 | GND | N/A | -+-------+--------------+-------------------------+ -| 5 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 6 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 7 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 8 | D10 (SS) | P0.22 | -+-------+--------------+-------------------------+ -| 9 | D9 | P0.20 | -+-------+--------------+-------------------------+ -| 10 | D8 | P0.19 | -+-------+--------------+-------------------------+ - -J11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-360 Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the -BMD-360-EVAL can be found. For example, under Linux, -:code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd360eval_nrf52811 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-360-EVAL -************************************************ - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is -running correctly on your board. The button and LED definitions -can be found in :zephyr_file:`boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.dts`. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/en/product/bmd-360-open-cpu diff --git a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig b/boards/arm/ubx_bmd380eval_nrf52840/Kconfig deleted file mode 100644 index 2620c816acb..00000000000 --- a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BMD-380-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC -bool "DCDC mode" -select SOC_DCDC_NRF52X -default y -depends on BOARD_UBX_BMD380EVAL_NRF52840 diff --git a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.board b/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.board deleted file mode 100644 index e930b4d4ac4..00000000000 --- a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.board +++ /dev/null @@ -1,11 +0,0 @@ -# BMD-380-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD380EVAL_NRF52840 - bool "u-blox BMD-380-EVAL" - depends on SOC_NRF52840_QIAA - -# should be CKAA, -# but SOC file not yet available from Nordic Semiconductor diff --git a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.defconfig b/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.defconfig deleted file mode 100644 index b77590a1fdd..00000000000 --- a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# BMD-380-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD380EVAL_NRF52840 - -config BOARD - default "ubx_bmd380eval_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_UBX_BMD380EVAL_NRF52840 diff --git a/boards/arm/ubx_bmd380eval_nrf52840/doc/index.rst b/boards/arm/ubx_bmd380eval_nrf52840/doc/index.rst deleted file mode 100644 index e76334dd96a..00000000000 --- a/boards/arm/ubx_bmd380eval_nrf52840/doc/index.rst +++ /dev/null @@ -1,519 +0,0 @@ -.. _ubx_bmd380eval_nrf52840: - -u-blox EVK-BMD-34/48: BMD-380-EVAL -################################## - -Overview -******** - -The BMD-380-EVAL hardware provides support for the -u-blox BMD-380 Bluetooth 5.0 module, based on The -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/BMD-34-38-EVAL.jpg - :align: center - :alt: BMD-340-EVAL - - BMD-340-EVAL (Credit: u-blox AG) - -.. note:: - The BMD-380-EVAL shares the same pin headers and assignments as the - BMD-340-EVAL with four exceptions. The BMD-340-EVAL is shown here. - See the pin tables below for the exceptions. - -More information about the BMD-340-EVAL and the BMD-340 module -can be found at the `u-blox website`_. All of the Nordic Semiconductor -examples for the nRF52840 DK (nrf52840dk_nrf52840) may be used without -modification. - -Hardware -******** - -The BMD-380 on the BMD-380-EVAL contains an internal high-frequency -oscillator at 32MHz. There is also a low frequency (slow) oscillator -of 32.768kHz. The BMD-380 itself does not include the slow crystal; -however, the BMD-380-eval does. - -.. note:: - - When targeting a custom design without a slow crystal, be sure - to modify code to utilize the internal RC oscillator for the - slow clock. - -Supported Features -================== - -The BMD-380-EVAL board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | IEEE 802.15.4 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of BMD-380-EVAL -hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.13 -* LED2 (red) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-340-eval_pin_out.jpg - :align: center - :alt: BMD-340-EVAL pin-out - -.. note:: - The BMD-380-EVAL shares the same pin headers and assignments as the - BMD-340-EVAL with four exceptions. The BMD-340-EVAL is shown here. - See the pin tables below for the exceptions. - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-380-EVAL - for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - -Debug IN (J26) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | BMD-340_VCC | -+-------+----------------+ -| 2 | BMD-340_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | BMD-340_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | BMD-340_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | GND | -+-------+----------------+ -| 10 | BMD-340_RESET | -+-------+----------------+ - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 / NFC2 | -+-------+----------------+ -| 2 | P0.09 / NFC1 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.01 / XL2 | -+-------+----------------+ -| 8 | P0.00 / XL1 | -+-------+----------------+ - -Auxiliary (J10) - -+-------+-------------------+ -| PIN # | Signal Name | -+=======+===================+ -| 1 | P0.11 / TRACED[2] | -+-------+-------------------+ -| 2 | P0.12 / TRACED[1] | -+-------+-------------------+ -| 3 | P0.13 | -+-------+-------------------+ -| 4 | P0.14 | -+-------+-------------------+ -| 5 | P0.15 | -+-------+-------------------+ -| 6 | P0.16 | -+-------+-------------------+ -| 7 | P0.17 / QSPI_CS | -+-------+-------------------+ -| 8 | P0.18 / RESET | -+-------+-------------------+ -| 9 | P0.19 / QSPI_CLK | -+-------+-------------------+ -| 10 | P0.20 / QSPI_D0 | -+-------+-------------------+ -| 11 | P0.21 / QSPI_D1 | -+-------+-------------------+ -| 12 | P0.22 / QSPI_D2 | -+-------+-------------------+ -| 13 | P0.23 / QSPI_D3 | -+-------+-------------------+ -| 14 | P0.24 | -+-------+-------------------+ -| 15 | P0.25 | -+-------+-------------------+ -| 16 | P1.00 / TRACED[0] | -+-------+-------------------+ -| 17 | P1.09 / TRACED[3] | -+-------+-------------------+ -| 18 | No connection | -+-------+-------------------+ - -Power (J5) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-380 Functions | -+=======+==============+=========================+ -| 1 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.18 / RESET | -+-------+--------------+-------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ - -Analog in (J8) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-380 Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -Digital I/O (J7) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-380 Functions | -+=======+==============+=========================+ -| 1 | D7 | P1.08 | -+-------+--------------+-------------------------+ -| 2 | - | No connection | -+-------+--------------+-------------------------+ -| 3 | D5 | P1.06 | -+-------+--------------+-------------------------+ -| 4 | D4 | No connection | -+-------+--------------+-------------------------+ -| 5 | - | No connection | -+-------+--------------+-------------------------+ -| 6 | - | No connection | -+-------+--------------+-------------------------+ -| 7 | D1 (TX) | P1.02 | -+-------+--------------+-------------------------+ -| 8 | - | No connection | -+-------+--------------+-------------------------+ - -Digital I/O (J6) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-380 Functions | -+=======+==============+=========================+ -| 1 | SCL | P0.27 | -+-------+--------------+-------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 3 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 4 | GND | N/A | -+-------+--------------+-------------------------+ -| 5 | D13 (SCK) | P1.15 | -+-------+--------------+-------------------------+ -| 6 | D12 (MISO) | P1.14 | -+-------+--------------+-------------------------+ -| 7 | D11 (MOSI) | P1.13 | -+-------+--------------+-------------------------+ -| 8 | D10 (SS) | P1.12 | -+-------+--------------+-------------------------+ -| 9 | D9 | P1.11 | -+-------+--------------+-------------------------+ -| 10 | D8 | P1.10 | -+-------+--------------+-------------------------+ - -J11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-380 Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.14 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.15 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.13 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Applications for the BMD-380-EVAL board configurations can -be built and flashed in the usual way -(see :ref:`build_an_application` and :ref:`application_run` -for more details); however, the standard debugging targets -are not currently available. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the BMD-380-EVAL -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd380eval_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-380-EVAL -************************************************ - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found -in -:zephyr_file:`boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts`. - -Using UART1 -*********** - -The following approach can be used when an application needs to use -more than one UART for connecting peripheral devices: - -1. Add device tree overlay file to the main directory of your - application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default: uart1_default { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep: uart1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is - used for TX - -2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` - -Overlay file naming -=================== - -The file has to be named ``.overlay`` and placed in the app -main directory to be picked up automatically by the device tree -compiler. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the data sheet for the BMD-380 at the `u-blox website`_, Section 2 -'Pin definition'. In the table 3 select the pins marked 'GPIO'. -Note that pins marked as 'Standard drive, low frequency I/O only -(<10 kH' can only be used in under-10KHz applications. -They are not suitable for 115200 speed of UART. - -.. note: - Pins are defined according to the "nRF52" pin number, not the module - pad number. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/docs/UBX-19039467 diff --git a/boards/arm/ubx_evkannab1_nrf52832/Kconfig b/boards/arm/ubx_evkannab1_nrf52832/Kconfig deleted file mode 100644 index 3effcbce4e4..00000000000 --- a/boards/arm/ubx_evkannab1_nrf52832/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# u-blox EVK-ANNA-B1 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKANNAB1_NRF52832 diff --git a/boards/arm/ubx_evkannab1_nrf52832/Kconfig.board b/boards/arm/ubx_evkannab1_nrf52832/Kconfig.board deleted file mode 100644 index 81a8fb291ba..00000000000 --- a/boards/arm/ubx_evkannab1_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# u-blox EVK-ANNA-B1 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_EVKANNAB1_NRF52832 - bool "u-blox EVK-ANNA-B1" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_evkannab1_nrf52832/Kconfig.defconfig b/boards/arm/ubx_evkannab1_nrf52832/Kconfig.defconfig deleted file mode 100644 index eaac8eb95d9..00000000000 --- a/boards/arm/ubx_evkannab1_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# u-blox EVK-ANNA-B1 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_EVKANNAB1_NRF52832 - -config BOARD - default "ubx_evkannab1_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_UBX_EVKANNAB1_NRF52832 diff --git a/boards/arm/ubx_evkannab1_nrf52832/doc/index.rst b/boards/arm/ubx_evkannab1_nrf52832/doc/index.rst deleted file mode 100644 index 8a4702f331c..00000000000 --- a/boards/arm/ubx_evkannab1_nrf52832/doc/index.rst +++ /dev/null @@ -1,169 +0,0 @@ -.. _ubx_evkannab1_nrf52832: - -u-blox EVK-ANNA-B11x -#################### - -Overview -******** - -The u-blox ANNA-B1 Evaluation Kit hardware is a Bluetooth low energy -module based on the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU -and has support for the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/EVK-ANNA-B112.jpg - - EVK ANNA-B1 - -More information about the ANNA-B1 module and the EVK-ANNA-B1 -can be found at `ANNA-B1 product page`_ and -`EVK-ANNA-B1 product page`_. - -Supported Features -================== - -The ubx_evkannab1_nrf52832 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth Low Energy | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `EVK-ANNA-B1 product page`_ and `ANNA-B1 Data Sheet`_ -for a complete list of EVK ANNA-B1 hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.27 -* LED1 (green) = P0.25 -* LED2 (blue) = P0.26 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.25 -* BUTTON2 = SW2 = P0.24 - -General information on module pin numbering -------------------------------------------- - -The numbering of the pins on the module and EVK do not follow the GPIO -numbering on the nRF52832 SoC. Please see the `ANNA-B1 Data Sheet`_ for -information on how to map ANNA-B1 pins to the pin numbering on the -nRF52832 SoC. - -The reason for this is the u-blox module family concept where different -modules share the same pinout and can be interchanged. - -Programming and Debugging -************************* - -Applications for the ``ubx_evkannab1_nrf52832`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); however, the standard -debugging targets are not currently available. - -Flashing -======== - -Build and flash applications as usual (see -:ref:`build_an_application` and :ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -Open a terminal program to the USB Serial Port installed when connecting -the board and listen for output. - -Settings: 115200, 8N1, no flow control. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_evkannab1_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging boards -containing a Nordic Semiconductor chip with a Segger IC. - - -Testing the LEDs and buttons in the EVK NINA-B11x -************************************************* - -There are 2 samples that allow you to test that the buttons (switches) -and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.dts`. - -Note that the buttons on the EVK-ANNA-B1 are marked SW1 and SW2, which -are named sw0 and sw1 in the dts file. -Also note that the SW1 button and the green LED are connected on HW level. - - -References -********** - -.. target-notes:: - -.. _ANNA-B1 product page: https://www.u-blox.com/en/product/anna-b112-open-cpu -.. _EVK-ANNA-B1 product page: https://www.u-blox.com/en/product/evk-anna-b112 -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _ANNA-B1 Data Sheet: https://www.u-blox.com/en/docs/UBX-18011707 diff --git a/boards/arm/ubx_evkninab1_nrf52832/Kconfig b/boards/arm/ubx_evkninab1_nrf52832/Kconfig deleted file mode 100644 index a55e5f96934..00000000000 --- a/boards/arm/ubx_evkninab1_nrf52832/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# u-blox EVK NINA-B1 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKNINAB1_NRF52832 diff --git a/boards/arm/ubx_evkninab1_nrf52832/Kconfig.board b/boards/arm/ubx_evkninab1_nrf52832/Kconfig.board deleted file mode 100644 index e97367f358c..00000000000 --- a/boards/arm/ubx_evkninab1_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# u-blox EVK-NINA-B1 board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_EVKNINAB1_NRF52832 - bool "u-blox EVK-NINA-B1" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_evkninab1_nrf52832/Kconfig.defconfig b/boards/arm/ubx_evkninab1_nrf52832/Kconfig.defconfig deleted file mode 100644 index 408147057d1..00000000000 --- a/boards/arm/ubx_evkninab1_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# u-blox EVK-NINA-B1 board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_EVKNINAB1_NRF52832 - -config BOARD - default "ubx_evkninab1_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_UBX_EVKNINAB1_NRF52832 diff --git a/boards/arm/ubx_evkninab1_nrf52832/doc/index.rst b/boards/arm/ubx_evkninab1_nrf52832/doc/index.rst deleted file mode 100644 index 666fdce7e5c..00000000000 --- a/boards/arm/ubx_evkninab1_nrf52832/doc/index.rst +++ /dev/null @@ -1,178 +0,0 @@ -.. _ubx_evkninab1_nrf52832: - -u-blox EVK NINA-B11x -#################### - -Overview -******** - -The u-blox NINA-B1 Evaluation Kit hardware is a Bluetooth -low energy module based on the Nordic Semiconductor nRF52832 -ARM Cortex-M4F CPU and has support for the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/EVK-NINA-B1.jpg - - EVK NINA-B1 - -More information about the NINA-B1 module and the EVK NINA-B1 -can be found at `NINA-B1 product page`_ and -`EVK-NINA-B1 product page`_. - -Supported Features -================== - -The ubx_evkninab1_nrf52832 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth Low Energy | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -.. note:: - Most Arduino interfaces are supported. Arduino pins - D5 and D8 are not available, so arduino_gpio is - disabled. On the EVK-NINA-B1, these pins are - assigned to SWDIO and SWDCLK, respectively. - -Other hardware features have not been enabled yet for this board. -See `EVK-NINA-B1 product page`_ and `NINA-B1 Data Sheet`_ -for a complete list of EVK NINA-B1 hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.08 -* LED1 (green) = P0.16 -* LED2 (blue) = P0.18 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.16 -* BUTTON2 = SW2 = P0.30 - - -General information on module pin numbering -------------------------------------------- - -The numbering of the pins on the module and EVK do not follow the GPIO -numbering on the nRF52832 SoC. Please see the `NINA-B1 Data Sheet`_ for -information on how to map NINA-B1 pins to the pin numbering on the -nRF52832 SoC. - -The reason for this is the u-blox module family concept where different -modules share the same pinout and can be interchanged, see -`NINA module family Nested design`_. - -Programming and Debugging -************************* - -Applications for the ``ubx_evkninab1_nrf52832`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); however, the standard -debugging targets are not currently available. - -Flashing -======== - -Build and flash applications as usual (see -:ref:`build_an_application` and :ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -Open a terminal program to the USB Serial Port installed when connecting -the board and listen for output. - -Settings: 115200, 8N1, no flow control. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_evkninab1_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging boards -containing a Nordic Semiconductor chip with a Segger IC. - - -Testing the LEDs and buttons in the EVK NINA-B11x -************************************************* - -There are 2 samples that allow you to test that the buttons (switches) -and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.dts`. - -Note that the buttons on the EVK-NINA-B1 are marked SW1 and SW2, which -are named sw0 and sw1 in the dts file. -Also note that the SW1 button and the green LED are connected on HW level. - - -References -********** - -.. target-notes:: - -.. _NINA-B1 product page: https://www.u-blox.com/en/product/nina-b1-series-open-cpu -.. _EVK-NINA-B1 product page: https://www.u-blox.com/en/product/evk-nina-b1 -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _NINA-B1 Data Sheet: https://www.u-blox.com/en/docs/UBX-15019243 -.. _NINA module family Nested design: https://www.u-blox.com/en/docs/UBX-17065600 diff --git a/boards/arm/ubx_evkninab3_nrf52840/Kconfig b/boards/arm/ubx_evkninab3_nrf52840/Kconfig deleted file mode 100644 index ca405a90b69..00000000000 --- a/boards/arm/ubx_evkninab3_nrf52840/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# EVK-NINA-B3 board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKNINAB3_NRF52840 diff --git a/boards/arm/ubx_evkninab3_nrf52840/Kconfig.board b/boards/arm/ubx_evkninab3_nrf52840/Kconfig.board deleted file mode 100644 index ee5b2dc98b9..00000000000 --- a/boards/arm/ubx_evkninab3_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# EVK-NINA-B3 board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_EVKNINAB3_NRF52840 - bool "u-blox EVK-NINA-B3" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_evkninab3_nrf52840/Kconfig.defconfig b/boards/arm/ubx_evkninab3_nrf52840/Kconfig.defconfig deleted file mode 100644 index e28e100e9fc..00000000000 --- a/boards/arm/ubx_evkninab3_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# EVK-NINA-B3 board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_EVKNINAB3_NRF52840 - -config BOARD - default "ubx_evkninab3_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_UBX_EVKNINAB3_NRF52840 diff --git a/boards/arm/ubx_evkninab3_nrf52840/doc/index.rst b/boards/arm/ubx_evkninab3_nrf52840/doc/index.rst deleted file mode 100644 index 6fc01e40a97..00000000000 --- a/boards/arm/ubx_evkninab3_nrf52840/doc/index.rst +++ /dev/null @@ -1,328 +0,0 @@ -.. _ubx_ninab3_nrf52840: - -u-blox EVK-NINA-B3 -################## - -Overview -******** - -The u-blox EVK-NINA-B30 Development Kit hardware provides support for the -u-blox NINA-B30x Bluetooth 5.0 module, based on the Nordic Semiconductor -nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/EVK-NINA-B3.jpg - :align: center - :alt: EVK-NINA-B3 - - EVK-NINA-B3 (Credit: u-blox AG) - -More information about the EVK-NINA-B3 and the NINA-B30x modules -can be found at the `u-blox website`_. - -Hardware -******** - -The NINA-B30x on the EVK-NINA-B30x contains an internal high-frequency -oscillator at 32MHz as well as a low frequency (slow) oscillator -of 32.768kHz. - - -Supported Features -================== - -The ubx_evkninab3_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | IEEE 802.15.4 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of EVK-NINA-B30x -hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.13 -* LED1 (green) = P0.25 -* LED2 (blue) = P1.00 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.25 -* BUTTON2 = SW2 = P0.2 -* BOOT = SW0 = boot/reset - -External Connectors -------------------- - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the EVK-NINA-B30x - for each header - - -Arduino Headers ---------------- - -Power (J1) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NINA-B30x Functions | -+=======+==============+=========================+ -| 1 | N/C | N/A | -+-------+--------------+-------------------------+ -| 2 | VDD_IO | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.18 / RESET | -+-------+--------------+-------------------------+ -| 4 | 3V3 | N/A | -+-------+--------------+-------------------------+ -| 5 | 5V0 | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | VIN | N/A | -+-------+--------------+-------------------------+ - -Analog in (J2) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NINA-B30x Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.05 / AIN3 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ - -Digital I/O (J3) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NINA-B30x Functions | -+=======+==============+=========================+ -| 8 | D7 | P0.10 | -+-------+--------------+-------------------------+ -| 7 | D6 | P0.09 | -+-------+--------------+-------------------------+ -| 6 | D5 | P0.11 | -+-------+--------------+-------------------------+ -| 5 | D4 | P0.13 | -+-------+--------------+-------------------------+ -| 4 | D3 | P0.31 | -+-------+--------------+-------------------------+ -| 3 | D2 | P1.12 | -+-------+--------------+-------------------------+ -| 2 | D1 (TX) | P1.13 | -+-------+--------------+-------------------------+ -| 1 | D0 (RX) | P0.29 | -+-------+--------------+-------------------------+ - -Digital I/O (J4) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NINA-B30x Functions | -+=======+==============+=========================+ -| 10 | SCL | P0.24 | -+-------+--------------+-------------------------+ -| 9 | SDA | P0.16 | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 6 | D13 (SCK) | P0.07 | -+-------+--------------+-------------------------+ -| 5 | D12 (MISO) | P1.00 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.15 | -+-------+--------------+-------------------------+ -| 3 | D10 (SS) | P0.14 | -+-------+--------------+-------------------------+ -| 2 | D9 | P0.12 | -+-------+--------------+-------------------------+ -| 1 | D8 | P1.09 | -+-------+--------------+-------------------------+ - - -Programming and Debugging -************************* - -Applications for the ``ubx_evkninab3_nrf52840`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); however, the standard -debugging targets are not currently available. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the EVK-NINA-B30x -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_evkninab3_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the EVK-NINA-B30x -************************************************* - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/ubx_evkninab3_nrf52840/ubx_ninab3_nrf52840.dts`. - -Using UART1 -*********** - -The following approach can be used when an application needs to use -more than one UART for connecting peripheral devices: - -1. Add device tree overlay file to the main directory of your application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default: uart1_default { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep: uart1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX - -2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` - -Overlay file naming -=================== - -The file has to be named ``.overlay`` and placed in the app main directory to be -picked up automatically by the device tree compiler. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the data sheet for the NINA-B3 at `u-blox website`_, Section 3 'Pin definition'. -In the table 7 select the pins marked 'GPIO_xx'. Note that pins marked as 'Radio sensitive pin' -can only be used in under-10KHz applications. They are not suitable for 115200 speed of UART. - -.. note: - Pins are defined according to the "nRF52" pin number, not the module pad number. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/en/product/nina-b3-series-open-cpu diff --git a/boards/arm/ubx_evkninab4_nrf52833/Kconfig b/boards/arm/ubx_evkninab4_nrf52833/Kconfig deleted file mode 100644 index 1b346d578f3..00000000000 --- a/boards/arm/ubx_evkninab4_nrf52833/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# NINA-B4 EVK board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKNINAB4_NRF52833 diff --git a/boards/arm/ubx_evkninab4_nrf52833/Kconfig.board b/boards/arm/ubx_evkninab4_nrf52833/Kconfig.board deleted file mode 100644 index 0eb3268ba9e..00000000000 --- a/boards/arm/ubx_evkninab4_nrf52833/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NINA-B4 EVK board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_EVKNINAB4_NRF52833 - bool "u-blox EVK-NINA-B4" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/ubx_evkninab4_nrf52833/Kconfig.defconfig b/boards/arm/ubx_evkninab4_nrf52833/Kconfig.defconfig deleted file mode 100644 index 0e6ffbcfc5a..00000000000 --- a/boards/arm/ubx_evkninab4_nrf52833/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# EVK-NINA-B4 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_EVKNINAB4_NRF52833 - -config BOARD - default "ubx_evkninab4_nrf52833" - -config BT_CTLR - default BT - -endif # BOARD_UBX_EVKNINAB4_NRF52833 diff --git a/boards/arm/ubx_evkninab4_nrf52833/doc/index.rst b/boards/arm/ubx_evkninab4_nrf52833/doc/index.rst deleted file mode 100644 index abdb7754a9d..00000000000 --- a/boards/arm/ubx_evkninab4_nrf52833/doc/index.rst +++ /dev/null @@ -1,230 +0,0 @@ -.. _ubx_ninab4_nrf52833: - -u-blox EVK NINA-B40x -#################### - -Overview -******** - -The u-blox NINA-B4 Evaluation Kit hardware is a Bluetooth low energy -module based on the Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU -and has support for the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/EVK-NINA-B406_Top_web.jpg - - EVK NINA-B4 - -More information about the NINA-B4 module and the EVK-NINA-B4 can be -found at `NINA-B40 product page`_ and `EVK-NINA-B4 product page`_. - -Supported Features -================== - -The ubx_evkninab4_nrf52833 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth low energy | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `EVK-NINA-B4 product page`_ and `NINA-B40 Data Sheet`_ -for a complete list of EVK NINA-B4 hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.13 -* LED1 (green) = P1.01 -* LED2 (blue) = P1.00 - -Push buttons ------------- - -* BUTTON1 = SW1 = P1.01 (Shared with green LED) -* BUTTON2 = SW2 = P0.02 - -General information on module pin numbering -------------------------------------------- - -The numbering of the pins on the module and EVK do not follow the GPIO -numbering on the nRF52833 SoC. Please see the `NINA-B40 Data Sheet`_ for -information on how to map NINA-B40 pins to the pin numbering on the -nRF52833 SoC. - -The reason for this is the u-blox module family concept where different -modules share the same pinout and can be interchanged, see -`NINA module family Nested design`_. - -Programming and Debugging -************************* - -Applications for the ``ubx_evkninab4_nrf52833`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); however, the standard -debugging targets are not currently available. - -Flashing -======== - -Build and flash applications as usual (see -:ref:`build_an_application` and :ref:`application_run` for more details) - -Here is an example for the :ref:`hello_world` application. - -Open a terminal program to the USB Serial Port installed when connecting -the board and listen for output. - -Settings: 115200, 8N1, no flow control. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_evknina4_nrf52833 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging boards -containing a Nordic Semiconductor chip with a Segger IC. - - -Testing the LEDs and buttons in the EVK NINA-B40x -************************************************* - -There are 2 samples that allow you to test that the buttons (switches) -and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.dts`. - -Note that the buttons on the EVK-NINA-B4 are marked SW1 and SW2, which -are named sw0 and sw1 in the dts file. -Also note that the SW1 button and the green LED are connected on HW level. - -Using UART1 -*********** - -The following approach can be used when an application needs to use -more than one UART for connecting peripheral devices: - -1. Add device tree overlay file to the main directory of your application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default: uart1_default { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep: uart1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX - -2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` - -Overlay file naming -=================== - -The file has to be named ``.overlay`` and placed in the app main directory to be -picked up automatically by the device tree compiler. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the data sheet for the NINA-B4 at `NINA-B40 Data Sheet`_, Section 3 'Pin definition'. -In the table 7 select the pins marked 'GPIO_xx'. Note that pins marked as 'Radio sensitive pin' -can only be used in under-10KHz applications. They are not suitable for 115200 speed of UART. - -.. note: - Pins are defined according to the "nRF52" pin number, not the module pad number. - - -References -********** - -.. target-notes:: - -.. _NINA-B40 product page: https://www.u-blox.com/en/product/nina-b40-series-open-cpu -.. _EVK-NINA-B4 product page: https://www.u-blox.com/en/product/evk-nina-b4 -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _NINA-B40 Data Sheet: https://www.u-blox.com/en/docs/UBX-19049405 -.. _NINA module family Nested design: https://www.u-blox.com/en/docs/UBX-17065600 diff --git a/boards/arm/ucans32k1sic/Kconfig.board b/boards/arm/ucans32k1sic/Kconfig.board deleted file mode 100644 index 314c7f98d5e..00000000000 --- a/boards/arm/ucans32k1sic/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UCANS32K1SIC - bool "ucans32k1sic" - depends on SOC_SERIES_S32K1XX - select SOC_PART_NUMBER_FS32K146UAT0VLHT diff --git a/boards/arm/ucans32k1sic/Kconfig.defconfig b/boards/arm/ucans32k1sic/Kconfig.defconfig deleted file mode 100644 index 044df50c0c5..00000000000 --- a/boards/arm/ucans32k1sic/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UCANS32K1SIC - -config BOARD - default "ucans32k1sic" - -if SERIAL - -config UART_CONSOLE - default y - -endif # SERIAL - -if CAN - -config GPIO - default y - -endif # CAN - -endif # BOARD_UCANS32K1SIC diff --git a/boards/arm/ucans32k1sic/doc/index.rst b/boards/arm/ucans32k1sic/doc/index.rst deleted file mode 100644 index 66138b44a00..00000000000 --- a/boards/arm/ucans32k1sic/doc/index.rst +++ /dev/null @@ -1,197 +0,0 @@ -.. _ucans32k1sic: - -NXP UCANS32K1SIC -################ - -Overview -******** - -`NXP UCANS32K1SIC`_ is a CAN signal improvement capability (SIC) evaluation -board designed for both automotive and industrial applications. The UCANS32K1SIC -provides two CAN SIC interfaces and is based on the 32-bit Arm Cortex-M4F -`NXP S32K146`_ microcontroller. - -.. image:: img/ucans32k1sic_top.webp - :align: center - :alt: NXP UCANS32K1SIC (TOP) - -Hardware -******** - -- NXP S32K146 - - Arm Cortex-M4F @ up to 112 Mhz - - 1 MB Flash - - 128 KB SRAM - - up to 127 I/Os - - 3x FlexCAN with 2x FD - - eDMA, 12-bit ADC, MPU, ECC and more. - -- Interfaces: - - DCD-LZ debug interface with SWD + Console / UART - - Dual CAN FD PHYs with dual connectors for daisy chain operation - - JST-GH DroneCode compliant standard connectors and I/O headers - - user RGB LED and button. - -More information about the hardware and design resources can be found at -`NXP UCANS32K1SIC`_ website. - -Supported Features -================== - -The ``ucans32k1sic`` board configuration supports the following hardware features: - -============ ========== ================================ -Interface Controller Driver/Component -============ ========== ================================ -SYSMPU on-chip mpu -PORT on-chip pinctrl -GPIO on-chip gpio -LPUART on-chip serial -LPI2C on-chip i2c -LPSPI on-chip spi -FTM on-chip pwm -FlexCAN on-chip can -Watchdog on-chip watchdog -RTC on-chip counter -============ ========== ================================ - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/ucans32k1sic/ucans32k1sic_defconfig`. - -Connections and IOs -=================== - -This board has 5 GPIO ports named from ``gpioa`` to ``gpioe``. - -Pin control can be further configured from your application overlay by adding -children nodes with the desired pinmux configuration to the singleton node -``pinctrl``. Supported properties are described in -:zephyr_file:`dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml`. - -LEDs ----- - -The UCANS32K1SIC board has one user RGB LED that can be used either as a GPIO -LED or as a PWM LED. - -.. table:: RGB LED as GPIO LED - :widths: auto - - =============== ================ =============== ===== - Devicetree node Devicetree alias Label Pin - =============== ================ =============== ===== - led1_red led0 LED1_RGB_RED PTD15 - led1_green led1 LED1_RGB_GREEN PTD16 - led1_blue led2 LED1_RGB_BLUE PTD0 - =============== ================ =============== ===== - -.. table:: RGB LED as PWM LED - :widths: auto - - =============== ======================== ================== ================ - Devicetree node Devicetree alias Label Pin - =============== ======================== ================== ================ - led1_red_pwm pwm-led0 / red-pwm-led LED1_RGB_RED_PWM PTD15 / FTM0_CH0 - led1_green_pwm pwm-led1 / green-pwm-led LED1_RGB_GREEN_PWM PTD16 / FTM0_CH1 - led1_blue_pwm pwm-led2 / blue-pwm-led LED1_RGB_BLUE_PWM PTD0 / FTM0_CH2 - =============== ======================== ================== ================ - -The user can control the LEDs in any way. An output of ``0`` illuminates the LED. - -Buttons -------- - -The UCANS32K1SIC board has one user button: - -======================= ============== ===== -Devicetree node Label Pin -======================= ============== ===== -sw0 / button_3 SW3 PTD15 -======================= ============== ===== - -Serial Console -============== - -The serial console is provided via ``lpuart1`` on the 7-pin DCD-LZ debug -connector ``P6``. - -========= ===== ============ -Connector Pin Pin Function -========= ===== ============ -P6.2 PTC7 LPUART1_TX -P6.3 PTC6 LPUART1_RX -========= ===== ============ - -System Clock -============ - -The Arm Cortex-M4F core is configured to run at 80 MHz (RUN mode). - -Programming and Debugging -************************* - -Applications for the ``ucans32k1sic`` board can be built in the usual way as -documented in :ref:`build_an_application`. - -This board configuration supports `Lauterbach TRACE32`_ and `SEGGER J-Link`_ -West runners for flashing and debugging applications. Follow the steps described -in :ref:`lauterbach-trace32-debug-host-tools` and :ref:`jlink-debug-host-tools`, -to setup the flash and debug host tools for these runners, respectively. The -default runner is J-Link. - -Flashing -======== - -Run the ``west flash`` command to flash the application using SEGGER J-Link. -Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32. - -The Lauterbach TRACE32 runner supports additional options that can be passed -through command line: - -.. code-block:: console - - west flash -r trace32 --startup-args elfFile= loadTo= - eraseFlash= verifyFlash= - -Where: - -- ```` is the path to the Zephyr application ELF in the output - directory -- ``loadTo=flash`` loads the application to the SoC internal program flash - (:kconfig:option:`CONFIG_XIP` must be set), and ``loadTo=sram`` load the - application to SRAM. The default is ``flash``. -- ``eraseFlash=yes`` erases the whole content of SoC internal flash before the - application is downloaded to either Flash or SRAM. This routine takes time to - execute. The default is ``no``. -- ``verifyFlash=yes`` verify the SoC internal flash content after programming - (use together with ``loadTo=flash``). The default is ``no``. - -For example, to erase and verify flash content: - -.. code-block:: console - - west flash -r trace32 --startup-args elfFile=build/zephyr/zephyr.elf loadTo=flash eraseFlash=yes verifyFlash=yes - -Debugging -========= - -Run the ``west debug`` command to start a GDB session using SEGGER J-Link. -Alternatively, run ``west debug -r trace32`` to launch the Lauterbach TRACE32 -software debugging interface. - -References -********** - -.. target-notes:: - -.. _NXP UCANS32K1SIC: - https://www.nxp.com/design/development-boards/analog-toolbox/can-sic-evaluation-board:UCANS32K1SIC - -.. _NXP S32K146: - https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k1-microcontrollers-for-automotive-general-purpose:S32K1 - -.. _Lauterbach TRACE32: - https://www.lauterbach.com - -.. _SEGGER J-Link: - https://wiki.segger.com/S32Kxxx diff --git a/boards/arm/ucans32k1sic/ucans32k1sic_defconfig b/boards/arm/ucans32k1sic/ucans32k1sic_defconfig deleted file mode 100644 index 8580c7155cb..00000000000 --- a/boards/arm/ucans32k1sic/ucans32k1sic_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_UCANS32K1SIC=y -CONFIG_SOC_SERIES_S32K1XX=y -CONFIG_SOC_S32K146=y -CONFIG_BUILD_OUTPUT_HEX=y - -# Use Systick as system clock -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000 - -# Run from internal program flash -CONFIG_XIP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y diff --git a/boards/arm/udoo_neo_full_m4/Kconfig.board b/boards/arm/udoo_neo_full_m4/Kconfig.board deleted file mode 100644 index f9f67b923ed..00000000000 --- a/boards/arm/udoo_neo_full_m4/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UDOO_NEO_FULL_M4 - bool "UDOO Neo Full" - depends on SOC_SERIES_IMX_6X_M4 - select SOC_PART_NUMBER_MCIMX6X4EVM10AB diff --git a/boards/arm/udoo_neo_full_m4/Kconfig.defconfig b/boards/arm/udoo_neo_full_m4/Kconfig.defconfig deleted file mode 100644 index 62636188a78..00000000000 --- a/boards/arm/udoo_neo_full_m4/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# UDOO Neo Full board - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UDOO_NEO_FULL_M4 - -config BOARD - default "udoo_neo_full_m4" - -endif # BOARD_UDOO_NEO_FULL_M4 diff --git a/boards/arm/udoo_neo_full_m4/doc/index.rst b/boards/arm/udoo_neo_full_m4/doc/index.rst deleted file mode 100644 index f3c11e3dd31..00000000000 --- a/boards/arm/udoo_neo_full_m4/doc/index.rst +++ /dev/null @@ -1,368 +0,0 @@ -.. _udoo_neo_full_m4: - -UDOO Neo Full -############# - -Overview -******** - -UDOO Neo Full is an open source Arduino Uno compatible single board computer. -It is equipped with an NXP |reg| i.MX 6SoloX hybrid multicore processor -composed of one ARM |reg| Cortex-A9 core running up to 1 GHz and one Cortex-M4 -core running up to 227 MHz for high CPU performance and real-time response. -Zephyr was ported to run on the Cortex-M4 core only. In a future release, it -will also communicate with the Cortex-A9 core (running Linux) via OpenAMP. - -.. figure:: udoo_neo_full_m4.jpg - :align: center - :alt: UDOO-Neo-Full - - UDOO Neo Full (Credit: udoo.org) - -Hardware -******** - -- MCIMX6X MCU with a single Cortex-A9 (1 GHz) core and single Cortex-M4 (227 MHz) core - -- Memory - - - 1 GB RAM - - 128 KB OCRAM - - 256 KB L2 cache (can be switched into OCRAM instead) - - 16 KB OCRAM_S - - 32 KB TCML - - 32 KB TCMU - - 32 KB CAAM (secure RAM) - -- A9 Boot Devices - - - NOR flash - - NAND flash - - OneNAND flash - - SD/MMC - - Serial (I2C/SPI) NOR flash and EEPROM - - QuadSPI (QSPI) flash - -- Display - - - Micro HDMI connector - - LVDS display connector - - Touch (I2C signals) - -- Multimedia - - - Integrated 2d/3d graphics controller - - 8-bit parallel interface for analog camera supporting NTSC and PAL - - HDMI audio transmitter - - S/PDIF - - I2S - -- Connectivity - - - USB 2.0 Type A port - - USB OTG (micro-AB connector) - - 10/100 Mbit/s Ethernet PHY - - Wi-Fi 802.11 b/g/n - - Bluetooth 4.0 Low Energy - - 3x UART ports - - 2x CAN Bus interfaces - - 8x PWM signals - - 3x I2C interface - - 1x SPI interface - - 6x multiplexable signals - - 32x GPIO (A9) - - 22x GPIO (M4) - -- Other - - - MicroSD card slot (8-bit SDIO interface) - - Power status LED (green) - - 2x user LED (red and orange) - -- Power - - - 5 V DC Micro USB - - 6-15 V DC jack - - RTC battery connector - -- Debug - - - pads for soldering of JTAG 14-pin connector - -- Sensor - - - 3-Axis Accelerometer - - 3-Axis Magnetometer - - 3-Axis Digital Gyroscope - - 1x Sensor Snap-In I2C connector - -- Expansion port - - - Arduino interface - -For more information about the MCIMX6X SoC and UDOO Neo Full board, -see these references: - -- `NXP i.MX 6SoloX Website`_ -- `NXP i.MX 6SoloX Datasheet`_ -- `NXP i.MX 6SoloX Reference Manual`_ -- `UDOO Neo Website`_ -- `UDOO Neo Getting Started`_ -- `UDOO Neo Documentation`_ -- `UDOO Neo Datasheet`_ -- `UDOO Neo Schematics`_ - -Supported Features -================== - -The UDOO Neo Full board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | general purpose input/output | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | counter | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/udoo_neo_full_m4/udoo_neo_full_m4_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The UDOO Neo Full board was tested with the following pinmux -controller configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| J4 RX | UART5_RX_DATA | UART Console | -+---------------+-----------------+---------------------------+ -| J4 TX | UART5_TX_DATA | UART Console | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The MCIMX6X SoC is configured to use the 24 MHz external oscillator -on the board with the on-chip PLL to generate core clock. -PLL settings for M4 core are set via code running on the A9 core. - -Serial Port -=========== - -The MCIMX6X SoC has six UARTs. UART5 is configured for the M4 core and the -remaining are used by the A9 core or not used. - -Programming and Debugging -************************* - -The M4 core does not have a flash memory and is not provided a clock -at power-on-reset. Therefore it needs to be started by the A9 core. -The A9 core is responsible to load the M4 binary application into the RAM, -put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get -the M4 out of reset. The A9 can perform these steps at the bootloader level -or after the Linux system has booted. - -The M4 core can use up to 5 different RAMs (some other types of memory like -a secure RAM are not currently implemented in Zephyr). -These are the memory mappings for A9 and M4: - -+------------+-----------------------+-----------------------+-----------------------+ -| Region | Cortex-A9 | Cortex-M4 | Size | -+============+=======================+=======================+=======================+ -| TCML | 0x007F8000-0x007FFFFF | 0x1FFF8000-0x1FFFFFFF | 32 KB | -+------------+-----------------------+-----------------------+-----------------------+ -| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | 32 KB | -+------------+-----------------------+-----------------------+-----------------------+ -| OCRAM_S | 0x008F8000-0x008FBFFF | 0x208F8000-0x208FBFFF | 16 KB | -+------------+-----------------------+-----------------------+-----------------------+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20900000-0x2091FFFF | 128 KB | -+------------+-----------------------+-----------------------+-----------------------+ -| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 2048 MB (1536 for M4) | -+------------+-----------------------+-----------------------+-----------------------+ - -References -========== - -- `NXP i.MX 6SoloX Reference Manual`_ Chapter 2 - Memory Maps - -You have to choose which RAM will be used at compilation time. This configuration -is done in the file ``boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.dts``. - -If you want to have the code placed in the subregion of a memory, which will -likely be the case when using DDR, select "zephyr,flash=&flash" and set the -DT_FLASH_SIZE macro to determine the region size and DT_FLASH_ADDR to determine -the address where the region begins. - -If you want to have the data placed in the subregion of a memory, which will -likely be the case when using DDR, select "zephyr,sram = &sram", which sets the -CONFIG_SRAM_SIZE macro to determine the region size and -CONFIG_SRAM_BASE_ADDRESS to determine the address where the region begins. - -Otherwise set "zephyr,flash" and/or "zephyr,sram" to one of the predefined -regions: - -.. code-block:: none - - "zephyr,flash" - - &tcml - - &ocram_s - - &ocram - - &ddr - - "zephyr,sram" - - &tcmu - - &ocram_s - - &ocram - - &ddr - -Below you will find the instructions how a Linux user space application running -on the A9 core can be used to load and run Zephyr application on the M4 core. - -The UDOOBuntu Linux distribution contains a `udooneo-m4uploader`_ utility, -but its purpose is to load UDOO Neo "Arduino-like" sketches, so it doesn't -work with Zephyr applications in most cases. The reason is that there is -an exchange of information between this utility and the program running on the -M4 core using hardcoded shared memory locations. The utility writes a flag which -is read by the program running on the M4 core. The program is then supposed to -end safely and write the status to the shared memory location for the main core. -The utility then loads the new application and reads its status from the shared -memory location to determine if it has successfully launched. Since this -functionality is specific for the UDOO Neo "Arduino-like" sketches, it is not -implemented in Zephyr. However Zephyr applications can support it on their own -if planned to be used along with the UDOOBuntu Linux running on the A9 core. -The udooneo-uploader utility calls another executable named -mqx_upload_on_m4SoloX which can be called directly to load Zephyr applications. -Copy the Zephyr binary image into the Linux filesystem and invoke the utility -as a root user: - -.. code-block:: console - - mqx_upload_on_m4SoloX zephyr.bin - -If the output looks like below, the mqx_upload_on_m4SoloX could not read -the status of the stopped application. This is expected if the previously -loaded application is not a UDOO Neo "Arduino-like" sketch and ignores the -shared memory communication: - -.. code-block:: console - - UDOONeo - mqx_upload_on_m4SoloX 1.1.0 - UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 - UDOONeo - Failed to Stop M4 sketch: reboot system ! - -In such situation, the mqx_upload_on_m4SoloX utility has reset the trace flags, -so it will succeed when called again. Then it can have this output below: - -.. code-block:: console - - UDOONeo - mqx_upload_on_m4SoloX 1.1.0 - UDOONeo - FILENAME = zephyr.bin; loadaddr = 0x84000000 - UDOONeo - start - end (0x84000000 - 0x84080000) - UDOONeo - Waiting M4 Run, m4TraceFlags: 000001E0 - UDOONeo - M4 sketch is running - -Or the one below, if the utility cannot read the status flag that the M4 core -applications has started. It can be ignored as the application should be -running, the utility just doesn't know it: - -.. code-block:: console - - UDOONeo - mqx_upload_on_m4SoloX 1.1.0 - UDOONeo - FILENAME = zephyr.bin; loadaddr = 0x84000000 - UDOONeo - start - end (0x84000000 - 0x84080000) - UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 - UDOONeo - Failed to Start M4 sketch: reboot system ! - -The stack pointer and the program counter values are read from the binary. -The memory address where binary will be placed is calculated from the program -counter as its value aligned to 64 KB down, or it can be provided as a second -command line argument: - -.. code-block:: console - - mqx_upload_on_m4SoloX zephyr.bin 0x84000000 - -It is necessary to provide the address if the binary is copied into a memory -region which has different mapping between the A9 and the M4 core. The address -calculated from the stack pointer value in the binary file would be wrong. - -It is possible to modify the mqx_upload_on_m4SoloX utility source code -to not exchange the information with the M4 core application using shared -memory. - -It is also possible to use the `imx-m4fwloader`_ utility to load the M4 core -application. - -One option applicable in UDOOBuntu Linux is to copy the binary file into the -file /var/opt/m4/m4last.fw in the Linux filesystem. The next time the system is -booted, Das U-Boot will load it from there. - -Another option is to directly use Das U-Boot to load the code. - -Debugging -========= - -The UDOO Neo Full board includes pads for soldering the 14-pin JTAG -connector. Zephyr applications running on the M4 core have only been -tested by observing UART console output. - -References -========== - -.. target-notes:: - -.. _UDOO Neo Website: - https://www.udoo.org/udoo-neo/ - -.. _UDOO Neo Getting Started: - https://www.udoo.org/get-started-neo/ - -.. _UDOO Neo Documentation: - https://www.udoo.org/docs-neo - -.. _UDOO Neo Datasheet: - https://www.udoo.org/download/files/datasheets/datasheet_udoo_neo.pdf - -.. _UDOO Neo Schematics: - https://www.udoo.org/download/files/schematics/UDOO_NEO_schematics.pdf - -.. _Udoo Neo Linux or Android Images for the A9 Core: - https://www.udoo.org/downloads/ - -.. _udooneo-m4uploader: - https://github.com/ektor5/udooneo-m4uploader - -.. _imx-m4fwloader: - https://github.com/codeauroraforum/imx-m4fwloader - -.. _NXP i.MX 6SoloX Website: - https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-6-processors/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:i.MX6SX - -.. _NXP i.MX 6SoloX Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMX6SXCEC.pdf - -.. _NXP i.MX 6SoloX Reference Manual: - https://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf - -.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: - https://www.nxp.com/docs/en/application-note/AN5317.pdf diff --git a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.dts b/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.dts deleted file mode 100644 index 6e7ee0bfb63..00000000000 --- a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.dts +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2018, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/* - * Determines the address and size for code memory which will be applied - * when "zephyr,flash = &flash". Use this to select a custom region, - * usually within DDR. - */ -#define DT_FLASH_SIZE DT_SIZE_K(512) -#define DT_FLASH_ADDR 84000000 /* DT_ADDR will add leading 0x where needed */ - -/* - * Determines the address and size for data memory which will be applied - * when "zephyr,sram = &sram". Use this to select a custom region, - * usually within DDR. - */ -#define DT_SRAM_SIZE DT_SIZE_K(128) -#define DT_SRAM_ADDR 84080000 /* DT_ADDR will add leading 0x where needed */ - -#include -#include "udoo_neo_full_m4-pinctrl.dtsi" - -/ { - model = "UDOO Neo Full board"; - compatible = "nxp,mcimx6x_m4"; - - aliases { - led0 = &red_led; - }; - - chosen { - zephyr,flash = &flash; - zephyr,sram = &tcmu; - zephyr,console = &uart5; - zephyr,shell-uart = &uart5; - }; - - leds { - compatible = "gpio-leds"; - red_led: led_0 { - gpios = <&gpio4 6 0>; - label = "User LD1"; - }; - }; -}; - -&uart5 { - status = "okay"; - current-speed = <115200>; - modem-mode = <0>; - pinctrl-0 = <&uart5_default>; - pinctrl-names = "default"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&gpio6 { - status = "okay"; -}; - -&mub { - status = "okay"; -}; - -&epit1 { - status = "okay"; -}; - -&epit2 { - status = "okay"; -}; diff --git a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.yaml b/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.yaml deleted file mode 100644 index 8e2876ca5ab..00000000000 --- a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: udoo_neo_full_m4 -name: UDOO Neo Full -type: mcu -arch: arm -ram: 32 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - uart -vendor: nxp diff --git a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4_defconfig b/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4_defconfig deleted file mode 100644 index c03d8770a7d..00000000000 --- a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MCIMX6X_M4=y -CONFIG_SOC_SERIES_IMX_6X_M4=y -CONFIG_BOARD_UDOO_NEO_FULL_M4=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=227000000 -CONFIG_PINCTRL=y diff --git a/boards/arm/usb_kw24d512/Kconfig.board b/boards/arm/usb_kw24d512/Kconfig.board deleted file mode 100644 index f76553fe19d..00000000000 --- a/boards/arm/usb_kw24d512/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# USB-KW24D512 board - -# Copyright (c) 2017, Phytec Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_USB_KW24D512 - bool "NXP USB-KW24D512" - depends on SOC_SERIES_KINETIS_KWX - select SOC_PART_NUMBER_MKW24D512VHA5 diff --git a/boards/arm/usb_kw24d512/Kconfig.defconfig b/boards/arm/usb_kw24d512/Kconfig.defconfig deleted file mode 100644 index 373eae6292a..00000000000 --- a/boards/arm/usb_kw24d512/Kconfig.defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# USB-KW24D512 board - -# Copyright (c) 2017, Phytec Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_USB_KW24D512 - -config BOARD - default "usb_kw24d512" - -config OSC_XTAL0_FREQ - # The MCU is configured to use 4 MHz external - # clock from the transceiver provided at the CLK_OUT output. - # CLK_OUT is internally connected to the input pin EXTAL0 - # of the MCU. - default 4000000 - -config MCG_PRDIV0 - default 0x1 - -config MCG_VDIV0 - default 0x0 - -config MCG_FCRDIV - default 2 - -config MCR20A_IS_PART_OF_KW2XD_SIP - default y - depends on IEEE802154_MCR20A - -endif # BOARD_USB_KW24D512 diff --git a/boards/arm/usb_kw24d512/doc/index.rst b/boards/arm/usb_kw24d512/doc/index.rst deleted file mode 100644 index 41b0d956c93..00000000000 --- a/boards/arm/usb_kw24d512/doc/index.rst +++ /dev/null @@ -1,231 +0,0 @@ -.. _usb_kw24d512: - -NXP USB-KW24D512 -################ - -Overview -******** - -The USB-KW24D512 is an evaluation board in a convenient USB dongle -form factor based on the NXP MKW24D512 System-in-Package (SiP) device -(KW2xD wireless MCU series). -MKW24D512 wireless MCU provides a low-power, compact device with -integrated IEEE 802.15.4 radio. The board can be used as a packet sniffer, -network node, border router or as a development board. - -Hardware -******** - -- Kinetis KW2xD-2.4 GHz 802.15.4 Wireless Radio Microcontroller - (50 MHz, 512 KB flash memory, 64 KB RAM, low-power, crystal-less USB) -- USB Type A Connector -- Two blue LEDs -- One user push button -- One reset button -- Integrated PCB Folded F-type antenna -- 10-pin (0.05”) JTAG debug port for target MCU - -For more information about the KW2xD SiP and USB-KW24D512 board: - -- `KW2xD Website`_ -- `KW2xD Datasheet`_ -- `KW2xD Reference Manual`_ -- `USB-KW24D512 Website`_ -- `USB-KW24D512 Hardware Reference Manual`_ - -Supported Features -================== - -The USB-KW24D512 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| RNGA | on-chip | entropy; | -| | | random | -+-----------+------------+-------------------------------------+ -| FTFL | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/usb_kw24d512/usb_kw24d512_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The KW2xD SoC has five pairs of pinmux/gpio controllers. - -+-------+-----------------+--------------------------------------+ -| Name | Function | Usage | -+=======+=================+======================================+ -| PTA1 | UART0_RX | UART Console | -+-------+-----------------+--------------------------------------+ -| PTA2 | UART0_TX | UART Console | -+-------+-----------------+--------------------------------------+ -| PTC4 | GPIO | SW1 | -+-------+-----------------+--------------------------------------+ -| PTD4 | GPIO | Blue LED (D2) | -+-------+-----------------+--------------------------------------+ -| PTD5 | GPIO | Blue LED (D3) | -+-------+-----------------+--------------------------------------+ -| PTB10 | SPI1_PCS0 | internal connected to MCR20A | -+-------+-----------------+--------------------------------------+ -| PTB11 | SPI1_SCK | internal connected to MCR20A | -+-------+-----------------+--------------------------------------+ -| PTB16 | SPI1_SOUT | internal connected to MCR20A | -+-------+-----------------+--------------------------------------+ -| PTB17 | SPI1_SIN | internal connected to MCR20A | -+-------+-----------------+--------------------------------------+ -| PTB19 | GPIO | internal connected to MCR20A (Reset) | -+-------+-----------------+--------------------------------------+ -| PTB3 | GPIO | internal connected to MCR20A (IRQ_B) | -+-------+-----------------+--------------------------------------+ -| PTC0 | GPIO | internal connected to MCR20A (GPIO5) | -+-------+-----------------+--------------------------------------+ - -System Clock -============ - -USB-KW24D512 contains 32 MHz oscillator crystal, which is connected to the -clock pins of the radio transceiver. The MCU is configured to -use the 4 MHz external clock from the transceiver with the on-chip PLL -to generate a 48 MHz system clock. - -Serial Port -=========== - -The KW2xD SoC has three UARTs. One is configured and can be used for the -console, but it uses the same pins as the JTAG interface and is only -accessible via the JTAG SWD connector. - -USB -=== - -The KW2xD SoC has a USB OTG (USBOTG) controller that supports both -device and host functions. Only USB device function is supported in Zephyr -at the moment. The USB-KW24D512 board has a USB Type A connector and -can only be used in device mode. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`jlink-external-debug-probe`. - -:ref:`jlink-external-debug-probe` ---------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Attach a J-Link 10-pin connector to J1. - -Configuring a Console -===================== - -The console is available using `Segger RTT`_. - -Connect a USB cable from your PC to J5. - -Once you have started a debug session, run telnet: - -.. code-block:: console - - Trying 127.0.0.1... - Connected to localhost. - Escape character is '^]'. - SEGGER J-Link V6.44 - Real time terminal output - SEGGER J-Link ARM V10.1, SN=600111924 - Process: JLinkGDBServerCLExe - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: usb_kw24d512 - :goals: flash - -The Segger RTT console is only available during a debug session. Use ``attach`` -to start one: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: usb_kw24d512 - :goals: attach - -Run telnet as shown earlier, and you should see the following message in the -terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! usb_kw24d512 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: usb_kw24d512 - :goals: debug - -Run telnet as shown earlier, step through the application in your debugger, and -you should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! usb_kw24d512 - -.. _USB-KW24D512 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/ieee-802.15.4-packet-sniffer-usb-dongle-form-factor:USB-KW24D512 - -.. _USB-KW24D512 Hardware Reference Manual: - https://www.nxp.com/webapp/Download?colCode=USB-KW2XHWRM - -.. _KW2xD Website: - https://www.nxp.com/products/wireless/thread/kinetis-kw2xd-2.4-ghz-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m4-core:KW2xD - -.. _KW2xD Datasheet: - https://www.nxp.com/docs/en/data-sheet/MKW2xDxxx.pdf - -.. _KW2xD Reference Manual: - https://www.nxp.com/webapp/Download?colCode=MKW2XDXXXRM - -.. _Segger RTT: - https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/ diff --git a/boards/arm/usb_kw24d512/usb_kw24d512_defconfig b/boards/arm/usb_kw24d512/usb_kw24d512_defconfig deleted file mode 100644 index 1d9dbb04067..00000000000 --- a/boards/arm/usb_kw24d512/usb_kw24d512_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_MKW24D5=y -CONFIG_SOC_SERIES_KINETIS_KWX=y -CONFIG_BOARD_USB_KW24D512=y -CONFIG_CONSOLE=y -CONFIG_RTT_CONSOLE=y -CONFIG_USE_SEGGER_RTT=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 -CONFIG_OSC_EXTERNAL=y diff --git a/boards/arm/v2m_beetle/Kconfig.board b/boards/arm/v2m_beetle/Kconfig.board deleted file mode 100644 index 6c0d883865d..00000000000 --- a/boards/arm/v2m_beetle/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# ARM V2M Beetle Board configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# V2M (V2 = Versatile Express, M = Motherboard) -config BOARD_V2M_BEETLE - bool "ARM V2M Beetle Board" - depends on SOC_BEETLE_R0 diff --git a/boards/arm/v2m_beetle/Kconfig.defconfig b/boards/arm/v2m_beetle/Kconfig.defconfig index 2c88eebef39..3e04387a233 100644 --- a/boards/arm/v2m_beetle/Kconfig.defconfig +++ b/boards/arm/v2m_beetle/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_V2M_BEETLE -config BOARD - default "v2m_beetle" - if SERIAL config UART_INTERRUPT_DRIVEN diff --git a/boards/arm/v2m_beetle/Kconfig.v2m_beetle b/boards/arm/v2m_beetle/Kconfig.v2m_beetle new file mode 100644 index 00000000000..574be8a942b --- /dev/null +++ b/boards/arm/v2m_beetle/Kconfig.v2m_beetle @@ -0,0 +1,8 @@ +# ARM V2M Beetle Board configuration options + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# V2M (V2 = Versatile Express, M = Motherboard) +config BOARD_V2M_BEETLE + select SOC_BEETLE_R0 diff --git a/boards/arm/v2m_beetle/board.yml b/boards/arm/v2m_beetle/board.yml new file mode 100644 index 00000000000..b19e9bfec75 --- /dev/null +++ b/boards/arm/v2m_beetle/board.yml @@ -0,0 +1,5 @@ +board: + name: v2m_beetle + vendor: arm + socs: + - name: beetle_r0 diff --git a/boards/arm/v2m_beetle/v2m_beetle_defconfig b/boards/arm/v2m_beetle/v2m_beetle_defconfig index 7301a8a2732..175c3072e9f 100644 --- a/boards/arm/v2m_beetle/v2m_beetle_defconfig +++ b/boards/arm/v2m_beetle/v2m_beetle_defconfig @@ -6,11 +6,9 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_BEETLE_R0=y -CONFIG_SOC_SERIES_BEETLE=y -CONFIG_BOARD_V2M_BEETLE=y CONFIG_RUNTIME_NMI=y CONFIG_CLOCK_CONTROL=y + # 24MHz system clock CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=24000000 diff --git a/boards/arm/v2m_musca_b1/Kconfig.board b/boards/arm/v2m_musca_b1/Kconfig.board deleted file mode 100644 index 6fc98094cfd..00000000000 --- a/boards/arm/v2m_musca_b1/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MUSCA_B1 - bool "ARM Cortex-M33 SMM on V2M-MUSCA" - depends on SOC_SERIES_MUSCA_B1 diff --git a/boards/arm/v2m_musca_b1/Kconfig.defconfig b/boards/arm/v2m_musca_b1/Kconfig.defconfig index 77dc7e9ad36..24b1c90fe77 100644 --- a/boards/arm/v2m_musca_b1/Kconfig.defconfig +++ b/boards/arm/v2m_musca_b1/Kconfig.defconfig @@ -1,11 +1,7 @@ # Copyright (c) 2019 Linaro Limited # SPDX-License-Identifier: Apache-2.0 -if BOARD_MUSCA_B1 - -config BOARD - default "musca_b1" if TRUSTED_EXECUTION_SECURE || !TRUSTED_EXECUTION_NONSECURE - default "musca_b1_ns" +if BOARD_V2M_MUSCA_B1 if SERIAL @@ -14,4 +10,4 @@ config UART_INTERRUPT_DRIVEN endif # SERIAL -endif +endif # BOARD_V2M_MUSCA_B1 diff --git a/boards/arm/v2m_musca_b1/Kconfig.v2m_musca_b1 b/boards/arm/v2m_musca_b1/Kconfig.v2m_musca_b1 new file mode 100644 index 00000000000..3171dc5033e --- /dev/null +++ b/boards/arm/v2m_musca_b1/Kconfig.v2m_musca_b1 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_V2M_MUSCA_B1 + select SOC_V2M_MUSCA_B1 diff --git a/boards/arm/v2m_musca_b1/board.yml b/boards/arm/v2m_musca_b1/board.yml new file mode 100644 index 00000000000..47cebc33bb1 --- /dev/null +++ b/boards/arm/v2m_musca_b1/board.yml @@ -0,0 +1,7 @@ +board: + name: v2m_musca_b1 + vendor: arm + socs: + - name: musca_b1 + variants: + - name: 'ns' diff --git a/boards/arm/v2m_musca_b1/doc/index.rst b/boards/arm/v2m_musca_b1/doc/index.rst index 0f0c261460a..0a7d41ac883 100644 --- a/boards/arm/v2m_musca_b1/doc/index.rst +++ b/boards/arm/v2m_musca_b1/doc/index.rst @@ -98,7 +98,7 @@ See the `V2M Musca B1 Website`_ for a complete list of V2M Musca board hardware features. The default configuration can be found in the defconfig file: -``boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig``. +:zephyr_file:`boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig`. Interrupt Controller ==================== diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml b/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml index 76ddda99468..72be434271d 100644 --- a/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml +++ b/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml @@ -1,4 +1,4 @@ -identifier: v2m_musca_b1 +identifier: v2m_musca_b1/musca_b1 name: ARM V2M MUSCA B1 type: mcu arch: arm diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig b/boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig index d6f7a3876d1..b04afd5915d 100644 --- a/boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig +++ b/boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_MUSCA_B1=y -CONFIG_SOC_V2M_MUSCA_B1=y CONFIG_RUNTIME_NMI=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_ARM_MPU=y diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_ns.dts b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.dts similarity index 100% rename from boards/arm/v2m_musca_b1/v2m_musca_b1_ns.dts rename to boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.dts diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.yaml b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.yaml new file mode 100644 index 00000000000..8f8700b0885 --- /dev/null +++ b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.yaml @@ -0,0 +1,11 @@ +identifier: v2m_musca_b1/musca_b1/ns +name: ARM V2M MUSCA B1 NonSecure +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 64 +flash: 1663 +vendor: arm diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns_defconfig b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns_defconfig new file mode 100644 index 00000000000..925071fbdf4 --- /dev/null +++ b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns_defconfig @@ -0,0 +1,7 @@ +# +# Copyright (c) 2019 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_ns.yaml b/boards/arm/v2m_musca_b1/v2m_musca_b1_ns.yaml deleted file mode 100644 index f116e1e52b9..00000000000 --- a/boards/arm/v2m_musca_b1/v2m_musca_b1_ns.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: v2m_musca_b1_ns -name: ARM V2M MUSCA B1 NonSecure -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 64 -flash: 1663 -vendor: arm diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_ns_defconfig b/boards/arm/v2m_musca_b1/v2m_musca_b1_ns_defconfig deleted file mode 100644 index b782032beff..00000000000 --- a/boards/arm/v2m_musca_b1/v2m_musca_b1_ns_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2019 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_MUSCA_B1=y -CONFIG_SOC_V2M_MUSCA_B1=y -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y -CONFIG_ARM_MPU=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/v2m_musca_s1/Kconfig.board b/boards/arm/v2m_musca_s1/Kconfig.board deleted file mode 100644 index 81261ba47bf..00000000000 --- a/boards/arm/v2m_musca_s1/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019-2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MUSCA_S1 - bool "ARM Cortex-M33 SMM on V2M-MUSCA-S1" - depends on SOC_SERIES_MUSCA_S1 diff --git a/boards/arm/v2m_musca_s1/Kconfig.defconfig b/boards/arm/v2m_musca_s1/Kconfig.defconfig index 532970a8b6b..f450de9f476 100644 --- a/boards/arm/v2m_musca_s1/Kconfig.defconfig +++ b/boards/arm/v2m_musca_s1/Kconfig.defconfig @@ -1,11 +1,7 @@ # Copyright (c) 2019-2020 Linaro Limited # SPDX-License-Identifier: Apache-2.0 -if BOARD_MUSCA_S1 - -config BOARD - default "musca_s1" if TRUSTED_EXECUTION_SECURE || !TRUSTED_EXECUTION_NONSECURE - default "musca_s1_ns" +if BOARD_V2M_MUSCA_S1 if SERIAL @@ -14,4 +10,4 @@ config UART_INTERRUPT_DRIVEN endif # SERIAL -endif +endif # BOARD_V2M_MUSCA_S1 diff --git a/boards/arm/v2m_musca_s1/Kconfig.v2m_musca_s1 b/boards/arm/v2m_musca_s1/Kconfig.v2m_musca_s1 new file mode 100644 index 00000000000..fd5ab86f341 --- /dev/null +++ b/boards/arm/v2m_musca_s1/Kconfig.v2m_musca_s1 @@ -0,0 +1,5 @@ +# Copyright (c) 2019-2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_V2M_MUSCA_S1 + select SOC_V2M_MUSCA_S1 diff --git a/boards/arm/v2m_musca_s1/board.yml b/boards/arm/v2m_musca_s1/board.yml new file mode 100644 index 00000000000..a7a3e18358d --- /dev/null +++ b/boards/arm/v2m_musca_s1/board.yml @@ -0,0 +1,7 @@ +board: + name: v2m_musca_s1 + vendor: arm + socs: + - name: musca_s1 + variants: + - name: 'ns' diff --git a/boards/arm/v2m_musca_s1/doc/index.rst b/boards/arm/v2m_musca_s1/doc/index.rst index 8a1c4b221bd..7072ef7e219 100644 --- a/boards/arm/v2m_musca_s1/doc/index.rst +++ b/boards/arm/v2m_musca_s1/doc/index.rst @@ -95,7 +95,7 @@ See the `V2M Musca-S1 Website`_ for a complete list of V2M Musca-S1 board hardware features. The default configuration can be found in the defconfig file: -``boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig``. +:zephyr_file:`boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig`. Interrupt Controller ==================== @@ -384,13 +384,13 @@ folder after TF-M built. Building the TF-M integration sample for Musca-S1 ------------------------------------------------- -The TF-M integration samples can be run using the ``v2m_musca_s1_ns`` +The TF-M integration samples can be run using the ``v2m_musca_s1/musca_s1/ns`` target. Please make sure all the requirements listed in the sample's description are met before building. .. zephyr-app-commands:: :zephyr-app: samples/tfm_integration/psa_crypto - :board: v2m_musca_s1_ns + :board: v2m_musca_s1/musca_s1/ns :goals: build To upload the build artifact to the board, first connect the Musca-S1 to your diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml b/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml index 194666cba50..7e99e0fc4eb 100644 --- a/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml +++ b/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml @@ -1,4 +1,4 @@ -identifier: v2m_musca_s1 +identifier: v2m_musca_s1/musca_s1 name: ARM V2M MUSCA-S1 type: mcu arch: arm diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig b/boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig index dd2b3491736..59601296cfa 100644 --- a/boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig +++ b/boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_MUSCA_S1=y -CONFIG_SOC_V2M_MUSCA_S1=y CONFIG_RUNTIME_NMI=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_ARM_MPU=y diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_ns.dts b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts similarity index 100% rename from boards/arm/v2m_musca_s1/v2m_musca_s1_ns.dts rename to boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.yaml b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.yaml new file mode 100644 index 00000000000..090f6996c58 --- /dev/null +++ b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.yaml @@ -0,0 +1,11 @@ +identifier: v2m_musca_s1/musca_s1/ns +name: ARM V2M MUSCA-S1 NonSecure +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 256 +flash: 511 +vendor: arm diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns_defconfig b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns_defconfig new file mode 100644 index 00000000000..d5c8f4180ac --- /dev/null +++ b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns_defconfig @@ -0,0 +1,7 @@ +# +# Copyright (c) 2019-2020 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_ns.yaml b/boards/arm/v2m_musca_s1/v2m_musca_s1_ns.yaml deleted file mode 100644 index 7494e2aff38..00000000000 --- a/boards/arm/v2m_musca_s1/v2m_musca_s1_ns.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: v2m_musca_s1_ns -name: ARM V2M MUSCA-S1 NonSecure -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 256 -flash: 511 -vendor: arm diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_ns_defconfig b/boards/arm/v2m_musca_s1/v2m_musca_s1_ns_defconfig deleted file mode 100644 index 146db80b6f8..00000000000 --- a/boards/arm/v2m_musca_s1/v2m_musca_s1_ns_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2019-2020 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_MUSCA_S1=y -CONFIG_SOC_V2M_MUSCA_S1=y -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y -CONFIG_ARM_MPU=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/verdin_imx8mp_m7/Kconfig.board b/boards/arm/verdin_imx8mp_m7/Kconfig.board deleted file mode 100644 index fb86601179c..00000000000 --- a/boards/arm/verdin_imx8mp_m7/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# VERDIN_IMX8MP_M7 board - -# Copyright (c) 2023 Toradex -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_VERDIN_IMX8MP_M7 - bool "Toradex iMX8M Plus M7" - depends on SOC_SERIES_IMX8ML_M7 - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm/verdin_imx8mp_m7/Kconfig.defconfig b/boards/arm/verdin_imx8mp_m7/Kconfig.defconfig deleted file mode 100644 index 3c3ab2db770..00000000000 --- a/boards/arm/verdin_imx8mp_m7/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# VERDIN_IMX8MP_M7 board defconfig - -# Copyright (c) 2023 Toradex -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_VERDIN_IMX8MP_M7 - -config BOARD - default "verdin_imx8mp_m7" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_VERDIN_IMX8MP_M7 diff --git a/boards/arm/verdin_imx8mp_m7/doc/index.rst b/boards/arm/verdin_imx8mp_m7/doc/index.rst deleted file mode 100644 index 455acb8c290..00000000000 --- a/boards/arm/verdin_imx8mp_m7/doc/index.rst +++ /dev/null @@ -1,304 +0,0 @@ -.. _verdin_imx8mp_m7: - -Toradex Verdin iMX8M Plus SoM -############################# - -Overview -******** - -The Verdin iMX8M Plus is a Computer on Module (CoM) developed by Toradex. It is based on the NXP® -i.MX 8M Plus family of processors (or System on Chips - SoCs). - -The Verdin iMX8M Plus family consists of: - -+-------------------------------------------------+-----------------------+ -| CoM | SoC | -+=================================================+=======================+ -| Verdin iMX8M Plus Quad 8GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | -+-------------------------------------------------+-----------------------+ -| Verdin iMX8M Plus Quad 4GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | -+-------------------------------------------------+-----------------------+ -| Verdin iMX8M Plus Quad 4GB IT | i.MX 8M Plus Quad | -+-------------------------------------------------+-----------------------+ -| Verdin iMX8M Plus Quad 2GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | -+-------------------------------------------------+-----------------------+ -| Verdin iMX8M Plus QuadLite 1GB IT | i.MX 8M Plus QuadLite | -+-------------------------------------------------+-----------------------+ - -Quoting NXP: - - The i.MX 8M Plus family focuses on machine learning and vision, advanced multimedia, and - industrial automation with high reliability. It is built to meet the needs of Smart Home, - Building, City and Industry 4.0 applications. - -The Verdin iMX8M Plus integrates a total of 4 Arm Cortex™-A53 CPUs, operating at 1.6 GHz, alongside -a single Arm Cortex™-M7F microcontroller operating at 800 MHz. - -.. figure:: verdin_imx8mp_front.jpg - :align: center - :alt: Toradex Verdin iMX8M Plus - - Toradex Verdin iMX8M Plus (Credit: Toradex) - -Regarding the Cortex-A53 cluster, it employs the ARMv8-A architecture as a mid-range and -energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1 -memory system. Moreover, the cluster incorporates a unified L2 cache that offers supplementary -functions. This cache is housed within a single APR region. Facilitating debugging processes, the -cores support both real-time trace through the ETM system and static debugging via JTAG. -Furthermore, the platform features support for real-time trace capabilities, achieved through ARM's -CoreSight ETM modules, and also enables cross-triggering by utilizing CTI and CTM modules. - -The Arm® Cortex®-M7 microcontroller is indicated for Real-time control, combining high-performance -with a minimal interrupt latency. It stands out for its compatibility with existing Cortex-M profile -processors. The microcontroller employs an efficient in-order super-scalar pipeline, allowing -dual-issued instructions such as load/load and load/store pairs, thanks to its multiple memory -interfaces. These interfaces encompass Tightly-Coupled Memory (TCM), Harvard caches, and an AXI -master interface. The Arm Cortex-M7 Platform boasts features like a 32 KB L1 Instruction Cache, 32 -KB L1 Data Cache, Floating Point Unit (FPU) with FPv5 architecture support, and an Internal Trace -(TRC) mechanism. Furthermore, the chip supports 160 IRQs, and integrates crucial Arm CoreSight -components including ETM and CTI, dedicated to facilitating debug and trace functions. - -Hardware -******** - -- SoC name: NXP® i.MX 8M Plus -- CPU Type: 4x Arm Cortex™-A53 (1.6 GHz) -- Microcontroller: 1x Arm Cortex™-M7F (800 MHz) - -- Memory: - - - RAM -> A53: 1GB, 2GB, 4GB or 8GB - - RAM -> M7: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) - - Flash -> A53: Up to 32GB eMMC - -- Connectivity: - - - USB 3.1: 1x Host / 1x OTG (Gen 1) - - USB 2.0: 1x Host / 1x OTG - - Ethernet Gigabit with TSN (+2nd RGMII) - - Wi-Fi Dual-band 802.11ac 2x2 MU-MIMO - - Bluetooth 5 - - 5x I2C - - 3x SPI - - 1 QSPI - - 4x UART - - Up to 92 GPIO - - 4x Analog Input - - 2x CAN (FlexCAN) - -- Multimedia: - - - Neural Processing Unit (NPU) - - Image Signal Processor (ISP) - - 2D and 3D acceleration - - HDMI, MIPI-DSI and MIPI-CSI interface - -For more information about the Verdin iMX8M Plus and the i.MX 8M Plus SoC refer to these links: - -- `i.MX 8M Plus Applications Processor page`_ -- `Verdin iMX8M Plus homepage`_ -- `Verdin iMX8M Plus developer page`_ -- `Verdin Development Board developer page`_ -- `Verdin iMX8M Plus Datasheet`_ -- `Verdin Development Board Datasheet`_ - -Supported Features -================== - -The Zephyr verdin_imx8mp_m7 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - -- :zephyr_file:`boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm_defconfig`, if you choose to use - the ITCM memory. - -- :zephyr_file:`boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr_defconfig`, if you choose to use - the DDR memory. - -It is recommended to disable peripherals used by the M7 core on the Linux host. - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -UART ----- - -Zephyr is configured to use the UART4 by default, which is connected to the FTDI USB converter on -most Toradex carrier boards. - -This is also the UART connected to WiFi/BT chip in modules that have the WiFi/BT chip. Therefore, if -UART4 is used, WiFI/BT will not work properly. - -If the WiFi/BT is needed, then another UART should be used for Zephyr (UART1 for example). You can -change the UART by changing the ``zephyr,console`` and ``zephyr,shell-uart`` in the -:zephyr_file:`boards/arm/verdin_imx8mp_m7_itcm.dts` or -:zephyr_file:`boards/arm/verdin_imx8mp_m7_ddr.dts` file. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART_1 | UART1 | General purpose UART | -+---------------+-----------------+---------------------------+ -| UART_4 | UART4 | Cortex-M4 debug UART | -+---------------+-----------------+---------------------------+ - -GPIO ----- - -All the GPIO banks available are enabled in the :zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. - -System Clock -============ - -The M7 Core is configured to run at a 800 MHz clock speed. - -Serial Port -=========== - -The i.MX8M Plus SoC has four UARTs. UART_4 is configured for the console and the remaining are not -used/tested. - -Programming and Debugging -************************* - -The Verdin iMX8M Plus board doesn't have QSPI flash for the M7, and it needs to be started by the -A53 core. The A53 core is responsible to load the M7 binary application into the RAM, put the M7 in -reset, set the M7 Program Counter and Stack Pointer, and get the M7 out of reset. The A53 can -perform these steps at bootloader level or after the Linux system has booted. - -The M7 can use up to 3 different RAMs (currently, only two configurations are supported: ITCM and -DDR). These are the memory mapping for A53 and M7: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the `i.MX 8M Plus Applications Processor Reference -Manual`_ (section 2.1 to 2.3) - -At compilation time you have to choose which RAM will be used. To facilitate this process, there are -two targets available: - -- ``verdin_imx8mp_m7_itcm``, which uses the ITCM configuration. -- ``verdin_imx8mp_m7_ddr``, which uses the DDR configuration. - - -Starting the Cortex-M7 via U-Boot -================================= - -Load and run Zephyr on M7 from A53 using u-boot by copying the compiled ``zephyr.bin`` to the first -FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot -execution at prompt. - -Load the M7 binary onto the desired memory and start its execution using: - -ITCM -==== - -Loading the binary from an EXT4 partition: - -.. code-block:: shell - - ext4load mmc 2:2 ${loadaddr} //zephyr.bin - cp.b ${loadaddr} 0x7e0000 - bootaux 0x7e0000 - -DDR -=== - -Loading the binary from an EXT4 partition: - -.. code-block:: shell - - ext4load mmc 2:2 ${loadaddr} //zephyr.bin - cp.b ${loadaddr} 0x80000000 - bootaux 0x80000000 - -Debugging -========= - -Toradex Verdin iMX8M Plus SoM can be debugged by connecting an external JLink JTAG debugger to the -X56 debug connector and to the PC, or simply connecting a USB-C to X66 on the Verdin Development -Board. Then, the application can be debugged using the usual way. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: verdin_imx8mp_m7_ddr - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.4.0-2300-g03905f7e55d2 *** - Hello World! verdin_imx8mp_m7_ddr - -References -========== - -- `How to Load Compiled Binaries into Cortex-M`_ -- `Cortex-M JTAG Debugging`_ -- `NXP website`_ - -.. _NXP website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK - -.. _i.MX 8M Plus Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MPRM - -.. _How to Load Compiled Binaries into Cortex-M: - https://developer.toradex.com/software/real-time/cortex-m/how-to-load-binaries - -.. _Cortex-M JTAG Debugging: - https://developer.toradex.com/software/real-time/cortex-m/cortexm-jtag-debugging/ - -.. _i.MX 8M Plus Applications Processor page: - https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-applications-processors/i-mx-8m-plus-arm-cortex-a53-machine-learning-vision-multimedia-and-industrial-iot:IMX8MPLUS - -.. _Verdin iMX8M Plus homepage: - https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus - -.. _Verdin iMX8M Plus developer page: - https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-imx8m-plus - -.. _Verdin Development Board developer page: - https://developer.toradex.com/hardware/verdin-som-family/carrier-boards/verdin-development-board/ - -.. _Verdin iMX8M Plus Datasheet: - https://docs.toradex.com/110977-verdin_imx8m_plus_v1.1_datasheet.pdf - -.. _Verdin Development Board Datasheet: - https://docs.toradex.com/109463-verdin_development_board_datasheet_v1.1.pdf diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.dts b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.dts deleted file mode 100644 index 861077246fd..00000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.dts +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2023 Toradex - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "verdin_imx8mp_m7-pinctrl.dtsi" -#include - -/ { - model = "Toradex Verdin iMX8M Plus M7"; - compatible = "nxp,mimx8mp_evk"; - - chosen { - /* DDR */ - zephyr,flash = &ddr_code; - zephyr,sram = &ddr_sys; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.yaml b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.yaml deleted file mode 100644 index fc64d8c3db8..00000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2023 Toradex -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: verdin_imx8mp_m7_ddr -name: Toradex Verdin iMX8M Plus (DDR) -type: mcu -arch: arm -ram: 2048 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - uart diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr_defconfig b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr_defconfig deleted file mode 100644 index 7c0d4073679..00000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2023 Toradex -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_VERDIN_IMX8MP_M7=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_DDR=y -CONFIG_PINCTRL=y diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.dts b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.dts deleted file mode 100644 index 5744928f8a7..00000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.dts +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2023 Toradex - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "verdin_imx8mp_m7-pinctrl.dtsi" -#include - -/ { - model = "Toradex Verdin iMX8M Plus M7"; - compatible = "nxp,mimx8mp_evk"; - - chosen { - /* TCM */ - zephyr,flash = &itcm; - zephyr,sram = &dtcm; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.yaml b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.yaml deleted file mode 100644 index 8db4c170c5d..00000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2023 Toradex -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: verdin_imx8mp_m7_itcm -name: Toradex Verdin iMX8M Plus (ITCM) -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - uart diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm_defconfig b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm_defconfig deleted file mode 100644 index 52c354abc1f..00000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2023 Toradex -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_VERDIN_IMX8MP_M7=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_ITCM=y -CONFIG_PINCTRL=y diff --git a/boards/arm/vmu_rt1170/CMakeLists.txt b/boards/arm/vmu_rt1170/CMakeLists.txt deleted file mode 100644 index 9e03e6cb024..00000000000 --- a/boards/arm/vmu_rt1170/CMakeLists.txt +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - set(RT1170_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1170") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1170 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(flexspi_nor_config.c) - zephyr_library_include_directories(${RT1170_BOARD_DIR}/xip) - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/vmu_rt1170/Kconfig.board b/boards/arm/vmu_rt1170/Kconfig.board deleted file mode 100644 index 53aa20f6800..00000000000 --- a/boards/arm/vmu_rt1170/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_VMU_RT1170 - bool "NXP VMU_RT1170" - depends on SOC_MIMXRT1176_CM7 - select SOC_PART_NUMBER_MIMXRT1176DVMAA diff --git a/boards/arm/vmu_rt1170/Kconfig.defconfig b/boards/arm/vmu_rt1170/Kconfig.defconfig deleted file mode 100644 index 1c27b74b23e..00000000000 --- a/boards/arm/vmu_rt1170/Kconfig.defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# VMU_RT1170 board - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_VMU_RT1170 - -config BOARD - default "vmu_rt1170" if BOARD_VMU_RT1170 - -choice CODE_LOCATION - default CODE_FLEXSPI if BOARD_VMU_RT1170 -endchoice - -if DISK_DRIVERS - -config IMX_USDHC_DAT3_PWR_TOGGLE - default y - -endif # DISK_DRIVERS - -if FLASH - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 -endchoice - -endif #FLASH - -if NETWORKING - -config NET_L2_ETHERNET - default y if CPU_CORTEX_M7 # No cache memory support is required for driver - -config ETH_MCUX_PHY_RESET - default n - -config ETH_MCUX_RMII_EXT_CLK - default y - -endif # NETWORKING - - -endif # BOARD_VMU_RT1170 diff --git a/boards/arm/vmu_rt1170/flexspi_nor_config.c b/boards/arm/vmu_rt1170/flexspi_nor_config.c deleted file mode 100644 index 21523fc29d0..00000000000 --- a/boards/arm/vmu_rt1170/flexspi_nor_config.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2019, MADMACHINE LIMITED - * - * refer to hal_nxp board file - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -/*! - * @brief ROM API init - * - * Get the bootloader api entry address. - */ -void ROM_API_Init(void); - -/*! - * @brief Initialize Serial NOR devices via FLEXSPI - * - * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs. - * - * @param instance storage the instance of FLEXSPI. - * @param config A pointer to the storage for the driver runtime state. - * - * @retval kStatus_Success Api was executed successfully. - * @retval kStatus_InvalidArgument A invalid argument is provided. - * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout - */ -status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, struct flexspi_nor_config_t *config); - - - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -/* Config used for booting */ - -const struct flexspi_nor_config_t Qspiflash_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = - kFlexSPIReadSampleClk_LoopbackInternally, - .csHoldTime = 1u, - .csSetupTime = 1u, - .sflashPadType = kSerialFlash_1Pad, - .serialClkFreq = kFlexSpiSerialClk_80MHz, - .sflashA1Size = 64u * 1024u * 1024u, - .lookupTable = { - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0x03, RADDR_SDR, - FLEXSPI_1PAD, 0x18), - FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, - 0x04, STOP, - FLEXSPI_1PAD, 0), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 64u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */ - -/* Config used for code execution */ -const struct flexspi_nor_config_t g_flash_fast_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, - .csHoldTime = 1, - .csSetupTime = 1, - .deviceModeCfgEnable = 1, - .deviceModeType = kDeviceConfigCmdType_Spi2Xpi, - .waitTimeCfgCommands = 1, - .deviceModeSeq = { - .seqNum = 1, - .seqId = 6, /* See Lookup table for more details */ - .reserved = 0, - }, - .deviceModeArg = 2, /* Enable OPI DDR mode */ - .controllerMiscOption = - (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) - | (1u << kFlexSpiMiscOffset_DdrModeEnable), - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_8Pads, - .serialClkFreq = kFlexSpiSerialClk_200MHz, - .sflashA1Size = 64ul * 1024u * 1024u, - .busyOffset = 0u, - .busyBitPolarity = 0u, - .lookupTable = { - /* Read */ - [0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, - 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11), - [0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, - 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04), - [0 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, - 0x04, STOP, FLEXSPI_1PAD, 0x00), - - /* Write enable SPI */ - [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0x06, STOP, FLEXSPI_1PAD, 0x00), - - /*Write Configuration Register 2 =01, Enable OPI DDR mode*/ - [4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0x72, CMD_SDR, FLEXSPI_1PAD, 0x00), - [4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00), - [4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01), - - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 64u * 1024u, - .isUniformBlockSize = false, - .ipcmdSerialClkFreq = 1, - .serialNorType = 2, - .reserve2[0] = 0x7008200, -}; - - -__ramfunc int imxrt_reclock_initialize(void) -{ - const uint32_t instance = 1; - - volatile struct flexspi_nor_config_t bootConfig; - - memcpy((struct flexspi_nor_config_t *)&bootConfig, &g_flash_fast_config, - sizeof(struct flexspi_nor_config_t)); - bootConfig.memConfig.tag = FLEXSPI_CFG_BLK_TAG; - - ROM_API_Init(); - - ROM_FLEXSPI_NorFlash_Init(instance, (struct flexspi_nor_config_t *)&bootConfig); - - return 0; -} - -SYS_INIT(imxrt_reclock_initialize, PRE_KERNEL_1, 0); diff --git a/boards/arm/w5500_evb_pico/Kconfig.board b/boards/arm/w5500_evb_pico/Kconfig.board deleted file mode 100644 index 9c863d899dc..00000000000 --- a/boards/arm/w5500_evb_pico/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Yonatan Schachter -# Copyright (c) 2023 Ian Wakely -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_W5500_EVB_PICO - bool "Wiznet W5500 Evaluation Board" - depends on SOC_RP2040 diff --git a/boards/arm/w5500_evb_pico/Kconfig.defconfig b/boards/arm/w5500_evb_pico/Kconfig.defconfig deleted file mode 100644 index 5e569b40cc9..00000000000 --- a/boards/arm/w5500_evb_pico/Kconfig.defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2021 Yonatan Schachter -# Copyright (c) 2023 Ian Wakely -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_W5500_EVB_PICO - -config BOARD - default "w5500_evb_pico" if BOARD_W5500_EVB_PICO - -config RP2_FLASH_W25Q080 - default y - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 125 - -endif #I2C_DW - -config USB_SELF_POWERED - default n - -endif # BOARD_W5500_EVB_PICO diff --git a/boards/arm/warp7_m4/Kconfig.board b/boards/arm/warp7_m4/Kconfig.board deleted file mode 100644 index 14ab7c1023f..00000000000 --- a/boards/arm/warp7_m4/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# WaRP7 iMX7S M4 board - -# Copyright (c) 2018, Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WARP7_M4 - bool "WaRP7 iMX7 Solo" - depends on SOC_SERIES_IMX7_M4 - select SOC_PART_NUMBER_MCIMX7S3DVK08SA diff --git a/boards/arm/warp7_m4/Kconfig.defconfig b/boards/arm/warp7_m4/Kconfig.defconfig deleted file mode 100644 index 6086acb474b..00000000000 --- a/boards/arm/warp7_m4/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# WaRP7 iMX7S M4 board - -# Copyright (c) 2018, Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WARP7_M4 - -config BOARD - default "warp7_m4" - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -config FXAS21002_DRDY_INT1 - default y - depends on FXAS21002_TRIGGER - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_WARP7_M4 diff --git a/boards/arm/warp7_m4/doc/index.rst b/boards/arm/warp7_m4/doc/index.rst deleted file mode 100644 index dc863e99d5a..00000000000 --- a/boards/arm/warp7_m4/doc/index.rst +++ /dev/null @@ -1,345 +0,0 @@ -.. _warp7_m4: - -WaRP7 - Next Generation IoT and Wearable Development Platform -############################################################# - -Overview -******** - -The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7 -core and Single Cortex M4 core. -Zephyr was ported to run on the M4 core. In a later release, it will also -communicate with the A7 core (running Linux) via RPmsg. - - -.. image:: warp7_m4.jpg - :align: center - :alt: WaRP7-iMX7S - -Hardware -******** - -The WaRP7 Platform is composed of a CPU and IO board. - -WaRP7 IO Board -============== - -- 6-axis Accelerometer Magnetometer: NXP FXOS8700CQ (I2C4 interface) -- 3-axis Gyroscope: NXP FXAS21002C (I2C4 interface) -- Altimeter: NXP MPL3115A2 (I2C4 interface) -- NXP NTAG NT3H1101 (I2C2 interface) -- Audio Codec: NXP SGTL5000 (I2C4 and SAI1 interfaces) -- S1 - Reset Button (POR_B signal) -- S2 - User Defined button (ENET1_RD1/GPIO7_IO1 signal) -- S3 - On/Off (MX7_ONOFF signal) -- Board to board connector (34 configurable pins) -- mikroBUS expansion connector -- 10-pin needle JTAG Connector -- Debug USB exposing two UARTs (UART1 for A7 and UART2 for M4) -- MIPI DSI 1 lane Connector -- LCD Touch Connector (I2C2 interface) -- Audio Jack: Mic and Stereo Headphone - -WaRP7 CPU Board -=============== - -- CPU i.MX7 Solo with a Single Cortex A7 (800MHz) core and - Single Cortex M4 (200MHz) core -- Memory - - - RAM -> A7: 4GB (Kingston 08EMCP04) - - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) - - Flash -> A7: 8GB eMMC (Kingston 08EMCP04) -- Multimedia - - - MIPI CSI 1 lane connector with 5MP OV5640 camera module (I2C2 interface) -- Connectivity - - - Board to board connector (34 configurable pins) - - Micro USB 2.0 OTG connector (USB_OTG1 interface) - - Murata Type 1DX Wi-Fi IEEE 802.11b/g/n and Bluetooth 4.1 plus EDR - (SD1, UART3 SAI2 interfaces) -- Li-ion/Li-polymer Battery Charger: NXP BC3770 (I2C1 interface) -- Power management integrated circuit (PMIC): NXP PF3000 (I2C1 interface) - - -For more information about the i.MX7 SoC and WaRP7, see these references: - -- `i.MX 7 Series Website`_ -- `i.MX 7 Solo Datasheet`_ -- `i.MX 7 Solo Reference Manual`_ -- `WaRP7 Site`_ -- `WaRP7 Quick Start Guide`_ -- `WaRP7 User Guide`_ -- `WaRP7 GitHub repository`_ - -Supported Features -================== - -The WaRP7 configuration supports the following hardware features on the -Cortex M4 Core: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger; | -| | | fxas21002 polling; | -| | | fxas21002 trigger; | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/warp7_m4/warp7_m4_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The WaRP7 board Board was tested with the following pinmux controller -configuration. - -+---------------+---------------------+--------------------------------+ -| Board Name | SoC Name | Usage | -+===============+=====================+================================+ -| FT_TX2 | UART2_TXD | UART Console | -+---------------+---------------------+--------------------------------+ -| FT_RX2 | UART2_RXD | UART Console | -+---------------+---------------------+--------------------------------+ -| MKBUS_TX | UART6_TXD | UART | -+---------------+---------------------+--------------------------------+ -| MKBUS_RX | UART6_RXD | UART | -+---------------+---------------------+--------------------------------+ -| S2 | ENET1_RD1/GPIO7_IO1 | SW0 | -+---------------+---------------------+--------------------------------+ -| I2C4_SDA | I2C4_SDA | I2C / FXOS8700 / FXAS21002 | -+---------------+---------------------+--------------------------------+ -| I2C4_SCL | I2C4_SCL | I2C / FXOS8700 / FXAS21002 | -+---------------+---------------------+--------------------------------+ -| SENSOR_INT_B | ENET1_RD0/GPIO7_IO0 | FXOS8700 INT1 / FXAS21002 INT1 | -+---------------+---------------------+--------------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 200 MHz clock speed. - -Serial Port -=========== - -The iMX7S SoC has seven UARTs. The number 2 is configured for the console and -the number 6 is used in the mikroBUS connector. - -Programming and Debugging -************************* - -The WaRP7 doesn't have QSPI flash for the M4 and it needs to be started by -the A7 core. The A7 core is responsible to load the M4 binary application into -the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and -get the M4 out of reset. -The A7 can perform these steps at bootloader level or after the Linux system -has booted. - -The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and -M4: - -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=======================+========================+=======================+======================+ -| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ - - -References -========== - -- `i.MX 7 Solo Reference Manual`_ from page 182 (section 2.1.2 and 2.1.3) -- `Toradex Wiki`_ - - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/warp7_m4/warp7_m4.dts`` with -"zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. The available -configurations are: - -.. code-block:: none - - "zephyr,flash" - - &ddr_code - - &tcml_code - - &ocram_code - - &ocram_s_code - - &ocram_pxp_code - - &ocram_epdc_code - - "zephyr,sram" - - &ddr_sys - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - - &ocram_pxp_sys - - &ocram_epdc_sys - - -Below you will find the instructions to load and run Zephyr on M4 from A7 using -u-boot. - -Connect both micro USB interfaces into the PC. In one USB interface you will -have 2 USB serial ports, the first one is the A7 console and the second is the -M4 console for Zephyr with both configured to work at 115200 8N1. -The other USB interface is used to power the CPU and IO boards and is connected -to the USB OTG interface of the i.MX7S. - -After powering up the platform stop the u-boot execution on the A7 core and -expose the eMMC as mass storage with the following command in the u-boot -prompt: ``ums 0 mmc 0``. Copy the compiled zephyr.bin to the first FAT -partition and remove the mounted device on the PC by issuing a "Ctrl+C" in the -u-boot prompt. -Set the u-boot environment variables and run the zephyr.bin from the -appropriated memory configured in the Zephyr compilation: - -.. code-block:: console - - setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' - # TCML - setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' - setenv bootm4tcml 'run m4tcml && run bootm4' - run bootm4tcml - # TCMU - setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' - setenv bootm4tcmu 'run m4tcmu && run bootm4' - run bootm4tcmu - # OCRAM - setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' - setenv bootm4ocram 'run m4ocram && run bootm4' - run bootm4ocram - # OCRAM_S - setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' - setenv bootm4ocrams 'run m4ocrams && run bootm4' - run bootm4ocrams - # DDR - setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' - setenv bootm4ddr 'run m4ddr && run bootm4' - run bootm4ddr - - -Debugging -========= - -Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. - -To run Zephyr Binary using J-Link, create the following script to get the -Program Counter and Stack Pointer from ``zephyr.bin``. - -get-pc-sp.sh: -.. code-block:: console - - #!/bin/sh - - firmware=$1 - - pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') - sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') - - echo pc=$pc - echo sp=$sp - - -Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` -.. code-block:: console - - pc=00900f01 - sp=00905020 - -Plug in the J-Link into the board and PC and run the J-Link command line tool: - -.. code-block:: console - - /usr/bin/JLinkExe -device Cortex-M4 -if JTAG \ - -speed 4000 -autoconnect 1 -jtagconf -1,-1 \ - -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript - -The following steps are necessary to run the zephyr.bin: - -1. Put the M4 core in reset -2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) -3. Set PC (Program Counter) -4. Set SP (Stack Pointer) -5. Get the M4 core out of reset - -Issue the following commands inside J-Link commander: - -.. code-block:: console - - w4 0x3039000C 0xAC - loadfile zephyr.bin,0x00900000 - w4 0x00180000 00900f01 - w4 0x00180004 00905020 - w4 0x3039000C 0xAA - -With these mechanisms, applications for the ``warp7_m4`` board -configuration can be built and debugged in the usual way (see -:ref:`build_an_application` and :ref:`application_run` for more details). - -References -========== - -- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ -- `J-Link iMX7D Instructions`_ - -.. _WaRP7 Site: - https://www.element14.com/warp7 - -.. _WaRP7 User Guide: - https://github.com/WaRP7/WaRP7-User-Guide/releases/download/v1.3/User_Guide_Manual_v1-3.pdf - -.. _WaRP7 Quick Start Guide: - https://www.nxp.com/docs/en/supporting-information/WARP7-LEAFLET-QSG.pdf - -.. _WaRP7 GitHub repository: - https://github.com/WaRP7 - -.. _i.MX 7 Series Website: - https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 - -.. _i.MX 7 Solo Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMX7SCEC.pdf - -.. _i.MX 7 Solo Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX7SRM - -.. _J-Link Tools: - https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack - -.. _NXP iMX7D Connect CortexM4.JLinkScript: - https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript - -.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: - https://www.nxp.com/docs/en/application-note/AN5317.pdf - -.. _J-Link iMX7D Instructions: - https://wiki.segger.com/IMX7D - -.. _Toradex Wiki: - https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/warp7_m4/warp7_m4.dts b/boards/arm/warp7_m4/warp7_m4.dts deleted file mode 100644 index 44f8153d749..00000000000 --- a/boards/arm/warp7_m4/warp7_m4.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2018, Diego Sueiro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "warp7_m4-pinctrl.dtsi" -#include - -/ { - model = "WaRP7 IMX7S board"; - compatible = "nxp,mcimx7d_m4"; - - aliases { - sw0 = &user_switch_1; - magn0 = &fxos8700; - accel0 = &fxos8700; - }; - - chosen { - zephyr,flash = &tcml_code; - zephyr,sram = &tcmu_sys; - zephyr,console = &uart2; - zephyr,shell-uart = &uart2; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_switch_1: user_sw_1 { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - label = "User SW1"; - zephyr,code = ; - }; - }; -}; - -&uart2 { - status = "okay"; - current-speed = <115200>; - modem-mode = <0>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&uart6 { - status = "okay"; - current-speed = <115200>; - modem-mode = <0>; - pinctrl-0 = <&uart6_default>; - pinctrl-names = "default"; -}; - -&gpio7 { - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_default>; - pinctrl-names = "default"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_default>; - pinctrl-names = "default"; -}; - -&i2c4 { - status = "okay"; - pinctrl-0 = <&i2c4_default>; - pinctrl-names = "default"; - - fxos8700: fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - int1-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - }; - - fxas21002@20 { - compatible = "nxp,fxas21002"; - reg = <0x20>; - int1-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - }; - -}; - -&mub { - status = "okay"; -}; diff --git a/boards/arm/warp7_m4/warp7_m4.yaml b/boards/arm/warp7_m4/warp7_m4.yaml deleted file mode 100644 index 67ed8dc2745..00000000000 --- a/boards/arm/warp7_m4/warp7_m4.yaml +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (c) 2018, Diego Sueiro -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: warp7_m4 -name: WaRP7 IMX7S -type: mcu -arch: arm -ram: 32 -flash: 32 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -supported: - - gpio - - i2c -vendor: nxp diff --git a/boards/arm/warp7_m4/warp7_m4_defconfig b/boards/arm/warp7_m4/warp7_m4_defconfig deleted file mode 100644 index 25281eb93ac..00000000000 --- a/boards/arm/warp7_m4/warp7_m4_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2018, Diego Sueiro -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX7_M4=y -CONFIG_SOC_MCIMX7_M4=y -CONFIG_BOARD_WARP7_M4=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/arm/waveshare_open103z/Kconfig.board b/boards/arm/waveshare_open103z/Kconfig.board deleted file mode 100644 index ea48f05c767..00000000000 --- a/boards/arm/waveshare_open103z/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Waveshare Open103Z board configuration - -# Copyright (c) 2020 Stefano Manni -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WAVESHARE_OPEN103Z - bool "Waveshare OPEN103Z Development Board" - depends on SOC_STM32F103XE diff --git a/boards/arm/waveshare_open103z/Kconfig.defconfig b/boards/arm/waveshare_open103z/Kconfig.defconfig deleted file mode 100644 index 4a2b56b826a..00000000000 --- a/boards/arm/waveshare_open103z/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Waveshare Open103Z board configuration - -# Copyright (c) 2020 Stefano Manni -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WAVESHARE_OPEN103Z - -config BOARD - default "waveshare_open103z" - -endif # BOARD_WAVESHARE_OPEN103Z diff --git a/boards/arm/we_ophelia1ev_nrf52805/Kconfig b/boards/arm/we_ophelia1ev_nrf52805/Kconfig deleted file mode 100644 index 5c6bc44014f..00000000000 --- a/boards/arm/we_ophelia1ev_nrf52805/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Ophelia-I EV nRF52805 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_WE_OPHELIA1EV_NRF52805 diff --git a/boards/arm/we_ophelia1ev_nrf52805/Kconfig.board b/boards/arm/we_ophelia1ev_nrf52805/Kconfig.board deleted file mode 100644 index c2709b066bb..00000000000 --- a/boards/arm/we_ophelia1ev_nrf52805/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WE_OPHELIA1EV_NRF52805 - bool "we_ophelia1ev_nrf52805" - depends on SOC_NRF52805_CAAA diff --git a/boards/arm/we_ophelia1ev_nrf52805/Kconfig.defconfig b/boards/arm/we_ophelia1ev_nrf52805/Kconfig.defconfig deleted file mode 100644 index b0a71cc3949..00000000000 --- a/boards/arm/we_ophelia1ev_nrf52805/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WE_OPHELIA1EV_NRF52805 - -config BOARD - default "we_ophelia1ev_nrf52805" - -config BT_CTLR - default BT - -endif diff --git a/boards/arm/we_ophelia1ev_nrf52805/doc/index.rst b/boards/arm/we_ophelia1ev_nrf52805/doc/index.rst deleted file mode 100644 index ea523c2fcf2..00000000000 --- a/boards/arm/we_ophelia1ev_nrf52805/doc/index.rst +++ /dev/null @@ -1,115 +0,0 @@ -.. _we_ophelia1ev_nrf52805: - -Ophelia-I EV NRF52805 -##################### - -Overview -******** - -The we_ophelia1ev_nrf52805 board is an evaluation board of the Ophelia-I radio module. -It provides support for the Nordic Semiconductor nRF52805 ARM CPU and -the following devices: - -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/we_ophelia1ev_nrf52805.jpg - :align: center - :alt: Ophelia-I EV - - Ophelia-I EV (Credit: Würth Elektronik) - -Hardware -******** - -The Ophelia-I uses the internal low frequency RC oscillator -and provides the so called smart antenna connection, that allows -to choose between the module's integrated PCB antenna and an external -antenna that can be connected to the available SMA connector. - -Supported Features -================== - -The we_ophelia1ev_nrf52805 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF52 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52dk_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -References -********** - -.. target-notes:: - -.. _Ophelia-I radio module website: https://www.we-online.com/katalog/de/OPHELIA-I -.. _nRF52805 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52805 diff --git a/boards/arm/we_proteus2ev_nrf52832/Kconfig.board b/boards/arm/we_proteus2ev_nrf52832/Kconfig.board deleted file mode 100644 index 98f30de1fee..00000000000 --- a/boards/arm/we_proteus2ev_nrf52832/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WE_PROTEUS2EV_NRF52832 - bool "we_proteus2ev_nrf52832" - depends on SOC_NRF52832_CIAA diff --git a/boards/arm/we_proteus2ev_nrf52832/Kconfig.defconfig b/boards/arm/we_proteus2ev_nrf52832/Kconfig.defconfig deleted file mode 100644 index 52437ae72db..00000000000 --- a/boards/arm/we_proteus2ev_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WE_PROTEUS2EV_NRF52832 - -config BOARD - default "we_proteus2ev_nrf52832" - -config BT_CTLR - default BT - -endif diff --git a/boards/arm/we_proteus2ev_nrf52832/doc/index.rst b/boards/arm/we_proteus2ev_nrf52832/doc/index.rst deleted file mode 100644 index 316d961c647..00000000000 --- a/boards/arm/we_proteus2ev_nrf52832/doc/index.rst +++ /dev/null @@ -1,162 +0,0 @@ -.. _we_proteus2ev_nrf52832: - -Würth Elektronik Proteus-II-EV -############################## - -Overview -******** - -The Proteus-II-EV hardware provides -support for the Proteus-II radio module that uses the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/we_proteus2ev_nrf52832.jpg - :align: center - :alt: Proteus-II EV - - Proteus-II-EV (Credit: Würth Elektronik) - -More information about the radio module can be found the Würth Elektronik web page https://www.we-online.com/katalog/de/PROTEUS-II . - - -Hardware -******** - -Proteus-II radio module provides only the internal oscillators. The frequency of the slow clock -is 32.768 kHz. The frequency of the main clock is 32 MHz. - -Supported Features -================== - -The we_proteus2ev_nrf52832 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features are not supported by the Zephyr kernel. - -Connections and IOs -=================== - -LED ---- - -* LED1 = P0.00 -* LED2 = P0.01 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.29 - - -Programming and Debugging -************************* - -Applications for the ``we_proteus2ev_nrf52832`` board configuration can be -built, flashed, and debugged in the usual way. See -:ref:`build_an_application` and :ref:`application_run` for more details on -building and running. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board Proteus-II-EV -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: we_proteus2ev_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the Proteus-II-EV -************************************************* - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.dts`. - -References -********** - -.. target-notes:: - -.. _Proteus-II radio module website: https://www.we-online.com/katalog/de/PROTEUS-II -.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/we_proteus3ev_nrf52840/Kconfig b/boards/arm/we_proteus3ev_nrf52840/Kconfig deleted file mode 100644 index 415c14238bf..00000000000 --- a/boards/arm/we_proteus3ev_nrf52840/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Proteus-III-EV board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WE_PROTEUS3EV_NRF52840 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_WE_PROTEUS3EV_NRF52840 diff --git a/boards/arm/we_proteus3ev_nrf52840/Kconfig.board b/boards/arm/we_proteus3ev_nrf52840/Kconfig.board deleted file mode 100644 index e59eb93e9c2..00000000000 --- a/boards/arm/we_proteus3ev_nrf52840/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WE_PROTEUS3EV_NRF52840 - bool "we_proteus3ev_nrf52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/we_proteus3ev_nrf52840/Kconfig.defconfig b/boards/arm/we_proteus3ev_nrf52840/Kconfig.defconfig deleted file mode 100644 index 8e1fa9443b4..00000000000 --- a/boards/arm/we_proteus3ev_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WE_PROTEUS3EV_NRF52840 - -config BOARD - default "we_proteus3ev_nrf52840" - -config BT_CTLR - default BT - -endif diff --git a/boards/arm/we_proteus3ev_nrf52840/doc/index.rst b/boards/arm/we_proteus3ev_nrf52840/doc/index.rst deleted file mode 100644 index 608f366716a..00000000000 --- a/boards/arm/we_proteus3ev_nrf52840/doc/index.rst +++ /dev/null @@ -1,164 +0,0 @@ -.. _we_proteus3ev_nrf52840: - -Würth Elektronik Proteus-III-EV -############################### - -Overview -******** - -The Proteus-III-EV (evaluation board) hardware provides support -for the Proteus-III radio module that uses the Nordic Semiconductor -nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/we_proteus3ev_nrf52840.jpg - :align: center - :alt: Proteus-III EV - - Proteus-III EV (Credit: Würth Elektronik) - -More information about the radio module can be found the Würth Elektronik -web page https://www.we-online.com/katalog/de/PROTEUS-III . - - -Hardware -******** - -Proteus-III radio module provides only the internal oscillators. The -frequency of the slow clock is 32.768 kHz. The frequency of the main -clock is 32 MHz. - -Supported Features -================== - -The we_proteus3ev_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features are not supported by the Zephyr kernel. - -Connections and IOs -=================== - -LED ---- - -* LED1 = P0.00 -* LED2 = P0.01 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.03 - -Programming and Debugging -************************* - -Applications for the ``we_proteus3ev_nrf52840`` board configuration can be -built, flashed, and debugged in the usual way. See -:ref:`build_an_application` and :ref:`application_run` for more details on -building and running. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board Proteus-III-EV -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: we_proteus3ev_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic -boards with a Segger IC. - -Testing the LEDs and buttons in the Proteus-III-EV -************************************************** - -There are 2 samples that allow you to test that the buttons (switches) and -LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly -on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.dts`. - -References -********** - -.. target-notes:: - -.. _Proteus-III radio module website: https://www.we-online.com/katalog/de/PROTEUS-III -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf diff --git a/boards/arm/weact_stm32g431_core/Kconfig.board b/boards/arm/weact_stm32g431_core/Kconfig.board deleted file mode 100644 index 9886fd64702..00000000000 --- a/boards/arm/weact_stm32g431_core/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2023 Andreas Sandberg -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_WEACT_STM32G431_CORE - bool "WeAct Studio STM32G431 Core Board" - depends on SOC_STM32G431XX diff --git a/boards/arm/weact_stm32g431_core/Kconfig.defconfig b/boards/arm/weact_stm32g431_core/Kconfig.defconfig deleted file mode 100644 index 25d65455013..00000000000 --- a/boards/arm/weact_stm32g431_core/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2023 Andreas Sandberg -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_WEACT_STM32G431_CORE - -config BOARD - default "weact_stm32g431_core" - -endif diff --git a/boards/arm/weact_stm32g431_core/doc/index.rst b/boards/arm/weact_stm32g431_core/doc/index.rst deleted file mode 100644 index 2d367ba2808..00000000000 --- a/boards/arm/weact_stm32g431_core/doc/index.rst +++ /dev/null @@ -1,147 +0,0 @@ -.. _weact_stm32g431_core: - -WeAct Studio STM32G431 Core Board -################################# - -The WeAct STM32G431 Core Board is a low-cost bare-bones STM32G431-based development -board. See the `STM32G431CB website`_ for more information about the MCU. More information -about the board, including schematics, is available from the `WeAct GitHub`_. - -Modifications USB-C Power Delivery -********************************** - -The board does not support USB-C PD in its standard configuration. To enable USB-C PD, CC1 -and CC2 need to be disconnected from their pull-down resistors and be connected to PB6 and -PB4 respectively. Dead battery support requires PA9 and PA10 to be routed to CC1 and -CC2. VBUS also needs to be connected to the MCU through a voltage divider. - -The pull-downs are disconnected by removing the zero-Ohm resistors on SB8 and SB9 next to -the USB-C connector. SB3, SB5, SB6, and SB7 then need to be closed to connect the CCx -lines to the MCU. The voltage divider is connected to PB2 by closing SB4. - -After these modifications have been made, PA9, PA10, PB2, PB4, and PB6 should be -considered reserved for USB-C and not available for other applications. - -.. warning:: - The internal USB DFU boot loader may not work correctly with machines that respect USB - PD signaling unless dead battery support has been enabled. A USB-C to USB-A adapter or - programming using the SWD port can be used as a workaround. - - -Supported Features -================== - -The Zephyr weact_stm32g431_core board configuration supports the following hardware -features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+------------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+------------+------------+-------------------------------------+ -| UCPD | on-chip | ucpd | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/weact_stm32g431_core/weact_stm32g431_core_defconfig`` - -Pin Mapping -=========== - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA3 -- UCPD1 CCx : PB6/PB4 (not connected by default) -- UCPD1 DBCCx : PA9/PA10 (not connected by default) -- BUTTON (User) : PC13 -- BUTTON (BOOT0) : PB8 -- LED0 : PC6 -- ADC (VBUS) : PB2 - -The ADC is disabled by default since the VBUS voltage divider is not connected in the -board's standard configuration. - - -Hardware Configuration ----------------------- -+---------------+---------+-----------------------------------------------+ -| Solder bridge | Default | Description | -+===============+=========+===============================================+ -| SB1/SB2 | Open | Route PC14/PC15 (LSE) to header | -+---------------+---------+-----------------------------------------------+ -| SB6/SB7 | Open | Connect PB4/PB6 (UCPD1_CCx) to USB-C CCx pins | -+---------------+---------+-----------------------------------------------+ -| SB3/SB5 | Open | Connect PA9/PA10 (UCPD1_DBCCx) to to PB6/PB4 | -+---------------+---------+-----------------------------------------------+ -| SB4 | Open | Connect PB2 to VBUS voltage divider | -+---------------+---------+-----------------------------------------------+ -| SB8/SB9 | Closed | Connect USB-CCx to pull-down resistors | -+---------------+---------+-----------------------------------------------+ -| SB10 | Open | VBUS protection diode bypass | -+---------------+---------+-----------------------------------------------+ - - -Clock Sources -------------- - -The board has two external oscillators. The frequency of the slow clock (LSE) is 32.768 -kHz. The frequency of the main clock (HSE) is 8 MHz. - -The default configuration sources the system clock from the PLL, which is derived from -HSE, and is set at 144 MHz. The 48 MHz clock used by the USB interface is derived from the -PLL instead of the internal 48 MHz oscillator. - -Programming and Debugging -************************* - -The MCU is normally programmed using the ROM bootloader or the exposed SWD port. - -Please note that some laptops may not detect the ROM bootloader correctly if the CCx -pull-downs have been disconnected by opening SB8 and SB9 unless dead battery support has -been enabled by closing SB3 and SB5. A USB-C to USB-A adapter can be used as a workaround -if this is a problem. - -Flashing an Application -======================= - -Connect a USB-C cable and the board should power ON. Force the board into DFU mode by -keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. - -The dfu-util runner is supported on this board and so a sample can be built and tested -easily. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: weact_stm32g431_core - :goals: build flash - -Debugging -========= - -The board can be debugged by installing the included 100 mil (0.1 inch) header, and -attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO pins on that header. - - -References -********** - -.. target-notes:: - -.. _WeAct GitHub: - https://github.com/WeActStudio/WeActStudio.STM32G431CoreBoard - -.. _STM32G431CB website: - https://www.st.com/en/microcontrollers-microprocessors/stm32g431cb.html - -.. _STM32F401x reference manual: - https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/wio_terminal/Kconfig.board b/boards/arm/wio_terminal/Kconfig.board deleted file mode 100644 index cec329c248f..00000000000 --- a/boards/arm/wio_terminal/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Joel Guittet -# Wio Terminal board configuration - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WIO_TERMINAL - bool "Wio Terminal" - depends on SOC_PART_NUMBER_SAMD51P19A diff --git a/boards/arm/wio_terminal/Kconfig.defconfig b/boards/arm/wio_terminal/Kconfig.defconfig deleted file mode 100644 index cca0d78a232..00000000000 --- a/boards/arm/wio_terminal/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 Joel Guittet -# Wio Terminal board configuration - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "wio_terminal" - depends on BOARD_WIO_TERMINAL - -config LV_COLOR_16_SWAP - default y if LVGL diff --git a/boards/arm/wio_terminal/doc/index.rst b/boards/arm/wio_terminal/doc/index.rst deleted file mode 100644 index 4b11a461323..00000000000 --- a/boards/arm/wio_terminal/doc/index.rst +++ /dev/null @@ -1,213 +0,0 @@ -.. _wio_terminal: - -Wio Terminal -############ - -Overview -******** - -The Wio Terminal is a small (72 mm x 57 mm x 12 mm) and powerful ARM board with -wireless connectivity (2.4G/5G dual-band Wi-Fi and BLE 5.0), LCD display, -USB C port, FPC connector, microSD card slot, Raspberry Pi compatible 40-pins -header and 2 Grove connectors. - -.. image:: img/wio_terminal.png - :width: 500px - :align: center - :alt: Seeed Studio Wio Terminal - -Hardware -******** - -- ATSAMD51P19 ARM Cortex-M4F processor at 120 MHz -- 512 KiB flash memory and 192 KiB of RAM -- 4 MiB external flash -- MicroSD card slot -- RTL8720DN 2.4G/5G Dual Bands Wireless and BLE5.0 Combo Module -- 2.4inch LCD display -- LIS3DH accelerometer -- Microphone 1.0V-10V -42dB -- Speaker ≥78dB @10cm 4000Hz -- Light Sensor 400-1050nm -- Infrared Emitter 940nm -- GPIO 40 pin (Raspberry Pi compatible) -- 2x Grove connectors -- 1x user LED -- 3x user buttons -- 5-way user button -- Power/Reset/Boot mode switch -- Native USB port - -Supported Features -================== - -The wio_terminal board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - Nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - Systick - * - WDT - - on-chip - - Watchdog - * - GPIO - - on-chip - - I/O ports - * - USART - - on-chip - - Serial port - * - I2C - - on-chip - - Inter-Integrated Circuit - * - SPI - - on-chip - - Serial Peripheral Interface port - * - TRNG - - on-chip - - True Random Number Generator - * - HWINFO - - on-chip - - Unique 128 bit serial number - * - RTC - - on-chip - - Real-Time Counter - * - USB - - on-chip - - USB device - * - PWM - - on-chip - - PWM - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/wio_terminal/wio_terminal_defconfig`. - -Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. -To use the RTC, set :kconfig:option:`CONFIG_CORTEX_M_SYSTICK=n` and set -:kconfig:option:`CONFIG_SYS_CLOCK_TICKS_PER_SEC` to no more than 32 kHZ divided -by 7, i.e. no more than 4500. - -Connections and IOs -=================== - -The `Wio Terminal Getting started guide`_ has detailed information about the -board including `pinouts`_ and its `schematics`_. - -System Clock -============ - -The SAMD51 MCU is configured to use the 32.768 kHz internal oscillator with the -on-chip PLL generating the 120 MHz system clock. - -Serial Port -=========== - -Zephyr console output is available using the USB connector, which is used to -make the console available on PC as USB CDC class. - -USB Device Port -=============== - -The SAMD51 MCU has a USB device port that can be used to communicate with a -host PC. See the :ref:`usb-samples` sample applications for more, such as the -:zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual serial port that echos -characters back to the host PC. - -Programming and Debugging -************************* - -The Wio Terminal ships with an UF2 bootloader that is BOSSA compatible. The -bootloader can be entered by quickly tapping the reset button twice. - -The UF2 file is generated when building the application, and it is possible to -use it to flash the target. Enter the bootloader by quickly sliding the power -button twice, and copy the UF2 file to the USB mass storage device. The device -reboots on the new firmware after the UF2 file has finished transferring. - -Flashing -======== - -#. Build the Zephyr kernel and the :code:`button` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: wio_terminal - :goals: build - :compact: - -#. Swipe the reset/power button down twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: wio_terminal - :goals: flash - :compact: - - You should see the blue (user) LED flashing whenever you press the third - (counting from the top left) user button at the top of the Wio Terminal. - -Debugging -========= - -In addition to the built-in bootloader, the Wio Terminal can be flashed and -debugged using an SWD probe such as the Segger J-Link. - -#. Solder cables to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, - :code:`GND`, and :code:`3V3` pins. See `Test with SWD`_ for more - information. - -#. Connect the board to the probe by connecting the :code:`SWCLK`, - :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the - Wio Terminal to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, - :code:`GND`, and :code:`VTref` pins on the `J-Link`_. - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: wio_terminal - :goals: flash - :flash-args: -r openocd - :compact: - -#. Start debugging: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: wio_terminal - :goals: debug - :compact: - -References -********** - -.. target-notes:: - -.. _Wio Terminal Getting started guide: - https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/ - -.. _pinouts: - https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#pinout-diagram - -.. _schematics: - https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#resources - -.. _Test with SWD: - https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#test-with-swd - -.. _J-Link: - https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/xiao_ble/Kconfig.board b/boards/arm/xiao_ble/Kconfig.board deleted file mode 100644 index ca317fd2451..00000000000 --- a/boards/arm/xiao_ble/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# XIAO BLE board configuration - -# Copyright (c) 2022 Marcin Niestroj -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_XIAO_BLE - bool "XIAO BLE" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/xiao_ble/Kconfig.defconfig b/boards/arm/xiao_ble/Kconfig.defconfig deleted file mode 100644 index e0e6dbc28e8..00000000000 --- a/boards/arm/xiao_ble/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# XIAO BLE board configuration - -# Copyright (c) 2022 Marcin Niestroj -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_XIAO_BLE - -config BOARD - default "xiao_ble" - -config BT_CTLR - default BT - -endif # BOARD_XIAO_BLE - -if USB_DEVICE_STACK - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y - -endif # USB_DEVICE_STACK diff --git a/boards/arm/xiao_ble/doc/index.rst b/boards/arm/xiao_ble/doc/index.rst deleted file mode 100644 index d4d4266311b..00000000000 --- a/boards/arm/xiao_ble/doc/index.rst +++ /dev/null @@ -1,219 +0,0 @@ -.. _xiao_ble: - -XIAO BLE (Sense) -################ - -Overview -******** - -The Seeed XIAO BLE (Sense) is a tiny (21 mm x 17.5 mm) Nordic Semiconductor -nRF52840 ARM Cortex-M4F development board with onboard LEDs, USB port, QSPI -flash, battery charger, and range of I/O broken out into 14 pins. - -.. figure:: img/xiao_ble.jpg - :align: center - :alt: XIAO BLE - -Hardware -******** - -- Nordic nRF52840 Cortex-M4F processor at 64MHz -- 2MB QSPI Flash -- RGB LED -- USB Type-C Connector, nRF52840 acting as USB device -- Battery charger BQ25101 -- Reset button -- Bluetooth antenna -- LSM6DS3TR-C 6D IMU (3D accelerometer and 3D gyroscope) (XIAO BLE Sense only) -- PDM microphone (XIAO BLE Sense only) - -Supported Features -================== - -The xiao_ble board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash, QSPI flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -The `XIAO BLE wiki`_ has detailed information about the board including -`pinouts`_ and the `schematic`_. - -LED ---- - -* LED1 (red) = P0.26 -* LED2 (green) = P0.30 -* LED3 (blue) = P0.06 - -Programming and Debugging -************************* - -The XIAO BLE ships with the `Adafruit nRF52 Bootloader`_ which supports flashing -using `UF2`_. Doing so allows easy flashing of new images, but does not support -debugging the device. For debugging please use `External Debugger`_. - -UF2 Flashing -============ - -To enter the bootloader, connect the USB port of the XIAO BLE to your host, and -double tap the reset botton to the left of the USB connector. A mass storage -device named `XIAO BLE` should appear on the host. Using the command line, or -your file manager copy the `zephyr/zephyr.uf2` file from your build to the base -of the `XIAO BLE` mass storage device. The XIAO BLE will automatically reset -and launch the newly flashed application. - -External Debugger -================= - -In order to support debugging the device, instead of using the bootloader, you -can use an :ref:`External Debug Probe `. To flash and debug Zephyr -applications you need to use `Seeeduino XIAO Expansion Board`_ or solder an SWD -header onto the back side of the board. - -For Segger J-Link debug probes, follow the instructions in the -:ref:`jlink-external-debug-probe` page to install and configure all the -necessary software. - -Flashing --------- - -Setup and connect a supported debug probe (JLink, instructions at :ref:`jlink-external-debug-probe` or -BlackMagic Probe). Then build and flash applications as -usual (see :ref:`build_an_application` and :ref:`application_run` for more -details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board XIAO BLE -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. Just add -``CONFIG_BOOT_DELAY=5000`` to the configuration, so that USB CDC ACM is -initialized before any text is printed, as below: - -.. tabs:: - - .. group-tab:: XIAO BLE - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_ble - :goals: build flash - :gen-args: -DCONFIG_BOOT_DELAY=5000 - - .. group-tab:: XIAO BLE Sense - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_ble_sense - :goals: build flash - :gen-args: -DCONFIG_BOOT_DELAY=5000 - -Debugging ---------- - -Refer to the :ref:`jlink-external-debug-probe` page to learn about debugging -boards with a Segger IC. - -Debugging using a BlackMagic Probe is also supported. - -Testing the LEDs in the XIAO BLE (Sense) -**************************************** - -There is a sample that allows to test that LEDs on the board are working -properly with Zephyr: - -.. tabs:: - - .. group-tab:: XIAO BLE - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: xiao_ble - :goals: build flash - - .. group-tab:: XIAO BLE Sense - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: xiao_ble_sense - :goals: build flash - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The LED definitions can be found in -:zephyr_file:`boards/arm/xiao_ble/xiao_ble_common.dtsi`. - -Testing shell over USB in the XIAO BLE (Sense) -********************************************** - -There is a sample that allows to test shell interface over USB CDC ACM interface -with Zephyr: - -.. tabs:: - - .. group-tab:: XIAO BLE - - .. zephyr-app-commands:: - :zephyr-app: samples/subsys/shell/shell_module - :board: xiao_ble - :goals: build flash - - .. group-tab:: XIAO BLE Sense - - .. zephyr-app-commands:: - :zephyr-app: samples/subsys/shell/shell_module - :board: xiao_ble_sense - :goals: build flash - -References -********** - -.. target-notes:: - -.. _XIAO BLE wiki: https://wiki.seeedstudio.com/XIAO_BLE/ -.. _pinouts: https://wiki.seeedstudio.com/XIAO_BLE/#hardware-overview -.. _schematic: https://wiki.seeedstudio.com/XIAO_BLE/#resources -.. _Seeeduino XIAO Expansion Board: https://wiki.seeedstudio.com/Seeeduino-XIAO-Expansion-Board/ -.. _Adafruit nRF52 Bootloader: https://github.com/adafruit/Adafruit_nRF52_Bootloader -.. _UF2: https://github.com/microsoft/uf2 diff --git a/boards/arm/xiao_ble/pre_dt_board.cmake b/boards/arm/xiao_ble/pre_dt_board.cmake deleted file mode 100644 index 3369c21d3af..00000000000 --- a/boards/arm/xiao_ble/pre_dt_board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - power@40000000 & clock@40000000 & bprot@40000000 -# - acl@4001e000 & flash-controller@4001e000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/xiao_ble/xiao_ble_defconfig b/boards/arm/xiao_ble/xiao_ble_defconfig deleted file mode 100644 index 59471d3d22a..00000000000 --- a/boards/arm/xiao_ble/xiao_ble_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_XIAO_BLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y - -# Logger cannot use itself to log -CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - -# enable USB -CONFIG_USB_DEVICE_STACK=y - -# Build UF2 by default, supported by the Adafruit nRF52 Bootloader -CONFIG_BUILD_OUTPUT_UF2=y -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/xiao_ble/xiao_ble_sense.yaml b/boards/arm/xiao_ble/xiao_ble_sense.yaml deleted file mode 100644 index 7d11907651a..00000000000 --- a/boards/arm/xiao_ble/xiao_ble_sense.yaml +++ /dev/null @@ -1,24 +0,0 @@ -identifier: xiao_ble_sense -name: XIAO BLE Sense -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - ble - - counter - - gpio - - i2c - - i2s - - pwm - - spi - - usb_cdc - - usb_device - - watchdog - - netif:openthread -vendor: seeed diff --git a/boards/arm/xiao_ble/xiao_ble_sense_defconfig b/boards/arm/xiao_ble/xiao_ble_sense_defconfig deleted file mode 100644 index 73878352edd..00000000000 --- a/boards/arm/xiao_ble/xiao_ble_sense_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_XIAO_BLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y - -# Logger cannot use itself to log -CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - -# enable USB -CONFIG_USB_DEVICE_STACK=y - -# Build UF2 by default, supported by the Adafruit nRF52 Bootloader -CONFIG_BUILD_OUTPUT_UF2=y -CONFIG_USE_DT_CODE_PARTITION=y - -# required to enable LSM6DS3TR-C power -CONFIG_REGULATOR=y diff --git a/boards/arm/xmc45_relax_kit/Kconfig.board b/boards/arm/xmc45_relax_kit/Kconfig.board deleted file mode 100644 index 6be8d366859..00000000000 --- a/boards/arm/xmc45_relax_kit/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -config BOARD_XMC45_RELAX_KIT - bool "Infineon Relax Kit" - depends on SOC_SERIES_XMC_4XXX - select SOC_PART_NUMBER_F100X1024 diff --git a/boards/arm/xmc45_relax_kit/Kconfig.defconfig b/boards/arm/xmc45_relax_kit/Kconfig.defconfig deleted file mode 100644 index 0296bc64ff7..00000000000 --- a/boards/arm/xmc45_relax_kit/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -if BOARD_XMC45_RELAX_KIT - -config BOARD - default "xmc45_relax_kit" - -if NETWORKING - -config NET_L2_ETHERNET - default y -config MDIO - default y -config TEST_RANDOM_GENERATOR - default y - -endif # NETWORKING - -endif # BOARD_XMC45_RELAX_KIT diff --git a/boards/arm/xmc47_relax_kit/Kconfig.board b/boards/arm/xmc47_relax_kit/Kconfig.board deleted file mode 100644 index 7c60e2a03e8..00000000000 --- a/boards/arm/xmc47_relax_kit/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Schlumberger - -config BOARD_XMC47_RELAX_KIT - bool "Infineon XMC4700 Relax Kit" - depends on SOC_SERIES_XMC_4XXX - select SOC_PART_NUMBER_F144X2048 diff --git a/boards/arm/xmc47_relax_kit/Kconfig.defconfig b/boards/arm/xmc47_relax_kit/Kconfig.defconfig deleted file mode 100644 index 98978ffd540..00000000000 --- a/boards/arm/xmc47_relax_kit/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Schlumberger - -if BOARD_XMC47_RELAX_KIT - -config BOARD - default "xmc47_relax_kit" - -if NETWORKING - -config NET_L2_ETHERNET - default y -config MDIO - default y -config TEST_RANDOM_GENERATOR - default y - -endif # NETWORKING - -endif diff --git a/boards/arm/xmc47_relax_kit/xmc47_relax_kit_defconfig b/boards/arm/xmc47_relax_kit/xmc47_relax_kit_defconfig deleted file mode 100644 index 85522ce92bd..00000000000 --- a/boards/arm/xmc47_relax_kit/xmc47_relax_kit_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Schlumberger - -CONFIG_BOARD_XMC47_RELAX_KIT=y -CONFIG_SOC_SERIES_XMC_4XXX=y -CONFIG_SOC_XMC4700=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/zybo/Kconfig.board b/boards/arm/zybo/Kconfig.board deleted file mode 100644 index 30dfd50f3da..00000000000 --- a/boards/arm/zybo/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Digilent Zybo board configuration - -# Copyright (c) 2022 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ZYBO - bool "Digilent Zybo" - depends on SOC_XILINX_XC7Z010 diff --git a/boards/arm/zybo/Kconfig.defconfig b/boards/arm/zybo/Kconfig.defconfig deleted file mode 100644 index ea8ddb6a62a..00000000000 --- a/boards/arm/zybo/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Digilent Zybo board - -# Copyright (c) 2022 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ZYBO - -config BOARD - default "zybo" - -endif # BOARD_ZYBO diff --git a/boards/arm/zybo/doc/index.rst b/boards/arm/zybo/doc/index.rst deleted file mode 100644 index 44810e666ce..00000000000 --- a/boards/arm/zybo/doc/index.rst +++ /dev/null @@ -1,147 +0,0 @@ -.. _zybo: - -Digilent Zybo -############# - -Overview -******** - -The `Digilent Zybo`_ (ZYnq BOard) is a feature-rich, ready-to-use embedded software and digital -circuit development board. It is built around the Xilinx Zynq-7000 family, which is based on the -Xilinx All Programmable System-on-Chip (AP SoC) architecture. This architecture tightly integrates a -dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. - -.. figure:: zybo-0.jpg - :align: center - :alt: Digilent Zybo - - Digilent (Credit: Digilent) - -Hardware -******** - -Supported Features -================== - -The zybo board configuration supports the following hardware features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| GICv1 | on-chip | ARM generic interrupt controller v1 | -+------------+------------+-------------------------------------+ -| ARCH TIMER | on-chip | ARM architected timer | -+------------+------------+-------------------------------------+ -| PINCTRL | on-chip | pinctrl | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/zybo/zybo_defconfig``. - -Other hardware features are not currently supported by the port. - -Programming and Debugging -************************* - -The Zynq-7000 series SoC needs to be initialized prior to running a Zephyr application. This can be -achieved in a number of ways (e.g. using the Xilinx First Stage Boot Loader (FSBL), the Xilinx -Vivado generated ``ps_init.tcl`` JTAG script, Das U-Boot Secondary Program Loader (SPL), ...). - -The instructions here use the U-Boot SPL. For further details and instructions for using Das U-Boot -with Xilinx Zynq-7000 series SoCs, see the following documentation: - -- `Das U-Boot Website`_ -- `Using Distro Boot With Xilinx U-Boot`_ - -Building Das U-Boot -=================== - -Clone and build Das U-Boot for the Digilent Zybo: - -.. code-block:: console - - git clone -b v2022.04 https://source.denx.de/u-boot/u-boot.git - cd u-boot - make distclean - make xilinx_zynq_virt_defconfig - export PATH=/path/to/zephyr-sdk/arm-zephyr-eabi/bin/:$PATH - export CROSS_COMPILE=arm-zephyr-eabi- - export DEVICE_TREE="zynq-zybo" - make - -Flashing -======== - -Here is an example for running the :ref:`hello_world` application via JTAG. - -Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press -the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot -SPL via JTAG. - -Next, upload and run the Zephyr application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: zybo - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx *** - Hello World! zybo - -Another option is to load and run the :ref:`hello_world` application via U-Boot. Copy -``u-boot/spl/boot.bin``, ``u-boot/u-boot.img``, and ``zephyr/zephyr.bin`` to a FAT32 formatted -microSD card, insert the card in the ``SD MICRO`` slot on the Zybo board, ensure the board is -configured for ``SD`` boot, and turn on the board. - -Once U-boot is done initializing, load an run the Zephyr application: - -.. code-block:: console - - Zynq> fatload mmc 0 0x0 zephyr.bin - 817120 bytes read in 56 ms (13.9 MiB/s) - Zynq> go 0x0 - ## Starting application at 0x00000000 ... - *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx *** - Hello World! zybo - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press -the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot -SPL via JTAG. - -Next, upload and debug the Zephyr application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: zybo - :goals: debug - -Step through the application in your debugger, and you should see the following message in the -terminal: - -.. code-block:: console - - *** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *** - Hello World! zybo - -.. _Digilent Zybo: - https://digilent.com/reference/programmable-logic/zybo/start - -.. _Das U-Boot Website: - https://www.denx.de/wiki/U-Boot - -.. _Using Distro Boot With Xilinx U-Boot: - https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/749142017/Using+Distro+Boot+With+Xilinx+U-Boot diff --git a/boards/arm/zybo/zybo_defconfig b/boards/arm/zybo/zybo_defconfig deleted file mode 100644 index ad4d88eaee3..00000000000 --- a/boards/arm/zybo/zybo_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_XILINX_XC7ZXXX=y -CONFIG_SOC_XILINX_XC7Z010=y -CONFIG_BOARD_ZYBO=y - -# The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) -CONFIG_ARM_ARCH_TIMER=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=325000000 - -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/bcm958402m2_a72/Kconfig.board b/boards/arm64/bcm958402m2_a72/Kconfig.board deleted file mode 100644 index 655d894e4d5..00000000000 --- a/boards/arm64/bcm958402m2_a72/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BCM958402M2_A72 - bool "Broadcom Viper BCM958402M2_A72" - depends on SOC_BCM58402_A72 diff --git a/boards/arm64/bcm958402m2_a72/Kconfig.defconfig b/boards/arm64/bcm958402m2_a72/Kconfig.defconfig deleted file mode 100644 index 8f7714ab9f3..00000000000 --- a/boards/arm64/bcm958402m2_a72/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "bcm958402m2_a72" - depends on BOARD_BCM958402M2_A72 diff --git a/boards/arm64/bcm958402m2_a72/bcm958402m2_a72.yaml b/boards/arm64/bcm958402m2_a72/bcm958402m2_a72.yaml deleted file mode 100644 index d59dd34439c..00000000000 --- a/boards/arm64/bcm958402m2_a72/bcm958402m2_a72.yaml +++ /dev/null @@ -1,8 +0,0 @@ -identifier: bcm958402m2_a72 -name: Broadcom BCM958402M2_A72 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -vendor: brcm diff --git a/boards/arm64/bcm958402m2_a72/bcm958402m2_a72_defconfig b/boards/arm64/bcm958402m2_a72/bcm958402m2_a72_defconfig deleted file mode 100644 index 6f758f867d9..00000000000 --- a/boards/arm64/bcm958402m2_a72/bcm958402m2_a72_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_VIPER=y -CONFIG_SOC_BCM58402_A72=y -CONFIG_BOARD_BCM958402M2_A72=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0x0 - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable PCIe EP -CONFIG_PCIE_ENDPOINT=y -CONFIG_PCIE_EP_IPROC=y -CONFIG_PCIE_EP_IPROC_V2=y - -# Enable DMA -CONFIG_DMA=y -CONFIG_DMA_64BIT=y diff --git a/boards/arm64/bcm958402m2_a72/doc/index.rst b/boards/arm64/bcm958402m2_a72/doc/index.rst deleted file mode 100644 index 8c8737f7e52..00000000000 --- a/boards/arm64/bcm958402m2_a72/doc/index.rst +++ /dev/null @@ -1,51 +0,0 @@ -.. _bcm958402m2_a72: - -Broadcom BCM958402M2 (Cortex-A72) -################################# - -Overview -******** -The Broadcom bcm958402m2_a72 board utilizes the Viper BCM58402_A72 SoC -to provide support for PCIe offload engine functionality. - -Hardware -******** -The bcm958402m2_a72 is a PCIe card with the following physical features: - -* PCIe Gen4 interface -* RS232 UART (optionally populated) -* JTAG (optionally populated) - -Supported Features -================== -The Broadcom bcm958402m2_a72 board configuration supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| GIC-500 | on-chip | GICv3 interrupt controller | -+-----------+------------+--------------------------------------+ -| UART | on-chip | NS16550 compatible serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm/bcm958402m2_a72/bcm958402m2_a72_defconfig`` - -Programming and Debugging -************************* - -Flashing -======== - -The flash on board is not supported by Zephyr at this time. -Board is booted over PCIe interface. - -Debugging -========= -The bcm958402m2_a72 board includes pads for soldering a JTAG connector. -Zephyr applications running on the Cortex-A72 core can also be tested -by observing UART console output. diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.board b/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.board deleted file mode 100644 index dbc0bf5ac7d..00000000000 --- a/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FVP_BASE_REVC_2XAEMV8A - bool "FVP Base RevC AEMv8A simulation board" - depends on SOC_FVP_BASE_REVC_2XAEMV8A diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.defconfig b/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.defconfig deleted file mode 100644 index bfbb54fb049..00000000000 --- a/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FVP_BASE_REVC_2XAEMV8A - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "fvp_base_revc_2xaemv8a" - -endif # BOARD_FVP_BASE_REVC_2XAEMV8A diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns.yaml b/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns.yaml deleted file mode 100644 index b6e39f0dab3..00000000000 --- a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -identifier: fvp_base_revc_2xaemv8a_smp_ns -name: FVP Emulation FVP_Base_RevC-2xAEMvA (SMP) -arch: arm64 -type: sim -toolchain: - - zephyr - - cross-compile -ram: 2048 -flash: 64 -vendor: arm diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns_defconfig b/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns_defconfig deleted file mode 100644 index 235444bcab5..00000000000 --- a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns_defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_FVP_AEMV8A=y -CONFIG_SOC_FVP_BASE_REVC_2XAEMV8A=y -CONFIG_BOARD_FVP_BASE_REVC_2XAEMV8A=y - -CONFIG_THREAD_STACK_INFO=y - -# Enable Timer and Sys clock -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_ARM_ARCH_TIMER=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable TFA -CONFIG_ARMV8_A_NS=y -CONFIG_BUILD_WITH_TFA=y - -# Enable SMP -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=4 -CONFIG_CACHE_MANAGEMENT=y -CONFIG_TIMEOUT_64BIT=y -CONFIG_ARM64_SET_VMPIDR_EL2=y -CONFIG_MAX_THREAD_BYTES=3 - -# PSCI is supported -CONFIG_PM_CPU_OPS=y diff --git a/boards/arm64/fvp_baser_aemv8r/Kconfig.board b/boards/arm64/fvp_baser_aemv8r/Kconfig.board deleted file mode 100644 index 3b0c7ba7081..00000000000 --- a/boards/arm64/fvp_baser_aemv8r/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FVP_BASER_AEMV8R - bool "FVP BaseR AEMv8R simulation board" - depends on SOC_FVP_AEMV8R_AARCH64 diff --git a/boards/arm64/fvp_baser_aemv8r/Kconfig.defconfig b/boards/arm64/fvp_baser_aemv8r/Kconfig.defconfig deleted file mode 100644 index 89a9b373803..00000000000 --- a/boards/arm64/fvp_baser_aemv8r/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FVP_BASER_AEMV8R - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "fvp_baser_aemv8r" - -endif # BOARD_FVP_BASER_AEMV8R diff --git a/boards/arm64/fvp_baser_aemv8r/board.cmake b/boards/arm64/fvp_baser_aemv8r/board.cmake deleted file mode 100644 index 410431bdcbf..00000000000 --- a/boards/arm64/fvp_baser_aemv8r/board.cmake +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS armfvp) -set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R) -set(ARMFVP_MIN_VERSION 11.16.16) - -set(ARMFVP_FLAGS - -C cluster0.has_aarch64=1 - -C cluster0.VMSA_supported=0 - -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS} - -C cluster0.gicv3.cpuintf-mmap-access-level=2 - -C cluster0.gicv3.SRE-enable-action-on-mmap=2 - -C cluster0.gicv3.SRE-EL2-enable-RAO=1 - -C cluster0.gicv3.extended-interrupt-range-support=1 - -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1 - -C gic_distributor.has-two-security-states=0 - -C bp.refcounter.non_arch_start_at_default=1 - # UART0 config - -C bp.pl011_uart0.out_file=- - -C bp.pl011_uart0.unbuffered_output=1 - -C bp.terminal_0.start_telnet=0 - # UART1 config - -C bp.pl011_uart1.out_file=- - -C bp.pl011_uart1.unbuffered_output=1 - -C bp.terminal_1.start_telnet=0 - # UART2 config - -C bp.pl011_uart2.out_file=- - -C bp.pl011_uart2.unbuffered_output=1 - -C bp.terminal_2.start_telnet=0 - # UART3 config - -C bp.pl011_uart3.out_file=- - -C bp.pl011_uart3.unbuffered_output=1 - -C bp.terminal_3.start_telnet=0 - - -C bp.vis.disable_visualisation=1 - -C bp.vis.rate_limit-enable=0 - -C cache_state_modelled=1 - ) diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.yaml b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.yaml deleted file mode 100644 index 840fa70e5c9..00000000000 --- a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -identifier: fvp_baser_aemv8r -name: FVP Emulation FVP_BaseR_AEMv8R -arch: arm64 -type: sim -toolchain: - - zephyr - - cross-compile -ram: 2048 -flash: 64 -testing: - timeout_multiplier: 8 -vendor: arm diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_defconfig b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_defconfig deleted file mode 100644 index 7876a745327..00000000000 --- a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_FVP_AEMV8R=y -CONFIG_SOC_FVP_AEMV8R_AARCH64=y -CONFIG_BOARD_FVP_BASER_AEMV8R=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -CONFIG_THREAD_STACK_INFO=y - -# Enable Timer and Sys clock -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_ARM_ARCH_TIMER=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.dts b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.dts deleted file mode 100644 index 13c39522ca1..00000000000 --- a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.dts +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "fvp_baser_aemv8r.dts" diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.yaml b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.yaml deleted file mode 100644 index ed63f35d101..00000000000 --- a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -identifier: fvp_baser_aemv8r_smp -name: FVP Emulation FVP_BaseR_AEMv8R (SMP) -arch: arm64 -type: sim -toolchain: - - zephyr - - cross-compile -ram: 2048 -flash: 64 -supported: - - smp -testing: - timeout_multiplier: 20 -vendor: arm diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp_defconfig b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp_defconfig deleted file mode 100644 index 9a96f0b3d4f..00000000000 --- a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_FVP_AEMV8R=y -CONFIG_SOC_FVP_AEMV8R_AARCH64=y -CONFIG_BOARD_FVP_BASER_AEMV8R=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -CONFIG_THREAD_STACK_INFO=y - -# Enable Timer and Sys clock -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_ARM_ARCH_TIMER=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable simulate cpu power management -CONFIG_SOC_FVP_AEMV8R_SIMULATE_CPU_PM=y -CONFIG_PM_CPU_OPS=y -CONFIG_PM_CPU_OPS_PSCI=n -CONFIG_ARM64_SET_VMPIDR_EL2=y - -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=4 - -CONFIG_MAX_THREAD_BYTES=3 diff --git a/boards/arm64/index.rst b/boards/arm64/index.rst deleted file mode 100644 index e7dbb2d6842..00000000000 --- a/boards/arm64/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-arm64: - -ARM64 Boards -############ - -.. toctree:: - :maxdepth: 1 - :glob: - - **/index diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.board b/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.board deleted file mode 100644 index a23f8c5d1e0..00000000000 --- a/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK - bool "Intel SoC FPGA Development Kit (Agilex5)" - select HAS_COVERAGE_SUPPORT - depends on SOC_AGILEX5 diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.defconfig b/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.defconfig deleted file mode 100644 index 5b832b29c00..00000000000 --- a/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "intel_socfpga_agilex5_socdk" - depends on BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK - -config MAX_THREAD_BYTES - default 5 diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/doc/index.rst b/boards/arm64/intel_socfpga_agilex5_socdk/doc/index.rst deleted file mode 100644 index 537b1628cde..00000000000 --- a/boards/arm64/intel_socfpga_agilex5_socdk/doc/index.rst +++ /dev/null @@ -1,80 +0,0 @@ -.. _intel_socfpga_agilex5_socdk: - -Intel® Agilex™ 5 SoC FPGA Development Kit -######################################### - -Overview -******** - -The Intel® Agilex™ 5 SoC FPGA Development Kit offers a complete design -environment that includes both hardware and software for developing -Intel® Agilex™ 5 E-Series based FPGA designs. This kit is recommended for -developing custom ARM* processor-based SoC designs and ideal for intelligent -applications at the edge, embedded and more. - -Hardware -******** - -The Intel® Agilex™ 5 Development Kit supports the following physical features: - -- Intel® Agilex™ 5 E-Series FPGA, 50K-656K LEs integrated with - multi-core ARM processors of Dual-core A55 and Dual-core A76 -- On-board 8 GB DDR5 memory -- On-board JTAG Intel FPGA Download Cable II -- QSPI flash daughtercard - -Supported Features -================== -The Intel® Agilex™ 5 SoC Development Kit configuration supports the following -hardware features: - -+-----------+------------+---------------------------------------------+ -| Interface | Controller | Hardware Subsystem Vendor | -+===========+============+=============================================+ -| GIC-600 | on-chip | ARM GICv3 interrupt controller | -+-----------+------------+---------------------------------------------+ -| UART | on-chip | Synopsys Designware,NS16550 compatible | -+-----------+------------+---------------------------------------------+ -| ARM TIMER | on-chip | ARM system timer | -+-----------+------------+---------------------------------------------+ -| Reset | on-chip | Intel Corporation, SoCFPGA Reset controller | -+-----------+------------+---------------------------------------------+ -| Clock | on-chip | Intel Corporation, SoCFPGA Clock controller | -+-----------+------------+---------------------------------------------+ - -NOTE: TODO, more details on dev kit will be updated as and when available. - -The default configuration can be found in the defconfig file: - `boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig` - -Programming and Debugging -************************* - -Zephyr Boot Flow -**************** -Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). -ATF BL2 is the First Stage Boot Loader (FSBL) and ATF BL31 is the Run time resident firmware which -provides services like SMC (Secure monitor calls) and PSCI (Power state coordination interface). - -Boot flow: - ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL1) - -Intel Arm Trusted Firmware (ATF) can be downloaded from github: - `altera-opensource/arm-trusted-firmware `_ - -Flashing -======== -Zephyr image can be loaded in DDR memory at address 0x80000000 from -SD Card or QSPI Flash or NAND in ATF BL2. - -Debugging -========= -The Intel® Agilex™ 5 SoC Development Kit includes one JTAG connector on -board, connect it to Intel USB blaster download cables for debugging. - -Zephyr applications running on the Cortex-A55/A76 core can be tested by -observing UART console output. - -References -========== -`Intel® Agilex™ 5 FPGA and SoC FPGA `_ diff --git a/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.board b/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.board deleted file mode 100644 index 7dcc7b1e7a5..00000000000 --- a/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_SOCFPGA_AGILEX_SOCDK - bool "Intel SoC FPGA Development Kit (Agilex)" - depends on SOC_AGILEX diff --git a/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.defconfig b/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.defconfig deleted file mode 100644 index 58c3bddb5a1..00000000000 --- a/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "intel_socfpga_agilex_socdk" - depends on BOARD_INTEL_SOCFPGA_AGILEX_SOCDK diff --git a/boards/arm64/intel_socfpga_agilex_socdk/doc/index.rst b/boards/arm64/intel_socfpga_agilex_socdk/doc/index.rst deleted file mode 100644 index fdf60262b15..00000000000 --- a/boards/arm64/intel_socfpga_agilex_socdk/doc/index.rst +++ /dev/null @@ -1,79 +0,0 @@ -.. _intel_socfpga_agilex_socdk: - -Intel Agilex SoC Development Kit -################################# - -Overview -******** - -The Intel Agilex SoC Development Kit offers a complete design environment -that includes both hardware and software for developing Intel Agilex -F-Series FPGA designs. This kit is recommended for developing custom -Arm* processor-based SoC designs and evaluating transceiver performance. - -Hardware -******** - -The Intel Agilex SoC Development Kit supports the following physical features: - -- Intel Agilex F-Series FPGA, 1400 KLE, 2486A package integrate the - quad-core Arm Cortex-A53 processor -- On-board 8 GB DDR4 memory -- On-board JTAG Intel FPGA Download Cable II -- QSPI flash daughtercard -- HPS OOBE daughtercard with UART and SD Card support - -Supported Features -================== -The Intel Agilex SoC Development Kit configuration supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| GIC-400 | on-chip | GICv2 interrupt controller | -+-----------+------------+--------------------------------------+ -| ARM TIMER | on-chip | System Clock | -+-----------+------------+--------------------------------------+ -| UART | on-chip | NS16550 compatible serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig`` - -Programming and Debugging -************************* - -Boot Flow -========= -Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). -ATF BL2 is first stage boot loader (FSBL) and ATF BL31 is second stage -boot loader (SSBL). - -Zephyr boot flow: - - ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL2->EL1) - -Intel Arm Trusted Firmware (ATF) can be downloaded from github: - - `altera-opensource/arm-trusted-firmware `_ - -Flashing -======== -Zephyr image can be loaded in DDR memory at address 0x10000000 from -SD Card or QSPI Flash in ATF BL2. - -Debugging -========= -The Intel Agilex SoC Development Kit includes one JTAG connector on -board, connect it to Intel USB blaster download cables for debugging. - -Zephyr applications running on the Cortex-A53 core can be tested by -observing UART console output. - -References -========== -`Intel Agilex Transceiver-SoC Development Kit `_ diff --git a/boards/arm64/khadas_edgev/Kconfig.board b/boards/arm64/khadas_edgev/Kconfig.board deleted file mode 100644 index 201df41a38b..00000000000 --- a/boards/arm64/khadas_edgev/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_KHADAS_EDGEV - bool "Khadas Edge-V" - depends on SOC_SERIES_RK3399 diff --git a/boards/arm64/khadas_edgev/Kconfig.defconfig b/boards/arm64/khadas_edgev/Kconfig.defconfig deleted file mode 100644 index ac8a0a4dada..00000000000 --- a/boards/arm64/khadas_edgev/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD - default "khadas_edgev" - depends on BOARD_KHADAS_EDGEV diff --git a/boards/arm64/khadas_edgev/doc/index.rst b/boards/arm64/khadas_edgev/doc/index.rst deleted file mode 100644 index 35128a04106..00000000000 --- a/boards/arm64/khadas_edgev/doc/index.rst +++ /dev/null @@ -1,85 +0,0 @@ -.. _khadas_edgev: - -Khadas Edge-V -################################# - -Overview -******** - -See - -Hardware -******** - -See - -Supported Features -================== - -Khadas Edge-V board default configuration supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| GIC-500 | on-chip | GICv3 interrupt controller | -+-----------+------------+--------------------------------------+ -| ARM TIMER | on-chip | System Clock | -+-----------+------------+--------------------------------------+ -| UART | on-chip | Synopsys DesignWare 8250 serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file for NON-SMP: - - ``boards/arm64/khadas_edgev/khadas_edgev_defconfig`` - -There are multiple serial ports on the board: Zephyr is using -uart2 as serial console. - -Programming and Debugging -************************* - -Use the following configuration to run basic Zephyr applications and -kernel tests on Khadas Edge-V board. For example, with the :ref:`hello_world`: - -1. Non-SMP mode - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :host-os: unix - :board: khadas_edgev - :goals: build - -This will build an image with the synchronization sample app. - -Build the zephyr image: - -.. code-block:: console - - mkimage -C none -A arm64 -O linux -a 0x10000000 -e 0x10000000 -d build/zephyr/zephyr.bin build/zephyr/zephyr.img - -Use u-boot to load and kick Zephyr.bin to CPU Core0: - -.. code-block:: console - - tftpboot ${pxefile_addr_r} zephyr.img; bootm start ${pxefile_addr_r}; bootm loados; bootm go - -It will display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build XXXXXXXXXXXX *** - Hello World! khadas_edgev - -Flashing -======== - -Zephyr image can be loaded in DDR memory at address 0x10000000 from SD Card, -EMMC, QSPI Flash or downloaded from network in uboot. - -References -========== - -`Documentation: `_ diff --git a/boards/arm64/mimx8mm_evk/Kconfig.board b/boards/arm64/mimx8mm_evk/Kconfig.board deleted file mode 100644 index c84e506adb7..00000000000 --- a/boards/arm64/mimx8mm_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2021-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MM_EVK_A53 - bool "NXP i.MX8M Mini EVK A53" - depends on SOC_SERIES_MIMX8M_A53 - select SOC_PART_NUMBER_MIMX8MM6DVTLZ diff --git a/boards/arm64/mimx8mm_evk/Kconfig.defconfig b/boards/arm64/mimx8mm_evk/Kconfig.defconfig deleted file mode 100644 index 9f4d9e9490f..00000000000 --- a/boards/arm64/mimx8mm_evk/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2020-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MM_EVK_A53 - -config BOARD - default "mimx8mm_evk_a53" - -endif # BOARD_MIMX8MM_EVK_A53 diff --git a/boards/arm64/mimx8mm_evk/doc/index.rst b/boards/arm64/mimx8mm_evk/doc/index.rst deleted file mode 100644 index 947abd2ba2a..00000000000 --- a/boards/arm64/mimx8mm_evk/doc/index.rst +++ /dev/null @@ -1,131 +0,0 @@ -.. _imx8mm_evk: - -NXP i.MX8MM EVK (Cortex-A53) -############################ - -Overview -******** - -i.MX8M Mini LPDDR4 EVK board is based on NXP i.MX8M Mini applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. -Zephyr OS is ported to run on the Cortex®-A53 core. - -- Board features: - - - RAM: 2GB LPDDR4 - - Storage: - - - SanDisk 16GB eMMC5.1 - - Micron 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11b/g/n - - Bluetooth: v4.1 - - USB: - - - OTG - 2x type C - - Ethernet - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M4 - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mm_evk_a53 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v3 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 8 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART4. - -Programming and Debugging -************************* - -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. - -Use U-Boot to load and kick zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 - -Or kick SMP zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 - - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: mimx8mm_evk_a53 - :goals: run - -This will build an image with the synchronization sample app, boot it and -display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** - thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! - -Use Jailhouse hypervisor, after root cell linux is up: - -.. code-block:: console - - #jailhouse enable imx8mm.cell - #jailhouse cell create imx8mm-zephyr.cell - #jailhouse cell load 1 zephyr.bin -a 0x93c00000 - #jailhouse cell start 1 - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/evaluation-kit-for-thebr-i.mx-8m-mini-applications-processor:8MMINILPD4-EVK - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MMRM diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.dts b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.dts deleted file mode 100644 index 942e5eae9a5..00000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.dts +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2020-2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mm_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MM A53"; - compatible = "fsl,mimx8mm"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - cpu@2 { - status = "disabled"; - }; - }; - - sram0: memory@93c00000 { - reg = <0x93c00000 DT_SIZE_M(1)>; - }; -}; - -&uart4 { - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.yaml b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.yaml deleted file mode 100644 index 72295bdb7eb..00000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: mimx8mm_evk_a53 -name: NXP i.MX8M Mini EVK A53 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_defconfig b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_defconfig deleted file mode 100644 index d8c66f1754a..00000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MM_A53=y -CONFIG_BOARD_MIMX8MM_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.dts b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.dts deleted file mode 100644 index 02b5ca010d1..00000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.dts +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2021-2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mm_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MM A53"; - compatible = "fsl,mimx8mm"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - sram0: memory@93c00000 { - reg = <0x93c00000 DT_SIZE_M(1)>; - }; -}; - -&uart4 { - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.yaml b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.yaml deleted file mode 100644 index b6a23c923e0..00000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: mimx8mm_evk_a53_smp -name: NXP i.MX8M Mini EVK A53 with SMP kernel -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -supported: - - smp -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp_defconfig b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp_defconfig deleted file mode 100644 index 3c06082bb59..00000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MM_A53=y -CONFIG_BOARD_MIMX8MM_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# SMP -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_PM_CPU_OPS=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx8mn_evk/Kconfig.board b/boards/arm64/mimx8mn_evk/Kconfig.board deleted file mode 100644 index 04506a42ed8..00000000000 --- a/boards/arm64/mimx8mn_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MN_EVK_A53 - bool "NXP i.MX8M Nano EVK A53" - depends on SOC_SERIES_MIMX8M_A53 - select SOC_PART_NUMBER_MIMX8MN6DVTJZ diff --git a/boards/arm64/mimx8mn_evk/Kconfig.defconfig b/boards/arm64/mimx8mn_evk/Kconfig.defconfig deleted file mode 100644 index 21f6caecd9b..00000000000 --- a/boards/arm64/mimx8mn_evk/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MN_EVK_A53 - -config BOARD - default "mimx8mn_evk_a53" - -endif # BOARD_MIMX8MN_EVK_A53 diff --git a/boards/arm64/mimx8mn_evk/doc/index.rst b/boards/arm64/mimx8mn_evk/doc/index.rst deleted file mode 100644 index b9620176b6e..00000000000 --- a/boards/arm64/mimx8mn_evk/doc/index.rst +++ /dev/null @@ -1,131 +0,0 @@ -.. _imx8mn_evk: - -NXP i.MX8MN EVK (Cortex-A53) -############################ - -Overview -******** - -i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. -Zephyr OS is ported to run on the Cortex®-A53 core. - -- Board features: - - - RAM: 2GB LPDDR4 - - Storage: - - - SanDisk 16GB eMMC5.1 - - Micron 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11b/g/n - - Bluetooth: v4.1 - - USB: - - - OTG - 2x type C - - Ethernet - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M7 - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mn_evk board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v3 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 8 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART4. - -Programming and Debugging -************************* - -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. - -Use U-Boot to load and kick zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 - -Or kick SMP zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 - - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: mimx8mn_evk_a53 - :goals: run - -This will build an image with the synchronization sample app, boot it and -display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** - thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! - -Use Jailhouse hypervisor, after root cell linux is up: - -.. code-block:: console - - #jailhouse enable imx8mn.cell - #jailhouse cell create imx8mn-zephyr.cell - #jailhouse cell load 1 zephyr.bin -a 0x93c00000 - #jailhouse cell start 1 - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-nano-applications-processor:8MNANOD4-EVK - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MNRM diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.dts b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.dts deleted file mode 100644 index a38bb21184c..00000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.dts +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mn_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MN A53"; - compatible = "fsl,mimx8mn"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - cpu@2 { - status = "disabled"; - }; - }; - - sram0: memory@93c00000 { - reg = <0x93c00000 DT_SIZE_M(1)>; - }; -}; - -&uart4 { - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.yaml b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.yaml deleted file mode 100644 index 4b6bd284846..00000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: mimx8mn_evk_a53 -name: NXP i.MX8M Nano EVK A53 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_defconfig b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_defconfig deleted file mode 100644 index 79da4a06d8f..00000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MN_A53=y -CONFIG_BOARD_MIMX8MN_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.dts b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.dts deleted file mode 100644 index 53af33520db..00000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.dts +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mn_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MN A53"; - compatible = "fsl,mimx8mn"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - sram0: memory@93c00000 { - reg = <0x93c00000 DT_SIZE_M(1)>; - }; -}; - -&uart4 { - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.yaml b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.yaml deleted file mode 100644 index 487c1bb8d3a..00000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: mimx8mn_evk_a53_smp -name: NXP i.MX8M Nano EVK A53 with SMP kernel -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -supported: - - smp -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp_defconfig b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp_defconfig deleted file mode 100644 index 111083ae550..00000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MN_A53=y -CONFIG_BOARD_MIMX8MN_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# SMP -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_PM_CPU_OPS=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx8mp_evk/Kconfig.board b/boards/arm64/mimx8mp_evk/Kconfig.board deleted file mode 100644 index c37a3a6d1f2..00000000000 --- a/boards/arm64/mimx8mp_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2021-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MP_EVK_A53 - bool "NXP i.MX8M Plus EVK A53" - depends on SOC_SERIES_MIMX8M_A53 - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm64/mimx8mp_evk/Kconfig.defconfig b/boards/arm64/mimx8mp_evk/Kconfig.defconfig deleted file mode 100644 index e43bd17cae8..00000000000 --- a/boards/arm64/mimx8mp_evk/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2021-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MP_EVK_A53 - -config BOARD - default "mimx8mp_evk_a53" - -endif # BOARD_MIMX8MP_EVK_A53 diff --git a/boards/arm64/mimx8mp_evk/doc/index.rst b/boards/arm64/mimx8mp_evk/doc/index.rst deleted file mode 100644 index e59f94189a0..00000000000 --- a/boards/arm64/mimx8mp_evk/doc/index.rst +++ /dev/null @@ -1,130 +0,0 @@ -.. _imx8mp_evk: - -NXP i.MX8MP EVK (Cortex-A53) -################################# - -Overview -******** - -i.MX8M Plus LPDDR4 EVK board is based on NXP i.MX8M Plus applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. -Zephyr OS is ported to run on the Cortex®-A53 core. - -- Board features: - - - RAM: 2GB LPDDR4 - - Storage: - - - SanDisk 16GB eMMC5.1 - - Micron 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11b/g/n - - Bluetooth: v4.1 - - USB: - - - OTG - 2x type C - - Ethernet - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M4 - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mp_evk_a53 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v3 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 8 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART4. - -Programming and Debugging -************************* - -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. - -Use U-Boot to load and kick non-smp zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xc0000000 - -Or kick SMP zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0xc0000000 - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: mimx8mp_evk_a53 - :goals: run - -This will build an image with the synchronization sample app, boot it and -display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** - thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! - -Use Jailhouse hypervisor, after root cell linux is up: - -.. code-block:: console - - #jailhouse enable imx8mp.cell - #jailhouse cell create imx8mp-zephyr.cell - #jailhouse cell load 1 zephyr.bin -a 0xc0000000 - #jailhouse cell start 1 - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/docs/en/reference-manual/IMX8MPRM.pdf diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.dts b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.dts deleted file mode 100644 index b0ffede31db..00000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2021-2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mp_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MP A53"; - compatible = "fsl,mimx8mp"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - cpu@2 { - status = "disabled"; - }; - }; - - sram0: memory@c0000000 { - reg = <0xc0000000 DT_SIZE_M(1)>; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.yaml b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.yaml deleted file mode 100644 index dbee1a28ef2..00000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: mimx8mp_evk_a53 -name: NXP i.MX8M Plus EVK A53 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_defconfig b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_defconfig deleted file mode 100644 index 215166ba080..00000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MP_A53=y -CONFIG_BOARD_MIMX8MP_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.dts b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.dts deleted file mode 100644 index 456fd5ea6e2..00000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.dts +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2021-2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mp_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MP A53"; - compatible = "fsl,mimx8mp"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - sram0: memory@c0000000 { - reg = <0xc0000000 DT_SIZE_M(1)>; - }; - -}; - -&uart4 { - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.yaml b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.yaml deleted file mode 100644 index c44defa6a5b..00000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: mimx8mp_evk_a53_smp -name: NXP i.MX8M Plus EVK A53 with SMP kernel -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -supported: - - smp -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp_defconfig b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp_defconfig deleted file mode 100644 index 3e135ef3e30..00000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MP_A53=y -CONFIG_BOARD_MIMX8MP_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# SMP -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_PM_CPU_OPS=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx93_evk/Kconfig.board b/boards/arm64/mimx93_evk/Kconfig.board deleted file mode 100644 index 59ecb516cde..00000000000 --- a/boards/arm64/mimx93_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX93_EVK_A55 - bool "NXP i.MX93 EVK A55" - depends on SOC_SERIES_MIMX9_A55 - select SOC_PART_NUMBER_MIMX9352CVUXK diff --git a/boards/arm64/mimx93_evk/Kconfig.defconfig b/boards/arm64/mimx93_evk/Kconfig.defconfig deleted file mode 100644 index 2e9cc7599ed..00000000000 --- a/boards/arm64/mimx93_evk/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX93_EVK_A55 - -config BOARD - default "mimx93_evk_a55" - -endif # BOARD_MIMX8MP_EVK_A55 diff --git a/boards/arm64/mimx93_evk/doc/index.rst b/boards/arm64/mimx93_evk/doc/index.rst deleted file mode 100644 index 50792491c95..00000000000 --- a/boards/arm64/mimx93_evk/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _imx93_evk: - -NXP i.MX93 EVK (Cortex-A55) -############################ - -Overview -******** - -The i.MX93 Evaluation Kit (MCIMX93-EVK board) is a platform designed to show -the most commonly used features of the i.MX 93 Applications Processor in a -small and low cost package. The MCIMX93-EVK board is an entry-level development -board, which helps developers to get familiar with the processor before -investing a large amount of resources in more specific designs. - -i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single -Cortex®-M33 core. Zephyr OS is ported to run on one of the Cortex®-A55 core. - -- Board features: - - - RAM: 2GB LPDDR4 - - Storage: - - - SanDisk 16GB eMMC5.1 - - microSD Socket - - Wireless: - - - Murata Type-2EL (SDIO+UART+SPI) module. It is based on NXP IW612 SoC, - which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.2, - and 802.15.4 - - USB: - - - Two USB 2.0 Type C connectors - - Ethernet - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 2x UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A55 and M33 - - -Supported Features -================== - -The Zephyr mimx93_evk board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v4 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 24 MHz. -Cortex-A55 Core runs up to 1.7 GHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART4. - -Programming and Debugging -************************* - -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. - -Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1: - -.. code-block:: console - - fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 1 release 0xd0000000 - - -Or use the following command to kick zephyr.bin to Cortex-A55 Core0: - -.. code-block:: console - - fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0000000 - - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: mimx93_evk_a55 - :goals: run - -This will build an image with the synchronization sample app, boot it and -display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.2.0-8-g1613870534a0 *** - thread_a: Hello World from cpu 0 on mimx93_evk_a55! - thread_b: Hello World from cpu 0 on mimx93_evk_a55! - thread_a: Hello World from cpu 0 on mimx93_evk_a55! - thread_b: Hello World from cpu 0 on mimx93_evk_a55! - -References -========== - -More information can refer to NXP official website: -`NXP website`_. - -.. _NXP website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-93-applications-processor-family-arm-cortex-a55-ml-acceleration-power-efficient-mpu:i.MX93 - - -Using the SOF-specific variant -****************************** - -Purpose -======= - -Since this board doesn't have a DSP, an alternative for people who might be interested -in running SOF on this board had to be found. The alternative consists of running SOF -on an A55 core using Jailhouse as a way to "take away" one A55 core from Linux and -assign it to Zephyr with `SOF`_. - -.. _SOF: - https://github.com/thesofproject/sof - -What is Jailhouse? -================== - -Jailhouse is a light-weight hypervisor that allows the partitioning of hardware resources. -For more details on how this is done and, generally, about Jailhouse, please see: `1`_, -`2`_ and `3`_. The GitHub repo can be found `here`_. - -.. _1: - https://lwn.net/Articles/578295/ - -.. _2: - https://lwn.net/Articles/578852/ - -.. _3: - http://events17.linuxfoundation.org/sites/events/files/slides/ELCE2016-Jailhouse-Tutorial.pdf - -.. _here: - https://github.com/siemens/jailhouse - - -How does it work? -================= -Firstly, we need to explain a few Jailhouse concepts that will be referred to later on: - -* **Cell**: refers to a set of hardware resources that the OS assigned to this - cell can utilize. - -* **Root cell**: refers to the cell in which Linux is running. This is the main cell which - will contain all the hardware resources that Linux will utilize and will be used to assign - resources to the inmates. The inmates CANNOT use resources such as the CPU that haven't been - assigned to the root cell. - -* **Inmate**: refers to any other OS that runs alongside Linux. The resources an inmate will - use are taken from the root cell (the cell Linux is running in). - -SOF+Zephyr will run as an inmate, alongside Linux, on core 1 of the board. This means that -said core will be taken away from Linux and will only be utilized by Zephyr. - -The hypervisor restricts inmate's/root's access to certain hardware resources using -the second-stage translation table which is based on the memory regions described in the -configuration files. Please consider the following scenario: - - Root cell wants to use the **UART** which let's say has its registers mapped in - the **[0x0 - 0x42000000]** region. If the inmate wants to use the same **UART** for - some reason then we'd need to also add this region to inmate's configuration - file and add the **JAILHOUSE_MEM_ROOTSHARED** flag. This flag means that the inmate - is allowed to share this region with the root. If this region is not set in - the inmate's configuration file and Zephyr (running as an inmate here) tries - to access this region this will result in a second stage translation fault. - -Notes: - -* Linux and Zephyr are not aware that they are running alongside each other. - They will only be aware of the cores they have been assigned through the config - files (there's a config file for the root and one for each inmate). - -Architecture overview -===================== - -The architecture overview can be found at this `location`_. (latest status update as of now -and the only one containing diagrams). - -.. _location: - https://github.com/thesofproject/sof/issues/7192 - - -How to use this board? -====================== - -This board has been designed for SOF so it's only intended to be used with SOF. - -TODO: document the SOF build process for this board. For now, the support for -i.MX93 is still in review and has yet to merged on SOF side. diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55.dts b/boards/arm64/mimx93_evk/mimx93_evk_a55.dts deleted file mode 100644 index 03b14cf9bc7..00000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55.dts +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright 2022,2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx93_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX93 A55"; - compatible = "fsl,mimx93"; - - chosen { - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - }; - - sram0: memory@d0000000 { - reg = <0xd0000000 DT_SIZE_M(1)>; - }; - - aliases { - led0 = &led_r; - sw0 = &btn_1; - }; - - leds { - compatible = "gpio-leds"; - led_r: led_r { - label = "LED_R"; - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - }; - led_g: led_g { - label = "LED_G"; - gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; - }; - led_b: led_b { - label = "LED_B"; - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - btn_1: btn_1{ - label = "BTN1"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - }; - - btn_2: btn_2{ - label = "BTN2"; - gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&lpuart1 { - status = "disabled"; - current-speed = <115200>; - /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&lpuart2 { - status = "okay"; - current-speed = <115200>; - /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - - -&lpi2c1{ - status = "disabled"; - clock-frequency = ; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&lpi2c2{ - status = "disabled"; - clock-frequency = ; - pinctrl-0 = <&i2c2_default>; - pinctrl-names = "default"; -}; - -&lpspi3 { - status = "disabled"; - clock-frequency = <1000000>; - pinctrl-0 = <&spi3_default>; - pinctrl-names = "default"; -}; - -&gpio1{ - status = "okay"; -}; - -&gpio2{ - status = "okay"; -}; - -&gpio3{ - status = "okay"; -}; - -&gpio4{ - status = "okay"; -}; diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55.yaml b/boards/arm64/mimx93_evk/mimx93_evk_a55.yaml deleted file mode 100644 index d4fc0bc7ae6..00000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: mimx93_evk_a55 -name: NXP i.MX93 Plus EVK A55 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -supported: - - gpio - - uart - - i2c - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55_defconfig b/boards/arm64/mimx93_evk/mimx93_evk_a55_defconfig deleted file mode 100644 index fb60fdfd9bb..00000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y - -# MMU Options -CONFIG_MAX_XLAT_TABLES=64 - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX9_A55=y -CONFIG_SOC_MIMX93_A55=y -CONFIG_BOARD_MIMX93_EVK_A55=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_KERNEL_DIRECT_MAP=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.dts b/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.dts deleted file mode 100644 index 2d1c03e3f9f..00000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.dts +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx93_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX93 A55"; - compatible = "fsl,mimx93"; - - chosen { - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - }; - - /* Inmate memory, reserved through "mem=1248MB" boot argument, - * starts at 0xce000000. - */ - sram0: memory@ce000000 { - reg = <0xce000000 DT_SIZE_M(1)>; - }; - - /* TODO: all of the nodes below are needed by SOF and should - * be removed once all drivers used by SOF have been moved - * to Zephyr. - * - * They are added in the DTS for the sake of not using hardcoded - * values in mmu_regions.c - */ - mu2_a: memory@42430000 { - reg = <0x42430000 DT_SIZE_K(64)>; - }; - - sai3: memory@42660000 { - reg = <0x42660000 DT_SIZE_K(64)>; - }; - - edma2_ch0: memory@42010000 { - reg = <0x42010000 DT_SIZE_K(32)>; - }; - - edma2_ch1: memory@42018000 { - reg = <0x42018000 DT_SIZE_K(32)>; - }; - - outbox: memory@ce100000 { - reg = <0xce100000 DT_SIZE_K(4)>; - }; - - inbox: memory@ce101000 { - reg = <0xce101000 DT_SIZE_K(4)>; - }; - - stream: memory@ce102000 { - reg = <0xce102000 DT_SIZE_K(4)>; - }; - - /* TODO: this is extremely bad and it's needed here because of - * the fact that the DMA buffer shared by host and FW is situated - * in this region. For now, it's easier to create a mapping for the - * whole region but in the future a mapping should only be created - * for the physical address of the buffer sent to the FW through an - * IPC. - */ - host_ram: memory@80000000 { - reg = <0x80000000 DT_SIZE_M(1024)>; - }; -}; - -&lpuart2 { - status = "okay"; - current-speed = <115200>; - /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.yaml b/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.yaml deleted file mode 100644 index 7fffa3f990e..00000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: mimx93_evk_a55_sof -name: NXP i.MX93 Plus EVK A55 for SOF module -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof_defconfig b/boards/arm64/mimx93_evk/mimx93_evk_a55_sof_defconfig deleted file mode 100644 index 6d0bc02b113..00000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof_defconfig +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y - -# The number of bits used for PAs and VAs -# from Zephyr needs to match the number of -# bits used for said address used by Jailhouse. -CONFIG_ARM64_VA_BITS_40=y -CONFIG_ARM64_PA_BITS_40=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y -# SOF doesn't currently support the usage of -# run-time data cache line size detection. -# Because of this, CONFIG_DCACHE_LINE_SIZE_DETECT -# (which defaults to n) can't be set to 'y'. -# The size of data cache line will have to be -# set manually to 64 (value taken from A55 TRM). -CONFIG_DCACHE_LINE_SIZE=64 - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX9_A55=y -CONFIG_SOC_MIMX93_A55=y -CONFIG_BOARD_MIMX93_EVK_A55=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y - -# Enable dynamic interrupts -CONFIG_DYNAMIC_INTERRUPTS=y diff --git a/boards/arm64/nxp_ls1046ardb/Kconfig.board b/boards/arm64/nxp_ls1046ardb/Kconfig.board deleted file mode 100644 index 5986971533e..00000000000 --- a/boards/arm64/nxp_ls1046ardb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2021 NXP -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_NXP_LS1046ARDB - bool "NXP Layerscape ls1046ardb" - depends on SOC_SERIES_LS1046A diff --git a/boards/arm64/nxp_ls1046ardb/Kconfig.defconfig b/boards/arm64/nxp_ls1046ardb/Kconfig.defconfig deleted file mode 100644 index 1896c014d5c..00000000000 --- a/boards/arm64/nxp_ls1046ardb/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2021 NXP -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD - default "nxp_ls1046ardb" - depends on BOARD_NXP_LS1046ARDB diff --git a/boards/arm64/nxp_ls1046ardb/doc/index.rst b/boards/arm64/nxp_ls1046ardb/doc/index.rst deleted file mode 100644 index 98e52f941bc..00000000000 --- a/boards/arm64/nxp_ls1046ardb/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _nxp_ls1046ardb: - -NXP LS1046A RDB -################################# - -Overview -******** - -The LS1046A reference design board (RDB) is a high-performance computing, -evaluation, and development platform that supports the Layerscape LS1046A -architecture processor. The LS1046ARDB board supports the Layerscape LS1046A -processor and is optimized to support the DDR4 memory and a full complement -of high-speed SerDes ports. - -The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72 -cores with packet processing acceleration and high-speed peripherals. The -impressive performance of more than 32,000 CoreMarks, paired with 10 Gb -Ethernet, PCIe Gen. 3, SATA 3.0, USB 3.0 and QSPI interfaces provides an -excellent combination for a range of enterprise and service provider -networking, storage, security and industrial applications. - -Hardware -******** - -LS1046A RDB boards supports the following features: - - -- Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed -- Supports 8 GB DDR4 SDRAM memory -- SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi - memory device -- One 512 MB SLC NAND flash with ECC support (1.8 V) -- CPLD connection: 8-bit registers in CPLD to configure mux/demux selections -- Support two 64 MB onboard QSPI NOR flash memories -- USB: - - Two USB 3.0 controllers with integrated PHYs. - - One USB1 3.0 port is connected to a Type A host connector. - - One USB1 3.0 port is configured as On-The-Go (OTG) with a Micro-AB connector. - - One USB2.0 is connected to miniPCIe connector . -- Ethernet: - - Supports SGMII 1G PHYs at Lane 2 and Lane 3 - - Supports SFP+module with XFI retimers - - Supports AQR106/107 10G PHY with XFI/2.5G SGMII -- PCIe and SATA: - - Mini PCIe express x1 (Gen1/2/3)card - - Standard PCIe x1 (Gen1/2/3) card - - Standard PCIe x1 (Gen1/2/3) card - - One SATA 3.0 connector - -Supported Features -================== - -NXP LS1046A RDB board default configuration supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| GIC-400 | on-chip | GICv2 interrupt controller | -+-----------+------------+--------------------------------------+ -| ARM TIMER | on-chip | System Clock | -+-----------+------------+--------------------------------------+ -| UART | on-chip | NS16550 compatible serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file for NON-SMP: - - ``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig`` - -Or for SMP running on all four CPU Cores: - - ``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores_defconfig`` - -Or for SMP running on 2 CPU Cores (Core2 and Core3): - - ``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores_defconfig`` - -There are two serial port on the board: uart1 and uart2, Zephyr is using -uart2 as serial console. - -Programming and Debugging -************************* - -Use the following configuration to run basic Zephyr applications and -kernel tests on LS1046A RDB board. For example, with the :zephyr:code-sample:`synchronization` sample: - -1. Non-SMP mode - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: nxp_ls1046ardb - :goals: build - -This will build an image with the synchronization sample app. - -Use u-boot to load and kick Zephyr.bin to CPU Core0: - -.. code-block:: console - - tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go 0xc0000000; - -Or kick Zephyr.bin to any other CPU Cores, for example run Zephyr on Core3: - -.. code-block:: console - - tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 3 release 0xc0000000; - - -It will display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - thread_b: Hello World from cpu 0 on nxp_ls1046ardb! - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - -2. SMP mode running on 4 CPU Cores - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: nxp_ls1046ardb_smp_4cores - :goals: build - -This will build an image with the synchronization sample app. - -Use u-boot to load and kick Zephyr.bin to CPU Core0: - -.. code-block:: console - - tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go 0xc0000000; - -It will display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** - Secondary CPU core 1 (MPID:0x1) is up - Secondary CPU core 2 (MPID:0x2) is up - Secondary CPU core 3 (MPID:0x3) is up - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - thread_b: Hello World from cpu 1 on nxp_ls1046ardb! - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - -3. SMP mode running on 2 CPU Cores: Core2 and Core3 - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: nxp_ls1046ardb_smp_2cores - :goals: build - -This will build an image with the synchronization sample app. - -Use u-boot to load and kick Zephyr.bin to CPU Core2: - -.. code-block:: console - - tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 2 release 0xc0000000; - -It will display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** - Secondary CPU core 1 (MPID:0x3) is up - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - thread_b: Hello World from cpu 1 on nxp_ls1046ardb! - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - -4. Running Zephyr on Jailhouse inmate Cell - -Use the following to run Zephyr in Jailhouse inmate, need to configure Jailhouse -inmate Cell to use a single Core for Zephyr non-SMP mode, or use Core2 and Core3 -for Zephyr SMP 2cores image. - -1) Use root Cell dts to boot root Cell Linux. - -2) Install Jailhouse module: - -.. code-block:: console - - modprobe jailhouse - -3) Run Zephyr demo in inmate Cell: - -.. code-block:: console - - jailhouse enable ls1046a-rdb.cell - jailhouse cell create ls1046a-rdb-inmate-demo.cell - jailhouse cell load 1 zephyr.bin --address 0xc0000000 - jailhouse cell start 1 - -Flashing -======== - -Zephyr image can be loaded in DDR memory at address 0xc0000000 from SD Card, -EMMC, QSPI Flash or downloaded from network in uboot. - -Debugging -========= - -LS1046A RDB board includes one JTAG connector on board, connect it to -CodeWarrior TAP for debugging. - -References -========== - -`Layerscape LS1046A Reference Design Board `_ - -`LS1046A Reference Manual `_ diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.yaml b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.yaml deleted file mode 100644 index e00a5475b1b..00000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.yaml +++ /dev/null @@ -1,9 +0,0 @@ -identifier: nxp_ls1046ardb -name: NXP LS1046ARDB on single CPU Core (NON-SMP) -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -vendor: nxp diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig deleted file mode 100644 index c8bb699fd1c..00000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_LS1046A=y -CONFIG_SOC_LS1046A=y -CONFIG_BOARD_NXP_LS1046ARDB=y -CONFIG_ARM64_VA_BITS_40=y -CONFIG_ARM64_PA_BITS_40=y -# 25 MHz system clock -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_AARCH64_IMAGE_HEADER=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores.yaml b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores.yaml deleted file mode 100644 index 93e56887e22..00000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores.yaml +++ /dev/null @@ -1,9 +0,0 @@ -identifier: nxp_ls1046ardb_smp_2cores -name: NXP LS1046ARDB SMP on CPU Core2 and Core3 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -vendor: nxp diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores_defconfig b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores_defconfig deleted file mode 100644 index 8339f5e897c..00000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_LS1046A=y -CONFIG_SOC_LS1046A=y -CONFIG_BOARD_NXP_LS1046ARDB=y -CONFIG_ARM64_VA_BITS_40=y -CONFIG_ARM64_PA_BITS_40=y -# 25 MHz system clock -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_MAX_THREAD_BYTES=5 -CONFIG_MAX_XLAT_TABLES=10 - -# SMP support -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_CACHE_MANAGEMENT=y -CONFIG_ARMV8_A_NS=y - -# PSCI is supported -CONFIG_PM_CPU_OPS=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores.yaml b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores.yaml deleted file mode 100644 index c74af99c1be..00000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores.yaml +++ /dev/null @@ -1,9 +0,0 @@ -identifier: nxp_ls1046ardb_smp_4cores -name: NXP LS1046ARDB SMP on four CPU Cores -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -vendor: nxp diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores_defconfig b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores_defconfig deleted file mode 100644 index 2ed89853987..00000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_LS1046A=y -CONFIG_SOC_LS1046A=y -CONFIG_BOARD_NXP_LS1046ARDB=y -CONFIG_ARM64_VA_BITS_40=y -CONFIG_ARM64_PA_BITS_40=y -# 25 MHz system clock -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_MAX_THREAD_BYTES=5 -CONFIG_MAX_XLAT_TABLES=10 - -# SMP support -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=4 -CONFIG_CACHE_MANAGEMENT=y -CONFIG_ARMV8_A_NS=y - -# PSCI is supported -CONFIG_PM_CPU_OPS=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/phycore_am62x_a53/Kconfig.board b/boards/arm64/phycore_am62x_a53/Kconfig.board deleted file mode 100644 index 1a8e9d08363..00000000000 --- a/boards/arm64/phycore_am62x_a53/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PHYCORE_AM62X_A53 - bool "PHYTEC phyCORE-AM62x A53" - depends on SOC_SERIES_AM6X_A53 diff --git a/boards/arm64/phycore_am62x_a53/Kconfig.defconfig b/boards/arm64/phycore_am62x_a53/Kconfig.defconfig deleted file mode 100644 index 51dd70ebc3c..00000000000 --- a/boards/arm64/phycore_am62x_a53/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PHYCORE_AM62X_A53 - -config BOARD - default "phycore_am62x_a53" - -endif # BOARD_PHYCORE_AM62X_A53 diff --git a/boards/arm64/phycore_am62x_a53/doc/index.rst b/boards/arm64/phycore_am62x_a53/doc/index.rst deleted file mode 100644 index 0fb1c6063b1..00000000000 --- a/boards/arm64/phycore_am62x_a53/doc/index.rst +++ /dev/null @@ -1,109 +0,0 @@ -.. _phycore_am62x_a53: - -PHYTEC phyCORE-AM62x (Cortex-A53) -################################# - -Overview -******** - -PHYTEC phyCORE-AM62x board is based on TI Sitara applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. -Zephyr OS is ported to run on the Cortex®-A53 core. - -- Board features: - - - RAM: 2GB DDR4 - - Storage: - - - 16GB eMMC - - 64MB OSPI NOR - - 4KB EEPROM - - Ethernet - -More information about the board can be found at the -`PHYTEC website`_. - -Supported Features -================== - -The Zephyr phycore_am62x_a53 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v3 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| PINCTRL | on-chip | pinctrl | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 200 MHz. - -DDR RAM -------- - -The board has 2GB of DDR RAM available. This board configuration -allocates Zephyr 1MB of RAM (0x82000000 to 0x82100000). - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART0. - -SD Card -******* - -Download PHYTEC's official `WIC`_ and `bmap`_ files and flash the WIC file with -bmap-tools on a SD-card. - -.. code-block:: console - - bmaptool copy phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz /dev/sdX - -Building -******** - -You can build an application in the usual way. Refer to -:ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :board: phycore_am62x_a53 - :zephyr-app: samples/hello_world - :goals: build - -Programming -*********** - -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. - -Use U-Boot to load and kick zephyr.bin: - -.. code-block:: console - - fatload mmc 1:1 0x82000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x82000000 - - -.. - References - -.. _PHYTEC website: - https://www.phytec.com/product/phycore-am62x/ - -.. _WIC: - https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz - -.. _Bmap: - https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.bmap diff --git a/boards/arm64/phycore_am62x_a53/phycore_am62x_a53.yaml b/boards/arm64/phycore_am62x_a53/phycore_am62x_a53.yaml deleted file mode 100644 index fe65e6b4a36..00000000000 --- a/boards/arm64/phycore_am62x_a53/phycore_am62x_a53.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: phycore_am62x_a53 -name: PHYTEC phyCORE-AM62x A53 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -testing: - ignore_tags: - - net - - bluetooth -vendor: ti diff --git a/boards/arm64/phycore_am62x_a53/phycore_am62x_a53_defconfig b/boards/arm64/phycore_am62x_a53/phycore_am62x_a53_defconfig deleted file mode 100644 index 3f5893f6747..00000000000 --- a/boards/arm64/phycore_am62x_a53/phycore_am62x_a53_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_AM6X_A53=y -CONFIG_SOC_AM6234_A53=y -CONFIG_BOARD_PHYCORE_AM62X_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/qemu_cortex_a53/Kconfig.board b/boards/arm64/qemu_cortex_a53/Kconfig.board deleted file mode 100644 index c14d70c2b72..00000000000 --- a/boards/arm64/qemu_cortex_a53/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_CORTEX_A53 - bool "Cortex-A53 Emulation (QEMU)" - depends on SOC_QEMU_CORTEX_A53 - select ARM64 - select QEMU_TARGET - -config QEMU_CORTEX_A53_ETH_E1000 - bool "Use Intel e1000 Ethernet driver for networking" - default y if !NET_TEST - depends on BOARD_QEMU_CORTEX_A53 && NETWORKING && DT_HAS_INTEL_E1000_ENABLED - select ETH_E1000 - select NET_L2_ETHERNET - select PCIE - select PCIE_CONTROLLER - select PCIE_ECAM diff --git a/boards/arm64/qemu_cortex_a53/Kconfig.defconfig b/boards/arm64/qemu_cortex_a53/Kconfig.defconfig deleted file mode 100644 index 8f10806f7ba..00000000000 --- a/boards/arm64/qemu_cortex_a53/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_CORTEX_A53 - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "qemu_cortex_a53" - -config MAX_THREAD_BYTES - default 3 - -if NETWORKING - -choice NET_QEMU_NETWORKING - default NET_QEMU_ETHERNET if QEMU_CORTEX_A53_ETH_E1000 -endchoice - -config NET_DRIVERS - default n if QEMU_CORTEX_A53_ETH_E1000 - -endif # NETWORKING - -# QEMU PCI requires at least 256M of virtual space -config KERNEL_VM_SIZE - default 0x80000000 if PCIE - -# QEMU PCI requires physical addresses with more than 32 bits -choice ARM64_VA_BITS - default ARM64_VA_BITS_40 if PCIE -endchoice - -choice ARM64_PA_BITS - default ARM64_PA_BITS_40 if PCIE -endchoice - -endif # BOARD_QEMU_CORTEX_A53 diff --git a/boards/arm64/qemu_cortex_a53/board.cmake b/boards/arm64/qemu_cortex_a53/board.cmake deleted file mode 100644 index 4935438e4b7..00000000000 --- a/boards/arm64/qemu_cortex_a53/board.cmake +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) -set(QEMU_ARCH aarch64) - -set(QEMU_CPU_TYPE_${ARCH} cortex-a53) - -if(CONFIG_ARMV8_A_NS) -set(QEMU_MACH virt,gic-version=3) -else() -set(QEMU_MACH virt,secure=on,gic-version=3) -endif() - -set(QEMU_FLAGS_${ARCH} - -cpu ${QEMU_CPU_TYPE_${ARCH}} - -nographic - -machine ${QEMU_MACH} - ) - -if(CONFIG_XIP) - # This should be equivalent to - # ... -drive if=pflash,file=build/zephyr/zephyr.bin,format=raw - # without having to pad the binary file to the FLASH size - set(QEMU_KERNEL_OPTION - -bios ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin - ) -endif() - -board_set_debugger_ifnset(qemu) diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_defconfig b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_defconfig deleted file mode 100644 index e697012a690..00000000000 --- a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_SOC_QEMU_CORTEX_A53=y -CONFIG_BOARD_QEMU_CORTEX_A53=y -CONFIG_ARM_ARCH_TIMER=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Avoid timing skew in tests -CONFIG_QEMU_ICOUNT=y -CONFIG_QEMU_ICOUNT_SHIFT=4 -CONFIG_QEMU_ICOUNT_SLEEP=y diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp.yaml b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp.yaml deleted file mode 100644 index 9a6e87c0a70..00000000000 --- a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: qemu_cortex_a53_smp -name: QEMU Emulation for Cortex-A53 SMP -type: qemu -simulation: qemu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -supported: - - smp -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: qemu diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp_defconfig b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp_defconfig deleted file mode 100644 index ad9011aa3b7..00000000000 --- a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -CONFIG_SOC_QEMU_CORTEX_A53=y -CONFIG_BOARD_QEMU_CORTEX_A53=y -CONFIG_ARM_ARCH_TIMER=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# icount does not work well with SMP -CONFIG_QEMU_ICOUNT=n - -# We have multiple QEMU-A53 boards, so let us exercise ARMV8_A_NS on this one -# (plus it is needed for SMP) -CONFIG_ARMV8_A_NS=y - -# PSCI is supported with NS -CONFIG_PM_CPU_OPS=y - -# SMP-related -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_TIMEOUT_64BIT=y diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.yaml b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.yaml deleted file mode 100644 index 5654908d3d2..00000000000 --- a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_cortex_a53_xip -name: QEMU Emulation for Cortex-A53 (XIP) -type: qemu -simulation: qemu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -testing: - default: true - only_tags: - - xip -vendor: qemu diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip_defconfig b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip_defconfig deleted file mode 100644 index d2dbdc1fc51..00000000000 --- a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_SOC_QEMU_CORTEX_A53=y -CONFIG_BOARD_QEMU_CORTEX_A53=y -CONFIG_ARM_ARCH_TIMER=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Avoid timing skew in tests -CONFIG_QEMU_ICOUNT=y -CONFIG_QEMU_ICOUNT_SHIFT=4 -CONFIG_QEMU_ICOUNT_SLEEP=y - -# Enable XIP -CONFIG_XIP=y diff --git a/boards/arm64/qemu_kvm_arm64/Kconfig.board b/boards/arm64/qemu_kvm_arm64/Kconfig.board deleted file mode 100644 index 6542a5383e5..00000000000 --- a/boards/arm64/qemu_kvm_arm64/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Huawei France Technologies SASU -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_KVM_ARM64 - bool "Cortex AArch64 KVM Virt Emulation (QEMU)" - depends on SOC_QEMU_VIRT_ARM64 - select ARM64 - select QEMU_TARGET diff --git a/boards/arm64/qemu_kvm_arm64/Kconfig.defconfig b/boards/arm64/qemu_kvm_arm64/Kconfig.defconfig deleted file mode 100644 index 0156bce7e2e..00000000000 --- a/boards/arm64/qemu_kvm_arm64/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2022 Huawei France Technologies SASU -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_KVM_ARM64 - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "qemu_kvm_arm64" - -endif # BOARD_QEMU_KVM_ARM64 diff --git a/boards/arm64/rcar_h3ulcb_ca57/Kconfig.board b/boards/arm64/rcar_h3ulcb_ca57/Kconfig.board deleted file mode 100644 index 7367501632b..00000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RCAR_H3ULCB_CA57 - bool "Renesas H3ULCB" - depends on SOC_ARM64_R8A77951 diff --git a/boards/arm64/rcar_h3ulcb_ca57/Kconfig.defconfig b/boards/arm64/rcar_h3ulcb_ca57/Kconfig.defconfig deleted file mode 100644 index fefd6e1259d..00000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RCAR_H3ULCB_CA57 - -config BOARD - default "rcar_h3ulcb_ca57" - -config BUILD_OUTPUT_BIN - default y - -endif # BOARD_RCAR_H3ULCB_CA57 diff --git a/boards/arm64/rcar_h3ulcb_ca57/doc/index.rst b/boards/arm64/rcar_h3ulcb_ca57/doc/index.rst deleted file mode 100644 index a22d948be2a..00000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/doc/index.rst +++ /dev/null @@ -1,86 +0,0 @@ -.. _rcar_h3ulcb_ca57: - -R-CAR H3 ARM CA57 (ARMv8) -######################### - -Overview -******** -The R-Car H3 is an SOC that features the basic functions for next-generation -car navigation systems. - -Hardware -******** -The R-Car H3 includes: - -* four 1.5-GHz ARM Cortex-A57 MPCore cores; -* four 1.2-GHz ARM Cortex-A53 MPCore cores; -* memory controller for LPDDR4-3200 with 32 bits x 4 channels; -* 2 channels for HDMI1.4b output and 1channel for RGB888 output and 1channel for LVDS; -* 4 channels MIPI-CSI2 Video Input, 2channels digital Video Input; -* serial ATA interface; -* USB3.0 x 2ch and USB2.0 x 3ch interfaces; -* 800-MHz ARM Cortex-R7 core; -* two- and three-dimensional graphics engines; -* video processing units; -* sound processing units; -* MediaLB interface; -* SD card host interface; -* USB3.0 and USB2.0 interfaces; -* PCI Express interface; -* CAN interface; -* EtherAVB. - -Connections and IOs -=================== - -H3ULCB Board ------------- - -Here are official IOs figures from eLinux for H3ULCB board: - -.. figure:: img/rcar_h3ulcb_top.jpg - :align: center - -.. figure:: img/rcar_h3ulcb_bottom.jpg - :align: center - -Supported Features -================== -The Renesas rcar_h3ulcb_ca57 board configuration supports the following -hardware features: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINCTRL | pinctrl | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+-----------+------------------------------+--------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57_defconfig`` - -Programming and Debugging -************************* - -Flashing -======== - -The flash on board is not supported by Zephyr at this time. - -References -********** - -- `Renesas R-Car Development Support website`_ -- `eLinux R-Car Starter Kit page`_ - -.. _Renesas R-Car Development Support website: - https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support - -.. _eLinux R-Car Starter Kit page: - https://elinux.org/R-Car/Boards/H3SK diff --git a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.dts b/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.dts deleted file mode 100644 index 7c1f153325d..00000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2023 EPAM Systems - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -/dts-v1/; -#include -#include -#include "rcar_h3ulcb_ca57-pinctrl.dtsi" - -/ { - model = "H3ULCB CA57"; - - chosen { - zephyr,sram = &ram; - zephyr,console = &scif2; - zephyr,shell-uart = &scif2; - }; - - ram: memory@48000000 { - device_type = "mmio-sram"; - reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_data_a_tx_default &scif2_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.yaml b/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.yaml deleted file mode 100644 index e34235c2d43..00000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: rcar_h3ulcb_ca57 -name: Renesas H3ULCB based on r8a77951 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 512 -supported: - - clock_control - - uart -testing: - ignore_tags: - - net - - bluetooth - - isotp -vendor: renesas diff --git a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57_defconfig b/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57_defconfig deleted file mode 100644 index 3995ececf44..00000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -CONFIG_SOC_ARM64_R8A77951=y -CONFIG_SOC_SERIES_RCAR_GEN3=y -CONFIG_BOARD_RCAR_H3ULCB_CA57=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -# Enable UART driver -CONFIG_SERIAL=y -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8300000 -CONFIG_XIP=n - -CONFIG_MAX_XLAT_TABLES=24 -CONFIG_ARMV8_A_NS=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable clock control -CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm64/rcar_salvator_xs_m3/Kconfig.board b/boards/arm64/rcar_salvator_xs_m3/Kconfig.board deleted file mode 100644 index 032514dac7a..00000000000 --- a/boards/arm64/rcar_salvator_xs_m3/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RCAR_SALVATOR_XS_M3 - bool "Renesas Salvator XS M3" - depends on SOC_R8A77961 diff --git a/boards/arm64/rcar_salvator_xs_m3/Kconfig.defconfig b/boards/arm64/rcar_salvator_xs_m3/Kconfig.defconfig deleted file mode 100644 index 7230474a1d7..00000000000 --- a/boards/arm64/rcar_salvator_xs_m3/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RCAR_SALVATOR_XS_M3 - -config BOARD - default "rcar_salvator_xs_m3" - -config BUILD_OUTPUT_BIN - default y - -endif # BOARD_RCAR_SALVATOR_XS_M3 diff --git a/boards/arm64/rcar_salvator_xs_m3/doc/index.rst b/boards/arm64/rcar_salvator_xs_m3/doc/index.rst deleted file mode 100644 index b89c71d4ecd..00000000000 --- a/boards/arm64/rcar_salvator_xs_m3/doc/index.rst +++ /dev/null @@ -1,69 +0,0 @@ -.. _rcar_salvator_xs_m3: - -R-CAR Salvator XS M3 ARM CA57 (ARMv8) -##################################### - -Overview -******** -The R-Car M3-W is an SOC that features the basic functions for next-generation -car navigation systems. - -Hardware -******** -The R-Car M3-W includes: - -* two 1.5-GHz ARM Cortex-A57 MPCore cores; -* four 1.3-GHz ARM Cortex-A53 MPCore cores, -* memory controller for LPDDR4-3200 with 32 bits x 2 channels; -* 1 channels for HDMI1.4b output and 1 channel for RGB888 output and 1channel for LVDS; -* 2 channels MIPI-CSI2 Video Input, 2 channels digital Video Input; -* USB3.0 x 1ch and USB2.0 x 2ch interfaces; -* 800-MHz ARM Cortex-R7 core; -* two- and three-dimensional graphics engines; -* video processing units; -* sound processing units; -* MediaLB interface; -* SD card host interface; -* USB3.0 and USB2.0 interfaces; -* PCI Express interface; -* CAN interface; -* EtherAVB. - -Supported Features -================== -The Renesas rcar_salvator_xs_m3 board configuration supports the following -hardware features: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINCTRL | pinctrl | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+-----------+------------------------------+--------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3_defconfig`` - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -References -********** - -- `Renesas R-Car Development Support website`_ -- `eLinux Salvator-XS page`_ - -.. _Renesas R-Car Development Support website: - https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support - -.. _eLinux Salvator-XS page: - https://elinux.org/R-Car/Boards/Salvator-XS diff --git a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.dts b/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.dts deleted file mode 100644 index 15fae0ca965..00000000000 --- a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2023 EPAM Systems - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -/dts-v1/; -#include -#include -#include "salvator_xs_m3-pinctrl.dtsi" - -/ { - model = "Salvator XS M3"; - - chosen { - zephyr,sram = &ram; - zephyr,console = &scif2; - zephyr,shell-uart = &scif2; - }; - - ram: memory@48000000 { - device_type = "mmio-sram"; - reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_data_a_tx_default &scif2_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.yaml b/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.yaml deleted file mode 100644 index 84d4a864a35..00000000000 --- a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: rcar_salvator_xs_m3 -name: Renesas Salvator XS M3 based on r8a77961 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 512 -supported: - - clock_control - - uart -testing: - ignore_tags: - - net - - bluetooth - - isotp -vendor: renesas diff --git a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3_defconfig b/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3_defconfig deleted file mode 100644 index a6eb4060d39..00000000000 --- a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -CONFIG_SOC_R8A77961=y -CONFIG_SOC_SERIES_RCAR_GEN3=y -CONFIG_BOARD_RCAR_SALVATOR_XS_M3=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -# Enable UART driver -CONFIG_SERIAL=y -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8300000 -CONFIG_XIP=n - -CONFIG_MAX_XLAT_TABLES=24 -CONFIG_ARMV8_A_NS=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable clock control -CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm64/roc_rk3568_pc/Kconfig.board b/boards/arm64/roc_rk3568_pc/Kconfig.board deleted file mode 100644 index 97844de31fd..00000000000 --- a/boards/arm64/roc_rk3568_pc/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyr -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ROC_RK3568_PC - bool "Rockchip ROC-RK3568-PC" - depends on SOC_SERIES_RK3568 - select ARM64 diff --git a/boards/arm64/roc_rk3568_pc/Kconfig.defconfig b/boards/arm64/roc_rk3568_pc/Kconfig.defconfig deleted file mode 100644 index 9ad4f73bd2b..00000000000 --- a/boards/arm64/roc_rk3568_pc/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyr -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ROC_RK3568_PC - -config BOARD - default "roc_rk3568_pc" - -endif # BOARD_ROC_RK3568_PC diff --git a/boards/arm64/roc_rk3568_pc/doc/index.rst b/boards/arm64/roc_rk3568_pc/doc/index.rst deleted file mode 100644 index ae999409545..00000000000 --- a/boards/arm64/roc_rk3568_pc/doc/index.rst +++ /dev/null @@ -1,142 +0,0 @@ -.. _roc_rk3568_pc: - -Firefly ROC-RK3568-PC (Quad-core Cortex-A55) -############################################ - -Overview -******** - -The ROC-RK3568-PC is a Quad-Core 64-Bit Mini Computer, which supports 4G large RAM. M.2 -and SATA3.0 interfaces enables expansion with large hard drives. -Providing dual Gigabit Ethernet ports, it supports WiFi 6 wireless transmission. -Control Port can be connected with RS485/RS232 devices. - -RK3568 quad-core 64-bit Cortex-A55 processor, with brand new ARM v8.2-A architecture, -has frequency up to 2.0GHz. Zephyr OS is ported to run on it. - - -- Board features: - - - RAM: 4GB LPDDR4 - - Storage: - - - 32GB eMMC - - M.2 PCIe 3.0 x 1 (Expand with 2242 / 2280 NVMe SSD) - - TF-Card Slot - - Wireless: - - - Supports WiFi 6 (802.11 AX) - - Supports BT5.0 - - USB: - - - One USB 3.0 - - Two USB 2.0 - - One Type-C - - Ethernet - - M.2 PCIe3.0 (Expand with NVMe SSD) - - LEDs: - - - 1x Power status LED - - Debug - - - UART debug ports for board - - -Supported Features -================== - -The Zephyr roc_rk3568_pc board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v3 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 24 MHz. -Cortex-A55 Core runs up to 2.0 GHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART2. - -Programming and Debugging -************************* - -Use U-Boot to load the zephyr.bin to the memory and kick it: - -.. code-block:: console - - tftp 0x40000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x40000000 - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: roc_rk3568_pc - :goals: run - -This will build an image with the synchronization sample app, boot it and -display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build bc695c6df5eb *** - thread_a: Hello World from cpu 0 on roc_rk3568_pc! - thread_b: Hello World from cpu 0 on roc_rk3568_pc! - thread_a: Hello World from cpu 0 on roc_rk3568_pc! - thread_b: Hello World from cpu 0 on roc_rk3568_pc! - - -roc_rk3568_pc_smp support, use this configuration to run Zephyr smp applications and subsys tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: roc_rk3568_pc_smp - :goals: run - -This will build an image with the shell_module sample app, boot it and -display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build bc695c6df5eb *** - I/TC: Secondary CPU 1 initializing - I/TC: Secondary CPU 1 switching to normal world boot - I/TC: Secondary CPU 2 initializing - I/TC: Secondary CPU 2 switching to normal world boot - I/TC: Secondary CPU 3 initializing - I/TC: Secondary CPU 3 switching to normal world boot - Secondary CPU core 1 (MPID:0x100) is up - Secondary CPU core 2 (MPID:0x200) is up - Secondary CPU core 3 (MPID:0x300) is up - - thread_a: Hello World from cpu 0 on roc_rk3568_pc! - thread_b: Hello World from cpu 1 on roc_rk3568_pc! - thread_a: Hello World from cpu 0 on roc_rk3568_pc! - thread_b: Hello World from cpu 1 on roc_rk3568_pc! - -References -========== - -More information can refer to Firefly official website: -`Firefly website`_. - -.. _Firefly website: - https://en.t-firefly.com/product/industry/rocrk3568pc.html?theme=pc diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.yaml b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.yaml deleted file mode 100644 index 07120b871fa..00000000000 --- a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: roc_rk3568_pc_smp -name: Rockchip ROC RK3568 PC SMP -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -supported: - - smp -testing: - ignore_tags: - - net - - bluetooth diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp_defconfig b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp_defconfig deleted file mode 100644 index 3ffc3f25b41..00000000000 --- a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyr -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_RK3568=y -CONFIG_SOC_RK3568=y -CONFIG_BOARD_ROC_RK3568_PC=y -CONFIG_ARM_ARCH_TIMER=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_NS16550=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# SMP support -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=4 -CONFIG_MAX_THREAD_BYTES=4 - -# ARMv8 NS world with cache management -CONFIG_ARMV8_A_NS=y -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE=y - -# PSCI support -CONFIG_PM_CPU_OPS=y -CONFIG_PM_CPU_OPS_PSCI=y - -# Clock support -CONFIG_CLOCK_CONTROL=y -CONFIG_TICKLESS_KERNEL=y diff --git a/boards/arm64/rpi_4b/Kconfig.board b/boards/arm64/rpi_4b/Kconfig.board deleted file mode 100644 index 9b0e9c80985..00000000000 --- a/boards/arm64/rpi_4b/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2023 honglin leng -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RPI_4B - bool "Broadcom BCM2711" - depends on SOC_BCM2711 diff --git a/boards/arm64/rpi_4b/Kconfig.defconfig b/boards/arm64/rpi_4b/Kconfig.defconfig deleted file mode 100644 index c04170c5751..00000000000 --- a/boards/arm64/rpi_4b/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2023 honglin leng -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "Raspberry Pi 4 Model B" - depends on BOARD_RPI_4B diff --git a/boards/arm64/rpi_4b/doc/index.rst b/boards/arm64/rpi_4b/doc/index.rst deleted file mode 100644 index a3222f368b7..00000000000 --- a/boards/arm64/rpi_4b/doc/index.rst +++ /dev/null @@ -1,71 +0,0 @@ -.. rpi_4b: - -Raspberry Pi 4 Model B (Cortex-A72) -################################### - -Overview -******** -see - -Hardware -******** -see - -Supported Features -================== -The Raspberry Pi 4 Model B board configuration supports the following -hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - GIC-400 - - N/A - - :dtcompatible:`arm,gic-v2` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`brcm,bcm2711-gpio` - * - UART (Mini UART) - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`brcm,bcm2711-aux-uart` - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm64/rpi_4b/rpi_4b_defconfig`` - -Programming and Debugging -************************* - -TF Card -======= - -Prepare a TF card with MBR and FAT32. In the root directory of the TF card: - -1. Download and place these firmware files: - - * `bcm2711-rpi-4-b.dtb `_ - * `bootcode.bin `_ - * `start4.elf `_ - -2. Copy ``build/zephyr/zephyr.bin`` -3. Create a ``config.txt``: - - .. code-block:: text - - kernel=zephyr.bin - arm_64bit=1 - enable_uart=1 - uart_2ndstage=1 - -Insert the card and power on the board. You should see the following output on -the serial console (GPIO 14/15): - -.. code-block:: text - - *** Booting Zephyr OS build XXXXXXXXXXXX *** - Hello World! Raspberry Pi 4 Model B! diff --git a/boards/arm64/xenvm/Kconfig.board b/boards/arm64/xenvm/Kconfig.board deleted file mode 100644 index a967e98216a..00000000000 --- a/boards/arm64/xenvm/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2020 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_XENVM - bool "Xen Virtual Machine" - depends on SOC_XENVM - select ARM64 diff --git a/boards/arm64/xenvm/Kconfig.defconfig b/boards/arm64/xenvm/Kconfig.defconfig deleted file mode 100644 index 2e8d48bc8f6..00000000000 --- a/boards/arm64/xenvm/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2020 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_XENVM - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "xenvm" - -endif # BOARD_XENVM diff --git a/boards/arm64/xenvm/doc/index.rst b/boards/arm64/xenvm/doc/index.rst deleted file mode 100644 index bfeb319aaae..00000000000 --- a/boards/arm64/xenvm/doc/index.rst +++ /dev/null @@ -1,188 +0,0 @@ -.. xenvm: - -ARMv8 Xen Virtual Machine Example -################################# - -Overview -******** - -This board allows to run Zephyr as Xen guest on any ARMv8 board that supports -ARM Virtualization Extensions. This is example configuration, as almost any VM -configuration is unique in many aspects. - -It provides minimal set of devices: - -* ARM Generic timer -* GICv2/GICv3 - -Hardware -******** -Supported Features -================== - -The following hardware features are supported: - -+--------------+-------------+----------------------+ -| Interface | Controller | Driver/Component | -+==============+=============+======================+ -| GIC | virtualized | interrupt controller | -+--------------+-------------+----------------------+ -| ARM TIMER | virtualized | system clock | -+--------------+-------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. - -The default configuration using GICv2 can be found in the defconfig file: - ``boards/arm64/xenvm/xenvm_defconfig`` - -The default configuration using GICv3 can be found in the defconfig file: - ``boards/arm64/xenvm/xenvm_gicv3_defconfig`` - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 8.32 MHz. This is the -default value, which should be corrected for user's actual hardware. - -You can determine clock frequency of your ARM Generic Timer by inspecting Xen -boot log: - -:: - - (XEN) [ 0.147541] Generic Timer IRQ: phys=30 hyp=26 virt=27 Freq: 8320 KHz - -Interrupt Controller --------------------- - -Depending on the version of the GIC on your hardware, you may choose one of the -following board configurations: - -- ``xenvm_defconfig`` selects GICv2 -- ``xenvm_gicv3_defconfig`` selects GICv3 - -CPU Core type -------------- - -Default core in this configuration is Cortex A72. Depending on yours actual -hardware you might want to change this option in the same way as Interrupt -Controller configuration. - -Known Problems or Limitations -============================== - -Xen configures guests in runtime by providing device tree that describes guest -environment. On other hand, Zephyr uses static configuration that should be know -at build time. So there are chances, that Zephyr image created with default -configuration would not boot on your hardware. In this case you need to update -configuration by altering device tree and Kconfig options. This will be covered -in detail in next section. - -Most of Xen-specific features are not supported at the moment. This includes: -* XenBus (under development) -* Xen PV drivers - -Now only following features are supported: -* Xen Enlighten memory page -* Xen event channels -* Xen PV console (2 versions: regular ring buffer based for DomU and consoleio for Dom0) -* Xen early console_io interface (mainly for debug purposes - requires debug version of Xen) -* Xen grant tables (granting access for own grants and map/unmap foreign grants) - -Building and Running -******************** - -Use this configuration to run basic Zephyr applications and kernel tests as Xen -guest, for example, with the :zephyr:code-sample:`synchronization` sample: - -- if your hardware is based on GICv2: - -.. code-block:: - - $ west build -b xenvm samples/synchronization - -- if your hardware is based on GICv3: - -.. code-block:: - - $ west build -b xenvm_gicv3 samples/synchronization - -This will build an image with the synchronization sample app. Next, you need to -create guest configuration file :code:`zephyr.conf`. There is example: - -.. code-block:: - - kernel="zephyr.bin" - name="zephyr" - vcpus=1 - memory=16 - gic_version="v2" - on_crash="preserve" - -When using ``xenvm_gicv3`` configuration, you need to remove the ``gic_version`` -parameter or set it to ``"v3"``. - -You need to upload both :code:`zephyr.bin` and :code:`zephyr.conf` to your Dom0 -and then you can run Zephyr by issuing - -.. code-block:: - - $ xl create zephyr.conf - -Next you need to attach to PV console: - -.. code-block:: - - $ xl console zephyr - -Also this can be performed via single command: - -.. code-block:: - - $ xl create -c zephyr.conf - -You will see Zephyr output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.4.0-1137-g5803ee1e8183 *** - thread_a: Hello World from cpu 0 on xenvm! - thread_b: Hello World from cpu 0 on xenvm! - thread_a: Hello World from cpu 0 on xenvm! - thread_b: Hello World from cpu 0 on xenvm! - thread_a: Hello World from cpu 0 on xenvm! - -Exit xen virtual console by pressing :kbd:`CTRL+]` - -Updating configuration -********************** - -As was said earlier, Xen describes hardware using device tree and expects that -guest will parse device tree in runtime. On other hand, Zephyr supports only -static, build time configuration. While provided configuration should work on -almost any ARMv8 host running in aarch64 mode, there is no guarantee, that Xen -will not change some values (like RAM base address) in the future. - -Also, frequency of system timer is board specific and should be updated when running -Zephyr xenvm image on new hardware. - -One can make Xen to dump generated DTB by using :code:`LIBXL_DEBUG_DUMP_DTB` -environment variable, like so: - -.. code-block:: - - $ LIBXL_DEBUG_DUMP_DTB=domu-libxl.dtb xl create zephyr.conf - -Then, generated "domu-libxl.dtb" file can be de-compiled using "dtc" tool. - -Use information from de-compiled DTB file to update all related entries in -provided "xenvm.dts" file. If memory layout is also changed, you may need to -update :code:`CONFIG_SRAM_BASE_ADDRESS` as well. - -References -********** - -`Xen ARM with Virtualization Extensions `_ - -`xl.conf (guest configuration file) manual `_ diff --git a/boards/arm64/xenvm/xenvm_gicv3.yaml b/boards/arm64/xenvm/xenvm_gicv3.yaml deleted file mode 100644 index 91026d183d2..00000000000 --- a/boards/arm64/xenvm/xenvm_gicv3.yaml +++ /dev/null @@ -1,9 +0,0 @@ -identifier: xenvm_gicv3 -name: ARMv8 Xen Virtual Machine With GICv3 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 16384 -vendor: xen diff --git a/boards/arm64/xenvm/xenvm_gicv3_defconfig b/boards/arm64/xenvm/xenvm_gicv3_defconfig deleted file mode 100644 index 7b6b9afa888..00000000000 --- a/boards/arm64/xenvm/xenvm_gicv3_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_SOC_XENVM=y -CONFIG_BOARD_XENVM=y - -# Enable UART driver -CONFIG_SERIAL=y - -CONFIG_MAX_XLAT_TABLES=24 - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable logging subsys -CONFIG_LOG=y -CONFIG_LOG_MODE_MINIMAL=n - -CONFIG_USERSPACE=n - -CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y diff --git a/boards/arturo182/index.rst b/boards/arturo182/index.rst new file mode 100644 index 00000000000..d9093d36c10 --- /dev/null +++ b/boards/arturo182/index.rst @@ -0,0 +1,10 @@ +.. _boards-arturo182: + +Arturo182 +######### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arturo182/serpente/Kconfig.serpente b/boards/arturo182/serpente/Kconfig.serpente new file mode 100644 index 00000000000..3c22b1b359b --- /dev/null +++ b/boards/arturo182/serpente/Kconfig.serpente @@ -0,0 +1,6 @@ +# Copyright (c) 2020 Alexander Falb +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SERPENTE + select SOC_SAMD21E18A diff --git a/boards/arm/serpente/board.cmake b/boards/arturo182/serpente/board.cmake similarity index 100% rename from boards/arm/serpente/board.cmake rename to boards/arturo182/serpente/board.cmake diff --git a/boards/arturo182/serpente/board.yml b/boards/arturo182/serpente/board.yml new file mode 100644 index 00000000000..e5775329a06 --- /dev/null +++ b/boards/arturo182/serpente/board.yml @@ -0,0 +1,5 @@ +board: + name: serpente + vendor: solderparty + socs: + - name: samd21e18a diff --git a/boards/arm/serpente/doc/img/serpente.jpg b/boards/arturo182/serpente/doc/img/serpente.jpg similarity index 100% rename from boards/arm/serpente/doc/img/serpente.jpg rename to boards/arturo182/serpente/doc/img/serpente.jpg diff --git a/boards/arturo182/serpente/doc/index.rst b/boards/arturo182/serpente/doc/index.rst new file mode 100644 index 00000000000..4b6bf5e7390 --- /dev/null +++ b/boards/arturo182/serpente/doc/index.rst @@ -0,0 +1,125 @@ +.. _serpente: + +Arturo182 Serpente +################## + +Overview +******** + +The Serpente is a very small low-cost development and prototyping +board equipped with 4MiB flash storage, a PWM enabled RGB led and 6 I/O pins. +The board comes with 3 different USB connector options: USB Type-C plug, +USB Type-C socket and USB Type-A plug. + +.. image:: img/serpente.jpg + :align: center + :alt: Serpente Boards + +Hardware +******** + +- ATSAMD21E18A ARM Cortex-M0+ processor at 48 MHz +- 256 KiB flash memory and 32 KiB of RAM +- Extra 4MiB SPI flash memory +- RGB User LED +- Reset button +- Native USB port + +Supported Features +================== + +The Serpente board configuration supports the +following hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/arturo182/serpente/serpente_defconfig`. + +Connections and IOs +=================== + +The `Serpente documentation`_ has detailed information about the board +including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD21 MCU is configured to use the 8MHz internal oscillator +with the on-chip PLL generating the 48 MHz system clock. + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which prints "Hello World!" +to the host PC. + +Programming and Debugging +========================= + +The Serpente ships the BOSSA compatible UF2 bootloader. The bootloader +can be entered by quickly tapping the reset button twice. + +Flashing +======== + +#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: serpente + :goals: build + :compact: + +#. Connect the Serpente to your host computer using USB + + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: serpente + :goals: flash + :compact: + + You should see the User LED blink. + +References +********** + +.. target-notes:: + +.. _Serpente documentation: + https://www.solder.party/docs/serpente/r2/ + +.. _pinouts: + https://www.solder.party/docs/serpente/r2/pinout/ + +.. _schematic: + https://www.solder.party/docs/serpente/r2/downloads/ diff --git a/boards/arm/atsamc21n_xpro/pre_dt_board.cmake b/boards/arturo182/serpente/pre_dt_board.cmake similarity index 100% rename from boards/arm/atsamc21n_xpro/pre_dt_board.cmake rename to boards/arturo182/serpente/pre_dt_board.cmake diff --git a/boards/arm/serpente/serpente-pinctrl.dtsi b/boards/arturo182/serpente/serpente-pinctrl.dtsi similarity index 100% rename from boards/arm/serpente/serpente-pinctrl.dtsi rename to boards/arturo182/serpente/serpente-pinctrl.dtsi diff --git a/boards/arm/serpente/serpente.dts b/boards/arturo182/serpente/serpente.dts similarity index 100% rename from boards/arm/serpente/serpente.dts rename to boards/arturo182/serpente/serpente.dts diff --git a/boards/arm/serpente/serpente.yaml b/boards/arturo182/serpente/serpente.yaml similarity index 96% rename from boards/arm/serpente/serpente.yaml rename to boards/arturo182/serpente/serpente.yaml index e93d19f463a..df7cff28db1 100644 --- a/boards/arm/serpente/serpente.yaml +++ b/boards/arturo182/serpente/serpente.yaml @@ -2,12 +2,12 @@ identifier: serpente name: SERPENTE type: mcu arch: arm -ram: 32 -flash: 256 toolchain: - zephyr - gnuarmemb - xtools +flash: 256 +ram: 32 supported: - adc - counter @@ -17,5 +17,6 @@ supported: - pwm - spi - uart + - usb - usb_device - watchdog diff --git a/boards/arturo182/serpente/serpente_defconfig b/boards/arturo182/serpente/serpente_defconfig new file mode 100644 index 00000000000..5690d6c73cd --- /dev/null +++ b/boards/arturo182/serpente/serpente_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_OSC8M=y +CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y + +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/aspeed/ast1030_evb/Kconfig.ast1030_evb b/boards/aspeed/ast1030_evb/Kconfig.ast1030_evb new file mode 100644 index 00000000000..ecae95bcd44 --- /dev/null +++ b/boards/aspeed/ast1030_evb/Kconfig.ast1030_evb @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Aspeed AST1030 evaluation board configuration +# +# Copyright (c) 2021 Aspeed Technology Inc. + +config BOARD_AST1030_EVB + select SOC_AST1030 diff --git a/boards/arm/ast1030_evb/ast1030_evb.dts b/boards/aspeed/ast1030_evb/ast1030_evb.dts similarity index 100% rename from boards/arm/ast1030_evb/ast1030_evb.dts rename to boards/aspeed/ast1030_evb/ast1030_evb.dts diff --git a/boards/arm/ast1030_evb/ast1030_evb.yaml b/boards/aspeed/ast1030_evb/ast1030_evb.yaml similarity index 100% rename from boards/arm/ast1030_evb/ast1030_evb.yaml rename to boards/aspeed/ast1030_evb/ast1030_evb.yaml diff --git a/boards/arm/ast1030_evb/ast1030_evb_defconfig b/boards/aspeed/ast1030_evb/ast1030_evb_defconfig similarity index 92% rename from boards/arm/ast1030_evb/ast1030_evb_defconfig rename to boards/aspeed/ast1030_evb/ast1030_evb_defconfig index 62278d44213..aa48ee095f7 100644 --- a/boards/arm/ast1030_evb/ast1030_evb_defconfig +++ b/boards/aspeed/ast1030_evb/ast1030_evb_defconfig @@ -2,7 +2,7 @@ # # Copyright (c) 2021 Aspeed Technology Inc. # -CONFIG_SOC_SERIES_AST10X0=y + CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 CONFIG_MAIN_STACK_SIZE=4096 CONFIG_FLASH_SIZE=0 diff --git a/boards/aspeed/ast1030_evb/board.yml b/boards/aspeed/ast1030_evb/board.yml new file mode 100644 index 00000000000..e129a899425 --- /dev/null +++ b/boards/aspeed/ast1030_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: ast1030_evb + vendor: aspeed + socs: + - name: ast1030 diff --git a/boards/arm/ast1030_evb/doc/ast1030_evb.jpg b/boards/aspeed/ast1030_evb/doc/ast1030_evb.jpg similarity index 100% rename from boards/arm/ast1030_evb/doc/ast1030_evb.jpg rename to boards/aspeed/ast1030_evb/doc/ast1030_evb.jpg diff --git a/boards/aspeed/ast1030_evb/doc/index.rst b/boards/aspeed/ast1030_evb/doc/index.rst new file mode 100644 index 00000000000..fb7d83d074b --- /dev/null +++ b/boards/aspeed/ast1030_evb/doc/index.rst @@ -0,0 +1,93 @@ +.. _ast1030_evb: + +AST1030_EVB +################### + +Overview +******** + +The AST1030_EVB kit is a development platform to evaluate the +Aspeed AST10x0 series SOCs. This board needs to be mated with +part number AST1030. + +.. image:: ast1030_evb.jpg + :align: center + :alt: AST1030 Evaluation Board + +Hardware +******** + +- ARM Cortex-M4F Processor +- 768 KB on-chip SRAM for instruction and data memory +- 1 MB on-chip Flash memory for boot ROM and data storage +- SPI interface +- UART interface +- I2C/I3C interface +- FAN PWM interface +- ADC interface +- JTAG interface +- USB interface +- LPC interface +- eSPI interface + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in +:zephyr_file:`boards/aspeed/ast1030_evb/ast1030_evb_defconfig` + + +Connections and IOs +=================== + +Aspeed to provide the schematic for this board. + +System Clock +============ + +The AST1030 SOC is configured to use external 25MHz clock input to generate 200Mhz system clock by +the on-chip PLL. + +Serial Port +=========== + +UART5 is configured for serial logs. The default serial setup is 115200 8N1. + + +Programming and Debugging +************************* + +This board comes with a JTAG port which facilitates debugging using a single physical connection. + +Flashing +======== + +Build application as usual for the ``ast1030_evb`` board, and flash +using SF100 SPI Flash programmer. See the +`Aspeed Zephyr SDK User Guide`_ for more information. + + +Debugging +========= + +Use JTAG or SWD with a J-Link + +References +********** +.. target-notes:: + +.. _Aspeed Zephyr SDK User Guide: + https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.01.03/Aspeed_Zephy_SDK_User_Guide_v00.01.03.pdf diff --git a/boards/aspeed/index.rst b/boards/aspeed/index.rst new file mode 100644 index 00000000000..3647c2f2101 --- /dev/null +++ b/boards/aspeed/index.rst @@ -0,0 +1,10 @@ +.. _boards-aspeed: + +ASPEED Technology Inc. +###################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/degu_evk/Kconfig b/boards/atmark_techno/degu_evk/Kconfig similarity index 100% rename from boards/arm/degu_evk/Kconfig rename to boards/atmark_techno/degu_evk/Kconfig diff --git a/boards/atmark_techno/degu_evk/Kconfig.defconfig b/boards/atmark_techno/degu_evk/Kconfig.defconfig new file mode 100644 index 00000000000..286008a36ab --- /dev/null +++ b/boards/atmark_techno/degu_evk/Kconfig.defconfig @@ -0,0 +1,33 @@ +# Degu Evaluation Kit configuration + +# Copyright (c) 2019 Atmark Techno, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_DEGU_EVK + +if USB_DEVICE_STACK + +config USB_DEVICE_PRODUCT + default "Degu Evaluation Kit" + +config UART_INTERRUPT_DRIVEN + default y + +config UART_LINE_CTRL + default y + +endif # USB_DEVICE_STACK + +if LOG + +# Logger cannot use itself to log +config USB_CDC_ACM_LOG_LEVEL + default 0 + +# Set USB log level to error only +config USB_DEVICE_LOG_LEVEL + default 1 + +endif # LOG + +endif # BOARD_DEGU_EVK diff --git a/boards/atmark_techno/degu_evk/Kconfig.degu_evk b/boards/atmark_techno/degu_evk/Kconfig.degu_evk new file mode 100644 index 00000000000..b9cea5477f5 --- /dev/null +++ b/boards/atmark_techno/degu_evk/Kconfig.degu_evk @@ -0,0 +1,7 @@ +# Degu Evaluation Kit configuration + +# Copyright (c) 2019 Atmark Techno, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DEGU_EVK + select SOC_NRF52840_QIAA diff --git a/boards/arm/degu_evk/board.cmake b/boards/atmark_techno/degu_evk/board.cmake similarity index 100% rename from boards/arm/degu_evk/board.cmake rename to boards/atmark_techno/degu_evk/board.cmake diff --git a/boards/atmark_techno/degu_evk/board.yml b/boards/atmark_techno/degu_evk/board.yml new file mode 100644 index 00000000000..19859fc1e7d --- /dev/null +++ b/boards/atmark_techno/degu_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: degu_evk + vendor: atmarktechno + socs: + - name: nrf52840 diff --git a/boards/arm/degu_evk/degu_evk-pinctrl.dtsi b/boards/atmark_techno/degu_evk/degu_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/degu_evk/degu_evk-pinctrl.dtsi rename to boards/atmark_techno/degu_evk/degu_evk-pinctrl.dtsi diff --git a/boards/arm/degu_evk/degu_evk.dts b/boards/atmark_techno/degu_evk/degu_evk.dts similarity index 100% rename from boards/arm/degu_evk/degu_evk.dts rename to boards/atmark_techno/degu_evk/degu_evk.dts diff --git a/boards/arm/degu_evk/degu_evk.yaml b/boards/atmark_techno/degu_evk/degu_evk.yaml similarity index 100% rename from boards/arm/degu_evk/degu_evk.yaml rename to boards/atmark_techno/degu_evk/degu_evk.yaml diff --git a/boards/atmark_techno/degu_evk/degu_evk_defconfig b/boards/atmark_techno/degu_evk/degu_evk_defconfig new file mode 100644 index 00000000000..ceed266a402 --- /dev/null +++ b/boards/atmark_techno/degu_evk/degu_evk_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable USB (for CDC ACM console) +CONFIG_USB_DEVICE_STACK=y + +# Additional board options +CONFIG_GPIO=y + +# Required to enable 3V3 power rail and Vin1 monitor +CONFIG_REGULATOR=y diff --git a/boards/arm/degu_evk/doc/img/degu_evk.jpg b/boards/atmark_techno/degu_evk/doc/img/degu_evk.jpg similarity index 100% rename from boards/arm/degu_evk/doc/img/degu_evk.jpg rename to boards/atmark_techno/degu_evk/doc/img/degu_evk.jpg diff --git a/boards/arm/degu_evk/doc/index.rst b/boards/atmark_techno/degu_evk/doc/index.rst similarity index 100% rename from boards/arm/degu_evk/doc/index.rst rename to boards/atmark_techno/degu_evk/doc/index.rst diff --git a/boards/arm/bl652_dvk/pre_dt_board.cmake b/boards/atmark_techno/degu_evk/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl652_dvk/pre_dt_board.cmake rename to boards/atmark_techno/degu_evk/pre_dt_board.cmake diff --git a/boards/atmark_techno/index.rst b/boards/atmark_techno/index.rst new file mode 100644 index 00000000000..f49e927fdab --- /dev/null +++ b/boards/atmark_techno/index.rst @@ -0,0 +1,10 @@ +.. _boards-atmark-techno: + +Atmark Techno +############# + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/atmel/index.rst b/boards/atmel/index.rst new file mode 100644 index 00000000000..94d1cafb403 --- /dev/null +++ b/boards/atmel/index.rst @@ -0,0 +1,10 @@ +.. _boards-atmel: + +Atmel Corporation +################# + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/atmel/sam/sam4e_xpro/Kconfig.defconfig b/boards/atmel/sam/sam4e_xpro/Kconfig.defconfig new file mode 100644 index 00000000000..f5e3a93e0c0 --- /dev/null +++ b/boards/atmel/sam/sam4e_xpro/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING diff --git a/boards/atmel/sam/sam4e_xpro/Kconfig.sam4e_xpro b/boards/atmel/sam/sam4e_xpro/Kconfig.sam4e_xpro new file mode 100644 index 00000000000..d545050aa90 --- /dev/null +++ b/boards/atmel/sam/sam4e_xpro/Kconfig.sam4e_xpro @@ -0,0 +1,5 @@ +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAM4E_XPRO + select SOC_SAM4E16E diff --git a/boards/arm/sam4e_xpro/board.cmake b/boards/atmel/sam/sam4e_xpro/board.cmake similarity index 100% rename from boards/arm/sam4e_xpro/board.cmake rename to boards/atmel/sam/sam4e_xpro/board.cmake diff --git a/boards/atmel/sam/sam4e_xpro/board.yml b/boards/atmel/sam/sam4e_xpro/board.yml new file mode 100644 index 00000000000..017a22d62cd --- /dev/null +++ b/boards/atmel/sam/sam4e_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: sam4e_xpro + vendor: atmel + socs: + - name: sam4e16e diff --git a/boards/arm/sam4e_xpro/doc/img/sam4e_xpro.jpg b/boards/atmel/sam/sam4e_xpro/doc/img/sam4e_xpro.jpg similarity index 100% rename from boards/arm/sam4e_xpro/doc/img/sam4e_xpro.jpg rename to boards/atmel/sam/sam4e_xpro/doc/img/sam4e_xpro.jpg diff --git a/boards/atmel/sam/sam4e_xpro/doc/index.rst b/boards/atmel/sam/sam4e_xpro/doc/index.rst new file mode 100644 index 00000000000..18d0836c6d6 --- /dev/null +++ b/boards/atmel/sam/sam4e_xpro/doc/index.rst @@ -0,0 +1,201 @@ +.. _sam4e_xpro: + +SAM4E Xplained Pro +################### + +Overview +******** + +The SAM4E Xplained Pro evaluation kit is a development platform to evaluate the +Atmel SAM4E series microcontrollers. + +.. image:: img/sam4e_xpro.jpg + :align: center + :alt: SAM4E Xplained Pro + +Hardware +******** + +- ATSAM4E16E ARM Cortex-M4F Processor +- 12 MHz crystal oscillator +- internal 32.768 kHz crystal oscillator +- 2 x IS61WV5128BLL 4Mb SRAM +- MT29F2G08ABAEAWP 2Gb NAND +- SD card connector +- CAN-bus (TLE7250GVIOXUMA1 CAN Transceiver) +- Ethernet port (KSZ8081MNXIA phy) +- Micro-AB USB device +- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data + Gateway Interface (DGI) +- One reset and one user pushbutton +- 1 yellow user LEDs + + +Supported Features +================== + +The sam4e_xpro board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| AFEC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | hwinfo | ++-----------+------------+-------------------------------------+ +| HSMCI | on-chip | sdhc | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam/sam4e_xpro/sam4e_xpro_defconfig`. + +Connections and IOs +=================== + +The `SAM4E Xplained Pro User Guide`_ has detailed information about board +connections. Download the `SAM4E Xplained Pro documentation`_ for more detail. + +System Clock +============ + +The SAM4E MCU is configured to use the 12 MHz internal oscillator on the board +with the on-chip PLL to generate an 120 MHz system clock. + +Serial Port +=========== + +The ATSAM4E16E MCU has 2 UARTs and 2 USARTs. One of the UARTs (UART0) is +configured for the console and is available as a Virtual COM Port by EDBG USB +chip. + +Programming and Debugging +************************* + +Flashing the Zephyr project onto SAM4E MCU requires the `OpenOCD tool`_. +By default a factory new SAM4E chip will boot SAM-BA boot loader located in +the ROM, not the flashed image. This is determined by the value of GPNVM1 +(General-Purpose NVM bit 1). The flash procedure will ensure that GPNVM1 is +set to 1 changing the default behavior to boot from Flash. + +If your chip has a security bit GPNVM0 set you will be unable to program flash +memory or connect to it via a debug interface. The only way to clear GPNVM0 +is to perform a chip erase procedure that will erase all GPNVM bits and the full +contents of the SAM4E flash memory: + +- With the board power off, set a jumper on the J304 header. +- Turn the board power on. The jumper can be removed soon after the power is on + (flash erasing procedure is started when the erase line is asserted for at + least 230ms) + +Flashing +======== + +For flash the board Zephyr provides two paths. One uses the default OpenOCD +tool and the second one uses :ref:`atmel_sam_ba_bootloader`. + +Using OpenOCD +------------- + +#. Connect the SAM4E Xplained Pro board to your host computer using the USB + debug port. Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4e_xpro + :goals: build flash + +Using SAM-BA bootloader +----------------------- + +#. Close the ``ERASE`` jumper on the SAM4E Xplained Pro board. Power on the + board for 10s. + +#. Open the ``ERASE`` jumper. + +#. Connect the SAM4E Xplained Pro board to your host computer using the SoC + USB port. Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4e_xpro + :goals: build + + .. code-block:: console + + $ west flash -r bossac + +Visualizing the message +----------------------- + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Press reset button + + You should see "Hello World! sam4e_xpro" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4e_xpro + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _SAM4E Xplained Pro User Guide: + http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42216-SAM4E-Xplained-Pro_User-Guide.pdf + +.. _SAM4E Xplained Pro documentation: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAM4E-Xplained-Pro_Design-Documentation.zip + +.. _OpenOCD tool: + http://openocd.org/ + +.. _SAM-BA: + https://www.microchip.com/developmenttools/ProductDetails/PartNO/SAM-BA%20In-system%20Programmer diff --git a/boards/arm/sam4e_xpro/sam4e_xpro-pinctrl.dtsi b/boards/atmel/sam/sam4e_xpro/sam4e_xpro-pinctrl.dtsi similarity index 96% rename from boards/arm/sam4e_xpro/sam4e_xpro-pinctrl.dtsi rename to boards/atmel/sam/sam4e_xpro/sam4e_xpro-pinctrl.dtsi index fb19be497ca..29f51f1e13c 100644 --- a/boards/arm/sam4e_xpro/sam4e_xpro-pinctrl.dtsi +++ b/boards/atmel/sam/sam4e_xpro/sam4e_xpro-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Gerson Fernando Budke + * Copyright (c) 2022-2024, Gerson Fernando Budke * SPDX-License-Identifier: Apache-2.0 */ @@ -105,5 +105,4 @@ ; }; }; - }; diff --git a/boards/arm/sam4e_xpro/sam4e_xpro.dts b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts similarity index 100% rename from boards/arm/sam4e_xpro/sam4e_xpro.dts rename to boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts diff --git a/boards/arm/sam4e_xpro/sam4e_xpro.yaml b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.yaml similarity index 76% rename from boards/arm/sam4e_xpro/sam4e_xpro.yaml rename to boards/atmel/sam/sam4e_xpro/sam4e_xpro.yaml index 76ca997b1a0..561b06b8afe 100644 --- a/boards/arm/sam4e_xpro/sam4e_xpro.yaml +++ b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.yaml @@ -6,11 +6,19 @@ toolchain: - zephyr - gnuarmemb - xtools +flash: 1024 +ram: 128 supported: - - netif:eth + - adc + - counter - gpio - - spi + - hwinfo + - i2c + - netif:eth + - pwm - sdhc + - spi + - uart - watchdog - xpro_gpio - xpro_i2c diff --git a/boards/atmel/sam/sam4e_xpro/sam4e_xpro_defconfig b/boards/atmel/sam/sam4e_xpro/sam4e_xpro_defconfig new file mode 100644 index 00000000000..cf189ca136b --- /dev/null +++ b/boards/atmel/sam/sam4e_xpro/sam4e_xpro_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam4e_xpro/support/openocd.cfg b/boards/atmel/sam/sam4e_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/sam4e_xpro/support/openocd.cfg rename to boards/atmel/sam/sam4e_xpro/support/openocd.cfg diff --git a/boards/atmel/sam/sam4l_ek/Kconfig.sam4l_ek b/boards/atmel/sam/sam4l_ek/Kconfig.sam4l_ek new file mode 100644 index 00000000000..be93be83111 --- /dev/null +++ b/boards/atmel/sam/sam4l_ek/Kconfig.sam4l_ek @@ -0,0 +1,5 @@ +# Copyright (c) 2020-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAM4L_EK + select SOC_SAM4LC4C diff --git a/boards/arm/sam4l_ek/board.cmake b/boards/atmel/sam/sam4l_ek/board.cmake similarity index 100% rename from boards/arm/sam4l_ek/board.cmake rename to boards/atmel/sam/sam4l_ek/board.cmake diff --git a/boards/atmel/sam/sam4l_ek/board.yml b/boards/atmel/sam/sam4l_ek/board.yml new file mode 100644 index 00000000000..7045ba351ce --- /dev/null +++ b/boards/atmel/sam/sam4l_ek/board.yml @@ -0,0 +1,5 @@ +board: + name: sam4l_ek + vendor: atmel + socs: + - name: sam4lc4c diff --git a/boards/arm/sam4l_ek/doc/img/atmel-sam4l-ek-callouts.jpg b/boards/atmel/sam/sam4l_ek/doc/img/atmel-sam4l-ek-callouts.jpg similarity index 100% rename from boards/arm/sam4l_ek/doc/img/atmel-sam4l-ek-callouts.jpg rename to boards/atmel/sam/sam4l_ek/doc/img/atmel-sam4l-ek-callouts.jpg diff --git a/boards/atmel/sam/sam4l_ek/doc/index.rst b/boards/atmel/sam/sam4l_ek/doc/index.rst new file mode 100644 index 00000000000..a28b0728836 --- /dev/null +++ b/boards/atmel/sam/sam4l_ek/doc/index.rst @@ -0,0 +1,176 @@ +.. _sam4l_ek: + +SAM4L-EK +######## + +Overview +******** + +The SAM4L series embeds picoPower technology for ultra-low power consumption. +Combined power control techniques are used to bring active current consumption +down to 90μA/MHz. The device allows a wide range of configurations giving the +user the ability to balance between the lowest possible power consumption and +the feature set selected for the application. The WAIT and RETENTION modes +provide full logic and RAM retention, associated with fast wake-up capability +(<1.5μs) and a very low consumption of, respectively, 3 μA and 1.5 μA. In +addition, WAIT mode supports SleepWalking features. In BACKUP mode, CPU, +peripherals and RAM are powered off consuming less than 0.9μA with external +interrupt wake-up support. + +The SAM4L-EK is a full featured design to develop for Atmel SAM4L SoC series. +The kit is equipped with a rich set of peripherals that make the ATSAM4L-EK a +perfect evaluation platform. Download the `SAM4L-EK Online User Guide`_ for +more details. + +.. image:: img/atmel-sam4l-ek-callouts.jpg + :align: center + :alt: SAM4L-EK + +Hardware +******** + +- ATSAM4LC4C ARM Cortex-M4 Processor +- 12 MHz crystal oscillator +- 32.768 kHz crystal oscillator +- 1 Micro-AB USB OTG host/device +- 1 AT86RF2xx IEEE 802.15.4 transceiver connector +- 1 RS-485 full duplex interface +- 1 Sensor Xplained board connector +- 1 Audio Jack connector 3.5mm +- 1 Dedicated Board Monitor MCU + + - Power measurement (VDDIN, VDDIO, VDDANA) + - 1 OLED Display (128x64) + - 5 LEDs + - 1 Joystick + - 1 USART + - 1 TWI +- 1 40x4 LCD Segment Display +- 1 user touch button and One user pushbutton +- 1 user LED +- 1 QTouch Slider +- 1 QTouch Button +- 1 TEMT6000 Light Sensor +- 1 AT25DF641A Serial NOR Flash + +Supported Features +================== + +The sam4l_ek board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique 120 bit serial number | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| TWIM | on-chip | i2c master port-interrupt | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb device | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig`. + +Connections and IOs +=================== + +The `SAM4L-EK Design Documentation`_ has detailed information about board +connections. Download the `SAM4L-EK Design Documentation`_ for more details. + +System Clock +============ + +The SAM4L MCU is configured to use the 12 MHz internal oscillator on the board +with the on-chip PLL to generate an 48 MHz system clock. + +Serial Port +=========== + +The ATSAM4LC4C MCU has 4 USARTs. One of the USARTs (USART2) is connected on +the embedded debug unit and can works as a console. The USART0 is shared +between all others headers and RS-485 port. + +Programming and Debugging +************************* + +The SAM4L-EK board have a Segger Embedded Debugger Unit +`J-Link OB `_. This provides a debug +interface to the SAM4LC4C chip. You can use Ozone or JLink to communicate with +the SAM4LC4C. + +Flashing +======== + +#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section + "J-Link Software and Documentation Pack" and install the "J-Link Software + and Documentation pack for Linux". The application JLinkExe needs to be + accessible from your path. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the SAM4L-EK board to your host computer using the USB debug port. + Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4l_ek + :goals: build flash + + You should see "Hello World! sam4l_ek" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4l_ek + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _SAM4L-EK Online User Guide: + http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42026-ATSAM4L-EK-User-Guide_ApplicationNote_AVR32850.pdf + +.. _SAM4L-EK Design Documentation: + http://ww1.microchip.com/downloads/en/DeviceDoc/doc42027_SAM4L-EK_Design_Documentation.PDF + +.. _JLink Downloads Page: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/sam4l_ek/sam4l_ek-pinctrl.dtsi b/boards/atmel/sam/sam4l_ek/sam4l_ek-pinctrl.dtsi similarity index 100% rename from boards/arm/sam4l_ek/sam4l_ek-pinctrl.dtsi rename to boards/atmel/sam/sam4l_ek/sam4l_ek-pinctrl.dtsi diff --git a/boards/arm/sam4l_ek/sam4l_ek.dts b/boards/atmel/sam/sam4l_ek/sam4l_ek.dts similarity index 100% rename from boards/arm/sam4l_ek/sam4l_ek.dts rename to boards/atmel/sam/sam4l_ek/sam4l_ek.dts diff --git a/boards/arm/sam4l_ek/sam4l_ek.yaml b/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml similarity index 78% rename from boards/arm/sam4l_ek/sam4l_ek.yaml rename to boards/atmel/sam/sam4l_ek/sam4l_ek.yaml index cdadbee508a..f33959c7805 100644 --- a/boards/arm/sam4l_ek/sam4l_ek.yaml +++ b/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml @@ -2,16 +2,20 @@ identifier: sam4l_ek name: SAM4L-EK type: mcu arch: arm -flash: 256 -ram: 32 toolchain: - zephyr - gnuarmemb - xtools +flash: 256 +ram: 32 supported: + - counter - gpio + - entropy + - hwinfo - i2c - spi - - usart + - uart + - usb - usb_device vendor: atmel diff --git a/boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig b/boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig new file mode 100644 index 00000000000..6c902f537d7 --- /dev/null +++ b/boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/atmel/sam/sam4s_xplained/Kconfig.sam4s_xplained b/boards/atmel/sam/sam4s_xplained/Kconfig.sam4s_xplained new file mode 100644 index 00000000000..08f005f16d0 --- /dev/null +++ b/boards/atmel/sam/sam4s_xplained/Kconfig.sam4s_xplained @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAM4S_XPLAINED + select SOC_SAM4S16C diff --git a/boards/arm/sam4s_xplained/board.cmake b/boards/atmel/sam/sam4s_xplained/board.cmake similarity index 100% rename from boards/arm/sam4s_xplained/board.cmake rename to boards/atmel/sam/sam4s_xplained/board.cmake diff --git a/boards/atmel/sam/sam4s_xplained/board.yml b/boards/atmel/sam/sam4s_xplained/board.yml new file mode 100644 index 00000000000..c406301245b --- /dev/null +++ b/boards/atmel/sam/sam4s_xplained/board.yml @@ -0,0 +1,5 @@ +board: + name: sam4s_xplained + vendor: atmel + socs: + - name: sam4s16c diff --git a/boards/arm/sam4s_xplained/doc/img/sam4s_xplained.jpg b/boards/atmel/sam/sam4s_xplained/doc/img/sam4s_xplained.jpg similarity index 100% rename from boards/arm/sam4s_xplained/doc/img/sam4s_xplained.jpg rename to boards/atmel/sam/sam4s_xplained/doc/img/sam4s_xplained.jpg diff --git a/boards/atmel/sam/sam4s_xplained/doc/index.rst b/boards/atmel/sam/sam4s_xplained/doc/index.rst new file mode 100644 index 00000000000..9c1b999eca9 --- /dev/null +++ b/boards/atmel/sam/sam4s_xplained/doc/index.rst @@ -0,0 +1,190 @@ +.. _sam4s_xplained: + +SAM4S Xplained +############## + +Overview +******** + +The SAM4S Xplained evaluation kit is a development platform to evaluate the +Atmel SAM4S series microcontrollers. + +.. image:: img/sam4s_xplained.jpg + :align: center + :alt: SAM4S Xplained + +Hardware +******** + +- ATSAM4S16C ARM Cortex-M4 Processor +- 12 MHz crystal oscillator +- internal 32.768 kHz crystal oscillator +- IS66WV51216DALL 8 Mb SRAM +- Micro-AB USB device +- Micro-AB USB debug interface supporting SEGGER OB and Virtual COM Port and + Data +- One reset and one user pushbutton +- 2 yellow user LEDs +- IC pads for external flash chip + +Supported Features +================== + +The sam4s_xplained board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| SMC | on-chip | memc (PSRAM) | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam/sam4s_xplained/sam4s_xplained_defconfig`. + +Connections and IOs +=================== + +Download the `SAM4S Xplained Design Files`_ for more information. It has +full schematic and gerbers files. + +System Clock +============ + +The SAM4S MCU is configured to use the 12 MHz internal oscillator on the board +with the on-chip PLL to generate an 84 MHz system clock. + +Serial Port +=========== + +The ATSAM4S16C MCU has 2 UARTs and 2 USARTs. One of the UARTs (UART0) is +connected to the Segger J-Link OB chip (the AT91SAM3U4 is programmed to be +Segger J-Link OB). Segger J-Link OB brings the UART out as a virtual COM port. +The section flashing uses the UART from the Segger USB debug connection. + +Programming and Debugging +************************* + +The SAM4S Xplained board comes with Segger +`J-Link OB `_. This provides a debug +interface to the SAM4S16C chip. You can use Ozone or JLink to communicate with +the SAM4S16C. + +Flashing +======== + +For flash the board Zephyr provides two paths. One uses the default JLink +tool and the second one uses :ref:`atmel_sam_ba_bootloader`. + +Using JLink +------------- + +#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section + "J-Link Software and Documentation Pack" and install the "J-Link Software + and Documentation pack for Linux". The application JLinkExe needs to be + accessible from your path. + +#. Connect the SAM4S Xplained board to your host computer using the USB debug + port. Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4s_xplained + :goals: build flash + + +Using SAM-BA bootloader +----------------------- + +#. Close the ``J25`` jumper on the SAM4S Xplained board. Power on the board + for 10s. + +#. Open the ``J25`` jumper. + +#. Connect the SAM4S Xplained board to your host computer using the SoC USB + port. Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4s_xplained + :goals: build + + .. code-block:: console + + $ west flash -r bossac + + +Visualizing the message +----------------------- + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Press reset button + + You should see "Hello World! sam4s_xplained" in your terminal. + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4s_xplained + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _SAM4S Xplained Online User Guide: + http://ww1.microchip.com/downloads/en/devicedoc/atmel-42075-sam4s-xplained-pro_user-guide.pdf + +.. _JLink Downloads Page: + https://www.segger.com/downloads/jlink + +.. _SAM4S Xplained Design Files: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAM4S-XPLD__KitsFiles.zip diff --git a/boards/arm/sam4s_xplained/sam4s_xplained-pinctrl.dtsi b/boards/atmel/sam/sam4s_xplained/sam4s_xplained-pinctrl.dtsi similarity index 100% rename from boards/arm/sam4s_xplained/sam4s_xplained-pinctrl.dtsi rename to boards/atmel/sam/sam4s_xplained/sam4s_xplained-pinctrl.dtsi diff --git a/boards/arm/sam4s_xplained/sam4s_xplained.dts b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts similarity index 100% rename from boards/arm/sam4s_xplained/sam4s_xplained.dts rename to boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts diff --git a/boards/arm/sam4s_xplained/sam4s_xplained.yaml b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.yaml similarity index 89% rename from boards/arm/sam4s_xplained/sam4s_xplained.yaml rename to boards/atmel/sam/sam4s_xplained/sam4s_xplained.yaml index 20e5949b0fe..0cc1a4f9deb 100644 --- a/boards/arm/sam4s_xplained/sam4s_xplained.yaml +++ b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.yaml @@ -6,9 +6,13 @@ toolchain: - zephyr - gnuarmemb - xtools +flash: 1024 +ram: 128 supported: - adc + - counter - gpio + - hwinfo - memc - pwm - spi @@ -17,5 +21,4 @@ supported: - xplained_i2c - xplained_serial - xplained_spi - - hwinfo vendor: atmel diff --git a/boards/atmel/sam/sam4s_xplained/sam4s_xplained_defconfig b/boards/atmel/sam/sam4s_xplained/sam4s_xplained_defconfig new file mode 100644 index 00000000000..91293d9a641 --- /dev/null +++ b/boards/atmel/sam/sam4s_xplained/sam4s_xplained_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_MEMC=y diff --git a/boards/atmel/sam/sam_e70_xplained/Kconfig.defconfig b/boards/atmel/sam/sam_e70_xplained/Kconfig.defconfig new file mode 100644 index 00000000000..59f0676d06b --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Atmel SMART SAM E70 Xplained Board configuration + +# Copyright (c) 2016 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +if ETH_SAM_GMAC + +# Read MAC address from AT24MAC402 EEPROM + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS + default 0x9A + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE + default 1 + +config ETH_SAM_GMAC_MAC_I2C_EEPROM + default y + select I2C + +endif # ETH_SAM_GMAC + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING diff --git a/boards/atmel/sam/sam_e70_xplained/Kconfig.sam_e70_xplained b/boards/atmel/sam/sam_e70_xplained/Kconfig.sam_e70_xplained new file mode 100644 index 00000000000..8cff5c27738 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/Kconfig.sam_e70_xplained @@ -0,0 +1,7 @@ +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAM_E70_XPLAINED + select SOC_SAME70Q21 if BOARD_SAM_E70_XPLAINED_SAME70Q21 + select SOC_SAME70Q21B if BOARD_SAM_E70_XPLAINED_SAME70Q21B diff --git a/boards/arm/sam_e70_xplained/board.cmake b/boards/atmel/sam/sam_e70_xplained/board.cmake similarity index 100% rename from boards/arm/sam_e70_xplained/board.cmake rename to boards/atmel/sam/sam_e70_xplained/board.cmake diff --git a/boards/atmel/sam/sam_e70_xplained/board.yml b/boards/atmel/sam/sam_e70_xplained/board.yml new file mode 100644 index 00000000000..1308363814a --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/board.yml @@ -0,0 +1,6 @@ +board: + name: sam_e70_xplained + vendor: atmel + socs: + - name: same70q21 + - name: same70q21b diff --git a/boards/arm/sam_e70_xplained/doc/img/sam_e70_xplained.jpg b/boards/atmel/sam/sam_e70_xplained/doc/img/sam_e70_xplained.jpg similarity index 100% rename from boards/arm/sam_e70_xplained/doc/img/sam_e70_xplained.jpg rename to boards/atmel/sam/sam_e70_xplained/doc/img/sam_e70_xplained.jpg diff --git a/boards/atmel/sam/sam_e70_xplained/doc/index.rst b/boards/atmel/sam/sam_e70_xplained/doc/index.rst new file mode 100644 index 00000000000..bab33f538c4 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/doc/index.rst @@ -0,0 +1,195 @@ +.. _sam_e70_xplained: + +SAM E70(B) Xplained +################### + +Overview +******** + +The SAM E70 Xplained evaluation kit is a development platform to evaluate the +Atmel SAM E70 series microcontrollers. The current version allows to use both +IC variations ATSAME70Q21A(B). + +.. image:: img/sam_e70_xplained.jpg + :align: center + :alt: SAM E70 Xplained + +Hardware +******** + +- ATSAME70Q21A(B) ARM Cortex-M7 Processor +- 12 MHz crystal oscillator +- 32.768 kHz crystal oscillator (not populated) +- AT24MAC402 EEPROM +- IS42S16100E 16 Mb SDRAM +- SD card connector +- Ethernet port +- Micro-AB USB device +- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data + Gateway Interface (DGI) +- JTAG interface connector +- One reset and one user pushbutton +- One green user LED + +Supported Features +================== + +The sam_e70_xplained board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| AFEC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CAN FD | on-chip | can | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| XDMAC | on-chip | dma | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21_defconfig`. + +Connections and IOs +=================== + +The `SAME70-XPLD User Guide`_ has detailed information about board connections. + +System Clock +============ + +The SAM E70 MCU is configured to use the 12 MHz external oscillator on the board +with the on-chip PLL to generate a 300 MHz system clock. + +Serial Port +=========== + +The ATSAME70Q21 MCU has five UARTs and three USARTs. One of the USARTs is +configured for the console and is available as a Virtual COM Port via EDBG USB +chip. + +Programming and Debugging +************************* + +Flashing the Zephyr project onto SAM E70 MCU requires the `OpenOCD tool`_. +Support for Atmel SAM E microcontroller series was added in OpenOCD release +0.10.0, which was added in Zephyr SDK 0.9.2. + +By default a factory new SAM E70 chip will boot SAM-BA boot loader located in +the ROM, not the flashed image. This is determined by the value of GPNVM1 +(General-Purpose NVM bit 1). The flash procedure will ensure that GPNVM1 is +set to 1 changing the default behavior to boot from Flash. + +If your chip has a security bit GPNVM0 set you will be unable to program flash +memory or connect to it via a debug interface. The only way to clear GPNVM0 +is to perform a chip erase procedure that will erase all GPNVM bits and the full +contents of the SAM E70 flash memory: + +- With the board power off, set a jumper on the J200 header. +- Turn the board power on. The jumper can be removed soon after the power is on + (flash erasing procedure is started when the erase line is asserted for at + least 230ms) + +Flashing +======== + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the SAM E70 Xplained board to your host computer using the + USB debug port. Then build and flash the :ref:`hello_world` + application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_e70_xplained/same70q21 + :goals: build flash + + You should see "Hello World! sam_e70_xplained" in your terminal. + +#. To use the SoC variation B IC, you need type "sam_e70_xplained/same70q21b". + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_e70_xplained/same70q21b + :goals: build flash + + You should see "Hello World! sam_e70_xplained" in your terminal. + +You can flash the image using an external debug adapter such as J-Link +or ULINK, connected to the 20-pin JTAG header. Supply the name of the +debug adapter (e.g., ``jlink``) via an OPENOCD_INTERFACE environment +variable. OpenOCD will look for the appropriate interface +configuration in an ``interface/$(OPENOCD_INTERFACE).cfg`` file on its +internal search path. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_e70_xplained/same70q21 + :maybe-skip-config: + :goals: debug + +References +********** + +SAM E70 Product Page: + http://www.atmel.com/products/microcontrollers/arm/sam-e.aspx + +.. _SAME70-XPLD User Guide: + http://www.atmel.com/Images/Atmel-44050-Cortex-M7-Microcontroller-SAM-E70-XPLD-Xplained_User-guide.pdf + +.. _OpenOCD tool: + http://openocd.org/ + +.. _SAM-BA: + http://www.atmel.com/tools/ATMELSAM-BAIN-SYSTEMPROGRAMMER.aspx diff --git a/boards/atmel/sam/sam_e70_xplained/pre_dt_board.cmake b/boards/atmel/sam/sam_e70_xplained/pre_dt_board.cmake new file mode 100644 index 00000000000..3b32c9ca518 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/pre_dt_board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - /soc/ethernet@40050000 & /soc/mdio@40050000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained-common.dtsi b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi similarity index 100% rename from boards/arm/sam_e70_xplained/sam_e70_xplained-common.dtsi rename to boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi similarity index 100% rename from boards/arm/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi rename to boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts new file mode 100644 index 00000000000..64a26cecc88 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2017 Piotr Mienkowski + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2020-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "sam_e70_xplained-common.dtsi" + +/ { + model = "Atmel SAM E70 Xplained board"; + compatible = "atmel,sam_e70_xplained", "atmel,same70q21", "atmel,same70"; +}; + +&tc0 { + status = "okay"; + compatible = "atmel,sam-tc-qdec"; + + pinctrl-0 = <&tc0_qdec_default>; + pinctrl-names = "default"; +}; + +&tc1 { + status = "disabled"; + compatible = "atmel,sam-tc-qdec"; + + pinctrl-0 = <&tc1_qdec_default>; + pinctrl-names = "default"; +}; + +&tc2 { + status = "disabled"; + compatible = "atmel,sam-tc-qdec"; + + pinctrl-0 = <&tc2_qdec_default>; + pinctrl-names = "default"; +}; + +&tc3 { + status = "disabled"; + compatible = "atmel,sam-tc-qdec"; + + pinctrl-0 = <&tc3_qdec_default>; + pinctrl-names = "default"; +}; diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml new file mode 100644 index 00000000000..e6da0170989 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml @@ -0,0 +1,26 @@ +identifier: sam_e70_xplained/same70q21 +name: SAM E70 Xplained +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 2048 +ram: 384 +supported: + - adc + - can + - counter + - dac + - dma + - gpio + - hwinfo + - i2s + - pwm + - netif:eth + - spi + - usb + - usb_device + - watchdog +vendor: atmel diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21_defconfig b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21_defconfig new file mode 100644 index 00000000000..f5404f816be --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.dts b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.dts new file mode 100644 index 00000000000..e65d9da3325 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.dts @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2020 Stephanos Ioannidis + * Copyright (c) 2020-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "sam_e70_xplained-common.dtsi" + +/ { + model = "Atmel SAM E70B Xplained board"; + compatible = "atmel,sam_e70b_xplained", "atmel,same70q21b", "atmel,same70b"; +}; diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml new file mode 100644 index 00000000000..8d15c3ae088 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml @@ -0,0 +1,26 @@ +identifier: sam_e70_xplained/same70q21b +name: SAM E70 Xplained (Revision B) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 2048 +ram: 384 +supported: + - adc + - can + - counter + - dac + - dma + - gpio + - hwinfo + - i2s + - pwm + - netif:eth + - spi + - usb + - usb_device + - watchdog +vendor: atmel diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b_defconfig b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b_defconfig new file mode 100644 index 00000000000..f5404f816be --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam_e70_xplained/support/openocd.cfg b/boards/atmel/sam/sam_e70_xplained/support/openocd.cfg similarity index 100% rename from boards/arm/sam_e70_xplained/support/openocd.cfg rename to boards/atmel/sam/sam_e70_xplained/support/openocd.cfg diff --git a/boards/atmel/sam/sam_v71_xult/Kconfig.defconfig b/boards/atmel/sam/sam_v71_xult/Kconfig.defconfig new file mode 100644 index 00000000000..5c860149dc8 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Atmel SMART SAM V71 Xplained Board configuration + +# Copyright (c) 2019 Gerson Fernando Budke +# Copyright (c) 2016 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +if ETH_SAM_GMAC + +# Read MAC address from AT24MAC402 EEPROM + +config ETH_SAM_GMAC_MAC_I2C_EEPROM + default y + select I2C + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS + default 0x9A + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE + default 1 + +endif # ETH_SAM_GMAC + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING diff --git a/boards/atmel/sam/sam_v71_xult/Kconfig.sam_v71_xult b/boards/atmel/sam/sam_v71_xult/Kconfig.sam_v71_xult new file mode 100644 index 00000000000..e84ae3fc535 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/Kconfig.sam_v71_xult @@ -0,0 +1,7 @@ +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAM_V71_XULT + select SOC_SAMV71Q21 if BOARD_SAM_V71_XULT_SAMV71Q21 + select SOC_SAMV71Q21B if BOARD_SAM_V71_XULT_SAMV71Q21B diff --git a/boards/arm/sam_v71_xult/board.cmake b/boards/atmel/sam/sam_v71_xult/board.cmake similarity index 100% rename from boards/arm/sam_v71_xult/board.cmake rename to boards/atmel/sam/sam_v71_xult/board.cmake diff --git a/boards/atmel/sam/sam_v71_xult/board.yml b/boards/atmel/sam/sam_v71_xult/board.yml new file mode 100644 index 00000000000..68996e06485 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/board.yml @@ -0,0 +1,6 @@ +board: + name: sam_v71_xult + vendor: atmel + socs: + - name: samv71q21 + - name: samv71q21b diff --git a/boards/arm/sam_v71_xult/doc/img/sam_v71_xult.jpg b/boards/atmel/sam/sam_v71_xult/doc/img/sam_v71_xult.jpg similarity index 100% rename from boards/arm/sam_v71_xult/doc/img/sam_v71_xult.jpg rename to boards/atmel/sam/sam_v71_xult/doc/img/sam_v71_xult.jpg diff --git a/boards/atmel/sam/sam_v71_xult/doc/index.rst b/boards/atmel/sam/sam_v71_xult/doc/index.rst new file mode 100644 index 00000000000..e0b5fce6c04 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/doc/index.rst @@ -0,0 +1,198 @@ +.. _sam_v71_xplained_ultra: + +SAM V71(B) Xplained Ultra +######################### + +Overview +******** + +The SAM V71 Xplained Ultra evaluation kit is a development platform to +evaluate the Atmel SAM V71 series microcontrollers. The current version +allows to use both IC variations ATSAMV71Q21A(B). + +.. image:: img/sam_v71_xult.jpg + :align: center + :alt: SAM V71 Xplained Ultra + +Hardware +******** + +- ATSAMV71Q21A(B) ARM Cortex-M7 Processor +- 12 MHz crystal oscillator +- 32.768 kHz crystal oscillator +- Supercap backup +- AT24MAC402 EEPROM +- IS42S16100E 16 Mb SDRAM +- S25FL116K 16 Mb QSPI +- WM8904 low power stereo audio codec +- ATA6561 CAN Transceiver +- SD card connector with SDIO support +- Camera interface connector +- MediaLB connector +- Ethernet port +- Micro-AB USB device +- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data + Gateway Interface (DGI) +- JTAG interface connector +- One reset and two user pushbuttons +- Two yellow user LEDs + +Supported Features +================== + +The sam_v71_xplained_ultra board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| AFEC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CAN FD | on-chip | can | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| XDMAC | on-chip | dma | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21_defconfig`. + +Connections and IOs +=================== + +The `SAMV71-XULT User Guide`_ has detailed information about board +connections. + +System Clock +============ + +The SAM V71 MCU is configured to use the 12 MHz external oscillator on the +board with the on-chip PLL to generate a 300 MHz system clock. + +Serial Port +=========== + +The ATSAMV71Q21 MCU has five UARTs and three USARTs. USART1 is configured +for the console and is available as a Virtual COM Port via EDBG USB chip. + +Programming and Debugging +************************* + +Flashing the Zephyr project onto SAM V71 MCU requires the `OpenOCD tool`_. +By default a factory new SAM V71 chip will boot the `SAM-BA`_ boot loader +located in the ROM, not the flashed image. This is determined by the value +of GPNVM1 (General-Purpose NVM bit 1). The flash procedure will ensure that +GPNVM1 is set to 1 changing the default behavior to boot from Flash. + +If your chip has a security bit GPNVM0 set you will be unable to program flash +memory or connect to it via a debug interface. The only way to clear GPNVM0 +is to perform a chip erase procedure that will erase all GPNVM bits and the +full contents of the SAM V71 flash memory: + +- With the board power off, set a jumper on the J200 header. +- Turn the board power on. The jumper can be removed soon after the power is + on (flash erasing procedure is started when the erase line is asserted for + at least 230ms) + +Flashing +======== + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the SAM V71 Xplained Ultra board to your host computer using the + USB debug port. Then build and flash the :ref:`hello_world` + application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_v71_xult/samv71q21 + :goals: build flash + + You should see "Hello World! sam_v71_xult" in your terminal. + +#. To use the SoC variation B IC, you need type "sam_v71_xult/samv71q21b". + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_v71_xult/samv71q21b + :goals: build flash + + You should see "Hello World! sam_v71_xult" in your terminal. + +You can flash the image using an external debug adapter such as J-Link +or ULINK, connected to the 20-pin JTAG header. Supply the name of the +debug adapter (e.g., ``jlink``) via an OPENOCD_INTERFACE environment +variable. OpenOCD will look for the appropriate interface +configuration in an ``interface/$(OPENOCD_INTERFACE).cfg`` file on its +internal search path. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_v71_xult/samv71q21 + :maybe-skip-config: + :goals: debug + +References +********** + +SAM V71 Product Page: + https://www.microchip.com/design-centers/32-bit/sam-32-bit-mcus/sam-v-mcus + +.. _SAMV71-XULT User Guide: + http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42408-SAMV71-Xplained-Ultra_User-Guide.pdf + +.. _OpenOCD tool: + http://openocd.org/ + +.. _SAM-BA: + https://www.microchip.com/developmenttools/ProductDetails/PartNO/SAM-BA%20In-system%20Programmer diff --git a/boards/atmel/sam/sam_v71_xult/pre_dt_board.cmake b/boards/atmel/sam/sam_v71_xult/pre_dt_board.cmake new file mode 100644 index 00000000000..3b32c9ca518 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/pre_dt_board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - /soc/ethernet@40050000 & /soc/mdio@40050000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi similarity index 100% rename from boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi rename to boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi diff --git a/boards/arm/sam_v71_xult/sam_v71_xult-pinctrl.dtsi b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi similarity index 100% rename from boards/arm/sam_v71_xult/sam_v71_xult-pinctrl.dtsi rename to boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.dts b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.dts new file mode 100644 index 00000000000..9bdcadc7946 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2017 Piotr Mienkowski + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2020-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "sam_v71_xult-common.dtsi" + +/ { + model = "Atmel SAM V71 Xplained Ultra board"; + compatible = "atmel,sam_v71_xult", "atmel,samv71q21", "atmel,samv71"; +}; diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml new file mode 100644 index 00000000000..e8b433685d0 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml @@ -0,0 +1,33 @@ +identifier: sam_v71_xult/samv71q21 +name: SAM V71 Xplained Ultra +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 2048 +ram: 384 +supported: + - adc + - arduino_gpio + - arduino_i2c + - arduino_spi + - can + - counter + - dac + - dma + - hwinfo + - gpio + - i2s + - pwm + - netif:eth + - spi + - usb + - usb_device + - watchdog + - xpro_gpio + - xpro_i2c + - xpro_serial + - xpro_spi +vendor: atmel diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21_defconfig b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21_defconfig new file mode 100644 index 00000000000..f5404f816be --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.dts b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.dts new file mode 100644 index 00000000000..f6f7f5a03eb --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.dts @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2020 Stephanos Ioannidis + * Copyright (c) 2020-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "sam_v71_xult-common.dtsi" + +/ { + model = "Atmel SAM V71B Xplained Ultra board"; + compatible = "atmel,sam_v71_xult", "atmel,samv71q21b", "atmel,samv71b"; +}; diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml new file mode 100644 index 00000000000..578359edbbe --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml @@ -0,0 +1,33 @@ +identifier: sam_v71_xult/samv71q21b +name: SAM V71 Xplained Ultra (Revision B) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 2048 +ram: 384 +supported: + - adc + - arduino_gpio + - arduino_i2c + - arduino_spi + - can + - counter + - dac + - dma + - hwinfo + - gpio + - i2s + - pwm + - netif:eth + - spi + - usb + - usb_device + - watchdog + - xpro_gpio + - xpro_i2c + - xpro_serial + - xpro_spi +vendor: atmel diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b_defconfig b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b_defconfig new file mode 100644 index 00000000000..f5404f816be --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam_v71_xult/support/openocd.cfg b/boards/atmel/sam/sam_v71_xult/support/openocd.cfg similarity index 100% rename from boards/arm/sam_v71_xult/support/openocd.cfg rename to boards/atmel/sam/sam_v71_xult/support/openocd.cfg diff --git a/boards/atmel/sam0/samc21n_xpro/Kconfig.samc21n_xpro b/boards/atmel/sam0/samc21n_xpro/Kconfig.samc21n_xpro new file mode 100644 index 00000000000..5041081eb3d --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/Kconfig.samc21n_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAMC21N_XPRO + select SOC_SAMC21N18A diff --git a/boards/arm/atsamc21n_xpro/board.cmake b/boards/atmel/sam0/samc21n_xpro/board.cmake similarity index 100% rename from boards/arm/atsamc21n_xpro/board.cmake rename to boards/atmel/sam0/samc21n_xpro/board.cmake diff --git a/boards/atmel/sam0/samc21n_xpro/board.yml b/boards/atmel/sam0/samc21n_xpro/board.yml new file mode 100644 index 00000000000..2037cde2398 --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: samc21n_xpro + vendor: atmel + socs: + - name: samc21n18a diff --git a/boards/arm/atsamc21n_xpro/doc/img/atsamc21n_xpro.jpg b/boards/atmel/sam0/samc21n_xpro/doc/img/atsamc21n_xpro.jpg similarity index 100% rename from boards/arm/atsamc21n_xpro/doc/img/atsamc21n_xpro.jpg rename to boards/atmel/sam0/samc21n_xpro/doc/img/atsamc21n_xpro.jpg diff --git a/boards/atmel/sam0/samc21n_xpro/doc/index.rst b/boards/atmel/sam0/samc21n_xpro/doc/index.rst new file mode 100644 index 00000000000..600163a00c9 --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/doc/index.rst @@ -0,0 +1,194 @@ +.. _samc21n_xpro: + +SAM C21N Xplained Pro Evaluation Kit +#################################### + +Overview +******** + +The SAM C21N Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM C21N Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. image:: img/atsamc21n_xpro.jpg + :align: center + :alt: SAMC21N-XPRO + +Hardware +******** + +- SAMC21N18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory, 32 KiB of RAM, 8KB RRW flash +- One yellow user LED +- One mechanical user push button +- One reset button +- One QTouch® button +- On-board USB based EDBG unit with serial console +- Two CAN transceivers + +Supported Features +================== + +The samc21n_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - ADC + - on-chip + - Analog to Digital Converter + * - GPIO + - on-chip + - I/O ports + * - PWM + - on-chip + - Pulse Width Modulation + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + * - CAN + - on-chip + - CAN ports + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/samc21n_xpro/samc21n_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM C21N Xplained Pro evaluation kit has 4 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM C21 Family Datasheet`_ and the `SAM C21N +Xplained Pro Schematic`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- ADC0 : PB09 +- ADC1 : PA08 +- CAN0 TX : PA24 +- CAN0 RX : PA25 +- CAN1 TX : PB14 +- CAN1 RX : PB15 +- SERCOM0 USART TX : PB24 +- SERCOM0 USART RX : PB25 +- SERCOM1 I2C SDA : PA16 +- SERCOM1 I2C SCL : PA17 +- SERCOM2 USART TX : PA12 +- SERCOM2 USART RX : PA13 +- SERCOM4 USART TX : PB10 +- SERCOM4 USART RX : PB11 +- SERCOM5 SPI MISO : PB00 +- SERCOM5 SPI MOSI : PB02 +- SERCOM5 SPI SCK : PB01 +- GPIO/PWM LED0 : PC05 + +System Clock +============ + +The SAMC21 MCU is configured to use the 32.768 kHz internal oscillator +with the on-chip internal oscillator generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMC21 MCU has eight SERCOM based USARTs with three configured as USARTs in +this BSP. SERCOM4 is the default Zephyr console. + +- SERCOM0 9600 8n1 +- SERCOM2 115200 8n1 +- SERCOM4 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAMC21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC2 instead of by GPIO. + +Programming and Debugging +************************* + +The SAM C21N Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMC21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samc21n_xpro + :goals: build + :compact: + +#. Connect the SAM C21N Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samc21n_xpro + :goals: flash + :compact: + + You should see "Hello World! samc21n_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + https://www.microchip.com/en-us/development-tool/ATSAMC21N-XPRO + +.. _SAM C21 Family Datasheet: + https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/DataSheets/SAM-C20-C21-Family-Data-Sheet-DS60001479J.pdf + +.. _SAM C21N Xplained Pro Schematic: + https://ww1.microchip.com/downloads/en/DeviceDoc/ATSAMC21N_Xplained_Pro_Design_Files.zip diff --git a/boards/arm/atsamd20_xpro/pre_dt_board.cmake b/boards/atmel/sam0/samc21n_xpro/pre_dt_board.cmake similarity index 100% rename from boards/arm/atsamd20_xpro/pre_dt_board.cmake rename to boards/atmel/sam0/samc21n_xpro/pre_dt_board.cmake diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro-pinctrl.dtsi b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsamc21n_xpro/atsamc21n_xpro-pinctrl.dtsi rename to boards/atmel/sam0/samc21n_xpro/samc21n_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.dts b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.dts new file mode 100644 index 00000000000..79ff5b90ecf --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.dts @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "samc21n_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM C21N Xplained Pro"; + compatible = "samc21n,xpro", "atmel,samc21n18a", "atmel,samc21"; + + chosen { + zephyr,console = &sercom4; + zephyr,shell-uart = &sercom4; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,canbus = &can0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + i2c-0 = &sercom1; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&portc 05 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc2 1 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&portb 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "User Button"; + zephyr,code = ; + }; + }; + +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&adc1 { + pinctrl-0 = <&adc1_default>; + pinctrl-names = "default"; +}; + +&tcc2 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + prescaler = <256>; + #pwm-cells = <2>; + + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <9600>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom0_uart_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom1_i2c_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom2_uart_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <3>; + txpo = <1>; + + pinctrl-0 = <&sercom4_uart_default>; + pinctrl-names = "default"; +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_spi_default>; + pinctrl-names = "default"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The final 16 KiB is reserved for the application. + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + storage_partition: partition@3c000 { + label = "storage"; + reg = <0x0003c000 0x00004000>; + }; + }; +}; + +&can0 { + status = "okay"; + + pinctrl-0 = <&can0_default>; + pinctrl-names = "default"; + + bus-speed = <125000>; + bus-speed-data = <1000000>; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&can1 { + pinctrl-0 = <&can1_default>; + pinctrl-names = "default"; + + bus-speed = <125000>; + bus-speed-data = <1000000>; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; diff --git a/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.yaml b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.yaml new file mode 100644 index 00000000000..428d79e1110 --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: samc21n_xpro +name: SAM C21N Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - can + - dma + - gpio + - i2c + - pwm + - spi + - uart +vendor: atmel diff --git a/boards/atmel/sam0/samc21n_xpro/samc21n_xpro_defconfig b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro_defconfig new file mode 100644 index 00000000000..73259566dbf --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamc21n_xpro/support/openocd.cfg b/boards/atmel/sam0/samc21n_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsamc21n_xpro/support/openocd.cfg rename to boards/atmel/sam0/samc21n_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/samd20_xpro/Kconfig.samd20_xpro b/boards/atmel/sam0/samd20_xpro/Kconfig.samd20_xpro new file mode 100644 index 00000000000..be7865252c7 --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/Kconfig.samd20_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2018 Sean Nyekjaer +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAMD20_XPRO + select SOC_SAMD20J18 diff --git a/boards/arm/atsamd20_xpro/board.cmake b/boards/atmel/sam0/samd20_xpro/board.cmake similarity index 100% rename from boards/arm/atsamd20_xpro/board.cmake rename to boards/atmel/sam0/samd20_xpro/board.cmake diff --git a/boards/atmel/sam0/samd20_xpro/board.yml b/boards/atmel/sam0/samd20_xpro/board.yml new file mode 100644 index 00000000000..c6c44e37830 --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: samd20_xpro + vendor: atmel + socs: + - name: samd20j18 diff --git a/boards/arm/atsamd20_xpro/doc/img/atsamd20_xpro.jpg b/boards/atmel/sam0/samd20_xpro/doc/img/atsamd20_xpro.jpg similarity index 100% rename from boards/arm/atsamd20_xpro/doc/img/atsamd20_xpro.jpg rename to boards/atmel/sam0/samd20_xpro/doc/img/atsamd20_xpro.jpg diff --git a/boards/atmel/sam0/samd20_xpro/doc/index.rst b/boards/atmel/sam0/samd20_xpro/doc/index.rst new file mode 100644 index 00000000000..b0dbff28229 --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/doc/index.rst @@ -0,0 +1,161 @@ +.. _samd20_xpro: + +SAM D20 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM D20 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM D20 Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. figure:: img/atsamd20_xpro.jpg + :width: 500px + :align: center + :alt: SAMD20-XPRO + + SAMD20-XPRO (Credit: `Microchip Technology`_) + +Hardware +******** + +- SAMD20J18 ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The samd20_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - ADC + - on-chip + - Analog to Digital Converter + * - GPIO + - on-chip + - I/O ports + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/samd20_xpro/samd20_xpro_defconfig`. + +Connections and IOs +=================== + +The `Microchip website`_ has detailed information about board +connections. Download the `SAM D20 Xplained Pro Schematic`_ for more detail. + +System Clock +============ + +The SAMD20 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMD20 MCU has 6 SERCOM based USARTs. One of the USARTs +(SERCOM3) is connected to the onboard Atmel Embedded Debugger (EDBG). +SERCOM4 is available on the EXT1 connector. + +SPI Port +======== + +The SAMD20 MCU has 6 SERCOM based SPIs. On the SAM D20 Xplained Pro, +SERCOM0 is available on the EXT1 connector. + +Programming and Debugging +************************* + +The SAM D20 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMD20 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samd20_xpro + :goals: build + :compact: + +#. Connect the SAM D20 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samd20_xpro + :goals: flash + :compact: + + You should see "Hello World! samd20_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip Technology: + https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD20-XPRO + +.. _Microchip website: + https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD20-XPRO + +.. _SAM D20 Xplained Pro Schematic: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD20-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsamd21_xpro/pre_dt_board.cmake b/boards/atmel/sam0/samd20_xpro/pre_dt_board.cmake similarity index 100% rename from boards/arm/atsamd21_xpro/pre_dt_board.cmake rename to boards/atmel/sam0/samd20_xpro/pre_dt_board.cmake diff --git a/boards/arm/atsamd20_xpro/atsamd20_xpro-pinctrl.dtsi b/boards/atmel/sam0/samd20_xpro/samd20_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsamd20_xpro/atsamd20_xpro-pinctrl.dtsi rename to boards/atmel/sam0/samd20_xpro/samd20_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/samd20_xpro/samd20_xpro.dts b/boards/atmel/sam0/samd20_xpro/samd20_xpro.dts new file mode 100644 index 00000000000..83f5df99c05 --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/samd20_xpro.dts @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2018 Sean Nyekjaer + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "samd20_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM D20 Xplained Pro"; + compatible = "samd20,xpro", "atmel,samd20j18", "atmel,samd20"; + + chosen { + zephyr,console = &sercom3; + zephyr,shell-uart = &sercom3; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &yellow_led; + sw0 = &user_button; + i2c-0 = &sercom2; + }; + + leds { + compatible = "gpio-leds"; + yellow_led: led_0 { + gpios = <&porta 14 GPIO_ACTIVE_LOW>; + label = "LED0"; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&porta 5 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&sercom0_spi_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom2_i2c_default>; + pinctrl-names = "default"; +}; + +&sercom3 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <3>; + txpo = <1>; + + pinctrl-0 = <&sercom3_uart_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom4_uart_default>; + pinctrl-names = "default"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The final 16 KiB is reserved for the application. + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + storage_partition: partition@3c000 { + label = "storage"; + reg = <0x0003c000 0x00004000>; + }; + }; +}; diff --git a/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml b/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml new file mode 100644 index 00000000000..548bd6c462a --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml @@ -0,0 +1,19 @@ +identifier: samd20_xpro +name: SAM D20 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - flash + - gpio + - i2c + - spi + - uart + - watchdog +vendor: atmel diff --git a/boards/atmel/sam0/samd20_xpro/samd20_xpro_defconfig b/boards/atmel/sam0/samd20_xpro/samd20_xpro_defconfig new file mode 100644 index 00000000000..c7f66b36c36 --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/samd20_xpro_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamd20_xpro/support/openocd.cfg b/boards/atmel/sam0/samd20_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsamd20_xpro/support/openocd.cfg rename to boards/atmel/sam0/samd20_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/samd21_xpro/Kconfig.samd21_xpro b/boards/atmel/sam0/samd21_xpro/Kconfig.samd21_xpro new file mode 100644 index 00000000000..3c1926b956e --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/Kconfig.samd21_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2018 Bryan O'Donoghue +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAMD21_XPRO + select SOC_SAMD21J18A diff --git a/boards/arm/atsamd21_xpro/board.cmake b/boards/atmel/sam0/samd21_xpro/board.cmake similarity index 100% rename from boards/arm/atsamd21_xpro/board.cmake rename to boards/atmel/sam0/samd21_xpro/board.cmake diff --git a/boards/atmel/sam0/samd21_xpro/board.yml b/boards/atmel/sam0/samd21_xpro/board.yml new file mode 100644 index 00000000000..d4fd578dd35 --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: samd21_xpro + vendor: atmel + socs: + - name: samd21j18a diff --git a/boards/arm/atsamd21_xpro/doc/img/ATSAMD21-XPRO-pinout.jpg b/boards/atmel/sam0/samd21_xpro/doc/img/ATSAMD21-XPRO-pinout.jpg similarity index 100% rename from boards/arm/atsamd21_xpro/doc/img/ATSAMD21-XPRO-pinout.jpg rename to boards/atmel/sam0/samd21_xpro/doc/img/ATSAMD21-XPRO-pinout.jpg diff --git a/boards/arm/atsamd21_xpro/doc/img/atsamd21_xpro.jpg b/boards/atmel/sam0/samd21_xpro/doc/img/atsamd21_xpro.jpg similarity index 100% rename from boards/arm/atsamd21_xpro/doc/img/atsamd21_xpro.jpg rename to boards/atmel/sam0/samd21_xpro/doc/img/atsamd21_xpro.jpg diff --git a/boards/atmel/sam0/samd21_xpro/doc/index.rst b/boards/atmel/sam0/samd21_xpro/doc/index.rst new file mode 100644 index 00000000000..f4f5bd3391d --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/doc/index.rst @@ -0,0 +1,202 @@ +.. _samd21_xpro: + +SAM D21 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM D21 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM D21 Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel's Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. figure:: img/atsamd21_xpro.jpg + :width: 500px + :align: center + :alt: SAMD21-XPRO + + SAMD21-XPRO (Credit: `Microchip Technology`_) + +Hardware +******** + +- SAMD21J18 ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The samd21_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - ADC + - on-chip + - Analog to Digital Converter + * - GPIO + - on-chip + - I/O ports + * - PWM + - on-chip + - Pulse Width Modulation + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + * - USB + - on-chip + - Universal Serial Bus device ports + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/samd21_xpro/samd21_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM D21 Xplained Pro evaluation kit has 3 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM D21 Family Datasheet`_ and the `SAM D21 +Xplained Pro Schematic`_. + +.. image:: img/ATSAMD21-XPRO-pinout.jpg + :align: center + :alt: SAMD21-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM0 USART TX : PA10 +- SERCOM0 USART RX : PA11 +- SERCOM1 USART TX : PA16 +- SERCOM1 USART RX : PA19 +- SERCOM2 I2C SDA : PA08 +- SERCOM2 I2C SCL : PA09 +- SERCOM3 USART TX : PA22 +- SERCOM3 USART RX : PA23 +- SERCOM5 SPI MISO : PB16 +- SERCOM5 SPI MOSI : PB22 +- SERCOM5 SPI SCK : PB23 +- USB DP : PA25 +- USB DM : PA24 +- GPIO SPI CS : PB17 +- GPIO/PWM LED0 : PB30 + +System Clock +============ + +The SAMD21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMD21 MCU has six SERCOM based USARTs with three configured as USARTs in +this BSP. SERCOM3 is the default Zephyr console. + +- SERCOM0 9600 8n1 +- SERCOM1 115200 8n1 +- SERCOM3 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the SAM D21 Xplained Pro, +SERCOM5 is connected to an 8 megabit SPI flash. + +Programming and Debugging +************************* + +The SAM D21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMD21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samd21_xpro + :goals: build + :compact: + +#. Connect the SAM D21 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samd21_xpro + :goals: flash + :compact: + + You should see "Hello World! samd21_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip Technology: + http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD21-XPRO + +.. _SAM D21 Family Datasheet: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAM-D21-Family-Datasheet-DS40001882C.pdf + +.. _SAM D21 Xplained Pro Schematic: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsamr21_xpro/pre_dt_board.cmake b/boards/atmel/sam0/samd21_xpro/pre_dt_board.cmake similarity index 100% rename from boards/arm/atsamr21_xpro/pre_dt_board.cmake rename to boards/atmel/sam0/samd21_xpro/pre_dt_board.cmake diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro-pinctrl.dtsi b/boards/atmel/sam0/samd21_xpro/samd21_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsamd21_xpro/atsamd21_xpro-pinctrl.dtsi rename to boards/atmel/sam0/samd21_xpro/samd21_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro.dts b/boards/atmel/sam0/samd21_xpro/samd21_xpro.dts new file mode 100644 index 00000000000..f390bc106de --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro.dts @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2018 Bryan O'Donoghue + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "samd21_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM D21 Xplained Pro"; + compatible = "samd21,xpro", "atmel,samd21j18a", "atmel,samd21"; + + chosen { + zephyr,console = &sercom3; + zephyr,shell-uart = &sercom3; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + i2c-0 = &sercom2; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&portb 30 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 0 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + /* Gives a maximum period of 1.4s */ + prescaler = <4>; + #pwm-cells = <2>; + + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <9600>; + rxpo = <3>; + txpo = <1>; + + pinctrl-0 = <&sercom0_uart_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <3>; + txpo = <0>; + + pinctrl-0 = <&sercom1_uart_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom2_i2c_default>; + pinctrl-names = "default"; +}; + +&sercom3 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom3_uart_default>; + pinctrl-names = "default"; +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_spi_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; + + pinctrl-0 = <&usb_dc_default>; + pinctrl-names = "default"; +}; diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml new file mode 100644 index 00000000000..d5e6a725003 --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml @@ -0,0 +1,26 @@ +# Copyright (c) 2018 Bryan O'Donoghue +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: samd21_xpro +name: SAM D21 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - counter + - dma + - gpio + - i2c + - pwm + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: atmel diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro_defconfig b/boards/atmel/sam0/samd21_xpro/samd21_xpro_defconfig new file mode 100644 index 00000000000..656d7033aa1 --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2018 Bryan O'Donoghue +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamd21_xpro/support/openocd.cfg b/boards/atmel/sam0/samd21_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsamd21_xpro/support/openocd.cfg rename to boards/atmel/sam0/samd21_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/same54_xpro/Kconfig.defconfig b/boards/atmel/sam0/same54_xpro/Kconfig.defconfig new file mode 100644 index 00000000000..17f73bc5ce4 --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/Kconfig.defconfig @@ -0,0 +1,28 @@ +# SAM E54 Xplained Pro board configuration +# +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if ETH_SAM_GMAC + +# Read MAC address from AT24MAC402 EEPROM + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS + default 0x9A + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE + default 1 + +config ETH_SAM_GMAC_MAC_I2C_EEPROM + default y + select I2C + +endif # ETH_SAM_GMAC + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING diff --git a/boards/atmel/sam0/same54_xpro/Kconfig.same54_xpro b/boards/atmel/sam0/same54_xpro/Kconfig.same54_xpro new file mode 100644 index 00000000000..c6d072763f8 --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/Kconfig.same54_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAME54_XPRO + select SOC_SAME54P20A diff --git a/boards/arm/atsame54_xpro/board.cmake b/boards/atmel/sam0/same54_xpro/board.cmake similarity index 100% rename from boards/arm/atsame54_xpro/board.cmake rename to boards/atmel/sam0/same54_xpro/board.cmake diff --git a/boards/atmel/sam0/same54_xpro/board.yml b/boards/atmel/sam0/same54_xpro/board.yml new file mode 100644 index 00000000000..d10fef7e7b7 --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: same54_xpro + vendor: atmel + socs: + - name: same54p20a diff --git a/boards/arm/atsame54_xpro/doc/img/ATSAME54-XPRO-pinout.jpg b/boards/atmel/sam0/same54_xpro/doc/img/ATSAME54-XPRO-pinout.jpg similarity index 100% rename from boards/arm/atsame54_xpro/doc/img/ATSAME54-XPRO-pinout.jpg rename to boards/atmel/sam0/same54_xpro/doc/img/ATSAME54-XPRO-pinout.jpg diff --git a/boards/arm/atsame54_xpro/doc/img/atsame54_xpro.jpg b/boards/atmel/sam0/same54_xpro/doc/img/atsame54_xpro.jpg similarity index 100% rename from boards/arm/atsame54_xpro/doc/img/atsame54_xpro.jpg rename to boards/atmel/sam0/same54_xpro/doc/img/atsame54_xpro.jpg diff --git a/boards/atmel/sam0/same54_xpro/doc/index.rst b/boards/atmel/sam0/same54_xpro/doc/index.rst new file mode 100644 index 00000000000..5fa1eb49e37 --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/doc/index.rst @@ -0,0 +1,230 @@ +.. _same54_xpro: + +SAM E54 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM E54 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM E54 Cortex®-M4F processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. image:: img/atsame54_xpro.jpg + :align: center + :alt: SAME54-XPRO + +Hardware +******** + +- SAME54P20A ARM Cortex-M4F processor at 120 MHz +- 32.768 kHz crystal oscillator +- 12 MHz crystal oscillator +- 1024 KiB flash memory and 256 KiB of RAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console +- One QTouch® PTC button +- 32 MiB QSPI Flash +- ATECC508 CryptoAuthentication™ device +- AT24MAC402 serial EEPROM with EUI-48™ MAC address +- Ethernet + + - RJ45 connector with built-in magnetics + - KSZ8091RNA PHY + - 10Base-T/100Base-TX IEE 802.3 compliant Ethernet transceiver + +- USB interface, host, and device +- SD/SDIO card connector + +Supported Features +================== + +The same54_xpro board configuration supports the following hardware +features: + ++---------------+------------+----------------------------+ +| Interface | Controller | Driver/Component | ++===============+============+============================+ +| ADC | on-chip | adc | ++---------------+------------+----------------------------+ +| DAC | on-chip | dac | ++---------------+------------+----------------------------+ +| DMAC | on-chip | dma | ++---------------+------------+----------------------------+ +| EEPROM | i2c | eeprom, EUI-48 MAC Address | ++---------------+------------+----------------------------+ +| EIC | on-chip | interrupt_controller | ++---------------+------------+----------------------------+ +| GMAC | on-chip | ethernet, mdio | ++---------------+------------+----------------------------+ +| GPIO | on-chip | gpio | ++---------------+------------+----------------------------+ +| MPU | on-chip | arch/arm | ++---------------+------------+----------------------------+ +| NVIC | on-chip | arch/arm | ++---------------+------------+----------------------------+ +| NVMCTRL | on-chip | flash | ++---------------+------------+----------------------------+ +| PORT | on-chip | pinctrl | ++---------------+------------+----------------------------+ +| RTC | on-chip | timer | ++---------------+------------+----------------------------+ +| SERCOM I2C | on-chip | i2c | ++---------------+------------+----------------------------+ +| SERCOM SPI | on-chip | spi | ++---------------+------------+----------------------------+ +| SERCOM USART | on-chip | serial, console | ++---------------+------------+----------------------------+ +| Serial Number | on-chip | hwinfo | ++---------------+------------+----------------------------+ +| SYSTICK | on-chip | timer | ++---------------+------------+----------------------------+ +| TC | on-chip | counter | ++---------------+------------+----------------------------+ +| TCC | on-chip | counter, pwm | ++---------------+------------+----------------------------+ +| TRNG | on-chip | entropy | ++---------------+------------+----------------------------+ +| USB | on-chip | usb | ++---------------+------------+----------------------------+ +| WDT | on-chip | watchdog | ++---------------+------------+----------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/same54_xpro/same54_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM E54 Xplained Pro evaluation kit has 4 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM D5x/E5x Family Datasheet`_ and the `SAM E54 +Xplained Pro Schematic`_. + +.. image:: img/ATSAME54-XPRO-pinout.jpg + :align: center + :alt: SAME54-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM2 USART TX : PB24 +- SERCOM2 USART RX : PB25 +- GPIO/PWM LED0 : PC18 +- GPIO SW0 : PB31 +- GMAC RMII REFCK : PA14 +- GMAC RMII TXEN : PA17 +- GMAC RMII TXD0 : PA18 +- GMAC RMII TXD1 : PA19 +- GMAC RMII CRSDV : PC20 +- GMAC RMII RXD0 : PA13 +- GMAC RMII RXD1 : PA12 +- GMAC RMII RXER : PA15 +- GMAC MDIO MDC : PC11 +- GMAC MDIO MDIO : PC12 +- SERCOM4 SPI SCK : PB26 +- SERCOM4 SPI MOSI : PB27 +- SERCOM4 SPI MISO : PB29 +- SERCOM7 I2C SDA : PD08 +- SERCOM7 I2C SCL : PD09 +- USB DP : PA25 +- USB DM : PA24 + +System Clock +============ + +The SAME54 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAME54 MCU has 8 SERCOM based USARTs with one configured as USARTs in +this BSP. SERCOM2 is the default Zephyr console. + +- SERCOM2 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAME54 MCU has 5 TCC based PWM units with up to 6 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAME54 MCU has 8 SERCOM based SPIs. + +I2C Port +======== + +The SAME54 MCU has 8 SERCOM based I2Cs. On the SAM E54 Xplained Pro, +SERCOM7 is connected to a AT24MAC402 EEPROM and a ATECC508A Crypto +Authentication device. + +Programming and Debugging +************************* + +The SAM E54 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAME54 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: same54_xpro + :goals: build + :compact: + +#. Connect the SAM E54 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: same54_xpro + :goals: flash + :compact: + + You should see "Hello World! same54_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAME54-XPRO + +.. _SAM D5x/E5x Family Datasheet: + http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf + +.. _SAM E54 Xplained Pro Schematic: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAME54-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsame54_xpro/pre_dt_board.cmake b/boards/atmel/sam0/same54_xpro/pre_dt_board.cmake similarity index 100% rename from boards/arm/atsame54_xpro/pre_dt_board.cmake rename to boards/atmel/sam0/same54_xpro/pre_dt_board.cmake diff --git a/boards/arm/atsame54_xpro/atsame54_xpro-pinctrl.dtsi b/boards/atmel/sam0/same54_xpro/same54_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsame54_xpro/atsame54_xpro-pinctrl.dtsi rename to boards/atmel/sam0/same54_xpro/same54_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro.dts b/boards/atmel/sam0/same54_xpro/same54_xpro.dts new file mode 100644 index 00000000000..f8d957727cd --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/same54_xpro.dts @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2019 Benjamin Valentin + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "same54_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM E54 Xplained Pro"; + compatible = "same54,xpro", "atmel,same54p20a", "atmel,same54"; + + chosen { + zephyr,console = &sercom2; + zephyr,shell-uart = &sercom2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &button0; + i2c-0 = &sercom7; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&portc 18 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 2 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&portb 31 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <120000000>; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + /* Gives a maximum period of 1.1s for 120MHz main clock */ + prescaler = <8>; + #pwm-cells = <2>; + + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom2_uart_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <3>; + dopo = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom4_spi_default>; + pinctrl-names = "default"; +}; + +&sercom7 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom7_i2c_default>; + pinctrl-names = "default"; + + eeprom: eeprom@5e { + compatible = "atmel,24mac402"; + reg = <0x5e>; + }; +}; + +&adc0 { + status = "okay"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; + + pinctrl-0 = <&usb_dc_default>; + pinctrl-names = "default"; +}; + +&gmac { + status = "okay"; + + pinctrl-0 = <&gmac_rmii>; + pinctrl-names = "default"; + + mac-eeprom = <&eeprom>; + phy-handle = <&phy>; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_default>; + pinctrl-names = "default"; + + phy: ethernet-phy@0 { + compatible = "ethernet-phy"; + status = "okay"; + reg = <0>; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The final 16 KiB is reserved for the application. + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + storage_partition: partition@fc000 { + label = "storage"; + reg = <0x000fc000 0x00004000>; + }; + }; +}; diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro.yaml b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml new file mode 100644 index 00000000000..1cddeeaf7ad --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: same54_xpro +name: SAM E54 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 1024 +ram: 256 +supported: + - adc + - flash + - gpio + - i2c + - netif:eth + - pwm + - spi + - uart + - usb_device +vendor: atmel diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro_defconfig b/boards/atmel/sam0/same54_xpro/same54_xpro_defconfig new file mode 100644 index 00000000000..33a48629acd --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/same54_xpro_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD5X_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsame54_xpro/support/openocd.cfg b/boards/atmel/sam0/same54_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsame54_xpro/support/openocd.cfg rename to boards/atmel/sam0/same54_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/saml21_xpro/Kconfig.saml21_xpro b/boards/atmel/sam0/saml21_xpro/Kconfig.saml21_xpro new file mode 100644 index 00000000000..465269f2d8d --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/Kconfig.saml21_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAML21_XPRO + select SOC_SAML21J18B diff --git a/boards/arm/atsaml21_xpro/board.cmake b/boards/atmel/sam0/saml21_xpro/board.cmake similarity index 100% rename from boards/arm/atsaml21_xpro/board.cmake rename to boards/atmel/sam0/saml21_xpro/board.cmake diff --git a/boards/atmel/sam0/saml21_xpro/board.yml b/boards/atmel/sam0/saml21_xpro/board.yml new file mode 100644 index 00000000000..10e2284d58b --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: saml21_xpro + vendor: atmel + socs: + - name: saml21j18b diff --git a/boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro-pinout.jpg b/boards/atmel/sam0/saml21_xpro/doc/img/atsaml21-xpro-pinout.jpg similarity index 100% rename from boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro-pinout.jpg rename to boards/atmel/sam0/saml21_xpro/doc/img/atsaml21-xpro-pinout.jpg diff --git a/boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro.jpg b/boards/atmel/sam0/saml21_xpro/doc/img/atsaml21-xpro.jpg similarity index 100% rename from boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro.jpg rename to boards/atmel/sam0/saml21_xpro/doc/img/atsaml21-xpro.jpg diff --git a/boards/atmel/sam0/saml21_xpro/doc/index.rst b/boards/atmel/sam0/saml21_xpro/doc/index.rst new file mode 100644 index 00000000000..172fa1f0826 --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/doc/index.rst @@ -0,0 +1,198 @@ + .. _saml21_xpro: + +SAM L21 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM L21 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM L21 Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. image:: img/atsaml21-xpro.jpg + :align: center + :alt: SAML21-XPRO + +Hardware +******** + +- SAML21J18 ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The saml21_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - GPIO + - on-chip + - I/O ports + * - PWM + - on-chip + - Pulse Width Modulation + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + * - TRNG + - on-chip + - True Random Number Generator + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/saml21_xpro/saml21_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM L21 Xplained Pro evaluation kit has 2 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM L21 Family Datasheet`_ and the `SAM L21 +Xplained Pro Schematic`_. + +.. image:: img/atsaml21-xpro-pinout.jpg + :align: center + :alt: SAML21-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM0 SPI MISO : PA04 +- SERCOM0 SPI MOSI : PA06 +- SERCOM0 SPI SCK : PA07 +- SERCOM1 USART TX : PA18 +- SERCOM1 USART RX : PA19 +- SERCOM2 I2C SDA : PA08 +- SERCOM2 I2C SCL : PA09 +- SERCOM3 USART TX : PA22 +- SERCOM3 USART RX : PA23 +- SERCOM4 USART TX : PB08 +- SERCOM4 USART RX : PB09 +- SERCOM5 SPI MISO : PB16 +- SERCOM5 SPI MOSI : PB22 +- SERCOM5 SPI SCK : PB23 +- USB DP : PA25 +- USB DM : PA24 +- GPIO SPI CS : PB17 +- GPIO/PWM LED0 : PB10 + +System Clock +============ + +The SAML21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAML21 MCU has six SERCOM based USARTs with two configured as USARTs in +this BSP. SERCOM3 is the default Zephyr console. + +- SERCOM1 115200 8n1 - connected to EXT2 and EXT3 +- SERCOM3 115200 8n1 - connected to the onboard Atmel Embedded Debugger (EDBG) +- SERCOM4 115200 8n1 - connected to EXT1 + +PWM +=== + +The SAML21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAML21 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. + +- SERCOM0 - connected to EXT1 +- SERCOM5 - connected to EXT2 and EXT3 + +Programming and Debugging +************************* + +The SAM L21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAML21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: saml21_xpro + :goals: build + :compact: + +#. Connect the SAM L21 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ picocom -b 115200 /dev/ttyACM0 + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: saml21_xpro + :goals: flash + :compact: + + You should see "Hello World! saml21_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + https://www.microchip.com/en-us/development-tool/atsaml21-xpro-b + +.. _SAM L21 Family Datasheet: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_L21_Family_DataSheet_DS60001477C.pdf + +.. _SAM L21 Xplained Pro Schematic: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAML21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro-pinctrl.dtsi b/boards/atmel/sam0/saml21_xpro/saml21_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsaml21_xpro/atsaml21_xpro-pinctrl.dtsi rename to boards/atmel/sam0/saml21_xpro/saml21_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/saml21_xpro/saml21_xpro.dts b/boards/atmel/sam0/saml21_xpro/saml21_xpro.dts new file mode 100644 index 00000000000..c0e0e43d666 --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/saml21_xpro.dts @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "saml21_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM L21 Xplained Pro"; + compatible = "saml21,xpro", "atmel,saml21j18b", "atmel,saml21"; + + chosen { + zephyr,console = &sercom3; + zephyr,shell-uart = &sercom3; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&portb 10 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 0 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&adc { + status = "okay"; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + /* Gives a maximum period of 1.4s */ + prescaler = <4>; + #pwm-cells = <2>; + + pinctrl-0 = <&tcc0_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom0_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <3>; + txpo = <0>; + + pinctrl-0 = <&sercom1_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom2_default>; + pinctrl-names = "default"; +}; + +&sercom3 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom3_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom4_default>; + pinctrl-names = "default"; +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; + + pinctrl-0 = <&usb0_default>; + pinctrl-names = "default"; +}; diff --git a/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml b/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml new file mode 100644 index 00000000000..3d531f66287 --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml @@ -0,0 +1,26 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: saml21_xpro +name: SAM L21 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - counter + - dma + - gpio + - i2c + - pwm + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: atmel diff --git a/boards/atmel/sam0/saml21_xpro/saml21_xpro_defconfig b/boards/atmel/sam0/saml21_xpro/saml21_xpro_defconfig new file mode 100644 index 00000000000..50125e5510d --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/saml21_xpro_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAML_XOSC32K=y +CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsaml21_xpro/support/openocd.cfg b/boards/atmel/sam0/saml21_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsaml21_xpro/support/openocd.cfg rename to boards/atmel/sam0/saml21_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/samr21_xpro/Kconfig.samr21_xpro b/boards/atmel/sam0/samr21_xpro/Kconfig.samr21_xpro new file mode 100644 index 00000000000..3f83d7d1adc --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/Kconfig.samr21_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAMR21_XPRO + select SOC_SAMR21G18A diff --git a/boards/arm/atsamr21_xpro/board.cmake b/boards/atmel/sam0/samr21_xpro/board.cmake similarity index 100% rename from boards/arm/atsamr21_xpro/board.cmake rename to boards/atmel/sam0/samr21_xpro/board.cmake diff --git a/boards/atmel/sam0/samr21_xpro/board.yml b/boards/atmel/sam0/samr21_xpro/board.yml new file mode 100644 index 00000000000..c56b60ffc6f --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: samr21_xpro + vendor: atmel + socs: + - name: samr21g18a diff --git a/boards/arm/atsamr21_xpro/doc/img/ATSAMR21-XPRO-pinout.jpg b/boards/atmel/sam0/samr21_xpro/doc/img/ATSAMR21-XPRO-pinout.jpg similarity index 100% rename from boards/arm/atsamr21_xpro/doc/img/ATSAMR21-XPRO-pinout.jpg rename to boards/atmel/sam0/samr21_xpro/doc/img/ATSAMR21-XPRO-pinout.jpg diff --git a/boards/arm/atsamr21_xpro/doc/img/atsamr21_xpro.jpg b/boards/atmel/sam0/samr21_xpro/doc/img/atsamr21_xpro.jpg similarity index 100% rename from boards/arm/atsamr21_xpro/doc/img/atsamr21_xpro.jpg rename to boards/atmel/sam0/samr21_xpro/doc/img/atsamr21_xpro.jpg diff --git a/boards/atmel/sam0/samr21_xpro/doc/index.rst b/boards/atmel/sam0/samr21_xpro/doc/index.rst new file mode 100644 index 00000000000..1172f8a3f98 --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/doc/index.rst @@ -0,0 +1,225 @@ +.. _samr21_xpro: + +SAM R21 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM R21 Xplained Pro is a compact evaluation board by Atmel featuring a +SAMR21G18A SoC. The SoC includes a SAMR21 ARM Cortex-M0+ micro-controller +bundled with Atmel's AT86RF233, a 2.4GHz IEEE802.15.4 compatible radio. +The kit includes Atmel’s Embedded Debugger (EDBG), which provides a full +debug interface without the need for additional hardware. + +.. image:: img/atsamr21_xpro.jpg + :align: center + :alt: SAMR21-XPRO + +Hardware +******** + +- SAMR21G18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The samr21_xpro board configuration supports the following hardware +features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+--------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+--------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+--------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+--------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+--------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+--------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+--------------------------------------+ +| I2C | on-chip | I2C Peripheral Interface ports | ++-----------+------------+--------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/samr21_xpro/samr21_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM R21 Xplained Pro evaluation kit has 3 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM R21 Family Datasheet`_ and the `SAM R21 +Xplained Pro Schematic`_. + +.. image:: img/ATSAMR21-XPRO-pinout.jpg + :align: center + :alt: SAMR21-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM0 USART TX : PA5 +- SERCOM0 USART RX : PA4 +- SERCOM1 I2C SDA : PA16 +- SERCOM1 I2C SCL : PA17 +- SERCOM5 SPI MISO : PB02 +- SERCOM5 SPI MOSI : PB22 +- SERCOM5 SPI SCK : PB23 +- GPIO SPI CS : PB03 +- GPIO/PWM LED0 : PA19 + +System Clock +============ + +The SAMR21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMR21 MCU has six SERCOM based USARTs with two configured as USARTs in +this BSP. SERCOM0 is the default Zephyr console. + +- SERCOM0 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAMR21 MCU has 3 TCC based PWM units with up to 4 outputs each and a +period of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then +LED0 is driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAMR21 MCU has 6 SERCOM based SPIs. + +- SERCOM5 is exposed via Xplained Pro Standard Extension Header + +I2C Port +======== + +When connecting an I2C device and a logic analyzer to an I2C port at the same +time, the internal pull-up resistors are not sufficient for stable bus +operation. You probably have to connect external pull-ups to both bus lines. 10K +is a good value to start with. + +- SERCOM1 is exposed via Xplained Pro Standard Extension Header + +Radio +===== + +The SAMR21 SoC includes an on-chip AT86RF233 radio. It is internally +connected via SPI and some GPIO pins and behaves the same way as +externally connected SPI devices. + ++-------------+------------------------------------------------------------------------------------------+ +| Sensor | AT86RF233 | ++=============+==========================================================================================+ +| Type | 2.4GHz IEEE802.15.4 radio | ++-------------+------------------------------------------------------------------------------------------+ +| Vendor | Atmel | ++-------------+------------------------------------------------------------------------------------------+ +| Datasheet |`Datasheet `_| ++-------------+------------------------------------------------------------------------------------------+ +| connected to| SPI_0 | ++-------------+------------------------------------------------------------------------------------------+ +| Pin Config: | ++-------------+------------------------------------------------------------------------------------------+ +| Device | SERCOM4 | ++-------------+------------------------------------------------------------------------------------------+ +| MOSI | PB30 (OUT, SPI MOSI) | ++-------------+------------------------------------------------------------------------------------------+ +| MISO | PC19 (IN, SPI MISO) | ++-------------+------------------------------------------------------------------------------------------+ +| SCLK | PC18 (OUT, SPI SCLK) | ++-------------+------------------------------------------------------------------------------------------+ +| CS | PB31 (OUT, GPIO output) | ++-------------+------------------------------------------------------------------------------------------+ +| IRQ | PB00 (IN, GPIO external interrupt) | ++-------------+------------------------------------------------------------------------------------------+ +| RSTN | PB15 (OUT, GPIO output) | ++-------------+------------------------------------------------------------------------------------------+ +| SLP_TR | PA20 (OUT, GPIO output) | ++-------------+------------------------------------------------------------------------------------------+ + +Zephyr provide several samples that can use this technology. You can check +:zephyr:code-sample:`wpan-usb` and :zephyr:code-sample:`wpan-serial` examples as starting +points. Another good test can be done with IPv6 by using the server/client +echo demo. More information at :zephyr:code-sample:`sockets-echo-server` and +:zephyr:code-sample:`sockets-echo-client`. + +Programming and Debugging +************************* + +The SAM R21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMR21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samr21_xpro + :goals: build + :compact: + +#. Connect the SAM R21 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samr21_xpro + :goals: flash + :compact: + + You should see "Hello World! samr21_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMR21-XPRO + +.. _SAM R21 Family Datasheet: + http://ww1.microchip.com/downloads/en/devicedoc/sam-r21_datasheet.pdf + +.. _SAM R21 Xplained Pro Schematic: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAMR21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/atmel/sam0/samr21_xpro/pre_dt_board.cmake b/boards/atmel/sam0/samr21_xpro/pre_dt_board.cmake new file mode 100644 index 00000000000..62686b6896c --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/pre_dt_board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via sercom so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - /soc/pinmux@41004400 & /soc/gpio@41004400 +# - /soc/pinmux@41004480 & /soc/gpio@41004480 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/atsamr21_xpro/atsamr21_xpro-pinctrl.dtsi b/boards/atmel/sam0/samr21_xpro/samr21_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsamr21_xpro/atsamr21_xpro-pinctrl.dtsi rename to boards/atmel/sam0/samr21_xpro/samr21_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts b/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts new file mode 100644 index 00000000000..01ed0e8826c --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2019 Benjamin Valentin + * Copyright (c) 2019-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "samr21_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM R21 Xplained Pro"; + compatible = "samr21,xpro", "atmel,samr21g18a", "atmel,samr21"; + + chosen { + zephyr,console = &sercom0; + zephyr,shell-uart = &sercom0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,ieee802154 = &ieee802154; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + i2c-0 = &sercom1; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&porta 19 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 3 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; + + ext1_header: xplained-pro-connector1 { + compatible = "atmel-xplained-pro-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; /* Shared */ + gpio-map = <0 0 &porta 6 0>, /* ADC6 */ + <1 0 &porta 7 0>, /* ADC7 */ + <2 0 &porta 13 0>, /* GPIO */ + <3 0 &porta 28 0>, /* GPIO */ + <4 0 &porta 18 0>, /* PWM_T0_W2 */ + <5 0 &porta 19 0>, /* PWM_T0_W3 */ + <6 0 &porta 22 0>, /* GPIO */ + <7 0 &porta 23 0>, /* GPIO */ + <8 0 &porta 16 0>, /* TWD1 EXT2 */ + <9 0 &porta 17 0>, /* TWCK1 EXT2 */ + <10 0 &porta 5 0>, /* RXD0 */ + <11 0 &porta 4 0>, /* TXD0 */ + <12 0 &portb 3 0>, /* SPI5(SS) */ + <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ + <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ + <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ + }; + + ext2_header: xplained-pro-connector2 { + compatible = "atmel-xplained-pro-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; /* Shared */ + gpio-map = /*<0 0 - - 0>, - */ + /*<1 0 - - 0>, - */ + <2 0 &porta 15 0>, /* GPIO */ + /*<3 0 - - 0>, - */ + /*<4 0 - - 0>, - */ + /*<5 0 - - 0>, - */ + /*<6 0 - - 0>, - */ + <7 0 &porta 8 0>, /* GPIO */ + <8 0 &porta 16 0>, /* TWD1 EXT1 */ + <9 0 &porta 17 0>, /* TWCK1 EXT1 */ + /*<11 0 - - 0>, - */ + /*<12 0 - - 0>, - */ + <12 0 &porta 14 0>, /* GPIO */ + <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ + <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ + <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + prescaler = <4>; + #pwm-cells = <2>; + + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom0_uart_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom1_i2c_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-spi"; + /* + * CS-PB31; MOSI-PB30; MISO-PC19; SCLK-PC18 + * PAD[1]; PAD[2]; PAD[0]; PAD[3] + */ + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom4_spi_default>; + pinctrl-names = "default"; + + cs-gpios = <&portb 31 GPIO_ACTIVE_LOW>; + + ieee802154: rf2xx@0 { + compatible = "atmel,rf2xx"; + reg = <0x0>; + spi-max-frequency = <6000000>; + irq-gpios = <&portb 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + reset-gpios = <&portb 15 GPIO_ACTIVE_LOW>; + slptr-gpios = <&porta 20 GPIO_ACTIVE_HIGH>; + dig2-gpios = <&portb 17 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + status = "okay"; + tx-pwr-min = [01 11]; /* -17.0 dBm */ + tx-pwr-max = [00 04]; /* 4.0 dBm */ + tx-pwr-table = [00 01 03 04 05 05 06 06 + 07 07 07 08 08 09 09 0a + 0a 0a 0b 0b 0b 0b 0c 0c + 0c 0c 0d 0d 0d 0d 0d 0d + 0d 0d 0e 0e 0e 0e 0e 0e + 0e 0e 0e 0e 0e 0e 0f 0f]; + }; +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_spi_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; + + pinctrl-0 = <&usb_dc_default>; + pinctrl-names = "default"; +}; + +ext1_spi: &sercom5 { +}; + +ext1_i2c: &sercom1 { +}; + +ext1_serial: &sercom0 { +}; + +ext2_spi: &sercom5 { +}; + +ext2_i2c: &sercom1 { +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The final 16 KiB is reserved for the application. + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + storage_partition: partition@3c000 { + label = "storage"; + reg = <0x0003c000 0x00004000>; + }; + }; +}; diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml new file mode 100644 index 00000000000..25ce756d667 --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml @@ -0,0 +1,28 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: samr21_xpro +name: SAM R21 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - flash + - gpio + - i2c + - netif + - pwm + - spi + - uart + - usb_device + - xpro_gpio + - xpro_i2c + - xpro_serial + - xpro_spi +vendor: atmel diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro_defconfig b/boards/atmel/sam0/samr21_xpro/samr21_xpro_defconfig new file mode 100644 index 00000000000..15f71b9d5ed --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamr21_xpro/support/openocd.cfg b/boards/atmel/sam0/samr21_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsamr21_xpro/support/openocd.cfg rename to boards/atmel/sam0/samr21_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/samr34_xpro/Kconfig.samr34_xpro b/boards/atmel/sam0/samr34_xpro/Kconfig.samr34_xpro new file mode 100644 index 00000000000..b5141577e59 --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/Kconfig.samr34_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAMR34_XPRO + select SOC_SAMR34J18B diff --git a/boards/arm/atsamr34_xpro/board.cmake b/boards/atmel/sam0/samr34_xpro/board.cmake similarity index 100% rename from boards/arm/atsamr34_xpro/board.cmake rename to boards/atmel/sam0/samr34_xpro/board.cmake diff --git a/boards/atmel/sam0/samr34_xpro/board.yml b/boards/atmel/sam0/samr34_xpro/board.yml new file mode 100644 index 00000000000..39df0e0451b --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: samr34_xpro + vendor: atmel + socs: + - name: samr34j18b diff --git a/boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro-pinout.jpg b/boards/atmel/sam0/samr34_xpro/doc/img/atsamr34-xpro-pinout.jpg similarity index 100% rename from boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro-pinout.jpg rename to boards/atmel/sam0/samr34_xpro/doc/img/atsamr34-xpro-pinout.jpg diff --git a/boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro.jpg b/boards/atmel/sam0/samr34_xpro/doc/img/atsamr34-xpro.jpg similarity index 100% rename from boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro.jpg rename to boards/atmel/sam0/samr34_xpro/doc/img/atsamr34-xpro.jpg diff --git a/boards/atmel/sam0/samr34_xpro/doc/index.rst b/boards/atmel/sam0/samr34_xpro/doc/index.rst new file mode 100644 index 00000000000..aa8849d2cb3 --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/doc/index.rst @@ -0,0 +1,218 @@ + .. _samr34_xpro: + +SAM R34 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM R34 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM R34 Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +The SAMR34 and SAMR35 parts are produced as a System-in-Package (SiP), +including both a SAML21 die, and a Semtech SX1276 LoRa radio die. + +This board is also referred to as DM320111. + +.. image:: img/atsamr34-xpro.jpg + :align: center + :alt: SAMR34-XPRO + +Hardware +******** + +- SAMR34J18 ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The samr34_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - GPIO + - on-chip + - I/O ports + * - PWM + - on-chip + - Pulse Width Modulation + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + * - TRNG + - on-chip + - True Random Number Generator + +The following hardware features are supported by Zephyr, but not yet fully +supported by the SOC: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - LoRa Radio + - on-chip + - Internal SX1276 LoRa Radio + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/samr34_xpro/samr34_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM R34 Xplained Pro evaluation kit has 3 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM R34 Family Datasheet`_ and the `SAM R34 +Xplained Pro Schematic`_. + +.. image:: img/atsamr34-xpro-pinout.jpg + :align: center + :alt: SAMR34-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM0 UART TX : PA04 +- SERCOM0 UART RX : PA05 +- SERCOM1 I2C SDA : PA16 +- SERCOM1 I2C SCL : PA17 +- SERCOM4 SPI MISO : PC19 +- SERCOM4 SPI MOSI : PB30 +- SERCOM4 SPI SCK : PC18 +- SERCOM4 GPIO CS : PB31 +- SERCOM5 SPI MISO : PB02 +- SERCOM5 SPI MOSI : PB22 +- SERCOM5 SPI SCK : PB23 +- SERCOM5 GPIO CS0 : PA23 +- SERCOM5 GPIO CS1 : PA14 +- USB DP : PA25 +- USB DM : PA24 +- GPIO/PWM LED0 : PA19 + +System Clock +============ + +The SAMR34 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMR34 MCU has six SERCOM based USARTs with one configured as USART in +this BSP. SERCOM0 is the default Zephyr console. + +- SERCOM0 115200 8n1 - connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAMR34 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAMR34 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. + +- SERCOM4 - connected to the internal LoRa radio +- SERCOM5 - connected to EXT1 and EXT3 + +Programming and Debugging +************************* + +The SAM R34 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMR34 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samr34_xpro + :goals: build + :compact: + +#. Connect the SAM R34 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ picocom -b 115200 /dev/ttyACM0 + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samr34_xpro + :goals: flash + :compact: + + You should see "Hello World! samr34_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + https://www.microchip.com/en-us/development-tool/dm320111 + +.. _SAM L21 Family Datasheet: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_L21_Family_DataSheet_DS60001477C.pdf + +.. _SAM R34 Family Datasheet: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAM-R34-R35-Low-Power-LoRa-Sub-GHz-SiP-Data-Sheet-DS70005356C.pdf + +.. _SAM R34 Xplained Pro Schematic: + https://ww1.microchip.com/downloads/Secure/en/DeviceDoc/SAMR34_SiP_Reference_Design_Package_V3.0.exe + +.. _Semtech SX1276: + https://www.semtech.com/products/wireless-rf/lora-transceivers/sx1276 diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro-pinctrl.dtsi b/boards/atmel/sam0/samr34_xpro/samr34_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsamr34_xpro/atsamr34_xpro-pinctrl.dtsi rename to boards/atmel/sam0/samr34_xpro/samr34_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/samr34_xpro/samr34_xpro.dts b/boards/atmel/sam0/samr34_xpro/samr34_xpro.dts new file mode 100644 index 00000000000..964cd8af4df --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/samr34_xpro.dts @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "samr34_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM R34 Xplained Pro"; + compatible = "samr34,xpro", "atmel,samr34j18b", "atmel,samr34"; + + chosen { + zephyr,console = &sercom0; + zephyr,shell-uart = &sercom0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&porta 19 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 3 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&adc { + status = "okay"; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + /* Gives a maximum period of 1.4s */ + prescaler = <4>; + #pwm-cells = <2>; + + pinctrl-0 = <&tcc0_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom0_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom1_default>; + pinctrl-names = "default"; +}; + +/* SERCOM4 is used for the internal LoRa radio */ +&sercom4 { + status = "okay"; +}; + +&lora { + status = "okay"; + + tcxo-power-gpios = <&porta 9 GPIO_ACTIVE_HIGH>; /* TCXO_PWR */ + tcxo-power-startup-delay-ms = <5>; + rfi-enable-gpios = <&porta 13 GPIO_ACTIVE_HIGH>; /* BAND_SEL */ + rfo-enable-gpios = <&porta 13 GPIO_ACTIVE_HIGH>; /* BAND_SEL */ +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; + + pinctrl-0 = <&usb0_default>; + pinctrl-names = "default"; +}; diff --git a/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml b/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml new file mode 100644 index 00000000000..be66ff6cde5 --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml @@ -0,0 +1,26 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: samr34_xpro +name: SAM R34 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - counter + - dma + - gpio + - i2c + - pwm + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: atmel diff --git a/boards/atmel/sam0/samr34_xpro/samr34_xpro_defconfig b/boards/atmel/sam0/samr34_xpro/samr34_xpro_defconfig new file mode 100644 index 00000000000..50125e5510d --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/samr34_xpro_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAML_XOSC32K=y +CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamr34_xpro/support/openocd.cfg b/boards/atmel/sam0/samr34_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsamr34_xpro/support/openocd.cfg rename to boards/atmel/sam0/samr34_xpro/support/openocd.cfg diff --git a/boards/bbc/index.rst b/boards/bbc/index.rst new file mode 100644 index 00000000000..e86cac8937b --- /dev/null +++ b/boards/bbc/index.rst @@ -0,0 +1,10 @@ +.. _boards-bbc: + +BBC +### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/bbc/microbit/Kconfig.bbc_microbit b/boards/bbc/microbit/Kconfig.bbc_microbit new file mode 100644 index 00000000000..37fc2a5e24f --- /dev/null +++ b/boards/bbc/microbit/Kconfig.bbc_microbit @@ -0,0 +1,7 @@ +# nRF51 BBC_MICROBIT board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BBC_MICROBIT + select SOC_NRF51822_QFAA diff --git a/boards/bbc/microbit/Kconfig.defconfig b/boards/bbc/microbit/Kconfig.defconfig new file mode 100644 index 00000000000..1f8bf5b8bc7 --- /dev/null +++ b/boards/bbc/microbit/Kconfig.defconfig @@ -0,0 +1,19 @@ +# nRF51 BBC_MICROBIT board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BBC_MICROBIT + +config BT_CTLR + default BT + +if FXOS8700 + +choice FXOS8700_MODE + default FXOS8700_MODE_ACCEL +endchoice + +endif # FXOS8700 + +endif # BOARD_BBC_MICROBIT diff --git a/boards/arm/bbc_microbit/bbc_microbit-pinctrl.dtsi b/boards/bbc/microbit/bbc_microbit-pinctrl.dtsi similarity index 100% rename from boards/arm/bbc_microbit/bbc_microbit-pinctrl.dtsi rename to boards/bbc/microbit/bbc_microbit-pinctrl.dtsi diff --git a/boards/arm/bbc_microbit/bbc_microbit.dts b/boards/bbc/microbit/bbc_microbit.dts similarity index 100% rename from boards/arm/bbc_microbit/bbc_microbit.dts rename to boards/bbc/microbit/bbc_microbit.dts diff --git a/boards/arm/bbc_microbit/bbc_microbit.yaml b/boards/bbc/microbit/bbc_microbit.yaml similarity index 100% rename from boards/arm/bbc_microbit/bbc_microbit.yaml rename to boards/bbc/microbit/bbc_microbit.yaml diff --git a/boards/bbc/microbit/bbc_microbit_defconfig b/boards/bbc/microbit/bbc_microbit_defconfig new file mode 100644 index 00000000000..6bff8b91228 --- /dev/null +++ b/boards/bbc/microbit/bbc_microbit_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Clock control +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y + +# Enable uart driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bbc_microbit/board.cmake b/boards/bbc/microbit/board.cmake similarity index 100% rename from boards/arm/bbc_microbit/board.cmake rename to boards/bbc/microbit/board.cmake diff --git a/boards/arm/bbc_microbit/board.h b/boards/bbc/microbit/board.h similarity index 100% rename from boards/arm/bbc_microbit/board.h rename to boards/bbc/microbit/board.h diff --git a/boards/bbc/microbit/board.yml b/boards/bbc/microbit/board.yml new file mode 100644 index 00000000000..3983adf061e --- /dev/null +++ b/boards/bbc/microbit/board.yml @@ -0,0 +1,5 @@ +board: + name: bbc_microbit + vendor: bbc + socs: + - name: nrf51822 diff --git a/boards/arm/bbc_microbit/doc/img/bbc_microbit.jpg b/boards/bbc/microbit/doc/img/bbc_microbit.jpg similarity index 100% rename from boards/arm/bbc_microbit/doc/img/bbc_microbit.jpg rename to boards/bbc/microbit/doc/img/bbc_microbit.jpg diff --git a/boards/arm/bbc_microbit/doc/index.rst b/boards/bbc/microbit/doc/index.rst similarity index 100% rename from boards/arm/bbc_microbit/doc/index.rst rename to boards/bbc/microbit/doc/index.rst diff --git a/boards/arm/96b_carbon_nrf51/pre_dt_board.cmake b/boards/bbc/microbit/pre_dt_board.cmake similarity index 100% rename from boards/arm/96b_carbon_nrf51/pre_dt_board.cmake rename to boards/bbc/microbit/pre_dt_board.cmake diff --git a/boards/bbc/microbit_v2/Kconfig.bbc_microbit_v2 b/boards/bbc/microbit_v2/Kconfig.bbc_microbit_v2 new file mode 100644 index 00000000000..172aaf9e965 --- /dev/null +++ b/boards/bbc/microbit_v2/Kconfig.bbc_microbit_v2 @@ -0,0 +1,7 @@ +# nRF52 BBC_MICROBIT_V2 board configuration + +# Copyright (c) 2020 Lingao Meng +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BBC_MICROBIT_V2 + select SOC_NRF52833_QIAA diff --git a/boards/bbc/microbit_v2/Kconfig.defconfig b/boards/bbc/microbit_v2/Kconfig.defconfig new file mode 100644 index 00000000000..3139f2f24c5 --- /dev/null +++ b/boards/bbc/microbit_v2/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52 BBC_MICROBIT_V2 board configuration + +# Copyright (c) 2020 Lingao Meng +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BBC_MICROBIT_V2 + +config BT_CTLR + default BT + +endif # BOARD_BBC_MICROBIT_V2 diff --git a/boards/arm/bbc_microbit_v2/bbc_microbit_v2-pinctrl.dtsi b/boards/bbc/microbit_v2/bbc_microbit_v2-pinctrl.dtsi similarity index 100% rename from boards/arm/bbc_microbit_v2/bbc_microbit_v2-pinctrl.dtsi rename to boards/bbc/microbit_v2/bbc_microbit_v2-pinctrl.dtsi diff --git a/boards/arm/bbc_microbit_v2/bbc_microbit_v2.dts b/boards/bbc/microbit_v2/bbc_microbit_v2.dts similarity index 100% rename from boards/arm/bbc_microbit_v2/bbc_microbit_v2.dts rename to boards/bbc/microbit_v2/bbc_microbit_v2.dts diff --git a/boards/arm/bbc_microbit_v2/bbc_microbit_v2.yaml b/boards/bbc/microbit_v2/bbc_microbit_v2.yaml similarity index 100% rename from boards/arm/bbc_microbit_v2/bbc_microbit_v2.yaml rename to boards/bbc/microbit_v2/bbc_microbit_v2.yaml diff --git a/boards/bbc/microbit_v2/bbc_microbit_v2_defconfig b/boards/bbc/microbit_v2/bbc_microbit_v2_defconfig new file mode 100644 index 00000000000..dddc2f924d0 --- /dev/null +++ b/boards/bbc/microbit_v2/bbc_microbit_v2_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# clock control +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bbc_microbit_v2/board.cmake b/boards/bbc/microbit_v2/board.cmake similarity index 100% rename from boards/arm/bbc_microbit_v2/board.cmake rename to boards/bbc/microbit_v2/board.cmake diff --git a/boards/bbc/microbit_v2/board.yml b/boards/bbc/microbit_v2/board.yml new file mode 100644 index 00000000000..1355002a7d1 --- /dev/null +++ b/boards/bbc/microbit_v2/board.yml @@ -0,0 +1,5 @@ +board: + name: bbc_microbit_v2 + vendor: bbc + socs: + - name: nrf52833 diff --git a/boards/arm/bbc_microbit_v2/doc/img/bbc_microbit2.jpg b/boards/bbc/microbit_v2/doc/img/bbc_microbit2.jpg similarity index 100% rename from boards/arm/bbc_microbit_v2/doc/img/bbc_microbit2.jpg rename to boards/bbc/microbit_v2/doc/img/bbc_microbit2.jpg diff --git a/boards/arm/bbc_microbit_v2/doc/index.rst b/boards/bbc/microbit_v2/doc/index.rst similarity index 100% rename from boards/arm/bbc_microbit_v2/doc/index.rst rename to boards/bbc/microbit_v2/doc/index.rst diff --git a/boards/arm/bl653_dvk/pre_dt_board.cmake b/boards/bbc/microbit_v2/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl653_dvk/pre_dt_board.cmake rename to boards/bbc/microbit_v2/pre_dt_board.cmake diff --git a/boards/arm/beagle_bcf/CMakeLists.txt b/boards/beagle/beagleconnect_freedom/CMakeLists.txt similarity index 100% rename from boards/arm/beagle_bcf/CMakeLists.txt rename to boards/beagle/beagleconnect_freedom/CMakeLists.txt diff --git a/boards/beagle/beagleconnect_freedom/Kconfig b/boards/beagle/beagleconnect_freedom/Kconfig new file mode 100644 index 00000000000..76a029c8860 --- /dev/null +++ b/boards/beagle/beagleconnect_freedom/Kconfig @@ -0,0 +1,17 @@ +# BeagleConnect Freedom board configuration + +# Copyright (c) 2020 Erik Larson +# Copyright (c) 2021 Jason Kridner, BeagleBoard.org Foundation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BEAGLECONNECT_FREEDOM + +config BOARD_ANTENNA_INIT_PRIO + int "Board antenna switch initialization priority" + default 70 + help + Set the priority for board init, must be greater than + KERNEL_INIT_PRIORITY_DEVICE but smaller than + IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO. + +endif # BOARD_BEAGLECONNECT_FREEDOM diff --git a/boards/beagle/beagleconnect_freedom/Kconfig.beagleconnect_freedom b/boards/beagle/beagleconnect_freedom/Kconfig.beagleconnect_freedom new file mode 100644 index 00000000000..28ddae96e89 --- /dev/null +++ b/boards/beagle/beagleconnect_freedom/Kconfig.beagleconnect_freedom @@ -0,0 +1,8 @@ +# BeagleConnect Freedom board configuration + +# Copyright (c) 2020 Erik Larson +# Copyright (c) 2021 Jason Kridner, BeagleBoard.org Foundation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BEAGLECONNECT_FREEDOM + select SOC_CC1352P7 diff --git a/boards/arm/beagle_bcf/beagleconnect_freedom-pinctrl.dtsi b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi similarity index 100% rename from boards/arm/beagle_bcf/beagleconnect_freedom-pinctrl.dtsi rename to boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi diff --git a/boards/arm/beagle_bcf/beagleconnect_freedom.dts b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts similarity index 100% rename from boards/arm/beagle_bcf/beagleconnect_freedom.dts rename to boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts diff --git a/boards/arm/beagle_bcf/beagleconnect_freedom.yaml b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml similarity index 100% rename from boards/arm/beagle_bcf/beagleconnect_freedom.yaml rename to boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml diff --git a/boards/arm/beagle_bcf/beagleconnect_freedom_defconfig b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom_defconfig similarity index 87% rename from boards/arm/beagle_bcf/beagleconnect_freedom_defconfig rename to boards/beagle/beagleconnect_freedom/beagleconnect_freedom_defconfig index a2c05f40f32..024c0463996 100644 --- a/boards/arm/beagle_bcf/beagleconnect_freedom_defconfig +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom_defconfig @@ -8,9 +8,6 @@ CONFIG_GPIO=y CONFIG_PINCTRL=y -CONFIG_SOC_SERIES_CC13X2X7_CC26X2X7=y -CONFIG_SOC_CC1352P7=y -CONFIG_BOARD_BEAGLECONNECT_FREEDOM=y CONFIG_BUILD_OUTPUT_HEX=y # custom callback for the antenna switch CONFIG_CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS=y diff --git a/boards/arm/beagle_bcf/board.cmake b/boards/beagle/beagleconnect_freedom/board.cmake similarity index 100% rename from boards/arm/beagle_bcf/board.cmake rename to boards/beagle/beagleconnect_freedom/board.cmake diff --git a/boards/beagle/beagleconnect_freedom/board.yml b/boards/beagle/beagleconnect_freedom/board.yml new file mode 100644 index 00000000000..a0d11fb2410 --- /dev/null +++ b/boards/beagle/beagleconnect_freedom/board.yml @@ -0,0 +1,5 @@ +board: + name: beagleconnect_freedom + vendor: beagle + socs: + - name: cc1352p7 diff --git a/boards/arm/beagle_bcf/board_antenna.c b/boards/beagle/beagleconnect_freedom/board_antenna.c similarity index 100% rename from boards/arm/beagle_bcf/board_antenna.c rename to boards/beagle/beagleconnect_freedom/board_antenna.c diff --git a/boards/arm/beagle_bcf/doc/img/beagleconnect_freedom.webp b/boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom.webp similarity index 100% rename from boards/arm/beagle_bcf/doc/img/beagleconnect_freedom.webp rename to boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom.webp diff --git a/boards/arm/beagle_bcf/doc/img/beagleconnect_freedom_back_annotated.webp b/boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom_back_annotated.webp similarity index 100% rename from boards/arm/beagle_bcf/doc/img/beagleconnect_freedom_back_annotated.webp rename to boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom_back_annotated.webp diff --git a/boards/arm/beagle_bcf/doc/img/beagleconnect_freedom_front_annotated.webp b/boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom_front_annotated.webp similarity index 100% rename from boards/arm/beagle_bcf/doc/img/beagleconnect_freedom_front_annotated.webp rename to boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom_front_annotated.webp diff --git a/boards/arm/beagle_bcf/doc/index.rst b/boards/beagle/beagleconnect_freedom/doc/index.rst similarity index 100% rename from boards/arm/beagle_bcf/doc/index.rst rename to boards/beagle/beagleconnect_freedom/doc/index.rst diff --git a/boards/beagle/beaglev_fire/Kconfig b/boards/beagle/beaglev_fire/Kconfig new file mode 100644 index 00000000000..a0ce11033e7 --- /dev/null +++ b/boards/beagle/beaglev_fire/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BEAGLEV_FIRE + select 64BIT + select SCHED_IPI_SUPPORTED + select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/beagle/beaglev_fire/Kconfig.beaglev_fire b/boards/beagle/beaglev_fire/Kconfig.beaglev_fire new file mode 100644 index 00000000000..b4bf8b4b2d3 --- /dev/null +++ b/boards/beagle/beaglev_fire/Kconfig.beaglev_fire @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BEAGLEV_FIRE + select SOC_POLARFIRE diff --git a/boards/riscv/beaglev_fire/beaglev_fire.dts b/boards/beagle/beaglev_fire/beaglev_fire.dts similarity index 100% rename from boards/riscv/beaglev_fire/beaglev_fire.dts rename to boards/beagle/beaglev_fire/beaglev_fire.dts diff --git a/boards/riscv/beaglev_fire/beaglev_fire.yaml b/boards/beagle/beaglev_fire/beaglev_fire.yaml similarity index 100% rename from boards/riscv/beaglev_fire/beaglev_fire.yaml rename to boards/beagle/beaglev_fire/beaglev_fire.yaml diff --git a/boards/riscv/beaglev_fire/beaglev_fire_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_defconfig similarity index 77% rename from boards/riscv/beaglev_fire/beaglev_fire_defconfig rename to boards/beagle/beaglev_fire/beaglev_fire_defconfig index eaf7d9c6f15..deb1db784f8 100644 --- a/boards/riscv/beaglev_fire/beaglev_fire_defconfig +++ b/boards/beagle/beaglev_fire/beaglev_fire_defconfig @@ -1,12 +1,9 @@ # Copyright (c) 2023 Microchip Technology Inc # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_POLARFIRE=y -CONFIG_SOC_POLARFIRE=y CONFIG_MPFS_HAL=n CONFIG_BASE64=y CONFIG_INCLUDE_RESET_VECTOR=y -CONFIG_BOARD_BEAGLEV_FIRE=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/beagle/beaglev_fire/board.yml b/boards/beagle/beaglev_fire/board.yml new file mode 100644 index 00000000000..89447e4b4ce --- /dev/null +++ b/boards/beagle/beaglev_fire/board.yml @@ -0,0 +1,5 @@ +board: + name: beaglev_fire + vendor: beagle + socs: + - name: polarfire diff --git a/boards/riscv/beaglev_fire/doc/img/BeagleV-Fire-Front-Annotated-768x432.webp b/boards/beagle/beaglev_fire/doc/img/BeagleV-Fire-Front-Annotated-768x432.webp similarity index 100% rename from boards/riscv/beaglev_fire/doc/img/BeagleV-Fire-Front-Annotated-768x432.webp rename to boards/beagle/beaglev_fire/doc/img/BeagleV-Fire-Front-Annotated-768x432.webp diff --git a/boards/riscv/beaglev_fire/doc/img/board-booting.png b/boards/beagle/beaglev_fire/doc/img/board-booting.png similarity index 100% rename from boards/riscv/beaglev_fire/doc/img/board-booting.png rename to boards/beagle/beaglev_fire/doc/img/board-booting.png diff --git a/boards/riscv/beaglev_fire/doc/index.rst b/boards/beagle/beaglev_fire/doc/index.rst similarity index 100% rename from boards/riscv/beaglev_fire/doc/index.rst rename to boards/beagle/beaglev_fire/doc/index.rst diff --git a/boards/beagle/index.rst b/boards/beagle/index.rst new file mode 100644 index 00000000000..e0afe34ad49 --- /dev/null +++ b/boards/beagle/index.rst @@ -0,0 +1,10 @@ +.. _boards-beagle: + +BeagleBoard.org Foundation +########################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/blue_clover/index.rst b/boards/blue_clover/index.rst new file mode 100644 index 00000000000..b629a34e8eb --- /dev/null +++ b/boards/blue_clover/index.rst @@ -0,0 +1,10 @@ +.. _boards-blue-clover: + +Blue Clover Devices +################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig b/boards/blue_clover/plt_demo_v2/Kconfig similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig rename to boards/blue_clover/plt_demo_v2/Kconfig diff --git a/boards/blue_clover/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 b/boards/blue_clover/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 new file mode 100644 index 00000000000..2b69264a29c --- /dev/null +++ b/boards/blue_clover/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 @@ -0,0 +1,7 @@ +# Blue Clover PLT Demo V2 Configuration + +# Copyright (c) 2021 Blue Clover +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 + select SOC_NRF52832_QFAA diff --git a/boards/blue_clover/plt_demo_v2/Kconfig.defconfig b/boards/blue_clover/plt_demo_v2/Kconfig.defconfig new file mode 100644 index 00000000000..ce7c0c3891f --- /dev/null +++ b/boards/blue_clover/plt_demo_v2/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Blue Clover PLT Demo V2 Configuration + +# Copyright (c) 2021 Blue Clover +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 + +config BT_CTLR + default BT + +config I2C + default SENSOR + +endif # BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832-pinctrl.dtsi b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832-pinctrl.dtsi rename to boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832-pinctrl.dtsi diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832.dts b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832.dts rename to boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832.yaml b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.yaml similarity index 85% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832.yaml rename to boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.yaml index f031e5105ef..6536b8a957f 100644 --- a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832.yaml +++ b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -identifier: blueclover_plt_demo_v2_nrf52832 +identifier: blueclover_plt_demo_v2/nrf52832 name: Blue Clover PLT Demo Board V2 type: mcu arch: arm diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832_defconfig b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832_defconfig similarity index 75% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832_defconfig rename to boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832_defconfig index d9999ba9516..e953d30137e 100644 --- a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832_defconfig +++ b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832_defconfig @@ -4,10 +4,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/board.cmake b/boards/blue_clover/plt_demo_v2/board.cmake similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/board.cmake rename to boards/blue_clover/plt_demo_v2/board.cmake diff --git a/boards/blue_clover/plt_demo_v2/board.yml b/boards/blue_clover/plt_demo_v2/board.yml new file mode 100644 index 00000000000..2d0c58bf628 --- /dev/null +++ b/boards/blue_clover/plt_demo_v2/board.yml @@ -0,0 +1,5 @@ +board: + name: blueclover_plt_demo_v2 + vendor: bcdevices + socs: + - name: nrf52832 diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/doc/img/blueclover_plt_demo_v2.jpg b/boards/blue_clover/plt_demo_v2/doc/img/blueclover_plt_demo_v2.jpg similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/doc/img/blueclover_plt_demo_v2.jpg rename to boards/blue_clover/plt_demo_v2/doc/img/blueclover_plt_demo_v2.jpg diff --git a/boards/blue_clover/plt_demo_v2/doc/index.rst b/boards/blue_clover/plt_demo_v2/doc/index.rst new file mode 100644 index 00000000000..ae3b5c158f7 --- /dev/null +++ b/boards/blue_clover/plt_demo_v2/doc/index.rst @@ -0,0 +1,153 @@ +.. _blueclover_plt_demo_v2_nrf52832: + +Blue Clover PLT Demo V2 nRF52832 +################################ + +Overview +******** + +The Blue Clover PLT Demo V2 is an open source (OSWHA certified) hardware +product, featuring the Nordic Semiconductor nRF52832 ARM Cortex-M4F MCU +and several useful external peripherals. + +The Nordic Semiconductor nRF52832 ARM Cortex-M4F MCU features the following: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/blueclover_plt_demo_v2.jpg + :align: center + :alt: Blue Clover PLT Demo V2 nRF52832 + +Hardware +******** + +- nRF52832 ARM Cortex-M4F processor at 64 MHz +- 512 KB flash memory and 64 KB of SRAM +- Bosch BMI270 IMU +- Sensiron SHT30 Humidity and Temperature sensor +- Murata PKLCS1212E4001R1 Piezo Buzzer +- Battery connector and charger for 3.7 V lithium polymer batteries +- 4 APA102C Addressable LEDs +- Reset button (can be configured as user button) +- 1 User button +- Tag-Connect TC2030-FP 6-pin Debug Connector + +Supported Features +================== + +The Blue Clover PLT Demo V2 board configuration supports the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +Push buttons +------------ + +* RESET = P0.21 +* STATUS = P0.26 + +UART +---- + +* TXD = P0.06 +* RXD = P0.08 + +Power +----- + +* USB-C Connector +* JST-PH Battery Connector + +NFC +--- + +* U.FL Connector, on NFC1/P0.09, NFC2/P0.10 + +Programming and Debugging +************************* + +Applications for the ``blueclover_plt_demo_v2/nrf52832`` board configuration +can be built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + +Flashing +======== + +Flashing Zephyr onto the ``blueclover_plt_demo_v2/nrf52832`` board requires +an external programmer. The programmer is attached to the SWD header. + +Build the Zephyr kernel and the :zephyr:code-sample:`led-apa102` sample application. + + .. zephyr-app-commands:: + :zephyr-app: samples/drivers/led_apa102 + :board: blueclover_plt_demo_v2/nrf52832 + :goals: build + :compact: + +Flash the image. + + .. zephyr-app-commands:: + :zephyr-app: samples/drivers/led_apa102 + :board: blueclover_plt_demo_v2/nrf52832 + :goals: flash + :compact: + +References +********** + +.. target-notes:: + +.. _Blue Clover PLT Demo V2 Product site: + https://bcdevices.com/products/plt-demo-board + +.. _Blue Clover PLT Demo V2 OSWHA Certification: + https://certification.oshwa.org/us002054.html + +.. _Schematic, layout, and gerbers: + https://github.com/bcdevices/plt-docs/tree/master/PLT-DEMOv2 diff --git a/boards/arm/bl654_dvk/pre_dt_board.cmake b/boards/blue_clover/plt_demo_v2/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl654_dvk/pre_dt_board.cmake rename to boards/blue_clover/plt_demo_v2/pre_dt_board.cmake diff --git a/boards/blues/index.rst b/boards/blues/index.rst new file mode 100644 index 00000000000..a4f76b4c9fa --- /dev/null +++ b/boards/blues/index.rst @@ -0,0 +1,10 @@ +.. _boards-blues: + +Blues +##### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/nrf52840dongle_nrf52840/CMakeLists.txt b/boards/blues/swan_r5/CMakeLists.txt similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/CMakeLists.txt rename to boards/blues/swan_r5/CMakeLists.txt diff --git a/boards/blues/swan_r5/Kconfig.defconfig b/boards/blues/swan_r5/Kconfig.defconfig new file mode 100644 index 00000000000..a9d7a1e00b1 --- /dev/null +++ b/boards/blues/swan_r5/Kconfig.defconfig @@ -0,0 +1,22 @@ +# Blues Wireless Swan board configuration + +# Copyright (c) 2022 Blues Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SWAN_R5 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +if NETWORKING + +config USB_DEVICE_STACK + default y + +config USB_DEVICE_NETWORK_EEM + default y + +endif # NETWORKING + +endif # BOARD_SWAN_R5 diff --git a/boards/blues/swan_r5/Kconfig.swan_r5 b/boards/blues/swan_r5/Kconfig.swan_r5 new file mode 100644 index 00000000000..6b3b835c31f --- /dev/null +++ b/boards/blues/swan_r5/Kconfig.swan_r5 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Blues Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SWAN_R5 + select SOC_STM32L4R5XX diff --git a/boards/arm/swan_r5/board.c b/boards/blues/swan_r5/board.c similarity index 100% rename from boards/arm/swan_r5/board.c rename to boards/blues/swan_r5/board.c diff --git a/boards/arm/swan_r5/board.cmake b/boards/blues/swan_r5/board.cmake similarity index 100% rename from boards/arm/swan_r5/board.cmake rename to boards/blues/swan_r5/board.cmake diff --git a/boards/blues/swan_r5/board.yml b/boards/blues/swan_r5/board.yml new file mode 100644 index 00000000000..d9d4096e352 --- /dev/null +++ b/boards/blues/swan_r5/board.yml @@ -0,0 +1,5 @@ +board: + name: swan_r5 + vendor: blues + socs: + - name: stm32l4r5xx diff --git a/boards/arm/swan_r5/doc/img/swan.jpg b/boards/blues/swan_r5/doc/img/swan.jpg similarity index 100% rename from boards/arm/swan_r5/doc/img/swan.jpg rename to boards/blues/swan_r5/doc/img/swan.jpg diff --git a/boards/blues/swan_r5/doc/index.rst b/boards/blues/swan_r5/doc/index.rst new file mode 100644 index 00000000000..644e82e86dd --- /dev/null +++ b/boards/blues/swan_r5/doc/index.rst @@ -0,0 +1,232 @@ +.. _swan_r5_board: + +Blues Wireless Swan +################### + +Overview +******** + +Swan is a low-cost embeddable STM32L4-based microcontroller designed to +accelerate the development and deployment of battery-powered solutions. +It is especially useful for applications requiring large memory or a high +degree of I/O expandability at an affordable cost, such as edge inferencing +and remote monitoring. + +Uniquely for Feather-compatible boards, Swan is designed to satisfy +developers' needs that span from early prototyping through high-volume +deployment. Developers may begin to use Swan in conjunction with +Adafruit's myriad sensors and FeatherWing-compatible carriers. +Due to its novel design, for high-volume deployment the low-cost Swan +can also be soldered directly to a parent PCB integrating those sensors, +utilizing the full range of Swan's I/O capabilities. + +The board has three independent power options-USB, Battery, or Line power- +and provides a software-switchable 2 Amp regulator for powering external +sensors. When operating in its low-power operating mode, the entire Swan +board commonly draws only about 8uA while retaining all of its memory, +making it quite suitable for battery-powered devices. + +The Swan board features an ARM Cortex-M4 based STM32L4R5ZI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the board: + +- STM32 microcontroller in WLCSP144 package +- 2MB of flash and 640KB of RAM +- Two types of extension resources: + + - Adafruit Feather-compatible connectivity + - Access to 36 additional STM32 pins (beyond the Feather pins) via 0.05" castellated edge headers + +- On-board ST-LINKV3 debugger/programmer with SWD connector + +- One Red User LED (LD1) +- Two push-buttons: USER and RESET + +- Castellated-edge access to 55 GPIO ports including: + + - 8 analog + - 16 digital + - 4x I2C, 3x SPI + - USB OTG full speed + - 1x 14-channel DMA + - tRNG + - 12-bit ADC, 2 x 12-bit DAC + - low-power RTC, and CRC calculation peripherals + +.. image:: img/swan.jpg + :align: center + :alt: Blues Wireless Swan + +More information about the board can be found at the `Swan Product Page`_. + +Hardware +******** + +The STM32L4R5ZI SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode + and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive + real-time accelerator (ART Accelerator) allowing 0-wait-state + execution from Flash memory, frequency up to 120 MHz, MPU, 150 + DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions + +- Memories + + - 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection + - 640 Kbytes of SRAM including 64 Kbytes with hardware parity check + - External memory interface for static memories supporting SRAM, + PSRAM, NOR, NAND and FRAM memories + - 2 x OctoSPI memory interface + +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace + Macrocell (ETM) + +More information about Swan can be found here: + +- `Swan Quickstart Guide`_ +- `Swan Datasheet`_ + +Supported Features +================== + +The Zephyr Swan board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/blues/swan_r5/swan_r5_defconfig` + + +Connections and IOs +=================== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- A0 : PA3 +- A1 : PA1 +- A2 : PC3 +- A3 : PC1 +- A4 : PC4 +- A5 : PC5 +- D4 : PE3 +- D5 : PE11 +- D6 : PE9 +- D9 : PD15 +- D10 : PA4 +- D11 : PA7 +- D12 : PA6 +- D13 : PA5 +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PD6 +- UART_3_TX : PB10 +- UART_3_RX : PB11 +- LPUART_TX : PG7 +- LPUART_RX : PG8 +- I2C_1_SCL : PB6 +- I2C_1_SDA : PB7 +- I2C_2_SCL : PF1 +- I2C_2_SDA : PF0 +- I2C_3_SCL : PC0 +- I2C_3_SDA : PC9 +- SPI_1_NSS : PA4 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- SPI_2_NSS : PD0 +- SPI_2_SCK : PD1 +- SPI_2_MISO : PB14 +- SPI_2_MOSI : PB15 +- SPI_3_NSS : PA15 +- SPI_3_SCK : PC10 +- SPI_3_MISO : PC11 +- SPI_3_MOSI : PC12 +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD1 : PE2 +- USB DM : PA11 +- USB DP : PA12 +- ADC1 : PA1 + +System Clock +------------ + +Swan System Clock could be driven by internal or external +oscillator, as well as main PLL clock. By default, the System clock is +driven by the PLL clock at 80MHz, driven by a 16MHz high speed +internal oscillator. + +Serial Port +----------- + +Swan has 4 U(S)ARTs. The Zephyr console output is +assigned to LPUART. Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Connect Swan to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Swan: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: swan_r5 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +References +********** + +.. _Swan Product Page: + https://blues.io/products/swan + +.. _Swan Quickstart Guide: + https://dev.blues.io/start/swan/swan-quickstart + +.. _Swan Datasheet: + https://dev.blues.io/hardware/swan-datasheet/ diff --git a/boards/arm/swan_r5/feather_connector.dtsi b/boards/blues/swan_r5/feather_connector.dtsi similarity index 100% rename from boards/arm/swan_r5/feather_connector.dtsi rename to boards/blues/swan_r5/feather_connector.dtsi diff --git a/boards/arm/nucleo_l476rg/support/openocd.cfg b/boards/blues/swan_r5/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l476rg/support/openocd.cfg rename to boards/blues/swan_r5/support/openocd.cfg diff --git a/boards/arm/swan_r5/swan_r5.dts b/boards/blues/swan_r5/swan_r5.dts similarity index 100% rename from boards/arm/swan_r5/swan_r5.dts rename to boards/blues/swan_r5/swan_r5.dts diff --git a/boards/arm/swan_r5/swan_r5.yaml b/boards/blues/swan_r5/swan_r5.yaml similarity index 100% rename from boards/arm/swan_r5/swan_r5.yaml rename to boards/blues/swan_r5/swan_r5.yaml diff --git a/boards/arm/swan_r5/swan_r5_defconfig b/boards/blues/swan_r5/swan_r5_defconfig similarity index 86% rename from boards/arm/swan_r5/swan_r5_defconfig rename to boards/blues/swan_r5/swan_r5_defconfig index caaca50d8b8..596cbc88cbd 100644 --- a/boards/arm/swan_r5/swan_r5_defconfig +++ b/boards/blues/swan_r5/swan_r5_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4R5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/bcm958401m2/CMakeLists.txt b/boards/brcm/bcm958401m2/CMakeLists.txt similarity index 100% rename from boards/arm/bcm958401m2/CMakeLists.txt rename to boards/brcm/bcm958401m2/CMakeLists.txt diff --git a/boards/brcm/bcm958401m2/Kconfig.bcm958401m2 b/boards/brcm/bcm958401m2/Kconfig.bcm958401m2 new file mode 100644 index 00000000000..38fd12a9ec5 --- /dev/null +++ b/boards/brcm/bcm958401m2/Kconfig.bcm958401m2 @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +config BOARD_BCM958401M2 + select SOC_BCM58400 diff --git a/boards/arm/bcm958401m2/bcm958401m2.dts b/boards/brcm/bcm958401m2/bcm958401m2.dts similarity index 100% rename from boards/arm/bcm958401m2/bcm958401m2.dts rename to boards/brcm/bcm958401m2/bcm958401m2.dts diff --git a/boards/arm/bcm958401m2/bcm958401m2.yaml b/boards/brcm/bcm958401m2/bcm958401m2.yaml similarity index 100% rename from boards/arm/bcm958401m2/bcm958401m2.yaml rename to boards/brcm/bcm958401m2/bcm958401m2.yaml diff --git a/boards/brcm/bcm958401m2/bcm958401m2_defconfig b/boards/brcm/bcm958401m2/bcm958401m2_defconfig new file mode 100644 index 00000000000..cc0d8af5baa --- /dev/null +++ b/boards/brcm/bcm958401m2/bcm958401m2_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 diff --git a/boards/arm/bcm958401m2/board.cmake b/boards/brcm/bcm958401m2/board.cmake similarity index 100% rename from boards/arm/bcm958401m2/board.cmake rename to boards/brcm/bcm958401m2/board.cmake diff --git a/boards/brcm/bcm958401m2/board.yml b/boards/brcm/bcm958401m2/board.yml new file mode 100644 index 00000000000..06c116fe825 --- /dev/null +++ b/boards/brcm/bcm958401m2/board.yml @@ -0,0 +1,5 @@ +board: + name: bcm958401m2 + vendor: brcm + socs: + - name: bcm58400 diff --git a/boards/brcm/bcm958401m2/doc/index.rst b/boards/brcm/bcm958401m2/doc/index.rst new file mode 100644 index 00000000000..e053bc2ce05 --- /dev/null +++ b/boards/brcm/bcm958401m2/doc/index.rst @@ -0,0 +1,57 @@ +.. _bcm958401m2: + +Broadcom BCM958401M2 +#################### + +Overview +******** +The Broadcom BCM958401M2 board utilizes the Valkyrie BCM58400 SoC to +provide support for PCIe offload engine functionality. + +Hardware +******** +The BCM958401M2 is a PCIe card with the following physical features: + +* PCIe Gen3 interface +* RS232 UART (optionally populated) +* JTAG (optionally populated) + +Supported Features +================== +The Broadcom BCM958401M2 board configuration supports the following hardware +features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| NVIC | on-chip | nested vectored interrupt controller | ++-----------+------------+--------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/broadcom/bcm958401m2/bcm958401m2_defconfig` + +Connections and IOs +=================== + + +Programming and Debugging +************************* + +Flashing +======== + +The flash on board is not supported by Zephyr at this time. +Board is booted over PCIe interface. + +Debugging +========= +The bcm958401m2 board includes pads for soldering a JTAG connector. +Zephyr applications running on the M7 core can also be tested by observing UART console output. + + +References +********** diff --git a/boards/arm/bcm958402m2_m7/CMakeLists.txt b/boards/brcm/bcm958402m2/CMakeLists.txt similarity index 100% rename from boards/arm/bcm958402m2_m7/CMakeLists.txt rename to boards/brcm/bcm958402m2/CMakeLists.txt diff --git a/boards/brcm/bcm958402m2/Kconfig.bcm958402m2 b/boards/brcm/bcm958402m2/Kconfig.bcm958402m2 new file mode 100644 index 00000000000..fb3fbf5a3bd --- /dev/null +++ b/boards/brcm/bcm958402m2/Kconfig.bcm958402m2 @@ -0,0 +1,6 @@ +# Copyright 2020 Broadcom +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BCM958402M2 + select SOC_BCM58402_M7 if BOARD_BCM958402M2_BCM58402_M7 + select SOC_BCM58402_A72 if BOARD_BCM958402M2_BCM58402_A72 diff --git a/boards/arm64/bcm958402m2_a72/bcm958402m2_a72.dts b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72.dts similarity index 100% rename from boards/arm64/bcm958402m2_a72/bcm958402m2_a72.dts rename to boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72.dts diff --git a/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72.yaml b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72.yaml new file mode 100644 index 00000000000..cbade5c4497 --- /dev/null +++ b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72.yaml @@ -0,0 +1,8 @@ +identifier: bcm958402m2/bcm58402/a72 +name: Broadcom BCM958402M2_A72 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +vendor: brcm diff --git a/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72_defconfig b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72_defconfig new file mode 100644 index 00000000000..e7b8f00265b --- /dev/null +++ b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72_defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable PCIe EP +CONFIG_PCIE_ENDPOINT=y +CONFIG_PCIE_EP_IPROC=y +CONFIG_PCIE_EP_IPROC_V2=y + +# Enable DMA +CONFIG_DMA=y +CONFIG_DMA_64BIT=y diff --git a/boards/arm/bcm958402m2_m7/bcm958402m2_m7.dts b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7.dts similarity index 100% rename from boards/arm/bcm958402m2_m7/bcm958402m2_m7.dts rename to boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7.dts diff --git a/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7.yaml b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7.yaml new file mode 100644 index 00000000000..c5c0c06996a --- /dev/null +++ b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7.yaml @@ -0,0 +1,8 @@ +identifier: bcm958402m2/bcm58402/m7 +name: Broadcom BCM958402M2_M7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +vendor: brcm diff --git a/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7_defconfig b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7_defconfig new file mode 100644 index 00000000000..5eb9b53fa6d --- /dev/null +++ b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable PCIe EP +CONFIG_PCIE_ENDPOINT=y +CONFIG_PCIE_EP_IPROC=y +CONFIG_PCIE_EP_IPROC_V2=y + +# Enable DMA +CONFIG_DMA=y +CONFIG_DMA_64BIT=y diff --git a/boards/arm/bcm958402m2_m7/board.cmake b/boards/brcm/bcm958402m2/board.cmake similarity index 100% rename from boards/arm/bcm958402m2_m7/board.cmake rename to boards/brcm/bcm958402m2/board.cmake diff --git a/boards/brcm/bcm958402m2/board.yml b/boards/brcm/bcm958402m2/board.yml new file mode 100644 index 00000000000..e9ad1770ed5 --- /dev/null +++ b/boards/brcm/bcm958402m2/board.yml @@ -0,0 +1,5 @@ +board: + name: bcm958402m2 + vendor: brcm + socs: + - name: bcm58402 diff --git a/boards/brcm/bcm958402m2/doc/a72.rst b/boards/brcm/bcm958402m2/doc/a72.rst new file mode 100644 index 00000000000..80fdd0ea4e5 --- /dev/null +++ b/boards/brcm/bcm958402m2/doc/a72.rst @@ -0,0 +1,50 @@ +.. _bcm958402m2_a72: + +Broadcom BCM958402M2 (Cortex-A72) +################################# + +Overview +******** +The Broadcom ``bcm958402m2/bcm58402/a72`` board utilizes the Viper BCM58402_A72 SoC +to provide support for PCIe offload engine functionality. + +Hardware +******** +The ``bcm958402m2/bcm58402/a72`` is a PCIe card with the following physical features: + +* PCIe Gen4 interface +* RS232 UART (optionally populated) +* JTAG (optionally populated) + +Supported Features +================== +The Broadcom ``bcm958402m2/bcm58402/a72`` board configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| GIC-500 | on-chip | GICv3 interrupt controller | ++-----------+------------+--------------------------------------+ +| UART | on-chip | NS16550 compatible serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/broadcom/bcm958402m2/bcm958402m2_bcm58402_a72_defconfig` + +Programming and Debugging +************************* + +Flashing +======== + +The flash on board is not supported by Zephyr at this time. +Board is booted over PCIe interface. + +Debugging +========= +The ``bcm958402m2/bcm58402/a72`` board includes pads for soldering a JTAG connector. +Zephyr applications running on the Cortex-A72 core can also be tested +by observing UART console output. diff --git a/boards/brcm/bcm958402m2/doc/m7.rst b/boards/brcm/bcm958402m2/doc/m7.rst new file mode 100644 index 00000000000..6edf1387964 --- /dev/null +++ b/boards/brcm/bcm958402m2/doc/m7.rst @@ -0,0 +1,50 @@ +.. _bcm958402m2_m7: + +Broadcom BCM958402M2 (Cortex-M7) +################################ + +Overview +******** +The Broadcom ``bcm958402m2/bcm58402/m7`` board utilizes the Viper BCM58402_M7 SoC to +provide support for PCIe offload engine functionality. + +Hardware +******** +The ``bcm958402m2/bcm58402/m7`` is a PCIe card with the following physical features: + +* PCIe Gen4 interface +* RS232 UART (optionally populated) +* JTAG (optionally populated) + +Supported Features +================== +The Broadcom ``bcm958402m2/bcm58402/m7`` board configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| NVIC | on-chip | nested vectored interrupt controller | ++-----------+------------+--------------------------------------+ +| UART | on-chip | Compatible with UART NS16550 | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/broadcom/bcm958402m2/bcm958402m2_bcm58402_m7_defconfig` + +Programming and Debugging +************************* + +Flashing +======== + +The flash on board is not supported by Zephyr at this time. +Board is booted over PCIe interface. + +Debugging +========= +The ``bcm958402m2/bcm58402/m7`` board includes pads for soldering a JTAG connector. +Zephyr applications running on the M7 core can also be tested +by observing UART console output. diff --git a/boards/brcm/index.rst b/boards/brcm/index.rst new file mode 100644 index 00000000000..08223cb7fc7 --- /dev/null +++ b/boards/brcm/index.rst @@ -0,0 +1,10 @@ +.. _boards-brcm: + +Broadcom Corporation +#################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/cdns/index.rst b/boards/cdns/index.rst new file mode 100644 index 00000000000..108368522b7 --- /dev/null +++ b/boards/cdns/index.rst @@ -0,0 +1,10 @@ +.. _boards-cdns: + +Cadence Design Systems Inc. +########################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/cdns/xt-sim/Kconfig.defconfig b/boards/cdns/xt-sim/Kconfig.defconfig new file mode 100644 index 00000000000..98be6f9e997 --- /dev/null +++ b/boards/cdns/xt-sim/Kconfig.defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Cadence Design Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config IPM_CONSOLE_STACK_SIZE + default 2048 if IPM_CONSOLE_RECEIVER diff --git a/boards/cdns/xt-sim/Kconfig.xt-sim b/boards/cdns/xt-sim/Kconfig.xt-sim new file mode 100644 index 00000000000..317547710db --- /dev/null +++ b/boards/cdns/xt-sim/Kconfig.xt-sim @@ -0,0 +1,7 @@ +# XTENSA board configuration + +# Copyright (c) 2016 Cadence Design Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XT_SIM + select SOC_XTENSA_SAMPLE_CONTROLLER diff --git a/boards/xtensa/xt-sim/board.cmake b/boards/cdns/xt-sim/board.cmake similarity index 100% rename from boards/xtensa/xt-sim/board.cmake rename to boards/cdns/xt-sim/board.cmake diff --git a/boards/cdns/xt-sim/board.yml b/boards/cdns/xt-sim/board.yml new file mode 100644 index 00000000000..d162e416a3b --- /dev/null +++ b/boards/cdns/xt-sim/board.yml @@ -0,0 +1,5 @@ +board: + name: xt-sim + vendor: cdns + socs: + - name: xtensa_sample_controller diff --git a/boards/xtensa/xt-sim/doc/img/xt-sim.jpg b/boards/cdns/xt-sim/doc/img/xt-sim.jpg similarity index 100% rename from boards/xtensa/xt-sim/doc/img/xt-sim.jpg rename to boards/cdns/xt-sim/doc/img/xt-sim.jpg diff --git a/boards/xtensa/xt-sim/doc/index.rst b/boards/cdns/xt-sim/doc/index.rst similarity index 100% rename from boards/xtensa/xt-sim/doc/index.rst rename to boards/cdns/xt-sim/doc/index.rst diff --git a/boards/xtensa/xt-sim/xt-sim.dts b/boards/cdns/xt-sim/xt-sim.dts similarity index 100% rename from boards/xtensa/xt-sim/xt-sim.dts rename to boards/cdns/xt-sim/xt-sim.dts diff --git a/boards/xtensa/xt-sim/xt-sim.yaml b/boards/cdns/xt-sim/xt-sim.yaml similarity index 100% rename from boards/xtensa/xt-sim/xt-sim.yaml rename to boards/cdns/xt-sim/xt-sim.yaml diff --git a/boards/xtensa/xt-sim/xt-sim_defconfig b/boards/cdns/xt-sim/xt-sim_defconfig similarity index 77% rename from boards/xtensa/xt-sim/xt-sim_defconfig rename to boards/cdns/xt-sim/xt-sim_defconfig index 73700f07275..9a055db716f 100644 --- a/boards/xtensa/xt-sim/xt-sim_defconfig +++ b/boards/cdns/xt-sim/xt-sim_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SOC_XTENSA_SAMPLE_CONTROLLER=y -CONFIG_BOARD_XT_SIM=y CONFIG_CONSOLE=y CONFIG_GEN_ISR_TABLES=y diff --git a/boards/circuit_dojo/feather/Kconfig.circuitdojo_feather b/boards/circuit_dojo/feather/Kconfig.circuitdojo_feather new file mode 100644 index 00000000000..74ef4bd8e27 --- /dev/null +++ b/boards/circuit_dojo/feather/Kconfig.circuitdojo_feather @@ -0,0 +1,8 @@ +# Circuit Dojo nRF9160 Feather configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# Copyright (c) 2020 Circuit Dojo LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CIRCUITDOJO_FEATHER + select SOC_NRF9160_SICA diff --git a/boards/circuit_dojo/feather/Kconfig.defconfig b/boards/circuit_dojo/feather/Kconfig.defconfig new file mode 100644 index 00000000000..f093911dc47 --- /dev/null +++ b/boards/circuit_dojo/feather/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Circuit Dojo nRF9160 Feather configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# Copyright (c) 2020 Circuit Dojo LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CIRCUITDOJO_FEATHER + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_CIRCUITDOJO_FEATHER_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS + +endif # BOARD_CIRCUITDOJO_FEATHER diff --git a/boards/arm/circuitdojo_feather_nrf9160/board.cmake b/boards/circuit_dojo/feather/board.cmake similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/board.cmake rename to boards/circuit_dojo/feather/board.cmake diff --git a/boards/circuit_dojo/feather/board.yml b/boards/circuit_dojo/feather/board.yml new file mode 100644 index 00000000000..0eb6ff5c4c0 --- /dev/null +++ b/boards/circuit_dojo/feather/board.yml @@ -0,0 +1,7 @@ +board: + name: circuitdojo_feather + vendor: circuitdojo + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160.dts b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160.dts similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160.dts rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160.dts diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160.yaml b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160.yaml similarity index 81% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160.yaml rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160.yaml index 05fd7a44189..ee93576b4af 100644 --- a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160.yaml +++ b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160.yaml @@ -1,4 +1,4 @@ -identifier: circuitdojo_feather_nrf9160 +identifier: circuitdojo_feather/nrf9160 name: CircuitDojo-Feather-nRF9160 type: mcu arch: arm diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common-pinctrl.dtsi b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_common-pinctrl.dtsi similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common-pinctrl.dtsi rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_common-pinctrl.dtsi diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common.dtsi b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_common.dtsi similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common.dtsi rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_common.dtsi diff --git a/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_defconfig b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_defconfig new file mode 100644 index 00000000000..b5a9bfd1f88 --- /dev/null +++ b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Required to enable 3V3 power rail +CONFIG_REGULATOR=y diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns.dts b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns.dts similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns.dts rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns.dts diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns.yaml b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns.yaml similarity index 80% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns.yaml rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns.yaml index 56905972e9f..582e28dbfc9 100644 --- a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns.yaml +++ b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns.yaml @@ -1,4 +1,4 @@ -identifier: circuitdojo_feather_nrf9160_ns +identifier: circuitdojo_feather/nrf9160/ns name: CircuitDojo-Feather-nRF9160-Non-Secure type: mcu arch: arm diff --git a/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns_defconfig b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns_defconfig new file mode 100644 index 00000000000..e87033d490d --- /dev/null +++ b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Required to enable 3V3 power rail +CONFIG_REGULATOR=y diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_partition_conf.dtsi b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_partition_conf.dtsi similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_partition_conf.dtsi rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_partition_conf.dtsi diff --git a/boards/arm/circuitdojo_feather_nrf9160/doc/img/circuitdojo_feather_nrf9160.jpg b/boards/circuit_dojo/feather/doc/img/circuitdojo_feather_nrf9160.jpg similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/doc/img/circuitdojo_feather_nrf9160.jpg rename to boards/circuit_dojo/feather/doc/img/circuitdojo_feather_nrf9160.jpg diff --git a/boards/arm/circuitdojo_feather_nrf9160/doc/img/nrf9160-feather-v31-features.jpg b/boards/circuit_dojo/feather/doc/img/nrf9160-feather-v31-features.jpg similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/doc/img/nrf9160-feather-v31-features.jpg rename to boards/circuit_dojo/feather/doc/img/nrf9160-feather-v31-features.jpg diff --git a/boards/circuit_dojo/feather/doc/index.rst b/boards/circuit_dojo/feather/doc/index.rst new file mode 100644 index 00000000000..0dd9bac2edd --- /dev/null +++ b/boards/circuit_dojo/feather/doc/index.rst @@ -0,0 +1,161 @@ +.. _circuitdojo_feather_nrf9160: + +nRF9160 Feather +############### + +.. figure:: img/circuitdojo_feather_nrf9160.jpg + :align: center + :alt: Circuit Dojo nRF9160 Feather + + nRF9160 Feather (Credit: Circuit Dojo) + +Overview +******** + +The nRF9160 Feather by Circuit Dojo is a single-board development +for bringing your LTE-M and NB-IoT applications to life. The circuitdojo_feather_nrf9160 +board configuration leverages the pre-existing support for the Nordic Semiconductor +nRF9160. Supported nRF9160 peripherals include: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +More information about the board can be found at the +`nRF9160 Feather Documentation`_. + + +Hardware +******** + +.. figure:: img/nrf9160-feather-v31-features.jpg + :align: center + :alt: nRF9160 Feather Features + +Connections and IOs +=================== + +The nRF9160 Feather has everything you know and love about +the Feather platform. Here are some of the highlights: + +LED +--- + +* D7 (blue) = P0.03 + +Push buttons and Switches +------------------------- + +* MODE = P0.12 +* RESET + +USB +--- + +Contains a USB/UART connection for both debugging and loading new +code using a UART Enabled MCUBoot. + +Standard Battery Connection +---------------------------- + +The nRF9160 Feather has a 2 pin battery connector on board. Lithium Polymer batteries > +300mA required. + +Nano SIM Holder +--------------- + +The nRF9160 Feather has a built-in nano SIM (4FF) holder located +on the bottom side. + + +Programming and Debugging +************************* + +circuitdojo_feather_nrf9160 has a Tag Connect TC2030-CTX-NL. It can be used +by most programmers like: + +* J-Link (the nRF53-DK is recommended) +* CMSIS-DAP based programmers + +Check out `Getting Started`_ for more info. + +Building an application +======================= + +In most cases you'll want to use the ``ns`` target with any of the Zephyr +or Nordic based examples. + +.. note:: + Trusted Firmware-M (TF-M) and building the ``ns`` target is not supported for this board. + +Some of the examples do not use secure mode, so they do not require the +``ns`` suffix. A great example of this is the `hello_world` below. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ screen /dev/ 115200 + +Replace :code:`` with the port where the nRF9160 Feather +can be found. In most cases (On Linux/Mac) it will be: :code:`/dev/tty.SLAB_USBtoUART`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: circuitdojo_feather_nrf9160 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons on the nRF9160 Feather +*************************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_common.dtsi`. + +References +********** + +.. target-notes:: + +**Side note** This page was based on the documentation for the nRF9160 DK. Thanks to Nordic for +developing a great platform! + +.. _nRF9160 Feather Documentation: https://docs.jaredwolff.com/nrf9160-introduction.html +.. _Getting Started: https://docs.jaredwolff.com/nrf9160-getting-started.html diff --git a/boards/arm/circuitdojo_feather_nrf9160/pre_dt_board.cmake b/boards/circuit_dojo/feather/pre_dt_board.cmake similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/pre_dt_board.cmake rename to boards/circuit_dojo/feather/pre_dt_board.cmake diff --git a/boards/circuit_dojo/index.rst b/boards/circuit_dojo/index.rst new file mode 100644 index 00000000000..63fe4f4a205 --- /dev/null +++ b/boards/circuit_dojo/index.rst @@ -0,0 +1,10 @@ +.. _boards-circuit-dojo: + +Circuit Dojo +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/common/openocd-nrf5.board.cmake b/boards/common/openocd-nrf5.board.cmake index 90ab5d32a4c..b8793628820 100644 --- a/boards/common/openocd-nrf5.board.cmake +++ b/boards/common/openocd-nrf5.board.cmake @@ -6,9 +6,14 @@ # # Boards which don't meet this convention can set this variable before # including this script. -if (NOT DEFINED OPENOCD_NRF5_SUBFAMILY) +if(NOT DEFINED OPENOCD_NRF5_SUBFAMILY) string(REGEX MATCH nrf5. OPENOCD_NRF5_SUBFAMILY "${BOARD}") + + if(HWMv2 AND "${OPENOCD_NRF5_SUBFAMILY}" STREQUAL "") + string(REGEX MATCH nrf5. OPENOCD_NRF5_SUBFAMILY "${BOARD_IDENTIFIER}") + endif() endif() + if("${OPENOCD_NRF5_SUBFAMILY}" STREQUAL "") message(FATAL_ERROR "Can't match nrf5 subfamily from BOARD name. " diff --git a/boards/contextual_electronics/abc/Kconfig b/boards/contextual_electronics/abc/Kconfig new file mode 100644 index 00000000000..b6a9479723e --- /dev/null +++ b/boards/contextual_electronics/abc/Kconfig @@ -0,0 +1,10 @@ +# ABC board configuration + +# Copyright (c) 2020 Analog Life LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_CONTEXTUALELECTRONICS_ABC diff --git a/boards/contextual_electronics/abc/Kconfig.contextualelectronics_abc b/boards/contextual_electronics/abc/Kconfig.contextualelectronics_abc new file mode 100644 index 00000000000..2dbfd946509 --- /dev/null +++ b/boards/contextual_electronics/abc/Kconfig.contextualelectronics_abc @@ -0,0 +1,7 @@ +# ABC board configuration + +# Copyright (c) 2020 Analog Life LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CONTEXTUALELECTRONICS_ABC + select SOC_NRF52840_QIAA diff --git a/boards/contextual_electronics/abc/Kconfig.defconfig b/boards/contextual_electronics/abc/Kconfig.defconfig new file mode 100644 index 00000000000..8568f02c34b --- /dev/null +++ b/boards/contextual_electronics/abc/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52840 BLE Cell board configuration + +# Copyright (c) 2020 Bilal Wasim +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CONTEXTUALELECTRONICS_ABC + +config BT_CTLR + default BT + +endif # BOARD_CONTEXTUALELECTRONICS_ABC diff --git a/boards/contextual_electronics/abc/board.cmake b/boards/contextual_electronics/abc/board.cmake new file mode 100644 index 00000000000..261663eef4e --- /dev/null +++ b/boards/contextual_electronics/abc/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(OPENOCD_NRF5_SUBFAMILY "nrf52") +board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") +board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/contextual_electronics/abc/board.yml b/boards/contextual_electronics/abc/board.yml new file mode 100644 index 00000000000..5c921f05256 --- /dev/null +++ b/boards/contextual_electronics/abc/board.yml @@ -0,0 +1,5 @@ +board: + name: contextualelectronics_abc + vendor: contextualelectronics + socs: + - name: nrf52840 diff --git a/boards/arm/contextualelectronics_abc/contextualelectronics_abc-pinctrl.dtsi b/boards/contextual_electronics/abc/contextualelectronics_abc-pinctrl.dtsi similarity index 100% rename from boards/arm/contextualelectronics_abc/contextualelectronics_abc-pinctrl.dtsi rename to boards/contextual_electronics/abc/contextualelectronics_abc-pinctrl.dtsi diff --git a/boards/arm/contextualelectronics_abc/contextualelectronics_abc.dts b/boards/contextual_electronics/abc/contextualelectronics_abc.dts similarity index 100% rename from boards/arm/contextualelectronics_abc/contextualelectronics_abc.dts rename to boards/contextual_electronics/abc/contextualelectronics_abc.dts diff --git a/boards/arm/contextualelectronics_abc/contextualelectronics_abc.yaml b/boards/contextual_electronics/abc/contextualelectronics_abc.yaml similarity index 100% rename from boards/arm/contextualelectronics_abc/contextualelectronics_abc.yaml rename to boards/contextual_electronics/abc/contextualelectronics_abc.yaml diff --git a/boards/arm/contextualelectronics_abc/contextualelectronics_abc_defconfig b/boards/contextual_electronics/abc/contextualelectronics_abc_defconfig similarity index 75% rename from boards/arm/contextualelectronics_abc/contextualelectronics_abc_defconfig rename to boards/contextual_electronics/abc/contextualelectronics_abc_defconfig index fce13936984..2908364b9c5 100644 --- a/boards/arm/contextualelectronics_abc/contextualelectronics_abc_defconfig +++ b/boards/contextual_electronics/abc/contextualelectronics_abc_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_CONTEXTELEC_ABC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/contextualelectronics_abc/doc/img/contextualelectronics_abc.jpg b/boards/contextual_electronics/abc/doc/img/contextualelectronics_abc.jpg similarity index 100% rename from boards/arm/contextualelectronics_abc/doc/img/contextualelectronics_abc.jpg rename to boards/contextual_electronics/abc/doc/img/contextualelectronics_abc.jpg diff --git a/boards/arm/contextualelectronics_abc/doc/index.rst b/boards/contextual_electronics/abc/doc/index.rst similarity index 100% rename from boards/arm/contextualelectronics_abc/doc/index.rst rename to boards/contextual_electronics/abc/doc/index.rst diff --git a/boards/arm/bl654_sensor_board/pre_dt_board.cmake b/boards/contextual_electronics/abc/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl654_sensor_board/pre_dt_board.cmake rename to boards/contextual_electronics/abc/pre_dt_board.cmake diff --git a/boards/contextual_electronics/index.rst b/boards/contextual_electronics/index.rst new file mode 100644 index 00000000000..d8f51610c4a --- /dev/null +++ b/boards/contextual_electronics/index.rst @@ -0,0 +1,10 @@ +.. _boards-contextual-electronics: + +Contextual Electronics +###################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble b/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble new file mode 100644 index 00000000000..450f6530657 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble @@ -0,0 +1,10 @@ +# PSoC6 BLE Pioneer Kit configuration + +# Copyright (c) 2018 Cypress +# Copyright (c) 2020 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CKIT_062_BLE + select SOC_PART_NUMBER_CY8C6347BZI_BLD53 + select SOC_CY8C6347_M0 if BOARD_CY8CKIT_062_BLE_CY8C6347_M0 + select SOC_CY8C6347_M4 if BOARD_CY8CKIT_062_BLE_CY8C6347_M4 diff --git a/boards/cypress/cy8ckit_062_ble/board.cmake b/boards/cypress/cy8ckit_062_ble/board.cmake new file mode 100644 index 00000000000..8a2483e4e8e --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/board.cmake @@ -0,0 +1,15 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_BOARD_CY8CKIT_062_BLE_CY8C6347_M0) + board_runner_args(jlink "--device=CY8C6xx7_CM0p" "--speed=2000") +elseif(CONFIG_BOARD_CY8CKIT_062_BLE_CY8C6347_M4) + board_runner_args(jlink "--device=CY8C6xx7_CM4" "--speed=2000") +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/cypress/cy8ckit_062_ble/board.yml b/boards/cypress/cy8ckit_062_ble/board.yml new file mode 100644 index 00000000000..f0b1325911a --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/board.yml @@ -0,0 +1,11 @@ +board: + name: cy8ckit_062_ble + vendor: cypress + revision: + format: "major.minor.patch" + default: "0.0.0" + revisions: + - name: "0.0.0" + - name: "1.0.0" + socs: + - name: cy8c6347 diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0.dts b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0.dts rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_0_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_0_0_0.overlay rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml new file mode 100644 index 00000000000..311c88f58ac --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020-2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m0 +name: Cypress PSoC6 BLE Pioneer Kit (M0) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - arduino_spi + - gpio + - spi +vendor: cypress diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_1_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_1_0_0.overlay rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml new file mode 100644 index 00000000000..c3bcfac49c5 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020-2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m0 +name: Cypress PSoC6 BLE Pioneer Kit (M0) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - arduino_spi + - gpio + - spi +vendor: cypress diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig new file mode 100644 index 00000000000..fefeed4980f --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_BUILD_OUTPUT_HEX=y + +# UART driver +CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4.dts b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4.dts rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_0_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_0_0_0.overlay rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml new file mode 100644 index 00000000000..ba22e8aa624 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020-2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m4 +name: Cypress PSoC6 BLE Pioneer Kit (M4) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - gpio +vendor: cypress diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml new file mode 100644 index 00000000000..bd4a3affce9 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020-2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m4 +name: Cypress PSoC6 BLE Pioneer Kit (M4) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - gpio +vendor: cypress diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig new file mode 100644 index 00000000000..fefeed4980f --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_BUILD_OUTPUT_HEX=y + +# UART driver +CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_ble/doc/img/cy8ckit-062-ble.jpg b/boards/cypress/cy8ckit_062_ble/doc/img/cy8ckit-062-ble.jpg similarity index 100% rename from boards/arm/cy8ckit_062_ble/doc/img/cy8ckit-062-ble.jpg rename to boards/cypress/cy8ckit_062_ble/doc/img/cy8ckit-062-ble.jpg diff --git a/boards/cypress/cy8ckit_062_ble/doc/index.rst b/boards/cypress/cy8ckit_062_ble/doc/index.rst new file mode 100644 index 00000000000..155f94f7b03 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/doc/index.rst @@ -0,0 +1,305 @@ +.. _cy8ckit_062_ble: + +INFINEON PSoC63 BLE Pioneer Kit +############################### + +Overview +******** + +The PSoC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) is a hardware platform that +enables design and debug of the Cypress PSoC 63 BLE MCU. + +The PSoC 6 BLE Pioneer Kit features the PSoC 63 MCU: a dual-core MCU, with a +150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm +Cortex-M0+ that supports low-power operations, 1MB of Flash, 288KB of SRAM, +an integrated BLE 4.2 radio, 78 GPIO, 7 programmable analog blocks, 12 +programmable digital blocks, and capacitive-sensing with CapSense. + +The PSoC 6 BLE Pioneer board offers compatibility with Arduino shields, a +512-Mb NOR flash, onboard programmer/debugger (KitProg2), USB Type-C power +delivery system (EZ-PD™ CCG3), 5-segment CapSense slider, two CapSense +buttons, one CapSense proximity sensing header, an RGB LED, two user LEDs, +and one push button. + +The CY8CKIT-062-BLE package includes a CY8CKIT-028-EPD E-INK Display Shield +that contains a 2.7-inch E-INK display, a motion sensor, a thermistor, and a +PDM microphone. The kit package also contains a CY5677 CySmart BLE 4.2 USB +Dongle that is factory-programmed to emulate a BLE GAP Central device, +enabling you to emulate a BLE host on your computer. + +The Cortex-M0+ is a primary core on the board's SoC. It starts first and +enables the CM4 core. + +.. image:: img/cy8ckit-062-ble.jpg + :align: center + :alt: CY8CKIT_062_BLE + +1. Battery charging indicator (LED6) +2. USB PD output voltage availability indicator (LED7) +3. KitProg2 USB Type-C connector (J10) +4. Cypress EZ-PD™ CCG3 Type-C Port Controller with PD (CYPD3125-40LQXI, U3) +5. KitProg2 programming mode selection button (SW3) +6. KitProg2 I/O header (J6)1 +7. KitProg2 programming/custom application header (J7)1 +8. External power supply connector (J9) +9. PSoC 6 BLE user button (SW2) +10. KitProg2 application selection button (SW4) +11. Digilent® Pmod™ compatible I/O header (J14)1 +12. Power LED (LED4) +13. KitProg2 status LEDs (LED1, LED2, and LED3) +14. PSoC 6 reset button (SW1) +15. PSoC 6 I/O header (J18, J19 and J20) +16. Arduino™ Uno R3 compatible power header (J1) +17. PSoC 6 debug and trace header (J12) +18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4) +19. PSoC 6 program and debug header (J11) +20. KitProg2 programming target selection switch (SW6) +21. CapSense slider and buttons +22. CapSense proximity header (J13) +23. PSoC 6 BLE VDD selection switch (SW5) +24. PSoC 6 BLE power monitoring jumper (J8)2 +25. Arduino Uno R3 compatible ICSP header (J5)1 +26. PSoC 6 user LEDs (LED8 and LED9) +27. RGB LED (LED5) +28. Cypress 512-Mbit serial NOR Flash memory (S25FL512S, U4) +29. Cypress serial Ferroelectric RAM (U5)1 +30. VBACKUP and PMIC control selection switch (SW7)2 +31. Cypress PSoC 6 BLE (CY8C6347BZI-BLD53, U1) +32. BLE Antenna +33. U.FL connector for external antenna (J17)1 +34. Cypress main voltage regulator (MB39C022G, U6) +35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) +36. Battery connector (J15)1,2 +37. USB PD output voltage (9V/12V) connector (J16) + +Hardware +******** + +For more information about the PSoC 63 BLE MCU SoC and CY8CKIT-062-BLE board: + +- `PSoC 63 BLE MCU SoC Website`_ +- `PSoC 63 BLE MCU Datasheet`_ +- `PSoC 63 BLE MCU Architecture Reference Manual`_ +- `PSoC 63 BLE MCU Register Reference Manual`_ +- `CY8CKIT-062-BLE Website`_ +- `CY8CKIT-062-BLE User Guide`_ +- `CY8CKIT-062-BLE Schematics`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-----------------------+ +| PINCTRL | on-chip | pin control | ++-----------+------------+-----------------------+ +| SPI | on-chip | spi | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-----------------------+ + + +The default configurations can be found in the Kconfig +:zephyr_file:`boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig` for +Cortex-M0+ and on the Kconfig +:zephyr_file:`boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig` for +Cortex-M4 + +System Clock +============ + +The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for +the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the +system clock are provided in the SOC, depending on your system requirements. + +Serial Port +=========== + +The PSoC 63 BLE MCU SoC has 8 SCB blocks and each one can be configured as +UART/SPI/I2C interfaces for serial communication. At the moment UART5 on SCB5 +and UART6 on SCB6 are configured. SCB5 is connected to the onboard KitProg2's +USB-UART Bridge working as a serial console interface. SCB6 to P13_0, P13_1 +pins on the J3 of the Arduino Uno R3 compatible PSoC6 I/O header for general +purposes. + +OpenOCD Installation +==================== + +To get the OpenOCD package, it is required that you + +1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox +2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox + export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts +3. Add the OpenOCD executable file's path to west flash/debug. +4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd +5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd + +Programming and Debugging +************************* + +The CY8CKIT-062-BLE includes an onboard programmer/debugger (KitProg2) with +mass storage programming to provide debugging, flash programming, and serial +communication over USB. There are also PSoC 6 program and debug headers J11 +and J12 that can be used with Segger J-Link [default]. +A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and +Cy_WDT_Disable(). + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cy8ckit_062_ble/cy8c6347/m0 + :goals: build + :compact: + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cy8ckit_062_ble/cy8c6347/m0 + :goals: flash + :compact: + + You should see "Hello World! cy8ckit_062_ble" in your terminal. + +Running on Dual Core +******************** + +#. Build the Zephyr kernel and the :zephyr:code-sample:`button` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: cy8ckit_062_ble/cy8c6347/m4 + :goals: build + :compact: + +#. If you have a USB-Serial adapter, you can connect SBC[UART]-6 on Arduino + header. Schematic should be checked for connections. Run your favorite + terminal program again now listen for another output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: cy8ckit_062_ble/cy8c6347/m4 + :goals: flash + :compact: + +#. Configure Cortex-M0+ to enable Cortex-M4: + + The last step flash the M4 image on the flash. However, Cortex-M0 by default + doesn't start the M4 and nothing will happen. To enable Cortex-M4 CPU, + repeat the steps on programming and debug and add the following parameter + when performing the build process. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cy8ckit_062_ble/cy8c6347/m0 + :goals: build flash + :gen-args: -DCONFIG_SOC_PSOC6_M0_ENABLES_M4=y + :compact: + + Now you can press button SW-2 and see LED-9 blink at same time you have the + "Hello World! cy8ckit_062_ble" in the your terminal. + +Board Revision +************** + +The CY8CKIT-062-BLE KitProg2 shares connections with Arduino-R3 header. This +connections may not allow the correct use of shields. The default board +revision (0.0.0) allows use of default connections. The use of Arduino headers +are only possible after rework the board and using the revision 1.0.0. + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application for + board revision 1.0.0: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cy8ckit_062_ble@1.0.0/cy8c6347/m0 + :goals: build + :compact: + +#. The differences from version 0.0.0 to 1.0.0: + ++-------------+------------+------------+ +| Connection | 0.0.0 | 1.0.0 | ++=============+============+============+ +| CDC-COM RX | P5_0 | P9_0 | ++-------------+------------+------------+ +| CDC-COM TX | P5_1 | P9_1 | ++-------------+------------+------------+ +| R77 | X | | ++-------------+------------+------------+ +| R78 | | X | ++-------------+------------+------------+ + + +The P9 pins are available at J2. Those signals should be routed to J6. + +J2-2 to J6-14 +J2-4 to J6-13 + +The most complex part is short circuit pins 14 and 15 from U13. That connect +UART_RTS with UART_CTS from KitProg2. + +References +********** + +.. _PSoC 63 BLE MCU SoC Website: + https://www.cypress.com/products/32-bit-arm-cortex-m4-cortex-m0-psoc-63-connectivity-line + +.. _PSoC 63 BLE MCU Datasheet: + https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-63-ble-datasheet-programmable-system-chip-psoc + +.. _PSoC 63 BLE MCU Architecture Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-63-ble-architecture-technical-reference + +.. _PSoC 63 BLE MCU Register Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-cy8c63x6-cy8c63x7-cy8c63x6-cy8c63x7-registers + +.. _CY8CKIT-062-BLE Website: + https://www.cypress.com/documentation/development-kitsboards/psoc-6-ble-pioneer-kit-cy8ckit-062-ble + +.. _CY8CKIT-062-BLE User Guide: + https://www.cypress.com/file/390496/download + +.. _CY8CKIT-062-BLE Schematics: + https://www.cypress.com/file/417021/download diff --git a/boards/arm/cy8ckit_062_ble/support/openocd.cfg b/boards/cypress/cy8ckit_062_ble/support/openocd.cfg similarity index 100% rename from boards/arm/cy8ckit_062_ble/support/openocd.cfg rename to boards/cypress/cy8ckit_062_ble/support/openocd.cfg diff --git a/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt b/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt new file mode 100644 index 00000000000..e77e648b62a --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt @@ -0,0 +1,10 @@ +# PSoC6 WiFi-BT Pioneer Kit configuration + +# Copyright (c) 2018 Cypress +# Copyright (c) 2020 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CKIT_062_WIFI_BT + select SOC_PART_NUMBER_CY8C6247BZI_D54 + select SOC_CY8C6247_M0 if BOARD_CY8CKIT_062_WIFI_BT_CY8C6247_M0 + select SOC_CY8C6247_M4 if BOARD_CY8CKIT_062_WIFI_BT_CY8C6247_M4 diff --git a/boards/arm/cy8ckit_062_wifi_bt/board.cmake b/boards/cypress/cy8ckit_062_wifi_bt/board.cmake similarity index 100% rename from boards/arm/cy8ckit_062_wifi_bt/board.cmake rename to boards/cypress/cy8ckit_062_wifi_bt/board.cmake diff --git a/boards/cypress/cy8ckit_062_wifi_bt/board.yml b/boards/cypress/cy8ckit_062_wifi_bt/board.yml new file mode 100644 index 00000000000..f5113e41a55 --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/board.yml @@ -0,0 +1,5 @@ +board: + name: cy8ckit_062_wifi_bt + vendor: cypress + socs: + - name: cy8c6247 diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts similarity index 100% rename from boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0.dts rename to boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml new file mode 100644 index 00000000000..3b2372a04dc --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml @@ -0,0 +1,19 @@ +# +# Copyright (c) 2018, Cypress +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_wifi_bt/cy8c6247/m0 +name: Cypress PSoC6 WiFi-BT Pioneer Kit (M0) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio +vendor: cypress diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig new file mode 100644 index 00000000000..fd9d1d319ab --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2018, Cypress +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_BUILD_OUTPUT_HEX=y + +# UART driver +CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts similarity index 100% rename from boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4.dts rename to boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml new file mode 100644 index 00000000000..df5c8c0b53b --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml @@ -0,0 +1,19 @@ +# +# Copyright (c) 2018, Cypress +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_wifi_bt/cy8c6247/m4 +name: Cypress PSoC6 WiFi-BT Pioneer Kit (M4) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio +vendor: cypress diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig new file mode 100644 index 00000000000..fd9d1d319ab --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2018, Cypress +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_BUILD_OUTPUT_HEX=y + +# UART driver +CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_wifi_bt/doc/img/cy8ckit_062_wifi_bt_m0.jpg b/boards/cypress/cy8ckit_062_wifi_bt/doc/img/cy8ckit_062_wifi_bt_m0.jpg similarity index 100% rename from boards/arm/cy8ckit_062_wifi_bt/doc/img/cy8ckit_062_wifi_bt_m0.jpg rename to boards/cypress/cy8ckit_062_wifi_bt/doc/img/cy8ckit_062_wifi_bt_m0.jpg diff --git a/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst b/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst new file mode 100644 index 00000000000..d7e20c9bcb0 --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst @@ -0,0 +1,208 @@ +.. _cy8ckit_062_wifi_bt: + +INFINEON PSoC6 WiFi-BT Pioneer Kit +################################## + +Overview +******** + +The PSoC 6 WiFi-BT Pioneer Kit (CY8CKIT-062-WiFi-BT) is a low-cost hardware +platform that enables design and debug of the PSoC 62 MCU and the Murata +LBEE5KL1DX Module (CYW4343W WiFi + Bluetooth Combo Chip). + +The PSoC 6 WiFi-BT Pioneer Kit features the PSoC 62 MCU: a +dual-core MCU, with a 150-MHz Arm Cortex-M4 as the primary application +processor and a 100-MHz Arm Cortex-M0+ that supports low-power operations, +1MB of Flash, 288KB of SRAM, 104 GPIO, 7 programmable analog blocks, +56 programmable digital blocks, Full-Speed USB, a serial memory interface, +a PDM-PCM digital microphone interface, and industry-leading capacitive-sensing +with CapSense. + +The PSoC 6 WiFi-BT Pioneer board offers compatibility with Arduino shields. + +The Cortex-M0+ is a primary core on the board's SoC. It starts first and +enables the CM4 core. + +.. image:: img/cy8ckit_062_wifi_bt_m0.jpg + :align: center + :alt: CY8CKIT_062_WIFI_BT + +1. USB PD output voltage availability indicator (LED7) +2. Battery charging indicator (LED6) +3. KitProg2 USB Type-C connector (J10) +4. Cypress EZ-PD™ CCG3 Type-C Port Controller with PD (CYPD3125-40LQXI, U3) +5. KitProg2 programming mode selection button (SW3) +6. KitProg2 I/O header (J6)1 +7. KitProg2 programming/custom application header (J7)1 +8. External power supply connector (J9) +9. PSoC 6 user button (SW2) +10. KitProg2 application selection button (SW4) +11. Digilent® Pmod™ compatible I/O header (J14)1 +12. Power LED (LED4) +13. KitProg2 status LEDs (LED1, LED2, and LED3) +14. PSoC 6 reset button (SW1) +15. PSoC 6 I/O header (J18, J19 and J20) +16. Arduino™ Uno R3 compatible power header (J1) +17. PSoC 6 debug and trace header (J12) +18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4) +19. PSoC 6 program and debug header (J11) +20. CapSense proximity header (J13) +21. CapSense slider and buttons +22. PSoC 6 VDD selection switch (SW5) +23. Cypress 512-Mbit serial NOR Flash memory (S25-FL512S, U4) +24. PSoC 6 user LEDs (LED8 and LED9) +25. RGB LED (LED5) +26. WiFi/BT module (LBEE5KL 1DX, U6) +27. Cypress serial Ferroelectric RAM (U5)1 +28. WiFi-BT Antenna +29. VBACKUP and PMIC control selection switch (SW7)2 +30. PSoC 6 USB device Type-C connector (J28) +31. Cypress PSoC 6 (CY8C6247BZI-D54, U1) +32. PSoC 6 USB Host Type-A connector (J27) +33. Arduino Uno R3 compatible ICSP header (J5)1 +34. PSoC 6 power monitoring jumper (J8)2 +35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) +36. Battery connector (J15)1,2 +37. USB PD output voltage (9V/12V) connector (J16) + +Hardware +******** + +For more information about the PSoC 62 MCU SoC and CY8CKIT-062-WiFi-BT board: + +- `PSoC 62 MCU SoC Website`_ +- `PSoC 62 MCU Datasheet`_ +- `PSoC 62 MCU Architecture Reference Manual`_ +- `PSoC 62 MCU Register Reference Manual`_ +- `CY8CKIT-062-WiFi-BT Website`_ +- `CY8CKIT-062-WiFi-BT User Guide`_ +- `CY8CKIT-062-WiFi-BT Schematics`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| PINCTRL | on-chip | pin control | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-----------------------+ + + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig`. + + +System Clock +============ + +The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for +the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the +system clock are provided in the SOC, depending on your system requirements. + +Serial Port +=========== + +The PSoC 62 MCU SoC has 9 SCB blocks 8 of each can be configured as UART +interfaces for serial communication. At the moment UART5 on SCB5 and UART6 on +SCB6 are configured. SCB5 is connected to the onboard KitProg2's USB-UART +Bridge, SCB6 to P12_0, P12_1 pins on the J3 of the Arduino Uno R3 compatible +PSoC6 I/O header. + +OpenOCD Installation +==================== + +To get the OpenOCD package, it is required that you + +1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox +2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox + export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts +3. Add the OpenOCD executable file's path to west flash/debug. +4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd +5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd + + +Programming and Debugging +************************* + +The CY8CKIT-062-WiFi-BT includes an onboard programmer/debugger (KitProg2) with +mass storage programming to provide debugging, flash programming, and serial +communication over USB. There are also PSoC 6 program and debug headers J11 +and J12 that can be used with Segger J-Link. +A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and +Cy_WDT_Disable(). + +Only the CM0+ core starts by default after the MCU reset. In order to have +CM4 core working FW for both cores should be written into Flash. CM0+ FW +should starts the CM4 core at one point using +Cy_SysEnableCM4(CM4_START_ADDRESS); call. CM4_START_ADDRESS is 0x10060000 in +the current configuration. The CM0+/CM4 Flash/SRAM areas are defined in +:zephyr_file:`dts/arm/cypress/psoc6.dtsi`. + +Build the project for CM0+ + +.. zephyr-app-commands:: + :board: cy8ckit_062_wifi_bt/cy8c6247/m0 + :goals: build + +Switch the DevKit into CMSIS-DAP mode using SW3 (LED2 should blink) and flash +the board: + +.. code-block:: console + + $\bin\openocd -c "source [find interface/cmsis-dap.cfg]" \ + -c "transport select swd" -c "source [find target/psoc6.cfg]" \ + -c "if [catch {program {\samples\hello_world\build\zephyr\zephyr.elf}} ] \ + { echo {** Program operation failed **} } \ + else { echo {** Program operation completed successfully **} }" \ + -c "reset_config srst_only;reset run;psoc6.dap dpreg 0x04 0x00;shutdown" + +Switch the DevKit back using SW3. Open a serial terminal (minicom, putty, +etc.) and connect to the board with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and the following message will appear on the corresponding +serial port: + +.. code-block:: console + + ***** Booting Zephyr OS zephyr-v1.13.0-1877-g9d14874db1 ***** + Hello World! cy8ckit_062_wifi_bt + + +References +********** + +.. _PSoC 62 MCU SoC Website: + https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 + +.. _PSoC 62 MCU Datasheet: + https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-62-datasheet-programmable-system-chip-psoc-preliminary + +.. _PSoC 62 MCU Architecture Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-architecture-technical-reference-manual + +.. _PSoC 62 MCU Register Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-register-technical-reference-manual-trm + +.. _CY8CKIT-062-WiFi-BT Website: + https://www.cypress.com/documentation/development-kitsboards/psoc-6-wifi-bt-pioneer-kit + +.. _CY8CKIT-062-WiFi-BT User Guide: + https://www.cypress.com/file/407731/download + +.. _CY8CKIT-062-WiFi-BT Schematics: + https://www.cypress.com/file/420846/download diff --git a/boards/arm/cy8ckit_062_wifi_bt/support/openocd.cfg b/boards/cypress/cy8ckit_062_wifi_bt/support/openocd.cfg similarity index 100% rename from boards/arm/cy8ckit_062_wifi_bt/support/openocd.cfg rename to boards/cypress/cy8ckit_062_wifi_bt/support/openocd.cfg diff --git a/boards/cypress/cy8ckit_062s4/Kconfig.cy8ckit_062s4 b/boards/cypress/cy8ckit_062s4/Kconfig.cy8ckit_062s4 new file mode 100644 index 00000000000..db5e8c37451 --- /dev/null +++ b/boards/cypress/cy8ckit_062s4/Kconfig.cy8ckit_062s4 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 David Ullmann +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CKIT_062S4 + select SOC_CY8C6244LQI_S4D92 diff --git a/boards/arm/cy8ckit_062s4/board.cmake b/boards/cypress/cy8ckit_062s4/board.cmake similarity index 100% rename from boards/arm/cy8ckit_062s4/board.cmake rename to boards/cypress/cy8ckit_062s4/board.cmake diff --git a/boards/cypress/cy8ckit_062s4/board.yml b/boards/cypress/cy8ckit_062s4/board.yml new file mode 100644 index 00000000000..adb45b87c07 --- /dev/null +++ b/boards/cypress/cy8ckit_062s4/board.yml @@ -0,0 +1,5 @@ +board: + name: cy8ckit_062s4 + vendor: cypress + socs: + - name: cy8c6244lqi_s4d92 diff --git a/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.dts b/boards/cypress/cy8ckit_062s4/cy8ckit_062s4.dts similarity index 100% rename from boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.dts rename to boards/cypress/cy8ckit_062s4/cy8ckit_062s4.dts diff --git a/boards/cypress/cy8ckit_062s4/cy8ckit_062s4.yaml b/boards/cypress/cy8ckit_062s4/cy8ckit_062s4.yaml new file mode 100644 index 00000000000..aaa7d0c8305 --- /dev/null +++ b/boards/cypress/cy8ckit_062s4/cy8ckit_062s4.yaml @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 David Ullmann + +identifier: cy8ckit_062s4 +name: CY8CKIT-062S4 PSoC 62S4 +type: mcu +arch: arm +ram: 128 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio +vendor: cypress diff --git a/boards/cypress/cy8ckit_062s4/cy8ckit_062s4_defconfig b/boards/cypress/cy8ckit_062s4/cy8ckit_062s4_defconfig new file mode 100644 index 00000000000..04b8a04dda6 --- /dev/null +++ b/boards/cypress/cy8ckit_062s4/cy8ckit_062s4_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2023 David Ullmann +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_PINCTRL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_XIP=y + +CONFIG_SOC_PSOC6_CM0P_IMAGE_SLEEP=y diff --git a/boards/arm/cy8ckit_062s4/doc/img/cy8ckit_062s4.png b/boards/cypress/cy8ckit_062s4/doc/img/cy8ckit_062s4.png similarity index 100% rename from boards/arm/cy8ckit_062s4/doc/img/cy8ckit_062s4.png rename to boards/cypress/cy8ckit_062s4/doc/img/cy8ckit_062s4.png diff --git a/boards/cypress/cy8ckit_062s4/doc/index.rst b/boards/cypress/cy8ckit_062s4/doc/index.rst new file mode 100644 index 00000000000..f3a026b3b6b --- /dev/null +++ b/boards/cypress/cy8ckit_062s4/doc/index.rst @@ -0,0 +1,115 @@ +.. _cy8ckit_062s4: + +[INFINEON PSoC 62S4 Pioneer Kit] +################################ + +Overview +******** +The PSOC 62S4 Pioneer kit has a CY8C62x4 MCU, which is an ultra-low-power PSoC device specifically designed for battery-operated analog +sensing applications. It includes a 150-MHz Arm® Cortex®-M4 CPU as the primary application processor, a 100-MHz Arm® Cortex®-M0+ CPU that +supports low-power operations, up to 256 KB Flash and 128 KB SRAM, programmable analog sensing, +CapSense™ touch-sensing, and programmable digital peripherals. + +The board features an onboard +programmer/debugger (KitProg3), a 512-Mbit Quad SPI NOR flash, a micro-B connector for USB device +interface, a thermistor, an ambient light sensor, a 5-segment CapSense™ slider, two CapSense™ buttons, two +user LEDs, and a push button. The board supports operating voltages from 1.8 V to 3.3 V for PSoC™ 6 MCU. + +.. figure::img/cy8ckit_062s4.png + :width: 800px + :align: center + :alt: Board Name + + Board Name (Credit: ) + +Hardware +******** + +`CY8CKIT 062S4 Pioneer Kit Website`_ +`CY8CKIT 062S4 Pioneer Kit Guide`_ +`CY8CKIT 062S4 Pioneer Kit Schematic`_ +`CY8CKIT 062S4 Pioneer Kit Technical Reference Manual`_ +`CY8CKIT 062S4 Pioneer Kit Datasheet`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| PINCTRL | on-chip | pin control | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | ++-----------+------------+-----------------------+ + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/cypress/cy8ckit_062s4/cy8ckit_062s4_defconfig`. + +Clock Configuration +=================== + ++-----------+------------+-----------------------+ +| Clock | Source | Output Frequency | ++===========+============+=======================+ +| FLL | IMO | 100.0 MHz | ++-----------+------------+-----------------------+ +| PLL | IMO | 48.0 MHz | ++-----------+------------+-----------------------+ +| CLK_HF0 | CLK_PATH0 | 100.0 MHz | ++-----------+------------+-----------------------+ + +Fetch Binary Blobs +================== + +.. code-block:: console + + west blobs fetch hal_infineon + + +Build and flash hello world sample +********************************** + + +.. code-block:: console + + cd zephyr/samples/hello_world + west build -p auto -b cy8ckit_062s4 --pristine + west flash + picocom /dev/ttyACM0 -b 115200 + +OpenOCD Installation +==================== + +To get the OpenOCD package, it is required that you + +1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox +2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox + export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts +3. Add the OpenOCD executable file's path to west flash/debug. +4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd +5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd + +References +********** + +.. _CY8CKIT 062S4 Pioneer Kit Guide: + https://www.infineon.com/dgdl/Infineon-CY8CKIT_062S4_PSoC62S4_pioneer_kit_guide-UserManual-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017e962f98992207 + +.. _CY8CKIT 062S4 Pioneer Kit Website: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8ckit-062s4/?redirId=VL1508&utm_medium=referral&utm_source=cypress&utm_campaign=202110_globe_en_all_integration-dev_kit + +.. _CY8CKIT 062S4 Pioneer Kit Schematic: + https://www.infineon.com/dgdl/Infineon-CY8CKIT-062S4_PSoC_62S4_Pioneer_Kit_Schematic-PCBDesignData-v01_00-EN.pdf?fileId=8ac78c8c7d710014017d7153484d2081 + +.. _CY8CKIT 062S4 Pioneer Kit Technical Reference Manual: + https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C61X4CY8C62X4_REGISTERS_TECHNICAL_REFERENCE_MANUAL_(TRM)_PSOC_61_PSOC_62_MCU-AdditionalTechnicalInformation-v03_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0fb34f0627a7 + +.. _CY8CKIT 062S4 Pioneer Kit Datasheet: + https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_CY8C62X4-DataSheet-v12_00-EN.pdf?fileId=8ac78c8c7ddc01d7017ddd026d585901 diff --git a/boards/cypress/cy8cproto_062_4343w/Kconfig.cy8cproto_062_4343w b/boards/cypress/cy8cproto_062_4343w/Kconfig.cy8cproto_062_4343w new file mode 100644 index 00000000000..6af485a6bed --- /dev/null +++ b/boards/cypress/cy8cproto_062_4343w/Kconfig.cy8cproto_062_4343w @@ -0,0 +1,7 @@ +# CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit + +# Copyright (c) 2021 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CPROTO_062_4343W + select SOC_CY8C624ABZI_S2D44 diff --git a/boards/cypress/cy8cproto_062_4343w/Kconfig.defconfig b/boards/cypress/cy8cproto_062_4343w/Kconfig.defconfig new file mode 100644 index 00000000000..270370c7660 --- /dev/null +++ b/boards/cypress/cy8cproto_062_4343w/Kconfig.defconfig @@ -0,0 +1,54 @@ +# CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit configuration + +# Copyright (c) 2021 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CY8CPROTO_062_4343W + +if WIFI || BT + +# Select AIROC part and module +choice AIROC_PART + default CYW4343W +endchoice + +choice CYW4343W_MODULE + default CYW4343W_MURATA_1DX +endchoice + +endif # WIFI || BT + +if WIFI + +config WIFI_AIROC + default y + +# Enable L2 Ethernet +config NET_L2_ETHERNET + default y + +endif # WIFI + +if BT + +# Select HCI components +config UART + bool + default y + +config BT_UART + default y + +choice BT_HCI_BUS_TYPE + default BT_H4 +endchoice + +endif # BT + +# Heap Pool Size +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 15000 if WIFI + default 4096 + +endif # BOARD_CY8CPROTO_062_4343W diff --git a/boards/arm/cy8cproto_062_4343w/board.cmake b/boards/cypress/cy8cproto_062_4343w/board.cmake similarity index 100% rename from boards/arm/cy8cproto_062_4343w/board.cmake rename to boards/cypress/cy8cproto_062_4343w/board.cmake diff --git a/boards/cypress/cy8cproto_062_4343w/board.yml b/boards/cypress/cy8cproto_062_4343w/board.yml new file mode 100644 index 00000000000..575dbf83414 --- /dev/null +++ b/boards/cypress/cy8cproto_062_4343w/board.yml @@ -0,0 +1,5 @@ +board: + name: cy8cproto_062_4343w + vendor: cypress + socs: + - name: cy8c624abzi_s2d44 diff --git a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi similarity index 100% rename from boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi rename to boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi diff --git a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w-pinctrl.dtsi b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w-pinctrl.dtsi similarity index 100% rename from boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w-pinctrl.dtsi rename to boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w-pinctrl.dtsi diff --git a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w.dts b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w.dts similarity index 100% rename from boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w.dts rename to boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w.dts diff --git a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml similarity index 100% rename from boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml rename to boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml diff --git a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig similarity index 84% rename from boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig rename to boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig index 3dd8e0eac78..19975610f60 100644 --- a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig +++ b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig @@ -3,10 +3,6 @@ # SPDX-License-Identifier: Apache-2.0 # -# Choice PSoC 6 Series and MPN -CONFIG_SOC_SERIES_PSOC_62=y -CONFIG_SOC_CY8C624ABZI_S2D44=y - # General configuration CONFIG_CORTEX_M_SYSTICK=y CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/cy8cproto_062_4343w/doc/img/board.jpg b/boards/cypress/cy8cproto_062_4343w/doc/img/board.jpg similarity index 100% rename from boards/arm/cy8cproto_062_4343w/doc/img/board.jpg rename to boards/cypress/cy8cproto_062_4343w/doc/img/board.jpg diff --git a/boards/cypress/cy8cproto_062_4343w/doc/index.rst b/boards/cypress/cy8cproto_062_4343w/doc/index.rst new file mode 100644 index 00000000000..e1be366086c --- /dev/null +++ b/boards/cypress/cy8cproto_062_4343w/doc/index.rst @@ -0,0 +1,184 @@ +.. _cy8cproto_062_4343w: + +INFINEON CY8CPROTO-062-4343W +############################ + +Overview +******** + +The CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Prototyping Kit is a low-cost hardware +platform that enables design and debug of PSoC 6 MCUs. It comes with a Murata +LBEE5KL1DX module, based on the CYW4343W combo device, industry-leading CAPSENSE +for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD +card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone, and a thermistor. + +This kit is designed with a snap-away form-factor, allowing the user to separate +the different components and features that come with this kit and use independently. +In addition, support for Digilent's Pmod interface is also provided with this kit. + +.. image:: img/board.jpg + :align: center + :alt: CY8CPROTO-062-4343W + +Hardware +******** + +For more information about the PSoC 62 MCU SoC and CY8CPROTO-062-4343W board: + +- `PSoC 62 MCU SoC Website`_ +- `PSoC 62 MCU Datasheet`_ +- `PSoC 62 MCU Architecture Reference Manual`_ +- `PSoC 62 MCU Register Reference Manual`_ +- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Website`_ +- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT User Guide`_ +- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Schematics`_ + +Kit Features: +============= + +- Support of up to 2MB Flash and 1MB SRAM +- Dedicated SDHC to interface with WICED wireless devices. +- Delivers dual-cores, with a 150-MHz Arm Cortex-M4 as the primary + application processor and a 100-MHz Arm Cortex-M0+ as the secondary + processor for low-power operations. +- Supports Full-Speed USB, capacitive-sensing with CAPSENSE, a PDM-PCM + digital microphone interface, a Quad-SPI interface, 13 serial communication + blocks, 7 programmable analog blocks, and 56 programmable digital blocks. + +Kit Contents: +============= + +- PSoC 6 Wi-Fi BT Prototyping Board +- USB Type-A to Micro-B cable +- Quick Start Guide + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| GPIO | on-chip | GPIO | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-----------------------+ + + +The default configuration can be found in the Kconfig + +:zephyr_file:`boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig` + + +System Clock +============ + +The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for +the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the +system clock are provided in the SOC, depending on your system requirements. + + +Fetch Binary Blobs +****************** + +cy8cproto_062_4343w board optionally uses binary blobs for features +(e.g WIFI/Bluetooth chip firmware, CM0p prebuilt images, etc). + +To fetch Binary Blobs: + +.. code-block:: console + + west blobs fetch hal_infineon + + +Build blinking led sample +************************* + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. code-block:: console + + cd zephyr + west build -p auto -b cy8cproto_062_4343w samples/basic/blink + +OpenOCD Installation +==================== + +To get the OpenOCD package, it is required that you + +1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox +2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox + export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts +3. Add the OpenOCD executable file's path to west flash/debug. +4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd +5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd + + +Programming and Debugging +************************* + +The CY8CPROTO-062-4343W includes an onboard programmer/debugger (KitProg2) with +mass storage programming to provide debugging, flash programming, and serial +communication over USB. Flash and debug commands must be pointed to the Cypress +OpenOCD you downloaded above. + +On Windows: + +.. code-block:: console + + west flash --openocd path/to/infineon/openocd/bin/openocd.exe + west debug --openocd path/to/infineon/openocd/bin/openocd.exe + +On Linux: + +.. code-block:: console + + west flash --openocd path/to/infineon/openocd/bin/openocd + west debug --openocd path/to/infineon/openocd/bin/openocd + +Once the gdb console starts after executing the west debug command, you may +now set breakpoints and perform other standard GDB debugging on the PSoC 6 CM4 core. + +Errata +====== + ++------------------------------------------------+----------------------------------------+ +| Problem | Solution | ++================================================+========================================+ +| The GPIO_INT_TRIG_BOTH interrupt is not raised | This will be fixed in a future release.| +| when the associated GPIO is asserted. | | ++------------------------------------------------+----------------------------------------+ +| GDB experiences a timeout error connecting to | This will be fixed in a future release.| +| a server instance started by west debugserver. | | ++------------------------------------------------+----------------------------------------+ + +.. _PSoC 62 MCU SoC Website: + https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 + +.. _PSoC 62 MCU Datasheet: + https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-62-datasheet-programmable-system-chip-psoc-preliminary + +.. _PSoC 62 MCU Architecture Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-architecture-technical-reference-manual + +.. _PSoC 62 MCU Register Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-register-technical-reference-manual-trm + +.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Website: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/ + +.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT User Guide: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/#!?fileId=8ac78c8c7d0d8da4017d0f0118571844 + +.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Schematics: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/#!?fileId=8ac78c8c7d0d8da4017d0f01126b183f + +.. _Infineon OpenOCD: + https://github.com/infineon/openocd/releases/tag/release-v4.3.0 diff --git a/boards/arm/cy8cproto_062_4343w/support/openocd.cfg b/boards/cypress/cy8cproto_062_4343w/support/openocd.cfg similarity index 100% rename from boards/arm/cy8cproto_062_4343w/support/openocd.cfg rename to boards/cypress/cy8cproto_062_4343w/support/openocd.cfg diff --git a/boards/cypress/cy8cproto_063_ble/Kconfig.cy8cproto_063_ble b/boards/cypress/cy8cproto_063_ble/Kconfig.cy8cproto_063_ble new file mode 100644 index 00000000000..23763f500c3 --- /dev/null +++ b/boards/cypress/cy8cproto_063_ble/Kconfig.cy8cproto_063_ble @@ -0,0 +1,8 @@ +# CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit +# +# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CPROTO_063_BLE + select SOC_CYBLE_416045_02 diff --git a/boards/cypress/cy8cproto_063_ble/Kconfig.defconfig b/boards/cypress/cy8cproto_063_ble/Kconfig.defconfig new file mode 100644 index 00000000000..2d079f63a6b --- /dev/null +++ b/boards/cypress/cy8cproto_063_ble/Kconfig.defconfig @@ -0,0 +1,13 @@ +# CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit + +# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CY8CPROTO_063_BLE + +choice BT_HCI_BUS_TYPE + default BT_PSOC6_BLESS if BT +endchoice + +endif # BOARD_CY8CPROTO_063_BLE diff --git a/boards/arm/cy8cproto_063_ble/board.cmake b/boards/cypress/cy8cproto_063_ble/board.cmake similarity index 100% rename from boards/arm/cy8cproto_063_ble/board.cmake rename to boards/cypress/cy8cproto_063_ble/board.cmake diff --git a/boards/cypress/cy8cproto_063_ble/board.yml b/boards/cypress/cy8cproto_063_ble/board.yml new file mode 100644 index 00000000000..b35cb08ec2f --- /dev/null +++ b/boards/cypress/cy8cproto_063_ble/board.yml @@ -0,0 +1,5 @@ +board: + name: cy8cproto_063_ble + vendor: cypress + socs: + - name: cyble_416045_02 diff --git a/boards/arm/cy8cproto_063_ble/cy8cproto_063_ble-pinctrl.dtsi b/boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble-pinctrl.dtsi similarity index 100% rename from boards/arm/cy8cproto_063_ble/cy8cproto_063_ble-pinctrl.dtsi rename to boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble-pinctrl.dtsi diff --git a/boards/arm/cy8cproto_063_ble/cy8cproto_063_ble.dts b/boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble.dts similarity index 100% rename from boards/arm/cy8cproto_063_ble/cy8cproto_063_ble.dts rename to boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble.dts diff --git a/boards/arm/cy8cproto_063_ble/cy8cproto_063_ble.yaml b/boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble.yaml similarity index 100% rename from boards/arm/cy8cproto_063_ble/cy8cproto_063_ble.yaml rename to boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble.yaml diff --git a/boards/arm/cy8cproto_063_ble/cy8cproto_063_ble_defconfig b/boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble_defconfig similarity index 89% rename from boards/arm/cy8cproto_063_ble/cy8cproto_063_ble_defconfig rename to boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble_defconfig index a3d7e7beab3..17d512d195d 100644 --- a/boards/arm/cy8cproto_063_ble/cy8cproto_063_ble_defconfig +++ b/boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble_defconfig @@ -4,10 +4,6 @@ # SPDX-Licence-Identifier: Apache-2.0 #*************************************************************************** -# Choice PSoC 6 Series and MPN -CONFIG_SOC_SERIES_PSOC_63=y -CONFIG_SOC_CYBLE_416045_02=y - # General configuration CONFIG_CORTEX_M_SYSTICK=y CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/cy8cproto_063_ble/doc/img/cy8cproto-063-ble.jpg b/boards/cypress/cy8cproto_063_ble/doc/img/cy8cproto-063-ble.jpg similarity index 100% rename from boards/arm/cy8cproto_063_ble/doc/img/cy8cproto-063-ble.jpg rename to boards/cypress/cy8cproto_063_ble/doc/img/cy8cproto-063-ble.jpg diff --git a/boards/cypress/cy8cproto_063_ble/doc/index.rst b/boards/cypress/cy8cproto_063_ble/doc/index.rst new file mode 100644 index 00000000000..8ef38711c8f --- /dev/null +++ b/boards/cypress/cy8cproto_063_ble/doc/index.rst @@ -0,0 +1,144 @@ +.. _cy8cproto_063_ble: + +INFINEON CY8CPROTO-063-BLE +########################### + +Overview +******** + +The PSoC 6 BLE Proto Kit (CY8CPROTO-063-BLE) is a hardware platform that +enables design and debug of the Cypress PSoC 63 BLE MCU. + +.. image:: img/cy8cproto-063-ble.jpg + :align: center + :alt: CY8CPROTO-063-BLE + +Hardware +******** + +For more information about the PSoC 63 BLE MCU SoC and CY8CPROTO-063-BLE board: + +- `PSoC 63 BLE MCU SoC Website`_ +- `PSoC 63 BLE MCU Datasheet`_ +- `PSoC 63 BLE MCU Architecture Reference Manual`_ +- `PSoC 63 BLE MCU Register Reference Manual`_ +- `CY8CPROTO-063-BLE Website`_ +- `CY8CPROTO-063-BLE User Guide`_ +- `CY8CPROTO-063-BLE Schematics`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-----------------------+ +| PINCTRL | on-chip | pin control | ++-----------+------------+-----------------------+ +| SPI | on-chip | spi | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-----------------------+ +| I2C | on-chip | I2C | ++-----------+------------+-----------------------+ +| PWM | on-chip | PWM | ++-----------+------------+-----------------------+ +| Counter | on-chip | Counter | ++-----------+------------+-----------------------+ +| Bluetooth | on-chip | Bluetooth | ++-----------+------------+-----------------------+ + + +The default configurations can be found in +:zephyr_file:`boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble_defconfig` + +System Clock +============ + +The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for +the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the +system clock are provided in the SOC, depending on your system requirements. + + +OpenOCD Installation +==================== + +To get the OpenOCD package, it is required that you + +1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox +2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox + export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts +3. Add the OpenOCD executable file's path to west flash/debug. +4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd +5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd + + +Fetch Binary Blobs +****************** + +cy8cproto_063_ble board requires fetch binary files +(e.g Bluetooth controller firmware, CM0p prebuilt images, etc). + +To fetch Binary Blobs: + +.. code-block:: console + + west blobs fetch hal_infineon + +Programming and Debugging +************************* + +The CY8CPROTO-063-BLE includes an onboard programmer/debugger (KitProg3) with +mass storage programming to provide debugging, flash programming, and serial +communication over USB. Flash and debug commands must be pointed to the Cypress +OpenOCD you downloaded above. + +On Windows: + +.. code-block:: console + + west flash --openocd path/to/infineon/openocd/bin/openocd.exe + west debug --openocd path/to/infineon/openocd/bin/openocd.exe + +On Linux: + +.. code-block:: console + + west flash --openocd path/to/infineon/openocd/bin/openocd + west debug --openocd path/to/infineon/openocd/bin/openocd + +References +********** + +.. _PSoC 63 BLE MCU SoC Website: + https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 + +.. _PSoC 63 BLE MCU Datasheet: + https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_PSoC_63_with_BLE_Datasheet_Programmable_System-on-Chip_(PSoC)-DataSheet-v16_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee4efe46c37&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files + +.. _PSoC 63 BLE MCU Architecture Reference Manual: + https://documentation.infineon.com/html/psoc6/zrs1651212645947.html + +.. _PSoC 63 BLE MCU Register Reference Manual: + https://documentation.infineon.com/html/psoc6/bnm1651211483724.html + +.. _CY8CPROTO-063-BLE Website: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/ + +.. _CY8CPROTO-063-BLE User Guide: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/#!?fileId=8ac78c8c7d0d8da4017d0f00d7eb1812 + +.. _CY8CPROTO-063-BLE Schematics: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/#!?fileId=8ac78c8c7d0d8da4017d0f00ea3c1821 + +.. _Infineon OpenOCD: + https://github.com/infineon/openocd/releases/tag/release-v4.3.0 diff --git a/boards/arm/cy8cproto_063_ble/support/openocd.cfg b/boards/cypress/cy8cproto_063_ble/support/openocd.cfg similarity index 100% rename from boards/arm/cy8cproto_063_ble/support/openocd.cfg rename to boards/cypress/cy8cproto_063_ble/support/openocd.cfg diff --git a/boards/cypress/index.rst b/boards/cypress/index.rst new file mode 100644 index 00000000000..571b8c69b68 --- /dev/null +++ b/boards/cypress/index.rst @@ -0,0 +1,10 @@ +.. _boards-cypress: + +Cypress +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/digilent/arty_a7/CMakeLists.txt b/boards/digilent/arty_a7/CMakeLists.txt new file mode 100644 index 00000000000..5b036b02a73 --- /dev/null +++ b/boards/digilent/arty_a7/CMakeLists.txt @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) + +if((CONFIG_BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1) AND (CONFIG_BUILD_OUTPUT_BIN)) + # Generate zephyr.mem verilog memory hex dump file for initialising ITCM in + # Xilinx Vivado. + # + # This ought to be done using the objcopy verilog bfd, but it contains a bug + # affecting endianness: https://sourceware.org/bugzilla/show_bug.cgi?id=25202 + # + # Instead we use bin2hex from the SiFive elf2hex package, if available. + # https://github.com/sifive/elf2hex + find_program(BIN2HEX ${CROSS_COMPILE_TARGET}-bin2hex) + + if(NOT ${BIN2HEX} STREQUAL BIN2HEX-NOTFOUND) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${BIN2HEX} + ARGS --bit-width 32 + ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin + ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.mem + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} + ) + message(STATUS "Verilog memory hex dump will be written to: ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.mem") + else() + message(STATUS "The bin2hex (${CROSS_COMPILE_TARGET}-bin2hex) utility was not found, verilog memory hex dump file cannot be generated") + endif() +endif() diff --git a/boards/digilent/arty_a7/Kconfig b/boards/digilent/arty_a7/Kconfig new file mode 100644 index 00000000000..19be35749f8 --- /dev/null +++ b/boards/digilent/arty_a7/Kconfig @@ -0,0 +1,13 @@ +# Digilent Arty board configuration + +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INIT_PRIORITY + int "Board initialization priority" + default 50 + depends on BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1 || BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3 + depends on "$(dt_nodelabel_enabled,daplink_qspi_mux)" + help + Board initialization priority. The board initialization must take + place after the GPIO driver is initialized. diff --git a/boards/digilent/arty_a7/Kconfig.arty_a7 b/boards/digilent/arty_a7/Kconfig.arty_a7 new file mode 100644 index 00000000000..6e5ac7bb179 --- /dev/null +++ b/boards/digilent/arty_a7/Kconfig.arty_a7 @@ -0,0 +1,8 @@ +# Digilent Arty board configuration + +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARTY_A7 + select SOC_DESIGNSTART_FPGA_CORTEX_M1 if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1 + select SOC_DESIGNSTART_FPGA_CORTEX_M3 if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/boards/digilent/arty_a7/Kconfig.defconfig b/boards/digilent/arty_a7/Kconfig.defconfig new file mode 100644 index 00000000000..ecd93d6954a --- /dev/null +++ b/boards/digilent/arty_a7/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Digilent Arty board configuration + +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1 || BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3 + +config CPU_CORTEX_M_HAS_SYSTICK + default y + +config CPU_HAS_ARM_MPU + default y if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3 + +config NUM_IRQS + default 7 + +config GPIO + default y if "$(dt_nodelabel_enabled,daplink_qspi_mux)" + +endif # BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1 || BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/boards/arm/arty/arty_a7_arm_designstart_m1.dts b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.dts similarity index 100% rename from boards/arm/arty/arty_a7_arm_designstart_m1.dts rename to boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.dts diff --git a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml new file mode 100644 index 00000000000..565ddbffdb8 --- /dev/null +++ b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml @@ -0,0 +1,14 @@ +identifier: arty_a7/designstart_fpga_cortex_m1 +name: Digilent Arty A7 ARM DesignStart Cortex-M1 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32 +flash: 64 +supported: + - flash + - spi + - gpio diff --git a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1_defconfig b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1_defconfig new file mode 100644 index 00000000000..ce3f3066fa0 --- /dev/null +++ b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 + +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arty/arty_a7_arm_designstart_m3.dts b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.dts similarity index 100% rename from boards/arm/arty/arty_a7_arm_designstart_m3.dts rename to boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.dts diff --git a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml new file mode 100644 index 00000000000..416365ff291 --- /dev/null +++ b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml @@ -0,0 +1,14 @@ +identifier: arty_a7/designstart_fpga_cortex_m3 +name: Digilent Arty A7 ARM DesignStart Cortex-M3 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32 +flash: 32 +supported: + - flash + - spi + - gpio diff --git a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3_defconfig b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3_defconfig new file mode 100644 index 00000000000..7952bdf9f20 --- /dev/null +++ b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=50000000 +CONFIG_ARM_MPU=y + +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arty/board.c b/boards/digilent/arty_a7/board.c similarity index 100% rename from boards/arm/arty/board.c rename to boards/digilent/arty_a7/board.c diff --git a/boards/digilent/arty_a7/board.cmake b/boards/digilent/arty_a7/board.cmake new file mode 100644 index 00000000000..0596bf31add --- /dev/null +++ b/boards/digilent/arty_a7/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1) + board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m1.cfg") + board_runner_args(jlink "--device=Cortex-M1" "--reset-after-load") +elseif(CONFIG_BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3) + board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m3.cfg") + board_runner_args(jlink "--device=Cortex-M3" "--reset-after-load") +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/arty/board.h b/boards/digilent/arty_a7/board.h similarity index 100% rename from boards/arm/arty/board.h rename to boards/digilent/arty_a7/board.h diff --git a/boards/digilent/arty_a7/board.yml b/boards/digilent/arty_a7/board.yml new file mode 100644 index 00000000000..14a2c9ef418 --- /dev/null +++ b/boards/digilent/arty_a7/board.yml @@ -0,0 +1,6 @@ +board: + name: arty_a7 + vendor: digilent + socs: + - name: designstart_fpga_cortex_m1 + - name: designstart_fpga_cortex_m3 diff --git a/boards/arm/arty/doc/arty_a7-35.jpg b/boards/digilent/arty_a7/doc/arty_a7-35.jpg similarity index 100% rename from boards/arm/arty/doc/arty_a7-35.jpg rename to boards/digilent/arty_a7/doc/arty_a7-35.jpg diff --git a/boards/digilent/arty_a7/doc/index.rst b/boards/digilent/arty_a7/doc/index.rst new file mode 100644 index 00000000000..4284320d6de --- /dev/null +++ b/boards/digilent/arty_a7/doc/index.rst @@ -0,0 +1,228 @@ +.. _arty: + +Digilent Arty +############# + +Overview +******** + +The `Digilent Arty`_ is a line of FPGA-based development boards aimed for makers +and hobbyists. The Arty is available in several configurations, each with a +different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series). + +Each board is equipped with on-board JTAG for FPGA programming and debugging, +LEDs, switches, buttons, DDR3 RAM, and QSPI flash for storing the FPGA +bitstream. + +.. figure:: arty_a7-35.jpg + :align: center + :alt: Digilent Arty A7-35 + + Digilent Arty A7-35 (Credit: Digilent Inc) + +The Spartan-7 and Artix-7 based Arty board do not contain a CPU, but require a +so-called soft processor to be instantiated within the FPGA in order to run +Zephyr. The Zynq-7000 based Arty boards are not yet supported by Zephyr. + +ARM Cortex-M1/M3 DesignStart FPGA +********************************* + +One way of instantiating soft processors on the Arty is using the `ARM +DesignStart FPGA`_ Xilinx edition reference designs from ARM. Zephyr supports +both the Cortex-M1 and the Cortex-M3 reference designs. The Cortex-M1 design +targets either the Spartan-7 or Artix-7 based Arty boards, whereas the Cortex-M3 +design only targets the Artix-7 based boards. Zephyr only supports the Artix-7 +targeted designs for now. + +For more information about the ARM Cortex-M1/M3 DesignStart FPGA, see the +following websites: + +- `Technical Resources for DesignStart FPGA`_ +- `Technical Resources for DesignStart FPGA on Xilinx`_ +- `ARM DesignStart FPGA Xilinx FAQs`_ + +Supported Features +================== + +The ``arty_a7/designstart_fpga_cortex_m1`` board configuration supports the following +hardware features of the Cortex-M1 reference design: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio, non-interrupt | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| QSPI | on-chip | QSPI flash | ++-----------+------------+-------------------------------------+ + +The default configuration for the Cortex-M1 can be found in the defconfig file: +:file:`boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1_defconfig`. + +In addition to the above, the ``arty_a7/designstart_fpga_cortex_m3`` board configuration +supports the following hardware features of the Cortex-M3 reference design: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | Memory Protection Unit | ++-----------+------------+-------------------------------------+ + +The default configuration for the Cortex-M3 can be found in the defconfig file: +:file:`boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3_defconfig`. + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The Cortex-M1 reference design is configured to use the 100 MHz external +oscillator on the board as CPU system clock whereas the Cortex-M3 reference +design is configured for 50MHz CPU system clock. + +Serial Port +=========== + +The reference design contains one Xilinx UART Lite. This UART is configured as +console and is accessible through the on-board JTAG adapter via USB connector +``J10``. + +Connecting the Debug Probes +=========================== + +Two different debug probes are needed in order to program the board; the +on-board Digilent JTAG connected to the FPGA, and an external Serial Wire Debug +(SWD) capable debug probe connected to the ARM Cortex-M1 CPU. + +The on-board JTAG is used for configuring and debugging the Xilinx FPGA +itself. It is available on USB connector ``J10``. + +The external SWD debug probe can be connected to connector ``J4`` (``nSRST`` on +``IO39``, ``SWDIO`` on ``IO40``, and ``SWCLK`` on ``IO41``). Another option is +to use the dedicated :ref:`v2c_daplink_shield`. + +Programming and Debugging +************************* + +First, configure the FPGA with the selected reference design FPGA bitstream +using Xilinx Vivado as described in the ARM Cortex-M1/Cortex-M3 DesignStart FPGA +Xilinx edition user guide (available as part of the reference design download +from `Technical Resources for DesignStart FPGA on Xilinx`_). + +Another option for configuring the FPGA with the reference design bitstream is +to use the :ref:`openocd-debug-host-tools`: + +.. code-block:: console + + openocd -f board/arty_s7.cfg -c "init;\ + pld load 0 m1_for_arty_a7_reference.bit;\ + shutdown" + +or: + +.. code-block:: console + + openocd -f board/arty_s7.cfg -c "init;\ + pld load 0 m3_for_arty_a7_reference.bit;\ + shutdown" + +.. note:: + + The pre-built FPGA bitstream only works for Arty boards equipped with an + Artix-35T FPGA. For other Arty variants (e.g. the Arty A7-100) the bitstream + must be rebuilt. + +Next, build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Console +===================== + +The UART console is available via the on-board JTAG on USB connector +``J10``. The on-board JTAG will enumerate as two USB serial ports. The UART is +typically available on the second serial port. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for building and flashing the :ref:`hello_world` application +for the Cortex-M1 reference design: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arty_a7/designstart_fpga_cortex_m1 + :goals: flash + +After flashing, you should see message similar to the following in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.3.99 *** + Hello World! arty_a7 + +The same procedure can be used for the Cortex-M3 reference design. + +Note, however, that the application was not persisted in flash memory by the +above steps. It was merely written to internal block RAM in the FPGA. It will +revert to the application stored in the block RAM within the FPGA bitstream +the next time the FPGA is configured. + +The steps to persist the application within the FPGA bitstream are covered by +the ARM Cortex-M1/M3 DesignStart FPGA Xilinx edition user guide. If the +:kconfig:option:`CONFIG_BUILD_OUTPUT_BIN` is enabled and the `SiFive elf2hex`_ package +is available, the build system will automatically generate a Verilog memory hex +dump :file:`zephyr.mem` file suitable for initialising the block RAM using +`Xilinx Vivado`_. + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arty_a7/designstart_fpga_cortex_m1 + :goals: debug + +Step through the application in your debugger, and you should see a message +similar to the following in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.3.99 *** + Hello World! arty_a7 + +.. _Digilent Arty: + https://store.digilentinc.com/arty + +.. _ARM DesignStart FPGA: + https://www.arm.com/resources/designstart/designstart-fpga + +.. _Technical Resources for DesignStart FPGA: + https://developer.arm.com/ip-products/designstart/fpga + +.. _Technical Resources for DesignStart FPGA on Xilinx: + https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx + +.. _ARM DesignStart FPGA Xilinx FAQs: + https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx-faqs + +.. _SiFive elf2hex: + https://github.com/sifive/elf2hex + +.. _Xilinx Vivado: + https://www.xilinx.com/products/design-tools/vivado.html diff --git a/boards/arm/arty/dts/arty_a7_arm_designstart.dtsi b/boards/digilent/arty_a7/dts/arty_a7_arm_designstart.dtsi similarity index 100% rename from boards/arm/arty/dts/arty_a7_arm_designstart.dtsi rename to boards/digilent/arty_a7/dts/arty_a7_arm_designstart.dtsi diff --git a/boards/arm/arty/dts/bindings/arm,daplink-qspi-mux.yaml b/boards/digilent/arty_a7/dts/bindings/arm,daplink-qspi-mux.yaml similarity index 100% rename from boards/arm/arty/dts/bindings/arm,daplink-qspi-mux.yaml rename to boards/digilent/arty_a7/dts/bindings/arm,daplink-qspi-mux.yaml diff --git a/boards/arm/arty/support/openocd_arty_a7_arm_designstart.cfg b/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart.cfg similarity index 100% rename from boards/arm/arty/support/openocd_arty_a7_arm_designstart.cfg rename to boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart.cfg diff --git a/boards/arm/arty/support/openocd_arty_a7_arm_designstart_m1.cfg b/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m1.cfg similarity index 100% rename from boards/arm/arty/support/openocd_arty_a7_arm_designstart_m1.cfg rename to boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m1.cfg diff --git a/boards/arm/arty/support/openocd_arty_a7_arm_designstart_m3.cfg b/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m3.cfg similarity index 100% rename from boards/arm/arty/support/openocd_arty_a7_arm_designstart_m3.cfg rename to boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m3.cfg diff --git a/boards/digilent/index.rst b/boards/digilent/index.rst new file mode 100644 index 00000000000..811282e59ae --- /dev/null +++ b/boards/digilent/index.rst @@ -0,0 +1,10 @@ +.. _boards-digilent: + +Digilent, Inc. +############## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/digilent/zybo/Kconfig.zybo b/boards/digilent/zybo/Kconfig.zybo new file mode 100644 index 00000000000..fc1662ed6be --- /dev/null +++ b/boards/digilent/zybo/Kconfig.zybo @@ -0,0 +1,7 @@ +# Digilent Zybo board configuration + +# Copyright (c) 2022 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ZYBO + select SOC_XILINX_XC7Z010 diff --git a/boards/arm/zybo/board.cmake b/boards/digilent/zybo/board.cmake similarity index 100% rename from boards/arm/zybo/board.cmake rename to boards/digilent/zybo/board.cmake diff --git a/boards/digilent/zybo/board.yml b/boards/digilent/zybo/board.yml new file mode 100644 index 00000000000..f9c9c98bea2 --- /dev/null +++ b/boards/digilent/zybo/board.yml @@ -0,0 +1,5 @@ +board: + name: zybo + vendor: digilent + socs: + - name: xc7z010 diff --git a/boards/digilent/zybo/doc/index.rst b/boards/digilent/zybo/doc/index.rst new file mode 100644 index 00000000000..f8e3857227d --- /dev/null +++ b/boards/digilent/zybo/doc/index.rst @@ -0,0 +1,147 @@ +.. _zybo: + +Digilent Zybo +############# + +Overview +******** + +The `Digilent Zybo`_ (ZYnq BOard) is a feature-rich, ready-to-use embedded software and digital +circuit development board. It is built around the Xilinx Zynq-7000 family, which is based on the +Xilinx All Programmable System-on-Chip (AP SoC) architecture. This architecture tightly integrates a +dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. + +.. figure:: zybo-0.jpg + :align: center + :alt: Digilent Zybo + + Digilent (Credit: Digilent) + +Hardware +******** + +Supported Features +================== + +The zybo board configuration supports the following hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| GICv1 | on-chip | ARM generic interrupt controller v1 | ++------------+------------+-------------------------------------+ +| ARCH TIMER | on-chip | ARM architected timer | ++------------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++------------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/digilent/zybo/zybo_defconfig` + +Other hardware features are not currently supported by the port. + +Programming and Debugging +************************* + +The Zynq-7000 series SoC needs to be initialized prior to running a Zephyr application. This can be +achieved in a number of ways (e.g. using the Xilinx First Stage Boot Loader (FSBL), the Xilinx +Vivado generated ``ps_init.tcl`` JTAG script, Das U-Boot Secondary Program Loader (SPL), ...). + +The instructions here use the U-Boot SPL. For further details and instructions for using Das U-Boot +with Xilinx Zynq-7000 series SoCs, see the following documentation: + +- `Das U-Boot Website`_ +- `Using Distro Boot With Xilinx U-Boot`_ + +Building Das U-Boot +=================== + +Clone and build Das U-Boot for the Digilent Zybo: + +.. code-block:: console + + git clone -b v2022.04 https://source.denx.de/u-boot/u-boot.git + cd u-boot + make distclean + make xilinx_zynq_virt_defconfig + export PATH=/path/to/zephyr-sdk/arm-zephyr-eabi/bin/:$PATH + export CROSS_COMPILE=arm-zephyr-eabi- + export DEVICE_TREE="zynq-zybo" + make + +Flashing +======== + +Here is an example for running the :ref:`hello_world` application via JTAG. + +Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press +the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot +SPL via JTAG. + +Next, upload and run the Zephyr application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: zybo + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx *** + Hello World! zybo + +Another option is to load and run the :ref:`hello_world` application via U-Boot. Copy +``u-boot/spl/boot.bin``, ``u-boot/u-boot.img``, and ``zephyr/zephyr.bin`` to a FAT32 formatted +microSD card, insert the card in the ``SD MICRO`` slot on the Zybo board, ensure the board is +configured for ``SD`` boot, and turn on the board. + +Once U-boot is done initializing, load an run the Zephyr application: + +.. code-block:: console + + Zynq> fatload mmc 0 0x0 zephyr.bin + 817120 bytes read in 56 ms (13.9 MiB/s) + Zynq> go 0x0 + ## Starting application at 0x00000000 ... + *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx *** + Hello World! zybo + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press +the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot +SPL via JTAG. + +Next, upload and debug the Zephyr application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: zybo + :goals: debug + +Step through the application in your debugger, and you should see the following message in the +terminal: + +.. code-block:: console + + *** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *** + Hello World! zybo + +.. _Digilent Zybo: + https://digilent.com/reference/programmable-logic/zybo/start + +.. _Das U-Boot Website: + https://www.denx.de/wiki/U-Boot + +.. _Using Distro Boot With Xilinx U-Boot: + https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/749142017/Using+Distro+Boot+With+Xilinx+U-Boot diff --git a/boards/arm/zybo/doc/zybo-0.jpg b/boards/digilent/zybo/doc/zybo-0.jpg similarity index 100% rename from boards/arm/zybo/doc/zybo-0.jpg rename to boards/digilent/zybo/doc/zybo-0.jpg diff --git a/boards/arm/zybo/support/openocd.cfg b/boards/digilent/zybo/support/openocd.cfg similarity index 100% rename from boards/arm/zybo/support/openocd.cfg rename to boards/digilent/zybo/support/openocd.cfg diff --git a/boards/arm/zybo/zybo-pinctrl.dtsi b/boards/digilent/zybo/zybo-pinctrl.dtsi similarity index 100% rename from boards/arm/zybo/zybo-pinctrl.dtsi rename to boards/digilent/zybo/zybo-pinctrl.dtsi diff --git a/boards/arm/zybo/zybo.dts b/boards/digilent/zybo/zybo.dts similarity index 100% rename from boards/arm/zybo/zybo.dts rename to boards/digilent/zybo/zybo.dts diff --git a/boards/arm/zybo/zybo.yaml b/boards/digilent/zybo/zybo.yaml similarity index 100% rename from boards/arm/zybo/zybo.yaml rename to boards/digilent/zybo/zybo.yaml diff --git a/boards/digilent/zybo/zybo_defconfig b/boards/digilent/zybo/zybo_defconfig new file mode 100644 index 00000000000..bf2bc2777e6 --- /dev/null +++ b/boards/digilent/zybo/zybo_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) +CONFIG_ARM_ARCH_TIMER=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=325000000 + +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/dragino/index.rst b/boards/dragino/index.rst new file mode 100644 index 00000000000..c9141395af8 --- /dev/null +++ b/boards/dragino/index.rst @@ -0,0 +1,10 @@ +.. _boards-dragino: + +Dragino +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/dragino/lsn50/Kconfig.dragino_lsn50 b/boards/dragino/lsn50/Kconfig.dragino_lsn50 new file mode 100644 index 00000000000..c8dd04dbd9e --- /dev/null +++ b/boards/dragino/lsn50/Kconfig.dragino_lsn50 @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Endre Karlson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DRAGINO_LSN50 + select SOC_STM32L072XX diff --git a/boards/arm/b_l072z_lrwan1/board.cmake b/boards/dragino/lsn50/board.cmake similarity index 100% rename from boards/arm/b_l072z_lrwan1/board.cmake rename to boards/dragino/lsn50/board.cmake diff --git a/boards/dragino/lsn50/board.yml b/boards/dragino/lsn50/board.yml new file mode 100644 index 00000000000..e7c09a9c7bd --- /dev/null +++ b/boards/dragino/lsn50/board.yml @@ -0,0 +1,5 @@ +board: + name: dragino_lsn50 + vendor: dragino + socs: + - name: stm32l072xx diff --git a/boards/arm/dragino_lsn50/doc/img/dragino_lsn50.jpg b/boards/dragino/lsn50/doc/img/dragino_lsn50.jpg similarity index 100% rename from boards/arm/dragino_lsn50/doc/img/dragino_lsn50.jpg rename to boards/dragino/lsn50/doc/img/dragino_lsn50.jpg diff --git a/boards/dragino/lsn50/doc/index.rst b/boards/dragino/lsn50/doc/index.rst new file mode 100644 index 00000000000..b3d14f92885 --- /dev/null +++ b/boards/dragino/lsn50/doc/index.rst @@ -0,0 +1,193 @@ +.. _dragino_lsn50_board: + +Dragino LSN50 LoRA Sensor Node +############################## + +Overview +******** + +The Dragino LSN50 LoRA Sensor Node for IoT allows users to develop +applications with LoraWAN connectivity via the HopeRF / SX1276/SX1278. +Dragino LSN50 enables a wide diversity of applications by exploiting +low-power communication, ARM |reg| Cortex |reg|-M0 core-based +STM32L0 Series features. + +This kit provides: + +- STM32L072CZ MCU +- SX1276/SX1278 LoRa Transceiver +- Expansion connectors: + + - PMOD +- Li/SOCI2 Unchargable Battery +- GPIOs exposed via screw terminals on the carrier board +- Housing + +.. image:: img/dragino_lsn50.jpg + :align: center + :alt: Dragino LSN50 + +More information about the board can be found at the `Dragino LSN50 website`_. + +Hardware +******** + +The STM32L072CZ SoC provides the following hardware IPs: + +- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz +- Clock Sources: + + - 1 to 32 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 37 kHz RC ( |plusminus| 5%) + - Internal multispeed low-power 65 kHz to 4.2 MHz RC +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 11x timers: + + - 2x 16-bit with up to 4 channels + - 2x 16-bit with up to 2 channels + - 1x 16-bit ultra-low-power timer + - 1x SysTick + - 1x RTC + - 2x 16-bit basic for DAC + - 2x watchdogs (independent/window) +- Up to 84 fast I/Os, most 5 V-tolerant. +- Memories + + - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 20 KB of SRAM + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 1.14 MSPS + - 2x 12-bit DAC + - 2x ultra-low-power comparators +- 11x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 6x SPIs (4x SPIs with the Quad SPI) +- 7-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L072CZ can be found here: + + - `STM32L072CZ on www.st.com`_ + - `STM32L0x2 reference manual`_ + +Supported Features +================== + +The Zephyr Dragino LSN50 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/dragino/lsn50/dragino_lsn50_defconfig` + + +Connections and IOs +=================== + +Dragino LSN50 Board has GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- + +For detailed information about available pins please refer to `Dragino LSN50 website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 + +System Clock +------------ + +Dragino LSN50 System Clock is at 32MHz, + +Serial Port +----------- + +Dragino LSN50 board has 2 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``dragino_lsn50`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Dragino LSN50 board requires an external debugger. + +Flashing an application to Dragino LSN50 +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Connect the Dragino LSN50 to a STLinkV2 to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dragino_lsn50 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dragino_lsn50 + :maybe-skip-config: + :goals: debug + +.. _Dragino LSN50 website: + https://www.dragino.com/products/lora-lorawan-end-node/item/128-lsn50.html + +.. _STM32L072CZ on www.st.com: + https://www.st.com/en/microcontrollers/stm32l072cz.html + +.. _STM32L0x2 reference manual: + https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/dragino_lsn50/dragino_lsn50.dts b/boards/dragino/lsn50/dragino_lsn50.dts similarity index 100% rename from boards/arm/dragino_lsn50/dragino_lsn50.dts rename to boards/dragino/lsn50/dragino_lsn50.dts diff --git a/boards/arm/dragino_lsn50/dragino_lsn50.yaml b/boards/dragino/lsn50/dragino_lsn50.yaml similarity index 100% rename from boards/arm/dragino_lsn50/dragino_lsn50.yaml rename to boards/dragino/lsn50/dragino_lsn50.yaml diff --git a/boards/dragino/lsn50/dragino_lsn50_defconfig b/boards/dragino/lsn50/dragino_lsn50_defconfig new file mode 100644 index 00000000000..06e8a32bb1f --- /dev/null +++ b/boards/dragino/lsn50/dragino_lsn50_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/dragino_lsn50/support/openocd.cfg b/boards/dragino/lsn50/support/openocd.cfg similarity index 100% rename from boards/arm/dragino_lsn50/support/openocd.cfg rename to boards/dragino/lsn50/support/openocd.cfg diff --git a/boards/dragino/nbsn95/Kconfig.dragino_nbsn95 b/boards/dragino/nbsn95/Kconfig.dragino_nbsn95 new file mode 100644 index 00000000000..21a6867793e --- /dev/null +++ b/boards/dragino/nbsn95/Kconfig.dragino_nbsn95 @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Next Big Thing AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DRAGINO_NBSN95 + select SOC_STM32L072XX diff --git a/boards/arm/dragino_lsn50/board.cmake b/boards/dragino/nbsn95/board.cmake similarity index 100% rename from boards/arm/dragino_lsn50/board.cmake rename to boards/dragino/nbsn95/board.cmake diff --git a/boards/dragino/nbsn95/board.yml b/boards/dragino/nbsn95/board.yml new file mode 100644 index 00000000000..66d568935ec --- /dev/null +++ b/boards/dragino/nbsn95/board.yml @@ -0,0 +1,5 @@ +board: + name: dragino_nbsn95 + vendor: dragino + socs: + - name: stm32l072xx diff --git a/boards/arm/dragino_nbsn95/doc/img/dragino_nbsn95.jpg b/boards/dragino/nbsn95/doc/img/dragino_nbsn95.jpg similarity index 100% rename from boards/arm/dragino_nbsn95/doc/img/dragino_nbsn95.jpg rename to boards/dragino/nbsn95/doc/img/dragino_nbsn95.jpg diff --git a/boards/dragino/nbsn95/doc/index.rst b/boards/dragino/nbsn95/doc/index.rst new file mode 100644 index 00000000000..09a8b91f6ce --- /dev/null +++ b/boards/dragino/nbsn95/doc/index.rst @@ -0,0 +1,192 @@ +.. _dragino_nbsn95_board: + +Dragino NBSN95 NB-IoT Sensor Node +################################# + +Overview +******** + +The Dragino NBSN95 NB-IoT Sensor Node for IoT allows users to develop +applications with NB-IoT connectivity via the Quectel BC95-G. +Dragino NBSN95 enables a wide diversity of applications by exploiting +low-power communication, ARM |reg| Cortex |reg|-M0 core-based +STM32L0 Series features. + +This kit provides: + +- STM32L072CZ MCU +- Quectel BC95-G NB-IoT +- Expansion connectors: + - PMOD +- Li/SOCI2 Unchargable Battery +- GPIOs exposed via screw terminals on the carrier board +- Housing + +.. image:: img/dragino_nbsn95.jpg + :align: center + :alt: Dragino NBSN95 + +More information about the board can be found at the `Dragino NBSN95 website`_. + +Hardware +******** + +The STM32L072CZ SoC provides the following hardware IPs: + +- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz +- Clock Sources: + + - 1 to 32 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 37 kHz RC ( |plusminus| 5%) + - Internal multispeed low-power 65 kHz to 4.2 MHz RC +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 11x timers: + + - 2x 16-bit with up to 4 channels + - 2x 16-bit with up to 2 channels + - 1x 16-bit ultra-low-power timer + - 1x SysTick + - 1x RTC + - 2x 16-bit basic for DAC + - 2x watchdogs (independent/window) +- Up to 84 fast I/Os, most 5 V-tolerant. +- Memories + + - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 20 KB of SRAM + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 1.14 MSPS + - 2x 12-bit DAC + - 2x ultra-low-power comparators +- 11x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 6x SPIs (4x SPIs with the Quad SPI) +- 7-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L072CZ can be found here: + + - `STM32L072CZ on www.st.com`_ + - `STM32L0x2 reference manual`_ + +Supported Features +================== + +The Zephyr Dragino NBSN95 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/dragino/nbsn95/dragino_nbsn95_defconfig` + + +Connections and IOs +=================== + +Dragino NBSN95 Board has GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- + +For detailed information about available pins please refer to `Dragino NBSN95 website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 + +System Clock +------------ + +Dragino NBSN95 System Clock is at 32MHz, + +Serial Port +----------- + +Dragino NBSN95 board has 2 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``dragino_nbsn95`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Dragino NBSN95 board requires an external debugger. + +Flashing an application to Dragino NBSN95 +----------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Connect the Dragino NBSN95 to a STLinkV2 to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dragino_nbsn95 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! dragino_nbsn95 + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dragino_nbsn95 + :maybe-skip-config: + :goals: debug + +.. _Dragino NBSN95 website: + https://www.dragino.com/products/nb-iot/item/163-nbsn95.html + +.. _STM32L072CZ on www.st.com: + https://www.st.com/en/microcontrollers/stm32l072cz.html + +.. _STM32L0x2 reference manual: + https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/dragino_nbsn95/dragino_nbsn95.dts b/boards/dragino/nbsn95/dragino_nbsn95.dts similarity index 100% rename from boards/arm/dragino_nbsn95/dragino_nbsn95.dts rename to boards/dragino/nbsn95/dragino_nbsn95.dts diff --git a/boards/arm/dragino_nbsn95/dragino_nbsn95.yaml b/boards/dragino/nbsn95/dragino_nbsn95.yaml similarity index 100% rename from boards/arm/dragino_nbsn95/dragino_nbsn95.yaml rename to boards/dragino/nbsn95/dragino_nbsn95.yaml diff --git a/boards/dragino/nbsn95/dragino_nbsn95_defconfig b/boards/dragino/nbsn95/dragino_nbsn95_defconfig new file mode 100644 index 00000000000..1a570d28d13 --- /dev/null +++ b/boards/dragino/nbsn95/dragino_nbsn95_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/dragino_nbsn95/support/openocd.cfg b/boards/dragino/nbsn95/support/openocd.cfg similarity index 100% rename from boards/arm/dragino_nbsn95/support/openocd.cfg rename to boards/dragino/nbsn95/support/openocd.cfg diff --git a/boards/ebyte/e73_tbb/Kconfig.defconfig b/boards/ebyte/e73_tbb/Kconfig.defconfig new file mode 100644 index 00000000000..d3434e975a2 --- /dev/null +++ b/boards/ebyte/e73_tbb/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EBYTE E73-TBB NRF52832 board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# Copyright (c) 2021 Michal Morsisko +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EBYTE_E73_TBB_NRF52832 + +config BT_CTLR + default BT + +endif # BOARD_EBYTE_E73_TBB_NRF52832 diff --git a/boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb b/boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb new file mode 100644 index 00000000000..8a04ffd502d --- /dev/null +++ b/boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb @@ -0,0 +1,7 @@ +# EBYTE-TBB board configuration + +# Copyright (c) 2021 Michal Morsisko +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EBYTE_E73_TBB_NRF52832 + select SOC_NRF52832_QFAA diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/board.cmake b/boards/ebyte/e73_tbb/board.cmake similarity index 100% rename from boards/arm/ebyte_e73_tbb_nrf52832/board.cmake rename to boards/ebyte/e73_tbb/board.cmake diff --git a/boards/ebyte/e73_tbb/board.yml b/boards/ebyte/e73_tbb/board.yml new file mode 100644 index 00000000000..3ae94fab665 --- /dev/null +++ b/boards/ebyte/e73_tbb/board.yml @@ -0,0 +1,5 @@ +board: + name: ebyte_e73_tbb + vendor: ebyte + socs: + - name: nrf52832 diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/doc/img/ebyte_e73_tbb_nrf52832.jpg b/boards/ebyte/e73_tbb/doc/img/ebyte_e73_tbb_nrf52832.jpg similarity index 100% rename from boards/arm/ebyte_e73_tbb_nrf52832/doc/img/ebyte_e73_tbb_nrf52832.jpg rename to boards/ebyte/e73_tbb/doc/img/ebyte_e73_tbb_nrf52832.jpg diff --git a/boards/ebyte/e73_tbb/doc/index.rst b/boards/ebyte/e73_tbb/doc/index.rst new file mode 100644 index 00000000000..f05a3454b6e --- /dev/null +++ b/boards/ebyte/e73_tbb/doc/index.rst @@ -0,0 +1,222 @@ +.. _ebyte_e73_tbb_nrf52832: + +EBYTE E73-TBB +############# + +Overview +******** + +The EBYTE E73-TBB hardware provides +support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/ebyte_e73_tbb_nrf52832.jpg + :align: center + :alt: EBYTE E73-TBB + + EBYTE E73-TBB (Credit: EBYTE) + +More information about the board can be found at the +`E73-TBB website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +E73-TBB has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. Additionally the board features CH340 USB-UART converter. +It is possible to connect external BT antenna using U.FL socket +and solder NFC antenna using NFC_ANT connector. + +Supported Features +================== + +The ebyte_e73_tbb/nrf52832 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features are not supported by the Zephyr kernel. +See `E73-TBB website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF52832 hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.17 +* LED1 (red) = P0.18 + +Push buttons +------------ + +* BUTTON0 = SW1 = P0.14 +* BUTTON1 = SW2 = P0.13 + +External Connectors +------------------- + +P1 Header + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | GND | ++-------+--------------+ +| 2 | 3.3V | ++-------+--------------+ +| 3 | P0.04 | ++-------+--------------+ +| 4 | P0.03 | ++-------+--------------+ +| 5 | P0.02 | ++-------+--------------+ +| 6 | P0.31 | ++-------+--------------+ +| 7 | P0.30 | ++-------+--------------+ +| 8 | P0.29 | ++-------+--------------+ +| 9 | P0.28 | ++-------+--------------+ +| 10 | P0.27 | ++-------+--------------+ +| 11 | P0.26 | ++-------+--------------+ +| 12 | P0.25 | ++-------+--------------+ + +P2 Header + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | P0.24 | ++-------+--------------+ +| 2 | P0.23 | ++-------+--------------+ +| 3 | P0.22 | ++-------+--------------+ +| 4 | SWDIO | ++-------+--------------+ +| 5 | SWDCLK | ++-------+--------------+ +| 6 | P0.21/RST | ++-------+--------------+ +| 7 | P0.20 | ++-------+--------------+ +| 8 | P0.19 | ++-------+--------------+ +| 9 | P0.16 | ++-------+--------------+ +| 10 | P0.15 | ++-------+--------------+ +| 11 | P0.12 | ++-------+--------------+ +| 12 | P0.11 | ++-------+--------------+ + +NFC_ANT + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | P0.10 | ++-------+--------------+ +| 2 | P0.09 | ++-------+--------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. +To flash the board connect pins: SWDIO, SWDCLK, RST, GND from E73-TBB +to corresponding pins on your J-Link device, then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ebyte_e73_tbb/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic chips with a +Segger IC. + + +Testing the LEDs and buttons in the E73-TBB +******************************************* + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + :zephyr:code-sample:`blinky` + :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts`. + +References +********** + +.. target-notes:: + +.. _E73-TBB website: https://www.ebyte.com/en/product-view-news.html?id=889 +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832-pinctrl.dtsi b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832-pinctrl.dtsi rename to boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832-pinctrl.dtsi diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.dts b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts similarity index 100% rename from boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.dts rename to boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.yaml b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.yaml similarity index 85% rename from boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.yaml rename to boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.yaml index ba39fdbfc46..9311e76cff1 100644 --- a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.yaml +++ b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: ebyte_e73_tbb_nrf52832 +identifier: ebyte_e73_tbb/nrf52832 name: EBYTE-E73-TBB-NRF52832 type: mcu arch: arm diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832_defconfig b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832_defconfig similarity index 76% rename from boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832_defconfig rename to boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832_defconfig index 8b9a09a8e8d..0ee25845f2e 100644 --- a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832_defconfig +++ b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_EBYTE_E73_TBB_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/ebyte/index.rst b/boards/ebyte/index.rst new file mode 100644 index 00000000000..b1a2b8ae327 --- /dev/null +++ b/boards/ebyte/index.rst @@ -0,0 +1,10 @@ +.. _boards-ebyte: + +Chengdu Ebyte Electronic Technology +################################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/efinix/index.rst b/boards/efinix/index.rst new file mode 100644 index 00000000000..901246a75a4 --- /dev/null +++ b/boards/efinix/index.rst @@ -0,0 +1,10 @@ +.. _boards-efinix: + +Efinix, Inc. +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/efinix/titanium_ti60_f225/Kconfig.titanium_ti60_f225 b/boards/efinix/titanium_ti60_f225/Kconfig.titanium_ti60_f225 new file mode 100644 index 00000000000..3b3f710bc79 --- /dev/null +++ b/boards/efinix/titanium_ti60_f225/Kconfig.titanium_ti60_f225 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TITANIUM_TI60_F225 + select SOC_EFINIX_SAPPHIRE diff --git a/boards/efinix/titanium_ti60_f225/board.yml b/boards/efinix/titanium_ti60_f225/board.yml new file mode 100644 index 00000000000..7daa700f0b3 --- /dev/null +++ b/boards/efinix/titanium_ti60_f225/board.yml @@ -0,0 +1,5 @@ +board: + name: titanium_ti60_f225 + vendor: efinix + socs: + - name: efinix_sapphire diff --git a/boards/riscv/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg b/boards/efinix/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg similarity index 100% rename from boards/riscv/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg rename to boards/efinix/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg diff --git a/boards/riscv/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg b/boards/efinix/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg similarity index 100% rename from boards/riscv/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg rename to boards/efinix/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg diff --git a/boards/riscv/titanium_ti60_f225/doc/index.rst b/boards/efinix/titanium_ti60_f225/doc/index.rst similarity index 100% rename from boards/riscv/titanium_ti60_f225/doc/index.rst rename to boards/efinix/titanium_ti60_f225/doc/index.rst diff --git a/boards/riscv/titanium_ti60_f225/titanium_ti60_f225.dts b/boards/efinix/titanium_ti60_f225/titanium_ti60_f225.dts similarity index 100% rename from boards/riscv/titanium_ti60_f225/titanium_ti60_f225.dts rename to boards/efinix/titanium_ti60_f225/titanium_ti60_f225.dts diff --git a/boards/riscv/titanium_ti60_f225/titanium_ti60_f225.yaml b/boards/efinix/titanium_ti60_f225/titanium_ti60_f225.yaml similarity index 100% rename from boards/riscv/titanium_ti60_f225/titanium_ti60_f225.yaml rename to boards/efinix/titanium_ti60_f225/titanium_ti60_f225.yaml diff --git a/boards/riscv/titanium_ti60_f225/titanium_ti60_f225_defconfig b/boards/efinix/titanium_ti60_f225/titanium_ti60_f225_defconfig similarity index 78% rename from boards/riscv/titanium_ti60_f225/titanium_ti60_f225_defconfig rename to boards/efinix/titanium_ti60_f225/titanium_ti60_f225_defconfig index 0608a8e8953..e540d6c5bac 100644 --- a/boards/riscv/titanium_ti60_f225/titanium_ti60_f225_defconfig +++ b/boards/efinix/titanium_ti60_f225/titanium_ti60_f225_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2023 Efinix Inc. # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_EFINIX_SAPPHIRE=y -CONFIG_BOARD_TITANIUM_TI60_F225=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/electronut_labs/index.rst b/boards/electronut_labs/index.rst new file mode 100644 index 00000000000..065a52cc96c --- /dev/null +++ b/boards/electronut_labs/index.rst @@ -0,0 +1,10 @@ +.. _boards-electronut-labs: + +Electronut Labs +############### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/nrf52840_blip/Kconfig b/boards/electronut_labs/nrf52840_blip/Kconfig similarity index 100% rename from boards/arm/nrf52840_blip/Kconfig rename to boards/electronut_labs/nrf52840_blip/Kconfig diff --git a/boards/electronut_labs/nrf52840_blip/Kconfig.defconfig b/boards/electronut_labs/nrf52840_blip/Kconfig.defconfig new file mode 100644 index 00000000000..91ff6042e0c --- /dev/null +++ b/boards/electronut_labs/nrf52840_blip/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Electronut Labs Blip board configuration + +# Copyright (c) 2018 Electronut Labs +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840_BLIP + +config BT_CTLR + default BT + +endif # BOARD_NRF52840_BLIP diff --git a/boards/electronut_labs/nrf52840_blip/Kconfig.nrf52840_blip b/boards/electronut_labs/nrf52840_blip/Kconfig.nrf52840_blip new file mode 100644 index 00000000000..b28eaadba83 --- /dev/null +++ b/boards/electronut_labs/nrf52840_blip/Kconfig.nrf52840_blip @@ -0,0 +1,7 @@ +# Electronut Labs Blip board configuration + +# Copyright (c) 2018 Electronut Labs +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840_BLIP + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_blip/board.cmake b/boards/electronut_labs/nrf52840_blip/board.cmake similarity index 100% rename from boards/arm/nrf52840_blip/board.cmake rename to boards/electronut_labs/nrf52840_blip/board.cmake diff --git a/boards/electronut_labs/nrf52840_blip/board.yml b/boards/electronut_labs/nrf52840_blip/board.yml new file mode 100644 index 00000000000..3964f015c2f --- /dev/null +++ b/boards/electronut_labs/nrf52840_blip/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52840_blip + vendor: electronut + socs: + - name: nrf52840 diff --git a/boards/arm/nrf52840_blip/doc/img/nrf52840_blip.jpg b/boards/electronut_labs/nrf52840_blip/doc/img/nrf52840_blip.jpg similarity index 100% rename from boards/arm/nrf52840_blip/doc/img/nrf52840_blip.jpg rename to boards/electronut_labs/nrf52840_blip/doc/img/nrf52840_blip.jpg diff --git a/boards/electronut_labs/nrf52840_blip/doc/index.rst b/boards/electronut_labs/nrf52840_blip/doc/index.rst new file mode 100644 index 00000000000..768168da60e --- /dev/null +++ b/boards/electronut_labs/nrf52840_blip/doc/index.rst @@ -0,0 +1,196 @@ +.. _nrf52840_blip: + +Electronut Labs Blip +#################### + +Overview +******** + +The Electronut Labs Blip hardware provides support for the Nordic Semiconductor +nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf52840_blip.jpg + :align: center + :alt: Electronut Labs Blip + + Electronut Labs Blip (Credit: Electronut Labs) + +More information about the board is available at https://github.com/electronut/ElectronutLabs-blip. + +Hardware +******** + +Blip has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The nrf52840_blip board configuration supports the following +hardware features currently: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (red) = P0.14 +* LED3 (blue) = P0.15 + +Push buttons +------------ + +* BUTTON1 = SW1 = P1.07 +* Reset = SW5 = P0.18 (can be used as GPIO also) + +UART +---- + +BMP does not support hardware flow control, so only RX/TX pins are connected. + +* TX = P0.6 +* RX = P0.8 + +I2C +--- + +I2C pins connected to onboard sensors: + +* SDA = P0.12 +* SCL = P0.11 + +SPI +--- + +* SCK = P0.25 +* MOSI = P1.02 +* MISO = P0.24 + +MicroSD is connected to these pins, and CS pin is connected to P0.17. + +Programming and Debugging +************************* + +Applications for the ``nrf52840_blip`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); The onboard Black Magic +Probe debugger presents itself as two USB-serial ports. On Linux, +they may come up as ``/dev/ttyACM0`` and ``/dev/ttyACM1``. The first +one of these (``/dev/ttyACM0`` here) is the debugger port. +GDB can directly connect to this port without requiring a GDB server by specifying +``target external /dev/ttyACM0``. The second port acts as a +serial port, connected to the SoC. + +Flashing +======== + +Applications are flashed and run as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the serial port of Black Magic Probe. +For example, under Linux, :code:`/dev/ttyACM1`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52840_blip + :goals: build flash + +Debugging +========= + +Debug and attach configurations are available using Black Magic Probe, and +``ninja debug``, or ``ninja attach`` (or with ``make``) are available. + +NOTE: You may need to press the reset button once after using ``ninja flash`` +to start executing the code. (not required with ``debug`` or ``attach``) + + +Testing the LEDs and buttons in the nRF52840 PDK +************************************************ + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/electronut_labs/nrf52840_blip/nrf52840_blip.dts`. + + +References +********** + +.. target-notes:: + +.. _Electronut Labs website: https://electronut.in +.. _Store link: https://www.tindie.com/stores/ElectronutLabs/ +.. _Blip website: https://github.com/electronut/ElectronutLabs-blip +.. _Schematic: https://github.com/electronut/ElectronutLabs-blip/blob/master/blip_v0.3_schematic.pdf +.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ +.. _Black Magic Probe website: https://github.com/blacksphere/blackmagic diff --git a/boards/arm/nrf52840_blip/nrf52840_blip-pinctrl.dtsi b/boards/electronut_labs/nrf52840_blip/nrf52840_blip-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840_blip/nrf52840_blip-pinctrl.dtsi rename to boards/electronut_labs/nrf52840_blip/nrf52840_blip-pinctrl.dtsi diff --git a/boards/arm/nrf52840_blip/nrf52840_blip.dts b/boards/electronut_labs/nrf52840_blip/nrf52840_blip.dts similarity index 100% rename from boards/arm/nrf52840_blip/nrf52840_blip.dts rename to boards/electronut_labs/nrf52840_blip/nrf52840_blip.dts diff --git a/boards/arm/nrf52840_blip/nrf52840_blip.yaml b/boards/electronut_labs/nrf52840_blip/nrf52840_blip.yaml similarity index 100% rename from boards/arm/nrf52840_blip/nrf52840_blip.yaml rename to boards/electronut_labs/nrf52840_blip/nrf52840_blip.yaml diff --git a/boards/electronut_labs/nrf52840_blip/nrf52840_blip_defconfig b/boards/electronut_labs/nrf52840_blip/nrf52840_blip_defconfig new file mode 100644 index 00000000000..7167aca850a --- /dev/null +++ b/boards/electronut_labs/nrf52840_blip/nrf52840_blip_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bl654_usb/pre_dt_board.cmake b/boards/electronut_labs/nrf52840_blip/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl654_usb/pre_dt_board.cmake rename to boards/electronut_labs/nrf52840_blip/pre_dt_board.cmake diff --git a/boards/arm/nrf52840_papyr/Kconfig b/boards/electronut_labs/nrf52840_papyr/Kconfig similarity index 100% rename from boards/arm/nrf52840_papyr/Kconfig rename to boards/electronut_labs/nrf52840_papyr/Kconfig diff --git a/boards/electronut_labs/nrf52840_papyr/Kconfig.defconfig b/boards/electronut_labs/nrf52840_papyr/Kconfig.defconfig new file mode 100644 index 00000000000..94d55d43358 --- /dev/null +++ b/boards/electronut_labs/nrf52840_papyr/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Electronut Labs Papyr board configuration + +# Copyright (c) 2018 Electronut Labs +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840_PAPYR + +config BT_CTLR + default BT + +endif # BOARD_NRF52840_PAPYR diff --git a/boards/electronut_labs/nrf52840_papyr/Kconfig.nrf52840_papyr b/boards/electronut_labs/nrf52840_papyr/Kconfig.nrf52840_papyr new file mode 100644 index 00000000000..f0825d7825f --- /dev/null +++ b/boards/electronut_labs/nrf52840_papyr/Kconfig.nrf52840_papyr @@ -0,0 +1,7 @@ +# Electronut Labs Papyr board configuration + +# Copyright (c) 2018 Electronut Labs +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840_PAPYR + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_papyr/board.cmake b/boards/electronut_labs/nrf52840_papyr/board.cmake similarity index 100% rename from boards/arm/nrf52840_papyr/board.cmake rename to boards/electronut_labs/nrf52840_papyr/board.cmake diff --git a/boards/electronut_labs/nrf52840_papyr/board.yml b/boards/electronut_labs/nrf52840_papyr/board.yml new file mode 100644 index 00000000000..fcb089ad625 --- /dev/null +++ b/boards/electronut_labs/nrf52840_papyr/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52840_papyr + vendor: electronut + socs: + - name: nrf52840 diff --git a/boards/arm/nrf52840_papyr/doc/img/nrf52840_papyr.jpg b/boards/electronut_labs/nrf52840_papyr/doc/img/nrf52840_papyr.jpg similarity index 100% rename from boards/arm/nrf52840_papyr/doc/img/nrf52840_papyr.jpg rename to boards/electronut_labs/nrf52840_papyr/doc/img/nrf52840_papyr.jpg diff --git a/boards/arm/nrf52840_papyr/doc/nrf52840_papyr.rst b/boards/electronut_labs/nrf52840_papyr/doc/nrf52840_papyr.rst similarity index 100% rename from boards/arm/nrf52840_papyr/doc/nrf52840_papyr.rst rename to boards/electronut_labs/nrf52840_papyr/doc/nrf52840_papyr.rst diff --git a/boards/arm/nrf52840_papyr/nrf52840_papyr-pinctrl.dtsi b/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840_papyr/nrf52840_papyr-pinctrl.dtsi rename to boards/electronut_labs/nrf52840_papyr/nrf52840_papyr-pinctrl.dtsi diff --git a/boards/arm/nrf52840_papyr/nrf52840_papyr.dts b/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr.dts similarity index 100% rename from boards/arm/nrf52840_papyr/nrf52840_papyr.dts rename to boards/electronut_labs/nrf52840_papyr/nrf52840_papyr.dts diff --git a/boards/arm/nrf52840_papyr/nrf52840_papyr.yaml b/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr.yaml similarity index 100% rename from boards/arm/nrf52840_papyr/nrf52840_papyr.yaml rename to boards/electronut_labs/nrf52840_papyr/nrf52840_papyr.yaml diff --git a/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr_defconfig b/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr_defconfig new file mode 100644 index 00000000000..7167aca850a --- /dev/null +++ b/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/pre_dt_board.cmake b/boards/electronut_labs/nrf52840_papyr/pre_dt_board.cmake similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/pre_dt_board.cmake rename to boards/electronut_labs/nrf52840_papyr/pre_dt_board.cmake diff --git a/boards/element14/index.rst b/boards/element14/index.rst new file mode 100644 index 00000000000..fbd25a3c5a8 --- /dev/null +++ b/boards/element14/index.rst @@ -0,0 +1,10 @@ +.. _boards-element-14: + +Element 14 +########## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/element14/warp7/Kconfig.defconfig b/boards/element14/warp7/Kconfig.defconfig new file mode 100644 index 00000000000..b73424093e0 --- /dev/null +++ b/boards/element14/warp7/Kconfig.defconfig @@ -0,0 +1,23 @@ +# WaRP7 iMX7S M4 board + +# Copyright (c) 2018, Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_WARP7 + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +config FXAS21002_DRDY_INT1 + default y + depends on FXAS21002_TRIGGER + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_WARP7 diff --git a/boards/element14/warp7/Kconfig.warp7 b/boards/element14/warp7/Kconfig.warp7 new file mode 100644 index 00000000000..438b4807d07 --- /dev/null +++ b/boards/element14/warp7/Kconfig.warp7 @@ -0,0 +1,7 @@ +# Copyright (c) 2018, Diego Sueiro +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WARP7 + select SOC_PART_NUMBER_MCIMX7S3DVK08SA + select SOC_MCIMX7D_M4 if BOARD_WARP7_MCIMX7D_M4 diff --git a/boards/element14/warp7/board.yml b/boards/element14/warp7/board.yml new file mode 100644 index 00000000000..99b037ded48 --- /dev/null +++ b/boards/element14/warp7/board.yml @@ -0,0 +1,5 @@ +board: + name: warp7 + vendor: element14 + socs: + - name: mcimx7d diff --git a/boards/element14/warp7/doc/index.rst b/boards/element14/warp7/doc/index.rst new file mode 100644 index 00000000000..e55de8a80e3 --- /dev/null +++ b/boards/element14/warp7/doc/index.rst @@ -0,0 +1,345 @@ +.. _warp7: + +WaRP7 - Next Generation IoT and Wearable Development Platform +############################################################# + +Overview +******** + +The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7 +core and Single Cortex M4 core. +Zephyr was ported to run on the M4 core. In a later release, it will also +communicate with the A7 core (running Linux) via RPmsg. + + +.. image:: warp7.jpg + :align: center + :alt: WaRP7-iMX7S + +Hardware +******** + +The WaRP7 Platform is composed of a CPU and IO board. + +WaRP7 IO Board +============== + +- 6-axis Accelerometer Magnetometer: NXP FXOS8700CQ (I2C4 interface) +- 3-axis Gyroscope: NXP FXAS21002C (I2C4 interface) +- Altimeter: NXP MPL3115A2 (I2C4 interface) +- NXP NTAG NT3H1101 (I2C2 interface) +- Audio Codec: NXP SGTL5000 (I2C4 and SAI1 interfaces) +- S1 - Reset Button (POR_B signal) +- S2 - User Defined button (ENET1_RD1/GPIO7_IO1 signal) +- S3 - On/Off (MX7_ONOFF signal) +- Board to board connector (34 configurable pins) +- mikroBUS expansion connector +- 10-pin needle JTAG Connector +- Debug USB exposing two UARTs (UART1 for A7 and UART2 for M4) +- MIPI DSI 1 lane Connector +- LCD Touch Connector (I2C2 interface) +- Audio Jack: Mic and Stereo Headphone + +WaRP7 CPU Board +=============== + +- CPU i.MX7 Solo with a Single Cortex A7 (800MHz) core and + Single Cortex M4 (200MHz) core +- Memory + + - RAM -> A7: 4GB (Kingston 08EMCP04) + - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) + - Flash -> A7: 8GB eMMC (Kingston 08EMCP04) +- Multimedia + + - MIPI CSI 1 lane connector with 5MP OV5640 camera module (I2C2 interface) +- Connectivity + + - Board to board connector (34 configurable pins) + - Micro USB 2.0 OTG connector (USB_OTG1 interface) + - Murata Type 1DX Wi-Fi IEEE 802.11b/g/n and Bluetooth 4.1 plus EDR + (SD1, UART3 SAI2 interfaces) +- Li-ion/Li-polymer Battery Charger: NXP BC3770 (I2C1 interface) +- Power management integrated circuit (PMIC): NXP PF3000 (I2C1 interface) + + +For more information about the i.MX7 SoC and WaRP7, see these references: + +- `i.MX 7 Series Website`_ +- `i.MX 7 Solo Datasheet`_ +- `i.MX 7 Solo Reference Manual`_ +- `WaRP7 Site`_ +- `WaRP7 Quick Start Guide`_ +- `WaRP7 User Guide`_ +- `WaRP7 GitHub repository`_ + +Supported Features +================== + +The WaRP7 configuration supports the following hardware features on the +Cortex M4 Core: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger; | +| | | fxas21002 polling; | +| | | fxas21002 trigger; | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/element14/warp7/warp7_mcimx7d_m4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The WaRP7 board Board was tested with the following pinmux controller +configuration. + ++---------------+---------------------+--------------------------------+ +| Board Name | SoC Name | Usage | ++===============+=====================+================================+ +| FT_TX2 | UART2_TXD | UART Console | ++---------------+---------------------+--------------------------------+ +| FT_RX2 | UART2_RXD | UART Console | ++---------------+---------------------+--------------------------------+ +| MKBUS_TX | UART6_TXD | UART | ++---------------+---------------------+--------------------------------+ +| MKBUS_RX | UART6_RXD | UART | ++---------------+---------------------+--------------------------------+ +| S2 | ENET1_RD1/GPIO7_IO1 | SW0 | ++---------------+---------------------+--------------------------------+ +| I2C4_SDA | I2C4_SDA | I2C / FXOS8700 / FXAS21002 | ++---------------+---------------------+--------------------------------+ +| I2C4_SCL | I2C4_SCL | I2C / FXOS8700 / FXAS21002 | ++---------------+---------------------+--------------------------------+ +| SENSOR_INT_B | ENET1_RD0/GPIO7_IO0 | FXOS8700 INT1 / FXAS21002 INT1 | ++---------------+---------------------+--------------------------------+ + +System Clock +============ + +The M4 Core is configured to run at a 200 MHz clock speed. + +Serial Port +=========== + +The iMX7S SoC has seven UARTs. The number 2 is configured for the console and +the number 6 is used in the mikroBUS connector. + +Programming and Debugging +************************* + +The WaRP7 doesn't have QSPI flash for the M4 and it needs to be started by +the A7 core. The A7 core is responsible to load the M4 binary application into +the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and +get the M4 out of reset. +The A7 can perform these steps at bootloader level or after the Linux system +has booted. + +The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and +M4: + ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=======================+========================+=======================+======================+ +| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ + + +References +========== + +- `i.MX 7 Solo Reference Manual`_ from page 182 (section 2.1.2 and 2.1.3) +- `Toradex Wiki`_ + + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file :zephyr_file:`boards/element14/warp7/warp7_mcimx7d_m4.dts` with +"zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. The available +configurations are: + +.. code-block:: none + + "zephyr,flash" + - &ddr_code + - &tcml_code + - &ocram_code + - &ocram_s_code + - &ocram_pxp_code + - &ocram_epdc_code + + "zephyr,sram" + - &ddr_sys + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + - &ocram_pxp_sys + - &ocram_epdc_sys + + +Below you will find the instructions to load and run Zephyr on M4 from A7 using +u-boot. + +Connect both micro USB interfaces into the PC. In one USB interface you will +have 2 USB serial ports, the first one is the A7 console and the second is the +M4 console for Zephyr with both configured to work at 115200 8N1. +The other USB interface is used to power the CPU and IO boards and is connected +to the USB OTG interface of the i.MX7S. + +After powering up the platform stop the u-boot execution on the A7 core and +expose the eMMC as mass storage with the following command in the u-boot +prompt: ``ums 0 mmc 0``. Copy the compiled zephyr.bin to the first FAT +partition and remove the mounted device on the PC by issuing a "Ctrl+C" in the +u-boot prompt. +Set the u-boot environment variables and run the zephyr.bin from the +appropriated memory configured in the Zephyr compilation: + +.. code-block:: console + + setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' + # TCML + setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' + setenv bootm4tcml 'run m4tcml && run bootm4' + run bootm4tcml + # TCMU + setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' + setenv bootm4tcmu 'run m4tcmu && run bootm4' + run bootm4tcmu + # OCRAM + setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' + setenv bootm4ocram 'run m4ocram && run bootm4' + run bootm4ocram + # OCRAM_S + setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' + setenv bootm4ocrams 'run m4ocrams && run bootm4' + run bootm4ocrams + # DDR + setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' + setenv bootm4ddr 'run m4ddr && run bootm4' + run bootm4ddr + + +Debugging +========= + +Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. + +To run Zephyr Binary using J-Link, create the following script to get the +Program Counter and Stack Pointer from ``zephyr.bin``. + +get-pc-sp.sh: +.. code-block:: console + + #!/bin/sh + + firmware=$1 + + pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') + sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') + + echo pc=$pc + echo sp=$sp + + +Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` +.. code-block:: console + + pc=00900f01 + sp=00905020 + +Plug in the J-Link into the board and PC and run the J-Link command line tool: + +.. code-block:: console + + /usr/bin/JLinkExe -device Cortex-M4 -if JTAG \ + -speed 4000 -autoconnect 1 -jtagconf -1,-1 \ + -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript + +The following steps are necessary to run the zephyr.bin: + +1. Put the M4 core in reset +2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) +3. Set PC (Program Counter) +4. Set SP (Stack Pointer) +5. Get the M4 core out of reset + +Issue the following commands inside J-Link commander: + +.. code-block:: console + + w4 0x3039000C 0xAC + loadfile zephyr.bin,0x00900000 + w4 0x00180000 00900f01 + w4 0x00180004 00905020 + w4 0x3039000C 0xAA + +With these mechanisms, applications for the ``warp7`` board +configuration can be built and debugged in the usual way (see +:ref:`build_an_application` and :ref:`application_run` for more details). + +References +========== + +- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ +- `J-Link iMX7D Instructions`_ + +.. _WaRP7 Site: + https://www.element14.com/warp7 + +.. _WaRP7 User Guide: + https://github.com/WaRP7/WaRP7-User-Guide/releases/download/v1.3/User_Guide_Manual_v1-3.pdf + +.. _WaRP7 Quick Start Guide: + https://www.nxp.com/docs/en/supporting-information/WARP7-LEAFLET-QSG.pdf + +.. _WaRP7 GitHub repository: + https://github.com/WaRP7 + +.. _i.MX 7 Series Website: + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 + +.. _i.MX 7 Solo Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMX7SCEC.pdf + +.. _i.MX 7 Solo Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX7SRM + +.. _J-Link Tools: + https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack + +.. _NXP iMX7D Connect CortexM4.JLinkScript: + https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript + +.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: + https://www.nxp.com/docs/en/application-note/AN5317.pdf + +.. _J-Link iMX7D Instructions: + https://wiki.segger.com/IMX7D + +.. _Toradex Wiki: + https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/warp7_m4/doc/warp7_m4.jpg b/boards/element14/warp7/doc/warp7.jpg similarity index 100% rename from boards/arm/warp7_m4/doc/warp7_m4.jpg rename to boards/element14/warp7/doc/warp7.jpg diff --git a/boards/arm/warp7_m4/warp7_m4-pinctrl.dtsi b/boards/element14/warp7/warp7-pinctrl.dtsi similarity index 100% rename from boards/arm/warp7_m4/warp7_m4-pinctrl.dtsi rename to boards/element14/warp7/warp7-pinctrl.dtsi diff --git a/boards/element14/warp7/warp7_mcimx7d_m4.dts b/boards/element14/warp7/warp7_mcimx7d_m4.dts new file mode 100644 index 00000000000..5947f86898a --- /dev/null +++ b/boards/element14/warp7/warp7_mcimx7d_m4.dts @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2018, Diego Sueiro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "warp7-pinctrl.dtsi" +#include + +/ { + model = "WaRP7 IMX7S board"; + compatible = "nxp,mcimx7d_m4"; + + aliases { + sw0 = &user_switch_1; + magn0 = &fxos8700; + accel0 = &fxos8700; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_switch_1: user_sw_1 { + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + label = "User SW1"; + zephyr,code = ; + }; + }; +}; + +&uart2 { + status = "okay"; + current-speed = <115200>; + modem-mode = <0>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&uart6 { + status = "okay"; + current-speed = <115200>; + modem-mode = <0>; + pinctrl-0 = <&uart6_default>; + pinctrl-names = "default"; +}; + +&gpio7 { + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4_default>; + pinctrl-names = "default"; + + fxos8700: fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + int1-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + }; + + fxas21002@20 { + compatible = "nxp,fxas21002"; + reg = <0x20>; + int1-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + }; + +}; + +&mub { + status = "okay"; +}; diff --git a/boards/element14/warp7/warp7_mcimx7d_m4.yaml b/boards/element14/warp7/warp7_mcimx7d_m4.yaml new file mode 100644 index 00000000000..96a7e7fbca8 --- /dev/null +++ b/boards/element14/warp7/warp7_mcimx7d_m4.yaml @@ -0,0 +1,24 @@ +# +# Copyright (c) 2018, Diego Sueiro +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: warp7/mcimx7d/m4 +name: WaRP7 IMX7S +type: mcu +arch: arm +ram: 32 +flash: 32 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - gpio + - i2c +vendor: nxp diff --git a/boards/element14/warp7/warp7_mcimx7d_m4_defconfig b/boards/element14/warp7/warp7_mcimx7d_m4_defconfig new file mode 100644 index 00000000000..b62210da43e --- /dev/null +++ b/boards/element14/warp7/warp7_mcimx7d_m4_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2018, Diego Sueiro +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_PINCTRL=y diff --git a/boards/enclustra/mercury_xu/CMakeLists.txt b/boards/enclustra/mercury_xu/CMakeLists.txt new file mode 100644 index 00000000000..f1877356e3b --- /dev/null +++ b/boards/enclustra/mercury_xu/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2020, Antmicro +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/enclustra/mercury_xu/Kconfig.defconfig b/boards/enclustra/mercury_xu/Kconfig.defconfig new file mode 100644 index 00000000000..3a6d5d2a524 --- /dev/null +++ b/boards/enclustra/mercury_xu/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2020, Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MERCURY_XU + +config FLASH_SIZE + int + default 64 + +config FLASH_BASE_ADDRESS + default 0x08000000 + +endif diff --git a/boards/enclustra/mercury_xu/Kconfig.mercury_xu b/boards/enclustra/mercury_xu/Kconfig.mercury_xu new file mode 100644 index 00000000000..0cc9368f54f --- /dev/null +++ b/boards/enclustra/mercury_xu/Kconfig.mercury_xu @@ -0,0 +1,5 @@ +# Copyright (c) 2020, Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MERCURY_XU + select SOC_XILINX_ZYNQMP_RPU diff --git a/boards/arm/mercury_xu/board.c b/boards/enclustra/mercury_xu/board.c similarity index 100% rename from boards/arm/mercury_xu/board.c rename to boards/enclustra/mercury_xu/board.c diff --git a/boards/enclustra/mercury_xu/board.yml b/boards/enclustra/mercury_xu/board.yml new file mode 100644 index 00000000000..739a5c95857 --- /dev/null +++ b/boards/enclustra/mercury_xu/board.yml @@ -0,0 +1,5 @@ +board: + name: mercury_xu + vendor: enclustra + socs: + - name: zynqmp_rpu diff --git a/boards/arm/mercury_xu/mercury_xu-pinctrl.dtsi b/boards/enclustra/mercury_xu/mercury_xu-pinctrl.dtsi similarity index 100% rename from boards/arm/mercury_xu/mercury_xu-pinctrl.dtsi rename to boards/enclustra/mercury_xu/mercury_xu-pinctrl.dtsi diff --git a/boards/arm/mercury_xu/mercury_xu.dts b/boards/enclustra/mercury_xu/mercury_xu.dts similarity index 100% rename from boards/arm/mercury_xu/mercury_xu.dts rename to boards/enclustra/mercury_xu/mercury_xu.dts diff --git a/boards/arm/mercury_xu/mercury_xu.yaml b/boards/enclustra/mercury_xu/mercury_xu.yaml similarity index 100% rename from boards/arm/mercury_xu/mercury_xu.yaml rename to boards/enclustra/mercury_xu/mercury_xu.yaml diff --git a/boards/enclustra/mercury_xu/mercury_xu_defconfig b/boards/enclustra/mercury_xu/mercury_xu_defconfig new file mode 100644 index 00000000000..10ed71b13c9 --- /dev/null +++ b/boards/enclustra/mercury_xu/mercury_xu_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2020, Antmicro + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable timer +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 + +CONFIG_PINCTRL=y diff --git a/boards/enjoy_digital/index.rst b/boards/enjoy_digital/index.rst new file mode 100644 index 00000000000..aedf86d9ecd --- /dev/null +++ b/boards/enjoy_digital/index.rst @@ -0,0 +1,10 @@ +.. _boards-enjoydigital: + +EnjoyDigital +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/enjoy_digital/litex_vexriscv/Kconfig.defconfig b/boards/enjoy_digital/litex_vexriscv/Kconfig.defconfig new file mode 100644 index 00000000000..f48e777e7a7 --- /dev/null +++ b/boards/enjoy_digital/litex_vexriscv/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2018 - 2019 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LITEX_VEXRISCV + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_LITEX_VEXRISCV diff --git a/boards/enjoy_digital/litex_vexriscv/Kconfig.litex_vexriscv b/boards/enjoy_digital/litex_vexriscv/Kconfig.litex_vexriscv new file mode 100644 index 00000000000..ae3a15d3685 --- /dev/null +++ b/boards/enjoy_digital/litex_vexriscv/Kconfig.litex_vexriscv @@ -0,0 +1,5 @@ +# Copyright (c) 2018 - 2019 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LITEX_VEXRISCV + select SOC_LITEX_VEXRISCV diff --git a/boards/enjoy_digital/litex_vexriscv/board.yml b/boards/enjoy_digital/litex_vexriscv/board.yml new file mode 100644 index 00000000000..18ea360bb83 --- /dev/null +++ b/boards/enjoy_digital/litex_vexriscv/board.yml @@ -0,0 +1,5 @@ +board: + name: litex_vexriscv + vendor: litex + socs: + - name: litex_vexriscv diff --git a/boards/riscv/litex_vexriscv/doc/img/litex_vexriscv.jpg b/boards/enjoy_digital/litex_vexriscv/doc/img/litex_vexriscv.jpg similarity index 100% rename from boards/riscv/litex_vexriscv/doc/img/litex_vexriscv.jpg rename to boards/enjoy_digital/litex_vexriscv/doc/img/litex_vexriscv.jpg diff --git a/boards/riscv/litex_vexriscv/doc/img/symbiflow.svg b/boards/enjoy_digital/litex_vexriscv/doc/img/symbiflow.svg similarity index 100% rename from boards/riscv/litex_vexriscv/doc/img/symbiflow.svg rename to boards/enjoy_digital/litex_vexriscv/doc/img/symbiflow.svg diff --git a/boards/riscv/litex_vexriscv/doc/index.rst b/boards/enjoy_digital/litex_vexriscv/doc/index.rst similarity index 100% rename from boards/riscv/litex_vexriscv/doc/index.rst rename to boards/enjoy_digital/litex_vexriscv/doc/index.rst diff --git a/boards/riscv/litex_vexriscv/litex_vexriscv.dts b/boards/enjoy_digital/litex_vexriscv/litex_vexriscv.dts similarity index 100% rename from boards/riscv/litex_vexriscv/litex_vexriscv.dts rename to boards/enjoy_digital/litex_vexriscv/litex_vexriscv.dts diff --git a/boards/riscv/litex_vexriscv/litex_vexriscv.yaml b/boards/enjoy_digital/litex_vexriscv/litex_vexriscv.yaml similarity index 100% rename from boards/riscv/litex_vexriscv/litex_vexriscv.yaml rename to boards/enjoy_digital/litex_vexriscv/litex_vexriscv.yaml diff --git a/boards/riscv/litex_vexriscv/litex_vexriscv_defconfig b/boards/enjoy_digital/litex_vexriscv/litex_vexriscv_defconfig similarity index 77% rename from boards/riscv/litex_vexriscv/litex_vexriscv_defconfig rename to boards/enjoy_digital/litex_vexriscv/litex_vexriscv_defconfig index b8730d07d06..d51a5923ff8 100644 --- a/boards/riscv/litex_vexriscv/litex_vexriscv_defconfig +++ b/boards/enjoy_digital/litex_vexriscv/litex_vexriscv_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_RISCV32_LITEX_VEXRISCV=y -CONFIG_BOARD_LITEX_VEXRISCV=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig b/boards/espressif/esp32_devkitc_wroom/Kconfig new file mode 100644 index 00000000000..7bb2bb0d629 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_DEVKITC_WROOM + select SOC_ESP32_PROCPU if BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig b/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig new file mode 100644 index 00000000000..6da35bf9735 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig @@ -0,0 +1,26 @@ +# ESP32 board configuration + +# Copyright (c) 2017 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU + +if BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 4096 + +endif # BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom b/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom new file mode 100644 index 00000000000..44cd4bcd7dd --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_DEVKITC_WROOM + select SOC_ESP32_WROOM_32UE_N4 diff --git a/boards/riscv/esp32c3_devkitm/Kconfig.sysbuild b/boards/espressif/esp32_devkitc_wroom/Kconfig.sysbuild similarity index 100% rename from boards/riscv/esp32c3_devkitm/Kconfig.sysbuild rename to boards/espressif/esp32_devkitc_wroom/Kconfig.sysbuild diff --git a/boards/xtensa/esp32_devkitc_wroom/board.cmake b/boards/espressif/esp32_devkitc_wroom/board.cmake similarity index 100% rename from boards/xtensa/esp32_devkitc_wroom/board.cmake rename to boards/espressif/esp32_devkitc_wroom/board.cmake diff --git a/boards/espressif/esp32_devkitc_wroom/board.yml b/boards/espressif/esp32_devkitc_wroom/board.yml new file mode 100644 index 00000000000..42d9d88dc23 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32_devkitc_wroom + vendor: espressif + socs: + - name: esp32 diff --git a/boards/xtensa/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg b/boards/espressif/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg similarity index 100% rename from boards/xtensa/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg rename to boards/espressif/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg diff --git a/boards/espressif/esp32_devkitc_wroom/doc/index.rst b/boards/espressif/esp32_devkitc_wroom/doc/index.rst new file mode 100644 index 00000000000..7b0d7d8964c --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/doc/index.rst @@ -0,0 +1,215 @@ +.. _esp32_devkitc_wroom: + +ESP32-DEVKITC-WROOM +################### + +Overview +******** + +ESP32-DEVKITC-WROOM is a series of low cost, low power system on a chip microcontrollers +with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a +Tensilica Xtensa LX6 microprocessor in both dual-core and single-core +variations. ESP32-WROOM is created and developed by Espressif Systems, a +Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm +process. [1]_ + +The features include the following: + +- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz +- 520KB of SRAM +- 802.11b/g/n/e/i +- Bluetooth v4.2 BR/EDR and BLE +- Various peripherals: + + - 12-bit ADC with up to 18 channels + - 2x 8-bit DACs + - 10x touch sensors + - Temperature sensor + - 4x SPI + - 2x I2S + - 2x I2C + - 3x UART + - SD/SDIO/MMC host + - Slave (SDIO/SPI) + - Ethernet MAC + - CAN bus 2.0 + - IR (RX/TX) + - Motor PWM + - LED PWM with up to 16 channels + - Hall effect sensor + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) +- 5uA deep sleep current + +.. figure:: img/esp32_devkitc_wroom.jpg + :align: center + :alt: ESP32-DEVKITC-WROOM + + ESP32-DevKitC-WROOM-32D DK + +Asymmetric Multiprocessing (AMP) +******************************** + +ESP32-DEVKITC-WROOM allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode +and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. + +Supported Features +================== + +Current Zephyr's ESP32-WROOM board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wroom/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32_devkitc_wroom`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wroom/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32_devkitc_wroom + +Debugging +--------- + +ESP32-DEVKITC-WROOM support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +On the ESP-WROOM-32 DevKitC board, the JTAG pins are not run to a +standard connector (e.g. ARM 20-pin) and need to be manually connected +to the external programmer (e.g. a Flyswatter2): + ++------------+-----------+ +| ESP32 pin | JTAG pin | ++============+===========+ +| 3V3 | VTRef | ++------------+-----------+ +| EN | nTRST | ++------------+-----------+ +| IO14 | TMS | ++------------+-----------+ +| IO12 | TDI | ++------------+-----------+ +| GND | GND | ++------------+-----------+ +| IO13 | TCK | ++------------+-----------+ +| IO15 | TDO | ++------------+-----------+ + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wroom/esp32/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wroom/esp32/procpu + :goals: debug + +Note on Debugging with GDB Stub +=============================== + +GDB stub is enabled on ESP32. + +* When adding breakpoints, please use hardware breakpoints with command + ``hbreak``. Command ``break`` uses software breakpoints which requires + modifying memory content to insert break/trap instructions. + This does not work as the code is on flash which cannot be randomly + accessed for modification. + +.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html +.. _`OpenOCD`: https://github.com/openocd-org/openocd + +References +********** + +.. [1] https://en.wikipedia.org/wiki/ESP32 +.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf +.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi rename to boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.dts new file mode 100644 index 00000000000..c52b029ea55 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Espressif ESP32-DevkitC APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.yaml b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.yaml new file mode 100644 index 00000000000..26d4e67df3f --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32_devkitc_wroom/esp32/appcpu +name: ESP32 DEVKITC WROOM APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu_defconfig b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu_defconfig new file mode 100644 index 00000000000..6caadbd90ce --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y +CONFIG_CONSOLE=n +CONFIG_SERIAL=n +CONFIG_UART_CONSOLE=n +CONFIG_GPIO=n diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.dts new file mode 100644 index 00000000000..1708a7badf9 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.dts @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp32_devkitc_wroom-pinctrl.dtsi" +#include +#include + +/ { + model = "Espressif ESP32-DevkitC PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + i2c-0 = &i2c0; + sw0 = &button0; + watchdog0 = &wdt0; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; + cpu-power-states = <&light_sleep &deep_sleep>; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&trng0 { + status = "okay"; +}; + +&psram0 { + status = "disabled"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.yaml b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.yaml new file mode 100644 index 00000000000..88e22e7b170 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.yaml @@ -0,0 +1,25 @@ +identifier: esp32_devkitc_wroom/esp32/procpu +name: ESP32-DevkitC-WROOM-32D +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - adc + - dac + - gpio + - i2c + - watchdog + - uart + - nvs + - pwm + - dac + - spi + - counter + - entropy + - input +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu_defconfig b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu_defconfig new file mode 100644 index 00000000000..3be2d9e39d5 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32_devkitc_wroom/support/openocd.cfg b/boards/espressif/esp32_devkitc_wroom/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32_devkitc_wroom/support/openocd.cfg rename to boards/espressif/esp32_devkitc_wroom/support/openocd.cfg diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig b/boards/espressif/esp32_devkitc_wrover/Kconfig new file mode 100644 index 00000000000..8c64a77ca46 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_DEVKITC_WROVER + select SOC_ESP32_PROCPU if BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig b/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig new file mode 100644 index 00000000000..ba249b4a0a6 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU + +if BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 4096 + +endif # BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover b/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover new file mode 100644 index 00000000000..06cebcd5855 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_DEVKITC_WROVER + select SOC_ESP32_WROVER_E_N4R8 diff --git a/boards/riscv/esp32c3_luatos_core/Kconfig.sysbuild b/boards/espressif/esp32_devkitc_wrover/Kconfig.sysbuild similarity index 100% rename from boards/riscv/esp32c3_luatos_core/Kconfig.sysbuild rename to boards/espressif/esp32_devkitc_wrover/Kconfig.sysbuild diff --git a/boards/xtensa/esp32_devkitc_wrover/board.cmake b/boards/espressif/esp32_devkitc_wrover/board.cmake similarity index 100% rename from boards/xtensa/esp32_devkitc_wrover/board.cmake rename to boards/espressif/esp32_devkitc_wrover/board.cmake diff --git a/boards/espressif/esp32_devkitc_wrover/board.yml b/boards/espressif/esp32_devkitc_wrover/board.yml new file mode 100644 index 00000000000..e0eae97f70f --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32_devkitc_wrover + vendor: espressif + socs: + - name: esp32 diff --git a/boards/xtensa/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg b/boards/espressif/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg similarity index 100% rename from boards/xtensa/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg rename to boards/espressif/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg diff --git a/boards/espressif/esp32_devkitc_wrover/doc/index.rst b/boards/espressif/esp32_devkitc_wrover/doc/index.rst new file mode 100644 index 00000000000..26f3a82e011 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/doc/index.rst @@ -0,0 +1,296 @@ +.. _esp32_devkitc_wrover: + +ESP32-DEVKITC-WROVER +#################### + +Overview +******** + +ESP32 is a series of low cost, low power system on a chip microcontrollers +with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a +Tensilica Xtensa LX6 microprocessor in both dual-core and single-core +variations. ESP32 is created and developed by Espressif Systems, a +Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm +process. [1]_ + +The features include the following: + +- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz +- 520KB of SRAM +- 802.11b/g/n/e/i +- Bluetooth v4.2 BR/EDR and BLE +- Various peripherals: + + - 12-bit ADC with up to 18 channels + - 2x 8-bit DACs + - 10x touch sensors + - Temperature sensor + - 4x SPI + - 2x I2S + - 2x I2C + - 3x UART + - SD/SDIO/MMC host + - Slave (SDIO/SPI) + - Ethernet MAC + - CAN bus 2.0 + - IR (RX/TX) + - Motor PWM + - LED PWM with up to 16 channels + - Hall effect sensor + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) +- 5uA deep sleep current + +.. figure:: img/esp32_devkitc_wrover.jpg + :align: center + :alt: ESP32-DEVKITC-WROVER + + ESP32-DevKitC-WROVER-IE + +Asymmetric Multiprocessing (AMP) +******************************** + +ESP32-DEVKITC-WROVER allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode +and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. + +Supported Features +================== + +Current Zephyr's ESP32-devkitc board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32_devkitc_wrover + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wrover/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32_devkitc_wrover`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wrover/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32_devkitc_wrover + +Debugging +********* + +ESP32 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +On the ESP-WROOM-32 DevKitC board, the JTAG pins are not run to a +standard connector (e.g. ARM 20-pin) and need to be manually connected +to the external programmer (e.g. a Flyswatter2): + ++------------+-----------+ +| ESP32 pin | JTAG pin | ++============+===========+ +| 3V3 | VTRef | ++------------+-----------+ +| EN | nTRST | ++------------+-----------+ +| IO14 | TMS | ++------------+-----------+ +| IO12 | TDI | ++------------+-----------+ +| GND | GND | ++------------+-----------+ +| IO13 | TCK | ++------------+-----------+ +| IO15 | TDO | ++------------+-----------+ + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wrover/esp32/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wrover/esp32/procpu + :goals: debug + +Note on Debugging with GDB Stub +=============================== + +GDB stub is enabled on ESP32. + +* When adding breakpoints, please use hardware breakpoints with command + ``hbreak``. Command ``break`` uses software breakpoints which requires + modifying memory content to insert break/trap instructions. + This does not work as the code is on flash which cannot be randomly + accessed for modification. + +.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html +.. _`OpenOCD`: https://github.com/openocd-org/openocd + +References +********** + +.. [1] https://en.wikipedia.org/wiki/ESP32 +.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf +.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi rename to boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.dts new file mode 100644 index 00000000000..7298148a2c3 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Espressif ESP32-DevkitC WROVER-E APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.yaml b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.yaml new file mode 100644 index 00000000000..8c8e8ae1577 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32_devkitc_wrover/esp32/appcpu +name: ESP32-DevkitC-WROVER-E +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu_defconfig b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.dts new file mode 100644 index 00000000000..60a063bc875 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.dts @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp32_devkitc_wrover-pinctrl.dtsi" +#include +#include + +/ { + model = "Espressif ESP32-DevkitC WROVER-E PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + i2c-0 = &i2c0; + sw0 = &button0; + watchdog0 = &wdt0; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.yaml b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.yaml new file mode 100644 index 00000000000..bf130d7d3a8 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.yaml @@ -0,0 +1,25 @@ +identifier: esp32_devkitc_wrover/esp32/procpu +name: ESP32-DevkitC-WROVER-E +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - adc + - dac + - gpio + - i2c + - watchdog + - uart + - nvs + - pwm + - dac + - spi + - counter + - entropy + - input +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu_defconfig b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu_defconfig new file mode 100644 index 00000000000..3be2d9e39d5 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32_devkitc_wrover/support/openocd.cfg b/boards/espressif/esp32_devkitc_wrover/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32_devkitc_wrover/support/openocd.cfg rename to boards/espressif/esp32_devkitc_wrover/support/openocd.cfg diff --git a/boards/xtensa/esp32_ethernet_kit/CMakeLists.txt b/boards/espressif/esp32_ethernet_kit/CMakeLists.txt similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/CMakeLists.txt rename to boards/espressif/esp32_ethernet_kit/CMakeLists.txt diff --git a/boards/espressif/esp32_ethernet_kit/Kconfig b/boards/espressif/esp32_ethernet_kit/Kconfig new file mode 100644 index 00000000000..0df985354cc --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_ETHERNET_KIT + select SOC_ESP32_PROCPU if BOARD_ESP32_ETHERNET_KIT_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ESP32_ETHERNET_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig b/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig new file mode 100644 index 00000000000..e7f2edb7c05 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig @@ -0,0 +1,33 @@ +# ESP32-ETHERNET-KIT board configuration + +# Copyright (c) 2022 Grant Ramsay +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32_ETHERNET_KIT_ESP32_PROCPU + +config ESP_SPIRAM + default y + +choice SPIRAM_TYPE + default SPIRAM_TYPE_ESPPSRAM64 +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ESP32_ETHERNET_KIT_ESP32_PROCPU + +if BOARD_ESP32_ETHERNET_KIT_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 4096 + +endif # BOARD_ESP32_ETHERNET_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp32_ethernet_kit/Kconfig.esp32_ethernet_kit b/boards/espressif/esp32_ethernet_kit/Kconfig.esp32_ethernet_kit new file mode 100644 index 00000000000..746c7763fda --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/Kconfig.esp32_ethernet_kit @@ -0,0 +1,7 @@ +# ESP32-ETHERNET-KIT board configuration + +# Copyright (c) 2022 Grant Ramsay +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_ETHERNET_KIT + select SOC_ESP32_WROVER_E_N4R8 diff --git a/boards/riscv/icev_wireless/Kconfig.sysbuild b/boards/espressif/esp32_ethernet_kit/Kconfig.sysbuild similarity index 100% rename from boards/riscv/icev_wireless/Kconfig.sysbuild rename to boards/espressif/esp32_ethernet_kit/Kconfig.sysbuild diff --git a/boards/riscv/esp32c3_devkitm/board.cmake b/boards/espressif/esp32_ethernet_kit/board.cmake similarity index 100% rename from boards/riscv/esp32c3_devkitm/board.cmake rename to boards/espressif/esp32_ethernet_kit/board.cmake diff --git a/boards/espressif/esp32_ethernet_kit/board.yml b/boards/espressif/esp32_ethernet_kit/board.yml new file mode 100644 index 00000000000..747690f38a6 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32_ethernet_kit + vendor: espressif + socs: + - name: esp32 diff --git a/boards/xtensa/esp32_ethernet_kit/board_init.c b/boards/espressif/esp32_ethernet_kit/board_init.c similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/board_init.c rename to boards/espressif/esp32_ethernet_kit/board_init.c diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-a-v1.2-layout.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-a-v1.2-layout.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-a-v1.2-layout.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-a-v1.2-layout.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-b-v1.0-layout.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-b-v1.0-layout.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-b-v1.0-layout.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-b-v1.0-layout.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-from-phy.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-from-phy.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-from-phy.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-from-phy.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-to-phy.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-to-phy.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-to-phy.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-to-phy.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.1-block-diagram.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.1-block-diagram.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.1-block-diagram.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.1-block-diagram.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2-overview.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2-overview.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2-overview.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2-overview.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2.jpg diff --git a/boards/espressif/esp32_ethernet_kit/doc/index.rst b/boards/espressif/esp32_ethernet_kit/doc/index.rst new file mode 100644 index 00000000000..fb0bd9aa425 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/doc/index.rst @@ -0,0 +1,623 @@ +.. _esp32_ethernet_kit: + +ESP32-ETHERNET-KIT +################## + +The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables +Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide +more flexible power supply options, the ESP32-Ethernet-Kit also supports power +over Ethernet (PoE). + +.. _get-started-esp32-ethernet-kit-v1.2-overview: + +.. figure:: img/esp32-ethernet-kit-v1.2-overview.jpg + :align: center + :alt: ESP32-Ethernet-Kit V1.2 + :figclass: align-center + + ESP32-Ethernet-Kit V1.2 Overview + +Overview +******** + +ESP32-Ethernet-Kit is an ESP32-based development board produced by +`Espressif `_. + +It consists of two development boards, the Ethernet board A and the PoE +board B. The `Ethernet board (A)`_ contains Bluetooth/Wi-Fi dual-mode +ESP32-WROVER-E module and IP101GRI, a Single Port 10/100 Fast Ethernet +Transceiver (PHY). The `PoE board (B)`_ provides power over Ethernet +functionality. The A board can work independently, without the board B +installed. + +.. _get-started-esp32-ethernet-kit-v1.2: + +.. figure:: img/esp32-ethernet-kit-v1.2.jpg + :align: center + :alt: ESP32-Ethernet-Kit V1.2 + :figclass: align-center + + ESP32-Ethernet-Kit V1.2 + +For the application loading and monitoring, the Ethernet board (A) also +features FTDI FT2232H chip - an advanced multi-interface USB bridge. +This chip enables to use JTAG for direct debugging of ESP32 through the +USB interface without a separate JTAG debugger. + + +Functionality Overview +====================== + +The block diagram below shows the main components of ESP32-Ethernet-Kit +and their interconnections. + +.. figure:: img/esp32-ethernet-kit-v1.1-block-diagram.jpg + :align: center + :alt: ESP32-Ethernet-Kit block diagram + :figclass: align-center + + ESP32-Ethernet-Kit block diagram + + +Functional Description +---------------------- + +The following figures and tables describe the key components, interfaces, +and controls of the ESP32-Ethernet-Kit. + +.. _get-started-esp32-ethernet-kit-a-v1.2-layout: + + +Ethernet Board (A) +^^^^^^^^^^^^^^^^^^ + +.. figure:: img/esp32-ethernet-kit-a-v1.2-layout.jpg + :align: center + :alt: ESP32-Ethernet-Kit V1.2 + :figclass: align-center + + ESP32-Ethernet-Kit - Ethernet board (A) layout + +The table below provides description starting from the picture's top right +corner and going clockwise. + +.. list-table:: Table 1 Component Description + :widths: 40 150 + :header-rows: 1 + + * - Key Component + - Description + * - ESP32-WROVER-E + - This ESP32 module features 64-Mbit PSRAM for flexible extended storage + and data processing capabilities. + * - GPIO Header 2 + - Five unpopulated through-hole solder pads to provide access to selected + GPIOs of ESP32. For details, see `GPIO Header 2`_. + * - Function Switch + - A 4-bit DIP switch used to configure the functionality of selected GPIOs + of ESP32. For details see `Function Switch`_. + * - Tx/Rx LEDs + - Two LEDs to show the status of UART transmission. + * - FT2232H + - The FT2232H chip serves as a multi-protocol USB-to-serial bridge which + can be programmed and controlled via USB to provide communication with + ESP32. FT2232H also features USB-to-JTAG interface which is available + on channel A of the chip, while USB-to-serial is on channel B. + The FT2232H chip enhances user-friendliness in terms of application + development and debugging. See + `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_. + * - USB Port + - USB interface. Power supply for the board as well as the communication + interface between a computer and the board. + * - Power Switch + - Power On/Off Switch. Toggling the switch to **5V0** position powers the + board on, toggling to **GND** position powers the board off. + * - 5V Input + - The 5 V power supply interface can be more convenient when the board is + operating autonomously (not connected to a computer). + * - 5V Power On LED + - This red LED turns on when power is supplied to the board, either from + USB or 5 V Input. + * - DC/DC Converter + - Provided DC 5 V to 3.3 V conversion, output current up to 2 A. + * - Board B Connectors + - A pair male and female header pins for mounting the `PoE board (B)`_ + * - IP101GRI (PHY) + - The physical layer (PHY) connection to the Ethernet cable is + implemented using the + `IP101GRI `_ + chip. The connection between PHY and ESP32 is done through the reduced + media-independent interface (RMII), a variant of the media-independent + interface `(MII) `_ + standard. The PHY supports the IEEE 802.3/802.3u standard of 10/100 + Mbps. + * - RJ45 Port + - Ethernet network data transmission port. + * - Magnetics Module + - The Magnetics are part of the Ethernet specification to protect against + faults and transients, including rejection of common mode signals + between the transceiver IC and the cable. The magnetics also provide + galvanic isolation between the transceiver and the Ethernet device. + * - Link/Activity LEDs + - Two LEDs (green and red) that respectively indicate the "Link" and + "Activity" statuses of the PHY. + * - BOOT Button + - Download button. Holding down **BOOT** and then pressing **EN** + initiates Firmware Download mode for downloading firmware through the + serial port. + * - EN Button + - Reset button. + * - GPIO Header 1 + - This header provides six unpopulated through-hole solder pads connected + to spare GPIOs of ESP32. For details, see `GPIO Header 1`_. + +PoE Board (B) +^^^^^^^^^^^^^ + +This board coverts power delivered over the Ethernet cable (PoE) to provide a +power supply for the Ethernet board (A). The main components of the PoE board +(B) are shown on the block diagram under `Functionality Overview`_. + +The PoE board (B) has the following features: + +* Support for IEEE 802.3at +* Power output: 5 V, 1.4 A + +To take advantage of the PoE functionality the **RJ45 Port** of the Ethernet +board (A) should be connected with an Ethernet cable to a switch that supports +PoE. When the Ethernet board (A) detects 5 V power output from the PoE board +(B), the USB power will be automatically cut off. + +.. figure:: img/esp32-ethernet-kit-b-v1.0-layout.jpg + :align: center + :alt: ESP32-Ethernet-Kit - PoE board (B) + :figclass: align-center + + ESP32-Ethernet-Kit - PoE board (B) layout + +.. list-table:: Table PoE board (B) + :widths: 40 150 + :header-rows: 1 + + * - Key Component + - Description + * - Board A Connector + - Four female (left) and four male (right) header pins for connecting the + PoE board (B) to `Ethernet board (A)`_. The pins on the left accept + power coming from a PoE switch. The pins on the right deliver 5 V power + supply to the Ethernet board (A). + * - External Power Terminals + - Optional power supply (26.6 ~ 54 V) to the PoE board (B). + +.. _get-started-esp32-ethernet-kit-v1.2-setup-options: + + +Setup Options +============= + +This section describes options to configure the ESP32-Ethernet-Kit hardware. + + +Function Switch +--------------- + +When in On position, this DIP switch is routing listed GPIOs to FT2232H to +provide JTAG functionality. When in Off position, the GPIOs may be used for +other purposes. + +======= ================ +DIP SW GPIO Pin +======= ================ + 1 GPIO13 + 2 GPIO12 + 3 GPIO15 + 4 GPIO14 +======= ================ + + +RMII Clock Selection +-------------------- + +The ethernet MAC and PHY under RMII working mode need a common 50 MHz +reference clock (i.e. RMII clock) that can be provided either externally, +or generated from internal ESP32 APLL (not recommended). + +.. note:: + + For additional information on the RMII clock selection, please refer to + `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_, + sheet 2, location D2. + + +RMII Clock Sourced Externally by PHY +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +By default, the ESP32-Ethernet-Kit is configured to provide RMII clock for the +IP101GRI PHY's 50M_CLKO output. The clock signal is generated by the frequency +multiplication of 25 MHz crystal connected to the PHY. For details, please see +the figure below. + +.. figure:: img/esp32-ethernet-kit-rmii-clk-from-phy.jpg + :align: center + :alt: RMII Clock from IP101GRI PHY + :figclass: align-center + + RMII Clock from IP101GRI PHY + +Please note that the PHY is reset on power up by pulling the RESET_N signal +down with a resistor. ESP32 should assert RESET_N high with GPIO5 to enable +PHY. Only this can ensure the power-up of system. Otherwise ESP32 may enter +download mode (when the clock signal of REF_CLK_50M is at a high logic level +during the GPIO0 power-up sampling phase). + + +RMII Clock Sourced Internally from ESP32's APLL +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Another option is to source the RMII Clock from internal ESP32 APLL, see +figure below. The clock signal coming from GPIO0 is first inverted, to account +for transmission line delay, and then supplied to the PHY. + +.. figure:: img/esp32-ethernet-kit-rmii-clk-to-phy.jpg + :align: center + :alt: RMII Clock from ESP Internal APLL + :figclass: align-center + + RMII Clock from ESP Internal APLL + +To implement this option, users need to remove or add some RC components on +the board. For details please refer to +`ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_, +sheet 2, location D2. Please note that if the APLL is already used for other +purposes (e.g. I2S peripheral), then you have no choice but use an external +RMII clock. + + +GPIO Allocation +--------------- + +This section describes allocation of ESP32 GPIOs to specific interfaces or +functions of the ESP32-Ethernet-Kit. + + +IP101GRI (PHY) Interface +^^^^^^^^^^^^^^^^^^^^^^^^ + +The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table +below. Implementation of ESP32-Ethernet-Kit defaults to Reduced +Media-Independent Interface (RMII). + +==== ================ =============== +No. ESP32 Pin (MAC) IP101GRI (PHY) +==== ================ =============== +*RMII Interface* +--------------------------------------- + 1 GPIO21 TX_EN + 2 GPIO19 TXD[0] + 3 GPIO22 TXD[1] + 4 GPIO25 RXD[0] + 5 GPIO26 RXD[1] + 6 GPIO27 CRS_DV + 7 GPIO0 REF_CLK +---- ---------------- --------------- +*Serial Management Interface* +--------------------------------------- + 8 GPIO23 MDC + 9 GPIO18 MDIO +---- ---------------- --------------- +*PHY Reset* +--------------------------------------- +10 GPIO5 Reset_N +==== ================ =============== + +.. note:: + + The allocation of all pins under the ESP32's *RMII Interface* is fixed and + cannot be changed either through IO MUX or GPIO Matrix. REF_CLK can only + be selected from GPIO0, GPIO16 or GPIO17 and it can not be changed through + GPIO Matrix. + + +GPIO Header 1 +^^^^^^^^^^^^^ + +This header exposes some GPIOs that are not used elsewhere on the +ESP32-Ethernet-Kit. + +==== ================ +No. ESP32 Pin +==== ================ + 1 GPIO32 + 2 GPIO33 + 3 GPIO34 + 4 GPIO35 + 5 GPIO36 + 6 GPIO39 +==== ================ + + +GPIO Header 2 +^^^^^^^^^^^^^ + +This header contains GPIOs that may be used for other purposes depending on +scenarios described in column "Comments". + +==== ========== ==================== +No. ESP32 Pin Comments +==== ========== ==================== + 1 GPIO17 See note 1 + 2 GPIO16 See note 1 + 3 GPIO4 + 4 GPIO2 + 5 GPIO13 See note 2 + 6 GPIO12 See note 2 + 7 GPIO15 See note 2 + 8 GPIO14 See note 2 + 9 GND Ground +10 3V3 3.3 V power supply +==== ========== ==================== + +.. note:: + + 1. The ESP32 pins GPIO16 and GPIO17 are not broken out to the + ESP32-WROVER-E module and therefore not available for use. If you need + to use these pins, please solder a module without PSRAM memory inside, + e.g. the ESP32-WROOM-32D or ESP32-SOLO-1. + + 2. Functionality depends on the settings of the `Function Switch`_. + + +GPIO Allocation Summary +^^^^^^^^^^^^^^^^^^^^^^^ + +.. csv-table:: + :header: ESP32-WROVER-E,IP101GRI,UART,JTAG,GPIO,Comments + + S_VP,,,,IO36, + S_VN,,,,IO39, + IO34,,,,IO34, + IO35,,,,IO35, + IO32,,,,IO32, + IO33,,,,IO33, + IO25,RXD[0],,,, + IO26,RXD[1],,,, + IO27,CRS_DV,,,, + IO14,,,TMS,IO14, + IO12,,,TDI,IO12, + IO13,,,TCK,IO13, + IO15,,,TDO,IO15, + IO2,,,,IO2, + IO0,REF_CLK,,,,See note 1 + IO4,,,,IO4, + IO16,,,,IO16 (NC),See note 2 + IO17,,,,IO17 (NC),See note 2 + IO5,Reset_N,,,,See note 1 + IO18,MDIO,,,, + IO19,TXD[0],,,, + IO21,TX_EN,,,, + RXD0,,RXD,,, + TXD0,,TXD,,, + IO22,TXD[1],,,, + IO23,MDC,,,, + +.. note:: + + 1. To prevent the power-on state of the GPIO0 from being affected by the + clock output on the PHY side, the RESET_N signal to PHY defaults to + low, turning the clock output off. After power-on you can control + RESET_N with GPIO5 to turn the clock output on. See also + `RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off + the clock output through RESET_N, it is recommended to use a crystal + module that can be disabled/enabled externally. Similarly like when + using RESET_N, the oscillator module should be disabled by default and + turned on by ESP32 after power-up. For a reference design please see + `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_. + + 2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the + ESP32-WROVER-E module and therefore not available for use. If you need + to use these pins, please solder a module without PSRAM memory inside, + e.g. the ESP32-WROOM-32D or ESP32-SOLO-1. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32_ethernet_kit + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_ethernet_kit/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32_ethernet_kit`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_ethernet_kit/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32_ethernet_kit + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_ethernet_kit/esp32/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_ethernet_kit/esp32/procpu + :goals: debug + + +Enabling Ethernet +***************** + +Enable Ethernet MAC, PHY and MDIO; add these to your device tree overlay: + +.. code-block:: devicetree + + ð { + status = "okay"; + }; + + &phy { + status = "okay"; + }; + + &mdio { + status = "okay"; + }; + +Enable Ethernet in KConfig: + +.. code-block:: cfg + + CONFIG_ETH_ESP32=y + CONFIG_NETWORKING=y + CONFIG_NET_L2_ETHERNET=y + +Board Init +========== + +RESET_N (GPIO5) is automatically set high to enable the Ethernet PHY +during board initialization (board_init.c) + +Related Documents +***************** + +* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic `_ (PDF) +* `ESP32-Ethernet-Kit PoE Board (B) Schematic `_ (PDF) +* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) PCB Layout `_ (PDF) +* `ESP32-Ethernet-Kit PoE Board (B) PCB Layout `_ (PDF) +* `ESP32 Datasheet `_ (PDF) +* `ESP32-WROVER-E Datasheet `_ (PDF) +* `OpenOCD ESP32 `_ diff --git a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi rename to boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.dts new file mode 100644 index 00000000000..c5e1217b25c --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Espressif ESP32-Ethernet-Kit APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.yaml b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.yaml new file mode 100644 index 00000000000..1984dea8da3 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32_ethernet_kit/esp32/appcpu +name: ESP32 ETHERNET KIT +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.dts new file mode 100644 index 00000000000..7e8310c9605 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.dts @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2022 Grant Ramsay + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp32_ethernet_kit-pinctrl.dtsi" + +/ { + model = "Espressif ESP32-Ethernet-Kit PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_default>; + pinctrl-names = "default"; + + phy: ethernet-phy@1 { + compatible = "ethernet-phy"; + status = "disabled"; + reg = <1>; + }; +}; + +ð { + phy-handle = <&phy>; +}; diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.yaml b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.yaml new file mode 100644 index 00000000000..d7d4958d2e7 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.yaml @@ -0,0 +1,17 @@ +identifier: esp32_ethernet_kit/esp32/procpu +name: ESP32 ETHERNET KIT +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - watchdog + - uart + - nvs + - pwm +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu_defconfig b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu_defconfig new file mode 100644 index 00000000000..f029cac9e9e --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32_ethernet_kit/support/openocd.cfg b/boards/espressif/esp32_ethernet_kit/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/support/openocd.cfg rename to boards/espressif/esp32_ethernet_kit/support/openocd.cfg diff --git a/boards/espressif/esp32c3_devkitm/Kconfig.defconfig b/boards/espressif/esp32c3_devkitm/Kconfig.defconfig new file mode 100644 index 00000000000..9944bb87195 --- /dev/null +++ b/boards/espressif/esp32c3_devkitm/Kconfig.defconfig @@ -0,0 +1,15 @@ +# ESP32C3 devkitm board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice diff --git a/boards/espressif/esp32c3_devkitm/Kconfig.esp32c3_devkitm b/boards/espressif/esp32c3_devkitm/Kconfig.esp32c3_devkitm new file mode 100644 index 00000000000..854b9944ef4 --- /dev/null +++ b/boards/espressif/esp32c3_devkitm/Kconfig.esp32c3_devkitm @@ -0,0 +1,7 @@ +# ESP32C3 devkitm board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32C3_DEVKITM + select SOC_ESP32C3_MINI_N4 diff --git a/boards/riscv/stamp_c3/Kconfig.sysbuild b/boards/espressif/esp32c3_devkitm/Kconfig.sysbuild similarity index 100% rename from boards/riscv/stamp_c3/Kconfig.sysbuild rename to boards/espressif/esp32c3_devkitm/Kconfig.sysbuild diff --git a/boards/riscv/icev_wireless/board.cmake b/boards/espressif/esp32c3_devkitm/board.cmake similarity index 100% rename from boards/riscv/icev_wireless/board.cmake rename to boards/espressif/esp32c3_devkitm/board.cmake diff --git a/boards/espressif/esp32c3_devkitm/board.yml b/boards/espressif/esp32c3_devkitm/board.yml new file mode 100644 index 00000000000..649dce34a7d --- /dev/null +++ b/boards/espressif/esp32c3_devkitm/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32c3_devkitm + vendor: espressif + socs: + - name: esp32c3 diff --git a/boards/espressif/esp32c3_devkitm/doc/index.rst b/boards/espressif/esp32c3_devkitm/doc/index.rst new file mode 100644 index 00000000000..379d2c31065 --- /dev/null +++ b/boards/espressif/esp32c3_devkitm/doc/index.rst @@ -0,0 +1,241 @@ +.. _esp32c3_devkitm: + +ESP32-C3 +######## + +Overview +******** + +ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, +based on the open-source RISC-V architecture. It strikes the right balance of power, +I/O capabilities and security, thus offering the optimal cost-effective +solution for connected devices. +The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy, +but it also facilitates a variety of use-cases based on dual connectivity. [1]_ + +The features include the following: + +- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz +- 400 KB of internal RAM +- 802.11b/g/n/e/i +- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh +- Various peripherals: + + - 12-bit ADC with up to 6 channels + - TWAI compatible with CAN bus 2.0 + - Temperature sensor + - 3x SPI + - 1x I2S + - 1x I2C + - 2x UART + - LED PWM with up to 6 channels + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) + +Supported Features +================== + +Current Zephyr's ESP32-C3-Devkitm board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32c3_devkitm + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitm + :goals: build + +The usual ``flash`` target will work with the ``esp32c3_devkitm`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitm + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32c3_devkitm + +Debugging +********* + +As with much custom hardware, the ESP32-C3 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitm + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitm + :goals: debug + +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases + +References +********** + +.. [1] https://www.espressif.com/en/products/socs/esp32-c3 +.. _ESP32C3 Devkitm User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/hw-reference/esp32c3/user-guide-devkitm-1.html +.. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _ESP32C3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi similarity index 100% rename from boards/riscv/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi rename to boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts similarity index 98% rename from boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts rename to boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts index 6c390956e48..e636089ba03 100644 --- a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts @@ -11,7 +11,7 @@ #include / { - model = "esp32c3_devkitm"; + model = "Espressif ESP32-DevkitM"; compatible = "espressif,esp32c3"; chosen { diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.yaml b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml similarity index 100% rename from boards/riscv/esp32c3_devkitm/esp32c3_devkitm.yaml rename to boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm_defconfig b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm_defconfig new file mode 100644 index 00000000000..ef633ce56a1 --- /dev/null +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/riscv/esp32c3_devkitm/support/openocd.cfg b/boards/espressif/esp32c3_devkitm/support/openocd.cfg similarity index 100% rename from boards/riscv/esp32c3_devkitm/support/openocd.cfg rename to boards/espressif/esp32c3_devkitm/support/openocd.cfg diff --git a/boards/espressif/esp32s2_saola/Kconfig.defconfig b/boards/espressif/esp32s2_saola/Kconfig.defconfig new file mode 100644 index 00000000000..5beaa3e15b1 --- /dev/null +++ b/boards/espressif/esp32s2_saola/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ESP32S2 Saola board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config ENTROPY_GENERATOR + default y + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 32768 if WIFI + default 4096 diff --git a/boards/espressif/esp32s2_saola/Kconfig.esp32s2_saola b/boards/espressif/esp32s2_saola/Kconfig.esp32s2_saola new file mode 100644 index 00000000000..f02ec0a49a0 --- /dev/null +++ b/boards/espressif/esp32s2_saola/Kconfig.esp32s2_saola @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S2_SAOLA + select SOC_ESP32S2_WROVER_N4R2 diff --git a/boards/riscv/xiao_esp32c3/Kconfig.sysbuild b/boards/espressif/esp32s2_saola/Kconfig.sysbuild similarity index 100% rename from boards/riscv/xiao_esp32c3/Kconfig.sysbuild rename to boards/espressif/esp32s2_saola/Kconfig.sysbuild diff --git a/boards/riscv/stamp_c3/board.cmake b/boards/espressif/esp32s2_saola/board.cmake similarity index 100% rename from boards/riscv/stamp_c3/board.cmake rename to boards/espressif/esp32s2_saola/board.cmake diff --git a/boards/espressif/esp32s2_saola/board.yml b/boards/espressif/esp32s2_saola/board.yml new file mode 100644 index 00000000000..aafb5f3ee1e --- /dev/null +++ b/boards/espressif/esp32s2_saola/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s2_saola + vendor: espressif + socs: + - name: esp32s2 diff --git a/boards/espressif/esp32s2_saola/doc/index.rst b/boards/espressif/esp32s2_saola/doc/index.rst new file mode 100644 index 00000000000..b329b45f682 --- /dev/null +++ b/boards/espressif/esp32s2_saola/doc/index.rst @@ -0,0 +1,249 @@ +.. _esp32s2_saola: + +ESP32-S2 +######## + +Overview +******** + +ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be secure and +cost-effective, with a high performance and a rich set of IO capabilities. [1]_ + +The features include the following: + +- RSA-3072-based secure boot +- AES-XTS-256-based flash encryption +- Protected private key and device secrets from software access +- Cryptographic accelerators for enhanced performance +- Protection against physical fault injection attacks +- Various peripherals: + + - 43x programmable GPIOs + - 14x configurable capacitive touch GPIOs + - USB OTG + - LCD interface + - camera interface + - SPI + - I2S + - UART + - ADC + - DAC + - LED PWM with up to 8 channels + +Supported Features +================== + +Current Zephyr's ESP32-S2-saola board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32s2_saola + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_saola + :goals: build + +The usual ``flash`` target will work with the ``esp32s2_saola`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_saola + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s2_saola + +Debugging +********* + +ESP32-S2 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +The following table shows the pin mapping between ESP32-S2 board and JTAG interface. + ++---------------+-----------+ +| ESP32 pin | JTAG pin | ++===============+===========+ +| MTDO / GPIO40 | TDO | ++---------------+-----------+ +| MTDI / GPIO41 | TDI | ++---------------+-----------+ +| MTCK / GPIO39 | TCK | ++---------------+-----------+ +| MTMS / GPIO42 | TMS | ++---------------+-----------+ + +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S2`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_saola + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_saola + :goals: debug + +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html + + +References +********** + +.. [1] https://www.espressif.com/en/products/socs/esp32-s2 +.. _ESP32-S2 Saola User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html +.. _ESP32S2 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf +.. _ESP32S2 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola-pinctrl.dtsi b/boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32s2_saola/esp32s2_saola-pinctrl.dtsi rename to boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola.dts b/boards/espressif/esp32s2_saola/esp32s2_saola.dts similarity index 98% rename from boards/xtensa/esp32s2_saola/esp32s2_saola.dts rename to boards/espressif/esp32s2_saola/esp32s2_saola.dts index 781f4b758d6..f7e73bb8f27 100644 --- a/boards/xtensa/esp32s2_saola/esp32s2_saola.dts +++ b/boards/espressif/esp32s2_saola/esp32s2_saola.dts @@ -12,7 +12,7 @@ #include / { - model = "esp32s2_saola"; + model = "Espressif ESP32S2-Saola"; compatible = "espressif,esp32s2"; aliases { diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola.yaml b/boards/espressif/esp32s2_saola/esp32s2_saola.yaml similarity index 100% rename from boards/xtensa/esp32s2_saola/esp32s2_saola.yaml rename to boards/espressif/esp32s2_saola/esp32s2_saola.yaml diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola_defconfig b/boards/espressif/esp32s2_saola/esp32s2_saola_defconfig new file mode 100644 index 00000000000..5476839e2ba --- /dev/null +++ b/boards/espressif/esp32s2_saola/esp32s2_saola_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_franzininho/support/openocd.cfg b/boards/espressif/esp32s2_saola/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32s2_franzininho/support/openocd.cfg rename to boards/espressif/esp32s2_saola/support/openocd.cfg diff --git a/boards/espressif/esp32s3_devkitm/Kconfig b/boards/espressif/esp32s3_devkitm/Kconfig new file mode 100644 index 00000000000..b4ccc062155 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_DEVKITM + select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitm/Kconfig.defconfig b/boards/espressif/esp32s3_devkitm/Kconfig.defconfig new file mode 100644 index 00000000000..1905ae5f551 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/Kconfig.defconfig @@ -0,0 +1,26 @@ +# ESP32S3 DevKitM board configuration + +# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU + +if BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitm/Kconfig.esp32s3_devkitm b/boards/espressif/esp32s3_devkitm/Kconfig.esp32s3_devkitm new file mode 100644 index 00000000000..7b9f2a7d043 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/Kconfig.esp32s3_devkitm @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_DEVKITM + select SOC_ESP32S3_MINI_N8 diff --git a/boards/xtensa/esp32_devkitc_wroom/Kconfig.sysbuild b/boards/espressif/esp32s3_devkitm/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32_devkitc_wroom/Kconfig.sysbuild rename to boards/espressif/esp32s3_devkitm/Kconfig.sysbuild diff --git a/boards/riscv/xiao_esp32c3/board.cmake b/boards/espressif/esp32s3_devkitm/board.cmake similarity index 100% rename from boards/riscv/xiao_esp32c3/board.cmake rename to boards/espressif/esp32s3_devkitm/board.cmake diff --git a/boards/espressif/esp32s3_devkitm/board.yml b/boards/espressif/esp32s3_devkitm/board.yml new file mode 100644 index 00000000000..2d0195fc27d --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s3_devkitm + vendor: espressif + socs: + - name: esp32s3 diff --git a/boards/espressif/esp32s3_devkitm/doc/index.rst b/boards/espressif/esp32s3_devkitm/doc/index.rst new file mode 100644 index 00000000000..5405100f364 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/doc/index.rst @@ -0,0 +1,286 @@ +.. _esp32s3_devkitm: + +ESP32S3-DevKitM +############### + +Overview +******** + +The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1 +or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi +and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitM`_ + +Hardware +******** + +ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi +and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor +(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, +RF module, and numerous peripherals. + +ESP32-S3 DevKitM includes the following features: + +- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz +- Additional vector instructions support for AI acceleration +- 512KB of SRAM +- 384KB of ROM +- Wi-Fi 802.11b/g/n +- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate + +Digital interfaces: + +- 45 programmable GPIOs +- 4x SPI +- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411 +- 1x DVP 8-bit ~16-bit camera interface +- 3x UART +- 2x I2C +- 2x I2S +- 1x RMT (TX/RX) +- 1x pulse counter +- LED PWM controller, up to 8 channels +- 1x full-speed USB OTG +- 1x USB Serial/JTAG controller +- 2x MCPWM +- 1x SDIO host controller with 2 slots +- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels +- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) +- Addressable RGB LED, driven by GPIO48. + +Analog interfaces: + +- 2x 12-bit SAR ADCs, up to 20 channels +- 1x temperature sensor +- 14x touch sensing IOs + +Timers: + +- 4x 54-bit general-purpose timers +- 1x 52-bit system timer +- 3x watchdog timers + +Low Power: + +- Power Management Unit with five power modes +- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM + +Security: + +- Secure boot +- Flash encryption +- 4-Kbit OTP, up to 1792 bits for users +- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) + +Asymmetric Multiprocessing (AMP) +******************************** + +ESP32S3-DevKitM allows 2 different applications to be executed in ESP32-S3 SoC. Due to its dual-core +architecture, each core can be enabled to execute customized tasks in stand-alone mode +and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. + +For more information, check the datasheet at `ESP32-S3 Datasheet`_. + +Supported Features +================== + +Current Zephyr's ESP32-S3-DevKitM board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32s3_devkitm + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32s3_devkitm`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s3_devkitm + +Debugging +********* + +ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32-S3`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm/esp32s3/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm/esp32s3/procpu + :goals: debug + +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`ESP32-S3 DevKitM`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html + +References +********** + +.. _ESP32-S3 DevKitM User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html +.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf +.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi rename to boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.dts new file mode 100644 index 00000000000..3815ebdacf9 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "Espressif ESP32S3-DevkitM APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.yaml b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.yaml new file mode 100644 index 00000000000..7af60717bd4 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32s3_devkitm/esp32s3/appcpu +name: ESP32-S3 DevKitM APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu.dts new file mode 100644 index 00000000000..e0d4461a33b --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu.dts @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp32s3_devkitm-pinctrl.dtsi" +#include +#include + +/ { + model = "Espressif ESP32S3-DevkitM PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + uart-0 = &uart0; + sw0 = &button0; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; + bus-speed = <125000>; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&usb_serial { + status = "disabled"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_.yaml b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_.yaml new file mode 100644 index 00000000000..f9e577353a9 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_.yaml @@ -0,0 +1,23 @@ +identifier: esp32s3_devkitm/esp32s3/procpu +name: ESP32-S3 DevKitM PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_defconfig b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_defconfig new file mode 100644 index 00000000000..d789bab1824 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32s3_devkitm/support/openocd.cfg b/boards/espressif/esp32s3_devkitm/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32s3_devkitm/support/openocd.cfg rename to boards/espressif/esp32s3_devkitm/support/openocd.cfg diff --git a/boards/espressif/esp_wrover_kit/Kconfig b/boards/espressif/esp_wrover_kit/Kconfig new file mode 100644 index 00000000000..df5e831dad1 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP_WROVER_KIT + select SOC_ESP32_PROCPU if BOARD_ESP_WROVER_KIT_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ESP_WROVER_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp_wrover_kit/Kconfig.defconfig b/boards/espressif/esp_wrover_kit/Kconfig.defconfig new file mode 100644 index 00000000000..a05a1684d6b --- /dev/null +++ b/boards/espressif/esp_wrover_kit/Kconfig.defconfig @@ -0,0 +1,29 @@ +# ESP-WROVER-KIT board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP_WROVER_KIT_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +config DISK_DRIVER_SDMMC + default y + +endif # BOARD_ESP_WROVER_KIT_ESP32_PROCPU + +if BOARD_ESP_WROVER_KIT_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 4096 + +endif # BOARD_ESP_WROVER_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp_wrover_kit/Kconfig.esp_wrover_kit b/boards/espressif/esp_wrover_kit/Kconfig.esp_wrover_kit new file mode 100644 index 00000000000..a8ae9779970 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/Kconfig.esp_wrover_kit @@ -0,0 +1,7 @@ +# ESP-WROVER-KIT board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP_WROVER_KIT + select SOC_ESP32_WROVER_E_N4R8 diff --git a/boards/xtensa/esp32_devkitc_wrover/Kconfig.sysbuild b/boards/espressif/esp_wrover_kit/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32_devkitc_wrover/Kconfig.sysbuild rename to boards/espressif/esp_wrover_kit/Kconfig.sysbuild diff --git a/boards/xtensa/esp32_ethernet_kit/board.cmake b/boards/espressif/esp_wrover_kit/board.cmake similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/board.cmake rename to boards/espressif/esp_wrover_kit/board.cmake diff --git a/boards/espressif/esp_wrover_kit/board.yml b/boards/espressif/esp_wrover_kit/board.yml new file mode 100644 index 00000000000..edfaae90477 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/board.yml @@ -0,0 +1,5 @@ +board: + name: esp_wrover_kit + vendor: espressif + socs: + - name: esp32 diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-block-diagram.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-block-diagram.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-block-diagram.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-block-diagram.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp14.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp14.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp14.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp14.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-jtag.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-jtag.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-jtag.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-jtag.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-back.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-back.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-back.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-back.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-front.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-front.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-front.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-front.jpg diff --git a/boards/espressif/esp_wrover_kit/doc/index.rst b/boards/espressif/esp_wrover_kit/doc/index.rst new file mode 100644 index 00000000000..06203863505 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/doc/index.rst @@ -0,0 +1,658 @@ +.. _esp_wrover_kit: + +ESP-WROVER-KIT +############## + +Overview +******** + +ESP-WROVER-KIT is an ESP32-based development board produced by `Espressif `_. + +ESP-WROVER-KIT features the following integrated components: + +- ESP32-WROVER-E module +- LCD screen +- MicroSD card slot + +Its another distinguishing feature is the embedded FTDI FT2232HL chip - an advanced multi-interface +USB bridge. This chip enables to use JTAG for direct debugging of ESP32 through the USB interface +without a separate JTAG debugger. ESP-WROVER-KIT makes development convenient, easy, and +cost-effective. + +Most of the ESP32 I/O pins are broken out to the board's pin headers for easy access. + +.. note:: + + ESP32's GPIO16 and GPIO17 are used as chip select and clock signals for PSRAM. By default, the two + GPIOs are not broken out to the board's pin headers in order to ensure reliable performance. + +Functionality Overview +********************** + +The block diagram below shows the main components of ESP-WROVER-KIT and their interconnections. + +.. image:: img/esp-wrover-kit-block-diagram.jpg + :align: center + :alt: ESP-WROVER-KIT + +Functional Description +********************** + +The following two figures and the table below describe the key components, interfaces, and controls +of the ESP-WROVER-KIT board. + +.. figure:: img/esp-wrover-kit-v4.1-layout-front.jpg + :align: center + :alt: esp wrover front + + ESP-WROVER-KIT board layout - front + +.. _esp wrover back: + +.. figure:: img/esp-wrover-kit-v4.1-layout-back.jpg + :align: center + :alt: esp wrover back + + ESP-WROVER-KIT board layout - back + +The table below provides description in the following manner: +- Starting from the first picture’s top right corner and going clockwise +- Then moving on to the second picture + ++------------------+-------------------------------------------------------------------------+ +| Key Component | Description | ++==================+=========================================================================+ +| FT2232 | The FT2232 chip serves as a multi-protocol USB-to-serial bridge | +| | which can be programmed and controlled via USB to provide | +| | communication with ESP32. FT2232 also features USB-to-JTAG | +| | interface which is available on channel A of the chip, while USB-to- | +| | serial is on channel B. The FT2232 chip enhances user-friendliness in | +| | terms of application development and debugging. See `ESP-WROVER-KIT | +| | V4.1 schematic | +| | `_. | ++------------------+-------------------------------------------------------------------------+ +| 32.768 kHz | External precision 32.768 kHz crystal oscillator serves as a clock with | +| | low-power consumption while the chip is in Deep-sleep mode. | ++------------------+-------------------------------------------------------------------------+ +| 0R | Zero-ohm resistor intended as a placeholder for a current shunt, can | +| | be desoldered or replaced with a current shunt to facilitate the | +| | measurement of ESP32’s current consumption in different modes. | ++------------------+-------------------------------------------------------------------------+ +| ESP32-WROVER-E | This ESP32 module features 64-Mbit PSRAM for flexible extended | +| module | storage and data processing capabilities. | ++------------------+-------------------------------------------------------------------------+ +| Diagnostic LEDs | Four red LEDs connected to the GPIO pins of FT2232. Intended for | +| | future use. | ++------------------+-------------------------------------------------------------------------+ +| UART | Serial port. The serial TX/RX signals of FT2232 and ESP32 are broken | +| | out to the inward and outward sides of JP2 respectively. By default, | +| | these pairs of pins are connected with jumpers. To use ESP32’s serial | +| | interface, remove the jumpers and connect another external serial | +| | device to the respective pins. | ++------------------+-------------------------------------------------------------------------+ +| SPI | By default, ESP32 uses its SPI interface to access flash and PSRAM | +| | memory inside the module. Use these pins to connect ESP32 to | +| | another SPI device. In this case, an extra chip select (CS) signal is | +| | needed. Please note that the voltage of this interface is 3.3 V. | ++------------------+-------------------------------------------------------------------------+ +| CTS/RTS | Serial port flow control signals: the pins are not connected to the | +| | circuitry by default. To enable them, short the respective pins of JP14 | +| | with jumpers. | ++------------------+-------------------------------------------------------------------------+ +| JTAG | JTAG interface. JTAG signals of FT2232 and ESP32 are broken out to | +| | the inward and outward sides of JP2 respectively. By default, these | +| | pairs of pins are disconnected. To enable JTAG, short the respective | +| | pins with jumpers as shown in Section | +| | :ref:`Setup Options` | ++------------------+-------------------------------------------------------------------------+ +| USB Port | USB interface. Power supply for the board as well as the | +| | communication interface between a computer and the board. | ++------------------+-------------------------------------------------------------------------+ +| EN Button | Reset button. | ++------------------+-------------------------------------------------------------------------+ +| BOOT Button | Download button. Holding down Boot and then pressing EN initiates | +| | Firmware Download mode for downloading firmware through the | ++------------------+-------------------------------------------------------------------------+ +| Power Switch | Power On/Off Switch. Toggling toward the Boot button powers the | +| | board on, toggling away from Boot powers the board off. | ++------------------+-------------------------------------------------------------------------+ +| Power Selector | Power supply selector interface. The board can be powered either via | +| | USB or via the 5V Input interface. Select the power source with a | +| | jumper. For more details, see Section Setup Options, jumper header | +| | JP7. | ++------------------+-------------------------------------------------------------------------+ +| 5V input | 5V power supply interface for a standard coaxial power connector, | +| | 5.5 x 2.1 mm, center positive. This interface can be more convenient | +| | when the board is operating autonomously (not connected to a | +| | computer). | ++------------------+-------------------------------------------------------------------------+ +| 5V Power On LED | This red LED turns on when power is supplied to the board, either | +| | from USB or 5V Input. | ++------------------+-------------------------------------------------------------------------+ +| LDO | NCP1117(1A). 5V-to-3.3V LDO. NCP1117 can provide a maximum | +| | current of 1A. The LDO on the board has a fixed output voltage. | +| | Although, the user can install an LDO with adjustable output voltage. | +| | For details, please refer to `ESP-WROVER-KIT V4.1 schematic | +| | `_. | ++------------------+-------------------------------------------------------------------------+ +| Camera Connector | Camera interface, a standard OV7670 camera module. | ++------------------+-------------------------------------------------------------------------+ +| RGB LED | Red, green and blue (RGB) light emitting diodes (LEDs), can be | +| | controlled by pulse width modulation (PWM). | ++------------------+-------------------------------------------------------------------------+ +| I/O Connector | All the pins on the ESP32 module are broken out to pin headers. You | +| | can program ESP32 to enable multiple functions, such as PWM, ADC, | +| | DAC, I2C, I2S, SPI, etc. | ++------------------+-------------------------------------------------------------------------+ +| MicroSD Card | Useful for developing applications that access MicroSD card for data | +| Slot | storage and retrieval. | ++------------------+-------------------------------------------------------------------------+ +| LCD | Support for mounting and interfacing a 3.2” SPI (standard 4-wire | +| | Serial Peripheral Interface) LCD, as shown on figure | +| | :ref:`ESP-WROVER-KIT board layout - back` | ++------------------+-------------------------------------------------------------------------+ + +.. _setup options: + +Setup Options +************* + +There are three jumper blocks available to set up the board functionality. The most frequently +required options are listed in the table below. + +.. |jmpextpwr| image:: img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg + +.. |jmpusbpwr| image:: img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg + +.. |jmpjtag| image:: img/esp-wrover-kit-v4.1-jp2-jtag.jpg + +.. |jmpuart| image:: img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg + +.. |jmpctrl| image:: img/esp-wrover-kit-v4.1-jp14.jpg + ++------------------+--------------------------------------------------------------+ +| Header | Jumper Setting | Description of Functionality | ++========+================+=======================================================+ +| JP7 | |jmpextpwr| | Power ESP-WROVER-KIT via an external power supply | ++--------+----------------+-------------------------------------------------------+ +| JP7 | |jmpusbpwr| | Power ESP-WROVER-KIT via USB | ++--------+----------------+-------------------------------------------------------+ +| JP2 | |jmpjtag| | Enable JTAG functionality | ++--------+----------------+-------------------------------------------------------+ +| JP2 | |jmpuart| | Enable UART communication | ++--------+----------------+-------------------------------------------------------+ +| JP14 | |jmpctrl| | Enable RTS/CTS flow control for serial communication | ++--------+----------------+-------------------------------------------------------+ + +Allocation of ESP32 Pins +************************ + +Some pins / terminals of ESP32 are allocated for use with the onboard or external hardware. If +that hardware is not used, e.g., nothing is plugged into the Camera (JP4) header, then these +GPIOs can be used for other purposes. + +Some of the pins, such as GPIO0 or GPIO2, have multiple functions and some of them are shared +among onboard and external peripheral devices. Certain combinations of peripherals cannot work +together. For example, it is not possible to do JTAG debugging of an application that is using +SD card, because several pins are shared by JTAG and the SD card slot. + +In other cases, peripherals can coexist under certain conditions. This is applicable to, for +example, LCD screen and SD card that share only a single pin GPIO21. This pin is used to provide +D/C (Data / Control) signal for the LCD as well as the Card Detect signal read from the SD card +slot. If the card detect functionality is not essential, then it may be disabled by removing R167, +so both LCD and SD may operate together. + +For more details on which pins are shared among which peripherals, please refer to the table in +the next section. + +Main I/O Connector / JP1 +************************ + +The JP1 connector consists of 14x2 male pins whose functions are shown in the middle two “I/O” +columns of the table below. The two “Shared With” columns on both sides describe where else on +the board a certain GPIO is used. + ++-------------------+------+------+----------------------+ +| Shared With | I/O | I/O | Shared With | ++===================+======+======+======================+ +| n/a | 3.3V | GND | n/a | ++-------------------+------+------+----------------------+ +| NC/XTAL | IO32 | IO33 | NC/XTAL | ++-------------------+------+------+----------------------+ +| JTAG, MicroSD | IO12 | IO13 | JTAG, MicroSD | ++-------------------+------+------+----------------------+ +| JTAG, MicroSD | IO14 | IO27 | Camera | ++-------------------+------+------+----------------------+ +| Camera | IO26 | IO25 | Camera, LCD | ++-------------------+------+------+----------------------+ +| Camera | IO35 | IO34 | Camera | ++-------------------+------+------+----------------------+ +| Camera | IO39 | IO36 | Camera | ++-------------------+------+------+----------------------+ +| JTAG | EN | IO23 | Camera, LCD | ++-------------------+------+------+----------------------+ +| Camera, LCD | IO22 | IO21 | Camera, LCD, MicroSD | ++-------------------+------+------+----------------------+ +| Camera, LCD | IO19 | IO18 | Camera, LCD | ++-------------------+------+------+----------------------+ +| Camera, LCD | IO5 | IO17 | PSRAM | ++-------------------+------+------+----------------------+ +| PSRAM | IO16 | IO4 | LED, Camera, MicroSD | ++-------------------+------+------+----------------------+ +| Camera, LED, Boot | IO0 | IO2 | LED, MicroSD | ++-------------------+------+------+----------------------+ +| JTAG, MicroSD | IO15 | 5V | | ++-------------------+------+------+----------------------+ + +Legend: + + - NC/XTAL - 32.768 kHz Oscillator + - JTAG - JTAG / JP2 + - Boot - Boot button / SW2 + - Camera - Camera / JP4 + - LED - RGB LED + - MicroSD - MicroSD Card / J4 + - LCD - LCD / U5 + - PSRAM - ESP32-WROVER-E’s PSRAM + +32.768 kHz Oscillator +********************* + ++---+-----------+ +| . | ESP32 Pin | ++===+===========+ +| 1 | GPIO32 | ++---+-----------+ +| 2 | GPIO33 | ++---+-----------+ + +.. note:: + + Since GPIO32 and GPIO33 are connected to the oscillator by default, they are not connected to + the JP1 I/O connector to maintain signal integrity. This allocation may be changed from the + oscillator to JP1 by desoldering the zero-ohm resistors from positions R11 / R23 and re- + soldering them to positions R12 / R24. + +SPI Flash / JP2 +*************** + ++---+--------------+ +| . | ESP32 Pin | ++===+==============+ +| 1 | CLK / GPIO6 | ++---+--------------+ +| 2 | SD0 / GPIO7 | ++---+--------------+ +| 3 | SD1 / GPIO8 | ++---+--------------+ +| 4 | SD2 / GPIO9 | ++---+--------------+ +| 5 | SD3 / GPIO10 | ++---+--------------+ +| 6 | CDM / GPIO11 | ++---+--------------+ + +.. important:: + The module’s flash bus is connected to the jumper block JP2 through zero-ohm resistors R140 ~ + R145. If the flash memory needs to operate at the frequency of 80 MHz, for reasons such as + improving the integrity of bus signals, you can desolder these resistors to disconnect the + module’s flash bus from the pin header JP2. + +JTAG / JP2 +********** + ++---+---------------+-------------+ +| . | ESP32 Pin | JTAG Signal | ++===+===============+=============+ +| 1 | EN | TRST_N | ++---+---------------+-------------+ +| 2 | MTMS / GPIO14 | TMS | ++---+---------------+-------------+ +| 3 | MTDO / GPIO15 | TDO | ++---+---------------+-------------+ +| 4 | MTDI / GPIO12 | TDI | ++---+---------------+-------------+ +| 5 | MTCK / GPIO13 | TCK | ++---+---------------+-------------+ + +Camera / JP4 +************ + ++----+-----------+-----------------------------+ +| . | ESP32 Pin | Camera Signal | ++====+===========+=============================+ +| 1 | n/a | 3.3V | ++----+-----------+-----------------------------+ +| 2 | n/a | Ground | ++----+-----------+-----------------------------+ +| 3 | GPIO27 | SIO_C / SCCB Clock | ++----+-----------+-----------------------------+ +| 4 | GPIO26 | SIO_D / SCCB Data | ++----+-----------+-----------------------------+ +| 5 | GPIO25 | VSYNC / Vertical Sync | ++----+-----------+-----------------------------+ +| 6 | GPIO23 | HREF / Horizontal Reference | ++----+-----------+-----------------------------+ +| 7 | GPIO22 | PCLK / Pixel Clock | ++----+-----------+-----------------------------+ +| 8 | GPIO21 | XCLK / System Clock | ++----+-----------+-----------------------------+ +| 9 | GPIO35 | D7 / Pixel Data Bit 7 | ++----+-----------+-----------------------------+ +| 10 | GPIO34 | D6 / Pixel Data Bit 6 | ++----+-----------+-----------------------------+ +| 11 | GPIO39 | D5 / Pixel Data Bit 5 | ++----+-----------+-----------------------------+ +| 12 | GPIO36 | D4 / Pixel Data Bit 4 | ++----+-----------+-----------------------------+ +| 13 | GPIO19 | D3 / Pixel Data Bit 3 | ++----+-----------+-----------------------------+ +| 14 | GPIO18 | D2 / Pixel Data Bit 2 | ++----+-----------+-----------------------------+ +| 15 | GPIO5 | D1 / Pixel Data Bit 1 | ++----+-----------+-----------------------------+ +| 16 | GPIO4 | D0 / Pixel Data Bit 0 | ++----+-----------+-----------------------------+ +| 17 | GPIO0 | RESET / Camera Reset | ++----+-----------+-----------------------------+ +| 18 | n/a | PWDN / Camera Power Down | ++----+-----------+-----------------------------+ + +- Signals D0 .. D7 denote camera data bus + +RGB LED +******* + ++----+-----------+---------+ +| . | ESP32 Pin | RGB LED | ++====+===========+=========+ +| 1 | GPIO0 | Red | ++----+-----------+---------+ +| 2 | GPIO2 | Green | ++----+-----------+---------+ +| 3 | GPIO4 | Blue | ++----+-----------+---------+ + +MicroSD Card +************ + ++---+---------------+----------------+ +| . | ESP32 Pin | MicroSD Signal | ++===+===============+================+ +| 1 | MTDI / GPIO12 | DATA2 | ++---+---------------+----------------+ +| 2 | MTCK / GPIO13 | CD / DATA3 | ++---+---------------+----------------+ +| 3 | MTDO / GPIO15 | CMD | ++---+---------------+----------------+ +| 4 | MTMS / GPIO14 | CLK | ++---+---------------+----------------+ +| 5 | GPIO2 | DATA0 | ++---+---------------+----------------+ +| 6 | GPIO4 | DATA1 | ++---+---------------+----------------+ +| 7 | GPIO21 | Card Detect | ++---+---------------+----------------+ + +LCD / U5 +******** + ++---+-----------+------------+ +| . | ESP32 Pin | LCD Signal | ++===+===========+============+ +| 1 | GPIO18 | RESET | ++---+-----------+------------+ +| 2 | GPIO19 | SCL | ++---+-----------+------------+ +| 3 | GPIO21 | D/C | ++---+-----------+------------+ +| 4 | GPIO22 | CS | ++---+-----------+------------+ +| 5 | GPIO23 | SDA | ++---+-----------+------------+ +| 6 | GPIO25 | SDO | ++---+-----------+------------+ +| 7 | GPIO5 | Backlight | ++---+-----------+------------+ + +Start Application Development +***************************** + +Before powering up your ESP-WROVER-KIT, please make sure that the board is in good +condition with no obvious signs of damage. + +Initial Setup +************* + +Please set only the following jumpers shown in the pictures below: + +- Select USB as the power source using the jumper block JP7. +- Enable UART communication using the jumper block JP2. + ++------------------------+---------------------------+ +| Power up from USB port | Enable UART communication | ++========+===============+===========================+ +| |jmpusbpwr| | |jmpuart| | ++------------------------+---------------------------+ + +Do not install any other jumpers. + +Turn the Power Switch to ON, the 5V Power On LED should light up. + +Supported Features +================== + +Current Zephyr's ESP32-Wrover-Kit board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp_wrover_kit + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp_wrover_kit/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp_wrover_kit`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp_wrover_kit/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp_wrover_kit + +Debugging +********* + +ESP32 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +On the ESP-WROVER-KIT board, the JTAG pins are connected internally to +a USB serial port on the same device as the console. These boards +require no external hardware and are debuggable as-is. The JTAG +signals, however, must be jumpered closed to connect the internal +controller (the default is to leave them disconnected). The jumper +headers are on the right side of the board as viewed from the power +switch, next to similar headers for SPI and UART. See +`ESP-WROVER-32 V3 Getting Started Guide`_ for details. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp_wrover_kit/esp32/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp_wrover_kit/esp32/procpu + :goals: debug + +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`ESP-WROVER-32 V3 Getting Started Guide`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/esp32/get-started-wrover-kit.html + +Related Documents +***************** + +.. _ESP-WROVER-KIT V4.1 schematics: https://dl.espressif.com/dl/schematics/ESP-WROVER-KIT_V4_1.pdf (PDF) +.. _ESP-WROVER-KIT V4.1 layout: https://dl.espressif.com/dl/schematics/ESP-WROVER-KIT_V4.1.dxf (DXF) +.. _ESP32 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf (PDF) +.. _ESP32-WROVER-E Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf (PDF) +.. _ESP32 Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi b/boards/espressif/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi rename to boards/espressif/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.dts new file mode 100644 index 00000000000..f0a046705ee --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Espressif ESP32-Wrover-Kit APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.yaml b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.yaml new file mode 100644 index 00000000000..64f7ef2124f --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp_wrover_kit/esp32/appcpu +name: ESP WROVER KIT +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.dts new file mode 100644 index 00000000000..3709a13b475 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.dts @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp_wrover_kit-pinctrl.dtsi" + +/ { + model = "Espressif ESP32-Wrover-Kit PROCPU"; + compatible = "espressif,esp32"; + + aliases { + led0 = &blue_led; + led1 = &green_led; + led2 = &red_led; + pwm-led0 = &pwm_led_red; + pwm-led1 = &pwm_led_green; + pwm-led2 = &pwm_led_blue; + red-pwm-led = &pwm_led_red; + green-pwm-led = &pwm_led_green; + blue-pwm-led = &pwm_led_blue; + uart-0 = &uart0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,display = &ili9341; + }; + + leds { + compatible = "gpio-leds"; + + blue_led: led_0 { + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + label = "Blue - LED0"; + }; + + green_led: led_1 { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + label = "Green - LED1"; + }; + + red_led: led_2 { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + label = "Red - LED2"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led_red: pwm_led_0 { + label = "Red PWM LED"; + pwms = <&ledc0 0 PWM_HZ(100) PWM_POLARITY_NORMAL>; + }; + pwm_led_green: pwm_led_1 { + label = "Green PWM LED"; + pwms = <&ledc0 1 PWM_HZ(100) PWM_POLARITY_NORMAL>; + }; + pwm_led_blue: pwm_led_2 { + label = "Blue PWM LED"; + pwms = <&ledc0 2 PWM_HZ(100) PWM_POLARITY_NORMAL>; + }; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + spi-dev = <&spi3>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + ili9341: ili9341@0 { + compatible = "ilitek,ili9341"; + mipi-max-frequency = <25000000>; + reg = <0>; + pixel-format = <0>; + rotation = <0>; + width = <240>; + height = <320>; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; + + /* FIXME: should be part of the display node */ + lcd-backlight { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&ledc0 { + pinctrl-0 = <&ledc0_default>; + pinctrl-names = "default"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + channel0@0 { + reg = <0x0>; + timer = <0>; + }; + channel1@1 { + reg = <0x1>; + timer = <1>; + }; + channel2@2 { + reg = <0x2>; + timer = <2>; + }; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.yaml b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.yaml new file mode 100644 index 00000000000..80c6a5d3983 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.yaml @@ -0,0 +1,23 @@ +identifier: esp_wrover_kit/esp32/procpu +name: ESP WROVER KIT +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - adc + - dac + - gpio + - i2c + - watchdog + - uart + - nvs + - pwm + - spi + - counter + - entropy +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu_defconfig b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu_defconfig new file mode 100644 index 00000000000..f029cac9e9e --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp_wrover_kit/support/openocd.cfg b/boards/espressif/esp_wrover_kit/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp_wrover_kit/support/openocd.cfg rename to boards/espressif/esp_wrover_kit/support/openocd.cfg diff --git a/boards/espressif/index.rst b/boards/espressif/index.rst new file mode 100644 index 00000000000..b1b7dfbeede --- /dev/null +++ b/boards/espressif/index.rst @@ -0,0 +1,10 @@ +.. _boards-espressif: + +Espressif +######### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/fanke/fk7b0m1_vbt6/Kconfig.fk7b0m1_vbt6 b/boards/fanke/fk7b0m1_vbt6/Kconfig.fk7b0m1_vbt6 new file mode 100644 index 00000000000..3f87d271463 --- /dev/null +++ b/boards/fanke/fk7b0m1_vbt6/Kconfig.fk7b0m1_vbt6 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Charles Dias +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FK7B0M1_VBT6 + select SOC_STM32H7B0XX diff --git a/boards/arm/fk7b0m1_vbt6/board.cmake b/boards/fanke/fk7b0m1_vbt6/board.cmake similarity index 100% rename from boards/arm/fk7b0m1_vbt6/board.cmake rename to boards/fanke/fk7b0m1_vbt6/board.cmake diff --git a/boards/fanke/fk7b0m1_vbt6/board.yml b/boards/fanke/fk7b0m1_vbt6/board.yml new file mode 100644 index 00000000000..204e3538a93 --- /dev/null +++ b/boards/fanke/fk7b0m1_vbt6/board.yml @@ -0,0 +1,5 @@ +board: + name: fk7b0m1_vbt6 + vendor: fanke + socs: + - name: stm32h7b0xx diff --git a/boards/arm/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6.webp b/boards/fanke/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6.webp similarity index 100% rename from boards/arm/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6.webp rename to boards/fanke/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6.webp diff --git a/boards/arm/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6_pins.webp b/boards/fanke/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6_pins.webp similarity index 100% rename from boards/arm/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6_pins.webp rename to boards/fanke/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6_pins.webp diff --git a/boards/fanke/fk7b0m1_vbt6/doc/index.rst b/boards/fanke/fk7b0m1_vbt6/doc/index.rst new file mode 100644 index 00000000000..220fc514d4c --- /dev/null +++ b/boards/fanke/fk7b0m1_vbt6/doc/index.rst @@ -0,0 +1,179 @@ +.. _fk7b0m1_vbt6: + +FANKE FK7B0M1-VBT6 +################## + +Overview +******** + +The FK7B0M1-VBT6 core board by FANKE Technology Co., Ltd. is an advanced microcontroller +platform based on the STMicroelectronics Arm® Cortex®-M7 core STM32H7B0VBT6 microcontroller. +This board is an ideal solution for developers looking to create high-performance +applications, especially in the field of Human-Machine Interface (HMI), leveraging its +robust capabilities and support for sophisticated display and touch technologies. + +The FK7B0M1-VBT6 is designed as a reference design for user application development before +transitioning to the final product, significantly simplifying the development process. +Its wide range of hardware features, including advanced display and touch capabilities, +make it exceptionally suitable for HMI applications, allowing for comprehensive evaluation +and testing of peripherals and functionalities. + +.. figure:: img/fk7b0m1_vbt6.webp + :width: 600px + :align: center + :alt: FK7B0M1-VBT6 + + FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd) + +Hardware +******** + +FK7B0M1-VBT6 provides the following hardware components: + +- STM32H7B6VB in LQFP100 package +- ARM 32-bit Cortex-M7 CPU with FPU +- 280 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 128 KB Flash +- ~1.4 MB SRAM max (1.18 Mbytes user SRAM + 64 Kbytes ITCM RAM + 128 Kbytes DTCM RAM + 4 Kbytes SRAM in Backup domain) +- Main clock: External 25MHz crystal oscillator. +- RTC: 32.768kHz crystal oscillator. +- 32-bit timers(2) +- 16-bit timers(12) +- 1 reset button, 1 user button, and 1 BOOT button +- 1 user LED +- External 64-Mbit QSPI (W25Q64) NOR Flash memory. +- External 64-Mbit SPI (W25Q64) NOR Flash memory. +- USB OTG Full Speed and High Speed(1) +- 1 micro SD card +- 1 RGB LCD interface +- SWD and serial port accessibility through a pin header +- Bring out 39 IO ports + +More information about STM32H7B0VB can be found here: + +- `STM32H7B0VB on www.st.com`_ + +Supported Features +================== + +The Zephyr nucleo_h723zg board configuration supports the following hardware +features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration per core can be found in +:zephyr_file:`boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig` + +Connections and IOs +=================== + +Available pins: +--------------- + +Nucleo FK7B0M1-VBT6 board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +.. figure:: img/fk7b0m1_vbt6_pins.webp + :width: 600px + :align: center + :alt: FK7B0M1-VBT6 + + FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd) + +LED +--- + +- User LED (blue) = PC1 + +Push buttons +------------------------- + +- BOOT = SW1 = BOOT0 +- RESET = SW2 = NRST +- User button = SW3 = PC13 + +UART +----- + +- TX device = USART1 PA9 +- RX device = USART1 PA10 + +USB +--- + +- USB D- = PA11 +- USB D+ = PA12 + +System Clock +============ + +The FK7B0M1-VBT6 System Clock could be driven by an internal or external oscillator, +as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 280MHz, +driven by an 25MHz external crystal oscillator. + +Serial Port +=========== + +The Zephyr console output is assigned to UART1. The default communication settings are 115200 8N1. + +Programming and Debugging +************************* + +The FK7B0M1-VBT6 board does not include an on-board debugger. As a result, it requires +an external debugger, such as ST-Link, for programming and debugging purposes. + +The board provides header pins for the Serial Wire Debug (SWD) interface. + +Flashing +======== + +To begin, connect the ST-Link Debug Programmer to the FK7B0M1-VBT6 board using the SWD +interface. Next, connect the ST-Link to your host computer via a USB port. +Once this setup is complete, you can proceed to build and flash your application to the board + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: fk7b0m1_vbt6 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 -b 115200 + +Then, press the RESET button, you should see the following message: + +.. code-block:: console + + Hello World! fk7b0m1_vbt6 + +Debugging +========= + +This current Zephyr port does not support debugging. + +References +********** + +.. target-notes:: +.. _STM32H7B0VB on www.st.com: https://www.st.com/en/microcontrollers/stm32h7b0vb.html diff --git a/boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6.dts b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts similarity index 100% rename from boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6.dts rename to boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts diff --git a/boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml similarity index 100% rename from boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml rename to boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml diff --git a/boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig similarity index 87% rename from boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig rename to boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig index 72587a3a897..dd4c5e18475 100644 --- a/boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig +++ b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig @@ -1,9 +1,6 @@ # Copyright (c) Charles Dias # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H7B0XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/fk7b0m1_vbt6/support/openocd.cfg b/boards/fanke/fk7b0m1_vbt6/support/openocd.cfg similarity index 100% rename from boards/arm/fk7b0m1_vbt6/support/openocd.cfg rename to boards/fanke/fk7b0m1_vbt6/support/openocd.cfg diff --git a/boards/fanke/index.rst b/boards/fanke/index.rst new file mode 100644 index 00000000000..2c9434547ae --- /dev/null +++ b/boards/fanke/index.rst @@ -0,0 +1,10 @@ +.. _boards-fanke: + +Fanke +##### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/firefly/index.rst b/boards/firefly/index.rst new file mode 100644 index 00000000000..3ba363b1d9f --- /dev/null +++ b/boards/firefly/index.rst @@ -0,0 +1,10 @@ +.. _boards-firefly: + +Firefly +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/frdm_k64f/CMakeLists.txt b/boards/firefly/roc_rk3568_pc/CMakeLists.txt similarity index 100% rename from boards/arm/frdm_k64f/CMakeLists.txt rename to boards/firefly/roc_rk3568_pc/CMakeLists.txt diff --git a/boards/firefly/roc_rk3568_pc/Kconfig.roc_rk3568_pc b/boards/firefly/roc_rk3568_pc/Kconfig.roc_rk3568_pc new file mode 100644 index 00000000000..eda2cdb36b6 --- /dev/null +++ b/boards/firefly/roc_rk3568_pc/Kconfig.roc_rk3568_pc @@ -0,0 +1,6 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ROC_RK3568_PC + select SOC_RK3568 diff --git a/boards/arm/google_kukui/board.cmake b/boards/firefly/roc_rk3568_pc/board.cmake similarity index 100% rename from boards/arm/google_kukui/board.cmake rename to boards/firefly/roc_rk3568_pc/board.cmake diff --git a/boards/firefly/roc_rk3568_pc/board.yml b/boards/firefly/roc_rk3568_pc/board.yml new file mode 100644 index 00000000000..8a60a165dc4 --- /dev/null +++ b/boards/firefly/roc_rk3568_pc/board.yml @@ -0,0 +1,7 @@ +board: + name: roc_rk3568_pc + vendor: firefly + socs: + - name: rk3568 + variants: + - name: smp diff --git a/boards/firefly/roc_rk3568_pc/doc/index.rst b/boards/firefly/roc_rk3568_pc/doc/index.rst new file mode 100644 index 00000000000..4da6df1023a --- /dev/null +++ b/boards/firefly/roc_rk3568_pc/doc/index.rst @@ -0,0 +1,142 @@ +.. _roc_rk3568_pc: + +Firefly ROC-RK3568-PC (Quad-core Cortex-A55) +############################################ + +Overview +******** + +The ROC-RK3568-PC is a Quad-Core 64-Bit Mini Computer, which supports 4G large RAM. M.2 +and SATA3.0 interfaces enables expansion with large hard drives. +Providing dual Gigabit Ethernet ports, it supports WiFi 6 wireless transmission. +Control Port can be connected with RS485/RS232 devices. + +RK3568 quad-core 64-bit Cortex-A55 processor, with brand new ARM v8.2-A architecture, +has frequency up to 2.0GHz. Zephyr OS is ported to run on it. + + +- Board features: + + - RAM: 4GB LPDDR4 + - Storage: + + - 32GB eMMC + - M.2 PCIe 3.0 x 1 (Expand with 2242 / 2280 NVMe SSD) + - TF-Card Slot + - Wireless: + + - Supports WiFi 6 (802.11 AX) + - Supports BT5.0 + - USB: + + - One USB 3.0 + - Two USB 2.0 + - One Type-C + - Ethernet + - M.2 PCIe3.0 (Expand with NVMe SSD) + - LEDs: + + - 1x Power status LED + - Debug + + - UART debug ports for board + + +Supported Features +================== + +The Zephyr roc_rk3568_pc board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz. +Cortex-A55 Core runs up to 2.0 GHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART2. + +Programming and Debugging +************************* + +Use U-Boot to load the zephyr.bin to the memory and kick it: + +.. code-block:: console + + tftp 0x40000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x40000000 + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: roc_rk3568_pc + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build bc695c6df5eb *** + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 0 on roc_rk3568_pc! + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 0 on roc_rk3568_pc! + + +``roc_rk3568_pc//smp`` support, use this configuration to run Zephyr smp applications and subsys tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: roc_rk3568_pc//smp + :goals: run + +This will build an image with the shell_module sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build bc695c6df5eb *** + I/TC: Secondary CPU 1 initializing + I/TC: Secondary CPU 1 switching to normal world boot + I/TC: Secondary CPU 2 initializing + I/TC: Secondary CPU 2 switching to normal world boot + I/TC: Secondary CPU 3 initializing + I/TC: Secondary CPU 3 switching to normal world boot + Secondary CPU core 1 (MPID:0x100) is up + Secondary CPU core 2 (MPID:0x200) is up + Secondary CPU core 3 (MPID:0x300) is up + + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 1 on roc_rk3568_pc! + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 1 on roc_rk3568_pc! + +References +========== + +More information can refer to Firefly official website: +`Firefly website`_. + +.. _Firefly website: + https://en.t-firefly.com/product/industry/rocrk3568pc.html?theme=pc diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.dts b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc.dts similarity index 100% rename from boards/arm64/roc_rk3568_pc/roc_rk3568_pc.dts rename to boards/firefly/roc_rk3568_pc/roc_rk3568_pc.dts diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.yaml b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc.yaml similarity index 100% rename from boards/arm64/roc_rk3568_pc/roc_rk3568_pc.yaml rename to boards/firefly/roc_rk3568_pc/roc_rk3568_pc.yaml diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_defconfig b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_defconfig similarity index 85% rename from boards/arm64/roc_rk3568_pc/roc_rk3568_pc_defconfig rename to boards/firefly/roc_rk3568_pc/roc_rk3568_pc_defconfig index d85c08d24e7..e9d051b573a 100644 --- a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_defconfig +++ b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_defconfig @@ -3,9 +3,6 @@ # SPDX-License-Identifier: Apache-2.0 # Platform Configuration -CONFIG_SOC_SERIES_RK3568=y -CONFIG_SOC_RK3568=y -CONFIG_BOARD_ROC_RK3568_PC=y CONFIG_ARM_ARCH_TIMER=y # Serial Drivers diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.dts b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.dts similarity index 100% rename from boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.dts rename to boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.dts diff --git a/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.yaml b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.yaml new file mode 100644 index 00000000000..fdf59e56fca --- /dev/null +++ b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.yaml @@ -0,0 +1,14 @@ +identifier: roc_rk3568_pc/rk3568/smp +name: Rockchip ROC RK3568 PC SMP +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - smp +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig new file mode 100644 index 00000000000..5d5b627f549 --- /dev/null +++ b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig @@ -0,0 +1,15 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +# SMP support +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 +CONFIG_MAX_THREAD_BYTES=4 + +# ARMv8 NS world with cache management +CONFIG_DCACHE=y + +# PSCI support +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y diff --git a/boards/franzininho/esp32s2_franzininho/Kconfig.defconfig b/boards/franzininho/esp32s2_franzininho/Kconfig.defconfig new file mode 100644 index 00000000000..7bf6f84463b --- /dev/null +++ b/boards/franzininho/esp32s2_franzininho/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ESP32S2 Franzininho board configuration + +# Copyright (c) 2022 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +config ENTROPY_GENERATOR + default y + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 32768 if WIFI + default 4096 diff --git a/boards/franzininho/esp32s2_franzininho/Kconfig.esp32s2_franzininho b/boards/franzininho/esp32s2_franzininho/Kconfig.esp32s2_franzininho new file mode 100644 index 00000000000..61c438408b5 --- /dev/null +++ b/boards/franzininho/esp32s2_franzininho/Kconfig.esp32s2_franzininho @@ -0,0 +1,7 @@ +# ESP32S2 Franzininho board configuration + +# Copyright (c) 2022 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S2_FRANZININHO + select SOC_ESP32S2_WROOM diff --git a/boards/xtensa/esp32_ethernet_kit/Kconfig.sysbuild b/boards/franzininho/esp32s2_franzininho/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/Kconfig.sysbuild rename to boards/franzininho/esp32s2_franzininho/Kconfig.sysbuild diff --git a/boards/xtensa/esp32s2_franzininho/board.cmake b/boards/franzininho/esp32s2_franzininho/board.cmake similarity index 100% rename from boards/xtensa/esp32s2_franzininho/board.cmake rename to boards/franzininho/esp32s2_franzininho/board.cmake diff --git a/boards/franzininho/esp32s2_franzininho/board.yml b/boards/franzininho/esp32s2_franzininho/board.yml new file mode 100644 index 00000000000..913c4d4232f --- /dev/null +++ b/boards/franzininho/esp32s2_franzininho/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s2_franzininho + vendor: espressif + socs: + - name: esp32s2 diff --git a/boards/xtensa/esp32s2_franzininho/doc/img/esp32_s2_franzininho.jpg b/boards/franzininho/esp32s2_franzininho/doc/img/esp32_s2_franzininho.jpg similarity index 100% rename from boards/xtensa/esp32s2_franzininho/doc/img/esp32_s2_franzininho.jpg rename to boards/franzininho/esp32s2_franzininho/doc/img/esp32_s2_franzininho.jpg diff --git a/boards/franzininho/esp32s2_franzininho/doc/index.rst b/boards/franzininho/esp32s2_franzininho/doc/index.rst new file mode 100644 index 00000000000..de0b2c8b1b7 --- /dev/null +++ b/boards/franzininho/esp32s2_franzininho/doc/index.rst @@ -0,0 +1,174 @@ +.. _esp32s2_franzininho: + +ESP32-S2 Franzininho +#################### + +Overview +******** + +Franzininho is an educational development board based on ESP32-S2 which is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, +designed to be secure and cost-effective, with a high performance and a rich set of IO capabilities. [1]_ + +The features include the following: + +- RSA-3072-based secure boot +- AES-XTS-256-based flash encryption +- Protected private key and device secrets from software access +- Cryptographic accelerators for enhanced performance +- Protection against physical fault injection attacks +- Various peripherals: + + - 43x programmable GPIOs + - 14x configurable capacitive touch GPIOs + - USB OTG + - LCD interface + - camera interface + - SPI + - I2S + - UART + - ADC + - DAC + - LED PWM with up to 8 channels + +.. figure:: img/esp32_s2_franzininho.jpg + :align: center + :alt: ESP32-S2 FRANZININHO + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32s2_franzininho + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_franzininho + :goals: build + +The usual ``flash`` target will work with the ``esp32s2_franzininho`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_franzininho + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s2_franzininho + +References +********** + +.. [1] https://www.espressif.com/en/products/socs/esp32-s2 +.. _`ESP32S2 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf +.. _`ESP32S2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho-pinctrl.dtsi b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32s2_franzininho/esp32s2_franzininho-pinctrl.dtsi rename to boards/franzininho/esp32s2_franzininho/esp32s2_franzininho-pinctrl.dtsi diff --git a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.dts b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts similarity index 98% rename from boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.dts rename to boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts index 2ce35ee5534..d8a6f1c7070 100644 --- a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.dts +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts @@ -10,7 +10,7 @@ #include "esp32s2_franzininho-pinctrl.dtsi" / { - model = "esp32s2_franzininho"; + model = "ESP32S2 Franzininho"; compatible = "espressif,esp32s2"; aliases { diff --git a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.yaml b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml similarity index 92% rename from boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.yaml rename to boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml index 9cc2a260342..0a227dc6021 100644 --- a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.yaml +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml @@ -16,4 +16,4 @@ testing: - heap - net - bluetooth -vendor: espressif +vendor: franzininho diff --git a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig new file mode 100644 index 00000000000..f566acd9340 --- /dev/null +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + + + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_lolin_mini/support/openocd.cfg b/boards/franzininho/esp32s2_franzininho/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32s2_lolin_mini/support/openocd.cfg rename to boards/franzininho/esp32s2_franzininho/support/openocd.cfg diff --git a/boards/franzininho/index.rst b/boards/franzininho/index.rst new file mode 100644 index 00000000000..e7222d6d4a1 --- /dev/null +++ b/boards/franzininho/index.rst @@ -0,0 +1,10 @@ +.. _boards-franzininho: + +Franzininho +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/gaisler/generic_leon3/Kconfig.defconfig b/boards/gaisler/generic_leon3/Kconfig.defconfig new file mode 100644 index 00000000000..0294060baa5 --- /dev/null +++ b/boards/gaisler/generic_leon3/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_GENERIC_LEON3 + +config SPARC_CASA + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 50000000 + +config UART_INTERRUPT_DRIVEN + default y + +endif diff --git a/boards/gaisler/generic_leon3/Kconfig.generic_leon3 b/boards/gaisler/generic_leon3/Kconfig.generic_leon3 new file mode 100644 index 00000000000..88240708cf0 --- /dev/null +++ b/boards/gaisler/generic_leon3/Kconfig.generic_leon3 @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GENERIC_LEON3 + select SOC_LEON3 diff --git a/boards/sparc/generic_leon3/board.cmake b/boards/gaisler/generic_leon3/board.cmake similarity index 100% rename from boards/sparc/generic_leon3/board.cmake rename to boards/gaisler/generic_leon3/board.cmake diff --git a/boards/gaisler/generic_leon3/board.yml b/boards/gaisler/generic_leon3/board.yml new file mode 100644 index 00000000000..33c4d806add --- /dev/null +++ b/boards/gaisler/generic_leon3/board.yml @@ -0,0 +1,5 @@ +board: + name: generic_leon3 + vendor: gaisler + socs: + - name: leon3 diff --git a/boards/sparc/generic_leon3/doc/index.rst b/boards/gaisler/generic_leon3/doc/index.rst similarity index 100% rename from boards/sparc/generic_leon3/doc/index.rst rename to boards/gaisler/generic_leon3/doc/index.rst diff --git a/boards/sparc/generic_leon3/generic_leon3.dts b/boards/gaisler/generic_leon3/generic_leon3.dts similarity index 100% rename from boards/sparc/generic_leon3/generic_leon3.dts rename to boards/gaisler/generic_leon3/generic_leon3.dts diff --git a/boards/sparc/generic_leon3/generic_leon3.yaml b/boards/gaisler/generic_leon3/generic_leon3.yaml similarity index 100% rename from boards/sparc/generic_leon3/generic_leon3.yaml rename to boards/gaisler/generic_leon3/generic_leon3.yaml diff --git a/boards/gaisler/generic_leon3/generic_leon3_defconfig b/boards/gaisler/generic_leon3/generic_leon3_defconfig new file mode 100644 index 00000000000..d7eb0842fa7 --- /dev/null +++ b/boards/gaisler/generic_leon3/generic_leon3_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_EXTRA_EXCEPTION_INFO=y diff --git a/boards/gaisler/gr716a_mini/Kconfig.defconfig b/boards/gaisler/gr716a_mini/Kconfig.defconfig new file mode 100644 index 00000000000..5617c96a6dd --- /dev/null +++ b/boards/gaisler/gr716a_mini/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_GR716A_MINI + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 20000000 + +config UART_INTERRUPT_DRIVEN + default y + +endif diff --git a/boards/gaisler/gr716a_mini/Kconfig.gr716a_mini b/boards/gaisler/gr716a_mini/Kconfig.gr716a_mini new file mode 100644 index 00000000000..11b033a54d8 --- /dev/null +++ b/boards/gaisler/gr716a_mini/Kconfig.gr716a_mini @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GR716A_MINI + select SOC_GR716A diff --git a/boards/sparc/gr716a_mini/board.cmake b/boards/gaisler/gr716a_mini/board.cmake similarity index 100% rename from boards/sparc/gr716a_mini/board.cmake rename to boards/gaisler/gr716a_mini/board.cmake diff --git a/boards/gaisler/gr716a_mini/board.yml b/boards/gaisler/gr716a_mini/board.yml new file mode 100644 index 00000000000..0de80629b40 --- /dev/null +++ b/boards/gaisler/gr716a_mini/board.yml @@ -0,0 +1,5 @@ +board: + name: gr716a_mini + vendor: gaisler + socs: + - name: gr716a diff --git a/boards/sparc/gr716a_mini/doc/gr716a_mini.jpg b/boards/gaisler/gr716a_mini/doc/gr716a_mini.jpg similarity index 100% rename from boards/sparc/gr716a_mini/doc/gr716a_mini.jpg rename to boards/gaisler/gr716a_mini/doc/gr716a_mini.jpg diff --git a/boards/sparc/gr716a_mini/doc/index.rst b/boards/gaisler/gr716a_mini/doc/index.rst similarity index 100% rename from boards/sparc/gr716a_mini/doc/index.rst rename to boards/gaisler/gr716a_mini/doc/index.rst diff --git a/boards/sparc/gr716a_mini/gr716a_mini.dts b/boards/gaisler/gr716a_mini/gr716a_mini.dts similarity index 100% rename from boards/sparc/gr716a_mini/gr716a_mini.dts rename to boards/gaisler/gr716a_mini/gr716a_mini.dts diff --git a/boards/sparc/gr716a_mini/gr716a_mini.yaml b/boards/gaisler/gr716a_mini/gr716a_mini.yaml similarity index 100% rename from boards/sparc/gr716a_mini/gr716a_mini.yaml rename to boards/gaisler/gr716a_mini/gr716a_mini.yaml diff --git a/boards/gaisler/gr716a_mini/gr716a_mini_defconfig b/boards/gaisler/gr716a_mini/gr716a_mini_defconfig new file mode 100644 index 00000000000..101f819969b --- /dev/null +++ b/boards/gaisler/gr716a_mini/gr716a_mini_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/gaisler/index.rst b/boards/gaisler/index.rst new file mode 100644 index 00000000000..ece74721dcd --- /dev/null +++ b/boards/gaisler/index.rst @@ -0,0 +1,10 @@ +.. _boards-gaisler: + +Gaisler +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/gd/gd32a503v_eval/Kconfig.gd32a503v_eval b/boards/gd/gd32a503v_eval/Kconfig.gd32a503v_eval new file mode 100644 index 00000000000..c1e49432cb6 --- /dev/null +++ b/boards/gd/gd32a503v_eval/Kconfig.gd32a503v_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32A503V_EVAL + select SOC_GD32A503 diff --git a/boards/arm/gd32a503v_eval/board.cmake b/boards/gd/gd32a503v_eval/board.cmake similarity index 100% rename from boards/arm/gd32a503v_eval/board.cmake rename to boards/gd/gd32a503v_eval/board.cmake diff --git a/boards/gd/gd32a503v_eval/board.yml b/boards/gd/gd32a503v_eval/board.yml new file mode 100644 index 00000000000..129cf4b0b50 --- /dev/null +++ b/boards/gd/gd32a503v_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32a503v_eval + vendor: gd + socs: + - name: gd32a503 diff --git a/boards/arm/gd32a503v_eval/doc/img/gd32a503v_eval.jpg b/boards/gd/gd32a503v_eval/doc/img/gd32a503v_eval.jpg similarity index 100% rename from boards/arm/gd32a503v_eval/doc/img/gd32a503v_eval.jpg rename to boards/gd/gd32a503v_eval/doc/img/gd32a503v_eval.jpg diff --git a/boards/arm/gd32a503v_eval/doc/index.rst b/boards/gd/gd32a503v_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32a503v_eval/doc/index.rst rename to boards/gd/gd32a503v_eval/doc/index.rst diff --git a/boards/arm/gd32a503v_eval/gd32a503v_eval-pinctrl.dtsi b/boards/gd/gd32a503v_eval/gd32a503v_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32a503v_eval/gd32a503v_eval-pinctrl.dtsi rename to boards/gd/gd32a503v_eval/gd32a503v_eval-pinctrl.dtsi diff --git a/boards/arm/gd32a503v_eval/gd32a503v_eval.dts b/boards/gd/gd32a503v_eval/gd32a503v_eval.dts similarity index 100% rename from boards/arm/gd32a503v_eval/gd32a503v_eval.dts rename to boards/gd/gd32a503v_eval/gd32a503v_eval.dts diff --git a/boards/arm/gd32a503v_eval/gd32a503v_eval.yaml b/boards/gd/gd32a503v_eval/gd32a503v_eval.yaml similarity index 100% rename from boards/arm/gd32a503v_eval/gd32a503v_eval.yaml rename to boards/gd/gd32a503v_eval/gd32a503v_eval.yaml diff --git a/boards/gd/gd32a503v_eval/gd32a503v_eval_defconfig b/boards/gd/gd32a503v_eval/gd32a503v_eval_defconfig new file mode 100644 index 00000000000..5d4c4159b6c --- /dev/null +++ b/boards/gd/gd32a503v_eval/gd32a503v_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/gd/gd32e103v_eval/Kconfig.gd32e103v_eval b/boards/gd/gd32e103v_eval/Kconfig.gd32e103v_eval new file mode 100644 index 00000000000..f4fb38d69e5 --- /dev/null +++ b/boards/gd/gd32e103v_eval/Kconfig.gd32e103v_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32E103V_EVAL + select SOC_GD32E103 diff --git a/boards/arm/gd32e103v_eval/board.cmake b/boards/gd/gd32e103v_eval/board.cmake similarity index 100% rename from boards/arm/gd32e103v_eval/board.cmake rename to boards/gd/gd32e103v_eval/board.cmake diff --git a/boards/gd/gd32e103v_eval/board.yml b/boards/gd/gd32e103v_eval/board.yml new file mode 100644 index 00000000000..1c489697783 --- /dev/null +++ b/boards/gd/gd32e103v_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32e103v_eval + vendor: gd + socs: + - name: gd32e103 diff --git a/boards/arm/gd32e103v_eval/doc/img/gd32e103v_eval.jpg b/boards/gd/gd32e103v_eval/doc/img/gd32e103v_eval.jpg similarity index 100% rename from boards/arm/gd32e103v_eval/doc/img/gd32e103v_eval.jpg rename to boards/gd/gd32e103v_eval/doc/img/gd32e103v_eval.jpg diff --git a/boards/arm/gd32e103v_eval/doc/index.rst b/boards/gd/gd32e103v_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32e103v_eval/doc/index.rst rename to boards/gd/gd32e103v_eval/doc/index.rst diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval-pinctrl.dtsi b/boards/gd/gd32e103v_eval/gd32e103v_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32e103v_eval/gd32e103v_eval-pinctrl.dtsi rename to boards/gd/gd32e103v_eval/gd32e103v_eval-pinctrl.dtsi diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval.dts b/boards/gd/gd32e103v_eval/gd32e103v_eval.dts similarity index 100% rename from boards/arm/gd32e103v_eval/gd32e103v_eval.dts rename to boards/gd/gd32e103v_eval/gd32e103v_eval.dts diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval.yaml b/boards/gd/gd32e103v_eval/gd32e103v_eval.yaml similarity index 100% rename from boards/arm/gd32e103v_eval/gd32e103v_eval.yaml rename to boards/gd/gd32e103v_eval/gd32e103v_eval.yaml diff --git a/boards/gd/gd32e103v_eval/gd32e103v_eval_defconfig b/boards/gd/gd32e103v_eval/gd32e103v_eval_defconfig new file mode 100644 index 00000000000..35ac235333c --- /dev/null +++ b/boards/gd/gd32e103v_eval/gd32e103v_eval_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021, YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GD32_HXTAL_8MHZ=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/gd32e103v_eval/support/openocd.cfg b/boards/gd/gd32e103v_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32e103v_eval/support/openocd.cfg rename to boards/gd/gd32e103v_eval/support/openocd.cfg diff --git a/boards/gd/gd32e507v_start/Kconfig.gd32e507v_start b/boards/gd/gd32e507v_start/Kconfig.gd32e507v_start new file mode 100644 index 00000000000..be09310ad58 --- /dev/null +++ b/boards/gd/gd32e507v_start/Kconfig.gd32e507v_start @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32E507V_START + select SOC_GD32E507 diff --git a/boards/arm/gd32e507v_start/board.cmake b/boards/gd/gd32e507v_start/board.cmake similarity index 100% rename from boards/arm/gd32e507v_start/board.cmake rename to boards/gd/gd32e507v_start/board.cmake diff --git a/boards/gd/gd32e507v_start/board.yml b/boards/gd/gd32e507v_start/board.yml new file mode 100644 index 00000000000..b364620f61a --- /dev/null +++ b/boards/gd/gd32e507v_start/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32e507v_start + vendor: gd + socs: + - name: gd32e507 diff --git a/boards/arm/gd32e507v_start/doc/img/gd32e507v_start.jpg b/boards/gd/gd32e507v_start/doc/img/gd32e507v_start.jpg similarity index 100% rename from boards/arm/gd32e507v_start/doc/img/gd32e507v_start.jpg rename to boards/gd/gd32e507v_start/doc/img/gd32e507v_start.jpg diff --git a/boards/arm/gd32e507v_start/doc/index.rst b/boards/gd/gd32e507v_start/doc/index.rst similarity index 100% rename from boards/arm/gd32e507v_start/doc/index.rst rename to boards/gd/gd32e507v_start/doc/index.rst diff --git a/boards/arm/gd32e507v_start/gd32e507v_start-pinctrl.dtsi b/boards/gd/gd32e507v_start/gd32e507v_start-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32e507v_start/gd32e507v_start-pinctrl.dtsi rename to boards/gd/gd32e507v_start/gd32e507v_start-pinctrl.dtsi diff --git a/boards/arm/gd32e507v_start/gd32e507v_start.dts b/boards/gd/gd32e507v_start/gd32e507v_start.dts similarity index 100% rename from boards/arm/gd32e507v_start/gd32e507v_start.dts rename to boards/gd/gd32e507v_start/gd32e507v_start.dts diff --git a/boards/arm/gd32e507v_start/gd32e507v_start.yaml b/boards/gd/gd32e507v_start/gd32e507v_start.yaml similarity index 100% rename from boards/arm/gd32e507v_start/gd32e507v_start.yaml rename to boards/gd/gd32e507v_start/gd32e507v_start.yaml diff --git a/boards/gd/gd32e507v_start/gd32e507v_start_defconfig b/boards/gd/gd32e507v_start/gd32e507v_start_defconfig new file mode 100644 index 00000000000..51f83a8ccd6 --- /dev/null +++ b/boards/gd/gd32e507v_start/gd32e507v_start_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/gd/gd32e507z_eval/Kconfig.gd32e507z_eval b/boards/gd/gd32e507z_eval/Kconfig.gd32e507z_eval new file mode 100644 index 00000000000..bd40810385c --- /dev/null +++ b/boards/gd/gd32e507z_eval/Kconfig.gd32e507z_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32E507Z_EVAL + select SOC_GD32E507 diff --git a/boards/arm/gd32e507z_eval/board.cmake b/boards/gd/gd32e507z_eval/board.cmake similarity index 100% rename from boards/arm/gd32e507z_eval/board.cmake rename to boards/gd/gd32e507z_eval/board.cmake diff --git a/boards/gd/gd32e507z_eval/board.yml b/boards/gd/gd32e507z_eval/board.yml new file mode 100644 index 00000000000..2325550db5d --- /dev/null +++ b/boards/gd/gd32e507z_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32e507z_eval + vendor: gd + socs: + - name: gd32e507 diff --git a/boards/arm/gd32e507z_eval/doc/img/gd32e507z_eval.webp b/boards/gd/gd32e507z_eval/doc/img/gd32e507z_eval.webp similarity index 100% rename from boards/arm/gd32e507z_eval/doc/img/gd32e507z_eval.webp rename to boards/gd/gd32e507z_eval/doc/img/gd32e507z_eval.webp diff --git a/boards/arm/gd32e507z_eval/doc/index.rst b/boards/gd/gd32e507z_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32e507z_eval/doc/index.rst rename to boards/gd/gd32e507z_eval/doc/index.rst diff --git a/boards/arm/gd32e507z_eval/gd32e507z_eval-pinctrl.dtsi b/boards/gd/gd32e507z_eval/gd32e507z_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32e507z_eval/gd32e507z_eval-pinctrl.dtsi rename to boards/gd/gd32e507z_eval/gd32e507z_eval-pinctrl.dtsi diff --git a/boards/arm/gd32e507z_eval/gd32e507z_eval.dts b/boards/gd/gd32e507z_eval/gd32e507z_eval.dts similarity index 100% rename from boards/arm/gd32e507z_eval/gd32e507z_eval.dts rename to boards/gd/gd32e507z_eval/gd32e507z_eval.dts diff --git a/boards/arm/gd32e507z_eval/gd32e507z_eval.yaml b/boards/gd/gd32e507z_eval/gd32e507z_eval.yaml similarity index 100% rename from boards/arm/gd32e507z_eval/gd32e507z_eval.yaml rename to boards/gd/gd32e507z_eval/gd32e507z_eval.yaml diff --git a/boards/gd/gd32e507z_eval/gd32e507z_eval_defconfig b/boards/gd/gd32e507z_eval/gd32e507z_eval_defconfig new file mode 100644 index 00000000000..51f83a8ccd6 --- /dev/null +++ b/boards/gd/gd32e507z_eval/gd32e507z_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/gd/gd32f350r_eval/Kconfig.gd32f350r_eval b/boards/gd/gd32f350r_eval/Kconfig.gd32f350r_eval new file mode 100644 index 00000000000..ae610061d8d --- /dev/null +++ b/boards/gd/gd32f350r_eval/Kconfig.gd32f350r_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F350R_EVAL + select SOC_GD32F350 diff --git a/boards/arm/gd32f350r_eval/board.cmake b/boards/gd/gd32f350r_eval/board.cmake similarity index 100% rename from boards/arm/gd32f350r_eval/board.cmake rename to boards/gd/gd32f350r_eval/board.cmake diff --git a/boards/gd/gd32f350r_eval/board.yml b/boards/gd/gd32f350r_eval/board.yml new file mode 100644 index 00000000000..ee486b17983 --- /dev/null +++ b/boards/gd/gd32f350r_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f350r_eval + vendor: gd + socs: + - name: gd32f350 diff --git a/boards/arm/gd32f350r_eval/doc/img/gd32f350r_eval.webp b/boards/gd/gd32f350r_eval/doc/img/gd32f350r_eval.webp similarity index 100% rename from boards/arm/gd32f350r_eval/doc/img/gd32f350r_eval.webp rename to boards/gd/gd32f350r_eval/doc/img/gd32f350r_eval.webp diff --git a/boards/arm/gd32f350r_eval/doc/index.rst b/boards/gd/gd32f350r_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32f350r_eval/doc/index.rst rename to boards/gd/gd32f350r_eval/doc/index.rst diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi b/boards/gd/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi rename to boards/gd/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval.dts b/boards/gd/gd32f350r_eval/gd32f350r_eval.dts similarity index 100% rename from boards/arm/gd32f350r_eval/gd32f350r_eval.dts rename to boards/gd/gd32f350r_eval/gd32f350r_eval.dts diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval.yaml b/boards/gd/gd32f350r_eval/gd32f350r_eval.yaml similarity index 100% rename from boards/arm/gd32f350r_eval/gd32f350r_eval.yaml rename to boards/gd/gd32f350r_eval/gd32f350r_eval.yaml diff --git a/boards/gd/gd32f350r_eval/gd32f350r_eval_defconfig b/boards/gd/gd32f350r_eval/gd32f350r_eval_defconfig new file mode 100644 index 00000000000..6df7f7edc24 --- /dev/null +++ b/boards/gd/gd32f350r_eval/gd32f350r_eval_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/gd32f350r_eval/support/openocd.cfg b/boards/gd/gd32f350r_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f350r_eval/support/openocd.cfg rename to boards/gd/gd32f350r_eval/support/openocd.cfg diff --git a/boards/gd/gd32f403z_eval/Kconfig.gd32f403z_eval b/boards/gd/gd32f403z_eval/Kconfig.gd32f403z_eval new file mode 100644 index 00000000000..e9fa7237053 --- /dev/null +++ b/boards/gd/gd32f403z_eval/Kconfig.gd32f403z_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F403Z_EVAL + select SOC_GD32F403 diff --git a/boards/arm/gd32f403z_eval/board.cmake b/boards/gd/gd32f403z_eval/board.cmake similarity index 100% rename from boards/arm/gd32f403z_eval/board.cmake rename to boards/gd/gd32f403z_eval/board.cmake diff --git a/boards/gd/gd32f403z_eval/board.yml b/boards/gd/gd32f403z_eval/board.yml new file mode 100644 index 00000000000..222ba863858 --- /dev/null +++ b/boards/gd/gd32f403z_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f403z_eval + vendor: gd + socs: + - name: gd32f403 diff --git a/boards/arm/gd32f403z_eval/doc/img/gd32f403z_eval.jpg b/boards/gd/gd32f403z_eval/doc/img/gd32f403z_eval.jpg similarity index 100% rename from boards/arm/gd32f403z_eval/doc/img/gd32f403z_eval.jpg rename to boards/gd/gd32f403z_eval/doc/img/gd32f403z_eval.jpg diff --git a/boards/arm/gd32f403z_eval/doc/index.rst b/boards/gd/gd32f403z_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32f403z_eval/doc/index.rst rename to boards/gd/gd32f403z_eval/doc/index.rst diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval-pinctrl.dtsi b/boards/gd/gd32f403z_eval/gd32f403z_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f403z_eval/gd32f403z_eval-pinctrl.dtsi rename to boards/gd/gd32f403z_eval/gd32f403z_eval-pinctrl.dtsi diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval.dts b/boards/gd/gd32f403z_eval/gd32f403z_eval.dts similarity index 100% rename from boards/arm/gd32f403z_eval/gd32f403z_eval.dts rename to boards/gd/gd32f403z_eval/gd32f403z_eval.dts diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval.yaml b/boards/gd/gd32f403z_eval/gd32f403z_eval.yaml similarity index 100% rename from boards/arm/gd32f403z_eval/gd32f403z_eval.yaml rename to boards/gd/gd32f403z_eval/gd32f403z_eval.yaml diff --git a/boards/gd/gd32f403z_eval/gd32f403z_eval_defconfig b/boards/gd/gd32f403z_eval/gd32f403z_eval_defconfig new file mode 100644 index 00000000000..1c7051a83fb --- /dev/null +++ b/boards/gd/gd32f403z_eval/gd32f403z_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/arm/gd32f403z_eval/support/openocd.cfg b/boards/gd/gd32f403z_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f403z_eval/support/openocd.cfg rename to boards/gd/gd32f403z_eval/support/openocd.cfg diff --git a/boards/gd/gd32f407v_start/Kconfig.gd32f407v_start b/boards/gd/gd32f407v_start/Kconfig.gd32f407v_start new file mode 100644 index 00000000000..6624205d86b --- /dev/null +++ b/boards/gd/gd32f407v_start/Kconfig.gd32f407v_start @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F407V_START + select SOC_GD32F407 diff --git a/boards/arm/gd32f407v_start/board.cmake b/boards/gd/gd32f407v_start/board.cmake similarity index 100% rename from boards/arm/gd32f407v_start/board.cmake rename to boards/gd/gd32f407v_start/board.cmake diff --git a/boards/gd/gd32f407v_start/board.yml b/boards/gd/gd32f407v_start/board.yml new file mode 100644 index 00000000000..c4a99ab566e --- /dev/null +++ b/boards/gd/gd32f407v_start/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f407v_start + vendor: gd + socs: + - name: gd32f407 diff --git a/boards/arm/gd32f407v_start/doc/img/gd32f407v_start.webp b/boards/gd/gd32f407v_start/doc/img/gd32f407v_start.webp similarity index 100% rename from boards/arm/gd32f407v_start/doc/img/gd32f407v_start.webp rename to boards/gd/gd32f407v_start/doc/img/gd32f407v_start.webp diff --git a/boards/arm/gd32f407v_start/doc/index.rst b/boards/gd/gd32f407v_start/doc/index.rst similarity index 100% rename from boards/arm/gd32f407v_start/doc/index.rst rename to boards/gd/gd32f407v_start/doc/index.rst diff --git a/boards/arm/gd32f407v_start/gd32f407v_start-pinctrl.dtsi b/boards/gd/gd32f407v_start/gd32f407v_start-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f407v_start/gd32f407v_start-pinctrl.dtsi rename to boards/gd/gd32f407v_start/gd32f407v_start-pinctrl.dtsi diff --git a/boards/arm/gd32f407v_start/gd32f407v_start.dts b/boards/gd/gd32f407v_start/gd32f407v_start.dts similarity index 100% rename from boards/arm/gd32f407v_start/gd32f407v_start.dts rename to boards/gd/gd32f407v_start/gd32f407v_start.dts diff --git a/boards/arm/gd32f407v_start/gd32f407v_start.yaml b/boards/gd/gd32f407v_start/gd32f407v_start.yaml similarity index 100% rename from boards/arm/gd32f407v_start/gd32f407v_start.yaml rename to boards/gd/gd32f407v_start/gd32f407v_start.yaml diff --git a/boards/gd/gd32f407v_start/gd32f407v_start_defconfig b/boards/gd/gd32f407v_start/gd32f407v_start_defconfig new file mode 100644 index 00000000000..b037de8dd84 --- /dev/null +++ b/boards/gd/gd32f407v_start/gd32f407v_start_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/gd/gd32f450i_eval/Kconfig.gd32f450i_eval b/boards/gd/gd32f450i_eval/Kconfig.gd32f450i_eval new file mode 100644 index 00000000000..04574e6b6df --- /dev/null +++ b/boards/gd/gd32f450i_eval/Kconfig.gd32f450i_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F450I_EVAL + select SOC_GD32F450 diff --git a/boards/arm/gd32f450i_eval/board.cmake b/boards/gd/gd32f450i_eval/board.cmake similarity index 100% rename from boards/arm/gd32f450i_eval/board.cmake rename to boards/gd/gd32f450i_eval/board.cmake diff --git a/boards/gd/gd32f450i_eval/board.yml b/boards/gd/gd32f450i_eval/board.yml new file mode 100644 index 00000000000..a5da3b33c36 --- /dev/null +++ b/boards/gd/gd32f450i_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f450i_eval + vendor: gd + socs: + - name: gd32f450 diff --git a/boards/arm/gd32f450i_eval/doc/img/gd32f450i_eval.webp b/boards/gd/gd32f450i_eval/doc/img/gd32f450i_eval.webp similarity index 100% rename from boards/arm/gd32f450i_eval/doc/img/gd32f450i_eval.webp rename to boards/gd/gd32f450i_eval/doc/img/gd32f450i_eval.webp diff --git a/boards/arm/gd32f450i_eval/doc/index.rst b/boards/gd/gd32f450i_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32f450i_eval/doc/index.rst rename to boards/gd/gd32f450i_eval/doc/index.rst diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval-pinctrl.dtsi b/boards/gd/gd32f450i_eval/gd32f450i_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f450i_eval/gd32f450i_eval-pinctrl.dtsi rename to boards/gd/gd32f450i_eval/gd32f450i_eval-pinctrl.dtsi diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval.dts b/boards/gd/gd32f450i_eval/gd32f450i_eval.dts similarity index 100% rename from boards/arm/gd32f450i_eval/gd32f450i_eval.dts rename to boards/gd/gd32f450i_eval/gd32f450i_eval.dts diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval.yaml b/boards/gd/gd32f450i_eval/gd32f450i_eval.yaml similarity index 100% rename from boards/arm/gd32f450i_eval/gd32f450i_eval.yaml rename to boards/gd/gd32f450i_eval/gd32f450i_eval.yaml diff --git a/boards/gd/gd32f450i_eval/gd32f450i_eval_defconfig b/boards/gd/gd32f450i_eval/gd32f450i_eval_defconfig new file mode 100644 index 00000000000..07ba35284c3 --- /dev/null +++ b/boards/gd/gd32f450i_eval/gd32f450i_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/arm/gd32f450i_eval/support/openocd.cfg b/boards/gd/gd32f450i_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f450i_eval/support/openocd.cfg rename to boards/gd/gd32f450i_eval/support/openocd.cfg diff --git a/boards/gd/gd32f450v_start/Kconfig.gd32f450v_start b/boards/gd/gd32f450v_start/Kconfig.gd32f450v_start new file mode 100644 index 00000000000..a666d791265 --- /dev/null +++ b/boards/gd/gd32f450v_start/Kconfig.gd32f450v_start @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F450V_START + select SOC_GD32F450 diff --git a/boards/arm/gd32f450v_start/board.cmake b/boards/gd/gd32f450v_start/board.cmake similarity index 100% rename from boards/arm/gd32f450v_start/board.cmake rename to boards/gd/gd32f450v_start/board.cmake diff --git a/boards/gd/gd32f450v_start/board.yml b/boards/gd/gd32f450v_start/board.yml new file mode 100644 index 00000000000..96e00536946 --- /dev/null +++ b/boards/gd/gd32f450v_start/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f450v_start + vendor: gd + socs: + - name: gd32f450 diff --git a/boards/arm/gd32f450v_start/doc/img/gd32f450v_start.webp b/boards/gd/gd32f450v_start/doc/img/gd32f450v_start.webp similarity index 100% rename from boards/arm/gd32f450v_start/doc/img/gd32f450v_start.webp rename to boards/gd/gd32f450v_start/doc/img/gd32f450v_start.webp diff --git a/boards/arm/gd32f450v_start/doc/index.rst b/boards/gd/gd32f450v_start/doc/index.rst similarity index 100% rename from boards/arm/gd32f450v_start/doc/index.rst rename to boards/gd/gd32f450v_start/doc/index.rst diff --git a/boards/arm/gd32f450v_start/gd32f450v_start-pinctrl.dtsi b/boards/gd/gd32f450v_start/gd32f450v_start-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f450v_start/gd32f450v_start-pinctrl.dtsi rename to boards/gd/gd32f450v_start/gd32f450v_start-pinctrl.dtsi diff --git a/boards/arm/gd32f450v_start/gd32f450v_start.dts b/boards/gd/gd32f450v_start/gd32f450v_start.dts similarity index 100% rename from boards/arm/gd32f450v_start/gd32f450v_start.dts rename to boards/gd/gd32f450v_start/gd32f450v_start.dts diff --git a/boards/arm/gd32f450v_start/gd32f450v_start.yaml b/boards/gd/gd32f450v_start/gd32f450v_start.yaml similarity index 100% rename from boards/arm/gd32f450v_start/gd32f450v_start.yaml rename to boards/gd/gd32f450v_start/gd32f450v_start.yaml diff --git a/boards/gd/gd32f450v_start/gd32f450v_start_defconfig b/boards/gd/gd32f450v_start/gd32f450v_start_defconfig new file mode 100644 index 00000000000..51f83a8ccd6 --- /dev/null +++ b/boards/gd/gd32f450v_start/gd32f450v_start_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/arm/gd32f450v_start/support/openocd.cfg b/boards/gd/gd32f450v_start/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f450v_start/support/openocd.cfg rename to boards/gd/gd32f450v_start/support/openocd.cfg diff --git a/boards/gd/gd32f450z_eval/Kconfig.gd32f450z_eval b/boards/gd/gd32f450z_eval/Kconfig.gd32f450z_eval new file mode 100644 index 00000000000..3126837aaa2 --- /dev/null +++ b/boards/gd/gd32f450z_eval/Kconfig.gd32f450z_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F450Z_EVAL + select SOC_GD32F450 diff --git a/boards/arm/gd32f450z_eval/board.cmake b/boards/gd/gd32f450z_eval/board.cmake similarity index 100% rename from boards/arm/gd32f450z_eval/board.cmake rename to boards/gd/gd32f450z_eval/board.cmake diff --git a/boards/gd/gd32f450z_eval/board.yml b/boards/gd/gd32f450z_eval/board.yml new file mode 100644 index 00000000000..53e30794b6a --- /dev/null +++ b/boards/gd/gd32f450z_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f450z_eval + vendor: gd + socs: + - name: gd32f450 diff --git a/boards/arm/gd32f450z_eval/doc/img/gd32f450z_eval.webp b/boards/gd/gd32f450z_eval/doc/img/gd32f450z_eval.webp similarity index 100% rename from boards/arm/gd32f450z_eval/doc/img/gd32f450z_eval.webp rename to boards/gd/gd32f450z_eval/doc/img/gd32f450z_eval.webp diff --git a/boards/arm/gd32f450z_eval/doc/index.rst b/boards/gd/gd32f450z_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32f450z_eval/doc/index.rst rename to boards/gd/gd32f450z_eval/doc/index.rst diff --git a/boards/arm/gd32f450z_eval/gd32f450z_eval-pinctrl.dtsi b/boards/gd/gd32f450z_eval/gd32f450z_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f450z_eval/gd32f450z_eval-pinctrl.dtsi rename to boards/gd/gd32f450z_eval/gd32f450z_eval-pinctrl.dtsi diff --git a/boards/arm/gd32f450z_eval/gd32f450z_eval.dts b/boards/gd/gd32f450z_eval/gd32f450z_eval.dts similarity index 100% rename from boards/arm/gd32f450z_eval/gd32f450z_eval.dts rename to boards/gd/gd32f450z_eval/gd32f450z_eval.dts diff --git a/boards/arm/gd32f450z_eval/gd32f450z_eval.yaml b/boards/gd/gd32f450z_eval/gd32f450z_eval.yaml similarity index 100% rename from boards/arm/gd32f450z_eval/gd32f450z_eval.yaml rename to boards/gd/gd32f450z_eval/gd32f450z_eval.yaml diff --git a/boards/gd/gd32f450z_eval/gd32f450z_eval_defconfig b/boards/gd/gd32f450z_eval/gd32f450z_eval_defconfig new file mode 100644 index 00000000000..4b47334704d --- /dev/null +++ b/boards/gd/gd32f450z_eval/gd32f450z_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Rtone. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/arm/gd32f450z_eval/support/openocd.cfg b/boards/gd/gd32f450z_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f450z_eval/support/openocd.cfg rename to boards/gd/gd32f450z_eval/support/openocd.cfg diff --git a/boards/gd/gd32f470i_eval/Kconfig.gd32f470i_eval b/boards/gd/gd32f470i_eval/Kconfig.gd32f470i_eval new file mode 100644 index 00000000000..09ef416cb79 --- /dev/null +++ b/boards/gd/gd32f470i_eval/Kconfig.gd32f470i_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F470I_EVAL + select SOC_GD32F470 diff --git a/boards/arm/gd32f470i_eval/board.cmake b/boards/gd/gd32f470i_eval/board.cmake similarity index 100% rename from boards/arm/gd32f470i_eval/board.cmake rename to boards/gd/gd32f470i_eval/board.cmake diff --git a/boards/gd/gd32f470i_eval/board.yml b/boards/gd/gd32f470i_eval/board.yml new file mode 100644 index 00000000000..a4205dc69d2 --- /dev/null +++ b/boards/gd/gd32f470i_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f470i_eval + vendor: gd + socs: + - name: gd32f470 diff --git a/boards/arm/gd32f470i_eval/doc/img/gd32f470i_eval.jpg b/boards/gd/gd32f470i_eval/doc/img/gd32f470i_eval.jpg similarity index 100% rename from boards/arm/gd32f470i_eval/doc/img/gd32f470i_eval.jpg rename to boards/gd/gd32f470i_eval/doc/img/gd32f470i_eval.jpg diff --git a/boards/arm/gd32f470i_eval/doc/index.rst b/boards/gd/gd32f470i_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32f470i_eval/doc/index.rst rename to boards/gd/gd32f470i_eval/doc/index.rst diff --git a/boards/arm/gd32f470i_eval/gd32f470i_eval-pinctrl.dtsi b/boards/gd/gd32f470i_eval/gd32f470i_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f470i_eval/gd32f470i_eval-pinctrl.dtsi rename to boards/gd/gd32f470i_eval/gd32f470i_eval-pinctrl.dtsi diff --git a/boards/arm/gd32f470i_eval/gd32f470i_eval.dts b/boards/gd/gd32f470i_eval/gd32f470i_eval.dts similarity index 100% rename from boards/arm/gd32f470i_eval/gd32f470i_eval.dts rename to boards/gd/gd32f470i_eval/gd32f470i_eval.dts diff --git a/boards/arm/gd32f470i_eval/gd32f470i_eval.yaml b/boards/gd/gd32f470i_eval/gd32f470i_eval.yaml similarity index 100% rename from boards/arm/gd32f470i_eval/gd32f470i_eval.yaml rename to boards/gd/gd32f470i_eval/gd32f470i_eval.yaml diff --git a/boards/gd/gd32f470i_eval/gd32f470i_eval_defconfig b/boards/gd/gd32f470i_eval/gd32f470i_eval_defconfig new file mode 100644 index 00000000000..4b47334704d --- /dev/null +++ b/boards/gd/gd32f470i_eval/gd32f470i_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Rtone. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/arm/gd32f470i_eval/support/openocd.cfg b/boards/gd/gd32f470i_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f470i_eval/support/openocd.cfg rename to boards/gd/gd32f470i_eval/support/openocd.cfg diff --git a/boards/gd/gd32l233r_eval/Kconfig.gd32l233r_eval b/boards/gd/gd32l233r_eval/Kconfig.gd32l233r_eval new file mode 100644 index 00000000000..ee489163d9a --- /dev/null +++ b/boards/gd/gd32l233r_eval/Kconfig.gd32l233r_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32L233R_EVAL + select SOC_GD32L233 diff --git a/boards/arm/gd32l233r_eval/board.cmake b/boards/gd/gd32l233r_eval/board.cmake similarity index 100% rename from boards/arm/gd32l233r_eval/board.cmake rename to boards/gd/gd32l233r_eval/board.cmake diff --git a/boards/gd/gd32l233r_eval/board.yml b/boards/gd/gd32l233r_eval/board.yml new file mode 100644 index 00000000000..847def4fe2c --- /dev/null +++ b/boards/gd/gd32l233r_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32l233r_eval + vendor: gd + socs: + - name: gd32l233 diff --git a/boards/arm/gd32l233r_eval/doc/img/gd32l233r_eval.jpg b/boards/gd/gd32l233r_eval/doc/img/gd32l233r_eval.jpg similarity index 100% rename from boards/arm/gd32l233r_eval/doc/img/gd32l233r_eval.jpg rename to boards/gd/gd32l233r_eval/doc/img/gd32l233r_eval.jpg diff --git a/boards/arm/gd32l233r_eval/doc/index.rst b/boards/gd/gd32l233r_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32l233r_eval/doc/index.rst rename to boards/gd/gd32l233r_eval/doc/index.rst diff --git a/boards/arm/gd32l233r_eval/gd32l233r_eval-pinctrl.dtsi b/boards/gd/gd32l233r_eval/gd32l233r_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32l233r_eval/gd32l233r_eval-pinctrl.dtsi rename to boards/gd/gd32l233r_eval/gd32l233r_eval-pinctrl.dtsi diff --git a/boards/arm/gd32l233r_eval/gd32l233r_eval.dts b/boards/gd/gd32l233r_eval/gd32l233r_eval.dts similarity index 100% rename from boards/arm/gd32l233r_eval/gd32l233r_eval.dts rename to boards/gd/gd32l233r_eval/gd32l233r_eval.dts diff --git a/boards/arm/gd32l233r_eval/gd32l233r_eval.yaml b/boards/gd/gd32l233r_eval/gd32l233r_eval.yaml similarity index 100% rename from boards/arm/gd32l233r_eval/gd32l233r_eval.yaml rename to boards/gd/gd32l233r_eval/gd32l233r_eval.yaml diff --git a/boards/gd/gd32l233r_eval/gd32l233r_eval_defconfig b/boards/gd/gd32l233r_eval/gd32l233r_eval_defconfig new file mode 100644 index 00000000000..32b8efcc716 --- /dev/null +++ b/boards/gd/gd32l233r_eval/gd32l233r_eval_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2022 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/gd/gd32vf103c_starter/Kconfig.gd32vf103c_starter b/boards/gd/gd32vf103c_starter/Kconfig.gd32vf103c_starter new file mode 100644 index 00000000000..2671a8a98dd --- /dev/null +++ b/boards/gd/gd32vf103c_starter/Kconfig.gd32vf103c_starter @@ -0,0 +1,5 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32VF103C_STARTER + select SOC_GD32VF103 diff --git a/boards/riscv/gd32vf103c_starter/board.cmake b/boards/gd/gd32vf103c_starter/board.cmake similarity index 100% rename from boards/riscv/gd32vf103c_starter/board.cmake rename to boards/gd/gd32vf103c_starter/board.cmake diff --git a/boards/gd/gd32vf103c_starter/board.yml b/boards/gd/gd32vf103c_starter/board.yml new file mode 100644 index 00000000000..e91c7178af8 --- /dev/null +++ b/boards/gd/gd32vf103c_starter/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32vf103c_starter + vendor: gd + socs: + - name: gd32vf103 diff --git a/boards/riscv/gd32vf103c_starter/doc/img/gd32vf103c_starter.jpg b/boards/gd/gd32vf103c_starter/doc/img/gd32vf103c_starter.jpg similarity index 100% rename from boards/riscv/gd32vf103c_starter/doc/img/gd32vf103c_starter.jpg rename to boards/gd/gd32vf103c_starter/doc/img/gd32vf103c_starter.jpg diff --git a/boards/riscv/gd32vf103c_starter/doc/index.rst b/boards/gd/gd32vf103c_starter/doc/index.rst similarity index 100% rename from boards/riscv/gd32vf103c_starter/doc/index.rst rename to boards/gd/gd32vf103c_starter/doc/index.rst diff --git a/boards/riscv/gd32vf103c_starter/gd32vf103c_starter-pinctrl.dtsi b/boards/gd/gd32vf103c_starter/gd32vf103c_starter-pinctrl.dtsi similarity index 100% rename from boards/riscv/gd32vf103c_starter/gd32vf103c_starter-pinctrl.dtsi rename to boards/gd/gd32vf103c_starter/gd32vf103c_starter-pinctrl.dtsi diff --git a/boards/riscv/gd32vf103c_starter/gd32vf103c_starter.dts b/boards/gd/gd32vf103c_starter/gd32vf103c_starter.dts similarity index 100% rename from boards/riscv/gd32vf103c_starter/gd32vf103c_starter.dts rename to boards/gd/gd32vf103c_starter/gd32vf103c_starter.dts diff --git a/boards/riscv/gd32vf103c_starter/gd32vf103c_starter.yaml b/boards/gd/gd32vf103c_starter/gd32vf103c_starter.yaml similarity index 100% rename from boards/riscv/gd32vf103c_starter/gd32vf103c_starter.yaml rename to boards/gd/gd32vf103c_starter/gd32vf103c_starter.yaml diff --git a/boards/gd/gd32vf103c_starter/gd32vf103c_starter_defconfig b/boards/gd/gd32vf103c_starter/gd32vf103c_starter_defconfig new file mode 100644 index 00000000000..1a94284e1b7 --- /dev/null +++ b/boards/gd/gd32vf103c_starter/gd32vf103c_starter_defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GD32_HXTAL_8MHZ=y diff --git a/boards/riscv/gd32vf103c_starter/support/openocd.cfg b/boards/gd/gd32vf103c_starter/support/openocd.cfg similarity index 100% rename from boards/riscv/gd32vf103c_starter/support/openocd.cfg rename to boards/gd/gd32vf103c_starter/support/openocd.cfg diff --git a/boards/gd/gd32vf103v_eval/Kconfig.gd32vf103v_eval b/boards/gd/gd32vf103v_eval/Kconfig.gd32vf103v_eval new file mode 100644 index 00000000000..77de39c9612 --- /dev/null +++ b/boards/gd/gd32vf103v_eval/Kconfig.gd32vf103v_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32VF103V_EVAL + select SOC_GD32VF103 diff --git a/boards/riscv/gd32vf103v_eval/board.cmake b/boards/gd/gd32vf103v_eval/board.cmake similarity index 100% rename from boards/riscv/gd32vf103v_eval/board.cmake rename to boards/gd/gd32vf103v_eval/board.cmake diff --git a/boards/gd/gd32vf103v_eval/board.yml b/boards/gd/gd32vf103v_eval/board.yml new file mode 100644 index 00000000000..3d12d916d38 --- /dev/null +++ b/boards/gd/gd32vf103v_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32vf103v_eval + vendor: gd + socs: + - name: gd32vf103 diff --git a/boards/riscv/gd32vf103v_eval/doc/img/gd32vf103v_eval.jpg b/boards/gd/gd32vf103v_eval/doc/img/gd32vf103v_eval.jpg similarity index 100% rename from boards/riscv/gd32vf103v_eval/doc/img/gd32vf103v_eval.jpg rename to boards/gd/gd32vf103v_eval/doc/img/gd32vf103v_eval.jpg diff --git a/boards/riscv/gd32vf103v_eval/doc/index.rst b/boards/gd/gd32vf103v_eval/doc/index.rst similarity index 100% rename from boards/riscv/gd32vf103v_eval/doc/index.rst rename to boards/gd/gd32vf103v_eval/doc/index.rst diff --git a/boards/riscv/gd32vf103v_eval/gd32vf103v_eval-pinctrl.dtsi b/boards/gd/gd32vf103v_eval/gd32vf103v_eval-pinctrl.dtsi similarity index 100% rename from boards/riscv/gd32vf103v_eval/gd32vf103v_eval-pinctrl.dtsi rename to boards/gd/gd32vf103v_eval/gd32vf103v_eval-pinctrl.dtsi diff --git a/boards/riscv/gd32vf103v_eval/gd32vf103v_eval.dts b/boards/gd/gd32vf103v_eval/gd32vf103v_eval.dts similarity index 100% rename from boards/riscv/gd32vf103v_eval/gd32vf103v_eval.dts rename to boards/gd/gd32vf103v_eval/gd32vf103v_eval.dts diff --git a/boards/riscv/gd32vf103v_eval/gd32vf103v_eval.yaml b/boards/gd/gd32vf103v_eval/gd32vf103v_eval.yaml similarity index 100% rename from boards/riscv/gd32vf103v_eval/gd32vf103v_eval.yaml rename to boards/gd/gd32vf103v_eval/gd32vf103v_eval.yaml diff --git a/boards/gd/gd32vf103v_eval/gd32vf103v_eval_defconfig b/boards/gd/gd32vf103v_eval/gd32vf103v_eval_defconfig new file mode 100644 index 00000000000..e34c644b264 --- /dev/null +++ b/boards/gd/gd32vf103v_eval/gd32vf103v_eval_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GD32_HXTAL_8MHZ=y + +CONFIG_GPIO=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/riscv/gd32vf103v_eval/support/openocd.cfg b/boards/gd/gd32vf103v_eval/support/openocd.cfg similarity index 100% rename from boards/riscv/gd32vf103v_eval/support/openocd.cfg rename to boards/gd/gd32vf103v_eval/support/openocd.cfg diff --git a/boards/gd/index.rst b/boards/gd/index.rst new file mode 100644 index 00000000000..79f0a161ca8 --- /dev/null +++ b/boards/gd/index.rst @@ -0,0 +1,10 @@ +.. _boards-gd: + +GigaDevice Semiconductor +######################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/google/dragonclaw/Kconfig.google_dragonclaw b/boards/google/dragonclaw/Kconfig.google_dragonclaw new file mode 100644 index 00000000000..37570bfc0e0 --- /dev/null +++ b/boards/google/dragonclaw/Kconfig.google_dragonclaw @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GOOGLE_DRAGONCLAW + select SOC_STM32F412CX diff --git a/boards/arm/google_dragonclaw/board.cmake b/boards/google/dragonclaw/board.cmake similarity index 100% rename from boards/arm/google_dragonclaw/board.cmake rename to boards/google/dragonclaw/board.cmake diff --git a/boards/google/dragonclaw/board.yml b/boards/google/dragonclaw/board.yml new file mode 100644 index 00000000000..28e8b84ab4f --- /dev/null +++ b/boards/google/dragonclaw/board.yml @@ -0,0 +1,5 @@ +board: + name: google_dragonclaw + vendor: google + socs: + - name: stm32f412zx diff --git a/boards/arm/google_dragonclaw/doc/index.rst b/boards/google/dragonclaw/doc/index.rst similarity index 100% rename from boards/arm/google_dragonclaw/doc/index.rst rename to boards/google/dragonclaw/doc/index.rst diff --git a/boards/arm/google_dragonclaw/google_dragonclaw.dts b/boards/google/dragonclaw/google_dragonclaw.dts similarity index 100% rename from boards/arm/google_dragonclaw/google_dragonclaw.dts rename to boards/google/dragonclaw/google_dragonclaw.dts diff --git a/boards/arm/google_dragonclaw/google_dragonclaw.yaml b/boards/google/dragonclaw/google_dragonclaw.yaml similarity index 100% rename from boards/arm/google_dragonclaw/google_dragonclaw.yaml rename to boards/google/dragonclaw/google_dragonclaw.yaml diff --git a/boards/arm/google_dragonclaw/google_dragonclaw_defconfig b/boards/google/dragonclaw/google_dragonclaw_defconfig similarity index 81% rename from boards/arm/google_dragonclaw/google_dragonclaw_defconfig rename to boards/google/dragonclaw/google_dragonclaw_defconfig index c39f9c6a269..3247707e4e4 100644 --- a/boards/arm/google_dragonclaw/google_dragonclaw_defconfig +++ b/boards/google/dragonclaw/google_dragonclaw_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2022 Google Inc # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F412CX=y -CONFIG_BOARD_GOOGLE_DRAGONCLAW=y - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/google/index.rst b/boards/google/index.rst new file mode 100644 index 00000000000..207a008b91c --- /dev/null +++ b/boards/google/index.rst @@ -0,0 +1,10 @@ +.. _boards-google: + +Google, Inc. +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/google/kukui/Kconfig.google_kukui b/boards/google/kukui/Kconfig.google_kukui new file mode 100644 index 00000000000..51b960645ee --- /dev/null +++ b/boards/google/kukui/Kconfig.google_kukui @@ -0,0 +1,5 @@ +# Copyright 2019 The Chromium OS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GOOGLE_KUKUI + select SOC_STM32F098XX diff --git a/boards/arm64/bcm958402m2_a72/board.cmake b/boards/google/kukui/board.cmake similarity index 100% rename from boards/arm64/bcm958402m2_a72/board.cmake rename to boards/google/kukui/board.cmake diff --git a/boards/google/kukui/board.yml b/boards/google/kukui/board.yml new file mode 100644 index 00000000000..699218ade22 --- /dev/null +++ b/boards/google/kukui/board.yml @@ -0,0 +1,5 @@ +board: + name: google_kukui + vendor: google + socs: + - name: stm32f098xx diff --git a/boards/google/kukui/doc/index.rst b/boards/google/kukui/doc/index.rst new file mode 100644 index 00000000000..a68586f311f --- /dev/null +++ b/boards/google/kukui/doc/index.rst @@ -0,0 +1,88 @@ +.. _google_kukui_board: + +Google Kukui EC +############### + +Overview +******** + +Kukui is a reference board for Chromium OS-based devices Krane and +Kodama. These are known as the Lenovo Chromebook Duet and 10e Chromebook +Tablet, respectively. + +Zephyr has support for the STM32-based embedded controller (EC) on-board. + +Hardware +******** + +- STM32F098RCH6 +- MT6370 battery charger +- BMM150 compass +- BMM160 gyroscope +- Connections to the MediaTek AP + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other features (such as I2C) are not available in Zephyr. + +The default configuration can be found in +:zephyr_file:`boards/google/kukui/google_kukui_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output +(push-pull or open-drain), as input (with or without pull-up or +pull-down), or as peripheral alternate function. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA10/PA9 +- I2C_1 SCL/SDA : PB8/PB9 +- I2C_2 SCL/SDA : PA11/PA12 +- Volume down : GPIOB pin 11 +- Volume up : GPIOB pin 10 +- Power : GPIOA pin 0 + +Programming and Debugging +************************* + +Build application as usual for the ``google_kukui`` board, and flash +using Servo V2, μServo, or Servo V4 (CCD). See the +`Chromium EC Flashing Documentation`_ for more information. + +Debugging +========= + +Use SWD with a J-Link or ST-Link. + +References +********** + +.. target-notes:: + +.. _Chromium EC Flashing Documentation: + https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/google_kukui/google_kukui.dts b/boards/google/kukui/google_kukui.dts similarity index 100% rename from boards/arm/google_kukui/google_kukui.dts rename to boards/google/kukui/google_kukui.dts diff --git a/boards/arm/google_kukui/google_kukui.yaml b/boards/google/kukui/google_kukui.yaml similarity index 100% rename from boards/arm/google_kukui/google_kukui.yaml rename to boards/google/kukui/google_kukui.yaml diff --git a/boards/google/kukui/google_kukui_defconfig b/boards/google/kukui/google_kukui_defconfig new file mode 100644 index 00000000000..0196b219b8f --- /dev/null +++ b/boards/google/kukui/google_kukui_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/google/twinkie_v2/Kconfig.google_twinkie_v2 b/boards/google/twinkie_v2/Kconfig.google_twinkie_v2 new file mode 100644 index 00000000000..52f0de57ebb --- /dev/null +++ b/boards/google/twinkie_v2/Kconfig.google_twinkie_v2 @@ -0,0 +1,5 @@ +# Copyright 2023 The ChromiumOS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GOOGLE_TWINKIE_V2 + select SOC_STM32G0B1XX diff --git a/boards/arm/google_twinkie_v2/board.cmake b/boards/google/twinkie_v2/board.cmake similarity index 100% rename from boards/arm/google_twinkie_v2/board.cmake rename to boards/google/twinkie_v2/board.cmake diff --git a/boards/google/twinkie_v2/board.yml b/boards/google/twinkie_v2/board.yml new file mode 100644 index 00000000000..b77d79328f7 --- /dev/null +++ b/boards/google/twinkie_v2/board.yml @@ -0,0 +1,5 @@ +board: + name: google_twinkie_v2 + vendor: google + socs: + - name: stm32g0b1xx diff --git a/boards/google/twinkie_v2/doc/index.rst b/boards/google/twinkie_v2/doc/index.rst new file mode 100644 index 00000000000..42be6aa2958 --- /dev/null +++ b/boards/google/twinkie_v2/doc/index.rst @@ -0,0 +1,57 @@ +.. _google_twinkie_v2_board: + +Google Twinkie V2 +################# + +Overview +******** + +Google Twinkie V2 is a reference board for the google power delivery analyzer +(PDA) Twinkie V2. + +Hardware +******** + +- STM32G0B1REI6 + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/google/twinkie_v2/google_twinkie_v2_defconfig` + +Pin Mapping +=========== + +Default Zephyr Peripheral Mapping: +---------------------------------- +- CC1_BUF : PA1 +- CC2_BUF : PA3 +- VBUS_READ_BUF : PB11 +- CSA_VBUS : PC4 +- CSA_CC2 : PC5 + +Programming and Debugging +************************* + +Build application as usual for the ``google_twinkie_v2`` board, and flash +using dfu-util or J-Link. + +Debugging +========= + +Use SWD with a J-Link or ST-Link. diff --git a/boards/arm/google_twinkie_v2/google_twinkie_v2.dts b/boards/google/twinkie_v2/google_twinkie_v2.dts similarity index 100% rename from boards/arm/google_twinkie_v2/google_twinkie_v2.dts rename to boards/google/twinkie_v2/google_twinkie_v2.dts diff --git a/boards/arm/google_twinkie_v2/google_twinkie_v2.yaml b/boards/google/twinkie_v2/google_twinkie_v2.yaml similarity index 100% rename from boards/arm/google_twinkie_v2/google_twinkie_v2.yaml rename to boards/google/twinkie_v2/google_twinkie_v2.yaml diff --git a/boards/arm/google_twinkie_v2/google_twinkie_v2_defconfig b/boards/google/twinkie_v2/google_twinkie_v2_defconfig similarity index 80% rename from boards/arm/google_twinkie_v2/google_twinkie_v2_defconfig rename to boards/google/twinkie_v2/google_twinkie_v2_defconfig index 040be2d3672..3262a345bd2 100644 --- a/boards/arm/google_twinkie_v2/google_twinkie_v2_defconfig +++ b/boards/google/twinkie_v2/google_twinkie_v2_defconfig @@ -2,9 +2,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G0B1XX=y - # GPIO Controller CONFIG_GPIO=y diff --git a/boards/hardkernel/index.rst b/boards/hardkernel/index.rst new file mode 100644 index 00000000000..b37651add3c --- /dev/null +++ b/boards/hardkernel/index.rst @@ -0,0 +1,10 @@ +.. _boards-hardkernel: + +HardKernel +########## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/hardkernel/odroid_go/Kconfig b/boards/hardkernel/odroid_go/Kconfig new file mode 100644 index 00000000000..b35c68b5a0e --- /dev/null +++ b/boards/hardkernel/odroid_go/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ODROID_GO + select SOC_ESP32_PROCPU if BOARD_ODROID_GO_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ODROID_GO_ESP32_APPCPU diff --git a/boards/hardkernel/odroid_go/Kconfig.defconfig b/boards/hardkernel/odroid_go/Kconfig.defconfig new file mode 100644 index 00000000000..345a0f4f64e --- /dev/null +++ b/boards/hardkernel/odroid_go/Kconfig.defconfig @@ -0,0 +1,39 @@ +# ODROID-GO Game Kit configuration + +# Copyright (c) 2019 Yannis Damigos +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ODROID_GO_ESP32_PROCPU + +config DISK_DRIVER_SDMMC + default y if DISK_ACCESS + +config SPI + default y if DISK_DRIVER_SDMMC + +config ESP_SPIRAM + default y + +choice SPIRAM_TYPE + default SPIRAM_TYPE_ESPPSRAM64 +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ODROID_GO_ESP32_PROCPU + +if BOARD_ODROID_GO_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 4096 + +endif # BOARD_ODROID_GO_ESP32_APPCPU diff --git a/boards/hardkernel/odroid_go/Kconfig.odroid_go b/boards/hardkernel/odroid_go/Kconfig.odroid_go new file mode 100644 index 00000000000..88d56badd91 --- /dev/null +++ b/boards/hardkernel/odroid_go/Kconfig.odroid_go @@ -0,0 +1,7 @@ +# ODROID-GO Game Kit configuration + +# Copyright (c) 2019 Yannis Damigos +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ODROID_GO + select SOC_ESP32_WROVER_E_N16R2 diff --git a/boards/xtensa/esp32s2_franzininho/Kconfig.sysbuild b/boards/hardkernel/odroid_go/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32s2_franzininho/Kconfig.sysbuild rename to boards/hardkernel/odroid_go/Kconfig.sysbuild diff --git a/boards/xtensa/heltec_wifi_lora32_v2/board.cmake b/boards/hardkernel/odroid_go/board.cmake similarity index 100% rename from boards/xtensa/heltec_wifi_lora32_v2/board.cmake rename to boards/hardkernel/odroid_go/board.cmake diff --git a/boards/hardkernel/odroid_go/board.yml b/boards/hardkernel/odroid_go/board.yml new file mode 100644 index 00000000000..fad513c5ee9 --- /dev/null +++ b/boards/hardkernel/odroid_go/board.yml @@ -0,0 +1,5 @@ +board: + name: odroid_go + vendor: hardkernel + socs: + - name: esp32 diff --git a/boards/xtensa/odroid_go/doc/img/odroid_go.jpg b/boards/hardkernel/odroid_go/doc/img/odroid_go.jpg similarity index 100% rename from boards/xtensa/odroid_go/doc/img/odroid_go.jpg rename to boards/hardkernel/odroid_go/doc/img/odroid_go.jpg diff --git a/boards/hardkernel/odroid_go/doc/index.rst b/boards/hardkernel/odroid_go/doc/index.rst new file mode 100644 index 00000000000..9fa4d107b13 --- /dev/null +++ b/boards/hardkernel/odroid_go/doc/index.rst @@ -0,0 +1,245 @@ +.. _odroid_go: + +ODROID-GO +######### + +Overview +******** + +ODROID-GO Game Kit is a "Do it yourself" ("DIY") portable game console by +HardKernel. It features a custom ESP32-WROVER with 16 MB flash and it operates +from 80 MHz - 240 MHz [1]_. + +The features include the following: + +- Dual core Xtensa microprocessor (LX6), running at 80 - 240MHz +- 4 MB of PSRAM +- 802.11b/g/n/e/i +- Bluetooth v4.2 BR/EDR and BLE +- 2.4 inch 320x240 TFT LCD +- Speaker +- Micro SD card slot +- Micro USB port (battery charging and USB_UART data communication +- Input Buttons (Menu, Volume, Select, Start, A, B, Direction Pad) +- Expansion port (I2C, GPIO, SPI) +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) + +.. figure:: img/odroid_go.jpg + :align: center + :alt: ODROID-GO + + ODROID-Go Game Kit + +External Connector +================== + ++-------+------------------+-------------------------+ +| PIN # | Signal Name | ESP32-WROVER Functions | ++=======+==================+=========================+ +| 1 | GND | GND | ++-------+------------------+-------------------------+ +| 2 | VSPI.SCK (IO18) | GPIO18, VSPICLK | ++-------+------------------+-------------------------+ +| 3 | IO12 | GPIO12 | ++-------+------------------+-------------------------+ +| 4 | IO15 | GPIO15, ADC2_CH3 | ++-------+------------------+-------------------------+ +| 5 | IO4 | GPIO4, ADC2_CH0 | ++-------+------------------+-------------------------+ +| 6 | P3V3 | 3.3 V | ++-------+------------------+-------------------------+ +| 7 | VSPI.MISO (IO19) | GPIO19, VSPIQ | ++-------+------------------+-------------------------+ +| 8 | VSPI.MOSI (IO23) | GPIO23, VSPID | ++-------+------------------+-------------------------+ +| 9 | N.C | N/A | ++-------+------------------+-------------------------+ +| 10 | VBUS | USB VBUS (5V) | ++-------+------------------+-------------------------+ + +Supported Features +================== + +The Zephyr odroid_go board configuration supports the following hardware +features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ + + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: odroid_go + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: odroid_go/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``odroid_go`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: odroid_go/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! odroid_go + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: odroid_go/esp32/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: odroid_go/esp32/procpu + :goals: debug + +References +********** + +.. target-notes:: + +.. [1] https://wiki.odroid.com/odroid_go/odroid_go +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/xtensa/odroid_go/odroid_go-pinctrl.dtsi b/boards/hardkernel/odroid_go/odroid_go-pinctrl.dtsi similarity index 100% rename from boards/xtensa/odroid_go/odroid_go-pinctrl.dtsi rename to boards/hardkernel/odroid_go/odroid_go-pinctrl.dtsi diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.dts b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.dts new file mode 100644 index 00000000000..6b59353de6d --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "ODROID-GO Game Kit APPCPU"; + compatible = "hardkernel,odroid_go", "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.yaml b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.yaml new file mode 100644 index 00000000000..a5a1c003ef3 --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: odroid_go/esp32/appcpu +name: ODROID-GO +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: hardkernel diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.dts b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.dts new file mode 100644 index 00000000000..caf722d8cc9 --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.dts @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2019 Yannis Damigos + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "odroid_go-pinctrl.dtsi" +#include + +/ { + model = "ODROID-GO Game Kit PROCPU"; + compatible = "hardkernel,odroid_go", "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,display = &ili9341; + }; + + leds { + compatible = "gpio-leds"; + blue_led: led { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + label = "Status Led"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + menu_button: menu_button { + label = "Menu"; + gpios = <&gpio0 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + volume_button: volume_button { + label = "Volume"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + select_button: select_button { + label = "Select"; + gpios = <&gpio0 27 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + a_button: a_button { + label = "A"; + gpios = <&gpio1 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + b_button: b_button { + label = "B"; + gpios = <&gpio1 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + start_button: start_button { + label = "Start"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + lcd_backlight_en { + compatible = "regulator-fixed"; + regulator-name = "lcd_backlight_enable"; + enable-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + aliases { + uart-0 = &uart0; + led0 = &blue_led; + sw0 = &menu_button; + watchdog0 = &wdt0; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + spi-dev = <&spi3>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + ili9341: ili9341@0 { + compatible = "ilitek,ili9341"; + mipi-max-frequency = <25000000>; + pixel-format = <0>; + reg = <0>; + rotation = <270>; + width = <320>; + height = <240>; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; + + blue-led-disable { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + + sdhc0: sdhc@1 { + compatible = "zephyr,sdhc-spi-slot"; + reg = <1>; + status = "okay"; + mmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + spi-max-frequency = <20000000>; + }; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.yaml b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.yaml new file mode 100644 index 00000000000..59363bb4ee9 --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.yaml @@ -0,0 +1,18 @@ +identifier: odroid_go/esp32/procpu +name: ODROID-GO +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: hardkernel diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_procpu_defconfig b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu_defconfig new file mode 100644 index 00000000000..5de7f124113 --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y + +# required to enable LCD backlight +CONFIG_REGULATOR=y diff --git a/boards/xtensa/heltec_wifi_lora32_v2/CMakeLists.txt b/boards/heltec/heltec_wifi_lora32_v2/CMakeLists.txt similarity index 100% rename from boards/xtensa/heltec_wifi_lora32_v2/CMakeLists.txt rename to boards/heltec/heltec_wifi_lora32_v2/CMakeLists.txt diff --git a/boards/heltec/heltec_wifi_lora32_v2/Kconfig b/boards/heltec/heltec_wifi_lora32_v2/Kconfig new file mode 100644 index 00000000000..bfffbcb9563 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HELTEC_WIFI_LORA32_V2 + select SOC_ESP32_PROCPU if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_APPCPU diff --git a/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig new file mode 100644 index 00000000000..4f459aa0ca4 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig @@ -0,0 +1,26 @@ +# HELTEC board configuration + +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_HELTEC_WIFI_LORA32_V2_ESP32_PROCPU + +if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_HELTEC_WIFI_LORA_V2_ESP32_APPCPU diff --git a/boards/heltec/heltec_wifi_lora32_v2/Kconfig.heltec_wifi_lora32_v2 b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.heltec_wifi_lora32_v2 new file mode 100644 index 00000000000..0e5d5c62da6 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.heltec_wifi_lora32_v2 @@ -0,0 +1,7 @@ +# HELTEC ESP32 board configuration + +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HELTEC_WIFI_LORA32_V2 + select SOC_ESP32_D0WD_V3 diff --git a/boards/xtensa/esp32s2_saola/Kconfig.sysbuild b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32s2_saola/Kconfig.sysbuild rename to boards/heltec/heltec_wifi_lora32_v2/Kconfig.sysbuild diff --git a/boards/xtensa/odroid_go/board.cmake b/boards/heltec/heltec_wifi_lora32_v2/board.cmake similarity index 100% rename from boards/xtensa/odroid_go/board.cmake rename to boards/heltec/heltec_wifi_lora32_v2/board.cmake diff --git a/boards/heltec/heltec_wifi_lora32_v2/board.yml b/boards/heltec/heltec_wifi_lora32_v2/board.yml new file mode 100644 index 00000000000..e87344a9766 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/board.yml @@ -0,0 +1,5 @@ +board: + name: heltec_wifi_lora32_v2 + vendor: heltec + socs: + - name: esp32 diff --git a/boards/xtensa/heltec_wifi_lora32_v2/board_init.c b/boards/heltec/heltec_wifi_lora32_v2/board_init.c similarity index 100% rename from boards/xtensa/heltec_wifi_lora32_v2/board_init.c rename to boards/heltec/heltec_wifi_lora32_v2/board_init.c diff --git a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst new file mode 100644 index 00000000000..07355a6d70b --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst @@ -0,0 +1,208 @@ +.. _heltec_wifi_lora32_v2: + +Heltec WiFi LoRa 32 (V2) +######################## + +Overview +******** + +Heltec WiFi LoRa 32 is a classic IoT dev-board designed & produced by Heltec Automation(TM), it's a highly +integrated product based on ESP32 + SX127x, it has Wi-Fi, BLE, LoRa functions, also Li-Po battery management +system, 0.96" OLED are also included. [1]_ + +The features include the following: + +- Microprocessor: ESP32 (dual-core 32-bit MCU + ULP core) +- LoRa node chip SX1276/SX1278 +- Micro USB interface with a complete voltage regulator, ESD protection, short circuit protection, + RF shielding, and other protection measures +- Onboard SH1.25-2 battery interface, integrated lithium battery management system +- Integrated WiFi, LoRa, Bluetooth three network connections, onboard Wi-Fi, Bluetooth dedicated 2.4GHz + metal 3D antenna, reserved IPEX (U.FL) interface for LoRa use +- Onboard 0.96-inch 128*64 dot matrix OLED display +- Integrated CP2102 USB to serial port chip + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: heltec_wifi_lora32_v2 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wifi_lora32_v2/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``heltec_wifi_lora32_v2`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wifi_lora32_v2/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! heltec_wifi_lora32_v2 + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wifi_lora32_v2/esp32/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wifi_lora32_v2/esp32/procpu + :goals: debug + +Utilizing Hardware Features +*************************** + +Onboard OLED display +==================== + +The onboard OLED display is of type ``ssd1306``, has 128*64 pixels and is +connected via I2C. It can therefore be used by enabling the +:ref:`ssd1306_128_shield` as shown in the following for the :zephyr:code-sample:`lvgl` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/display/lvgl + :board: heltec_wifi_lora32_v2/esp32/procpu + :shield: ssd1306_128x64 + :goals: flash + +References +********** + +- `Heltec WiFi LoRa (v2) Pinout Diagram `_ +- `Heltec WiFi LoRa (v2) Schematic Diagrams `_ +- `ESP32 Toolchain `_ +- `esptool documentation `_ +- `OpenOCD ESP32 `_ + +.. [1] https://heltec.org/project/wifi-lora-32/ diff --git a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2-pinctrl.dtsi b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2-pinctrl.dtsi similarity index 100% rename from boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2-pinctrl.dtsi rename to boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2-pinctrl.dtsi diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.dts new file mode 100644 index 00000000000..4cf9e26b89d --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Heltec Wi-Fi Lora32 V2 APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.yaml b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.yaml new file mode 100644 index 00000000000..373c6b0eae9 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: heltec_wifi_lora32_v2/esp32/appcpu +name: ESP32 DEVKITC WROVER APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu_defconfig b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.dts new file mode 100644 index 00000000000..5e1c8c6c6ff --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.dts @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "heltec_wifi_lora32_v2-pinctrl.dtsi" +#include + +/ { + model = "Heltec Wi-Fi Lora32 V2 PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + i2c-0 = &i2c0; + led0 = &led0; + sw0 = &button0; + watchdog0 = &wdt0; + lora0 = &lora0; + }; + + leds { + compatible = "gpio-leds"; + led0: led { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + label = "White LED"; + }; + + vext: vext { + gpios = <&gpio0 21 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "External VCC"; + }; + + oledrst: oledrst { + gpios = <&gpio0 16 (GPIO_PULL_UP | GPIO_ACTIVE_HIGH)>; + label = "OLED Reset"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "PRG Button"; + zephyr,code = ; + }; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + lora0: lora@0 { + compatible = "semtech,sx1276"; + reg = <0>; + reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + dio-gpios = + /* SX1276 D0 -> GPIO26 */ + <&gpio0 26 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D1 -> GPIO35 */ + <&gpio1 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D1 -> GPIO34 */ + <&gpio1 2 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + spi-max-frequency = <1000000>; + power-amplifier-output = "pa-boost"; + }; +}; + +&flash0 { + /* the board is using plain d0wd SoC part without the flash + * so any additional flash size should be defined at the board level + */ + reg = <0x0 DT_SIZE_M(8)>; + + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; + +/* Required by the ssd1306_128x64 shield which enables the OLED display */ +arduino_i2c: &i2c0 {}; diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.yaml b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.yaml new file mode 100644 index 00000000000..f8571589d7a --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.yaml @@ -0,0 +1,17 @@ +identifier: heltec_wifi_lora32_v2/esp32/procpu +name: HELTEC WiFi LoRa 32 (V2) Board +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - watchdog + - uart + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu_defconfig b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu_defconfig new file mode 100644 index 00000000000..f029cac9e9e --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/CMakeLists.txt b/boards/heltec/heltec_wireless_stick_lite_v3/CMakeLists.txt similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/CMakeLists.txt rename to boards/heltec/heltec_wireless_stick_lite_v3/CMakeLists.txt diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig new file mode 100644 index 00000000000..fc8b7634c1d --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HELTEC_WIRELESS_STICK_LITE_V3 + select SOC_ESP32S3_PROCPU if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_APPCPU diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig new file mode 100644 index 00000000000..82915e44b94 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Heltec Wireless Stick Lite (V3) board configuration + +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# Copyright (c) 2023 The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_PROCPU + +if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_APPCPU diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.heltec_wireless_stick_lite_v3 b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.heltec_wireless_stick_lite_v3 new file mode 100644 index 00000000000..d868ea29de2 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.heltec_wireless_stick_lite_v3 @@ -0,0 +1,8 @@ +# Heltec Wireless Stick Lite (V3) board configuration + +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# Copyright (c) 2023 The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HELTEC_WIRELESS_STICK_LITE_V3 + select SOC_ESP32S3_FN8 diff --git a/boards/xtensa/esp32s3_devkitm/Kconfig.sysbuild b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32s3_devkitm/Kconfig.sysbuild rename to boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.sysbuild diff --git a/boards/xtensa/esp32s2_lolin_mini/board.cmake b/boards/heltec/heltec_wireless_stick_lite_v3/board.cmake similarity index 100% rename from boards/xtensa/esp32s2_lolin_mini/board.cmake rename to boards/heltec/heltec_wireless_stick_lite_v3/board.cmake diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/board.yml b/boards/heltec/heltec_wireless_stick_lite_v3/board.yml new file mode 100644 index 00000000000..12cb133cb4f --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/board.yml @@ -0,0 +1,5 @@ +board: + name: heltec_wireless_stick_lite_v3 + vendor: heltec + socs: + - name: esp32s3 diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/board_init.c b/boards/heltec/heltec_wireless_stick_lite_v3/board_init.c similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/board_init.c rename to boards/heltec/heltec_wireless_stick_lite_v3/board_init.c diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3.webp b/boards/heltec/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3.webp similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3.webp rename to boards/heltec/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3.webp diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3_pinout.webp b/boards/heltec/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3_pinout.webp similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3_pinout.webp rename to boards/heltec/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3_pinout.webp diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst new file mode 100644 index 00000000000..987eeb9f0f1 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst @@ -0,0 +1,306 @@ +.. heltec_wireless_stick_lite_v3: + +HelTec Wireless Stick Lite (V3) +############################### + +Overview +******** + +HelTec Wireless Stick Lite (V3) is a development board with Wi-Fi, Bluetooth and LoRa support. It is designed and produced by HelTec Automation(TM). [1]_ + +.. figure:: heltec_wireless_stick_lite_v3.webp + :width: 400px + :align: center + :alt: HelTec Wireless Stick Lite (V3) + + HelTec Wireless Stick Lite (V3) (Credit: Chengdu HelTec Automation Technology Co., Ltd.) + +Hardware +******** + +The main hardware features are: + +- ESP32-S3FN8 low-power MCU-based SoC (dual-core Xtensa® 32-bit LX7 microprocessor, five stage pipeline rack Structure, main frequency up to 240 MHz). +- Semtech SX1262 LoRa node chip +- Type-C USB interface with a complete voltage regulator, ESD protection, short circuit protection, RF shielding, and other protection measures (note: you need an USB-A to USB-C cable if you want to power-up the board from USB). +- Onboard SH1.25-2 battery interface, integrated lithium battery management system (charge and discharge management, overcharge protection, battery power detection, USB / battery power automatic switching). +- Integrated WiFi and Bluetooth interfaces with 2.4GHz metal spring antenna and reserved IPEX (U.FL) interface for LoRa use. +- Integrated CP2102 USB to serial port chip, convenient for program downloading, debugging information printing. +- Good RF circuit design and low-power design. + +Supported Features +================== +- LoRa via SPI +- UART0 (USB Serial via CP2102) +- UART1 +- I2C +- CAN (optional, need to enable) +- PWM LED +- User Switch / Button + +Connections and IOs +=================== + +.. figure:: heltec_wireless_stick_lite_v3_pinout.webp + :width: 600px + :align: center + :alt: HelTec Wireless Stick Lite (V3) Pinout + + Pinout (Credit: Chengdu HelTec Automation Technology Co., Ltd.) + +.. table:: HelTec Wireless Stick Lite (V3) Pinout + :widths: auto + + +--------+---------+-----------------------------+ + | Header | Function| Description | + +========+=========+=============================+ + | J2.1 | Ve | | + +--------+---------+-----------------------------+ + | J2.2 | GND | | + +--------+---------+-----------------------------+ + | J2.3 | | | + +--------+---------+-----------------------------+ + | J2.4 | U0RXD | Zephyr Console+Shell | + +--------+---------+-----------------------------+ + | J2.5 | U0TXD | Zephyr Console+Shell | + +--------+---------+-----------------------------+ + | J2.6 | | | + +--------+---------+-----------------------------+ + | J2.7 | | | + +--------+---------+-----------------------------+ + | J2.8 | GPIO35 | PWM LED Control | + +--------+---------+-----------------------------+ + | J2.9 | GPIO36 | Vext Control | + +--------+---------+-----------------------------+ + | J2.10 | GPIO37 | ADC Control | + +--------+---------+-----------------------------+ + | J2.11 | | | + +--------+---------+-----------------------------+ + | J2.12 | GPIO39 | | + +--------+---------+-----------------------------+ + | J2.13 | GPIO40 | | + +--------+---------+-----------------------------+ + | J2.14 | GPIO41 | | + +--------+---------+-----------------------------+ + | J2.15 | GPIO42 | | + +--------+---------+-----------------------------+ + | J2.16 | GPIO45 | | + +--------+---------+-----------------------------+ + | J2.17 | GPIO46 | | + +--------+---------+-----------------------------+ + | J2.18 | ADC1_CH0| Battery Voltage Measurement | + +--------+---------+-----------------------------+ + | J2.19 | | | + +--------+---------+-----------------------------+ + | J2.20 | | | + +--------+---------+-----------------------------+ + | J3.1 | 5V | | + +--------+---------+-----------------------------+ + | J3.2 | 3V3 | | + +--------+---------+-----------------------------+ + | J3.3 | GND | | + +--------+---------+-----------------------------+ + | J3.4 | GPIO47 | | + +--------+---------+-----------------------------+ + | J3.5 | GPIO48 | | + +--------+---------+-----------------------------+ + | J3.6 | GPIO0 | User Switch | + +--------+---------+-----------------------------+ + | J3.7 | | | + +--------+---------+-----------------------------+ + | J3.8 | | | + +--------+---------+-----------------------------+ + | J3.9 | U1RXD | UART 1 | + +--------+---------+-----------------------------+ + | J3.10 | GPIO21 | | + +--------+---------+-----------------------------+ + | J3.11 | | | + +--------+---------+-----------------------------+ + | J3.12 | U1TXD | UART 1 | + +--------+---------+-----------------------------+ + | J3.13 | | | + +--------+---------+-----------------------------+ + | J3.14 | NC | Reset Switch | + +--------+---------+-----------------------------+ + | J3.15 | | | + +--------+---------+-----------------------------+ + | J3.16 | | | + +--------+---------+-----------------------------+ + | J3.17 | | | + +--------+---------+-----------------------------+ + | J3.18 | | | + +--------+---------+-----------------------------+ + | J3.19 | TWAI_TX | CAN (optional) | + +--------+---------+-----------------------------+ + | J3.20 | TWAI_RX | CAN (optional) | + +--------+---------+-----------------------------+ + + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Programming and Debugging +************************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the EPS32-S3 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: heltec_wireless_stick_lite_v3 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32S3 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wireless_stick_lite_v3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``heltec_wireless_stick_lite_v3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wireless_stick_lite_v3/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! heltec_wireless_stick_lite_v3 + +Debugging +========= + +As with much custom hardware, the ESP32S3 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wireless_stick_lite_v3/esp32s3/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wireless_stick_lite_v3/esp32s3/procpu + :goals: debug + +References +********** + +- `Heltec Wireless Stick Lite (v3) Pinout Diagram `_ +- `Heltec Wireless Stick Lite (v3) Schematic Diagrams `_ +- `ESP-IDF Programming Guide `_ +- `esptool documentation `_ +- `OpenOCD ESP32 `_ + +.. [1] https://heltec.org/project/wireless-stick-lite-v2/ diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3-pinctrl.dtsi b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3-pinctrl.dtsi similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3-pinctrl.dtsi rename to boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3-pinctrl.dtsi diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.dts new file mode 100644 index 00000000000..6c49e64e8d1 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "Heltec Wireless Stick Lite V3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.yaml b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.yaml new file mode 100644 index 00000000000..a465da8f94d --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: heltec_wireless_stick_lite_v3/esp32s3/appcpu +name: ESP32-S3 DevKitM APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: heltec diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.dts new file mode 100644 index 00000000000..38d870a6fbb --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.dts @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2023 The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "heltec_wireless_stick_lite_v3-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "Heltec Wireless Stick Lite V3 PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + pwm-0 = &ledc0; + pwm-led0 = &pwm_led_white; + uart-0 = &uart0; + uart-1 = &uart1; + i2c-0 = &i2c0; + lora0 = &lora0; + sw0 = &button0; + watchdog0 = &wdt0; + }; + + leds { + compatible = "gpio-leds"; + + vext: vext { + gpios = <&gpio0 36 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Vext Control"; + }; + + adc: adc { + gpios = <&gpio0 37 GPIO_ACTIVE_LOW>; + label = "ADC Control"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led_white: pwm_led_gpio0_35 { + label = "White PWM LED"; + pwms = <&ledc0 0 PWM_MSEC(10) PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "USER SW"; + zephyr,code = ; + }; + }; + + vbatt { + compatible = "voltage-divider"; + io-channels = <&adc1 0>; + output-ohms = <100000>; + full-ohms = <(100000 + 390000)>; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&adc1 { + status ="okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&ledc0 { + pinctrl-0 = <&ledc0_default>; + pinctrl-names = "default"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + channel0@0 { + reg = <0x0>; + timer = <0>; + }; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; + lora0: lora@0 { + compatible = "semtech,sx1262"; + reg = <0>; + reset-gpios = <&gpio0 12 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + busy-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + dio1-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + dio2-tx-enable; + dio3-tcxo-voltage = ; + tcxo-power-startup-delay-ms = <5>; + spi-max-frequency = <16000000>; + }; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; + bus-speed = <125000>; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.yaml b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.yaml new file mode 100644 index 00000000000..91221f8616b --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.yaml @@ -0,0 +1,23 @@ +identifier: heltec_wireless_stick_lite_v3/esp32s3/procpu +name: Heltec Wireless Stick Lite (V3) +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - lora +testing: + ignore_tags: + - net + - bluetooth +vendor: heltec diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu_defconfig b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu_defconfig new file mode 100644 index 00000000000..2dfe1853d5c --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_PWM=y +CONFIG_SERIAL=y +CONFIG_SPI=y +CONFIG_UART_CONSOLE=y diff --git a/boards/xtensa/esp32s3_luatos_core/support/openocd.cfg b/boards/heltec/heltec_wireless_stick_lite_v3/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/support/openocd.cfg rename to boards/heltec/heltec_wireless_stick_lite_v3/support/openocd.cfg diff --git a/boards/heltec/index.rst b/boards/heltec/index.rst new file mode 100644 index 00000000000..5e8fb67eea2 --- /dev/null +++ b/boards/heltec/index.rst @@ -0,0 +1,10 @@ +.. _boards-heltec: + +Heltec +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/holyiot/index.rst b/boards/holyiot/index.rst new file mode 100644 index 00000000000..9fb2705a252 --- /dev/null +++ b/boards/holyiot/index.rst @@ -0,0 +1,10 @@ +.. _boards-holyiot: + +Shenzhen Holyiot Technology Co. +############################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/holyiot/yj16019/Kconfig.defconfig b/boards/holyiot/yj16019/Kconfig.defconfig new file mode 100644 index 00000000000..c4298c49d6e --- /dev/null +++ b/boards/holyiot/yj16019/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Holyiot YJ-16019 board configuration + +# Copyright (c) 2019 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HOLYIOT_YJ16019 + +config BT_CTLR + default BT + +endif # BOARD_HOLYIOT_YJ16019 diff --git a/boards/holyiot/yj16019/Kconfig.holyiot_yj16019 b/boards/holyiot/yj16019/Kconfig.holyiot_yj16019 new file mode 100644 index 00000000000..6db73feb405 --- /dev/null +++ b/boards/holyiot/yj16019/Kconfig.holyiot_yj16019 @@ -0,0 +1,7 @@ +# Holyiot YJ-16019 board configuration + +# Copyright (c) 2019 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HOLYIOT_YJ16019 + select SOC_NRF52832_QFAA diff --git a/boards/arm/holyiot_yj16019/board.cmake b/boards/holyiot/yj16019/board.cmake similarity index 100% rename from boards/arm/holyiot_yj16019/board.cmake rename to boards/holyiot/yj16019/board.cmake diff --git a/boards/holyiot/yj16019/board.yml b/boards/holyiot/yj16019/board.yml new file mode 100644 index 00000000000..e8ab16bc427 --- /dev/null +++ b/boards/holyiot/yj16019/board.yml @@ -0,0 +1,5 @@ +board: + name: holyiot_yj16019 + vendor: holyiot + socs: + - name: nrf52832 diff --git a/boards/arm/holyiot_yj16019/doc/img/holyiot_yj16019_front.jpg b/boards/holyiot/yj16019/doc/img/holyiot_yj16019_front.jpg similarity index 100% rename from boards/arm/holyiot_yj16019/doc/img/holyiot_yj16019_front.jpg rename to boards/holyiot/yj16019/doc/img/holyiot_yj16019_front.jpg diff --git a/boards/arm/holyiot_yj16019/doc/img/holyiot_yj16019_pcb.jpg b/boards/holyiot/yj16019/doc/img/holyiot_yj16019_pcb.jpg similarity index 100% rename from boards/arm/holyiot_yj16019/doc/img/holyiot_yj16019_pcb.jpg rename to boards/holyiot/yj16019/doc/img/holyiot_yj16019_pcb.jpg diff --git a/boards/holyiot/yj16019/doc/index.rst b/boards/holyiot/yj16019/doc/index.rst new file mode 100644 index 00000000000..7ecbf5b0931 --- /dev/null +++ b/boards/holyiot/yj16019/doc/index.rst @@ -0,0 +1,147 @@ +.. _holyiot_yj16019: + +Holyiot YJ-16019 +################ + +Overview +******** + +The `Holyiot`_ YJ-16019 hardware provides support for the Nordic +Semiconductor nRF52832 ARM Cortex-M4 CPU and the following devices: + +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/holyiot_yj16019_front.jpg + :align: center + :alt: Holyiot YJ-16019 + + Holyiot YJ-16019 (Credit: Holyiot) + +The board is equipped with one LED, one push button, and is powered by +a CR2032 coin cell. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + +Hardware +******** + +The nRF52832 of the Holyiot YJ-16019 is clocked by an external crystal with a frequency of 32 MHz +(Y1). The 32.768 kHz crystal (Y2) shown on the board schematics is not mounted. + +Supported Features +================== + +The holyiot_yj16019 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +LED and push button +------------------- + +* Push button = P0.28 +* LED = P0.29 + +Programming and Debugging +************************* + +Applications for the ``holyiot_yj16019`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); however, an external +Segger J-Link is required since the board does not have any on-board +debug IC. + +The following pins of the Segger J-Link must be connected to the following test +pads on the PCB (see image): + +* VTref = VCC +* GND = GND +* SWDIO = SDO +* SWCLK = SCK + +.. figure:: img/holyiot_yj16019_pcb.jpg + :align: center + :alt: Holyiot YJ-16019 PCB + + Holyiot YJ-16019 PCB (Credit: Holyiot) + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: holyiot_yj16019 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +nRF52x-based boards with a Segger debugger. + + +Testing the LED and button on the Holyiot YJ-16019 +************************************************** + +There are 2 samples that allow you to test that the button and LED on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found +in :zephyr_file:`boards/holyiot/yj16019/holyiot_yj16019.dts`. + +References +********** + +.. target-notes:: + +.. _Holyiot: http://www.holyiot.com +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/holyiot_yj16019/holyiot_yj16019-pinctrl.dtsi b/boards/holyiot/yj16019/holyiot_yj16019-pinctrl.dtsi similarity index 100% rename from boards/arm/holyiot_yj16019/holyiot_yj16019-pinctrl.dtsi rename to boards/holyiot/yj16019/holyiot_yj16019-pinctrl.dtsi diff --git a/boards/arm/holyiot_yj16019/holyiot_yj16019.dts b/boards/holyiot/yj16019/holyiot_yj16019.dts similarity index 100% rename from boards/arm/holyiot_yj16019/holyiot_yj16019.dts rename to boards/holyiot/yj16019/holyiot_yj16019.dts diff --git a/boards/arm/holyiot_yj16019/holyiot_yj16019.yaml b/boards/holyiot/yj16019/holyiot_yj16019.yaml similarity index 100% rename from boards/arm/holyiot_yj16019/holyiot_yj16019.yaml rename to boards/holyiot/yj16019/holyiot_yj16019.yaml diff --git a/boards/holyiot/yj16019/holyiot_yj16019_defconfig b/boards/holyiot/yj16019/holyiot_yj16019_defconfig new file mode 100644 index 00000000000..cee867613f0 --- /dev/null +++ b/boards/holyiot/yj16019/holyiot_yj16019_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +# 32kHz clock source +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/arm/bt510/pre_dt_board.cmake b/boards/holyiot/yj16019/pre_dt_board.cmake similarity index 100% rename from boards/arm/bt510/pre_dt_board.cmake rename to boards/holyiot/yj16019/pre_dt_board.cmake diff --git a/boards/index.rst b/boards/index.rst index 9c843c9e95b..77814350d9e 100644 --- a/boards/index.rst +++ b/boards/index.rst @@ -15,15 +15,17 @@ available under :zephyr_file:`doc/templates/board.tmpl`. .. toctree:: :maxdepth: 2 + :glob: - arc/index.rst - arm/index.rst - arm64/index.rst - mips/index.rst - nios2/index.rst - posix/index.rst - riscv/index.rst - sparc/index.rst - x86/index.rst - xtensa/index.rst - shields/index.rst + */index + +.. _boards-shields: + +Shields +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + shields/**/* diff --git a/boards/infineon/index.rst b/boards/infineon/index.rst new file mode 100644 index 00000000000..729b67d60a6 --- /dev/null +++ b/boards/infineon/index.rst @@ -0,0 +1,10 @@ +.. _boards-cypress: + +Infineon Technologies +##################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/infineon/xmc45_relax_kit/Kconfig.defconfig b/boards/infineon/xmc45_relax_kit/Kconfig.defconfig new file mode 100644 index 00000000000..b47f54cf8ab --- /dev/null +++ b/boards/infineon/xmc45_relax_kit/Kconfig.defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +if BOARD_XMC45_RELAX_KIT + +if NETWORKING + +config NET_L2_ETHERNET + default y +config MDIO + default y +config TEST_RANDOM_GENERATOR + default y + +endif # NETWORKING + +endif # BOARD_XMC45_RELAX_KIT diff --git a/boards/infineon/xmc45_relax_kit/Kconfig.xmc45_relax_kit b/boards/infineon/xmc45_relax_kit/Kconfig.xmc45_relax_kit new file mode 100644 index 00000000000..e88549aa49c --- /dev/null +++ b/boards/infineon/xmc45_relax_kit/Kconfig.xmc45_relax_kit @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +config BOARD_XMC45_RELAX_KIT + select SOC_XMC4500 + select SOC_PART_NUMBER_F100X1024 diff --git a/boards/arm/xmc45_relax_kit/board.cmake b/boards/infineon/xmc45_relax_kit/board.cmake similarity index 100% rename from boards/arm/xmc45_relax_kit/board.cmake rename to boards/infineon/xmc45_relax_kit/board.cmake diff --git a/boards/infineon/xmc45_relax_kit/board.yml b/boards/infineon/xmc45_relax_kit/board.yml new file mode 100644 index 00000000000..9622337aa30 --- /dev/null +++ b/boards/infineon/xmc45_relax_kit/board.yml @@ -0,0 +1,5 @@ +board: + name: xmc45_relax_kit + vendor: infineon + socs: + - name: xmc4500 diff --git a/boards/arm/xmc45_relax_kit/doc/index.rst b/boards/infineon/xmc45_relax_kit/doc/index.rst similarity index 100% rename from boards/arm/xmc45_relax_kit/doc/index.rst rename to boards/infineon/xmc45_relax_kit/doc/index.rst diff --git a/boards/arm/xmc45_relax_kit/doc/xmc45_relax_kit.jpg b/boards/infineon/xmc45_relax_kit/doc/xmc45_relax_kit.jpg similarity index 100% rename from boards/arm/xmc45_relax_kit/doc/xmc45_relax_kit.jpg rename to boards/infineon/xmc45_relax_kit/doc/xmc45_relax_kit.jpg diff --git a/boards/arm/xmc45_relax_kit/support/openocd.cfg b/boards/infineon/xmc45_relax_kit/support/openocd.cfg similarity index 100% rename from boards/arm/xmc45_relax_kit/support/openocd.cfg rename to boards/infineon/xmc45_relax_kit/support/openocd.cfg diff --git a/boards/arm/xmc45_relax_kit/xmc45_relax_kit-pinctrl.dtsi b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit-pinctrl.dtsi similarity index 100% rename from boards/arm/xmc45_relax_kit/xmc45_relax_kit-pinctrl.dtsi rename to boards/infineon/xmc45_relax_kit/xmc45_relax_kit-pinctrl.dtsi diff --git a/boards/arm/xmc45_relax_kit/xmc45_relax_kit.dts b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts similarity index 100% rename from boards/arm/xmc45_relax_kit/xmc45_relax_kit.dts rename to boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts diff --git a/boards/arm/xmc45_relax_kit/xmc45_relax_kit.yaml b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml similarity index 100% rename from boards/arm/xmc45_relax_kit/xmc45_relax_kit.yaml rename to boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml diff --git a/boards/arm/xmc45_relax_kit/xmc45_relax_kit_defconfig b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit_defconfig similarity index 76% rename from boards/arm/xmc45_relax_kit/xmc45_relax_kit_defconfig rename to boards/infineon/xmc45_relax_kit/xmc45_relax_kit_defconfig index 97c44446daf..db059d2bd55 100644 --- a/boards/arm/xmc45_relax_kit/xmc45_relax_kit_defconfig +++ b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit_defconfig @@ -3,9 +3,6 @@ # Copyright (c) 2020 Linumiz # Author: Parthiban Nallathambi -CONFIG_BOARD_XMC45_RELAX_KIT=y -CONFIG_SOC_SERIES_XMC_4XXX=y -CONFIG_SOC_XMC4500=y CONFIG_ARM_MPU=y # enable uart driver diff --git a/boards/infineon/xmc47_relax_kit/Kconfig.defconfig b/boards/infineon/xmc47_relax_kit/Kconfig.defconfig new file mode 100644 index 00000000000..aa8b936f764 --- /dev/null +++ b/boards/infineon/xmc47_relax_kit/Kconfig.defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Schlumberger + +if BOARD_XMC47_RELAX_KIT + +if NETWORKING + +config NET_L2_ETHERNET + default y +config MDIO + default y +config TEST_RANDOM_GENERATOR + default y + +endif # NETWORKING + +endif diff --git a/boards/infineon/xmc47_relax_kit/Kconfig.xmc47_relax_kit b/boards/infineon/xmc47_relax_kit/Kconfig.xmc47_relax_kit new file mode 100644 index 00000000000..c70d84c1746 --- /dev/null +++ b/boards/infineon/xmc47_relax_kit/Kconfig.xmc47_relax_kit @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Schlumberger + +config BOARD_XMC47_RELAX_KIT + select SOC_XMC4700 + select SOC_PART_NUMBER_F144X2048 diff --git a/boards/arm/xmc47_relax_kit/arduino_r3_connector.dtsi b/boards/infineon/xmc47_relax_kit/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/xmc47_relax_kit/arduino_r3_connector.dtsi rename to boards/infineon/xmc47_relax_kit/arduino_r3_connector.dtsi diff --git a/boards/arm/xmc47_relax_kit/board.cmake b/boards/infineon/xmc47_relax_kit/board.cmake similarity index 100% rename from boards/arm/xmc47_relax_kit/board.cmake rename to boards/infineon/xmc47_relax_kit/board.cmake diff --git a/boards/infineon/xmc47_relax_kit/board.yml b/boards/infineon/xmc47_relax_kit/board.yml new file mode 100644 index 00000000000..e0077321e3a --- /dev/null +++ b/boards/infineon/xmc47_relax_kit/board.yml @@ -0,0 +1,5 @@ +board: + name: xmc47_relax_kit + vendor: infineon + socs: + - name: xmc4700 diff --git a/boards/arm/xmc47_relax_kit/doc/index.rst b/boards/infineon/xmc47_relax_kit/doc/index.rst similarity index 100% rename from boards/arm/xmc47_relax_kit/doc/index.rst rename to boards/infineon/xmc47_relax_kit/doc/index.rst diff --git a/boards/arm/xmc47_relax_kit/doc/xmc47_relax_kit.jpg b/boards/infineon/xmc47_relax_kit/doc/xmc47_relax_kit.jpg similarity index 100% rename from boards/arm/xmc47_relax_kit/doc/xmc47_relax_kit.jpg rename to boards/infineon/xmc47_relax_kit/doc/xmc47_relax_kit.jpg diff --git a/boards/arm/xmc47_relax_kit/xmc47_relax_kit-pinctrl.dtsi b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit-pinctrl.dtsi similarity index 100% rename from boards/arm/xmc47_relax_kit/xmc47_relax_kit-pinctrl.dtsi rename to boards/infineon/xmc47_relax_kit/xmc47_relax_kit-pinctrl.dtsi diff --git a/boards/arm/xmc47_relax_kit/xmc47_relax_kit.dts b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts similarity index 100% rename from boards/arm/xmc47_relax_kit/xmc47_relax_kit.dts rename to boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts diff --git a/boards/arm/xmc47_relax_kit/xmc47_relax_kit.yaml b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.yaml similarity index 100% rename from boards/arm/xmc47_relax_kit/xmc47_relax_kit.yaml rename to boards/infineon/xmc47_relax_kit/xmc47_relax_kit.yaml diff --git a/boards/infineon/xmc47_relax_kit/xmc47_relax_kit_defconfig b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit_defconfig new file mode 100644 index 00000000000..ce881b0d426 --- /dev/null +++ b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Schlumberger + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/innblue/index.rst b/boards/innblue/index.rst new file mode 100644 index 00000000000..c5491ac8f80 --- /dev/null +++ b/boards/innblue/index.rst @@ -0,0 +1,10 @@ +.. _boards-innblue: + +innblue +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/innblue/innblue21/Kconfig.defconfig b/boards/innblue/innblue21/Kconfig.defconfig new file mode 100644 index 00000000000..abf57a46a11 --- /dev/null +++ b/boards/innblue/innblue21/Kconfig.defconfig @@ -0,0 +1,45 @@ +# nRF9160 innblue V2.1 board configuration + +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_INNBLUE21 + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +if BOARD_INNBLUE21_NRF9160 && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_INNBLUE21_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_INNBLUE21_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_INNBLUE21_NRF9160_NS + +config BT_HCI_VS + default y if BT + +config REGULATOR + default y if SENSOR + +endif # BOARD_INNBLUE21 diff --git a/boards/innblue/innblue21/Kconfig.innblue21 b/boards/innblue/innblue21/Kconfig.innblue21 new file mode 100644 index 00000000000..718e3753087 --- /dev/null +++ b/boards/innblue/innblue21/Kconfig.innblue21 @@ -0,0 +1,7 @@ +# nRF9160 innblue V2.1 board configuration + +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INNBLUE21 + select SOC_NRF9160_SICA diff --git a/boards/arm/nrf9160_innblue21/board.cmake b/boards/innblue/innblue21/board.cmake similarity index 100% rename from boards/arm/nrf9160_innblue21/board.cmake rename to boards/innblue/innblue21/board.cmake diff --git a/boards/innblue/innblue21/board.yml b/boards/innblue/innblue21/board.yml new file mode 100644 index 00000000000..8d62be56790 --- /dev/null +++ b/boards/innblue/innblue21/board.yml @@ -0,0 +1,7 @@ +board: + name: innblue21 + vendor: innblue + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/nrf9160_innblue21/doc/img/nrf9160_innblue21.jpg b/boards/innblue/innblue21/doc/img/nrf9160_innblue21.jpg similarity index 100% rename from boards/arm/nrf9160_innblue21/doc/img/nrf9160_innblue21.jpg rename to boards/innblue/innblue21/doc/img/nrf9160_innblue21.jpg diff --git a/boards/innblue/innblue21/doc/index.rst b/boards/innblue/innblue21/doc/index.rst new file mode 100644 index 00000000000..333db42bfd9 --- /dev/null +++ b/boards/innblue/innblue21/doc/index.rst @@ -0,0 +1,144 @@ +.. _nrf9160_innblue21: + +nRF9160 INNBLUE21 +################# + +Overview +******** + +The nRF9160 innblue21 is a cellular IoT sensor development board, which +is based on the nRF9160 SiP, and features NB-IoT and LTE-M connectivity. + +.. figure:: img/nrf9160_innblue21.jpg + :align: center + :alt: nRF9160 innblue21 + + nRF9160 innblue21 (Credit: innblue) + +Hardware +******** + +The following parts are built into the board: + +* Accelerometer: ST LIS2DH12 +* CryptoElement: Atmel ATECC608a +* Humidity Sensor: ST HTS221 +* Qi charger: TI BQ51013 +* Battery fuel gauge: TI BQ27421 + +Supported Features +================== + +The innblue21 board configuration supports the following +hardware (as of nRF9160) features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +* LED1 ( red ) = P0.7 +* LED2 (green) = P0.6 +* LED3 ( blue) = P0.5 +* LED4 ( red ) = P0.4 + +Push buttons and Switches +------------------------- + +* BUTTON1 = P0.31 + +Security components +=================== + +- Implementation Defined Attribution Unit. The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Programming and Debugging +************************* + +innblue21 supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=innblue21`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=innblue21/nrf9160/ns``. +3. Merge the two binaries together. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=innblue21``. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9160 innblue21 +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: innblue21 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_common-pinctrl.dtsi b/boards/innblue/innblue21/innblue21_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9160_innblue21/nrf9160_innblue21_common-pinctrl.dtsi rename to boards/innblue/innblue21/innblue21_common-pinctrl.dtsi diff --git a/boards/innblue/innblue21/innblue21_common.dtsi b/boards/innblue/innblue21/innblue21_common.dtsi new file mode 100644 index 00000000000..53160a680c6 --- /dev/null +++ b/boards/innblue/innblue21/innblue21_common.dtsi @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "innblue21_common-pinctrl.dtsi" +#include + +/ { + model = "innblue v21 Dev Kit"; + compatible = "innblue,innblue21"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_1 { + gpios = <&gpio0 7 0>; + label = "RGB red channel"; + }; + green_led: led_2 { + gpios = <&gpio0 6 0>; + label = "RGB green channel"; + }; + blue_led: led_3 { + gpios = <&gpio0 5 0>; + label = "RGB blue channel"; + }; + + mode_led: led_4 { + gpios = <&gpio0 4 0>; + label = "mode red channel"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio0 31 GPIO_PULL_UP>; + label = "Button 0"; + zephyr,code = ; + }; + }; + + en_3v3_sensor: enable-3v3-sensor { + compatible = "regulator-fixed"; + regulator-name = "en_3v3_sensor"; + enable-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + startup-delay-us = <10000>; + regulator-boot-on; + }; + + en_5v0_boost: enable-5v0-boost { + compatible = "regulator-fixed"; + regulator-name = "en_5v0_boost"; + enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <10000>; + regulator-boot-on; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + led3 = &mode_led; + sw0 = &button0; + rgb-pwm = &pwm0; + mode-pwm = &pwm1; + watchdog0 = &wdt0; + accel0 = &lis2dh12_accel; + }; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-1 = <&uart2_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c2 { + compatible = "nordic,nrf-twim"; + status = "okay"; + + clock-frequency = ; + + pinctrl-0 = <&i2c2_default>; + pinctrl-1 = <&i2c2_sleep>; + pinctrl-names = "default", "sleep"; + lis2dh12_accel: lis2dh12-accel@19 { + compatible = "st,lis2dh"; + reg = <0x19>; + irq-gpios = <&gpio0 0 0>, <&gpio0 1 0>; + }; + + hts221@5f { + compatible = "st,hts221"; + reg = <0x5f>; + drdy-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + }; + + lps22hb-press@5c { + compatible = "st,lps22hb-press"; + reg = <0x5c>; + }; + + ccs811: ccs811@5a { + compatible = "ams,ccs811"; + reg = <0x5a>; + }; + + bme680@76 { + compatible = "bosch,bme680"; + reg = <0x76>; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1_default>; + pinctrl-1 = <&pwm1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x10000>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + }; + slot0_ns_partition: partition@50000 { + label = "image-0-nonsecure"; + }; + slot1_partition: partition@80000 { + label = "image-1"; + }; + slot1_ns_partition: partition@c0000 { + label = "image-1-nonsecure"; + }; + storage_partition: partition@f8000 { + label = "storage"; + reg = <0x000f8000 0x00008000>; + }; + }; +}; + +/ { + /* SRAM allocated and used by the BSD library */ + sram0_bsd: memory@20010000 { + compatible = "mmio-sram"; + }; + + /* SRAM allocated to the Non-Secure image */ + sram0_ns: memory@20020000 { + compatible = "mmio-sram"; + }; +}; + +/* Include partition configuration file */ +#include "innblue21_partition_conf.dtsi" diff --git a/boards/innblue/innblue21/innblue21_nrf9160.dts b/boards/innblue/innblue21/innblue21_nrf9160.dts new file mode 100644 index 00000000000..f13c5c9036a --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "innblue21_common.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/boards/innblue/innblue21/innblue21_nrf9160.yaml b/boards/innblue/innblue21/innblue21_nrf9160.yaml new file mode 100644 index 00000000000..5722ebcd8c9 --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160.yaml @@ -0,0 +1,14 @@ +identifier: innblue21/nrf9160 +name: nRF9160-INNBLUE21 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - i2c + - pwm + - watchdog diff --git a/boards/innblue/innblue21/innblue21_nrf9160_defconfig b/boards/innblue/innblue21/innblue21_nrf9160_defconfig new file mode 100644 index 00000000000..75e6bba7131 --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/innblue/innblue21/innblue21_nrf9160_ns.dts b/boards/innblue/innblue21/innblue21_nrf9160_ns.dts new file mode 100644 index 00000000000..2ca97a7b162 --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160_ns.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "innblue21_common.dtsi" + +/ { + chosen { + zephyr,flash = &flash0; + zephyr,sram = &sram0_ns; + zephyr,code-partition = &slot0_ns_partition; + }; +}; diff --git a/boards/innblue/innblue21/innblue21_nrf9160_ns.yaml b/boards/innblue/innblue21/innblue21_nrf9160_ns.yaml new file mode 100644 index 00000000000..17faee49190 --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160_ns.yaml @@ -0,0 +1,14 @@ +identifier: innblue21/nrf9160/ns +name: nRF9160-INNBLUE21-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - i2c + - pwm + - watchdog diff --git a/boards/innblue/innblue21/innblue21_nrf9160_ns_defconfig b/boards/innblue/innblue21/innblue21_nrf9160_ns_defconfig new file mode 100644 index 00000000000..e27861efc3c --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160_ns_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_partition_conf.dtsi b/boards/innblue/innblue21/innblue21_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9160_innblue21/nrf9160_innblue21_partition_conf.dtsi rename to boards/innblue/innblue21/innblue21_partition_conf.dtsi diff --git a/boards/arm/nrf9131ek_nrf9131/pre_dt_board.cmake b/boards/innblue/innblue21/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/pre_dt_board.cmake rename to boards/innblue/innblue21/pre_dt_board.cmake diff --git a/boards/innblue/innblue22/Kconfig.defconfig b/boards/innblue/innblue22/Kconfig.defconfig new file mode 100644 index 00000000000..540a784ec97 --- /dev/null +++ b/boards/innblue/innblue22/Kconfig.defconfig @@ -0,0 +1,45 @@ +# nRF9160 innblue V2.2 board configuration + +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_INNBLUE22 + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +if BOARD_INNBLUE22_NRF9160 && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_INNBLUE22_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_INNBLUE22_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_INNBLUE22_NRF9160_NS + +config BT_HCI_VS + default y if BT + +config REGULATOR + default y if SENSOR + +endif # BOARD_INNBLUE22 diff --git a/boards/innblue/innblue22/Kconfig.innblue22 b/boards/innblue/innblue22/Kconfig.innblue22 new file mode 100644 index 00000000000..53c5d7dd861 --- /dev/null +++ b/boards/innblue/innblue22/Kconfig.innblue22 @@ -0,0 +1,7 @@ +# nRF9160 innblue V2.2 board configuration + +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INNBLUE22 + select SOC_NRF9160_SICA diff --git a/boards/arm/nrf9160_innblue22/board.cmake b/boards/innblue/innblue22/board.cmake similarity index 100% rename from boards/arm/nrf9160_innblue22/board.cmake rename to boards/innblue/innblue22/board.cmake diff --git a/boards/innblue/innblue22/board.yml b/boards/innblue/innblue22/board.yml new file mode 100644 index 00000000000..eeb4f946ffb --- /dev/null +++ b/boards/innblue/innblue22/board.yml @@ -0,0 +1,7 @@ +board: + name: innblue22 + vendor: innblue + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/nrf9160_innblue22/doc/img/nrf9160_innblue22.jpg b/boards/innblue/innblue22/doc/img/nrf9160_innblue22.jpg similarity index 100% rename from boards/arm/nrf9160_innblue22/doc/img/nrf9160_innblue22.jpg rename to boards/innblue/innblue22/doc/img/nrf9160_innblue22.jpg diff --git a/boards/innblue/innblue22/doc/index.rst b/boards/innblue/innblue22/doc/index.rst new file mode 100644 index 00000000000..862c42cdd22 --- /dev/null +++ b/boards/innblue/innblue22/doc/index.rst @@ -0,0 +1,144 @@ +.. _nrf9160_innblue22: + +nRF9160 INNBLUE22 +################# + +Overview +******** + +The nRF9160 innblue22 is a cellular IoT sensor development board, which +is based on the nRF9160 SiP, and features NB-IoT and LTE-M connectivity. + +.. figure:: img/nrf9160_innblue22.jpg + :align: center + :alt: nRF9160 innblue22 + + nRF9160 innblue22 (Credit: innblue) + +Hardware +******** + +The following parts are built into the board: + +* Accelerometer: ST LIS2DH12 +* CryptoElement: Atmel ATECC608a +* Humidity Sensor: ST HTS221 +* Qi charger: TI BQ51013 +* Battery fuel gauge: TI BQ27421 + +Supported Features +================== + +The innblue22 board configuration supports the following +hardware (as of nRF9160) features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +* LED1 ( red ) = P0.7 +* LED2 (green) = P0.6 +* LED3 ( blue) = P0.5 +* LED4 ( red ) = P0.4 + +Push buttons and Switches +------------------------- + +* BUTTON1 = P0.31 + +Security components +=================== + +- Implementation Defined Attribution Unit. The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Programming and Debugging +************************* + +innblue22 supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=innblue22`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=innblue22/nrf9160/ns``. +3. Merge the two binaries together. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=innblue22``. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9160 innblue22 +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: innblue22 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_common-pinctrl.dtsi b/boards/innblue/innblue22/innblue22_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9160_innblue22/nrf9160_innblue22_common-pinctrl.dtsi rename to boards/innblue/innblue22/innblue22_common-pinctrl.dtsi diff --git a/boards/innblue/innblue22/innblue22_common.dtsi b/boards/innblue/innblue22/innblue22_common.dtsi new file mode 100644 index 00000000000..de57fa1ced4 --- /dev/null +++ b/boards/innblue/innblue22/innblue22_common.dtsi @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "innblue22_common-pinctrl.dtsi" +#include + +/ { + model = "innblue v22 Dev Kit"; + compatible = "innblue,innblue22"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_1 { + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + label = "RGB red channel"; + }; + green_led: led_2 { + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + label = "RGB green channel"; + }; + blue_led: led_3 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + label = "RGB blue channel"; + }; + + mode_led: led_4 { + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + label = "mode red channel"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio0 31 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Button 0"; + zephyr,code = ; + }; + }; + + en_5v0_boost: enable-5v0-boost { + compatible = "regulator-fixed"; + regulator-name = "en_5v0_boost"; + enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <10000>; + regulator-boot-on; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + led3 = &mode_led; + sw0 = &button0; + rgb-pwm = &pwm0; + mode-pwm = &pwm1; + watchdog0 = &wdt0; + accel0 = &lis2dh12_accel; + }; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-1 = <&uart2_sleep>; + pinctrl-names = "default", "sleep"; +}; + + +&i2c2 { + compatible = "nordic,nrf-twim"; + status = "okay"; + + clock-frequency = ; + + pinctrl-0 = <&i2c2_default>; + pinctrl-1 = <&i2c2_sleep>; + pinctrl-names = "default", "sleep"; + bq27421@55 { + compatible = "ti,bq274xx"; + reg = <0x55>; + design-voltage = <3700>; + design-capacity = <1800>; + taper-current = <45>; + terminate-voltage = <3000>; + }; + + lis2dh12_accel: lis2dh12-accel@19 { + compatible = "st,lis2dh"; + reg = <0x19>; + irq-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + + hts221@5f { + compatible = "st,hts221"; + reg = <0x5f>; + drdy-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + }; + + lps22hb-press@5c { + compatible = "st,lps22hb-press"; + reg = <0x5c>; + }; + + ccs811: ccs811@5a { + compatible = "ams,ccs811"; + reg = <0x5a>; + }; + + bme680@76 { + compatible = "bosch,bme680"; + reg = <0x76>; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1_default>; + pinctrl-1 = <&pwm1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x10000>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + }; + slot0_ns_partition: partition@50000 { + label = "image-0-nonsecure"; + }; + slot1_partition: partition@80000 { + label = "image-1"; + }; + slot1_ns_partition: partition@c0000 { + label = "image-1-nonsecure"; + }; + /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ + storage_partition: partition@f8000 { + label = "storage"; + reg = <0x000f8000 0x00008000>; + }; + }; +}; + +/ { + /* SRAM allocated and used by the BSD library */ + sram0_bsd: memory@20010000 { + compatible = "mmio-sram"; + }; + + /* SRAM allocated to the Non-Secure image */ + sram0_ns: memory@20020000 { + compatible = "mmio-sram"; + }; +}; + +/* Include partition configuration file */ +#include "innblue22_partition_conf.dtsi" diff --git a/boards/innblue/innblue22/innblue22_nrf9160.dts b/boards/innblue/innblue22/innblue22_nrf9160.dts new file mode 100644 index 00000000000..c9c24c1090c --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "innblue22_common.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/boards/innblue/innblue22/innblue22_nrf9160.yaml b/boards/innblue/innblue22/innblue22_nrf9160.yaml new file mode 100644 index 00000000000..9bad5763319 --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160.yaml @@ -0,0 +1,14 @@ +identifier: innblue22/nrf9160 +name: nRF9160-INNBLUE22 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - i2c + - pwm + - watchdog diff --git a/boards/innblue/innblue22/innblue22_nrf9160_defconfig b/boards/innblue/innblue22/innblue22_nrf9160_defconfig new file mode 100644 index 00000000000..75e6bba7131 --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/innblue/innblue22/innblue22_nrf9160_ns.dts b/boards/innblue/innblue22/innblue22_nrf9160_ns.dts new file mode 100644 index 00000000000..93fa33ba334 --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160_ns.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "innblue22_common.dtsi" + +/ { + chosen { + zephyr,flash = &flash0; + zephyr,sram = &sram0_ns; + zephyr,code-partition = &slot0_ns_partition; + }; +}; diff --git a/boards/innblue/innblue22/innblue22_nrf9160_ns.yaml b/boards/innblue/innblue22/innblue22_nrf9160_ns.yaml new file mode 100644 index 00000000000..4542d90bad0 --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160_ns.yaml @@ -0,0 +1,14 @@ +identifier: innblue22/nrf9160/ns +name: nRF9160-INNBLUE22-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - i2c + - pwm + - watchdog diff --git a/boards/innblue/innblue22/innblue22_nrf9160_ns_defconfig b/boards/innblue/innblue22/innblue22_nrf9160_ns_defconfig new file mode 100644 index 00000000000..e27861efc3c --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160_ns_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_partition_conf.dtsi b/boards/innblue/innblue22/innblue22_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9160_innblue22/nrf9160_innblue22_partition_conf.dtsi rename to boards/innblue/innblue22/innblue22_partition_conf.dtsi diff --git a/boards/arm/nrf9151dk_nrf9151/pre_dt_board.cmake b/boards/innblue/innblue22/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/pre_dt_board.cmake rename to boards/innblue/innblue22/pre_dt_board.cmake diff --git a/boards/intel/adl/CMakeLists.txt b/boards/intel/adl/CMakeLists.txt new file mode 100644 index 00000000000..36ddcdf9d13 --- /dev/null +++ b/boards/intel/adl/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/intel/adl/Kconfig.defconfig b/boards/intel/adl/Kconfig.defconfig new file mode 100644 index 00000000000..518f0c01ee2 --- /dev/null +++ b/boards/intel/adl/Kconfig.defconfig @@ -0,0 +1,53 @@ +# Copyright (c) 2023-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BUILD_OUTPUT_STRIPPED + default y + +config MP_MAX_NUM_CPUS + default 2 + +# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1900000000 if APIC_TSC_DEADLINE_TIMER + default 1900000000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER +config APIC_TIMER_IRQ + default 24 +config APIC_TIMER_TSC_M + default 3 +config APIC_TIMER_TSC_N + default 249 +endif + +config ACPI + default y + +if ACPI +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 64000000 +config MAIN_STACK_SIZE + default 320000 + +if SHELL +config SHELL_STACK_SIZE + default 320000 +endif # SHELL +endif # ACPI + +if DMA +config DMA_64BIT + default y +config DMA_DW_HW_LLI + default n +config DMA_DW_CHANNEL_COUNT + default 2 +endif + +config UART_NS16550_INTEL_LPSS_DMA + default y + +config HAS_COVERAGE_SUPPORT + default y diff --git a/boards/intel/adl/Kconfig.intel_adl_crb b/boards/intel/adl/Kconfig.intel_adl_crb new file mode 100644 index 00000000000..81b9bd972b5 --- /dev/null +++ b/boards/intel/adl/Kconfig.intel_adl_crb @@ -0,0 +1,5 @@ +# Copyright (c) 2023-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ADL_CRB + select SOC_ALDER_LAKE diff --git a/boards/intel/adl/Kconfig.intel_adl_rvp b/boards/intel/adl/Kconfig.intel_adl_rvp new file mode 100644 index 00000000000..01eca2f55f4 --- /dev/null +++ b/boards/intel/adl/Kconfig.intel_adl_rvp @@ -0,0 +1,5 @@ +# Copyright (c) 2023-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ADL_RVP + select SOC_ALDER_LAKE diff --git a/boards/x86/intel_adl/board.cmake b/boards/intel/adl/board.cmake similarity index 100% rename from boards/x86/intel_adl/board.cmake rename to boards/intel/adl/board.cmake diff --git a/boards/intel/adl/board.yml b/boards/intel/adl/board.yml new file mode 100644 index 00000000000..fe51b63f813 --- /dev/null +++ b/boards/intel/adl/board.yml @@ -0,0 +1,9 @@ +boards: + - name: intel_adl_crb + vendor: intel + socs: + - name: alder_lake + - name: intel_adl_rvp + vendor: intel + socs: + - name: alder_lake diff --git a/boards/intel/adl/doc/index.rst b/boards/intel/adl/doc/index.rst new file mode 100644 index 00000000000..ac3a4c03076 --- /dev/null +++ b/boards/intel/adl/doc/index.rst @@ -0,0 +1,65 @@ +.. _intel_adl_n: + +Alder Lake N +############ + +Overview +******** +Alder Lake processor is a 64-bit multi-core processor built on 10-nanometer +technology process. + +Currently supported is N-processor line, Single Chip Platform that consists of +the Processor Die and Alder Lake N Platform Controller Hub (ADL-N PCH) Die on +the same package as Multi-Chip Package (MCP). + +Proposed branding for Adler Lake N is Intel Processor (N100,N200) and +Intel Core i3 (N300, N305). + +Alder Lake N Customer Reference Board (ADL-N CRB) and Alder Lake Reference +Validation Platform (ADL-N RVP) are example implementations of compact single +board computer with high performance for IoT edge devices. + +This board configuration enables kernel support for the Alder Lake N boards. + +Hardware +******** + +General information about the board can be found at the `INTEL_ADL`_ website. + +Connections and IOs +=================== + +Refer to the `INTEL_ADL`_ website for more information. + +Programming and Debugging +************************* +Use the following procedures for booting an image for an Alder Lake N CRB board. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application for Alder Lake N CRB: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: intel_adl_crb + :goals: build + + .. note:: + + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. + +Booting the Alder Lake N CRB Board using UEFI +============================================= + +.. include:: ../../../intel/common/efi_boot.rst + :start-after: start_include_here + +.. _INTEL_ADL: https://edc.intel.com/content/www/us/en/design/products/platforms/processor-and-core-i3-n-series-datasheet-volume-1-of-2/ diff --git a/boards/x86/intel_adl/intel_adl.dts b/boards/intel/adl/intel_adl.dts similarity index 100% rename from boards/x86/intel_adl/intel_adl.dts rename to boards/intel/adl/intel_adl.dts diff --git a/boards/x86/intel_adl/intel_adl_crb.dts b/boards/intel/adl/intel_adl_crb.dts similarity index 100% rename from boards/x86/intel_adl/intel_adl_crb.dts rename to boards/intel/adl/intel_adl_crb.dts diff --git a/boards/x86/intel_adl/intel_adl_crb.yaml b/boards/intel/adl/intel_adl_crb.yaml similarity index 100% rename from boards/x86/intel_adl/intel_adl_crb.yaml rename to boards/intel/adl/intel_adl_crb.yaml diff --git a/boards/x86/intel_adl/intel_adl_crb_defconfig b/boards/intel/adl/intel_adl_crb_defconfig similarity index 81% rename from boards/x86/intel_adl/intel_adl_crb_defconfig rename to boards/intel/adl/intel_adl_crb_defconfig index 5287bfcacc0..fb9be2a4994 100644 --- a/boards/x86/intel_adl/intel_adl_crb_defconfig +++ b/boards/intel/adl/intel_adl_crb_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ALDER_LAKE=y -CONFIG_BOARD_INTEL_ADL_CRB=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/intel_adl/intel_adl_rvp.dts b/boards/intel/adl/intel_adl_rvp.dts similarity index 100% rename from boards/x86/intel_adl/intel_adl_rvp.dts rename to boards/intel/adl/intel_adl_rvp.dts diff --git a/boards/x86/intel_adl/intel_adl_rvp.yaml b/boards/intel/adl/intel_adl_rvp.yaml similarity index 100% rename from boards/x86/intel_adl/intel_adl_rvp.yaml rename to boards/intel/adl/intel_adl_rvp.yaml diff --git a/boards/x86/intel_adl/intel_adl_rvp_defconfig b/boards/intel/adl/intel_adl_rvp_defconfig similarity index 81% rename from boards/x86/intel_adl/intel_adl_rvp_defconfig rename to boards/intel/adl/intel_adl_rvp_defconfig index 0f6ed718268..fb9be2a4994 100644 --- a/boards/x86/intel_adl/intel_adl_rvp_defconfig +++ b/boards/intel/adl/intel_adl_rvp_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ALDER_LAKE=y -CONFIG_BOARD_INTEL_ADL_RVP=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/intel/adsp/Kconfig.defconfig b/boards/intel/adsp/Kconfig.defconfig new file mode 100644 index 00000000000..eafedb0c550 --- /dev/null +++ b/boards/intel/adsp/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2020-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if DAI_INTEL_SSP + +config DAI_SSP_HAS_POWER_CONTROL + def_bool y + +endif diff --git a/boards/intel/adsp/Kconfig.intel_adsp b/boards/intel/adsp/Kconfig.intel_adsp new file mode 100644 index 00000000000..2e4c9844720 --- /dev/null +++ b/boards/intel/adsp/Kconfig.intel_adsp @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ADSP + select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25 + select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25_TGPH + select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM + select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL diff --git a/boards/intel/adsp/board.cmake b/boards/intel/adsp/board.cmake new file mode 100644 index 00000000000..bcdfc328646 --- /dev/null +++ b/boards/intel/adsp/board.cmake @@ -0,0 +1,42 @@ +# Copyright (c) 2022-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_INTEL_ADSP_CAVS25 OR CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH) + + if($ENV{CAVS_OLD_FLASHER}) + board_set_flasher_ifnset(misc-flasher) + board_finalize_runner_args(misc-flasher) + endif() + + board_set_flasher_ifnset(intel_adsp) + + set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in cavs25/board.cmake") + + if(CONFIG_BOARD_INTEL_ADSP_CAVS25) + board_set_rimage_target(tgl) + endif() + + if(CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH) + board_set_rimage_target(tgl-h) + endif() + + board_finalize_runner_args(intel_adsp) + +elseif(CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM) + + board_set_rimage_target(mtl) + + set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace15_mtpm/board.cmake") + + board_finalize_runner_args(intel_adsp) + +elseif(CONFIG_BOARD_INTEL_ADSP_ACE20_LNL) + + set(SUPPORTED_EMU_PLATFORMS acesim) + + board_set_rimage_target(lnl) + + set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace20_lnl/board.cmake") + +endif() diff --git a/boards/intel/adsp/board.yml b/boards/intel/adsp/board.yml new file mode 100644 index 00000000000..9295ae0c3eb --- /dev/null +++ b/boards/intel/adsp/board.yml @@ -0,0 +1,9 @@ +boards: + - name: intel_adsp + vendor: intel + socs: + - name: cavs25 + variants: + - name: 'tgph' + - name: ace15_mtpm + - name: ace20_lnl diff --git a/boards/xtensa/intel_adsp_cavs25/doc/chromebooks_adsp.rst b/boards/intel/adsp/doc/chromebooks_adsp.rst similarity index 98% rename from boards/xtensa/intel_adsp_cavs25/doc/chromebooks_adsp.rst rename to boards/intel/adsp/doc/chromebooks_adsp.rst index 867df7b8389..a89d2b75881 100644 --- a/boards/xtensa/intel_adsp_cavs25/doc/chromebooks_adsp.rst +++ b/boards/intel/adsp/doc/chromebooks_adsp.rst @@ -1,5 +1,3 @@ -:orphan: - .. _zephyr-audio-dsp-development-on-chromebooks: Zephyr Audio DSP Development on Chromebooks @@ -366,7 +364,7 @@ the Crouton environment installed above. Copy them: .. code-block:: console - dev$ scp soc/xtensa/intel_adsp/tools/cavstool.py user@crouton: + dev$ scp soc/intel/intel_adsp/tools/cavstool.py user@crouton: Then start the service in the Crouton environment: @@ -386,7 +384,7 @@ a "zephyr.ri" file to be copied to the device. .. code-block:: console - dev$ west build -b intel_adsp_cavs25 samples/hello_world + dev$ west build -b intel_adsp/cavs25 samples/hello_world dev$ west sign --tool-data=~/rimage/config -t ~/rimage/rimage -- \ -k $ZEPHYR_BASE/../modules/audio/sof/keys/otc_private_key_3k.pem @@ -401,7 +399,7 @@ the logging script. .. code-block:: console dev$ west flash --remote-host crouton - Hello World! intel_adsp_cavs25 + Hello World! intel_adsp Misc References *************** diff --git a/boards/intel/adsp/doc/index.rst b/boards/intel/adsp/doc/index.rst new file mode 100644 index 00000000000..3145b7637cd --- /dev/null +++ b/boards/intel/adsp/doc/index.rst @@ -0,0 +1,11 @@ +.. _boards-intel-adsp: + +Intel ADSP +########## + +.. toctree:: + + intel_adsp_generic + chromebooks_adsp + intel_adsp_cavs25 + intel_adsp_ace15_mtpm diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/doc/index.rst b/boards/intel/adsp/doc/intel_adsp_ace15_mtpm.rst similarity index 100% rename from boards/xtensa/intel_adsp_ace15_mtpm/doc/index.rst rename to boards/intel/adsp/doc/intel_adsp_ace15_mtpm.rst diff --git a/boards/xtensa/intel_adsp_cavs25/doc/index.rst b/boards/intel/adsp/doc/intel_adsp_cavs25.rst similarity index 100% rename from boards/xtensa/intel_adsp_cavs25/doc/index.rst rename to boards/intel/adsp/doc/intel_adsp_cavs25.rst diff --git a/boards/xtensa/intel_adsp_cavs25/doc/intel_adsp_generic.rst b/boards/intel/adsp/doc/intel_adsp_generic.rst similarity index 90% rename from boards/xtensa/intel_adsp_cavs25/doc/intel_adsp_generic.rst rename to boards/intel/adsp/doc/intel_adsp_generic.rst index 6b0a4526fe4..e0a8edf1ba2 100644 --- a/boards/xtensa/intel_adsp_cavs25/doc/intel_adsp_generic.rst +++ b/boards/intel/adsp/doc/intel_adsp_generic.rst @@ -1,5 +1,3 @@ -:orphan: - .. _intel_adsp_generic: Intel ADSP cAVS and ACE @@ -115,7 +113,7 @@ Build as usual. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: intel_adsp_cavs25 + :board: intel_adsp/cavs25 :goals: build Signing @@ -141,7 +139,7 @@ undocumented rimage precedence rules it's best to use only one way at a time. - For board-specific needs you can define WEST_SIGN_OPTS in ``boards/my/board/board.cmake``, see example in - ``soc/xtensa/intel_adsp/common/CMakeLists.txt`` + ``soc/intel/adsp/common/CMakeLists.txt`` Starting with Zephyr 3.6.0, ``west flash`` does not invoke ``west sign`` anymore and you cannot pass rimage parameters to ``west flash`` anymore. To @@ -162,16 +160,16 @@ this point onward, we will refer to the board as the "remote host" and your development machine as the "local host". Copy the below scripts to the cAVS board. -:zephyr_file:`soc/xtensa/intel_adsp/tools/remote-fw-service.py` will receive +:zephyr_file:`soc/intel/intel_adsp/tools/remote-fw-service.py` will receive the binary sent over the network by West and invoke -:zephyr_file:`soc/xtensa/intel_adsp/tools/cavstool.py` (referred to as the +:zephyr_file:`soc/intel/intel_adsp/tools/cavstool.py` (referred to as the "cAVS tool"), which performs the flash and captures the log. Start :file:`remote-fw-service.py`. .. code-block:: console - scp -r $ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstool.py username@remotehostname - scp -r $ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/remote-fw-service.py username@remotehostname + scp -r $ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstool.py username@remotehostname + scp -r $ZEPHYR_BASE/soc/intel/intel_adsp/tools/remote-fw-service.py username@remotehostname ssh username@remotehostname sudo ./remote-fw-service.py @@ -179,7 +177,7 @@ the binary sent over the network by West and invoke communicate. It forwards logs collected by :file:`cavstool.py` on port 9999 (referred to as its "log port") and services requests on port 10000 (its "requests port"). When you run West or Twister on your local host, -it sends requests using the :zephyr_file:`soc/xtensa/intel_adsp/tools/cavstool_client.py` +it sends requests using the :zephyr_file:`soc/intel/intel_adsp/tools/cavstool_client.py` script (referred to as "cAVS tool client"). It also uses ports 9999 and 10000 on your local host, so be sure those ports are free. @@ -193,7 +191,7 @@ Running tests with Twister is slightly more complicated. .. code-block:: console - twister -p intel_adsp_cavs25 --device-testing --device-serial-pty="$ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstool_client.py,-s,remotehostname,-l" --west-flash="--remote-host=remotehostname" -T samples/hello_world + twister -p intel_adsp/cavs25 --device-testing --device-serial-pty="$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstool_client.py,-s,remotehostname,-l" --west-flash="--remote-host=remotehostname" -T samples/hello_world If your network is set up such that the TCP connection from :file:`cavstool_client.py` to :file:`remote-fw-service.py` is forwarded through @@ -204,14 +202,14 @@ the port numbers to the intermediate host name. .. code-block:: console west flash --remote-host intermediatehost:reqport --pty remotehostname:logport - twister -p intel_adsp_cavs25 --device-testing --device-serial-pty="$ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstool_client.py,-s,remotehostname:logport,-l" --west-flash="--remote-host=remotehostname:reqport" -T samples/hello_world + twister -p intel_adsp/cavs25 --device-testing --device-serial-pty="$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstool_client.py,-s,remotehostname:logport,-l" --west-flash="--remote-host=remotehostname:reqport" -T samples/hello_world You can also save this information to a hardware map file and pass that to Twister. .. code-block:: console - twister -p intel_adsp_cavs25 --hardware-map cavs.map --device-testing -T samples/hello_world + twister -p intel_adsp/cavs25 --hardware-map cavs.map --device-testing -T samples/hello_world Here's a sample ``cavs.map``: @@ -219,10 +217,10 @@ Here's a sample ``cavs.map``: - connected: true id: None - platform: intel_adsp_cavs25 + platform: intel_adsp/cavs25 product: None runner: intel_adsp - serial_pty: "/home/zephyrus/zephyrproject/zephyr/soc/xtensa/intel_adsp/tools/cavstool_client.py,-s,remotehostname:logport,-l" + serial_pty: "/home/zephyrus/zephyrproject/zephyr/soc/intel/intel_adsp/tools/cavstool_client.py,-s,remotehostname:logport,-l" runner_params: - --remote-host=remotehostname:reqport @@ -247,7 +245,7 @@ You should see the following at the end of the log if you are successful: .. code-block:: console ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! intel_adsp_cavs25 + Hello World! intel_adsp Flashing to ACE-based ADSP -------------------------- diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm.dts b/boards/intel/adsp/intel_adsp_ace15_mtpm.dts similarity index 100% rename from boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm.dts rename to boards/intel/adsp/intel_adsp_ace15_mtpm.dts diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm.yaml b/boards/intel/adsp/intel_adsp_ace15_mtpm.yaml similarity index 84% rename from boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm.yaml rename to boards/intel/adsp/intel_adsp_ace15_mtpm.yaml index 9493e4c08da..3449cda35f7 100644 --- a/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm.yaml +++ b/boards/intel/adsp/intel_adsp_ace15_mtpm.yaml @@ -1,4 +1,4 @@ -identifier: intel_adsp_ace15_mtpm +identifier: intel_adsp/ace15_mtpm name: ACE 1.5 MTL M Audio DSP type: mcu arch: xtensa diff --git a/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig b/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig new file mode 100644 index 00000000000..2237dfb963a --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_MM_DRV=y +CONFIG_CRYPTO=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.dts b/boards/intel/adsp/intel_adsp_ace20_lnl.dts similarity index 100% rename from boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.dts rename to boards/intel/adsp/intel_adsp_ace20_lnl.dts diff --git a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml b/boards/intel/adsp/intel_adsp_ace20_lnl.yaml similarity index 85% rename from boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml rename to boards/intel/adsp/intel_adsp_ace20_lnl.yaml index 693f3ad2ce6..47a02563654 100644 --- a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml +++ b/boards/intel/adsp/intel_adsp_ace20_lnl.yaml @@ -1,4 +1,4 @@ -identifier: intel_adsp_ace20_lnl +identifier: intel_adsp/ace20_lnl name: ACE 2.0 LNL Audio DSP type: mcu arch: xtensa diff --git a/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig b/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig new file mode 100644 index 00000000000..3d897eb9673 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_MM_DRV=y +CONFIG_MM_DRV_INTEL_ADSP_MTL_TLB=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.dts b/boards/intel/adsp/intel_adsp_cavs25.dts similarity index 100% rename from boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.dts rename to boards/intel/adsp/intel_adsp_cavs25.dts diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.yaml b/boards/intel/adsp/intel_adsp_cavs25.yaml similarity index 87% rename from boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.yaml rename to boards/intel/adsp/intel_adsp_cavs25.yaml index 8d175cbc621..79982b426e7 100644 --- a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.yaml +++ b/boards/intel/adsp/intel_adsp_cavs25.yaml @@ -1,4 +1,4 @@ -identifier: intel_adsp_cavs25 +identifier: intel_adsp/cavs25 name: cAVS 2.5 Audio DSP (converged Audio Voice and Speech) type: mcu arch: xtensa diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.dts b/boards/intel/adsp/intel_adsp_cavs25_cavs25_tgph.dts similarity index 100% rename from boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.dts rename to boards/intel/adsp/intel_adsp_cavs25_cavs25_tgph.dts diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig b/boards/intel/adsp/intel_adsp_cavs25_defconfig similarity index 76% rename from boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig rename to boards/intel/adsp/intel_adsp_cavs25_defconfig index 18a58706176..24443bce131 100644 --- a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig +++ b/boards/intel/adsp/intel_adsp_cavs25_defconfig @@ -1,11 +1,9 @@ +# Copyright (c) 2020-2024 Intel Corporation +# # SPDX-License-Identifier: Apache-2.0 CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y -CONFIG_SOC_INTEL_CAVS_V25=y -CONFIG_BOARD_INTEL_ADSP_CAVS25=y - CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.yaml b/boards/intel/adsp/intel_adsp_cavs25_tgph.yaml similarity index 86% rename from boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.yaml rename to boards/intel/adsp/intel_adsp_cavs25_tgph.yaml index f11256de9bf..db3d32fad8f 100644 --- a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.yaml +++ b/boards/intel/adsp/intel_adsp_cavs25_tgph.yaml @@ -1,4 +1,4 @@ -identifier: intel_adsp_cavs25_tgph +identifier: intel_adsp/cavs25/tgph name: cAVS 2.5 Audio DSP for Tiger Lake H PCH (Converged Audio Voice and Speech) type: mcu arch: xtensa diff --git a/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig new file mode 100644 index 00000000000..a0b72230091 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2020-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_CORE_COUNT=2 diff --git a/boards/intel/adsp/pre_dt_board.cmake b/boards/intel/adsp/pre_dt_board.cmake new file mode 100644 index 00000000000..9a917df707b --- /dev/null +++ b/boards/intel/adsp/pre_dt_board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if(NOT CONFIG_BOARD_INTEL_ADSP_ACE20_LNL) + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - dmic0: dmic0@10000 & dmic1: dmic1@10000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") + +endif() diff --git a/boards/x86/common/efi_boot.rst b/boards/intel/common/efi_boot.rst similarity index 100% rename from boards/x86/common/efi_boot.rst rename to boards/intel/common/efi_boot.rst diff --git a/boards/x86/common/net_boot.rst b/boards/intel/common/net_boot.rst similarity index 100% rename from boards/x86/common/net_boot.rst rename to boards/intel/common/net_boot.rst diff --git a/boards/x86/common/scripts/build_grub.sh b/boards/intel/common/scripts/build_grub.sh similarity index 100% rename from boards/x86/common/scripts/build_grub.sh rename to boards/intel/common/scripts/build_grub.sh diff --git a/boards/intel/ehl/CMakeLists.txt b/boards/intel/ehl/CMakeLists.txt new file mode 100644 index 00000000000..36ddcdf9d13 --- /dev/null +++ b/boards/intel/ehl/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/intel/ehl/Kconfig.defconfig b/boards/intel/ehl/Kconfig.defconfig new file mode 100644 index 00000000000..9e7dcf48a04 --- /dev/null +++ b/boards/intel/ehl/Kconfig.defconfig @@ -0,0 +1,39 @@ +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + + +config BUILD_OUTPUT_STRIPPED + default y + +config MP_MAX_NUM_CPUS + default 2 + +if BOARD_INTEL_EHL_CRB_ELKHART_LAKE_SBL +config SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN + depends on SHELL_BACKEND_SERIAL + default n +endif + +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 2097152 + depends on ACPI + +# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1900000000 if APIC_TSC_DEADLINE_TIMER + default 1900000000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER +config APIC_TIMER_IRQ + default 24 +config APIC_TIMER_TSC_M + default 3 +config APIC_TIMER_TSC_N + default 249 +endif + +if BOARD_INTEL_EHL_CRB_ELKHART_LAKE + config HAS_COVERAGE_SUPPORT + default y +endif diff --git a/boards/intel/ehl/Kconfig.intel_ehl_crb b/boards/intel/ehl/Kconfig.intel_ehl_crb new file mode 100644 index 00000000000..1d99891fe58 --- /dev/null +++ b/boards/intel/ehl/Kconfig.intel_ehl_crb @@ -0,0 +1,5 @@ +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_EHL_CRB + select SOC_ELKHART_LAKE diff --git a/boards/x86/intel_ehl/board.cmake b/boards/intel/ehl/board.cmake similarity index 100% rename from boards/x86/intel_ehl/board.cmake rename to boards/intel/ehl/board.cmake diff --git a/boards/intel/ehl/board.yml b/boards/intel/ehl/board.yml new file mode 100644 index 00000000000..5f8d3cafa1b --- /dev/null +++ b/boards/intel/ehl/board.yml @@ -0,0 +1,7 @@ +board: + name: intel_ehl_crb + vendor: intel + socs: + - name: elkhart_lake + variants: + - name: 'sbl' diff --git a/boards/intel/ehl/doc/index.rst b/boards/intel/ehl/doc/index.rst new file mode 100644 index 00000000000..16bf6c2bd22 --- /dev/null +++ b/boards/intel/ehl/doc/index.rst @@ -0,0 +1,89 @@ +.. _intel_ehl_crb: + +Elkhart Lake CRB +################ + +Overview +******** +Elkhart Lake Reference Board (EHL CRB) is an example implementation of a +compact single board computer with high performance for IoT edge devices. + +This board configuration enables kernel support for the `EHL`_ board. + +.. note:: + This board configuration works on the variant of `EHL`_ + boards containing Intel |reg| Atom |trade| SoC. + +Hardware +******** + +General information about the board can be found at the `EHL`_ website. + +.. include:: ../../../../soc/intel/elkhart_lake/doc/supported_features.txt + + +Connections and IOs +=================== + +Refer to the `EHL`_ website for more information. + +Programming and Debugging +************************* +Use the following procedures for booting an image on a EHL CRB board. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application on Elkhart Lake CRB: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: intel_ehl_crb + :goals: build + + .. note:: + + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. + +Booting the Elkhart Lake CRB Board using UEFI +============================================= + +.. include:: ../../../intel/common/efi_boot.rst + :start-after: start_include_here + +Booting the Elkhart Lake CRB Board over network +=============================================== + +.. include:: ../../../intel/common/net_boot.rst + :start-after: start_include_here + +.. note:: + To enable PXE boot for Elkhart Lake CRB board do the following: + + #. Enable boot from PXE. Go to EFI shell and make sure that the first boot + option is ``UEFI PXEv4``. + + .. code-block:: console + + Shell> bcfg boot dump + Option: 00. Variable: Boot0007 + Desc - UEFI PXEv4 (MAC:6805CABC1997) + DevPath - PciRoot(0x0)/Pci(0x1C,0x0)/Pci(0x0,0x0)/MAC(6805CABC1997,0x0)/IPv4(0.0.0.0) + Optional- Y + ... + + #. If UEFI PXEv4 is not the first boot option use ``bcfg boot mv`` command to + change boot order + + .. code-block:: console + + Shell> bcfg boot mv 7 0 + +.. _EHL: https://www.intel.com/content/www/us/en/products/docs/processors/embedded/enhanced-for-iot-platform-brief.html diff --git a/boards/x86/intel_ehl/intel_ehl_crb.dts b/boards/intel/ehl/intel_ehl_crb.dts similarity index 100% rename from boards/x86/intel_ehl/intel_ehl_crb.dts rename to boards/intel/ehl/intel_ehl_crb.dts diff --git a/boards/x86/intel_ehl/intel_ehl_crb.yaml b/boards/intel/ehl/intel_ehl_crb.yaml similarity index 100% rename from boards/x86/intel_ehl/intel_ehl_crb.yaml rename to boards/intel/ehl/intel_ehl_crb.yaml diff --git a/boards/x86/intel_ehl/intel_ehl_crb_defconfig b/boards/intel/ehl/intel_ehl_crb_defconfig similarity index 80% rename from boards/x86/intel_ehl/intel_ehl_crb_defconfig rename to boards/intel/ehl/intel_ehl_crb_defconfig index e25760a5a05..ba1c681c4cf 100644 --- a/boards/x86/intel_ehl/intel_ehl_crb_defconfig +++ b/boards/intel/ehl/intel_ehl_crb_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ELKHART_LAKE=y -CONFIG_BOARD_INTEL_EHL_CRB=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/intel_ehl/intel_ehl_crb_sbl.dts b/boards/intel/ehl/intel_ehl_crb_sbl.dts similarity index 100% rename from boards/x86/intel_ehl/intel_ehl_crb_sbl.dts rename to boards/intel/ehl/intel_ehl_crb_sbl.dts diff --git a/boards/x86/intel_ehl/intel_ehl_crb_sbl.yaml b/boards/intel/ehl/intel_ehl_crb_sbl.yaml similarity index 78% rename from boards/x86/intel_ehl/intel_ehl_crb_sbl.yaml rename to boards/intel/ehl/intel_ehl_crb_sbl.yaml index 52cfa670ae6..3493ed0611d 100644 --- a/boards/x86/intel_ehl/intel_ehl_crb_sbl.yaml +++ b/boards/intel/ehl/intel_ehl_crb_sbl.yaml @@ -1,4 +1,4 @@ -identifier: intel_ehl_crb_sbl +identifier: intel_ehl_crb/elkhart_lake/sbl name: Elkhart Lake CRB with Slim Bootloader type: mcu arch: x86 diff --git a/boards/x86/intel_ehl/intel_ehl_crb_sbl_defconfig b/boards/intel/ehl/intel_ehl_crb_sbl_defconfig similarity index 75% rename from boards/x86/intel_ehl/intel_ehl_crb_sbl_defconfig rename to boards/intel/ehl/intel_ehl_crb_sbl_defconfig index 1ccff387dc1..29055f28717 100644 --- a/boards/x86/intel_ehl/intel_ehl_crb_sbl_defconfig +++ b/boards/intel/ehl/intel_ehl_crb_sbl_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ELKHART_LAKE=y -CONFIG_BOARD_INTEL_EHL_CRB_SBL=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/intel/index.rst b/boards/intel/index.rst new file mode 100644 index 00000000000..800c4e5bd51 --- /dev/null +++ b/boards/intel/index.rst @@ -0,0 +1,10 @@ +.. _boards-intel: + +Intel Corporation +################# + +.. toctree:: + :maxdepth: 1 + :glob: + + */**/index diff --git a/boards/intel/ish/Kconfig.defconfig b/boards/intel/ish/Kconfig.defconfig new file mode 100644 index 00000000000..fdedc70fd29 --- /dev/null +++ b/boards/intel/ish/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2023 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +if TEST +config TEST_EXTRA_STACK_SIZE + default 1024 +endif # TEST + +config SYS_CLOCK_TICKS_PER_SEC + default 2048 if HPET_TIMER # HPET is 32768 HZ diff --git a/boards/intel/ish/Kconfig.intel_ish_5_4_1 b/boards/intel/ish/Kconfig.intel_ish_5_4_1 new file mode 100644 index 00000000000..62ef1213675 --- /dev/null +++ b/boards/intel/ish/Kconfig.intel_ish_5_4_1 @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ISH_5_4_1 + select SOC_INTEL_ISH_5_4_1 diff --git a/boards/intel/ish/Kconfig.intel_ish_5_6_0 b/boards/intel/ish/Kconfig.intel_ish_5_6_0 new file mode 100644 index 00000000000..4c8fe37972c --- /dev/null +++ b/boards/intel/ish/Kconfig.intel_ish_5_6_0 @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ISH_5_6_0 + select SOC_INTEL_ISH_5_6_0 diff --git a/boards/intel/ish/Kconfig.intel_ish_5_8_0 b/boards/intel/ish/Kconfig.intel_ish_5_8_0 new file mode 100644 index 00000000000..122fc3b30ba --- /dev/null +++ b/boards/intel/ish/Kconfig.intel_ish_5_8_0 @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ISH_5_8_0 + select SOC_INTEL_ISH_5_8_0 diff --git a/boards/intel/ish/board.yml b/boards/intel/ish/board.yml new file mode 100644 index 00000000000..ee7c4661800 --- /dev/null +++ b/boards/intel/ish/board.yml @@ -0,0 +1,16 @@ +boards: + + - name: intel_ish_5_4_1 + vendor: intel + socs: + - name: intel_ish_5_4_1 + + - name: intel_ish_5_6_0 + vendor: intel + socs: + - name: intel_ish_5_6_0 + + - name: intel_ish_5_8_0 + vendor: intel + socs: + - name: intel_ish_5_8_0 diff --git a/boards/intel/ish/doc/index.rst b/boards/intel/ish/doc/index.rst new file mode 100644 index 00000000000..d9c3c179b23 --- /dev/null +++ b/boards/intel/ish/doc/index.rst @@ -0,0 +1,79 @@ +.. _intel_ish: + +Intel Integrated Sensor Hub (ISH) +################################# + +Overview +******** +Intel Integrated Sensor Hub (ISH) is a lower-power/always-on co-processor +inside many Intel Processors. It helps offload sensor processing tasks from +the core processor for better power saving. + +Hardware +******** + +- LMT MinuteIA Core: + + - 16KB instruction cache and 16KB data cache. + - 640KB SRAM space for code and data - implemented as L2 SRAM. + - 8KB AON RF space for code resident during deep D0i2/3 PG states. + +- Interface-to-Sensor peripherals (I2C, SPI, UART, I3C, GPIO, DMA). +- Inter Process Communications (IPC) to core processor and other IP processors. + +.. include:: ../../../../soc/intel/intel_ish/doc/supported_features.txt + +Programming and Debugging +************************* +Use the following procedures for booting an ISH image on a ADL RVP board +for Chrome. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application for ISH 5.4.1 on Intel ADL Processor: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: intel_ish_5_4_1 + :goals: build + + .. note:: + + A Zephyr image file named :file:`ish_fw.bin` is automatically + created in the build directory after the application is built. + +Run ish_fw.bin on ADL RVP board for Chrome +========================================== + +- Power on the ADL RVP board. +- Log in Chrome OS. (Note: the user must have root access right, see `Developer Mode`_) +- Re-mount the root filesystem as read-write: + +.. code-block:: console + + $ mount -o remount,rw / + +- If re-mount fails, execute below commands to Remove rootfs verification: + +.. code-block:: console + + $ /usr/share/vboot/bin/make_dev_ssd.sh --remove_rootfs_verification --partitions + $ reboot + +- Go to the ISH firmware direcoty: + +.. code-block:: console + + $ cd /lib/firmware/intel + +- Relace the file adlrvp_ish.bin with zephyr image built out, ish_fw.bin. +- Reboot, then observe Zephyr log output via ISH UART0. + +.. _Developer Mode: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_mode.md diff --git a/boards/x86/intel_ish/intel_ish_5_4_1.dts b/boards/intel/ish/intel_ish_5_4_1.dts similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_4_1.dts rename to boards/intel/ish/intel_ish_5_4_1.dts diff --git a/boards/x86/intel_ish/intel_ish_5_4_1.yaml b/boards/intel/ish/intel_ish_5_4_1.yaml similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_4_1.yaml rename to boards/intel/ish/intel_ish_5_4_1.yaml diff --git a/boards/intel/ish/intel_ish_5_4_1_defconfig b/boards/intel/ish/intel_ish_5_4_1_defconfig new file mode 100644 index 00000000000..de4d5660e15 --- /dev/null +++ b/boards/intel/ish/intel_ish_5_4_1_defconfig @@ -0,0 +1,10 @@ +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +# uart & console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/x86/intel_ish/intel_ish_5_6_0.dts b/boards/intel/ish/intel_ish_5_6_0.dts similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_6_0.dts rename to boards/intel/ish/intel_ish_5_6_0.dts diff --git a/boards/x86/intel_ish/intel_ish_5_6_0.yaml b/boards/intel/ish/intel_ish_5_6_0.yaml similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_6_0.yaml rename to boards/intel/ish/intel_ish_5_6_0.yaml diff --git a/boards/intel/ish/intel_ish_5_6_0_defconfig b/boards/intel/ish/intel_ish_5_6_0_defconfig new file mode 100644 index 00000000000..de4d5660e15 --- /dev/null +++ b/boards/intel/ish/intel_ish_5_6_0_defconfig @@ -0,0 +1,10 @@ +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +# uart & console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/x86/intel_ish/intel_ish_5_8_0.dts b/boards/intel/ish/intel_ish_5_8_0.dts similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_8_0.dts rename to boards/intel/ish/intel_ish_5_8_0.dts diff --git a/boards/x86/intel_ish/intel_ish_5_8_0.yaml b/boards/intel/ish/intel_ish_5_8_0.yaml similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_8_0.yaml rename to boards/intel/ish/intel_ish_5_8_0.yaml diff --git a/boards/intel/ish/intel_ish_5_8_0_defconfig b/boards/intel/ish/intel_ish_5_8_0_defconfig new file mode 100644 index 00000000000..de4d5660e15 --- /dev/null +++ b/boards/intel/ish/intel_ish_5_8_0_defconfig @@ -0,0 +1,10 @@ +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +# uart & console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/intel/niosv_g/Kconfig.niosv_g b/boards/intel/niosv_g/Kconfig.niosv_g new file mode 100644 index 00000000000..2d07c1b5e15 --- /dev/null +++ b/boards/intel/niosv_g/Kconfig.niosv_g @@ -0,0 +1,8 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NIOSV_G + select SOC_NIOSV_G + help + Intel FPGA Nios V/g General Purpose Processor diff --git a/boards/intel/niosv_g/board.yml b/boards/intel/niosv_g/board.yml new file mode 100644 index 00000000000..7f6cc30ce62 --- /dev/null +++ b/boards/intel/niosv_g/board.yml @@ -0,0 +1,4 @@ +board: + name: niosv_g + socs: + - name: niosv_g diff --git a/boards/riscv/niosv_g/doc/index.rst b/boards/intel/niosv_g/doc/index.rst similarity index 100% rename from boards/riscv/niosv_g/doc/index.rst rename to boards/intel/niosv_g/doc/index.rst diff --git a/boards/riscv/niosv_g/niosv_g.dts b/boards/intel/niosv_g/niosv_g.dts similarity index 100% rename from boards/riscv/niosv_g/niosv_g.dts rename to boards/intel/niosv_g/niosv_g.dts diff --git a/boards/riscv/niosv_g/niosv_g.yaml b/boards/intel/niosv_g/niosv_g.yaml similarity index 100% rename from boards/riscv/niosv_g/niosv_g.yaml rename to boards/intel/niosv_g/niosv_g.yaml diff --git a/boards/intel/niosv_g/niosv_g_defconfig b/boards/intel/niosv_g/niosv_g_defconfig new file mode 100644 index 00000000000..27dd451aaf5 --- /dev/null +++ b/boards/intel/niosv_g/niosv_g_defconfig @@ -0,0 +1,9 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_PRINTK=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n diff --git a/boards/intel/niosv_m/Kconfig.niosv_m b/boards/intel/niosv_m/Kconfig.niosv_m new file mode 100644 index 00000000000..c7474b4b926 --- /dev/null +++ b/boards/intel/niosv_m/Kconfig.niosv_m @@ -0,0 +1,8 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NIOSV_M + select SOC_NIOSV_M + help + Intel FPGA NIOSV Microcontroller Core Processor diff --git a/boards/intel/niosv_m/board.yml b/boards/intel/niosv_m/board.yml new file mode 100644 index 00000000000..a77efa39ff1 --- /dev/null +++ b/boards/intel/niosv_m/board.yml @@ -0,0 +1,4 @@ +board: + name: niosv_m + socs: + - name: niosv_m diff --git a/boards/riscv/niosv_m/doc/index.rst b/boards/intel/niosv_m/doc/index.rst similarity index 100% rename from boards/riscv/niosv_m/doc/index.rst rename to boards/intel/niosv_m/doc/index.rst diff --git a/boards/riscv/niosv_m/niosv_m.dts b/boards/intel/niosv_m/niosv_m.dts similarity index 100% rename from boards/riscv/niosv_m/niosv_m.dts rename to boards/intel/niosv_m/niosv_m.dts diff --git a/boards/riscv/niosv_m/niosv_m.yaml b/boards/intel/niosv_m/niosv_m.yaml similarity index 100% rename from boards/riscv/niosv_m/niosv_m.yaml rename to boards/intel/niosv_m/niosv_m.yaml diff --git a/boards/intel/niosv_m/niosv_m_defconfig b/boards/intel/niosv_m/niosv_m_defconfig new file mode 100644 index 00000000000..9ac86fe8e52 --- /dev/null +++ b/boards/intel/niosv_m/niosv_m_defconfig @@ -0,0 +1,10 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_PRINTK=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_ALTERA_JTAG=y +CONFIG_XIP=n diff --git a/boards/intel/rpl/CMakeLists.txt b/boards/intel/rpl/CMakeLists.txt new file mode 100644 index 00000000000..36ddcdf9d13 --- /dev/null +++ b/boards/intel/rpl/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/intel/rpl/Kconfig.defconfig b/boards/intel/rpl/Kconfig.defconfig new file mode 100644 index 00000000000..ca8a7742688 --- /dev/null +++ b/boards/intel/rpl/Kconfig.defconfig @@ -0,0 +1,59 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + + +config BUILD_OUTPUT_STRIPPED + default y + +config MP_MAX_NUM_CPUS + default 2 + +# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1900000000 if APIC_TSC_DEADLINE_TIMER + default 1900000000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER +config APIC_TIMER_IRQ + default 24 +config APIC_TIMER_TSC_M + default 3 +config APIC_TIMER_TSC_N + default 249 +endif + +config ACPI + default y + +if ACPI +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 64000000 +config MAIN_STACK_SIZE + default 320000 + +if SHELL +config SHELL_STACK_SIZE + default 320000 +endif # SHELL +endif # ACPI + +if DMA +config DMA_64BIT + default y +config DMA_DW_HW_LLI + default n +config DMA_DW_CHANNEL_COUNT + default 2 +endif + +config UART_NS16550_INTEL_LPSS_DMA + default y if BOARD_INTEL_RPL_S_CRB + +if SHELL +config SHELL_STACK_SIZE + default 320000 +endif + +config HAS_COVERAGE_SUPPORT + default y diff --git a/boards/intel/rpl/Kconfig.intel_rpl_p_crb b/boards/intel/rpl/Kconfig.intel_rpl_p_crb new file mode 100644 index 00000000000..91449a9d2b7 --- /dev/null +++ b/boards/intel/rpl/Kconfig.intel_rpl_p_crb @@ -0,0 +1,5 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_RPL_P_CRB + select SOC_RAPTOR_LAKE diff --git a/boards/intel/rpl/Kconfig.intel_rpl_s_crb b/boards/intel/rpl/Kconfig.intel_rpl_s_crb new file mode 100644 index 00000000000..79dc093dfe6 --- /dev/null +++ b/boards/intel/rpl/Kconfig.intel_rpl_s_crb @@ -0,0 +1,5 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_RPL_S_CRB + select SOC_RAPTOR_LAKE diff --git a/boards/x86/intel_rpl/board.cmake b/boards/intel/rpl/board.cmake similarity index 100% rename from boards/x86/intel_rpl/board.cmake rename to boards/intel/rpl/board.cmake diff --git a/boards/intel/rpl/board.yml b/boards/intel/rpl/board.yml new file mode 100644 index 00000000000..cc3969adced --- /dev/null +++ b/boards/intel/rpl/board.yml @@ -0,0 +1,9 @@ +boards: + - name: intel_rpl_p_crb + vendor: intel + socs: + - name: raptor_lake + - name: intel_rpl_s_crb + vendor: intel + socs: + - name: raptor_lake diff --git a/boards/intel/rpl/doc/index.rst b/boards/intel/rpl/doc/index.rst new file mode 100644 index 00000000000..4c078ab765e --- /dev/null +++ b/boards/intel/rpl/doc/index.rst @@ -0,0 +1,75 @@ +.. _intel_rpl_crb: + +Raptor Lake CRB +############### + +Overview +******** +Raptor Lake processor is a 13th generation 64-bit multi-core processor built +on a 10-nanometer technology process. Raptor Lake is based on a Hybrid +architecture, utilizing P-cores for performance and E-Cores for efficiency. + +Raptor Lake S and Raptor Lake P processor lines are supported. + +The S-Processor line is a 2-Chip Platform that includes the Processor Die and +Platform Controller Hub (PCH-S) Die in the Package. + +The P-Processor line is a 2-Die Multi Chip Package (MCP) that includes the +Processor Die and Platform Controller Hub (PCH-P) Die on the same package as +the Processor Die. + +For more information about Raptor Lake Processor lines, P-cores, and E-cores +please refer to `RPL`_. + +Raptor Lake Customer Reference Board (RPL CRB) is an example implementation of a +compact single board computer with high performance for IoT edge devices. The +supported boards are `intel_rpl_s_crb` and `intel_rpl_p_crb`. + +These board configurations enable kernel support for the supported Raptor Lake +boards. + +Hardware +******** + +General information about the board can be found at the `RPL`_. + +.. include:: ../../../../soc/intel/raptor_lake/doc/supported_features.txt + + +Connections and IOs +=================== + +Refer to the `RPL`_ for more information. + +Programming and Debugging +************************* +Use the following procedures for booting an image on an RPL CRB board. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application on Raptor Lake S CRB: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: intel_rpl_s_crb + :goals: build + + .. note:: + + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. + +Booting the Raptor Lake S CRB Board using UEFI +============================================== + +.. include:: ../../../intel/common/efi_boot.rst + :start-after: start_include_here + +.. _RPL: https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/ diff --git a/boards/x86/intel_rpl/intel_rpl_p_crb.dts b/boards/intel/rpl/intel_rpl_p_crb.dts similarity index 100% rename from boards/x86/intel_rpl/intel_rpl_p_crb.dts rename to boards/intel/rpl/intel_rpl_p_crb.dts diff --git a/boards/x86/intel_rpl/intel_rpl_p_crb.yaml b/boards/intel/rpl/intel_rpl_p_crb.yaml similarity index 100% rename from boards/x86/intel_rpl/intel_rpl_p_crb.yaml rename to boards/intel/rpl/intel_rpl_p_crb.yaml diff --git a/boards/x86/intel_rpl/intel_rpl_p_crb_defconfig b/boards/intel/rpl/intel_rpl_p_crb_defconfig similarity index 82% rename from boards/x86/intel_rpl/intel_rpl_p_crb_defconfig rename to boards/intel/rpl/intel_rpl_p_crb_defconfig index 09fd65cf261..c94efc744f6 100644 --- a/boards/x86/intel_rpl/intel_rpl_p_crb_defconfig +++ b/boards/intel/rpl/intel_rpl_p_crb_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_RAPTOR_LAKE=y -CONFIG_BOARD_INTEL_RPL_P_CRB=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/intel_rpl/intel_rpl_s_crb.dts b/boards/intel/rpl/intel_rpl_s_crb.dts similarity index 100% rename from boards/x86/intel_rpl/intel_rpl_s_crb.dts rename to boards/intel/rpl/intel_rpl_s_crb.dts diff --git a/boards/x86/intel_rpl/intel_rpl_s_crb.yaml b/boards/intel/rpl/intel_rpl_s_crb.yaml similarity index 100% rename from boards/x86/intel_rpl/intel_rpl_s_crb.yaml rename to boards/intel/rpl/intel_rpl_s_crb.yaml diff --git a/boards/x86/intel_rpl/intel_rpl_s_crb_defconfig b/boards/intel/rpl/intel_rpl_s_crb_defconfig similarity index 82% rename from boards/x86/intel_rpl/intel_rpl_s_crb_defconfig rename to boards/intel/rpl/intel_rpl_s_crb_defconfig index 1d8570bdeb7..c94efc744f6 100644 --- a/boards/x86/intel_rpl/intel_rpl_s_crb_defconfig +++ b/boards/intel/rpl/intel_rpl_s_crb_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_RAPTOR_LAKE=y -CONFIG_BOARD_INTEL_RPL_S_CRB=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/intel/socfpga/agilex5_socdk/Kconfig.defconfig b/boards/intel/socfpga/agilex5_socdk/Kconfig.defconfig new file mode 100644 index 00000000000..549795110a5 --- /dev/null +++ b/boards/intel/socfpga/agilex5_socdk/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config HAS_COVERAGE_SUPPORT + default y + +config MAX_THREAD_BYTES + default 5 diff --git a/boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk b/boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk new file mode 100644 index 00000000000..603cdb55a67 --- /dev/null +++ b/boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk @@ -0,0 +1,7 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK + select SOC_AGILEX5 + help + Intel SoC FPGA Development Kit (Agilex5) diff --git a/boards/intel/socfpga/agilex5_socdk/board.yml b/boards/intel/socfpga/agilex5_socdk/board.yml new file mode 100644 index 00000000000..fd4f5c91d66 --- /dev/null +++ b/boards/intel/socfpga/agilex5_socdk/board.yml @@ -0,0 +1,4 @@ +board: + name: intel_socfpga_agilex5_socdk + socs: + - name: agilex5 diff --git a/boards/intel/socfpga/agilex5_socdk/doc/index.rst b/boards/intel/socfpga/agilex5_socdk/doc/index.rst new file mode 100644 index 00000000000..006ca066251 --- /dev/null +++ b/boards/intel/socfpga/agilex5_socdk/doc/index.rst @@ -0,0 +1,80 @@ +.. _intel_socfpga_agilex5_socdk: + +Intel® Agilex™ 5 SoC FPGA Development Kit +######################################### + +Overview +******** + +The Intel® Agilex™ 5 SoC FPGA Development Kit offers a complete design +environment that includes both hardware and software for developing +Intel® Agilex™ 5 E-Series based FPGA designs. This kit is recommended for +developing custom ARM* processor-based SoC designs and ideal for intelligent +applications at the edge, embedded and more. + +Hardware +******** + +The Intel® Agilex™ 5 Development Kit supports the following physical features: + +- Intel® Agilex™ 5 E-Series FPGA, 50K-656K LEs integrated with + multi-core ARM processors of Dual-core A55 and Dual-core A76 +- On-board 8 GB DDR5 memory +- On-board JTAG Intel FPGA Download Cable II +- QSPI flash daughtercard + +Supported Features +================== +The Intel® Agilex™ 5 SoC Development Kit configuration supports the following +hardware features: + ++-----------+------------+---------------------------------------------+ +| Interface | Controller | Hardware Subsystem Vendor | ++===========+============+=============================================+ +| GIC-600 | on-chip | ARM GICv3 interrupt controller | ++-----------+------------+---------------------------------------------+ +| UART | on-chip | Synopsys Designware,NS16550 compatible | ++-----------+------------+---------------------------------------------+ +| ARM TIMER | on-chip | ARM system timer | ++-----------+------------+---------------------------------------------+ +| Reset | on-chip | Intel Corporation, SoCFPGA Reset controller | ++-----------+------------+---------------------------------------------+ +| Clock | on-chip | Intel Corporation, SoCFPGA Clock controller | ++-----------+------------+---------------------------------------------+ + +NOTE: TODO, more details on dev kit will be updated as and when available. + +The default configuration can be found in the defconfig file: + `boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig` + +Programming and Debugging +************************* + +Zephyr Boot Flow +**************** +Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). +ATF BL2 is the First Stage Boot Loader (FSBL) and ATF BL31 is the Run time resident firmware which +provides services like SMC (Secure monitor calls) and PSCI (Power state coordination interface). + +Boot flow: + ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL1) + +Intel Arm Trusted Firmware (ATF) can be downloaded from github: + `altera-opensource/arm-trusted-firmware `_ + +Flashing +======== +Zephyr image can be loaded in DDR memory at address 0x80000000 from +SD Card or QSPI Flash or NAND in ATF BL2. + +Debugging +========= +The Intel® Agilex™ 5 SoC Development Kit includes one JTAG connector on +board, connect it to Intel USB blaster download cables for debugging. + +Zephyr applications running on the Cortex-A55/A76 core can be tested by +observing UART console output. + +References +========== +`Intel® Agilex™ 5 FPGA and SoC FPGA `_ diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk.dts b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts similarity index 100% rename from boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk.dts rename to boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk.yaml b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.yaml similarity index 100% rename from boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk.yaml rename to boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.yaml diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig similarity index 84% rename from boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig rename to boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig index 0985f470c74..2ac56d65d37 100644 --- a/boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig +++ b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig @@ -1,14 +1,10 @@ -# Copyright (c) 2023 Intel Corporation +# Copyright (c) 2023-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 # The Zephyr build from this defconfig is expected to boot from # Intel Arm Trusted Firmware (ATF). # Boot Flow is: ATF BL21 -> ATF BL31 -> Zephyr -CONFIG_SOC_SERIES_AGILEX5=y -CONFIG_SOC_AGILEX5=y -CONFIG_BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK=y - # Compiler Options CONFIG_FORTIFY_SOURCE_RUN_TIME=y diff --git a/boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk b/boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk new file mode 100644 index 00000000000..18fcd9d69e8 --- /dev/null +++ b/boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk @@ -0,0 +1,7 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_SOCFPGA_AGILEX_SOCDK + select SOC_AGILEX + help + Intel SoC FPGA Development Kit (Agilex) diff --git a/boards/intel/socfpga/agilex_socdk/board.yml b/boards/intel/socfpga/agilex_socdk/board.yml new file mode 100644 index 00000000000..1c09cba0491 --- /dev/null +++ b/boards/intel/socfpga/agilex_socdk/board.yml @@ -0,0 +1,4 @@ +board: + name: intel_socfpga_agilex_socdk + socs: + - name: agilex diff --git a/boards/intel/socfpga/agilex_socdk/doc/index.rst b/boards/intel/socfpga/agilex_socdk/doc/index.rst new file mode 100644 index 00000000000..92db2c98300 --- /dev/null +++ b/boards/intel/socfpga/agilex_socdk/doc/index.rst @@ -0,0 +1,78 @@ +.. _intel_socfpga_agilex_socdk: + +Intel Agilex SoC Development Kit +################################# + +Overview +******** + +The Intel Agilex SoC Development Kit offers a complete design environment +that includes both hardware and software for developing Intel Agilex +F-Series FPGA designs. This kit is recommended for developing custom +Arm* processor-based SoC designs and evaluating transceiver performance. + +Hardware +******** + +The Intel Agilex SoC Development Kit supports the following physical features: + +- Intel Agilex F-Series FPGA, 1400 KLE, 2486A package integrate the + quad-core Arm Cortex-A53 processor +- On-board 8 GB DDR4 memory +- On-board JTAG Intel FPGA Download Cable II +- QSPI flash daughtercard +- HPS OOBE daughtercard with UART and SD Card support + +Supported Features +================== +The Intel Agilex SoC Development Kit configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| GIC-400 | on-chip | GICv2 interrupt controller | ++-----------+------------+--------------------------------------+ +| ARM TIMER | on-chip | System Clock | ++-----------+------------+--------------------------------------+ +| UART | on-chip | NS16550 compatible serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk_defconfig` + +Programming and Debugging +************************* + +Boot Flow +========= +Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). +ATF BL2 is first stage boot loader (FSBL) and ATF BL31 is second stage +boot loader (SSBL). + +Zephyr boot flow: + + ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL2->EL1) + +Intel Arm Trusted Firmware (ATF) can be downloaded from github: + + `altera-opensource/arm-trusted-firmware `_ + +Flashing +======== +Zephyr image can be loaded in DDR memory at address 0x10000000 from +SD Card or QSPI Flash in ATF BL2. + +Debugging +========= +The Intel Agilex SoC Development Kit includes one JTAG connector on +board, connect it to Intel USB blaster download cables for debugging. + +Zephyr applications running on the Cortex-A53 core can be tested by +observing UART console output. + +References +========== +`Intel Agilex Transceiver-SoC Development Kit `_ diff --git a/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.dts b/boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk.dts similarity index 100% rename from boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.dts rename to boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk.dts diff --git a/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.yaml b/boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk.yaml similarity index 100% rename from boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.yaml rename to boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk.yaml diff --git a/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig b/boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk_defconfig similarity index 77% rename from boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig rename to boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk_defconfig index b2ffb0602d3..6b5cf5c9cb7 100644 --- a/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig +++ b/boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk_defconfig @@ -1,13 +1,10 @@ -# Copyright (c) 2021 Intel Corporation +# Copyright (c) 2021-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 # The Zephyr build from this defconfig is expected to boot from # Intel Arm Trusted Firmware (ATF) # Boot Flow: BL21 -> BL31 -> Zephyr -CONFIG_SOC_SERIES_AGILEX=y -CONFIG_SOC_AGILEX=y -CONFIG_BOARD_INTEL_SOCFPGA_AGILEX_SOCDK=y CONFIG_ARM_ARCH_TIMER=y # Serial Drivers diff --git a/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.cyclonev_socdk b/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.cyclonev_socdk new file mode 100644 index 00000000000..cb62866b339 --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.cyclonev_socdk @@ -0,0 +1,7 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CYCLONEV_SOCDK + select SOC_CYCLONEV + help + Intel Cyclone V Development Kit diff --git a/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.defconfig b/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.defconfig new file mode 100644 index 00000000000..8afe506078b --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if I2C_DW +config I2C_DW_CLOCK_SPEED + default 200 +endif # I2C_DW + +if USB_DEVICE_STACK +config USB_DW_USB_2_0 + default y +config USB_DEVICE_DRIVER + default y +endif # USB_DEVICE_STACK + +if NETWORKING + +config NET_L2_ETHERNET + default y +config TEST_RANDOM_GENERATOR + default y + +endif # NETWORKING diff --git a/boards/intel/socfpga_std/cyclonev_socdk/board.cmake b/boards/intel/socfpga_std/cyclonev_socdk/board.cmake new file mode 100644 index 00000000000..adc44a8125a --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/board.cmake @@ -0,0 +1,19 @@ +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(intel_cyclonev) +board_set_debugger_ifnset(intel_cyclonev) + +if(OPENOCD_USE_LOAD_IMAGE) + set_ifndef(OPENOCD_FLASH load_image) +else() + set_ifndef(OPENOCD_FLASH "flash write_image erase") +endif() + +set(OPENOCD_CMD_LOAD_DEFAULT "${OPENOCD_FLASH}") +set(OPENOCD_CMD_VERIFY_DEFAULT "verify_image") + +board_finalize_runner_args(intel_cyclonev + --cmd-load "${OPENOCD_CMD_LOAD_DEFAULT}" + --cmd-verify "${OPENOCD_CMD_VERIFY_DEFAULT}" + ) diff --git a/boards/intel/socfpga_std/cyclonev_socdk/board.yml b/boards/intel/socfpga_std/cyclonev_socdk/board.yml new file mode 100644 index 00000000000..420762dda3f --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/board.yml @@ -0,0 +1,4 @@ +board: + name: cyclonev_socdk + socs: + - name: cyclonev diff --git a/boards/arm/cyclonev_socdk/cyclonev_socdk.dts b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts similarity index 92% rename from boards/arm/cyclonev_socdk/cyclonev_socdk.dts rename to boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts index 79753b3d53f..5218c62f2c7 100644 --- a/boards/arm/cyclonev_socdk/cyclonev_socdk.dts +++ b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts @@ -6,12 +6,12 @@ * this file is based on the GSRD DTS for Linux */ -#include "intel_socfpga_std/socfpga_cyclone5.dtsi" +#include "intel_socfpga_std/socfpga_cyclonev.dtsi" #include / { model = "Altera SOCFPGA Cyclone V SoC Development Kit"; - compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "altr,socfpga-cyclonev-socdk", "altr,socfpga-cyclonev", "altr,socfpga"; ddr0: memory@0 { name = "memory"; diff --git a/boards/arm/cyclonev_socdk/cyclonev_socdk.yaml b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.yaml similarity index 100% rename from boards/arm/cyclonev_socdk/cyclonev_socdk.yaml rename to boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.yaml diff --git a/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk_defconfig b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk_defconfig new file mode 100644 index 00000000000..32f784e44c8 --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_ARCH_TIMER=y + +CONFIG_SYSCON=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_NS16550_VARIANT_NS16950=y + +#Config Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#Flash not used. +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# GPIOs +CONFIG_GPIO=y diff --git a/boards/arm/cyclonev_socdk/doc/img/cv_soc_board.jpg b/boards/intel/socfpga_std/cyclonev_socdk/doc/img/cv_soc_board.jpg similarity index 100% rename from boards/arm/cyclonev_socdk/doc/img/cv_soc_board.jpg rename to boards/intel/socfpga_std/cyclonev_socdk/doc/img/cv_soc_board.jpg diff --git a/boards/arm/cyclonev_socdk/doc/img/cyclonev_blinky.jpg b/boards/intel/socfpga_std/cyclonev_socdk/doc/img/cyclonev_blinky.jpg similarity index 100% rename from boards/arm/cyclonev_socdk/doc/img/cyclonev_blinky.jpg rename to boards/intel/socfpga_std/cyclonev_socdk/doc/img/cyclonev_blinky.jpg diff --git a/boards/arm/cyclonev_socdk/doc/img/cyclonev_westflash.jpg b/boards/intel/socfpga_std/cyclonev_socdk/doc/img/cyclonev_westflash.jpg similarity index 100% rename from boards/arm/cyclonev_socdk/doc/img/cyclonev_westflash.jpg rename to boards/intel/socfpga_std/cyclonev_socdk/doc/img/cyclonev_westflash.jpg diff --git a/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst new file mode 100644 index 00000000000..752284a63b9 --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst @@ -0,0 +1,359 @@ +.. _cyclonev_socdk: + +Intel® Cyclone® V SoC Development Kit +##################################### + +Overview +******** + + +The Zephyr kernel is supported on the Intel® Cyclone® V SoC Development Kit, +using its Hard Processor System (HPS) CPU. + +.. figure:: img/cv_soc_board.jpg + :align: center + :alt: Intel's Cyclone® V SoC FPGA DevKit + + Intel®'s Cyclone® V SoC FPGA DevKit (Credit: Intel®) + +Hardware +******** + +Jumpers and DIP Switch settings +=============================== + +Recommended board settings are the same as the GSRD for Cyclone® V +SoC Development Board. + +There are two sets of switches on the back of the board. Of particular +importance is SW2. First, the board jumpers need to be configured as follows: + +* J5 : Open +* J6 : Short +* J7 : Short +* J9 : Open +* J13: Short +* J16: Open +* J26: Short pins 1-2 +* J27: Short pins 2-3 +* J28: Short pins 1-2 +* J29: Short pins 2-3 +* J30: Short pins 1-2 +* J31: Open + +Then, the board switches need to be configured as follows: + +* SW1: All OFF +* SW2: All OFF +* SW3: ON-OFF-ON-OFF-ON-ON +* SW4: OFF-OFF-ON-ON + +Other switches are user switches, their position is application-specific. +Refer to the development kit user manual for specifics about jumpers and switches + +Necessary Software +================== + +You will need the Intel® Quartus® Prime SDK in order to work with this device. The +`Intel® Quartus® Prime Lite Edition `_ +for Linux may be obtained without charge. + +For your convenience using the SDK tools (such as ``quartus_pgm``), +you should put the binaries provided by the SDK +in your path. Below is an example, adjust ALTERA_BASE to where you installed the +SDK: + +.. code-block:: console + + export QUARTUS_ROOTDIR=/opt/intelFPGA_lite/21.1 + export PATH=$PATH:$QUARTUS_ROOTDIR/quartus/bin:$QUARTUS_ROOTDIR/programmer/bin + +You may need to adjust your udev rules so that you can talk to the USB Blaster +II peripheral, which is the built-in JTAG interface for this device. + +The following works for Ubuntu: + +.. code-block:: console + + # For Altera USB-Blaster permissions. + SUBSYSTEM=="usb",\ + ENV{DEVTYPE}=="usb_device",\ + ATTR{idVendor}=="09fb",\ + ATTR{idProduct}=="6010",\ + MODE="0666",\ + NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ + RUN+="/bin/chmod 0666 %c" + SUBSYSTEM=="usb",\ + ENV{DEVTYPE}=="usb_device",\ + ATTR{idVendor}=="09fb",\ + ATTR{idProduct}=="6810",\ + MODE="0666",\ + NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ + RUN+="/bin/chmod 0666 %c" + +You can test connectivity with the SDK jtagconfig tool, you should see something +like: + +.. code-block:: console + + $ jtagconfig + 1) USB-BlasterII [1-5] + 4ba00477 SOCVHPS + 02D020DD 5ZSEBA6(.|ES)/5CSEMA6/.. + + +Golden Reference Design +======================= + +The Golden System Reference Design (GSRD) provides a set of essential hardware +and software system componets that can be used as a starting point for various +custom user designs. + +The Zephyr support for Cyclone® V SoC Development Kit is based on GSRD hardware. +Please refer to `Intel® Cyclone® V SoC GSRD `_ + +The hardware use for this release is based on Intel® Quartus® version 21.1 +the hardware files can be found `here `_ + +The directory "cv_soc_devkit_ghrd" contains the necessary files to create +a Intel® Quartus® project: + +* ghrd_top.v : top level Verilog (HDL) file for the GSRD +* soc_system.qpf : Quartus® Prime Project File +* soc_system.qsf : Quartus® Prime Settings File +* soc_system.qsys : Platform Designer file (contains the SoC system) +* soc_system.sopcinfo : SOPC Information file contains details about modules instantiated in the project, parameter names and values. +* soc_system_timing.sdc : Synopsys Desing Constraint FILE. +* output_files/soc_system.sof : FPGA configuration file. + + +Flash this FPGA file (.sof) using the ``quartus_pgm`` SDK tool with the FPGA +configuration file soc_system.sof: + +.. code-block:: console + + $ quartus_pgm -m jtag -o "p;path/to/soc_system.sof" + +This system is composed by the HPS, ARM Cortex-A9. In this example the UART, timer, +USB, I2C, DDR memory are exposed. Please double check the peripheral you intend to +use have its corresponding driver support. +You can find more information of the Cyclone® V SoC Devkit GSRD in RocketBoards +or consult the "Cyclone® V Hard Processor System Technical Reference Manual" + + +Console Output +============== + +16550 UART +---------- + +By default, the kernel is configured to send console output to the 16550 UART. +You can monitor this on your workstation by connecting to the top right mini USB +port on the board (J8/UART) (it will show up in /dev as a ttyUSB node), and then running +minicom/PuTTy with flow control disabled, 115200-8N1 settings. + + +Programming and Debugging +************************* + +Flashing +======== + +Flashing Kernel into the board +------------------------------ + +The usual ``flash`` target will work with the ``cyclonev_socdk`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +``Important!!!`` : Before flashing the board a ``preloader`` is required, +you can download `cv_soc_devkit_ghrd.tar.gz `_, +extract the file and copy ``cv_soc_devkit_ghrd/software/preloader/uboot-socfpga/spl/u-boot-spl`` +to :zephyr_file:`boards/intel/socfpga_std/cyclonev_socdk/support/` + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cyclonev_socdk + :goals: flash + +Refer to :ref:`build_an_application` and :ref:`application_run` for +more details. + +This provisions the Zephyr kernel and the CPU configuration onto the board, +using the customized OpenOCD runner script :zephyr_file:`scripts/west_commands/runners/intel_cyclonev.py` +After it completes the kernel will immediately boot using the GSRD preloader. +Notice that there a lot of helper files to ``flash`` the application with +OpenOCD and GDB Debbuger (Zephyr SDK must be installed in your machine). +This files should be located in :zephyr_file:`boards/intel/socfpga_std/cyclonev_socdk/support/` including: + +* blaster_6810.hex : USB-BlasterII firmware +* tmp_preloader_dl_cmd.txt : GDB helper file to load the preloader +* tmp_appli_dl_cmd.gdb : GDB helper file to load the zephyr.elf file +* tmp_appli_debug_cmd.gdb : GDB helper file to load the zephyr.elf file while debugging +* openocd.cfg : sources configuration files for OpenOCD +* download_all.gdb : GDB helper file to load the preloader +* u-boot-spl : Cyclone® V SoC DevKit GSRD preloader (copied from GSRD: cv_soc_devkit_ghrd.tar.gz) + +The following image shows the expected output (UART) after executing "west flash" using +the "hello world" sample design: + +.. figure:: img/cyclonev_westflash.jpg + :align: center + :alt: UART output after "west flash" example + + UART output after "west flash" example (Credit: Intel®) + +Debugging +========= + +The Zephyr SDK includes a GDB server which can be used to debug a Cyclone® V +SoC Development Kit board. +You can either debug a running image that was flashed onto the device in User +Flash Memory (UFM), or load an image over the JTAG using GDB. + +Debugging With Flashed Image +---------------------------- + +You can debug an application in the usual way. Here is an example. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cyclonev_socdk + :goals: debug + +You will see output similar to the following: + +.. code-block:: console + + -- west debug: rebuilding + ninja: no work to do. + -- west debug: using runner intel_cyclonev + -- runners.intel_cyclonev: OpenOCD GDB server running on port 3333; no thread info available + Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) + Licensed under GNU GPL v2 + For bug reports, read http://openocd.org/doc/doxygen/bugs.html + Info : only one transport option; autoselect 'jtag' + cycv_dbginit + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + Info : Altera USB-Blaster II (uninitialized) found + Info : Loading firmware... + Info : Waiting for reenumerate... + Info : Waiting for reenumerate... + Info : Altera USB-Blaster II found (Firm. rev. = 1.39) + Info : This adapter doesn't support configurable speed + Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) + Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) + Info : DAP transaction stalled (WAIT) - slowing down + Info : DAP transaction stalled (WAIT) - slowing down + Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints + Info : starting gdb server for fpgasoc.cpu.0 on 3333 + Info : Listening on port 3333 for gdb connections + Info : accepting 'gdb' connection on tcp/3333 + Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 + Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT + target halted in ARM state due to debug-request, current mode: Supervisor + cpsr: 0x600001d3 pc: 0x00002fa4 + MMU: disabled, D-Cache: disabled, I-Cache: enabled + warning: No executable has been specified and target does not support + determining executable automatically. Try using the "file" command. + 0x00002fa4 in ?? () + Restoring section .text (0xffff0000 to 0xffff6f84) + Info : DAP transaction stalled (WAIT) - slowing down + Warn : keep_alive() was not invoked in the 1000 ms timelimit. GDB alive packet not sent! (1469 ms). Workaround: increase "set remotetimeout" in GDB + Restoring section .rodata (0xffff6f84 to 0xffff8af9) + Restoring section .data (0xffff8b00 to 0xffff99d4) + Info : DAP transaction stalled (WAIT) - slowing down + Hardware assisted breakpoint 1 at 0xffff147e + Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 + fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 + + Temporary breakpoint 1, 0xffff147e in spl_boot_device () + [Inferior 1 (Remote target) detached] + Info : dropped 'gdb' connection + shutdown command invoked + Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) + Licensed under GNU GPL v2 + For bug reports, read http://openocd.org/doc/doxygen/bugs.html + Info : only one transport option; autoselect 'jtag' + cycv_dbginit + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + Info : Altera USB-Blaster II found (Firm. rev. = 1.39) + Info : This adapter doesn't support configurable speed + Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) + Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) + Info : DAP transaction stalled (WAIT) - slowing down + Info : DAP transaction stalled (WAIT) - slowing down + Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints + Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 + Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT + Info : starting gdb server for fpgasoc.cpu.0 on 3333 + Info : Listening on port 3333 for gdb connections + Info : accepting 'gdb' connection on tcp/3333 + warning: No executable has been specified and target does not support + determining executable automatically. Try using the "file" command. + 0xffff147c in ?? () + warning: /home/demo/zephyrproject/zephyr/boards/intel/socfpga_std/cyclonev_socdk/support/tmp_appli_debug_cmd.gdb: No such file or directory + [Inferior 1 (Remote target) detached] + Info : dropped 'gdb' connection + shutdown command invoked + Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) + Licensed under GNU GPL v2 + For bug reports, read http://openocd.org/doc/doxygen/bugs.html + Info : only one transport option; autoselect 'jtag' + cycv_dbginit + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + Info : Altera USB-Blaster II found (Firm. rev. = 1.39) + Info : This adapter doesn't support configurable speed + Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) + Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) + Info : DAP transaction stalled (WAIT) - slowing down + Info : DAP transaction stalled (WAIT) - slowing down + Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints + Reading symbols from /home/demo/zephyrproject/zephyr/build/zephyr/zephyr.elf... + Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 + Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT + Info : starting gdb server for fpgasoc.cpu.0 on 3333 + Info : Listening on port 3333 for gdb connections + Remote debugging using :3333 + Info : accepting 'gdb' connection on tcp/3333 + main () at /home/demo/zephyrproject/zephyr/samples/hello_world/src/main.c:11 + 11 printk("Hello World! %s\n", CONFIG_BOARD); + (gdb) + + +Try other examples +================== +There are varios examples that can be downloaded to the Cyclone® V SoC FPGA +Development Kit Board. Try to ``blink`` an LED from the HPS side of the chip: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: cyclonev_socdk + :goals: flash + +.. figure:: img/cyclonev_blinky.jpg + :align: center + :alt: HPS LED0 blinking example + + HPS LED0 blinking example (Credit: Intel®) + +Try writing characters to the LCD display connected to the i2c bus: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/lcd_cyclonev_socdk + :board: cyclonev_socdk + :goals: flash + + +References +********** + +* `Cyclone® V Hard Processor System Technical Reference Manual `_ +* `Cyclone® V SoC Development Kit and Intel® SoC FPGA Embedded Development Suite `_ +* `Cyclone® V SoC GSRD in RocketBoards.org `_ +* `Intel® FPGA Software Download Center `_ +* `Embedded Peripherals IP User Guide `_ +* `Quartus II Scripting Reference Manual `_ diff --git a/boards/arm/cyclonev_socdk/support/altera-usb-blaster2-cyclonev.cfg b/boards/intel/socfpga_std/cyclonev_socdk/support/altera-usb-blaster2-cyclonev.cfg similarity index 100% rename from boards/arm/cyclonev_socdk/support/altera-usb-blaster2-cyclonev.cfg rename to boards/intel/socfpga_std/cyclonev_socdk/support/altera-usb-blaster2-cyclonev.cfg diff --git a/boards/arm/cyclonev_socdk/support/appli_debug_cmd.gdb b/boards/intel/socfpga_std/cyclonev_socdk/support/appli_debug_cmd.gdb similarity index 100% rename from boards/arm/cyclonev_socdk/support/appli_debug_cmd.gdb rename to boards/intel/socfpga_std/cyclonev_socdk/support/appli_debug_cmd.gdb diff --git a/boards/arm/cyclonev_socdk/support/appli_dl_cmd.gdb b/boards/intel/socfpga_std/cyclonev_socdk/support/appli_dl_cmd.gdb similarity index 100% rename from boards/arm/cyclonev_socdk/support/appli_dl_cmd.gdb rename to boards/intel/socfpga_std/cyclonev_socdk/support/appli_dl_cmd.gdb diff --git a/boards/arm/cyclonev_socdk/support/blaster_6810.hex b/boards/intel/socfpga_std/cyclonev_socdk/support/blaster_6810.hex similarity index 100% rename from boards/arm/cyclonev_socdk/support/blaster_6810.hex rename to boards/intel/socfpga_std/cyclonev_socdk/support/blaster_6810.hex diff --git a/boards/intel/socfpga_std/cyclonev_socdk/support/download_all.gdb b/boards/intel/socfpga_std/cyclonev_socdk/support/download_all.gdb new file mode 100644 index 00000000000..97700438910 --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/support/download_all.gdb @@ -0,0 +1,18 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 +# Description: +# Download preloader and .elf using GDB commands + +set confirm off +set pagination off + +#Download and Run preloader +source boards/intel/socfpga_std/cyclonev_socdk/support/preloader_dl_cmd.txt + +#Stop watchdog timer +#permodrst Reg , reset watch dog timer +set $permodrst = (int *)0xffd05014 +set *$permodrst = (*$permodrst) | (1<<6) +set *$permodrst = (*$permodrst) & ~(1<<6) + +quit diff --git a/boards/arm/cyclonev_socdk/support/openocd.cfg b/boards/intel/socfpga_std/cyclonev_socdk/support/openocd.cfg similarity index 100% rename from boards/arm/cyclonev_socdk/support/openocd.cfg rename to boards/intel/socfpga_std/cyclonev_socdk/support/openocd.cfg diff --git a/boards/intel/socfpga_std/cyclonev_socdk/support/preloader_dl_cmd.txt b/boards/intel/socfpga_std/cyclonev_socdk/support/preloader_dl_cmd.txt new file mode 100644 index 00000000000..f349b2ec6db --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/support/preloader_dl_cmd.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 +# Description: +# Helper file to download the GSRD preloader to the board before the application + +restore boards/intel/socfpga_std/cyclonev_socdk/support/u-boot-spl +symbol-file -readnow boards/intel/socfpga_std/cyclonev_socdk/support/u-boot-spl +thbreak spl_boot_device +jump _start diff --git a/boards/ite/index.rst b/boards/ite/index.rst new file mode 100644 index 00000000000..e603fcd44c1 --- /dev/null +++ b/boards/ite/index.rst @@ -0,0 +1,10 @@ +.. _boards-ite: + +ITE Tech. Inc. +############## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/ite/it82xx2_evb/Kconfig.defconfig b/boards/ite/it82xx2_evb/Kconfig.defconfig new file mode 100644 index 00000000000..a106a9d6151 --- /dev/null +++ b/boards/ite/it82xx2_evb/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2023 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IT82XX2_EVB + +config INPUT + default y if KSCAN + +endif diff --git a/boards/ite/it82xx2_evb/Kconfig.it82xx2_evb b/boards/ite/it82xx2_evb/Kconfig.it82xx2_evb new file mode 100644 index 00000000000..94025707fa4 --- /dev/null +++ b/boards/ite/it82xx2_evb/Kconfig.it82xx2_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2023 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IT82XX2_EVB + select SOC_IT82202_AX diff --git a/boards/ite/it82xx2_evb/board.yml b/boards/ite/it82xx2_evb/board.yml new file mode 100644 index 00000000000..f986050cad3 --- /dev/null +++ b/boards/ite/it82xx2_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: it82xx2_evb + vendor: ite + socs: + - name: it82202ax diff --git a/boards/riscv/it82xx2_evb/doc/WinFlashTool_P1.jpg b/boards/ite/it82xx2_evb/doc/WinFlashTool_P1.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/WinFlashTool_P1.jpg rename to boards/ite/it82xx2_evb/doc/WinFlashTool_P1.jpg diff --git a/boards/riscv/it82xx2_evb/doc/WinFlashTool_P2.jpg b/boards/ite/it82xx2_evb/doc/WinFlashTool_P2.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/WinFlashTool_P2.jpg rename to boards/ite/it82xx2_evb/doc/WinFlashTool_P2.jpg diff --git a/boards/riscv/it82xx2_evb/doc/WinFlashTool_P3.jpg b/boards/ite/it82xx2_evb/doc/WinFlashTool_P3.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/WinFlashTool_P3.jpg rename to boards/ite/it82xx2_evb/doc/WinFlashTool_P3.jpg diff --git a/boards/riscv/it82xx2_evb/doc/WinFlashTool_P4.jpg b/boards/ite/it82xx2_evb/doc/WinFlashTool_P4.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/WinFlashTool_P4.jpg rename to boards/ite/it82xx2_evb/doc/WinFlashTool_P4.jpg diff --git a/boards/ite/it82xx2_evb/doc/index.rst b/boards/ite/it82xx2_evb/doc/index.rst new file mode 100644 index 00000000000..e969114180e --- /dev/null +++ b/boards/ite/it82xx2_evb/doc/index.rst @@ -0,0 +1,247 @@ +.. _it82xx2_evb: + +ITE IT82XX2 series +###################### + +Overview +******** + +The IT82XX2 is a 32-bit RISC-V microcontroller. +And a highly integrated embedded controller with system functions. +It is suitable for mobile system applications. The picture below is +the IT82202 development board (also known as it82xx2_evb) and its debug card. + +.. figure:: it82xx2_evb_and_debug_card.jpg + :align: center + :alt: IT82202 EVB + +To find out more about ITE, visit our World Wide Web at:`ITE's website`_ + +Hardware +******** +The IT82XX2 series contains different chip types(ex, it82202, it82302), +and they support different hardware features. +Listing the IT82202 hardware features as following: + +- RISC-V RV32IMAFC instruction set +- 4KB instruction cache size +- 256KB SRAM in total +- Built-in 32.768 kHz clock generator +- Embedded Flash, 512K/1024K-byte e-flash +- eSPI, SSPI, SPI slave, BRAM, KBC, PECI, UART +- GPIO, PWM, ADC, INTC, WUC, Timer, Watchdog, KB scan, JTAG +- Support 6 Voltage Comparator +- Support Cryptographic Engine +- 6 SMBus channels, with 6 DMA controller, compatible with I2C +- USB 2.0 Full-speed Controller +- USB Type-c CC Logic +- USB Power Delivery + + +Supported Features +================== +currently supports the following hardware features: + +.. list-table:: Supported Features + :header-rows: 1 + :widths: auto + + * - Interface + - Controller + - Driver/Component + * - NVIC + - on-chip + - interrupt controller + * - FLASH + - on-chip + - flash controller + * - PINCTRL + - on-chip + - pin controller + * - ESPI + - on-chip + - espi + * - PECI + - on-chip + - peci + * - UART + - on-chip + - serial + * - GPIO + - on-chip + - gpio + * - PWM + - on-chip + - pwm + * - ADC + - on-chip + - adc + * - TIMER + - on-chip + - timer + * - WATCHDOG + - on-chip + - watchdog + * - KSCAN + - on-chip + - kscan + * - SENSOR + - on-chip + - voltage comparator + * - I2C + - on-chip + - i2c + + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the +:zephyr_file:`boards/ite/it82xx2_evb/it82xx2_evb_defconfig` Kconfig file. + +Programming and debugging on it82202 +************************************ + +In order to upload the application to the device, +you'll need our flash tool and Download board. +You can get them at: `ITE's website`_. + +Wiring +======= +#. Connect the Download Board to your host computer using the USB cable. + +#. Connect the it82xx2_evb to the evolution motherboard. + +#. Connect the Download Board J5 to J41 on the evolution motherboard. + +#. Connect the USB to UART wire to J33 on the evolution motherboard. + + .. image:: it82xx2_evb_wiring.jpg + :align: center + :alt: it82xx2_evb wiring + + .. note:: Be careful during connection! + Use separate wires to connect I2C pins with pins on the it82xx2_evb board. + Wiring connection is described in the table below. + + +-------------+---------------+ + | J5 | it82xx2_evb | + | Connector | J41 Connector | + +=============+===============+ + | 2 | E0 | + +-------------+---------------+ + | 3 | E7 | + +-------------+---------------+ + | 4 | GND | + +-------------+---------------+ + + For USB to UART cable, connect the evolution motherboard as below: + + +-------------+---------------+ + | USB to UART | Evolution | + | cable | motherboard | + | | J33 Connector | + +=============+===============+ + | RX | B0 | + +-------------+---------------+ + | TX | B1 | + +-------------+---------------+ + | GND | GND | + +-------------+---------------+ + +Building +======== + +#. Build :ref:`hello_world` application as you would normally do + (see :`Zephyr Getting Started Guide`_):. + + .. zephyr-app-commands:: + :board: it82xx2_evb + :zephyr-app: samples/hello_world + :goals: build + +#. The file :file:`zephyr.bin` will be created by west. + +Flashing +======== + +Windows +-------- + +Use the winflash tool to program a zephyr application +to the it82xx2 board flash. + +#. Open the winflash tool and make sure the order you open the switch is right. + First, turn on the Download board switch. + Second, turn on the it82xx2_evb board switch. + Then, configure your winflash tool like below. + + .. figure:: WinFlashTool_P2.jpg + :align: center + + .. figure:: WinFlashTool_P4.jpg + +#. Using the winflash tool flash ``zephyr.bin`` into your ITE board. + First, click the ``Load`` button and select your ``zephyr.bin`` file. + Second, click ``run`` to flash the image into board. + + .. figure:: WinFlashTool_P3.jpg + :align: center + +#. At this point, you have flashed your image into ITE board and + it will work if you turn on the ITE board. You can use a terminal program + to verify flashing worked correctly. + + For example, open device manager to find the USB Serial Port(COM4) and use your + terminal program to connect it(Speed: 115200). + + .. figure:: WinFlashTool_P1.jpg + :align: center + +#. Turn on the it82xx2_evb board switch, you should see ``"Hello World! it82xx2_evb"`` + sent by the board. If you don't see this message, press the Reset button and the + message should appear. + +Ubuntu +-------- + +#. Run your favorite terminal program to listen for output. + Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. + + For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -b 115200 + +#. Open a second terminal window and use the Linux flash tool to flash your board. + + .. code-block:: console + + $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin + + .. note:: The source code of ITE tool can be downloaded here: + https://www.ite.com.tw/uploads/product_download/itedlb4-linux-v106.tar.bz2 + +#. Split first and second terminal windows to view both of them. + You should see ``"Hello World! it82xx2_evb"`` in the first terminal window. + If you don't see this message, press the Reset button and the message should appear. + +Debugging +========= + +it82xx2_evb board can be debugged by connecting USB to UART. We can write commands and +read messages through minicom in the Ubuntu terminal. + +Troubleshooting +=============== + +#. If the flash tool reports a failure, re-plug the 8390 Download board or + power cycle the it82xx2_evb board and try again. + +References +========== + +.. target-notes:: + +.. _ITE's website: https://www.ite.com.tw/zh-tw/product/view?mid=169 +.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html diff --git a/boards/riscv/it82xx2_evb/doc/it82xx2_evb_and_debug_card.jpg b/boards/ite/it82xx2_evb/doc/it82xx2_evb_and_debug_card.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/it82xx2_evb_and_debug_card.jpg rename to boards/ite/it82xx2_evb/doc/it82xx2_evb_and_debug_card.jpg diff --git a/boards/riscv/it82xx2_evb/doc/it82xx2_evb_wiring.jpg b/boards/ite/it82xx2_evb/doc/it82xx2_evb_wiring.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/it82xx2_evb_wiring.jpg rename to boards/ite/it82xx2_evb/doc/it82xx2_evb_wiring.jpg diff --git a/boards/riscv/it82xx2_evb/it82xx2_evb.dts b/boards/ite/it82xx2_evb/it82xx2_evb.dts similarity index 100% rename from boards/riscv/it82xx2_evb/it82xx2_evb.dts rename to boards/ite/it82xx2_evb/it82xx2_evb.dts diff --git a/boards/riscv/it82xx2_evb/it82xx2_evb.yaml b/boards/ite/it82xx2_evb/it82xx2_evb.yaml similarity index 100% rename from boards/riscv/it82xx2_evb/it82xx2_evb.yaml rename to boards/ite/it82xx2_evb/it82xx2_evb.yaml diff --git a/boards/riscv/it82xx2_evb/it82xx2_evb_defconfig b/boards/ite/it82xx2_evb/it82xx2_evb_defconfig similarity index 81% rename from boards/riscv/it82xx2_evb/it82xx2_evb_defconfig rename to boards/ite/it82xx2_evb/it82xx2_evb_defconfig index 6866e3f633b..2b174670d48 100644 --- a/boards/riscv/it82xx2_evb/it82xx2_evb_defconfig +++ b/boards/ite/it82xx2_evb/it82xx2_evb_defconfig @@ -1,11 +1,6 @@ # Copyright (c) 2023 ITE Corporation. All Rights Reserved. # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_ITE_IT8XXX2=y -CONFIG_SOC_IT8XXX2=y -CONFIG_SOC_IT82202_AX=y -CONFIG_BOARD_IT82XX2_EVB=y - CONFIG_GEN_IRQ_VECTOR_TABLE=n # General Kernel Options diff --git a/boards/ite/it8xxx2_evb/Kconfig.defconfig b/boards/ite/it8xxx2_evb/Kconfig.defconfig new file mode 100644 index 00000000000..57fc0404475 --- /dev/null +++ b/boards/ite/it8xxx2_evb/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IT8XXX2_EVB + +if PM + +config PM_DEVICE + default y + +choice PM_POLICY + default PM_POLICY_CUSTOM +endchoice + +endif # PM + +config INPUT + default y if KSCAN + +endif # BOARD_IT8XXX2_EVB diff --git a/boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb b/boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb new file mode 100644 index 00000000000..9eed36bcacd --- /dev/null +++ b/boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IT8XXX2_EVB + select SOC_IT82202_AX diff --git a/boards/riscv/it8xxx2_evb/board.cmake b/boards/ite/it8xxx2_evb/board.cmake similarity index 100% rename from boards/riscv/it8xxx2_evb/board.cmake rename to boards/ite/it8xxx2_evb/board.cmake diff --git a/boards/ite/it8xxx2_evb/board.yml b/boards/ite/it8xxx2_evb/board.yml new file mode 100644 index 00000000000..ff2f8ca7776 --- /dev/null +++ b/boards/ite/it8xxx2_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: it8xxx2_evb + vendor: ite + socs: + - name: it82202ax diff --git a/boards/riscv/it8xxx2_evb/doc/WinFlashTool_P1.jpg b/boards/ite/it8xxx2_evb/doc/WinFlashTool_P1.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/WinFlashTool_P1.jpg rename to boards/ite/it8xxx2_evb/doc/WinFlashTool_P1.jpg diff --git a/boards/riscv/it8xxx2_evb/doc/WinFlashTool_P2.jpg b/boards/ite/it8xxx2_evb/doc/WinFlashTool_P2.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/WinFlashTool_P2.jpg rename to boards/ite/it8xxx2_evb/doc/WinFlashTool_P2.jpg diff --git a/boards/riscv/it8xxx2_evb/doc/WinFlashTool_P3.jpg b/boards/ite/it8xxx2_evb/doc/WinFlashTool_P3.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/WinFlashTool_P3.jpg rename to boards/ite/it8xxx2_evb/doc/WinFlashTool_P3.jpg diff --git a/boards/riscv/it8xxx2_evb/doc/WinFlashTool_P4.jpg b/boards/ite/it8xxx2_evb/doc/WinFlashTool_P4.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/WinFlashTool_P4.jpg rename to boards/ite/it8xxx2_evb/doc/WinFlashTool_P4.jpg diff --git a/boards/ite/it8xxx2_evb/doc/index.rst b/boards/ite/it8xxx2_evb/doc/index.rst new file mode 100644 index 00000000000..9f345639c48 --- /dev/null +++ b/boards/ite/it8xxx2_evb/doc/index.rst @@ -0,0 +1,228 @@ +.. _it8xxx2_evb: + +ITE IT8XXX2 series +###################### + +Overview +******** + +The IT8XXX2 is a 32-bit RISC-V Micro-controller. +And a highly integrated embedded controller with system functions. +It is suitable for mobile system applications. The picture below is +the IT81302 MECC board (also known as it8xxx2_evb) and its debug card. + +.. figure:: it8xxx2_evb_and_debug_card.jpg + :align: center + :alt: IT81302 EVB + +To find out more about ITE, visit our World Wide Web at:`ITE's website`_ + +Hardware +******** +The IT8XXX2 series contains different chip types(ex, it81302, it83202), +and they support different hardware features. +Listing the IT81302 hardware features as following: + +- RISC-V RV32IMAFC instruction set +- 4KB instruction cache size +- 60KB SDRAM in total +- Built-in 32.768 kHz clock generator +- PWM, eSPI, LPC, FLASH, UART, GPIO, Timer, Watchdog, ADC, JTAG +- 6 SMBus channels, with 3 DMA controllers, compatible with I2C +- SPI master/slave +- USB Type-c CC Logic +- USB Power Delivery +- Support KB scan + + +Supported Features +================== +currently supports the following hardware features: + +.. list-table:: Supported Features + :header-rows: 1 + :widths: auto + + * - Interface + - Controller + - Driver/Component + * - NVIC + - on-chip + - interrupt controller + * - TIMER + - on-chip + - timer + * - UART + - on-chip + - serial + * - GPIO + - on-chip + - gpio + * - ADC + - on-chip + - adc + * - I2C + - on-chip + - i2c + * - KSCAN + - on-chip + - kscan + + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the +:zephyr_file:`boards/ite/it8xxx2_evb/it8xxx2_evb_defconfig` Kconfig file. + +Hardware reworks +**************** + +Before using the it8xxx2_evb, some hardware rework is needed. The HW rework +guide can be found in ITE's website. +https://www.ite.com.tw/uploads/product_download/IT81302_MECC_Rework_Guide_0927.pdf + +Programming and debugging on it83202 +************************************ + +In order to upload the application to the device, +you'll need our flash tool and Download board. +You can get them at: `ITE's website`_. + +Wiring +======= +#. Connect the Download Board to your host computer using the USB cable. + +#. Connect the it8xxx2_evb to your host computer or a 5V1A USB power supply. + +#. Connect the Download Board J5 to J8 on the it8xxx2_evb board. + +#. Connect the USB to UART wire to it8xxx2_evb. + + .. image:: it8xxx2_evb_wiring.jpg + :align: center + :alt: it8xxx2_evb wiring + + .. note:: Be careful during connection! + Use separate wires to connect I2C pins with pins on the it8xxx2_evb board. + Wiring connection is described in the table below. + + +-------------+---------------+ + | J5 | it8xxx2_evb | + | Connector | J8 Connector | + +=============+===============+ + | 2 | 1 | + +-------------+---------------+ + | 3 | 3 | + +-------------+---------------+ + | 4 | 5 | + +-------------+---------------+ + + For USB to UART cable, connect the it8xxx2_evb as below: + + +-------------+---------------+ + | USB to UART | it8xxx2_evb | + | cable | J5 Connector | + +=============+===============+ + | RX | J5.3 | + +-------------+---------------+ + | TX | J5.4 | + +-------------+---------------+ + | GND | eSPI Debug.10 | + +-------------+---------------+ + +Building +======== + +#. Build :ref:`hello_world` application as you would normally do + (see :`Zephyr Getting Started Guide`_):. + + .. zephyr-app-commands:: + :board: it8xxx2_evb + :zephyr-app: samples/hello_world + :goals: build + +#. The file :file:`zephyr.bin` will be created by west. + +Flashing +======== + +Windows +-------- + +Use the winflash tool to program a zephyr application +to the it8xxx2 board flash. + +#. Open winflash tool and make sure the order you open the switch is right. + Fisrt, turn on the Download board switch. + Second, turn on the it8xxx2_evb board switch. + Then, configure your winflash tool like below. + + .. figure:: WinFlashTool_P2.jpg + :align: center + + .. figure:: WinFlashTool_P4.jpg + +#. Using winflash tool flash zephyr.bin into your ITE board. + First, click ``Load`` button and select your zephyr.bin file. + Second, click ``run`` to flash the iamge into board. + + .. figure:: WinFlashTool_P3.jpg + :align: center + +#. At this point, you have flashed your image into ITE board and + it will work if you turn on ITE board. You can use a terminal program + to verify flashing worked correctly. + + For example, open device manager to find the USB Serial Port(COM4) and use your + terminal program to connect it(Speed: 115200). + + .. figure:: WinFlashTool_P1.jpg + :align: center + +#. Turn on the it8xxx2_evb board switch, you should see ``"Hello World! it8xxx2_evb"`` + sent by the board. If you don't see this message, press the Reset button and the + message should appear. + +Ubuntu +-------- + +#. Run your favorite terminal program to listen for output. + Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. + + For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -b 115200 + +#. Open a second terminal window and use linux flash tool to flash your board. + + .. code-block:: console + + $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin + + .. note:: The source code of ITE tool can be downloaded here: + https://www.ite.com.tw/uploads/product_download/itedlb4-linux-v106.tar.bz2 + +#. Split first and second terminal windows to view both of them. + You should see ``"Hello World! it8xxx2_evb"`` in the first terminal window. + If you don't see this message, press the Reset button and the message should appear. + +Debugging +========= + +Supporting uart debug, currently. + +Troubleshooting +=============== + +#. If the flash tool reports a failure, re-plug the 8390 Download board or + power cycle the it8xxx2_evb board and try again. + +References +========== + +.. target-notes:: + +.. _ITE's website: http://www.ite.com.tw/en/product/view?mid=149 +.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html diff --git a/boards/riscv/it8xxx2_evb/doc/it8xxx2_evb_and_debug_card.jpg b/boards/ite/it8xxx2_evb/doc/it8xxx2_evb_and_debug_card.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/it8xxx2_evb_and_debug_card.jpg rename to boards/ite/it8xxx2_evb/doc/it8xxx2_evb_and_debug_card.jpg diff --git a/boards/riscv/it8xxx2_evb/doc/it8xxx2_evb_wiring.jpg b/boards/ite/it8xxx2_evb/doc/it8xxx2_evb_wiring.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/it8xxx2_evb_wiring.jpg rename to boards/ite/it8xxx2_evb/doc/it8xxx2_evb_wiring.jpg diff --git a/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts b/boards/ite/it8xxx2_evb/it8xxx2_evb.dts similarity index 100% rename from boards/riscv/it8xxx2_evb/it8xxx2_evb.dts rename to boards/ite/it8xxx2_evb/it8xxx2_evb.dts diff --git a/boards/riscv/it8xxx2_evb/it8xxx2_evb.yaml b/boards/ite/it8xxx2_evb/it8xxx2_evb.yaml similarity index 100% rename from boards/riscv/it8xxx2_evb/it8xxx2_evb.yaml rename to boards/ite/it8xxx2_evb/it8xxx2_evb.yaml diff --git a/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig b/boards/ite/it8xxx2_evb/it8xxx2_evb_defconfig similarity index 83% rename from boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig rename to boards/ite/it8xxx2_evb/it8xxx2_evb_defconfig index 38a44d6f8f3..a73b3068d1e 100644 --- a/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig +++ b/boards/ite/it8xxx2_evb/it8xxx2_evb_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2020 ITE Corporation. All Rights Reserved. # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_ITE_IT8XXX2=y -CONFIG_SOC_IT8XXX2=y -CONFIG_BOARD_IT8XXX2_EVB=y CONFIG_BOOT_DELAY=1 CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/riscv/it8xxx2_evb/support/it8xxx2_evb.resc b/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc similarity index 100% rename from boards/riscv/it8xxx2_evb/support/it8xxx2_evb.resc rename to boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc diff --git a/boards/arm/frdm_k82f/CMakeLists.txt b/boards/khadas/edgev/CMakeLists.txt similarity index 100% rename from boards/arm/frdm_k82f/CMakeLists.txt rename to boards/khadas/edgev/CMakeLists.txt diff --git a/boards/khadas/edgev/Kconfig.khadas_edgev b/boards/khadas/edgev/Kconfig.khadas_edgev new file mode 100644 index 00000000000..324629cbc7f --- /dev/null +++ b/boards/khadas/edgev/Kconfig.khadas_edgev @@ -0,0 +1,7 @@ +# +# Copyright 2022 Huawei France Technologies SASU +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_KHADAS_EDGEV + select SOC_RK3399 diff --git a/boards/arm64/khadas_edgev/board.cmake b/boards/khadas/edgev/board.cmake similarity index 100% rename from boards/arm64/khadas_edgev/board.cmake rename to boards/khadas/edgev/board.cmake diff --git a/boards/khadas/edgev/board.yml b/boards/khadas/edgev/board.yml new file mode 100644 index 00000000000..fc70dcf0a44 --- /dev/null +++ b/boards/khadas/edgev/board.yml @@ -0,0 +1,5 @@ +board: + name: khadas_edgev + vendor: khadas + socs: + - name: rk3399 diff --git a/boards/khadas/edgev/doc/index.rst b/boards/khadas/edgev/doc/index.rst new file mode 100644 index 00000000000..2c73d109b09 --- /dev/null +++ b/boards/khadas/edgev/doc/index.rst @@ -0,0 +1,84 @@ +.. _khadas_edgev: + +Khadas Edge-V +################################# + +Overview +******** + +See + +Hardware +******** + +See + +Supported Features +================== + +Khadas Edge-V board default configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| GIC-500 | on-chip | GICv3 interrupt controller | ++-----------+------------+--------------------------------------+ +| ARM TIMER | on-chip | System Clock | ++-----------+------------+--------------------------------------+ +| UART | on-chip | Synopsys DesignWare 8250 serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in (NON-SMP) +:zephyr_file:`boards/khadas/edgev/khadas_edgev_defconfig` + +There are multiple serial ports on the board: Zephyr is using +uart2 as serial console. + +Programming and Debugging +************************* + +Use the following configuration to run basic Zephyr applications and +kernel tests on Khadas Edge-V board. For example, with the :ref:`hello_world`: + +1. Non-SMP mode + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: khadas_edgev + :goals: build + +This will build an image with the synchronization sample app. + +Build the zephyr image: + +.. code-block:: console + + mkimage -C none -A arm64 -O linux -a 0x10000000 -e 0x10000000 -d build/zephyr/zephyr.bin build/zephyr/zephyr.img + +Use u-boot to load and kick Zephyr.bin to CPU Core0: + +.. code-block:: console + + tftpboot ${pxefile_addr_r} zephyr.img; bootm start ${pxefile_addr_r}; bootm loados; bootm go + +It will display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build XXXXXXXXXXXX *** + Hello World! khadas_edgev + +Flashing +======== + +Zephyr image can be loaded in DDR memory at address 0x10000000 from SD Card, +EMMC, QSPI Flash or downloaded from network in uboot. + +References +========== + +`Documentation: `_ diff --git a/boards/arm64/khadas_edgev/khadas_edgev.dts b/boards/khadas/edgev/khadas_edgev.dts similarity index 100% rename from boards/arm64/khadas_edgev/khadas_edgev.dts rename to boards/khadas/edgev/khadas_edgev.dts diff --git a/boards/arm64/khadas_edgev/khadas_edgev.yaml b/boards/khadas/edgev/khadas_edgev.yaml similarity index 100% rename from boards/arm64/khadas_edgev/khadas_edgev.yaml rename to boards/khadas/edgev/khadas_edgev.yaml diff --git a/boards/arm64/khadas_edgev/khadas_edgev_defconfig b/boards/khadas/edgev/khadas_edgev_defconfig similarity index 81% rename from boards/arm64/khadas_edgev/khadas_edgev_defconfig rename to boards/khadas/edgev/khadas_edgev_defconfig index 6573521640f..44e7ed446c4 100644 --- a/boards/arm64/khadas_edgev/khadas_edgev_defconfig +++ b/boards/khadas/edgev/khadas_edgev_defconfig @@ -1,9 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 # Platform Configuration -CONFIG_SOC_SERIES_RK3399=y -CONFIG_SOC_RK3399=y -CONFIG_BOARD_KHADAS_EDGEV=y CONFIG_ARM64_VA_BITS_40=y CONFIG_ARM64_PA_BITS_40=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=24000000 diff --git a/boards/khadas/index.rst b/boards/khadas/index.rst new file mode 100644 index 00000000000..357dfc3543c --- /dev/null +++ b/boards/khadas/index.rst @@ -0,0 +1,10 @@ +.. _boards-khadas: + +Khadas +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/kincony/index.rst b/boards/kincony/index.rst new file mode 100644 index 00000000000..afa86ed0895 --- /dev/null +++ b/boards/kincony/index.rst @@ -0,0 +1,10 @@ +.. _boards-kincony: + +Kincony +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/kincony/kincony_kc868_a32/Kconfig b/boards/kincony/kincony_kc868_a32/Kconfig new file mode 100644 index 00000000000..446d0a838bd --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KINCONY_KC868_A32 + select SOC_ESP32_PROCPU if BOARD_KINCONY_KC868_A32_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_KINCONY_KC868_A32_ESP32_APPCPU diff --git a/boards/kincony/kincony_kc868_a32/Kconfig.defconfig b/boards/kincony/kincony_kc868_a32/Kconfig.defconfig new file mode 100644 index 00000000000..e8705a11f98 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Bartosz Bilas +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_KINCONY_KC868_A32_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_KINCONY_KC868_A32_ESP32_PROCPU + +if BOARD_KINCONY_KC868_A32_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_KINCONY_KC868_A32_ESP32_APPCPU diff --git a/boards/kincony/kincony_kc868_a32/Kconfig.kincony_kc868_a32 b/boards/kincony/kincony_kc868_a32/Kconfig.kincony_kc868_a32 new file mode 100644 index 00000000000..ad38ee9ab76 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/Kconfig.kincony_kc868_a32 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Bartosz Bilas +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KINCONY_KC868_A32 + select SOC_ESP32_WROOM_32UE_N4 diff --git a/boards/xtensa/kincony_kc868_a32/Kconfig.sysbuild b/boards/kincony/kincony_kc868_a32/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/kincony_kc868_a32/Kconfig.sysbuild rename to boards/kincony/kincony_kc868_a32/Kconfig.sysbuild diff --git a/boards/xtensa/kincony_kc868_a32/board.cmake b/boards/kincony/kincony_kc868_a32/board.cmake similarity index 100% rename from boards/xtensa/kincony_kc868_a32/board.cmake rename to boards/kincony/kincony_kc868_a32/board.cmake diff --git a/boards/kincony/kincony_kc868_a32/board.yml b/boards/kincony/kincony_kc868_a32/board.yml new file mode 100644 index 00000000000..99bf4fa715b --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/board.yml @@ -0,0 +1,5 @@ +board: + name: kincony_kc868_a32 + vendor: kincony + socs: + - name: esp32 diff --git a/boards/xtensa/kincony_kc868_a32/doc/img/kincony_kc868_a32.jpg b/boards/kincony/kincony_kc868_a32/doc/img/kincony_kc868_a32.jpg similarity index 100% rename from boards/xtensa/kincony_kc868_a32/doc/img/kincony_kc868_a32.jpg rename to boards/kincony/kincony_kc868_a32/doc/img/kincony_kc868_a32.jpg diff --git a/boards/kincony/kincony_kc868_a32/doc/index.rst b/boards/kincony/kincony_kc868_a32/doc/index.rst new file mode 100644 index 00000000000..a6117bec55e --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/doc/index.rst @@ -0,0 +1,97 @@ +.. _kincony_kc868_a32: + +KINCONY KC868-A32 +################# + +Overview +******** + +Kincony KC868-A32 is a home automation relay module based on the +Espressif ESP-WROOM-32 module with all its inherent capabilities +(Wi-Fi, Bluetooth, etc.) + +The features include the following: + +- 32 digital optoisolated inputs “dry contact” +- 4 analog inputs 0-5 V +- 32 relays 220 V, 10 A (COM, NO, NC) +- RS485 interface +- I2C connector +- Connector GSM/HMI +- Ethernet LAN8270A +- USB Type-B connector for programming and filling firmware +- RESET and DOWNLOAD buttons +- Powered by 12V DC + +.. figure:: img/kincony_kc868_a32.jpg + :align: center + :alt: KINCONCY-KC868-A32 + + KINCONCY-KC868-A32 + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: kincony_kc868_a32/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``kincony_kc868_a32`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: kincony_kc868_a32/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! kincony_kc868_a32 + +Enabling Ethernet +***************** + +Enable Ethernet in KConfig: + +.. code-block:: cfg + + CONFIG_NETWORKING=y + CONFIG_NET_L2_ETHERNET=y + CONFIG_MDIO=y + +References +********** + +.. _KINCONY KC868-A32 User Guide: https://www.kincony.com/arduino-esp32-32-channel-relay-module-kc868-a32.html diff --git a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32-pinctrl.dtsi b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32-pinctrl.dtsi similarity index 100% rename from boards/xtensa/kincony_kc868_a32/kincony_kc868_a32-pinctrl.dtsi rename to boards/kincony/kincony_kc868_a32/kincony_kc868_a32-pinctrl.dtsi diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.dts b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.dts new file mode 100644 index 00000000000..7940256ff29 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Kincony KC868_A32 APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.yaml b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.yaml new file mode 100644 index 00000000000..af75ec0edbc --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: kincony_kc868_a32/esp32/appcpu +name: ESP32 DEVKITC WROVER APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.dts b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.dts new file mode 100644 index 00000000000..0f459d7f7c5 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.dts @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2023 Bartosz Bilas + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "kincony_kc868_a32-pinctrl.dtsi" + +/ { + model = "Kincony KC868_A32 PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; + cpu-power-states = <&light_sleep &deep_sleep>; +}; + +&cpu1 { + clock-frequency = ; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 13 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + i2c0_pcf8574@21 { + compatible = "nxp,pcf857x"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c0_pcf8574@22 { + compatible = "nxp,pcf857x"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c0_pcf8574@24 { + compatible = "nxp,pcf857x"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c0_pcf8574@25 { + compatible = "nxp,pcf857x"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 5 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + + i2c1_pcf8574@21 { + compatible = "nxp,pcf857x"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c1_pcf8574@22 { + compatible = "nxp,pcf857x"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c1_pcf8574@24 { + compatible = "nxp,pcf857x"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c1_pcf8574@25 { + compatible = "nxp,pcf857x"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_default>; + pinctrl-names = "default"; + status = "okay"; + + phy: ethernet-phy@0 { + compatible = "ethernet-phy"; + status = "okay"; + reg = <0>; + }; +}; + +ð { + status = "okay"; + phy-handle = <&phy>; + ref-clk-output-gpios = <&gpio0 17 0>; +}; + +&psram0 { + status = "disabled"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.yaml b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.yaml new file mode 100644 index 00000000000..51ac12191f6 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.yaml @@ -0,0 +1,19 @@ +identifier: kincony_kc868_a32/esp32/procpu +name: KINCONY-KC868-A32 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - watchdog + - uart + - nvs + - counter + - entropy +testing: + ignore_tags: + - net + - bluetooth +vendor: kincony diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu_defconfig b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu_defconfig new file mode 100644 index 00000000000..071024ac98d --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) Bartosz Bilas +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/xtensa/kincony_kc868_a32/support/openocd.cfg b/boards/kincony/kincony_kc868_a32/support/openocd.cfg similarity index 100% rename from boards/xtensa/kincony_kc868_a32/support/openocd.cfg rename to boards/kincony/kincony_kc868_a32/support/openocd.cfg diff --git a/boards/lairdconnect/bl5340_dvk/CMakeLists.txt b/boards/lairdconnect/bl5340_dvk/CMakeLists.txt new file mode 100644 index 00000000000..ab8867f56a4 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2019 Nordic Semiconductor ASA. +# Copyright (c) 2021-2023 Laird Connectivity. +# SPDX-License-Identifier: Apache-2.0 + +if((CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS) + AND CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(bl5340_dvk_cpunet_reset.c) + + if(CONFIG_BUILD_WITH_TFM) + zephyr_library_include_directories( + $/api_ns/interface/include + ) + endif() +endif() diff --git a/boards/lairdconnect/bl5340_dvk/Kconfig b/boards/lairdconnect/bl5340_dvk/Kconfig new file mode 100644 index 00000000000..da61ea66547 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/Kconfig @@ -0,0 +1,62 @@ +# BL5340-DVK board configuration + +# Copyright (c) 2019-2021 Nordic Semiconductor ASA +# Copyright (c) 2021-2023 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "bl5340_dvk/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the bl5340_dvk_cpunet for + Bluetooth applications. + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +if BOARD_BL5340_DVK_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "bl5340_dvk/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340_dvk/Kconfig.bl5340_dvk b/boards/lairdconnect/bl5340_dvk/Kconfig.bl5340_dvk new file mode 100644 index 00000000000..7451d37b908 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/Kconfig.bl5340_dvk @@ -0,0 +1,9 @@ +# BL5340-DVK board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL5340_DVK + select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340_DVK_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340_dvk/Kconfig.defconfig b/boards/lairdconnect/bl5340_dvk/Kconfig.defconfig new file mode 100644 index 00000000000..65c005ee286 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/Kconfig.defconfig @@ -0,0 +1,119 @@ +# BL5340-DVK board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# Copyright (c) 2021-2023 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config I2C + default GPIO || DAC + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_BL5340_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +config BT_HCI_VS + default y if BT + +# 2.8" TFT Touch Shield for Arduino w/Capacitive Touch Screen Module +# is mounted to the DVK using standoffs. +# https://www.buydisplay.com/2-8-inch-tft-touch-shield-for-arduino-w-capacitive-touch-screen-module +if DISPLAY + +config INPUT_FT5336_INTERRUPT + default y + +if LVGL + +config LV_Z_VDB_SIZE + default 64 + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +config LV_COLOR_16_SWAP + default y + +config INPUT + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config IPM_NRFX + default IPM + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_BL5340_DVK_NRF5340_CPUNET + +# BT_CTLR depends on BT. When BT is enabled we should default to also +# enabling the controller. +config BT_CTLR + default y if BT + +config BT_ECC + default y if BT + +endif # BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts new file mode 100644 index 00000000000..7640e86e4aa --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl5340_dvk_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Laird Connectivity BL5340 (nRF5340) Application"; + compatible = "lairdconnect,bl5340-dvk-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + zephyr,sram-non-secure-partition = &sram0_ns; + }; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000..1b23d5f23ec --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml @@ -0,0 +1,22 @@ +identifier: bl5340_dvk/nrf5340/cpuapp +name: BL5340-DVK-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 448 +flash: 1024 +supported: + - counter + - gpio + - i2c + - pwm + - qspi + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: lairdconnect diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common-pinctrl.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common-pinctrl.dtsi rename to boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi new file mode 100644 index 00000000000..ff29e1f176e --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2019-2023 Nordic Semiconductor ASA + * Copyright (c) 2021-2023 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi" +#include + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,display = &ili9340; + zephyr,bt-hci-ipc = &ipc0; + }; + + /* Main LEDs and buttons are on an I2C TCA9538 GPIO port expander */ + /* Note TCA9538 does not have configurable internal pull ups/ downs */ + buttons { + compatible = "gpio-keys"; + boot_button0: boot_button { + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + label = "Bootloader button (S4)"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio_exp0 0 GPIO_ACTIVE_LOW>; + label = "Push button switch 1 (S1)"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio_exp0 1 GPIO_ACTIVE_LOW>; + label = "Push button switch 2 (S2)"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio_exp0 2 GPIO_ACTIVE_LOW>; + label = "Push button switch 3 (S9)"; + zephyr,code = ; + }; + + button4: button_4 { + gpios = <&gpio_exp0 3 GPIO_ACTIVE_LOW>; + label = "Push button switch 4 (S10)"; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio_exp0 4 GPIO_ACTIVE_LOW>; + label = "Blue LED 1"; + }; + led2: led_2 { + gpios = <&gpio_exp0 5 GPIO_ACTIVE_LOW>; + label = "Blue LED 2"; + }; + led3: led_3 { + gpios = <&gpio_exp0 6 GPIO_ACTIVE_LOW>; + label = "Blue LED 3"; + }; + led4: led_4 { + gpios = <&gpio_exp0 7 GPIO_ACTIVE_LOW>; + label = "Blue LED 4"; + }; + }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&ft5336>; + swap-xy; + invert-x; + invert-y; + }; + + gpio_fwd: nrf-gpio-forwarder { + compatible = "nordic,nrf-gpio-forwarder"; + status = "okay"; + uart { + gpios = <&gpio1 8 0>, <&gpio1 10 0>, <&gpio1 7 0>, <&gpio1 9 0>; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + led2 = &led3; + led3 = &led4; + sw0 = &button1; + sw1 = &button2; + sw2 = &button3; + sw3 = &button4; + mcuboot-button0 = &button1; + mcuboot-led0 = &led1; + sdhc0 = &sdhc0; + watchdog0 = &wdt0; + accel0 = &lis3dh; + bbram0 = &extrtc0; + spi-flash0 = &mx25r64; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + spi-dev = <&spi2>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + ili9340: ili9340@0 { + compatible = "ilitek,ili9340"; + reg = <0>; + mipi-max-frequency = <32000000>; + rotation = <270>; + width = <320>; + height = <240>; + }; + }; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c1 { + compatible = "nordic,nrf-twim"; + status = "okay"; + + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; + at24c256@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <32768>; + pagesize = <64>; + address-width = <16>; + timeout = <10>; + }; + + lis3dh: lis3dh@18 { + compatible = "st,lis2dh"; + reg = <0x18>; + irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>, <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; + + ft5336: ft5336@38 { + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + }; + + bme680@76 { + compatible = "bosch,bme680"; + reg = <0x76>; + }; + + dac0: mcp4725@60 { + compatible = "microchip,mcp4725"; + reg = <0x60>; + #io-channel-cells = <1>; + }; + + extrtc0: mcp7940n@6f { + compatible = "microchip,mcp7940n"; + reg = <0x6f>; + status = "okay"; + }; + + gpio_exp0: tca9538@70 { + compatible = "ti,tca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + nint-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; +}; + +&spi2 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi2_default>; + pinctrl-1 = <&spi2_sleep>; + pinctrl-names = "default", "sleep"; + enc424j600@0 { + compatible = "microchip,enc424j600"; + reg = <0>; + spi-max-frequency = <8000000>; + int-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + }; +}; + +&spi3 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + pinctrl-names = "default", "sleep"; + sdhc0: sdhc@0 { + reg = <0>; + compatible = "zephyr,sdhc-spi-slot"; + status = "okay"; + spi-max-frequency = <8000000>; + mmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + }; +}; + +&spi4 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi4_default>; + pinctrl-1 = <&spi4_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&qspi { + status = "okay"; + pinctrl-0 = <&qspi_default>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; + mx25r64: mx25r6435f@0 { + compatible = "nordic,qspi-nor"; + reg = <0>; + /* MX25R64 supports only pp and pp4io */ + writeoc = "pp4io"; + /* MX25R64 supports all readoc options */ + readoc = "read4io"; + sck-frequency = <8000000>; + jedec-id = [c2 28 17]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 64K */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + }; + /* 640K */ + slot0_partition: partition@10000 { + label = "image-0"; + }; + /* 256K */ + slot0_ns_partition: partition@b0000 { + label = "image-0-nonsecure"; + }; + + /* + * The flash starting at 0x000f8000 and ending at + * 0x000fffff is reserved for use by the application. + */ + + /* + * Storage partition will be used by FCB/NVS + * if enabled. 32K + */ + storage_partition: partition@f8000 { + label = "storage"; + reg = <0x000f8000 0x00008000>; + }; + }; +}; + +&mx25r64 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 640K */ + slot1_partition: partition@0 { + label = "image-1"; + }; + /* 256K */ + slot1_ns_partition: partition@A0000 { + label = "image-1-nonsecure"; + }; + /* 128K */ + scratch_partition: partition@e0000 { + label = "image-scratch"; + reg = <0x000e0000 0x00020000>; + }; + /* 7MB */ + lfs_partition: partition@100000 { + label = "lfs_storage"; + reg = <0x00100000 0x00700000>; + }; + }; +}; + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_image: image@20000000 { + /* Zephyr image(s) memory */ + }; + + sram0_s: image_s@20000000 { + /* Secure image memory */ + }; + + sram0_ns: image_ns@20040000 { + /* Non-Secure image memory */ + }; + }; +}; + +/* Include partition configuration file */ +#include "bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi" diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000..b60faf810bb --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Setup clocks +CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y +CONFIG_SOC_LFXO_CAP_INT_7PF=y +CONFIG_SOC_HFXO_CAP_INTERNAL=y +CONFIG_SOC_HFXO_CAP_INT_VALUE_X2=27 diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts new file mode 100644 index 00000000000..d159b8c4afe --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl5340_dvk_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Laird Connectivity BL5340 (nRF5340) Application"; + compatible = "lairdconnect,bl5340-dvk-cpuapp"; + + chosen { + zephyr,sram = &sram0_ns; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_ns_partition; + }; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml new file mode 100644 index 00000000000..087975c8d0d --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml @@ -0,0 +1,21 @@ +identifier: bl5340_dvk/nrf5340/cpuapp/ns +name: BL5340-DVK-application-MCU-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 192 +flash: 192 +supported: + - counter + - gpio + - i2c + - pwm + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: lairdconnect diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig new file mode 100644 index 00000000000..2a74dd56f41 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi new file mode 100644 index 00000000000..b85e3d03dc2 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2019-2020 Nordic Semiconductor ASA + * Copyright (c) 2021 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Default Flash planning for bl5340_dvk CPUAPP (Application MCU). + * + * Zephyr build for BL5340 with ARM TrustZone-M support + * implies building Secure and Non-Secure Zephyr images. + * + * Secure image will be placed, by default, in flash0 + * (or in slot0, if MCUboot is present). + * Secure image will use sram0 for system memory. + * + * Non-Secure image will be placed in slot0_ns, and use + * sram0_ns for system memory. + * + * Note that the Secure image only requires knowledge of + * the beginning of the Non-Secure image (not its size). + */ + +&slot0_partition { + reg = <0x00010000 0xa0000>; +}; + +&slot0_ns_partition { + reg = <0x000b0000 0x40000>; +}; + +&slot1_partition { + reg = <0x00000000 0xa0000>; +}; + +&slot1_ns_partition { + reg = <0x000a0000 0x40000>; +}; + +/* Default SRAM planning when building for nRF5340 with + * ARM TrustZone-M support + * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) + * - Middle 192 kB allocated to Non-Secure image (sram0_ns) + * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) + * (see bl5340_dvk_shared_sram_planning_conf.dtsi) + */ +&sram0_image { + reg = <0x20000000 DT_SIZE_K(448)>; +}; + +&sram0_s { + reg = <0x20000000 0x40000>; +}; + +&sram0_ns { + reg = <0x20040000 0x30000>; +}; + +/* Include shared RAM configuration file */ +#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet-pinctrl.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/bl5340_dvk/bl5340_dvk_cpunet-pinctrl.dtsi rename to boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts new file mode 100644 index 00000000000..4df761d0487 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021-2023 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi" +#include "bl5340_dvk_nrf5340_cpunet_common.dtsi" + +/ { + model = "Laird Connectivity BL5340 (nRF5340) Network"; + compatible = "lairdconnect,bl5340-dvk-cpunet"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,sram = &sram1; + zephyr,flash = &flash1; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci-ipc = &ipc0; + }; + + aliases { + watchdog0 = &wdt0; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml new file mode 100644 index 00000000000..d9727296714 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml @@ -0,0 +1,18 @@ +identifier: bl5340_dvk/nrf5340/cpunet +name: BL5340-DVK-network-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - counter + - gpio + - i2c + - spi + - uart + - watchdog +vendor: lairdconnect diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi new file mode 100644 index 00000000000..ce2e145d587 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2021-2023 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&flash1 { + /* + * For more information, see: + * http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 48K */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0xc000>; + }; + /* 88K */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000C000 0x16000>; + }; + /* 88K */ + slot1_partition: partition@22000 { + label = "image-1"; + reg = <0x00022000 0x16000>; + }; + /* 32K */ + storage_partition: partition@38000 { + label = "storage"; + reg = <0x00038000 0x8000>; + }; + }; +}; + +/* Include shared RAM configuration file */ +#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..56940c43a09 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_reset.c b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c similarity index 100% rename from boards/arm/bl5340_dvk/bl5340_dvk_cpunet_reset.c rename to boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c diff --git a/boards/arm/frdm_kl25z/CMakeLists.txt b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_defconfig similarity index 100% rename from boards/arm/frdm_kl25z/CMakeLists.txt rename to boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_defconfig diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_shared_sram_planning_conf.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi similarity index 100% rename from boards/arm/bl5340_dvk/bl5340_dvk_shared_sram_planning_conf.dtsi rename to boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi diff --git a/boards/lairdconnect/bl5340_dvk/board.cmake b/boards/lairdconnect/bl5340_dvk/board.cmake new file mode 100644 index 00000000000..15aec8e6a36 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/board.cmake @@ -0,0 +1,21 @@ +# Copyright (c) 2019 Nordic Semiconductor ASA +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(BOARD_BL5340_DVK_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/lairdconnect/bl5340_dvk/board.yml b/boards/lairdconnect/bl5340_dvk/board.yml new file mode 100644 index 00000000000..71343692f4c --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/board.yml @@ -0,0 +1,8 @@ +board: + name: bl5340_dvk + vendor: lairdconnect + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/arm/bl5340_dvk/doc/img/bl5340_dvk_top.jpg b/boards/lairdconnect/bl5340_dvk/doc/img/bl5340_dvk_top.jpg similarity index 100% rename from boards/arm/bl5340_dvk/doc/img/bl5340_dvk_top.jpg rename to boards/lairdconnect/bl5340_dvk/doc/img/bl5340_dvk_top.jpg diff --git a/boards/lairdconnect/bl5340_dvk/doc/index.rst b/boards/lairdconnect/bl5340_dvk/doc/index.rst new file mode 100644 index 00000000000..4148b639a6d --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/doc/index.rst @@ -0,0 +1,436 @@ +.. _bl5340_dvk: + +Laird Connectivity BL5340 DVK +############################# + +Overview +******** +The BL5340 Development Kit provides support for the Laird Connectivity +BL5340 module which is powered by a dual-core Nordic Semiconductor +nRF5340 ARM Cortex-M33F CPU. The nRF5340 inside the BL5340 module is a +dual-core SoC based on the Arm® Cortex®-M33 architecture, with: + +* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and + Armv8-M Security Extension, running at up to 128 MHz, referred to as + the **application core** +* a secondary Arm Cortex-M33 core, with a reduced feature set, running + at a fixed 64 MHz, referred to as the **network core**. + +The ``bl5340_dvk/nrf5340/cpuapp`` build target provides support for the application +core on the BL5340 module. The ``bl5340_dvk/nrf5340/cpunet`` build target provides +support for the network core on the BL5340 module. If ARM TrustZone is +used then the ``bl5340_dvk/nrf5340/cpuapp`` build target provides support for the +non-secure partition of the application core on the BL5340 module. + +This development kit has the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`I2S (Inter-Integrated Sound)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/bl5340_dvk_top.jpg + :align: center + :alt: BL5340 DVK + + BL5340 DVK (Credit: Laird Connectivity) + +More information about the module can be found on the +`BL5340 homepage`_. + +The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + +Hardware +******** + +The BL5340 DVK has two external oscillators. The frequency of +the slow clock is 32.768KHz. The frequency of the main clock +is 32MHz. + +Supported Features +================== + +The ``bl5340_dvk/nrf5340/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| QSPI(M) | on-chip | nor | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``bl5340_dvk/nrf5340/cpunet`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `Nordic Semiconductor Infocenter`_ +for a complete list of hardware features. + +Connections and IOs +=================== + +An eight-pin GPIO port expander is used to provide additional inputs +and outputs to the BL5340 module. + +Refer to the `TI TCA9538 datasheet`_ for further details. + +LEDs +---- + +* LED1 (blue) = via TCA9538 port expander channel P4 (active low) +* LED2 (blue) = via TCA9538 port expander channel P5 (active low) +* LED3 (blue) = via TCA9538 port expander channel P6 (active low) +* LED4 (blue) = via TCA9538 port expander channel P7 (active low) + +Push buttons +------------ + +* BUTTON1 = SW1 = via TCA9538 port expander channel P0 (active low) +* BUTTON2 = SW2 = via TCA9538 port expander channel P1 (active low) +* BUTTON3 = SW3 = via TCA9538 port expander channel P2 (active low) +* BUTTON4 = SW4 = via TCA9538 port expander channel P3 (active low) +* BOOT = boot (active low) + +External Memory +=============== + +Several external memory sources are available for the BL5340 DVK. These +are described as follows. + +Flash Memory +------------ + +A Macronix MX25R6435FZNIL0 8MB external QSPI Flash memory part is +incorporated for application image storage and large datasets. + +Refer to the `Macronix MX25R6435FZNIL0 datasheet`_ for further details. + +EEPROM Memory +------------- + +A 32KB Giantec GT24C256C-2GLI-TR EEPROM is available via I2C for +storage of infrequently updated data and small datasets. + +Refer to the `Giantec GT24C256C-2GLI-TR datasheet`_ for further details. + +External Memory +--------------- + +An on-board micro SD card slot is available for use with micro SD cards. + +Sensors +======= + +The BL5340 DVK incorporates two sensors for user application testing. +These are described as follows. + +Temperature, Pressure, Humidity & Air Quality Sensor +---------------------------------------------------- + +A Bosch BME680 Temperature, Pressure, Humidity & Air Quality sensor is +available via I2C for environmental measurement applications. + +Refer to the `Bosch BME680 datasheet`_ for further details. + +3-Axis Accelerometer +-------------------- + +An ST Microelectronics LIS3DH 3-Axis Accelerometer is available via I2C +for vibration and motion detection applications. + +Refer to the `ST Microelectronics LIS3DH datasheet`_ for further details. + +Ethernet +======== + +Cabled 10/100 Base-T Ethernet Connectivity is available via a Microchip +ENC424J600 Ethernet controller. + +Refer to the `Microchip ENC424J600 datasheet`_ for further details. + +TFT Display & Capacitive Touch Screen Controller +================================================ + +A 2.8 inch, 240 x 320 pixel TFT display with capacitive touch +controller is included with the BL5340 DVK for user interface +application features. + +Refer to the `ER_TFTM028_4 datasheet`_ for a high level overview of the +display. + +An ILI9341 TFT controller is incorporated in the TFT module and +acts as the main controller, controlled via SPI. + +Refer to the `ILI9341 datasheet`_ for further details. + +An FT6206 Capacitive Touch Controller, controlled via I2C is +also incorporated in the TFT module. + +Refer to the `FT6206 datasheet`_ for further details. + +Real-Time Clock +=============== + +A real-time clock is available for accurate time data availability. + +Refer to the `Microchip MCP7940N datasheet`_ for further details. + +DAC +=== + +A 10-bit Digital to Analog Converter is incorporated for generation of +variable voltages. + +Refer to the `Microchip MCP4725 datasheet`_ for further details. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_) on the application + core. The IDAU is implemented with the System Protection Unit and is + used to define secure and non-secure memory maps. By default, all of + the memory space (Flash, SRAM, and peripheral address space) is + defined to be secure accessible only. +- Secure boot. + +Programming and Debugging +************************* + +The BL5340's application core supports the Armv8-M Security Extension. +Applications built for the ``bl5340_dvk/nrf5340/cpuapp`` board by default +boot in the Secure state. + +The BL5340's network core does not support the Armv8-M Security +Extension. The IDAU may configure bus accesses by the network core to +have Secure attribute set; the latter allows to build and run Secure +only applications on the BL5340 module. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the BL5340 module may contain a Secure and a Non-Secure +firmware image for the application core. The Secure image can be built +using either Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure +firmware images are always built using Zephyr. The two alternatives are +described below. + +.. note:: + + By default the Secure image for BL5340's application core is + built using TF-M. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the +Non-Secure firmware image using Zephyr requires the following steps: + +1. Build the Non-Secure Zephyr application + for the application core using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output image binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may + be required, to adjust the Non-Secure image Flash and SRAM starting + address and sizes. + +2. Build the application firmware for the network core using + ``-DBOARD=bl5340_dvk/nrf5340/cpunet``. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process to build the Secure and the Non-Secure firmware images +using Zephyr requires the following steps: + +1. Build the Secure Zephyr application for the application core + using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` + in the application project configuration file. +2. Build the Non-Secure Zephyr application for the application core + using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``. +3. Merge the two binaries together. +4. Build the application firmware for the network core using + ``-DBOARD=bl5340_dvk/nrf5340/cpunet``. + +When building a Secure/Non-Secure application for the BL5340's +application core, the Secure application will have to set the IDAU +(SPU) configuration to allow Non-Secure access to all CPU resources +utilized by the Non-Secure application firmware. SPU configuration +shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` for +the firmware running on the BL5340's application core, and using +``-DBOARD=bl5340_dvk/nrf5340/cpunet`` for the firmware running +on the BL5340's network core. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then you can build and flash +applications as usual (:ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The BL5340 has a flash read-back protection feature. When flash + read-back protection is active, you will need to recover the chip + before reflashing. If you are flashing with + :ref:`west `, run this command for more + details on the related ``--recover`` option: + + .. code-block:: console + + west flash -H -r nrfjprog --skip-rebuild + +.. note:: + + Flashing and debugging applications on the BL5340 DVK requires + upgrading the nRF Command Line Tools to version 10.12.0 or newer. + Further information on how to install the nRF Command Line Tools can + be found in :ref:`nordic_segger_flashing`. + +Here is an example for the :ref:`hello_world` application running on the +BL5340's application core. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the BL5340 DVK board +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: bl5340_dvk/nrf5340/cpuapp + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +boards with a Segger IC. + +Testing Bluetooth on the BL5340 DVK +*********************************** +Many of the Bluetooth examples will work on the BL5340 DVK. +Try them out: + +* :ref:`ble_peripheral` +* :ref:`bluetooth-eddystone-sample` +* :ref:`bluetooth-ibeacon-sample` + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _BL5340 homepage: https://www.lairdconnect.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl5340-series-multi-core-bluetooth-52-802154-nfc-modules +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _TI TCA9538 datasheet: https://www.ti.com/lit/gpn/TCA9538 +.. _Macronix MX25R6435FZNIL0 datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.6.pdf +.. _Giantec GT24C256C-2GLI-TR datasheet: https://www.giantec-semi.com/juchen1123/uploads/pdf/GT24C256C_DS_Cu.pdf +.. _Bosch BME680 datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme680-ds001.pdf +.. _ST Microelectronics LIS3DH datasheet: https://www.st.com/resource/en/datasheet/lis3dh.pdf +.. _Microchip ENC424J600 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf +.. _ER_TFTM028_4 datasheet: https://www.buydisplay.com/download/manual/ER-TFTM028-4_Datasheet.pdf +.. _ILI9341 datasheet: https://www.buydisplay.com/download/ic/ILI9341.pdf +.. _FT6206 datasheet: https://www.buydisplay.com/download/ic/FT6206.pdf +.. _Microchip MCP7940N datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/20005010H.pdf +.. _Microchip MCP4725 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22039d.pdf +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/bl5340_dvk/pre_dt_board.cmake b/boards/lairdconnect/bl5340_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl5340_dvk/pre_dt_board.cmake rename to boards/lairdconnect/bl5340_dvk/pre_dt_board.cmake diff --git a/boards/arm/bl652_dvk/Kconfig b/boards/lairdconnect/bl652_dvk/Kconfig similarity index 100% rename from boards/arm/bl652_dvk/Kconfig rename to boards/lairdconnect/bl652_dvk/Kconfig diff --git a/boards/lairdconnect/bl652_dvk/Kconfig.bl652_dvk b/boards/lairdconnect/bl652_dvk/Kconfig.bl652_dvk new file mode 100644 index 00000000000..0a6881d76fd --- /dev/null +++ b/boards/lairdconnect/bl652_dvk/Kconfig.bl652_dvk @@ -0,0 +1,7 @@ +# BL652 DVK board configuration + +# Copyright (c) 2019 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL652_DVK + select SOC_NRF52832_QFAA diff --git a/boards/lairdconnect/bl652_dvk/Kconfig.defconfig b/boards/lairdconnect/bl652_dvk/Kconfig.defconfig new file mode 100644 index 00000000000..62fac3e6c21 --- /dev/null +++ b/boards/lairdconnect/bl652_dvk/Kconfig.defconfig @@ -0,0 +1,18 @@ +# BL652 DVK board configuration + +# Copyright (c) 2019 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL652_DVK + +config BT_CTLR + default BT + +if DAC + +config I2C + default y + +endif # DAC + +endif # BOARD_BL652_DVK diff --git a/boards/arm/bl652_dvk/bl652_dvk-pinctrl.dtsi b/boards/lairdconnect/bl652_dvk/bl652_dvk-pinctrl.dtsi similarity index 100% rename from boards/arm/bl652_dvk/bl652_dvk-pinctrl.dtsi rename to boards/lairdconnect/bl652_dvk/bl652_dvk-pinctrl.dtsi diff --git a/boards/arm/bl652_dvk/bl652_dvk.dts b/boards/lairdconnect/bl652_dvk/bl652_dvk.dts similarity index 100% rename from boards/arm/bl652_dvk/bl652_dvk.dts rename to boards/lairdconnect/bl652_dvk/bl652_dvk.dts diff --git a/boards/arm/bl652_dvk/bl652_dvk.yaml b/boards/lairdconnect/bl652_dvk/bl652_dvk.yaml similarity index 100% rename from boards/arm/bl652_dvk/bl652_dvk.yaml rename to boards/lairdconnect/bl652_dvk/bl652_dvk.yaml diff --git a/boards/arm/bl652_dvk/bl652_dvk_defconfig b/boards/lairdconnect/bl652_dvk/bl652_dvk_defconfig similarity index 81% rename from boards/arm/bl652_dvk/bl652_dvk_defconfig rename to boards/lairdconnect/bl652_dvk/bl652_dvk_defconfig index def931d42fc..a108273c64c 100644 --- a/boards/arm/bl652_dvk/bl652_dvk_defconfig +++ b/boards/lairdconnect/bl652_dvk/bl652_dvk_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_BL652_DVK=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bl652_dvk/board.cmake b/boards/lairdconnect/bl652_dvk/board.cmake similarity index 100% rename from boards/arm/bl652_dvk/board.cmake rename to boards/lairdconnect/bl652_dvk/board.cmake diff --git a/boards/lairdconnect/bl652_dvk/board.yml b/boards/lairdconnect/bl652_dvk/board.yml new file mode 100644 index 00000000000..2c2e672ec80 --- /dev/null +++ b/boards/lairdconnect/bl652_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: bl652_dvk + vendor: lairdconnect + socs: + - name: nrf52832 diff --git a/boards/arm/bl652_dvk/doc/bl652_dvk.rst b/boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst similarity index 99% rename from boards/arm/bl652_dvk/doc/bl652_dvk.rst rename to boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst index 9d14b847fb9..a0d6657d4c1 100644 --- a/boards/arm/bl652_dvk/doc/bl652_dvk.rst +++ b/boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst @@ -260,7 +260,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/bl652_dvk/bl652_dvk.dts`. +:zephyr_file:`boards/laird_connect/bl652_dvk/bl652_dvk.dts`. References ********** diff --git a/boards/arm/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg b/boards/lairdconnect/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg similarity index 100% rename from boards/arm/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg rename to boards/lairdconnect/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg diff --git a/boards/arm/bl652_dvk/doc/img/bl652_dvk.jpg b/boards/lairdconnect/bl652_dvk/doc/img/bl652_dvk.jpg similarity index 100% rename from boards/arm/bl652_dvk/doc/img/bl652_dvk.jpg rename to boards/lairdconnect/bl652_dvk/doc/img/bl652_dvk.jpg diff --git a/boards/arm/bt610/pre_dt_board.cmake b/boards/lairdconnect/bl652_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/bt610/pre_dt_board.cmake rename to boards/lairdconnect/bl652_dvk/pre_dt_board.cmake diff --git a/boards/arm/bl653_dvk/Kconfig b/boards/lairdconnect/bl653_dvk/Kconfig similarity index 100% rename from boards/arm/bl653_dvk/Kconfig rename to boards/lairdconnect/bl653_dvk/Kconfig diff --git a/boards/lairdconnect/bl653_dvk/Kconfig.bl653_dvk b/boards/lairdconnect/bl653_dvk/Kconfig.bl653_dvk new file mode 100644 index 00000000000..65fd5c9a277 --- /dev/null +++ b/boards/lairdconnect/bl653_dvk/Kconfig.bl653_dvk @@ -0,0 +1,7 @@ +# BL653 DVK board configuration + +# Copyright (c) 2020 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL653_DVK + select SOC_NRF52833_QIAA diff --git a/boards/lairdconnect/bl653_dvk/Kconfig.defconfig b/boards/lairdconnect/bl653_dvk/Kconfig.defconfig new file mode 100644 index 00000000000..43f19f65a6d --- /dev/null +++ b/boards/lairdconnect/bl653_dvk/Kconfig.defconfig @@ -0,0 +1,18 @@ +# BL653 DVK board configuration + +# Copyright (c) 2020 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL653_DVK + +config BT_CTLR + default BT + +if DAC + +config I2C + default y + +endif # DAC + +endif # BOARD_BL653_DVK diff --git a/boards/arm/bl653_dvk/bl653_dvk-pinctrl.dtsi b/boards/lairdconnect/bl653_dvk/bl653_dvk-pinctrl.dtsi similarity index 100% rename from boards/arm/bl653_dvk/bl653_dvk-pinctrl.dtsi rename to boards/lairdconnect/bl653_dvk/bl653_dvk-pinctrl.dtsi diff --git a/boards/arm/bl653_dvk/bl653_dvk.dts b/boards/lairdconnect/bl653_dvk/bl653_dvk.dts similarity index 100% rename from boards/arm/bl653_dvk/bl653_dvk.dts rename to boards/lairdconnect/bl653_dvk/bl653_dvk.dts diff --git a/boards/arm/bl653_dvk/bl653_dvk.yaml b/boards/lairdconnect/bl653_dvk/bl653_dvk.yaml similarity index 100% rename from boards/arm/bl653_dvk/bl653_dvk.yaml rename to boards/lairdconnect/bl653_dvk/bl653_dvk.yaml diff --git a/boards/arm/bl653_dvk/bl653_dvk_defconfig b/boards/lairdconnect/bl653_dvk/bl653_dvk_defconfig similarity index 80% rename from boards/arm/bl653_dvk/bl653_dvk_defconfig rename to boards/lairdconnect/bl653_dvk/bl653_dvk_defconfig index b1abe06089c..e61d78a6a18 100644 --- a/boards/arm/bl653_dvk/bl653_dvk_defconfig +++ b/boards/lairdconnect/bl653_dvk/bl653_dvk_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_BL653_DVK=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bl653_dvk/board.cmake b/boards/lairdconnect/bl653_dvk/board.cmake similarity index 100% rename from boards/arm/bl653_dvk/board.cmake rename to boards/lairdconnect/bl653_dvk/board.cmake diff --git a/boards/lairdconnect/bl653_dvk/board.yml b/boards/lairdconnect/bl653_dvk/board.yml new file mode 100644 index 00000000000..c898247f1f3 --- /dev/null +++ b/boards/lairdconnect/bl653_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: bl653_dvk + vendor: lairdconnect + socs: + - name: nrf52833 diff --git a/boards/arm/bl653_dvk/doc/bl653_dvk.rst b/boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst similarity index 99% rename from boards/arm/bl653_dvk/doc/bl653_dvk.rst rename to boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst index ee5996e81ae..8e4c76b4d09 100644 --- a/boards/arm/bl653_dvk/doc/bl653_dvk.rst +++ b/boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst @@ -167,7 +167,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/bl653_dvk/bl653_dvk.dts`. +:zephyr_file:`boards/laird_connect/bl653_dvk/bl653_dvk.dts`. Using UART1 *********** diff --git a/boards/arm/bl653_dvk/doc/img/bl653_dvk.jpg b/boards/lairdconnect/bl653_dvk/doc/img/bl653_dvk.jpg similarity index 100% rename from boards/arm/bl653_dvk/doc/img/bl653_dvk.jpg rename to boards/lairdconnect/bl653_dvk/doc/img/bl653_dvk.jpg diff --git a/boards/arm/contextualelectronics_abc/pre_dt_board.cmake b/boards/lairdconnect/bl653_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/contextualelectronics_abc/pre_dt_board.cmake rename to boards/lairdconnect/bl653_dvk/pre_dt_board.cmake diff --git a/boards/arm/bl654_dvk/Kconfig b/boards/lairdconnect/bl654_dvk/Kconfig similarity index 100% rename from boards/arm/bl654_dvk/Kconfig rename to boards/lairdconnect/bl654_dvk/Kconfig diff --git a/boards/lairdconnect/bl654_dvk/Kconfig.bl654_dvk b/boards/lairdconnect/bl654_dvk/Kconfig.bl654_dvk new file mode 100644 index 00000000000..ec8ac37b241 --- /dev/null +++ b/boards/lairdconnect/bl654_dvk/Kconfig.bl654_dvk @@ -0,0 +1,7 @@ +# BL654 DVK board configuration + +# Copyright (c) 2019 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL654_DVK + select SOC_NRF52840_QIAA diff --git a/boards/lairdconnect/bl654_dvk/Kconfig.defconfig b/boards/lairdconnect/bl654_dvk/Kconfig.defconfig new file mode 100644 index 00000000000..facb6117693 --- /dev/null +++ b/boards/lairdconnect/bl654_dvk/Kconfig.defconfig @@ -0,0 +1,18 @@ +# BL654 DVK board configuration + +# Copyright (c) 2019 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL654_DVK + +config BT_CTLR + default BT + +if DAC + +config I2C + default y + +endif # DAC + +endif # BOARD_BL654_DVK diff --git a/boards/arm/bl654_dvk/bl654_dvk-pinctrl.dtsi b/boards/lairdconnect/bl654_dvk/bl654_dvk-pinctrl.dtsi similarity index 100% rename from boards/arm/bl654_dvk/bl654_dvk-pinctrl.dtsi rename to boards/lairdconnect/bl654_dvk/bl654_dvk-pinctrl.dtsi diff --git a/boards/arm/bl654_dvk/bl654_dvk.dts b/boards/lairdconnect/bl654_dvk/bl654_dvk.dts similarity index 100% rename from boards/arm/bl654_dvk/bl654_dvk.dts rename to boards/lairdconnect/bl654_dvk/bl654_dvk.dts diff --git a/boards/arm/bl654_dvk/bl654_dvk.yaml b/boards/lairdconnect/bl654_dvk/bl654_dvk.yaml similarity index 100% rename from boards/arm/bl654_dvk/bl654_dvk.yaml rename to boards/lairdconnect/bl654_dvk/bl654_dvk.yaml diff --git a/boards/arm/bl654_dvk/bl654_dvk_defconfig b/boards/lairdconnect/bl654_dvk/bl654_dvk_defconfig similarity index 81% rename from boards/arm/bl654_dvk/bl654_dvk_defconfig rename to boards/lairdconnect/bl654_dvk/bl654_dvk_defconfig index 7d5b17577b2..a108273c64c 100644 --- a/boards/arm/bl654_dvk/bl654_dvk_defconfig +++ b/boards/lairdconnect/bl654_dvk/bl654_dvk_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_BL654_DVK=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bl654_dvk/board.cmake b/boards/lairdconnect/bl654_dvk/board.cmake similarity index 100% rename from boards/arm/bl654_dvk/board.cmake rename to boards/lairdconnect/bl654_dvk/board.cmake diff --git a/boards/lairdconnect/bl654_dvk/board.yml b/boards/lairdconnect/bl654_dvk/board.yml new file mode 100644 index 00000000000..26fbd0e33bd --- /dev/null +++ b/boards/lairdconnect/bl654_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: bl654_dvk + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/bl654_dvk/doc/bl654_dvk.rst b/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst similarity index 98% rename from boards/arm/bl654_dvk/doc/bl654_dvk.rst rename to boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst index c70afb78729..f4cbc11e332 100644 --- a/boards/arm/bl654_dvk/doc/bl654_dvk.rst +++ b/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst @@ -173,7 +173,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/bl654_dvk/bl654_dvk.dts`. +:zephyr_file:`boards/laird_connect/bl654_dvk/bl654_dvk.dts`. References diff --git a/boards/arm/bl654_dvk/doc/img/455-00001_BoxContents.jpg b/boards/lairdconnect/bl654_dvk/doc/img/455-00001_BoxContents.jpg similarity index 100% rename from boards/arm/bl654_dvk/doc/img/455-00001_BoxContents.jpg rename to boards/lairdconnect/bl654_dvk/doc/img/455-00001_BoxContents.jpg diff --git a/boards/arm/bl654_dvk/doc/img/bl654_dvk.jpg b/boards/lairdconnect/bl654_dvk/doc/img/bl654_dvk.jpg similarity index 100% rename from boards/arm/bl654_dvk/doc/img/bl654_dvk.jpg rename to boards/lairdconnect/bl654_dvk/doc/img/bl654_dvk.jpg diff --git a/boards/arm/decawave_dwm1001_dev/pre_dt_board.cmake b/boards/lairdconnect/bl654_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/decawave_dwm1001_dev/pre_dt_board.cmake rename to boards/lairdconnect/bl654_dvk/pre_dt_board.cmake diff --git a/boards/arm/bl654_sensor_board/Kconfig b/boards/lairdconnect/bl654_sensor_board/Kconfig similarity index 100% rename from boards/arm/bl654_sensor_board/Kconfig rename to boards/lairdconnect/bl654_sensor_board/Kconfig diff --git a/boards/lairdconnect/bl654_sensor_board/Kconfig.bl654_sensor_board b/boards/lairdconnect/bl654_sensor_board/Kconfig.bl654_sensor_board new file mode 100644 index 00000000000..71ff5ad2f6f --- /dev/null +++ b/boards/lairdconnect/bl654_sensor_board/Kconfig.bl654_sensor_board @@ -0,0 +1,7 @@ +# BL654 Sensor Board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL654_SENSOR_BOARD + select SOC_NRF52840_QIAA diff --git a/boards/lairdconnect/bl654_sensor_board/Kconfig.defconfig b/boards/lairdconnect/bl654_sensor_board/Kconfig.defconfig new file mode 100644 index 00000000000..3ac458bcec9 --- /dev/null +++ b/boards/lairdconnect/bl654_sensor_board/Kconfig.defconfig @@ -0,0 +1,11 @@ +# BL654 Sensor Board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL654_SENSOR_BOARD + +config BT_CTLR + default BT + +endif # BOARD_BL654_SENSOR_BOARD diff --git a/boards/arm/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi b/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi similarity index 100% rename from boards/arm/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi rename to boards/lairdconnect/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi diff --git a/boards/arm/bl654_sensor_board/bl654_sensor_board.dts b/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.dts similarity index 100% rename from boards/arm/bl654_sensor_board/bl654_sensor_board.dts rename to boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.dts diff --git a/boards/arm/bl654_sensor_board/bl654_sensor_board.yaml b/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.yaml similarity index 100% rename from boards/arm/bl654_sensor_board/bl654_sensor_board.yaml rename to boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.yaml diff --git a/boards/arm/bl654_sensor_board/bl654_sensor_board_defconfig b/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board_defconfig similarity index 77% rename from boards/arm/bl654_sensor_board/bl654_sensor_board_defconfig rename to boards/lairdconnect/bl654_sensor_board/bl654_sensor_board_defconfig index f8352265d3f..fedbabc0837 100644 --- a/boards/arm/bl654_sensor_board/bl654_sensor_board_defconfig +++ b/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_BL654_SENSOR_BOARD=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bl654_sensor_board/board.cmake b/boards/lairdconnect/bl654_sensor_board/board.cmake similarity index 100% rename from boards/arm/bl654_sensor_board/board.cmake rename to boards/lairdconnect/bl654_sensor_board/board.cmake diff --git a/boards/lairdconnect/bl654_sensor_board/board.yml b/boards/lairdconnect/bl654_sensor_board/board.yml new file mode 100644 index 00000000000..ebe40b44601 --- /dev/null +++ b/boards/lairdconnect/bl654_sensor_board/board.yml @@ -0,0 +1,5 @@ +board: + name: bl654_sensor_board + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/bl654_sensor_board/doc/bl654_sensor_board.rst b/boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst similarity index 99% rename from boards/arm/bl654_sensor_board/doc/bl654_sensor_board.rst rename to boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst index 673eed4eefb..b3114b2948f 100644 --- a/boards/arm/bl654_sensor_board/doc/bl654_sensor_board.rst +++ b/boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst @@ -238,7 +238,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/bl654_sensor_board/bl654_sensor_board.dts`. +:zephyr_file:`boards/laird_connect/bl654_sensor_board/bl654_sensor_board.dts`. References diff --git a/boards/arm/bl654_sensor_board/doc/img/bl654_sensor_board.jpg b/boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board.jpg similarity index 100% rename from boards/arm/bl654_sensor_board/doc/img/bl654_sensor_board.jpg rename to boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board.jpg diff --git a/boards/arm/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg b/boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg similarity index 100% rename from boards/arm/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg rename to boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg diff --git a/boards/arm/degu_evk/pre_dt_board.cmake b/boards/lairdconnect/bl654_sensor_board/pre_dt_board.cmake similarity index 100% rename from boards/arm/degu_evk/pre_dt_board.cmake rename to boards/lairdconnect/bl654_sensor_board/pre_dt_board.cmake diff --git a/boards/arm/bl654_usb/Kconfig b/boards/lairdconnect/bl654_usb/Kconfig similarity index 100% rename from boards/arm/bl654_usb/Kconfig rename to boards/lairdconnect/bl654_usb/Kconfig diff --git a/boards/lairdconnect/bl654_usb/Kconfig.bl654_usb b/boards/lairdconnect/bl654_usb/Kconfig.bl654_usb new file mode 100644 index 00000000000..0dba254491a --- /dev/null +++ b/boards/lairdconnect/bl654_usb/Kconfig.bl654_usb @@ -0,0 +1,7 @@ +# BL654 USB adapter board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL654_USB + select SOC_NRF52840_QIAA diff --git a/boards/lairdconnect/bl654_usb/Kconfig.defconfig b/boards/lairdconnect/bl654_usb/Kconfig.defconfig new file mode 100644 index 00000000000..baf624a0c5a --- /dev/null +++ b/boards/lairdconnect/bl654_usb/Kconfig.defconfig @@ -0,0 +1,59 @@ +# BL654 USB adapter board configuration + +# Copyright (c) 2021-2022 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL654_USB + +# To let the nRF5 bootloader load an application, the application +# must be linked after Nordic MBR, that is factory-programmed on the board. + +# Nordic nRF5 bootloader exists outside of the partitions specified in the +# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application +# correctly, after Nordic MBR, and limit the maximum size to not protude into +# the bootloader at the end of flash. + +# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION +# which will make it link into the correct partition specified in DTS file, +# so no override or limit is necessary. + +config FLASH_LOAD_OFFSET + default 0x1000 + depends on !USE_DT_CODE_PARTITION + +config FLASH_LOAD_SIZE + default 0xdf000 + depends on !USE_DT_CODE_PARTITION + +config USB_CDC_ACM + default n if USB_DEVICE_BLUETOOTH + +if BL654_USB_SERIAL_BACKEND_CDCACM + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if !MCUBOOT + +config SHELL_BACKEND_SERIAL_CHECK_DTR + default SHELL + depends on UART_LINE_CTRL + +config UART_LINE_CTRL + default SHELL + +# Logger cannot use itself to log +config USB_CDC_ACM_LOG_LEVEL + default 0 + +# Set USB log level to error only +config USB_DEVICE_LOG_LEVEL + default 1 + +endif #BL654_USB_SERIAL_BACKEND_CDCACM + +config BT_CTLR + default BT + +endif # BOARD_BL654_USB diff --git a/boards/arm/bl654_usb/bl654_usb-pinctrl.dtsi b/boards/lairdconnect/bl654_usb/bl654_usb-pinctrl.dtsi similarity index 100% rename from boards/arm/bl654_usb/bl654_usb-pinctrl.dtsi rename to boards/lairdconnect/bl654_usb/bl654_usb-pinctrl.dtsi diff --git a/boards/arm/bl654_usb/bl654_usb.dts b/boards/lairdconnect/bl654_usb/bl654_usb.dts similarity index 100% rename from boards/arm/bl654_usb/bl654_usb.dts rename to boards/lairdconnect/bl654_usb/bl654_usb.dts diff --git a/boards/arm/bl654_usb/bl654_usb.yaml b/boards/lairdconnect/bl654_usb/bl654_usb.yaml similarity index 100% rename from boards/arm/bl654_usb/bl654_usb.yaml rename to boards/lairdconnect/bl654_usb/bl654_usb.yaml diff --git a/boards/arm/bl654_usb/bl654_usb_defconfig b/boards/lairdconnect/bl654_usb/bl654_usb_defconfig similarity index 79% rename from boards/arm/bl654_usb/bl654_usb_defconfig rename to boards/lairdconnect/bl654_usb/bl654_usb_defconfig index b51d0c1d99e..ba7d61d55be 100644 --- a/boards/arm/bl654_usb/bl654_usb_defconfig +++ b/boards/lairdconnect/bl654_usb/bl654_usb_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_BL654_USB=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/lairdconnect/bl654_usb/board.yml b/boards/lairdconnect/bl654_usb/board.yml new file mode 100644 index 00000000000..dc616554605 --- /dev/null +++ b/boards/lairdconnect/bl654_usb/board.yml @@ -0,0 +1,5 @@ +board: + name: bl654_usb + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/bl654_usb/doc/bl654_usb.rst b/boards/lairdconnect/bl654_usb/doc/bl654_usb.rst similarity index 95% rename from boards/arm/bl654_usb/doc/bl654_usb.rst rename to boards/lairdconnect/bl654_usb/doc/bl654_usb.rst index 5d4fdc774de..d2fd722f504 100644 --- a/boards/arm/bl654_usb/doc/bl654_usb.rst +++ b/boards/lairdconnect/bl654_usb/doc/bl654_usb.rst @@ -103,9 +103,9 @@ Programming and Debugging Applications for the ``bl654_usb`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). The -``bl654_usb`` board cannot be used for debugging. The compatible BL654_DVK -board can be used for development. Documentation can be found at the `BL654_DVK -Zephyr site`_ and :zephyr_file:`boards/arm/bl654_dvk/doc/bl654_dvk.rst` +``bl654_usb`` board cannot be used for debugging. The compatible BL654 DVK +board can be used for development. Documentation can be found at the :ref:`bl654_dvk` +site and :zephyr_file:`boards/laird_connect/bl654_dvk/doc/bl654_dvk.rst` Flashing ======== @@ -175,7 +175,7 @@ the board is working properly with Zephyr: You can build and flash the example to make sure Zephyr is running correctly on your board. The LED definitions can be found in -:zephyr_file:`boards/arm/bl654_usb/bl654_usb.dts`. +:zephyr_file:`boards/laird_connect/bl654_usb/bl654_usb.dts`. References @@ -188,4 +188,3 @@ References .. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html .. _Creating a secure bootloader image: https://www.lairdconnect.com/documentation/application-note-creating-secure-bootloader-image-bl654-usb .. _nrfutil: https://github.com/NordicSemiconductor/pc-nrfutil -.. _BL654_DVK Zephyr site: https://docs.zephyrproject.org/latest/boards/arm/bl654_dvk/doc/bl654_dvk.html diff --git a/boards/arm/bl654_usb/doc/img/bl654_usb.jpg b/boards/lairdconnect/bl654_usb/doc/img/bl654_usb.jpg similarity index 100% rename from boards/arm/bl654_usb/doc/img/bl654_usb.jpg rename to boards/lairdconnect/bl654_usb/doc/img/bl654_usb.jpg diff --git a/boards/arm/bl654_usb/doc/img/bl654_usb_pcb.jpg b/boards/lairdconnect/bl654_usb/doc/img/bl654_usb_pcb.jpg similarity index 100% rename from boards/arm/bl654_usb/doc/img/bl654_usb_pcb.jpg rename to boards/lairdconnect/bl654_usb/doc/img/bl654_usb_pcb.jpg diff --git a/boards/arm/bl654_usb/doc/img/bl654_usb_reset.jpg b/boards/lairdconnect/bl654_usb/doc/img/bl654_usb_reset.jpg similarity index 100% rename from boards/arm/bl654_usb/doc/img/bl654_usb_reset.jpg rename to boards/lairdconnect/bl654_usb/doc/img/bl654_usb_reset.jpg diff --git a/boards/arm/holyiot_yj16019/pre_dt_board.cmake b/boards/lairdconnect/bl654_usb/pre_dt_board.cmake similarity index 100% rename from boards/arm/holyiot_yj16019/pre_dt_board.cmake rename to boards/lairdconnect/bl654_usb/pre_dt_board.cmake diff --git a/boards/arm/bt510/Kconfig b/boards/lairdconnect/bt510/Kconfig similarity index 100% rename from boards/arm/bt510/Kconfig rename to boards/lairdconnect/bt510/Kconfig diff --git a/boards/lairdconnect/bt510/Kconfig.bt510 b/boards/lairdconnect/bt510/Kconfig.bt510 new file mode 100644 index 00000000000..20a34044970 --- /dev/null +++ b/boards/lairdconnect/bt510/Kconfig.bt510 @@ -0,0 +1,7 @@ +# BT510 DVK board configuration + +# Copyright (c) 2020 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BT510 + select SOC_NRF52840_QIAA diff --git a/boards/lairdconnect/bt510/Kconfig.defconfig b/boards/lairdconnect/bt510/Kconfig.defconfig new file mode 100644 index 00000000000..70cb87fa1f7 --- /dev/null +++ b/boards/lairdconnect/bt510/Kconfig.defconfig @@ -0,0 +1,14 @@ +# BT510 Sensor configuration + +# Copyright (c) 2020 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BT510 + +config BT_CTLR + default BT + +config I2C + default SENSOR + +endif # BOARD_BT510 diff --git a/boards/arm/bt510/board.cmake b/boards/lairdconnect/bt510/board.cmake similarity index 100% rename from boards/arm/bt510/board.cmake rename to boards/lairdconnect/bt510/board.cmake diff --git a/boards/lairdconnect/bt510/board.yml b/boards/lairdconnect/bt510/board.yml new file mode 100644 index 00000000000..1a9760895ec --- /dev/null +++ b/boards/lairdconnect/bt510/board.yml @@ -0,0 +1,5 @@ +board: + name: bt510 + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/bt510/bt510-pinctrl.dtsi b/boards/lairdconnect/bt510/bt510-pinctrl.dtsi similarity index 100% rename from boards/arm/bt510/bt510-pinctrl.dtsi rename to boards/lairdconnect/bt510/bt510-pinctrl.dtsi diff --git a/boards/arm/bt510/bt510.dts b/boards/lairdconnect/bt510/bt510.dts similarity index 100% rename from boards/arm/bt510/bt510.dts rename to boards/lairdconnect/bt510/bt510.dts diff --git a/boards/arm/bt510/bt510.yaml b/boards/lairdconnect/bt510/bt510.yaml similarity index 100% rename from boards/arm/bt510/bt510.yaml rename to boards/lairdconnect/bt510/bt510.yaml diff --git a/boards/arm/bt510/bt510_defconfig b/boards/lairdconnect/bt510/bt510_defconfig similarity index 79% rename from boards/arm/bt510/bt510_defconfig rename to boards/lairdconnect/bt510/bt510_defconfig index cd897918fe1..c4cc98bc3b7 100644 --- a/boards/arm/bt510/bt510_defconfig +++ b/boards/lairdconnect/bt510/bt510_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_BT510=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bt510/doc/bt510.rst b/boards/lairdconnect/bt510/doc/bt510.rst similarity index 99% rename from boards/arm/bt510/doc/bt510.rst rename to boards/lairdconnect/bt510/doc/bt510.rst index 841c27b85d6..cbee5deabb8 100644 --- a/boards/arm/bt510/doc/bt510.rst +++ b/boards/lairdconnect/bt510/doc/bt510.rst @@ -244,7 +244,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button, LED and sensor device definitions can be found in -:zephyr_file:`boards/arm/bt510/bt510.dts`. +:zephyr_file:`boards/laird_connect/bt510/bt510.dts`. References diff --git a/boards/arm/bt510/doc/img/bt510.jpg b/boards/lairdconnect/bt510/doc/img/bt510.jpg similarity index 100% rename from boards/arm/bt510/doc/img/bt510.jpg rename to boards/lairdconnect/bt510/doc/img/bt510.jpg diff --git a/boards/arm/bt510/doc/img/bt510_back.jpg b/boards/lairdconnect/bt510/doc/img/bt510_back.jpg similarity index 100% rename from boards/arm/bt510/doc/img/bt510_back.jpg rename to boards/lairdconnect/bt510/doc/img/bt510_back.jpg diff --git a/boards/arm/bt510/doc/img/bt510_prog.jpg b/boards/lairdconnect/bt510/doc/img/bt510_prog.jpg similarity index 100% rename from boards/arm/bt510/doc/img/bt510_prog.jpg rename to boards/lairdconnect/bt510/doc/img/bt510_prog.jpg diff --git a/boards/arm/mg100/pre_dt_board.cmake b/boards/lairdconnect/bt510/pre_dt_board.cmake similarity index 100% rename from boards/arm/mg100/pre_dt_board.cmake rename to boards/lairdconnect/bt510/pre_dt_board.cmake diff --git a/boards/arm/bt610/Kconfig b/boards/lairdconnect/bt610/Kconfig similarity index 100% rename from boards/arm/bt610/Kconfig rename to boards/lairdconnect/bt610/Kconfig diff --git a/boards/lairdconnect/bt610/Kconfig.bt610 b/boards/lairdconnect/bt610/Kconfig.bt610 new file mode 100644 index 00000000000..c87453d32a9 --- /dev/null +++ b/boards/lairdconnect/bt610/Kconfig.bt610 @@ -0,0 +1,7 @@ +# BT610 board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BT610 + select SOC_NRF52840_QIAA diff --git a/boards/lairdconnect/bt610/Kconfig.defconfig b/boards/lairdconnect/bt610/Kconfig.defconfig new file mode 100644 index 00000000000..9a82770655e --- /dev/null +++ b/boards/lairdconnect/bt610/Kconfig.defconfig @@ -0,0 +1,14 @@ +# BT6X0 Sensor configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BT610 + +config BT_CTLR + default BT + +config I2C + default $(dt_compat_on_bus,$(DT_COMPAT_TI_TCA9538),i2c) + +endif # BOARD_BT610 diff --git a/boards/arm/bt610/board.cmake b/boards/lairdconnect/bt610/board.cmake similarity index 100% rename from boards/arm/bt610/board.cmake rename to boards/lairdconnect/bt610/board.cmake diff --git a/boards/lairdconnect/bt610/board.yml b/boards/lairdconnect/bt610/board.yml new file mode 100644 index 00000000000..c5a846a0d8d --- /dev/null +++ b/boards/lairdconnect/bt610/board.yml @@ -0,0 +1,5 @@ +board: + name: bt610 + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/bt610/bt610-pinctrl.dtsi b/boards/lairdconnect/bt610/bt610-pinctrl.dtsi similarity index 100% rename from boards/arm/bt610/bt610-pinctrl.dtsi rename to boards/lairdconnect/bt610/bt610-pinctrl.dtsi diff --git a/boards/arm/bt610/bt610.dts b/boards/lairdconnect/bt610/bt610.dts similarity index 100% rename from boards/arm/bt610/bt610.dts rename to boards/lairdconnect/bt610/bt610.dts diff --git a/boards/arm/bt610/bt610.yaml b/boards/lairdconnect/bt610/bt610.yaml similarity index 100% rename from boards/arm/bt610/bt610.yaml rename to boards/lairdconnect/bt610/bt610.yaml diff --git a/boards/arm/bt610/bt610_defconfig b/boards/lairdconnect/bt610/bt610_defconfig similarity index 82% rename from boards/arm/bt610/bt610_defconfig rename to boards/lairdconnect/bt610/bt610_defconfig index 531ba015b1e..3bff5fbaeb5 100644 --- a/boards/arm/bt610/bt610_defconfig +++ b/boards/lairdconnect/bt610/bt610_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_BT610=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bt610/doc/bt610.rst b/boards/lairdconnect/bt610/doc/bt610.rst similarity index 99% rename from boards/arm/bt610/doc/bt610.rst rename to boards/lairdconnect/bt610/doc/bt610.rst index 2fe7d7ad931..25798b12810 100644 --- a/boards/arm/bt610/doc/bt610.rst +++ b/boards/lairdconnect/bt610/doc/bt610.rst @@ -598,7 +598,7 @@ on the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button, LED and sensor device definitions can be found in -:zephyr_file:`boards/arm/bt610/bt610.dts`. +:zephyr_file:`boards/laird_connect/bt610/bt610.dts`. References diff --git a/boards/arm/bt610/doc/img/bt610_back.jpg b/boards/lairdconnect/bt610/doc/img/bt610_back.jpg similarity index 100% rename from boards/arm/bt610/doc/img/bt610_back.jpg rename to boards/lairdconnect/bt610/doc/img/bt610_back.jpg diff --git a/boards/arm/bt610/doc/img/bt610_board.jpg b/boards/lairdconnect/bt610/doc/img/bt610_board.jpg similarity index 100% rename from boards/arm/bt610/doc/img/bt610_board.jpg rename to boards/lairdconnect/bt610/doc/img/bt610_board.jpg diff --git a/boards/arm/bt610/doc/img/bt610_front.jpg b/boards/lairdconnect/bt610/doc/img/bt610_front.jpg similarity index 100% rename from boards/arm/bt610/doc/img/bt610_front.jpg rename to boards/lairdconnect/bt610/doc/img/bt610_front.jpg diff --git a/boards/arm/nrf21540dk_nrf52840/pre_dt_board.cmake b/boards/lairdconnect/bt610/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf21540dk_nrf52840/pre_dt_board.cmake rename to boards/lairdconnect/bt610/pre_dt_board.cmake diff --git a/boards/lairdconnect/index.rst b/boards/lairdconnect/index.rst new file mode 100644 index 00000000000..5c3a6d6621a --- /dev/null +++ b/boards/lairdconnect/index.rst @@ -0,0 +1,10 @@ +.. _boards-lairdconnect: + +Laird Connectivity +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/mg100/Kconfig b/boards/lairdconnect/mg100/Kconfig similarity index 100% rename from boards/arm/mg100/Kconfig rename to boards/lairdconnect/mg100/Kconfig diff --git a/boards/lairdconnect/mg100/Kconfig.defconfig b/boards/lairdconnect/mg100/Kconfig.defconfig new file mode 100644 index 00000000000..7c08d74f8c5 --- /dev/null +++ b/boards/lairdconnect/mg100/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2022 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MG100 + +config MODEM + default NETWORKING + +config MODEM_HL7800 + default NETWORKING + +config NORDIC_QSPI_NOR + default BOOTLOADER_MCUBOOT + +config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 if NORDIC_QSPI_NOR + +config REGULATOR + default DISK_DRIVER_SDMMC + +config BT_CTLR + default BT + +endif # BOARD_MG100 diff --git a/boards/lairdconnect/mg100/Kconfig.mg100 b/boards/lairdconnect/mg100/Kconfig.mg100 new file mode 100644 index 00000000000..9129b132911 --- /dev/null +++ b/boards/lairdconnect/mg100/Kconfig.mg100 @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MG100 + bool + default y + select SOC_NRF52840_QIAA diff --git a/boards/arm/mg100/board.cmake b/boards/lairdconnect/mg100/board.cmake similarity index 100% rename from boards/arm/mg100/board.cmake rename to boards/lairdconnect/mg100/board.cmake diff --git a/boards/lairdconnect/mg100/board.yml b/boards/lairdconnect/mg100/board.yml new file mode 100644 index 00000000000..25a3ace314f --- /dev/null +++ b/boards/lairdconnect/mg100/board.yml @@ -0,0 +1,5 @@ +board: + name: mg100 + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/mg100/doc/img/mg100.jpg b/boards/lairdconnect/mg100/doc/img/mg100.jpg similarity index 100% rename from boards/arm/mg100/doc/img/mg100.jpg rename to boards/lairdconnect/mg100/doc/img/mg100.jpg diff --git a/boards/lairdconnect/mg100/doc/index.rst b/boards/lairdconnect/mg100/doc/index.rst new file mode 100644 index 00000000000..e89fb09cf0a --- /dev/null +++ b/boards/lairdconnect/mg100/doc/index.rst @@ -0,0 +1,249 @@ +.. _mg100: + +Laird Connectivity Sentrius™ MG100 Gateway +########################################## + +Overview +******** +The Sentrius™ MG100 Gateway offers a compact, out of box Bluetooth to low power cellular gateway +solution. + +Based on the Pinnacle 100 socket modem, the Sentrius™ MG100 gateway captures data from any +Bluetooth 5 modules or devices and sends it to the cloud via a global low power cellular +(LTE-M/NB-IoT) connection. The MG100 seamlessly incorporates a powerful Cortex M4F controller, +full Bluetooth 5 connectivity, and dual-mode LTE-M/NB-IoT capabilities. The MG100 has full regulatory +and network certifications and End Device carrier approvals. + +Develop your application directly on the integrated Cortex M4F microcontroller using Zephyr RTOS, +enabling your application development with a secure, open source RTOS with more than just kernel +services. Remotely debug your fleet of devices with the `Memfault Platform`_. Take advantage of the +Zephyr community and Laird Connectivity’s multi featured Out of Box (OOB) sample source code +covering all aspects of the product's capabilities and hardware interfaces. The MG100 also delivers +complete antenna flexibility with internal or external antenna options available, and the optional +battery backup provides uninterrupted reporting of remote Bluetooth sensor data. + +More information about the board can be found at the `MG100 website`_. + +The MG100 hardware provides support for the Nordic Semiconductor `nRF52840`_ ARM Cortex-M4F CPU, +`Sierra Wireless HL7800`_ +and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* :abbr:`LIS3DH (ST Micro 3-axis MEMS accelerometer)` +* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` +* :abbr:`SD Card` + +.. figure:: img/mg100.jpg + :align: center + :alt: MG100 + + MG100 (450-00054-K1) + +Hardware +******** + +Supported Features +================== + +The MG100 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| QSPI | on-chip | qspi/MX25R64(8MB) | ++-----------+------------+----------------------+ +| LIS3DH | I2C(M) | sensor/lis3dh | ++-----------+------------+----------------------+ +| HL7800 | UART | HL7800 modem driver | ++-----------+------------+----------------------+ +| SDMMC | SPI(M) | SD Card via SPI | ++-----------+------------+----------------------+ + +See `MG100 website`_ for a complete list +of MG100 hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P1.7 +* LED2 (blue) = P1.6 +* LED3 (green) = P1.5 + +Push buttons +------------ + +* BUTTON1 = P0.3 + +External flash memory +--------------------- + +A 64Mbit external flash memory part is available for storage of application +images and data. Refer to the `Macronix MX25R6435F datasheet`_ for further +details. + +The flash memory is connected to the on-board QSPI device controller. + +* MX25R64 = QSPI + +SCK = P0.19 +IO0 = P0.20 +IO1 = P0.21 +IO2 = P0.22 +IO3 = P0.23 +CSN = P0.17 + +LIS3DH Motion Sensor +-------------------- + +Motion sensor to detect if the gateway moves. + +IRQ IO = P0.28 +I2C SDA = P0.26 +I2C SCL = P0.27 + +SD Card +------- + +SD card used to store large amounts of data. + +SPI CS = P0.29 +SPI SCK = P1.09 +SPI MOSI = P0.11 +SPI MISO = P0.12 + +Programming and Debugging +************************* + +Applications for the ``mg100`` board configuration can be +built and flashed in the usual way. (see :ref:`build_an_application` +and :ref:`application_run` for more details) + +The `Laird Connectivity USB-SWD Programming Kit`_ contains all the necessary +hardware to enable programming and debugging an MG100. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. note:: On the MG100, + the USB connector should be used to access the UART console. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board MG100 +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mg100 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +Software +******** + +MG100 Out-of-Box Demo Software +============================== +The MG100 ships with an out of the box software demo. +Check out the `BLE Gateway OOB Demo`_ source code and documentation. + +Testing Bluetooth on the MG100 +============================== +Many of the Bluetooth examples will work on the MG100. +Try them out: + +* :ref:`ble_peripheral` +* :ref:`bluetooth-eddystone-sample` +* :ref:`bluetooth-ibeacon-sample` + +Testing the LEDs and buttons in the MG100 +==================================================== + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/laird_connect/mg100/mg100.dts`. + +References +********** + +.. target-notes:: + +.. _MG100 website: https://www.lairdconnect.com/iot-devices/iot-gateways/sentrius-mg100-gateway-lte-mnb-iot-and-bluetooth-5 +.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf +.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _BLE Gateway OOB Demo: https://github.com/LairdCP/Pinnacle-100-Firmware-Manifest +.. _Macronix MX25R6435F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7913/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.5.pdf +.. _Laird Connectivity USB-SWD Programming Kit: https://www.lairdconnect.com/wireless-modules/programming-kits/usb-swd-programming-kit +.. _Memfault Platform: https://docs.memfault.com/docs/mcu/pinnacle-100-guide +.. _nRF52840: https://www.nordicsemi.com/products/nrf52840 diff --git a/boards/arm/mg100/mg100-pinctrl.dtsi b/boards/lairdconnect/mg100/mg100-pinctrl.dtsi similarity index 100% rename from boards/arm/mg100/mg100-pinctrl.dtsi rename to boards/lairdconnect/mg100/mg100-pinctrl.dtsi diff --git a/boards/arm/mg100/mg100.dts b/boards/lairdconnect/mg100/mg100.dts similarity index 100% rename from boards/arm/mg100/mg100.dts rename to boards/lairdconnect/mg100/mg100.dts diff --git a/boards/arm/mg100/mg100.yaml b/boards/lairdconnect/mg100/mg100.yaml similarity index 100% rename from boards/arm/mg100/mg100.yaml rename to boards/lairdconnect/mg100/mg100.yaml diff --git a/boards/arm/mg100/mg100_defconfig b/boards/lairdconnect/mg100/mg100_defconfig similarity index 81% rename from boards/arm/mg100/mg100_defconfig rename to boards/lairdconnect/mg100/mg100_defconfig index e2af3973938..f40691b7952 100644 --- a/boards/arm/mg100/mg100_defconfig +++ b/boards/lairdconnect/mg100/mg100_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2022 Laird Connectivity # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_MG100=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52832_mdk/pre_dt_board.cmake b/boards/lairdconnect/mg100/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52832_mdk/pre_dt_board.cmake rename to boards/lairdconnect/mg100/pre_dt_board.cmake diff --git a/boards/arm/pinnacle_100_dvk/Kconfig b/boards/lairdconnect/pinnacle_100_dvk/Kconfig similarity index 100% rename from boards/arm/pinnacle_100_dvk/Kconfig rename to boards/lairdconnect/pinnacle_100_dvk/Kconfig diff --git a/boards/lairdconnect/pinnacle_100_dvk/Kconfig.defconfig b/boards/lairdconnect/pinnacle_100_dvk/Kconfig.defconfig new file mode 100644 index 00000000000..181dc76a04e --- /dev/null +++ b/boards/lairdconnect/pinnacle_100_dvk/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Pinnacle(TM) 100 DVK board configuration + +# Copyright (c) 2019 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PINNACLE_100_DVK + +config MODEM + default NETWORKING + +config MODEM_HL7800 + default NETWORKING + +config NORDIC_QSPI_NOR + default BOOTLOADER_MCUBOOT + +config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 if NORDIC_QSPI_NOR + +config BT_CTLR + default BT + +endif # BOARD_PINNACLE_100_DVK diff --git a/boards/lairdconnect/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk b/boards/lairdconnect/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk new file mode 100644 index 00000000000..fa018b9ab03 --- /dev/null +++ b/boards/lairdconnect/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk @@ -0,0 +1,9 @@ +# Pinnacle(TM) 100 DVK board configuration +# +# Copyright (c) 2020 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PINNACLE_100_DVK + bool + default y + select SOC_NRF52840_QIAA diff --git a/boards/arm/pinnacle_100_dvk/board.cmake b/boards/lairdconnect/pinnacle_100_dvk/board.cmake similarity index 100% rename from boards/arm/pinnacle_100_dvk/board.cmake rename to boards/lairdconnect/pinnacle_100_dvk/board.cmake diff --git a/boards/lairdconnect/pinnacle_100_dvk/board.yml b/boards/lairdconnect/pinnacle_100_dvk/board.yml new file mode 100644 index 00000000000..1741e687ace --- /dev/null +++ b/boards/lairdconnect/pinnacle_100_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: pinnacle_100_dvk + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg b/boards/lairdconnect/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg similarity index 100% rename from boards/arm/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg rename to boards/lairdconnect/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg diff --git a/boards/lairdconnect/pinnacle_100_dvk/doc/index.rst b/boards/lairdconnect/pinnacle_100_dvk/doc/index.rst new file mode 100644 index 00000000000..483fff9dd8e --- /dev/null +++ b/boards/lairdconnect/pinnacle_100_dvk/doc/index.rst @@ -0,0 +1,220 @@ +.. _pinnacle_100_dvk: + +Laird Connectivity Pinnacle 100 DVK +################################### + +Overview +******** +The Pinnacle™ 100 cellular modem seamlessly incorporates a powerful Cortex M4F +controller, full Bluetooth 5 and LTE-M/NB-IoT capabilities – all with full +regulatory certifications and LTE carrier approvals. The Pinnacle 100 also +delivers complete antenna flexibility, with pre-integrated internal or external +antenna options such as the Revie Flex family of LTE and NB-IoT +internal antennas. + +Develop your application directly on the M4F controller using Zephyr RTOS to +cut BOM costs and power consumption. Take advantage of the Zephyr community, +Laird Connectivity’s sample code (cellular, Bluetooth) and hardware interfaces, +or use our hosted mode AT commands set firmware. + +Extremely power conscious, the Pinnacle 100 is ideal for battery-powered +devices operating at the edge of your IoT networks, seamlessly bridging the +cellular WAN to BLE. It’s never been easier to bridge wireless +Bluetooth 5 sensor data to cloud services like AWS IoT over a +low-power LTE connection. + +More information about the board can be found at the `Pinnacle 100 website`_. + +The Pinnacle 100 Development Kit (453-00010-K1 or 453-00011-K1) hardware +provides support for the +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU, `Sierra Wireless HL7800`_ (Altair ALT1250) +and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* :abbr:`BME680 (Bosch Sensortec BME680 environmental sensor)` +* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` + +.. figure:: img/pinnacle_100_dvk.jpg + :align: center + :alt: Pinnacle 100 DVK + + Pinnacle 100 DVK (453-00010-K1) + +Hardware +******** + +Supported Features +================== + +The Pinnacle 100 development board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| QSPI | on-chip | qspi/MX25R64(8MB) | ++-----------+------------+----------------------+ +| BME680 | I2C(M) | sensor/bme680 | ++-----------+------------+----------------------+ +| HL7800 | UART | HL7800 modem driver | ++-----------+------------+----------------------+ + +See `Pinnacle 100 website`_ for a complete list +of Pinnacle 100 Development Kit hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (blue) = P1.4 +* LED2 (green) = P1.5 +* LED3 (red) = P1.6 +* LED4 (green) = P1.7 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.31 +* BUTTON2 = SW2 = P0.3 +* BUTTON3 = SW3 = P0.4 +* BUTTON4 = SW4 = P0.2 +* NRF RESET = SW5 = reset + +Programming and Debugging +************************* + +Applications for the ``pinnacle_100_dvk`` board configuration can be +built and flashed in the usual way. (see :ref:`build_an_application` +and :ref:`application_run` for more details) + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. note:: On the Pinnacle 100 development board, + the FTDI USB should be used to access the UART console. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board Pinnacle 100 DVK +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: pinnacle_100_dvk + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +Software +******** + +Pinnacle 100 Out-of-Box Demo Software +===================================== +The Pinnacle 100 development kit ships with an out of the box software demo. +Check out the `Pinnacle 100 OOB Demo`_ source code and documentation. + +Sample Applications +=================== +`Pinnacle 100 Sample Applications`_ are available. + +Testing Bluetooth on the Pinnacle 100 DVK +========================================= +Many of the Bluetooth examples will work on the Pinnacle 100 DVK. +Try them out: + +* :ref:`ble_peripheral` +* :ref:`bluetooth-eddystone-sample` +* :ref:`bluetooth-ibeacon-sample` + +Testing the LEDs and buttons in the Pinnacle 100 DVK +==================================================== + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/laird_connect/pinnacle_100_dvk/pinnacle_100_dvk.dts`. + +References +********** + +.. target-notes:: + +.. _Pinnacle 100 website: https://www.lairdconnect.com/wireless-modules/cellular-solutions/pinnacle-100-cellular-modem +.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf +.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _Pinnacle 100 OOB Demo: https://github.com/LairdCP/Pinnacle_100_oob_demo +.. _Pinnacle 100 Sample Applications: https://github.com/LairdCP/Pinnacle_100_Sample_Applications diff --git a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi similarity index 100% rename from boards/arm/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi rename to boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi diff --git a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.dts b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts similarity index 100% rename from boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.dts rename to boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts diff --git a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.yaml b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.yaml similarity index 100% rename from boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.yaml rename to boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.yaml diff --git a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk_defconfig similarity index 81% rename from boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig rename to boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk_defconfig index 0e6c950ae36..06f53140c43 100644 --- a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig +++ b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk_defconfig @@ -2,10 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PINNACLE_100_DVK=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52833dk_nrf52820/pre_dt_board.cmake b/boards/lairdconnect/pinnacle_100_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52833dk_nrf52820/pre_dt_board.cmake rename to boards/lairdconnect/pinnacle_100_dvk/pre_dt_board.cmake diff --git a/boards/lairdconnect/rm1xx_dvk/Kconfig.defconfig b/boards/lairdconnect/rm1xx_dvk/Kconfig.defconfig new file mode 100644 index 00000000000..01cbc05ee78 --- /dev/null +++ b/boards/lairdconnect/rm1xx_dvk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# rm1xx_dvk board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RM1XX_DVK + +config BT_CTLR + default BT + +endif # BOARD_RM1XX_DVK diff --git a/boards/lairdconnect/rm1xx_dvk/Kconfig.rm1xx_dvk b/boards/lairdconnect/rm1xx_dvk/Kconfig.rm1xx_dvk new file mode 100644 index 00000000000..ead49ede862 --- /dev/null +++ b/boards/lairdconnect/rm1xx_dvk/Kconfig.rm1xx_dvk @@ -0,0 +1,7 @@ +# rm1xx_dvk board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RM1XX_DVK + select SOC_NRF51822_QFAC diff --git a/boards/arm/rm1xx_dvk/board.cmake b/boards/lairdconnect/rm1xx_dvk/board.cmake similarity index 100% rename from boards/arm/rm1xx_dvk/board.cmake rename to boards/lairdconnect/rm1xx_dvk/board.cmake diff --git a/boards/lairdconnect/rm1xx_dvk/board.yml b/boards/lairdconnect/rm1xx_dvk/board.yml new file mode 100644 index 00000000000..1e7ddd8f806 --- /dev/null +++ b/boards/lairdconnect/rm1xx_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: rm1xx_dvk + vendor: lairdconnect + socs: + - name: nrf51822 diff --git a/boards/arm/rm1xx_dvk/doc/img/RM186-DVK.jpg b/boards/lairdconnect/rm1xx_dvk/doc/img/RM186-DVK.jpg similarity index 100% rename from boards/arm/rm1xx_dvk/doc/img/RM186-DVK.jpg rename to boards/lairdconnect/rm1xx_dvk/doc/img/RM186-DVK.jpg diff --git a/boards/arm/rm1xx_dvk/doc/img/RM186-SM.jpg b/boards/lairdconnect/rm1xx_dvk/doc/img/RM186-SM.jpg similarity index 100% rename from boards/arm/rm1xx_dvk/doc/img/RM186-SM.jpg rename to boards/lairdconnect/rm1xx_dvk/doc/img/RM186-SM.jpg diff --git a/boards/arm/rm1xx_dvk/doc/index.rst b/boards/lairdconnect/rm1xx_dvk/doc/index.rst similarity index 100% rename from boards/arm/rm1xx_dvk/doc/index.rst rename to boards/lairdconnect/rm1xx_dvk/doc/index.rst diff --git a/boards/arm/bbc_microbit/pre_dt_board.cmake b/boards/lairdconnect/rm1xx_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/bbc_microbit/pre_dt_board.cmake rename to boards/lairdconnect/rm1xx_dvk/pre_dt_board.cmake diff --git a/boards/arm/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi b/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi similarity index 100% rename from boards/arm/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi rename to boards/lairdconnect/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi diff --git a/boards/arm/rm1xx_dvk/rm1xx_dvk.dts b/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.dts similarity index 100% rename from boards/arm/rm1xx_dvk/rm1xx_dvk.dts rename to boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.dts diff --git a/boards/arm/rm1xx_dvk/rm1xx_dvk.yaml b/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.yaml similarity index 100% rename from boards/arm/rm1xx_dvk/rm1xx_dvk.yaml rename to boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.yaml diff --git a/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk_defconfig b/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk_defconfig new file mode 100644 index 00000000000..46dc69d74cd --- /dev/null +++ b/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_PINCTRL=y diff --git a/boards/lowrisc/index.rst b/boards/lowrisc/index.rst new file mode 100644 index 00000000000..cc96e30f501 --- /dev/null +++ b/boards/lowrisc/index.rst @@ -0,0 +1,10 @@ +.. _boards-lowrisc: + +lowRISC +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/lowrisc/opentitan_earlgrey/Kconfig.opentitan_earlgrey b/boards/lowrisc/opentitan_earlgrey/Kconfig.opentitan_earlgrey new file mode 100644 index 00000000000..b7ba3bd9f71 --- /dev/null +++ b/boards/lowrisc/opentitan_earlgrey/Kconfig.opentitan_earlgrey @@ -0,0 +1,5 @@ +# Copyright (c) 2023 by Rivos Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OPENTITAN_EARLGREY + select SOC_OPENTITAN diff --git a/boards/lowrisc/opentitan_earlgrey/board.yml b/boards/lowrisc/opentitan_earlgrey/board.yml new file mode 100644 index 00000000000..d7e8a24879c --- /dev/null +++ b/boards/lowrisc/opentitan_earlgrey/board.yml @@ -0,0 +1,5 @@ +board: + name: opentitan_earlgrey + vendor: lowrisc + socs: + - name: opentitan diff --git a/boards/riscv/opentitan_earlgrey/doc/index.rst b/boards/lowrisc/opentitan_earlgrey/doc/index.rst similarity index 100% rename from boards/riscv/opentitan_earlgrey/doc/index.rst rename to boards/lowrisc/opentitan_earlgrey/doc/index.rst diff --git a/boards/riscv/opentitan_earlgrey/opentitan_earlgrey.dts b/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey.dts similarity index 100% rename from boards/riscv/opentitan_earlgrey/opentitan_earlgrey.dts rename to boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey.dts diff --git a/boards/riscv/opentitan_earlgrey/opentitan_earlgrey.yaml b/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey.yaml similarity index 100% rename from boards/riscv/opentitan_earlgrey/opentitan_earlgrey.yaml rename to boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey.yaml diff --git a/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey_defconfig b/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey_defconfig new file mode 100644 index 00000000000..f9c0c4a356a --- /dev/null +++ b/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023 by Rivos Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_BUILD_OUTPUT_BIN=n diff --git a/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig b/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig new file mode 100644 index 00000000000..054ac256729 --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig @@ -0,0 +1,15 @@ +# ESP32C3 core board configuration + +# Copyright (c) 2023 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice diff --git a/boards/luatos/esp32c3_luatos_core/Kconfig.esp32c3_luatos_core b/boards/luatos/esp32c3_luatos_core/Kconfig.esp32c3_luatos_core new file mode 100644 index 00000000000..e7eb73ed384 --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/Kconfig.esp32c3_luatos_core @@ -0,0 +1,5 @@ +# Copyright (c) 2023 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32C3_LUATOS_CORE + select SOC_ESP32C3_MINI_N4 diff --git a/boards/xtensa/esp32s3_luatos_core/Kconfig.sysbuild b/boards/luatos/esp32c3_luatos_core/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/Kconfig.sysbuild rename to boards/luatos/esp32c3_luatos_core/Kconfig.sysbuild diff --git a/boards/riscv/esp32c3_luatos_core/board.cmake b/boards/luatos/esp32c3_luatos_core/board.cmake similarity index 100% rename from boards/riscv/esp32c3_luatos_core/board.cmake rename to boards/luatos/esp32c3_luatos_core/board.cmake diff --git a/boards/luatos/esp32c3_luatos_core/board.yml b/boards/luatos/esp32c3_luatos_core/board.yml new file mode 100644 index 00000000000..e1a5ed42046 --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/board.yml @@ -0,0 +1,7 @@ +board: + name: esp32c3_luatos_core + vendor: luatos + socs: + - name: esp32c3 + variants: + - name: usb diff --git a/boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core.jpg b/boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core.jpg similarity index 100% rename from boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core.jpg rename to boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core.jpg diff --git a/boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_pinfunc.jpg b/boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_pinfunc.jpg similarity index 100% rename from boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_pinfunc.jpg rename to boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_pinfunc.jpg diff --git a/boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_usb.jpg b/boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_usb.jpg similarity index 100% rename from boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_usb.jpg rename to boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_usb.jpg diff --git a/boards/luatos/esp32c3_luatos_core/doc/index.rst b/boards/luatos/esp32c3_luatos_core/doc/index.rst new file mode 100644 index 00000000000..beaf0d1e85b --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/doc/index.rst @@ -0,0 +1,259 @@ +.. _esp32c3_luatos_core: + +ESP32C3_LUATOS_CORE +################### + +Overview +******** + +ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, +based on the open-source RISC-V architecture. It strikes the right balance of power, +I/O capabilities and security, thus offering the optimal cost-effective +solution for connected devices. +The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy, +but it also facilitates a variety of use-cases based on dual connectivity. [1]_ + +The features include the following: + +- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz +- 400 KB of internal RAM +- 802.11b/g/n/e/i +- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh +- Various peripherals: + + - 12-bit ADC with up to 6 channels + - TWAI compatible with CAN bus 2.0 + - Temperature sensor + - 3x SPI + - 1x I2S + - 1x I2C + - 2x UART + - LED PWM with up to 6 channels + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) + +There are two version hardware of this board. The difference between them is the ch343 chip. + +1. USB-C connect to UART over CH343 chip(esp32c3_luatos_core) + +.. image:: img/esp32c3_luatos_core.jpg + :align: center + :alt: esp32c3_luatos_core + +2. USB-C connect to esp32 chip directly(esp32c3_luatos_core/esp32c3/usb) + +.. image:: img/esp32c3_luatos_core_usb.jpg + :align: center + :alt: esp32c3_luatos_core/esp32c3/usb + +Supported Features +================== + +Current Zephyr's ESP32C3_LUATOS_CORE board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +.. image:: img/esp32c3_luatos_core_pinfunc.jpg + :align: center + :alt: esp32c3_luatos_core_pinfunc + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32c3_luatos_core + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_luatos_core + :goals: build + +The usual ``flash`` target will work with the ``esp32c3_luatos_core`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_luatos_core + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32c3_luatos_core + +Debugging +********* + +As with much custom hardware, the ESP32-C3 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_luatos_core + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_luatos_core + :goals: debug + +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases + +References +********** + +.. [1] https://www.espressif.com/en/products/socs/esp32-c3 +.. _ESP32C3 Core Website: https://wiki.luatos.com/chips/esp32c3/board.html +.. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _ESP32C3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core-pinctrl.dtsi b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core-pinctrl.dtsi similarity index 100% rename from boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core-pinctrl.dtsi rename to boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core-pinctrl.dtsi diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.dts b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dts similarity index 100% rename from boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.dts rename to boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dts diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.dtsi b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi similarity index 98% rename from boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.dtsi rename to boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi index 2a1a74996c5..2972e4725f1 100644 --- a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.dtsi +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi @@ -9,7 +9,7 @@ #include / { - model = "esp32c3_luatos_core"; + model = "ESP32C3 Luatos Core"; compatible = "espressif,esp32c3"; aliases { diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.yaml b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.yaml similarity index 80% rename from boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.yaml rename to boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.yaml index 21f96ad6c9e..5baefb918a2 100644 --- a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.yaml +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.yaml @@ -1,4 +1,4 @@ -identifier: esp32c3_luatos_core +identifier: esp32c3_luatos_core/esp32c3 name: ESP32C3 LuatOS Core type: mcu arch: riscv @@ -19,4 +19,4 @@ testing: ignore_tags: - net - bluetooth -vendor: espressif +vendor: luatos diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig new file mode 100644 index 00000000000..ef633ce56a1 --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb.dts b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.dts similarity index 100% rename from boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb.dts rename to boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.dts diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml new file mode 100644 index 00000000000..7910c6ac8ee --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml @@ -0,0 +1,22 @@ +identifier: esp32c3_luatos_core/esp32c3/usb +name: ESP32C3 LuatOS Core USB +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - adc + - gpio + - i2c + - watchdog + - uart + - dma + - pwm + - spi + - counter + - entropy +testing: + ignore_tags: + - net + - bluetooth +vendor: luatos diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig new file mode 100644 index 00000000000..ef633ce56a1 --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/riscv/esp32c3_luatos_core/support/openocd.cfg b/boards/luatos/esp32c3_luatos_core/support/openocd.cfg similarity index 100% rename from boards/riscv/esp32c3_luatos_core/support/openocd.cfg rename to boards/luatos/esp32c3_luatos_core/support/openocd.cfg diff --git a/boards/luatos/esp32s3_luatos_core/Kconfig b/boards/luatos/esp32s3_luatos_core/Kconfig new file mode 100644 index 00000000000..96c55ea054d --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_LUATOS_CORE + select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB + select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB diff --git a/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig b/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig new file mode 100644 index 00000000000..093805f235b --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig @@ -0,0 +1,26 @@ +# ESP32S3 Core board configuration + +# Copyright (c) 2023 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB + +if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB diff --git a/boards/luatos/esp32s3_luatos_core/Kconfig.esp32s3_luatos_core b/boards/luatos/esp32s3_luatos_core/Kconfig.esp32s3_luatos_core new file mode 100644 index 00000000000..98ca53fefca --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/Kconfig.esp32s3_luatos_core @@ -0,0 +1,5 @@ +# Copyright (c) 2023 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_LUATOS_CORE + select SOC_ESP32S3_MINI_N8 diff --git a/boards/xtensa/esp_wrover_kit/Kconfig.sysbuild b/boards/luatos/esp32s3_luatos_core/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp_wrover_kit/Kconfig.sysbuild rename to boards/luatos/esp32s3_luatos_core/Kconfig.sysbuild diff --git a/boards/xtensa/esp32s2_saola/board.cmake b/boards/luatos/esp32s3_luatos_core/board.cmake similarity index 100% rename from boards/xtensa/esp32s2_saola/board.cmake rename to boards/luatos/esp32s3_luatos_core/board.cmake diff --git a/boards/luatos/esp32s3_luatos_core/board.yml b/boards/luatos/esp32s3_luatos_core/board.yml new file mode 100644 index 00000000000..cd29886c969 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/board.yml @@ -0,0 +1,10 @@ +board: + name: esp32s3_luatos_core + vendor: luatos + socs: + - name: esp32s3 + variants: + - name: usb + cpucluster: procpu + - name: usb + cpucluster: appcpu diff --git a/boards/xtensa/esp32s3_luatos_core/doc/img/esp32s3_luatos_core.jpg b/boards/luatos/esp32s3_luatos_core/doc/img/esp32s3_luatos_core.jpg similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/doc/img/esp32s3_luatos_core.jpg rename to boards/luatos/esp32s3_luatos_core/doc/img/esp32s3_luatos_core.jpg diff --git a/boards/xtensa/esp32s3_luatos_core/doc/img/esp32s3_luatos_core_pinout.jpg b/boards/luatos/esp32s3_luatos_core/doc/img/esp32s3_luatos_core_pinout.jpg similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/doc/img/esp32s3_luatos_core_pinout.jpg rename to boards/luatos/esp32s3_luatos_core/doc/img/esp32s3_luatos_core_pinout.jpg diff --git a/boards/luatos/esp32s3_luatos_core/doc/index.rst b/boards/luatos/esp32s3_luatos_core/doc/index.rst new file mode 100644 index 00000000000..4921e11e915 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/doc/index.rst @@ -0,0 +1,292 @@ +.. _esp32s3_luatos_core: + +ESP32S3-Luatos-Core +################### + +Overview +******** + +The ESP32S3-LUATOS-CORE development board is a compact board based on Espressif ESP32-S3. +The board comes equipped with a 2.4GHz antenna and supports both Wi-Fi and Bluetooth functionalities. +For more information, check `ESP32S3-LUATOS-CORE`_ (chinese) + +.. image:: img/esp32s3_luatos_core.jpg + :align: center + :alt: esp32s3_luatos_core + +Hardware +******** + +ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi +and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor +(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, +RF module, and numerous peripherals. + +ESP32S3-LUATOS-CORE includes the following features: + +- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz +- Additional vector instructions support for AI acceleration +- 512KB of SRAM +- 384KB of ROM +- 8MB of PSRAM +- 16MB of FLASH +- Wi-Fi 802.11b/g/n +- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate + +Digital interfaces: + +- 4x SPI +- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411 +- 1x DVP 8-bit ~16-bit camera interface +- 3x UART +- 2x I2C +- 2x I2S +- 1x RMT (TX/RX) +- 1x pulse counter +- LED PWM controller, up to 8 channels +- 1x USB Port with USB switcher, supporting following modes: + - 1x full-speed USB OTG or 1x USB Serial/JTAG controller + - USB to serial chip CH343 +- 2x MCPWM +- 1x SDIO host controller with 2 slots +- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels +- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) +- 2x Blue LED + +Analog interfaces: + +- 2x 12-bit SAR ADCs, up to 20 channels + +Timers: + +- 4x 54-bit general-purpose timers +- 1x 52-bit system timer +- 3x watchdog timers + +Low Power: + +- Power Management Unit with five power modes +- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM + +Security: + +- Secure boot +- Flash encryption +- 4-Kbit OTP, up to 1792 bits for users +- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) + +For more information, check the datasheet at `ESP32-S3 Datasheet`_. + +.. image:: img/esp32s3_luatos_core_pinout.jpg + :align: center + :alt: esp32s3_luatos_core_pinout + +Supported Features +================== + +Current Zephyr's ESP32S3-LUATOS-Core board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32s3_luatos_core + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_luatos_core/esp32s3/procpu + :goals: build + +If CH343 chip is disabled, You need use the following command to build: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_luatos_core_usb/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32s3_luatos_core`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_luatos_core/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s3_luatos_core + +Debugging +********* + +ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32-S3`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_luatos_core/esp32s3/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_luatos_core/esp32s3/procpu + :goals: debug + +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`ESP32S3-LUATOS-CORE`: https://wiki.luatos.com/chips/esp32s3/board.html + +References +********** + +.. _ESP32S3-LUATOS-CORE User Guide: https://wiki.luatos.com/chips/esp32s3/board.html +.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf +.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core-pinctrl.dtsi b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core-pinctrl.dtsi rename to boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core-pinctrl.dtsi diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.dtsi b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.dtsi rename to boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.dts new file mode 100644 index 00000000000..e33c7f43401 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "ESP32S3 Luatos Core APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.yaml b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.yaml new file mode 100644 index 00000000000..05aac04c00f --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32s3_luatos_core/esp32s3/appcpu +name: ESP32-S3 LuatOS Core +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: luatos diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.dts new file mode 100644 index 00000000000..7a251b40e04 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "ESP32S3 Luatos Core USB APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.yaml b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.yaml new file mode 100644 index 00000000000..cb2ac02717b --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.yaml @@ -0,0 +1,27 @@ +identifier: esp32s3_luatos_core/esp32s3/appcpu/usb +name: ESP32-S3 LuatOS Core USB +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: luatos diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.dts new file mode 100644 index 00000000000..8c44d0cebd7 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023 YuLong Yao + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include "esp32s3_luatos_core.dtsi" + +/ { + model = "ESP32S3 Luatos Core PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + led0 = &led0; + led1 = &led1; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + uart-0 = &uart0; + sw0 = &button0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.yaml b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.yaml new file mode 100644 index 00000000000..2a1bb02cc2f --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.yaml @@ -0,0 +1,22 @@ +identifier: esp32s3_luatos_core/esp32s3/procpu +name: ESP32-S3 LuatOS Core +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma +testing: + ignore_tags: + - net + - bluetooth +vendor: luatos diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_defconfig new file mode 100644 index 00000000000..d789bab1824 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.dts new file mode 100644 index 00000000000..0a707724f9f --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.dts @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2023 YuLong Yao + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include "esp32s3_luatos_core.dtsi" + +/ { + model = "ESP32S3 Luatos Core USB PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + led0 = &led0; + led1 = &led1; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + uart-0 = &usb_serial; + sw0 = &button0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "disabled"; +}; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.yaml b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.yaml new file mode 100644 index 00000000000..f1cd4d19d5a --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.yaml @@ -0,0 +1,22 @@ +identifier: esp32s3_luatos_core/esp32s3/procpu/usb +name: ESP32-S3 LuatOS Core USB +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma +testing: + ignore_tags: + - net + - bluetooth +vendor: luatos diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb_defconfig new file mode 100644 index 00000000000..d789bab1824 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/support/openocd.cfg b/boards/luatos/esp32s3_luatos_core/support/openocd.cfg similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/support/openocd.cfg rename to boards/luatos/esp32s3_luatos_core/support/openocd.cfg diff --git a/boards/luatos/index.rst b/boards/luatos/index.rst new file mode 100644 index 00000000000..3a9934889e4 --- /dev/null +++ b/boards/luatos/index.rst @@ -0,0 +1,10 @@ +.. _boards-luatos: + +Luatos +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/m5stack/index.rst b/boards/m5stack/index.rst new file mode 100644 index 00000000000..e4d1a57d992 --- /dev/null +++ b/boards/m5stack/index.rst @@ -0,0 +1,10 @@ +.. _boards-m5stack: + +M5Stack +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/m5stack/m5stack_atoms3/Kconfig b/boards/m5stack/m5stack_atoms3/Kconfig new file mode 100644 index 00000000000..651e5528b94 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_ATOMS3 + select SOC_ESP32S3_PROCPU if BOARD_M5STACK_ATOMS3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_M5STACK_ATOMS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3/Kconfig.defconfig b/boards/m5stack/m5stack_atoms3/Kconfig.defconfig new file mode 100644 index 00000000000..c0dadaceeb4 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/Kconfig.defconfig @@ -0,0 +1,28 @@ +# M5Stack AtomS3 board configuration +# Copyright (c) 2023 Benjamin Cabé +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_ATOMS3_ESP32S3_PROCPU + +config LV_COLOR_16_SWAP + default y if LVGL + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_M5STACK_ATOMS3_ESP32S3_PROCPU + +if BOARD_M5STACK_ATOMS3_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_M5STACK_ATOMS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3/Kconfig.m5stack_atoms3 b/boards/m5stack/m5stack_atoms3/Kconfig.m5stack_atoms3 new file mode 100644 index 00000000000..e858deba10d --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/Kconfig.m5stack_atoms3 @@ -0,0 +1,7 @@ +# M5Stack AtomS3 board configuration + +# Copyright (c) 2023 Benjamin Cabé +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_ATOMS3 + select SOC_ESP32S3_FN8 diff --git a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.sysbuild b/boards/m5stack/m5stack_atoms3/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/heltec_wifi_lora32_v2/Kconfig.sysbuild rename to boards/m5stack/m5stack_atoms3/Kconfig.sysbuild diff --git a/boards/xtensa/esp32s3_devkitm/board.cmake b/boards/m5stack/m5stack_atoms3/board.cmake similarity index 100% rename from boards/xtensa/esp32s3_devkitm/board.cmake rename to boards/m5stack/m5stack_atoms3/board.cmake diff --git a/boards/m5stack/m5stack_atoms3/board.yml b/boards/m5stack/m5stack_atoms3/board.yml new file mode 100644 index 00000000000..4126aa17d2e --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/board.yml @@ -0,0 +1,5 @@ +board: + name: m5stack_atoms3 + vendor: m5stack + socs: + - name: esp32s3 diff --git a/boards/xtensa/m5stack_atoms3/doc/img/m5stack_atoms3.webp b/boards/m5stack/m5stack_atoms3/doc/img/m5stack_atoms3.webp similarity index 100% rename from boards/xtensa/m5stack_atoms3/doc/img/m5stack_atoms3.webp rename to boards/m5stack/m5stack_atoms3/doc/img/m5stack_atoms3.webp diff --git a/boards/m5stack/m5stack_atoms3/doc/index.rst b/boards/m5stack/m5stack_atoms3/doc/index.rst new file mode 100644 index 00000000000..c053f73c101 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/doc/index.rst @@ -0,0 +1,136 @@ +.. _m5stack_atoms3: + +M5Stack AtomS3 +############## + +Overview +******** + +M5Stack AtomS3 is an ESP32-based development board from M5Stack. + +It features the following integrated components: + +- ESP32-S3FN8 chip (240MHz dual core, Wi-Fi/BLE 5.0) +- 512KB of SRAM +- 384KB of ROM +- 8MB of Flash +- LCD IPS TFT 0.85", 128x128 px screen (ST7789 compatible) +- 6-axis IMU MPU6886 +- Infrared emitter + + +.. figure:: img/m5stack_atoms3.webp + :align: center + :alt: M5Stack AtomS3 + + M5Stack AtomS3 + + +Supported Features +================== + +The Zephyr m5stack_atoms3 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + + +Start Application Development +***************************** + +Before powering up your M5Stack AtomS3, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: shell + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_atoms3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``m5stack_atoms3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_atoms3/esp32s3/procpu + :goals: flash + +The baud rate of 921600bps is set by default. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stack_atoms3 + +Debugging +--------- + +M5Stack AtomS3 debugging is not supported due to pinout limitations. + +Related Documents +***************** + +- `M5Stack AtomS3 schematic `_ +- `ESP32S3 Datasheet `_ diff --git a/boards/xtensa/m5stack_atoms3/grove_connectors.dtsi b/boards/m5stack/m5stack_atoms3/grove_connectors.dtsi similarity index 100% rename from boards/xtensa/m5stack_atoms3/grove_connectors.dtsi rename to boards/m5stack/m5stack_atoms3/grove_connectors.dtsi diff --git a/boards/xtensa/m5stack_atoms3/m5stack_atoms3-pinctrl.dtsi b/boards/m5stack/m5stack_atoms3/m5stack_atoms3-pinctrl.dtsi similarity index 100% rename from boards/xtensa/m5stack_atoms3/m5stack_atoms3-pinctrl.dtsi rename to boards/m5stack/m5stack_atoms3/m5stack_atoms3-pinctrl.dtsi diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.dts new file mode 100644 index 00000000000..91bcff6c007 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "M5Stack AtomS3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.yaml b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.yaml new file mode 100644 index 00000000000..a8efc9aad00 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stack_atoms3/esp32s3/appcpu +name: M5Stack AtomS3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.dts new file mode 100644 index 00000000000..1b5a5da32da --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.dts @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2023 Benjamin Cabé + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stack_atoms3-pinctrl.dtsi" +#include "grove_connectors.dtsi" +#include + +/ { + model = "M5Stack AtomS3 PROCPU"; + compatible = "m5stack,atoms3"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,display = &st7789v; + }; + + aliases { + sw0 = &user_button_0; + watchdog0 = &wdt0; + accel0 = &mpu6886; + }; + + gpio_keys { + compatible = "gpio-keys"; + + /* This is the button that's underneath the LCD display */ + user_button_0: button_0 { + label = "User button 0"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; // G42 + zephyr,code = ; + }; + }; + + /* Regulators */ + lcd_backlight_en { + compatible = "regulator-fixed"; + regulator-name = "lcd_backlight_enable"; + enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + mpu6886: mpu6886@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + status = "okay"; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; + + st7789v: st7789v@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + spi-max-frequency = <27000000>; + cmd-data-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; /* G33 */ + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* G34 */ + + width = <128>; + height = <128>; + x-offset = <2>; + y-offset = <1>; + + vcom = <0x28>; + gctrl = <0x35>; + vrhs = <0x10>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x0c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 00]; + pwctrl1-param = [a4 a1]; + pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; + nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; + ram-param = [00 E0]; + rgb-param = [40 02 14]; + }; + +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.yaml b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.yaml new file mode 100644 index 00000000000..4be28b02f83 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.yaml @@ -0,0 +1,21 @@ +identifier: m5stack_atoms3/esp32s3/procpu +name: M5Stack AtomS3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - regulator + - uart + - pinmux + - nvs + - display +testing: + ignore_tags: + - net + - bluetooth +vendor: m5stack diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu_defconfig b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu_defconfig new file mode 100644 index 00000000000..88c69e52e8c --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_GPIO=y +CONFIG_REGULATOR=y # for LCD backlight + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/m5stack/m5stack_atoms3_lite/Kconfig b/boards/m5stack/m5stack_atoms3_lite/Kconfig new file mode 100644 index 00000000000..bcf86cfa018 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_ATOMS3_LITE + select SOC_ESP32S3_PROCPU if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig b/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig new file mode 100644 index 00000000000..8039b4762cd --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig @@ -0,0 +1,28 @@ +# M5Stack AtomS3 Lite board configuration +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +config KERNEL_MEM_POOL + default y + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_M5STACK_ATOMS3_LITE_ESP32S3_PROCPU + +if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_M5STACK_ATOMS3_LITE_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3_lite/Kconfig.m5stack_atoms3_lite b/boards/m5stack/m5stack_atoms3_lite/Kconfig.m5stack_atoms3_lite new file mode 100644 index 00000000000..0d21265e495 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/Kconfig.m5stack_atoms3_lite @@ -0,0 +1,6 @@ +# M5Stack AtomS3 Lite board configuration +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_ATOMS3_LITE + select SOC_ESP32S3_FN8 diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.sysbuild b/boards/m5stack/m5stack_atoms3_lite/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.sysbuild rename to boards/m5stack/m5stack_atoms3_lite/Kconfig.sysbuild diff --git a/boards/xtensa/esp32s3_luatos_core/board.cmake b/boards/m5stack/m5stack_atoms3_lite/board.cmake similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/board.cmake rename to boards/m5stack/m5stack_atoms3_lite/board.cmake diff --git a/boards/m5stack/m5stack_atoms3_lite/board.yml b/boards/m5stack/m5stack_atoms3_lite/board.yml new file mode 100644 index 00000000000..c9204d5159c --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/board.yml @@ -0,0 +1,5 @@ +board: + name: m5stack_atoms3_lite + vendor: m5stack + socs: + - name: esp32s3 diff --git a/boards/xtensa/m5stack_atoms3_lite/doc/img/m5stack_atoms3_lite.webp b/boards/m5stack/m5stack_atoms3_lite/doc/img/m5stack_atoms3_lite.webp similarity index 100% rename from boards/xtensa/m5stack_atoms3_lite/doc/img/m5stack_atoms3_lite.webp rename to boards/m5stack/m5stack_atoms3_lite/doc/img/m5stack_atoms3_lite.webp diff --git a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst new file mode 100644 index 00000000000..204d8e5bbec --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst @@ -0,0 +1,134 @@ +.. _m5stack_atoms3_lite: + +M5Stack AtomS3 Lite +################### + +Overview +******** + +M5Stack AtomS3 Lite is an ESP32-based development board from M5Stack. + +It features the following integrated components: + +- ESP32-S3FN8 chip (240MHz dual core, Wi-Fi/BLE 5.0) +- 512KB of SRAM +- 384KB of ROM +- 8MB of Flash +- RGB Status-LED + + +.. figure:: img/m5stack_atoms3_lite.webp + :align: center + :alt: M5Stack AtomS3 Lite + + M5Stack AtomS3 Lite + + +Supported Features +================== + +The Zephyr m5stack_atoms3_lite board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + + +Start Application Development +***************************** + +Before powering up your M5Stack AtomS3 Lite, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: shell + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_atoms3_lite/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``m5stack_atoms3_lite`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_atoms3_lite/esp32s3/procpu + :goals: flash + +The baud rate of 921600bps is set by default. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stack_atoms3_lite + +Debugging +--------- + +M5Stack AtomS3 Lite debugging is not supported due to pinout limitations. + +Related Documents +***************** + +- `M5Stack AtomS3 Lite schematic `_ +- `ESP32S3 Datasheet `_ diff --git a/boards/xtensa/m5stack_atoms3_lite/grove_connectors.dtsi b/boards/m5stack/m5stack_atoms3_lite/grove_connectors.dtsi similarity index 100% rename from boards/xtensa/m5stack_atoms3_lite/grove_connectors.dtsi rename to boards/m5stack/m5stack_atoms3_lite/grove_connectors.dtsi diff --git a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite-pinctrl.dtsi b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite-pinctrl.dtsi similarity index 100% rename from boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite-pinctrl.dtsi rename to boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite-pinctrl.dtsi diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.dts new file mode 100644 index 00000000000..994c9b9a3b2 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "M5Stack AtomS3 Lite APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.yaml b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.yaml new file mode 100644 index 00000000000..0a641e9ef12 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stack_atoms3_lite/esp32s3/appcpu +name: M5Stack AtomS3-Lite +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu_defconfig b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.dts new file mode 100644 index 00000000000..430de46a554 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.dts @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023 Benjamin Cabé + * Copyright (c) 2023 Martin Kiepfer + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stack_atoms3_lite-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "M5Stack AtomS3 Lite PROCPU"; + compatible = "m5stack,atoms3_lite"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + sw0 = &user_button_0; + watchdog0 = &wdt0; + i2c-0 = &i2c0; + led-strip = &status_rgb_led; + }; + + buttons { + compatible = "gpio-keys"; + debounce-interval-ms = <100>; + user_button_0: button_0 { + label = "User button 0"; + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "okay"; +}; +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + line-idle-low; + pinctrl-0 = <&spim3_ws2812_led>; + pinctrl-names = "default"; + + status_rgb_led: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + reg = <0>; + spi-max-frequency = ; + + chain-length = <1>; + color-mapping = , + , + ; + spi-one-frame = ; + spi-zero-frame = ; + }; +}; +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.yaml b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.yaml new file mode 100644 index 00000000000..3012207d36d --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.yaml @@ -0,0 +1,23 @@ +identifier: m5stack_atoms3_lite/esp32s3/procpu +name: M5Stack AtomS3-Lite +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - counter + - watchdog + - entropy + - pwm + - pinmux + - nvs + - dma +testing: + ignore_tags: + - net + - bluetooth +vendor: m5stack diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu_defconfig b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu_defconfig new file mode 100644 index 00000000000..d789bab1824 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/m5stack/m5stack_core2/Kconfig b/boards/m5stack/m5stack_core2/Kconfig new file mode 100644 index 00000000000..abe38faa5ec --- /dev/null +++ b/boards/m5stack/m5stack_core2/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_CORE2 + select SOC_ESP32_PROCPU if BOARD_M5STACK_CORE2_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_M5STACK_CORE2_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_core2/Kconfig.defconfig b/boards/m5stack/m5stack_core2/Kconfig.defconfig new file mode 100644 index 00000000000..6057cf0a0f5 --- /dev/null +++ b/boards/m5stack/m5stack_core2/Kconfig.defconfig @@ -0,0 +1,53 @@ +# M5Stack Core2 board configuration +# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_CORE2_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 65536 if BT + default 4096 + +config KERNEL_MEM_POOL + default y + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +config REGULATOR_AXP192_INIT_PRIORITY + default 81 + +config GPIO_HOGS_INIT_PRIORITY + default 82 + +config INPUT_FT5336_INTERRUPT + default y if INPUT + +config INPUT + default y + +config LV_COLOR_16_SWAP + default y if LVGL + +# Increase initialization priority of MIPI DBI device, so that it initializes +# after the GPIO controller +if MIPI_DBI + +config MIPI_DBI_INIT_PRIORITY + default 82 + +endif # MIPI_DBI + +endif # BOARD_M5STACK_CORE2_ESP32_PROCPU + +if BOARD_M5STACK_CORE2_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_M5STACK_CORE2_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_core2/Kconfig.m5stack_core2 b/boards/m5stack/m5stack_core2/Kconfig.m5stack_core2 new file mode 100644 index 00000000000..f6858d5a928 --- /dev/null +++ b/boards/m5stack/m5stack_core2/Kconfig.m5stack_core2 @@ -0,0 +1,7 @@ +# M5Stack Core2 board configuration + +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_CORE2 + select SOC_ESP32_D0WD_V3 diff --git a/boards/xtensa/esp_wrover_kit/board.cmake b/boards/m5stack/m5stack_core2/board.cmake similarity index 100% rename from boards/xtensa/esp_wrover_kit/board.cmake rename to boards/m5stack/m5stack_core2/board.cmake diff --git a/boards/m5stack/m5stack_core2/board.yml b/boards/m5stack/m5stack_core2/board.yml new file mode 100644 index 00000000000..1ff253f8201 --- /dev/null +++ b/boards/m5stack/m5stack_core2/board.yml @@ -0,0 +1,5 @@ +board: + name: m5stack_core2 + vendor: m5stack + socs: + - name: esp32 diff --git a/boards/xtensa/m5stack_core2/doc/img/m5stack_core2.webp b/boards/m5stack/m5stack_core2/doc/img/m5stack_core2.webp similarity index 100% rename from boards/xtensa/m5stack_core2/doc/img/m5stack_core2.webp rename to boards/m5stack/m5stack_core2/doc/img/m5stack_core2.webp diff --git a/boards/m5stack/m5stack_core2/doc/index.rst b/boards/m5stack/m5stack_core2/doc/index.rst new file mode 100644 index 00000000000..9dc66f5c9ba --- /dev/null +++ b/boards/m5stack/m5stack_core2/doc/index.rst @@ -0,0 +1,197 @@ +.. _m5stack_core2: + +M5Stack Core2 +############# + +Overview +******** + +M5Stack Core2 is an ESP32-based development board from M5Stack. It is the successor for the Core module. + +M5Stack Core2 features the following integrated components: + +- ESP32-D0WDQ6-V3 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi) +- PSRAM 8MB +- Flash 16MB +- LCD IPS TFT 2", 320x240 px screen (ILI9342C) +- Touch screen (FT6336U) +- PMU AXP192 +- Audio NS4168 amplifier (1W-092 speaker) +- Vibration motor +- RTC BM8563 +- USB CP2104 +- SD-Card slot +- IMO 6-axis IMU MPU6886 +- MIC SPM1423 +- Battery 390mAh 3,7V + +.. figure:: img/m5stack_core2.webp + :align: center + :alt: M5Stack-Core2 + :width: 400 px + + M5Stack-Core2 module + +Functional Description +********************** + +The following table below describes the key components, interfaces, and controls +of the M5Stack Core2 board. + +.. _M5Core2 Schematic: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/schematic/Core/CORE2_V1.0_SCH.pdf +.. _MPU-ESP32: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/esp32_datasheet_en_v3.9.pdf +.. _TOUCH-FT6336U: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/Ft6336GU_Firmware%20外部寄存器_20151112-%20EN.xlsx +.. _SND-NS4168: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/NS4168_CN_datasheet.pdf +.. _MPU-6886: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/MPU-6886-000193%2Bv1.1_GHIC_en.pdf +.. _LCD-ILI9342C: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/ILI9342C-ILITEK.pdf +.. _SPM-1423: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SPM1423HM4H-B_datasheet_en.pdf +.. _RTC-BM8563: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/BM8563_V1.1_cn.pdf +.. _SY7088: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SY7088-Silergy.pdf +.. _PMU-AXP192: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/AXP192_datasheet_en.pdf +.. _VIB-1072_RFN01: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/1027RFN01-33d.pdf + ++------------------+--------------------------------------------------------------------------+------------+ +| Key Component | Description | Status | ++==================+==========================================================================+============+ +|| ESP32-D0WDQ6-V2 || This `MPU-ESP32`_ module provides complete Wi-Fi and Bluetooth || supported | +|| module || functionalities and integrates a 16-MB SPI flash. || | ++------------------+--------------------------------------------------------------------------+------------+ +|| 32.768 kHz RTC || External precision 32.768 kHz crystal oscillator serves as a clock with || supported | +|| || low-power consumption while the chip is in Deep-sleep mode. || | ++------------------+--------------------------------------------------------------------------+------------+ +| Status LED | One user LED connected to the GPIO pin. | supported | ++------------------+--------------------------------------------------------------------------+------------+ +|| USB Port || USB interface. Power supply for the board as well as the || supported | +|| || communication interface between a computer and the board. || | +|| || Contains: TypeC x 1, GROVE(I2C+I/O+UART) x 1 || | ++------------------+--------------------------------------------------------------------------+------------+ +| Reset button | Reset button | supported | ++------------------+--------------------------------------------------------------------------+------------+ +| Power Switch | Power on/off button. | supported | ++------------------+--------------------------------------------------------------------------+------------+ +|| LCD screen || Built-in LCD TFT display \(`LCD-ILI9342C`_, 2", 320x240 px\) || supported | +|| || controlled via SPI interface || | ++------------------+--------------------------------------------------------------------------+------------+ +| SD-Card slot | SD-Card connection via SPI-mode. | supported | ++------------------+--------------------------------------------------------------------------+------------+ +|| 6-axis IMU || The `MPU-6886`_ is a 6-axis motion tracker (6DOF IMU) device that || todo | +|| MPU6886 || combines a 3-axis gyroscope and a 3-axis accelerometer. || | +|| || For details please refer to :ref:`m5stack_core2_ext` || | ++------------------+--------------------------------------------------------------------------+------------+ +|| Built-in || The `SPM-1423`_ I2S driven microphone. || todo | +|| microphone || || | ++------------------+--------------------------------------------------------------------------+------------+ +| Built-in speaker | 1W speaker for audio output via I2S interface. | todo | ++------------------+--------------------------------------------------------------------------+------------+ + +Supported Features +================== + +The Zephyr m5stack_core2 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + + +Start Application Development +***************************** + +Before powering up your M5Stack Core2, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_core2/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``m5stack_core2`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_core2/esp32/procpu + :goals: flash + +The baud rate of 921600bps is set by default. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stack_core2 + +Debugging +--------- + +M5Stack Core2 debugging is not supported due to pinout limitations. + +Related Documents +***************** + +- `M5StickC PLUS schematic `_ (WEBP) +- `ESP32-PICO-D4 Datasheet `_ (PDF) +- `M5StickC PLUS docs `_ +- `ESP32 Datasheet `_ (PDF) +- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stack_core2/grove_connectors.dtsi b/boards/m5stack/m5stack_core2/grove_connectors.dtsi similarity index 100% rename from boards/xtensa/m5stack_core2/grove_connectors.dtsi rename to boards/m5stack/m5stack_core2/grove_connectors.dtsi diff --git a/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi b/boards/m5stack/m5stack_core2/m5stack_core2-pinctrl.dtsi similarity index 100% rename from boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi rename to boards/m5stack/m5stack_core2/m5stack_core2-pinctrl.dtsi diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.dts new file mode 100644 index 00000000000..cd5cf5d0bf2 --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "M5Stack Core2 APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.yaml b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.yaml new file mode 100644 index 00000000000..8e5a51d07c7 --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stack_core2/esp32/appcpu +name: M5Stack Core2 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.dts new file mode 100644 index 00000000000..0ca3efab6cd --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.dts @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2023 Martin Kiepfer + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stack_core2-pinctrl.dtsi" +#include "grove_connectors.dtsi" +#include "m5stack_mbus_connectors.dtsi" +#include +#include + +/ { + model = "M5Stack Core2 PROCPU"; + compatible = "m5stack,core2"; + + aliases { + pwr-led = &pwr_led; + uart-0 = &uart0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + rtc = &pfc8563_rtc; + led0 = &led_pwr; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,display = &ili9342c; + zephyr,code-partition = &slot0_partition; + zephyr,rtc = &pfc8563_rtc; + }; + + leds { + compatible = "gpio-leds"; + led_pwr: led_pwr { + gpios = <&axp192_gpio 1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + label = "Power LED"; + }; + }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&ft5336_touch>; + swap-xy; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + dc-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + reset-gpios = <&axp192_gpio 4 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + spi-dev = <&spi3>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + ili9342c: ili9342c@0 { + compatible = "ilitek,ili9342c"; + mipi-max-frequency = <30000000>; + reg = <0>; + vin-supply = <&lcd_bg>; + pixel-format = ; + display-inversion; + width = <320>; + height = <240>; + rotation = <0>; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&psram0 { + reg = <0x3f800000 DT_SIZE_M(8)>; + status = "disabled"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_tx_gpio1 &uart0_rx_gpio3>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_gpio33 &uart1_tx_gpio32>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + scl-timeout-us = <0>; + pinctrl-names = "default"; + + pfc8563_rtc: pfc8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + status = "okay"; + }; + + axp192_pmic: axp192@34 { + compatible = "x-powers,axp192"; + reg = <0x34>; + status = "okay"; + + axp192_regulator: axp192_regulator { + compatible = "x-powers,axp192-regulator"; + status = "okay"; + + vdd_mcu: DCDC1 { + regulator-init-microvolt = <3350000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + regulator-boot-on; + regulator-always-on; + }; + + lcd_bg: DCDC3 { + regulator-init-microvolt = <2800000>; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + v_peri: LDO2 { + regulator-init-microvolt = <3300000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + vib_motor: LDO3 { + regulator-init-microvolt = <2800000>; + }; + }; + + axp192_gpio: axp192_gpio { + compatible = "x-powers,axp192-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <5>; + status = "okay"; + + pwr_led: axp192_gpio1 { + gpio-hog; + gpios = <1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + output-high; + line-name = "pwr-led"; + }; + + bus_pwr_en: axp192_gpio0 { + gpio-hog; + gpios = <0 0>; + input; + }; + }; + }; + + ft5336_touch: ft5336@38 { + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&gpio1 7 0>; + }; +}; + +&i2c1 { + status = "disabled"; + clock-frequency = ; + sda-gpios = <&gpio1 0 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio1 1 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + dma-enabled; + clock-frequency = <20000000>; + cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>, + <&gpio0 4 GPIO_ACTIVE_LOW>; + + sdhc0: sdhc@1 { + compatible = "zephyr,sdhc-spi-slot"; + reg = <1>; + status = "okay"; + spi-max-frequency = <20000000>; + mmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + + }; +}; + + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + reg = <0 DT_SIZE_M(16)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + /* 14MB storage */ + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00db0000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.yaml b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.yaml new file mode 100644 index 00000000000..b5f7a37910d --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.yaml @@ -0,0 +1,20 @@ +identifier: m5stack_core2/esp32/procpu +name: M5Stack Core2 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - regulator + - uart + - pinmux + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: m5stack diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu_defconfig b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu_defconfig new file mode 100644 index 00000000000..008eb0afc9e --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_ESP_HEAP_MEM_POOL_REGION_1_SIZE=0 + +CONFIG_GPIO=y + +CONFIG_REGULATOR=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +# for debugging +CONFIG_SHELL=y diff --git a/boards/xtensa/m5stack_core2/m5stack_mbus_connectors.dtsi b/boards/m5stack/m5stack_core2/m5stack_mbus_connectors.dtsi similarity index 100% rename from boards/xtensa/m5stack_core2/m5stack_mbus_connectors.dtsi rename to boards/m5stack/m5stack_core2/m5stack_mbus_connectors.dtsi diff --git a/boards/xtensa/m5stack_core2/support/openocd.cfg b/boards/m5stack/m5stack_core2/support/openocd.cfg similarity index 100% rename from boards/xtensa/m5stack_core2/support/openocd.cfg rename to boards/m5stack/m5stack_core2/support/openocd.cfg diff --git a/boards/m5stack/m5stack_stamps3/Kconfig b/boards/m5stack/m5stack_stamps3/Kconfig new file mode 100644 index 00000000000..3bc66a42ed4 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_STAMPS3 + select SOC_ESP32S3_PROCPU if BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_stamps3/Kconfig.defconfig b/boards/m5stack/m5stack_stamps3/Kconfig.defconfig new file mode 100644 index 00000000000..70493b8d475 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/Kconfig.defconfig @@ -0,0 +1,28 @@ +# M5Stack StampS3 board configuration +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +config KERNEL_MEM_POOL + default y + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU + +if BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_stamps3/Kconfig.m5stack_stamps3 b/boards/m5stack/m5stack_stamps3/Kconfig.m5stack_stamps3 new file mode 100644 index 00000000000..a48130faf89 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/Kconfig.m5stack_stamps3 @@ -0,0 +1,7 @@ +# M5Stack StampS3 board configuration + +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_STAMPS3 + select SOC_ESP32S3_FN8 diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/board.cmake b/boards/m5stack/m5stack_stamps3/board.cmake similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/board.cmake rename to boards/m5stack/m5stack_stamps3/board.cmake diff --git a/boards/m5stack/m5stack_stamps3/board.yml b/boards/m5stack/m5stack_stamps3/board.yml new file mode 100644 index 00000000000..e723d91c19a --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/board.yml @@ -0,0 +1,5 @@ +board: + name: m5stack_stamps3 + vendor: m5stack + socs: + - name: esp32s3 diff --git a/boards/xtensa/m5stack_stamps3/doc/img/m5stack_stamps3.webp b/boards/m5stack/m5stack_stamps3/doc/img/m5stack_stamps3.webp similarity index 100% rename from boards/xtensa/m5stack_stamps3/doc/img/m5stack_stamps3.webp rename to boards/m5stack/m5stack_stamps3/doc/img/m5stack_stamps3.webp diff --git a/boards/xtensa/m5stack_stamps3/doc/img/m5stack_stamps3_header.webp b/boards/m5stack/m5stack_stamps3/doc/img/m5stack_stamps3_header.webp similarity index 100% rename from boards/xtensa/m5stack_stamps3/doc/img/m5stack_stamps3_header.webp rename to boards/m5stack/m5stack_stamps3/doc/img/m5stack_stamps3_header.webp diff --git a/boards/m5stack/m5stack_stamps3/doc/index.rst b/boards/m5stack/m5stack_stamps3/doc/index.rst new file mode 100644 index 00000000000..59e1d5145aa --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/doc/index.rst @@ -0,0 +1,199 @@ +.. _m5stack_stamps3: + +M5Stack StampS3 +############### + +Overview +******** + +M5Stack StampS3 is an ESP32-based development board from M5Stack. +It features the following integrated components: + +- ESP32-S3FN8 chip (240MHz dual core) +- 512KB SRAM +- 384KB ROM +- 8MB Flash +- Wi-Fi +- Bluetooth +- User-Button + +.. figure:: img/m5stack_stamps3.webp + :align: center + :alt: M5Stack StampS3 + :width: 400 px + + M5Stack StampS3 module + +Functional Description +********************** + +The following table below describes the key components, interfaces, and controls +of the M5Stack StampS3 module. + ++---------------+-----------------------------------------------------------------+-----------+ +| Key Component | Description | Status | ++===============+=================================================================+===========+ +| ESP32-S3FN8 | This MPU-ESP32S3 module provides complete Wi-Fi and Bluetooth | supported | +| module | functionalities and integrates a 8MB flash. | | ++---------------+-----------------------------------------------------------------+-----------+ +| Status LED | One user LED connected via :dtcompatible:`worldsemi,ws2812-spi` | supported | +| | interface (``led-strip``). | | ++---------------+-----------------------------------------------------------------+-----------+ +| USB Port | USB interface. Power supply for the board as well as the | supported | +| | communication interface between a computer and the board. | | ++---------------+-----------------------------------------------------------------+-----------+ +| User button | User button (``sw0``) | supported | ++---------------+-----------------------------------------------------------------+-----------+ + +Main connector header +===================== + +The Zephyr m5stack_stamps3 board can be used on various applications. It +therefore publishes a header definition to be used in different shields: +:dtcompatible:`m5stack,stamps3-header`. + +.. figure:: img/m5stack_stamps3_header.webp + :align: center + :alt: M5Stack StampS3 Header + :width: 400 px + + M5Stack StampS3 connector header + +Following interfaces are being exported for this header: + +- ``m5stack_stamps3_clkout0``: PWM output with 2 channels (0 and 2). +- ``m5stack_stamps3_spilcd``: SPI interface for interfacing LCDs. Consists of a + CLK, MOSI and CS signal. +- ``m5stack_stamps3_i2c0`` and ``m5stack_stamps3_i2c1``: I2C interfaces (SDA, SCL). +- ``m5stack_stamps3_uart0``: UART interface (RXD, TXD). +- ``m5stack_stamps3_header``: All GPIOs are of course accessible via main header + definition. + ++-----+-----------------------------------------+-----+---------------------------------+ +| Pin | Functions | Pin | Functions | ++=====+=========================================+=====+=================================+ +| 1 | | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 2 | | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 3 | ``m5stack_stamps3_clkout0`` - Channel 0 | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 4 | | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 5 | ``m5stack_stamps3_spilcd`` - MOSI | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 6 | ``m5stack_stamps3_spilcd`` - CLK | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 7 | ``m5stack_stamps3_spilcd`` - CS | 28 | **3V3** | ++-----+-----------------------------------------+-----+---------------------------------+ +| 8 | | 27 | ``m5stack_stamps3_uart0`` - TXD | ++-----+-----------------------------------------+-----+---------------------------------+ +| 9 | ``m5stack_stamps3_clkout0`` - Channel 2 | 26 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 10 | | 25 | ``m5stack_stamps3_uart0`` - RXD | ++-----+-----------------------------------------+-----+---------------------------------+ +| 11 | **GND** | 24 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 12 | ``m5stack_stamps3_i2c1`` - SDA | 23 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 13 | **5V** | 22 | **EN** | ++-----+-----------------------------------------+-----+---------------------------------+ +| 14 | ``m5stack_stamps3_i2c1`` - SCL | 21 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 15 | ``m5stack_stamps3_i2c0`` - SDA | 20 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 16 | | 19 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 17 | ``m5stack_stamps3_i2c0`` - SCL | 18 | **GND** | ++-----+-----------------------------------------+-----+---------------------------------+ + +Power supply +============ + +M5Stack StampS3 requires a single 5V input power supply. The module internally +features a DCDC (MUN3CAD01-SC) to generate the 3.3V needed for the MCU. + +The **EN** signal (Pin 22) is an active low signal to enable the **3V3** power +supply. If this pin is pulled low this main 3.3V power supply for the MCU will be +deactivated. It is internally equipped with a pull-up and can hence be left open +if unused. + +Start Application Development +***************************** + +Before powering up your M5Stack StampS3, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_stamps3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``m5stack_stamps3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_stamps3/esp32s3/procpu + :goals: flash + +The baud rate of 921600bps is set by default. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stack_stamps3 + +Debugging +--------- + +M5Stack StampS3 exports a JTAG-interface via Pins 19 (MTCK), 21 (MTDO), 23 +(MTDI), 25 (MTMS). + +.. note:: + + Please note that additional JTAG equipment is needed to utilize JTAG. Refer to + the ESP32S3 datasheet and the M5Stack StampS3 documentation for details. + +Related Documents +***************** + +- `M5Stack StampS3 schematic `_ +- `M5Stack StampS3 `_ +- `ESP32 Datasheet `_ (PDF) +- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stack_stamps3/m5stack_stamps3-pinctrl.dtsi b/boards/m5stack/m5stack_stamps3/m5stack_stamps3-pinctrl.dtsi similarity index 100% rename from boards/xtensa/m5stack_stamps3/m5stack_stamps3-pinctrl.dtsi rename to boards/m5stack/m5stack_stamps3/m5stack_stamps3-pinctrl.dtsi diff --git a/boards/xtensa/m5stack_stamps3/m5stack_stamps3_connectors.dtsi b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_connectors.dtsi similarity index 100% rename from boards/xtensa/m5stack_stamps3/m5stack_stamps3_connectors.dtsi rename to boards/m5stack/m5stack_stamps3/m5stack_stamps3_connectors.dtsi diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.dts new file mode 100644 index 00000000000..a9e590b9bbf --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "M5Stack StampS3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.yaml b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.yaml new file mode 100644 index 00000000000..eb4fcfcd028 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stack_stamps3/esp32s3/appcpu +name: M5Stack StampS3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.dts new file mode 100644 index 00000000000..f832f4618ba --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.dts @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2023 Martin Kiepfer + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stack_stamps3-pinctrl.dtsi" +#include "m5stack_stamps3_connectors.dtsi" +#include +#include +#include +#include + +/ { + model = "M5Stack StampS3 PROCPU"; + compatible = "m5stack,stamps3"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + sw0 = &user_button_0; + watchdog0 = &wdt0; + //pwm-0 = &ledc0; + i2c-0 = &i2c0; + led-strip = &status_rgb_led; + }; + + gpio_keys { + compatible = "gpio-keys"; + + /* This is the button that's underneath the LCD display */ + user_button_0: button_0 { + label = "User button 0"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&mcpwm0 { + status = "okay"; + pinctrl-0 = <&mcpwm0_default>; + pinctrl-names = "default"; + prescale = <255>; + prescale-timer0 = <100>; + prescale-timer1 = <100>; +}; + +&ledc0 { + pinctrl-0 = <&ledc0_default>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + channel0@0 { + reg = <0x0>; + timer = <0>; + }; + channel0@1 { + reg = <0x1>; + timer = <0>; + }; +}; + + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + line-idle-low; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + + status_rgb_led: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + reg = <0x0>; + spi-max-frequency = ; + + chain-length = <1>; + color-mapping = , + , + ; + spi-one-frame = ; + spi-zero-frame = ; + reset-delay = <250>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.yaml b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.yaml new file mode 100644 index 00000000000..99e14f59b19 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.yaml @@ -0,0 +1,20 @@ +identifier: m5stack_stamps3/esp32s3/procpu +name: M5Stack StampS3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - pwm + - pinmux + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: m5stack diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu_defconfig b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu_defconfig new file mode 100644 index 00000000000..466f9999601 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_GPIO=y + +CONFIG_CONSOLE=y +CONFIG_PWM=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/m5stack/m5stickc_plus/Kconfig b/boards/m5stack/m5stickc_plus/Kconfig new file mode 100644 index 00000000000..0befa89fc68 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STICKC_PLUS + select SOC_ESP32_PROCPU if BOARD_M5STICKC_PLUS_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_M5STICKC_PLUS_ESP32_APPCPU diff --git a/boards/m5stack/m5stickc_plus/Kconfig.defconfig b/boards/m5stack/m5stickc_plus/Kconfig.defconfig new file mode 100644 index 00000000000..638a054bec1 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/Kconfig.defconfig @@ -0,0 +1,26 @@ +# M5StickC PLUS board configuration + +# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STICKC_PLUS_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_M5STICKC_PLUS_ESP32_PROCPU + +if BOARD_M5STICKC_PLUS_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_M5STICKC_PLUS_ESP32_APPCPU diff --git a/boards/m5stack/m5stickc_plus/Kconfig.m5stickc_plus b/boards/m5stack/m5stickc_plus/Kconfig.m5stickc_plus new file mode 100644 index 00000000000..9ab1db5c121 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/Kconfig.m5stickc_plus @@ -0,0 +1,7 @@ +# M5StickC PLUS board configuration + +# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STICKC_PLUS + select SOC_ESP32_PICO_D4 diff --git a/boards/xtensa/m5stack_atoms3_lite/Kconfig.sysbuild b/boards/m5stack/m5stickc_plus/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/m5stack_atoms3_lite/Kconfig.sysbuild rename to boards/m5stack/m5stickc_plus/Kconfig.sysbuild diff --git a/boards/xtensa/m5stickc_plus/board.cmake b/boards/m5stack/m5stickc_plus/board.cmake similarity index 100% rename from boards/xtensa/m5stickc_plus/board.cmake rename to boards/m5stack/m5stickc_plus/board.cmake diff --git a/boards/m5stack/m5stickc_plus/board.yml b/boards/m5stack/m5stickc_plus/board.yml new file mode 100644 index 00000000000..3a604266d07 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/board.yml @@ -0,0 +1,5 @@ +board: + name: m5stickc_plus + vendor: m5stack + socs: + - name: esp32 diff --git a/boards/m5stack/m5stickc_plus/doc/index.rst b/boards/m5stack/m5stickc_plus/doc/index.rst new file mode 100644 index 00000000000..1e5907d50cd --- /dev/null +++ b/boards/m5stack/m5stickc_plus/doc/index.rst @@ -0,0 +1,218 @@ +.. _m5stickc_plus: + +M5StickC PLUS +############# + +Overview +******** + +M5StickC PLUS, one of the core devices in M5Stacks product series, is an ESP32-based development board. + +M5StickC PLUS features the following integrated components: + +- ESP32-PICO-D4 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi) +- ST7789v2, LCD TFT 1.14", 135x240 px screen +- IMU MPU-6886 +- SPM-1423 microphone +- RTC BM8563 +- PMU AXP192 +- 120 mAh 3,7 V battery + +Some of the ESP32 I/O pins are broken out to the board's pin headers for easy access. + +Functional Description +********************** + +The following table below describes the key components, interfaces, and controls +of the M5StickC PLUS board. + +.. _ST7789v2: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/ST7789V.pdf +.. _MPU-6886: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/MPU-6886-000193%2Bv1.1_GHIC_en.pdf +.. _ESP32-PICO-D4: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/esp32-pico-d4_datasheet_en.pdf +.. _SPM-1423: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SPM1423HM4H-B_datasheet_en.pdf + ++------------------+-------------------------------------------------------------------------+ +| Key Component | Description | ++==================+=========================================================================+ +| 32.768 kHz RTC | External precision 32.768 kHz crystal oscillator serves as a clock with | +| | low-power consumption while the chip is in Deep-sleep mode. | ++------------------+-------------------------------------------------------------------------+ +| ESP32-PICO-D4 | This `ESP32-PICO-D4`_ module provides complete Wi-Fi and Bluetooth | +| module | functionalities and integrates a 4-MB SPI flash. | ++------------------+-------------------------------------------------------------------------+ +| Diagnostic LED | One user LED connected to the GPIO pin. | ++------------------+-------------------------------------------------------------------------+ +| USB Port | USB interface. Power supply for the board as well as the | +| | communication interface between a computer and the board. | +| | Contains: TypeC x 1, GROVE(I2C+I/O+UART) x 1 | ++------------------+-------------------------------------------------------------------------+ +| Power Switch | Power on/off button. | ++------------------+-------------------------------------------------------------------------+ +| A/B user buttons | Two push buttons intended for any user use. | ++------------------+-------------------------------------------------------------------------+ +| LCD screen | Built-in LCD TFT display \(`ST7789v2`_, 1.14", 135x240 px\) controlled | +| | by the SPI interface | ++------------------+-------------------------------------------------------------------------+ +| MPU-6886 | The `MPU-6886`_ is a 6-axis MotionTracking device that combines a | +| | 3-axis gyroscope and a 3-axis accelerometer. | ++------------------+-------------------------------------------------------------------------+ +| Built-in | The `SPM-1423`_ I2S driven microphone. | +| microphone | | ++------------------+-------------------------------------------------------------------------+ + + +Start Application Development +***************************** + +Before powering up your M5StickC PLUS, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: m5stickc_plus + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stickc_plus/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``m5stickc_plus`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stickc_plus/esp32/procpu + :goals: flash + +The default baud rate for the M5StickC PLUS is set to 1500000bps. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stickc_plus + +Debugging +********* + +M5StickC PLUS debugging is not supported due to pinout limitations. + +Related Documents +***************** + +- `M5StickC PLUS schematic `_ (WEBP) +- `ESP32-PICO-D4 Datasheet `_ (PDF) +- `M5StickC PLUS docs `_ +- `ESP32 Datasheet `_ (PDF) +- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stickc_plus/m5stickc_plus-pinctrl.dtsi b/boards/m5stack/m5stickc_plus/m5stickc_plus-pinctrl.dtsi similarity index 100% rename from boards/xtensa/m5stickc_plus/m5stickc_plus-pinctrl.dtsi rename to boards/m5stack/m5stickc_plus/m5stickc_plus-pinctrl.dtsi diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.dts new file mode 100644 index 00000000000..8b7e74fdd98 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "M5StickC Plus APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.yaml b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.yaml new file mode 100644 index 00000000000..e436849ced4 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stickc_plus/esp32/appcpu +name: M5StickC PLUS +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.dts new file mode 100644 index 00000000000..2f0f6975bba --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.dts @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stickc_plus-pinctrl.dtsi" +#include + +/ { + model = "M5StickC Plus PROCPU"; + compatible = "m5stack,m5stickc-plus"; + + aliases { + led0 = &red_led; + sw0 = &user_button_0; + sw1 = &user_button_1; + uart-0 = &uart0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + + red_led: led_0 { + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + label = "Red - LED0"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button_0: button_0 { + label = "User button 0"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_1: button_1 { + label = "User button 1"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_tx_gpio1 &uart0_rx_gpio3>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +/* IMU MPU-6886, RTC BM8563, PMU AXP192 */ +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_sda_gpio21 &i2c0_scl_gpio22>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_miso_gpio12 &spim2_mosi_gpio11 + &spim2_sclk_gpio14 &spim2_csel_gpio16>; + pinctrl-names = "default"; +}; + +/* LCD TFT 1.14", 135x240 px, ST7789v2 */ +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_miso_gpio25 &spim3_mosi_gpio15 + &spim3_sclk_gpio13 &spim3_csel_gpio5>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.yaml b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.yaml new file mode 100644 index 00000000000..24499601d4a --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.yaml @@ -0,0 +1,19 @@ +identifier: m5stickc_plus/esp32/procpu +name: M5StickC PLUS +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - pinmux + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: m5stack diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu_defconfig b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu_defconfig new file mode 100644 index 00000000000..ee9920cda68 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/xtensa/m5stickc_plus/support/openocd.cfg b/boards/m5stack/m5stickc_plus/support/openocd.cfg similarity index 100% rename from boards/xtensa/m5stickc_plus/support/openocd.cfg rename to boards/m5stack/m5stickc_plus/support/openocd.cfg diff --git a/boards/m5stack/stamp_c3/Kconfig.defconfig b/boards/m5stack/stamp_c3/Kconfig.defconfig new file mode 100644 index 00000000000..4ce7fe02e12 --- /dev/null +++ b/boards/m5stack/stamp_c3/Kconfig.defconfig @@ -0,0 +1,19 @@ +# M5Stack STAMP-C3 board configuration + +# Copyright 2022 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +if BT + +choice BT_HCI_BUS_TYPE + default BT_ESP32 +endchoice + +endif # BT diff --git a/boards/m5stack/stamp_c3/Kconfig.stamp_c3 b/boards/m5stack/stamp_c3/Kconfig.stamp_c3 new file mode 100644 index 00000000000..dd126de3dfd --- /dev/null +++ b/boards/m5stack/stamp_c3/Kconfig.stamp_c3 @@ -0,0 +1,7 @@ +# M5Stack STAMP-C3 board configuration + +# Copyright 2022 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STAMP_C3 + select SOC_ESP32C3_FX4 diff --git a/boards/xtensa/m5stickc_plus/Kconfig.sysbuild b/boards/m5stack/stamp_c3/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/m5stickc_plus/Kconfig.sysbuild rename to boards/m5stack/stamp_c3/Kconfig.sysbuild diff --git a/boards/xtensa/m5stack_atoms3/board.cmake b/boards/m5stack/stamp_c3/board.cmake similarity index 100% rename from boards/xtensa/m5stack_atoms3/board.cmake rename to boards/m5stack/stamp_c3/board.cmake diff --git a/boards/m5stack/stamp_c3/board.yml b/boards/m5stack/stamp_c3/board.yml new file mode 100644 index 00000000000..aa24963edd6 --- /dev/null +++ b/boards/m5stack/stamp_c3/board.yml @@ -0,0 +1,5 @@ +board: + name: stamp_c3 + vendor: m5stack + socs: + - name: esp32c3 diff --git a/boards/m5stack/stamp_c3/doc/index.rst b/boards/m5stack/stamp_c3/doc/index.rst new file mode 100644 index 00000000000..9ac2a05b7ec --- /dev/null +++ b/boards/m5stack/stamp_c3/doc/index.rst @@ -0,0 +1,205 @@ +.. _stamp_c3: + +M5Stack STAMP-C3 +################## + +Overview +******** + +STAMP-C3 featuring ESPRESSIF ESP32-C3 RISC-V MCU with Wi-Fi connectivity +for IoT edge devices such as home appliances and Industrial Automation. + +For more details see the `M5Stack STAMP-C3`_ page. + +Supported Features +================== + +The STAMP-C3 board configuration supports the following hardware features: + ++-----------+------------+------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==================+ +| PMP | on-chip | arch/riscv | ++-----------+------------+------------------+ +| INTMTRX | on-chip | intc_esp32c3 | ++-----------+------------+------------------+ +| PINMUX | on-chip | pinctrl_esp32 | ++-----------+------------+------------------+ +| USB UART | on-chip | serial_esp32_usb | ++-----------+------------+------------------+ +| GPIO | on-chip | gpio_esp32 | ++-----------+------------+------------------+ +| UART | on-chip | uart_esp32 | ++-----------+------------+------------------+ +| I2C | on-chip | i2c_esp32 | ++-----------+------------+------------------+ +| SPI | on-chip | spi_esp32_spim | ++-----------+------------+------------------+ +| TWAI | on-chip | can_esp32_twai | ++-----------+------------+------------------+ + + +Prerequisites +************* + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: stamp_c3 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: build + +The usual ``flash`` target will work with the ``stamp_c3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! stamp_c3 + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: debug + +References +********** + +.. target-notes:: + +.. _`M5Stack STAMP-C3`: https://docs.m5stack.com/en/core/stamp_c3 +.. _`ESP32C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _`ESP32C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/riscv/stamp_c3/stamp_c3-pinctrl.dtsi b/boards/m5stack/stamp_c3/stamp_c3-pinctrl.dtsi similarity index 100% rename from boards/riscv/stamp_c3/stamp_c3-pinctrl.dtsi rename to boards/m5stack/stamp_c3/stamp_c3-pinctrl.dtsi diff --git a/boards/riscv/stamp_c3/stamp_c3.dts b/boards/m5stack/stamp_c3/stamp_c3.dts similarity index 100% rename from boards/riscv/stamp_c3/stamp_c3.dts rename to boards/m5stack/stamp_c3/stamp_c3.dts diff --git a/boards/riscv/stamp_c3/stamp_c3.yaml b/boards/m5stack/stamp_c3/stamp_c3.yaml similarity index 100% rename from boards/riscv/stamp_c3/stamp_c3.yaml rename to boards/m5stack/stamp_c3/stamp_c3.yaml diff --git a/boards/m5stack/stamp_c3/stamp_c3_defconfig b/boards/m5stack/stamp_c3/stamp_c3_defconfig new file mode 100644 index 00000000000..ef633ce56a1 --- /dev/null +++ b/boards/m5stack/stamp_c3/stamp_c3_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/riscv/stamp_c3/support/openocd.cfg b/boards/m5stack/stamp_c3/support/openocd.cfg similarity index 100% rename from boards/riscv/stamp_c3/support/openocd.cfg rename to boards/m5stack/stamp_c3/support/openocd.cfg diff --git a/boards/madmachine/index.rst b/boards/madmachine/index.rst new file mode 100644 index 00000000000..a43bebd08ad --- /dev/null +++ b/boards/madmachine/index.rst @@ -0,0 +1,10 @@ +.. _boards-mad-machine: + +Mad Machine +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/madmachine/mm_feather/CMakeLists.txt b/boards/madmachine/mm_feather/CMakeLists.txt new file mode 100644 index 00000000000..623a4b901ac --- /dev/null +++ b/boards/madmachine/mm_feather/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (c) 2021 MADMACHINE LIMITED +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR flexspi_nor_config.c) + zephyr_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA mmfeather_sdram_ini_dcd.c) +endif() diff --git a/boards/madmachine/mm_feather/Kconfig.defconfig b/boards/madmachine/mm_feather/Kconfig.defconfig new file mode 100644 index 00000000000..a2503d832b4 --- /dev/null +++ b/boards/madmachine/mm_feather/Kconfig.defconfig @@ -0,0 +1,18 @@ +# MM-FEATHER board + +# Copyright (c) 2021, MADMACHINE LIMITED +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MM_FEATHER + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_MM_FEATHER diff --git a/boards/madmachine/mm_feather/Kconfig.mm_feather b/boards/madmachine/mm_feather/Kconfig.mm_feather new file mode 100644 index 00000000000..33a0180483d --- /dev/null +++ b/boards/madmachine/mm_feather/Kconfig.mm_feather @@ -0,0 +1,7 @@ +# Copyright (c) 2021, MADMACHINE LIMITED +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MM_FEATHER + select SOC_PART_NUMBER_MIMXRT1062DVL6A + select SOC_MIMXRT1062 diff --git a/boards/arm/mm_feather/board.cmake b/boards/madmachine/mm_feather/board.cmake similarity index 100% rename from boards/arm/mm_feather/board.cmake rename to boards/madmachine/mm_feather/board.cmake diff --git a/boards/madmachine/mm_feather/board.yml b/boards/madmachine/mm_feather/board.yml new file mode 100644 index 00000000000..1b9ca3f2c7c --- /dev/null +++ b/boards/madmachine/mm_feather/board.yml @@ -0,0 +1,5 @@ +board: + name: mm_feather + vendor: madmachine + socs: + - name: mimxrt1062 diff --git a/boards/arm/mm_feather/doc/index.rst b/boards/madmachine/mm_feather/doc/index.rst similarity index 100% rename from boards/arm/mm_feather/doc/index.rst rename to boards/madmachine/mm_feather/doc/index.rst diff --git a/boards/arm/mm_feather/doc/mm_feather.jpg b/boards/madmachine/mm_feather/doc/mm_feather.jpg similarity index 100% rename from boards/arm/mm_feather/doc/mm_feather.jpg rename to boards/madmachine/mm_feather/doc/mm_feather.jpg diff --git a/boards/madmachine/mm_feather/flexspi_nor_config.c b/boards/madmachine/mm_feather/flexspi_nor_config.c new file mode 100644 index 00000000000..c229eda7d99 --- /dev/null +++ b/boards/madmachine/mm_feather/flexspi_nor_config.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2019, MADMACHINE LIMITED + * + * refer to hal_nxp board file + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const struct flexspi_nor_config_t Qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = { + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, + 0x06, READ_SDR, + FLEXSPI_4PAD, 0x04), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ diff --git a/boards/arm/mm_feather/mm_feather-pinctrl.dtsi b/boards/madmachine/mm_feather/mm_feather-pinctrl.dtsi similarity index 100% rename from boards/arm/mm_feather/mm_feather-pinctrl.dtsi rename to boards/madmachine/mm_feather/mm_feather-pinctrl.dtsi diff --git a/boards/arm/mm_feather/mm_feather.dts b/boards/madmachine/mm_feather/mm_feather.dts similarity index 100% rename from boards/arm/mm_feather/mm_feather.dts rename to boards/madmachine/mm_feather/mm_feather.dts diff --git a/boards/arm/mm_feather/mm_feather.yaml b/boards/madmachine/mm_feather/mm_feather.yaml similarity index 100% rename from boards/arm/mm_feather/mm_feather.yaml rename to boards/madmachine/mm_feather/mm_feather.yaml diff --git a/boards/arm/mm_feather/mm_feather_defconfig b/boards/madmachine/mm_feather/mm_feather_defconfig similarity index 83% rename from boards/arm/mm_feather/mm_feather_defconfig rename to boards/madmachine/mm_feather/mm_feather_defconfig index 1ec155fc2fe..65cb3610d48 100644 --- a/boards/arm/mm_feather/mm_feather_defconfig +++ b/boards/madmachine/mm_feather/mm_feather_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/mm_feather/mmfeather_sdram_ini_dcd.c b/boards/madmachine/mm_feather/mmfeather_sdram_ini_dcd.c similarity index 100% rename from boards/arm/mm_feather/mmfeather_sdram_ini_dcd.c rename to boards/madmachine/mm_feather/mmfeather_sdram_ini_dcd.c diff --git a/boards/madmachine/mm_swiftio/CMakeLists.txt b/boards/madmachine/mm_swiftio/CMakeLists.txt new file mode 100644 index 00000000000..c3084a6b71b --- /dev/null +++ b/boards/madmachine/mm_swiftio/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (c) 20179 MADMACHINE LIMITED +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR flexspi_nor_config.c) + zephyr_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA mmswiftio_sdram_ini_dcd.c) +endif() diff --git a/boards/madmachine/mm_swiftio/Kconfig.defconfig b/boards/madmachine/mm_swiftio/Kconfig.defconfig new file mode 100644 index 00000000000..207e95b6757 --- /dev/null +++ b/boards/madmachine/mm_swiftio/Kconfig.defconfig @@ -0,0 +1,18 @@ +# MM-SWIFTIO board + +# Copyright (c) 2019, MADMACHINE LIMITED +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MM_SWIFTIO + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_MM_SWIFTIO diff --git a/boards/madmachine/mm_swiftio/Kconfig.mm_swiftio b/boards/madmachine/mm_swiftio/Kconfig.mm_swiftio new file mode 100644 index 00000000000..11ed8ddafd5 --- /dev/null +++ b/boards/madmachine/mm_swiftio/Kconfig.mm_swiftio @@ -0,0 +1,6 @@ +# Copyright (c) 2019, MADMACHINE LIMITED +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MM_SWIFTIO + select SOC_PART_NUMBER_MIMXRT1052DVL6B diff --git a/boards/arm/mm_swiftio/board.cmake b/boards/madmachine/mm_swiftio/board.cmake similarity index 100% rename from boards/arm/mm_swiftio/board.cmake rename to boards/madmachine/mm_swiftio/board.cmake diff --git a/boards/madmachine/mm_swiftio/board.yml b/boards/madmachine/mm_swiftio/board.yml new file mode 100644 index 00000000000..784e79c52ad --- /dev/null +++ b/boards/madmachine/mm_swiftio/board.yml @@ -0,0 +1,5 @@ +board: + name: mm_swiftio + vendor: madmachine + socs: + - name: mimxrt1052 diff --git a/boards/arm/mm_swiftio/doc/index.rst b/boards/madmachine/mm_swiftio/doc/index.rst similarity index 100% rename from boards/arm/mm_swiftio/doc/index.rst rename to boards/madmachine/mm_swiftio/doc/index.rst diff --git a/boards/arm/mm_swiftio/doc/mm_swiftio.jpg b/boards/madmachine/mm_swiftio/doc/mm_swiftio.jpg similarity index 100% rename from boards/arm/mm_swiftio/doc/mm_swiftio.jpg rename to boards/madmachine/mm_swiftio/doc/mm_swiftio.jpg diff --git a/boards/madmachine/mm_swiftio/flexspi_nor_config.c b/boards/madmachine/mm_swiftio/flexspi_nor_config.c new file mode 100644 index 00000000000..c229eda7d99 --- /dev/null +++ b/boards/madmachine/mm_swiftio/flexspi_nor_config.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2019, MADMACHINE LIMITED + * + * refer to hal_nxp board file + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const struct flexspi_nor_config_t Qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = { + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, + 0x06, READ_SDR, + FLEXSPI_4PAD, 0x04), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ diff --git a/boards/arm/mm_swiftio/mm_swiftio-pinctrl.dtsi b/boards/madmachine/mm_swiftio/mm_swiftio-pinctrl.dtsi similarity index 100% rename from boards/arm/mm_swiftio/mm_swiftio-pinctrl.dtsi rename to boards/madmachine/mm_swiftio/mm_swiftio-pinctrl.dtsi diff --git a/boards/arm/mm_swiftio/mm_swiftio.dts b/boards/madmachine/mm_swiftio/mm_swiftio.dts similarity index 100% rename from boards/arm/mm_swiftio/mm_swiftio.dts rename to boards/madmachine/mm_swiftio/mm_swiftio.dts diff --git a/boards/arm/mm_swiftio/mm_swiftio.yaml b/boards/madmachine/mm_swiftio/mm_swiftio.yaml similarity index 100% rename from boards/arm/mm_swiftio/mm_swiftio.yaml rename to boards/madmachine/mm_swiftio/mm_swiftio.yaml diff --git a/boards/arm/mm_swiftio/mm_swiftio_defconfig b/boards/madmachine/mm_swiftio/mm_swiftio_defconfig similarity index 83% rename from boards/arm/mm_swiftio/mm_swiftio_defconfig rename to boards/madmachine/mm_swiftio/mm_swiftio_defconfig index d09c986b33a..0aee57c3625 100644 --- a/boards/arm/mm_swiftio/mm_swiftio_defconfig +++ b/boards/madmachine/mm_swiftio/mm_swiftio_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1052=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/mm_swiftio/mmswiftio_sdram_ini_dcd.c b/boards/madmachine/mm_swiftio/mmswiftio_sdram_ini_dcd.c similarity index 100% rename from boards/arm/mm_swiftio/mmswiftio_sdram_ini_dcd.c rename to boards/madmachine/mm_swiftio/mmswiftio_sdram_ini_dcd.c diff --git a/boards/maker_diary/index.rst b/boards/maker_diary/index.rst new file mode 100644 index 00000000000..eee9613df01 --- /dev/null +++ b/boards/maker_diary/index.rst @@ -0,0 +1,10 @@ +.. _boards-maker-diary: + +Maker Diary +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/nrf52832_mdk/Kconfig b/boards/maker_diary/nrf52832_mdk/Kconfig similarity index 100% rename from boards/arm/nrf52832_mdk/Kconfig rename to boards/maker_diary/nrf52832_mdk/Kconfig diff --git a/boards/maker_diary/nrf52832_mdk/Kconfig.defconfig b/boards/maker_diary/nrf52832_mdk/Kconfig.defconfig new file mode 100644 index 00000000000..13d65f68be1 --- /dev/null +++ b/boards/maker_diary/nrf52832_mdk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52832-MDK board configuration + +# Copyright (c) 2018 makerdiary.com. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52832_MDK + +config BT_CTLR + default BT + +endif # BOARD_NRF52832_MDK diff --git a/boards/maker_diary/nrf52832_mdk/Kconfig.nrf52832_mdk b/boards/maker_diary/nrf52832_mdk/Kconfig.nrf52832_mdk new file mode 100644 index 00000000000..87fc85bda30 --- /dev/null +++ b/boards/maker_diary/nrf52832_mdk/Kconfig.nrf52832_mdk @@ -0,0 +1,7 @@ +# nRF52832-MDK board configuration + +# Copyright (c) 2018 makerdiary.com. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52832_MDK + select SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52832_mdk/board.cmake b/boards/maker_diary/nrf52832_mdk/board.cmake similarity index 100% rename from boards/arm/nrf52832_mdk/board.cmake rename to boards/maker_diary/nrf52832_mdk/board.cmake diff --git a/boards/maker_diary/nrf52832_mdk/board.yml b/boards/maker_diary/nrf52832_mdk/board.yml new file mode 100644 index 00000000000..70028809dc3 --- /dev/null +++ b/boards/maker_diary/nrf52832_mdk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52832_mdk + vendor: makerdiary + socs: + - name: nrf52832 diff --git a/boards/arm/nrf52832_mdk/doc/index.rst b/boards/maker_diary/nrf52832_mdk/doc/index.rst similarity index 100% rename from boards/arm/nrf52832_mdk/doc/index.rst rename to boards/maker_diary/nrf52832_mdk/doc/index.rst diff --git a/boards/arm/nrf52832_mdk/nrf52832_mdk-pinctrl.dtsi b/boards/maker_diary/nrf52832_mdk/nrf52832_mdk-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52832_mdk/nrf52832_mdk-pinctrl.dtsi rename to boards/maker_diary/nrf52832_mdk/nrf52832_mdk-pinctrl.dtsi diff --git a/boards/arm/nrf52832_mdk/nrf52832_mdk.dts b/boards/maker_diary/nrf52832_mdk/nrf52832_mdk.dts similarity index 100% rename from boards/arm/nrf52832_mdk/nrf52832_mdk.dts rename to boards/maker_diary/nrf52832_mdk/nrf52832_mdk.dts diff --git a/boards/arm/nrf52832_mdk/nrf52832_mdk.yaml b/boards/maker_diary/nrf52832_mdk/nrf52832_mdk.yaml similarity index 100% rename from boards/arm/nrf52832_mdk/nrf52832_mdk.yaml rename to boards/maker_diary/nrf52832_mdk/nrf52832_mdk.yaml diff --git a/boards/maker_diary/nrf52832_mdk/nrf52832_mdk_defconfig b/boards/maker_diary/nrf52832_mdk/nrf52832_mdk_defconfig new file mode 100644 index 00000000000..7167aca850a --- /dev/null +++ b/boards/maker_diary/nrf52832_mdk/nrf52832_mdk_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52833dk_nrf52833/pre_dt_board.cmake b/boards/maker_diary/nrf52832_mdk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52833dk_nrf52833/pre_dt_board.cmake rename to boards/maker_diary/nrf52832_mdk/pre_dt_board.cmake diff --git a/boards/arm/nrf52840_mdk/Kconfig b/boards/maker_diary/nrf52840_mdk/Kconfig similarity index 100% rename from boards/arm/nrf52840_mdk/Kconfig rename to boards/maker_diary/nrf52840_mdk/Kconfig diff --git a/boards/maker_diary/nrf52840_mdk/Kconfig.defconfig b/boards/maker_diary/nrf52840_mdk/Kconfig.defconfig new file mode 100644 index 00000000000..4ffd9e4ea08 --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52840-MDK board configuration + +# Copyright (c) 2018 makerdiary.com +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840_MDK + +config BT_CTLR + default BT + +endif # BOARD_NRF52840_MDK diff --git a/boards/maker_diary/nrf52840_mdk/Kconfig.nrf52840_mdk b/boards/maker_diary/nrf52840_mdk/Kconfig.nrf52840_mdk new file mode 100644 index 00000000000..a32c79ad741 --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk/Kconfig.nrf52840_mdk @@ -0,0 +1,7 @@ +# nRF52840-MDK board configuration + +# Copyright (c) 2018 makerdiary.com +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840_MDK + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_mdk/board.cmake b/boards/maker_diary/nrf52840_mdk/board.cmake similarity index 100% rename from boards/arm/nrf52840_mdk/board.cmake rename to boards/maker_diary/nrf52840_mdk/board.cmake diff --git a/boards/maker_diary/nrf52840_mdk/board.yml b/boards/maker_diary/nrf52840_mdk/board.yml new file mode 100644 index 00000000000..09e13811fc3 --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52840_mdk + vendor: makerdiary + socs: + - name: nrf52840 diff --git a/boards/arm/nrf52840_mdk/doc/index.rst b/boards/maker_diary/nrf52840_mdk/doc/index.rst similarity index 100% rename from boards/arm/nrf52840_mdk/doc/index.rst rename to boards/maker_diary/nrf52840_mdk/doc/index.rst diff --git a/boards/arm/nrf52840_mdk/nrf52840_mdk-pinctrl.dtsi b/boards/maker_diary/nrf52840_mdk/nrf52840_mdk-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840_mdk/nrf52840_mdk-pinctrl.dtsi rename to boards/maker_diary/nrf52840_mdk/nrf52840_mdk-pinctrl.dtsi diff --git a/boards/arm/nrf52840_mdk/nrf52840_mdk.dts b/boards/maker_diary/nrf52840_mdk/nrf52840_mdk.dts similarity index 100% rename from boards/arm/nrf52840_mdk/nrf52840_mdk.dts rename to boards/maker_diary/nrf52840_mdk/nrf52840_mdk.dts diff --git a/boards/arm/nrf52840_mdk/nrf52840_mdk.yaml b/boards/maker_diary/nrf52840_mdk/nrf52840_mdk.yaml similarity index 100% rename from boards/arm/nrf52840_mdk/nrf52840_mdk.yaml rename to boards/maker_diary/nrf52840_mdk/nrf52840_mdk.yaml diff --git a/boards/maker_diary/nrf52840_mdk/nrf52840_mdk_defconfig b/boards/maker_diary/nrf52840_mdk/nrf52840_mdk_defconfig new file mode 100644 index 00000000000..7167aca850a --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk/nrf52840_mdk_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52840_blip/pre_dt_board.cmake b/boards/maker_diary/nrf52840_mdk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840_blip/pre_dt_board.cmake rename to boards/maker_diary/nrf52840_mdk/pre_dt_board.cmake diff --git a/boards/arm/nrf52840_mdk_usb_dongle/Kconfig b/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/Kconfig rename to boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig diff --git a/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.defconfig b/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.defconfig new file mode 100644 index 00000000000..eb2cfed745d --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.defconfig @@ -0,0 +1,37 @@ +# nRF52840 MDK USB Dongle board configuration +# +# Copyright (c) 2018 Nordic Semiconductor ASA +# +# Copyright (c) 2022 Nikola Trifunovic +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840_MDK_USB_DONGLE + +# To let the nRF5 bootloader load an application, the application +# must be linked after Nordic MBR, that is factory-programmed on the board. + +# Nordic nRF5 bootloader exists outside of the partitions specified in the +# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application +# correctly, after Nordic MBR. + +# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION +# which will make it link into the correct partition specified in DTS file, +# so no override is necessary. + +config FLASH_LOAD_OFFSET + default 0x1000 + depends on BOARD_HAS_NRF5_BOOTLOADER && !USE_DT_CODE_PARTITION + +if USB_DEVICE_STACK + +# Enable UART driver, needed for CDC ACM +config SERIAL + default y + +endif # USB_DEVICE_STACK + +config BT_CTLR + default BT + +endif # BOARD_NRF52840_MDK_USB_DONGLE diff --git a/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.nrf52840_mdk_usb_dongle b/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.nrf52840_mdk_usb_dongle new file mode 100644 index 00000000000..7f71811f3f2 --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.nrf52840_mdk_usb_dongle @@ -0,0 +1,8 @@ +# nRF52840 MDK USB Dongle board configuration + +# Copyright (c) 2022 Nikola Trifunovic +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840_MDK_USB_DONGLE + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_mdk_usb_dongle/board.cmake b/boards/maker_diary/nrf52840_mdk_usb_dongle/board.cmake similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/board.cmake rename to boards/maker_diary/nrf52840_mdk_usb_dongle/board.cmake diff --git a/boards/maker_diary/nrf52840_mdk_usb_dongle/board.yml b/boards/maker_diary/nrf52840_mdk_usb_dongle/board.yml new file mode 100644 index 00000000000..1c3020c52b5 --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk_usb_dongle/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52840_mdk_usb_dongle + vendor: makerdiary + socs: + - name: nrf52840 diff --git a/boards/arm/nrf52840_mdk_usb_dongle/doc/index.rst b/boards/maker_diary/nrf52840_mdk_usb_dongle/doc/index.rst similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/doc/index.rst rename to boards/maker_diary/nrf52840_mdk_usb_dongle/doc/index.rst diff --git a/boards/arm/nrf52840_mdk_usb_dongle/doc/nrf52840-mdk-usb-dongle-pinout.jpg b/boards/maker_diary/nrf52840_mdk_usb_dongle/doc/nrf52840-mdk-usb-dongle-pinout.jpg similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/doc/nrf52840-mdk-usb-dongle-pinout.jpg rename to boards/maker_diary/nrf52840_mdk_usb_dongle/doc/nrf52840-mdk-usb-dongle-pinout.jpg diff --git a/boards/arm/nrf52840_mdk_usb_dongle/fstab-debugger.dtsi b/boards/maker_diary/nrf52840_mdk_usb_dongle/fstab-debugger.dtsi similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/fstab-debugger.dtsi rename to boards/maker_diary/nrf52840_mdk_usb_dongle/fstab-debugger.dtsi diff --git a/boards/arm/nrf52840_mdk_usb_dongle/fstab-stock.dtsi b/boards/maker_diary/nrf52840_mdk_usb_dongle/fstab-stock.dtsi similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/fstab-stock.dtsi rename to boards/maker_diary/nrf52840_mdk_usb_dongle/fstab-stock.dtsi diff --git a/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle-pinctrl.dtsi b/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle-pinctrl.dtsi rename to boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle-pinctrl.dtsi diff --git a/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts b/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts rename to boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts diff --git a/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml b/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml rename to boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml diff --git a/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig b/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig new file mode 100644 index 00000000000..86ff0f6c71f --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Console +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable GPIO +CONFIG_GPIO=y diff --git a/boards/arm/nrf52840_mdk/pre_dt_board.cmake b/boards/maker_diary/nrf52840_mdk_usb_dongle/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840_mdk/pre_dt_board.cmake rename to boards/maker_diary/nrf52840_mdk_usb_dongle/pre_dt_board.cmake diff --git a/boards/microchip/ev11l78a/Kconfig.defconfig b/boards/microchip/ev11l78a/Kconfig.defconfig new file mode 100644 index 00000000000..9fe8fda5d74 --- /dev/null +++ b/boards/microchip/ev11l78a/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if USBC_STACK + +# Kernel Options due to Low Memory (4k) +CONFIG_LOG_BUFFER_SIZE=256 +CONFIG_MAIN_STACK_SIZE=640 +CONFIG_IDLE_STACK_SIZE=200 +CONFIG_ISR_STACK_SIZE=512 +CONFIG_USBC_STACK_SIZE=512 +# Prevent Interrupt Vector Table in RAM +CONFIG_SRAM_VECTOR_TABLE=n + +# This board only supports the sink role, so +# no need to ever implement source for it. +CONFIG_USBC_CSM_SINK_ONLY=y + +endif # USBC_STACK diff --git a/boards/microchip/ev11l78a/Kconfig.ev11l78a b/boards/microchip/ev11l78a/Kconfig.ev11l78a new file mode 100644 index 00000000000..2e4080c0e17 --- /dev/null +++ b/boards/microchip/ev11l78a/Kconfig.ev11l78a @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Meta Platforms, Inc. and its affiliates. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EV11L78A + select SOC_SAMD20E16 diff --git a/boards/arm/ev11l78a/board.cmake b/boards/microchip/ev11l78a/board.cmake similarity index 100% rename from boards/arm/ev11l78a/board.cmake rename to boards/microchip/ev11l78a/board.cmake diff --git a/boards/microchip/ev11l78a/board.yml b/boards/microchip/ev11l78a/board.yml new file mode 100644 index 00000000000..abaabec67ab --- /dev/null +++ b/boards/microchip/ev11l78a/board.yml @@ -0,0 +1,5 @@ +board: + name: ev11l78a + vendor: microchip + socs: + - name: samd20e16 diff --git a/boards/arm/ev11l78a/doc/img/ev11l78a.jpg b/boards/microchip/ev11l78a/doc/img/ev11l78a.jpg similarity index 100% rename from boards/arm/ev11l78a/doc/img/ev11l78a.jpg rename to boards/microchip/ev11l78a/doc/img/ev11l78a.jpg diff --git a/boards/microchip/ev11l78a/doc/index.rst b/boards/microchip/ev11l78a/doc/index.rst new file mode 100644 index 00000000000..2197ede6331 --- /dev/null +++ b/boards/microchip/ev11l78a/doc/index.rst @@ -0,0 +1,105 @@ +.. _ev11l78a: + +UPD301C Basic Sink Application Example +###################################### + +Overview +******** + +The UPD301C Basic Sink Application Example Evaluation Kit (EV11L78A) +is a low-cost evaluation platform for Microchip's UPD301C Standalone +Programmable USB Power Delivery (PD) Controller. This RoHS-compliant +evaluation platform comes in a small form factor and adheres to the +USB Type-C™ Connector Specification and USB PD 3.0 specification. + +.. figure:: img/ev11l78a.jpg + :width: 500px + :align: center + :alt: EV11L78A + + UPD301C Basic Sink Application Example (Credit: `Microchip Technology`_) + +Hardware +******** + +- ATSAMD20E16 ARM Cortex-M0+ processor at 48 MHz +- UPD301C combines a SAMD20 core and a UPD350 USB-PD controller +- Sink PDO Selector Switch +- Onboard LED Voltmeter + +Supported Features +================== + +The ev11l78a board configuration supports the following hardware +features: + + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - ADC + - on-chip + - Analog to Digital Converter + * - GPIO + - on-chip + - I/O ports + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + +Other hardware features are not currently supported by Zephyr. + +Refer to the `EV11L78A Schematics`_ for a detailed hardware diagram. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/microchip/ev11l78a/ev11l78a_defconfig`. + +Serial Port +=========== + +The SAMD20 MCU has 6 SERCOM based USARTs. One of the USARTs +(SERCOM1) is available on the Debug/Status header. + +SPI Port +======== + +The SAMD20 MCU has 6 SERCOM based SPIs. One of the SPIs (SERCOM0) +is internally connected between the SAMD20 core and the UPD350. + +I²C Port +======== + +The SAMD20 MCU has 6 SERCOM based I2Cs. One of the I2Cs (SERCOM3) +is available on the Debug/Status header. + +References +********** + +.. target-notes:: + +.. _Microchip Technology: + https://www.microchip.com/en-us/development-tool/ev11l78a + +.. _EV11L78A Schematics: + https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/SupportingCollateral/03-00056-R1.0.PDF diff --git a/boards/arm/ev11l78a/ev11l78a-pinctrl.dtsi b/boards/microchip/ev11l78a/ev11l78a-pinctrl.dtsi similarity index 100% rename from boards/arm/ev11l78a/ev11l78a-pinctrl.dtsi rename to boards/microchip/ev11l78a/ev11l78a-pinctrl.dtsi diff --git a/boards/arm/ev11l78a/ev11l78a.dts b/boards/microchip/ev11l78a/ev11l78a.dts similarity index 100% rename from boards/arm/ev11l78a/ev11l78a.dts rename to boards/microchip/ev11l78a/ev11l78a.dts diff --git a/boards/arm/ev11l78a/ev11l78a.yaml b/boards/microchip/ev11l78a/ev11l78a.yaml similarity index 100% rename from boards/arm/ev11l78a/ev11l78a.yaml rename to boards/microchip/ev11l78a/ev11l78a.yaml diff --git a/boards/microchip/ev11l78a/ev11l78a_defconfig b/boards/microchip/ev11l78a/ev11l78a_defconfig new file mode 100644 index 00000000000..481d0cf5360 --- /dev/null +++ b/boards/microchip/ev11l78a/ev11l78a_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_OSC8M=y +CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/ev11l78a/pre_dt_board.cmake b/boards/microchip/ev11l78a/pre_dt_board.cmake similarity index 100% rename from boards/arm/ev11l78a/pre_dt_board.cmake rename to boards/microchip/ev11l78a/pre_dt_board.cmake diff --git a/boards/arm/ev11l78a/support/openocd.cfg b/boards/microchip/ev11l78a/support/openocd.cfg similarity index 100% rename from boards/arm/ev11l78a/support/openocd.cfg rename to boards/microchip/ev11l78a/support/openocd.cfg diff --git a/boards/microchip/index.rst b/boards/microchip/index.rst new file mode 100644 index 00000000000..1610cf6a7c2 --- /dev/null +++ b/boards/microchip/index.rst @@ -0,0 +1,10 @@ +.. _boards-microchip-technology-inc: + +Microchip Technology Inc. +######################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/microchip/m2gl025_miv/Kconfig.m2gl025_miv b/boards/microchip/m2gl025_miv/Kconfig.m2gl025_miv new file mode 100644 index 00000000000..62484218132 --- /dev/null +++ b/boards/microchip/m2gl025_miv/Kconfig.m2gl025_miv @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M2GL025_MIV + select SOC_MIV diff --git a/boards/riscv/m2gl025_miv/board.cmake b/boards/microchip/m2gl025_miv/board.cmake similarity index 100% rename from boards/riscv/m2gl025_miv/board.cmake rename to boards/microchip/m2gl025_miv/board.cmake diff --git a/boards/microchip/m2gl025_miv/board.yml b/boards/microchip/m2gl025_miv/board.yml new file mode 100644 index 00000000000..84e61821f35 --- /dev/null +++ b/boards/microchip/m2gl025_miv/board.yml @@ -0,0 +1,5 @@ +board: + name: m2gl025_miv + vendor: microchip + socs: + - name: miv diff --git a/boards/riscv/m2gl025_miv/doc/index.rst b/boards/microchip/m2gl025_miv/doc/index.rst similarity index 100% rename from boards/riscv/m2gl025_miv/doc/index.rst rename to boards/microchip/m2gl025_miv/doc/index.rst diff --git a/boards/riscv/m2gl025_miv/m2gl025_miv.dts b/boards/microchip/m2gl025_miv/m2gl025_miv.dts similarity index 100% rename from boards/riscv/m2gl025_miv/m2gl025_miv.dts rename to boards/microchip/m2gl025_miv/m2gl025_miv.dts diff --git a/boards/riscv/m2gl025_miv/m2gl025_miv.yaml b/boards/microchip/m2gl025_miv/m2gl025_miv.yaml similarity index 100% rename from boards/riscv/m2gl025_miv/m2gl025_miv.yaml rename to boards/microchip/m2gl025_miv/m2gl025_miv.yaml diff --git a/boards/riscv/m2gl025_miv/m2gl025_miv_defconfig b/boards/microchip/m2gl025_miv/m2gl025_miv_defconfig similarity index 75% rename from boards/riscv/m2gl025_miv/m2gl025_miv_defconfig rename to boards/microchip/m2gl025_miv/m2gl025_miv_defconfig index e33765680d5..a00960e8ca0 100644 --- a/boards/riscv/m2gl025_miv/m2gl025_miv_defconfig +++ b/boards/microchip/m2gl025_miv/m2gl025_miv_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_MIV=y -CONFIG_SOC_MIV=y -CONFIG_BOARD_M2GL025_MIV=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/m2gl025_miv/support/m2gl025_miv.repl b/boards/microchip/m2gl025_miv/support/m2gl025_miv.repl similarity index 100% rename from boards/riscv/m2gl025_miv/support/m2gl025_miv.repl rename to boards/microchip/m2gl025_miv/support/m2gl025_miv.repl diff --git a/boards/riscv/m2gl025_miv/support/m2gl025_miv.resc b/boards/microchip/m2gl025_miv/support/m2gl025_miv.resc similarity index 100% rename from boards/riscv/m2gl025_miv/support/m2gl025_miv.resc rename to boards/microchip/m2gl025_miv/support/m2gl025_miv.resc diff --git a/boards/arm/mec1501modular_assy6885/CMakeLists.txt b/boards/microchip/mec1501modular_assy6885/CMakeLists.txt similarity index 100% rename from boards/arm/mec1501modular_assy6885/CMakeLists.txt rename to boards/microchip/mec1501modular_assy6885/CMakeLists.txt diff --git a/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig b/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig new file mode 100644 index 00000000000..1f5c692b90f --- /dev/null +++ b/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig @@ -0,0 +1,46 @@ +# Copyright (c) 2019 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MEC1501MODULAR_ASSY6885 + +#PS/2 driver is compiled in terms of this flag. +config ESPI_PERIPHERAL_8042_KBC + default y + depends on ESPI_XEC + +if RTOS_TIMER + +# XEC RTOS timer HW frequency is fixed at 32768 +# The driver requires tickless mode and ticks per +# second to be 32768 for accurate operation. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +endif # RTOS_TIMER + +if !RTOS_TIMER + +# If RTOS timer is not enabled we use ARM Cortex-M +# SYSTICK. SYSTICK frequency is 48MHz divided by +# SOC_MEC1501_PROC_CLK_DIV. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 48000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +if ESPI + +config ESPI_PERIPHERAL_UART_SOC_MAPPING + default 1 + +endif # ESPI + +endif # RTOS_TIMER + +endif # BOARD_MEC1501MODULAR_ASSY6885 diff --git a/boards/microchip/mec1501modular_assy6885/Kconfig.mec1501modular_assy6885 b/boards/microchip/mec1501modular_assy6885/Kconfig.mec1501modular_assy6885 new file mode 100644 index 00000000000..721f2a0da96 --- /dev/null +++ b/boards/microchip/mec1501modular_assy6885/Kconfig.mec1501modular_assy6885 @@ -0,0 +1,5 @@ +# Copyright (c) 2019, Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC1501MODULAR_ASSY6885 + select SOC_MEC1501_HSZ diff --git a/boards/arm/mec1501modular_assy6885/board.cmake b/boards/microchip/mec1501modular_assy6885/board.cmake similarity index 100% rename from boards/arm/mec1501modular_assy6885/board.cmake rename to boards/microchip/mec1501modular_assy6885/board.cmake diff --git a/boards/microchip/mec1501modular_assy6885/board.yml b/boards/microchip/mec1501modular_assy6885/board.yml new file mode 100644 index 00000000000..d45ec4217f7 --- /dev/null +++ b/boards/microchip/mec1501modular_assy6885/board.yml @@ -0,0 +1,5 @@ +board: + name: mec1501modular_assy6885 + vendor: microchip + socs: + - name: mec1501_hsz diff --git a/boards/microchip/mec1501modular_assy6885/doc/index.rst b/boards/microchip/mec1501modular_assy6885/doc/index.rst new file mode 100644 index 00000000000..a74f48163fb --- /dev/null +++ b/boards/microchip/mec1501modular_assy6885/doc/index.rst @@ -0,0 +1,321 @@ +.. _mec1501modular_assy6885: + +Microchip MEC1501 Modular card ASSY6885 +####################################### + +Overview +******** + +The MEC1501 Modular card ASSY6885 is a development board to evaluate the Microchip +MEC152X series microcontrollers. This board can work standalone or be mated with +any platform that complies with MECC specification. + +.. image:: mec1501modular_assy6885.jpg + :align: center + :alt: MEC1501 Modular ASSY 6885 + +Hardware +******** + +- MEC1521HA0SZ ARM Cortex-M4 Processor +- 256 KB RAM and 64 KB boot ROM +- GPIO headers +- UART1 using microUSB +- PECI interface 3.0 +- 10 SMBUS instances +- FAN, PMW and TACHO pins +- VCI interface +- Independent Hardware Driven PS/2 Ports + +At difference from MEC15xx evaluation board, modular MEC1521 exposes the pins +in 2 different ways: + +1) Standalone mode via headers + + - GPIOs + - PWM5 + - JTAG/SWD, ETM and MCHP Trace ports + - eSPI bus + - SMB0 + +2) Mated mode with another platform that has a high density MECC connector. + + - FAN0, PWM0, SMB0, SMB1, SMB4 and SMB5 + - eSPI bus + - Breathing/Blinking LEDs + +The board is powered through the +5V USB Micro A connector or from the MECC connector. + + +For more information about the SOC please see the `MEC152x Reference Manual`_ + +Supported Features +================== + +The mec1501modular_assy6885 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| ESPI | on-chip | espi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| RTOS | on-chip | timer | ++-----------+------------+-------------------------------------+ +| TIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| PS2 | on-chip | ps2 | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in the +:zephyr_file:`boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig` +Kconfig file. + +Connections and IOs +=================== + +This evaluation board kit is comprised of the following HW blocks: + +- MEC1501 Modular Card ASSY 6885 Rev A0 `MEC1501 Modular EC Card - Assy_6885 Rev A0p1`_ + +System Clock +============ + +The MEC1501 MCU is configured to use the 48Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock +control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in +the references at the end of this document. + +Serial Port +=========== +UART1 is configured for serial logs. + +Jumper settings +*************** + +Please follow the jumper settings below to properly demo this +board. Advanced users may deviate from this recommendation. + +Jumper setting for MEC1501 Modular Assy 6885 Rev A1p0 +===================================================== + +Power-related jumpers +--------------------- + +If you wish to power from type A/B connector ``P10`` set the jumper ``JP35 1-2``. + +If you wish to power through MECC connector ``P1`` and mate to external platform, +set the jumper to ``JP35 3-4``. + +.. note:: A single jumper is required in JP35. + ++------+---------+---------+------+------+------+----------+ +| JP30 | JP31 | JP32 | JP33 | JP34 | JP40 | JP21 | +| VTR3 | VTR_PLL | VTR_REG | VTR1 | VTR2 | 3.3V | VREF_ADC | ++======+=========+=========+======+======+======+==========+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++------+---------+---------+------+------+------+----------+ + + ++------+------------+------+----------+ +| JP6 | JP36 | JP27 | JP4 | +| VBAT | VTR_ANALOG | PECI | VREF_VTT | ++======+============+======+==========+ +| 2-3 | 1-2 | 2-3 | open | ++------+------------+------+----------+ + +These jumpers configure nRESETI and JTAG_STRAP respectively. + ++-----------+---------------+ +| JP22 | JP29 | +| (nRESETI) | (JTAG_STRAP) | ++===========+===============+ +| 11-12 | 1-2 | ++-----------+---------------+ + +Boot-ROM Straps +--------------- + +These jumpers configure MEC1501 Boot-ROM straps. + ++-------------+------------+--------------+-------------+ +| JP37 | J6 | JP41 | JP23 | +| (CMP_STRAP) | (CR_STRAP) | (VTR2_STRAP) | (BSS_STRAP) | ++=============+============+==============+=============+ +| 1-2 | 1-2 | 1-2 | 3-4 | ++-------------+------------+--------------+-------------+ + + +``JP23 3-4`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples +SHD SPI CS0# and if high, it loads code from SHD SPI. +This is the recommended setup. + ++-------------+------------+----------------------------+ +| CR_STRAP | BSS_STRAP | SOURCE | ++-------------+------------+----------------------------+ +| 0 | X | Use 3.3V Private SPI | ++-------------+------------+----------------------------+ +| 1 | 0 | Use eSPI Flash channel | ++-------------+------------+----------------------------+ +| | 1 | Use 3.3V Shared channel(R)| ++-------------+------------+----------------------------+ + +Power management +---------------- +``JP20 2-3`` is required so all GPIOs powered by VTR3 rail worked at 1.8V. + +.. note:: External 1.8V needs to be connected to JP13.1 + ++-------------------+-----------------+ +| JP20 | JP13 | +| (VTR3 selection) | (1.8V source) | ++===================+=================+ +| 2-3 | 1.8V to pin 1 | ++-------------------+-----------------+ + + +Jumper location map +------------------- + +.. code-block:: none + + +--------------------------------------------------------------------------------------+ + | |------------| +----------+ J10 || | + | [BT1] + +------------+ J50 ++ ++ || | + | | JP38 JP43 ++ || || | + | + + + +-+ JP4 + + JP26 || || | + | JP6 + + + + + + + + || || | + | JP31 ++ JP32 JP36 +-+ JP27 + + + + J6 || | + | JP18 JP37 JP41 JP42 ++ | + | ++ + + +--------+ J48 | + | || JP21 + + +--------+ JP22 +----------+ | + | J2 || + JP34 JP30 J11 ++ | + | ++ + J44 || | + | ++ +----------------+ || | + | +---------------+ || + JP24 |----------------| ++ | + | |---------------| ++ + +----------+ +----------------+ J47 | + | JP20 +---------------+ JP23 JP40 +----------+ ++ | + | + ++ JP29 || | + | + + +----------+ + || | + | J52+---------------+ + + +----------+ J5 +-------------+ ++ | + | J45+---------------+ JP33 TP57 JP25 +-------------+ J4 J49 | + | | + | ++ TP4 +----------+ ++ | + | ++ + + + + + + TP61 +----------+ ++ | + | JP28 + + + + + TP65 + TP60 J51 JP35 | + | TP58 JP16 JP11 JP13 JP15 JP10 | + | TP5 | + | TP6 TP1 | + +--------------------------------------------------------------------------------------+ + + +Programming and Debugging +************************* + +Setup +===== + +#. Clone the `MEC152x SPI Image Gen`_ repository or download the files within + that directory. For the pre-production MEC150x use the `MEC150x SPI Image Gen`_ + repository. + +#. Make the image generation available for Zephyr, by making the tool + searchable by path, or by setting an environment variable + ``EVERGLADES_SPI_GEN``, for example: + + .. code-block:: console + + export EVERGLADES_SPI_GEN=/everglades_spi_gen_RomE + + Note that the tools for Linux and Windows have different file names. + For the pre-production MEC1501 SOC use everglades_spi_gen_lin64. + +#. If needed, a custom SPI image configuration file can be specified + to override the default one. + + .. code-block:: console + + export EVERGLADES_SPI_CFG=custom_spi_cfg.txt + + +Building +========== +#. Build :ref:`hello_world` application as you would normally do. + +#. Once you have ``zephyr.bin``, use the `MEC152x SPI Image Gen`_ microchip tool + to create the final binary. You need the output from this tool to flash + in the SHD SPI memory. + +Flashing +======== + +#. Connect Dediprog into header ``J2``. + +#. Flash the SPI NOR ``U3`` at offset 0x0 using Dediprog SF100 + or a similar tool for flashing SPI chips. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the MEC1501MODULAR_ASSY6885 board to your host computer using the + UART1 port and apply power. + + You should see ``"Hello World! mec1501modular_assy6885"`` in your terminal. + +Debugging +========= +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG only sessions. + +HW Issues +========= +In case you don't see your application running, please make sure ``LED1`` is lit. +If is off, then check the power related jumpers again. + +References +********** +.. target-notes:: + +.. _MEC152x Preliminary Data Sheet: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf +.. _MEC152x Reference Manual: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf +.. _MEC1501 Modular EC Card - Assy_6885 Rev A0p1: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501%20Modular%20EC%20Card%20-%20Assy_6885%20Rev%20A0p1%20-%20SCH.pdf +.. _MEC152x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC152x/SPI_image_gen +.. _MEC150x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC1501/SPI_image_gen diff --git a/boards/arm/mec1501modular_assy6885/doc/mec1501modular_assy6885.jpg b/boards/microchip/mec1501modular_assy6885/doc/mec1501modular_assy6885.jpg similarity index 100% rename from boards/arm/mec1501modular_assy6885/doc/mec1501modular_assy6885.jpg rename to boards/microchip/mec1501modular_assy6885/doc/mec1501modular_assy6885.jpg diff --git a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi similarity index 100% rename from boards/arm/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi rename to boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi diff --git a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts similarity index 100% rename from boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts rename to boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts diff --git a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.yaml b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml similarity index 100% rename from boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.yaml rename to boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml diff --git a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885_defconfig b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig similarity index 80% rename from boards/arm/mec1501modular_assy6885/mec1501modular_assy6885_defconfig rename to boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig index 7ab9a08fba2..1f9a9f937c5 100644 --- a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885_defconfig +++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig @@ -4,12 +4,9 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MEC1501_HSZ=y -CONFIG_SOC_SERIES_MEC1501X=y # Make sure external power management setup is as indicated in documentation CONFIG_SOC_MEC1501_VTR3_1_8V=y CONFIG_SOC_MEC1501_VCI_PINS_AS_GPIOS=n -CONFIG_BOARD_MEC1501MODULAR_ASSY6885=y CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/mec1501modular_assy6885/support/spi_cfg.txt b/boards/microchip/mec1501modular_assy6885/support/spi_cfg.txt similarity index 100% rename from boards/arm/mec1501modular_assy6885/support/spi_cfg.txt rename to boards/microchip/mec1501modular_assy6885/support/spi_cfg.txt diff --git a/boards/arm/mec15xxevb_assy6853/CMakeLists.txt b/boards/microchip/mec15xxevb_assy6853/CMakeLists.txt similarity index 100% rename from boards/arm/mec15xxevb_assy6853/CMakeLists.txt rename to boards/microchip/mec15xxevb_assy6853/CMakeLists.txt diff --git a/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig b/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig new file mode 100644 index 00000000000..c4dae2ad32e --- /dev/null +++ b/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig @@ -0,0 +1,39 @@ +# Copyright (c) 2019 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MEC15XXEVB_ASSY6853 + +config ESPI_XEC + default y + depends on ESPI + +if RTOS_TIMER + +# XEC RTOS timer HW frequency is fixed at 32768 +# The driver requires tickless mode and ticks per +# second to be 32768 for accurate operation. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +endif # RTOS_TIMER + +if !RTOS_TIMER + +# If RTOS timer is not enabled we use ARM Cortex-M +# SYSTICK. SYSTICK frequency is 48MHz divided by +# SOC_MEC1501_PROC_CLK_DIV. +# + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 48000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +endif # RTOS_TIMER + +endif # BOARD_MEC15XXEVB_ASSY6853 diff --git a/boards/microchip/mec15xxevb_assy6853/Kconfig.mec15xxevb_assy6853 b/boards/microchip/mec15xxevb_assy6853/Kconfig.mec15xxevb_assy6853 new file mode 100644 index 00000000000..b5397e26932 --- /dev/null +++ b/boards/microchip/mec15xxevb_assy6853/Kconfig.mec15xxevb_assy6853 @@ -0,0 +1,5 @@ +# Copyright (c) 2019, Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC15XXEVB_ASSY6853 + select SOC_MEC1501_HSZ diff --git a/boards/arm/mec15xxevb_assy6853/board.cmake b/boards/microchip/mec15xxevb_assy6853/board.cmake similarity index 100% rename from boards/arm/mec15xxevb_assy6853/board.cmake rename to boards/microchip/mec15xxevb_assy6853/board.cmake diff --git a/boards/arm/mec15xxevb_assy6853/board.h b/boards/microchip/mec15xxevb_assy6853/board.h similarity index 100% rename from boards/arm/mec15xxevb_assy6853/board.h rename to boards/microchip/mec15xxevb_assy6853/board.h diff --git a/boards/microchip/mec15xxevb_assy6853/board.yml b/boards/microchip/mec15xxevb_assy6853/board.yml new file mode 100644 index 00000000000..ae558489438 --- /dev/null +++ b/boards/microchip/mec15xxevb_assy6853/board.yml @@ -0,0 +1,5 @@ +board: + name: mec15xxevb_assy6853 + vendor: microchip + socs: + - name: mec1501_hsz diff --git a/boards/arm/mec15xxevb_assy6853/doc/dediprog_connector_2.jpg b/boards/microchip/mec15xxevb_assy6853/doc/dediprog_connector_2.jpg similarity index 100% rename from boards/arm/mec15xxevb_assy6853/doc/dediprog_connector_2.jpg rename to boards/microchip/mec15xxevb_assy6853/doc/dediprog_connector_2.jpg diff --git a/boards/microchip/mec15xxevb_assy6853/doc/index.rst b/boards/microchip/mec15xxevb_assy6853/doc/index.rst new file mode 100644 index 00000000000..e3b29e99212 --- /dev/null +++ b/boards/microchip/mec15xxevb_assy6853/doc/index.rst @@ -0,0 +1,467 @@ +.. _mec15xxevb_assy6853: + +Microchip MEC15xxEVB ASSY6853 +############################# + +Overview +******** + +The MEC15xxEVB_ASSY6853 kit is a future development platform to evaluate the +Microchip MEC15XX series microcontrollers. This board needs to be mated with +part number MEC1501 144WFBA SOLDER DC ASSY 6860(cpu board) in order to operate. +The MEC152x has superseded the MEC1501 in production. MEC152x is identical to +MEC150x except for an enhanced Boot-ROM SPI loader. The SPI image format has +been updated requiring a new SPI image tool. MEC1501 and MEC152x SPI image +formats are not compatible with each other. Evaluation and cpu boards are +compatible. + +.. image:: mec15xxevb_assy6853.jpg + :align: center + :alt: MEC15XX EVB ASSY 6853 + +Hardware +******** + +- MEC1521HA0SZ ARM Cortex-M4 Processor +- 256 KB RAM and 64 KB boot ROM +- Keyboard interface +- ADC & GPIO headers +- UART0, UART1, and UART2 +- FAN0, FAN1, FAN2 headers +- FAN PWM interface +- JTAG/SWD, ETM and MCHP Trace ports +- PECI interface 3.0 +- I2C voltage translator +- 10 SMBUS headers +- 4 SGPIO headers +- VCI interface +- 5 independent Hardware Driven PS/2 Ports +- eSPI header +- 3 Breathing/Blinking LEDs +- 2 Sockets for SPI NOR chips +- One reset and VCC_PWRDGD pushbuttons +- One external PCA9555 I/O port with jumper selectable I2C address. +- One external LTC2489 delta-sigma ADC with jumper selectable I2C address. +- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector. + +For more information about the SOC's please see `MEC152x Reference Manual`_ + +Supported Features +================== + +The mec15xxevb_assy6853 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PS/2 | on-chip | ps2 | ++-----------+------------+-------------------------------------+ +| KSCAN | on-chip | kscan | ++-----------+------------+-------------------------------------+ +| TACH | on-chip | tachometer | ++-----------+------------+-------------------------------------+ + + + + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in the +:zephyr_file:`boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig` Kconfig file. + +Connections and IOs +=================== + +This evaluation board kit is comprised of the following HW blocks: + +- MEC15xx EVB ASSY 6853 Rev A `MEC15xx EVB Schematic`_ +- MEC1501 144WFBA SOLDER DC ASSY 6883 with MEC152x silicon `MEC1501 Daughter Card Schematic`_ +- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_ + +System Clock +============ + +The MEC1521 MCU is configured to use the 48Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock +control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in +the references at the end of this document. + +Serial Port +=========== + +UART2 is configured for serial logs. + +Jumper settings +*************** + +Please follow the jumper settings below to properly demo this +board. Advanced users may deviate from this recommendation. + +Jumper setting for MEC15xx EVB Assy 6853 Rev A1p0 +================================================= + +Power-related jumpers +--------------------- + +If you wish to power from +5V power brick, then connect to barrel connector ``P11`` +(5.5mm OD, 2.1mm ID) and move the jumper to ``JP88 5-6``. + +If you wish to power from micro-USB type A/B connector ``P12``, move the +jumper to ``JP88 7-8``. + + +.. note:: A single jumper is required in JP88. + ++-------+------+------+------+------+------+------+------+------+------+------+ +| JP22 | JP32 | JP33 | JP37 | JP43 | JP47 | JP54 | JP56 | JP58 | JP64 | JP65 | ++=======+======+======+======+======+======+======+======+======+======+======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++-------+------+------+------+------+------+------+------+------+------+------+ + ++------+------+------+------+------+------+------+------+------+------+ +| JP72 | JP73 | JP76 | JP79 | JP80 | JP81 | JP82 | JP84 | JP87 | JP89 | ++======+======+======+======+======+======+======+======+======+======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++------+------+------+------+------+------+------+------+------+------+ + ++------+------+-------+-------+-------+ +| JP90 | JP91 | JP100 | JP101 | JP118 | ++======+======+=======+=======+=======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 2-3 | ++------+------+-------+-------+-------+ + +These jumpers configure VCC Power good, nRESETI and JTAG_STRAP respectively. + ++------------------+-----------+--------------+ +| JP5 | JP4 | JP45 | +| (VCC Power good) | (nRESETI) | (JTAG_STRAP) | ++==================+===========+==============+ +| 1-2 | 1-2 | 2-3 | ++------------------+-----------+--------------+ + +Boot-ROM Straps. +---------------- + +These jumpers configure MEC1501 Boot-ROM straps. + ++-------------+------------+--------------+-------------+ +| JP93 | JP11 | JP46 | JP96 | +| (CMP_STRAP) | (CR_STRAP) | (VTR2_STRAP) | (BSS_STRAP) | ++=============+============+==============+=============+ +| 2-3 | 1-2 | 2-3 | 1-2 | ++-------------+------------+--------------+-------------+ + +``JP96 1-2`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples +SHD SPI CS0# and if high, it loads code from SHD SPI. + +Peripheral Routing Jumpers +-------------------------- + +Each column of the following table illustrates how to enable UART2, SWD, +PVT SPI, SHD SPI and LED0-2 respectively. + ++----------+----------+--------+-----------+----------+---------+ +| JP48 | JP9 | JP9 | JP38 | JP98 | JP41 | +| (UART2) | (UART2) | (SWD) | (PVT SPI) | (SHD SPI)| (LED0-2)| ++==========+==========+========+===========+==========+=========+ +| 1-2 | | 2-3 | 2-3 | 2-3 | 1-2 | ++----------+----------+--------+-----------+----------+---------+ +| 4-5 | 4-5 | | 5-6 | 5-6 | 3-4 | ++----------+----------+--------+-----------+----------+---------+ +| 7-8 | | 8-9 | 8-9 | 8-9 | 5-6 | ++----------+----------+--------+-----------+----------+---------+ +| 10-11 | 10-11 | | 11-12 | 11-12 | | ++----------+----------+--------+-----------+----------+---------+ +| | | | 14-15 | 14-15 | | ++----------+----------+--------+-----------+----------+---------+ +| | | | 17-18 | 20-21 | | ++----------+----------+--------+-----------+----------+---------+ + +.. note:: For UART2 make sure JP39 have jumpers connected 1-2, 3-4. + +To receive UART2 serial output, please refer to the picture below +to make sure that JP9 configured for UART2 output. + +.. image:: mec15xxevb_assy6853_jp9_1.jpg + :align: center + :alt: JP9 header Assy6853 + +Jumper settings for MEC1501 144WFBGA Socket DC Assy 6883 Rev B1p0 +================================================================= + +The jumper configuration explained above covers the base board. The ASSY +6883 MEC1501 CPU board provides capability for an optional, external 32KHz +clock source. The card includes a 32KHz crystal oscillator. The card can +also be configured to use an external 50% duty cycle 32KHz source on the +XTAL2/32KHZ_IN pin. Note, firmware must set the MEC15xx clock enable +register to select the external source matching the jumper settings. If +using the MEC15xx internal silicon oscillator then the 32K jumper settings +are don't cares. ``JP1`` is for scoping test clock outputs. Please refer to +the schematic in reference section below. + +Parallel 32KHz crystal configuration +------------------------------------ ++-------+-------+ +| JP2 | JP3 | ++=======+=======+ +| 1-2 | 2-3 | ++-------+-------+ + +External 32KHz 50% duty cycle configuration +------------------------------------------- ++-------+-------+ +| JP2 | JP3 | ++=======+=======+ +| NC | 1-2 | ++-------+-------+ + + +Jumper settings for MEC1503 144WFBGA Socket DC Assy 6856 Rev B1p0 +================================================================= + +The MEC1503 ASSY 6856 CPU card does not include an onboard external +32K crystal or oscillator. The one jumper block ``JP1`` is for scoping +test clock outputs not for configuration. Please refer to schematic +in reference section below. + +Programming and Debugging +************************* + +Setup +===== +#. If you use Dediprog SF100 programmer, then setup it. + + Windows version can be found at the `SF100 Product page`_. + + Linux version source code can be found at `SF100 Linux GitHub`_. + Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer. + For Linux please make sure that you copied ``60-dediprog.rules`` + from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d) + then restart service using: + + .. code-block:: console + + $ udevadm control --reload + + Add directory with program ``dpcmd`` (on Linux) + or ``dpcmd.exe`` (on Windows) to your ``PATH``. + +#. Clone the `MEC152x SPI Image Gen`_ repository or download the files within + that directory. For the pre-production MEC150x use `MEC150x SPI Image Gen`_ + repository. + +#. Make the image generation available for Zephyr, by making the tool + searchable by path, or by setting an environment variable + ``EVERGLADES_SPI_GEN``, for example: + + .. code-block:: console + + export EVERGLADES_SPI_GEN=/everglades_spi_gen_RomE + + Note that the tools for Linux and Windows have different file names. + For the pre-production MEC1501 SOC use everglades_spi_gen_lin64. + +#. If needed, a custom SPI image configuration file can be specified + to override the default one. + + .. code-block:: console + + export EVERGLADES_SPI_CFG=custom_spi_cfg.txt + +Wiring +======== +#. Connect the SPI Dongle ASSY 6791 to ``J44`` in the EVB. + + .. image:: spidongle_assy6791_view1.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + +#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip ``U3`` + Make sure that your programmer's offset is 0x0. + For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips. + + .. list-table:: Microchip board wiring + :align: center + + * - + .. image:: spidongle_assy6791.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 + + - + .. image:: spidongle_assy6791_view2.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 view 2 + + | + + .. image:: dediprog_connector_2.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + + + .. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers! + Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board. + Wiring connection is described in the table below. + + +------------+---------------+ + | Dediprog | Assy6791 | + | Connector | J6 Connector | + +============+===============+ + | VCC | 1 | + +------------+---------------+ + | GND | 2 | + +------------+---------------+ + | CS | 3 | + +------------+---------------+ + | CLK | 4 | + +------------+---------------+ + | MISO | 6 | + +------------+---------------+ + | MOSI | 5 | + +------------+---------------+ + +#. Connect UART2 port of the MEC15xxEVB_ASSY_6853 board + to your host computer using the RS232 cable. + +#. Apply power to the board via a micro-USB cable. + Configure this option by using a jumper between ``JP88 7-8``. + + .. image:: jp88_power_options.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + +#. Final wiring for the board should look like this: + + .. image:: mec_board_setup.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + +Building +======== +#. Build :ref:`hello_world` application as you would normally do. + +#. The file :file:`spi_image.bin` will be created if the build system + can find the image generation tool. This binary image can be used + to flash the SPI chip. + +Flashing +======== +#. Run your favorite terminal program to listen for output. + Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. + + For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Flash your board using ``west`` from the second terminal window. + Split first and second terminal windows to view both of them. + + .. code-block:: console + + $ west flash + + .. note:: When west process started press Reset button and do not release it + till the whole west process will not be finished successfully. + + .. image:: reset_button_1.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + + + .. note:: If you don't want to press Reset button every time, you can disconnect + SPI Dongle ASSY 6791 from the EVB during the west flash programming. + Then connect it back to the ``J44`` header and apply power to the EVB. + Result will be the same. + + +#. You should see ``"Hello World! mec15xxevb_assy6853"`` in the first terminal window. + If you don't see this message, press the Reset button and the message should appear. + +Debugging +========= +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG only sessions. + +Troubleshooting +=============== +#. In case you don't see your application running, please make sure ``LED7``, ``LED8``, and ``LED1`` + are lit. If one of these is off, then check the power-related jumpers again. + +#. If you can't program the board using Dediprog, disconnect the Assy6791 + from the main board Assy6853 and try again. + +#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again. + +Notes +===== +#. To enable PCA9555PW and test the I2C on mec15xxevb_assy6853, additional works are needed: + + As the I2C slave device NXP pca95xx on mec15xxevb_assy6853 is connected to I2C00 port, + however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log, + so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use + I2C01 port by making some jumpers setting as below: + + * JP99 1-2 Connected Connect I2C01_SDA from CPU to header J5 + * JP99 13-14 Connected Connect I2C01_SCL from CPU to header J5 + * JP25 21-22 Connected External pull-up for I2C01_SDA + * JP25 23-24 Connected External pull-up for I2C01_SCL + * + * JP44.1 J5.1 Connected Connect NXP PCA95xx to I2C01 + * JP44.3 J5.3 Connected Connect NXP PCA95xx to I2C01 + + +References +********** +.. target-notes:: + +.. _MEC1501 Preliminary Data Sheet: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501_Datasheet.pdf +.. _MEC1501 Reference Manual: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501_Datasheet.pdf +.. _MEC152x Preliminary Data Sheet: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf +.. _MEC152x Reference Manual: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf +.. _MEC15xx EVB Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/Everglades%20EVB%20-%20Assy_6853%20Rev%20A1p1%20-%20SCH.pdf +.. _MEC1501 Daughter Card Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501%20Socket%20DC%20for%20EVERGLADES%20EVB%20-%20Assy_6883%20Rev%20A0p1%20-%20SCH.pdf +.. _MEC1503 Daughter Card Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1503%20Socket%20DC%20for%20EVERGLADES%20EVB%20-%20Assy_6856%20Rev%20A1p0%20-%20SCH.pdf +.. _SPI Dongle Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/SPI%20Dongles%20and%20Aardvark%20Interposer%20Assy%206791%20Rev%20A1p1%20-%20SCH.pdf +.. _MEC152x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC152x/SPI_image_gen +.. _MEC150x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC1501/SPI_image_gen +.. _SF100 Linux GitHub: + https://github.com/DediProgSW/SF100Linux +.. _SF100 Product page: + https://www.dediprog.com/product/SF100 +.. _SF100 Linux manual: + https://www.dediprog.com/download/save/727.pdf diff --git a/boards/arm/mec15xxevb_assy6853/doc/jp88_power_options.jpg b/boards/microchip/mec15xxevb_assy6853/doc/jp88_power_options.jpg similarity index 100% rename from boards/arm/mec15xxevb_assy6853/doc/jp88_power_options.jpg rename to boards/microchip/mec15xxevb_assy6853/doc/jp88_power_options.jpg diff --git a/boards/arm/mec15xxevb_assy6853/doc/mec15xxevb_assy6853.jpg b/boards/microchip/mec15xxevb_assy6853/doc/mec15xxevb_assy6853.jpg similarity index 100% rename from boards/arm/mec15xxevb_assy6853/doc/mec15xxevb_assy6853.jpg rename to boards/microchip/mec15xxevb_assy6853/doc/mec15xxevb_assy6853.jpg diff --git a/boards/arm/mec15xxevb_assy6853/doc/mec15xxevb_assy6853_jp9_1.jpg b/boards/microchip/mec15xxevb_assy6853/doc/mec15xxevb_assy6853_jp9_1.jpg similarity index 100% rename from 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100644 --- a/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig +++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig @@ -4,10 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MEC1501_HSZ=y -CONFIG_SOC_SERIES_MEC1501X=y CONFIG_SOC_MEC1501_VTR3_1_8V=y -CONFIG_BOARD_MEC15XXEVB_ASSY6853=y CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/mec15xxevb_assy6853/support/spi_cfg.txt b/boards/microchip/mec15xxevb_assy6853/support/spi_cfg.txt similarity index 100% rename from boards/arm/mec15xxevb_assy6853/support/spi_cfg.txt rename to boards/microchip/mec15xxevb_assy6853/support/spi_cfg.txt diff --git a/boards/arm/mec172xevb_assy6906/CMakeLists.txt b/boards/microchip/mec172xevb_assy6906/CMakeLists.txt similarity index 100% rename from boards/arm/mec172xevb_assy6906/CMakeLists.txt rename to boards/microchip/mec172xevb_assy6906/CMakeLists.txt diff --git a/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig b/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig new file mode 100644 index 00000000000..c31952ed766 --- /dev/null +++ b/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Copyright (c) 2021 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MEC172XEVB_ASSY6906 + +if RTOS_TIMER + +# XEC RTOS timer HW frequency is fixed at 32768 Hz. +# The driver requires tickless mode and ticks per second to be 32768 for +# accurate operation. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +endif # RTOS_TIMER + +if !RTOS_TIMER + +# If RTOS timer is not enabled we use ARM Cortex-M +# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR +# processor clock divider register. We assume PCR processor clock divider +# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV +# + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 96000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +endif # RTOS_TIMER + +endif # BOARD_MEC172XEVB_ASSY6906 diff --git a/boards/microchip/mec172xevb_assy6906/Kconfig.mec172xevb_assy6906 b/boards/microchip/mec172xevb_assy6906/Kconfig.mec172xevb_assy6906 new file mode 100644 index 00000000000..d11b6386811 --- /dev/null +++ b/boards/microchip/mec172xevb_assy6906/Kconfig.mec172xevb_assy6906 @@ -0,0 +1,5 @@ +# Copyright (c) 2021, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC172XEVB_ASSY6906 + select SOC_MEC172X_NSZ diff --git a/boards/arm/mec172xevb_assy6906/board.cmake b/boards/microchip/mec172xevb_assy6906/board.cmake similarity index 100% rename from boards/arm/mec172xevb_assy6906/board.cmake rename to boards/microchip/mec172xevb_assy6906/board.cmake diff --git a/boards/microchip/mec172xevb_assy6906/board.yml b/boards/microchip/mec172xevb_assy6906/board.yml new file mode 100644 index 00000000000..5f3f57b29a7 --- /dev/null +++ b/boards/microchip/mec172xevb_assy6906/board.yml @@ -0,0 +1,5 @@ +board: + name: mec172xevb_assy6906 + vendor: microchip + socs: + - name: mec172x_nsz diff --git a/boards/arm/mec172xevb_assy6906/doc/Reset_Button.jpg b/boards/microchip/mec172xevb_assy6906/doc/Reset_Button.jpg similarity index 100% rename from boards/arm/mec172xevb_assy6906/doc/Reset_Button.jpg rename to boards/microchip/mec172xevb_assy6906/doc/Reset_Button.jpg diff --git a/boards/arm/mec172xevb_assy6906/doc/dediprog_connector.jpg b/boards/microchip/mec172xevb_assy6906/doc/dediprog_connector.jpg similarity index 100% rename from boards/arm/mec172xevb_assy6906/doc/dediprog_connector.jpg rename to boards/microchip/mec172xevb_assy6906/doc/dediprog_connector.jpg diff --git a/boards/microchip/mec172xevb_assy6906/doc/index.rst b/boards/microchip/mec172xevb_assy6906/doc/index.rst new file mode 100644 index 00000000000..a2100e5a2d6 --- /dev/null +++ b/boards/microchip/mec172xevb_assy6906/doc/index.rst @@ -0,0 +1,479 @@ +.. _mec172xevb_assy6906: + +Microchip MEC172xEVB ASSY6906 +############################# + +Overview +******** + +The MEC172xEVB_ASSY6906 kit is a future development platform to evaluate the +Microchip MEC172X series microcontrollers. This board needs to be mated with +part number MEC172x 144WFBGA SOLDER DC ASSY 6914 (cpu board) in order to operate. +MEC172x and MEC152x SPI image formats are not compatible with each other. + +.. image:: mec172xevb_assy6906.jpg + :align: center + :alt: MEC172X EVB ASSY 6906 + +Hardware +******** + +- MEC172x ARM Cortex-M4 Processor +- 416 KB RAM and 128 KB boot ROM +- Keyboard interface +- ADC & GPIO headers +- UART0 and UART1 +- FAN0, FAN1, FAN2 headers +- FAN PWM interface +- JTAG/SWD, ETM and MCHP Trace ports +- PECI interface 3.0 +- I2C voltage translator +- 10 SMBUS headers +- VCI interface +- 1 Hardware Driven PS/2 Port +- eSPI header +- 2 Sockets for SPI NOR chips +- One reset and VCC_PWRDGD pushbuttons +- One external PCA9555 I/O port with jumper selectable I2C address. +- One external LTC2489 delta-sigma ADC with jumper selectable I2C address. +- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector. + +For more information about the SOC's please see `MEC172x Reference Manual`_ + +Supported Features +================== + +The mec172xevb_assy6906 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PS/2 | on-chip | ps2 | ++-----------+------------+-------------------------------------+ +| KSCAN | on-chip | kscan | ++-----------+------------+-------------------------------------+ +| TACH | on-chip | tachometer | ++-----------+------------+-------------------------------------+ +| RPMFAN | on-chip | Fan speed controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the +:zephyr_file:`boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig` Kconfig file. + +Connections and IOs +=================== + +This evaluation board kit is comprised of the following HW blocks: + +- MEC172x EVB ASSY 6906 Rev A `MEC172x EVB Schematic`_ +- MEC172x 144WFBGA SOLDER DC ASSY 6914 with MEC172x silicon `MEC172x Daughter Card Schematic`_ +- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_ + +System Clock +============ + +The MEC1723 MCU is configured to use the 96Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock +control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in +the references at the end of this document. + +Serial Port +=========== + +UART1 is configured for serial logs. + +Jumper settings +*************** + +Please follow the jumper settings below to properly demo this +board. Advanced users may deviate from this recommendation. + +Jumper setting for MEC172x EVB Assy 6906 Rev A1p0 +================================================= + +Power-related jumpers +--------------------- + +If you wish to power from +5V power brick, then connect to barrel connector ``P1`` +(5.5mm OD, 2.1mm ID) and move the jumper to ``JP30 5-6``. + +If you wish to power from micro-USB type A/B connector ``P2``, move the +jumper to ``JP30 7-8``. + + +.. note:: A single jumper is required in ``JP30``. + ++------+-------+-------+------+------+ +| JP31 | JP158 | JP159 | JP40 | JP42 | ++======+=======+=======+======+======+ +| 2-3 | 2-3 | 2-3 | 1-2 | 1-2 | ++------+-------+-------+------+------+ + ++------+------+------+------+------+------+------+ +| JP36 | JP37 | JP38 | JP39 | JP41 | JP43 | JP44 | ++======+======+======+======+======+======+======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++------+------+------+------+------+------+------+ + ++------+------+------+------+------+------+------+------+------+ +| JP45 | JP46 | JP47 | JP50 | JP51 | JP52 | JP55 | JP56 | JP57 | ++======+======+======+======+======+======+======+======+======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++------+------+------+------+------+------+------+------+------+ + ++------+------+------+------+------+------+------+ +| JP59 | JP60 | JP61 | JP62 | JP63 | JP65 | JP66 | ++======+======+======+======+======+======+======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++------+------+------+------+------+------+------+ + +These jumpers configure VCC Power good and nRESET_IN. + ++------------------+-------------+ +| JP32 | JP33 | +| (VCC Power good) | (nRESET_IN) | ++==================+=============+ +| 1-2 | 1-2 | ++------------------+-------------+ + +Boot-ROM Straps +--------------- + +These jumpers configure MEC172x Boot-ROM straps. + ++------------+--------------+-------------+-------------+---------------+ +| JP1 | JP2 | JP3 | JP7 | JP160 | +| (CR_STRAP) | (JTAG_STRAP) | (CMP_STRAP) | (BSS_STRAP) | (UART_BSTRAP) | ++============+==============+=============+=============+===============+ +| 1-2 | 2-3 | 2-3 | 1-2 | 1-2 | ++------------+--------------+-------------+-------------+---------------+ + +``JP7 1-2`` pulls SHD SPI CS0# up to VTR2. MEC172x Boot-ROM samples +SHD SPI CS0# and if high, it loads code from SHD SPI. + +Peripheral Routing Jumpers +-------------------------- + +Each column of the following table illustrates how to enable UART0, UART1, SHD SPI +and SWD, respectively. + ++-------+-------+------+------+------+------+------+ +| UART0 (P11) | ++-------+-------+------+------+------+------+------+ +| JP13 | JP17 | JP19 | JP22 | JP88 | JP89 | JP93 | ++=======+=======+======+======+======+======+======+ +| 2-3 | 2-3 | 1-2 | 1-2 | 2-3 | 2-3 | 1-3 | ++-------+-------+------+------+------+------+------+ +| 5-6 | 5-6 | 4-5 | 4-5 | | | 2-4 | ++-------+-------+------+------+------+------+------+ +| 8-9 | 8-9 | | | | | | ++-------+-------+------+------+------+------+------+ +| 11-12 | 11-12 | | | | | | ++-------+-------+------+------+------+------+------+ +| 14-15 | 14-15 | | | | | | ++-------+-------+------+------+------+------+------+ +| 17-18 | 17-18 | | | | | | ++-------+-------+------+------+------+------+------+ +| | 20-21 | | | | | | ++-------+-------+------+------+------+------+------+ +| | 23-24 | | | | | | ++-------+-------+------+------+------+------+------+ + ++------+------+-------+-------+------+------+-------+-----+--------+------+------+------+-------+ +| UART1 | ++---------------------------------------------------+-------------------------------------------+ +| (P12) | (P2) | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| JP11 | JP14 | JP19 | JP24 | JP90 | JP94 | JP157 | JP11 | JP19 | JP24 | JP90 | JP94 | JP157 | ++======+======+=======+=======+======+======+=======+======+=======+======+======+======+=======+ +| 1-2 | 1-2 | 20-21 | 2-3 | 2-3 | 1-3 | 1-2 | 1-2 | 11-12 | 5-6 | 2-3 | 1-3 | 1-3 | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| 4-5 | | | 5-6 | | 2-4 | 4-5 | 4-5 | | 8-9 | | 2-4 | 4-6 | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| 8-9 | | | 8-9 | | | 7-8 | | |17-18 | | | 7-9 | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| | | | 11-12 | | | 10-11 | | |23-24 | | | 10-12 | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| | | | 14-15 | | | | | | | | | | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| | | | 17-18 | | | | | | | | | | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ + +NOTE: The "Hello World" example outputs at ``UART1 P12`` . + ++----------------------+-------+--------+ +| SHD_SPI | SWD | LED4-5 | ++-------+------+-------+-------+--------+ +| JP23 | JP25 | JP156 | J18 | JP21 | ++=======+======+=======+=======+========+ +| 2-3 | 1-2 | 1-2 | 8-9 | 4-5 | ++-------+------+-------+-------+--------+ +| 8-9 | | | 11-12 | 16-17 | ++-------+------+-------+-------+--------+ +| 14-15 | | | | | ++-------+------+-------+-------+--------+ +| 17-18 | | | | | ++-------+------+-------+-------+--------+ + +Jumper settings for MEC172x 144WFBGA Socket DC Assy 6914 Rev A0p1 +================================================================= + +The jumper configuration explained above covers the base board. The ASSY +6914 MEC172x CPU board provides capability for an optional, external 32KHz +clock source. The card includes a 32KHz crystal oscillator. The card can +also be configured to use an external 50% duty cycle 32KHz source on the +XTAL2/32KHZ_IN pin. Note, firmware must set the MEC172x clock enable +register to select the external source matching the jumper settings. If +using the MEC172x internal silicon oscillator then the 32K jumper settings +are don't cares. ``JP1`` on DC is for scoping test clock outputs. Please +refer to the schematic in reference section below. + +Parallel 32KHz crystal configuration +------------------------------------ + ++-------+-------+ +| JP1 | JP2 | ++=======+=======+ +| 1-2 | 2-3 | ++-------+-------+ + +External 32KHz 50% duty cycle configuration +------------------------------------------- + ++-------+-------+ +| JP2 | JP3 | ++=======+=======+ +| NC | 1-2 | ++-------+-------+ + +NOTE: ``JP121 3-4`` on base board also needs to be loaded. + + +Programming and Debugging +************************* + +Setup +===== + +#. If you use Dediprog SF100 programmer, then setup it. + + Windows version can be found at the `SF100 Product page`_. + + Linux version source code can be found at `SF100 Linux GitHub`_. + Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer. + For Linux please make sure that you copied ``60-dediprog.rules`` + from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d) + then restart service using: + + .. code-block:: console + + $ udevadm control --reload + + Add directory with program ``dpcmd`` (on Linux) + or ``dpcmd.exe`` (on Windows) to your ``PATH``. + +#. Clone the `MEC172x SPI Image Gen`_ repository or download the files within + that directory. + +#. Make the image generation available for Zephyr, by making the tool + searchable by path, or by setting an environment variable + ``MEC172X_SPI_GEN``, for example: + + .. code-block:: console + + export MEC172X_SPI_GEN=/mec172x_spi_gen_lin_x86_64 + + Note that the tools for Linux and Windows have different file names. + +#. The default MEC172X_SPI_CFG file is spi_cfg.txt located in ${BOARD_DIR}/support. + If needed, a custom SPI image configuration file can be specified to override the + default one. + + .. code-block:: console + + export MEC172X_SPI_CFG=custom_spi_cfg.txt + +Wiring +======== + +#. Connect the SPI Dongle ASSY 6791 to ``J34`` in the EVB. + + .. image:: spidongle_assy6791.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + +#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip + ``U3``. Make sure that your programmer's offset is 0x0. + For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips. + + .. image:: dediprog_connector.jpg + :align: center + :alt: SF100 Connected + + + .. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers! + Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board. + Wiring connection is described in the table below. + + +------------+---------------+ + | Dediprog | Assy6791 | + | Connector | J6 Connector | + +============+===============+ + | VCC | 1 | + +------------+---------------+ + | GND | 2 | + +------------+---------------+ + | CS | 3 | + +------------+---------------+ + | CLK | 4 | + +------------+---------------+ + | MISO | 6 | + +------------+---------------+ + | MOSI | 5 | + +------------+---------------+ + +#. Connect UART1 port of the MEC17xxEVB_ASSY_6906 board + to your host computer using the RS232 cable. + +#. Apply power to the board via a micro-USB cable. + Configure this option by using a jumper between ``JP30 7-8``. + + .. image:: jp30_power_options.jpg + :align: center + :alt: Power Connection + +Building +======== + +#. Build :ref:`hello_world` application as you would normally do. + +#. The file :file:`spi_image.bin` will be created if the build system + can find the image generation tool. This binary image can be used + to flash the SPI chip. + +Flashing +======== + +#. Run your favorite terminal program to listen for output. + Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. + + For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Flash your board using ``west`` from the second terminal window. + Split first and second terminal windows to view both of them. + + .. code-block:: console + + $ west flash + + .. note:: When west process started press Reset button ``S2`` and do not release it + till the whole west process will not be finished successfully. + + .. image:: Reset_Button.jpg + :align: center + :alt: Reset Button + + .. note:: If you don't want to press Reset button every time, you can disconnect + SPI Dongle ASSY 6791 from the EVB during the west flash programming. + Then connect it back to the ``J34`` header and apply power to the EVB. + Result will be the same. + + +#. You should see ``"Hello World! mec172xevb_assy6906"`` in the first terminal window. + If you don't see this message, press the Reset button and the message should appear. + +Debugging +========= + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG only sessions. + +Troubleshooting +=============== + +#. In case you don't see your application running, please make sure ``LED1`` and ``LED2`` + are lit. If one of these is off, then check the power-related jumpers again. + +#. If you can't program the board using Dediprog, disconnect the Assy6791 + from the main board Assy6906 and try again. + +#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again. + +PCA9555 Enabling +================ +#. To enable PCA9555PW and test the I2C on mec172xevb_assy6906, additional works are needed: + + As the I2C slave device NXP pca95xx on mec172xevb_assy6906 is connected to I2C00 port, + however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log, + so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use + I2C01 port by making some jumpers setting as below: + + +---------+---------+------------------------------------------+ + | Pin 1 | Pin 2 | Comment | + +=========+=========+==========================================+ + | JP49.1 | JP49.2 | Connect PCA9555 VCC to +3.3V_STBY | + +---------+---------+------------------------------------------+ + | JP53.1 | JP53.2 | Select address 0100b, which means 0x26 | + +---------+---------+------------------------------------------+ + | JP12.13 | JP12.14 | Connect I2C01_SDA from CPU to header J20 | + +---------+---------+------------------------------------------+ + | JP12.4 | JP12.5 | Connect I2C01_SCL from CPU to header J20 | + +---------+---------+------------------------------------------+ + | JP77.7 | JP77.8 | External pull-up for I2C01_SDA | + +---------+---------+------------------------------------------+ + | JP77.9 | JP77.10 | External pull-up for I2C01_SCL | + +---------+---------+------------------------------------------+ + | JP58.1 | JP20.1 | Connect NXP PCA9555 SCL to I2C01 | + +---------+---------+------------------------------------------+ + | JP58.3 | JP20.3 | Connect NXP PCA9555 SDA to I2C01 | + +---------+---------+------------------------------------------+ + +References +********** + +.. target-notes:: + +.. _MEC172x Reference Manual: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172x-Data-Sheet.pdf +.. _MEC172x EVB Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-EVB-Assy_6906-A1p0-SCH.pdf +.. _MEC172x Daughter Card Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-144WFBGA-Socket-DC-Assy6914-Rev-A-SCH.pdf +.. _SPI Dongle Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/SPI%20Dongles%20and%20Aardvark%20Interposer%20Assy%206791%20Rev%20A1p1%20-%20SCH.pdf +.. _MEC172x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC172x/SPI_image_gen +.. _SF100 Linux GitHub: + https://github.com/DediProgSW/SF100Linux +.. _SF100 Product page: + https://www.dediprog.com/product/SF100 +.. _SF100 Linux manual: + https://www.dediprog.com/download/save/727.pdf diff --git a/boards/arm/mec172xevb_assy6906/doc/jp30_power_options.jpg b/boards/microchip/mec172xevb_assy6906/doc/jp30_power_options.jpg similarity index 100% rename from boards/arm/mec172xevb_assy6906/doc/jp30_power_options.jpg rename to boards/microchip/mec172xevb_assy6906/doc/jp30_power_options.jpg diff --git a/boards/arm/mec172xevb_assy6906/doc/mec172xevb_assy6906.jpg b/boards/microchip/mec172xevb_assy6906/doc/mec172xevb_assy6906.jpg similarity index 100% rename from boards/arm/mec172xevb_assy6906/doc/mec172xevb_assy6906.jpg rename to boards/microchip/mec172xevb_assy6906/doc/mec172xevb_assy6906.jpg diff --git a/boards/arm/mec172xevb_assy6906/doc/spidongle_assy6791.jpg b/boards/microchip/mec172xevb_assy6906/doc/spidongle_assy6791.jpg similarity index 100% rename from boards/arm/mec172xevb_assy6906/doc/spidongle_assy6791.jpg rename to boards/microchip/mec172xevb_assy6906/doc/spidongle_assy6791.jpg diff --git a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.dts b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts similarity index 100% rename from boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.dts rename to boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts diff --git a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.yaml b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.yaml similarity index 100% rename from boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.yaml rename to boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.yaml diff --git a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig new file mode 100644 index 00000000000..a925bc7538d --- /dev/null +++ b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2021, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_RTOS_TIMER=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/mec172xevb_assy6906/support/mec172x_remote_flasher.py b/boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py similarity index 98% rename from boards/arm/mec172xevb_assy6906/support/mec172x_remote_flasher.py rename to boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py index 14482fd093f..38d4bc39d88 100755 --- a/boards/arm/mec172xevb_assy6906/support/mec172x_remote_flasher.py +++ b/boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py @@ -31,7 +31,7 @@ product: mec172xevb_assy6906 runner: misc-flasher runner_params: - - /boards/arm/mec172xevb_assy6906/support/mec172x_remote_flasher.py + - /boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py - serial_pty: "nc,," diff --git a/boards/arm/mec172xevb_assy6906/support/spi_cfg.txt b/boards/microchip/mec172xevb_assy6906/support/spi_cfg.txt similarity index 100% rename from boards/arm/mec172xevb_assy6906/support/spi_cfg.txt rename to boards/microchip/mec172xevb_assy6906/support/spi_cfg.txt diff --git a/boards/arm/mec172xmodular_assy6930/CMakeLists.txt b/boards/microchip/mec172xmodular_assy6930/CMakeLists.txt similarity index 100% rename from boards/arm/mec172xmodular_assy6930/CMakeLists.txt rename to boards/microchip/mec172xmodular_assy6930/CMakeLists.txt diff --git a/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig b/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig new file mode 100644 index 00000000000..c0ad2565043 --- /dev/null +++ b/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Copyright (c) 2022 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MEC172XMODULAR_ASSY6930 + +if RTOS_TIMER + +# XEC RTOS timer HW frequency is fixed at 32768 Hz. +# The driver requires tickless mode and ticks per second to be 32768 for +# accurate operation. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +endif # RTOS_TIMER + +if !RTOS_TIMER + +# If RTOS timer is not enabled we use ARM Cortex-M +# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR +# processor clock divider register. We assume PCR processor clock divider +# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV +# + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 96000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +endif # RTOS_TIMER + +endif # BOARD_MEC172XMODULAR_ASSY6930 diff --git a/boards/microchip/mec172xmodular_assy6930/Kconfig.mec172xmodular_assy6930 b/boards/microchip/mec172xmodular_assy6930/Kconfig.mec172xmodular_assy6930 new file mode 100644 index 00000000000..a9c6469db85 --- /dev/null +++ b/boards/microchip/mec172xmodular_assy6930/Kconfig.mec172xmodular_assy6930 @@ -0,0 +1,5 @@ +# Copyright (c) 2022, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC172XMODULAR_ASSY6930 + select SOC_MEC172X_NSZ diff --git a/boards/arm/mec172xmodular_assy6930/board.cmake b/boards/microchip/mec172xmodular_assy6930/board.cmake similarity index 100% rename from boards/arm/mec172xmodular_assy6930/board.cmake rename to boards/microchip/mec172xmodular_assy6930/board.cmake diff --git a/boards/microchip/mec172xmodular_assy6930/board.yml b/boards/microchip/mec172xmodular_assy6930/board.yml new file mode 100644 index 00000000000..1fe04eba6e8 --- /dev/null +++ b/boards/microchip/mec172xmodular_assy6930/board.yml @@ -0,0 +1,5 @@ +board: + name: mec172xmodular_assy6930 + vendor: microchip + socs: + - name: mec172x_nsz diff --git a/boards/arm/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.jpg b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.jpg similarity index 100% rename from boards/arm/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.jpg rename to boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.jpg diff --git a/boards/arm/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst similarity index 98% rename from boards/arm/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst rename to boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst index 457cb85edaa..a3a85487342 100644 --- a/boards/arm/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst +++ b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst @@ -85,7 +85,7 @@ The mec172xmodular_assy6930 (Rev. B) board configuration supports the following Other hardware features are not currently supported by Zephyr (at the moment) The default configuration can be found in the -:zephyr_file:`boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig` Kconfig file. +:zephyr_file:`boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig` Kconfig file. Connections and IOs =================== @@ -205,7 +205,7 @@ Setup .. code-block:: console - west build -p auto -b mec172xmodular_assy6930 samples/hello_world -- -DMEC172X_SPI_GEN=$HOME/CPGZephyrDocs/MEC172x/SPI_image_gen/mec172x_spi_gen_lin_x86_64 -DMEC172X_SPI_CFG=$HOME/zephyrproject/zephyr/boards/arm/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt + west build -p auto -b mec172xmodular_assy6930 samples/hello_world -- -DMEC172X_SPI_GEN=$HOME/CPGZephyrDocs/MEC172x/SPI_image_gen/mec172x_spi_gen_lin_x86_64 -DMEC172X_SPI_CFG=$HOME/zephyrproject/zephyr/boards/microchip/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt Wiring diff --git a/boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930.dts b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts similarity index 100% rename from boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930.dts rename to boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts diff --git a/boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930.yaml b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.yaml similarity index 100% rename from boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930.yaml rename to boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.yaml diff --git a/boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig similarity index 76% rename from boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig rename to boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig index 4ebe3b29bf8..0df404e408f 100644 --- a/boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig +++ b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MEC172X_NSZ=y -CONFIG_SOC_SERIES_MEC172X=y -CONFIG_BOARD_MEC172XMODULAR_ASSY6930=y CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/mec172xmodular_assy6930/support/spi_cfg.txt b/boards/microchip/mec172xmodular_assy6930/support/spi_cfg.txt similarity index 100% rename from boards/arm/mec172xmodular_assy6930/support/spi_cfg.txt rename to boards/microchip/mec172xmodular_assy6930/support/spi_cfg.txt diff --git a/boards/arm/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt b/boards/microchip/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt similarity index 100% rename from boards/arm/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt rename to boards/microchip/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt diff --git a/boards/arm/mec172xmodular_assy6930/support/spi_cfg_4MBit.txt b/boards/microchip/mec172xmodular_assy6930/support/spi_cfg_4MBit.txt similarity index 100% rename from boards/arm/mec172xmodular_assy6930/support/spi_cfg_4MBit.txt rename to boards/microchip/mec172xmodular_assy6930/support/spi_cfg_4MBit.txt diff --git a/boards/microchip/mpfs_icicle/Kconfig b/boards/microchip/mpfs_icicle/Kconfig new file mode 100644 index 00000000000..bbacc84d304 --- /dev/null +++ b/boards/microchip/mpfs_icicle/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2021-2022 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPFS_ICICLE + select 64BIT + select SCHED_IPI_SUPPORTED + select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle b/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle new file mode 100644 index 00000000000..cc744a4f940 --- /dev/null +++ b/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle @@ -0,0 +1,5 @@ +# Copyright (c) 2021-2022 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPFS_ICICLE + select SOC_POLARFIRE diff --git a/boards/riscv/mpfs_icicle/board.cmake b/boards/microchip/mpfs_icicle/board.cmake similarity index 100% rename from boards/riscv/mpfs_icicle/board.cmake rename to boards/microchip/mpfs_icicle/board.cmake diff --git a/boards/microchip/mpfs_icicle/board.yml b/boards/microchip/mpfs_icicle/board.yml new file mode 100644 index 00000000000..a4976aa909b --- /dev/null +++ b/boards/microchip/mpfs_icicle/board.yml @@ -0,0 +1,5 @@ +board: + name: mpfs_icicle + vendor: microchip + socs: + - name: polarfire diff --git a/boards/riscv/mpfs_icicle/doc/index.rst b/boards/microchip/mpfs_icicle/doc/index.rst similarity index 100% rename from boards/riscv/mpfs_icicle/doc/index.rst rename to boards/microchip/mpfs_icicle/doc/index.rst diff --git a/boards/riscv/mpfs_icicle/mpfs_icicle.dts b/boards/microchip/mpfs_icicle/mpfs_icicle.dts similarity index 100% rename from boards/riscv/mpfs_icicle/mpfs_icicle.dts rename to boards/microchip/mpfs_icicle/mpfs_icicle.dts diff --git a/boards/riscv/mpfs_icicle/mpfs_icicle.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle.yaml similarity index 100% rename from boards/riscv/mpfs_icicle/mpfs_icicle.yaml rename to boards/microchip/mpfs_icicle/mpfs_icicle.yaml diff --git a/boards/riscv/mpfs_icicle/mpfs_icicle_defconfig b/boards/microchip/mpfs_icicle/mpfs_icicle_defconfig similarity index 80% rename from boards/riscv/mpfs_icicle/mpfs_icicle_defconfig rename to boards/microchip/mpfs_icicle/mpfs_icicle_defconfig index 60df70677e1..0e3812d078d 100644 --- a/boards/riscv/mpfs_icicle/mpfs_icicle_defconfig +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_defconfig @@ -1,12 +1,9 @@ # Copyright (c) 2020-2021 Microchip Technology Inc # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_POLARFIRE=y -CONFIG_SOC_POLARFIRE=y CONFIG_MPFS_HAL=n CONFIG_BASE64=y CONFIG_INCLUDE_RESET_VECTOR=y -CONFIG_BOARD_MPFS_ICICLE=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/mpfs_icicle/support/mpfs250t.resc b/boards/microchip/mpfs_icicle/support/mpfs250t.resc similarity index 100% rename from boards/riscv/mpfs_icicle/support/mpfs250t.resc rename to boards/microchip/mpfs_icicle/support/mpfs250t.resc diff --git a/boards/mikroe/clicker_2/Kconfig.defconfig b/boards/mikroe/clicker_2/Kconfig.defconfig new file mode 100644 index 00000000000..0bec9d8d1b2 --- /dev/null +++ b/boards/mikroe/clicker_2/Kconfig.defconfig @@ -0,0 +1,12 @@ +# MikroE Clicker 2 board configuration + +# Copyright (c) 2020 Trifork +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIKROE_CLICKER_2 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif #BOARD_MIKROE_CLICKER_2 diff --git a/boards/mikroe/clicker_2/Kconfig.mikroe_clicker_2 b/boards/mikroe/clicker_2/Kconfig.mikroe_clicker_2 new file mode 100644 index 00000000000..811134eef03 --- /dev/null +++ b/boards/mikroe/clicker_2/Kconfig.mikroe_clicker_2 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Trifork +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIKROE_CLICKER_2 + select SOC_STM32F407XG diff --git a/boards/arm/mikroe_clicker_2/board.cmake b/boards/mikroe/clicker_2/board.cmake similarity index 100% rename from boards/arm/mikroe_clicker_2/board.cmake rename to boards/mikroe/clicker_2/board.cmake diff --git a/boards/mikroe/clicker_2/board.yml b/boards/mikroe/clicker_2/board.yml new file mode 100644 index 00000000000..8ffead86036 --- /dev/null +++ b/boards/mikroe/clicker_2/board.yml @@ -0,0 +1,5 @@ +board: + name: mikroe_clicker_2 + vendor: mikroe + socs: + - name: stm32f407xx diff --git a/boards/arm/mikroe_clicker_2/doc/img/clicker-2-stm32f4-thickbox_default-2.jpg b/boards/mikroe/clicker_2/doc/img/clicker-2-stm32f4-thickbox_default-2.jpg similarity index 100% rename from boards/arm/mikroe_clicker_2/doc/img/clicker-2-stm32f4-thickbox_default-2.jpg rename to boards/mikroe/clicker_2/doc/img/clicker-2-stm32f4-thickbox_default-2.jpg diff --git a/boards/arm/mikroe_clicker_2/doc/mikroe_clicker_2.rst b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst similarity index 97% rename from boards/arm/mikroe_clicker_2/doc/mikroe_clicker_2.rst rename to boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst index 76ee5d81867..99cb9ce0c61 100644 --- a/boards/arm/mikroe_clicker_2/doc/mikroe_clicker_2.rst +++ b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst @@ -54,9 +54,8 @@ The Zephyr MikroE Clicker 2 configuration supports the following hardware featur Other hardware features have not been enabled yet for this board. -The default configuration can be found in the defconfig file: - - ``boards/arm/mikroe_clicker_2/mikroe_clicker_2_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/mikroe/clicker_2/mikroe_clicker_2_defconfig` Connections and IOs =================== diff --git a/boards/arm/mikroe_clicker_2/mikroe_clicker_2.dts b/boards/mikroe/clicker_2/mikroe_clicker_2.dts similarity index 100% rename from boards/arm/mikroe_clicker_2/mikroe_clicker_2.dts rename to boards/mikroe/clicker_2/mikroe_clicker_2.dts diff --git a/boards/arm/mikroe_clicker_2/mikroe_clicker_2.yaml b/boards/mikroe/clicker_2/mikroe_clicker_2.yaml similarity index 100% rename from boards/arm/mikroe_clicker_2/mikroe_clicker_2.yaml rename to boards/mikroe/clicker_2/mikroe_clicker_2.yaml diff --git a/boards/mikroe/clicker_2/mikroe_clicker_2_defconfig b/boards/mikroe/clicker_2/mikroe_clicker_2_defconfig new file mode 100644 index 00000000000..2c36e734c57 --- /dev/null +++ b/boards/mikroe/clicker_2/mikroe_clicker_2_defconfig @@ -0,0 +1,17 @@ +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/mikroe/index.rst b/boards/mikroe/index.rst new file mode 100644 index 00000000000..e1471b2139f --- /dev/null +++ b/boards/mikroe/index.rst @@ -0,0 +1,10 @@ +.. _boards-mikroe: + +MikroElektronika d.o.o. +####################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/mikroe/mini_m4_for_stm32/Kconfig.defconfig b/boards/mikroe/mini_m4_for_stm32/Kconfig.defconfig new file mode 100644 index 00000000000..c2f0b85f4c6 --- /dev/null +++ b/boards/mikroe/mini_m4_for_stm32/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Mikroe MINI-M4 for STM32 board configuration + +# Copyright (c) 2019, Kwon Tae-young +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIKROE_MINI_M4_FOR_STM32 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_MIKROE_MINI_M4_FOR_STM32 diff --git a/boards/mikroe/mini_m4_for_stm32/Kconfig.mikroe_mini_m4_for_stm32 b/boards/mikroe/mini_m4_for_stm32/Kconfig.mikroe_mini_m4_for_stm32 new file mode 100644 index 00000000000..0d55a5cd14d --- /dev/null +++ b/boards/mikroe/mini_m4_for_stm32/Kconfig.mikroe_mini_m4_for_stm32 @@ -0,0 +1,5 @@ +# Copyright (c) 2019, Kwon Tae-young +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIKROE_MINI_M4_FOR_STM32 + select SOC_STM32F415XX diff --git a/boards/arm/mikroe_mini_m4_for_stm32/board.cmake b/boards/mikroe/mini_m4_for_stm32/board.cmake similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/board.cmake rename to boards/mikroe/mini_m4_for_stm32/board.cmake diff --git a/boards/mikroe/mini_m4_for_stm32/board.yml b/boards/mikroe/mini_m4_for_stm32/board.yml new file mode 100644 index 00000000000..60dde764fe6 --- /dev/null +++ b/boards/mikroe/mini_m4_for_stm32/board.yml @@ -0,0 +1,5 @@ +board: + name: mikroe_mini_m4_for_stm32 + vendor: mikroe + socs: + - name: stm32f415xx diff --git a/boards/arm/mikroe_mini_m4_for_stm32/doc/img/mikroe_mini_m4_for_stm32.jpg b/boards/mikroe/mini_m4_for_stm32/doc/img/mikroe_mini_m4_for_stm32.jpg similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/doc/img/mikroe_mini_m4_for_stm32.jpg rename to boards/mikroe/mini_m4_for_stm32/doc/img/mikroe_mini_m4_for_stm32.jpg diff --git a/boards/arm/mikroe_mini_m4_for_stm32/doc/img/st-linkv2.jpg b/boards/mikroe/mini_m4_for_stm32/doc/img/st-linkv2.jpg similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/doc/img/st-linkv2.jpg rename to boards/mikroe/mini_m4_for_stm32/doc/img/st-linkv2.jpg diff --git a/boards/arm/mikroe_mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst similarity index 97% rename from boards/arm/mikroe_mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst rename to boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst index 4536296915e..7198f2da36e 100644 --- a/boards/arm/mikroe_mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst +++ b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst @@ -85,9 +85,8 @@ features: Other hardware features have not been enabled yet for this board. -The default configuration can be found in the defconfig file: - - ``boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig` Serial Port =========== diff --git a/boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts rename to boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts diff --git a/boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml rename to boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml diff --git a/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig new file mode 100644 index 00000000000..201c26b992a --- /dev/null +++ b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig @@ -0,0 +1,20 @@ +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/mikroe_mini_m4_for_stm32/support/openocd.cfg b/boards/mikroe/mini_m4_for_stm32/support/openocd.cfg similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/support/openocd.cfg rename to boards/mikroe/mini_m4_for_stm32/support/openocd.cfg diff --git a/boards/mips/index.rst b/boards/mips/index.rst deleted file mode 100644 index 011f9d74cd4..00000000000 --- a/boards/mips/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-mips: - -MIPS Boards -########### - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/mips/qemu_malta/Kconfig.board b/boards/mips/qemu_malta/Kconfig.board deleted file mode 100644 index 4716bd6dbe5..00000000000 --- a/boards/mips/qemu_malta/Kconfig.board +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2020 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_QEMU_MALTA - bool "QEMU emulation for little endian MIPS Malta" - depends on SOC_QEMU_MALTA - select QEMU_TARGET - -config BOARD_QEMU_MALTA_BE - bool "QEMU emulation for big endian MIPS Malta" - depends on SOC_QEMU_MALTA - select QEMU_TARGET - select BIG_ENDIAN diff --git a/boards/mips/qemu_malta/Kconfig.defconfig b/boards/mips/qemu_malta/Kconfig.defconfig deleted file mode 100644 index 4a583be0d9e..00000000000 --- a/boards/mips/qemu_malta/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2020 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_QEMU_MALTA || BOARD_QEMU_MALTA_BE - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_malta" if BOARD_QEMU_MALTA - default "qemu_malta_be" if BOARD_QEMU_MALTA_BE - -endif # BOARD_QEMU_MALTA || BOARD_QEMU_MALTA_BE diff --git a/boards/mips/qemu_malta/doc/index.rst b/boards/mips/qemu_malta/doc/index.rst deleted file mode 100644 index abca3138061..00000000000 --- a/boards/mips/qemu_malta/doc/index.rst +++ /dev/null @@ -1,106 +0,0 @@ -.. _qemu_malta: - -MIPS Malta Emulation (QEMU) -########################### - -Overview -******** - -This board configuration will use QEMU to emulate the MIPS Malta platform. - -This configuration provides support for an MIPS 4Kc/24Kc CPU cores and these devices: - -* CP0 Interrupt Controller -* CP0 Core Timer -* NS16550 UART - - -.. note:: - This board configuration makes no claims about its suitability for use - with an actual MIPS Malta hardware system, or any other hardware system. - -Hardware -******** - -Supported Features -================== - -The following hardware features are supported: - -+----------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+================+============+======================+ -| CP0 IntC | on-chip | interrupt controller | -+----------------+------------+----------------------+ -| CP0 Core Timer | on-chip | system clock | -+----------------+------------+----------------------+ -| NS16550 | FPGA | serial port | -| UART | | | -+----------------+------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. - -Devices -======== -System Clock ------------- - -Qemu CP0 timer uses a clock frequency of 200 MHz, -see target/mips/cp0_timer.c in Qemu source tree for details. - -Serial Port ------------ - -This board configuration uses a single serial communication channel -with the FPGA UART2. - -Programming and Debugging -************************* - -Use this configuration to run basic Zephyr applications and kernel tests in the QEMU -emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: qemu_malta - :goals: run - -This will build an image with the synchronization sample app, boot it using -QEMU, and display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build v2.7.99-1627-g9bea7790d620 *** - thread_a: Hello World from cpu 0 on qemu_malta! - thread_b: Hello World from cpu 0 on qemu_malta! - thread_a: Hello World from cpu 0 on qemu_malta! - thread_b: Hello World from cpu 0 on qemu_malta! - thread_a: Hello World from cpu 0 on qemu_malta! - thread_b: Hello World from cpu 0 on qemu_malta! - thread_a: Hello World from cpu 0 on qemu_malta! - thread_b: Hello World from cpu 0 on qemu_malta! - thread_a: Hello World from cpu 0 on qemu_malta! - thread_b: Hello World from cpu 0 on qemu_malta! - - -Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. - - -Big-Endian -========== - -Use this configuration to run :zephyr:code-sample:`synchronization` sample in big-endian mode: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: qemu_malta_be - :goals: run - - -References -********** - -https://www.qemu.org/ -https://www.linux-mips.org/wiki/MIPS_Malta diff --git a/boards/mips/qemu_malta/qemu_malta_be.yaml b/boards/mips/qemu_malta/qemu_malta_be.yaml deleted file mode 100644 index 91a9444d00b..00000000000 --- a/boards/mips/qemu_malta/qemu_malta_be.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: qemu_malta_be -name: QEMU emulation for MIPS (big endian) -type: qemu -simulation: qemu -arch: mips -toolchain: - - zephyr - - xtools -ram: 1024 -flash: 512 -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: qemu diff --git a/boards/mips/qemu_malta/qemu_malta_be_defconfig b/boards/mips/qemu_malta/qemu_malta_be_defconfig deleted file mode 100644 index cbdcfed736a..00000000000 --- a/boards/mips/qemu_malta/qemu_malta_be_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_SOC_QEMU_MALTA=y -CONFIG_BOARD_QEMU_MALTA_BE=y -CONFIG_MIPS_CP0_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT=y -CONFIG_QEMU_ICOUNT_SHIFT=3 diff --git a/boards/mips/qemu_malta/qemu_malta_defconfig b/boards/mips/qemu_malta/qemu_malta_defconfig deleted file mode 100644 index edf9e147897..00000000000 --- a/boards/mips/qemu_malta/qemu_malta_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_SOC_QEMU_MALTA=y -CONFIG_BOARD_QEMU_MALTA=y -CONFIG_MIPS_CP0_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT=y -CONFIG_QEMU_ICOUNT_SHIFT=3 diff --git a/boards/mxchip/az3166_iotdevkit/Kconfig.az3166_iotdevkit b/boards/mxchip/az3166_iotdevkit/Kconfig.az3166_iotdevkit new file mode 100644 index 00000000000..6e28ac7185b --- /dev/null +++ b/boards/mxchip/az3166_iotdevkit/Kconfig.az3166_iotdevkit @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Benjamin Cabé +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_AZ3166_IOTDEVKIT + select SOC_STM32F412RX diff --git a/boards/arm/az3166_iotdevkit/az3166_iotdevkit.dts b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts similarity index 100% rename from boards/arm/az3166_iotdevkit/az3166_iotdevkit.dts rename to boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts diff --git a/boards/arm/az3166_iotdevkit/az3166_iotdevkit.yaml b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.yaml similarity index 100% rename from boards/arm/az3166_iotdevkit/az3166_iotdevkit.yaml rename to boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.yaml diff --git a/boards/arm/az3166_iotdevkit/az3166_iotdevkit_defconfig b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit_defconfig similarity index 85% rename from boards/arm/az3166_iotdevkit/az3166_iotdevkit_defconfig rename to boards/mxchip/az3166_iotdevkit/az3166_iotdevkit_defconfig index 883b48c2622..ee16a27c1e1 100644 --- a/boards/arm/az3166_iotdevkit/az3166_iotdevkit_defconfig +++ b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F412RX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/az3166_iotdevkit/board.cmake b/boards/mxchip/az3166_iotdevkit/board.cmake similarity index 100% rename from boards/arm/az3166_iotdevkit/board.cmake rename to boards/mxchip/az3166_iotdevkit/board.cmake diff --git a/boards/mxchip/az3166_iotdevkit/board.yml b/boards/mxchip/az3166_iotdevkit/board.yml new file mode 100644 index 00000000000..4ac727ed1c2 --- /dev/null +++ b/boards/mxchip/az3166_iotdevkit/board.yml @@ -0,0 +1,5 @@ +board: + name: az3166_iotdevkit + vendor: mxchip + socs: + - name: stm32f412rx diff --git a/boards/arm/az3166_iotdevkit/doc/img/az3166-iotdevkit.webp b/boards/mxchip/az3166_iotdevkit/doc/img/az3166-iotdevkit.webp similarity index 100% rename from boards/arm/az3166_iotdevkit/doc/img/az3166-iotdevkit.webp rename to boards/mxchip/az3166_iotdevkit/doc/img/az3166-iotdevkit.webp diff --git a/boards/arm/az3166_iotdevkit/doc/index.rst b/boards/mxchip/az3166_iotdevkit/doc/index.rst similarity index 100% rename from boards/arm/az3166_iotdevkit/doc/index.rst rename to boards/mxchip/az3166_iotdevkit/doc/index.rst diff --git a/boards/arm/az3166_iotdevkit/support/openocd.cfg b/boards/mxchip/az3166_iotdevkit/support/openocd.cfg similarity index 100% rename from boards/arm/az3166_iotdevkit/support/openocd.cfg rename to boards/mxchip/az3166_iotdevkit/support/openocd.cfg diff --git a/boards/mxchip/index.rst b/boards/mxchip/index.rst new file mode 100644 index 00000000000..9cad4f437d8 --- /dev/null +++ b/boards/mxchip/index.rst @@ -0,0 +1,10 @@ +.. _boards-mxchip: + +MXCHIP +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/posix/common/extra_args/CMakeLists.txt b/boards/native/common/extra_args/CMakeLists.txt similarity index 100% rename from boards/posix/common/extra_args/CMakeLists.txt rename to boards/native/common/extra_args/CMakeLists.txt diff --git a/boards/posix/common/extra_args/Kconfig b/boards/native/common/extra_args/Kconfig similarity index 100% rename from boards/posix/common/extra_args/Kconfig rename to boards/native/common/extra_args/Kconfig diff --git a/boards/posix/common/extra_args/extra_args.c b/boards/native/common/extra_args/extra_args.c similarity index 100% rename from boards/posix/common/extra_args/extra_args.c rename to boards/native/common/extra_args/extra_args.c diff --git a/boards/posix/common/irq/board_irq.h b/boards/native/common/irq/board_irq.h similarity index 100% rename from boards/posix/common/irq/board_irq.h rename to boards/native/common/irq/board_irq.h diff --git a/boards/posix/common/natsim_config.cmake b/boards/native/common/natsim_config.cmake similarity index 95% rename from boards/posix/common/natsim_config.cmake rename to boards/native/common/natsim_config.cmake index 54e800cd327..d9decf2cacd 100644 --- a/boards/posix/common/natsim_config.cmake +++ b/boards/native/common/natsim_config.cmake @@ -5,7 +5,7 @@ set(zephyr_build_path ${APPLICATION_BINARY_DIR}/zephyr) get_property(CCACHE GLOBAL PROPERTY RULE_LAUNCH_COMPILE) target_link_options(native_simulator INTERFACE - "-T ${ZEPHYR_BASE}/boards/posix/common/natsim_linker_script.ld") + "-T ${ZEPHYR_BASE}/boards/native/common/natsim_linker_script.ld") set(nsi_config_content ${nsi_config_content} diff --git a/boards/posix/common/natsim_linker_script.ld b/boards/native/common/natsim_linker_script.ld similarity index 100% rename from boards/posix/common/natsim_linker_script.ld rename to boards/native/common/natsim_linker_script.ld diff --git a/boards/posix/common/sdl/CMakeLists.txt b/boards/native/common/sdl/CMakeLists.txt similarity index 100% rename from boards/posix/common/sdl/CMakeLists.txt rename to boards/native/common/sdl/CMakeLists.txt diff --git a/boards/posix/common/sdl/Kconfig b/boards/native/common/sdl/Kconfig similarity index 100% rename from boards/posix/common/sdl/Kconfig rename to boards/native/common/sdl/Kconfig diff --git a/boards/posix/common/sdl/sdl_events.c b/boards/native/common/sdl/sdl_events.c similarity index 100% rename from boards/posix/common/sdl/sdl_events.c rename to boards/native/common/sdl/sdl_events.c diff --git a/boards/posix/common/sdl/sdl_events_bottom.c b/boards/native/common/sdl/sdl_events_bottom.c similarity index 100% rename from boards/posix/common/sdl/sdl_events_bottom.c rename to boards/native/common/sdl/sdl_events_bottom.c diff --git a/boards/posix/common/sdl/sdl_events_bottom.h b/boards/native/common/sdl/sdl_events_bottom.h similarity index 100% rename from boards/posix/common/sdl/sdl_events_bottom.h rename to boards/native/common/sdl/sdl_events_bottom.h diff --git a/boards/posix/doc/Port_vs_QEMU_vs.svg b/boards/native/doc/Port_vs_QEMU_vs.svg similarity index 100% rename from boards/posix/doc/Port_vs_QEMU_vs.svg rename to boards/native/doc/Port_vs_QEMU_vs.svg diff --git a/boards/posix/doc/Zephyr_and_bsim.svg b/boards/native/doc/Zephyr_and_bsim.svg similarity index 100% rename from boards/posix/doc/Zephyr_and_bsim.svg rename to boards/native/doc/Zephyr_and_bsim.svg diff --git a/boards/posix/doc/arch_soc.rst b/boards/native/doc/arch_soc.rst similarity index 100% rename from boards/posix/doc/arch_soc.rst rename to boards/native/doc/arch_soc.rst diff --git a/boards/posix/doc/bsim_boards_design.rst b/boards/native/doc/bsim_boards_design.rst similarity index 100% rename from boards/posix/doc/bsim_boards_design.rst rename to boards/native/doc/bsim_boards_design.rst diff --git a/boards/posix/doc/layering.svg b/boards/native/doc/layering.svg similarity index 100% rename from boards/posix/doc/layering.svg rename to boards/native/doc/layering.svg diff --git a/boards/posix/doc/layering_natsim.svg b/boards/native/doc/layering_natsim.svg similarity index 100% rename from boards/posix/doc/layering_natsim.svg rename to boards/native/doc/layering_natsim.svg diff --git a/boards/posix/index.rst b/boards/native/index.rst similarity index 100% rename from boards/posix/index.rst rename to boards/native/index.rst diff --git a/boards/native/native_posix/CMakeLists.txt b/boards/native/native_posix/CMakeLists.txt new file mode 100644 index 00000000000..b86941cc854 --- /dev/null +++ b/boards/native/native_posix/CMakeLists.txt @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Oticon A/S + +zephyr_library() + +zephyr_library_compile_definitions(NO_POSIX_CHEATS) +zephyr_library_compile_definitions(_POSIX_C_SOURCE=200809L _XOPEN_SOURCE=600 _XOPEN_SOURCE_EXTENDED) + +zephyr_library_sources( + hw_models_top.c + timer_model.c + native_rtc.c + irq_handler.c + irq_ctrl.c + main.c + tracing.c + cmdline_common.c + cmdline.c + cpu_wait.c + hw_counter.c + ) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/posix/include + ) + +if(CONFIG_HAS_SDL) + add_subdirectory(${ZEPHYR_BASE}/boards/native/common/sdl/ ${CMAKE_CURRENT_BINARY_DIR}/sdl) +endif() + +zephyr_ld_options( + -lm +) diff --git a/boards/native/native_posix/Kconfig b/boards/native/native_posix/Kconfig new file mode 100644 index 00000000000..eee6cd26b03 --- /dev/null +++ b/boards/native/native_posix/Kconfig @@ -0,0 +1,47 @@ +# Copyright (c) 2017 Oticon A/S +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_POSIX + bool + imply NATIVE_POSIX_TIMER + select POSIX_ARCH_CONSOLE + select NATIVE_APPLICATION + select 64BIT if BOARD_NATIVE_POSIX_NATIVE_64 + help + Native POSIX + Will produce a console Linux process which can be executed natively. + It provides some minimal needed models: + An interrupt controller, timer (system tick), and redirects kernel prints to + stdout. + +config BOARD_NATIVE_POSIX_64 + bool + select BOARD_NATIVE_POSIX + select 64BIT + help + Native POSIX - 64 bit version + Will produce a console Linux process which can be executed natively + as a 64-bit executable. + It provides some minimal needed models: + An interrupt controller, timer (system tick), and redirects kernel prints to + stdout. + +if BOARD_NATIVE_POSIX + +comment "Native POSIX options" + +config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME + bool "Slow down execution to real time" + default n if ARCH_POSIX_LIBFUZZER + default y if BT_USERCHAN || !TEST + help + When selected the execution of the process will be slowed down to real time. + (if there is a lot of load it may be slower than real time) + If deselected, the process will run as fast as possible. + Note that this only decouples simulated time from real/wall time. In either + case the zephyr kernel and application cannot tell the difference unless they + interact with some other driver/device which runs at real time. + +source "boards/native/common/sdl/Kconfig" + +endif # BOARD_NATIVE_POSIX diff --git a/boards/native/native_posix/Kconfig.defconfig b/boards/native/native_posix/Kconfig.defconfig new file mode 100644 index 00000000000..5fc24d50c62 --- /dev/null +++ b/boards/native/native_posix/Kconfig.defconfig @@ -0,0 +1,69 @@ +# Copyright (c) 2017 Oticon A/S +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NATIVE_POSIX + +config BUILD_OUTPUT_BIN + default n + +config BUILD_OUTPUT_EXE + default y + +config OUTPUT_PRINT_MEMORY_USAGE + default n + +if NETWORKING + +config NET_L2_ETHERNET + default y if !NET_LOOPBACK && !NET_TEST + +config ETH_NATIVE_POSIX + default y if NET_L2_ETHERNET && ETH_DRIVER + +endif # NETWORKING + +choice BT_HCI_BUS_TYPE + default BT_USERCHAN + depends on BT_HCI +endchoice + +if LOG + +# For native_posix we can log synchronously without any problem +# Doing so will be nicer for debugging +choice LOG_MODE + default LOG_MODE_IMMEDIATE +endchoice + +endif # LOG + +if CONSOLE + +config POSIX_ARCH_CONSOLE + default y if !SERIAL + +config UART_CONSOLE + default y if SERIAL + +endif # CONSOLE + +config FLASH_SIMULATOR + default y + depends on FLASH + +config USB_NATIVE_POSIX + default y + depends on USB_DEVICE_DRIVER + +config EEPROM_SIMULATOR + default y + depends on EEPROM + +if I2C + +config EMUL + default y + +endif # I2C + +endif # BOARD_NATIVE_POSIX diff --git a/boards/native/native_posix/Kconfig.native_posix b/boards/native/native_posix/Kconfig.native_posix new file mode 100644 index 00000000000..cb7c03889c4 --- /dev/null +++ b/boards/native/native_posix/Kconfig.native_posix @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_POSIX + select SOC_POSIX diff --git a/boards/native/native_posix/Kconfig.native_posix_64 b/boards/native/native_posix/Kconfig.native_posix_64 new file mode 100644 index 00000000000..8151a520910 --- /dev/null +++ b/boards/native/native_posix/Kconfig.native_posix_64 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_POSIX_64 + select SOC_POSIX diff --git a/boards/native/native_posix/board.cmake b/boards/native/native_posix/board.cmake new file mode 100644 index 00000000000..f8c2fd58f87 --- /dev/null +++ b/boards/native/native_posix/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Oticon A/S + +set(SUPPORTED_EMU_PLATFORMS native) + +board_set_debugger_ifnset(native_gdb) +board_finalize_runner_args(native_gdb) diff --git a/boards/native/native_posix/board.yml b/boards/native/native_posix/board.yml new file mode 100644 index 00000000000..8ab212aa1f9 --- /dev/null +++ b/boards/native/native_posix/board.yml @@ -0,0 +1,15 @@ +boards: +- name: native_posix + vendor: zephyr + socs: + - name: native + variants: + - name: "64" + +# This board definition below, together with its respective +# Kconfig.native_posix_64 exist for backwards compatibility with the hwmv1 board name +# Once all its usage in tree is removed, or an alias has been introduced they can be removed. +- name: native_posix_64 + vendor: zephyr + socs: + - name: native diff --git a/boards/posix/native_posix/board_irq.h b/boards/native/native_posix/board_irq.h similarity index 100% rename from boards/posix/native_posix/board_irq.h rename to boards/native/native_posix/board_irq.h diff --git a/boards/posix/native_posix/board_soc.h b/boards/native/native_posix/board_soc.h similarity index 100% rename from boards/posix/native_posix/board_soc.h rename to boards/native/native_posix/board_soc.h diff --git a/boards/posix/native_posix/cmdline.c b/boards/native/native_posix/cmdline.c similarity index 100% rename from boards/posix/native_posix/cmdline.c rename to boards/native/native_posix/cmdline.c diff --git a/boards/posix/native_posix/cmdline.h b/boards/native/native_posix/cmdline.h similarity index 100% rename from boards/posix/native_posix/cmdline.h rename to boards/native/native_posix/cmdline.h diff --git a/boards/posix/native_posix/cmdline_common.c b/boards/native/native_posix/cmdline_common.c similarity index 100% rename from boards/posix/native_posix/cmdline_common.c rename to boards/native/native_posix/cmdline_common.c diff --git a/boards/posix/native_posix/cmdline_common.h b/boards/native/native_posix/cmdline_common.h similarity index 100% rename from boards/posix/native_posix/cmdline_common.h rename to boards/native/native_posix/cmdline_common.h diff --git a/boards/posix/native_posix/cpu_wait.c b/boards/native/native_posix/cpu_wait.c similarity index 100% rename from boards/posix/native_posix/cpu_wait.c rename to boards/native/native_posix/cpu_wait.c diff --git a/boards/posix/native_posix/doc/index.rst b/boards/native/native_posix/doc/index.rst similarity index 100% rename from boards/posix/native_posix/doc/index.rst rename to boards/native/native_posix/doc/index.rst diff --git a/boards/posix/native_posix/hw_counter.c b/boards/native/native_posix/hw_counter.c similarity index 100% rename from boards/posix/native_posix/hw_counter.c rename to boards/native/native_posix/hw_counter.c diff --git a/boards/posix/native_posix/hw_counter.h b/boards/native/native_posix/hw_counter.h similarity index 100% rename from boards/posix/native_posix/hw_counter.h rename to boards/native/native_posix/hw_counter.h diff --git a/boards/posix/native_posix/hw_models_top.c b/boards/native/native_posix/hw_models_top.c similarity index 100% rename from boards/posix/native_posix/hw_models_top.c rename to boards/native/native_posix/hw_models_top.c diff --git a/boards/posix/native_posix/hw_models_top.h b/boards/native/native_posix/hw_models_top.h similarity index 100% rename from boards/posix/native_posix/hw_models_top.h rename to boards/native/native_posix/hw_models_top.h diff --git a/boards/posix/native_posix/irq_ctrl.c b/boards/native/native_posix/irq_ctrl.c similarity index 100% rename from boards/posix/native_posix/irq_ctrl.c rename to boards/native/native_posix/irq_ctrl.c diff --git a/boards/posix/native_posix/irq_ctrl.h b/boards/native/native_posix/irq_ctrl.h similarity index 100% rename from boards/posix/native_posix/irq_ctrl.h rename to boards/native/native_posix/irq_ctrl.h diff --git a/boards/posix/native_posix/irq_handler.c b/boards/native/native_posix/irq_handler.c similarity index 100% rename from boards/posix/native_posix/irq_handler.c rename to boards/native/native_posix/irq_handler.c diff --git a/boards/posix/native_posix/irq_handler.h b/boards/native/native_posix/irq_handler.h similarity index 100% rename from boards/posix/native_posix/irq_handler.h rename to boards/native/native_posix/irq_handler.h diff --git a/boards/posix/native_posix/main.c b/boards/native/native_posix/main.c similarity index 100% rename from boards/posix/native_posix/main.c rename to boards/native/native_posix/main.c diff --git a/boards/posix/native_posix/native_posix.dts b/boards/native/native_posix/native_posix.dts similarity index 100% rename from boards/posix/native_posix/native_posix.dts rename to boards/native/native_posix/native_posix.dts diff --git a/boards/posix/native_posix/native_posix.yaml b/boards/native/native_posix/native_posix.yaml similarity index 100% rename from boards/posix/native_posix/native_posix.yaml rename to boards/native/native_posix/native_posix.yaml diff --git a/boards/posix/native_posix/native_posix_64.dts b/boards/native/native_posix/native_posix_64.dts similarity index 100% rename from boards/posix/native_posix/native_posix_64.dts rename to boards/native/native_posix/native_posix_64.dts diff --git a/boards/posix/native_posix/native_posix_64.yaml b/boards/native/native_posix/native_posix_64.yaml similarity index 100% rename from boards/posix/native_posix/native_posix_64.yaml rename to boards/native/native_posix/native_posix_64.yaml diff --git a/boards/native/native_posix/native_posix_64_defconfig b/boards/native/native_posix/native_posix_64_defconfig new file mode 100644 index 00000000000..b0033eda61f --- /dev/null +++ b/boards/native/native_posix/native_posix_64_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/native/native_posix/native_posix_defconfig b/boards/native/native_posix/native_posix_defconfig new file mode 100644 index 00000000000..b0033eda61f --- /dev/null +++ b/boards/native/native_posix/native_posix_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/native_posix/native_rtc.c b/boards/native/native_posix/native_rtc.c similarity index 100% rename from boards/posix/native_posix/native_rtc.c rename to boards/native/native_posix/native_rtc.c diff --git a/boards/posix/native_posix/native_rtc.h b/boards/native/native_posix/native_rtc.h similarity index 100% rename from boards/posix/native_posix/native_rtc.h rename to boards/native/native_posix/native_rtc.h diff --git a/boards/posix/native_posix/native_tracing.h b/boards/native/native_posix/native_tracing.h similarity index 100% rename from boards/posix/native_posix/native_tracing.h rename to boards/native/native_posix/native_tracing.h diff --git a/boards/posix/native_posix/timer_model.c b/boards/native/native_posix/timer_model.c similarity index 100% rename from boards/posix/native_posix/timer_model.c rename to boards/native/native_posix/timer_model.c diff --git a/boards/posix/native_posix/timer_model.h b/boards/native/native_posix/timer_model.h similarity index 100% rename from boards/posix/native_posix/timer_model.h rename to boards/native/native_posix/timer_model.h diff --git a/boards/posix/native_posix/tracing.c b/boards/native/native_posix/tracing.c similarity index 100% rename from boards/posix/native_posix/tracing.c rename to boards/native/native_posix/tracing.c diff --git a/boards/native/native_sim/CMakeLists.txt b/boards/native/native_sim/CMakeLists.txt new file mode 100644 index 00000000000..2bb964f49e8 --- /dev/null +++ b/boards/native/native_sim/CMakeLists.txt @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_compile_definitions(NO_POSIX_CHEATS) + +zephyr_library_sources( + cmdline.c + cpu_wait.c + nsi_if.c + irq_handler.c + misc.c + posix_arch_if.c + ) + +zephyr_include_directories( + ${NSI_DIR}/common/src/include + ${NSI_DIR}/native/src/include +) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/posix/include +) + +if(CONFIG_HAS_SDL) + add_subdirectory(${ZEPHYR_BASE}/boards/native/common/sdl/ ${CMAKE_CURRENT_BINARY_DIR}/sdl) +endif() + +add_subdirectory(${ZEPHYR_BASE}/boards/native/common/extra_args/ + ${CMAKE_CURRENT_BINARY_DIR}/extra_args +) + +set(nsi_config_content + ${nsi_config_content} + "NSI_NATIVE=1" +) + +include(../common/natsim_config.cmake) diff --git a/boards/native/native_sim/Kconfig b/boards/native/native_sim/Kconfig new file mode 100644 index 00000000000..e61028cce07 --- /dev/null +++ b/boards/native/native_sim/Kconfig @@ -0,0 +1,63 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_SIM + bool + select POSIX_ARCH_CONSOLE + select NATIVE_LIBRARY + select NATIVE_POSIX_TIMER + select 64BIT if BOARD_NATIVE_SIM_NATIVE_64 + imply BOARD_NATIVE_POSIX if NATIVE_SIM_NATIVE_POSIX_COMPAT + help + Native simulator (Single Core) + Will produce a console Linux process which can be executed natively. + +config BOARD_NATIVE_SIM_64 + bool + select BOARD_NATIVE_SIM + select 64BIT + help + Native simulator (Single Core) - 64 bit version + Will produce a console Linux process which can be executed natively + as a 64-bit executable. + +if BOARD_NATIVE_SIM + +comment "Native Simular (Single Core) options" + +config NATIVE_SIM_NATIVE_POSIX_COMPAT + bool "Pretend to be a native_posix board" + default y + help + When this option is set the native_sim board will pretend to be + a native_posix board from kconfig point of view, to allow using it directly with + code which was meant for the native_posix board and checks for the macro + CONFIG_BOARD_NATIVE_POSIX, or requires other kconfig options which depend on it. + +config NATIVE_SIM_SLOWDOWN_TO_REAL_TIME + bool "Slow down execution to real time" + default n if ARCH_POSIX_LIBFUZZER + default y if BT_USERCHAN || !TEST + help + When selected the execution of the process will be slowed down to real time. + (if there is a lot of load it may be slower than real time) + If deselected, the process will run as fast as possible. + Note that this only decouples simulated time from real/wall time. In either + case the zephyr kernel and application cannot tell the difference unless they + interact with some other driver/device which runs at real time. + +# This option definition exists only to enable NATIVE_SIM_NATIVE_POSIX_COMPAT +config BOARD_NATIVE_POSIX + bool + +config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME + bool "Slow down execution to real time (native_posix compat)" + select NATIVE_SIM_SLOWDOWN_TO_REAL_TIME + help + Transitional option which allows applications which targeted native_posix + to set the correct native_sim option (CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME) + +source "boards/native/common/sdl/Kconfig" +source "boards/native/common/extra_args/Kconfig" + +endif # BOARD_NATIVE_SIM diff --git a/boards/native/native_sim/Kconfig.defconfig b/boards/native/native_sim/Kconfig.defconfig new file mode 100644 index 00000000000..64657779d7a --- /dev/null +++ b/boards/native/native_sim/Kconfig.defconfig @@ -0,0 +1,69 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NATIVE_SIM + +config BUILD_OUTPUT_BIN + default n + +config BUILD_OUTPUT_EXE + default y + +config OUTPUT_PRINT_MEMORY_USAGE + default n + +if NETWORKING + +config NET_L2_ETHERNET + default y if !NET_LOOPBACK && !NET_TEST + +config ETH_NATIVE_POSIX + default y if NET_L2_ETHERNET && ETH_DRIVER + +endif # NETWORKING + +choice BT_HCI_BUS_TYPE + default BT_USERCHAN + depends on BT_HCI +endchoice + +if LOG + +# For native_sim we can log synchronously without any problem +# Doing so will be nicer for debugging +choice LOG_MODE + default LOG_MODE_IMMEDIATE +endchoice + +endif # LOG + +if CONSOLE + +config POSIX_ARCH_CONSOLE + default y if !SERIAL + +config UART_CONSOLE + default y if SERIAL + +endif # CONSOLE + +config FLASH_SIMULATOR + default y + depends on FLASH + +config USB_NATIVE_POSIX + default y + depends on USB_DEVICE_DRIVER + +config EEPROM_SIMULATOR + default y + depends on EEPROM + +if I2C + +config EMUL + default y + +endif # I2C + +endif # BOARD_NATIVE_SIM diff --git a/boards/native/native_sim/Kconfig.native_sim b/boards/native/native_sim/Kconfig.native_sim new file mode 100644 index 00000000000..8d75397d490 --- /dev/null +++ b/boards/native/native_sim/Kconfig.native_sim @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_SIM + select SOC_POSIX diff --git a/boards/native/native_sim/Kconfig.native_sim_64 b/boards/native/native_sim/Kconfig.native_sim_64 new file mode 100644 index 00000000000..c03791abd35 --- /dev/null +++ b/boards/native/native_sim/Kconfig.native_sim_64 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_SIM_64 + select SOC_POSIX diff --git a/boards/posix/native_posix/board.cmake b/boards/native/native_sim/board.cmake similarity index 100% rename from boards/posix/native_posix/board.cmake rename to boards/native/native_sim/board.cmake diff --git a/boards/native/native_sim/board.yml b/boards/native/native_sim/board.yml new file mode 100644 index 00000000000..31ee9fabc08 --- /dev/null +++ b/boards/native/native_sim/board.yml @@ -0,0 +1,15 @@ +boards: +- name: native_sim + vendor: zephyr + socs: + - name: native + variants: + - name: "64" + +# This board definition below, together with its respective +# Kconfig.native_sim_64 exist for backwards compatibility with the hwmv1 board name +# Once all its usage in tree is removed, or an alias has been introduced they can be removed. +- name: native_sim_64 + vendor: zephyr + socs: + - name: native diff --git a/boards/posix/native_sim/board_irq.h b/boards/native/native_sim/board_irq.h similarity index 100% rename from boards/posix/native_sim/board_irq.h rename to boards/native/native_sim/board_irq.h diff --git a/boards/posix/native_sim/board_soc.h b/boards/native/native_sim/board_soc.h similarity index 100% rename from boards/posix/native_sim/board_soc.h rename to boards/native/native_sim/board_soc.h diff --git a/boards/posix/native_sim/cmdline.c b/boards/native/native_sim/cmdline.c similarity index 100% rename from boards/posix/native_sim/cmdline.c rename to boards/native/native_sim/cmdline.c diff --git a/boards/posix/native_sim/cmdline.h b/boards/native/native_sim/cmdline.h similarity index 100% rename from boards/posix/native_sim/cmdline.h rename to boards/native/native_sim/cmdline.h diff --git a/boards/posix/native_sim/cmdline_common.h b/boards/native/native_sim/cmdline_common.h similarity index 100% rename from boards/posix/native_sim/cmdline_common.h rename to boards/native/native_sim/cmdline_common.h diff --git a/boards/posix/native_sim/cpu_wait.c b/boards/native/native_sim/cpu_wait.c similarity index 100% rename from boards/posix/native_sim/cpu_wait.c rename to boards/native/native_sim/cpu_wait.c diff --git a/boards/posix/native_sim/doc/index.rst b/boards/native/native_sim/doc/index.rst similarity index 100% rename from boards/posix/native_sim/doc/index.rst rename to boards/native/native_sim/doc/index.rst diff --git a/boards/posix/native_sim/irq_handler.c b/boards/native/native_sim/irq_handler.c similarity index 100% rename from boards/posix/native_sim/irq_handler.c rename to boards/native/native_sim/irq_handler.c diff --git a/boards/posix/native_sim/irq_handler.h b/boards/native/native_sim/irq_handler.h similarity index 100% rename from boards/posix/native_sim/irq_handler.h rename to boards/native/native_sim/irq_handler.h diff --git a/boards/posix/native_sim/misc.c b/boards/native/native_sim/misc.c similarity index 100% rename from boards/posix/native_sim/misc.c rename to boards/native/native_sim/misc.c diff --git a/boards/posix/native_sim/native_posix_compat.h b/boards/native/native_sim/native_posix_compat.h similarity index 100% rename from boards/posix/native_sim/native_posix_compat.h rename to boards/native/native_sim/native_posix_compat.h diff --git a/boards/posix/native_sim/native_sim.dts b/boards/native/native_sim/native_sim.dts similarity index 100% rename from boards/posix/native_sim/native_sim.dts rename to boards/native/native_sim/native_sim.dts diff --git a/boards/posix/native_sim/native_sim.yaml b/boards/native/native_sim/native_sim.yaml similarity index 100% rename from boards/posix/native_sim/native_sim.yaml rename to boards/native/native_sim/native_sim.yaml diff --git a/boards/posix/native_sim/native_sim_64.dts b/boards/native/native_sim/native_sim_64.dts similarity index 100% rename from boards/posix/native_sim/native_sim_64.dts rename to boards/native/native_sim/native_sim_64.dts diff --git a/boards/posix/native_sim/native_sim_64.yaml b/boards/native/native_sim/native_sim_64.yaml similarity index 100% rename from boards/posix/native_sim/native_sim_64.yaml rename to boards/native/native_sim/native_sim_64.yaml diff --git a/boards/native/native_sim/native_sim_64_defconfig b/boards/native/native_sim/native_sim_64_defconfig new file mode 100644 index 00000000000..b0033eda61f --- /dev/null +++ b/boards/native/native_sim/native_sim_64_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/native/native_sim/native_sim_defconfig b/boards/native/native_sim/native_sim_defconfig new file mode 100644 index 00000000000..b0033eda61f --- /dev/null +++ b/boards/native/native_sim/native_sim_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/native_sim/nsi_if.c b/boards/native/native_sim/nsi_if.c similarity index 100% rename from boards/posix/native_sim/nsi_if.c rename to boards/native/native_sim/nsi_if.c diff --git a/boards/posix/native_sim/posix_arch_if.c b/boards/native/native_sim/posix_arch_if.c similarity index 100% rename from boards/posix/native_sim/posix_arch_if.c rename to boards/native/native_sim/posix_arch_if.c diff --git a/boards/posix/native_sim/timer_model.h b/boards/native/native_sim/timer_model.h similarity index 100% rename from boards/posix/native_sim/timer_model.h rename to boards/native/native_sim/timer_model.h diff --git a/boards/native/nrf_bsim/CMakeLists.txt b/boards/native/nrf_bsim/CMakeLists.txt new file mode 100644 index 00000000000..a4329cd8880 --- /dev/null +++ b/boards/native/nrf_bsim/CMakeLists.txt @@ -0,0 +1,80 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# Copyright (c) 2018 Oticon A/S +# SPDX-License-Identifier: Apache-2.0 + +find_package(BabbleSim) + +zephyr_library() + +# Due to the BLE controller assumption about enum size +zephyr_compile_options( + -fshort-enums +) +# Structures layouts needs to match in the interface between the runner and the embedded SW +# The nrfx HAL uses enums in its definitions,so they need to have the same size in both, +# as both the HW models and embedded SW use them. +target_compile_options(native_simulator INTERFACE -fshort-enums) + +zephyr_library_sources( + irq_handler.c + cpu_wait.c + argparse.c + nsi_if.c + soc/nrfx_coredep.c + common/bstests_entry.c + common/cmsis/cmsis.c + common/trace_hook.c +) + +# Include sync_rtc from real SOC code if enabled +zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC + ${ZEPHYR_BASE}/soc/nordic/nrf53/sync_rtc.c + ) + +target_sources(native_simulator INTERFACE + common/bsim_args_runner.c + common/bsim_extra_cpu_if_stubs.c + common/phy_sync_ctrl.c + common/runner_hooks.c + common/posix_arch_if.c + common/trace_hook.c +) + +if (CONFIG_IPC_SERVICE AND CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUAPP) + zephyr_library_sources( + ipc_backend.c + ) +endif() + +zephyr_include_directories( + soc + common + common/cmsis + ${NSI_DIR}/common/src/include +) + +zephyr_library_include_directories( + ${BSIM_COMPONENTS_PATH}/libUtilv1/src/ + ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/ + ${BSIM_COMPONENTS_PATH}/libRandv2/src/ + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/posix/include + common/ +) + +set(libpath ${BSIM_OUT_PATH}/lib) +set_property(TARGET native_simulator APPEND PROPERTY RUNNER_LINK_LIBRARIES + ${libpath}/libUtilv1.32.a + ${libpath}/libPhyComv1.32.a + ${libpath}/lib2G4PhyComv1.32.a + ${libpath}/libRandv2.32.a +) + +target_compile_options(native_simulator INTERFACE + "-DNSI_PRIMARY_MCU_N=${CONFIG_NATIVE_SIMULATOR_PRIMARY_MCU_INDEX}") + +add_subdirectory(${ZEPHYR_BASE}/boards/native/common/extra_args/ + ${CMAKE_CURRENT_BINARY_DIR}/extra_args +) + +include(../common/natsim_config.cmake) diff --git a/boards/native/nrf_bsim/Kconfig b/boards/native/nrf_bsim/Kconfig new file mode 100644 index 00000000000..caed5baf8b6 --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig @@ -0,0 +1,93 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_BSIM + bool + select SOC_SERIES_BSIM_NRF52X + select SOC_COMPATIBLE_NRF52833 + select NRF_RTC_TIMER + select CLOCK_CONTROL + help + NRF52 simulation model + Will produce a console Linux process which can be executed natively. + It needs the BabbleSim simulator both in compile time and to execute + +config BOARD_NRF5340BSIM_NRF5340_CPUNET + bool + select SOC_SERIES_BSIM_NRF53X + select SOC_COMPATIBLE_NRF5340_CPUNET + select NRF_RTC_TIMER + select CLOCK_CONTROL + help + Simulated NRF53 Network core + Will produce a console Linux process which can be executed natively. + It needs the BabbleSim simulator both in compile time and to execute + +config BOARD_NRF5340BSIM_NRF5340_CPUAPP + bool + select SOC_SERIES_BSIM_NRF53X + select SOC_COMPATIBLE_NRF5340_CPUAPP + select NRF_RTC_TIMER + select CLOCK_CONTROL + help + Simulated NRF53 Application core + Will produce a console Linux process which can be executed natively. + It needs the BabbleSim simulator both in compile time and to execute + + +if SOC_SERIES_BSIM_NRFXX + +# The following file is normally parsed only for the ARM architecture, which is +# used by Nordic SoCs, so to make the symbols defined in this file available for +# the simulated nrf5x_bsim boards, which use the POSIX architecture, the file +# must be read also from here. +source "soc/nordic/common/Kconfig.peripherals" + +source "boards/native/common/extra_args/Kconfig" + +endif # SOC_SERIES_BSIM_NRFXX + + +# This would eventually be shared by a possible family of simulated NRF boards +# which use BabbleSim. When that happens, we can move this to a common +# Kconfig file + +config SOC_SERIES_BSIM_NRFXX + bool + select NATIVE_LIBRARY + select SOC_COMPATIBLE_NRF + select HAS_NRFX + select HAS_NORDIC_DRIVERS + select PINCTRL_DYNAMIC if PINCTRL + help + Any NRF simulated SOC with BabbleSim, based on the POSIX arch + +config SOC_SERIES_BSIM_NRF52X + bool + select SOC_SERIES_BSIM_NRFXX + select SOC_COMPATIBLE_NRF52X + help + Any NRF52 simulated SOC with BabbleSim, based on the POSIX arch + +config SOC_SERIES_BSIM_NRF53X + bool + select SOC_SERIES_BSIM_NRFXX + select SOC_COMPATIBLE_NRF53X + help + Any NRF53 simulated SOC with BabbleSim, based on the POSIX arch + +if BOARD_NRF5340BSIM_NRF5340_CPUAPP + +# Replica of the option provided by the BOARD_NRF5340DK_NRF5340_CPUAPP board so samples can be +# reused as is +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + +endif # BOARD_NRF5340BSIM_NRF5340_CPUNET + +if SOC_SERIES_BSIM_NRF53X + +# Let's reuse the RTC sync options so applications which use it can be reused as is +source "soc/nordic/nrf53/Kconfig.sync_rtc" + +endif # SOC_SERIES_BSIM_NRF53X diff --git a/boards/native/nrf_bsim/Kconfig.defconfig b/boards/native/nrf_bsim/Kconfig.defconfig new file mode 100644 index 00000000000..639c5d47428 --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig.defconfig @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +if SOC_SERIES_BSIM_NRFXX + +config BUILD_OUTPUT_BIN + default n + +config BUILD_OUTPUT_EXE + # When the IPC service is used, the net core image requires the application core image, as it needs + # access to its IPC buffer. Without it, the executable cannot be built. + default y if !(BOARD_NRF5340BSIM_NRF5340_CPUNET && IPC_SERVICE && (NATIVE_SIMULATOR_EXTRA_IMAGE_PATHS = "")) + +config OUTPUT_PRINT_MEMORY_USAGE + default n + +config NATIVE_SIMULATOR_NUMBER_MCUS + default 2 if BOARD_NRF5340BSIM_NRF5340_CPUNET || BOARD_NRF5340BSIM_NRF5340_CPUAPP + default 1 + +config NATIVE_SIMULATOR_MCU_N + default 1 if BOARD_NRF5340BSIM_NRF5340_CPUNET + default 0 + +config NATIVE_SIMULATOR_AUTOSTART_MCU + default y if BOARD_NRF5340BSIM_NRF5340_CPUNET + +config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX + default 1 if SOC_SERIES_BSIM_NRF53X + default 0 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 128 if !TICKLESS_KERNEL + default 32768 + +config BT_CTLR + default y if BOARD_NRF52_BSIM || BOARD_NRF5340BSIM_NRF5340_CPUNET + depends on BT + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + default 4096 if NRF_802154_SER_HOST && BOARD_NRF5340BSIM_NRF5340_CPUAPP + default 4096 if NRF_802154_SER_RADIO && BOARD_NRF5340BSIM_NRF5340_CPUNET + +if BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET + +config MBOX_NRFX_IPC + default MBOX + +endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET + +if BOARD_NRF5340BSIM_NRF5340_CPUAPP + +config IPC_SERVICE_BACKEND_RPMSG_SHMEM_RESET + default y if IPC_SERVICE_BACKEND_RPMSG + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC +endchoice + +endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP + +# The 15.4 driver Tx encryption is currently not functional with this +# simulated board => we disable it by default. With this Openthread will normally +# default to encrypt packets on its own. +config NRF_802154_ENCRYPTION + default n + +if LOG + +# For this board we can log synchronously without any problem +# Doing so will be nicer for debugging +choice LOG_MODE + default LOG_MODE_IMMEDIATE +endchoice + +endif # LOG + +if CONSOLE + +config POSIX_ARCH_CONSOLE + default y + +endif # CONSOLE + +endif # SOC_SERIES_BSIM_NRFXX diff --git a/boards/native/nrf_bsim/Kconfig.nrf52_bsim b/boards/native/nrf_bsim/Kconfig.nrf52_bsim new file mode 100644 index 00000000000..c4cc397af5b --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig.nrf52_bsim @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_BSIM + select SOC_POSIX diff --git a/boards/native/nrf_bsim/Kconfig.nrf5340bsim b/boards/native/nrf_bsim/Kconfig.nrf5340bsim new file mode 100644 index 00000000000..7847a16ab76 --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig.nrf5340bsim @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF5340BSIM + select SOC_POSIX diff --git a/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpuapp b/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpuapp new file mode 100644 index 00000000000..8e342000c3e --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpuapp @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF5340BSIM_NRF5340_CPUAPP + select SOC_POSIX diff --git a/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpunet b/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpunet new file mode 100644 index 00000000000..e6867244e77 --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpunet @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF5340BSIM_NRF5340_CPUNET + select SOC_POSIX diff --git a/boards/posix/nrf_bsim/argparse.c b/boards/native/nrf_bsim/argparse.c similarity index 100% rename from boards/posix/nrf_bsim/argparse.c rename to boards/native/nrf_bsim/argparse.c diff --git a/boards/posix/nrf_bsim/argparse.h b/boards/native/nrf_bsim/argparse.h similarity index 100% rename from boards/posix/nrf_bsim/argparse.h rename to boards/native/nrf_bsim/argparse.h diff --git a/boards/native/nrf_bsim/board.cmake b/boards/native/nrf_bsim/board.cmake new file mode 100644 index 00000000000..70a6c0f0f4d --- /dev/null +++ b/boards/native/nrf_bsim/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +set(SUPPORTED_EMU_PLATFORMS native) + +board_set_debugger_ifnset(native_gdb) +board_finalize_runner_args(native_gdb) diff --git a/boards/native/nrf_bsim/board.yml b/boards/native/nrf_bsim/board.yml new file mode 100644 index 00000000000..20c9137a233 --- /dev/null +++ b/boards/native/nrf_bsim/board.yml @@ -0,0 +1,23 @@ +boards: +- name: nrf52_bsim + vendor: zephyr + socs: + - name: native +- name: nrf5340bsim + vendor: zephyr + socs: + # Note this is referring to the real SOC yaml, but we only use its name and cpu-cluster definition + # In practice this board uses the same native SOC (SOC_POSIX) as the nrf52_bsim + - name: nrf5340 + +# These two board definitions below, together with their respective +# Kconfig.nrf5340bsim_nrf5340_cpu[app,net] exist for backwards compatibility with hwmv1 usage +# Once all their usage in tree is removed, or aliases have been introduced they can be removed. +- name: nrf5340bsim_nrf5340_cpuapp + vendor: zephyr + socs: + - name: native +- name: nrf5340bsim_nrf5340_cpunet + vendor: zephyr + socs: + - name: native diff --git a/boards/posix/nrf_bsim/board_irq.h b/boards/native/nrf_bsim/board_irq.h similarity index 100% rename from boards/posix/nrf_bsim/board_irq.h rename to boards/native/nrf_bsim/board_irq.h diff --git a/boards/posix/nrf_bsim/board_soc.h b/boards/native/nrf_bsim/board_soc.h similarity index 100% rename from boards/posix/nrf_bsim/board_soc.h rename to boards/native/nrf_bsim/board_soc.h diff --git a/boards/posix/nrf_bsim/common/README.txt b/boards/native/nrf_bsim/common/README.txt similarity index 100% rename from boards/posix/nrf_bsim/common/README.txt rename to boards/native/nrf_bsim/common/README.txt diff --git a/boards/posix/nrf_bsim/common/bsim_args_runner.c b/boards/native/nrf_bsim/common/bsim_args_runner.c similarity index 100% rename from boards/posix/nrf_bsim/common/bsim_args_runner.c rename to boards/native/nrf_bsim/common/bsim_args_runner.c diff --git a/boards/posix/nrf_bsim/common/bsim_args_runner.h b/boards/native/nrf_bsim/common/bsim_args_runner.h similarity index 100% rename from boards/posix/nrf_bsim/common/bsim_args_runner.h rename to boards/native/nrf_bsim/common/bsim_args_runner.h diff --git a/boards/posix/nrf_bsim/common/bsim_extra_cpu_if_stubs.c b/boards/native/nrf_bsim/common/bsim_extra_cpu_if_stubs.c similarity index 100% rename from boards/posix/nrf_bsim/common/bsim_extra_cpu_if_stubs.c rename to boards/native/nrf_bsim/common/bsim_extra_cpu_if_stubs.c diff --git a/boards/posix/nrf_bsim/common/bstests.h b/boards/native/nrf_bsim/common/bstests.h similarity index 100% rename from boards/posix/nrf_bsim/common/bstests.h rename to boards/native/nrf_bsim/common/bstests.h diff --git a/boards/posix/nrf_bsim/common/bstests_entry.c b/boards/native/nrf_bsim/common/bstests_entry.c similarity index 100% rename from boards/posix/nrf_bsim/common/bstests_entry.c rename to boards/native/nrf_bsim/common/bstests_entry.c diff --git a/boards/posix/nrf_bsim/common/cmdline.h b/boards/native/nrf_bsim/common/cmdline.h similarity index 100% rename from boards/posix/nrf_bsim/common/cmdline.h rename to boards/native/nrf_bsim/common/cmdline.h diff --git a/boards/posix/nrf_bsim/common/cmsis/cmsis.c b/boards/native/nrf_bsim/common/cmsis/cmsis.c similarity index 100% rename from boards/posix/nrf_bsim/common/cmsis/cmsis.c rename to boards/native/nrf_bsim/common/cmsis/cmsis.c diff --git a/boards/posix/nrf_bsim/common/cmsis/cmsis.h b/boards/native/nrf_bsim/common/cmsis/cmsis.h similarity index 100% rename from boards/posix/nrf_bsim/common/cmsis/cmsis.h rename to boards/native/nrf_bsim/common/cmsis/cmsis.h diff --git a/boards/posix/nrf_bsim/common/cmsis/cmsis_compiler.h b/boards/native/nrf_bsim/common/cmsis/cmsis_compiler.h similarity index 100% rename from boards/posix/nrf_bsim/common/cmsis/cmsis_compiler.h rename to boards/native/nrf_bsim/common/cmsis/cmsis_compiler.h diff --git a/boards/posix/nrf_bsim/common/cmsis/cmsis_instr.h b/boards/native/nrf_bsim/common/cmsis/cmsis_instr.h similarity index 100% rename from boards/posix/nrf_bsim/common/cmsis/cmsis_instr.h rename to boards/native/nrf_bsim/common/cmsis/cmsis_instr.h diff --git a/boards/posix/nrf_bsim/common/phy_sync_ctrl.c b/boards/native/nrf_bsim/common/phy_sync_ctrl.c similarity index 100% rename from boards/posix/nrf_bsim/common/phy_sync_ctrl.c rename to boards/native/nrf_bsim/common/phy_sync_ctrl.c diff --git a/boards/posix/nrf_bsim/common/phy_sync_ctrl.h b/boards/native/nrf_bsim/common/phy_sync_ctrl.h similarity index 100% rename from boards/posix/nrf_bsim/common/phy_sync_ctrl.h rename to boards/native/nrf_bsim/common/phy_sync_ctrl.h diff --git a/boards/posix/nrf_bsim/common/posix_arch_if.c b/boards/native/nrf_bsim/common/posix_arch_if.c similarity index 100% rename from boards/posix/nrf_bsim/common/posix_arch_if.c rename to boards/native/nrf_bsim/common/posix_arch_if.c diff --git a/boards/posix/nrf_bsim/common/runner_hooks.c b/boards/native/nrf_bsim/common/runner_hooks.c similarity index 100% rename from boards/posix/nrf_bsim/common/runner_hooks.c rename to boards/native/nrf_bsim/common/runner_hooks.c diff --git a/boards/posix/nrf_bsim/common/trace_hook.c b/boards/native/nrf_bsim/common/trace_hook.c similarity index 100% rename from boards/posix/nrf_bsim/common/trace_hook.c rename to boards/native/nrf_bsim/common/trace_hook.c diff --git a/boards/posix/nrf_bsim/cpu_wait.c b/boards/native/nrf_bsim/cpu_wait.c similarity index 100% rename from boards/posix/nrf_bsim/cpu_wait.c rename to boards/native/nrf_bsim/cpu_wait.c diff --git a/boards/posix/nrf_bsim/doc/nrf52_bsim.rst b/boards/native/nrf_bsim/doc/nrf52_bsim.rst similarity index 100% rename from boards/posix/nrf_bsim/doc/nrf52_bsim.rst rename to boards/native/nrf_bsim/doc/nrf52_bsim.rst diff --git a/boards/posix/nrf_bsim/doc/nrf5340bsim.rst b/boards/native/nrf_bsim/doc/nrf5340bsim.rst similarity index 100% rename from boards/posix/nrf_bsim/doc/nrf5340bsim.rst rename to boards/native/nrf_bsim/doc/nrf5340bsim.rst diff --git a/boards/posix/nrf_bsim/ipc_backend.c b/boards/native/nrf_bsim/ipc_backend.c similarity index 100% rename from boards/posix/nrf_bsim/ipc_backend.c rename to boards/native/nrf_bsim/ipc_backend.c diff --git a/boards/posix/nrf_bsim/irq_handler.c b/boards/native/nrf_bsim/irq_handler.c similarity index 100% rename from boards/posix/nrf_bsim/irq_handler.c rename to boards/native/nrf_bsim/irq_handler.c diff --git a/boards/posix/nrf_bsim/nrf52_bsim.dts b/boards/native/nrf_bsim/nrf52_bsim.dts similarity index 96% rename from boards/posix/nrf_bsim/nrf52_bsim.dts rename to boards/native/nrf_bsim/nrf52_bsim.dts index 8410c80fb74..d591c7920c6 100644 --- a/boards/posix/nrf_bsim/nrf52_bsim.dts +++ b/boards/native/nrf_bsim/nrf52_bsim.dts @@ -10,7 +10,7 @@ #include #include /* We resuse the pinctrl definitions directly from the real board : */ -#include <../boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833-pinctrl.dtsi> +#include <../boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi> / { model = "nrf52 bsim"; diff --git a/boards/posix/nrf_bsim/nrf52_bsim.yaml b/boards/native/nrf_bsim/nrf52_bsim.yaml similarity index 100% rename from boards/posix/nrf_bsim/nrf52_bsim.yaml rename to boards/native/nrf_bsim/nrf52_bsim.yaml diff --git a/boards/native/nrf_bsim/nrf52_bsim_defconfig b/boards/native/nrf_bsim/nrf52_bsim_defconfig new file mode 100644 index 00000000000..0559b646712 --- /dev/null +++ b/boards/native/nrf_bsim/nrf52_bsim_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_NO_OPTIMIZATIONS=y +CONFIG_LOG_BACKEND_UART=n diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts similarity index 97% rename from boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts rename to boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts index 72194f3b0e1..aa1f235e16e 100644 --- a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts @@ -115,4 +115,4 @@ /* We re-use the IPC shared buffer definition from the real HW. But note the start address of the * buffer won't be used. */ -#include <../boards/arm/nrf5340dk_nrf5340/nrf5340_shared_sram_planning_conf.dtsi> +#include <../boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi> diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml similarity index 100% rename from boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml rename to boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000..83aba50dc57 --- /dev/null +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +CONFIG_CONSOLE=y +CONFIG_NO_OPTIMIZATIONS=y diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts similarity index 95% rename from boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts rename to boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts index 93e3ee27163..7553a2cfc55 100644 --- a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts @@ -77,4 +77,4 @@ /* We re-use the IPC shared buffer definition from the real HW. But note the start address of the * buffer won't be used. */ -#include <../boards/arm/nrf5340dk_nrf5340/nrf5340_shared_sram_planning_conf.dtsi> +#include <../boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi> diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml similarity index 100% rename from boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml rename to boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..83aba50dc57 --- /dev/null +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +CONFIG_CONSOLE=y +CONFIG_NO_OPTIMIZATIONS=y diff --git a/boards/posix/nrf_bsim/nsi_if.c b/boards/native/nrf_bsim/nsi_if.c similarity index 100% rename from boards/posix/nrf_bsim/nsi_if.c rename to boards/native/nrf_bsim/nsi_if.c diff --git a/boards/arm/nrf52840_mdk_usb_dongle/pre_dt_board.cmake b/boards/native/nrf_bsim/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/pre_dt_board.cmake rename to boards/native/nrf_bsim/pre_dt_board.cmake diff --git a/boards/posix/nrf_bsim/soc/nrfx_coredep.c b/boards/native/nrf_bsim/soc/nrfx_coredep.c similarity index 100% rename from boards/posix/nrf_bsim/soc/nrfx_coredep.c rename to boards/native/nrf_bsim/soc/nrfx_coredep.c diff --git a/boards/native/nrf_bsim/soc/pinctrl_soc.h b/boards/native/nrf_bsim/soc/pinctrl_soc.h new file mode 100644 index 00000000000..b5d9981a35e --- /dev/null +++ b/boards/native/nrf_bsim/soc/pinctrl_soc.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H +#define BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H + +/* We reuse the real SOC's header: */ +#include "../soc/nordic/common/pinctrl_soc.h" + +#endif /* BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H */ diff --git a/boards/posix/nrf_bsim/soc/soc_nrf_common.h b/boards/native/nrf_bsim/soc/soc_nrf_common.h similarity index 83% rename from boards/posix/nrf_bsim/soc/soc_nrf_common.h rename to boards/native/nrf_bsim/soc/soc_nrf_common.h index a77778de653..a835f2f2fc0 100644 --- a/boards/posix/nrf_bsim/soc/soc_nrf_common.h +++ b/boards/native/nrf_bsim/soc/soc_nrf_common.h @@ -8,6 +8,6 @@ #define BOARDS_POSIX_NRF_BSIM_SOC_SOC_NRF_COMMON_H /* We reuse the real SOC's header: */ -#include "../soc/arm/nordic_nrf/common/soc_nrf_common.h" +#include "../soc/nordic/common/soc_nrf_common.h" #endif /* BOARDS_POSIX_NRF_BSIM_SOC_SOC_NRF_COMMON_H */ diff --git a/boards/posix/nrf_bsim/soc/soc_secure.h b/boards/native/nrf_bsim/soc/soc_secure.h similarity index 87% rename from boards/posix/nrf_bsim/soc/soc_secure.h rename to boards/native/nrf_bsim/soc/soc_secure.h index 667823334d0..a39c02435a8 100644 --- a/boards/posix/nrf_bsim/soc/soc_secure.h +++ b/boards/native/nrf_bsim/soc/soc_secure.h @@ -5,7 +5,7 @@ */ /* - * Replacement for Nordic's nrf soc/arm/nordic_nrf/common/soc_secure.h + * Replacement for Nordic's nrf soc/nordic/common/soc_secure.h */ #ifndef BOARDS_POSIX_NRF52_BSIM_SOC_SECURE_H #define BOARDS_POSIX_NRF52_BSIM_SOC_SECURE_H diff --git a/boards/posix/nrf_bsim/time_machine.h b/boards/native/nrf_bsim/time_machine.h similarity index 100% rename from boards/posix/nrf_bsim/time_machine.h rename to boards/native/nrf_bsim/time_machine.h diff --git a/boards/nios2/altera_max10/Kconfig.board b/boards/nios2/altera_max10/Kconfig.board deleted file mode 100644 index 90f467915bd..00000000000 --- a/boards/nios2/altera_max10/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ALTERA_MAX10 - bool "Altera MAX10 Board" - depends on SOC_NIOS2F_ZEPHYR diff --git a/boards/nios2/altera_max10/Kconfig.defconfig b/boards/nios2/altera_max10/Kconfig.defconfig deleted file mode 100644 index a2ca4d47bf9..00000000000 --- a/boards/nios2/altera_max10/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ALTERA_MAX10 - -config BOARD - default "altera_max10" - -if FLASH - -config SOC_FLASH_NIOS2_QSPI - default y - -if SOC_FLASH_NIOS2_QSPI - -if DISK_DRIVER_FLASH - -endif # DISK_DRIVER_FLASH - -endif # SOC_FLASH_NIOS2_QSPI - -endif # FLASH - -endif # BOARD_ALTERA_MAX10 diff --git a/boards/nios2/altera_max10/altera_max10_defconfig b/boards/nios2/altera_max10/altera_max10_defconfig deleted file mode 100644 index 925abcca34c..00000000000 --- a/boards/nios2/altera_max10/altera_max10_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NIOS2F_ZEPHYR=y -CONFIG_BOARD_ALTERA_MAX10=y -CONFIG_HAS_ALTERA_HAL=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/nios2/altera_max10/doc/index.rst b/boards/nios2/altera_max10/doc/index.rst deleted file mode 100644 index db4daf5256a..00000000000 --- a/boards/nios2/altera_max10/doc/index.rst +++ /dev/null @@ -1,332 +0,0 @@ -.. _altera_max10: - -Altera MAX10 -############ - -Overview -******** - - -The Zephyr kernel is supported on the Altera MAX10 Rev C development kit, using -the Nios II Gen 2 soft CPU. - -.. figure:: img/altera_max10.jpg - :align: center - :alt: Altera's MAX* 10 - - Altera's MAX* 10 (Credit: Altera) - -Hardware -******** - -DIP Switch settings -=================== - -There are two sets of switches on the back of the board. Of particular -importance is SW2: - -* Switch 2 (CONFIG_SEL) should be in the OFF (up) position so that the first - boot image is CFM0 -* Switch 3 (VTAP_BYPASS) needs to be in the ON (down) position or the flashing - scripts won't work -* Switch 4 (HSMC_BYPASSN) should be OFF (up) - -.. image:: img/Altera_MAX10_switches.jpg - :align: center - :alt: Altera's MAX* 10 Switches - -Other switches are user switches, their position is application-specific. - -Necessary Software -================== - -You will need the Altera Quartus SDK in order to work with this device. The -`Altera Lite Distribution`_ of Quartus may be obtained without -charge. - -For your convenience using the SDK tools (such as ``nios2-configure-sof``), -you should put the binaries provided by the SDK -in your path. Below is an example, adjust ALTERA_BASE to where you installed the -SDK: - -.. code-block:: console - - export ALTERA_BASE=/opt/altera_lite/16.0 - export PATH=$PATH:$ALTERA_BASE/quartus/bin:$ALTERA_BASE/nios2eds/bin - -You may need to adjust your udev rules so that you can talk to the USB Blaster -II peripheral, which is the built-in JTAG interface for this device. - -The following works for Fedora 23: - -.. code-block:: console - - # For Altera USB-Blaster permissions. - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6010",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6810",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - -You can test connectivity with the SDK jtagconfig tool, you should see something -like: - -.. code-block:: console - - $ jtagconfig - 1) USB-BlasterII [1-1.2] - 031050DD 10M50DA(.|ES)/10M50DC - 020D10DD VTAP10 - - -Reference CPU -============= - -A reference CPU design of a Nios II/f core is included in the Zephyr tree -in the :zephyr_file:`soc/nios2/nios2f-zephyr/cpu` directory. - -Flash this CPU using the ``nios2-configure-sof`` SDK tool with the FPGA -configuration file -:zephyr_file:`soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof`: - -.. code-block:: console - - $ nios2-configure-sof ghrd_10m50da.sof - -This CPU is a Nios II/F core with a 16550 UART, JTAG UART, and the Avalon Timer. -For any Nios II SOC definition, you can find out more details about the CPU -configuration by inspecting system.h in the SOC's include directory. - -Console Output -============== - -16550 UART ----------- - -By default, the kernel is configured to send console output to the 16550 UART. -You can monitor this on your workstation by connecting to the top right mini USB -port on the board (it will show up in /dev as a ttyUSB node), and then running -minicom with flow control disabled, 115200-8N1 settings. - -JTAG UART ---------- - -You can also have it send its console output to the JTAG UART. -Enable ``jtag_uart`` node in :file:`altera_max10.dts` or overlay file: - -.. code-block:: devicetree - - &jtag_uart { - status = "okay"; - current-speed = <115200>; - }; - -To view these messages on your local workstation, run the terminal application -in the SDK: - -.. code-block:: console - - $ nios2-terminal - -Programming and Debugging -************************* - -Flashing -======== - -Flashing Kernel into UFM ------------------------- - -The usual ``flash`` target will work with the ``altera_max10`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: altera_max10 - :goals: flash - -Refer to :ref:`build_an_application` and :ref:`application_run` for -more details. - -This provisions the Zephyr kernel and the CPU configuration onto the board, -using the scripts/support/quartus-flash.py script. After it completes the kernel -will immediately boot. - - -Flashing Kernel directly into RAM over JTAG -------------------------------------------- - -The SDK included the nios2-download tool which will let you flash a kernel -directly into RAM and then boot it from the __start symbol. - -In order for this to work, your entire kernel must be located in RAM. Make sure -the following config options are disabled: - -.. code-block:: console - - CONFIG_XIP=n - CONFIG_INCLUDE_RESET_VECTOR=n - -Then, after building your kernel, push it into device's RAM by running -this from the build directory: - -.. code-block:: console - - $ nios2-download --go zephyr/zephyr.elf - -If you have a console session running (either minicom or nios2-terminal) you -should see the application's output. There are additional arguments you can pass -to nios2-download so that it spawns a GDB server that you can connect to, -although it's typically simpler to just use nios2-gdb-server as described below. - -Debugging -========= - -The Altera SDK includes a GDB server which can be used to debug a MAX10 board. -You can either debug a running image that was flashed onto the device in User -Flash Memory (UFM), or load an image over the JTAG using GDB. - -Debugging With UFM Flashed Image --------------------------------- - -You can debug an application in the usual way. Here is an example. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: altera_max10 - :goals: debug - -You will see output similar to the following: - -.. code-block:: console - - Nios II GDB server running on port 3335 - Ignoring --stop option because --tcpport also specified - GNU gdb (GDB) 7.11.0.20160511-git - Copyright (C) 2016 Free Software Foundation, Inc. - License GPLv3+: GNU GPL version 3 or later - This is free software: you are free to change and redistribute it. - There is NO WARRANTY, to the extent permitted by law. Type "show copying" - and "show warranty" for details. - This GDB was configured as "--host=x86_64-pokysdk-linux --target=nios2-zephyr-elf". - Type "show configuration" for configuration details. - For bug reporting instructions, please see: - . - Find the GDB manual and other documentation resources online at: - . - For help, type "help". - Type "apropos word" to search for commands related to "word"... - Reading symbols from /projects/zephyr/samples/hello_world/build/zephyr/zephyr.elf...done. - Remote debugging using :3335 - Using cable "USB-BlasterII [3-1.3]", device 1, instance 0x00 - Resetting and pausing target processor: OK - Listening on port 3335 for connection from GDB: accepted - isr_tables_syms () at /projects/zephyr/arch/common/isr_tables.c:63 - 63 GEN_ABSOLUTE_SYM(__ISR_LIST_SIZEOF, sizeof(struct _isr_list)); - (gdb) b z_prep_c - Breakpoint 1 at 0xdf0: file /projects/zephyr/arch/nios2/core/prep_c.c, line 36. - (gdb) b z_cstart - Breakpoint 2 at 0x1254: file /projects/zephyr/kernel/init.c, line 348. - (gdb) c - Continuing. - - Breakpoint 2, z_cstart () at /projects/zephyr/kernel/init.c:348 - 348 { - (gdb) - -To start debugging manually: - - -.. code-block:: console - - nios2-gdb-server --tcpport 1234 --stop --reset-target - -And then connect with GDB from the build directory: - - -.. code-block:: console - - nios2-poky-elf-gdb zephyr/zephyr.elf -ex "target remote :1234" - -Debugging With JTAG Flashed Image ---------------------------------- - -In order for this to work, execute-in-place must be disabled, since the GDB -'load' command can only put text and data in RAM. Ensure this is in your -configuration: - -.. code-block:: console - - CONFIG_XIP=n - -It is OK for this procedure to leave the reset vector enabled, unlike -nios2-download (which errors out if it finds sections outside of SRAM) it will -be ignored. - -In a terminal, launch the nios2 GDB server. It doesn't matter what kernel (if -any) is on the device, but you should have at least flashed a CPU using -nios2-configure-sof. You can leave this process running. - -.. code-block:: console - - $ nios2-gdb-server --tcpport 1234 --tcppersist --init-cache --reset-target - -Build your Zephyr kernel, and load it into a GDB built for Nios II (included in -the Zephyr SDK) from the build directory: - -.. code-block:: console - - $ nios2-poky-elf-gdb zephyr/zephyr.elf - -Then connect to the GDB server: - -.. code-block:: console - - (gdb) target remote :1234 - -And then load the kernel image over the wire. The CPU will not start from the -reset vector, instead it will boot from the __start symbol: - - -.. code-block:: console - - (gdb) load - Loading section reset, size 0xc lma 0x0 - Loading section exceptions, size 0x1b0 lma 0x400020 - Loading section text, size 0x8df0 lma 0x4001d0 - Loading section devconfig, size 0x30 lma 0x408fc0 - Loading section rodata, size 0x3f4 lma 0x408ff0 - Loading section datas, size 0x888 lma 0x4093e4 - Loading section initlevel, size 0x30 lma 0x409c6c - Loading section _k_task_list, size 0x58 lma 0x409c9c - Loading section _k_task_ptr, size 0x8 lma 0x409cf4 - Loading section _k_event_list, size 0x10 lma 0x409cfc - Start address 0x408f54, load size 40184 - Transfer rate: 417 KB/sec, 368 bytes/write. - After this is done you may set breakpoints and continue execution. If you ever want to reset the CPU, issue the 'load' command again. - - - -References -********** - -* `CPU Documentation `_ -* `Nios II Processor Booting Methods in MAX 10 FPGA Devices `_ -* `Embedded Peripherals IP User Guide `_ -* `MAX 10 FPGA Configuration User Guide `_ -* `MAX 10 FPGA Development Kit User Guide `_ -* `Nios II Command-Line Tools `_ -* `Quartus II Scripting Reference Manual `_ - - -.. _Altera Lite Distribution: https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html diff --git a/boards/nios2/index.rst b/boards/nios2/index.rst deleted file mode 100644 index 61c352619ad..00000000000 --- a/boards/nios2/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-nios2: - -Nios II Boards -############## - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/nios2/qemu_nios2/Kconfig.board b/boards/nios2/qemu_nios2/Kconfig.board deleted file mode 100644 index de59ab26b4a..00000000000 --- a/boards/nios2/qemu_nios2/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_NIOS2 - bool "QEMU NIOS II target" - depends on SOC_NIOS2_QEMU - select QEMU_TARGET diff --git a/boards/nios2/qemu_nios2/Kconfig.defconfig b/boards/nios2/qemu_nios2/Kconfig.defconfig deleted file mode 100644 index b550e80e0f6..00000000000 --- a/boards/nios2/qemu_nios2/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_NIOS2 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_nios2" - -endif diff --git a/boards/nios2/qemu_nios2/board.cmake b/boards/nios2/qemu_nios2/board.cmake deleted file mode 100644 index d4cd0427b36..00000000000 --- a/boards/nios2/qemu_nios2/board.cmake +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_CPU_TYPE_${ARCH} nios2) - -set(QEMU_FLAGS_${ARCH} - -machine altera_10m50_zephyr - -nographic - ) - -board_set_debugger_ifnset(qemu) diff --git a/boards/nordic/index.rst b/boards/nordic/index.rst new file mode 100644 index 00000000000..69e38ab15ca --- /dev/null +++ b/boards/nordic/index.rst @@ -0,0 +1,10 @@ +.. _boards-nordic: + +Nordic Semiconductor +#################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/nordic/nrf21540dk/Kconfig b/boards/nordic/nrf21540dk/Kconfig new file mode 100644 index 00000000000..522eb6e44dd --- /dev/null +++ b/boards/nordic/nrf21540dk/Kconfig @@ -0,0 +1,10 @@ +# nRF21540 DK NRF52840 board configuration + +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_NRF21540DK diff --git a/boards/nordic/nrf21540dk/Kconfig.defconfig b/boards/nordic/nrf21540dk/Kconfig.defconfig new file mode 100644 index 00000000000..28a3f3e2c98 --- /dev/null +++ b/boards/nordic/nrf21540dk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF21540 DK NRF52840 board configuration + +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF21540DK + +config BT_CTLR + default BT + +endif # BOARD_NRF21540DK diff --git a/boards/nordic/nrf21540dk/Kconfig.nrf21540dk b/boards/nordic/nrf21540dk/Kconfig.nrf21540dk new file mode 100644 index 00000000000..858fc460505 --- /dev/null +++ b/boards/nordic/nrf21540dk/Kconfig.nrf21540dk @@ -0,0 +1,7 @@ +# nRF21540 DK NRF52840 board configuration + +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF21540DK + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf21540dk_nrf52840/board.cmake b/boards/nordic/nrf21540dk/board.cmake similarity index 100% rename from boards/arm/nrf21540dk_nrf52840/board.cmake rename to boards/nordic/nrf21540dk/board.cmake diff --git a/boards/nordic/nrf21540dk/board.yml b/boards/nordic/nrf21540dk/board.yml new file mode 100644 index 00000000000..4c9cf5943fe --- /dev/null +++ b/boards/nordic/nrf21540dk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf21540dk + vendor: nordic + socs: + - name: nrf52840 diff --git a/boards/arm/nrf21540dk_nrf52840/doc/img/nrf21540dk_nrf52840.jpg b/boards/nordic/nrf21540dk/doc/img/nrf21540dk_nrf52840.jpg similarity index 100% rename from boards/arm/nrf21540dk_nrf52840/doc/img/nrf21540dk_nrf52840.jpg rename to boards/nordic/nrf21540dk/doc/img/nrf21540dk_nrf52840.jpg diff --git a/boards/nordic/nrf21540dk/doc/index.rst b/boards/nordic/nrf21540dk/doc/index.rst new file mode 100644 index 00000000000..fdc72605636 --- /dev/null +++ b/boards/nordic/nrf21540dk/doc/index.rst @@ -0,0 +1,236 @@ +.. _nrf21540dk_nrf52840: + +nRF21540 DK +########### + +Overview +******** +The nRF21540 DK (PCA10112) shows possibility of the Nordic Semiconductor +nRF21540 Front End Module connected with nRF52840 ARM Cortex-M4F CPU. +The CPU provides support for the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf21540dk_nrf52840.jpg + :align: center + :alt: nRF21540 DK + + nRF21540 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the `nRF21540 website`_. +The `Nordic Semiconductor Infocenter`_ contains the processor's and front end +module's information and the datasheet. + +Hardware +******** + +The nRF52840 on the nRF21540 DK has two external oscillators. The frequency +of the slow clock is 32.768 kHz. The frequency of the main clock is 32 MHz. + +Supported Features +================== + +The nrf21540dk/nrf52840 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF52840 Product Specification`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF21540 Development Kit board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (green) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +Front End Module +---------------- + +* MOSI = P1.13 +* MISO = P1.14 +* CLOCK = P1.15 +* CHIP SELECT = P0.21 +* PDN = P0.23 +* MODE = P0.17 +* RXEN = P0.19 +* ANTSEL = P0.20 +* TXEN = P0.22 + +Programming and Debugging +************************* + +Applications for the ``nrf21540dk/nrf52840`` board configuration can be built, +flashed, and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF21540 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf21540dk/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF21540 DK +*********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts`. + +Changing UART1 pins +******************* + +The following approach can be used when an application needs to use another set +of pins for UART1: + +1. Add devicetree overlay file to the main directory of your application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default_alt: uart1_default_alt { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep_alt: uart1_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + pinctrl-0 = <&uart1_default_alt>; + /* if sleep state is not used, use /delete-property/ pinctrl-1; and + * skip the "sleep" entry. + */ + pinctrl-1 = <&uart1_sleep_alt>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX + +See :ref:`set-devicetree-overlays` for further details. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the `nRF52840 Product Specification`_, chapter 7 'Hardware and Layout'. +In the table 7.1.1 'aQFN73 ball assignments' select the pins marked +'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used +in under-10KHz applications. They are not suitable for 115200 speed of UART. + +References +********** + +.. target-notes:: + +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _nRF21540 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF21540 +.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf +.. _nRF21540 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF21540_PS_v1.0.pdf diff --git a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840-pinctrl.dtsi rename to boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi diff --git a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.dts b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts similarity index 100% rename from boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.dts rename to boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts diff --git a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.yaml b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml similarity index 90% rename from boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.yaml rename to boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml index 985dba241e1..a1bcc36e034 100644 --- a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.yaml +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: nrf21540dk_nrf52840 +identifier: nrf21540dk/nrf52840 name: nRF21540-DK-NRF52840 type: mcu arch: arm diff --git a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840_defconfig b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig similarity index 76% rename from boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840_defconfig rename to boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig index fecb5052471..8daa29dc473 100644 --- a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840_defconfig +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF21540DK_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52840_papyr/pre_dt_board.cmake b/boards/nordic/nrf21540dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840_papyr/pre_dt_board.cmake rename to boards/nordic/nrf21540dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf51dk/Kconfig.defconfig b/boards/nordic/nrf51dk/Kconfig.defconfig new file mode 100644 index 00000000000..ae8e85130f3 --- /dev/null +++ b/boards/nordic/nrf51dk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF51 DK NRF51822 board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF51DK_NRF51822 + +config BT_CTLR + default BT + +endif # BOARD_NRF51DK_NRF51822 diff --git a/boards/nordic/nrf51dk/Kconfig.nrf51dk b/boards/nordic/nrf51dk/Kconfig.nrf51dk new file mode 100644 index 00000000000..51802271197 --- /dev/null +++ b/boards/nordic/nrf51dk/Kconfig.nrf51dk @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF51DK + select SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51dk_nrf51422/board.cmake b/boards/nordic/nrf51dk/board.cmake similarity index 100% rename from boards/arm/nrf51dk_nrf51422/board.cmake rename to boards/nordic/nrf51dk/board.cmake diff --git a/boards/nordic/nrf51dk/board.yml b/boards/nordic/nrf51dk/board.yml new file mode 100644 index 00000000000..788be3d79bc --- /dev/null +++ b/boards/nordic/nrf51dk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf51dk + vendor: nordic + socs: + - name: nrf51822 diff --git a/boards/arm/nrf51dk_nrf51422/doc/img/nrf51dk_nrf51422.jpg b/boards/nordic/nrf51dk/doc/img/nrf51dk_nrf51822.jpg similarity index 100% rename from boards/arm/nrf51dk_nrf51422/doc/img/nrf51dk_nrf51422.jpg rename to boards/nordic/nrf51dk/doc/img/nrf51dk_nrf51822.jpg diff --git a/boards/nordic/nrf51dk/doc/index.rst b/boards/nordic/nrf51dk/doc/index.rst new file mode 100644 index 00000000000..b97e70e9613 --- /dev/null +++ b/boards/nordic/nrf51dk/doc/index.rst @@ -0,0 +1,159 @@ +.. _nrf51dk_nrf51422: + +nRF51 DK +######## + +Overview +******** + +The nRF51 Development Kit (PCA10028) hardware provides support for the Nordic +Semiconductor nRF51822 ARM Cortex-M0 CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf51dk_nrf51822.jpg + :align: center + :alt: nRF51 DK + + nRF51 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the +`nRF51 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF51 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 16 MHz. + +Supported Features +================== + +The nrf51dk/nrf51822 board configuration supports the following nRF51 +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF51 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF51 Development Kit board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.21 +* LED2 (green) = P0.22 +* LED3 (green) = P0.23 +* LED4 (green) = P0.24 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.17 +* BUTTON2 = SW2 = P0.18 +* BUTTON3 = SW3 = P0.19 +* BUTTON4 = SW4 = P0.20 +* BOOT = SW5 = boot/reset + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF51 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf51dk/nrf51822 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF51 DK +******************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf51dk/nrf51dk_nrf51822.dts`. + +References +********** + +.. target-notes:: + +.. _nRF51 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF51-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422-pinctrl.dtsi b/boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422-pinctrl.dtsi rename to boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi diff --git a/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts b/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts new file mode 100644 index 00000000000..15e74d15f40 --- /dev/null +++ b/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf51dk_nrf51822-pinctrl.dtsi" +#include + +/ { + model = "Nordic nRF51 DK NRF51822"; + compatible = "nordic,nrf51-dk-nrf51822"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + label = "Green LED 0"; + }; + led1: led_1 { + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + label = "Green LED 1"; + }; + led2: led_2 { + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + label = "Green LED 2"; + }; + led3: led_3 { + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 17 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button2: button_2 { + gpios = <&gpio0 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + button3: button_3 { + gpios = <&gpio0 20 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 3"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + pwm-led0 = &pwm_led0; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + bootloader-led0 = &led0; + mcuboot-button0 = &button0; + mcuboot-led0 = &led0; + watchdog0 = &wdt0; + }; +}; + +&sw_pwm { + status ="okay"; + channel-gpios = <&gpio0 21 PWM_POLARITY_INVERTED>; + clock-prescaler = <8>; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c1 { + /* Cannot be used together with spi1. */ + /* status = "okay"; */ + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi0 { + /* Cannot be used together with i2c0. */ + /* status = "okay"; */ + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi1 { + compatible = "nordic,nrf-spi"; + status = "okay"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x8000>; + }; + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x00008000 0x1b000>; + }; + slot1_partition: partition@23000 { + label = "image-1"; + reg = <0x00023000 0x1b000>; + }; + storage_partition: partition@3e000 { + label = "storage"; + reg = <0x0003e000 0x00002000>; + }; + }; +}; diff --git a/boards/nordic/nrf51dk/nrf51dk_nrf51822.yaml b/boards/nordic/nrf51dk/nrf51dk_nrf51822.yaml new file mode 100644 index 00000000000..e3aab4cbf85 --- /dev/null +++ b/boards/nordic/nrf51dk/nrf51dk_nrf51822.yaml @@ -0,0 +1,24 @@ +identifier: nrf51dk/nrf51822 +name: nRF51-DK-NRF51822 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32 +flash: 256 +supported: + - adc + - ble + - counter + - gpio + - i2c + - nvs + - pwm + - spi + - watchdog +testing: + ignore_tags: + - net +vendor: nordic diff --git a/boards/nordic/nrf51dk/nrf51dk_nrf51822_defconfig b/boards/nordic/nrf51dk/nrf51dk_nrf51822_defconfig new file mode 100644 index 00000000000..1289685e1e8 --- /dev/null +++ b/boards/nordic/nrf51dk/nrf51dk_nrf51822_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51_ble400/pre_dt_board.cmake b/boards/nordic/nrf51dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf51_ble400/pre_dt_board.cmake rename to boards/nordic/nrf51dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf51dongle/Kconfig.defconfig b/boards/nordic/nrf51dongle/Kconfig.defconfig new file mode 100644 index 00000000000..fed53a7a316 --- /dev/null +++ b/boards/nordic/nrf51dongle/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF51 Dongle NRF51822 board configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF51DONGLE + +config BT_CTLR + default BT + +endif # BOARD_NRF51DONGLE diff --git a/boards/nordic/nrf51dongle/Kconfig.nrf51dongle b/boards/nordic/nrf51dongle/Kconfig.nrf51dongle new file mode 100644 index 00000000000..a13b3e208be --- /dev/null +++ b/boards/nordic/nrf51dongle/Kconfig.nrf51dongle @@ -0,0 +1,7 @@ +# nRF51 Dongle NRF51822 board configuration + +# Copyright (c) 2018 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF51DONGLE + select SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51dongle_nrf51422/board.cmake b/boards/nordic/nrf51dongle/board.cmake similarity index 100% rename from boards/arm/nrf51dongle_nrf51422/board.cmake rename to boards/nordic/nrf51dongle/board.cmake diff --git a/boards/nordic/nrf51dongle/board.yml b/boards/nordic/nrf51dongle/board.yml new file mode 100644 index 00000000000..4c89cac7fdc --- /dev/null +++ b/boards/nordic/nrf51dongle/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf51dongle + vendor: nordic + socs: + - name: nrf51822 diff --git a/boards/arm/nrf51dongle_nrf51422/doc/img/nrf51dongle_nrf51422.jpg b/boards/nordic/nrf51dongle/doc/img/nrf51dongle_nrf51822.jpg similarity index 100% rename from boards/arm/nrf51dongle_nrf51422/doc/img/nrf51dongle_nrf51422.jpg rename to boards/nordic/nrf51dongle/doc/img/nrf51dongle_nrf51822.jpg diff --git a/boards/nordic/nrf51dongle/doc/index.rst b/boards/nordic/nrf51dongle/doc/index.rst new file mode 100644 index 00000000000..720ff3a5986 --- /dev/null +++ b/boards/nordic/nrf51dongle/doc/index.rst @@ -0,0 +1,144 @@ +.. _nrf51dongle_nrf51422: + +nRF51 Dongle +############ + +Overview +******** + +The nRF51 Dongle (PCA10031) hardware provides support for the Nordic +Semiconductor nRF51822 ARM Cortex-M0 CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf51dongle_nrf51822.jpg + :align: center + :alt: nRF51 Dongle + + nRF51 Dongle (Credit: Nordic Semiconductor) + +More information about the board can be found at the +`nRF51 Dongle website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF51 Dongle has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 16 MHz. + +Supported Features +================== + +The nrf51dongle/nrf51822 board configuration supports the following nRF51 +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF51 Dongle website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF51 Dongle hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.21 +* LED1 (green) = P0.22 +* LED1 (blue) = P0.23 + +Push buttons +------------ + +* BOOT = SW1 = boot/reset + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF51 Dongle +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf51dongle/nrf51822 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +Testing the LEDs on the nRF51 Dongle +************************************ + +Build and flash the :zephyr:code-sample:`blinky` sample to test that the onboard LED +is working properly with Zephyr. + +References +********** + +.. target-notes:: + +.. _nRF51 Dongle website: http://www.nordicsemi.com/eng/Products/nRF51-Dongle +.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/nrf51_blenano/nrf51_blenano-pinctrl.dtsi b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf51_blenano/nrf51_blenano-pinctrl.dtsi rename to boards/nordic/nrf51dongle/nrf51dongle_nrf51822-pinctrl.dtsi diff --git a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.dts b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.dts new file mode 100644 index 00000000000..746b2ca767c --- /dev/null +++ b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.dts @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf51dongle_nrf51822-pinctrl.dtsi" + +/ { + model = "Nordic nRF51 Dongle NRF51822"; + compatible = "nordic,nrf51-dongle-nrf51822"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + led0_red: led_0 { + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + label = "Red LED 0"; + }; + led0_green: led_1 { + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + label = "Green LED 0"; + }; + led0_blue: led_2 { + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + label = "Blue LED 0"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0_red; + led1 = &led0_green; + led2 = &led0_blue; + pwm-led0 = &pwm_led0; + watchdog0 = &wdt0; + }; +}; + +&sw_pwm { + status ="okay"; + channel-gpios = <&gpio0 21 PWM_POLARITY_INVERTED>; + clock-prescaler = <8>; +}; + +&gpiote { + status ="okay"; +}; + +&gpio0 { + status ="okay"; +}; + +&adc { + status ="okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x8000>; + }; + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x00008000 0x1b000>; + }; + slot1_partition: partition@23000 { + label = "image-1"; + reg = <0x00023000 0x1b000>; + }; + storage_partition: partition@3e000 { + label = "storage"; + reg = <0x0003e000 0x00002000>; + }; + }; +}; diff --git a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.yaml b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.yaml new file mode 100644 index 00000000000..8622e018ba3 --- /dev/null +++ b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.yaml @@ -0,0 +1,14 @@ +identifier: nrf51dongle/nrf51822 +name: nRF51-Dongle-nRF51822 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32 +flash: 256 +supported: + - ble + - nvs +vendor: nordic diff --git a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822_defconfig b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822_defconfig new file mode 100644 index 00000000000..1289685e1e8 --- /dev/null +++ b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51_blenano/pre_dt_board.cmake b/boards/nordic/nrf51dongle/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf51_blenano/pre_dt_board.cmake rename to boards/nordic/nrf51dongle/pre_dt_board.cmake diff --git a/boards/nordic/nrf52833dk/CMakeLists.txt b/boards/nordic/nrf52833dk/CMakeLists.txt new file mode 100644 index 00000000000..f7df5c94a3b --- /dev/null +++ b/boards/nordic/nrf52833dk/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF52833DK_NRF52820) + # The nrf52833dk_nrf52820 board mirrors the nRF52833 DK hardware. This + # needs to be considered by certain system initialization functionality + # residing in system_nrf52820.c and SoC dependent routines in nrfx_coredep.h. + zephyr_compile_definitions(DEVELOP_IN_NRF52833) + zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) +endif() diff --git a/boards/nordic/nrf52833dk/Kconfig b/boards/nordic/nrf52833dk/Kconfig new file mode 100644 index 00000000000..8b53d5bd73f --- /dev/null +++ b/boards/nordic/nrf52833dk/Kconfig @@ -0,0 +1,10 @@ +# nRF52833 DK NRF52833 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_NRF52833DK diff --git a/boards/nordic/nrf52833dk/Kconfig.defconfig b/boards/nordic/nrf52833dk/Kconfig.defconfig new file mode 100644 index 00000000000..30c49fa7fb7 --- /dev/null +++ b/boards/nordic/nrf52833dk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52833 DK NRF52833 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52833DK + +config BT_CTLR + default BT + +endif # BOARD_NRF52833DK diff --git a/boards/nordic/nrf52833dk/Kconfig.nrf52833dk b/boards/nordic/nrf52833dk/Kconfig.nrf52833dk new file mode 100644 index 00000000000..1705a59edec --- /dev/null +++ b/boards/nordic/nrf52833dk/Kconfig.nrf52833dk @@ -0,0 +1,8 @@ +# nRF52833 DK NRF52833 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52833DK + select SOC_NRF52820_QDAA if BOARD_NRF52833DK_NRF52820 + select SOC_NRF52833_QIAA if BOARD_NRF52833DK_NRF52833 diff --git a/boards/arm/nrf52833dk_nrf52833/board.cmake b/boards/nordic/nrf52833dk/board.cmake similarity index 100% rename from boards/arm/nrf52833dk_nrf52833/board.cmake rename to boards/nordic/nrf52833dk/board.cmake diff --git a/boards/nordic/nrf52833dk/board.yml b/boards/nordic/nrf52833dk/board.yml new file mode 100644 index 00000000000..2d6b6e5b12f --- /dev/null +++ b/boards/nordic/nrf52833dk/board.yml @@ -0,0 +1,6 @@ +board: + name: nrf52833dk + vendor: nordic + socs: + - name: nrf52820 + - name: nrf52833 diff --git a/boards/nordic/nrf52833dk/doc/index.rst b/boards/nordic/nrf52833dk/doc/index.rst new file mode 100644 index 00000000000..d182053d506 --- /dev/null +++ b/boards/nordic/nrf52833dk/doc/index.rst @@ -0,0 +1,241 @@ +.. _nrf52833dk_nrf52833: + +nRF52833 DK +########### + +Overview +******** + +The nRF52833 Development Kit (PCA10100) hardware provides +support for the Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +More information about the board can be found at the +`nRF52833 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF52833 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf52833dk/nrf52833`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF52833 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF52833 Development Kit board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (green) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +Programming and Debugging +************************* + +Applications for the ``nrf52833dk/nrf52833`` board configuration can be built, +flashed, and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF52 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52833dk/nrf52833 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF52833 DK +*********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts`. + +Changing UART1 pins +******************* + +The following approach can be used when an application needs to use another set +of pins for UART1: + +1. Add devicetree overlay file to the main directory of your application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default_alt: uart1_default_alt { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep_alt: uart1_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + pinctrl-0 = <&uart1_default_alt>; + /* if sleep state is not used, use /delete-property/ pinctrl-1; and + * skip the "sleep" entry. + */ + pinctrl-1 = <&uart1_sleep_alt>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX + +See :ref:`set-devicetree-overlays` for further details. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the `nRF52833 Product Specification`_, chapter 7 'Hardware and Layout'. +In the table 7.1.1 'aQFN73 ball assignments' select the pins marked +'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used +in under-10KHz applications. They are not suitable for 115200 speed of UART. + +References +********** + +.. target-notes:: + +.. _nRF52833 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _nRF52833 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52833_OPS_v0.7.pdf + +.. _nrf52833dk_nrf52820: + +nRF52820 emulation on nRF52833 DK +################################# + +Overview +******** + +The ``nrf52833dk/nrf52820`` board is a modified version of the +:ref:`nrf52833dk_nrf52833` that enforces the limitations imposed by the nRF52820 +IC, which is a variant of the original nRF52833. Since Nordic does not offer a +development kit for the nRF52820 you can use this board to develop for this IC +while using the nRF52833 Development Kit (PCA10100). + +See :ref:`nrf52833dk_nrf52833` for more information about the development board +and `nRF52820 website`_ for the official reference on the IC itself. + +References +********** + +.. target-notes:: + +.. _nRF52820 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52820 diff --git a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820-pinctrl.dtsi b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820-pinctrl.dtsi rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi diff --git a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts similarity index 100% rename from boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.dts rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts diff --git a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.yaml b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.yaml similarity index 87% rename from boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.yaml rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52820.yaml index 1e31da83439..b2d59ed4e41 100644 --- a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.yaml +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.yaml @@ -1,4 +1,4 @@ -identifier: nrf52833dk_nrf52820 +identifier: nrf52833dk/nrf52820 name: nRF52833-DK-NRF52820 type: mcu arch: arm diff --git a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820_defconfig b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig similarity index 76% rename from boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820_defconfig rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig index f953cca65f1..8daa29dc473 100644 --- a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820_defconfig +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52820_QDAA=y -CONFIG_BOARD_NRF52833DK_NRF52820=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833-pinctrl.dtsi b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833-pinctrl.dtsi rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi diff --git a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts similarity index 100% rename from boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.dts rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts diff --git a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.yaml b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.yaml similarity index 89% rename from boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.yaml rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52833.yaml index 24cacd6ffa3..cd3ed1b54d2 100644 --- a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.yaml +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.yaml @@ -1,4 +1,4 @@ -identifier: nrf52833dk_nrf52833 +identifier: nrf52833dk/nrf52833 name: nRF52833-DK-NRF52833 type: mcu arch: arm diff --git a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833_defconfig b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig similarity index 76% rename from boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833_defconfig rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig index d4d96e6e395..8daa29dc473 100644 --- a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833_defconfig +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_NRF52833DK_NRF52833=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52840dk_nrf52811/pre_dt_board.cmake b/boards/nordic/nrf52833dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840dk_nrf52811/pre_dt_board.cmake rename to boards/nordic/nrf52833dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf52840dk/CMakeLists.txt b/boards/nordic/nrf52840dk/CMakeLists.txt new file mode 100644 index 00000000000..3f75c04696c --- /dev/null +++ b/boards/nordic/nrf52840dk/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2019 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +# The nrf52840dk_nrf52811 board mirrors the nRF52840 DK hardware. This +# needs to be considered by certain system initialization functionality +# residing in system_nrf52811.c and SoC dependent routines in nrfx_coredep.h. +if(CONFIG_BOARD_NRF52840DK_NRF52811) + zephyr_compile_definitions(DEVELOP_IN_NRF52840) + zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) +endif() diff --git a/boards/nordic/nrf52840dk/Kconfig b/boards/nordic/nrf52840dk/Kconfig new file mode 100644 index 00000000000..61d553e93c5 --- /dev/null +++ b/boards/nordic/nrf52840dk/Kconfig @@ -0,0 +1,19 @@ +# nRF52840 DK NRF52840 board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840DK + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF52X_HV + default y + depends on SOC_NRF52840_QIAA + +endif # BOARD_NRF52840DK diff --git a/boards/nordic/nrf52840dk/Kconfig.defconfig b/boards/nordic/nrf52840dk/Kconfig.defconfig new file mode 100644 index 00000000000..7e932d27f7a --- /dev/null +++ b/boards/nordic/nrf52840dk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52840 DK NRF52840 board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840DK + +config BT_CTLR + default BT + +endif # BOARD_NRF52840DK diff --git a/boards/nordic/nrf52840dk/Kconfig.nrf52840dk b/boards/nordic/nrf52840dk/Kconfig.nrf52840dk new file mode 100644 index 00000000000..63dc7a84ae8 --- /dev/null +++ b/boards/nordic/nrf52840dk/Kconfig.nrf52840dk @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Zephyr Project members and individual contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840DK + select SOC_NRF52840_QIAA if BOARD_NRF52840DK_NRF52840 + select SOC_NRF52811_QFAA if BOARD_NRF52840DK_NRF52811 diff --git a/boards/arm/nrf52840dk_nrf52840/board.cmake b/boards/nordic/nrf52840dk/board.cmake similarity index 100% rename from boards/arm/nrf52840dk_nrf52840/board.cmake rename to boards/nordic/nrf52840dk/board.cmake diff --git a/boards/nordic/nrf52840dk/board.yml b/boards/nordic/nrf52840dk/board.yml new file mode 100644 index 00000000000..d15e1975027 --- /dev/null +++ b/boards/nordic/nrf52840dk/board.yml @@ -0,0 +1,8 @@ +board: + name: nrf52840dk + vendor: nordic + socs: + # Physical nRF52840 SoC on PCA10056 + - name: nrf52840 + # nRF52840 SoC in nRF52811 emulation mode on PCA10056 + - name: nrf52811 diff --git a/boards/arm/nrf52840dk_nrf52840/doc/img/nrf52840dk_nrf52840.jpg b/boards/nordic/nrf52840dk/doc/img/nrf52840dk_nrf52840.jpg similarity index 100% rename from boards/arm/nrf52840dk_nrf52840/doc/img/nrf52840dk_nrf52840.jpg rename to boards/nordic/nrf52840dk/doc/img/nrf52840dk_nrf52840.jpg diff --git a/boards/nordic/nrf52840dk/doc/index.rst b/boards/nordic/nrf52840dk/doc/index.rst new file mode 100644 index 00000000000..953c86fd190 --- /dev/null +++ b/boards/nordic/nrf52840dk/doc/index.rst @@ -0,0 +1,250 @@ +.. _nrf52840dk_nrf52840: + +nRF52840 DK +########### + +Overview +******** + +The nRF52840 Development Kit (PCA10056) hardware provides support for the +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf52840dk_nrf52840.jpg + :align: center + :alt: nRF52840 DK + + nRF52840 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the `nRF52840 DK website`_. +The `Nordic Semiconductor Infocenter`_ contains the processor's information +and the datasheet. + + +Hardware +******** + +nRF52840 DK has two external oscillators. The frequency of the slow clock +is 32.768 kHz. The frequency of the main clock is 32 MHz. + +Supported Features +================== + +The ``nrf52840dk/nrf52840`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF52840 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF52840 Development Kit board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (green) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +Programming and Debugging +************************* + +Applications for the ``nrf52840dk/nrf52840`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF52840 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52840dk/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF52840 DK +*********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts`. + +Changing UART1 pins +******************* + +The following approach can be used when an application needs to use another set +of pins for UART1: + +1. Add devicetree overlay file to the main directory of your application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default_alt: uart1_default_alt { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep_alt: uart1_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + pinctrl-0 = <&uart1_default_alt>; + /* if sleep state is not used, use /delete-property/ pinctrl-1; and + * skip the "sleep" entry. + */ + pinctrl-1 = <&uart1_sleep_alt>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX + +See :ref:`set-devicetree-overlays` for further details. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the `nRF52840 Product Specification`_, chapter 7 'Hardware and Layout'. +In the table 7.1.1 'aQFN73 ball assignments' select the pins marked +'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used +in under-10KHz applications. They are not suitable for 115200 speed of UART. + +.. _nrf52840dk_nrf52811: + +nRF52811 emulation on nRF52840 DK +################################# + +Overview +******** + +The ``nrf52840dk/nrf52811`` board variant is a modified version of the +:ref:`nrf52840dk_nrf52840` that enforces the limitations imposed by the nRF52811 +IC, which is a variant of the original nRF52840. Since Nordic does not offer a +development kit for the nRF52811 you can use this board to develop for this IC +while using the nRF52840 Development Kit (PCA10056). + +See :ref:`nrf52840dk_nrf52840` for more information about the development board +and `nRF52811 website`_ for the official reference on the IC itself. + + +References +********** + +.. target-notes:: + +.. _nRF52811 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52811 + +References +********** + +.. target-notes:: + +.. _nRF52840 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf +.. _nRF52811 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52811 diff --git a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811-pinctrl.dtsi b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811-pinctrl.dtsi rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi diff --git a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts similarity index 100% rename from boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.dts rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts diff --git a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.yaml b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.yaml similarity index 85% rename from boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.yaml rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52811.yaml index 40d927db116..4c06984e3de 100644 --- a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.yaml +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.yaml @@ -1,4 +1,4 @@ -identifier: nrf52840dk_nrf52811 +identifier: nrf52840dk/nrf52811 name: nRF52840-DK-NRF52811 type: mcu arch: arm diff --git a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811_defconfig b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811_defconfig similarity index 84% rename from boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811_defconfig rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52811_defconfig index 97eaa9232e5..c076e7d8897 100644 --- a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811_defconfig +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811_defconfig @@ -2,10 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52811_QFAA=y -CONFIG_BOARD_NRF52840DK_NRF52811=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840-pinctrl.dtsi rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi diff --git a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts similarity index 100% rename from boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts diff --git a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.yaml b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml similarity index 91% rename from boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.yaml rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml index 00ee8701a97..30a96d563c9 100644 --- a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.yaml +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: nrf52840dk_nrf52840 +identifier: nrf52840dk/nrf52840 name: nRF52840-DK-NRF52840 type: mcu arch: arm diff --git a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840_defconfig b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig similarity index 76% rename from boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840_defconfig rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig index 107f9e00d59..8daa29dc473 100644 --- a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840_defconfig +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840DK_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52840dk_nrf52840/pre_dt_board.cmake b/boards/nordic/nrf52840dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840dk_nrf52840/pre_dt_board.cmake rename to boards/nordic/nrf52840dk/pre_dt_board.cmake diff --git a/boards/arm/nrf9160dk_nrf52840/CMakeLists.txt b/boards/nordic/nrf52840dongle/CMakeLists.txt similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/CMakeLists.txt rename to boards/nordic/nrf52840dongle/CMakeLists.txt diff --git a/boards/nordic/nrf52840dongle/Kconfig b/boards/nordic/nrf52840dongle/Kconfig new file mode 100644 index 00000000000..c4e9b309762 --- /dev/null +++ b/boards/nordic/nrf52840dongle/Kconfig @@ -0,0 +1,29 @@ +# nRF52840 Dongle NRF52840 board configuration + +# Copyright (c) 2018-2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840DONGLE + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF52X_HV + default y + +config BOARD_HAS_NRF5_BOOTLOADER + bool "Board has nRF5 bootloader" + default y + help + If selected, applications are linked so that they can be loaded by Nordic + nRF5 bootloader. + +config BOARD_SERIAL_BACKEND_CDC_ACM + bool "USB CDC" + default y + +endif # BOARD_NRF52840DONGLE diff --git a/boards/nordic/nrf52840dongle/Kconfig.defconfig b/boards/nordic/nrf52840dongle/Kconfig.defconfig new file mode 100644 index 00000000000..1288e33bcdb --- /dev/null +++ b/boards/nordic/nrf52840dongle/Kconfig.defconfig @@ -0,0 +1,83 @@ +# nRF52840 Dongle NRF52840 board configuration +# +# Copyright (c) 2018-2023 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840DONGLE + +# To let the nRF5 bootloader load an application, the application +# must be linked after Nordic MBR, that is factory-programmed on the board. + +# Nordic nRF5 bootloader exists outside of the partitions specified in the +# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application +# correctly, after Nordic MBR. + +# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION +# which will make it link into the correct partition specified in DTS file, +# the offset is applied here so that the full partition size can be used when +# the bootloader Kconfig option has been disabled. + +config FLASH_LOAD_OFFSET + default 0x1000 + depends on BOARD_HAS_NRF5_BOOTLOADER && (MCUBOOT || !USE_DT_CODE_PARTITION) + +if BOARD_SERIAL_BACKEND_CDC_ACM + +config USB_DEVICE_STACK + default y + +config USB_CDC_ACM + default SERIAL + +config CONSOLE + default y + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if !MCUBOOT && CONSOLE + +config SHELL_BACKEND_SERIAL_CHECK_DTR + default SHELL + depends on UART_LINE_CTRL + +config UART_LINE_CTRL + default SHELL + +config USB_DEVICE_REMOTE_WAKEUP + default n + +if LOG + +# Logger cannot use itself to log +choice USB_CDC_ACM_LOG_LEVEL_CHOICE + default USB_CDC_ACM_LOG_LEVEL_OFF +endchoice + +# Set USB log level to error only +choice USB_DEVICE_LOG_LEVEL_CHOICE + default USB_DEVICE_LOG_LEVEL_ERR +endchoice + +# Wait 4000ms at startup for logging +config LOG_PROCESS_THREAD_STARTUP_DELAY_MS + default 4000 + +endif # LOG + +if USB_DEVICE_STACK + +# Enable UART driver, needed for CDC ACM +config SERIAL + default y + +endif # USB_DEVICE_STACK + +endif # BOARD_SERIAL_BACKEND_CDC_ACM + +config BT_CTLR + default BT + +endif # BOARD_NRF52840DONGLE diff --git a/boards/nordic/nrf52840dongle/Kconfig.nrf52840dongle b/boards/nordic/nrf52840dongle/Kconfig.nrf52840dongle new file mode 100644 index 00000000000..cd58d54c688 --- /dev/null +++ b/boards/nordic/nrf52840dongle/Kconfig.nrf52840dongle @@ -0,0 +1,7 @@ +# nRF52840 Dongle NRF52840 board configuration + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840DONGLE + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840dongle_nrf52840/board.c b/boards/nordic/nrf52840dongle/board.c similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/board.c rename to boards/nordic/nrf52840dongle/board.c diff --git a/boards/arm/nrf52840dongle_nrf52840/board.cmake b/boards/nordic/nrf52840dongle/board.cmake similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/board.cmake rename to boards/nordic/nrf52840dongle/board.cmake diff --git a/boards/nordic/nrf52840dongle/board.yml b/boards/nordic/nrf52840dongle/board.yml new file mode 100644 index 00000000000..a22449e5519 --- /dev/null +++ b/boards/nordic/nrf52840dongle/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52840dongle + vendor: nordic + socs: + - name: nrf52840 diff --git a/boards/arm/nrf52840dongle_nrf52840/doc/img/nRF52840_dongle_press_reset.svg b/boards/nordic/nrf52840dongle/doc/img/nRF52840_dongle_press_reset.svg similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/doc/img/nRF52840_dongle_press_reset.svg rename to boards/nordic/nrf52840dongle/doc/img/nRF52840_dongle_press_reset.svg diff --git a/boards/arm/nrf52840dongle_nrf52840/doc/img/nrf52840dongle_nrf52840.jpg b/boards/nordic/nrf52840dongle/doc/img/nrf52840dongle_nrf52840.jpg similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/doc/img/nrf52840dongle_nrf52840.jpg rename to boards/nordic/nrf52840dongle/doc/img/nrf52840dongle_nrf52840.jpg diff --git a/boards/nordic/nrf52840dongle/doc/index.rst b/boards/nordic/nrf52840dongle/doc/index.rst new file mode 100644 index 00000000000..235b0ea4b35 --- /dev/null +++ b/boards/nordic/nrf52840dongle/doc/index.rst @@ -0,0 +1,348 @@ +.. _nrf52840dongle_nrf52840: + +nRF52840 Dongle +############### + +Overview +******** + +The nRF52840 Dongle (PCA10059) hardware provides support for the Nordic +Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf52840dongle_nrf52840.jpg + :align: center + :alt: nRF52840 Dongle + + nRF52840 Dongle + +More information about the board can be found at the +`nRF52840 Dongle website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +The ``nrf52840dongle/nrf52840`` has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf52840dongle/nrf52840`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF52840 Dongle website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF52840 Dongle board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (green) = P0.6 +* LED1 (red) = P0.8 +* LED1 (green) = P1.9 +* LED1 (blue) = P0.12 + +Push buttons +------------ + +* BUTTON1 = SW1 = P1.6 +* RESET = SW2 = P0.18 + +Programming and Debugging +************************* + +Applications for the ``nrf52840dongle/nrf52840`` board configuration can be +built in the usual way (see :ref:`build_an_application` for more details). + +Flashing +======== + +The board supports the following programming options: + +1. Using the built-in bootloader only +2. Using MCUboot in serial recovery mode +3. Using an external :ref:`debug probe ` + +These instructions use the :ref:`west ` tool and assume you are in the +root directory of your :term:`west installation`. + +Option 1: Using the Built-In Bootloader Only +-------------------------------------------- + +The board is factory-programmed with Nordic's bootloader from Nordic's nRF5 +SDK. With this option, you'll use Nordic's `nrfutil`_ program to create +firmware packages supported by this bootloader and flash them to the +device. Make sure ``nrfutil`` is installed before proceeding. + +#. Reset the board into the Nordic bootloader by pressing the RESET button. + + The push button is on the far side of the board from the USB connector. Note + that the button does not face up. You will have to push it from the outside + in, towards the USB connector: + + .. image:: img/nRF52840_dongle_press_reset.svg + :alt: Location of RESET button and direction of push + + The red LED should start a fade pattern, signalling the bootloader is + running. + +#. Compile a Zephyr application; we'll use :zephyr:code-sample:`blinky`. + + .. zephyr-app-commands:: + :app: zephyr/samples/basic/blinky + :board: nrf52840dongle/nrf52840 + :goals: build + +#. Package the application for the bootloader using ``nrfutil``: + + .. code-block:: console + + nrfutil pkg generate --hw-version 52 --sd-req=0x00 \ + --application build/zephyr/zephyr.hex \ + --application-version 1 blinky.zip + +#. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be + something like ``COMx`` on Windows, and something else on macOS. + + .. code-block:: console + + nrfutil dfu usb-serial -pkg blinky.zip -p /dev/ttyACM0 + + When this command exits, observe the green LED on the board blinking, + instead of the red LED used by the bootloader. + +For more information, see `Nordic Semiconductor USB DFU`_. + +Option 2: Using MCUboot in Serial Recovery Mode +----------------------------------------------- + +It is also possible to use the MCUboot bootloader with this board to flash +Zephyr applications. You need to do some one-time set-up to build and flash +MCUboot on your board. From that point on, you can build and flash other Zephyr +applications using MCUboot's serial recovery mode. This process does not +overwrite the built-in Nordic bootloader, so you can always go back to using +Option 1 later. + +Install `nrfutil`_ and `mcumgr`_ first, and make sure MCUboot's ``imgtool`` is +available for signing your binary for MCUboot as described on :ref:`west-sign`. + +Next, do the **one-time setup** to flash MCUboot. We'll assume you've cloned +the `MCUboot`_ repository into the directory ``mcuboot``, and that it is next +to the zephyr repository on your computer. + +#. Reset the board into the Nordic bootloader as described above. + +#. Compile MCUboot as a Zephyr application. + + .. zephyr-app-commands:: + :app: mcuboot/boot/zephyr + :board: nrf52840dongle/nrf52840 + :build-dir: mcuboot + :goals: build + +#. Package the application for the bootloader using ``nrfutil``: + + .. code-block:: console + + nrfutil pkg generate --hw-version 52 --sd-req=0x00 \ + --application build/mcuboot/zephyr/zephyr.hex \ + --application-version 1 mcuboot.zip + +#. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be + something like ``COMx`` on Windows, and something else on macOS. + + .. code-block:: console + + nrfutil dfu usb-serial -pkg mcuboot.zip -p /dev/ttyACM0 + +You can now flash a Zephyr application to the board using MCUboot's serial +recovery mode. We'll use the :zephyr:code-sample:`smp-svr` sample since it's ready to be +compiled for chain-loading by MCUboot (and itself supports firmware updates +over Bluetooth). + +#. Boot into MCUboot serial recovery mode by plugging the board in with the SW1 + button pressed down. See above for a picture showing where SW1 is. + + **Do not press RESET**; that will run the Nordic bootloader, which is + different than MCUboot. + + A serial port will enumerate on your board. On Windows, "MCUBOOT" should + appear under "Other Devices" in the Device Manager (in addition to the usual + ``COMx`` device). On Linux, something like + :file:`/dev/serial/by-id/usb-ZEPHYR_MCUBOOT_0.01-if00` should be created. + + If no serial port appears, try plugging it in again, making sure SW1 is + pressed. If it still doesn't appear, retry the one-time MCUboot setup. + +#. Compile ``smp_svr``. + + .. zephyr-app-commands:: + :app: zephyr/samples/subsys/mgmt/mcumgr/smp_svr + :board: nrf52840dongle/nrf52840 + :build-dir: smp_svr + :goals: build + +#. Sign ``smp_svr`` for chain-loading by MCUboot. + + .. code-block:: console + + west sign -t imgtool --bin --no-hex -d build/smp_svr \ + -B smp_svr.signed.bin -- --key mcuboot/root-rsa-2048.pem + +#. Flash the application to the MCUboot serial port using ``mcumgr``: + + .. code-block:: console + + mcumgr --conntype=serial --connstring='dev=/dev/ttyACM0,baud=115200' \ + image upload -e smp_svr.signed.bin + +#. Reset the device: + + .. code-block:: console + + mcumgr --conntype=serial --connstring='dev=/dev/ttyACM0,baud=115200' reset + +You should now be able to scan for Bluetooth devices using a smartphone or +computer. The device you just flashed will be listed with ``Zephyr`` in its +name. + +.. note:: + + This board supports building other Zephyr applications for flashing with + MCUboot in this way also. Just make sure :kconfig:option:`CONFIG_BOOTLOADER_MCUBOOT` + is set when building your application. For example, to compile blinky for + loading by MCUboot, use this: + + .. zephyr-app-commands:: + :app: zephyr/samples/basic/blinky + :board: nrf52840dongle/nrf52840 + :build-dir: blinky + :goals: build + :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y + + You can then sign and flash it using the steps above. + +Option 3: Using an External Debug Probe +--------------------------------------- + +If you have one, you can also use an external :ref:`debug probe ` +to flash and debug Zephyr applications, but you need to solder an SWD header +onto the back side of the board. + +For Segger J-Link debug probes, follow the instructions in the +:ref:`nordic_segger` page to install and configure all the necessary +software. Further information can be found in :ref:`nordic_segger_flashing`. + +Locate the DTS file: :zephyr_file:`boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts`. +This file requires a small modification to use a different partition table. +Edit the include directive to include "fstab-debugger" instead of "fstab-stock". + +In addition, the Kconfig file in the same directory must be modified by setting +``BOARD_HAS_NRF5_BOOTLOADER`` to be default ``n``, otherwise the code will be +flashed with an offset. + +Then build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nrf52840dongle/nrf52840 + :goals: build flash + +Observe the LED on the board blinking. + +Debugging +========= + +The ``nrf52840dongle/nrf52840`` board does not have an on-board J-Link debug IC +as some nRF5x development boards, however, instructions from the +:ref:`nordic_segger` page also apply to this board, with the additional step +of connecting an external debugger. + +Testing the LEDs and buttons on the nRF52840 Dongle +*************************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` + +You can build and program the examples to make sure Zephyr is running correctly +on your board. + + +References +********** + +.. target-notes:: + +.. _nRF52840 Dongle website: + https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle +.. _Nordic Semiconductor Infocenter: + https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: + https://www.segger.com/jlink-software.html +.. _Nordic Semiconductor USB DFU: + https://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.sdk5.v15.2.0%2Fsdk_app_serial_dfu_bootloader.html +.. _nrfutil: + https://github.com/NordicSemiconductor/pc-nrfutil +.. _MCUboot: + https://github.com/JuulLabs-OSS/mcuboot +.. _mcumgr: + https://github.com/apache/mynewt-mcumgr-cli diff --git a/boards/arm/nrf52840dongle_nrf52840/fstab-debugger.dtsi b/boards/nordic/nrf52840dongle/fstab-debugger.dtsi similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/fstab-debugger.dtsi rename to boards/nordic/nrf52840dongle/fstab-debugger.dtsi diff --git a/boards/arm/nrf52840dongle_nrf52840/fstab-stock.dtsi b/boards/nordic/nrf52840dongle/fstab-stock.dtsi similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/fstab-stock.dtsi rename to boards/nordic/nrf52840dongle/fstab-stock.dtsi diff --git a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840-pinctrl.dtsi b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840-pinctrl.dtsi rename to boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi diff --git a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.dts b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.dts rename to boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts diff --git a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.yaml b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml similarity index 87% rename from boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.yaml rename to boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml index f0fb4cdafbf..1e61b0e71e4 100644 --- a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.yaml +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: nrf52840dongle_nrf52840 +identifier: nrf52840dongle/nrf52840 name: nRF52840-Dongle-NRF52840 type: mcu arch: arm diff --git a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840_defconfig b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_defconfig similarity index 82% rename from boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840_defconfig rename to boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_defconfig index 36998fc79a1..ffaccd75ea8 100644 --- a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840_defconfig +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840DONGLE_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52840dongle_nrf52840/pre_dt_board.cmake b/boards/nordic/nrf52840dongle/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/pre_dt_board.cmake rename to boards/nordic/nrf52840dongle/pre_dt_board.cmake diff --git a/boards/nordic/nrf52dk/CMakeLists.txt b/boards/nordic/nrf52dk/CMakeLists.txt new file mode 100644 index 00000000000..9135ec34d6f --- /dev/null +++ b/boards/nordic/nrf52dk/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF52DK_NRF52805 OR CONFIG_BOARD_NRF52DK_NRF52810) + # The nrf52dk_nrf52805/nrf52dk_nrf52810 boards mirrors the nRF52832 DK hardware. This + # needs to be considered by certain system initialization functionality + # residing in system_nrf52810.c and SoC dependent routines in nrfx_coredep.h. + zephyr_compile_definitions(DEVELOP_IN_NRF52832) + zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) +endif() diff --git a/boards/nordic/nrf52dk/Kconfig b/boards/nordic/nrf52dk/Kconfig new file mode 100644 index 00000000000..fb039240e01 --- /dev/null +++ b/boards/nordic/nrf52dk/Kconfig @@ -0,0 +1,18 @@ +# nRF52 DK nRF52810 board configuration + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52DK + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +# BT_CTLR depends on BT. When BT is enabled we should default to also +# enabling the controller. +config BT_CTLR + default y if BT + +endif # BOARD_NRF52DK diff --git a/boards/nordic/nrf52dk/Kconfig.nrf52dk b/boards/nordic/nrf52dk/Kconfig.nrf52dk new file mode 100644 index 00000000000..d04465a5135 --- /dev/null +++ b/boards/nordic/nrf52dk/Kconfig.nrf52dk @@ -0,0 +1,9 @@ +# nRF52 DK nRF52810 board configuration + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52DK + select SOC_NRF52805_CAAA if BOARD_NRF52DK_NRF52805 + select SOC_NRF52810_QFAA if BOARD_NRF52DK_NRF52810 + select SOC_NRF52832_QFAA if BOARD_NRF52DK_NRF52832 diff --git a/boards/arm/nrf52dk_nrf52832/board.cmake b/boards/nordic/nrf52dk/board.cmake similarity index 100% rename from boards/arm/nrf52dk_nrf52832/board.cmake rename to boards/nordic/nrf52dk/board.cmake diff --git a/boards/nordic/nrf52dk/board.yml b/boards/nordic/nrf52dk/board.yml new file mode 100644 index 00000000000..1f21be9c60e --- /dev/null +++ b/boards/nordic/nrf52dk/board.yml @@ -0,0 +1,7 @@ +board: + name: nrf52dk + vendor: nordic + socs: + - name: nrf52805 + - name: nrf52810 + - name: nrf52832 diff --git a/boards/arm/nrf52dk_nrf52832/doc/img/nrf52dk_nrf52832.jpg b/boards/nordic/nrf52dk/doc/img/nrf52dk_nrf52832.jpg similarity index 100% rename from boards/arm/nrf52dk_nrf52832/doc/img/nrf52dk_nrf52832.jpg rename to boards/nordic/nrf52dk/doc/img/nrf52dk_nrf52832.jpg diff --git a/boards/nordic/nrf52dk/doc/index.rst b/boards/nordic/nrf52dk/doc/index.rst new file mode 100644 index 00000000000..07f241eac1e --- /dev/null +++ b/boards/nordic/nrf52dk/doc/index.rst @@ -0,0 +1,455 @@ +.. _nrf52dk_nrf52832: + +nRF52 DK +######## + +Overview +******** + +The nRF52 Development Kit (PCA10040) hardware provides +support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf52dk_nrf52832.jpg + :align: center + :alt: nRF52 DK + + nRF52 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the +`nRF52 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF52 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf52dk/nrf52832`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF52 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF52 Development Kit board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.17 +* LED2 (green) = P0.18 +* LED3 (green) = P0.19 +* LED4 (green) = P0.20 +* LD5 (red/green) = OB LED 1/2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.13 +* BUTTON2 = SW2 = P0.14 +* BUTTON3 = SW3 = P0.15 +* BUTTON4 = SW4 = P0.16 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +J-Link Prog Connector + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + +Debug IN + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | VDD | N/A | ++-------+--------------+-------------------------+ +| 2 | SWDIO | SWDIO | ++-------+--------------+-------------------------+ +| 3 | GND | N/A | ++-------+--------------+-------------------------+ +| 4 | SWDCLK | SWDCLK | ++-------+--------------+-------------------------+ +| 5 | GND | N/A | ++-------+--------------+-------------------------+ +| 6 | P0.18 | P0.18 / TRACEDATA[0] / | +| | | SWO | ++-------+--------------+-------------------------+ +| 7 | Cut off | N/A | ++-------+--------------+-------------------------+ +| 8 | Cut off | N/A | ++-------+--------------+-------------------------+ +| 9 | GND | N/A | ++-------+--------------+-------------------------+ +| 10 | P0.21 | P0.21 / RESET | ++-------+--------------+-------------------------+ + +Debug OUT + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | +| | | ++-------+----------------+ +| 7 | Cut off | ++-------+----------------+ +| 8 | Cut off | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + +Shield Debug and Current measurement + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | VDD_nRF | ++-------+----------------+ +| 2 | VDD | ++-------+----------------+ +| 3 | SH_VTG | ++-------+----------------+ +| 4 | SH_SWDIO | ++-------+----------------+ +| 5 | SH_SWDCLK | ++-------+----------------+ +| 6 | SH_SWO | ++-------+----------------+ +| 7 | SH_RESET | ++-------+----------------+ +| 8 | SH_GND_DETECT | ++-------+----------------+ + +Auxiliary + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | P0.00 | P0.00 / XL1 | ++-------+--------------+-------------------------+ +| 2 | P0.01 | P0.01 / XL2 | ++-------+--------------+-------------------------+ +| 3 | P0.21 | P0.21 / RESET | ++-------+--------------+-------------------------+ +| 4 | P0.05_C | P0.05 / AIN3 | ++-------+--------------+-------------------------+ +| 5 | P0.06_C | P0.06 | ++-------+--------------+-------------------------+ +| 6 | P0.07_C | P0.07 | ++-------+--------------+-------------------------+ +| 7 | P0.08_C | P0.08 | ++-------+--------------+-------------------------+ +| 8 | P0.09 | P0.09 / NFC1 | ++-------+--------------+-------------------------+ +| 9 | P0.10 | P0.10 / NFC2 | ++-------+--------------+-------------------------+ + +Arduino Headers +--------------- + +P1/P7 Power + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | VDD | N/A | ++-------+--------------+-------------------------+ +| 2 | VDD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.21 / RESET | ++-------+--------------+-------------------------+ +| 4 | VDD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | VIN | N/A | ++-------+--------------+-------------------------+ + +P2/P8 Analog in + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +P3/P9 Digital I/O + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | D0 (RX) | P0.11 | ++-------+--------------+-------------------------+ +| 2 | D1 (TX) | P0.12 | ++-------+--------------+-------------------------+ +| 3 | D2 | P0.13 | ++-------+--------------+-------------------------+ +| 4 | D3 | P0.14 / TRACEDATA[3] | ++-------+--------------+-------------------------+ +| 5 | D4 | P0.15 / TRACEDATA[2] | ++-------+--------------+-------------------------+ +| 6 | D5 | P0.16 / TRACEDATA[1] | ++-------+--------------+-------------------------+ +| 7 | D6 | P0.17 | ++-------+--------------+-------------------------+ +| 8 | D7 | P0.18 / TRACEDATA[3] / | +| | | SWO | ++-------+--------------+-------------------------+ + +P4/P10 Digital I/O + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | D8 | P0.19 | ++-------+--------------+-------------------------+ +| 2 | D9 | P0.20 / TRACECLK | ++-------+--------------+-------------------------+ +| 3 | D10 (SS) | P0.22 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 5 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 6 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 9 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 10 | SCL | P0.27 | ++-------+--------------+-------------------------+ + +P5/P11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF52 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52dk/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF52 DK +******************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf52dk/nrf52dk_nrf52832.dts`. + +References +********** + +.. target-notes:: + +.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com + +.. _nrf52dk_nrf52805: + +nRF52805 emulation on nRF52 DK +############################## + +Overview +******** + +The ``nrf52dk/nrf52805`` board is a modified version of the :ref:`nrf52dk_nrf52832` +that enforces the limitations imposed by the nRF52805 IC, which is a +cost-reduced variant of the original nRF52832. Since Nordic does not offer a +development kit for the nRF52805, you can use this board to develop for this +IC while using the nRF52 Development Kit (PCA10040). + +See :ref:`nrf52dk_nrf52832` for more information about the development board and +`nRF52805 website`_ for the official reference on the IC itself. + +References +********** + +.. target-notes:: + +.. _nRF52805 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52805 + +.. _nrf52dk_nrf52810: + +nRF52810 emulation on nRF52 DK +############################## + +Overview +******** + +The ``nrf52dk/nrf52810`` board is a modified version of the :ref:`nrf52dk_nrf52832` +that enforces the limitations imposed by the nRF52810 IC, which is a +cost-reduced variant of the original nRF52832. Since Nordic does not offer a +development kit for the nRF52810 you can use this board to develop for this +IC while using the nRF52 Development Kit (PCA10040). + +See :ref:`nrf52dk_nrf52832` for more information about the development board and +`nRF52810 website`_ for the official reference on the IC itself. + + +References +********** + +.. target-notes:: + +.. _nRF52810 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52810 diff --git a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805-pinctrl.dtsi rename to boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi diff --git a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts similarity index 100% rename from boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805.dts rename to boards/nordic/nrf52dk/nrf52dk_nrf52805.dts diff --git a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805.yaml b/boards/nordic/nrf52dk/nrf52dk_nrf52805.yaml similarity index 84% rename from boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805.yaml rename to boards/nordic/nrf52dk/nrf52dk_nrf52805.yaml index 3ebff8db1a4..86d3e44b8ef 100644 --- a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805.yaml +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805.yaml @@ -1,4 +1,4 @@ -identifier: nrf52dk_nrf52805 +identifier: nrf52dk/nrf52805 name: nRF52-DK-NRF52805 type: mcu arch: arm diff --git a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805_defconfig b/boards/nordic/nrf52dk/nrf52dk_nrf52805_defconfig similarity index 81% rename from boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805_defconfig rename to boards/nordic/nrf52dk/nrf52dk_nrf52805_defconfig index d1c9da8186c..a4b09719b93 100644 --- a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805_defconfig +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52805_CAAA=y -CONFIG_BOARD_NRF52DK_NRF52805=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810-pinctrl.dtsi rename to boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi diff --git a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts similarity index 100% rename from boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810.dts rename to boards/nordic/nrf52dk/nrf52dk_nrf52810.dts diff --git a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810.yaml b/boards/nordic/nrf52dk/nrf52dk_nrf52810.yaml similarity index 84% rename from boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810.yaml rename to boards/nordic/nrf52dk/nrf52dk_nrf52810.yaml index 05e07eeba2a..46cc9adbac6 100644 --- a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810.yaml +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52810.yaml @@ -1,4 +1,4 @@ -identifier: nrf52dk_nrf52810 +identifier: nrf52dk/nrf52810 name: nRF52-DK-NRF52810 type: mcu arch: arm diff --git a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810_defconfig b/boards/nordic/nrf52dk/nrf52dk_nrf52810_defconfig similarity index 83% rename from boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810_defconfig rename to boards/nordic/nrf52dk/nrf52dk_nrf52810_defconfig index a90ea346ba0..a6749163af4 100644 --- a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810_defconfig +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52810_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52810_QFAA=y -CONFIG_BOARD_NRF52DK_NRF52810=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832-pinctrl.dtsi rename to boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi diff --git a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts similarity index 100% rename from boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.dts rename to boards/nordic/nrf52dk/nrf52dk_nrf52832.dts diff --git a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.yaml b/boards/nordic/nrf52dk/nrf52dk_nrf52832.yaml similarity index 89% rename from boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.yaml rename to boards/nordic/nrf52dk/nrf52dk_nrf52832.yaml index 209069df379..f50bb91ba04 100644 --- a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.yaml +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: nrf52dk_nrf52832 +identifier: nrf52dk/nrf52832 name: nRF52-DK-NRF52832 type: mcu arch: arm diff --git a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832_defconfig b/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig similarity index 77% rename from boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832_defconfig rename to boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig index 1f1eccdbec2..8daa29dc473 100644 --- a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832_defconfig +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52DK_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52_adafruit_feather/pre_dt_board.cmake b/boards/nordic/nrf52dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52_adafruit_feather/pre_dt_board.cmake rename to boards/nordic/nrf52dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf5340_audio_dk/CMakeLists.txt b/boards/nordic/nrf5340_audio_dk/CMakeLists.txt new file mode 100644 index 00000000000..63112d0d00b --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2021 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +if((CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) + AND CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(nrf5340_audio_dk_cpunet_reset.c) + + if(CONFIG_BUILD_WITH_TFM) + zephyr_library_include_directories( + $/api_ns/interface/include + ) + endif() +endif() diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig b/boards/nordic/nrf5340_audio_dk/Kconfig new file mode 100644 index 00000000000..e626c40acc7 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/Kconfig @@ -0,0 +1,61 @@ +# nRF5340 Audio DK board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "nRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "nrf5340_audio_dk/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "nrf5340_audio_dk/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig b/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig new file mode 100644 index 00000000000..c8d07e2adfa --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig @@ -0,0 +1,77 @@ +# nRF5340 Audio DK board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +config IPM_NRFX + default IPM + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET + +config BT_CTLR + default y if BT + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig.nrf5340_audio_dk b/boards/nordic/nrf5340_audio_dk/Kconfig.nrf5340_audio_dk new file mode 100644 index 00000000000..a04b8f85a6a --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/Kconfig.nrf5340_audio_dk @@ -0,0 +1,9 @@ +# nRF5340 Audio DK board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF5340_AUDIO_DK + select SOC_NRF5340_CPUAPP_QKAA if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET diff --git a/boards/nordic/nrf5340_audio_dk/board.cmake b/boards/nordic/nrf5340_audio_dk/board.cmake new file mode 100644 index 00000000000..b44ece9b7e5 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/board.cmake @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf5340_audio_dk/board.yml b/boards/nordic/nrf5340_audio_dk/board.yml new file mode 100644 index 00000000000..443381b9461 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/board.yml @@ -0,0 +1,8 @@ +board: + name: nrf5340_audio_dk + vendor: nordic + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/doc/img/nrf5340_audio_dk.jpg b/boards/nordic/nrf5340_audio_dk/doc/img/nrf5340_audio_dk.jpg similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/doc/img/nrf5340_audio_dk.jpg rename to boards/nordic/nrf5340_audio_dk/doc/img/nrf5340_audio_dk.jpg diff --git a/boards/nordic/nrf5340_audio_dk/doc/index.rst b/boards/nordic/nrf5340_audio_dk/doc/index.rst new file mode 100644 index 00000000000..558f995be66 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/doc/index.rst @@ -0,0 +1,109 @@ +.. _nrf5340_audio_dk_nrf5340: + +nRF5340 Audio DK +################ + +Overview +******** + +The nRF5340 Audio DK (PCA10121) is designed for showcasing, developing and experimenting +with Bluetooth® LE Audio. + +You can use this board for developing LE-Audio-compatible applications that support Auracast™, +connected isochronous streams (CIS) and broadcast isochronous streams (BIS), +and offer support for acting as a audio source, audio sink and source + sink. + +Zephyr uses the ``nrf5340_audio_dk/nrf5340`` board configuration for building +for the nRF5340 Audio DK. + +Hardware +******** + +The nRF5340 Audio DK comes with the following hardware features: + +* nRF5340 dual-core SoC based on the Arm® Cortex®-M33 architecture +* CS47L63 Low-Power Audio DSP with mono differential headphone driver +* nPM1100 Ultra-small form-factor Power Management IC +* On-board digital microphone +* On-board power measurement +* SD card slot +* Built-in debugger +* Stereo analog input using 3.5 mm jack +* USB soundcard capability + +.. figure:: img/nrf5340_audio_dk.jpg + :align: center + :alt: nRF5340 DK + +More information about the board can be found at the `nRF5340 Audio DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + +nRF5340 SoC +=========== + +The nRF5340 Audio DK is built around the nRF5340 SoC, which has the following characteristics: + +* A full-featured Arm Cortex-M33F core with DSP instructions, + FPU, and Armv8-M Security Extension, running at up to 128 MHz, + referred to as the **application core**. +* A secondary Arm Cortex-M33 core, with a reduced feature set, + running at a fixed 64 MHz, referred to as the **network core**. + +The ``nrf5340_audio_dk/nrf5340/cpuapp`` build target provides support for the application +core on the nRF5340 SoC. The ``nrf5340_audio_dk/nrf5340/cpunet`` build target provides +support for the network core on the nRF5340 SoC. + +The `Nordic Semiconductor Infocenter`_ contains the processor's information and +the datasheet. + +Supported Features +================== + +See :ref:`nrf5340dk_nrf5340` and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF5340 Audio DK board hardware features. + + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then you can build and flash +applications as usual (:ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The nRF5340 has a flash read-back protection feature. When flash read-back + protection is active, you will need to recover the chip before reflashing. + If you are flashing with :ref:`west `, run + this command for more details on the related ``--recover`` option: + + .. code-block:: console + + west flash -H -r nrfjprog --skip-rebuild + +.. note:: + + Flashing and debugging applications on the nRF5340 Audio DK requires + upgrading the nRF Command Line Tools to version 10.12.0. Further + information on how to install the nRF Command Line Tools can be + found in :ref:`nordic_segger_flashing`. + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +boards with a Segger IC. + +References +********** + +.. target-notes:: + +.. _nRF5340 Audio DK website: + https://www.nordicsemi.com/Products/Development-hardware/nrf5340-audio-dk +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_cpunet_reset.c b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_cpunet_reset.c rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.dts similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.dts rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.dts diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml similarity index 84% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.yaml rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml index d5598ed9efc..9c131a6c9d4 100644 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.yaml +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340_audio_dk_nrf5340_cpuapp +identifier: nrf5340_audio_dk/nrf5340/cpuapp name: NRF5340-AUDIO-DK-NRF5340-application-MCU type: mcu arch: arm diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_defconfig b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000..516f0cf7407 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y + +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_ARM_TRUSTZONE_M=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_REGULATOR=y diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml similarity index 83% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml index 7b670992a87..4194fc63574 100644 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340_audio_dk_nrf5340_cpuapp_ns +identifier: nrf5340_audio_dk/nrf5340/cpuapp/ns name: NRF5340-AUDIO-DK-NRF5340-application-MCU-Non-Secure type: mcu arch: arm diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig new file mode 100644 index 00000000000..5883909a4f0 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y + +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_REGULATOR=y diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet.dts rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet.yaml b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.yaml similarity index 79% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet.yaml rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.yaml index 28ecb10a8b5..35e0ba7ca28 100644 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet.yaml +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340_audio_dk_nrf5340_cpunet +identifier: nrf5340_audio_dk/nrf5340/cpunet name: NRF5340-AUDIO-DK-NRF5340-network-MCU type: mcu arch: arm diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet_defconfig b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..56940c43a09 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/frdm_kw41z/CMakeLists.txt b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_defconfig similarity index 100% rename from boards/arm/frdm_kw41z/CMakeLists.txt rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_defconfig diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_shared.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_shared.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/pre_dt_board.cmake b/boards/nordic/nrf5340_audio_dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/pre_dt_board.cmake rename to boards/nordic/nrf5340_audio_dk/pre_dt_board.cmake diff --git a/boards/arm/nrf5340dk_nrf5340/CMakeLists.txt b/boards/nordic/nrf5340dk/CMakeLists.txt similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/CMakeLists.txt rename to boards/nordic/nrf5340dk/CMakeLists.txt diff --git a/boards/nordic/nrf5340dk/Kconfig b/boards/nordic/nrf5340dk/Kconfig new file mode 100644 index 00000000000..7513fab4277 --- /dev/null +++ b/boards/nordic/nrf5340dk/Kconfig @@ -0,0 +1,58 @@ +# nRF5340 DK board configuration + +# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "nrf5340dk/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +config DOMAIN_CPUAPP_BOARD + string + default "nrf5340dk/nrf5340/cpuapp" + depends on BOARD_NRF5340DK_NRF5340_CPUNET + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. diff --git a/boards/nordic/nrf5340dk/Kconfig.defconfig b/boards/nordic/nrf5340dk/Kconfig.defconfig new file mode 100644 index 00000000000..67d7c7db9d5 --- /dev/null +++ b/boards/nordic/nrf5340dk/Kconfig.defconfig @@ -0,0 +1,78 @@ +# nRF5340 DK nRF5340 board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_NRF5340DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_NRF5340DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +if BOARD_NRF5340DK_NRF5340_CPUNET + +config BT_CTLR + default y if BT + +endif # BOARD_NRF5340DK_NRF5340_CPUNET diff --git a/boards/nordic/nrf5340dk/Kconfig.nrf5340dk b/boards/nordic/nrf5340dk/Kconfig.nrf5340dk new file mode 100644 index 00000000000..6d9e11d7faa --- /dev/null +++ b/boards/nordic/nrf5340dk/Kconfig.nrf5340dk @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Zephyr Project members and individual contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF5340DK + select SOC_NRF5340_CPUAPP_QKAA if BOARD_NRF5340DK_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_NRF5340DK_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_NRF5340DK_NRF5340_CPUNET diff --git a/boards/arm/nrf5340dk_nrf5340/board.cmake b/boards/nordic/nrf5340dk/board.cmake similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/board.cmake rename to boards/nordic/nrf5340dk/board.cmake diff --git a/boards/nordic/nrf5340dk/board.yml b/boards/nordic/nrf5340dk/board.yml new file mode 100644 index 00000000000..fd90df34350 --- /dev/null +++ b/boards/nordic/nrf5340dk/board.yml @@ -0,0 +1,8 @@ +board: + name: nrf5340dk + vendor: nordic + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/arm/nrf5340dk_nrf5340/doc/img/nrf5340dk.jpg b/boards/nordic/nrf5340dk/doc/img/nrf5340dk.jpg similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/doc/img/nrf5340dk.jpg rename to boards/nordic/nrf5340dk/doc/img/nrf5340dk.jpg diff --git a/boards/nordic/nrf5340dk/doc/index.rst b/boards/nordic/nrf5340dk/doc/index.rst new file mode 100644 index 00000000000..f8ce8a2a84b --- /dev/null +++ b/boards/nordic/nrf5340dk/doc/index.rst @@ -0,0 +1,330 @@ +.. _nrf5340dk_nrf5340: + +nRF5340 DK +########## + +Overview +******** + +The nRF5340 DK (PCA10095) is a single-board development kit for evaluation +and development on the Nordic nRF5340 System-on-Chip (SoC). + +The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with: + +* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and + Armv8-M Security Extension, running at up to 128 MHz, referred to as + the **application core** +* a secondary Arm Cortex-M33 core, with a reduced feature set, running at + a fixed 64 MHz, referred to as the **network core**. + +The ``nrf5340dk/nrf5340/cpuapp`` build target provides support for the application +core on the nRF5340 SoC. The ``nrf5340dk/nrf5340/cpunet`` build target provides +support for the network core on the nRF5340 SoC. + +nRF5340 SoC provides support for the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf5340dk.jpg + :align: center + :alt: nRF5340 DK + + nRF5340 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the +`nRF5340 DK website`_. +The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF5340 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf5340dk/nrf5340/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``nrf5340dk/nrf5340/cpunet`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `Nordic Semiconductor Infocenter`_ +for a complete list of nRF5340 DK board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.28 +* LED2 (green) = P0.29 +* LED3 (green) = P0.30 +* LED4 (green) = P0.31 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.23 +* BUTTON2 = SW2 = P0.24 +* BUTTON3 = SW3 = P0.8 +* BUTTON4 = SW4 = P0.9 +* BOOT = SW5 = boot/reset + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_) on the application core. + The IDAU is implemented with the System Protection Unit and is used to + define secure and non-secure memory maps. By default, all of the memory + space (Flash, SRAM, and peripheral address space) is defined to be secure + accessible only. +- Secure boot. + +Programming and Debugging +************************* + +nRF5340 application core supports the Armv8-M Security Extension. +Applications built for the ``nrf5340dk/nrf5340/cpuapp`` board by default +boot in the Secure state. + +nRF5340 network core does not support the Armv8-M Security Extension. +nRF5340 IDAU may configure bus accesses by the nRF5340 network core +to have Secure attribute set; the latter allows to build and run +Secure only applications on the nRF5340 SoC. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the nRF5340 may contain a Secure and a Non-Secure firmware +image for the application core. The Secure image can be built using either +Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure firmware +images are always built using Zephyr. The two alternatives are described below. + +.. note:: + + By default the Secure image for nRF5340 application core is built + using TF-M. + + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the Non-Secure +firmware image using Zephyr requires the following steps: + +1. Build the Non-Secure Zephyr application + for the application core using ``-DBOARD=nrf5340dk/nrf5340/cpuapp/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output image binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may be + required, to adjust the Non-Secure image Flash and SRAM starting address + and sizes. + +2. Build the application firmware for the network core using + ``-DBOARD=nrf5340dk/nrf5340/cpunet``. + + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process to build the Secure and the Non-Secure firmware images +using Zephyr requires the following steps: + +1. Build the Secure Zephyr application for the application core + using ``-DBOARD=nrf5340dk/nrf5340/cpuapp`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` + in the application project configuration file. +2. Build the Non-Secure Zephyr application for the application core + using ``-DBOARD=nrf5340dk/nrf5340/cpuapp/ns``. +3. Merge the two binaries together. +4. Build the application firmware for the network core using + ``-DBOARD=nrf5340dk/nrf5340/cpunet``. + + +When building a Secure/Non-Secure application for the nRF5340 application core, +the Secure application will have to set the IDAU (SPU) configuration to allow +Non-Secure access to all CPU resources utilized by the Non-Secure application +firmware. SPU configuration shall take place before jumping to the Non-Secure +application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=nrf5340dk/nrf5340/cpuapp`` for +the firmware running on the nRF5340 application core, and using +``-DBOARD=nrf5340dk/nrf5340/cpunet`` for the firmware running +on the nRF5340 network core. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then you can build and flash +applications as usual (:ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The nRF5340 has a flash read-back protection feature. When flash read-back + protection is active, you will need to recover the chip before reflashing. + If you are flashing with :ref:`west `, run + this command for more details on the related ``--recover`` option: + + .. code-block:: console + + west flash -H -r nrfjprog --skip-rebuild + +.. note:: + + Flashing and debugging applications on the nRF5340 DK requires + upgrading the nRF Command Line Tools to version 10.12.0. Further + information on how to install the nRF Command Line Tools can be + found in :ref:`nordic_segger_flashing`. + +Here is an example for the :ref:`hello_world` application running on the +nRF5340 application core. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF5340 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf5340dk/nrf5340/cpuapp + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +boards with a Segger IC. + + +Testing the LEDs and buttons in the nRF5340 DK +********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and +LEDs on the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi`. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _nRF5340 DK website: + https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF5340-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common-pinctrl.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common-pinctrl.dtsi rename to boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common.dtsi rename to boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_partition_conf.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_partition_conf.dtsi rename to boards/nordic/nrf5340dk/nrf5340_cpuapp_partition_conf.dtsi diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340_cpunet_reset.c b/boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340_cpunet_reset.c rename to boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340_shared_sram_planning_conf.dtsi b/boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340_shared_sram_planning_conf.dtsi rename to boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.dts rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml similarity index 87% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.yaml rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml index 6ed15a5d7ef..0a8bfabf5c4 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.yaml +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340dk_nrf5340_cpuapp +identifier: nrf5340dk/nrf5340/cpuapp name: NRF5340-DK-NRF5340-application-MCU type: mcu arch: arm diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_defconfig b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_defconfig similarity index 75% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_defconfig rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_defconfig index 22e8f52ff31..db40370dad0 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_defconfig +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.dts rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml similarity index 86% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.yaml rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml index 90abc04b119..4b311f76e25 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.yaml +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340dk_nrf5340_cpuapp_ns +identifier: nrf5340dk/nrf5340/cpuapp/ns name: NRF5340-DK-NRF5340-application-MCU-Non-Secure type: mcu arch: arm diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns_defconfig b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns_defconfig similarity index 79% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns_defconfig rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns_defconfig index 0fe351e2780..1886b926bfd 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns_defconfig +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP_NS=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.dts rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml similarity index 82% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.yaml rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml index 2f92bb86440..a55a7879fc0 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.yaml +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340dk_nrf5340_cpunet +identifier: nrf5340dk/nrf5340/cpunet name: NRF5340-DK-NRF5340-network-MCU type: mcu arch: arm diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet_defconfig b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..39428726753 --- /dev/null +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf5340dk_nrf5340/pre_dt_board.cmake b/boards/nordic/nrf5340dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/pre_dt_board.cmake rename to boards/nordic/nrf5340dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf54h20pdk/Kconfig.defconfig b/boards/nordic/nrf54h20pdk/Kconfig.defconfig new file mode 100644 index 00000000000..5aa509ba12e --- /dev/null +++ b/boards/nordic/nrf54h20pdk/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54H20PDK + +# Data cache is disabled due to a HW issue in the EngA SoC revision. +config DCACHE + default n + +endif # BOARD_NRF54H20PDK diff --git a/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk b/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk new file mode 100644 index 00000000000..4185c95ef2a --- /dev/null +++ b/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54H20PDK + select SOC_NRF54H20_ENGA_CPUAPP if BOARD_NRF54H20PDK_NRF54H20_CPUAPP + select SOC_NRF54H20_ENGA_CPURAD if BOARD_NRF54H20PDK_NRF54H20_CPURAD + select SOC_NRF54H20_ENGA_CPUPPR if BOARD_NRF54H20PDK_NRF54H20_CPUPPR diff --git a/boards/arm/nrf54h20pdk_nrf54h20/board.cmake b/boards/nordic/nrf54h20pdk/board.cmake similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/board.cmake rename to boards/nordic/nrf54h20pdk/board.cmake diff --git a/boards/nordic/nrf54h20pdk/board.yml b/boards/nordic/nrf54h20pdk/board.yml new file mode 100644 index 00000000000..50e2945307f --- /dev/null +++ b/boards/nordic/nrf54h20pdk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf54h20pdk + vendor: nordic + socs: + - name: nrf54h20 diff --git a/boards/arm/nrf54h20pdk_nrf54h20/doc/img/nrf54h20pdk_nrf54h20.webp b/boards/nordic/nrf54h20pdk/doc/img/nrf54h20pdk_nrf54h20.webp similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/doc/img/nrf54h20pdk_nrf54h20.webp rename to boards/nordic/nrf54h20pdk/doc/img/nrf54h20pdk_nrf54h20.webp diff --git a/boards/nordic/nrf54h20pdk/doc/index.rst b/boards/nordic/nrf54h20pdk/doc/index.rst new file mode 100644 index 00000000000..dd30ff1d133 --- /dev/null +++ b/boards/nordic/nrf54h20pdk/doc/index.rst @@ -0,0 +1,153 @@ +.. _nrf54h20pdk_nrf54h20: + +nRF54H20 PDK +############ + +Overview +******** + +.. note:: + + All software for the nRF54H20 SoC is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The nRF54H20 PDK is a single-board preview development kit for evaluation +and development on the Nordic nRF54H20 System-on-Chip (SoC). + +The nRF54H20 is a multicore SoC with: + +* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security + Extensions, running at up to 320 MHz, referred to as the **application core** +* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security + Extensions, running at up to 256 MHz, referred to as the **radio core**. + +The ``nrf54h20pdk/nrf54h20/cpuapp`` build target provides support for +the application core on the nRF54H20 SoC. +The ``nrf54h20pdk/nrf54h20/cpurad`` build target provides support for +the radio core on the nRF54H20 SoC. + +nRF54H20 SoC provides support for the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`GPIOTE (General Purpose Input Output tasks and events)` +* :abbr:`GRTC (Global real-time counter)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* MRAM +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf54h20pdk_nrf54h20.webp + :align: center + :alt: nRF54H20 PDK + + nRF54H20 PDK (Credit: Nordic Semiconductor) + +Hardware +******** + +nRF54H20 PDK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +Supported Features +================== + +The ``nrf54h20pdk/nrf54h20/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GPIOTE | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ + +The ``nrf54h20pdk/nrf54h20/cpurad`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GPIOTE | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +LEDs +---- + +* LED1 (green) = P9.0 +* LED2 (green) = P9.1 +* LED3 (green) = P9.2 +* LED4 (green) = P9.3 + +Push buttons +------------ + +* BUTTON1 = P0.8 +* BUTTON2 = P0.9 +* BUTTON3 = P0.10 +* BUTTON4 = P0.11 +* RESET (SW1) + +Programming and Debugging +************************* + +Applications for both the ``nrf54h20pdk/nrf54h20/cpuapp`` and +``nrf54h20pdk/nrf54h20/cpurad`` targets can be built, flashed, +and debugged in the usual way. See :ref:`build_an_application` +and :ref:`application_run` for more details on building and running. + +Flashing +======== + +As an example, this section shows how to build and flash the :ref:`hello_world` +application. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF54H20 PDK, complete the following steps: + +First, connect the nRF54H20 PDK to you computer using the IMCU USB port on the PDK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf54h20pdk/nrf54h20/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF54H20 PDK +************************************************ + +There are 2 samples that allow you to test that the buttons (switches) and LEDs +on the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts`. diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_defconfig new file mode 100644 index 00000000000..bad567cbd74 --- /dev/null +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-pinctrl.dtsi b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-pinctrl.dtsi rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-pinctrl.dtsi diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.yaml similarity index 85% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.yaml rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.yaml index a364c2863d3..3c2b266c530 100644 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.yaml +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: nrf54h20pdk_nrf54h20_cpuapp +identifier: nrf54h20pdk/nrf54h20/cpuapp name: nRF54H20-PDK-nRF54H20-Application type: mcu arch: arm diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp_defconfig new file mode 100644 index 00000000000..b014eb7b031 --- /dev/null +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_USE_DT_CODE_PARTITION=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot be applied +# as the (0x0 - 0x400) region is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts similarity index 100% rename from boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml similarity index 83% rename from boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.yaml rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml index 274be865c36..e3cdc3cd1c8 100644 --- a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.yaml +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: nrf54h20pdk_nrf54h20_cpuppr +identifier: nrf54h20pdk/nrf54h20/cpuppr name: nRF54H20-PDK-nRF54H20-PPR type: mcu arch: riscv diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_defconfig new file mode 100644 index 00000000000..0e657c5081e --- /dev/null +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.yaml similarity index 84% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.yaml rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.yaml index d1c8548d07d..138adf12001 100644 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.yaml +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: nrf54h20pdk_nrf54h20_cpurad +identifier: nrf54h20pdk/nrf54h20/cpurad name: nRF54H20-PDK-nRF54H20-Radio type: mcu arch: arm diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad_defconfig new file mode 100644 index 00000000000..1a62a205502 --- /dev/null +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_USE_DT_CODE_PARTITION=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot be applied +# as the (0x0 - 0x400) region is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/pre_dt_board.cmake b/boards/nordic/nrf54h20pdk/pre_dt_board.cmake similarity index 100% rename from boards/riscv/nrf54h20pdk_nrf54h20/pre_dt_board.cmake rename to boards/nordic/nrf54h20pdk/pre_dt_board.cmake diff --git a/boards/nordic/nrf54l15pdk/Kconfig.defconfig b/boards/nordic/nrf54l15pdk/Kconfig.defconfig new file mode 100644 index 00000000000..bd9c7231616 --- /dev/null +++ b/boards/nordic/nrf54l15pdk/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54L15PDK_NRF54L15_CPUAPP + +config BT_CTLR + default BT + +endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP diff --git a/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk b/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk new file mode 100644 index 00000000000..4ec5b6ee62d --- /dev/null +++ b/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54L15PDK_NRF54L15_CPUAPP + select SOC_NRF54L15_ENGA_CPUAPP diff --git a/boards/arm/nrf54l15pdk_nrf54l15/board.cmake b/boards/nordic/nrf54l15pdk/board.cmake similarity index 100% rename from boards/arm/nrf54l15pdk_nrf54l15/board.cmake rename to boards/nordic/nrf54l15pdk/board.cmake diff --git a/boards/nordic/nrf54l15pdk/board.yml b/boards/nordic/nrf54l15pdk/board.yml new file mode 100644 index 00000000000..b33ecf7c4f6 --- /dev/null +++ b/boards/nordic/nrf54l15pdk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf54l15pdk + vendor: nordic + socs: + - name: nrf54l15 diff --git a/boards/arm/nrf54l15pdk_nrf54l15/doc/img/nrf54l15pdk_nrf54l15.webp b/boards/nordic/nrf54l15pdk/doc/img/nrf54l15pdk_nrf54l15.webp similarity index 100% rename from boards/arm/nrf54l15pdk_nrf54l15/doc/img/nrf54l15pdk_nrf54l15.webp rename to boards/nordic/nrf54l15pdk/doc/img/nrf54l15pdk_nrf54l15.webp diff --git a/boards/nordic/nrf54l15pdk/doc/index.rst b/boards/nordic/nrf54l15pdk/doc/index.rst new file mode 100644 index 00000000000..ccc6230dd7d --- /dev/null +++ b/boards/nordic/nrf54l15pdk/doc/index.rst @@ -0,0 +1,139 @@ +.. _nrf54l15pdk_nrf54l15: + +nRF54L15 PDK +############ + +Overview +******** + +.. note:: + + All software for the nRF54L15 SoC is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The nRF54L15 Preview Development Kit hardware provides +support for the Nordic Semiconductor nRF54L15 Arm Cortex-M33 CPU and +the following devices: + +* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)` +* CLOCK +* RRAM +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`GRTC (Global real-time counter)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf54l15pdk_nrf54l15.webp + :align: center + :alt: nRF54L15 PDK + + nRF54L15 PDK (Credit: Nordic Semiconductor) + +Hardware +******** + +nRF54L15 PDK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillators can be configured to use either +internal or external capacitors. + +Supported Features +================== + +The ``nrf54l15pdk/nrf54l15/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| SAADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| RRAM | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| TWIM | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| GRTC | on-chip | counter | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Programming and Debugging +************************* + +Applications for the ``nrf54l15pdk/nrf54l15/cpuapp`` board can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +As an example, this section shows how to build and flash the :ref:`hello_world` +application. + +.. warning:: + + When programming the device, you might get an error similar to the following message:: + + ERROR: The operation attempted is unavailable due to readback protection in + ERROR: your device. Please use --recover to unlock the device. + + This error occurs when readback protection is enabled. + To disable the readback protection, you must *recover* your device. + + Enter the following command to recover the core:: + + west flash --recover + + The ``--recover`` command erases the flash memory and then writes a small binary into + the recovered flash memory. + This binary prevents the readback protection from enabling itself again after a pin + reset or power cycle. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF54L15 PDK, complete the following steps: + +First, connect the nRF54L15 PDK to you computer using the IMCU USB port on the PDK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf54l15pdk/nrf54l15/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF54L15 PDK +************************************************ + +Test the nRF54L15 PDK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi rename to boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts similarity index 100% rename from boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts rename to boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml similarity index 87% rename from boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml rename to boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml index de5ce29d162..ddcd456fb4a 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: nrf54l15pdk_nrf54l15_cpuapp +identifier: nrf54l15pdk/nrf54l15/cpuapp name: nRF54l15-PDK-nRF54l15-Application type: mcu arch: arm diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_defconfig b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_defconfig similarity index 85% rename from boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_defconfig rename to boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_defconfig index bc74c3eeb33..0352761e0ce 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_defconfig +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF54LX=y -CONFIG_SOC_NRF54L15_ENGA_CPUAPP=y -CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUAPP=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/hexiwear_kw40z/CMakeLists.txt b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_defconfig similarity index 100% rename from boards/arm/hexiwear_kw40z/CMakeLists.txt rename to boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_defconfig diff --git a/boards/arm/nrf54l15pdk_nrf54l15/revision.cmake b/boards/nordic/nrf54l15pdk/revision.cmake similarity index 100% rename from boards/arm/nrf54l15pdk_nrf54l15/revision.cmake rename to boards/nordic/nrf54l15pdk/revision.cmake diff --git a/boards/nordic/nrf9131ek/Kconfig.defconfig b/boards/nordic/nrf9131ek/Kconfig.defconfig new file mode 100644 index 00000000000..b63e7ef8d34 --- /dev/null +++ b/boards/nordic/nrf9131ek/Kconfig.defconfig @@ -0,0 +1,35 @@ +# nRF9131 EK NRF9131 board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF9131EK_NRF9131 || BOARD_NRF9131EK_NRF9131_NS + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_NRF9131EK_NRF9131 && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF9131EK_NRF9131_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF9131EK_NRF9131_NS + +endif # BOARD_NRF9131EK_NRF9131 || BOARD_NRF9131EK_NRF9131_NS diff --git a/boards/nordic/nrf9131ek/Kconfig.nrf9131ek b/boards/nordic/nrf9131ek/Kconfig.nrf9131ek new file mode 100644 index 00000000000..447e4577a7d --- /dev/null +++ b/boards/nordic/nrf9131ek/Kconfig.nrf9131ek @@ -0,0 +1,7 @@ +# nRF9131-EK board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF9131EK + select SOC_NRF9131_LACA diff --git a/boards/arm/nrf9131ek_nrf9131/board.cmake b/boards/nordic/nrf9131ek/board.cmake similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/board.cmake rename to boards/nordic/nrf9131ek/board.cmake diff --git a/boards/nordic/nrf9131ek/board.yml b/boards/nordic/nrf9131ek/board.yml new file mode 100644 index 00000000000..246aef6f4e3 --- /dev/null +++ b/boards/nordic/nrf9131ek/board.yml @@ -0,0 +1,7 @@ +board: + name: nrf9131ek + vendor: nordic + socs: + - name: nrf9131 + variants: + - name: 'ns' diff --git a/boards/arm/nrf9131ek_nrf9131/doc/img/nrf9131ek_nrf9131.webp b/boards/nordic/nrf9131ek/doc/img/nrf9131ek_nrf9131.webp similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/doc/img/nrf9131ek_nrf9131.webp rename to boards/nordic/nrf9131ek/doc/img/nrf9131ek_nrf9131.webp diff --git a/boards/nordic/nrf9131ek/doc/index.rst b/boards/nordic/nrf9131ek/doc/index.rst new file mode 100644 index 00000000000..4e328e0bb0e --- /dev/null +++ b/boards/nordic/nrf9131ek/doc/index.rst @@ -0,0 +1,229 @@ +.. _nrf9131ek_nrf9131: + +nRF9131 EK +########## + +Overview +******** + +The nRF9131 EK (PCA10165) is a single-board evaluation kit for the nRF9131 SiP +for DECT NR+ and LTE-M/NB-IoT with GNSS. +The ``nrf9131ek/nrf9131`` board configuration provides support for the Nordic Semiconductor nRF9131 ARM +Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +.. figure:: img/nrf9131ek_nrf9131.webp + :align: center + :alt: nRF9131 EK + + nRF9131 EK (Credit: Nordic Semiconductor) + +The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF9131 EK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf9131ek/nrf9131`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +* LED (red) = P0.29 +* LED (green) = P0.30 +* LED (blue) = P0.31 + +Push buttons and Switches +------------------------- + +* BUTTON = P0.28 +* RESET + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + + +Programming and Debugging +************************* + +``nrf9131ek/nrf9131`` supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the nRF9131 may contain a Secure and a Non-Secure firmware +image. The Secure image can be built using either Zephyr or +`Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built +using Zephyr. The two alternatives are described below. + +.. note:: + + By default the Secure image for nRF9131 is built using TF-M. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=nrf9131ek/nrf9131`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9131ek/nrf9131/ns``. +3. Merge the two binaries together. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the Non-Secure +firmware image using Zephyr requires the following action: + +1. Build the Non-Secure Zephyr application + using ``-DBOARD=nrf9131ek/nrf9131/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may be + required, to adjust the Non-Secure image Flash and SRAM starting address + and sizes. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=nrf9131ek/nrf9131``. + + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9131 EK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf9131ek/nrf9131 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF9131 EK +********************************************** + +There are 2 samples that allow you to test that the button and LED on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi`. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131.dts b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131.dts similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131.dts rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131.dts diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131.yaml b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131.yaml similarity index 85% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131.yaml rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131.yaml index d1b04054ce8..8cb2adc385f 100644 --- a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131.yaml +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131.yaml @@ -1,4 +1,4 @@ -identifier: nrf9131ek_nrf9131 +identifier: nrf9131ek/nrf9131 name: nRF9131-EK-NRF9131 type: mcu arch: arm diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_common-pinctrl.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_common-pinctrl.dtsi rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_common.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_common.dtsi rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_defconfig b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_defconfig new file mode 100644 index 00000000000..4936d06617f --- /dev/null +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_PINCTRL=y diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns.dts b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns.dts rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns.yaml b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.yaml similarity index 84% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns.yaml rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.yaml index cf33abd55da..c6e312066bf 100644 --- a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns.yaml +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.yaml @@ -1,4 +1,4 @@ -identifier: nrf9131ek_nrf9131_ns +identifier: nrf9131ek/nrf9131/ns name: nRF9131-EK-NRF9131-Non-Secure type: mcu arch: arm diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns_defconfig b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns_defconfig new file mode 100644 index 00000000000..4051bf70caa --- /dev/null +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns_defconfig @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_PINCTRL=y + +# Enable PMIC +CONFIG_I2C=y +CONFIG_REGULATOR=y +CONFIG_SENSOR=y +CONFIG_NPM1300_CHARGER=y diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_partition_conf.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_partition_conf.dtsi rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131_partition_conf.dtsi diff --git a/boards/arm/nrf9160_innblue21/pre_dt_board.cmake b/boards/nordic/nrf9131ek/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9160_innblue21/pre_dt_board.cmake rename to boards/nordic/nrf9131ek/pre_dt_board.cmake diff --git a/boards/nordic/nrf9151dk/Kconfig.defconfig b/boards/nordic/nrf9151dk/Kconfig.defconfig new file mode 100644 index 00000000000..21f036f7607 --- /dev/null +++ b/boards/nordic/nrf9151dk/Kconfig.defconfig @@ -0,0 +1,44 @@ +# nRF9151 DK NRF9151 board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF9151DK_NRF9151 || BOARD_NRF9151DK_NRF9151_NS + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_NRF9151DK_NRF9151 && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF9151DK_NRF9151_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF9151DK_NRF9151_NS + +config BT_HCI_VS + default y if BT + +config BT_WAIT_NOP + default BT && $(dt_nodelabel_enabled,nrf5340_reset) + +config I2C + default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) + +endif # BOARD_NRF9151DK_NRF9151 || BOARD_NRF9151DK_NRF9151_NS diff --git a/boards/nordic/nrf9151dk/Kconfig.nrf9151dk b/boards/nordic/nrf9151dk/Kconfig.nrf9151dk new file mode 100644 index 00000000000..3125926cd8c --- /dev/null +++ b/boards/nordic/nrf9151dk/Kconfig.nrf9151dk @@ -0,0 +1,7 @@ +# nRF9151 DK NRF9151 board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF9151DK + select SOC_NRF9151_LACA diff --git a/boards/arm/nrf9151dk_nrf9151/board.cmake b/boards/nordic/nrf9151dk/board.cmake similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/board.cmake rename to boards/nordic/nrf9151dk/board.cmake diff --git a/boards/nordic/nrf9151dk/board.yml b/boards/nordic/nrf9151dk/board.yml new file mode 100644 index 00000000000..f765134a460 --- /dev/null +++ b/boards/nordic/nrf9151dk/board.yml @@ -0,0 +1,7 @@ +board: + name: nrf9151dk + vendor: nordic + socs: + - name: nrf9151 + variants: + - name: 'ns' diff --git a/boards/nordic/nrf9151dk/doc/index.rst b/boards/nordic/nrf9151dk/doc/index.rst new file mode 100644 index 00000000000..a3a56f632c6 --- /dev/null +++ b/boards/nordic/nrf9151dk/doc/index.rst @@ -0,0 +1,203 @@ +.. _nrf9151dk_nrf9151: + +nRF9151 DK +########## + +Overview +******** + +The nRF9151 DK (PCA10171) is a single-board development kit for evaluation and +development on the nRF9151 SiP for DECT NR+ and LTE-M/NB-IoT with GNSS. The ``nrf9151dk/nrf9151`` +board configuration provides support for the Nordic Semiconductor nRF9151 ARM +Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +More information about the board can be found at the +`nRF9151 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF9151 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf9151dk/nrf9151`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| FLASH | external | spi | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GPIO | external | i2c | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | nRF53 | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + + +.. _nrf9151dk_additional_hardware: + +Other hardware features have not been enabled yet for this board. +See `nRF9151 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF9151 DK board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.0 +* LED2 (green) = P0.1 +* LED3 (green) = P0.4 +* LED4 (green) = P0.5 + +Push buttons and Switches +------------------------- + +* BUTTON1 = P0.8 +* BUTTON2 = P0.9 +* SWITCH1 = P0.18 +* SWITCH2 = P0.19 +* BOOT = SW5 = boot/reset + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + + +Programming and Debugging +************************* + +``nrf9151dk/nrf9151`` supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=nrf9151dk/nrf9151`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9151dk/nrf9151/ns``. +3. Merge the two binaries together. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=nrf9151dk/nrf9151``. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9151 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf9151dk/nrf9151 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF9151 DK +********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi`. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _nRF9151 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9151-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9151dk_nrf9151/dts/bindings/nordic,nrf9151dk-nrf5340-reset.yaml b/boards/nordic/nrf9151dk/dts/bindings/nordic,nrf9151dk-nrf5340-reset.yaml similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/dts/bindings/nordic,nrf9151dk-nrf5340-reset.yaml rename to boards/nordic/nrf9151dk/dts/bindings/nordic,nrf9151dk-nrf5340-reset.yaml diff --git a/boards/arm/nrf9151dk_nrf9151/dts/nrf9151dk_buttons_on_io_expander.dtsi b/boards/nordic/nrf9151dk/dts/nrf9151dk_buttons_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/dts/nrf9151dk_buttons_on_io_expander.dtsi rename to boards/nordic/nrf9151dk/dts/nrf9151dk_buttons_on_io_expander.dtsi diff --git a/boards/arm/nrf9151dk_nrf9151/dts/nrf9151dk_leds_on_io_expander.dtsi b/boards/nordic/nrf9151dk/dts/nrf9151dk_leds_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/dts/nrf9151dk_leds_on_io_expander.dtsi rename to boards/nordic/nrf9151dk/dts/nrf9151dk_leds_on_io_expander.dtsi diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151.dts b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151.dts similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151.dts rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151.dts diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151.yaml b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151.yaml similarity index 89% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151.yaml rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151.yaml index 3ad90fea76d..aa4473d49ea 100644 --- a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151.yaml +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151.yaml @@ -1,4 +1,4 @@ -identifier: nrf9151dk_nrf9151 +identifier: nrf9151dk/nrf9151 name: nRF9151-DK-NRF9151 type: mcu arch: arm diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_common-pinctrl.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_common-pinctrl.dtsi rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_common.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_common.dtsi rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_defconfig b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns.dts b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns.dts rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns.yaml b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.yaml similarity index 88% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns.yaml rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.yaml index c5d4fe92541..97e78ff3736 100644 --- a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns.yaml +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.yaml @@ -1,4 +1,4 @@ -identifier: nrf9151dk_nrf9151_ns +identifier: nrf9151dk/nrf9151/ns name: nRF9151-DK-NRF9151-Non-Secure type: mcu arch: arm diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns_defconfig b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns_defconfig new file mode 100644 index 00000000000..2a74dd56f41 --- /dev/null +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_partition_conf.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_partition_conf.dtsi rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151_partition_conf.dtsi diff --git a/boards/arm/nrf9160_innblue22/pre_dt_board.cmake b/boards/nordic/nrf9151dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9160_innblue22/pre_dt_board.cmake rename to boards/nordic/nrf9151dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf9160dk/CMakeLists.txt b/boards/nordic/nrf9160dk/CMakeLists.txt new file mode 100644 index 00000000000..6b0e7e4ce64 --- /dev/null +++ b/boards/nordic/nrf9160dk/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2019 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF9160DK_NRF9160) + zephyr_library() + zephyr_library_sources(nrf52840_reset.c) +elseif(CONFIG_BOARD_NRF9160DK_NRF52840) + zephyr_library() + zephyr_library_sources(board.c) +endif() diff --git a/boards/nordic/nrf9160dk/Kconfig b/boards/nordic/nrf9160dk/Kconfig new file mode 100644 index 00000000000..92b1b9a892a --- /dev/null +++ b/boards/nordic/nrf9160dk/Kconfig @@ -0,0 +1,23 @@ +# nRF9160 DK NRF52840 board configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF9160DK + # The GPIO driver is required by this board's initialization code + # (board.c), so it is forced here to be enabled always, not only + # enabled by default (in defconfig). + select GPIO if BOARD_NRF9160DK_NRF52840 + +if BOARD_NRF9160DK_NRF52840 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +module = BOARD_NRF9160DK +module-str = Board Control +source "subsys/logging/Kconfig.template.log_config" + +endif # BOARD_NRF9160DK_NRF52840 diff --git a/boards/nordic/nrf9160dk/Kconfig.defconfig b/boards/nordic/nrf9160dk/Kconfig.defconfig new file mode 100644 index 00000000000..11880ae2a13 --- /dev/null +++ b/boards/nordic/nrf9160dk/Kconfig.defconfig @@ -0,0 +1,54 @@ +# nRF9160 DK NRF9160 board configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_NRF9160DK_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF9160DK_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF9160DK_NRF9160_NS + +config BT_HCI_VS + default y if BT + +config BT_WAIT_NOP + default BT && $(dt_nodelabel_enabled,nrf52840_reset) + +config I2C + default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) + +endif # BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS + +if BOARD_NRF9160DK_NRF52840 + +config BT_CTLR + default BT + +config BT_WAIT_NOP + default BT && $(dt_nodelabel_enabled,reset_input) + +endif # BOARD_NRF9160DK_NRF52840 diff --git a/boards/nordic/nrf9160dk/Kconfig.nrf9160dk b/boards/nordic/nrf9160dk/Kconfig.nrf9160dk new file mode 100644 index 00000000000..c4c42657c37 --- /dev/null +++ b/boards/nordic/nrf9160dk/Kconfig.nrf9160dk @@ -0,0 +1,8 @@ +# nRF9160 DK NRF9160 board configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF9160DK + select SOC_NRF9160_SICA if BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS + select SOC_NRF52840_QIAA if BOARD_NRF9160DK_NRF52840 diff --git a/boards/arm/nrf9160dk_nrf52840/board.c b/boards/nordic/nrf9160dk/board.c similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/board.c rename to boards/nordic/nrf9160dk/board.c diff --git a/boards/nordic/nrf9160dk/board.cmake b/boards/nordic/nrf9160dk/board.cmake new file mode 100644 index 00000000000..8bb0e688183 --- /dev/null +++ b/boards/nordic/nrf9160dk/board.cmake @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF9160DK_NRF9160 OR CONFIG_BOARD_NRF9160DK_NRF9160_NS) + if(CONFIG_BOARD_NRF9160DK_NRF9160_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") + endif() + + if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) + endif() + + board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") + include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) + include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +elseif(CONFIG_BOARD_NRF9160DK_NRF52840) + board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") + include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) + include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) +endif() diff --git a/boards/nordic/nrf9160dk/board.yml b/boards/nordic/nrf9160dk/board.yml new file mode 100644 index 00000000000..5e6dcfad89b --- /dev/null +++ b/boards/nordic/nrf9160dk/board.yml @@ -0,0 +1,14 @@ +board: + name: nrf9160dk + vendor: nordic + socs: + - name: nrf9160 + variants: + - name: 'ns' + - name: nrf52840 + revision: + format: major.minor.patch + default: "0.14.0" + revisions: + - name: "0.7.0" + - name: "0.14.0" diff --git a/boards/arm/nrf9160dk_nrf9160/doc/img/nrf9160dk_nrf9160.jpg b/boards/nordic/nrf9160dk/doc/img/nrf9160dk_nrf9160.jpg similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/doc/img/nrf9160dk_nrf9160.jpg rename to boards/nordic/nrf9160dk/doc/img/nrf9160dk_nrf9160.jpg diff --git a/boards/nordic/nrf9160dk/doc/index.rst b/boards/nordic/nrf9160dk/doc/index.rst new file mode 100644 index 00000000000..0e8a3171a22 --- /dev/null +++ b/boards/nordic/nrf9160dk/doc/index.rst @@ -0,0 +1,531 @@ +.. _nrf9160dk_nrf9160: + +nRF9160 DK +########## + +Overview +******** + +The nRF9160 DK (PCA10090) is a single-board development kit for evaluation and +development on the nRF9160 SiP for LTE-M and NB-IoT. The nrf9160dk/nrf9160 +board configuration provides support for the Nordic Semiconductor nRF9160 ARM +Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +.. figure:: img/nrf9160dk_nrf9160.jpg + :align: center + :alt: nRF9160 DK + + nRF9160 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the +`nRF9160 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF9160 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The nrf9160dk/nrf9160 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +.. _nrf9160dk_additional_hardware: + +Additional hardware in v0.14.0+ +------------------------------- + +Starting from v0.14.0, additional hardware is available on the DK: + +* External flash memory (MX25R6435F, 64 Mb) +* I/O expander (PCAL6408A) that can be used to interface LEDs, slide switches, + and buttons + +To use this additional hardware, specify the revision of the board that +should be used when building your application (for more information, see +:ref:`application_board_version`). For example, to build for nRF9160 DK v1.0.0: + +.. zephyr-app-commands:: + :tool: all + :cd-into: + :board: nrf9160dk/nrf9160@1.0.0 + :goals: build + :compact: + +Remember to also enable routing for this additional hardware in the firmware for +:ref:`nrf9160dk_nrf52840` (see :ref:`nrf9160dk_board_controller_firmware`). + +Other hardware features have not been enabled yet for this board. +See `nRF9160 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF9160 DK board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.2 +* LED2 (green) = P0.3 +* LED3 (green) = P0.4 +* LED4 (green) = P0.5 + +Push buttons and Switches +------------------------- + +* BUTTON1 = P0.6 +* BUTTON2 = P0.7 +* SWITCH1 = P0.8 +* SWITCH2 = P0.9 +* BOOT = SW5 = boot/reset + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + + +Programming and Debugging +************************* + +nrf9160dk/nrf9160 supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the nRF9160 may contain a Secure and a Non-Secure firmware +image. The Secure image can be built using either Zephyr or +`Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built +using Zephyr. The two alternatives are described below. + +.. note:: + + By default the Secure image for nRF9160 is built using TF-M. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=nrf9160dk/nrf9160`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9160dk/nrf9160/ns``. +3. Merge the two binaries together. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the Non-Secure +firmware image using Zephyr requires the following action: + +1. Build the Non-Secure Zephyr application + using ``-DBOARD=nrf9160dk_nrf9160_ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may be + required, to adjust the Non-Secure image Flash and SRAM starting address + and sizes. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=nrf9160dk/nrf9160``. + + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9160 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf9160dk/nrf9160 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF9160 DK +********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic_nrf/nrf9160dk/nrf9160dk_nrf9160_common.dtsi`. + +.. _nrf9160dk_nrf52840: + +nRF9160 DK - nRF52840 +##################### + +Overview +******** + +The nRF52840 SoC on the nRF9160 DK (PCA10090) hardware provides support for the +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: + +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +The nRF52840 SoC does not have any connection to the any of the LEDs, +buttons, switches, and Arduino pin headers on the nRF9160 DK board. It is, +however, possible to route some of the pins of the nRF52840 SoC to the nRF9160 +SiP. + +More information about the board can be found at +the `Nordic Low power cellular IoT`_ website. +The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +The nRF9160 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The nrf9160dk/nrf52840 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Programming and Debugging +************************* + +Applications for the ``nrf9160dk/nrf52840`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + +Make sure that the PROG/DEBUG switch on the DK is set to nRF52. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Remember to set the PROG/DEBUG switch on the DK to nRF52. + +See the following example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF52840 SoC is connected +to. Usually, under Linux it will be ``/dev/ttyACM1``. The ``/dev/ttyACM0`` +port is connected to the nRF9160 SiP on the board. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf9160dk/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards +with a Segger IC. + +Remember to set the PROG/DEBUG switch on the DK to nRF52. + +.. _nrf9160dk_board_controller_firmware: + +Board controller firmware +************************* + +The board controller firmware is a small snippet of code that takes care of +routing specific pins of the nRF9160 SiP to different components on the DK, +such as LEDs and buttons, UART interfaces (VCOMx) of the interface MCU, and +specific nRF52840 SoC pins. + +.. note:: + In nRF9160 DK revisions earlier than v0.14.0, nRF9160 signals routed to + other components on the DK are not simultaneously available on the DK + connectors. + +When compiling a project for nrf9160dk/nrf52840, the board controller firmware +will be compiled and run automatically after the Kernel has been initialized. + +By default, the board controller firmware will route the following: + ++--------------------------------+----------------------------------+ +| nRF9160 pins | Routed to | ++================================+==================================+ +| P0.26, P0.27, P0.28, and P0.29 | VCOM0 | ++--------------------------------+----------------------------------+ +| P0.01, P0.00, P0.15, and P0.14 | VCOM2 | ++--------------------------------+----------------------------------+ +| P0.02 | LED1 | ++--------------------------------+----------------------------------+ +| P0.03 | LED2 | ++--------------------------------+----------------------------------+ +| P0.04 | LED3 | ++--------------------------------+----------------------------------+ +| P0.05 | LED4 | ++--------------------------------+----------------------------------+ +| P0.08 | Switch 1 | ++--------------------------------+----------------------------------+ +| P0.09 | Switch 2 | ++--------------------------------+----------------------------------+ +| P0.06 | Button 1 | ++--------------------------------+----------------------------------+ +| P0.07 | Button 2 | ++--------------------------------+----------------------------------+ +| P0.17, P0.18, and P0.19 | Arduino pin headers | ++--------------------------------+----------------------------------+ +| P0.21, P0.22, and P0.23 | Trace interface | ++--------------------------------+----------------------------------+ +| COEX0, COEX1, and COEX2 | COEX interface | ++--------------------------------+----------------------------------+ + +For a complete list of all the routing options available, +see the `nRF9160 DK board control section in the nRF9160 DK User Guide`_. + +If you want to route some of the above pins differently or enable any of the +other available routing options, enable or disable the devicetree node that +represents the analog switch that provides the given routing. + +The following devicetree nodes are defined for the analog switches present +on the nRF9160 DK: + ++------------------------------------+------------------------------+ +| Devicetree node label | Analog switch name | ++====================================+==============================+ +| ``vcom0_pins_routing`` | nRF91_UART1 (nRF91_APP1) | ++------------------------------------+------------------------------+ +| ``vcom2_pins_routing`` | nRF91_UART2 (nRF91_APP2) | ++------------------------------------+------------------------------+ +| ``led1_pin_routing`` | nRF91_LED1 | ++------------------------------------+------------------------------+ +| ``led2_pin_routing`` | nRF91_LED2 | ++------------------------------------+------------------------------+ +| ``led3_pin_routing`` | nRF91_LED3 | ++------------------------------------+------------------------------+ +| ``led4_pin_routing`` | nRF91_LED4 | ++------------------------------------+------------------------------+ +| ``switch1_pin_routing`` | nRF91_SWITCH1 | ++------------------------------------+------------------------------+ +| ``switch2_pin_routing`` | nRF91_SWITCH2 | ++------------------------------------+------------------------------+ +| ``button1_pin_routing`` | nRF91_BUTTON1 | ++------------------------------------+------------------------------+ +| ``button2_pin_routing`` | nRF91_BUTTON2 | ++------------------------------------+------------------------------+ +| ``nrf_interface_pins_0_2_routing`` | nRF_IF0-2_CTRL (nRF91_GPIO) | ++------------------------------------+------------------------------+ +| ``nrf_interface_pins_3_5_routing`` | nRF_IF3-5_CTRL (nRF91_TRACE) | ++------------------------------------+------------------------------+ +| ``nrf_interface_pins_6_8_routing`` | nRF_IF6-8_CTRL (nRF91_COEX) | ++------------------------------------+------------------------------+ + +When building for the DK revision 0.14.0 or later, you can use the following +additional nodes (see :ref:`application_board_version` for information how to +build for specific revisions of the board): + ++------------------------------------+------------------------------+ +| Devicetree node label | Analog switch name | ++====================================+==============================+ +| ``nrf_interface_pin_9_routing`` | nRF_IF9_CTRL | ++------------------------------------+------------------------------+ +| ``io_expander_pins_routing`` | IO_EXP_EN | ++------------------------------------+------------------------------+ +| ``external_flash_pins_routing`` | EXT_MEM_CTRL | ++------------------------------------+------------------------------+ + +For example, if you want to enable the optional routing for the nRF9160 pins +P0.17, P0.18, and P0.19 so that they are routed to nRF52840 pins P0.17, P0.20, +and P0.15, respectively, add the following in the devicetree overlay in your +application: + +.. code-block:: devicetree + + &nrf_interface_pins_0_2_routing { + status = "okay"; + }; + +And if you want to, for example, disable routing for the VCOM2 pins, add the +following: + +.. code-block:: devicetree + + &vcom2_pins_routing { + status = "disabled"; + }; + +A few helper .dtsi files are provided in the directories +:zephyr_file:`boards/nordic_nrf/nrf9160dk/dts/nrf52840` and +:zephyr_file:`boards/nordic_nrf/nrf9160dk/dts/nrf9160`. They can serve as examples of +how to configure and use the above routings. You can also include them from +respective devicetree overlay files in your applications to conveniently +configure the signal routing between nRF9160 and nRF52840 on the nRF9160 DK. +For example, to use ``uart1`` on both these chips for communication between +them, add the following line in the overlays for applications on both sides, nRF52840: + +.. code-block:: devicetree + + #include + +nRF9160: + +.. code-block:: devicetree + + #include + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _nRF9160 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9160-DK +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ +.. _Nordic Low power cellular IoT: https://www.nordicsemi.com/Products/Low-power-cellular-IoT +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _nRF9160 DK board control section in the nRF9160 DK User Guide: https://infocenter.nordicsemi.com/topic/ug_nrf91_dk/UG/nrf91_DK/board_controller.html diff --git a/boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml b/boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml rename to boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml diff --git a/boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml b/boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml rename to boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml diff --git a/boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-optional-routing.yaml b/boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-optional-routing.yaml similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-optional-routing.yaml rename to boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-optional-routing.yaml diff --git a/boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_buttons_on_io_expander.dtsi b/boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_buttons_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_buttons_on_io_expander.dtsi rename to boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_buttons_on_io_expander.dtsi diff --git a/boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_leds_on_io_expander.dtsi b/boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_leds_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_leds_on_io_expander.dtsi rename to boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_leds_on_io_expander.dtsi diff --git a/boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_nrf52840_reset_on_if5.dtsi b/boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_nrf52840_reset_on_if5.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_nrf52840_reset_on_if5.dtsi rename to boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_nrf52840_reset_on_if5.dtsi diff --git a/boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_nrf52840_reset_on_if9.dtsi b/boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_nrf52840_reset_on_if9.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_nrf52840_reset_on_if9.dtsi rename to boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_nrf52840_reset_on_if9.dtsi diff --git a/boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_uart1_on_if0_3.dtsi b/boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_uart1_on_if0_3.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_uart1_on_if0_3.dtsi rename to boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_uart1_on_if0_3.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_buttons_on_io_expander.dtsi b/boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_buttons_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_buttons_on_io_expander.dtsi rename to boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_buttons_on_io_expander.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_leds_on_io_expander.dtsi b/boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_leds_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_leds_on_io_expander.dtsi rename to boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_leds_on_io_expander.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_nrf52840_reset_on_if5.dtsi b/boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_nrf52840_reset_on_if5.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_nrf52840_reset_on_if5.dtsi rename to boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_nrf52840_reset_on_if5.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_nrf52840_reset_on_if9.dtsi b/boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_nrf52840_reset_on_if9.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_nrf52840_reset_on_if9.dtsi rename to boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_nrf52840_reset_on_if9.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_uart1_on_if0_3.dtsi b/boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_uart1_on_if0_3.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_uart1_on_if0_3.dtsi rename to boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_uart1_on_if0_3.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/nrf52840_reset.c b/boards/nordic/nrf9160dk/nrf52840_reset.c similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf52840_reset.c rename to boards/nordic/nrf9160dk/nrf52840_reset.c diff --git a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840-pinctrl.dtsi rename to boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi diff --git a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.dts b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840.dts similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.dts rename to boards/nordic/nrf9160dk/nrf9160dk_nrf52840.dts diff --git a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840_0_14_0.overlay b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_14_0.overlay similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840_0_14_0.overlay rename to boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_14_0.overlay diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_14_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_14_0.yaml new file mode 100644 index 00000000000..2219fa3b3a4 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_14_0.yaml @@ -0,0 +1,14 @@ +identifier: nrf9160dk/nrf52840 +name: nRF9160-DK-NRF52840 +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - ble + - netif:openthread + - gpio +vendor: nordic diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_7_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_7_0.yaml new file mode 100644 index 00000000000..20b76523286 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_7_0.yaml @@ -0,0 +1,14 @@ +identifier: nrf9160dk@0.7.0/nrf52840 +name: nRF9160-DK-NRF52840 +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - ble + - netif:openthread + - gpio +vendor: nordic diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_defconfig b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_defconfig new file mode 100644 index 00000000000..cfe82dd2678 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160.dts b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160.dts similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160.dts rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160.dts diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_0_14_0.overlay b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.overlay similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_0_14_0.overlay rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.overlay diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.yaml new file mode 100644 index 00000000000..71e5bc2d0b3 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.yaml @@ -0,0 +1,22 @@ +identifier: nrf9160dk/nrf9160 +name: nRF9160-DK-NRF9160 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 1024 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: nordic diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_7_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_7_0.yaml new file mode 100644 index 00000000000..d66078fde8b --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_7_0.yaml @@ -0,0 +1,22 @@ +identifier: nrf9160dk@0.7.0/nrf9160 +name: nRF9160-DK-NRF9160 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 1024 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: nordic diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common-pinctrl.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common-pinctrl.dtsi rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common.dtsi rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common_0_14_0.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common_0_14_0.dtsi rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_defconfig b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns.dts b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns.dts rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns_0_14_0.overlay b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.overlay similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns_0_14_0.overlay rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.overlay diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.yaml new file mode 100644 index 00000000000..d610095afaf --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.yaml @@ -0,0 +1,21 @@ +identifier: nrf9160dk/nrf9160/ns +name: nRF9160-DK-NRF9160-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - i2c + - pwm + - watchdog + - netif:modem + - gpio +vendor: nordic diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_7_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_7_0.yaml new file mode 100644 index 00000000000..1957bc3ad25 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_7_0.yaml @@ -0,0 +1,21 @@ +identifier: nrf9160dk@0.7.0/nrf9160/ns +name: nRF9160-DK-NRF9160-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - i2c + - pwm + - watchdog + - netif:modem + - gpio +vendor: nordic diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_defconfig b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_defconfig new file mode 100644 index 00000000000..624f98b1da3 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable uart driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_partition_conf.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_partition_conf.dtsi rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_partition_conf.dtsi diff --git a/boards/arm/nrf52_blenano2/pre_dt_board.cmake b/boards/nordic/nrf9160dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52_blenano2/pre_dt_board.cmake rename to boards/nordic/nrf9160dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf9161dk/Kconfig.defconfig b/boards/nordic/nrf9161dk/Kconfig.defconfig new file mode 100644 index 00000000000..3790d580a29 --- /dev/null +++ b/boards/nordic/nrf9161dk/Kconfig.defconfig @@ -0,0 +1,44 @@ +# nRF9161 DK NRF9161 board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF9161DK_NRF9161 || BOARD_NRF9161DK_NRF9161_NS + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_NRF9161DK_NRF9161 && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF9161DK_NRF9161_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF9161DK_NRF9161_NS + +config BT_HCI_VS + default y if BT + +config BT_WAIT_NOP + default BT && $(dt_nodelabel_enabled,nrf5340_reset) + +config I2C + default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) + +endif # BOARD_NRF9161DK_NRF9161 || BOARD_NRF9161DK_NRF9161_NS diff --git a/boards/nordic/nrf9161dk/Kconfig.nrf9161dk b/boards/nordic/nrf9161dk/Kconfig.nrf9161dk new file mode 100644 index 00000000000..ff03a9d421f --- /dev/null +++ b/boards/nordic/nrf9161dk/Kconfig.nrf9161dk @@ -0,0 +1,7 @@ +# nRF9161 DK NRF9161 board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF9161DK + select SOC_NRF9161_LACA diff --git a/boards/arm/nrf9161dk_nrf9161/board.cmake b/boards/nordic/nrf9161dk/board.cmake similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/board.cmake rename to boards/nordic/nrf9161dk/board.cmake diff --git a/boards/nordic/nrf9161dk/board.yml b/boards/nordic/nrf9161dk/board.yml new file mode 100644 index 00000000000..9bffcec81a6 --- /dev/null +++ b/boards/nordic/nrf9161dk/board.yml @@ -0,0 +1,13 @@ +board: + name: nrf9161dk + vendor: nordic + socs: + - name: nrf9161 + variants: + - name: 'ns' + revision: + format: major.minor.patch + default: "0.9.0" + revisions: + - name: "0.7.0" + - name: "0.9.0" diff --git a/boards/nordic/nrf9161dk/doc/index.rst b/boards/nordic/nrf9161dk/doc/index.rst new file mode 100644 index 00000000000..8b3a7fb0236 --- /dev/null +++ b/boards/nordic/nrf9161dk/doc/index.rst @@ -0,0 +1,203 @@ +.. _nrf9161dk_nrf9161: + +nRF9161 DK +########## + +Overview +******** + +The nRF9161 DK (PCA10153) is a single-board development kit for evaluation and +development on the nRF9161 SiP for DECT NR+ and LTE-M/NB-IoT with GNSS. The ``nrf9161dk/nrf9161`` +board configuration provides support for the Nordic Semiconductor nRF9161 ARM +Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +More information about the board can be found at the +`nRF9161 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF9161 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf9161dk/nrf9161`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| FLASH | external | spi | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GPIO | external | i2c | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | nRF53 | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + + +.. _nrf9161dk_additional_hardware: + +Other hardware features have not been enabled yet for this board. +See `nRF9161 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF9161 DK board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.0 +* LED2 (green) = P0.1 +* LED3 (green) = P0.4 +* LED4 (green) = P0.5 + +Push buttons and Switches +------------------------- + +* BUTTON1 = P0.8 +* BUTTON2 = P0.9 +* SWITCH1 = P0.18 +* SWITCH2 = P0.19 +* BOOT = SW5 = boot/reset + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + + +Programming and Debugging +************************* + +``nrf9161dk/nrf9161`` supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=nrf9161dk/nrf9161`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9161dk/nrf9161/ns``. +3. Merge the two binaries together. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=nrf9161dk/nrf9161``. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9161 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf9161dk/nrf9161 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF9161 DK +********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi`. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _nRF9161 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9161-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9161dk_nrf9161/dts/bindings/nordic,nrf9161dk-nrf5340-reset.yaml b/boards/nordic/nrf9161dk/dts/bindings/nordic,nrf9161dk-nrf5340-reset.yaml similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/dts/bindings/nordic,nrf9161dk-nrf5340-reset.yaml rename to boards/nordic/nrf9161dk/dts/bindings/nordic,nrf9161dk-nrf5340-reset.yaml diff --git a/boards/arm/nrf9161dk_nrf9161/dts/nrf9161dk_buttons_on_io_expander.dtsi b/boards/nordic/nrf9161dk/dts/nrf9161dk_buttons_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/dts/nrf9161dk_buttons_on_io_expander.dtsi rename to boards/nordic/nrf9161dk/dts/nrf9161dk_buttons_on_io_expander.dtsi diff --git a/boards/arm/nrf9161dk_nrf9161/dts/nrf9161dk_leds_on_io_expander.dtsi b/boards/nordic/nrf9161dk/dts/nrf9161dk_leds_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/dts/nrf9161dk_leds_on_io_expander.dtsi rename to boards/nordic/nrf9161dk/dts/nrf9161dk_leds_on_io_expander.dtsi diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161.dts b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161.dts similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161.dts rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161.dts diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_0_7_0.overlay b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.overlay similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_0_7_0.overlay rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.overlay diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.yaml new file mode 100644 index 00000000000..47842c49d46 --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.yaml @@ -0,0 +1,22 @@ +identifier: nrf9161dk@0.7.0/nrf9161 +name: nRF9161-DK-NRF9161 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 1024 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: nordic diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_9_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_9_0.yaml new file mode 100644 index 00000000000..55e021d3f68 --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_9_0.yaml @@ -0,0 +1,22 @@ +identifier: nrf9161dk/nrf9161 +name: nRF9161-DK-NRF9161 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 1024 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: nordic diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common-pinctrl.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common-pinctrl.dtsi rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common.dtsi rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common_0_7_0.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common_0_7_0.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common_0_7_0.dtsi rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common_0_7_0.dtsi diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_defconfig b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns.dts b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns.dts rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns_0_7_0.overlay b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.overlay similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns_0_7_0.overlay rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.overlay diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.yaml new file mode 100644 index 00000000000..fd95098a773 --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.yaml @@ -0,0 +1,20 @@ +identifier: nrf9161dk@0.7.0/nrf9161/ns +name: nRF9161-DK-NRF9161-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - i2c + - pwm + - watchdog + - netif:modem +vendor: nordic diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_9_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_9_0.yaml new file mode 100644 index 00000000000..13cf209bc2d --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_9_0.yaml @@ -0,0 +1,20 @@ +identifier: nrf9161dk/nrf9161/ns +name: nRF9161-DK-NRF9161-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - i2c + - pwm + - watchdog + - netif:modem +vendor: nordic diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_defconfig b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_defconfig new file mode 100644 index 00000000000..2a74dd56f41 --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_partition_conf.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_partition_conf.dtsi rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_partition_conf.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/pre_dt_board.cmake b/boards/nordic/nrf9161dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/pre_dt_board.cmake rename to boards/nordic/nrf9161dk/pre_dt_board.cmake diff --git a/boards/nordic/thingy52/CMakeLists.txt b/boards/nordic/thingy52/CMakeLists.txt new file mode 100644 index 00000000000..94f5692b56a --- /dev/null +++ b/boards/nordic/thingy52/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_CCS811) + zephyr_library() + zephyr_library_sources(board.c) +endif() diff --git a/boards/nordic/thingy52/Kconfig b/boards/nordic/thingy52/Kconfig new file mode 100644 index 00000000000..e9629096e28 --- /dev/null +++ b/boards/nordic/thingy52/Kconfig @@ -0,0 +1,17 @@ +# Thingy52 NRF52832 board configuration + +# Copyright (c) 2018 Aapo Vienamo +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_THINGY52 + +config BOARD_CCS_VDD_PWR_CTRL_INIT_PRIORITY + int "CCS_VDD power rail init priority" + default 85 + depends on GPIO_SX1509B + help + Initialization priority for the CCS_VDD power rail. This powers the + CCS811 gas sensor. The value has to be greater than + BOARD_VDD_PWR_CTRL_INIT_PRIORITY, but smaller than SENSOR_INIT_PRIORITY. + +endif # BOARD_THINGY52 diff --git a/boards/nordic/thingy52/Kconfig.defconfig b/boards/nordic/thingy52/Kconfig.defconfig new file mode 100644 index 00000000000..40bdd8c6cdf --- /dev/null +++ b/boards/nordic/thingy52/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Thingy52 NRF52832 board configuration + +# Copyright (c) 2018 Aapo Vienamo +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_THINGY52 + +config BT_CTLR + default BT + +endif # BOARD_THINGY52 diff --git a/boards/nordic/thingy52/Kconfig.thingy52 b/boards/nordic/thingy52/Kconfig.thingy52 new file mode 100644 index 00000000000..433eb4a2a95 --- /dev/null +++ b/boards/nordic/thingy52/Kconfig.thingy52 @@ -0,0 +1,7 @@ +# Thingy52 NRF52832 board configuration + +# Copyright (c) 2018 Aapo Vienamo +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_THINGY52 + select SOC_NRF52832_QFAA diff --git a/boards/arm/thingy52_nrf52832/board.c b/boards/nordic/thingy52/board.c similarity index 100% rename from boards/arm/thingy52_nrf52832/board.c rename to boards/nordic/thingy52/board.c diff --git a/boards/arm/thingy52_nrf52832/board.cmake b/boards/nordic/thingy52/board.cmake similarity index 100% rename from boards/arm/thingy52_nrf52832/board.cmake rename to boards/nordic/thingy52/board.cmake diff --git a/boards/nordic/thingy52/board.yml b/boards/nordic/thingy52/board.yml new file mode 100644 index 00000000000..425e24fb596 --- /dev/null +++ b/boards/nordic/thingy52/board.yml @@ -0,0 +1,5 @@ +board: + name: thingy52 + vendor: nordic + socs: + - name: nrf52832 diff --git a/boards/arm/thingy52_nrf52832/doc/img/thingy52_nrf52832.jpg b/boards/nordic/thingy52/doc/img/thingy52_nrf52832.jpg similarity index 100% rename from boards/arm/thingy52_nrf52832/doc/img/thingy52_nrf52832.jpg rename to boards/nordic/thingy52/doc/img/thingy52_nrf52832.jpg diff --git a/boards/nordic/thingy52/doc/index.rst b/boards/nordic/thingy52/doc/index.rst new file mode 100644 index 00000000000..0dd8b6067b6 --- /dev/null +++ b/boards/nordic/thingy52/doc/index.rst @@ -0,0 +1,388 @@ +.. _thingy52_nrf52832: + +Thingy:52 +######### + +Overview +******** + +Zephyr uses the thingy52/nrf52832 (PCA20020) board configuration for building +for the Thingy:52 board. The board has the nRF52832 MCU with ARM Cortex-M4F +processor, a set of environmental sensors, a pushbutton, and two RGB LEDs. + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* Gas sensor +* :abbr:`GPIO (General Purpose Input Output)` +* GPIO Expander +* Humidity and temperature sensor +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* Pressure sensor +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* RGB LEDs +* :abbr:`RTC (nRF RTC System Clock)` +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/thingy52_nrf52832.jpg + :align: center + :alt: nRF52 Thingy:52 + + nRF52 Thingy:52 (Credit: Nordic Semiconductor) + +More information about the board can be found at the `nRF52 DK website`_. The +`Nordic Semiconductor Infocenter`_ contains the processor's information and the +datasheet. + + +Hardware +******** + +Thingy:52 has the following features: + +* Two RGB LEDs +* CO2 and TVOC sensor +* Humidity and temperature sensor +* Color sensor +* I2C GPIO expander +* Provisions for a pin header and I2C and serial connectors +* Bluetooth radio + +Supported Features +================== + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| Gas | on-board | ccs811 | +| Sensor | | | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GPIO Exp | on-board | sx1509b | ++-----------+------------+----------------------+ +| Humidity | on-board | hts221 | +| and Temp | | | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| Pressure | on-board | lps22hb_press | +| and Temp | | | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +Lightwell RGB LED +----------------- +The LED is driven by the SX1509B GPIO expander chip (device name GPIO_P0). + ++-------------------+-------------+ +| GPIO Expander Pin | LED Channel | ++===================+=============+ +| 5 | Green | ++-------------------+-------------+ +| 6 | Blue | ++-------------------+-------------+ +| 7 | Red | ++-------------------+-------------+ + +Button +------ + +Thingy:52 has a pushbutton, connected to the P0.11 SOC GPIO pin. + +Serial +------ + +By default the system UART has the following pin configuration: + ++---------+--------+ +| SOC Pin | Signal | ++=========+========+ +| P0.02 | TX | ++---------+--------+ +| P0.03 | RX | ++---------+--------+ + +The pins can be found on the P4 and P6 connectors. The system UART console +uses these pins by default. + +Internal I2C Bus +---------------- + +The internal I2C bus (I2C_0) is not routed to any of the external connectors, +but most of the on-board devices are accessed through it. The following pins +have been assigned to the bus: + ++---------+---------+ +| SOC Pin | Signal | ++=========+=========+ +| P0.07 | SDA | ++---------+---------+ +| P0.08 | SCL | ++---------+---------+ + +The following devices are attached to the bus. + ++----------+---------+ +| Device | Address | ++==========+=========+ +| SX1509B | 0x3e | ++----------+---------+ +| LPS22HB | 0x5c | ++----------+---------+ +| HTS221 | 0x5f | ++----------+---------+ +| CCS811 | 0x5a | ++----------+---------+ + +External I2C Bus +---------------- + +The external I2C bus (I2C_1) can be found on the P4 header and the P5 and P7 +connectors. + ++---------+---------+ +| SOC Pin | Signal | ++=========+=========+ +| P0.14 | SDA_EXT | ++---------+---------+ +| P0.15 | SCL_EXT | ++---------+---------+ + +Pin Header +---------- + +This is the pinout of the P4 pin header. Some of the SOC GPIO pins and I2C GPIO +expander pins are accessible through it. It also allows attaching external +devices to the four on-board N-channel MOSFET transistors. + ++-----+---------------+-----------------------+ +| Pin | Device | Signal / Device Pin | ++=====+===============+=======================+ +| 1 | SOC | SCL_EXT / P0.15 | ++-----+---------------+-----------------------+ +| 2 | SOC | SDA_EXT / P0.14 | ++-----+---------------+-----------------------+ +| 3 | SOC | ANA/DIG0 / P0.02 | ++-----+---------------+-----------------------+ +| 4 | SOC | ANA/DIG1 / P0.03 | ++-----+---------------+-----------------------+ +| 5 | SOC | ANA/DIG2 / P0.04 | ++-----+---------------+-----------------------+ +| 6 | | GND | ++-----+---------------+-----------------------+ +| 7 | GPIO Expander | Pin 0 | ++-----+---------------+-----------------------+ +| 8 | GPIO Expander | Pin 1 | ++-----+---------------+-----------------------+ +| 9 | GPIO Expander | Pin 2 | ++-----+---------------+-----------------------+ +| 10 | GPIO Expander | Pin 3 | ++-----+---------------+-----------------------+ +| 11 | MOSFET 1 | Drain | ++-----+---------------+-----------------------+ +| 12 | MOSFET 1 | Source | ++-----+---------------+-----------------------+ +| 13 | MOSFET 2 | Drain | ++-----+---------------+-----------------------+ +| 14 | MOSFET 2 | Source | ++-----+---------------+-----------------------+ +| 15 | MOSFET 3 | Drain | ++-----+---------------+-----------------------+ +| 16 | MOSFET 3 | Source | ++-----+---------------+-----------------------+ +| 17 | MOSFET 4 | Drain | ++-----+---------------+-----------------------+ +| 18 | MOSFET 4 | Source | ++-----+---------------+-----------------------+ +| 19 | | VDD | ++-----+---------------+-----------------------+ +| 20 | | GND | ++-----+---------------+-----------------------+ + +MOSFETs +~~~~~~~ + +The MOSFETs are attached to the following SOC GPIO pins: + ++----------+----------+ +| Device | Gate Pin | ++==========+==========+ +| MOSFET 1 | P0.18 | ++----------+----------+ +| MOSFET 2 | P0.19 | ++----------+----------+ +| MOSFET 3 | P0.20 | ++----------+----------+ +| MOSFET 4 | P0.21 | ++----------+----------+ + +Power Rails +----------- + +Thing:52 has multiple power rails. The necessary rails for the currently +supported devices are listed here. + ++---------+--------------+----------------------+ +| Name | Derived from | Controlled by | ++=========+==============+======================+ +| VREG | The battery | Always on | ++---------+--------------+----------------------+ +| VDD_nRF | VREG | Always on | ++---------+--------------+----------------------+ +| VDD | VREG | SOC pin P0.30 | ++---------+--------------+----------------------+ +| VDD_CCS | VDD | GPIO expander pin 10 | ++---------+--------------+----------------------+ + +Due to the dependencies of the power rails, multiple rails may need to be +powered for a given device to turn on. The correct order of powering up the +rails is the order of the rails down the dependency chain. For example, in order +to power the CCS811 gas sensor, VDD has to be turned on first and VDD_CCS after +it. Here's a list of the devices and their power rails: + ++----------+---------+ +| Device | Rail | ++==========+=========+ +| nRF52832 | VDD_nRF | ++----------+---------+ +| SX1509B | VDD | ++----------+---------+ +| LPS22HB | VDD | ++----------+---------+ +| HTS221 | VDD | ++----------+---------+ +| CCS811 | VDD_CCS | ++----------+---------+ + +Sensors +------- + ++----------+---------------------------------+-------+-------------+------------+ +| Device | Function | Bus | I2C Address | Power Rail | ++==========+=================================+=======+=============+============+ +| LPS22HB | Pressure and Temperature sensor | I2C_0 | 0x5c | VDD | ++----------+---------------------------------+-------+-------------+------------+ +| HTS221 | Humidity and Temperature sensor | I2C_0 | 0x5f | VDD | ++----------+---------------------------------+-------+-------------+------------+ +| CCS811 | Gas sensor | I2C_0 | 0x5a | VDD_CCS | ++----------+---------------------------------+-------+-------------+------------+ + +Misc. Device Pins +----------------- + +SX1509B +~~~~~~~ + ++---------------+-------------------+ +| Device Signal | SOC Pin | ++===============+===================+ +| SX_OSCIO | P0.05 | ++---------------+-------------------+ +| SX_RESET | P0.16 | ++---------------+-------------------+ + +LPS22HB +~~~~~~~ + ++---------------+-------------------+ +| Sensor Signal | SOC Pin | ++===============+===================+ +| LPS_INT | P0.23 | ++---------------+-------------------+ + +HTS221 +~~~~~~ + ++---------------+-------------------+ +| Sensor Signal | SOC Pin | ++===============+===================+ +| HTS_INT | P0.24 | ++---------------+-------------------+ + +CCS811 +~~~~~~ + ++---------------+-------------------+ +| Sensor Signal | GPIO Expander Pin | ++===============+===================+ +| CCS_RESET | 11 | ++---------------+-------------------+ +| CCS_WAKE | 12 | ++---------------+-------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Flashing Zephyr onto Thingy:52 requires an external J-Link programmer. The +programmer is attached to the P9 programming header. + + +Debugging +========= + +Thingy:52 does not have an on-board J-Link debug IC as some other nRF5 +development boards, however, instructions from the :ref:`nordic_segger` page +also apply to this board, with the additional step of connecting an external +debugger. A development board with a Debug out connector such as the +:ref:`nrf52dk_nrf52832` can be used as a debugger with Thingy:52. + +Testing board features +********************** + +The green lightwell LED can be tested with the :zephyr:code-sample:`blinky` example. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: thingy52/nrf52832 + :goals: build flash + + + +Also the temperature and humidity sensor can be tested with the :ref:`hts221` +sample. + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/hts221 + :board: thingy52/nrf52832 + :goals: build flash + +References +********** + +.. target-notes:: + +.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/Nordic-Thingy-52 +.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/nrf52_sparkfun/pre_dt_board.cmake b/boards/nordic/thingy52/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52_sparkfun/pre_dt_board.cmake rename to boards/nordic/thingy52/pre_dt_board.cmake diff --git a/boards/arm/thingy52_nrf52832/thingy52_nrf52832-pinctrl.dtsi b/boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/thingy52_nrf52832/thingy52_nrf52832-pinctrl.dtsi rename to boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi diff --git a/boards/arm/thingy52_nrf52832/thingy52_nrf52832.dts b/boards/nordic/thingy52/thingy52_nrf52832.dts similarity index 100% rename from boards/arm/thingy52_nrf52832/thingy52_nrf52832.dts rename to boards/nordic/thingy52/thingy52_nrf52832.dts diff --git a/boards/arm/thingy52_nrf52832/thingy52_nrf52832.yaml b/boards/nordic/thingy52/thingy52_nrf52832.yaml similarity index 84% rename from boards/arm/thingy52_nrf52832/thingy52_nrf52832.yaml rename to boards/nordic/thingy52/thingy52_nrf52832.yaml index c4aa66f67ce..a49aeaba6ce 100644 --- a/boards/arm/thingy52_nrf52832/thingy52_nrf52832.yaml +++ b/boards/nordic/thingy52/thingy52_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: thingy52_nrf52832 +identifier: thingy52/nrf52832 name: Thingy52-NRF52832 type: mcu arch: arm diff --git a/boards/nordic/thingy52/thingy52_nrf52832_defconfig b/boards/nordic/thingy52/thingy52_nrf52832_defconfig new file mode 100644 index 00000000000..401a71ab47a --- /dev/null +++ b/boards/nordic/thingy52/thingy52_nrf52832_defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2018 Aapo Vienamo +# SPDX-License-Identifier: Apache-2.0 + +# Enable regulators +CONFIG_REGULATOR=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + +# Enable regulators (init priority adjusted so that they +# are turned before I2C GPIO expander) +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_INIT_PRIORITY=45 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nordic/thingy53/CMakeLists.txt b/boards/nordic/thingy53/CMakeLists.txt new file mode 100644 index 00000000000..4cf3ec75526 --- /dev/null +++ b/boards/nordic/thingy53/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_THINGY53_NRF5340_CPUAPP OR CONFIG_BOARD_THINGY53_NRF5340_CPUAPP_NS) + zephyr_library() + zephyr_library_sources(board.c) +endif() diff --git a/boards/nordic/thingy53/Kconfig b/boards/nordic/thingy53/Kconfig new file mode 100644 index 00000000000..d7be16ff007 --- /dev/null +++ b/boards/nordic/thingy53/Kconfig @@ -0,0 +1,74 @@ +# Thingy53 NRF5340 board configuration + +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config THINGY53_INIT_PRIORITY + int "Init priority" + default 79 + help + Initialization priority of the Thingy:53. + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_SERIAL_BACKEND_CDC_ACM + bool "USB CDC" + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "thingy53/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS + +if BOARD_THINGY53_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "thingy53/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/nordic/thingy53/Kconfig.defconfig b/boards/nordic/thingy53/Kconfig.defconfig new file mode 100644 index 00000000000..701bd9be4e6 --- /dev/null +++ b/boards/nordic/thingy53/Kconfig.defconfig @@ -0,0 +1,146 @@ +# Thingy53 NRF5340 board configuration + +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_THINGY53_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_THINGY53_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_THINGY53_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_THINGY53_NRF5340_CPUAPP_NS + +if !TRUSTED_EXECUTION_SECURE + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +config BT_HAS_HCI_VS + default BT + +config USB_NRFX_ATTACHED_EVENT_DELAY + default 700 if USB_DEVICE_DRIVER + +config I2C + default y + +config SPI + default y + +config REGULATOR + default y + +endif # !TRUSTED_EXECUTION_SECURE + +if BOARD_SERIAL_BACKEND_CDC_ACM + +config USB_DEVICE_PRODUCT + default "Thingy:53 Application" + +config USB_DEVICE_VID + default 0x1915 + +config USB_DEVICE_PID + default 0x530C + +config USB_DEVICE_STACK + default y + +config USB_CDC_ACM + default y + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if !MCUBOOT + +config SHELL_BACKEND_SERIAL_CHECK_DTR + default SHELL + depends on UART_LINE_CTRL + +config UART_LINE_CTRL + default SHELL + +config USB_DEVICE_REMOTE_WAKEUP + default n + +if LOG + +# Logger cannot use itself to log +choice USB_CDC_ACM_LOG_LEVEL_CHOICE + default USB_CDC_ACM_LOG_LEVEL_OFF +endchoice + +# Set USB log level to error only +choice USB_DEVICE_LOG_LEVEL_CHOICE + default USB_DEVICE_LOG_LEVEL_ERR +endchoice + +# Wait 4000ms at startup for logging +config LOG_PROCESS_THREAD_STARTUP_DELAY_MS + default 4000 + +endif # LOG + +endif # BOARD_SERIAL_BACKEND_CDC_ACM + +endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS + +if BOARD_THINGY53_NRF5340_CPUNET + +config BT_CTLR + default BT + +config BT_ECC + default BT + +endif # BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/nordic/thingy53/Kconfig.thingy53 b/boards/nordic/thingy53/Kconfig.thingy53 new file mode 100644 index 00000000000..e7b23191373 --- /dev/null +++ b/boards/nordic/thingy53/Kconfig.thingy53 @@ -0,0 +1,9 @@ +# Thingy53 NRF5340 board configuration + +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_THINGY53 + select SOC_NRF5340_CPUAPP_QKAA if BOARD_THINGY53_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_THINGY53_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/arm/thingy53_nrf5340/board.c b/boards/nordic/thingy53/board.c similarity index 100% rename from boards/arm/thingy53_nrf5340/board.c rename to boards/nordic/thingy53/board.c diff --git a/boards/nordic/thingy53/board.cmake b/boards/nordic/thingy53/board.cmake new file mode 100644 index 00000000000..dc63ca31895 --- /dev/null +++ b/boards/nordic/thingy53/board.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_THINGY53_NRF5340_CPUAPP OR CONFIG_BOARD_THINGY53_NRF5340_CPUAPP_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(CONFIG_BOARD_THINGY53_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/thingy53/board.yml b/boards/nordic/thingy53/board.yml new file mode 100644 index 00000000000..4659222a346 --- /dev/null +++ b/boards/nordic/thingy53/board.yml @@ -0,0 +1,8 @@ +board: + name: thingy53 + vendor: nordic + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/nordic/thingy53/doc/index.rst b/boards/nordic/thingy53/doc/index.rst new file mode 100644 index 00000000000..e2f8b000f17 --- /dev/null +++ b/boards/nordic/thingy53/doc/index.rst @@ -0,0 +1,51 @@ +.. _thingy53_nrf5340: + +Thingy:53 +######### + +Overview +******** + +Zephyr uses the ``thingy53/nrf5340`` board configuration for building +for the Thingy:53 board. The board has the nRF5340 MCU processor, a set of +environmental sensors, a pushbutton, and RGB LED. + +The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with: + +* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and + Armv8-M Security Extension, running at up to 128 MHz, referred to as + the **application core** +* a secondary Arm Cortex-M33 core, with a reduced feature set, running at + a fixed 64 MHz, referred to as the **network core**. + +The ``thingy53/nrf5340/cpuapp`` build target provides support for the application +core on the nRF5340 SoC. The ``thingy53/nrf5340/cpunet`` build target provides +support for the network core on the nRF5340 SoC. + +The `Nordic Semiconductor Infocenter`_ contains the processor's information and +the datasheet. + +Programming and Debugging +************************* + +Flashing +======== + +Flashing Zephyr onto Thingy:53 requires an external J-Link programmer. The +programmer is attached to the P9 programming header. + +Debugging +========= + +Thingy:53 does not have an on-board J-Link debug IC as some other nRF5 +development boards, however, instructions from the :ref:`nordic_segger` page +also apply to this board, with the additional step of connecting an external +debugger. A development board with a Debug out connector such as the +:ref:`nrf5340dk_nrf5340` can be used as a debugger with Thingy:53. + +References +********** + +.. target-notes:: + +.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/pre_dt_board.cmake b/boards/nordic/thingy53/pre_dt_board.cmake similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/pre_dt_board.cmake rename to boards/nordic/thingy53/pre_dt_board.cmake diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_common-pinctrl.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_common-pinctrl.dtsi rename to boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_common.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_common.dtsi rename to boards/nordic/thingy53/thingy53_nrf5340_common.dtsi diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.dts rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml similarity index 86% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.yaml rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml index b4651427a22..fbc4eb33579 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.yaml +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml @@ -1,4 +1,4 @@ -identifier: thingy53_nrf5340_cpuapp +identifier: thingy53/nrf5340/cpuapp name: Thingy53-NRF5340-application-MCU type: mcu arch: arm diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_defconfig b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_defconfig similarity index 82% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_defconfig rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp_defconfig index 5f3fd735660..de1c1fd5964 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_defconfig +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_THINGY53_NRF5340_CPUAPP=y - # Enable MPU CONFIG_ARM_MPU=y @@ -20,7 +16,7 @@ CONFIG_GPIO=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Enable uart driver +# Enable UART driver CONFIG_SERIAL=y # Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.dts rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml similarity index 86% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.yaml rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml index d8db4ae1520..b534406ea07 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.yaml +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml @@ -1,4 +1,4 @@ -identifier: thingy53_nrf5340_cpuapp_ns +identifier: thingy53/nrf5340/cpuapp/ns name: Thingy53-NRF5340-application-MCU-Non-Secure type: mcu arch: arm diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns_defconfig b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns_defconfig similarity index 84% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns_defconfig rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns_defconfig index 23d7e5ff6e0..39dc91517e0 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns_defconfig +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_THINGY53_NRF5340_CPUAPP_NS=y - # Enable MPU CONFIG_ARM_MPU=y @@ -23,7 +19,7 @@ CONFIG_GPIO=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Enable uart driver +# Enable UART driver CONFIG_SERIAL=y # Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet-pinctrl.dtsi rename to boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet.dts rename to boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.yaml similarity index 82% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet.yaml rename to boards/nordic/thingy53/thingy53_nrf5340_cpunet.yaml index a41d496937f..c039c5ad9f4 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet.yaml +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.yaml @@ -1,4 +1,4 @@ -identifier: thingy53_nrf5340_cpunet +identifier: thingy53/nrf5340/cpunet name: Thingy53-NRF5340-network-MCU type: mcu arch: arm diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpunet_defconfig b/boards/nordic/thingy53/thingy53_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..c115d16a9d0 --- /dev/null +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpunet_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/arm/rddrone_fmuk66/CMakeLists.txt b/boards/nordic/thingy53/thingy53_nrf5340_defconfig similarity index 100% rename from boards/arm/rddrone_fmuk66/CMakeLists.txt rename to boards/nordic/thingy53/thingy53_nrf5340_defconfig diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_partition_conf.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_partition_conf.dtsi similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_partition_conf.dtsi rename to boards/nordic/thingy53/thingy53_nrf5340_partition_conf.dtsi diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_shared_sram_planning_conf.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_shared_sram_planning_conf.dtsi similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_shared_sram_planning_conf.dtsi rename to boards/nordic/thingy53/thingy53_nrf5340_shared_sram_planning_conf.dtsi diff --git a/boards/nuvoton/index.rst b/boards/nuvoton/index.rst new file mode 100644 index 00000000000..eec26543a0b --- /dev/null +++ b/boards/nuvoton/index.rst @@ -0,0 +1,10 @@ +.. _boards-nuvoton: + +Nuvoton Technology Corporation +############################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/nuvoton/npcx4m8f_evb/Kconfig.defconfig b/boards/nuvoton/npcx4m8f_evb/Kconfig.defconfig new file mode 100644 index 00000000000..4bd26c0d348 --- /dev/null +++ b/boards/nuvoton/npcx4m8f_evb/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config INPUT + default y if KSCAN diff --git a/boards/nuvoton/npcx4m8f_evb/Kconfig.npcx4m8f_evb b/boards/nuvoton/npcx4m8f_evb/Kconfig.npcx4m8f_evb new file mode 100644 index 00000000000..4483d2ee0c2 --- /dev/null +++ b/boards/nuvoton/npcx4m8f_evb/Kconfig.npcx4m8f_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NPCX4M8F_EVB + select SOC_NPCX4M8F diff --git a/boards/arm/npcx4m8f_evb/board.cmake b/boards/nuvoton/npcx4m8f_evb/board.cmake similarity index 100% rename from boards/arm/npcx4m8f_evb/board.cmake rename to boards/nuvoton/npcx4m8f_evb/board.cmake diff --git a/boards/nuvoton/npcx4m8f_evb/board.yml b/boards/nuvoton/npcx4m8f_evb/board.yml new file mode 100644 index 00000000000..16f6190d195 --- /dev/null +++ b/boards/nuvoton/npcx4m8f_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: npcx4m8f_evb + vendor: nuvoton + socs: + - name: npcx4m8f diff --git a/boards/nuvoton/npcx4m8f_evb/doc/index.rst b/boards/nuvoton/npcx4m8f_evb/doc/index.rst new file mode 100644 index 00000000000..928c4f2ce81 --- /dev/null +++ b/boards/nuvoton/npcx4m8f_evb/doc/index.rst @@ -0,0 +1,131 @@ +.. _npcx4m8f_evb: + +Nuvoton NPCX4M8F_EVB +#################### + +Overview +******** + +The NPCX4M8F_EVB kit is a development platform to evaluate the +Nuvoton NPCX4 series microcontrollers. This board needs to be mated with +part number NPCX498F. + +.. image:: npcx4m8f_evb.jpg + :align: center + :alt: NPCX4M8F Evaluation Board + +Hardware +******** + +- ARM Cortex-M4F Processor +- 512 KB RAM and 64 KB boot ROM +- ADC & GPIO headers +- UART0 and UART1 +- FAN PWM interface +- Jtag interface +- Intel Modular Embedded Controller Card (MECC) headers + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port/controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PM | on-chip | power management | ++-----------+------------+-------------------------------------+ +| PSL | on-chip | power switch logic | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pulse width modulator | ++-----------+------------+-------------------------------------+ +| TACH | on-chip | tachometer sensor | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig` + + +Connections and IOs +=================== + +Nuvoton to provide the schematic for this board. + +System Clock +============ + +The NPCX4M8F MCU is configured to use the 120Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock +control register (chapter 4 in user manual) + +Serial Port +=========== + +UART1 is configured for serial logs. + +Programming and Debugging +************************* + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG-only sessions. + +Flashing +======== + +If the correct headers are installed, this board supports both J-TAG and also +the ChromiumOS servo. + +To flash using Servo V2, μServo, or Servo V4 (CCD), see the +`Chromium EC Flashing Documentation`_ for more information. + +To flash with J-TAG, install the drivers for your programmer, for example: +SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ + +The openocd from Zephyr SDK 0.16.1 doesn't include npcx4 support, so build openocd from source.:: + + sudo apt-get install libftdi-dev libusb-1.0.0-dev + git clone https://git.code.sf.net/p/openocd/code ~/openocd + cd ~/openocd + ./bootstrap + ./configure --enable-jlink --enable-ftdi + make clean + make + sudo make install + +Build and flash the blinky sample.:: + + west build -t clean && \ + west build -c -p auto -b npcx4m8f_evb samples/basic/blinky && \ + west flash --openocd /usr/local/bin/openocd + +Debugging +========= + +Use JTAG/SWD with a J-Link + +References +********** +.. target-notes:: + +.. _Chromium EC Flashing Documentation: + https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/npcx4m8f_evb/doc/npcx4m8f_evb.jpg b/boards/nuvoton/npcx4m8f_evb/doc/npcx4m8f_evb.jpg similarity index 100% rename from boards/arm/npcx4m8f_evb/doc/npcx4m8f_evb.jpg rename to boards/nuvoton/npcx4m8f_evb/doc/npcx4m8f_evb.jpg diff --git a/boards/arm/npcx4m8f_evb/npcx4m8f_evb-pinctrl.dtsi b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/npcx4m8f_evb/npcx4m8f_evb-pinctrl.dtsi rename to boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb-pinctrl.dtsi diff --git a/boards/arm/npcx4m8f_evb/npcx4m8f_evb.dts b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts similarity index 100% rename from boards/arm/npcx4m8f_evb/npcx4m8f_evb.dts rename to boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts diff --git a/boards/arm/npcx4m8f_evb/npcx4m8f_evb.yaml b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.yaml similarity index 100% rename from boards/arm/npcx4m8f_evb/npcx4m8f_evb.yaml rename to boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.yaml diff --git a/boards/arm/npcx4m8f_evb/npcx4m8f_evb_defconfig b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig similarity index 88% rename from boards/arm/npcx4m8f_evb/npcx4m8f_evb_defconfig rename to boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig index 4ec779de482..05a91e020f3 100644 --- a/boards/arm/npcx4m8f_evb/npcx4m8f_evb_defconfig +++ b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig @@ -4,10 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_NPCX4M8F=y -CONFIG_SOC_SERIES_NPCX4=y -CONFIG_BOARD_NPCX4M8F_EVB=y - # Enable NPCX firmware header CONFIG_NPCX_HEADER=y CONFIG_NPCX_IMAGE_OUTPUT_HEX=y diff --git a/boards/arm/npcx4m8f_evb/support/openocd.cfg b/boards/nuvoton/npcx4m8f_evb/support/openocd.cfg similarity index 100% rename from boards/arm/npcx4m8f_evb/support/openocd.cfg rename to boards/nuvoton/npcx4m8f_evb/support/openocd.cfg diff --git a/boards/nuvoton/npcx7m6fb_evb/Kconfig.defconfig b/boards/nuvoton/npcx7m6fb_evb/Kconfig.defconfig new file mode 100644 index 00000000000..91a81edc353 --- /dev/null +++ b/boards/nuvoton/npcx7m6fb_evb/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config INPUT + default y if KSCAN diff --git a/boards/nuvoton/npcx7m6fb_evb/Kconfig.npcx7m6fb_evb b/boards/nuvoton/npcx7m6fb_evb/Kconfig.npcx7m6fb_evb new file mode 100644 index 00000000000..3c7ee46d993 --- /dev/null +++ b/boards/nuvoton/npcx7m6fb_evb/Kconfig.npcx7m6fb_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NPCX7M6FB_EVB + select SOC_NPCX7M6FB diff --git a/boards/arm/npcx7m6fb_evb/board.cmake b/boards/nuvoton/npcx7m6fb_evb/board.cmake similarity index 100% rename from boards/arm/npcx7m6fb_evb/board.cmake rename to boards/nuvoton/npcx7m6fb_evb/board.cmake diff --git a/boards/nuvoton/npcx7m6fb_evb/board.yml b/boards/nuvoton/npcx7m6fb_evb/board.yml new file mode 100644 index 00000000000..33528cde347 --- /dev/null +++ b/boards/nuvoton/npcx7m6fb_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: npcx7m6fb_evb + vendor: nuvoton + socs: + - name: npcx7m6fb diff --git a/boards/nuvoton/npcx7m6fb_evb/doc/index.rst b/boards/nuvoton/npcx7m6fb_evb/doc/index.rst new file mode 100644 index 00000000000..3bcf013f84f --- /dev/null +++ b/boards/nuvoton/npcx7m6fb_evb/doc/index.rst @@ -0,0 +1,107 @@ +.. _npcx7m6fb_evb: + +Nuvoton NPCX7M6FB_EVB +##################### + +Overview +******** + +The NPCX7M6FB_EVB kit is a development platform to evaluate the +Nuvoton NPCX7 series microcontrollers. This board needs to be mated with +part number NPCX796FB. + +.. image:: npcx7m6fb_evb.jpg + :align: center + :alt: NPCX7M6FB Evaluation Board + +Hardware +******** + +- ARM Cortex-M4F Processor +- 256 KB RAM and 64 KB boot ROM +- ADC & GPIO headers +- UART0 and UART1 +- FAN PWM interface +- Jtag interface +- Intel Modular Embedded Controller Card (MECC) headers + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig` + + +Connections and IOs +=================== + +Nuvoton to provide the schematic for this board. + +System Clock +============ + +The NPCX7M6FB MCU is configured to use the 90Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock +control register (chapter 4 in user manual) + +Serial Port +=========== + +UART1 is configured for serial logs. + + +Programming and Debugging +************************* + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG only sessions. + +Flashing +======== + +If the correct IDC headers are installed, this board supports both J-TAG and +also the ChromiumOS servo. + +To flash using Servo V2, μServo, or Servo V4 (CCD), see the +`Chromium EC Flashing Documentation`_ for more information. + +To flash with J-TAG, install the drivers for your programmer, for example: +SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: npcx7m6fb_evb + :maybe-skip-config: + :goals: build flash + +Debugging +========= + +Use JTAG/SWD with a J-Link + +References +********** +.. target-notes:: + +.. _Chromium EC Flashing Documentation: + https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/npcx7m6fb_evb/doc/npcx7m6fb_evb.jpg b/boards/nuvoton/npcx7m6fb_evb/doc/npcx7m6fb_evb.jpg similarity index 100% rename from boards/arm/npcx7m6fb_evb/doc/npcx7m6fb_evb.jpg rename to boards/nuvoton/npcx7m6fb_evb/doc/npcx7m6fb_evb.jpg diff --git a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb-pinctrl.dtsi b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/npcx7m6fb_evb/npcx7m6fb_evb-pinctrl.dtsi rename to boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb-pinctrl.dtsi diff --git a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts similarity index 100% rename from boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts rename to boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts diff --git a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.yaml b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.yaml similarity index 100% rename from boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.yaml rename to boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.yaml diff --git a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig similarity index 88% rename from boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig rename to boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig index c1abbbb44f9..13dabc3f51c 100644 --- a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig +++ b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig @@ -4,10 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_NPCX7M6FB=y -CONFIG_SOC_SERIES_NPCX7=y -CONFIG_BOARD_NPCX7M6FB_EVB=y - # Enable NPCX firmware header CONFIG_NPCX_HEADER=y CONFIG_NPCX_IMAGE_OUTPUT_HEX=y diff --git a/boards/arm/npcx7m6fb_evb/support/openocd.cfg b/boards/nuvoton/npcx7m6fb_evb/support/openocd.cfg similarity index 100% rename from boards/arm/npcx7m6fb_evb/support/openocd.cfg rename to boards/nuvoton/npcx7m6fb_evb/support/openocd.cfg diff --git a/boards/nuvoton/npcx9m6f_evb/Kconfig.defconfig b/boards/nuvoton/npcx9m6f_evb/Kconfig.defconfig new file mode 100644 index 00000000000..3004ce803d4 --- /dev/null +++ b/boards/nuvoton/npcx9m6f_evb/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config INPUT + default y if KSCAN diff --git a/boards/nuvoton/npcx9m6f_evb/Kconfig.npcx9m6f_evb b/boards/nuvoton/npcx9m6f_evb/Kconfig.npcx9m6f_evb new file mode 100644 index 00000000000..792ab76ad47 --- /dev/null +++ b/boards/nuvoton/npcx9m6f_evb/Kconfig.npcx9m6f_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NPCX9M6F_EVB + select SOC_NPCX9M6F diff --git a/boards/arm/npcx9m6f_evb/board.cmake b/boards/nuvoton/npcx9m6f_evb/board.cmake similarity index 100% rename from boards/arm/npcx9m6f_evb/board.cmake rename to boards/nuvoton/npcx9m6f_evb/board.cmake diff --git a/boards/nuvoton/npcx9m6f_evb/board.yml b/boards/nuvoton/npcx9m6f_evb/board.yml new file mode 100644 index 00000000000..7baeb00dfa3 --- /dev/null +++ b/boards/nuvoton/npcx9m6f_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: npcx9m6f_evb + vendor: nuvoton + socs: + - name: npcx9m6f diff --git a/boards/nuvoton/npcx9m6f_evb/doc/index.rst b/boards/nuvoton/npcx9m6f_evb/doc/index.rst new file mode 100644 index 00000000000..e9ed19970c5 --- /dev/null +++ b/boards/nuvoton/npcx9m6f_evb/doc/index.rst @@ -0,0 +1,121 @@ +.. _npcx9m6f_evb: + +Nuvoton NPCX9M6F_EVB +#################### + +Overview +******** + +The NPCX9M6F_EVB kit is a development platform to evaluate the +Nuvoton NPCX9 series microcontrollers. This board needs to be mated with +part number NPCX996F. + +.. image:: npcx9m6f_evb.jpg + :align: center + :alt: NPCX9M6F Evaluation Board + +Hardware +******** + +- ARM Cortex-M4F Processor +- 256 KB RAM and 64 KB boot ROM +- ADC & GPIO headers +- UART0 and UART1 +- FAN PWM interface +- Jtag interface +- Intel Modular Embedded Controller Card (MECC) headers + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port/controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PM | on-chip | power management | ++-----------+------------+-------------------------------------+ +| PSL | on-chip | power switch logic | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pulse width modulator | ++-----------+------------+-------------------------------------+ +| TACH | on-chip | tachometer sensor | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig` + + +Connections and IOs +=================== + +Nuvoton to provide the schematic for this board. + +System Clock +============ + +The NPCX9M6F MCU is configured to use the 90Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock +control register (chapter 4 in user manual) + +Serial Port +=========== + +UART1 is configured for serial logs. + + +Programming and Debugging +************************* + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG-only sessions. + +Flashing +======== + +If the correct IDC headers are installed, this board supports both J-TAG and +also the ChromiumOS servo. + +To flash using Servo V2, μServo, or Servo V4 (CCD), see the +`Chromium EC Flashing Documentation`_ for more information. + +To flash with J-TAG, install the drivers for your programmer, for example: +SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: npcx9m6f_evb + :maybe-skip-config: + :goals: build flash + +Debugging +========= + +Use JTAG/SWD with a J-Link + +References +********** +.. target-notes:: + +.. _Chromium EC Flashing Documentation: + https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/npcx9m6f_evb/doc/npcx9m6f_evb.jpg b/boards/nuvoton/npcx9m6f_evb/doc/npcx9m6f_evb.jpg similarity index 100% rename from boards/arm/npcx9m6f_evb/doc/npcx9m6f_evb.jpg rename to boards/nuvoton/npcx9m6f_evb/doc/npcx9m6f_evb.jpg diff --git a/boards/arm/npcx9m6f_evb/npcx9m6f_evb-pinctrl.dtsi b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/npcx9m6f_evb/npcx9m6f_evb-pinctrl.dtsi rename to boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb-pinctrl.dtsi diff --git a/boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts similarity index 100% rename from boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts rename to boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts diff --git a/boards/arm/npcx9m6f_evb/npcx9m6f_evb.yaml b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.yaml similarity index 100% rename from boards/arm/npcx9m6f_evb/npcx9m6f_evb.yaml rename to boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.yaml diff --git a/boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig similarity index 88% rename from boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig rename to boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig index ae8b83cf8eb..c076f906112 100644 --- a/boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig +++ b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig @@ -4,10 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_NPCX9M6F=y -CONFIG_SOC_SERIES_NPCX9=y -CONFIG_BOARD_NPCX9M6F_EVB=y - # Enable NPCX firmware header CONFIG_NPCX_HEADER=y CONFIG_NPCX_IMAGE_OUTPUT_HEX=y diff --git a/boards/arm/npcx9m6f_evb/support/openocd.cfg b/boards/nuvoton/npcx9m6f_evb/support/openocd.cfg similarity index 100% rename from boards/arm/npcx9m6f_evb/support/openocd.cfg rename to boards/nuvoton/npcx9m6f_evb/support/openocd.cfg diff --git a/boards/nuvoton/numaker_pfm_m467/Kconfig b/boards/nuvoton/numaker_pfm_m467/Kconfig new file mode 100644 index 00000000000..c18a30cfc2d --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m467/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton PFM M467 board configuration +# +# Copyright (c) 2023 Nuvoton Technology Corporation. + +config BOARD_NUMAKER_PFM_M467 + select SOC_FLASH_NUMAKER diff --git a/boards/nuvoton/numaker_pfm_m467/Kconfig.defconfig b/boards/nuvoton/numaker_pfm_m467/Kconfig.defconfig new file mode 100644 index 00000000000..2d476ffc561 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m467/Kconfig.defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton PFM M467 board configuration +# +# Copyright (c) 2023 Nuvoton Technology Corporation. + +if BOARD_NUMAKER_PFM_M467 + +if NETWORKING + +config NET_L2_ETHERNET + default y if !MODEM + +endif # NETWORKING + +endif # BOARD_NUMAKER_PFM_M467 diff --git a/boards/nuvoton/numaker_pfm_m467/Kconfig.numaker_pfm_m467 b/boards/nuvoton/numaker_pfm_m467/Kconfig.numaker_pfm_m467 new file mode 100644 index 00000000000..0516c6bdb94 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m467/Kconfig.numaker_pfm_m467 @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton PFM M467 board configuration +# +# Copyright (c) 2023 Nuvoton Technology Corporation. + +config BOARD_NUMAKER_PFM_M467 + select SOC_M467 diff --git a/boards/nuvoton/numaker_pfm_m467/board.cmake b/boards/nuvoton/numaker_pfm_m467/board.cmake new file mode 100644 index 00000000000..58661cdae22 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m467/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(pyocd "--target=m467hjhae") +board_runner_args(nulink "-f") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nulink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/canopen.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nuvoton/numaker_pfm_m467/board.yml b/boards/nuvoton/numaker_pfm_m467/board.yml new file mode 100644 index 00000000000..d9b195940ee --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m467/board.yml @@ -0,0 +1,5 @@ +board: + name: numaker_pfm_m467 + vendor: nuvoton + socs: + - name: m467 diff --git a/boards/arm/numaker_pfm_m467/doc/index.rst b/boards/nuvoton/numaker_pfm_m467/doc/index.rst similarity index 100% rename from boards/arm/numaker_pfm_m467/doc/index.rst rename to boards/nuvoton/numaker_pfm_m467/doc/index.rst diff --git a/boards/arm/numaker_pfm_m467/doc/pfm_m467.jpeg b/boards/nuvoton/numaker_pfm_m467/doc/pfm_m467.jpeg similarity index 100% rename from boards/arm/numaker_pfm_m467/doc/pfm_m467.jpeg rename to boards/nuvoton/numaker_pfm_m467/doc/pfm_m467.jpeg diff --git a/boards/arm/numaker_pfm_m467/numaker_pfm_m467-pinctrl.dtsi b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467-pinctrl.dtsi similarity index 100% rename from boards/arm/numaker_pfm_m467/numaker_pfm_m467-pinctrl.dtsi rename to boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467-pinctrl.dtsi diff --git a/boards/arm/numaker_pfm_m467/numaker_pfm_m467.dts b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts similarity index 100% rename from boards/arm/numaker_pfm_m467/numaker_pfm_m467.dts rename to boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts diff --git a/boards/arm/numaker_pfm_m467/numaker_pfm_m467.yaml b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml similarity index 100% rename from boards/arm/numaker_pfm_m467/numaker_pfm_m467.yaml rename to boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml diff --git a/boards/arm/numaker_pfm_m467/numaker_pfm_m467_defconfig b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467_defconfig similarity index 78% rename from boards/arm/numaker_pfm_m467/numaker_pfm_m467_defconfig rename to boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467_defconfig index abc0d144a94..a5396d157c3 100644 --- a/boards/arm/numaker_pfm_m467/numaker_pfm_m467_defconfig +++ b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_M46X=y -CONFIG_SOC_M467=y CONFIG_PINCTRL=y CONFIG_GPIO=y @@ -13,14 +11,13 @@ CONFIG_CLOCK_CONTROL_NUMAKER_SCC=y CONFIG_ARM_MPU=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 -# enable uart driver +# Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# console +# Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y # Enable FMC CONFIG_FLASH=y -CONFIG_SOC_FLASH_NUMAKER=y diff --git a/boards/arm/numaker_pfm_m467/support/openocd.cfg b/boards/nuvoton/numaker_pfm_m467/support/openocd.cfg similarity index 100% rename from boards/arm/numaker_pfm_m467/support/openocd.cfg rename to boards/nuvoton/numaker_pfm_m467/support/openocd.cfg diff --git a/boards/nuvoton/numaker_pfm_m487/Kconfig.numaker_pfm_m487 b/boards/nuvoton/numaker_pfm_m487/Kconfig.numaker_pfm_m487 new file mode 100644 index 00000000000..156feae907e --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/Kconfig.numaker_pfm_m487 @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton PFM M467 board configuration +# +# Copyright (c) 2023 Nuvoton Technology Corporation. + +config BOARD_NUMAKER_PFM_M487 + select SOC_M487 diff --git a/boards/arm/nuvoton_pfm_m487/board.cmake b/boards/nuvoton/numaker_pfm_m487/board.cmake similarity index 100% rename from boards/arm/nuvoton_pfm_m487/board.cmake rename to boards/nuvoton/numaker_pfm_m487/board.cmake diff --git a/boards/nuvoton/numaker_pfm_m487/board.yml b/boards/nuvoton/numaker_pfm_m487/board.yml new file mode 100644 index 00000000000..cc9dc43fe6a --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/board.yml @@ -0,0 +1,5 @@ +board: + name: numaker_pfm_m487 + vendor: nuvoton + socs: + - name: m487 diff --git a/boards/nuvoton/numaker_pfm_m487/doc/index.rst b/boards/nuvoton/numaker_pfm_m487/doc/index.rst new file mode 100644 index 00000000000..323be5f5923 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/doc/index.rst @@ -0,0 +1,98 @@ +.. _nuvoton_pfm_m487: + +NUVOTON NUMAKER PFM M487 +######################## + +Overview +******** + +The NuMaker PFM M487 is an Internet of Things (IoT) application focused platform +specially developed by Nuvoton. The PFM-M487 is based on the NuMicro® M487 +Ethernet series MCU with ARM® -Cortex®-M4F core. + +.. image:: pfm_m487.jpg + :align: center + :alt: PFM-M487 + +Features: +========= +- 32-bit Arm Cortex®-M4 M487JIDAE MCU +- Core clock up to 192 MHz +- 512 KB embedded Dual Bank Flash and 160 KB SRAM +- Audio codec (NAU88L25) with Microphone In and Headphone Out +- Ethernet (IP101GR) for network application +- USB 2.0 High-Speed OTG / Host / Device +- USB 1.1 Full-Speed OTG / Host / Device +- External SPI Flash (Winbond W25Q20) which can be regarded as ROM module +- MicroSD Card slot for T-Flash +- M487 extended interface 4 connector with 36 pins each +- Arduino UNO compatible interface +- Three push-buttons: one is for reset and the other two are for user-defined +- Four LEDs: one is for power indication and the other three are for user-defined +- On-board NU-Link-Me ICE debugger/programmer with SWD connector + +More information about the board can be found at the `PFM M487 User Manual`_. + +Supported Features +================== + +* The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 192MHz. + +The development board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port | ++-----------+------------+-----------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +More details about the supported peripherals are available in `M480 TRM`_ +Other hardware features are not currently supported by the Zephyr kernel. + +Building and Flashing +********************* +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +On board debugger Nu-link-Me can emulate UART0 as a virtual COM port over usb, +To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. +Connect the PFM M487 IoT to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: numaker_pfm_m487 + :goals: flash + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: numaker_pfm_m487 + :goals: debug + +Step through the application in your debugger. + +References +********** + +.. _PFM M487 User Manual: + https://www.nuvoton.com/export/resource-files/UM_NuMaker-PFM-M487_User_Manual_EN_Rev1.01.pdf +.. _M480 TRM: + https://www.nuvoton.com/export/resource-files/TRM_M480_Series_EN_Rev2.02.pdf diff --git a/boards/arm/nuvoton_pfm_m487/doc/pfm_m487.jpg b/boards/nuvoton/numaker_pfm_m487/doc/pfm_m487.jpg similarity index 100% rename from boards/arm/nuvoton_pfm_m487/doc/pfm_m487.jpg rename to boards/nuvoton/numaker_pfm_m487/doc/pfm_m487.jpg diff --git a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487-pinctrl.dtsi b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487-pinctrl.dtsi similarity index 100% rename from boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487-pinctrl.dtsi rename to boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487-pinctrl.dtsi diff --git a/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.dts b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.dts new file mode 100644 index 00000000000..87f24bb13d2 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.dts @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2020 Linumiz + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "numaker_pfm_m487-pinctrl.dtsi" +#include + +/ { + model = "Nuvoton PFM M487 board"; + compatible = "nuvoton,pfm-m487", "nuvoton,m487"; + + aliases { + led0 = &red_led; + led1 = &yellow_led; + led2 = &green_led; + sw0 = &sw2; + sw1 = &sw3; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpioh 0 GPIO_ACTIVE_LOW>; + label = "User LED Red"; + }; + yellow_led: led_1 { + gpios = <&gpioh 1 GPIO_ACTIVE_LOW>; + label = "User LED Yellow"; + }; + green_led: led_2 { + gpios = <&gpioh 2 GPIO_ACTIVE_LOW>; + label = "User LED Green"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + sw2: button_0 { + gpios = <&gpiog 15 GPIO_ACTIVE_LOW>; + label = "User SW2"; + zephyr,code = ; + }; + sw3: button_1 { + gpios = <&gpiof 11 GPIO_ACTIVE_LOW>; + label = "User SW3"; + zephyr,code = ; + }; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(160)>; +}; + +&gpiob { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&gpiog { + status = "okay"; +}; + +&gpioh { + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.yaml b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.yaml new file mode 100644 index 00000000000..396f6780698 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.yaml @@ -0,0 +1,11 @@ +identifier: numaker_pfm_m487 +name: NUVOTON-PFM-M487 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 160 +flash: 512 +vendor: nuvoton diff --git a/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487_defconfig b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487_defconfig new file mode 100644 index 00000000000..bd250a1e060 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=192000000 + +# Enable GPIO and pinctrl drivers +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nuvoton_pfm_m487/support/openocd.cfg b/boards/nuvoton/numaker_pfm_m487/support/openocd.cfg similarity index 100% rename from boards/arm/nuvoton_pfm_m487/support/openocd.cfg rename to boards/nuvoton/numaker_pfm_m487/support/openocd.cfg diff --git a/boards/arm/frdm_k22f/CMakeLists.txt b/boards/nxp/frdm_k22f/CMakeLists.txt similarity index 100% rename from boards/arm/frdm_k22f/CMakeLists.txt rename to boards/nxp/frdm_k22f/CMakeLists.txt diff --git a/boards/nxp/frdm_k22f/Kconfig.defconfig b/boards/nxp/frdm_k22f/Kconfig.defconfig new file mode 100644 index 00000000000..8978b957c14 --- /dev/null +++ b/boards/nxp/frdm_k22f/Kconfig.defconfig @@ -0,0 +1,20 @@ +# FRDM-K22F board + +# Copyright (c) 2018 Prevas A/S +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_K22F + +config OSC_XTAL0_FREQ + default 8000000 + +config MCG_PRDIV0 + default 0x3 + +config MCG_VDIV0 + default 0xc + +config MCG_FCRDIV + default 0 + +endif # BOARD_FRDM_K22F diff --git a/boards/nxp/frdm_k22f/Kconfig.frdm_k22f b/boards/nxp/frdm_k22f/Kconfig.frdm_k22f new file mode 100644 index 00000000000..4ca1a2c0fa4 --- /dev/null +++ b/boards/nxp/frdm_k22f/Kconfig.frdm_k22f @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_K22F + select SOC_MK22F51212 + select SOC_PART_NUMBER_MK22FN512VLH12 diff --git a/boards/arm/frdm_k22f/board.cmake b/boards/nxp/frdm_k22f/board.cmake similarity index 100% rename from boards/arm/frdm_k22f/board.cmake rename to boards/nxp/frdm_k22f/board.cmake diff --git a/boards/nxp/frdm_k22f/board.yml b/boards/nxp/frdm_k22f/board.yml new file mode 100644 index 00000000000..0498d799129 --- /dev/null +++ b/boards/nxp/frdm_k22f/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_k22f + vendor: nxp + socs: + - name: mk22f51212 diff --git a/boards/arm/frdm_k22f/doc/frdm_k22f.jpg b/boards/nxp/frdm_k22f/doc/frdm_k22f.jpg similarity index 100% rename from boards/arm/frdm_k22f/doc/frdm_k22f.jpg rename to boards/nxp/frdm_k22f/doc/frdm_k22f.jpg diff --git a/boards/nxp/frdm_k22f/doc/index.rst b/boards/nxp/frdm_k22f/doc/index.rst new file mode 100644 index 00000000000..f0f98048561 --- /dev/null +++ b/boards/nxp/frdm_k22f/doc/index.rst @@ -0,0 +1,298 @@ +.. _frdm_k22f: + +NXP FRDM-K22F +############## + +Overview +******** + +The Freedom-K22F is an ultra-low-cost development platform for Kinetis K22 +MCUs. + +- Form-factor compatible with the Arduino R3 pin layout +- Peripherals enable rapid prototyping, including a 6-axis digital + accelerometer and magnetometer to create full eCompass capabilities, a + tri-colored LED and 2 user push-buttons for direct interaction, a optional + microSD card slot, and headers for use with Bluetooth* and 2.4 GHz radio + add-on modules +- OpenSDAv2, the NXP open source hardware embedded serial and debug adapter + running an open source bootloader, offers options for serial communication, + flash programming, and run-control debugging + +.. image:: frdm_k22f.jpg + :align: center + :alt: FRDM-K22F + +Hardware +******** + +- MK22FN512VLH12 (120 MHz, 1 MB flash memory, 256 KB RAM, low-power, + crystal-less USB, and 64 pin Low profile Quad Flat Package (LQFP)) +- Dual role USB interface with micro-B USB connector +- RGB LED +- FXOS8700CQ accelerometer and magnetometer +- Two user push buttons +- Flexible power supply option - OpenSDAv2 USB, Kinetis K22 USB, and external source +- Easy access to MCU input/output through Arduino* R3 compatible I/O connectors +- Programmable OpenSDAv2 debug circuit supporting the CMSIS-DAP Interface + software that provides: + + - Mass storage device (MSD) flash programming interface + - CMSIS-DAP debug interface over a driver-less USB HID connection providing + run-control debugging and compatibility with IDE tools + - Virtual serial port interface + - Open source CMSIS-DAP software project + +- Optional SDHC + +For more information about the K22F SoC and FRDM-K22F board: + +- `K22F Website`_ +- `K22F Datasheet`_ +- `K22F Reference Manual`_ +- `FRDM-K22F Website`_ +- `FRDM-K22F User Guide`_ +- `FRDM-K22F Schematics`_ + +Supported Features +================== + +The frdm_k22f board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the frdm_k64f board may have additional features +already supported, which can also be re-used on this frdm_k22f board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger | ++-----------+------------+-------------------------------------+ +| RNGA | on-chip | entropy; | +| | | random | ++-----------+------------+-------------------------------------+ +| FTFE | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + +:zephyr_file:`boards/nxp/frdm_k22f/frdm_k22f_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The K22F SoC has five pairs of pinmux/gpio controllers. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTA1 | GPIO | Red LED | ++-------+-----------------+---------------------------+ +| PTA2 | GPIO | Green LED | ++-------+-----------------+---------------------------+ +| PTD5 | GPIO | Blue LED | ++-------+-----------------+---------------------------+ +| PTC1 | GPIO | SW2 | ++-------+-----------------+---------------------------+ +| PTD0 | GPIO | FXOS8700 INT1 | ++-------+-----------------+---------------------------+ +| PTD1 | GPIO | FXOS8700 INT2 | ++-------+-----------------+---------------------------+ +| PTB17 | GPIO | SW3 | ++-------+-----------------+---------------------------+ +| PTE1 | UART1_RX | UART Console | ++-------+-----------------+---------------------------+ +| PTE0 | UART1_TX | UART Console | ++-------+-----------------+---------------------------+ +| PTD2 | UART2_RX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTD3 | UART2_TX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTC4 | SPI0_PCS0 | SPI | ++-------+-----------------+---------------------------+ +| PTD1 | SPI0_SCK | SPI | ++-------+-----------------+---------------------------+ +| PTD2 | SPI0_SOUT | SPI | ++-------+-----------------+---------------------------+ +| PTD3 | SPI0_SIN | SPI | ++-------+-----------------+---------------------------+ +| PTB2 | I2C0_SCL | I2C / FXOS8700 | ++-------+-----------------+---------------------------+ +| PTB3 | I2C0_SDA | I2C / FXOS8700 | ++-------+-----------------+---------------------------+ + +System Clock +============ + +The K22F SoC is configured to use the 8 MHz crystal oscillator on the board +with the on-chip PLL to generate a 72 MHz system clock in its RUN mode. This +clock was selected to allow for the maximum number of peripherals to be used +with the crystal and PLL clocks. Other clock configurations are possible +through NXP SDK currently. + +Serial Port +=========== + +The K22F SoC has three UARTs. One is configured for the console, another for BT +HCI, and the remaining are not used. + +USB +=== + +The K22F SoC has a USB OTG (USBOTG) controller that supports both +device and host functions through its micro USB connector (K22F USB). +Only USB device function is supported in Zephyr at the moment. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) +------------------------------------------------------------------ + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program +the `OpenSDA DAPLink FRDM-K22F Firmware`_. + +Option 2: :ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `Segger J-Link OpenSDA V2.1 Firmware`_. Note that Segger +does provide an OpenSDA J-Link Board-Specific Firmware for this board, however +it is not compatible with the DAPLink bootloader. + +Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and +``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the +default runner from pyOCD to J-Link: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k22f + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J26. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k22f + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.0.0 ***** + Hello World! frdm_k22f + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k22f + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.0.0 ***** + Hello World! frdm_k22f + +.. _FRDM-K22F Website: + https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/freedom-development-boards/mcu-boards/nxp-freedom-development-platform-for-kinetis-k22-mcus:FRDM-K22F + +.. _FRDM-K22F User Guide: + https://www.nxp.com/webapp/Download?colCode=FRDMK22FUG + +.. _FRDM-K22F Schematics: + https://www.nxp.com/webapp/Download?colCode=FRDM-K22F-SCH + +.. _K22F Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k2x-usb/kinetis-k22-120-mhz-cost-effective-full-speed-usb-microcontrollers-mcus-based-on-arm-cortex-m4-core:K22_120 + +.. _K22F Datasheet: + https://www.nxp.com/docs/en/data-sheet/K22P121M120SF7.pdf + +.. _K22F Reference Manual: + https://www.nxp.com/docs/en/reference-manual/K22P121M120SF7RM.pdf + +.. _OpenSDA DAPLink FRDM-K22F Firmware: + https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk22f_if_crc_legacy_0x8000.bin + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _Segger J-Link OpenSDA V2.1 Firmware: + https://www.segger.com/downloads/jlink/OpenSDA_V2_1.bin diff --git a/boards/arm/frdm_k22f/frdm_k22f-pinctrl.dtsi b/boards/nxp/frdm_k22f/frdm_k22f-pinctrl.dtsi similarity index 100% rename from boards/arm/frdm_k22f/frdm_k22f-pinctrl.dtsi rename to boards/nxp/frdm_k22f/frdm_k22f-pinctrl.dtsi diff --git a/boards/arm/frdm_k22f/frdm_k22f.dts b/boards/nxp/frdm_k22f/frdm_k22f.dts similarity index 100% rename from boards/arm/frdm_k22f/frdm_k22f.dts rename to boards/nxp/frdm_k22f/frdm_k22f.dts diff --git a/boards/arm/frdm_k22f/frdm_k22f.yaml b/boards/nxp/frdm_k22f/frdm_k22f.yaml similarity index 100% rename from boards/arm/frdm_k22f/frdm_k22f.yaml rename to boards/nxp/frdm_k22f/frdm_k22f.yaml diff --git a/boards/arm/frdm_k22f/frdm_k22f_defconfig b/boards/nxp/frdm_k22f/frdm_k22f_defconfig similarity index 84% rename from boards/arm/frdm_k22f/frdm_k22f_defconfig rename to boards/nxp/frdm_k22f/frdm_k22f_defconfig index 4ee913104de..28e4f2b6ec3 100644 --- a/boards/arm/frdm_k22f/frdm_k22f_defconfig +++ b/boards/nxp/frdm_k22f/frdm_k22f_defconfig @@ -6,8 +6,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MK22F51212=y -CONFIG_SOC_SERIES_KINETIS_K2X=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/frdm_k22f/support/openocd.cfg b/boards/nxp/frdm_k22f/support/openocd.cfg similarity index 100% rename from boards/arm/frdm_k22f/support/openocd.cfg rename to boards/nxp/frdm_k22f/support/openocd.cfg diff --git a/boards/arm/segger_trb_stm32f407/CMakeLists.txt b/boards/nxp/frdm_k64f/CMakeLists.txt similarity index 100% rename from boards/arm/segger_trb_stm32f407/CMakeLists.txt rename to boards/nxp/frdm_k64f/CMakeLists.txt diff --git a/boards/nxp/frdm_k64f/Kconfig.defconfig b/boards/nxp/frdm_k64f/Kconfig.defconfig new file mode 100644 index 00000000000..1faad7cad92 --- /dev/null +++ b/boards/nxp/frdm_k64f/Kconfig.defconfig @@ -0,0 +1,30 @@ +# FRDM-K64F board + +# Copyright (c) 2016, Freescale Semiconductor, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_K64F + +config OSC_XTAL0_FREQ + default 50000000 + +config MCG_PRDIV0 + default 0x13 + +config MCG_VDIV0 + default 0x18 + +config MCG_FCRDIV + default 1 + +config TEST_EXTRA_STACK_SIZE + default 128 + +if NETWORKING + +config NET_L2_ETHERNET + default y if !MODEM + +endif # NETWORKING + +endif # BOARD_FRDM_K64F diff --git a/boards/nxp/frdm_k64f/Kconfig.frdm_k64f b/boards/nxp/frdm_k64f/Kconfig.frdm_k64f new file mode 100644 index 00000000000..31c7e706ce2 --- /dev/null +++ b/boards/nxp/frdm_k64f/Kconfig.frdm_k64f @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_K64F + select SOC_MK64F12 + select SOC_PART_NUMBER_MK64FN1M0VLL12 diff --git a/boards/arm/frdm_k64f/board.cmake b/boards/nxp/frdm_k64f/board.cmake similarity index 100% rename from boards/arm/frdm_k64f/board.cmake rename to boards/nxp/frdm_k64f/board.cmake diff --git a/boards/nxp/frdm_k64f/board.yml b/boards/nxp/frdm_k64f/board.yml new file mode 100644 index 00000000000..a338af6b99c --- /dev/null +++ b/boards/nxp/frdm_k64f/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_k64f + vendor: nxp + socs: + - name: mk64f12 diff --git a/boards/arm/frdm_k64f/doc/frdm_k64f.jpg b/boards/nxp/frdm_k64f/doc/frdm_k64f.jpg similarity index 100% rename from boards/arm/frdm_k64f/doc/frdm_k64f.jpg rename to boards/nxp/frdm_k64f/doc/frdm_k64f.jpg diff --git a/boards/nxp/frdm_k64f/doc/index.rst b/boards/nxp/frdm_k64f/doc/index.rst new file mode 100644 index 00000000000..97c158804ee --- /dev/null +++ b/boards/nxp/frdm_k64f/doc/index.rst @@ -0,0 +1,401 @@ +.. _frdm_k64f: + +NXP FRDM-K64F +############## + +Overview +******** + +The Freedom-K64F is an ultra-low-cost development platform for Kinetis K64, +K63, and K24 MCUs. + +- Form-factor compatible with the Arduino R3 pin layout +- Peripherals enable rapid prototyping, including a 6-axis digital + accelerometer and magnetometer to create full eCompass capabilities, a + tri-colored LED and 2 user push-buttons for direct interaction, a microSD + card slot, and connectivity using onboard Ethernet port and headers for use + with Bluetooth* and 2.4 GHz radio add-on modules +- OpenSDAv2, the NXP open source hardware embedded serial and debug adapter + running an open source bootloader, offers options for serial communication, + flash programming, and run-control debugging + +.. image:: frdm_k64f.jpg + :align: center + :alt: FRDM-K64F + +Hardware +******** + +- MK64FN1M0VLL12 MCU (120 MHz, 1 MB flash memory, 256 KB RAM, low-power, + crystal-less USB, and 100 Low profile Quad Flat Package (LQFP)) +- Dual role USB interface with micro-B USB connector +- RGB LED +- FXOS8700CQ accelerometer and magnetometer +- Two user push buttons +- Flexible power supply option - OpenSDAv2 USB, Kinetis K64 USB, and external source +- Easy access to MCU input/output through Arduino* R3 compatible I/O connectors +- Programmable OpenSDAv2 debug circuit supporting the CMSIS-DAP Interface + software that provides: + + - Mass storage device (MSD) flash programming interface + - CMSIS-DAP debug interface over a driver-less USB HID connection providing + run-control debugging and compatibility with IDE tools + - Virtual serial port interface + - Open source CMSIS-DAP software project + +- Ethernet +- SDHC + +For more information about the K64F SoC and FRDM-K64F board: + +- `K64F Website`_ +- `K64F Datasheet`_ +- `K64F Reference Manual`_ +- `FRDM-K64F Website`_ +- `FRDM-K64F User Guide`_ +- `FRDM-K64F Schematics`_ + +Supported Features +================== + +NXP considers the FRDM-K64F as the superset board for the Kinetis K +series of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire Kinetis K series. NXP prioritizes enabling +this board with new support for Zephyr features. The frdm_k64f board +configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| RNGA | on-chip | entropy; | +| | | random | ++-----------+------------+-------------------------------------+ +| FTFE | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/frdm_k64f/frdm_k64f_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The K64F SoC has five pairs of pinmux/gpio controllers. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTB22 | GPIO | Red LED | ++-------+-----------------+---------------------------+ +| PTE26 | GPIO | Green LED | ++-------+-----------------+---------------------------+ +| PTB21 | GPIO | Blue LED | ++-------+-----------------+---------------------------+ +| PTC6 | GPIO | SW2 / FXOS8700 INT1 | ++-------+-----------------+---------------------------+ +| PTC13 | GPIO | FXOS8700 INT2 | ++-------+-----------------+---------------------------+ +| PTA4 | GPIO | SW3 | ++-------+-----------------+---------------------------+ +| PTB10 | ADC | ADC1 channel 14 | ++-------+-----------------+---------------------------+ +| PTB16 | UART0_RX | UART Console | ++-------+-----------------+---------------------------+ +| PTB17 | UART0_TX | UART Console | ++-------+-----------------+---------------------------+ +| PTB18 | CAN0_TX | CAN TX | ++-------+-----------------+---------------------------+ +| PTB19 | CAN0_RX | CAN RX | ++-------+-----------------+---------------------------+ +| PTC8 | PWM | PWM_3 channel 4 | ++-------+-----------------+---------------------------+ +| PTC9 | PWM | PWM_3 channel 5 | ++-------+-----------------+---------------------------+ +| PTC16 | UART3_RX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTC17 | UART3_TX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTD0 | SPI0_PCS0 | SPI | ++-------+-----------------+---------------------------+ +| PTD1 | SPI0_SCK | SPI | ++-------+-----------------+---------------------------+ +| PTD2 | SPI0_SOUT | SPI | ++-------+-----------------+---------------------------+ +| PTD3 | SPI0_SIN | SPI | ++-------+-----------------+---------------------------+ +| PTE24 | I2C0_SCL | I2C / FXOS8700 | ++-------+-----------------+---------------------------+ +| PTE25 | I2C0_SDA | I2C / FXOS8700 | ++-------+-----------------+---------------------------+ +| PTA5 | MII0_RXER | Ethernet | ++-------+-----------------+---------------------------+ +| PTA12 | MII0_RXD1 | Ethernet | ++-------+-----------------+---------------------------+ +| PTA13 | MII0_RXD0 | Ethernet | ++-------+-----------------+---------------------------+ +| PTA14 | MII0_RXDV | Ethernet | ++-------+-----------------+---------------------------+ +| PTA15 | MII0_TXEN | Ethernet | ++-------+-----------------+---------------------------+ +| PTA16 | MII0_TXD0 | Ethernet | ++-------+-----------------+---------------------------+ +| PTA17 | MII0_TXD1 | Ethernet | ++-------+-----------------+---------------------------+ +| PTA28 | MII0_TXER | Ethernet | ++-------+-----------------+---------------------------+ +| PTB0 | MII0_MDIO | Ethernet | ++-------+-----------------+---------------------------+ +| PTB1 | MII0_MDC | Ethernet | ++-------+-----------------+---------------------------+ +| PTC16 | ENET0_1588_TMR0 | Ethernet | ++-------+-----------------+---------------------------+ +| PTC17 | ENET0_1588_TMR1 | Ethernet | ++-------+-----------------+---------------------------+ +| PTC18 | ENET0_1588_TMR2 | Ethernet | ++-------+-----------------+---------------------------+ +| PTC19 | ENET0_1588_TMR3 | Ethernet | ++-------+-----------------+---------------------------+ + +.. note:: + Do not enable Ethernet and UART BT HCI simultaneously because they conflict + on PTC16-17. + +System Clock +============ + +The K64F SoC is configured to use the 50 MHz external oscillator on the board +with the on-chip PLL to generate a 120 MHz system clock. + +Serial Port +=========== + +The K64F SoC has six UARTs. One is configured for the console, another for BT +HCI, and the remaining are not used. + +USB +=== + +The K64F SoC has a USB OTG (USBOTG) controller that supports both +device and host functions through its micro USB connector (K64F USB). +Only USB device function is supported in Zephyr at the moment. + +CAN +=== + +The FRDM-K64F board does not come with an onboard CAN transceiver. In order to +use the CAN bus, an external CAN bus transceiver must be connected to ``PTB18`` +(``CAN0_TX``) and ``PTB19`` (``CAN0_RX``). + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +.. tabs:: + + .. group-tab:: OpenSDA DAPLink Onboard (Recommended) + + Install the :ref:`linkserver-debug-host-tools` and make sure they are in your + search path. LinkServer works with the default CMSIS-DAP firmware included in + the on-board debugger. + + Linkserver is the default for this board, ``west flash`` and ``west debug`` will + call the linkserver runner. + + .. code-block:: console + + west flash + + Alternatively, pyOCD can be used to flash and debug the board by using the + ``-r pyocd`` option with West. pyOCD is installed when you complete the + :ref:`gs_python_deps` step in the Getting Started Guide. The runners supported + by NXP are LinkServer and JLink. pyOCD is another potential option, but NXP + does not test or support the pyOCD runner. + + + .. group-tab:: OpenSDA JLink Onboard + + Install the :ref:`jlink-debug-host-tools` and make sure they are in your search + path. + + The version of J-Link firmware to program to the board depends on the version + of the DAPLink bootloader. Refer to `OpenSDA Serial and Debug Adapter`_ for + more details. On this page, change the pull-down menu for "Choose your board to + start" to FRDM-K64F, and review the section "To update your board with OpenSDA + applications". Note that Segger does provide an OpenSDA J-Link Board-Specific + Firmware for this board, however it is not compatible with the DAPLink + bootloader. After downloading the appropriate J-Link firmware, follow the + instructions in :ref:`opensda-jlink-onboard-debug-probe` to program to the + board. + + Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and + ``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the + default runner to J-Link: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k64f + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J26. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k64f + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_k64f + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k64f + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_k64f + +Troubleshooting +=============== + +If pyocd raises an uncaught ``DAPAccessIntf.TransferFaultError()`` exception +when you try to flash or debug, it's possible that the K64F flash may have been +locked by a corrupt application. You can unlock it with the following sequence +of pyocd commands: + +.. code-block:: console + + $ pyocd cmd + 0001915:WARNING:target_kinetis:Forcing halt on connect in order to gain control of device + Connected to K64F [Halted]: 0240000026334e450028400d5e0e000e4eb1000097969900 + >>> unlock + 0016178:WARNING:target_kinetis:K64F secure state: unlocked successfully + >>> reinit + 0034584:WARNING:target_kinetis:Forcing halt on connect in order to gain control of device + >>> load build/zephyr/zephyr.bin + [====================] 100% + >>> reset + Resetting target + >>> quit + +.. _FRDM-K64F Website: + https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F + +.. _FRDM-K64F User Guide: + https://www.nxp.com/webapp/Download?colCode=FRDMK64FUG + +.. _FRDM-K64F Schematics: + https://www.nxp.com/webapp/Download?colCode=FRDM-K64F-SCH-E4 + +.. _K64F Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k6x-ethernet/kinetis-k64-120-mhz-256kb-sram-microcontrollers-mcus-based-on-arm-cortex-m4-core:K64_120 + +.. _K64F Datasheet: + https://www.nxp.com/docs/en/data-sheet/K64P144M120SF5.pdf + +.. _K64F Reference Manual: + https://www.nxp.com/docs/en/reference-manual/K64P144M120SF5RM.pdf + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _OpenSDA DAPLink FRDM-K64F Firmware: + https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk64f_if_crc_legacy_0x5000.bin + +.. _OpenSDA Serial and Debug Adapter: + https://www.nxp.com/design/microcontrollers-developer-resources/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA#FRDM-K64F + +Experimental ENET Driver +======================== + +Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new +driver with binding `nxp,enet`, which is experimental and undergoing development, but will have +enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. + +To build for this EVK with the new driver, include the experimental overlay to west build with +the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/frdm_k64f/dts/nxp,enet-experimental.overlay b/boards/nxp/frdm_k64f/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/frdm_k64f/dts/nxp,enet-experimental.overlay rename to boards/nxp/frdm_k64f/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/frdm_k64f/frdm_k64f-pinctrl.dtsi b/boards/nxp/frdm_k64f/frdm_k64f-pinctrl.dtsi similarity index 100% rename from boards/arm/frdm_k64f/frdm_k64f-pinctrl.dtsi rename to boards/nxp/frdm_k64f/frdm_k64f-pinctrl.dtsi diff --git a/boards/arm/frdm_k64f/frdm_k64f.dts b/boards/nxp/frdm_k64f/frdm_k64f.dts similarity index 100% rename from boards/arm/frdm_k64f/frdm_k64f.dts rename to boards/nxp/frdm_k64f/frdm_k64f.dts diff --git a/boards/arm/frdm_k64f/frdm_k64f.yaml b/boards/nxp/frdm_k64f/frdm_k64f.yaml similarity index 100% rename from boards/arm/frdm_k64f/frdm_k64f.yaml rename to boards/nxp/frdm_k64f/frdm_k64f.yaml diff --git a/boards/arm/frdm_k64f/frdm_k64f_defconfig b/boards/nxp/frdm_k64f/frdm_k64f_defconfig similarity index 82% rename from boards/arm/frdm_k64f/frdm_k64f_defconfig rename to boards/nxp/frdm_k64f/frdm_k64f_defconfig index 1f2df24a866..74d8a115b89 100644 --- a/boards/arm/frdm_k64f/frdm_k64f_defconfig +++ b/boards/nxp/frdm_k64f/frdm_k64f_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_MK64F12=y -CONFIG_SOC_SERIES_KINETIS_K6X=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/frdm_k64f/support/openocd.cfg b/boards/nxp/frdm_k64f/support/openocd.cfg similarity index 100% rename from boards/arm/frdm_k64f/support/openocd.cfg rename to boards/nxp/frdm_k64f/support/openocd.cfg diff --git a/boards/arm/twr_kv58f220m/CMakeLists.txt b/boards/nxp/frdm_k82f/CMakeLists.txt similarity index 100% rename from boards/arm/twr_kv58f220m/CMakeLists.txt rename to boards/nxp/frdm_k82f/CMakeLists.txt diff --git a/boards/nxp/frdm_k82f/Kconfig.defconfig b/boards/nxp/frdm_k82f/Kconfig.defconfig new file mode 100644 index 00000000000..310e6d3709d --- /dev/null +++ b/boards/nxp/frdm_k82f/Kconfig.defconfig @@ -0,0 +1,24 @@ +# FRDM-K82F board + +# Copyright (c) 2019 SEAL AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_K82F + +config OSC_XTAL0_FREQ + default 12000000 + +config MCG_PRDIV0 + default 0x0 + +config MCG_VDIV0 + default 0x4 + +config MCG_FCRDIV + default 1 + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +endif # BOARD_FRDM_K82F diff --git a/boards/nxp/frdm_k82f/Kconfig.frdm_k82f b/boards/nxp/frdm_k82f/Kconfig.frdm_k82f new file mode 100644 index 00000000000..b05d7b858b1 --- /dev/null +++ b/boards/nxp/frdm_k82f/Kconfig.frdm_k82f @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_K82F + select SOC_MK82F25615 + select SOC_PART_NUMBER_MK82FN256VLL15 diff --git a/boards/arm/frdm_k82f/board.cmake b/boards/nxp/frdm_k82f/board.cmake similarity index 100% rename from boards/arm/frdm_k82f/board.cmake rename to boards/nxp/frdm_k82f/board.cmake diff --git a/boards/nxp/frdm_k82f/board.yml b/boards/nxp/frdm_k82f/board.yml new file mode 100644 index 00000000000..cf7bc47e121 --- /dev/null +++ b/boards/nxp/frdm_k82f/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_k82f + vendor: nxp + socs: + - name: mk82f25615 diff --git a/boards/arm/frdm_k82f/doc/frdm_k82f.jpg b/boards/nxp/frdm_k82f/doc/frdm_k82f.jpg similarity index 100% rename from boards/arm/frdm_k82f/doc/frdm_k82f.jpg rename to boards/nxp/frdm_k82f/doc/frdm_k82f.jpg diff --git a/boards/nxp/frdm_k82f/doc/index.rst b/boards/nxp/frdm_k82f/doc/index.rst new file mode 100644 index 00000000000..71e6e5133fc --- /dev/null +++ b/boards/nxp/frdm_k82f/doc/index.rst @@ -0,0 +1,253 @@ +.. _frdm_k82f: + +NXP FRDM-K82F +############## + +Overview +******** + +The FRDM-K82F is a low-cost development platform for Kinetis K80, K81, +and K82 MCUs. + +- Form-factor compatible with the Arduino R3 pin layout +- Peripherals enable rapid prototyping, including a six-axis digital + accelerometer and magnetometer to create full eCompass capabilities, a + tri-colored LED and two user push-buttons for direct interaction, 2x32 Mb + QuadSPI external flash, FlexIO camera header, touchpads and headers for use + with Bluetooth and 2.4 GHz radio add-on modules +- OpenSDAv2.1, the NXP open source hardware embedded serial and debug adapter + running an open source bootloader, offers options for serial communication, + flash programming, and run-control debugging + +.. image:: frdm_k82f.jpg + :align: center + :alt: FRDM-K82F + +Hardware +******** + +- MK82FN256VLL15 MCU (150 MHz, 256 KB flash memory, 256 KB RAM, low-power, + crystal-less USB, and 100 Low profile Quad Flat Package (LQFP)) +- Dual role USB interface with micro-B USB connector +- RGB LED +- FXOS8700CQ accelerometer and magnetometer +- Two user push buttons +- 2x 32 Mb QSPI flash +- Flexible power supply option - OpenSDAv2.1 USB, Kinetis K82 USB, and external source +- Easy access to MCU input/output through Arduino R3 compatible I/O connectors +- Programmable OpenSDAv2.1 debug circuit supporting the CMSIS-DAP Interface + software that provides: + + - Mass storage device (MSD) flash programming interface + - CMSIS-DAP debug interface over a driver-less USB HID connection providing + run-control debugging and compatibility with IDE tools + - Virtual serial port interface + - Open source CMSIS-DAP software project + +- FlexIO header + +For more information about the K82F SoC and FRDM-K82F board: + +- `K82F Website`_ +- `K82F Datasheet`_ +- `K82F Reference Manual`_ +- `FRDM-K82F Website`_ +- `FRDM-K82F User Guide`_ +- `FRDM-K82F Schematics`_ + +Supported Features +================== + +The frdm_k82f board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the frdm_k64f board may have additional features +already supported, which can also be re-used on this frdm_k82f board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| FLASH | off-chip | QSPI flash | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FTFA | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/frdm_k82f/frdm_k82f_defconfig` + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The K82F SoC is configured to use the 12 MHz external oscillator on the board +with the on-chip PLL to generate a 120 MHz system clock. + +Serial Port +=========== + +The K82F SoC has five UARTs. One is configured for the console, the remaining +ones are not used. + +USB +=== + +The K82F SoC has a USB OTG (USBOTG) controller that supports both +device and host functions through its micro USB connector (J11). +Only USB device function is supported in Zephyr at the moment. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) +------------------------------------------------------------------ + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program +the `OpenSDA DAPLink FRDM-K82F Firmware`_. + +Option 2: :ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Firmware for FRDM-K82F`_. + +Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and +``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the +default runner from pyOCD to J-Link: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k82f + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J5. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k82f + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! frdm_k82f + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k82f + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! frdm_k82f + +.. _FRDM-K82F Website: + https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k82-k81-and-k80-mcus:FRDM-K82F + +.. _FRDM-K82F User Guide: + https://www.nxp.com/webapp/Download?colCode=FRDMK82FUG + +.. _FRDM-K82F Schematics: + https://www.nxp.com/downloads/en/schematics/FRDM-K82F-SCH.pdf + +.. _K82F Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k8x-secure/kinetis-k82-150-mhz-hw-cryptographic-co-processor-quadspi-microcontrollers-mcus-based-on-arm-cortex-m4-core:K82_150 + +.. _K82F Datasheet: + https://www.nxp.com/docs/en/data-sheet/K82P121M150SF5.pdf + +.. _K82F Reference Manual: + https://www.nxp.com/webapp/Download?colCode=K82P121M150SF5RM + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _OpenSDA DAPLink FRDM-K82F Firmware: + https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk82f_if_crc_legacy_0x8000.bin + +.. _OpenSDA J-Link Firmware for FRDM-K82F: + https://www.segger.com/downloads/jlink/OpenSDA_FRDM-K82F diff --git a/boards/arm/frdm_k82f/frdm_k82f-pinctrl.dtsi b/boards/nxp/frdm_k82f/frdm_k82f-pinctrl.dtsi similarity index 100% rename from boards/arm/frdm_k82f/frdm_k82f-pinctrl.dtsi rename to boards/nxp/frdm_k82f/frdm_k82f-pinctrl.dtsi diff --git a/boards/arm/frdm_k82f/frdm_k82f.dts b/boards/nxp/frdm_k82f/frdm_k82f.dts similarity index 100% rename from boards/arm/frdm_k82f/frdm_k82f.dts rename to boards/nxp/frdm_k82f/frdm_k82f.dts diff --git a/boards/arm/frdm_k82f/frdm_k82f.yaml b/boards/nxp/frdm_k82f/frdm_k82f.yaml similarity index 100% rename from boards/arm/frdm_k82f/frdm_k82f.yaml rename to boards/nxp/frdm_k82f/frdm_k82f.yaml diff --git a/boards/arm/frdm_k82f/frdm_k82f_defconfig b/boards/nxp/frdm_k82f/frdm_k82f_defconfig similarity index 83% rename from boards/arm/frdm_k82f/frdm_k82f_defconfig rename to boards/nxp/frdm_k82f/frdm_k82f_defconfig index 8b8a4e33367..752e5539cbb 100644 --- a/boards/arm/frdm_k82f/frdm_k82f_defconfig +++ b/boards/nxp/frdm_k82f/frdm_k82f_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_KINETIS_K8X=y -CONFIG_SOC_MK82F25615=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/usb_kw24d512/CMakeLists.txt b/boards/nxp/frdm_kl25z/CMakeLists.txt similarity index 100% rename from boards/arm/usb_kw24d512/CMakeLists.txt rename to boards/nxp/frdm_kl25z/CMakeLists.txt diff --git a/boards/nxp/frdm_kl25z/Kconfig.defconfig b/boards/nxp/frdm_kl25z/Kconfig.defconfig new file mode 100644 index 00000000000..5f32a4528a7 --- /dev/null +++ b/boards/nxp/frdm_kl25z/Kconfig.defconfig @@ -0,0 +1,31 @@ +# FRDM-KL25Z board + +# Copyright (c) 2017, NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_KL25Z + +config OSC_XTAL0_FREQ + default 8000000 + +config MCG_PRDIV0 + default 0x01 + +config MCG_VDIV0 + default 0x00 + +config MCG_FRDIV + default 5 + +config MCG_FCRDIV + default 0 + +if FXOS8700 + +choice FXOS8700_MODE + default FXOS8700_MODE_ACCEL +endchoice + +endif # FXOS8700 + +endif # BOARD_FRDM_KL25Z diff --git a/boards/nxp/frdm_kl25z/Kconfig.frdm_kl25z b/boards/nxp/frdm_kl25z/Kconfig.frdm_kl25z new file mode 100644 index 00000000000..20165db2180 --- /dev/null +++ b/boards/nxp/frdm_kl25z/Kconfig.frdm_kl25z @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_KL25Z + select SOC_MKL25Z4 + select SOC_PART_NUMBER_MKL25Z128VLK4 diff --git a/boards/arm/frdm_kl25z/board.cmake b/boards/nxp/frdm_kl25z/board.cmake similarity index 100% rename from boards/arm/frdm_kl25z/board.cmake rename to boards/nxp/frdm_kl25z/board.cmake diff --git a/boards/nxp/frdm_kl25z/board.yml b/boards/nxp/frdm_kl25z/board.yml new file mode 100644 index 00000000000..0caf35c690e --- /dev/null +++ b/boards/nxp/frdm_kl25z/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_kl25z + vendor: nxp + socs: + - name: mkl25z4 diff --git a/boards/arm/frdm_kl25z/doc/frdm_kl25z.jpg b/boards/nxp/frdm_kl25z/doc/frdm_kl25z.jpg similarity index 100% rename from boards/arm/frdm_kl25z/doc/frdm_kl25z.jpg rename to boards/nxp/frdm_kl25z/doc/frdm_kl25z.jpg diff --git a/boards/nxp/frdm_kl25z/doc/index.rst b/boards/nxp/frdm_kl25z/doc/index.rst new file mode 100644 index 00000000000..6695974c29e --- /dev/null +++ b/boards/nxp/frdm_kl25z/doc/index.rst @@ -0,0 +1,250 @@ +.. _frdm_kl25z: + +NXP FRDM-KL25Z +############## + +Overview +******** + +The Freedom KL25Z is an ultra-low-cost development platform for +Kinetis |reg| L Series KL1x (KL14/15) and KL2x (KL24/25) MCUs built +on ARM |reg| Cortex |reg|-M0+ processor. + +The FRDM-KL25Z features include easy access to MCU I/O, battery-ready, +low-power operation, a standard-based form factor with expansion board +options and a built-in debug interface for flash programming and run-control. + + +.. image:: frdm_kl25z.jpg + :align: center + :alt: FRDM-KL25Z + +Hardware +******** + +- MKL25Z128VLK4 MCU @ 48 MHz, 128 KB flash, 16 KB SRAM, USB OTG (FS), 80LQFP +- On board capacitive touch "slider", MMA8451Q accelerometer, and tri-color LED +- OpenSDA debug interface + +For more information about the KL25Z SoC and FRDM-KL25Z board: + +- `KL25Z Website`_ +- `KL25Z Datasheet`_ +- `KL25Z Reference Manual`_ +- `FRDM-KL25Z Website`_ +- `FRDM-KL25Z User Guide`_ +- `FRDM-KL25Z Schematics`_ + +Supported Features +================== + +The frdm_kl25z board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/frdm_kl25z/frdm_kl25z_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The KL25Z SoC has five pairs of pinmux/gpio controllers, and all are currently enabled +(PORTA/GPIOA, PORTB/GPIOB, PORTC/GPIOC, PORTD/GPIOD, and PORTE/GPIOE) for the FRDM-KL25Z board. + ++-------+-------------+---------------------------+ +| Name | Function | Usage | ++=======+=============+===========================+ +| PTB2 | ADC | ADC0 channel 12 | ++-------+-------------+---------------------------+ +| PTB18 | GPIO | Red LED | ++-------+-------------+---------------------------+ +| PTB19 | GPIO | Green LED | ++-------+-------------+---------------------------+ +| PTD1 | GPIO | Blue LED | ++-------+-------------+---------------------------+ +| PTA1 | UART0_RX | UART Console | ++-------+-------------+---------------------------+ +| PTA2 | UART0_TX | UART Console | ++-------+-------------+---------------------------+ +| PTE24 | I2C0_SCL | I2C | ++-------+-------------+---------------------------+ +| PTE25 | I2C0_SDA | I2C | ++-------+-------------+---------------------------+ + + +System Clock +============ + +The KL25Z SoC is configured to use the 8 MHz external oscillator on the board +with the on-chip FLL to generate a 48 MHz system clock. + +Serial Port +=========== + +The KL25Z UART0 is used for the console. + +USB +=== + +The KL25Z SoC has a USB OTG (USBOTG) controller that supports both +device and host functions through its mini USB connector (USB KL25Z). +Only USB device function is supported in Zephyr at the moment. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +Option 1: Linkserver: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) +------------------------------------------------------------------------------ + + Install the :ref:`linkserver-debug-host-tools` and make sure they are in your + search path. LinkServer works with the CMSIS-DAP debug firmware. Please follow the + instructions on :ref:`opensda-daplink-onboard-debug-probe` and select the latest revision + of the firmware image. + + Linkserver is the default for this board, ``west flash`` and ``west debug`` will + call the linkserver runner. + + .. code-block:: console + + west flash + west debug + +Option 2: :ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link FRDM-KL25Z Firmware`_. + +Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and +``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the +default runner from pyOCD to J-Link: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kl25z + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Note: +----- + +The runners supported by NXP are LinkServer and JLink. pyOCD is another potential option, +but NXP does not test or support the pyOCD runner. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J7. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kl25z + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_kl25z + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kl25z + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_kl25z + +.. _FRDM-KL25Z Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/l-seriesultra-low-powerm0-plus/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z + +.. _FRDM-KL25Z User Guide: + https://www.nxp.com/webapp/Download?colCode=FRDMKL25ZUM + +.. _FRDM-KL25Z Schematics: + https://www.nxp.com/downloads/en/schematics/FRDM-KL25Z_SCH_REV_E.pdf + +.. _KL25Z Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/l-seriesultra-low-powerm0-plus/kinetis-kl2x-72-96mhz-usb-ultra-low-power-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KL2x?&l + +.. _KL25Z Datasheet: + https://www.nxp.com/docs/en/data-sheet/KL25P80M48SF0.pdf + +.. _KL25Z Reference Manual: + https://www.nxp.com/webapp/Download?colCode=KL25P80M48SF0RM + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _OpenSDA DAPLink FRDM-KL25Z Firmware: + https://www.nxp.com/downloads/en/ide-debug-compile-build-tools/OpenSDAv2.2_DAPLink_frdmkl25z_rev0242.zip + +.. _OpenSDA J-Link FRDM-KL25Z Firmware: + https://www.segger.com/downloads/jlink/OpenSDA_FRDM-KL25Z diff --git a/boards/arm/frdm_kl25z/frdm_kl25z-pinctrl.dtsi b/boards/nxp/frdm_kl25z/frdm_kl25z-pinctrl.dtsi similarity index 100% rename from boards/arm/frdm_kl25z/frdm_kl25z-pinctrl.dtsi rename to boards/nxp/frdm_kl25z/frdm_kl25z-pinctrl.dtsi diff --git a/boards/arm/frdm_kl25z/frdm_kl25z.dts b/boards/nxp/frdm_kl25z/frdm_kl25z.dts similarity index 100% rename from boards/arm/frdm_kl25z/frdm_kl25z.dts rename to boards/nxp/frdm_kl25z/frdm_kl25z.dts diff --git a/boards/arm/frdm_kl25z/frdm_kl25z.yaml b/boards/nxp/frdm_kl25z/frdm_kl25z.yaml similarity index 100% rename from boards/arm/frdm_kl25z/frdm_kl25z.yaml rename to boards/nxp/frdm_kl25z/frdm_kl25z.yaml diff --git a/boards/arm/frdm_kl25z/frdm_kl25z_defconfig b/boards/nxp/frdm_kl25z/frdm_kl25z_defconfig similarity index 85% rename from boards/arm/frdm_kl25z/frdm_kl25z_defconfig rename to boards/nxp/frdm_kl25z/frdm_kl25z_defconfig index 54f27a6c14e..0645bba8800 100644 --- a/boards/arm/frdm_kl25z/frdm_kl25z_defconfig +++ b/boards/nxp/frdm_kl25z/frdm_kl25z_defconfig @@ -1,6 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_KINETIS_KL2X=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm64/bcm958402m2_a72/CMakeLists.txt b/boards/nxp/frdm_kw41z/CMakeLists.txt similarity index 100% rename from boards/arm64/bcm958402m2_a72/CMakeLists.txt rename to boards/nxp/frdm_kw41z/CMakeLists.txt diff --git a/boards/nxp/frdm_kw41z/Kconfig.defconfig b/boards/nxp/frdm_kw41z/Kconfig.defconfig new file mode 100644 index 00000000000..2f1d83f690e --- /dev/null +++ b/boards/nxp/frdm_kw41z/Kconfig.defconfig @@ -0,0 +1,25 @@ +# FRDM-KW41Z board + +# Copyright (c) 2017, NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_KW41Z + +config OSC_XTAL0_FREQ + default 32000000 + +config MCG_FRDIV + default 5 + +config MCG_FCRDIV + default 0 + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +choice ADC_MCUX_ADC16_VREF + default ADC_MCUX_ADC16_VREF_ALTERNATE +endchoice + +endif # BOARD_FRDM_KW41Z diff --git a/boards/nxp/frdm_kw41z/Kconfig.frdm_kw41z b/boards/nxp/frdm_kw41z/Kconfig.frdm_kw41z new file mode 100644 index 00000000000..3044a899ed0 --- /dev/null +++ b/boards/nxp/frdm_kw41z/Kconfig.frdm_kw41z @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_KW41Z + select SOC_MKW41Z4 + select SOC_PART_NUMBER_MKW41Z512VHT4 diff --git a/boards/arm/frdm_kw41z/board.cmake b/boards/nxp/frdm_kw41z/board.cmake similarity index 100% rename from boards/arm/frdm_kw41z/board.cmake rename to boards/nxp/frdm_kw41z/board.cmake diff --git a/boards/nxp/frdm_kw41z/board.yml b/boards/nxp/frdm_kw41z/board.yml new file mode 100644 index 00000000000..b17c67beb3e --- /dev/null +++ b/boards/nxp/frdm_kw41z/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_kw41z + vendor: nxp + socs: + - name: mkw41z4 diff --git a/boards/arm/frdm_kw41z/doc/frdm_kw41z.jpg b/boards/nxp/frdm_kw41z/doc/frdm_kw41z.jpg similarity index 100% rename from boards/arm/frdm_kw41z/doc/frdm_kw41z.jpg rename to boards/nxp/frdm_kw41z/doc/frdm_kw41z.jpg diff --git a/boards/nxp/frdm_kw41z/doc/index.rst b/boards/nxp/frdm_kw41z/doc/index.rst new file mode 100644 index 00000000000..4457b6d9b16 --- /dev/null +++ b/boards/nxp/frdm_kw41z/doc/index.rst @@ -0,0 +1,259 @@ +.. _frdm_kw41z: + +NXP FRDM-KW41Z +############## + +Overview +******** + +The FRDM-KW41Z is a development kit enabled by the Kinetis |reg| W series +KW41Z/31Z/21Z (KW41Z) family built on ARM |reg| Cortex |reg|-M0+ processor with +integrated 2.4 GHz transceiver supporting Bluetooth |reg| Smart/Bluetooth +|reg| Low Energy +(BLE) v4.2, Generic FSK, IEEE |reg| 802.15.4 and Thread. + +The FRDM-KW41Z kit contains two Freedom boards that can be used as a +development board or a shield to connect to a host processor. The FRDM-KW41Z is +form-factor compatible with the Arduino |trade| R3 pin layout for more expansion +options. + +The FRDM-KW41Z highly-sensitive, optimized 2.4 GHz radio features a PCB +F-antenna which can be bypassed to test via SMA connection, multiple power +supply options, push/capacitive touch buttons, switches, LEDs and integrated +sensors. + +.. image:: frdm_kw41z.jpg + :align: center + :alt: FRDM-KW41Z + +Hardware +******** + +- Can be configured as Host or Shield for connection to Host Processor +- Supports all DC-DC configurations (Buck, Boost, Bypass) +- PCB inverted F-type antenna +- SMA RF Connector +- RF regulatory certified +- Serial Flash for OTA firmware upgrades +- On board NXP FXOS8700CQ digital sensor, 3D Accelerometer ( |plusminus| 2g/ + |plusminus| 4g/ |plusminus| 8g) + 3D + Magnetometer +- OpenSDA and JTAG debug + +For more information about the KW41Z SoC and FRDM-KW41Z board: + +- `KW41Z Website`_ +- `KW41Z Datasheet`_ +- `KW41Z Reference Manual`_ +- `FRDM-KW41Z Website`_ +- `FRDM-KW41Z User Guide`_ +- `FRDM-KW41Z Schematics`_ + +Supported Features +================== + +The frdm_kw41z board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling: | +| | | fxos8700 trigger | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | tpm | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FTFA | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/frdm_kw41z/frdm_kw41z_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The KW41Z SoC has three pairs of pinmux/gpio controllers, but only two are +currently enabled (PORTA/GPIOA and PORTC/GPIOC) for the FRDM-KW41Z board. + ++-------+-------------+---------------------------+ +| Name | Function | Usage | ++=======+=============+===========================+ +| PTC1 | GPIO | Red LED / FXOS8700 INT1 | ++-------+-------------+---------------------------+ +| PTA19 | GPIO | Green LED | ++-------+-------------+---------------------------+ +| PTA18 | GPIO | Blue LED | ++-------+-------------+---------------------------+ +| PTB2 | ADC | ADC0 channel 3 | ++-------+-------------+---------------------------+ +| PTC2 | I2C1_SCL | I2C / FXOS8700 | ++-------+-------------+---------------------------+ +| PTC3 | I2C1_SDA | I2C / FXOS8700 | ++-------+-------------+---------------------------+ +| PTC4 | GPIO | SW3 | ++-------+-------------+---------------------------+ +| PTC5 | GPIO | SW4 | ++-------+-------------+---------------------------+ +| PTC6 | LPUART0_RX | UART Console | ++-------+-------------+---------------------------+ +| PTC7 | LPUART0_TX | UART Console | ++-------+-------------+---------------------------+ +| PTC16 | SPI0_SCK | SPI | ++-------+-------------+---------------------------+ +| PTC17 | SPI0_SOUT | SPI | ++-------+-------------+---------------------------+ +| PTC18 | SPI0_SIN | SPI | ++-------+-------------+---------------------------+ +| PTC19 | SPI0_PCS0 | SPI | ++-------+-------------+---------------------------+ + +System Clock +============ + +The KW41Z SoC is configured to use the 32 MHz external oscillator on the board +with the on-chip FLL to generate a 40 MHz system clock. + +Serial Port +=========== + +The KW41Z SoC has one UART, which is used for the console. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) +------------------------------------------------------------------ + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program +the `OpenSDA DAPLink FRDM-KW41Z Firmware`_. + +Option 2: :ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link FRDM-KW41Z Firmware`_. + +Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and +``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the +default runner from pyOCD to J-Link: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kw41z + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J6. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kw41z + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_kw41z + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kw41z + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_kw41z + +.. _FRDM-KW41Z Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/freedom-development-kit-for-kinetis-kw41z-31z-21z-mcus:FRDM-KW41Z + +.. _FRDM-KW41Z User Guide: + https://www.nxp.com/webapp/Download?colCode=FRDMKW41ZUG + +.. _FRDM-KW41Z Schematics: + https://www.nxp.com/webapp/Download?colCode=FRDM-KW41Z-SCH + +.. _KW41Z Website: + https://www.nxp.com/products/wireless/zigbee/kinetis-kw41z-2.4-ghz-dual-mode-bluetooth-low-energy-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW41Z + +.. _KW41Z Datasheet: + https://www.nxp.com/docs/en/data-sheet/MKW41Z512.pdf + +.. _KW41Z Reference Manual: + https://www.nxp.com/webapp/Download?colCode=MKW41Z512RM + +.. _OpenSDA DAPLink FRDM-KW41Z Firmware: + https://www.nxp.com/downloads/en/reference-applications/OpenSDAv2.2_DAPLink_frdmkw41z_rev0241.zip + +.. _OpenSDA J-Link FRDM-KW41Z Firmware: + https://www.segger.com/downloads/jlink/OpenSDA_FRDM-KW41Z diff --git a/boards/arm/frdm_kw41z/frdm_kw41z-pinctrl.dtsi b/boards/nxp/frdm_kw41z/frdm_kw41z-pinctrl.dtsi similarity index 100% rename from boards/arm/frdm_kw41z/frdm_kw41z-pinctrl.dtsi rename to boards/nxp/frdm_kw41z/frdm_kw41z-pinctrl.dtsi diff --git a/boards/arm/frdm_kw41z/frdm_kw41z.dts b/boards/nxp/frdm_kw41z/frdm_kw41z.dts similarity index 100% rename from boards/arm/frdm_kw41z/frdm_kw41z.dts rename to boards/nxp/frdm_kw41z/frdm_kw41z.dts diff --git a/boards/arm/frdm_kw41z/frdm_kw41z.yaml b/boards/nxp/frdm_kw41z/frdm_kw41z.yaml similarity index 100% rename from boards/arm/frdm_kw41z/frdm_kw41z.yaml rename to boards/nxp/frdm_kw41z/frdm_kw41z.yaml diff --git a/boards/arm/frdm_kw41z/frdm_kw41z_defconfig b/boards/nxp/frdm_kw41z/frdm_kw41z_defconfig similarity index 78% rename from boards/arm/frdm_kw41z/frdm_kw41z_defconfig rename to boards/nxp/frdm_kw41z/frdm_kw41z_defconfig index f72dbb5af69..ec5a311d8fe 100644 --- a/boards/arm/frdm_kw41z/frdm_kw41z_defconfig +++ b/boards/nxp/frdm_kw41z/frdm_kw41z_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_MKW41Z4=y -CONFIG_SOC_SERIES_KINETIS_KWX=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/hexiwear/Kconfig.defconfig b/boards/nxp/hexiwear/Kconfig.defconfig new file mode 100644 index 00000000000..652e7dac804 --- /dev/null +++ b/boards/nxp/hexiwear/Kconfig.defconfig @@ -0,0 +1,39 @@ +# Hexiwear K64 board + +# Copyright (c) 2016, Freescale Semiconductor, Inc. +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HEXIWEAR_MK64F12 + +config OSC_XTAL0_FREQ + default 12000000 + +config MCG_PRDIV0 + default 0x02 + +config MCG_VDIV0 + default 0x06 + +config MCG_FCRDIV + default 1 + +config REGULATOR + default y if ADC || SENSOR + +endif # BOARD_HEXIWEAR_MK64F12 + +# Hexiwear KW40Z board + +if BOARD_HEXIWEAR_MKW40Z4 + +config OSC_XTAL0_FREQ + default 32000000 + +config MCG_FRDIV + default 5 + +config MCG_FCRDIV + default 0 + +endif # BOARD_HEXIWEAR_MKW40Z4 diff --git a/boards/nxp/hexiwear/Kconfig.hexiwear b/boards/nxp/hexiwear/Kconfig.hexiwear new file mode 100644 index 00000000000..5acdde083f4 --- /dev/null +++ b/boards/nxp/hexiwear/Kconfig.hexiwear @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HEXIWEAR + select SOC_MK64F12 if BOARD_HEXIWEAR_MK64F12 + select SOC_PART_NUMBER_MK64FN1M0VDC12 if BOARD_HEXIWEAR_MK64F12 + select SOC_MKW40Z4 if BOARD_HEXIWEAR_MKW40Z4 + select SOC_PART_NUMBER_MKW40Z160VHT4 if BOARD_HEXIWEAR_MKW40Z4 diff --git a/boards/nxp/hexiwear/board.cmake b/boards/nxp/hexiwear/board.cmake new file mode 100644 index 00000000000..c56e7d5e138 --- /dev/null +++ b/boards/nxp/hexiwear/board.cmake @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +if (CONFIG_BOARD_HEXIWEAR_MK64F12) + board_runner_args(pyocd "--target=k64f") + board_runner_args(jlink "--device=MK64FN1M0xxx12") + + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +else() + board_runner_args(jlink "--device=MKW40Z160xxx4") + board_runner_args(pyocd "--target=kw40z4") + + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +endif() diff --git a/boards/nxp/hexiwear/board.yml b/boards/nxp/hexiwear/board.yml new file mode 100644 index 00000000000..c478fa02678 --- /dev/null +++ b/boards/nxp/hexiwear/board.yml @@ -0,0 +1,6 @@ +board: + name: hexiwear + vendor: nxp + socs: + - name: mk64f12 + - name: mkw40z4 diff --git a/boards/arm/hexiwear_k64/doc/hexiwear_k64.jpg b/boards/nxp/hexiwear/doc/hexiwear_k64.jpg similarity index 100% rename from boards/arm/hexiwear_k64/doc/hexiwear_k64.jpg rename to boards/nxp/hexiwear/doc/hexiwear_k64.jpg diff --git a/boards/nxp/hexiwear/doc/index.rst b/boards/nxp/hexiwear/doc/index.rst new file mode 100644 index 00000000000..bc4d58a70d4 --- /dev/null +++ b/boards/nxp/hexiwear/doc/index.rst @@ -0,0 +1,517 @@ +.. _hexiwear: + +Hexiwear +######## + +Overview +******** + +Hexiwear is powered by a Kinetis K64 microcontroller based on the ARM Cortex-M4 +core. Another Kinetis wireless MCU, the KW40Z, provides Bluetooth Low Energy +connectivity. Hexiwear also integrates a wide variety of sensors, as well as a +user interface consisting of a 1.1" 96px x 96px full color OLED display and six +capacitive buttons with haptic feedback. + +- Eye-catching Smart Watch form factor with powerful, low power Kinetis K6x MCU + and 6 on-board sensors. +- Designed for wearable applications with the onboard rechargeable battery, + OLED screen and onboard sensors such as optical heart rate, accelerometer, + magnetometer and gyroscope. +- Designed for IoT end node applications with the onboard sensor's such as + temperature, pressure, humidity and ambient light. +- Flexibility to let you add the sensors of your choice nearly 200 additional + sensors through click boards. + +.. image:: hexiwear_k64.jpg + :align: center + :alt: Hexiwear + +Hardware +******** + +- Main MCU: NXP Kinetis K64x (ARM Cortex-M4, 120 MHz, 1M Flash, 256K SRAM) +- Wireless MCU: NXP Kinetis KW4x (ARM Cortex-M0+, Bluetooth Low Energy & + 802.15.4 radio) +- 6-axis combo Accelerometer and Magnetometer NXP FXOS8700 +- 3-Axis Gyroscope: NXP FXAS21002 +- Absolute Pressure sensor NXP MPL3115 +- Li-Ion/Li-Po Battery Charger NXP MC34671 +- Optical heart rate sensor Maxim MAX30101 +- Ambient Light sensor, Humidity and Temperature sensor +- 1.1" full color OLED display +- Haptic feedback engine +- 190 mAh 2C Li-Po battery +- Capacitive touch interface +- RGB LED + +For more information about the K64F SoC and Hexiwear board: + +- `K64F Website`_ +- `K64F Datasheet`_ +- `K64F Reference Manual`_ +- `Hexiwear Website`_ +- `Hexiwear Fact Sheet`_ +- `Hexiwear Schematics`_ + +Supported Features +================== + +The hexiwear/mk64f12 board variant supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger; | +| | | fxas21002 polling; | +| | | fxas21002 trigger; | +| | | max30101 polling | ++-----------+------------+-------------------------------------+ +| RNGA | on-chip | entropy; | +| | | random | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/nxp/hexiwear/hexiwear_mk64f12_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The K64F SoC has five pairs of pinmux/gpio controllers. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTA29 | GPIO | LDO_EN | ++-------+-----------------+---------------------------+ +| PTB0 | I2C0_SCL | I2C / MAX30101 | ++-------+-----------------+---------------------------+ +| PTB1 | I2C0_SDA | I2C / MAX30101 | ++-------+-----------------+---------------------------+ +| PTB12 | GPIO | 3V3B EN | ++-------+-----------------+---------------------------+ +| PTB16 | UART0_RX | UART Console | ++-------+-----------------+---------------------------+ +| PTB17 | UART0_TX | UART Console | ++-------+-----------------+---------------------------+ +| PTC8 | GPIO / PWM | Red LED | ++-------+-----------------+---------------------------+ +| PTC9 | GPIO / PWM | Green LED | ++-------+-----------------+---------------------------+ +| PTC10 | I2C1_SCL | I2C / FXOS8700 / FXAS21002| ++-------+-----------------+---------------------------+ +| PTC11 | I2C1_SDA | I2C / FXOS8700 / FXAS21002| ++-------+-----------------+---------------------------+ +| PTC14 | GPIO | Battery sense enable | ++-------+-----------------+---------------------------+ +| PTC18 | GPIO | FXAS21002 INT2 | ++-------+-----------------+---------------------------+ +| PTD0 | GPIO / PWM | Blue LED | ++-------+-----------------+---------------------------+ +| PTD13 | GPIO | FXOS8700 INT2 | ++-------+-----------------+---------------------------+ +| PTE24 | UART4_RX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTE25 | UART4_TX | UART BT HCI | ++-------+-----------------+---------------------------+ + +.. note:: + + To enable battery sensing, you will need to enable the ``en_bat_sens`` + regulator in Devicetree. Similarly, to enable devices connected to the 1V8 + or 3V3 power rails (sensors), you will need to enable the ``en_ldo`` + and ``en_3v3b`` regulators in Devicetree. + +System Clock +============ + +The K64F SoC is configured to use the 12 MHz external oscillator on the board +with the on-chip PLL to generate a 120 MHz system clock. + +Serial Port +=========== + +The K64F SoC has six UARTs. One is configured for the console, another for BT +HCI, and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +but because Segger RTT is required for a console on KW40Z, we recommend that +you reconfigure the board for the :ref:`opensda-jlink-onboard-debug-probe`. + +.. note:: + OpenSDA is shared between the K64 and the KW40Z via switches, therefore only + one SoC can be flashed, debugged, or have an open console at a time. + +Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended) +---------------------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches +SW1 and SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals +are connected to the OpenSDA microcontroller. + +Option 2: :ref:`opensda-daplink-onboard-debug-probe` +---------------------------------------------------- + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to +program the `OpenSDA DAPLink Hexiwear Firmware`_. Check that switches SW1 and +SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals are +connected to the OpenSDA microcontroller. + +Add the arguments ``-DBOARD_FLASH_RUNNER=pyocd`` and +``-DBOARD_DEBUG_RUNNER=pyocd`` when you invoke ``west build`` to override the +default runner from J-Link to pyOCD: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mk64f12 + :gen-args: -DBOARD_FLASH_RUNNER=pyocd -DBOARD_DEBUG_RUNNER=pyocd + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to CN1. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mk64f12 + :goals: flash + +Open a serial terminal, reset the board (press the T4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mk64f12 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +Using Bluetooth +*************** + +Configure the KW40Z as a Bluetooth controller +============================================= + +The K64 can support Zephyr Bluetooth host applications when you configure the +KW40Z as a Bluetooth controller. + +#. Download and install the `KW40Z Connectivity Software`_. This package + contains Bluetooth controller application for the KW40Z. +#. Flash the file ``tools/binaries/BLE_HCI_Modem.bin`` to the KW40Z. + +Now you can build and run the sample Zephyr Bluetooth host applications on the +K64. You do not need to repeat this step each time you flash a new Bluetooth +host application to the K64. + +Peripheral Heart Rate Sensor +============================ + +Navigate to the Zephyr ``samples/bluetooth/peripheral_hr`` sample +application, then build and flash it to the Hexiwear K64. Make sure +the OpenSDA switches on the docking station are configured for the +K64. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/peripheral_hr + :board: hexiwear/mk64f12 + :goals: build flash + +Reset the KW40Z and the K64 using the push buttons on the docking station. + +Install the Kinetis BLE Toolbox on your smartphone: + +- `Kinetis BLE Toolbox for iOS`_ +- `Kinetis BLE Toolbox for Android`_ + +Open the app, tap the **Heart Rate** feature, and you should see a **Zephyr +Heartrate Sensor** device. Tap the **Zephyr Heartrate Sensor** device and you +will then see a plot of the heart rate data that updates once per second. + + +.. _Hexiwear Website: + https://www.mikroe.com/hexiwear + +.. _Hexiwear Fact Sheet: + https://www.nxp.com/docs/en/fact-sheet/HEXIWEAR-FS.pdf + +.. _Hexiwear Schematics: + http://cdn-docs.mikroe.com/images/c/c0/Sch_Hexiwear_MainBoard_v106c.pdf + +.. _K64F Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k6x-ethernet/kinetis-k64-120-mhz-256kb-sram-microcontrollers-mcus-based-on-arm-cortex-m4-core:K64_120 + +.. _K64F Datasheet: + https://www.nxp.com/docs/en/data-sheet/K64P144M120SF5.pdf + +.. _K64F Reference Manual: + https://www.nxp.com/docs/en/reference-manual/K64P144M120SF5RM.pdf + +.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: + https://www.segger.com/downloads/jlink/OpenSDA_V2_1 + +.. _OpenSDA DAPLink Hexiwear Firmware: + https://github.com/MikroElektronika/HEXIWEAR/blob/master/HW/HEXIWEAR_DockingStation/HEXIWEAR_DockingStation_DAPLINK_FW.bin + +.. _KW40Z Connectivity Software: + https://www.nxp.com/webapp/Download?colCode=KW40Z-CONNECTIVITY-SOFTWARE&appType=license&location=null&fpsp=1&WT_TYPE=Protocol%20Stacks&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=exe&WT_ASSET=Downloads&fileExt=.exe&Parent_nodeId=1432854896956716810497&Parent_pageType=product + +.. _Kinetis BLE Toolbox for iOS: + https://itunes.apple.com/us/app/kinetis-ble-toolbox/id1049036961?mt=8 + +.. _Kinetis BLE Toolbox for Android: + https://play.google.com/store/apps/details?id=com.freescale.kinetisbletoolbox + + +Hexiwear KW40Z +############## + +Overview +******** + +The KW40Z is a secondary SoC on the board that provides wireless connectivity +with a multimode BLE and 802.15.4 radio. + +For more information about the KW40Z SoC: + +- `KW40Z Website`_ +- `KW40Z Datasheet`_ +- `KW40Z Reference Manual`_ + +Supported Features +================== + +The hexiwear/mkw40z4 board variant supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| RTT | on-chip | console | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The KW40Z SoC has three pairs of pinmux/gpio controllers, but only one is +currently enabled (PORTC/GPIOC) for the hexiwear/mkw40z4 board. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTB1 | ADC | ADC0 channel 1 | ++-------+-----------------+---------------------------+ +| PTC6 | UART0_RX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTC7 | UART0_TX | UART BT HCI | ++-------+-----------------+---------------------------+ + +System Clock +============ + +The KW40Z SoC is configured to use the 32 MHz external oscillator on the board +with the on-chip FLL to generate a 40 MHz system clock. + +Serial Port +=========== + +The KW40Z SoC has one UART, which is used for BT HCI. There is no UART +available for a console. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +but because Segger RTT is required for a console, you must reconfigure the +board for one of the following debug probes instead. + +:ref:`opensda-jlink-onboard-debug-probe` +---------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches +SW1 and SW2 are **off**, and SW3 and SW4 are **on** to ensure KW40Z SWD signals +are connected to the OpenSDA microcontroller. + +Configuring a Console +===================== + +The console is available using `Segger RTT`_. + +Connect a USB cable from your PC to CN1. + +Once you have started a debug session, run telnet: + +.. code-block:: console + + $ telnet localhost 19021 + Trying 127.0.0.1... + Connected to localhost. + Escape character is '^]'. + SEGGER J-Link V6.44 - Real time terminal output + J-Link OpenSDA 2 compiled Feb 28 2017 19:27:57 V1.0, SN=621000000 + Process: JLinkGDBServerCLExe + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mkw40z4 + :goals: flash + +The Segger RTT console is only available during a debug session. Use ``attach`` +to start one: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mkw40z4 + :goals: attach + +Run telnet as shown earlier, and you should see the following message in the +terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mkw40z4 + :goals: debug + +Run telnet as shown earlier, step through the application in your debugger, and +you should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +.. _KW40Z Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/kinetis-kw40z-2.4-ghz-dual-mode-ble-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW40Z + +.. _KW40Z Datasheet: + https://www.nxp.com/docs/en/data-sheet/MKW40Z160.pdf + +.. _KW40Z Reference Manual: + https://www.nxp.com/webapp/Download?colCode=MKW40Z160RM + +.. _Segger RTT: + https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/ + +.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: + https://www.segger.com/downloads/jlink/OpenSDA_V2_1 diff --git a/boards/arm/hexiwear_k64/hexiwear_k64-pinctrl.dtsi b/boards/nxp/hexiwear/hexiwear_mk64f12-pinctrl.dtsi similarity index 100% rename from boards/arm/hexiwear_k64/hexiwear_k64-pinctrl.dtsi rename to boards/nxp/hexiwear/hexiwear_mk64f12-pinctrl.dtsi diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.dts b/boards/nxp/hexiwear/hexiwear_mk64f12.dts new file mode 100644 index 00000000000..bbd3b43051e --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mk64f12.dts @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include +#include +#include "hexiwear_mk64f12-pinctrl.dtsi" + +/ { + model = "Hexiwear K64 board"; + compatible = "nxp,hexiwear", "nxp,k64f", "nxp,k6x"; + + aliases { + led0 = &green_led; + led1 = &blue_led; + led2 = &red_led; + pwm-led0 = &green_pwm_led; + red-pwm-led = &red_pwm_led; + green-pwm-led = &green_pwm_led; + blue-pwm-led = &blue_pwm_led; + magn0 = &fxos8700; + accel0 = &fxos8700; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,bt-uart = &uart4; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpioc 8 GPIO_ACTIVE_LOW>; + label = "User LD1"; + }; + green_led: led_1 { + gpios = <&gpiod 0 GPIO_ACTIVE_LOW>; + label = "User LD2"; + }; + blue_led: led_2 { + gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; + label = "User LD3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + red_pwm_led: red_pwm_led { + pwms = <&ftm3 4 15625000 PWM_POLARITY_INVERTED>; + }; + green_pwm_led: green_pwm_led { + pwms = <&ftm3 0 15625000 PWM_POLARITY_INVERTED>; + }; + blue_pwm_led: blue_pwm_led { + pwms = <&ftm3 5 15625000 PWM_POLARITY_INVERTED>; + }; + }; + + en_bat_sens: enable-battery-sense { + compatible = "regulator-fixed"; + regulator-name = "en_bat_sens"; + enable-gpios = <&gpioc 14 GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; + + en_ldo: enable-ldo { + compatible = "regulator-fixed"; + regulator-name = "en_ldo"; + enable-gpios = <&gpioa 29 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + en_3v3b: enable-3v3b { + compatible = "regulator-fixed"; + regulator-name = "en_3v3b"; + enable-gpios = <&gpiob 12 GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; +}; + +&sim { + pllfll-select = ; + er32k-select = ; +}; + +&cpu0 { + clock-frequency = <120000000>; +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&ftm3 { + status = "okay"; + compatible = "nxp,kinetis-ftm-pwm"; + #pwm-cells = <3>; + pinctrl-0 = <&ftm3_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + max30101@57 { + status = "disabled"; + compatible = "maxim,max30101"; + reg = <0x57>; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + + fxos8700: fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + int1-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; + int2-gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; + }; + + fxas21002@20 { + compatible = "nxp,fxas21002"; + reg = <0x20>; + int1-gpios = <&gpiod 1 GPIO_ACTIVE_LOW>; + int2-gpios = <&gpioc 18 GPIO_ACTIVE_LOW>; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* + * The flash starting at 0x00010000 and ending at + * 0x0001ffff (sectors 16-31) is reserved for use + * by the application. + */ + + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 0x00060000>; + }; + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x00080000 0x00060000>; + }; + scratch_partition: partition@e0000 { + label = "image-scratch"; + reg = <0x000e0000 0x00020000>; + }; + }; +}; diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.yaml b/boards/nxp/hexiwear/hexiwear_mk64f12.yaml new file mode 100644 index 00000000000..d8f165c7131 --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mk64f12.yaml @@ -0,0 +1,16 @@ +identifier: hexiwear/mk64f12 +name: Hexiwear +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - ble + - gpio + - i2c + - pwm + - watchdog +vendor: nxp diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig b/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig new file mode 100644 index 00000000000..8609fa1f8da --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 +CONFIG_OSC_LOW_POWER=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/hexiwear_kw40z/hexiwear_kw40z-pinctrl.dtsi b/boards/nxp/hexiwear/hexiwear_mkw40z4-pinctrl.dtsi similarity index 100% rename from boards/arm/hexiwear_kw40z/hexiwear_kw40z-pinctrl.dtsi rename to boards/nxp/hexiwear/hexiwear_mkw40z4-pinctrl.dtsi diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4.dts b/boards/nxp/hexiwear/hexiwear_mkw40z4.dts new file mode 100644 index 00000000000..c75ca229d34 --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mkw40z4.dts @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include +#include "hexiwear_mkw40z4-pinctrl.dtsi" + +/ { + model = "Hexiwear KW40 board"; + compatible = "nxp,kw40z", "nxp,mkw40z4"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&sim { + pllfll-select = ; + er32k-select = ; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&lpuart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart0_default>; + pinctrl-names = "default"; +}; + +&gpioa { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml b/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml new file mode 100644 index 00000000000..af4d8d5220d --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml @@ -0,0 +1,14 @@ +identifier: hexiwear/mkw40z4 +name: Hexiwear KW40Z +type: mcu +arch: arm +ram: 16 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net +vendor: nxp diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig b/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig new file mode 100644 index 00000000000..4f25cadc1ee --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_RTT_CONSOLE=y +CONFIG_USE_SEGGER_RTT=y +CONFIG_PINCTRL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 +CONFIG_OSC_EXTERNAL=y diff --git a/boards/nxp/imx8mm_evk/Kconfig.defconfig b/boards/nxp/imx8mm_evk/Kconfig.defconfig new file mode 100644 index 00000000000..5cc30c81ed1 --- /dev/null +++ b/boards/nxp/imx8mm_evk/Kconfig.defconfig @@ -0,0 +1,15 @@ +# MIMX8MM EVK board defconfig + +# Copyright (c) 2020, Manivannan Sadhasivam +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IMX8MM_EVK_MIMX8MM6_M4 + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_IMX8MM_EVK_MIMX8MM6_M4 diff --git a/boards/nxp/imx8mm_evk/Kconfig.imx8mm_evk b/boards/nxp/imx8mm_evk/Kconfig.imx8mm_evk new file mode 100644 index 00000000000..390956d2096 --- /dev/null +++ b/boards/nxp/imx8mm_evk/Kconfig.imx8mm_evk @@ -0,0 +1,7 @@ +# Copyright 2021-2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8MM_EVK + select SOC_MIMX8MM6_A53 if BOARD_IMX8MM_EVK_MIMX8MM6_A53 || BOARD_IMX8MM_EVK_MIMX8MM6_A53_SMP + select SOC_MIMX8MM6_M4 if BOARD_IMX8MM_EVK_MIMX8MM6_M4 + select SOC_PART_NUMBER_MIMX8MM6DVTLZ diff --git a/boards/nxp/imx8mm_evk/board.cmake b/boards/nxp/imx8mm_evk/board.cmake new file mode 100644 index 00000000000..ddcd01410a3 --- /dev/null +++ b/boards/nxp/imx8mm_evk/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2024 NXP + +if(CONFIG_BOARD_IMX8MM_EVK_MIMX8MM6_M4) + board_set_debugger_ifnset(jlink) + board_set_flasher_ifnset(jlink) + + board_runner_args(jlink "--device=MIMX8MD6_M4") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nxp/imx8mm_evk/board.yml b/boards/nxp/imx8mm_evk/board.yml new file mode 100644 index 00000000000..0c46177f70b --- /dev/null +++ b/boards/nxp/imx8mm_evk/board.yml @@ -0,0 +1,8 @@ +board: + name: imx8mm_evk + vendor: nxp + socs: + - name: mimx8mm6 + variants: + - name: smp + cpucluster: a53 diff --git a/boards/nxp/imx8mm_evk/doc/index.rst b/boards/nxp/imx8mm_evk/doc/index.rst new file mode 100644 index 00000000000..6483febdcba --- /dev/null +++ b/boards/nxp/imx8mm_evk/doc/index.rst @@ -0,0 +1,237 @@ +.. _imx8mm_evk: + +NXP i.MX8MM EVK +############### + +Overview +******** + +i.MX8M Mini LPDDR4 EVK board is based on NXP i.MX8M Mini applications +processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. +Zephyr OS is ported to run on the Cortex®-A53 core. + +- Board features: + + - RAM: 2GB LPDDR4 + - Storage: + + - SanDisk 16GB eMMC5.1 + - Micron 32MB QSPI NOR + - microSD Socket + - Wireless: + + - WiFi: 2.4/5GHz IEEE 802.11b/g/n + - Bluetooth: v4.1 + - USB: + + - OTG - 2x type C + - Ethernet + - PCI-E M.2 + - Connectors: + + - 40-Pin Dual Row Header + - LEDs: + + - 1x Power status LED + - 1x UART LED + - Debug + + - JTAG 20-pin connector + - MicroUSB for UART debug, two COM ports for A53 and M4 + +More information about the board can be found at the +`NXP website`_. + +Supported Features +================== + +The Zephyr imx8mm_evk board for Cortex-A53 configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +The Zephyr imx8mm_evk board for Cortex-M4 supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig` + +It is recommended to disable peripherals used by the M4 core on the Linux host. + +Other hardware features are not currently supported by the port. + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 8 MHz. + +The M4 Core is configured to run at a 400 MHz clock speed. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART4. This is used for the M4 and A53 core targets. + +Programming and Debugging (A53) +******************************* + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 + +Or kick SMP zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 + + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx8mm_evk/mimx8mm6/a53 + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** + thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mm_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mm_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! + +Use Jailhouse hypervisor, after root cell linux is up: + +.. code-block:: console + + #jailhouse enable imx8mm.cell + #jailhouse cell create imx8mm-zephyr.cell + #jailhouse cell load 1 zephyr.bin -a 0x93c00000 + #jailhouse cell start 1 + +Programming and Debugging (M4) +****************************** + +The MIMX8MM EVK board doesn't have QSPI flash for the M4 and it needs +to be started by the A53 core. The A53 core is responsible to load the M4 binary +application into the RAM, put the M4 in reset, set the M4 Program Counter and +Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at +bootloader level or after the Linux system has booted. + +The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file +:zephyr_file:`boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts` +with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. +The available configurations are: + +.. code-block:: none + + "zephyr,flash" + - &tcml_code + - &ocram_code + - &ocram_s_code + + "zephyr,sram" + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + +Load and run Zephyr on M4 from A53 using u-boot by copying the compiled +``zephyr.bin`` to the first FAT partition of the SD card and plug the SD +card into the board. Power it up and stop the u-boot execution at prompt. + +Load the M4 binary onto the desired memory and start its execution using: + +.. code-block:: console + + fatload mmc 0:1 0x7e0000 zephyr.bin;bootaux 0x7e0000 + +Debugging +========= + +MIMX8MM EVK board can be debugged by connecting an external JLink +JTAG debugger to the J902 debug connector and to the PC. Then +the application can be debugged using the usual way. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx8mm_evk/mimx8mm6/m4 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build zephyr-v2.0.0-1859-g292afe8533c0 ***** + Hello World! imx8mm_evk + +References +========== + +.. _NXP website: + https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/evaluation-kit-for-thebr-i.mx-8m-mini-applications-processor:8MMINILPD4-EVK + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MMRM diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk-pinctrl.dtsi b/boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi similarity index 100% rename from boards/arm64/mimx8mm_evk/mimx8mm_evk-pinctrl.dtsi rename to boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts new file mode 100644 index 00000000000..0a2b5c666ea --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts @@ -0,0 +1,44 @@ +/* + * Copyright 2020-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mm_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MM A53"; + compatible = "fsl,mimx8mm"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + cpu@2 { + status = "disabled"; + }; + }; + + sram0: memory@93c00000 { + reg = <0x93c00000 DT_SIZE_M(1)>; + }; +}; + +&uart4 { + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml new file mode 100644 index 00000000000..1ab75987c38 --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mm_evk/mimx8mm6/a53 +name: NXP i.MX8M Mini EVK A53 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig new file mode 100644 index 00000000000..4e31bf4e946 --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts new file mode 100644 index 00000000000..308094cfb20 --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts @@ -0,0 +1,46 @@ +/* + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mm_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MM A53"; + compatible = "fsl,mimx8mm"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + sram0: memory@93c00000 { + reg = <0x93c00000 DT_SIZE_M(1)>; + }; +}; + +&uart4 { + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml new file mode 100644 index 00000000000..1ff3cd7af45 --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml @@ -0,0 +1,21 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mm_evk/mimx8mm6/a53/smp +name: NXP i.MX8M Mini EVK A53 with SMP kernel +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +supported: + - smp +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig new file mode 100644 index 00000000000..845b48736a7 --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# SMP +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_PM_CPU_OPS=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts new file mode 100644 index 00000000000..e7680d1286f --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2020, Manivannan Sadhasivam + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +#include "imx8mm_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8M Mini EVK board"; + compatible = "nxp,mimx8mm_evk"; + + aliases { + uart-4 = &uart4; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; + +&mailbox0 { + status = "okay"; +}; diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml new file mode 100644 index 00000000000..9ae6cadff5d --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml @@ -0,0 +1,22 @@ +# +# Copyright (c) 2020, Manivannan Sadhasivam +# Copyright 2024 +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mm_evk/mimx8mm6/m4 +name: NXP i.MX8M Mini EVK +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig new file mode 100644 index 00000000000..e0223e4f71f --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2020, Manivannan Sadhasivam +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mn_evk/Kconfig.imx8mn_evk b/boards/nxp/imx8mn_evk/Kconfig.imx8mn_evk new file mode 100644 index 00000000000..f9142e55b0f --- /dev/null +++ b/boards/nxp/imx8mn_evk/Kconfig.imx8mn_evk @@ -0,0 +1,6 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8MN_EVK + select SOC_MIMX8MN6_A53 if BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP + select SOC_PART_NUMBER_MIMX8MN6DVTJZ if BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP diff --git a/boards/arm64/mimx8mm_evk/board.cmake b/boards/nxp/imx8mn_evk/board.cmake similarity index 100% rename from boards/arm64/mimx8mm_evk/board.cmake rename to boards/nxp/imx8mn_evk/board.cmake diff --git a/boards/nxp/imx8mn_evk/board.yml b/boards/nxp/imx8mn_evk/board.yml new file mode 100644 index 00000000000..294060de506 --- /dev/null +++ b/boards/nxp/imx8mn_evk/board.yml @@ -0,0 +1,8 @@ +board: + name: imx8mn_evk + vendor: nxp + socs: + - name: mimx8mn6 + variants: + - name: smp + cpucluster: a53 diff --git a/boards/nxp/imx8mn_evk/doc/index.rst b/boards/nxp/imx8mn_evk/doc/index.rst new file mode 100644 index 00000000000..3e27bb233ba --- /dev/null +++ b/boards/nxp/imx8mn_evk/doc/index.rst @@ -0,0 +1,131 @@ +.. _imx8mn_evk: + +NXP i.MX8MN EVK (Cortex-A53) +############################ + +Overview +******** + +i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano applications +processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. +Zephyr OS is ported to run on the Cortex®-A53 core. + +- Board features: + + - RAM: 2GB LPDDR4 + - Storage: + + - SanDisk 16GB eMMC5.1 + - Micron 32MB QSPI NOR + - microSD Socket + - Wireless: + + - WiFi: 2.4/5GHz IEEE 802.11b/g/n + - Bluetooth: v4.1 + - USB: + + - OTG - 2x type C + - Ethernet + - PCI-E M.2 + - Connectors: + + - 40-Pin Dual Row Header + - LEDs: + + - 1x Power status LED + - 1x UART LED + - Debug + + - JTAG 20-pin connector + - MicroUSB for UART debug, two COM ports for A53 and M7 + +More information about the board can be found at the +`NXP website`_. + +Supported Features +================== + +The Zephyr mimx8mn_evk board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 8 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART4. + +Programming and Debugging +************************* + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 + +Or kick SMP zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 + + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx8mn_evk/mimx8mn6/a53 + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** + thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mn_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mn_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! + +Use Jailhouse hypervisor, after root cell linux is up: + +.. code-block:: console + + #jailhouse enable imx8mn.cell + #jailhouse cell create imx8mn-zephyr.cell + #jailhouse cell load 1 zephyr.bin -a 0x93c00000 + #jailhouse cell start 1 + +References +========== + +.. _NXP website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-nano-applications-processor:8MNANOD4-EVK + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MNRM diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk-pinctrl.dtsi b/boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi similarity index 100% rename from boards/arm64/mimx8mn_evk/mimx8mn_evk-pinctrl.dtsi rename to boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts new file mode 100644 index 00000000000..2927ff9d1ca --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts @@ -0,0 +1,44 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mn_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MN A53"; + compatible = "fsl,mimx8mn"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + cpu@2 { + status = "disabled"; + }; + }; + + sram0: memory@93c00000 { + reg = <0x93c00000 DT_SIZE_M(1)>; + }; +}; + +&uart4 { + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml new file mode 100644 index 00000000000..b75fb589d21 --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mn_evk/mimx8mn6/a53 +name: NXP i.MX8M Nano EVK A53 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig new file mode 100644 index 00000000000..4e31bf4e946 --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts new file mode 100644 index 00000000000..3dbc8b593ae --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts @@ -0,0 +1,46 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mn_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MN A53"; + compatible = "fsl,mimx8mn"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + sram0: memory@93c00000 { + reg = <0x93c00000 DT_SIZE_M(1)>; + }; +}; + +&uart4 { + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml new file mode 100644 index 00000000000..d82cced07a9 --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml @@ -0,0 +1,21 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mn_evk/mimx8mn6/a53/smp +name: NXP i.MX8M Nano EVK A53 with SMP kernel +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - smp +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig new file mode 100644 index 00000000000..845b48736a7 --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# SMP +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_PM_CPU_OPS=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/arm64/khadas_edgev/CMakeLists.txt b/boards/nxp/imx8mp_evk/CMakeLists.txt similarity index 100% rename from boards/arm64/khadas_edgev/CMakeLists.txt rename to boards/nxp/imx8mp_evk/CMakeLists.txt diff --git a/boards/nxp/imx8mp_evk/Kconfig.defconfig b/boards/nxp/imx8mp_evk/Kconfig.defconfig new file mode 100644 index 00000000000..3fdc7b3cd9c --- /dev/null +++ b/boards/nxp/imx8mp_evk/Kconfig.defconfig @@ -0,0 +1,15 @@ +# MIMX8MP EVK board defconfig + +# Copyright (c) 2021, Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR diff --git a/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk b/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk new file mode 100644 index 00000000000..fbda0ccc10d --- /dev/null +++ b/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk @@ -0,0 +1,8 @@ +# Copyright 2021-2022, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8MP_EVK + select SOC_MIMX8ML8_A53 if BOARD_IMX8MP_EVK_MIMX8ML8_A53 || BOARD_IMX8MP_EVK_MIMX8ML8_A53_SMP + select SOC_MIMX8MP_ADSP if BOARD_IMX8MP_EVK_MIMX8ML8_ADSP + select SOC_MIMX8MP_M7 if BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR + select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/nxp/imx8mp_evk/board.cmake b/boards/nxp/imx8mp_evk/board.cmake new file mode 100644 index 00000000000..55a52a15b19 --- /dev/null +++ b/boards/nxp/imx8mp_evk/board.cmake @@ -0,0 +1,20 @@ +# +# Copyright (c) 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMX8MP_ADSP) + board_set_flasher_ifnset(misc-flasher) + board_finalize_runner_args(misc-flasher) + + board_set_rimage_target(imx8m) +endif() + +if(CONFIG_SOC_MIMX8MP_M7) + board_set_debugger_ifnset(jlink) + board_set_flasher_ifnset(jlink) + + board_runner_args(jlink "--device=MIMX8ML8_M7") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nxp/imx8mp_evk/board.yml b/boards/nxp/imx8mp_evk/board.yml new file mode 100644 index 00000000000..d810c27a596 --- /dev/null +++ b/boards/nxp/imx8mp_evk/board.yml @@ -0,0 +1,10 @@ +board: + name: imx8mp_evk + vendor: nxp + socs: + - name: mimx8ml8 + variants: + - name: smp + cpucluster: a53 + - name: ddr + cpucluster: m7 diff --git a/boards/nxp/imx8mp_evk/doc/index.rst b/boards/nxp/imx8mp_evk/doc/index.rst new file mode 100644 index 00000000000..9952c7c90b5 --- /dev/null +++ b/boards/nxp/imx8mp_evk/doc/index.rst @@ -0,0 +1,229 @@ +.. _imx8mp_evk: + +NXP i.MX8MP EVK +############### + +Overview +******** + +i.MX8M Plus LPDDR4 EVK board is based on NXP i.MX8M Plus applications +processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. +Zephyr OS is ported to run on the Cortex®-A53 core. + +- Board features: + + - RAM: 2GB LPDDR4 + - Storage: + + - SanDisk 16GB eMMC5.1 + - Micron 32MB QSPI NOR + - microSD Socket + - Wireless: + + - WiFi: 2.4/5GHz IEEE 802.11b/g/n + - Bluetooth: v4.1 + - USB: + + - OTG - 2x type C + - Ethernet + - PCI-E M.2 + - Connectors: + + - 40-Pin Dual Row Header + - LEDs: + + - 1x Power status LED + - 1x UART LED + - Debug + + - JTAG 20-pin connector + - MicroUSB for UART debug, two COM ports for A53 and M4 + +More information about the board can be found at the +`NXP website`_. + +Supported Features +================== + +The Zephyr mimx8mp_evk_a53 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +The Zephyr mimx8mp_evk_m7 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 8 MHz. + +The M7 Core is configured to run at a 800 MHz clock speed. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART4. + +Programming and Debugging (A53) +******************************* + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick non-smp zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xc0000000 + +Or kick SMP zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0xc0000000 + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx8mp_evk/mimx8ml8/a53 + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** + thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mp_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mp_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! + +Use Jailhouse hypervisor, after root cell linux is up: + +.. code-block:: console + + #jailhouse enable imx8mp.cell + #jailhouse cell create imx8mp-zephyr.cell + #jailhouse cell load 1 zephyr.bin -a 0xc0000000 + #jailhouse cell start 1 + +Programming and Debugging (M7) +****************************** + +The MIMX8MP EVK board doesn't have QSPI flash for the M7, and it needs +to be started by the A53 core. The A53 core is responsible to load the M7 binary +application into the RAM, put the M7 in reset, set the M7 Program Counter and +Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at +bootloader level or after the Linux system has booted. + +The M7 can use up to 3 different RAMs (currently, only two configurations are +supported: ITCM and DDR). These are the memory mapping for A53 and M7: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Applications Processor Reference Manual`_ (section 2.1 to 2.3) + +At compilation time you have to choose which RAM will be used. This +configuration is done based on board name (imx8mp_evk/mimx8ml8/m7 for ITCM and +imx8mp_evk/mimx8ml8/m7/ddr for DDR). + +Load and run Zephyr on M7 from A53 using u-boot by copying the compiled +``zephyr.bin`` to the first FAT partition of the SD card and plug the SD +card into the board. Power it up and stop the u-boot execution at prompt. + +Load the M7 binary onto the desired memory and start its execution using: + +ITCM +=== + +.. code-block:: console + + fatload mmc 0:1 0x48000000 zephyr.bin + cp.b 0x48000000 0x7e0000 20000 + bootaux 0x7e0000 + +DDR +=== + +.. code-block:: console + + fatload mmc 0:1 0x80000000 zephyr.bin + dcache flush + bootaux 0x80000000 + +Debugging +========= + +MIMX8MP EVK board can be debugged by connecting an external JLink +JTAG debugger to the J24 debug connector and to the PC. Then +the application can be debugged using the usual way. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx8mp_evk/mimx8ml8/m7 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.7.99-1310-g2801bf644a91 *** + Hello World! imx8mp_evk + +References +========== + +.. _NXP website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/docs/en/reference-manual/IMX8MPRM.pdf diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk-pinctrl.dtsi b/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi similarity index 100% rename from boards/arm64/mimx8mp_evk/mimx8mp_evk-pinctrl.dtsi rename to boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts new file mode 100644 index 00000000000..18cff6569d4 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts @@ -0,0 +1,45 @@ +/* + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mp_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MP A53"; + compatible = "fsl,mimx8mp"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + cpu@2 { + status = "disabled"; + }; + }; + + sram0: memory@c0000000 { + reg = <0xc0000000 DT_SIZE_M(1)>; + }; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml new file mode 100644 index 00000000000..f1c632d8298 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mp_evk/mimx8ml8/a53 +name: NXP i.MX8M Plus EVK A53 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig new file mode 100644 index 00000000000..4e31bf4e946 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts new file mode 100644 index 00000000000..0137c60d611 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mp_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MP A53"; + compatible = "fsl,mimx8mp"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + sram0: memory@c0000000 { + reg = <0xc0000000 DT_SIZE_M(1)>; + }; + +}; + +&uart4 { + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.yaml new file mode 100644 index 00000000000..c1b90505235 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.yaml @@ -0,0 +1,21 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mp_evk/mimx8ml8/a53/smp +name: NXP i.MX8M Plus EVK A53 with SMP kernel +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +supported: + - smp +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig new file mode 100644 index 00000000000..845b48736a7 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# SMP +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_PM_CPU_OPS=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.dts new file mode 100644 index 00000000000..dc8c0ab48a5 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.dts @@ -0,0 +1,41 @@ +/* + * Copyright 2021, 2023, 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "NXP i.MX 8MPLUS Audio DSP"; + compatible = "nxp"; + + chosen { + zephyr,sram = &sram0; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&pinctrl { + uart4_default: uart4_default { + group0 { + pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, + <&iomuxc_uart4_txd_uart_tx_uart4_tx>; + bias-pull-up; + slew-rate = "slow"; + drive-strength = "x1"; + }; + }; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.yaml new file mode 100644 index 00000000000..78668aa26f6 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.yaml @@ -0,0 +1,16 @@ +identifier: imx8mp_evk/mimx8ml8/adsp +name: NXP i.MX 8MPLUS Audio DSP +type: mcu +arch: xtensa +toolchain: + - xcc + - xt-clang + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - mcumgr +vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp_defconfig new file mode 100644 index 00000000000..e2c64fa2e0d --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp_defconfig @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: Apache-2.0 + +# size of stack for initialization and main thread +CONFIG_MAIN_STACK_SIZE=3072 + +# enable logger +CONFIG_LOG=y + +# no need for a "raw" binary zephyr/zephyr.bin in the build directory +CONFIG_BUILD_OUTPUT_BIN=n + +# enable uart driver +CONFIG_SERIAL=y + +# clock configuration +CONFIG_CLOCK_CONTROL=y + +# console (remote proc console by default) +CONFIG_CONSOLE=y + +# uart console (overrides remote proc console) +CONFIG_UART_CONSOLE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts new file mode 100644 index 00000000000..2b05cab20ce --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021, Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mp_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8M Plus EVK board"; + compatible = "nxp,mimx8mp_evk"; + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; + +&gpio3 { + status = "okay"; +}; + +&mailbox0 { + status = "okay"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml new file mode 100644 index 00000000000..6ab73e3386a --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2021, Laird Connectivity +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mp_evk/mimx8ml8/m7 +name: NXP i.MX8M Plus EVK +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - uart +vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts new file mode 100644 index 00000000000..ba805ef7cbf --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021, Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mp_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8M Plus EVK board"; + compatible = "nxp,mimx8mp_evk"; + + chosen { + /* DDR */ + zephyr,flash = &ddr_code; + zephyr,sram = &ddr_sys; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; + +&gpio3 { + status = "okay"; +}; + +&mailbox0 { + status = "okay"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml new file mode 100644 index 00000000000..e5ed32a1d38 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2021, Laird Connectivity +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mp_evk/mimx8ml8/m7/ddr +name: NXP i.MX8M Plus EVK (DDR) +type: mcu +arch: arm +ram: 2048 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - uart +vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig new file mode 100644 index 00000000000..17542cb4eec --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2021, Laird Connectivity +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_CODE_DDR=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig new file mode 100644 index 00000000000..0f7d91f447e --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2021, Laird Connectivity +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_CODE_ITCM=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mq_evk/Kconfig.defconfig b/boards/nxp/imx8mq_evk/Kconfig.defconfig new file mode 100644 index 00000000000..054cfde7fb7 --- /dev/null +++ b/boards/nxp/imx8mq_evk/Kconfig.defconfig @@ -0,0 +1,16 @@ +# MIMX8MQ EVK board defconfig + +# Copyright (c) 2021, Kwon Tae-young +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IMX8MQ_EVK + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_IMX8MQ_EVK diff --git a/boards/nxp/imx8mq_evk/Kconfig.imx8mq_evk b/boards/nxp/imx8mq_evk/Kconfig.imx8mq_evk new file mode 100644 index 00000000000..c34dcaa7695 --- /dev/null +++ b/boards/nxp/imx8mq_evk/Kconfig.imx8mq_evk @@ -0,0 +1,9 @@ +# MIMX8MQ EVK board + +# Copyright (c) 2021, Kwon Tae-young +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8MQ_EVK + select SOC_PART_NUMBER_MIMX8MQ6DVAJZ + select SOC_MIMX8MQ6_M4 if BOARD_IMX8MQ_EVK_MIMX8MQ6_M4 diff --git a/boards/arm/mimx8mq_evk/board.cmake b/boards/nxp/imx8mq_evk/board.cmake similarity index 100% rename from boards/arm/mimx8mq_evk/board.cmake rename to boards/nxp/imx8mq_evk/board.cmake diff --git a/boards/nxp/imx8mq_evk/board.yml b/boards/nxp/imx8mq_evk/board.yml new file mode 100644 index 00000000000..c599f0a7afd --- /dev/null +++ b/boards/nxp/imx8mq_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: imx8mq_evk + vendor: nxp + socs: + - name: mimx8mq6 diff --git a/boards/arm/mimx8mq_evk/doc/img/mimx8mq_evk.jpg b/boards/nxp/imx8mq_evk/doc/img/mimx8mq_evk.jpg similarity index 100% rename from boards/arm/mimx8mq_evk/doc/img/mimx8mq_evk.jpg rename to boards/nxp/imx8mq_evk/doc/img/mimx8mq_evk.jpg diff --git a/boards/nxp/imx8mq_evk/doc/index.rst b/boards/nxp/imx8mq_evk/doc/index.rst new file mode 100644 index 00000000000..40bd5ac5c50 --- /dev/null +++ b/boards/nxp/imx8mq_evk/doc/index.rst @@ -0,0 +1,215 @@ +.. _mimx8mq_evk: + +NXP MIMX8MQ EVK +############### + +Overview +******** + +i.MX8MQ EVK board is based on NXP i.MX8MQ applications +processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. +Zephyr OS is ported to run on the Cortex®-M4 core. + +- Board features: + + - RAM: 3GB LPDDR4 + - Storage: + + - 16GB eMMC5.0 + - 32MB QSPI NOR + - microSD Socket + - Wireless: + + - WiFi: 2.4/5GHz IEEE 802.11 a/b/g/n/ac + - Bluetooth: v4.1 + - USB: + + - OTG - 1x type C + - HOST - 1x type A + - Ethernet + - PCI-E M.2 + - LEDs: + + - 1x Power status LED + - 1x UART LED + - Debug + + - JTAG 10-pin connector + - MicroUSB for UART debug, two COM ports for A53 and M4 + +.. image:: img/mimx8mq_evk.jpg + :align: center + :alt: MIMX8MQ EVK + +More information about the board can be found at the +`NXP website`_. + +Supported Features +================== + +The Zephyr mimx8mq_evk board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig`. + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +MIMX8MQ EVK board was tested with the following pinmux controller +configuration. + ++---------------+-----------------+---------------------------+ +| Board Name | SoC Name | Usage | ++===============+=================+===========================+ +| UART2 RXD | UART2_TXD | UART Console | ++---------------+-----------------+---------------------------+ +| UART2 TXD | UART2_RXD | UART Console | ++---------------+-----------------+---------------------------+ + +System Clock +============ + +The M4 Core is configured to run at a 266 MHz clock speed. + +Serial Port +=========== + +The i.MX8MQ SoC has four UARTs. UART_2 is configured for the console and +the remaining are not used/tested. + +Programming and Debugging +************************* + +The MIMX8MQ EVK board doesn't have QSPI flash for the M4 and it needs +to be started by the A53 core. The A53 core is responsible to load the M4 binary +application into the RAM, put the M4 in reset, set the M4 Program Counter and +Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at +bootloader level or after the Linux system has booted. + +The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file :zephyr_file:`boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts` +with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. +The available configurations are: + +.. code-block:: none + + "zephyr,flash" + - &tcml_code + - &ocram_code + - &ocram_s_code + + "zephyr,sram" + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + +Load and run Zephyr on M4 from A53 using u-boot. + +.. tabs:: + + .. group-tab:: From an SD card + Copy the compiled ``zephyr.bin`` to the first FAT partition of the + SD card and plug the SD card into the board. Power it up and stop the u-boot + execution at prompt. + + Load the M4 binary onto the desired memory and start its execution using: + + .. code-block:: console + + fatload mmc 0:1 0x40480000 zephyr.bin + cp.b 0x40480000 0x7e0000 0x8000 + bootaux 0x7e0000 + + .. group-tab:: From serial + This procedure requires ``screen`` and ``lrzsz`` to be installed. + + Start ``screen``, power up the board, and stop the u-boot execution at prompt: + + .. code-block:: console + + screen 115200 + + Start ``loadx`` with offset ``7e0000``: + + .. code-block:: console + + loadx 7e0000 115200 + + Send the compiled ``zephyr.bin`` with ``sx`` by pressing :kbd:`Ctrl-a` followed by :kbd:`:` + and write: + + .. code-block:: console + + exec !! sx + + Start execution: + + .. code-block:: console + + bootaux 0x7e0000 + +Debugging +========= + +MIMX8MQ EVK board can be debugged by connecting an external JLink +JTAG debugger to the J401 debug connector and to the PC. Then +the application can be debugged using the usual way. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx8mq_evk/mimx8mq6/m4 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build zephyr-v2.6.99-30942-g6ee70bd22058 ***** + Hello World! imx8mq_evk + +References +========== + +.. _NXP website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-applications-processor:MCIMX8M-EVK + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM diff --git a/boards/arm/mimx8mq_evk/mimx8mq_evk-pinctrl.dtsi b/boards/nxp/imx8mq_evk/imx8mq_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimx8mq_evk/mimx8mq_evk-pinctrl.dtsi rename to boards/nxp/imx8mq_evk/imx8mq_evk-pinctrl.dtsi diff --git a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts new file mode 100644 index 00000000000..7809ce505f7 --- /dev/null +++ b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021, Kwon Tae-young + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mq_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MQ EVK board"; + compatible = "nxp,mimx8mq_evk"; + + aliases { + uart-2 = &uart2; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + }; +}; + +&uart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml new file mode 100644 index 00000000000..acb8e15d8a5 --- /dev/null +++ b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2021, Kwon Tae-young +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mq_evk/mimx8mq6/m4 +name: NXP i.MX8MQ EVK CM4 +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig new file mode 100644 index 00000000000..e169a060eab --- /dev/null +++ b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2021, Kwon Tae-young +# Copyright 2024 +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek b/boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek new file mode 100644 index 00000000000..f70580b800c --- /dev/null +++ b/boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek @@ -0,0 +1,8 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8QM_MEK + select SOC_MIMX8QM_ADSP if BOARD_IMX8QM_MEK_MIMX8QM6_ADSP + select SOC_PART_NUMBER_MIMX8QM6AVUFF diff --git a/boards/nxp/imx8qm_mek/board.cmake b/boards/nxp/imx8qm_mek/board.cmake new file mode 100644 index 00000000000..0924bf99eec --- /dev/null +++ b/boards/nxp/imx8qm_mek/board.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMX8QM_ADSP) + board_set_flasher_ifnset(misc-flasher) + board_finalize_runner_args(misc-flasher) + + board_set_rimage_target(imx) +endif() diff --git a/boards/nxp/imx8qm_mek/board.yml b/boards/nxp/imx8qm_mek/board.yml new file mode 100644 index 00000000000..d044277a622 --- /dev/null +++ b/boards/nxp/imx8qm_mek/board.yml @@ -0,0 +1,5 @@ +board: + name: imx8qm_mek + vendor: nxp + socs: + - name: mimx8qm6 diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8-pinctrl.dtsi b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi similarity index 100% rename from boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8-pinctrl.dtsi rename to boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts new file mode 100644 index 00000000000..325e293851f --- /dev/null +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021, 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi" + +/ { + model = "NXP i.MX 8QM Audio DSP"; + compatible = "nxp"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + }; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.yaml b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.yaml new file mode 100644 index 00000000000..c2a70b2652d --- /dev/null +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.yaml @@ -0,0 +1,11 @@ +identifier: imx8qm_mek/mimx8qm6/adsp +name: NXP i.MX 8QM Audio DSP +type: mcu +arch: xtensa +toolchain: + - zephyr +testing: + only_tags: + - kernel + - sof +vendor: nxp diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig new file mode 100644 index 00000000000..325b05b84e9 --- /dev/null +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=3072 + +# board/soc-related configurations +CONFIG_LOG=y + +# TODO: maybe move this to SOF? +CONFIG_DYNAMIC_INTERRUPTS=y +CONFIG_BUILD_OUTPUT_BIN=n + +# clock-related configurations +CONFIG_CLOCK_CONTROL=y + +# serial-related configurations +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek b/boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek new file mode 100644 index 00000000000..fbd35d46b2f --- /dev/null +++ b/boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek @@ -0,0 +1,8 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8QXP_MEK + select SOC_MIMX8QXP_ADSP if BOARD_IMX8QXP_MEK_MIMX8QX6_ADSP + select SOC_PART_NUMBER_MIMX8QX6AVLFZ diff --git a/boards/nxp/imx8qxp_mek/board.cmake b/boards/nxp/imx8qxp_mek/board.cmake new file mode 100644 index 00000000000..699964c5e39 --- /dev/null +++ b/boards/nxp/imx8qxp_mek/board.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMX8QXP_ADSP) + board_set_flasher_ifnset(misc-flasher) + board_finalize_runner_args(misc-flasher) + + board_set_rimage_target(imx) +endif() diff --git a/boards/nxp/imx8qxp_mek/board.yml b/boards/nxp/imx8qxp_mek/board.yml new file mode 100644 index 00000000000..e31754086d7 --- /dev/null +++ b/boards/nxp/imx8qxp_mek/board.yml @@ -0,0 +1,5 @@ +board: + name: imx8qxp_mek + vendor: nxp + socs: + - name: mimx8qx6 diff --git a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x-pinctrl.dtsi b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi similarity index 100% rename from boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x-pinctrl.dtsi rename to boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts new file mode 100644 index 00000000000..24a9ee09d9e --- /dev/null +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021, 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi" + +/ { + model = "NXP i.MX 8QXP Audio DSP"; + compatible = "nxp"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + }; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.yaml b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.yaml new file mode 100644 index 00000000000..4f168ada93e --- /dev/null +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.yaml @@ -0,0 +1,11 @@ +identifier: imx8qxp_mek/mimx8qx6/adsp +name: NXP i.MX 8QXP Audio DSP +type: mcu +arch: xtensa +toolchain: + - zephyr +testing: + only_tags: + - kernel + - sof +vendor: nxp diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig new file mode 100644 index 00000000000..325b05b84e9 --- /dev/null +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=3072 + +# board/soc-related configurations +CONFIG_LOG=y + +# TODO: maybe move this to SOF? +CONFIG_DYNAMIC_INTERRUPTS=y +CONFIG_BUILD_OUTPUT_BIN=n + +# clock-related configurations +CONFIG_CLOCK_CONTROL=y + +# serial-related configurations +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk b/boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk new file mode 100644 index 00000000000..dbf611081ab --- /dev/null +++ b/boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk @@ -0,0 +1,7 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8ULP_EVK + select SOC_MIMX8ULP_ADSP if BOARD_IMX8ULP_EVK_IMX8ULP_ADSP diff --git a/boards/nxp/imx8ulp_evk/board.cmake b/boards/nxp/imx8ulp_evk/board.cmake new file mode 100644 index 00000000000..97e0a80ba04 --- /dev/null +++ b/boards/nxp/imx8ulp_evk/board.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMX8ULP_ADSP) + board_set_flasher_ifnset(misc-flasher) + board_finalize_runner_args(misc-flasher) + + board_set_rimage_target(imx8ulp) +endif() diff --git a/boards/nxp/imx8ulp_evk/board.yml b/boards/nxp/imx8ulp_evk/board.yml new file mode 100644 index 00000000000..b401615d7d7 --- /dev/null +++ b/boards/nxp/imx8ulp_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: imx8ulp_evk + vendor: nxp + socs: + - name: imx8ulp diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.dts b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.dts new file mode 100644 index 00000000000..49ad098fb24 --- /dev/null +++ b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.dts @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2023-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "NXP i.MX 8ULP Audio DSP"; + compatible = "nxp"; + + chosen { + zephyr,sram = &sram0; + }; +}; diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.yaml b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.yaml new file mode 100644 index 00000000000..437d112ee58 --- /dev/null +++ b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.yaml @@ -0,0 +1,10 @@ +identifier: imx8ulp_evk/imx8ulp/adsp +name: NXP i.MX 8ULP Audio DSP +type: mcu +arch: xtensa +toolchain: + - zephyr +testing: + only_tags: + - kernel + - sof diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp_defconfig b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp_defconfig new file mode 100644 index 00000000000..e8d594b3070 --- /dev/null +++ b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DYNAMIC_INTERRUPTS=y + +CONFIG_LOG=y diff --git a/boards/arm64/mimx8mp_evk/CMakeLists.txt b/boards/nxp/imx93_evk/CMakeLists.txt similarity index 100% rename from boards/arm64/mimx8mp_evk/CMakeLists.txt rename to boards/nxp/imx93_evk/CMakeLists.txt diff --git a/boards/nxp/imx93_evk/Kconfig.imx93_evk b/boards/nxp/imx93_evk/Kconfig.imx93_evk new file mode 100644 index 00000000000..e3121418393 --- /dev/null +++ b/boards/nxp/imx93_evk/Kconfig.imx93_evk @@ -0,0 +1,6 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX93_EVK_MIMX9352_A55 + select SOC_MIMX9352_A55 + select SOC_PART_NUMBER_MIMX9352CVUXK diff --git a/boards/arm64/mimx8mn_evk/board.cmake b/boards/nxp/imx93_evk/board.cmake similarity index 100% rename from boards/arm64/mimx8mn_evk/board.cmake rename to boards/nxp/imx93_evk/board.cmake diff --git a/boards/nxp/imx93_evk/board.yml b/boards/nxp/imx93_evk/board.yml new file mode 100644 index 00000000000..110334be558 --- /dev/null +++ b/boards/nxp/imx93_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: imx93_evk + vendor: nxp + socs: + - name: mimx9352 diff --git a/boards/nxp/imx93_evk/doc/index.rst b/boards/nxp/imx93_evk/doc/index.rst new file mode 100644 index 00000000000..0fdeb237ec2 --- /dev/null +++ b/boards/nxp/imx93_evk/doc/index.rst @@ -0,0 +1,215 @@ +.. _imx93_evk: + +NXP i.MX93 EVK (Cortex-A55) +############################ + +Overview +******** + +The i.MX93 Evaluation Kit (MCIMX93-EVK board) is a platform designed to show +the most commonly used features of the i.MX 93 Applications Processor in a +small and low cost package. The MCIMX93-EVK board is an entry-level development +board, which helps developers to get familiar with the processor before +investing a large amount of resources in more specific designs. + +i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single +Cortex®-M33 core. Zephyr OS is ported to run on one of the Cortex®-A55 core. + +- Board features: + + - RAM: 2GB LPDDR4 + - Storage: + + - SanDisk 16GB eMMC5.1 + - microSD Socket + - Wireless: + + - Murata Type-2EL (SDIO+UART+SPI) module. It is based on NXP IW612 SoC, + which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.2, + and 802.15.4 + - USB: + + - Two USB 2.0 Type C connectors + - Ethernet + - PCI-E M.2 + - Connectors: + + - 40-Pin Dual Row Header + - LEDs: + + - 1x Power status LED + - 2x UART LED + - Debug + + - JTAG 20-pin connector + - MicroUSB for UART debug, two COM ports for A55 and M33 + + +Supported Features +================== + +The Zephyr mimx93_evk board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v4 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz. +Cortex-A55 Core runs up to 1.7 GHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART4. + +Programming and Debugging +************************* + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 1 release 0xd0000000 + + +Or use the following command to kick zephyr.bin to Cortex-A55 Core0: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0000000 + + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: mimx93_evk/mimx9352/a55 + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.2.0-8-g1613870534a0 *** + thread_a: Hello World from cpu 0 on mimx93_evk_a55! + thread_b: Hello World from cpu 0 on mimx93_evk_a55! + thread_a: Hello World from cpu 0 on mimx93_evk_a55! + thread_b: Hello World from cpu 0 on mimx93_evk_a55! + +References +========== + +More information can refer to NXP official website: +`NXP website`_. + +.. _NXP website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-93-applications-processor-family-arm-cortex-a55-ml-acceleration-power-efficient-mpu:i.MX93 + + +Using the SOF-specific variant +****************************** + +Purpose +======= + +Since this board doesn't have a DSP, an alternative for people who might be interested +in running SOF on this board had to be found. The alternative consists of running SOF +on an A55 core using Jailhouse as a way to "take away" one A55 core from Linux and +assign it to Zephyr with `SOF`_. + +.. _SOF: + https://github.com/thesofproject/sof + +What is Jailhouse? +================== + +Jailhouse is a light-weight hypervisor that allows the partitioning of hardware resources. +For more details on how this is done and, generally, about Jailhouse, please see: `1`_, +`2`_ and `3`_. The GitHub repo can be found `here`_. + +.. _1: + https://lwn.net/Articles/578295/ + +.. _2: + https://lwn.net/Articles/578852/ + +.. _3: + http://events17.linuxfoundation.org/sites/events/files/slides/ELCE2016-Jailhouse-Tutorial.pdf + +.. _here: + https://github.com/siemens/jailhouse + + +How does it work? +================= +Firstly, we need to explain a few Jailhouse concepts that will be referred to later on: + +* **Cell**: refers to a set of hardware resources that the OS assigned to this + cell can utilize. + +* **Root cell**: refers to the cell in which Linux is running. This is the main cell which + will contain all the hardware resources that Linux will utilize and will be used to assign + resources to the inmates. The inmates CANNOT use resources such as the CPU that haven't been + assigned to the root cell. + +* **Inmate**: refers to any other OS that runs alongside Linux. The resources an inmate will + use are taken from the root cell (the cell Linux is running in). + +SOF+Zephyr will run as an inmate, alongside Linux, on core 1 of the board. This means that +said core will be taken away from Linux and will only be utilized by Zephyr. + +The hypervisor restricts inmate's/root's access to certain hardware resources using +the second-stage translation table which is based on the memory regions described in the +configuration files. Please consider the following scenario: + + Root cell wants to use the **UART** which let's say has its registers mapped in + the **[0x0 - 0x42000000]** region. If the inmate wants to use the same **UART** for + some reason then we'd need to also add this region to inmate's configuration + file and add the **JAILHOUSE_MEM_ROOTSHARED** flag. This flag means that the inmate + is allowed to share this region with the root. If this region is not set in + the inmate's configuration file and Zephyr (running as an inmate here) tries + to access this region this will result in a second stage translation fault. + +Notes: + +* Linux and Zephyr are not aware that they are running alongside each other. + They will only be aware of the cores they have been assigned through the config + files (there's a config file for the root and one for each inmate). + +Architecture overview +===================== + +The architecture overview can be found at this `location`_. (latest status update as of now +and the only one containing diagrams). + +.. _location: + https://github.com/thesofproject/sof/issues/7192 + + +How to use this board? +====================== + +This board has been designed for SOF so it's only intended to be used with SOF. + +TODO: document the SOF build process for this board. For now, the support for +i.MX93 is still in review and has yet to merged on SOF side. diff --git a/boards/arm64/mimx93_evk/mimx93_evk-pinctrl.dtsi b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi similarity index 100% rename from boards/arm64/mimx93_evk/mimx93_evk-pinctrl.dtsi rename to boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts new file mode 100644 index 00000000000..a519801e875 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts @@ -0,0 +1,120 @@ +/* + * Copyright 2022,2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx93_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX93 A55"; + compatible = "fsl,mimx93"; + + chosen { + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + }; + + sram0: memory@d0000000 { + reg = <0xd0000000 DT_SIZE_M(1)>; + }; + + aliases { + led0 = &led_r; + sw0 = &btn_1; + }; + + leds { + compatible = "gpio-leds"; + led_r: led_r { + label = "LED_R"; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; + led_g: led_g { + label = "LED_G"; + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + }; + led_b: led_b { + label = "LED_B"; + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + btn_1: btn_1{ + label = "BTN1"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + }; + + btn_2: btn_2{ + label = "BTN2"; + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&lpuart1 { + status = "disabled"; + current-speed = <115200>; + /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + + +&lpi2c1{ + status = "disabled"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&lpi2c2{ + status = "disabled"; + clock-frequency = ; + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; +}; + +&lpspi3 { + status = "disabled"; + clock-frequency = <1000000>; + pinctrl-0 = <&spi3_default>; + pinctrl-names = "default"; +}; + +&gpio1{ + status = "okay"; +}; + +&gpio2{ + status = "okay"; +}; + +&gpio3{ + status = "okay"; +}; + +&gpio4{ + status = "okay"; +}; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml new file mode 100644 index 00000000000..3a045828f84 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml @@ -0,0 +1,24 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx93_evk/mimx9352/a55 +name: NXP i.MX93 Plus EVK A55 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - gpio + - uart + - i2c + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig new file mode 100644 index 00000000000..6b4743c4643 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig @@ -0,0 +1,31 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +CONFIG_MAX_XLAT_TABLES=64 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/index.rst b/boards/nxp/index.rst new file mode 100644 index 00000000000..4ccb239797b --- /dev/null +++ b/boards/nxp/index.rst @@ -0,0 +1,10 @@ +.. _boards-nxp: + +NXP Semiconductors +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/lpcxpresso11u68/CMakeLists.txt b/boards/nxp/lpcxpresso11u68/CMakeLists.txt similarity index 100% rename from boards/arm/lpcxpresso11u68/CMakeLists.txt rename to boards/nxp/lpcxpresso11u68/CMakeLists.txt diff --git a/boards/nxp/lpcxpresso11u68/Kconfig.lpcxpresso11u68 b/boards/nxp/lpcxpresso11u68/Kconfig.lpcxpresso11u68 new file mode 100644 index 00000000000..37bf6133254 --- /dev/null +++ b/boards/nxp/lpcxpresso11u68/Kconfig.lpcxpresso11u68 @@ -0,0 +1,8 @@ +# Copyright (c) 2020, Seagate +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO11U68 + select SOC_LPC11U68 + select SOC_PART_NUMBER_LPC11U68JBD100 diff --git a/boards/arm/lpcxpresso11u68/board.cmake b/boards/nxp/lpcxpresso11u68/board.cmake similarity index 100% rename from boards/arm/lpcxpresso11u68/board.cmake rename to boards/nxp/lpcxpresso11u68/board.cmake diff --git a/boards/nxp/lpcxpresso11u68/board.yml b/boards/nxp/lpcxpresso11u68/board.yml new file mode 100644 index 00000000000..30712d42e69 --- /dev/null +++ b/boards/nxp/lpcxpresso11u68/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso11u68 + vendor: nxp + socs: + - name: lpc11u68 diff --git a/boards/arm/lpcxpresso11u68/doc/index.rst b/boards/nxp/lpcxpresso11u68/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso11u68/doc/index.rst rename to boards/nxp/lpcxpresso11u68/doc/index.rst diff --git a/boards/arm/lpcxpresso11u68/doc/lpcxpresso11u68.jpg b/boards/nxp/lpcxpresso11u68/doc/lpcxpresso11u68.jpg similarity index 100% rename from boards/arm/lpcxpresso11u68/doc/lpcxpresso11u68.jpg rename to boards/nxp/lpcxpresso11u68/doc/lpcxpresso11u68.jpg diff --git a/boards/arm/lpcxpresso11u68/lpcxpresso11u68-pinctrl.dtsi b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso11u68/lpcxpresso11u68-pinctrl.dtsi rename to boards/nxp/lpcxpresso11u68/lpcxpresso11u68-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso11u68/lpcxpresso11u68.dts b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts similarity index 100% rename from boards/arm/lpcxpresso11u68/lpcxpresso11u68.dts rename to boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts diff --git a/boards/arm/lpcxpresso11u68/lpcxpresso11u68.yaml b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.yaml similarity index 100% rename from boards/arm/lpcxpresso11u68/lpcxpresso11u68.yaml rename to boards/nxp/lpcxpresso11u68/lpcxpresso11u68.yaml diff --git a/boards/arm/lpcxpresso11u68/lpcxpresso11u68_defconfig b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68_defconfig similarity index 94% rename from boards/arm/lpcxpresso11u68/lpcxpresso11u68_defconfig rename to boards/nxp/lpcxpresso11u68/lpcxpresso11u68_defconfig index 45ee27f2f72..523128641ea 100644 --- a/boards/arm/lpcxpresso11u68/lpcxpresso11u68_defconfig +++ b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68_defconfig @@ -2,7 +2,6 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 CONFIG_GPIO=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SOC_SERIES_LPC11U6X=y # Since the board has little memory (32k), stack sizes are lowered # so that the application has more RAM for itself. CONFIG_MAIN_STACK_SIZE=512 diff --git a/boards/arm/faze/pre_dt_board.cmake b/boards/nxp/lpcxpresso11u68/pre_dt_board.cmake similarity index 100% rename from boards/arm/faze/pre_dt_board.cmake rename to boards/nxp/lpcxpresso11u68/pre_dt_board.cmake diff --git a/boards/arm/lpcxpresso11u68/support/openocd.cfg b/boards/nxp/lpcxpresso11u68/support/openocd.cfg similarity index 100% rename from boards/arm/lpcxpresso11u68/support/openocd.cfg rename to boards/nxp/lpcxpresso11u68/support/openocd.cfg diff --git a/boards/nxp/lpcxpresso51u68/Kconfig.lpcxpresso51u68 b/boards/nxp/lpcxpresso51u68/Kconfig.lpcxpresso51u68 new file mode 100644 index 00000000000..ff4e5e1d362 --- /dev/null +++ b/boards/nxp/lpcxpresso51u68/Kconfig.lpcxpresso51u68 @@ -0,0 +1,8 @@ +# Copyright (c) 2021 metraTec GmbH +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO51U68 + select SOC_LPC51U68 + select SOC_PART_NUMBER_LPC51U68JBD64 diff --git a/boards/arm/lpcxpresso51u68/board.cmake b/boards/nxp/lpcxpresso51u68/board.cmake similarity index 100% rename from boards/arm/lpcxpresso51u68/board.cmake rename to boards/nxp/lpcxpresso51u68/board.cmake diff --git a/boards/nxp/lpcxpresso51u68/board.yml b/boards/nxp/lpcxpresso51u68/board.yml new file mode 100644 index 00000000000..7eb0f17095e --- /dev/null +++ b/boards/nxp/lpcxpresso51u68/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso51u68 + vendor: nxp + socs: + - name: lpc51u68 diff --git a/boards/arm/lpcxpresso51u68/doc/index.rst b/boards/nxp/lpcxpresso51u68/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso51u68/doc/index.rst rename to boards/nxp/lpcxpresso51u68/doc/index.rst diff --git a/boards/arm/lpcxpresso51u68/doc/lpcxpresso51u68.jpg b/boards/nxp/lpcxpresso51u68/doc/lpcxpresso51u68.jpg similarity index 100% rename from boards/arm/lpcxpresso51u68/doc/lpcxpresso51u68.jpg rename to boards/nxp/lpcxpresso51u68/doc/lpcxpresso51u68.jpg diff --git a/boards/arm/lpcxpresso51u68/lpcxpresso51u68-pinctrl.dtsi b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso51u68/lpcxpresso51u68-pinctrl.dtsi rename to boards/nxp/lpcxpresso51u68/lpcxpresso51u68-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso51u68/lpcxpresso51u68.dts b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.dts similarity index 100% rename from boards/arm/lpcxpresso51u68/lpcxpresso51u68.dts rename to boards/nxp/lpcxpresso51u68/lpcxpresso51u68.dts diff --git a/boards/arm/lpcxpresso51u68/lpcxpresso51u68.yaml b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.yaml similarity index 100% rename from boards/arm/lpcxpresso51u68/lpcxpresso51u68.yaml rename to boards/nxp/lpcxpresso51u68/lpcxpresso51u68.yaml diff --git a/boards/nxp/lpcxpresso51u68/lpcxpresso51u68_defconfig b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68_defconfig new file mode 100644 index 00000000000..9cc3359a890 --- /dev/null +++ b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68_defconfig @@ -0,0 +1,6 @@ +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000 diff --git a/boards/arm/lpcxpresso51u68/pre_dt_board.cmake b/boards/nxp/lpcxpresso51u68/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso51u68/pre_dt_board.cmake rename to boards/nxp/lpcxpresso51u68/pre_dt_board.cmake diff --git a/boards/nxp/lpcxpresso54114/Kconfig.defconfig b/boards/nxp/lpcxpresso54114/Kconfig.defconfig new file mode 100644 index 00000000000..a7f124a048e --- /dev/null +++ b/boards/nxp/lpcxpresso54114/Kconfig.defconfig @@ -0,0 +1,15 @@ +# LPCXpresso54114 board +# +# Copyright (c) 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +# Place size restrictions on first image if dual core is enabled +if SECOND_CORE_MCUX && BOARD_LPCXPRESSO54114_LPC54114_M4 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # SECOND_CORE_MCUX && BOARD_LPCXPRESSO54114_LPC54114_M4 diff --git a/boards/nxp/lpcxpresso54114/Kconfig.lpcxpresso54114 b/boards/nxp/lpcxpresso54114/Kconfig.lpcxpresso54114 new file mode 100644 index 00000000000..8442760ccda --- /dev/null +++ b/boards/nxp/lpcxpresso54114/Kconfig.lpcxpresso54114 @@ -0,0 +1,9 @@ +# LPCXpresso54114 board + +# Copyright 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO54114 + select SOC_LPC54114_M4 if BOARD_LPCXPRESSO54114_LPC54114_M4 + select SOC_LPC54114_M0 if BOARD_LPCXPRESSO54114_LPC54114_M0 + select SOC_PART_NUMBER_LPC54114J256BD64 diff --git a/boards/nxp/lpcxpresso54114/board.cmake b/boards/nxp/lpcxpresso54114/board.cmake new file mode 100644 index 00000000000..0a88f68d928 --- /dev/null +++ b/boards/nxp/lpcxpresso54114/board.cmake @@ -0,0 +1,13 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(BOARD_LPCXPRESSO54114_LPC54114_M4 OR CONFIG_SECOND_CORE_MCUX) + board_runner_args(jlink "--device=LPC54114J256_M4" "--reset-after-load") +elseif(BOARD_LPCXPRESSO54114_LPC54114_M0) + board_runner_args(jlink "--device=LPC54114J256_M0" "--reset-after-load") +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/lpcxpresso54114/board.yml b/boards/nxp/lpcxpresso54114/board.yml new file mode 100644 index 00000000000..64477bf2ac8 --- /dev/null +++ b/boards/nxp/lpcxpresso54114/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso54114 + vendor: nxp + socs: + - name: lpc54114 diff --git a/boards/nxp/lpcxpresso54114/doc/index.rst b/boards/nxp/lpcxpresso54114/doc/index.rst new file mode 100644 index 00000000000..644de94e415 --- /dev/null +++ b/boards/nxp/lpcxpresso54114/doc/index.rst @@ -0,0 +1,218 @@ +.. _lpcxpresso54114: + +NXP LPCXPRESSO54114 +################### + +Overview +******** + +The LPCXpresso54114 board has been developed by NXP to enable evaluation of and +prototyping with the low-power LPC54110 family of MCUs. LPCXpresso* is a +low-cost development platform available from NXP supporting NXP's ARM-based +microcontrollers. LPCXpresso is an end-to-end solution enabling embedded +engineers to develop their applications from initial evaluation to final +production. + +.. image:: lpcxpresso54114_m4.jpg + :align: center + :alt: LPCXPRESSO54114 + +Hardware +******** + +- LPC54114 dual-core (M4F and dual M0) MCU running at up to 100 MHz +- On-board high-speed USB based debug probe with CMSIS-DAP and J-Link protocol + support, can debug the on-board LPC54114 or an external target +- External debug probe option +- Tri-color LED, target Reset, ISP & interrupt/user buttons for easy testing of + software functionality +- Expansion options based on Arduino UNO and Pmod™, plus additional expansion + port pins +- On-board 1.8 V and 3.3 V regulators plus external power supply option +- 8 Mb Macronix MX25R SPI flash +- Built-in MCU power consumption and supply voltage measurement +- UART, I²C and SPI port bridging from LPC54114 target to USB via the on-board + debug probe +- FTDI UART connector + +For more information about the LPC54114 SoC and LPCXPRESSO54114 board: + +- `LPC54114 SoC Website`_ +- `LPC54114 Datasheet`_ +- `LPC54114 Reference Manual`_ +- `LPCXPRESSO54114 Website`_ +- `LPCXPRESSO54114 User Guide`_ +- `LPCXPRESSO54114 Schematics`_ + +Supported Features +================== + +The lpcxpresso54114 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| IOCON | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port-polling | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| IAP | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration for each core can be found in the defconfig files: + + `boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig` + `boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The LPC54114 SoC has IOCON registers, which can be used to configure the +functionality of a pin. + ++---------+-----------------+----------------------------+ +| Name | Function | Usage | ++=========+=================+============================+ +| PIO0_0 | USART | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_1 | USART | USART TX | ++---------+-----------------+----------------------------+ +| PIO0_18 | SPI | SPI MISO | ++---------+-----------------+----------------------------+ +| PIO0_19 | SPI | SPI SCK | ++---------+-----------------+----------------------------+ +| PIO0_20 | SPI | SPI MOSI | ++---------+-----------------+----------------------------+ +| PIO0_25 | I2C | I2C SCL | ++---------+-----------------+----------------------------+ +| PIO0_26 | I2C | I2C SDA | ++---------+-----------------+----------------------------+ +| PIO0_29 | GPIO | RED LED | ++---------+-----------------+----------------------------+ +| PIO1_1 | SPI | SPI SSEL2 | ++---------+-----------------+----------------------------+ +| PIO1_9 | GPIO | BLUE_LED | ++---------+-----------------+----------------------------+ +| PIO1_10 | GPIO | GREEN LED | ++---------+-----------------+----------------------------+ + +System Clock +============ + +The LPC54114 SoC is configured to use the internal FRO at 48MHz as a source for +the system clock. Other sources for the system clock are provided in the SOC, +depending on your system requirements. + +Serial Port +=========== + +The LPC54114 SoC has 8 FLEXCOMM interfaces for serial communication. One is +configured as USART for the console and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe, +however the :ref:`pyocd-debug-host-tools` do not support this probe so you must +reconfigure the board for one of the following debug probes instead. + +:ref:`lpclink2-jlink-onboard-debug-probe` +----------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program +the J-Link firmware. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the LPC-Link2 +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J5 + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: lpcxpresso54114/lpc54114/m4 + :goals: flash + +Open a serial terminal, reset the board (press the SW4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! lpcxpresso54114_m4 + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: lpcxpresso54114/lpc54114/m4 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! lpcxpresso54114_m4 + +.. _LPC54114 SoC Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc54000-series-cortex-m4-mcus/low-power-microcontrollers-mcus-based-on-arm-cortex-m4-cores-with-optional-cortex-m0-plus-co-processor:LPC541XX + +.. _LPC54114 Datasheet: + https://www.nxp.com/docs/en/data-sheet/LPC5411X.pdf + +.. _LPC54114 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=UM10914 + +.. _LPCXPRESSO54114 Website: + https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso54114-board:OM13089 + +.. _LPCXPRESSO54114 User Guide: + https://www.nxp.com/webapp/Download?colCode=UM10973 + +.. _LPCXPRESSO54114 Schematics: + https://www.nxp.com/downloads/en/design-support/LPCX5411x_Schematic_Rev_A1.pdf diff --git a/boards/arm/lpcxpresso54114/doc/lpcxpresso54114_m4.jpg b/boards/nxp/lpcxpresso54114/doc/lpcxpresso54114_m4.jpg similarity index 100% rename from boards/arm/lpcxpresso54114/doc/lpcxpresso54114_m4.jpg rename to boards/nxp/lpcxpresso54114/doc/lpcxpresso54114_m4.jpg diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114-pinctrl.dtsi b/boards/nxp/lpcxpresso54114/lpcxpresso54114-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso54114/lpcxpresso54114-pinctrl.dtsi rename to boards/nxp/lpcxpresso54114/lpcxpresso54114-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114.dtsi b/boards/nxp/lpcxpresso54114/lpcxpresso54114.dtsi similarity index 100% rename from boards/arm/lpcxpresso54114/lpcxpresso54114.dtsi rename to boards/nxp/lpcxpresso54114/lpcxpresso54114.dtsi diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0.dts b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.dts similarity index 100% rename from boards/arm/lpcxpresso54114/lpcxpresso54114_m0.dts rename to boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.dts diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml new file mode 100644 index 00000000000..8f99d4bbd9d --- /dev/null +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml @@ -0,0 +1,20 @@ +# +# Copyright (c) 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: lpcxpresso54114/lpc54114/m0 +name: NXP LPCXpresso54114 M0 +type: mcu +arch: arm +ram: 32 +flash: 64 +testing: + ignore_tags: + - net +toolchain: + - xtools + - zephyr + - gnuarmemb +vendor: nxp diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig new file mode 100644 index 00000000000..9242d2359a0 --- /dev/null +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_USE_SEGGER_RTT=y +CONFIG_SERIAL=n +CONFIG_GPIO=n +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 +CONFIG_PINCTRL=y diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m4.dts b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts similarity index 100% rename from boards/arm/lpcxpresso54114/lpcxpresso54114_m4.dts rename to boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml new file mode 100644 index 00000000000..c539b58e442 --- /dev/null +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: lpcxpresso54114/lpc54114/m4 +name: NXP LPCXpresso54114 M4 +type: mcu +arch: arm +ram: 64 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_i2c + - arduino_spi + - gpio + - i2c + - spi +vendor: nxp diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig new file mode 100644 index 00000000000..921c68d49ad --- /dev/null +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig @@ -0,0 +1,15 @@ +# +# Copyright (c) 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/lpcxpresso54114/pre_dt_board.cmake b/boards/nxp/lpcxpresso54114/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso54114/pre_dt_board.cmake rename to boards/nxp/lpcxpresso54114/pre_dt_board.cmake diff --git a/boards/nxp/lpcxpresso55s06/Kconfig.defconfig b/boards/nxp/lpcxpresso55s06/Kconfig.defconfig new file mode 100644 index 00000000000..9d9e527b56e --- /dev/null +++ b/boards/nxp/lpcxpresso55s06/Kconfig.defconfig @@ -0,0 +1,16 @@ +# LPCXpresso55S06 board + +# Copyright (c) 2022 metraTec +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LPCXPRESSO55S06 + +if BOOTLOADER_MCUBOOT +choice MCUBOOT_BOOTLOADER_MODE + # Board only supports MCUBoot via "upgrade only" method: + default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY +endchoice +endif #BOOTLOADER_MCUBOOT + +endif # BOARD_LPCXPRESSO55S06 diff --git a/boards/nxp/lpcxpresso55s06/Kconfig.lpcxpresso55s06 b/boards/nxp/lpcxpresso55s06/Kconfig.lpcxpresso55s06 new file mode 100644 index 00000000000..b810ca2a91f --- /dev/null +++ b/boards/nxp/lpcxpresso55s06/Kconfig.lpcxpresso55s06 @@ -0,0 +1,8 @@ +# Copyright (c) 2022 metraTec +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO55S06 + select SOC_LPC55S06 + select SOC_PART_NUMBER_LPC55S06JBD64 diff --git a/boards/arm/lpcxpresso55s06/board.cmake b/boards/nxp/lpcxpresso55s06/board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s06/board.cmake rename to boards/nxp/lpcxpresso55s06/board.cmake diff --git a/boards/nxp/lpcxpresso55s06/board.yml b/boards/nxp/lpcxpresso55s06/board.yml new file mode 100644 index 00000000000..a15c5a1da85 --- /dev/null +++ b/boards/nxp/lpcxpresso55s06/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso55s06 + vendor: nxp + socs: + - name: lpc55s06 diff --git a/boards/arm/lpcxpresso55s06/doc/index.rst b/boards/nxp/lpcxpresso55s06/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso55s06/doc/index.rst rename to boards/nxp/lpcxpresso55s06/doc/index.rst diff --git a/boards/arm/lpcxpresso55s06/doc/lpcxpress55s06.jpg b/boards/nxp/lpcxpresso55s06/doc/lpcxpress55s06.jpg similarity index 100% rename from boards/arm/lpcxpresso55s06/doc/lpcxpress55s06.jpg rename to boards/nxp/lpcxpresso55s06/doc/lpcxpress55s06.jpg diff --git a/boards/arm/lpcxpresso55s06/lpcxpresso55s06-pinctrl.dtsi b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s06/lpcxpresso55s06-pinctrl.dtsi rename to boards/nxp/lpcxpresso55s06/lpcxpresso55s06-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso55s06/lpcxpresso55s06.dts b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.dts similarity index 100% rename from boards/arm/lpcxpresso55s06/lpcxpresso55s06.dts rename to boards/nxp/lpcxpresso55s06/lpcxpresso55s06.dts diff --git a/boards/arm/lpcxpresso55s06/lpcxpresso55s06.yaml b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml similarity index 100% rename from boards/arm/lpcxpresso55s06/lpcxpresso55s06.yaml rename to boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml diff --git a/boards/arm/lpcxpresso55s06/lpcxpresso55s06_common.dtsi b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s06/lpcxpresso55s06_common.dtsi rename to boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi diff --git a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_defconfig b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_defconfig new file mode 100644 index 00000000000..6fcd01d4551 --- /dev/null +++ b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_defconfig @@ -0,0 +1,15 @@ +# +# Copyright (c) 2022 metraTec +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_ARM_MPU=y + +CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s06/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s06/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s06/pre_dt_board.cmake rename to boards/nxp/lpcxpresso55s06/pre_dt_board.cmake diff --git a/boards/nxp/lpcxpresso55s16/Kconfig.defconfig b/boards/nxp/lpcxpresso55s16/Kconfig.defconfig new file mode 100644 index 00000000000..5b29155063a --- /dev/null +++ b/boards/nxp/lpcxpresso55s16/Kconfig.defconfig @@ -0,0 +1,19 @@ +# LPCXpresso55S16 board + +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LPCXPRESSO55S16 + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +if BOOTLOADER_MCUBOOT +choice MCUBOOT_BOOTLOADER_MODE + # Board only supports MCUBoot via "upgrade only" method: + default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY +endchoice +endif #BOOTLOADER_MCUBOOT + +endif # BOARD_LPCXPRESSO55S16 diff --git a/boards/nxp/lpcxpresso55s16/Kconfig.lpcxpresso55s16 b/boards/nxp/lpcxpresso55s16/Kconfig.lpcxpresso55s16 new file mode 100644 index 00000000000..38928131a5e --- /dev/null +++ b/boards/nxp/lpcxpresso55s16/Kconfig.lpcxpresso55s16 @@ -0,0 +1,8 @@ +# Copyright (c) 2020 Henrik Brix Andersen +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO55S16 + select SOC_LPC55S16 + select SOC_PART_NUMBER_LPC55S16JBD100 diff --git a/boards/arm/lpcxpresso55s16/board.cmake b/boards/nxp/lpcxpresso55s16/board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s16/board.cmake rename to boards/nxp/lpcxpresso55s16/board.cmake diff --git a/boards/nxp/lpcxpresso55s16/board.yml b/boards/nxp/lpcxpresso55s16/board.yml new file mode 100644 index 00000000000..5b4c627af1c --- /dev/null +++ b/boards/nxp/lpcxpresso55s16/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso55s16 + vendor: nxp + socs: + - name: lpc55s16 diff --git a/boards/arm/lpcxpresso55s16/doc/index.rst b/boards/nxp/lpcxpresso55s16/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso55s16/doc/index.rst rename to boards/nxp/lpcxpresso55s16/doc/index.rst diff --git a/boards/arm/lpcxpresso55s16/doc/lpcxpresso55S16.jpg b/boards/nxp/lpcxpresso55s16/doc/lpcxpresso55S16.jpg similarity index 100% rename from boards/arm/lpcxpresso55s16/doc/lpcxpresso55S16.jpg rename to boards/nxp/lpcxpresso55s16/doc/lpcxpresso55S16.jpg diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16-pinctrl.dtsi b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s16/lpcxpresso55s16-pinctrl.dtsi rename to boards/nxp/lpcxpresso55s16/lpcxpresso55s16-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16.dts b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts similarity index 100% rename from boards/arm/lpcxpresso55s16/lpcxpresso55s16.dts rename to boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16.yaml b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml similarity index 100% rename from boards/arm/lpcxpresso55s16/lpcxpresso55s16.yaml rename to boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16_common.dtsi b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s16/lpcxpresso55s16_common.dtsi rename to boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16_defconfig b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_defconfig similarity index 76% rename from boards/arm/lpcxpresso55s16/lpcxpresso55s16_defconfig rename to boards/nxp/lpcxpresso55s16/lpcxpresso55s16_defconfig index 44af7c468e1..e327fa910d7 100644 --- a/boards/arm/lpcxpresso55s16/lpcxpresso55s16_defconfig +++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S16=y -CONFIG_BOARD_LPCXPRESSO55S16=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/lpcxpresso55s16/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s16/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s16/pre_dt_board.cmake rename to boards/nxp/lpcxpresso55s16/pre_dt_board.cmake diff --git a/boards/nxp/lpcxpresso55s28/Kconfig.defconfig b/boards/nxp/lpcxpresso55s28/Kconfig.defconfig new file mode 100644 index 00000000000..5642f6b9a0f --- /dev/null +++ b/boards/nxp/lpcxpresso55s28/Kconfig.defconfig @@ -0,0 +1,44 @@ +# LPCXpresso55S28 board + +# Copyright (c) 2020 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LPCXPRESSO55S28 + +if FXOS8700 + +choice FXOS8700_MODE + default FXOS8700_MODE_ACCEL +endchoice + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +endif # FXOS8700 + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_LPCXPRESSO55S28 && TRUSTED_EXECUTION_SECURE + +if BOOTLOADER_MCUBOOT +choice MCUBOOT_BOOTLOADER_MODE + # Board only supports MCUBoot via "upgrade only" method: + default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY +endchoice +endif #BOOTLOADER_MCUBOOT + +endif # BOARD_LPCXPRESSO55S28 diff --git a/boards/nxp/lpcxpresso55s28/Kconfig.lpcxpresso55s28 b/boards/nxp/lpcxpresso55s28/Kconfig.lpcxpresso55s28 new file mode 100644 index 00000000000..7947180bdf4 --- /dev/null +++ b/boards/nxp/lpcxpresso55s28/Kconfig.lpcxpresso55s28 @@ -0,0 +1,8 @@ +# Copyright (c) 2020 Lemonbeat GmbH +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO55S28 + select SOC_LPC55S28 + select SOC_PART_NUMBER_LPC55S28JBD100 diff --git a/boards/arm/lpcxpresso55s28/board.cmake b/boards/nxp/lpcxpresso55s28/board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s28/board.cmake rename to boards/nxp/lpcxpresso55s28/board.cmake diff --git a/boards/nxp/lpcxpresso55s28/board.yml b/boards/nxp/lpcxpresso55s28/board.yml new file mode 100644 index 00000000000..d4309c4e3df --- /dev/null +++ b/boards/nxp/lpcxpresso55s28/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso55s28 + vendor: nxp + socs: + - name: lpc55s28 diff --git a/boards/arm/lpcxpresso55s28/doc/LPC55S28-EVK.jpg b/boards/nxp/lpcxpresso55s28/doc/LPC55S28-EVK.jpg similarity index 100% rename from boards/arm/lpcxpresso55s28/doc/LPC55S28-EVK.jpg rename to boards/nxp/lpcxpresso55s28/doc/LPC55S28-EVK.jpg diff --git a/boards/arm/lpcxpresso55s28/doc/index.rst b/boards/nxp/lpcxpresso55s28/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso55s28/doc/index.rst rename to boards/nxp/lpcxpresso55s28/doc/index.rst diff --git a/boards/arm/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi rename to boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso55s28/lpcxpresso55s28.dts b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts similarity index 100% rename from boards/arm/lpcxpresso55s28/lpcxpresso55s28.dts rename to boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts diff --git a/boards/arm/lpcxpresso55s28/lpcxpresso55s28.yaml b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml similarity index 100% rename from boards/arm/lpcxpresso55s28/lpcxpresso55s28.yaml rename to boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml diff --git a/boards/arm/lpcxpresso55s28/lpcxpresso55s28_common.dtsi b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s28/lpcxpresso55s28_common.dtsi rename to boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi diff --git a/boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig similarity index 78% rename from boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig rename to boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig index 8ce8f718d7e..1a23b7b3d78 100644 --- a/boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig @@ -1,12 +1,10 @@ # # Copyright (c) 2020 Lemonbeat GmbH +# Copyright 2024 NXP # # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S28=y -CONFIG_BOARD_LPCXPRESSO55S28=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/lpcxpresso55s28/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s28/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s28/pre_dt_board.cmake rename to boards/nxp/lpcxpresso55s28/pre_dt_board.cmake diff --git a/boards/arm/lpcxpresso55s36/Kconfig.defconfig b/boards/nxp/lpcxpresso55s36/Kconfig.defconfig similarity index 100% rename from boards/arm/lpcxpresso55s36/Kconfig.defconfig rename to boards/nxp/lpcxpresso55s36/Kconfig.defconfig diff --git a/boards/nxp/lpcxpresso55s36/Kconfig.lpcxpresso55s36 b/boards/nxp/lpcxpresso55s36/Kconfig.lpcxpresso55s36 new file mode 100644 index 00000000000..61e25cddbe8 --- /dev/null +++ b/boards/nxp/lpcxpresso55s36/Kconfig.lpcxpresso55s36 @@ -0,0 +1,6 @@ +# Copyright 2022, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO55S36 + select SOC_LPC55S36 + select SOC_PART_NUMBER_LPC55S36JBD100 diff --git a/boards/arm/lpcxpresso55s36/board.cmake b/boards/nxp/lpcxpresso55s36/board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s36/board.cmake rename to boards/nxp/lpcxpresso55s36/board.cmake diff --git a/boards/nxp/lpcxpresso55s36/board.yml b/boards/nxp/lpcxpresso55s36/board.yml new file mode 100644 index 00000000000..e888d768815 --- /dev/null +++ b/boards/nxp/lpcxpresso55s36/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso55s36 + vendor: nxp + socs: + - name: lpc55s36 diff --git a/boards/arm/lpcxpresso55s36/doc/index.rst b/boards/nxp/lpcxpresso55s36/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso55s36/doc/index.rst rename to boards/nxp/lpcxpresso55s36/doc/index.rst diff --git a/boards/arm/lpcxpresso55s36/doc/lpcxpresso55S36.jpg b/boards/nxp/lpcxpresso55s36/doc/lpcxpresso55S36.jpg similarity index 100% rename from boards/arm/lpcxpresso55s36/doc/lpcxpresso55S36.jpg rename to boards/nxp/lpcxpresso55s36/doc/lpcxpresso55S36.jpg diff --git a/boards/arm/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi rename to boards/nxp/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso55s36/lpcxpresso55s36.dts b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts similarity index 100% rename from boards/arm/lpcxpresso55s36/lpcxpresso55s36.dts rename to boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts diff --git a/boards/arm/lpcxpresso55s36/lpcxpresso55s36.yaml b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml similarity index 100% rename from boards/arm/lpcxpresso55s36/lpcxpresso55s36.yaml rename to boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36_defconfig b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36_defconfig new file mode 100644 index 00000000000..9aaf3ff8452 --- /dev/null +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36_defconfig @@ -0,0 +1,15 @@ +# +# Copyright 2022, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_ARM_MPU=y + +CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s36/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s36/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s36/pre_dt_board.cmake rename to boards/nxp/lpcxpresso55s36/pre_dt_board.cmake diff --git a/boards/arm/lpcxpresso55s69/CMakeLists.txt b/boards/nxp/lpcxpresso55s69/CMakeLists.txt similarity index 100% rename from boards/arm/lpcxpresso55s69/CMakeLists.txt rename to boards/nxp/lpcxpresso55s69/CMakeLists.txt diff --git a/boards/nxp/lpcxpresso55s69/Kconfig.defconfig b/boards/nxp/lpcxpresso55s69/Kconfig.defconfig new file mode 100644 index 00000000000..5a48b7afe24 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/Kconfig.defconfig @@ -0,0 +1,59 @@ +# Copyright 2019,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LPCXPRESSO55S69 + +if FXOS8700 + +choice FXOS8700_MODE + default FXOS8700_MODE_ACCEL +endchoice + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +endif # FXOS8700 + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 && TRUSTED_EXECUTION_SECURE + +if TRUSTED_EXECUTION_NONSECURE || BOARD_LPCXPRESSO55S69_LPC55S69_CPU1 + +config FLASH_LOAD_OFFSET + default 0x50000 if (!TFM_BL2 && BUILD_WITH_TFM) + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default 0x40000 if (!TFM_BL2 && BUILD_WITH_TFM) + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # TRUSTED_EXECUTION_NONSECURE || BOARD_LPCXPRESSO55S69_LPC55S69_CPU1 + +choice TFM_PROFILE_TYPE + depends on BUILD_WITH_TFM + default TFM_PROFILE_TYPE_MEDIUM +endchoice + +if BOOTLOADER_MCUBOOT +choice MCUBOOT_BOOTLOADER_MODE + # Board only supports MCUBoot via "upgrade only" method: + default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY +endchoice +endif #BOOTLOADER_MCUBOOT + +endif # BOARD_LPCXPRESSO55S69 diff --git a/boards/nxp/lpcxpresso55s69/Kconfig.lpcxpresso55s69 b/boards/nxp/lpcxpresso55s69/Kconfig.lpcxpresso55s69 new file mode 100644 index 00000000000..c047500eca1 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/Kconfig.lpcxpresso55s69 @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO55S69 + select SOC_LPC55S69_CPU0 if BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 || \ + BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS + select SOC_LPC55S69_CPU1 if BOARD_LPCXPRESSO55S69_LPC55S69_CPU1 + select SOC_PART_NUMBER_LPC55S69JBD100 diff --git a/boards/nxp/lpcxpresso55s69/board.cmake b/boards/nxp/lpcxpresso55s69/board.cmake new file mode 100644 index 00000000000..137b2e614f3 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/board.cmake @@ -0,0 +1,30 @@ +# +# Copyright 2019, 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + + +## DAP Link implementation in pyocd is underway, +## until then jlink can be used or copy image to storage + +if(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR + CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS OR + CONFIG_SECOND_CORE_MCUX) + board_runner_args(jlink "--device=LPC55S69_M33_0") + board_runner_args(linkserver "--device=LPC55S69:LPCXpresso55S69") + board_runner_args(linkserver "--override=/device/memory/0/flash-driver=LPC55xx_S.cfx") + board_runner_args(linkserver "--override=/device/memory/0/location=0x10000000") +elseif(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU1) + board_runner_args(jlink "--device=LPC55S69_M33_1") +endif() + +board_runner_args(pyocd "--target=lpc55s69") + +if(CONFIG_BUILD_WITH_TFM) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/lpcxpresso55s69/board.yml b/boards/nxp/lpcxpresso55s69/board.yml new file mode 100644 index 00000000000..605ab7b3e9f --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/board.yml @@ -0,0 +1,8 @@ +board: + name: lpcxpresso55s69 + vendor: nxp + socs: + - name: lpc55s69 + variants: + - name: "ns" + cpucluster: 'cpu0' diff --git a/boards/nxp/lpcxpresso55s69/doc/index.rst b/boards/nxp/lpcxpresso55s69/doc/index.rst new file mode 100644 index 00000000000..449d80b7af6 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/doc/index.rst @@ -0,0 +1,413 @@ +.. _lpcxpresso55s69: + +NXP LPCXPRESSO55S69 +################### + +Overview +******** + +The LPCXpresso55S69 development board provides the ideal platform for evaluation +of and development with the LPC55S6x MCU based on the Arm® Cortex®-M33 +architecture. The board includes a high performance onboard debug probe, audio +subsystem, and accelerometer, with several options for adding off-the-shelf +add-on boards for networking, sensors, displays, and other interfaces. + +.. image:: lpcxpresso55s69.jpg + :align: center + :alt: LPCXPRESSO55S69 + +Hardware +******** + +- LPC55S69 dual core Arm Cortex-M33 microcontroller running at up to 100 MHz +- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER J-Link + protocol options +- UART and SPI port bridging from LPC55S69 target to USB via the onboard debug + probe +- Hardware support for external debug probe +- 3 x user LEDs, plus Reset, ISP (3) and user buttons +- Micro SD card slot (4-bit SDIO) +- NXP MMA8652FCR1 accelerometer +- Stereo audio codec with line in/out +- High and full speed USB ports with micro A/B connector for host or device + functionality +- MikroEletronika Click expansion option +- LPCXpresso-V3 expansion option compatible with Arduino UNO +- PMod compatible expansion / host connector + +For more information about the LPC55S69 SoC and LPCXPRESSO55S69 board, see: + +- `LPC55S69 SoC Website`_ +- `LPC55S69 Datasheet`_ +- `LPC55S69 Reference Manual`_ +- `LPCXPRESSO55S69 Website`_ +- `LPCXPRESSO55S69 User Guide`_ +- `LPCXPRESSO55S69 Schematics`_ +- `LPCXPRESSO55S69 Debug Firmware`_ + +Supported Features +================== + +NXP considers the LPCXpresso55S69 as the superset board for the LPC55xx +series of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire LPC55xx series. NXP prioritizes enabling +this board with new support for Zephyr features. The lpcxpresso55s69 board +configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| IOCON | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WWDT | on-chip | windowed watchdog timer | ++-----------+------------+-------------------------------------+ +| TrustZone | on-chip | Trusted Firmware-M | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| MAILBOX | on-chip | ipm | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| USB HS | on-chip | USB High Speed device | ++-----------+------------+-------------------------------------+ +| USB FS | on-chip | USB Full Speed device | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | entropy; | +| | | random | ++-----------+------------+-------------------------------------+ +| IAP | on-chip | flash programming | ++-----------+------------+-------------------------------------+ +| SDIF | on-chip | sdhc | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma (on CPU0) | ++-----------+------------+-------------------------------------+ + +Targets available +================== + +The default configuration file +``boards/arm/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig`` +only enables the first core. +CPU0 is the only target that can run standalone. + +- *lpcxpresso55s69/lpc55s69/cpu0* secure (S) address space for CPU0 +- *lpcxpresso55s69/lpc55s69/cpu0/ns* non-secure (NS) address space for CPU0 +- *lpcxpresso55s69/lpc55s69/cpu1* CPU1 target, no security extensions + +NS target for CPU0 does not work correctly without a secure image to configure +the system, then hand execution over to the NS environment. To enable a secure +image, run any of the ``tfm_integration`` samples. When using the NS target +``CONFIG_BUILD_WITH_TFM`` is always enabled to ensure that a valid S image is +included during the build process. + +CPU1 does not work without CPU0 enabling it. +To enable it, run one of the following samples in ``subsys\ipc``: +- ``ipm_mcux`` +- ``openamp`` + +Connections and IOs +=================== + +The LPC55S69 SoC has IOCON registers, which can be used to configure the +functionality of a pin. + ++---------+-----------------+----------------------------+ +| Name | Function | Usage | ++=========+=================+============================+ +| PIO0_26 | SPI | SPI MOSI | ++---------+-----------------+----------------------------+ +| PIO0_27 | USART | USART TX | ++---------+-----------------+----------------------------+ +| PIO0_29 | USART | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_30 | USART | USART TX | ++---------+-----------------+----------------------------+ +| PIO1_1 | SPI | SPI SSEL | ++---------+-----------------+----------------------------+ +| PIO1_2 | SPI | SPI SCK | ++---------+-----------------+----------------------------+ +| PIO1_3 | SPI | SPI MISO | ++---------+-----------------+----------------------------+ +| PIO1_4 | GPIO | RED LED | ++---------+-----------------+----------------------------+ +| PIO1_6 | GPIO | BLUE_LED | ++---------+-----------------+----------------------------+ +| PIO1_7 | GPIO | GREEN LED | ++---------+-----------------+----------------------------+ +| PIO1_20 | I2C | I2C SCL | ++---------+-----------------+----------------------------+ +| PIO1_21 | I2C | I2C SDA | ++---------+-----------------+----------------------------+ +| PIO1_24 | USART | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_20 | I2S | I2S DATAOUT | ++---------+-----------------+----------------------------+ +| PIO0_19 | I2S | I2S TX WS | ++---------+-----------------+----------------------------+ +| PIO0_21 | I2S | I2S TX SCK | ++---------+-----------------+----------------------------+ +| PIO1_13 | I2S | I2S DATAIN | ++---------+-----------------+----------------------------+ +| PIO0_15 | SCT0_OUT2 | PWM | ++---------+-----------------+----------------------------+ +| PIO0_24 | SD0_D0 | SDHC | ++---------+-----------------+----------------------------+ +| PIO0_25 | SD0_D1 | SDHC | ++---------+-----------------+----------------------------+ +| PIO0_31 | SD0_D2 | SDHC | ++---------+-----------------+----------------------------+ +| PIO0_7 | SD0_CLK | SDHC | ++---------+-----------------+----------------------------+ +| PIO0_8 | SD0_CMD | SDHC | ++---------+-----------------+----------------------------+ +| PIO0_9 | SD0_POW_EN | SDHC | ++---------+-----------------+----------------------------+ +| PIO1_0 | SD0_D3 | SDHC | ++---------+-----------------+----------------------------+ + +Memory mappings +=============== + +There are multiple memory configurations, they all start from the +MCUboot partitioning which looks like the table below + ++----------+------------------+---------------------------------+ +| Name | Address[Size] | Comment | ++==========+==================+=================================+ +| boot | 0x00000000[32K] | Bootloader | ++----------+------------------+---------------------------------+ +| slot0 | 0x00008000[160k] | Image that runs after boot | ++----------+------------------+---------------------------------+ +| slot0_ns | 0x00030000[96k] | Second image, core 1 or NS | ++----------+------------------+---------------------------------+ +| slot1 | 0x00048000[160k] | Updates slot0 image | ++----------+------------------+---------------------------------+ +| slot1_ns | 0x00070000[96k] | Updates slot0_ns image | ++----------+------------------+---------------------------------+ +| storage | 0x00088000[50k] | File system, persistent storage | ++----------+------------------+---------------------------------+ + +See below examples of how this partitioning is used + +Trusted Execution +***************** + ++-----------+------------------+--------------------+ +| Memory | Address[Size] | Comment | ++===========+==================+====================+ +| MCUboot | 0x00000000[32K] | Secure bootloader | ++-----------+------------------+--------------------+ +| TFM_S | 0x00008000[160k] | Secure image | ++-----------+------------------+--------------------+ +| Zephyr_NS | 0x00030000[96k] | Non-Secure image | ++-----------+------------------+--------------------+ +| storage | 0x00088000[50k] | Persistent storage | ++-----------+------------------+--------------------+ + ++----------------+------------------+-------------------+ +| RAM | Address[Size] | Comment | ++================+==================+===================+ +| secure_ram | 0x20000000[136k] | Secure memory | ++----------------+------------------+-------------------+ +| non_secure_ram | 0x20022000[136k] | Non-Secure memory | ++----------------+------------------+-------------------+ + +Dual Core samples +***************** + ++--------+------------------+----------------------------+ +| Memory | Address[Size] | Comment | ++========+==================+============================+ +| CPU0 | 0x00000000[630K] | CPU0, can access all flash | ++--------+------------------+----------------------------+ +| CPU1 | 0x00030000[96k] | CPU1, has no MPU | ++--------+------------------+----------------------------+ + ++-------+------------------+-----------------------+ +| RAM | Address[Size] | Comment | ++=======+==================+=======================+ +| sram0 | 0x20000000[64k] | CPU0 memory | ++-------+------------------+-----------------------+ +| sram3 | 0x20030000[64k] | CPU1 memory | ++-------+------------------+-----------------------+ +| sram4 | 0x20040000[16k] | Mailbox/shared memory | ++-------+------------------+-----------------------+ + +System Clock +============ + +The LPC55S69 SoC is configured to use PLL1 clocked from the external 16MHz +crystal, running at 144MHz as a source for the system clock. When the flash +controller is enabled, the core clock will be reduced to 96MHz. The application +may reconfigure clocks after initialization, provided that the core clock is +always set to 96MHz when flash programming operations are performed. + +Serial Port +=========== + +The LPC55S69 SoC has 8 FLEXCOMM interfaces for serial communication. One is +configured as USART for the console and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe, +however the :ref:`pyocd-debug-host-tools` does not yet support this probe so you +must reconfigure the board for one of the following debug probes instead. + +:ref:`lpclink2-jlink-onboard-debug-probe` +----------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program +the J-Link firmware. Please make sure you have the latest firmware for this +board. + +:ref:`lpclink2-cmsis-onboard-debug-probe` +----------------------------------------- + + 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. + 2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware` + +:ref:`opensda-daplink-onboard-debug-probe` +------------------------------------------ + +PyOCD support for this board is ongoing and not yet available. +To use DAPLink's flash memory programming on this board, follow the instructions +for `updating LPCXpresso firmware`_. + +Configuring a Console +===================== + +Connect a USB cable from your PC to P6, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: lpcxpresso55s69/lpc55s69/cpu0 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0 ***** + Hello World! lpcxpresso55s69_cpu0 + +Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| +---------------------------------------------------------------------- +The TF-M integration samples can be run using the ``lpcxpresso55s69_ns`` target. +To run we need to manually flash the resulting image (``tfm_merged.hex``) with +a J-Link as follows (reset and erase are for recovering a locked core): + + .. code-block:: console + + JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1 + J-Link>r + J-Link>erase + J-Link>loadfile build/zephyr/tfm_merged.hex + +We need to reset the board manually after flashing the image to run this code. + +Building a dual-core image +-------------------------- +The dual-core samples are run using ``lpcxpresso55s69_cpu0`` target, +``lpcxpresso55s69_cpu1`` will be automatically built and merged in a single +image when ``SECOND_CORE_MCUX`` is selected. +To run we need to manually flash the resulting image (``multicore.bin``) with a +J-Link as follows (reset and erase are for recovering a locked core): + + .. code-block:: console + + JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1 + J-Link>r + J-Link>erase + J-Link>loadfile build/multicore.bin + +We need to reset the board manually after flashing the image to run this code. + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: lpcxpresso55s69_cpu0 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS zephyr-v1.14.0 ***** + Hello World! lpcxpresso55s69_cpu0 + +.. _LPC55S69 SoC Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/high-efficiency-arm-cortex-m33-based-microcontroller-family:LPC55S6x + +.. _LPC55S69 Datasheet: + https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf + +.. _LPC55S69 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=UM11126 + +.. _LPCXPRESSO55S69 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/lpcxpresso55s69-development-board:LPC55S69-EVK + +.. _LPCXPRESSO55S69 User Guide: + https://www.nxp.com/webapp/Download?colCode=UM11158 + +.. _LPCXPRESSO55S69 Debug Firmware: + https://www.nxp.com/docs/en/application-note/AN13206.pdf + +.. _LPCXPRESSO55S69 Schematics: + https://www.nxp.com/webapp/Download?colCode=LPC55S69-SCH + +.. _updating LPCXpresso firmware: + https://os.mbed.com/teams/NXP/wiki/Updating-LPCXpresso-firmware diff --git a/boards/arm/lpcxpresso55s69/doc/lpcxpresso55s69.jpg b/boards/nxp/lpcxpresso55s69/doc/lpcxpresso55s69.jpg similarity index 100% rename from boards/arm/lpcxpresso55s69/doc/lpcxpresso55s69.jpg rename to boards/nxp/lpcxpresso55s69/doc/lpcxpresso55s69.jpg diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi rename to boards/nxp/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69.dtsi b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s69/lpcxpresso55s69.dtsi rename to boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_defconfig new file mode 100644 index 00000000000..32700cd4833 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_defconfig @@ -0,0 +1,12 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +# Common Kconfigs for all board targets +# + +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts similarity index 100% rename from boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts rename to boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml new file mode 100644 index 00000000000..ae375cdeb66 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml @@ -0,0 +1,30 @@ +# +# Copyright 2019, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: lpcxpresso55s69/lpc55s69/cpu0 +name: NXP LPCXpresso55S69 (CPU0) +type: mcu +arch: arm +ram: 64 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - arduino_i2c + - arduino_serial + - arduino_spi + - counter + - gpio + - i2c + - i2s + - spi + - sdhc + - usb_device + - watchdog +vendor: nxp diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig new file mode 100644 index 00000000000..966a0228f10 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig @@ -0,0 +1,16 @@ +# +# Copyright 2019,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y +CONFIG_ARM_TRUSTZONE_M=y diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts similarity index 100% rename from boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.dts rename to boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml new file mode 100644 index 00000000000..5d76704ba7b --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml @@ -0,0 +1,25 @@ +# +# Copyright 2019, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: lpcxpresso55s69/lpc55s69/cpu0/ns +name: NXP LPCXpresso55S69 (Non-Secure) +type: mcu +arch: arm +ram: 136 +flash: 96 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - arduino_spi + - counter + - dma + - gpio + - spi + - watchdog +vendor: nxp diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig new file mode 100644 index 00000000000..b93da92c709 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig @@ -0,0 +1,19 @@ +# +# Copyright 2019,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +CONFIG_ARM_MPU=n + +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_NONSECURE=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_BUILD_WITH_TFM=y + +CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.dts similarity index 100% rename from boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.dts rename to boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.dts diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml new file mode 100644 index 00000000000..4d6f1c70ab8 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2019, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: lpcxpresso55s69/lpc55s69/cpu1 +name: NXP LPCXpresso55S69 (CPU1) +type: mcu +arch: arm +ram: 64 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio +vendor: nxp diff --git a/boards/arm/lpcxpresso55s69/pinmux.c b/boards/nxp/lpcxpresso55s69/pinmux.c similarity index 100% rename from boards/arm/lpcxpresso55s69/pinmux.c rename to boards/nxp/lpcxpresso55s69/pinmux.c diff --git a/boards/arm/lpcxpresso55s69/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s69/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s69/pre_dt_board.cmake rename to boards/nxp/lpcxpresso55s69/pre_dt_board.cmake diff --git a/boards/arm64/mimx93_evk/CMakeLists.txt b/boards/nxp/ls1046ardb/CMakeLists.txt similarity index 100% rename from boards/arm64/mimx93_evk/CMakeLists.txt rename to boards/nxp/ls1046ardb/CMakeLists.txt diff --git a/boards/nxp/ls1046ardb/Kconfig.ls1046ardb b/boards/nxp/ls1046ardb/Kconfig.ls1046ardb new file mode 100644 index 00000000000..4b671144be7 --- /dev/null +++ b/boards/nxp/ls1046ardb/Kconfig.ls1046ardb @@ -0,0 +1,8 @@ +# +# Copyright 2021,2024 NXP +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_LS1046ARDB + select SOC_LS1046A + select SOC_PART_NUMBER_LS1046A diff --git a/boards/arm64/mimx8mp_evk/board.cmake b/boards/nxp/ls1046ardb/board.cmake similarity index 100% rename from boards/arm64/mimx8mp_evk/board.cmake rename to boards/nxp/ls1046ardb/board.cmake diff --git a/boards/nxp/ls1046ardb/board.yml b/boards/nxp/ls1046ardb/board.yml new file mode 100644 index 00000000000..9ad69170480 --- /dev/null +++ b/boards/nxp/ls1046ardb/board.yml @@ -0,0 +1,9 @@ +board: + name: ls1046ardb + vendor: nxp + socs: + - name: ls1046a + variants: + - name: smp + variants: + - name: 4cores diff --git a/boards/nxp/ls1046ardb/doc/index.rst b/boards/nxp/ls1046ardb/doc/index.rst new file mode 100644 index 00000000000..c6065c4f312 --- /dev/null +++ b/boards/nxp/ls1046ardb/doc/index.rst @@ -0,0 +1,215 @@ +.. _nxp_ls1046ardb: + +NXP LS1046A RDB +################################# + +Overview +******** + +The LS1046A reference design board (RDB) is a high-performance computing, +evaluation, and development platform that supports the Layerscape LS1046A +architecture processor. The LS1046ARDB board supports the Layerscape LS1046A +processor and is optimized to support the DDR4 memory and a full complement +of high-speed SerDes ports. + +The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72 +cores with packet processing acceleration and high-speed peripherals. The +impressive performance of more than 32,000 CoreMarks, paired with 10 Gb +Ethernet, PCIe Gen. 3, SATA 3.0, USB 3.0 and QSPI interfaces provides an +excellent combination for a range of enterprise and service provider +networking, storage, security and industrial applications. + +Hardware +******** + +LS1046A RDB boards supports the following features: + + +- Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed +- Supports 8 GB DDR4 SDRAM memory +- SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi + memory device +- One 512 MB SLC NAND flash with ECC support (1.8 V) +- CPLD connection: 8-bit registers in CPLD to configure mux/demux selections +- Support two 64 MB onboard QSPI NOR flash memories +- USB: + - Two USB 3.0 controllers with integrated PHYs. + - One USB1 3.0 port is connected to a Type A host connector. + - One USB1 3.0 port is configured as On-The-Go (OTG) with a Micro-AB connector. + - One USB2.0 is connected to miniPCIe connector . +- Ethernet: + - Supports SGMII 1G PHYs at Lane 2 and Lane 3 + - Supports SFP+module with XFI retimers + - Supports AQR106/107 10G PHY with XFI/2.5G SGMII +- PCIe and SATA: + - Mini PCIe express x1 (Gen1/2/3)card + - Standard PCIe x1 (Gen1/2/3) card + - Standard PCIe x1 (Gen1/2/3) card + - One SATA 3.0 connector + +Supported Features +================== + +NXP LS1046A RDB board default configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| GIC-400 | on-chip | GICv2 interrupt controller | ++-----------+------------+--------------------------------------+ +| ARM TIMER | on-chip | System Clock | ++-----------+------------+--------------------------------------+ +| UART | on-chip | NS16550 compatible serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in the defconfig file for NON-SMP: + + :zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig` + +Or for SMP running on all four CPU Cores: + + :zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig` + +Or for SMP running on 2 CPU Cores (Core2 and Core3): + + :zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig` + +There are two serial port on the board: uart1 and uart2, Zephyr is using +uart2 as serial console. + +Programming and Debugging +************************* + +Use the following configuration to run basic Zephyr applications and +kernel tests on LS1046A RDB board. For example, with the :zephyr:code-sample:`synchronization` sample: + +1. Non-SMP mode + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: ls1046ardb + :goals: build + +This will build an image with the synchronization sample app. + +Use u-boot to load and kick Zephyr.bin to CPU Core0: + +.. code-block:: console + + tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go 0xc0000000; + +Or kick Zephyr.bin to any other CPU Cores, for example run Zephyr on Core3: + +.. code-block:: console + + tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 3 release 0xc0000000; + + +It will display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + thread_b: Hello World from cpu 0 on nxp_ls1046ardb! + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + +2. SMP mode running on 4 CPU Cores + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: ls1046ardb/ls1046a/smp/4cores + :goals: build + +This will build an image with the synchronization sample app. + +Use u-boot to load and kick Zephyr.bin to CPU Core0: + +.. code-block:: console + + tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go 0xc0000000; + +It will display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** + Secondary CPU core 1 (MPID:0x1) is up + Secondary CPU core 2 (MPID:0x2) is up + Secondary CPU core 3 (MPID:0x3) is up + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + thread_b: Hello World from cpu 1 on nxp_ls1046ardb! + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + +3. SMP mode running on 2 CPU Cores: Core2 and Core3 + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: ls1046ardb/ls1046a/smp + :goals: build + +This will build an image with the synchronization sample app. + +Use u-boot to load and kick Zephyr.bin to CPU Core2: + +.. code-block:: console + + tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 2 release 0xc0000000; + +It will display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** + Secondary CPU core 1 (MPID:0x3) is up + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + thread_b: Hello World from cpu 1 on nxp_ls1046ardb! + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + +4. Running Zephyr on Jailhouse inmate Cell + +Use the following to run Zephyr in Jailhouse inmate, need to configure Jailhouse +inmate Cell to use a single Core for Zephyr non-SMP mode, or use Core2 and Core3 +for Zephyr SMP 2cores image. + +1) Use root Cell dts to boot root Cell Linux. + +2) Install Jailhouse module: + +.. code-block:: console + + modprobe jailhouse + +3) Run Zephyr demo in inmate Cell: + +.. code-block:: console + + jailhouse enable ls1046a-rdb.cell + jailhouse cell create ls1046a-rdb-inmate-demo.cell + jailhouse cell load 1 zephyr.bin --address 0xc0000000 + jailhouse cell start 1 + +Flashing +======== + +Zephyr image can be loaded in DDR memory at address 0xc0000000 from SD Card, +EMMC, QSPI Flash or downloaded from network in uboot. + +Debugging +========= + +LS1046A RDB board includes one JTAG connector on board, connect it to +CodeWarrior TAP for debugging. + +References +========== + +`Layerscape LS1046A Reference Design Board `_ + +`LS1046A Reference Manual `_ diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.dts b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a.dts similarity index 100% rename from boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.dts rename to boards/nxp/ls1046ardb/ls1046ardb_ls1046a.dts diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a.yaml b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a.yaml new file mode 100644 index 00000000000..bbf14171767 --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a.yaml @@ -0,0 +1,9 @@ +identifier: ls1046ardb +name: NXP LS1046ARDB on single CPU Core (NON-SMP) +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +vendor: nxp diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig new file mode 100644 index 00000000000..f33d12913c8 --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig @@ -0,0 +1,20 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_40=y +CONFIG_ARM64_PA_BITS_40=y +# 25 MHz system clock +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_AARCH64_IMAGE_HEADER=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores.dts b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.dts similarity index 100% rename from boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores.dts rename to boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.dts diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.yaml b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.yaml new file mode 100644 index 00000000000..50a321527b0 --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.yaml @@ -0,0 +1,9 @@ +identifier: ls1046ardb/ls1046a/smp +name: NXP LS1046ARDB SMP on CPU Core2 and Core3 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +vendor: nxp diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores.dts b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.dts similarity index 100% rename from boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores.dts rename to boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.dts diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.yaml b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.yaml new file mode 100644 index 00000000000..484e40bd0b4 --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.yaml @@ -0,0 +1,9 @@ +identifier: ls1046ardb/ls1046a/smp/4cores +name: NXP LS1046ARDB SMP on four CPU Cores +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +vendor: nxp diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig new file mode 100644 index 00000000000..2d2429f57d2 --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# SMP support +CONFIG_MP_MAX_NUM_CPUS=4 diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig new file mode 100644 index 00000000000..ace2e242267 --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Zephyr Kernel Configuration +CONFIG_MAX_THREAD_BYTES=5 +CONFIG_MAX_XLAT_TABLES=10 + +# SMP support +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_CACHE_MANAGEMENT=y +CONFIG_ARMV8_A_NS=y + +# PSCI is supported +CONFIG_PM_CPU_OPS=y diff --git a/boards/nxp/mimxrt1010_evk/CMakeLists.txt b/boards/nxp/mimxrt1010_evk/CMakeLists.txt new file mode 100644 index 00000000000..260448d63c7 --- /dev/null +++ b/boards/nxp/mimxrt1010_evk/CMakeLists.txt @@ -0,0 +1,33 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(init.c) + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + if(NOT DEFINED CONFIG_BOARD_MIMXRT1010_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1010-EVK, but targeting a custom board. You may need to " + "update your flash configuration data blocks") + endif() + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1010 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + set(RT1010_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1010") + zephyr_library_sources(${RT1010_BOARD_DIR}/xip/evkmimxrt1010_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1010_BOARD_DIR}/xip) + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1010_evk/Kconfig.mimxrt1010_evk b/boards/nxp/mimxrt1010_evk/Kconfig.mimxrt1010_evk new file mode 100644 index 00000000000..faf3f0c884d --- /dev/null +++ b/boards/nxp/mimxrt1010_evk/Kconfig.mimxrt1010_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2019, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1010_EVK + select SOC_PART_NUMBER_MIMXRT1011DAE5A diff --git a/boards/arm/mimxrt1010_evk/board.cmake b/boards/nxp/mimxrt1010_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1010_evk/board.cmake rename to boards/nxp/mimxrt1010_evk/board.cmake diff --git a/boards/nxp/mimxrt1010_evk/board.yml b/boards/nxp/mimxrt1010_evk/board.yml new file mode 100644 index 00000000000..8c5dd6f1d75 --- /dev/null +++ b/boards/nxp/mimxrt1010_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1010_evk + vendor: nxp + socs: + - name: mimxrt1011 diff --git a/boards/arm/mimxrt1010_evk/doc/index.rst b/boards/nxp/mimxrt1010_evk/doc/index.rst similarity index 100% rename from boards/arm/mimxrt1010_evk/doc/index.rst rename to boards/nxp/mimxrt1010_evk/doc/index.rst diff --git a/boards/arm/mimxrt1010_evk/doc/mimxrt1010_evk.jpg b/boards/nxp/mimxrt1010_evk/doc/mimxrt1010_evk.jpg similarity index 100% rename from boards/arm/mimxrt1010_evk/doc/mimxrt1010_evk.jpg rename to boards/nxp/mimxrt1010_evk/doc/mimxrt1010_evk.jpg diff --git a/boards/arm/mimxrt1010_evk/init.c b/boards/nxp/mimxrt1010_evk/init.c similarity index 88% rename from boards/arm/mimxrt1010_evk/init.c rename to boards/nxp/mimxrt1010_evk/init.c index 1e62f4b5a6b..1fd4b67e457 100644 --- a/boards/arm/mimxrt1010_evk/init.c +++ b/boards/nxp/mimxrt1010_evk/init.c @@ -7,7 +7,7 @@ void SystemInitHook(void) { -#ifdef CONFIG_CODE_FLEXSPI +#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash))) /* AT25SF128A SPI Flash on the RT1010-EVK requires special alignment * considerations, so set the READADDROPT bit in the FlexSPI so it * will fetch more data than each AHB burst requires to meet alignment @@ -18,5 +18,5 @@ void SystemInitHook(void) * the instruction cache in very early boot. */ FLEXSPI->AHBCR |= FLEXSPI_AHBCR_READADDROPT_MASK; -#endif /* CONFIG_CODE_FLEXSPI */ +#endif } diff --git a/boards/arm/mimxrt1010_evk/mimxrt1010_evk-pinctrl.dtsi b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1010_evk/mimxrt1010_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1010_evk/mimxrt1010_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1010_evk/mimxrt1010_evk.dts b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts similarity index 100% rename from boards/arm/mimxrt1010_evk/mimxrt1010_evk.dts rename to boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts diff --git a/boards/arm/mimxrt1010_evk/mimxrt1010_evk.yaml b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml similarity index 100% rename from boards/arm/mimxrt1010_evk/mimxrt1010_evk.yaml rename to boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml diff --git a/boards/arm/mimxrt1010_evk/mimxrt1010_evk_defconfig b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig similarity index 79% rename from boards/arm/mimxrt1010_evk/mimxrt1010_evk_defconfig rename to boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig index 2e6ad98a5e7..dc0fdc31f2a 100644 --- a/boards/arm/mimxrt1010_evk/mimxrt1010_evk_defconfig +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1011=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1015_evk/CMakeLists.txt b/boards/nxp/mimxrt1015_evk/CMakeLists.txt new file mode 100644 index 00000000000..115153b462b --- /dev/null +++ b/boards/nxp/mimxrt1015_evk/CMakeLists.txt @@ -0,0 +1,32 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT DEFINED CONFIG_BOARD_MIMXRT1015_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1015-EVK, but targeting a custom board. You may need to " + "update your flash configuration data blocks") + endif() + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1015 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + set(RT1015_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1015") + zephyr_library_sources(${RT1015_BOARD_DIR}/xip/evkmimxrt1015_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1015_BOARD_DIR}/xip) + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1015_evk/Kconfig.mimxrt1015_evk b/boards/nxp/mimxrt1015_evk/Kconfig.mimxrt1015_evk new file mode 100644 index 00000000000..3685fc618b5 --- /dev/null +++ b/boards/nxp/mimxrt1015_evk/Kconfig.mimxrt1015_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2019, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1015_EVK + select SOC_PART_NUMBER_MIMXRT1015DAF5A diff --git a/boards/arm/mimxrt1015_evk/board.cmake b/boards/nxp/mimxrt1015_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1015_evk/board.cmake rename to boards/nxp/mimxrt1015_evk/board.cmake diff --git a/boards/nxp/mimxrt1015_evk/board.yml b/boards/nxp/mimxrt1015_evk/board.yml new file mode 100644 index 00000000000..5f26dc3898b --- /dev/null +++ b/boards/nxp/mimxrt1015_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1015_evk + vendor: nxp + socs: + - name: mimxrt1015 diff --git a/boards/arm/mimxrt1015_evk/doc/index.rst b/boards/nxp/mimxrt1015_evk/doc/index.rst similarity index 100% rename from boards/arm/mimxrt1015_evk/doc/index.rst rename to boards/nxp/mimxrt1015_evk/doc/index.rst diff --git a/boards/arm/mimxrt1015_evk/doc/mimxrt1015_evk.jpg b/boards/nxp/mimxrt1015_evk/doc/mimxrt1015_evk.jpg similarity index 100% rename from boards/arm/mimxrt1015_evk/doc/mimxrt1015_evk.jpg rename to boards/nxp/mimxrt1015_evk/doc/mimxrt1015_evk.jpg diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk-pinctrl.dtsi b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1015_evk/mimxrt1015_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1015_evk/mimxrt1015_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts similarity index 100% rename from boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts rename to boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk.yaml b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml similarity index 100% rename from boards/arm/mimxrt1015_evk/mimxrt1015_evk.yaml rename to boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig similarity index 79% rename from boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig rename to boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig index 3268f61aebc..dc0fdc31f2a 100644 --- a/boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig +++ b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1015=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1020_evk/CMakeLists.txt b/boards/nxp/mimxrt1020_evk/CMakeLists.txt new file mode 100644 index 00000000000..63a6d289e6d --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/CMakeLists.txt @@ -0,0 +1,44 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT DEFINED CONFIG_BOARD_MIMXRT1020_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1020-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + set(RT1020_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1020") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1020 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1020_BOARD_DIR}/xip/evkmimxrt1020_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1020_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1020 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1020_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1020_evk/Kconfig.defconfig b/boards/nxp/mimxrt1020_evk/Kconfig.defconfig new file mode 100644 index 00000000000..9c2251e2e60 --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/Kconfig.defconfig @@ -0,0 +1,24 @@ +# MIMXRT1020-EVK board + +# Copyright 2018,2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1020_EVK + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config ETH_MCUX_PHY_RESET + default y + +endif # NETWORKING + +endif # BOARD_MIMXRT1020_EVK diff --git a/boards/nxp/mimxrt1020_evk/Kconfig.mimxrt1020_evk b/boards/nxp/mimxrt1020_evk/Kconfig.mimxrt1020_evk new file mode 100644 index 00000000000..a616953d344 --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/Kconfig.mimxrt1020_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2018, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1020_EVK + select SOC_PART_NUMBER_MIMXRT1021DAG5A diff --git a/boards/arm/mimxrt1020_evk/board.cmake b/boards/nxp/mimxrt1020_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1020_evk/board.cmake rename to boards/nxp/mimxrt1020_evk/board.cmake diff --git a/boards/nxp/mimxrt1020_evk/board.yml b/boards/nxp/mimxrt1020_evk/board.yml new file mode 100644 index 00000000000..4df4def13bc --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1020_evk + vendor: nxp + socs: + - name: mimxrt1021 diff --git a/boards/arm/mimxrt1020_evk/doc/index.rst b/boards/nxp/mimxrt1020_evk/doc/index.rst similarity index 100% rename from boards/arm/mimxrt1020_evk/doc/index.rst rename to boards/nxp/mimxrt1020_evk/doc/index.rst diff --git a/boards/arm/mimxrt1020_evk/doc/mimxrt1020_evk.jpg b/boards/nxp/mimxrt1020_evk/doc/mimxrt1020_evk.jpg similarity index 100% rename from boards/arm/mimxrt1020_evk/doc/mimxrt1020_evk.jpg rename to boards/nxp/mimxrt1020_evk/doc/mimxrt1020_evk.jpg diff --git a/boards/arm/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1020_evk/mimxrt1020_evk.dts b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts similarity index 100% rename from boards/arm/mimxrt1020_evk/mimxrt1020_evk.dts rename to boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts diff --git a/boards/arm/mimxrt1020_evk/mimxrt1020_evk.yaml b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml similarity index 100% rename from boards/arm/mimxrt1020_evk/mimxrt1020_evk.yaml rename to boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml diff --git a/boards/arm/mimxrt1020_evk/mimxrt1020_evk_defconfig b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig similarity index 79% rename from boards/arm/mimxrt1020_evk/mimxrt1020_evk_defconfig rename to boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig index 3ca8b4d09f0..8af2d462809 100644 --- a/boards/arm/mimxrt1020_evk/mimxrt1020_evk_defconfig +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1021=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1024_evk/CMakeLists.txt b/boards/nxp/mimxrt1024_evk/CMakeLists.txt new file mode 100644 index 00000000000..229a396bcf6 --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/CMakeLists.txt @@ -0,0 +1,44 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT DEFINED CONFIG_BOARD_MIMXRT1024_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1024-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + set(RT1024_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1024") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1024 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1024_BOARD_DIR}/xip/evkmimxrt1024_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1024_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1024 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1024_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1024_evk/Kconfig.defconfig b/boards/nxp/mimxrt1024_evk/Kconfig.defconfig new file mode 100644 index 00000000000..f9bc8cbfe60 --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/Kconfig.defconfig @@ -0,0 +1,32 @@ +# MIMXRT1024-EVK board + +# Copyright 2020,2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1024_EVK + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config I2C_MCUX_LPI2C_BUS_RECOVERY + default y + depends on I2C_MCUX_LPI2C && PINCTRL + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_MCUX + +config ETH_MCUX_PHY_RESET + default y + +endif # ETH_MCUX + +endif # NETWORKING + +endif # BOARD_MIMXRT1024_EVK diff --git a/boards/nxp/mimxrt1024_evk/Kconfig.mimxrt1024_evk b/boards/nxp/mimxrt1024_evk/Kconfig.mimxrt1024_evk new file mode 100644 index 00000000000..e1e69dc4565 --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/Kconfig.mimxrt1024_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2020, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1024_EVK + select SOC_PART_NUMBER_MIMXRT1024DAG5A diff --git a/boards/arm/mimxrt1024_evk/board.cmake b/boards/nxp/mimxrt1024_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1024_evk/board.cmake rename to boards/nxp/mimxrt1024_evk/board.cmake diff --git a/boards/nxp/mimxrt1024_evk/board.yml b/boards/nxp/mimxrt1024_evk/board.yml new file mode 100644 index 00000000000..c9420ad2b75 --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1024_evk + vendor: nxp + socs: + - name: mimxrt1024 diff --git a/boards/arm/mimxrt1024_evk/doc/index.rst b/boards/nxp/mimxrt1024_evk/doc/index.rst similarity index 100% rename from boards/arm/mimxrt1024_evk/doc/index.rst rename to boards/nxp/mimxrt1024_evk/doc/index.rst diff --git a/boards/arm/mimxrt1024_evk/doc/mimxrt1024_evk.jpg b/boards/nxp/mimxrt1024_evk/doc/mimxrt1024_evk.jpg similarity index 100% rename from boards/arm/mimxrt1024_evk/doc/mimxrt1024_evk.jpg rename to boards/nxp/mimxrt1024_evk/doc/mimxrt1024_evk.jpg diff --git a/boards/arm/mimxrt1024_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1024_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1024_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1024_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk-pinctrl.dtsi b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1024_evk/mimxrt1024_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1024_evk/mimxrt1024_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts similarity index 100% rename from boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts rename to boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml similarity index 100% rename from boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml rename to boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig similarity index 79% rename from boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig rename to boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig index c41a65e312d..591d8071552 100644 --- a/boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1024=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1040_evk/CMakeLists.txt b/boards/nxp/mimxrt1040_evk/CMakeLists.txt new file mode 100644 index 00000000000..9fc000a98ab --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/CMakeLists.txt @@ -0,0 +1,44 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT DEFINED CONFIG_BOARD_MIMXRT1040_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1040-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + set(RT1040_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1040") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1040 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1040_BOARD_DIR}/xip/evkmimxrt1040_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1040_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1040 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1040_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1040_evk/Kconfig.defconfig b/boards/nxp/mimxrt1040_evk/Kconfig.defconfig new file mode 100644 index 00000000000..87cdb61799a --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright 2023, NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1040_EVK + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +endif # BOARD_MIMXRT1040_EVK diff --git a/boards/nxp/mimxrt1040_evk/Kconfig.mimxrt1040_evk b/boards/nxp/mimxrt1040_evk/Kconfig.mimxrt1040_evk new file mode 100644 index 00000000000..6cfd479dadc --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/Kconfig.mimxrt1040_evk @@ -0,0 +1,5 @@ +# Copyright 2023, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1040_EVK + select SOC_PART_NUMBER_MIMXRT1042XJM5B diff --git a/boards/arm/mimxrt1040_evk/board.cmake b/boards/nxp/mimxrt1040_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1040_evk/board.cmake rename to boards/nxp/mimxrt1040_evk/board.cmake diff --git a/boards/nxp/mimxrt1040_evk/board.yml b/boards/nxp/mimxrt1040_evk/board.yml new file mode 100644 index 00000000000..ded85cfce4a --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1040_evk + vendor: nxp + socs: + - name: mimxrt1042 diff --git a/boards/nxp/mimxrt1040_evk/doc/index.rst b/boards/nxp/mimxrt1040_evk/doc/index.rst new file mode 100644 index 00000000000..c2f1e1561ce --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/doc/index.rst @@ -0,0 +1,372 @@ +.. _mimxrt1040_evk: + +NXP MIMXRT1040-EVK +################## + +Overview +******** + +i.MX RT1040 crossover MCUs add additional flexibility with new packages and an +extended temperature range up to 125° C. The i.MX RT1040 MCU has a compact +9x9 mm package, as well as the 11x11 mm package that supports implementing a +2-layer PCB design. The i.MX RT1040 MCUs run on the Arm® Cortex®-M7 core at +600 MHz. + +.. image:: mimxrt1040_evk.jpg + :align: center + :alt: MIMXRT1040-EVK + +Hardware +******** + +- MIMXRT1042XJM5B MCU (600 MHz, 512 KB TCM) + +- Memory + + - 256 MBit SDRAM (Winbond W9825G6KH) + - 64 Mbit QSPI Flash (Winbond W25Q64JVSSIQ) + +- Display + + - LCD connector + - Touch connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - OpenSDA with DAPLink + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1040 SoC and MIMXRT1040-EVK board, see +these references: + +- `i.MX RT1040 Website`_ +- `i.MX RT1040 Datasheet`_ +- `i.MX RT1040 Reference Manual`_ +- `MIMXRT1040-EVK Website`_ +- `MIMXRT1040-EVK User Guide`_ +- `MIMXRT1040-EVK Design Files`_ + +External Memory +=============== + +This platform has the following external memories: + ++----------------+------------+-------------------------------------+ +| Device | Controller | Status | ++================+============+=====================================+ +| W9825G6KH | SEMC | Enabled via device configuration | +| | | data block, which sets up SEMC at | +| | | boot time | ++----------------+------------+-------------------------------------+ +| W25Q64JVSSIQ | FLEXSPI | Enabled via flash configurationn | +| | | block, which sets up FLEXSPI at | +| | | boot time. Supported for XIP only. | ++----------------+------------+-------------------------------------+ + +Supported Features +================== + +The mimxrt1040_evk board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the mimxrt1064_evk board may have additional features +already supported, which can also be re-used on this mimxrt1040_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + ``boards/arm/mimxrt1040_evk/mimxrt1040_evk_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MIMXRT1040 SoC has five pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| GPIO_AD_B0_12 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_13 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ +| WAKEUP | GPIO | SW0 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_08 | GPIO | User LD1 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | FLEXPWM1 PWM3A | PWM Output | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_14 | ADC0 IN3 | ADC0 Input | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_15 | ADC0 IN4 | ADC0 Input | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_02 | LPSPI1_SDO | SPI Output | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_03 | LPSPI1_SDI | SPI Input | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_00 | LPSPI1_SCK | SPI Clock | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_00 | LPSPI1_SCK | SPI Clock | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_00 | LPI2C1_SCL | I2C Clock | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_01 | LPI2C1_SDA | I2C Data | ++---------------+-----------------+---------------------------+ + +.. note:: + In order to use the SPI peripheral on this board, resistors R350, R346, + and R360 must be populated with zero ohm resistors. + +System Clock +============ + +The MIMXRT1040 SoC is configured to use SysTick as the system clock source, +running at 600MHz. + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1040 SoC has eight UARTs. ``LPUART1`` is configured for the console, +and the remaining UARTs are not used. + + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended) +---------------------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Check that jumpers J9 and J10 are **on** to ensure SWD signals are connected to +the OpenSDA microcontroller. Then, follow the instructions in `NXP AN13206`_ to +program a JLink based firmware to the LPC4322 based debugger on this board. + +Once the JLink based firmware is present on this board, the SOC will no longer +be powered via the USB connection to J1. Move J40 to short pins 3 and 4 in +order to use J48 for USB power, and connect another USB cable to power the SoC. +LED D16 should illuminate to indicate the board is powered, and it should now be +possible to program the SoC. + +Option 2: :ref:`jlink-external-debug-probe` +------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +The board can be programmed using the :ref:`jlink-external-debug-probe`, +provided the onboard debug circuit's SWD signals are isolated from the MCU. +To do so, ensure that jumpers J9 and J10 are **off** (they are on by default +when the board ships from the factory). The external probe's 20 pin connector +can then be connected to J2 to program the SOC. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J11 and J13 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J1. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1040_evk + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS Booting Zephyr OS build v3.3.0-rc3-66 ***** + Hello World! mimxrt1040_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1040_evk + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS Booting Zephyr OS build v3.3.0-rc3-66 ***** + Hello World! mimxrt1040_evk + +Troubleshooting +=============== + +USER_LED D8 +----------- +The MIMXRT1040-EVK board ships with the wireless module in the M.2 connector, +and with jumper J80 shorted. This causes a conflict with the USER_LED D8, +and the LED will not turn off. Samples and applications using USER_LED D8, +like blinky, require removal of J80 jumper. + +Boot Header +----------- + +If the debug probe fails to connect with the following error, it's possible +that the boot header in QSPI is invalid or corrupted. The boot header is +configured by :kconfig:option:`CONFIG_NXP_IMXRT_BOOT_HEADER`. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the QSPI with the following +steps: + +#. Set the SW4 DIP switches to OFF-OFF-OFF-ON to boot into the ROM bootloader. + +#. Reset by pressing SW1 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application. + +#. Set the SW4 DIP switches to OFF-OFF-ON-OFF to boot from QSPI. + +#. Reset by pressing SW1 + + +WiFi Module +----------- + +If the debugger fails to connect with the following error, it's possible +the M.2 WiFi module is interfering with the debug signals + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +To resolve this, you may remove the M.2 WiFi module from the board when +flashing or debugging it, or remove jumper J80. + + +.. _MIMXRT1040-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1040-evaluation-kit:MIMXRT1040-EVK + +.. _MIMXRT1040-EVK User Guide: + https://www.nxp.com/webapp/Download?colCode=MIMXRT1040-EVKUM + +.. _MIMXRT1040-EVK Design Files: + https://www.nxp.com/webapp/Download?colCode=MIMXRT1040-EVK-DESIGNFILES + +.. _i.MX RT1040 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1040-crossover-mcu-with-arm-cortex-m7-core:i.MX-RT1040 + +.. _i.MX RT1040 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1040CEC.pdf + +.. _i.MX RT1040 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT1040RM + +.. _NXP AN13206: + https://www.nxp.com/docs/en/application-note/AN13206.pdf diff --git a/boards/arm/mimxrt1040_evk/doc/mimxrt1040_evk.jpg b/boards/nxp/mimxrt1040_evk/doc/mimxrt1040_evk.jpg similarity index 100% rename from boards/arm/mimxrt1040_evk/doc/mimxrt1040_evk.jpg rename to boards/nxp/mimxrt1040_evk/doc/mimxrt1040_evk.jpg diff --git a/boards/arm/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1040_evk/mimxrt1040_evk.dts b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts similarity index 100% rename from boards/arm/mimxrt1040_evk/mimxrt1040_evk.dts rename to boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts diff --git a/boards/arm/mimxrt1040_evk/mimxrt1040_evk.yaml b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml similarity index 100% rename from boards/arm/mimxrt1040_evk/mimxrt1040_evk.yaml rename to boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig new file mode 100644 index 00000000000..5d1b150c729 --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig @@ -0,0 +1,13 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1050_evk/CMakeLists.txt b/boards/nxp/mimxrt1050_evk/CMakeLists.txt new file mode 100644 index 00000000000..597a64852cf --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/CMakeLists.txt @@ -0,0 +1,55 @@ +# +# Copyright 2017-2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if (CONFIG_DISPLAY) +message(WARNING " +CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board +") +endif() + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_HYPERFLASH_ENABLED) + set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) + elseif(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_NOR_ENABLED) + set(FLASH_CONF evkbimxrt1050_flexspi_nor_qspi_config.c) + else() + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1050-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + # Default EVK configuration uses hyperflash, so use that file + set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) + endif() + set(RT1050_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkbimxrt1050") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1050 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1050_BOARD_DIR}/xip/${FLASH_CONF}) + zephyr_library_include_directories(${RT1050_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1050 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1050_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1050_evk/Kconfig.defconfig b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig new file mode 100644 index 00000000000..bfb4a84e341 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig @@ -0,0 +1,52 @@ +# MIMXRT1050-EVK board + +# Copyright (c) 2017, NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1050_EVK + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config INPUT + default y if LVGL + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +endif # INPUT + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_MCUX + +config ETH_MCUX_PHY_RESET + default y + +endif # ETH_MCUX + +endif # NETWORKING + +if LVGL + +config LV_Z_VDB_SIZE + default 16 + +config LV_DPI_DEF + default 128 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +endif # LVGL + +endif # BOARD_MIMXRT1050_EVK diff --git a/boards/nxp/mimxrt1050_evk/Kconfig.mimxrt1050_evk b/boards/nxp/mimxrt1050_evk/Kconfig.mimxrt1050_evk new file mode 100644 index 00000000000..f146c002672 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/Kconfig.mimxrt1050_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2017, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1050_EVK + select SOC_PART_NUMBER_MIMXRT1052DVL6B diff --git a/boards/nxp/mimxrt1050_evk/board.cmake b/boards/nxp/mimxrt1050_evk/board.cmake new file mode 100644 index 00000000000..3e42ddc78fe --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/board.cmake @@ -0,0 +1,18 @@ +# +# Copyright 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +board_runner_args(jlink "--device=MCIMXRT1052") + +if("${BOARD_REVISION}" STREQUAL "qspi") + board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") + board_runner_args(pyocd "--target=mimxrt1050_quadspi") +else() + board_runner_args(pyocd "--target=mimxrt1050_hyperflash") + board_runner_args(linkserver "--device=MIMXRT1052xxxxB:EVKB-IMXRT1050") + include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/mimxrt1050_evk/board.yml b/boards/nxp/mimxrt1050_evk/board.yml new file mode 100644 index 00000000000..c1276214baa --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/board.yml @@ -0,0 +1,11 @@ +board: + name: mimxrt1050_evk + vendor: nxp + socs: + - name: mimxrt1052 + revision: + format: "custom" + default: "hyperflash" + revisions: + - name: "hyperflash" + - name: "qspi" diff --git a/boards/nxp/mimxrt1050_evk/doc/index.rst b/boards/nxp/mimxrt1050_evk/doc/index.rst new file mode 100644 index 00000000000..165f3491f2c --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/doc/index.rst @@ -0,0 +1,499 @@ +.. _mimxrt1050_evk: + +NXP MIMXRT1050-EVK +################## + +Overview +******** + +The i.MX RT1050 is a new processor family featuring NXP's advanced +implementation of the ARM Cortex-M7 Core. It provides high CPU performance and +real-time response. + +The i.MX RT1050 provides various memory interfaces, including SDRAM, Raw NAND +FLASH, NOR FLASH, SD/eMMC, Quad SPI, HyperBus and a wide range of other +interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, displays, +and camera sensors. As with other i.MX processors, i.MX RT1050 also has rich +audio and video features, including LCD display, basic 2D graphics, camera +interface, SPDIF, and I2S audio interface. + +The following document refers to the discontinued MIMXRT1050-EVK board. For the +MIMXRT1050-EVKB board, refer to `Board Revisions`_ section. + +.. image:: mimxrt1050_evk.jpg + :align: center + :alt: MIMXRT1050-EVK + +Hardware +******** + +- MIMXRT1052DVL6A MCU (600 MHz, 512 KB TCM) + +- Memory + + - 256 KB SDRAM + - 64 Mbit QSPI Flash + - 512 Mbit Hyper Flash + +- Display + + - LCD connector + - Touch connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + - USB 2.0 host connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - OpenSDA with DAPLink + +- Sensor + + - FXOS8700CQ 6-axis e-compass + - CMOS camera sensor interface + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1050 SoC and MIMXRT1050-EVK board, see +these references: + +- `i.MX RT1050 Website`_ +- `i.MX RT1050 Datasheet`_ +- `i.MX RT1050 Reference Manual`_ +- `MIMXRT1050-EVK Website`_ +- `MIMXRT1050-EVK User Guide`_ +- `MIMXRT1050-EVK Schematics`_ + +External Memory +=============== + +This platform has the following external memories: + ++--------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++====================+============+=====================================+ +| IS42S16160J | SEMC | Enabled via device configuration | +| | | data block, which sets up SEMC at | +| | | boot time | ++--------------------+------------+-------------------------------------+ +| S26KS512SDPBHI020 | FLEXSPI | Enabled via flash configurationn | +| | | block, which sets up FLEXSPI at | +| | | boot time. | ++--------------------+------------+-------------------------------------+ + +Supported Features +================== + +The mimxrt1050_evk board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the mimxrt1064_evk board may have additional features +already supported, which can also be re-used on this mimxrt1050_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | display | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| GPT | on-chip | gpt | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + ``boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MIMXRT1050 SoC has five pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_05 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | GPIO/ENET_RST | LED | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_11 | GPIO | Touch Interrupt | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_12 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_13 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_00 | LPI2C1_SCL | I2C | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_01 | LPI2C1_SDA | I2C | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_11 | ADC | ADC1 channel 0 | ++---------------+-----------------+---------------------------+ +| WAKEUP | GPIO | SW0 | ++---------------+-----------------+---------------------------+ +| GPIO_B0_00 | LCD_CLK | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_01 | LCD_ENABLE | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_02 | LCD_HSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_03 | LCD_VSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_04 | LCD_DATA00 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_05 | LCD_DATA01 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_06 | LCD_DATA02 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_07 | LCD_DATA03 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_08 | LCD_DATA04 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_09 | LCD_DATA05 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_10 | LCD_DATA06 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_11 | LCD_DATA07 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_12 | LCD_DATA08 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_13 | LCD_DATA09 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_14 | LCD_DATA10 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_15 | LCD_DATA11 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_00 | LCD_DATA12 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_01 | LCD_DATA13 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_02 | LCD_DATA14 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_03 | LCD_DATA15 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_06 | ENET_RX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_09 | ENET_TX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_10 | ENET_REF_CLK | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_11 | ENET_RX_ER | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_12 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_14 | USDHC1_VSELECT | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_40 | ENET_MDC | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_41 | ENET_MDIO | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | ENET_RST | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | ENET_INT | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_02 | 1588_EVENT2_OUT | 1588 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_03 | 1588_EVENT2_IN | 1588 | ++---------------+-----------------+---------------------------+ + +.. note:: + In order to use the SPI peripheral on this board, resistors R278, + R279, R280, and R281 must be populated with zero ohm resistors + +System Clock +============ + +The MIMXRT1050 SoC is configured to use SysTick as the system clock source, +running at 600MHz. + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1050 SoC has eight UARTs. ``LPUART1`` is configured for the console, +``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the +remaining are not used. + +USB +=== + +The RT1050 SoC has two USB OTG (USBOTG) controllers that supports both +device and host functions through its micro USB connectors. +Only USB device function is supported in Zephyr at the moment. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +Using LinkServer +---------------- + +Install the :ref:`linkserver-debug-host-tools` and make sure they are in your +search path. LinkServer works with the default CMSIS-DAP firmware included in +the on-board debugger. + +Linkserver is the default runner. You may also se the ``-r linkserver`` option +with West to use the LinkServer runner. + +.. code-block:: console + + west flash + west debug + +JLink (on-board): :ref:`opensda-jlink-onboard-debug-probe` +---------------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link MIMXRT1050-EVK-Hyperflash Firmware`_. Check that jumpers +J32 and J33 are **on** (they are on by default when boards ship from the +factory) to ensure SWD signals are connected to the OpenSDA microcontroller. + +Follow the instructions in `Enable QSPI flash support in SEGGER JLink`_ +in order to support your EVK if you have modified it to boot from QSPI NOR +flash as specified by NXP AN12108. + +External JLink :ref:`jlink-external-debug-probe` +------------------------------------------------ + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Attach a J-Link 20-pin connector to J21. Check that jumpers J32 and J33 are +**off** (they are on by default when boards ship from the factory) to ensure +SWD signals are disconnected from the OpenSDA microcontroller. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J30 and J31 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J28. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1050_evk + :goals: flash + +Open a serial terminal, reset the board (press the SW4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1050_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1050_evk + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1050_evk + +Troubleshooting +=============== + +If the debug probe fails to connect with the following error, it's possible +that the boot header in HyperFlash is invalid or corrupted. The boot header is +configured by :kconfig:option:`CONFIG_NXP_IMXRT_BOOT_HEADER`. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the HyperFlash with the following +steps: + +#. Set the SW7 DIP switches to ON-ON-ON-OFF to prevent booting from HyperFlash. + +#. Reset by pressing SW4 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application. + +#. Set the SW7 DIP switches to OFF-ON-ON-OFF to boot from HyperFlash. + +#. Reset by pressing SW4 + +Board Revisions +*************** + +The original MIMXRT1050-EVK (rev A0) board was updated with a newer +MIMXRT1050-EVKB (rev A1) board, with these major hardware differences: + +- SoC changed from MIMXRT1052DVL6\ **A** to MIMXRT1052DVL6\ **B** +- Hardware bug fixes for: power, interfaces, and memory +- Arduino headers included + +For more details, please see the following `NXP i.MXRT1050 A0 to A1 Migration Guide`_. + +Current Zephyr build supports the new MIMXRT1050-EVKB + +.. _MIMXRT1050-EVK Website: + https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK + +.. _MIMXRT1050-EVK User Guide: + https://www.nxp.com/webapp/Download?colCode=IMXRT1050EVKBHUG + +.. _MIMXRT1050-EVK Schematics: + https://www.nxp.com/webapp/Download?colCode=MIMXRT1050-EVK-DESIGNFILES + +.. _i.MX RT1050 Website: + https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1050 + +.. _i.MX RT1050 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1050CEC.pdf + +.. _i.MX RT1050 Reference Manual: + https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf + +.. _OpenSDA J-Link MIMXRT1050-EVK-Hyperflash Firmware: + https://www.segger.com/downloads/jlink/OpenSDA_MIMXRT1050-EVK-Hyperflash + +.. _NXP i.MXRT1050 A0 to A1 Migration Guide: + https://www.nxp.com/docs/en/nxp/application-notes/AN12146.pdf + +.. _Enable QSPI flash support in SEGGER JLink: + https://wiki.segger.com/i.MXRT1050#QSPI_flash + +Experimental ENET Driver +======================== + +Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new +driver with binding `nxp,enet`, which is experimental and undergoing development, but will have +enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. + +To build for this EVK with the new driver, include the experimental overlay to west build with +the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1050_evk/doc/mimxrt1050_evk.jpg b/boards/nxp/mimxrt1050_evk/doc/mimxrt1050_evk.jpg similarity index 100% rename from boards/arm/mimxrt1050_evk/doc/mimxrt1050_evk.jpg rename to boards/nxp/mimxrt1050_evk/doc/mimxrt1050_evk.jpg diff --git a/boards/arm/mimxrt1050_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1050_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1050_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1050_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk-pinctrl.dtsi b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1050_evk/mimxrt1050_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1050_evk/mimxrt1050_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts similarity index 77% rename from boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts rename to boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts index d1e8da5834b..e636fc207d5 100644 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts @@ -30,9 +30,6 @@ zephyr,dtcm = &dtcm; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; - zephyr,flash-controller = &s26ks512s0; - zephyr,flash = &s26ks512s0; - zephyr,code-partition = &slot0_partition; zephyr,display = &lcdif; }; @@ -115,64 +112,6 @@ arduino_serial: &lpuart3 { pinctrl-names = "default"; }; -&flexspi { - status = "okay"; - ahb-prefetch; - ahb-read-addr-opt; - pinctrl-0 = <&pinmux_flexspi1>; - pinctrl-names = "default"; - ahb-bufferable; - ahb-cacheable; - sck-differential-clock; - combination-mode; - rx-clock-source = <3>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; - s26ks512s0: s26ks512s@0 { - compatible = "nxp,imx-flexspi-hyperflash"; - size = ; - reg = <0>; - spi-max-frequency = <166000000>; - word-addressable; - cs-interval-unit = <1>; - cs-interval = <2>; - cs-hold-time = <0>; - cs-setup-time = <3>; - data-valid-time = <1>; - column-space = <3>; - ahb-write-wait-unit = <2>; - ahb-write-wait-interval = <20>; - status = "okay"; - erase-block-size = <4096>; - write-block-size = <16>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(256)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@40000 { - label = "image-0"; - reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; - }; - slot1_partition: partition@341000 { - label = "image-1"; - reg = <0x00341000 DT_SIZE_M(3)>; - }; - storage_partition: partition@641000 { - label = "storage"; - reg = <0x00641000 (DT_SIZE_M(57) + DT_SIZE_K(764))>; - }; - }; - }; -}; - &lcdif { status = "okay"; width = <480>; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig new file mode 100644 index 00000000000..e4f0cbedcc2 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay new file mode 100644 index 00000000000..ccce00a5628 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay @@ -0,0 +1,71 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash-controller = &s26ks512s0; + zephyr,flash = &s26ks512s0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + pinctrl-0 = <&pinmux_flexspi1>; + pinctrl-names = "default"; + ahb-bufferable; + ahb-cacheable; + sck-differential-clock; + combination-mode; + rx-clock-source = <3>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; + s26ks512s0: s26ks512s@0 { + compatible = "nxp,imx-flexspi-hyperflash"; + size = ; + reg = <0>; + spi-max-frequency = <166000000>; + word-addressable; + cs-interval-unit = <1>; + cs-interval = <2>; + cs-hold-time = <0>; + cs-setup-time = <3>; + data-valid-time = <1>; + column-space = <3>; + ahb-write-wait-unit = <2>; + ahb-write-wait-interval = <20>; + status = "okay"; + erase-block-size = <4096>; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(256)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@40000 { + label = "image-0"; + reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + }; + slot1_partition: partition@341000 { + label = "image-1"; + reg = <0x00341000 DT_SIZE_M(3)>; + }; + storage_partition: partition@641000 { + label = "storage"; + reg = <0x00641000 (DT_SIZE_M(57) + DT_SIZE_K(764))>; + }; + }; + }; +}; diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk.yaml b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml similarity index 100% rename from boards/arm/mimxrt1050_evk/mimxrt1050_evk.yaml rename to boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay new file mode 100644 index 00000000000..1fd770ec655 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash-controller = &is25wp064; + zephyr,flash = &is25wp064; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + rx-clock-source = <1>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; + is25wp064: is25wp064@0 { + compatible = "nxp,imx-flexspi-nor"; + size = <67108864>; + reg = <0>; + spi-max-frequency = <133000000>; + status = "okay"; + jedec-id = [9d 70 17]; + erase-block-size = <4096>; + write-block-size = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + }; + slot1_partition: partition@311000 { + label = "image-1"; + reg = <0x00311000 DT_SIZE_M(3)>; + }; + storage_partition: partition@611000 { + label = "storage"; + reg = <0x00611000 DT_SIZE_K(1980)>; + }; + }; + }; +}; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml new file mode 100644 index 00000000000..6476d666984 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml @@ -0,0 +1,31 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1050_evk@qspi +name: NXP MIMXRT1050-EVK-QSPI +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32768 +flash: 8192 +supported: + - arduino_gpio + - arduino_serial + - counter + - display + - dma + - gpio + - i2c + - netif:eth + - sdhc + - spi + - usb_device + - watchdog + - adc +vendor: nxp diff --git a/boards/nxp/mimxrt1050_evk/revision.cmake b/boards/nxp/mimxrt1050_evk/revision.cmake new file mode 100644 index 00000000000..3e6f006a735 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/revision.cmake @@ -0,0 +1,7 @@ +if (NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION "hyperflash") +else () + if (NOT (BOARD_REVISION STREQUAL "hyperflash") AND NOT (BOARD_REVISION STREQUAL "qspi")) + message(FATAL_ERROR "Invalid board revision, ${BOARD_REVISION}, valid revisions are: hyperflash, qspi") + endif() +endif() diff --git a/boards/nxp/mimxrt1060_evk/CMakeLists.txt b/boards/nxp/mimxrt1060_evk/CMakeLists.txt new file mode 100644 index 00000000000..29c2d6f9068 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/CMakeLists.txt @@ -0,0 +1,64 @@ +# +# Copyright 2018-2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if (CONFIG_DISPLAY) +message(WARNING " +CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board +") +endif() + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(CONFIG_BOARD_MIMXRT1060_EVKB) + set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c) + set(BOARD_NAME evkbmimxrt1060) + elseif(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_NOR_ENABLED) + set(FLASH_CONF evkmimxrt1060_flexspi_nor_config.c) + set(BOARD_NAME evkmimxrt1060) + elseif(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_HYPERFLASH_ENABLED) + # No flash configuration block exists for the RT1060 with HyperFlash in + # the SDK, but we can reuse the block for the RT1050 as both boards use + # the same HyperFlash chip + set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) + set(BOARD_NAME evkbimxrt1050) + else() + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1060-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + # Default EVK configuration uses qspi, so use that file + set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c) + set(BOARD_NAME evkbmimxrt1060) + endif() + set(RT1060_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${BOARD_NAME}") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1060 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1060_BOARD_DIR}/xip/${FLASH_CONF}) + zephyr_library_include_directories(${RT1060_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1060 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1060_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1060_evk/Kconfig.defconfig b/boards/nxp/mimxrt1060_evk/Kconfig.defconfig new file mode 100644 index 00000000000..37dc90279dd --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/Kconfig.defconfig @@ -0,0 +1,73 @@ +# MIMXRT1060-EVK board + +# Copyright 2018,2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVKB + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config INPUT + default y if LVGL + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +endif # INPUT + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_MCUX + +config ETH_MCUX_PHY_RESET + default y + +endif # ETH_MCUX + +endif # NETWORKING + +if LVGL + +# LVGL should allocate buffers equal to size of display +config LV_Z_VDB_SIZE + default 100 + +# Enable double buffering +config LV_Z_DOUBLE_VDB + default y + +# Force full refresh. This prevents memory copy associated with partial +# display refreshes, which is not necessary for the eLCDIF driver +config LV_Z_FULL_REFRESH + default y + +config LV_DPI_DEF + default 128 + +config LV_Z_BITS_PER_PIXEL + default 16 + +# Force display buffers to be aligned to cache line size (32 bytes) +config LV_Z_VDB_ALIGN + default 32 + +# Use offloaded render thread +config LV_Z_FLUSH_THREAD + default y + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +endif # LVGL + +endif # BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVKB diff --git a/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evk b/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evk new file mode 100644 index 00000000000..a636a49b251 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2018, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1060_EVK + select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evkb b/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evkb new file mode 100644 index 00000000000..d2f59c8c9cf --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evkb @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1060_EVKB + select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/nxp/mimxrt1060_evk/board.cmake b/boards/nxp/mimxrt1060_evk/board.cmake new file mode 100644 index 00000000000..722afd541f7 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/board.cmake @@ -0,0 +1,19 @@ +# +# Copyright (c) 2018, 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(pyocd "--target=mimxrt1060") +board_runner_args(jlink "--device=MIMXRT1062xxx6A") +board_runner_args(linkserver "--device=MIMXRT1062xxxxA:EVK-MIMXRT1060") + +if (("${BOARD_REVISION}" STREQUAL "qspi") OR CONFIG_BOARD_MIMXRT1060_EVKB) + board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") +elseif ("${BOARD_REVISION}" STREQUAL "hyperflash") + board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=HyperFlash") +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/mimxrt1060_evk/board.yml b/boards/nxp/mimxrt1060_evk/board.yml new file mode 100644 index 00000000000..6682fbd7228 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/board.yml @@ -0,0 +1,11 @@ +boards: + - name: mimxrt1060_evk + vendor: nxp + socs: + - name: mimxrt1062 + revision: + format: "custom" + - name: mimxrt1060_evkb + vendor: nxp + socs: + - name: mimxrt1062 diff --git a/boards/nxp/mimxrt1060_evk/doc/index.rst b/boards/nxp/mimxrt1060_evk/doc/index.rst new file mode 100644 index 00000000000..de0943ce83c --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/doc/index.rst @@ -0,0 +1,484 @@ +.. _mimxrt1060_evk: + +NXP MIMXRT1060-EVK +################## + +Overview +******** + +The i.MX RT1060 adds to the industry's first crossover +processor series and expands the i.MX RT series to three scalable families. + +The i.MX RT1060 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin +compatibility with i.MX RT1050. This series introduces additional features +ideal for real-time applications such as High-Speed GPIO, CAN FD, and +synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1060 runs on the +Arm® Cortex-M7® core up to 600 MHz. + +.. image:: mimxrt1060_evk.jpg + :align: center + :alt: MIMXRT1060-EVK + +Hardware +******** + +- MIMXRT1062DVL6A MCU (600 MHz, 1024 KB on-chip memory) + +- Memory + + - 256 Mbit SDRAM + - 64 Mbit QSPI Flash + - 512 Mbit Hyper Flash + - TF socket for SD card + +- Display + + - LCD connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + - USB 2.0 host connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - OpenSDA with DAPLink + +- Sensor + + - FXOS8700CQ 6-axis e-compass + - CMOS camera sensor interface + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1060 SoC and MIMXRT1060-EVK board, see +these references: + +- `i.MX RT1060 Website`_ +- `i.MX RT1060 Datasheet`_ +- `i.MX RT1060 Reference Manual`_ +- `MIMXRT1060-EVK Website`_ +- `MIMXRT1060-EVK User Guide`_ +- `MIMXRT1060-EVK Schematics`_ +- `MIMXRT1060-EVK Debug Firmware`_ + +External Memory +=============== + +This platform has the following external memories: + ++--------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++====================+============+=====================================+ +| IS25WP064AJBLE | SEMC | Enabled via device configuration | +| | | data block, which sets up SEMC at | +| | | boot time | ++--------------------+------------+-------------------------------------+ +| IS42S16160J | FLEXSPI | Enabled via flash configurationn | +| | | block, which sets up FLEXSPI at | +| | | boot time. | ++--------------------+------------+-------------------------------------+ + +Supported Features +================== + +The mimxrt1060_evk board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the mimxrt1064_evk board may have additional features +already supported, which can also be re-used on this mimxrt1060_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | display | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | QSPI flash | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| SAI | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| GPT | on-chip | gpt | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +``boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and I/Os +==================== + +The MIMXRT1060 SoC has five pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_05 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | GPIO/ENET_RST | LED | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_11 | GPIO | Touch Interrupt | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_12 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_13 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_00 | LPI2C1_SCL | I2C | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_01 | LPI2C1_SDA | I2C | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI | ++---------------+-----------------+---------------------------+ +| WAKEUP | GPIO | SW0 | ++---------------+-----------------+---------------------------+ +| GPIO_B0_00 | LCD_CLK | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_01 | LCD_ENABLE | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_02 | LCD_HSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_03 | LCD_VSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_04 | LCD_DATA00 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_05 | LCD_DATA01 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_06 | LCD_DATA02 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_07 | LCD_DATA03 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_08 | LCD_DATA04 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_09 | LCD_DATA05 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_10 | LCD_DATA06 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_11 | LCD_DATA07 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_12 | LCD_DATA08 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_13 | LCD_DATA09 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_14 | LCD_DATA10 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_15 | LCD_DATA11 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_00 | LCD_DATA12 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_01 | LCD_DATA13 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_02 | LCD_DATA14 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_03 | LCD_DATA15 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_06 | ENET_RX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_09 | ENET_TX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_10 | ENET_REF_CLK | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_11 | ENET_RX_ER | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_12 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_14 | USDHC1_VSELECT | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_40 | ENET_MDC | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_41 | ENET_MDIO | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | ENET_RST | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | ENET_INT | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_11 | ADC | ADC1 Channel 0 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_10 | ADC | ADC1 Channel 15 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_09 | SAI1_MCLK | I2S | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_12 | SAI1_RX | I2S | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_13 | SAI1_TX | I2S | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_14 | SAI1_TX_BCLK | I2S | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_15 | SAI1_TX_SYNC | I2S | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_02 | 1588_EVENT2_OUT | 1588 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_03 | 1588_EVENT2_IN | 1588 | ++---------------+-----------------+---------------------------+ + +.. note:: + In order to use the SPI peripheral on this board, resistors R278, R279, + R280 and R281 must be populated with zero ohm resistors. + +System Clock +============ + +The MIMXRT1060 SoC is configured to use SysTick as the system clock source, +running at 600MHz. + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + + +Serial Port +=========== + +The MIMXRT1060 SoC has eight UARTs. ``LPUART1`` is configured for the console, +``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the +remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +.. _Using LinkServer: + + 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. + 2. To update the debug firmware, please follow the instructions on `MIMXRT1060-EVK Debug Firmware` + +.. _Using J-Link RT1060: + +Using J-Link +--------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +There are two options: the onboard debug circuit can be updated with Segger +J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the +EVK. See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ or +`Using J-Link with MIMXRT1060-EVKB`_ for more details. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J45 and J46 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J41. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Using SWO +--------- +SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``. +Your SWO viewer should be configured with a CPU frequency of 132MHz, and +SWO frequency of 7500KHz. + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1060_evk + :goals: flash + +Open a serial terminal, reset the board (press the SW9 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1060_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1060_evk + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1060_evk + +Troubleshooting +=============== + +If the debug probe fails to connect with the following error, it's possible +that the boot header in QSPI flash is invalid or corrupted. The boot header is +configured by :kconfig:option:`CONFIG_NXP_IMXRT_BOOT_HEADER`. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the QSPI flash with the following +steps: + +#. Set the SW7 DIP switches to ON-OFF-ON-OFF to prevent booting from QSPI flash. + +#. Reset by pressing SW9 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application. + +#. Set the SW7 DIP switches to OFF-OFF-ON-OFF to boot from QSPI flash. + +#. Reset by pressing SW9 + +If the west flash or debug commands fail, and the command hangs while executing +runners.jlink, confirm the J-Link debug probe is configured, powered, and +connected to the EVK properly. See :ref:`Using J-Link RT1060` for more details. + +.. _MIMXRT1060-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1060-evaluation-kit:MIMXRT1060-EVKB + +.. _MIMXRT1060-EVK User Guide: + https://www.nxp.com/webapp/Download?colCode=MIMXRT10601064EKBHUG + +.. _MIMXRT1060-EVK Debug Firmware: + https://www.nxp.com/docs/en/application-note/AN13206.pdf + +.. _MIMXRT1060-EVK Schematics: + https://www.nxp.com/webapp/Download?colCode=MIMXRT1060-EVK-DESIGNFILE-A3 + +.. _i.MX RT1060 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060 + +.. _i.MX RT1060 Datasheet: + https://www.nxp.com/docs/en/nxp/data-sheets/IMXRT1060CEC.pdf + +.. _i.MX RT1060 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT1060RM + +.. _Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVK-or-MIMXRT1064-EVK/ta-p/1281149 + +.. _Using J-Link with MIMXRT1060-EVKB: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVKB/ta-p/1452717 + +Experimental ENET Driver +======================== + +Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new +driver with binding `nxp,enet`, which is experimental and undergoing development, but will have +enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. + +To build for this EVK with the new driver, include the experimental overlay to west build with +the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1060_evk/doc/mimxrt1060_evk.jpg b/boards/nxp/mimxrt1060_evk/doc/mimxrt1060_evk.jpg similarity index 100% rename from boards/arm/mimxrt1060_evk/doc/mimxrt1060_evk.jpg rename to boards/nxp/mimxrt1060_evk/doc/mimxrt1060_evk.jpg diff --git a/boards/arm/mimxrt1060_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1060_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1060_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1060_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts similarity index 82% rename from boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts rename to boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts index 42782b40454..6e90b878717 100644 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts @@ -24,9 +24,6 @@ }; chosen { - zephyr,flash-controller = &is25wp064; - zephyr,flash = &is25wp064; - zephyr,code-partition = &slot0_partition; zephyr,sram = &sdram0; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; @@ -116,52 +113,6 @@ arduino_serial: &lpuart3 { pinctrl-names = "default", "sleep"; }; -&flexspi { - status = "okay"; - pinctrl-0 = <&pinmux_flexspi1>; - pinctrl-names = "default"; - ahb-prefetch; - ahb-read-addr-opt; - rx-clock-source = <1>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; - is25wp064: is25wp064@0 { - compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; - reg = <0>; - spi-max-frequency = <133000000>; - status = "okay"; - jedec-id = [9d 70 17]; - erase-block-size = <4096>; - write-block-size = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; - }; - slot1_partition: partition@311000 { - label = "image-1"; - reg = <0x00311000 DT_SIZE_M(3)>; - }; - storage_partition: partition@611000 { - label = "storage"; - reg = <0x00611000 DT_SIZE_K(1980)>; - }; - }; - }; -}; - &lcdif { status = "okay"; width = <480>; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig new file mode 100644 index 00000000000..8af2d462809 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2018, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay new file mode 100644 index 00000000000..4d94e82f611 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2018, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash-controller = &s26ks512s0; + zephyr,flash = &s26ks512s0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + ahb-bufferable; + ahb-cacheable; + sck-differential-clock; + combination-mode; + rx-clock-source = <3>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; + s26ks512s0: s26ks512s@0 { + compatible = "nxp,imx-flexspi-hyperflash"; + size = ; + reg = <0>; + spi-max-frequency = <166000000>; + word-addressable; + cs-interval-unit = <1>; + cs-interval = <2>; + cs-hold-time = <0>; + cs-setup-time = <3>; + data-valid-time = <1>; + column-space = <3>; + ahb-write-wait-unit = <2>; + ahb-write-wait-interval = <20>; + status = "okay"; + erase-block-size = <4096>; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(256)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@40000 { + label = "image-0"; + reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + }; + slot1_partition: partition@341000 { + label = "image-1"; + reg = <0x00341000 DT_SIZE_M(3)>; + }; + storage_partition: partition@641000 { + label = "storage"; + reg = <0x00641000 (DT_SIZE_M(57) + DT_SIZE_K(764))>; + }; + }; + }; +}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml new file mode 100644 index 00000000000..93a7915e6fd --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml @@ -0,0 +1,32 @@ +# +# Copyright (c) 2018, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1060_evk@hyperflash +name: NXP MIMXRT1060-EVK-HYPERFLASH +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32768 +flash: 65536 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - counter + - display + - dma + - gpio + - i2c + - netif:eth + - sdhc + - spi + - usb_device + - watchdog +vendor: nxp diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay new file mode 100644 index 00000000000..9fddaea0c62 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay @@ -0,0 +1,59 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash-controller = &is25wp064; + zephyr,flash = &is25wp064; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + pinctrl-0 = <&pinmux_flexspi1>; + pinctrl-names = "default"; + ahb-prefetch; + ahb-read-addr-opt; + rx-clock-source = <1>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; + is25wp064: is25wp064@0 { + compatible = "nxp,imx-flexspi-nor"; + size = <67108864>; + reg = <0>; + spi-max-frequency = <133000000>; + status = "okay"; + jedec-id = [9d 70 17]; + erase-block-size = <4096>; + write-block-size = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + }; + slot1_partition: partition@311000 { + label = "image-1"; + reg = <0x00311000 DT_SIZE_M(3)>; + }; + storage_partition: partition@611000 { + label = "storage"; + reg = <0x00611000 DT_SIZE_K(1980)>; + }; + }; + }; +}; diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml similarity index 100% rename from boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml rename to boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evkb.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.dts similarity index 84% rename from boards/arm/mimxrt1060_evk/mimxrt1060_evkb.dts rename to boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.dts index 56104fe9432..506f0d0d7a7 100644 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evkb.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.dts @@ -5,6 +5,7 @@ */ #include "mimxrt1060_evk.dts" +#include "mimxrt1060_evk_mimxrt1062_qspi.overlay" /* FLEXPWM not routed to LED on this EVK */ &flexpwm2_pwm3 { diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evkb.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.yaml similarity index 100% rename from boards/arm/mimxrt1060_evk/mimxrt1060_evkb.yaml rename to boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.yaml diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb_defconfig b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb_defconfig new file mode 100644 index 00000000000..365bcc53c40 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2022, Whisper.ai +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1060_evk/revision.cmake b/boards/nxp/mimxrt1060_evk/revision.cmake new file mode 100644 index 00000000000..97a3da96ea4 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/revision.cmake @@ -0,0 +1,9 @@ +if (NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION "qspi") +else () + if (NOT (BOARD_REVISION STREQUAL "hyperflash") AND NOT (BOARD_REVISION STREQUAL "qspi")) + message(FATAL_ERROR "Invalid board revision, ${BOARD_REVISION}, valid revisions are: hyperflash, qspi") + elseif (BOARD_REVISION STREQUAL "hyperflash" AND CONFIG_BOARD_MIMXRT1060_EVKB) + message(FATAL_ERROR "hyperflash not supported on RT1060 EVKB") + endif() +endif() diff --git a/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt b/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt new file mode 100644 index 00000000000..70f8df6e741 --- /dev/null +++ b/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt @@ -0,0 +1,40 @@ +# +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2023 NXP +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(CONFIG_BOARD_MIMXRT1062_FMURT6) + # No flash configuration block exists for the RT1060 with HyperFlash in + # the SDK, but we can reuse the block for the RT1050 as FMURT6 also uses + # the same HyperFlash chip + set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) + set(BOARD_NAME evkbimxrt1050) + endif() + set(RT1062_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${BOARD_NAME}") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1050 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1062_BOARD_DIR}/xip/${FLASH_CONF}) + zephyr_library_include_directories(${RT1062_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1050 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1062_BOARD_DIR}/dcd.c) + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1062_fmurt6/Kconfig.defconfig b/boards/nxp/mimxrt1062_fmurt6/Kconfig.defconfig new file mode 100644 index 00000000000..073cd680ec0 --- /dev/null +++ b/boards/nxp/mimxrt1062_fmurt6/Kconfig.defconfig @@ -0,0 +1,22 @@ +# MIMXRT1062-FMURT6 board + +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2023 NXP + +if BOARD_MIMXRT1062_FMURT6 + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + + +endif # BOARD_MIMXRT1062_FMURT6 diff --git a/boards/nxp/mimxrt1062_fmurt6/Kconfig.mimxrt1062_fmurt6 b/boards/nxp/mimxrt1062_fmurt6/Kconfig.mimxrt1062_fmurt6 new file mode 100644 index 00000000000..852363cbbd0 --- /dev/null +++ b/boards/nxp/mimxrt1062_fmurt6/Kconfig.mimxrt1062_fmurt6 @@ -0,0 +1,5 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1062_FMURT6 + select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/arm/mimxrt1062_fmurt6/board.cmake b/boards/nxp/mimxrt1062_fmurt6/board.cmake similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/board.cmake rename to boards/nxp/mimxrt1062_fmurt6/board.cmake diff --git a/boards/nxp/mimxrt1062_fmurt6/board.yml b/boards/nxp/mimxrt1062_fmurt6/board.yml new file mode 100644 index 00000000000..bebcb6c7954 --- /dev/null +++ b/boards/nxp/mimxrt1062_fmurt6/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1062_fmurt6 + vendor: nxp + socs: + - name: mimxrt1062 diff --git a/boards/arm/mimxrt1062_fmurt6/doc/index.rst b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/doc/index.rst rename to boards/nxp/mimxrt1062_fmurt6/doc/index.rst diff --git a/boards/arm/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg b/boards/nxp/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg rename to boards/nxp/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg diff --git a/boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6-pinctrl.dtsi b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6-pinctrl.dtsi rename to boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6-pinctrl.dtsi diff --git a/boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts rename to boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts diff --git a/boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml rename to boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml diff --git a/boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig similarity index 76% rename from boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig rename to boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig index 4efad5e51cb..3db75b19e6d 100644 --- a/boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig +++ b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig @@ -4,9 +4,6 @@ # Copyright 2023 NXP # -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1062_FMURT6=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1064_evk/CMakeLists.txt b/boards/nxp/mimxrt1064_evk/CMakeLists.txt new file mode 100644 index 00000000000..7d2f7effa10 --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/CMakeLists.txt @@ -0,0 +1,49 @@ +# +# Copyright 2018-2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if (CONFIG_DISPLAY) +message(WARNING " +CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board +") +endif() + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT DEFINED CONFIG_BOARD_MIMXRT1064_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1064-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + set(RT1064_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1064") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1064 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1064_BOARD_DIR}/xip/evkmimxrt1064_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1064_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1064 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1064_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1064_evk/Kconfig.defconfig b/boards/nxp/mimxrt1064_evk/Kconfig.defconfig new file mode 100644 index 00000000000..4ec3c9ebe2f --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/Kconfig.defconfig @@ -0,0 +1,52 @@ +# MIMXRT1064-EVK board + +# Copyright 2018,2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1064_EVK + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config INPUT + default y if LVGL + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +endif # INPUT + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_MCUX + +config ETH_MCUX_PHY_RESET + default y + +endif # ETH_MCUX + +endif # NETWORKING + +if LVGL + +config LV_Z_VDB_SIZE + default 16 + +config LV_DPI_DEF + default 128 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +endif # LVGL + +endif # BOARD_MIMXRT1064_EVK diff --git a/boards/nxp/mimxrt1064_evk/Kconfig.mimxrt1064_evk b/boards/nxp/mimxrt1064_evk/Kconfig.mimxrt1064_evk new file mode 100644 index 00000000000..719b5428740 --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/Kconfig.mimxrt1064_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2018, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1064_EVK + select SOC_PART_NUMBER_MIMXRT1064DVL6A diff --git a/boards/arm/mimxrt1064_evk/board.cmake b/boards/nxp/mimxrt1064_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1064_evk/board.cmake rename to boards/nxp/mimxrt1064_evk/board.cmake diff --git a/boards/nxp/mimxrt1064_evk/board.yml b/boards/nxp/mimxrt1064_evk/board.yml new file mode 100644 index 00000000000..b3116560663 --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1064_evk + vendor: nxp + socs: + - name: mimxrt1064 diff --git a/boards/nxp/mimxrt1064_evk/doc/index.rst b/boards/nxp/mimxrt1064_evk/doc/index.rst new file mode 100644 index 00000000000..38d284f1c47 --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/doc/index.rst @@ -0,0 +1,477 @@ +.. _mimxrt1064_evk: + +NXP MIMXRT1064-EVK +################## + +Overview +******** + +The i.MX RT1064 adds to the industry's first crossover +processor series and expands the i.MX RT series to three scalable families. +The i.MX RT1064 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin +compatibility with i.MX RT1050. This series introduces additional features +ideal for real-time applications such as High-Speed GPIO, CAN FD, and +synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1064 runs on the +Arm® Cortex-M7® core up to 600 MHz. + +.. image:: mimxrt1064_evk.jpg + :align: center + :alt: MIMXRT1064-EVK + +Hardware +******** + +- MIMXRT1064DVL6A MCU (600 MHz, 1024 KB on-chip memory, 4096KB on-chip QSPI + flash) + +- Memory + + - 256 Mbit SDRAM + - 64 Mbit QSPI Flash + - 512 Mbit Hyper Flash + - TF socket for SD card + +- Display + + - LCD connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + - USB 2.0 host connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - OpenSDA with DAPLink + +- Sensor + + - FXOS8700CQ 6-axis e-compass + - CMOS camera sensor interface + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1064 SoC and MIMXRT1064-EVK board, see +these references: + +- `i.MX RT1064 Website`_ +- `i.MX RT1064 Datasheet`_ +- `i.MX RT1064 Reference Manual`_ +- `MIMXRT1064-EVK Website`_ +- `MIMXRT1064-EVK Quick Reference Guide`_ +- `MIMXRT1064-EVK User Guide`_ +- `MIMXRT1064-EVK Schematics`_ +- `MIMXRT1064-EVK Debug Firmware`_ + +External Memory +=============== + +This platform has the following external memories: + ++--------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++====================+============+=====================================+ +| MT48LC16M16A2 | SEMC | Enabled via device configuration | +| | | data block, which sets up SEMC at | +| | | boot time | ++--------------------+------------+-------------------------------------+ + +Supported Features +================== + +NXP considers the MIMXRT1064-EVK as the superset board for the i.MX RT10xx +family of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire RT10xx family. NXP prioritizes enabling +this board with new support for Zephyr features. The mimxrt1064_evk board +configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | display | ++-----------+------------+-------------------------------------+ +| VIDEO | on-chip | video, using CSI | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | QSPI flash | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| GPT | on-chip | gpt | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +``boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and I/Os +==================== + +The MIMXRT1064 SoC has four pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_05 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | GPIO/ENET_RST | LED/Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_11 | GPIO | Touch Interrupt | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_12 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_13 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_06 | LPUART3_TX | UART Arduino | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_07 | LPUART3_RX | UART Arduino | ++---------------+-----------------+---------------------------+ +| WAKEUP | GPIO | SW0 | ++---------------+-----------------+---------------------------+ +| GPIO_B0_00 | LCD_CLK | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_01 | LCD_ENABLE | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_02 | LCD_HSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_03 | LCD_VSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_04 | LCD_DATA00 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_05 | LCD_DATA01 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_06 | LCD_DATA02 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_07 | LCD_DATA03 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_08 | LCD_DATA04 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_09 | LCD_DATA05 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_10 | LCD_DATA06 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_11 | LCD_DATA07 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_12 | LCD_DATA08 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_13 | LCD_DATA09 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_14 | LCD_DATA10 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_15 | LCD_DATA11 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_00 | LCD_DATA12 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_01 | LCD_DATA13 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_02 | LCD_DATA14 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_03 | LCD_DATA15 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_06 | ENET_RX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_09 | ENET_TX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_10 | ENET_REF_CLK | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_11 | ENET_RX_ER | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_12 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_14 | USDHC1_VSELECT | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_40 | ENET_MDC | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_41 | ENET_MDIO | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | ENET_RST | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | ENET_INT | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_05 | FLEXSPIA_DQS | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_06 | FLEXSPIA_SS0_B | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_07 | FLEXSPIA_SCLK | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_08 | FLEXSPIA_DATA00 | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_09 | FLEXSPIA_DATA01 | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_10 | FLEXSPIA_DATA02 | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_11 | FLEXSPIA_DATA03 | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_11 | ADC | ADC1 Channel 0 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_10 | ADC | ADC1 Channel 1 | ++---------------+-----------------+---------------------------+ + +.. note:: + In order to use the SPI peripheral on this board, resistors R278, R279, + R280 and R281 must be populated with zero ohm resistors + +System Clock +============ + +The MIMXRT1064 SoC is configured to use SysTick as the system clock source, +running at 600MHz. + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1064 SoC has eight UARTs. ``LPUART1`` is configured for the console +and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +.. note:: + When the device transitions into low power states, the debugger may be + unable to access the chip. Use caution when enabling ``CONFIG_PM``, and + if the debugger cannot flash the part, see :ref:`Troubleshooting RT1064` + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +.. _Using LinkServer: + + 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. + 2. To update the debug firmware, please follow the instructions on `MIMXRT1064-EVK Debug Firmware` + +.. _Using J-Link RT1064: + +Using J-Link +--------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +There are two options: the onboard debug circuit can be updated with Segger +J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the +EVK. See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ for more +details. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J45 and J46 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J41. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Using SWO +--------- +SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``. +Your SWO viewer should be configured with a CPU frequency of 132MHz, and +SWO frequency of 7500KHz. + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1064_evk + :goals: flash + +Open a serial terminal, reset the board (press the SW9 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1064_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1064_evk + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1064_evk + + +.. _Troubleshooting RT1064: + +Troubleshooting +=============== + +If the debug probe fails to connect with the following error, it's possible +that the boot header in QSPI flash is invalid or corrupted. The boot header is +configured by :kconfig:option:`CONFIG_NXP_IMXRT_BOOT_HEADER`. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the QSPI flash with the following +steps: + +#. Set the SW7 DIP switches to ON-OFF-ON-OFF to prevent booting from QSPI flash. + +#. Reset by pressing SW9 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application. + +#. Set the SW7 DIP switches to OFF-OFF-ON-OFF to boot from QSPI flash. + +#. Reset by pressing SW9 + +If the west flash or debug commands fail, and the command hangs while executing +runners.jlink, confirm the J-Link debug probe is configured, powered, and +connected to the EVK properly. See :ref:`Using J-Link RT1064` for more +details. + +.. _MIMXRT1064-EVK Website: + https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK + +.. _MIMXRT1064-EVK Quick Reference Guide: + https://www.nxp.com/webapp/Download?colCode=IMXRT1064QSG + +.. _MIMXRT1064-EVK User Guide: + https://www.nxp.com/docs/en/data-sheet/MIMXRT10601064EKBHUG.pdf + +.. _MIMXRT1064-EVK Debug Firmware: + https://www.nxp.com/docs/en/application-note/AN13206.pdf + +.. _MIMXRT1064-EVK Schematics: + https://www.nxp.com/webapp/Download?colCode=i.MXRT160EVKDS&Parent_nodeId=1537930933174731284155&Parent_pageType=product + +.. _i.MX RT1064 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1064-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1064 + +.. _i.MX RT1064 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1064CEC.pdf + +.. _i.MX RT1064 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT1064RM + +.. _Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVK-or-MIMXRT1064-EVK/ta-p/1281149 diff --git a/boards/arm/mimxrt1064_evk/doc/mimxrt1064_evk.jpg b/boards/nxp/mimxrt1064_evk/doc/mimxrt1064_evk.jpg similarity index 100% rename from boards/arm/mimxrt1064_evk/doc/mimxrt1064_evk.jpg rename to boards/nxp/mimxrt1064_evk/doc/mimxrt1064_evk.jpg diff --git a/boards/arm/mimxrt1064_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1064_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1064_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1064_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts similarity index 100% rename from boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts rename to boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk.yaml b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml similarity index 100% rename from boards/arm/mimxrt1064_evk/mimxrt1064_evk.yaml rename to boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig similarity index 79% rename from boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig rename to boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig index 22911d8b782..8af2d462809 100644 --- a/boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig +++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1064=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1160_evk/CMakeLists.txt b/boards/nxp/mimxrt1160_evk/CMakeLists.txt new file mode 100644 index 00000000000..928a9693df7 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/CMakeLists.txt @@ -0,0 +1,44 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT ((DEFINED CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7) + OR (DEFINED CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4))) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1160-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + set(RT1160_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1160") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1160 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1160_BOARD_DIR}/xip/evkmimxrt1160_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1160_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1160 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1160_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1160_evk/Kconfig.defconfig b/boards/nxp/mimxrt1160_evk/Kconfig.defconfig new file mode 100644 index 00000000000..340878191a0 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/Kconfig.defconfig @@ -0,0 +1,53 @@ +# MIMXRT1160-EVK board + +# Copyright 2021,2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1160_EVK + +# Only use DCD when booting primary core (M7) +config DEVICE_CONFIGURATION_DATA + default y if CPU_CORTEX_M7 + +config NXP_IMX_EXTERNAL_SDRAM + default y if CPU_CORTEX_M7 + +if SECOND_CORE_MCUX && BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 + +config BUILD_OUTPUT_INFO_HEADER + default y + +DT_CHOSEN_IMAGE_M4 = nxp,m4-partition + +# Adjust the offset of the output image if building for RT11xx SOC +config BUILD_OUTPUT_ADJUST_LMA + default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \ + $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \ + $(dt_node_reg_addr_hex,/soc/ocram@20200000)" + +endif + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 240000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 && CORTEX_M_SYSTICK + default 600000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 && CORTEX_M_SYSTICK + +if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 + default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 +endchoice + +endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +if NETWORKING + +config NET_L2_ETHERNET + default y if CPU_CORTEX_M7 # No cache memory support is required for driver + +config ETH_MCUX_PHY_RESET + default y + +endif # NETWORKING + +endif # BOARD_MIMXRT1160_EVK diff --git a/boards/nxp/mimxrt1160_evk/Kconfig.mimxrt1160_evk b/boards/nxp/mimxrt1160_evk/Kconfig.mimxrt1160_evk new file mode 100644 index 00000000000..7a58b49cbbc --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/Kconfig.mimxrt1160_evk @@ -0,0 +1,10 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_MIMXRT1160_EVK + select SOC_PART_NUMBER_MIMXRT1166DVM6A + select SOC_MIMXRT1166_CM7 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 + select SOC_MIMXRT1166_CM4 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 diff --git a/boards/arm/mimxrt1160_evk/board.cmake b/boards/nxp/mimxrt1160_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1160_evk/board.cmake rename to boards/nxp/mimxrt1160_evk/board.cmake diff --git a/boards/nxp/mimxrt1160_evk/board.yml b/boards/nxp/mimxrt1160_evk/board.yml new file mode 100644 index 00000000000..4fe56f8d256 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1160_evk + vendor: nxp + socs: + - name: mimxrt1166 diff --git a/boards/nxp/mimxrt1160_evk/doc/index.rst b/boards/nxp/mimxrt1160_evk/doc/index.rst new file mode 100644 index 00000000000..501182df322 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/doc/index.rst @@ -0,0 +1,366 @@ +.. _mimxrt1160_evk: + +NXP MIMXRT1160-EVK +################## + +Overview +******** + +The dual core i.MX RT1160 runs on the Cortex-M7 core at 600 MHz and on the +Cortex-M4 at 240 MHz. The i.MX RT1160 MCU offers support over a wide +temperature range and is qualified for consumer, industrial and automotive +markets. + +.. image:: mimxrt1160_evk.jpg + :align: center + :alt: MIMXRT1160-EVK + +Hardware +******** + +- MIMXRT1166DVM6A MCU + + - 600MHz Cortex-M7 & 240Mhz Cortex-M4 + - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 + +- Memory + + - 512 Mbit SDRAM + - 128 Mbit QSPI Flash + - 512 Mbit Octal Flash + - TF socket for SD card + +- Display + + - MIPI LCD connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + - 10/100/1000 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + - USB 2.0 host connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - OpenSDA with DAPLink + +- Sensor + + - MIPI camera sensor connector + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1160 SoC and MIMXRT1160-EVK board, see +these references: + +- `i.MX RT1160 Website`_ +- `i.MX RT1160 Datasheet`_ +- `i.MX RT1160 Reference Manual`_ +- `MIMXRT1160-EVK Website`_ +- `MIMXRT1160-EVK Board Hardware User's Guide`_ + +External Memory +=============== + +This platform has the following external memories: + ++--------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++====================+============+=====================================+ +| W9825G6KH | SEMC | Enabled via device configuration | +| | | data block, which sets up SEMC at | +| | | boot time | ++--------------------+------------+-------------------------------------+ +| IS25WP128 | FLEXSPI | Enabled via flash configurationn | +| | | block, which sets up FLEXSPI at | +| | | boot time. | ++--------------------+------------+-------------------------------------+ + +Supported Features +================== + +The mimxrt1160_evk board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`mimxrt1170_evk` , which is the superset board in NXP's i.MX RT11xx family. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the mimxrt1170_evk board may have additional features +already supported, which can also be re-used on this mimxrt1160_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | flexcan | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| GPT | on-chip | gpt | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB Device | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| CAAM RNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig` + +Other hardware features are not currently supported by the port. + + +Connections and I/Os +==================== + +The MIMXRT1160 SoC has six pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| WAKEUP | GPIO | SW7 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_04 | GPIO | LED | ++---------------+-----------------+---------------------------+ +| GPIO_AD_24 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_25 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_LPSR_00 | CAN3_TX | flexcan | ++---------------+-----------------+---------------------------+ +| GPIO_LPSR_01 | CAN3_RX | flexcan | ++---------------+-----------------+---------------------------+ +| GPIO_AD_29 | SPI1_CS0 | spi | ++---------------+-----------------+---------------------------+ +| GPIO_AD_28 | SPI1_CLK | spi | ++---------------+-----------------+---------------------------+ +| GPIO_AD_30 | SPI1_SDO | spi | ++---------------+-----------------+---------------------------+ +| GPIO_AD_31 | SPI1_SDI | spi | ++---------------+-----------------+---------------------------+ +| GPIO_AD_08 | LPI2C1_SCL | i2c | ++---------------+-----------------+---------------------------+ +| GPIO_AD_09 | LPI2C1_SDA | i2c | ++---------------+-----------------+---------------------------+ +| GPIO_LPSR_05 | LPI2C5_SCL | i2c | ++---------------+-----------------+---------------------------+ +| GPIO_LPSR_04 | LPI2C5_SDA | i2c | ++---------------+-----------------+---------------------------+ +| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm | ++---------------+-----------------+---------------------------+ + + +Dual Core samples +***************** + ++-----------+------------------+----------------------------+ +| Core | Boot Address | Comment | ++===========+==================+============================+ +| Cortex M7 | 0x30000000[630K] | primary core | ++-----------+------------------+----------------------------+ +| Cortex M4 | 0x20020000[96k] | boots from OCRAM | ++-----------+------------------+----------------------------+ + ++----------+------------------+-----------------------+ +| Memory | Address[Size] | Comment | ++==========+==================+=======================+ +| flexspi1 | 0x30000000[16M] | Cortex M7 flash | ++----------+------------------+-----------------------+ +| sdram0 | 0x80030000[64M] | Cortex M7 ram | ++----------+------------------+-----------------------+ +| ocram | 0x20020000[512K] | Cortex M4 "flash" | ++----------+------------------+-----------------------+ +| sram1 | 0x20000000[128K] | Cortex M4 ram | ++----------+------------------+-----------------------+ +| ocram2 | 0x200C0000[512K] | Mailbox/shared memory | ++----------+------------------+-----------------------+ + +Only the first 16K of ocram2 has the correct MPU region attributes set to be +used as shared memory + +System Clock +============ + +The MIMXRT1160 SoC is configured to use SysTick as the system clock source, +running at 600MHz. When targeting the M4 core, SysTick will also be used, +running at 240MHz + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1160 SoC has 12 UARTs. One is configured for the console and the +remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Building a Dual-Core Image +========================== +Dual core samples load the M4 core image from flash into the shared ``ocram`` +region. The M7 core then sets the M4 boot address to this region. The only +sample currently enabled for dual core builds is the ``openamp`` sample. +To flash a dual core sample, the M4 image must be flashed first, so that it is +written to flash. Then, the M7 image must be flashed. The openamp sysbuild +sample will do this automatically by setting the image order. + +The secondary core can be debugged normally in single core builds +(where the target is ``mimxrt1160_evk/mimxrt1166/cm4``). For dual core builds, the +secondary core should be placed into a loop, then a debugger can be attached +(see `AN13264`_, section 4.2.3 for more information) + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +.. _Using J-Link RT1160: + +Using J-Link +--------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +There are two options: the onboard debug circuit can be updated with Segger +J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the +EVK. See `Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK`_ for more details. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J5 and J8 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J11. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +Before power on the board, make sure SW1 is set to 0001b + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1160_evk/mimxrt1166/cm7 + :goals: flash + +Power off the board, and change SW1 to 0010b. Then power on the board and +open a serial terminal, reset the board (press the SW4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.6.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1160_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1160_evk/mimxrt1166/cm7 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.4.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1160_evk + +.. _MIMXRT1160-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1160-evaluation-kit:MIMXRT1160-EVK + +.. _MIMXRT1160-EVK Board Hardware User's Guide: + https://www.nxp.com/webapp/Download?colCode=UM11617 + +.. _i.MX RT1160 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1160-crossover-mcu-family-high-performance-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1160 + +.. _i.MX RT1160 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1160CEC.pdf + +.. _i.MX RT1160 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT1160RM + +.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760 + +.. _AN13264: + https://www.nxp.com/docs/en/application-note/AN13264.pdf + +Experimental ENET Driver +======================== + +Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new +driver with binding `nxp,enet`, which is experimental and undergoing development, but will have +enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. + +To build for this EVK with the new driver, include the experimental overlay to west build with +the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1160_evk/doc/mimxrt1160_evk.jpg b/boards/nxp/mimxrt1160_evk/doc/mimxrt1160_evk.jpg similarity index 100% rename from boards/arm/mimxrt1160_evk/doc/mimxrt1160_evk.jpg rename to boards/nxp/mimxrt1160_evk/doc/mimxrt1160_evk.jpg diff --git a/boards/arm/mimxrt1160_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1160_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1160_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1160_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi similarity index 100% rename from boards/arm/mimxrt1160_evk/mimxrt1160_evk.dtsi rename to boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts similarity index 100% rename from boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts rename to boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml new file mode 100644 index 00000000000..400e501406f --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml @@ -0,0 +1,23 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1160_evk/mimxrt1166/cm4 +name: NXP MIMXRT1160-EVK CM4 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 128 +supported: + - dma + - i2c + - gpio + - pwm + - uart +vendor: nxp diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig new file mode 100644 index 00000000000..5139427b850 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig @@ -0,0 +1,13 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts similarity index 100% rename from boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts rename to boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml new file mode 100644 index 00000000000..9ff9b57258d --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml @@ -0,0 +1,29 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1160_evk/mimxrt1166/cm7 +name: NXP MIMXRT1160-EVK CM7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 256 +flash: 16384 +supported: + - counter + - can + - dma + - gpio + - hwinfo + - i2c + - netif:eth + - pwm + - spi + - usb_device + - watchdog +vendor: nxp diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig new file mode 100644 index 00000000000..78f5191a154 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig @@ -0,0 +1,14 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1170_evk/CMakeLists.txt b/boards/nxp/mimxrt1170_evk/CMakeLists.txt new file mode 100644 index 00000000000..c564e77e492 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/CMakeLists.txt @@ -0,0 +1,49 @@ +# +# Copyright 2022-2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT ((DEFINED CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7) + OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM4))) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1170-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + if (${BOARD_REVISION} STREQUAL "A") + set(RT1170_BOARD_NAME "evkmimxrt1170") + elseif (${BOARD_REVISION} STREQUAL "B") + set(RT1170_BOARD_NAME "evkbmimxrt1170") + endif() + set(RT1170_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${RT1170_BOARD_NAME}") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1170 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1170_BOARD_DIR}/xip/${RT1170_BOARD_NAME}_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1170_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1170 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1170_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1170_evk/Kconfig.defconfig b/boards/nxp/mimxrt1170_evk/Kconfig.defconfig new file mode 100644 index 00000000000..395d8351794 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/Kconfig.defconfig @@ -0,0 +1,56 @@ +# MIMXRT1170-EVK board + +# Copyright 2021,2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1170_EVK + +# Only use DCD when booting primary core (M7) +config DEVICE_CONFIGURATION_DATA + default y if CPU_CORTEX_M7 + +config NXP_IMX_EXTERNAL_SDRAM + default y if CPU_CORTEX_M7 + +if SECOND_CORE_MCUX && CPU_CORTEX_M4 + +config BUILD_OUTPUT_INFO_HEADER + default y + +DT_CHOSEN_IMAGE_M4 = nxp,m4-partition + +# Adjust the offset of the output image if building for RT11xx SOC +config BUILD_OUTPUT_ADJUST_LMA + default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \ + $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \ + $(dt_node_reg_addr_hex,/soc/ocram@20200000)" + +endif + +if DISK_DRIVERS + +config IMX_USDHC_DAT3_PWR_TOGGLE + default y + +endif # DISK_DRIVERS + +if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 + default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 +endchoice + +endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +if NETWORKING + +config NET_L2_ETHERNET + default y if CPU_CORTEX_M7 # No cache memory support is required for driver + +config ETH_MCUX_PHY_RESET + default y + +endif # NETWORKING + +endif diff --git a/boards/nxp/mimxrt1170_evk/Kconfig.mimxrt1170_evk b/boards/nxp/mimxrt1170_evk/Kconfig.mimxrt1170_evk new file mode 100644 index 00000000000..c1777551076 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/Kconfig.mimxrt1170_evk @@ -0,0 +1,9 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1170_EVK + select SOC_PART_NUMBER_MIMXRT1176DVMAA + select SOC_MIMXRT1176_CM7 if BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 + select SOC_MIMXRT1176_CM4 if BOARD_MIMXRT1170_EVK_MIMXRT1176_CM4 diff --git a/boards/nxp/mimxrt1170_evk/board.cmake b/boards/nxp/mimxrt1170_evk/board.cmake new file mode 100644 index 00000000000..d1438e4a7b1 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/board.cmake @@ -0,0 +1,32 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMXRT1176_CM7 OR CONFIG_SECOND_CORE_MCUX) + board_runner_args(pyocd "--target=mimxrt1170_cm7") + board_runner_args(jlink "--device=MIMXRT1176xxxA_M7" "--reset-after-load") + + if(${BOARD_REVISION} STREQUAL "A") + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") + elseif(${BOARD_REVISION} STREQUAL "B") + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVKB") + endif() + + board_runner_args(linkserver "--core=cm7") +elseif(CONFIG_SOC_MIMXRT1176_CM4) + board_runner_args(pyocd "--target=mimxrt1170_cm4") + # Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core) + board_runner_args(jlink "--device=MIMXRT1176xxxA_M4") + if(${BOARD_REVISION} STREQUAL "A") + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") + elseif(${BOARD_REVISION} STREQUAL "B") + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVKB") + endif() + board_runner_args(linkserver "--core=cm4") +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/mimxrt1170_evk/board.yml b/boards/nxp/mimxrt1170_evk/board.yml new file mode 100644 index 00000000000..0b8e2b058e0 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/board.yml @@ -0,0 +1,11 @@ +board: + name: mimxrt1170_evk + vendor: nxp + socs: + - name: mimxrt1176 + revision: + format: "letter" + default: "A" + revisions: + - name: "A" + - name: "B" diff --git a/boards/nxp/mimxrt1170_evk/doc/index.rst b/boards/nxp/mimxrt1170_evk/doc/index.rst new file mode 100644 index 00000000000..40dffaba765 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/doc/index.rst @@ -0,0 +1,454 @@ +.. _mimxrt1170_evk: + +NXP MIMXRT1170-EVK/EVKB +####################### + +Overview +******** + +The dual core i.MX RT1170 runs on the Cortex-M7 core at 1 GHz and on the Cortex-M4 +at 400 MHz. The i.MX RT1170 MCU offers support over a wide temperature range +and is qualified for consumer, industrial and automotive markets. Zephyr +supports the initial revision of this EVK, as well as rev EVKB. + +.. image:: mimxrt1170_evk.jpg + :align: center + :alt: MIMXRT1170-EVK + +Hardware +******** + +- MIMXRT1176DVMAA MCU + + - 1GHz Cortex-M7 & 400Mhz Cortex-M4 + - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 + +- Memory + + - 512 Mbit SDRAM + - 128 Mbit QSPI Flash + - 512 Mbit Octal Flash + - 2 Gbit raw NAND flash + - 64 Mbit LPSPI flash + - TF socket for SD card + +- Display + + - MIPI LCD connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + - 10/100/1000 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + - USB 2.0 host connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - on-board debugger + +- Sensor + + - FXOS8700CQ 6-axis e-compass + - MIPI camera sensor connector + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1170 SoC and MIMXRT1170-EVK board, see +these references: + +- `i.MX RT1170 Website`_ +- `i.MX RT1170 Datasheet`_ +- `i.MX RT1170 Reference Manual`_ +- `MIMXRT1170-EVK Website`_ +- `MIMXRT1170-EVK Board Hardware User's Guide`_ + +External Memory +=============== + +This platform has the following external memories: + ++--------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++====================+============+=====================================+ +| W9825G6KH | SEMC | Enabled via device configuration | +| SDRAM | | data (DCD) block, which sets up | +| | | the SEMC at boot time | ++--------------------+------------+-------------------------------------+ +| IS25WP128 | FLEXSPI | Enabled via flash configuration | +| QSPI flash | | block (FCB), which sets up the | +| (RT1170 EVK) | | FLEXSPI at boot time. | ++--------------------+------------+-------------------------------------+ +| W25Q512NWEIQ | FLEXSPI | Enabled via flash configuration | +| QSPI flash | | block (FCB), which sets up the | +| (RT1170 EVKB) | | FLEXSPI at boot time. Supported for | +| | | XIP only. | ++--------------------+------------+-------------------------------------+ + +Supported Features +================== + +NXP considers the MIMXRT1170-EVK as the superset board for the i.MX RT11xx +family of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire RT11xx family. NXP prioritizes enabling +this board with new support for Zephyr features. Note that this table +covers two boards: the RT1170 EVK (`mimxrt1170_evk//cm7/cm4`), and +RT1170 EVKB (`mimxrt1170_evk@B//cm7/cm4`) + ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| Interface | Controller | Driver/Component | RT1170 EVK | RT1170 EVKB | ++===========+============+=====================================+=================+=================+ +| NVIC | on-chip | nested vector interrupt controller | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| SYSTICK | on-chip | systick | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| GPIO | on-chip | gpio | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| COUNTER | on-chip | gpt | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| TIMER | on-chip | gpt | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| CAN | on-chip | flexcan | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| SPI | on-chip | spi | Supported (M7) | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| I2C | on-chip | i2c | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| PWM | on-chip | pwm | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| ADC | on-chip | adc | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| UART | on-chip | serial port-polling; | Supported | Supported | +| | | serial port-interrupt; | | | +| | | serial port-async | | | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| DMA | on-chip | dma | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| WATCHDOG | on-chip | watchdog | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| ENET | on-chip | ethernet - 10/100M (ENET_QOS or | Supported (M7) | No support | +| ENET1G | | GigE not supported yet) | | | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| SAI | on-chip | i2s | Supported | No support | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| USB | on-chip | USB Device | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| HWINFO | on-chip | Unique device serial number | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| DISPLAY | on-chip | eLCDIF; MIPI-DSI. Tested with | Supported (M7) | Supported (M7) | +| | | :ref:`rk055hdmipi4m`, | | | +| | | :ref:`rk055hdmipi4ma0`, | | | +| | | and :ref:`g1120b0mipi` shields | | | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| ACMP | on-chip | analog comparator | Supported | No support | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| CAAM RNG | on-chip | entropy | Supported (M7) | No support | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| FLEXSPI | on-chip | flash programming | Supported (M7) | No support | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| SDHC | on-chip | SD host controller | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ + +The default configuration can be found in the defconfig files: +:zephyr_file:`boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig` +:zephyr_file:`boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig` + +Connections and I/Os +==================== + +The MIMXRT1170 SoC has six pairs of pinmux/gpio controllers. + ++---------------------------+----------------+------------------+ +| Name | Function | Usage | ++---------------------------+----------------+------------------+ +| WAKEUP | GPIO | SW7 | ++---------------------------+----------------+------------------+ +| GPIO_AD_04 | GPIO | LED | ++---------------------------+----------------+------------------+ +| GPIO_AD_24 | LPUART1_TX | UART Console | ++---------------------------+----------------+------------------+ +| GPIO_AD_25 | LPUART1_RX | UART Console | ++---------------------------+----------------+------------------+ +| GPIO_LPSR_00 | CAN3_TX | flexcan | ++---------------------------+----------------+------------------+ +| GPIO_LPSR_01 | CAN3_RX | flexcan | ++---------------------------+----------------+------------------+ +| GPIO_AD_29 | SPI1_CS0 | spi | ++---------------------------+----------------+------------------+ +| GPIO_AD_28 | SPI1_CLK | spi | ++---------------------------+----------------+------------------+ +| GPIO_AD_30 | SPI1_SDO | spi | ++---------------------------+----------------+------------------+ +| GPIO_AD_31 | SPI1_SDI | spi | ++---------------------------+----------------+------------------+ +| GPIO_AD_08 | LPI2C1_SCL | i2c | ++---------------------------+----------------+------------------+ +| GPIO_AD_09 | LPI2C1_SDA | i2c | ++---------------------------+----------------+------------------+ +| GPIO_LPSR_05 | LPI2C5_SCL | i2c | ++---------------------------+----------------+------------------+ +| GPIO_LPSR_04 | LPI2C5_SDA | i2c | ++---------------------------+----------------+------------------+ +| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm | ++---------------------------+----------------+------------------+ +| GPIO_AD_32 | ENET_MDC | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_AD_33 | ENET_MDIO | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_02 | ENET_TX_DATA00 | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_03 | ENET_TX_DATA01 | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_04 | ENET_TX_EN | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_05 | ENET_REF_CLK | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_06 | ENET_RX_DATA00 | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_07 | ENET_RX_DATA01 | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_08 | ENET_RX_EN | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_09 | ENET_RX_ER | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_AD_17_SAI1_MCLK | SAI_MCLK | SAI | ++---------------------------+----------------+------------------+ +| GPIO_AD_21_SAI1_TX_DATA00 | SAI1_TX_DATA | SAI | ++---------------------------+----------------+------------------+ +| GPIO_AD_22_SAI1_TX_BCLK | SAI1_TX_BCLK | SAI | ++---------------------------+----------------+------------------+ +| GPIO_AD_23_SAI1_TX_SYNC | SAI1_TX_SYNC | SAI | ++---------------------------+----------------+------------------+ +| GPIO_AD_17_SAI1_MCLK | SAI1_MCLK | SAI | ++---------------------------+----------------+------------------+ +| GPIO_AD_20_SAI1_RX_DATA00 | SAI1_RX_DATA00 | SAI | ++---------------------------+----------------+------------------+ + +Dual Core samples +***************** + ++-----------+------------------+----------------------------+ +| Core | Boot Address | Comment | ++===========+==================+============================+ +| Cortex M7 | 0x30000000[630K] | primary core | ++-----------+------------------+----------------------------+ +| Cortex M4 | 0x20020000[96k] | boots from OCRAM | ++-----------+------------------+----------------------------+ + ++----------+------------------+-----------------------+ +| Memory | Address[Size] | Comment | ++==========+==================+=======================+ +| flexspi1 | 0x30000000[16M] | Cortex M7 flash | ++----------+------------------+-----------------------+ +| sdram0 | 0x80030000[64M] | Cortex M7 ram | ++----------+------------------+-----------------------+ +| ocram | 0x20020000[512K] | Cortex M4 "flash" | ++----------+------------------+-----------------------+ +| sram1 | 0x20000000[128K] | Cortex M4 ram | ++----------+------------------+-----------------------+ +| ocram2 | 0x200C0000[512K] | Mailbox/shared memory | ++----------+------------------+-----------------------+ + +Only the first 16K of ocram2 has the correct MPU region attributes set to be +used as shared memory + +System Clock +============ + +The MIMXRT1170 SoC is configured to use SysTick as the system clock source, +running at 996MHz. When targeting the M4 core, SysTick will also be used, +running at 400MHz + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1170 SoC has 12 UARTs. One is configured for the console and the +remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Building a Dual-Core Image +========================== +Dual core samples load the M4 core image from flash into the shared ``ocram`` +region. The M7 core then sets the M4 boot address to this region. The only +sample currently enabled for dual core builds is the ``openamp`` sample. +To flash a dual core sample, the M4 image must be flashed first, so that it is +written to flash. Then, the M7 image must be flashed. The openamp sysbuild +sample will do this automatically by setting the image order. + +The secondary core can be debugged normally in single core builds +(where the target is ``mimxrt1170_evk/mimxrt1176/cm4``). For dual core builds, the +secondary core should be placed into a loop, then a debugger can be attached +(see `AN13264`_, section 4.2.3 for more information) + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. The on-board +debugger listed below works with the LinkServer runner by default, or can be +reprogrammed with JLink firmware. +- MIMXRT1170-EVKB: :ref:`mcu-link-cmsis-onboard-debug-probe` +- MIMXRT1170-EVK: :ref:`opensda-daplink-onboard-debug-probe` + +Using J-Link +------------ + +JLink is the default runner for this board. Install the +:ref:`jlink-debug-host-tools` and make sure they are in your search path. + +There are two options: the onboard debug circuit can be updated with Segger +J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the +EVK. See `Using J-Link with MIMXRT1170-EVKB`_ or +`Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK`_ for more details. + +Using LinkServer +---------------- + +Known limitations with LinkServer and these boards include: +- ``west debug`` does not yet work correctly, and the application image is not +properly written to the memory. `NXP MCUXpresso for Visual Studio Code`_ +can be used to debug Zephyr applications with LinkServer. +- ``west flash`` will not write images to non-flash locations. The flash +command only works when all data in the image is written to flash memory +regions. + +Install the :ref:`linkserver-debug-host-tools` and make sure they are in your +search path. LinkServer works with the default CMSIS-DAP firmware included in +the on-board debugger. + +Use the ``-r linkserver`` option with West to use the LinkServer runner. + +.. code-block:: console + + west flash -r linkserver + +Alternatively, pyOCD can be used to flash and debug the board by using the +``-r pyocd`` option with West. pyOCD is installed when you complete the +:ref:`gs_python_deps` step in the Getting Started Guide. The runners supported +by NXP are LinkServer and JLink. pyOCD is another potential option, but NXP +does not test or support the pyOCD runner. + +Configuring a Console +===================== + +We will use the on-board debugger +microcontroller as a usb-to-serial adapter for the serial console. The following +jumper settings are default on these boards, and are required to connect the +UART signals to the USB bridge circuit: +- MIMXRT1170-EVKB: JP2 open (default) +- MIMXRT1170-EVK: J31 and J32 shorted (default) + +Connect a USB cable from your PC to the on-board debugger USB port: +- MIMXRT1170-EVKB: J86 +- MIMXRT1170-EVK: J11 + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +Before powering the board, make sure SW1 is set to 0001b + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1170_evk/mimxrt1176/cm7 + :goals: flash + +Power off the board, and change SW1 to 0010b. Then power on the board and +open a serial terminal, reset the board (press the SW4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1170_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1170_evk/mimxrt1176/cm7 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1170_evk + +.. _MIMXRT1170-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVK + +.. _MIMXRT1170-EVK Board Hardware User's Guide: + https://www.nxp.com/webapp/Download?colCode=MIMXRT1170EVKHUG + +.. _i.MX RT1170 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1170-crossover-mcu-family-first-ghz-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1170 + +.. _i.MX RT1170 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1170CEC.pdf + +.. _i.MX RT1170 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT1170RM + +.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760 + +.. _Using J-Link with MIMXRT1170-EVKB: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1170-EVKB/ta-p/1715138 + +.. _AN13264: + https://www.nxp.com/docs/en/application-note/AN13264.pdf + +.. _NXP MCUXpresso for Visual Studio Code: + https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-for-visual-studio-code:MCUXPRESSO-VSC + +Experimental ENET Driver +======================== + +Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new +driver with binding `nxp,enet`, which is experimental and undergoing development, but will have +enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. + +To build for this EVK with the new driver, include the experimental overlay to west build with +the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1170_evk/doc/mimxrt1170_evk.jpg b/boards/nxp/mimxrt1170_evk/doc/mimxrt1170_evk.jpg similarity index 100% rename from boards/arm/mimxrt1170_evk/doc/mimxrt1170_evk.jpg rename to boards/nxp/mimxrt1170_evk/doc/mimxrt1170_evk.jpg diff --git a/boards/arm/mimxrt1170_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1170_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1170_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1170_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi similarity index 100% rename from boards/arm/mimxrt1170_evk/mimxrt1170_evk.dtsi rename to boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts similarity index 100% rename from boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts rename to boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml new file mode 100644 index 00000000000..87788b3a015 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml @@ -0,0 +1,22 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1170_evk/mimxrt1176/cm4 +name: NXP MIMXRT1170-EVK CM4 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 128 +supported: + - dma + - gpio + - i2c + - pwm +vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000..c92d197f548 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,81 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + /delete-property/ zephyr,flash-controller; + /delete-property/ zephyr,code-partition; + }; + + aliases { + /delete-property/ magn0; + /delete-property/ accel0; + }; +}; + +&flexspi { + /* RT1170 EVKB uses a different QSPI flash chip */ + /delete-node/ is25wp128@0; + status = "okay"; + reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; + w25q512nw:w25q512nw@0 { + /* IS25WP128 flash chip not currently enabled */ + compatible = "nxp,imx-flexspi-nor"; + size = ; + reg = <0>; + spi-max-frequency = <133000000>; + status = "okay"; + jedec-id = [ef 60 20]; + erase-block-size = <4096>; + write-block-size = <1>; + + /* + * Partitions are present to support dual core operation. + * as flash write is not supported, MCUBoot is not enabled. + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 0x301000>; + }; + slot1_partition: partition@321000 { + label = "image-1"; + reg = <0x00321000 0x300000>; + }; + storage_partition: partition@621000 { + label = "storage"; + reg = <0x00621000 DT_SIZE_K(1984)>; + }; + }; + }; +}; + +&lpspi1 { + dmas = <&edma_lpsr0 0 36>, <&edma_lpsr0 1 37>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +&lpi2c5 { + /* FXOS accelerometer is not present in this board */ + /delete-node/ fxos8700@1f; +}; + +/* Disable ethernet, as PHY is not supported */ +&enet { + status = "disabled"; +}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml new file mode 100644 index 00000000000..da1f36a162c --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml @@ -0,0 +1,23 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1170_evk@B/mimxrt1176/cm4 +name: NXP MIMXRT1170-EVKB CM4 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 128 +supported: + - dma + - gpio + - i2c + - spi + - pwm +vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig new file mode 100644 index 00000000000..822498def23 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig @@ -0,0 +1,13 @@ +# +# Copyright 2021,2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts similarity index 100% rename from boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts rename to boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml new file mode 100644 index 00000000000..c7e846adf6a --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml @@ -0,0 +1,31 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1170_evk/mimxrt1176/cm7 +name: NXP MIMXRT1170-EVK CM7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 256 +flash: 16384 +supported: + - adc + - counter + - can + - dma + - gpio + - hwinfo + - i2c + - mipi_dsi + - netif:eth + - pwm + - spi + - usb_device + - watchdog +vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay new file mode 100644 index 00000000000..4073b78a83e --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -0,0 +1,76 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &w25q512nw; + /delete-property/ zephyr,flash-controller; + /delete-property/ zephyr,code-partition; + }; + + aliases { + /delete-property/ magn0; + /delete-property/ accel0; + }; +}; + +&flexspi { + /* RT1170 EVKB uses a different QSPI flash chip */ + /delete-node/ is25wp128@0; + status = "okay"; + reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; + w25q512nw:w25q512nw@0 { + /* IS25WP128 flash chip not currently enabled */ + compatible = "nxp,imx-flexspi-nor"; + size = ; + reg = <0>; + spi-max-frequency = <133000000>; + status = "okay"; + jedec-id = [ef 60 20]; + erase-block-size = <4096>; + write-block-size = <1>; + + /* + * Partitions are present to support dual core operation. + * as flash write is not supported, MCUBoot is not enabled. + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 0x301000>; + }; + slot1_partition: partition@321000 { + label = "image-1"; + reg = <0x00321000 0x300000>; + }; + storage_partition: partition@621000 { + label = "storage"; + reg = <0x00621000 DT_SIZE_K(1984)>; + }; + }; + }; +}; + +&lpi2c5 { + /* FXOS accelerometer is not present in this board */ + /delete-node/ fxos8700@1f; +}; + +/* Disable ethernet, as PHY is not supported */ +&enet { + status = "disabled"; +}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml new file mode 100644 index 00000000000..5cdfdf97c87 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml @@ -0,0 +1,29 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1170_evk@B/mimxrt1176/cm7 +name: NXP MIMXRT1170-EVKB CM7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 65536 +flash: 65536 +supported: + - adc + - counter + - can + - dma + - gpio + - hwinfo + - i2c + - mipi_dsi + - spi + - usb_device + - watchdog +vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig new file mode 100644 index 00000000000..822498def23 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig @@ -0,0 +1,13 @@ +# +# Copyright 2021,2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt595_evk/CMakeLists.txt b/boards/nxp/mimxrt595_evk/CMakeLists.txt new file mode 100644 index 00000000000..f7db55d9430 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/CMakeLists.txt @@ -0,0 +1,32 @@ +# +# Copyright 2022-2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_BOARD_MIMXRT595_EVK_MIMXRT595S_CM33) + zephyr_library() + zephyr_library_sources(board.c) + zephyr_library_include_directories(.) +endif() + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + if(NOT DEFINED CONFIG_BOARD_MIMXRT595_EVK_MIMXRT595S_CM33) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT595-EVK, but targeting a custom board. You may need to " + "update your flash configuration block data") + endif() + # Include flash configuration block for R595 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN13304 for more information. + zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + set(RT595_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt595") + zephyr_library_sources(${RT595_BOARD_DIR}/flash_config/flash_config.c) + zephyr_library_include_directories(${RT595_BOARD_DIR}/flash_config) +endif() + +# Add custom linker section to relocate framebuffers to PSRAM +zephyr_linker_sources_ifdef(CONFIG_LV_Z_VBD_CUSTOM_SECTION + SECTIONS dc_ram.ld) diff --git a/boards/nxp/mimxrt595_evk/Kconfig b/boards/nxp/mimxrt595_evk/Kconfig new file mode 100644 index 00000000000..c97c859f16d --- /dev/null +++ b/boards/nxp/mimxrt595_evk/Kconfig @@ -0,0 +1,48 @@ +# Copyright 2022, NXP +# Copyright (c) 2023 Google LLC. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INIT_PRIORITY + int "Board initialization priority" + default 45 + help + Board initialization priority. + +DT_ADSP_RESET_MEM := $(dt_nodelabel_path,adsp_reset) +DT_ADSP_DATA_MEM := $(dt_nodelabel_path,adsp_data) +DT_ADSP_TEXT_MEM := $(dt_nodelabel_path,adsp_text) + +if BOARD_MIMXRT595_EVK_MIMXRT595S_F1 + +config RT595_ADSP_STACK_SIZE + hex "Boot time stack size" + default 0x1000 + help + Stack space is reserved at the end of the RT595_ADSP_DATA_MEM + region, starting at RT595_ADSP_DATA_MEM_ADDR - RT595_ADSP_STACK_SIZE + +config RT595_ADSP_RESET_MEM_ADDR + hex + default $(dt_node_reg_addr_hex,$(DT_ADSP_RESET_MEM)) + +config RT595_ADSP_RESET_MEM_SIZE + hex + default $(dt_node_reg_size_hex,$(DT_ADSP_RESET_MEM)) + +config RT595_ADSP_DATA_MEM_ADDR + hex + default $(dt_node_reg_addr_hex,$(DT_ADSP_DATA_MEM)) + +config RT595_ADSP_DATA_MEM_SIZE + hex + default $(dt_node_reg_size_hex,$(DT_ADSP_DATA_MEM)) + +config RT595_ADSP_TEXT_MEM_ADDR + hex + default $(dt_node_reg_addr_hex,$(DT_ADSP_TEXT_MEM)) + +config RT595_ADSP_TEXT_MEM_SIZE + hex + default $(dt_node_reg_size_hex,$(DT_ADSP_TEXT_MEM)) + +endif # BOARD_MIMXRT595_EVK_RT595_F1 diff --git a/boards/nxp/mimxrt595_evk/Kconfig.defconfig b/boards/nxp/mimxrt595_evk/Kconfig.defconfig new file mode 100644 index 00000000000..9813fb6bdf1 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/Kconfig.defconfig @@ -0,0 +1,39 @@ +# MIMXRT595-EVK board + +# Copyright 2022-2023, NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT595_EVK_MIMXRT595S_CM33 + +config FLASH_MCUX_FLEXSPI_MX25UM51345G + default y if FLASH + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM +endchoice + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +if DMA_MCUX_LPC + +# Memory from the heap pool is used to allocate DMA descriptors for +# channels that use multiple blocks for a DMA transfer. +# Adjust HEAP_MEM_POOL_MIN_SIZE in case you need more memory. +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 + +endif # DMA_MCUX_LPC + +# Turn on Device Level Power Management as we wish +# to reconfigure the FlexSPI pins for power savings +# when transitioning the SoC to Deep Low Power modes. +config PM_DEVICE + default y if PM + +config REGULATOR + default y if PM || POWEROFF + +endif # BOARD_MIMXRT595_EVK_MIMXRT595S_CM33 diff --git a/boards/nxp/mimxrt595_evk/Kconfig.mimxrt595_evk b/boards/nxp/mimxrt595_evk/Kconfig.mimxrt595_evk new file mode 100644 index 00000000000..eaf79c89a5d --- /dev/null +++ b/boards/nxp/mimxrt595_evk/Kconfig.mimxrt595_evk @@ -0,0 +1,10 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_MIMXRT595_EVK + select SOC_PART_NUMBER_MIMXRT595SFFOC + select SOC_MIMXRT595S_CM33 if BOARD_MIMXRT595_EVK_MIMXRT595S_CM33 + select SOC_MIMXRT595S_F1 if BOARD_MIMXRT595_EVK_MIMXRT595S_F1 diff --git a/boards/arm/mimxrt595_evk/board.c b/boards/nxp/mimxrt595_evk/board.c similarity index 100% rename from boards/arm/mimxrt595_evk/board.c rename to boards/nxp/mimxrt595_evk/board.c diff --git a/boards/arm/mimxrt595_evk/board.cmake b/boards/nxp/mimxrt595_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt595_evk/board.cmake rename to boards/nxp/mimxrt595_evk/board.cmake diff --git a/boards/arm/mimxrt595_evk/board.h b/boards/nxp/mimxrt595_evk/board.h similarity index 100% rename from boards/arm/mimxrt595_evk/board.h rename to boards/nxp/mimxrt595_evk/board.h diff --git a/boards/nxp/mimxrt595_evk/board.yml b/boards/nxp/mimxrt595_evk/board.yml new file mode 100644 index 00000000000..5982f346712 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt595_evk + vendor: nxp + socs: + - name: mimxrt595s diff --git a/boards/arm/mimxrt595_evk/dc_ram.ld b/boards/nxp/mimxrt595_evk/dc_ram.ld similarity index 100% rename from boards/arm/mimxrt595_evk/dc_ram.ld rename to boards/nxp/mimxrt595_evk/dc_ram.ld diff --git a/boards/nxp/mimxrt595_evk/doc/index.rst b/boards/nxp/mimxrt595_evk/doc/index.rst new file mode 100644 index 00000000000..5be8e0da21c --- /dev/null +++ b/boards/nxp/mimxrt595_evk/doc/index.rst @@ -0,0 +1,334 @@ +.. _mimxrt595_evk: + +NXP MIMXRT595-EVK +################## + +Overview +******** + +i.MX RT500 crossover MCUs are part of the edge computing family and are optimized +for low-power HMI applications by combining a graphics engine and a streamlined +Cadence Tensilica Fusion F1 DSP core with a next-generation Arm Cortex-M33 +core. These devices are designed to unlock the potential of display-based applications +with a secure, power-optimized embedded processor. + +i.MX RT500 MCUs provides up to 5MB of on-chip SRAM and several high-bandwidth interfaces +to access off-chip flash, including an Octal/Quad SPI interface with an on-the-fly +decryption engine. + +.. image:: mimxrt595_evk.jpg + :align: center + :alt: MIMXRT595-EVK + +Hardware +******** + +- MIMXRT595SFFOC Cortex-M33 (275 MHz) core processor with Cadence Tensilica Fusion F1 DSP +- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug only) +- USB2.0 high-speed host and device with micro USB connector and external crystal +- Octal/Quad/pSRAM external memories via FlexSPI +- 5 MB system SRAM +- Full size SD card slot (SDIO) +- On-board eMMC chip +- On-board 5 V inputs NXP PCA9420UK PMIC providing 1.2 V, 1.8 V, 3.3 V +- User LEDs +- Reset and User buttons +- MIPI-DSI connector +- Single row headers for ARDUINO signals and MikroBus connector +- FlexIO connector for MikroElektronica TFT Proto 5 inch capacitive touch display +- One motion sensor combo accelero-/magneto-meter NXP FXOS8700CQ +- Stereo audio codec with line-In/ line-Out/ and Microphone +- Pmod/host expansion connector +- NXP TFA9896 audio digital amplifier +- Support for up to eight off-board digital microphones via 12-pin header +- Two on-board digital microphones + +For more information about the MIMXRT595 SoC and MIMXRT595-EVK board, see +these references: + +- `i.MX RT595 Website`_ +- `i.MX RT595 Datasheet`_ +- `i.MX RT595 Reference Manual`_ +- `MIMXRT595-EVK Website`_ +- `MIMXRT595-EVK User Guide`_ +- `MIMXRT595-EVK Schematics`_ +- `MIMXRT595-EVK Debug Firmware`_ + +Supported Features +================== + +NXP considers the MIMXRT595-EVK as a superset board for the i.MX RT5xx +family of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire RT5xx family. NXP prioritizes enabling +this board with new support for Zephyr features. The mimxrt595_evk board +configuration supports the hardware features below. Another very similar +board is the :ref:`mimxrt685_evk`, and that board may have additional features +already supported, which can also be re-used on this mimxrt595_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| OS_TIMER | on-chip | os timer | ++-----------+------------+-------------------------------------+ +| IOCON | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CTIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | OctalSPI Flash | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| PM | on-chip | power management; uses SoC sleep, | +| | | deep sleep and deep-powerdown modes | ++-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access (works with eMMC & SD) | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | LCDIF; MIPI-DSI. Tested with | +| | | :ref:`rk055hdmipi4m`, | +| | | :ref:`rk055hdmipi4ma0`, and | +| | | :ref:`g1120b0mipi` display shields | ++-----------+------------+-------------------------------------+ +| DMIC | on-chip | dmic | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MIMXRT595 SoC has IOCON registers, which can be used to configure the +functionality of a pin. + ++---------+-----------------+----------------------------+ +| Name | Function | Usage | ++=========+=================+============================+ +| PIO0_2 | USART0 | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_1 | USART0 | USART TX | ++---------+-----------------+----------------------------+ +| PIO0_14 | GPIO | GREEN LED | ++---------+-----------------+----------------------------+ +| PIO0_25 | GPIO | SW0 | ++---------+-----------------+----------------------------+ +| PIO0_10 | GPIO | SW1 | ++---------+-----------------+----------------------------+ +| PIO4_30 | USART12 | USART TX | ++---------+-----------------+----------------------------+ +| PIO4_31 | USART12 | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_29 | I2C | I2C SCL | ++---------+-----------------+----------------------------+ +| PIO0_30 | I2C | I2C SDA | ++---------+-----------------+----------------------------+ +| PIO0_22 | GPIO | FXOS8700 TRIGGER | ++---------+-----------------+----------------------------+ +| PIO1_5 | SPI | SPI MOSI | ++---------+-----------------+----------------------------+ +| PIO1_4 | SPI | SPI MISO | ++---------+-----------------+----------------------------+ +| PIO1_3 | SPI | SPI SCK | ++---------+-----------------+----------------------------+ +| PIO1_6 | SPI | SPI SSEL | ++---------+-----------------+----------------------------+ +| PIO0_5 | SCT0 | SCT0 GPI0 | ++---------+-----------------+----------------------------+ +| PIO0_6 | SCT0 | SCT0 GPI1 | ++---------+-----------------+----------------------------+ + +System Clock +============ + +The MIMXRT595 EVK is configured to use the OS Event timer +as a source for the system clock. + +Serial Port +=========== + +The MIMXRT595 SoC has 13 FLEXCOMM interfaces for serial communication. One is +configured as USART for the console and the remaining are not used. + +Fusion F1 DSP Core +================== + +You can build a Zephyr application for the RT500 DSP core by targeting the F1 +SOC. Xtensa toolchain supporting RT500 DSP core is included in Zephyr SDK. +To build the hello_world sample for the RT500 DSP core: + +.. code-block:: shell + + $ west build -b mimxrt595_evk/mimxrt595s/f1 samples/hello_world + +For detailed instructions on how to debug DSP firmware, please refer to +this document: `Getting Started with Xplorer for EVK-MIMXRT595`_ + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the LPC-Link2. + +.. tabs:: + + .. group-tab:: LPCLink2 JLink Onboard + + + 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. + 2. To connect the SWD signals to onboard debug circuit, install jumpers JP17, JP18 and JP19, + if not already done (these jumpers are installed by default). + 3. Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program the + J-Link firmware. Please make sure you have the latest firmware for this board. + + .. group-tab:: JLink External + + + 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. + + 2. To disconnect the SWD signals from onboard debug circuit, **remove** jumpers J17, J18, + and J19 (these are installed by default). + + 3. Connect the J-Link probe to J2 10-pin header. + + See :ref:`jlink-external-debug-probe` for more information. + + .. group-tab:: Linkserver + + 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. + 2. To update the debug firmware, please follow the instructions on `MIMXRT595-EVK Debug Firmware` + +Configuring a Console +===================== + +Connect a USB cable from your PC to J40, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt595_evk/mimxrt595s/cm33 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS v2.7 *** + Hello World! mimxrt595_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt595_evk/mimxrt595s/cm33 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS v2.7 *** + Hello World! mimxrt595_evk + +Troubleshooting +=============== + +If the debug probe fails to connect with the following error, it's possible +that the image in flash is interfering and causing this issue. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the flash with the following +steps: + +#. Set the SW7 DIP switches to ON-ON-ON to prevent booting from flash. + +#. Reset by pressing SW3 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application (example "Hello World"). + +#. Set the SW5 DIP switches to OFF-OFF-ON to boot from flash. + +#. Reset by pressing SW3 + +.. _MIMXRT595-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK + +.. _MIMXRT595-EVK User Guide: + https://www.nxp.com/webapp/Download?colCode=MIMXRT595EVKHUG + +.. _MIMXRT595-EVK Debug Firmware: + https://www.nxp.com/docs/en/application-note/AN13206.pdf + +.. _MIMXRT595-EVK Schematics: + https://www.nxp.com/downloads/en/schematics/MIMXRT595-EVK-DESIGN-FILES.zip + +.. _i.MX RT595 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt500-crossover-mcu-with-arm-cortex-m33-dsp-and-gpu-cores:i.MX-RT500 + +.. _i.MX RT595 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT500EC.pdf + +.. _i.MX RT595 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT500RM + +.. _Getting Started with Xplorer for EVK-MIMXRT595: + https://www.nxp.com/docs/en/supporting-information/GSXEVKMIMXRT595.pdf diff --git a/boards/arm/mimxrt595_evk/doc/mimxrt595_evk.jpg b/boards/nxp/mimxrt595_evk/doc/mimxrt595_evk.jpg similarity index 100% rename from boards/arm/mimxrt595_evk/doc/mimxrt595_evk.jpg rename to boards/nxp/mimxrt595_evk/doc/mimxrt595_evk.jpg diff --git a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33-pinctrl.dtsi b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt595_evk/mimxrt595_evk_cm33-pinctrl.dtsi rename to boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts new file mode 100644 index 00000000000..eccf7d45365 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts @@ -0,0 +1,512 @@ +/* + * Copyright 2022-2023, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi" + + +/ { + model = "NXP MIMXRT595-EVK board"; + compatible = "nxp,mimxrt595"; + + aliases { + sw0 = &user_button_1; + sw1 = &user_button_2; + led0 = &green_led; + led1 = &blue_led; + led2 = &red_led; + usart-0 = &flexcomm0; + watchdog0 = &wwdt0; + magn0 = &fxos8700; + accel0 = &fxos8700; + sdhc0 = &usdhc0; + pwm-0 = &sc_timer; + dmic-dev = &dmic0; + }; + + chosen { + zephyr,flash-controller = &mx25um51345g; + zephyr,flash = &mx25um51345g; + zephyr,code-partition = &slot0_partition; + zephyr,sram = &sram0; + zephyr,console = &flexcomm0; + zephyr,shell-uart = &flexcomm0; + zephyr,display = &lcdif; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_1: button_0 { + label = "User SW1"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_2: button_1 { + label = "User SW2"; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&gpio1 0 0>; + label = "User LED_GREEN"; + }; + blue_led: led_2 { + gpios = <&gpio3 17 0>; + label = "User LED_BLUE"; + }; + red_led: led_3 { + gpios = <&gpio0 14 0>; + label = "User LED_RED"; + }; + }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 5 0>, /* A0 */ + <1 0 &gpio0 6 0>, /* A1 */ + <2 0 &gpio0 19 0>, /* A2 */ + <3 0 &gpio0 13 0>, /* A3 */ + <4 0 &gpio4 22 0>, /* A4 */ + <5 0 &gpio4 21 0>, /* A5 */ + <6 0 &gpio4 31 0>, /* D0 */ + <7 0 &gpio4 30 0>, /* D1 */ + <8 0 &gpio4 20 0>, /* D2 */ + <9 0 &gpio4 23 0>, /* D3 */ + <10 0 &gpio4 24 0>, /* D4 */ + <11 0 &gpio4 25 0>, /* D5 */ + <12 0 &gpio4 26 0>, /* D6 */ + <13 0 &gpio4 27 0>, /* D7 */ + <14 0 &gpio4 28 0>, /* D8 */ + <15 0 &gpio4 29 0>, /* D9 */ + <16 0 &gpio5 0 0>, /* D10 */ + <17 0 &gpio5 1 0>, /* D11 */ + <18 0 &gpio5 2 0>, /* D12 */ + <19 0 &gpio5 3 0>, /* D13 */ + <20 0 &gpio4 22 0>, /* D14 */ + <21 0 &gpio4 21 0>; /* D15 */ + }; + + /* + * This node describes the GPIO pins of the MIPI FPC interface, + * J44 on the EVK. This interface is standard to several + * NXP EVKs, and is used with several MIPI displays + * (available as zephyr shields) + */ + nxp_mipi_connector: mipi-connector { + compatible = "gpio-nexus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 12 0>, /* Pin 1, LEDK */ + <21 0 &gpio3 21 0>, /* Pin 21, RESET */ + <22 0 &gpio3 18 0>, /* Pin 22, LPTE */ + <26 0 &gpio0 30 0>, /* Pin 26, CTP_I2C SDA */ + <27 0 &gpio0 29 0>, /* Pin 27, CTP_I2C SCL */ + <28 0 &gpio4 4 0>, /* Pin 28, CTP_RST */ + <29 0 &gpio3 19 0>, /* Pin 29, CTP_INT */ + <32 0 &gpio3 15 0>, /* Pin 32, PWR_EN */ + <34 0 &gpio0 12 0>; /* Pin 34, BL_PWM */ + }; + + en_mipi_display: enable-mipi-display { + compatible = "regulator-fixed"; + regulator-name = "en_mipi_display"; + enable-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; +}; + +/* + * RT595 EVK board uses OS timer as the kernel timer + * In case we need to switch to SYSTICK timer, then + * replace &os_timer with &systick + */ +&os_timer { + status = "okay"; + wakeup-source; +}; + +&rtc { + status = "okay"; +}; + +&flexcomm0 { + compatible = "nxp,lpc-usart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm0_usart>; + pinctrl-names = "default"; + dmas = <&dma0 0>, <&dma0 1>; + dma-names = "rx", "tx"; +}; + +arduino_i2c: &flexcomm4 { + compatible = "nxp,lpc-i2c"; + status = "okay"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinmux_flexcomm4_i2c>; + pinctrl-names = "default"; + + fxos8700: fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + int1-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; + +nxp_mipi_i2c: &arduino_i2c {}; + +zephyr_mipi_dsi: &mipi_dsi {}; + +zephyr_lcdif: &lcdif {}; + + +hs_spi1: &hs_lspi1 { + compatible = "nxp,lpc-spi"; + pinctrl-0 = <&pinmux_flexcomm16_spi>; + pinctrl-names = "default"; + dmas = <&dma0 28>, <&dma0 29>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +/* I2S RX */ +i2s0: &flexcomm1 { + compatible = "nxp,lpc-i2s"; + pinctrl-0 = <&pinmux_flexcomm1_i2s>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 2>; + dma-names = "rx"; + status = "disabled"; +}; + +/* I2S TX */ +i2s1: &flexcomm3 { + compatible = "nxp,lpc-i2s"; + pinctrl-0 = <&pinmux_flexcomm3_i2s>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 7>; + dma-names = "tx"; + status = "disabled"; +}; + +arduino_serial: &flexcomm12 { + compatible = "nxp,lpc-usart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm12_usart>; + pinctrl-names = "default"; + dmas = <&dma0 34>, <&dma0 35>; + dma-names = "rx", "tx"; +}; + +/* PCA9420 PMIC */ +&pmic_i2c { + status = "okay"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinmux_pmic_i2c>; + pinctrl-names = "default"; + + pca9420: pca9420@61 { + compatible = "nxp,pca9420"; + reg = <0x61>; + nxp,enable-modesel-pins; + + pca9420_sw1: BUCK1 { + regulator-boot-on; + nxp,mode0-microvolt = <1100000>; + nxp,mode1-microvolt = <600000>; + nxp,mode2-microvolt = <900000>; + nxp,mode3-microvolt = <800000>; + }; + + pca9420_sw2: BUCK2 { + regulator-boot-on; + nxp,mode0-microvolt = <1800000>; + nxp,mode1-microvolt = <1800000>; + nxp,mode2-microvolt = <1800000>; + nxp,mode3-microvolt = <1800000>; + }; + + pca9420_ldo1: LDO1 { + regulator-boot-on; + nxp,mode0-microvolt = <1800000>; + nxp,mode1-microvolt = <1800000>; + nxp,mode2-microvolt = <1800000>; + nxp,mode3-microvolt = <1800000>; + }; + + pca9420_ldo2: LDO2 { + regulator-boot-on; + nxp,mode0-microvolt = <3300000>; + nxp,mode1-microvolt = <3300000>; + nxp,mode2-microvolt = <3300000>; + nxp,mode3-microvolt = <3300000>; + }; + }; +}; + +&lpadc0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +/* + * GPIO module interrupts are shared between all GPIO devices on this + * SOC, but Zephyr does not currently support sharing interrupts between + * devices. The user can select GPIO modules to support interrupts by + * setting the appropriate `int-source` and `interrupt` property for + * a given module. On this board, GPIO3 and GPIO4 are configured to support + * interrupts. + */ +&gpio3 { + status = "okay"; + int-source = "int-a"; + interrupts = <2 0>; +}; + +&gpio4 { + status = "okay"; + int-source = "int-b"; + interrupts = <3 0>; +}; + +&gpio5 { + status = "okay"; +}; + +&gpio6 { + status = "okay"; +}; + +&user_button_1 { + status = "okay"; +}; + +&user_button_2 { + status = "okay"; +}; + +&green_led { + status = "okay"; +}; + +&blue_led { + status = "okay"; +}; + +&red_led { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +zephyr_udc0: &usbhs { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; + +&ctimer1 { + status = "okay"; +}; + +&ctimer2 { + status = "okay"; +}; + +&ctimer3 { + status = "okay"; +}; + +&ctimer4 { + status = "okay"; +}; + +&usdhc0 { + status = "okay"; + pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + mmc { + compatible = "zephyr,mmc-disk"; + status = "okay"; + }; + pinctrl-0 = <&pinmux_usdhc>; + pinctrl-names = "default"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; +}; + +&wwdt0 { + status = "okay"; +}; + +&flexspi { + status = "okay"; + pinctrl-0 = <&pinmux_flexspi>; + pinctrl-1 = <&pinmux_flexspi_sleep>; + pinctrl-names = "default", "sleep"; + + mx25um51345g: mx25um51345g@0 { + compatible = "nxp,imx-flexspi-mx25um51345g"; + /* MX25UM51245G is 64MB, 512MBit flash part */ + size = ; + reg = <0>; + spi-max-frequency = <200000000>; + status = "okay"; + jedec-id = [c2 81 3a]; + erase-block-size = <4096>; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 DT_SIZE_K(3076)>; + }; + slot1_partition: partition@321000 { + label = "image-1"; + reg = <0x00321000 DT_SIZE_K(3072)>; + }; + storage_partition: partition@621000 { + label = "storage"; + reg = <0x00621000 DT_SIZE_M(57)>; + }; + }; + }; +}; + +&flexspi2 { + status = "okay"; + pinctrl-0 = <&pinmux_flexspi2>; + pinctrl-names = "default"; + rx-clock-source = <3>; + ahb-prefetch; + ahb-bufferable; + ahb-cacheable; + ahb-read-addr-opt; + aps6408l: aps6408l@0 { + compatible = "nxp,imx-flexspi-aps6408l"; + /* APS6408L is 8MB, 64MBit pSRAM */ + size = ; + reg = <0>; + spi-max-frequency = <198000000>; + status = "okay"; + cs-interval-unit = <1>; + cs-interval = <5>; + cs-hold-time = <3>; + cs-setup-time = <3>; + data-valid-time = <1>; + column-space = <0>; + ahb-write-wait-unit = <2>; + ahb-write-wait-interval = <0>; + }; +}; + +&sc_timer { + pinctrl-0 = <&pinmux_sctimer_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i3c0 { + pinctrl-0 = <&pinmux_i3c>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mbox { + status = "okay"; +}; + +/* Disable this node if not using USB and need another MPU region */ +&sram1 { + status = "okay"; +}; + +/* Enable smartDMA controller */ +&smartdma { + status = "okay"; +}; + +/* Add smartDMA to mipi DSI */ +&mipi_dsi { + dmas = <&smartdma>; + dma-names = "smartdma"; +}; + +&dmic0 { + status = "okay"; + pinctrl-0 = <&pinmux_dmic0>; + pinctrl-names = "default"; + use2fs; +}; + +/* Configure pdm channels 0 and 1 with gain, and cutoff settings + * appropriate for the attached MEMS microphones. + */ +&pdmc0 { + status = "okay"; + gainshift = <3>; + dc-cutoff = "155hz"; + dc-gain = <1>; +}; + +&pdmc1 { + status = "okay"; + gainshift = <3>; + dc-cutoff = "155hz"; + dc-gain = <1>; +}; + +&mrt_channel0 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml new file mode 100644 index 00000000000..532fa9519ea --- /dev/null +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml @@ -0,0 +1,32 @@ +# +# Copyright (c) 2022, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt595_evk/mimxrt595s/cm33 +name: NXP MIMXRT595-EVK +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 4608 +flash: 65536 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - counter + - dma + - gpio + - i2c + - spi + - usb_device + - watchdog + - sdhc + - pwm + - i2s + - dmic +vendor: nxp diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig new file mode 100644 index 00000000000..a25ec7156e7 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig @@ -0,0 +1,16 @@ +# +# Copyright 2022,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_PINCTRL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595.dts b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.dts similarity index 100% rename from boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595.dts rename to boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.dts diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml new file mode 100644 index 00000000000..48245feebc6 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml @@ -0,0 +1,10 @@ +identifier: mimxrt595_evk/mimxrt595s/f1 +name: i.MXRT595 Fusion F1 DSP +type: mcu +arch: xtensa +toolchain: + - zephyr +testing: + only_tags: + - kernel +vendor: nxp diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1_defconfig b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1_defconfig new file mode 100644 index 00000000000..0cb1f999e92 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1_defconfig @@ -0,0 +1,4 @@ +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n +CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY=y +CONFIG_NXP_IMXRT_BOOT_HEADER=n diff --git a/boards/arm/mimxrt595_evk/pre_dt_board.cmake b/boards/nxp/mimxrt595_evk/pre_dt_board.cmake similarity index 100% rename from boards/arm/mimxrt595_evk/pre_dt_board.cmake rename to boards/nxp/mimxrt595_evk/pre_dt_board.cmake diff --git a/boards/nxp/mimxrt685_evk/CMakeLists.txt b/boards/nxp/mimxrt685_evk/CMakeLists.txt new file mode 100644 index 00000000000..39c978f14cc --- /dev/null +++ b/boards/nxp/mimxrt685_evk/CMakeLists.txt @@ -0,0 +1,25 @@ +# +# Copyright 2020-2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(init.c) + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + if(NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT685-EVK, but targeting a custom board. You may need to " + "update your flash configuration block data") + endif() + # Include flash configuration block for R685 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN13386 for more information. + zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + set(RT685_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt685") + zephyr_library_sources(${RT685_BOARD_DIR}/flash_config/flash_config.c) + zephyr_library_include_directories(${RT685_BOARD_DIR}/flash_config) +endif() diff --git a/boards/arm/mimxrt685_evk/Kconfig b/boards/nxp/mimxrt685_evk/Kconfig similarity index 100% rename from boards/arm/mimxrt685_evk/Kconfig rename to boards/nxp/mimxrt685_evk/Kconfig diff --git a/boards/nxp/mimxrt685_evk/Kconfig.defconfig b/boards/nxp/mimxrt685_evk/Kconfig.defconfig new file mode 100644 index 00000000000..8fbc681e052 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/Kconfig.defconfig @@ -0,0 +1,29 @@ +# MIMXRT685-EVK board + +# Copyright 2020, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT685_EVK + +config NXP_IMXRT_BOOT_HEADER + default y if !BOOTLOADER_MCUBOOT + +config XTAL_SYS_CLK_HZ + default 24000000 + +config SYSOSC_SETTLING_US + default 260 + +choice FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_MODE + default FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_STR +endchoice + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM +endchoice + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +endif # BOARD_MIMXRT685_EVK diff --git a/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk b/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk new file mode 100644 index 00000000000..d87399aebd7 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk @@ -0,0 +1,5 @@ +# Copyright 2020, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT685_EVK + select SOC_PART_NUMBER_MIMXRT685SFVKB diff --git a/boards/arm/mimxrt685_evk/board.cmake b/boards/nxp/mimxrt685_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt685_evk/board.cmake rename to boards/nxp/mimxrt685_evk/board.cmake diff --git a/boards/nxp/mimxrt685_evk/board.yml b/boards/nxp/mimxrt685_evk/board.yml new file mode 100644 index 00000000000..41956acbb31 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt685_evk + vendor: nxp + socs: + - name: mimxrt685s diff --git a/boards/nxp/mimxrt685_evk/doc/index.rst b/boards/nxp/mimxrt685_evk/doc/index.rst new file mode 100644 index 00000000000..3b0357ffb02 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/doc/index.rst @@ -0,0 +1,370 @@ +.. _mimxrt685_evk: + +NXP MIMXRT685-EVK +################## + +Overview +******** + +The i.MX RT600 is a crossover MCU family optimized for 32-bit immersive audio +playback and voice user interface applications combining a high-performance +Cadence Tensilica HiFi 4 audio DSP core with a next-generation Cortex-M33 +core. The i.MX RT600 family of crossover MCUs is designed to unlock the +potential of voice-assisted end nodes with a secure, power-optimized embedded +processor. + +The i.MX RT600 family provides up to 4.5MB of on-chip SRAM and several +high-bandwidth interfaces to access off-chip flash, including an Octal/Quad SPI +interface with an on-the-fly decryption engine. + +.. image:: mimxrt685_evk.jpg + :align: center + :alt: MIMXRT685-EVK + +Hardware +******** + +- MIMXRT685SFVKB Cortex-M33 (300 MHz, 128 KB TCM) core processor with Cadence Xtensa HiFi4 DSP +- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug only) +- High speed USB port with micro A/B connector for the host or device functionality +- UART, I2C and SPI port bridging from i.MX RT685 target to USB via the on-board debug probe +- 512 MB Macronix Octal SPI Flash operating at 1.8 V +- 4.5 MB Apmemory PSRAM +- Full size SD card slot (SDIO) +- NXP PCA9420UK PMIC +- User LEDs +- Reset and User buttons +- Arduino and PMod/Host expansion connectors +- NXP FXOS8700CQ accelerometer +- Stereo audio codec with line in/out and electret microphone +- Stereo NXP TFA9894 digital amplifiers, with option for external +5V power for higher performance speakers +- Support for up to eight off-board digital microphones via 12-pin header +- Two on-board DMICS + +For more information about the MIMXRT685 SoC and MIMXRT685-EVK board, see +these references: + +- `i.MX RT685 Website`_ +- `i.MX RT685 Datasheet`_ +- `i.MX RT685 Reference Manual`_ +- `MIMXRT685-EVK Website`_ +- `MIMXRT685-EVK User Guide`_ +- `MIMXRT685-EVK Schematics`_ + +Supported Features +================== + +NXP considers the MIMXRT685-EVK as a superset board for the i.MX RT6xx +family of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire RT6xx family. NXP prioritizes enabling +this board with new support for Zephyr features. The mimxrt685_evk board +configuration supports the hardware features below. Another very similar +board is the :ref:`mimxrt595_evk`, and that board may have additional features +already supported, which can also be re-used on this mimxrt685_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| OS_TIMER | on-chip | os timer | ++-----------+------------+-------------------------------------+ +| IOCON | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | OctalSPI Flash | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CTIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + ``boards/arm/mimxrt685_evk/mimxrt685_evk_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MIMXRT685 SoC has IOCON registers, which can be used to configure the +functionality of a pin. + ++---------+-----------------+----------------------------+ +| Name | Function | Usage | ++=========+=================+============================+ +| PIO0_2 | USART | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_1 | USART | USART TX | ++---------+-----------------+----------------------------+ +| PIO0_14 | GPIO | GREEN LED | ++---------+-----------------+----------------------------+ +| PIO1_1 | GPIO | SW0 | ++---------+-----------------+----------------------------+ +| PIO0_17 | I2C | I2C SDA | ++---------+-----------------+----------------------------+ +| PIO0_18 | I2C | I2C SCL | ++---------+-----------------+----------------------------+ +| PIO1_5 | GPIO | FXOS8700 TRIGGER | ++---------+-----------------+----------------------------+ +| PIO1_5 | SPI | SPI MOSI | ++---------+-----------------+----------------------------+ +| PIO1_4 | SPI | SPI MISO | ++---------+-----------------+----------------------------+ +| PIO1_3 | SPI | SPI SCK | ++---------+-----------------+----------------------------+ +| PIO1_6 | SPI | SPI SSEL | ++---------+-----------------+----------------------------+ +| PIO0_23 | I2S | I2S DATAOUT | ++---------+-----------------+----------------------------+ +| PIO0_22 | I2S | I2S TX WS | ++---------+-----------------+----------------------------+ +| PIO0_21 | I2S | I2S TX SCK | ++---------+-----------------+----------------------------+ +| PIO0_9 | I2S | I2S DATAIN | ++---------+-----------------+----------------------------+ +| PIO0_29 | USART | USART TX | ++---------+-----------------+----------------------------+ +| PIO0_30 | USART | USART RX | ++---------+-----------------+----------------------------+ +| PIO1_11 | FLEXSPI0B_DATA0 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO1_12 | FLEXSPI0B_DATA1 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO1_13 | FLEXSPI0B_DATA2 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO1_14 | FLEXSPI0B_DATA3 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO1_29 | FLEXSPI0B_SCLK | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_12 | PIO2_12 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_17 | FLEXSPI0B_DATA4 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_18 | FLEXSPI0B_DATA5 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_19 | FLEXSPI0B_SS0_N | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_22 | FLEXSPI0B_DATA6 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_23 | FLEXSPI0B_DATA7 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO0_27 | SCT0_OUT7 | PWM | ++---------+-----------------+----------------------------+ +| PIO1_30 | SD0_CLK | SD card | ++---------+-----------------+----------------------------+ +| PIO1_31 | SD0_CMD | SD card | ++---------+-----------------+----------------------------+ +| PIO2_0 | SD0_D0 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_1 | SD0_D1 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_2 | SD0_D2 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_3 | SD0_D3 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_4 | SD0_WR_PRT | SD card | ++---------+-----------------+----------------------------+ +| PIO2_9 | SD0_CD | SD card | ++---------+-----------------+----------------------------+ +| PIO2_10 | SD0_RST | SD card | ++---------+-----------------+----------------------------+ + +System Clock +============ + +The MIMXRT685 EVK is configured to use the OS Event timer +as a source for the system clock. + +Serial Port +=========== + +The MIMXRT685 SoC has 8 FLEXCOMM interfaces for serial communication. One is +configured as USART for the console and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the LPC-Link2. + +.. tabs:: + + .. group-tab:: LinkServer CMSIS-DAP + + 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your + search path. LinkServer works with the default CMSIS-DAP firmware included in + the on-board debugger. + 2. Make sure the jumpers JP17, JP18 and JP19 are installed. + + linkserver is the default runner for this board + + .. code-block:: console + + west flash + west debug + + .. group-tab:: LPCLink2 JLink Onboard + + + 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. + 2. To connect the SWD signals to onboard debug circuit, install jumpers JP17, JP18 and JP19, + if not already done (these jumpers are installed by default). + 3. Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program the + J-Link firmware. Please make sure you have the latest firmware for this board. + + .. code-block:: console + + west flash -r jlink + west debug -r jlink + + .. group-tab:: JLink External + + + 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. + + 2. To disconnect the SWD signals from onboard debug circuit, **remove** jumpers J17, J18, + and J19 (these are installed by default). + + 3. Connect the J-Link probe to J2 10-pin header. + + See :ref:`jlink-external-debug-probe` for more information. + + .. code-block:: console + + west flash -r jlink + west debug -r jlink + +Configuring a Console +===================== + +Connect a USB cable from your PC to J16, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`linkserver-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt685_evk + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0 ***** + Hello World! mimxrt685_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`linkserver-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt685_evk + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS zephyr-v2.3.0 ***** + Hello World! mimxrt685_evk + +Troubleshooting +=============== + +If the debug probe fails to connect with the following error, it's possible +that the image in flash is interfering and causing this issue. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the flash with the following +steps: + +#. Set the SW5 DIP switches to ON-ON-ON to prevent booting from flash. + +#. Reset by pressing SW3 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application (example "Hello World"). + +#. Set the SW5 DIP switches to ON-OFF-ON to boot from flash. + +#. Reset by pressing SW3 + +.. _MIMXRT685-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK + +.. _MIMXRT685-EVK User Guide: + https://www.nxp.com/webapp/Download?colCode=UM11159 + +.. _MIMXRT685-EVK Schematics: + https://www.nxp.com/downloads/en/design-support/RT685-DESIGNFILES.zip + +.. _i.MX RT685 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt600-crossover-mcu-with-arm-cortex-m33-and-dsp-cores:i.MX-RT600 + +.. _i.MX RT685 Datasheet: + https://www.nxp.com/docs/en/data-sheet/DS-RT600.pdf + +.. _i.MX RT685 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=UM11147 diff --git a/boards/arm/mimxrt685_evk/doc/mimxrt685_evk.jpg b/boards/nxp/mimxrt685_evk/doc/mimxrt685_evk.jpg similarity index 100% rename from boards/arm/mimxrt685_evk/doc/mimxrt685_evk.jpg rename to boards/nxp/mimxrt685_evk/doc/mimxrt685_evk.jpg diff --git a/boards/arm/mimxrt685_evk/init.c b/boards/nxp/mimxrt685_evk/init.c similarity index 100% rename from boards/arm/mimxrt685_evk/init.c rename to boards/nxp/mimxrt685_evk/init.c diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33-pinctrl.dtsi b/boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt685_evk/mimxrt685_evk_cm33-pinctrl.dtsi rename to boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk.dts new file mode 100644 index 00000000000..a7df8a693ef --- /dev/null +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk.dts @@ -0,0 +1,387 @@ +/* + * Copyright (c) 2020-2023, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include + +#include "mimxrt685_evk-pinctrl.dtsi" + +/ { + model = "NXP MIMXRT685-EVK board"; + compatible = "nxp,mimxrt685"; + + aliases { + sw0 = &user_button_1; + sw1 = &user_button_2; + led0 = &green_led; + led1 = &blue_led; + led2 = &red_led; + usart-0 = &flexcomm0; + /* For pwm test suites */ + pwm-0 = &sc_timer; + pwm-led0 = &green_pwm_led; + green-pwm-led = &green_pwm_led; + blue-pwm-led = &blue_pwm_led; + red-pwm-led = &red_pwm_led; + watchdog0 = &wwdt0; + magn0 = &fxos8700; + accel0 = &fxos8700; + sdhc0 = &usdhc0; + }; + + chosen { + zephyr,flash-controller = &mx25um51345g; + zephyr,flash = &mx25um51345g; + zephyr,code-partition = &slot0_partition; + zephyr,sram = &sram0; + zephyr,console = &flexcomm0; + zephyr,shell-uart = &flexcomm0; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_1: button_0 { + label = "User SW1"; + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_2: button_1 { + label = "User SW2"; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&gpio0 14 0>; + label = "User LED_GREEN"; + }; + blue_led: led_2 { + gpios = <&gpio0 26 0>; + label = "User LED_BLUE"; + }; + red_led: led_3 { + gpios = <&gpio0 31 0>; + label = "User LED_RED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + green_pwm_led: green_pwm_led { + pwms = <&sc_timer 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "Green PWM LED"; + status = "okay"; + }; + blue_pwm_led: blue_pwm_led { + pwms = <&sc_timer 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "Blue PWM LED"; + status = "okay"; + }; + red_pwm_led: red_pwm_led { + pwms = <&sc_timer 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "Red PWM LED"; + status = "disabled"; + }; + }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 5 0>, /* A0 */ + <1 0 &gpio0 6 0>, /* A1 */ + <2 0 &gpio0 19 0>, /* A2 */ + <3 0 &gpio0 20 0>, /* A3 */ + <4 0 &gpio0 17 0>, /* A4 */ + <5 0 &gpio0 18 0>, /* A5 */ + <6 0 &gpio0 30 0>, /* D0 */ + <7 0 &gpio0 29 0>, /* D1 */ + <8 0 &gpio0 28 0>, /* D2 */ + <9 0 &gpio0 27 0>, /* D3 */ + <10 0 &gpio1 0 0>, /* D4 */ + <11 0 &gpio1 10 0>, /* D5 */ + <12 0 &gpio1 2 0>, /* D6 */ + <13 0 &gpio1 8 0>, /* D7 */ + <14 0 &gpio1 9 0>, /* D8 */ + <15 0 &gpio1 7 0>, /* D9 */ + <16 0 &gpio1 6 0>, /* D10 */ + <17 0 &gpio1 5 0>, /* D11 */ + <18 0 &gpio1 4 0>, /* D12 */ + <19 0 &gpio1 3 0>, /* D13 */ + <20 0 &gpio0 17 0>, /* D14 */ + <21 0 &gpio0 18 0>; /* D15 */ + }; +}; + +/* + * RT600 EVK board uses OS timer as the kernel timer + * In case we need to switch to SYSTICK timer, then + * replace &os_timer with &systick + */ +&os_timer { + status = "okay"; + wakeup-source; +}; + +&rtc { + status = "okay"; +}; + +&flexcomm0 { + compatible = "nxp,lpc-usart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm0_usart>; + pinctrl-names = "default"; + dmas = <&dma0 0>, <&dma0 1>; + dma-names = "rx", "tx"; +}; + +arduino_i2c: &flexcomm2 { + compatible = "nxp,lpc-i2c"; + status = "okay"; + pinctrl-0 = <&pinmux_flexcomm2_i2c>; + pinctrl-names = "default"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + fxos8700: fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + int1-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; + +arduino_serial: &flexcomm4 { + compatible = "nxp,lpc-usart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm4_usart>; + pinctrl-names = "default"; + dmas = <&dma0 8>, <&dma0 9>; + dma-names = "rx", "tx"; +}; + +arduino_spi: &flexcomm5 { + compatible = "nxp,lpc-spi"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 10>, <&dma0 11>; + dma-names = "rx", "tx"; + pinctrl-0 = <&pinmux_flexcomm5_spi>; + pinctrl-names = "default"; +}; + +/* I2S receive channel */ +i2s0: &flexcomm1 { + status = "okay"; + compatible = "nxp,lpc-i2s"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 2>; + dma-names = "rx"; + pinctrl-0 = <&pinmux_flexcomm1_i2s>; + pinctrl-names = "default"; +}; + +/* I2S transmit channel */ +i2s1: &flexcomm3 { + status = "okay"; + compatible = "nxp,lpc-i2s"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 7>; + dma-names = "tx"; + pinctrl-0 = <&pinmux_flexcomm3_i2s>; + pinctrl-names = "default"; +}; + +/* PCA9420 PMIC */ +&pmic_i2c { + status = "okay"; + compatible = "nxp,lpc-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinmux_pmic_i2c>; + pinctrl-names = "default"; + + pca9420: pca9420@61 { + compatible = "nxp,pca9420"; + reg = <0x61>; + nxp,enable-modesel-pins; + + buck1: BUCK1 { + regulator-boot-on; + }; + + buck2: BUCK2 { + regulator-boot-on; + }; + + ldo1: LDO1 { + regulator-boot-on; + }; + + ldo2: LDO2 { + regulator-boot-on; + }; + + + }; +}; + +&flexspi { + pinctrl-0 = <&pinmux_flexspi>; + pinctrl-names = "default"; + status = "okay"; + mx25um51345g: mx25um51345g@2 { + compatible = "nxp,imx-flexspi-mx25um51345g"; + /* MX25UM51245G is 64MB, 512MBit flash part */ + size = ; + reg = <2>; + spi-max-frequency = <200000000>; + status = "okay"; + jedec-id = [c2 81 3a]; + erase-block-size = <4096>; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 DT_SIZE_K(3076)>; + }; + slot1_partition: partition@321000 { + label = "image-1"; + reg = <0x00321000 DT_SIZE_K(3072)>; + }; + storage_partition: partition@621000 { + label = "storage"; + reg = <0x00621000 DT_SIZE_M(57)>; + }; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&wwdt0 { + status = "okay"; +}; + +&user_button_1 { + status = "okay"; +}; + +&user_button_2 { + status = "okay"; +}; + +&green_led { + status = "okay"; +}; + +&blue_led { + status = "okay"; +}; + +&red_led { + status = "okay"; +}; + +&sc_timer { + status = "okay"; + pinctrl-0 = <&pinmux_sctimer>; + pinctrl-names = "default"; +}; + +&usdhc0 { + status = "okay"; + /* Quick fix for 1.8V SD cards on RT600- disable 1.8V negotiation */ + no-1-8-v; + pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + pinctrl-0 = <&pinmux_usdhc>; + pinctrl-names = "default"; +}; + +&lpadc0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usbhs { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; + +&ctimer1 { + status = "okay"; +}; + +&ctimer2 { + status = "okay"; +}; + +&ctimer3 { + status = "okay"; +}; + +&ctimer4 { + status = "okay"; +}; + +&i3c0 { + pinctrl-0 = <&pinmux_i3c>; + pinctrl-names = "default"; + + status = "okay"; +}; + +/* Disable this node if not using USB and need another MPU region */ +&sram1 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml b/boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml new file mode 100644 index 00000000000..53f260fc60e --- /dev/null +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml @@ -0,0 +1,34 @@ +# +# Copyright (c) 2020, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt685_evk +name: NXP MIMXRT685-EVK +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 4608 +flash: 65536 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - counter + - dma + - pwm + - gpio + - hwinfo + - i2c + - i3c + - i2s + - sdhc + - spi + - watchdog + - usb_device +vendor: nxp diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_defconfig b/boards/nxp/mimxrt685_evk/mimxrt685_evk_defconfig new file mode 100644 index 00000000000..47128760e08 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_defconfig @@ -0,0 +1,17 @@ +# +# Copyright (c) 2020, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_PINCTRL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/mimxrt685_evk/pre_dt_board.cmake b/boards/nxp/mimxrt685_evk/pre_dt_board.cmake similarity index 100% rename from boards/arm/mimxrt685_evk/pre_dt_board.cmake rename to boards/nxp/mimxrt685_evk/pre_dt_board.cmake diff --git a/boards/nxp/mr_canhubk3/Kconfig.defconfig b/boards/nxp/mr_canhubk3/Kconfig.defconfig new file mode 100644 index 00000000000..02710328d68 --- /dev/null +++ b/boards/nxp/mr_canhubk3/Kconfig.defconfig @@ -0,0 +1,43 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MR_CANHUBK3 + +if SERIAL + +config UART_CONSOLE + default y + +endif # SERIAL + +if SPI + +config SPI_INIT_PRIORITY + default 50 + +if WDT_NXP_FS26 + +config WDT_NXP_FS26_INIT_PRIORITY + default 51 + +endif # WDT_NXP_FS26 +endif # SPI + +if CAN + +config GPIO + default y + +endif # CAN + +if NETWORKING + +config NET_L2_ETHERNET + default y if !NET_LOOPBACK && !NET_TEST + +config MDIO + default y if NET_L2_ETHERNET + +endif # NETWORKING + +endif # BOARD_MR_CANHUBK3 diff --git a/boards/nxp/mr_canhubk3/Kconfig.mr_canhubk3 b/boards/nxp/mr_canhubk3/Kconfig.mr_canhubk3 new file mode 100644 index 00000000000..447411b0b35 --- /dev/null +++ b/boards/nxp/mr_canhubk3/Kconfig.mr_canhubk3 @@ -0,0 +1,6 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MR_CANHUBK3 + select SOC_S32K344 + select SOC_PART_NUMBER_PS32K344EHVPBS diff --git a/boards/arm/mr_canhubk3/board.cmake b/boards/nxp/mr_canhubk3/board.cmake similarity index 100% rename from boards/arm/mr_canhubk3/board.cmake rename to boards/nxp/mr_canhubk3/board.cmake diff --git a/boards/nxp/mr_canhubk3/board.yml b/boards/nxp/mr_canhubk3/board.yml new file mode 100644 index 00000000000..3840a8f3d30 --- /dev/null +++ b/boards/nxp/mr_canhubk3/board.yml @@ -0,0 +1,5 @@ +board: + name: mr_canhubk3 + vendor: nxp + socs: + - name: s32k344 diff --git a/boards/arm/mr_canhubk3/doc/img/mr_canhubk3_top.jpg b/boards/nxp/mr_canhubk3/doc/img/mr_canhubk3_top.jpg similarity index 100% rename from boards/arm/mr_canhubk3/doc/img/mr_canhubk3_top.jpg rename to boards/nxp/mr_canhubk3/doc/img/mr_canhubk3_top.jpg diff --git a/boards/nxp/mr_canhubk3/doc/index.rst b/boards/nxp/mr_canhubk3/doc/index.rst new file mode 100644 index 00000000000..2fe3780236a --- /dev/null +++ b/boards/nxp/mr_canhubk3/doc/index.rst @@ -0,0 +1,339 @@ +.. _mr_canhubk3: + +NXP MR-CANHUBK3 +############### + +Overview +******** + +`NXP MR-CANHUBK3`_ is an evaluation board for mobile robotics applications such +as autonomous mobile robots (AMR) and automated guided vehicles (AGV). It +features an `NXP S32K344`_ general-purpose automotive microcontroller based on +an Arm Cortex-M7 core (Lock-Step). + +.. image:: img/mr_canhubk3_top.jpg + :align: center + :alt: NXP MR-CANHUBK3 (TOP) + +Hardware +******** + +- NXP S32K344 + - Arm Cortex-M7 (Lock-Step), 160 MHz (Max.) + - 4 MB of program flash, with ECC + - 320 KB RAM, with ECC + - Ethernet 100 Mbps, CAN FD, FlexIO, QSPI + - 12-bit 1 Msps ADC, 16-bit eMIOS timer + +- `NXP FS26 Safety System Basis Chip`_ + +- Interfaces: + - Console UART + - 6x CAN FD + - 100Base-T1 Ethernet + - JST-GH connectors and I/O headers for I2C, SPI, GPIO, + PWM, etc. + +More information about the hardware and design resources can be found at +`NXP MR-CANHUBK3`_ website. + +Supported Features +================== + +The ``mr_canhubk3`` board configuration supports the following hardware features: + +============ ========== ================================ +Interface Controller Driver/Component +============ ========== ================================ +SIUL2 on-chip | pinctrl + | gpio + | external interrupt controller +WKPU on-chip interrupt controller +LPUART on-chip serial +QSPI on-chip flash +FLEXCAN on-chip can +LPI2C on-chip i2c +ADC SAR on-chip adc +LPSPI on-chip spi +WDT FS26 SBC watchdog +EMAC on-chip ethernet + mdio +eMIOS on-chip pwm +EDMA on-chip dma +============ ========== ================================ + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/nxp/mr_canhubk3/mr_canhubk3_defconfig`. + +Connections and IOs +=================== + +Each GPIO port is divided into two banks: low bank, from pin 0 to 15, and high +bank, from pin 16 to 31. For example, ``PTA2`` is the pin 2 of ``gpioa_l`` (low +bank), and ``PTA20`` is the pin 4 of ``gpioa_h`` (high bank). + +The GPIO controller provides the option to route external input pad interrupts +to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC. +By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller, +unless they are explicity configured to be directed to the WKPU interrupt +controller, as outlined in :zephyr_file:`dts/bindings/gpio/nxp,s32-gpio.yaml`. + +To find information about which GPIOs are compatible with each interrupt +controller, refer to the device reference manual. + +.. note:: + + It is important to highlight that the current board configuration lacks + support for wake-up events and power-management features. WKPU functionality + is restricted solely to serving as an interrupt controller. + +LEDs +---- + +The MR-CANHUBK3 board has one user RGB LED: + +======================= ===== ===== =================================== +Devicetree node Color Pin Pin Functions +======================= ===== ===== =================================== +led0 / user_led1_red Red PTE14 FXIO D7 / EMIOS0 CH19 +led1 / user_led1_green Green PTA27 FXIO D5 / EMIOS1 CH10 / EMIOS2 CH10 +led2 / user_led1_blue Blue PTE12 FXIO D8 / EMIOS1 CH5 +======================= ===== ===== =================================== + +The user can control the LEDs in any way. An output of ``0`` illuminates the LED. + +Buttons +------- + +The MR-CANHUBK3 board has two user buttons: + +======================= ===== ===== ============== +Devicetree node Label Pin Pin Functions +======================= ===== ===== ============== +sw0 / user_button_1 SW1 PTD15 EIRQ31 +sw0 / user_button_2 SW2 PTA25 EIRQ5 / WKPU34 +======================= ===== ===== ============== + +System Clock +============ + +The Arm Cortex-M7 (Lock-Step) are configured to run at 160 MHz. + +Serial Console +============== + +By default, the serial console is provided through ``lpuart2`` on the 7-pin +DCD-LZ debug connector ``P6``. + +========= ===== ============ +Connector Pin Pin Function +========= ===== ============ +P6.2 PTA9 LPUART2_TX +P6.3 PTA8 LPUART2_RX +========= ===== ============ + +CAN +=== + +CAN is provided through FLEXCAN interface with 6 instances. + +=============== ======= =============== ============= +Devicetree node Pin Pin Function Bus Connector +=============== ======= =============== ============= +flexcan0 | PTA6 | PTA6_CAN0_RX P12/P13 + | PTA7 | PTA7_CAN0_TX +flexcan1 | PTC9 | PTC9_CAN0_RX P14/P15 + | PTC8 | PTC8_CAN0_TX +flexcan2 | PTE25 | PTE25_CAN0_RX P16/P17 + | PTE24 | PTE24_CAN0_TX +flexcan3 | PTC29 | PTC29_CAN0_RX P18/019 + | PTC28 | PTC28_CAN0_TX +flexcan4 | PTC31 | PTC31_CAN0_RX P20/P21 + | PTC30 | PTC30_CAN0_TX +flexcan5 | PTC11 | PTC11_CAN0_RX P22/P23 + | PTC10 | PTC10_CAN0_TX +=============== ======= =============== ============= + +.. note:: + There is limitation by HAL SDK, so CAN only has support maximum 64 message buffers (MBs) + and support maximum 32 message buffers for concurrent active instances with 8 bytes + payload. We need to pay attention to configuration options: + + 1. :kconfig:option:`CONFIG_CAN_MAX_MB` must be less or equal than the + maximum number of message buffers that is according to the table below. + + 2. :kconfig:option:`CONFIG_CAN_MAX_FILTER` must be less or equal than + :kconfig:option:`CONFIG_CAN_MAX_MB`. + +=============== ========== ================ ================ +Devicetree node Payload Hardware support Software support +=============== ========== ================ ================ +flexcan0 | 8 bytes | 96 MBs | 64 MBs + | 16 bytes | 63 MBs | 42 MBs + | 32 bytes | 36 MBs | 24 MBs + | 64 bytes | 21 MBs | 14 MBs +flexcan1 | 8 bytes | 64 MBs | 64 MBs + | 16 bytes | 42 MBs | 42 MBs + | 32 bytes | 24 MBs | 24 MBs + | 64 bytes | 14 MBs | 14 MBs +flexcan2 | 8 bytes | 64 MBs | 64 MBs + | 16 bytes | 42 MBs | 42 MBs + | 32 bytes | 24 MBs | 24 MBs + | 64 bytes | 14 MBs | 14 MBs +flexcan3 | 8 bytes | 32 MBs | 32 MBs + | 16 bytes | 21 MBs | 21 MBs + | 32 bytes | 12 MBs | 12 MBs + | 64 bytes | 7 MBs | 7 MBs +flexcan4 | 8 bytes | 32 MBs | 32 MBs + | 16 bytes | 21 MBs | 21 MBs + | 32 bytes | 12 MBs | 12 MBs + | 64 bytes | 7 MBs | 7 MBs +flexcan5 | 8 bytes | 32 MBs | 32 MBs + | 16 bytes | 21 MBs | 21 MBs + | 32 bytes | 12 MBs | 12 MBs + | 64 bytes | 7 MBs | 7 MBs +=============== ========== ================ ================ + +.. note:: + A CAN bus usually requires 60 Ohm termination at both ends of the bus. This may be + accomplished using one of the included CAN termination boards. For more details, refer + to the section ``6.3 CAN Connectors`` in the Hardware User Manual of `NXP MR-CANHUBK3`_. + +I2C +=== + +I2C is provided through LPI2C interface with 2 instances ``lpi2c0`` and ``lpi2c1`` +on corresponding connectors ``P4``, ``P3``. + +========= ===== ============ +Connector Pin Pin Function +========= ===== ============ +P3.2 PTD9 LPI2C1_SCL +P3.3 PTD8 LPI2C1_SDA +P4.3 PTD14 LPI2C0_SCL +P4.4 PTD13 LPI2C0_SDA +========= ===== ============ + +ADC +=== + +ADC is provided through ADC SAR controller with 3 instances. ADC channels are divided into +3 groups (precision, standard and external). + +.. note:: + All channels of an instance only run on 1 group channel at the same time. + +FS26 SBC Watchdog +================= + +On normal operation after the board is powered on, there is a window of 256 ms +on which the FS26 watchdog must be serviced with a good token refresh, otherwise +the watchdog will signal a reset to the MCU. This board configuration enables +the FS26 watchdog driver that handles this initialization. + +.. note:: + + The FS26 can also be started in debug mode (watchdog disabled) following + these steps: + + 1. Power off the board. + 2. Remove the jumper ``JP1`` (pins 1-2 open), which is connected by default. + 3. Power on the board. + 4. Reconnect the jumper ``JP1`` (pins 1-2 shorted). + +External Flash +============== + +The on-board MX25L6433F 64M-bit multi-I/O Serial NOR Flash memory is connected +to the QSPI controller port A1. This board configuration selects it as the +default flash controller. + +Ethernet +======== + +This board has a single instance of Ethernet Media Access Controller (EMAC) +interfacing with a `NXP TJA1103`_ 100Base-T1 Ethernet PHY. Currently, there is +limited driver for this PHY that allows for overiding the default pin strapping configuration for +the PHY (RMII, master, autonomous mode enabled, polarity correction enabled) +to slave mode. + +The 100Base-T1 signals are available in connector ``P9`` and can be converted to +100Base-T using a Ethernet media converter such as `RDDRONE-T1ADAPT`_. + +Programming and Debugging +************************* + +Applications for the ``mr_canhubk3`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +This board configuration supports `Lauterbach TRACE32`_ and `SEGGER J-Link`_ +West runners for flashing and debugging applications. Follow the steps described +in :ref:`lauterbach-trace32-debug-host-tools` and :ref:`jlink-debug-host-tools`, +to setup the flash and debug host tools for these runners, respectively. The +default runner is J-Link. + +Flashing +======== + +Run the ``west flash`` command to flash the application using SEGGER J-Link. +Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32. + +The Lauterbach TRACE32 runner supports additional options that can be passed +through command line: + +.. code-block:: console + + west flash -r trace32 --startup-args elfFile= loadTo= + eraseFlash= verifyFlash= + +Where: + +- ```` is the path to the Zephyr application ELF in the output + directory +- ``loadTo=flash`` loads the application to the SoC internal program flash + (:kconfig:option:`CONFIG_XIP` must be set), and ``loadTo=sram`` load the + application to SRAM. Default is ``flash``. +- ``eraseFlash=yes`` erases the whole content of SoC internal flash before the + application is downloaded to either Flash or SRAM. This routine takes time to + execute. Default is ``no``. +- ``verifyFlash=yes`` verify the SoC internal flash content after programming + (use together with ``loadTo=flash``). Default is ``no``. + +For example, to erase and verify flash content: + +.. code-block:: console + + west flash -r trace32 --startup-args elfFile=build/zephyr/zephyr.elf loadTo=flash eraseFlash=yes verifyFlash=yes + +Debugging +========= + +Run the ``west debug`` command to start a GDB session using SEGGER J-Link. +Alternatively, run ``west debug -r trace32`` to launch the Lauterbach TRACE32 +software debugging interface. + +References +********** + +.. target-notes:: + +.. _NXP MR-CANHUBK3: + https://www.nxp.com/design/development-boards/automotive-development-platforms/s32k-mcu-platforms/s32k344-evaluation-board-for-mobile-robotics-incorporating-100baset1-and-six-can-fd:MR-CANHUBK344 + +.. _NXP S32K344: + https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k3-microcontrollers-for-automotive-general-purpose:S32K3 + +.. _NXP FS26 Safety System Basis Chip: + https://www.nxp.com/products/power-management/pmics-and-sbcs/safety-sbcs/safety-system-basis-chip-with-low-power-fit-for-asil-d:FS26 + +.. _NXP TJA1103: + https://www.nxp.com/products/interfaces/ethernet-/automotive-ethernet-phys/asil-b-compliant-100base-t1-ethernet-phy:TJA1103 + +.. _RDDRONE-T1ADAPT: + https://www.nxp.com/products/interfaces/ethernet-/automotive-ethernet-phys/ethernet-media-converter-for-drones-rovers-mobile-robotics-and-automotive:RDDRONE-T1ADAPT + +.. _Lauterbach TRACE32: + https://www.lauterbach.com + +.. _SEGGER J-Link: + https://wiki.segger.com/NXP_S32K3xx diff --git a/boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi b/boards/nxp/mr_canhubk3/mr_canhubk3-pinctrl.dtsi similarity index 100% rename from boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi rename to boards/nxp/mr_canhubk3/mr_canhubk3-pinctrl.dtsi diff --git a/boards/arm/mr_canhubk3/mr_canhubk3.dts b/boards/nxp/mr_canhubk3/mr_canhubk3.dts similarity index 100% rename from boards/arm/mr_canhubk3/mr_canhubk3.dts rename to boards/nxp/mr_canhubk3/mr_canhubk3.dts diff --git a/boards/arm/mr_canhubk3/mr_canhubk3.yaml b/boards/nxp/mr_canhubk3/mr_canhubk3.yaml similarity index 100% rename from boards/arm/mr_canhubk3/mr_canhubk3.yaml rename to boards/nxp/mr_canhubk3/mr_canhubk3.yaml diff --git a/boards/arm/mr_canhubk3/mr_canhubk3_defconfig b/boards/nxp/mr_canhubk3/mr_canhubk3_defconfig similarity index 79% rename from boards/arm/mr_canhubk3/mr_canhubk3_defconfig rename to boards/nxp/mr_canhubk3/mr_canhubk3_defconfig index d8182ce8327..b6d3e6e78c7 100644 --- a/boards/arm/mr_canhubk3/mr_canhubk3_defconfig +++ b/boards/nxp/mr_canhubk3/mr_canhubk3_defconfig @@ -1,9 +1,6 @@ -# Copyright 2023 NXP +# Copyright 2023-2024 NXP # SPDX-License-Identifier: Apache-2.0 -CONFIG_BOARD_MR_CANHUBK3=y -CONFIG_SOC_S32K344=y -CONFIG_SOC_SERIES_S32K3XX=y CONFIG_BUILD_OUTPUT_HEX=y # Use Systick as system clock diff --git a/boards/arm/mr_canhubk3/support/debug.cmm b/boards/nxp/mr_canhubk3/support/debug.cmm similarity index 100% rename from boards/arm/mr_canhubk3/support/debug.cmm rename to boards/nxp/mr_canhubk3/support/debug.cmm diff --git a/boards/arm/mr_canhubk3/support/flash.cmm b/boards/nxp/mr_canhubk3/support/flash.cmm similarity index 100% rename from boards/arm/mr_canhubk3/support/flash.cmm rename to boards/nxp/mr_canhubk3/support/flash.cmm diff --git a/boards/arm/mr_canhubk3/support/startup.cmm b/boards/nxp/mr_canhubk3/support/startup.cmm similarity index 100% rename from boards/arm/mr_canhubk3/support/startup.cmm rename to boards/nxp/mr_canhubk3/support/startup.cmm diff --git a/boards/arm64/nxp_ls1046ardb/CMakeLists.txt b/boards/nxp/rddrone_fmuk66/CMakeLists.txt similarity index 100% rename from boards/arm64/nxp_ls1046ardb/CMakeLists.txt rename to boards/nxp/rddrone_fmuk66/CMakeLists.txt diff --git a/boards/nxp/rddrone_fmuk66/Kconfig.defconfig b/boards/nxp/rddrone_fmuk66/Kconfig.defconfig new file mode 100644 index 00000000000..b9a6f469655 --- /dev/null +++ b/boards/nxp/rddrone_fmuk66/Kconfig.defconfig @@ -0,0 +1,27 @@ +# RDDRONE-FMUK66 board + +# Copyright (c) 2021, Electromaticus LLC, 2021 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RDDRONE_FMUK66 + +config OSC_XTAL0_FREQ + default 16000000 + +config MCG_PRDIV0 + default 0x0 + +config MCG_VDIV0 + default 0x4 + +config MCG_FCRDIV + default 1 + +if NETWORKING + +config NET_L2_ETHERNET + default y if !MODEM + +endif # NETWORKING + +endif # BOARD_RDDRONE_FMUK66 diff --git a/boards/nxp/rddrone_fmuk66/Kconfig.rddrone_fmuk66 b/boards/nxp/rddrone_fmuk66/Kconfig.rddrone_fmuk66 new file mode 100644 index 00000000000..5587aeeaf66 --- /dev/null +++ b/boards/nxp/rddrone_fmuk66/Kconfig.rddrone_fmuk66 @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RDDRONE_FMUK66 + select SOC_MK66F18 + select SOC_PART_NUMBER_MK66FN2M0VLQ18 diff --git a/boards/arm/rddrone_fmuk66/board.cmake b/boards/nxp/rddrone_fmuk66/board.cmake similarity index 100% rename from boards/arm/rddrone_fmuk66/board.cmake rename to boards/nxp/rddrone_fmuk66/board.cmake diff --git a/boards/nxp/rddrone_fmuk66/board.yml b/boards/nxp/rddrone_fmuk66/board.yml new file mode 100644 index 00000000000..40707b2f2e4 --- /dev/null +++ b/boards/nxp/rddrone_fmuk66/board.yml @@ -0,0 +1,5 @@ +board: + name: rddrone_fmuk66 + vendor: nxp + socs: + - name: mk66f18 diff --git a/boards/nxp/rddrone_fmuk66/doc/index.rst b/boards/nxp/rddrone_fmuk66/doc/index.rst new file mode 100644 index 00000000000..69d862455ac --- /dev/null +++ b/boards/nxp/rddrone_fmuk66/doc/index.rst @@ -0,0 +1,202 @@ +.. _rddrone_fmuk66: + +NXP RDDRONE-FMUK66 +################## + +Overview +******** + +The RDDRONE FMUK66 is an drone control board with commonly used peripheral +connectors and a Kinetis K66 on board. + +- Comes with a J-Link Edu Mini for programming and UART console. + +.. image:: rddrone_fmuk66.jpg + :align: center + :alt: RDDRONE-FMUK66 + +Hardware +******** + +- MK66FN2MOVLQ18 MCU (180 MHz, 2 MB flash memory, 256 KB RAM, low-power, + crystal-less USB, and 144 Low profile Quad Flat Package (LQFP)) +- Dual role USB interface with micro-B USB connector +- RGB LED +- FXOS8700CQ accelerometer and magnetometer +- FXAS21002CQ gyro +- BMM150 magnetometer +- ML3114A2 barometer +- BMP280 barometer +- Connector for PWM servo/motor controls +- Connector for UART GPS/GLONASS +- SDHC + +For more information about the K64F SoC and FRDM-K64F board: + +- `K66F Website`_ +- `K66F Datasheet`_ +- `K66F Reference Manual`_ +- `RDDRONE-FMUK66 Website`_ +- `RDDRONE-FMUK66 User Guide`_ +- `RDDRONE-FMUK66 Schematics`_ + +Supported Features +================== + +The rddrone-fmuk66 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig` + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The K66F SoC is configured to use the 16 MHz external oscillator on the board +with the on-chip PLL to generate a 160 MHz system clock. + +Serial Port +=========== + +The K66F SoC has six UARTs. LPUART0 is configured for the console, UART0 is labeled Serial 2, +UART2 is labeled GPS, UART4 is labeled Serial 1. Any of these UARTs may be used as the console by +overlaying the board device tree. + +USB +=== + +The K66F SoC has a USB OTG (USBOTG) controller that supports both +device and host functions through its micro USB connector (K66F USB). +Only USB device function is supported in Zephyr at the moment. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use jlink. The board package +with accessories comes with a jlink mini edu and cable specifically for this board +along with a usb to uart that connects directly to the jlink mini edu. This is the expected +default configuration for programming and getting a console. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rddrone-fmuk66 + :gen-args: + :goals: build + +Configuring a Console +===================== + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rddrone-fmuk66 + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.7.0 ***** + Hello World! rddrone-fmuk66 + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rddrone-fmuk66 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.7.0 ***** + Hello World! rddrone-fmuk66 + +.. _RDDRONE-FMUK66 Website: + +https://www.nxp.com/design/designs/px4-robotic-drone-vehicle-flight-management-unit-vmu-fmu-rddrone-fmuk66:RDDRONE-FMUK66 + +.. _RDDRONE-FMUK66 User Guide: + +https://nxp.gitbook.io/hovergames/userguide/getting-started + +.. _RDDRONE-FMUK66 Schematics: + +https://www.nxp.com/webapp/Download?colCode=SPF-39053 + +.. _K66F Website: + +https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k6x-ethernet/kinetis-k66-180-mhz-dual-high-speed-full-speed-usbs-2mb-flash-microcontrollers-mcus-based-on-arm-cortex-m4-core:K66_180 + +.. _K66F Datasheet: + +https://www.nxp.com/docs/en/data-sheet/K66P144M180SF5V2.pdf + +.. _K66F Reference Manual: + +https://www.nxp.com/webapp/Download?colCode=K66P144M180SF5RMV2 diff --git a/boards/arm/rddrone_fmuk66/doc/rddrone_fmuk66.jpg b/boards/nxp/rddrone_fmuk66/doc/rddrone_fmuk66.jpg similarity index 100% rename from boards/arm/rddrone_fmuk66/doc/rddrone_fmuk66.jpg rename to boards/nxp/rddrone_fmuk66/doc/rddrone_fmuk66.jpg diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi similarity index 100% rename from boards/arm/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi rename to boards/nxp/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts similarity index 100% rename from boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts rename to boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66.yaml b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.yaml similarity index 100% rename from boards/arm/rddrone_fmuk66/rddrone_fmuk66.yaml rename to boards/nxp/rddrone_fmuk66/rddrone_fmuk66.yaml diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig similarity index 86% rename from boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig rename to boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig index b8aa9785942..fe63a4dd234 100644 --- a/boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig +++ b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_MK66F18=y -CONFIG_SOC_SERIES_KINETIS_K6X=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/s32z2xxdc2/Kconfig.defconfig b/boards/nxp/s32z2xxdc2/Kconfig.defconfig new file mode 100644 index 00000000000..f54f3ca4d13 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1 + +config BUILD_OUTPUT_BIN + default n + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +config UART_CONSOLE + default y + +endif # SERIAL + +if SHELL + +config SHELL_STACK_SIZE + default 4096 + +endif # SHELL + +endif # BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1 diff --git a/boards/nxp/s32z2xxdc2/Kconfig.s32z2xxdc2 b/boards/nxp/s32z2xxdc2/Kconfig.s32z2xxdc2 new file mode 100644 index 00000000000..ed9e2ea917f --- /dev/null +++ b/boards/nxp/s32z2xxdc2/Kconfig.s32z2xxdc2 @@ -0,0 +1,7 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_S32Z2XXDC2 + select SOC_S32Z270_RTU0 if BOARD_S32Z2XXDC2_S32Z270_RTU0 + select SOC_S32Z270_RTU1 if BOARD_S32Z2XXDC2_S32Z270_RTU1 + select SOC_PART_NUMBER_P32Z270ADCK0MJFT if BOARD_S32Z2XXDC2 diff --git a/boards/arm/s32z270dc2_r52/board.cmake b/boards/nxp/s32z2xxdc2/board.cmake similarity index 100% rename from boards/arm/s32z270dc2_r52/board.cmake rename to boards/nxp/s32z2xxdc2/board.cmake diff --git a/boards/nxp/s32z2xxdc2/board.yml b/boards/nxp/s32z2xxdc2/board.yml new file mode 100644 index 00000000000..bffe1839c3c --- /dev/null +++ b/boards/nxp/s32z2xxdc2/board.yml @@ -0,0 +1,11 @@ +board: + name: s32z2xxdc2 + vendor: nxp + revision: + format: letter + default: B + revisions: + - name: B + - name: D + socs: + - name: s32z270 diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst new file mode 100644 index 00000000000..18660e2fee5 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/doc/index.rst @@ -0,0 +1,310 @@ +.. _s32z2xxdc2: + +NXP X-S32Z27X-DC (DC2) +###################### + +Overview +******** + +The X-S32Z27X-DC (DC2) board is based on the NXP S32Z2 Real-Time Processor, +which includes two Real-Time Units (RTU) composed of four ARM Cortex-R52 cores +each, with flexible split/lock configurations. + +There is one Zephyr board per SoC/RTU: + +- ``s32z2xxdc2/s32z270/rtu0``, for S32Z270/RTU0 +- ``s32z2xxdc2/s32z270/rtu1``, for S32Z270/RTU1. + +Hardware +******** + +Information about the hardware and design resources can be found at +`NXP S32Z2 Real-Time Processors website`_. + +Supported Features +================== + +The boards support the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| Arm GIC | on-chip | interrupt_controller | ++-----------+------------+-------------------------------------+ +| Arm Timer | on-chip | timer | ++-----------+------------+-------------------------------------+ +| LINFlexD | on-chip | serial | ++-----------+------------+-------------------------------------+ +| MRU | on-chip | mbox | ++-----------+------------+-------------------------------------+ +| NETC | on-chip | ethernet | +| | | | +| | | mdio | ++-----------+------------+-------------------------------------+ +| SIUL2 | on-chip | pinctrl | +| | | | +| | | gpio | +| | | | +| | | external interrupt controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| SWT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| CANEXCEL | on-chip | can | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The SoC's pads are grouped into ports and pins for consistency with GPIO driver +and the HAL drivers used by this Zephyr port. The following table summarizes +the mapping between pads and ports/pins. This must be taken into account when +using GPIO driver or configuring the pinmuxing for the device drivers. + ++-------------------+-------------+ +| Pads | Port/Pins | ++===================+=============+ +| PAD_000 - PAD_015 | PA0 - PA15 | ++-------------------+-------------+ +| PAD_016 - PAD_030 | PB0 - PB14 | ++-------------------+-------------+ +| PAD_031 | PC15 | ++-------------------+-------------+ +| PAD_032 - PAD_047 | PD0 - PD15 | ++-------------------+-------------+ +| PAD_048 - PAD_063 | PE0 - PE15 | ++-------------------+-------------+ +| PAD_064 - PAD_079 | PF0 - PF15 | ++-------------------+-------------+ +| PAD_080 - PAD_091 | PG0 - PG11 | ++-------------------+-------------+ +| PAD_092 - PAD_095 | PH12 - PH15 | ++-------------------+-------------+ +| PAD_096 - PAD_111 | PI0 - PI15 | ++-------------------+-------------+ +| PAD_112 - PAD_127 | PJ0 - PJ15 | ++-------------------+-------------+ +| PAD_128 - PAD_143 | PK0 - PK15 | ++-------------------+-------------+ +| PAD_144 - PAD_145 | PL0 - PL1 | ++-------------------+-------------+ +| PAD_146 - PAD_159 | PM2 - PM15 | ++-------------------+-------------+ +| PAD_160 - PAD_169 | PN0 - PN9 | ++-------------------+-------------+ +| PAD_170 - PAD_173 | PO10 - PO13 | ++-------------------+-------------+ + +This board does not include user LED's or switches, which are needed for some +of the samples such as :zephyr:code-sample:`blinky` or :zephyr:code-sample:`button`. +Follow the steps described in the sample description to enable support for this +board. + +System Clock +============ + +The Cortex-R52 cores are configured to run at 800 MHz. + +Serial Port +=========== + +The SoC has 12 LINFlexD instances that can be used in UART mode. The console can +be accessed by default on the USB micro-B connector `J119`. + +Watchdog +======== + +The watchdog driver only supports triggering an interrupt upon timer expiration. +Zephyr is currently running from SRAM on this board, thus system reset is not +supported. + +Ethernet +======== + +NETC driver supports to manage the Physical Station Interface (PSI0) and/or a +single Virtual SI (VSI). The rest of the VSI's shall be assigned to different +cores of the system. Refer to :ref:`nxp_s32_netc-samples` to learn how to +configure the Ethernet network controller. + +Controller Area Network (CAN) +============================= + +Currently, the CANXL transceiver is not populated in this board. So CAN transceiver +connection is required for running external traffic. We can use any CAN transceiver, +which supports CAN 2.0 and CAN FD protocol. + +CAN driver supports classic (CAN 2.0) and CAN FD mode. Remote transmission request is +not supported as this feature is not available on NXP S32 CANXL HAL. + +Programming and Debugging +************************* + +Applications for the ``s32z2xxdc2`` boards can be built in the usual way as +documented in :ref:`build_an_application`. + +Currently is only possible to load and execute a Zephyr application binary on +this board from the core internal SRAM. + +This board supports West runners for the following debug tools: + +- :ref:`NXP S32 Debug Probe ` (default) +- :ref:`Lauterbach TRACE32 ` + +Follow the installation steps of the debug tool you plan to use before loading +your firmware. + +Set-up the Board +================ + +Connect the external debugger probe to the board's JTAG connector (``J134``) +and to the host computer via USB or Ethernet, as supported by the probe. + +For visualizing the serial output, connect the board's USB/UART port (``J119``) to +the host computer and run your favorite terminal program to listen for output. +For example, using the cross-platform `pySerial miniterm`_ terminal: + +.. code-block:: console + + python -m serial.tools.miniterm 115200 + +Replace ```` with the port where the board can be found. For example, +under Linux, ``/dev/ttyUSB0``. + +Debugging +========= + +You can build and debug the :ref:`hello_world` sample for the board +``s32z2xxdc2/s32z270/rtu0`` with: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2/s32z270/rtu0 + :goals: build debug + +In case you are using a newer PCB revision, you have to use an adapted board +definition as the default PCB revision is B. For example, if using revision D: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2@D/s32z270/rtu0 + :goals: build debug + :compact: + +At this point you can do your normal debug session. Set breakpoints and then +:kbd:`c` to continue into the program. You should see the following message in +the terminal: + +.. code-block:: console + + Hello World! s32z2xxdc2 + +To debug with Lauterbach TRACE32 softare run instead: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2/s32z270/rtu0 + :goals: build debug -r trace32 + :compact: + +Flashing +======== + +Follow these steps if you just want to download the application to the board +SRAM and run. + +``flash`` command is supported only by the Lauterbach TRACE32 runner: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2/s32z270/rtu0 + :goals: build flash -r trace32 + :compact: + +.. note:: + Currently, the Lauterbach start-up scripts executed with ``flash`` and + ``debug`` commands perform the same steps to initialize the SoC and + load the application to SRAM. The difference is that ``flash`` hides the + Lauterbach TRACE32 interface, executes the application and exits. + +To imitate a similar behavior using NXP S32 Debug Probe runner, you can run the +``debug`` command with GDB in batch mode: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2/s32z270/rtu0 + :goals: build debug --tool-opt='--batch' + :compact: + +RTU and Core Configuration +========================== + +This Zephyr port can only run single core in any of the Cortex-R52 cores, +either in lock-step or split-lock mode. By default, Zephyr runs on the first +core of the RTU chosen and in lock-step mode (which is the reset +configuration). + +To build for split-lock mode, the :kconfig:option:`CONFIG_DCLS` must be +disabled from your application Kconfig file. + +By default the board configuration will set the runner arguments according to +the build configuration. To debug for a core different than the default use: + +.. tabs:: + + .. group-tab:: lockstep configuration + + .. code-block:: console + + west debug --core-name='R52___LS' + + .. group-tab:: split-lock configuration + + .. code-block:: console + + west debug --core-name='R52__' + +Where: + +- ```` is the zero-based RTU index +- ```` is the zero-based core index relative to the RTU on which to + run the Zephyr application (0, 1, 2 or 3) + +For example, to build the :ref:`hello_world` sample for the board +``s32z2xxdc2/s32z270/rtu0`` with split-lock core configuration: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2/s32z270/rtu0 + :goals: build + :gen-args: -DCONFIG_DCLS=n + :compact: + +To execute this sample in the second core of RTU0 in split-lock mode: + +.. code-block:: console + + west debug --core-name='R52_0_1' + +If using Lauterbach TRACE32, all runner parameters must be overridden from command +line: + +.. code-block:: console + + west debug --startup-args elfFile= rtu= core= lockstep= + +Where ```` is the path to the Zephyr application ELF in the output +directory. + +References +********** + +.. target-notes:: + +.. _NXP S32Z2 Real-Time Processors website: + https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32z-and-s32e-real-time-processors/s32z2-safe-and-secure-high-performance-real-time-processors:S32Z2 + +.. _pySerial miniterm: + https://pyserial.readthedocs.io/en/latest/tools.html#module-serial.tools.miniterm diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi new file mode 100644 index 00000000000..10fda8bb439 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "s32z2xxdc2_s32z270_pinctrl.dtsi" + +&swt0 { + status = "okay"; +}; + +&emdio { + pinctrl-0 = <&emdio_default>; + pinctrl-names = "default"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy"; + reg = <0x7>; + status = "okay"; + }; +}; + +&enetc_psi0 { + local-mac-address = [00 00 00 01 02 00]; + pinctrl-0 = <ð0_default>; + pinctrl-names = "default"; + clock-frequency = <300000000>; + phy-handle = <&phy0>; + status = "okay"; +}; + +&can0 { + pinctrl-0 = <&can0_default>; + pinctrl-names = "default"; + bus-speed = <125000>; + sample-point = <875>; + bus-speed-data = <1000000>; + sample-point-data = <875>; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_default>; + pinctrl-names = "default"; + bus-speed = <125000>; + sample-point = <875>; + bus-speed-data = <1000000>; + sample-point-data = <875>; +}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl-common.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi similarity index 100% rename from boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl-common.dtsi rename to boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts new file mode 100644 index 00000000000..37c2f6b74ff --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts @@ -0,0 +1,33 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "s32z2xxdc2_s32z270.dtsi" + +/ { + model = "NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores"; + compatible = "nxp,s32z270"; + + chosen { + zephyr,sram = &sram0; + zephyr,canbus = &can0; + }; + + aliases { + watchdog0 = &swt0; + }; +}; + +&mru0 { + rx-channels = <1>; + status = "okay"; +}; + +&enetc_psi0 { + mboxes = <&mru0 0>; + mbox-names = "rx"; +}; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml new file mode 100644 index 00000000000..9bbb05c6414 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml @@ -0,0 +1,19 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32z2xxdc2/s32z270/rtu0 +name: NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores +type: mcu +arch: arm +ram: 1024 +toolchain: + - zephyr +supported: + - uart + - gpio + - watchdog + - netif:eth + - can + - spi + - counter +vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_B.overlay b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_B.overlay similarity index 100% rename from boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_B.overlay rename to boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_B.overlay diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.overlay b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.overlay similarity index 100% rename from boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.overlay rename to boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.overlay diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml new file mode 100644 index 00000000000..75d0455ee59 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml @@ -0,0 +1,19 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32z2xxdc2@D/s32z270/rtu0 +name: NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores (rev. D) +type: mcu +arch: arm +ram: 1024 +toolchain: + - zephyr +supported: + - uart + - gpio + - watchdog + - netif:eth + - can + - spi + - counter +vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig new file mode 100644 index 00000000000..d7f502c0af0 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig @@ -0,0 +1,11 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n +CONFIG_ISR_STACK_SIZE=512 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 +CONFIG_ARM_MPU=y +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts new file mode 100644 index 00000000000..ce5d16260ab --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts @@ -0,0 +1,35 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "s32z2xxdc2_s32z270.dtsi" + +/ { + model = "NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores"; + compatible = "nxp,s32z270"; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,canbus = &can0; + }; + + aliases { + watchdog0 = &swt0; + }; +}; + +&mru4 { + rx-channels = <1>; + status = "okay"; +}; + +&enetc_psi0 { + mboxes = <&mru4 0>; + mbox-names = "rx"; +}; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml new file mode 100644 index 00000000000..77a57961550 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml @@ -0,0 +1,19 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32z2xxdc2/s32z270/rtu1 +name: NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores +type: mcu +arch: arm +ram: 1024 +toolchain: + - zephyr +supported: + - uart + - gpio + - watchdog + - netif:eth + - can + - spi + - counter +vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_B.overlay b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_B.overlay similarity index 100% rename from boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_B.overlay rename to boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_B.overlay diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.overlay b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.overlay similarity index 100% rename from boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.overlay rename to boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.overlay diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml new file mode 100644 index 00000000000..1d99009466c --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml @@ -0,0 +1,19 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32z2xxdc2@D/s32z270/rtu1 +name: NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores (rev. D) +type: mcu +arch: arm +ram: 1024 +toolchain: + - zephyr +supported: + - uart + - gpio + - watchdog + - netif:eth + - can + - spi + - counter +vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig new file mode 100644 index 00000000000..d7f502c0af0 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig @@ -0,0 +1,11 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n +CONFIG_ISR_STACK_SIZE=512 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 +CONFIG_ARM_MPU=y +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y diff --git a/boards/arm/s32z270dc2_r52/support/debug.cmm b/boards/nxp/s32z2xxdc2/support/debug.cmm similarity index 77% rename from boards/arm/s32z270dc2_r52/support/debug.cmm rename to boards/nxp/s32z2xxdc2/support/debug.cmm index f4e524ff388..6c5054a5bd0 100644 --- a/boards/arm/s32z270dc2_r52/support/debug.cmm +++ b/boards/nxp/s32z2xxdc2/support/debug.cmm @@ -1,8 +1,8 @@ ;******************************************************************************* -; Copyright 2022 NXP * +; Copyright 2022,2024 NXP * ; SPDX-License-Identifier: Apache-2.0 * ; * -; Lauterbach TRACE32 start-up script for debugging s32z270dc2_r52 * +; Lauterbach TRACE32 start-up script for debugging s32z2xxdc2 * ; * ;******************************************************************************* diff --git a/boards/arm/s32z270dc2_r52/support/flash.cmm b/boards/nxp/s32z2xxdc2/support/flash.cmm similarity index 77% rename from boards/arm/s32z270dc2_r52/support/flash.cmm rename to boards/nxp/s32z2xxdc2/support/flash.cmm index 60e3c103a3f..1bfad445e83 100644 --- a/boards/arm/s32z270dc2_r52/support/flash.cmm +++ b/boards/nxp/s32z2xxdc2/support/flash.cmm @@ -1,8 +1,8 @@ ;******************************************************************************* -; Copyright 2022 NXP * +; Copyright 2022,2024 NXP * ; SPDX-License-Identifier: Apache-2.0 * ; * -; Lauterbach TRACE32 start-up script for flashing s32z270dc2_r52 * +; Lauterbach TRACE32 start-up script for flashing s32z2xxdc2 * ; * ;******************************************************************************* diff --git a/boards/arm/s32z270dc2_r52/support/startup.cmm b/boards/nxp/s32z2xxdc2/support/startup.cmm similarity index 100% rename from boards/arm/s32z270dc2_r52/support/startup.cmm rename to boards/nxp/s32z2xxdc2/support/startup.cmm diff --git a/boards/arm/twr_ke18f/CMakeLists.txt b/boards/nxp/twr_ke18f/CMakeLists.txt similarity index 100% rename from boards/arm/twr_ke18f/CMakeLists.txt rename to boards/nxp/twr_ke18f/CMakeLists.txt diff --git a/boards/arm/twr_ke18f/Kconfig b/boards/nxp/twr_ke18f/Kconfig similarity index 100% rename from boards/arm/twr_ke18f/Kconfig rename to boards/nxp/twr_ke18f/Kconfig diff --git a/boards/nxp/twr_ke18f/Kconfig.defconfig b/boards/nxp/twr_ke18f/Kconfig.defconfig new file mode 100644 index 00000000000..46d718137c5 --- /dev/null +++ b/boards/nxp/twr_ke18f/Kconfig.defconfig @@ -0,0 +1,17 @@ +# TWR-KE18F board + +# Copyright (c) 2019 Vestas Wind Systems A/S +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_TWR_KE18F + +config I2C_MCUX_LPI2C_BUS_RECOVERY + default y + depends on I2C_MCUX_LPI2C && PINCTRL + +# The KE1xF has 8 MPU regions, which is not enough for both HW stack protection +# and userspace. Only enable HW stack protection if userspace is not enabled. +config HW_STACK_PROTECTION + default y if !USERSPACE + +endif # BOARD_TWR_KE18F diff --git a/boards/nxp/twr_ke18f/Kconfig.twr_ke18f b/boards/nxp/twr_ke18f/Kconfig.twr_ke18f new file mode 100644 index 00000000000..dbd881ae4b4 --- /dev/null +++ b/boards/nxp/twr_ke18f/Kconfig.twr_ke18f @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TWR_KE18F + select SOC_MKE18F16 + select SOC_PART_NUMBER_MKE18F512VLL16 diff --git a/boards/arm/twr_ke18f/board.cmake b/boards/nxp/twr_ke18f/board.cmake similarity index 100% rename from boards/arm/twr_ke18f/board.cmake rename to boards/nxp/twr_ke18f/board.cmake diff --git a/boards/nxp/twr_ke18f/board.yml b/boards/nxp/twr_ke18f/board.yml new file mode 100644 index 00000000000..ffaf5fb235f --- /dev/null +++ b/boards/nxp/twr_ke18f/board.yml @@ -0,0 +1,5 @@ +board: + name: twr_ke18f + vendor: nxp + socs: + - name: mke18f16 diff --git a/boards/arm/twr_ke18f/doc/TWR-KE18F-DEVICE.jpg b/boards/nxp/twr_ke18f/doc/TWR-KE18F-DEVICE.jpg similarity index 100% rename from boards/arm/twr_ke18f/doc/TWR-KE18F-DEVICE.jpg rename to boards/nxp/twr_ke18f/doc/TWR-KE18F-DEVICE.jpg diff --git a/boards/nxp/twr_ke18f/doc/index.rst b/boards/nxp/twr_ke18f/doc/index.rst new file mode 100644 index 00000000000..a72227beb67 --- /dev/null +++ b/boards/nxp/twr_ke18f/doc/index.rst @@ -0,0 +1,254 @@ +.. _twr_ke18f: + +NXP TWR-KE18F +############# + +Overview +******** + +The TWR-KE18F is a development board for NXP Kinetis KE1xF 32-bit +MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, +running an open source bootloader, offers options for serial +communication, flash programming, and run-control debugging. + +.. figure:: TWR-KE18F-DEVICE.jpg + :align: center + :alt: TWR-KE18F + + TWR-KE18F (Credit: NXP) + +Hardware +******** + +- MKE18F512VLL16 MCU (up to 168 MHz, 512 KB flash memory, 64 KB RAM, + and 100 Low profile Quad Flat Package (LQFP)) +- 3.3 V or 5 V MCU operation +- 6-axis FXOS8700CQ digital accelerometer and magnetometer +- RGB LED +- Four user LEDs +- Two user push-buttons +- Potentiometer +- Thermistor +- Infrared port (IrDA) +- CAN pin header +- Flex I/O pin header + +For more information about the KE1xF SoC and the TWR-KE18F board, see +these NXP reference documents: + +- `KE1xF Website`_ +- `KE1xF Datasheet`_ +- `KE1xF Reference Manual`_ +- `TWR-KE18F Website`_ +- `TWR-KE18F User Guide`_ +- `TWR-KE18F Schematics`_ + +Supported Features +================== + +The twr_ke18f board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | trigger supported with H/W mods | +| | | explained below; | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| ACMP | on-chip | analog comparator | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/twr_ke18f/twr_ke18f_defconfig`. + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The KE18 SoC is configured to use the 8 MHz external oscillator on the +board with the on-chip PLL to generate a 120 MHz system clock. + +Serial Port +=========== + +The KE18 SoC has three UARTs. UART0 is configured for the console. The +remaining UARTs are not used. + +Accelerometer and magnetometer +============================== + +The TWR-KE18F board by default only supports polling the FXOS8700 +accelerometer and magnetometer for sensor values +(``CONFIG_FXOS8700_TRIGGER_NONE=y``). + +In order to support FXOS8700 triggers (interrupts) the 0 ohm resistors +``R47`` and ``R57`` must be mounted on the TWR-KE18F board. The +devicetree must also be modified to describe the FXOS8700 interrupt +GPIOs: + +.. code-block:: devicetree + + /dts-v1/; + + &fxos8700 { + int1-gpios = <&gpioa 14 0>; + int2-gpios = <&gpioc 17 0>; + }; + +Finally, a trigger option must be enabled in Kconfig (either +``FXOS8700_TRIGGER_GLOBAL_THREAD=y`` or +``FXOS8700_TRIGGER_OWN_THREAD=y``). + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) +------------------------------------------------------------------ + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program +the `OpenSDA DAPLink TWR-KE18F Firmware`_. + +Option 2: :ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Firmware for TWR-KE18F`_. + +Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and +``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the +default runner from pyOCD to J-Link: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twr_ke18f + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J2. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twr_ke18f + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! twr_ke18f + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twr_ke18f + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! twr_ke18f + +.. _TWR-KE18F Website: + https://www.nxp.com/TWR-KE18F + +.. _TWR-KE18F User Guide: + https://www.nxp.com/docs/en/user-guide/TWRKE18FUG.pdf + +.. _TWR-KE18F Schematics: + https://www.nxp.com/webapp/Download?colCode=TWR-KE18F-SCH-DESIGNFILES + +.. _KE1xF Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/e-series5v-robustm0-plus-m4/kinetis-ke1xf-168mhz-performance-with-can-5v-microcontrollers-based-on-arm-cortex-m4:KE1xF + +.. _KE1xF Datasheet: + https://www.nxp.com/docs/en/data-sheet/KE1xFP100M168SF0.pdf + +.. _KE1xF Reference Manual: + https://www.nxp.com/docs/en/reference-manual/KE1xFP100M168SF0RM.pdf + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _OpenSDA DAPLink TWR-KE18F Firmware: + https://www.nxp.com/support/developer-resources/run-time-software/kinetis-developer-resources/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA#TWR-KE18F + +.. _OpenSDA J-Link Firmware for TWR-KE18F: + https://www.segger.com/downloads/jlink/OpenSDA_TWR-KE18F diff --git a/boards/arm/twr_ke18f/dts/bindings/nxp,flexio.yaml b/boards/nxp/twr_ke18f/dts/bindings/nxp,flexio.yaml similarity index 100% rename from boards/arm/twr_ke18f/dts/bindings/nxp,flexio.yaml rename to boards/nxp/twr_ke18f/dts/bindings/nxp,flexio.yaml diff --git a/boards/arm/twr_ke18f/dts/lpspi0_pcs2.overlay b/boards/nxp/twr_ke18f/dts/lpspi0_pcs2.overlay similarity index 100% rename from boards/arm/twr_ke18f/dts/lpspi0_pcs2.overlay rename to boards/nxp/twr_ke18f/dts/lpspi0_pcs2.overlay diff --git a/boards/arm/twr_ke18f/dts/lpspi1_pcs0.overlay b/boards/nxp/twr_ke18f/dts/lpspi1_pcs0.overlay similarity index 100% rename from boards/arm/twr_ke18f/dts/lpspi1_pcs0.overlay rename to boards/nxp/twr_ke18f/dts/lpspi1_pcs0.overlay diff --git a/boards/arm/twr_ke18f/dts/lpspi1_pcs0_pcs2.overlay b/boards/nxp/twr_ke18f/dts/lpspi1_pcs0_pcs2.overlay similarity index 100% rename from boards/arm/twr_ke18f/dts/lpspi1_pcs0_pcs2.overlay rename to boards/nxp/twr_ke18f/dts/lpspi1_pcs0_pcs2.overlay diff --git a/boards/arm/twr_ke18f/dts/lpspi1_pcs2.overlay b/boards/nxp/twr_ke18f/dts/lpspi1_pcs2.overlay similarity index 100% rename from boards/arm/twr_ke18f/dts/lpspi1_pcs2.overlay rename to boards/nxp/twr_ke18f/dts/lpspi1_pcs2.overlay diff --git a/boards/arm/twr_ke18f/pinmux.c b/boards/nxp/twr_ke18f/pinmux.c similarity index 100% rename from boards/arm/twr_ke18f/pinmux.c rename to boards/nxp/twr_ke18f/pinmux.c diff --git a/boards/arm/twr_ke18f/twr_ke18f-pinctrl.dtsi b/boards/nxp/twr_ke18f/twr_ke18f-pinctrl.dtsi similarity index 100% rename from boards/arm/twr_ke18f/twr_ke18f-pinctrl.dtsi rename to boards/nxp/twr_ke18f/twr_ke18f-pinctrl.dtsi diff --git a/boards/arm/twr_ke18f/twr_ke18f.dts b/boards/nxp/twr_ke18f/twr_ke18f.dts similarity index 100% rename from boards/arm/twr_ke18f/twr_ke18f.dts rename to boards/nxp/twr_ke18f/twr_ke18f.dts diff --git a/boards/arm/twr_ke18f/twr_ke18f.yaml b/boards/nxp/twr_ke18f/twr_ke18f.yaml similarity index 100% rename from boards/arm/twr_ke18f/twr_ke18f.yaml rename to boards/nxp/twr_ke18f/twr_ke18f.yaml diff --git a/boards/nxp/twr_ke18f/twr_ke18f_defconfig b/boards/nxp/twr_ke18f/twr_ke18f_defconfig new file mode 100644 index 00000000000..1890a440902 --- /dev/null +++ b/boards/nxp/twr_ke18f/twr_ke18f_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_PINCTRL=y +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y diff --git a/boards/arm64/roc_rk3568_pc/CMakeLists.txt b/boards/nxp/twr_kv58f220m/CMakeLists.txt similarity index 100% rename from boards/arm64/roc_rk3568_pc/CMakeLists.txt rename to boards/nxp/twr_kv58f220m/CMakeLists.txt diff --git a/boards/nxp/twr_kv58f220m/Kconfig.defconfig b/boards/nxp/twr_kv58f220m/Kconfig.defconfig new file mode 100644 index 00000000000..e77978b430a --- /dev/null +++ b/boards/nxp/twr_kv58f220m/Kconfig.defconfig @@ -0,0 +1,20 @@ +# TWR-KV58F220M board + +# Copyright (c) 2019 SEAL AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_TWR_KV58F220M + +config OSC_XTAL0_FREQ + default 50000000 + +config MCG_PRDIV0 + default 0x3 + +config MCG_VDIV0 + default 0x16 + +config MCG_FCRDIV + default 1 + +endif # BOARD_TWR_KV58F220M diff --git a/boards/nxp/twr_kv58f220m/Kconfig.twr_kv58f220m b/boards/nxp/twr_kv58f220m/Kconfig.twr_kv58f220m new file mode 100644 index 00000000000..280f8b625a4 --- /dev/null +++ b/boards/nxp/twr_kv58f220m/Kconfig.twr_kv58f220m @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TWR_KV58F220M + select SOC_MKV58F24 + select SOC_PART_NUMBER_MKV58F1M0VLQ24 diff --git a/boards/arm/twr_kv58f220m/board.cmake b/boards/nxp/twr_kv58f220m/board.cmake similarity index 100% rename from boards/arm/twr_kv58f220m/board.cmake rename to boards/nxp/twr_kv58f220m/board.cmake diff --git a/boards/nxp/twr_kv58f220m/board.yml b/boards/nxp/twr_kv58f220m/board.yml new file mode 100644 index 00000000000..536e16c178f --- /dev/null +++ b/boards/nxp/twr_kv58f220m/board.yml @@ -0,0 +1,5 @@ +board: + name: twr_kv58f220m + vendor: nxp + socs: + - name: mkv58f24 diff --git a/boards/nxp/twr_kv58f220m/doc/index.rst b/boards/nxp/twr_kv58f220m/doc/index.rst new file mode 100644 index 00000000000..98cc3a880af --- /dev/null +++ b/boards/nxp/twr_kv58f220m/doc/index.rst @@ -0,0 +1,200 @@ +.. _twr_kv58f220m: + +NXP TWR-KV58F220M +################# + +Overview +******** + +The TWR-KV58F220M is a development board for NXP Kinetis KV5x 32-bit +MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, +running an open source bootloader, offers options for serial +communication, flash programming, and run-control debugging. + +.. figure:: twr_kv58f220m.jpg + :align: center + :alt: TWR-KV58F220M + + TWR-KV58F220M (Credit: NXP) + +Hardware +******** + +- MKV58F1M0VLQ24 MCU (up to 240 MHz, 1 MB flash memory, 256 KB RAM, + and 144 Low profile Quad Flat Package (LQFP)) +- 1.8 V or 3.3 V MCU operation +- 6-axis FXOS8700CQ digital accelerometer and magnetometer +- Four user LEDs +- Four user push-buttons +- Potentiometer +- Two general purpose TWRPI headers +- Motor pin header + +For more information about the KV5x SoC and the TWR-KV58F220M board, see +these NXP reference documents: + +- `KV5x Website`_ +- `KV5x Datasheet`_ +- `KV5x Reference Manual`_ +- `TWR-KV58F220M Website`_ +- `TWR-KV58F220M User Guide`_ +- `TWR-KV58F220M Schematics`_ + +Supported Features +================== + +The twr_kv58f220m board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig`. + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The KV58 SoC is configured to use the 50 MHz external oscillator on the +board with the on-chip PLL to generate a 237.5 MHz system clock. + +Serial Port +=========== + +The KV58 SoC has six UARTs. UART0 is configured for the console. The +remaining UARTs are not used. + +Accelerometer and magnetometer +============================== + +The TWR-KV58F220M board by default only supports polling the FXOS8700 +accelerometer and magnetometer for sensor values +(``CONFIG_FXOS8700_TRIGGER_NONE=y``). + +In order to support FXOS8700 triggers (interrupts), shunts must be placed on +the jumpers ``J2`` and ``J9``. A trigger option also must be enabled in Kconfig +(either ``CONFIG_FXOS8700_TRIGGER_GLOBAL_THREAD=y`` or +``CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y``). + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +This board integrates an OpenSDA debug probe. However, it can currently only be +used for flashing the KV58 SoC by copying the compiled firmware to the USB Mass +Storage Device. The board cannot be debugged using the OpenSDA probe, since +pyOCD does not support the target. The OpenSDA J-Link firmware (as of release +2019-06-03) also cannot be used, since the flash algorithm for the KV58 seems to +be broken at the time of writing. + +An external J-Link debug probe connected to the JTAG header J13 is used to debug +the target. + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :tool: all + :board: twr_kv58f220m + :goals: build + +Configuring a Console +===================== + +Even though the OpenSDA probe cannot be used for debugging, we will use it as a +USB-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J22. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twr_kv58f220m + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! twr_kv58f220m + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twr_kv58f220m + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! twr_kv58f220m + +.. _TWR-KV58F220M Website: + https://www.nxp.com/TWR-KV58F220M + +.. _TWR-KV58F220M User Guide: + https://www.nxp.com/webapp/Download?colCode=TWRKV58F220MUG + +.. _TWR-KV58F220M Schematics: + https://www.nxp.com/webapp/Download?colCode=TWR-KV58F220M-SCH + +.. _KV5x Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/general-purpose-mcus/kv-series-cortex-m4-m0-plus-m7/kinetis-kv5x-240-mhz-motor-control-and-power-conversion-ethernet-mcus-based-on-arm-cortex-m7:KV5x + +.. _KV5x Datasheet: + https://www.nxp.com/docs/en/data-sheet/KV5XP144M240.pdf + +.. _KV5x Reference Manual: + https://www.nxp.com/webapp/Download?colCode=KV5XP144M240RM diff --git a/boards/arm/twr_kv58f220m/doc/twr_kv58f220m.jpg b/boards/nxp/twr_kv58f220m/doc/twr_kv58f220m.jpg similarity index 100% rename from boards/arm/twr_kv58f220m/doc/twr_kv58f220m.jpg rename to boards/nxp/twr_kv58f220m/doc/twr_kv58f220m.jpg diff --git a/boards/arm/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi b/boards/nxp/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi similarity index 100% rename from boards/arm/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi rename to boards/nxp/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi diff --git a/boards/arm/twr_kv58f220m/twr_kv58f220m.dts b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts similarity index 100% rename from boards/arm/twr_kv58f220m/twr_kv58f220m.dts rename to boards/nxp/twr_kv58f220m/twr_kv58f220m.dts diff --git a/boards/arm/twr_kv58f220m/twr_kv58f220m.yaml b/boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml similarity index 100% rename from boards/arm/twr_kv58f220m/twr_kv58f220m.yaml rename to boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml diff --git a/boards/arm/twr_kv58f220m/twr_kv58f220m_defconfig b/boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig similarity index 75% rename from boards/arm/twr_kv58f220m/twr_kv58f220m_defconfig rename to boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig index c46bf43c2a6..88afd604b5b 100644 --- a/boards/arm/twr_kv58f220m/twr_kv58f220m_defconfig +++ b/boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_KINETIS_KV5X=y -CONFIG_SOC_MKV58F24=y -CONFIG_BOARD_TWR_KV58F220M=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/nxp/ucans32k1sic/Kconfig.defconfig b/boards/nxp/ucans32k1sic/Kconfig.defconfig new file mode 100644 index 00000000000..9c6542625ba --- /dev/null +++ b/boards/nxp/ucans32k1sic/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UCANS32K1SIC + +if SERIAL + +config UART_CONSOLE + default y + +endif # SERIAL + +if CAN + +config GPIO + default y + +endif # CAN + +endif # BOARD_UCANS32K1SIC diff --git a/boards/nxp/ucans32k1sic/Kconfig.ucans32k1sic b/boards/nxp/ucans32k1sic/Kconfig.ucans32k1sic new file mode 100644 index 00000000000..26ec94435f4 --- /dev/null +++ b/boards/nxp/ucans32k1sic/Kconfig.ucans32k1sic @@ -0,0 +1,6 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UCANS32K1SIC + select SOC_S32K146 + select SOC_PART_NUMBER_FS32K146UAT0VLHT diff --git a/boards/arm/ucans32k1sic/board.cmake b/boards/nxp/ucans32k1sic/board.cmake similarity index 100% rename from boards/arm/ucans32k1sic/board.cmake rename to boards/nxp/ucans32k1sic/board.cmake diff --git a/boards/nxp/ucans32k1sic/board.yml b/boards/nxp/ucans32k1sic/board.yml new file mode 100644 index 00000000000..87964b5201f --- /dev/null +++ b/boards/nxp/ucans32k1sic/board.yml @@ -0,0 +1,5 @@ +board: + name: ucans32k1sic + vendor: nxp + socs: + - name: s32k146 diff --git a/boards/arm/ucans32k1sic/doc/img/ucans32k1sic_top.webp b/boards/nxp/ucans32k1sic/doc/img/ucans32k1sic_top.webp similarity index 100% rename from boards/arm/ucans32k1sic/doc/img/ucans32k1sic_top.webp rename to boards/nxp/ucans32k1sic/doc/img/ucans32k1sic_top.webp diff --git a/boards/nxp/ucans32k1sic/doc/index.rst b/boards/nxp/ucans32k1sic/doc/index.rst new file mode 100644 index 00000000000..969d67e815a --- /dev/null +++ b/boards/nxp/ucans32k1sic/doc/index.rst @@ -0,0 +1,197 @@ +.. _ucans32k1sic: + +NXP UCANS32K1SIC +################ + +Overview +******** + +`NXP UCANS32K1SIC`_ is a CAN signal improvement capability (SIC) evaluation +board designed for both automotive and industrial applications. The UCANS32K1SIC +provides two CAN SIC interfaces and is based on the 32-bit Arm Cortex-M4F +`NXP S32K146`_ microcontroller. + +.. image:: img/ucans32k1sic_top.webp + :align: center + :alt: NXP UCANS32K1SIC (TOP) + +Hardware +******** + +- NXP S32K146 + - Arm Cortex-M4F @ up to 112 Mhz + - 1 MB Flash + - 128 KB SRAM + - up to 127 I/Os + - 3x FlexCAN with 2x FD + - eDMA, 12-bit ADC, MPU, ECC and more. + +- Interfaces: + - DCD-LZ debug interface with SWD + Console / UART + - Dual CAN FD PHYs with dual connectors for daisy chain operation + - JST-GH DroneCode compliant standard connectors and I/O headers + - user RGB LED and button. + +More information about the hardware and design resources can be found at +`NXP UCANS32K1SIC`_ website. + +Supported Features +================== + +The ``ucans32k1sic`` board configuration supports the following hardware features: + +============ ========== ================================ +Interface Controller Driver/Component +============ ========== ================================ +SYSMPU on-chip mpu +PORT on-chip pinctrl +GPIO on-chip gpio +LPUART on-chip serial +LPI2C on-chip i2c +LPSPI on-chip spi +FTM on-chip pwm +FlexCAN on-chip can +Watchdog on-chip watchdog +RTC on-chip counter +============ ========== ================================ + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/nxp/ucans32k1sic/ucans32k1sic_defconfig`. + +Connections and IOs +=================== + +This board has 5 GPIO ports named from ``gpioa`` to ``gpioe``. + +Pin control can be further configured from your application overlay by adding +children nodes with the desired pinmux configuration to the singleton node +``pinctrl``. Supported properties are described in +:zephyr_file:`dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml`. + +LEDs +---- + +The UCANS32K1SIC board has one user RGB LED that can be used either as a GPIO +LED or as a PWM LED. + +.. table:: RGB LED as GPIO LED + :widths: auto + + =============== ================ =============== ===== + Devicetree node Devicetree alias Label Pin + =============== ================ =============== ===== + led1_red led0 LED1_RGB_RED PTD15 + led1_green led1 LED1_RGB_GREEN PTD16 + led1_blue led2 LED1_RGB_BLUE PTD0 + =============== ================ =============== ===== + +.. table:: RGB LED as PWM LED + :widths: auto + + =============== ======================== ================== ================ + Devicetree node Devicetree alias Label Pin + =============== ======================== ================== ================ + led1_red_pwm pwm-led0 / red-pwm-led LED1_RGB_RED_PWM PTD15 / FTM0_CH0 + led1_green_pwm pwm-led1 / green-pwm-led LED1_RGB_GREEN_PWM PTD16 / FTM0_CH1 + led1_blue_pwm pwm-led2 / blue-pwm-led LED1_RGB_BLUE_PWM PTD0 / FTM0_CH2 + =============== ======================== ================== ================ + +The user can control the LEDs in any way. An output of ``0`` illuminates the LED. + +Buttons +------- + +The UCANS32K1SIC board has one user button: + +======================= ============== ===== +Devicetree node Label Pin +======================= ============== ===== +sw0 / button_3 SW3 PTD15 +======================= ============== ===== + +Serial Console +============== + +The serial console is provided via ``lpuart1`` on the 7-pin DCD-LZ debug +connector ``P6``. + +========= ===== ============ +Connector Pin Pin Function +========= ===== ============ +P6.2 PTC7 LPUART1_TX +P6.3 PTC6 LPUART1_RX +========= ===== ============ + +System Clock +============ + +The Arm Cortex-M4F core is configured to run at 80 MHz (RUN mode). + +Programming and Debugging +************************* + +Applications for the ``ucans32k1sic`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +This board configuration supports `Lauterbach TRACE32`_ and `SEGGER J-Link`_ +West runners for flashing and debugging applications. Follow the steps described +in :ref:`lauterbach-trace32-debug-host-tools` and :ref:`jlink-debug-host-tools`, +to setup the flash and debug host tools for these runners, respectively. The +default runner is J-Link. + +Flashing +======== + +Run the ``west flash`` command to flash the application using SEGGER J-Link. +Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32. + +The Lauterbach TRACE32 runner supports additional options that can be passed +through command line: + +.. code-block:: console + + west flash -r trace32 --startup-args elfFile= loadTo= + eraseFlash= verifyFlash= + +Where: + +- ```` is the path to the Zephyr application ELF in the output + directory +- ``loadTo=flash`` loads the application to the SoC internal program flash + (:kconfig:option:`CONFIG_XIP` must be set), and ``loadTo=sram`` load the + application to SRAM. The default is ``flash``. +- ``eraseFlash=yes`` erases the whole content of SoC internal flash before the + application is downloaded to either Flash or SRAM. This routine takes time to + execute. The default is ``no``. +- ``verifyFlash=yes`` verify the SoC internal flash content after programming + (use together with ``loadTo=flash``). The default is ``no``. + +For example, to erase and verify flash content: + +.. code-block:: console + + west flash -r trace32 --startup-args elfFile=build/zephyr/zephyr.elf loadTo=flash eraseFlash=yes verifyFlash=yes + +Debugging +========= + +Run the ``west debug`` command to start a GDB session using SEGGER J-Link. +Alternatively, run ``west debug -r trace32`` to launch the Lauterbach TRACE32 +software debugging interface. + +References +********** + +.. target-notes:: + +.. _NXP UCANS32K1SIC: + https://www.nxp.com/design/development-boards/analog-toolbox/can-sic-evaluation-board:UCANS32K1SIC + +.. _NXP S32K146: + https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k1-microcontrollers-for-automotive-general-purpose:S32K1 + +.. _Lauterbach TRACE32: + https://www.lauterbach.com + +.. _SEGGER J-Link: + https://wiki.segger.com/S32Kxxx diff --git a/boards/arm/ucans32k1sic/support/debug.cmm b/boards/nxp/ucans32k1sic/support/debug.cmm similarity index 100% rename from boards/arm/ucans32k1sic/support/debug.cmm rename to boards/nxp/ucans32k1sic/support/debug.cmm diff --git a/boards/arm/ucans32k1sic/support/flash.cmm b/boards/nxp/ucans32k1sic/support/flash.cmm similarity index 100% rename from boards/arm/ucans32k1sic/support/flash.cmm rename to boards/nxp/ucans32k1sic/support/flash.cmm diff --git a/boards/arm/ucans32k1sic/support/startup.cmm b/boards/nxp/ucans32k1sic/support/startup.cmm similarity index 100% rename from boards/arm/ucans32k1sic/support/startup.cmm rename to boards/nxp/ucans32k1sic/support/startup.cmm diff --git a/boards/arm/ucans32k1sic/ucans32k1sic-pinctrl.dtsi b/boards/nxp/ucans32k1sic/ucans32k1sic-pinctrl.dtsi similarity index 100% rename from boards/arm/ucans32k1sic/ucans32k1sic-pinctrl.dtsi rename to boards/nxp/ucans32k1sic/ucans32k1sic-pinctrl.dtsi diff --git a/boards/arm/ucans32k1sic/ucans32k1sic.dts b/boards/nxp/ucans32k1sic/ucans32k1sic.dts similarity index 100% rename from boards/arm/ucans32k1sic/ucans32k1sic.dts rename to boards/nxp/ucans32k1sic/ucans32k1sic.dts diff --git a/boards/arm/ucans32k1sic/ucans32k1sic.yaml b/boards/nxp/ucans32k1sic/ucans32k1sic.yaml similarity index 100% rename from boards/arm/ucans32k1sic/ucans32k1sic.yaml rename to boards/nxp/ucans32k1sic/ucans32k1sic.yaml diff --git a/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig b/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig new file mode 100644 index 00000000000..e852568a799 --- /dev/null +++ b/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig @@ -0,0 +1,17 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +# Use Systick as system clock +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000 + +# Run from internal program flash +CONFIG_XIP=y + +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y diff --git a/boards/arm64/rpi_4b/CMakeLists.txt b/boards/nxp/usb_kw24d512/CMakeLists.txt similarity index 100% rename from boards/arm64/rpi_4b/CMakeLists.txt rename to boards/nxp/usb_kw24d512/CMakeLists.txt diff --git a/boards/nxp/usb_kw24d512/Kconfig.defconfig b/boards/nxp/usb_kw24d512/Kconfig.defconfig new file mode 100644 index 00000000000..edee8ad53a3 --- /dev/null +++ b/boards/nxp/usb_kw24d512/Kconfig.defconfig @@ -0,0 +1,28 @@ +# USB-KW24D512 board + +# Copyright (c) 2017, Phytec Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_USB_KW24D512 + +config OSC_XTAL0_FREQ + # The MCU is configured to use 4 MHz external + # clock from the transceiver provided at the CLK_OUT output. + # CLK_OUT is internally connected to the input pin EXTAL0 + # of the MCU. + default 4000000 + +config MCG_PRDIV0 + default 0x1 + +config MCG_VDIV0 + default 0x0 + +config MCG_FCRDIV + default 2 + +config MCR20A_IS_PART_OF_KW2XD_SIP + default y + depends on IEEE802154_MCR20A + +endif # BOARD_USB_KW24D512 diff --git a/boards/nxp/usb_kw24d512/Kconfig.usb_kw24d512 b/boards/nxp/usb_kw24d512/Kconfig.usb_kw24d512 new file mode 100644 index 00000000000..768435783af --- /dev/null +++ b/boards/nxp/usb_kw24d512/Kconfig.usb_kw24d512 @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_USB_KW24D512 + select SOC_MKW24D5 + select SOC_PART_NUMBER_MKW24D512VHA5 diff --git a/boards/arm/usb_kw24d512/board.cmake b/boards/nxp/usb_kw24d512/board.cmake similarity index 100% rename from boards/arm/usb_kw24d512/board.cmake rename to boards/nxp/usb_kw24d512/board.cmake diff --git a/boards/nxp/usb_kw24d512/board.yml b/boards/nxp/usb_kw24d512/board.yml new file mode 100644 index 00000000000..21dae9f8435 --- /dev/null +++ b/boards/nxp/usb_kw24d512/board.yml @@ -0,0 +1,5 @@ +board: + name: usb_kw24d512 + vendor: nxp + socs: + - name: mkw24d5 diff --git a/boards/nxp/usb_kw24d512/doc/index.rst b/boards/nxp/usb_kw24d512/doc/index.rst new file mode 100644 index 00000000000..b617edcf6d6 --- /dev/null +++ b/boards/nxp/usb_kw24d512/doc/index.rst @@ -0,0 +1,230 @@ +.. _usb_kw24d512: + +NXP USB-KW24D512 +################ + +Overview +******** + +The USB-KW24D512 is an evaluation board in a convenient USB dongle +form factor based on the NXP MKW24D512 System-in-Package (SiP) device +(KW2xD wireless MCU series). +MKW24D512 wireless MCU provides a low-power, compact device with +integrated IEEE 802.15.4 radio. The board can be used as a packet sniffer, +network node, border router or as a development board. + +Hardware +******** + +- Kinetis KW2xD-2.4 GHz 802.15.4 Wireless Radio Microcontroller + (50 MHz, 512 KB flash memory, 64 KB RAM, low-power, crystal-less USB) +- USB Type A Connector +- Two blue LEDs +- One user push button +- One reset button +- Integrated PCB Folded F-type antenna +- 10-pin (0.05”) JTAG debug port for target MCU + +For more information about the KW2xD SiP and USB-KW24D512 board: + +- `KW2xD Website`_ +- `KW2xD Datasheet`_ +- `KW2xD Reference Manual`_ +- `USB-KW24D512 Website`_ +- `USB-KW24D512 Hardware Reference Manual`_ + +Supported Features +================== + +The USB-KW24D512 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| RNGA | on-chip | entropy; | +| | | random | ++-----------+------------+-------------------------------------+ +| FTFL | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/usb_kw24d512/usb_kw24d512_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The KW2xD SoC has five pairs of pinmux/gpio controllers. + ++-------+-----------------+--------------------------------------+ +| Name | Function | Usage | ++=======+=================+======================================+ +| PTA1 | UART0_RX | UART Console | ++-------+-----------------+--------------------------------------+ +| PTA2 | UART0_TX | UART Console | ++-------+-----------------+--------------------------------------+ +| PTC4 | GPIO | SW1 | ++-------+-----------------+--------------------------------------+ +| PTD4 | GPIO | Blue LED (D2) | ++-------+-----------------+--------------------------------------+ +| PTD5 | GPIO | Blue LED (D3) | ++-------+-----------------+--------------------------------------+ +| PTB10 | SPI1_PCS0 | internal connected to MCR20A | ++-------+-----------------+--------------------------------------+ +| PTB11 | SPI1_SCK | internal connected to MCR20A | ++-------+-----------------+--------------------------------------+ +| PTB16 | SPI1_SOUT | internal connected to MCR20A | ++-------+-----------------+--------------------------------------+ +| PTB17 | SPI1_SIN | internal connected to MCR20A | ++-------+-----------------+--------------------------------------+ +| PTB19 | GPIO | internal connected to MCR20A (Reset) | ++-------+-----------------+--------------------------------------+ +| PTB3 | GPIO | internal connected to MCR20A (IRQ_B) | ++-------+-----------------+--------------------------------------+ +| PTC0 | GPIO | internal connected to MCR20A (GPIO5) | ++-------+-----------------+--------------------------------------+ + +System Clock +============ + +USB-KW24D512 contains 32 MHz oscillator crystal, which is connected to the +clock pins of the radio transceiver. The MCU is configured to +use the 4 MHz external clock from the transceiver with the on-chip PLL +to generate a 48 MHz system clock. + +Serial Port +=========== + +The KW2xD SoC has three UARTs. One is configured and can be used for the +console, but it uses the same pins as the JTAG interface and is only +accessible via the JTAG SWD connector. + +USB +=== + +The KW2xD SoC has a USB OTG (USBOTG) controller that supports both +device and host functions. Only USB device function is supported in Zephyr +at the moment. The USB-KW24D512 board has a USB Type A connector and +can only be used in device mode. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`jlink-external-debug-probe`. + +:ref:`jlink-external-debug-probe` +--------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Attach a J-Link 10-pin connector to J1. + +Configuring a Console +===================== + +The console is available using `Segger RTT`_. + +Connect a USB cable from your PC to J5. + +Once you have started a debug session, run telnet: + +.. code-block:: console + + Trying 127.0.0.1... + Connected to localhost. + Escape character is '^]'. + SEGGER J-Link V6.44 - Real time terminal output + SEGGER J-Link ARM V10.1, SN=600111924 + Process: JLinkGDBServerCLExe + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: usb_kw24d512 + :goals: flash + +The Segger RTT console is only available during a debug session. Use ``attach`` +to start one: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: usb_kw24d512 + :goals: attach + +Run telnet as shown earlier, and you should see the following message in the +terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! usb_kw24d512 + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: usb_kw24d512 + :goals: debug + +Run telnet as shown earlier, step through the application in your debugger, and +you should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! usb_kw24d512 + +.. _USB-KW24D512 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/ieee-802.15.4-packet-sniffer-usb-dongle-form-factor:USB-KW24D512 + +.. _USB-KW24D512 Hardware Reference Manual: + https://www.nxp.com/webapp/Download?colCode=USB-KW2XHWRM + +.. _KW2xD Website: + https://www.nxp.com/products/wireless/thread/kinetis-kw2xd-2.4-ghz-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m4-core:KW2xD + +.. _KW2xD Datasheet: + https://www.nxp.com/docs/en/data-sheet/MKW2xDxxx.pdf + +.. _KW2xD Reference Manual: + https://www.nxp.com/webapp/Download?colCode=MKW2XDXXXRM + +.. _Segger RTT: + https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/ diff --git a/boards/arm/usb_kw24d512/usb_kw24d512-pinctrl.dtsi b/boards/nxp/usb_kw24d512/usb_kw24d512-pinctrl.dtsi similarity index 100% rename from boards/arm/usb_kw24d512/usb_kw24d512-pinctrl.dtsi rename to boards/nxp/usb_kw24d512/usb_kw24d512-pinctrl.dtsi diff --git a/boards/arm/usb_kw24d512/usb_kw24d512.dts b/boards/nxp/usb_kw24d512/usb_kw24d512.dts similarity index 100% rename from boards/arm/usb_kw24d512/usb_kw24d512.dts rename to boards/nxp/usb_kw24d512/usb_kw24d512.dts diff --git a/boards/arm/usb_kw24d512/usb_kw24d512.yaml b/boards/nxp/usb_kw24d512/usb_kw24d512.yaml similarity index 100% rename from boards/arm/usb_kw24d512/usb_kw24d512.yaml rename to boards/nxp/usb_kw24d512/usb_kw24d512.yaml diff --git a/boards/nxp/usb_kw24d512/usb_kw24d512_defconfig b/boards/nxp/usb_kw24d512/usb_kw24d512_defconfig new file mode 100644 index 00000000000..005cd998960 --- /dev/null +++ b/boards/nxp/usb_kw24d512/usb_kw24d512_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_RTT_CONSOLE=y +CONFIG_USE_SEGGER_RTT=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 +CONFIG_OSC_EXTERNAL=y diff --git a/boards/nxp/vmu_rt1170/CMakeLists.txt b/boards/nxp/vmu_rt1170/CMakeLists.txt new file mode 100644 index 00000000000..2a12ecb3611 --- /dev/null +++ b/boards/nxp/vmu_rt1170/CMakeLists.txt @@ -0,0 +1,26 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + set(RT1170_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1170") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1170 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(flexspi_nor_config.c) + zephyr_library_include_directories(${RT1170_BOARD_DIR}/xip) + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/vmu_rt1170/Kconfig.defconfig b/boards/nxp/vmu_rt1170/Kconfig.defconfig new file mode 100644 index 00000000000..f0f7bffa888 --- /dev/null +++ b/boards/nxp/vmu_rt1170/Kconfig.defconfig @@ -0,0 +1,38 @@ +# VMU_RT1170 board + +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_VMU_RT1170 + +if DISK_DRIVERS + +config IMX_USDHC_DAT3_PWR_TOGGLE + default y + +endif # DISK_DRIVERS + +if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 + default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 +endchoice + +endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +if NETWORKING + +config NET_L2_ETHERNET + default y if CPU_CORTEX_M7 # No cache memory support is required for driver + +config ETH_MCUX_PHY_RESET + default n + +config ETH_MCUX_RMII_EXT_CLK + default y + +endif # NETWORKING + + +endif # BOARD_VMU_RT1170 diff --git a/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 b/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 new file mode 100644 index 00000000000..cfd9ba449db --- /dev/null +++ b/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 @@ -0,0 +1,6 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_VMU_RT1170_MIMXRT1176_CM7 + select SOC_MIMXRT1176_CM7 + select SOC_PART_NUMBER_MIMXRT1176DVMAA diff --git a/boards/arm/vmu_rt1170/board.cmake b/boards/nxp/vmu_rt1170/board.cmake similarity index 100% rename from boards/arm/vmu_rt1170/board.cmake rename to boards/nxp/vmu_rt1170/board.cmake diff --git a/boards/nxp/vmu_rt1170/board.yml b/boards/nxp/vmu_rt1170/board.yml new file mode 100644 index 00000000000..91d9d2e83b2 --- /dev/null +++ b/boards/nxp/vmu_rt1170/board.yml @@ -0,0 +1,5 @@ +board: + name: vmu_rt1170 + vendor: nxp + socs: + - name: mimxrt1176 diff --git a/boards/arm/vmu_rt1170/doc/index.rst b/boards/nxp/vmu_rt1170/doc/index.rst similarity index 100% rename from boards/arm/vmu_rt1170/doc/index.rst rename to boards/nxp/vmu_rt1170/doc/index.rst diff --git a/boards/arm/vmu_rt1170/doc/vmu_rt1170.jpg b/boards/nxp/vmu_rt1170/doc/vmu_rt1170.jpg similarity index 100% rename from boards/arm/vmu_rt1170/doc/vmu_rt1170.jpg rename to boards/nxp/vmu_rt1170/doc/vmu_rt1170.jpg diff --git a/boards/nxp/vmu_rt1170/flexspi_nor_config.c b/boards/nxp/vmu_rt1170/flexspi_nor_config.c new file mode 100644 index 00000000000..85ad476cf84 --- /dev/null +++ b/boards/nxp/vmu_rt1170/flexspi_nor_config.c @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2019, MADMACHINE LIMITED + * + * refer to hal_nxp board file + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/*! + * @brief ROM API init + * + * Get the bootloader api entry address. + */ +void ROM_API_Init(void); + +/*! + * @brief Initialize Serial NOR devices via FLEXSPI + * + * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, struct flexspi_nor_config_t *config); + + + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +/* Config used for booting */ + +const struct flexspi_nor_config_t Qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackInternally, + .csHoldTime = 1u, + .csSetupTime = 1u, + .sflashPadType = kSerialFlash_1Pad, + .serialClkFreq = kFlexSpiSerialClk_80MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .lookupTable = { + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x03, RADDR_SDR, + FLEXSPI_1PAD, 0x18), + FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, + 0x04, STOP, + FLEXSPI_1PAD, 0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ + +/* Config used for code execution */ +const struct flexspi_nor_config_t g_flash_fast_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 1, + .csSetupTime = 1, + .deviceModeCfgEnable = 1, + .deviceModeType = kDeviceConfigCmdType_Spi2Xpi, + .waitTimeCfgCommands = 1, + .deviceModeSeq = { + .seqNum = 1, + .seqId = 6, /* See Lookup table for more details */ + .reserved = 0, + }, + .deviceModeArg = 2, /* Enable OPI DDR mode */ + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) + | (1u << kFlexSpiMiscOffset_DdrModeEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_200MHz, + .sflashA1Size = 64ul * 1024u * 1024u, + .busyOffset = 0u, + .busyBitPolarity = 0u, + .lookupTable = { + /* Read */ + [0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, + 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11), + [0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, + 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04), + [0 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, + 0x04, STOP, FLEXSPI_1PAD, 0x00), + + /* Write enable SPI */ + [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x06, STOP, FLEXSPI_1PAD, 0x00), + + /*Write Configuration Register 2 =01, Enable OPI DDR mode*/ + [4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x72, CMD_SDR, FLEXSPI_1PAD, 0x00), + [4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00), + [4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01), + + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, + .ipcmdSerialClkFreq = 1, + .serialNorType = 2, + .reserve2[0] = 0x7008200, +}; + + +__ramfunc int imxrt_reclock_initialize(void) +{ + const uint32_t instance = 1; + + volatile struct flexspi_nor_config_t bootConfig; + + memcpy((struct flexspi_nor_config_t *)&bootConfig, &g_flash_fast_config, + sizeof(struct flexspi_nor_config_t)); + bootConfig.memConfig.tag = FLEXSPI_CFG_BLK_TAG; + + ROM_API_Init(); + + ROM_FLEXSPI_NorFlash_Init(instance, (struct flexspi_nor_config_t *)&bootConfig); + + return 0; +} + +SYS_INIT(imxrt_reclock_initialize, PRE_KERNEL_1, 0); diff --git a/boards/arm/vmu_rt1170/vmu_rt1170-pinctrl.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi similarity index 100% rename from boards/arm/vmu_rt1170/vmu_rt1170-pinctrl.dtsi rename to boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi diff --git a/boards/arm/vmu_rt1170/vmu_rt1170.dts b/boards/nxp/vmu_rt1170/vmu_rt1170.dts similarity index 100% rename from boards/arm/vmu_rt1170/vmu_rt1170.dts rename to boards/nxp/vmu_rt1170/vmu_rt1170.dts diff --git a/boards/arm/vmu_rt1170/vmu_rt1170.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi similarity index 100% rename from boards/arm/vmu_rt1170/vmu_rt1170.dtsi rename to boards/nxp/vmu_rt1170/vmu_rt1170.dtsi diff --git a/boards/arm/vmu_rt1170/vmu_rt1170.yaml b/boards/nxp/vmu_rt1170/vmu_rt1170.yaml similarity index 89% rename from boards/arm/vmu_rt1170/vmu_rt1170.yaml rename to boards/nxp/vmu_rt1170/vmu_rt1170.yaml index 2eb4ce0e588..9446ece2d95 100644 --- a/boards/arm/vmu_rt1170/vmu_rt1170.yaml +++ b/boards/nxp/vmu_rt1170/vmu_rt1170.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: vmu_rt1170 +identifier: vmu_rt1170/mimxrt1176/cm7 name: NXP VMU RT1170 type: mcu arch: arm diff --git a/boards/arm/vmu_rt1170/vmu_rt1170_defconfig b/boards/nxp/vmu_rt1170/vmu_rt1170_defconfig similarity index 86% rename from boards/arm/vmu_rt1170/vmu_rt1170_defconfig rename to boards/nxp/vmu_rt1170/vmu_rt1170_defconfig index 875d84e7b64..e6d72e55f46 100644 --- a/boards/arm/vmu_rt1170/vmu_rt1170_defconfig +++ b/boards/nxp/vmu_rt1170/vmu_rt1170_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1176_CM7=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_SHELL=y CONFIG_UART_CONSOLE=y diff --git a/boards/olimex/index.rst b/boards/olimex/index.rst new file mode 100644 index 00000000000..17494488d61 --- /dev/null +++ b/boards/olimex/index.rst @@ -0,0 +1,10 @@ +.. _boards-olimex: + +OLIMEX Ltd. +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/olimex/lora_stm32wl_devkit/Kconfig.olimex_lora_stm32wl_devkit b/boards/olimex/lora_stm32wl_devkit/Kconfig.olimex_lora_stm32wl_devkit new file mode 100644 index 00000000000..f1c883d3577 --- /dev/null +++ b/boards/olimex/lora_stm32wl_devkit/Kconfig.olimex_lora_stm32wl_devkit @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Martin Jäger +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_LORA_STM32WL_DEVKIT + select SOC_STM32WLE5XX diff --git a/boards/arm/olimex_lora_stm32wl_devkit/board.cmake b/boards/olimex/lora_stm32wl_devkit/board.cmake similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/board.cmake rename to boards/olimex/lora_stm32wl_devkit/board.cmake diff --git a/boards/olimex/lora_stm32wl_devkit/board.yml b/boards/olimex/lora_stm32wl_devkit/board.yml new file mode 100644 index 00000000000..511de6634d2 --- /dev/null +++ b/boards/olimex/lora_stm32wl_devkit/board.yml @@ -0,0 +1,11 @@ +board: + name: olimex_lora_stm32wl_devkit + vendor: olimex + revision: + format: letter + default: "C" + revisions: + - name: "C" + - name: "D" + socs: + - name: stm32wle5xx diff --git a/boards/arm/olimex_lora_stm32wl_devkit/doc/olimex-stm32wl-devkit.jpg b/boards/olimex/lora_stm32wl_devkit/doc/olimex-stm32wl-devkit.jpg similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/doc/olimex-stm32wl-devkit.jpg rename to boards/olimex/lora_stm32wl_devkit/doc/olimex-stm32wl-devkit.jpg diff --git a/boards/arm/olimex_lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst b/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst similarity index 95% rename from boards/arm/olimex_lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst rename to boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst index cd7d3436296..84e219fc170 100644 --- a/boards/arm/olimex_lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst +++ b/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst @@ -81,10 +81,10 @@ hardware features: Other hardware features are not yet supported on this Zephyr port. -The default configuration can be found in the defconfig and dts files: +The default configuration can be found in: -- :zephyr_file:`boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig` -- :zephyr_file:`boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts` +- :zephyr_file:`boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig` +- :zephyr_file:`boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts` Programming and Debugging ************************* diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.conf b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.conf similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.conf rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.conf diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.overlay b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.overlay similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.overlay rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.overlay diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.yaml b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.yaml similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.yaml rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.yaml diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.conf b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.conf similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.conf rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.conf diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.overlay b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.overlay similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.overlay rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.overlay diff --git a/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml new file mode 100644 index 00000000000..29559d1e262 --- /dev/null +++ b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml @@ -0,0 +1,20 @@ +identifier: olimex_lora_stm32wl_devkit@D +name: Olimex LoRa STM32WL DevKit +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 64 +flash: 256 +supported: + - counter + - gpio + - i2c + - nvs + - spi + - uart + - watchdog + - lora +vendor: olimex diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig similarity index 83% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig index 5e6649fe25a..0d6dc9f80d3 100644 --- a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig +++ b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WLX=y -CONFIG_SOC_STM32WLE5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/olimex/olimex_esp32_evb/Kconfig b/boards/olimex/olimex_esp32_evb/Kconfig new file mode 100644 index 00000000000..c13221afa37 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_ESP32_EVB + select SOC_ESP32_PROCPU if BOARD_OLIMEX_ESP32_EVB_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_OLIMEX_ESP32_EVB_ESP32_APPCPU diff --git a/boards/olimex/olimex_esp32_evb/Kconfig.defconfig b/boards/olimex/olimex_esp32_evb/Kconfig.defconfig new file mode 100644 index 00000000000..c15264f5538 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Olimex ESP32-EVB board configuration + +# Copyright (c) 2022 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_OLIMEX_ESP32_EVB_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_OLIMEX_ESP32_EVB_ESP32_PROCPU + +if BOARD_OLIMEX_ESP32_EVB_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_OLIMEX_ESP32_EVB_ESP32_APPCPU diff --git a/boards/olimex/olimex_esp32_evb/Kconfig.olimex_esp32_evb b/boards/olimex/olimex_esp32_evb/Kconfig.olimex_esp32_evb new file mode 100644 index 00000000000..850460473ae --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/Kconfig.olimex_esp32_evb @@ -0,0 +1,7 @@ +# Olimex ESP32-EVB board configuration + +# Copyright (c) 2022 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_ESP32_EVB + select SOC_ESP32_WROVER_E_N8R2 diff --git a/boards/xtensa/odroid_go/Kconfig.sysbuild b/boards/olimex/olimex_esp32_evb/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/odroid_go/Kconfig.sysbuild rename to boards/olimex/olimex_esp32_evb/Kconfig.sysbuild diff --git a/boards/xtensa/m5stack_atoms3_lite/board.cmake b/boards/olimex/olimex_esp32_evb/board.cmake similarity index 100% rename from boards/xtensa/m5stack_atoms3_lite/board.cmake rename to boards/olimex/olimex_esp32_evb/board.cmake diff --git a/boards/olimex/olimex_esp32_evb/board.yml b/boards/olimex/olimex_esp32_evb/board.yml new file mode 100644 index 00000000000..8dc816efceb --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_esp32_evb + vendor: olimex + socs: + - name: esp32 diff --git a/boards/xtensa/olimex_esp32_evb/doc/ESP32-EVB.jpg b/boards/olimex/olimex_esp32_evb/doc/ESP32-EVB.jpg similarity index 100% rename from boards/xtensa/olimex_esp32_evb/doc/ESP32-EVB.jpg rename to boards/olimex/olimex_esp32_evb/doc/ESP32-EVB.jpg diff --git a/boards/olimex/olimex_esp32_evb/doc/index.rst b/boards/olimex/olimex_esp32_evb/doc/index.rst new file mode 100644 index 00000000000..38df52c4920 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/doc/index.rst @@ -0,0 +1,265 @@ +.. _olimex_esp32_evb: + +Olimex ESP32-EVB +################ + +Overview +******** + +The Olimex ESP32-EVB is an OSHW certified, open-source IoT board based on the +Espressif ESP32-WROOM-32E/UE module. It has a wired 100Mbit/s Ethernet Interface, +Bluetooth LE, WiFi, infrared remote control, and CAN connectivity. Two relays +allows switching power appliances on and off. + +The board can operate from a single LiPo backup battery as it has an internal +LiPo battery charger. There is no step-up converter, so relays, CAN, and USB +power does not work when running off battery. + +.. figure:: ESP32-EVB.jpg + :align: center + :alt: ESP32-EVB + + ESP32-EVB (Credit: Olimex) + +Hardware +******** + +- ESP32-WROOM-32E/UE module with 4MB flash. +- On-board programmer, CH340T USB-to-UART +- WiFi, Bluetooth LE connectivity. +- 100Mbit/s Ethernet interface, Microchip LAN8710A PHY. +- MicroSD card slot. +- 2 x 10A/250VAC (15A/120VAC 15A/24VDC) relays with connectors and status LEDs. +- CAN interface, Microchip MCP2562-E high-speed CAN transceiver. +- IR receiver and transmitter, up to 5 meters distance. +- BL4054B LiPo battery charger with status LEDs for stand-alone operation during + power outages. +- Power jack for external 5VDC power supply. +- Univeral EXTension (UEXT) connector for connecting UEXT modules. +- User push button. +- 40 pin GPIO connector with all ESP32 pins. + +For more information about the ESP32-EVB and the ESP32-WROOM-32E/UE module, see +these reference documents: + +- `ESP32-EVB Website`_ +- `ESP32-EVB Schematic`_ +- `ESP32-EVB GitHub Repository`_ +- `ESP32-WROOM32-E/UE Datasheet`_ + +Supported Features +****************** + +The olimex_esp32_evb board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| EFUSE | on-chip | hwinfo, device ID | ++-----------+------------+-------------------------------------+ +| FLASH | module | External flash | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | I2C | ++-----------+------------+-------------------------------------+ +| INTERRUPT | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| IO_MUX | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| TIMG | on-chip | counter | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| TWAI | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | uart | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| WiFi | on-chip | WiFi | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +``boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig``. + +Other hardware features are not currently supported by the port. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: olimex_esp32_evb + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: olimex_esp32_evb/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``olimex_esp32_evb`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: olimex_esp32_evb/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! olimex_esp32_evb + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: olimex_esp32_evb/esp32/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: olimex_esp32_evb/esp32/procpu + :goals: debug + +References +********** + +.. _ESP32-EVB Website: + https://www.olimex.com/Products/IoT/ESP32/ESP32-EVB/open-source-hardware + +.. _ESP32-EVB Schematic: + https://github.com/OLIMEX/ESP32-EVB/raw/master/HARDWARE/REV-I/ESP32-EVB_Rev_I.pdf + +.. _ESP32-EVB GitHub Repository: + https://github.com/OLIMEX/ESP32-EVB + +.. _ESP32-WROOM32-E/UE Datasheet: + https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32e_esp32-wroom-32ue_datasheet_en.pdf + +.. _OpenOCD ESP32: + https://github.com/espressif/openocd-esp32/releases diff --git a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb-pinctrl.dtsi b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb-pinctrl.dtsi similarity index 100% rename from boards/xtensa/olimex_esp32_evb/olimex_esp32_evb-pinctrl.dtsi rename to boards/olimex/olimex_esp32_evb/olimex_esp32_evb-pinctrl.dtsi diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.dts b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.dts new file mode 100644 index 00000000000..c52b029ea55 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Espressif ESP32-DevkitC APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.yaml b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.yaml new file mode 100644 index 00000000000..9e81868de21 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: olimex_esp32_evb/esp32/appcpu +name: Olimex ESP32-EVB +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig new file mode 100644 index 00000000000..6caadbd90ce --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y +CONFIG_CONSOLE=n +CONFIG_SERIAL=n +CONFIG_UART_CONSOLE=n +CONFIG_GPIO=n diff --git a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb.dts b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.dts similarity index 100% rename from boards/xtensa/olimex_esp32_evb/olimex_esp32_evb.dts rename to boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.dts diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.yaml b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.yaml new file mode 100644 index 00000000000..f4929c52b42 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.yaml @@ -0,0 +1,20 @@ +identifier: olimex_esp32_evb/esp32/procpu +name: Olimex ESP32-EVB +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - can + - counter + - gpio + - hwinfo + - i2c + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: olimex diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu_defconfig b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu_defconfig new file mode 100644 index 00000000000..f029cac9e9e --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/olimex_esp32_evb/support/openocd.cfg b/boards/olimex/olimex_esp32_evb/support/openocd.cfg similarity index 100% rename from boards/xtensa/olimex_esp32_evb/support/openocd.cfg rename to boards/olimex/olimex_esp32_evb/support/openocd.cfg diff --git a/boards/olimex/olimexino_stm32/Kconfig.defconfig b/boards/olimex/olimexino_stm32/Kconfig.defconfig new file mode 100644 index 00000000000..1f2ff6acf96 --- /dev/null +++ b/boards/olimex/olimexino_stm32/Kconfig.defconfig @@ -0,0 +1,12 @@ +# OLIMEXINO-STM32 board configuration + +# Copyright (c) 2016, I-SENSE group of ICCS +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_OLIMEXINO_STM32 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_OLIMEXINO_STM32 diff --git a/boards/olimex/olimexino_stm32/Kconfig.olimexino_stm32 b/boards/olimex/olimexino_stm32/Kconfig.olimexino_stm32 new file mode 100644 index 00000000000..523f1c99023 --- /dev/null +++ b/boards/olimex/olimexino_stm32/Kconfig.olimexino_stm32 @@ -0,0 +1,5 @@ +# Copyright (c) 2016, I-SENSE group of ICCS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEXINO_STM32 + select SOC_STM32F103XB diff --git a/boards/arm/olimexino_stm32/board.cmake b/boards/olimex/olimexino_stm32/board.cmake similarity index 100% rename from boards/arm/olimexino_stm32/board.cmake rename to boards/olimex/olimexino_stm32/board.cmake diff --git a/boards/olimex/olimexino_stm32/board.yml b/boards/olimex/olimexino_stm32/board.yml new file mode 100644 index 00000000000..0944c4bb280 --- /dev/null +++ b/boards/olimex/olimexino_stm32/board.yml @@ -0,0 +1,5 @@ +board: + name: olimexino_stm32 + vendor: olimex + socs: + - name: stm32f103xb diff --git a/boards/arm/olimexino_stm32/doc/img/olimexino-stm32-front.jpg b/boards/olimex/olimexino_stm32/doc/img/olimexino-stm32-front.jpg similarity index 100% rename from boards/arm/olimexino_stm32/doc/img/olimexino-stm32-front.jpg rename to boards/olimex/olimexino_stm32/doc/img/olimexino-stm32-front.jpg diff --git a/boards/arm/olimexino_stm32/doc/img/olimexino_stm32.jpg b/boards/olimex/olimexino_stm32/doc/img/olimexino_stm32.jpg similarity index 100% rename from boards/arm/olimexino_stm32/doc/img/olimexino_stm32.jpg rename to boards/olimex/olimexino_stm32/doc/img/olimexino_stm32.jpg diff --git a/boards/arm/olimexino_stm32/doc/index.rst b/boards/olimex/olimexino_stm32/doc/index.rst similarity index 100% rename from boards/arm/olimexino_stm32/doc/index.rst rename to boards/olimex/olimexino_stm32/doc/index.rst diff --git a/boards/arm/olimexino_stm32/olimexino_stm32.dts b/boards/olimex/olimexino_stm32/olimexino_stm32.dts similarity index 100% rename from boards/arm/olimexino_stm32/olimexino_stm32.dts rename to boards/olimex/olimexino_stm32/olimexino_stm32.dts diff --git a/boards/arm/olimexino_stm32/olimexino_stm32.yaml b/boards/olimex/olimexino_stm32/olimexino_stm32.yaml similarity index 100% rename from boards/arm/olimexino_stm32/olimexino_stm32.yaml rename to boards/olimex/olimexino_stm32/olimexino_stm32.yaml diff --git a/boards/arm/olimexino_stm32/olimexino_stm32_defconfig b/boards/olimex/olimexino_stm32/olimexino_stm32_defconfig similarity index 85% rename from boards/arm/olimexino_stm32/olimexino_stm32_defconfig rename to boards/olimex/olimexino_stm32/olimexino_stm32_defconfig index f8edab4b980..9472e788675 100644 --- a/boards/arm/olimexino_stm32/olimexino_stm32_defconfig +++ b/boards/olimex/olimexino_stm32/olimexino_stm32_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103XB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimexino_stm32/support/openocd.cfg b/boards/olimex/olimexino_stm32/support/openocd.cfg similarity index 100% rename from boards/arm/olimexino_stm32/support/openocd.cfg rename to boards/olimex/olimexino_stm32/support/openocd.cfg diff --git a/boards/olimex/stm32_e407/Kconfig.olimex_stm32_e407 b/boards/olimex/stm32_e407/Kconfig.olimex_stm32_e407 new file mode 100644 index 00000000000..0272cc31f5b --- /dev/null +++ b/boards/olimex/stm32_e407/Kconfig.olimex_stm32_e407 @@ -0,0 +1,5 @@ +# Copyright (c) 2017, Erwin Rol +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_STM32_E407 + select SOC_STM32F407XG diff --git a/boards/arm/black_f407zg_pro/board.cmake b/boards/olimex/stm32_e407/board.cmake similarity index 100% rename from boards/arm/black_f407zg_pro/board.cmake rename to boards/olimex/stm32_e407/board.cmake diff --git a/boards/olimex/stm32_e407/board.yml b/boards/olimex/stm32_e407/board.yml new file mode 100644 index 00000000000..b01060566dc --- /dev/null +++ b/boards/olimex/stm32_e407/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_stm32_e407 + vendor: olimex + socs: + - name: stm32f407xx diff --git a/boards/arm/olimex_stm32_e407/doc/img/olimex-stm32-e407-front.jpg b/boards/olimex/stm32_e407/doc/img/olimex-stm32-e407-front.jpg similarity index 100% rename from boards/arm/olimex_stm32_e407/doc/img/olimex-stm32-e407-front.jpg rename to boards/olimex/stm32_e407/doc/img/olimex-stm32-e407-front.jpg diff --git a/boards/arm/olimex_stm32_e407/doc/img/olimex_stm32_e407.jpg b/boards/olimex/stm32_e407/doc/img/olimex_stm32_e407.jpg similarity index 100% rename from boards/arm/olimex_stm32_e407/doc/img/olimex_stm32_e407.jpg rename to boards/olimex/stm32_e407/doc/img/olimex_stm32_e407.jpg diff --git a/boards/arm/olimex_stm32_e407/doc/index.rst b/boards/olimex/stm32_e407/doc/index.rst similarity index 100% rename from boards/arm/olimex_stm32_e407/doc/index.rst rename to boards/olimex/stm32_e407/doc/index.rst diff --git a/boards/arm/olimex_stm32_e407/olimex_stm32_e407.dts b/boards/olimex/stm32_e407/olimex_stm32_e407.dts similarity index 100% rename from boards/arm/olimex_stm32_e407/olimex_stm32_e407.dts rename to boards/olimex/stm32_e407/olimex_stm32_e407.dts diff --git a/boards/arm/olimex_stm32_e407/olimex_stm32_e407.yaml b/boards/olimex/stm32_e407/olimex_stm32_e407.yaml similarity index 100% rename from boards/arm/olimex_stm32_e407/olimex_stm32_e407.yaml rename to boards/olimex/stm32_e407/olimex_stm32_e407.yaml diff --git a/boards/arm/olimex_stm32_e407/olimex_stm32_e407_defconfig b/boards/olimex/stm32_e407/olimex_stm32_e407_defconfig similarity index 84% rename from boards/arm/olimex_stm32_e407/olimex_stm32_e407_defconfig rename to boards/olimex/stm32_e407/olimex_stm32_e407_defconfig index ad325266c72..c729b83e3d0 100644 --- a/boards/arm/olimex_stm32_e407/olimex_stm32_e407_defconfig +++ b/boards/olimex/stm32_e407/olimex_stm32_e407_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimex_stm32_e407/support/openocd.cfg b/boards/olimex/stm32_e407/support/openocd.cfg similarity index 100% rename from boards/arm/olimex_stm32_e407/support/openocd.cfg rename to boards/olimex/stm32_e407/support/openocd.cfg diff --git a/boards/olimex/stm32_h103/Kconfig.olimex_stm32_h103 b/boards/olimex/stm32_h103/Kconfig.olimex_stm32_h103 new file mode 100644 index 00000000000..d88ee02890a --- /dev/null +++ b/boards/olimex/stm32_h103/Kconfig.olimex_stm32_h103 @@ -0,0 +1,5 @@ +# Copyright (c) 2020, Josep Puigdemont +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_STM32_H103 + select SOC_STM32F103XB diff --git a/boards/arm/olimex_stm32_h103/board.cmake b/boards/olimex/stm32_h103/board.cmake similarity index 100% rename from boards/arm/olimex_stm32_h103/board.cmake rename to boards/olimex/stm32_h103/board.cmake diff --git a/boards/olimex/stm32_h103/board.yml b/boards/olimex/stm32_h103/board.yml new file mode 100644 index 00000000000..2917e4e19d9 --- /dev/null +++ b/boards/olimex/stm32_h103/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_stm32_h103 + vendor: olimex + socs: + - name: stm32f103xb diff --git a/boards/arm/olimex_stm32_h103/doc/img/olimex_stm32_h103_bottom.jpg b/boards/olimex/stm32_h103/doc/img/olimex_stm32_h103_bottom.jpg similarity index 100% rename from boards/arm/olimex_stm32_h103/doc/img/olimex_stm32_h103_bottom.jpg rename to boards/olimex/stm32_h103/doc/img/olimex_stm32_h103_bottom.jpg diff --git a/boards/arm/olimex_stm32_h103/doc/img/olimex_stm32_h103_top.jpg b/boards/olimex/stm32_h103/doc/img/olimex_stm32_h103_top.jpg similarity index 100% rename from boards/arm/olimex_stm32_h103/doc/img/olimex_stm32_h103_top.jpg rename to boards/olimex/stm32_h103/doc/img/olimex_stm32_h103_top.jpg diff --git a/boards/arm/olimex_stm32_h103/doc/index.rst b/boards/olimex/stm32_h103/doc/index.rst similarity index 100% rename from boards/arm/olimex_stm32_h103/doc/index.rst rename to boards/olimex/stm32_h103/doc/index.rst diff --git a/boards/arm/olimex_stm32_h103/olimex_stm32_h103.dts b/boards/olimex/stm32_h103/olimex_stm32_h103.dts similarity index 100% rename from boards/arm/olimex_stm32_h103/olimex_stm32_h103.dts rename to boards/olimex/stm32_h103/olimex_stm32_h103.dts diff --git a/boards/arm/olimex_stm32_h103/olimex_stm32_h103.yaml b/boards/olimex/stm32_h103/olimex_stm32_h103.yaml similarity index 100% rename from boards/arm/olimex_stm32_h103/olimex_stm32_h103.yaml rename to boards/olimex/stm32_h103/olimex_stm32_h103.yaml diff --git a/boards/arm/olimex_stm32_h103/olimex_stm32_h103_defconfig b/boards/olimex/stm32_h103/olimex_stm32_h103_defconfig similarity index 81% rename from boards/arm/olimex_stm32_h103/olimex_stm32_h103_defconfig rename to boards/olimex/stm32_h103/olimex_stm32_h103_defconfig index 7dc8d8f3b6f..9fd4400ac20 100644 --- a/boards/arm/olimex_stm32_h103/olimex_stm32_h103_defconfig +++ b/boards/olimex/stm32_h103/olimex_stm32_h103_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103XB=y - # enable uart driver CONFIG_SERIAL=y # enable console diff --git a/boards/arm/olimex_stm32_h103/support/openocd.cfg b/boards/olimex/stm32_h103/support/openocd.cfg similarity index 100% rename from boards/arm/olimex_stm32_h103/support/openocd.cfg rename to boards/olimex/stm32_h103/support/openocd.cfg diff --git a/boards/arm/olimex_stm32_h103/support/openocd_olimex_jtag.cfg b/boards/olimex/stm32_h103/support/openocd_olimex_jtag.cfg similarity index 100% rename from boards/arm/olimex_stm32_h103/support/openocd_olimex_jtag.cfg rename to boards/olimex/stm32_h103/support/openocd_olimex_jtag.cfg diff --git a/boards/arm/olimex_stm32_h103/support/openocd_stlink.cfg b/boards/olimex/stm32_h103/support/openocd_stlink.cfg similarity index 100% rename from boards/arm/olimex_stm32_h103/support/openocd_stlink.cfg rename to boards/olimex/stm32_h103/support/openocd_stlink.cfg diff --git a/boards/olimex/stm32_h405/Kconfig.olimex_stm32_h405 b/boards/olimex/stm32_h405/Kconfig.olimex_stm32_h405 new file mode 100644 index 00000000000..e6797add494 --- /dev/null +++ b/boards/olimex/stm32_h405/Kconfig.olimex_stm32_h405 @@ -0,0 +1,5 @@ +# Copyright (c) 2020, 2021 Antony Pavlov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_STM32_H405 + select SOC_STM32F405XX diff --git a/boards/arm/olimex_stm32_h405/board.cmake b/boards/olimex/stm32_h405/board.cmake similarity index 100% rename from boards/arm/olimex_stm32_h405/board.cmake rename to boards/olimex/stm32_h405/board.cmake diff --git a/boards/olimex/stm32_h405/board.yml b/boards/olimex/stm32_h405/board.yml new file mode 100644 index 00000000000..bd0e8f4beaa --- /dev/null +++ b/boards/olimex/stm32_h405/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_stm32_h405 + vendor: olimex + socs: + - name: stm32f405xx diff --git a/boards/arm/olimex_stm32_h405/doc/index.rst b/boards/olimex/stm32_h405/doc/index.rst similarity index 100% rename from boards/arm/olimex_stm32_h405/doc/index.rst rename to boards/olimex/stm32_h405/doc/index.rst diff --git a/boards/arm/olimex_stm32_h405/doc/olimex_stm32_h405_bottom.jpg b/boards/olimex/stm32_h405/doc/olimex_stm32_h405_bottom.jpg similarity index 100% rename from boards/arm/olimex_stm32_h405/doc/olimex_stm32_h405_bottom.jpg rename to boards/olimex/stm32_h405/doc/olimex_stm32_h405_bottom.jpg diff --git a/boards/arm/olimex_stm32_h405/doc/olimex_stm32_h405_top.jpg b/boards/olimex/stm32_h405/doc/olimex_stm32_h405_top.jpg similarity index 100% rename from boards/arm/olimex_stm32_h405/doc/olimex_stm32_h405_top.jpg rename to boards/olimex/stm32_h405/doc/olimex_stm32_h405_top.jpg diff --git a/boards/arm/olimex_stm32_h405/olimex_stm32_h405.dts b/boards/olimex/stm32_h405/olimex_stm32_h405.dts similarity index 100% rename from boards/arm/olimex_stm32_h405/olimex_stm32_h405.dts rename to boards/olimex/stm32_h405/olimex_stm32_h405.dts diff --git a/boards/arm/olimex_stm32_h405/olimex_stm32_h405.yaml b/boards/olimex/stm32_h405/olimex_stm32_h405.yaml similarity index 100% rename from boards/arm/olimex_stm32_h405/olimex_stm32_h405.yaml rename to boards/olimex/stm32_h405/olimex_stm32_h405.yaml diff --git a/boards/arm/olimex_stm32_h405/olimex_stm32_h405_defconfig b/boards/olimex/stm32_h405/olimex_stm32_h405_defconfig similarity index 84% rename from boards/arm/olimex_stm32_h405/olimex_stm32_h405_defconfig rename to boards/olimex/stm32_h405/olimex_stm32_h405_defconfig index ca015a21976..c729b83e3d0 100644 --- a/boards/arm/olimex_stm32_h405/olimex_stm32_h405_defconfig +++ b/boards/olimex/stm32_h405/olimex_stm32_h405_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F405XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimex_stm32_h405/support/openocd.cfg b/boards/olimex/stm32_h405/support/openocd.cfg similarity index 100% rename from boards/arm/olimex_stm32_h405/support/openocd.cfg rename to boards/olimex/stm32_h405/support/openocd.cfg diff --git a/boards/olimex/stm32_h407/Kconfig.olimex_stm32_h407 b/boards/olimex/stm32_h407/Kconfig.olimex_stm32_h407 new file mode 100644 index 00000000000..12c96366272 --- /dev/null +++ b/boards/olimex/stm32_h407/Kconfig.olimex_stm32_h407 @@ -0,0 +1,5 @@ +# Copyright (c) 2018, Reto Schneider +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_STM32_H407 + select SOC_STM32F407XG diff --git a/boards/arm/olimex_stm32_e407/board.cmake b/boards/olimex/stm32_h407/board.cmake similarity index 100% rename from boards/arm/olimex_stm32_e407/board.cmake rename to boards/olimex/stm32_h407/board.cmake diff --git a/boards/olimex/stm32_h407/board.yml b/boards/olimex/stm32_h407/board.yml new file mode 100644 index 00000000000..5d2f0d7a783 --- /dev/null +++ b/boards/olimex/stm32_h407/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_stm32_h407 + vendor: olimex + socs: + - name: stm32f407xx diff --git a/boards/arm/olimex_stm32_h407/doc/img/olimex-stm32-h407-front.jpg b/boards/olimex/stm32_h407/doc/img/olimex-stm32-h407-front.jpg similarity index 100% rename from boards/arm/olimex_stm32_h407/doc/img/olimex-stm32-h407-front.jpg rename to boards/olimex/stm32_h407/doc/img/olimex-stm32-h407-front.jpg diff --git a/boards/arm/olimex_stm32_h407/doc/img/olimex_stm32_h407.jpg b/boards/olimex/stm32_h407/doc/img/olimex_stm32_h407.jpg similarity index 100% rename from boards/arm/olimex_stm32_h407/doc/img/olimex_stm32_h407.jpg rename to boards/olimex/stm32_h407/doc/img/olimex_stm32_h407.jpg diff --git a/boards/arm/olimex_stm32_h407/doc/index.rst b/boards/olimex/stm32_h407/doc/index.rst similarity index 100% rename from boards/arm/olimex_stm32_h407/doc/index.rst rename to boards/olimex/stm32_h407/doc/index.rst diff --git a/boards/arm/olimex_stm32_h407/olimex_stm32_h407.dts b/boards/olimex/stm32_h407/olimex_stm32_h407.dts similarity index 100% rename from boards/arm/olimex_stm32_h407/olimex_stm32_h407.dts rename to boards/olimex/stm32_h407/olimex_stm32_h407.dts diff --git a/boards/arm/olimex_stm32_h407/olimex_stm32_h407.yaml b/boards/olimex/stm32_h407/olimex_stm32_h407.yaml similarity index 100% rename from boards/arm/olimex_stm32_h407/olimex_stm32_h407.yaml rename to boards/olimex/stm32_h407/olimex_stm32_h407.yaml diff --git a/boards/arm/olimex_stm32_h407/olimex_stm32_h407_defconfig b/boards/olimex/stm32_h407/olimex_stm32_h407_defconfig similarity index 84% rename from boards/arm/olimex_stm32_h407/olimex_stm32_h407_defconfig rename to boards/olimex/stm32_h407/olimex_stm32_h407_defconfig index ad325266c72..c729b83e3d0 100644 --- a/boards/arm/olimex_stm32_h407/olimex_stm32_h407_defconfig +++ b/boards/olimex/stm32_h407/olimex_stm32_h407_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimex_stm32_h407/support/openocd.cfg b/boards/olimex/stm32_h407/support/openocd.cfg similarity index 100% rename from boards/arm/olimex_stm32_h407/support/openocd.cfg rename to boards/olimex/stm32_h407/support/openocd.cfg diff --git a/boards/olimex/stm32_p405/Kconfig.olimex_stm32_p405 b/boards/olimex/stm32_p405/Kconfig.olimex_stm32_p405 new file mode 100644 index 00000000000..7c61fe39272 --- /dev/null +++ b/boards/olimex/stm32_p405/Kconfig.olimex_stm32_p405 @@ -0,0 +1,5 @@ +# Copyright (c) 2017, Erwin Rol +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_STM32_P405 + select SOC_STM32F405XX diff --git a/boards/arm/olimex_stm32_p405/board.cmake b/boards/olimex/stm32_p405/board.cmake similarity index 100% rename from boards/arm/olimex_stm32_p405/board.cmake rename to boards/olimex/stm32_p405/board.cmake diff --git a/boards/olimex/stm32_p405/board.yml b/boards/olimex/stm32_p405/board.yml new file mode 100644 index 00000000000..12201ed22c9 --- /dev/null +++ b/boards/olimex/stm32_p405/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_stm32_p405 + vendor: olimex + socs: + - name: stm32f405xx diff --git a/boards/arm/olimex_stm32_p405/doc/img/olimex-stm32-p405-front.jpg b/boards/olimex/stm32_p405/doc/img/olimex-stm32-p405-front.jpg similarity index 100% rename from boards/arm/olimex_stm32_p405/doc/img/olimex-stm32-p405-front.jpg rename to boards/olimex/stm32_p405/doc/img/olimex-stm32-p405-front.jpg diff --git a/boards/arm/olimex_stm32_p405/doc/img/olimex_stm32_p405.jpg b/boards/olimex/stm32_p405/doc/img/olimex_stm32_p405.jpg similarity index 100% rename from boards/arm/olimex_stm32_p405/doc/img/olimex_stm32_p405.jpg rename to boards/olimex/stm32_p405/doc/img/olimex_stm32_p405.jpg diff --git a/boards/arm/olimex_stm32_p405/doc/index.rst b/boards/olimex/stm32_p405/doc/index.rst similarity index 100% rename from boards/arm/olimex_stm32_p405/doc/index.rst rename to boards/olimex/stm32_p405/doc/index.rst diff --git a/boards/arm/olimex_stm32_p405/olimex_stm32_p405.dts b/boards/olimex/stm32_p405/olimex_stm32_p405.dts similarity index 100% rename from boards/arm/olimex_stm32_p405/olimex_stm32_p405.dts rename to boards/olimex/stm32_p405/olimex_stm32_p405.dts diff --git a/boards/arm/olimex_stm32_p405/olimex_stm32_p405.yaml b/boards/olimex/stm32_p405/olimex_stm32_p405.yaml similarity index 100% rename from boards/arm/olimex_stm32_p405/olimex_stm32_p405.yaml rename to boards/olimex/stm32_p405/olimex_stm32_p405.yaml diff --git a/boards/arm/olimex_stm32_p405/olimex_stm32_p405_defconfig b/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig similarity index 85% rename from boards/arm/olimex_stm32_p405/olimex_stm32_p405_defconfig rename to boards/olimex/stm32_p405/olimex_stm32_p405_defconfig index 18d48f08e1a..758675b14ba 100644 --- a/boards/arm/olimex_stm32_p405/olimex_stm32_p405_defconfig +++ b/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F405XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimex_stm32_p405/support/openocd.cfg b/boards/olimex/stm32_p405/support/openocd.cfg similarity index 100% rename from boards/arm/olimex_stm32_p405/support/openocd.cfg rename to boards/olimex/stm32_p405/support/openocd.cfg diff --git a/boards/openisa/index.rst b/boards/openisa/index.rst new file mode 100644 index 00000000000..d1a8c33af06 --- /dev/null +++ b/boards/openisa/index.rst @@ -0,0 +1,10 @@ +.. _boards-openisa: + +OpenISA +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/openisa/rv32m1_vega/Kconfig.defconfig b/boards/openisa/rv32m1_vega/Kconfig.defconfig new file mode 100644 index 00000000000..08279d8ed04 --- /dev/null +++ b/boards/openisa/rv32m1_vega/Kconfig.defconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2018 Foundries.io Ltd + +if BOARD_RV32M1_VEGA + +if BT + +config BT_CTLR + default y + +#TODO: Resolve the complete non-BLE support for crypto CAU3 firmware/driver +#config HAS_RV32M1_CAU3 +# bool +# default y if BT_CTLR_CRYPTO && !BT_CTLR_LE_ENC_SUPPORT + +config HAS_RV32M1_CAU3_BLE + bool + default y if BT_CTLR_CRYPTO && \ + (BT_CTLR_LE_ENC_SUPPORT || BT_CTLR_PRIVACY_SUPPORT) + +config RV32M1_INTMUX_CHANNEL_2 + default n + +config RV32M1_INTMUX_CHANNEL_3 + default n + +endif # BT + +endif # BOARD_RV32M1_VEGA diff --git a/boards/openisa/rv32m1_vega/Kconfig.rv32m1_vega b/boards/openisa/rv32m1_vega/Kconfig.rv32m1_vega new file mode 100644 index 00000000000..40134c6f442 --- /dev/null +++ b/boards/openisa/rv32m1_vega/Kconfig.rv32m1_vega @@ -0,0 +1,6 @@ +# Copyright 2018 Foundries.io Ltd +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RV32M1_VEGA + select SOC_OPENISA_RV32M1_RI5CY if BOARD_RV32M1_VEGA_OPENISA_RV32M1_RI5CY + select SOC_OPENISA_RV32M1_ZERO_RISCY if BOARD_RV32M1_VEGA_OPENISA_RV32M1_ZERO_RISCY diff --git a/boards/openisa/rv32m1_vega/board.cmake b/boards/openisa/rv32m1_vega/board.cmake new file mode 100644 index 00000000000..8bc69de47a5 --- /dev/null +++ b/boards/openisa/rv32m1_vega/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2018 Foundries.io Ltd + +set(OPENOCD_USE_LOAD_IMAGE NO) + +if(CONFIG_SOC_OPENISA_RV32M1_RI5CY) + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_ri5cy.cfg") +elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY) + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_zero_riscy.cfg") +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/openisa/rv32m1_vega/board.yml b/boards/openisa/rv32m1_vega/board.yml new file mode 100644 index 00000000000..5813a21b54f --- /dev/null +++ b/boards/openisa/rv32m1_vega/board.yml @@ -0,0 +1,5 @@ +board: + name: rv32m1_vega + vendor: openisa + socs: + - name: openisa_rv32m1 diff --git a/boards/openisa/rv32m1_vega/doc/index.rst b/boards/openisa/rv32m1_vega/doc/index.rst new file mode 100644 index 00000000000..339b8dc5e0c --- /dev/null +++ b/boards/openisa/rv32m1_vega/doc/index.rst @@ -0,0 +1,841 @@ +.. highlight:: sh + +.. _rv32m1_vega: + +OpenISA VEGAboard +################# + +Overview +******** + +The VEGAboard contains the RV32M1 SoC, featuring two RISC-V CPUs, +on-die XIP flash, and a full complement of peripherals, including a +2.4 GHz multi-protocol radio. It also has built-in sensors and +Arduino-style expansion connectors. + +.. figure:: rv32m1_vega.jpg + :align: center + :alt: RV32M1-VEGA + + OpenISA VEGAboard (image copyright: www.open-isa.org) + +The two RISC-V CPUs are named RI5CY and ZERO-RISCY, and are +respectively based on the `PULP platform`_ designs by the same names: +`RI5CY`_ and `ZERO-RISCY`_. RI5CY is the "main" core; it has more +flash and RAM as well as a more powerful CPU design. ZERO-RISCY is a +"secondary" core. The main ZERO-RISCY use-case is as a wireless +coprocessor for applications running on RI5CY. The two cores can +communicate via shared memory and messaging peripherals. + +Currently, Zephyr supports RI5CY with the ``rv32m1_vega/openisa_rv32m1/ri5cy`` board +configuration name, and ZERO_RISCY with the ``rv32m1_vega/openisa_rv32m1/zero_riscy`` board +configuration name. + +Hardware +******** + +The VEGAboard includes the following features. + +RV32M1 multi-core SoC: + +- 1 MiB flash and 192 KiB SRAM (RI5CY core) +- 256 KiB flash and 128 KiB SRAM (ZERO-RISCY core) +- Low power modes +- DMA support +- Watchdog, CRC, cryptographic acceleration, ADC, DAC, comparator, + timers, PWM, RTC, I2C, UART, SPI, external memory, I2S, smart + card, USB full-speed, uSDHC, and 2.4 GHz multiprotocol radio + peripherals + +On-board sensors and peripherals: + +- 32 Mbit SPI flash +- 6-axis accelerometer, magnetometer, and temperature sensor (FXOS8700) +- Ambient light sensor +- RGB LED +- microSD card slot +- Antenna interface + +Additional features: + +- Form-factor compatible with Arduino Uno Rev 3 expansion connector + layout (not all Arduino shields may be pin-compatible) +- UART via USB using separate OpenSDA chip +- RISC-V flash and debug using external JTAG dongle (not included) via + 2x5 5 mil pitch connector (commonly called the "ARM 10-pin JTAG" + connector) + +Supported Features +================== + +Zephyr's RI5CY configuration, ``rv32m1_vega/openisa_rv32m1/ri5cy``, currently supports +the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| EVENT | on-chip | event unit interrupt controller | ++-----------+------------+-------------------------------------+ +| INTMUX | on-chip | level 2 interrupt controller | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | lptmr-based system timer | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| TPM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger; | ++-----------+------------+-------------------------------------+ + +Zephyr's ZERO-RISCY configuration, ``rv32m1_vega/openisa_rv32m1/zero_riscy``, currently +supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| EVENT | on-chip | event unit interrupt controller | ++-----------+------------+-------------------------------------+ +| INTMUX | on-chip | level 2 interrupt controller | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | lptmr-based system timer | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| TPM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger; | ++-----------+------------+-------------------------------------+ + +BLE Software Link Layer experimental support +================================================== +This is an experimental feature supported on the Zephyr's RI5CY +configuration, ``rv32m1_vega/openisa_rv32m1/ri5cy``. It uses the Software Link Layer +framework by Nordic Semi to enable the on-SoC radio and transceiver for +implementing a software defined BLE controller. By using both the controller +and the host stack available in Zephyr, the following BLE samples can be used +with this board: + +- beacon +- central +- central_hr +- eddystone +- hci_uart +- ibeacon +- peripheral_csc (Cycling Speed Cadence) +- peripheral_dis (Device Information Service) +- peripheral_esp (Environmental Sensing Service) +- peripheral_hr (Heart Rate) +- peripheral_ht (Health Thermometer) +- peripheral +- scan_adv + +.. note:: + + BLE Software Link Layer limitations: + + - no 512/256 Kbps PHY + - no TX power adjustment + + +Connections and IOs +=================== + +RV32M1 SoC pins are brought out to Arduino-style expansion connectors. +These are 2 pins wide each, adding an additional row of expansion pins +per header compared to the standard Arduino layout. + +They are described in the tables in the following subsections. Since +pins are usually grouped by logical function in rows on these headers, +the odd- and even-numbered pins are listed in separate tables. The +"Port/bit" columns refer to the SoC PORT and GPIO peripheral +naming scheme, e.g. "E/13" means PORTE/GPIOE pin 13. + +See the schematic and chip reference manual for details. +(Documentation is available from the `OpenISA GitHub releases`_ page.) + +.. note:: + + Pins with peripheral functionality may also be muxed as GPIOs. + +**Top right expansion header (J1)** + +Odd/bottom pins: + +=== ======== ================= +Pin Port/bit Function +=== ======== ================= +1 E/13 I2S_TX_BCLK +3 E/14 I2S_TX_FS +5 E/15 I2S_TXD +7 E/19 I2S_MCLK +9 E/16 I2S_RX_BCLK +11 E/21 SOF_OUT +13 E/17 I2S_RX_FS +15 E/18 I2S_RXD +=== ======== ================= + +Even/top pins: + +=== ======== ================= +Pin Port/bit Function +=== ======== ================= +2 A/25 UART1_RX +4 A/26 UART1_TX +6 A/27 GPIO +8 B/13 PWM +10 B/14 GPIO +12 A/30 PWM +14 A/31 PWM/CMP +16 B/1 GPIO +=== ======== ================= + +**Top left expansion header (J2)** + +Odd/bottom pins: + +=== ======== ================= +Pin Port/bit Function +=== ======== ================= +1 D/5 FLEXIO_D25 +3 D/4 FLEXIO_D24 +5 D/3 FLEXIO_D23 +7 D/2 FLEXIO_D22 +9 D/1 FLEXIO_D21 +11 D/0 FLEXIO_D20 +13 C/30 FLEXIO_D19 +15 C/29 FLEXIO_D18 +17 C/28 FLEXIO_D17 +19 B/29 FLEXIO_D16 +=== ======== ================= + +Even/top pins: + +=== ======== ================= +Pin Port/bit Function +=== ======== ================= +2 B/2 GPIO +4 B/3 PWM +6 B/6 SPI0_PCS2 +8 B/5 SPI0_SOUT +10 B/7 SPI0_SIN +12 B/4 SPI0_SCK +14 - GND +16 - AREF +18 C/9 I2C0_SDA +20 C/10 I2C0_SCL +=== ======== ================= + +**Bottom left expansion header (J3)** + +Note that the headers at the bottom of the board have odd-numbered +pins on the top, unlike the headers at the top of the board. + +Odd/top pins: + +=== ======== ==================== +Pin Port/bit Function +=== ======== ==================== +1 A/21 ARDUINO_EMVSIM_PD +3 A/20 ARDUINO_EMVSIM_IO +5 A/19 ARDUINO_EMVSIM_VCCEN +7 A/18 ARDUINO_EMVSIM_RST +9 A/17 ARDUINO_EMVSIM_CLK +11 B/17 FLEXIO_D7 +13 B/16 FLEXIO_D6 +15 B/15 FLEXIO_D5 +=== ======== ==================== + +Even/bottom pins: note that these are mostly power-related. + +=== ======== ================= +Pin Port/bit Function +=== ======== ================= +2 - SDA_GPIO0 +4 - BRD_IO_PER +6 - RST_SDA +8 - BRD_IO_PER +10 - P5V_INPUT +12 - GND +14 - GND +16 - P5-9V VIN +=== ======== ================= + +**Bottom right expansion header (J4)** + +Note that the headers at the bottom of the board have odd-numbered +pins on the top, unlike the headers at the top of the board. + +Odd/top pins: + +=== ======== ======================================== +Pin Port/bit Function +=== ======== ======================================== +1 - TAMPER2 +3 - TAMPER1/RTC_CLKOUT +5 - TAMPER0/RTC_WAKEUP_b +7 E/2 ADC0_SE19 +9 E/5 LPCMP1_IN2/LPCMP1_OUT +11 - DAC0_OUT/ADC0_SE16/LPCMP0_IN3/LPCMP1_IN3 +=== ======== ======================================== + +Even/bottom pins: + +=== ======== =========================================== +Pin Port/bit Function +=== ======== =========================================== +2 C/11 ADC0_SE6 +4 C/12 ADC0_SE7 +6 B/9 ADC0_SE3 +8 E/4 ADC0_SE21 +10 E/10 ADC0_SE19 (and E/10, I2C3_SDA via 0 Ohm DNP) +12 E/11 ADC0_SE20 (and E/11, I2C3_SCL via 0 Ohm DNP) +=== ======== =========================================== + +Additional Pins +--------------- + +For an up-to-date description of additional pins (such as buttons, +LEDs, etc.) supported by Zephyr, see the board DTS files in the Zephyr +source code, i.e. +:zephyr_file:`boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts` for RI5CY and +:zephyr_file:`boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts` for +ZERO-RISCY. + +See the schematic in the documentation available from the `OpenISA +GitHub releases`_ page for additional details. + +System Clocks +============= + +The RI5CY and ZERO-RISCY cores are configured to use the slow internal +reference clock (SIRC) as the clock source for an LPTMR peripheral to manage +the system timer, and the fast internal reference clock (FIRC) to generate a +48MHz core clock. + +Serial Port +=========== + +The USB connector at the top left of the board (near the RESET button) is +connected to an OpenSDA chip which provides a serial USB device. This is +connected to the LPUART0 peripheral which the RI5CY and ZERO-RISCY cores use by +default for console and logging. + +.. warning:: + + The OpenSDA chip cannot be used to flash or debug the RISC-V cores. + + See the next section for flash and debug instructions for the + RISC-V cores using an external JTAG dongle. + +Programming and Debugging +************************* + +.. _rv32m1-programming-hw: + +.. important:: + + To use this board, you will need: + + - a `SEGGER J-Link`_ debug probe to debug the RISC-V cores + - a J-Link `9-Pin Cortex-M Adapter`_ board and ribbon cable + - the SEGGER `J-Link Software and Documentation Pack`_ software + installed + + A JTAG dongle is not included with the board itself. + +Follow these steps to: + +#. Get a toolchain and OpenOCD +#. Set up the board for booting RI5CY +#. Compile a Zephyr application for the RI5CY core +#. Flash the application to your board +#. Debug the board using GDB + +.. _rv32m1-toolchain-openocd: + +Get the Toolchain and OpenOCD +============================= + +Before programming and debugging, you first need to get a GNU +toolchain and an OpenOCD build. There are vendor-specific versions of +each for the RV32M1 SoC\ [#toolchain_openocd]_. + +Option 1 (Recommended): Prebuilt Toolchain and OpenOCD +------------------------------------------------------ + +The following prebuilt toolchains and OpenOCD archives are available +on the `OpenISA GitHub releases`_ page: + +- :file:`Toolchain_Linux.tar.gz` +- :file:`Toolchain_Mac.tar.gz` +- :file:`Toolchain_Windows.zip` + +Download and extract the archive for your system, then extract the +toolchain and OpenOCD archives inside. + +Linux:: + + tar xvzf Toolchain_Linux.tar.gz + tar xvzf openocd.tar.gz + tar xvzf riscv32-unknown-elf-gcc.tar.gz + mv openocd ~/rv32m1-openocd + mv riscv32-unknown-elf-gcc ~ + +macOS (unfortunately, the OpenISA 1.0.0 release's Mac +:file:`riscv32-unknown-elf-gcc.tar.gz` file doesn't expand into a +:file:`riscv32-unknown-elf-gcc` directory, so it has to be created):: + + tar xvzf Toolchain_Mac.tar.gz + tar xvzf openocd.tar.gz + mkdir riscv32-unknown-elf-gcc + mv riscv32-unknown-elf-gcc.tar.gz riscv32-unknown-elf-gcc + cd riscv32-unknown-elf-gcc/ + tar xvzf riscv32-unknown-elf-gcc.tar.gz + cd .. + mv openocd ~/rv32m1-openocd + mv riscv32-unknown-elf-gcc ~ + +Windows: + +#. Extract :file:`Toolchain_Windows.zip` in the file manager +#. Extract the :file:`openocd.zip` and :file:`riscv32-unknown-elf-gcc.zip` files + in the resulting :file:`Toolchain_Windows` folder +#. Move the extracted :file:`openocd` folder to :file:`C:\\rv32m1-openocd` +#. Move the extracted :file:`riscv32-unknown-elf-gcc` folder to + :file:`C:\\riscv32-unknown-elf-gcc` + +For simplicity, this guide assumes: + +- You put the extracted toolchain at :file:`~/riscv32-unknown-elf-gcc` + on macOS or Linux, and :file:`C:\\riscv32-unknown-elf-gcc` on + Windows. +- You put the extracted OpenOCD binary at :file:`~/rv32m1-openocd` on + macOS or Linux, and the OpenOCD folder into :file:`C:\\rv32m1-openocd` + on Windows. + +You can put them elsewhere, but be aware: + +- If you put the toolchain somewhere else, you will need to change + the ``CROSS_COMPILE`` value described below accordingly. +- If you put OpenOCD somewhere else, you will need to change the + OpenOCD path in the flashing and debugging instructions below. +- Don't use installation directories with spaces anywhere in the path; + this won't work with Zephyr's build system. + +Option 2: Building Toolchain and OpenOCD From Source +---------------------------------------------------- + +See :ref:`rv32m1_vega_toolchain_build`. + +.. _rv32m1-vega-jtag: + +JTAG Setup +========== + +This section describes how to connect to your board via the J-Link +debugger and adapter board. See the :ref:`above information +` for details on required hardware. + +#. Connect the J-Link debugger through the adapter board to the + VEGAboard as shown in the figure. + + .. figure:: rv32m1_vega_jtag.jpg + :align: center + :alt: RV32M1-VEGA + + VEGAboard connected properly to J-Link debugger. + VEGAboard connector J55 should be used. Pin 1 is on the bottom left. + +#. Power the VEGAboard via USB. The OpenSDA connector at the top left + is recommended for UART access. + +#. Make sure your J-Link is connected to your computer via USB. + +One-Time Board Setup For Booting RI5CY or ZERO-RISCY +==================================================== + +Next, you'll need to make sure your board boots the RI5CY or ZERO-RISCY core. +**You only need to do this once.** + +The RV32M1 SoC on the VEGAboard has multiple cores, any of which can +be selected as the boot core. Before flashing and debugging, you'll +first make sure you're booting the right core. + +**Linux and macOS**: + +.. note:: + + Linux users: to run these commands as a normal user, you will need + to install the `60-openocd.rules`_ udev rules file (usually by + placing it in :file:`/etc/udev/rules.d`, then unplugging and + plugging the J-Link in again via USB). + +.. note:: + + These Zephyr-specific instructions differ slightly from the + equivalent SDK ones. The Zephyr OpenOCD configuration file does not + run ``init``, so you have to do it yourself as explained below. + +1. In one terminal, use OpenOCD to connect to the board:: + + ~/rv32m1-openocd -f boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg + + The output should look like this: + + .. code-block:: console + + $ ~/rv32m1-openocd -f boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg + Open On-Chip Debugger 0.10.0+dev-00431-ge1ec3c7d (2018-10-31-07:29) + [...] + Info : Listening on port 3333 for gdb connections + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + +2. In another terminal, connect to OpenOCD's telnet server and execute + the ``init`` and ``ri5cy_boot`` commands **with the reset button on + the board (at top left) pressed down**:: + + $ telnet localhost 4444 + Trying 127.0.0.1... + Connected to localhost. + Escape character is '^]'. + Open On-Chip Debugger + > init + > ri5cy_boot + + To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with + ``zero_boot``. + + The reset button is at top left, as shown in the following figure. + + .. figure:: ri5cy_boot.jpg + :align: center + :alt: Reset button is pressed + + Now quit the telnet session in this terminal and exit OpenOCD in the + other terminal. + +3. Unplug your J-Link and VEGAboard, and plug them back in. + +**Windows**: + +In one cmd.exe prompt in the Zephyr directory:: + + C:\rv32m1-openocd\bin\openocd.exe rv32m1-openocd -f boards\openisa\rv32m1_vega\support\openocd_rv32m1_vega_ri5cy.cfg + +In a telnet program of your choice: + +#. Connect to localhost port 4444 using telnet. +#. Run ``init`` and ``ri5cy_boot`` as shown above, with RESET held down. +#. Quit the OpenOCD and telnet sessions. +#. Unplug your J-Link and VEGAboard, and plug them back in. + + To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with + ``zero_boot``. + +Compiling a Program +=================== + +.. important:: + + These instructions assume you've set up a development system, + cloned the Zephyr repository, and installed Python dependencies as + described in the :ref:`getting_started`. + + You should also have already downloaded and installed the toolchain + and OpenOCD as described above in :ref:`rv32m1-toolchain-openocd`. + +The first step is to set up environment variables to point at your +toolchain and OpenOCD:: + + # Linux or macOS + export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + export CROSS_COMPILE=~/riscv32-unknown-elf-gcc/bin/riscv32-unknown-elf- + + # Windows + set ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + set CROSS_COMPILE=C:\riscv32-unknown-elf-gcc\bin\riscv32-unknown-elf- + +.. note:: + + The above only sets these variables for your current shell session. + You need to make sure this happens every time you use this board. + +Now let's compile the :ref:`hello_world` application. (You can try +others as well; see :ref:`samples-and-demos` for more.) + +.. We can't use zephyr-app-commands to provide build instructions + due to the below mentioned linker issue. + +Due to a toolchain `linker issue`_, you need to add an option setting +``CMAKE_REQUIRED_FLAGS`` when running CMake to generate a build system +(see :ref:`application` for information about Zephyr's build system). + +Linux and macOS (run this in a terminal from the Zephyr directory):: + + # Set up environment and create build directory: + source zephyr-env.sh + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :tool: cmake + :cd-into: + :board: rv32m1_vega/openisa_rv32m1/ri5cy + :gen-args: -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=/dev/null + :goals: build + +Windows (run this in a ``cmd`` prompt, from the Zephyr directory):: + + # Set up environment and create build directory + zephyr-env.cmd + cd samples\hello_world + mkdir build & cd build + + # Use CMake to generate a Ninja-based build system: + type NUL > empty.ld + cmake -GNinja -DBOARD=rv32m1_vega/openisa_rv32m1/ri5cy -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=%cd%\empty.ld .. + + # Build the sample + ninja + +Flashing +======== + +.. note:: + + Make sure you've done the :ref:`JTAG setup `, and + that the VEGAboard's top left USB connector is connected to your + computer too (for UART access). + +.. note:: + + Linux users: to run these commands as a normal user, you will need + to install the `60-openocd.rules`_ udev rules file (usually by + placing it in :file:`/etc/udev/rules.d`, then unplugging and + plugging the J-Link in again via USB). + +Make sure you've followed the above instructions to set up your board +and build a program first. + +Since you need to use a special OpenOCD, the easiest way to flash is +by using :ref:`west flash ` instead of ``ninja +flash`` like you might see with other Zephyr documentation. + +Run these commands from the build directory where you ran ``ninja`` in +the above section. + +Linux and macOS:: + + # Don't use "~/rv32m1-openocd". It won't work. + west flash --openocd=$HOME/rv32m1-openocd + +Windows:: + + west flash --openocd=C:\rv32m1-openocd\bin\openocd.exe + +If you have problems: + +- Make sure you don't have another ``openocd`` process running in the + background. +- Unplug the boards and plug them back in. +- On Linux, make sure udev rules are installed, as described above. + +As an alternative, for manual steps to run OpenOCD and GDB to flash, +see the `SDK README`_. + +Debugging +========= + +.. note:: + + Make sure you've done the :ref:`JTAG setup `, and + that the VEGAboard's top left USB connector is connected to your + computer too (for UART access). + +.. note:: + + Linux users: to run these commands as a normal user, you will need + to install the `60-openocd.rules`_ udev rules file (usually by + placing it in :file:`/etc/udev/rules.d`, then unplugging and + plugging the J-Link in again via USB). + +Make sure you've followed the above instructions to set up your board +and build a program first. + +To debug with gdb:: + + # Linux, macOS + west debug --openocd=$HOME/rv32m1-openocd + + # Windows + west debug --openocd=C:\rv32m1-openocd\bin\openocd.exe + +Then, from the ``(gdb)`` prompt, follow these steps to halt the core, +load the binary (:file:`zephyr.elf`), and re-sync with the OpenOCD +server:: + + (gdb) monitor init + (gdb) monitor reset halt + (gdb) load + (gdb) monitor gdb_sync + (gdb) stepi + +You can then set breakpoints and debug using normal GDB commands. + +.. note:: + + GDB can get out of sync with the target if you execute commands + that reset it. To reset RI5CY and get GDB back in sync with it + without reloading the binary:: + + (gdb) monitor reset halt + (gdb) monitor gdb_sync + (gdb) stepi + +If you have problems: + +- Make sure you don't have another ``openocd`` process running in the + background. +- Unplug the boards and plug them back in. +- On Linux, make sure udev rules are installed, as described above. + +References +********** + +- OpenISA developer portal: http://open-isa.org +- `OpenISA GitHub releases`_: includes toolchain and OpenOCD + prebuilts, as well as documentation, such as the SoC datasheet and + reference manual, board schematic and user guides, etc. +- Base toolchain: `pulp-riscv-gnu-toolchain`_; extra toolchain patches: + `rv32m1_gnu_toolchain_patch`_ (only needed if building from source). +- OpenOCD repository: `rv32m1-openocd`_ (only needed if building from + source). +- Vendor SDK: `rv32m1_sdk_riscv`_. Contains HALs, non-Zephyr sample + applications, and information on using the board with Eclipse which + may be interesting when combined with the Eclipse Debugging + information in the :ref:`application`. + +.. _rv32m1_vega_toolchain_build: + +Appendix: Building Toolchain and OpenOCD from Source +**************************************************** + +.. note:: + + Toolchain and OpenOCD build instructions are provided for Linux and + macOS only. + + Instructions for building OpenOCD have only been verified on Linux. + +.. warning:: + + Don't use installation directories with spaces anywhere in + the path; this won't work with Zephyr's build system. + +Ubuntu 18.04 users need to install these additional dependencies:: + + sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \ + libmpfr-dev libgmp-dev gawk build-essential bison \ + flex texinfo gperf libtool patchutils bc zlib1g-dev \ + libusb-1.0-0-dev libudev1 libudev-dev g++ + +Users of other Linux distributions need to install the above packages +with their system package manager. + +macOS users need to install dependencies with Homebrew:: + + brew install gawk gnu-sed gmp mpfr libmpc isl zlib + +The build toolchain is based on the `pulp-riscv-gnu-toolchain`_, with +some additional patches hosted in a separate repository, +`rv32m1_gnu_toolchain_patch`_. To build the toolchain, follow the +instructions in the ``rv32m1_gnu_toolchain_patch`` repository's +`readme.md`_ file to apply the patches, then run:: + + ./configure --prefix= --with-arch=rv32imc --with-cmodel=medlow --enable-multilib + make + +If you set ```` to +:file:`~/riscv32-unknown-elf-gcc`, you can use the above instructions +for setting ``CROSS_COMPILE`` when building Zephyr +applications. If you set it to something else, you will need to update +your ``CROSS_COMPILE`` setting accordingly. + +.. note:: + + Strangely, there is no separate ``make install`` step for the + toolchain. That is, the ``make`` invocation both builds and + installs the toolchain. This means ``make`` has to be run as root + if you want to set ``--prefix`` to a system directory such as + :file:`/usr/local` or :file:`/opt` on Linux. + +To build OpenOCD, clone the `rv32m1-openocd`_ repository, then run +these from the repository top level:: + + ./bootstrap + ./configure --prefix= + make + make install + +If ```` is :file:`~/rv32m1-openocd`, you +should set your OpenOCD path to :file:`~/rv32m1-openocd/bin/openocd` +in the above flash and debug instructions. + +.. _RI5CY: + https://github.com/pulp-platform/riscv +.. _ZERO-RISCY: + https://github.com/pulp-platform/zero-riscy +.. _PULP platform: + http://iis-projects.ee.ethz.ch/index.php/PULP + +.. _pulp-riscv-gnu-toolchain: + https://github.com/pulp-platform/pulp-riscv-gnu-toolchain +.. _rv32m1_gnu_toolchain_patch: + https://github.com/open-isa-rv32m1/rv32m1_gnu_toolchain_patch +.. _rv32m1-openocd: + https://github.com/open-isa-rv32m1/rv32m1-openocd +.. _readme.md: + https://github.com/open-isa-rv32m1/rv32m1_gnu_toolchain_patch/blob/master/readme.md +.. _OpenISA GitHub releases: + https://github.com/open-isa-org/open-isa.org/releases +.. _rv32m1_sdk_riscv: + https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv +.. _linker issue: + https://github.com/pulp-platform/pulpino/issues/240 +.. _60-openocd.rules: + https://github.com/open-isa-rv32m1/rv32m1-openocd/blob/master/contrib/60-openocd.rules +.. _SEGGER J-Link: + https://www.segger.com/products/debug-probes/j-link/ +.. _9-Pin Cortex-M Adapter: + https://www.segger.com/products/debug-probes/j-link/accessories/adapters/9-pin-cortex-m-adapter/ +.. _J-Link Software and Documentation Pack: + https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack +.. _SDK README: + https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv/blob/master/readme.md + +.. rubric:: Footnotes + +.. [#toolchain_openocd] + + For Linux users, the RISC-V toolchain in the :ref:`Zephyr SDK + ` may work, but it hasn't been thoroughly tested with this + SoC, and will not allow use of any available RISC-V ISA extensions. + + Support for the RV32M1 SoC is not currently available in the OpenOCD + upstream repository or the OpenOCD build in the Zephyr SDK. diff --git a/boards/riscv/rv32m1_vega/doc/ri5cy_boot.jpg b/boards/openisa/rv32m1_vega/doc/ri5cy_boot.jpg similarity index 100% rename from boards/riscv/rv32m1_vega/doc/ri5cy_boot.jpg rename to boards/openisa/rv32m1_vega/doc/ri5cy_boot.jpg diff --git a/boards/riscv/rv32m1_vega/doc/rv32m1_vega.jpg b/boards/openisa/rv32m1_vega/doc/rv32m1_vega.jpg similarity index 100% rename from boards/riscv/rv32m1_vega/doc/rv32m1_vega.jpg rename to boards/openisa/rv32m1_vega/doc/rv32m1_vega.jpg diff --git a/boards/riscv/rv32m1_vega/doc/rv32m1_vega_jtag.jpg b/boards/openisa/rv32m1_vega/doc/rv32m1_vega_jtag.jpg similarity index 100% rename from boards/riscv/rv32m1_vega/doc/rv32m1_vega_jtag.jpg rename to boards/openisa/rv32m1_vega/doc/rv32m1_vega_jtag.jpg diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega-pinctrl.dtsi b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1-pinctrl.dtsi similarity index 100% rename from boards/riscv/rv32m1_vega/rv32m1_vega-pinctrl.dtsi rename to boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1-pinctrl.dtsi diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi new file mode 100644 index 00000000000..f23b0ddd2e1 --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi @@ -0,0 +1,176 @@ +/* + * Copyright 2018 Foundries.io Ltd + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "rv32m1_vega_openisa_rv32m1-pinctrl.dtsi" +#include + +/ { + aliases { + led0 = &green_led; + led1 = &blue_led; + led2 = &red_led; + led3 = &sts_led; + pwm-led0 = &blue_pwm_led; + pwm-led1 = &green_pwm_led; + pwm-led2 = &red_pwm_led; + blue-pwm-led = &blue_pwm_led; + green-pwm-led = &green_pwm_led; + red-pwm-led = &red_pwm_led; + sw0 = &user_button_2; + sw1 = &user_button_3; + sw2 = &user_button_4; + sw3 = &user_button_5; + magn0 = &fxos8700; + accel0 = &fxos8700; + }; + + leds { + compatible = "gpio-leds"; + blue_led: led_0 { + gpios = <&gpioa 22 GPIO_ACTIVE_HIGH>; + label = "User LD1"; + }; + green_led: led_1 { + gpios = <&gpioa 23 GPIO_ACTIVE_HIGH>; + label = "User LD2"; + }; + red_led: led_2 { + gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>; + label = "User LD3"; + }; + sts_led: led_3 { + gpios = <&gpioe 0 GPIO_ACTIVE_HIGH>; + label = "User LD4"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + blue_pwm_led: pwm_led_0 { + pwms = <&tpm2 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "User PWM LD1"; + }; + green_pwm_led: pwm_led_1 { + pwms = <&tpm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "User PWM LD2"; + }; + red_pwm_led: pwm_led_2 { + pwms = <&tpm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "User PWM LD3"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_2: button_0 { + label = "User SW2"; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_3: button_1 { + label = "User SW3"; + gpios = <&gpioe 8 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_4: button_2 { + label = "User SW4"; + gpios = <&gpioe 9 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_5: button_3 { + label = "User SW5"; + gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioc 11 0>, /* A0 */ + <1 0 &gpioc 12 0>, /* A1 */ + <2 0 &gpiob 9 0>, /* A2 */ + <3 0 &gpioe 4 0>, /* A3 */ + <4 0 &gpioe 10 0>, /* A4 */ + <5 0 &gpioe 11 0>, /* A5 */ + <6 0 &gpioa 25 0>, /* D0 */ + <7 0 &gpioa 26 0>, /* D1 */ + <8 0 &gpioa 27 0>, /* D2 */ + <9 0 &gpiob 13 0>, /* D3 */ + <10 0 &gpiob 14 0>, /* D4 */ + <11 0 &gpioa 30 0>, /* D5 */ + <12 0 &gpioa 31 0>, /* D6 */ + <13 0 &gpiob 1 0>, /* D7 */ + <14 0 &gpiob 2 0>, /* D8 */ + <15 0 &gpiob 3 0>, /* D9 */ + <16 0 &gpiob 6 0>, /* D10 */ + <17 0 &gpiob 5 0>, /* D11 */ + <18 0 &gpiob 7 0>, /* D12 */ + <19 0 &gpiob 4 0>, /* D13 */ + <20 0 &gpioc 9 0>, /* D14 */ + <21 0 &gpioc 10 0>; /* D15 */ + }; +}; + +arduino_serial: &lpuart1 { + pinctrl-0 = <&lpuart1_default>; + pinctrl-names = "default"; +}; + +&lpuart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&lpuart0_default>; + pinctrl-names = "default"; +}; + +arduino_i2c: &lpi2c0 { + status = "okay"; + pinctrl-0 = <&lpi2c0_default>; + pinctrl-names = "default"; +}; + +&lpi2c3 { + status = "okay"; + pinctrl-0 = <&lpi2c3_default>; + pinctrl-names = "default"; + + fxos8700: fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + reset-gpios = <&gpioe 27 GPIO_ACTIVE_HIGH>; + int1-gpios = <&gpioe 1 GPIO_ACTIVE_LOW>; + int2-gpios = <&gpioe 22 GPIO_ACTIVE_LOW>; + }; +}; + +arduino_spi: &lpspi0 { + status = "okay"; + pinctrl-0 = <&lpspi0_default>; + pinctrl-names = "default"; +}; + +&lpspi1 { + status = "okay"; + cs-gpios = <&gpiob 22 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&lpspi1_default>; + pinctrl-names = "default"; + + mx25r32: mx25r3235f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + jedec-id = [c2 28 16]; + size = <33554432>; + }; +}; + +&tpm2 { + status = "okay"; + pinctrl-0 = <&tpm2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_defconfig b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_defconfig new file mode 100644 index 00000000000..908f07c0198 --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2018 Foundries.io Ltd + +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_MULTI_LEVEL_INTERRUPTS=y diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts new file mode 100644 index 00000000000..b21e9b960ec --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts @@ -0,0 +1,60 @@ +/* + * Copyright 2018 Foundries.io Ltd + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "openisa/rv32m1_ri5cy.dtsi" +#include "rv32m1_vega_openisa_rv32m1.dtsi" + +/ { + model = "OpenISA RV32M1 Vega RI5CY"; + compatible = "openisa,rv32m1"; + + chosen { + zephyr,sram = &m4_dtcm; + zephyr,flash = &m4_flash; + zephyr,console = &lpuart0; + zephyr,shell-uart = &lpuart0; + zephyr,uart-pipe = &lpuart0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + spi-flash0 = &mx25r32; + }; +}; + +&m4_flash { + /* + * For more information, see: + * http://docs.zephyrproject.org/latest/guides/dts/index.html + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 0x00069000>; + }; + slot1_partition: partition@69000 { + label = "image-1"; + reg = <0x00069000 0x00069000>; + }; + scratch_partition: partition@d2000 { + label = "image-scratch"; + reg = <0x000d2000 0x0001e000>; + }; + storage_partition: partition@f0000 { + label = "storage"; + reg = <0x000f0000 0x00004000>; + }; + boot_partition: partition@f4000 { + label = "mcuboot"; + reg = <0x000f4000 0x0000C000>; + }; + }; +}; diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.yaml b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.yaml new file mode 100644 index 00000000000..59add3074d0 --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.yaml @@ -0,0 +1,15 @@ +identifier: rv32m1_vega/openisa_rv32m1/ri5cy +name: RV32M1-VEGA (RI5CY) +type: mcu +arch: riscv +toolchain: + - cross-compile + - zephyr +supported: + - arduino_gpio + - arduino_i2c + - arduino_spi + - i2c + - pwm + - spi +vendor: openisa diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts new file mode 100644 index 00000000000..10d2382ca94 --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts @@ -0,0 +1,22 @@ +/* + * Copyright 2018 Foundries.io Ltd + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "openisa/rv32m1_zero_riscy.dtsi" +#include "rv32m1_vega_openisa_rv32m1.dtsi" + +/ { + model = "OpenISA RV32M1 Vega Zero RISCY"; + compatible = "openisa,rv32m1"; + + chosen { + zephyr,sram = &m0_tcm; + zephyr,flash = &m0_flash; + zephyr,console = &lpuart0; + zephyr,uart-pipe = &lpuart0; + zephyr,code-partition = &zero_riscy_code_partition; + }; +}; diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.yaml b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.yaml new file mode 100644 index 00000000000..0a2886ffabe --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.yaml @@ -0,0 +1,13 @@ +identifier: rv32m1_vega/openisa_rv32m1/zero_riscy +name: RV32M1-VEGA (ZERO-RISCY) +type: mcu +arch: riscv +toolchain: + - cross-compile + - zephyr +supported: + - arduino_gpio + - arduino_i2c + - i2c + - pwm +vendor: openisa diff --git a/boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg b/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg similarity index 100% rename from boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg rename to boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg diff --git a/boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg b/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg similarity index 100% rename from boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg rename to boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg diff --git a/boards/others/black_f407ve/Kconfig.black_f407ve b/boards/others/black_f407ve/Kconfig.black_f407ve new file mode 100644 index 00000000000..09ce6d70f2b --- /dev/null +++ b/boards/others/black_f407ve/Kconfig.black_f407ve @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLACK_F407VE + select SOC_STM32F407XE diff --git a/boards/others/black_f407ve/Kconfig.defconfig b/boards/others/black_f407ve/Kconfig.defconfig new file mode 100644 index 00000000000..2d08ba38ceb --- /dev/null +++ b/boards/others/black_f407ve/Kconfig.defconfig @@ -0,0 +1,12 @@ +# black_f407ve board configuration + +# Copyright (c) 2020 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BLACK_F407VE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_BLACK_F407VE diff --git a/boards/arm/black_f407ve/black_f407ve.dts b/boards/others/black_f407ve/black_f407ve.dts similarity index 100% rename from boards/arm/black_f407ve/black_f407ve.dts rename to boards/others/black_f407ve/black_f407ve.dts diff --git a/boards/arm/black_f407ve/black_f407ve.yaml b/boards/others/black_f407ve/black_f407ve.yaml similarity index 100% rename from boards/arm/black_f407ve/black_f407ve.yaml rename to boards/others/black_f407ve/black_f407ve.yaml diff --git a/boards/arm/black_f407ve/black_f407ve_defconfig b/boards/others/black_f407ve/black_f407ve_defconfig similarity index 85% rename from boards/arm/black_f407ve/black_f407ve_defconfig rename to boards/others/black_f407ve/black_f407ve_defconfig index 03fd48b1072..02216f83f72 100644 --- a/boards/arm/black_f407ve/black_f407ve_defconfig +++ b/boards/others/black_f407ve/black_f407ve_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/black_f407ve/board.cmake b/boards/others/black_f407ve/board.cmake similarity index 100% rename from boards/arm/black_f407ve/board.cmake rename to boards/others/black_f407ve/board.cmake diff --git a/boards/others/black_f407ve/board.yml b/boards/others/black_f407ve/board.yml new file mode 100644 index 00000000000..472d766cbc7 --- /dev/null +++ b/boards/others/black_f407ve/board.yml @@ -0,0 +1,5 @@ +board: + name: black_f407ve + vendor: others + socs: + - name: stm32f407xx diff --git a/boards/arm/black_f407ve/doc/img/black_f407ve.jpg b/boards/others/black_f407ve/doc/img/black_f407ve.jpg similarity index 100% rename from boards/arm/black_f407ve/doc/img/black_f407ve.jpg rename to boards/others/black_f407ve/doc/img/black_f407ve.jpg diff --git a/boards/arm/black_f407ve/doc/img/stm32f407vet6_left02.jpg b/boards/others/black_f407ve/doc/img/stm32f407vet6_left02.jpg similarity index 100% rename from boards/arm/black_f407ve/doc/img/stm32f407vet6_left02.jpg rename to boards/others/black_f407ve/doc/img/stm32f407vet6_left02.jpg diff --git a/boards/arm/black_f407ve/doc/img/stm32f407vet6_right01.jpg b/boards/others/black_f407ve/doc/img/stm32f407vet6_right01.jpg similarity index 100% rename from boards/arm/black_f407ve/doc/img/stm32f407vet6_right01.jpg rename to boards/others/black_f407ve/doc/img/stm32f407vet6_right01.jpg diff --git a/boards/arm/black_f407ve/doc/img/stm32f407vet6_st-link02.jpg b/boards/others/black_f407ve/doc/img/stm32f407vet6_st-link02.jpg similarity index 100% rename from boards/arm/black_f407ve/doc/img/stm32f407vet6_st-link02.jpg rename to boards/others/black_f407ve/doc/img/stm32f407vet6_st-link02.jpg diff --git a/boards/others/black_f407ve/doc/index.rst b/boards/others/black_f407ve/doc/index.rst new file mode 100644 index 00000000000..a338e7ccf4b --- /dev/null +++ b/boards/others/black_f407ve/doc/index.rst @@ -0,0 +1,243 @@ +.. _black_f407ve_board: + +Black STM32 F407VE Development Board +#################################### + +Overview +******** + +The BLACK_F407VE board features an ARM Cortex-M4 based STM32F407xx MCU +with a wide range of connectivity support and configurations. There are +multiple version of this board like ``black_f407ve``. +Here are some highlights of the BLACK_F407VE board: + +- STM32 microcontroller in LQFP100 package +- Extension header for all LQFP100 I/Os for quick connection to prototyping + board and easy probing +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V) + - Power management access point + +- Three LEDs: + + - 3.3 V power on (LD0) + - Two user LEDs: green (LD1), green (LD2) + +- Four push-buttons: RESET, K0, K1 and WK_UP +- Mini-AB connector + +.. image:: img/black_f407ve.jpg + :align: center + :alt: BLACK_F407VE + +See also board descriptions at `STM32-base website`_, +`STM32F407VET6 black board`_ and `MCUDev Black STM32F407VET6`_ + +.. warning:: The +5V pins on this board are directly connected to the +5V pin + of the USB connector. There is no protection in place. Do not + power this board through USB and an external power supply at + the same time. + + +Hardware +******** + +BLACK_F407VE board provides the following hardware components: + +- STM32F407VET6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 168 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 8MHz system crystal +- 32.768KHz RTC crystal +- JTAG/SWD header +- 512 kB Flash +- 192+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC battery CR1220 +- Advanced-control Timer (2) +- General Purpose Timers (12) +- Watchdog Timers (2) +- USART (3), UART (2) +- I2C (3) +- I2S (2) +- SPI (3) +- SDIO (1) +- CAN (2) +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- CRC calculation unit +- True random number generator +- DMA Controller +- Micro SD +- 1x 10/100 Ethernet MAC +- 1x 8 to 12-bit Parallel Camera interface +- Micro USB for power and comms +- 2x jumpers for bootloader selection +- 2x16 FMSC LCD Interface +- NRF24L01 socket +- Dimensions: 85.1mm x 72.45mm + +More information about STM32F407VE SOC can be found here: + - `STM32F407VE on www.st.com`_ + +Supported Features +================== + +The Zephyr black_f407ve board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver. + Zephyr default configuration uses CAN_2 exclusively, as + simultaneous use of CAN_1 and CAN_2 is not yet supported. + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/others/black_f407ve/black_f407ve_defconfig` + + +Pin Mapping +=========== + +BLACK_F407VE has 5 GPIO controllers. These controllers are responsible for pin +muxing, input/output, pull-up, etc. + +.. image:: img/stm32f407vet6_left02.jpg + :align: center + :alt: left pins + +.. image:: img/stm32f407vet6_right01.jpg + :align: center + :alt: right pins + +.. image:: img/stm32f407vet6_st-link02.jpg + :align: center + :alt: bottom and top pins + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PA0 +- LD3 : PD13 +- LD4 : PD12 +- LD5 : PD14 +- LD6 : PD15 +- USB DM : PA11 +- USB DP : PA12 +- CAN1_RX : PD0 +- CAN1_TX : PD1 +- CAN2_RX : PB12 +- CAN2_TX : PB13 +- SPI1 MISO : PB4 +- SPI1 MOSI : PB5 +- SPI1 SCK : PB3 +- SPI1 Flash CS : PB0 +- SPI2 MISO : PC2 +- SPI2 MOSI : PC3 +- SPI2 SCK : PB10 + +System Clock +============ + +BLACK_F407VE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock +at 168MHz, driven by 8MHz high speed external clock. + +Serial Port +=========== + +BLACK_F407VE has up to 6 UARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. +Please note that ST-Link Virtual Com Port is not wired to chip serial port. +In order to enable console output you should use a serial cable and connect +it to UART1 pins (PA9/PA10). + + +Programming and Debugging +************************* + +Applications for the ``black_f407ve`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +BLACK_F407VE board includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to BLACK_F407VE +--------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: black_f407ve + :goals: build flash + +You should see user led "LD1" blinking. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: black_f407ve + :maybe-skip-config: + :goals: debug + +.. _STM32-base website: + https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0.html + +.. _STM32F407VE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f407ve.html + +.. _STM32F407VET6 black board: + https://os.mbed.com/users/hudakz/code/STM32F407VET6_Hello/ + +.. _MCUDev Black STM32F407VET6: + https://github.com/mcauser/BLACK_F407VE diff --git a/boards/arm/black_f407ve/support/openocd.cfg b/boards/others/black_f407ve/support/openocd.cfg similarity index 100% rename from boards/arm/black_f407ve/support/openocd.cfg rename to boards/others/black_f407ve/support/openocd.cfg diff --git a/boards/others/black_f407zg_pro/Kconfig.black_f407zg_pro b/boards/others/black_f407zg_pro/Kconfig.black_f407zg_pro new file mode 100644 index 00000000000..162f8ad71de --- /dev/null +++ b/boards/others/black_f407zg_pro/Kconfig.black_f407zg_pro @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLACK_F407ZG_PRO + select SOC_STM32F407XG diff --git a/boards/others/black_f407zg_pro/Kconfig.defconfig b/boards/others/black_f407zg_pro/Kconfig.defconfig new file mode 100644 index 00000000000..52929e95a9d --- /dev/null +++ b/boards/others/black_f407zg_pro/Kconfig.defconfig @@ -0,0 +1,12 @@ +# black_f407zg board configuration + +# Copyright (c) 2020 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BLACK_F407ZG_PRO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_BLACK_F407ZG_PRO diff --git a/boards/arm/black_f407zg_pro/black_f407zg_pro.dts b/boards/others/black_f407zg_pro/black_f407zg_pro.dts similarity index 100% rename from boards/arm/black_f407zg_pro/black_f407zg_pro.dts rename to boards/others/black_f407zg_pro/black_f407zg_pro.dts diff --git a/boards/arm/black_f407zg_pro/black_f407zg_pro.yaml b/boards/others/black_f407zg_pro/black_f407zg_pro.yaml similarity index 100% rename from boards/arm/black_f407zg_pro/black_f407zg_pro.yaml rename to boards/others/black_f407zg_pro/black_f407zg_pro.yaml diff --git a/boards/arm/black_f407zg_pro/black_f407zg_pro_defconfig b/boards/others/black_f407zg_pro/black_f407zg_pro_defconfig similarity index 85% rename from boards/arm/black_f407zg_pro/black_f407zg_pro_defconfig rename to boards/others/black_f407zg_pro/black_f407zg_pro_defconfig index 3e74a5e5885..02216f83f72 100644 --- a/boards/arm/black_f407zg_pro/black_f407zg_pro_defconfig +++ b/boards/others/black_f407zg_pro/black_f407zg_pro_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimex_stm32_h407/board.cmake b/boards/others/black_f407zg_pro/board.cmake similarity index 100% rename from boards/arm/olimex_stm32_h407/board.cmake rename to boards/others/black_f407zg_pro/board.cmake diff --git a/boards/others/black_f407zg_pro/board.yml b/boards/others/black_f407zg_pro/board.yml new file mode 100644 index 00000000000..dc322315620 --- /dev/null +++ b/boards/others/black_f407zg_pro/board.yml @@ -0,0 +1,5 @@ +board: + name: black_f407zg_pro + vendor: others + socs: + - name: stm32f407xx diff --git a/boards/arm/black_f407zg_pro/doc/img/black_f407zg_pro.jpg b/boards/others/black_f407zg_pro/doc/img/black_f407zg_pro.jpg similarity index 100% rename from boards/arm/black_f407zg_pro/doc/img/black_f407zg_pro.jpg rename to boards/others/black_f407zg_pro/doc/img/black_f407zg_pro.jpg diff --git a/boards/others/black_f407zg_pro/doc/index.rst b/boards/others/black_f407zg_pro/doc/index.rst new file mode 100644 index 00000000000..1ca764cdf1d --- /dev/null +++ b/boards/others/black_f407zg_pro/doc/index.rst @@ -0,0 +1,216 @@ +.. _black_f407zg_pro_board: + +Black STM32 F407ZG Pro Development Board +######################################## + +Overview +******** + +The BLACK_F407ZG_PRO board features an ARM Cortex-M4 based STM32F407zg MCU +with a wide range of connectivity support and configurations. There are +multiple version of this board like ``black_f407ve``. +Here are some highlights of the BLACK_F407ZG_PRO board: + +- STM32 microcontroller in LQFP144 package +- Extension header for all LQFP144 I/Os for quick connection to prototyping + board and easy probing +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V) + - Power management access point + +- Three LEDs: + + - 3.3 V power on (LD0) + - Two user LEDs: green (LD1), green (LD2) + +- Four push-buttons: RESET, K0, K1 and WK_UP +- Mini-AB connector + +.. image:: img/black_f407zg_pro.jpg + :align: center + :alt: BLACK_F407ZG_PRO + +.. warning:: The +5V pins on this board are directly connected to the +5V pin + of the USB connector. There is no protection in place. Do not + power this board through USB and an external power supply at + the same time. + + +Hardware +******** + +BLACK_F407ZG_PRO board provides the following hardware components: + +- STM32F407ZGT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 168 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 8MHz system crystal +- 32.768KHz RTC crystal +- JTAG/SWD header +- 1024 kB Flash +- 192+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC battery CR1220 +- Advanced-control Timer (2) +- General Purpose Timers (12) +- Watchdog Timers (2) +- USART (3), UART (2) +- I2C (3) +- I2S (2) +- SPI (3) +- SDIO (1) +- CAN (2) +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- CRC calculation unit +- True random number generator +- DMA Controller +- Micro SD +- 1x 10/100 Ethernet MAC +- 1x 8 to 12-bit Parallel Camera interface +- Micro USB for power and comms +- 2x jumpers for bootloader selection +- 2x16 FMSC LCD Interface +- NRF24L01 socket +- Dimensions: 102.5mm x 74.56mm + +More information about STM32F407ZG SOC can be found here: + - `STM32F407ZG on www.st.com`_ + +Supported Features +================== + +The Zephyr black_f407zg_pro board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver. + Zephyr default configuration uses CAN_2 exclusively, as + simultaneous use of CAN_1 and CAN_2 is not yet supported. + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/others/black_f407zg_pro/black_f407zg_pro_defconfig` + + +Pin Mapping +=========== + +BLACK_F407ZG_PRO has 7 GPIO controllers. These controllers are responsible for pin +muxing, input/output, pull-up, etc. + + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PA0 +- LD3 : PD13 +- LD4 : PD12 +- LD5 : PD14 +- LD6 : PD15 +- USB DM : PA11 +- USB DP : PA12 +- CAN1_RX : PD0 +- CAN1_TX : PD1 +- CAN2_RX : PB12 +- CAN2_TX : PB13 +- SPI2 MISO : PC2 +- SPI2 MOSI : PC3 +- SPI2 SCK : PB10 + +System Clock +============ + +BLACK_F407ZG_PRO System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock +at 168MHz, driven by 8MHz high speed external clock. + +Serial Port +=========== + +BLACK_F407ZG_PRO has up to 6 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. +Please note that ST-Link Virtual Com Port is not wired to chip serial port. +In order to enable console output you should use a serial cable and connect +it to UART2 pins (PA2/PA3). + + +Programming and Debugging +************************* + +Applications for the ``black_f407zg_pro`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +BLACK_F407ZG_PRO board includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to BLACK_F407ZG_PRO +------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: black_f407zg_pro + :goals: build flash + +You should see user led "LD1" blinking. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: black_f407zg_pro + :maybe-skip-config: + :goals: debug + +.. _STM32F407ZG on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32f407zg.html diff --git a/boards/arm/black_f407zg_pro/support/openocd.cfg b/boards/others/black_f407zg_pro/support/openocd.cfg similarity index 100% rename from boards/arm/black_f407zg_pro/support/openocd.cfg rename to boards/others/black_f407zg_pro/support/openocd.cfg diff --git a/boards/others/icev_wireless/Kconfig.defconfig b/boards/others/icev_wireless/Kconfig.defconfig new file mode 100644 index 00000000000..96ed16249d4 --- /dev/null +++ b/boards/others/icev_wireless/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2022 Friedt Professional Engineering Services, Inc +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice diff --git a/boards/others/icev_wireless/Kconfig.icev_wireless b/boards/others/icev_wireless/Kconfig.icev_wireless new file mode 100644 index 00000000000..22ef32910e5 --- /dev/null +++ b/boards/others/icev_wireless/Kconfig.icev_wireless @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Friedt Professional Engineering Services, Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ICEV_WIRELESS + select SOC_ESP32C3_MINI_N4 diff --git a/boards/xtensa/olimex_esp32_evb/Kconfig.sysbuild b/boards/others/icev_wireless/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/olimex_esp32_evb/Kconfig.sysbuild rename to boards/others/icev_wireless/Kconfig.sysbuild diff --git a/boards/xtensa/m5stack_core2/board.cmake b/boards/others/icev_wireless/board.cmake similarity index 100% rename from boards/xtensa/m5stack_core2/board.cmake rename to boards/others/icev_wireless/board.cmake diff --git a/boards/others/icev_wireless/board.yml b/boards/others/icev_wireless/board.yml new file mode 100644 index 00000000000..2dcef96cbdf --- /dev/null +++ b/boards/others/icev_wireless/board.yml @@ -0,0 +1,5 @@ +board: + name: icev_wireless + vendor: others + socs: + - name: esp32c3 diff --git a/boards/riscv/icev_wireless/doc/img/icev_wireless.jpg b/boards/others/icev_wireless/doc/img/icev_wireless.jpg similarity index 100% rename from boards/riscv/icev_wireless/doc/img/icev_wireless.jpg rename to boards/others/icev_wireless/doc/img/icev_wireless.jpg diff --git a/boards/riscv/icev_wireless/doc/img/icev_wireless_back.jpg b/boards/others/icev_wireless/doc/img/icev_wireless_back.jpg similarity index 100% rename from boards/riscv/icev_wireless/doc/img/icev_wireless_back.jpg rename to boards/others/icev_wireless/doc/img/icev_wireless_back.jpg diff --git a/boards/riscv/icev_wireless/doc/img/icev_wireless_pinout.jpg b/boards/others/icev_wireless/doc/img/icev_wireless_pinout.jpg similarity index 100% rename from boards/riscv/icev_wireless/doc/img/icev_wireless_pinout.jpg rename to boards/others/icev_wireless/doc/img/icev_wireless_pinout.jpg diff --git a/boards/others/icev_wireless/doc/index.rst b/boards/others/icev_wireless/doc/index.rst new file mode 100644 index 00000000000..a931bb33da7 --- /dev/null +++ b/boards/others/icev_wireless/doc/index.rst @@ -0,0 +1,259 @@ +.. _icev_wireless: + +ICE-V Wireless +############## + +Overview +******** + +The ICE-V Wireless is a combined ESP32C3 and iCE40 FPGA board. + +See the `ICE-V Wireless Github Project`_ for details. + +.. figure:: img/icev_wireless.jpg + :align: center + :alt: ICE-V Wireless + + ICE-V Wireless + +Hardware +******** + +This board combines an Espressif ESP32-C3-MINI-1 (which includes 4MB of flash in the module) with a +Lattice iCE40UP5k-SG48 FPGA to allow WiFi and Bluetooth control of the FPGA. ESP32 and FPGA I/O is +mostly uncommitted except for the pins used for SPI communication between ESP32 and FPGA. Several +of the ESP32C3 GPIO pins are available for additonal interfaces such as serial, ADC, I2C, etc. + +For details on ESP32-C3 hardware please refer to the following resources: + +* `ESP32-C3-MINI-1 Datasheet`_ +* `ESP32-C3 Datasheet`_ +* `ESP32-C3 Technical Reference Manual`_ + +For details on iCE40 hardware please refer to the following resources: + +* `iCE40 UltraPlus Family Datasheet`_ + +Supported Features +================== + +The ICE-V Wireless board configuration supports the following hardware +features: + ++-----------+------------+------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==================+ +| PMP | on-chip | arch/riscv | ++-----------+------------+------------------+ +| INTMTRX | on-chip | intc_esp32c3 | ++-----------+------------+------------------+ +| PINMUX | on-chip | pinctrl_esp32 | ++-----------+------------+------------------+ +| USB UART | on-chip | serial_esp32_usb | ++-----------+------------+------------------+ +| GPIO | on-chip | gpio_esp32 | ++-----------+------------+------------------+ +| UART | on-chip | uart_esp32 | ++-----------+------------+------------------+ +| I2C | on-chip | i2c_esp32 | ++-----------+------------+------------------+ +| SPI | on-chip | spi_esp32_spim | ++-----------+------------+------------------+ +| ADC | on-chip | | ++-----------+------------+------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +The ICE-V Wireless provides 1 row of reference, ESP32-C3, and iCE40 signals +brought out to J3, as well as 3 PMOD connectors for interfacing directly to +the iCE40 FPGA. Note that several of the iCE40 pins brought out to the PMOD +connectors are capable of operating as differential pairs. + +.. figure:: img/icev_wireless_back.jpg + :align: center + :alt: ICE-V Wireless (Back) + + ICE-V Wireless (Back) + +The J3 pins are 4V, 3.3V, NRST, GPIO2, GPIO3, GPIO8, GPIO9, GPIO10, GPIO20, +GPIO21, FPGA_P34, and GND. Note that GPIO2 and GPIO3 may be configured for +ADC operation. + +For PMOD details, please refer to the `PMOD Specification`_ and the image +below. + +.. figure:: img/icev_wireless_pinout.jpg + :align: center + :alt: ICE-V Wireless Pinout + +Programming and Debugging +************************* + +Programming and debugging for the ICE-V Wireless ESP32-C3 target is +incredibly easy 🎉 following the steps below. + +Building and Flashing +********************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: icev_wireless + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +For the :code:`Hello, world!` application, follow the instructions below. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: icev_wireless + :goals: build flash + +Open the serial monitor using the following command: + +.. code-block:: console + + $ west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! icev_wireless + +Debugging +********* + +As with much custom hardware, the ESP32C3 modules require patches to +OpenOCD that are not upstreamed. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained by running the following extension: + +.. code-block:: console + + west espressif install + +.. note:: + + By default, the OpenOCD will be downloaded and installed under $HOME/.espressif/tools/zephyr directory + (%USERPROFILE%/.espressif/tools/zephyr on Windows). + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: icev_wireless + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: icev_wireless + :maybe-skip-config: + :goals: debug + +References +********** + +.. _ICE-V Wireless Github Project: + https://github.com/ICE-V-Wireless/ICE-V-Wireless + +.. _ESP32-C3-MINI-1 Datasheet: + https://www.espressif.com/sites/default/files/documentation/esp32-c3-mini-1_datasheet_en.pdf + +.. _ESP32-C3 Datasheet: + https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf + +.. _ESP32-C3 Technical Reference Manual: + https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf + +.. _iCE40 UltraPlus Family Datasheet: + https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/iCE/iCE40-UltraPlus-Family-Data-Sheet.ashx + +.. _PMOD Specification: + https://digilent.com/reference/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf diff --git a/boards/riscv/icev_wireless/icev_wireless-pinctrl.dtsi b/boards/others/icev_wireless/icev_wireless-pinctrl.dtsi similarity index 100% rename from boards/riscv/icev_wireless/icev_wireless-pinctrl.dtsi rename to boards/others/icev_wireless/icev_wireless-pinctrl.dtsi diff --git a/boards/riscv/icev_wireless/icev_wireless.dts b/boards/others/icev_wireless/icev_wireless.dts similarity index 98% rename from boards/riscv/icev_wireless/icev_wireless.dts rename to boards/others/icev_wireless/icev_wireless.dts index 1e5719fe2aa..8ed474200e0 100644 --- a/boards/riscv/icev_wireless/icev_wireless.dts +++ b/boards/others/icev_wireless/icev_wireless.dts @@ -11,7 +11,7 @@ #include / { - model = "icev_wireless"; + model = "ICEV Wireless"; compatible = "espressif,esp32c3"; chosen { diff --git a/boards/riscv/icev_wireless/icev_wireless.yaml b/boards/others/icev_wireless/icev_wireless.yaml similarity index 100% rename from boards/riscv/icev_wireless/icev_wireless.yaml rename to boards/others/icev_wireless/icev_wireless.yaml diff --git a/boards/others/icev_wireless/icev_wireless_defconfig b/boards/others/icev_wireless/icev_wireless_defconfig new file mode 100644 index 00000000000..ef633ce56a1 --- /dev/null +++ b/boards/others/icev_wireless/icev_wireless_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/riscv/icev_wireless/support/openocd.cfg b/boards/others/icev_wireless/support/openocd.cfg similarity index 100% rename from boards/riscv/icev_wireless/support/openocd.cfg rename to boards/others/icev_wireless/support/openocd.cfg diff --git a/boards/others/index.rst b/boards/others/index.rst new file mode 100644 index 00000000000..c39d99c4d08 --- /dev/null +++ b/boards/others/index.rst @@ -0,0 +1,10 @@ +.. _boards-others: + +Other and unknown vendors +######################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/riscv/neorv32/CMakeLists.txt b/boards/others/neorv32/CMakeLists.txt similarity index 100% rename from boards/riscv/neorv32/CMakeLists.txt rename to boards/others/neorv32/CMakeLists.txt diff --git a/boards/others/neorv32/Kconfig b/boards/others/neorv32/Kconfig new file mode 100644 index 00000000000..57e0edc10d6 --- /dev/null +++ b/boards/others/neorv32/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NEORV32 + select SOC_NEORV32_V1_8_6 if "$(BOARD_REVISION)" = "1.8.6" diff --git a/boards/others/neorv32/Kconfig.neorv32 b/boards/others/neorv32/Kconfig.neorv32 new file mode 100644 index 00000000000..1e5efecd08f --- /dev/null +++ b/boards/others/neorv32/Kconfig.neorv32 @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NEORV32 + select SOC_NEORV32 diff --git a/boards/riscv/neorv32/board.cmake b/boards/others/neorv32/board.cmake similarity index 100% rename from boards/riscv/neorv32/board.cmake rename to boards/others/neorv32/board.cmake diff --git a/boards/others/neorv32/board.yml b/boards/others/neorv32/board.yml new file mode 100644 index 00000000000..f12fa42b78f --- /dev/null +++ b/boards/others/neorv32/board.yml @@ -0,0 +1,10 @@ +board: + name: neorv32 + vendor: others + revision: + format: major.minor.patch + default: "1.8.6" + revisions: + - name: "1.8.6" + socs: + - name: neorv32 diff --git a/boards/riscv/neorv32/doc/index.rst b/boards/others/neorv32/doc/index.rst similarity index 100% rename from boards/riscv/neorv32/doc/index.rst rename to boards/others/neorv32/doc/index.rst diff --git a/boards/riscv/neorv32/neorv32.dts b/boards/others/neorv32/neorv32.dts similarity index 100% rename from boards/riscv/neorv32/neorv32.dts rename to boards/others/neorv32/neorv32.dts diff --git a/boards/riscv/neorv32/neorv32.yaml b/boards/others/neorv32/neorv32.yaml similarity index 100% rename from boards/riscv/neorv32/neorv32.yaml rename to boards/others/neorv32/neorv32.yaml diff --git a/boards/riscv/neorv32/neorv32_defconfig b/boards/others/neorv32/neorv32_defconfig similarity index 84% rename from boards/riscv/neorv32/neorv32_defconfig rename to boards/others/neorv32/neorv32_defconfig index 7dc8a74ffff..2642d046b50 100644 --- a/boards/riscv/neorv32/neorv32_defconfig +++ b/boards/others/neorv32/neorv32_defconfig @@ -1,9 +1,7 @@ # Copyright (c) 2021 Henrik Brix Andersen # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_NEORV32=y CONFIG_SOC_NEORV32_ISA_C=y -CONFIG_BOARD_NEORV32=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/neorv32/support/neorv32.cfg b/boards/others/neorv32/support/neorv32.cfg similarity index 100% rename from boards/riscv/neorv32/support/neorv32.cfg rename to boards/others/neorv32/support/neorv32.cfg diff --git a/boards/riscv/neorv32/support/openocd.cfg b/boards/others/neorv32/support/openocd.cfg similarity index 100% rename from boards/riscv/neorv32/support/openocd.cfg rename to boards/others/neorv32/support/openocd.cfg diff --git a/boards/others/stm32_min_dev/Kconfig.stm32_min_dev b/boards/others/stm32_min_dev/Kconfig.stm32_min_dev new file mode 100644 index 00000000000..6ca578a2287 --- /dev/null +++ b/boards/others/stm32_min_dev/Kconfig.stm32_min_dev @@ -0,0 +1,7 @@ +# STM32 Minimum Development Board Configuration + +# Copyright (c) 2017, embedjournal.com +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32_MIN_DEV + select SOC_STM32F103X8 diff --git a/boards/arm/stm32_min_dev/board.cmake b/boards/others/stm32_min_dev/board.cmake similarity index 100% rename from boards/arm/stm32_min_dev/board.cmake rename to boards/others/stm32_min_dev/board.cmake diff --git a/boards/others/stm32_min_dev/board.yml b/boards/others/stm32_min_dev/board.yml new file mode 100644 index 00000000000..28a35697379 --- /dev/null +++ b/boards/others/stm32_min_dev/board.yml @@ -0,0 +1,7 @@ +board: + name: stm32_min_dev + vendor: others + revision: + format: custom + socs: + - name: stm32f103xb diff --git a/boards/arm/stm32_min_dev/doc/img/stm32_min_dev.jpg b/boards/others/stm32_min_dev/doc/img/stm32_min_dev.jpg similarity index 100% rename from boards/arm/stm32_min_dev/doc/img/stm32_min_dev.jpg rename to boards/others/stm32_min_dev/doc/img/stm32_min_dev.jpg diff --git a/boards/arm/stm32_min_dev/doc/img/stm32_min_dev_pinout_blue.jpg b/boards/others/stm32_min_dev/doc/img/stm32_min_dev_pinout_blue.jpg similarity index 100% rename from boards/arm/stm32_min_dev/doc/img/stm32_min_dev_pinout_blue.jpg rename to boards/others/stm32_min_dev/doc/img/stm32_min_dev_pinout_blue.jpg diff --git a/boards/others/stm32_min_dev/doc/index.rst b/boards/others/stm32_min_dev/doc/index.rst new file mode 100644 index 00000000000..61caf674f95 --- /dev/null +++ b/boards/others/stm32_min_dev/doc/index.rst @@ -0,0 +1,186 @@ +.. _stm32_min_dev: + +STM32 Minimum Development Board +############################### + +Overview +******** + +The STM32 Minimum Development Board, is a popular and inexpensive +breadboard-friendly breakout board for the `STM32F103x8`_ CPU. There +are two variants of the board: + +- Blue Pill Board +- Black Pill Board + +Zephyr applications can use the stm32_min_dev@blue or stm32_min_dev@black board +configuration to use these boards. + +.. figure:: img/stm32_min_dev.jpg + :align: center + :alt: STM32 Minimum Development Board + + STM32 Minimum Development Board + +As the name suggests, these boards have the bare minimum components required to +power on the CPU. For practical use, you'll need to add additional components +and circuits using a breadboard, for example. + +Pin Mapping +=========== + +This port is a starting point for your own customizations and not a complete +port for a specific board. Most of the GPIOs on the STM32 SoC has been exposed +in the external header with silk screen labels that match the SoC's pin names. + +Each board vendor has their own variations in pin mapping on their boards' +external connectors and placement of components. Many vendors use port PC13/PB12 +for connecting an LED, so only this device is supported by our Zephyr port. +Additional device support is left for the user to implement. + +More information on hooking up peripherals and lengthy how to articles can be +found at `EmbedJournal`_. + +The pinout diagram of STM32 Minimum Development Blue Pill board can be seen +below. The Black Pill's one is similar: + +.. figure:: img/stm32_min_dev_pinout_blue.jpg + :align: center + :alt: Pinout for STM32 Minimum Development Blue Pill Board + + Pinout for STM32 Minimum Development Blue Pill Board + + +STLinkV2 connection: +==================== + +The board can be flashed by using STLinkV2 with the following connections. + ++--------+---------------+ +| Pin | STLINKv2 | ++========+===============+ +| G | GND | ++--------+---------------+ +| CLK | Clock | ++--------+---------------+ +| IO | SW IO | ++--------+---------------+ +| V3 | VCC | ++--------+---------------+ + +Boot Configuration +================== + +The boot configuration for this board is configured through jumpers on B0 (Boot 0) +and B1 (Boot 1). The pins B0 and B1 are present in between logic 0 and 1 lines. The +silk screen on the PCB reads BX- or BX+ to indicate 0 and 1 logic lines for B0 and B1 +respectively. + ++--------+--------+-------------------+---------------------------------------------+ +| Boot 1 | Boot 0 | Boot Mode | Aliasing | ++========+========+===================+=============================================+ +| X | 0 | Main Flash Memory | Main flash memory is selected as boot space | ++--------+--------+-------------------+---------------------------------------------+ +| 0 | 1 | System Memory | System memory is selected as boot space | ++--------+--------+-------------------+---------------------------------------------+ +| 1 | 1 | Embedded SRAM | Embedded SRAM is selected as boot space | ++--------+--------+-------------------+---------------------------------------------+ + + +Supported Features +================== + +The stm32_min_dev board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+----------------------+ +| UART | on-chip | serial port | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| USB | on-chip | USB device | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX: PA9/PA10 +- UART_2 TX/RX: PA2/PA3 +- UART_3 TX/RX: PB10/PB11 +- I2C_1 SCL/SDA : PB6/PB7 +- I2C_2 SCL/SDA : PB10/PB11 +- PWM_1_CH1: PA8 +- SPI_1 NSS_OE/SCK/MISO/MOSI: PA4/PA5/PA6/PA7 +- SPI_2 NSS_OE/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 +- USB_DC DM/DP: PA11/PA12 +- ADC_1: PA0 + +System Clock +------------ + +The on-board 8Mhz crystal is used to produce a 72Mhz system clock with PLL. + +Serial Port +----------- + +STM32 Minimum Development Board has 3 U(S)ARTs. The Zephyr console output is +assigned to UART_1. Default settings are 115200 8N1. + +On-Board LEDs +------------- + +The board has one on-board LED that is connected to PB12/PC13 on the black/blue +variants respectively. + +Programming and Debugging +************************* + +Applications for the ``stm32_min_dev@(blue|black)`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32_min_dev + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32_min_dev + :maybe-skip-config: + :goals: debug + +.. _STM32F103x8: + https://www.st.com/resource/en/datasheet/stm32f103c8.pdf +.. _EmbedJournal: + https://embedjournal.com/tag/stm32-min-dev/ diff --git a/boards/others/stm32_min_dev/revision.cmake b/boards/others/stm32_min_dev/revision.cmake new file mode 100644 index 00000000000..37dc3550db8 --- /dev/null +++ b/boards/others/stm32_min_dev/revision.cmake @@ -0,0 +1,8 @@ +set(BOARD_REVISIONS "blue" "black") +if(NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION "blue") +else() + if(NOT BOARD_REVISION IN_LIST BOARD_REVISIONS) + message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for stm32_min_dev. Accepted revisions: ${BOARD_REVISIONS}") + endif() +endif() diff --git a/boards/arm/stm32_min_dev/stm32_min_dev.dtsi b/boards/others/stm32_min_dev/stm32_min_dev.dts similarity index 100% rename from boards/arm/stm32_min_dev/stm32_min_dev.dtsi rename to boards/others/stm32_min_dev/stm32_min_dev.dts diff --git a/boards/others/stm32_min_dev/stm32_min_dev_black.yaml b/boards/others/stm32_min_dev/stm32_min_dev_black.yaml new file mode 100644 index 00000000000..0740dc17faf --- /dev/null +++ b/boards/others/stm32_min_dev/stm32_min_dev_black.yaml @@ -0,0 +1,15 @@ +identifier: stm32_min_dev@black +name: STM32 Minimum Development Board +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 20 +supported: + - i2c + - pwm + - spi + - adc + - gpio diff --git a/boards/others/stm32_min_dev/stm32_min_dev_blue.yaml b/boards/others/stm32_min_dev/stm32_min_dev_blue.yaml new file mode 100644 index 00000000000..8249d6f9719 --- /dev/null +++ b/boards/others/stm32_min_dev/stm32_min_dev_blue.yaml @@ -0,0 +1,15 @@ +identifier: stm32_min_dev@blue +name: STM32 Minimum Development Board +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 20 +supported: + - i2c + - pwm + - spi + - adc + - gpio diff --git a/boards/others/stm32_min_dev/stm32_min_dev_defconfig b/boards/others/stm32_min_dev/stm32_min_dev_defconfig new file mode 100644 index 00000000000..ac78c1fed4e --- /dev/null +++ b/boards/others/stm32_min_dev/stm32_min_dev_defconfig @@ -0,0 +1,21 @@ +# STM32 Minimum Development Board Configuration +# +# Copyright (c) 2019, embedjournal.com +# +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# enable clock control +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_black.overlay b/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_black.overlay new file mode 100644 index 00000000000..25b8bf2688c --- /dev/null +++ b/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_black.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2019, embedjournal.com + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + model = "STM32 Minimum Development Board (Black)"; + compatible = "stm32_min_dev_black", "st,stm32f103c8"; + + leds { + led: led { + gpios = <&gpiob 12 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_blue.overlay b/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_blue.overlay new file mode 100644 index 00000000000..41f657276d5 --- /dev/null +++ b/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_blue.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2017, embedjournal.com + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + model = "STM32 Minimum Development Board (Blue)"; + compatible = "stm32_min_dev_blue", "st,stm32f103c8"; + + leds { + led: led { + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/boards/arm/stm32_min_dev/support/openocd.cfg b/boards/others/stm32_min_dev/support/openocd.cfg similarity index 100% rename from boards/arm/stm32_min_dev/support/openocd.cfg rename to boards/others/stm32_min_dev/support/openocd.cfg diff --git a/boards/others/stm32f030_demo/Kconfig.stm32f030_demo b/boards/others/stm32f030_demo/Kconfig.stm32f030_demo new file mode 100644 index 00000000000..b349bf791c7 --- /dev/null +++ b/boards/others/stm32f030_demo/Kconfig.stm32f030_demo @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Antony Pavlov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F030_DEMO + select SOC_STM32F030X4 diff --git a/boards/arm/stm32f030_demo/board.cmake b/boards/others/stm32f030_demo/board.cmake similarity index 100% rename from boards/arm/stm32f030_demo/board.cmake rename to boards/others/stm32f030_demo/board.cmake diff --git a/boards/others/stm32f030_demo/board.yml b/boards/others/stm32f030_demo/board.yml new file mode 100644 index 00000000000..348d40a665b --- /dev/null +++ b/boards/others/stm32f030_demo/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f030_demo + vendor: others + socs: + - name: stm32f030x6 diff --git a/boards/arm/stm32f030_demo/doc/img/stm32f030_demo.jpg b/boards/others/stm32f030_demo/doc/img/stm32f030_demo.jpg similarity index 100% rename from boards/arm/stm32f030_demo/doc/img/stm32f030_demo.jpg rename to boards/others/stm32f030_demo/doc/img/stm32f030_demo.jpg diff --git a/boards/others/stm32f030_demo/doc/index.rst b/boards/others/stm32f030_demo/doc/index.rst new file mode 100644 index 00000000000..8080f2b33d9 --- /dev/null +++ b/boards/others/stm32f030_demo/doc/index.rst @@ -0,0 +1,123 @@ +.. _stm32f030_demo: + +STM32F030 DEMO BOARD +#################### + +This board has the bare minimum components required to power on +the STM32F030F4P6 MCU. Most of the GPIOs on the STM32 SoC have +been exposed in the external headers with silk screen labels +that match the SoC's pin names. + +For practical use, you'll need to add additional components +and circuits using a breadboard, for example. + +.. image:: img/stm32f030_demo.jpg + :align: center + :alt: STM32F030 DEMO BOARD + +More information about the board can be found at the `stm32-base.org website`_. + +More information about STM32F030F4P6 can be found here: + +- `STM32F030 reference manual`_ +- `STM32F030 data sheet`_ + +Hardware +******** + +- STM32F030F4P6 ARM Cortex-M0 processor, frequency up to 48 MHz +- 16 KiB of flash memory and 4 KiB of RAM +- 8 MHz quartz crystal +- 1 user LED +- One reset button +- 2-way jumper (BOOT0) +- Serial (1x4 male dupont (2.54mm)) +- SWD (1x4 male dupont (2.54mm)) +- USB port (power only) + +Supported Features +================== + +The Zephyr stm32f030_demo board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/others/stm32f030_demo/stm32f030_demo_defconfig` + +Pin Mapping +=========== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- LED : PA4 + +Programming and Debugging +************************* + +Applications for the ``stm32f030_demo`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The board can be flashed by using ST-LINKV2 in-circuit debugger and programmer. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to STM32F030 DEMO BOARD +----------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f030_demo + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f030_demo + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _stm32-base.org website: + https://stm32-base.org/boards/STM32F030F4P6-STM32F030-DEMO-BOARD-V1.1 + +.. _STM32F030 reference manual: + https://www.st.com/resource/en/reference_manual/dm00091010.pdf + +.. _STM32F030 data sheet: + https://www.st.com/resource/en/datasheet/stm32f030f4.pdf diff --git a/boards/arm/stm32f030_demo/stm32f030_demo.dts b/boards/others/stm32f030_demo/stm32f030_demo.dts similarity index 100% rename from boards/arm/stm32f030_demo/stm32f030_demo.dts rename to boards/others/stm32f030_demo/stm32f030_demo.dts diff --git a/boards/arm/stm32f030_demo/stm32f030_demo.yaml b/boards/others/stm32f030_demo/stm32f030_demo.yaml similarity index 100% rename from boards/arm/stm32f030_demo/stm32f030_demo.yaml rename to boards/others/stm32f030_demo/stm32f030_demo.yaml diff --git a/boards/arm/stm32f030_demo/stm32f030_demo_defconfig b/boards/others/stm32f030_demo/stm32f030_demo_defconfig similarity index 80% rename from boards/arm/stm32f030_demo/stm32f030_demo_defconfig rename to boards/others/stm32f030_demo/stm32f030_demo_defconfig index 1e436d1e3ea..d7de7d90f54 100644 --- a/boards/arm/stm32f030_demo/stm32f030_demo_defconfig +++ b/boards/others/stm32f030_demo/stm32f030_demo_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F030X4=y - # Kernel Options due to Low Memory (4k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/arm/stm32f030_demo/support/openocd.cfg b/boards/others/stm32f030_demo/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f030_demo/support/openocd.cfg rename to boards/others/stm32f030_demo/support/openocd.cfg diff --git a/boards/others/stm32f401_mini/Kconfig.defconfig b/boards/others/stm32f401_mini/Kconfig.defconfig new file mode 100644 index 00000000000..b622b27da98 --- /dev/null +++ b/boards/others/stm32f401_mini/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2022 Brian Bradley +# SPDX-License-Identifier: Apache-2.0 + +# STM32 Mini F401 board definitions + +if BOARD_STM32F401_MINI + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_STM32F401_MINI diff --git a/boards/others/stm32f401_mini/Kconfig.stm32f401_mini b/boards/others/stm32f401_mini/Kconfig.stm32f401_mini new file mode 100644 index 00000000000..8b1c204760e --- /dev/null +++ b/boards/others/stm32f401_mini/Kconfig.stm32f401_mini @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Brian Bradley +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F401_MINI + select SOC_STM32F401XC diff --git a/boards/arm/stm32f401_mini/board.cmake b/boards/others/stm32f401_mini/board.cmake similarity index 100% rename from boards/arm/stm32f401_mini/board.cmake rename to boards/others/stm32f401_mini/board.cmake diff --git a/boards/others/stm32f401_mini/board.yml b/boards/others/stm32f401_mini/board.yml new file mode 100644 index 00000000000..b6ec3cd3af8 --- /dev/null +++ b/boards/others/stm32f401_mini/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f401_mini + vendor: others + socs: + - name: stm32f401xc diff --git a/boards/arm/stm32f401_mini/doc/img/STM32_Mini_F401-1.jpg b/boards/others/stm32f401_mini/doc/img/STM32_Mini_F401-1.jpg similarity index 100% rename from boards/arm/stm32f401_mini/doc/img/STM32_Mini_F401-1.jpg rename to boards/others/stm32f401_mini/doc/img/STM32_Mini_F401-1.jpg diff --git a/boards/others/stm32f401_mini/doc/index.rst b/boards/others/stm32f401_mini/doc/index.rst new file mode 100644 index 00000000000..b24538f3137 --- /dev/null +++ b/boards/others/stm32f401_mini/doc/index.rst @@ -0,0 +1,153 @@ +.. _stm32f401_mini: + +STM32 Mini F401 +############### + +Overview +******** + +The STM32 Mini F401 is an extremely low cost and bare-bones +development board featuring the STM32F401CC, see `STM32F401CC website`_. +More info about the board with schematics available `here `_ + +.. image:: img/STM32_Mini_F401-1.jpg + :align: center + :alt: STM32 Mini F401 + +Hardware +******** + +The STM32F401CC based board provides the following +hardware components: + +- STM32F401CCU6 in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 84 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 256 KB Flash +- 64 KB SRAM +- GPIO with external interrupt capability +- 1x12-bit, 2.4 MSPS ADC with 16 channels +- DMA Controller +- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (3) +- I2C (3) +- SPI/I2S (4) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- CRC calculation unit +- 96-bit unique ID +- RTC + +Supported Features +================== + +The Zephyr stm32f401_mini board configuration supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/others/stm32f401_mini/stm32f401_mini_defconfig` + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- I2C1 SCL/SDA : PB8/PB9 +- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 +- PWM_4_CH1 : PB6 +- PWM_4_CH2 : PB7 +- ADC_1 : PA1 +- SW0 : PB2 (routed to BOOT1 dip switch) +- LED0 : PC13 + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is +32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. + +The default configuration sources the system clock from the PLL, which is +derived from HSE, and is set at 84MHz. + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin, which on this board +is a dip switch. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an Application +----------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by setting the BOOT0 dip switch position to ON. Reset the board with the NRST button. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f401_mini + :goals: build flash + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, +and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO +pins on that header. + +References +********** + +.. target-notes:: + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _stm32-base-board-page: + https://stm32-base.org/boards/STM32F401CCU6-STM32-Mini-F401 + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32F401CC website: + https://www.st.com/en/microcontrollers-microprocessors/stm32f401cc.html diff --git a/boards/arm/stm32f401_mini/stm32f401_mini.dts b/boards/others/stm32f401_mini/stm32f401_mini.dts similarity index 100% rename from boards/arm/stm32f401_mini/stm32f401_mini.dts rename to boards/others/stm32f401_mini/stm32f401_mini.dts diff --git a/boards/arm/stm32f401_mini/stm32f401_mini.yaml b/boards/others/stm32f401_mini/stm32f401_mini.yaml similarity index 100% rename from boards/arm/stm32f401_mini/stm32f401_mini.yaml rename to boards/others/stm32f401_mini/stm32f401_mini.yaml diff --git a/boards/arm/stm32f401_mini/stm32f401_mini_defconfig b/boards/others/stm32f401_mini/stm32f401_mini_defconfig similarity index 86% rename from boards/arm/stm32f401_mini/stm32f401_mini_defconfig rename to boards/others/stm32f401_mini/stm32f401_mini_defconfig index cd8cbcfcad1..8f08a2bfe96 100644 --- a/boards/arm/stm32f401_mini/stm32f401_mini_defconfig +++ b/boards/others/stm32f401_mini/stm32f401_mini_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/blackpill_f401cc/support/openocd.cfg b/boards/others/stm32f401_mini/support/openocd.cfg similarity index 100% rename from boards/arm/blackpill_f401cc/support/openocd.cfg rename to boards/others/stm32f401_mini/support/openocd.cfg diff --git a/boards/panasonic/index.rst b/boards/panasonic/index.rst new file mode 100644 index 00000000000..cc32d30559f --- /dev/null +++ b/boards/panasonic/index.rst @@ -0,0 +1,10 @@ +.. _boards-panasonic: + +Panasonic Corporation +##################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/pan1770_evb/Kconfig b/boards/panasonic/pan1770_evb/Kconfig similarity index 100% rename from boards/arm/pan1770_evb/Kconfig rename to boards/panasonic/pan1770_evb/Kconfig diff --git a/boards/panasonic/pan1770_evb/Kconfig.defconfig b/boards/panasonic/pan1770_evb/Kconfig.defconfig new file mode 100644 index 00000000000..8a91e35369a --- /dev/null +++ b/boards/panasonic/pan1770_evb/Kconfig.defconfig @@ -0,0 +1,11 @@ +# PAN1770 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PAN1770_EVB + +config BT_CTLR + default BT + +endif # BOARD_PAN1770_EVB diff --git a/boards/panasonic/pan1770_evb/Kconfig.pan1770_evb b/boards/panasonic/pan1770_evb/Kconfig.pan1770_evb new file mode 100644 index 00000000000..26aa94c1f71 --- /dev/null +++ b/boards/panasonic/pan1770_evb/Kconfig.pan1770_evb @@ -0,0 +1,7 @@ +# PAN1770 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1770_EVB + select SOC_NRF52840_QIAA diff --git a/boards/arm/pan1770_evb/board.cmake b/boards/panasonic/pan1770_evb/board.cmake similarity index 100% rename from boards/arm/pan1770_evb/board.cmake rename to boards/panasonic/pan1770_evb/board.cmake diff --git a/boards/panasonic/pan1770_evb/board.yml b/boards/panasonic/pan1770_evb/board.yml new file mode 100644 index 00000000000..0808b91b99b --- /dev/null +++ b/boards/panasonic/pan1770_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: pan1770_evb + vendor: panasonic + socs: + - name: nrf52840 diff --git a/boards/arm/pan1770_evb/doc/index.rst b/boards/panasonic/pan1770_evb/doc/index.rst similarity index 100% rename from boards/arm/pan1770_evb/doc/index.rst rename to boards/panasonic/pan1770_evb/doc/index.rst diff --git a/boards/arm/pan1770_evb/doc/pan1770_evaluation_board.jpg b/boards/panasonic/pan1770_evb/doc/pan1770_evaluation_board.jpg similarity index 100% rename from boards/arm/pan1770_evb/doc/pan1770_evaluation_board.jpg rename to boards/panasonic/pan1770_evb/doc/pan1770_evaluation_board.jpg diff --git a/boards/arm/pan1770_evb/pan1770_evb-pinctrl.dtsi b/boards/panasonic/pan1770_evb/pan1770_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1770_evb/pan1770_evb-pinctrl.dtsi rename to boards/panasonic/pan1770_evb/pan1770_evb-pinctrl.dtsi diff --git a/boards/arm/pan1770_evb/pan1770_evb.dts b/boards/panasonic/pan1770_evb/pan1770_evb.dts similarity index 100% rename from boards/arm/pan1770_evb/pan1770_evb.dts rename to boards/panasonic/pan1770_evb/pan1770_evb.dts diff --git a/boards/arm/pan1770_evb/pan1770_evb.yaml b/boards/panasonic/pan1770_evb/pan1770_evb.yaml similarity index 100% rename from boards/arm/pan1770_evb/pan1770_evb.yaml rename to boards/panasonic/pan1770_evb/pan1770_evb.yaml diff --git a/boards/arm/pan1770_evb/pan1770_evb_defconfig b/boards/panasonic/pan1770_evb/pan1770_evb_defconfig similarity index 82% rename from boards/arm/pan1770_evb/pan1770_evb_defconfig rename to boards/panasonic/pan1770_evb/pan1770_evb_defconfig index 7fbc9b87408..5d2537faace 100644 --- a/boards/arm/pan1770_evb/pan1770_evb_defconfig +++ b/boards/panasonic/pan1770_evb/pan1770_evb_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PAN1770_EVB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52_vbluno52/pre_dt_board.cmake b/boards/panasonic/pan1770_evb/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52_vbluno52/pre_dt_board.cmake rename to boards/panasonic/pan1770_evb/pre_dt_board.cmake diff --git a/boards/arm/pan1780_evb/Kconfig b/boards/panasonic/pan1780_evb/Kconfig similarity index 100% rename from boards/arm/pan1780_evb/Kconfig rename to boards/panasonic/pan1780_evb/Kconfig diff --git a/boards/panasonic/pan1780_evb/Kconfig.defconfig b/boards/panasonic/pan1780_evb/Kconfig.defconfig new file mode 100644 index 00000000000..81bb7a60819 --- /dev/null +++ b/boards/panasonic/pan1780_evb/Kconfig.defconfig @@ -0,0 +1,11 @@ +# PAN1780 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PAN1780_EVB + +config BT_CTLR + default BT + +endif # BOARD_PAN1780_EVB diff --git a/boards/panasonic/pan1780_evb/Kconfig.pan1780_evb b/boards/panasonic/pan1780_evb/Kconfig.pan1780_evb new file mode 100644 index 00000000000..079b30fac68 --- /dev/null +++ b/boards/panasonic/pan1780_evb/Kconfig.pan1780_evb @@ -0,0 +1,7 @@ +# PAN1780 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1780_EVB + select SOC_NRF52840_QIAA diff --git a/boards/arm/pan1780_evb/board.cmake b/boards/panasonic/pan1780_evb/board.cmake similarity index 100% rename from boards/arm/pan1780_evb/board.cmake rename to boards/panasonic/pan1780_evb/board.cmake diff --git a/boards/panasonic/pan1780_evb/board.yml b/boards/panasonic/pan1780_evb/board.yml new file mode 100644 index 00000000000..53a9a68192a --- /dev/null +++ b/boards/panasonic/pan1780_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: pan1780_evb + vendor: panasonic + socs: + - name: nrf52840 diff --git a/boards/arm/pan1780_evb/doc/index.rst b/boards/panasonic/pan1780_evb/doc/index.rst similarity index 100% rename from boards/arm/pan1780_evb/doc/index.rst rename to boards/panasonic/pan1780_evb/doc/index.rst diff --git a/boards/arm/pan1780_evb/doc/pan1780_evaluation_board.jpg b/boards/panasonic/pan1780_evb/doc/pan1780_evaluation_board.jpg similarity index 100% rename from boards/arm/pan1780_evb/doc/pan1780_evaluation_board.jpg rename to boards/panasonic/pan1780_evb/doc/pan1780_evaluation_board.jpg diff --git a/boards/arm/pan1780_evb/pan1780_evb-pinctrl.dtsi b/boards/panasonic/pan1780_evb/pan1780_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1780_evb/pan1780_evb-pinctrl.dtsi rename to boards/panasonic/pan1780_evb/pan1780_evb-pinctrl.dtsi diff --git a/boards/arm/pan1780_evb/pan1780_evb.dts b/boards/panasonic/pan1780_evb/pan1780_evb.dts similarity index 100% rename from boards/arm/pan1780_evb/pan1780_evb.dts rename to boards/panasonic/pan1780_evb/pan1780_evb.dts diff --git a/boards/arm/pan1780_evb/pan1780_evb.yaml b/boards/panasonic/pan1780_evb/pan1780_evb.yaml similarity index 100% rename from boards/arm/pan1780_evb/pan1780_evb.yaml rename to boards/panasonic/pan1780_evb/pan1780_evb.yaml diff --git a/boards/arm/pan1780_evb/pan1780_evb_defconfig b/boards/panasonic/pan1780_evb/pan1780_evb_defconfig similarity index 82% rename from boards/arm/pan1780_evb/pan1780_evb_defconfig rename to boards/panasonic/pan1780_evb/pan1780_evb_defconfig index 1bb9d720f52..16b6ca3b450 100644 --- a/boards/arm/pan1780_evb/pan1780_evb_defconfig +++ b/boards/panasonic/pan1780_evb/pan1780_evb_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PAN1780_EVB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52dk_nrf52805/pre_dt_board.cmake b/boards/panasonic/pan1780_evb/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52dk_nrf52805/pre_dt_board.cmake rename to boards/panasonic/pan1780_evb/pre_dt_board.cmake diff --git a/boards/arm/pan1781_evb/Kconfig b/boards/panasonic/pan1781_evb/Kconfig similarity index 100% rename from boards/arm/pan1781_evb/Kconfig rename to boards/panasonic/pan1781_evb/Kconfig diff --git a/boards/panasonic/pan1781_evb/Kconfig.defconfig b/boards/panasonic/pan1781_evb/Kconfig.defconfig new file mode 100644 index 00000000000..518676e3643 --- /dev/null +++ b/boards/panasonic/pan1781_evb/Kconfig.defconfig @@ -0,0 +1,11 @@ +# PAN1781 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PAN1781_EVB + +config BT_CTLR + default BT + +endif # BOARD_PAN1781_EVB diff --git a/boards/panasonic/pan1781_evb/Kconfig.pan1781_evb b/boards/panasonic/pan1781_evb/Kconfig.pan1781_evb new file mode 100644 index 00000000000..e7253895d08 --- /dev/null +++ b/boards/panasonic/pan1781_evb/Kconfig.pan1781_evb @@ -0,0 +1,7 @@ +# PAN1781 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1781_EVB + select SOC_NRF52820_QDAA diff --git a/boards/arm/pan1781_evb/board.cmake b/boards/panasonic/pan1781_evb/board.cmake similarity index 100% rename from boards/arm/pan1781_evb/board.cmake rename to boards/panasonic/pan1781_evb/board.cmake diff --git a/boards/panasonic/pan1781_evb/board.yml b/boards/panasonic/pan1781_evb/board.yml new file mode 100644 index 00000000000..64a5a239961 --- /dev/null +++ b/boards/panasonic/pan1781_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: pan1781_evb + vendor: panasonic + socs: + - name: nrf52820 diff --git a/boards/arm/pan1781_evb/doc/index.rst b/boards/panasonic/pan1781_evb/doc/index.rst similarity index 100% rename from boards/arm/pan1781_evb/doc/index.rst rename to boards/panasonic/pan1781_evb/doc/index.rst diff --git a/boards/arm/pan1781_evb/doc/pan1781_evaluation_board.jpg b/boards/panasonic/pan1781_evb/doc/pan1781_evaluation_board.jpg similarity index 100% rename from boards/arm/pan1781_evb/doc/pan1781_evaluation_board.jpg rename to boards/panasonic/pan1781_evb/doc/pan1781_evaluation_board.jpg diff --git a/boards/arm/pan1781_evb/pan1781_evb-pinctrl.dtsi b/boards/panasonic/pan1781_evb/pan1781_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1781_evb/pan1781_evb-pinctrl.dtsi rename to boards/panasonic/pan1781_evb/pan1781_evb-pinctrl.dtsi diff --git a/boards/arm/pan1781_evb/pan1781_evb.dts b/boards/panasonic/pan1781_evb/pan1781_evb.dts similarity index 100% rename from boards/arm/pan1781_evb/pan1781_evb.dts rename to boards/panasonic/pan1781_evb/pan1781_evb.dts diff --git a/boards/arm/pan1781_evb/pan1781_evb.yaml b/boards/panasonic/pan1781_evb/pan1781_evb.yaml similarity index 100% rename from boards/arm/pan1781_evb/pan1781_evb.yaml rename to boards/panasonic/pan1781_evb/pan1781_evb.yaml diff --git a/boards/arm/pan1781_evb/pan1781_evb_defconfig b/boards/panasonic/pan1781_evb/pan1781_evb_defconfig similarity index 82% rename from boards/arm/pan1781_evb/pan1781_evb_defconfig rename to boards/panasonic/pan1781_evb/pan1781_evb_defconfig index 90e88bd4e1c..444314839f6 100644 --- a/boards/arm/pan1781_evb/pan1781_evb_defconfig +++ b/boards/panasonic/pan1781_evb/pan1781_evb_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52820_QDAA=y -CONFIG_BOARD_PAN1781_EVB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/pan1782_evb/Kconfig b/boards/panasonic/pan1782_evb/Kconfig similarity index 100% rename from boards/arm/pan1782_evb/Kconfig rename to boards/panasonic/pan1782_evb/Kconfig diff --git a/boards/panasonic/pan1782_evb/Kconfig.defconfig b/boards/panasonic/pan1782_evb/Kconfig.defconfig new file mode 100644 index 00000000000..c9136006be4 --- /dev/null +++ b/boards/panasonic/pan1782_evb/Kconfig.defconfig @@ -0,0 +1,11 @@ +# PAN1782 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PAN1782_EVB + +config BT_CTLR + default BT + +endif # BOARD_PAN1782_EVB diff --git a/boards/panasonic/pan1782_evb/Kconfig.pan1782_evb b/boards/panasonic/pan1782_evb/Kconfig.pan1782_evb new file mode 100644 index 00000000000..d0a403f0380 --- /dev/null +++ b/boards/panasonic/pan1782_evb/Kconfig.pan1782_evb @@ -0,0 +1,7 @@ +# PAN1782 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1782_EVB + select SOC_NRF52833_QIAA diff --git a/boards/arm/pan1782_evb/board.cmake b/boards/panasonic/pan1782_evb/board.cmake similarity index 100% rename from boards/arm/pan1782_evb/board.cmake rename to boards/panasonic/pan1782_evb/board.cmake diff --git a/boards/panasonic/pan1782_evb/board.yml b/boards/panasonic/pan1782_evb/board.yml new file mode 100644 index 00000000000..649e5507d82 --- /dev/null +++ b/boards/panasonic/pan1782_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: pan1782_evb + vendor: panasonic + socs: + - name: nrf52833 diff --git a/boards/arm/pan1782_evb/doc/index.rst b/boards/panasonic/pan1782_evb/doc/index.rst similarity index 100% rename from boards/arm/pan1782_evb/doc/index.rst rename to boards/panasonic/pan1782_evb/doc/index.rst diff --git a/boards/arm/pan1782_evb/doc/pan1782_evaluation_board.jpg b/boards/panasonic/pan1782_evb/doc/pan1782_evaluation_board.jpg similarity index 100% rename from boards/arm/pan1782_evb/doc/pan1782_evaluation_board.jpg rename to boards/panasonic/pan1782_evb/doc/pan1782_evaluation_board.jpg diff --git a/boards/arm/pan1782_evb/pan1782_evb-pinctrl.dtsi b/boards/panasonic/pan1782_evb/pan1782_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1782_evb/pan1782_evb-pinctrl.dtsi rename to boards/panasonic/pan1782_evb/pan1782_evb-pinctrl.dtsi diff --git a/boards/arm/pan1782_evb/pan1782_evb.dts b/boards/panasonic/pan1782_evb/pan1782_evb.dts similarity index 100% rename from boards/arm/pan1782_evb/pan1782_evb.dts rename to boards/panasonic/pan1782_evb/pan1782_evb.dts diff --git a/boards/arm/pan1782_evb/pan1782_evb.yaml b/boards/panasonic/pan1782_evb/pan1782_evb.yaml similarity index 100% rename from boards/arm/pan1782_evb/pan1782_evb.yaml rename to boards/panasonic/pan1782_evb/pan1782_evb.yaml diff --git a/boards/arm/pan1782_evb/pan1782_evb_defconfig b/boards/panasonic/pan1782_evb/pan1782_evb_defconfig similarity index 84% rename from boards/arm/pan1782_evb/pan1782_evb_defconfig rename to boards/panasonic/pan1782_evb/pan1782_evb_defconfig index 98904968416..af565be5cb1 100644 --- a/boards/arm/pan1782_evb/pan1782_evb_defconfig +++ b/boards/panasonic/pan1782_evb/pan1782_evb_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_PAN1782_EVB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/panasonic/pan1783/CMakeLists.txt b/boards/panasonic/pan1783/CMakeLists.txt new file mode 100644 index 00000000000..88360ce24f7 --- /dev/null +++ b/boards/panasonic/pan1783/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF5340_CPUAPP_QKAA AND CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(pan1783_nrf5340_cpunet_reset.c) +endif() diff --git a/boards/panasonic/pan1783/Kconfig b/boards/panasonic/pan1783/Kconfig new file mode 100644 index 00000000000..671d17acad9 --- /dev/null +++ b/boards/panasonic/pan1783/Kconfig @@ -0,0 +1,56 @@ +# PAN1783 EVB board configuration + +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF5340_CPUAPP_QKAA + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "pan1783_evb/nrf5340/cpunet" if BOARD_PAN1783_EVB_NRF5340_CPUAPP + default "pan1783a_evb/nrf5340/cpunet" if BOARD_PAN1783A_EVB_NRF5340_CPUAPP + default "pan1783a_pa_evb/nrf5340/cpunet" if BOARD_PAN1783A_PA_EVB_NRF5340_CPUAPP + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # SOC_NRF5340_CPUAPP_QKAA + +config DOMAIN_CPUAPP_BOARD + string + default "pan1783_evb/nrf5340/cpuapp" if BOARD_PAN1783_EVB_NRF5340_CPUNET + default "pan1783a_evb/nrf5340/cpuapp" if BOARD_PAN1783A_EVB_NRF5340_CPUNET + default "pan1783a_pa_evb/nrf5340/cpuapp" if BOARD_PAN1783A_PA_EVB_NRF5340_CPUNET + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. diff --git a/boards/panasonic/pan1783/Kconfig.defconfig b/boards/panasonic/pan1783/Kconfig.defconfig new file mode 100644 index 00000000000..ec08e860bbd --- /dev/null +++ b/boards/panasonic/pan1783/Kconfig.defconfig @@ -0,0 +1,26 @@ +# PAN1783 EVB board configuration + +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config MBOX_NRFX_IPC + default MBOX + +if SOC_NRF5340_CPUAPP_QKAA + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +endif # SOC_NRF5340_CPUAPP_QKAA + +if SOC_NRF5340_CPUNET_QKAA + +config BT_CTLR + default y if BT + +endif # SOC_NRF5340_CPUNET_QKAA diff --git a/boards/panasonic/pan1783/Kconfig.pan1783_evb b/boards/panasonic/pan1783/Kconfig.pan1783_evb new file mode 100644 index 00000000000..7476162e39a --- /dev/null +++ b/boards/panasonic/pan1783/Kconfig.pan1783_evb @@ -0,0 +1,8 @@ +# PAN1783 EVB board configuration + +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1783_EVB + select SOC_NRF5340_CPUAPP_QKAA if BOARD_PAN1783_EVB_NRF5340_CPUAPP + select SOC_NRF5340_CPUNET_QKAA if BOARD_PAN1783_EVB_NRF5340_CPUNET diff --git a/boards/panasonic/pan1783/Kconfig.pan1783a_evb b/boards/panasonic/pan1783/Kconfig.pan1783a_evb new file mode 100644 index 00000000000..f7b2b005a69 --- /dev/null +++ b/boards/panasonic/pan1783/Kconfig.pan1783a_evb @@ -0,0 +1,8 @@ +# PAN1783 EVB board configuration + +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1783A_EVB + select SOC_NRF5340_CPUAPP_QKAA if BOARD_PAN1783A_EVB_NRF5340_CPUAPP + select SOC_NRF5340_CPUNET_QKAA if BOARD_PAN1783A_EVB_NRF5340_CPUNET diff --git a/boards/panasonic/pan1783/Kconfig.pan1783a_pa_evb b/boards/panasonic/pan1783/Kconfig.pan1783a_pa_evb new file mode 100644 index 00000000000..46a47ca0f67 --- /dev/null +++ b/boards/panasonic/pan1783/Kconfig.pan1783a_pa_evb @@ -0,0 +1,8 @@ +# PAN1783 EVB board configuration + +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1783A_PA_EVB + select SOC_NRF5340_CPUAPP_QKAA if BOARD_PAN1783A_PA_EVB_NRF5340_CPUAPP + select SOC_NRF5340_CPUNET_QKAA if BOARD_PAN1783A_PA_EVB_NRF5340_CPUNET diff --git a/boards/panasonic/pan1783/board.cmake b/boards/panasonic/pan1783/board.cmake new file mode 100644 index 00000000000..1a211bc95c9 --- /dev/null +++ b/boards/panasonic/pan1783/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF5340_CPUAPP_QKAA) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +endif() + +if(CONFIG_SOC_NRF5340_CPUNET_QKAA) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/panasonic/pan1783/board.yml b/boards/panasonic/pan1783/board.yml new file mode 100644 index 00000000000..461763d86f2 --- /dev/null +++ b/boards/panasonic/pan1783/board.yml @@ -0,0 +1,13 @@ +boards: +- name: pan1783_evb + vendor: panasonic + socs: + - name: nrf5340 +- name: pan1783a_evb + vendor: panasonic + socs: + - name: nrf5340 +- name: pan1783a_pa_evb + vendor: panasonic + socs: + - name: nrf5340 diff --git a/boards/arm/pan1783/doc/img/pan1783_evb.webp b/boards/panasonic/pan1783/doc/img/pan1783_evb.webp similarity index 100% rename from boards/arm/pan1783/doc/img/pan1783_evb.webp rename to boards/panasonic/pan1783/doc/img/pan1783_evb.webp diff --git a/boards/arm/pan1783/doc/index.rst b/boards/panasonic/pan1783/doc/index.rst similarity index 100% rename from boards/arm/pan1783/doc/index.rst rename to boards/panasonic/pan1783/doc/index.rst diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.dts b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.dts new file mode 100644 index 00000000000..27bfbbc52e9 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.dts @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Panasonic PAN1783 EVB (NRF5340) Application"; + compatible = "panasonic,pan1783-evb-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + }; +}; diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000..401745b3333 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml @@ -0,0 +1,21 @@ +identifier: pan1783_evb/nrf5340/cpuapp +name: PAN1783-EVB-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 448 +flash: 1024 +supported: + - gpio + - i2c + - i2s + - pwm + - watchdog + - usb_cdc + - usb_device + - netif:openthread + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp_defconfig b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000..f158f01995f --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp_defconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts new file mode 100644 index 00000000000..28feb6d660f --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpunet_common.dtsi" + +/ { + model = "Panasonic PAN1783 EVB (NRF5340) Network"; + compatible = "panasonic,pan1783-evb-cpunet"; + + chosen { + zephyr,sram = &sram1; + zephyr,flash = &flash1; + zephyr,code-partition = &slot0_partition; + }; +}; + +/* Include shared RAM configuration file */ +#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml new file mode 100644 index 00000000000..510ceef5691 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml @@ -0,0 +1,14 @@ +identifier: pan1783_evb/nrf5340/cpunet +name: PAN1783-EVB-network-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - watchdog + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet_defconfig b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..71784075dfd --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783_cpuapp_common-pinctrl.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1783/pan1783_cpuapp_common-pinctrl.dtsi rename to boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi new file mode 100644 index 00000000000..fae7f566fcc --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "pan1783_nrf5340_cpuapp_common-pinctrl.dtsi" +#include + +/ { + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,bt-hci-ipc = &ipc0; + nordic,802154-spinel-ipc = &ipc0; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + evb_led1: evb_led_1 { + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + label = "LED1 on EVB"; + }; + evb_led2: evb_led_2 { + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + label = "LED2 on EVB"; + }; + evb_led3: evb_led_3 { + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + label = "LED3 on EVB"; + }; + evb_led4: evb_led_4 { + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + label = "LED4 on EVB"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_evb_led1: pwm_evb_led_1 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + buttons { + compatible = "gpio-keys"; + evb_sw1: evb_sw_1 { + gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW1 on EVB"; + zephyr,code = ; + }; + evb_sw2: evb_sw_2 { + gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2 on EVB"; + zephyr,code = ; + }; + evb_sw3: evb_sw_3 { + gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW3 on EVB"; + zephyr,code = ; + }; + evb_sw4: evb_sw_4 { + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW4 on EVB"; + zephyr,code = ; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* AN */ + /* Not a GPIO*/ /* RST */ + <2 0 &gpio1 12 0>, /* CS */ + <3 0 &gpio1 15 0>, /* SCK */ + <4 0 &gpio1 14 0>, /* MISO */ + <5 0 &gpio1 13 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpio1 7 0>, /* PWM */ + <7 0 &gpio1 4 0>, /* INT */ + <8 0 &gpio1 0 0>, /* RX */ + <9 0 &gpio1 1 0>, /* TX */ + <10 0 &gpio1 3 0>, /* SCL */ + <11 0 &gpio1 2 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* A0 */ + <1 0 &gpio0 5 0>, /* A1 */ + <2 0 &gpio0 6 0>, /* A2 */ + <3 0 &gpio0 7 0>, /* A3 */ + <4 0 &gpio0 25 0>, /* A4 */ + <5 0 &gpio0 26 0>, /* A5 */ + <6 0 &gpio1 0 0>, /* D0 */ + <7 0 &gpio1 1 0>, /* D1 */ + <8 0 &gpio1 4 0>, /* D2 */ + <9 0 &gpio1 5 0>, /* D3 */ + <10 0 &gpio1 6 0>, /* D4 */ + <11 0 &gpio1 7 0>, /* D5 */ + <12 0 &gpio1 8 0>, /* D6 */ + <13 0 &gpio1 9 0>, /* D7 */ + <14 0 &gpio1 10 0>, /* D8 */ + <15 0 &gpio1 11 0>, /* D9 */ + <16 0 &gpio1 12 0>, /* D10 */ + <17 0 &gpio1 13 0>, /* D11 */ + <18 0 &gpio1 14 0>, /* D12 */ + <19 0 &gpio1 15 0>, /* D13 */ + <20 0 &gpio1 2 0>, /* D14 */ + <21 0 &gpio1 3 0>; /* D15 */ + }; + + arduino_adc: analog-connector { + compatible = "arduino,uno-adc"; + #io-channel-cells = <1>; + io-channel-map = <0 &adc 0>, /* A0 = P0.4 = AIN0 */ + <1 &adc 1>, /* A1 = P0.5 = AIN1 */ + <2 &adc 2>, /* A2 = P0.6 = AIN2 */ + <3 &adc 3>, /* A3 = P0.7 = AIN3 */ + <4 &adc 4>, /* A4 = P0.25 = AIN4 */ + <5 &adc 5>; /* A5 = P0.26 = AIN5 */ + }; + + gpio_fwd: nrf-gpio-forwarder { + compatible = "nordic,nrf-gpio-forwarder"; + status = "disabled"; + uart { + gpios = <&gpio0 20 0>, <&gpio0 22 0>, <&gpio0 11 0>, <&gpio0 10 0>; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &evb_led1; + led1 = &evb_led2; + led2 = &evb_led3; + led3 = &evb_led4; + pwm-led0 = &pwm_evb_led1; + sw0 = &evb_sw1; + sw1 = &evb_sw2; + sw2 = &evb_sw3; + sw3 = &evb_sw4; + bootloader-led0 = &evb_led1; + mcuboot-button0 = &evb_sw1; + mcuboot-led0 = &evb_led1; + watchdog0 = &wdt0; + spi-flash0 = &mx25r64; + }; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c1 { + compatible = "nordic,nrf-twim"; + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&qspi { + status = "okay"; + pinctrl-0 = <&qspi_default>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; + mx25r64: mx25r6435f@0 { + compatible = "nordic,qspi-nor"; + reg = <0>; + /* MX25R64 supports only pp and pp4io */ + writeoc = "pp4io"; + /* MX25R64 supports all readoc options */ + readoc = "read4io"; + sck-frequency = <8000000>; + jedec-id = [ c2 28 17 ]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + }; +}; + +arduino_serial: &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_i2c: &i2c1 {}; + +arduino_spi: &spi4 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + pinctrl-0 = <&spi4_default>; + pinctrl-1 = <&spi4_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + }; + slot1_partition: partition@80000 { + label = "image-1"; + }; + /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ + storage_partition: partition@f8000 { + label = "storage"; + reg = <0x000f8000 0x00008000>; + }; + }; +}; + +&ieee802154 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; + +/ { + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_image: image@20000000 { + /* Zephyr image(s) memory */ + }; + + sram0_s: image_s@20000000 { + /* Secure image memory */ + }; + }; +}; + +/* Include partition configuration file */ +#include "pan1783_nrf5340_cpuapp_partition_conf.dtsi" diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_partition_conf.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_partition_conf.dtsi new file mode 100644 index 00000000000..a6edad09bba --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_partition_conf.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Default Flash planning for pan1783_evb CPUAPP (Application MCU). + * + * Secure image will be placed, by default, in flash0 + * (or in slot0, if MCUboot is present). + * Secure image will use sram0 for system memory. + * + */ + +&slot0_partition { + reg = <0x00010000 0x40000>; +}; + +&slot1_partition { + reg = <0x00080000 0x40000>; +}; + +/* Default SRAM planning when building for nRF5340 + * - Lowest 448 kB SRAM allocated to Secure image (sram0_s) + * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) + * (see shared_sram_planning_conf.dtsi) + */ +&sram0_image { + reg = <0x20000000 DT_SIZE_K(448)>; +}; + +&sram0_s { + reg = <0x20000000 0x70000>; +}; + +/* Include shared RAM configuration file */ +#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783_cpunet-pinctrl.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1783/pan1783_cpunet-pinctrl.dtsi rename to boards/panasonic/pan1783/pan1783_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi new file mode 100644 index 00000000000..a23b1d87b10 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "pan1783_nrf5340_cpunet-pinctrl.dtsi" +#include + +/ { + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,bt-hci-ipc = &ipc0; + nordic,802154-spinel-ipc = &ipc0; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + evb_led1: evb_led_1 { + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + label = "LED1 on EVB"; + }; + evb_led2: evb_led_2 { + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + label = "LED2 on EVB"; + }; + evb_led3: evb_led_3 { + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + label = "LED3 on EVB"; + }; + evb_led4: evb_led_4 { + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + label = "LED4 on EVB"; + }; + }; + + buttons { + compatible = "gpio-keys"; + evb_sw1: evb_sw_1 { + gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW1 on EVB"; + zephyr,code = ; + }; + evb_sw2: evb_sw_2 { + gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2 on EVB"; + zephyr,code = ; + }; + evb_sw3: evb_sw_3 { + gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW3 on EVB"; + zephyr,code = ; + }; + evb_sw4: evb_sw_4 { + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW4 on EVB"; + zephyr,code = ; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* AN */ + /* Not a GPIO*/ /* RST */ + <2 0 &gpio1 12 0>, /* CS */ + <3 0 &gpio1 15 0>, /* SCK */ + <4 0 &gpio1 14 0>, /* MISO */ + <5 0 &gpio1 13 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpio1 7 0>, /* PWM */ + <7 0 &gpio1 4 0>, /* INT */ + <8 0 &gpio1 0 0>, /* RX */ + <9 0 &gpio1 1 0>, /* TX */ + <10 0 &gpio1 3 0>, /* SCL */ + <11 0 &gpio1 2 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* A0 */ + <1 0 &gpio0 5 0>, /* A1 */ + <2 0 &gpio0 6 0>, /* A2 */ + <3 0 &gpio0 7 0>, /* A3 */ + <4 0 &gpio0 25 0>, /* A4 */ + <5 0 &gpio0 26 0>, /* A5 */ + <6 0 &gpio1 0 0>, /* D0 */ + <7 0 &gpio1 1 0>, /* D1 */ + <8 0 &gpio1 4 0>, /* D2 */ + <9 0 &gpio1 5 0>, /* D3 */ + <10 0 &gpio1 6 0>, /* D4 */ + <11 0 &gpio1 7 0>, /* D5 */ + <12 0 &gpio1 8 0>, /* D6 */ + <13 0 &gpio1 9 0>, /* D7 */ + <14 0 &gpio1 10 0>, /* D8 */ + <15 0 &gpio1 11 0>, /* D9 */ + <16 0 &gpio1 12 0>, /* D10 */ + <17 0 &gpio1 13 0>, /* D11 */ + <18 0 &gpio1 14 0>, /* D12 */ + <19 0 &gpio1 15 0>, /* D13 */ + <20 0 &gpio1 2 0>, /* D14 */ + <21 0 &gpio1 3 0>; /* D15 */ + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &evb_led1; + led1 = &evb_led2; + led2 = &evb_led3; + led3 = &evb_led4; + sw0 = &evb_sw1; + sw1 = &evb_sw2; + sw2 = &evb_sw3; + sw3 = &evb_sw4; + bootloader-led0 = &evb_led1; + mcuboot-button0 = &evb_sw1; + mcuboot-led0 = &evb_led1; + watchdog0 = &wdt0; + }; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&uart0 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_serial: &uart0 {}; + +arduino_i2c: &i2c0 { + compatible = "nordic,nrf-twim"; + /* Cannot be used together with uart0. */ + /* status = "okay"; */ + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_spi: &spi0 { + compatible = "nordic,nrf-spim"; + /* Cannot be used together with uart0. */ + /* status = "okay"; */ + cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash1 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0xc000>; + }; + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000C000 0x17000>; + }; + slot1_partition: partition@23000 { + label = "image-1"; + reg = <0x00023000 0x17000>; + }; + storage_partition: partition@3a000 { + label = "storage"; + reg = <0x0003a000 0x6000>; + }; + }; +}; + +&ieee802154 { + status = "okay"; +}; + +/* Include shared RAM configuration file */ +#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c new file mode 100644 index 00000000000..bf0626ce30b --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include +#include + +#if defined(CONFIG_BOARD_PAN1783_EVB_NRF5340_CPUAPP) +LOG_MODULE_REGISTER(pan1783_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); +#elif defined(CONFIG_BOARD_PAN1783A_EVB_NRF5340_CPUAPP) +LOG_MODULE_REGISTER(pan1783a_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); +#elif defined(CONFIG_BOARD_PAN1783A_PA_EVB_NRF5340_CPUAPP) +LOG_MODULE_REGISTER(pan1783a_pa_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); +#else +#error "No board selected!" +#endif + +#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) +#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> +#else +#define DEBUG_SETUP() +#endif + +static void remoteproc_mgr_config(void) +{ + /* Route Bluetooth Controller Debug Pins */ + DEBUG_SETUP(); + + /* Retain nRF5340 Network MCU */ + NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; +} + +static int remoteproc_mgr_boot(void) +{ + /* Configure permissions for the Network MCU. */ + remoteproc_mgr_config(); + + /* Release the Network MCU, 'Release force off signal' */ + nrf_reset_network_force_off(NRF_RESET, false); + + LOG_DBG("Network MCU released."); + + return 0; +} + +SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/arm/pan1783/pan1783_shared_sram_planning_conf.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_shared_sram_planning_conf.dtsi similarity index 100% rename from boards/arm/pan1783/pan1783_shared_sram_planning_conf.dtsi rename to boards/panasonic/pan1783/pan1783_nrf5340_shared_sram_planning_conf.dtsi diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.dts b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.dts new file mode 100644 index 00000000000..b47b14510fe --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.dts @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Panasonic PAN1783A EVB (NRF5340) Application"; + compatible = "panasonic,pan1783a-evb-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + }; +}; diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000..f5a789788bf --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml @@ -0,0 +1,21 @@ +identifier: pan1783a_evb/nrf5340/cpuapp +name: PAN1783A-EVB-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 448 +flash: 1024 +supported: + - gpio + - i2c + - i2s + - pwm + - watchdog + - usb_cdc + - usb_device + - netif:openthread + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp_defconfig b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000..f158f01995f --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp_defconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts new file mode 100644 index 00000000000..44d61d69c25 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpunet_common.dtsi" + +/ { + model = "Panasonic PAN1783A EVB (NRF5340) Network"; + compatible = "panasonic,pan1783a-evb-cpunet"; + + chosen { + zephyr,sram = &sram1; + zephyr,flash = &flash1; + zephyr,code-partition = &slot0_partition; + }; +}; + +/* Include shared RAM configuration file */ +#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.yaml b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.yaml new file mode 100644 index 00000000000..4904371041c --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.yaml @@ -0,0 +1,14 @@ +identifier: pan1783a_evb/nrf5340/cpunet +name: PAN1783A-EVB-network-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - watchdog + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet_defconfig b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..71784075dfd --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.dts b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.dts new file mode 100644 index 00000000000..1bddfdb9862 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Panasonic PAN1783A-PA EVB (NRF5340) Application"; + compatible = "panasonic,pan1783a_pa-evb-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + }; +}; + +&gpio_fwd { + /delete-node/ uart; + + status = "okay"; + fem { + gpios = <&gpio0 19 0>, <&gpio0 21 0>; + }; +}; diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000..dc5600a999a --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml @@ -0,0 +1,21 @@ +identifier: pan1783a_pa_evb/nrf5340/cpuapp +name: PAN1783A-PA-EVB-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 448 +flash: 1024 +supported: + - gpio + - i2c + - i2s + - pwm + - watchdog + - usb_cdc + - usb_device + - netif:openthread + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp_defconfig b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000..f158f01995f --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp_defconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts new file mode 100644 index 00000000000..4856deaa3a1 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpunet_common.dtsi" + +/ { + model = "Panasonic PAN1783A-PA EVB (NRF5340) Network"; + compatible = "panasonic,pan1783a_pa-evb-cpunet"; + + chosen { + zephyr,sram = &sram1; + zephyr,flash = &flash1; + zephyr,code-partition = &slot0_partition; + }; + + nrf_radio_fem: fem_node { + compatible = "skyworks,sky66407-11", "generic-fem-two-ctrl-pins"; + ctx-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + crx-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; +}; + +&radio { + fem = <&nrf_radio_fem>; +}; + +/* Include shared RAM configuration file */ +#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml new file mode 100644 index 00000000000..14ff8c16914 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml @@ -0,0 +1,14 @@ +identifier: pan1783a_pa_evb/nrf5340/cpunet +name: PAN1783A-PA-EVB-network-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - watchdog + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet_defconfig b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..71784075dfd --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pre_dt_board.cmake b/boards/panasonic/pan1783/pre_dt_board.cmake similarity index 100% rename from boards/arm/pan1783/pre_dt_board.cmake rename to boards/panasonic/pan1783/pre_dt_board.cmake diff --git a/boards/arm/particle_argon/CMakeLists.txt b/boards/particle/argon/CMakeLists.txt similarity index 100% rename from boards/arm/particle_argon/CMakeLists.txt rename to boards/particle/argon/CMakeLists.txt diff --git a/boards/arm/particle_argon/Kconfig b/boards/particle/argon/Kconfig similarity index 100% rename from boards/arm/particle_argon/Kconfig rename to boards/particle/argon/Kconfig diff --git a/boards/particle/argon/Kconfig.defconfig b/boards/particle/argon/Kconfig.defconfig new file mode 100644 index 00000000000..72954154c71 --- /dev/null +++ b/boards/particle/argon/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Particle Argon board configuration + +# Copyright (c) 2018 Matthias Boesl +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PARTICLE_ARGON + +config BT_CTLR + default BT + +endif # BOARD_PARTICLE_ARGON diff --git a/boards/particle/argon/Kconfig.particle_argon b/boards/particle/argon/Kconfig.particle_argon new file mode 100644 index 00000000000..3a056b673b6 --- /dev/null +++ b/boards/particle/argon/Kconfig.particle_argon @@ -0,0 +1,7 @@ +# Particle Argon configuration + +# Copyright (c) 2018 Matthias Boesl +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PARTICLE_ARGON + select SOC_NRF52840_QIAA diff --git a/boards/arm/particle_argon/board.c b/boards/particle/argon/board.c similarity index 100% rename from boards/arm/particle_argon/board.c rename to boards/particle/argon/board.c diff --git a/boards/arm/particle_argon/board.cmake b/boards/particle/argon/board.cmake similarity index 100% rename from boards/arm/particle_argon/board.cmake rename to boards/particle/argon/board.cmake diff --git a/boards/particle/argon/board.yml b/boards/particle/argon/board.yml new file mode 100644 index 00000000000..08eadfda743 --- /dev/null +++ b/boards/particle/argon/board.yml @@ -0,0 +1,5 @@ +board: + name: particle_argon + vendor: particle + socs: + - name: nrf52840 diff --git a/boards/arm/particle_argon/doc/img/particle_argon.jpg b/boards/particle/argon/doc/img/particle_argon.jpg similarity index 100% rename from boards/arm/particle_argon/doc/img/particle_argon.jpg rename to boards/particle/argon/doc/img/particle_argon.jpg diff --git a/boards/arm/particle_argon/doc/index.rst b/boards/particle/argon/doc/index.rst similarity index 100% rename from boards/arm/particle_argon/doc/index.rst rename to boards/particle/argon/doc/index.rst diff --git a/boards/arm/particle_argon/dts/mesh_feather-pinctrl.dtsi b/boards/particle/argon/dts/mesh_feather-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather-pinctrl.dtsi rename to boards/particle/argon/dts/mesh_feather-pinctrl.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather.dtsi b/boards/particle/argon/dts/mesh_feather.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather.dtsi rename to boards/particle/argon/dts/mesh_feather.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather_i2c1_twi1.dtsi b/boards/particle/argon/dts/mesh_feather_i2c1_twi1.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather_i2c1_twi1.dtsi rename to boards/particle/argon/dts/mesh_feather_i2c1_twi1.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather_spi1_spi3.dtsi b/boards/particle/argon/dts/mesh_feather_spi1_spi3.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather_spi1_spi3.dtsi rename to boards/particle/argon/dts/mesh_feather_spi1_spi3.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather_spi_spi1.dtsi b/boards/particle/argon/dts/mesh_feather_spi_spi1.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather_spi_spi1.dtsi rename to boards/particle/argon/dts/mesh_feather_spi_spi1.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather_spi_spi3.dtsi b/boards/particle/argon/dts/mesh_feather_spi_spi3.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather_spi_spi3.dtsi rename to boards/particle/argon/dts/mesh_feather_spi_spi3.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather_uart1_rtscts.dtsi b/boards/particle/argon/dts/mesh_feather_uart1_rtscts.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather_uart1_rtscts.dtsi rename to boards/particle/argon/dts/mesh_feather_uart1_rtscts.dtsi diff --git a/boards/arm/particle_argon/particle_argon-pinctrl.dtsi b/boards/particle/argon/particle_argon-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_argon/particle_argon-pinctrl.dtsi rename to boards/particle/argon/particle_argon-pinctrl.dtsi diff --git a/boards/arm/particle_argon/particle_argon.dts b/boards/particle/argon/particle_argon.dts similarity index 100% rename from boards/arm/particle_argon/particle_argon.dts rename to boards/particle/argon/particle_argon.dts diff --git a/boards/arm/particle_argon/particle_argon.yaml b/boards/particle/argon/particle_argon.yaml similarity index 100% rename from boards/arm/particle_argon/particle_argon.yaml rename to boards/particle/argon/particle_argon.yaml diff --git a/boards/arm/particle_argon/particle_argon_defconfig b/boards/particle/argon/particle_argon_defconfig similarity index 76% rename from boards/arm/particle_argon/particle_argon_defconfig rename to boards/particle/argon/particle_argon_defconfig index 5f3f7a7e2b5..78464adc4aa 100644 --- a/boards/arm/particle_argon/particle_argon_defconfig +++ b/boards/particle/argon/particle_argon_defconfig @@ -4,10 +4,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PARTICLE_ARGON=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52dk_nrf52810/pre_dt_board.cmake b/boards/particle/argon/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52dk_nrf52810/pre_dt_board.cmake rename to boards/particle/argon/pre_dt_board.cmake diff --git a/boards/arm/particle_boron/CMakeLists.txt b/boards/particle/boron/CMakeLists.txt similarity index 100% rename from boards/arm/particle_boron/CMakeLists.txt rename to boards/particle/boron/CMakeLists.txt diff --git a/boards/arm/particle_boron/Kconfig b/boards/particle/boron/Kconfig similarity index 100% rename from boards/arm/particle_boron/Kconfig rename to boards/particle/boron/Kconfig diff --git a/boards/particle/boron/Kconfig.defconfig b/boards/particle/boron/Kconfig.defconfig new file mode 100644 index 00000000000..cce1a36897f --- /dev/null +++ b/boards/particle/boron/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Particle Boron board configuration + +# Copyright (c) 2018 Peter Bigot Consulting, LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PARTICLE_BORON + +config BT_CTLR + default BT + +if MODEM + +config MODEM_UBLOX_SARA + default y + +choice MODEM_UBLOX_SARA_VARIANT + default MODEM_UBLOX_SARA_R4 +endchoice + +config UART_INTERRUPT_DRIVEN + default y + +endif # MODEM + +endif # BOARD_PARTICLE_BORON diff --git a/boards/particle/boron/Kconfig.particle_boron b/boards/particle/boron/Kconfig.particle_boron new file mode 100644 index 00000000000..d5a1d5be0fb --- /dev/null +++ b/boards/particle/boron/Kconfig.particle_boron @@ -0,0 +1,7 @@ +# Particle Boron configuration + +# Copyright (c) 2018 Peter Bigot Consulting, LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PARTICLE_BORON + select SOC_NRF52840_QIAA diff --git a/boards/arm/particle_boron/board.c b/boards/particle/boron/board.c similarity index 100% rename from boards/arm/particle_boron/board.c rename to boards/particle/boron/board.c diff --git a/boards/arm/particle_boron/board.cmake b/boards/particle/boron/board.cmake similarity index 100% rename from boards/arm/particle_boron/board.cmake rename to boards/particle/boron/board.cmake diff --git a/boards/particle/boron/board.yml b/boards/particle/boron/board.yml new file mode 100644 index 00000000000..bb77655e8c0 --- /dev/null +++ b/boards/particle/boron/board.yml @@ -0,0 +1,5 @@ +board: + name: particle_boron + vendor: particle + socs: + - name: nrf52840 diff --git a/boards/arm/particle_boron/doc/img/particle_boron.jpg b/boards/particle/boron/doc/img/particle_boron.jpg similarity index 100% rename from boards/arm/particle_boron/doc/img/particle_boron.jpg rename to boards/particle/boron/doc/img/particle_boron.jpg diff --git a/boards/arm/particle_boron/doc/index.rst b/boards/particle/boron/doc/index.rst similarity index 100% rename from boards/arm/particle_boron/doc/index.rst rename to boards/particle/boron/doc/index.rst diff --git a/boards/arm/particle_boron/dts/mesh_feather-pinctrl.dtsi b/boards/particle/boron/dts/mesh_feather-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_boron/dts/mesh_feather-pinctrl.dtsi rename to boards/particle/boron/dts/mesh_feather-pinctrl.dtsi diff --git a/boards/arm/particle_boron/dts/mesh_feather.dtsi b/boards/particle/boron/dts/mesh_feather.dtsi similarity index 100% rename from boards/arm/particle_boron/dts/mesh_feather.dtsi rename to boards/particle/boron/dts/mesh_feather.dtsi diff --git a/boards/arm/particle_boron/dts/mesh_feather_spi1_spi3.dtsi b/boards/particle/boron/dts/mesh_feather_spi1_spi3.dtsi similarity index 100% rename from boards/arm/particle_boron/dts/mesh_feather_spi1_spi3.dtsi rename to boards/particle/boron/dts/mesh_feather_spi1_spi3.dtsi diff --git a/boards/arm/particle_boron/dts/mesh_feather_spi_spi3.dtsi b/boards/particle/boron/dts/mesh_feather_spi_spi3.dtsi similarity index 100% rename from boards/arm/particle_boron/dts/mesh_feather_spi_spi3.dtsi rename to boards/particle/boron/dts/mesh_feather_spi_spi3.dtsi diff --git a/boards/arm/particle_boron/dts/mesh_feather_uart1_rtscts.dtsi b/boards/particle/boron/dts/mesh_feather_uart1_rtscts.dtsi similarity index 100% rename from boards/arm/particle_boron/dts/mesh_feather_uart1_rtscts.dtsi rename to boards/particle/boron/dts/mesh_feather_uart1_rtscts.dtsi diff --git a/boards/arm/particle_boron/particle_boron-pinctrl.dtsi b/boards/particle/boron/particle_boron-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_boron/particle_boron-pinctrl.dtsi rename to boards/particle/boron/particle_boron-pinctrl.dtsi diff --git a/boards/arm/particle_boron/particle_boron.dts b/boards/particle/boron/particle_boron.dts similarity index 100% rename from boards/arm/particle_boron/particle_boron.dts rename to boards/particle/boron/particle_boron.dts diff --git a/boards/arm/particle_boron/particle_boron.yaml b/boards/particle/boron/particle_boron.yaml similarity index 100% rename from boards/arm/particle_boron/particle_boron.yaml rename to boards/particle/boron/particle_boron.yaml diff --git a/boards/arm/particle_boron/particle_boron_defconfig b/boards/particle/boron/particle_boron_defconfig similarity index 83% rename from boards/arm/particle_boron/particle_boron_defconfig rename to boards/particle/boron/particle_boron_defconfig index 453981d2a64..b2fb4cb49c5 100644 --- a/boards/arm/particle_boron/particle_boron_defconfig +++ b/boards/particle/boron/particle_boron_defconfig @@ -3,10 +3,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PARTICLE_BORON=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52dk_nrf52832/pre_dt_board.cmake b/boards/particle/boron/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52dk_nrf52832/pre_dt_board.cmake rename to boards/particle/boron/pre_dt_board.cmake diff --git a/boards/particle/index.rst b/boards/particle/index.rst new file mode 100644 index 00000000000..c5bf20bb5c8 --- /dev/null +++ b/boards/particle/index.rst @@ -0,0 +1,10 @@ +.. _boards-particle: + +Particle Industries +################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/particle/nrf51_blenano/Kconfig.defconfig b/boards/particle/nrf51_blenano/Kconfig.defconfig new file mode 100644 index 00000000000..fb61b031143 --- /dev/null +++ b/boards/particle/nrf51_blenano/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF51 BLENANO board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF51_BLENANO + +config BT_CTLR + default BT + +endif # BOARD_NRF51_BLENANO diff --git a/boards/particle/nrf51_blenano/Kconfig.nrf51_blenano b/boards/particle/nrf51_blenano/Kconfig.nrf51_blenano new file mode 100644 index 00000000000..19888cdc202 --- /dev/null +++ b/boards/particle/nrf51_blenano/Kconfig.nrf51_blenano @@ -0,0 +1,7 @@ +# nRF51 BLENANO board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF51_BLENANO + select SOC_NRF51822_QFAA diff --git a/boards/arm/nrf51_blenano/board.cmake b/boards/particle/nrf51_blenano/board.cmake similarity index 100% rename from boards/arm/nrf51_blenano/board.cmake rename to boards/particle/nrf51_blenano/board.cmake diff --git a/boards/particle/nrf51_blenano/board.yml b/boards/particle/nrf51_blenano/board.yml new file mode 100644 index 00000000000..bc651160fa4 --- /dev/null +++ b/boards/particle/nrf51_blenano/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf51_blenano + vendor: particle + socs: + - name: nrf51822 diff --git a/boards/arm/nrf51_blenano/doc/img/daplink.jpg b/boards/particle/nrf51_blenano/doc/img/daplink.jpg similarity index 100% rename from boards/arm/nrf51_blenano/doc/img/daplink.jpg rename to boards/particle/nrf51_blenano/doc/img/daplink.jpg diff --git a/boards/arm/nrf51_blenano/doc/img/nrf51_blenano.jpg b/boards/particle/nrf51_blenano/doc/img/nrf51_blenano.jpg similarity index 100% rename from boards/arm/nrf51_blenano/doc/img/nrf51_blenano.jpg rename to boards/particle/nrf51_blenano/doc/img/nrf51_blenano.jpg diff --git a/boards/arm/nrf51_blenano/doc/index.rst b/boards/particle/nrf51_blenano/doc/index.rst similarity index 100% rename from boards/arm/nrf51_blenano/doc/index.rst rename to boards/particle/nrf51_blenano/doc/index.rst diff --git a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422-pinctrl.dtsi b/boards/particle/nrf51_blenano/nrf51_blenano-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422-pinctrl.dtsi rename to boards/particle/nrf51_blenano/nrf51_blenano-pinctrl.dtsi diff --git a/boards/arm/nrf51_blenano/nrf51_blenano.dts b/boards/particle/nrf51_blenano/nrf51_blenano.dts similarity index 100% rename from boards/arm/nrf51_blenano/nrf51_blenano.dts rename to boards/particle/nrf51_blenano/nrf51_blenano.dts diff --git a/boards/arm/nrf51_blenano/nrf51_blenano.yaml b/boards/particle/nrf51_blenano/nrf51_blenano.yaml similarity index 100% rename from boards/arm/nrf51_blenano/nrf51_blenano.yaml rename to boards/particle/nrf51_blenano/nrf51_blenano.yaml diff --git a/boards/particle/nrf51_blenano/nrf51_blenano_defconfig b/boards/particle/nrf51_blenano/nrf51_blenano_defconfig new file mode 100644 index 00000000000..1289685e1e8 --- /dev/null +++ b/boards/particle/nrf51_blenano/nrf51_blenano_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51_vbluno51/pre_dt_board.cmake b/boards/particle/nrf51_blenano/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf51_vbluno51/pre_dt_board.cmake rename to boards/particle/nrf51_blenano/pre_dt_board.cmake diff --git a/boards/particle/nrf52_blenano2/Kconfig.defconfig b/boards/particle/nrf52_blenano2/Kconfig.defconfig new file mode 100644 index 00000000000..df0bcd9b33a --- /dev/null +++ b/boards/particle/nrf52_blenano2/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52 BLENANO 2 board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52_BLENANO2 + +config BT_CTLR + default BT + +endif # BOARD_NRF52_BLENANO2 diff --git a/boards/particle/nrf52_blenano2/Kconfig.nrf52_blenano2 b/boards/particle/nrf52_blenano2/Kconfig.nrf52_blenano2 new file mode 100644 index 00000000000..f48ace77e7a --- /dev/null +++ b/boards/particle/nrf52_blenano2/Kconfig.nrf52_blenano2 @@ -0,0 +1,7 @@ +# nRF52 BLENANO 2 board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_BLENANO2 + select SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_blenano2/board.cmake b/boards/particle/nrf52_blenano2/board.cmake similarity index 100% rename from boards/arm/nrf52_blenano2/board.cmake rename to boards/particle/nrf52_blenano2/board.cmake diff --git a/boards/particle/nrf52_blenano2/board.yml b/boards/particle/nrf52_blenano2/board.yml new file mode 100644 index 00000000000..fedad35babc --- /dev/null +++ b/boards/particle/nrf52_blenano2/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52_blenano2 + vendor: particle + socs: + - name: nrf52832 diff --git a/boards/arm/nrf52_blenano2/doc/dap.jpg b/boards/particle/nrf52_blenano2/doc/dap.jpg similarity index 100% rename from boards/arm/nrf52_blenano2/doc/dap.jpg rename to boards/particle/nrf52_blenano2/doc/dap.jpg diff --git a/boards/arm/nrf52_blenano2/doc/index.rst b/boards/particle/nrf52_blenano2/doc/index.rst similarity index 100% rename from boards/arm/nrf52_blenano2/doc/index.rst rename to boards/particle/nrf52_blenano2/doc/index.rst diff --git a/boards/arm/nrf52_blenano2/doc/nrf52_blenano2.jpg b/boards/particle/nrf52_blenano2/doc/nrf52_blenano2.jpg similarity index 100% rename from boards/arm/nrf52_blenano2/doc/nrf52_blenano2.jpg rename to boards/particle/nrf52_blenano2/doc/nrf52_blenano2.jpg diff --git a/boards/arm/nrf52_blenano2/nrf52_blenano2-pinctrl.dtsi b/boards/particle/nrf52_blenano2/nrf52_blenano2-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52_blenano2/nrf52_blenano2-pinctrl.dtsi rename to boards/particle/nrf52_blenano2/nrf52_blenano2-pinctrl.dtsi diff --git a/boards/arm/nrf52_blenano2/nrf52_blenano2.dts b/boards/particle/nrf52_blenano2/nrf52_blenano2.dts similarity index 100% rename from boards/arm/nrf52_blenano2/nrf52_blenano2.dts rename to boards/particle/nrf52_blenano2/nrf52_blenano2.dts diff --git a/boards/arm/nrf52_blenano2/nrf52_blenano2.yaml b/boards/particle/nrf52_blenano2/nrf52_blenano2.yaml similarity index 100% rename from boards/arm/nrf52_blenano2/nrf52_blenano2.yaml rename to boards/particle/nrf52_blenano2/nrf52_blenano2.yaml diff --git a/boards/particle/nrf52_blenano2/nrf52_blenano2_defconfig b/boards/particle/nrf52_blenano2/nrf52_blenano2_defconfig new file mode 100644 index 00000000000..7167aca850a --- /dev/null +++ b/boards/particle/nrf52_blenano2/nrf52_blenano2_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf52840/pre_dt_board.cmake b/boards/particle/nrf52_blenano2/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/pre_dt_board.cmake rename to boards/particle/nrf52_blenano2/pre_dt_board.cmake diff --git a/boards/arm/particle_xenon/CMakeLists.txt b/boards/particle/xenon/CMakeLists.txt similarity index 100% rename from boards/arm/particle_xenon/CMakeLists.txt rename to boards/particle/xenon/CMakeLists.txt diff --git a/boards/arm/particle_xenon/Kconfig b/boards/particle/xenon/Kconfig similarity index 100% rename from boards/arm/particle_xenon/Kconfig rename to boards/particle/xenon/Kconfig diff --git a/boards/particle/xenon/Kconfig.defconfig b/boards/particle/xenon/Kconfig.defconfig new file mode 100644 index 00000000000..1cd3ad31f06 --- /dev/null +++ b/boards/particle/xenon/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Particle Xenon board configuration + +# Copyright (c) 2018 Endre Karlson +# Copyright (c) 2018 Peter Bigot Consulting, LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PARTICLE_XENON + +config BT_CTLR + default BT + +endif # BOARD_PARTICLE_XENON diff --git a/boards/particle/xenon/Kconfig.particle_xenon b/boards/particle/xenon/Kconfig.particle_xenon new file mode 100644 index 00000000000..84487057f49 --- /dev/null +++ b/boards/particle/xenon/Kconfig.particle_xenon @@ -0,0 +1,7 @@ +# Particle Xenon configuration + +# Copyright (c) 2018 Endre Karlson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PARTICLE_XENON + select SOC_NRF52840_QIAA diff --git a/boards/arm/particle_xenon/board.c b/boards/particle/xenon/board.c similarity index 100% rename from boards/arm/particle_xenon/board.c rename to boards/particle/xenon/board.c diff --git a/boards/arm/particle_xenon/board.cmake b/boards/particle/xenon/board.cmake similarity index 100% rename from boards/arm/particle_xenon/board.cmake rename to boards/particle/xenon/board.cmake diff --git a/boards/particle/xenon/board.yml b/boards/particle/xenon/board.yml new file mode 100644 index 00000000000..a681db97a1f --- /dev/null +++ b/boards/particle/xenon/board.yml @@ -0,0 +1,5 @@ +board: + name: particle_xenon + vendor: particle + socs: + - name: nrf52840 diff --git a/boards/arm/particle_xenon/doc/img/particle_xenon.jpg b/boards/particle/xenon/doc/img/particle_xenon.jpg similarity index 100% rename from boards/arm/particle_xenon/doc/img/particle_xenon.jpg rename to boards/particle/xenon/doc/img/particle_xenon.jpg diff --git a/boards/arm/particle_xenon/doc/index.rst b/boards/particle/xenon/doc/index.rst similarity index 100% rename from boards/arm/particle_xenon/doc/index.rst rename to boards/particle/xenon/doc/index.rst diff --git a/boards/arm/particle_xenon/dts/mesh_feather-pinctrl.dtsi b/boards/particle/xenon/dts/mesh_feather-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather-pinctrl.dtsi rename to boards/particle/xenon/dts/mesh_feather-pinctrl.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather.dtsi b/boards/particle/xenon/dts/mesh_feather.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather.dtsi rename to boards/particle/xenon/dts/mesh_feather.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather_i2c1_twi1.dtsi b/boards/particle/xenon/dts/mesh_feather_i2c1_twi1.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather_i2c1_twi1.dtsi rename to boards/particle/xenon/dts/mesh_feather_i2c1_twi1.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather_spi1_spi3.dtsi b/boards/particle/xenon/dts/mesh_feather_spi1_spi3.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather_spi1_spi3.dtsi rename to boards/particle/xenon/dts/mesh_feather_spi1_spi3.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather_spi_spi1.dtsi b/boards/particle/xenon/dts/mesh_feather_spi_spi1.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather_spi_spi1.dtsi rename to boards/particle/xenon/dts/mesh_feather_spi_spi1.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather_spi_spi3.dtsi b/boards/particle/xenon/dts/mesh_feather_spi_spi3.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather_spi_spi3.dtsi rename to boards/particle/xenon/dts/mesh_feather_spi_spi3.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather_uart1_rtscts.dtsi b/boards/particle/xenon/dts/mesh_feather_uart1_rtscts.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather_uart1_rtscts.dtsi rename to boards/particle/xenon/dts/mesh_feather_uart1_rtscts.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_xenon_uart2.dtsi b/boards/particle/xenon/dts/mesh_xenon_uart2.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_xenon_uart2.dtsi rename to boards/particle/xenon/dts/mesh_xenon_uart2.dtsi diff --git a/boards/arm/particle_xenon/particle_xenon-pinctrl.dtsi b/boards/particle/xenon/particle_xenon-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_xenon/particle_xenon-pinctrl.dtsi rename to boards/particle/xenon/particle_xenon-pinctrl.dtsi diff --git a/boards/arm/particle_xenon/particle_xenon.dts b/boards/particle/xenon/particle_xenon.dts similarity index 100% rename from boards/arm/particle_xenon/particle_xenon.dts rename to boards/particle/xenon/particle_xenon.dts diff --git a/boards/arm/particle_xenon/particle_xenon.yaml b/boards/particle/xenon/particle_xenon.yaml similarity index 100% rename from boards/arm/particle_xenon/particle_xenon.yaml rename to boards/particle/xenon/particle_xenon.yaml diff --git a/boards/particle/xenon/particle_xenon_defconfig b/boards/particle/xenon/particle_xenon_defconfig new file mode 100644 index 00000000000..918f925556e --- /dev/null +++ b/boards/particle/xenon/particle_xenon_defconfig @@ -0,0 +1,17 @@ +# +# Copyright (c) 2018, Endre Karlson +# +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/particle_argon/pre_dt_board.cmake b/boards/particle/xenon/pre_dt_board.cmake similarity index 100% rename from boards/arm/particle_argon/pre_dt_board.cmake rename to boards/particle/xenon/pre_dt_board.cmake diff --git a/boards/phytec/index.rst b/boards/phytec/index.rst new file mode 100644 index 00000000000..0bde22965df --- /dev/null +++ b/boards/phytec/index.rst @@ -0,0 +1,10 @@ +.. _boards-phytec: + +PHYTEC Messtechnik GmbH +####################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/phytec/mimx8mm_phyboard_polis/Kconfig.defconfig b/boards/phytec/mimx8mm_phyboard_polis/Kconfig.defconfig new file mode 100644 index 00000000000..ec8c8486351 --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/Kconfig.defconfig @@ -0,0 +1,15 @@ +# MIMX8MM_PHYBOARD_POLIS board defconfig +# +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMX8MM_PHYBOARD_POLIS + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_MIMX8MM_PHYBOARD_POLIS diff --git a/boards/phytec/mimx8mm_phyboard_polis/Kconfig.mimx8mm_phyboard_polis b/boards/phytec/mimx8mm_phyboard_polis/Kconfig.mimx8mm_phyboard_polis new file mode 100644 index 00000000000..0039e251a76 --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/Kconfig.mimx8mm_phyboard_polis @@ -0,0 +1,7 @@ +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMX8MM_PHYBOARD_POLIS + select SOC_PART_NUMBER_MIMX8MM6DVTLZ + select SOC_MIMX8MM6_M4 if BOARD_MIMX8MM_PHYBOARD_POLIS_MIMX8MM6_M4 diff --git a/boards/arm/mimx8mm_evk/board.cmake b/boards/phytec/mimx8mm_phyboard_polis/board.cmake similarity index 100% rename from boards/arm/mimx8mm_evk/board.cmake rename to boards/phytec/mimx8mm_phyboard_polis/board.cmake diff --git a/boards/phytec/mimx8mm_phyboard_polis/board.yml b/boards/phytec/mimx8mm_phyboard_polis/board.yml new file mode 100644 index 00000000000..1c416b90eb1 --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/board.yml @@ -0,0 +1,5 @@ +board: + name: mimx8mm_phyboard_polis + vendor: phytec + socs: + - name: mimx8mm6 diff --git a/boards/arm/mimx8mm_phyboard_polis/doc/img/PEB-EVAL-01.jpg b/boards/phytec/mimx8mm_phyboard_polis/doc/img/PEB-EVAL-01.jpg similarity index 100% rename from boards/arm/mimx8mm_phyboard_polis/doc/img/PEB-EVAL-01.jpg rename to boards/phytec/mimx8mm_phyboard_polis/doc/img/PEB-EVAL-01.jpg diff --git a/boards/arm/mimx8mm_phyboard_polis/doc/img/phyBOARD-Polis.jpg b/boards/phytec/mimx8mm_phyboard_polis/doc/img/phyBOARD-Polis.jpg similarity index 100% rename from boards/arm/mimx8mm_phyboard_polis/doc/img/phyBOARD-Polis.jpg rename to boards/phytec/mimx8mm_phyboard_polis/doc/img/phyBOARD-Polis.jpg diff --git a/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst b/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst new file mode 100644 index 00000000000..1568a6f3f2b --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst @@ -0,0 +1,342 @@ +.. _mimx8mm_phyboard_polis: + +PhyBOARD Polis (NXP i.MX8M Mini) +################################ + +Overview +******** + +The phyBOARD-Polis, either a development platform for the +phyCORE-i.MX 8M Mini/Nano, or a powerful, industry-compatible single-board +computer for immediate implementation of your product idea. As a development +platform, the phyBOARD-Polis serves as reference design for your +customer-specific application and enables parallel development of the software +and carrier board for the phyCORE-i.MX 8M Mini/Nano. + + +As a powerful, industrial single-board computer (SBC), the phyBOARD-Polis is +equipped with a variety of standard interfaces which are available on standard +or socket/pin header connectors, while interesting extensions of the +phyCORE-i.MX 8M Mini/Nano features such as CAN FD, WLAN and an integrated +TPM chip further extend the range of applications that can be developed with +the phyCORE-i.MX 8M Mini/Nano. + +- Board features: + + - RAM: 512MB - 4GB (LPDDR4) + - Storage: + + - 4GB - 128GB eMMC + - 8MB - 128MB SPI NOR Flash + - microSD Interfacce + - 4kB EEPROM + - Wireless: + + - WiFi: 802.11 b/g/n (ac) 2,4 GHz / 5 GHz + - BLE 4.2 + - USB: + + - 1x USB2.0 OTG + - 1x USB2.0 + - Ethernet: 1x 10/100/1000BASE-T + - Interfaces: + - 1x RS232 / RS485 + - 2x UART + - 3x I²C + - 2x SPI + - Up to 4x PWM + - 4x SAI + - 1x MIPI CSI-2 + - 1x MIPI DSI-2 + - 2x MMC/SD/SDIO + - 1x PCIe (mini PCIE) + - LEDs: + + - 1x Status LED (3 Color LED) + - 1x Debug UART LED + - Debug + + - JTAG 20-pin connector + - MicroUSB for UART debug, two COM ports for A53 and M4 + +.. image:: img/phyBOARD-Polis.jpg + :align: center + :alt: PhyBOARD Polis + :width: 500 + +More information about the board can be found at the +`PHYTEC website`_. + +Supported Features +================== + +The Zephyr ``mimx8mm_phyboard_polis/mimx8mm6/m4`` board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig`. + +It is recommended to disable peripherals used by the M4 core on the Linux host. + +Other hardware features are not currently supported with Zephyr on the +M4-Core. + +Connections and IOs +=================== + +The following components are tested and working correctly. + +UART: +----- + +Zephyr is configured to use UART4 on the PhyBoard Polis by default to minimize +problems with the A53-Core because UART4 is only accessible from the M4-Core. + ++---------------+-----------------+-----------------------------------+ +| Board Name | SoM Name | Usage | ++===============+=================+===================================+ +| RS232/485 | UART1 | RS232 / RS485 with flow-control | ++---------------+-----------------+-----------------------------------+ +| To WiFi Module| UART2 | UART to WiFi/BLE Module | ++---------------+-----------------+-----------------------------------+ +| Debug USB(A53)| UART3 | UART Debug Console via USB | ++---------------+-----------------+-----------------------------------+ +| Debug USB(M4) | UART4 | UART Debug Console via USB | ++---------------+-----------------+-----------------------------------+ + +.. note:: + Please note, that the to UART2 connected Wifi/BLE Module isn't working with + Zephyr yet. + +.. warning:: + On Boards with the version number 1532.1 UART4 isn't connected to the Debug + USB. UART4 connects to pin 10(RX) and 12(TX) on the X8 pinheader. + + +LEDs: +----- + +Zephyr has the 3-color status LED configured. The led0 alias (the standard +Zephyr led) is configured to be the blue led. The LED can also light up in red +and green. + +GPIO: +----- + +The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mm devicetree +created by NXP. You can find it here: + +:zephyr_file:`dts/arm/nxp/nxp_imx8m_m4.dtsi`. + +The Pinout of the PhyBOARD Polis can be found here: + +`PHYTEC website`_ + +System Clock +============ + +The M4 Core is configured to run at a 400 MHz clock speed. + + +Programming and Debugging +************************* + +The i.MX8MM does not have a separate flash for the M4-Core. Because of this +the A53-Core has to load the program for the M4-Core to the right memory +address, set the PC and start the processor. +This can be done with U-Boot or Phytec's Linux BSP via remoteproc. + +Because remoteproc in Phytec's BSP only writes to the TCM memory area, +everything was tested in this memory area. + +You can read more about remoteproc in Phytec's BSP here: `Remoteproc BSP`_ + +These are the memory mapping for A53 and M4: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file ``boards/arm/mimx8mm_evk/mimx8mm_evk.dts`` +with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. +The available configurations are: + +If you don't want to use the TCM memory area, you can either overwrite the +boards devicetree in your program or edit the board devicetree located here: + +:zephyr_file:`boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.dts`. + +You also have to set XIP=n or edit the boards defconfig file, if you don't want +the TCM memory area to be used. You can find the defconf file here: + +:zephyr_file:`boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig`. + +The following configurations are possible for the flash and sram chosen nodes +to change the used memory area: + +.. code-block:: none + + "zephyr,flash" + - &tcml_code + - &ocram_code + - &ocram_s_code + + "zephyr,sram" + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + + +Starting the M4-Core via U-Boot +=============================== + +Load the compiled zephyr.bin to memory address 0x4800000. +This should output something like this: + +.. code-block:: console + + u-boot=> tftp 0x48000000 192.168.3.10:zyphr.bin + Using ethernet@30be0000 device + TFTP from server 192.168.3.10; our IP address is 192.168.3.11 + Filename 'zepyhr.bin'. + Load address: 0x48000000 + Loading: ## + 2 KiB/s + done + Bytes transferred = 27240 (6a68 hex) + +Because it's not possible to load directly to the TCM memory area you have to +copy the binaries. The last argument given is the size of the file in bytes, +you can copy it from the output of the last command. + +.. code-block:: console + + u-boot=> cp.b 0x48000000 0x7e0000 27240 + +And finaly starting the M4-Core at the right memory address: + +.. code-block:: console + + u-boot=> bootaux 0x7e0000 + ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905... + + +Starting the M4-Core via remoteproc +=================================== + +Copy the zepyhr.elf to ``/lib/firmware`` on the target. Maybe a Zephyr sample +will be included in a future BSP release. + +.. note:: + In order to use remoteproc you have to add ``imx8mm-phycore-rpmsg.dtbo`` at + the end of the line in the ``/boot/bootenv.txt``, then reboot the target. + +.. warning:: + Remoteproc only reads firmware files from the ``/lib/firmware`` directory! + If you try to load a binary from another location unexpected errors will + occur! + +To load and start a firmware use this commands: + +.. code-block:: console + + target$ echo /lib/firmware/zepyhr.elf > /sys/class/remoteproc/remoteproc0/firmware + target$ echo start > /sys/class/remoteproc/remoteproc0/state + [ 90.700611] remoteproc remoteproc0: powering up imx-rproc + [ 90.706114] remoteproc remoteproc0: Direct firmware load for /lib/firmware/zepyhr.elf failed w2 + [ 90.716571] remoteproc remoteproc0: Falling back to sysfs fallback for: /lib/firmware/zepyhr.elf + [ 90.739280] remoteproc remoteproc0: Booting fw image /lib/firmware/zepyhr.elf, size 599356 + [ 90.804448] remoteproc remoteproc0: remote processor imx-rproc is now up + + +The M4-Core is now started up and running. You can see the output from Zephyr +on UART4. + +Debugging +========= + +The PhyBOARD Polis can be debugged using a JTAG Debugger. +The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's +``PEB-EVAL-01`` Shield, which can be directly connected to the JLink. +You can find the JLink Software package here: `JLink Software`_ + +.. figure:: img/PEB-EVAL-01.jpg + :alt: PEB-EVAL-01 + :width: 350 + + PEB-EVAL-01 + +To debug efficiently you should use multiple terminals: + +(But its also possible to use ``west debug``) + +After connecting everything and building with west use this command while in +the directory of the program you build earlier to start a debug server: + +.. code-block:: console + + host$ west debugserver + +West automatically connects via the JLink to the Target. And keeps open a +debug server. + +Use another terminal, start gdb, connect to target and load Zephyr on the +target: + +.. code-block:: console + + host$ gdb-multiarch build/zephyr/zephyr.elf -tui + (gdb) targ rem :2331 + Remote debugging using :2331 + 0x1ffe0008 in _vector_table () + (gdb) mon halt + (gdb) mon reset + (gdb) c + Continuing. + +The program can be debugged using standard gdb techniques. + +.. _PHYTEC website: + https://www.phytec.de/produkte/single-board-computer/phyboard-polis-imx8m-mini/ + +.. _PhyBOARD Polis pinout: + https://download.phytec.de/Products/phyBOARD-Polis-iMX8M_Mini/TechData/phyCORE-i.MX8M_MINI_Pin_Muxing_Table.A1.xlsx?_ga=2.237582016.1177557183.1660563641-1900651135.1634193918 + +.. _Remoteproc BSP: + https://wiki.phytec.com/pages/releaseview.action?pageId=472257137#L1002e.A3i.MX8MMini/NanoBSPManual-RunningExamplesfromLinuxusingRemoteproc + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MMRM + +.. _JLink Software: + https://www.segger.com/downloads/jlink/ diff --git a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi similarity index 100% rename from boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi rename to boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi diff --git a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.dts b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.dts similarity index 100% rename from boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.dts rename to boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.dts diff --git a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.yaml b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.yaml new file mode 100644 index 00000000000..0125a4fa399 --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2020 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimx8mm_phyboard_polis/mimx8mm6/m4 +name: Phyboard Polis i.MX8M Mini +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig new file mode 100644 index 00000000000..9fad86a42a7 --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_PINCTRL=y +CONFIG_GPIO=y diff --git a/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.defconfig b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.defconfig new file mode 100644 index 00000000000..e860faf97cf --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.defconfig @@ -0,0 +1,15 @@ +# PhyBOARD Pollux (i.MX8MP) defconfig + +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMX8MP_PHYBOARD_POLLUX + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_MIMX8MP_PHYBOARD_POLLUX diff --git a/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux new file mode 100644 index 00000000000..75165bf5a29 --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux @@ -0,0 +1,6 @@ +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMX8MP_PHYBOARD_POLLUX + select SOC_MIMX8MP_M7 if BOARD_MIMX8MP_PHYBOARD_POLLUX_MIMX8ML8_M7 + select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm/mimx8mp_phyboard_pollux/board.cmake b/boards/phytec/mimx8mp_phyboard_pollux/board.cmake similarity index 100% rename from boards/arm/mimx8mp_phyboard_pollux/board.cmake rename to boards/phytec/mimx8mp_phyboard_pollux/board.cmake diff --git a/boards/phytec/mimx8mp_phyboard_pollux/board.yml b/boards/phytec/mimx8mp_phyboard_pollux/board.yml new file mode 100644 index 00000000000..b871a53e370 --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/board.yml @@ -0,0 +1,5 @@ +board: + name: mimx8mp_phyboard_pollux + vendor: phytec + socs: + - name: mimx8ml8 diff --git a/boards/arm/mimx8mp_phyboard_pollux/doc/img/PEB-EVAL-01.jpg b/boards/phytec/mimx8mp_phyboard_pollux/doc/img/PEB-EVAL-01.jpg similarity index 100% rename from boards/arm/mimx8mp_phyboard_pollux/doc/img/PEB-EVAL-01.jpg rename to boards/phytec/mimx8mp_phyboard_pollux/doc/img/PEB-EVAL-01.jpg diff --git a/boards/arm/mimx8mp_phyboard_pollux/doc/img/Phyboard_Pollux.jpg b/boards/phytec/mimx8mp_phyboard_pollux/doc/img/Phyboard_Pollux.jpg similarity index 100% rename from boards/arm/mimx8mp_phyboard_pollux/doc/img/Phyboard_Pollux.jpg rename to boards/phytec/mimx8mp_phyboard_pollux/doc/img/Phyboard_Pollux.jpg diff --git a/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst b/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst new file mode 100644 index 00000000000..501c7f541a0 --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst @@ -0,0 +1,272 @@ +.. _mimx8mp_phyboard_pollux: + +PhyBOARD Pollux (NXP i.MX8M Plus) +################################# + +Overview +******** + +The PhyBOARD Pollux is based upon the PhyCore-i.MX8M Plus SOM which is based on +the NXP i.MX8M Plus SoC. The SoC includes four Coretex-A53 cores and one +Coretex-M7 core for real time applications like Zephyr. The PhyBOARD Pollux +can be used for various applications like SmartHomes, Industry 4.0, IoT etc. +It features a lots of interfaces and computing capacity. It can be used as +a reference, to develop or in the final product too. + + +Board features: + +- Memory: + + - RAM: 256MB - 8GB LPDDR4 + - EEPROM: 4kB - 32kB + - eMMC: 4GB - 64GB (eMMC 5.1) + - SPI NOR Flash: 4MB - 256MB +- Interfaces: + + - Ethernet: 2x 10/100/1000BASE-T (1x TSN Support) + - USB: 2x 3.0 Host + - Serial: 1x RS232 / RS485 Full Duplex / Half Duplex + - CAN: 2x CAN FD + - Digital I/O: via Expansion Connector + - PCIe: 1x miniPCIe + - MMX/SD/SDIO: microSD slot + - Display: LVDS(1x4 or 1x8), MIPI DSI(1x4), HDMI + - Audio: SAI + - Camera: 2x MIPI CSI-2 (PhyCAM-M) + - Expansion Bus: I2C, SPI, SDIO, UART, USB + - JTAG: via PEB-EVAL-01 +- LEDs: + + - 1x Multicolor Status LED via I2C + + +.. image:: img/Phyboard_Pollux.jpg + :width: 720px + :align: center + :height: 405px + :alt: PhyBOARD Pollux + +More information about the board can be found at the +`PHYTEC website`_. + +Supported Features +================== + +The Zephyr mimx8mp_phyboard_polis board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig`. + +It's recommended to disable peripherals used by the M7-Core on the host running +on the Linux host. + +Other hardware features are not currently supported with Zephyr on the +M7-Core. + +Connections and IOs +=================== + +The following Compontens are tested and working correctly. + +UART +---- + ++---------------+-----------------+-----------------------------------+ +| Board Name | SoM Name | Usage | ++===============+=================+===================================+ +| Debug USB(A53)| UART1 | UART Debug Console via USB | ++---------------+-----------------+-----------------------------------+ +| Wo WiFi Module| UART3 | UART to WiFi/BLE Module | ++---------------+-----------------+-----------------------------------+ +| Debug USB(M4) | UART4 | UART Debug Console via USB | ++---------------+-----------------+-----------------------------------+ + +.. note:: + Please note, that the, to UART3 connected, Wifi/BLE Module isn't working with + Zephyr yet. UART3 can also be used through pin 31(RX) and 33(TX) of the + X6 Connector. + +GPIO +---- + +The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mp devicetree +created by NXP. You can find it here: + +:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. + +The Pinout of the PhyBOARD Polis can be found here: + +`PHYTEC website`_ + +Programming and Debugging +************************* + +The i.MX8MP does not have a separate flash for the M7-Core. Because of this +the A53-Core has to load the program for the M7-Core to the right memory +address, set the PC and start the processor. +This can only by done with u-boot at the moment. We are working on our BSP to +enable remoteproc support. + +The M7 can use up to 3 different RAMs (currently, only two configurations are +supported: ITCM and DDR). These are the memory mapping for A53 and M7: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3) + +At compilation time you have to choose which memory region will be used. This +configuration is done in the devicetree and the defconfig / the config of your +program. + +**By default Zephyr will use the TCM memory region.** You can configure it like +this for the DDR region: + +In the devicetree overwrite the following nodes like this: + +.. code-block:: DTS + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + }; + +change it to + +.. code-block:: DTS + + chosen { + /* DDR */ + zephyr,flash = &ddr_code; + zephyr,sram = &ddr_sys; + }; + + +In your prj.conf overwrite the configuration like this for the **DDR** memory +region: + +.. code-block:: console + + CONFIG_CODE_DDR=y + CONFIG_CODE_ITCM=n + + +Starting the M7-Core via U-Boot +=============================== + +Load the compiled zephyr.bin to memory address 0x4800000. +This should output something like this: + +.. code-block:: console + + u-boot=> tftp 0x48000000 192.168.3.10:zyphr.bin + Using ethernet@30be0000 device + TFTP from server 192.168.3.10; our IP address is 192.168.3.11 + Filename 'zepyhr.bin'. + Load address: 0x48000000 + Loading: ## + 2 KiB/s + done + Bytes transferred = 27240 (6a68 hex) + +Because it's not possible to load directly to the TCM memory area you have to +copy the binaries. The last argument given is the size of the file in bytes, +you can copy it from the output of the last command. + +.. code-block:: console + + u-boot=> cp.b 0x48000000 0x7e0000 27240 + +And finaly starting the M7-Core at the right memory address: + +.. code-block:: console + + u-boot=> bootaux 0x7e0000 + ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905... + +Debugging +========= + +The PhyBOARD Polis can be debugged using a JTAG Debugger. +The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's +``PEB-EVAL-01`` Shield, which can be directly connected to the JLink. +You can find the JLink Software package here: `JLink Software`_ + +.. figure:: img/PEB-EVAL-01.jpg + :alt: PEB-EVAL-01 + :width: 350 + + PEB-EVAL-01 + +To debug efficiently you have to use multiple terminals: + +After connecting everything and building with west use this command while in +the directory of the program you build earlier to start a debug server: + +.. code-block:: console + + host$ west debugserver + +West automatically connects via the JLink to the Target and keeps open a +debug server. + +Use another terminal, start gdb, connect to target and load Zephyr on the +target: + +.. code-block:: console + + host$ gdb-multiarch build/zephyr/zephyr.elf -tui + (gdb) targ rem :2331 + Remote debugging using :2331 + 0x1ffe0008 in _vector_table () + (gdb) mon halt + (gdb) mon reset + (gdb) c + Continuing. + +The program can be debugged using standard gdb techniques. + +References +========== + +.. _PHYTEC website: + https://www.phytec.de/produkte/single-board-computer/phyboard-pollux/ + +.. _i.MX 8M Plus Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MPRM + +.. _JLink Software: + https://www.segger.com/downloads/jlink/ diff --git a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux-pinctrl.dtsi b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux-pinctrl.dtsi similarity index 100% rename from boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux-pinctrl.dtsi rename to boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux-pinctrl.dtsi diff --git a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux.dts b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.dts similarity index 100% rename from boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux.dts rename to boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.dts diff --git a/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.yaml b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.yaml new file mode 100644 index 00000000000..aa2cc09a553 --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.yaml @@ -0,0 +1,24 @@ +# +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimx8mp_phyboard_pollux/mimx8ml8/m7 +name: PhyBOARD Pollux (i.MX8MP) +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - uart + - gpio +vendor: nxp diff --git a/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig new file mode 100644 index 00000000000..4926fdbe4e1 --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig @@ -0,0 +1,20 @@ +# +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y + +# y for TCM memory space +CONFIG_CODE_ITCM=y + +# y for DDR memory space +CONFIG_CODE_DDR=n + +CONFIG_PINCTRL=y diff --git a/boards/phytec/phyboard_lyra_am62x/Kconfig.phyboard_lyra_am62x b/boards/phytec/phyboard_lyra_am62x/Kconfig.phyboard_lyra_am62x new file mode 100644 index 00000000000..1b9c5eb8161 --- /dev/null +++ b/boards/phytec/phyboard_lyra_am62x/Kconfig.phyboard_lyra_am62x @@ -0,0 +1,11 @@ +# Texas Instruments Sitara AM62x-SK-M4 EVM +# +# Copyright (c) 2023 Texas Instruments Incorporated +# Copyright (c) 2023 L Lakshmanan +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PHYBOARD_LYRA_AM62X + select SOC_AM6234_M4 if BOARD_PHYBOARD_LYRA_AM62X_AM6234_M4 + help + PHYTEC AM62x M4 phyBOARD-Lyra diff --git a/boards/phytec/phyboard_lyra_am62x/board.yml b/boards/phytec/phyboard_lyra_am62x/board.yml new file mode 100644 index 00000000000..d91be2b4786 --- /dev/null +++ b/boards/phytec/phyboard_lyra_am62x/board.yml @@ -0,0 +1,5 @@ +board: + name: phyboard_lyra_am62x + vendor: phytec + socs: + - name: am6234 diff --git a/boards/arm/am62x_m4/doc/img/phyCORE-AM62x_Lyra_frontside.webp b/boards/phytec/phyboard_lyra_am62x/doc/img/phyCORE-AM62x_Lyra_frontside.webp similarity index 100% rename from boards/arm/am62x_m4/doc/img/phyCORE-AM62x_Lyra_frontside.webp rename to boards/phytec/phyboard_lyra_am62x/doc/img/phyCORE-AM62x_Lyra_frontside.webp diff --git a/boards/phytec/phyboard_lyra_am62x/doc/index.rst b/boards/phytec/phyboard_lyra_am62x/doc/index.rst new file mode 100644 index 00000000000..f18636318fd --- /dev/null +++ b/boards/phytec/phyboard_lyra_am62x/doc/index.rst @@ -0,0 +1,145 @@ +.. _am62x_m4_phyboard_lyra: + +AM62x phyBOARD-Lyra M4F Core +############################ + +Overview +******** + +The AM62x phyBOARD-Lyra board configuration is used by Zephyr applications +that run on the TI AM62x platform. The board configuration provides support +for the ARM Cortex-M4F MCU core and the following features: + +- Nested Vector Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) + +The board configuration also enables support for the semihosting debugging console. + +See the `PHYTEC AM62x Product Page`_ for details. + +.. figure:: img/phyCORE-AM62x_Lyra_frontside.webp + :align: center + :alt: AM62x phyBOARD-Lyra + + PHYTEC phyBOARD-Lyra with the phyCORE-AM62x SoM + +Hardware +******** +The AM62x phyBOARD-Lyra kit features the AM62x SoC, which is composed of a +quad Cortex-A53 cluster and a single Cortex-M4 core in the MCU domain. Zephyr +is ported to run on the M4F core and the following listed hardware +specifications are used: + +- Low-power ARM Cortex-M4F +- Memory + + - 256KB of SRAM + - 2GB of DDR4 + +- Debug + + - XDS110 based JTAG + +Supported Features +================== + +The am62x_m4_phyboard_lyra configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 400 MHz. + +DDR RAM +------- + +The board has 2GB of DDR RAM available. This board configuration +allocates Zephyr 4kB of RAM (only for resource table: 0x9CC00000 to 0x9CC00400). + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +MCU domain UART (MCU_UART0). + +SD Card +******* + +Download PHYTEC's official `WIC`_ as well as `BMAP`_ and flash the WIC file with +an etching software onto an SD-card. This will boot Linux on the A53 application +cores of the SoM. These cores will then load the zephyr binary on the M4 core +using remoteproc. + +The default configuration can be found in +:zephyr_file:`boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4_defconfig` + +Flashing +******** + +The Linux running on the A53 uses the remoteproc framework to manage the M4F co-processor. +Therefore, the testing requires the binary to be copied to the SD card to allow the A53 cores to +load it while booting using remoteproc. + +To test the M4F core, we build the `hello_world` sample with the following command. + +.. code-block:: console + + # From the root of the Zephyr repository + west build -p -b phyboard_lyra_am62x/am6234/m4 samples/hello_world + +This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. + +We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. + +.. code-block:: console + + # Mount the SD card at sdcard for example + sudo mount /dev/sdX sdcard + # copy the elf to the /lib/firmware directory + sudo cp --remove-destination zephyr.elf sdcard/lib/firmware/am62-mcu-m4f0_0-fw + +The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot. + +To allow the board to boot using the SD card, set the boot pins to the SD Card boot mode. Refer to `phyBOARD SD Card Booting Essentials`_. + +After changing the boot mode, stop in U-Boot to enable the M4F co-processor. + +.. code-block:: console + + setenv overlays k3-am62-phyboard-lyra-rpmsg.dtbo + # Save the overlays variable permanently + saveenv + boot + +The board should boot into Linux and the binary will run and print Hello world to the MCU_UART0 +port. + + + +.. _PHYTEC AM62x Product Page: + https://www.phytec.com/product/phycore-am62x/ + +.. _WIC: + https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz + +.. _BMAP: + https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.bmap + +.. _phyBOARD SD Card Booting Essentials: + https://docs.phytec.com/latest/phycore-am62x/bootingessentials/sdcard.html diff --git a/boards/arm/am62x_m4/am62x_m4_phyboard_lyra.dts b/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.dts similarity index 100% rename from boards/arm/am62x_m4/am62x_m4_phyboard_lyra.dts rename to boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.dts diff --git a/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.yaml b/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.yaml new file mode 100644 index 00000000000..df0e8ec65bd --- /dev/null +++ b/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.yaml @@ -0,0 +1,8 @@ +identifier: phyboard_lyra_am62x/am6234/m4 +name: PHYTEC AM62x M4 phyBOARD-Lyra +type: mcu +arch: arm +toolchain: + - zephyr +ram: 192 +vendor: phytec diff --git a/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4_defconfig b/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4_defconfig new file mode 100644 index 00000000000..7e20705fa3f --- /dev/null +++ b/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4_defconfig @@ -0,0 +1,25 @@ +# PHYTEC AM62x M4 phyBOARD-Lyra +# +# Copyright (C) 2023 PHYTEC Messtechnik GmbH +# Author: Daniel Schultz +# +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_CORTEX_M_SYSTICK=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Enable Pinctrl +CONFIG_PINCTRL=y + +# Serial Driver +CONFIG_SERIAL=y + +# GPIO Driver +CONFIG_GPIO=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/phytec/phycore_am62x/Kconfig.phycore_am62x b/boards/phytec/phycore_am62x/Kconfig.phycore_am62x new file mode 100644 index 00000000000..8c66cb29198 --- /dev/null +++ b/boards/phytec/phycore_am62x/Kconfig.phycore_am62x @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Enphase Energy +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PHYCORE_AM62X + select SOC_AM6234_A53 if BOARD_PHYCORE_AM62X_AM6234_A53 diff --git a/boards/phytec/phycore_am62x/board.yml b/boards/phytec/phycore_am62x/board.yml new file mode 100644 index 00000000000..ae8e3412ff4 --- /dev/null +++ b/boards/phytec/phycore_am62x/board.yml @@ -0,0 +1,5 @@ +board: + name: phycore_am62x + vendor: phytec + socs: + - name: am6234 diff --git a/boards/phytec/phycore_am62x/doc/index.rst b/boards/phytec/phycore_am62x/doc/index.rst new file mode 100644 index 00000000000..fd711350fe3 --- /dev/null +++ b/boards/phytec/phycore_am62x/doc/index.rst @@ -0,0 +1,109 @@ +.. _phycore_am62x_a53: + +PHYTEC phyCORE-AM62x (Cortex-A53) +################################# + +Overview +******** + +PHYTEC phyCORE-AM62x board is based on TI Sitara applications +processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. +Zephyr OS is ported to run on the Cortex®-A53 core. + +- Board features: + + - RAM: 2GB DDR4 + - Storage: + + - 16GB eMMC + - 64MB OSPI NOR + - 4KB EEPROM + - Ethernet + +More information about the board can be found at the +`PHYTEC website`_. + +Supported Features +================== + +The Zephyr phycore_am62x_a53 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 200 MHz. + +DDR RAM +------- + +The board has 2GB of DDR RAM available. This board configuration +allocates Zephyr 1MB of RAM (0x82000000 to 0x82100000). + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART0. + +SD Card +******* + +Download PHYTEC's official `WIC`_ and `bmap`_ files and flash the WIC file with +bmap-tools on a SD-card. + +.. code-block:: console + + bmaptool copy phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz /dev/sdX + +Building +******** + +You can build an application in the usual way. Refer to +:ref:`build_an_application` for more details. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :board: phycore_am62x/am6234/a53 + :zephyr-app: samples/hello_world + :goals: build + +Programming +*********** + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin: + +.. code-block:: console + + fatload mmc 1:1 0x82000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x82000000 + + +.. + References + +.. _PHYTEC website: + https://www.phytec.com/product/phycore-am62x/ + +.. _WIC: + https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz + +.. _Bmap: + https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.bmap diff --git a/boards/arm64/phycore_am62x_a53/phycore_am62x_a53.dts b/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53.dts similarity index 100% rename from boards/arm64/phycore_am62x_a53/phycore_am62x_a53.dts rename to boards/phytec/phycore_am62x/phycore_am62x_am6234_a53.dts diff --git a/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53.yaml b/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53.yaml new file mode 100644 index 00000000000..b12e8863b50 --- /dev/null +++ b/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53.yaml @@ -0,0 +1,13 @@ +identifier: phycore_am62x/am6234/a53 +name: PHYTEC phyCORE-AM62x A53 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +testing: + ignore_tags: + - net + - bluetooth +vendor: ti diff --git a/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53_defconfig b/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53_defconfig new file mode 100644 index 00000000000..527a3fc2347 --- /dev/null +++ b/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53_defconfig @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Platform Configuration + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/reel_board/CMakeLists.txt b/boards/phytec/reel_board/CMakeLists.txt similarity index 100% rename from boards/arm/reel_board/CMakeLists.txt rename to boards/phytec/reel_board/CMakeLists.txt diff --git a/boards/phytec/reel_board/Kconfig b/boards/phytec/reel_board/Kconfig new file mode 100644 index 00000000000..7c826262404 --- /dev/null +++ b/boards/phytec/reel_board/Kconfig @@ -0,0 +1,10 @@ +# reel board configuration + +# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_REEL_BOARD diff --git a/boards/phytec/reel_board/Kconfig.defconfig b/boards/phytec/reel_board/Kconfig.defconfig new file mode 100644 index 00000000000..68061a3ef3b --- /dev/null +++ b/boards/phytec/reel_board/Kconfig.defconfig @@ -0,0 +1,40 @@ +# reel board configuration + +# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_REEL_BOARD + +config I2C + default y + +config BT_CTLR + default y + depends on BT + +if FXOS8700 + +choice FXOS8700_MODE + default FXOS8700_MODE_ACCEL +endchoice + +endif # FXOS8700 + +if LVGL + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_1 +endchoice + +config LV_Z_BITS_PER_PIXEL + default 1 + +config LV_DPI_DEF + default 130 + +config LV_Z_VDB_SIZE + default 16 + +endif # LVGL + +endif # BOARD_REEL_BOARD diff --git a/boards/phytec/reel_board/Kconfig.reel_board b/boards/phytec/reel_board/Kconfig.reel_board new file mode 100644 index 00000000000..78eee825ccd --- /dev/null +++ b/boards/phytec/reel_board/Kconfig.reel_board @@ -0,0 +1,7 @@ +# reel board configuration + +# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_REEL_BOARD + select SOC_NRF52840_QIAA diff --git a/boards/arm/reel_board/board.c b/boards/phytec/reel_board/board.c similarity index 100% rename from boards/arm/reel_board/board.c rename to boards/phytec/reel_board/board.c diff --git a/boards/arm/reel_board/board.cmake b/boards/phytec/reel_board/board.cmake similarity index 100% rename from boards/arm/reel_board/board.cmake rename to boards/phytec/reel_board/board.cmake diff --git a/boards/phytec/reel_board/board.yml b/boards/phytec/reel_board/board.yml new file mode 100644 index 00000000000..75878900418 --- /dev/null +++ b/boards/phytec/reel_board/board.yml @@ -0,0 +1,11 @@ +board: + name: reel_board + vendor: phytec + socs: + - name: nrf52840 + revision: + format: number + default: "1" + revisions: + - name: "1" + - name: "2" diff --git a/boards/arm/reel_board/doc/img/link_board_base.jpg b/boards/phytec/reel_board/doc/img/link_board_base.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/link_board_base.jpg rename to boards/phytec/reel_board/doc/img/link_board_base.jpg diff --git a/boards/arm/reel_board/doc/img/rb_lb_shield.jpg b/boards/phytec/reel_board/doc/img/rb_lb_shield.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/rb_lb_shield.jpg rename to boards/phytec/reel_board/doc/img/rb_lb_shield.jpg diff --git a/boards/arm/reel_board/doc/img/reel_board.jpg b/boards/phytec/reel_board/doc/img/reel_board.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/reel_board.jpg rename to boards/phytec/reel_board/doc/img/reel_board.jpg diff --git a/boards/arm/reel_board/doc/img/reel_board_debug.jpg b/boards/phytec/reel_board/doc/img/reel_board_debug.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/reel_board_debug.jpg rename to boards/phytec/reel_board/doc/img/reel_board_debug.jpg diff --git a/boards/arm/reel_board/doc/img/reel_board_descr_back.jpg b/boards/phytec/reel_board/doc/img/reel_board_descr_back.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/reel_board_descr_back.jpg rename to boards/phytec/reel_board/doc/img/reel_board_descr_back.jpg diff --git a/boards/arm/reel_board/doc/img/reel_board_excon.jpg b/boards/phytec/reel_board/doc/img/reel_board_excon.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/reel_board_excon.jpg rename to boards/phytec/reel_board/doc/img/reel_board_excon.jpg diff --git a/boards/arm/reel_board/doc/img/reel_board_tp.jpg b/boards/phytec/reel_board/doc/img/reel_board_tp.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/reel_board_tp.jpg rename to boards/phytec/reel_board/doc/img/reel_board_tp.jpg diff --git a/boards/phytec/reel_board/doc/index.rst b/boards/phytec/reel_board/doc/index.rst new file mode 100644 index 00000000000..79001a009e5 --- /dev/null +++ b/boards/phytec/reel_board/doc/index.rst @@ -0,0 +1,564 @@ +.. _reel_board: + +reel board +########## + +Overview +******** + +`reel board`_ is a evaluation board based on the Nordic Semiconductor +nRF52840 SoC. The board was developed by PHYTEC Messtechnik GmbH in +cooperation with Zephyr Project for the Hackathon - "Get Connected". +The board has a built-in debug adapter based on the DAPLink interface +firmware and NXP MK20DX128VFM5 SoC. + +It is equipped with the Electrophoretic (electronic ink) Display (EPD), +environmental (temperature, humidity, light, accelerometer) sensors, and +Bluetooth connectivity making it easy to experiment and evaluate the +Zephyr OS in these kinds of use cases: + +* battery powered sensor node +* low-power, low-cost human-machine interface (HMI) for remote + control and environmental sensor monitoring +* temperature and humidity monitor on your table +* product, name or price tag +* interactive badge for meetings and conferences + +The board provides support for the Nordic Semiconductor nRF52840 ARM |reg| +Cortex |reg|-M4F SoC with an integrated 2.4 GHz transceiver supporting Bluetooth +|reg| Low Energy and IEEE |reg| 802.15.4. + +The schematic can be found on the `reel board website`_. + +Hardware +******** + +On the front of the board are RGB-LED, ADPS9960 and HDC1010 sensors, +and Electrophoretic Display. +The RGB-LED is controlled by the nRF52840 via GPIO pins. +Display is controlled by the nRF52840 via SPI and 3 GPIOs. + +On the back side of the board are all other components such as nRF52840, +a circuit for the Debug Adapter, On/Off and power source switch, battery holder, +buttons and the MMA8652FC (accelerometer) sensor. + +ADPS9960 is a Digital Proximity, Ambient Light, RGB and Gesture sensor. +HDC1010 is a digital humidity and temperature sensor. +MMA8652FC is a 12-bit Digital Accelerometer. +All sensors are connected to the I2C bus and one GPIO pin each, +which can be used as an interrupt source. + +.. figure:: img/reel_board.jpg + :align: center + :alt: reel board front + + reel board front (Credit: PHYTEC) + +.. figure:: img/reel_board_descr_back.jpg + :align: center + :alt: reel board back + + reel board back (Credit: PHYTEC) + +Since PCB version 1507.2, the nRF52840 SoC is not soldered directly to +the board but integrated as a module on a NOTM.2 adapter. +The wiring is identical for versions 1507.1 and 1507.2. + +.. _reel_board_display: + +Display +======= + +GDEH0213B1 is the display with which the board was introduced +in 2018. Unfortunately, this display has been discontinued. +Currently the board is delivered with the display GDEH0213B72. +It is expected that the display will be replaced over time +due the short product lifecycle of this type of displays. +The following table lists the displays used on the reel board. +The label on the ribbon cable can help to distinguish the displays. +According to the display type, the correct designation must be +used for building an application. + ++--------------+--------------------+----------------------+-------------------+ +| Display | Ribbon Cable Label | Controller / Driver | Board Designation | ++==============+====================+======================+===================+ +| Good Display | HINK-E0213 | SSD1673 / | reel_board | +| GDEH0213B1 | | ssd16xx | | ++--------------+--------------------+----------------------+-------------------+ +| Good Display | HINK-E0213A22 | SSD1675A / | reel_board@2 | +| GDEH0213B72 | | ssd16xx | | ++--------------+--------------------+----------------------+-------------------+ + +Power supply +============ + +The board is optimized for low power applications and supports two +power source configurations, battery and micro USB connector. + +The On/Off switch can choose which power source is used. + +reel board uses a TPS610981 boost converter to generate supply voltage +for nRF52840 and peripherals (sensors and EPD). +The boost converter has two modes: + +* Active mode - supply voltages for nRF52840 and peripherals are on +* Low Power mode - only supply voltage for nRF52840 is on + +The mode is controlled by MODE pin (P1.00). + +.. note:: + Actually there is no possibility to reduce energy consumption by the + Low Power mode. Both voltages are always on, see: + :zephyr_file:`boards/phytec/reel_board/board.c` + +Supported Features +================== + +The reel_board board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| UART | on-chip | serial port | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| SENSOR | off-chip | MMA8652FC polling: | +| | | ADPS9960 polling: | +| | | HDC1010 polling | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +Port P0 +------- + ++-------+----------------------------+---------------------------+ +| Name | Function | Usage | ++=======+============================+===========================+ +| P0.00 | XL1 | 32.768 kHz oscillator | ++-------+----------------------------+---------------------------+ +| P0.01 | XL2 | 32.768 kHz oscillator | ++-------+----------------------------+---------------------------+ +| P0.02 | expansion connector pin 30 | None | ++-------+----------------------------+---------------------------+ +| P0.03 | expansion connector pin 31 | None | ++-------+----------------------------+---------------------------+ +| P0.04 | expansion connector pin 19 | None | ++-------+----------------------------+---------------------------+ +| P0.05 | expansion connector pin 11 | None | ++-------+----------------------------+---------------------------+ +| P0.06 | UART0_TX | UART Console over USB | ++-------+----------------------------+---------------------------+ +| P0.07 | Button | user button (S5) | ++-------+----------------------------+---------------------------+ +| P0.08 | UART0_RX | UART Console over USB | ++-------+----------------------------+---------------------------+ +| P0.09 | expansion connector pin 27 | None | ++-------+----------------------------+---------------------------+ +| P0.10 | expansion connector pin 29 | None | ++-------+----------------------------+---------------------------+ +| P0.11 | RGB LED (red) | GPIO | ++-------+----------------------------+---------------------------+ +| P0.12 | RGB LED (green) | GPIO | ++-------+----------------------------+---------------------------+ +| P0.13 | PWM LED | Buzzer | GPIO | ++-------+----------------------------+---------------------------+ +| P0.14 | EPD Busy output | GPIO | ++-------+----------------------------+---------------------------+ +| P0.15 | EPD Reset input | GPIO | ++-------+----------------------------+---------------------------+ +| P0.16 | EPD DC input | GPIO | ++-------+----------------------------+---------------------------+ +| P0.17 | EPD SPI3_CS | SPI | ++-------+----------------------------+---------------------------+ +| P0.18 | CPU Reset | Reset (S4) | ++-------+----------------------------+---------------------------+ +| P0.19 | EPD SPI3_CLK | SPI | ++-------+----------------------------+---------------------------+ +| P0.20 | EPD SPI3_MOSI | SPI | ++-------+----------------------------+---------------------------+ +| P0.21 | SPI3_MISO | SPI (not connected) | ++-------+----------------------------+---------------------------+ +| P0.22 | HDC1010 DRDYn | GPIO | ++-------+----------------------------+---------------------------+ +| P0.23 | APDS9960 INT | GPIO | ++-------+----------------------------+---------------------------+ +| P0.24 | MMA8652FC INT1 | GPIO | ++-------+----------------------------+---------------------------+ +| P0.25 | MMA8652FC INT2 | GPIO | ++-------+----------------------------+---------------------------+ +| P0.26 | I2C_0 | I2C | ++-------+----------------------------+---------------------------+ +| P0.27 | I2C_0 | I2C | ++-------+----------------------------+---------------------------+ +| P0.28 | expansion connector pin 3 | None | ++-------+----------------------------+---------------------------+ +| P0.29 | expansion connector pin 52 | None | ++-------+----------------------------+---------------------------+ +| P0.30 | expansion connector pin 1 | None | ++-------+----------------------------+---------------------------+ +| P0.31 | expansion connector pin 37 | None | ++-------+----------------------------+---------------------------+ + +Port P1 +------- + ++-------+----------------------------+---------------------------+ +| Name | Function | Usage | ++=======+============================+===========================+ +| P1.00 | peripheral power on | GPIO | ++-------+----------------------------+---------------------------+ +| P1.01 | expansion connector pin 32 | None | ++-------+----------------------------+---------------------------+ +| P1.02 | expansion connector pin 34 | None | ++-------+----------------------------+---------------------------+ +| P1.03 | expansion connector pin 17 | None | ++-------+----------------------------+---------------------------+ +| P1.04 | expansion connector pin 15 | None | ++-------+----------------------------+---------------------------+ +| P1.05 | expansion connector pin 13 | None | ++-------+----------------------------+---------------------------+ +| P1.06 | expansion connector pin 33 | None | ++-------+----------------------------+---------------------------+ +| P1.07 | expansion connector pin 35 | None | ++-------+----------------------------+---------------------------+ +| P1.08 | expansion connector pin 45 | None | ++-------+----------------------------+---------------------------+ +| P1.09 | RGB LED (blue) | GPIO | ++-------+----------------------------+---------------------------+ +| P1.10 | expansion connector pin 47 | None | ++-------+----------------------------+---------------------------+ +| P1.11 | expansion connector pin 49 | None | ++-------+----------------------------+---------------------------+ +| P1.12 | expansion connector pin 51 | None | ++-------+----------------------------+---------------------------+ +| P1.13 | expansion connector pin 36 | None | ++-------+----------------------------+---------------------------+ +| P1.14 | expansion connector pin 48 | None | ++-------+----------------------------+---------------------------+ +| P1.15 | expansion connector pin 50 | None | ++-------+----------------------------+---------------------------+ + +Solder Jumper and Testpoints +============================ + +There are several labeled solder jumpers on the board. +These can be used to connect a logic analyzer to check the behavior of a +driver or to measure the voltage of a signal. + +.. figure:: img/reel_board_tp.jpg + :align: center + :alt: reel board Jumper and Testpoints + + reel board testpoints (Credit: PHYTEC) + +I2C bus and sensors testpoints +------------------------------ + ++-------+-----------------------+---------------------------+ +| Name | Type | Usage | ++=======+=======================+===========================+ +| J19 | closed solder jumper | testpoint I2C SDA | ++-------+-----------------------+---------------------------+ +| J20 | closed solder jumper | testpoint I2C SCL | ++-------+-----------------------+---------------------------+ +| J7 | closed solder jumper | testpoint INT1 MMA8652FC | ++-------+-----------------------+---------------------------+ +| J24 | closed solder jumper | testpoint INT2 MMA8652FC | ++-------+-----------------------+---------------------------+ +| J11 | closed solder jumper | testpoint INT APDS9960 | ++-------+-----------------------+---------------------------+ +| J12 | closed solder jumper | testpoint DRDYn HDC1010 | ++-------+-----------------------+---------------------------+ + +EPD testpoints +-------------- + ++-------+-----------------------+---------------------------+ +| Name | Type | Usage | ++=======+=======================+===========================+ +| J13 | closed solder jumper | testpoint EPD Busy | ++-------+-----------------------+---------------------------+ +| J14 | closed solder jumper | testpoint EPD Reset | ++-------+-----------------------+---------------------------+ +| J15 | closed solder jumper | testpoint EPD DC | ++-------+-----------------------+---------------------------+ +| J16 | closed solder jumper | testpoint EPD SPI_CS | ++-------+-----------------------+---------------------------+ +| J17 | closed solder jumper | testpoint EPD SPI_CLK | ++-------+-----------------------+---------------------------+ +| J18 | closed solder jumper | testpoint EPD SPI_MOSI | ++-------+-----------------------+---------------------------+ + +Power supply testpoint +---------------------- + ++-------+-----------------------+-------------------------------------------+ +| Name | Type | Usage | ++=======+=======================+===========================================+ +| J21 | closed solder jumper | testpoint peripheral voltage on/off | ++-------+-----------------------+-------------------------------------------+ +| TP11 | testpoint | testpoint peripheral voltage | ++-------+-----------------------+-------------------------------------------+ +| TP12 | testpoint | testpoint nRF52840 supply voltage VDD_nRF | ++-------+-----------------------+-------------------------------------------+ +| TP13 | testpoint | testpoint boost converter input voltage | ++-------+-----------------------+-------------------------------------------+ + +Built-in Debug Adapter +====================== + +The debug adapter is based on the DAPLink interface firmware and +NXP MK20DX128VFM5 SoC. The adapter is powered via a micro USB connector and +is always on when the board is connected to the USB host. +reel board can be flashed and debugged, powered either from battery or USB. +If the Adapter is powered via USB, the Adapter circuit heats the board +slightly and the temperature sensor can output values up to 1.5 degrees higher. + +.. figure:: img/reel_board_debug.jpg + :align: center + :alt: reel board Debug Adapter + + reel board Debug Adapter overview (Credit: PHYTEC) + +Debug Adapter Firmware +---------------------- + +DAPLink firmware for the adapter can be found at `DAPLink reel board Firmware`_. +To update the firmware (if necessary), the adapter must be started in bootloader +mode. For this, the board should be disconnected from the USB host, +the J22 should be closed (use tweezers for this) and the board reconnected to +the USB host. + +Debug Adapter Jumper +-------------------- + ++-------+-----------------------+----------------------------------------------+ +| Name | Type | Usage | ++=======+=======================+==============================================+ +| J3 | open solder jumper | close to pass UART TX to external adapter | ++-------+-----------------------+----------------------------------------------+ +| J4 | open solder jumper | close to pass UART RX to external adapter | ++-------+-----------------------+----------------------------------------------+ +| J22 | open solder jumper | close to start adapter in bootloader mode | ++-------+-----------------------+----------------------------------------------+ + +Adapter LEDs +------------ + ++-------+-----------------------+--------------------------------+ +| Name | Type | Usage | ++=======+=======================+================================+ +| D11 | green | flashes when adapter is active | ++-------+-----------------------+--------------------------------+ +| D14 | red | reserved | ++-------+-----------------------+--------------------------------+ +| D15 | yellow | reserved | ++-------+-----------------------+--------------------------------+ + +Expansion Connector +************************ + +The expansion connector has the same dimensions and similar pinout +as the BBC MicroBit edge connector. The expansion components that are +designed especially for the reel board are called link boards. + +.. figure:: img/reel_board_excon.jpg + :align: center + :alt: reel board Expansion Connector + + reel board Expansion Connector (Credit: PHYTEC) + +link board BASE +=============== + +link board BASE is a passive expansion board and allows other link boards or +third party shields in Arduino UNO R3 format to be connected to the reel board. +In addition, it includes a NOTM.2 connector and more powerful DCDC converter +then reel board. + +.. figure:: img/rb_lb_shield.jpg + :align: center + :alt: reel board and link board BASE + + reel board and link board BASE (Credit: PHYTEC) + +link board BASE can be used in combination with other link boards or +third party shields in two ways: + + As an adapter + reel board is plugged into the link board BASE. Both peripherals on + reel board and shields can be used as long as there is no conflict + between I2C devices. Care should be taken to provide enough power + to the complete circuit. + + Stand-alone + NOTM.2 adapter is removed from the reel board and + connected to NOTM.2 connector on the link board BASE. + The wiring to the shield connector is identical to the + configuration above and no software modifications for the shield + are necessary. + Stand-alone configuration is more suitable for applications where + peripherals on the reel board are not used or in conflict, + power provided by the reel board is not enough, + or for prototypes in the field. + +.. figure:: img/link_board_base.jpg + :align: center + :alt: link board BASE + + link board BASE (Credit: PHYTEC) + +Components on the link board BASE: + + reel board Connector: + 2x40 position edge connector. + + Micro USB Connector: + USB can be used as power source. USB data lines are wired + to NOTM.2 connector. + + NOTM.2 Connector: + Connector for NOTM.2 adapter. If the connector is used then + reel board should be removed from reel board connector. + + SWD Connector X11: + Wired to NOTM.2 connector. A debug probe can + be connected to program or debug MCU in Stand-alone configuration. + + Alternative Power Source X5 or X9: + Positive pin is closer to the + character. Nominal voltage is + 3.3V, there is no protection against reverse polarity or overvoltage. + Use it with care. + + Shield Connector: + Connector for link boards and third party shields in Arduino UNO R3 + format. Only shields designed for 3.3V supply voltage are supported. + +Meaning of the Power Source Switch positions: + + EXT + link board BASE is powered from Alternative Power Source Connector + X9 or X5. + + USB + link board BASE is powered from USB connector (via DCDC converter). + + RB + link board BASE is powered from reel board. The available power is + below 0.3W and depends on which source is used to power the reel board. + +Programming and Debugging +************************* + +Applications for the ``reel_board`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + +Flashing +======== + +If you use Linux, create a udev rule (as ``root``) to fix a permission issue +when not using root for flashing. + +.. code-block:: console + + # echo 'ATTR{idProduct}=="0204", ATTR{idVendor}=="0d28", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-cmsis-dap.rules + +Reload the rules and replug the device. + +.. code-block:: console + + $ sudo udevadm control --reload-rules + +Finally, unplug and plug the board again for the rules to take effect. + +Build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the reel board +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: reel_board + :goals: build flash + +.. note:: + Please use reel_board@2 to build a application for the board equipped with + the GDEH0213B72, see :ref:`reel_board_display`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: reel_board@2 + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: reel_board + :maybe-skip-config: + :goals: debug + + +Testing the LEDs and buttons +**************************** + +There are 2 samples that allow you to test that the buttons (switches) and +LEDs on the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. + +References +********** + +.. _reel board Website: + https://www.phytec.de/reelboard/ + +.. target-notes:: + +.. _reel board: + https://www.phytec.de/reelboard/ + +.. _DAPLink reel board Firmware: + https://github.com/PHYTEC-Messtechnik-GmbH/DAPLink/tree/reel-board diff --git a/boards/arm/reel_board/dts/reel_board-pinctrl.dtsi b/boards/phytec/reel_board/dts/reel_board-pinctrl.dtsi similarity index 100% rename from boards/arm/reel_board/dts/reel_board-pinctrl.dtsi rename to boards/phytec/reel_board/dts/reel_board-pinctrl.dtsi diff --git a/boards/arm/reel_board/dts/reel_board.dtsi b/boards/phytec/reel_board/dts/reel_board.dtsi similarity index 100% rename from boards/arm/reel_board/dts/reel_board.dtsi rename to boards/phytec/reel_board/dts/reel_board.dtsi diff --git a/boards/arm/particle_boron/pre_dt_board.cmake b/boards/phytec/reel_board/pre_dt_board.cmake similarity index 100% rename from boards/arm/particle_boron/pre_dt_board.cmake rename to boards/phytec/reel_board/pre_dt_board.cmake diff --git a/boards/arm/reel_board/reel_board-pinctrl.dtsi b/boards/phytec/reel_board/reel_board-pinctrl.dtsi similarity index 100% rename from boards/arm/reel_board/reel_board-pinctrl.dtsi rename to boards/phytec/reel_board/reel_board-pinctrl.dtsi diff --git a/boards/arm/reel_board/reel_board.dts b/boards/phytec/reel_board/reel_board.dts similarity index 100% rename from boards/arm/reel_board/reel_board.dts rename to boards/phytec/reel_board/reel_board.dts diff --git a/boards/arm/reel_board/reel_board.yaml b/boards/phytec/reel_board/reel_board_1.yaml similarity index 100% rename from boards/arm/reel_board/reel_board.yaml rename to boards/phytec/reel_board/reel_board_1.yaml diff --git a/boards/phytec/reel_board/reel_board_defconfig b/boards/phytec/reel_board/reel_board_defconfig new file mode 100644 index 00000000000..7167aca850a --- /dev/null +++ b/boards/phytec/reel_board/reel_board_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/reel_board/reel_board_v2-pinctrl.dtsi b/boards/phytec/reel_board/reel_board_nrf52840_2-pinctrl.dtsi similarity index 100% rename from boards/arm/reel_board/reel_board_v2-pinctrl.dtsi rename to boards/phytec/reel_board/reel_board_nrf52840_2-pinctrl.dtsi diff --git a/boards/phytec/reel_board/reel_board_nrf52840_2.overlay b/boards/phytec/reel_board/reel_board_nrf52840_2.overlay new file mode 100644 index 00000000000..b6652cbf4e8 --- /dev/null +++ b/boards/phytec/reel_board/reel_board_nrf52840_2.overlay @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH + * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "reel_board_nrf52840_2-pinctrl.dtsi" + +/ { + model = "reel board v2"; + compatible = "phytec,reel_board_v2"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,display = &ssd16xx; + }; + + aliases { + watchdog0 = &wdt0; + }; +}; + +&spi1 { + compatible = "nordic,nrf-spi"; + status = "okay"; + cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + pinctrl-names = "default", "sleep"; + ssd16xx: ssd16xxfb@0 { + compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a"; + spi-max-frequency = <4000000>; + reg = <0>; + width = <250>; + height = <122>; + reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + busy-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + + full { + gdv = [15]; + sdv = [41 a8 32]; + vcom = <0x26>; + border-waveform = <0x03>; + dummy-line = <0x30>; + gate-line-width = <0x0a>; + lut = [ + /* + * Waveform Composition + * + * There are 7 Voltage Source (VS) Level groups + * n = {0,1,2...6}, each group contains + * 4 phases x = {A,B,C,D}. + * 2 bits represent the voltage in a phase: + * 00 – VSS, 01 – VSH1, 10 – VSL, 11 - VSH2 + * + * For example 0x80 represents sequence VSL-VSS-VSS-VSS, + */ + 80 60 40 00 00 00 00 /* LUT0: BB: VS 0..6 */ + 10 60 20 00 00 00 00 /* LUT1: BW: VS 0..6 */ + 80 60 40 00 00 00 00 /* LUT2: WB: VS 0..6 */ + 10 60 20 00 00 00 00 /* LUT3: WW: VS 0..6 */ + 00 00 00 00 00 00 00 /* LUT4: VCOM: VS 0..6 */ + /* + * TPnx determines the length of each phase, + * and RPn repeat count of a sequence. + * TPnA, TPnB, TPnC, TPnD, RPn + * + * For example TP0A=3, TP0B=3, and RP0=2: + * VS sequence : VSL-VSS-VSS-VSS + * number of Gate Pulses (length) : 3 3 0 0 + * repeat count : 2 + */ + 03 03 00 00 02 /* TP0A TP0B TP0C TP0D RP0 */ + 09 09 00 00 02 /* TP1A TP1B TP1C TP1D RP1 */ + 03 03 00 00 02 /* TP2A TP2B TP2C TP2D RP2 */ + 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ + 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ + 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ + 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ + ]; + }; + + partial { + gdv = [15]; + sdv = [41 a8 32]; + vcom = <0x26>; + border-waveform = <0x01>; + dummy-line = <0x30>; + gate-line-width = <0x0a>; + lut = [ + 00 00 00 00 00 00 00 /* LUT0: BB: VS0..6 */ + 80 00 00 00 00 00 00 /* LUT1: BW: VS0..6 */ + 40 00 00 00 00 00 00 /* LUT2: WB: VS0..6 */ + 80 00 00 00 00 00 00 /* LUT3: WW: VS0..6 */ + 00 00 00 00 00 00 00 /* LUT4: VCOM: VS0..6 */ + 0A 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */ + 00 00 00 00 00 /* TP1A TP1B TP1C TP1D RP1 */ + 00 00 00 00 00 /* TP2A TP2B TP2C TP2D RP2 */ + 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ + 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ + 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ + 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ + ]; + }; + }; +}; diff --git a/boards/phytec/reel_board/reel_board_nrf52840_2.yaml b/boards/phytec/reel_board/reel_board_nrf52840_2.yaml new file mode 100644 index 00000000000..dc6361d4f50 --- /dev/null +++ b/boards/phytec/reel_board/reel_board_nrf52840_2.yaml @@ -0,0 +1,22 @@ +identifier: reel_board@2 +name: reel-board +type: mcu +arch: arm +ram: 512 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - i2c + - spi + - gpio + - usb_device + - usb_cdc + - ble + - pwm + - arduino_i2c + - arduino_spi + - arduino_gpio +vendor: phytec diff --git a/boards/arm/reel_board/support/pyocd.yaml b/boards/phytec/reel_board/support/pyocd.yaml similarity index 100% rename from boards/arm/reel_board/support/pyocd.yaml rename to boards/phytec/reel_board/support/pyocd.yaml diff --git a/boards/pine64/index.rst b/boards/pine64/index.rst new file mode 100644 index 00000000000..2be21aa3a12 --- /dev/null +++ b/boards/pine64/index.rst @@ -0,0 +1,10 @@ +.. _boards-pine64: + +Pine64 +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/pine64/pinetime_devkit0/Kconfig.defconfig b/boards/pine64/pinetime_devkit0/Kconfig.defconfig new file mode 100644 index 00000000000..adfebb274d9 --- /dev/null +++ b/boards/pine64/pinetime_devkit0/Kconfig.defconfig @@ -0,0 +1,21 @@ +# PineTime DevKit0 board configuration + +# Copyright (c) 2020 Stephane Dorre +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PINETIME_DEVKIT0 + +config BT_CTLR + default BT + +config INPUT + default y if LVGL + +if FLASH + +config SPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 + +endif # FLASH + +endif # BOARD_PINETIME_DEVKIT0 diff --git a/boards/pine64/pinetime_devkit0/Kconfig.pinetime_devkit0 b/boards/pine64/pinetime_devkit0/Kconfig.pinetime_devkit0 new file mode 100644 index 00000000000..e2a5705c171 --- /dev/null +++ b/boards/pine64/pinetime_devkit0/Kconfig.pinetime_devkit0 @@ -0,0 +1,7 @@ +# PineTime DevKit0 board configuration + +# Copyright (c) 2020 Stephane Dorre +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PINETIME_DEVKIT0 + select SOC_NRF52832_QFAA diff --git a/boards/arm/pinetime_devkit0/board.cmake b/boards/pine64/pinetime_devkit0/board.cmake similarity index 100% rename from boards/arm/pinetime_devkit0/board.cmake rename to boards/pine64/pinetime_devkit0/board.cmake diff --git a/boards/pine64/pinetime_devkit0/board.yml b/boards/pine64/pinetime_devkit0/board.yml new file mode 100644 index 00000000000..e4c926cf96b --- /dev/null +++ b/boards/pine64/pinetime_devkit0/board.yml @@ -0,0 +1,5 @@ +board: + name: pinetime_devkit0 + vendor: pine64 + socs: + - name: nrf52832 diff --git a/boards/arm/pinetime_devkit0/doc/img/PineTime_DevKit0.jpg b/boards/pine64/pinetime_devkit0/doc/img/PineTime_DevKit0.jpg similarity index 100% rename from boards/arm/pinetime_devkit0/doc/img/PineTime_DevKit0.jpg rename to boards/pine64/pinetime_devkit0/doc/img/PineTime_DevKit0.jpg diff --git a/boards/arm/pinetime_devkit0/doc/img/PineTime_SWD_location.jpg b/boards/pine64/pinetime_devkit0/doc/img/PineTime_SWD_location.jpg similarity index 100% rename from boards/arm/pinetime_devkit0/doc/img/PineTime_SWD_location.jpg rename to boards/pine64/pinetime_devkit0/doc/img/PineTime_SWD_location.jpg diff --git a/boards/arm/pinetime_devkit0/doc/img/PineTime_leaflet.jpg b/boards/pine64/pinetime_devkit0/doc/img/PineTime_leaflet.jpg similarity index 100% rename from boards/arm/pinetime_devkit0/doc/img/PineTime_leaflet.jpg rename to boards/pine64/pinetime_devkit0/doc/img/PineTime_leaflet.jpg diff --git a/boards/arm/pinetime_devkit0/doc/index.rst b/boards/pine64/pinetime_devkit0/doc/index.rst similarity index 100% rename from boards/arm/pinetime_devkit0/doc/index.rst rename to boards/pine64/pinetime_devkit0/doc/index.rst diff --git a/boards/arm/pinetime_devkit0/pinetime_devkit0-pinctrl.dtsi b/boards/pine64/pinetime_devkit0/pinetime_devkit0-pinctrl.dtsi similarity index 100% rename from boards/arm/pinetime_devkit0/pinetime_devkit0-pinctrl.dtsi rename to boards/pine64/pinetime_devkit0/pinetime_devkit0-pinctrl.dtsi diff --git a/boards/arm/pinetime_devkit0/pinetime_devkit0.dts b/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts similarity index 100% rename from boards/arm/pinetime_devkit0/pinetime_devkit0.dts rename to boards/pine64/pinetime_devkit0/pinetime_devkit0.dts diff --git a/boards/arm/pinetime_devkit0/pinetime_devkit0.yaml b/boards/pine64/pinetime_devkit0/pinetime_devkit0.yaml similarity index 100% rename from boards/arm/pinetime_devkit0/pinetime_devkit0.yaml rename to boards/pine64/pinetime_devkit0/pinetime_devkit0.yaml diff --git a/boards/pine64/pinetime_devkit0/pinetime_devkit0_defconfig b/boards/pine64/pinetime_devkit0/pinetime_devkit0_defconfig new file mode 100644 index 00000000000..353082fbb63 --- /dev/null +++ b/boards/pine64/pinetime_devkit0/pinetime_devkit0_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/particle_xenon/pre_dt_board.cmake b/boards/pine64/pinetime_devkit0/pre_dt_board.cmake similarity index 100% rename from boards/arm/particle_xenon/pre_dt_board.cmake rename to boards/pine64/pinetime_devkit0/pre_dt_board.cmake diff --git a/boards/pjrc/index.rst b/boards/pjrc/index.rst new file mode 100644 index 00000000000..9a8e66fea3f --- /dev/null +++ b/boards/pjrc/index.rst @@ -0,0 +1,10 @@ +.. _boards-pjrc: + +PJRC +#### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/pjrc/teensy4/CMakeLists.txt b/boards/pjrc/teensy4/CMakeLists.txt new file mode 100644 index 00000000000..7b0c243fbbb --- /dev/null +++ b/boards/pjrc/teensy4/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (c) 2020, Bernhard Kraemer +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(flexspi_nor_config.c) + zephyr_library_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA teensy4_sdram_ini_dcd.c) +endif() diff --git a/boards/pjrc/teensy4/Kconfig.defconfig b/boards/pjrc/teensy4/Kconfig.defconfig new file mode 100644 index 00000000000..4bdd626e94a --- /dev/null +++ b/boards/pjrc/teensy4/Kconfig.defconfig @@ -0,0 +1,16 @@ +# +# Copyright (c) 2020, Bernhard Kraemer +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_TEENSY40 || BOARD_TEENSY41 + +config BUILD_OUTPUT_HEX + bool + default y + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_TEENSY40 || BOARD_TEENSY41 diff --git a/boards/pjrc/teensy4/Kconfig.teensy40 b/boards/pjrc/teensy4/Kconfig.teensy40 new file mode 100644 index 00000000000..bcc62d6bb42 --- /dev/null +++ b/boards/pjrc/teensy4/Kconfig.teensy40 @@ -0,0 +1,9 @@ +# +# Copyright (c) 2020, Bernhard Kraemer +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_TEENSY40 + select SOC_PART_NUMBER_MIMXRT1062DVJ6A diff --git a/boards/pjrc/teensy4/Kconfig.teensy41 b/boards/pjrc/teensy4/Kconfig.teensy41 new file mode 100644 index 00000000000..d66c5f979a0 --- /dev/null +++ b/boards/pjrc/teensy4/Kconfig.teensy41 @@ -0,0 +1,9 @@ +# +# Copyright (c) 2020, Bernhard Kraemer +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_TEENSY41 + select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/pjrc/teensy4/board.yml b/boards/pjrc/teensy4/board.yml new file mode 100644 index 00000000000..7906ae3b823 --- /dev/null +++ b/boards/pjrc/teensy4/board.yml @@ -0,0 +1,9 @@ +boards: + - name: teensy40 + vendor: pjrc + socs: + - name: mimxrt1062 + - name: teensy41 + vendor: pjrc + socs: + - name: mimxrt1062 diff --git a/boards/arm/teensy4/doc/index.rst b/boards/pjrc/teensy4/doc/index.rst similarity index 100% rename from boards/arm/teensy4/doc/index.rst rename to boards/pjrc/teensy4/doc/index.rst diff --git a/boards/arm/teensy4/doc/teensy40.jpg b/boards/pjrc/teensy4/doc/teensy40.jpg similarity index 100% rename from boards/arm/teensy4/doc/teensy40.jpg rename to boards/pjrc/teensy4/doc/teensy40.jpg diff --git a/boards/arm/teensy4/doc/teensy41.jpg b/boards/pjrc/teensy4/doc/teensy41.jpg similarity index 100% rename from boards/arm/teensy4/doc/teensy41.jpg rename to boards/pjrc/teensy4/doc/teensy41.jpg diff --git a/boards/pjrc/teensy4/flexspi_nor_config.c b/boards/pjrc/teensy4/flexspi_nor_config.c new file mode 100644 index 00000000000..020bf6abd57 --- /dev/null +++ b/boards/pjrc/teensy4/flexspi_nor_config.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019, MADMACHINE LIMITED + * Copyright (c) 2021, Bernhard Kraemer + * + * refer to hal_nxp board file + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const struct flexspi_nor_config_t Qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = { + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, + 0x06, READ_SDR, + FLEXSPI_4PAD, 0x04), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ diff --git a/boards/arm/teensy4/teensy4-pinctrl.dtsi b/boards/pjrc/teensy4/teensy4-pinctrl.dtsi similarity index 100% rename from boards/arm/teensy4/teensy4-pinctrl.dtsi rename to boards/pjrc/teensy4/teensy4-pinctrl.dtsi diff --git a/boards/arm/teensy4/teensy40.dts b/boards/pjrc/teensy4/teensy40.dts similarity index 100% rename from boards/arm/teensy4/teensy40.dts rename to boards/pjrc/teensy4/teensy40.dts diff --git a/boards/arm/teensy4/teensy40.yaml b/boards/pjrc/teensy4/teensy40.yaml similarity index 100% rename from boards/arm/teensy4/teensy40.yaml rename to boards/pjrc/teensy4/teensy40.yaml diff --git a/boards/arm/teensy4/teensy40_defconfig b/boards/pjrc/teensy4/teensy40_defconfig similarity index 79% rename from boards/arm/teensy4/teensy40_defconfig rename to boards/pjrc/teensy4/teensy40_defconfig index 89b2890fbe2..1d186d986c4 100644 --- a/boards/arm/teensy4/teensy40_defconfig +++ b/boards/pjrc/teensy4/teensy40_defconfig @@ -4,10 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_DEVICE_CONFIGURATION_DATA=n -CONFIG_BOARD_TEENSY40=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/teensy4/teensy41.dts b/boards/pjrc/teensy4/teensy41.dts similarity index 100% rename from boards/arm/teensy4/teensy41.dts rename to boards/pjrc/teensy4/teensy41.dts diff --git a/boards/arm/teensy4/teensy41.yaml b/boards/pjrc/teensy4/teensy41.yaml similarity index 100% rename from boards/arm/teensy4/teensy41.yaml rename to boards/pjrc/teensy4/teensy41.yaml diff --git a/boards/arm/teensy4/teensy41_defconfig b/boards/pjrc/teensy4/teensy41_defconfig similarity index 79% rename from boards/arm/teensy4/teensy41_defconfig rename to boards/pjrc/teensy4/teensy41_defconfig index 018d31d009e..1d186d986c4 100644 --- a/boards/arm/teensy4/teensy41_defconfig +++ b/boards/pjrc/teensy4/teensy41_defconfig @@ -4,10 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_DEVICE_CONFIGURATION_DATA=n -CONFIG_BOARD_TEENSY41=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/posix/native_posix/CMakeLists.txt b/boards/posix/native_posix/CMakeLists.txt deleted file mode 100644 index 20210a46a81..00000000000 --- a/boards/posix/native_posix/CMakeLists.txt +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_compile_definitions(NO_POSIX_CHEATS) -zephyr_library_compile_definitions(_POSIX_C_SOURCE=200809L _XOPEN_SOURCE=600 _XOPEN_SOURCE_EXTENDED) - -zephyr_library_sources( - hw_models_top.c - timer_model.c - native_rtc.c - irq_handler.c - irq_ctrl.c - main.c - tracing.c - cmdline_common.c - cmdline.c - cpu_wait.c - hw_counter.c - ) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/posix/include - ) - -if(CONFIG_HAS_SDL) - add_subdirectory(${ZEPHYR_BASE}/boards/${ARCH}/common/sdl/ ${CMAKE_CURRENT_BINARY_DIR}/sdl) -endif() - -zephyr_ld_options( - -lm -) diff --git a/boards/posix/native_posix/Kconfig b/boards/posix/native_posix/Kconfig deleted file mode 100644 index 42a77bdf6c7..00000000000 --- a/boards/posix/native_posix/Kconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_POSIX - bool - imply NATIVE_POSIX_TIMER - select POSIX_ARCH_CONSOLE - select NATIVE_APPLICATION - -if BOARD_NATIVE_POSIX - -comment "Native POSIX options" - -config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME - bool "Slow down execution to real time" - default n if ARCH_POSIX_LIBFUZZER - default y if BT_USERCHAN || !TEST - help - When selected the execution of the process will be slowed down to real time. - (if there is a lot of load it may be slower than real time) - If deselected, the process will run as fast as possible. - Note that this only decouples simulated time from real/wall time. In either - case the zephyr kernel and application cannot tell the difference unless they - interact with some other driver/device which runs at real time. - -source "boards/$(ARCH)/common/sdl/Kconfig" - -endif # BOARD_NATIVE_POSIX diff --git a/boards/posix/native_posix/Kconfig.board b/boards/posix/native_posix/Kconfig.board deleted file mode 100644 index 4367cd50631..00000000000 --- a/boards/posix/native_posix/Kconfig.board +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_POSIX_32BIT - bool "Native POSIX for 32-bit host" - depends on SOC_POSIX - select BOARD_NATIVE_POSIX - help - Will produce a console Linux process which can be executed natively - as a 32-bit executable. - It provides some minimal needed models: - An interrupt controller, timer (system tick), and redirects kernel prints to - stdout. - -config BOARD_NATIVE_POSIX_64BIT - bool "Native POSIX for 64-bit host" - depends on SOC_POSIX - select BOARD_NATIVE_POSIX - select 64BIT - help - Will produce a console Linux process which can be executed natively - as a 64-bit executable. - It provides some minimal needed models: - An interrupt controller, timer (system tick), and redirects kernel prints to - stdout. diff --git a/boards/posix/native_posix/Kconfig.defconfig b/boards/posix/native_posix/Kconfig.defconfig deleted file mode 100644 index 985e6661847..00000000000 --- a/boards/posix/native_posix/Kconfig.defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NATIVE_POSIX - -config BUILD_OUTPUT_BIN - default n - -config BUILD_OUTPUT_EXE - default y - -config OUTPUT_PRINT_MEMORY_USAGE - default n - -config BOARD - default "native_posix_64" if BOARD_NATIVE_POSIX_64BIT - default "native_posix" - -if NETWORKING - -config NET_L2_ETHERNET - default y if !NET_LOOPBACK && !NET_TEST - -config ETH_NATIVE_POSIX - default y if NET_L2_ETHERNET && ETH_DRIVER - -endif # NETWORKING - -choice BT_HCI_BUS_TYPE - default BT_USERCHAN - depends on BT_HCI -endchoice - -if LOG - -# For native_posix we can log synchronously without any problem -# Doing so will be nicer for debugging -choice LOG_MODE - default LOG_MODE_IMMEDIATE -endchoice - -endif # LOG - -if CONSOLE - -config POSIX_ARCH_CONSOLE - default y if !SERIAL - -config UART_CONSOLE - default y if SERIAL - -endif # CONSOLE - -config FLASH_SIMULATOR - default y - depends on FLASH - -config USB_NATIVE_POSIX - default y - depends on USB_DEVICE_DRIVER - -config EEPROM_SIMULATOR - default y - depends on EEPROM - -if I2C - -config EMUL - default y - -endif # I2C - -endif # BOARD_NATIVE_POSIX diff --git a/boards/posix/native_posix/native_posix_64_defconfig b/boards/posix/native_posix/native_posix_64_defconfig deleted file mode 100644 index 5ccadf2bc6a..00000000000 --- a/boards/posix/native_posix/native_posix_64_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NATIVE_POSIX_64BIT=y -CONFIG_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/native_posix/native_posix_defconfig b/boards/posix/native_posix/native_posix_defconfig deleted file mode 100644 index ee7f4b92eda..00000000000 --- a/boards/posix/native_posix/native_posix_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NATIVE_POSIX_32BIT=y -CONFIG_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/native_sim/CMakeLists.txt b/boards/posix/native_sim/CMakeLists.txt deleted file mode 100644 index 5ddf0e5f143..00000000000 --- a/boards/posix/native_sim/CMakeLists.txt +++ /dev/null @@ -1,39 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_compile_definitions(NO_POSIX_CHEATS) - -zephyr_library_sources( - cmdline.c - cpu_wait.c - nsi_if.c - irq_handler.c - misc.c - posix_arch_if.c - ) - -zephyr_include_directories( - ${NSI_DIR}/common/src/include - ${NSI_DIR}/native/src/include -) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/posix/include -) - -if(CONFIG_HAS_SDL) - add_subdirectory(${ZEPHYR_BASE}/boards/${ARCH}/common/sdl/ ${CMAKE_CURRENT_BINARY_DIR}/sdl) -endif() - -add_subdirectory(${ZEPHYR_BASE}/boards/${ARCH}/common/extra_args/ - ${CMAKE_CURRENT_BINARY_DIR}/extra_args -) - -set(nsi_config_content - ${nsi_config_content} - "NSI_NATIVE=1" -) - -include(../common/natsim_config.cmake) diff --git a/boards/posix/native_sim/Kconfig b/boards/posix/native_sim/Kconfig deleted file mode 100644 index ddf76a5f157..00000000000 --- a/boards/posix/native_sim/Kconfig +++ /dev/null @@ -1,51 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_SIM - bool "Native simulator (Single Core)" - select POSIX_ARCH_CONSOLE - select NATIVE_LIBRARY - select NATIVE_POSIX_TIMER - depends on SOC_POSIX - imply BOARD_NATIVE_POSIX if NATIVE_SIM_NATIVE_POSIX_COMPAT - -if BOARD_NATIVE_SIM - -comment "Native Simular (Single Core) options" - -config NATIVE_SIM_NATIVE_POSIX_COMPAT - bool "Pretend to be a native_posix board" - default y - help - When this option is set the native_sim board will pretend to be - a native_posix board from kconfig point of view, to allow using it directly with - code which was meant for the native_posix board and checks for the macro - CONFIG_BOARD_NATIVE_POSIX, or requires other kconfig options which depend on it. - -config NATIVE_SIM_SLOWDOWN_TO_REAL_TIME - bool "Slow down execution to real time" - default n if ARCH_POSIX_LIBFUZZER - default y if BT_USERCHAN || !TEST - help - When selected the execution of the process will be slowed down to real time. - (if there is a lot of load it may be slower than real time) - If deselected, the process will run as fast as possible. - Note that this only decouples simulated time from real/wall time. In either - case the zephyr kernel and application cannot tell the difference unless they - interact with some other driver/device which runs at real time. - -# This option definition exists only to enable NATIVE_SIM_NATIVE_POSIX_COMPAT -config BOARD_NATIVE_POSIX - bool - -config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME - bool "Slow down execution to real time (native_posix compat)" - select NATIVE_SIM_SLOWDOWN_TO_REAL_TIME - help - Transitional option which allows applications which targeted native_posix - to set the correct native_sim option (CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME) - -source "boards/$(ARCH)/common/sdl/Kconfig" -source "boards/$(ARCH)/common/extra_args/Kconfig" - -endif # BOARD_NATIVE_SIM diff --git a/boards/posix/native_sim/Kconfig.board b/boards/posix/native_sim/Kconfig.board deleted file mode 100644 index 7cc9ead031f..00000000000 --- a/boards/posix/native_sim/Kconfig.board +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_SIM_32BIT - bool "Native simulation, 32-bit mode" - select BOARD_NATIVE_SIM - help - Will produce a console Linux process which can be executed natively - as a 32-bit executable. - -config BOARD_NATIVE_SIM_64BIT - bool "Native simulation, 64-bit mode" - select BOARD_NATIVE_SIM - select 64BIT - help - Will produce a console Linux process which can be executed natively - as a 64-bit executable. diff --git a/boards/posix/native_sim/Kconfig.defconfig b/boards/posix/native_sim/Kconfig.defconfig deleted file mode 100644 index c4bcb6184a3..00000000000 --- a/boards/posix/native_sim/Kconfig.defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NATIVE_SIM - -config BUILD_OUTPUT_BIN - default n - -config BUILD_OUTPUT_EXE - default y - -config OUTPUT_PRINT_MEMORY_USAGE - default n - -config BOARD - default "native_sim_64" if BOARD_NATIVE_SIM_64BIT - default "native_sim" - -if NETWORKING - -config NET_L2_ETHERNET - default y if !NET_LOOPBACK && !NET_TEST - -config ETH_NATIVE_POSIX - default y if NET_L2_ETHERNET && ETH_DRIVER - -endif # NETWORKING - -choice BT_HCI_BUS_TYPE - default BT_USERCHAN - depends on BT_HCI -endchoice - -if LOG - -# For native_sim we can log synchronously without any problem -# Doing so will be nicer for debugging -choice LOG_MODE - default LOG_MODE_IMMEDIATE -endchoice - -endif # LOG - -if CONSOLE - -config POSIX_ARCH_CONSOLE - default y if !SERIAL - -config UART_CONSOLE - default y if SERIAL - -endif # CONSOLE - -config FLASH_SIMULATOR - default y - depends on FLASH - -config USB_NATIVE_POSIX - default y - depends on USB_DEVICE_DRIVER - -config EEPROM_SIMULATOR - default y - depends on EEPROM - -if I2C - -config EMUL - default y - -endif # I2C - -endif # BOARD_NATIVE_SIM diff --git a/boards/posix/native_sim/board.cmake b/boards/posix/native_sim/board.cmake deleted file mode 100644 index d9d444c1be9..00000000000 --- a/boards/posix/native_sim/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS native) - -board_set_debugger_ifnset(native_gdb) -board_finalize_runner_args(native_gdb) diff --git a/boards/posix/native_sim/native_sim_64_defconfig b/boards/posix/native_sim/native_sim_64_defconfig deleted file mode 100644 index abd666317cd..00000000000 --- a/boards/posix/native_sim/native_sim_64_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NATIVE_SIM_64BIT=y -CONFIG_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/native_sim/native_sim_defconfig b/boards/posix/native_sim/native_sim_defconfig deleted file mode 100644 index f3f1e1299c1..00000000000 --- a/boards/posix/native_sim/native_sim_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NATIVE_SIM_32BIT=y -CONFIG_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/nrf_bsim/CMakeLists.txt b/boards/posix/nrf_bsim/CMakeLists.txt deleted file mode 100644 index 3ff7d632d4f..00000000000 --- a/boards/posix/nrf_bsim/CMakeLists.txt +++ /dev/null @@ -1,80 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# Copyright (c) 2018 Oticon A/S -# SPDX-License-Identifier: Apache-2.0 - -find_package(BabbleSim) - -zephyr_library() - -# Due to the BLE controller assumption about enum size -zephyr_compile_options( - -fshort-enums -) -# Structures layouts needs to match in the interface between the runner and the embedded SW -# The nrfx HAL uses enums in its definitions,so they need to have the same size in both, -# as both the HW models and embedded SW use them. -target_compile_options(native_simulator INTERFACE -fshort-enums) - -zephyr_library_sources( - irq_handler.c - cpu_wait.c - argparse.c - nsi_if.c - soc/nrfx_coredep.c - common/bstests_entry.c - common/cmsis/cmsis.c - common/trace_hook.c -) - -# Include sync_rtc from real SOC code if enabled -zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC - ${ZEPHYR_BASE}/soc/arm/nordic_nrf/nrf53/sync_rtc.c - ) - -target_sources(native_simulator INTERFACE - common/bsim_args_runner.c - common/bsim_extra_cpu_if_stubs.c - common/phy_sync_ctrl.c - common/runner_hooks.c - common/posix_arch_if.c - common/trace_hook.c -) - -if (CONFIG_IPC_SERVICE AND CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUAPP) - zephyr_library_sources( - ipc_backend.c - ) -endif() - -zephyr_include_directories( - soc - common - common/cmsis - ${NSI_DIR}/common/src/include -) - -zephyr_library_include_directories( - ${BSIM_COMPONENTS_PATH}/libUtilv1/src/ - ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/ - ${BSIM_COMPONENTS_PATH}/libRandv2/src/ - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/posix/include - common/ -) - -set(libpath ${BSIM_OUT_PATH}/lib) -set_property(TARGET native_simulator APPEND PROPERTY RUNNER_LINK_LIBRARIES - ${libpath}/libUtilv1.32.a - ${libpath}/libPhyComv1.32.a - ${libpath}/lib2G4PhyComv1.32.a - ${libpath}/libRandv2.32.a -) - -target_compile_options(native_simulator INTERFACE - "-DNSI_PRIMARY_MCU_N=${CONFIG_NATIVE_SIMULATOR_PRIMARY_MCU_INDEX}") - -add_subdirectory(${ZEPHYR_BASE}/boards/${ARCH}/common/extra_args/ - ${CMAKE_CURRENT_BINARY_DIR}/extra_args -) - -include(../common/natsim_config.cmake) diff --git a/boards/posix/nrf_bsim/Kconfig b/boards/posix/nrf_bsim/Kconfig deleted file mode 100644 index b43db7fac4a..00000000000 --- a/boards/posix/nrf_bsim/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_BSIM_NRFXX - -# The following file is normally parsed only for the ARM architecture, which is -# used by Nordic SoCs, so to make the symbols defined in this file available for -# the simulated nrf5x_bsim boards, which use the POSIX architecture, the file -# must be read also from here. -source "soc/common/nordic_nrf/Kconfig.peripherals" - -source "boards/$(ARCH)/common/extra_args/Kconfig" - -endif # SOC_SERIES_BSIM_NRFXX - - -# This would eventually be shared by a possible family of simulated NRF boards -# which use BabbleSim. When that happens, we can move this to a common -# Kconfig file - -config SOC_SERIES_BSIM_NRFXX - bool - select NATIVE_LIBRARY - select SOC_COMPATIBLE_NRF - select HAS_NRFX - select HAS_NORDIC_DRIVERS - select PINCTRL_DYNAMIC if PINCTRL - help - Any NRF simulated SOC with BabbleSim, based on the POSIX arch - -config SOC_SERIES_BSIM_NRF52X - bool - select SOC_SERIES_BSIM_NRFXX - select SOC_COMPATIBLE_NRF52X - help - Any NRF52 simulated SOC with BabbleSim, based on the POSIX arch - -config SOC_SERIES_BSIM_NRF53X - bool - select SOC_SERIES_BSIM_NRFXX - select SOC_COMPATIBLE_NRF53X - help - Any NRF53 simulated SOC with BabbleSim, based on the POSIX arch - -if BOARD_NRF5340BSIM_NRF5340_CPUAPP - -# Replica of the option provided by the BOARD_NRF5340DK_NRF5340_CPUAPP board so samples can be -# reused as is -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - -endif # BOARD_NRF5340BSIM_NRF5340_CPUNET - -if SOC_SERIES_BSIM_NRF53X - -# Let's reuse the RTC sync options so applications which use it can be reused as is -source "soc/arm/nordic_nrf/nrf53/Kconfig.sync_rtc" - -endif # SOC_SERIES_BSIM_NRF53X diff --git a/boards/posix/nrf_bsim/Kconfig.board b/boards/posix/nrf_bsim/Kconfig.board deleted file mode 100644 index fcfbae4d4e7..00000000000 --- a/boards/posix/nrf_bsim/Kconfig.board +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52_BSIM - bool "NRF52 simulation model" - select SOC_SERIES_BSIM_NRF52X - select SOC_COMPATIBLE_NRF52833 - select NRF_RTC_TIMER - select CLOCK_CONTROL - help - Will produce a console Linux process which can be executed natively. - It needs the BabbleSim simulator both in compile time and to execute - -config BOARD_NRF5340BSIM_NRF5340_CPUNET - bool "Simulated NRF53 Network core" - select SOC_SERIES_BSIM_NRF53X - select SOC_COMPATIBLE_NRF5340_CPUNET - select NRF_RTC_TIMER - select CLOCK_CONTROL - help - Will produce a console Linux process which can be executed natively. - It needs the BabbleSim simulator both in compile time and to execute - -config BOARD_NRF5340BSIM_NRF5340_CPUAPP - bool "Simulated NRF53 Application core" - select SOC_SERIES_BSIM_NRF53X - select SOC_COMPATIBLE_NRF5340_CPUAPP - select NRF_RTC_TIMER - select CLOCK_CONTROL - help - Will produce a console Linux process which can be executed natively. - It needs the BabbleSim simulator both in compile time and to execute diff --git a/boards/posix/nrf_bsim/Kconfig.defconfig b/boards/posix/nrf_bsim/Kconfig.defconfig deleted file mode 100644 index d4e48ada7ad..00000000000 --- a/boards/posix/nrf_bsim/Kconfig.defconfig +++ /dev/null @@ -1,94 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_BSIM_NRFXX - -config BUILD_OUTPUT_BIN - default n - -config BUILD_OUTPUT_EXE - # When the IPC service is used, the net core image requires the application core image, as it needs - # access to its IPC buffer. Without it, the executable cannot be built. - default y if !(BOARD_NRF5340BSIM_NRF5340_CPUNET && IPC_SERVICE && (NATIVE_SIMULATOR_EXTRA_IMAGE_PATHS = "")) - -config OUTPUT_PRINT_MEMORY_USAGE - default n - -config BOARD - default "nrf52_bsim" if BOARD_NRF52_BSIM - default "nrf5340bsim_nrf5340_cpunet" if BOARD_NRF5340BSIM_NRF5340_CPUNET - default "nrf5340bsim_nrf5340_cpuapp" if BOARD_NRF5340BSIM_NRF5340_CPUAPP - -config NATIVE_SIMULATOR_NUMBER_MCUS - default 2 if BOARD_NRF5340BSIM_NRF5340_CPUNET || BOARD_NRF5340BSIM_NRF5340_CPUAPP - default 1 - -config NATIVE_SIMULATOR_MCU_N - default 1 if BOARD_NRF5340BSIM_NRF5340_CPUNET - default 0 - -config NATIVE_SIMULATOR_AUTOSTART_MCU - default y if BOARD_NRF5340BSIM_NRF5340_CPUNET - -config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX - default 1 if SOC_SERIES_BSIM_NRF53X - default 0 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 128 if !TICKLESS_KERNEL - default 32768 - -config BT_CTLR - default y if BOARD_NRF52_BSIM || BOARD_NRF5340BSIM_NRF5340_CPUNET - depends on BT - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - default 4096 if NRF_802154_SER_HOST && BOARD_NRF5340BSIM_NRF5340_CPUAPP - default 4096 if NRF_802154_SER_RADIO && BOARD_NRF5340BSIM_NRF5340_CPUNET - -if BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET - -config MBOX_NRFX_IPC - default MBOX - -endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET - -if BOARD_NRF5340BSIM_NRF5340_CPUAPP - -config IPC_SERVICE_BACKEND_RPMSG_SHMEM_RESET - default y if IPC_SERVICE_BACKEND_RPMSG - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC -endchoice - -endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP - -# The 15.4 driver Tx encryption is currently not functional with this -# simulated board => we disable it by default. With this Openthread will normally -# default to encrypt packets on its own. -config NRF_802154_ENCRYPTION - default n - -if LOG - -# For this board we can log synchronously without any problem -# Doing so will be nicer for debugging -choice LOG_MODE - default LOG_MODE_IMMEDIATE -endchoice - -endif # LOG - -if CONSOLE - -config POSIX_ARCH_CONSOLE - default y - -endif # CONSOLE - -endif # SOC_SERIES_BSIM_NRFXX diff --git a/boards/posix/nrf_bsim/board.cmake b/boards/posix/nrf_bsim/board.cmake deleted file mode 100644 index d9d444c1be9..00000000000 --- a/boards/posix/nrf_bsim/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS native) - -board_set_debugger_ifnset(native_gdb) -board_finalize_runner_args(native_gdb) diff --git a/boards/posix/nrf_bsim/nrf52_bsim_defconfig b/boards/posix/nrf_bsim/nrf52_bsim_defconfig deleted file mode 100644 index 953e8c1aa93..00000000000 --- a/boards/posix/nrf_bsim/nrf52_bsim_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NRF52_BSIM=y -CONFIG_CONSOLE=y -CONFIG_NO_OPTIMIZATIONS=y -CONFIG_LOG_BACKEND_UART=n diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig b/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig deleted file mode 100644 index fcf14c5b33a..00000000000 --- a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUAPP=y -CONFIG_CONSOLE=y -CONFIG_NO_OPTIMIZATIONS=y diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig b/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig deleted file mode 100644 index 5da7b71af05..00000000000 --- a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUNET=y -CONFIG_CONSOLE=y -CONFIG_NO_OPTIMIZATIONS=y diff --git a/boards/posix/nrf_bsim/pre_dt_board.cmake b/boards/posix/nrf_bsim/pre_dt_board.cmake deleted file mode 100644 index 3369c21d3af..00000000000 --- a/boards/posix/nrf_bsim/pre_dt_board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - power@40000000 & clock@40000000 & bprot@40000000 -# - acl@4001e000 & flash-controller@4001e000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/posix/nrf_bsim/soc/pinctrl_soc.h b/boards/posix/nrf_bsim/soc/pinctrl_soc.h deleted file mode 100644 index f0be0443d5b..00000000000 --- a/boards/posix/nrf_bsim/soc/pinctrl_soc.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H -#define BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H - -/* We reuse the real SOC's header: */ -#include "../soc/common/nordic_nrf/pinctrl_soc.h" - -#endif /* BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H */ diff --git a/boards/arc/iotdk/CMakeLists.txt b/boards/qemu/arc/CMakeLists.txt similarity index 100% rename from boards/arc/iotdk/CMakeLists.txt rename to boards/qemu/arc/CMakeLists.txt diff --git a/boards/qemu/arc/Kconfig b/boards/qemu/arc/Kconfig new file mode 100644 index 00000000000..c335cfb8dcf --- /dev/null +++ b/boards/qemu/arc/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2020 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_ARC + select QEMU_TARGET + select HAS_COVERAGE_SUPPORT diff --git a/boards/qemu/arc/Kconfig.defconfig b/boards/qemu/arc/Kconfig.defconfig new file mode 100644 index 00000000000..ed5b1f0c014 --- /dev/null +++ b/boards/qemu/arc/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2020,2021 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_ARC + +if NETWORKING + +config NET_L2_ETHERNET + default y + +# Required to satisfy dependency of networking stack on RNG +config TEST_RANDOM_GENERATOR + default y + +endif # NETWORKING + +endif diff --git a/boards/qemu/arc/Kconfig.qemu_arc b/boards/qemu/arc/Kconfig.qemu_arc new file mode 100644 index 00000000000..69b406379eb --- /dev/null +++ b/boards/qemu/arc/Kconfig.qemu_arc @@ -0,0 +1,9 @@ +# Copyright (c) 2020 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_ARC + select SOC_QEMU_ARC_EM if BOARD_QEMU_ARC_QEMU_ARC_EM + select SOC_QEMU_ARC_HS if BOARD_QEMU_ARC_QEMU_ARC_HS || BOARD_QEMU_ARC_QEMU_ARC_HS_XIP + select SOC_QEMU_ARC_HS5X if BOARD_QEMU_ARC_QEMU_ARC_HS5X + select SOC_QEMU_ARC_HS6X if BOARD_QEMU_ARC_QEMU_ARC_HS6X diff --git a/boards/arc/qemu_arc/arc_mpu_regions.c b/boards/qemu/arc/arc_mpu_regions.c similarity index 100% rename from boards/arc/qemu_arc/arc_mpu_regions.c rename to boards/qemu/arc/arc_mpu_regions.c diff --git a/boards/qemu/arc/board.cmake b/boards/qemu/arc/board.cmake new file mode 100644 index 00000000000..569343d273c --- /dev/null +++ b/boards/qemu/arc/board.cmake @@ -0,0 +1,44 @@ +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(QEMU_CPU_TYPE_${ARCH} arc) + +if(${CONFIG_SOC_QEMU_ARC_EM}) + set(QEMU_CPU_TYPE_${ARCH} arcem) + set(QEMU_FLAGS_${ARCH} -cpu arcem) +elseif(${CONFIG_SOC_QEMU_ARC_HS}) + set(QEMU_CPU_TYPE_${ARCH} archs) + set(QEMU_FLAGS_${ARCH} -cpu archs) +elseif(${CONFIG_SOC_QEMU_ARC_HS5X}) + set(QEMU_ARCH arc) + set(QEMU_CPU_TYPE_${ARCH} hs5x) + set(QEMU_FLAGS_${ARCH} -cpu hs5x) +elseif(${CONFIG_SOC_QEMU_ARC_HS6X}) + set(QEMU_ARCH arc64) + set(QEMU_CPU_TYPE_${ARCH} hs6x) + set(QEMU_FLAGS_${ARCH} -cpu hs6x) +endif() + +# For old QEMU we had 'simhs' qemu board, however we are going to rename it +# to 'virt' board. It will be renamed in ARC QEMU in the nearest Zephyr SDK +# (where ARCv3 HS6x support will be added to QEMU) +# Let's rely on the QEMU defaults instead of specifying exact board name, +# until the updated Zephyr SDK will be set as default. By that we keep both SDKs +# (old and new) working for ARCv2. +# After that we can specify board explicitly with '-M virt' option. +list(APPEND QEMU_FLAGS_${ARCH} + -m 8M + -nographic + -no-reboot + -monitor none + -global cpu.firq=false + -global cpu.num-irqlevels=15 + -global cpu.num-irq=25 + -global cpu.ext-irq=20 + -global cpu.freq_hz=10000000 + -global cpu.timer0=true + -global cpu.timer1=true + -global cpu.has-mpu=true + -global cpu.mpu-numreg=16 + ) + +set(BOARD_DEBUG_RUNNER qemu) diff --git a/boards/qemu/arc/board.yml b/boards/qemu/arc/board.yml new file mode 100644 index 00000000000..1fb49911afa --- /dev/null +++ b/boards/qemu/arc/board.yml @@ -0,0 +1,10 @@ +board: + name: qemu_arc + vendor: qemu + socs: + - name: qemu_arc_em + - name: qemu_arc_hs + variants: + - name: xip + - name: qemu_arc_hs5x + - name: qemu_arc_hs6x diff --git a/boards/qemu/arc/doc/index.rst b/boards/qemu/arc/doc/index.rst new file mode 100644 index 00000000000..0aef5d8dc39 --- /dev/null +++ b/boards/qemu/arc/doc/index.rst @@ -0,0 +1,102 @@ +.. _qemu_arc: + +ARCv2 & ARCv3 Emulation (QEMU) +############################### + +Overview +******** + +This board configuration will use QEMU to emulate set of generic +ARCv2 and ARCv3 hardware platforms. + +The following features of ARC ISA cores are currently supported: + +* CPU: + * ARCv2 EM + * ARCv2 HS3x + * ARCv3 HS5x + * ARCv3 HS6x +* Only little-endian configurations +* Full 32 register set +* ARC core free-running timers/counters Timer0 & Timer1 +* ARC core interrupt controller with multiple priority levels +* DW UART +* 5 slots for MMIO Virtio devices + +Hardware +******** +Supported Features +================== + +The following hardware features are supported: + ++--------------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++==============+============+======================+ +| ARCv2 INTC | on-chip | interrupt controller | ++--------------+------------+----------------------+ +| DW UART | on-chip | serial port | ++--------------+------------+----------------------+ +| ARC TIMER0 | on-chip | system clock | ++--------------+------------+----------------------+ + +The kernel currently does not support other hardware features on this platform. + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 1 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +DesignWare UART. + +Known Problems or Limitations +============================== + +The following platform features are unsupported: + +* Memory-protection unit (MPU) +* MMIO Virtio Ethernet + +Programming and Debugging +************************* + +Use this configuration to run basic Zephyr applications and kernel tests in the QEMU +emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample +(note you may use ``qemu_arc/qemu_em``, ``qemu_arc/qemu_hs``, ``qemu_arc/qemu_hs5x`` or +``qemu_arc/qemu_hs6x`` depending on target CPU): + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_arc/qemu_em + :goals: run + +This will build an image with the synchronization sample app, boot it using +QEMU, and display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.2.0-2486-g7dbfcf4bab57 *** + threadA: Hello World from qemu_arc! + threadB: Hello World from qemu_arc! + threadA: Hello World from qemu_arc! + threadB: Hello World from qemu_arc! + +Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. + +References +********** + +1.`Programmer’s Reference Manual for ARC HS + `_ diff --git a/boards/arc/qemu_arc/qemu_arc.dtsi b/boards/qemu/arc/qemu_arc.dtsi similarity index 100% rename from boards/arc/qemu_arc/qemu_arc.dtsi rename to boards/qemu/arc/qemu_arc.dtsi diff --git a/boards/arc/qemu_arc/qemu_arc_em.dts b/boards/qemu/arc/qemu_arc_qemu_arc_em.dts similarity index 100% rename from boards/arc/qemu_arc/qemu_arc_em.dts rename to boards/qemu/arc/qemu_arc_qemu_arc_em.dts diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml new file mode 100644 index 00000000000..15adaf6b25a --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml @@ -0,0 +1,14 @@ +identifier: qemu_arc/qemu_arc_em +name: QEMU Emulation for ARC EM +type: qemu +simulation: qemu +arch: arc +toolchain: + - zephyr + - cross-compile +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_em_defconfig b/boards/qemu/arc/qemu_arc_qemu_arc_em_defconfig new file mode 100644 index 00000000000..681d2008147 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_em_defconfig @@ -0,0 +1,10 @@ +CONFIG_XIP=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_HAS_STACK_CHECKING=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT_SHIFT=6 +CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/qemu_arc/qemu_arc_hs.dts b/boards/qemu/arc/qemu_arc_qemu_arc_hs.dts similarity index 100% rename from boards/arc/qemu_arc/qemu_arc_hs.dts rename to boards/qemu/arc/qemu_arc_qemu_arc_hs.dts diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml new file mode 100644 index 00000000000..92ea09d4ee8 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml @@ -0,0 +1,15 @@ +identifier: qemu_arc/qemu_arc_hs +name: QEMU Emulation for ARC HS +type: qemu +simulation: qemu +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_hs5x.dts b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.dts similarity index 100% rename from boards/arc/qemu_arc/qemu_arc_hs5x.dts rename to boards/qemu/arc/qemu_arc_qemu_arc_hs5x.dts diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml new file mode 100644 index 00000000000..152fbf0b5c0 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml @@ -0,0 +1,14 @@ +identifier: qemu_arc/qemu_arc_hs5x +name: QEMU Emulation for ARC HS5x +type: qemu +simulation: qemu +arch: arc +toolchain: + - zephyr + - cross-compile +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs5x_defconfig b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x_defconfig new file mode 100644 index 00000000000..31f5cff2f42 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x_defconfig @@ -0,0 +1,10 @@ +CONFIG_ISA_ARCV3=y +CONFIG_XIP=n +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_HAS_STACK_CHECKING=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/arc/qemu_arc/qemu_arc_hs6x.dts b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.dts similarity index 100% rename from boards/arc/qemu_arc/qemu_arc_hs6x.dts rename to boards/qemu/arc/qemu_arc_qemu_arc_hs6x.dts diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml new file mode 100644 index 00000000000..94b4342a40a --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml @@ -0,0 +1,14 @@ +identifier: qemu_arc/qemu_arc_hs6x +name: QEMU Emulation for ARC HS6x +type: qemu +simulation: qemu +arch: arc +toolchain: + - cross-compile + - zephyr +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs6x_defconfig b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x_defconfig new file mode 100644 index 00000000000..31f5cff2f42 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x_defconfig @@ -0,0 +1,10 @@ +CONFIG_ISA_ARCV3=y +CONFIG_XIP=n +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_HAS_STACK_CHECKING=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs_defconfig b/boards/qemu/arc/qemu_arc_qemu_arc_hs_defconfig new file mode 100644 index 00000000000..d2fd7fddaa6 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs_defconfig @@ -0,0 +1,10 @@ +CONFIG_XIP=n +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_HAS_STACK_CHECKING=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT_SHIFT=6 +CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/qemu_arc/qemu_arc_hs_xip.dts b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.dts similarity index 100% rename from boards/arc/qemu_arc/qemu_arc_hs_xip.dts rename to boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.dts diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml new file mode 100644 index 00000000000..dec824ec6b0 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml @@ -0,0 +1,14 @@ +identifier: qemu_arc/qemu_arc_hs/xip +name: QEMU Emulation for ARC HS (XIP) +type: qemu +simulation: qemu +arch: arc +toolchain: + - zephyr + - cross-compile +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip_defconfig b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip_defconfig new file mode 100644 index 00000000000..681d2008147 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip_defconfig @@ -0,0 +1,10 @@ +CONFIG_XIP=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_HAS_STACK_CHECKING=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT_SHIFT=6 +CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/qemu/cortex_a53/Kconfig b/boards/qemu/cortex_a53/Kconfig new file mode 100644 index 00000000000..13f79db59cb --- /dev/null +++ b/boards/qemu/cortex_a53/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config QEMU_CORTEX_A53_ETH_E1000 + bool + default y if !NET_TEST + depends on BOARD_QEMU_CORTEX_A53 && NETWORKING && DT_HAS_INTEL_E1000_ENABLED + select ETH_E1000 + select NET_L2_ETHERNET + select PCIE + select PCIE_CONTROLLER + select PCIE_ECAM diff --git a/boards/qemu/cortex_a53/Kconfig.defconfig b/boards/qemu/cortex_a53/Kconfig.defconfig new file mode 100644 index 00000000000..70fe11c6d73 --- /dev/null +++ b/boards/qemu/cortex_a53/Kconfig.defconfig @@ -0,0 +1,46 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_CORTEX_A53 + +config BUILD_OUTPUT_BIN + default y + +config MAX_THREAD_BYTES + default 3 + +if NETWORKING + +choice NET_QEMU_NETWORKING + default NET_QEMU_ETHERNET if QEMU_CORTEX_A53_ETH_E1000 +endchoice + +config NET_DRIVERS + default n if QEMU_CORTEX_A53_ETH_E1000 + +endif # NETWORKING + +# QEMU PCI requires at least 256M of virtual space +config KERNEL_VM_SIZE + default 0x80000000 if PCIE + +# QEMU PCI requires physical addresses with more than 32 bits +choice ARM64_VA_BITS + default ARM64_VA_BITS_40 if PCIE +endchoice + +choice ARM64_PA_BITS + default ARM64_PA_BITS_40 if PCIE +endchoice + +if QEMU_ICOUNT + +config QEMU_ICOUNT_SHIFT + default 4 + +config QEMU_ICOUNT_SLEEP + default y + +endif # QEMU_ICOUNT + +endif # BOARD_QEMU_CORTEX_A53 diff --git a/boards/qemu/cortex_a53/Kconfig.qemu_cortex_a53 b/boards/qemu/cortex_a53/Kconfig.qemu_cortex_a53 new file mode 100644 index 00000000000..a7d876a9e55 --- /dev/null +++ b/boards/qemu/cortex_a53/Kconfig.qemu_cortex_a53 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_A53 + select SOC_QEMU_CORTEX_A53 diff --git a/boards/qemu/cortex_a53/board.cmake b/boards/qemu/cortex_a53/board.cmake new file mode 100644 index 00000000000..7cc424e4544 --- /dev/null +++ b/boards/qemu/cortex_a53/board.cmake @@ -0,0 +1,30 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) +set(QEMU_ARCH aarch64) + +set(QEMU_CPU_TYPE_${ARCH} cortex-a53) + +if(CONFIG_ARMV8_A_NS) + set(QEMU_MACH virt,gic-version=3) +else() + set(QEMU_MACH virt,secure=on,gic-version=3) +endif() + +set(QEMU_FLAGS_${ARCH} + -cpu ${QEMU_CPU_TYPE_${ARCH}} + -nographic + -machine ${QEMU_MACH} + ) + +if(CONFIG_XIP) + # This should be equivalent to + # ... -drive if=pflash,file=build/zephyr/zephyr.bin,format=raw + # without having to pad the binary file to the FLASH size + set(QEMU_KERNEL_OPTION + -bios ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin + ) +endif() + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/cortex_a53/board.yml b/boards/qemu/cortex_a53/board.yml new file mode 100644 index 00000000000..ab04f6ac8f1 --- /dev/null +++ b/boards/qemu/cortex_a53/board.yml @@ -0,0 +1,8 @@ +board: + name: qemu_cortex_a53 + vendor: arm + socs: + - name: qemu_cortex_a53 + variants: + - name: smp + - name: xip diff --git a/boards/arm64/qemu_cortex_a53/doc/index.rst b/boards/qemu/cortex_a53/doc/index.rst similarity index 100% rename from boards/arm64/qemu_cortex_a53/doc/index.rst rename to boards/qemu/cortex_a53/doc/index.rst diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53.dts b/boards/qemu/cortex_a53/qemu_cortex_a53.dts similarity index 100% rename from boards/arm64/qemu_cortex_a53/qemu_cortex_a53.dts rename to boards/qemu/cortex_a53/qemu_cortex_a53.dts diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53.yaml b/boards/qemu/cortex_a53/qemu_cortex_a53.yaml similarity index 100% rename from boards/arm64/qemu_cortex_a53/qemu_cortex_a53.yaml rename to boards/qemu/cortex_a53/qemu_cortex_a53.yaml diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_defconfig b/boards/qemu/cortex_a53/qemu_cortex_a53_defconfig new file mode 100644 index 00000000000..26b07e5862c --- /dev/null +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM_ARCH_TIMER=y + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Avoid timing skew in tests +CONFIG_QEMU_ICOUNT=y diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp.dts b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.dts similarity index 100% rename from boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp.dts rename to boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.dts diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml new file mode 100644 index 00000000000..4804d064564 --- /dev/null +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml @@ -0,0 +1,17 @@ +identifier: qemu_cortex_a53/qemu_cortex_a53/smp +name: QEMU Emulation for Cortex-A53 SMP +type: qemu +simulation: qemu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +supported: + - smp +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: qemu diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp_defconfig b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp_defconfig new file mode 100644 index 00000000000..63099649065 --- /dev/null +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM_ARCH_TIMER=y + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# icount does not work well with SMP +CONFIG_QEMU_ICOUNT=n + +# We have multiple QEMU-A53 boards, so let us exercise ARMV8_A_NS on this one +# (plus it is needed for SMP) +CONFIG_ARMV8_A_NS=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_TIMEOUT_64BIT=y diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.dts b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.dts similarity index 100% rename from boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.dts rename to boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.dts diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml new file mode 100644 index 00000000000..5805780ee33 --- /dev/null +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml @@ -0,0 +1,14 @@ +identifier: qemu_cortex_a53/qemu_cortex_a53/xip +name: QEMU Emulation for Cortex-A53 (XIP) +type: qemu +simulation: qemu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +testing: + default: true + only_tags: + - xip +vendor: qemu diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip_defconfig b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip_defconfig new file mode 100644 index 00000000000..f38fd56af71 --- /dev/null +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM_ARCH_TIMER=y + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Avoid timing skew in tests +CONFIG_QEMU_ICOUNT=y + +# Enable XIP +CONFIG_XIP=y diff --git a/boards/qemu/cortex_a9/Kconfig b/boards/qemu/cortex_a9/Kconfig new file mode 100644 index 00000000000..f5d8700f0be --- /dev/null +++ b/boards/qemu/cortex_a9/Kconfig @@ -0,0 +1,9 @@ +# +# Kconfig - Cortex-A9 QEMU Emulation +# +# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_QEMU_CORTEX_A9 + select QEMU_TARGET diff --git a/boards/qemu/cortex_a9/Kconfig.defconfig b/boards/qemu/cortex_a9/Kconfig.defconfig new file mode 100644 index 00000000000..c2051fe5408 --- /dev/null +++ b/boards/qemu/cortex_a9/Kconfig.defconfig @@ -0,0 +1,70 @@ +# +# Kconfig - Cortex-A9 (Zynq-7000) QEMU Emulation +# +# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_QEMU_CORTEX_A9 + +config BUILD_OUTPUT_BIN + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 111111111 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +if LOG_PROCESS_THREAD + +config LOG_PROCESS_THREAD_STACK_SIZE + default 8192 + +endif # LOG_PROCESS_THREAD + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config NET_TX_STACK_SIZE + default 8192 + +config NET_RX_STACK_SIZE + default 8192 + +if NET_TCP + +config NET_TCP_WORKQ_STACK_SIZE + default 8192 + +endif # NET_TCP + +if NET_MGMT_EVENT + +config NET_MGMT_EVENT_STACK_SIZE + default 8192 + +endif # NET_MGMT_EVENT + +config TEST_RANDOM_GENERATOR + default y + +endif # NETWORKING + +if QEMU_ICOUNT + +config QEMU_ICOUNT_SHIFT + default 3 + +config QEMU_ICOUNT_SLEEP + default y + +endif # QEMU_ICOUNT + +config SHELL_STACK_SIZE + default 8192 if SHELL + +endif # BOARD_QEMU_CORTEX_A9 diff --git a/boards/qemu/cortex_a9/Kconfig.qemu_cortex_a9 b/boards/qemu/cortex_a9/Kconfig.qemu_cortex_a9 new file mode 100644 index 00000000000..9e869cc2f66 --- /dev/null +++ b/boards/qemu/cortex_a9/Kconfig.qemu_cortex_a9 @@ -0,0 +1,9 @@ +# +# Kconfig - Cortex-A9 QEMU Emulation +# +# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_QEMU_CORTEX_A9 + select SOC_XILINX_XC7Z007S diff --git a/boards/qemu/cortex_a9/board.cmake b/boards/qemu/cortex_a9/board.cmake new file mode 100644 index 00000000000..45d2dcd7138 --- /dev/null +++ b/boards/qemu/cortex_a9/board.cmake @@ -0,0 +1,21 @@ +# +# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +set(SUPPORTED_EMU_PLATFORMS qemu) +set(QEMU_ARCH xilinx-aarch64) + +set(QEMU_CPU_TYPE_${ARCH} cortex-a9) + +set(QEMU_FLAGS_${ARCH} + -nographic + -machine arm-generic-fdt-7series + -dtb ${CMAKE_CURRENT_LIST_DIR}/fdt-zynq7000s.dtb + ) + +set(QEMU_KERNEL_OPTION + "-device;loader,file=\$,cpu-num=0" + ) + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/cortex_a9/board.yml b/boards/qemu/cortex_a9/board.yml new file mode 100644 index 00000000000..72cba6ce8d9 --- /dev/null +++ b/boards/qemu/cortex_a9/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_cortex_a9 + vendor: qemu + socs: + - name: xc7z007s diff --git a/boards/arm/qemu_cortex_a9/fdt-zynq7000s.dtb b/boards/qemu/cortex_a9/fdt-zynq7000s.dtb similarity index 100% rename from boards/arm/qemu_cortex_a9/fdt-zynq7000s.dtb rename to boards/qemu/cortex_a9/fdt-zynq7000s.dtb diff --git a/boards/arm/qemu_cortex_a9/qemu_cortex_a9.dts b/boards/qemu/cortex_a9/qemu_cortex_a9.dts similarity index 100% rename from boards/arm/qemu_cortex_a9/qemu_cortex_a9.dts rename to boards/qemu/cortex_a9/qemu_cortex_a9.dts diff --git a/boards/arm/qemu_cortex_a9/qemu_cortex_a9.yaml b/boards/qemu/cortex_a9/qemu_cortex_a9.yaml similarity index 100% rename from boards/arm/qemu_cortex_a9/qemu_cortex_a9.yaml rename to boards/qemu/cortex_a9/qemu_cortex_a9.yaml diff --git a/boards/arm/qemu_cortex_a9/qemu_cortex_a9_defconfig b/boards/qemu/cortex_a9/qemu_cortex_a9_defconfig similarity index 82% rename from boards/arm/qemu_cortex_a9/qemu_cortex_a9_defconfig rename to boards/qemu/cortex_a9/qemu_cortex_a9_defconfig index 01c7b5191b8..16149af1d7c 100644 --- a/boards/arm/qemu_cortex_a9/qemu_cortex_a9_defconfig +++ b/boards/qemu/cortex_a9/qemu_cortex_a9_defconfig @@ -4,11 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_BOARD_QEMU_CORTEX_A9=y - -CONFIG_SOC_SERIES_XILINX_XC7ZXXXS=y -CONFIG_SOC_XILINX_XC7Z007S=y - CONFIG_ARM_ARCH_TIMER=y CONFIG_SERIAL=y diff --git a/boards/arm/qemu_cortex_m0/CMakeLists.txt b/boards/qemu/cortex_m0/CMakeLists.txt similarity index 100% rename from boards/arm/qemu_cortex_m0/CMakeLists.txt rename to boards/qemu/cortex_m0/CMakeLists.txt diff --git a/boards/qemu/cortex_m0/Kconfig b/boards/qemu/cortex_m0/Kconfig new file mode 100644 index 00000000000..e0fd84c85d2 --- /dev/null +++ b/boards/qemu/cortex_m0/Kconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_M0 + select QEMU_TARGET + +config NRF_TIMER_TIMER + bool "nRF Timer Counter (NRF_TIMER0) Timer" + depends on CLOCK_CONTROL + depends on SOC_COMPATIBLE_NRF + depends on SYS_CLOCK_EXISTS + select TICKLESS_CAPABLE + default y + help + This module implements a kernel device driver for the nRF Timer + Counter NRF_TIMER0 and provides the standard "system clock driver" + interfaces. diff --git a/boards/qemu/cortex_m0/Kconfig.defconfig b/boards/qemu/cortex_m0/Kconfig.defconfig new file mode 100644 index 00000000000..3bdf6271212 --- /dev/null +++ b/boards/qemu/cortex_m0/Kconfig.defconfig @@ -0,0 +1,17 @@ +# QEMU Cortex-M0 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_CORTEX_M0 + +config NRF_RTC_TIMER + default n if SYS_CLOCK_EXISTS + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 100 + +endif # BOARD_QEMU_CORTEX_M0 diff --git a/boards/qemu/cortex_m0/Kconfig.qemu_cortex_m0 b/boards/qemu/cortex_m0/Kconfig.qemu_cortex_m0 new file mode 100644 index 00000000000..9c99bb7d2f3 --- /dev/null +++ b/boards/qemu/cortex_m0/Kconfig.qemu_cortex_m0 @@ -0,0 +1,7 @@ +# QEMU Cortex-M0 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_M0 + select SOC_NRF51822_QFAA diff --git a/boards/arm/qemu_cortex_m0/board.cmake b/boards/qemu/cortex_m0/board.cmake similarity index 100% rename from boards/arm/qemu_cortex_m0/board.cmake rename to boards/qemu/cortex_m0/board.cmake diff --git a/boards/qemu/cortex_m0/board.yml b/boards/qemu/cortex_m0/board.yml new file mode 100644 index 00000000000..fc71c63896b --- /dev/null +++ b/boards/qemu/cortex_m0/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_cortex_m0 + vendor: nordic + socs: + - name: nrf51822 diff --git a/boards/arm/qemu_cortex_m0/doc/index.rst b/boards/qemu/cortex_m0/doc/index.rst similarity index 100% rename from boards/arm/qemu_cortex_m0/doc/index.rst rename to boards/qemu/cortex_m0/doc/index.rst diff --git a/boards/arm/qemu_cortex_m0/nrf_timer_timer.c b/boards/qemu/cortex_m0/nrf_timer_timer.c similarity index 100% rename from boards/arm/qemu_cortex_m0/nrf_timer_timer.c rename to boards/qemu/cortex_m0/nrf_timer_timer.c diff --git a/boards/arm/nrf51dk_nrf51422/pre_dt_board.cmake b/boards/qemu/cortex_m0/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf51dk_nrf51422/pre_dt_board.cmake rename to boards/qemu/cortex_m0/pre_dt_board.cmake diff --git a/boards/arm/qemu_cortex_m0/qemu_cortex_m0-pinctrl.dtsi b/boards/qemu/cortex_m0/qemu_cortex_m0-pinctrl.dtsi similarity index 100% rename from boards/arm/qemu_cortex_m0/qemu_cortex_m0-pinctrl.dtsi rename to boards/qemu/cortex_m0/qemu_cortex_m0-pinctrl.dtsi diff --git a/boards/arm/qemu_cortex_m0/qemu_cortex_m0.dts b/boards/qemu/cortex_m0/qemu_cortex_m0.dts similarity index 100% rename from boards/arm/qemu_cortex_m0/qemu_cortex_m0.dts rename to boards/qemu/cortex_m0/qemu_cortex_m0.dts diff --git a/boards/arm/qemu_cortex_m0/qemu_cortex_m0.yaml b/boards/qemu/cortex_m0/qemu_cortex_m0.yaml similarity index 100% rename from boards/arm/qemu_cortex_m0/qemu_cortex_m0.yaml rename to boards/qemu/cortex_m0/qemu_cortex_m0.yaml diff --git a/boards/qemu/cortex_m0/qemu_cortex_m0_defconfig b/boards/qemu/cortex_m0/qemu_cortex_m0_defconfig new file mode 100644 index 00000000000..6b0fce4e16a --- /dev/null +++ b/boards/qemu/cortex_m0/qemu_cortex_m0_defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_QEMU_ICOUNT_SHIFT=6 + +# Enable GPIO +CONFIG_GPIO=y + +# Clock control +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# icount is kinda broken when the NRF timer emulation is used +CONFIG_QEMU_ICOUNT=n diff --git a/boards/qemu/cortex_m3/Kconfig b/boards/qemu/cortex_m3/Kconfig new file mode 100644 index 00000000000..eef57a4eea4 --- /dev/null +++ b/boards/qemu/cortex_m3/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Zephyr Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_M3 + select QEMU_TARGET diff --git a/boards/qemu/cortex_m3/Kconfig.defconfig b/boards/qemu/cortex_m3/Kconfig.defconfig new file mode 100644 index 00000000000..07f168ce414 --- /dev/null +++ b/boards/qemu/cortex_m3/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2016 Zephyr Contributors +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_CORTEX_M3 + +config BUILD_OUTPUT_BIN + default n + +# DWT is not properly emulated in QEMU +choice NULL_POINTER_EXCEPTION_DETECTION + bool + default NULL_POINTER_EXCEPTION_DETECTION_NONE +endchoice + +endif # BOARD_QEMU_CORTEX_M3 diff --git a/boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 b/boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 new file mode 100644 index 00000000000..0e8d2cb2301 --- /dev/null +++ b/boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 @@ -0,0 +1,7 @@ +# Copyright (c) 2016 Zephyr Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_M3 + select SOC_TI_LM3S6965 + help + Cortex-M3 Emulation (QEMU) diff --git a/boards/qemu/cortex_m3/board.cmake b/boards/qemu/cortex_m3/board.cmake new file mode 100644 index 00000000000..47d20e706a9 --- /dev/null +++ b/boards/qemu/cortex_m3/board.cmake @@ -0,0 +1,13 @@ +# Copyright (c) 2016 Zephyr Contributors +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(QEMU_CPU_TYPE_${ARCH} cortex-m3) +set(QEMU_FLAGS_${ARCH} + -cpu ${QEMU_CPU_TYPE_${ARCH}} + -machine lm3s6965evb + -nographic + -vga none + ) +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/cortex_m3/board.yml b/boards/qemu/cortex_m3/board.yml new file mode 100644 index 00000000000..5566adb5e02 --- /dev/null +++ b/boards/qemu/cortex_m3/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_cortex_m3 + vendor: qemu + socs: + - name: ti_lm3s6965 diff --git a/boards/arm/qemu_cortex_m3/doc/index.rst b/boards/qemu/cortex_m3/doc/index.rst similarity index 100% rename from boards/arm/qemu_cortex_m3/doc/index.rst rename to boards/qemu/cortex_m3/doc/index.rst diff --git a/boards/arm/qemu_cortex_m3/qemu_cortex_m3.dts b/boards/qemu/cortex_m3/qemu_cortex_m3.dts similarity index 95% rename from boards/arm/qemu_cortex_m3/qemu_cortex_m3.dts rename to boards/qemu/cortex_m3/qemu_cortex_m3.dts index 2d8e2f02dc6..2e0bd95755f 100644 --- a/boards/arm/qemu_cortex_m3/qemu_cortex_m3.dts +++ b/boards/qemu/cortex_m3/qemu_cortex_m3.dts @@ -1,3 +1,4 @@ +/* Copyright (c) 2016 Zephyr Contributors */ /* SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; diff --git a/boards/arm/qemu_cortex_m3/qemu_cortex_m3.yaml b/boards/qemu/cortex_m3/qemu_cortex_m3.yaml similarity index 100% rename from boards/arm/qemu_cortex_m3/qemu_cortex_m3.yaml rename to boards/qemu/cortex_m3/qemu_cortex_m3.yaml diff --git a/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig b/boards/qemu/cortex_m3/qemu_cortex_m3_defconfig similarity index 77% rename from boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig rename to boards/qemu/cortex_m3/qemu_cortex_m3_defconfig index 7abc1e1d58a..ed69699fa71 100644 --- a/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig +++ b/boards/qemu/cortex_m3/qemu_cortex_m3_defconfig @@ -1,8 +1,7 @@ +# Copyright (c) 2016 Zephyr Contributors # SPDX-License-Identifier: Apache-2.0 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000 -CONFIG_SOC_TI_LM3S6965=y -CONFIG_BOARD_QEMU_CORTEX_M3=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/qemu/cortex_r5/Kconfig b/boards/qemu/cortex_r5/Kconfig new file mode 100644 index 00000000000..1b7fa887f41 --- /dev/null +++ b/boards/qemu/cortex_r5/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_R5 + select QEMU_TARGET diff --git a/boards/qemu/cortex_r5/Kconfig.defconfig b/boards/qemu/cortex_r5/Kconfig.defconfig new file mode 100644 index 00000000000..a6ea313a4ab --- /dev/null +++ b/boards/qemu/cortex_r5/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_CORTEX_R5 + +config BUILD_OUTPUT_BIN + default n + +if USERSPACE + +config COMPILER_ISA_THUMB2 + default n + +endif + +endif # BOARD_QEMU_CORTEX_R5 diff --git a/boards/qemu/cortex_r5/Kconfig.qemu_cortex_r5 b/boards/qemu/cortex_r5/Kconfig.qemu_cortex_r5 new file mode 100644 index 00000000000..054936f844b --- /dev/null +++ b/boards/qemu/cortex_r5/Kconfig.qemu_cortex_r5 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_R5 + select SOC_XILINX_ZYNQMP_RPU diff --git a/boards/qemu/cortex_r5/board.cmake b/boards/qemu/cortex_r5/board.cmake new file mode 100644 index 00000000000..0b35a9e6e4b --- /dev/null +++ b/boards/qemu/cortex_r5/board.cmake @@ -0,0 +1,21 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) +set(QEMU_ARCH xilinx-aarch64) + +set(QEMU_CPU_TYPE_${ARCH} cortex-r5) +set(QEMU_FLAGS_${ARCH} + -nographic + -machine arm-generic-fdt + -dtb ${CMAKE_CURRENT_LIST_DIR}/fdt-single_arch-zcu102-arm.dtb + ) + +set(QEMU_KERNEL_OPTION + "-device;loader,file=\$,cpu-num=4" + "-device;loader,addr=0xff5e023c,data=0x80008fde,data-len=4" + "-device;loader,addr=0xff9a0000,data=0x80000218,data-len=4" + ) + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/cortex_r5/board.yml b/boards/qemu/cortex_r5/board.yml new file mode 100644 index 00000000000..6cf5b2fee95 --- /dev/null +++ b/boards/qemu/cortex_r5/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_cortex_r5 + vendor: qemu + socs: + - name: zynqmp_rpu diff --git a/boards/arm/qemu_cortex_r5/doc/index.rst b/boards/qemu/cortex_r5/doc/index.rst similarity index 100% rename from boards/arm/qemu_cortex_r5/doc/index.rst rename to boards/qemu/cortex_r5/doc/index.rst diff --git a/boards/arm/qemu_cortex_r5/fdt-single_arch-zcu102-arm.dtb b/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb similarity index 100% rename from boards/arm/qemu_cortex_r5/fdt-single_arch-zcu102-arm.dtb rename to boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb diff --git a/boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts b/boards/qemu/cortex_r5/qemu_cortex_r5.dts similarity index 100% rename from boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts rename to boards/qemu/cortex_r5/qemu_cortex_r5.dts diff --git a/boards/arm/qemu_cortex_r5/qemu_cortex_r5.yaml b/boards/qemu/cortex_r5/qemu_cortex_r5.yaml similarity index 100% rename from boards/arm/qemu_cortex_r5/qemu_cortex_r5.yaml rename to boards/qemu/cortex_r5/qemu_cortex_r5.yaml diff --git a/boards/arm/qemu_cortex_r5/qemu_cortex_r5_defconfig b/boards/qemu/cortex_r5/qemu_cortex_r5_defconfig similarity index 79% rename from boards/arm/qemu_cortex_r5/qemu_cortex_r5_defconfig rename to boards/qemu/cortex_r5/qemu_cortex_r5_defconfig index ac7ff922ed7..40e22978ec0 100644 --- a/boards/arm/qemu_cortex_r5/qemu_cortex_r5_defconfig +++ b/boards/qemu/cortex_r5/qemu_cortex_r5_defconfig @@ -1,5 +1,3 @@ -CONFIG_SOC_XILINX_ZYNQMP_RPU=y -CONFIG_BOARD_QEMU_CORTEX_R5=y CONFIG_XIP=n CONFIG_QEMU_ICOUNT_SHIFT=3 diff --git a/boards/qemu/index.rst b/boards/qemu/index.rst new file mode 100644 index 00000000000..6f640ed3311 --- /dev/null +++ b/boards/qemu/index.rst @@ -0,0 +1,10 @@ +.. _boards-qemu: + +QEMU +#### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/qemu/kvm_arm64/Kconfig b/boards/qemu/kvm_arm64/Kconfig new file mode 100644 index 00000000000..960c63886ab --- /dev/null +++ b/boards/qemu/kvm_arm64/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Huawei France Technologies SASU +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_KVM_ARM64 + select ARM64 + select QEMU_TARGET diff --git a/boards/qemu/kvm_arm64/Kconfig.defconfig b/boards/qemu/kvm_arm64/Kconfig.defconfig new file mode 100644 index 00000000000..7d13e73aa7f --- /dev/null +++ b/boards/qemu/kvm_arm64/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Huawei France Technologies SASU +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_KVM_ARM64 + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_QEMU_KVM_ARM64 diff --git a/boards/qemu/kvm_arm64/Kconfig.qemu_kvm_arm64 b/boards/qemu/kvm_arm64/Kconfig.qemu_kvm_arm64 new file mode 100644 index 00000000000..6f4df12bad6 --- /dev/null +++ b/boards/qemu/kvm_arm64/Kconfig.qemu_kvm_arm64 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Huawei France Technologies SASU +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_KVM_ARM64 + select SOC_QEMU_VIRT_ARM64 diff --git a/boards/arm64/qemu_kvm_arm64/board.cmake b/boards/qemu/kvm_arm64/board.cmake similarity index 100% rename from boards/arm64/qemu_kvm_arm64/board.cmake rename to boards/qemu/kvm_arm64/board.cmake diff --git a/boards/qemu/kvm_arm64/board.yml b/boards/qemu/kvm_arm64/board.yml new file mode 100644 index 00000000000..dd0edf80316 --- /dev/null +++ b/boards/qemu/kvm_arm64/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_kvm_arm64 + vendor: arm + socs: + - name: qemu_virt_arm64 diff --git a/boards/arm64/qemu_kvm_arm64/doc/index.rst b/boards/qemu/kvm_arm64/doc/index.rst similarity index 100% rename from boards/arm64/qemu_kvm_arm64/doc/index.rst rename to boards/qemu/kvm_arm64/doc/index.rst diff --git a/boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64.dts b/boards/qemu/kvm_arm64/qemu_kvm_arm64.dts similarity index 100% rename from boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64.dts rename to boards/qemu/kvm_arm64/qemu_kvm_arm64.dts diff --git a/boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64.yaml b/boards/qemu/kvm_arm64/qemu_kvm_arm64.yaml similarity index 100% rename from boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64.yaml rename to boards/qemu/kvm_arm64/qemu_kvm_arm64.yaml diff --git a/boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64_defconfig b/boards/qemu/kvm_arm64/qemu_kvm_arm64_defconfig similarity index 83% rename from boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64_defconfig rename to boards/qemu/kvm_arm64/qemu_kvm_arm64_defconfig index f94384176d9..0060ce3f82f 100644 --- a/boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64_defconfig +++ b/boards/qemu/kvm_arm64/qemu_kvm_arm64_defconfig @@ -1,5 +1,3 @@ -CONFIG_SOC_QEMU_VIRT_ARM64=y -CONFIG_BOARD_QEMU_KVM_ARM64=y CONFIG_ARM_ARCH_TIMER=y CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y CONFIG_QEMU_ICOUNT=n diff --git a/boards/qemu/leon3/Kconfig b/boards/qemu/leon3/Kconfig new file mode 100644 index 00000000000..f99064ef58c --- /dev/null +++ b/boards/qemu/leon3/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_LEON3 + select QEMU_TARGET + select CPU_HAS_FPU diff --git a/boards/qemu/leon3/Kconfig.defconfig b/boards/qemu/leon3/Kconfig.defconfig new file mode 100644 index 00000000000..f90c04a345c --- /dev/null +++ b/boards/qemu/leon3/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_LEON3 + +config UART_INTERRUPT_DRIVEN + default y + +endif diff --git a/boards/qemu/leon3/Kconfig.qemu_leon3 b/boards/qemu/leon3/Kconfig.qemu_leon3 new file mode 100644 index 00000000000..06d2be337b0 --- /dev/null +++ b/boards/qemu/leon3/Kconfig.qemu_leon3 @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_LEON3 + select SOC_LEON3 diff --git a/boards/sparc/qemu_leon3/board.cmake b/boards/qemu/leon3/board.cmake similarity index 100% rename from boards/sparc/qemu_leon3/board.cmake rename to boards/qemu/leon3/board.cmake diff --git a/boards/qemu/leon3/board.yml b/boards/qemu/leon3/board.yml new file mode 100644 index 00000000000..6d4fdc189bf --- /dev/null +++ b/boards/qemu/leon3/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_leon3 + vendor: gaisler + socs: + - name: leon3 diff --git a/boards/sparc/qemu_leon3/doc/index.rst b/boards/qemu/leon3/doc/index.rst similarity index 100% rename from boards/sparc/qemu_leon3/doc/index.rst rename to boards/qemu/leon3/doc/index.rst diff --git a/boards/sparc/qemu_leon3/qemu_leon3.dts b/boards/qemu/leon3/qemu_leon3.dts similarity index 100% rename from boards/sparc/qemu_leon3/qemu_leon3.dts rename to boards/qemu/leon3/qemu_leon3.dts diff --git a/boards/sparc/qemu_leon3/qemu_leon3.yaml b/boards/qemu/leon3/qemu_leon3.yaml similarity index 100% rename from boards/sparc/qemu_leon3/qemu_leon3.yaml rename to boards/qemu/leon3/qemu_leon3.yaml diff --git a/boards/sparc/qemu_leon3/qemu_leon3_defconfig b/boards/qemu/leon3/qemu_leon3_defconfig similarity index 77% rename from boards/sparc/qemu_leon3/qemu_leon3_defconfig rename to boards/qemu/leon3/qemu_leon3_defconfig index 7f57d930478..72f7285f608 100644 --- a/boards/sparc/qemu_leon3/qemu_leon3_defconfig +++ b/boards/qemu/leon3/qemu_leon3_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_LEON3=y -CONFIG_BOARD_QEMU_LEON3=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/qemu/malta/Kconfig b/boards/qemu/malta/Kconfig new file mode 100644 index 00000000000..5813610828d --- /dev/null +++ b/boards/qemu/malta/Kconfig @@ -0,0 +1,9 @@ +# +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_QEMU_MALTA + select QEMU_TARGET + select BIG_ENDIAN if BOARD_QEMU_MALTA_QEMU_MALTA_BE diff --git a/boards/qemu/malta/Kconfig.defconfig b/boards/qemu/malta/Kconfig.defconfig new file mode 100644 index 00000000000..fb24d3b5b47 --- /dev/null +++ b/boards/qemu/malta/Kconfig.defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_QEMU_MALTA + +config BUILD_OUTPUT_BIN + default n + +endif # BOARD_QEMU_MALTA diff --git a/boards/qemu/malta/Kconfig.qemu_malta b/boards/qemu/malta/Kconfig.qemu_malta new file mode 100644 index 00000000000..fe93f3b3874 --- /dev/null +++ b/boards/qemu/malta/Kconfig.qemu_malta @@ -0,0 +1,8 @@ +# +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_QEMU_MALTA + select SOC_QEMU_MALTA diff --git a/boards/mips/qemu_malta/board.cmake b/boards/qemu/malta/board.cmake similarity index 100% rename from boards/mips/qemu_malta/board.cmake rename to boards/qemu/malta/board.cmake diff --git a/boards/qemu/malta/board.yml b/boards/qemu/malta/board.yml new file mode 100644 index 00000000000..050bd381c73 --- /dev/null +++ b/boards/qemu/malta/board.yml @@ -0,0 +1,7 @@ +board: + name: qemu_malta + vendor: qemu + socs: + - name: qemu_malta + variants: + - name: 'be' diff --git a/boards/qemu/malta/doc/index.rst b/boards/qemu/malta/doc/index.rst new file mode 100644 index 00000000000..178d787f951 --- /dev/null +++ b/boards/qemu/malta/doc/index.rst @@ -0,0 +1,106 @@ +.. _qemu_malta: + +MIPS Malta Emulation (QEMU) +########################### + +Overview +******** + +This board configuration will use QEMU to emulate the MIPS Malta platform. + +This configuration provides support for an MIPS 4Kc/24Kc CPU cores and these devices: + +* CP0 Interrupt Controller +* CP0 Core Timer +* NS16550 UART + + +.. note:: + This board configuration makes no claims about its suitability for use + with an actual MIPS Malta hardware system, or any other hardware system. + +Hardware +******** + +Supported Features +================== + +The following hardware features are supported: + ++----------------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++================+============+======================+ +| CP0 IntC | on-chip | interrupt controller | ++----------------+------------+----------------------+ +| CP0 Core Timer | on-chip | system clock | ++----------------+------------+----------------------+ +| NS16550 | FPGA | serial port | +| UART | | | ++----------------+------------+----------------------+ + +The kernel currently does not support other hardware features on this platform. + +Devices +======== +System Clock +------------ + +Qemu CP0 timer uses a clock frequency of 200 MHz, +see target/mips/cp0_timer.c in Qemu source tree for details. + +Serial Port +----------- + +This board configuration uses a single serial communication channel +with the FPGA UART2. + +Programming and Debugging +************************* + +Use this configuration to run basic Zephyr applications and kernel tests in the QEMU +emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_malta + :goals: run + +This will build an image with the synchronization sample app, boot it using +QEMU, and display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build v2.7.99-1627-g9bea7790d620 *** + thread_a: Hello World from cpu 0 on qemu_malta! + thread_b: Hello World from cpu 0 on qemu_malta! + thread_a: Hello World from cpu 0 on qemu_malta! + thread_b: Hello World from cpu 0 on qemu_malta! + thread_a: Hello World from cpu 0 on qemu_malta! + thread_b: Hello World from cpu 0 on qemu_malta! + thread_a: Hello World from cpu 0 on qemu_malta! + thread_b: Hello World from cpu 0 on qemu_malta! + thread_a: Hello World from cpu 0 on qemu_malta! + thread_b: Hello World from cpu 0 on qemu_malta! + + +Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. + + +Big-Endian +========== + +Use this configuration to run :zephyr:code-sample:`synchronization` sample in big-endian mode: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_malta//be + :goals: run + + +References +********** + +https://www.qemu.org/ +https://www.linux-mips.org/wiki/MIPS_Malta diff --git a/boards/mips/qemu_malta/qemu_malta.dts b/boards/qemu/malta/qemu_malta.dts similarity index 100% rename from boards/mips/qemu_malta/qemu_malta.dts rename to boards/qemu/malta/qemu_malta.dts diff --git a/boards/mips/qemu_malta/qemu_malta.yaml b/boards/qemu/malta/qemu_malta.yaml similarity index 100% rename from boards/mips/qemu_malta/qemu_malta.yaml rename to boards/qemu/malta/qemu_malta.yaml diff --git a/boards/qemu/malta/qemu_malta_defconfig b/boards/qemu/malta/qemu_malta_defconfig new file mode 100644 index 00000000000..fe217db926b --- /dev/null +++ b/boards/qemu/malta/qemu_malta_defconfig @@ -0,0 +1,6 @@ +CONFIG_MIPS_CP0_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT=y +CONFIG_QEMU_ICOUNT_SHIFT=3 diff --git a/boards/mips/qemu_malta/qemu_malta_be.dts b/boards/qemu/malta/qemu_malta_qemu_malta_be.dts similarity index 100% rename from boards/mips/qemu_malta/qemu_malta_be.dts rename to boards/qemu/malta/qemu_malta_qemu_malta_be.dts diff --git a/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml b/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml new file mode 100644 index 00000000000..98aa9884dbf --- /dev/null +++ b/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml @@ -0,0 +1,16 @@ +identifier: qemu_malta//be +name: QEMU emulation for MIPS (big endian) +type: qemu +simulation: qemu +arch: mips +toolchain: + - zephyr + - xtools +ram: 1024 +flash: 512 +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: qemu diff --git a/boards/qemu/malta/qemu_malta_qemu_malta_be_defconfig b/boards/qemu/malta/qemu_malta_qemu_malta_be_defconfig new file mode 100644 index 00000000000..fe217db926b --- /dev/null +++ b/boards/qemu/malta/qemu_malta_qemu_malta_be_defconfig @@ -0,0 +1,6 @@ +CONFIG_MIPS_CP0_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT=y +CONFIG_QEMU_ICOUNT_SHIFT=3 diff --git a/boards/qemu/nios2/Kconfig b/boards/qemu/nios2/Kconfig new file mode 100644 index 00000000000..22dbe917954 --- /dev/null +++ b/boards/qemu/nios2/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_NIOS2 + select QEMU_TARGET diff --git a/boards/qemu/nios2/Kconfig.defconfig b/boards/qemu/nios2/Kconfig.defconfig new file mode 100644 index 00000000000..81494ff905e --- /dev/null +++ b/boards/qemu/nios2/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_NIOS2 + +config BUILD_OUTPUT_BIN + default n + +endif diff --git a/boards/qemu/nios2/Kconfig.qemu_nios2 b/boards/qemu/nios2/Kconfig.qemu_nios2 new file mode 100644 index 00000000000..23292f07ffb --- /dev/null +++ b/boards/qemu/nios2/Kconfig.qemu_nios2 @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_NIOS2 + select SOC_QEMU_NIOS2 diff --git a/boards/qemu/nios2/board.cmake b/boards/qemu/nios2/board.cmake new file mode 100644 index 00000000000..9f9bf21124c --- /dev/null +++ b/boards/qemu/nios2/board.cmake @@ -0,0 +1,13 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(QEMU_CPU_TYPE_${ARCH} nios2) + +set(QEMU_FLAGS_${ARCH} + -machine altera_10m50_zephyr + -nographic + ) + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/nios2/board.yml b/boards/qemu/nios2/board.yml new file mode 100644 index 00000000000..93f6487d318 --- /dev/null +++ b/boards/qemu/nios2/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_nios2 + vendor: altr + socs: + - name: qemu_nios2 diff --git a/boards/nios2/qemu_nios2/doc/index.rst b/boards/qemu/nios2/doc/index.rst similarity index 100% rename from boards/nios2/qemu_nios2/doc/index.rst rename to boards/qemu/nios2/doc/index.rst diff --git a/boards/nios2/qemu_nios2/qemu_nios2.dts b/boards/qemu/nios2/qemu_nios2.dts similarity index 100% rename from boards/nios2/qemu_nios2/qemu_nios2.dts rename to boards/qemu/nios2/qemu_nios2.dts diff --git a/boards/nios2/qemu_nios2/qemu_nios2.yaml b/boards/qemu/nios2/qemu_nios2.yaml similarity index 100% rename from boards/nios2/qemu_nios2/qemu_nios2.yaml rename to boards/qemu/nios2/qemu_nios2.yaml diff --git a/boards/nios2/qemu_nios2/qemu_nios2_defconfig b/boards/qemu/nios2/qemu_nios2_defconfig similarity index 80% rename from boards/nios2/qemu_nios2/qemu_nios2_defconfig rename to boards/qemu/nios2/qemu_nios2_defconfig index 7820e1f8fc5..feda1075277 100644 --- a/boards/nios2/qemu_nios2/qemu_nios2_defconfig +++ b/boards/qemu/nios2/qemu_nios2_defconfig @@ -1,7 +1,6 @@ +# Copyright (c) 2018 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_NIOS2_QEMU=y -CONFIG_BOARD_QEMU_NIOS2=y CONFIG_HAS_ALTERA_HAL=y CONFIG_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/qemu/riscv32/Kconfig b/boards/qemu/riscv32/Kconfig new file mode 100644 index 00000000000..96de9ecb507 --- /dev/null +++ b/boards/qemu/riscv32/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32 + select QEMU_TARGET diff --git a/boards/qemu/riscv32/Kconfig.defconfig b/boards/qemu/riscv32/Kconfig.defconfig new file mode 100644 index 00000000000..8564054e21d --- /dev/null +++ b/boards/qemu/riscv32/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_RISCV32 + +# Use thread local storage by default so that this feature gets more CI coverage. +config THREAD_LOCAL_STORAGE + default y + +config BUILD_OUTPUT_BIN + default n + +config HAS_COVERAGE_SUPPORT + default y + +config QEMU_ICOUNT_SHIFT + default 6 if QEMU_ICOUNT + +endif # BOARD_QEMU_RISCV32 diff --git a/boards/qemu/riscv32/Kconfig.qemu_riscv32 b/boards/qemu/riscv32/Kconfig.qemu_riscv32 new file mode 100644 index 00000000000..39f614e955b --- /dev/null +++ b/boards/qemu/riscv32/Kconfig.qemu_riscv32 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32 + select SOC_QEMU_VIRT_RISCV32 diff --git a/boards/qemu/riscv32/board.cmake b/boards/qemu/riscv32/board.cmake new file mode 100644 index 00000000000..1e13b4b5176 --- /dev/null +++ b/boards/qemu/riscv32/board.cmake @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(QEMU_binary_suffix riscv32) +set(QEMU_CPU_TYPE_${ARCH} riscv32) + +set(QEMU_FLAGS_${ARCH} + -nographic + -machine virt + -bios none + -m 256 +) + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/riscv32/board.yml b/boards/qemu/riscv32/board.yml new file mode 100644 index 00000000000..0ba208612a9 --- /dev/null +++ b/boards/qemu/riscv32/board.yml @@ -0,0 +1,7 @@ +board: + name: qemu_riscv32 + vendor: qemu + socs: + - name: qemu_virt_riscv32 + variants: + - name: smp diff --git a/boards/riscv/qemu_riscv32/doc/index.rst b/boards/qemu/riscv32/doc/index.rst similarity index 100% rename from boards/riscv/qemu_riscv32/doc/index.rst rename to boards/qemu/riscv32/doc/index.rst diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32.dts b/boards/qemu/riscv32/qemu_riscv32.dts similarity index 100% rename from boards/riscv/qemu_riscv32/qemu_riscv32.dts rename to boards/qemu/riscv32/qemu_riscv32.dts diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32.yaml b/boards/qemu/riscv32/qemu_riscv32.yaml similarity index 100% rename from boards/riscv/qemu_riscv32/qemu_riscv32.yaml rename to boards/qemu/riscv32/qemu_riscv32.yaml diff --git a/boards/qemu/riscv32/qemu_riscv32_defconfig b/boards/qemu/riscv32/qemu_riscv32_defconfig new file mode 100644 index 00000000000..7a822571bb3 --- /dev/null +++ b/boards/qemu/riscv32/qemu_riscv32_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_STACK_SENTINEL=y +CONFIG_XIP=n +CONFIG_RISCV_PMP=y diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml new file mode 100644 index 00000000000..ee9af4a3083 --- /dev/null +++ b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml @@ -0,0 +1,16 @@ +identifier: qemu_riscv32/qemu_virt_riscv32/smp +name: QEMU Emulation for RISC-V 32-bit SMP +type: qemu +simulation: qemu +arch: riscv +toolchain: + - zephyr + - xtools +supported: + - netif + - smp +testing: + default: true + ignore_tags: + - net + - bluetooth diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig new file mode 100644 index 00000000000..412b05982f3 --- /dev/null +++ b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_IDLE_STACK_SIZE=1024 +CONFIG_QEMU_ICOUNT=n diff --git a/boards/qemu/riscv32_xip/Kconfig b/boards/qemu/riscv32_xip/Kconfig new file mode 100644 index 00000000000..233b31d0f18 --- /dev/null +++ b/boards/qemu/riscv32_xip/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32_XIP + select QEMU_TARGET diff --git a/boards/qemu/riscv32_xip/Kconfig.defconfig b/boards/qemu/riscv32_xip/Kconfig.defconfig new file mode 100644 index 00000000000..27142fceed5 --- /dev/null +++ b/boards/qemu/riscv32_xip/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_RISCV32_XIP + +# Use thread local storage by default so that this feature gets more CI coverage. +config THREAD_LOCAL_STORAGE + default y + +config BUILD_OUTPUT_BIN + default n + +config HAS_COVERAGE_SUPPORT + default y + +endif # BOARD_QEMU_RISCV32_XIP diff --git a/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip b/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip new file mode 100644 index 00000000000..ac31b7857eb --- /dev/null +++ b/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32_XIP + select SOC_SIFIVE_FREEDOM_FE310 diff --git a/boards/qemu/riscv32_xip/board.cmake b/boards/qemu/riscv32_xip/board.cmake new file mode 100644 index 00000000000..d1132858b48 --- /dev/null +++ b/boards/qemu/riscv32_xip/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(QEMU_binary_suffix riscv32) +set(QEMU_CPU_TYPE_${ARCH} riscv32) + +set(QEMU_FLAGS_${ARCH} + -nographic + -machine sifive_e +) + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/riscv32_xip/board.yml b/boards/qemu/riscv32_xip/board.yml new file mode 100644 index 00000000000..beca29532f4 --- /dev/null +++ b/boards/qemu/riscv32_xip/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_riscv32_xip + vendor: qemu + socs: + - name: fe310 diff --git a/boards/qemu/riscv32_xip/doc/index.rst b/boards/qemu/riscv32_xip/doc/index.rst new file mode 100644 index 00000000000..4cc4f30522f --- /dev/null +++ b/boards/qemu/riscv32_xip/doc/index.rst @@ -0,0 +1,55 @@ +.. _qemu_riscv32_xip: + +RISCV32 XIP Emulation (QEMU) +############################ + +Overview +******** + +The RISCV32 XIP QEMU board configuration is used to emulate the RISCV32 architecture. + +Programming and Debugging +************************* + +Applications for the ``qemu_riscv32_xip`` board configuration can be built and run in +the usual way for emulated boards (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +While this board is emulated and you can't "flash" it, you can use this +configuration to run basic Zephyr applications and kernel tests in the QEMU +emulated environment. For example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_riscv32_xip + :goals: run + +This will build an image with the synchronization sample app, boot it using +QEMU, and display the following console output: + +.. code-block:: console + + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + +Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_xip-pinctrl.dtsi b/boards/qemu/riscv32_xip/qemu_riscv32_xip-pinctrl.dtsi similarity index 100% rename from boards/riscv/qemu_riscv32/qemu_riscv32_xip-pinctrl.dtsi rename to boards/qemu/riscv32_xip/qemu_riscv32_xip-pinctrl.dtsi diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_xip.dts b/boards/qemu/riscv32_xip/qemu_riscv32_xip.dts similarity index 100% rename from boards/riscv/qemu_riscv32/qemu_riscv32_xip.dts rename to boards/qemu/riscv32_xip/qemu_riscv32_xip.dts diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_xip.yaml b/boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml similarity index 100% rename from boards/riscv/qemu_riscv32/qemu_riscv32_xip.yaml rename to boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml diff --git a/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig b/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig new file mode 100644 index 00000000000..f9bc269d13f --- /dev/null +++ b/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_PINCTRL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 +CONFIG_QEMU_ICOUNT_SHIFT=6 +CONFIG_RISCV_CORE_E31=y diff --git a/boards/qemu/riscv32e/Kconfig b/boards/qemu/riscv32e/Kconfig new file mode 100644 index 00000000000..515c3d7287a --- /dev/null +++ b/boards/qemu/riscv32e/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32E + select QEMU_TARGET diff --git a/boards/qemu/riscv32e/Kconfig.defconfig b/boards/qemu/riscv32e/Kconfig.defconfig new file mode 100644 index 00000000000..c3424c8722a --- /dev/null +++ b/boards/qemu/riscv32e/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_RISCV32E + +# Use thread local storage by default so that this feature gets more CI coverage. +config THREAD_LOCAL_STORAGE + default y + +config BUILD_OUTPUT_BIN + default n + +config HAS_COVERAGE_SUPPORT + default y + +endif # BOARD_QEMU_RISCV32E diff --git a/boards/qemu/riscv32e/Kconfig.qemu_riscv32e b/boards/qemu/riscv32e/Kconfig.qemu_riscv32e new file mode 100644 index 00000000000..f1256088e61 --- /dev/null +++ b/boards/qemu/riscv32e/Kconfig.qemu_riscv32e @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32E + select SOC_QEMU_VIRT_RISCV32E diff --git a/boards/riscv/qemu_riscv32e/board.cmake b/boards/qemu/riscv32e/board.cmake similarity index 100% rename from boards/riscv/qemu_riscv32e/board.cmake rename to boards/qemu/riscv32e/board.cmake diff --git a/boards/qemu/riscv32e/board.yml b/boards/qemu/riscv32e/board.yml new file mode 100644 index 00000000000..cc8e6f0becc --- /dev/null +++ b/boards/qemu/riscv32e/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_riscv32e + vendor: qemu + socs: + - name: qemu_virt_riscv32e diff --git a/boards/riscv/qemu_riscv32e/doc/index.rst b/boards/qemu/riscv32e/doc/index.rst similarity index 100% rename from boards/riscv/qemu_riscv32e/doc/index.rst rename to boards/qemu/riscv32e/doc/index.rst diff --git a/boards/riscv/qemu_riscv32e/qemu_riscv32e.dts b/boards/qemu/riscv32e/qemu_riscv32e.dts similarity index 100% rename from boards/riscv/qemu_riscv32e/qemu_riscv32e.dts rename to boards/qemu/riscv32e/qemu_riscv32e.dts diff --git a/boards/riscv/qemu_riscv32e/qemu_riscv32e.yaml b/boards/qemu/riscv32e/qemu_riscv32e.yaml similarity index 100% rename from boards/riscv/qemu_riscv32e/qemu_riscv32e.yaml rename to boards/qemu/riscv32e/qemu_riscv32e.yaml diff --git a/boards/riscv/qemu_riscv32e/qemu_riscv32e_defconfig b/boards/qemu/riscv32e/qemu_riscv32e_defconfig similarity index 76% rename from boards/riscv/qemu_riscv32e/qemu_riscv32e_defconfig rename to boards/qemu/riscv32e/qemu_riscv32e_defconfig index 1f1c46acb10..affc1eeffb7 100644 --- a/boards/riscv/qemu_riscv32e/qemu_riscv32e_defconfig +++ b/boards/qemu/riscv32e/qemu_riscv32e_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_RISCV_VIRT=y -CONFIG_BOARD_QEMU_RISCV32E=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/qemu/riscv64/Kconfig b/boards/qemu/riscv64/Kconfig new file mode 100644 index 00000000000..6adb7c15032 --- /dev/null +++ b/boards/qemu/riscv64/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV64 + select QEMU_TARGET diff --git a/boards/qemu/riscv64/Kconfig.defconfig b/boards/qemu/riscv64/Kconfig.defconfig new file mode 100644 index 00000000000..90a501d002d --- /dev/null +++ b/boards/qemu/riscv64/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_RISCV64 + +config BUILD_OUTPUT_BIN + default n + +config HAS_COVERAGE_SUPPORT + default y + +config QEMU_ICOUNT_SHIFT + default 6 if QEMU_ICOUNT + +endif # BOARD_QEMU_RISCV64 diff --git a/boards/qemu/riscv64/Kconfig.qemu_riscv64 b/boards/qemu/riscv64/Kconfig.qemu_riscv64 new file mode 100644 index 00000000000..7d136aebb22 --- /dev/null +++ b/boards/qemu/riscv64/Kconfig.qemu_riscv64 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV64 + select SOC_QEMU_VIRT_RISCV64 diff --git a/boards/riscv/qemu_riscv64/board.cmake b/boards/qemu/riscv64/board.cmake similarity index 100% rename from boards/riscv/qemu_riscv64/board.cmake rename to boards/qemu/riscv64/board.cmake diff --git a/boards/qemu/riscv64/board.yml b/boards/qemu/riscv64/board.yml new file mode 100644 index 00000000000..aa51fd1fdba --- /dev/null +++ b/boards/qemu/riscv64/board.yml @@ -0,0 +1,7 @@ +board: + name: qemu_riscv64 + vendor: qemu + socs: + - name: qemu_virt_riscv64 + variants: + - name: smp diff --git a/boards/riscv/qemu_riscv64/doc/index.rst b/boards/qemu/riscv64/doc/index.rst similarity index 100% rename from boards/riscv/qemu_riscv64/doc/index.rst rename to boards/qemu/riscv64/doc/index.rst diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64.dts b/boards/qemu/riscv64/qemu_riscv64.dts similarity index 100% rename from boards/riscv/qemu_riscv64/qemu_riscv64.dts rename to boards/qemu/riscv64/qemu_riscv64.dts diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64.yaml b/boards/qemu/riscv64/qemu_riscv64.yaml similarity index 100% rename from boards/riscv/qemu_riscv64/qemu_riscv64.yaml rename to boards/qemu/riscv64/qemu_riscv64.yaml diff --git a/boards/qemu/riscv64/qemu_riscv64_defconfig b/boards/qemu/riscv64/qemu_riscv64_defconfig new file mode 100644 index 00000000000..18dbae0da77 --- /dev/null +++ b/boards/qemu/riscv64/qemu_riscv64_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_PRIVILEGED_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_STACK_SENTINEL=y +CONFIG_XIP=n +CONFIG_RISCV_PMP=y diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml new file mode 100644 index 00000000000..3b39ef7499d --- /dev/null +++ b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml @@ -0,0 +1,15 @@ +identifier: qemu_riscv64/qemu_virt_riscv64/smp +name: QEMU Emulation for RISC-V 64-bit SMP +type: qemu +simulation: qemu +arch: riscv +toolchain: + - zephyr +supported: + - netif + - smp +testing: + default: true + ignore_tags: + - net + - bluetooth diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig new file mode 100644 index 00000000000..412b05982f3 --- /dev/null +++ b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_IDLE_STACK_SIZE=1024 +CONFIG_QEMU_ICOUNT=n diff --git a/boards/qemu/x86/CMakeLists.txt b/boards/qemu/x86/CMakeLists.txt new file mode 100644 index 00000000000..1f37a49df8c --- /dev/null +++ b/boards/qemu/x86/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +if(CONFIG_BOARD_QEMU_X86_64 AND CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -i ${ZEPHYR_BASE}/include + -o ${CMAKE_OBJCOPY} + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/qemu/x86/Kconfig b/boards/qemu/x86/Kconfig new file mode 100644 index 00000000000..092f34f453d --- /dev/null +++ b/boards/qemu/x86/Kconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_X86 + bool + select CPU_HAS_FPU + +config BOARD_QEMU_X86_64 + bool + select X86_64 + +config BOARD_QEMU_X86_LAKEMONT + bool + select CPU_HAS_FPU + +config BOARD_QEMU_X86_TINY + bool + select CPU_HAS_FPU diff --git a/boards/qemu/x86/Kconfig.defconfig b/boards/qemu/x86/Kconfig.defconfig new file mode 100644 index 00000000000..5afe94d68e5 --- /dev/null +++ b/boards/qemu/x86/Kconfig.defconfig @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +if BOARD_QEMU_X86 || BOARD_QEMU_X86_64 || BOARD_QEMU_X86_LAKEMONT || BOARD_QEMU_X86_TINY + +# The EEPROM emulator must be initialized after the flash simulator +config EEPROM_INIT_PRIORITY + default 60 + depends on EEPROM + +config BUILD_OUTPUT_BIN + default n + +config QEMU_TARGET + default y + +config HAS_COVERAGE_SUPPORT + default y + +endif # BOARD_QEMU_X86 || BOARD_QEMU_X86_64 || BOARD_QEMU_X86_LAKEMONT || BOARD_QEMU_X86_TINY + + +if BOARD_QEMU_X86 + +config FLASH_SIMULATOR + default y + depends on FLASH + +config KERNEL_VM_SIZE + default 0x10000000 if ACPI + +config MULTIBOOT + default y + +config MULTIBOOT_INFO + default y if MULTIBOOT + +config MULTIBOOT_MEMMAP + default y if MULTIBOOT + +config QEMU_ICOUNT + default n if HPET_TIMER && SHELL + +config QEMU_ICOUNT_SHIFT + default 5 + +endif # BOARD_QEMU_X86 + + +if BOARD_QEMU_X86_64 + +config KERNEL_VM_SIZE + default 0x10000000 if ACPI + +endif # BOARD_QEMU_X86_64 + + +if BOARD_QEMU_X86_LAKEMONT + +config KERNEL_VM_SIZE + default 0x400000 + +config MULTIBOOT + # This is needed for QEMU to load the ELF image + default y + +config X86_PC_COMPATIBLE + # QEMU presents a PC-compatible machine + default y + +config QEMU_ICOUNT + default n if HPET_TIMER && SHELL + +config QEMU_ICOUNT_SHIFT + default 5 + +endif # BOARD_QEMU_X86_LAKEMONT + + +if BOARD_QEMU_X86_TINY + +config KERNEL_VM_SIZE + default 0x400000 + +config MULTIBOOT + # This is needed for QEMU to load the ELF image + default y + +config X86_PC_COMPATIBLE + # QEMU presents a PC-compatible machine + default y + +config QEMU_ICOUNT + default n if HPET_TIMER && SHELL + +config QEMU_ICOUNT_SHIFT + default 5 + +config HAVE_CUSTOM_LINKER_SCRIPT + default y + +config CUSTOM_LINKER_SCRIPT + default "${ZEPHYR_BASE}/boards/qemu/x86/qemu_x86_tiny.ld" + +config X86_EXTRA_PAGE_TABLE_PAGES + # This is needed for gen_mmu.py to map the flash into memory + default 2 if DEMAND_PAGING && !LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT + +config DEMAND_PAGING_PAGE_FRAMES_RESERVE + # Need to accommodate the heap for newlib or common malloc in libc-hook.c + default 6 if NEWLIB_LIBC || (COMMON_LIBC_MALLOC && COMMON_LIBC_MALLOC_ARENA_SIZE != 0) + +endif # BOARD_QEMU_X86_TINY diff --git a/boards/qemu/x86/Kconfig.qemu_x86 b/boards/qemu/x86/Kconfig.qemu_x86 new file mode 100644 index 00000000000..126afd6fd68 --- /dev/null +++ b/boards/qemu/x86/Kconfig.qemu_x86 @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_X86 + select SOC_ATOM diff --git a/boards/qemu/x86/Kconfig.qemu_x86_64 b/boards/qemu/x86/Kconfig.qemu_x86_64 new file mode 100644 index 00000000000..2ee42f2b211 --- /dev/null +++ b/boards/qemu/x86/Kconfig.qemu_x86_64 @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_X86_64 + select SOC_ATOM diff --git a/boards/qemu/x86/Kconfig.qemu_x86_lakemont b/boards/qemu/x86/Kconfig.qemu_x86_lakemont new file mode 100644 index 00000000000..f48e1b99c2a --- /dev/null +++ b/boards/qemu/x86/Kconfig.qemu_x86_lakemont @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_X86_LAKEMONT + select SOC_LAKEMONT diff --git a/boards/qemu/x86/Kconfig.qemu_x86_tiny b/boards/qemu/x86/Kconfig.qemu_x86_tiny new file mode 100644 index 00000000000..c6468168f9e --- /dev/null +++ b/boards/qemu/x86/Kconfig.qemu_x86_tiny @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_X86_TINY + select SOC_ATOM diff --git a/boards/qemu/x86/board.cmake b/boards/qemu/x86/board.cmake new file mode 100644 index 00000000000..2738f43bdde --- /dev/null +++ b/boards/qemu/x86/board.cmake @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +set(SUPPORTED_EMU_PLATFORMS qemu) + +if(NOT CONFIG_REBOOT) + set(REBOOT_FLAG -no-reboot) +endif() + +if(CONFIG_X86_64) + set(QEMU_binary_suffix x86_64) + set(QEMU_CPU_TYPE_${ARCH} qemu64,+x2apic) + if("${CONFIG_MP_MAX_NUM_CPUS}" STREQUAL "1") + # icount works with 1 CPU so we can enable it here. + # FIXME: once this works across configs, remove this line and set + # CONFIG_QEMU_ICOUNT_SHIFT in defconfig instead. + list(APPEND QEMU_EXTRA_FLAGS -icount shift=5,align=off,sleep=off -rtc clock=vm) + endif() +else() + set(QEMU_CPU_TYPE_${ARCH} qemu32,+nx,+pae) +endif() + +if(CONFIG_XIP) + # Extra 4MB to emulate flash area + math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024 + 4") +elseif(CONFIG_BOARD_QEMU_X86_TINY AND CONFIG_DEMAND_PAGING + AND NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) + # Flash is at 4MB-8MB, so need this to be large enough + math(EXPR QEMU_MEMORY_SIZE_MB "8") +else() + math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024") +endif() + +set(QEMU_CPU_FLAGS "") +if(CONFIG_X86_MMX) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmx") + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmxext") +endif() +if(CONFIG_X86_SSE) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse") +endif() +if(CONFIG_X86_SSE2) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse2") +endif() +if(CONFIG_X86_SSE3) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "pni") +endif() +if(CONFIG_X86_SSSE3) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "ssse3") +endif() +if(CONFIG_X86_SSE41) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.1") +endif() +if(CONFIG_X86_SSE42) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.2") +endif() +if(CONFIG_X86_SSE4A) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4a") +endif() +if(NOT CONFIG_X86_64 AND CONFIG_CACHE_MANAGEMENT) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "clflush") +endif() + +set(QEMU_FLAGS_${ARCH} + -m ${QEMU_MEMORY_SIZE_MB} + -cpu ${QEMU_CPU_TYPE_${ARCH}}${QEMU_CPU_FLAGS} + -machine q35 + -device isa-debug-exit,iobase=0xf4,iosize=0x04 + ${REBOOT_FLAG} + -nographic + ) + +if(NOT CONFIG_ACPI) + list(APPEND QEMU_FLAGS_${ARCH} -no-acpi) +endif() + +# TODO: Support debug +# board_set_debugger_ifnset(qemu) +# debugserver: QEMU_EXTRA_FLAGS += -s -S +# debugserver: qemu + +if(CONFIG_BOARD_QEMU_X86_TINY AND CONFIG_DEMAND_PAGING + AND NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) + # This is to map the flash so it is accessible. + math(EXPR QEMU_FLASH_SIZE_KB "${CONFIG_FLASH_SIZE} * 1024") + set(X86_EXTRA_GEN_MMU_ARGUMENTS + --map ${CONFIG_FLASH_BASE_ADDRESS},${QEMU_FLASH_SIZE_KB},W) +endif() diff --git a/boards/qemu/x86/board.yml b/boards/qemu/x86/board.yml new file mode 100644 index 00000000000..75d0cd6eb4b --- /dev/null +++ b/boards/qemu/x86/board.yml @@ -0,0 +1,25 @@ +boards: + + - name: qemu_x86 + socs: + - name: atom + variants: + - name: 'nokpti' + - name: 'nommu' + - name: 'nopae' + - name: 'virt' + - name: 'xip' + + - name: qemu_x86_lakemont + socs: + - name: lakemont + + - name: qemu_x86_64 + socs: + - name: atom + variants: + - name: 'nokpti' + + - name: qemu_x86_tiny + socs: + - name: atom diff --git a/boards/x86/qemu_x86/doc/index.rst b/boards/qemu/x86/doc/index.rst similarity index 100% rename from boards/x86/qemu_x86/doc/index.rst rename to boards/qemu/x86/doc/index.rst diff --git a/boards/x86/qemu_x86/qemu_x86.dts b/boards/qemu/x86/qemu_x86.dts similarity index 97% rename from boards/x86/qemu_x86/qemu_x86.dts rename to boards/qemu/x86/qemu_x86.dts index 6117d7927ab..85e3f56c36e 100644 --- a/boards/x86/qemu_x86/qemu_x86.dts +++ b/boards/qemu/x86/qemu_x86.dts @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright (c) 2019 Intel Corp. */ /dts-v1/; @@ -12,7 +13,7 @@ #endif #define DT_FLASH_SIZE DT_SIZE_K(4096) -#include +#include #include / { diff --git a/boards/x86/qemu_x86/qemu_x86.yaml b/boards/qemu/x86/qemu_x86.yaml similarity index 100% rename from boards/x86/qemu_x86/qemu_x86.yaml rename to boards/qemu/x86/qemu_x86.yaml diff --git a/boards/x86/qemu_x86/qemu_x86_64.dts b/boards/qemu/x86/qemu_x86_64.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_64.dts rename to boards/qemu/x86/qemu_x86_64.dts diff --git a/boards/x86/qemu_x86/qemu_x86_64.yaml b/boards/qemu/x86/qemu_x86_64.yaml similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_64.yaml rename to boards/qemu/x86/qemu_x86_64.yaml diff --git a/boards/x86/qemu_x86/qemu_x86_64_nokpti.dts b/boards/qemu/x86/qemu_x86_64_atom_nokpti.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_64_nokpti.dts rename to boards/qemu/x86/qemu_x86_64_atom_nokpti.dts diff --git a/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml new file mode 100644 index 00000000000..22033bdc24d --- /dev/null +++ b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml @@ -0,0 +1,18 @@ +identifier: qemu_x86_64/atom/nokpti +name: QEMU Emulation for X86_64 (KPTI disabled) +type: qemu +arch: x86 +toolchain: + - zephyr + - xtools +supported: + - smp +simulation: qemu +testing: + default: true + only_tags: + - kernel + - userspace + ignore_tags: + - benchmark +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig b/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig new file mode 100644 index 00000000000..01dd154ba5a --- /dev/null +++ b/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_X86_KPTI=n diff --git a/boards/x86/qemu_x86/qemu_x86_64_defconfig b/boards/qemu/x86/qemu_x86_64_defconfig similarity index 88% rename from boards/x86/qemu_x86/qemu_x86_64_defconfig rename to boards/qemu/x86/qemu_x86_64_defconfig index 9f37e55e138..9ca58bfcb70 100644 --- a/boards/x86/qemu_x86/qemu_x86_64_defconfig +++ b/boards/qemu/x86/qemu_x86_64_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86_64=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/qemu_x86/qemu_x86_nokpti.dts b/boards/qemu/x86/qemu_x86_atom_nokpti.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_nokpti.dts rename to boards/qemu/x86/qemu_x86_atom_nokpti.dts diff --git a/boards/qemu/x86/qemu_x86_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml new file mode 100644 index 00000000000..54b8d1857d9 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml @@ -0,0 +1,16 @@ +identifier: qemu_x86/atom/nokpti +name: QEMU Emulation for X86 (KPTI disabled) +type: qemu +arch: x86 +simulation: qemu +toolchain: + - zephyr + - xtools +testing: + default: true + only_tags: + - kernel + - userspace + ignore_tags: + - benchmark +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig b/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig new file mode 100644 index 00000000000..01dd154ba5a --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_X86_KPTI=n diff --git a/boards/qemu/x86/qemu_x86_atom_nommu.dts b/boards/qemu/x86/qemu_x86_atom_nommu.dts new file mode 100644 index 00000000000..0713146821d --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nommu.dts @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright (c) 2019 Intel Corp. */ + +#include "qemu_x86.dts" diff --git a/boards/qemu/x86/qemu_x86_atom_nommu.yaml b/boards/qemu/x86/qemu_x86_atom_nommu.yaml new file mode 100644 index 00000000000..1076c2f3f87 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nommu.yaml @@ -0,0 +1,14 @@ +identifier: qemu_x86/atom/nommu +name: QEMU Emulation for X86 (MMU disabled) +type: qemu +arch: x86 +simulation: qemu +toolchain: + - zephyr + - xtools +testing: + default: true + only_tags: + - kernel + - userspace +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_nommu_defconfig b/boards/qemu/x86/qemu_x86_atom_nommu_defconfig new file mode 100644 index 00000000000..32dbada07b4 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nommu_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_X86_MMU=n +CONFIG_SCHED_DUMB=y +CONFIG_WAITQ_DUMB=y +CONFIG_X86_VERY_EARLY_CONSOLE=n diff --git a/boards/x86/qemu_x86/qemu_x86_nopae.dts b/boards/qemu/x86/qemu_x86_atom_nopae.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_nopae.dts rename to boards/qemu/x86/qemu_x86_atom_nopae.dts diff --git a/boards/qemu/x86/qemu_x86_atom_nopae.yaml b/boards/qemu/x86/qemu_x86_atom_nopae.yaml new file mode 100644 index 00000000000..2d3b46acc3f --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nopae.yaml @@ -0,0 +1,16 @@ +identifier: qemu_x86/atom/nopae +name: QEMU Emulation for X86 (32-bit page tables) +type: qemu +arch: x86 +simulation: qemu +toolchain: + - zephyr + - xtools +testing: + default: true + only_tags: + - kernel + - userspace + ignore_tags: + - benchmark +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_nopae_defconfig b/boards/qemu/x86/qemu_x86_atom_nopae_defconfig new file mode 100644 index 00000000000..36ec7d7d8e5 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nopae_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_X86_PAE=n diff --git a/boards/x86/qemu_x86/qemu_x86_virt.dts b/boards/qemu/x86/qemu_x86_atom_virt.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_virt.dts rename to boards/qemu/x86/qemu_x86_atom_virt.dts diff --git a/boards/qemu/x86/qemu_x86_atom_virt.yaml b/boards/qemu/x86/qemu_x86_atom_virt.yaml new file mode 100644 index 00000000000..ac656ad922d --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_virt.yaml @@ -0,0 +1,16 @@ +identifier: qemu_x86/atom/virt +name: QEMU Emulation for X86 (Run in Virtual Address Space) +type: qemu +arch: x86 +simulation: qemu +toolchain: + - zephyr + - xtools +testing: + default: true + only_tags: + - kernel + - userspace + ignore_tags: + - benchmark +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_virt_defconfig b/boards/qemu/x86/qemu_x86_atom_virt_defconfig new file mode 100644 index 00000000000..6c1679d7728 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_virt_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_SRAM_OFFSET=0x100000 +CONFIG_KERNEL_VM_SIZE=0x400000 +CONFIG_KERNEL_VM_BASE=0x40000000 +CONFIG_KERNEL_VM_OFFSET=0 + +CONFIG_LINKER_USE_BOOT_SECTION=y +CONFIG_LINKER_USE_PINNED_SECTION=y diff --git a/boards/x86/qemu_x86/qemu_x86_xip.dts b/boards/qemu/x86/qemu_x86_atom_xip.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_xip.dts rename to boards/qemu/x86/qemu_x86_atom_xip.dts diff --git a/boards/qemu/x86/qemu_x86_atom_xip.yaml b/boards/qemu/x86/qemu_x86_atom_xip.yaml new file mode 100644 index 00000000000..f55d0b2097a --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_xip.yaml @@ -0,0 +1,13 @@ +identifier: qemu_x86/atom/xip +name: QEMU Emulation for X86 (XIP enabled) +type: qemu +arch: x86 +simulation: qemu +toolchain: + - zephyr + - xtools +testing: + default: true + only_tags: + - xip +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_xip_defconfig b/boards/qemu/x86/qemu_x86_atom_xip_defconfig new file mode 100644 index 00000000000..c186d568275 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_xip_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_X86_MMU=n +CONFIG_XIP=y diff --git a/boards/x86/qemu_x86/qemu_x86_defconfig b/boards/qemu/x86/qemu_x86_defconfig similarity index 88% rename from boards/x86/qemu_x86/qemu_x86_defconfig rename to boards/qemu/x86/qemu_x86_defconfig index 75320082a68..754f0a47c83 100644 --- a/boards/x86/qemu_x86/qemu_x86_defconfig +++ b/boards/qemu/x86/qemu_x86_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/qemu_x86/qemu_x86_lakemont.dts b/boards/qemu/x86/qemu_x86_lakemont.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_lakemont.dts rename to boards/qemu/x86/qemu_x86_lakemont.dts diff --git a/boards/x86/qemu_x86/qemu_x86_lakemont.yaml b/boards/qemu/x86/qemu_x86_lakemont.yaml similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_lakemont.yaml rename to boards/qemu/x86/qemu_x86_lakemont.yaml diff --git a/boards/x86/qemu_x86/qemu_x86_lakemont_defconfig b/boards/qemu/x86/qemu_x86_lakemont_defconfig similarity index 85% rename from boards/x86/qemu_x86/qemu_x86_lakemont_defconfig rename to boards/qemu/x86/qemu_x86_lakemont_defconfig index c4902a34a6c..754f0a47c83 100644 --- a/boards/x86/qemu_x86/qemu_x86_lakemont_defconfig +++ b/boards/qemu/x86/qemu_x86_lakemont_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. -CONFIG_SOC_LAKEMONT=y -CONFIG_BOARD_QEMU_X86_LAKEMONT=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/qemu_x86/qemu_x86_tiny.dts b/boards/qemu/x86/qemu_x86_tiny.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_tiny.dts rename to boards/qemu/x86/qemu_x86_tiny.dts diff --git a/boards/x86/qemu_x86/qemu_x86_tiny.ld b/boards/qemu/x86/qemu_x86_tiny.ld similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_tiny.ld rename to boards/qemu/x86/qemu_x86_tiny.ld diff --git a/boards/x86/qemu_x86/qemu_x86_tiny.yaml b/boards/qemu/x86/qemu_x86_tiny.yaml similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_tiny.yaml rename to boards/qemu/x86/qemu_x86_tiny.yaml diff --git a/boards/x86/qemu_x86/qemu_x86_tiny_defconfig b/boards/qemu/x86/qemu_x86_tiny_defconfig similarity index 93% rename from boards/x86/qemu_x86/qemu_x86_tiny_defconfig rename to boards/qemu/x86/qemu_x86_tiny_defconfig index 8b8111746f6..349e1b6ec71 100644 --- a/boards/x86/qemu_x86/qemu_x86_tiny_defconfig +++ b/boards/qemu/x86/qemu_x86_tiny_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86_TINY=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/qemu/xtensa/Kconfig b/boards/qemu/xtensa/Kconfig new file mode 100644 index 00000000000..8cdc6ec28ff --- /dev/null +++ b/boards/qemu/xtensa/Kconfig @@ -0,0 +1,9 @@ +# XTENSA board configuration + +# Copyright (c) 2017, 2023 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_XTENSA + select QEMU_TARGET + select ARCH_SUPPORTS_COREDUMP + select XTENSA_MMU if BOARD_QEMU_XTENSA_DC233C_MMU diff --git a/boards/qemu/xtensa/Kconfig.defconfig b/boards/qemu/xtensa/Kconfig.defconfig new file mode 100644 index 00000000000..081971b5e81 --- /dev/null +++ b/boards/qemu/xtensa/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2017, 2023 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_XTENSA + +config BUILD_OUTPUT_BIN + default n + +config IPM_CONSOLE_STACK_SIZE + default 2048 if IPM_CONSOLE_RECEIVER + +endif # BOARD_QEMU_XTENSA diff --git a/boards/qemu/xtensa/Kconfig.qemu_xtensa b/boards/qemu/xtensa/Kconfig.qemu_xtensa new file mode 100644 index 00000000000..f0aa1c8010c --- /dev/null +++ b/boards/qemu/xtensa/Kconfig.qemu_xtensa @@ -0,0 +1,7 @@ +# XTENSA board configuration + +# Copyright (c) 2017, 2023 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_XTENSA + select SOC_XTENSA_DC233C diff --git a/boards/qemu/xtensa/board.cmake b/boards/qemu/xtensa/board.cmake new file mode 100644 index 00000000000..40818845da6 --- /dev/null +++ b/boards/qemu/xtensa/board.cmake @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) + +if(CONFIG_BOARD_QEMU_XTENSA) + set(QEMU_CPU_TYPE_${ARCH} dc233c) + + set(QEMU_FLAGS_${ARCH} + -machine sim -semihosting -nographic -cpu dc233c + ) +endif() + +# TODO: Support debug +# board_set_debugger_ifnset(qemu) +# debugserver: QEMU_EXTRA_FLAGS += -s -S +# debugserver: qemu diff --git a/boards/qemu/xtensa/board.yml b/boards/qemu/xtensa/board.yml new file mode 100644 index 00000000000..1441dcc25fc --- /dev/null +++ b/boards/qemu/xtensa/board.yml @@ -0,0 +1,7 @@ +board: + name: qemu_xtensa + vendor: cdns + socs: + - name: dc233c + variants: + - name: mmu diff --git a/boards/xtensa/qemu_xtensa/doc/index.rst b/boards/qemu/xtensa/doc/index.rst similarity index 100% rename from boards/xtensa/qemu_xtensa/doc/index.rst rename to boards/qemu/xtensa/doc/index.rst diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa.dts b/boards/qemu/xtensa/qemu_xtensa.dts similarity index 100% rename from boards/xtensa/qemu_xtensa/qemu_xtensa.dts rename to boards/qemu/xtensa/qemu_xtensa.dts diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa.yaml b/boards/qemu/xtensa/qemu_xtensa.yaml similarity index 100% rename from boards/xtensa/qemu_xtensa/qemu_xtensa.yaml rename to boards/qemu/xtensa/qemu_xtensa.yaml diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu.dts b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.dts similarity index 100% rename from boards/xtensa/qemu_xtensa/qemu_xtensa_mmu.dts rename to boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.dts diff --git a/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml new file mode 100644 index 00000000000..61ab14c9130 --- /dev/null +++ b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml @@ -0,0 +1,13 @@ +identifier: qemu_xtensa/dc233c/mmu +name: QEMU Emulation for Xtensa with MMU +type: qemu +simulation: qemu +arch: xtensa +toolchain: + - zephyr + - xtools +testing: + default: true + ignore_tags: + - net + - bluetooth diff --git a/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu_defconfig b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu_defconfig new file mode 100644 index 00000000000..d23b5a9f174 --- /dev/null +++ b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 +CONFIG_STACK_SENTINEL=y +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n +CONFIG_SIMULATOR_XTENSA=y +CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa_defconfig b/boards/qemu/xtensa/qemu_xtensa_defconfig similarity index 82% rename from boards/xtensa/qemu_xtensa/qemu_xtensa_defconfig rename to boards/qemu/xtensa/qemu_xtensa_defconfig index ec51bb17a38..d23b5a9f174 100644 --- a/boards/xtensa/qemu_xtensa/qemu_xtensa_defconfig +++ b/boards/qemu/xtensa/qemu_xtensa_defconfig @@ -1,9 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_BOARD_QEMU_XTENSA=y CONFIG_CONSOLE=y -CONFIG_SOC_XTENSA_DC233C=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 CONFIG_STACK_SENTINEL=y CONFIG_GEN_ISR_TABLES=y diff --git a/boards/arm/decawave_dwm1001_dev/Kconfig b/boards/qorvo/decawave_dwm1001_dev/Kconfig similarity index 100% rename from boards/arm/decawave_dwm1001_dev/Kconfig rename to boards/qorvo/decawave_dwm1001_dev/Kconfig diff --git a/boards/qorvo/decawave_dwm1001_dev/Kconfig.decawave_dwm1001_dev b/boards/qorvo/decawave_dwm1001_dev/Kconfig.decawave_dwm1001_dev new file mode 100644 index 00000000000..ba9f6965b1d --- /dev/null +++ b/boards/qorvo/decawave_dwm1001_dev/Kconfig.decawave_dwm1001_dev @@ -0,0 +1,7 @@ +# DecaWave DWM1001 board configuration + +# Copyright (c) 2019 Stéphane D'Alu +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DECAWAVE_DWM1001_DEV + select SOC_NRF52832_QFAA diff --git a/boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig b/boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig new file mode 100644 index 00000000000..cd2a985b1eb --- /dev/null +++ b/boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig @@ -0,0 +1,18 @@ +# DecaWave DWM1001 board configuration + +# Copyright (c) 2019 Stéphane D'Alu +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_DECAWAVE_DWM1001_DEV + +config BT_CTLR + default BT + +config I2C + default SENSOR + +config SPI + default y + depends on IEEE802154 + +endif # BOARD_DECAWAVE_DWM1001_DEV diff --git a/boards/arm/decawave_dwm1001_dev/board.cmake b/boards/qorvo/decawave_dwm1001_dev/board.cmake similarity index 100% rename from boards/arm/decawave_dwm1001_dev/board.cmake rename to boards/qorvo/decawave_dwm1001_dev/board.cmake diff --git a/boards/qorvo/decawave_dwm1001_dev/board.yml b/boards/qorvo/decawave_dwm1001_dev/board.yml new file mode 100644 index 00000000000..f1d0ae7def0 --- /dev/null +++ b/boards/qorvo/decawave_dwm1001_dev/board.yml @@ -0,0 +1,5 @@ +board: + name: decawave_dwm1001_dev + vendor: qorvo + socs: + - name: nrf52832 diff --git a/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev-pinctrl.dtsi b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev-pinctrl.dtsi similarity index 100% rename from boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev-pinctrl.dtsi rename to boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev-pinctrl.dtsi diff --git a/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev.dts b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts similarity index 100% rename from boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev.dts rename to boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts diff --git a/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml similarity index 100% rename from boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml rename to boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml diff --git a/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig new file mode 100644 index 00000000000..bb14402e1bb --- /dev/null +++ b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_RTT_CONSOLE=y diff --git a/boards/arm/decawave_dwm1001_dev/doc/index.rst b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst similarity index 100% rename from boards/arm/decawave_dwm1001_dev/doc/index.rst rename to boards/qorvo/decawave_dwm1001_dev/doc/index.rst diff --git a/boards/arm/pinetime_devkit0/pre_dt_board.cmake b/boards/qorvo/decawave_dwm1001_dev/pre_dt_board.cmake similarity index 100% rename from boards/arm/pinetime_devkit0/pre_dt_board.cmake rename to boards/qorvo/decawave_dwm1001_dev/pre_dt_board.cmake diff --git a/boards/qorvo/index.rst b/boards/qorvo/index.rst new file mode 100644 index 00000000000..e7bd9b34aff --- /dev/null +++ b/boards/qorvo/index.rst @@ -0,0 +1,10 @@ +.. _boards-qorvo: + +Qorvo, Inc. +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/quicklogic/index.rst b/boards/quicklogic/index.rst new file mode 100644 index 00000000000..9c28f105053 --- /dev/null +++ b/boards/quicklogic/index.rst @@ -0,0 +1,10 @@ +.. _boards-quicklogic: + +QuickLogic Corp. +################ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/qomu/Kconfig b/boards/quicklogic/qomu/Kconfig similarity index 100% rename from boards/arm/qomu/Kconfig rename to boards/quicklogic/qomu/Kconfig diff --git a/boards/quicklogic/qomu/Kconfig.qomu b/boards/quicklogic/qomu/Kconfig.qomu new file mode 100644 index 00000000000..285ae1bf122 --- /dev/null +++ b/boards/quicklogic/qomu/Kconfig.qomu @@ -0,0 +1,7 @@ +# QuickLogic Qomu board + +# Copyright (c) 2022 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QOMU + select SOC_EOS_S3 diff --git a/boards/quicklogic/qomu/board.yml b/boards/quicklogic/qomu/board.yml new file mode 100644 index 00000000000..e71125610fa --- /dev/null +++ b/boards/quicklogic/qomu/board.yml @@ -0,0 +1,5 @@ +board: + name: qomu + vendor: quicklogic + socs: + - name: quicklogic_eos_s3 diff --git a/boards/arm/qomu/doc/img/qomu-board.png b/boards/quicklogic/qomu/doc/img/qomu-board.png similarity index 100% rename from boards/arm/qomu/doc/img/qomu-board.png rename to boards/quicklogic/qomu/doc/img/qomu-board.png diff --git a/boards/arm/qomu/doc/index.rst b/boards/quicklogic/qomu/doc/index.rst similarity index 100% rename from boards/arm/qomu/doc/index.rst rename to boards/quicklogic/qomu/doc/index.rst diff --git a/boards/arm/qomu/qomu.dts b/boards/quicklogic/qomu/qomu.dts similarity index 100% rename from boards/arm/qomu/qomu.dts rename to boards/quicklogic/qomu/qomu.dts diff --git a/boards/arm/qomu/qomu.yaml b/boards/quicklogic/qomu/qomu.yaml similarity index 100% rename from boards/arm/qomu/qomu.yaml rename to boards/quicklogic/qomu/qomu.yaml diff --git a/boards/arm/qomu/qomu_defconfig b/boards/quicklogic/qomu/qomu_defconfig similarity index 88% rename from boards/arm/qomu/qomu_defconfig rename to boards/quicklogic/qomu/qomu_defconfig index 4f169841289..c1d806d7b57 100644 --- a/boards/arm/qomu/qomu_defconfig +++ b/boards/quicklogic/qomu/qomu_defconfig @@ -2,14 +2,12 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=n -CONFIG_SOC_EOS_S3=y -CONFIG_BOARD_QOMU=y -# system clock +# System clock CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=61440000 CONFIG_CORTEX_M_SYSTICK=y -# console +# Console CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/quick_feather/Kconfig b/boards/quicklogic/quick_feather/Kconfig similarity index 100% rename from boards/arm/quick_feather/Kconfig rename to boards/quicklogic/quick_feather/Kconfig diff --git a/boards/quicklogic/quick_feather/Kconfig.quick_feather b/boards/quicklogic/quick_feather/Kconfig.quick_feather new file mode 100644 index 00000000000..244356b5c36 --- /dev/null +++ b/boards/quicklogic/quick_feather/Kconfig.quick_feather @@ -0,0 +1,7 @@ +# Quick Feather board + +# Copyright (c) 2020 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QUICK_FEATHER + select SOC_EOS_S3 diff --git a/boards/quicklogic/quick_feather/board.yml b/boards/quicklogic/quick_feather/board.yml new file mode 100644 index 00000000000..3ca618cbe34 --- /dev/null +++ b/boards/quicklogic/quick_feather/board.yml @@ -0,0 +1,5 @@ +board: + name: quick_feather + vendor: quicklogic + socs: + - name: quicklogic_eos_s3 diff --git a/boards/arm/quick_feather/doc/img/feather-board.jpg b/boards/quicklogic/quick_feather/doc/img/feather-board.jpg similarity index 100% rename from boards/arm/quick_feather/doc/img/feather-board.jpg rename to boards/quicklogic/quick_feather/doc/img/feather-board.jpg diff --git a/boards/quicklogic/quick_feather/doc/index.rst b/boards/quicklogic/quick_feather/doc/index.rst new file mode 100644 index 00000000000..d5bf1e7026d --- /dev/null +++ b/boards/quicklogic/quick_feather/doc/index.rst @@ -0,0 +1,125 @@ +.. _quickfeather: + +QuickFeather +############ + +Overview +******** + +The QuickFeather development board is a platform with an on-board QuickLogic +EOS S3 Sensor Processing Platform. + + +.. figure:: img/feather-board.jpg + :align: center + :alt: QuickFeather + + QuickFeather (Credit: QuickLogic) + +Hardware +******** + +- QuickLogic EOS S3 MCU Platform +- mCube MC3635 accelerometer +- Infineon DPS310 pressure sensor +- Infineon IM69D130 MEMS microphone +- 16 Mbit of on-board flash memory +- User button +- RGB LED +- Integrated battery charger + +Detailed information about the board can be found in a `QuickFeather repository`_. + +Supported Features +================== + +The QuickFeather configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/quicklogic/quick_feather/quick_feather_defconfig`. + +Connections and IOs +=================== + +Detailed information about pinouts is available in the `schematics document`_. + +Programming and Debugging +************************* + +Flashing +======== + +The QuickFeather platform by default boots from flash. Currently +the Zephyr port only enables loading the program directly to SRAM using either +OpenOCD and a SWD programmer or SEGGER JLink. + +OpenOCD +------- + +In order to connect to the target a SWD programmer supported in +OpenOCD is needed. To connect to the board run: + +.. code-block:: console + + openocd -f /path/to/swd-programmer.cfg -f tcl/board/quicklogic_quickfeather.cfg -c "init" -c "reset halt" + +`The QuickFeather OpenOCD config`_ can be found in the OpenOCD mainline repository. + +JLink +----- + +To connect to the QuickFeather board with JLink please follow instructions +in the `QuickFeather User Guide`_. + +Debugging +========= + +To debug the QuickFeather board please connect to the target with either +OpenOCD or JLink and use GDB distributed in Zephyr's SDK in *arm-zephyr-eabi/bin* +directory. + +To load basic sample via GDB: + +- Build the sample in an usual way: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: quick_feather + :goals: build + +- Connect to the target using either OpenOCD or JLink +- Connect via GDB and load an ELF file: + +.. code-block:: console + + /path/to/zephyr-sdk/arm-zephyr-eabi/bin/arm-zephyr-eabi-gdb + target remote + file + load + continue + +References +********** + +.. target-notes:: + +.. _QuickFeather repository: + https://github.com/QuickLogic-Corp/quick-feather-dev-board + +.. _schematics document: + https://github.com/QuickLogic-Corp/quick-feather-dev-board/blob/master/doc/quickfeather-board.pdf + +.. _The QuickFeather OpenOCD config: + https://sourceforge.net/p/openocd/code/ci/master/tree/tcl/board/quicklogic_quickfeather.cfg + +.. _QuickFeather User Guide: + https://github.com/QuickLogic-Corp/quick-feather-dev-board/blob/master/doc/QuickFeather_UserGuide.pdf diff --git a/boards/arm/quick_feather/quick_feather.dts b/boards/quicklogic/quick_feather/quick_feather.dts similarity index 100% rename from boards/arm/quick_feather/quick_feather.dts rename to boards/quicklogic/quick_feather/quick_feather.dts diff --git a/boards/arm/quick_feather/quick_feather.yaml b/boards/quicklogic/quick_feather/quick_feather.yaml similarity index 100% rename from boards/arm/quick_feather/quick_feather.yaml rename to boards/quicklogic/quick_feather/quick_feather.yaml diff --git a/boards/arm/quick_feather/quick_feather_defconfig b/boards/quicklogic/quick_feather/quick_feather_defconfig similarity index 86% rename from boards/arm/quick_feather/quick_feather_defconfig rename to boards/quicklogic/quick_feather/quick_feather_defconfig index 6f88908e44c..137acf1e62a 100644 --- a/boards/arm/quick_feather/quick_feather_defconfig +++ b/boards/quicklogic/quick_feather/quick_feather_defconfig @@ -2,13 +2,11 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=n -CONFIG_SOC_EOS_S3=y -CONFIG_BOARD_QUICK_FEATHER=y -# system clock +# System clock CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=61440000 -# console +# Console CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/rak/index.rst b/boards/rak/index.rst new file mode 100644 index 00000000000..334d985e609 --- /dev/null +++ b/boards/rak/index.rst @@ -0,0 +1,10 @@ +.. _boards-rak: + +RAKwireless +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/rak/rak4631/Kconfig.defconfig b/boards/rak/rak4631/Kconfig.defconfig new file mode 100644 index 00000000000..bf7cf003b29 --- /dev/null +++ b/boards/rak/rak4631/Kconfig.defconfig @@ -0,0 +1,11 @@ +# RAKWIRELESS RAK4631 Board configuration + +# Copyright (c) 2021 Guillaume Paquet +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAK4631 + +config BT_CTLR + default BT + +endif # BOARD_RAK4631 diff --git a/boards/rak/rak4631/Kconfig.rak4631 b/boards/rak/rak4631/Kconfig.rak4631 new file mode 100644 index 00000000000..4ba2754e42f --- /dev/null +++ b/boards/rak/rak4631/Kconfig.rak4631 @@ -0,0 +1,7 @@ +# RAKWIRELESS RAK4631 selection + +# Copyright (c) 2021 Guillaume Paquet +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAK4631 + select SOC_NRF52840_QIAA diff --git a/boards/arm/rak4631_nrf52840/board.cmake b/boards/rak/rak4631/board.cmake similarity index 100% rename from boards/arm/rak4631_nrf52840/board.cmake rename to boards/rak/rak4631/board.cmake diff --git a/boards/rak/rak4631/board.yml b/boards/rak/rak4631/board.yml new file mode 100644 index 00000000000..a3b88672823 --- /dev/null +++ b/boards/rak/rak4631/board.yml @@ -0,0 +1,5 @@ +board: + name: rak4631 + vendor: rakwireless + socs: + - name: nrf52840 diff --git a/boards/arm/rak4631_nrf52840/doc/img/rak4631-front-parts.jpg b/boards/rak/rak4631/doc/img/rak4631-front-parts.jpg similarity index 100% rename from boards/arm/rak4631_nrf52840/doc/img/rak4631-front-parts.jpg rename to boards/rak/rak4631/doc/img/rak4631-front-parts.jpg diff --git a/boards/rak/rak4631/doc/index.rst b/boards/rak/rak4631/doc/index.rst new file mode 100644 index 00000000000..ffa39ca8265 --- /dev/null +++ b/boards/rak/rak4631/doc/index.rst @@ -0,0 +1,154 @@ +.. _rak4631_nrf52840: + +RAK4631 +####### + +Overview +******** + +RAK4631 is a WisBlock Core module for RAK WisBlock. +It extends the WisBlock series with a powerful +Nordic nRF52840 MCU that supports Bluetooth 5.0 +(Bluetooth Low Energy) and the newest LoRa transceiver +from Semtech, the SX1262. The Semtech SX1262 has compared +to the older SX127x series a lower power consumption at +the same TX power. This makes the RAK4631 an ultra-low +power communication solution. RAK4631 can be comfortably +programmed with ZephyrRTOS. + +.. image:: img/rak4631-front-parts.jpg + :align: center + :alt: RAK4631-NRF52840 + +Hardware +******** + +To use a RAK4631, you need at least a WisBlock Base +to plug the module in. WisBlock Base is the power +supply for the RAK4631 module and has the +programming/debug interface. + +- nRF52840 ARM Cortex-M4F Processor +- 64 MHz CPU clock +- 1 Micro-AB USB OTG host/device +- Semtech SX1262 low power high range LoRa transceiver +- iPEX connectors for the LORA antenna and BLE antenna. +- Multiple interfaces, I2C, UART, GPIO, ADC +- 2 user LEDs on RAK5005 mother Board +- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port + +Supported Features +================== + +The ``rak4631/nrf52840`` board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RADIO | on-board | LoRa (SX1262) | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The default board configuration can be found in +:zephyr_file:`boards/rak/rak4631/rak4631_nrf52840_defconfig` + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P1.3 +* LED2 (blue) = P1.4 + +Programming and Debugging +************************* + +The RAK4631 board shall be connected to a Segger Embedded Debugger Unit +`J-Link OB `_. This provides a debug +interface to the NRF52840 chip. You can use JLink to communicate with +the NRF52840. + +Flashing +======== + +#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section + "J-Link Software and Documentation Pack" and install the "J-Link Software + and Documentation pack for Linux". The application JLinkExe needs to be + accessible from your path. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the RAK4631 board to your host computer using the USB debug port. + Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak4631/nrf52840 + :goals: build flash + + You should see "Hello World! rak4631_nrf52840" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak4631/nrf52840 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _RAK4631 Product Description: + https://docs.rakwireless.com/Product-Categories/WisBlock/RAK4631/Datasheet/#overview + +.. _JLink Downloads Page: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/pinnacle_100_dvk/pre_dt_board.cmake b/boards/rak/rak4631/pre_dt_board.cmake similarity index 100% rename from boards/arm/pinnacle_100_dvk/pre_dt_board.cmake rename to boards/rak/rak4631/pre_dt_board.cmake diff --git a/boards/arm/rak4631_nrf52840/rak4631_nrf52840-pinctrl.dtsi b/boards/rak/rak4631/rak4631_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/rak4631_nrf52840/rak4631_nrf52840-pinctrl.dtsi rename to boards/rak/rak4631/rak4631_nrf52840-pinctrl.dtsi diff --git a/boards/arm/rak4631_nrf52840/rak4631_nrf52840.dts b/boards/rak/rak4631/rak4631_nrf52840.dts similarity index 100% rename from boards/arm/rak4631_nrf52840/rak4631_nrf52840.dts rename to boards/rak/rak4631/rak4631_nrf52840.dts diff --git a/boards/arm/rak4631_nrf52840/rak4631_nrf52840.yaml b/boards/rak/rak4631/rak4631_nrf52840.yaml similarity index 89% rename from boards/arm/rak4631_nrf52840/rak4631_nrf52840.yaml rename to boards/rak/rak4631/rak4631_nrf52840.yaml index fb56f5275f6..42c638ac35c 100644 --- a/boards/arm/rak4631_nrf52840/rak4631_nrf52840.yaml +++ b/boards/rak/rak4631/rak4631_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: rak4631_nrf52840 +identifier: rak4631/nrf52840 name: RAK4631-NRF52840 type: mcu arch: arm diff --git a/boards/arm/rak4631_nrf52840/rak4631_nrf52840_defconfig b/boards/rak/rak4631/rak4631_nrf52840_defconfig similarity index 77% rename from boards/arm/rak4631_nrf52840/rak4631_nrf52840_defconfig rename to boards/rak/rak4631/rak4631_nrf52840_defconfig index bfdc1718875..8daa29dc473 100644 --- a/boards/arm/rak4631_nrf52840/rak4631_nrf52840_defconfig +++ b/boards/rak/rak4631/rak4631_nrf52840_defconfig @@ -1,7 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_RAK4631_NRF52840=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/rak/rak5010/Kconfig.defconfig b/boards/rak/rak5010/Kconfig.defconfig new file mode 100644 index 00000000000..302f7fecd07 --- /dev/null +++ b/boards/rak/rak5010/Kconfig.defconfig @@ -0,0 +1,11 @@ +# RAKWIRELESS RAK5010 Board configuration + +# Copyright (c) 2020 Guillaume Paquet +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAK5010 + +config BT_CTLR + default BT + +endif # BOARD_RAK5010 diff --git a/boards/rak/rak5010/Kconfig.rak5010 b/boards/rak/rak5010/Kconfig.rak5010 new file mode 100644 index 00000000000..ced2b62b39c --- /dev/null +++ b/boards/rak/rak5010/Kconfig.rak5010 @@ -0,0 +1,7 @@ +# RAKWIRELESS RAK5010 selection + +# Copyright (c) 2020 Guillaume Paquet +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAK5010_NRF52840 + select SOC_NRF52840_QIAA diff --git a/boards/arm/rak5010_nrf52840/board.cmake b/boards/rak/rak5010/board.cmake similarity index 100% rename from boards/arm/rak5010_nrf52840/board.cmake rename to boards/rak/rak5010/board.cmake diff --git a/boards/rak/rak5010/board.yml b/boards/rak/rak5010/board.yml new file mode 100644 index 00000000000..c681ac27cb7 --- /dev/null +++ b/boards/rak/rak5010/board.yml @@ -0,0 +1,5 @@ +board: + name: rak5010 + vendor: rakwireless + socs: + - name: nrf52840 diff --git a/boards/arm/rak5010_nrf52840/doc/img/rak5010-front-parts.jpg b/boards/rak/rak5010/doc/img/rak5010-front-parts.jpg similarity index 100% rename from boards/arm/rak5010_nrf52840/doc/img/rak5010-front-parts.jpg rename to boards/rak/rak5010/doc/img/rak5010-front-parts.jpg diff --git a/boards/rak/rak5010/doc/index.rst b/boards/rak/rak5010/doc/index.rst new file mode 100644 index 00000000000..fac00cf72df --- /dev/null +++ b/boards/rak/rak5010/doc/index.rst @@ -0,0 +1,159 @@ +.. _rak5010_nrf52840: + +RAK5010 +####### + +Overview +******** + +WisTrio NB-IoT Tracker Pro (RAK5010) is a tracker +with integrated LTE CAT M1 & NB1, GPS, BLE, and sensors. +It is built on the Quectel BG96 LTE CAT M1 & NB1 module, +which has an integrated GPS receiver. The MCU running +the board is a Nordic nRF52840 controller. + +As it has both GPS and BLE it can be used for outdoor +and indoor scenarios, where location-based services need be present. + +The built-in sensors for RAK5010 are temperature and +humidity sensor, motion sensor, pressure sensor, and light sensor. +The extension IOs allow adding more sensors in addition to the on-board ones. + +This board is particularly suitable to be used as a +quick testing and prototyping tool for applications +requiring NB-IoT connectivity. Application development +supports the GCC environment. + +.. image:: img/rak5010-front-parts.jpg + :align: center + :alt: RAK5010-NRF52840 + +Hardware +******** + +- nRF52840 ARM Cortex-M4F Processor +- 32.768 kHz crystal oscillator +- 1 Micro-AB USB OTG host/device +- Quectel BG96, with LTE CAT M1, LTE NB1, and GNSS +- iPEX connectors for the LTE and GPS antenna and an on-board ceramic antenna for the BLE. +- nano-SIM and ESIM options. +- Multiple interfaces, I2C, UART, GPIO, ADC +- 1 user LED +- 1 SHTC3 Humidity and Temperature Sensor +- 1 OPT3001DNPR Ambient Light Sensor +- 1 LPS22HB Pressure Sensor +- 1 LIS3DH Motion Sensor +- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port + +Supported Features +================== + +The ``rak5010/nrf52840`` board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +LED +--- + +* LED0 (green) = P0.12 + + +Programming and Debugging +************************* + +The RAK5010 board shall be connected to a Segger Embedded Debugger Unit +`J-Link OB `_. This provides a debug +interface to the NRF52840 chip. You can use JLink to communicate with +the NRF52840. + +Flashing +======== + +#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section + "J-Link Software and Documentation Pack" and install the "J-Link Software + and Documentation pack for Linux". The application JLinkExe needs to be + accessible from your path. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the RAK5010 board to your host computer using the USB debug port. + Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak5010/nrf52840 + :goals: build flash + + You should see "Hello World! rak5010_nrf52840" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak5010/nrf52840 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _RAK5010 Product Description: + https://doc.rakwireless.com/datasheet/rakproducts/rak5010-wistrio-nb-iot-tracker-datasheet + +.. _JLink Downloads Page: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/rak4631_nrf52840/pre_dt_board.cmake b/boards/rak/rak5010/pre_dt_board.cmake similarity index 100% rename from boards/arm/rak4631_nrf52840/pre_dt_board.cmake rename to boards/rak/rak5010/pre_dt_board.cmake diff --git a/boards/arm/rak5010_nrf52840/rak5010_nrf52840-pinctrl.dtsi b/boards/rak/rak5010/rak5010_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/rak5010_nrf52840/rak5010_nrf52840-pinctrl.dtsi rename to boards/rak/rak5010/rak5010_nrf52840-pinctrl.dtsi diff --git a/boards/arm/rak5010_nrf52840/rak5010_nrf52840.dts b/boards/rak/rak5010/rak5010_nrf52840.dts similarity index 100% rename from boards/arm/rak5010_nrf52840/rak5010_nrf52840.dts rename to boards/rak/rak5010/rak5010_nrf52840.dts diff --git a/boards/arm/rak5010_nrf52840/rak5010_nrf52840.yaml b/boards/rak/rak5010/rak5010_nrf52840.yaml similarity index 88% rename from boards/arm/rak5010_nrf52840/rak5010_nrf52840.yaml rename to boards/rak/rak5010/rak5010_nrf52840.yaml index 1238add9d37..21b8e122970 100644 --- a/boards/arm/rak5010_nrf52840/rak5010_nrf52840.yaml +++ b/boards/rak/rak5010/rak5010_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: rak5010_nrf52840 +identifier: rak5010/nrf52840 name: RAK5010-NRF52840 type: mcu arch: arm diff --git a/boards/arm/rak5010_nrf52840/rak5010_nrf52840_defconfig b/boards/rak/rak5010/rak5010_nrf52840_defconfig similarity index 77% rename from boards/arm/rak5010_nrf52840/rak5010_nrf52840_defconfig rename to boards/rak/rak5010/rak5010_nrf52840_defconfig index b7e873c3f03..8daa29dc473 100644 --- a/boards/arm/rak5010_nrf52840/rak5010_nrf52840_defconfig +++ b/boards/rak/rak5010/rak5010_nrf52840_defconfig @@ -1,7 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_RAK5010_NRF52840=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/raspberrypi/index.rst b/boards/raspberrypi/index.rst new file mode 100644 index 00000000000..5128a34a3b5 --- /dev/null +++ b/boards/raspberrypi/index.rst @@ -0,0 +1,10 @@ +.. _boards-raspberrypi: + +Raspberry Pi Foundation +####################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm64/mimx93_evk/board.cmake b/boards/raspberrypi/rpi_4b/CMakeLists.txt similarity index 100% rename from boards/arm64/mimx93_evk/board.cmake rename to boards/raspberrypi/rpi_4b/CMakeLists.txt diff --git a/boards/raspberrypi/rpi_4b/Kconfig.defconfig b/boards/raspberrypi/rpi_4b/Kconfig.defconfig new file mode 100644 index 00000000000..70e62317248 --- /dev/null +++ b/boards/raspberrypi/rpi_4b/Kconfig.defconfig @@ -0,0 +1,2 @@ +# Copyright 2023 honglin leng +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/raspberrypi/rpi_4b/Kconfig.rpi_4b b/boards/raspberrypi/rpi_4b/Kconfig.rpi_4b new file mode 100644 index 00000000000..ca717ac191e --- /dev/null +++ b/boards/raspberrypi/rpi_4b/Kconfig.rpi_4b @@ -0,0 +1,5 @@ +# Copyright 2023 honglin leng +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RPI_4B + select SOC_BCM2711 diff --git a/boards/arm64/nxp_ls1046ardb/board.cmake b/boards/raspberrypi/rpi_4b/board.cmake similarity index 100% rename from boards/arm64/nxp_ls1046ardb/board.cmake rename to boards/raspberrypi/rpi_4b/board.cmake diff --git a/boards/raspberrypi/rpi_4b/board.yml b/boards/raspberrypi/rpi_4b/board.yml new file mode 100644 index 00000000000..a84904f9b29 --- /dev/null +++ b/boards/raspberrypi/rpi_4b/board.yml @@ -0,0 +1,5 @@ +board: + name: rpi_4b + vendor: raspberrypi + socs: + - name: bcm2711 diff --git a/boards/raspberrypi/rpi_4b/doc/index.rst b/boards/raspberrypi/rpi_4b/doc/index.rst new file mode 100644 index 00000000000..e31845fdea9 --- /dev/null +++ b/boards/raspberrypi/rpi_4b/doc/index.rst @@ -0,0 +1,70 @@ +.. rpi_4b: + +Raspberry Pi 4 Model B (Cortex-A72) +################################### + +Overview +******** +see + +Hardware +******** +see + +Supported Features +================== +The Raspberry Pi 4 Model B board configuration supports the following +hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - GIC-400 + - N/A + - :dtcompatible:`arm,gic-v2` + * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`brcm,bcm2711-gpio` + * - UART (Mini UART) + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`brcm,bcm2711-aux-uart` + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/raspberry_pi/rpi_4b/rpi_4b_defconfig` + +Programming and Debugging +************************* + +TF Card +======= + +Prepare a TF card with MBR and FAT32. In the root directory of the TF card: + +1. Download and place these firmware files: + + * `bcm2711-rpi-4-b.dtb `_ + * `bootcode.bin `_ + * `start4.elf `_ + +2. Copy ``build/zephyr/zephyr.bin`` +3. Create a ``config.txt``: + + .. code-block:: text + + kernel=zephyr.bin + arm_64bit=1 + enable_uart=1 + uart_2ndstage=1 + +Insert the card and power on the board. You should see the following output on +the serial console (GPIO 14/15): + +.. code-block:: text + + *** Booting Zephyr OS build XXXXXXXXXXXX *** + Hello World! Raspberry Pi 4 Model B! diff --git a/boards/arm64/rpi_4b/rpi_4b.dts b/boards/raspberrypi/rpi_4b/rpi_4b.dts similarity index 100% rename from boards/arm64/rpi_4b/rpi_4b.dts rename to boards/raspberrypi/rpi_4b/rpi_4b.dts diff --git a/boards/arm64/rpi_4b/rpi_4b.yaml b/boards/raspberrypi/rpi_4b/rpi_4b.yaml similarity index 100% rename from boards/arm64/rpi_4b/rpi_4b.yaml rename to boards/raspberrypi/rpi_4b/rpi_4b.yaml diff --git a/boards/arm64/rpi_4b/rpi_4b_defconfig b/boards/raspberrypi/rpi_4b/rpi_4b_defconfig similarity index 90% rename from boards/arm64/rpi_4b/rpi_4b_defconfig rename to boards/raspberrypi/rpi_4b/rpi_4b_defconfig index fb79c77a1f6..124ef834088 100644 --- a/boards/arm64/rpi_4b/rpi_4b_defconfig +++ b/boards/raspberrypi/rpi_4b/rpi_4b_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 # Platform Configuration -CONFIG_SOC_BCM2711=y -CONFIG_BOARD_RPI_4B=y CONFIG_ARM64_VA_BITS_36=y CONFIG_ARM64_PA_BITS_36=y diff --git a/boards/raspberrypi/rpi_pico/Kconfig.defconfig b/boards/raspberrypi/rpi_pico/Kconfig.defconfig new file mode 100644 index 00000000000..1b4c3175a51 --- /dev/null +++ b/boards/raspberrypi/rpi_pico/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RPI_PICO + +config RP2_FLASH_W25Q080 + default y + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_RPI_PICO diff --git a/boards/raspberrypi/rpi_pico/Kconfig.rpi_pico b/boards/raspberrypi/rpi_pico/Kconfig.rpi_pico new file mode 100644 index 00000000000..cde6b9c8d27 --- /dev/null +++ b/boards/raspberrypi/rpi_pico/Kconfig.rpi_pico @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RPI_PICO + select SOC_RP2040 diff --git a/boards/arm/rpi_pico/board.cmake b/boards/raspberrypi/rpi_pico/board.cmake similarity index 100% rename from boards/arm/rpi_pico/board.cmake rename to boards/raspberrypi/rpi_pico/board.cmake diff --git a/boards/raspberrypi/rpi_pico/board.yml b/boards/raspberrypi/rpi_pico/board.yml new file mode 100644 index 00000000000..e4f8e5bc8d5 --- /dev/null +++ b/boards/raspberrypi/rpi_pico/board.yml @@ -0,0 +1,7 @@ +board: + name: rpi_pico + vendor: raspberrypi + socs: + - name: rp2040 + variants: + - name: w diff --git a/boards/arm/rpi_pico/doc/img/rpi_pico.jpg b/boards/raspberrypi/rpi_pico/doc/img/rpi_pico.jpg similarity index 100% rename from boards/arm/rpi_pico/doc/img/rpi_pico.jpg rename to boards/raspberrypi/rpi_pico/doc/img/rpi_pico.jpg diff --git a/boards/arm/rpi_pico/doc/img/rpi_pico_w.jpg b/boards/raspberrypi/rpi_pico/doc/img/rpi_pico_w.jpg similarity index 100% rename from boards/arm/rpi_pico/doc/img/rpi_pico_w.jpg rename to boards/raspberrypi/rpi_pico/doc/img/rpi_pico_w.jpg diff --git a/boards/arm/rpi_pico/doc/index.rst b/boards/raspberrypi/rpi_pico/doc/index.rst similarity index 100% rename from boards/arm/rpi_pico/doc/index.rst rename to boards/raspberrypi/rpi_pico/doc/index.rst diff --git a/boards/arm/rpi_pico/rpi_pico-common.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi similarity index 100% rename from boards/arm/rpi_pico/rpi_pico-common.dtsi rename to boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi diff --git a/boards/arm/rpi_pico/rpi_pico-pinctrl.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi similarity index 100% rename from boards/arm/rpi_pico/rpi_pico-pinctrl.dtsi rename to boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi diff --git a/boards/arm/rpi_pico/rpi_pico.dts b/boards/raspberrypi/rpi_pico/rpi_pico.dts similarity index 75% rename from boards/arm/rpi_pico/rpi_pico.dts rename to boards/raspberrypi/rpi_pico/rpi_pico.dts index 97d721024d7..f92c55c6825 100644 --- a/boards/arm/rpi_pico/rpi_pico.dts +++ b/boards/raspberrypi/rpi_pico/rpi_pico.dts @@ -8,6 +8,10 @@ #include "rpi_pico-common.dtsi" +/* Only the rpi_pico/rp2040 has a pwm. */ +/* This define can be used to avoid sourcing board overlays when the PWM is not available */ +#define HAS_DT_PWM_LED 1 + / { leds { compatible = "gpio-leds"; diff --git a/boards/arm/rpi_pico/rpi_pico.yaml b/boards/raspberrypi/rpi_pico/rpi_pico.yaml similarity index 100% rename from boards/arm/rpi_pico/rpi_pico.yaml rename to boards/raspberrypi/rpi_pico/rpi_pico.yaml diff --git a/boards/arm/rpi_pico/rpi_pico_defconfig b/boards/raspberrypi/rpi_pico/rpi_pico_defconfig similarity index 78% rename from boards/arm/rpi_pico/rpi_pico_defconfig rename to boards/raspberrypi/rpi_pico/rpi_pico_defconfig index 111edceb147..df003531af9 100644 --- a/boards/arm/rpi_pico/rpi_pico_defconfig +++ b/boards/raspberrypi/rpi_pico/rpi_pico_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_RPI_PICO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 CONFIG_SERIAL=y CONFIG_CONSOLE=y diff --git a/boards/arm/rpi_pico/rpi_pico_w.dts b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts similarity index 100% rename from boards/arm/rpi_pico/rpi_pico_w.dts rename to boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml new file mode 100644 index 00000000000..581645830a7 --- /dev/null +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml @@ -0,0 +1,24 @@ +identifier: rpi_pico/rp2040/w +name: RaspberryPi-Pico-w +type: mcu +arch: arm +flash: 2048 +ram: 264 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart + - gpio + - adc + - i2c + - spi + - hwinfo + - watchdog + - pwm + - flash + - dma + - pio + - counter + - clock diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig new file mode 100644 index 00000000000..df003531af9 --- /dev/null +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig @@ -0,0 +1,11 @@ +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_USE_DT_CODE_PARTITION=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_RESET=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/rpi_pico/support/openocd.cfg b/boards/raspberrypi/rpi_pico/support/openocd.cfg similarity index 100% rename from boards/arm/rpi_pico/support/openocd.cfg rename to boards/raspberrypi/rpi_pico/support/openocd.cfg diff --git a/boards/raytac/index.rst b/boards/raytac/index.rst new file mode 100644 index 00000000000..a3471445b5f --- /dev/null +++ b/boards/raytac/index.rst @@ -0,0 +1,10 @@ +.. _boards-raytac: + +Raytac Corporation +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/raytac/mdbt50q_db_33/Kconfig b/boards/raytac/mdbt50q_db_33/Kconfig new file mode 100644 index 00000000000..33290b29c1f --- /dev/null +++ b/boards/raytac/mdbt50q_db_33/Kconfig @@ -0,0 +1,10 @@ +# Raytac MDBT50Q-DB-33 nRF52833 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_RAYTAC_MDBT50Q_DB_33 diff --git a/boards/raytac/mdbt50q_db_33/Kconfig.defconfig b/boards/raytac/mdbt50q_db_33/Kconfig.defconfig new file mode 100644 index 00000000000..bb5e7c4a14d --- /dev/null +++ b/boards/raytac/mdbt50q_db_33/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Raytac MDBT50Q-DB-33 NRF52833 board configuration + +# Copyright (c) 2022 Raytac Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT50Q_DB_33 + +config BT_CTLR + default BT + +endif # BOARD_RAYTAC_MDBT50Q_DB_33 diff --git a/boards/raytac/mdbt50q_db_33/Kconfig.raytac_mdbt50q_db_33 b/boards/raytac/mdbt50q_db_33/Kconfig.raytac_mdbt50q_db_33 new file mode 100644 index 00000000000..edd49089253 --- /dev/null +++ b/boards/raytac/mdbt50q_db_33/Kconfig.raytac_mdbt50q_db_33 @@ -0,0 +1,7 @@ +# Raytac MDBT50Q-DB-33 nRF52833 board configuration + +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAYTAC_MDBT50Q_DB_33 + select SOC_NRF52833_QIAA diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/board.cmake b/boards/raytac/mdbt50q_db_33/board.cmake similarity index 100% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/board.cmake rename to boards/raytac/mdbt50q_db_33/board.cmake diff --git a/boards/raytac/mdbt50q_db_33/board.yml b/boards/raytac/mdbt50q_db_33/board.yml new file mode 100644 index 00000000000..dbad99fd489 --- /dev/null +++ b/boards/raytac/mdbt50q_db_33/board.yml @@ -0,0 +1,5 @@ +board: + name: raytac_mdbt50q_db_33 + vendor: raytac + socs: + - name: nrf52833 diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/doc/img/mdbt50q_db_33.jpg b/boards/raytac/mdbt50q_db_33/doc/img/mdbt50q_db_33.jpg similarity index 100% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/doc/img/mdbt50q_db_33.jpg rename to boards/raytac/mdbt50q_db_33/doc/img/mdbt50q_db_33.jpg diff --git a/boards/raytac/mdbt50q_db_33/doc/index.rst b/boards/raytac/mdbt50q_db_33/doc/index.rst new file mode 100644 index 00000000000..b078dd2984e --- /dev/null +++ b/boards/raytac/mdbt50q_db_33/doc/index.rst @@ -0,0 +1,213 @@ +.. _raytac_mdbt50q_db_33_nrf52833: + +Raytac MDBT50Q-DB-33 +#################### + +Overview +******** + +The Raytac MDBT50Q-DB-33 hardware provides support for the +Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/mdbt50q_db_33.jpg + :width: 442px + :align: center + :alt: MDBT50Q-DB-33 + +More information about the board can be found at the `MDBT50Q-DB-33 website`_. +The `MDBT50Q-DB-33 Specification`_ contains the demo board's datasheet. +The `MDBT50Q-DB-33 Schematic`_ contains the demo board's schematic. + +Hardware +******** +- Module Demo Board build by MDBT50Q-512K +- Nordic nRF52833 SoC Solution +- A recommnded 3rd-party module by Nordic Semiconductor. +- BT5.2&BT5.1&BT5 Bluetooth Specification Cerified +- Supports BT5 Long Range Features +- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC +- 32-bit ARM® Cortex™ M4F CPU +- 512kB Flash Memory/128kB RAM +- RoHs & Reach Compiant. +- 42 GPIO +- Chip Antenna +- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB +- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. +- 3 User LEDs +- 4 User buttons +- 1 Mini USB connector for power supply and USB communication +- SWD connector for FW programing +- J-Link interface for FW programing +- UART interface for UART communication + +Supported Features +================== + +The raytac_mdbt50q_db_33/nrf52833 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `MDBT50Q-DB-33 website`_ and `MDBT50Q-DB-33 Specification`_ +for a complete list of Raytac MDBT50Q-DB-33 board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (red) = P0.14 +* LED3 (blue) = P0.15 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 + +UART +---- +* RXD = P0.08 +* TXD = P0.06 +* RTS = P0.05 +* CTS = P0.07 + +Programming and Debugging +************************* + +Applications for the ``raytac_mdbt50q_db_33/nrf52833`` board configuration can be +built, flashed, and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +.. note:: + Flashing and Debugging Zephyr onto the raytac_mdbt50q_db_33/nrf52833 board + requires an external J-Link programmer. The programmer is attached to the J1 + or J9 SWD connector. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_33/nrf52833 +J10 connector. Then run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the USB to TTL converter +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: raytac_mdbt50q_db_33/nrf52833 + :goals: build flash + +Debugging +========= + +The ``raytac_mdbt50q_db_33/nrf52833`` board does not have an on-board-J-Link debug IC, +however, instructions from the :ref:`nordic_segger` page also apply to this board. +Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER +J-Link OB IF to debug. + +Testing the LEDs and buttons in the Raytac MDBT50Q-DB-33 +******************************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts`. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the `MDBT50Q-DB-33 Specification`_, chapter 2.5 'Pin Assignment'. +Select the pins marked 'General-purpose I/O'. Note that pins marked as 'low-frequency I/O +only' can only be used in under-10KHz applications. They are not suitable for SPI, I2C, +UART, and PWM. + +References +********** + +.. target-notes:: + +.. _MDBT50Q-DB-33 website: + https://www.raytac.com/product/ins.php?index_id=97 +.. _MDBT50Q-DB-33 Specification: + https://www.raytac.com/download/index.php?index_id=46 +.. _MDBT50Q-DB-33 Schematic: + https://www.raytac.com/upload/catalog_b/407c1150fa33511a47e8a2f85d106ff3.jpg +.. _J-Link Software and documentation pack: + https://www.segger.com/jlink-software.html diff --git a/boards/arm/rak5010_nrf52840/pre_dt_board.cmake b/boards/raytac/mdbt50q_db_33/pre_dt_board.cmake similarity index 100% rename from boards/arm/rak5010_nrf52840/pre_dt_board.cmake rename to boards/raytac/mdbt50q_db_33/pre_dt_board.cmake diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi rename to boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.dts b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts similarity index 100% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.dts rename to boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.yaml b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml similarity index 89% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.yaml rename to boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml index 9284c90aa8e..673705fa123 100644 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.yaml +++ b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2022 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -identifier: raytac_mdbt50q_db_33_nrf52833 +identifier: raytac_mdbt50q_db_33/nrf52833 name: Raytac MDBT50Q-DB-33 nRF52833 type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833_defconfig b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833_defconfig similarity index 79% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833_defconfig rename to boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833_defconfig index 1176302a56d..d0b9df8255d 100644 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833_defconfig +++ b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_RAYTAC_MDBT50Q_DB_33_NRF52833=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/raytac/mdbt50q_db_40/Kconfig b/boards/raytac/mdbt50q_db_40/Kconfig new file mode 100644 index 00000000000..bb2c5c4ad77 --- /dev/null +++ b/boards/raytac/mdbt50q_db_40/Kconfig @@ -0,0 +1,18 @@ +# Raytac MDBT50Q-DB-40 nRF52840 board configuration + +# Copyright (c) 2022 Raytac Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT50Q_DB_40 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF52X_HV + default y + +endif # BOARD_RAYTAC_MDBT50Q_DB_40 diff --git a/boards/raytac/mdbt50q_db_40/Kconfig.defconfig b/boards/raytac/mdbt50q_db_40/Kconfig.defconfig new file mode 100644 index 00000000000..2919530e87c --- /dev/null +++ b/boards/raytac/mdbt50q_db_40/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Raytac MDBT50Q-DB-40 NRF52840 board configuration + +# Copyright (c) 2022 Raytac Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT50Q_DB_40 + +config BT_CTLR + default BT + +endif # BOARD_RAYTAC_MDBT50Q_DB_40 diff --git a/boards/raytac/mdbt50q_db_40/Kconfig.raytac_mdbt50q_db_40 b/boards/raytac/mdbt50q_db_40/Kconfig.raytac_mdbt50q_db_40 new file mode 100644 index 00000000000..30fb87de803 --- /dev/null +++ b/boards/raytac/mdbt50q_db_40/Kconfig.raytac_mdbt50q_db_40 @@ -0,0 +1,7 @@ +# Raytac MDBT50Q-DB-40 nRF52840 board configuration + +# Copyright (c) 2022 Raytac Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAYTAC_MDBT50Q_DB_40 + select SOC_NRF52840_QIAA diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/board.cmake b/boards/raytac/mdbt50q_db_40/board.cmake similarity index 100% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/board.cmake rename to boards/raytac/mdbt50q_db_40/board.cmake diff --git a/boards/raytac/mdbt50q_db_40/board.yml b/boards/raytac/mdbt50q_db_40/board.yml new file mode 100644 index 00000000000..a8c109b715f --- /dev/null +++ b/boards/raytac/mdbt50q_db_40/board.yml @@ -0,0 +1,5 @@ +board: + name: raytac_mdbt50q_db_40 + vendor: raytac + socs: + - name: nrf52840 diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/doc/img/mdbt50q_db_40.jpg b/boards/raytac/mdbt50q_db_40/doc/img/mdbt50q_db_40.jpg similarity index 100% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/doc/img/mdbt50q_db_40.jpg rename to boards/raytac/mdbt50q_db_40/doc/img/mdbt50q_db_40.jpg diff --git a/boards/raytac/mdbt50q_db_40/doc/index.rst b/boards/raytac/mdbt50q_db_40/doc/index.rst new file mode 100644 index 00000000000..f9d79818f6a --- /dev/null +++ b/boards/raytac/mdbt50q_db_40/doc/index.rst @@ -0,0 +1,215 @@ +.. _raytac_mdbt50q_db_40_nrf52840: + +Raytac MDBT50Q-DB-40 +#################### + +Overview +******** + +The Raytac MDBT50Q-DB-40 hardware provides support for the +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/mdbt50q_db_40.jpg + :width: 442px + :align: center + :alt: MDBT50Q-DB-40 + +More information about the board can be found at the `MDBT50Q-DB-40 website`_. +The `MDBT50Q-DB-40 Specification`_ contains the demo board's datasheet. +The `MDBT50Q-DB-40 Schematic`_ contains the demo board's schematic. + +Hardware +******** +- Module Demo Board build by MDBT50Q-1MV2 +- Nordic nRF52840 SoC Solution Version: 2 +- A recommnded 3rd-party module by Nordic Semiconductor. +- BT5.2&BT5.1&BT5 Bluetooth Specification Cerified +- Supports BT5 Long Range Features +- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC +- 32-bit ARM® Cortex™ M4F CPU +- 1MB Flash Memory/256kB RAM +- RoHs & Reach Compiant. +- 48 GPIO +- Chip Antenna +- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB +- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. +- 3 User LEDs +- 4 User buttons +- 1 Mini USB connector for power supply and USB communication +- SWD connector for FW programing +- J-Link interface for FW programing +- UART interface for UART communication + +Supported Features +================== + +The raytac_mdbt50q_db_40/nrf52840 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| QSPI(M) | on-chip | qspi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `MDBT50Q-DB-40 website`_ and `MDBT50Q-DB-40 Specification`_ +for a complete list of Raytac MDBT50Q-DB-40 board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (red) = P0.14 +* LED3 (blue) = P0.15 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 + +UART +---- +* RXD = P0.08 +* TXD = P0.06 +* RTS = P0.05 +* CTS = P0.07 + +Programming and Debugging +************************* + +Applications for the ``raytac_mdbt50q_db_40/nrf52840`` board configuration can be +built, flashed, and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +.. note:: + Flashing and Debugging Zephyr onto the raytac_mdbt50q_db_40/nrf52840 board + requires an external J-Link programmer. The programmer is attached to the J1 + or J9 SWD connector. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_40/nrf52840 +J10 connector. Then run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the USB to TTL converter +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: raytac_mdbt50q_db_40/nrf52840 + :goals: build flash + +Debugging +========= + +The ``raytac_mdbt50q_db_40/nrf52840`` board does not have an on-board-J-Link debug IC, +however, instructions from the :ref:`nordic_segger` page also apply to this board. +Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER +J-Link OB IF to debug. + +Testing the LEDs and buttons in the MDBT50Q-DB-40 +************************************************* + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts`. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the `MDBT50Q-DB-40 Specification`_, chapter 2.5 'Pin Assignment'. +Select the pins marked 'General-purpose I/O'. Note that pins marked as 'low-frequency I/O +only' can only be used in under-10KHz applications. They are not suitable for SPI, I2C, +UART, and PWM. + +References +********** + +.. target-notes:: + +.. _MDBT50Q-DB-40 website: + https://www.raytac.com/product/ins.php?index_id=81 +.. _MDBT50Q-DB-40 Specification: + https://www.raytac.com/download/index.php?index_id=43 +.. _MDBT50Q-DB-40 Schematic: + https://www.raytac.com/upload/catalog_b/134ade06b5db3dd5803d27c5b17f22f3.jpg +.. _J-Link Software and documentation pack: + https://www.segger.com/jlink-software.html diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/pre_dt_board.cmake b/boards/raytac/mdbt50q_db_40/pre_dt_board.cmake similarity index 100% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/pre_dt_board.cmake rename to boards/raytac/mdbt50q_db_40/pre_dt_board.cmake diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840-pinctrl.dtsi b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840-pinctrl.dtsi rename to boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.dts b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts similarity index 100% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.dts rename to boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.yaml b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml similarity index 90% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.yaml rename to boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml index 7c6626fbe34..15ba012594e 100644 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.yaml +++ b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml @@ -3,7 +3,7 @@ # Copyright (c) 2022 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -identifier: raytac_mdbt50q_db_40_nrf52840 +identifier: raytac_mdbt50q_db_40/nrf52840 name: Raytac MDBT50Q_DB_40_NRF52840 type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840_defconfig b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840_defconfig similarity index 79% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840_defconfig rename to boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840_defconfig index 3651902f740..7515c65a6a7 100644 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840_defconfig +++ b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_RAYTAC_MDBT50Q_DB_40_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/raytac/mdbt53_db_40/CMakeLists.txt b/boards/raytac/mdbt53_db_40/CMakeLists.txt new file mode 100644 index 00000000000..44bcab2993e --- /dev/null +++ b/boards/raytac/mdbt53_db_40/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +if((CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS) + AND CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(raytac_mdbt53_db_40_nrf5340_cpunet_reset.c) +endif() diff --git a/boards/raytac/mdbt53_db_40/Kconfig b/boards/raytac/mdbt53_db_40/Kconfig new file mode 100644 index 00000000000..a436b55cfb4 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/Kconfig @@ -0,0 +1,61 @@ +# Ratac MDBT53-DB-40 nRF5340 board configuration + +# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "raytac_mdbt53_db_40/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "raytac_mdbt53_db_40/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53_db_40/Kconfig.defconfig b/boards/raytac/mdbt53_db_40/Kconfig.defconfig new file mode 100644 index 00000000000..7bb0e9da948 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/Kconfig.defconfig @@ -0,0 +1,77 @@ +# Raytac MDBT53-DB-40 nRF5340 board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +config IPM_NRFX + default IPM + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET + +config BT_CTLR + default y if BT + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53_db_40/Kconfig.raytac_mdbt53_db_40 b/boards/raytac/mdbt53_db_40/Kconfig.raytac_mdbt53_db_40 new file mode 100644 index 00000000000..52d6bfd6dbb --- /dev/null +++ b/boards/raytac/mdbt53_db_40/Kconfig.raytac_mdbt53_db_40 @@ -0,0 +1,9 @@ +# Raytac MDBT53-DB-40 NRF5340 board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAYTAC_MDBT53_DB_40 + select SOC_NRF5340_CPUAPP_QKAA if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53_db_40/board.cmake b/boards/raytac/mdbt53_db_40/board.cmake new file mode 100644 index 00000000000..e181f29ca44 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/board.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/raytac/mdbt53_db_40/board.yml b/boards/raytac/mdbt53_db_40/board.yml new file mode 100644 index 00000000000..84bef186b33 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/board.yml @@ -0,0 +1,8 @@ +board: + name: raytac_mdbt53_db_40 + vendor: raytac + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/doc/img/MDBT53-DB-40.jpg b/boards/raytac/mdbt53_db_40/doc/img/MDBT53-DB-40.jpg similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/doc/img/MDBT53-DB-40.jpg rename to boards/raytac/mdbt53_db_40/doc/img/MDBT53-DB-40.jpg diff --git a/boards/raytac/mdbt53_db_40/doc/index.rst b/boards/raytac/mdbt53_db_40/doc/index.rst new file mode 100644 index 00000000000..a57fc5225dc --- /dev/null +++ b/boards/raytac/mdbt53_db_40/doc/index.rst @@ -0,0 +1,271 @@ +.. _raytac_mdbt53_db_40_nrf5340: + +Raytac MDBT53-DB-40 +################### + +Overview +******** + +Raytac MDBT53-DB-40 demo board is a development board based on the Raytac MDBT53-1M module, +using Nordic Semiconductor nRF5340 ARM Cortex-M33 SoC. Its design concept is to connect all +of the module's pins to 2.54mm pin headers. It is convenient for developers to verify whether +the modules are connected to other peripheral devices or sensors as a tool for software development. + +The nRF5340 inside the MDBT53-1M module is a +dual-core SoC based on the Arm® Cortex®-M33 architecture, with: + +* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and + Armv8-M Security Extension, running at up to 128 MHz, referred to as + the **application core** +* a secondary Arm Cortex-M33 core, with a reduced feature set, running + at a fixed 64 MHz, referred to as the **network core**. + +The ``raytac_mdbt53_db_40/nrf5340/cpuapp`` build target provides support for the application +core on the nRF5340 SoC. The ``raytac_mdbt53_db_40/nrf5340/cpuapp`` build target provides +support for the network core on the nRF5340 SoC. + +nRF5340 SoC provides support for the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/MDBT53-DB-40.jpg + :width: 442px + :align: center + :alt: MDBT53-DB-40 + + MDBT53-DB-40 (Credit: Raytac Corporation) + +More information about the board can be found at the `MDBT53-DB-40 website`_. +The `MDBT53-DB-40 Specification`_ contains the demo board's datasheet. +The `MDBT53-DB-40 Schematic`_ contains the demo board's schematic. + +Hardware +******** +- Module Demo Board build by MDBT53-1M +- Nordic nRF5340 SoC Solution +- A recommnded 3rd-party module by Nordic Semiconductor. +- Dual-core Arm® Cortex® M33 +- 1MB/256KB Flash Memory; 512kB/ 64kB RAM +- Supports BT5 Long Range Features +- Bluetooth specification v5.2 +- Supports Bluetooth Direction Finding & Mesh +- Supports Bluetooth low energy audio +- Certifications: FCC, IC, CE, Telec (MIC), KC, SRRC, NCC, RCM, WPC +- RoHs & Reach Compiant. +- 48 GPIO +- Chip Antenna +- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB +- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. +- 4 User LEDs +- 4 User buttons +- 1 Mini USB connector for power supply +- SWD connector for FW programing +- J-Link interface for FW programing +- UART interface for UART communication + +Supported Features +================== + +The ``raytac_mdbt53_db_40_nrf5340/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| QSPI(M) | on-chip | nor | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``raytac_mdbt53_db_40_nrf5340/cpunet`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `MDBT53-DB-40 website`_ and `MDBT53-DB-40 Specification`_ +for a complete list of Raytac MDBT53-DB-40 board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.28 +* LED2 (red) = P0.30 +* LED3 = P0.31 +* LED4 = P0.29 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.24 +* BUTTON2 = SW2 = P0.08 +* BUTTON3 = SW3 = P0.23 +* BUTTON4 = SW4 = P0.09 + +UART +---- +* RX = P0.22 +* TX = P0.20 +* RTS = P0.19 +* CTS = P0.21 + + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_) on the application core. + The IDAU is implemented with the System Protection Unit and is used to + define secure and non-secure memory maps. By default, all of the memory + space (Flash, SRAM, and peripheral address space) is defined to be secure + accessible only. +- Secure boot. + +Programming and Debugging +************************* + +nRF5340 application core supports the Armv8-M Security Extension. +Applications built for the ``raytac_mdbt53_db_40/nrf5340/cpuapp`` board by +default boot in the Secure state. + +nRF5340 network core does not support the Armv8-M Security Extension. +nRF5340 IDAU may configure bus accesses by the nRF5340 network core +to have Secure attribute set; the latter allows to build and run +Secure only applications on the nRF5340 SoC. + +Applications for the ``raytac_mdbt53_db_40_nrf5340`` board configuration can be +built, flashed, and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +.. note:: + Flashing and Debugging Zephyr onto the raytac_mdbt53_db_40_nrf5340 board + requires an external J-Link programmer. The programmer is attached to the J1 + or J9 SWD connector. + + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The nRF5340 has a flash read-back protection feature. When flash read-back + protection is active, you will need to recover the chip before reflashing. + If you are flashing with :ref:`west `, run + this command for more details on the related ``--recover`` option: + +Here is an example for the :ref:`hello_world` application. + +Use a USB to TTL converter to connect the computer and raytac_mdbt53_db_40_nrf5340 +J10 connector. Then run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the USB to TTL converter +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: raytac_mdbt53_db_40_nrf5340 + :goals: build flash + +Debugging +========= + +The ``raytac_mdbt53_db_40_nrf5340`` board does not have an on-board-J-Link debug IC, +however, instructions from the :ref:`nordic_segger` page also apply to this board. +Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER +J-Link OB IF to debug. + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +boards with a Segger IC. + + +References +********** + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _MDBT53-DB-40 website: + https://www.raytac.com/product/ins.php?index_id=139 +.. _MDBT53-DB-40 Specification: + https://www.raytac.com/download/index.php?index_id=60 +.. _MDBT53-DB-40 Schematic: + https://www.raytac.com/upload/catalog_b/8b5e364600a9cc8c53a869733e97f07e.jpg +.. _J-Link Software and documentation pack: + https://www.segger.com/jlink-software.html diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/pre_dt_board.cmake b/boards/raytac/mdbt53_db_40/pre_dt_board.cmake similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/pre_dt_board.cmake rename to boards/raytac/mdbt53_db_40/pre_dt_board.cmake diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml similarity index 85% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml index 4f70a9e375d..f962784606b 100644 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml @@ -1,4 +1,4 @@ -identifier: raytac_mdbt53_db_40_nrf5340_cpuapp +identifier: raytac_mdbt53_db_40/nrf5340/cpuapp name: RAYTAC-MDBT53-DB-40-NRF5340-application-MCU type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml similarity index 84% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml index 5c402d46273..46fbe1ea192 100644 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml @@ -1,4 +1,4 @@ -identifier: raytac_mdbt53_db_40_nrf5340_cpuapp_ns +identifier: raytac_mdbt53_db_40/nrf5340/cpuapp/ns name: RAYTAC-MDBT53-DB-40-NRF52840-application-MCU-Non-Secure type: mcu arch: arm diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig new file mode 100644 index 00000000000..2a74dd56f41 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet-pinctrl.dtsi b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet-pinctrl.dtsi rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.dts diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet.yaml b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.yaml similarity index 87% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet.yaml rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.yaml index bf82a0627c1..b6badb279f9 100644 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet.yaml +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.yaml @@ -2,7 +2,7 @@ # Copyright (c) 2023 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -identifier: raytac_mdbt53_db_40_nrf5340_cpunet +identifier: raytac_mdbt53_db_40/nrf5340/cpunet name: RAYTAC MDBT53-DB-40-NRF5340-network-MCU type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..56940c43a09 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c diff --git a/boards/arm64/roc_rk3568_pc/board.cmake b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_defconfig similarity index 100% rename from boards/arm64/roc_rk3568_pc/board.cmake rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_defconfig diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts diff --git a/boards/raytac/mdbt53v_db_40/CMakeLists.txt b/boards/raytac/mdbt53v_db_40/CMakeLists.txt new file mode 100644 index 00000000000..b31ed4ce0f2 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +if((CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS) + AND CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c) +endif() diff --git a/boards/raytac/mdbt53v_db_40/Kconfig b/boards/raytac/mdbt53v_db_40/Kconfig new file mode 100644 index 00000000000..fb688bae818 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/Kconfig @@ -0,0 +1,61 @@ +# Ratac MDBT53V-DB-40 nRF5340 board configuration + +# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "raytac_mdbt53v_db_40/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "raytac_mdbt53v_db_40/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53v_db_40/Kconfig.defconfig b/boards/raytac/mdbt53v_db_40/Kconfig.defconfig new file mode 100644 index 00000000000..9cdb1683eed --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/Kconfig.defconfig @@ -0,0 +1,77 @@ +# Raytac MDBT53V-DB-40 nRF5340 board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +config IPM_NRFX + default IPM + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET + +config BT_CTLR + default y if BT + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53v_db_40/Kconfig.raytac_mdbt53v_db_40 b/boards/raytac/mdbt53v_db_40/Kconfig.raytac_mdbt53v_db_40 new file mode 100644 index 00000000000..1d72e87151c --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/Kconfig.raytac_mdbt53v_db_40 @@ -0,0 +1,9 @@ +# Raytac MDBT53-DB-40 NRF5340 board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAYTAC_MDBT53V_DB_40 + select SOC_NRF5340_CPUAPP_QKAA if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53v_db_40/board.cmake b/boards/raytac/mdbt53v_db_40/board.cmake new file mode 100644 index 00000000000..da45d8b8e83 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/board.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/raytac/mdbt53v_db_40/board.yml b/boards/raytac/mdbt53v_db_40/board.yml new file mode 100644 index 00000000000..9d3bfd4689b --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/board.yml @@ -0,0 +1,8 @@ +board: + name: raytac_mdbt53v_db_40 + vendor: raytac + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/doc/img/MDBT53V-DB-40.jpg b/boards/raytac/mdbt53v_db_40/doc/img/MDBT53V-DB-40.jpg similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/doc/img/MDBT53V-DB-40.jpg rename to boards/raytac/mdbt53v_db_40/doc/img/MDBT53V-DB-40.jpg diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/doc/index.rst b/boards/raytac/mdbt53v_db_40/doc/index.rst similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/doc/index.rst rename to boards/raytac/mdbt53v_db_40/doc/index.rst diff --git a/boards/arm/thingy53_nrf5340/pre_dt_board.cmake b/boards/raytac/mdbt53v_db_40/pre_dt_board.cmake similarity index 100% rename from boards/arm/thingy53_nrf5340/pre_dt_board.cmake rename to boards/raytac/mdbt53v_db_40/pre_dt_board.cmake diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml similarity index 83% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml index c9552cb6202..bd576367268 100644 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml @@ -1,4 +1,4 @@ -identifier: raytac_mdbt53v_db_40_nrf5340_cpuapp +identifier: raytac_mdbt53v_db_40/nrf5340/cpuapp name: RAYTAC-MDBT53V-DB-40-NRF5340-application-MCU type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml similarity index 81% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml index 5251dc8737f..e5340237e6a 100644 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml @@ -1,4 +1,4 @@ -identifier: raytac_mdbt53v_db_40_nrf5340_cpuapp_ns +identifier: raytac_mdbt53v_db_40/nrf5340/cpuapp/ns name: RAYTAC-MDBT53V-DB-40-NRF52840-application-MCU-Non-Secure type: mcu arch: arm diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig new file mode 100644 index 00000000000..2a74dd56f41 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.dts diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml similarity index 86% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml index a76a74a6598..eb5cac4d609 100644 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml @@ -2,7 +2,7 @@ # Copyright (c) 2023 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -identifier: raytac_mdbt53v_db_40_nrf5340_cpunet +identifier: raytac_mdbt53v_db_40/nrf5340/cpunet name: RAYTAC MDBT53V-DB-40-NRF5340-network-MCU type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..56940c43a09 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c diff --git a/boards/arm64/rpi_4b/board.cmake b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_defconfig similarity index 100% rename from boards/arm64/rpi_4b/board.cmake rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_defconfig diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts diff --git a/boards/renesas/da14695_dk_usb/Kconfig.da14695_dk_usb b/boards/renesas/da14695_dk_usb/Kconfig.da14695_dk_usb new file mode 100644 index 00000000000..7a321bc345b --- /dev/null +++ b/boards/renesas/da14695_dk_usb/Kconfig.da14695_dk_usb @@ -0,0 +1,7 @@ +# DA14695 Development Kit USB board configuration + +# Copyright (c) 2023 Renesas Electronics Corporation and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DA14695_DK_USB + select SOC_DA14695 diff --git a/boards/arm/da14695_dk_usb/board.cmake b/boards/renesas/da14695_dk_usb/board.cmake similarity index 100% rename from boards/arm/da14695_dk_usb/board.cmake rename to boards/renesas/da14695_dk_usb/board.cmake diff --git a/boards/renesas/da14695_dk_usb/board.yml b/boards/renesas/da14695_dk_usb/board.yml new file mode 100644 index 00000000000..b9d3f06cb1d --- /dev/null +++ b/boards/renesas/da14695_dk_usb/board.yml @@ -0,0 +1,5 @@ +board: + name: da14695_dk_usb + vendor: renesas + socs: + - name: da14695 diff --git a/boards/arm/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi b/boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi similarity index 100% rename from boards/arm/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi rename to boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi diff --git a/boards/arm/da14695_dk_usb/da14695_dk_usb.dts b/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts similarity index 100% rename from boards/arm/da14695_dk_usb/da14695_dk_usb.dts rename to boards/renesas/da14695_dk_usb/da14695_dk_usb.dts diff --git a/boards/arm/da14695_dk_usb/da14695_dk_usb.yaml b/boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml similarity index 100% rename from boards/arm/da14695_dk_usb/da14695_dk_usb.yaml rename to boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml diff --git a/boards/arm/da14695_dk_usb/da14695_dk_usb_defconfig b/boards/renesas/da14695_dk_usb/da14695_dk_usb_defconfig similarity index 77% rename from boards/arm/da14695_dk_usb/da14695_dk_usb_defconfig rename to boards/renesas/da14695_dk_usb/da14695_dk_usb_defconfig index d0a67243034..737b2cdd1b3 100644 --- a/boards/arm/da14695_dk_usb/da14695_dk_usb_defconfig +++ b/boards/renesas/da14695_dk_usb/da14695_dk_usb_defconfig @@ -4,10 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_DA1469X=y -CONFIG_SOC_DA14695=y -CONFIG_BOARD_DA14695_DK_USB=y - CONFIG_HW_STACK_PROTECTION=y CONFIG_GPIO=y diff --git a/boards/arm/da14695_dk_usb/doc/da14695-00hqdevkt-u-usb-board.jpg b/boards/renesas/da14695_dk_usb/doc/da14695-00hqdevkt-u-usb-board.jpg similarity index 100% rename from boards/arm/da14695_dk_usb/doc/da14695-00hqdevkt-u-usb-board.jpg rename to boards/renesas/da14695_dk_usb/doc/da14695-00hqdevkt-u-usb-board.jpg diff --git a/boards/arm/da14695_dk_usb/doc/index.rst b/boards/renesas/da14695_dk_usb/doc/index.rst similarity index 100% rename from boards/arm/da14695_dk_usb/doc/index.rst rename to boards/renesas/da14695_dk_usb/doc/index.rst diff --git a/boards/renesas/da1469x_dk_pro/Kconfig.da1469x_dk_pro b/boards/renesas/da1469x_dk_pro/Kconfig.da1469x_dk_pro new file mode 100644 index 00000000000..890b918347d --- /dev/null +++ b/boards/renesas/da1469x_dk_pro/Kconfig.da1469x_dk_pro @@ -0,0 +1,7 @@ +# DA1469x series Development Kit Pro board configuration + +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DA1469X_DK_PRO + select SOC_DA14699 diff --git a/boards/arm/da1469x_dk_pro/board.cmake b/boards/renesas/da1469x_dk_pro/board.cmake similarity index 100% rename from boards/arm/da1469x_dk_pro/board.cmake rename to boards/renesas/da1469x_dk_pro/board.cmake diff --git a/boards/renesas/da1469x_dk_pro/board.yml b/boards/renesas/da1469x_dk_pro/board.yml new file mode 100644 index 00000000000..09ab03c0b26 --- /dev/null +++ b/boards/renesas/da1469x_dk_pro/board.yml @@ -0,0 +1,5 @@ +board: + name: da1469x_dk_pro + vendor: renesas + socs: + - name: da14699 diff --git a/boards/arm/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi similarity index 100% rename from boards/arm/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi rename to boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi diff --git a/boards/arm/da1469x_dk_pro/da1469x_dk_pro.dts b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts similarity index 100% rename from boards/arm/da1469x_dk_pro/da1469x_dk_pro.dts rename to boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts diff --git a/boards/arm/da1469x_dk_pro/da1469x_dk_pro.yaml b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml similarity index 100% rename from boards/arm/da1469x_dk_pro/da1469x_dk_pro.yaml rename to boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig new file mode 100644 index 00000000000..e31b6eb8457 --- /dev/null +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_GPIO=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_BUILD_OUTPUT_HEX=n + +CONFIG_I2C=y +CONFIG_I2C_CALLBACK=y diff --git a/boards/arm/da1469x_dk_pro/doc/da14695-00hqdevkt-board.jpg b/boards/renesas/da1469x_dk_pro/doc/da14695-00hqdevkt-board.jpg similarity index 100% rename from boards/arm/da1469x_dk_pro/doc/da14695-00hqdevkt-board.jpg rename to boards/renesas/da1469x_dk_pro/doc/da14695-00hqdevkt-board.jpg diff --git a/boards/arm/da1469x_dk_pro/doc/index.rst b/boards/renesas/da1469x_dk_pro/doc/index.rst similarity index 100% rename from boards/arm/da1469x_dk_pro/doc/index.rst rename to boards/renesas/da1469x_dk_pro/doc/index.rst diff --git a/boards/renesas/index.rst b/boards/renesas/index.rst new file mode 100644 index 00000000000..2597c70e29e --- /dev/null +++ b/boards/renesas/index.rst @@ -0,0 +1,10 @@ +.. _boards-renesas: + +Renesas Electronics Corporation +############################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/renesas/rcar_h3ulcb/Kconfig.defconfig b/boards/renesas/rcar_h3ulcb/Kconfig.defconfig new file mode 100644 index 00000000000..6586e5575bc --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RCAR_H3ULCB + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_RCAR_H3ULCB diff --git a/boards/renesas/rcar_h3ulcb/Kconfig.rcar_h3ulcb b/boards/renesas/rcar_h3ulcb/Kconfig.rcar_h3ulcb new file mode 100644 index 00000000000..87d3065cd8f --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/Kconfig.rcar_h3ulcb @@ -0,0 +1,6 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RCAR_H3ULCB + select SOC_R8A77951_R7 if BOARD_RCAR_H3ULCB_R8A77951_R7 + select SOC_R8A77951_A57 if BOARD_RCAR_H3ULCB_R8A77951_A57 diff --git a/boards/renesas/rcar_h3ulcb/board.cmake b/boards/renesas/rcar_h3ulcb/board.cmake new file mode 100644 index 00000000000..963f11d9f47 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_RCAR_H3ULCB_R8A77951_R7) + board_runner_args(openocd "--use-elf") + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +endif() diff --git a/boards/renesas/rcar_h3ulcb/board.yml b/boards/renesas/rcar_h3ulcb/board.yml new file mode 100644 index 00000000000..7989c688e81 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/board.yml @@ -0,0 +1,5 @@ +board: + name: rcar_h3ulcb + vendor: renesas + socs: + - name: r8a77951 diff --git a/boards/arm64/rcar_h3ulcb_ca57/doc/img/rcar_h3ulcb_bottom.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_bottom.jpg similarity index 100% rename from boards/arm64/rcar_h3ulcb_ca57/doc/img/rcar_h3ulcb_bottom.jpg rename to boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_bottom.jpg diff --git a/boards/arm/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg similarity index 100% rename from boards/arm/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg rename to boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg diff --git a/boards/arm/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg similarity index 100% rename from boards/arm/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg rename to boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg diff --git a/boards/arm64/rcar_h3ulcb_ca57/doc/img/rcar_h3ulcb_top.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_top.jpg similarity index 100% rename from boards/arm64/rcar_h3ulcb_ca57/doc/img/rcar_h3ulcb_top.jpg rename to boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_top.jpg diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst new file mode 100644 index 00000000000..038666ad623 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst @@ -0,0 +1,85 @@ +.. _rcar_h3ulcb_ca57: + +R-CAR H3 ARM CA57 (ARMv8) +######################### + +Overview +******** +The R-Car H3 is an SOC that features the basic functions for next-generation +car navigation systems. + +Hardware +******** +The R-Car H3 includes: + +* four 1.5-GHz ARM Cortex-A57 MPCore cores; +* four 1.2-GHz ARM Cortex-A53 MPCore cores; +* memory controller for LPDDR4-3200 with 32 bits x 4 channels; +* 2 channels for HDMI1.4b output and 1channel for RGB888 output and 1channel for LVDS; +* 4 channels MIPI-CSI2 Video Input, 2channels digital Video Input; +* serial ATA interface; +* USB3.0 x 2ch and USB2.0 x 3ch interfaces; +* 800-MHz ARM Cortex-R7 core; +* two- and three-dimensional graphics engines; +* video processing units; +* sound processing units; +* MediaLB interface; +* SD card host interface; +* USB3.0 and USB2.0 interfaces; +* PCI Express interface; +* CAN interface; +* EtherAVB. + +Connections and IOs +=================== + +H3ULCB Board +------------ + +Here are official IOs figures from eLinux for H3ULCB board: + +.. figure:: img/rcar_h3ulcb_top.jpg + :align: center + +.. figure:: img/rcar_h3ulcb_bottom.jpg + :align: center + +Supported Features +================== +The Renesas rcar_h3ulcb_ca57 board configuration supports the following +hardware features: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINCTRL | pinctrl | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++-----------+------------------------------+--------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig`` + +Programming and Debugging +************************* + +Flashing +======== + +The flash on board is not supported by Zephyr at this time. + +References +********** + +- `Renesas R-Car Development Support website`_ +- `eLinux R-Car Starter Kit page`_ + +.. _Renesas R-Car Development Support website: + https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support + +.. _eLinux R-Car Starter Kit page: + https://elinux.org/R-Car/Boards/H3SK diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst new file mode 100644 index 00000000000..5fcd4fa0909 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst @@ -0,0 +1,276 @@ +.. _rcar_h3ulcb_boards: + +Renesas R-Car H3ULCB +#################### + +Overview +******** +- The H3 Starter Kit board is designed for evaluating the features and performance of the R-CAR H3 device from Renesas Electronics and it is also used for developing and evaluating application software for these R-CAR H3. + +- The H3 Starter Kit, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, via 440pin connector on bottom side. + +It is possible to order 2 different types of H3 Starter Kit Boards, one with Ethernet connection onboard and one with Ethernet connection on ComExpress. + +.. figure:: img/rcar_h3ulcb_starter_kit.jpg + :align: center + :alt: R-Car starter kit + +.. note:: The H3ULCB board can be plugged on a Renesas Kingfisher Infotainment daughter board through COM Express connector in order to physically access more I/O. CAUTION: In this case, power supply is managed by the daughter board. + +More information about the board can be found at `Renesas R-Car Starter Kit website`_. + +Hardware +******** + +Hardware capabilities for the H3ULCB for can be found on the `eLinux H3SK page`_ of the board. + +.. figure:: img/rcar_h3ulcb_features.jpg + :align: center + :alt: R-Car starter kit features + +.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. + +More information about the SoC that equips the board can be found here: + +- `Renesas R-Car H3 chip`_ + +Supported Features +================== + +Here is the current supported features when running Zephyr Project on the R-Car ULCB CR7: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINMUX | pinmux | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| GPIO | gpio | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++ + + + +| | FT232RQ / CP2102 | serial port-interrupt | ++-----------+------------------------------+--------------------------------+ +| CAN | can | normal mode | ++ + + + +| | TCAN332GDCNT | loopback mode | ++-----------+------------------------------+--------------------------------+ +| I2C | i2c | interrupt driven | ++-----------+------------------------------+--------------------------------+ +| PWM | pwm | All channels | ++-----------+------------------------------+--------------------------------+ + +It's also currently possible to write on the ram console. + +More features will be supported soon. + +Connections and IOs +=================== + +H3ULCB Board +------------ + +Here are official IOs figures from eLinux for H3ULCB board: + +`H3SK top view`_ + +`H3SK bottom view`_ + +Kingfisher Infotainment daughter board +-------------------------------------- + +When connected to Kingfisher Infotainment board through COMExpress connector, the board is exposing much more IOs. + +Here are official IOs figures from eLinux for Kingfisher Infotainment board: + +`Kingfisher top view`_ + +`Kingfisher bottom view`_ + +GPIO +---- + +By running Zephyr on H3ULCB, the software readable push button 'SW3' can be used as input, and the software controllable LED 'LED5' can be used as output. + +UART +---- + +H3ULCB board is providing two serial ports, only one is commonly available on the board, however, the second one can be made available either by welding components or by plugging the board on a Kingfisher Infotainment daughter board. + +Here is information about these serial ports: + ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| Physical Interface | Physical Location | Software Interface | Converter | Further Information | ++====================+===================+====================+===========+======================================+ +| CN12 DEBUG SERIAL | ULCB Board | SCIF2 | FT232RQ | Used by U-BOOT & Linux | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| CN10 DEBUG SERIAL | ULCB Board | SCIF1 | CP2102 | Non-welded | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| CN04 DEBUG SERIAL | Kingfisher | SCIF1 | | Secondary UART // Through ComExpress | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ + +.. note:: The Zephyr console output is assigned to SCIF1 (commonly used on Kingfisher daughter board) with settings 115200 8N1 without hardware flow control by default. + +Here is CN04 UART interface pinout (depending on your Kingfisher board version): + ++--------+----------+----------+ +| Signal | Pin KF03 | Pin KF04 | ++========+==========+==========+ +| RXD | 3 | 4 | ++--------+----------+----------+ +| TXD | 5 | 2 | ++--------+----------+----------+ +| RTS | 4 | 1 | ++--------+----------+----------+ +| CTS | 6 | 3 | ++--------+----------+----------+ +| GND | 9 | 6 | ++--------+----------+----------+ + +CAN +--- + +H3ULCB board provides two CAN interfaces. Both interfaces are available on the Kingfisher daughter board. + ++--------------------+--------------------+--------------+ +| Physical Interface | Software Interface | Transceiver | ++====================+====================+==============+ +| CN17 | CAN0 | TCAN332GDCNT | ++--------------------+--------------------+--------------+ +| CN18 | CAN1 | TCAN332GDCNT | ++--------------------+--------------------+--------------+ + +.. note:: Interfaces are set to 125 kbit/s by default. + +The following table lists CAN physical interfaces pinout: + ++-----+--------+ +| Pin | Signal | ++=====+========+ +| 1 | CANH | ++-----+--------+ +| 2 | CANL | ++-----+--------+ +| 3 | GND | ++-----+--------+ + +I2C +--- + +H3ULCB board provides two I2C buses. Unfortunately direct access to these buses is not available through connectors. + +I2C is mainly used to manage and power on multiple of onboard chips on the H3ULCB and Kingfisher daughter board. + +Embedded I2C devices and I/O expanders are not yet supported. The current I2C support therefore does not make any devices available to the user at this time. + +PWM +--- + +ULCB boards provide one PWM controller with a maximum of 7 channels [0..6]. H3ULCB does provide the pwm0 from test pin CP8 only. + +When plugged on a Kingfisher daughter board, pwm4 channel is available on CN7 LVDS connector. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Supported Debug Probe +===================== + +The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This probe is supported by OpenOCD that is shipped with the Zephyr SDK. + +The "Olimex ARM-USB-OCD-H" probe needs to be connected with a SICA20I2P adapter to CN3 on H3ULCB. + +.. note:: + See `eLinux Kingfisher page`_ "Known issues" section if you encounter problem with JTAG. + +Configuring a Console +===================== + +Connect a USB cable from your PC to CN04 of your Kingfisher daughter board. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +First of all, open your serial terminal. + +Applications for the ``rcar_h3ulcb/r8a77951/r7`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_h3ulcb/r8a77951/r7 + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_h3ulcb + +Debugging +========= + +First of all, open your serial terminal. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_h3ulcb/r8a77951/r7 + :goals: debug + +You will then get access to a GDB session for debug. + +By continuing the app, you should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_h3ulcb + +References +********** + +- `Renesas R-Car Starter Kit website`_ +- `Renesas R-Car H3 chip`_ +- `eLinux H3SK page`_ +- `eLinux Kingfisher page`_ + +.. _Renesas R-Car Starter Kit website: + https://www.renesas.com/br/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-m3-starter-kit + +.. _Renesas R-Car H3 chip: + https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support + +.. _eLinux H3SK page: + https://elinux.org/R-Car/Boards/H3SK + +.. _H3SK top view: + https://elinux.org/images/1/1f/R-Car-H3-topview.jpg + +.. _H3SK bottom view: + https://elinux.org/images/c/c2/R-Car-H3-bottomview.jpg + +.. _eLinux Kingfisher page: + https://elinux.org/R-Car/Boards/Kingfisher + +.. _Kingfisher top view: + https://elinux.org/images/0/08/Kfisher_top_specs.png + +.. _Kingfisher bottom view: + https://elinux.org/images/0/06/Kfisher_bot_specs.png + +.. _Install a toolchain: + https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57-pinctrl.dtsi b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi similarity index 100% rename from boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57-pinctrl.dtsi rename to boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts new file mode 100644 index 00000000000..5a2bef11c82 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include +#include "rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi" + +/ { + model = "H3ULCB CA57"; + + chosen { + zephyr,sram = &ram; + zephyr,console = &scif2; + zephyr,shell-uart = &scif2; + }; + + ram: memory@48000000 { + device_type = "mmio-sram"; + reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_data_a_tx_default &scif2_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.yaml b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.yaml new file mode 100644 index 00000000000..13d59c78801 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.yaml @@ -0,0 +1,17 @@ +identifier: rcar_h3ulcb/r8a77951/a57 +name: Renesas H3ULCB based on r8a77951 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 512 +supported: + - clock_control + - uart +testing: + ignore_tags: + - net + - bluetooth + - isotp +vendor: renesas diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig new file mode 100644 index 00000000000..802c04ef5ea --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8300000 +CONFIG_XIP=n + +CONFIG_MAX_XLAT_TABLES=24 +CONFIG_ARMV8_A_NS=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable clock control +CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7-pinctrl.dtsi b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7-pinctrl.dtsi similarity index 100% rename from boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7-pinctrl.dtsi rename to boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7-pinctrl.dtsi diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.dts b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.dts new file mode 100644 index 00000000000..a5a23e779d8 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.dts @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2021 IoT.bzh + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include "rcar_h3ulcb_r8a77951_r7-pinctrl.dtsi" +#include + +/ { + model = "Renesas h3ulcb board"; + compatible = "renesas,h3ulcb-cr7"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &scif1; + zephyr,shell-uart = &scif1; + zephyr,canbus = &can0; + }; + + leds { + compatible = "gpio-leds"; + user_led: led_5 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: sw3 { + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + label = "User switch"; + zephyr,code = ; + }; + }; + + aliases { + pwm-0 = &pwm0; + led0 = &user_led; + sw0 = &user_button; + }; +}; + +&cmt0 { + status = "okay"; + clock-frequency = <32000>; +}; + +&gpio6 { + status = "okay"; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_default>; + pinctrl-names = "default"; +}; + +&can0 { + pinctrl-0 = <&can0_data_a_tx_default &can0_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; + bus-speed = <125000>; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_data_a_tx_default &scif1_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.yaml b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.yaml new file mode 100644 index 00000000000..30e9cfb1f18 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.yaml @@ -0,0 +1,17 @@ +identifier: rcar_h3ulcb/r8a77951/r7 +name: Cortex r7 for Renesas H3ULCB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - i2c + - can + - gpio + - clock_control + - uart +testing: + ignore_tags: + - isotp +vendor: renesas diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7_defconfig b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7_defconfig new file mode 100644 index 00000000000..b70c8f29e22 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7_defconfig @@ -0,0 +1,10 @@ +CONFIG_CLOCK_CONTROL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000 +CONFIG_CONSOLE=y +CONFIG_RAM_CONSOLE=y +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0 +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/renesas/rcar_salvator_x/Kconfig.rcar_salvator_x b/boards/renesas/rcar_salvator_x/Kconfig.rcar_salvator_x new file mode 100644 index 00000000000..eac2470dc3e --- /dev/null +++ b/boards/renesas/rcar_salvator_x/Kconfig.rcar_salvator_x @@ -0,0 +1,5 @@ +# Copyright (c) 2022 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RCAR_SALVATOR_X + select SOC_R8A77951_R7 diff --git a/boards/arm/rcar_h3_salvatorx/board.cmake b/boards/renesas/rcar_salvator_x/board.cmake similarity index 100% rename from boards/arm/rcar_h3_salvatorx/board.cmake rename to boards/renesas/rcar_salvator_x/board.cmake diff --git a/boards/renesas/rcar_salvator_x/board.yml b/boards/renesas/rcar_salvator_x/board.yml new file mode 100644 index 00000000000..b85c3aebe67 --- /dev/null +++ b/boards/renesas/rcar_salvator_x/board.yml @@ -0,0 +1,5 @@ +board: + name: rcar_salvator_x + vendor: renesas + socs: + - name: r8a77951 diff --git a/boards/arm/rcar_h3_salvatorx/doc/img/r-car-h3-salvator-x-connections.jpg b/boards/renesas/rcar_salvator_x/doc/img/r-car-h3-salvator-x-connections.jpg similarity index 100% rename from boards/arm/rcar_h3_salvatorx/doc/img/r-car-h3-salvator-x-connections.jpg rename to boards/renesas/rcar_salvator_x/doc/img/r-car-h3-salvator-x-connections.jpg diff --git a/boards/arm/rcar_h3_salvatorx/doc/img/rcar_h3_features.jpg b/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_features.jpg similarity index 100% rename from boards/arm/rcar_h3_salvatorx/doc/img/rcar_h3_features.jpg rename to boards/renesas/rcar_salvator_x/doc/img/rcar_h3_features.jpg diff --git a/boards/arm/rcar_h3_salvatorx/doc/img/rcar_h3_salvatorx.jpg b/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_salvatorx.jpg similarity index 100% rename from boards/arm/rcar_h3_salvatorx/doc/img/rcar_h3_salvatorx.jpg rename to boards/renesas/rcar_salvator_x/doc/img/rcar_h3_salvatorx.jpg diff --git a/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst new file mode 100644 index 00000000000..e95049a42c4 --- /dev/null +++ b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst @@ -0,0 +1,183 @@ +.. _rcar_h3_salvatorx_boards: + +Renesas R-Car H3 Salvator-X +########################### + +Overview +******** +- The H3 Salvator-X board is designed for evaluating the features and performance + of the R-CAR H3 device from Renesas Electronics and it is also used for developing + and evaluating application software for these R-CAR H3. + +- The H3 Salvator-X, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, + each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces + like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, + via 440pin connector on bottom side. + +.. figure:: img/rcar_h3_salvatorx.jpg + :align: center + :alt: R-Car Salvator-X kit + +More information about the board can be found at `Renesas R-Car Development Support website`_. + +Hardware +******** + +Hardware capabilities for the H3 Salvator-X for can be found on the `eLinux H3 Salvator-X page`_ +of the board. + +.. figure:: img/rcar_h3_features.jpg + :align: center + :alt: R-Car Salvator-X features + +.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. + +More information about the SoC that equips the board can be found here: + +- `Renesas R-Car H3 chip`_ + +Supported Features +================== + +Here is the current supported features when running Zephyr Project on the R-Car Salvator-X CR7: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINCTRL | pinctrl | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| GPIO | gpio | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++ + + + +| | FT232RQ / CP2102 | serial port-interrupt | ++-----------+------------------------------+--------------------------------+ +| CAN | can | normal mode | ++ + + + +| | TCAN332GDCNT | loopback mode | ++-----------+------------------------------+--------------------------------+ +| I2C | i2c | interrupt driven | ++-----------+------------------------------+--------------------------------+ + +It's also currently possible to write on the ram console. + +Connections and IOs +=================== + +.. figure:: img/r-car-h3-salvator-x-connections.jpg + :align: center + :alt: R-Car Salvator-X connections + +GPIO +---- + +By running Zephyr on H3 Salvator-X, the software readable push buttons 'SW20', +'SW21', 'SW22' can be used as input, and the software contollable LEDs 'LED4', +'LED5', 'LED6' can be used as output. + +UART +---- + +Salvator-X board is providing two serial ports: + +- one is for A53/A57 processors +- the other one is for CR7 + +Both ports are converted to USB through CP2102 converters and they are exposed +as follows: + ++-----------+-----------+ +| Connector | Processor | ++===========+===========+ +| CN25 | A53/A57 | ++-----------+-----------+ +| CN26 | CR7 | ++-----------+-----------+ + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Supported Debug Probe +===================== + +The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This +probe is supported by OpenOCD that is shipped with the Zephyr SDK. + +The "Olimex ARM-USB-OCD-H" probe needs to be connected to CN1 on Salvator-X. + +Configuring a Console +===================== + +Connect a USB cable from your PC to CN25 and/or CN26 then use the following +settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +First of all, open your serial terminal. + +Applications for the ``rcar_salvator_x`` board configuration can be built +in the usual way (see :ref:`build_an_application` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_salvator_x + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_salvator_x + +Debugging +========= + +First of all, open your serial terminal. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_salvator_x + :goals: debug + +You will then get access to a GDB session for debug. + +By continuing the app, you should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_salvator_x + +References +********** + +- `Renesas R-Car H3 chip`_ +- `Renesas R-Car Development Support website`_ +- `eLinux H3 Salvator-X page`_ + +.. _Renesas R-Car H3 chip: + https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support + +.. _Renesas R-Car Development Support website: + https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support + +.. _eLinux H3 Salvator-X page: + https://elinux.org/R-Car/Boards/Salvator-X + +.. _Install a toolchain: + https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7-pinctrl.dtsi b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7-pinctrl.dtsi similarity index 100% rename from boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7-pinctrl.dtsi rename to boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7-pinctrl.dtsi diff --git a/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.dts b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.dts new file mode 100644 index 00000000000..ce5c046f54a --- /dev/null +++ b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.dts @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2022 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include "rcar_salvator_x_r8a77951_r7-pinctrl.dtsi" +#include + +/ { + model = "Renesas h3 Salvator-X board"; + compatible = "renesas,h3-salvatorx-cr7"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &scif1; + zephyr,shell-uart = &scif1; + zephyr,canbus = &can0; + }; + + leds { + compatible = "gpio-leds"; + user_led_0: led_4 { + gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; + label = "led4"; + }; + user_led_1: led_5 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + label = "led5"; + }; + user_led_2: led_6 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + label = "led6"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_0: sw20 { + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + label = "sw20"; + zephyr,code = ; + }; + user_button_1: sw21 { + gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + label = "sw21"; + zephyr,code = ; + }; + user_button_2: sw22 { + gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; + label = "sw22"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &user_led_1; + sw0 = &user_button_0; + }; +}; + +&cmt0 { + status = "okay"; + clock-frequency = <32000>; +}; + +&gpio6 { + status = "okay"; +}; + +&can0 { + pinctrl-0 = <&can0_data_a_tx_default &can0_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; + bus-speed = <125000>; +}; + +&scif1 { + pinctrl-0 = <&scif1_data_a_tx_default &scif1_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; diff --git a/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.yaml b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.yaml new file mode 100644 index 00000000000..589a0ec03a6 --- /dev/null +++ b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.yaml @@ -0,0 +1,16 @@ +identifier: rcar_salvator_x/r8a77951/r7 +name: Cortex r7 for Renesas H3 Salvator-X +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - i2c + - gpio + - clock_control + - uart +testing: + ignore_tags: + - isotp +vendor: renesas diff --git a/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7_defconfig b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7_defconfig new file mode 100644 index 00000000000..b70c8f29e22 --- /dev/null +++ b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7_defconfig @@ -0,0 +1,10 @@ +CONFIG_CLOCK_CONTROL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000 +CONFIG_CONSOLE=y +CONFIG_RAM_CONSOLE=y +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0 +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/rcar_h3_salvatorx/support/openocd.cfg b/boards/renesas/rcar_salvator_x/support/openocd.cfg similarity index 100% rename from boards/arm/rcar_h3_salvatorx/support/openocd.cfg rename to boards/renesas/rcar_salvator_x/support/openocd.cfg diff --git a/boards/renesas/rcar_salvator_xs/Kconfig.defconfig b/boards/renesas/rcar_salvator_xs/Kconfig.defconfig new file mode 100644 index 00000000000..099fee1ebd8 --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RCAR_SALVATOR_XS + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_RCAR_SALVATOR_XS diff --git a/boards/renesas/rcar_salvator_xs/Kconfig.rcar_salvator_xs b/boards/renesas/rcar_salvator_xs/Kconfig.rcar_salvator_xs new file mode 100644 index 00000000000..d18a34388ff --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/Kconfig.rcar_salvator_xs @@ -0,0 +1,5 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RCAR_SALVATOR_XS + select SOC_R8A77961 diff --git a/boards/renesas/rcar_salvator_xs/board.yml b/boards/renesas/rcar_salvator_xs/board.yml new file mode 100644 index 00000000000..b48fda7ff48 --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/board.yml @@ -0,0 +1,5 @@ +board: + name: rcar_salvator_xs + vendor: renesas + socs: + - name: r8a77961 diff --git a/boards/renesas/rcar_salvator_xs/doc/index.rst b/boards/renesas/rcar_salvator_xs/doc/index.rst new file mode 100644 index 00000000000..a9900158169 --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/doc/index.rst @@ -0,0 +1,68 @@ +.. _rcar_salvator_xs: + +R-CAR Salvator XS M3 ARM CA57 (ARMv8) +##################################### + +Overview +******** +The R-Car M3-W is an SOC that features the basic functions for next-generation +car navigation systems. + +Hardware +******** +The R-Car M3-W includes: + +* two 1.5-GHz ARM Cortex-A57 MPCore cores; +* four 1.3-GHz ARM Cortex-A53 MPCore cores, +* memory controller for LPDDR4-3200 with 32 bits x 2 channels; +* 1 channels for HDMI1.4b output and 1 channel for RGB888 output and 1channel for LVDS; +* 2 channels MIPI-CSI2 Video Input, 2 channels digital Video Input; +* USB3.0 x 1ch and USB2.0 x 2ch interfaces; +* 800-MHz ARM Cortex-R7 core; +* two- and three-dimensional graphics engines; +* video processing units; +* sound processing units; +* MediaLB interface; +* SD card host interface; +* USB3.0 and USB2.0 interfaces; +* PCI Express interface; +* CAN interface; +* EtherAVB. + +Supported Features +================== +The Renesas rcar_salvator_xs board configuration supports the following +hardware features: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINCTRL | pinctrl | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++-----------+------------------------------+--------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig` + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +References +********** + +- `Renesas R-Car Development Support website`_ +- `eLinux Salvator-XS page`_ + +.. _Renesas R-Car Development Support website: + https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support + +.. _eLinux Salvator-XS page: + https://elinux.org/R-Car/Boards/Salvator-XS diff --git a/boards/arm64/rcar_salvator_xs_m3/salvator_xs_m3-pinctrl.dtsi b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs-pinctrl.dtsi similarity index 100% rename from boards/arm64/rcar_salvator_xs_m3/salvator_xs_m3-pinctrl.dtsi rename to boards/renesas/rcar_salvator_xs/rcar_salvator_xs-pinctrl.dtsi diff --git a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts new file mode 100644 index 00000000000..9c6bfc9a6eb --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include +#include "rcar_salvator_xs-pinctrl.dtsi" + +/ { + model = "Salvator XS M3"; + + chosen { + zephyr,sram = &ram; + zephyr,console = &scif2; + zephyr,shell-uart = &scif2; + }; + + ram: memory@48000000 { + device_type = "mmio-sram"; + reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_data_a_tx_default &scif2_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.yaml b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.yaml new file mode 100644 index 00000000000..904c5dc58d9 --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.yaml @@ -0,0 +1,17 @@ +identifier: rcar_salvator_xs +name: Renesas Salvator XS M3 based on r8a77961 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 512 +supported: + - clock_control + - uart +testing: + ignore_tags: + - net + - bluetooth + - isotp +vendor: renesas diff --git a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig new file mode 100644 index 00000000000..802c04ef5ea --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8300000 +CONFIG_XIP=n + +CONFIG_MAX_XLAT_TABLES=24 +CONFIG_ARMV8_A_NS=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable clock control +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/rcar_spider_s4/Kconfig.rcar_spider_s4 b/boards/renesas/rcar_spider_s4/Kconfig.rcar_spider_s4 new file mode 100644 index 00000000000..7f6bacf4894 --- /dev/null +++ b/boards/renesas/rcar_spider_s4/Kconfig.rcar_spider_s4 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RCAR_SPIDER_S4 + select SOC_R8A779F0 diff --git a/boards/arm/rcar_h3ulcb/board.cmake b/boards/renesas/rcar_spider_s4/board.cmake similarity index 100% rename from boards/arm/rcar_h3ulcb/board.cmake rename to boards/renesas/rcar_spider_s4/board.cmake diff --git a/boards/renesas/rcar_spider_s4/board.yml b/boards/renesas/rcar_spider_s4/board.yml new file mode 100644 index 00000000000..560ed7f2ae8 --- /dev/null +++ b/boards/renesas/rcar_spider_s4/board.yml @@ -0,0 +1,5 @@ +board: + name: rcar_spider_s4 + vendor: renesas + socs: + - name: r8a779f0 diff --git a/boards/arm/rcar_spider/doc/img/rcar_s4_block_diagram.jpg b/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_block_diagram.jpg similarity index 100% rename from boards/arm/rcar_spider/doc/img/rcar_s4_block_diagram.jpg rename to boards/renesas/rcar_spider_s4/doc/img/rcar_s4_block_diagram.jpg diff --git a/boards/arm/rcar_spider/doc/img/rcar_s4_spider_full.jpg b/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_spider_full.jpg similarity index 100% rename from boards/arm/rcar_spider/doc/img/rcar_s4_spider_full.jpg rename to boards/renesas/rcar_spider_s4/doc/img/rcar_s4_spider_full.jpg diff --git a/boards/arm/rcar_spider/doc/rcar_spider.rst b/boards/renesas/rcar_spider_s4/doc/rcar_spider.rst similarity index 97% rename from boards/arm/rcar_spider/doc/rcar_spider.rst rename to boards/renesas/rcar_spider_s4/doc/rcar_spider.rst index 33deb1f27a8..933c7054130 100644 --- a/boards/arm/rcar_spider/doc/rcar_spider.rst +++ b/boards/renesas/rcar_spider_s4/doc/rcar_spider.rst @@ -141,12 +141,12 @@ Flashing First of all, open your serial terminal. -Applications for the ``rcar_spider_cr52`` board configuration can be built in the +Applications for the ``rcar_spider_s4`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: rcar_spider_cr52 + :board: rcar_spider_s4 :goals: flash You should see the following message in the terminal: @@ -154,7 +154,7 @@ You should see the following message in the terminal: .. code-block:: console *** Booting Zephyr OS build v3.3.0-rc2 *** - Hello World! rcar_spider_cr52 + Hello World! rcar_spider_s4 Debugging ========= @@ -165,7 +165,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: rcar_spider_cr52 + :board: rcar_spider_s4 :goals: debug You will then get access to a GDB session for debugging. @@ -175,7 +175,7 @@ By continuing the app, you should see the following message in the terminal: .. code-block:: console *** Booting Zephyr OS build v3.3.0-rc2 *** - Hello World! rcar_spider_cr52 + Hello World! rcar_spider_s4 References ********** diff --git a/boards/arm/rcar_spider/rcar_spider_cr52-pinctrl.dtsi b/boards/renesas/rcar_spider_s4/rcar_spider_s4-pinctrl.dtsi similarity index 100% rename from boards/arm/rcar_spider/rcar_spider_cr52-pinctrl.dtsi rename to boards/renesas/rcar_spider_s4/rcar_spider_s4-pinctrl.dtsi diff --git a/boards/renesas/rcar_spider_s4/rcar_spider_s4.dts b/boards/renesas/rcar_spider_s4/rcar_spider_s4.dts new file mode 100644 index 00000000000..367c867682d --- /dev/null +++ b/boards/renesas/rcar_spider_s4/rcar_spider_s4.dts @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2023 IoT.bzh + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include "rcar_spider_s4-pinctrl.dtsi" +#include + +/ { + model = "Renesas Spider board"; + compatible = "renesas,spider-s4"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &scif0; + zephyr,shell-uart = &scif0; + }; + + leds { + compatible = "gpio-leds"; + user_led: led_8 { + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: sw10 { + gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; + label = "User switch"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &user_led; + sw0 = &user_button; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_data_tx_default &scif0_data_rx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; diff --git a/boards/renesas/rcar_spider_s4/rcar_spider_s4.yaml b/boards/renesas/rcar_spider_s4/rcar_spider_s4.yaml new file mode 100644 index 00000000000..92b98f20d30 --- /dev/null +++ b/boards/renesas/rcar_spider_s4/rcar_spider_s4.yaml @@ -0,0 +1,11 @@ +identifier: rcar_spider_s4 +name: Cortex r52 for Renesas Spider +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - clock_control + - uart diff --git a/boards/renesas/rcar_spider_s4/rcar_spider_s4_defconfig b/boards/renesas/rcar_spider_s4/rcar_spider_s4_defconfig new file mode 100644 index 00000000000..0b1a3fb8df8 --- /dev/null +++ b/boards/renesas/rcar_spider_s4/rcar_spider_s4_defconfig @@ -0,0 +1,10 @@ +CONFIG_CLOCK_CONTROL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12500000 +CONFIG_CONSOLE=y +CONFIG_RAM_CONSOLE=y +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0 +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y diff --git a/boards/arm/rcar_spider/support/openocd.cfg b/boards/renesas/rcar_spider_s4/support/openocd.cfg similarity index 100% rename from boards/arm/rcar_spider/support/openocd.cfg rename to boards/renesas/rcar_spider_s4/support/openocd.cfg diff --git a/boards/renesas/rzt2m_starterkit/Kconfig.rzt2m_starter_kit b/boards/renesas/rzt2m_starterkit/Kconfig.rzt2m_starter_kit new file mode 100644 index 00000000000..83f98b5c90b --- /dev/null +++ b/boards/renesas/rzt2m_starterkit/Kconfig.rzt2m_starter_kit @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RZT2M_STARTER_KIT + select SOC_RENESAS_RZT2M diff --git a/boards/arm/rzt2m_starterkit/board.cmake b/boards/renesas/rzt2m_starterkit/board.cmake similarity index 100% rename from boards/arm/rzt2m_starterkit/board.cmake rename to boards/renesas/rzt2m_starterkit/board.cmake diff --git a/boards/renesas/rzt2m_starterkit/board.yml b/boards/renesas/rzt2m_starterkit/board.yml new file mode 100644 index 00000000000..def32c06cd2 --- /dev/null +++ b/boards/renesas/rzt2m_starterkit/board.yml @@ -0,0 +1,5 @@ +board: + name: rzt2m_starter_kit + vendor: renesas + socs: + - name: renesas_rzt2m diff --git a/boards/arm/rzt2m_starterkit/doc/index.rst b/boards/renesas/rzt2m_starterkit/doc/index.rst similarity index 100% rename from boards/arm/rzt2m_starterkit/doc/index.rst rename to boards/renesas/rzt2m_starterkit/doc/index.rst diff --git a/boards/arm/rzt2m_starterkit/doc/rzt2m_starterkit.png b/boards/renesas/rzt2m_starterkit/doc/rzt2m_starterkit.png similarity index 100% rename from boards/arm/rzt2m_starterkit/doc/rzt2m_starterkit.png rename to boards/renesas/rzt2m_starterkit/doc/rzt2m_starterkit.png diff --git a/boards/arm/rzt2m_starterkit/rzt2m_starter_kit.yaml b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit.yaml similarity index 100% rename from boards/arm/rzt2m_starterkit/rzt2m_starter_kit.yaml rename to boards/renesas/rzt2m_starterkit/rzt2m_starter_kit.yaml diff --git a/boards/arm/rzt2m_starterkit/rzt2m_starter_kit.dts b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts similarity index 100% rename from boards/arm/rzt2m_starterkit/rzt2m_starter_kit.dts rename to boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts diff --git a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m_defconfig b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m_defconfig new file mode 100644 index 00000000000..18f0eb4aee7 --- /dev/null +++ b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m_defconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/renode/index.rst b/boards/renode/index.rst new file mode 100644 index 00000000000..dcad0d00dcf --- /dev/null +++ b/boards/renode/index.rst @@ -0,0 +1,10 @@ +.. _boards-renode: + +Renode +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/renode/riscv32_virtual/Kconfig.riscv32_virtual b/boards/renode/riscv32_virtual/Kconfig.riscv32_virtual new file mode 100644 index 00000000000..ead3da9543e --- /dev/null +++ b/boards/renode/riscv32_virtual/Kconfig.riscv32_virtual @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Meta +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RISCV32_VIRTUAL + select SOC_RISCV_VIRTUAL_RENODE diff --git a/boards/riscv/riscv32_virtual/board.cmake b/boards/renode/riscv32_virtual/board.cmake similarity index 100% rename from boards/riscv/riscv32_virtual/board.cmake rename to boards/renode/riscv32_virtual/board.cmake diff --git a/boards/renode/riscv32_virtual/board.yml b/boards/renode/riscv32_virtual/board.yml new file mode 100644 index 00000000000..b059266009a --- /dev/null +++ b/boards/renode/riscv32_virtual/board.yml @@ -0,0 +1,5 @@ +board: + name: riscv32_virtual + vendor: renode + socs: + - name: riscv_virtual_renode diff --git a/boards/riscv/riscv32_virtual/doc/index.rst b/boards/renode/riscv32_virtual/doc/index.rst similarity index 100% rename from boards/riscv/riscv32_virtual/doc/index.rst rename to boards/renode/riscv32_virtual/doc/index.rst diff --git a/boards/riscv/riscv32_virtual/riscv32_virtual.dts b/boards/renode/riscv32_virtual/riscv32_virtual.dts similarity index 100% rename from boards/riscv/riscv32_virtual/riscv32_virtual.dts rename to boards/renode/riscv32_virtual/riscv32_virtual.dts diff --git a/boards/riscv/riscv32_virtual/riscv32_virtual.yaml b/boards/renode/riscv32_virtual/riscv32_virtual.yaml similarity index 100% rename from boards/riscv/riscv32_virtual/riscv32_virtual.yaml rename to boards/renode/riscv32_virtual/riscv32_virtual.yaml diff --git a/boards/riscv/riscv32_virtual/riscv32_virtual_defconfig b/boards/renode/riscv32_virtual/riscv32_virtual_defconfig similarity index 78% rename from boards/riscv/riscv32_virtual/riscv32_virtual_defconfig rename to boards/renode/riscv32_virtual/riscv32_virtual_defconfig index 4dcad0a7ea1..911302fc640 100644 --- a/boards/riscv/riscv32_virtual/riscv32_virtual_defconfig +++ b/boards/renode/riscv32_virtual/riscv32_virtual_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2023 Meta # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_RISCV32_VIRTUAL_RENODE=y -CONFIG_BOARD_RISCV32_VIRTUAL=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/riscv32_virtual/support/riscv32_virtual.repl b/boards/renode/riscv32_virtual/support/riscv32_virtual.repl similarity index 100% rename from boards/riscv/riscv32_virtual/support/riscv32_virtual.repl rename to boards/renode/riscv32_virtual/support/riscv32_virtual.repl diff --git a/boards/riscv/riscv32_virtual/support/riscv32_virtual.resc b/boards/renode/riscv32_virtual/support/riscv32_virtual.resc similarity index 100% rename from boards/riscv/riscv32_virtual/support/riscv32_virtual.resc rename to boards/renode/riscv32_virtual/support/riscv32_virtual.resc diff --git a/boards/riscv/adp_xc7k_ae350/Kconfig.board b/boards/riscv/adp_xc7k_ae350/Kconfig.board deleted file mode 100644 index 5b58e01fbfd..00000000000 --- a/boards/riscv/adp_xc7k_ae350/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Andes Technology Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADP_XC7K_AE350 - bool "Andes ADP-XC7K AE350 Platform" - depends on SOC_ANDES_AE350 diff --git a/boards/riscv/adp_xc7k_ae350/Kconfig.defconfig b/boards/riscv/adp_xc7k_ae350/Kconfig.defconfig deleted file mode 100644 index 7438c2eae72..00000000000 --- a/boards/riscv/adp_xc7k_ae350/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2021 Andes Technology Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adp_xc7k_ae350" if BOARD_ADP_XC7K_AE350 diff --git a/boards/riscv/adp_xc7k_ae350/doc/index.rst b/boards/riscv/adp_xc7k_ae350/doc/index.rst deleted file mode 100644 index c12c04cabc4..00000000000 --- a/boards/riscv/adp_xc7k_ae350/doc/index.rst +++ /dev/null @@ -1,334 +0,0 @@ -.. _adp_xc7k_ae350: - -Andes ADP-XC7K AE350 -#################### - -Overview -******** - -ADP-XC7K AE350 board is for AndeShape AE350 platform on ADP-XC7K series -FPGA-based development boards. - -ADP-XC7K series are FPGA-based development and prototyping boards for evaluation of -variety of AndesCore processors and AndeShape SoC platform IPs. -AE350 is a RISC-V platform which can integrate AndesCore CPUs with a collection -of fundamental peripheral IPs. - -1st figure shows the green PCB is ADP-XC7K160 and 2nd figure shows the red PCB is ADP-XC7K410. - -.. image:: img/adp_xc7k160.jpg - :align: center - :alt: ADP-XC7K160 - -.. image:: img/adp_xc7k410.jpg - :align: center - :alt: ADP-XC7K410 - -More information can be found on `ADP-XC7K160/410`_ and `AndeShape AE350`_ websites. - -Hardware -******** - -The ADP-XC7K AE350 platform integrates 1 ~ 4 cores 32/64-bit 60MHz RISC-V CPUs, DSP, -1GB RAM, Cache, SPI flash memory, ethernet controller and other peripherals. - -The ADP-XC7K AE350 platform provides following hardware components: - -- 1 ~ 4 cores 32/64-bit 60MHz AndeStar v5 RISC-V CPUs -- 1GB on-board SDRAM -- 2MB SPI flash memory (1MB can be used for XIP) -- UART -- I2C -- SPI -- GPIO -- PWM -- DMA -- 10/100 Ethernet RJ45 port -- LCD module connector -- 16KB I2C EEPROM -- SD memory card slot -- MIC-in, Line-in, and Line-out with AC97 audio codec - -Supported Features -================== - -The ``adp_xc7k_ae350`` board configuration supports the following hardware features: - -+----------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+================+============+======================+ -| PLIC | on-chip | interrupt_controller | -+----------------+------------+----------------------+ -| RISC-V Machine | on-chip | timer | -| Timer | | | -+----------------+------------+----------------------+ -| GPIO | on-chip | gpio | -+----------------+------------+----------------------+ -| UART | on-chip | serial | -+----------------+------------+----------------------+ -| COUNTER | on-chip | counter | -+----------------+------------+----------------------+ -| SPI | on-chip | spi | -+----------------+------------+----------------------+ -| I2C | on-chip | i2c | -+----------------+------------+----------------------+ -| EEPROM | on-chip | eeprom | -+----------------+------------+----------------------+ -| FLASH | on-chip | flash | -+----------------+------------+----------------------+ -| HWINFO | on-chip | syscon | -+----------------+------------+----------------------+ -| MAILBOX | on-chip | mbox | -+----------------+------------+----------------------+ -| DMA | on-chip | dma | -+----------------+------------+----------------------+ -| WATCHDOG | on-chip | wdt | -+----------------+------------+----------------------+ - -Other hardware features are not supported yet. - -Connections and IOs -=================== - -The ADP-XC7K AE350 platform has 1 GPIO controller. It providing 32 bits of IO. -It is responsible for pin input/output, pull-up, etc. - -Mapping from GPIO controller to the ADP-XC7K board pins: - -+--------------------+--------------------+ -| GPIO controller | Usage / Board pins | -+====================+====================+ -| **Push Buttons** | | -+--------------------+--------------------+ -| GPIO.0 | SW1 | -+--------------------+--------------------+ -| GPIO.1 | SW2 | -+--------------------+--------------------+ -| GPIO.2 | SW3 | -+--------------------+--------------------+ -| GPIO.3 | SW4 | -+--------------------+--------------------+ -| GPIO.4 | SW5 | -+--------------------+--------------------+ -| GPIO.5 | SW6 | -+--------------------+--------------------+ -| GPIO.6 | SW7 | -+--------------------+--------------------+ -| **7-Segment LED1** | | -+--------------------+--------------------+ -| GPIO.16 | 7SEG1.A | -+--------------------+--------------------+ -| GPIO.17 | 7SEG1.B | -+--------------------+--------------------+ -| GPIO.18 | 7SEG1.C | -+--------------------+--------------------+ -| GPIO.19 | 7SEG1.D | -+--------------------+--------------------+ -| GPIO.20 | 7SEG1.E | -+--------------------+--------------------+ -| GPIO.21 | 7SEG1.F | -+--------------------+--------------------+ -| GPIO.22 | 7SEG1.G | -+--------------------+--------------------+ -| GPIO.23 | 7SEG1.DP | -+--------------------+--------------------+ -| **7-Segment LED2** | | -+--------------------+--------------------+ -| GPIO.24 | 7SEG2.A | -+--------------------+--------------------+ -| GPIO.25 | 7SEG2.B | -+--------------------+--------------------+ -| GPIO.26 | 7SEG2.C | -+--------------------+--------------------+ -| GPIO.27 | 7SEG2.D | -+--------------------+--------------------+ -| GPIO.28 | 7SEG2.E | -+--------------------+--------------------+ -| GPIO.29 | 7SEG2.F | -+--------------------+--------------------+ -| GPIO.30 | 7SEG2.G | -+--------------------+--------------------+ -| GPIO.31 | 7SEG2.DP | -+--------------------+--------------------+ -| **GPIO pins** | | -+--------------------+--------------------+ -| GPIO.7 | IDE_CON1.4 | -+--------------------+--------------------+ -| GPIO.8 | IDE_CON1.6 | -+--------------------+--------------------+ -| GPIO.9 | IDE_CON1.8 | -+--------------------+--------------------+ -| GPIO.10 | IDE_CON1.10 | -+--------------------+--------------------+ -| GPIO.11 | IDE_CON1.11 | -+--------------------+--------------------+ -| GPIO.12 | IDE_CON1.12 | -+--------------------+--------------------+ -| GPIO.13 | IDE_CON1.13 | -+--------------------+--------------------+ -| GPIO.14 | IDE_CON1.14 | -+--------------------+--------------------+ -| GPIO.15 | IDE_CON1.15 | -+--------------------+--------------------+ - -Other peripheral mapping are listed below: - -+-------------+---------------------------------+ -| Peripherals | Usage / Board pins | -+=============+=================================+ -| SPI_1 | internal connected to SPI Flash | -+-------------+---------------------------------+ -| SPI_2_CS | IDE_CON1.37 | -+-------------+---------------------------------+ -| SPI_2_MOSI | IDE_CON1.36 | -+-------------+---------------------------------+ -| SPI_2_MISO | IDE_CON1.38 | -+-------------+---------------------------------+ -| SPI_2_SCLK | IDE_CON1.35 | -+-------------+---------------------------------+ -| I2C_SDA | J27.1 | -+-------------+---------------------------------+ -| I2C_SCL | J27.2 | -+-------------+---------------------------------+ - -System Clock ------------- - -The ADP-XC7K AE350 platform has 60MHz core clock. - -Serial Port ------------ - -The ADP-XC7K AE350 platform has 2 UARTs. -The Zephyr console output is by default assigned to UART2 and the default -settings are 115200 8N1. - -Programming and debugging -************************* - -For debugging zephyr applications or burning them into a flash, you will need to -connect Andes ICE from host computer to ADP-XC7K board and execute the -Andes ICE management software, ICEman, on this host computer. - -Connecting Andes ICE (AICE) -=========================== - -AICE is used for flashing and debugging the board. Please connect AICE to both -ADP-XC7K board and the host computer as shown in the figure. - -.. image:: img/connect_aice.jpg - :align: center - :alt: Connect AICE - -More information can be found on `AICE-MINI+`_, `AICE-MICRO`_ website - -Building -======== - -You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adp_xc7k_ae350 - :goals: build - -Flashing -======== - -Before flashing, you have to download ICEman (``ice.zip``) from the -`Andes Development Kit`_. -If you want to use XIP mode (``CONFIG_XIP=y``), you also need to download -the flash burner (``flash.zip``). - -At first, you should run ICEman when flashing and debugging program. - -.. code-block:: console - - # Enable execute file permission of ICEman - chmod a+x ./ICEman - - # Running the ICEman server - sudo ./ICEman -Z v5 - -.. note:: - - To run ICEman commands as a normal user, you will need to install the - :file:`70-ndsusb-v1.rules` udev rules file (usually by placing it in - :file:`/etc/udev/rules.d`, then unplugging and plugging the - AICE adapter in again via USB.). - -If ``CONFIG_XIP=n``, you can load the program (``zephyr.elf``) into RAM directly -and execute it. - -.. code-block:: console - - # Check the ICEman server is running - # Load the program into RAM and execute it - riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf - (gdb) target remote :1111 - (gdb) monitor reset halt - (gdb) load - (gdb) quit - -If ``CONFIG_XIP=y``, you need to burn the program (``zephyr.bin``) into flash memory -and execute it. - -.. code-block:: console - - # Check the ICEman server is running - # Burn the program into flash and execute it - /bin/target_burn_frontend \ - -P 4444 --unlock --verify --image=build/zephyr/zephyr.bin \ - --algorithm-bin=/target_bin/target_SPI_v5_[32|64].bin - - # Note: - # 1. Assume the flash burner is downloaded to directory - # 2. For algorithm-bin file, use target_SPI_v5_32.bin in RV32 platform and - # use target_SPI_v5_64.bin in RV64 platform - -Open a serial terminal with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -you should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.4.0 ***** - Hello World! adp_xc7k_ae350 - -Debugging -========= - -.. code-block:: console - - # Check the ICEman server is running - # Load and debug program - ./riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf - (gdb) target remote :1111 - (gdb) monitor reset halt - (gdb) load - -If ``CONFIG_XIP=y``, please follow the flashing section to burn the program into -flash memory first. -Then, you can use GDB to debug program by above commands but do NOT execute ``load`` -command since the program has been placed in the flash memory. - -References -********** - -.. target-notes:: - -.. _ADP-XC7K160/410: http://www.andestech.com/en/products-solutions/andeshape-platforms/adp-xc7k160-410/ - -.. _AndeShape AE350: http://www.andestech.com/en/products-solutions/andeshape-platforms/ae350-axi-based-platform-pre-integrated-with-n25f-nx25f-a25-ax25/ - -.. _AICE-MINI+: http://www.andestech.com/en/products-solutions/andeshape-platforms/aice-mini-plus/ - -.. _AICE-MICRO: http://www.andestech.com/en/products-solutions/andeshape-platforms/aice-micro/ - -.. _Andes Development Kit: https://github.com/andestech/Andes-Development-Kit/releases diff --git a/boards/riscv/beaglev_fire/Kconfig.board b/boards/riscv/beaglev_fire/Kconfig.board deleted file mode 100644 index 55b59d4ac92..00000000000 --- a/boards/riscv/beaglev_fire/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BEAGLEV_FIRE - bool "Beagleboard BeagleV-Fire" - depends on SOC_POLARFIRE - select 64BIT - select SCHED_IPI_SUPPORTED - select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/riscv/beaglev_fire/Kconfig.defconfig b/boards/riscv/beaglev_fire/Kconfig.defconfig deleted file mode 100644 index df89660bcb6..00000000000 --- a/boards/riscv/beaglev_fire/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "beaglev_fire" - depends on BOARD_BEAGLEV_FIRE diff --git a/boards/riscv/esp32c3_devkitm/Kconfig.board b/boards/riscv/esp32c3_devkitm/Kconfig.board deleted file mode 100644 index 51f0f3957df..00000000000 --- a/boards/riscv/esp32c3_devkitm/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32C3 devkitm board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32C3_DEVKITM - bool "ESP32C3 Devkit-M Board" - depends on SOC_SERIES_ESP32C3 - -choice SOC_PART_NUMBER - default SOC_ESP32C3_MINI_N4 -endchoice diff --git a/boards/riscv/esp32c3_devkitm/Kconfig.defconfig b/boards/riscv/esp32c3_devkitm/Kconfig.defconfig deleted file mode 100644 index 922368f923b..00000000000 --- a/boards/riscv/esp32c3_devkitm/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# ESP32C3 devkitm board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32c3_devkitm" - depends on BOARD_ESP32C3_DEVKITM - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/riscv/esp32c3_devkitm/doc/index.rst b/boards/riscv/esp32c3_devkitm/doc/index.rst deleted file mode 100644 index 26f1521e087..00000000000 --- a/boards/riscv/esp32c3_devkitm/doc/index.rst +++ /dev/null @@ -1,241 +0,0 @@ -.. _esp32c3_devkitm: - -ESP32-C3 -######## - -Overview -******** - -ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, -based on the open-source RISC-V architecture. It strikes the right balance of power, -I/O capabilities and security, thus offering the optimal cost-effective -solution for connected devices. -The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy, -but it also facilitates a variety of use-cases based on dual connectivity. [1]_ - -The features include the following: - -- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz -- 400 KB of internal RAM -- 802.11b/g/n/e/i -- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh -- Various peripherals: - - - 12-bit ADC with up to 6 channels - - TWAI compatible with CAN bus 2.0 - - Temperature sensor - - 3x SPI - - 1x I2S - - 1x I2C - - 2x UART - - LED PWM with up to 6 channels - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) - -Supported Features -================== - -Current Zephyr's ESP32-C3-Devkitm board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32c3_devkitm - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_devkitm - :goals: build - -The usual ``flash`` target will work with the ``esp32c3_devkitm`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_devkitm - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32c3_devkitm - -Debugging -********* - -As with much custom hardware, the ESP32-C3 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_devkitm - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_devkitm - :goals: debug - -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases - -References -********** - -.. [1] https://www.espressif.com/en/products/socs/esp32-c3 -.. _ESP32C3 Devkitm User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/hw-reference/esp32c3/user-guide-devkitm-1.html -.. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf -.. _ESP32C3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig deleted file mode 100644 index 1ca521d9d95..00000000000 --- a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32C3_DEVKITM=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/riscv/esp32c3_luatos_core/Kconfig.board b/boards/riscv/esp32c3_luatos_core/Kconfig.board deleted file mode 100644 index ac7b48a7a36..00000000000 --- a/boards/riscv/esp32c3_luatos_core/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32C3_LUATOS_CORE - bool "luatos ESP32C3-CORE Board" - depends on SOC_SERIES_ESP32C3 - -config BOARD_ESP32C3_LUATOS_CORE_USB - bool "luatos ESP32C3-CORE Board without UART chip" - depends on SOC_SERIES_ESP32C3 - -choice SOC_PART_NUMBER - default SOC_ESP32C3_MINI_N4 -endchoice diff --git a/boards/riscv/esp32c3_luatos_core/Kconfig.defconfig b/boards/riscv/esp32c3_luatos_core/Kconfig.defconfig deleted file mode 100644 index 82e3a5a0c94..00000000000 --- a/boards/riscv/esp32c3_luatos_core/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# ESP32C3 core board configuration - -# Copyright (c) 2023 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32c3_luatos_core" - depends on BOARD_ESP32C3_LUATOS_CORE || BOARD_ESP32C3_LUATOS_CORE_USB - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/riscv/esp32c3_luatos_core/doc/index.rst b/boards/riscv/esp32c3_luatos_core/doc/index.rst deleted file mode 100644 index fae8e2eb178..00000000000 --- a/boards/riscv/esp32c3_luatos_core/doc/index.rst +++ /dev/null @@ -1,259 +0,0 @@ -.. _esp32c3_luatos_core: - -ESP32C3_LUATOS_CORE -################### - -Overview -******** - -ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, -based on the open-source RISC-V architecture. It strikes the right balance of power, -I/O capabilities and security, thus offering the optimal cost-effective -solution for connected devices. -The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy, -but it also facilitates a variety of use-cases based on dual connectivity. [1]_ - -The features include the following: - -- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz -- 400 KB of internal RAM -- 802.11b/g/n/e/i -- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh -- Various peripherals: - - - 12-bit ADC with up to 6 channels - - TWAI compatible with CAN bus 2.0 - - Temperature sensor - - 3x SPI - - 1x I2S - - 1x I2C - - 2x UART - - LED PWM with up to 6 channels - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) - -There are two version hardware of this board. The difference between them is the ch343 chip. - -1. USB-C connect to UART over CH343 chip(esp32c3_luatos_core) - -.. image:: img/esp32c3_luatos_core.jpg - :align: center - :alt: esp32c3_luatos_core - -2. USB-C connect to esp32 chip directly(esp32c3_luatos_core_usb) - -.. image:: img/esp32c3_luatos_core_usb.jpg - :align: center - :alt: esp32c3_luatos_core_usb - -Supported Features -================== - -Current Zephyr's ESP32C3_LUATOS_CORE board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -.. image:: img/esp32c3_luatos_core_pinfunc.jpg - :align: center - :alt: esp32c3_luatos_core_pinfunc - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32c3_luatos_core - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_luatos_core - :goals: build - -The usual ``flash`` target will work with the ``esp32c3_luatos_core`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_luatos_core - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32c3_luatos_core - -Debugging -********* - -As with much custom hardware, the ESP32-C3 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_luatos_core - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_luatos_core - :goals: debug - -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases - -References -********** - -.. [1] https://www.espressif.com/en/products/socs/esp32-c3 -.. _ESP32C3 Core Website: https://wiki.luatos.com/chips/esp32c3/board.html -.. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf -.. _ESP32C3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_defconfig b/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_defconfig deleted file mode 100644 index d3f8458a2ef..00000000000 --- a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32C3_LUATOS_CORE=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb.yaml b/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb.yaml deleted file mode 100644 index ed8f1b2bc0a..00000000000 --- a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: esp32c3_luatos_core_usb -name: ESP32C3 LuatOS Core USB -type: mcu -arch: riscv -toolchain: - - zephyr -supported: - - adc - - gpio - - i2c - - watchdog - - uart - - dma - - pwm - - spi - - counter - - entropy -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb_defconfig b/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb_defconfig deleted file mode 100644 index 0a441dde0bb..00000000000 --- a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32C3_LUATOS_CORE_USB=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/riscv/gd32vf103c_starter/Kconfig.board b/boards/riscv/gd32vf103c_starter/Kconfig.board deleted file mode 100644 index 747958bef1a..00000000000 --- a/boards/riscv/gd32vf103c_starter/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32VF103C_STARTER - bool "GigaDevice GD32VF103C-STARTER" - depends on SOC_GD32VF103 diff --git a/boards/riscv/gd32vf103c_starter/Kconfig.defconfig b/boards/riscv/gd32vf103c_starter/Kconfig.defconfig deleted file mode 100644 index 09c16cab055..00000000000 --- a/boards/riscv/gd32vf103c_starter/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32VF103C_STARTER - -config BOARD - default "gd32vf103c_starter" - -endif # BOARD_GD32VF103C_STARTER diff --git a/boards/riscv/gd32vf103c_starter/gd32vf103c_starter_defconfig b/boards/riscv/gd32vf103c_starter/gd32vf103c_starter_defconfig deleted file mode 100644 index 056959e18fb..00000000000 --- a/boards/riscv/gd32vf103c_starter/gd32vf103c_starter_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32VF103=y -CONFIG_SOC_GD32VF103=y -CONFIG_BOARD_GD32VF103C_STARTER=y - -CONFIG_GD32_HXTAL_8MHZ=y diff --git a/boards/riscv/gd32vf103v_eval/Kconfig.board b/boards/riscv/gd32vf103v_eval/Kconfig.board deleted file mode 100644 index 1893adae071..00000000000 --- a/boards/riscv/gd32vf103v_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32VF103V_EVAL - bool "GigaDevice GD32VF103V-EVAL" - depends on SOC_GD32VF103 diff --git a/boards/riscv/gd32vf103v_eval/Kconfig.defconfig b/boards/riscv/gd32vf103v_eval/Kconfig.defconfig deleted file mode 100644 index e3c8b4150f7..00000000000 --- a/boards/riscv/gd32vf103v_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32VF103V_EVAL - -config BOARD - default "gd32vf103v_eval" - -endif # BOARD_GD32VF103V_EVAL diff --git a/boards/riscv/gd32vf103v_eval/gd32vf103v_eval_defconfig b/boards/riscv/gd32vf103v_eval/gd32vf103v_eval_defconfig deleted file mode 100644 index 078392eed2a..00000000000 --- a/boards/riscv/gd32vf103v_eval/gd32vf103v_eval_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32VF103=y -CONFIG_SOC_GD32VF103=y -CONFIG_BOARD_GD32VF103V_EVAL=y - -CONFIG_GD32_HXTAL_8MHZ=y - -CONFIG_GPIO=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/riscv/hifive1/Kconfig.board b/boards/riscv/hifive1/Kconfig.board deleted file mode 100644 index d2f40472f24..00000000000 --- a/boards/riscv/hifive1/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HIFIVE1 - bool "HiFive1 target" - depends on SOC_SIFIVE_FREEDOM_E340 diff --git a/boards/riscv/hifive1/Kconfig.defconfig b/boards/riscv/hifive1/Kconfig.defconfig deleted file mode 100644 index 33356cb4da7..00000000000 --- a/boards/riscv/hifive1/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HIFIVE1 - -config BOARD - default "hifive1" - -config SYS_CLOCK_TICKS_PER_SEC - default 128 - -endif diff --git a/boards/riscv/hifive1/board.cmake b/boards/riscv/hifive1/board.cmake deleted file mode 100644 index 8d5f8476145..00000000000 --- a/boards/riscv/hifive1/board.cmake +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS renode qemu) -set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/hifive1.resc) -set(RENODE_UART sysbus.uart0) - -set(QEMU_binary_suffix riscv32) -set(QEMU_CPU_TYPE_${ARCH} riscv32) - -set(QEMU_FLAGS_${ARCH} - -nographic - -machine sifive_e - ) - -board_set_flasher_ifnset(hifive1) -board_finalize_runner_args(hifive1) - -board_runner_args(openocd --cmd-load "hifive1-load") -board_runner_args(openocd --cmd-reset-halt "hifive1-reset-halt") -board_runner_args(openocd --cmd-post-verify "hifive1-post-verify") - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/riscv/hifive1/doc/index.rst b/boards/riscv/hifive1/doc/index.rst deleted file mode 100644 index 9482a6ad0d4..00000000000 --- a/boards/riscv/hifive1/doc/index.rst +++ /dev/null @@ -1,62 +0,0 @@ -.. _hifive1: - -SiFive HiFive1 -############## - -Overview -******** - -The HiFive1 is an Arduino-compatible development board with -an FE310 RISC-V SoC. -More information can be found on -`SiFive's website `_. - -.. image:: img/hifive1.jpg - :align: center - :alt: SiFive HiFive1 board - -Programming and debugging -************************* - -Building -======== - -Applications for the ``hifive1`` board configuration can be built as usual -(see :ref:`build_an_application`) using the corresponding board name: - -.. zephyr-app-commands:: - :board: hifive1 - :goals: build - -Flashing -======== - -In order to upload the application to the device, you'll need OpenOCD with -RISC-V support. Download the tarball for your OS from the `SiFive website -`_ and extract it. - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can -overwrite that behavior by adding the -``-DOPENOCD=`` parameter when building: - -.. zephyr-app-commands:: - :board: hifive1 - :goals: build - :gen-args: -DOPENOCD= - -When using a custom toolchain it should be enough to have the downloaded -version of the binary in your ``PATH``. - -Now you can flash the application as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details): - -.. code-block:: console - - ninja flash - -Depending on your OS you might have to run the flash command as superuser. - -Debugging -========= - -Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/riscv/hifive1/hifive1_defconfig b/boards/riscv/hifive1/hifive1_defconfig deleted file mode 100644 index 8e4e8e21c1a..00000000000 --- a/boards/riscv/hifive1/hifive1_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_E300=y -CONFIG_SOC_SIFIVE_FREEDOM_E340=y -CONFIG_BOARD_HIFIVE1=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_PINCTRL=y -CONFIG_GPIO=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/riscv/hifive1_revb/Kconfig.board b/boards/riscv/hifive1_revb/Kconfig.board deleted file mode 100644 index b0bf1edd156..00000000000 --- a/boards/riscv/hifive1_revb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 SiFive Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HIFIVE1_REVB - bool "HiFive1 Rev B target" - depends on SOC_SIFIVE_FREEDOM_E340 diff --git a/boards/riscv/hifive1_revb/Kconfig.defconfig b/boards/riscv/hifive1_revb/Kconfig.defconfig deleted file mode 100644 index 22b33b3d960..00000000000 --- a/boards/riscv/hifive1_revb/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2019 SiFive Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HIFIVE1_REVB - -config BOARD - default "hifive1_revb" - -config HAS_FLASH_LOAD_OFFSET - default y - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/spi@10014000,1) - -config FLASH_LOAD_OFFSET - default 0x0 - -config SYS_CLOCK_TICKS_PER_SEC - default 128 - -endif diff --git a/boards/riscv/hifive1_revb/board.cmake b/boards/riscv/hifive1_revb/board.cmake deleted file mode 100644 index f339e968e86..00000000000 --- a/boards/riscv/hifive1_revb/board.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2019 SiFive Inc. -# SPDX-License-Identifier: Apache-2.0 -board_runner_args(jlink "--device=FE310") -board_runner_args(jlink "--iface=JTAG") -board_runner_args(jlink "--speed=4000") -board_runner_args(jlink "--tool-opt=-jtagconf -1,-1") -board_runner_args(jlink "--tool-opt=-autoconnect 1") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/riscv/hifive1_revb/doc/index.rst b/boards/riscv/hifive1_revb/doc/index.rst deleted file mode 100644 index 843192fe2cc..00000000000 --- a/boards/riscv/hifive1_revb/doc/index.rst +++ /dev/null @@ -1,49 +0,0 @@ -.. _hifive1_revb: - -SiFive HiFive1 Rev B -#################### - -Overview -******** - -The HiFive1 Rev B is an Arduino-compatible development board with -a SiFive FE310-G002 RISC-V SoC. - -.. image:: img/hifive1_revb.jpg - :align: center - :alt: SiFive HiFive1 Rev B board - -Programming and debugging -************************* - -Building -======== - -Applications for the ``hifive1_revb`` board configuration can be built as usual -(see :ref:`build_an_application`) using the corresponding board name: - -.. zephyr-app-commands:: - :board: hifive1_revb - :goals: build - -Flashing -======== - -The HiFive 1 Rev B uses Segger J-Link OB for flashing and debugging. To flash and -debug the board, you'll need to install the -`Segger J-Link Software and Documentation Pack -`_ -and choose version V6.46a or later (Downloads for Windows, Linux, and macOS are -available). - -With the Segger J-Link Software installed, you can flash the application as usual -(see :ref:`build_an_application` and :ref:`application_run` for more details): - -.. code-block:: console - - west flash - -Debugging -========= - -Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/riscv/hifive1_revb/hifive1_revb-pinctrl.dtsi b/boards/riscv/hifive1_revb/hifive1_revb-pinctrl.dtsi deleted file mode 100644 index 093cdcb6a41..00000000000 --- a/boards/riscv/hifive1_revb/hifive1_revb-pinctrl.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2022 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&pinctrl { - /* UART0 */ - uart0_rx_default: uart0_rx_default { - pinmux = <16 SIFIVE_PINMUX_IOF0>; - }; - uart0_tx_default: uart0_tx_default { - pinmux = <17 SIFIVE_PINMUX_IOF0>; - }; - - /* SPI1 */ - spi1_cs0_default: spi1_cs0_default { - pinmux = <2 SIFIVE_PINMUX_IOF0>; - }; - spi1_mosi_default: spi1_mosi_default { - pinmux = <3 SIFIVE_PINMUX_IOF0>; - }; - spi1_miso_default: spi1_miso_default { - pinmux = <4 SIFIVE_PINMUX_IOF0>; - }; - spi1_sck_default: spi1_sck_default { - pinmux = <5 SIFIVE_PINMUX_IOF0>; - }; - spi1_cs2_default: spi1_cs2_default { - pinmux = <9 SIFIVE_PINMUX_IOF0>; - }; - spi1_cs3_default: spi1_cs3_default { - pinmux = <10 SIFIVE_PINMUX_IOF0>; - }; - - /* PWM0 */ - pwm0_0_default: pwm0_0_default { - pinmux = <0 SIFIVE_PINMUX_IOF1>; - }; - pwm0_1_default: pwm0_1_default { - pinmux = <1 SIFIVE_PINMUX_IOF1>; - }; - pwm0_2_default: pwm0_2_default { - pinmux = <2 SIFIVE_PINMUX_IOF1>; - }; - pwm0_3_default: pwm0_3_default { - pinmux = <3 SIFIVE_PINMUX_IOF1>; - }; - - /* PWM1 */ - pwm1_0_default: pwm1_0_default { - pinmux = <20 SIFIVE_PINMUX_IOF1>; - }; - pwm1_1_default: pwm1_1_default { - pinmux = <19 SIFIVE_PINMUX_IOF1>; - }; - pwm1_2_default: pwm1_2_default { - pinmux = <21 SIFIVE_PINMUX_IOF1>; - }; - pwm1_3_default: pwm1_3_default { - pinmux = <22 SIFIVE_PINMUX_IOF1>; - }; - - /* PWM2 */ - pwm2_0_default: pwm2_0_default { - pinmux = <10 SIFIVE_PINMUX_IOF1>; - }; - pwm2_1_default: pwm2_1_default { - pinmux = <11 SIFIVE_PINMUX_IOF1>; - }; - pwm2_2_default: pwm2_2_default { - pinmux = <12 SIFIVE_PINMUX_IOF1>; - }; - pwm2_3_default: pwm2_3_default { - pinmux = <13 SIFIVE_PINMUX_IOF1>; - }; - - /* I2C0 */ - i2c0_0_default: i2c0_0_default { - pinmux = <12 SIFIVE_PINMUX_IOF0>; - }; - i2c0_1_default: i2c0_1_default { - pinmux = <13 SIFIVE_PINMUX_IOF0>; - }; -}; diff --git a/boards/riscv/hifive1_revb/hifive1_revb.dts b/boards/riscv/hifive1_revb/hifive1_revb.dts deleted file mode 100644 index f01711d8c59..00000000000 --- a/boards/riscv/hifive1_revb/hifive1_revb.dts +++ /dev/null @@ -1,143 +0,0 @@ -/* Copyright (c) 2019 SiFive, Inc. */ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include -#include -#include "hifive1_revb-pinctrl.dtsi" - -/ { - model = "SiFive HiFive 1 Rev B"; - compatible = "sifive,hifive1-revb"; - - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - watchdog0 = &wdog0; - }; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &dtim; - zephyr,flash = &flash0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; - label = "Green LED"; - }; - led1: led_1 { - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - label = "Blue LED"; - }; - led2: led_2 { - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - label = "Red LED"; - }; - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = /* A0 not connected */ - <1 0 &gpio0 9 0>, /* A1, also CS2 */ - <2 0 &gpio0 10 0>, /* A2, also WF_INT */ - <3 0 &gpio0 11 0>, /* A3 */ - <4 0 &gpio0 12 0>, /* A4 */ - <5 0 &gpio0 13 0>, /* A5 */ - <6 0 &gpio0 16 0>, /* D0, also TX */ - <7 0 &gpio0 17 0>, /* D1, also RX */ - <8 0 &gpio0 18 0>, /* D2 */ - <9 0 &gpio0 19 0>, /* D3 */ - <10 0 &gpio0 20 0>, /* D4 */ - <11 0 &gpio0 21 0>, /* D5 */ - <12 0 &gpio0 22 0>, /* D6 */ - <13 0 &gpio0 23 0>, /* D7 */ - <14 0 &gpio0 0 0>, /* D8 */ - <15 0 &gpio0 1 0>, /* D9 */ - <16 0 &gpio0 2 0>, /* D10 */ - <17 0 &gpio0 3 0>, /* D11, also MOSI */ - <18 0 &gpio0 4 0>, /* D12, also MISO */ - <19 0 &gpio0 5 0>, /* D13, also SCK */ - <20 0 &gpio0 12 0>, /* D14, also SDA */ - <21 0 &gpio0 13 0>; /* D15, also SCL */ - }; -}; - -&coreclk { - clock-frequency = ; - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; - pinctrl-names = "default"; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; -}; - -/* disabled (used by Flash ROM by default) */ -&spi0 { - reg = <0x10014000 0x1000 0x20010000 0x3c0900>; - flash0: flash@0 { - compatible = "issi,is25lp128", "jedec,spi-nor"; - status = "disabled"; - size = <134217728>; - jedec-id = [96 60 18]; - reg = <0>; - spi-max-frequency = <133000000>; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&spi1_cs0_default - &spi1_mosi_default - &spi1_miso_default - &spi1_sck_default>; - pinctrl-names = "default"; -}; - -&spi2 { - status = "okay"; - pinctrl-0 = <&spi1_cs2_default - &spi1_mosi_default - &spi1_miso_default - &spi1_sck_default>; - pinctrl-names = "default"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -arduino_i2c: &i2c0 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c0_0_default &i2c0_1_default>; - pinctrl-names = "default"; -}; diff --git a/boards/riscv/hifive1_revb/hifive1_revb.yaml b/boards/riscv/hifive1_revb/hifive1_revb.yaml deleted file mode 100644 index 5a44018354c..00000000000 --- a/boards/riscv/hifive1_revb/hifive1_revb.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: hifive1_revb -name: SiFive HiFive1 Rev B -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 16 -testing: - ignore_tags: - - net - - bluetooth -supported: - - arduino_gpio - - arduino_i2c - - gpio - - i2c -vendor: sifive diff --git a/boards/riscv/hifive1_revb/hifive1_revb_defconfig b/boards/riscv/hifive1_revb/hifive1_revb_defconfig deleted file mode 100644 index b2119eecae9..00000000000 --- a/boards/riscv/hifive1_revb/hifive1_revb_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_E300=y -CONFIG_SOC_SIFIVE_FREEDOM_E340=y -CONFIG_BOARD_HIFIVE1_REVB=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_RISCV_CORE_E31=y diff --git a/boards/riscv/hifive_unleashed/Kconfig.board b/boards/riscv/hifive_unleashed/Kconfig.board deleted file mode 100644 index f6c623e9928..00000000000 --- a/boards/riscv/hifive_unleashed/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Katsuhiro Suzuki -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HIFIVE_UNLEASHED - bool "HiFive Unleashed target" - depends on SOC_SIFIVE_FREEDOM_U540 diff --git a/boards/riscv/hifive_unleashed/Kconfig.defconfig b/boards/riscv/hifive_unleashed/Kconfig.defconfig deleted file mode 100644 index 213aab0aab9..00000000000 --- a/boards/riscv/hifive_unleashed/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Katsuhiro Suzuki -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HIFIVE_UNLEASHED - -config BOARD - default "hifive_unleashed" - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -endif diff --git a/boards/riscv/hifive_unleashed/hifive_unleashed_defconfig b/boards/riscv/hifive_unleashed/hifive_unleashed_defconfig deleted file mode 100644 index 51d324d457d..00000000000 --- a/boards/riscv/hifive_unleashed/hifive_unleashed_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_U500=y -CONFIG_SOC_SIFIVE_FREEDOM_U540=y -CONFIG_BOARD_HIFIVE_UNLEASHED=y -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_XIP=n diff --git a/boards/riscv/hifive_unmatched/Kconfig.board b/boards/riscv/hifive_unmatched/Kconfig.board deleted file mode 100644 index bb303cc3aac..00000000000 --- a/boards/riscv/hifive_unmatched/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Katsuhiro Suzuki -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HIFIVE_UNMATCHED - bool "HiFive Unmatched target" - depends on SOC_SIFIVE_FREEDOM_U740 diff --git a/boards/riscv/hifive_unmatched/Kconfig.defconfig b/boards/riscv/hifive_unmatched/Kconfig.defconfig deleted file mode 100644 index ee38da1c579..00000000000 --- a/boards/riscv/hifive_unmatched/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Katsuhiro Suzuki -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HIFIVE_UNMATCHED - -config BOARD - default "hifive_unmatched" - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -endif diff --git a/boards/riscv/hifive_unmatched/hifive_unmatched_defconfig b/boards/riscv/hifive_unmatched/hifive_unmatched_defconfig deleted file mode 100644 index be13ed10358..00000000000 --- a/boards/riscv/hifive_unmatched/hifive_unmatched_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_U700=y -CONFIG_SOC_SIFIVE_FREEDOM_U740=y -CONFIG_BOARD_HIFIVE_UNMATCHED=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_XIP=n diff --git a/boards/riscv/icev_wireless/Kconfig.board b/boards/riscv/icev_wireless/Kconfig.board deleted file mode 100644 index 21e7a72815e..00000000000 --- a/boards/riscv/icev_wireless/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Friedt Professional Engineering Services, Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ICEV_WIRELESS - bool "ICE-V Wireless Board" - depends on SOC_ESP32C3 diff --git a/boards/riscv/icev_wireless/Kconfig.defconfig b/boards/riscv/icev_wireless/Kconfig.defconfig deleted file mode 100644 index 44157fd5b6a..00000000000 --- a/boards/riscv/icev_wireless/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2022 Friedt Professional Engineering Services, Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "icev_wireless" - depends on BOARD_ICEV_WIRELESS - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/riscv/icev_wireless/doc/index.rst b/boards/riscv/icev_wireless/doc/index.rst deleted file mode 100644 index a3ae804c668..00000000000 --- a/boards/riscv/icev_wireless/doc/index.rst +++ /dev/null @@ -1,259 +0,0 @@ -.. _icev_wireless: - -ICE-V Wireless -############## - -Overview -******** - -The ICE-V Wireless is a combined ESP32C3 and iCE40 FPGA board. - -See the `ICE-V Wireless Github Project`_ for details. - -.. figure:: img/icev_wireless.jpg - :align: center - :alt: ICE-V Wireless - - ICE-V Wireless - -Hardware -******** - -This board combines an Espressif ESP32-C3-MINI-1 (which includes 4MB of flash in the module) with a -Lattice iCE40UP5k-SG48 FPGA to allow WiFi and Bluetooth control of the FPGA. ESP32 and FPGA I/O is -mostly uncommitted except for the pins used for SPI communication between ESP32 and FPGA. Several -of the ESP32C3 GPIO pins are available for additonal interfaces such as serial, ADC, I2C, etc. - -For details on ESP32-C3 hardware please refer to the following resources: - -* `ESP32-C3-MINI-1 Datasheet`_ -* `ESP32-C3 Datasheet`_ -* `ESP32-C3 Technical Reference Manual`_ - -For details on iCE40 hardware please refer to the following resources: - -* `iCE40 UltraPlus Family Datasheet`_ - -Supported Features -================== - -The ICE-V Wireless board configuration supports the following hardware -features: - -+-----------+------------+------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==================+ -| PMP | on-chip | arch/riscv | -+-----------+------------+------------------+ -| INTMTRX | on-chip | intc_esp32c3 | -+-----------+------------+------------------+ -| PINMUX | on-chip | pinctrl_esp32 | -+-----------+------------+------------------+ -| USB UART | on-chip | serial_esp32_usb | -+-----------+------------+------------------+ -| GPIO | on-chip | gpio_esp32 | -+-----------+------------+------------------+ -| UART | on-chip | uart_esp32 | -+-----------+------------+------------------+ -| I2C | on-chip | i2c_esp32 | -+-----------+------------+------------------+ -| SPI | on-chip | spi_esp32_spim | -+-----------+------------+------------------+ -| ADC | on-chip | | -+-----------+------------+------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -The ICE-V Wireless provides 1 row of reference, ESP32-C3, and iCE40 signals -brought out to J3, as well as 3 PMOD connectors for interfacing directly to -the iCE40 FPGA. Note that several of the iCE40 pins brought out to the PMOD -connectors are capable of operating as differential pairs. - -.. figure:: img/icev_wireless_back.jpg - :align: center - :alt: ICE-V Wireless (Back) - - ICE-V Wireless (Back) - -The J3 pins are 4V, 3.3V, NRST, GPIO2, GPIO3, GPIO8, GPIO9, GPIO10, GPIO20, -GPIO21, FPGA_P34, and GND. Note that GPIO2 and GPIO3 may be configured for -ADC operation. - -For PMOD details, please refer to the `PMOD Specification`_ and the image -below. - -.. figure:: img/icev_wireless_pinout.jpg - :align: center - :alt: ICE-V Wireless Pinout - -Programming and Debugging -************************* - -Programming and debugging for the ICE-V Wireless ESP32-C3 target is -incredibly easy 🎉 following the steps below. - -Building and Flashing -********************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: icev_wireless - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -For the :code:`Hello, world!` application, follow the instructions below. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: icev_wireless - :goals: build flash - -Open the serial monitor using the following command: - -.. code-block:: console - - $ west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! icev_wireless - -Debugging -********* - -As with much custom hardware, the ESP32C3 modules require patches to -OpenOCD that are not upstreamed. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained by running the following extension: - -.. code-block:: console - - west espressif install - -.. note:: - - By default, the OpenOCD will be downloaded and installed under $HOME/.espressif/tools/zephyr directory - (%USERPROFILE%/.espressif/tools/zephyr on Windows). - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: icev_wireless - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: icev_wireless - :maybe-skip-config: - :goals: debug - -References -********** - -.. _ICE-V Wireless Github Project: - https://github.com/ICE-V-Wireless/ICE-V-Wireless - -.. _ESP32-C3-MINI-1 Datasheet: - https://www.espressif.com/sites/default/files/documentation/esp32-c3-mini-1_datasheet_en.pdf - -.. _ESP32-C3 Datasheet: - https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf - -.. _ESP32-C3 Technical Reference Manual: - https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf - -.. _iCE40 UltraPlus Family Datasheet: - https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/iCE/iCE40-UltraPlus-Family-Data-Sheet.ashx - -.. _PMOD Specification: - https://digilent.com/reference/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf diff --git a/boards/riscv/icev_wireless/icev_wireless_defconfig b/boards/riscv/icev_wireless/icev_wireless_defconfig deleted file mode 100644 index c5be5732a71..00000000000 --- a/boards/riscv/icev_wireless/icev_wireless_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ICEV_WIRELESS=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/riscv/index.rst b/boards/riscv/index.rst deleted file mode 100644 index aecea8aa600..00000000000 --- a/boards/riscv/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-riscv: - -RISC-V Boards -############# - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/riscv/it82xx2_evb/Kconfig.board b/boards/riscv/it82xx2_evb/Kconfig.board deleted file mode 100644 index 1aa6f491d7f..00000000000 --- a/boards/riscv/it82xx2_evb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_IT82XX2_EVB - bool "IT82XX2 EV-board" - depends on SOC_IT8XXX2 diff --git a/boards/riscv/it82xx2_evb/Kconfig.defconfig b/boards/riscv/it82xx2_evb/Kconfig.defconfig deleted file mode 100644 index 37d6dc601c9..00000000000 --- a/boards/riscv/it82xx2_evb/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_IT82XX2_EVB - -config BOARD - default "it82xx2_evb" - -config INPUT - default y if KSCAN - -endif diff --git a/boards/riscv/it82xx2_evb/doc/index.rst b/boards/riscv/it82xx2_evb/doc/index.rst deleted file mode 100644 index 293cc5b156d..00000000000 --- a/boards/riscv/it82xx2_evb/doc/index.rst +++ /dev/null @@ -1,247 +0,0 @@ -.. _it82xx2_evb: - -ITE IT82XX2 series -###################### - -Overview -******** - -The IT82XX2 is a 32-bit RISC-V microcontroller. -And a highly integrated embedded controller with system functions. -It is suitable for mobile system applications. The picture below is -the IT82202 development board (also known as it82xx2_evb) and its debug card. - -.. figure:: it82xx2_evb_and_debug_card.jpg - :align: center - :alt: IT82202 EVB - -To find out more about ITE, visit our World Wide Web at:`ITE's website`_ - -Hardware -******** -The IT82XX2 series contains different chip types(ex, it82202, it82302), -and they support different hardware features. -Listing the IT82202 hardware features as following: - -- RISC-V RV32IMAFC instruction set -- 4KB instruction cache size -- 256KB SRAM in total -- Built-in 32.768 kHz clock generator -- Embedded Flash, 512K/1024K-byte e-flash -- eSPI, SSPI, SPI slave, BRAM, KBC, PECI, UART -- GPIO, PWM, ADC, INTC, WUC, Timer, Watchdog, KB scan, JTAG -- Support 6 Voltage Comparator -- Support Cryptographic Engine -- 6 SMBus channels, with 6 DMA controller, compatible with I2C -- USB 2.0 Full-speed Controller -- USB Type-c CC Logic -- USB Power Delivery - - -Supported Features -================== -currently supports the following hardware features: - -.. list-table:: Supported Features - :header-rows: 1 - :widths: auto - - * - Interface - - Controller - - Driver/Component - * - NVIC - - on-chip - - interrupt controller - * - FLASH - - on-chip - - flash controller - * - PINCTRL - - on-chip - - pin controller - * - ESPI - - on-chip - - espi - * - PECI - - on-chip - - peci - * - UART - - on-chip - - serial - * - GPIO - - on-chip - - gpio - * - PWM - - on-chip - - pwm - * - ADC - - on-chip - - adc - * - TIMER - - on-chip - - timer - * - WATCHDOG - - on-chip - - watchdog - * - KSCAN - - on-chip - - kscan - * - SENSOR - - on-chip - - voltage comparator - * - I2C - - on-chip - - i2c - - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the -:zephyr_file:`boards/riscv/it82xx2_evb/it82xx2_evb_defconfig` Kconfig file. - -Programming and debugging on it82202 -************************************ - -In order to upload the application to the device, -you'll need our flash tool and Download board. -You can get them at: `ITE's website`_. - -Wiring -======= -#. Connect the Download Board to your host computer using the USB cable. - -#. Connect the it82xx2_evb to the evolution motherboard. - -#. Connect the Download Board J5 to J41 on the evolution motherboard. - -#. Connect the USB to UART wire to J33 on the evolution motherboard. - - .. image:: it82xx2_evb_wiring.jpg - :align: center - :alt: it82xx2_evb wiring - - .. note:: Be careful during connection! - Use separate wires to connect I2C pins with pins on the it82xx2_evb board. - Wiring connection is described in the table below. - - +-------------+---------------+ - | J5 | it82xx2_evb | - | Connector | J41 Connector | - +=============+===============+ - | 2 | E0 | - +-------------+---------------+ - | 3 | E7 | - +-------------+---------------+ - | 4 | GND | - +-------------+---------------+ - - For USB to UART cable, connect the evolution motherboard as below: - - +-------------+---------------+ - | USB to UART | Evolution | - | cable | motherboard | - | | J33 Connector | - +=============+===============+ - | RX | B0 | - +-------------+---------------+ - | TX | B1 | - +-------------+---------------+ - | GND | GND | - +-------------+---------------+ - -Building -======== - -#. Build :ref:`hello_world` application as you would normally do - (see :`Zephyr Getting Started Guide`_):. - - .. zephyr-app-commands:: - :board: it82xx2_evb - :zephyr-app: samples/hello_world - :goals: build - -#. The file :file:`zephyr.bin` will be created by west. - -Flashing -======== - -Windows --------- - -Use the winflash tool to program a zephyr application -to the it82xx2 board flash. - -#. Open the winflash tool and make sure the order you open the switch is right. - First, turn on the Download board switch. - Second, turn on the it82xx2_evb board switch. - Then, configure your winflash tool like below. - - .. figure:: WinFlashTool_P2.jpg - :align: center - - .. figure:: WinFlashTool_P4.jpg - -#. Using the winflash tool flash ``zephyr.bin`` into your ITE board. - First, click the ``Load`` button and select your ``zephyr.bin`` file. - Second, click ``run`` to flash the image into board. - - .. figure:: WinFlashTool_P3.jpg - :align: center - -#. At this point, you have flashed your image into ITE board and - it will work if you turn on the ITE board. You can use a terminal program - to verify flashing worked correctly. - - For example, open device manager to find the USB Serial Port(COM4) and use your - terminal program to connect it(Speed: 115200). - - .. figure:: WinFlashTool_P1.jpg - :align: center - -#. Turn on the it82xx2_evb board switch, you should see ``"Hello World! it82xx2_evb"`` - sent by the board. If you don't see this message, press the Reset button and the - message should appear. - -Ubuntu --------- - -#. Run your favorite terminal program to listen for output. - Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. - - For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -b 115200 - -#. Open a second terminal window and use the Linux flash tool to flash your board. - - .. code-block:: console - - $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin - - .. note:: The source code of ITE tool can be downloaded here: - https://www.ite.com.tw/uploads/product_download/itedlb4-linux-v106.tar.bz2 - -#. Split first and second terminal windows to view both of them. - You should see ``"Hello World! it82xx2_evb"`` in the first terminal window. - If you don't see this message, press the Reset button and the message should appear. - -Debugging -========= - -it82xx2_evb board can be debugged by connecting USB to UART. We can write commands and -read messages through minicom in the Ubuntu terminal. - -Troubleshooting -=============== - -#. If the flash tool reports a failure, re-plug the 8390 Download board or - power cycle the it82xx2_evb board and try again. - -References -========== - -.. target-notes:: - -.. _ITE's website: https://www.ite.com.tw/zh-tw/product/view?mid=169 -.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html diff --git a/boards/riscv/it8xxx2_evb/Kconfig.board b/boards/riscv/it8xxx2_evb/Kconfig.board deleted file mode 100644 index 52040e4854c..00000000000 --- a/boards/riscv/it8xxx2_evb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_IT8XXX2_EVB - bool "IT8XXX2 EV-board" - depends on SOC_IT8XXX2 diff --git a/boards/riscv/it8xxx2_evb/Kconfig.defconfig b/boards/riscv/it8xxx2_evb/Kconfig.defconfig deleted file mode 100644 index 8c198316bed..00000000000 --- a/boards/riscv/it8xxx2_evb/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_IT8XXX2_EVB - -config BOARD - default "it8xxx2_evb" - -if PM -config PM_DEVICE - default y - -choice PM_POLICY - default PM_POLICY_CUSTOM -endchoice -endif # PM - -config INPUT - default y if KSCAN - -endif # BOARD_IT8XXX2_EVB diff --git a/boards/riscv/it8xxx2_evb/doc/index.rst b/boards/riscv/it8xxx2_evb/doc/index.rst deleted file mode 100644 index 419a525c1e7..00000000000 --- a/boards/riscv/it8xxx2_evb/doc/index.rst +++ /dev/null @@ -1,228 +0,0 @@ -.. _it8xxx2_evb: - -ITE IT8XXX2 series -###################### - -Overview -******** - -The IT8XXX2 is a 32-bit RISC-V Micro-controller. -And a highly integrated embedded controller with system functions. -It is suitable for mobile system applications. The picture below is -the IT81302 MECC board (also known as it8xxx2_evb) and its debug card. - -.. figure:: it8xxx2_evb_and_debug_card.jpg - :align: center - :alt: IT81302 EVB - -To find out more about ITE, visit our World Wide Web at:`ITE's website`_ - -Hardware -******** -The IT8XXX2 series contains different chip types(ex, it81302, it83202), -and they support different hardware features. -Listing the IT81302 hardware features as following: - -- RISC-V RV32IMAFC instruction set -- 4KB instruction cache size -- 60KB SDRAM in total -- Built-in 32.768 kHz clock generator -- PWM, eSPI, LPC, FLASH, UART, GPIO, Timer, Watchdog, ADC, JTAG -- 6 SMBus channels, with 3 DMA controllers, compatible with I2C -- SPI master/slave -- USB Type-c CC Logic -- USB Power Delivery -- Support KB scan - - -Supported Features -================== -currently supports the following hardware features: - -.. list-table:: Supported Features - :header-rows: 1 - :widths: auto - - * - Interface - - Controller - - Driver/Component - * - NVIC - - on-chip - - interrupt controller - * - TIMER - - on-chip - - timer - * - UART - - on-chip - - serial - * - GPIO - - on-chip - - gpio - * - ADC - - on-chip - - adc - * - I2C - - on-chip - - i2c - * - KSCAN - - on-chip - - kscan - - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the -:zephyr_file:`boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig` Kconfig file. - -Hardware reworks -**************** - -Before using the it8xxx2_evb, some hardware rework is needed. The HW rework -guide can be found in ITE's website. -https://www.ite.com.tw/uploads/product_download/IT81302_MECC_Rework_Guide_0927.pdf - -Programming and debugging on it83202 -************************************ - -In order to upload the application to the device, -you'll need our flash tool and Download board. -You can get them at: `ITE's website`_. - -Wiring -======= -#. Connect the Download Board to your host computer using the USB cable. - -#. Connect the it8xxx2_evb to your host computer or a 5V1A USB power supply. - -#. Connect the Download Board J5 to J8 on the it8xxx2_evb board. - -#. Connect the USB to UART wire to it8xxx2_evb. - - .. image:: it8xxx2_evb_wiring.jpg - :align: center - :alt: it8xxx2_evb wiring - - .. note:: Be careful during connection! - Use separate wires to connect I2C pins with pins on the it8xxx2_evb board. - Wiring connection is described in the table below. - - +-------------+---------------+ - | J5 | it8xxx2_evb | - | Connector | J8 Connector | - +=============+===============+ - | 2 | 1 | - +-------------+---------------+ - | 3 | 3 | - +-------------+---------------+ - | 4 | 5 | - +-------------+---------------+ - - For USB to UART cable, connect the it8xxx2_evb as below: - - +-------------+---------------+ - | USB to UART | it8xxx2_evb | - | cable | J5 Connector | - +=============+===============+ - | RX | J5.3 | - +-------------+---------------+ - | TX | J5.4 | - +-------------+---------------+ - | GND | eSPI Debug.10 | - +-------------+---------------+ - -Building -======== - -#. Build :ref:`hello_world` application as you would normally do - (see :`Zephyr Getting Started Guide`_):. - - .. zephyr-app-commands:: - :board: it8xxx2_evb - :zephyr-app: samples/hello_world - :goals: build - -#. The file :file:`zephyr.bin` will be created by west. - -Flashing -======== - -Windows --------- - -Use the winflash tool to program a zephyr application -to the it8xxx2 board flash. - -#. Open winflash tool and make sure the order you open the switch is right. - Fisrt, turn on the Download board switch. - Second, turn on the it8xxx2_evb board switch. - Then, configure your winflash tool like below. - - .. figure:: WinFlashTool_P2.jpg - :align: center - - .. figure:: WinFlashTool_P4.jpg - -#. Using winflash tool flash zephyr.bin into your ITE board. - First, click ``Load`` button and select your zephyr.bin file. - Second, click ``run`` to flash the iamge into board. - - .. figure:: WinFlashTool_P3.jpg - :align: center - -#. At this point, you have flashed your image into ITE board and - it will work if you turn on ITE board. You can use a terminal program - to verify flashing worked correctly. - - For example, open device manager to find the USB Serial Port(COM4) and use your - terminal program to connect it(Speed: 115200). - - .. figure:: WinFlashTool_P1.jpg - :align: center - -#. Turn on the it8xxx2_evb board switch, you should see ``"Hello World! it8xxx2_evb"`` - sent by the board. If you don't see this message, press the Reset button and the - message should appear. - -Ubuntu --------- - -#. Run your favorite terminal program to listen for output. - Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. - - For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -b 115200 - -#. Open a second terminal window and use linux flash tool to flash your board. - - .. code-block:: console - - $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin - - .. note:: The source code of ITE tool can be downloaded here: - https://www.ite.com.tw/uploads/product_download/itedlb4-linux-v106.tar.bz2 - -#. Split first and second terminal windows to view both of them. - You should see ``"Hello World! it8xxx2_evb"`` in the first terminal window. - If you don't see this message, press the Reset button and the message should appear. - -Debugging -========= - -Supporting uart debug, currently. - -Troubleshooting -=============== - -#. If the flash tool reports a failure, re-plug the 8390 Download board or - power cycle the it8xxx2_evb board and try again. - -References -========== - -.. target-notes:: - -.. _ITE's website: http://www.ite.com.tw/en/product/view?mid=149 -.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html diff --git a/boards/riscv/litex_vexriscv/Kconfig.board b/boards/riscv/litex_vexriscv/Kconfig.board deleted file mode 100644 index de9d8026b6a..00000000000 --- a/boards/riscv/litex_vexriscv/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2018 - 2019 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LITEX_VEXRISCV - bool "Board with LiteX/VexRiscV CPU" - depends on SOC_RISCV32_LITEX_VEXRISCV diff --git a/boards/riscv/litex_vexriscv/Kconfig.defconfig b/boards/riscv/litex_vexriscv/Kconfig.defconfig deleted file mode 100644 index ef0440b9a37..00000000000 --- a/boards/riscv/litex_vexriscv/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2018 - 2019 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LITEX_VEXRISCV - -config BOARD - default "litex_vexriscv" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_LITEX_VEXRISCV diff --git a/boards/riscv/longan_nano/Kconfig.board b/boards/riscv/longan_nano/Kconfig.board deleted file mode 100644 index f656bdbf67a..00000000000 --- a/boards/riscv/longan_nano/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Tokita, Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LONGAN_NANO - bool "Sipeed Longan Nano target" - depends on SOC_GD32VF103 - -config BOARD_LONGAN_NANO_LITE - bool "Sipeed Longan Nano Lite target" - depends on SOC_GD32VF103 diff --git a/boards/riscv/longan_nano/Kconfig.defconfig b/boards/riscv/longan_nano/Kconfig.defconfig deleted file mode 100644 index af4f75cf898..00000000000 --- a/boards/riscv/longan_nano/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Sipeed longan nano Development Board Configuration - -# Copyright (c) 2021 Tokita, Hiroshi - -if BOARD_LONGAN_NANO || BOARD_LONGAN_NANO_LITE - -config BOARD - default "longan_nano" if BOARD_LONGAN_NANO - default "longan_nano_lite" if BOARD_LONGAN_NANO_LITE - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_LONGAN_NANO || BOARD_LONGAN_NANO_LITE diff --git a/boards/riscv/longan_nano/longan_nano_lite.yaml b/boards/riscv/longan_nano/longan_nano_lite.yaml deleted file mode 100644 index 14f7e6fc938..00000000000 --- a/boards/riscv/longan_nano/longan_nano_lite.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: longan_nano_lite -name: Sipeed Longan Nano Lite -type: mcu -arch: riscv -toolchain: - - zephyr - - xtools -flash: 64 -ram: 20 -supported: - - watchdog - - dma - - spi -vendor: sipeed diff --git a/boards/riscv/longan_nano/longan_nano_lite_defconfig b/boards/riscv/longan_nano/longan_nano_lite_defconfig deleted file mode 100644 index 2c3743c0162..00000000000 --- a/boards/riscv/longan_nano/longan_nano_lite_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Sipeed Longan Nano Lite board Configuration -# -# Copyright (c) 2021 Tokita, Hiroshi -# -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32VF103=y -CONFIG_SOC_GD32VF103=y -CONFIG_BOARD_LONGAN_NANO_LITE=y - -CONFIG_GD32_HXTAL_8MHZ=y - -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/riscv/m2gl025_miv/Kconfig.board b/boards/riscv/m2gl025_miv/Kconfig.board deleted file mode 100644 index 9f81fad406f..00000000000 --- a/boards/riscv/m2gl025_miv/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_M2GL025_MIV - bool "Microchip M2GL025 IGLOO2 dev board with Mi-V CPU" - depends on SOC_MIV diff --git a/boards/riscv/m2gl025_miv/Kconfig.defconfig b/boards/riscv/m2gl025_miv/Kconfig.defconfig deleted file mode 100644 index 43f9c813c9a..00000000000 --- a/boards/riscv/m2gl025_miv/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "m2gl025_miv" - depends on BOARD_M2GL025_MIV diff --git a/boards/riscv/mpfs_icicle/Kconfig.board b/boards/riscv/mpfs_icicle/Kconfig.board deleted file mode 100644 index e772b82d7f5..00000000000 --- a/boards/riscv/mpfs_icicle/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021-2022 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MPFS_ICICLE - bool "Microchip PolarFire SoC ICICLE kit" - depends on SOC_POLARFIRE - select 64BIT - select SCHED_IPI_SUPPORTED - select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/riscv/mpfs_icicle/Kconfig.defconfig b/boards/riscv/mpfs_icicle/Kconfig.defconfig deleted file mode 100644 index 5993e6878c9..00000000000 --- a/boards/riscv/mpfs_icicle/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2020-2021 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "mpfs_icicle" - depends on BOARD_MPFS_ICICLE diff --git a/boards/riscv/neorv32/Kconfig.board b/boards/riscv/neorv32/Kconfig.board deleted file mode 100644 index 6d85ebb2e40..00000000000 --- a/boards/riscv/neorv32/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NEORV32 - bool "NEORV32 Processor (SoC)" - depends on SOC_NEORV32 diff --git a/boards/riscv/neorv32/Kconfig.defconfig b/boards/riscv/neorv32/Kconfig.defconfig deleted file mode 100644 index 350255fb06a..00000000000 --- a/boards/riscv/neorv32/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NEORV32 - -config BOARD - default "neorv32" - -endif # BOARD_NEORV32 diff --git a/boards/riscv/neorv32/neorv32_1_8_6.conf b/boards/riscv/neorv32/neorv32_1_8_6.conf deleted file mode 100644 index b1852631eeb..00000000000 --- a/boards/riscv/neorv32/neorv32_1_8_6.conf +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NEORV32_V1_8_6=y diff --git a/boards/riscv/neorv32/revision.cmake b/boards/riscv/neorv32/revision.cmake deleted file mode 100644 index b09cf369611..00000000000 --- a/boards/riscv/neorv32/revision.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT MAJOR.MINOR.PATCH - DEFAULT_REVISION 1.8.6 -) diff --git a/boards/riscv/niosv_g/Kconfig.board b/boards/riscv/niosv_g/Kconfig.board deleted file mode 100644 index bcc48f497d8..00000000000 --- a/boards/riscv/niosv_g/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NIOSV_G - bool "Intel FPGA Nios V/g General Purpose Processor" - depends on SOC_NIOSV_G diff --git a/boards/riscv/niosv_g/Kconfig.defconfig b/boards/riscv/niosv_g/Kconfig.defconfig deleted file mode 100644 index ecfc8b41bab..00000000000 --- a/boards/riscv/niosv_g/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NIOSV_G - -config BOARD - default "niosv_g" - -endif # BOARD_NIOSV_G diff --git a/boards/riscv/niosv_g/niosv_g_defconfig b/boards/riscv/niosv_g/niosv_g_defconfig deleted file mode 100644 index f933bca3874..00000000000 --- a/boards/riscv/niosv_g/niosv_g_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NIOSV=y -CONFIG_SOC_NIOSV_G=y -CONFIG_BOARD_NIOSV_G=y -CONFIG_CONSOLE=y -CONFIG_PRINTK=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_XIP=n diff --git a/boards/riscv/niosv_m/Kconfig.board b/boards/riscv/niosv_m/Kconfig.board deleted file mode 100644 index 92e853c4640..00000000000 --- a/boards/riscv/niosv_m/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NIOSV_M - bool "Intel FPGA NIOSV Microcontroller Core Processor" - depends on SOC_NIOSV_M diff --git a/boards/riscv/niosv_m/Kconfig.defconfig b/boards/riscv/niosv_m/Kconfig.defconfig deleted file mode 100644 index 40d9389e25b..00000000000 --- a/boards/riscv/niosv_m/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NIOSV_M - -config BOARD - default "niosv_m" - -endif # BOARD_NIOSV_M diff --git a/boards/riscv/niosv_m/niosv_m_defconfig b/boards/riscv/niosv_m/niosv_m_defconfig deleted file mode 100644 index 1eba59917a3..00000000000 --- a/boards/riscv/niosv_m/niosv_m_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NIOSV=y -CONFIG_SOC_NIOSV_M=y -CONFIG_BOARD_NIOSV_M=y -CONFIG_CONSOLE=y -CONFIG_PRINTK=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_ALTERA_JTAG=y -CONFIG_XIP=n diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.board b/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.board deleted file mode 100644 index 9bbbba60dd4..00000000000 --- a/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF54H20PDK_NRF54H20_CPUPPR - bool "nRF54H20 PDK nRF54H20 PPR MCU" - depends on SOC_NRF54H20_ENGA_CPUPPR diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.defconfig b/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.defconfig deleted file mode 100644 index 256976d6519..00000000000 --- a/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "nrf54h20pdk_nrf54h20_cpuppr" - depends on BOARD_NRF54H20PDK_NRF54H20_CPUPPR diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/board.cmake b/boards/riscv/nrf54h20pdk_nrf54h20/board.cmake deleted file mode 100644 index 4c63f1dd05e..00000000000 --- a/boards/riscv/nrf54h20pdk_nrf54h20/board.cmake +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr_defconfig b/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr_defconfig deleted file mode 100644 index 112140693ef..00000000000 --- a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF54HX=y -CONFIG_SOC_NRF54H20=y -CONFIG_SOC_NRF54H20_ENGA_CPUPPR=y -CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPUPPR=y - -CONFIG_USE_DT_CODE_PARTITION=y - -CONFIG_SERIAL=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/opentitan_earlgrey/Kconfig.board b/boards/riscv/opentitan_earlgrey/Kconfig.board deleted file mode 100644 index 544c02b1b2a..00000000000 --- a/boards/riscv/opentitan_earlgrey/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 by Rivos Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OPENTITAN_EARLGREY - bool "OpenTitan Earl Grey Target" - depends on SOC_OPENTITAN diff --git a/boards/riscv/opentitan_earlgrey/Kconfig.defconfig b/boards/riscv/opentitan_earlgrey/Kconfig.defconfig deleted file mode 100644 index 743d2bd28a1..00000000000 --- a/boards/riscv/opentitan_earlgrey/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 by Rivos Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OPENTITAN_EARLGREY - -config BOARD - default "opentitan_earlgrey" - -endif # BOARD_OPENTITAN_EARLGREY diff --git a/boards/riscv/opentitan_earlgrey/opentitan_earlgrey_defconfig b/boards/riscv/opentitan_earlgrey/opentitan_earlgrey_defconfig deleted file mode 100644 index 886e439b88a..00000000000 --- a/boards/riscv/opentitan_earlgrey/opentitan_earlgrey_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 by Rivos Inc. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_OPENTITAN=y -CONFIG_BOARD_OPENTITAN_EARLGREY=y -CONFIG_XIP=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_BUILD_OUTPUT_BIN=n diff --git a/boards/riscv/qemu_riscv32/Kconfig.board b/boards/riscv/qemu_riscv32/Kconfig.board deleted file mode 100644 index 7c94b59455c..00000000000 --- a/boards/riscv/qemu_riscv32/Kconfig.board +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV32 - bool "QEMU RISCV32 target" - depends on SOC_RISCV_VIRT - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - select CPU_HAS_FPU - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config BOARD_QEMU_RISCV32_SMP - bool "QEMU RISCV32 SMP target" - depends on SOC_RISCV_VIRT - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - select CPU_HAS_FPU - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config BOARD_QEMU_RISCV32_XIP - bool "QEMU RISCV32 XIP target" - depends on SOC_SIFIVE_FREEDOM_E340 - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - select CPU_HAS_FPU - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI diff --git a/boards/riscv/qemu_riscv32/Kconfig.defconfig b/boards/riscv/qemu_riscv32/Kconfig.defconfig deleted file mode 100644 index f0e0768d082..00000000000 --- a/boards/riscv/qemu_riscv32/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_riscv32" if BOARD_QEMU_RISCV32 - default "qemu_riscv32_xip" if BOARD_QEMU_RISCV32_XIP - default "qemu_riscv32_smp" if BOARD_QEMU_RISCV32_SMP - -# Use thread local storage by default so that -# this feature gets more CI coverage. -config THREAD_LOCAL_STORAGE - default y diff --git a/boards/riscv/qemu_riscv32/board.cmake b/boards/riscv/qemu_riscv32/board.cmake deleted file mode 100644 index 9ade8c5ef28..00000000000 --- a/boards/riscv/qemu_riscv32/board.cmake +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_binary_suffix riscv32) -set(QEMU_CPU_TYPE_${ARCH} riscv32) - -if(CONFIG_BOARD_QEMU_RISCV32 OR CONFIG_BOARD_QEMU_RISCV32_SMP) - set(QEMU_FLAGS_${ARCH} - -nographic - -machine virt - -bios none - -m 256 - ) -else() - set(QEMU_FLAGS_${ARCH} - -nographic - -machine sifive_e - ) -endif() - - -board_set_debugger_ifnset(qemu) diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_defconfig b/boards/riscv/qemu_riscv32/qemu_riscv32_defconfig deleted file mode 100644 index 946e679a6e8..00000000000 --- a/boards/riscv/qemu_riscv32/qemu_riscv32_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_RISCV_VIRT=y -CONFIG_BOARD_QEMU_RISCV32=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_STACK_SENTINEL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_XIP=n -CONFIG_RISCV_PMP=y diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_smp.dts b/boards/riscv/qemu_riscv32/qemu_riscv32_smp.dts deleted file mode 100644 index d335dbcde6f..00000000000 --- a/boards/riscv/qemu_riscv32/qemu_riscv32_smp.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &ram0; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_smp.yaml b/boards/riscv/qemu_riscv32/qemu_riscv32_smp.yaml deleted file mode 100644 index 38ffe83e831..00000000000 --- a/boards/riscv/qemu_riscv32/qemu_riscv32_smp.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: qemu_riscv32_smp -name: QEMU Emulation for RISC-V 32-bit SMP -type: qemu -simulation: qemu -arch: riscv -toolchain: - - zephyr - - xtools -supported: - - netif - - smp -testing: - default: true - ignore_tags: - - net - - bluetooth diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_smp_defconfig b/boards/riscv/qemu_riscv32/qemu_riscv32_smp_defconfig deleted file mode 100644 index 90f87ef6b98..00000000000 --- a/boards/riscv/qemu_riscv32/qemu_riscv32_smp_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_RISCV_VIRT=y -CONFIG_BOARD_QEMU_RISCV32_SMP=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_STACK_SENTINEL=y -CONFIG_XIP=n -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_QEMU_ICOUNT=n - -CONFIG_IDLE_STACK_SIZE=1024 -CONFIG_RISCV_PMP=y diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_xip_defconfig b/boards/riscv/qemu_riscv32/qemu_riscv32_xip_defconfig deleted file mode 100644 index 948fa909a08..00000000000 --- a/boards/riscv/qemu_riscv32/qemu_riscv32_xip_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_E300=y -CONFIG_SOC_SIFIVE_FREEDOM_E340=y -CONFIG_BOARD_QEMU_RISCV32_XIP=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_PINCTRL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_RISCV_CORE_E31=y diff --git a/boards/riscv/qemu_riscv32e/Kconfig.board b/boards/riscv/qemu_riscv32e/Kconfig.board deleted file mode 100644 index ace6a7322dd..00000000000 --- a/boards/riscv/qemu_riscv32e/Kconfig.board +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV32E - bool "QEMU RISCV32E target" - depends on SOC_RISCV_VIRT - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - select RISCV_ISA_RV32E - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI diff --git a/boards/riscv/qemu_riscv32e/Kconfig.defconfig b/boards/riscv/qemu_riscv32e/Kconfig.defconfig deleted file mode 100644 index 54d455ef540..00000000000 --- a/boards/riscv/qemu_riscv32e/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2022 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_riscv32e" if BOARD_QEMU_RISCV32E - -# Use thread local storage by default so that -# this feature gets more CI coverage. -config THREAD_LOCAL_STORAGE - default y diff --git a/boards/riscv/qemu_riscv64/Kconfig.board b/boards/riscv/qemu_riscv64/Kconfig.board deleted file mode 100644 index f75ba14b7a4..00000000000 --- a/boards/riscv/qemu_riscv64/Kconfig.board +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2019 BayLibre SAS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV64 - bool "QEMU RISCV64 target" - depends on SOC_RISCV_VIRT - select QEMU_TARGET - select 64BIT - select HAS_COVERAGE_SUPPORT - select CPU_HAS_FPU_DOUBLE_PRECISION - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config BOARD_QEMU_RISCV64_SMP - bool "QEMU RISCV64 SMP target" - depends on SOC_RISCV_VIRT - select QEMU_TARGET - select 64BIT - select HAS_COVERAGE_SUPPORT - select CPU_HAS_FPU_DOUBLE_PRECISION - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI diff --git a/boards/riscv/qemu_riscv64/Kconfig.defconfig b/boards/riscv/qemu_riscv64/Kconfig.defconfig deleted file mode 100644 index 7b5d8bfbdcf..00000000000 --- a/boards/riscv/qemu_riscv64/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019 BayLibre SAS -# SPDX-License-Identifier: Apache-2.0 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_riscv64" if BOARD_QEMU_RISCV64 - default "qemu_riscv64_smp" if BOARD_QEMU_RISCV64_SMP diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64_defconfig b/boards/riscv/qemu_riscv64/qemu_riscv64_defconfig deleted file mode 100644 index 6bfc46ac907..00000000000 --- a/boards/riscv/qemu_riscv64/qemu_riscv64_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_RISCV_VIRT=y -CONFIG_BOARD_QEMU_RISCV64=y -CONFIG_PRIVILEGED_STACK_SIZE=2048 -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_STACK_SENTINEL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_XIP=n -CONFIG_RISCV_PMP=y diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64_smp.dts b/boards/riscv/qemu_riscv64/qemu_riscv64_smp.dts deleted file mode 100644 index d335dbcde6f..00000000000 --- a/boards/riscv/qemu_riscv64/qemu_riscv64_smp.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &ram0; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64_smp.yaml b/boards/riscv/qemu_riscv64/qemu_riscv64_smp.yaml deleted file mode 100644 index 5daf38c7055..00000000000 --- a/boards/riscv/qemu_riscv64/qemu_riscv64_smp.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: qemu_riscv64_smp -name: QEMU Emulation for RISC-V 64-bit SMP -type: qemu -simulation: qemu -arch: riscv -toolchain: - - zephyr -supported: - - netif - - smp -testing: - default: true - ignore_tags: - - net - - bluetooth diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64_smp_defconfig b/boards/riscv/qemu_riscv64/qemu_riscv64_smp_defconfig deleted file mode 100644 index 265d84a1ded..00000000000 --- a/boards/riscv/qemu_riscv64/qemu_riscv64_smp_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_RISCV_VIRT=y -CONFIG_BOARD_QEMU_RISCV64_SMP=y -CONFIG_PRIVILEGED_STACK_SIZE=2048 -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_STACK_SENTINEL=y -CONFIG_XIP=n -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_QEMU_ICOUNT=n - -CONFIG_IDLE_STACK_SIZE=1024 -CONFIG_RISCV_PMP=y -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/riscv/riscv32_virtual/Kconfig.board b/boards/riscv/riscv32_virtual/Kconfig.board deleted file mode 100644 index c8722acb384..00000000000 --- a/boards/riscv/riscv32_virtual/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Meta -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RISCV32_VIRTUAL - bool "riscv32_virtual" - depends on SOC_RISCV32_VIRTUAL_RENODE diff --git a/boards/riscv/riscv32_virtual/Kconfig.defconfig b/boards/riscv/riscv32_virtual/Kconfig.defconfig deleted file mode 100644 index 840b10fd594..00000000000 --- a/boards/riscv/riscv32_virtual/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Meta -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "riscv32_virtual" - depends on BOARD_RISCV32_VIRTUAL diff --git a/boards/riscv/rv32m1_vega/Kconfig.board b/boards/riscv/rv32m1_vega/Kconfig.board deleted file mode 100644 index 1c36ce9cd7e..00000000000 --- a/boards/riscv/rv32m1_vega/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RV32M1_VEGA - bool "RV32M1 RISC-V cores" - depends on SOC_OPENISA_RV32M1_RISCV32 diff --git a/boards/riscv/rv32m1_vega/Kconfig.defconfig b/boards/riscv/rv32m1_vega/Kconfig.defconfig deleted file mode 100644 index 9446ac4a9ae..00000000000 --- a/boards/riscv/rv32m1_vega/Kconfig.defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RV32M1_VEGA - -config BOARD - default "rv32m1_vega_ri5cy" if SOC_OPENISA_RV32M1_RI5CY - default "rv32m1_vega_zero_riscy" if SOC_OPENISA_RV32M1_ZERO_RISCY - -if BT - -config BT_CTLR - default y - -#TODO: Resolve the complete non-BLE support for crypto CAU3 firmware/driver -#config HAS_RV32M1_CAU3 -# bool -# default y if BT_CTLR_CRYPTO && !BT_CTLR_LE_ENC_SUPPORT - -config HAS_RV32M1_CAU3_BLE - bool - default y if BT_CTLR_CRYPTO && \ - (BT_CTLR_LE_ENC_SUPPORT || BT_CTLR_PRIVACY_SUPPORT) - -config RV32M1_INTMUX_CHANNEL_2 - default n - -config RV32M1_INTMUX_CHANNEL_3 - default n - -endif # BT - -endif # BOARD_RV32M1_VEGA diff --git a/boards/riscv/rv32m1_vega/board.cmake b/boards/riscv/rv32m1_vega/board.cmake deleted file mode 100644 index dc1b5b256c4..00000000000 --- a/boards/riscv/rv32m1_vega/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(OPENOCD_USE_LOAD_IMAGE NO) - -if(CONFIG_SOC_OPENISA_RV32M1_RI5CY) -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_ri5cy.cfg") -elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY) -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_zero_riscy.cfg") -endif() - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/riscv/rv32m1_vega/doc/index.rst b/boards/riscv/rv32m1_vega/doc/index.rst deleted file mode 100644 index a2f3d107224..00000000000 --- a/boards/riscv/rv32m1_vega/doc/index.rst +++ /dev/null @@ -1,841 +0,0 @@ -.. highlight:: sh - -.. _rv32m1_vega: - -OpenISA VEGAboard -################# - -Overview -******** - -The VEGAboard contains the RV32M1 SoC, featuring two RISC-V CPUs, -on-die XIP flash, and a full complement of peripherals, including a -2.4 GHz multi-protocol radio. It also has built-in sensors and -Arduino-style expansion connectors. - -.. figure:: rv32m1_vega.jpg - :align: center - :alt: RV32M1-VEGA - - OpenISA VEGAboard (image copyright: www.open-isa.org) - -The two RISC-V CPUs are named RI5CY and ZERO-RISCY, and are -respectively based on the `PULP platform`_ designs by the same names: -`RI5CY`_ and `ZERO-RISCY`_. RI5CY is the "main" core; it has more -flash and RAM as well as a more powerful CPU design. ZERO-RISCY is a -"secondary" core. The main ZERO-RISCY use-case is as a wireless -coprocessor for applications running on RI5CY. The two cores can -communicate via shared memory and messaging peripherals. - -Currently, Zephyr supports RI5CY with the ``rv32m1_vega_ri5cy`` board -configuration name, and ZERO_RISCY with the ``rv32m1_vega_zero_riscy`` board -configuration name. - -Hardware -******** - -The VEGAboard includes the following features. - -RV32M1 multi-core SoC: - -- 1 MiB flash and 192 KiB SRAM (RI5CY core) -- 256 KiB flash and 128 KiB SRAM (ZERO-RISCY core) -- Low power modes -- DMA support -- Watchdog, CRC, cryptographic acceleration, ADC, DAC, comparator, - timers, PWM, RTC, I2C, UART, SPI, external memory, I2S, smart - card, USB full-speed, uSDHC, and 2.4 GHz multiprotocol radio - peripherals - -On-board sensors and peripherals: - -- 32 Mbit SPI flash -- 6-axis accelerometer, magnetometer, and temperature sensor (FXOS8700) -- Ambient light sensor -- RGB LED -- microSD card slot -- Antenna interface - -Additional features: - -- Form-factor compatible with Arduino Uno Rev 3 expansion connector - layout (not all Arduino shields may be pin-compatible) -- UART via USB using separate OpenSDA chip -- RISC-V flash and debug using external JTAG dongle (not included) via - 2x5 5 mil pitch connector (commonly called the "ARM 10-pin JTAG" - connector) - -Supported Features -================== - -Zephyr's RI5CY configuration, ``rv32m1_vega_ri5cy``, currently supports -the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| EVENT | on-chip | event unit interrupt controller | -+-----------+------------+-------------------------------------+ -| INTMUX | on-chip | level 2 interrupt controller | -+-----------+------------+-------------------------------------+ -| LPTMR | on-chip | lptmr-based system timer | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| TPM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger; | -+-----------+------------+-------------------------------------+ - -Zephyr's ZERO-RISCY configuration, ``rv32m1_vega_zero_riscy``, currently -supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| EVENT | on-chip | event unit interrupt controller | -+-----------+------------+-------------------------------------+ -| INTMUX | on-chip | level 2 interrupt controller | -+-----------+------------+-------------------------------------+ -| LPTMR | on-chip | lptmr-based system timer | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| TPM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger; | -+-----------+------------+-------------------------------------+ - -BLE Software Link Layer experimental support -================================================== -This is an experimental feature supported on the Zephyr's RI5CY -configuration, ``rv32m1_vega_ri5cy``. It uses the Software Link Layer -framework by Nordic Semi to enable the on-SoC radio and transceiver for -implementing a software defined BLE controller. By using both the controller -and the host stack available in Zephyr, the following BLE samples can be used -with this board: - -- beacon -- central -- central_hr -- eddystone -- hci_uart -- ibeacon -- peripheral_csc (Cycling Speed Cadence) -- peripheral_dis (Device Information Service) -- peripheral_esp (Environmental Sensing Service) -- peripheral_hr (Heart Rate) -- peripheral_ht (Health Thermometer) -- peripheral -- scan_adv - -.. note:: - - BLE Software Link Layer limitations: - - - no 512/256 Kbps PHY - - no TX power adjustment - - -Connections and IOs -=================== - -RV32M1 SoC pins are brought out to Arduino-style expansion connectors. -These are 2 pins wide each, adding an additional row of expansion pins -per header compared to the standard Arduino layout. - -They are described in the tables in the following subsections. Since -pins are usually grouped by logical function in rows on these headers, -the odd- and even-numbered pins are listed in separate tables. The -"Port/bit" columns refer to the SoC PORT and GPIO peripheral -naming scheme, e.g. "E/13" means PORTE/GPIOE pin 13. - -See the schematic and chip reference manual for details. -(Documentation is available from the `OpenISA GitHub releases`_ page.) - -.. note:: - - Pins with peripheral functionality may also be muxed as GPIOs. - -**Top right expansion header (J1)** - -Odd/bottom pins: - -=== ======== ================= -Pin Port/bit Function -=== ======== ================= -1 E/13 I2S_TX_BCLK -3 E/14 I2S_TX_FS -5 E/15 I2S_TXD -7 E/19 I2S_MCLK -9 E/16 I2S_RX_BCLK -11 E/21 SOF_OUT -13 E/17 I2S_RX_FS -15 E/18 I2S_RXD -=== ======== ================= - -Even/top pins: - -=== ======== ================= -Pin Port/bit Function -=== ======== ================= -2 A/25 UART1_RX -4 A/26 UART1_TX -6 A/27 GPIO -8 B/13 PWM -10 B/14 GPIO -12 A/30 PWM -14 A/31 PWM/CMP -16 B/1 GPIO -=== ======== ================= - -**Top left expansion header (J2)** - -Odd/bottom pins: - -=== ======== ================= -Pin Port/bit Function -=== ======== ================= -1 D/5 FLEXIO_D25 -3 D/4 FLEXIO_D24 -5 D/3 FLEXIO_D23 -7 D/2 FLEXIO_D22 -9 D/1 FLEXIO_D21 -11 D/0 FLEXIO_D20 -13 C/30 FLEXIO_D19 -15 C/29 FLEXIO_D18 -17 C/28 FLEXIO_D17 -19 B/29 FLEXIO_D16 -=== ======== ================= - -Even/top pins: - -=== ======== ================= -Pin Port/bit Function -=== ======== ================= -2 B/2 GPIO -4 B/3 PWM -6 B/6 SPI0_PCS2 -8 B/5 SPI0_SOUT -10 B/7 SPI0_SIN -12 B/4 SPI0_SCK -14 - GND -16 - AREF -18 C/9 I2C0_SDA -20 C/10 I2C0_SCL -=== ======== ================= - -**Bottom left expansion header (J3)** - -Note that the headers at the bottom of the board have odd-numbered -pins on the top, unlike the headers at the top of the board. - -Odd/top pins: - -=== ======== ==================== -Pin Port/bit Function -=== ======== ==================== -1 A/21 ARDUINO_EMVSIM_PD -3 A/20 ARDUINO_EMVSIM_IO -5 A/19 ARDUINO_EMVSIM_VCCEN -7 A/18 ARDUINO_EMVSIM_RST -9 A/17 ARDUINO_EMVSIM_CLK -11 B/17 FLEXIO_D7 -13 B/16 FLEXIO_D6 -15 B/15 FLEXIO_D5 -=== ======== ==================== - -Even/bottom pins: note that these are mostly power-related. - -=== ======== ================= -Pin Port/bit Function -=== ======== ================= -2 - SDA_GPIO0 -4 - BRD_IO_PER -6 - RST_SDA -8 - BRD_IO_PER -10 - P5V_INPUT -12 - GND -14 - GND -16 - P5-9V VIN -=== ======== ================= - -**Bottom right expansion header (J4)** - -Note that the headers at the bottom of the board have odd-numbered -pins on the top, unlike the headers at the top of the board. - -Odd/top pins: - -=== ======== ======================================== -Pin Port/bit Function -=== ======== ======================================== -1 - TAMPER2 -3 - TAMPER1/RTC_CLKOUT -5 - TAMPER0/RTC_WAKEUP_b -7 E/2 ADC0_SE19 -9 E/5 LPCMP1_IN2/LPCMP1_OUT -11 - DAC0_OUT/ADC0_SE16/LPCMP0_IN3/LPCMP1_IN3 -=== ======== ======================================== - -Even/bottom pins: - -=== ======== =========================================== -Pin Port/bit Function -=== ======== =========================================== -2 C/11 ADC0_SE6 -4 C/12 ADC0_SE7 -6 B/9 ADC0_SE3 -8 E/4 ADC0_SE21 -10 E/10 ADC0_SE19 (and E/10, I2C3_SDA via 0 Ohm DNP) -12 E/11 ADC0_SE20 (and E/11, I2C3_SCL via 0 Ohm DNP) -=== ======== =========================================== - -Additional Pins ---------------- - -For an up-to-date description of additional pins (such as buttons, -LEDs, etc.) supported by Zephyr, see the board DTS files in the Zephyr -source code, i.e. -:zephyr_file:`boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.dts` for RI5CY and -:zephyr_file:`boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts` for -ZERO-RISCY. - -See the schematic in the documentation available from the `OpenISA -GitHub releases`_ page for additional details. - -System Clocks -============= - -The RI5CY and ZERO-RISCY cores are configured to use the slow internal -reference clock (SIRC) as the clock source for an LPTMR peripheral to manage -the system timer, and the fast internal reference clock (FIRC) to generate a -48MHz core clock. - -Serial Port -=========== - -The USB connector at the top left of the board (near the RESET button) is -connected to an OpenSDA chip which provides a serial USB device. This is -connected to the LPUART0 peripheral which the RI5CY and ZERO-RISCY cores use by -default for console and logging. - -.. warning:: - - The OpenSDA chip cannot be used to flash or debug the RISC-V cores. - - See the next section for flash and debug instructions for the - RISC-V cores using an external JTAG dongle. - -Programming and Debugging -************************* - -.. _rv32m1-programming-hw: - -.. important:: - - To use this board, you will need: - - - a `SEGGER J-Link`_ debug probe to debug the RISC-V cores - - a J-Link `9-Pin Cortex-M Adapter`_ board and ribbon cable - - the SEGGER `J-Link Software and Documentation Pack`_ software - installed - - A JTAG dongle is not included with the board itself. - -Follow these steps to: - -#. Get a toolchain and OpenOCD -#. Set up the board for booting RI5CY -#. Compile a Zephyr application for the RI5CY core -#. Flash the application to your board -#. Debug the board using GDB - -.. _rv32m1-toolchain-openocd: - -Get the Toolchain and OpenOCD -============================= - -Before programming and debugging, you first need to get a GNU -toolchain and an OpenOCD build. There are vendor-specific versions of -each for the RV32M1 SoC\ [#toolchain_openocd]_. - -Option 1 (Recommended): Prebuilt Toolchain and OpenOCD ------------------------------------------------------- - -The following prebuilt toolchains and OpenOCD archives are available -on the `OpenISA GitHub releases`_ page: - -- :file:`Toolchain_Linux.tar.gz` -- :file:`Toolchain_Mac.tar.gz` -- :file:`Toolchain_Windows.zip` - -Download and extract the archive for your system, then extract the -toolchain and OpenOCD archives inside. - -Linux:: - - tar xvzf Toolchain_Linux.tar.gz - tar xvzf openocd.tar.gz - tar xvzf riscv32-unknown-elf-gcc.tar.gz - mv openocd ~/rv32m1-openocd - mv riscv32-unknown-elf-gcc ~ - -macOS (unfortunately, the OpenISA 1.0.0 release's Mac -:file:`riscv32-unknown-elf-gcc.tar.gz` file doesn't expand into a -:file:`riscv32-unknown-elf-gcc` directory, so it has to be created):: - - tar xvzf Toolchain_Mac.tar.gz - tar xvzf openocd.tar.gz - mkdir riscv32-unknown-elf-gcc - mv riscv32-unknown-elf-gcc.tar.gz riscv32-unknown-elf-gcc - cd riscv32-unknown-elf-gcc/ - tar xvzf riscv32-unknown-elf-gcc.tar.gz - cd .. - mv openocd ~/rv32m1-openocd - mv riscv32-unknown-elf-gcc ~ - -Windows: - -#. Extract :file:`Toolchain_Windows.zip` in the file manager -#. Extract the :file:`openocd.zip` and :file:`riscv32-unknown-elf-gcc.zip` files - in the resulting :file:`Toolchain_Windows` folder -#. Move the extracted :file:`openocd` folder to :file:`C:\\rv32m1-openocd` -#. Move the extracted :file:`riscv32-unknown-elf-gcc` folder to - :file:`C:\\riscv32-unknown-elf-gcc` - -For simplicity, this guide assumes: - -- You put the extracted toolchain at :file:`~/riscv32-unknown-elf-gcc` - on macOS or Linux, and :file:`C:\\riscv32-unknown-elf-gcc` on - Windows. -- You put the extracted OpenOCD binary at :file:`~/rv32m1-openocd` on - macOS or Linux, and the OpenOCD folder into :file:`C:\\rv32m1-openocd` - on Windows. - -You can put them elsewhere, but be aware: - -- If you put the toolchain somewhere else, you will need to change - the ``CROSS_COMPILE`` value described below accordingly. -- If you put OpenOCD somewhere else, you will need to change the - OpenOCD path in the flashing and debugging instructions below. -- Don't use installation directories with spaces anywhere in the path; - this won't work with Zephyr's build system. - -Option 2: Building Toolchain and OpenOCD From Source ----------------------------------------------------- - -See :ref:`rv32m1_vega_toolchain_build`. - -.. _rv32m1-vega-jtag: - -JTAG Setup -========== - -This section describes how to connect to your board via the J-Link -debugger and adapter board. See the :ref:`above information -` for details on required hardware. - -#. Connect the J-Link debugger through the adapter board to the - VEGAboard as shown in the figure. - - .. figure:: rv32m1_vega_jtag.jpg - :align: center - :alt: RV32M1-VEGA - - VEGAboard connected properly to J-Link debugger. - VEGAboard connector J55 should be used. Pin 1 is on the bottom left. - -#. Power the VEGAboard via USB. The OpenSDA connector at the top left - is recommended for UART access. - -#. Make sure your J-Link is connected to your computer via USB. - -One-Time Board Setup For Booting RI5CY or ZERO-RISCY -==================================================== - -Next, you'll need to make sure your board boots the RI5CY or ZERO-RISCY core. -**You only need to do this once.** - -The RV32M1 SoC on the VEGAboard has multiple cores, any of which can -be selected as the boot core. Before flashing and debugging, you'll -first make sure you're booting the right core. - -**Linux and macOS**: - -.. note:: - - Linux users: to run these commands as a normal user, you will need - to install the `60-openocd.rules`_ udev rules file (usually by - placing it in :file:`/etc/udev/rules.d`, then unplugging and - plugging the J-Link in again via USB). - -.. note:: - - These Zephyr-specific instructions differ slightly from the - equivalent SDK ones. The Zephyr OpenOCD configuration file does not - run ``init``, so you have to do it yourself as explained below. - -1. In one terminal, use OpenOCD to connect to the board:: - - ~/rv32m1-openocd -f boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg - - The output should look like this: - - .. code-block:: console - - $ ~/rv32m1-openocd -f boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg - Open On-Chip Debugger 0.10.0+dev-00431-ge1ec3c7d (2018-10-31-07:29) - [...] - Info : Listening on port 3333 for gdb connections - Info : Listening on port 6666 for tcl connections - Info : Listening on port 4444 for telnet connections - -2. In another terminal, connect to OpenOCD's telnet server and execute - the ``init`` and ``ri5cy_boot`` commands **with the reset button on - the board (at top left) pressed down**:: - - $ telnet localhost 4444 - Trying 127.0.0.1... - Connected to localhost. - Escape character is '^]'. - Open On-Chip Debugger - > init - > ri5cy_boot - - To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with - ``zero_boot``. - - The reset button is at top left, as shown in the following figure. - - .. figure:: ri5cy_boot.jpg - :align: center - :alt: Reset button is pressed - - Now quit the telnet session in this terminal and exit OpenOCD in the - other terminal. - -3. Unplug your J-Link and VEGAboard, and plug them back in. - -**Windows**: - -In one cmd.exe prompt in the Zephyr directory:: - - C:\rv32m1-openocd\bin\openocd.exe rv32m1-openocd -f boards\riscv32\rv32m1_vega\support\openocd_rv32m1_vega_ri5cy.cfg - -In a telnet program of your choice: - -#. Connect to localhost port 4444 using telnet. -#. Run ``init`` and ``ri5cy_boot`` as shown above, with RESET held down. -#. Quit the OpenOCD and telnet sessions. -#. Unplug your J-Link and VEGAboard, and plug them back in. - - To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with - ``zero_boot``. - -Compiling a Program -=================== - -.. important:: - - These instructions assume you've set up a development system, - cloned the Zephyr repository, and installed Python dependencies as - described in the :ref:`getting_started`. - - You should also have already downloaded and installed the toolchain - and OpenOCD as described above in :ref:`rv32m1-toolchain-openocd`. - -The first step is to set up environment variables to point at your -toolchain and OpenOCD:: - - # Linux or macOS - export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile - export CROSS_COMPILE=~/riscv32-unknown-elf-gcc/bin/riscv32-unknown-elf- - - # Windows - set ZEPHYR_TOOLCHAIN_VARIANT=cross-compile - set CROSS_COMPILE=C:\riscv32-unknown-elf-gcc\bin\riscv32-unknown-elf- - -.. note:: - - The above only sets these variables for your current shell session. - You need to make sure this happens every time you use this board. - -Now let's compile the :ref:`hello_world` application. (You can try -others as well; see :ref:`samples-and-demos` for more.) - -.. We can't use zephyr-app-commands to provide build instructions - due to the below mentioned linker issue. - -Due to a toolchain `linker issue`_, you need to add an option setting -``CMAKE_REQUIRED_FLAGS`` when running CMake to generate a build system -(see :ref:`application` for information about Zephyr's build system). - -Linux and macOS (run this in a terminal from the Zephyr directory):: - - # Set up environment and create build directory: - source zephyr-env.sh - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :tool: cmake - :cd-into: - :board: rv32m1_vega_ri5cy - :gen-args: -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=/dev/null - :goals: build - -Windows (run this in a ``cmd`` prompt, from the Zephyr directory):: - - # Set up environment and create build directory - zephyr-env.cmd - cd samples\hello_world - mkdir build & cd build - - # Use CMake to generate a Ninja-based build system: - type NUL > empty.ld - cmake -GNinja -DBOARD=rv32m1_vega_ri5cy -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=%cd%\empty.ld .. - - # Build the sample - ninja - -Flashing -======== - -.. note:: - - Make sure you've done the :ref:`JTAG setup `, and - that the VEGAboard's top left USB connector is connected to your - computer too (for UART access). - -.. note:: - - Linux users: to run these commands as a normal user, you will need - to install the `60-openocd.rules`_ udev rules file (usually by - placing it in :file:`/etc/udev/rules.d`, then unplugging and - plugging the J-Link in again via USB). - -Make sure you've followed the above instructions to set up your board -and build a program first. - -Since you need to use a special OpenOCD, the easiest way to flash is -by using :ref:`west flash ` instead of ``ninja -flash`` like you might see with other Zephyr documentation. - -Run these commands from the build directory where you ran ``ninja`` in -the above section. - -Linux and macOS:: - - # Don't use "~/rv32m1-openocd". It won't work. - west flash --openocd=$HOME/rv32m1-openocd - -Windows:: - - west flash --openocd=C:\rv32m1-openocd\bin\openocd.exe - -If you have problems: - -- Make sure you don't have another ``openocd`` process running in the - background. -- Unplug the boards and plug them back in. -- On Linux, make sure udev rules are installed, as described above. - -As an alternative, for manual steps to run OpenOCD and GDB to flash, -see the `SDK README`_. - -Debugging -========= - -.. note:: - - Make sure you've done the :ref:`JTAG setup `, and - that the VEGAboard's top left USB connector is connected to your - computer too (for UART access). - -.. note:: - - Linux users: to run these commands as a normal user, you will need - to install the `60-openocd.rules`_ udev rules file (usually by - placing it in :file:`/etc/udev/rules.d`, then unplugging and - plugging the J-Link in again via USB). - -Make sure you've followed the above instructions to set up your board -and build a program first. - -To debug with gdb:: - - # Linux, macOS - west debug --openocd=$HOME/rv32m1-openocd - - # Windows - west debug --openocd=C:\rv32m1-openocd\bin\openocd.exe - -Then, from the ``(gdb)`` prompt, follow these steps to halt the core, -load the binary (:file:`zephyr.elf`), and re-sync with the OpenOCD -server:: - - (gdb) monitor init - (gdb) monitor reset halt - (gdb) load - (gdb) monitor gdb_sync - (gdb) stepi - -You can then set breakpoints and debug using normal GDB commands. - -.. note:: - - GDB can get out of sync with the target if you execute commands - that reset it. To reset RI5CY and get GDB back in sync with it - without reloading the binary:: - - (gdb) monitor reset halt - (gdb) monitor gdb_sync - (gdb) stepi - -If you have problems: - -- Make sure you don't have another ``openocd`` process running in the - background. -- Unplug the boards and plug them back in. -- On Linux, make sure udev rules are installed, as described above. - -References -********** - -- OpenISA developer portal: http://open-isa.org -- `OpenISA GitHub releases`_: includes toolchain and OpenOCD - prebuilts, as well as documentation, such as the SoC datasheet and - reference manual, board schematic and user guides, etc. -- Base toolchain: `pulp-riscv-gnu-toolchain`_; extra toolchain patches: - `rv32m1_gnu_toolchain_patch`_ (only needed if building from source). -- OpenOCD repository: `rv32m1-openocd`_ (only needed if building from - source). -- Vendor SDK: `rv32m1_sdk_riscv`_. Contains HALs, non-Zephyr sample - applications, and information on using the board with Eclipse which - may be interesting when combined with the Eclipse Debugging - information in the :ref:`application`. - -.. _rv32m1_vega_toolchain_build: - -Appendix: Building Toolchain and OpenOCD from Source -**************************************************** - -.. note:: - - Toolchain and OpenOCD build instructions are provided for Linux and - macOS only. - - Instructions for building OpenOCD have only been verified on Linux. - -.. warning:: - - Don't use installation directories with spaces anywhere in - the path; this won't work with Zephyr's build system. - -Ubuntu 18.04 users need to install these additional dependencies:: - - sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \ - libmpfr-dev libgmp-dev gawk build-essential bison \ - flex texinfo gperf libtool patchutils bc zlib1g-dev \ - libusb-1.0-0-dev libudev1 libudev-dev g++ - -Users of other Linux distributions need to install the above packages -with their system package manager. - -macOS users need to install dependencies with Homebrew:: - - brew install gawk gnu-sed gmp mpfr libmpc isl zlib - -The build toolchain is based on the `pulp-riscv-gnu-toolchain`_, with -some additional patches hosted in a separate repository, -`rv32m1_gnu_toolchain_patch`_. To build the toolchain, follow the -instructions in the ``rv32m1_gnu_toolchain_patch`` repository's -`readme.md`_ file to apply the patches, then run:: - - ./configure --prefix= --with-arch=rv32imc --with-cmodel=medlow --enable-multilib - make - -If you set ```` to -:file:`~/riscv32-unknown-elf-gcc`, you can use the above instructions -for setting ``CROSS_COMPILE`` when building Zephyr -applications. If you set it to something else, you will need to update -your ``CROSS_COMPILE`` setting accordingly. - -.. note:: - - Strangely, there is no separate ``make install`` step for the - toolchain. That is, the ``make`` invocation both builds and - installs the toolchain. This means ``make`` has to be run as root - if you want to set ``--prefix`` to a system directory such as - :file:`/usr/local` or :file:`/opt` on Linux. - -To build OpenOCD, clone the `rv32m1-openocd`_ repository, then run -these from the repository top level:: - - ./bootstrap - ./configure --prefix= - make - make install - -If ```` is :file:`~/rv32m1-openocd`, you -should set your OpenOCD path to :file:`~/rv32m1-openocd/bin/openocd` -in the above flash and debug instructions. - -.. _RI5CY: - https://github.com/pulp-platform/riscv -.. _ZERO-RISCY: - https://github.com/pulp-platform/zero-riscy -.. _PULP platform: - http://iis-projects.ee.ethz.ch/index.php/PULP - -.. _pulp-riscv-gnu-toolchain: - https://github.com/pulp-platform/pulp-riscv-gnu-toolchain -.. _rv32m1_gnu_toolchain_patch: - https://github.com/open-isa-rv32m1/rv32m1_gnu_toolchain_patch -.. _rv32m1-openocd: - https://github.com/open-isa-rv32m1/rv32m1-openocd -.. _readme.md: - https://github.com/open-isa-rv32m1/rv32m1_gnu_toolchain_patch/blob/master/readme.md -.. _OpenISA GitHub releases: - https://github.com/open-isa-org/open-isa.org/releases -.. _rv32m1_sdk_riscv: - https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv -.. _linker issue: - https://github.com/pulp-platform/pulpino/issues/240 -.. _60-openocd.rules: - https://github.com/open-isa-rv32m1/rv32m1-openocd/blob/master/contrib/60-openocd.rules -.. _SEGGER J-Link: - https://www.segger.com/products/debug-probes/j-link/ -.. _9-Pin Cortex-M Adapter: - https://www.segger.com/products/debug-probes/j-link/accessories/adapters/9-pin-cortex-m-adapter/ -.. _J-Link Software and Documentation Pack: - https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack -.. _SDK README: - https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv/blob/master/readme.md - -.. rubric:: Footnotes - -.. [#toolchain_openocd] - - For Linux users, the RISC-V toolchain in the :ref:`Zephyr SDK - ` may work, but it hasn't been thoroughly tested with this - SoC, and will not allow use of any available RISC-V ISA extensions. - - Support for the RV32M1 SoC is not currently available in the OpenOCD - upstream repository or the OpenOCD build in the Zephyr SDK. diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega.dtsi b/boards/riscv/rv32m1_vega/rv32m1_vega.dtsi deleted file mode 100644 index b416b0a4806..00000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright 2018 Foundries.io Ltd - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "rv32m1_vega-pinctrl.dtsi" -#include - -/ { - aliases { - led0 = &green_led; - led1 = &blue_led; - led2 = &red_led; - led3 = &sts_led; - pwm-led0 = &blue_pwm_led; - pwm-led1 = &green_pwm_led; - pwm-led2 = &red_pwm_led; - blue-pwm-led = &blue_pwm_led; - green-pwm-led = &green_pwm_led; - red-pwm-led = &red_pwm_led; - sw0 = &user_button_2; - sw1 = &user_button_3; - sw2 = &user_button_4; - sw3 = &user_button_5; - magn0 = &fxos8700; - accel0 = &fxos8700; - }; - - leds { - compatible = "gpio-leds"; - blue_led: led_0 { - gpios = <&gpioa 22 GPIO_ACTIVE_HIGH>; - label = "User LD1"; - }; - green_led: led_1 { - gpios = <&gpioa 23 GPIO_ACTIVE_HIGH>; - label = "User LD2"; - }; - red_led: led_2 { - gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>; - label = "User LD3"; - }; - sts_led: led_3 { - gpios = <&gpioe 0 GPIO_ACTIVE_HIGH>; - label = "User LD4"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - blue_pwm_led: pwm_led_0 { - pwms = <&tpm2 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "User PWM LD1"; - }; - green_pwm_led: pwm_led_1 { - pwms = <&tpm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "User PWM LD2"; - }; - red_pwm_led: pwm_led_2 { - pwms = <&tpm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "User PWM LD3"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_2: button_0 { - label = "User SW2"; - gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_3: button_1 { - label = "User SW3"; - gpios = <&gpioe 8 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_4: button_2 { - label = "User SW4"; - gpios = <&gpioe 9 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_5: button_3 { - label = "User SW5"; - gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 11 0>, /* A0 */ - <1 0 &gpioc 12 0>, /* A1 */ - <2 0 &gpiob 9 0>, /* A2 */ - <3 0 &gpioe 4 0>, /* A3 */ - <4 0 &gpioe 10 0>, /* A4 */ - <5 0 &gpioe 11 0>, /* A5 */ - <6 0 &gpioa 25 0>, /* D0 */ - <7 0 &gpioa 26 0>, /* D1 */ - <8 0 &gpioa 27 0>, /* D2 */ - <9 0 &gpiob 13 0>, /* D3 */ - <10 0 &gpiob 14 0>, /* D4 */ - <11 0 &gpioa 30 0>, /* D5 */ - <12 0 &gpioa 31 0>, /* D6 */ - <13 0 &gpiob 1 0>, /* D7 */ - <14 0 &gpiob 2 0>, /* D8 */ - <15 0 &gpiob 3 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpiob 7 0>, /* D12 */ - <19 0 &gpiob 4 0>, /* D13 */ - <20 0 &gpioc 9 0>, /* D14 */ - <21 0 &gpioc 10 0>; /* D15 */ - }; -}; - -arduino_serial: &lpuart1 { - pinctrl-0 = <&lpuart1_default>; - pinctrl-names = "default"; -}; - -&lpuart0 { - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&lpuart0_default>; - pinctrl-names = "default"; -}; - -arduino_i2c: &lpi2c0 { - status = "okay"; - pinctrl-0 = <&lpi2c0_default>; - pinctrl-names = "default"; -}; - -&lpi2c3 { - status = "okay"; - pinctrl-0 = <&lpi2c3_default>; - pinctrl-names = "default"; - - fxos8700: fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - reset-gpios = <&gpioe 27 GPIO_ACTIVE_HIGH>; - int1-gpios = <&gpioe 1 GPIO_ACTIVE_LOW>; - int2-gpios = <&gpioe 22 GPIO_ACTIVE_LOW>; - }; -}; - -arduino_spi: &lpspi0 { - status = "okay"; - pinctrl-0 = <&lpspi0_default>; - pinctrl-names = "default"; -}; - -&lpspi1 { - status = "okay"; - cs-gpios = <&gpiob 22 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&lpspi1_default>; - pinctrl-names = "default"; - - mx25r32: mx25r3235f@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - jedec-id = [c2 28 16]; - size = <33554432>; - }; -}; - -&tpm2 { - status = "okay"; - pinctrl-0 = <&tpm2_default>; - pinctrl-names = "default"; -}; diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.dts b/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.dts deleted file mode 100644 index fb68675989c..00000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2018 Foundries.io Ltd - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include "openisa/rv32m1_ri5cy.dtsi" -#include "rv32m1_vega.dtsi" - -/ { - model = "OpenISA RV32M1 Vega RI5CY"; - compatible = "openisa,rv32m1"; - - chosen { - zephyr,sram = &m4_dtcm; - zephyr,flash = &m4_flash; - zephyr,console = &lpuart0; - zephyr,shell-uart = &lpuart0; - zephyr,uart-pipe = &lpuart0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - spi-flash0 = &mx25r32; - }; -}; - -&m4_flash { - /* - * For more information, see: - * http://docs.zephyrproject.org/latest/guides/dts/index.html - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - slot0_partition: partition@0 { - label = "image-0"; - reg = <0x00000000 0x00069000>; - }; - slot1_partition: partition@69000 { - label = "image-1"; - reg = <0x00069000 0x00069000>; - }; - scratch_partition: partition@d2000 { - label = "image-scratch"; - reg = <0x000d2000 0x0001e000>; - }; - storage_partition: partition@f0000 { - label = "storage"; - reg = <0x000f0000 0x00004000>; - }; - boot_partition: partition@f4000 { - label = "mcuboot"; - reg = <0x000f4000 0x0000C000>; - }; - }; -}; diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.yaml b/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.yaml deleted file mode 100644 index cddd5e221e8..00000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: rv32m1_vega_ri5cy -name: RV32M1-VEGA (RI5CY) -type: mcu -arch: riscv -toolchain: - - cross-compile - - zephyr -supported: - - arduino_gpio - - arduino_i2c - - arduino_spi - - i2c - - pwm - - spi -vendor: openisa diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy_defconfig b/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy_defconfig deleted file mode 100644 index 51071efb902..00000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_OPENISA_RV32M1_RISCV32=y -CONFIG_SOC_OPENISA_RV32M1_RI5CY=y -CONFIG_BOARD_RV32M1_VEGA=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_MULTI_LEVEL_INTERRUPTS=y diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts b/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts deleted file mode 100644 index c59d7bd9b76..00000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2018 Foundries.io Ltd - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include "openisa/rv32m1_zero_riscy.dtsi" -#include "rv32m1_vega.dtsi" - -/ { - model = "OpenISA RV32M1 Vega Zero RISCY"; - compatible = "openisa,rv32m1"; - - chosen { - zephyr,sram = &m0_tcm; - zephyr,flash = &m0_flash; - zephyr,console = &lpuart0; - zephyr,uart-pipe = &lpuart0; - zephyr,code-partition = &zero_riscy_code_partition; - }; -}; diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.yaml b/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.yaml deleted file mode 100644 index 3ca9ac8c9e7..00000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: rv32m1_vega_zero_riscy -name: RV32M1-VEGA (ZERO-RISCY) -type: mcu -arch: riscv -toolchain: - - cross-compile - - zephyr -supported: - - arduino_gpio - - arduino_i2c - - i2c - - pwm -vendor: openisa diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig b/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig deleted file mode 100644 index 627ed311846..00000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_SOC_OPENISA_RV32M1_RISCV32=y -CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY=y -CONFIG_BOARD_RV32M1_VEGA=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_MULTI_LEVEL_INTERRUPTS=y diff --git a/boards/riscv/sparkfun_red_v_things_plus/Kconfig.board b/boards/riscv/sparkfun_red_v_things_plus/Kconfig.board deleted file mode 100644 index cc9e7b4f935..00000000000 --- a/boards/riscv/sparkfun_red_v_things_plus/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SPARKFUN_RED_V_THINGS_PLUS - bool "SparkFun RED-V Things Plus board" - depends on SOC_SIFIVE_FREEDOM_E340 diff --git a/boards/riscv/sparkfun_red_v_things_plus/Kconfig.defconfig b/boards/riscv/sparkfun_red_v_things_plus/Kconfig.defconfig deleted file mode 100644 index e505db59222..00000000000 --- a/boards/riscv/sparkfun_red_v_things_plus/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SPARKFUN_RED_V_THINGS_PLUS - -config BOARD - default "sparkfun_red_v_things_plus" - -config HAS_FLASH_LOAD_OFFSET - default y - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/spi@10014000,1) - -config FLASH_LOAD_OFFSET - default 0x0 - -config SYS_CLOCK_TICKS_PER_SEC - default 128 - -endif diff --git a/boards/riscv/sparkfun_red_v_things_plus/board.cmake b/boards/riscv/sparkfun_red_v_things_plus/board.cmake deleted file mode 100644 index f339e968e86..00000000000 --- a/boards/riscv/sparkfun_red_v_things_plus/board.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2019 SiFive Inc. -# SPDX-License-Identifier: Apache-2.0 -board_runner_args(jlink "--device=FE310") -board_runner_args(jlink "--iface=JTAG") -board_runner_args(jlink "--speed=4000") -board_runner_args(jlink "--tool-opt=-jtagconf -1,-1") -board_runner_args(jlink "--tool-opt=-autoconnect 1") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus_defconfig b/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus_defconfig deleted file mode 100644 index 8cf24ffbe09..00000000000 --- a/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_E300=y -CONFIG_SOC_SIFIVE_FREEDOM_E340=y -CONFIG_BOARD_SPARKFUN_RED_V_THINGS_PLUS=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_RISCV_CORE_E31=y -CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/riscv/stamp_c3/Kconfig.board b/boards/riscv/stamp_c3/Kconfig.board deleted file mode 100644 index 09ec15d6348..00000000000 --- a/boards/riscv/stamp_c3/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5Stack STAMP-C3 board configuration - -# Copyright 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STAMP_C3 - bool "M5Stack STAMP-C3 Board" - depends on SOC_SERIES_ESP32C3 - -choice SOC_PART_NUMBER - default SOC_ESP32C3_FX4 -endchoice diff --git a/boards/riscv/stamp_c3/Kconfig.defconfig b/boards/riscv/stamp_c3/Kconfig.defconfig deleted file mode 100644 index 911a8845d70..00000000000 --- a/boards/riscv/stamp_c3/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# M5Stack STAMP-C3 board configuration - -# Copyright 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "stamp_c3" - depends on BOARD_STAMP_C3 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -if BT - -choice BT_HCI_BUS_TYPE - default BT_ESP32 -endchoice - -endif # BT diff --git a/boards/riscv/stamp_c3/doc/index.rst b/boards/riscv/stamp_c3/doc/index.rst deleted file mode 100644 index 8da74e9e1d8..00000000000 --- a/boards/riscv/stamp_c3/doc/index.rst +++ /dev/null @@ -1,205 +0,0 @@ -.. _stamp_c3: - -M5Stack STAMP-C3 -################## - -Overview -******** - -STAMP-C3 featuring ESPRESSIF ESP32-C3 RISC-V MCU with Wi-Fi connectivity -for IoT edge devices such as home appliances and Industrial Automation. - -For more details see the `M5Stack STAMP-C3`_ page. - -Supported Features -================== - -The STAMP-C3 board configuration supports the following hardware features: - -+-----------+------------+------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==================+ -| PMP | on-chip | arch/riscv | -+-----------+------------+------------------+ -| INTMTRX | on-chip | intc_esp32c3 | -+-----------+------------+------------------+ -| PINMUX | on-chip | pinctrl_esp32 | -+-----------+------------+------------------+ -| USB UART | on-chip | serial_esp32_usb | -+-----------+------------+------------------+ -| GPIO | on-chip | gpio_esp32 | -+-----------+------------+------------------+ -| UART | on-chip | uart_esp32 | -+-----------+------------+------------------+ -| I2C | on-chip | i2c_esp32 | -+-----------+------------+------------------+ -| SPI | on-chip | spi_esp32_spim | -+-----------+------------+------------------+ -| TWAI | on-chip | can_esp32_twai | -+-----------+------------+------------------+ - - -Prerequisites -************* - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: stamp_c3 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stamp_c3 - :goals: build - -The usual ``flash`` target will work with the ``stamp_c3`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stamp_c3 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! stamp_c3 - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stamp_c3 - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stamp_c3 - :goals: debug - -References -********** - -.. target-notes:: - -.. _`M5Stack STAMP-C3`: https://docs.m5stack.com/en/core/stamp_c3 -.. _`ESP32C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf -.. _`ESP32C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/riscv/stamp_c3/stamp_c3_defconfig b/boards/riscv/stamp_c3/stamp_c3_defconfig deleted file mode 100644 index 021a4e84162..00000000000 --- a/boards/riscv/stamp_c3/stamp_c3_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_STAMP_C3=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/riscv/titanium_ti60_f225/Kconfig.board b/boards/riscv/titanium_ti60_f225/Kconfig.board deleted file mode 100644 index bac70816b20..00000000000 --- a/boards/riscv/titanium_ti60_f225/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Efinix Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_TITANIUM_TI60_F225 - bool "Board with Efinix Sapphire riscv SoC" - depends on SOC_EFINIX_SAPPHIRE diff --git a/boards/riscv/titanium_ti60_f225/Kconfig.defconfig b/boards/riscv/titanium_ti60_f225/Kconfig.defconfig deleted file mode 100644 index 577c21b3d1a..00000000000 --- a/boards/riscv/titanium_ti60_f225/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Efinix Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_TITANIUM_TI60_F225 - -config BOARD - default "titanium_ti60_f225" - -endif # BOARD_TITANIUM_TI60_F225 diff --git a/boards/riscv/tlsr9518adk80d/Kconfig.board b/boards/riscv/tlsr9518adk80d/Kconfig.board deleted file mode 100644 index 971b34dc13b..00000000000 --- a/boards/riscv/tlsr9518adk80d/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_TLSR9518ADK80D - bool "Telink B91 Platform" - depends on SOC_TELINK_TLSR9518 diff --git a/boards/riscv/tlsr9518adk80d/Kconfig.defconfig b/boards/riscv/tlsr9518adk80d/Kconfig.defconfig deleted file mode 100644 index ce11f3aaabe..00000000000 --- a/boards/riscv/tlsr9518adk80d/Kconfig.defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_TLSR9518ADK80D - -config BOARD - default "tlsr9518adk80d" - -config SOC_FLASH_TELINK_B91 - default y if FLASH - -if BT - -# BLE Controller SDK from hal_telink requires -# Telink's toolchain with FPU support -config FPU - default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" - -config BT_HCI_ACL_FLOW_CONTROL - default n - -choice BT_HCI_BUS_TYPE - default BT_B91 -endchoice - -endif # BT - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_DT_CODE_PARTITION - -# Buffer for image writter shall be less(multiple of access alignment) or -# equal to flash page. tlsr9518adk80d boards use external P25Q16 IC as -# flesh memory. Flash page size of the IC is 256 bytes. So that, it is -# maximum image writer buffer size for such kind of boards. -config IMG_BLOCK_BUF_SIZE - default 256 if MCUBOOT_IMG_MANAGER - -endif diff --git a/boards/riscv/tlsr9518adk80d/doc/index.rst b/boards/riscv/tlsr9518adk80d/doc/index.rst deleted file mode 100644 index 4bf62efdf78..00000000000 --- a/boards/riscv/tlsr9518adk80d/doc/index.rst +++ /dev/null @@ -1,267 +0,0 @@ -.. _tlsr9518adk80d: - -Telink TLSR9518ADK80D -##################### - -Overview -******** - -The TLSR9518A Generic Starter Kit is a hardware platform which -can be used to verify the `Telink TLSR951x series chipset`_ and develop applications -for several 2.4 GHz air interface standards including Bluetooth 5.2 (Basic data -rate, Enhanced data rate, LE, Indoor positioning and BLE Mesh), -Zigbee 3.0, Homekit, 6LoWPAN, Thread and 2.4 Ghz proprietary. - -.. figure:: img/tlsr9518adk80d.jpg - :align: center - :alt: TLSR9518ADK80D - -More information about the board can be found at the `Telink B91 Generic Starter Kit Hardware Guide`_ website. - -Hardware -******** - -The TLSR9518A SoC integrates a powerful 32-bit RISC-V MCU, DSP, AI Engine, 2.4 GHz ISM Radio, 256 -KB SRAM (128 KB of Data Local Memory and 128 KB of Instruction Local Memory), external Flash memory, -stereo audio codec, 14 bit AUX ADC, analog and digital Microphone input, PWM, flexible IO interfaces, -and other peripheral blocks required for advanced IoT, hearable, and wearable devices. - -.. figure:: img/tlsr9518_block_diagram.jpg - :align: center - :alt: TLSR9518ADK80D_SOC - -The TLSR9518ADK80D default board configuration provides the following hardware components: - -- RF conducted antenna -- 1 MB External Flash memory with reset button -- Chip reset button -- Mini USB interface -- 4-wire JTAG -- 4 LEDs, Key matrix up to 4 keys -- 2 line-in function (Dual Analog microphone supported when switching jumper from microphone path) -- Dual Digital microphone -- Stereo line-out - -Supported Features -================== - -The Zephyr TLSR9518ADK80D board configuration supports the following hardware features: - -+----------------+------------+------------------------------+ -| Interface | Controller | Driver/Component | -+================+============+==============================+ -| PLIC | on-chip | interrupt_controller | -+----------------+------------+------------------------------+ -| RISC-V Machine | on-chip | timer | -| Timer (32 KHz) | | | -+----------------+------------+------------------------------+ -| PINCTRL | on-chip | pinctrl | -+----------------+------------+------------------------------+ -| GPIO | on-chip | gpio | -+----------------+------------+------------------------------+ -| UART | on-chip | serial | -+----------------+------------+------------------------------+ -| PWM | on-chip | pwm | -+----------------+------------+------------------------------+ -| TRNG | on-chip | entropy | -+----------------+------------+------------------------------+ -| FLASH (MSPI) | on-chip | flash | -+----------------+------------+------------------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154, OpenThread | -+----------------+------------+------------------------------+ -| SPI (Master) | on-chip | spi | -+----------------+------------+------------------------------+ -| I2C (Master) | on-chip | i2c | -+----------------+------------+------------------------------+ -| ADC | on-chip | adc | -+----------------+------------+------------------------------+ - -.. note:: - To support "button" example project PC3-KEY3 (J20-19, J20-20) jumper needs to be removed and KEY3 (J20-19) should be connected to VDD3_DCDC (J51-13) externally. - - For the rest example projects use the default jumpers configuration. - -Other hardware features and example projects are not supported yet. - -Limitations ------------ - -- Maximum 3 GPIO pins could be configured to generate interrupts simultaneously. All pins must be related to different ports and use different IRQ numbers. -- DMA mode is not supported by I2C, SPI and Serial Port. -- UART hardware flow control is not implemented. -- SPI Slave mode is not implemented. -- I2C Slave mode is not implemented. - -Default configuration and IOs -============================= - -System Clock ------------- - -The TLSR9518ADK80D board is configured to use the 24 MHz external crystal oscillator -with the on-chip PLL/DIV generating the 48 MHz system clock. -The following values also could be assigned to the system clock in the board DTS file -(``boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts``): - -- 16000000 -- 24000000 -- 32000000 -- 48000000 -- 64000000 -- 96000000 - -.. code-block:: - - &cpu0 { - clock-frequency = <48000000>; - }; - -PINs Configuration ------------------- - -The TLSR9518A SoC has five GPIO controllers (PORT_A to PORT_E), but only two are -currently enabled (PORT_B for LEDs control and PORT_C for buttons) in the board DTS file: - -- LED0 (blue): PB4, LED1 (green): PB5, LED2 (white): PB6, LED3 (red): PB7 -- Key Matrix SW0: PC2_PC3, SW1: PC2_PC1, SW2: PC0_PC3, SW3: PC0_PC1 - -Peripheral's pins on the SoC are mapped to the following GPIO pins in the -``boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts`` file: - -- UART0 TX: PB2, RX: PB3 -- UART1 TX: PC6, RX: PC7 -- PWM Channel 0: PB4 -- PSPI CS0: PC4, CLK: PC5, MISO: PC6, MOSI: PC7 -- HSPI CS0: PA1, CLK: PA2, MISO: PA3, MOSI: PA4 -- I2C SCL: PE1, SDA: PE3 - -Serial Port ------------ - -The TLSR9518A SoC has 2 UARTs. The Zephyr console output is assigned to UART0. -The default settings are 115200 8N1. - -Programming and debugging -************************* - -Building -======== - -.. important:: - - These instructions assume you've set up a development environment as - described in the :ref:`getting_started`. - -To build applications using the default RISC-V toolchain from Zephyr SDK, just run the west build command. -Here is an example for the "hello_world" application. - -.. code-block:: console - - # From the root of the zephyr repository - west build -b tlsr9518adk80d samples/hello_world - -To use `Telink RISC-V Linux Toolchain`_, ``ZEPHYR_TOOLCHAIN_VARIANT`` and ``CROSS_COMPILE`` variables need to be set. -In addition ``CONFIG_FPU=y`` must be selected in ``boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig`` file since this -toolchain is compatible only with the float point unit usage. - -.. code-block:: console - - # Set Zephyr toolchain variant to cross-compile - export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile - # Specify the Telink RISC-V Toolchain location - export CROSS_COMPILE=~/toolchains/nds32le-elf-mculib-v5f/bin/riscv32-elf- - # From the root of the zephyr repository - west build -b tlsr9518adk80d samples/hello_world - -`Telink RISC-V Linux Toolchain`_ is available on the `Burning and Debugging Tools for TLSR9 Series in Linux`_ page. - -Open a serial terminal with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flash the board, reset and observe the following messages on the selected -serial port: - -.. code-block:: console - - *** Booting Zephyr OS version 2.5.0 *** - Hello World! tlsr9518adk80d - - -Flashing -======== - -To flash the TLSR9518ADK80D board see the sources below: - -- `Burning and Debugging Tools for all Series`_ -- `Burning and Debugging Tools for TLSR9 Series`_ -- `Burning and Debugging Tools for TLSR9 Series in Linux`_ - -It is also possible to use the west flash command, but additional steps are required to set it up: - -- Download `Telink RISC-V Linux Toolchain`_. The toolchain contains tools for the board flashing as well. -- Since the ICEman tool is created for the 32-bit OS version it is necessary to install additional packages in case of the 64-bit OS version. - -.. code-block:: console - - sudo dpkg --add-architecture i386 - sudo apt-get update - sudo apt-get install -y libc6:i386 libncurses5:i386 libstdc++6:i386 - -- Run the "ICEman.sh" script. - -.. code-block:: console - - # From the root of the {path to the Telink RISC-V Linux Toolchain}/ice repository - sudo ./ICEman.sh - -- Now you should be able to run the west flash command with the toolchain path specified (TELINK_TOOLCHAIN_PATH). - -.. code-block:: console - - west flash --telink-tools-path=$TELINK_TOOLCHAIN_PATH - -- You can also run the west flash command without toolchain path specification if add SPI_burn and ICEman to PATH. - -.. code-block:: console - - export PATH=$TELINK_TOOLCHAIN_PATH/flash/bin:"$PATH" - export PATH=$TELINK_TOOLCHAIN_PATH/ice:"$PATH" - -Debugging -========= - -This port supports UART debug and OpenOCD+GDB. The `west debug` command also supported. You may run -it in a simple way, like: - -.. code-block:: console - - west debug - -Or with additional arguments, like: - -.. code-block:: console - - west debug --gdb-port= --gdb-ex= - -Example: - -.. code-block:: console - - west debug --gdb-port=1111 --gdb-ex="-ex monitor reset halt -ex b main -ex continue" - -References -********** - -.. target-notes:: - -.. _Telink TLSR951x series chipset: https://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/ -.. _Telink B91 Generic Starter Kit Hardware Guide: https://wiki.telink-semi.cn/wiki/Hardware/B91_Generic_Starter_Kit_Hardware_Guide/ -.. _Telink RISC-V Linux Toolchain: https://wiki.telink-semi.cn/tools_and_sdk/Tools/IDE/telink_riscv_linux_toolchain.zip -.. _Burning and Debugging Tools for all Series: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/Burning-and-Debugging-Tools-for-all-Series/ -.. _Burning and Debugging Tools for TLSR9 Series: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/Burning-and-Debugging-Tools-for-TLSR9-Series/ -.. _Burning and Debugging Tools for TLSR9 Series in Linux: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/BDT_for_TLSR9_Series_in_Linux/ diff --git a/boards/riscv/xiao_esp32c3/Kconfig.board b/boards/riscv/xiao_esp32c3/Kconfig.board deleted file mode 100644 index f8a7e0ecb5b..00000000000 --- a/boards/riscv/xiao_esp32c3/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2022 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_XIAO_ESP32C3 - bool "XIAO ESP32C3 Board" - depends on SOC_SERIES_ESP32C3 - -choice SOC_PART_NUMBER - default SOC_ESP32C3_FX4 -endchoice diff --git a/boards/riscv/xiao_esp32c3/Kconfig.defconfig b/boards/riscv/xiao_esp32c3/Kconfig.defconfig deleted file mode 100644 index 2852d11301d..00000000000 --- a/boards/riscv/xiao_esp32c3/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2022 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "xiao_esp32c3" - depends on BOARD_XIAO_ESP32C3 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/riscv/xiao_esp32c3/doc/index.rst b/boards/riscv/xiao_esp32c3/doc/index.rst deleted file mode 100644 index 18c56c3ff9b..00000000000 --- a/boards/riscv/xiao_esp32c3/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ -.. _xiao_esp32c3: - -XIAO ESP32C3 -############ - -Overview -******** - -Seeed Studio XIAO ESP32C3 is an IoT mini development board based on the -Espressif ESP32-C3 WiFi/Bluetooth dual-mode chip. - -For more details see the `Seeed Studio XIAO ESP32C3`_ wiki page. - -.. figure:: img/xiao_esp32c.jpg - :align: center - :alt: XIAO ESP32C3 - - XIAO ESP32C3 - -Hardware -******** - -This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It -has an USB-C port for programming and debugging, integrated battery charging -and an U.FL external antenna connector. It is based on a standard XIAO 14 pin -pinout. - -Supported Features -================== - -The XIAO ESP32C3 board configuration supports the following hardware features: - -+-----------+------------+------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==================+ -| PMP | on-chip | arch/riscv | -+-----------+------------+------------------+ -| INTMTRX | on-chip | intc_esp32c3 | -+-----------+------------+------------------+ -| PINMUX | on-chip | pinctrl_esp32 | -+-----------+------------+------------------+ -| USB UART | on-chip | serial_esp32_usb | -+-----------+------------+------------------+ -| GPIO | on-chip | gpio_esp32 | -+-----------+------------+------------------+ -| UART | on-chip | uart_esp32 | -+-----------+------------+------------------+ -| I2C | on-chip | i2c_esp32 | -+-----------+------------+------------------+ -| SPI | on-chip | spi_esp32_spim | -+-----------+------------+------------------+ -| TWAI | on-chip | can_esp32_twai | -+-----------+------------+------------------+ - -Connections and IOs -=================== - -The board uses a standard XIAO pinout, the default pin mapping is the following: - -.. figure:: img/xiao_esp32c3_pinout.jpg - :align: center - :alt: XIAO ESP32C3 Pinout - - XIAO ESP32C3 Pinout - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: xiao_esp32c3 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by Sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -For the :code:`Hello, world!` application, follow the instructions below. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32c3 - :goals: build flash - -Since the Zephyr console is by default on the `usb_serial` device, we use -the espressif monitor to view. - -.. code-block:: console - - $ west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! xiao_esp32c3 - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32c3 - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32c3 - :goals: debug - -References -********** - -.. target-notes:: - -.. _`Seeed Studio XIAO ESP32C3`: https://wiki.seeedstudio.com/XIAO_ESP32C3_Getting_Started -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/riscv/xiao_esp32c3/xiao_esp32c3_defconfig b/boards/riscv/xiao_esp32c3/xiao_esp32c3_defconfig deleted file mode 100644 index 0dc868fa60a..00000000000 --- a/boards/riscv/xiao_esp32c3/xiao_esp32c3_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_XIAO_ESP32C3=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/ronoth/index.rst b/boards/ronoth/index.rst new file mode 100644 index 00000000000..2c41a8c379c --- /dev/null +++ b/boards/ronoth/index.rst @@ -0,0 +1,10 @@ +.. _boards-ronoth: + +Ronoth +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/ronoth/lodev/Kconfig.defconfig b/boards/ronoth/lodev/Kconfig.defconfig new file mode 100644 index 00000000000..23abc27cc1e --- /dev/null +++ b/boards/ronoth/lodev/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Ronoth LoDev board configuration +# Copyright (c) 2020/2021 Dean Weiten +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RONOTH_LODEV + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_RONOTH_LODEV diff --git a/boards/ronoth/lodev/Kconfig.ronoth_lodev b/boards/ronoth/lodev/Kconfig.ronoth_lodev new file mode 100644 index 00000000000..a8f323fb3c9 --- /dev/null +++ b/boards/ronoth/lodev/Kconfig.ronoth_lodev @@ -0,0 +1,5 @@ +# Copyright (c) 2020/2021 Dean Weiten +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RONOTH_LODEV + select SOC_STM32L073XX diff --git a/boards/arm/ronoth_lodev/board.cmake b/boards/ronoth/lodev/board.cmake similarity index 100% rename from boards/arm/ronoth_lodev/board.cmake rename to boards/ronoth/lodev/board.cmake diff --git a/boards/ronoth/lodev/board.yml b/boards/ronoth/lodev/board.yml new file mode 100644 index 00000000000..008f2e5a7f5 --- /dev/null +++ b/boards/ronoth/lodev/board.yml @@ -0,0 +1,5 @@ +board: + name: ronoth_lodev + vendor: ronoth + socs: + - name: stm32l073xx diff --git a/boards/arm/ronoth_lodev/doc/img/acsip_s76s.jpg b/boards/ronoth/lodev/doc/img/acsip_s76s.jpg similarity index 100% rename from boards/arm/ronoth_lodev/doc/img/acsip_s76s.jpg rename to boards/ronoth/lodev/doc/img/acsip_s76s.jpg diff --git a/boards/arm/ronoth_lodev/doc/img/lodev.jpg b/boards/ronoth/lodev/doc/img/lodev.jpg similarity index 100% rename from boards/arm/ronoth_lodev/doc/img/lodev.jpg rename to boards/ronoth/lodev/doc/img/lodev.jpg diff --git a/boards/arm/ronoth_lodev/doc/img/pinout.jpg b/boards/ronoth/lodev/doc/img/pinout.jpg similarity index 100% rename from boards/arm/ronoth_lodev/doc/img/pinout.jpg rename to boards/ronoth/lodev/doc/img/pinout.jpg diff --git a/boards/arm/ronoth_lodev/doc/index.rst b/boards/ronoth/lodev/doc/index.rst similarity index 100% rename from boards/arm/ronoth_lodev/doc/index.rst rename to boards/ronoth/lodev/doc/index.rst diff --git a/boards/arm/ronoth_lodev/doc/s76s.rst b/boards/ronoth/lodev/doc/s76s.rst similarity index 100% rename from boards/arm/ronoth_lodev/doc/s76s.rst rename to boards/ronoth/lodev/doc/s76s.rst diff --git a/boards/arm/ronoth_lodev/ronoth_lodev.dts b/boards/ronoth/lodev/ronoth_lodev.dts similarity index 100% rename from boards/arm/ronoth_lodev/ronoth_lodev.dts rename to boards/ronoth/lodev/ronoth_lodev.dts diff --git a/boards/arm/ronoth_lodev/ronoth_lodev.yaml b/boards/ronoth/lodev/ronoth_lodev.yaml similarity index 100% rename from boards/arm/ronoth_lodev/ronoth_lodev.yaml rename to boards/ronoth/lodev/ronoth_lodev.yaml diff --git a/boards/arm/ronoth_lodev/ronoth_lodev_defconfig b/boards/ronoth/lodev/ronoth_lodev_defconfig similarity index 77% rename from boards/arm/ronoth_lodev/ronoth_lodev_defconfig rename to boards/ronoth/lodev/ronoth_lodev_defconfig index 1e4ef45671f..ccccd7ca20f 100644 --- a/boards/arm/ronoth_lodev/ronoth_lodev_defconfig +++ b/boards/ronoth/lodev/ronoth_lodev_defconfig @@ -2,12 +2,6 @@ # Copyright (c) 2021 Dean Weiten # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L073XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/ruuvi/index.rst b/boards/ruuvi/index.rst new file mode 100644 index 00000000000..1ef2779b565 --- /dev/null +++ b/boards/ruuvi/index.rst @@ -0,0 +1,10 @@ +.. _boards-ruuvi: + +Ruuvi +##### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/ruuvi_ruuvitag/Kconfig b/boards/ruuvi/ruuvitag/Kconfig similarity index 100% rename from boards/arm/ruuvi_ruuvitag/Kconfig rename to boards/ruuvi/ruuvitag/Kconfig diff --git a/boards/ruuvi/ruuvitag/Kconfig.defconfig b/boards/ruuvi/ruuvitag/Kconfig.defconfig new file mode 100644 index 00000000000..237d564c746 --- /dev/null +++ b/boards/ruuvi/ruuvitag/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Ruuvi RuuviTag configuration + +# Copyright (c) 2020 Ruuvi Innovations Ltd (Oy) +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RUUVI_RUUVITAG + +config SPI + default y + +config BT_CTLR + default BT + +endif # BOARD_RUUVI_RUUVITAG diff --git a/boards/ruuvi/ruuvitag/Kconfig.ruuvi_ruuvitag b/boards/ruuvi/ruuvitag/Kconfig.ruuvi_ruuvitag new file mode 100644 index 00000000000..29d7dfc5190 --- /dev/null +++ b/boards/ruuvi/ruuvitag/Kconfig.ruuvi_ruuvitag @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Ruuvi Innovations Ltd (Oy) +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RUUVI_RUUVITAG + select SOC_NRF52832_QFAA diff --git a/boards/arm/ruuvi_ruuvitag/board.cmake b/boards/ruuvi/ruuvitag/board.cmake similarity index 100% rename from boards/arm/ruuvi_ruuvitag/board.cmake rename to boards/ruuvi/ruuvitag/board.cmake diff --git a/boards/ruuvi/ruuvitag/board.yml b/boards/ruuvi/ruuvitag/board.yml new file mode 100644 index 00000000000..c8d45886d82 --- /dev/null +++ b/boards/ruuvi/ruuvitag/board.yml @@ -0,0 +1,5 @@ +board: + name: ruuvi_ruuvitag + vendor: ruuvi + socs: + - name: nrf52832 diff --git a/boards/arm/ruuvi_ruuvitag/doc/img/pinout.jpg b/boards/ruuvi/ruuvitag/doc/img/pinout.jpg similarity index 100% rename from boards/arm/ruuvi_ruuvitag/doc/img/pinout.jpg rename to boards/ruuvi/ruuvitag/doc/img/pinout.jpg diff --git a/boards/arm/ruuvi_ruuvitag/doc/img/ruuvitag.jpg b/boards/ruuvi/ruuvitag/doc/img/ruuvitag.jpg similarity index 100% rename from boards/arm/ruuvi_ruuvitag/doc/img/ruuvitag.jpg rename to boards/ruuvi/ruuvitag/doc/img/ruuvitag.jpg diff --git a/boards/ruuvi/ruuvitag/doc/index.rst b/boards/ruuvi/ruuvitag/doc/index.rst new file mode 100644 index 00000000000..42348b8a387 --- /dev/null +++ b/boards/ruuvi/ruuvitag/doc/index.rst @@ -0,0 +1,184 @@ +.. _ruuvi_ruuvitag: + +Ruuvi RuuviTag +############## + +Overview +******** + +RuuviTag is an advanced battery-operated open-source Bluetooth +enabled sensor beacon platform capable of sending temperature, humidity, +pressure, and motion information over Bluetooth Low Energy. + +.. figure:: img/ruuvitag.jpg + :align: center + :alt: RUUVI RuuviTag + + RUUVI RuuviTag (Credit: https://ruuvi.com/) + +More information about the board can be found at the +`ruuvitag website`_. + +Hardware +******** + +RuuviTag's have the following physical features: + +* Nordic Semiconductor nRF52832 System-on-Chip +* STMicroelectronics LIS2DH12 accelerometer +* Bosch BME 280 temperature + relative air humidity + air pressure sensor +* NFC™-A tag antenna +* 1000mAh CR2477 battery +* 2 buttons +* 1 Green LED +* 1 Red LED +* IP67 Enclosure +* Long range RF antenna + +Supported Features +================== + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| Humidity, | on-board | bme280 | +| Temp & Air| | | +| Pressure | | | ++-----------+------------+----------------------+ +| Acc | on-board | lis2dh12 | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.17 +* LED1 (green) = P0.19 + +Push buttons +------------ + +* BUTTON0 = SW1 = P0.13 + +Pin descriptions +---------------- + +.. figure:: img/pinout.jpg + :align: center + :alt: RUUVI Pinout + +* 2 = P0.29 = SPI_SCK +* 3 = P0.28 = SPI_MISO +* 10 = P0.04 = GPIO (can be used as a GPIO / ADC pin) +* 11 = P0.05 = GPIO (can be used as a GPIO / ADC pin) +* 12 = P0.25 = SPI_MOSI +* 13 = P0.19 = LED2 (green) / GPIO (can be used as a GPIO pin but the LED will blink) +* 14 = P0.17 = LED1 (red) / GPIO (can be used as a GPIO pin but the LED will blink) +* 15 = P0.13 = Button / GPIO (can be used as a GPIO pin) +* 16 = GND (Battery's negative contact) +* 17 = Battery's positive contact +* 18 = Battery's positive contact +* 19 = SWDIO +* 20 = SWDCLK +* 21 = P0.18 = SWO / GPIO (can be used as a GPIO pin) +* 22 = P0.21 = Reset / GPIO (can be used as a GPIO pin if no need to reset the device) +* 23 = GND (Battery's negative contact) +* 24 = P0.31 = GPIO (can be used as a GPIO / ADC pin) +* 25 = P0.30 = GPIO (can be used as a GPIO / ADC pin) + +GPIO = General Purpose Input Output pin + +P1 = Standard 10-pin ARM Cortex debug connector (on RuuviTag Rev.B1-B5) + +* 1 = VDD +* 2 = SWDIO +* 3 = GND (Battery's negative contact) +* 4 = SWDCLK +* 5 = GND (Battery's negative contact) +* 6 = SWO +* 7 = No Connect +* 8 = No Connect +* 9 = GND (Battery's negative contact) +* 10 = Reset + +P1 = TC2030 TagConnect (on RuuviTag Rev.B6) + +* 1 = Battery's positive contact +* 2 = SWDIO +* 3 = Reset +* 4 = SWDCLK +* 5 = GND (Battery's negative contact) +* 6 = SWO + + +Programming and Debugging +************************* + +Flashing +======== + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +The easiest way to flash Zephyr onto a RuuviTag requires an external Ruuvi DEVKIT. More information about the board can be found at the +`ruuvitag devkit`_. + +Once your tag is connected to the DEVKIT and connected to your PC, build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ruuvi_ruuvitag + :goals: build flash + +Advanced users may want to program the RuuviTag without the DEVKIT, this can be achieved via the SWDIO and SWDCLK pins located on the back of the RuuviTag. + +Debugging +========= + +If using the Ruuvi DEVKIT refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +Testing the LEDs and buttons on the RuuviTag +******************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in :file:`boards/ruuvi//ruuvi_ruuvitag/ruuvi_ruuvitag.dts`. + +References +********** + +.. target-notes:: + +.. _ruuvitag website: https://ruuvi.com +.. _ruuvitag datasheet: https://ruuvi.com/files/ruuvitag-tech-spec-2019-7.pdf +.. _ruuvitag devkit: https://lab.ruuvi.com/devshield/ diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/pre_dt_board.cmake b/boards/ruuvi/ruuvitag/pre_dt_board.cmake similarity index 100% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/pre_dt_board.cmake rename to boards/ruuvi/ruuvitag/pre_dt_board.cmake diff --git a/boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag-pinctrl.dtsi b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag-pinctrl.dtsi similarity index 100% rename from boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag-pinctrl.dtsi rename to boards/ruuvi/ruuvitag/ruuvi_ruuvitag-pinctrl.dtsi diff --git a/boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag.dts b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts similarity index 100% rename from boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag.dts rename to boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts diff --git a/boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag.yaml b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.yaml similarity index 100% rename from boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag.yaml rename to boards/ruuvi/ruuvitag/ruuvi_ruuvitag.yaml diff --git a/boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag_defconfig b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag_defconfig similarity index 76% rename from boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag_defconfig rename to boards/ruuvi/ruuvitag/ruuvi_ruuvitag_defconfig index 08403e5d814..9ece16276d2 100644 --- a/boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag_defconfig +++ b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2020 Ruuvi Innovations Ltd (Oy) # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_RUUVI_RUUVITAG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/sc/index.rst b/boards/sc/index.rst new file mode 100644 index 00000000000..1347be14086 --- /dev/null +++ b/boards/sc/index.rst @@ -0,0 +1,10 @@ +.. _boards-space-cubics: + +Space Cubics +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/sc/scobc_module1/Kconfig.defconfig b/boards/sc/scobc_module1/Kconfig.defconfig new file mode 100644 index 00000000000..35aae169147 --- /dev/null +++ b/boards/sc/scobc_module1/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Space Cubics OBC module 1 + +# Copyright (c) 2021 Space Cubics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SCOBC_MODULE1 + +config CPU_CORTEX_M_HAS_SYSTICK + default y + +config CPU_HAS_ARM_MPU + default y + +config NUM_IRQS + default 7 + +endif # BOARD_SCOBC_MODULE1 diff --git a/boards/sc/scobc_module1/Kconfig.scobc_module1 b/boards/sc/scobc_module1/Kconfig.scobc_module1 new file mode 100644 index 00000000000..d8a7a3e5ac7 --- /dev/null +++ b/boards/sc/scobc_module1/Kconfig.scobc_module1 @@ -0,0 +1,7 @@ +# Space Cubics OBC module 1 configuration + +# Copyright (c) 2021 Space Cubics, LLC. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SCOBC_MODULE1 + select SOC_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/boards/sc/scobc_module1/board.cmake b/boards/sc/scobc_module1/board.cmake new file mode 100644 index 00000000000..a0f4d5f5fed --- /dev/null +++ b/boards/sc/scobc_module1/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd-ftdi.cfg") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/sc/scobc_module1/board.yml b/boards/sc/scobc_module1/board.yml new file mode 100644 index 00000000000..d8f83a733ac --- /dev/null +++ b/boards/sc/scobc_module1/board.yml @@ -0,0 +1,5 @@ +board: + name: scobc_module1 + vendor: spacecubics + socs: + - name: designstart_fpga_cortex_m3 diff --git a/boards/arm/scobc_module1/doc/index.rst b/boards/sc/scobc_module1/doc/index.rst similarity index 100% rename from boards/arm/scobc_module1/doc/index.rst rename to boards/sc/scobc_module1/doc/index.rst diff --git a/boards/arm/scobc_module1/doc/scobc.jpg b/boards/sc/scobc_module1/doc/scobc.jpg similarity index 100% rename from boards/arm/scobc_module1/doc/scobc.jpg rename to boards/sc/scobc_module1/doc/scobc.jpg diff --git a/boards/arm/scobc_module1/dts/bindings/sc,hrmem.yaml b/boards/sc/scobc_module1/dts/bindings/sc,hrmem.yaml similarity index 100% rename from boards/arm/scobc_module1/dts/bindings/sc,hrmem.yaml rename to boards/sc/scobc_module1/dts/bindings/sc,hrmem.yaml diff --git a/boards/arm/scobc_module1/scobc_module1.dts b/boards/sc/scobc_module1/scobc_module1.dts similarity index 100% rename from boards/arm/scobc_module1/scobc_module1.dts rename to boards/sc/scobc_module1/scobc_module1.dts diff --git a/boards/arm/scobc_module1/scobc_module1.yaml b/boards/sc/scobc_module1/scobc_module1.yaml similarity index 100% rename from boards/arm/scobc_module1/scobc_module1.yaml rename to boards/sc/scobc_module1/scobc_module1.yaml diff --git a/boards/sc/scobc_module1/scobc_module1_defconfig b/boards/sc/scobc_module1/scobc_module1_defconfig new file mode 100644 index 00000000000..f06a7a1dee8 --- /dev/null +++ b/boards/sc/scobc_module1/scobc_module1_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 +CONFIG_ARM_MPU=n + +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 diff --git a/boards/arm/scobc_module1/support/akizuki-m-02990.cfg b/boards/sc/scobc_module1/support/akizuki-m-02990.cfg similarity index 100% rename from boards/arm/scobc_module1/support/akizuki-m-02990.cfg rename to boards/sc/scobc_module1/support/akizuki-m-02990.cfg diff --git a/boards/arm/scobc_module1/support/openocd-ft232r.cfg b/boards/sc/scobc_module1/support/openocd-ft232r.cfg similarity index 100% rename from boards/arm/scobc_module1/support/openocd-ft232r.cfg rename to boards/sc/scobc_module1/support/openocd-ft232r.cfg diff --git a/boards/arm/scobc_module1/support/openocd-ftdi.cfg b/boards/sc/scobc_module1/support/openocd-ftdi.cfg similarity index 100% rename from boards/arm/scobc_module1/support/openocd-ftdi.cfg rename to boards/sc/scobc_module1/support/openocd-ftdi.cfg diff --git a/boards/arm/scobc_module1/support/openocd.cfg b/boards/sc/scobc_module1/support/openocd.cfg similarity index 100% rename from boards/arm/scobc_module1/support/openocd.cfg rename to boards/sc/scobc_module1/support/openocd.cfg diff --git a/boards/arm/scobc_module1/support/scobc-module1.cfg b/boards/sc/scobc_module1/support/scobc-module1.cfg similarity index 100% rename from boards/arm/scobc_module1/support/scobc-module1.cfg rename to boards/sc/scobc_module1/support/scobc-module1.cfg diff --git a/boards/arm/faze/CMakeLists.txt b/boards/seagate/faze/CMakeLists.txt similarity index 100% rename from boards/arm/faze/CMakeLists.txt rename to boards/seagate/faze/CMakeLists.txt diff --git a/boards/seagate/faze/Kconfig.faze b/boards/seagate/faze/Kconfig.faze new file mode 100644 index 00000000000..13e0852f582 --- /dev/null +++ b/boards/seagate/faze/Kconfig.faze @@ -0,0 +1,5 @@ +# Copyright (c) 2020, Seagate Technology LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FAZE + select SOC_LPC11U67 diff --git a/boards/arm/faze/board.cmake b/boards/seagate/faze/board.cmake similarity index 100% rename from boards/arm/faze/board.cmake rename to boards/seagate/faze/board.cmake diff --git a/boards/seagate/faze/board.yml b/boards/seagate/faze/board.yml new file mode 100644 index 00000000000..bd672fe549f --- /dev/null +++ b/boards/seagate/faze/board.yml @@ -0,0 +1,5 @@ +board: + name: faze + vendor: seagate + socs: + - name: lpc11u67 diff --git a/boards/arm/faze/doc/firecuda-gaming-ssd.jpg b/boards/seagate/faze/doc/firecuda-gaming-ssd.jpg similarity index 100% rename from boards/arm/faze/doc/firecuda-gaming-ssd.jpg rename to boards/seagate/faze/doc/firecuda-gaming-ssd.jpg diff --git a/boards/arm/faze/doc/index.rst b/boards/seagate/faze/doc/index.rst similarity index 100% rename from boards/arm/faze/doc/index.rst rename to boards/seagate/faze/doc/index.rst diff --git a/boards/arm/faze/faze-pinctrl.dtsi b/boards/seagate/faze/faze-pinctrl.dtsi similarity index 100% rename from boards/arm/faze/faze-pinctrl.dtsi rename to boards/seagate/faze/faze-pinctrl.dtsi diff --git a/boards/arm/faze/faze.dts b/boards/seagate/faze/faze.dts similarity index 100% rename from boards/arm/faze/faze.dts rename to boards/seagate/faze/faze.dts diff --git a/boards/arm/faze/faze.yaml b/boards/seagate/faze/faze.yaml similarity index 100% rename from boards/arm/faze/faze.yaml rename to boards/seagate/faze/faze.yaml diff --git a/boards/arm/faze/faze_defconfig b/boards/seagate/faze/faze_defconfig similarity index 87% rename from boards/arm/faze/faze_defconfig rename to boards/seagate/faze/faze_defconfig index f6dc6fafb97..257f6fb3c61 100644 --- a/boards/arm/faze/faze_defconfig +++ b/boards/seagate/faze/faze_defconfig @@ -7,8 +7,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 CONFIG_GPIO=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SOC_SERIES_LPC11U6X=y -CONFIG_SOC_LPC11U67=y CONFIG_MAIN_STACK_SIZE=512 CONFIG_ISR_STACK_SIZE=768 CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_SRAM1=y diff --git a/boards/arm/lpcxpresso11u68/pre_dt_board.cmake b/boards/seagate/faze/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso11u68/pre_dt_board.cmake rename to boards/seagate/faze/pre_dt_board.cmake diff --git a/boards/arm/faze/support/openocd.cfg b/boards/seagate/faze/support/openocd.cfg similarity index 100% rename from boards/arm/faze/support/openocd.cfg rename to boards/seagate/faze/support/openocd.cfg diff --git a/boards/seagate/index.rst b/boards/seagate/index.rst new file mode 100644 index 00000000000..6232f7d2a11 --- /dev/null +++ b/boards/seagate/index.rst @@ -0,0 +1,10 @@ +.. _boards-seagate: + +Seagate Technology PLC +###################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/seagate/legend/Kconfig.defconfig b/boards/seagate/legend/Kconfig.defconfig new file mode 100644 index 00000000000..ac77ec7855e --- /dev/null +++ b/boards/seagate/legend/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Legend board family configuration + +# Copyright (c) 2021, Seagate Technology LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LEGEND + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_LEGEND diff --git a/boards/seagate/legend/Kconfig.legend b/boards/seagate/legend/Kconfig.legend new file mode 100644 index 00000000000..68ee4b4d56b --- /dev/null +++ b/boards/seagate/legend/Kconfig.legend @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Seagate Technology +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LEGEND + select SOC_STM32F070XB diff --git a/boards/arm/legend/board.cmake b/boards/seagate/legend/board.cmake similarity index 100% rename from boards/arm/legend/board.cmake rename to boards/seagate/legend/board.cmake diff --git a/boards/seagate/legend/board.yml b/boards/seagate/legend/board.yml new file mode 100644 index 00000000000..0c100284bde --- /dev/null +++ b/boards/seagate/legend/board.yml @@ -0,0 +1,7 @@ +board: + name: legend + vendor: seagate + revision: + format: custom + socs: + - name: stm32f070xb diff --git a/boards/arm/legend/doc/img/firecuda_gaming_hard_drive.jpg b/boards/seagate/legend/doc/img/firecuda_gaming_hard_drive.jpg similarity index 100% rename from boards/arm/legend/doc/img/firecuda_gaming_hard_drive.jpg rename to boards/seagate/legend/doc/img/firecuda_gaming_hard_drive.jpg diff --git a/boards/arm/legend/doc/img/firecuda_gaming_hub.jpg b/boards/seagate/legend/doc/img/firecuda_gaming_hub.jpg similarity index 100% rename from boards/arm/legend/doc/img/firecuda_gaming_hub.jpg rename to boards/seagate/legend/doc/img/firecuda_gaming_hub.jpg diff --git a/boards/arm/legend/doc/index.rst b/boards/seagate/legend/doc/index.rst similarity index 100% rename from boards/arm/legend/doc/index.rst rename to boards/seagate/legend/doc/index.rst diff --git a/boards/arm/legend/legend.dts b/boards/seagate/legend/legend.dts similarity index 100% rename from boards/arm/legend/legend.dts rename to boards/seagate/legend/legend.dts diff --git a/boards/seagate/legend/legend_defconfig b/boards/seagate/legend/legend_defconfig new file mode 100644 index 00000000000..8bb683ce992 --- /dev/null +++ b/boards/seagate/legend/legend_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Clock Control +CONFIG_CLOCK_CONTROL=y + +# Enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/legend/legend_25hdd.overlay b/boards/seagate/legend/legend_stm32f070xb_25hdd.overlay similarity index 100% rename from boards/arm/legend/legend_25hdd.overlay rename to boards/seagate/legend/legend_stm32f070xb_25hdd.overlay diff --git a/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml b/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml new file mode 100644 index 00000000000..a9eb85aee47 --- /dev/null +++ b/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml @@ -0,0 +1,20 @@ +identifier: legend@25hdd +name: Legend +type: mcu +arch: arm +ram: 16 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - pwm + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: seagate diff --git a/boards/arm/legend/legend_25ssd.overlay b/boards/seagate/legend/legend_stm32f070xb_25ssd.overlay similarity index 100% rename from boards/arm/legend/legend_25ssd.overlay rename to boards/seagate/legend/legend_stm32f070xb_25ssd.overlay diff --git a/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml b/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml new file mode 100644 index 00000000000..db494bd878c --- /dev/null +++ b/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml @@ -0,0 +1,20 @@ +identifier: legend@25ssd +name: Legend +type: mcu +arch: arm +ram: 16 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - pwm + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: seagate diff --git a/boards/arm/legend/legend_35.overlay b/boards/seagate/legend/legend_stm32f070xb_35.overlay similarity index 100% rename from boards/arm/legend/legend_35.overlay rename to boards/seagate/legend/legend_stm32f070xb_35.overlay diff --git a/boards/seagate/legend/legend_stm32f070xb_35.yaml b/boards/seagate/legend/legend_stm32f070xb_35.yaml new file mode 100644 index 00000000000..37ed59788d9 --- /dev/null +++ b/boards/seagate/legend/legend_stm32f070xb_35.yaml @@ -0,0 +1,20 @@ +identifier: legend@35 +name: Legend +type: mcu +arch: arm +ram: 16 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - pwm + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: seagate diff --git a/boards/arm/legend/revision.cmake b/boards/seagate/legend/revision.cmake similarity index 100% rename from boards/arm/legend/revision.cmake rename to boards/seagate/legend/revision.cmake diff --git a/boards/arm/legend/support/openocd.cfg b/boards/seagate/legend/support/openocd.cfg similarity index 100% rename from boards/arm/legend/support/openocd.cfg rename to boards/seagate/legend/support/openocd.cfg diff --git a/boards/seco/index.rst b/boards/seco/index.rst new file mode 100644 index 00000000000..c38b58dc14d --- /dev/null +++ b/boards/seco/index.rst @@ -0,0 +1,10 @@ +.. _boards-seco: + +SECO SpA +######## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/seco/stm32f3_seco_d23/Kconfig.stm32f3_seco_d23 b/boards/seco/stm32f3_seco_d23/Kconfig.stm32f3_seco_d23 new file mode 100644 index 00000000000..0c8590e470d --- /dev/null +++ b/boards/seco/stm32f3_seco_d23/Kconfig.stm32f3_seco_d23 @@ -0,0 +1,5 @@ +# Copyright (c) 2022, SECO Spa +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F3_SECO_D23 + select SOC_STM32F302XC diff --git a/boards/arm/stm32f3_seco_d23/board.cmake b/boards/seco/stm32f3_seco_d23/board.cmake similarity index 100% rename from boards/arm/stm32f3_seco_d23/board.cmake rename to boards/seco/stm32f3_seco_d23/board.cmake diff --git a/boards/seco/stm32f3_seco_d23/board.yml b/boards/seco/stm32f3_seco_d23/board.yml new file mode 100644 index 00000000000..a7976211a2c --- /dev/null +++ b/boards/seco/stm32f3_seco_d23/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f3_seco_d23 + vendor: seco + socs: + - name: stm32f302xc diff --git a/boards/arm/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg b/boards/seco/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg similarity index 100% rename from boards/arm/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg rename to boards/seco/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg diff --git a/boards/arm/stm32f3_seco_d23/doc/index.rst b/boards/seco/stm32f3_seco_d23/doc/index.rst similarity index 100% rename from boards/arm/stm32f3_seco_d23/doc/index.rst rename to boards/seco/stm32f3_seco_d23/doc/index.rst diff --git a/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.dts b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.dts similarity index 100% rename from boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.dts rename to boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.dts diff --git a/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.yaml b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.yaml similarity index 100% rename from boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.yaml rename to boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.yaml diff --git a/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23_defconfig b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23_defconfig similarity index 89% rename from boards/arm/stm32f3_seco_d23/stm32f3_seco_d23_defconfig rename to boards/seco/stm32f3_seco_d23/stm32f3_seco_d23_defconfig index 344746567ad..9432c4e8149 100644 --- a/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23_defconfig +++ b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23_defconfig @@ -3,9 +3,6 @@ # # Copyright (c) 2022, SECO Spa -CONFIG_SOC_SERIES_STM32F3X=y -CONFIG_SOC_STM32F302XC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f3_seco_d23/support/openocd.cfg b/boards/seco/stm32f3_seco_d23/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f3_seco_d23/support/openocd.cfg rename to boards/seco/stm32f3_seco_d23/support/openocd.cfg diff --git a/boards/seeed/index.rst b/boards/seeed/index.rst new file mode 100644 index 00000000000..dad63401530 --- /dev/null +++ b/boards/seeed/index.rst @@ -0,0 +1,10 @@ +.. _boards-seeed: + +Seeed Technology Co., Ltd +######################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/seeed/lora_e5_dev_board/Kconfig.lora_e5_dev_board b/boards/seeed/lora_e5_dev_board/Kconfig.lora_e5_dev_board new file mode 100644 index 00000000000..691f4e748a2 --- /dev/null +++ b/boards/seeed/lora_e5_dev_board/Kconfig.lora_e5_dev_board @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LORA_E5_DEV_BOARD + select SOC_STM32WLE5XX diff --git a/boards/seeed/lora_e5_dev_board/board.cmake b/boards/seeed/lora_e5_dev_board/board.cmake new file mode 100644 index 00000000000..07d09a3aba0 --- /dev/null +++ b/boards/seeed/lora_e5_dev_board/board.cmake @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2021 Thomas Stranger + +board_runner_args(pyocd "--target=stm32wle5jcix") +board_runner_args(pyocd "--flash-opt=-O reset_type=hw") +board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") +board_runner_args(jlink "--device=STM32WLE5JC" "--speed=4000" "--reset-after-load") +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(blackmagicprobe "--connect-rst") + +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) diff --git a/boards/seeed/lora_e5_dev_board/board.yml b/boards/seeed/lora_e5_dev_board/board.yml new file mode 100644 index 00000000000..b6691948f2b --- /dev/null +++ b/boards/seeed/lora_e5_dev_board/board.yml @@ -0,0 +1,5 @@ +board: + name: lora_e5_dev_board + vendor: seeed + socs: + - name: stm32wle5xx diff --git a/boards/arm/lora_e5_dev_board/doc/img/lora_e5_dev_board.jpg b/boards/seeed/lora_e5_dev_board/doc/img/lora_e5_dev_board.jpg similarity index 100% rename from boards/arm/lora_e5_dev_board/doc/img/lora_e5_dev_board.jpg rename to boards/seeed/lora_e5_dev_board/doc/img/lora_e5_dev_board.jpg diff --git a/boards/arm/lora_e5_dev_board/doc/img/lora_e5_dev_board_pinout.jpg b/boards/seeed/lora_e5_dev_board/doc/img/lora_e5_dev_board_pinout.jpg similarity index 100% rename from boards/arm/lora_e5_dev_board/doc/img/lora_e5_dev_board_pinout.jpg rename to boards/seeed/lora_e5_dev_board/doc/img/lora_e5_dev_board_pinout.jpg diff --git a/boards/arm/lora_e5_dev_board/doc/lora_e5_dev_board.rst b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst similarity index 97% rename from boards/arm/lora_e5_dev_board/doc/lora_e5_dev_board.rst rename to boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst index c3c91fc8f74..039c2addbf0 100644 --- a/boards/arm/lora_e5_dev_board/doc/lora_e5_dev_board.rst +++ b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst @@ -111,10 +111,9 @@ features: Other hardware features are not yet supported on this Zephyr port. -The default configuration can be found in the defconfig and dts files: - -- :zephyr_file:`boards/arm/lora_e5_dev_board/lora_e5_dev_board_defconfig` -- :zephyr_file:`boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts` +The default configuration can be found in: +- :zephyr_file:`boards/seeed_studio/lora_e5_dev_board/lora_e5_dev_board_defconfig` +- :zephyr_file:`boards/seeed_studio/lora_e5_dev_board/lora_e5_dev_board.dts` Connections and IOs @@ -215,7 +214,7 @@ set the RDP option byte to ``AA``, or use the STM32_Programmer_CLI passing the ``--readunprotect`` command to perform this read protection regression. The RDP level 1 to RDP level 0 regression will erase the factory programmed AT -firmware, from which seeed has neither released the source code nor a binary. +firmware, from which seeed studio has neither released the source code nor a binary. Also, note that on the module the ``BOOT0`` pin of the SOC is not accessible, so the system bootloader will only be executed if configured in the option bytes. diff --git a/boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts similarity index 99% rename from boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts rename to boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts index 02602825712..64ea2f84726 100644 --- a/boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts +++ b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include / { diff --git a/boards/arm/lora_e5_dev_board/lora_e5_dev_board.yaml b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml similarity index 91% rename from boards/arm/lora_e5_dev_board/lora_e5_dev_board.yaml rename to boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml index 446bc1934cb..dede51f8125 100644 --- a/boards/arm/lora_e5_dev_board/lora_e5_dev_board.yaml +++ b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml @@ -17,4 +17,4 @@ supported: - uart - watchdog - lora -vendor: seeed +vendor: seeed studio diff --git a/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig new file mode 100644 index 00000000000..17aa77ac7f8 --- /dev/null +++ b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2021 Thomas Stranger + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable regulator for the power-rails +CONFIG_REGULATOR=y + +# Enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/lora_e5_dev_board/support/openocd.cfg b/boards/seeed/lora_e5_dev_board/support/openocd.cfg similarity index 100% rename from boards/arm/lora_e5_dev_board/support/openocd.cfg rename to boards/seeed/lora_e5_dev_board/support/openocd.cfg diff --git a/boards/seeed/lora_e5_mini/Kconfig.lora_e5_mini b/boards/seeed/lora_e5_mini/Kconfig.lora_e5_mini new file mode 100644 index 00000000000..47be610d845 --- /dev/null +++ b/boards/seeed/lora_e5_mini/Kconfig.lora_e5_mini @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Marcin Niestroj +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LORA_E5_MINI + select SOC_STM32WLE5XX diff --git a/boards/arm/lora_e5_dev_board/board.cmake b/boards/seeed/lora_e5_mini/board.cmake similarity index 100% rename from boards/arm/lora_e5_dev_board/board.cmake rename to boards/seeed/lora_e5_mini/board.cmake diff --git a/boards/seeed/lora_e5_mini/board.yml b/boards/seeed/lora_e5_mini/board.yml new file mode 100644 index 00000000000..1643caea3c1 --- /dev/null +++ b/boards/seeed/lora_e5_mini/board.yml @@ -0,0 +1,5 @@ +board: + name: lora_e5_mini + vendor: seeed + socs: + - name: stm32wle5xx diff --git a/boards/arm/lora_e5_mini/doc/img/lora_e5_mini.jpg b/boards/seeed/lora_e5_mini/doc/img/lora_e5_mini.jpg similarity index 100% rename from boards/arm/lora_e5_mini/doc/img/lora_e5_mini.jpg rename to boards/seeed/lora_e5_mini/doc/img/lora_e5_mini.jpg diff --git a/boards/arm/lora_e5_mini/doc/img/lora_e5_mini_pinout.jpg b/boards/seeed/lora_e5_mini/doc/img/lora_e5_mini_pinout.jpg similarity index 100% rename from boards/arm/lora_e5_mini/doc/img/lora_e5_mini_pinout.jpg rename to boards/seeed/lora_e5_mini/doc/img/lora_e5_mini_pinout.jpg diff --git a/boards/seeed/lora_e5_mini/doc/index.rst b/boards/seeed/lora_e5_mini/doc/index.rst new file mode 100644 index 00000000000..0b4120f2c8c --- /dev/null +++ b/boards/seeed/lora_e5_mini/doc/index.rst @@ -0,0 +1,226 @@ +.. _lora_e5_mini: + +Seeed Studio LoRa-E5 mini +######################### + +Overview +******** + +LoRa-E5 mini is a compacted-sized development board suitable for the rapid +testing and building of small-sized LoRa device, exposing all capabilities of +Seeed Studio LoRa-E5 STM32WLE5JC module. + +.. image:: img/lora_e5_mini.jpg + :align: center + :alt: LoRa-E5 mini + +Hardware +******** + +The boards' LoRa-E5 Module packages a STM32WLE5JC SOC, a 32MHz TCXO, +and a 32.768kHz crystal oscillator in a 28-pin SMD package. +This STM32WLEJC SOC is powered by ARM Cortex-M4 core and integrates Semtech +SX126X LoRa IP to support (G)FSK, BPSK, (G)MSK, and LoRa modulations. + +- LoRa-E5 STM32WLE5JC Module with STM32WLE5JC multiprotocol LPWAN single-core + 32-bit microcontroller (Arm® Cortex®-M4 at 48 MHz) in 28-pin SMD package + featuring: + + - Ultra-low-power MCU + - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®, + (G)FSK, (G)MSK, and BPSK modulations + - 256-Kbyte Flash memory and 64-Kbyte SRAM + - Hardware encryption AES256-bit and a True random number generator + +- 1 user LED +- 2 serial communication (RX/TX) LEDs +- 1 boot/user and 1 reset push-button +- 32.768 kHz LSE crystal oscillator +- 32 MHz HSE oscillator +- Board connectors: + + - USB Type-C connector + - +/- (battery) power input pins (3-5V) + - SMA-K and IPEX antenna connectors + +- Delivered with SMA antenna (per default IPEX connector is disconnected) +- Flexible power-supply options: USB Type C or 3-5V battery soldered to +/- pins +- Suitable for rapid prototyping of end nodes based on LoRaWAN, Sigfox, wM-Bus, + and many other proprietary protocols +- All GPIOs led out from the LoRa-E5 STM32WLE5JC module +- 4x M2 mounting holes + +More information about the board can be found at the `LoRa-E5 mini Wiki`_. + +More information about LoRa-E5 STM32WLE5JC Module can be found here: + +- `LoRa-E5 STM32WLE5JC Module Wiki`_ +- `LoRa-E5 STM32WLE5JC Module datasheet`_ +- `STM32WLE5JC datasheet`_ +- `STM32WLE5JC reference manual`_ +- `STM32WLE5JC on www.st.com`_ + +Supported Features +================== + +The Zephyr LoRa-E5 mini configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | LoRa | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in: + +- :zephyr_file:`boards/seeed_studio/lora_e5_mini/lora_e5_mini_defconfig` +- :zephyr_file:`boards/seeed_studio/lora_e5_mini/lora_e5_mini.dts` + + +Connections and IOs +=================== + +LoRa-E5 mini has 4 GPIO controllers. These controllers are responsible for pin +muxing, input/output, pull-up, etc. + +Available pins: +--------------- + +.. image:: img/lora_e5_mini_pinout.jpg + :align: center + :alt: LoRa-E5 mini Pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART_1 TX : PB6 +- USART_1 RX : PB7 +- I2C_2_SCL : PB15 +- I2C_2_SDA : PA15 +- BOOT_PB : PB13 +- LED_1 : PB5 + +System Clock +------------ + +LoRa-E5 mini board System Clock could be driven by the low-power internal (MSI), +High-speed internal (HSI) or High-speed external (HSE) oscillator, as well as +main PLL clock. By default System clock is driven by the MSI clock at 48MHz. + +Programming and Debugging +************************* + +Applications for the ``lora_e5_mini`` board configuration can be built the +usual way (see :ref:`build_an_application`). + +In the factory the module is flashed with an DFU bootloader, an AT command +firmware, and the read protection level 1 is enabled. +So before you can program a Zephyr application to the module for the first time +you have to reset the read protection to level 0. +In case you use an st-link debugger you can use the STM32CubeProgrammer GUI to +set the RDP option byte to ``AA``, +or use the STM32_Programmer_CLI passing the ``--readunprotect`` command +to perform this read protection regression. +The RDP level 1 to RDP level 0 regression will erase the factory programmed AT +firmware, from which seeed studio has neither released the source code nor a binary. +Also, note that on the module the ``BOOT0`` pin of the SOC is not accessible, +so the system bootloader will only be executed if configured in the option bytes. + +Flashing +======== + +The LoRa-E5 mini does not include a on-board debug probe. +But the module can be debugged by connecting an external debug probe to the +2.54mm header. +Depending on the external probe used, ``openocd``, the ``stm32cubeprogrammer``, +``pyocd``, ``blackmagic``, or ``jlink`` runner can be used to flash the board. +Additional notes: + +- Pyocd: For STM32WL support Pyocd needs additional target information, which + can be installed by adding "pack" support with the following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32wl + +Flashing an application to LoRa-E5 mini +--------------------------------------- + +Connect the LoRa-E5 to your host computer using the external debug probe. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your board: +Per default the console on ``usart1`` is available on the USB Type C connector +via the built-in USB to UART converter. + +.. code-block:: console + + $ picocom --baud 115200 /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: lora_e5_mini + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: lora_e5_mini + :maybe-skip-config: + :goals: debug + +.. _LoRa-E5 mini Wiki: + https://wiki.seeedstudio.com/LoRa_E5_mini/ + +.. _LoRa-E5 STM32WLE5JC Module Wiki: + https://wiki.seeedstudio.com/LoRa-E5_STM32WLE5JC_Module/ + +.. _LoRa-E5 STM32WLE5JC Module datasheet: + https://files.seeedstudio.com/products/317990687/res/LoRa-E5%20module%20datasheet_V1.0.pdf + +.. _STM32WLE5JC on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32wle5jc.html + +.. _STM32WLE5JC datasheet: + https://www.st.com/resource/en/datasheet/stm32wle5jc.pdf + +.. _STM32WLE5JC reference manual: + https://www.st.com/resource/en/reference_manual/dm00530369-stm32wlex-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf diff --git a/boards/arm/lora_e5_mini/lora_e5_mini.dts b/boards/seeed/lora_e5_mini/lora_e5_mini.dts similarity index 98% rename from boards/arm/lora_e5_mini/lora_e5_mini.dts rename to boards/seeed/lora_e5_mini/lora_e5_mini.dts index e65572c6e35..3eb9e803301 100644 --- a/boards/arm/lora_e5_mini/lora_e5_mini.dts +++ b/boards/seeed/lora_e5_mini/lora_e5_mini.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include / { diff --git a/boards/arm/lora_e5_mini/lora_e5_mini.yaml b/boards/seeed/lora_e5_mini/lora_e5_mini.yaml similarity index 91% rename from boards/arm/lora_e5_mini/lora_e5_mini.yaml rename to boards/seeed/lora_e5_mini/lora_e5_mini.yaml index 144ee2275ad..72a8018b0e3 100644 --- a/boards/arm/lora_e5_mini/lora_e5_mini.yaml +++ b/boards/seeed/lora_e5_mini/lora_e5_mini.yaml @@ -16,4 +16,4 @@ supported: - uart - watchdog - lora -vendor: seeed +vendor: seeed studio diff --git a/boards/arm/lora_e5_mini/lora_e5_mini_defconfig b/boards/seeed/lora_e5_mini/lora_e5_mini_defconfig similarity index 83% rename from boards/arm/lora_e5_mini/lora_e5_mini_defconfig rename to boards/seeed/lora_e5_mini/lora_e5_mini_defconfig index 5e6649fe25a..0d6dc9f80d3 100644 --- a/boards/arm/lora_e5_mini/lora_e5_mini_defconfig +++ b/boards/seeed/lora_e5_mini/lora_e5_mini_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WLX=y -CONFIG_SOC_STM32WLE5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/lora_e5_mini/support/openocd.cfg b/boards/seeed/lora_e5_mini/support/openocd.cfg similarity index 100% rename from boards/arm/lora_e5_mini/support/openocd.cfg rename to boards/seeed/lora_e5_mini/support/openocd.cfg diff --git a/boards/seeed/seeeduino_xiao/Kconfig.seeeduino_xiao b/boards/seeed/seeeduino_xiao/Kconfig.seeeduino_xiao new file mode 100644 index 00000000000..a66bf5bc5c0 --- /dev/null +++ b/boards/seeed/seeeduino_xiao/Kconfig.seeeduino_xiao @@ -0,0 +1,6 @@ +# Copyright (c) 2020 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SEEEDUINO_XIAO + select SOC_SAMD21G18A diff --git a/boards/arm/seeeduino_xiao/board.cmake b/boards/seeed/seeeduino_xiao/board.cmake similarity index 100% rename from boards/arm/seeeduino_xiao/board.cmake rename to boards/seeed/seeeduino_xiao/board.cmake diff --git a/boards/seeed/seeeduino_xiao/board.yml b/boards/seeed/seeeduino_xiao/board.yml new file mode 100644 index 00000000000..386a3b3cbb6 --- /dev/null +++ b/boards/seeed/seeeduino_xiao/board.yml @@ -0,0 +1,5 @@ +board: + name: seeeduino_xiao + vendor: seeed + socs: + - name: samd21g18a diff --git a/boards/arm/seeeduino_xiao/doc/img/seeeduino_xiao.jpg b/boards/seeed/seeeduino_xiao/doc/img/seeeduino_xiao.jpg similarity index 100% rename from boards/arm/seeeduino_xiao/doc/img/seeeduino_xiao.jpg rename to boards/seeed/seeeduino_xiao/doc/img/seeeduino_xiao.jpg diff --git a/boards/seeed/seeeduino_xiao/doc/index.rst b/boards/seeed/seeeduino_xiao/doc/index.rst new file mode 100644 index 00000000000..17033e22ff7 --- /dev/null +++ b/boards/seeed/seeeduino_xiao/doc/index.rst @@ -0,0 +1,176 @@ +.. _seeeduino_xiao: + +Seeeduino XIAO +############## + +Overview +******** + +The Seeeduino XIAO is a tiny (20 mm x 17.5 mm) ARM development +board with onboard LEDs, USB port, and range of I/O broken out +onto 14 pins. + +.. image:: img/seeeduino_xiao.jpg + :align: center + :alt: Seeeduino XIAO + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 256 KiB flash memory and 32 KiB of RAM +- Three user LEDs +- Native USB port + +Supported Features +================== + +The seeeduino_xiao board configuration supports the following hardware +features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| DMA | on-chip | Direct memory access | ++-----------+------------+------------------------------------------+ +| DAC | on-chip | Digital to analogue converter | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| HWINFO | on-chip | Hardware info | ++-----------+------------+------------------------------------------+ +| I2C | on-chip | Inter-Integrated Circuit | ++-----------+------------+------------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/seeed_studio/seeeduino_xiao/seeeduino_xiao_defconfig`. + +Connections and IOs +=================== + +The `Seeeduino XIAO wiki`_ has detailed information about +the board including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD21 MCU is configured to use the 32 kHz external crystal +with the on-chip PLL generating the 48 MHz system clock. The internal +APB and GCLK unit are set up in the same way as the upstream Arduino +libraries. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the XIAO, SERCOM0 can be put +into SPI mode and used to connect to devices over pin 9 (MISO), pin 10 +(MOSI), and pin 8 (SCK). + +I2C Port +======== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the XIAO, SERCOM2 is available on +pin 4 (SDA) and pin 5 (SCL). + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the XIAO, SERCOM4 is +the Zephyr console and is available on pins 7 (RX) and 6 (TX). + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +DAC +=== + +The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On +the XIAO, the DAC is available on pin 0. + +Programming and Debugging +************************* + +The XIAO ships the BOSSA compatible UF2 bootloader. The bootloader can be +entered by shorting the RST and GND pads twice. + +Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader +will be entered automatically when you run :code:`west flash`. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: seeeduino_xiao + :goals: build + :compact: + +#. Connect the XIAO to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Short the RST and GND pads twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: seeeduino_xiao + :goals: flash + :compact: + + You should see "Hello World! seeeduino_xiao" in your terminal. + +References +********** + +.. target-notes:: + +.. _Seeeduino XIAO wiki: + https://wiki.seeedstudio.com/Seeeduino-XIAO/ + +.. _pinouts: + https://wiki.seeedstudio.com/Seeeduino-XIAO/#hardware-overview + +.. _schematic: + https://wiki.seeedstudio.com/Seeeduino-XIAO/#resourses diff --git a/boards/arm/seeeduino_xiao/pre_dt_board.cmake b/boards/seeed/seeeduino_xiao/pre_dt_board.cmake similarity index 100% rename from boards/arm/seeeduino_xiao/pre_dt_board.cmake rename to boards/seeed/seeeduino_xiao/pre_dt_board.cmake diff --git a/boards/arm/seeeduino_xiao/seeed_xiao_connector.dtsi b/boards/seeed/seeeduino_xiao/seeed_xiao_connector.dtsi similarity index 100% rename from boards/arm/seeeduino_xiao/seeed_xiao_connector.dtsi rename to boards/seeed/seeeduino_xiao/seeed_xiao_connector.dtsi diff --git a/boards/arm/seeeduino_xiao/seeeduino_xiao-pinctrl.dtsi b/boards/seeed/seeeduino_xiao/seeeduino_xiao-pinctrl.dtsi similarity index 100% rename from boards/arm/seeeduino_xiao/seeeduino_xiao-pinctrl.dtsi rename to boards/seeed/seeeduino_xiao/seeeduino_xiao-pinctrl.dtsi diff --git a/boards/arm/seeeduino_xiao/seeeduino_xiao.dts b/boards/seeed/seeeduino_xiao/seeeduino_xiao.dts similarity index 100% rename from boards/arm/seeeduino_xiao/seeeduino_xiao.dts rename to boards/seeed/seeeduino_xiao/seeeduino_xiao.dts diff --git a/boards/arm/seeeduino_xiao/seeeduino_xiao.yaml b/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml similarity index 96% rename from boards/arm/seeeduino_xiao/seeeduino_xiao.yaml rename to boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml index 73bfc8b114d..b3532949edd 100644 --- a/boards/arm/seeeduino_xiao/seeeduino_xiao.yaml +++ b/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml @@ -2,20 +2,21 @@ identifier: seeeduino_xiao name: Seeeduino XIAO type: mcu arch: arm -ram: 32 -flash: 256 toolchain: - zephyr - gnuarmemb - xtools +flash: 256 +ram: 32 supported: - dma - dac - gpio - hwinfo - - spi - i2c + - spi - uart + - usb - usb_device - watchdog vendor: seeed diff --git a/boards/arm/seeeduino_xiao/seeeduino_xiao_defconfig b/boards/seeed/seeeduino_xiao/seeeduino_xiao_defconfig similarity index 75% rename from boards/arm/seeeduino_xiao/seeeduino_xiao_defconfig rename to boards/seeed/seeeduino_xiao/seeeduino_xiao_defconfig index 01123f55b5a..a53d4bd7283 100644 --- a/boards/arm/seeeduino_xiao/seeeduino_xiao_defconfig +++ b/boards/seeed/seeeduino_xiao/seeeduino_xiao_defconfig @@ -1,14 +1,14 @@ +# Copyright (c) 2024 Gerson Fernando Budke # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_SEEEDUINO_XIAO=y CONFIG_SOC_ATMEL_SAMD_XOSC32K=y CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y + CONFIG_CONSOLE=y +CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y -CONFIG_BUILD_OUTPUT_UF2=y diff --git a/boards/arm/seeeduino_xiao/support/openocd.cfg b/boards/seeed/seeeduino_xiao/support/openocd.cfg similarity index 100% rename from boards/arm/seeeduino_xiao/support/openocd.cfg rename to boards/seeed/seeeduino_xiao/support/openocd.cfg diff --git a/boards/seeed/wio_terminal/Kconfig.defconfig b/boards/seeed/wio_terminal/Kconfig.defconfig new file mode 100644 index 00000000000..4b742f1a228 --- /dev/null +++ b/boards/seeed/wio_terminal/Kconfig.defconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Joel Guittet +# Wio Terminal board configuration + +# SPDX-License-Identifier: Apache-2.0 + +config LV_COLOR_16_SWAP + default y if LVGL diff --git a/boards/seeed/wio_terminal/Kconfig.wio_terminal b/boards/seeed/wio_terminal/Kconfig.wio_terminal new file mode 100644 index 00000000000..a24d6f8df4a --- /dev/null +++ b/boards/seeed/wio_terminal/Kconfig.wio_terminal @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Joel Guittet +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WIO_TERMINAL + select SOC_SAMD51P19A diff --git a/boards/arm/wio_terminal/board.cmake b/boards/seeed/wio_terminal/board.cmake similarity index 100% rename from boards/arm/wio_terminal/board.cmake rename to boards/seeed/wio_terminal/board.cmake diff --git a/boards/seeed/wio_terminal/board.yml b/boards/seeed/wio_terminal/board.yml new file mode 100644 index 00000000000..a7080a87777 --- /dev/null +++ b/boards/seeed/wio_terminal/board.yml @@ -0,0 +1,5 @@ +board: + name: wio_terminal + vendor: seeed + socs: + - name: samd51p19a diff --git a/boards/arm/wio_terminal/doc/img/wio_terminal.png b/boards/seeed/wio_terminal/doc/img/wio_terminal.png similarity index 100% rename from boards/arm/wio_terminal/doc/img/wio_terminal.png rename to boards/seeed/wio_terminal/doc/img/wio_terminal.png diff --git a/boards/seeed/wio_terminal/doc/index.rst b/boards/seeed/wio_terminal/doc/index.rst new file mode 100644 index 00000000000..e12212be4cc --- /dev/null +++ b/boards/seeed/wio_terminal/doc/index.rst @@ -0,0 +1,213 @@ +.. _wio_terminal: + +Wio Terminal +############ + +Overview +******** + +The Wio Terminal is a small (72 mm x 57 mm x 12 mm) and powerful ARM board with +wireless connectivity (2.4G/5G dual-band Wi-Fi and BLE 5.0), LCD display, +USB C port, FPC connector, microSD card slot, Raspberry Pi compatible 40-pins +header and 2 Grove connectors. + +.. image:: img/wio_terminal.png + :width: 500px + :align: center + :alt: Seeed Studio Wio Terminal + +Hardware +******** + +- ATSAMD51P19 ARM Cortex-M4F processor at 120 MHz +- 512 KiB flash memory and 192 KiB of RAM +- 4 MiB external flash +- MicroSD card slot +- RTL8720DN 2.4G/5G Dual Bands Wireless and BLE5.0 Combo Module +- 2.4inch LCD display +- LIS3DH accelerometer +- Microphone 1.0V-10V -42dB +- Speaker ≥78dB @10cm 4000Hz +- Light Sensor 400-1050nm +- Infrared Emitter 940nm +- GPIO 40 pin (Raspberry Pi compatible) +- 2x Grove connectors +- 1x user LED +- 3x user buttons +- 5-way user button +- Power/Reset/Boot mode switch +- Native USB port + +Supported Features +================== + +The wio_terminal board configuration supports the following hardware features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - Nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - Systick + * - WDT + - on-chip + - Watchdog + * - GPIO + - on-chip + - I/O ports + * - USART + - on-chip + - Serial port + * - I2C + - on-chip + - Inter-Integrated Circuit + * - SPI + - on-chip + - Serial Peripheral Interface port + * - TRNG + - on-chip + - True Random Number Generator + * - HWINFO + - on-chip + - Unique 128 bit serial number + * - RTC + - on-chip + - Real-Time Counter + * - USB + - on-chip + - USB device + * - PWM + - on-chip + - PWM + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/seeed_studio/wio_terminal/wio_terminal_defconfig`. + +Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. +To use the RTC, set :kconfig:option:`CONFIG_CORTEX_M_SYSTICK=n` and set +:kconfig:option:`CONFIG_SYS_CLOCK_TICKS_PER_SEC` to no more than 32 kHZ divided +by 7, i.e. no more than 4500. + +Connections and IOs +=================== + +The `Wio Terminal Getting started guide`_ has detailed information about the +board including `pinouts`_ and its `schematics`_. + +System Clock +============ + +The SAMD51 MCU is configured to use the 32.768 kHz internal oscillator with the +on-chip PLL generating the 120 MHz system clock. + +Serial Port +=========== + +Zephyr console output is available using the USB connector, which is used to +make the console available on PC as USB CDC class. + +USB Device Port +=============== + +The SAMD51 MCU has a USB device port that can be used to communicate with a +host PC. See the :ref:`usb-samples` sample applications for more, such as the +:zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual serial port that echos +characters back to the host PC. + +Programming and Debugging +************************* + +The Wio Terminal ships with an UF2 bootloader that is BOSSA compatible. The +bootloader can be entered by quickly tapping the reset button twice. + +The UF2 file is generated when building the application, and it is possible to +use it to flash the target. Enter the bootloader by quickly sliding the power +button twice, and copy the UF2 file to the USB mass storage device. The device +reboots on the new firmware after the UF2 file has finished transferring. + +Flashing +======== + +#. Build the Zephyr kernel and the :code:`button` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: wio_terminal + :goals: build + :compact: + +#. Swipe the reset/power button down twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: wio_terminal + :goals: flash + :compact: + + You should see the blue (user) LED flashing whenever you press the third + (counting from the top left) user button at the top of the Wio Terminal. + +Debugging +========= + +In addition to the built-in bootloader, the Wio Terminal can be flashed and +debugged using an SWD probe such as the Segger J-Link. + +#. Solder cables to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, + :code:`GND`, and :code:`3V3` pins. See `Test with SWD`_ for more + information. + +#. Connect the board to the probe by connecting the :code:`SWCLK`, + :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the + Wio Terminal to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, + :code:`GND`, and :code:`VTref` pins on the `J-Link`_. + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: wio_terminal + :goals: flash + :flash-args: -r openocd + :compact: + +#. Start debugging: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: wio_terminal + :goals: debug + :compact: + +References +********** + +.. target-notes:: + +.. _Wio Terminal Getting started guide: + https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/ + +.. _pinouts: + https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#pinout-diagram + +.. _schematics: + https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#resources + +.. _Test with SWD: + https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#test-with-swd + +.. _J-Link: + https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/wio_terminal/grove_connectors.dtsi b/boards/seeed/wio_terminal/grove_connectors.dtsi similarity index 100% rename from boards/arm/wio_terminal/grove_connectors.dtsi rename to boards/seeed/wio_terminal/grove_connectors.dtsi diff --git a/boards/arm/wio_terminal/pre_dt_board.cmake b/boards/seeed/wio_terminal/pre_dt_board.cmake similarity index 100% rename from boards/arm/wio_terminal/pre_dt_board.cmake rename to boards/seeed/wio_terminal/pre_dt_board.cmake diff --git a/boards/arm/wio_terminal/raspberrypi_40pins_connector.dtsi b/boards/seeed/wio_terminal/raspberrypi_40pins_connector.dtsi similarity index 100% rename from boards/arm/wio_terminal/raspberrypi_40pins_connector.dtsi rename to boards/seeed/wio_terminal/raspberrypi_40pins_connector.dtsi diff --git a/boards/arm/wio_terminal/support/openocd.cfg b/boards/seeed/wio_terminal/support/openocd.cfg similarity index 100% rename from boards/arm/wio_terminal/support/openocd.cfg rename to boards/seeed/wio_terminal/support/openocd.cfg diff --git a/boards/arm/wio_terminal/wio_terminal-pinctrl.dtsi b/boards/seeed/wio_terminal/wio_terminal-pinctrl.dtsi similarity index 100% rename from boards/arm/wio_terminal/wio_terminal-pinctrl.dtsi rename to boards/seeed/wio_terminal/wio_terminal-pinctrl.dtsi diff --git a/boards/arm/wio_terminal/wio_terminal.dts b/boards/seeed/wio_terminal/wio_terminal.dts similarity index 100% rename from boards/arm/wio_terminal/wio_terminal.dts rename to boards/seeed/wio_terminal/wio_terminal.dts diff --git a/boards/arm/wio_terminal/wio_terminal.yaml b/boards/seeed/wio_terminal/wio_terminal.yaml similarity index 100% rename from boards/arm/wio_terminal/wio_terminal.yaml rename to boards/seeed/wio_terminal/wio_terminal.yaml diff --git a/boards/arm/wio_terminal/wio_terminal_defconfig b/boards/seeed/wio_terminal/wio_terminal_defconfig similarity index 87% rename from boards/arm/wio_terminal/wio_terminal_defconfig rename to boards/seeed/wio_terminal/wio_terminal_defconfig index 353a699c150..20852ef411e 100644 --- a/boards/arm/wio_terminal/wio_terminal_defconfig +++ b/boards/seeed/wio_terminal/wio_terminal_defconfig @@ -1,16 +1,14 @@ # Copyright (c) 2023 Joel Guittet +# Copyright (c) 2024 Gerson Fernando Budke # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_SAMD51=y -CONFIG_SOC_PART_NUMBER_SAMD51P19A=y CONFIG_SOC_ATMEL_SAMD5X_XOSC32K=y CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN=y -CONFIG_BOARD_WIO_TERMINAL=y + CONFIG_ARM_MPU=y CONFIG_CORTEX_M_SYSTICK=y CONFIG_HW_STACK_PROTECTION=y CONFIG_REGULATOR=y -CONFIG_GPIO=y # BOSSA bootloader CONFIG_BOOTLOADER_BOSSA=y diff --git a/boards/arm/xiao_ble/Kconfig b/boards/seeed/xiao_ble/Kconfig similarity index 100% rename from boards/arm/xiao_ble/Kconfig rename to boards/seeed/xiao_ble/Kconfig diff --git a/boards/seeed/xiao_ble/Kconfig.defconfig b/boards/seeed/xiao_ble/Kconfig.defconfig new file mode 100644 index 00000000000..d02785ec152 --- /dev/null +++ b/boards/seeed/xiao_ble/Kconfig.defconfig @@ -0,0 +1,21 @@ +# XIAO BLE board configuration + +# Copyright (c) 2022 Marcin Niestroj +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XIAO_BLE + +config BT_CTLR + default BT + +if USB_DEVICE_STACK + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y + +endif # USB_DEVICE_STACK + +endif # BOARD_XIAO_BLE diff --git a/boards/seeed/xiao_ble/Kconfig.xiao_ble b/boards/seeed/xiao_ble/Kconfig.xiao_ble new file mode 100644 index 00000000000..8901b7dcbdb --- /dev/null +++ b/boards/seeed/xiao_ble/Kconfig.xiao_ble @@ -0,0 +1,7 @@ +# XIAO BLE board configuration + +# Copyright (c) 2022 Marcin Niestroj +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_BLE + select SOC_NRF52840_QIAA diff --git a/boards/arm/xiao_ble/board.cmake b/boards/seeed/xiao_ble/board.cmake similarity index 100% rename from boards/arm/xiao_ble/board.cmake rename to boards/seeed/xiao_ble/board.cmake diff --git a/boards/seeed/xiao_ble/board.yml b/boards/seeed/xiao_ble/board.yml new file mode 100644 index 00000000000..3f83399a7fb --- /dev/null +++ b/boards/seeed/xiao_ble/board.yml @@ -0,0 +1,7 @@ +board: + name: xiao_ble + vendor: seeed + socs: + - name: nrf52840 + variants: + - name: 'sense' diff --git a/boards/arm/xiao_ble/doc/img/xiao_ble.jpg b/boards/seeed/xiao_ble/doc/img/xiao_ble.jpg similarity index 100% rename from boards/arm/xiao_ble/doc/img/xiao_ble.jpg rename to boards/seeed/xiao_ble/doc/img/xiao_ble.jpg diff --git a/boards/seeed/xiao_ble/doc/index.rst b/boards/seeed/xiao_ble/doc/index.rst new file mode 100644 index 00000000000..a7f0778d3b3 --- /dev/null +++ b/boards/seeed/xiao_ble/doc/index.rst @@ -0,0 +1,219 @@ +.. _xiao_ble: + +XIAO BLE (Sense) +################ + +Overview +******** + +The Seeed XIAO BLE (Sense) is a tiny (21 mm x 17.5 mm) Nordic Semiconductor +nRF52840 ARM Cortex-M4F development board with onboard LEDs, USB port, QSPI +flash, battery charger, and range of I/O broken out into 14 pins. + +.. figure:: img/xiao_ble.jpg + :align: center + :alt: XIAO BLE + +Hardware +******** + +- Nordic nRF52840 Cortex-M4F processor at 64MHz +- 2MB QSPI Flash +- RGB LED +- USB Type-C Connector, nRF52840 acting as USB device +- Battery charger BQ25101 +- Reset button +- Bluetooth antenna +- LSM6DS3TR-C 6D IMU (3D accelerometer and 3D gyroscope) (XIAO BLE Sense only) +- PDM microphone (XIAO BLE Sense only) + +Supported Features +================== + +The xiao_ble board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash, QSPI flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +The `XIAO BLE wiki`_ has detailed information about the board including +`pinouts`_ and the `schematic`_. + +LED +--- + +* LED1 (red) = P0.26 +* LED2 (green) = P0.30 +* LED3 (blue) = P0.06 + +Programming and Debugging +************************* + +The XIAO BLE ships with the `Adafruit nRF52 Bootloader`_ which supports flashing +using `UF2`_. Doing so allows easy flashing of new images, but does not support +debugging the device. For debugging please use `External Debugger`_. + +UF2 Flashing +============ + +To enter the bootloader, connect the USB port of the XIAO BLE to your host, and +double tap the reset botton to the left of the USB connector. A mass storage +device named `XIAO BLE` should appear on the host. Using the command line, or +your file manager copy the `zephyr/zephyr.uf2` file from your build to the base +of the `XIAO BLE` mass storage device. The XIAO BLE will automatically reset +and launch the newly flashed application. + +External Debugger +================= + +In order to support debugging the device, instead of using the bootloader, you +can use an :ref:`External Debug Probe `. To flash and debug Zephyr +applications you need to use `Seeeduino XIAO Expansion Board`_ or solder an SWD +header onto the back side of the board. + +For Segger J-Link debug probes, follow the instructions in the +:ref:`jlink-external-debug-probe` page to install and configure all the +necessary software. + +Flashing +-------- + +Setup and connect a supported debug probe (JLink, instructions at :ref:`jlink-external-debug-probe` or +BlackMagic Probe). Then build and flash applications as +usual (see :ref:`build_an_application` and :ref:`application_run` for more +details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board XIAO BLE +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. Just add +``CONFIG_BOOT_DELAY=5000`` to the configuration, so that USB CDC ACM is +initialized before any text is printed, as below: + +.. tabs:: + + .. group-tab:: XIAO BLE + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_ble + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + + .. group-tab:: XIAO BLE Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_ble/nrf52840/sense + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + +Debugging +--------- + +Refer to the :ref:`jlink-external-debug-probe` page to learn about debugging +boards with a Segger IC. + +Debugging using a BlackMagic Probe is also supported. + +Testing the LEDs in the XIAO BLE (Sense) +**************************************** + +There is a sample that allows to test that LEDs on the board are working +properly with Zephyr: + +.. tabs:: + + .. group-tab:: XIAO BLE + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: xiao_ble + :goals: build flash + + .. group-tab:: XIAO BLE Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: xiao_ble/nrf52840/sense + :goals: build flash + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The LED definitions can be found in +:zephyr_file:`boards/seeed_studio/xiao_ble/xiao_ble_common.dtsi`. + +Testing shell over USB in the XIAO BLE (Sense) +********************************************** + +There is a sample that allows to test shell interface over USB CDC ACM interface +with Zephyr: + +.. tabs:: + + .. group-tab:: XIAO BLE + + .. zephyr-app-commands:: + :zephyr-app: samples/subsys/shell/shell_module + :board: xiao_ble + :goals: build flash + + .. group-tab:: XIAO BLE Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/subsys/shell/shell_module + :board: xiao_ble/nrf52840/sense + :goals: build flash + +References +********** + +.. target-notes:: + +.. _XIAO BLE wiki: https://wiki.seeedstudio.com/XIAO_BLE/ +.. _pinouts: https://wiki.seeedstudio.com/XIAO_BLE/#hardware-overview +.. _schematic: https://wiki.seeedstudio.com/XIAO_BLE/#resources +.. _Seeeduino XIAO Expansion Board: https://wiki.seeedstudio.com/Seeeduino-XIAO-Expansion-Board/ +.. _Adafruit nRF52 Bootloader: https://github.com/adafruit/Adafruit_nRF52_Bootloader +.. _UF2: https://github.com/microsoft/uf2 diff --git a/boards/arm/reel_board/pre_dt_board.cmake b/boards/seeed/xiao_ble/pre_dt_board.cmake similarity index 100% rename from boards/arm/reel_board/pre_dt_board.cmake rename to boards/seeed/xiao_ble/pre_dt_board.cmake diff --git a/boards/arm/xiao_ble/seeed_xiao_connector.dtsi b/boards/seeed/xiao_ble/seeed_xiao_connector.dtsi similarity index 100% rename from boards/arm/xiao_ble/seeed_xiao_connector.dtsi rename to boards/seeed/xiao_ble/seeed_xiao_connector.dtsi diff --git a/boards/arm/xiao_ble/xiao_ble-pinctrl.dtsi b/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi similarity index 100% rename from boards/arm/xiao_ble/xiao_ble-pinctrl.dtsi rename to boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi diff --git a/boards/arm/xiao_ble/xiao_ble.dts b/boards/seeed/xiao_ble/xiao_ble.dts similarity index 100% rename from boards/arm/xiao_ble/xiao_ble.dts rename to boards/seeed/xiao_ble/xiao_ble.dts diff --git a/boards/arm/xiao_ble/xiao_ble.yaml b/boards/seeed/xiao_ble/xiao_ble.yaml similarity index 100% rename from boards/arm/xiao_ble/xiao_ble.yaml rename to boards/seeed/xiao_ble/xiao_ble.yaml diff --git a/boards/arm/xiao_ble/xiao_ble_common.dtsi b/boards/seeed/xiao_ble/xiao_ble_common.dtsi similarity index 100% rename from boards/arm/xiao_ble/xiao_ble_common.dtsi rename to boards/seeed/xiao_ble/xiao_ble_common.dtsi diff --git a/boards/seeed/xiao_ble/xiao_ble_defconfig b/boards/seeed/xiao_ble/xiao_ble_defconfig new file mode 100644 index 00000000000..84eb3e97f22 --- /dev/null +++ b/boards/seeed/xiao_ble/xiao_ble_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y + +# Logger cannot use itself to log +CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y + +# Enable USB +CONFIG_USB_DEVICE_STACK=y + +# Build UF2 by default, supported by the Adafruit nRF52 Bootloader +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/xiao_ble/xiao_ble_sense.dts b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts similarity index 100% rename from boards/arm/xiao_ble/xiao_ble_sense.dts rename to boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts diff --git a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml new file mode 100644 index 00000000000..dfb8bc4e8af --- /dev/null +++ b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml @@ -0,0 +1,24 @@ +identifier: xiao_ble/nrf52840/sense +name: XIAO BLE Sense +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - ble + - counter + - gpio + - i2c + - i2s + - pwm + - spi + - usb_cdc + - usb_device + - watchdog + - netif:openthread +vendor: seeed diff --git a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig new file mode 100644 index 00000000000..ff4b012b93c --- /dev/null +++ b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Required to enable LSM6DS3TR-C power +CONFIG_REGULATOR=y diff --git a/boards/seeed/xiao_esp32c3/Kconfig.defconfig b/boards/seeed/xiao_esp32c3/Kconfig.defconfig new file mode 100644 index 00000000000..f70e724ed8e --- /dev/null +++ b/boards/seeed/xiao_esp32c3/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright 2022 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice diff --git a/boards/xtensa/xiao_esp32s3/Kconfig.sysbuild b/boards/seeed/xiao_esp32c3/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/xiao_esp32s3/Kconfig.sysbuild rename to boards/seeed/xiao_esp32c3/Kconfig.sysbuild diff --git a/boards/seeed/xiao_esp32c3/Kconfig.xiao_esp32c3 b/boards/seeed/xiao_esp32c3/Kconfig.xiao_esp32c3 new file mode 100644 index 00000000000..e4db49fc4a6 --- /dev/null +++ b/boards/seeed/xiao_esp32c3/Kconfig.xiao_esp32c3 @@ -0,0 +1,5 @@ +# Copyright 2022 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_ESP32C3 + select SOC_ESP32C3_FX4 diff --git a/boards/xtensa/m5stack_stamps3/board.cmake b/boards/seeed/xiao_esp32c3/board.cmake similarity index 100% rename from boards/xtensa/m5stack_stamps3/board.cmake rename to boards/seeed/xiao_esp32c3/board.cmake diff --git a/boards/seeed/xiao_esp32c3/board.yml b/boards/seeed/xiao_esp32c3/board.yml new file mode 100644 index 00000000000..2bd54cf346f --- /dev/null +++ b/boards/seeed/xiao_esp32c3/board.yml @@ -0,0 +1,5 @@ +board: + name: xiao_esp32c3 + vendor: seeed + socs: + - name: esp32c3 diff --git a/boards/riscv/xiao_esp32c3/doc/img/xiao_esp32c.jpg b/boards/seeed/xiao_esp32c3/doc/img/xiao_esp32c.jpg similarity index 100% rename from boards/riscv/xiao_esp32c3/doc/img/xiao_esp32c.jpg rename to boards/seeed/xiao_esp32c3/doc/img/xiao_esp32c.jpg diff --git a/boards/riscv/xiao_esp32c3/doc/img/xiao_esp32c3_pinout.jpg b/boards/seeed/xiao_esp32c3/doc/img/xiao_esp32c3_pinout.jpg similarity index 100% rename from boards/riscv/xiao_esp32c3/doc/img/xiao_esp32c3_pinout.jpg rename to boards/seeed/xiao_esp32c3/doc/img/xiao_esp32c3_pinout.jpg diff --git a/boards/seeed/xiao_esp32c3/doc/index.rst b/boards/seeed/xiao_esp32c3/doc/index.rst new file mode 100644 index 00000000000..11d5109b3cf --- /dev/null +++ b/boards/seeed/xiao_esp32c3/doc/index.rst @@ -0,0 +1,218 @@ +.. _xiao_esp32c3: + +XIAO ESP32C3 +############ + +Overview +******** + +Seeed Studio XIAO ESP32C3 is an IoT mini development board based on the +Espressif ESP32-C3 WiFi/Bluetooth dual-mode chip. + +For more details see the `Seeed Studio XIAO ESP32C3`_ wiki page. + +.. figure:: img/xiao_esp32c.jpg + :align: center + :alt: XIAO ESP32C3 + + XIAO ESP32C3 + +Hardware +******** + +This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It +has an USB-C port for programming and debugging, integrated battery charging +and an U.FL external antenna connector. It is based on a standard XIAO 14 pin +pinout. + +Supported Features +================== + +The XIAO ESP32C3 board configuration supports the following hardware features: + ++-----------+------------+------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==================+ +| PMP | on-chip | arch/riscv | ++-----------+------------+------------------+ +| INTMTRX | on-chip | intc_esp32c3 | ++-----------+------------+------------------+ +| PINMUX | on-chip | pinctrl_esp32 | ++-----------+------------+------------------+ +| USB UART | on-chip | serial_esp32_usb | ++-----------+------------+------------------+ +| GPIO | on-chip | gpio_esp32 | ++-----------+------------+------------------+ +| UART | on-chip | uart_esp32 | ++-----------+------------+------------------+ +| I2C | on-chip | i2c_esp32 | ++-----------+------------+------------------+ +| SPI | on-chip | spi_esp32_spim | ++-----------+------------+------------------+ +| TWAI | on-chip | can_esp32_twai | ++-----------+------------+------------------+ + +Connections and IOs +=================== + +The board uses a standard XIAO pinout, the default pin mapping is the following: + +.. figure:: img/xiao_esp32c3_pinout.jpg + :align: center + :alt: XIAO ESP32C3 Pinout + + XIAO ESP32C3 Pinout + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: xiao_esp32c3 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by Sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +For the :code:`Hello, world!` application, follow the instructions below. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c3 + :goals: build flash + +Since the Zephyr console is by default on the `usb_serial` device, we use +the espressif monitor to view. + +.. code-block:: console + + $ west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! xiao_esp32c3 + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c3 + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c3 + :goals: debug + +References +********** + +.. target-notes:: + +.. _`Seeed Studio XIAO ESP32C3`: https://wiki.seeedstudio.com/XIAO_ESP32C3_Getting_Started +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/riscv/xiao_esp32c3/seeed_xiao_connector.dtsi b/boards/seeed/xiao_esp32c3/seeed_xiao_connector.dtsi similarity index 100% rename from boards/riscv/xiao_esp32c3/seeed_xiao_connector.dtsi rename to boards/seeed/xiao_esp32c3/seeed_xiao_connector.dtsi diff --git a/boards/riscv/xiao_esp32c3/support/openocd.cfg b/boards/seeed/xiao_esp32c3/support/openocd.cfg similarity index 100% rename from boards/riscv/xiao_esp32c3/support/openocd.cfg rename to boards/seeed/xiao_esp32c3/support/openocd.cfg diff --git a/boards/riscv/xiao_esp32c3/xiao_esp32c3-pinctrl.dtsi b/boards/seeed/xiao_esp32c3/xiao_esp32c3-pinctrl.dtsi similarity index 100% rename from boards/riscv/xiao_esp32c3/xiao_esp32c3-pinctrl.dtsi rename to boards/seeed/xiao_esp32c3/xiao_esp32c3-pinctrl.dtsi diff --git a/boards/riscv/xiao_esp32c3/xiao_esp32c3.dts b/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts similarity index 100% rename from boards/riscv/xiao_esp32c3/xiao_esp32c3.dts rename to boards/seeed/xiao_esp32c3/xiao_esp32c3.dts diff --git a/boards/riscv/xiao_esp32c3/xiao_esp32c3.yaml b/boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml similarity index 100% rename from boards/riscv/xiao_esp32c3/xiao_esp32c3.yaml rename to boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml diff --git a/boards/seeed/xiao_esp32c3/xiao_esp32c3_defconfig b/boards/seeed/xiao_esp32c3/xiao_esp32c3_defconfig new file mode 100644 index 00000000000..ef633ce56a1 --- /dev/null +++ b/boards/seeed/xiao_esp32c3/xiao_esp32c3_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/seeed/xiao_esp32s3/Kconfig b/boards/seeed/xiao_esp32s3/Kconfig new file mode 100644 index 00000000000..20855be092e --- /dev/null +++ b/boards/seeed/xiao_esp32s3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_ESP32S3 + select SOC_ESP32S3_PROCPU if BOARD_XIAO_ESP32S3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_XIAO_ESP32S3_ESP32S3_APPCPU diff --git a/boards/seeed/xiao_esp32s3/Kconfig.defconfig b/boards/seeed/xiao_esp32s3/Kconfig.defconfig new file mode 100644 index 00000000000..424820d78ad --- /dev/null +++ b/boards/seeed/xiao_esp32s3/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Seeed Studio inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XIAO_ESP32S3_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_XIAO_ESP32S3_ESP32S3_PROCPU + +if BOARD_XIAO_ESP32S3_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_XIAO_ESP32S3_ESP32S3_APPCPU diff --git a/boards/xtensa/yd_esp32/Kconfig.sysbuild b/boards/seeed/xiao_esp32s3/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/yd_esp32/Kconfig.sysbuild rename to boards/seeed/xiao_esp32s3/Kconfig.sysbuild diff --git a/boards/seeed/xiao_esp32s3/Kconfig.xiao_esp32s3 b/boards/seeed/xiao_esp32s3/Kconfig.xiao_esp32s3 new file mode 100644 index 00000000000..68c6020cd52 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/Kconfig.xiao_esp32s3 @@ -0,0 +1,7 @@ +# XIAO ESP32S3 board configuration + +# Copyright (c) 2023 Seeed Studio inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_ESP32S3 + select SOC_ESP32S3_WROOM_N8R8 diff --git a/boards/xtensa/olimex_esp32_evb/board.cmake b/boards/seeed/xiao_esp32s3/board.cmake similarity index 100% rename from boards/xtensa/olimex_esp32_evb/board.cmake rename to boards/seeed/xiao_esp32s3/board.cmake diff --git a/boards/seeed/xiao_esp32s3/board.yml b/boards/seeed/xiao_esp32s3/board.yml new file mode 100644 index 00000000000..02ba87e5bc2 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/board.yml @@ -0,0 +1,5 @@ +board: + name: xiao_esp32s3 + vendor: seeed + socs: + - name: esp32s3 diff --git a/boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3.jpg b/boards/seeed/xiao_esp32s3/doc/img/xiao_esp32s3.jpg similarity index 100% rename from boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3.jpg rename to boards/seeed/xiao_esp32s3/doc/img/xiao_esp32s3.jpg diff --git a/boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3_pinout.jpg b/boards/seeed/xiao_esp32s3/doc/img/xiao_esp32s3_pinout.jpg similarity index 100% rename from boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3_pinout.jpg rename to boards/seeed/xiao_esp32s3/doc/img/xiao_esp32s3_pinout.jpg diff --git a/boards/seeed/xiao_esp32s3/doc/index.rst b/boards/seeed/xiao_esp32s3/doc/index.rst new file mode 100644 index 00000000000..1880e6ff9a4 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/doc/index.rst @@ -0,0 +1,243 @@ +.. _xiao_esp32s3: + +XIAO ESP32S3 +############ + +Overview +******** + +Seeed Studio XIAO ESP32S3 is an IoT mini development board based on the +Espressif ESP32-S3 WiFi/Bluetooth dual-mode chip. + +For more details see the `Seeed Studio XIAO ESP32S3`_ wiki page. + +.. figure:: img/xiao_esp32s3.jpg + :align: center + :alt: XIAO ESP32S3 + + XIAO ESP32S3 + +Hardware +******** + +This board is based on the ESP32-S3 with 8MB of flash, WiFi and BLE support. It +has an USB-C port for programming and debugging, integrated battery charging +and an U.FL external antenna connector. It is based on a standard XIAO 14 pin +pinout. + +ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi +and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor +(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, +RF module, and numerous peripherals. + +Supported Features +================== + +Current Zephyr's XIAO ESP32S3 board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ + +Connections and IOs +=================== + +The board uses a standard XIAO pinout, the default pin mapping is the following: + +.. figure:: img/xiao_esp32s3_pinout.jpg + :align: center + :alt: XIAO ESP32S3 Pinout + + XIAO ESP32S3 Pinout + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: xiao_esp32s3 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``xiao_esp32s3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! xiao_esp32s3 + +Debugging +********* + +ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32-S3`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32/procpu + :goals: debug +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD`: https://github.com/openocd-org/openocd + +References +********** + +.. target-notes:: + +.. _`Seeed Studio XIAO ESP32S3`: https://wiki.seeedstudio.com/xiao_esp32s3_getting_started/ diff --git a/boards/xtensa/xiao_esp32s3/seeed_xiao_connector.dtsi b/boards/seeed/xiao_esp32s3/seeed_xiao_connector.dtsi similarity index 100% rename from boards/xtensa/xiao_esp32s3/seeed_xiao_connector.dtsi rename to boards/seeed/xiao_esp32s3/seeed_xiao_connector.dtsi diff --git a/boards/xtensa/xiao_esp32s3/support/openocd.cfg b/boards/seeed/xiao_esp32s3/support/openocd.cfg similarity index 100% rename from boards/xtensa/xiao_esp32s3/support/openocd.cfg rename to boards/seeed/xiao_esp32s3/support/openocd.cfg diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi b/boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi similarity index 100% rename from boards/xtensa/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi rename to boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.dts new file mode 100644 index 00000000000..672c52a5cba --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "Seeed Xiao ESP32S3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.yaml b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.yaml new file mode 100644 index 00000000000..5d66048e038 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: xiao_esp32s3/esp32s3/appcpu +name: XIAO ESP32S3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: seeed diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu_defconfig b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.dts new file mode 100644 index 00000000000..99d7f0deb75 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.dts @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2023 Seeed Studio inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "xiao_esp32s3-pinctrl.dtsi" +#include "seeed_xiao_connector.dtsi" + +/ { + model = "Seeed Xiao ESP32S3 PROCPU"; + compatible = "seeed,xiao-esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + led0 = &led0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + label = "BUILTIN LED"; + }; + }; + +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; + bus-speed = <125000>; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.yaml b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.yaml new file mode 100644 index 00000000000..8a1ace79ba6 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.yaml @@ -0,0 +1,22 @@ +identifier: xiao_esp32s3/esp32s3/procpu +name: XIAO ESP32S3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma +testing: + ignore_tags: + - net + - bluetooth +vendor: seeed diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu_defconfig b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu_defconfig new file mode 100644 index 00000000000..6539bd42e59 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/segger/index.rst b/boards/segger/index.rst new file mode 100644 index 00000000000..ec863c07d2d --- /dev/null +++ b/boards/segger/index.rst @@ -0,0 +1,10 @@ +.. _boards-segger: + +SEGGER Microcontroller GmbH +########################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/ip_k66f/CMakeLists.txt b/boards/segger/ip_k66f/CMakeLists.txt similarity index 100% rename from boards/arm/ip_k66f/CMakeLists.txt rename to boards/segger/ip_k66f/CMakeLists.txt diff --git a/boards/segger/ip_k66f/Kconfig.defconfig b/boards/segger/ip_k66f/Kconfig.defconfig new file mode 100644 index 00000000000..06952ee0707 --- /dev/null +++ b/boards/segger/ip_k66f/Kconfig.defconfig @@ -0,0 +1,33 @@ +# IP-K66F board + +# Copyright (c) 2020 DENX Software Engineering GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IP_K66F + +config OSC_XTAL0_FREQ + default 12000000 + +config MCG_PRDIV0 + default 0x0 + +config MCG_VDIV0 + default 0xe + +config MCG_FCRDIV + default 1 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config ETH_MCUX_RMII_EXT_CLK + default y if ETH_MCUX + +config ETH_MCUX_NO_PHY_SMI + default y if ETH_MCUX + +endif # NETWORKING + +endif # BOARD_IP_K66F diff --git a/boards/segger/ip_k66f/Kconfig.ip_k66f b/boards/segger/ip_k66f/Kconfig.ip_k66f new file mode 100644 index 00000000000..22ec9ddf3e3 --- /dev/null +++ b/boards/segger/ip_k66f/Kconfig.ip_k66f @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IP_K66F + select SOC_MK66F18 + select SOC_PART_NUMBER_MK66FN2M0VMD18 diff --git a/boards/arm/ip_k66f/board.cmake b/boards/segger/ip_k66f/board.cmake similarity index 100% rename from boards/arm/ip_k66f/board.cmake rename to boards/segger/ip_k66f/board.cmake diff --git a/boards/segger/ip_k66f/board.yml b/boards/segger/ip_k66f/board.yml new file mode 100644 index 00000000000..c1593280a49 --- /dev/null +++ b/boards/segger/ip_k66f/board.yml @@ -0,0 +1,5 @@ +board: + name: ip_k66f + vendor: segger + socs: + - name: mk66f18 diff --git a/boards/segger/ip_k66f/doc/index.rst b/boards/segger/ip_k66f/doc/index.rst new file mode 100644 index 00000000000..5b4cd7195f0 --- /dev/null +++ b/boards/segger/ip_k66f/doc/index.rst @@ -0,0 +1,174 @@ +.. _ip_k66f: + +SEGGER IP Switch Board +###################### + +Overview +******** + +The Segger IP Switch Board is a Evaluation board based on NXP Kinetis K66 MCU. +It comes with Micrel/Microchip KSZ8794CNX integrated 4-port 10/100 managed +Ethernet switch with Gigabit RGMII/MII/RMII interface. + +- KSZ8794CNX enables evaluation for switch functions +- On-board debug probe J-Link-OB for programming + +.. image:: ip_k66f.jpg + :align: center + :alt: IP-K66F + +Hardware +******** + +- MK66FN2M0VMD18 MCU (180 MHz, 2 MB flash memory, 256 KB RAM, low-power, + crystal-less USB +- Dual role USB interface with micro-B USB connector +- 2 User LED +- On-board debug probe J-Link-OB for programming +- Micrel/Microchip Ethernet Switch KSZ8794CNX with 3 RJ45 connectors + +For more information about the K66F SoC and IP-K66F board: + +- `K66F Website`_ +- `K66F Datasheet`_ +- `K66F Reference Manual`_ +- `IP-K66F Website`_ +- `IP-K66F User Guide`_ +- `IP-K66F Schematics`_ + +Supported Features +================== + +The ip_k66f board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/segger/ip_k66f/ip_k66f_defconfig` + +Micrel/Microchip KSZ8794CNX Ethernet Switch is not currently +supported. + +Connections and IOs +=================== + +The K66F SoC has five pairs of pinmux/gpio controllers. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTA8 | GPIO | Red LED | ++-------+-----------------+---------------------------+ +| PTA10 | GPIO | RED LED | ++-------+-----------------+---------------------------+ + +System Clock +============ + +The K66F SoC is configured to use the 12 MHz low gain crystal oscillator on the +board with the on-chip PLL to generate a 180 MHz system clock. + +Serial Port +=========== + +The K66F SoC has six UARTs. None of them are used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-jlink-onboard-debug-probe`. + +:ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Generic Firmware for V3.2 Bootloader`_. Note that Segger +does provide an OpenSDA J-Link Board-Specific Firmware for this board, however +it is not compatible with the DAPLink bootloader. + +The default flasher is ``jlink`` using the built-in SEGGER Jlink interface. + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ip_k66f + :goals: flash + +Red LED0 should blink at 1 second delay. + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ip_k66f + :goals: debug + +Step through the application in your debugger. + +.. _IP-K66F Website: + https://www.segger.com/evaluate-our-software/segger/embosip-switch-board/ + +.. _IP-K66F User Guide: + https://www.segger.com/downloads/emnet/UM06002 + +.. _IP-K66F Schematics: + https://www.segger.com/downloads/emnet/embOSIP_SwitchBoard_V2.0_WEB_Schematic.pdf + +.. _K66F Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k6x-ethernet/kinetis-k66-180-mhz-dual-high-speed-full-speed-usbs-2mb-flash-microcontrollers-mcus-based-on-arm-cortex-m4-core:K66_180 + +.. _K66F Datasheet: + https://www.nxp.com/docs/en/data-sheet/K66P144M180SF5V2.pdf + +.. _K66F Reference Manual: + https://www.nxp.com/webapp/Download?colCode=K66P144M180SF5RMV2 + +.. _OpenSDA J-Link Generic Firmware for V3.2 Bootloader: + https://www.segger.com/downloads/jlink/OpenSDA_V3_2 + +Serial console +============== + +The ``ip_k66f`` board only uses Segger's RTT console for providing serial +console. There is no physical serial port available. + +- To communicate with this board one needs in one console: + +``/opt/SEGGER/JLink_V664/JLinkRTTLogger -Device MK66FN2M0XXX18 -RTTChannel 1 -if SWD -Speed 4000 ~/rtt.log`` + +- In another one: + +``nc localhost 19021`` diff --git a/boards/arm/ip_k66f/doc/ip_k66f.jpg b/boards/segger/ip_k66f/doc/ip_k66f.jpg similarity index 100% rename from boards/arm/ip_k66f/doc/ip_k66f.jpg rename to boards/segger/ip_k66f/doc/ip_k66f.jpg diff --git a/boards/arm/ip_k66f/ip_k66f-pinctrl.dtsi b/boards/segger/ip_k66f/ip_k66f-pinctrl.dtsi similarity index 100% rename from boards/arm/ip_k66f/ip_k66f-pinctrl.dtsi rename to boards/segger/ip_k66f/ip_k66f-pinctrl.dtsi diff --git a/boards/arm/ip_k66f/ip_k66f.dts b/boards/segger/ip_k66f/ip_k66f.dts similarity index 100% rename from boards/arm/ip_k66f/ip_k66f.dts rename to boards/segger/ip_k66f/ip_k66f.dts diff --git a/boards/arm/ip_k66f/ip_k66f.yaml b/boards/segger/ip_k66f/ip_k66f.yaml similarity index 100% rename from boards/arm/ip_k66f/ip_k66f.yaml rename to boards/segger/ip_k66f/ip_k66f.yaml diff --git a/boards/arm/ip_k66f/ip_k66f_defconfig b/boards/segger/ip_k66f/ip_k66f_defconfig similarity index 81% rename from boards/arm/ip_k66f/ip_k66f_defconfig rename to boards/segger/ip_k66f/ip_k66f_defconfig index 6bb29071f79..3a283228faf 100644 --- a/boards/arm/ip_k66f/ip_k66f_defconfig +++ b/boards/segger/ip_k66f/ip_k66f_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_MK66F18=y -CONFIG_SOC_SERIES_KINETIS_K6X=y -CONFIG_BOARD_IP_K66F=y CONFIG_GPIO=y CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000 diff --git a/boards/arm/ip_k66f/linker.ld b/boards/segger/ip_k66f/linker.ld similarity index 100% rename from boards/arm/ip_k66f/linker.ld rename to boards/segger/ip_k66f/linker.ld diff --git a/boards/arm/ip_k66f/support/openocd.cfg b/boards/segger/ip_k66f/support/openocd.cfg similarity index 100% rename from boards/arm/ip_k66f/support/openocd.cfg rename to boards/segger/ip_k66f/support/openocd.cfg diff --git a/boards/segger/trb_stm32f407/CMakeLists.txt b/boards/segger/trb_stm32f407/CMakeLists.txt new file mode 100644 index 00000000000..9881313609a --- /dev/null +++ b/boards/segger/trb_stm32f407/CMakeLists.txt @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/segger/trb_stm32f407/Kconfig.segger_trb_stm32f407 b/boards/segger/trb_stm32f407/Kconfig.segger_trb_stm32f407 new file mode 100644 index 00000000000..91d1e6a9b17 --- /dev/null +++ b/boards/segger/trb_stm32f407/Kconfig.segger_trb_stm32f407 @@ -0,0 +1,5 @@ +# Copyright (c) 2020, Erwin Rol +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SEGGER_TRB_STM32F407 + select SOC_STM32F407XE diff --git a/boards/arm/segger_trb_stm32f407/board.cmake b/boards/segger/trb_stm32f407/board.cmake similarity index 100% rename from boards/arm/segger_trb_stm32f407/board.cmake rename to boards/segger/trb_stm32f407/board.cmake diff --git a/boards/segger/trb_stm32f407/board.yml b/boards/segger/trb_stm32f407/board.yml new file mode 100644 index 00000000000..52ba24a33eb --- /dev/null +++ b/boards/segger/trb_stm32f407/board.yml @@ -0,0 +1,5 @@ +board: + name: segger_trb_stm32f407 + vendor: segger + socs: + - name: stm32f407xx diff --git a/boards/arm/segger_trb_stm32f407/doc/img/segger_trb_stm32f407.jpg b/boards/segger/trb_stm32f407/doc/img/segger_trb_stm32f407.jpg similarity index 100% rename from boards/arm/segger_trb_stm32f407/doc/img/segger_trb_stm32f407.jpg rename to boards/segger/trb_stm32f407/doc/img/segger_trb_stm32f407.jpg diff --git a/boards/arm/segger_trb_stm32f407/doc/index.rst b/boards/segger/trb_stm32f407/doc/index.rst similarity index 100% rename from boards/arm/segger_trb_stm32f407/doc/index.rst rename to boards/segger/trb_stm32f407/doc/index.rst diff --git a/boards/arm/segger_trb_stm32f407/segger_trb_stm32f407.dts b/boards/segger/trb_stm32f407/segger_trb_stm32f407.dts similarity index 100% rename from boards/arm/segger_trb_stm32f407/segger_trb_stm32f407.dts rename to boards/segger/trb_stm32f407/segger_trb_stm32f407.dts diff --git a/boards/arm/segger_trb_stm32f407/segger_trb_stm32f407.yaml b/boards/segger/trb_stm32f407/segger_trb_stm32f407.yaml similarity index 100% rename from boards/arm/segger_trb_stm32f407/segger_trb_stm32f407.yaml rename to boards/segger/trb_stm32f407/segger_trb_stm32f407.yaml diff --git a/boards/arm/segger_trb_stm32f407/segger_trb_stm32f407_defconfig b/boards/segger/trb_stm32f407/segger_trb_stm32f407_defconfig similarity index 86% rename from boards/arm/segger_trb_stm32f407/segger_trb_stm32f407_defconfig rename to boards/segger/trb_stm32f407/segger_trb_stm32f407_defconfig index 0ae4151a7d2..9e96c29aafd 100644 --- a/boards/arm/segger_trb_stm32f407/segger_trb_stm32f407_defconfig +++ b/boards/segger/trb_stm32f407/segger_trb_stm32f407_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst b/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst index 330a8ffd11a..209b3029389 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst +++ b/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst @@ -61,7 +61,7 @@ Set ``-DSHIELD=adafruit_2_8_tft_touch_v2`` when you invoke ``west build``. For e .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: adafruit_2_8_tft_touch_v2 :goals: build diff --git a/boards/shields/adafruit_pca9685/doc/index.rst b/boards/shields/adafruit_pca9685/doc/index.rst index cb3e08e0d3f..ee6f1649fce 100644 --- a/boards/shields/adafruit_pca9685/doc/index.rst +++ b/boards/shields/adafruit_pca9685/doc/index.rst @@ -32,7 +32,7 @@ For example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/led_pwm - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: adafruit_pca9685 :goals: build diff --git a/boards/shields/arceli_eth_w5500/doc/index.rst b/boards/shields/arceli_eth_w5500/doc/index.rst index 359a91e482a..467559be881 100644 --- a/boards/shields/arceli_eth_w5500/doc/index.rst +++ b/boards/shields/arceli_eth_w5500/doc/index.rst @@ -43,7 +43,7 @@ Set ``-DSHIELD=arceli_eth_w5500`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/net/dhcpv4_client - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: arceli_eth_w5500 :goals: build diff --git a/boards/shields/arduino_uno_click/doc/index.rst b/boards/shields/arduino_uno_click/doc/index.rst index c13c3cb8d8c..4e260a7db43 100644 --- a/boards/shields/arduino_uno_click/doc/index.rst +++ b/boards/shields/arduino_uno_click/doc/index.rst @@ -44,7 +44,7 @@ other mikroBUS shields. For example: .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_server :host-os: unix - :board: sam_v71_xult + :board: sam_v71_xult/samv71q21 :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf :shield: "arduino_uno_click atmel_rf2xx_mikrobus" :goals: build diff --git a/boards/shields/atmel_rf2xx/doc/index.rst b/boards/shields/atmel_rf2xx/doc/index.rst index e9d2777fafe..31670bf936d 100644 --- a/boards/shields/atmel_rf2xx/doc/index.rst +++ b/boards/shields/atmel_rf2xx/doc/index.rst @@ -265,15 +265,15 @@ details). Tested Boards ============= -+-----------------------------+------------------------------+-----------+ -| Board | Disabled Interface | Variation | -+=============================+==============================+===========+ -| ATMEL sam4s_xplained | | 2 | -+-----------------------------+------------------------------+-----------+ -| ATMEL sam4e_xpro | Ethernet | 3 , 4 | -+-----------------------------+------------------------------+-----------+ -| ATMEL sam_v71_xult | Ethernet | 3 , 4 , 5 | -+-----------------------------+------------------------------+-----------+ ++------------------------------+------------------------------+-----------+ +| Board | Disabled Interface | Variation | ++==============================+==============================+===========+ +| ATMEL sam4s_xplained | | 2 | ++------------------------------+------------------------------+-----------+ +| ATMEL sam4e_xpro | Ethernet | 3 , 4 | ++------------------------------+------------------------------+-----------+ +| ATMEL sam_v71_xult/samv71q21 | Ethernet | 3 , 4 , 5 | ++------------------------------+------------------------------+-----------+ Sample usage ************ @@ -303,7 +303,7 @@ Set ``-DSHIELD=`` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_server :host-os: unix - :board: [sam4e_xpro | sam_v71_xult] + :board: [sam4e_xpro | sam_v71_xult/samv71q21] :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf :shield: [atmel_rf2xx_xpro | atmel_rf2xx_legacy] :goals: build flash @@ -312,7 +312,7 @@ Set ``-DSHIELD=`` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_server :host-os: unix - :board: [sam_v71_xult | frdm_k64f | nucleo_f767zi] + :board: [sam_v71_xult/samv71q21 | frdm_k64f | nucleo_f767zi] :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf :shield: atmel_rf2xx_arduino :goals: build flash diff --git a/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst b/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst index ec62df14bf5..ccd4fd1b410 100644 --- a/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst +++ b/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst @@ -61,7 +61,7 @@ Set ``-DSHIELD=buydisplay_2_8_tft_touch_arduino`` when you invoke .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: buydisplay_2_8_tft_touch_arduino :goals: build diff --git a/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst b/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst index 7950e967391..bd8a505339f 100644 --- a/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst +++ b/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst @@ -63,7 +63,7 @@ Set ``-DSHIELD=buydisplay_3_5_tft_touch_arduino`` when you invoke .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: buydisplay_3_5_tft_touch_arduino :goals: build diff --git a/boards/shields/ftdi_vm800c/doc/index.rst b/boards/shields/ftdi_vm800c/doc/index.rst index df72ff21111..b1d2ab2d765 100644 --- a/boards/shields/ftdi_vm800c/doc/index.rst +++ b/boards/shields/ftdi_vm800c/doc/index.rst @@ -80,7 +80,7 @@ Set ``-DSHIELD=`` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/drivers/misc/ft800 :host-os: unix - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: ftdi_vm800c :goals: build flash :compact: diff --git a/boards/shields/g1120b0mipi/boards/mimxrt1170_evk_cm7.overlay b/boards/shields/g1120b0mipi/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from boards/shields/g1120b0mipi/boards/mimxrt1170_evk_cm7.overlay rename to boards/shields/g1120b0mipi/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/boards/shields/g1120b0mipi/boards/mimxrt1170_evkb_cm7.overlay b/boards/shields/g1120b0mipi/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from boards/shields/g1120b0mipi/boards/mimxrt1170_evkb_cm7.overlay rename to boards/shields/g1120b0mipi/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/boards/shields/g1120b0mipi/boards/mimxrt595_evk_cm33.conf b/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from boards/shields/g1120b0mipi/boards/mimxrt595_evk_cm33.conf rename to boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/boards/shields/g1120b0mipi/boards/mimxrt595_evk_cm33.overlay b/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from boards/shields/g1120b0mipi/boards/mimxrt595_evk_cm33.overlay rename to boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/boards/shields/g1120b0mipi/doc/index.rst b/boards/shields/g1120b0mipi/doc/index.rst index ccfeae05833..d13a4b49edc 100644 --- a/boards/shields/g1120b0mipi/doc/index.rst +++ b/boards/shields/g1120b0mipi/doc/index.rst @@ -55,7 +55,7 @@ example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/display - :board: mimxrt595_evk_cm33 + :board: mimxrt595_evk/mimxrt595s/cm33 :shield: g1120b0mipi :goals: build diff --git a/boards/shields/index.rst b/boards/shields/index.rst deleted file mode 100644 index 5a73aba302d..00000000000 --- a/boards/shields/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-shields: - -Shields -####### - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/shields/inventek_eswifi/doc/index.rst b/boards/shields/inventek_eswifi/doc/index.rst index e19713acd3f..9b0d9a46e1d 100644 --- a/boards/shields/inventek_eswifi/doc/index.rst +++ b/boards/shields/inventek_eswifi/doc/index.rst @@ -121,15 +121,15 @@ details). Tested Boards ============= -+-----------------------------+------------------------------+-----------+ -| Board | Disabled Interface | Variation | -+=============================+==============================+===========+ -| ATMEL sam_v71_xult | Ethernet | 2 , 3 | -+-----------------------------+------------------------------+-----------+ -| ST nucleo_f767zi | Ethernet | 2 , 3 | -+-----------------------------+------------------------------+-----------+ -| ST disco_l475_iot1 | | - | -+-----------------------------+------------------------------+-----------+ ++------------------------------+------------------------------+-----------+ +| Board | Disabled Interface | Variation | ++==============================+==============================+===========+ +| ATMEL sam_v71_xult/samv71q21 | Ethernet | 2 , 3 | ++------------------------------+------------------------------+-----------+ +| ST nucleo_f767zi | Ethernet | 2 , 3 | ++------------------------------+------------------------------+-----------+ +| ST disco_l475_iot1 | | - | ++------------------------------+------------------------------+-----------+ .. note:: ST disco_l475_iot1 already have an ISM43362 module with IWIN SPI @@ -152,7 +152,7 @@ Set ``-DSHIELD=`` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/net/wifi :host-os: unix - :board: [sam_v71_xult | nucleo_f767zi] + :board: [sam_v71_xult/samv71q21 | nucleo_f767zi] :shield: inventek_eswifi_arduino_uart :goals: build flash :compact: @@ -160,7 +160,7 @@ Set ``-DSHIELD=`` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/net/wifi :host-os: unix - :board: [sam_v71_xult | nucleo_f767zi] + :board: [sam_v71_xult/samv71q21 | nucleo_f767zi] :shield: inventek_eswifi_arduino_spi :goals: build flash :compact: diff --git a/boards/shields/ls0xx_generic/doc/index.rst b/boards/shields/ls0xx_generic/doc/index.rst index aec3c35e5dd..415dbb0227c 100644 --- a/boards/shields/ls0xx_generic/doc/index.rst +++ b/boards/shields/ls0xx_generic/doc/index.rst @@ -92,7 +92,7 @@ Set ``-DSHIELD=ls013b7dh03`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: ls013b7dh03 :goals: build diff --git a/boards/shields/m5stack_core2_ext/doc/index.rst b/boards/shields/m5stack_core2_ext/doc/index.rst index 691ad98f4a2..9fdcf5bd0a0 100644 --- a/boards/shields/m5stack_core2_ext/doc/index.rst +++ b/boards/shields/m5stack_core2_ext/doc/index.rst @@ -43,7 +43,7 @@ For example: .. zephyr-app-commands:: :zephyr-app: samples/sensor/mpu6050 - :board: m5stack_core2 + :board: m5stack_core2/esp32/procpu :shield: m5stack_core2_ext :goals: build diff --git a/boards/shields/max7219/doc/index.rst b/boards/shields/max7219/doc/index.rst index 7413ec4e461..8cc10554503 100644 --- a/boards/shields/max7219/doc/index.rst +++ b/boards/shields/max7219/doc/index.rst @@ -35,6 +35,6 @@ Set ``-DSHIELD=max7219_8x8`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/display/ - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: max7219_8x8 :goals: build diff --git a/boards/shields/mcp2515/doc/index.rst b/boards/shields/mcp2515/doc/index.rst index fd35aa0b2eb..70082c0b9cc 100644 --- a/boards/shields/mcp2515/doc/index.rst +++ b/boards/shields/mcp2515/doc/index.rst @@ -346,14 +346,14 @@ example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/can/counter :tool: all - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :shield: dfrobot_can_bus_v2_0 :goals: build flash .. zephyr-app-commands:: :zephyr-app: samples/drivers/can/counter :tool: all - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: keyestudio_can_bus_ks0411 :goals: build flash diff --git a/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_cm33.conf b/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_cm33.conf rename to boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_cm33.overlay b/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_cm33.overlay rename to boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_cm33.conf b/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_cm33.conf rename to boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_cm33.overlay b/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_cm33.overlay rename to boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/boards/shields/st7735r/doc/index.rst b/boards/shields/st7735r/doc/index.rst index 015396b9690..3004fde6163 100644 --- a/boards/shields/st7735r/doc/index.rst +++ b/boards/shields/st7735r/doc/index.rst @@ -54,7 +54,7 @@ Set ``-DSHIELD=st7735r_ada_160x128`` when you invoke ``west build``. For example .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: st7735r_ada_160x128 :goals: build diff --git a/boards/shields/st7789v_generic/doc/index.rst b/boards/shields/st7789v_generic/doc/index.rst index 8f16d5bf9d5..d9282b60bf9 100644 --- a/boards/shields/st7789v_generic/doc/index.rst +++ b/boards/shields/st7789v_generic/doc/index.rst @@ -57,7 +57,7 @@ Set ``-DSHIELD=st7789v_tl019fqv01`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: st7789v_tl019fqv01 :goals: build diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_m7.conf b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf similarity index 100% rename from boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_m7.conf rename to boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_m7.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_m7.overlay rename to boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst b/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst index 815b65f5750..4e71b025ee3 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst @@ -107,7 +107,7 @@ Set ``-DSHIELD="st_b_lcd40_dsi1_mb1166"`` when you invoke ``west build``. For ex .. zephyr-app-commands:: :zephyr-app: samples/drivers/display - :board: stm32h747i_disco_m7 + :board: stm32h747i_disco/stm32h747xx/m7 :shield: st_b_lcd40_dsi1_mb1166 :goals: build diff --git a/boards/shields/waveshare_epaper/doc/index.rst b/boards/shields/waveshare_epaper/doc/index.rst index 127d8af728e..876ba1d107e 100644 --- a/boards/shields/waveshare_epaper/doc/index.rst +++ b/boards/shields/waveshare_epaper/doc/index.rst @@ -83,7 +83,7 @@ For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: waveshare_epaper_gdeh0213b1 :goals: build diff --git a/boards/sifive/hifive1/Kconfig b/boards/sifive/hifive1/Kconfig new file mode 100644 index 00000000000..304048665a7 --- /dev/null +++ b/boards/sifive/hifive1/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HIFIVE1 + select RISCV_CORE_E31 if "$(BOARD_REVISION)" = "B" diff --git a/boards/sifive/hifive1/Kconfig.defconfig b/boards/sifive/hifive1/Kconfig.defconfig new file mode 100644 index 00000000000..841e2c9ce41 --- /dev/null +++ b/boards/sifive/hifive1/Kconfig.defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 SiFive, Inc. + +if BOARD_HIFIVE1_FE310 + +config SYS_CLOCK_TICKS_PER_SEC + default 128 + +if "$(BOARD_REVISION)" = "B" + +config HAS_FLASH_LOAD_OFFSET + default y + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/spi@10014000,1) + +config FLASH_LOAD_OFFSET + default 0x0 + +endif # "$(BOARD_REVISION)" = "B" + +endif # BOARD_HIFIVE1_FE310 diff --git a/boards/sifive/hifive1/Kconfig.hifive1 b/boards/sifive/hifive1/Kconfig.hifive1 new file mode 100644 index 00000000000..29132f70288 --- /dev/null +++ b/boards/sifive/hifive1/Kconfig.hifive1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HIFIVE1 + select SOC_SIFIVE_FREEDOM_FE310 diff --git a/boards/sifive/hifive1/board.cmake b/boards/sifive/hifive1/board.cmake new file mode 100644 index 00000000000..4f39320870c --- /dev/null +++ b/boards/sifive/hifive1/board.cmake @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 SiFive, Inc. + +set(SUPPORTED_EMU_PLATFORMS renode qemu) +set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/hifive1.resc) +set(RENODE_UART sysbus.uart0) + +set(QEMU_binary_suffix riscv32) +set(QEMU_CPU_TYPE_${ARCH} riscv32) + +set(QEMU_FLAGS_${ARCH} + -nographic + -machine sifive_e + ) + +if("${BOARD_REVISION}" STREQUAL "A") + board_set_flasher_ifnset(hifive1) + board_finalize_runner_args(hifive1) + board_runner_args(openocd --cmd-load "hifive1-load") + board_runner_args(openocd --cmd-reset-halt "hifive1-reset-halt") + board_runner_args(openocd --cmd-post-verify "hifive1-post-verify") + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +elseif("${BOARD_REVISION}" STREQUAL "B") + board_runner_args(jlink "--device=FE310") + board_runner_args(jlink "--iface=JTAG") + board_runner_args(jlink "--speed=4000") + board_runner_args(jlink "--tool-opt=-jtagconf -1,-1") + board_runner_args(jlink "--tool-opt=-autoconnect 1") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/sifive/hifive1/board.yml b/boards/sifive/hifive1/board.yml new file mode 100644 index 00000000000..2909cb5aaeb --- /dev/null +++ b/boards/sifive/hifive1/board.yml @@ -0,0 +1,11 @@ +board: + name: hifive1 + vendor: sifive + socs: + - name: fe310 + revision: + format: letter + default: "A" + revisions: + - name: "A" + - name: "B" diff --git a/boards/riscv/hifive1/doc/img/hifive1.jpg b/boards/sifive/hifive1/doc/img/hifive1.jpg similarity index 100% rename from boards/riscv/hifive1/doc/img/hifive1.jpg rename to boards/sifive/hifive1/doc/img/hifive1.jpg diff --git a/boards/riscv/hifive1_revb/doc/img/hifive1_revb.jpg b/boards/sifive/hifive1/doc/img/hifive1_revb.jpg similarity index 100% rename from boards/riscv/hifive1_revb/doc/img/hifive1_revb.jpg rename to boards/sifive/hifive1/doc/img/hifive1_revb.jpg diff --git a/boards/sifive/hifive1/doc/index.rst b/boards/sifive/hifive1/doc/index.rst new file mode 100644 index 00000000000..2c3d2ba1fb6 --- /dev/null +++ b/boards/sifive/hifive1/doc/index.rst @@ -0,0 +1,97 @@ +.. _hifive1: + +SiFive HiFive1 +############## + +Overview +******** + +The HiFive1 is an Arduino-compatible development board with +an FE310 RISC-V SoC. Two revisions of this board are supported in Zephyr: +`HiFive1 `__ (also known as HiFive1 Rev A) +and `HiFive1 Rev B `__. + +.. figure:: img/hifive1.jpg + :align: center + :alt: SiFive HiFive1 board + + SiFive HiFive1 board (image courtesy of SiFive) + +.. figure:: img/hifive1_revb.jpg + :align: center + :alt: SiFive HiFive1 Rev B board + + SiFive HiFive1 Rev B board (image courtesy of SiFive) + +Programming and debugging +************************* + +Building +======== + +Applications for the HiFive1 board configuration can be built as usual (see +:ref:`build_an_application`) using the corresponding board name: + +.. tabs:: + + .. group-tab:: HiFive1 + + .. zephyr-app-commands:: + :board: hifive1 + :goals: build + + .. group-tab:: HiFive1 Rev B + + .. zephyr-app-commands:: + :board: hifive1@B + :goals: build + +Flashing +======== + + +HiFive1 +------- + +.. tabs:: + + .. group-tab:: HiFive1 + + In order to upload the application to the device, you'll need OpenOCD with + RISC-V support. Download the tarball for your OS from the `SiFive website + `_ and extract it. + + The Zephyr SDK uses a bundled version of OpenOCD by default. You can + overwrite that behavior by adding the + ``-DOPENOCD=`` parameter when building: + + .. zephyr-app-commands:: + :board: hifive1 + :goals: build + :gen-args: -DOPENOCD= + + When using a custom toolchain it should be enough to have the downloaded + version of the binary in your ``PATH``. + + .. group-tab:: HiFive1 Rev B + + The HiFive 1 Rev B uses Segger J-Link OB for flashing and debugging. To flash and + debug the board, you'll need to install the + `Segger J-Link Software and Documentation Pack + `_ + and choose version V6.46a or later (Downloads for Windows, Linux, and macOS are + available). + +Now you can flash the application as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details): + +.. code-block:: console + + west flash + +Depending on your OS you might have to run the flash command as superuser. + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/riscv/hifive1/hifive1-pinctrl.dtsi b/boards/sifive/hifive1/hifive1-pinctrl.dtsi similarity index 100% rename from boards/riscv/hifive1/hifive1-pinctrl.dtsi rename to boards/sifive/hifive1/hifive1-pinctrl.dtsi diff --git a/boards/riscv/hifive1/hifive1.dts b/boards/sifive/hifive1/hifive1.dts similarity index 100% rename from boards/riscv/hifive1/hifive1.dts rename to boards/sifive/hifive1/hifive1.dts diff --git a/boards/riscv/hifive1/hifive1.yaml b/boards/sifive/hifive1/hifive1.yaml similarity index 100% rename from boards/riscv/hifive1/hifive1.yaml rename to boards/sifive/hifive1/hifive1.yaml diff --git a/boards/sifive/hifive1/hifive1_defconfig b/boards/sifive/hifive1/hifive1_defconfig new file mode 100644 index 00000000000..21c46be1caf --- /dev/null +++ b/boards/sifive/hifive1/hifive1_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 SiFive, Inc. + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_PINCTRL=y +CONFIG_GPIO=y diff --git a/boards/sifive/hifive1/hifive1_fe310_A_defconfig b/boards/sifive/hifive1/hifive1_fe310_A_defconfig new file mode 100644 index 00000000000..7fe6d1a00e7 --- /dev/null +++ b/boards/sifive/hifive1/hifive1_fe310_A_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 SiFive, Inc. + +CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/sifive/hifive1/hifive1_fe310_B.overlay b/boards/sifive/hifive1/hifive1_fe310_B.overlay new file mode 100644 index 00000000000..e4afe2eef67 --- /dev/null +++ b/boards/sifive/hifive1/hifive1_fe310_B.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + model = "SiFive HiFive 1 Rev. B"; + compatible = "sifive,hifive1_revb"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; + +&spi2 { + status = "okay"; + pinctrl-0 = <&spi1_cs2_default + &spi1_mosi_default + &spi1_miso_default + &spi1_sck_default>; + pinctrl-names = "default"; +}; diff --git a/boards/sifive/hifive1/hifive1_fe310_B.yaml b/boards/sifive/hifive1/hifive1_fe310_B.yaml new file mode 100644 index 00000000000..8a82df4ab18 --- /dev/null +++ b/boards/sifive/hifive1/hifive1_fe310_B.yaml @@ -0,0 +1,17 @@ +identifier: hifive1@B +name: SiFive HiFive1 Rev B +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 16 +testing: + ignore_tags: + - net + - bluetooth +supported: + - arduino_gpio + - arduino_i2c + - gpio + - i2c +vendor: sifive diff --git a/boards/riscv/hifive1/support/hifive1.resc b/boards/sifive/hifive1/support/hifive1.resc similarity index 100% rename from boards/riscv/hifive1/support/hifive1.resc rename to boards/sifive/hifive1/support/hifive1.resc diff --git a/boards/riscv/hifive1/support/openocd.cfg b/boards/sifive/hifive1/support/openocd.cfg similarity index 100% rename from boards/riscv/hifive1/support/openocd.cfg rename to boards/sifive/hifive1/support/openocd.cfg diff --git a/boards/sifive/hifive_unleashed/Kconfig.defconfig b/boards/sifive/hifive_unleashed/Kconfig.defconfig new file mode 100644 index 00000000000..24541a6af9c --- /dev/null +++ b/boards/sifive/hifive_unleashed/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HIFIVE_UNLEASHED + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +endif # BOARD_HIFIVE_UNLEASHED diff --git a/boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed b/boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed new file mode 100644 index 00000000000..2fc2f15d50f --- /dev/null +++ b/boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HIFIVE_UNLEASHED + select SOC_SIFIVE_FREEDOM_FU540 diff --git a/boards/riscv/hifive_unleashed/board.cmake b/boards/sifive/hifive_unleashed/board.cmake similarity index 100% rename from boards/riscv/hifive_unleashed/board.cmake rename to boards/sifive/hifive_unleashed/board.cmake diff --git a/boards/sifive/hifive_unleashed/board.yml b/boards/sifive/hifive_unleashed/board.yml new file mode 100644 index 00000000000..f9dd3ce6e6b --- /dev/null +++ b/boards/sifive/hifive_unleashed/board.yml @@ -0,0 +1,5 @@ +board: + name: hifive_unleashed + vendor: sifive + socs: + - name: fu540 diff --git a/boards/riscv/hifive_unleashed/doc/img/hifive_unleashed.jpg b/boards/sifive/hifive_unleashed/doc/img/hifive_unleashed.jpg similarity index 100% rename from boards/riscv/hifive_unleashed/doc/img/hifive_unleashed.jpg rename to boards/sifive/hifive_unleashed/doc/img/hifive_unleashed.jpg diff --git a/boards/riscv/hifive_unleashed/doc/index.rst b/boards/sifive/hifive_unleashed/doc/index.rst similarity index 100% rename from boards/riscv/hifive_unleashed/doc/index.rst rename to boards/sifive/hifive_unleashed/doc/index.rst diff --git a/boards/riscv/hifive_unleashed/hifive_unleashed.dts b/boards/sifive/hifive_unleashed/hifive_unleashed.dts similarity index 100% rename from boards/riscv/hifive_unleashed/hifive_unleashed.dts rename to boards/sifive/hifive_unleashed/hifive_unleashed.dts diff --git a/boards/riscv/hifive_unleashed/hifive_unleashed.yaml b/boards/sifive/hifive_unleashed/hifive_unleashed.yaml similarity index 100% rename from boards/riscv/hifive_unleashed/hifive_unleashed.yaml rename to boards/sifive/hifive_unleashed/hifive_unleashed.yaml diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed_defconfig b/boards/sifive/hifive_unleashed/hifive_unleashed_defconfig new file mode 100644 index 00000000000..39b107d3455 --- /dev/null +++ b/boards/sifive/hifive_unleashed/hifive_unleashed_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n diff --git a/boards/riscv/hifive_unleashed/support/hifive_unleashed.resc b/boards/sifive/hifive_unleashed/support/hifive_unleashed.resc similarity index 100% rename from boards/riscv/hifive_unleashed/support/hifive_unleashed.resc rename to boards/sifive/hifive_unleashed/support/hifive_unleashed.resc diff --git a/boards/riscv/hifive_unleashed/support/openocd_hifive_unleashed.cfg b/boards/sifive/hifive_unleashed/support/openocd_hifive_unleashed.cfg similarity index 100% rename from boards/riscv/hifive_unleashed/support/openocd_hifive_unleashed.cfg rename to boards/sifive/hifive_unleashed/support/openocd_hifive_unleashed.cfg diff --git a/boards/sifive/hifive_unmatched/Kconfig.defconfig b/boards/sifive/hifive_unmatched/Kconfig.defconfig new file mode 100644 index 00000000000..3ced33713cb --- /dev/null +++ b/boards/sifive/hifive_unmatched/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HIFIVE_UNMATCHED + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +endif # BOARD_HIFIVE_UNMATCHED diff --git a/boards/sifive/hifive_unmatched/Kconfig.hifive_unmatched b/boards/sifive/hifive_unmatched/Kconfig.hifive_unmatched new file mode 100644 index 00000000000..87911f3ccb3 --- /dev/null +++ b/boards/sifive/hifive_unmatched/Kconfig.hifive_unmatched @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HIFIVE_UNMATCHED + select SOC_SIFIVE_FREEDOM_FU740 diff --git a/boards/riscv/hifive_unmatched/board.cmake b/boards/sifive/hifive_unmatched/board.cmake similarity index 100% rename from boards/riscv/hifive_unmatched/board.cmake rename to boards/sifive/hifive_unmatched/board.cmake diff --git a/boards/sifive/hifive_unmatched/board.yml b/boards/sifive/hifive_unmatched/board.yml new file mode 100644 index 00000000000..703d94e852b --- /dev/null +++ b/boards/sifive/hifive_unmatched/board.yml @@ -0,0 +1,5 @@ +board: + name: hifive_unmatched + vendor: sifive + socs: + - name: fu740 diff --git a/boards/riscv/hifive_unmatched/doc/img/hifive_unmatched.jpg b/boards/sifive/hifive_unmatched/doc/img/hifive_unmatched.jpg similarity index 100% rename from boards/riscv/hifive_unmatched/doc/img/hifive_unmatched.jpg rename to boards/sifive/hifive_unmatched/doc/img/hifive_unmatched.jpg diff --git a/boards/riscv/hifive_unmatched/doc/index.rst b/boards/sifive/hifive_unmatched/doc/index.rst similarity index 100% rename from boards/riscv/hifive_unmatched/doc/index.rst rename to boards/sifive/hifive_unmatched/doc/index.rst diff --git a/boards/riscv/hifive_unmatched/hifive_unmatched.dts b/boards/sifive/hifive_unmatched/hifive_unmatched.dts similarity index 100% rename from boards/riscv/hifive_unmatched/hifive_unmatched.dts rename to boards/sifive/hifive_unmatched/hifive_unmatched.dts diff --git a/boards/riscv/hifive_unmatched/hifive_unmatched.yaml b/boards/sifive/hifive_unmatched/hifive_unmatched.yaml similarity index 100% rename from boards/riscv/hifive_unmatched/hifive_unmatched.yaml rename to boards/sifive/hifive_unmatched/hifive_unmatched.yaml diff --git a/boards/sifive/hifive_unmatched/hifive_unmatched_defconfig b/boards/sifive/hifive_unmatched/hifive_unmatched_defconfig new file mode 100644 index 00000000000..02295cf19df --- /dev/null +++ b/boards/sifive/hifive_unmatched/hifive_unmatched_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n diff --git a/boards/riscv/hifive_unmatched/support/hifive_unmatched.resc b/boards/sifive/hifive_unmatched/support/hifive_unmatched.resc similarity index 100% rename from boards/riscv/hifive_unmatched/support/hifive_unmatched.resc rename to boards/sifive/hifive_unmatched/support/hifive_unmatched.resc diff --git a/boards/riscv/hifive_unmatched/support/openocd_hifive_unmatched.cfg b/boards/sifive/hifive_unmatched/support/openocd_hifive_unmatched.cfg similarity index 100% rename from boards/riscv/hifive_unmatched/support/openocd_hifive_unmatched.cfg rename to boards/sifive/hifive_unmatched/support/openocd_hifive_unmatched.cfg diff --git a/boards/sifive/index.rst b/boards/sifive/index.rst new file mode 100644 index 00000000000..2249014c08e --- /dev/null +++ b/boards/sifive/index.rst @@ -0,0 +1,10 @@ +.. _boards-sifive: + +SiFive +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/silabs/efm32gg_sltb009a/Kconfig.defconfig b/boards/silabs/efm32gg_sltb009a/Kconfig.defconfig new file mode 100644 index 00000000000..a24eda68abd --- /dev/null +++ b/boards/silabs/efm32gg_sltb009a/Kconfig.defconfig @@ -0,0 +1,20 @@ +# EFM32GG SLTB009A default board configuration +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32GG_SLTB009A + +config CMU_HFXO_FREQ + default 50000000 + +config CMU_HFRCO_FREQ + default 72000000 + +config CMU_LFXO_FREQ + default 32768 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +endif # BOARD_EFM32GG_SLTB009A diff --git a/boards/silabs/efm32gg_sltb009a/Kconfig.efm32gg_sltb009a b/boards/silabs/efm32gg_sltb009a/Kconfig.efm32gg_sltb009a new file mode 100644 index 00000000000..e1f93ff9da9 --- /dev/null +++ b/boards/silabs/efm32gg_sltb009a/Kconfig.efm32gg_sltb009a @@ -0,0 +1,6 @@ +# EFM32GG SLTB009A board configuration +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32GG_SLTB009A + select SOC_PART_NUMBER_EFM32GG12B810F1024GM64 diff --git a/boards/arm/efm32gg_sltb009a/board.cmake b/boards/silabs/efm32gg_sltb009a/board.cmake similarity index 100% rename from boards/arm/efm32gg_sltb009a/board.cmake rename to boards/silabs/efm32gg_sltb009a/board.cmake diff --git a/boards/silabs/efm32gg_sltb009a/board.yml b/boards/silabs/efm32gg_sltb009a/board.yml new file mode 100644 index 00000000000..388301f55e1 --- /dev/null +++ b/boards/silabs/efm32gg_sltb009a/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32gg_sltb009a + vendor: silabs + socs: + - name: efm32gg12b810f1024gm64 diff --git a/boards/arm/efm32gg_sltb009a/doc/efm32gg12-thunderboard-kit.jpg b/boards/silabs/efm32gg_sltb009a/doc/efm32gg12-thunderboard-kit.jpg similarity index 100% rename from boards/arm/efm32gg_sltb009a/doc/efm32gg12-thunderboard-kit.jpg rename to boards/silabs/efm32gg_sltb009a/doc/efm32gg12-thunderboard-kit.jpg diff --git a/boards/silabs/efm32gg_sltb009a/doc/index.rst b/boards/silabs/efm32gg_sltb009a/doc/index.rst new file mode 100644 index 00000000000..e27fcc34ba0 --- /dev/null +++ b/boards/silabs/efm32gg_sltb009a/doc/index.rst @@ -0,0 +1,165 @@ +.. _efm32gg_sltb009a: + +EFM32GG12 Thunderboard Kit +########################## + +Overview +******** + +The EFM32GG12 Thunderboard Kit (SLTB009A) is an evaluation platform for the EFM32GG12 GiantGecko Microcontroller, +featuring an ARM Cortex-M4 with FPU, 1024kB flash, and 192kB RAM. + +.. figure:: efm32gg12-thunderboard-kit.jpg + :align: center + :alt: SLTB009A + + SLTB009A (Credit: Silicon Labs) + +Hardware +******** + +- PDM stereo microphones +- USB connectivity +- On-board Segger J-Link USB debugger +- 2 user buttons and 2 LEDs +- USB C connector + +For more information about the WGM160P and SLTB009A board: + +- `SLTB009A Website`_ +- `SLTB009A User Guide`_ +- `EFM32GG12 Datasheet`_ +- `EFM32GG12 Reference Manual`_ + +Supported Features +================== + +The efm32gg_sltb009a board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a_defconfig` + +Connections and IOs +=================== + +The EFM32GG12 MCU has six GPIO controllers (PORTA to PORTF), all of which are +currently enabled for the SLTB009A board. + +In the following table, the column **Name** contains pin names. For example, PE1 +means pin number 1 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PE12 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PA13 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PD5 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PD8 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | ++-------+-------------+-------------------------------------+ +| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | ++-------+-------------+-------------------------------------+ +| PC0 | I2C_SDA | SENSOR_I2C_SDA I2C0_SDA #1 | ++-------+-------------+-------------------------------------+ +| PC1 | I2C_SCL | SENSOR_I2C_SCL I2C0_SCL #1 | ++-------+-------------+-------------------------------------+ +| PC4 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | ++-------+-------------+-------------------------------------+ +| PC5 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32GG12 MCU is configured to work at 72 MHz. + +Serial Port +=========== + +The EFM32GG12 SoC has five USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The SLTB009A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to SLTB009A +-------------------------------------- + +Connect the SLTB009A to your host computer using the USB port. + +Here is an example to build and flash the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32gg_stb009a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! efm32gg_sltb009a + +.. _SLTB009A Website: + https://www.silabs.com/development-tools/thunderboard/thunderboard-gg12-kit + +.. _SLTB009A User Guide: + https://www.silabs.com/documents/public/user-guides/ug371-sltb009a-user-guide.pdf + +.. _EFM32GG12 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32gg12-datasheet.pdf + +.. _EFM32GG12 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32gg12-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32gg_sltb009a/efm32gg_sltb009a-pinctrl.dtsi b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a-pinctrl.dtsi similarity index 100% rename from boards/arm/efm32gg_sltb009a/efm32gg_sltb009a-pinctrl.dtsi rename to boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a-pinctrl.dtsi diff --git a/boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.dts b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.dts similarity index 100% rename from boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.dts rename to boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.dts diff --git a/boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.yaml b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.yaml similarity index 100% rename from boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.yaml rename to boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.yaml diff --git a/boards/arm/efm32gg_sltb009a/efm32gg_sltb009a_defconfig b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a_defconfig similarity index 79% rename from boards/arm/efm32gg_sltb009a/efm32gg_sltb009a_defconfig rename to boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a_defconfig index 31f29cf85e5..2cfd7572706 100644 --- a/boards/arm/efm32gg_sltb009a/efm32gg_sltb009a_defconfig +++ b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2023 Antmicro # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32GG12B=y -CONFIG_BOARD_EFM32GG_SLTB009A=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/efm32gg_slwstk6121a/CMakeLists.txt b/boards/silabs/efm32gg_slwstk6121a/CMakeLists.txt similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/CMakeLists.txt rename to boards/silabs/efm32gg_slwstk6121a/CMakeLists.txt diff --git a/boards/silabs/efm32gg_slwstk6121a/Kconfig.defconfig b/boards/silabs/efm32gg_slwstk6121a/Kconfig.defconfig new file mode 100644 index 00000000000..33e5b1192c0 --- /dev/null +++ b/boards/silabs/efm32gg_slwstk6121a/Kconfig.defconfig @@ -0,0 +1,29 @@ +# EFM32GG SLWSTK6121A default board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# Copyright (c) 2020 Thorvald Natvig +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32GG_SLWSTK6121A + +config CMU_HFXO_FREQ + default 50000000 + +config CMU_HFRCO_FREQ + default 72000000 + +config CMU_LFXO_FREQ + default 32768 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_EFM32GG_SLWSTK6121A diff --git a/boards/silabs/efm32gg_slwstk6121a/Kconfig.efm32gg_slwstk6121a b/boards/silabs/efm32gg_slwstk6121a/Kconfig.efm32gg_slwstk6121a new file mode 100644 index 00000000000..2e064a306f1 --- /dev/null +++ b/boards/silabs/efm32gg_slwstk6121a/Kconfig.efm32gg_slwstk6121a @@ -0,0 +1,8 @@ +# EFM32GG SLWSTK6121A board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# Copyright (c) 2020 Thorvald Natvig +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32GG_SLWSTK6121A + select SOC_PART_NUMBER_EFM32GG11B820F2048GM64 diff --git a/boards/arm/efm32gg_slwstk6121a/board.c b/boards/silabs/efm32gg_slwstk6121a/board.c similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/board.c rename to boards/silabs/efm32gg_slwstk6121a/board.c diff --git a/boards/arm/efm32gg_slwstk6121a/board.cmake b/boards/silabs/efm32gg_slwstk6121a/board.cmake similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/board.cmake rename to boards/silabs/efm32gg_slwstk6121a/board.cmake diff --git a/boards/arm/efm32gg_slwstk6121a/board.h b/boards/silabs/efm32gg_slwstk6121a/board.h similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/board.h rename to boards/silabs/efm32gg_slwstk6121a/board.h diff --git a/boards/silabs/efm32gg_slwstk6121a/board.yml b/boards/silabs/efm32gg_slwstk6121a/board.yml new file mode 100644 index 00000000000..7f91de02759 --- /dev/null +++ b/boards/silabs/efm32gg_slwstk6121a/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32gg_slwstk6121a + vendor: silabs + socs: + - name: efm32gg11b820f2048gm64 diff --git a/boards/silabs/efm32gg_slwstk6121a/doc/index.rst b/boards/silabs/efm32gg_slwstk6121a/doc/index.rst new file mode 100644 index 00000000000..47d2a5a93a1 --- /dev/null +++ b/boards/silabs/efm32gg_slwstk6121a/doc/index.rst @@ -0,0 +1,186 @@ +.. _efm32gg_slwstk6121a: + +WGM160P Starter Kit +################### + +Overview +******** + +The WGM160P Starter Kit SLWSTK6121A comes with the BRD4321A radio board. +This radio boards contains a WGM160P module, which combines the WF200 Wi-Fi +transceiver with an EFM32GG11 microcontroller. + +.. figure:: wgm160p-starter-kit.jpg + :align: center + :alt: SLWSTK6121A + + SLWSTK6121A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel color Memory-LCD +- 2 user buttons and 2 LEDs +- Si7021 Humidity and Temperature Sensor +- On-board Segger J-Link USB and Ethernet debugger +- 10/100Base-TX ethernet PHY and RJ-45 jack (on included expansion board) +- MicroSD card slot +- USB Micro-AB connector + +For more information about the WGM160P and SLWSTK6121A board: + +- `WGM160P Website`_ +- `WGM160P Datasheet`_ +- `SLWSTK6121A Website`_ +- `SLWSTK6121A User Guide`_ +- `EFM32GG11 Datasheet`_ +- `EFM32GG11 Reference Manual`_ +- `WF200 Datasheet`_ + +Supported Features +================== + +The efm32gg_slwstk6121a board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig` + +Other hardware features, including the WF200 WiFi transceiver, are +currently not supported by the port. + +Connections and IOs +=================== + +The WGM160P's EFM32GG11 SoC has six GPIO controllers (PORTA to PORTF), all of which are +currently enabled for the SLWSTK6121A board. + +In the following table, the column **Name** contains pin names. For example, PE1 +means pin number 1 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PA4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PD6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PD8 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | ++-------+-------------+-------------------------------------+ +| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | ++-------+-------------+-------------------------------------+ +| PB11 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | ++-------+-------------+-------------------------------------+ +| PB12 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32GG11 SoC has four USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The SLWSTK6121A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to SLWSTK6121A +-------------------------------------- + +Connect the SLWSTK6121A to your host computer using the USB port. + +Here is an example to build and flash the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32gg_slwstk6121a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! efm32gg_slwstk6121a + +.. _WGM160P Website: + https://www.silabs.com/wireless/wi-fi/wfm160-series-1-modules + +.. _WGM160P Datasheet: + https://www.silabs.com/documents/public/data-sheets/wgm160p-datasheet.pdf + +.. _SLWSTK6121A Website: + https://www.silabs.com/development-tools/wireless/wi-fi/wgm160p-wifi-module-starter-kit + +.. _SLWSTK6121A User Guide: + https://www.silabs.com/documents/public/user-guides/ug351-brd4321a-user-guide.pdf + +.. _EFM32GG11 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf + +.. _EFM32GG11 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf + +.. _WF200 Datasheet: + https://www.silabs.com/documents/public/data-sheets/wf200-datasheet.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32gg_slwstk6121a/doc/wgm160p-starter-kit.jpg b/boards/silabs/efm32gg_slwstk6121a/doc/wgm160p-starter-kit.jpg similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/doc/wgm160p-starter-kit.jpg rename to boards/silabs/efm32gg_slwstk6121a/doc/wgm160p-starter-kit.jpg diff --git a/boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a-pinctrl.dtsi b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a-pinctrl.dtsi similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a-pinctrl.dtsi rename to boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a-pinctrl.dtsi diff --git a/boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a.dts b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.dts similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a.dts rename to boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.dts diff --git a/boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a.yaml b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.yaml similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a.yaml rename to boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.yaml diff --git a/boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig similarity index 84% rename from boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig rename to boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig index 4eadfce741a..f7dfcb09cba 100644 --- a/boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig +++ b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig @@ -3,8 +3,6 @@ # Copyright (c) 2020 Thorvald Natvig # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32GG11B=y -CONFIG_BOARD_EFM32GG_SLWSTK6121A=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/efm32gg_slwstk6121a/support/openocd.cfg b/boards/silabs/efm32gg_slwstk6121a/support/openocd.cfg similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/support/openocd.cfg rename to boards/silabs/efm32gg_slwstk6121a/support/openocd.cfg diff --git a/boards/arm/efm32gg_stk3701a/CMakeLists.txt b/boards/silabs/efm32gg_stk3701a/CMakeLists.txt similarity index 100% rename from boards/arm/efm32gg_stk3701a/CMakeLists.txt rename to boards/silabs/efm32gg_stk3701a/CMakeLists.txt diff --git a/boards/silabs/efm32gg_stk3701a/Kconfig.defconfig b/boards/silabs/efm32gg_stk3701a/Kconfig.defconfig new file mode 100644 index 00000000000..c56b944202f --- /dev/null +++ b/boards/silabs/efm32gg_stk3701a/Kconfig.defconfig @@ -0,0 +1,28 @@ +# EFM32GG STK3701A default board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32GG_STK3701A + +config CMU_HFXO_FREQ + default 50000000 + +config CMU_HFRCO_FREQ + default 72000000 + +config CMU_LFXO_FREQ + default 32768 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_EFM32GG_STK3701A diff --git a/boards/silabs/efm32gg_stk3701a/Kconfig.efm32gg_stk3701a b/boards/silabs/efm32gg_stk3701a/Kconfig.efm32gg_stk3701a new file mode 100644 index 00000000000..058ea533a21 --- /dev/null +++ b/boards/silabs/efm32gg_stk3701a/Kconfig.efm32gg_stk3701a @@ -0,0 +1,7 @@ +# EFM32GG STK3701A board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32GG_STK3701A + select SOC_PART_NUMBER_EFM32GG11B820F2048GL192 diff --git a/boards/arm/efm32gg_stk3701a/board.c b/boards/silabs/efm32gg_stk3701a/board.c similarity index 100% rename from boards/arm/efm32gg_stk3701a/board.c rename to boards/silabs/efm32gg_stk3701a/board.c diff --git a/boards/arm/efm32gg_stk3701a/board.cmake b/boards/silabs/efm32gg_stk3701a/board.cmake similarity index 100% rename from boards/arm/efm32gg_stk3701a/board.cmake rename to boards/silabs/efm32gg_stk3701a/board.cmake diff --git a/boards/arm/efm32gg_stk3701a/board.h b/boards/silabs/efm32gg_stk3701a/board.h similarity index 100% rename from boards/arm/efm32gg_stk3701a/board.h rename to boards/silabs/efm32gg_stk3701a/board.h diff --git a/boards/silabs/efm32gg_stk3701a/board.yml b/boards/silabs/efm32gg_stk3701a/board.yml new file mode 100644 index 00000000000..d69afebb60b --- /dev/null +++ b/boards/silabs/efm32gg_stk3701a/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32gg_stk3701a + vendor: silabs + socs: + - name: efm32gg11b820f2048gl192 diff --git a/boards/arm/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg b/boards/silabs/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg similarity index 100% rename from boards/arm/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg rename to boards/silabs/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg diff --git a/boards/silabs/efm32gg_stk3701a/doc/index.rst b/boards/silabs/efm32gg_stk3701a/doc/index.rst new file mode 100644 index 00000000000..ddb5a1f38d7 --- /dev/null +++ b/boards/silabs/efm32gg_stk3701a/doc/index.rst @@ -0,0 +1,200 @@ +.. _efm32gg_stk3701a: + +EFM32 Giant Gecko GG11 Starter Kit +################################## + +Overview +******** + +The EFM32 Giant Gecko Starter Kit EFM32GG-STK3701A contains an MCU from the +EFM32GG Series 1 family built on an ARM® Cortex®-M4F processor with excellent +low power capabilities. + +.. figure:: efm32gg_stk3701a.jpg + :align: center + :alt: EFM32GG-SLSTK3701A + + EFM32GG-SLSTK3701A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel color Memory-LCD +- 2 user buttons, 2 LEDs and a touch slider +- Relative humidity, magnetic Hall Effect and inductive-capacitive metal sensor +- USB interface for Host/Device/OTG +- 32 Mb Quad-SPI Flash memory +- SD card slot +- RJ-45 Ethernet jack +- 2 digital microphones +- On-board Segger J-Link USB debugger + +For more information about the EFM32GG11 SoC and EFM32GG-STK3701A board: + +- `EFM32GG Series 1 Website`_ +- `EFM32GG11 Datasheet`_ +- `EFM32GG11 Reference Manual`_ +- `EFM32GG-STK3701A Website`_ +- `EFM32GG-STK3701A User Guide`_ +- `EFM32GG-STK3701A Schematics`_ + +Supported Features +================== + +The efm32gg_stk3701a board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32GG11 SoC has nine GPIO controllers (PORTA to PORTI), all of which are +currently enabled for the EFM32GG-STK3701A board. + +In the following table, the column **Name** contains pin names. For example, PE1 +means pin number 1 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PH10 | GPIO | LED0 red | ++-------+-------------+-------------------------------------+ +| PH11 | GPIO | LED0 green | ++-------+-------------+-------------------------------------+ +| PH12 | GPIO | LED0 blue | ++-------+-------------+-------------------------------------+ +| PH13 | GPIO | LED1 red | ++-------+-------------+-------------------------------------+ +| PH14 | GPIO | LED1 green | ++-------+-------------+-------------------------------------+ +| PH15 | GPIO | LED1 blue | ++-------+-------------+-------------------------------------+ +| PC8 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PC9 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PE1 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PH4 | UART_TX | UART TX Console VCOM_TX US0_TX #4 | ++-------+-------------+-------------------------------------+ +| PH5 | UART_RX | UART RX Console VCOM_RX US0_RX #4 | ++-------+-------------+-------------------------------------+ +| PI4 | I2C_SDA | SENSOR_I2C_SDA I2C2_SDA #7 | ++-------+-------------+-------------------------------------+ +| PI5 | I2C_SCL | SENSOR_I2C_SCL I2C2_SCL #7 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32GG11 SoC has six USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART4 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32GG-STK3701A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a mass storage device and a + USB serial port. +- A serial flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to EFM32GG-STK3701A +------------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32gg_stk3701a + :goals: build + +Connect the EFM32GG-STK3701A to your host computer using the USB port and you +should see a USB connection which exposes a mass storage device(STK3701A) and +a USB Serial Port. Copy the generated zephyr.bin to the STK3701A drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! efm32gg_stk3701a + + +.. _EFM32GG-STK3701A Website: + https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-giant-gecko-gg11-starter-kit + +.. _EFM32GG-STK3701A User Guide: + https://www.silabs.com/documents/public/user-guides/ug287-stk3701.pdf + +.. _EFM32GG-STK3701A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD2204A-B00-schematic.pdf + +.. _EFM32GG Series 1 Website: + https://www.silabs.com/products/mcu/32-bit/efm32-giant-gecko-s1 + +.. _EFM32GG11 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf + +.. _EFM32GG11 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a-pinctrl.dtsi b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a-pinctrl.dtsi similarity index 100% rename from boards/arm/efm32gg_stk3701a/efm32gg_stk3701a-pinctrl.dtsi rename to boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a-pinctrl.dtsi diff --git a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.dts b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.dts similarity index 100% rename from boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.dts rename to boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.dts diff --git a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.yaml b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.yaml similarity index 100% rename from boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.yaml rename to boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.yaml diff --git a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a_defconfig similarity index 81% rename from boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig rename to boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a_defconfig index 61c099b5726..76b773c1f7c 100644 --- a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig +++ b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a_defconfig @@ -2,8 +2,6 @@ # Copyright (c) 2019 Oane Kingma # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32GG11B=y -CONFIG_BOARD_EFM32GG_STK3701A=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/efm32gg_stk3701a/support/openocd.cfg b/boards/silabs/efm32gg_stk3701a/support/openocd.cfg similarity index 100% rename from boards/arm/efm32gg_stk3701a/support/openocd.cfg rename to boards/silabs/efm32gg_stk3701a/support/openocd.cfg diff --git a/boards/silabs/efm32hg_slstk3400a/Kconfig.defconfig b/boards/silabs/efm32hg_slstk3400a/Kconfig.defconfig new file mode 100644 index 00000000000..c15834e7229 --- /dev/null +++ b/boards/silabs/efm32hg_slstk3400a/Kconfig.defconfig @@ -0,0 +1,14 @@ +# EFM32HG SLSTK3400A board + +# Copyright (c) 2018, Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32HG_SLSTK3400A + +config CMU_HFXO_FREQ + default 24000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_EFM32HG_SLSTK3400A diff --git a/boards/silabs/efm32hg_slstk3400a/Kconfig.efm32hg_slstk3400a b/boards/silabs/efm32hg_slstk3400a/Kconfig.efm32hg_slstk3400a new file mode 100644 index 00000000000..3ab1289920f --- /dev/null +++ b/boards/silabs/efm32hg_slstk3400a/Kconfig.efm32hg_slstk3400a @@ -0,0 +1,7 @@ +# EFM32HG SLSTK3400A board + +# Copyright (c) 2018, Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32HG_SLSTK3400A + select SOC_PART_NUMBER_EFM32HG322F64 diff --git a/boards/silabs/efm32hg_slstk3400a/board.yml b/boards/silabs/efm32hg_slstk3400a/board.yml new file mode 100644 index 00000000000..8aae393fcae --- /dev/null +++ b/boards/silabs/efm32hg_slstk3400a/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32hg_slstk3400a + vendor: silabs + socs: + - name: efm32hg322f64 diff --git a/boards/arm/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.jpg b/boards/silabs/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.jpg similarity index 100% rename from boards/arm/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.jpg rename to boards/silabs/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.jpg diff --git a/boards/silabs/efm32hg_slstk3400a/doc/index.rst b/boards/silabs/efm32hg_slstk3400a/doc/index.rst new file mode 100644 index 00000000000..a1e0b84f16d --- /dev/null +++ b/boards/silabs/efm32hg_slstk3400a/doc/index.rst @@ -0,0 +1,176 @@ +.. _efm32hg_slstk3400a: + +EFM32HG-SLSTK3400A +################## + +Overview +******** + +The EFM32 Happy Gecko Starter Kit EFM32HG-SLSTK3400A contains a MCU from the +EFM32HG family built on ARM® Cortex®-M0+ processor with excellent low +power capabilities. + +.. figure:: efm32hg_slstk3400a.jpg + :align: center + :alt: EFM32HG-SLSTK3400A + + EFM32HG-SLSTK3400A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring system for precise current tracking +- Real-time energy and power profiling +- ARM Cortex M0+ with 64 kB Flash and 8 kB RAM +- 128 X 128 pixel Memory LCD +- 2 user buttons, 2 user LEDs and 2 touch buttons +- 20 pin expansion header +- Silicon Labs Si7021 Relative Humidity/Temperature sensor +- USB device interface +- Integrated SEGGER J-Link USB debugger/emulator with debug out functionality + + +See these documents for more information + +- `EFM32HG Website`_ +- `EFM32HG Datasheet`_ +- `EFM32HG Reference Manual`_ +- `EFM32HG-SLSTK3400A Website`_ +- `EFM32HG-SLSTK3400A User Guide`_ +- `EFM32HG-SLSTK3400A Schematics`_ + +Supported Features +================== + +The efm32hg_slstk3400 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32HG SoC has six GPIO controllers (PORTA to PORTF), but only three are +currently enabled (PORTB, PORTE and PORTF) for the EFM32HG-SLSTK3400A board. + +In the following table, the column Name contains Pin names. For example, PF4 +means Pin number 4 on PORTF, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PC9 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PC10 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PF2 | USART0_TX | USART Console EFM_BC_TX U0_TX #4 | ++-------+-------------+-------------------------------------+ +| PA9 | USART0_RX | USART Console EFM_BC_RX U0_RX #4 | ++-------+-------------+-------------------------------------+ + +System Clock +============ + +The EFM32HG SoC is configured to use the 24 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32HG SoC has two USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART1 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32HG-SLSTK3400 includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a Mass Storage and a + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +Flashing an application to EFM32-SLSTK3400A +------------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32hg_slstk3400a + :goals: build + +Connect the EFM32HG-SLSTK3400A to your host computer using the USB port and +you should see a USB connection that exposes a mass storage device (STK3400) +and a USB Serial Port. Copy the generated ``zephyr.bin`` in the STK3400 drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you will see this message written to the serial port: + +.. code-block:: console + + Hello World! arm + + +.. _EFM32HG-SLSTK3400A Website: + https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-happy-gecko-starter-kit + +.. _EFM32HG-SLSTK3400A User Guide: + https://www.silabs.com/documents/public/user-guides/ug255-stk3400-user-guide.pdf + +.. _EFM32HG-SLSTK3400A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD2012A-B01-schematic.pdf + +.. _EFM32HG Website: + https://www.silabs.com/products/mcu/32-bit/efm32-happy-gecko + +.. _EFM32HG Datasheet: + https://www.silabs.com/documents/public/data-sheets/EFM32HG322.pdf + +.. _EFM32HG Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/EFM32HG-RM.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a.dts b/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.dts similarity index 100% rename from boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a.dts rename to boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.dts diff --git a/boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a.yaml b/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.yaml similarity index 100% rename from boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a.yaml rename to boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.yaml diff --git a/boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig b/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig similarity index 82% rename from boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig rename to boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig index 834cb328d0c..957fedcc584 100644 --- a/boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig +++ b/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32HG=y -CONFIG_BOARD_EFM32HG_SLSTK3400A=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/silabs/efm32pg_stk3401a/Kconfig.defconfig b/boards/silabs/efm32pg_stk3401a/Kconfig.defconfig new file mode 100644 index 00000000000..9853bf434cc --- /dev/null +++ b/boards/silabs/efm32pg_stk3401a/Kconfig.defconfig @@ -0,0 +1,14 @@ +# EFM32PG STK3401A board + +# Copyright (c) 2020, Rafael Dias Menezes +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32PG_STK3401A + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_EFM32PG_STK3401A diff --git a/boards/silabs/efm32pg_stk3401a/Kconfig.efm32pg_stk3401a b/boards/silabs/efm32pg_stk3401a/Kconfig.efm32pg_stk3401a new file mode 100644 index 00000000000..42de02a430a --- /dev/null +++ b/boards/silabs/efm32pg_stk3401a/Kconfig.efm32pg_stk3401a @@ -0,0 +1,7 @@ +# EFM32PG STK3401A board + +# Copyright (c) 2020, Rafael Dias Menezes +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32PG_STK3401A + select SOC_PART_NUMBER_EFM32PG1B200F256GM48 diff --git a/boards/arm/efm32pg_stk3401a/board.cmake b/boards/silabs/efm32pg_stk3401a/board.cmake similarity index 100% rename from boards/arm/efm32pg_stk3401a/board.cmake rename to boards/silabs/efm32pg_stk3401a/board.cmake diff --git a/boards/silabs/efm32pg_stk3401a/board.yml b/boards/silabs/efm32pg_stk3401a/board.yml new file mode 100644 index 00000000000..636c7e8c562 --- /dev/null +++ b/boards/silabs/efm32pg_stk3401a/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32pg_stk3401a + vendor: silabs + socs: + - name: efm32pg1b200f256gm48 diff --git a/boards/arm/efm32pg_stk3401a/doc/efm32pg_stk3401a.jpg b/boards/silabs/efm32pg_stk3401a/doc/efm32pg_stk3401a.jpg similarity index 100% rename from boards/arm/efm32pg_stk3401a/doc/efm32pg_stk3401a.jpg rename to boards/silabs/efm32pg_stk3401a/doc/efm32pg_stk3401a.jpg diff --git a/boards/silabs/efm32pg_stk3401a/doc/index.rst b/boards/silabs/efm32pg_stk3401a/doc/index.rst new file mode 100644 index 00000000000..a38930275a2 --- /dev/null +++ b/boards/silabs/efm32pg_stk3401a/doc/index.rst @@ -0,0 +1,188 @@ +.. _efm32pg_stk3401a: + +EFM32 Pearl Gecko Starter Kit +############################# + +Overview +******** + +The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3401A contains an MCU from the +EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low +power capabilities. + +.. figure:: efm32pg_stk3401a.jpg + :align: center + :alt: EFM32PG-SLSTK3401A + + EFM32PG-SLSTK3401A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel Memory-LCD +- 2 user buttons, 2 LEDs and 2 capacitive buttons +- Humidity and temperature sensor +- On-board Segger J-Link USB debugger + +For more information about the EFM32PG SoC and EFM32PG-STK3401A board: + +- `EFM32PG Website`_ +- `EFM32PG1 Datasheet`_ +- `EFM32PG1 Reference Manual`_ +- `EFM32PG-STK3401A Website`_ +- `EFM32PG-STK3401A User Guide`_ + +Supported Features +================== + +The efm32pg_stk3401a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32PG1 SoC has five GPIO controllers (PORTA to PORTD and PORTF) and +all are enabled for the EFM32PG-STK3401A board. + +In the following table, the column **Name** contains pin names. For example, PF4 +means pin number 4 on PORTF, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PF6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | ++-------+-------------+-------------------------------------+ +| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | ++-------+-------------+-------------------------------------+ +| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | ++-------+-------------+-------------------------------------+ +| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | ++-------+-------------+-------------------------------------+ +| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | ++-------+-------------+-------------------------------------+ +| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32PG SoC is configured to use the 40 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32PG SoC has two USARTs and one Low Energy UART (LEUART). + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32PG-STK3401A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a mass storage device and a + USB serial port. +- A serial flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to EFM32PG-STK3401A +------------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32pg_stk3401a + :goals: build + +Connect the EFM32PG-STK3401A to your host computer using the USB port and you +should see a USB connection which exposes a mass storage device(STK3401A). +Copy the generated zephyr.bin to the STK3401A drive. + +Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the +expansion header. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! arm + + +.. _EFM32PG-STK3401A Website: + https://www.silabs.com/development-tools/mcu/32-bit/efm32pg1-starter-kit + +.. _EFM32PG-STK3401A User Guide: + https://www.silabs.com/documents/public/user-guides/ug154-stk3401-user-guide.pdf + +.. _EFM32PG Website: + https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko + +.. _EFM32PG1 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32pg1-datasheet.pdf + +.. _EFM32PG1 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32pg1-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a-pinctrl.dtsi b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a-pinctrl.dtsi similarity index 100% rename from boards/arm/efm32pg_stk3401a/efm32pg_stk3401a-pinctrl.dtsi rename to boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a-pinctrl.dtsi diff --git a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a.dts b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.dts similarity index 100% rename from boards/arm/efm32pg_stk3401a/efm32pg_stk3401a.dts rename to boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.dts diff --git a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a.yaml b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.yaml similarity index 100% rename from boards/arm/efm32pg_stk3401a/efm32pg_stk3401a.yaml rename to boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.yaml diff --git a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_common.dtsi b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_common.dtsi similarity index 100% rename from boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_common.dtsi rename to boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_common.dtsi diff --git a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_defconfig b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_defconfig similarity index 75% rename from boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_defconfig rename to boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_defconfig index 541e45f901f..f220c60c9a8 100644 --- a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_defconfig +++ b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32PG1B=y -CONFIG_BOARD_EFM32PG_STK3401A=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/silabs/efm32pg_stk3402a/Kconfig.defconfig b/boards/silabs/efm32pg_stk3402a/Kconfig.defconfig new file mode 100644 index 00000000000..3d9a498ecd5 --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/Kconfig.defconfig @@ -0,0 +1,15 @@ +# EFM32PG STK3402A board + +# Copyright (c) 2018, Christian Taedcke +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32PG_STK3402A + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_EFM32PG_STK3402A diff --git a/boards/silabs/efm32pg_stk3402a/Kconfig.efm32pg_stk3402a b/boards/silabs/efm32pg_stk3402a/Kconfig.efm32pg_stk3402a new file mode 100644 index 00000000000..7f4bea41475 --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/Kconfig.efm32pg_stk3402a @@ -0,0 +1,9 @@ +# EFM32PG STK3402A board + +# Copyright (c) 2018, Christian Taedcke +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32PG_STK3402A + select SOC_PART_NUMBER_EFM32PG12B500F1024GL125 if BOARD_EFM32PG_STK3402A_EFM32PG12B500F1024GL125 + select SOC_PART_NUMBER_EFM32JG12B500F1024GL125 if BOARD_EFM32PG_STK3402A_EFM32JG12B500F1024GL125 diff --git a/boards/arm/efm32pg_stk3402a/board.cmake b/boards/silabs/efm32pg_stk3402a/board.cmake similarity index 100% rename from boards/arm/efm32pg_stk3402a/board.cmake rename to boards/silabs/efm32pg_stk3402a/board.cmake diff --git a/boards/silabs/efm32pg_stk3402a/board.yml b/boards/silabs/efm32pg_stk3402a/board.yml new file mode 100644 index 00000000000..068aa663798 --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/board.yml @@ -0,0 +1,6 @@ +board: + name: efm32pg_stk3402a + vendor: silabs + socs: + - name: efm32pg12b500f1024gl125 + - name: efm32jg12b500f1024gl125 diff --git a/boards/arm/efm32pg_stk3402a/doc/efm32pg_stk3402a.jpg b/boards/silabs/efm32pg_stk3402a/doc/efm32pg_stk3402a.jpg similarity index 100% rename from boards/arm/efm32pg_stk3402a/doc/efm32pg_stk3402a.jpg rename to boards/silabs/efm32pg_stk3402a/doc/efm32pg_stk3402a.jpg diff --git a/boards/silabs/efm32pg_stk3402a/doc/index.rst b/boards/silabs/efm32pg_stk3402a/doc/index.rst new file mode 100644 index 00000000000..8014f310b0c --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/doc/index.rst @@ -0,0 +1,212 @@ +.. _efm32pg_stk3402a: + +EFM32 Pearl Gecko Starter Kit +############################# + +Overview +******** + +The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3402A contains an MCU from the +EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low +power capabilities. + +.. figure:: efm32pg_stk3402a.jpg + :align: center + :alt: EFM32PG-SLSTK3402A + + EFM32PG-SLSTK3402A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel Memory-LCD +- 2 user buttons, 2 LEDs and a touch slider +- Humidity, temperature, and inductive-capacitive metal sensor +- On-board Segger J-Link USB debugger + +For more information about the EFM32PG SoC and EFM32PG-STK3402A board: + +- `EFM32PG Website`_ +- `EFM32PG12 Datasheet`_ +- `EFM32PG12 Reference Manual`_ +- `EFM32PG-STK3402A Website`_ +- `EFM32PG-STK3402A User Guide`_ +- `EFM32PG-STK3402A Schematics`_ + +Supported Features +================== + +The efm32pg_stk3402a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | true random number generator | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125_defconfig` + +The default configuration when building for this EFM32JG12B SoC can be found in +:zephyr_file:`boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125_defconfig` + +Other hardware features are currently not supported by the port. + +EFM32 Jade Gecko SoC +-------------------- + +The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3402A can also be used to evaluate +the EFM32 Jade Gecko SoC (EFM32JG12B). The only difference between the Pearl +Gecko and the Jade Gecko is their core. The Pearl Gecko contains an ARM® +Cortex®-M4F core, and the Jade Gecko an ARM® Cortex®-M3 core. Other features +such as memory and peripherals are the same. + +Code that is built for the Jade Gecko also runs on an equivalent Pearl Gecko. + +To build firmware for the Jade Gecko and run it on the EFM32 Pearl Gecko Starter +Kit, use the board ``efm32pg_stk3402a/efm32pg12b500f1024gl125`` instead of ``efm32pg_stk3402a/efm32jg12b500f1024gl125``. + +Connections and IOs +=================== + +The EFM32PG12 SoC has twelve GPIO controllers (PORTA to PORTL), but only four +are currently enabled (PORTA, PORTB, PORTD and PORTF) for the EFM32PG-STK3402A +board. + +In the following table, the column **Name** contains pin names. For example, PE2 +means pin number 2 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PF6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | ++-------+-------------+-------------------------------------+ +| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | ++-------+-------------+-------------------------------------+ +| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | ++-------+-------------+-------------------------------------+ +| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | ++-------+-------------+-------------------------------------+ +| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | ++-------+-------------+-------------------------------------+ +| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32PG SoC is configured to use the 40 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32PG SoC has four USARTs and one Low Energy UART (LEUART). + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32PG-STK3402A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a mass storage device and a + USB serial port. +- A serial flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to EFM32PG-STK3402A +------------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32pg_stk3402a/efm32pg12b500f1024gl125 + :goals: build + +Connect the EFM32PG-STK3402A to your host computer using the USB port and you +should see a USB connection which exposes a mass storage device(STK3402A). +Copy the generated zephyr.bin to the STK3402A drive. + +Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the +expansion header. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! arm + + +.. _EFM32PG-STK3402A Website: + https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-pearl-gecko-pg12-starter-kit + +.. _EFM32PG-STK3402A User Guide: + https://www.silabs.com/documents/public/user-guides/ug257-stk3402-usersguide.pdf + +.. _EFM32PG-STK3402A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD2501A-A01-schematic.pdf + +.. _EFM32PG Website: + https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko + +.. _EFM32PG12 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32pg12-datasheet.pdf + +.. _EFM32PG12 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32pg12-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a-pinctrl.dtsi b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a-pinctrl.dtsi similarity index 100% rename from boards/arm/efm32pg_stk3402a/efm32pg_stk3402a-pinctrl.dtsi rename to boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a-pinctrl.dtsi diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi similarity index 100% rename from boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi rename to boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg.dts b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.dts similarity index 100% rename from boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg.dts rename to boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.dts diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.yaml b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.yaml new file mode 100644 index 00000000000..7373e65edb2 --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.yaml @@ -0,0 +1,19 @@ +identifier: efm32pg_stk3402a/efm32jg12b500f1024gl125 +name: EFM32PG-STK3402A-JG +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - i2c + - gpio + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125_defconfig b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125_defconfig new file mode 100644 index 00000000000..f220c60c9a8 --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 +CONFIG_CMU_HFCLK_HFXO=y diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a.dts b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.dts similarity index 100% rename from boards/arm/efm32pg_stk3402a/efm32pg_stk3402a.dts rename to boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.dts diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.yaml b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.yaml new file mode 100644 index 00000000000..153ebae67ef --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.yaml @@ -0,0 +1,20 @@ +identifier: efm32pg_stk3402a/efm32pg12b500f1024gl125 +name: EFM32PG-STK3402A +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - i2c + - gpio + - nvs + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125_defconfig b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125_defconfig new file mode 100644 index 00000000000..f220c60c9a8 --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 +CONFIG_CMU_HFCLK_HFXO=y diff --git a/boards/silabs/efm32wg_stk3800/Kconfig.defconfig b/boards/silabs/efm32wg_stk3800/Kconfig.defconfig new file mode 100644 index 00000000000..12fb1b4f236 --- /dev/null +++ b/boards/silabs/efm32wg_stk3800/Kconfig.defconfig @@ -0,0 +1,14 @@ +# EFM32WG STK3800 board + +# Copyright (c) 2017, Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32WG_STK3800 + +config CMU_HFXO_FREQ + default 48000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_EFM32WG_STK3800 diff --git a/boards/silabs/efm32wg_stk3800/Kconfig.efm32wg_stk3800 b/boards/silabs/efm32wg_stk3800/Kconfig.efm32wg_stk3800 new file mode 100644 index 00000000000..025ac1849f0 --- /dev/null +++ b/boards/silabs/efm32wg_stk3800/Kconfig.efm32wg_stk3800 @@ -0,0 +1,7 @@ +# EFM32WG STK3800 board + +# Copyright (c) 2017, Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32WG_STK3800 + select SOC_PART_NUMBER_EFM32WG990F256 diff --git a/boards/arm/efm32wg_stk3800/board.cmake b/boards/silabs/efm32wg_stk3800/board.cmake similarity index 100% rename from boards/arm/efm32wg_stk3800/board.cmake rename to boards/silabs/efm32wg_stk3800/board.cmake diff --git a/boards/silabs/efm32wg_stk3800/board.yml b/boards/silabs/efm32wg_stk3800/board.yml new file mode 100644 index 00000000000..034c623141b --- /dev/null +++ b/boards/silabs/efm32wg_stk3800/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32wg_stk3800 + vendor: silabs + socs: + - name: efm32wg990f256 diff --git a/boards/arm/efm32wg_stk3800/doc/efm32wg_stk3800.jpg b/boards/silabs/efm32wg_stk3800/doc/efm32wg_stk3800.jpg similarity index 100% rename from boards/arm/efm32wg_stk3800/doc/efm32wg_stk3800.jpg rename to boards/silabs/efm32wg_stk3800/doc/efm32wg_stk3800.jpg diff --git a/boards/silabs/efm32wg_stk3800/doc/index.rst b/boards/silabs/efm32wg_stk3800/doc/index.rst new file mode 100644 index 00000000000..30810f0d71e --- /dev/null +++ b/boards/silabs/efm32wg_stk3800/doc/index.rst @@ -0,0 +1,177 @@ +.. _efm32wg_stk3800: + +EFM32WG-STK3800 +############### + +Overview +******** + +The EFM32 Wonder Gecko Starter Kit EFM32WG-STK3800 contains a MCU from the +EFM32WG family built on ARM® Cortex®-M4F processor with excellent low +power capabilities. + +.. figure:: efm32wg_stk3800.jpg + :align: center + :alt: EFM32WG-STK3800 + + EFM32WG-STK3800 (image courtesy of Silicon Labs) + + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- 32MByte parallel NAND Flash +- 160 segment Energy Micro LCD +- 2 user buttons, 2 LEDs and a touch slider +- Ambient Light Sensor and Inductive-capacitive metal sensor +- On-board Segger J-Link USB debugger + +For more information about the EFM32WG SoC and EFM32WG-STK3800 board: + +- `EFM32WG Website`_ +- `EFM32WG Datasheet`_ +- `EFM32WG Reference Manual`_ +- `EFM32WG-STK3800 Website`_ +- `EFM32WG-STK3800 User Guide`_ +- `EFM32WG-STK3800 Schematics`_ + +Supported Features +================== + +The efm32wg_stk3800 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32wg_stk3800/efm32wg_stk3800_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32WG SoC has six gpio controllers (PORTA to PORTF), but only three are +currently enabled (PORTB, PORTE and PORTF) for the EFM32WG-STK3800 board. + +In the following table, the column Name contains Pin names. For example, PE2 +means Pin number 2 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PE2 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PE3 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PB9 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PB10 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PE0 | UART0_TX | UART Console EFM_BC_TX U0_TX #1 | ++-------+-------------+-------------------------------------+ +| PE1 | UART0_RX | UART Console EFM_BC_RX U0_RX #1 | ++-------+-------------+-------------------------------------+ + +System Clock +============ + +The EFM32WG SoC is configured to use the 48 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32WG SoC has three USARTs, two UARTs and two Low Energy UARTs (LEUART). +UART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32WG-STK3800 includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a Mass Storage and a + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +Flashing an application to EFM32-STK3800 +---------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32wg_stk3800 + :goals: build + +Connect the EFM32WG-STK3800 to your host computer using the USB port and you +should see a USB connection which exposes a Mass Storage (STK3800) and a +USB Serial Port. Copy the generated zephyr.bin in the STK3800 drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! arm + + +.. _EFM32WG-STK3800 Website: + http://www.silabs.com/products/development-tools/mcu/32-bit/efm32-wonder-gecko-starter-kit + +.. _EFM32WG-STK3800 User Guide: + http://www.silabs.com/documents/public/user-guides/efm32wg-stk3800-ug.pdf + +.. _EFM32WG-STK3800 Schematics: + http://www.silabs.com/documents/public/schematic-files/BRD2400A_A00.pdf + +.. _EFM32WG Website: + http://www.silabs.com/products/mcu/32-bit/efm32-wonder-gecko + +.. _EFM32WG Datasheet: + http://www.silabs.com/documents/public/data-sheets/EFM32WG990.pdf + +.. _EFM32WG Reference Manual: + http://www.silabs.com/documents/public/reference-manuals/EFM32WG-RM.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32wg_stk3800/efm32wg_stk3800.dts b/boards/silabs/efm32wg_stk3800/efm32wg_stk3800.dts similarity index 100% rename from boards/arm/efm32wg_stk3800/efm32wg_stk3800.dts rename to boards/silabs/efm32wg_stk3800/efm32wg_stk3800.dts diff --git a/boards/arm/efm32wg_stk3800/efm32wg_stk3800.yaml b/boards/silabs/efm32wg_stk3800/efm32wg_stk3800.yaml similarity index 100% rename from boards/arm/efm32wg_stk3800/efm32wg_stk3800.yaml rename to boards/silabs/efm32wg_stk3800/efm32wg_stk3800.yaml diff --git a/boards/arm/efm32wg_stk3800/efm32wg_stk3800_defconfig b/boards/silabs/efm32wg_stk3800/efm32wg_stk3800_defconfig similarity index 76% rename from boards/arm/efm32wg_stk3800/efm32wg_stk3800_defconfig rename to boards/silabs/efm32wg_stk3800/efm32wg_stk3800_defconfig index cda53788ee6..5563b773d7d 100644 --- a/boards/arm/efm32wg_stk3800/efm32wg_stk3800_defconfig +++ b/boards/silabs/efm32wg_stk3800/efm32wg_stk3800_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32WG=y -CONFIG_BOARD_EFM32WG_STK3800=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/silabs/efr32_radio/Kconfig.defconfig b/boards/silabs/efr32_radio/Kconfig.defconfig new file mode 100644 index 00000000000..ce20c2ef360 --- /dev/null +++ b/boards/silabs/efr32_radio/Kconfig.defconfig @@ -0,0 +1,51 @@ +# EFR32 radio board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFR32_RADIO + +config CMU_HFXO_FREQ + default 39000000 if BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48 + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x08000000 if BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48 + default 0x0 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default n if SOC_FAMILY_SILABS_S1 + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config MINIMAL_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +choice BT_HCI_BUS_TYPE + default BT_SILABS_HCI +endchoice + +endif # BT + +endif # BOARD_EFR32_RADIO diff --git a/boards/silabs/efr32_radio/Kconfig.efr32_radio b/boards/silabs/efr32_radio/Kconfig.efr32_radio new file mode 100644 index 00000000000..1ebc6a94455 --- /dev/null +++ b/boards/silabs/efr32_radio/Kconfig.efr32_radio @@ -0,0 +1,15 @@ +# EFR32BG13 BRD4104A / EFR32MG21 BRD4180A / +# EFR32FG1P BRD4250B / EFR32FG13P BRD4255A board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32_RADIO + select SOC_PART_NUMBER_EFR32BG13P632F512GM48 if BOARD_EFR32_RADIO_EFR32BG13P632F512GM48 + select SOC_PART_NUMBER_EFR32MG12P433F1024GM68 if BOARD_EFR32_RADIO_EFR32MG12P433F1024GM68 + select SOC_PART_NUMBER_EFR32MG12P432F1024GL125 if BOARD_EFR32_RADIO_EFR32MG12P432F1024GL125 + select SOC_PART_NUMBER_EFR32FG1P133F256GM48 if BOARD_EFR32_RADIO_EFR32FG1P133F256GM48 + select SOC_PART_NUMBER_EFR32MG21A020F1024IM32 if BOARD_EFR32_RADIO_EFR32MG21A020F1024IM32 + select SOC_PART_NUMBER_EFR32MG24B220F1536IM48 if BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48 + select SOC_PART_NUMBER_EFR32FG13P233F512GM48 if BOARD_EFR32_RADIO_EFR32FG13P233F512GM48 diff --git a/boards/silabs/efr32_radio/board.cmake b/boards/silabs/efr32_radio/board.cmake new file mode 100644 index 00000000000..142165be8c7 --- /dev/null +++ b/boards/silabs/efr32_radio/board.cmake @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd) + +if(CONFIG_BOARD_EFR32_RADIO_EFR32BG13P632F512GM48) + board_runner_args(jlink "--device=EFR32BG13PxxxF512") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32FG1P133F256GM48) + board_runner_args(jlink "--device=EFR32FG1PxxxF256") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG12P433F1024GM68) + board_runner_args(jlink "--device=EFR32MG12PxxxF1024") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG12P432F1024GL125) + board_runner_args(jlink "--device=EFR32MG12PxxxF1024") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG21A020F1024IM32) + board_runner_args(jlink "--device=EFR32MG21AxxxF1024") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48) + board_runner_args(jlink "--device=EFR32MG24BxxxF1536") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32FG13P233F512GM48) + board_runner_args(jlink "--device=EFR32FG13PxxxF512") +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/efr32_radio/board.yml b/boards/silabs/efr32_radio/board.yml new file mode 100644 index 00000000000..5e68cef3826 --- /dev/null +++ b/boards/silabs/efr32_radio/board.yml @@ -0,0 +1,10 @@ +boards: + - name: efr32_radio + socs: + - name: efr32bg13p632f512gm48 + - name: efr32mg12p433f1024gm68 + - name: efr32mg12p432f1024gl125 + - name: efr32fg1p133f256gm48 + - name: efr32mg21a020f1024im32 + - name: efr32mg24b220f1536im48 + - name: efr32fg13p233f512gm48 diff --git a/boards/arm/efr32_radio/doc/brd4104a.rst b/boards/silabs/efr32_radio/doc/brd4104a.rst similarity index 93% rename from boards/arm/efr32_radio/doc/brd4104a.rst rename to boards/silabs/efr32_radio/doc/brd4104a.rst index e52f54d22c2..7fa1336345c 100644 --- a/boards/arm/efr32_radio/doc/brd4104a.rst +++ b/boards/silabs/efr32_radio/doc/brd4104a.rst @@ -49,11 +49,10 @@ Supported Features Please refer to :ref:`EFR32 Radio Board Supported Features ` for details of the configuration and common features supported by the -efr32_radio_brd4104a board. +``efr32_radio/efr32bg13p632f512gm48`` board. -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4104a_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48_defconfig` System Clock ============ @@ -84,7 +83,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4104a + :board: efr32_radio/efr32bg13p632f512gm48 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -98,7 +97,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4104a + Hello World! efr32_radio .. _EFR32BG13 Website: diff --git a/boards/arm/efr32_radio/doc/brd4161a.rst b/boards/silabs/efr32_radio/doc/brd4161a.rst similarity index 91% rename from boards/arm/efr32_radio/doc/brd4161a.rst rename to boards/silabs/efr32_radio/doc/brd4161a.rst index f51d54b5f3d..992d5f7a4ac 100644 --- a/boards/arm/efr32_radio/doc/brd4161a.rst +++ b/boards/silabs/efr32_radio/doc/brd4161a.rst @@ -44,11 +44,10 @@ Supported Features Please refer to :ref:`EFR32 Radio Board Supported Features ` for details of the configuration and common features supported by the -efr32_radio_brd4161a board. +``efr32_radio/efr32mg12p432f1024gl125`` board. -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4161a_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig` System Clock ============ @@ -79,7 +78,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4161a + :board: efr32_radio/efr32mg12p432f1024gl125 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -93,7 +92,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4161a + Hello World! efr32_radio .. _EFR32MG12 Website: diff --git a/boards/arm/efr32_radio/doc/brd4170a.rst b/boards/silabs/efr32_radio/doc/brd4170a.rst similarity index 91% rename from boards/arm/efr32_radio/doc/brd4170a.rst rename to boards/silabs/efr32_radio/doc/brd4170a.rst index 9924c2b1d1a..a1751424f37 100644 --- a/boards/arm/efr32_radio/doc/brd4170a.rst +++ b/boards/silabs/efr32_radio/doc/brd4170a.rst @@ -44,11 +44,10 @@ Supported Features Please refer to :ref:`EFR32 Radio Board Supported Features ` for details of the configuration and common features supported by the -efr32_radio_brd4170a board. +``efr32_radio/efr32mg12p433f1024gm68`` board. -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4170a_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig` System Clock ============ @@ -79,7 +78,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4170a + :board: efr32_radio/efr32mg12p433f1024gm68 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -93,7 +92,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4170a + Hello World! efr32_radio .. _EFR32MG12 Website: diff --git a/boards/arm/efr32_radio/doc/brd4180a.rst b/boards/silabs/efr32_radio/doc/brd4180a.rst similarity index 96% rename from boards/arm/efr32_radio/doc/brd4180a.rst rename to boards/silabs/efr32_radio/doc/brd4180a.rst index 870b324a279..4998122bbcd 100644 --- a/boards/arm/efr32_radio/doc/brd4180a.rst +++ b/boards/silabs/efr32_radio/doc/brd4180a.rst @@ -95,9 +95,8 @@ means Pin number 2 on PORTA, as used in the board's datasheets and manuals. | PA6 | USART1_RX | UART Console EFM_BC_RX US1_RX | +-------+-------------+-------------------------------------+ -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4180a_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig` System Clock ============ @@ -128,7 +127,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4180a + :board: efr32_radio/efr32mg21a020f1024im32 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -142,7 +141,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4180a + Hello World! efr32_radio .. _EFR32-SLWSTK6006A Website: diff --git a/boards/arm/efr32_radio/doc/brd4187c.rst b/boards/silabs/efr32_radio/doc/brd4187c.rst similarity index 96% rename from boards/arm/efr32_radio/doc/brd4187c.rst rename to boards/silabs/efr32_radio/doc/brd4187c.rst index 03ff14ad45c..63f106bd072 100644 --- a/boards/arm/efr32_radio/doc/brd4187c.rst +++ b/boards/silabs/efr32_radio/doc/brd4187c.rst @@ -96,9 +96,8 @@ means Pin number 2 on PORTA, as used in the board's datasheets and manuals. | PA9 | USART0_RX | UART Console VCOM_RX US0_RX | +-------+-------------+-------------------------------------+ -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4187c_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig`` System Clock ============ @@ -129,7 +128,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4187c + :board: efr32_radio/efr32mg24b220f1536im48 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -143,7 +142,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4187c + Hello World! efr32_radio .. _xG24-PK6010A Website: diff --git a/boards/arm/efr32_radio/doc/brd4250b.rst b/boards/silabs/efr32_radio/doc/brd4250b.rst similarity index 93% rename from boards/arm/efr32_radio/doc/brd4250b.rst rename to boards/silabs/efr32_radio/doc/brd4250b.rst index effac2a407e..6ccb4ca22ca 100644 --- a/boards/arm/efr32_radio/doc/brd4250b.rst +++ b/boards/silabs/efr32_radio/doc/brd4250b.rst @@ -48,11 +48,10 @@ Supported Features Please refer to :ref:`EFR32 Radio Board Supported Features ` for details of the configuration and common features supported by the -efr32_radio_brd4250b board. +``efr32_radio/efr32fg1p133f256gm48`` board. -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4250b_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig` System Clock ============ @@ -83,7 +82,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4250b + :board: efr32_radio/efr32fg1p133f256gm48 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -97,7 +96,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4250b + Hello World! efr32_radio .. _EFR32FG1 Website: diff --git a/boards/arm/efr32_radio/doc/brd4255a.rst b/boards/silabs/efr32_radio/doc/brd4255a.rst similarity index 92% rename from boards/arm/efr32_radio/doc/brd4255a.rst rename to boards/silabs/efr32_radio/doc/brd4255a.rst index ab81e513c90..60138f08610 100644 --- a/boards/arm/efr32_radio/doc/brd4255a.rst +++ b/boards/silabs/efr32_radio/doc/brd4255a.rst @@ -44,11 +44,10 @@ Supported Features Please refer to :ref:`EFR32 Radio Board Supported Features ` for details of the configuration and common features supported by the -efr32_radio_brd4255a board. +``efr32_radio/efr32fg13p233f512gm48`` board. -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4255a_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig` System Clock ============ @@ -79,7 +78,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4255a + :board: efr32_radio/efr32fg13p233f512gm48 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -93,7 +92,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4255a + Hello World! efr32_radio .. _EFR32FG13 Website: diff --git a/boards/arm/efr32_radio/doc/efr32_slwstk6020b.jpg b/boards/silabs/efr32_radio/doc/efr32_slwstk6020b.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32_slwstk6020b.jpg rename to boards/silabs/efr32_radio/doc/efr32_slwstk6020b.jpg diff --git a/boards/arm/efr32_radio/doc/efr32bg13-slwrb4104a.jpg b/boards/silabs/efr32_radio/doc/efr32bg13-slwrb4104a.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32bg13-slwrb4104a.jpg rename to boards/silabs/efr32_radio/doc/efr32bg13-slwrb4104a.jpg diff --git a/boards/arm/efr32_radio/doc/efr32fg1-slwrb4250b.jpg b/boards/silabs/efr32_radio/doc/efr32fg1-slwrb4250b.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32fg1-slwrb4250b.jpg rename to boards/silabs/efr32_radio/doc/efr32fg1-slwrb4250b.jpg diff --git a/boards/arm/efr32_radio/doc/efr32fg13-slwrb4255a.jpg b/boards/silabs/efr32_radio/doc/efr32fg13-slwrb4255a.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32fg13-slwrb4255a.jpg rename to boards/silabs/efr32_radio/doc/efr32fg13-slwrb4255a.jpg diff --git a/boards/arm/efr32_radio/doc/efr32mg12-slwrb4161a.jpeg b/boards/silabs/efr32_radio/doc/efr32mg12-slwrb4161a.jpeg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32mg12-slwrb4161a.jpeg rename to boards/silabs/efr32_radio/doc/efr32mg12-slwrb4161a.jpeg diff --git a/boards/arm/efr32_radio/doc/efr32mg12-slwrb4170a.jpg b/boards/silabs/efr32_radio/doc/efr32mg12-slwrb4170a.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32mg12-slwrb4170a.jpg rename to boards/silabs/efr32_radio/doc/efr32mg12-slwrb4170a.jpg diff --git a/boards/arm/efr32_radio/doc/efr32mg21-slwrb4180a.jpg b/boards/silabs/efr32_radio/doc/efr32mg21-slwrb4180a.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32mg21-slwrb4180a.jpg rename to boards/silabs/efr32_radio/doc/efr32mg21-slwrb4180a.jpg diff --git a/boards/arm/efr32_radio/doc/efr32mg24-xg24-rb4187c.jpg b/boards/silabs/efr32_radio/doc/efr32mg24-xg24-rb4187c.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32mg24-xg24-rb4187c.jpg rename to boards/silabs/efr32_radio/doc/efr32mg24-xg24-rb4187c.jpg diff --git a/boards/arm/efr32_radio/doc/index.rst b/boards/silabs/efr32_radio/doc/index.rst similarity index 100% rename from boards/arm/efr32_radio/doc/index.rst rename to boards/silabs/efr32_radio/doc/index.rst diff --git a/boards/arm/efr32_radio/efr32_radio-pinctrl.dtsi b/boards/silabs/efr32_radio/efr32_radio-pinctrl.dtsi similarity index 100% rename from boards/arm/efr32_radio/efr32_radio-pinctrl.dtsi rename to boards/silabs/efr32_radio/efr32_radio-pinctrl.dtsi diff --git a/boards/arm/efr32_radio/efr32_radio.dtsi b/boards/silabs/efr32_radio/efr32_radio.dtsi similarity index 100% rename from boards/arm/efr32_radio/efr32_radio.dtsi rename to boards/silabs/efr32_radio/efr32_radio.dtsi diff --git a/boards/arm/efr32_radio/efr32_radio_brd4104a.dts b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.dts similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4104a.dts rename to boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.dts diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.yaml new file mode 100644 index 00000000000..8edaadbadf7 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.yaml @@ -0,0 +1,22 @@ +identifier: efr32_radio/efr32bg13p632f512gm48 +name: BRD4104A +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48_defconfig new file mode 100644 index 00000000000..17eefb534ca --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4255a.dts b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.dts similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4255a.dts rename to boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.dts diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.yaml new file mode 100644 index 00000000000..af096e1af9e --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.yaml @@ -0,0 +1,22 @@ +identifier: efr32_radio/efr32fg13p233f512gm48 +name: BRD4255A +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig new file mode 100644 index 00000000000..17eefb534ca --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4250b.dts b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.dts similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4250b.dts rename to boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.dts diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.yaml new file mode 100644 index 00000000000..356d959514c --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.yaml @@ -0,0 +1,22 @@ +identifier: efr32_radio/efr32fg1p133f256gm48 +name: BRD4250B +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig new file mode 100644 index 00000000000..17eefb534ca --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4161a.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.dts similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4161a.dts rename to boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.dts diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.yaml new file mode 100644 index 00000000000..8092040c672 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.yaml @@ -0,0 +1,21 @@ +identifier: efr32_radio/efr32mg12p432f1024gl125 +name: BRD4161A +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig new file mode 100644 index 00000000000..17eefb534ca --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4170a.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.dts similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4170a.dts rename to boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.dts diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.yaml new file mode 100644 index 00000000000..ac0779d0d01 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.yaml @@ -0,0 +1,21 @@ +identifier: efr32_radio/efr32mg12p433f1024gm68 +name: BRD4170A +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig new file mode 100644 index 00000000000..17eefb534ca --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4180a-pinctrl.dtsi b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32-pinctrl.dtsi similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4180a-pinctrl.dtsi rename to boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32-pinctrl.dtsi diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.dts new file mode 100644 index 00000000000..379fd031e22 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.dts @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "efr32_radio_efr32mg21a020f1024im32-pinctrl.dtsi" + +/ { + model = "Silicon Labs BRD4180A (Mighty Gecko Radio Board)"; + compatible = "silabs,efr32mg21_brd4180a", "silabs,efr32mg21"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiob 0 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiob 1 0>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpiod 2 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpiod 3 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + +}; + +&cpu0 { + clock-frequency = <38400000>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtcc0 { + prescaler = <1>; + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&wdog0 { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x0000c000>; + read-only; + }; + + /* Reserve 464 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 0x00074000>; + }; + + /* Reserve 464 kB for the application in slot 1 */ + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x00080000 0x00074000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@f4000 { + label = "image-scratch"; + reg = <0x000f4000 0x00008000>; + }; + + /* Set 16Kb of storage at the end of the 1024Kb of flash */ + storage_partition: partition@fc000 { + label = "storage"; + reg = <0x000fc000 0x00004000>; + }; + + }; +}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.yaml new file mode 100644 index 00000000000..c6103f5336b --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.yaml @@ -0,0 +1,21 @@ +identifier: efr32_radio/efr32mg21a020f1024im32 +name: BRD4180A +type: mcu +arch: arm +ram: 96 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig new file mode 100644 index 00000000000..053f12a36f4 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_PINCTRL=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4187c-pinctrl.dtsi b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48-pinctrl.dtsi similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4187c-pinctrl.dtsi rename to boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48-pinctrl.dtsi diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.dts new file mode 100644 index 00000000000..0fb0b4becc3 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.dts @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2023 Fr. Sauter AG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "efr32_radio_efr32mg24b220f1536im48-pinctrl.dtsi" + +/ { + model = "Silicon Labs BRD4187C (Mighty Gecko Radio Board)"; + compatible = "silabs,efr32mg24_brd4187c", "silabs,efr32mg24"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + +}; + +&cpu0 { + clock-frequency = <39000000>; +}; + +&pstate_em3 { + status = "disabled"; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&burtc0 { + status = "okay"; +}; + +&stimer0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(48)>; + read-only; + }; + + /* Reserve 720 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 0x000B4000>; + }; + + /* Reserve 720 kB for the application in slot 1 */ + slot1_partition: partition@C0000 { + label = "image-1"; + reg = <0x000C0000 0x000B4000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@174000 { + label = "image-scratch"; + reg = <0x00174000 DT_SIZE_K(32)>; + }; + + /* Set 16 kB of storage at the end of the 1536 kB of flash */ + storage_partition: partition@17c000 { + label = "storage"; + reg = <0x0017c000 DT_SIZE_K(16)>; + }; + }; +}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.yaml new file mode 100644 index 00000000000..278f40a4866 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.yaml @@ -0,0 +1,21 @@ +identifier: efr32_radio/efr32mg24b220f1536im48 +name: BRD4187C +type: mcu +arch: arm +ram: 256 +flash: 1536 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth + - pm + - hwinfo +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig new file mode 100644 index 00000000000..7e41ebc6a13 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=78000000 +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y +CONFIG_PINCTRL=y + +# Use BURTC as system clock source +CONFIG_GECKO_BURTC_TIMER=y +CONFIG_CMU_BURTCCLK_LFXO=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1024 diff --git a/boards/arm/efr32_radio/pre_dt_board.cmake b/boards/silabs/efr32_radio/pre_dt_board.cmake similarity index 100% rename from boards/arm/efr32_radio/pre_dt_board.cmake rename to boards/silabs/efr32_radio/pre_dt_board.cmake diff --git a/boards/arm/efr32_radio/support/openocd.cfg b/boards/silabs/efr32_radio/support/openocd.cfg similarity index 100% rename from boards/arm/efr32_radio/support/openocd.cfg rename to boards/silabs/efr32_radio/support/openocd.cfg diff --git a/boards/arm/efr32_thunderboard/CMakeLists.txt b/boards/silabs/efr32_thunderboard/CMakeLists.txt similarity index 100% rename from boards/arm/efr32_thunderboard/CMakeLists.txt rename to boards/silabs/efr32_thunderboard/CMakeLists.txt diff --git a/boards/arm/efr32_thunderboard/Kconfig b/boards/silabs/efr32_thunderboard/Kconfig similarity index 100% rename from boards/arm/efr32_thunderboard/Kconfig rename to boards/silabs/efr32_thunderboard/Kconfig diff --git a/boards/silabs/efr32_thunderboard/Kconfig.defconfig b/boards/silabs/efr32_thunderboard/Kconfig.defconfig new file mode 100644 index 00000000000..9c116263518 --- /dev/null +++ b/boards/silabs/efr32_thunderboard/Kconfig.defconfig @@ -0,0 +1,38 @@ +# Thunderboard-style boards + +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config CMU_HFXO_FREQ + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +choice BT_HCI_BUS_TYPE + default BT_SILABS_HCI +endchoice + +endif # BT + +config REGULATOR + default y if SI7210 diff --git a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184a b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184a new file mode 100644 index 00000000000..2cbcd439761 --- /dev/null +++ b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184a @@ -0,0 +1,7 @@ +# EFR32BG SLTB010A board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32BG22_BRD4184A + select SOC_PART_NUMBER_EFR32BG22C224F512IM40 diff --git a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184b b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184b new file mode 100644 index 00000000000..48a8915cf5a --- /dev/null +++ b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184b @@ -0,0 +1,7 @@ +# EFR32BG SLTB010A board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32BG22_BRD4184B + select SOC_PART_NUMBER_EFR32BG22C224F512IM40 diff --git a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg27_brd2602a b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg27_brd2602a new file mode 100644 index 00000000000..7bf2e70d455 --- /dev/null +++ b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg27_brd2602a @@ -0,0 +1,7 @@ +# EFR32BG SLTB010A board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32BG27_BRD2602A + select SOC_PART_NUMBER_EFR32BG27C140F768IM40 diff --git a/boards/arm/efr32_thunderboard/board.c b/boards/silabs/efr32_thunderboard/board.c similarity index 100% rename from boards/arm/efr32_thunderboard/board.c rename to boards/silabs/efr32_thunderboard/board.c diff --git a/boards/silabs/efr32_thunderboard/board.cmake b/boards/silabs/efr32_thunderboard/board.cmake new file mode 100644 index 00000000000..d27a7983eb1 --- /dev/null +++ b/boards/silabs/efr32_thunderboard/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_EFR32BG22_BRD4184A OR CONFIG_BOARD_EFR32BG22_BRD4184B) + board_runner_args(jlink "--device=EFR32BG22C224F512IM40" "--reset-after-load") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +elseif(CONFIG_BOARD_EFR32BG27_BRD2602A) + board_runner_args(silabs_commander "--device=EFR32BG27C140F768IM40") + include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) +endif() diff --git a/boards/silabs/efr32_thunderboard/board.yml b/boards/silabs/efr32_thunderboard/board.yml new file mode 100644 index 00000000000..ebfe25a104c --- /dev/null +++ b/boards/silabs/efr32_thunderboard/board.yml @@ -0,0 +1,13 @@ +boards: + - name: efr32bg22_brd4184a + vendor: silabs + socs: + - name: efr32bg22c224f512im40 + - name: efr32bg22_brd4184b + vendor: silabs + socs: + - name: efr32bg22c224f512im40 + - name: efr32bg27_brd2602a + vendor: silabs + socs: + - name: efr32bg27c140f768im40 diff --git a/boards/arm/efr32_thunderboard/doc/brd2602.rst b/boards/silabs/efr32_thunderboard/doc/brd2602.rst similarity index 100% rename from boards/arm/efr32_thunderboard/doc/brd2602.rst rename to boards/silabs/efr32_thunderboard/doc/brd2602.rst diff --git a/boards/arm/efr32_thunderboard/doc/brd4184.rst b/boards/silabs/efr32_thunderboard/doc/brd4184.rst similarity index 96% rename from boards/arm/efr32_thunderboard/doc/brd4184.rst rename to boards/silabs/efr32_thunderboard/doc/brd4184.rst index 56685b31079..a6f1c281d3c 100644 --- a/boards/arm/efr32_thunderboard/doc/brd4184.rst +++ b/boards/silabs/efr32_thunderboard/doc/brd4184.rst @@ -79,9 +79,10 @@ The efr32bg22_brd4184a/b board configuration supports the following hardware fea | RADIO | on-chip | bluetooth | +-----------+------------+-------------------------------------+ -The default configuration can be found in the defconfig files: -- ``boards/arm/efr32_thunderboard/efr32bg22_brd4184a_defconfig`` -- ``boards/arm/efr32_thunderboard/efr32bg22_brd4184b_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_thunderboard/efr32bg22_brd4184a_defconfig` +and +:zephyr_file:`boards/silabs/efr32_thunderboard/efr32bg22_brd4184b_defconfig` Connections and IOs =================== @@ -168,17 +169,9 @@ Open a serial terminal (minicom, putty, etc.) with the following settings: Reset the board and you should be able to see on the corresponding Serial Port the following message: -BRD4184A: - -.. code-block:: console - - Hello World! efr32bg22_brd4184a - -BRD4184B: - .. code-block:: console - Hello World! efr32bg22_brd4184b + Hello World! efr32bg22_brd4184 Bluetooth ========= diff --git a/boards/arm/efr32_thunderboard/doc/efr32bg_sltb010a.jpg b/boards/silabs/efr32_thunderboard/doc/efr32bg_sltb010a.jpg similarity index 100% rename from boards/arm/efr32_thunderboard/doc/efr32bg_sltb010a.jpg rename to boards/silabs/efr32_thunderboard/doc/efr32bg_sltb010a.jpg diff --git a/boards/arm/efr32_thunderboard/doc/index.rst b/boards/silabs/efr32_thunderboard/doc/index.rst similarity index 100% rename from boards/arm/efr32_thunderboard/doc/index.rst rename to boards/silabs/efr32_thunderboard/doc/index.rst diff --git a/boards/arm/efr32_thunderboard/dts/bindings/silabs,gecko-wake-up-triggers.yaml b/boards/silabs/efr32_thunderboard/dts/bindings/silabs,gecko-wake-up-triggers.yaml similarity index 100% rename from boards/arm/efr32_thunderboard/dts/bindings/silabs,gecko-wake-up-triggers.yaml rename to boards/silabs/efr32_thunderboard/dts/bindings/silabs,gecko-wake-up-triggers.yaml diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184.dtsi b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184.dtsi similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184.dtsi rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184.dtsi diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184a.dts b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.dts similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184a.dts rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.dts diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184a.yaml b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.yaml similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184a.yaml rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.yaml diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184a_defconfig b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a_defconfig similarity index 88% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184a_defconfig rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184a_defconfig index cbef0c4a05c..50a14221ec9 100644 --- a/boards/arm/efr32_thunderboard/efr32bg22_brd4184a_defconfig +++ b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32BG22=y -CONFIG_BOARD_EFR32BG22_BRD4184A=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184b.dts b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.dts similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184b.dts rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.dts diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184b.yaml b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.yaml similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184b.yaml rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.yaml diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184b_defconfig b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b_defconfig similarity index 88% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184b_defconfig rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184b_defconfig index 2d2e5f1ad7e..50a14221ec9 100644 --- a/boards/arm/efr32_thunderboard/efr32bg22_brd4184b_defconfig +++ b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32BG22=y -CONFIG_BOARD_EFR32BG22_BRD4184B=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/efr32_thunderboard/efr32bg27_brd2602a.dts b/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.dts similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg27_brd2602a.dts rename to boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.dts diff --git a/boards/arm/efr32_thunderboard/efr32bg27_brd2602a.yaml b/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.yaml similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg27_brd2602a.yaml rename to boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.yaml diff --git a/boards/arm/efr32_thunderboard/efr32bg27_brd2602a_defconfig b/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a_defconfig similarity index 88% rename from boards/arm/efr32_thunderboard/efr32bg27_brd2602a_defconfig rename to boards/silabs/efr32_thunderboard/efr32bg27_brd2602a_defconfig index ecb0b7172ff..50a14221ec9 100644 --- a/boards/arm/efr32_thunderboard/efr32bg27_brd2602a_defconfig +++ b/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32BG27=y -CONFIG_BOARD_EFR32BG27_BRD2602A=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/efr32_thunderboard/pre_dt_board.cmake b/boards/silabs/efr32_thunderboard/pre_dt_board.cmake similarity index 100% rename from boards/arm/efr32_thunderboard/pre_dt_board.cmake rename to boards/silabs/efr32_thunderboard/pre_dt_board.cmake diff --git a/boards/arm/efr32_thunderboard/thunderboard.dtsi b/boards/silabs/efr32_thunderboard/thunderboard.dtsi similarity index 100% rename from boards/arm/efr32_thunderboard/thunderboard.dtsi rename to boards/silabs/efr32_thunderboard/thunderboard.dtsi diff --git a/boards/arm/efr32mg_sltb004a/CMakeLists.txt b/boards/silabs/efr32mg_sltb004a/CMakeLists.txt similarity index 100% rename from boards/arm/efr32mg_sltb004a/CMakeLists.txt rename to boards/silabs/efr32mg_sltb004a/CMakeLists.txt diff --git a/boards/silabs/efr32mg_sltb004a/Kconfig.defconfig b/boards/silabs/efr32mg_sltb004a/Kconfig.defconfig new file mode 100644 index 00000000000..5dd6c6417a7 --- /dev/null +++ b/boards/silabs/efr32mg_sltb004a/Kconfig.defconfig @@ -0,0 +1,14 @@ +# EFR32MG SLTB004A board + +# Copyright (c) 2018, Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFR32MG_SLTB004A + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_EFR32MG_SLTB004A diff --git a/boards/silabs/efr32mg_sltb004a/Kconfig.efr32mg_sltb004a b/boards/silabs/efr32mg_sltb004a/Kconfig.efr32mg_sltb004a new file mode 100644 index 00000000000..3f2245d372e --- /dev/null +++ b/boards/silabs/efr32mg_sltb004a/Kconfig.efr32mg_sltb004a @@ -0,0 +1,7 @@ +# EFR32MG SLTB004A board + +# Copyright (c) 2018, Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32MG_SLTB004A + select SOC_PART_NUMBER_EFR32MG12P332F1024GL125 diff --git a/boards/arm/efr32mg_sltb004a/board.c b/boards/silabs/efr32mg_sltb004a/board.c similarity index 100% rename from boards/arm/efr32mg_sltb004a/board.c rename to boards/silabs/efr32mg_sltb004a/board.c diff --git a/boards/arm/efr32mg_sltb004a/board.cmake b/boards/silabs/efr32mg_sltb004a/board.cmake similarity index 100% rename from boards/arm/efr32mg_sltb004a/board.cmake rename to boards/silabs/efr32mg_sltb004a/board.cmake diff --git a/boards/silabs/efr32mg_sltb004a/board.yml b/boards/silabs/efr32mg_sltb004a/board.yml new file mode 100644 index 00000000000..cef6207cf03 --- /dev/null +++ b/boards/silabs/efr32mg_sltb004a/board.yml @@ -0,0 +1,5 @@ +board: + name: efr32mg_sltb004a + vendor: silabs + socs: + - name: efr32mg12p332f1024gl125 diff --git a/boards/arm/efr32mg_sltb004a/doc/efr32mg_sltb004a.jpg b/boards/silabs/efr32mg_sltb004a/doc/efr32mg_sltb004a.jpg similarity index 100% rename from boards/arm/efr32mg_sltb004a/doc/efr32mg_sltb004a.jpg rename to boards/silabs/efr32mg_sltb004a/doc/efr32mg_sltb004a.jpg diff --git a/boards/silabs/efr32mg_sltb004a/doc/index.rst b/boards/silabs/efr32mg_sltb004a/doc/index.rst new file mode 100644 index 00000000000..fb595bbc7a8 --- /dev/null +++ b/boards/silabs/efr32mg_sltb004a/doc/index.rst @@ -0,0 +1,220 @@ +.. _efr32mg_sltb004a: + +EFR32MG-SLTB004A +################ + +Overview +******** + +The EFR32™ Mighty Gecko Starter Kit EFR32MG-SLTB004A (a.k.a Thunderboard +Sense 2) contains a MCU from the EFR32MG family built on ARM® Cortex®-M4F +processor with low power capabilities. + +.. image:: efr32mg_sltb004a.jpg + :align: center + :alt: EFR32MG-SLTB004A + +Hardware +******** + +- EFR32MG12 Mighty Gecko Wireless SoC with 38.4 MHz operating frequency +- ARM® Cortex® M4 core with 256 kB RAM and 1024 kB Flash +- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F) +- 2.4 GHz ceramic antenna for wireless transmission +- Silicon Labs Si7021 relative humidity and temperature sensor +- Silicon Labs Si1133 UV index and ambient light sensor +- Silicon Labs Si7210 hall effect sensor +- Bosch Sensortec BMP280 barometric pressure sensor +- ams CCS811 indoor air quality gas sensor +- TDK InvenSense ICM-20648 6-axis inertial sensor +- TDK InvenSense ICS-43434 MEMS microphone +- Four high brightness RGB LEDs from Broadcom Limited (ASMT-YTB7-0AA02) +- One bi-color LED and two push buttons +- Power enable signals for fine grained power-control +- On-board SEGGER J-Link debugger for easy programming and debugging, which + includes a USB virtual COM port +- Mini Simplicity connector for access to energy profiling and advanced wireless + network debugging +- Breakout pads for GPIO access and connection to external hardware +- Reset button +- Automatic switch-over between USB and battery power +- CR2032 coin cell holder and external battery connector + +For more information about the EFR32MG SoC and Thunderboard Sense 2 +(EFR32MG-SLTB004A) board: + +- `EFR32MG Website`_ +- `EFR32MG Datasheet`_ +- `EFR32MG Reference Manual`_ +- `EFR32MG-SLTB004A Website`_ +- `EFR32MG-SLTB004A User Guide`_ +- `EFR32MG-SLTB004A Schematics`_ + +Supported Features +================== + +The efr32mg_sltb004a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | true random number generator | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig`` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFR32MG SoC has eight gpio controllers (PORTA, PORTB, PORTC, PORTD, +PORTF, PORTI, PORTJ and PORTK). + +In the following table, the column Name contains Pin names. For example, PE2 +means Pin number 2 on PORTE and #27 represents the location bitfield , as used +in the board's and microcontroller's datasheets and manuals. + ++------+-------------+-----------------------------------+ +| Name | Function | Usage | ++======+=============+===================================+ +| PD8 | GPIO | LED0 (RED) | ++------+-------------+-----------------------------------+ +| PD9 | GPIO | LED1 (GREEN) | ++------+-------------+-----------------------------------+ +| PD14 | GPIO | SW0 Push Button PB0 | ++------+-------------+-----------------------------------+ +| PD15 | GPIO | Push Button PB1 | ++------+-------------+-----------------------------------+ +| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | ++------+-------------+-----------------------------------+ +| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | ++------+-------------+-----------------------------------+ +| PF3 | UART_TX | EXP12_UART_TX LEU0_TX #27 | ++------+-------------+-----------------------------------+ +| PF4 | UART_RX | EXP14_UART_RX LEU0_RX #27 | ++------+-------------+-----------------------------------+ +| PC10 | I2C_SDA | EXP16_I2C_SDA I2C0_SDA #15 | ++------+-------------+-----------------------------------+ +| PC11 | I2C_SCL | EXP15_I2C_SCL I2C0_SCL #15 | ++------+-------------+-----------------------------------+ +| PB6 | I2C_SDA | CCS811_I2C_SDA I2C1_SDA #6 | ++------+-------------+-----------------------------------+ +| PB7 | I2C_SCL | CCS811_I2C_SCL I2C1_SCL #6 | ++------+-------------+-----------------------------------+ +| PK0 | SPI_MOSI | Flash MOSI US2_TX #29 | ++------+-------------+-----------------------------------+ +| PK2 | SPI_MISO | Flash MISO US2_RX #30 | ++------+-------------+-----------------------------------+ +| PF7 | SPI_SCLK | Flash SCLK US2_CLK #18 | ++------+-------------+-----------------------------------+ +| PK1 | SPI_CS | Flash Chip Select (GPIO) | ++------+-------------+-----------------------------------+ + +System Clock +============ + +The EFR32MG SoC is configured to use the 38.4 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG SoC has four USARTs and one Low Energy UARTs (LEUART with 9600 +maximum baudrate). USART0 is configured as the Zephyr console and is connected +to the On-Board J-Link Debugger that presents a virtual COM port for general +purpose application serial data transfer with this interface. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFR32MG-SLTB004A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a Mass Storage and a + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +Flashing an application to EFR32-SLTB004A +----------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efr32mg_sltb004a + :goals: build + +Connect the EFR32MG-SLTB004A to your host computer using the USB port and you +should see a USB connection which exposes a Mass Storage (TB004) and a +USB Serial Port. Copy the generated zephyr.bin in the SLTB004A drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! arm + + +.. _EFR32MG-SLTB004A Website: + https://www.silabs.com/products/development-tools/thunderboard/thunderboard-sense-two-kit + +.. _EFR32MG-SLTB004A User Guide: + https://www.silabs.com/documents/public/user-guides/ug309-sltb004a-user-guide.pdf + +.. _EFR32MG-SLTB004A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD4166A-D00-schematic.pdf + +.. _EFR32MG Website: + https://www.silabs.com/products/wireless/mesh-networking/efr32mg-mighty-gecko-zigbee-thread-soc + +.. _EFR32MG Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg12-datasheet.pdf + +.. _EFR32MG Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg12-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.dts b/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.dts similarity index 100% rename from boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.dts rename to boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.dts diff --git a/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.yaml b/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.yaml similarity index 100% rename from boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.yaml rename to boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.yaml diff --git a/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a_defconfig b/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig similarity index 80% rename from boards/arm/efr32mg_sltb004a/efr32mg_sltb004a_defconfig rename to boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig index 4182a0df8e4..17eefb534ca 100644 --- a/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a_defconfig +++ b/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32MG12P=y -CONFIG_BOARD_EFR32MG_SLTB004A=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/efr32mg_sltb004a/pre_dt_board.cmake b/boards/silabs/efr32mg_sltb004a/pre_dt_board.cmake similarity index 100% rename from boards/arm/efr32mg_sltb004a/pre_dt_board.cmake rename to boards/silabs/efr32mg_sltb004a/pre_dt_board.cmake diff --git a/boards/arm/efr32xg24_dk2601b/Kconfig b/boards/silabs/efr32xg24_dk2601b/Kconfig similarity index 100% rename from boards/arm/efr32xg24_dk2601b/Kconfig rename to boards/silabs/efr32xg24_dk2601b/Kconfig diff --git a/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig b/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig new file mode 100644 index 00000000000..a63ff0ee6a7 --- /dev/null +++ b/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig @@ -0,0 +1,42 @@ +# EFR32XG24 DK2601B board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFR32XG24_DK2601B + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x08000000 + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config MINIMAL_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 2304 + +choice BT_HCI_BUS_TYPE + default BT_SILABS_HCI +endchoice + +endif # BT + +endif # BOARD_EFR32XG24_DK2601B diff --git a/boards/silabs/efr32xg24_dk2601b/Kconfig.efr32xg24_dk2601b b/boards/silabs/efr32xg24_dk2601b/Kconfig.efr32xg24_dk2601b new file mode 100644 index 00000000000..3826dc11b2a --- /dev/null +++ b/boards/silabs/efr32xg24_dk2601b/Kconfig.efr32xg24_dk2601b @@ -0,0 +1,7 @@ +# EFR32XG24 DK2601B board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32XG24_DK2601B + select SOC_PART_NUMBER_EFR32MG24B310F1536IM48 diff --git a/boards/arm/efr32xg24_dk2601b/board.c b/boards/silabs/efr32xg24_dk2601b/board.c similarity index 100% rename from boards/arm/efr32xg24_dk2601b/board.c rename to boards/silabs/efr32xg24_dk2601b/board.c diff --git a/boards/arm/efr32xg24_dk2601b/board.cmake b/boards/silabs/efr32xg24_dk2601b/board.cmake similarity index 100% rename from boards/arm/efr32xg24_dk2601b/board.cmake rename to boards/silabs/efr32xg24_dk2601b/board.cmake diff --git a/boards/silabs/efr32xg24_dk2601b/board.yml b/boards/silabs/efr32xg24_dk2601b/board.yml new file mode 100644 index 00000000000..d4efb7ba178 --- /dev/null +++ b/boards/silabs/efr32xg24_dk2601b/board.yml @@ -0,0 +1,5 @@ +board: + name: efr32xg24_dk2601b + vendor: silabs + socs: + - name: efr32mg24b310f1536im48 diff --git a/boards/arm/efr32xg24_dk2601b/doc/img/efr32xg24_dk2601b.jpg b/boards/silabs/efr32xg24_dk2601b/doc/img/efr32xg24_dk2601b.jpg similarity index 100% rename from boards/arm/efr32xg24_dk2601b/doc/img/efr32xg24_dk2601b.jpg rename to boards/silabs/efr32xg24_dk2601b/doc/img/efr32xg24_dk2601b.jpg diff --git a/boards/silabs/efr32xg24_dk2601b/doc/index.rst b/boards/silabs/efr32xg24_dk2601b/doc/index.rst new file mode 100644 index 00000000000..f6be0f82889 --- /dev/null +++ b/boards/silabs/efr32xg24_dk2601b/doc/index.rst @@ -0,0 +1,184 @@ +.. _efr32mg24_dk2601b: + +xG24-DK2601B +########################### + +Overview +******** + +The EFR32MG24 Mighty Gecko Board dev kit contains +a Wireless System-On-Chip from the EFR32MG24 family built on an +ARM Cortex®-M33F processor with excellent low power capabilities. + +.. figure:: ./img/efr32xg24_dk2601b.jpg + :height: 260px + :align: center + :alt: SLWRB4180A Mighty Gecko Radio Board + + xG24-DK2601B (image courtesy of Silicon Labs) + +Hardware +******** + +- EFR32MG24B310F1536IM48-B Mighty Gecko SoC +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 1536 kB +- RAM: 256 kB +- Transmit power: up to +20 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). +- On board sensors: + + - Silicon Labs Si7021 relative humidity & temperature sensor + - Silicon Labs Si7210 hall effect sensor + - 2x TDK InvenSense ICS-43434 MEMS microphones with I2S output + - TDK InvenSense ICM-20689 6-axis inertial measurement sensor + - Vishay VEML6035 ambient light sensor + - Bosch BMP384 pressure sensor with internal temperature sensor + +For more information about the EFR32MG24 SoC and BRD2601B board, refer to these +documents: + +- `EFR32MG24 Website`_ +- `EFR32MG24 Datasheet`_ +- `EFR32xG24 Reference Manual`_ +- `BRD2601B User Guide`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | semailbox | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| I2C(M/S) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | bluetooth | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PA4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PB0 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PB2 | GPIO | Push Button 0 | ++-------+-------------+-------------------------------------+ +| PB3 | GPIO | Push Button 1 | ++-------+-------------+-------------------------------------+ +| PA5 | USART0_TX | UART Console EFM_BC_TX US0_TX | ++-------+-------------+-------------------------------------+ +| PA6 | USART0_RX | UART Console EFM_BC_RX US0_RX | ++-------+-------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig` + +System Clock +============ + +The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG24 SoC has one USART and two EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efr32xg24_dk2601b + :goals: build + +Connect the efr32xg24_dk2601b to your host computer using the USB port and you +should see a USB connection. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! efr32xg24_dk2601b + +Bluetooth +========= + +To use the BLE function, run the command below to retrieve necessary binary +blobs from the SiLabs HAL repository. + +.. code-block:: console + + west blobs fetch silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :ref:`bluetooth-observer-sample` sample application is used in +this example. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: efr32xg24_dk2601b + :goals: build + +.. _EFR32MG24 Website: + https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-socs# + +.. _EFR32MG24 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf + +.. _EFR32xG24 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg24-rm.pdf + +.. _BRD2601B User Guide: + https://www.silabs.com/documents/public/user-guides/ug524-brd2601b-user-guide.pdf + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efr32xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml b/boards/silabs/efr32xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml similarity index 100% rename from boards/arm/efr32xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml rename to boards/silabs/efr32xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml diff --git a/boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b.dts b/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.dts similarity index 100% rename from boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b.dts rename to boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.dts diff --git a/boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b.yaml b/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.yaml similarity index 100% rename from boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b.yaml rename to boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.yaml diff --git a/boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig b/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig similarity index 86% rename from boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig rename to boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig index e09abbd5482..caadb4bb35b 100644 --- a/boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig +++ b/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2022 Silicon Labs # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFR32MG24=y -CONFIG_BOARD_EFR32XG24_DK2601B=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -11,9 +9,9 @@ CONFIG_CORTEX_M_SYSTICK=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=76800000 CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y CONFIG_CMU_HFCLK_LFXO=y CONFIG_HW_STACK_PROTECTION=y CONFIG_PINCTRL=y CONFIG_REGULATOR=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32xg24_dk2601b/pre_dt_board.cmake b/boards/silabs/efr32xg24_dk2601b/pre_dt_board.cmake similarity index 100% rename from boards/arm/efr32xg24_dk2601b/pre_dt_board.cmake rename to boards/silabs/efr32xg24_dk2601b/pre_dt_board.cmake diff --git a/boards/silabs/index.rst b/boards/silabs/index.rst new file mode 100644 index 00000000000..0b658035e63 --- /dev/null +++ b/boards/silabs/index.rst @@ -0,0 +1,10 @@ +.. _boards-silabs: + +Silabgs +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/sipeed/index.rst b/boards/sipeed/index.rst new file mode 100644 index 00000000000..e84a42fc254 --- /dev/null +++ b/boards/sipeed/index.rst @@ -0,0 +1,10 @@ +.. _boards-sipeed: + +Sipeed +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/sipeed/longan_nano/Kconfig.defconfig b/boards/sipeed/longan_nano/Kconfig.defconfig new file mode 100644 index 00000000000..2eef2edbc2f --- /dev/null +++ b/boards/sipeed/longan_nano/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Sipeed longan nano Development Board Configuration + +# Copyright (c) 2021 Tokita, Hiroshi + +if BOARD_LONGAN_NANO + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_LONGAN_NANO diff --git a/boards/sipeed/longan_nano/Kconfig.longan_nano b/boards/sipeed/longan_nano/Kconfig.longan_nano new file mode 100644 index 00000000000..2ac5424d6b7 --- /dev/null +++ b/boards/sipeed/longan_nano/Kconfig.longan_nano @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LONGAN_NANO + select SOC_GD32VF103 diff --git a/boards/riscv/longan_nano/board.cmake b/boards/sipeed/longan_nano/board.cmake similarity index 100% rename from boards/riscv/longan_nano/board.cmake rename to boards/sipeed/longan_nano/board.cmake diff --git a/boards/sipeed/longan_nano/board.yml b/boards/sipeed/longan_nano/board.yml new file mode 100644 index 00000000000..035ea8f540d --- /dev/null +++ b/boards/sipeed/longan_nano/board.yml @@ -0,0 +1,7 @@ +board: + name: longan_nano + vendor: sipeed + socs: + - name: gd32vf103 + variants: + - name: lite diff --git a/boards/riscv/longan_nano/doc/img/longan_nano.jpg b/boards/sipeed/longan_nano/doc/img/longan_nano.jpg similarity index 100% rename from boards/riscv/longan_nano/doc/img/longan_nano.jpg rename to boards/sipeed/longan_nano/doc/img/longan_nano.jpg diff --git a/boards/riscv/longan_nano/doc/index.rst b/boards/sipeed/longan_nano/doc/index.rst similarity index 100% rename from boards/riscv/longan_nano/doc/index.rst rename to boards/sipeed/longan_nano/doc/index.rst diff --git a/boards/riscv/longan_nano/longan_nano-common.dtsi b/boards/sipeed/longan_nano/longan_nano-common.dtsi similarity index 100% rename from boards/riscv/longan_nano/longan_nano-common.dtsi rename to boards/sipeed/longan_nano/longan_nano-common.dtsi diff --git a/boards/riscv/longan_nano/longan_nano-pinctrl.dtsi b/boards/sipeed/longan_nano/longan_nano-pinctrl.dtsi similarity index 100% rename from boards/riscv/longan_nano/longan_nano-pinctrl.dtsi rename to boards/sipeed/longan_nano/longan_nano-pinctrl.dtsi diff --git a/boards/riscv/longan_nano/longan_nano.dts b/boards/sipeed/longan_nano/longan_nano.dts similarity index 100% rename from boards/riscv/longan_nano/longan_nano.dts rename to boards/sipeed/longan_nano/longan_nano.dts diff --git a/boards/riscv/longan_nano/longan_nano.yaml b/boards/sipeed/longan_nano/longan_nano.yaml similarity index 100% rename from boards/riscv/longan_nano/longan_nano.yaml rename to boards/sipeed/longan_nano/longan_nano.yaml diff --git a/boards/riscv/longan_nano/longan_nano_defconfig b/boards/sipeed/longan_nano/longan_nano_defconfig similarity index 78% rename from boards/riscv/longan_nano/longan_nano_defconfig rename to boards/sipeed/longan_nano/longan_nano_defconfig index fc2aa06f616..353e533ef84 100644 --- a/boards/riscv/longan_nano/longan_nano_defconfig +++ b/boards/sipeed/longan_nano/longan_nano_defconfig @@ -4,10 +4,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_GD32VF103=y -CONFIG_SOC_GD32VF103=y -CONFIG_BOARD_LONGAN_NANO=y - CONFIG_GD32_HXTAL_8MHZ=y CONFIG_SERIAL=y diff --git a/boards/riscv/longan_nano/longan_nano_lite.dts b/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.dts similarity index 100% rename from boards/riscv/longan_nano/longan_nano_lite.dts rename to boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.dts diff --git a/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml b/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml new file mode 100644 index 00000000000..27636b6d47e --- /dev/null +++ b/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml @@ -0,0 +1,14 @@ +identifier: longan_nano/gd32vf103/lite +name: Sipeed Longan Nano Lite +type: mcu +arch: riscv +toolchain: + - zephyr + - xtools +flash: 64 +ram: 20 +supported: + - watchdog + - dma + - spi +vendor: sipeed diff --git a/boards/riscv/longan_nano/support/openocd.cfg b/boards/sipeed/longan_nano/support/openocd.cfg similarity index 100% rename from boards/riscv/longan_nano/support/openocd.cfg rename to boards/sipeed/longan_nano/support/openocd.cfg diff --git a/boards/sparc/generic_leon3/Kconfig.board b/boards/sparc/generic_leon3/Kconfig.board deleted file mode 100644 index 9ba65374a3c..00000000000 --- a/boards/sparc/generic_leon3/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GENERIC_LEON3 - bool "Generic LEON3 system" - depends on SOC_LEON3 diff --git a/boards/sparc/generic_leon3/Kconfig.defconfig b/boards/sparc/generic_leon3/Kconfig.defconfig deleted file mode 100644 index 97a92b57df5..00000000000 --- a/boards/sparc/generic_leon3/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GENERIC_LEON3 - -config BOARD - default "generic_leon3" - -config SPARC_CASA - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 50000000 - -config UART_INTERRUPT_DRIVEN - default y - -endif diff --git a/boards/sparc/generic_leon3/generic_leon3_defconfig b/boards/sparc/generic_leon3/generic_leon3_defconfig deleted file mode 100644 index 8ec49d62baf..00000000000 --- a/boards/sparc/generic_leon3/generic_leon3_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_LEON3=y -CONFIG_BOARD_GENERIC_LEON3=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_EXTRA_EXCEPTION_INFO=y diff --git a/boards/sparc/gr716a_mini/Kconfig.board b/boards/sparc/gr716a_mini/Kconfig.board deleted file mode 100644 index e200d6160c0..00000000000 --- a/boards/sparc/gr716a_mini/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GR716A_MINI - bool "GR716-MINI Development Board" - depends on SOC_GR716A diff --git a/boards/sparc/gr716a_mini/Kconfig.defconfig b/boards/sparc/gr716a_mini/Kconfig.defconfig deleted file mode 100644 index 08132736348..00000000000 --- a/boards/sparc/gr716a_mini/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GR716A_MINI - -config BOARD - default "gr716a_mini" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 20000000 - -config UART_INTERRUPT_DRIVEN - default y - -endif diff --git a/boards/sparc/gr716a_mini/gr716a_mini_defconfig b/boards/sparc/gr716a_mini/gr716a_mini_defconfig deleted file mode 100644 index 4f30129d3b2..00000000000 --- a/boards/sparc/gr716a_mini/gr716a_mini_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_GR716A=y -CONFIG_BOARD_GR716A_MINI=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/sparc/index.rst b/boards/sparc/index.rst deleted file mode 100644 index ef090183645..00000000000 --- a/boards/sparc/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-sparc: - -SPARC Boards -############ - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/sparc/qemu_leon3/Kconfig.board b/boards/sparc/qemu_leon3/Kconfig.board deleted file mode 100644 index 6ba0234a17a..00000000000 --- a/boards/sparc/qemu_leon3/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_LEON3 - bool "QEMU LEON3 target" - depends on SOC_LEON3 - select QEMU_TARGET - select CPU_HAS_FPU diff --git a/boards/sparc/qemu_leon3/Kconfig.defconfig b/boards/sparc/qemu_leon3/Kconfig.defconfig deleted file mode 100644 index 0a48c2a4752..00000000000 --- a/boards/sparc/qemu_leon3/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_LEON3 - -config BOARD - default "qemu_leon3" - -config UART_INTERRUPT_DRIVEN - default y - -endif diff --git a/boards/sparkfun/index.rst b/boards/sparkfun/index.rst new file mode 100644 index 00000000000..7f24ea10536 --- /dev/null +++ b/boards/sparkfun/index.rst @@ -0,0 +1,10 @@ +.. _boards-sparkfun-electronics: + +SparkFun Electronics +#################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/sparkfun/nrf52_sparkfun/Kconfig.defconfig b/boards/sparkfun/nrf52_sparkfun/Kconfig.defconfig new file mode 100644 index 00000000000..47d8a99ceca --- /dev/null +++ b/boards/sparkfun/nrf52_sparkfun/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Sparkfun nRF52832 breakout board configuration + +# Copyright (c) 2017 Shawn Nock +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52_SPARKFUN + +config BT_CTLR + default BT + +endif # BOARD_NRF52_SPARKFUN diff --git a/boards/sparkfun/nrf52_sparkfun/Kconfig.nrf52_sparkfun b/boards/sparkfun/nrf52_sparkfun/Kconfig.nrf52_sparkfun new file mode 100644 index 00000000000..b2a3c575e35 --- /dev/null +++ b/boards/sparkfun/nrf52_sparkfun/Kconfig.nrf52_sparkfun @@ -0,0 +1,8 @@ +# Sparkfun nRF52832 breakout board configuration + +# Copyright (c) 2017 Shawn Nock +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_SPARKFUN + select SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_sparkfun/board.cmake b/boards/sparkfun/nrf52_sparkfun/board.cmake similarity index 100% rename from boards/arm/nrf52_sparkfun/board.cmake rename to boards/sparkfun/nrf52_sparkfun/board.cmake diff --git a/boards/sparkfun/nrf52_sparkfun/board.yml b/boards/sparkfun/nrf52_sparkfun/board.yml new file mode 100644 index 00000000000..5e44e8a072b --- /dev/null +++ b/boards/sparkfun/nrf52_sparkfun/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52_sparkfun + vendor: sparkfun + socs: + - name: nrf52832 diff --git a/boards/arm/nrf52_sparkfun/doc/sparkfun-nrf52832-breakout-schematic-v10.pdf b/boards/sparkfun/nrf52_sparkfun/doc/sparkfun-nrf52832-breakout-schematic-v10.pdf similarity index 100% rename from boards/arm/nrf52_sparkfun/doc/sparkfun-nrf52832-breakout-schematic-v10.pdf rename to boards/sparkfun/nrf52_sparkfun/doc/sparkfun-nrf52832-breakout-schematic-v10.pdf diff --git a/boards/arm/nrf52_sparkfun/nrf52_sparkfun-pinctrl.dtsi b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52_sparkfun/nrf52_sparkfun-pinctrl.dtsi rename to boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun-pinctrl.dtsi diff --git a/boards/arm/nrf52_sparkfun/nrf52_sparkfun.dts b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.dts similarity index 100% rename from boards/arm/nrf52_sparkfun/nrf52_sparkfun.dts rename to boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.dts diff --git a/boards/arm/nrf52_sparkfun/nrf52_sparkfun.yaml b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.yaml similarity index 100% rename from boards/arm/nrf52_sparkfun/nrf52_sparkfun.yaml rename to boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.yaml diff --git a/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun_defconfig b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun_defconfig new file mode 100644 index 00000000000..7167aca850a --- /dev/null +++ b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/ruuvi_ruuvitag/pre_dt_board.cmake b/boards/sparkfun/nrf52_sparkfun/pre_dt_board.cmake similarity index 100% rename from boards/arm/ruuvi_ruuvitag/pre_dt_board.cmake rename to boards/sparkfun/nrf52_sparkfun/pre_dt_board.cmake diff --git a/boards/sparkfun/pro_micro_rp2040/Kconfig.defconfig b/boards/sparkfun/pro_micro_rp2040/Kconfig.defconfig new file mode 100644 index 00000000000..57aecafff00 --- /dev/null +++ b/boards/sparkfun/pro_micro_rp2040/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2021 Pete Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SPARKFUN_PRO_MICRO_RP2040 + +config RP2_FLASH_W25Q080 + default y + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_SPARKFUN_PRO_MICRO_RP2040 diff --git a/boards/sparkfun/pro_micro_rp2040/Kconfig.sparkfun_pro_micro_rp2040 b/boards/sparkfun/pro_micro_rp2040/Kconfig.sparkfun_pro_micro_rp2040 new file mode 100644 index 00000000000..1bb3c7bf6e5 --- /dev/null +++ b/boards/sparkfun/pro_micro_rp2040/Kconfig.sparkfun_pro_micro_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Pete Johanson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARKFUN_PRO_MICRO_RP2040 + select SOC_RP2040 diff --git a/boards/arm/sparkfun_pro_micro_rp2040/board.cmake b/boards/sparkfun/pro_micro_rp2040/board.cmake similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/board.cmake rename to boards/sparkfun/pro_micro_rp2040/board.cmake diff --git a/boards/sparkfun/pro_micro_rp2040/board.yml b/boards/sparkfun/pro_micro_rp2040/board.yml new file mode 100644 index 00000000000..ed9e449e8aa --- /dev/null +++ b/boards/sparkfun/pro_micro_rp2040/board.yml @@ -0,0 +1,5 @@ +board: + name: sparkfun_pro_micro_rp2040 + vendor: sparkfun + socs: + - name: rp2040 diff --git a/boards/arm/sparkfun_pro_micro_rp2040/doc/img/sparkfun_pro_micro_rp2040.jpg b/boards/sparkfun/pro_micro_rp2040/doc/img/sparkfun_pro_micro_rp2040.jpg similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/doc/img/sparkfun_pro_micro_rp2040.jpg rename to boards/sparkfun/pro_micro_rp2040/doc/img/sparkfun_pro_micro_rp2040.jpg diff --git a/boards/arm/sparkfun_pro_micro_rp2040/doc/index.rst b/boards/sparkfun/pro_micro_rp2040/doc/index.rst similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/doc/index.rst rename to boards/sparkfun/pro_micro_rp2040/doc/index.rst diff --git a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi rename to boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi diff --git a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi rename to boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi diff --git a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts rename to boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts diff --git a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml rename to boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml diff --git a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig similarity index 76% rename from boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig rename to boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig index 36aba349204..ef4e863884a 100644 --- a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig @@ -1,17 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_SPARKFUN_PRO_MICRO_RP2040=y - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 CONFIG_RESET=y -# enable uart driver +# Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/sparkfun/red_v_things_plus/Kconfig.defconfig b/boards/sparkfun/red_v_things_plus/Kconfig.defconfig new file mode 100644 index 00000000000..a67cae7efe3 --- /dev/null +++ b/boards/sparkfun/red_v_things_plus/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2019 SiFive Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SPARKFUN_RED_V_THINGS_PLUS + +config SYS_CLOCK_TICKS_PER_SEC + default 128 + +config HAS_FLASH_LOAD_OFFSET + default y + +config FLASH_LOAD_OFFSET + default 0x0 + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/spi@10014000,1) + +endif # BOARD_SPARKFUN_RED_V_THINGS_PLUS diff --git a/boards/sparkfun/red_v_things_plus/Kconfig.sparkfun_red_v_things_plus b/boards/sparkfun/red_v_things_plus/Kconfig.sparkfun_red_v_things_plus new file mode 100644 index 00000000000..7118f8a3ce3 --- /dev/null +++ b/boards/sparkfun/red_v_things_plus/Kconfig.sparkfun_red_v_things_plus @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARKFUN_RED_V_THINGS_PLUS + select SOC_SIFIVE_FREEDOM_FE310 diff --git a/boards/sparkfun/red_v_things_plus/board.cmake b/boards/sparkfun/red_v_things_plus/board.cmake new file mode 100644 index 00000000000..13417293188 --- /dev/null +++ b/boards/sparkfun/red_v_things_plus/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2019 SiFive Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=FE310") +board_runner_args(jlink "--iface=JTAG") +board_runner_args(jlink "--speed=4000") +board_runner_args(jlink "--tool-opt=-jtagconf -1,-1") +board_runner_args(jlink "--tool-opt=-autoconnect 1") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/sparkfun/red_v_things_plus/board.yml b/boards/sparkfun/red_v_things_plus/board.yml new file mode 100644 index 00000000000..6ef8e39c2f9 --- /dev/null +++ b/boards/sparkfun/red_v_things_plus/board.yml @@ -0,0 +1,5 @@ +board: + name: sparkfun_red_v_things_plus + vendor: sparkfun + socs: + - name: fe310 diff --git a/boards/riscv/sparkfun_red_v_things_plus/doc/img/sparkfun_red_v_things_plus.jpg b/boards/sparkfun/red_v_things_plus/doc/img/sparkfun_red_v_things_plus.jpg similarity index 100% rename from boards/riscv/sparkfun_red_v_things_plus/doc/img/sparkfun_red_v_things_plus.jpg rename to boards/sparkfun/red_v_things_plus/doc/img/sparkfun_red_v_things_plus.jpg diff --git a/boards/riscv/sparkfun_red_v_things_plus/doc/index.rst b/boards/sparkfun/red_v_things_plus/doc/index.rst similarity index 100% rename from boards/riscv/sparkfun_red_v_things_plus/doc/index.rst rename to boards/sparkfun/red_v_things_plus/doc/index.rst diff --git a/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus-pinctrl.dtsi b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus-pinctrl.dtsi similarity index 100% rename from boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus-pinctrl.dtsi rename to boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus-pinctrl.dtsi diff --git a/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus.dts b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus.dts similarity index 100% rename from boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus.dts rename to boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus.dts diff --git a/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus.yaml b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus.yaml similarity index 100% rename from boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus.yaml rename to boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus.yaml diff --git a/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus_defconfig b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus_defconfig new file mode 100644 index 00000000000..2085c58676a --- /dev/null +++ b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus_defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2019 SiFive Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y diff --git a/boards/sparkfun/thing_plus/Kconfig b/boards/sparkfun/thing_plus/Kconfig new file mode 100644 index 00000000000..dec3626ba75 --- /dev/null +++ b/boards/sparkfun/thing_plus/Kconfig @@ -0,0 +1,11 @@ +# Sparkfun nRF9160 Thing Plus configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# Copyright (c) 2020 Circuit Dojo LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARKFUN_THING_PLUS + # The GPIO driver is required by this board's initialization code + # (board.c), so it is forced here to be enabled always, not only + # enabled by default (in defconfig). + select GPIO diff --git a/boards/sparkfun/thing_plus/Kconfig.defconfig b/boards/sparkfun/thing_plus/Kconfig.defconfig new file mode 100644 index 00000000000..5273768aa50 --- /dev/null +++ b/boards/sparkfun/thing_plus/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Circuit Dojo nRF9160 Feather configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# Copyright (c) 2020 Circuit Dojo LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SPARKFUN_THING_PLUS + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_SPARKFUN_THING_PLUS_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_SPARKFUN_THING_PLUS_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_SPARKFUN_THING_PLUS_NRF9160 + +endif # BOARD_SPARKFUN_THING_PLUS diff --git a/boards/sparkfun/thing_plus/Kconfig.sparkfun_thing_plus b/boards/sparkfun/thing_plus/Kconfig.sparkfun_thing_plus new file mode 100644 index 00000000000..30710c008ee --- /dev/null +++ b/boards/sparkfun/thing_plus/Kconfig.sparkfun_thing_plus @@ -0,0 +1,8 @@ +# Sparkfun nRF9160 Thing Plus configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# Copyright (c) 2020 Circuit Dojo LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARKFUN_THING_PLUS + select SOC_NRF9160_SICA diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/board.cmake b/boards/sparkfun/thing_plus/board.cmake similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/board.cmake rename to boards/sparkfun/thing_plus/board.cmake diff --git a/boards/sparkfun/thing_plus/board.yml b/boards/sparkfun/thing_plus/board.yml new file mode 100644 index 00000000000..18037dfd5b6 --- /dev/null +++ b/boards/sparkfun/thing_plus/board.yml @@ -0,0 +1,7 @@ +board: + name: sparkfun_thing_plus + vendor: sparkfun + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/doc/img/sparkfun_thing_plus_nrf9160.jpg b/boards/sparkfun/thing_plus/doc/img/sparkfun_thing_plus_nrf9160.jpg similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/doc/img/sparkfun_thing_plus_nrf9160.jpg rename to boards/sparkfun/thing_plus/doc/img/sparkfun_thing_plus_nrf9160.jpg diff --git a/boards/sparkfun/thing_plus/doc/index.rst b/boards/sparkfun/thing_plus/doc/index.rst new file mode 100644 index 00000000000..a6c7aee9742 --- /dev/null +++ b/boards/sparkfun/thing_plus/doc/index.rst @@ -0,0 +1,153 @@ +.. _sparkfun_thing_plus_nrf9160: + +nRF9160 Thing Plus +################## + +.. figure:: img/sparkfun_thing_plus_nrf9160.jpg + :align: center + :alt: Sparkfun nRF9160 Thing Plus + + nRF9160 Thing Plus (Credit: Sparkfun) + +Overview +******** + +The nRF9160 Thing Plus designed by Circuit Dojo is a single-board development +for bringing your LTE-M and NB-IoT applications to life. The sparkfun_thing_plus_nrf9160 +board configuration leverages the pre-existing support for the Nordic Semiconductor +nRF9160. Supported nRF9160 peripherals include: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +More information about the board can be found at the +`nRF9160 Thing Plus Documentation`_. + + +Hardware +******** + +Connections and IOs +=================== + +The nRF9160 Thing Plus has everything you know and love about +the Feather platform. Here are some of the highlights: + +LED +--- + +* D7 (blue) = P0.03 + +Push buttons and Switches +------------------------- + +* MODE = P0.12 +* RESET + +USB +--- + +Contains a USB/UART connection for both debugging and loading new +code using a UART Enabled MCUBoot. + +Standard Battery Connection +---------------------------- + +The nRF9160 Thing Plus has a 2 pin battery connector on board. Lithium Polymer batteries > +300mA required. + +Nano SIM Holder +--------------- + +The nRF9160 Thing Plus has a built-in nano SIM (4FF) holder located +on the bottom side. + + +Programming and Debugging +************************* + +sparkfun_thing_plus_nrf9160 can be used with most programmers like: + +* J-Link (the nRF53-DK is recommended) +* CMSIS-DAP based programmers + +Check out `Getting Started`_ for more info. + +Building an application +======================= + +In most cases you'll want to use the ``ns`` target with any of the Zephyr +or Nordic based examples. + +Some of the examples do not use secure mode, so they do not required the ``ns`` suffix. +A great example of this is the `hello_world` below. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ screen /dev/ 115200 + +Replace :code:`` with the port where the nRF9160 Thing Plus +can be found. In most cases (On Linux/Mac) it will be: :code:`/dev/tty.SLAB_USBtoUART`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sparkfun_thing_plus_nrf9160 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons on the nRF9160 Thing Plus +****************************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common.dtsi`. + +References +********** + +.. target-notes:: + +**Side note** This page was based on the documentation for the nRF9160 DK. Thanks to Nordic for +developing a great platform! + +.. _nRF9160 Thing Plus Documentation: https://docs.jaredwolff.com/nrf9160-introduction.html +.. _Getting Started: https://docs.jaredwolff.com/nrf9160-getting-started.html diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160.dts b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.dts similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160.dts rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.dts diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160.yaml b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.yaml similarity index 82% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160.yaml rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.yaml index 8758b385c9d..f9d59872c14 100644 --- a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160.yaml +++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.yaml @@ -1,4 +1,4 @@ -identifier: sparkfun_thing_plus_nrf9160 +identifier: sparkfun_thing_plus/nrf9160 name: Sparkfun-Thing-Plus-nRF9160 type: mcu arch: arm diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_common-pinctrl.dtsi b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common-pinctrl.dtsi similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_common-pinctrl.dtsi rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common-pinctrl.dtsi diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_common.dtsi b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common.dtsi similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_common.dtsi rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common.dtsi diff --git a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_defconfig b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_defconfig new file mode 100644 index 00000000000..52852bb832c --- /dev/null +++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_REGULATOR=y diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns.dts b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.dts similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns.dts rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.dts diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns.yaml b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.yaml similarity index 81% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns.yaml rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.yaml index 65f9eaad326..6fbb1dfb13a 100644 --- a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns.yaml +++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.yaml @@ -1,4 +1,4 @@ -identifier: sparkfun_thing_plus_nrf9160_ns +identifier: sparkfun_thing_plus/nrf9160/ns name: Sparkfun-Thing-Plus-nRF9160-Non-Secure type: mcu arch: arm diff --git a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns_defconfig b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns_defconfig new file mode 100644 index 00000000000..2e8c7a1f9c8 --- /dev/null +++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns_defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_REGULATOR=y diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_partition_conf.dtsi b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_partition_conf.dtsi similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_partition_conf.dtsi rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_partition_conf.dtsi diff --git a/boards/st/b_g474e_dpow1/Kconfig.b_g474e_dpow1 b/boards/st/b_g474e_dpow1/Kconfig.b_g474e_dpow1 new file mode 100644 index 00000000000..75a8d42b2ee --- /dev/null +++ b/boards/st/b_g474e_dpow1/Kconfig.b_g474e_dpow1 @@ -0,0 +1,5 @@ +# Copyright 2022 The Chromium OS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_B_G474E_DPOW1 + select SOC_STM32G474XX diff --git a/boards/arm/b_g474e_dpow1/b_g474e_dpow1.dts b/boards/st/b_g474e_dpow1/b_g474e_dpow1.dts similarity index 100% rename from boards/arm/b_g474e_dpow1/b_g474e_dpow1.dts rename to boards/st/b_g474e_dpow1/b_g474e_dpow1.dts diff --git a/boards/arm/b_g474e_dpow1/b_g474e_dpow1.yaml b/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml similarity index 100% rename from boards/arm/b_g474e_dpow1/b_g474e_dpow1.yaml rename to boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml diff --git a/boards/arm/b_g474e_dpow1/b_g474e_dpow1_defconfig b/boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig similarity index 88% rename from boards/arm/b_g474e_dpow1/b_g474e_dpow1_defconfig rename to boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig index 6e0659f281d..3da57c5589e 100644 --- a/boards/arm/b_g474e_dpow1/b_g474e_dpow1_defconfig +++ b/boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig @@ -2,9 +2,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G4X=y -CONFIG_SOC_STM32G474XX=y - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/b_g474e_dpow1/board.cmake b/boards/st/b_g474e_dpow1/board.cmake similarity index 100% rename from boards/arm/b_g474e_dpow1/board.cmake rename to boards/st/b_g474e_dpow1/board.cmake diff --git a/boards/st/b_g474e_dpow1/board.yml b/boards/st/b_g474e_dpow1/board.yml new file mode 100644 index 00000000000..06d037f81a0 --- /dev/null +++ b/boards/st/b_g474e_dpow1/board.yml @@ -0,0 +1,5 @@ +board: + name: b_g474e_dpow1 + vendor: st + socs: + - name: stm32g474xx diff --git a/boards/arm/b_g474e_dpow1/doc/img/b_g474e_dpow1.jpg b/boards/st/b_g474e_dpow1/doc/img/b_g474e_dpow1.jpg similarity index 100% rename from boards/arm/b_g474e_dpow1/doc/img/b_g474e_dpow1.jpg rename to boards/st/b_g474e_dpow1/doc/img/b_g474e_dpow1.jpg diff --git a/boards/st/b_g474e_dpow1/doc/index.rst b/boards/st/b_g474e_dpow1/doc/index.rst new file mode 100644 index 00000000000..afaa8d94f81 --- /dev/null +++ b/boards/st/b_g474e_dpow1/doc/index.rst @@ -0,0 +1,159 @@ +.. _b_g474e_dpow1_board: + +ST B-G474E-DPOW1 Discovery +########################## + +Overview +******** +The B-G474E-DPOW1 Discovery kit is a digital power solution and a complete +demonstration and development platform for the STMicroelectronics STM32G474RET6 +microcontroller. Leveraging the new HRTimer-oriented features, 96 Kbytes of +embedded RAM, math accelerator functions and USB-PD 3.0 offered by STM32G474RET6, +the B-G474E-DPOW1 Discovery kit, based on the USB 2.0 FS Type-C™ connector +interface, helps the user to prototype applications with digital power such as a +buck-boost converter, RGB power LED lighting or a class-D audio amplifier. The +B-G474E-DPOW1 Discovery kit does not require any separate probe, as it integrates +the STLINK-V3E debugger and programmer. + +- STM32G474RET6 Arm® Cortex®-M4 core-based microcontroller, featuring 512 Kbytes + of Flash memory and 128 Kbytes of SRAM, in LQFP64 package +- USB Type-C™ with USB 2.0 FS interface compatible with USB-PD 3.0 +- RGB power LED for a bright lighting +- Digital power buck-boost converter with internal or external Input voltage and + with onboard resistor loads +- Audio Class-D amplifier capable +- 4 user LEDs +- 3 LEDs for power and ST-LINK communication +- 4-direction joystick with a selection button +- Reset push-button +- Board connectors: + - USB Type-C™ + - USB Micro-B + - 2 x 32-pin header, 2.54 mm pitch, daughterboard extension connector for breadboard connection +- Flexible power-supply options: ST-LINK USB VBUS or USB Type-C™ VBUS or external source +- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: mass storage, + Virtual COM port, and debug port + +.. image:: img/b_g474e_dpow1.jpg + :align: center + :alt: B-G474E-DPOW1 + +More information about the board can be found at the `B-G474E-DPOW1 website`_. + + +More information about STM32G474RE can be found here: +- `G474RE on www.st.com`_ +- `STM32G4 reference manual`_ + + +Supported Features +================== + +The Zephyr b_g474e_dpow1 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| UCPD | on-chip | ucpd | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) +- BUTTON (JOY_SEL) : PC13 +- BUTTON (JOY_LEFT) : PC4 +- BUTTON (JOY_DOWN) : PC5 +- BUTTON (JOY_RIGHT) : PB2 +- BUTTON (JOY_UP) : PB10 +- LED (DOWN BLUE) : PA15 +- LED (LEFT ORANGE) : PB1 +- LED (UP RED) : PB5 +- LED (RIGHT GREEN) : PB7 +- USB DM : PA11 +- USB DP : PA12 +- UCPD CC2 : PB4 +- UCPD CC1 : PB6 + +For more details please refer to `B-G474E-DPOW1 Discovery board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``b_g474e_dpow1`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The B-G474E-DPOW1 Discovery board includes an ST-LINK/V3E embedded debug tool interface. + +.. code-block:: console + + $ west flash + +Flashing an application to the B_G474E_DPOW1 +-------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: b_g474e_dpow1 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_g474e_dpow1 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _B-G474E-DPOW1 website: + https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html + +.. _STM32G4 reference manual: + https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _B-G474E-DPOW1 Discovery board User Manual: + https://www.st.com/resource/en/user_manual/um2577-discovery-kit-with-stm32g474re-mcu-stmicroelectronics.pdf + +.. _G474RE on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32g474re.html diff --git a/boards/st/b_l072z_lrwan1/Kconfig.b_l072z_lrwan1 b/boards/st/b_l072z_lrwan1/Kconfig.b_l072z_lrwan1 new file mode 100644 index 00000000000..6c1d12e2a80 --- /dev/null +++ b/boards/st/b_l072z_lrwan1/Kconfig.b_l072z_lrwan1 @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Aleksandr Makarov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_B_L072Z_LRWAN1 + select SOC_STM32L072XX diff --git a/boards/arm/b_l072z_lrwan1/b_l072z_lrwan1.dts b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.dts similarity index 100% rename from boards/arm/b_l072z_lrwan1/b_l072z_lrwan1.dts rename to boards/st/b_l072z_lrwan1/b_l072z_lrwan1.dts diff --git a/boards/arm/b_l072z_lrwan1/b_l072z_lrwan1.yaml b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml similarity index 100% rename from boards/arm/b_l072z_lrwan1/b_l072z_lrwan1.yaml rename to boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml diff --git a/boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig new file mode 100644 index 00000000000..8accdc5b47c --- /dev/null +++ b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/dragino_nbsn95/board.cmake b/boards/st/b_l072z_lrwan1/board.cmake similarity index 100% rename from boards/arm/dragino_nbsn95/board.cmake rename to boards/st/b_l072z_lrwan1/board.cmake diff --git a/boards/st/b_l072z_lrwan1/board.yml b/boards/st/b_l072z_lrwan1/board.yml new file mode 100644 index 00000000000..1a7b494de19 --- /dev/null +++ b/boards/st/b_l072z_lrwan1/board.yml @@ -0,0 +1,5 @@ +board: + name: b_l072z_lrwan1 + vendor: st + socs: + - name: stm32l072xx diff --git a/boards/arm/b_l072z_lrwan1/doc/img/b_l072z_lrwan1.jpg b/boards/st/b_l072z_lrwan1/doc/img/b_l072z_lrwan1.jpg similarity index 100% rename from boards/arm/b_l072z_lrwan1/doc/img/b_l072z_lrwan1.jpg rename to boards/st/b_l072z_lrwan1/doc/img/b_l072z_lrwan1.jpg diff --git a/boards/st/b_l072z_lrwan1/doc/index.rst b/boards/st/b_l072z_lrwan1/doc/index.rst new file mode 100644 index 00000000000..5ea80847871 --- /dev/null +++ b/boards/st/b_l072z_lrwan1/doc/index.rst @@ -0,0 +1,250 @@ +.. _b_l072z_lrwan1_board: + +ST B-L072Z-LRWAN1 Discovery kit +############################### + +Overview +******** + +This Discovery kit features an all-in-one open module CMWX1ZZABZ-091 (by Murata). +The module is powered by an STM32L072CZ and an SX1276 transceiver. + +This kit provides: + +- CMWX1ZZABZ-091 LoRa* / Sigfox* module (Murata) + + - Embedded ultra-low-power STM32L072CZ Series MCUs, based on + Arm* Cortex* -M0+ core, with 192 Kbytes of Flash + memory, 20 Kbytes of RAM, 6 Kbytes of EEPROM + - Frequency range: 860 MHz - 930 MHz + - USB 2.0 FS + - 4-channel,12-bit ADC, 2xDAC + - 6-bit timers, LP-UART, I2C and SPI + - Embedded SX1276 transceiver + - LoRa* , FSK, GFSK, MSK, GMSK and OOK modulations (+ Sigfox* compatibility) + - +14 dBm or +20 dBm selectable output power + - 157 dB maximum link budget + - Programmable bit rate up to 300 kbit/s + - High sensitivity: down to -137 dBm + - Bullet-proof front end: IIP3 = -12.5 dBm + - 89 dB blocking immunity + - Low Rx current of 10 mA, 200 nA register retention + - Fully integrated synthesizer with a resolution of 61 Hz + - Built-in bit synchronizer for clock recovery + - Sync word recognition + - Preamble detection + - 127 dB+ dynamic range RSSI + +- SMA and U.FL RF interface connectors +- Including 50 ohm SMA RF antenna +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability + +- USB ST-LINK functions: +- Board power supply: + + - Through USB bus or external VIN/3.3 V supply voltage or batteries +- 3xAAA-type-battery holder for standalone operation +- 7 LEDs: + + - 4 general-purpose LEDs + - A 5 V-power LED + - An ST-LINK-communication LED + - A fault-power LED + - 2 push-buttons (user and reset) +- Arduino* Uno V3 connectors + +.. image:: img/b_l072z_lrwan1.jpg + :align: center + :alt: B-L072Z-LRWAN1 + +More information about the board can be found at the `B-L072Z-LRWAN1 website`_. + +Hardware +******** + +The STM32L072CZ SoC provides the following hardware IPs: + +- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) +- Core: ARM* 32-bit Cortex*-M0+ CPU, frequency up to 32 MHz +- Clock Sources: + + - 1 to 32 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 37 kHz RC ( |plusminus| 5%) + - Internal multispeed low-power 65 kHz to 4.2 MHz RC +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 11x timers: + + - 2x 16-bit with up to 4 channels + - 2x 16-bit with up to 2 channels + - 1x 16-bit ultra-low-power timer + - 1x SysTick + - 1x RTC + - 2x 16-bit basic for DAC + - 2x watchdogs (independent/window) +- Up to 84 fast I/Os, most 5 V-tolerant. +- Memories + + - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 20 KB of SRAM + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 1.14 MSPS + - 2x 12-bit DAC + - 2x ultra-low-power comparators +- 11x communication interfaces + + - USB 2.0 full-speed device, LPM and BCD + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 6x SPIs (4x SPIs with the Quad SPI) +- 7-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32L072CZ can be found here: + +- `STM32L072CZ on www.st.com`_ +- `STM32L0x2 reference manual`_ + +Supported Features +================== + +The Zephyr B-L072Z-LRWAN1 Discovery board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | true random number generator | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| LoRa | on-module | sx1276 | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig` + + +Connections and IOs +=================== + +B-L072Z-LRWAN1 Discovery kit has GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- + +For detailed information about available pins please refer to `B-L072Z-LRWAN1 website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX/RX: PA9/PA10 (Arduino Serial) +- UART_2_TX/RX: PA2/PA3 (ST-Link Virtual COM Port) +- SPI1 NSS/SCK/MISO/MOSI: PA15/PB3/PA6/PA7 (Semtech SX1276 LoRa* Transceiver) +- SPI2 NSS/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 (Arduino SPI) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) + +System Clock +------------ + +B-L072Z-LRWAN1 Discovery board System Clock is at 32MHz. + +Serial Port +----------- + +B-L072Z-LRWAN1 Discovery board has 2 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + +USB device +---------- + +B-L072Z-LRWAN1 Discovery board has 1 USB device controller. However, +the USB data lines are not connected to the MCU by default. To connect +the USB data lines to the MCU, short solder bridges SB15 and SB16. + +Programming and Debugging +************************* + +Applications for the ``b_l072z_lrwan1`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +B-L072Z-LRWAN1 Discovery board includes an ST-LINK/V2-1 embedded debug +tool interface. This interface is supported by the openocd version included +in the Zephyr SDK since v0.9.2. + + +Flashing an application to B-L072Z-LRWAN1 Discovery board +--------------------------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Connect the B-L072Z-LRWAN1 Discovery board to a STLinkV2 to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_l072z_lrwan1 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_l072z_lrwan1 + :maybe-skip-config: + :goals: debug + +.. _B-L072Z-LRWAN1 website: + https://www.st.com/en/evaluation-tools/b-l072z-lrwan1.html + +.. _STM32L072CZ on www.st.com: + https://www.st.com/en/microcontrollers/stm32l072cz.html + +.. _STM32L0x2 reference manual: + https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/b_l072z_lrwan1/support/openocd.cfg b/boards/st/b_l072z_lrwan1/support/openocd.cfg similarity index 100% rename from boards/arm/b_l072z_lrwan1/support/openocd.cfg rename to boards/st/b_l072z_lrwan1/support/openocd.cfg diff --git a/boards/st/b_l4s5i_iot01a/Kconfig.b_l4s5i_iot01a b/boards/st/b_l4s5i_iot01a/Kconfig.b_l4s5i_iot01a new file mode 100644 index 00000000000..e4c8a21a27a --- /dev/null +++ b/boards/st/b_l4s5i_iot01a/Kconfig.b_l4s5i_iot01a @@ -0,0 +1,5 @@ +# Copyright (c) 2020 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_B_L4S5I_IOT01A + select SOC_STM32L4S5XX diff --git a/boards/st/b_l4s5i_iot01a/Kconfig.defconfig b/boards/st/b_l4s5i_iot01a/Kconfig.defconfig new file mode 100644 index 00000000000..36b722dbf38 --- /dev/null +++ b/boards/st/b_l4s5i_iot01a/Kconfig.defconfig @@ -0,0 +1,44 @@ +# B_L4S5I_IOT01A discovery kit board configuration + +# Copyright (c) 2020 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_B_L4S5I_IOT01A + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +choice LIS3MDL_TRIGGER_MODE + default LIS3MDL_TRIGGER_NONE +endchoice + +choice HTS221_TRIGGER_MODE + default HTS221_TRIGGER_NONE +endchoice + +choice LSM6DSL_TRIGGER_MODE + default LSM6DSL_TRIGGER_GLOBAL_THREAD + depends on LSM6DSL +endchoice + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +config BT_BLUENRG_ACI + default y +# Disable Flow control +config BT_HCI_ACL_FLOW_CONTROL + default n +config BT_HCI_VS_EXT + default n + +endif # BT + +endif # BOARD_B_L4S5I_IOT01A diff --git a/boards/arm/b_l4s5i_iot01a/arduino_r3_connector.dtsi b/boards/st/b_l4s5i_iot01a/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/b_l4s5i_iot01a/arduino_r3_connector.dtsi rename to boards/st/b_l4s5i_iot01a/arduino_r3_connector.dtsi diff --git a/boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a.dts b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts similarity index 100% rename from boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a.dts rename to boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts diff --git a/boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml similarity index 100% rename from boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml rename to boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml diff --git a/boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig similarity index 81% rename from boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig rename to boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig index 981dd5f1670..9e3dfce576e 100644 --- a/boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig +++ b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4S5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/b_l4s5i_iot01a/board.cmake b/boards/st/b_l4s5i_iot01a/board.cmake similarity index 100% rename from boards/arm/b_l4s5i_iot01a/board.cmake rename to boards/st/b_l4s5i_iot01a/board.cmake diff --git a/boards/st/b_l4s5i_iot01a/board.yml b/boards/st/b_l4s5i_iot01a/board.yml new file mode 100644 index 00000000000..e41cb4b1002 --- /dev/null +++ b/boards/st/b_l4s5i_iot01a/board.yml @@ -0,0 +1,5 @@ +board: + name: b_l4s5i_iot01a + vendor: st + socs: + - name: stm32l4s5xx diff --git a/boards/arm/b_l4s5i_iot01a/doc/img/b-l4s5i_iot01a.jpg b/boards/st/b_l4s5i_iot01a/doc/img/b-l4s5i_iot01a.jpg similarity index 100% rename from boards/arm/b_l4s5i_iot01a/doc/img/b-l4s5i_iot01a.jpg rename to boards/st/b_l4s5i_iot01a/doc/img/b-l4s5i_iot01a.jpg diff --git a/boards/st/b_l4s5i_iot01a/doc/index.rst b/boards/st/b_l4s5i_iot01a/doc/index.rst new file mode 100644 index 00000000000..17455c772dd --- /dev/null +++ b/boards/st/b_l4s5i_iot01a/doc/index.rst @@ -0,0 +1,233 @@ +.. _b_l4s5i_iot01a_board: + +ST B_L4S5I_IOT01A Discovery kit +############################### + +Overview +******** + +The B_L4S5I_IOT01A Discovery kit features an ARM Cortex-M4 based STM32L4S5VI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the B_L4S5I_IOT01A Discovery kit: + + +- STM32L4S5VIT6 microcontroller featuring 2 Mbyte of Flash memory, 640 Kbytes of RAM in LQFP100 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- Three different interfaces supported on USB: + + - Virtual com port + - Mass storage + - Debug port + +- ARDUINO ® Uno V3 and Pmod TM expansion connector +- 4 LEDs (2 for user, wifi, BLE) +- 2 push-buttons (user and reset) +- USB OTG FS with micro-AB connector +- Dynamic NFC tag +- 2 digital omnidirectional microphones +- Capacitive digital sensor for relative humidity and temperature +- Time-of-flight and gesture-detection sensors +- High-performance 3-axis magnetometer +- 3D accelerometer and 3D gyroscope +- 64-Mbit Quad-SPI Flash memory +- Bluetooth ® 4.1 module +- 802.11 b/g/n compliant Wi‐Fi ® module +- MCU current ammeter with 4 ranges and auto-calibration + +- Flexible power supply options: + - ST-LINK/V2-1 + - USB FS connector + - External 5 V + + +.. image:: img/b-l4s5i_iot01a.jpg + :align: center + :alt: B_L4S5I_IOT01A Discovery kit + +More information about the board can be found at the `B L4S5I IOT01A Discovery kit website`_. + +Hardware +******** + +The STM32L4S5VI SoC provides the following hardware features: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 120 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC +- RTC with HW calendar, alarms and calibration +- Up to 21 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + - 2x 16-bit advanced control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer +- Up to 83 fast I/Os, most 5 V-tolerant +- Memories + - Up to 2 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 640 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Octo SPI memory interface +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators +- 18x communication interfaces + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SDMMC I/F + - DCMI camera interface +- 14-channel DMA controller with multiplex request router +- True random number generator +- CRC calculation unit, 96-bit unique ID +- AES and HASH hardware accelerators +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L4S5VI can be found here: + - `STM32L4S5VI on www.st.com`_ + - `STM32L4S5 reference manual`_ + + +Supported Features +================== + +The Zephyr b_l4s5i_iot01a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| BLE | module | bluetooth | ++-----------+------------+-------------------------------------+ +| WIFI | module | es-wifi | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig` + + +Connections and IOs +=================== + +B_L4S5I_IOT01A Discovery kit has 9 GPIO controllers (from A to I). These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `B L47S5I IOT01A board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 (ST-Link Virtual Port Com) +- UART_4 TX/RX : PA0/PA1 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PB10/PB11 (Sensor I2C bus) +- SPI1 NSS/SCK/MISO/MOSI : PA2/PA5/PA6/PA7 (Arduino SPI) +- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (BT SPI bus) +- PWM_2_CH1 : PA15 +- LD1 : PA5 +- LD2 : PB14 +- user button : PC13 + +System Clock +------------ + +B_L4S5I_IOT01A Discovery System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +B_L4S5I_IOT01A Discovery kit has 4 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +B_L4S5I_IOT01A Discovery kit includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to B_L4S5I_IOT01A Discovery kit +------------------------------------------------------- + +Connect the B_L4S5I_IOT01A Discovery kit to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_l4s5i_iot01a + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_l4s5i_iot01a + :maybe-skip-config: + :goals: debug + +.. _B L4S5I IOT01A Discovery kit website: + https://www.st.com/en/evaluation-tools/b-l4s5i-iot01a.html + +.. _B L47S5I IOT01A board User Manual: + https://www.st.com/resource/en/user_manual/dm00698410.pdf + +.. _STM32L4S5VI on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l4s5vi.html + +.. _STM32L4S5 reference manual: + https://www.st.com/resource/en/reference_manual/dm00310109.pdf diff --git a/boards/arm/b_l4s5i_iot01a/support/openocd.cfg b/boards/st/b_l4s5i_iot01a/support/openocd.cfg similarity index 100% rename from boards/arm/b_l4s5i_iot01a/support/openocd.cfg rename to boards/st/b_l4s5i_iot01a/support/openocd.cfg diff --git a/boards/arm/b_u585i_iot02a/CMakeLists.txt b/boards/st/b_u585i_iot02a/CMakeLists.txt similarity index 100% rename from boards/arm/b_u585i_iot02a/CMakeLists.txt rename to boards/st/b_u585i_iot02a/CMakeLists.txt diff --git a/boards/st/b_u585i_iot02a/Kconfig.b_u585i_iot02a b/boards/st/b_u585i_iot02a/Kconfig.b_u585i_iot02a new file mode 100644 index 00000000000..0b544f0ae53 --- /dev/null +++ b/boards/st/b_u585i_iot02a/Kconfig.b_u585i_iot02a @@ -0,0 +1,5 @@ +# Copyright (c) 2021 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_B_U585I_IOT02A + select SOC_STM32U585XX diff --git a/boards/st/b_u585i_iot02a/Kconfig.defconfig b/boards/st/b_u585i_iot02a/Kconfig.defconfig new file mode 100644 index 00000000000..b8b6eeb4e2c --- /dev/null +++ b/boards/st/b_u585i_iot02a/Kconfig.defconfig @@ -0,0 +1,31 @@ +# B_U585I_IOT02A discovery kit board configuration + +# Copyright (c) 2021 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_B_U585I_IOT02A + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +if BUILD_WITH_TFM + +# Initial Attestation key provisioned by the BL1 bootloader +config TFM_INITIAL_ATTESTATION_KEY + default y + +config TFM_DUMMY_PROVISIONING + default n + +endif # BUILD_WITH_TFM + +# Disable Flow control +if BT + +config BT_HCI_ACL_FLOW_CONTROL + default n + +endif # BT + +endif # BOARD_B_U585I_IOT02A diff --git a/boards/arm/b_u585i_iot02a/arduino_r3_connector.dtsi b/boards/st/b_u585i_iot02a/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/b_u585i_iot02a/arduino_r3_connector.dtsi rename to boards/st/b_u585i_iot02a/arduino_r3_connector.dtsi diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a-common.dtsi b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi similarity index 100% rename from boards/arm/b_u585i_iot02a/b_u585i_iot02a-common.dtsi rename to boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a.dts b/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts similarity index 100% rename from boards/arm/b_u585i_iot02a/b_u585i_iot02a.dts rename to boards/st/b_u585i_iot02a/b_u585i_iot02a.dts diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a.yaml b/boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml similarity index 100% rename from boards/arm/b_u585i_iot02a/b_u585i_iot02a.yaml rename to boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig b/boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig similarity index 81% rename from boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig rename to boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig index c034f717771..9e3dfce576e 100644 --- a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U585XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns.dts b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.dts similarity index 100% rename from boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns.dts rename to boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.dts diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.yaml b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.yaml new file mode 100644 index 00000000000..662c6f18848 --- /dev/null +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.yaml @@ -0,0 +1,11 @@ +identifier: b_u585i_iot02a/stm32u585xx/ns +name: ST B_U585I_IOT02A Discovery kit non secure target +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 786 +flash: 512 +vendor: st diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns_defconfig b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns_defconfig new file mode 100644 index 00000000000..2141cc748f8 --- /dev/null +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns_defconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable pin controller +CONFIG_PINCTRL=y + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/b_u585i_iot02a/board.cmake b/boards/st/b_u585i_iot02a/board.cmake similarity index 100% rename from boards/arm/b_u585i_iot02a/board.cmake rename to boards/st/b_u585i_iot02a/board.cmake diff --git a/boards/st/b_u585i_iot02a/board.yml b/boards/st/b_u585i_iot02a/board.yml new file mode 100644 index 00000000000..55e740ec45d --- /dev/null +++ b/boards/st/b_u585i_iot02a/board.yml @@ -0,0 +1,7 @@ +board: + name: b_u585i_iot02a + vendor: st + socs: + - name: stm32u585xx + variants: + - name: ns diff --git a/boards/arm/b_u585i_iot02a/doc/img/b-u585i-iot02a.jpg b/boards/st/b_u585i_iot02a/doc/img/b-u585i-iot02a.jpg similarity index 100% rename from boards/arm/b_u585i_iot02a/doc/img/b-u585i-iot02a.jpg rename to boards/st/b_u585i_iot02a/doc/img/b-u585i-iot02a.jpg diff --git a/boards/st/b_u585i_iot02a/doc/index.rst b/boards/st/b_u585i_iot02a/doc/index.rst new file mode 100644 index 00000000000..2d9b782c90a --- /dev/null +++ b/boards/st/b_u585i_iot02a/doc/index.rst @@ -0,0 +1,438 @@ +.. _b_u585i_iot02a_board: + +ST B_U585I_IOT02A Discovery kit +############################### + +Overview +******** + +The B_U585I_IOT02A Discovery kit features an ARM Cortex-M33 based STM32U585AI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the B_U585I_IOT02A Discovery kit: + + +- STM32U585AII6Q microcontroller featuring 2 Mbyte of Flash memory, 786 Kbytes of RAM in UFBGA169 package +- 512-Mbit octal-SPI Flash memory, 64-Mbit octal-SPI PSRAM, 256-Kbit I2C EEPROM +- USB FS, Sink and Source power, 2.5 W power capability +- 802.11 b/g/n compliant Wi-Fi® module from MXCHIP +- Bluetooth Low Energy from STMicroelectronics +- MEMS sensors from STMicroelectronics + + - 2 digital microphones + - Relative humidity and temperature sensor + - 3-axis magnetometer + - 3D accelerometer and 3D gyroscope + - Pressure sensor, 260-1260 hPa absolute digital output barometer + - Time-of-flight and gesture-detection sensor + - Ambient-light sensor + +- 2 push-buttons (user and reset) +- 2 user LEDs + +- Flexible power supply options: + - ST-LINK/V3 + - USB Vbus + - External sources + + +.. image:: img/b-u585i-iot02a.jpg + :align: center + :alt: B_U585I_IOT02A Discovery kit + +More information about the board can be found at the `B U585I IOT02A Discovery kit website`_. + +Hardware +******** + +The STM32U585xx devices are an ultra-low-power microcontrollers family (STM32U5 +Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. +They operate at a frequency of up to 160 MHz. + +- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1.5 DMPIS/MHz (Drystone 2.1) + - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) + +- Security and cryptography + + - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals + - Flexible life cycle scheme with RDP (readout protection) and password protected debug + - Root of trust thanks to unique boot entry and secure hide protection area (HDP) + - Secure Firmware Installation thanks to embedded Root Secure Services + - Secure data storage with hardware unique key (HUK) + - Secure Firmware Update support with TF-M + - 2 AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - Active tampers + - True Random Number Generator NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte One-Time Programmable for user data + - Active tampers + +- Clock management: + + - 4 to 50 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + - Internal 48 MHz with clock recovery + +- Power management + + - Embedded regulator (LDO) + - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling + +- RTC with HW calendar and calibration +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- Up to 17 timers and 2 watchdogs + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5 x 16-bit general purpose + - 4x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- ART accelerator + + - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and + external memories: up to 160 MHz, MPU, 240 DMIPS and DSP + - 4-Kbyte data cache for external memories + +- Memories + + - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles + - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON + - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories + - 2 Octo-SPI memory interfaces + +- Rich analog peripherals (independent supply) + + - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling + - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode + - 12-bit DAC, low-power sample and hold + - 2 operational amplifiers with built-in PGA + - 2 ultra-low-power comparators + +- Up to 22 communication interfaces + + - USB Type-C / USB power delivery controller + - USB OTG 2.0 full-speed controller + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) + - 1x FDCAN + - 2x SDMMC interface + - 16- and 4-channel DMA controllers, functional in Stop mode + - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with + sound-activity detection + +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| +- True Random Number Generator (RNG) + +- Graphic features + + - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation + - 1 digital camera interface + +- Mathematical co-processor + + - CORDIC for trigonometric functions acceleration + - FMAC (filter mathematical accelerator) + + + +More information about STM32U585AI can be found here: + +- `STM32U585 on www.st.com`_ +- `STM32U585 reference manual`_ + + +Supported Features +================== + +The Zephyr b_u585i_iot02a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ +| BKP SRAM | on-chip | Backup SRAM | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ +| RADIO | STM32WB5MMG| Bluetooth Low Energy (BLE) | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig` + +Zephyr board options +==================== + +The STM32U585i is an SoC with Cortex-M33 architecture. Zephyr provides support +for building for both Secure and Non-Secure firmware. + +The BOARD options are summarized below: + ++-------------------------------+-------------------------------------------+ +| BOARD | Description | ++===============================+===========================================+ +| b_u585i_iot02a | For building Trust Zone Disabled firmware | ++-------------------------------+-------------------------------------------+ +| b_u585i_iot02a/stm32u585xx/ns | For building Non-Secure firmware | ++-------------------------------+-------------------------------------------+ + +Here are the instructions to build Zephyr with a non-secure configuration, +using `tfm_ipc_` sample: + + .. code-block:: bash + + $ west build -b b_u585i_iot02a/stm32u585xx/ns samples/tfm_integration/tfm_ipc/ + +Once done, before flashing, you need to first run a generated script that +will set platform option bytes config and erase platform (among others, +option bit TZEN will be set). + + .. code-block:: bash + + $ ./build/tfm/regression.sh + $ west flash + +Please note that, after having run a TFM sample on the board, you will need to +run `./build/tfm/regression.sh` once more to clean up the board from secure +options and get back the platform back to a "normal" state and be able to run +usual, non-TFM, binaries. +Also note that, even then, TZEN will remain set, and you will need to use +STM32CubeProgrammer_ to disable it fully, if required. + +Connections and IOs +=================== + +B_U585I_IOT02A Discovery kit has 9 GPIO controllers (from A to I). These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `B U585I IOT02A board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) +- LD1 : PH7 +- LD2 : PH6 +- user button : PC13 +- SPI1 NSS/SCK/MISO/MOSI : PE12/P13/P14/P15 (Arduino SPI) +- I2C_1 SDA/SDL : PB9/PB8 (Arduino I2C) +- I2C_2 SDA/SDL : PH5/PH4 +- DAC1 CH1 : PA4 (STMOD+1) +- ADC1_IN15 : PB0 +- USB OTG : PA11/PA12 +- PWM4 : CN14 PB6 +- PWM3 : CN4 PE4 + +System Clock +------------ + +B_U585I_IOT02A Discovery System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +B_U585I_IOT02A Discovery kit has 4 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB6`` jumper on the back side of the board. + + +Programming and Debugging +************************* + +B_U585I_IOT02A Discovery kit includes an ST-LINK/V3 embedded debug tool interface. +This probe allows to flash the board using various tools. + + +Flashing +======== + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board. + +Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be +used to flash and debug the board if west is told to use it as runner, +using ``-r openocd``. + +Connect the B_U585I_IOT02A Discovery kit to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_u585i_iot02a + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +Default flasher for this board is openocd. It could be used in the usual way. +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: b_u585i_iot02a + :goals: debug + +Building a secure/non-secure with Arm |reg| TrustZone |reg| +=========================================================== + +The TF-M applications can be run on this board, thanks to its Arm |reg| TrustZone |reg| +support. +In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image +can be generated using ``b_u585i_iot02a/stm32u585xx/ns`` as build target. + +.. code-block:: bash + + $ west build -b b_u585i_iot02a/stm32u585xx/ns path/to/source/directory + +Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script +is run automatically in a post-build step to make some required flash layout changes. + +Once the build is completed, run the following script to initialize the option bytes. + +.. code-block:: bash + + $ build/tfm/api_ns/regression.sh + +Finally, to flash the board, run: + +.. code-block:: bash + + $ west flash + + +Disabling TrustZone |reg| on the board +====================================== + +If you have flashed a sample to the board that enables TrustZone, you will need +to disable it before you can flash and run a new non-TrustZone sample on the +board. + +To disable TrustZone, it's necessary to change AT THE SAME TIME the ``TZEN`` +and ``RDP`` bits. ``TZEN`` needs to get set from 1 to 0 and ``RDP``, +needs to be set from ``DC`` to ``AA`` (step 3 below). + +This is docummented in the `AN5347, in section 9`_, "TrustZone deactivation". + +However, it's possible that the ``RDP`` bit is not yet set to ``DC``, so you +first need to set it to ``DC`` (step 2). + +Finally you need to set the "Write Protection 1 & 2" bytes properly, otherwise +some memory regions won't be erasable and mass erase will fail (step 4). + +The following command sequence will fully deactivate TZ: + +Step 1: + +Ensure U23 BOOT0 switch is set to 1 (switch is on the left, assuming you read +"BOOT0" silkscreen label from left to right). You need to press "Reset" (B2 RST +switch) after changing the switch to make the change effective. + +Step 2: + +.. code-block:: console + + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob rdp=0xDC + +Step 3: + +.. code-block:: console + + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -tzenreg + +Step 4: + +.. code-block:: console + + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1a_pstrt=0x7f + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1a_pend=0x0 + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1b_pstrt=0x7f + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1b_pend=0x0 + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2a_pstrt=0x7f + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2a_pend=0x0 + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2b_pstrt=0x7f + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2b_pend=0x0 + + +.. _B U585I IOT02A Discovery kit website: + https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html + +.. _B U585I IOT02A board User Manual: + https://www.st.com/resource/en/user_manual/um2839-discovery-kit-for-iot-node-with-stm32u5-series-stmicroelectronics.pdf + +.. _STM32U585 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html + +.. _STM32U585 reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STMicroelectronics customized version of OpenOCD: + https://github.com/STMicroelectronics/OpenOCD + +.. _AN5347, in section 9: + https://www.st.com/resource/en/application_note/dm00625692-stm32l5-series-trustzone-features-stmicroelectronics.pdf diff --git a/boards/arm/b_u585i_iot02a/pre_dt_board.cmake b/boards/st/b_u585i_iot02a/pre_dt_board.cmake similarity index 100% rename from boards/arm/b_u585i_iot02a/pre_dt_board.cmake rename to boards/st/b_u585i_iot02a/pre_dt_board.cmake diff --git a/boards/arm/b_u585i_iot02a/support/openocd.cfg b/boards/st/b_u585i_iot02a/support/openocd.cfg similarity index 100% rename from boards/arm/b_u585i_iot02a/support/openocd.cfg rename to boards/st/b_u585i_iot02a/support/openocd.cfg diff --git a/boards/st/disco_l475_iot1/Kconfig.defconfig b/boards/st/disco_l475_iot1/Kconfig.defconfig new file mode 100644 index 00000000000..5679d2caff8 --- /dev/null +++ b/boards/st/disco_l475_iot1/Kconfig.defconfig @@ -0,0 +1,44 @@ +# Discovery IoT L475 board configuration + +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_DISCO_L475_IOT1 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +choice LIS3MDL_TRIGGER_MODE + default LIS3MDL_TRIGGER_NONE +endchoice + +choice HTS221_TRIGGER_MODE + default HTS221_TRIGGER_NONE +endchoice + +choice LSM6DSL_TRIGGER_MODE + default LSM6DSL_TRIGGER_GLOBAL_THREAD + depends on LSM6DSL +endchoice + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +config BT_BLUENRG_ACI + default y +# Disable Flow control +config BT_HCI_ACL_FLOW_CONTROL + default n +config BT_HCI_VS_EXT + default n + +endif # BT + +endif # BOARD_DISCO_L475_IOT1 diff --git a/boards/st/disco_l475_iot1/Kconfig.disco_l475_iot1 b/boards/st/disco_l475_iot1/Kconfig.disco_l475_iot1 new file mode 100644 index 00000000000..ee535239188 --- /dev/null +++ b/boards/st/disco_l475_iot1/Kconfig.disco_l475_iot1 @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DISCO_L475_IOT1 + select SOC_STM32L475XX diff --git a/boards/arm/disco_l475_iot1/arduino_r3_connector.dtsi b/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/disco_l475_iot1/arduino_r3_connector.dtsi rename to boards/st/disco_l475_iot1/arduino_r3_connector.dtsi diff --git a/boards/arm/disco_l475_iot1/board.cmake b/boards/st/disco_l475_iot1/board.cmake similarity index 100% rename from boards/arm/disco_l475_iot1/board.cmake rename to boards/st/disco_l475_iot1/board.cmake diff --git a/boards/st/disco_l475_iot1/board.yml b/boards/st/disco_l475_iot1/board.yml new file mode 100644 index 00000000000..c11f22591a5 --- /dev/null +++ b/boards/st/disco_l475_iot1/board.yml @@ -0,0 +1,5 @@ +board: + name: disco_l475_iot1 + vendor: st + socs: + - name: stm32l475xx diff --git a/boards/arm/disco_l475_iot1/disco_l475_iot1.dts b/boards/st/disco_l475_iot1/disco_l475_iot1.dts similarity index 100% rename from boards/arm/disco_l475_iot1/disco_l475_iot1.dts rename to boards/st/disco_l475_iot1/disco_l475_iot1.dts diff --git a/boards/arm/disco_l475_iot1/disco_l475_iot1.yaml b/boards/st/disco_l475_iot1/disco_l475_iot1.yaml similarity index 100% rename from boards/arm/disco_l475_iot1/disco_l475_iot1.yaml rename to boards/st/disco_l475_iot1/disco_l475_iot1.yaml diff --git a/boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig b/boards/st/disco_l475_iot1/disco_l475_iot1_defconfig similarity index 80% rename from boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig rename to boards/st/disco_l475_iot1/disco_l475_iot1_defconfig index a25b1eff645..2ff706148f2 100644 --- a/boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig +++ b/boards/st/disco_l475_iot1/disco_l475_iot1_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_BOARD_DISCO_L475_IOT1=y -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L475XX=y - # enable uart driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/disco_l475_iot1/doc/img/disco_l475_iot1.jpg b/boards/st/disco_l475_iot1/doc/img/disco_l475_iot1.jpg similarity index 100% rename from boards/arm/disco_l475_iot1/doc/img/disco_l475_iot1.jpg rename to boards/st/disco_l475_iot1/doc/img/disco_l475_iot1.jpg diff --git a/boards/st/disco_l475_iot1/doc/index.rst b/boards/st/disco_l475_iot1/doc/index.rst new file mode 100644 index 00000000000..dc49d4fcb2d --- /dev/null +++ b/boards/st/disco_l475_iot1/doc/index.rst @@ -0,0 +1,248 @@ +.. _disco_l475_iot1_board: + +ST Disco L475 IOT01 (B-L475E-IOT01A) +#################################### + +Overview +******** + +The B-L475E-IOT01A Discovery kit for IoT node allows users to develop +applications with direct connection to cloud servers. +The Discovery kit enables a wide diversity of applications by exploiting +low-power communication, multiway sensing and ARM |reg| Cortex |reg|-M4 core-based +STM32L4 Series features. + +This kit provides: + +- 64-Mbit Quad-SPI (Macronix) Flash memory +- Bluetooth |reg| V4.1 module (SPBTLE-RF) +- Sub-GHz (868 or 915 MHz) low-power-programmable RF module (SPSGRF-868 or SPSGRF-915) +- Wi-Fi |reg| module Inventek ISM43362-M3G-L44 (802.11 b/g/n compliant) +- Dynamic NFC tag based on M24SR with its printed NFC antenna +- 2 digital omni-directional microphones (MP34DT01) +- Capacitive digital sensor for relative humidity and temperature (HTS221) +- High-performance 3-axis magnetometer (LIS3MDL) +- 3D accelerometer and 3D gyroscope (LSM6DSL) +- 260-1260 hPa absolute digital output barometer (LPS22HB) +- Time-of-Flight and gesture-detection sensor (VL53L0X) +- 2 push-buttons (user and reset) +- USB OTG FS with Micro-AB connector +- Expansion connectors: + - Arduino |trade| Uno V3 + - PMOD +- Flexible power-supply options: + - ST LINK USB VBUS or external sources +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: + - mass storage, virtual COM port and debug port + + +.. image:: img/disco_l475_iot1.jpg + :align: center + :alt: Disco L475 IoT1 + +More information about the board can be found at the `Disco L475 IoT1 website`_. + +Hardware +******** + +The STM32L475VG SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 120 nA Standby mode and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 128 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators +- 18x communication interfaces + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L475VG can be found here: + - `STM32L475VG on www.st.com`_ + - `STM32L475 reference manual`_ + +Supported Features +================== + +The Zephyr Disco L475 IoT board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/st/disco_l475_iot1/disco_l475_iot1_defconfig` + + +Connections and IOs +=================== + +Disco L475 IoT Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- + +For detailed information about available pins please refer to `STM32 Disco L475 IoT1 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 (ST-Link Virtual Port Com) +- UART_4 TX/RX : PA0/PA1 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PB10/PB11 (Sensor I2C bus) +- I2C3 SCL/SDA : PC0/PC1 +- SPI1 NSS/SCK/MISO/MOSI : PA2/PA5/PA6/PA7 (Arduino SPI) +- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (BT SPI bus) +- PWM_2_CH1 : PA15 +- USER_PB : PC13 +- LD2 : PA5 +- ADC12_IN5 : PA0 +- ADC123_IN3 : PC2 +- ADC123_IN4 : PC3 +- ADC12_IN13 : PC4 +- ADC12_IN14 : PC5 +- DAC1_OUT1 : PA4 + +System Clock +------------ + +Disco L475 IoT System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Disco L475 IoT board has 6 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``disco_l475_iot1`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Disco L475 IoT board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Disco L475 IoT +----------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Connect the Disco L475 IoT to your host computer using the USB port, then +run a serial host program to connect with your Nucleo board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: disco_l475_iot1 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: disco_l475_iot1 + :maybe-skip-config: + :goals: debug + +.. _Disco L475 IoT1 website: + https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-discovery-kits/b-l475e-iot01a.html + +.. _STM32 Disco L475 IoT1 board User Manual: + https://www.st.com/resource/en/user_manual/dm00347848.pdf + +.. _STM32L475VG on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l475vg.html + +.. _STM32L475 reference manual: + https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/disco_l475_iot1/support/openocd.cfg b/boards/st/disco_l475_iot1/support/openocd.cfg similarity index 100% rename from boards/arm/disco_l475_iot1/support/openocd.cfg rename to boards/st/disco_l475_iot1/support/openocd.cfg diff --git a/boards/st/index.rst b/boards/st/index.rst new file mode 100644 index 00000000000..3cc804c72a8 --- /dev/null +++ b/boards/st/index.rst @@ -0,0 +1,10 @@ +.. _boards-st: + +STMicroelectronics +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/st/nucleo_c031c6/Kconfig.nucleo_c031c6 b/boards/st/nucleo_c031c6/Kconfig.nucleo_c031c6 new file mode 100644 index 00000000000..839f9916405 --- /dev/null +++ b/boards/st/nucleo_c031c6/Kconfig.nucleo_c031c6 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Benjamin Björnsson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_C031C6 + select SOC_STM32C031XX diff --git a/boards/arm/nucleo_c031c6/arduino_r3_connector.dtsi b/boards/st/nucleo_c031c6/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_c031c6/arduino_r3_connector.dtsi rename to boards/st/nucleo_c031c6/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_c031c6/board.cmake b/boards/st/nucleo_c031c6/board.cmake similarity index 100% rename from boards/arm/nucleo_c031c6/board.cmake rename to boards/st/nucleo_c031c6/board.cmake diff --git a/boards/st/nucleo_c031c6/board.yml b/boards/st/nucleo_c031c6/board.yml new file mode 100644 index 00000000000..37d48de4d52 --- /dev/null +++ b/boards/st/nucleo_c031c6/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_c031c6 + vendor: st + socs: + - name: stm32c031xx diff --git a/boards/arm/nucleo_c031c6/doc/img/nucleo_c031c6.jpg b/boards/st/nucleo_c031c6/doc/img/nucleo_c031c6.jpg similarity index 100% rename from boards/arm/nucleo_c031c6/doc/img/nucleo_c031c6.jpg rename to boards/st/nucleo_c031c6/doc/img/nucleo_c031c6.jpg diff --git a/boards/st/nucleo_c031c6/doc/index.rst b/boards/st/nucleo_c031c6/doc/index.rst new file mode 100644 index 00000000000..8ed5a7edfea --- /dev/null +++ b/boards/st/nucleo_c031c6/doc/index.rst @@ -0,0 +1,151 @@ +.. _nucleo_c031c6_board: + +ST Nucleo C031C6 +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32C031C6 MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_c031c6.jpg + :align: center + :alt: Nucleo C031C6 + +More information about the board can be found at the `Nucleo C031C6 website`_. + +Hardware +******** +Nucleo C031C6 provides the following hardware components: + +- STM32 microcontroller in 48-pin package featuring 32 Kbytes of Flash memory + and 12 Kbytes of SRAM. +- Extension resource: + + - Arduino* Uno V3 connectivity + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Current consumption measurement (IDD) + +- Four LEDs: + + - USB communication (LD1), USB power fault LED (LD2), power LED (LD3), + user LED (LD4) + +- Two push-button: USER and RESET + +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +More information about STM32C031C6 can be found here: +`STM32C0x1 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_c031c6 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| IWDG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| WWDG | on-chip | window watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_c031c6/nucleo_c031c6_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- LD4 : PA5 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_c031c6`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo C031C6 board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo C031C6 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_c031c6 + :goals: build flash + +You will see the LED blinking every second. + +References +********** + +.. target-notes:: + +.. _Nucleo C031C6 website: + https://www.st.com/en/evaluation-tools/nucleo-c031c6.html + +.. _STM32C0x1 reference manual: + https://www.st.com/resource/en/reference_manual/rm0490-stm32c0x1-advanced-armbased-64bit-mcus-stmicroelectronics.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/um2953-stm32c0-nucleo64-board-mb1717-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_c031c6/nucleo_c031c6.dts b/boards/st/nucleo_c031c6/nucleo_c031c6.dts similarity index 100% rename from boards/arm/nucleo_c031c6/nucleo_c031c6.dts rename to boards/st/nucleo_c031c6/nucleo_c031c6.dts diff --git a/boards/arm/nucleo_c031c6/nucleo_c031c6.yaml b/boards/st/nucleo_c031c6/nucleo_c031c6.yaml similarity index 100% rename from boards/arm/nucleo_c031c6/nucleo_c031c6.yaml rename to boards/st/nucleo_c031c6/nucleo_c031c6.yaml diff --git a/boards/st/nucleo_c031c6/nucleo_c031c6_defconfig b/boards/st/nucleo_c031c6/nucleo_c031c6_defconfig new file mode 100644 index 00000000000..1a570d28d13 --- /dev/null +++ b/boards/st/nucleo_c031c6/nucleo_c031c6_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f030r8/Kconfig.nucleo_f030r8 b/boards/st/nucleo_f030r8/Kconfig.nucleo_f030r8 new file mode 100644 index 00000000000..039a9e00c6c --- /dev/null +++ b/boards/st/nucleo_f030r8/Kconfig.nucleo_f030r8 @@ -0,0 +1,5 @@ +# Copyright (c) 2017 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F030R8 + select SOC_STM32F030X8 diff --git a/boards/arm/nucleo_f030r8/arduino_r3_connector.dtsi b/boards/st/nucleo_f030r8/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f030r8/arduino_r3_connector.dtsi rename to boards/st/nucleo_f030r8/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f030r8/board.cmake b/boards/st/nucleo_f030r8/board.cmake similarity index 100% rename from boards/arm/nucleo_f030r8/board.cmake rename to boards/st/nucleo_f030r8/board.cmake diff --git a/boards/st/nucleo_f030r8/board.yml b/boards/st/nucleo_f030r8/board.yml new file mode 100644 index 00000000000..515aae8c5b0 --- /dev/null +++ b/boards/st/nucleo_f030r8/board.yml @@ -0,0 +1,11 @@ +board: + name: nucleo_f030r8 + vendor: st + revision: + format: number + default: "1" + revisions: + - name: "1" + - name: "2" + socs: + - name: stm32f030x8 diff --git a/boards/arm/nucleo_f030r8/doc/img/nucleo_f030r8.jpg b/boards/st/nucleo_f030r8/doc/img/nucleo_f030r8.jpg similarity index 100% rename from boards/arm/nucleo_f030r8/doc/img/nucleo_f030r8.jpg rename to boards/st/nucleo_f030r8/doc/img/nucleo_f030r8.jpg diff --git a/boards/arm/nucleo_f030r8/doc/img/nucleo_f030r8_connectors.jpg b/boards/st/nucleo_f030r8/doc/img/nucleo_f030r8_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f030r8/doc/img/nucleo_f030r8_connectors.jpg rename to boards/st/nucleo_f030r8/doc/img/nucleo_f030r8_connectors.jpg diff --git a/boards/st/nucleo_f030r8/doc/index.rst b/boards/st/nucleo_f030r8/doc/index.rst new file mode 100644 index 00000000000..a7479859d09 --- /dev/null +++ b/boards/st/nucleo_f030r8/doc/index.rst @@ -0,0 +1,217 @@ +.. _nucleo_f030r8_board: + +ST Nucleo F030R8 +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32F030R8 MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f030r8.jpg + :align: center + :alt: Nucleo F030R8 + +More information about the board can be found at the `Nucleo F030R8 website`_. + +Hardware +******** +Nucleo F030R8 provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32F030R8 can be found here: + +- `STM32F030 reference manual`_ +- `STM32F030 data sheet`_ + +Supported Features +================== + +The Zephyr nucleo_f030r8 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f030r8/nucleo_f030r8_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_f030r8_connectors.jpg + :align: center + :alt: Nucleo F030R8 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PB10/PB11 +- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- USER_PB : PC13 +- LD1 : PA5 +- ADC : PA0 + + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f030r8`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. _nucleo-f030r8-flashing: + +Flashing +======== + +Nucleo F030R8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F030R8 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f030r8 + :goals: build flash + +You will see the LED blinking every second. + +If using the C-01 board, select revision '1' that supports the board. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f030r8@1 + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f030r8 + :maybe-skip-config: + :goals: debug + +Again you have to use the adapted command for C-01. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f030r8@1 + :maybe-skip-config: + :goals: debug + +Board Revisions +*************** + +Nucleo F030R8 has some version of board variants. +`STM32 Nucleo-64 board User Manual`_ mentions to Nucleo board variants. + + | *The board version MB1136 C-01 or MB1136 C-02 is mentioned on the sticker, placed on the bottom side of the PCB.* + | *The board marking MB1136 C-01 corresponds to a board, configured as HSE not used.* + | *The board marking MB1136 C-02 (or higher) corresponds to a board, configured to use ST-LINK MCO as the clock input.* + +Using revision **2** adapted for C-02(or higher) as default when not explicitly selecting revisions. +If using the C-01 board, select revision **1**. +Please see :ref:`Flashing ` section. + +References +********** + +.. target-notes:: + +.. _Nucleo F030R8 website: + https://www.st.com/en/evaluation-tools/nucleo-f030r8.html + +.. _STM32F030 reference manual: + https://www.st.com/resource/en/reference_manual/dm00091010.pdf + +.. _STM32F030 data sheet: + https://www.st.com/resource/en/datasheet/stm32f030r8.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8.dts b/boards/st/nucleo_f030r8/nucleo_f030r8.dts similarity index 100% rename from boards/arm/nucleo_f030r8/nucleo_f030r8.dts rename to boards/st/nucleo_f030r8/nucleo_f030r8.dts diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8.yaml b/boards/st/nucleo_f030r8/nucleo_f030r8_1.yaml similarity index 100% rename from boards/arm/nucleo_f030r8/nucleo_f030r8.yaml rename to boards/st/nucleo_f030r8/nucleo_f030r8_1.yaml diff --git a/boards/st/nucleo_f030r8/nucleo_f030r8_2.yaml b/boards/st/nucleo_f030r8/nucleo_f030r8_2.yaml new file mode 100644 index 00000000000..194e1b45199 --- /dev/null +++ b/boards/st/nucleo_f030r8/nucleo_f030r8_2.yaml @@ -0,0 +1,24 @@ +identifier: nucleo_f030r8@2 +name: ST Nucleo F030R8 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 8 +flash: 64 +supported: + - arduino_gpio + - arduino_i2c + - arduino_spi + - i2c + - spi + - gpio + - watchdog + - adc +testing: + ignore_tags: + - net + - bluetooth +vendor: st diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8_defconfig b/boards/st/nucleo_f030r8/nucleo_f030r8_defconfig similarity index 80% rename from boards/arm/nucleo_f030r8/nucleo_f030r8_defconfig rename to boards/st/nucleo_f030r8/nucleo_f030r8_defconfig index 1ba94fff95d..18ac599df25 100644 --- a/boards/arm/nucleo_f030r8/nucleo_f030r8_defconfig +++ b/boards/st/nucleo_f030r8/nucleo_f030r8_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F030X8=y - # Kernel Options due to Low Memory (8k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8_1.overlay b/boards/st/nucleo_f030r8/nucleo_f030r8_stm32f030x8_1.overlay similarity index 100% rename from boards/arm/nucleo_f030r8/nucleo_f030r8_1.overlay rename to boards/st/nucleo_f030r8/nucleo_f030r8_stm32f030x8_1.overlay diff --git a/boards/arm/nucleo_f030r8/st_morpho_connector.dtsi b/boards/st/nucleo_f030r8/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f030r8/st_morpho_connector.dtsi rename to boards/st/nucleo_f030r8/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f030r8/support/openocd.cfg b/boards/st/nucleo_f030r8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f030r8/support/openocd.cfg rename to boards/st/nucleo_f030r8/support/openocd.cfg diff --git a/boards/st/nucleo_f031k6/Kconfig.nucleo_f031k6 b/boards/st/nucleo_f031k6/Kconfig.nucleo_f031k6 new file mode 100644 index 00000000000..2e1f222fb0e --- /dev/null +++ b/boards/st/nucleo_f031k6/Kconfig.nucleo_f031k6 @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Sebastian Schwabe +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F031K6 + select SOC_STM32F031X6 diff --git a/boards/arm/nucleo_f031k6/board.cmake b/boards/st/nucleo_f031k6/board.cmake similarity index 100% rename from boards/arm/nucleo_f031k6/board.cmake rename to boards/st/nucleo_f031k6/board.cmake diff --git a/boards/st/nucleo_f031k6/board.yml b/boards/st/nucleo_f031k6/board.yml new file mode 100644 index 00000000000..01fc79ac033 --- /dev/null +++ b/boards/st/nucleo_f031k6/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f031k6 + vendor: st + socs: + - name: stm32f031x6 diff --git a/boards/arm/nucleo_f031k6/doc/img/nucleo_f031k6.jpg b/boards/st/nucleo_f031k6/doc/img/nucleo_f031k6.jpg similarity index 100% rename from boards/arm/nucleo_f031k6/doc/img/nucleo_f031k6.jpg rename to boards/st/nucleo_f031k6/doc/img/nucleo_f031k6.jpg diff --git a/boards/arm/nucleo_f031k6/doc/img/nucleo_f031k6_connectors.jpg b/boards/st/nucleo_f031k6/doc/img/nucleo_f031k6_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f031k6/doc/img/nucleo_f031k6_connectors.jpg rename to boards/st/nucleo_f031k6/doc/img/nucleo_f031k6_connectors.jpg diff --git a/boards/st/nucleo_f031k6/doc/index.rst b/boards/st/nucleo_f031k6/doc/index.rst new file mode 100644 index 00000000000..99ae997ce26 --- /dev/null +++ b/boards/st/nucleo_f031k6/doc/index.rst @@ -0,0 +1,155 @@ +.. _nucleo_f031k6_board: + +ST Nucleo F031K6 +################ + +Overview +******** +The STM32 Nucleo-32 development board with STM32F031K6 MCU, supports Arduino nano connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f031k6.jpg + :align: center + :alt: Nucleo F031k6 + +More information about the board can be found at the `Nucleo F031K6 website`_. + +Hardware +******** +Nucleo F031K6 provides the following hardware components: + +- STM32 microcontroller in LQFP32 package + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- reset push button + +More information about STM32F031K6 can be found here: + +- `STM32F031 reference manual`_ +- `STM32F031 data sheet`_ + +Supported Features +================== + +The Zephyr nucleo_f031k6 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f031k6/nucleo_f031k6_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. + +Board connectors: +----------------- +.. image:: img/nucleo_f031k6_connectors.jpg + :align: center + :alt: Nucleo F031K6 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA2/PA15 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB6/PB7 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) +- LD2 : PB3 + + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f031k6`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F030R8 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f031k6 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f031k6 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F031K6 website: + https://www.st.com/en/evaluation-tools/nucleo-f031k6.html + +.. _STM32F031 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32F031 data sheet: + https://www.st.com/resource/en/datasheet/stm32f031k6.pdf + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_f031k6/nucleo_f031k6.dts b/boards/st/nucleo_f031k6/nucleo_f031k6.dts similarity index 100% rename from boards/arm/nucleo_f031k6/nucleo_f031k6.dts rename to boards/st/nucleo_f031k6/nucleo_f031k6.dts diff --git a/boards/arm/nucleo_f031k6/nucleo_f031k6.yaml b/boards/st/nucleo_f031k6/nucleo_f031k6.yaml similarity index 100% rename from boards/arm/nucleo_f031k6/nucleo_f031k6.yaml rename to boards/st/nucleo_f031k6/nucleo_f031k6.yaml diff --git a/boards/arm/nucleo_f031k6/nucleo_f031k6_defconfig b/boards/st/nucleo_f031k6/nucleo_f031k6_defconfig similarity index 86% rename from boards/arm/nucleo_f031k6/nucleo_f031k6_defconfig rename to boards/st/nucleo_f031k6/nucleo_f031k6_defconfig index 87cb9a81148..62817c1ba47 100644 --- a/boards/arm/nucleo_f031k6/nucleo_f031k6_defconfig +++ b/boards/st/nucleo_f031k6/nucleo_f031k6_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Platform Configuration -CONFIG_SOC_SERIES_STM32F0X=y -CONFIG_SOC_STM32F031X6=y # Kernel Options due to Low Memory (4k) CONFIG_MAIN_STACK_SIZE=512 diff --git a/boards/arm/nucleo_f031k6/support/openocd.cfg b/boards/st/nucleo_f031k6/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f031k6/support/openocd.cfg rename to boards/st/nucleo_f031k6/support/openocd.cfg diff --git a/boards/st/nucleo_f042k6/Kconfig.nucleo_f042k6 b/boards/st/nucleo_f042k6/Kconfig.nucleo_f042k6 new file mode 100644 index 00000000000..ed5b7b1c303 --- /dev/null +++ b/boards/st/nucleo_f042k6/Kconfig.nucleo_f042k6 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F042K6 + select SOC_STM32F042X6 diff --git a/boards/arm/nucleo_f042k6/board.cmake b/boards/st/nucleo_f042k6/board.cmake similarity index 100% rename from boards/arm/nucleo_f042k6/board.cmake rename to boards/st/nucleo_f042k6/board.cmake diff --git a/boards/st/nucleo_f042k6/board.yml b/boards/st/nucleo_f042k6/board.yml new file mode 100644 index 00000000000..89d8b050428 --- /dev/null +++ b/boards/st/nucleo_f042k6/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f042k6 + vendor: st + socs: + - name: stm32f042x6 diff --git a/boards/arm/nucleo_f042k6/doc/img/nucleo_f042k6.jpg b/boards/st/nucleo_f042k6/doc/img/nucleo_f042k6.jpg similarity index 100% rename from boards/arm/nucleo_f042k6/doc/img/nucleo_f042k6.jpg rename to boards/st/nucleo_f042k6/doc/img/nucleo_f042k6.jpg diff --git a/boards/arm/nucleo_f042k6/doc/img/nucleo_f042k6_connectors.jpg b/boards/st/nucleo_f042k6/doc/img/nucleo_f042k6_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f042k6/doc/img/nucleo_f042k6_connectors.jpg rename to boards/st/nucleo_f042k6/doc/img/nucleo_f042k6_connectors.jpg diff --git a/boards/st/nucleo_f042k6/doc/index.rst b/boards/st/nucleo_f042k6/doc/index.rst new file mode 100644 index 00000000000..a1d90c8c4f3 --- /dev/null +++ b/boards/st/nucleo_f042k6/doc/index.rst @@ -0,0 +1,155 @@ +.. _nucleo_f042k6_board: + +ST Nucleo F042K6 +################ + +Overview +******** +The STM32 Nucleo-32 development board with STM32F042K6 MCU, supports Arduino nano connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f042k6.jpg + :align: center + :alt: Nucleo F042k6 + +More information about the board can be found at the `Nucleo F042K6 website`_. + +Hardware +******** +Nucleo F042K6 provides the following hardware components: + +- STM32 microcontroller in LQFP32 package + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- reset push button + +More information about STM32F042K6 can be found here: + +- `STM32F042 reference manual`_ +- `STM32F042 data sheet`_ + +Supported Features +================== + +The Zephyr nucleo_f042k6 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f042k6/nucleo_f042k6_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. + +Board connectors: +----------------- +.. image:: img/nucleo_f042k6_connectors.jpg + :align: center + :alt: Nucleo F042K6 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA2/PA15 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB6/PB7 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) +- LD2 : PB3 + + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f042k6`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F042K6 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F042K6 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f042k6 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f042k6 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F042K6 website: + https://www.st.com/en/evaluation-tools/nucleo-f042k6.html + +.. _STM32F042 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32F042 data sheet: + https://www.st.com/resource/en/datasheet/stm32f042k6.pdf + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_f042k6/nucleo_f042k6.dts b/boards/st/nucleo_f042k6/nucleo_f042k6.dts similarity index 100% rename from boards/arm/nucleo_f042k6/nucleo_f042k6.dts rename to boards/st/nucleo_f042k6/nucleo_f042k6.dts diff --git a/boards/arm/nucleo_f042k6/nucleo_f042k6.yaml b/boards/st/nucleo_f042k6/nucleo_f042k6.yaml similarity index 100% rename from boards/arm/nucleo_f042k6/nucleo_f042k6.yaml rename to boards/st/nucleo_f042k6/nucleo_f042k6.yaml diff --git a/boards/st/nucleo_f042k6/nucleo_f042k6_defconfig b/boards/st/nucleo_f042k6/nucleo_f042k6_defconfig new file mode 100644 index 00000000000..06e8a32bb1f --- /dev/null +++ b/boards/st/nucleo_f042k6/nucleo_f042k6_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f042k6/support/openocd.cfg b/boards/st/nucleo_f042k6/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f042k6/support/openocd.cfg rename to boards/st/nucleo_f042k6/support/openocd.cfg diff --git a/boards/st/nucleo_f070rb/Kconfig.defconfig b/boards/st/nucleo_f070rb/Kconfig.defconfig new file mode 100644 index 00000000000..49649c776a9 --- /dev/null +++ b/boards/st/nucleo_f070rb/Kconfig.defconfig @@ -0,0 +1,12 @@ +# NUCLEO_F070RB board configuration + +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F070RB + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F070RB diff --git a/boards/st/nucleo_f070rb/Kconfig.nucleo_f070rb b/boards/st/nucleo_f070rb/Kconfig.nucleo_f070rb new file mode 100644 index 00000000000..0ebe4a837ba --- /dev/null +++ b/boards/st/nucleo_f070rb/Kconfig.nucleo_f070rb @@ -0,0 +1,5 @@ +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F070RB + select SOC_STM32F070XB diff --git a/boards/arm/nucleo_f070rb/arduino_r3_connector.dtsi b/boards/st/nucleo_f070rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f070rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_f070rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f070rb/board.cmake b/boards/st/nucleo_f070rb/board.cmake similarity index 100% rename from boards/arm/nucleo_f070rb/board.cmake rename to boards/st/nucleo_f070rb/board.cmake diff --git a/boards/st/nucleo_f070rb/board.yml b/boards/st/nucleo_f070rb/board.yml new file mode 100644 index 00000000000..8f3a6a49878 --- /dev/null +++ b/boards/st/nucleo_f070rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f070rb + vendor: st + socs: + - name: stm32f070xb diff --git a/boards/arm/nucleo_f070rb/doc/img/nucleo_f070rb.jpg b/boards/st/nucleo_f070rb/doc/img/nucleo_f070rb.jpg similarity index 100% rename from boards/arm/nucleo_f070rb/doc/img/nucleo_f070rb.jpg rename to boards/st/nucleo_f070rb/doc/img/nucleo_f070rb.jpg diff --git a/boards/arm/nucleo_f070rb/doc/img/nucleo_f070rb_connectors.jpg b/boards/st/nucleo_f070rb/doc/img/nucleo_f070rb_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f070rb/doc/img/nucleo_f070rb_connectors.jpg rename to boards/st/nucleo_f070rb/doc/img/nucleo_f070rb_connectors.jpg diff --git a/boards/st/nucleo_f070rb/doc/index.rst b/boards/st/nucleo_f070rb/doc/index.rst new file mode 100644 index 00000000000..5e6544e9cfb --- /dev/null +++ b/boards/st/nucleo_f070rb/doc/index.rst @@ -0,0 +1,180 @@ +.. _nucleo_f070rb_board: + +ST Nucleo F070RB +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32F070RB MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f070rb.jpg + :align: center + :alt: Nucleo F070RB + +More information about the board can be found at the `Nucleo F070RB website`_. + +Hardware +******** +Nucleo F070RB provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32F070RB can be found in +the `STM32F070 reference manual`_ . + + +Supported Features +================== + +The Zephyr nucleo_f070rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | SPI controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f070rb/nucleo_f070rb_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_f070rb_connectors.jpg + :align: center + :alt: Nucleo F070RB connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PB10/PB11 +- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 +- USER_PB : PC13 +- LD1 : PA5 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f070rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F070RB board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F070RB +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f070rb + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f070rb + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F070RB website: + https://www.st.com/en/evaluation-tools/nucleo-f070rb.html + +.. _STM32F070 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f070rb/nucleo_f070rb.dts b/boards/st/nucleo_f070rb/nucleo_f070rb.dts similarity index 100% rename from boards/arm/nucleo_f070rb/nucleo_f070rb.dts rename to boards/st/nucleo_f070rb/nucleo_f070rb.dts diff --git a/boards/arm/nucleo_f070rb/nucleo_f070rb.yaml b/boards/st/nucleo_f070rb/nucleo_f070rb.yaml similarity index 100% rename from boards/arm/nucleo_f070rb/nucleo_f070rb.yaml rename to boards/st/nucleo_f070rb/nucleo_f070rb.yaml diff --git a/boards/st/nucleo_f070rb/nucleo_f070rb_defconfig b/boards/st/nucleo_f070rb/nucleo_f070rb_defconfig new file mode 100644 index 00000000000..bee511a2809 --- /dev/null +++ b/boards/st/nucleo_f070rb/nucleo_f070rb_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f070rb/st_morpho_connector.dtsi b/boards/st/nucleo_f070rb/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f070rb/st_morpho_connector.dtsi rename to boards/st/nucleo_f070rb/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f070rb/support/openocd.cfg b/boards/st/nucleo_f070rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f070rb/support/openocd.cfg rename to boards/st/nucleo_f070rb/support/openocd.cfg diff --git a/boards/st/nucleo_f091rc/Kconfig.defconfig b/boards/st/nucleo_f091rc/Kconfig.defconfig new file mode 100644 index 00000000000..81a59cb529d --- /dev/null +++ b/boards/st/nucleo_f091rc/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-64 development board with STM32F091RC MCU + +# Copyright (c) 2017 Bobby Noelte +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F091RC + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F091RC diff --git a/boards/st/nucleo_f091rc/Kconfig.nucleo_f091rc b/boards/st/nucleo_f091rc/Kconfig.nucleo_f091rc new file mode 100644 index 00000000000..8bb34456d83 --- /dev/null +++ b/boards/st/nucleo_f091rc/Kconfig.nucleo_f091rc @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Bobby Noelte +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F091RC + select SOC_STM32F091XC diff --git a/boards/arm/nucleo_f091rc/arduino_r3_connector.dtsi b/boards/st/nucleo_f091rc/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f091rc/arduino_r3_connector.dtsi rename to boards/st/nucleo_f091rc/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f091rc/board.cmake b/boards/st/nucleo_f091rc/board.cmake similarity index 100% rename from boards/arm/nucleo_f091rc/board.cmake rename to boards/st/nucleo_f091rc/board.cmake diff --git a/boards/st/nucleo_f091rc/board.yml b/boards/st/nucleo_f091rc/board.yml new file mode 100644 index 00000000000..9f3fe67f8f6 --- /dev/null +++ b/boards/st/nucleo_f091rc/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f091rc + vendor: st + socs: + - name: stm32f091xc diff --git a/boards/arm/nucleo_f091rc/doc/img/nucleo_f091rc.jpg b/boards/st/nucleo_f091rc/doc/img/nucleo_f091rc.jpg similarity index 100% rename from boards/arm/nucleo_f091rc/doc/img/nucleo_f091rc.jpg rename to boards/st/nucleo_f091rc/doc/img/nucleo_f091rc.jpg diff --git a/boards/arm/nucleo_f091rc/doc/img/nucleo_f091rc_connectors.jpg b/boards/st/nucleo_f091rc/doc/img/nucleo_f091rc_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f091rc/doc/img/nucleo_f091rc_connectors.jpg rename to boards/st/nucleo_f091rc/doc/img/nucleo_f091rc_connectors.jpg diff --git a/boards/st/nucleo_f091rc/doc/index.rst b/boards/st/nucleo_f091rc/doc/index.rst new file mode 100644 index 00000000000..eee47f79254 --- /dev/null +++ b/boards/st/nucleo_f091rc/doc/index.rst @@ -0,0 +1,197 @@ +.. _nucleo_f091rc_board: + +ST Nucleo F091RC +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32F091RC MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f091rc.jpg + :align: center + :alt: Nucleo F091RC + +More information about the board can be found at the `Nucleo F091RC website`_. + +Hardware +******** +Nucleo F091RC provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32F091RC can be found in the +`STM32F091 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_f091rc board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | SPI controller | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC controller | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC controller | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f091rc/nucleo_f091rc_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_f091rc_connectors.jpg + :align: center + :alt: Nucleo F091RC connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PA11/PA12 (disabled by default, uses same pins as CAN) +- CAN RX/TX : PA11/PA12 +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) +- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 +- USER_PB : PC13 +- LD2 : PA5 +- DAC_OUT1 : PA4 +- PWM_2_CH1 : PA5 (might conflict with SPI1) + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f091rc`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F091RC board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F091RC +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f091rc + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f091rc + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F091RC website: + https://www.st.com/en/evaluation-tools/nucleo-f091rc.html + +.. _STM32F091 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f091rc/nucleo_f091rc.dts b/boards/st/nucleo_f091rc/nucleo_f091rc.dts similarity index 100% rename from boards/arm/nucleo_f091rc/nucleo_f091rc.dts rename to boards/st/nucleo_f091rc/nucleo_f091rc.dts diff --git a/boards/arm/nucleo_f091rc/nucleo_f091rc.yaml b/boards/st/nucleo_f091rc/nucleo_f091rc.yaml similarity index 100% rename from boards/arm/nucleo_f091rc/nucleo_f091rc.yaml rename to boards/st/nucleo_f091rc/nucleo_f091rc.yaml diff --git a/boards/st/nucleo_f091rc/nucleo_f091rc_defconfig b/boards/st/nucleo_f091rc/nucleo_f091rc_defconfig new file mode 100644 index 00000000000..06e8a32bb1f --- /dev/null +++ b/boards/st/nucleo_f091rc/nucleo_f091rc_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f091rc/st_morpho_connector.dtsi b/boards/st/nucleo_f091rc/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f091rc/st_morpho_connector.dtsi rename to boards/st/nucleo_f091rc/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f091rc/support/openocd.cfg b/boards/st/nucleo_f091rc/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f091rc/support/openocd.cfg rename to boards/st/nucleo_f091rc/support/openocd.cfg diff --git a/boards/st/nucleo_f103rb/Kconfig.nucleo_f103rb b/boards/st/nucleo_f103rb/Kconfig.nucleo_f103rb new file mode 100644 index 00000000000..08cdc321800 --- /dev/null +++ b/boards/st/nucleo_f103rb/Kconfig.nucleo_f103rb @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F103RB + select SOC_STM32F103XB diff --git a/boards/arm/nucleo_f103rb/arduino_r3_connector.dtsi b/boards/st/nucleo_f103rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f103rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_f103rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f103rb/board.cmake b/boards/st/nucleo_f103rb/board.cmake similarity index 100% rename from boards/arm/nucleo_f103rb/board.cmake rename to boards/st/nucleo_f103rb/board.cmake diff --git a/boards/st/nucleo_f103rb/board.yml b/boards/st/nucleo_f103rb/board.yml new file mode 100644 index 00000000000..57425f7832d --- /dev/null +++ b/boards/st/nucleo_f103rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f103rb + vendor: st + socs: + - name: stm32f103xb diff --git a/boards/arm/nucleo_f103rb/doc/img/nucleo_f103rb.jpg b/boards/st/nucleo_f103rb/doc/img/nucleo_f103rb.jpg similarity index 100% rename from boards/arm/nucleo_f103rb/doc/img/nucleo_f103rb.jpg rename to boards/st/nucleo_f103rb/doc/img/nucleo_f103rb.jpg diff --git a/boards/arm/nucleo_f103rb/doc/img/nucleo_f103rb_connectors.jpg b/boards/st/nucleo_f103rb/doc/img/nucleo_f103rb_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f103rb/doc/img/nucleo_f103rb_connectors.jpg rename to boards/st/nucleo_f103rb/doc/img/nucleo_f103rb_connectors.jpg diff --git a/boards/st/nucleo_f103rb/doc/index.rst b/boards/st/nucleo_f103rb/doc/index.rst new file mode 100644 index 00000000000..0ff1a60ef85 --- /dev/null +++ b/boards/st/nucleo_f103rb/doc/index.rst @@ -0,0 +1,190 @@ +.. _nucleo_f103rb_board: + +ST Nucleo F103RB +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32F103RB MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f103rb.jpg + :align: center + :alt: Nucleo F103RB + +More information about the board can be found at the `Nucleo F103RB website`_. + +Hardware +******** +Nucleo F103RB provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32F103RB can be found here: + +- `STM32F103 reference manual`_ +- `STM32F103 data sheet`_ + +Supported Features +================== + +The Zephyr nucleo_f103rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f103rb/nucleo_f103rb_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_f103rb_connectors.jpg + :align: center + :alt: Nucleo F103RB connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) +- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- SPI2 SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- I2C1 SDA/SCL: PB9/PB8 (Arduino I2C) +- PWM1_CH1: PA8 +- USER_PB : PC13 +- LD1 : PA5 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f103rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F103RB board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F103RB +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f103rb + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f103rb + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F103RB website: + https://www.st.com/en/evaluation-tools/nucleo-f103rb.html + +.. _STM32F103 reference manual: + https://www.st.com/resource/en/reference_manual/cd00171190.pdf + +.. _STM32F103 data sheet: + https://www.st.com/resource/en/datasheet/stm32f103rb.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f103rb/nucleo_f103rb.dts b/boards/st/nucleo_f103rb/nucleo_f103rb.dts similarity index 100% rename from boards/arm/nucleo_f103rb/nucleo_f103rb.dts rename to boards/st/nucleo_f103rb/nucleo_f103rb.dts diff --git a/boards/arm/nucleo_f103rb/nucleo_f103rb.yaml b/boards/st/nucleo_f103rb/nucleo_f103rb.yaml similarity index 100% rename from boards/arm/nucleo_f103rb/nucleo_f103rb.yaml rename to boards/st/nucleo_f103rb/nucleo_f103rb.yaml diff --git a/boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig b/boards/st/nucleo_f103rb/nucleo_f103rb_defconfig similarity index 81% rename from boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig rename to boards/st/nucleo_f103rb/nucleo_f103rb_defconfig index b3d7a802a88..d4828716f02 100644 --- a/boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig +++ b/boards/st/nucleo_f103rb/nucleo_f103rb_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103XB=y - # enable uart driver CONFIG_SERIAL=y # enable console diff --git a/boards/arm/nucleo_f103rb/st_morpho_connector.dtsi b/boards/st/nucleo_f103rb/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f103rb/st_morpho_connector.dtsi rename to boards/st/nucleo_f103rb/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f103rb/support/openocd.cfg b/boards/st/nucleo_f103rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f103rb/support/openocd.cfg rename to boards/st/nucleo_f103rb/support/openocd.cfg diff --git a/boards/st/nucleo_f207zg/Kconfig.defconfig b/boards/st/nucleo_f207zg/Kconfig.defconfig new file mode 100644 index 00000000000..c859796428d --- /dev/null +++ b/boards/st/nucleo_f207zg/Kconfig.defconfig @@ -0,0 +1,15 @@ +# NUCLEO-144 F207ZG board configuration + +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F207ZG + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F207ZG diff --git a/boards/st/nucleo_f207zg/Kconfig.nucleo_f207zg b/boards/st/nucleo_f207zg/Kconfig.nucleo_f207zg new file mode 100644 index 00000000000..08d270ad236 --- /dev/null +++ b/boards/st/nucleo_f207zg/Kconfig.nucleo_f207zg @@ -0,0 +1,5 @@ +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F207ZG + select SOC_STM32F207XX diff --git a/boards/arm/nucleo_f207zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f207zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f207zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_f207zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f207zg/board.cmake b/boards/st/nucleo_f207zg/board.cmake similarity index 100% rename from boards/arm/nucleo_f207zg/board.cmake rename to boards/st/nucleo_f207zg/board.cmake diff --git a/boards/st/nucleo_f207zg/board.yml b/boards/st/nucleo_f207zg/board.yml new file mode 100644 index 00000000000..8b35f4457cd --- /dev/null +++ b/boards/st/nucleo_f207zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f207zg + vendor: st + socs: + - name: stm32f207xx diff --git a/boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg.jpg b/boards/st/nucleo_f207zg/doc/img/nucleo_f207zg.jpg similarity index 100% rename from boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg.jpg rename to boards/st/nucleo_f207zg/doc/img/nucleo_f207zg.jpg diff --git a/boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_left.jpg b/boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_left.jpg similarity index 100% rename from boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_left.jpg rename to boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_left.jpg diff --git a/boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_right.jpg b/boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_right.jpg similarity index 100% rename from boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_right.jpg rename to boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_right.jpg diff --git a/boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_zio_left.jpg b/boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_zio_left.jpg similarity index 100% rename from boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_zio_left.jpg rename to boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_zio_left.jpg diff --git a/boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_zio_right.jpg b/boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_zio_right.jpg similarity index 100% rename from boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_zio_right.jpg rename to boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_zio_right.jpg diff --git a/boards/st/nucleo_f207zg/doc/index.rst b/boards/st/nucleo_f207zg/doc/index.rst new file mode 100644 index 00000000000..a801f0bc1e9 --- /dev/null +++ b/boards/st/nucleo_f207zg/doc/index.rst @@ -0,0 +1,206 @@ +.. _nucleo_f207zg_board: + +ST Nucleo F207ZG +################ + +Overview +******** + +The Nucleo F207ZG board features an ARM Cortex-M3 based STM32F207ZG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F207ZG board: + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 +- Two types of extension resources: + + - ST Zio connector including: support for Arduino* Uno V3 connectivity + (A0 to A5, D0 to D15) and additional signals exposing a wide range of + peripherals + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- Three user LEDs +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f207zg.jpg + :align: center + :alt: Nucleo F207ZG + +More information about the board can be found at the `Nucleo F207ZG website`_. + +Hardware +******** + +Nucleo F207ZG provides the following hardware components: + +- STM32F207ZGT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M3 CPU +- 120 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1 MB Flash +- 128 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 24 channels +- RTC +- 17 General purpose timers +- 2 watchdog timers (independent and window) +- SysTick timer +- USART/UART (6) +- I2C (3) +- SPI (3) +- SDIO +- USB 2.0 OTG FS +- DMA Controller +- 10/100 Ethernet MAC with dedicated DMA +- CRC calculation unit +- True random number generator + +More information about STM32F207ZG can be found here: + +- `STM32F207ZG on www.st.com`_ +- `STM32F207 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_207zg board configuration supports the following hardware features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| ETHERNET | on-chip | Ethernet | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-------------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-------------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | PWM | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | Random Number Generator | ++-------------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-------------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_f207zg/nucleo_f207zg_defconfig` + + +Connections and IOs +=================== + +Nucleo F207ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f207zg_zio_left.jpg + :align: center + :alt: Nucleo F207ZG ZIO connectors (left) +.. image:: img/nucleo_f207zg_zio_right.jpg + :align: center + :alt: Nucleo F207ZG ZIO connectors (right) +.. image:: img/nucleo_f207zg_morpho_left.jpg + :align: center + :alt: Nucleo F207ZG Morpho connectors (left) +.. image:: img/nucleo_f207zg_morpho_right.jpg + :align: center + :alt: Nucleo F207ZG Morpho connectors (right) + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- USB_DM : PA11 +- USB_DP : PA12 +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- DAC: PA4 +- ADC: PA0 +- PWM_1_CH1 : PE9 + +System Clock +------------ + +Nucleo F207ZG System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 120MHz, +driven by 8MHz high speed external clock. + +Serial Port +----------- + +Nucleo F207ZG board has 4 UARTs. The Zephyr console output is assigned to UART3. +Default settings are 115200 8N1. + +Network interface +----------------- + +Ethernet configured as the default network interface + +USB +--- +Nucleo F207ZG board has a USB OTG dual-role device (DRD) controller that +supports both device and host functions through its micro USB connector +(USB USER). Only USB device function is supported in Zephyr at the moment. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB156`` jumper on the back side of the board. + +Programming and Debugging +************************* + +Nucleo F207ZG board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F207ZG website: + https://www.st.com/en/evaluation-tools/nucleo-f207zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32F207ZG on www.st.com: + https://www.st.com/en/microcontrollers/stm32f207zg.html + +.. _STM32F207 reference manual: + https://www.st.com/resource/en/reference_manual/cd00225773.pdf diff --git a/boards/arm/nucleo_f207zg/nucleo_f207zg.dts b/boards/st/nucleo_f207zg/nucleo_f207zg.dts similarity index 100% rename from boards/arm/nucleo_f207zg/nucleo_f207zg.dts rename to boards/st/nucleo_f207zg/nucleo_f207zg.dts diff --git a/boards/arm/nucleo_f207zg/nucleo_f207zg.yaml b/boards/st/nucleo_f207zg/nucleo_f207zg.yaml similarity index 100% rename from boards/arm/nucleo_f207zg/nucleo_f207zg.yaml rename to boards/st/nucleo_f207zg/nucleo_f207zg.yaml diff --git a/boards/arm/nucleo_f207zg/nucleo_f207zg_defconfig b/boards/st/nucleo_f207zg/nucleo_f207zg_defconfig similarity index 84% rename from boards/arm/nucleo_f207zg/nucleo_f207zg_defconfig rename to boards/st/nucleo_f207zg/nucleo_f207zg_defconfig index b501adaa7ca..2f2243e0a3b 100644 --- a/boards/arm/nucleo_f207zg/nucleo_f207zg_defconfig +++ b/boards/st/nucleo_f207zg/nucleo_f207zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F2X=y -CONFIG_SOC_STM32F207XX=y - CONFIG_SERIAL=y # Enable MPU diff --git a/boards/arm/nucleo_f207zg/support/openocd.cfg b/boards/st/nucleo_f207zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f207zg/support/openocd.cfg rename to boards/st/nucleo_f207zg/support/openocd.cfg diff --git a/boards/st/nucleo_f302r8/Kconfig.nucleo_f302r8 b/boards/st/nucleo_f302r8/Kconfig.nucleo_f302r8 new file mode 100644 index 00000000000..06038690606 --- /dev/null +++ b/boards/st/nucleo_f302r8/Kconfig.nucleo_f302r8 @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Seitz & Associates +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F302R8 + select SOC_STM32F302X8 diff --git a/boards/arm/nucleo_f302r8/arduino_r3_connector.dtsi b/boards/st/nucleo_f302r8/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f302r8/arduino_r3_connector.dtsi rename to boards/st/nucleo_f302r8/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f302r8/board.cmake b/boards/st/nucleo_f302r8/board.cmake similarity index 100% rename from boards/arm/nucleo_f302r8/board.cmake rename to boards/st/nucleo_f302r8/board.cmake diff --git a/boards/st/nucleo_f302r8/board.yml b/boards/st/nucleo_f302r8/board.yml new file mode 100644 index 00000000000..a39ae3dc6d2 --- /dev/null +++ b/boards/st/nucleo_f302r8/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f302r8 + vendor: st + socs: + - name: stm32f302x8 diff --git a/boards/arm/nucleo_f302r8/doc/img/nucleo_f302r8.jpg b/boards/st/nucleo_f302r8/doc/img/nucleo_f302r8.jpg similarity index 100% rename from boards/arm/nucleo_f302r8/doc/img/nucleo_f302r8.jpg rename to boards/st/nucleo_f302r8/doc/img/nucleo_f302r8.jpg diff --git a/boards/arm/nucleo_f302r8/doc/img/nucleo_f302r8_connectors.jpg b/boards/st/nucleo_f302r8/doc/img/nucleo_f302r8_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f302r8/doc/img/nucleo_f302r8_connectors.jpg rename to boards/st/nucleo_f302r8/doc/img/nucleo_f302r8_connectors.jpg diff --git a/boards/st/nucleo_f302r8/doc/index.rst b/boards/st/nucleo_f302r8/doc/index.rst new file mode 100644 index 00000000000..88afebe40cb --- /dev/null +++ b/boards/st/nucleo_f302r8/doc/index.rst @@ -0,0 +1,168 @@ +.. _nucleo_f302r8_board: + +ST Nucleo F302R8 +################ + +Overview +******** + +The Nucleo F302R8 board features an ARM Cortex-M4 based STM32F302R8 +mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. +Here are some highlights of the Nucleo F302R8 board: + +- STM32 microcontroller in LQFP64 package +- LSE crystal: 32.768 kHz crystal oscillator +- Two types of extension resources: + + - Arduino* Uno V3 connectors + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- One user LED +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f302r8.jpg + :align: center + :alt: Nucleo F302R8 + +More information about the board can be found at the `Nucleo F302R8 website`_, +and in the `STM32 Nucleo-64 board User Manual`_. + +Hardware +******** + +The Nucleo F302R8 provides the following hardware components: + +- STM32F302R8T6 in QFP64 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 72 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 64 MB Flash +- 16 KB SRAM +- RTC +- Advanced-control Timer +- General Purpose Timers (4) +- Basic Timer +- Watchdog Timers (2) +- PWM channels (18) +- SPI/I2S (2) +- I2C (3) +- USART/UART (3/3) +- USB 2.0 FS with on-chip PHY +- CAN (2) +- GPIO with external interrupt capability +- DMA channels (7) +- Capacitive sensing channels (18) +- 12-bit ADC with 15 channels +- 12-bit D/A converter +- Analog comparator (3) +- Op amp + + +More information about the STM32F302R8 can be found here: + +- `STM32F302R8 on www.st.com`_ +- `STM32F302R8 reference manual`_ +- `STM32F302R8 datasheet`_ + +Supported Features +================== + +The Zephyr nucleo_f302r8 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f302r8/nucleo_f302r8_defconfig` + +Connections and IOs +=================== + +The Nucleo F302R8 Board has 5 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +Board connectors: +----------------- +.. image:: img/nucleo_f302r8_connectors.jpg + :align: center + :alt: Nucleo F302R8 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F302R8 board features an Arduino Uno V3 connector and a ST +morpho connector. Board is configured as follows: + +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- UART_3 TX/RX : PC10/PC11 +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI2 CS/SCK/MISO/MOSI : PB6/PB13/PB14/P15 (Arduino SPI) +- PWM_2_CH2 : PA0 +- USER_PB : PC13 +- LD2 : PB13 + +System Clock +------------ + +The Nucleo F302R8 System Clock can be driven by an internal or +external oscillator, as well as by the main PLL clock. By default the +System Clock is driven by the PLL clock at 72 MHz. The input to the +PLL is an 8 MHz external clock supplied by the processor of the +on-board ST-LINK/V2-1 debugger/programmer. + +Serial Port +----------- + +The Nucleo F302R8 board has 3 UARTs. The Zephyr console output is assigned +to UART2. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +The Nucleo F302R8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F302R8 website: + https://www.st.com/en/evaluation-tools/nucleo-f302r8.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F302R8 on www.st.com: + https://www.st.com/en/microcontrollers/stm32f302r8.html + +.. _STM32F302R8 reference manual: + https://www.st.com/resource/en/reference_manual/dm00094349.pdf + +.. _STM32F302R8 datasheet: + https://www.st.com/resource/en/datasheet/stm32f302r8.pdf diff --git a/boards/arm/nucleo_f302r8/nucleo_f302r8.dts b/boards/st/nucleo_f302r8/nucleo_f302r8.dts similarity index 100% rename from boards/arm/nucleo_f302r8/nucleo_f302r8.dts rename to boards/st/nucleo_f302r8/nucleo_f302r8.dts diff --git a/boards/arm/nucleo_f302r8/nucleo_f302r8.yaml b/boards/st/nucleo_f302r8/nucleo_f302r8.yaml similarity index 100% rename from boards/arm/nucleo_f302r8/nucleo_f302r8.yaml rename to boards/st/nucleo_f302r8/nucleo_f302r8.yaml diff --git a/boards/arm/nucleo_f302r8/nucleo_f302r8_defconfig b/boards/st/nucleo_f302r8/nucleo_f302r8_defconfig similarity index 79% rename from boards/arm/nucleo_f302r8/nucleo_f302r8_defconfig rename to boards/st/nucleo_f302r8/nucleo_f302r8_defconfig index 8cb3b3a13ad..ed6630de61e 100644 --- a/boards/arm/nucleo_f302r8/nucleo_f302r8_defconfig +++ b/boards/st/nucleo_f302r8/nucleo_f302r8_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F3X=y -CONFIG_SOC_STM32F302X8=y - CONFIG_SERIAL=y # console diff --git a/boards/arm/nucleo_f302r8/st_morpho_connector.dtsi b/boards/st/nucleo_f302r8/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f302r8/st_morpho_connector.dtsi rename to boards/st/nucleo_f302r8/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f302r8/support/openocd.cfg b/boards/st/nucleo_f302r8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f302r8/support/openocd.cfg rename to boards/st/nucleo_f302r8/support/openocd.cfg diff --git a/boards/st/nucleo_f303k8/Kconfig.nucleo_f303k8 b/boards/st/nucleo_f303k8/Kconfig.nucleo_f303k8 new file mode 100644 index 00000000000..6da913d4a82 --- /dev/null +++ b/boards/st/nucleo_f303k8/Kconfig.nucleo_f303k8 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Sebastian Schwabe +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F303K8 + select SOC_STM32F303X8 diff --git a/boards/arm/nucleo_f303k8/board.cmake b/boards/st/nucleo_f303k8/board.cmake similarity index 100% rename from boards/arm/nucleo_f303k8/board.cmake rename to boards/st/nucleo_f303k8/board.cmake diff --git a/boards/st/nucleo_f303k8/board.yml b/boards/st/nucleo_f303k8/board.yml new file mode 100644 index 00000000000..ae44e2bbb55 --- /dev/null +++ b/boards/st/nucleo_f303k8/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f303k8 + vendor: st + socs: + - name: stm32f303x8 diff --git a/boards/arm/nucleo_f303k8/doc/img/nucleo_f303k8.jpg b/boards/st/nucleo_f303k8/doc/img/nucleo_f303k8.jpg similarity index 100% rename from boards/arm/nucleo_f303k8/doc/img/nucleo_f303k8.jpg rename to boards/st/nucleo_f303k8/doc/img/nucleo_f303k8.jpg diff --git a/boards/arm/nucleo_f303k8/doc/img/nucleo_f303k8_pinout.jpg b/boards/st/nucleo_f303k8/doc/img/nucleo_f303k8_pinout.jpg similarity index 100% rename from boards/arm/nucleo_f303k8/doc/img/nucleo_f303k8_pinout.jpg rename to boards/st/nucleo_f303k8/doc/img/nucleo_f303k8_pinout.jpg diff --git a/boards/st/nucleo_f303k8/doc/index.rst b/boards/st/nucleo_f303k8/doc/index.rst new file mode 100644 index 00000000000..1f8ff4a3250 --- /dev/null +++ b/boards/st/nucleo_f303k8/doc/index.rst @@ -0,0 +1,159 @@ +.. _nucleo_f303k8_board: + +ST Nucleo F303K8 +################ + +Overview +******** + +The Nucleo F303K8 board features an ARM Cortex-M4 based STM32F303K8 +mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. +Here are some highlights of the Nucleo F303K8 board: + +- STM32 microcontroller in LQFP32 package +- one type of extension resources: + +- Arduino™ Nano V3 connectivity support + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + +- 5 V from ST-LINK/V2-1 USB VBUS +- External power sources: 3.3 V, 5V and 7 - 12 V + +- One user LED +- One push-buttons: RESET + +.. image:: img/nucleo_f303k8.jpg + :align: center + :alt: Nucleo F303K8 + +More information about the board can be found at the `Nucleo F303K8 website`_, +and in the `STM32 Nucleo-32 board User Manual`_. + +Hardware +******** + +The Nucleo F303K8 provides the following hardware components: + +- STM32F303K8T6 in LQFP32 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 72 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 64 MB Flash +- 12 KB SRAM +- RTC +- Advanced-control Timer +- General Purpose Timers (5) +- Basic Timer (2) +- Watchdog Timers (2) +- PWM channels (12) +- SPI/I2S (1) +- I2C (1) +- USART/UART (2) +- CAN (1) +- GPIO with external interrupt capability +- DMA channels (7) +- Capacitive sensing channels (18) +- 12-bit ADC with 21 channels +- 12-bit D/A converter +- Analog comparator (3) +- Op amp + + +More information about the STM32F303K8 can be found here: + +- `STM32F303K8 on www.st.com`_ +- `STM32F303K8 reference manual`_ +- `STM32F303K8 datasheet`_ + +Supported Features +================== + +The Zephyr nucleo_f303k8 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f303k8/nucleo_f303k8_defconfig` + +Connections and IOs +=================== + +The Nucleo F303K8 Board has 1 GPIO controller. This controllers is responsible +for input/output, pull-up, etc. + +Board connectors: +----------------- +.. image:: img/nucleo_f303k8_pinout.jpg + :align: center + :alt: Nucleo F303K8 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F303K8 board features an Arduino Zero V3 connector. Board is configured as follows: + +- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB7/PB6 +- SPI1 CS/SCK/MISO/MOSI : PA_4/PA_5/PB_4/PA_7 +- LD2 : PB3 + +System Clock +------------ + +The Nucleo F303K8 System Clock can be driven by an internal or +external oscillator, as well as by the main PLL clock. By default the +System Clock is driven by the PLL clock at 72 MHz. The input to the +PLL is an 8 MHz internal clock supply. + +Serial Port +----------- + +The Nucleo F303K8 board has 2 UARTs. The Zephyr console output is assigned +to UART2. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +The Nucleo F303K8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F303K8 website: + https://www.st.com/en/evaluation-tools/nucleo-F303K8.html + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf + +.. _STM32F303K8 on www.st.com: + https://www.st.com/en/microcontrollers/stm32F303K8.html + +.. _STM32F303K8 reference manual: + https://www.st.com/resource/en/reference_manual/dm00043574-stm32f303xbcde-stm32f303x68-stm32f328x8-stm32f358xc-stm32f398xe-advanced-armbased-mcus-stmicroelectronics.pdf + +.. _STM32F303K8 datasheet: + https://www.st.com/resource/en/datasheet/stm32f303k8.pdf diff --git a/boards/arm/nucleo_f303k8/nucleo_f303k8.dts b/boards/st/nucleo_f303k8/nucleo_f303k8.dts similarity index 100% rename from boards/arm/nucleo_f303k8/nucleo_f303k8.dts rename to boards/st/nucleo_f303k8/nucleo_f303k8.dts diff --git a/boards/arm/nucleo_f303k8/nucleo_f303k8.yaml b/boards/st/nucleo_f303k8/nucleo_f303k8.yaml similarity index 100% rename from boards/arm/nucleo_f303k8/nucleo_f303k8.yaml rename to boards/st/nucleo_f303k8/nucleo_f303k8.yaml diff --git a/boards/arm/nucleo_f303k8/nucleo_f303k8_defconfig b/boards/st/nucleo_f303k8/nucleo_f303k8_defconfig similarity index 79% rename from boards/arm/nucleo_f303k8/nucleo_f303k8_defconfig rename to boards/st/nucleo_f303k8/nucleo_f303k8_defconfig index 67f7f844b42..ed6630de61e 100644 --- a/boards/arm/nucleo_f303k8/nucleo_f303k8_defconfig +++ b/boards/st/nucleo_f303k8/nucleo_f303k8_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F3X=y -CONFIG_SOC_STM32F303X8=y - CONFIG_SERIAL=y # console diff --git a/boards/arm/nucleo_f303k8/support/openocd.cfg b/boards/st/nucleo_f303k8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f303k8/support/openocd.cfg rename to boards/st/nucleo_f303k8/support/openocd.cfg diff --git a/boards/st/nucleo_f303re/Kconfig.nucleo_f303re b/boards/st/nucleo_f303re/Kconfig.nucleo_f303re new file mode 100644 index 00000000000..7f2ad4639e3 --- /dev/null +++ b/boards/st/nucleo_f303re/Kconfig.nucleo_f303re @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Paul M. Bendixen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F303RE + select SOC_STM32F303XE diff --git a/boards/arm/nucleo_f303re/arduino_r3_connector.dtsi b/boards/st/nucleo_f303re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f303re/arduino_r3_connector.dtsi rename to boards/st/nucleo_f303re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f303re/board.cmake b/boards/st/nucleo_f303re/board.cmake similarity index 100% rename from boards/arm/nucleo_f303re/board.cmake rename to boards/st/nucleo_f303re/board.cmake diff --git a/boards/st/nucleo_f303re/board.yml b/boards/st/nucleo_f303re/board.yml new file mode 100644 index 00000000000..dc99dcc1d6a --- /dev/null +++ b/boards/st/nucleo_f303re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f303re + vendor: st + socs: + - name: stm32f303xe diff --git a/boards/arm/nucleo_f303re/doc/img/nucleo_connectors.jpg b/boards/st/nucleo_f303re/doc/img/nucleo_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f303re/doc/img/nucleo_connectors.jpg rename to boards/st/nucleo_f303re/doc/img/nucleo_connectors.jpg diff --git a/boards/arm/nucleo_f303re/doc/img/nucleo_f303re.jpg b/boards/st/nucleo_f303re/doc/img/nucleo_f303re.jpg similarity index 100% rename from boards/arm/nucleo_f303re/doc/img/nucleo_f303re.jpg rename to boards/st/nucleo_f303re/doc/img/nucleo_f303re.jpg diff --git a/boards/st/nucleo_f303re/doc/index.rst b/boards/st/nucleo_f303re/doc/index.rst new file mode 100644 index 00000000000..967079f1ff3 --- /dev/null +++ b/boards/st/nucleo_f303re/doc/index.rst @@ -0,0 +1,162 @@ +.. _nucleo_f303re_board: + +ST Nucleo F303RE +################ + +Overview +******** + +The Nucleo F303RE board features an ARM Cortex-M4 based STM32F303RE +mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. +Here are some highlights of the Nucleo F303RE board: + +- STM32 microcontroller in LQFP64 package +- LSE crystal: 32.768 kHz crystal oscillator +- Two types of extension resources: + + - Arduino* Uno V3 connectors + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- One user LED +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f303re.jpg + :align: center + :alt: Nucleo F303RE + +More information about the board can be found at the `Nucleo F303RE website`_, +and in the `STM32 Nucleo-64 board User Manual`_. + +Hardware +******** + +The Nucleo F303RE provides the following hardware components: + +- STM32F303RET6 in QFP64 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 72 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 512 MB Flash +- 64 + 16 KB SRAM +- RTC +- Advanced-control Timer +- General Purpose Timers (4) +- Basic Timer +- Watchdog Timers (2) +- PWM channels (18) +- SPI/I2S (2) +- I2C (3) +- USART/UART (3/3) +- USB 2.0 FS with on-chip PHY +- CAN (2) +- GPIO with external interrupt capability +- DMA channels (12) +- Capacitive sensing channels (18) +- 12-bit ADC with 40 channels (4) +- 12-bit D/A converter with two channels +- Analog comparator (7) +- Op amp (4) +- Capacitive sensing 24 channels + + +More information about the STM32F303RE can be found here: + +- `STM32F303RE on www.st.com`_ +- `STM32F303RE reference manual`_ +- `STM32F303RE datasheet`_ + +Supported Features +================== + +The Zephyr nucleo_f303re board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f303re/nucleo_f303re_defconfig` + +Connections and IOs +=================== + +The Nucleo F303RE Board has 5 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +Board connectors: +----------------- +.. image:: img/nucleo_connectors.jpg + :align: center + :alt: Nucleo F303RE connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F303RE board features an Arduino Uno V3 connector and a ST +morpho connector. Board is configured as follows: + +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD2 : PA5 + +System Clock +------------ + +The Nucleo F303RE System Clock can be driven by an internal or +external oscillator, as well as by the main PLL clock. By default the +System Clock is driven by the PLL clock at 72 MHz. The input to the +PLL is an 8 MHz external clock supplied by the processor of the +on-board ST-LINK/V2-1 debugger/programmer. + +Serial Port +----------- + +The Nucleo F303RE board has 2 UARTs. The Zephyr console output is assigned +to UART2. Default settings are 115200 8N1. + +Programming and Debugging +************************* + +The Nucleo F303RE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F303RE website: + https://www.st.com/en/evaluation-tools/nucleo-f303re.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F303RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f303re.html + +.. _STM32F303RE reference manual: + https://www.st.com/resource/en/reference_manual/dm00043574.pdf + +.. _STM32F303RE datasheet: + https://www.st.com/resource/en/datasheet/stm32f303re.pdf diff --git a/boards/arm/nucleo_f303re/nucleo_f303re.dts b/boards/st/nucleo_f303re/nucleo_f303re.dts similarity index 100% rename from boards/arm/nucleo_f303re/nucleo_f303re.dts rename to boards/st/nucleo_f303re/nucleo_f303re.dts diff --git a/boards/arm/nucleo_f303re/nucleo_f303re.yaml b/boards/st/nucleo_f303re/nucleo_f303re.yaml similarity index 100% rename from boards/arm/nucleo_f303re/nucleo_f303re.yaml rename to boards/st/nucleo_f303re/nucleo_f303re.yaml diff --git a/boards/arm/nucleo_f303re/nucleo_f303re_defconfig b/boards/st/nucleo_f303re/nucleo_f303re_defconfig similarity index 84% rename from boards/arm/nucleo_f303re/nucleo_f303re_defconfig rename to boards/st/nucleo_f303re/nucleo_f303re_defconfig index c73a485b239..2f2243e0a3b 100644 --- a/boards/arm/nucleo_f303re/nucleo_f303re_defconfig +++ b/boards/st/nucleo_f303re/nucleo_f303re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F3X=y -CONFIG_SOC_STM32F303XE=y - CONFIG_SERIAL=y # Enable MPU diff --git a/boards/arm/nucleo_f303re/st_morpho_connector.dtsi b/boards/st/nucleo_f303re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f303re/st_morpho_connector.dtsi rename to boards/st/nucleo_f303re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f303re/support/openocd.cfg b/boards/st/nucleo_f303re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f303re/support/openocd.cfg rename to boards/st/nucleo_f303re/support/openocd.cfg diff --git a/boards/st/nucleo_f334r8/Kconfig.defconfig b/boards/st/nucleo_f334r8/Kconfig.defconfig new file mode 100644 index 00000000000..7a48abedd47 --- /dev/null +++ b/boards/st/nucleo_f334r8/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-64 development board with STM32F334R8 MCU + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F334R8 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F334R8 diff --git a/boards/st/nucleo_f334r8/Kconfig.nucleo_f334r8 b/boards/st/nucleo_f334r8/Kconfig.nucleo_f334r8 new file mode 100644 index 00000000000..d605a67440e --- /dev/null +++ b/boards/st/nucleo_f334r8/Kconfig.nucleo_f334r8 @@ -0,0 +1,5 @@ +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F334R8 + select SOC_STM32F334X8 diff --git a/boards/arm/nucleo_f334r8/arduino_r3_connector.dtsi b/boards/st/nucleo_f334r8/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f334r8/arduino_r3_connector.dtsi rename to boards/st/nucleo_f334r8/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f334r8/board.cmake b/boards/st/nucleo_f334r8/board.cmake similarity index 100% rename from boards/arm/nucleo_f334r8/board.cmake rename to boards/st/nucleo_f334r8/board.cmake diff --git a/boards/st/nucleo_f334r8/board.yml b/boards/st/nucleo_f334r8/board.yml new file mode 100644 index 00000000000..7a8a3e642d8 --- /dev/null +++ b/boards/st/nucleo_f334r8/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f334r8 + vendor: st + socs: + - name: stm32f334x8 diff --git a/boards/arm/nucleo_f334r8/doc/img/nucleo_f334r8.jpg b/boards/st/nucleo_f334r8/doc/img/nucleo_f334r8.jpg similarity index 100% rename from boards/arm/nucleo_f334r8/doc/img/nucleo_f334r8.jpg rename to boards/st/nucleo_f334r8/doc/img/nucleo_f334r8.jpg diff --git a/boards/arm/nucleo_f334r8/doc/img/nucleo_f334r8_connectors.jpg b/boards/st/nucleo_f334r8/doc/img/nucleo_f334r8_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f334r8/doc/img/nucleo_f334r8_connectors.jpg rename to boards/st/nucleo_f334r8/doc/img/nucleo_f334r8_connectors.jpg diff --git a/boards/st/nucleo_f334r8/doc/index.rst b/boards/st/nucleo_f334r8/doc/index.rst new file mode 100644 index 00000000000..10e31269624 --- /dev/null +++ b/boards/st/nucleo_f334r8/doc/index.rst @@ -0,0 +1,179 @@ +.. _nucleo_f334r8_board: + +ST Nucleo F334R8 +################ + +Overview +******** +STM32 Nucleo-64 development board with STM32F334R8 MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board does not require any separate probe as it integrates the ST-LINK/V2-1 +debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f334r8.jpg + :align: center + :alt: Nucleo F334R8 + +More information about the board can be found at the `Nucleo F334R8 website`_. + +Hardware +******** +Nucleo F334R8 provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32F334R8 can be found in the +`STM32F334 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_f334r8 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f334r8/nucleo_f334r8_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_f334r8_connectors.jpg + :align: center + :alt: Nucleo F334R8 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- UART_3 TX/RX : PB10/PB11 +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- PWM_1_CH1 : PA8 +- USER_PB : PC13 +- LD2 : PA5 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f334r8`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F334R8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to Nucleo F334R8 +---------------------------------------- + +Connect the Nucleo F334R8 to your host computer using the USB port, +then build and flash an application. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f334r8 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for +the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f334r8 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F334R8 website: + https://www.st.com/en/evaluation-tools/nucleo-f334r8.html + +.. _STM32F334 reference manual: + https://www.st.com/resource/en/reference_manual/dm00093941.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f334r8/nucleo_f334r8.dts b/boards/st/nucleo_f334r8/nucleo_f334r8.dts similarity index 100% rename from boards/arm/nucleo_f334r8/nucleo_f334r8.dts rename to boards/st/nucleo_f334r8/nucleo_f334r8.dts diff --git a/boards/arm/nucleo_f334r8/nucleo_f334r8.yaml b/boards/st/nucleo_f334r8/nucleo_f334r8.yaml similarity index 100% rename from boards/arm/nucleo_f334r8/nucleo_f334r8.yaml rename to boards/st/nucleo_f334r8/nucleo_f334r8.yaml diff --git a/boards/st/nucleo_f334r8/nucleo_f334r8_defconfig b/boards/st/nucleo_f334r8/nucleo_f334r8_defconfig new file mode 100644 index 00000000000..d20d3802415 --- /dev/null +++ b/boards/st/nucleo_f334r8/nucleo_f334r8_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable clock +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f334r8/st_morpho_connector.dtsi b/boards/st/nucleo_f334r8/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f334r8/st_morpho_connector.dtsi rename to boards/st/nucleo_f334r8/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f334r8/support/openocd.cfg b/boards/st/nucleo_f334r8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f334r8/support/openocd.cfg rename to boards/st/nucleo_f334r8/support/openocd.cfg diff --git a/boards/st/nucleo_f401re/Kconfig.defconfig b/boards/st/nucleo_f401re/Kconfig.defconfig new file mode 100644 index 00000000000..cfb78f33442 --- /dev/null +++ b/boards/st/nucleo_f401re/Kconfig.defconfig @@ -0,0 +1,13 @@ +# NUCLEO-64 F401RE board configuration + +# Copyright (c) 2016 Linaro Limited. +# Copyright (c) 2019 Centaur Analytics, Inc +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F401RE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F401RE diff --git a/boards/st/nucleo_f401re/Kconfig.nucleo_f401re b/boards/st/nucleo_f401re/Kconfig.nucleo_f401re new file mode 100644 index 00000000000..8b67befec4b --- /dev/null +++ b/boards/st/nucleo_f401re/Kconfig.nucleo_f401re @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F401RE + select SOC_STM32F401XE diff --git a/boards/arm/nucleo_f401re/arduino_r3_connector.dtsi b/boards/st/nucleo_f401re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f401re/arduino_r3_connector.dtsi rename to boards/st/nucleo_f401re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f401re/board.cmake b/boards/st/nucleo_f401re/board.cmake similarity index 100% rename from boards/arm/nucleo_f401re/board.cmake rename to boards/st/nucleo_f401re/board.cmake diff --git a/boards/st/nucleo_f401re/board.yml b/boards/st/nucleo_f401re/board.yml new file mode 100644 index 00000000000..4cb781427b5 --- /dev/null +++ b/boards/st/nucleo_f401re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f401re + vendor: st + socs: + - name: stm32f401xe diff --git a/boards/arm/nucleo_f401re/doc/img/nucleo_f401re.jpg b/boards/st/nucleo_f401re/doc/img/nucleo_f401re.jpg similarity index 100% rename from boards/arm/nucleo_f401re/doc/img/nucleo_f401re.jpg rename to boards/st/nucleo_f401re/doc/img/nucleo_f401re.jpg diff --git a/boards/arm/nucleo_f401re/doc/img/nucleo_f401re_arduino.jpg b/boards/st/nucleo_f401re/doc/img/nucleo_f401re_arduino.jpg similarity index 100% rename from boards/arm/nucleo_f401re/doc/img/nucleo_f401re_arduino.jpg rename to boards/st/nucleo_f401re/doc/img/nucleo_f401re_arduino.jpg diff --git a/boards/arm/nucleo_f401re/doc/img/nucleo_f401re_morpho.jpg b/boards/st/nucleo_f401re/doc/img/nucleo_f401re_morpho.jpg similarity index 100% rename from boards/arm/nucleo_f401re/doc/img/nucleo_f401re_morpho.jpg rename to boards/st/nucleo_f401re/doc/img/nucleo_f401re_morpho.jpg diff --git a/boards/st/nucleo_f401re/doc/index.rst b/boards/st/nucleo_f401re/doc/index.rst new file mode 100644 index 00000000000..bd806a6378a --- /dev/null +++ b/boards/st/nucleo_f401re/doc/index.rst @@ -0,0 +1,206 @@ +.. _nucleo_f401re_board: + +ST Nucleo F401RE +################ + +Overview +******** + +The Nucleo F401RE board features an ARM Cortex-M4 based STM32F401RE MCU +with a wide range of connectivity support and configurations Here are +some highlights of the Nucleo F401RE board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f401re.jpg + :align: center + :alt: Nucleo F401RE + +More information about the board can be found at the `Nucleo F401RE website`_. + +Hardware +******** + +Nucleo F401RE provides the following hardware components: + +- STM32F401RET6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 84 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 96 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 16 channels +- RTC +- Advanced-control Timer +- General Purpose Timers (7) +- Watchdog Timers (2) +- USART/UART (3) +- I2C (3) +- SPI (4) +- SDIO +- USB 2.0 OTG FS +- DMA Controller + +More information about STM32F401RE can be found here: + +- `STM32F401RE on www.st.com`_ +- `STM32F401 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_401re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | System Window Watchdog | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f401re/nucleo_f401re_defconfig` + + +Pin Mapping +=========== + +Nucleo F401RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f401re_arduino.jpg + :align: center + :alt: Nucleo F401RE Arduino connectors +.. image:: img/nucleo_f401re_morpho.jpg + :align: center + :alt: Nucleo F401RE Morpho connectors + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD2 : PA5 + +System Clock +============ + +Nucleo F401RE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 84MHz, +driven by 8MHz high speed external clock. + +Serial Port +=========== + +Nucleo F401RE board has 3 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + +I2C +=== + +Nucleo F401RE board has up to 3 I2Cs. The default I2C mapping for Zephyr is: + +- I2C1_SCL : PB8 +- I2C1_SDA : PB9 + +Programming and Debugging +************************* + +Applications for the ``nucleo_f401re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F401RE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to Nucleo F401RE +---------------------------------------- + +Connect the Nucleo F401RE to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f401re + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f401re + :maybe-skip-config: + :goals: debug + +.. _Nucleo F401RE website: + https://www.st.com/en/evaluation-tools/nucleo-f401re.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F401RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f401re.html + +.. _STM32F401 reference manual: + https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/nucleo_f401re/nucleo_f401re.dts b/boards/st/nucleo_f401re/nucleo_f401re.dts similarity index 100% rename from boards/arm/nucleo_f401re/nucleo_f401re.dts rename to boards/st/nucleo_f401re/nucleo_f401re.dts diff --git a/boards/arm/nucleo_f401re/nucleo_f401re.yaml b/boards/st/nucleo_f401re/nucleo_f401re.yaml similarity index 100% rename from boards/arm/nucleo_f401re/nucleo_f401re.yaml rename to boards/st/nucleo_f401re/nucleo_f401re.yaml diff --git a/boards/arm/nucleo_f401re/nucleo_f401re_defconfig b/boards/st/nucleo_f401re/nucleo_f401re_defconfig similarity index 85% rename from boards/arm/nucleo_f401re/nucleo_f401re_defconfig rename to boards/st/nucleo_f401re/nucleo_f401re_defconfig index 637108b6d83..750f99bdff3 100644 --- a/boards/arm/nucleo_f401re/nucleo_f401re_defconfig +++ b/boards/st/nucleo_f401re/nucleo_f401re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f401re/st_morpho_connector.dtsi b/boards/st/nucleo_f401re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f401re/st_morpho_connector.dtsi rename to boards/st/nucleo_f401re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f401re/support/openocd.cfg b/boards/st/nucleo_f401re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f401re/support/openocd.cfg rename to boards/st/nucleo_f401re/support/openocd.cfg diff --git a/boards/st/nucleo_f410rb/Kconfig.defconfig b/boards/st/nucleo_f410rb/Kconfig.defconfig new file mode 100644 index 00000000000..198018e7cc0 --- /dev/null +++ b/boards/st/nucleo_f410rb/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32F410RB Nucleo board configuration + +# Copyright (c) 2020 Hans Unzner +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F410RB + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F410RB diff --git a/boards/st/nucleo_f410rb/Kconfig.nucleo_f410rb b/boards/st/nucleo_f410rb/Kconfig.nucleo_f410rb new file mode 100644 index 00000000000..2a62a1eecc7 --- /dev/null +++ b/boards/st/nucleo_f410rb/Kconfig.nucleo_f410rb @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Hans Unzner +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F410RB + select SOC_STM32F410RX diff --git a/boards/arm/nucleo_f410rb/arduino_r3_connector.dtsi b/boards/st/nucleo_f410rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f410rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_f410rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f410rb/board.cmake b/boards/st/nucleo_f410rb/board.cmake similarity index 100% rename from boards/arm/nucleo_f410rb/board.cmake rename to boards/st/nucleo_f410rb/board.cmake diff --git a/boards/st/nucleo_f410rb/board.yml b/boards/st/nucleo_f410rb/board.yml new file mode 100644 index 00000000000..23c247e3bad --- /dev/null +++ b/boards/st/nucleo_f410rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f410rb + vendor: st + socs: + - name: stm32f410rx diff --git a/boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb.jpg b/boards/st/nucleo_f410rb/doc/img/nucleo_f410rb.jpg similarity index 100% rename from boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb.jpg rename to boards/st/nucleo_f410rb/doc/img/nucleo_f410rb.jpg diff --git a/boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_left.jpg b/boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_left.jpg similarity index 100% rename from boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_left.jpg rename to boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_left.jpg diff --git a/boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_right.jpg b/boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_right.jpg similarity index 100% rename from boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_right.jpg rename to boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_right.jpg diff --git a/boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_left.jpg b/boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_left.jpg similarity index 100% rename from boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_left.jpg rename to boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_left.jpg diff --git a/boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_right.jpg b/boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_right.jpg similarity index 100% rename from boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_right.jpg rename to boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_right.jpg diff --git a/boards/st/nucleo_f410rb/doc/index.rst b/boards/st/nucleo_f410rb/doc/index.rst new file mode 100644 index 00000000000..58579bce21c --- /dev/null +++ b/boards/st/nucleo_f410rb/doc/index.rst @@ -0,0 +1,212 @@ +.. _nucleo_f410rb_board: + +ST Nucleo F410RB +################ + +Overview +******** + +The Nucleo F410RB board features an ARM Cortex-M4 based STM32F410RB MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F410RB board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f410rb.jpg + :align: center + :alt: Nucleo F410RB + +More information about the board can be found at the `Nucleo F410RB website`_. + +Hardware +******** + +Nucleo F410RB provides the following hardware components: + +- STM32F410RBT6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- Adaptive real-time accelerator (ART Accelerator) +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 128 KB Flash +- 32 KB SRAM +- General purpose timer (4) +- Low-power timer (1) +- Advanced-control timer (1) +- Random number generator (TRNG for HW entropy) +- SPI/I2S (3) +- I2C (3) +- USART (3) +- GPIO (50) with external interrupt capability +- 12-bit ADC with 16 channels +- 12-bit DAC with 1 channel +- RTC + + +More information about STM32F410RB can be found here: + +- `STM32F410RB on www.st.com`_ +- `STM32F410 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_f410rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | window & independent | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f410rb/nucleo_f410rb_defconfig` + + +Connections and IOs +=================== + +Nucleo F410RB Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f410rb_arduino_top_left.jpg + :align: center + :alt: Nucleo F410RB Arduino connectors (top left) +.. image:: img/nucleo_f410rb_arduino_top_right.jpg + :align: center + :alt: Nucleo F410RB Arduino connectors (top right) +.. image:: img/nucleo_f410rb_morpho_top_left.jpg + :align: center + :alt: Nucleo F410RB Morpho connectors (top left) +.. image:: img/nucleo_f410rb_morpho_top_right.jpg + :align: center + :alt: Nucleo F410RB Morpho connectors (top right) + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PC13 +- LD2 : PA5 +- I2C1_SDA : PB9 +- I2C1_SCL : PB8 +- I2C2_SDA : PB3 +- I2C2_SCL : PB10 + +System Clock +------------ + +Nucleo F410RB System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, +driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F410RB board has 3 USARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_f410rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F410RB board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F410RB +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f410rb + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f410rb + :maybe-skip-config: + :goals: debug + +.. _Nucleo F410RB website: + https://www.st.com/en/evaluation-tools/nucleo-F410RB.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F410RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32f410rb.html + +.. _STM32F410 reference manual: + https://www.st.com/resource/en/reference_manual/dm00180366.pdf diff --git a/boards/arm/nucleo_f410rb/nucleo_f410rb.dts b/boards/st/nucleo_f410rb/nucleo_f410rb.dts similarity index 100% rename from boards/arm/nucleo_f410rb/nucleo_f410rb.dts rename to boards/st/nucleo_f410rb/nucleo_f410rb.dts diff --git a/boards/arm/nucleo_f410rb/nucleo_f410rb.yaml b/boards/st/nucleo_f410rb/nucleo_f410rb.yaml similarity index 100% rename from boards/arm/nucleo_f410rb/nucleo_f410rb.yaml rename to boards/st/nucleo_f410rb/nucleo_f410rb.yaml diff --git a/boards/arm/nucleo_f410rb/nucleo_f410rb_defconfig b/boards/st/nucleo_f410rb/nucleo_f410rb_defconfig similarity index 84% rename from boards/arm/nucleo_f410rb/nucleo_f410rb_defconfig rename to boards/st/nucleo_f410rb/nucleo_f410rb_defconfig index 4c7485eb6b3..c729b83e3d0 100644 --- a/boards/arm/nucleo_f410rb/nucleo_f410rb_defconfig +++ b/boards/st/nucleo_f410rb/nucleo_f410rb_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F410RX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f410rb/st_morpho_connector.dtsi b/boards/st/nucleo_f410rb/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f410rb/st_morpho_connector.dtsi rename to boards/st/nucleo_f410rb/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f410rb/support/openocd.cfg b/boards/st/nucleo_f410rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f410rb/support/openocd.cfg rename to boards/st/nucleo_f410rb/support/openocd.cfg diff --git a/boards/st/nucleo_f411re/Kconfig.defconfig b/boards/st/nucleo_f411re/Kconfig.defconfig new file mode 100644 index 00000000000..43b605301ea --- /dev/null +++ b/boards/st/nucleo_f411re/Kconfig.defconfig @@ -0,0 +1,12 @@ +# NUCLEO-64 F411RE board configuration + +# Copyright (c) 2016 Matthias Boesl +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F411RE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F411RE diff --git a/boards/st/nucleo_f411re/Kconfig.nucleo_f411re b/boards/st/nucleo_f411re/Kconfig.nucleo_f411re new file mode 100644 index 00000000000..9f615187467 --- /dev/null +++ b/boards/st/nucleo_f411re/Kconfig.nucleo_f411re @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Matthias Boesl +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F411RE + select SOC_STM32F411XE diff --git a/boards/arm/nucleo_f411re/arduino_r3_connector.dtsi b/boards/st/nucleo_f411re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f411re/arduino_r3_connector.dtsi rename to boards/st/nucleo_f411re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f411re/board.cmake b/boards/st/nucleo_f411re/board.cmake similarity index 100% rename from boards/arm/nucleo_f411re/board.cmake rename to boards/st/nucleo_f411re/board.cmake diff --git a/boards/st/nucleo_f411re/board.yml b/boards/st/nucleo_f411re/board.yml new file mode 100644 index 00000000000..6ed17fdc2c4 --- /dev/null +++ b/boards/st/nucleo_f411re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f411re + vendor: st + socs: + - name: stm32f411xe diff --git a/boards/arm/nucleo_f411re/doc/img/nucleo_f411re.jpg b/boards/st/nucleo_f411re/doc/img/nucleo_f411re.jpg similarity index 100% rename from boards/arm/nucleo_f411re/doc/img/nucleo_f411re.jpg rename to boards/st/nucleo_f411re/doc/img/nucleo_f411re.jpg diff --git a/boards/arm/nucleo_f411re/doc/img/nucleo_f411re_arduino.jpg b/boards/st/nucleo_f411re/doc/img/nucleo_f411re_arduino.jpg similarity index 100% rename from boards/arm/nucleo_f411re/doc/img/nucleo_f411re_arduino.jpg rename to boards/st/nucleo_f411re/doc/img/nucleo_f411re_arduino.jpg diff --git a/boards/arm/nucleo_f411re/doc/img/nucleo_f411re_morpho.jpg b/boards/st/nucleo_f411re/doc/img/nucleo_f411re_morpho.jpg similarity index 100% rename from boards/arm/nucleo_f411re/doc/img/nucleo_f411re_morpho.jpg rename to boards/st/nucleo_f411re/doc/img/nucleo_f411re_morpho.jpg diff --git a/boards/st/nucleo_f411re/doc/index.rst b/boards/st/nucleo_f411re/doc/index.rst new file mode 100644 index 00000000000..77ca25184c6 --- /dev/null +++ b/boards/st/nucleo_f411re/doc/index.rst @@ -0,0 +1,200 @@ +.. _nucleo_f411re_board: + +ST Nucleo F411RE +################ + +Overview +******** + +The Nucleo F411RE board features an ARM Cortex-M4 based STM32F411RE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F411RE board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f411re.jpg + :align: center + :alt: Nucleo F411RE + +More information about the board can be found at the `Nucleo F411RE website`_. + +Hardware +******** + +Nucleo F411RE provides the following hardware components: + +- STM32F411RET6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 128 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 16 channels, with FIFO and burst support +- RTC +- 8 General purpose timers +- 2 watchdog timers (independent and window) +- SysTick timer +- USART/UART (3) +- I2C (3) +- SPI/I2S (5) +- SDIO +- USB 2.0 OTG FS +- DMA Controller +- CRC calculation unit + +More information about STM32F411RE can be found here: + +- `STM32F411RE on www.st.com`_ +- `STM32F411 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_f411re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f411re/nucleo_f411re_defconfig` + + +Connections and IOs +=================== + +Nucleo F411RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f411re_arduino.jpg + :align: center + :alt: Nucleo F411RE Arduino connectors +.. image:: img/nucleo_f411re_morpho.jpg + :align: center + :alt: Nucleo F411RE Morpho connectors + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PB10/PB3 +- I2C1 SCL/SDA : PA8/B4 +- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) +- I2S1 SCK/SD : PA5/PA7 (Arduino I2S) +- USER_PB : PC13 +- LD2 : PA5 + +.. note:: Please note that SPI1 and I2S1 are connected to the same mcu pins, as the h/w controller is the same one. + +System Clock +------------ + +Nucleo F411RE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 84MHz, +driven by 8MHz high speed external clock. + +Serial Port +----------- + +Nucleo F411RE board has 3 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_f411re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F411RE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to Nucleo F411RE +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f411re + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f411re + :maybe-skip-config: + :goals: debug + +.. _Nucleo F411RE website: + https://www.st.com/en/evaluation-tools/nucleo-f411re.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F411RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f411re.html + +.. _STM32F411 reference manual: + https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/nucleo_f411re/nucleo_f411re.dts b/boards/st/nucleo_f411re/nucleo_f411re.dts similarity index 100% rename from boards/arm/nucleo_f411re/nucleo_f411re.dts rename to boards/st/nucleo_f411re/nucleo_f411re.dts diff --git a/boards/arm/nucleo_f411re/nucleo_f411re.yaml b/boards/st/nucleo_f411re/nucleo_f411re.yaml similarity index 100% rename from boards/arm/nucleo_f411re/nucleo_f411re.yaml rename to boards/st/nucleo_f411re/nucleo_f411re.yaml diff --git a/boards/arm/nucleo_f411re/nucleo_f411re_defconfig b/boards/st/nucleo_f411re/nucleo_f411re_defconfig similarity index 85% rename from boards/arm/nucleo_f411re/nucleo_f411re_defconfig rename to boards/st/nucleo_f411re/nucleo_f411re_defconfig index cc07fdb2d8f..750f99bdff3 100644 --- a/boards/arm/nucleo_f411re/nucleo_f411re_defconfig +++ b/boards/st/nucleo_f411re/nucleo_f411re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F411XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f411re/st_morpho_connector.dtsi b/boards/st/nucleo_f411re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f411re/st_morpho_connector.dtsi rename to boards/st/nucleo_f411re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f411re/support/openocd.cfg b/boards/st/nucleo_f411re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f411re/support/openocd.cfg rename to boards/st/nucleo_f411re/support/openocd.cfg diff --git a/boards/st/nucleo_f412zg/Kconfig.defconfig b/boards/st/nucleo_f412zg/Kconfig.defconfig new file mode 100644 index 00000000000..a2c9ec55881 --- /dev/null +++ b/boards/st/nucleo_f412zg/Kconfig.defconfig @@ -0,0 +1,18 @@ +# NUCLEO-144 F412ZG board configuration + +# Copyright (c) 2017 Florian Vaussard, HEIG-VD +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F412ZG + +if NETWORKING + +config USB_DEVICE_STACK + default y + +config USB_DEVICE_NETWORK_ECM + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F412ZG diff --git a/boards/st/nucleo_f412zg/Kconfig.nucleo_f412zg b/boards/st/nucleo_f412zg/Kconfig.nucleo_f412zg new file mode 100644 index 00000000000..93a0b9f9a5b --- /dev/null +++ b/boards/st/nucleo_f412zg/Kconfig.nucleo_f412zg @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Florian Vaussard, HEIG-VD +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F412ZG + select SOC_STM32F412ZX diff --git a/boards/arm/nucleo_f412zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f412zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f412zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_f412zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f412zg/board.cmake b/boards/st/nucleo_f412zg/board.cmake similarity index 100% rename from boards/arm/nucleo_f412zg/board.cmake rename to boards/st/nucleo_f412zg/board.cmake diff --git a/boards/st/nucleo_f412zg/board.yml b/boards/st/nucleo_f412zg/board.yml new file mode 100644 index 00000000000..b4bb8372f50 --- /dev/null +++ b/boards/st/nucleo_f412zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f412zg + vendor: st + socs: + - name: stm32f412zx diff --git a/boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg.jpg b/boards/st/nucleo_f412zg/doc/img/nucleo_f412zg.jpg similarity index 100% rename from boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg.jpg rename to boards/st/nucleo_f412zg/doc/img/nucleo_f412zg.jpg diff --git a/boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_left.jpg b/boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_left.jpg similarity index 100% rename from boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_left.jpg rename to boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_left.jpg diff --git a/boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_right.jpg b/boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_right.jpg similarity index 100% rename from boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_right.jpg rename to boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_right.jpg diff --git a/boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_zio_left.jpg b/boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_zio_left.jpg similarity index 100% rename from boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_zio_left.jpg rename to boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_zio_left.jpg diff --git a/boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_zio_right.jpg b/boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_zio_right.jpg similarity index 100% rename from boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_zio_right.jpg rename to boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_zio_right.jpg diff --git a/boards/st/nucleo_f412zg/doc/index.rst b/boards/st/nucleo_f412zg/doc/index.rst new file mode 100644 index 00000000000..40039aed089 --- /dev/null +++ b/boards/st/nucleo_f412zg/doc/index.rst @@ -0,0 +1,172 @@ +.. _nucleo_f412zg_board: + +ST Nucleo F412ZG +################ + +Overview +******** + +The Nucleo F412ZG board features an ARM Cortex-M4 based STM32F412ZG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F412ZG board: + +- STM32 microcontroller in LQFP144 package +- Two types of extension resources: + + - ST Zio connector including: support for Arduino* Uno V3 connectivity + (A0 to A5, D0 to D15) and additional signals exposing a wide range of + peripherals + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- Three user LEDs +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f412zg.jpg + :align: center + :alt: Nucleo F412ZG + +More information about the board can be found at the `Nucleo F412ZG website`_. + +Hardware +******** + +Nucleo F412ZG provides the following hardware components: + +- STM32F412ZGT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1 MB Flash +- 256 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 16 channels, with FIFO and burst support +- RTC +- 14 General purpose timers +- 2 watchdog timers (independent and window) +- SysTick timer +- USART/UART (4) +- I2C (4) +- SPI (5) +- SDIO +- USB 2.0 OTG FS +- DMA Controller +- CRC calculation unit + +More information about STM32F412ZG can be found here: + +- `STM32F412ZG on www.st.com`_ +- `STM32F412 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_412zg board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f412zg/nucleo_f412zg_defconfig` + + +Connections and IOs +=================== + +Nucleo F412ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f412zg_zio_left.jpg + :align: center + :alt: Nucleo F412ZG ZIO connectors (left) +.. image:: img/nucleo_f412zg_zio_right.jpg + :align: center + :alt: Nucleo F412ZG ZIO connectors (right) +.. image:: img/nucleo_f412zg_morpho_left.jpg + :align: center + :alt: Nucleo F412ZG Morpho connectors (left) +.. image:: img/nucleo_f412zg_morpho_right.jpg + :align: center + :alt: Nucleo F412ZG Morpho connectors (right) + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- USB DM : PA11 +- USB DP : PA12 + +System Clock +------------ + +Nucleo F412ZG System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz, +driven by 8MHz high speed external clock. + +Serial Port +----------- + +Nucleo F412ZG board has 4 UARTs. The Zephyr console output is assigned to UART3. +Default settings are 115200 8N1. + +Network interface +----------------- + +Ethernet over USB is configured as the default network interface + +Programming and Debugging +************************* + +Nucleo F412ZG board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F412ZG website: + https://www.st.com/en/evaluation-tools/nucleo-f412zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32F412ZG on www.st.com: + https://www.st.com/en/microcontrollers/stm32f412zg.html + +.. _STM32F412 reference manual: + https://www.st.com/resource/en/reference_manual/dm00180369.pdf diff --git a/boards/arm/nucleo_f412zg/nucleo_f412zg.dts b/boards/st/nucleo_f412zg/nucleo_f412zg.dts similarity index 100% rename from boards/arm/nucleo_f412zg/nucleo_f412zg.dts rename to boards/st/nucleo_f412zg/nucleo_f412zg.dts diff --git a/boards/arm/nucleo_f412zg/nucleo_f412zg.yaml b/boards/st/nucleo_f412zg/nucleo_f412zg.yaml similarity index 100% rename from boards/arm/nucleo_f412zg/nucleo_f412zg.yaml rename to boards/st/nucleo_f412zg/nucleo_f412zg.yaml diff --git a/boards/arm/nucleo_f412zg/nucleo_f412zg_defconfig b/boards/st/nucleo_f412zg/nucleo_f412zg_defconfig similarity index 84% rename from boards/arm/nucleo_f412zg/nucleo_f412zg_defconfig rename to boards/st/nucleo_f412zg/nucleo_f412zg_defconfig index d9ce153a46b..c729b83e3d0 100644 --- a/boards/arm/nucleo_f412zg/nucleo_f412zg_defconfig +++ b/boards/st/nucleo_f412zg/nucleo_f412zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F412ZX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f412zg/support/openocd.cfg b/boards/st/nucleo_f412zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f412zg/support/openocd.cfg rename to boards/st/nucleo_f412zg/support/openocd.cfg diff --git a/boards/st/nucleo_f413zh/Kconfig.defconfig b/boards/st/nucleo_f413zh/Kconfig.defconfig new file mode 100644 index 00000000000..34fb8d56961 --- /dev/null +++ b/boards/st/nucleo_f413zh/Kconfig.defconfig @@ -0,0 +1,18 @@ +# NUCLEO-144 F413ZH board configuration + +# Copyright (c) 2017 Florian Vaussard, HEIG-VD +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F413ZH + +if NETWORKING + +config USB_DEVICE_STACK + default y + +config USB_DEVICE_NETWORK_ECM + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F413ZH diff --git a/boards/st/nucleo_f413zh/Kconfig.nucleo_f413zh b/boards/st/nucleo_f413zh/Kconfig.nucleo_f413zh new file mode 100644 index 00000000000..7ca7fe10894 --- /dev/null +++ b/boards/st/nucleo_f413zh/Kconfig.nucleo_f413zh @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Florian Vaussard, HEIG-VD +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F413ZH + select SOC_STM32F413XX diff --git a/boards/arm/nucleo_f413zh/arduino_r3_connector.dtsi b/boards/st/nucleo_f413zh/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f413zh/arduino_r3_connector.dtsi rename to boards/st/nucleo_f413zh/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f413zh/board.cmake b/boards/st/nucleo_f413zh/board.cmake similarity index 100% rename from boards/arm/nucleo_f413zh/board.cmake rename to boards/st/nucleo_f413zh/board.cmake diff --git a/boards/st/nucleo_f413zh/board.yml b/boards/st/nucleo_f413zh/board.yml new file mode 100644 index 00000000000..a372cec4b8a --- /dev/null +++ b/boards/st/nucleo_f413zh/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f413zh + vendor: st + socs: + - name: stm32f413xx diff --git a/boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh.jpg b/boards/st/nucleo_f413zh/doc/img/nucleo_f413zh.jpg similarity index 100% rename from boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh.jpg rename to boards/st/nucleo_f413zh/doc/img/nucleo_f413zh.jpg diff --git a/boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_left.jpg b/boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_left.jpg similarity index 100% rename from boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_left.jpg rename to boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_left.jpg diff --git a/boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_right.jpg b/boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_right.jpg similarity index 100% rename from boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_right.jpg rename to boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_right.jpg diff --git a/boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_zio_left.jpg b/boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_zio_left.jpg similarity index 100% rename from boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_zio_left.jpg rename to boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_zio_left.jpg diff --git a/boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_zio_right.jpg b/boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_zio_right.jpg similarity index 100% rename from boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_zio_right.jpg rename to boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_zio_right.jpg diff --git a/boards/st/nucleo_f413zh/doc/index.rst b/boards/st/nucleo_f413zh/doc/index.rst new file mode 100644 index 00000000000..c6452fb4456 --- /dev/null +++ b/boards/st/nucleo_f413zh/doc/index.rst @@ -0,0 +1,174 @@ +.. _nucleo_f413zh_board: + +ST Nucleo F413ZH +################ + +Overview +******** + +The Nucleo F413ZH board features an ARM Cortex-M4 based STM32F413ZH MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F413ZH board: + +- STM32 microcontroller in LQFP144 package +- Two types of extension resources: + + - ST Zio connector including: support for Arduino* Uno V3 connectivity + (A0 to A5, D0 to D15) and additional signals exposing a wide range of + peripherals + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- Three user LEDs +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f413zh.jpg + :align: center + :alt: Nucleo F413ZH + +More information about the board can be found at the `Nucleo F413ZH website`_. + +Hardware +******** + +Nucleo F413ZH provides the following hardware components: + +- STM32F413ZHT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1.5 MB Flash +- 320 KB SRAM +- GPIO with external interrupt capability +- 2 12-bit ADC with 16 channels, with FIFO and burst support +- RTC +- 14 General purpose timers +- 2 watchdog timers (independent and window) +- SysTick timer +- USART/UART (10) +- I2C (4) +- SPI (5) +- SDIO +- USB 2.0 OTG FS +- DMA Controller +- CRC calculation unit + +More information about STM32F413ZH can be found here: + +- `STM32F413ZH on www.st.com`_ +- `STM32F413/423 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_413zh board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f413zh/nucleo_f413zh_defconfig` + + +Connections and IOs +=================== + +Nucleo F413ZH Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f413zh_zio_left.jpg + :align: center + :alt: Nucleo F413ZH ZIO connectors (left) +.. image:: img/nucleo_f413zh_zio_right.jpg + :align: center + :alt: Nucleo F413ZH ZIO connectors (right) +.. image:: img/nucleo_f413zh_morpho_left.jpg + :align: center + :alt: Nucleo F413ZH Morpho connectors (left) +.. image:: img/nucleo_f413zh_morpho_right.jpg + :align: center + :alt: Nucleo F413ZH Morpho connectors (right) + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) +- PWM_2_CH1 : PA0 +- USB_DM : PA11 +- USB_DP : PA12 +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 + +System Clock +------------ + +Nucleo F413ZH System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz, +driven by 8MHz high speed external clock. + +Serial Port +----------- + +Nucleo F413ZH board has 10 UARTs. The Zephyr console output is assigned to UART3. +Default settings are 115200 8N1. + +USB +=== +Nucleo F413ZH board has a USB OTG dual-role device (DRD) controller that +supports both device and host functions through its micro USB connector +(USB USER). Only USB device function is supported in Zephyr at the moment. + + +Programming and Debugging +************************* + +Nucleo F413ZH board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F413ZH website: + https://www.st.com/en/evaluation-tools/nucleo-f413zh.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32F413ZH on www.st.com: + https://www.st.com/en/microcontrollers/stm32f413zh.html + +.. _STM32F413/423 reference manual: + https://www.st.com/resource/en/reference_manual/dm00305666.pdf diff --git a/boards/arm/nucleo_f413zh/nucleo_f413zh.dts b/boards/st/nucleo_f413zh/nucleo_f413zh.dts similarity index 100% rename from boards/arm/nucleo_f413zh/nucleo_f413zh.dts rename to boards/st/nucleo_f413zh/nucleo_f413zh.dts diff --git a/boards/arm/nucleo_f413zh/nucleo_f413zh.yaml b/boards/st/nucleo_f413zh/nucleo_f413zh.yaml similarity index 100% rename from boards/arm/nucleo_f413zh/nucleo_f413zh.yaml rename to boards/st/nucleo_f413zh/nucleo_f413zh.yaml diff --git a/boards/arm/nucleo_f413zh/nucleo_f413zh_defconfig b/boards/st/nucleo_f413zh/nucleo_f413zh_defconfig similarity index 84% rename from boards/arm/nucleo_f413zh/nucleo_f413zh_defconfig rename to boards/st/nucleo_f413zh/nucleo_f413zh_defconfig index 1b7b52cb5b7..c729b83e3d0 100644 --- a/boards/arm/nucleo_f413zh/nucleo_f413zh_defconfig +++ b/boards/st/nucleo_f413zh/nucleo_f413zh_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F413XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f413zh/support/openocd.cfg b/boards/st/nucleo_f413zh/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f413zh/support/openocd.cfg rename to boards/st/nucleo_f413zh/support/openocd.cfg diff --git a/boards/st/nucleo_f429zi/Kconfig.defconfig b/boards/st/nucleo_f429zi/Kconfig.defconfig new file mode 100644 index 00000000000..2198e75674f --- /dev/null +++ b/boards/st/nucleo_f429zi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# NUCLEO-144 F429ZI board configuration + +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F429ZI + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F429ZI diff --git a/boards/st/nucleo_f429zi/Kconfig.nucleo_f429zi b/boards/st/nucleo_f429zi/Kconfig.nucleo_f429zi new file mode 100644 index 00000000000..baed70d72d7 --- /dev/null +++ b/boards/st/nucleo_f429zi/Kconfig.nucleo_f429zi @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F429ZI + select SOC_STM32F429XX diff --git a/boards/arm/nucleo_f429zi/arduino_r3_connector.dtsi b/boards/st/nucleo_f429zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f429zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_f429zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f429zi/board.cmake b/boards/st/nucleo_f429zi/board.cmake similarity index 100% rename from boards/arm/nucleo_f429zi/board.cmake rename to boards/st/nucleo_f429zi/board.cmake diff --git a/boards/st/nucleo_f429zi/board.yml b/boards/st/nucleo_f429zi/board.yml new file mode 100644 index 00000000000..ecf8e93828b --- /dev/null +++ b/boards/st/nucleo_f429zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f429zi + vendor: st + socs: + - name: stm32f429xx diff --git a/boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi.jpg b/boards/st/nucleo_f429zi/doc/img/nucleo_f429zi.jpg similarity index 100% rename from boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi.jpg rename to boards/st/nucleo_f429zi/doc/img/nucleo_f429zi.jpg diff --git a/boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn11.jpg b/boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn11.jpg similarity index 100% rename from boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn11.jpg rename to boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn11.jpg diff --git a/boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn12.jpg b/boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn12.jpg similarity index 100% rename from boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn12.jpg rename to boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn12.jpg diff --git a/boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn7.jpg b/boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn7.jpg similarity index 100% rename from boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn7.jpg rename to boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn7.jpg diff --git a/boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn8.jpg b/boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn8.jpg similarity index 100% rename from boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn8.jpg rename to boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn8.jpg diff --git a/boards/st/nucleo_f429zi/doc/index.rst b/boards/st/nucleo_f429zi/doc/index.rst new file mode 100644 index 00000000000..9e795649a4e --- /dev/null +++ b/boards/st/nucleo_f429zi/doc/index.rst @@ -0,0 +1,217 @@ +.. _nucleo_f429zi_board: + +ST Nucleo F429ZI +################ + +Overview +******** + +The Nucleo F429ZI board features an ARM Cortex-M4 based STM32F429ZI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F429ZI board: + +- STM32 microcontroller in LQFP144 package +- LSE crystal: 32.768 kHz crystal oscillator +- USB OTG +- Ethernet compliant with IEEE-802.3-2002 +- Two types of extension resources: + + - ST Zio connector including: support for Arduino* Uno V3 connectivity + (A0 to A5, D0 to D15) and additional signals exposing a wide range of + peripherals + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- Three user LEDs +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f429zi.jpg + :align: center + :alt: Nucleo F429ZI + +More information about the board can be found at the `Nucleo F429ZI website`_. + +Hardware +******** + +The Nucleo F429ZI provides the following hardware components: + +- STM32F429ZIT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 180 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 2 MB Flash +- 256+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (4/4) +- I2C (3) +- SPI (6) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F429ZI can be found here: + +- `STM32F429ZI on www.st.com`_ +- `STM32F429 reference manual`_ +- `STM32F429 datasheet`_ + +Supported Features +================== + +The Zephyr nucleo_f429zi board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | Ethernet | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f429zi/nucleo_f429zi_defconfig` + + +Connections and IOs +=================== + +The Nucleo F429ZI Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f429zi_cn8.jpg + :align: center + :alt: Nucleo F429ZI ZIO connectors (left) +.. image:: img/nucleo_f429zi_cn7.jpg + :align: center + :alt: Nucleo F429ZI ZIO connectors (right) +.. image:: img/nucleo_f429zi_cn11.jpg + :align: center + :alt: Nucleo F429ZI Morpho connectors (left) +.. image:: img/nucleo_f429zi_cn12.jpg + :align: center + :alt: Nucleo F429ZI Morpho connectors (right) + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F429ZI board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) +- PWM_2_CH1 : PE13 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- USB DM : PA11 +- USB DP : PA12 +- ADC1 : PA0 + +System Clock +------------ + +The Nucleo F429ZI System Clock could be driven by an internal or external oscillator, +as well as by the main PLL clock. By default System clock is driven by PLL clock at 180MHz, +driven by an 8MHz high speed external clock. + +Serial Port +----------- + +The Nucleo F429ZI board has 8 UARTs. The Zephyr console output is assigned to UART3. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +The Nucleo F429ZI board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flash partitions for MCUBoot bootloader +*************************************** + +The on-board STM32F429ZI MCU has 2MBs of internal flash memory. To use `MCUboot`_, +define a :ref:`Zephyr partition table ` for the flash memory in +its devicetree file ``nucleo_f429zi.dts``. As a reference, a partition table for +MCUBoot is already defined in the devicetree file, with these settings: + +- `MCUBoot`_ bootloader partition takes 64K bytes. +- Zephyr settings partition takes 64K bytes. +- Application image takes 256K bytes in Slot 0 partition. +- Updating image takes another 256K bytes in Slot 1 partition. +- A scratch partition with 128K is required for image swap. + +A specific application can adjust each partition size based on its needs. + + +.. _Nucleo F429ZI website: + https://www.st.com/en/evaluation-tools/nucleo-f429zi.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32F429ZI on www.st.com: + https://www.st.com/en/microcontrollers/stm32f429zi.html + +.. _STM32F429 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031020.pdf + +.. _STM32F429 datasheet: + https://www.st.com/resource/en/datasheet/DM00071990.pdf + +.. _MCUBoot: + https://github.com/JuulLabs-OSS/mcuboot/blob/master/README.md diff --git a/boards/arm/nucleo_f429zi/nucleo_f429zi.dts b/boards/st/nucleo_f429zi/nucleo_f429zi.dts similarity index 100% rename from boards/arm/nucleo_f429zi/nucleo_f429zi.dts rename to boards/st/nucleo_f429zi/nucleo_f429zi.dts diff --git a/boards/arm/nucleo_f429zi/nucleo_f429zi.yaml b/boards/st/nucleo_f429zi/nucleo_f429zi.yaml similarity index 100% rename from boards/arm/nucleo_f429zi/nucleo_f429zi.yaml rename to boards/st/nucleo_f429zi/nucleo_f429zi.yaml diff --git a/boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig b/boards/st/nucleo_f429zi/nucleo_f429zi_defconfig similarity index 85% rename from boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig rename to boards/st/nucleo_f429zi/nucleo_f429zi_defconfig index 478a485246c..750f99bdff3 100644 --- a/boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig +++ b/boards/st/nucleo_f429zi/nucleo_f429zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F429XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f429zi/support/openocd.cfg b/boards/st/nucleo_f429zi/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f429zi/support/openocd.cfg rename to boards/st/nucleo_f429zi/support/openocd.cfg diff --git a/boards/st/nucleo_f446re/Kconfig.defconfig b/boards/st/nucleo_f446re/Kconfig.defconfig new file mode 100644 index 00000000000..4ccbf9d1580 --- /dev/null +++ b/boards/st/nucleo_f446re/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32F446RE Nucleo board configuration + +# Copyright (c) 2018 Philémon Jaermann +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F446RE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F446RE diff --git a/boards/st/nucleo_f446re/Kconfig.nucleo_f446re b/boards/st/nucleo_f446re/Kconfig.nucleo_f446re new file mode 100644 index 00000000000..72bfcd37459 --- /dev/null +++ b/boards/st/nucleo_f446re/Kconfig.nucleo_f446re @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Philémon Jaermann +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F446RE + select SOC_STM32F446XX diff --git a/boards/arm/nucleo_f446re/arduino_r3_connector.dtsi b/boards/st/nucleo_f446re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f446re/arduino_r3_connector.dtsi rename to boards/st/nucleo_f446re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f446re/board.cmake b/boards/st/nucleo_f446re/board.cmake similarity index 100% rename from boards/arm/nucleo_f446re/board.cmake rename to boards/st/nucleo_f446re/board.cmake diff --git a/boards/st/nucleo_f446re/board.yml b/boards/st/nucleo_f446re/board.yml new file mode 100644 index 00000000000..d68a45990b8 --- /dev/null +++ b/boards/st/nucleo_f446re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f446re + vendor: st + socs: + - name: stm32f446xx diff --git a/boards/arm/nucleo_f446re/doc/img/nucleo_f446re.jpg b/boards/st/nucleo_f446re/doc/img/nucleo_f446re.jpg similarity index 100% rename from boards/arm/nucleo_f446re/doc/img/nucleo_f446re.jpg rename to boards/st/nucleo_f446re/doc/img/nucleo_f446re.jpg diff --git a/boards/arm/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_left.jpg b/boards/st/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_left.jpg similarity index 100% rename from boards/arm/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_left.jpg rename to boards/st/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_left.jpg diff --git a/boards/arm/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_right.jpg b/boards/st/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_right.jpg similarity index 100% rename from boards/arm/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_right.jpg rename to boards/st/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_right.jpg diff --git a/boards/arm/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_left.jpg b/boards/st/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_left.jpg similarity index 100% rename from boards/arm/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_left.jpg rename to boards/st/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_left.jpg diff --git a/boards/arm/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_right.jpg b/boards/st/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_right.jpg similarity index 100% rename from boards/arm/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_right.jpg rename to boards/st/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_right.jpg diff --git a/boards/st/nucleo_f446re/doc/index.rst b/boards/st/nucleo_f446re/doc/index.rst new file mode 100644 index 00000000000..28fe7699e60 --- /dev/null +++ b/boards/st/nucleo_f446re/doc/index.rst @@ -0,0 +1,226 @@ +.. _nucleo_f446re_board: + +ST Nucleo F446RE +################ + +Overview +******** + +The Nucleo F446RE board features an ARM Cortex-M4 based STM32F446RE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F446RE board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f446re.jpg + :align: center + :alt: Nucleo F446RE + +More information about the board can be found at the `Nucleo F446RE website`_. + +Hardware +******** + +Nucleo F446RE provides the following hardware components: + +- STM32F446RET6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- Adaptive real-time accelerator (ART Accelerator) +- 180 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 128 KB SRAM +- 10 General purpose timers +- 2 Advanced control timers +- 2 basic timers +- SPI(4) +- I2C(3) +- USART(4) +- UART(2) +- USB OTG Full Speed and High Speed +- CAN(2) +- SAI(2) +- SPDIF_Rx(1) +- HDMI_CEC(1) +- Quad SPI(1) +- Camera Interface +- GPIO(50) with external interrupt capability +- 12-bit ADC(3) with 16 channels +- 12-bit DAC with 2 channels + +More information about STM32F446RE can be found here: + +- `STM32F446RE on www.st.com`_ +- `STM32F446 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_f446re board configuration supports the following hardware features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ +| CAN 1/2 | on-chip | Controller Area Network | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f446re/nucleo_f446re_defconfig` + + +Connections and IOs +=================== + +Nucleo F446RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f446re_arduino_top_left.jpg + :align: center + :alt: Nucleo F446RE Arduino connectors (top left) +.. image:: img/nucleo_f446re_arduino_top_right.jpg + :align: center + :alt: Nucleo F446RE Arduino connectors (top right) +.. image:: img/nucleo_f446re_morpho_top_left.jpg + :align: center + :alt: Nucleo F446RE Morpho connectors (top left) +.. image:: img/nucleo_f446re_morpho_top_right.jpg + :align: center + :alt: Nucleo F446RE Morpho connectors (top right) + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PC13 +- LD2 : PA5 +- I2C1_SDA : PB9 +- I2C1_SCL : PB8 +- I2C2_SDA : PB3 +- I2C2_SCL : PB10 +- I2C3_SDA : PB4 +- I2C3_SCL : PA8 + +System Clock +------------ + +Nucleo F446RE System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, +driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F446RE board has 2 UARTs and 4 USARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB45`` jumper on the back side of the board. + +Controller Area Network +----------------------- + +The TX/RX wires connected with D14/D15 of CN5 connector. Thus the board can be +used with `RS485 CAN Shield`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f446re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F446RE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F446RE +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f446re + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f446re + :maybe-skip-config: + :goals: debug + +.. _Nucleo F446RE website: + https://www.st.com/en/evaluation-tools/nucleo-f446re.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F446RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f446re.html + +.. _STM32F446 reference manual: + https://www.st.com/resource/en/reference_manual/dm00135183.pdf + +.. _RS485 CAN Shield: + https://www.waveshare.com/wiki/RS485_CAN_Shield diff --git a/boards/arm/nucleo_f446re/nucleo_f446re.dts b/boards/st/nucleo_f446re/nucleo_f446re.dts similarity index 100% rename from boards/arm/nucleo_f446re/nucleo_f446re.dts rename to boards/st/nucleo_f446re/nucleo_f446re.dts diff --git a/boards/arm/nucleo_f446re/nucleo_f446re.yaml b/boards/st/nucleo_f446re/nucleo_f446re.yaml similarity index 100% rename from boards/arm/nucleo_f446re/nucleo_f446re.yaml rename to boards/st/nucleo_f446re/nucleo_f446re.yaml diff --git a/boards/arm/nucleo_f446re/nucleo_f446re_defconfig b/boards/st/nucleo_f446re/nucleo_f446re_defconfig similarity index 84% rename from boards/arm/nucleo_f446re/nucleo_f446re_defconfig rename to boards/st/nucleo_f446re/nucleo_f446re_defconfig index a9e0141c125..c729b83e3d0 100644 --- a/boards/arm/nucleo_f446re/nucleo_f446re_defconfig +++ b/boards/st/nucleo_f446re/nucleo_f446re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F446XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f446re/st_morpho_connector.dtsi b/boards/st/nucleo_f446re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f446re/st_morpho_connector.dtsi rename to boards/st/nucleo_f446re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f446re/support/openocd.cfg b/boards/st/nucleo_f446re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f446re/support/openocd.cfg rename to boards/st/nucleo_f446re/support/openocd.cfg diff --git a/boards/st/nucleo_f446ze/Kconfig.defconfig b/boards/st/nucleo_f446ze/Kconfig.defconfig new file mode 100644 index 00000000000..0023ff8bde8 --- /dev/null +++ b/boards/st/nucleo_f446ze/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32F446ZE Nucleo board configuration + +# Copyright (c) 2021 Tom Owen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F446ZE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F446ZE diff --git a/boards/st/nucleo_f446ze/Kconfig.nucleo_f446ze b/boards/st/nucleo_f446ze/Kconfig.nucleo_f446ze new file mode 100644 index 00000000000..13ff942a567 --- /dev/null +++ b/boards/st/nucleo_f446ze/Kconfig.nucleo_f446ze @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Tom Owen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F446ZE + select SOC_STM32F446XX diff --git a/boards/arm/nucleo_f446ze/arduino_r3_connector.dtsi b/boards/st/nucleo_f446ze/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f446ze/arduino_r3_connector.dtsi rename to boards/st/nucleo_f446ze/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f446ze/board.cmake b/boards/st/nucleo_f446ze/board.cmake similarity index 100% rename from boards/arm/nucleo_f446ze/board.cmake rename to boards/st/nucleo_f446ze/board.cmake diff --git a/boards/st/nucleo_f446ze/board.yml b/boards/st/nucleo_f446ze/board.yml new file mode 100644 index 00000000000..eb577af456b --- /dev/null +++ b/boards/st/nucleo_f446ze/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f446ze + vendor: st + socs: + - name: stm32f446xx diff --git a/boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze.jpg b/boards/st/nucleo_f446ze/doc/img/nucleo_f446ze.jpg similarity index 100% rename from boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze.jpg rename to boards/st/nucleo_f446ze/doc/img/nucleo_f446ze.jpg diff --git a/boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_left_2019_8_29.jpg b/boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_left_2019_8_29.jpg similarity index 100% rename from boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_left_2019_8_29.jpg rename to boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_left_2019_8_29.jpg diff --git a/boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_right_2019_8_29.jpg b/boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_right_2019_8_29.jpg similarity index 100% rename from boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_right_2019_8_29.jpg rename to boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_right_2019_8_29.jpg diff --git a/boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_zio_left_2019_8_29.jpg b/boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_zio_left_2019_8_29.jpg similarity index 100% rename from boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_zio_left_2019_8_29.jpg rename to boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_zio_left_2019_8_29.jpg diff --git a/boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_zio_right_2019_8_29.jpg b/boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_zio_right_2019_8_29.jpg similarity index 100% rename from boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_zio_right_2019_8_29.jpg rename to boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_zio_right_2019_8_29.jpg diff --git a/boards/st/nucleo_f446ze/doc/index.rst b/boards/st/nucleo_f446ze/doc/index.rst new file mode 100644 index 00000000000..d99167db159 --- /dev/null +++ b/boards/st/nucleo_f446ze/doc/index.rst @@ -0,0 +1,248 @@ +.. _nucleo_f446ze_board: + +ST Nucleo F446ZE +################ + + +Overview +******** + +The Nucleo F446ZE board features an ARM Cortex-M4 based STM32F446ZE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F446ZE board: + +- STM32F446 microcontroller in QFP144 package +- Two types of extension resources: + + - ST zio support for Arduino™ Uno V3 connectivity (A0 to A5, D0 to D15) and additional signals exposing a wide range of peripherals + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- USB re-enumeration capability. Three different interfaces supported on USB: + - Virtual Com port + - Mass storage (USB Disk drive) for drag'n'drop programming + - Debug port +- Flexible board power supply: + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + - USB OTG + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f446ze.jpg + :align: center + :alt: Nucleo F446ZE + +More information about the board can be found at the `Nucleo F446ZE website`_. + +Hardware +******** + +Nucleo F446ZE provides the following hardware components: + +- STM32F446ZET6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- Adaptive real-time accelerator (ART Accelerator) +- 180 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 128 KB SRAM +- 10 General purpose timers +- 2 Advanced control timers +- 2 basic timers +- SPI(4) +- I2C(4) +- USART(4) +- UART(2) +- USB OTG Full Speed and High Speed +- CAN(2) +- SAI(2) +- SPDIF_Rx(1) +- HDMI_CEC(1) +- Quad SPI(1) +- Camera Interface +- GPIO(50) with external interrupt capability +- 12-bit ADC(3) with 16 channels +- 12-bit DAC with 2 channels + +More information about STM32F446ZE can be found here: + +- `STM32F446ZE on www.st.com`_ +- `STM32F446 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_f446ze board configuration supports the following hardware features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ +| CAN 1/2 | on-chip | Controller Area Network | ++-------------+------------+-------------------------------------+ +| ADC | on-chip | Analog Input | ++-------------+------------+-------------------------------------+ +| DAC | on-chip | Analog Output | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f446ze/nucleo_f446ze_defconfig` + + +Connections and IOs +=================== + +Nucleo F446ZE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f446ze_zio_left_2019_8_29.jpg + :align: center + :alt: Nucleo F446ZE Zio/Arduino connectors (left) +.. image:: img/nucleo_f446ze_zio_right_2019_8_29.jpg + :align: center + :alt: Nucleo F446ZE Zio/Arduino connectors (right) +.. image:: img/nucleo_f446ze_morpho_left_2019_8_29.jpg + :align: center + :alt: Nucleo F446ZE Morpho connectors (left) +.. image:: img/nucleo_f446ze_morpho_right_2019_8_29.jpg + :align: center + :alt: Nucleo F446ZE Morpho connectors (right) + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- UART_3_TX : PD8 +- UART_3_RX : PD9 +- USER_PB : PC13 +- LD0 : PB0 +- LD1 : PB7 +- LD2 : PB14 +- I2C1_SDA : PB9 +- I2C1_SCL : PB8 +- I2C2_SDA : PF0 +- I2C2_SCL : PF1 +- SPI1_CS : PD14 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 +- CAN1_RX : PD0 +- CAN1_TX : PD1 +- USB_DP : PA11 +- USB_DM : PA12 +- ADC1_IN0 : PA0 +- DAC_OUT1 : PA4 + + +System Clock +------------ + +Nucleo F446ZE System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, +driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F446ZE board has 2 UARTs and 4 USARTs. The Zephyr console output is assigned to USART3. +Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB156`` jumper on the back side of the board. + +Controller Area Network +----------------------- + +The TX/RX wires are connected with pins 25/27 of CN9 connector. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f446ze`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F446ZE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F446ZE +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f446ze + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f446ze + :maybe-skip-config: + :goals: debug + +.. _Nucleo F446ZE website: + https://www.st.com/en/evaluation-tools/nucleo-f446ze.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/um1974-stm32-nucleo144-boards-mb1137-stmicroelectronics.pdf + +.. _STM32F446ZE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f446ze.html + +.. _STM32F446 reference manual: + https://www.st.com/resource/en/reference_manual/dm00135183.pdf diff --git a/boards/arm/nucleo_f446ze/nucleo_f446ze.dts b/boards/st/nucleo_f446ze/nucleo_f446ze.dts similarity index 100% rename from boards/arm/nucleo_f446ze/nucleo_f446ze.dts rename to boards/st/nucleo_f446ze/nucleo_f446ze.dts diff --git a/boards/arm/nucleo_f446ze/nucleo_f446ze.yaml b/boards/st/nucleo_f446ze/nucleo_f446ze.yaml similarity index 100% rename from boards/arm/nucleo_f446ze/nucleo_f446ze.yaml rename to boards/st/nucleo_f446ze/nucleo_f446ze.yaml diff --git a/boards/arm/nucleo_f446ze/nucleo_f446ze_defconfig b/boards/st/nucleo_f446ze/nucleo_f446ze_defconfig similarity index 84% rename from boards/arm/nucleo_f446ze/nucleo_f446ze_defconfig rename to boards/st/nucleo_f446ze/nucleo_f446ze_defconfig index a9e0141c125..c729b83e3d0 100644 --- a/boards/arm/nucleo_f446ze/nucleo_f446ze_defconfig +++ b/boards/st/nucleo_f446ze/nucleo_f446ze_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F446XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f446ze/support/openocd.cfg b/boards/st/nucleo_f446ze/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f446ze/support/openocd.cfg rename to boards/st/nucleo_f446ze/support/openocd.cfg diff --git a/boards/st/nucleo_f722ze/Kconfig.defconfig b/boards/st/nucleo_f722ze/Kconfig.defconfig new file mode 100644 index 00000000000..475a7e465f6 --- /dev/null +++ b/boards/st/nucleo_f722ze/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32F722ZE Nucleo board configuration +# +# Copyright (c) 2023 Evan Perry Grove +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F722ZE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F722ZE diff --git a/boards/st/nucleo_f722ze/Kconfig.nucleo_f722ze b/boards/st/nucleo_f722ze/Kconfig.nucleo_f722ze new file mode 100644 index 00000000000..12cc5a5d418 --- /dev/null +++ b/boards/st/nucleo_f722ze/Kconfig.nucleo_f722ze @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Evan Perry Grove +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F722ZE + select SOC_STM32F722XX diff --git a/boards/arm/nucleo_f722ze/arduino_r3_connector.dtsi b/boards/st/nucleo_f722ze/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f722ze/arduino_r3_connector.dtsi rename to boards/st/nucleo_f722ze/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f722ze/board.cmake b/boards/st/nucleo_f722ze/board.cmake similarity index 100% rename from boards/arm/nucleo_f722ze/board.cmake rename to boards/st/nucleo_f722ze/board.cmake diff --git a/boards/st/nucleo_f722ze/board.yml b/boards/st/nucleo_f722ze/board.yml new file mode 100644 index 00000000000..793193bc2ca --- /dev/null +++ b/boards/st/nucleo_f722ze/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f722ze + vendor: st + socs: + - name: stm32f722xx diff --git a/boards/arm/nucleo_f722ze/doc/img/nucleo_f722ze.jpg b/boards/st/nucleo_f722ze/doc/img/nucleo_f722ze.jpg similarity index 100% rename from boards/arm/nucleo_f722ze/doc/img/nucleo_f722ze.jpg rename to boards/st/nucleo_f722ze/doc/img/nucleo_f722ze.jpg diff --git a/boards/arm/nucleo_f722ze/doc/index.rst b/boards/st/nucleo_f722ze/doc/index.rst similarity index 100% rename from boards/arm/nucleo_f722ze/doc/index.rst rename to boards/st/nucleo_f722ze/doc/index.rst diff --git a/boards/arm/nucleo_f722ze/nucleo_f722ze.dts b/boards/st/nucleo_f722ze/nucleo_f722ze.dts similarity index 100% rename from boards/arm/nucleo_f722ze/nucleo_f722ze.dts rename to boards/st/nucleo_f722ze/nucleo_f722ze.dts diff --git a/boards/arm/nucleo_f722ze/nucleo_f722ze.yaml b/boards/st/nucleo_f722ze/nucleo_f722ze.yaml similarity index 100% rename from boards/arm/nucleo_f722ze/nucleo_f722ze.yaml rename to boards/st/nucleo_f722ze/nucleo_f722ze.yaml diff --git a/boards/arm/nucleo_f722ze/nucleo_f722ze_defconfig b/boards/st/nucleo_f722ze/nucleo_f722ze_defconfig similarity index 86% rename from boards/arm/nucleo_f722ze/nucleo_f722ze_defconfig rename to boards/st/nucleo_f722ze/nucleo_f722ze_defconfig index 345694efd80..86e44f22e55 100644 --- a/boards/arm/nucleo_f722ze/nucleo_f722ze_defconfig +++ b/boards/st/nucleo_f722ze/nucleo_f722ze_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F722XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f722ze/support/openocd.cfg b/boards/st/nucleo_f722ze/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f722ze/support/openocd.cfg rename to boards/st/nucleo_f722ze/support/openocd.cfg diff --git a/boards/st/nucleo_f746zg/Kconfig.defconfig b/boards/st/nucleo_f746zg/Kconfig.defconfig new file mode 100644 index 00000000000..7cf77f7d6f0 --- /dev/null +++ b/boards/st/nucleo_f746zg/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32F746ZG Nucleo board configuration + +# Copyright (c) 2018 AJ Palmer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F746ZG + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F746ZG diff --git a/boards/st/nucleo_f746zg/Kconfig.nucleo_f746zg b/boards/st/nucleo_f746zg/Kconfig.nucleo_f746zg new file mode 100644 index 00000000000..89bf9f55bbe --- /dev/null +++ b/boards/st/nucleo_f746zg/Kconfig.nucleo_f746zg @@ -0,0 +1,5 @@ +# Copyright (c) 2018 AJ Palmer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F746ZG + select SOC_STM32F746XX diff --git a/boards/arm/nucleo_f746zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f746zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f746zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_f746zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f746zg/board.cmake b/boards/st/nucleo_f746zg/board.cmake similarity index 100% rename from boards/arm/nucleo_f746zg/board.cmake rename to boards/st/nucleo_f746zg/board.cmake diff --git a/boards/st/nucleo_f746zg/board.yml b/boards/st/nucleo_f746zg/board.yml new file mode 100644 index 00000000000..1df68107ece --- /dev/null +++ b/boards/st/nucleo_f746zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f746zg + vendor: st + socs: + - name: stm32f746xx diff --git a/boards/arm/nucleo_f746zg/doc/img/nucleo_f746zg.jpg b/boards/st/nucleo_f746zg/doc/img/nucleo_f746zg.jpg similarity index 100% rename from boards/arm/nucleo_f746zg/doc/img/nucleo_f746zg.jpg rename to boards/st/nucleo_f746zg/doc/img/nucleo_f746zg.jpg diff --git a/boards/st/nucleo_f746zg/doc/index.rst b/boards/st/nucleo_f746zg/doc/index.rst new file mode 100644 index 00000000000..cc1ca6d95ed --- /dev/null +++ b/boards/st/nucleo_f746zg/doc/index.rst @@ -0,0 +1,235 @@ +.. _nucleo_f746zg_board: + +ST Nucleo F746ZG +################ + +Overview +******** + +The STM32 Nucleo-144 boards offer combinations of performance and power that +provide an affordable and flexible way for users to build prototypes and try +out new concepts. For compatible boards, the SMPS significantly reduces power +consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V2-1 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_f746zg.jpg + :align: center + :alt: Nucleo F746ZG + +More information about the board can be found at the `Nucleo F746ZG website`_. + +Hardware +******** + +Nucleo F746ZG provides the following hardware components: + +- STM32F746ZG in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- ART Accelerator +- 216 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1 MB Flash +- 320 KB SRAM +- 16-bit timers(10) +- 32-bit timers(2) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO(up to 168) with external interrupt capability +- 12-bit ADC(3) with 24 channels / 2.4 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_f746zg board configuration supports the following hardware +features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-------------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-------------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-------------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-------------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f746zg/nucleo_f746zg_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F746ZG board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino UART) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- USB DM : PA11 +- USB DP : PA12 +- I2C : PB8, PB9 +- PWM : PE13 +- SPI : PD14, PA5, PA6, PA7 +- ADC1_IN0 : PA0 +- DAC1_OUT1 : PA4 + +Note. The Arduino Uno v3 specified SPI device conflicts with the on-board ETH +device on pin PA7. + +System Clock +------------ + +Nucleo F746ZG System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F746ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB156`` jumper on the back side of the board. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f746zg`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F746ZG board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo F746ZG +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f746zg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_f746zg + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f746zg + :maybe-skip-config: + :goals: debug + +.. _Nucleo F746ZG website: + https://www.st.com/en/evaluation-tools/nucleo-f746zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32F746ZG on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f746zg.html + +.. _STM32F746 reference manual: + https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/nucleo_f746zg/nucleo_f746zg.dts b/boards/st/nucleo_f746zg/nucleo_f746zg.dts similarity index 100% rename from boards/arm/nucleo_f746zg/nucleo_f746zg.dts rename to boards/st/nucleo_f746zg/nucleo_f746zg.dts diff --git a/boards/arm/nucleo_f746zg/nucleo_f746zg.yaml b/boards/st/nucleo_f746zg/nucleo_f746zg.yaml similarity index 100% rename from boards/arm/nucleo_f746zg/nucleo_f746zg.yaml rename to boards/st/nucleo_f746zg/nucleo_f746zg.yaml diff --git a/boards/arm/nucleo_f746zg/nucleo_f746zg_defconfig b/boards/st/nucleo_f746zg/nucleo_f746zg_defconfig similarity index 85% rename from boards/arm/nucleo_f746zg/nucleo_f746zg_defconfig rename to boards/st/nucleo_f746zg/nucleo_f746zg_defconfig index e1eb901f61c..261e47c2d53 100644 --- a/boards/arm/nucleo_f746zg/nucleo_f746zg_defconfig +++ b/boards/st/nucleo_f746zg/nucleo_f746zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F746XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f746zg/support/openocd.cfg b/boards/st/nucleo_f746zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f746zg/support/openocd.cfg rename to boards/st/nucleo_f746zg/support/openocd.cfg diff --git a/boards/st/nucleo_f756zg/Kconfig.defconfig b/boards/st/nucleo_f756zg/Kconfig.defconfig new file mode 100644 index 00000000000..4ca0a6ee3a0 --- /dev/null +++ b/boards/st/nucleo_f756zg/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32F756ZG Nucleo board configuration + +# Copyright (c) 2018 AJ Palmer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F756ZG + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F756ZG diff --git a/boards/st/nucleo_f756zg/Kconfig.nucleo_f756zg b/boards/st/nucleo_f756zg/Kconfig.nucleo_f756zg new file mode 100644 index 00000000000..3f8154cdebc --- /dev/null +++ b/boards/st/nucleo_f756zg/Kconfig.nucleo_f756zg @@ -0,0 +1,5 @@ +# Copyright (c) 2018 AJ Palmer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F756ZG + select SOC_STM32F756XX diff --git a/boards/arm/nucleo_f756zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f756zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f756zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_f756zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f756zg/board.cmake b/boards/st/nucleo_f756zg/board.cmake similarity index 100% rename from boards/arm/nucleo_f756zg/board.cmake rename to boards/st/nucleo_f756zg/board.cmake diff --git a/boards/st/nucleo_f756zg/board.yml b/boards/st/nucleo_f756zg/board.yml new file mode 100644 index 00000000000..791d7601754 --- /dev/null +++ b/boards/st/nucleo_f756zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f756zg + vendor: st + socs: + - name: stm32f756xx diff --git a/boards/arm/nucleo_f756zg/doc/img/nucleo_f756zg.jpg b/boards/st/nucleo_f756zg/doc/img/nucleo_f756zg.jpg similarity index 100% rename from boards/arm/nucleo_f756zg/doc/img/nucleo_f756zg.jpg rename to boards/st/nucleo_f756zg/doc/img/nucleo_f756zg.jpg diff --git a/boards/st/nucleo_f756zg/doc/index.rst b/boards/st/nucleo_f756zg/doc/index.rst new file mode 100644 index 00000000000..fd8b5f259c3 --- /dev/null +++ b/boards/st/nucleo_f756zg/doc/index.rst @@ -0,0 +1,218 @@ +.. _nucleo_f756zg_board: + +ST Nucleo F756ZG +################ + +Overview +******** + +The STM32 Nucleo-144 boards offer combinations of performance and power that +provide an affordable and flexible way for users to build prototypes and try +out new concepts. For compatible boards, the SMPS significantly reduces power +consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V2-1 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration + capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the +- STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_f756zg.jpg + :align: center + :alt: Nucleo F756ZG + +More information about the board can be found at the `Nucleo F756ZG website`_. + +Hardware +******** + +Nucleo F756ZG provides the following hardware components: + +- STM32F756ZG in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- ART Accelerator +- 216 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1 MB Flash +- 320 KB SRAM +- 16-bit timers(10) +- 32-bit timers(2) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO(up to 168) with external interrupt capability +- 12-bit ADC(3) with 24 channels / 2.4 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_f756zg board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f756zg/nucleo_f756zg_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F756ZG board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino UART) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- USB DM : PA11 +- USB DP : PA12 +- I2C : PB8, PB9 +- PWM : PE13 +- SPI : PD14, PA5, PA6, PA7 + +Note. The Arduino Uno v3 specified SPI device conflicts with the on-board ETH +device on pin PA7. + +System Clock +------------ + +Nucleo F756ZG System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F756ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_f756zg`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F756ZG board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo F756ZG +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f756zg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_f756zg + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f756zg + :maybe-skip-config: + :goals: debug + +.. _Nucleo F756ZG website: + https://www.st.com/en/evaluation-tools/nucleo-f756zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F756ZG on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f756zg.html + +.. _STM32F756 reference manual: + https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/nucleo_f756zg/nucleo_f756zg.dts b/boards/st/nucleo_f756zg/nucleo_f756zg.dts similarity index 100% rename from boards/arm/nucleo_f756zg/nucleo_f756zg.dts rename to boards/st/nucleo_f756zg/nucleo_f756zg.dts diff --git a/boards/arm/nucleo_f756zg/nucleo_f756zg.yaml b/boards/st/nucleo_f756zg/nucleo_f756zg.yaml similarity index 100% rename from boards/arm/nucleo_f756zg/nucleo_f756zg.yaml rename to boards/st/nucleo_f756zg/nucleo_f756zg.yaml diff --git a/boards/arm/nucleo_f756zg/nucleo_f756zg_defconfig b/boards/st/nucleo_f756zg/nucleo_f756zg_defconfig similarity index 85% rename from boards/arm/nucleo_f756zg/nucleo_f756zg_defconfig rename to boards/st/nucleo_f756zg/nucleo_f756zg_defconfig index 6f89a9784b9..261e47c2d53 100644 --- a/boards/arm/nucleo_f756zg/nucleo_f756zg_defconfig +++ b/boards/st/nucleo_f756zg/nucleo_f756zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F756XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f756zg/support/openocd.cfg b/boards/st/nucleo_f756zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f756zg/support/openocd.cfg rename to boards/st/nucleo_f756zg/support/openocd.cfg diff --git a/boards/st/nucleo_f767zi/Kconfig.defconfig b/boards/st/nucleo_f767zi/Kconfig.defconfig new file mode 100644 index 00000000000..45850f2d06d --- /dev/null +++ b/boards/st/nucleo_f767zi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32F767ZI Nucleo board configuration + +# Copyright (c) 2019 Roland Ma +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F767ZI + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F767ZI diff --git a/boards/st/nucleo_f767zi/Kconfig.nucleo_f767zi b/boards/st/nucleo_f767zi/Kconfig.nucleo_f767zi new file mode 100644 index 00000000000..e14bf165a8f --- /dev/null +++ b/boards/st/nucleo_f767zi/Kconfig.nucleo_f767zi @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Roland Ma +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F767ZI + select SOC_STM32F767XX diff --git a/boards/arm/nucleo_f767zi/arduino_r3_connector.dtsi b/boards/st/nucleo_f767zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f767zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_f767zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f767zi/board.cmake b/boards/st/nucleo_f767zi/board.cmake similarity index 100% rename from boards/arm/nucleo_f767zi/board.cmake rename to boards/st/nucleo_f767zi/board.cmake diff --git a/boards/st/nucleo_f767zi/board.yml b/boards/st/nucleo_f767zi/board.yml new file mode 100644 index 00000000000..810b80a5fdc --- /dev/null +++ b/boards/st/nucleo_f767zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f767zi + vendor: st + socs: + - name: stm32f767xx diff --git a/boards/arm/nucleo_f767zi/doc/img/nucleo_f767zi.jpg b/boards/st/nucleo_f767zi/doc/img/nucleo_f767zi.jpg similarity index 100% rename from boards/arm/nucleo_f767zi/doc/img/nucleo_f767zi.jpg rename to boards/st/nucleo_f767zi/doc/img/nucleo_f767zi.jpg diff --git a/boards/st/nucleo_f767zi/doc/index.rst b/boards/st/nucleo_f767zi/doc/index.rst new file mode 100644 index 00000000000..8500f7fd3f1 --- /dev/null +++ b/boards/st/nucleo_f767zi/doc/index.rst @@ -0,0 +1,236 @@ +.. _nucleo_f767zi_board: + +ST Nucleo F767ZI +################ + +Overview +******** + +The STM32 Nucleo-144 F767ZI boards offer combinations of performance and +power that provide an affordable and flexible way for users to build +prototypes and try out new concepts. For compatible boards, the SMPS +significantly reduces power consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V2-1 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_f767zi.jpg + :align: center + :alt: Nucleo F767ZI + +More information about the board can be found at the `Nucleo F767ZI website`_. + +Hardware +******** + +Nucleo F767ZI provides the following hardware components: + +- STM32F767ZI in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- ART Accelerator +- 216 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 2 MB Flash +- 512 KB SRAM +- 16-bit timers(10) +- 32-bit timers(2) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO(up to 168) with external interrupt capability +- 12-bit ADC(3) with 24 channels / 2.4 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_f767zi board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet (*) | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ + + +(*) nucleo_f767zi with soc cut-A (Device marking A) has some ethernet + instability (:github:`26519`). + Use of cut-Z is advised. + see restrictions errata: + https://www.st.com/content/ccc/resource/technical/document/errata_sheet/group0/23/a6/11/0b/30/24/46/a5/DM00257543/files/DM00257543.pdf/jcr:content/translations/en.DM00257543.pdf + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f767zi/nucleo_f767zi_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F767ZI board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino UART) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- USB DM : PA11 +- USB DP : PA12 +- I2C : PB8, PB9 +- PWM : PE13 +- SPI : PD14, PA5, PA6, PA7 + +.. note:: + The Arduino Uno v3 specified SPI device conflicts with the on-board ETH + device on pin PA7. + +System Clock +------------ + +Nucleo F767ZI System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F767ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_f767zi`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F767ZI board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo F767ZI +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f767zi + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_f767zi + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f767zi + :maybe-skip-config: + :goals: debug + +.. _Nucleo f767zi website: + https://www.st.com/en/evaluation-tools/nucleo-f767zi.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32f767zi on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x&/stm32f767zi.html + +.. _STM32F767 reference manual: + https://www.st.com/resource/en/reference_manual/DM00224583.pdf diff --git a/boards/arm/nucleo_f767zi/nucleo_f767zi.dts b/boards/st/nucleo_f767zi/nucleo_f767zi.dts similarity index 100% rename from boards/arm/nucleo_f767zi/nucleo_f767zi.dts rename to boards/st/nucleo_f767zi/nucleo_f767zi.dts diff --git a/boards/arm/nucleo_f767zi/nucleo_f767zi.yaml b/boards/st/nucleo_f767zi/nucleo_f767zi.yaml similarity index 100% rename from boards/arm/nucleo_f767zi/nucleo_f767zi.yaml rename to boards/st/nucleo_f767zi/nucleo_f767zi.yaml diff --git a/boards/arm/nucleo_f767zi/nucleo_f767zi_defconfig b/boards/st/nucleo_f767zi/nucleo_f767zi_defconfig similarity index 85% rename from boards/arm/nucleo_f767zi/nucleo_f767zi_defconfig rename to boards/st/nucleo_f767zi/nucleo_f767zi_defconfig index df549434139..261e47c2d53 100644 --- a/boards/arm/nucleo_f767zi/nucleo_f767zi_defconfig +++ b/boards/st/nucleo_f767zi/nucleo_f767zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F767XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f767zi/support/openocd.cfg b/boards/st/nucleo_f767zi/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f767zi/support/openocd.cfg rename to boards/st/nucleo_f767zi/support/openocd.cfg diff --git a/boards/st/nucleo_g031k8/Kconfig.defconfig b/boards/st/nucleo_g031k8/Kconfig.defconfig new file mode 100644 index 00000000000..2c6c84ed50d --- /dev/null +++ b/boards/st/nucleo_g031k8/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-32 development board with STM32G031K8 MCU + +# Copyright (c) 2022 Joylab AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_G031K8 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_G031K8 diff --git a/boards/st/nucleo_g031k8/Kconfig.nucleo_g031k8 b/boards/st/nucleo_g031k8/Kconfig.nucleo_g031k8 new file mode 100644 index 00000000000..b748af9991d --- /dev/null +++ b/boards/st/nucleo_g031k8/Kconfig.nucleo_g031k8 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Joylab AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G031K8 + select SOC_STM32G031XX diff --git a/boards/arm/nucleo_g031k8/arduino_nano_r3_connector.dtsi b/boards/st/nucleo_g031k8/arduino_nano_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g031k8/arduino_nano_r3_connector.dtsi rename to boards/st/nucleo_g031k8/arduino_nano_r3_connector.dtsi diff --git a/boards/arm/nucleo_g031k8/board.cmake b/boards/st/nucleo_g031k8/board.cmake similarity index 100% rename from boards/arm/nucleo_g031k8/board.cmake rename to boards/st/nucleo_g031k8/board.cmake diff --git a/boards/st/nucleo_g031k8/board.yml b/boards/st/nucleo_g031k8/board.yml new file mode 100644 index 00000000000..690afd52fb0 --- /dev/null +++ b/boards/st/nucleo_g031k8/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g031k8 + vendor: st + socs: + - name: stm32g031xx diff --git a/boards/arm/nucleo_g031k8/doc/img/nucleo_g031k8.jpg b/boards/st/nucleo_g031k8/doc/img/nucleo_g031k8.jpg similarity index 100% rename from boards/arm/nucleo_g031k8/doc/img/nucleo_g031k8.jpg rename to boards/st/nucleo_g031k8/doc/img/nucleo_g031k8.jpg diff --git a/boards/st/nucleo_g031k8/doc/index.rst b/boards/st/nucleo_g031k8/doc/index.rst new file mode 100644 index 00000000000..e140ac74040 --- /dev/null +++ b/boards/st/nucleo_g031k8/doc/index.rst @@ -0,0 +1,168 @@ +.. _nucleo_g031k8_board: + +ST Nucleo G031K8 +################ + +Overview +******** +The STM32 Nucleo-32 board provides an affordable and flexible way for users to try +out new concepts and build prototypes by choosing from the various combinations of +performance and power consumption features, provided by the STM32 +microcontroller. + +The Arduino™ Nano V3 connectivity support allows the easy expansion of the +functionality of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo-32 board does not require any separate probe as it integrates the +ST-LINK debugger/programmer. + +The STM32 Nucleo-32 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + + +.. image:: img/nucleo_g031k8.jpg + :align: center + :alt: Nucleo G031K8 + +More information about the board can be found at the `Nucleo G031K8 website`_. + +Hardware +******** +Nucleo G031K8 provides the following hardware components: + +- STM32 microcontroller in 32-pin package featuring 64 Kbytes of Flash memory + and 8 Kbytes of SRAM. +- Extension resource: + + - Arduino* Nano V3 connectivity + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Current consumption measurement (IDD) + +- Four LEDs: + + - USB communication (LD1), power LED (LD2), user LED (LD3), + USB power fault LED (LD4) + +- One push-button: RESET + +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +More information about STM32G031K8 can be found in the +`STM32G0x1 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_g031k8 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g031k8/nucleo_g031k8_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C2 SCL/SDA : PA9/PA10 (Arduino I2C) +- SPI1 SCK/MISO/MOSI : PB3/PB4/PB5 (Arduino SPI) +- LD3 : PC6 + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g031k8`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G031K8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo G031K8 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_g031k8 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g031k8 + :maybe-skip-config: + :goals: debug + +Restriction +*********** + +On some boards, the board reset line is not used by the controller. +Therefore the reset button, reset-pin and the ST-Link reset have no effect. +To enable those functionalities, the option byte NRST_mode in the User +Configuration needs to be changed from 2 to 1 or 3 - depending on the +requirements. + +References +********** + +.. target-notes:: + +.. _Nucleo G031K8 website: + https://www.st.com/en/evaluation-tools/nucleo-g031k8.html + +.. _STM32G0x1 reference manual: + https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/um2591-stm32g0-nucleo32-board-mb1455-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_g031k8/nucleo_g031k8.dts b/boards/st/nucleo_g031k8/nucleo_g031k8.dts similarity index 100% rename from boards/arm/nucleo_g031k8/nucleo_g031k8.dts rename to boards/st/nucleo_g031k8/nucleo_g031k8.dts diff --git a/boards/arm/nucleo_g031k8/nucleo_g031k8.yaml b/boards/st/nucleo_g031k8/nucleo_g031k8.yaml similarity index 100% rename from boards/arm/nucleo_g031k8/nucleo_g031k8.yaml rename to boards/st/nucleo_g031k8/nucleo_g031k8.yaml diff --git a/boards/arm/nucleo_g031k8/nucleo_g031k8_defconfig b/boards/st/nucleo_g031k8/nucleo_g031k8_defconfig similarity index 78% rename from boards/arm/nucleo_g031k8/nucleo_g031k8_defconfig rename to boards/st/nucleo_g031k8/nucleo_g031k8_defconfig index e4a8706b596..06484e88bea 100644 --- a/boards/arm/nucleo_g031k8/nucleo_g031k8_defconfig +++ b/boards/st/nucleo_g031k8/nucleo_g031k8_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32G0X=y - -# Platform Configuration -CONFIG_SOC_STM32G031XX=y - # Kernel Options due to Low Memory (8k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/arm/nucleo_g031k8/support/openocd.cfg b/boards/st/nucleo_g031k8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g031k8/support/openocd.cfg rename to boards/st/nucleo_g031k8/support/openocd.cfg diff --git a/boards/st/nucleo_g070rb/Kconfig.nucleo_g070rb b/boards/st/nucleo_g070rb/Kconfig.nucleo_g070rb new file mode 100644 index 00000000000..0465a3f4273 --- /dev/null +++ b/boards/st/nucleo_g070rb/Kconfig.nucleo_g070rb @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Marin Jurjević +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G070RB + select SOC_STM32G070XX diff --git a/boards/arm/nucleo_g070rb/arduino_r3_connector.dtsi b/boards/st/nucleo_g070rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g070rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_g070rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_g070rb/board.cmake b/boards/st/nucleo_g070rb/board.cmake similarity index 100% rename from boards/arm/nucleo_g070rb/board.cmake rename to boards/st/nucleo_g070rb/board.cmake diff --git a/boards/st/nucleo_g070rb/board.yml b/boards/st/nucleo_g070rb/board.yml new file mode 100644 index 00000000000..88306b0d7f0 --- /dev/null +++ b/boards/st/nucleo_g070rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g070rb + vendor: st + socs: + - name: stm32g070xx diff --git a/boards/arm/nucleo_g070rb/doc/img/nucleo_g070rb.jpg b/boards/st/nucleo_g070rb/doc/img/nucleo_g070rb.jpg similarity index 100% rename from boards/arm/nucleo_g070rb/doc/img/nucleo_g070rb.jpg rename to boards/st/nucleo_g070rb/doc/img/nucleo_g070rb.jpg diff --git a/boards/st/nucleo_g070rb/doc/index.rst b/boards/st/nucleo_g070rb/doc/index.rst new file mode 100644 index 00000000000..b18525ee0eb --- /dev/null +++ b/boards/st/nucleo_g070rb/doc/index.rst @@ -0,0 +1,191 @@ +.. _nucleo_g070rb_board: + +ST Nucleo G070RB +################ + +Overview +******** +The Nucleo G070RB board features an ARM Cortex-M0+ based STM32G070RB MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo G070RB board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_g070rb.jpg + :align: center + :alt: Nucleo G070RB + +More information about the board can be found at the `Nucleo G070RB website`_. + +Hardware +******** +Nucleo G070RB provides the following hardware components: + +- STM32 microcontroller in LQFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD4), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32G070RB can be found here: + +- `G070RB on www.st.com`_ + +Supported Features +================== + +The Zephyr nucleo_g070rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | arm memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g070rb/nucleo_g070rb_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PC4/PC5 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PA11/PA12 +- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) +- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- USER_PB : PC13 +- LD4 : PA5 +- PWM : PA6 +- ADC1 IN0 : PA0 +- ADC1 IN1 : PA1 +- DAC1_OUT1 : PA4 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g070rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G070RB board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo G070RB +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_g070rb + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g070rb + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo G070RB website: + https://www.st.com/en/evaluation-tools/nucleo-g070rb.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00452640.pdf + +.. _G070RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32g070rb.html diff --git a/boards/arm/nucleo_g070rb/nucleo_g070rb.dts b/boards/st/nucleo_g070rb/nucleo_g070rb.dts similarity index 100% rename from boards/arm/nucleo_g070rb/nucleo_g070rb.dts rename to boards/st/nucleo_g070rb/nucleo_g070rb.dts diff --git a/boards/arm/nucleo_g070rb/nucleo_g070rb.yaml b/boards/st/nucleo_g070rb/nucleo_g070rb.yaml similarity index 100% rename from boards/arm/nucleo_g070rb/nucleo_g070rb.yaml rename to boards/st/nucleo_g070rb/nucleo_g070rb.yaml diff --git a/boards/arm/nucleo_g070rb/nucleo_g070rb_defconfig b/boards/st/nucleo_g070rb/nucleo_g070rb_defconfig similarity index 75% rename from boards/arm/nucleo_g070rb/nucleo_g070rb_defconfig rename to boards/st/nucleo_g070rb/nucleo_g070rb_defconfig index cf5cff7fe61..0055481a2e8 100644 --- a/boards/arm/nucleo_g070rb/nucleo_g070rb_defconfig +++ b/boards/st/nucleo_g070rb/nucleo_g070rb_defconfig @@ -1,7 +1,3 @@ -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G070XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_g070rb/support/openocd.cfg b/boards/st/nucleo_g070rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g070rb/support/openocd.cfg rename to boards/st/nucleo_g070rb/support/openocd.cfg diff --git a/boards/st/nucleo_g071rb/Kconfig.nucleo_g071rb b/boards/st/nucleo_g071rb/Kconfig.nucleo_g071rb new file mode 100644 index 00000000000..4237b458f47 --- /dev/null +++ b/boards/st/nucleo_g071rb/Kconfig.nucleo_g071rb @@ -0,0 +1,5 @@ +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G071RB + select SOC_STM32G071XX diff --git a/boards/arm/nucleo_g071rb/arduino_r3_connector.dtsi b/boards/st/nucleo_g071rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g071rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_g071rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_g071rb/board.cmake b/boards/st/nucleo_g071rb/board.cmake similarity index 100% rename from boards/arm/nucleo_g071rb/board.cmake rename to boards/st/nucleo_g071rb/board.cmake diff --git a/boards/st/nucleo_g071rb/board.yml b/boards/st/nucleo_g071rb/board.yml new file mode 100644 index 00000000000..05e948a2f36 --- /dev/null +++ b/boards/st/nucleo_g071rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g071rb + vendor: st + socs: + - name: stm32g071xx diff --git a/boards/arm/nucleo_g071rb/doc/img/nucleo_g071rb.jpg b/boards/st/nucleo_g071rb/doc/img/nucleo_g071rb.jpg similarity index 100% rename from boards/arm/nucleo_g071rb/doc/img/nucleo_g071rb.jpg rename to boards/st/nucleo_g071rb/doc/img/nucleo_g071rb.jpg diff --git a/boards/st/nucleo_g071rb/doc/index.rst b/boards/st/nucleo_g071rb/doc/index.rst new file mode 100644 index 00000000000..9cc78b0f4c8 --- /dev/null +++ b/boards/st/nucleo_g071rb/doc/index.rst @@ -0,0 +1,198 @@ +.. _nucleo_g071rb_board: + +ST Nucleo G071RB +################ + +Overview +******** +The Nucleo G071RB board features an ARM Cortex-M0+ based STM32G071RB MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo G071RB board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_g071rb.jpg + :align: center + :alt: Nucleo G071RB + +More information about the board can be found at the `Nucleo G071RB website`_. + +Hardware +******** +Nucleo G071RB provides the following hardware components: + +- STM32 microcontroller in LQFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD4), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32G071RB can be found here: + +- `G071RB on www.st.com`_ +- `STM32G071 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_g071rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | arm memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g071rb/nucleo_g071rb_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PC4/PC5 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PA11/PA12 +- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) +- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- USER_PB : PC13 +- LD4 : PA5 +- PWM : PA6 +- ADC1 IN0 : PA0 +- ADC1 IN1 : PA1 +- DAC1_OUT1 : PA4 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g071rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G071RB board includes an ST-LINK/V3 embedded debug tool interface. + +Flashing an application to Nucleo G071RB +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_g071rb + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g071rb + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo G071RB website: + https://www.st.com/en/evaluation-tools/nucleo-g071rb.html + +.. _STM32G071 reference manual: + https://www.st.com/resource/en/reference_manual/dm00371828.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00452640.pdf + +.. _G071RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32g071rb.html diff --git a/boards/arm/nucleo_g071rb/nucleo_g071rb.dts b/boards/st/nucleo_g071rb/nucleo_g071rb.dts similarity index 100% rename from boards/arm/nucleo_g071rb/nucleo_g071rb.dts rename to boards/st/nucleo_g071rb/nucleo_g071rb.dts diff --git a/boards/arm/nucleo_g071rb/nucleo_g071rb.yaml b/boards/st/nucleo_g071rb/nucleo_g071rb.yaml similarity index 100% rename from boards/arm/nucleo_g071rb/nucleo_g071rb.yaml rename to boards/st/nucleo_g071rb/nucleo_g071rb.yaml diff --git a/boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig b/boards/st/nucleo_g071rb/nucleo_g071rb_defconfig similarity index 75% rename from boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig rename to boards/st/nucleo_g071rb/nucleo_g071rb_defconfig index 71cc51e4ffc..0055481a2e8 100644 --- a/boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig +++ b/boards/st/nucleo_g071rb/nucleo_g071rb_defconfig @@ -1,7 +1,3 @@ -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G071XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_g071rb/support/openocd.cfg b/boards/st/nucleo_g071rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g071rb/support/openocd.cfg rename to boards/st/nucleo_g071rb/support/openocd.cfg diff --git a/boards/st/nucleo_g0b1re/Kconfig.nucleo_g0b1re b/boards/st/nucleo_g0b1re/Kconfig.nucleo_g0b1re new file mode 100644 index 00000000000..05d7b4b1862 --- /dev/null +++ b/boards/st/nucleo_g0b1re/Kconfig.nucleo_g0b1re @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G0B1RE + select SOC_STM32G0B1XX diff --git a/boards/arm/nucleo_g0b1re/arduino_r3_connector.dtsi b/boards/st/nucleo_g0b1re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g0b1re/arduino_r3_connector.dtsi rename to boards/st/nucleo_g0b1re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_g0b1re/board.cmake b/boards/st/nucleo_g0b1re/board.cmake similarity index 100% rename from boards/arm/nucleo_g0b1re/board.cmake rename to boards/st/nucleo_g0b1re/board.cmake diff --git a/boards/st/nucleo_g0b1re/board.yml b/boards/st/nucleo_g0b1re/board.yml new file mode 100644 index 00000000000..b9d0f93261f --- /dev/null +++ b/boards/st/nucleo_g0b1re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g0b1re + vendor: st + socs: + - name: stm32g0b1xx diff --git a/boards/arm/nucleo_g0b1re/doc/img/nucleo_g0b1re.jpg b/boards/st/nucleo_g0b1re/doc/img/nucleo_g0b1re.jpg similarity index 100% rename from boards/arm/nucleo_g0b1re/doc/img/nucleo_g0b1re.jpg rename to boards/st/nucleo_g0b1re/doc/img/nucleo_g0b1re.jpg diff --git a/boards/st/nucleo_g0b1re/doc/index.rst b/boards/st/nucleo_g0b1re/doc/index.rst new file mode 100644 index 00000000000..b283d6d3d1f --- /dev/null +++ b/boards/st/nucleo_g0b1re/doc/index.rst @@ -0,0 +1,211 @@ +.. _nucleo_g0b1re_board: + +ST Nucleo G0B1RE +################ + +Overview +******** +The Nucleo G0B1RE board features an ARM Cortex-M0+ based STM32G0B1RE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo G0B1RE board: + +- STM32 microcontroller in QFP64 package +- Board connectors: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5V_USB_STLK from ST-Link USB connector + - VIN (7 - 12V) from ARDUINO connector or ST morpho connector + - E5V from ST morpho connector + - 5V_USB_CHG from ST-LINK USB connector + - 3.3V on ARDUINO connector or ST morpho connector + +- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) +- Two push-buttons: USER and RESET +- 32.768 kHz crystal oscillator + +.. image:: img/nucleo_g0b1re.jpg + :align: center + :alt: Nucleo G0B1RE + +More information about the board can be found at the `Nucleo G0B1RE website`_. + +Hardware +******** +Nucleo G0B1RE provides the following hardware components: + +- STM32G0B1RE in LQFP64 package +- ARM 32-bit Cortex-M0+ CPU +- 64 MHz max CPU frequency +- Voltage range from 1.7 V to 3.6 V +- 512 KB Flash +- 144 kB SRAM +- 32-bit timers(1) +- 16-bit timers(11) +- watchdogs(2) +- systick(1) +- Calendar RTC with alarm and periodic wakeup +- I2C(3) +- USART(6) +- LPUART(2) +- 32 Mbit/s SPI(3) multiplexed with I2S(2) +- HDMI_CEC(1) +- USB 2.0 FS device (crystal-less) and host controller(1) +- USB Type-C Power Delivery controller +- CAN FD(2) +- GPIO (up to 94) with external interrupt capability +- Tamper Pins(3) +- 12-bit ADC with 16 channels +- 12-bit DAC with 2 channels(2) +- Analog Comparator(3) +- 12-channel DMA + + +More information about STM32G0B1RE can be found here: + +- `G0B1RE on www.st.com`_ +- `STM32G0B1 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_g0b1re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | arm memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ +| FDCAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PC4/PC5 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PA11/PA12 +- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) +- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- USER_PB : PC13 +- LD4 : PA5 +- PWM : PA6 +- ADC1 IN0 : PA0 +- ADC1 IN1 : PA1 +- DAC1_OUT1 : PA4 +- FDCAN1 RX/TX: PA11/PA12 +- FDCAN2 RX/TX: PB0/PB1 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g0b1re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G0B1RE board includes an ST-LINK/V2-1 embedded debug tool interface. + +This interface is not yet supported by the openocd version included in the Zephyr SDK. +But JLink, STM32CubeProgrammer and Pyocd interfaces are supported. +Pyocd support is currently limited: As the stm32g0b1 target causes issues, +the stm32g071 target is used. For STM32G0 support pyocd needs additional target +information, which can be installed by adding "pack" support with the +following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32g0 + + +Flashing an application to Nucleo G0B1RE +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_g0b1re + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g0b1re + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo G0B1RE website: + https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html + +.. _STM32G0B1 reference manual: + https://www.st.com/resource/en/reference_manual/dm00371828.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00452640.pdf + +.. _G0B1RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32g0b1re.html diff --git a/boards/arm/nucleo_g0b1re/nucleo_g0b1re.dts b/boards/st/nucleo_g0b1re/nucleo_g0b1re.dts similarity index 100% rename from boards/arm/nucleo_g0b1re/nucleo_g0b1re.dts rename to boards/st/nucleo_g0b1re/nucleo_g0b1re.dts diff --git a/boards/arm/nucleo_g0b1re/nucleo_g0b1re.yaml b/boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml similarity index 100% rename from boards/arm/nucleo_g0b1re/nucleo_g0b1re.yaml rename to boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml diff --git a/boards/arm/nucleo_g0b1re/nucleo_g0b1re_defconfig b/boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig similarity index 75% rename from boards/arm/nucleo_g0b1re/nucleo_g0b1re_defconfig rename to boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig index c57537f7c31..84d7129fd51 100644 --- a/boards/arm/nucleo_g0b1re/nucleo_g0b1re_defconfig +++ b/boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig @@ -1,7 +1,3 @@ -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G0B1XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_g0b1re/support/openocd.cfg b/boards/st/nucleo_g0b1re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g0b1re/support/openocd.cfg rename to boards/st/nucleo_g0b1re/support/openocd.cfg diff --git a/boards/st/nucleo_g431rb/Kconfig.defconfig b/boards/st/nucleo_g431rb/Kconfig.defconfig new file mode 100644 index 00000000000..9d0323049ba --- /dev/null +++ b/boards/st/nucleo_g431rb/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32G431RB Nucleo board configuration + +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_G431RB + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_G431RB diff --git a/boards/st/nucleo_g431rb/Kconfig.nucleo_g431rb b/boards/st/nucleo_g431rb/Kconfig.nucleo_g431rb new file mode 100644 index 00000000000..304e9cc0888 --- /dev/null +++ b/boards/st/nucleo_g431rb/Kconfig.nucleo_g431rb @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G431RB + select SOC_STM32G431XX diff --git a/boards/arm/nucleo_g431rb/arduino_r3_connector.dtsi b/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g431rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_g431rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_g431rb/board.cmake b/boards/st/nucleo_g431rb/board.cmake similarity index 100% rename from boards/arm/nucleo_g431rb/board.cmake rename to boards/st/nucleo_g431rb/board.cmake diff --git a/boards/st/nucleo_g431rb/board.yml b/boards/st/nucleo_g431rb/board.yml new file mode 100644 index 00000000000..460dcf740e8 --- /dev/null +++ b/boards/st/nucleo_g431rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g431rb + vendor: st + socs: + - name: stm32g431xx diff --git a/boards/arm/nucleo_g431rb/doc/img/nucleo_g431rb.jpg b/boards/st/nucleo_g431rb/doc/img/nucleo_g431rb.jpg similarity index 100% rename from boards/arm/nucleo_g431rb/doc/img/nucleo_g431rb.jpg rename to boards/st/nucleo_g431rb/doc/img/nucleo_g431rb.jpg diff --git a/boards/st/nucleo_g431rb/doc/index.rst b/boards/st/nucleo_g431rb/doc/index.rst new file mode 100644 index 00000000000..08d660a0c7d --- /dev/null +++ b/boards/st/nucleo_g431rb/doc/index.rst @@ -0,0 +1,263 @@ +.. _nucleo_g431rb_board: + +ST Nucleo G431RB +################ + +Overview +******** + +The Nucleo G431RB board features an ARM Cortex-M4 based STM32G431RB MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo G431RB board: + +- STM32 microcontroller in LQFP64 package +- Arduino Uno V3 connectivity +- On-board ST-LINK/V3E debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD2) +- Two push-buttons: RESET and USER + +.. image:: img/nucleo_g431rb.jpg + :align: center + :alt: Nucleo G431RB + +More information about the board can be found at the `Nucleo G431RB website`_. + +Hardware +******** + +The STM32G431RB SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 170 MHz +- Clock Sources: + + - 4 to 48 MHz crystal oscillator (HSE) + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- 14x timers: + + - 1x 32-bit timer and 2x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 2x 16-bit 8-channel advanced motor control timers, with up to 8x PWM channels, dead time generation and emergency stop + - 1x 16-bit timer with 2x IC/OCs, one OCN/PWM, dead time generation and emergency stop + - 2x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop + - 2x watchdog timers (independent, window) + - 2x 16-bit basic timers + - SysTick timer + - 1x low-power timer + +- Up to 86 fast I/Os, most 5 V-tolerant +- Memories + + - Up to 128 KB single bank Flash, proprietary code readout protection + - Up to 22 KB of SRAM including 16 KB with hardware parity check + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 4x 12-bit DAC, low-power sample and hold + - 3x operational amplifiers with built-in PGA + - 4x ultra-fast rail-to-rail analog comparators + +- 16x communication interfaces + + - 1 x FDCAN controller supporting flexible data rate + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART + - 3x SPIs (2x with multiplexed half duplex I2S interface) + - 1x SAI (serial audio interface) + - USB 2.0 full-speed interface with LPM and BCD support + - IRTIM (Infrared interface) + - USB Type-C™ /USB power delivery controller (UCPD) + +- 12-channel DMA controller +- True random number generator (RNG) +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32G431RB can be found here: + +- `STM32G431RB on www.st.com`_ +- `STM32G4 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_g431rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | rng | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g431rb/nucleo_g431rb_defconfig` + + +Connections and IOs +=================== + +Nucleo G431RB Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32G4 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PC4 +- UART_1_RX : PC5 +- LPUART_1_TX : PA2 +- LPUART_1_RX : PA3 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB9 +- SPI_1_NSS : PB6 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- SPI_2_NSS : PB12 +- SPI_2_SCK : PB13 +- SPI_2_MISO : PB14 +- SPI_2_MOSI : PB15 +- SPI_3_NSS : PA15 +- SPI_3_SCK : PC10 +- SPI_3_MISO : PC11 +- SPI_3_MOSI : PC12 +- PWM_3_CH1 : PB4 +- USER_PB : PC13 +- LD2 : PA5 +- DAC1_OUT1 : PA4 + +System Clock +------------ + +Nucleo G431RB System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 150MHz, +driven by 16MHz high speed internal oscillator. The clock can be boosted to 170MHz if boost mode +is selected. + +Serial Port +----------- + +Nucleo G431RB board has 3 U(S)ARTs and one LPUART. The Zephyr console output is assigned to LPUART1. +Default settings are 115200 8N1. + +Please note that LPUART1 baudrate is limited to 9600 if the MCU is clocked by LSE (32.768 kHz) in +low power mode. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g431rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G431RB board includes an ST-LINK/V3E embedded debug tool interface. + +This interface is not yet supported by the openocd version included in the Zephyr SDK. + +Instead, support can be enabled on pyocd by adding "pack" support with +the following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32g431rb + +Note: +To manually enable the openocd interface, You can still update, compile and install +a 'local' openocd from the official openocd repo http://openocd.zylin.com . +Then run the following openocd command where the '/usr/local/bin/openocd'is your path +for the freshly installed openocd, given by "$ which openocd" : + +.. code-block:: console + + $ west flash --openocd /usr/local/bin/openocd + +Flashing an application to Nucleo G431RB +---------------------------------------- + +Connect the Nucleo G431RB to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g431rb + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g431rb + :maybe-skip-config: + :goals: debug + +.. _Nucleo G431RB website: + https://www.st.com/en/evaluation-tools/nucleo-g431rb.html + +.. _STM32G4 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00556337.pdf + +.. _STM32G431RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32g431rb.html + +.. _STM32G4 reference manual: + https://www.st.com/resource/en/reference_manual/dm00355726.pdf diff --git a/boards/arm/nucleo_g431rb/nucleo_g431rb.dts b/boards/st/nucleo_g431rb/nucleo_g431rb.dts similarity index 100% rename from boards/arm/nucleo_g431rb/nucleo_g431rb.dts rename to boards/st/nucleo_g431rb/nucleo_g431rb.dts diff --git a/boards/arm/nucleo_g431rb/nucleo_g431rb.yaml b/boards/st/nucleo_g431rb/nucleo_g431rb.yaml similarity index 100% rename from boards/arm/nucleo_g431rb/nucleo_g431rb.yaml rename to boards/st/nucleo_g431rb/nucleo_g431rb.yaml diff --git a/boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig b/boards/st/nucleo_g431rb/nucleo_g431rb_defconfig similarity index 85% rename from boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig rename to boards/st/nucleo_g431rb/nucleo_g431rb_defconfig index 92c2363d2d8..5bd145ba76c 100644 --- a/boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig +++ b/boards/st/nucleo_g431rb/nucleo_g431rb_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G4X=y -CONFIG_SOC_STM32G431XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_g431rb/st_morpho_connector.dtsi b/boards/st/nucleo_g431rb/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g431rb/st_morpho_connector.dtsi rename to boards/st/nucleo_g431rb/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_g431rb/support/openocd.cfg b/boards/st/nucleo_g431rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g431rb/support/openocd.cfg rename to boards/st/nucleo_g431rb/support/openocd.cfg diff --git a/boards/st/nucleo_g474re/Kconfig.defconfig b/boards/st/nucleo_g474re/Kconfig.defconfig new file mode 100644 index 00000000000..fb93e1098d1 --- /dev/null +++ b/boards/st/nucleo_g474re/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32G474RE Nucleo board configuration + +# Copyright (c) 2019 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_G474RE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_G431RB diff --git a/boards/st/nucleo_g474re/Kconfig.nucleo_g474re b/boards/st/nucleo_g474re/Kconfig.nucleo_g474re new file mode 100644 index 00000000000..bf6ef199971 --- /dev/null +++ b/boards/st/nucleo_g474re/Kconfig.nucleo_g474re @@ -0,0 +1,5 @@ +# Copyright (c) 2019 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G474RE + select SOC_STM32G474XX diff --git a/boards/arm/nucleo_g474re/arduino_r3_connector.dtsi b/boards/st/nucleo_g474re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g474re/arduino_r3_connector.dtsi rename to boards/st/nucleo_g474re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_g474re/board.cmake b/boards/st/nucleo_g474re/board.cmake similarity index 100% rename from boards/arm/nucleo_g474re/board.cmake rename to boards/st/nucleo_g474re/board.cmake diff --git a/boards/st/nucleo_g474re/board.yml b/boards/st/nucleo_g474re/board.yml new file mode 100644 index 00000000000..7cf7857f527 --- /dev/null +++ b/boards/st/nucleo_g474re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g474re + vendor: st + socs: + - name: stm32g474xx diff --git a/boards/arm/nucleo_g474re/doc/img/nucleo_g474re.jpg b/boards/st/nucleo_g474re/doc/img/nucleo_g474re.jpg similarity index 100% rename from boards/arm/nucleo_g474re/doc/img/nucleo_g474re.jpg rename to boards/st/nucleo_g474re/doc/img/nucleo_g474re.jpg diff --git a/boards/st/nucleo_g474re/doc/index.rst b/boards/st/nucleo_g474re/doc/index.rst new file mode 100644 index 00000000000..9d23c072b75 --- /dev/null +++ b/boards/st/nucleo_g474re/doc/index.rst @@ -0,0 +1,255 @@ +.. _nucleo_g474re_board: + +ST Nucleo G474RE +################ + +Overview +******** + +The Nucleo G474RE board features an ARM Cortex-M4 based STM32G474RE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo G474RE board: + +- STM32 microcontroller in LQFP64 package +- Arduino Uno V3 connectivity +- On-board ST-LINK/V3E debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD2) +- Two push-buttons: RESET and USER + +.. image:: img/nucleo_g474re.jpg + :align: center + :alt: Nucleo G474RE + +More information about the board can be found at the `Nucleo G474RE website`_. + +Hardware +******** + +The STM32G474RE SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 170 MHz +- Clock Sources: + + - 4 to 48 MHz crystal oscillator (HSE) + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- 14x timers: + + - 1x 32-bit timer and 2x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 2x 16-bit 8-channel advanced motor control timers, with up to 8x PWM channels, dead time generation and emergency stop + - 1x 16-bit timer with 2x IC/OCs, one OCN/PWM, dead time generation and emergency stop + - 2x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop + - 2x watchdog timers (independent, window) + - 2x 16-bit basic timers + - SysTick timer + - 1x low-power timer + +- Up to 86 fast I/Os, most 5 V-tolerant +- Memories + + - Up to 128 KB single bank Flash, proprietary code readout protection + - Up to 22 KB of SRAM including 16 KB with hardware parity check + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 4x 12-bit DAC, low-power sample and hold + - 3x operational amplifiers with built-in PGA + - 4x ultra-fast rail-to-rail analog comparators + +- 16x communication interfaces + + - 1 x FDCAN controller supporting flexible data rate + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART + - 3x SPIs (2x with multiplexed half duplex I2S interface) + - 1x SAI (serial audio interface) + - USB 2.0 full-speed interface with LPM and BCD support + - IRTIM (Infrared interface) + - USB Type-C™ /USB power delivery controller (UCPD) + +- 12-channel DMA controller +- True random number generator (RNG) +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32G474RE can be found here: + +- `STM32G474RE on www.st.com`_ +- `STM32G4 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_g474re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ +| FDCAN1 | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g474re/nucleo_g474re_defconfig` + + +Connections and IOs +=================== + +Nucleo G474RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32G4 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PC4 +- UART_1_RX : PC5 +- LPUART_1_TX : PA2 +- LPUART_1_RX : PA3 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB9 +- SPI_1_NSS : PB6 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- SPI_2_NSS : PB12 +- SPI_2_SCK : PB13 +- SPI_2_MISO : PB14 +- SPI_2_MOSI : PB15 +- SPI_3_NSS : PA15 +- SPI_3_SCK : PC10 +- SPI_3_MISO : PC11 +- SPI_3_MOSI : PC12 +- PWM_2_CH1 : PA5 (might conflict with SPI1) +- PWM_3_CH1 : PB4 +- USER_PB : PC13 +- LD2 : PA5 +- ADC1_IN1 : PA0 +- DAC1_OUT1 : PA4 +- FDCAN1_RX: PA11 +- FDCAN1_TX: PA12 + +System Clock +------------ + +Nucleo G474RE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 150MHz, +driven by 16MHz high speed internal oscillator. The clock can be boosted to 170MHz if boost mode +is selected. + +Serial Port +----------- + +Nucleo G474RE board has 3 U(S)ARTs. The Zephyr console output is assigned to LPUART1. +Default settings are 115200 8N1. + +Please note that LPUART1 baudrate is limited to 9600 if the MCU is clocked by LSE (32.768 kHz) in +low power mode. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g474re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G474RE board includes an ST-LINK/V3E embedded debug tool interface. + +Flashing an application to Nucleo G474RE +---------------------------------------- + +Connect the Nucleo G474RE to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g474re + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g474re + :maybe-skip-config: + :goals: debug + +.. _Nucleo G474RE website: + https://www.st.com/en/evaluation-tools/nucleo-g474re.html + +.. _STM32G4 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00556337.pdf + +.. _STM32G474RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32g474re.html + +.. _STM32G4 reference manual: + https://www.st.com/resource/en/reference_manual/dm00355726.pdf diff --git a/boards/arm/nucleo_g474re/nucleo_g474re.dts b/boards/st/nucleo_g474re/nucleo_g474re.dts similarity index 100% rename from boards/arm/nucleo_g474re/nucleo_g474re.dts rename to boards/st/nucleo_g474re/nucleo_g474re.dts diff --git a/boards/arm/nucleo_g474re/nucleo_g474re.yaml b/boards/st/nucleo_g474re/nucleo_g474re.yaml similarity index 100% rename from boards/arm/nucleo_g474re/nucleo_g474re.yaml rename to boards/st/nucleo_g474re/nucleo_g474re.yaml diff --git a/boards/arm/nucleo_g474re/nucleo_g474re_defconfig b/boards/st/nucleo_g474re/nucleo_g474re_defconfig similarity index 85% rename from boards/arm/nucleo_g474re/nucleo_g474re_defconfig rename to boards/st/nucleo_g474re/nucleo_g474re_defconfig index 15b382fefae..b22a31b2f20 100644 --- a/boards/arm/nucleo_g474re/nucleo_g474re_defconfig +++ b/boards/st/nucleo_g474re/nucleo_g474re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G4X=y -CONFIG_SOC_STM32G474XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_g474re/support/openocd.cfg b/boards/st/nucleo_g474re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g474re/support/openocd.cfg rename to boards/st/nucleo_g474re/support/openocd.cfg diff --git a/boards/st/nucleo_h563zi/Kconfig.defconfig b/boards/st/nucleo_h563zi/Kconfig.defconfig new file mode 100644 index 00000000000..54426df3945 --- /dev/null +++ b/boards/st/nucleo_h563zi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32H563ZI Nucleo board configuration + +# Copyright (c) 2023 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H563ZI + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_H563ZI diff --git a/boards/st/nucleo_h563zi/Kconfig.nucleo_h563zi b/boards/st/nucleo_h563zi/Kconfig.nucleo_h563zi new file mode 100644 index 00000000000..49209ab6a16 --- /dev/null +++ b/boards/st/nucleo_h563zi/Kconfig.nucleo_h563zi @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H563ZI + select SOC_STM32H563XX diff --git a/boards/arm/nucleo_h563zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h563zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h563zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_h563zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_h563zi/board.cmake b/boards/st/nucleo_h563zi/board.cmake similarity index 100% rename from boards/arm/nucleo_h563zi/board.cmake rename to boards/st/nucleo_h563zi/board.cmake diff --git a/boards/st/nucleo_h563zi/board.yml b/boards/st/nucleo_h563zi/board.yml new file mode 100644 index 00000000000..42319f55755 --- /dev/null +++ b/boards/st/nucleo_h563zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h563zi + vendor: st + socs: + - name: stm32h563xx diff --git a/boards/arm/nucleo_h563zi/doc/img/nucleo_h563zi.jpg b/boards/st/nucleo_h563zi/doc/img/nucleo_h563zi.jpg similarity index 100% rename from boards/arm/nucleo_h563zi/doc/img/nucleo_h563zi.jpg rename to boards/st/nucleo_h563zi/doc/img/nucleo_h563zi.jpg diff --git a/boards/st/nucleo_h563zi/doc/index.rst b/boards/st/nucleo_h563zi/doc/index.rst new file mode 100644 index 00000000000..9be05804330 --- /dev/null +++ b/boards/st/nucleo_h563zi/doc/index.rst @@ -0,0 +1,317 @@ +.. _nucleo_h563zi_board: + +ST Nucleo H563ZI +################ + +Overview +******** + +The Nucleo H563ZI board is designed as an affordable development platform for +STMicroelectronics ARM |reg| Cortex |reg|-M33 core-based STM32H563ZIT6 +microcontroller with TrustZone |reg|. +Here are some highlights of the Nucleo H563ZI board: + +- STM32H563ZI microcontroller featuring 2 Mbytes of Flash memory and 640Kbyte of + SRAM in LQFP144 package +- Board connectors: + + - USB Type-C |trade| Sink device FS + - Ethernet RJ45 connector compliant with IEEE-802.3-2002 (depending on STM32 support) + - ST Zio expansion connector including Arduino Uno V3 connectivity (CN7, CN8, CN9, CN10) + - ST morpho extension connector (CN11, CN12) + +- Flexible board power supply: + + - 5V_USB_STLK from ST-Link USB connector + - VIN (7 - 12V, 0.8A) supplied via pin header CN8 pin 15 or CN11 pin 24 + - 5V_EXT on the ST morpho connector CN11 Pin 6 (5V, 1.3) + - CHGR from a USB charger via the ST-LINK USB connector + - USB_USER from the USB user connector (5V, 3A) + - 3V3_EXT supplied via a pin header CN8 pin 7 or CN11 pin 16 (3.3V, 1.3A) + +- On-board ST-LINK/V3EC debugger/programmer + + - mass storage + - Virtual COM port + - debug port + +- Three users LEDs +- Two push-buttons: USER and RESET +- 32.789 kHz crystal oscillator + +More information about the board can be found at the `NUCLEO_H563ZI website`_. + +.. image:: img/nucleo_h563zi.jpg + :align: center + :alt: NUCLEO H563ZI + +Hardware +******** + +The STM32H563xx devices are high-performance microcontrollers from the STM32H5 +Series based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. +They operate at a frequency of up to 250 MHz. + +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 375 DMPIS/MHz (Dhrystone 2.1) + +- Security + + - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension + - Up to 8 configurable SAU regions + - TrustZone |reg| aware and securable peripherals + - Flexible lifecycle scheme with secure debug authentication + - SFI (secure firmware installation) + - Secure firmware upgrade support with TF-M + - HASH hardware accelerator + - True random number generator, NIST SP800-90B compliant + - 96-bit unique ID + - Active tampers + +- Clock management: + + - 25 MHz crystal oscillator (HSE) + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 64 MHz (HSI) trimmable by software + - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) + - Internal 4 MHz oscillator (CSI), trimmable by software + - Internal 48 MHz (HSI48) with recovery system + - 3 PLLs for system clock, USB, audio, ADC + +- Power management + + - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry + - Embedded SMPS step-down converter + +- RTC with HW calendar, alarms and calibration +- Up to 139 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V +- Up to 16 timers and 2 watchdogs + + - 12x 16-bit + - 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 6x 16-bit low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- Memories + + - Up to 2 MB Flash, 2 banks read-while-write + - 1 Kbyte OTP (one-time programmable) + - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC + - 4 Kbytes of backup SRAM available in the lowest power modes + - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories + - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats + - 2x SD/SDIO/MMC interfaces + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC with up to 5 MSPS in 12-bit + - 1x 12-bit D/A with 2 channels + - 1x Digital temperature sensor + +- 34x communication interfaces + + - 1x USB Type-C / USB power-delivery controller + - 1x USB 2.0 full-speed host and device + - 4x I2C FM+ interfaces (SMBus/PMBus) + - 1x I3C interface + - 12x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) + - 1x LP UART + - 6x SPIs including 3 muxed with full-duplex I2S + - 5x additional SPI from 5x USART when configured in Synchronous mode + - 2x SAI + - 2x FDCAN + - 1x SDMMC interface + - 2x 16 channel DMA controllers + - 1x 8- to 14- bit camera interface + - 1x HDMI-CEC + - 1x Ethernel MAC interface with DMA controller + - 1x 16-bit parallel slave synchronous-interface + +- CORDIC for trigonometric functions acceleration +- FMAC (filter mathematical accelerator) +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + +More information about STM32H563ZI can be found here: + +- `STM32H563ZI on www.st.com`_ +- `STM32H563 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_h563zi board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | Real Time Clock | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi bus | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB full-speed host/device bus | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig and dts files: + +- Secure target: + + - :zephyr_file:`boards/st/nucleo_h563zi/nucleo_h563zi_defconfig` + - :zephyr_file:`boards/st/nucleo_h563zi/nucleo_h563zi.dts` + +Zephyr board options +==================== + +The STM32H563 is an SoC with Cortex-M33 architecture. Zephyr provides support +for building for Secure firmware. + +The BOARD options are summarized below: + ++----------------------+-----------------------------------------------+ +| BOARD | Description | ++======================+===============================================+ +| nucleo_h563zi | For building Secure firmware | ++----------------------+-----------------------------------------------+ + +Connections and IOs +=================== + +Nucleo H563ZI Board has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32H5 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- ADC1 channel 3 input: PA6 +- ADC1 channel 15 input: PA3 +- DAC1 channel 2 output: PA5 +- LD1 (green): PB0 +- LD2 (yellow): PF4 +- LD3 (red): PG4 +- LPUART1 TX/RX : PB6/PB7 (Arduino LPUART1) +- SPI1 SCK/MISO/MOSI/CS: PA5/PG9/PB5/PD14 +- UART3 TX/RX : PD8/PD9 (VCP) +- USER_PB : PC13 + +System Clock +------------ + +Nucleo H563ZI System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +240MHz, driven by 8MHz external clock provided from the STLINK-V3EC. + +Serial Port +----------- + +Nucleo H563ZI board has up to 12 U(S)ARTs. The Zephyr console output is assigned +to USART3. Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``nucleo_h563zi`` board can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo H563ZI board includes an ST-LINK/V3EC embedded debug tool interface. +This probe allows to flash the board using various tools. + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board. + +Alternatively, pyocd or jlink via an external probe can also be used to flash +and debug the board if west is told to use it as runner, which can be done by +passing either or ``-r pyocd``, or ``-r jlink``. + +For pyocd additional target information needs to be installed. +This can be done by executing the following commands. + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32h5 + + +Flashing an application to Nucleo H563ZI +------------------------------------------ + +Connect the Nucleo H563ZI to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h563zi + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! nucleo_h563zi + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_h563zi + :goals: debug + +.. _NUCLEO_H563ZI website: + https://www.st.com/en/evaluation-tools/nucleo-h563zi + +.. _STM32H5 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/um3115-stm32h5-nucleo144-board-mb1404-stmicroelectronics.pdf + +.. _STM32H563ZI on www.st.com: + https://www.st.com/en/microcontrollers/stm32h563zi.html + +.. _STM32H563 reference manual: + https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/nucleo_h563zi/nucleo_h563zi-common.dtsi b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi similarity index 100% rename from boards/arm/nucleo_h563zi/nucleo_h563zi-common.dtsi rename to boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi diff --git a/boards/arm/nucleo_h563zi/nucleo_h563zi.dts b/boards/st/nucleo_h563zi/nucleo_h563zi.dts similarity index 100% rename from boards/arm/nucleo_h563zi/nucleo_h563zi.dts rename to boards/st/nucleo_h563zi/nucleo_h563zi.dts diff --git a/boards/arm/nucleo_h563zi/nucleo_h563zi.yaml b/boards/st/nucleo_h563zi/nucleo_h563zi.yaml similarity index 100% rename from boards/arm/nucleo_h563zi/nucleo_h563zi.yaml rename to boards/st/nucleo_h563zi/nucleo_h563zi.yaml diff --git a/boards/arm/nucleo_h563zi/nucleo_h563zi_defconfig b/boards/st/nucleo_h563zi/nucleo_h563zi_defconfig similarity index 85% rename from boards/arm/nucleo_h563zi/nucleo_h563zi_defconfig rename to boards/st/nucleo_h563zi/nucleo_h563zi_defconfig index a14e2d48eec..d751abf075b 100644 --- a/boards/arm/nucleo_h563zi/nucleo_h563zi_defconfig +++ b/boards/st/nucleo_h563zi/nucleo_h563zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H5X=y -CONFIG_SOC_STM32H563XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_h563zi/st_morpho_connector.dtsi b/boards/st/nucleo_h563zi/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h563zi/st_morpho_connector.dtsi rename to boards/st/nucleo_h563zi/st_morpho_connector.dtsi diff --git a/boards/st/nucleo_h723zg/Kconfig.defconfig b/boards/st/nucleo_h723zg/Kconfig.defconfig new file mode 100644 index 00000000000..2e205cf96c4 --- /dev/null +++ b/boards/st/nucleo_h723zg/Kconfig.defconfig @@ -0,0 +1,19 @@ +# STM32H723ZG Nucleo board configuration + +# Copyright (c) 2020 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H723ZG + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +config USB_DC_HAS_HS_SUPPORT + default y + depends on USB_DC_STM32 + +endif # BOARD_NUCLEO_H723ZG diff --git a/boards/st/nucleo_h723zg/Kconfig.nucleo_h723zg b/boards/st/nucleo_h723zg/Kconfig.nucleo_h723zg new file mode 100644 index 00000000000..a8ff99320e6 --- /dev/null +++ b/boards/st/nucleo_h723zg/Kconfig.nucleo_h723zg @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H723ZG + select SOC_STM32H723XX diff --git a/boards/arm/nucleo_h723zg/arduino_r3_connector.dtsi b/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h723zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_h723zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_h723zg/board.cmake b/boards/st/nucleo_h723zg/board.cmake similarity index 100% rename from boards/arm/nucleo_h723zg/board.cmake rename to boards/st/nucleo_h723zg/board.cmake diff --git a/boards/st/nucleo_h723zg/board.yml b/boards/st/nucleo_h723zg/board.yml new file mode 100644 index 00000000000..56a6d5cfb52 --- /dev/null +++ b/boards/st/nucleo_h723zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h723zg + vendor: st + socs: + - name: stm32h723xx diff --git a/boards/arm/nucleo_h723zg/doc/img/nucleo_h723zg.jpg b/boards/st/nucleo_h723zg/doc/img/nucleo_h723zg.jpg similarity index 100% rename from boards/arm/nucleo_h723zg/doc/img/nucleo_h723zg.jpg rename to boards/st/nucleo_h723zg/doc/img/nucleo_h723zg.jpg diff --git a/boards/st/nucleo_h723zg/doc/index.rst b/boards/st/nucleo_h723zg/doc/index.rst new file mode 100644 index 00000000000..cce94294255 --- /dev/null +++ b/boards/st/nucleo_h723zg/doc/index.rst @@ -0,0 +1,248 @@ +.. _nucleo_h723zg_board: + +ST Nucleo H723ZG +################ + +Overview +******** + +The STM32 Nucleo-144 board provides an affordable and flexible way for users +to try out new concepts and build prototypes by choosing from the various combinations +of performance and power consumption features, provided by the STM32 microcontroller. +For the compatible boards, the internal or external SMPS significantly reduces power +consumption in Run mode. + +The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and +the ST morpho headers provide an easy means of expanding the functionality of the Nucleo +open development platform with a wide choice of specialized shields. +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK V3 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - Ethernet RJ45 (depending on STM32 support) + - SWDST Zio connector including Arduino* Uno V3ST + - ST morpho expansion + +- Flexible power-supply options: ST-LINK USB VBUS or external sources +- External or internal SMPS to generate Vcore logic supply +- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port +- USB OTG full speed or device only + +.. image:: img/nucleo_h723zg.jpg + :align: center + :alt: Nucleo H723ZG + +More information about the board can be found at the `Nucleo H723ZG website`_. + +Hardware +******** + +Nucleo H723ZG provides the following hardware components: + +- STM32H723ZG in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 550 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 1 MB Flash +- 562 kB SRAM max (376 kb used currently) +- High-resolution timer (2.1 ns) +- 32-bit timers(2) +- 16-bit timers(12) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN FD(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 114) with external interrupt capability +- 16-bit ADC(3) with 36 channels / 3.6 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_h723zg board configuration supports the following hardware +features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig files: +:zephyr_file:`boards/st/nucleo_h723zg/nucleo_h723zg_defconfig`` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H723ZG board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- I2C : PB8, PB9 +- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) + +System Clock +------------ + +Nucleo H723ZG System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 550MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H723ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB52`` jumper on the back side of the board. + +Programming and Debugging +************************* + +Currently the ``nucleo_h723zg`` board supports stm32cubeprogrammer (default), OpenOCD and J-Link debuggers. + +.. note:: + + Official OpenOCD support for this board was added on October '20. + Make sure your openocd version is older than that. + Following links may be helpful: `OpenOCD installing Debug Version`_ + and `OpenOCD installing with ST-LINK V3 support`_ + +.. note:: + + Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeIDE`_ + +Flashing +======== + +Nucleo H723ZG board includes an ST-LINK/V3 embedded debug tool interface. + +First, connect the NUCLEO-H723ZG to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your NUCLEO-H723ZG board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +or use screen: + +.. code-block:: console + + $ screen /dev/ttyACM0 115200 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h723zg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h723zg + +Blinky example can also be used: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_h723zg + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h723zg + :maybe-skip-config: + :goals: debug + +.. _Nucleo H723ZG website: + https://www.st.com/en/evaluation-tools/nucleo-h723zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00499160-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf + +.. _STM32H723ZG on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h723zg.html + +.. _STM32H723 reference manual: + https://www.st.com/resource/en/reference_manual/dm00603761-stm32h723733-stm32h725735-and-stm32h730-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _OpenOCD installing Debug Version: + https://github.com/zephyrproject-rtos/openocd + +.. _OpenOCD installing with ST-LINK V3 support: + https://mbd.kleier.net/integrating-st-link-v3.html + +.. _STM32CubeIDE: + https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/nucleo_h723zg/nucleo_h723zg.dts b/boards/st/nucleo_h723zg/nucleo_h723zg.dts similarity index 100% rename from boards/arm/nucleo_h723zg/nucleo_h723zg.dts rename to boards/st/nucleo_h723zg/nucleo_h723zg.dts diff --git a/boards/arm/nucleo_h723zg/nucleo_h723zg.yaml b/boards/st/nucleo_h723zg/nucleo_h723zg.yaml similarity index 100% rename from boards/arm/nucleo_h723zg/nucleo_h723zg.yaml rename to boards/st/nucleo_h723zg/nucleo_h723zg.yaml diff --git a/boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig b/boards/st/nucleo_h723zg/nucleo_h723zg_defconfig similarity index 78% rename from boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig rename to boards/st/nucleo_h723zg/nucleo_h723zg_defconfig index 676bfa4533f..96a37909f6b 100644 --- a/boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig +++ b/boards/st/nucleo_h723zg/nucleo_h723zg_defconfig @@ -1,10 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H723XX=y - -CONFIG_BOARD_NUCLEO_H723ZG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_h723zg/support/openocd.cfg b/boards/st/nucleo_h723zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_h723zg/support/openocd.cfg rename to boards/st/nucleo_h723zg/support/openocd.cfg diff --git a/boards/st/nucleo_h743zi/Kconfig.defconfig b/boards/st/nucleo_h743zi/Kconfig.defconfig new file mode 100644 index 00000000000..b893c798c11 --- /dev/null +++ b/boards/st/nucleo_h743zi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32H743ZI Nucleo board configuration + +# Copyright (c) 2020 Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H743ZI + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_H743ZI diff --git a/boards/st/nucleo_h743zi/Kconfig.nucleo_h743zi b/boards/st/nucleo_h743zi/Kconfig.nucleo_h743zi new file mode 100644 index 00000000000..f1f89927f01 --- /dev/null +++ b/boards/st/nucleo_h743zi/Kconfig.nucleo_h743zi @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H743ZI + select SOC_STM32H743XX diff --git a/boards/arm/nucleo_h743zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h743zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h743zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_h743zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_h743zi/board.cmake b/boards/st/nucleo_h743zi/board.cmake similarity index 100% rename from boards/arm/nucleo_h743zi/board.cmake rename to boards/st/nucleo_h743zi/board.cmake diff --git a/boards/st/nucleo_h743zi/board.yml b/boards/st/nucleo_h743zi/board.yml new file mode 100644 index 00000000000..e133a6fc034 --- /dev/null +++ b/boards/st/nucleo_h743zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h743zi + vendor: st + socs: + - name: stm32h743xx diff --git a/boards/arm/nucleo_h743zi/doc/img/nucleo_h743zi.jpg b/boards/st/nucleo_h743zi/doc/img/nucleo_h743zi.jpg similarity index 100% rename from boards/arm/nucleo_h743zi/doc/img/nucleo_h743zi.jpg rename to boards/st/nucleo_h743zi/doc/img/nucleo_h743zi.jpg diff --git a/boards/st/nucleo_h743zi/doc/index.rst b/boards/st/nucleo_h743zi/doc/index.rst new file mode 100644 index 00000000000..d5d1ee596b6 --- /dev/null +++ b/boards/st/nucleo_h743zi/doc/index.rst @@ -0,0 +1,246 @@ +.. _nucleo_h743zi_board: + +ST Nucleo H743ZI +################ + +Overview +******** + +The STM32 Nucleo-144 boards offer combinations of performance and power that +provide an affordable and flexible way for users to build prototypes and try +out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) +significantly reduces power consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V2-1 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_h743zi.jpg + :align: center + :alt: Nucleo H743ZI + +More information about the board can be found at the `Nucleo H743ZI website`_. + +Hardware +******** + +Nucleo H743ZI provides the following hardware components: + +- STM32H743ZI in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 480 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 2 MB Flash +- 1 MB SRAM +- High-resolution timer (2.1 ns) +- 32-bit timers(2) +- 16-bit timers(12) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN FD(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 114) with external interrupt capability +- 16-bit ADC(3) with 36 channels / 3.6 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_h743zi board configuration supports the following hardware +features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-------------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-------------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-------------+------------+-------------------------------------+ +| CAN/CANFD | on-chip | canbus | ++-------------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_h743zi/nucleo_h743zi_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H743ZI board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- I2C : PB8, PB9 +- ADC1_INP15 : PA3 +- DAC1_OUT1 : PA4 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PB5 (Arduino SPI) +- CAN/CANFD : PD0, PD1 + +System Clock +------------ + +Nucleo H743ZI System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H743ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB156`` jumper on the back side of the board. + +CAN, CANFD +---------- + +Requires an external CAN or CANFD transceiver. + +Programming and Debugging +************************* + +Applications for the ``nucleo_h743zi`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. note:: + + If using OpenOCD you will need a recent development version as the last + official release does not support H7 series yet. You can also choose the + ``stm32cubeprogrammer`` runner. + +Flashing +======== + +Nucleo H743ZI board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo H743ZI +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h743zi + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h743zi + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h743zi + :maybe-skip-config: + :goals: debug + +.. _Nucleo H743ZI website: + https://www.st.com/en/evaluation-tools/nucleo-h743zi.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32H743ZI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h743-753/stm32h743zi.html + +.. _STM32H743 reference manual: + https://www.st.com/resource/en/reference_manual/dm00314099.pdf diff --git a/boards/arm/nucleo_h743zi/nucleo_h743zi.dts b/boards/st/nucleo_h743zi/nucleo_h743zi.dts similarity index 100% rename from boards/arm/nucleo_h743zi/nucleo_h743zi.dts rename to boards/st/nucleo_h743zi/nucleo_h743zi.dts diff --git a/boards/arm/nucleo_h743zi/nucleo_h743zi.yaml b/boards/st/nucleo_h743zi/nucleo_h743zi.yaml similarity index 100% rename from boards/arm/nucleo_h743zi/nucleo_h743zi.yaml rename to boards/st/nucleo_h743zi/nucleo_h743zi.yaml diff --git a/boards/arm/nucleo_h743zi/nucleo_h743zi_defconfig b/boards/st/nucleo_h743zi/nucleo_h743zi_defconfig similarity index 85% rename from boards/arm/nucleo_h743zi/nucleo_h743zi_defconfig rename to boards/st/nucleo_h743zi/nucleo_h743zi_defconfig index c06c8d34406..8dcaab60f61 100644 --- a/boards/arm/nucleo_h743zi/nucleo_h743zi_defconfig +++ b/boards/st/nucleo_h743zi/nucleo_h743zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H743XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_h743zi/support/openocd.cfg b/boards/st/nucleo_h743zi/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_h743zi/support/openocd.cfg rename to boards/st/nucleo_h743zi/support/openocd.cfg diff --git a/boards/st/nucleo_h745zi_q/Kconfig.defconfig b/boards/st/nucleo_h745zi_q/Kconfig.defconfig new file mode 100644 index 00000000000..9ad83aa96d1 --- /dev/null +++ b/boards/st/nucleo_h745zi_q/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32H745ZI Nucleo board configuration + +# Copyright (c) 2020 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H745ZI_Q + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_H745ZI_Q diff --git a/boards/st/nucleo_h745zi_q/Kconfig.nucleo_h745zi_q b/boards/st/nucleo_h745zi_q/Kconfig.nucleo_h745zi_q new file mode 100644 index 00000000000..6d19d1592ae --- /dev/null +++ b/boards/st/nucleo_h745zi_q/Kconfig.nucleo_h745zi_q @@ -0,0 +1,8 @@ +# STM32H745ZI Nucleo board configuration + +# Copyright (c) 2020 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H745ZI_Q + select SOC_STM32H745XX_M7 if BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M7 + select SOC_STM32H745XX_M4 if BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M4 diff --git a/boards/arm/nucleo_h745zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h745zi_q/arduino_r3_connector.dtsi rename to boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi diff --git a/boards/st/nucleo_h745zi_q/board.cmake b/boards/st/nucleo_h745zi_q/board.cmake new file mode 100644 index 00000000000..677c748de35 --- /dev/null +++ b/boards/st/nucleo_h745zi_q/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2020 Alexander Kozhinov + +board_runner_args(jlink "--device=STM32H745ZI" "--speed=4000") +if(CONFIG_BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M7) +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +elseif(CONFIG_BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M4) +board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_h745zi_q/board.yml b/boards/st/nucleo_h745zi_q/board.yml new file mode 100644 index 00000000000..7ba025f5bb7 --- /dev/null +++ b/boards/st/nucleo_h745zi_q/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h745zi_q + vendor: st + socs: + - name: stm32h745xx diff --git a/boards/arm/nucleo_h745zi_q/doc/img/nucleo_h745zi_q.jpg b/boards/st/nucleo_h745zi_q/doc/img/nucleo_h745zi_q.jpg similarity index 100% rename from boards/arm/nucleo_h745zi_q/doc/img/nucleo_h745zi_q.jpg rename to boards/st/nucleo_h745zi_q/doc/img/nucleo_h745zi_q.jpg diff --git a/boards/st/nucleo_h745zi_q/doc/index.rst b/boards/st/nucleo_h745zi_q/doc/index.rst new file mode 100644 index 00000000000..265d3385be8 --- /dev/null +++ b/boards/st/nucleo_h745zi_q/doc/index.rst @@ -0,0 +1,290 @@ +.. _nucleo_h745zi_q_board: + +ST Nucleo H745ZI-Q +################### + +Overview +******** + +The STM32 Nucleo-144 board provides an affordable and flexible way for users +to try out new concepts and build prototypes by choosing from the various combinations +of performance and power consumption features, provided by the STM32 microcontroller. +For the compatible boards, the internal or external SMPS significantly reduces power +consumption in Run mode. + +The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and +the ST morpho headers provide an easy means of expanding the functionality of the Nucleo +open development platform with a wide choice of specialized shields. +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK V3 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - Ethernet RJ45 (depending on STM32 support) + - SWDST Zio connector including Arduino* Uno V3ST + - ST morpho expansion + +- Flexible power-supply options: ST-LINK USB VBUS or external sources +- External or internal SMPS to generate Vcore logic supply +- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port +- USB OTG full speed or device only +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_h745zi_q.jpg + :align: center + :alt: Nucleo H745ZI-Q + +More information about the board can be found at the `Nucleo H745ZI-Q website`_. + +Hardware +******** + +Nucleo H745ZI-Q provides the following hardware components: + +- STM32H745ZI in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- ARM 32-bit Cortex-M4 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 480 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 2 MB Flash +- 1 MB SRAM +- High-resolution timer (2.1 ns) +- 32-bit timers(2) +- 16-bit timers(12) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN FD(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 114) with external interrupt capability +- 16-bit ADC(3) with 36 channels / 3.6 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_h745zi_q board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration per core can be found in the defconfig files: +:zephyr_file:`boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig`` and +:zephyr_file:`boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H745ZI board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- I2C : PB8, PB9 + +System Clock +------------ + +Nucleo H745ZI-Q System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 480MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H745ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + +Resources sharing +----------------- + +The dual core nature of STM32H745 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Programming and Debugging +************************* + +Applications for the ``nucleo_h745zi_q`` board should be built per core target, +using either ``nucleo_h745zi_q_m7`` or ```nucleo_h745zi_q_m4`` as the target +(see :ref:`build_an_application` and :ref:`application_run` for more details). + +.. note:: + + If using OpenOCD you will need a recent development version as the last + official release does not support H7 series and ST-LINK V3 yet. + Following links may be helpful: `OpenOCD installing Debug Version`_ + and `OpenOCD installing with ST-LINK V3 support`_ + +.. note:: + + Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeIDE`_ + +Flashing +======== + +Nucleo H745ZI-Q board includes an ST-LINK/V3 embedded debug tool interface. + +Flashing operation will depend on the target to be flashed and the SoC +option bytes configuration. + +By default: + + - CPU0 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0) + - CPU1 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0) + +Also, default out of the box board configuration enables CM7 and CM4 boot when +board is powered (Option bytes BCM7 and BCM4 are checked). +In that configuration, Kconfig boot option ``STM32H7_BOOT_CM4_CM7`` should be selected. +Zephyr flash configuration has been set to meet these default settings. + +Flashing an application to STM32H745ZI M7 Core +---------------------------------------------- +First, connect the NUCLEO-H745ZI-Q to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your NUCLEO-H745ZI-Q board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +or use screen: + +.. code-block:: console + + $ screen /dev/ttyACM0 115200 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h745zi_q_m7 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h745zi_q_m7 + +.. note:: + Sometimes, flashing is not working. It is necessary to erase the flash + (with STM32CubeProgrammer for example) to make it work again. + +Similarly, you can build and flash samples on the M4 target. For this, please +take care of the resource sharing (UART port used for console for instance). + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_h745zi_q_m4 + :goals: build flash + +.. note:: + + Flashing both M4 and M7 and pushing RESTART button on the board leads + to LD1 and LD2 flashing simultaneously. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h745zi_q_m7 + :maybe-skip-config: + :goals: debug + +Debugging with west is currently not available on Cortex M4 side. +In order to debug a Zephyr application on Cortex M4 side, you can use +`STM32CubeIDE`_. + +.. _Nucleo H745ZI-Q website: + https://www.st.com/en/evaluation-tools/nucleo-h745zi-q.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00499171-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf + +.. _STM32H745ZI on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h745zi.html + +.. _STM32H745 reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _OpenOCD installing Debug Version: + https://github.com/zephyrproject-rtos/openocd + +.. _OpenOCD installing with ST-LINK V3 support: + https://mbd.kleier.net/integrating-st-link-v3.html + +.. _STM32CubeIDE: + https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q.dtsi b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q.dtsi similarity index 100% rename from boards/arm/nucleo_h745zi_q/nucleo_h745zi_q.dtsi rename to boards/st/nucleo_h745zi_q/nucleo_h745zi_q.dtsi diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts similarity index 100% rename from boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.dts rename to boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml new file mode 100644 index 00000000000..19c2a5a1f1c --- /dev/null +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml @@ -0,0 +1,19 @@ +identifier: nucleo_h745zi_q/stm32h745xx/m4 +name: ST Nucleo H745ZI-Q (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 288 +flash: 1024 +supported: + - arduino_gpio + - gpio + - netif:eth +testing: + ignore_tags: + - mpu + - nfc +vendor: st diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig new file mode 100644 index 00000000000..2eb7224edab --- /dev/null +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2020 Alexander Kozhinov + +# Enable GPIO +CONFIG_GPIO=y + +# Enable clock +CONFIG_CLOCK_CONTROL=y + +# By default SERIAL peripherals are assigned to m7 + +# Enable uart driver +#CONFIG_SERIAL=y + +# Console +#CONFIG_CONSOLE=y +#CONFIG_UART_CONSOLE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts similarity index 100% rename from boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.dts rename to boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml new file mode 100644 index 00000000000..c480b150189 --- /dev/null +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml @@ -0,0 +1,20 @@ +identifier: nucleo_h745zi_q/stm32h745xx/m7 +name: ST Nucleo H745ZI-Q (M7) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 1024 +supported: + - arduino_gpio + - arduino_i2c + - uart + - gpio + - counter + - i2c + - pwm + - netif:eth +vendor: st diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig new file mode 100644 index 00000000000..a38b7cad80e --- /dev/null +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2020 Alexander Kozhinov + +# Enable the internal SMPS regulator +CONFIG_POWER_SUPPLY_DIRECT_SMPS=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART ( disable to assign to M4 core) +CONFIG_SERIAL=y + +# Console ( disable to assign to M4 core) +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Clock +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_h745zi_q/support/openocd.cfg b/boards/st/nucleo_h745zi_q/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_h745zi_q/support/openocd.cfg rename to boards/st/nucleo_h745zi_q/support/openocd.cfg diff --git a/boards/st/nucleo_h753zi/Kconfig.defconfig b/boards/st/nucleo_h753zi/Kconfig.defconfig new file mode 100644 index 00000000000..57c83698109 --- /dev/null +++ b/boards/st/nucleo_h753zi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32H753ZI Nucleo board configuration + +# Copyright (c) 2021 Blue Clover Devices +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H753ZI + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_H753ZI diff --git a/boards/st/nucleo_h753zi/Kconfig.nucleo_h753zi b/boards/st/nucleo_h753zi/Kconfig.nucleo_h753zi new file mode 100644 index 00000000000..2ca1de7fd93 --- /dev/null +++ b/boards/st/nucleo_h753zi/Kconfig.nucleo_h753zi @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Blue Clover Devices +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H753ZI + select SOC_STM32H753XX diff --git a/boards/arm/nucleo_h753zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h753zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h753zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_h753zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_h753zi/board.cmake b/boards/st/nucleo_h753zi/board.cmake similarity index 100% rename from boards/arm/nucleo_h753zi/board.cmake rename to boards/st/nucleo_h753zi/board.cmake diff --git a/boards/st/nucleo_h753zi/board.yml b/boards/st/nucleo_h753zi/board.yml new file mode 100644 index 00000000000..12dc4b5a501 --- /dev/null +++ b/boards/st/nucleo_h753zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h753zi + vendor: st + socs: + - name: stm32h753xx diff --git a/boards/arm/nucleo_h753zi/doc/img/nucleo_h753zi.jpg b/boards/st/nucleo_h753zi/doc/img/nucleo_h753zi.jpg similarity index 100% rename from boards/arm/nucleo_h753zi/doc/img/nucleo_h753zi.jpg rename to boards/st/nucleo_h753zi/doc/img/nucleo_h753zi.jpg diff --git a/boards/st/nucleo_h753zi/doc/index.rst b/boards/st/nucleo_h753zi/doc/index.rst new file mode 100644 index 00000000000..536d90d6310 --- /dev/null +++ b/boards/st/nucleo_h753zi/doc/index.rst @@ -0,0 +1,233 @@ +.. _nucleo_h753zi_board: + +ST Nucleo H753ZI +################ + +Overview +******** + +The STM32 Nucleo-144 boards offer combinations of performance and power that +provide an affordable and flexible way for users to build prototypes and try +out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) +significantly reduces power consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V2-1 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_h753zi.jpg + :align: center + :alt: Nucleo H753ZI + +More information about the board can be found at the `Nucleo H753ZI website`_. + +Hardware +******** + +Nucleo H753ZI provides the following hardware components: + +- STM32H753ZI in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 480 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 2 MB Flash +- 1 MB SRAM +- High-resolution timer (2.1 ns) +- 32-bit timers(2) +- 16-bit timers(12) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN FD(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 114) with external interrupt capability +- 16-bit ADC(3) with 36 channels / 3.6 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution +- Cryptographic acceleration: AES 128, 192, 256, TDES, HASH (MD5, SHA-1, SHA-2), HMAC +- Secure firmware upgrade support, Secure access mode + +Supported Features +================== + +The Zephyr nucleo_h753zi board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ +| CAN/CANFD | on-chip | canbus | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_h753zi/nucleo_h753zi_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H753ZI board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- I2C : PB8, PB9 +- ADC1_INP15 : PA3 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) +- CAN/CANFD : PD0, PD1 + +System Clock +------------ + +Nucleo H753ZI System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H753ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + +CAN, CANFD +---------- + +Requires an external CAN or CANFD transceiver. + +Programming and Debugging +************************* + +Applications for the ``nucleo_h753zi`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. note:: + + If using OpenOCD you will need a recent development version as the last + official release does not support H7 series yet. You can also choose the + ``stm32cubeprogrammer`` runner. + +Flashing +======== + +Nucleo H753ZI board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo H753ZI +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h753zi + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h753zi + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h753zi + :maybe-skip-config: + :goals: debug + +.. _Nucleo H753ZI website: + https://www.st.com/en/evaluation-tools/nucleo-h753zi.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32H753ZI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h743-753/stm32h753zi.html + +.. _STM32H753 reference manual: + https://www.st.com/resource/en/reference_manual/dm00314099.pdf diff --git a/boards/arm/nucleo_h753zi/nucleo_h753zi.dts b/boards/st/nucleo_h753zi/nucleo_h753zi.dts similarity index 100% rename from boards/arm/nucleo_h753zi/nucleo_h753zi.dts rename to boards/st/nucleo_h753zi/nucleo_h753zi.dts diff --git a/boards/arm/nucleo_h753zi/nucleo_h753zi.yaml b/boards/st/nucleo_h753zi/nucleo_h753zi.yaml similarity index 100% rename from boards/arm/nucleo_h753zi/nucleo_h753zi.yaml rename to boards/st/nucleo_h753zi/nucleo_h753zi.yaml diff --git a/boards/arm/nucleo_h753zi/nucleo_h753zi_defconfig b/boards/st/nucleo_h753zi/nucleo_h753zi_defconfig similarity index 85% rename from boards/arm/nucleo_h753zi/nucleo_h753zi_defconfig rename to boards/st/nucleo_h753zi/nucleo_h753zi_defconfig index 42eb8fd0f12..8dcaab60f61 100644 --- a/boards/arm/nucleo_h753zi/nucleo_h753zi_defconfig +++ b/boards/st/nucleo_h753zi/nucleo_h753zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H753XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_h753zi/support/openocd.cfg b/boards/st/nucleo_h753zi/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_h753zi/support/openocd.cfg rename to boards/st/nucleo_h753zi/support/openocd.cfg diff --git a/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig b/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig new file mode 100644 index 00000000000..e8fd3484ea7 --- /dev/null +++ b/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32H7A3ZI-Q Nucleo board configuration + +# Copyright (c) 2021 Electrolance Solutions +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H7A3ZI_Q + +config USB_DC_HAS_HS_SUPPORT + default y + depends on USB_DC_STM32 + +endif # BOARD_NUCLEO_H7A3ZI_Q diff --git a/boards/st/nucleo_h7a3zi_q/Kconfig.nucleo_h7a3zi_q b/boards/st/nucleo_h7a3zi_q/Kconfig.nucleo_h7a3zi_q new file mode 100644 index 00000000000..7a00b2bd8fe --- /dev/null +++ b/boards/st/nucleo_h7a3zi_q/Kconfig.nucleo_h7a3zi_q @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Electrolance Solutions +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H7A3ZI_Q + select SOC_STM32H7A3XXQ diff --git a/boards/arm/nucleo_h7a3zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/arduino_r3_connector.dtsi rename to boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_h7a3zi_q/board.cmake b/boards/st/nucleo_h7a3zi_q/board.cmake similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/board.cmake rename to boards/st/nucleo_h7a3zi_q/board.cmake diff --git a/boards/st/nucleo_h7a3zi_q/board.yml b/boards/st/nucleo_h7a3zi_q/board.yml new file mode 100644 index 00000000000..0c64ac88228 --- /dev/null +++ b/boards/st/nucleo_h7a3zi_q/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h7a3zi_q + vendor: st + socs: + - name: stm32h7a3xx diff --git a/boards/arm/nucleo_h7a3zi_q/doc/img/nucleo_h7a3zi_q.jpg b/boards/st/nucleo_h7a3zi_q/doc/img/nucleo_h7a3zi_q.jpg similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/doc/img/nucleo_h7a3zi_q.jpg rename to boards/st/nucleo_h7a3zi_q/doc/img/nucleo_h7a3zi_q.jpg diff --git a/boards/st/nucleo_h7a3zi_q/doc/index.rst b/boards/st/nucleo_h7a3zi_q/doc/index.rst new file mode 100644 index 00000000000..484c7e82196 --- /dev/null +++ b/boards/st/nucleo_h7a3zi_q/doc/index.rst @@ -0,0 +1,206 @@ +.. _nucleo_h7a3zi_q_board: + +ST Nucleo H7A3ZI-Q +################## + +Overview +******** + +The STM32 Nucleo-144 boards offer combinations of performance and power that +provide an affordable and flexible way for users to build prototypes and try +out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) +significantly reduces power consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V3E debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V3E debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_h7a3zi_q.jpg + :align: center + :alt: Nucleo H7A3ZI-Q + +More information about the board can be found at the `Nucleo H7A3ZI-Q website`_. + +Hardware +******** + +Nucleo H7A3ZI-Q provides the following hardware components: + +- STM32H7A3ZI in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 280 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 2 MB Flash +- ~1.4 Mbytes SRAM +- 32-bit timers(2) +- 16-bit timers(15) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(5) +- UART(5) +- USB OTG Full Speed and High Speed(1) +- CAN FD(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 114) with external interrupt capability +- 16-bit ADC(2) with 24 channels / 3.6 MSPS +- 12-bit DAC with 1/2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_h7a3zi_q board configuration supports the following hardware +features: + ++-------------+------------+------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+------------------------------------+ +| ADC | on-chip | adc | ++-------------+------------+------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+------------------------------------+ +| USB OTG HS | on-chip | USB device | ++-------------+------------+------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+------------------------------------+ + + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H7A3ZI-Q board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- USART3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PE1 +- LD3 : PB14 +- ADC1_INP15 : PA3 (Arduino analog, A0) + +System Clock +------------ + +Nucleo H7A3ZI-Q System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H7A3ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to USART3. Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``nucleo_h7a3zi_q`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo H7A3ZI-Q board includes an ST-LINK/V3E embedded debug tool interface. + +Flashing an application to Nucleo H7A3ZI-Q +------------------------------------------ + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h7a3zi_q + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h7a3zi_q + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h7a3zi_q + :maybe-skip-config: + :goals: debug + +.. _Nucleo H7A3ZI-Q website: + https://www.st.com/en/evaluation-tools/nucleo-h7a3zi-q.html#overview + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/um2408-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf + +.. _STM32H7A3ZI-Q on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3zi.html + +.. _STM32H7A3ZI-Q reference manual: + https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts rename to boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts diff --git a/boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml rename to boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml diff --git a/boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig similarity index 87% rename from boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig rename to boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig index 86ed02f8045..5490e9f1fc7 100644 --- a/boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig +++ b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2021 Electrolance Solutions # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H7A3XXQ=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_h7a3zi_q/support/openocd.cfg b/boards/st/nucleo_h7a3zi_q/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/support/openocd.cfg rename to boards/st/nucleo_h7a3zi_q/support/openocd.cfg diff --git a/boards/st/nucleo_l011k4/Kconfig.defconfig b/boards/st/nucleo_l011k4/Kconfig.defconfig new file mode 100644 index 00000000000..f05a90ff9b2 --- /dev/null +++ b/boards/st/nucleo_l011k4/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-32 development board with STM32L011K4 MCU + +# Copyright (c) 2020 Steven Daglish +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L011K4 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L011K4 diff --git a/boards/st/nucleo_l011k4/Kconfig.nucleo_l011k4 b/boards/st/nucleo_l011k4/Kconfig.nucleo_l011k4 new file mode 100644 index 00000000000..e83f4b27968 --- /dev/null +++ b/boards/st/nucleo_l011k4/Kconfig.nucleo_l011k4 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Steven Daglish +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L011K4 + select SOC_STM32L011XX diff --git a/boards/arm/nucleo_l011k4/board.cmake b/boards/st/nucleo_l011k4/board.cmake similarity index 100% rename from boards/arm/nucleo_l011k4/board.cmake rename to boards/st/nucleo_l011k4/board.cmake diff --git a/boards/st/nucleo_l011k4/board.yml b/boards/st/nucleo_l011k4/board.yml new file mode 100644 index 00000000000..be64789e754 --- /dev/null +++ b/boards/st/nucleo_l011k4/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l011k4 + vendor: st + socs: + - name: stm32l011xx diff --git a/boards/arm/nucleo_l011k4/doc/img/nucleo_l011k4.jpg b/boards/st/nucleo_l011k4/doc/img/nucleo_l011k4.jpg similarity index 100% rename from boards/arm/nucleo_l011k4/doc/img/nucleo_l011k4.jpg rename to boards/st/nucleo_l011k4/doc/img/nucleo_l011k4.jpg diff --git a/boards/st/nucleo_l011k4/doc/index.rst b/boards/st/nucleo_l011k4/doc/index.rst new file mode 100644 index 00000000000..7344ed734ad --- /dev/null +++ b/boards/st/nucleo_l011k4/doc/index.rst @@ -0,0 +1,167 @@ +.. _nucleo_l011k4_board: + +ST Nucleo L011K4 +################ + +Overview +******** +The STM32 Nucleo-32 development board with STM32L011K4 MCU, supports Arduino Nano V3 connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Nano V3 connectivity support allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_l011k4.jpg + :align: center + :alt: Nucleo L011K4 + +More information about the board can be found at the `Nucleo L011K4 website`_. + +Hardware +******** +Nucleo L011K4 provides the following hardware components: + +- STM32 microcontroller in LQFP32 package +- Extension resource: + + - Arduino* Nano V3 connectivity + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- One push-button: RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32L011K4 can be found in the +`STM32L0x1 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_l011k4 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l011k4/nucleo_l011k4_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PA4/PA10 (Arduino I2C) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) +- LD2 : PB3 + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_l011k4`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L011K4 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo L011K4 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_l011k4 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l011k4 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo L011K4 website: + https://www.st.com/en/evaluation-tools/nucleo-l011k4.html + +.. _STM32L0x1 reference manual: + https://www.st.com/resource/en/reference_manual/dm00108282-ultralowpower-stm32l0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l011k4/nucleo_l011k4.dts b/boards/st/nucleo_l011k4/nucleo_l011k4.dts similarity index 100% rename from boards/arm/nucleo_l011k4/nucleo_l011k4.dts rename to boards/st/nucleo_l011k4/nucleo_l011k4.dts diff --git a/boards/arm/nucleo_l011k4/nucleo_l011k4.yaml b/boards/st/nucleo_l011k4/nucleo_l011k4.yaml similarity index 100% rename from boards/arm/nucleo_l011k4/nucleo_l011k4.yaml rename to boards/st/nucleo_l011k4/nucleo_l011k4.yaml diff --git a/boards/arm/nucleo_l011k4/nucleo_l011k4_defconfig b/boards/st/nucleo_l011k4/nucleo_l011k4_defconfig similarity index 78% rename from boards/arm/nucleo_l011k4/nucleo_l011k4_defconfig rename to boards/st/nucleo_l011k4/nucleo_l011k4_defconfig index 62de04f9b1a..255389258c4 100644 --- a/boards/arm/nucleo_l011k4/nucleo_l011k4_defconfig +++ b/boards/st/nucleo_l011k4/nucleo_l011k4_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L011XX=y - # Kernel Options due to Low Memory (2k) CONFIG_MAIN_STACK_SIZE=320 CONFIG_IDLE_STACK_SIZE=100 diff --git a/boards/arm/nucleo_l011k4/support/openocd.cfg b/boards/st/nucleo_l011k4/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l011k4/support/openocd.cfg rename to boards/st/nucleo_l011k4/support/openocd.cfg diff --git a/boards/st/nucleo_l031k6/Kconfig.defconfig b/boards/st/nucleo_l031k6/Kconfig.defconfig new file mode 100644 index 00000000000..335784c4151 --- /dev/null +++ b/boards/st/nucleo_l031k6/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-32 development board with STM32L031K6 MCU + +# Copyright (c) 2020 Steven Daglish +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L031K6 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L031K6 diff --git a/boards/st/nucleo_l031k6/Kconfig.nucleo_l031k6 b/boards/st/nucleo_l031k6/Kconfig.nucleo_l031k6 new file mode 100644 index 00000000000..8e2c0345fc0 --- /dev/null +++ b/boards/st/nucleo_l031k6/Kconfig.nucleo_l031k6 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Steven Daglish +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L031K6 + select SOC_STM32L031XX diff --git a/boards/arm/nucleo_l031k6/arduino_nano_r3_connector.dtsi b/boards/st/nucleo_l031k6/arduino_nano_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l031k6/arduino_nano_r3_connector.dtsi rename to boards/st/nucleo_l031k6/arduino_nano_r3_connector.dtsi diff --git a/boards/arm/nucleo_l031k6/board.cmake b/boards/st/nucleo_l031k6/board.cmake similarity index 100% rename from boards/arm/nucleo_l031k6/board.cmake rename to boards/st/nucleo_l031k6/board.cmake diff --git a/boards/st/nucleo_l031k6/board.yml b/boards/st/nucleo_l031k6/board.yml new file mode 100644 index 00000000000..7fc334c0c2d --- /dev/null +++ b/boards/st/nucleo_l031k6/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l031k6 + vendor: st + socs: + - name: stm32l031xx diff --git a/boards/arm/nucleo_l031k6/doc/img/nucleo_l031k6.jpg b/boards/st/nucleo_l031k6/doc/img/nucleo_l031k6.jpg similarity index 100% rename from boards/arm/nucleo_l031k6/doc/img/nucleo_l031k6.jpg rename to boards/st/nucleo_l031k6/doc/img/nucleo_l031k6.jpg diff --git a/boards/st/nucleo_l031k6/doc/index.rst b/boards/st/nucleo_l031k6/doc/index.rst new file mode 100644 index 00000000000..543d0cc01f8 --- /dev/null +++ b/boards/st/nucleo_l031k6/doc/index.rst @@ -0,0 +1,160 @@ +.. _nucleo_l031k6_board: + +ST Nucleo L031K6 +################ + +Overview +******** +The STM32 Nucleo-32 development board with STM32L031K6 MCU, supports Arduino Nano V3 connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Nano V3 connectivity support allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_l031k6.jpg + :align: center + :alt: Nucleo L031K6 + +More information about the board can be found at the `Nucleo L031K6 website`_. + +Hardware +******** +Nucleo L031K6 provides the following hardware components: + +- STM32 microcontroller in LQFP32 package +- Extension resource: + + - Arduino* Nano V3 connectivity + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- One push-button: RESET + +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +More information about STM32L031K6 can be found in the +`STM32L0x1 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l031k6 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l031k6/nucleo_l031k6_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PA9/PA10 (Arduino I2C) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) +- LD2 : PB3 + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_l031k6`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo L031K6 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_l031k6 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l031k6 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo L031K6 website: + https://www.st.com/en/evaluation-tools/nucleo-l031k6.html + +.. _STM32L0x1 reference manual: + https://www.st.com/resource/en/reference_manual/dm00108282-ultralowpower-stm32l0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l031k6/nucleo_l031k6.dts b/boards/st/nucleo_l031k6/nucleo_l031k6.dts similarity index 100% rename from boards/arm/nucleo_l031k6/nucleo_l031k6.dts rename to boards/st/nucleo_l031k6/nucleo_l031k6.dts diff --git a/boards/arm/nucleo_l031k6/nucleo_l031k6.yaml b/boards/st/nucleo_l031k6/nucleo_l031k6.yaml similarity index 100% rename from boards/arm/nucleo_l031k6/nucleo_l031k6.yaml rename to boards/st/nucleo_l031k6/nucleo_l031k6.yaml diff --git a/boards/arm/nucleo_l031k6/nucleo_l031k6_defconfig b/boards/st/nucleo_l031k6/nucleo_l031k6_defconfig similarity index 78% rename from boards/arm/nucleo_l031k6/nucleo_l031k6_defconfig rename to boards/st/nucleo_l031k6/nucleo_l031k6_defconfig index 83745ca36af..06484e88bea 100644 --- a/boards/arm/nucleo_l031k6/nucleo_l031k6_defconfig +++ b/boards/st/nucleo_l031k6/nucleo_l031k6_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L031XX=y - # Kernel Options due to Low Memory (8k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/arm/nucleo_l031k6/support/openocd.cfg b/boards/st/nucleo_l031k6/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l031k6/support/openocd.cfg rename to boards/st/nucleo_l031k6/support/openocd.cfg diff --git a/boards/st/nucleo_l053r8/Kconfig.defconfig b/boards/st/nucleo_l053r8/Kconfig.defconfig new file mode 100644 index 00000000000..1e7c587a040 --- /dev/null +++ b/boards/st/nucleo_l053r8/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-64 development board with STM32L053R8 MCU + +# Copyright (c) 2018 Anthony Kreft +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L053R8 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L053R8 diff --git a/boards/st/nucleo_l053r8/Kconfig.nucleo_l053r8 b/boards/st/nucleo_l053r8/Kconfig.nucleo_l053r8 new file mode 100644 index 00000000000..69194b81d03 --- /dev/null +++ b/boards/st/nucleo_l053r8/Kconfig.nucleo_l053r8 @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Anthony Kreft +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L053R8 + select SOC_STM32L053XX diff --git a/boards/arm/nucleo_l053r8/arduino_r3_connector.dtsi b/boards/st/nucleo_l053r8/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l053r8/arduino_r3_connector.dtsi rename to boards/st/nucleo_l053r8/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l053r8/board.cmake b/boards/st/nucleo_l053r8/board.cmake similarity index 100% rename from boards/arm/nucleo_l053r8/board.cmake rename to boards/st/nucleo_l053r8/board.cmake diff --git a/boards/st/nucleo_l053r8/board.yml b/boards/st/nucleo_l053r8/board.yml new file mode 100644 index 00000000000..a31629d6443 --- /dev/null +++ b/boards/st/nucleo_l053r8/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l053r8 + vendor: st + socs: + - name: stm32l053xx diff --git a/boards/arm/nucleo_l053r8/doc/img/nucleo_l053r8.jpg b/boards/st/nucleo_l053r8/doc/img/nucleo_l053r8.jpg similarity index 100% rename from boards/arm/nucleo_l053r8/doc/img/nucleo_l053r8.jpg rename to boards/st/nucleo_l053r8/doc/img/nucleo_l053r8.jpg diff --git a/boards/arm/nucleo_l053r8/doc/img/nucleo_l053r8_connectors.jpg b/boards/st/nucleo_l053r8/doc/img/nucleo_l053r8_connectors.jpg similarity index 100% rename from boards/arm/nucleo_l053r8/doc/img/nucleo_l053r8_connectors.jpg rename to boards/st/nucleo_l053r8/doc/img/nucleo_l053r8_connectors.jpg diff --git a/boards/st/nucleo_l053r8/doc/index.rst b/boards/st/nucleo_l053r8/doc/index.rst new file mode 100644 index 00000000000..e8fdac96751 --- /dev/null +++ b/boards/st/nucleo_l053r8/doc/index.rst @@ -0,0 +1,176 @@ +.. _nucleo_l053r8_board: + +ST Nucleo L053R8 +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32L053R8 MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_l053r8.jpg + :align: center + :alt: Nucleo L053R8 + +More information about the board can be found at the `Nucleo L053R8 website`_. + +Hardware +******** +Nucleo L053R8 provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32L053R8 can be found in the +`STM32L0x3 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_l053r8 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l053r8/nucleo_l053r8_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_l053r8_connectors.jpg + :align: center + :alt: Nucleo L053R8 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) +- USER_PB : PC13 +- LD2 : PA5 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_l053r8`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L053R8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo L053R8 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_l053r8 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l053r8 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo L053R8 website: + https://www.st.com/en/evaluation-tools/nucleo-l053r8.html + +.. _STM32L0x3 reference manual: + https://www.st.com/resource/en/reference_manual/dm00095744.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l053r8/nucleo_l053r8.dts b/boards/st/nucleo_l053r8/nucleo_l053r8.dts similarity index 100% rename from boards/arm/nucleo_l053r8/nucleo_l053r8.dts rename to boards/st/nucleo_l053r8/nucleo_l053r8.dts diff --git a/boards/arm/nucleo_l053r8/nucleo_l053r8.yaml b/boards/st/nucleo_l053r8/nucleo_l053r8.yaml similarity index 100% rename from boards/arm/nucleo_l053r8/nucleo_l053r8.yaml rename to boards/st/nucleo_l053r8/nucleo_l053r8.yaml diff --git a/boards/arm/nucleo_l053r8/nucleo_l053r8_defconfig b/boards/st/nucleo_l053r8/nucleo_l053r8_defconfig similarity index 79% rename from boards/arm/nucleo_l053r8/nucleo_l053r8_defconfig rename to boards/st/nucleo_l053r8/nucleo_l053r8_defconfig index 154565653da..7742224e030 100644 --- a/boards/arm/nucleo_l053r8/nucleo_l053r8_defconfig +++ b/boards/st/nucleo_l053r8/nucleo_l053r8_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L053XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_l053r8/st_morpho_connector.dtsi b/boards/st/nucleo_l053r8/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l053r8/st_morpho_connector.dtsi rename to boards/st/nucleo_l053r8/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_l053r8/support/openocd.cfg b/boards/st/nucleo_l053r8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l053r8/support/openocd.cfg rename to boards/st/nucleo_l053r8/support/openocd.cfg diff --git a/boards/st/nucleo_l073rz/Kconfig.defconfig b/boards/st/nucleo_l073rz/Kconfig.defconfig new file mode 100644 index 00000000000..5d5c910151f --- /dev/null +++ b/boards/st/nucleo_l073rz/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-64 development board with STM32L073RZ MCU + +# Copyright (c) 2018 Ilya Tagunov +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L073RZ + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L073RZ diff --git a/boards/st/nucleo_l073rz/Kconfig.nucleo_l073rz b/boards/st/nucleo_l073rz/Kconfig.nucleo_l073rz new file mode 100644 index 00000000000..06e54aa03c4 --- /dev/null +++ b/boards/st/nucleo_l073rz/Kconfig.nucleo_l073rz @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Ilya Tagunov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L073RZ + select SOC_STM32L073XX diff --git a/boards/arm/nucleo_l073rz/arduino_r3_connector.dtsi b/boards/st/nucleo_l073rz/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l073rz/arduino_r3_connector.dtsi rename to boards/st/nucleo_l073rz/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l073rz/board.cmake b/boards/st/nucleo_l073rz/board.cmake similarity index 100% rename from boards/arm/nucleo_l073rz/board.cmake rename to boards/st/nucleo_l073rz/board.cmake diff --git a/boards/st/nucleo_l073rz/board.yml b/boards/st/nucleo_l073rz/board.yml new file mode 100644 index 00000000000..232170aa06d --- /dev/null +++ b/boards/st/nucleo_l073rz/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l073rz + vendor: st + socs: + - name: stm32l073xx diff --git a/boards/arm/nucleo_l073rz/doc/img/nucleo_l073rz.jpg b/boards/st/nucleo_l073rz/doc/img/nucleo_l073rz.jpg similarity index 100% rename from boards/arm/nucleo_l073rz/doc/img/nucleo_l073rz.jpg rename to boards/st/nucleo_l073rz/doc/img/nucleo_l073rz.jpg diff --git a/boards/arm/nucleo_l073rz/doc/img/nucleo_l073rz_connectors.jpg b/boards/st/nucleo_l073rz/doc/img/nucleo_l073rz_connectors.jpg similarity index 100% rename from boards/arm/nucleo_l073rz/doc/img/nucleo_l073rz_connectors.jpg rename to boards/st/nucleo_l073rz/doc/img/nucleo_l073rz_connectors.jpg diff --git a/boards/st/nucleo_l073rz/doc/index.rst b/boards/st/nucleo_l073rz/doc/index.rst new file mode 100644 index 00000000000..4c4ca788ddd --- /dev/null +++ b/boards/st/nucleo_l073rz/doc/index.rst @@ -0,0 +1,190 @@ +.. _nucleo_l073rz_board: + +ST Nucleo L073RZ +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32L073RZ MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_l073rz.jpg + :align: center + :alt: Nucleo L073RZ + +More information about the board can be found at the `Nucleo L073RZ website`_. + +Hardware +******** +Nucleo L073RZ provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32L073RZ can be found in the +`STM32L0x3 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_l073rz board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | Random Number Generator | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l073rz/nucleo_l073rz_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_l073rz_connectors.jpg + :align: center + :alt: Nucleo L073RZ connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) +- USER_PB : PC13 +- LD2 : PA5 +- DAC : PA4 +- PWM_2_CH1 : PA5 (might conflict with SPI1) + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_l073rz`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L073RZ board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo L073RZ +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_l073rz + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l073rz + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo L073RZ website: + https://www.st.com/en/evaluation-tools/nucleo-l073rz.html + +.. _STM32L0x3 reference manual: + https://www.st.com/resource/en/reference_manual/dm00095744.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l073rz/nucleo_l073rz.dts b/boards/st/nucleo_l073rz/nucleo_l073rz.dts similarity index 100% rename from boards/arm/nucleo_l073rz/nucleo_l073rz.dts rename to boards/st/nucleo_l073rz/nucleo_l073rz.dts diff --git a/boards/arm/nucleo_l073rz/nucleo_l073rz.yaml b/boards/st/nucleo_l073rz/nucleo_l073rz.yaml similarity index 100% rename from boards/arm/nucleo_l073rz/nucleo_l073rz.yaml rename to boards/st/nucleo_l073rz/nucleo_l073rz.yaml diff --git a/boards/st/nucleo_l073rz/nucleo_l073rz_defconfig b/boards/st/nucleo_l073rz/nucleo_l073rz_defconfig new file mode 100644 index 00000000000..f877d5b620a --- /dev/null +++ b/boards/st/nucleo_l073rz/nucleo_l073rz_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_l073rz/st_morpho_connector.dtsi b/boards/st/nucleo_l073rz/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l073rz/st_morpho_connector.dtsi rename to boards/st/nucleo_l073rz/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_l073rz/support/openocd.cfg b/boards/st/nucleo_l073rz/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l073rz/support/openocd.cfg rename to boards/st/nucleo_l073rz/support/openocd.cfg diff --git a/boards/st/nucleo_l152re/Kconfig.nucleo_l152re b/boards/st/nucleo_l152re/Kconfig.nucleo_l152re new file mode 100644 index 00000000000..04252bf55d4 --- /dev/null +++ b/boards/st/nucleo_l152re/Kconfig.nucleo_l152re @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Antony Pavlov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L152RE + select SOC_STM32L152XE diff --git a/boards/arm/nucleo_l152re/arduino_r3_connector.dtsi b/boards/st/nucleo_l152re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l152re/arduino_r3_connector.dtsi rename to boards/st/nucleo_l152re/arduino_r3_connector.dtsi diff --git a/boards/arm/cc3220sf_launchxl/board.cmake b/boards/st/nucleo_l152re/board.cmake similarity index 100% rename from boards/arm/cc3220sf_launchxl/board.cmake rename to boards/st/nucleo_l152re/board.cmake diff --git a/boards/st/nucleo_l152re/board.yml b/boards/st/nucleo_l152re/board.yml new file mode 100644 index 00000000000..2838a81f7b0 --- /dev/null +++ b/boards/st/nucleo_l152re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l152re + vendor: st + socs: + - name: stm32l152xe diff --git a/boards/arm/nucleo_l152re/doc/img/nucleo_l152re.jpg b/boards/st/nucleo_l152re/doc/img/nucleo_l152re.jpg similarity index 100% rename from boards/arm/nucleo_l152re/doc/img/nucleo_l152re.jpg rename to boards/st/nucleo_l152re/doc/img/nucleo_l152re.jpg diff --git a/boards/arm/nucleo_l152re/doc/img/nucleo_l152re_connectors.jpg b/boards/st/nucleo_l152re/doc/img/nucleo_l152re_connectors.jpg similarity index 100% rename from boards/arm/nucleo_l152re/doc/img/nucleo_l152re_connectors.jpg rename to boards/st/nucleo_l152re/doc/img/nucleo_l152re_connectors.jpg diff --git a/boards/st/nucleo_l152re/doc/index.rst b/boards/st/nucleo_l152re/doc/index.rst new file mode 100644 index 00000000000..9d8e31a6a6e --- /dev/null +++ b/boards/st/nucleo_l152re/doc/index.rst @@ -0,0 +1,187 @@ +.. _nucleo_l152re_board: + +ST Nucleo L152RE +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32L152RE MCU, supports Arduino™ and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The Arduino Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_l152re.jpg + :align: center + :alt: NUCLEO-L152RE + +More information about the board can be found at the `Nucleo L152RE website`_. + +Hardware +******** +Nucleo L152RE provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: B1 (USER/blue) and B2 (RESET/black) +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +More information about STM32L152RE can be found here: + +- `STM32L152 reference manual`_ +- `STM32L152 data sheet`_ + +Supported Features +================== + +The Zephyr nucleo_l152re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_l152re/nucleo_l152re_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_l152re_connectors.jpg + :align: center + :alt: Nucleo L152RE connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- B1 (USER/blue) : PC13 +- LD1 : PA5 +- DAC : PA4 +- PWM_3_CH1 : PA6 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_l152re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L152RE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo L152RE +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_l152re + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l152re + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo L152RE website: + https://www.st.com/en/evaluation-tools/nucleo-l152re.html + +.. _STM32L152 reference manual: + https://www.st.com/resource/en/reference_manual/cd00240193.pdf + +.. _STM32L152 data sheet: + https://www.st.com/resource/en/datasheet/stm32l152re.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l152re/nucleo_l152re.dts b/boards/st/nucleo_l152re/nucleo_l152re.dts similarity index 100% rename from boards/arm/nucleo_l152re/nucleo_l152re.dts rename to boards/st/nucleo_l152re/nucleo_l152re.dts diff --git a/boards/arm/nucleo_l152re/nucleo_l152re.yaml b/boards/st/nucleo_l152re/nucleo_l152re.yaml similarity index 100% rename from boards/arm/nucleo_l152re/nucleo_l152re.yaml rename to boards/st/nucleo_l152re/nucleo_l152re.yaml diff --git a/boards/arm/nucleo_l152re/nucleo_l152re_defconfig b/boards/st/nucleo_l152re/nucleo_l152re_defconfig similarity index 85% rename from boards/arm/nucleo_l152re/nucleo_l152re_defconfig rename to boards/st/nucleo_l152re/nucleo_l152re_defconfig index b8045bd70a5..02fb0a26c54 100644 --- a/boards/arm/nucleo_l152re/nucleo_l152re_defconfig +++ b/boards/st/nucleo_l152re/nucleo_l152re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L1X=y -CONFIG_SOC_STM32L152XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_l152re/st_morpho_connector.dtsi b/boards/st/nucleo_l152re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l152re/st_morpho_connector.dtsi rename to boards/st/nucleo_l152re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_l152re/support/openocd.cfg b/boards/st/nucleo_l152re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l152re/support/openocd.cfg rename to boards/st/nucleo_l152re/support/openocd.cfg diff --git a/boards/st/nucleo_l412rb_p/Kconfig.defconfig b/boards/st/nucleo_l412rb_p/Kconfig.defconfig new file mode 100644 index 00000000000..1ea0e9a194a --- /dev/null +++ b/boards/st/nucleo_l412rb_p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32L412RB Nucleo board configuration + +# Copyright (c) 2021 Guðni Már Gilbert +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L412RB_P + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L412RB_P diff --git a/boards/st/nucleo_l412rb_p/Kconfig.nucleo_l412rb_p b/boards/st/nucleo_l412rb_p/Kconfig.nucleo_l412rb_p new file mode 100644 index 00000000000..9faaea40854 --- /dev/null +++ b/boards/st/nucleo_l412rb_p/Kconfig.nucleo_l412rb_p @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Guðni Már Gilbert +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L412RB_P + select SOC_STM32L412XX diff --git a/boards/arm/nucleo_l412rb_p/arduino_r3_connector.dtsi b/boards/st/nucleo_l412rb_p/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l412rb_p/arduino_r3_connector.dtsi rename to boards/st/nucleo_l412rb_p/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l412rb_p/board.cmake b/boards/st/nucleo_l412rb_p/board.cmake similarity index 100% rename from boards/arm/nucleo_l412rb_p/board.cmake rename to boards/st/nucleo_l412rb_p/board.cmake diff --git a/boards/st/nucleo_l412rb_p/board.yml b/boards/st/nucleo_l412rb_p/board.yml new file mode 100644 index 00000000000..92ab56d2df3 --- /dev/null +++ b/boards/st/nucleo_l412rb_p/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l412rb_p + vendor: st + socs: + - name: stm32l412xx diff --git a/boards/arm/nucleo_l412rb_p/doc/img/nucleo_l412rb_p.jpg b/boards/st/nucleo_l412rb_p/doc/img/nucleo_l412rb_p.jpg similarity index 100% rename from boards/arm/nucleo_l412rb_p/doc/img/nucleo_l412rb_p.jpg rename to boards/st/nucleo_l412rb_p/doc/img/nucleo_l412rb_p.jpg diff --git a/boards/arm/nucleo_l412rb_p/doc/img/nucleo_l412rb_p_pinout.jpg b/boards/st/nucleo_l412rb_p/doc/img/nucleo_l412rb_p_pinout.jpg similarity index 100% rename from boards/arm/nucleo_l412rb_p/doc/img/nucleo_l412rb_p_pinout.jpg rename to boards/st/nucleo_l412rb_p/doc/img/nucleo_l412rb_p_pinout.jpg diff --git a/boards/st/nucleo_l412rb_p/doc/index.rst b/boards/st/nucleo_l412rb_p/doc/index.rst new file mode 100644 index 00000000000..b423f06c174 --- /dev/null +++ b/boards/st/nucleo_l412rb_p/doc/index.rst @@ -0,0 +1,269 @@ +.. _nucleo_l412rb_p_board: + +ST Nucleo L412RB-P +################## + +Overview +******** + +The Nucleo L412RB board features an ARM Cortex-M4 based STM32L412RB MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L412RB board: + +- STM32 microcontroller in LQFP64 package +- 1 user LED shared with ARDUINO |reg| +- 1 user and 1 reset push-buttons +- 32.768 kHz crystal oscillator +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port and debug port +- Flexible power-supply options: ST-LINK, USB VBUS, or external sources + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Board specific features + + - External SMPS to generate Vcore logic supply + - 24 MHz HSE + - Board connectors: + + - External SMPS experimentation dedicated connector + - Micro-AB or Mini-AB USB connector for the ST-LINK + - MIPI® debug connector + + - Arm® Mbed Enabled |trade| compliant + +.. image:: img/nucleo_l412rb_p.jpg + :align: center + :alt: Nucleo L412RB + +More information about the board can be found at the `Nucleo L412RB-P website`_. + +Hardware +******** + +Nucleo L412RB-P provides the following hardware components: + +- STM32L412RBT6 in LQFP64 package +- Ultra-low-power with FlexPowerControl + + - 1.71 V to 3.6 V power supply + - -40 °C to 85/125 °C temperature range + - 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers + - 16 nA Shutdown mode (4 wakeup pins) + - 32 nA Standby mode (4 wakeup pins) + - 245 nA Standby mode with RTC + - 0.7 |micro| A Stop 2 mode, 0.95 |micro| A with RTC + - 79 |micro| A/MHz run mode (LDO Mode) + - 28 |micro| A/MHz run mode (@3.3 V SMPS Mode) + - Batch acquisition mode (BAM) + - 4 |micro| s wakeup from Stop mode + - Brown out reset (BOR) + - Interconnect matrix + +- Core: Arm |reg| 32-bit Cortex |reg| -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator |trade| ) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions +- Performance benchmark + + - 1.25 DMIPS/MHz (Drystone 2.1) + - 273.55 CoreMark |reg| (3.42 CoreMark/MHz @ 80 MHz) + +- Energy benchmark + + - 442 ULPMark-CP® + - 165 ULPMark-PP® + +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than |plusminus| 0.25 % accuracy) + - Internal 48 MHz with clock recovery + - PLL for system clock + +- Up to 52 fast I/Os, most 5 V-tolerant +- RTC with HW calendar, alarms and calibration +- Up to 12 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 10x timers: + + - 1x 16-bit advanced motor-control + - 1x 32-bit and 2x 16-bit general purpose + - 1x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Memories + + - 128 KB single bank Flash, proprietary code readout protection + - 40 KB of SRAM including 8 KB with hardware parity check + - Quad SPI memory interface with XIP capability + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 |micro| A/Msps + - 2x operational amplifiers with built-in PGA + - 1x ultra-low-power comparator + - Accurate 2.5 V or 2.048 V reference voltage buffered output + +- 12x communication interfaces + - USB 2.0 full-speed crystal less solution with LPM and BCD + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 3x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART (Stop 2 wake-up) + - 2x SPIs (and 1x Quad SPI) + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| +- All packages are ECOPACK2 compliant + +Note: the current board revision is C. (MB1319C) + +More information about STM32L412RB can be found here: + +- `STM32L412RB on www.st.com`_ +- `STM32L412 reference manual`_ + +Supported Features +================== + +The Zephyr ``nucleo_l412rb_p`` board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig` + + +Connections and IOs +=================== + +Nucleo L412RB-P Board has 5 GPIO controllers (Ports A, B, C, D and H). These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_l412rb_p_pinout.jpg + :align: center + :alt: Nucleo L412RB-P + +For more details please refer to `ST Nucleo L412RB-P User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- LPUART1 TX/RX : PA2/PA3 +- I2C1 SCL/SDA : PB8/PB7 (Arduino I2C) +- SPI2 CS/SCK/MISO/MOSI : PA11/PB13/PB14/PB15 (Arduino SPI) +- UART1 TX/RX : PA9/PA10 +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD4 : PB13 + +Note: SPI2 CS pin (PB12) is not located on the Arduino connector. + +System Clock +------------ + +Nucleo L412RB-P System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L412RB-P board has 3 U(S)ARTs and 1 LPUART. The Zephyr console output is assigned to LPUART1. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l412rb_p`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L412RB-P board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Nucleo L412RB-P +------------------------------------------ + +Connect the Nucleo L412RB-P to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l412rb_p + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_l412rb_p + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l412rb_p + :maybe-skip-config: + :goals: debug + +.. _Nucleo L412RB-P website: + https://www.st.com/en/evaluation-tools/nucleo-l412rb-p.html + +.. _ST Nucleo L412RB-P User Manual: + https://www.st.com/resource/en/user_manual/dm00387966-stm32-nucleo-64-p-boards-stmicroelectronics.pdf + +.. _STM32L412RB on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l412rb.html + +.. _STM32L412 reference manual: + https://www.st.com/resource/en/reference_manual/dm00151940-stm32l41xxx42xxx43xxx44xxx45xxx46xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l412rb_p/nucleo_l412rb_p.dts b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.dts similarity index 100% rename from boards/arm/nucleo_l412rb_p/nucleo_l412rb_p.dts rename to boards/st/nucleo_l412rb_p/nucleo_l412rb_p.dts diff --git a/boards/arm/nucleo_l412rb_p/nucleo_l412rb_p.yaml b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.yaml similarity index 100% rename from boards/arm/nucleo_l412rb_p/nucleo_l412rb_p.yaml rename to boards/st/nucleo_l412rb_p/nucleo_l412rb_p.yaml diff --git a/boards/arm/nucleo_l412rb_p/nucleo_l412rb_p_defconfig b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig similarity index 85% rename from boards/arm/nucleo_l412rb_p/nucleo_l412rb_p_defconfig rename to boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig index a3541daa6f6..349e958591e 100644 --- a/boards/arm/nucleo_l412rb_p/nucleo_l412rb_p_defconfig +++ b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L412XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_l412rb_p/support/openocd.cfg b/boards/st/nucleo_l412rb_p/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l412rb_p/support/openocd.cfg rename to boards/st/nucleo_l412rb_p/support/openocd.cfg diff --git a/boards/st/nucleo_l432kc/Kconfig.defconfig b/boards/st/nucleo_l432kc/Kconfig.defconfig new file mode 100644 index 00000000000..2820946d23a --- /dev/null +++ b/boards/st/nucleo_l432kc/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32L432KC Nucleo board configuration + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L432KC + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L432KC diff --git a/boards/st/nucleo_l432kc/Kconfig.nucleo_l432kc b/boards/st/nucleo_l432kc/Kconfig.nucleo_l432kc new file mode 100644 index 00000000000..800f96f6c01 --- /dev/null +++ b/boards/st/nucleo_l432kc/Kconfig.nucleo_l432kc @@ -0,0 +1,5 @@ +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L432KC + select SOC_STM32L432XX diff --git a/boards/arm/nucleo_l432kc/board.cmake b/boards/st/nucleo_l432kc/board.cmake similarity index 100% rename from boards/arm/nucleo_l432kc/board.cmake rename to boards/st/nucleo_l432kc/board.cmake diff --git a/boards/st/nucleo_l432kc/board.yml b/boards/st/nucleo_l432kc/board.yml new file mode 100644 index 00000000000..25ccfc0ddf9 --- /dev/null +++ b/boards/st/nucleo_l432kc/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l432kc + vendor: st + socs: + - name: stm32l432xx diff --git a/boards/arm/nucleo_l432kc/doc/img/nucleo_l432kc.jpg b/boards/st/nucleo_l432kc/doc/img/nucleo_l432kc.jpg similarity index 100% rename from boards/arm/nucleo_l432kc/doc/img/nucleo_l432kc.jpg rename to boards/st/nucleo_l432kc/doc/img/nucleo_l432kc.jpg diff --git a/boards/arm/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.jpg b/boards/st/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.jpg similarity index 100% rename from boards/arm/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.jpg rename to boards/st/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.jpg diff --git a/boards/st/nucleo_l432kc/doc/index.rst b/boards/st/nucleo_l432kc/doc/index.rst new file mode 100644 index 00000000000..ddbfaec6a80 --- /dev/null +++ b/boards/st/nucleo_l432kc/doc/index.rst @@ -0,0 +1,229 @@ +.. _nucleo_l432kc_board: + +ST Nucleo L432KC +################ + +Overview +******** + +The Nucleo L432KC board features an ARM Cortex-M4 based STM32L432KC MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L432KC board: + +- STM32 microcontroller in UFQFPN32 package +- Arduino Uno V3 connectivity +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), power LED (LD2), user LED (LD3) +- One push-button: RESET + +.. image:: img/nucleo_l432kc.jpg + :align: center + :alt: Nucleo L432KC + +More information about the board can be found at the `Nucleo L432KC website`_. + +Hardware +******** + +The STM32L432KC SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, + 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 2 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 11x timers: + + - 1x 16-bit advanced motor-control + - 1x 32-bit and 2x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 26 fast I/Os, most 5 V-tolerant +- Memories + + - Up to 256 KB single bank Flash, proprietary code readout protection + - Up to 64 KB of SRAM including 16 KB with hardware parity check + - Quad SPI memory interface + +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 1x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 13x communication interfaces + + - USB OTG 2.0 full-speed crystal less solution with LPM and BCD + - 1x SAIs (serial audio interface) + - 2x I2C FM+(1 Mbit/s), SMBus/PMBus + - 3x USARTs (ISO 7816, LIN, IrDA, modem) + - 2x SPIs (3x SPIs with the Quad SPI) + - CAN (2.0B Active) + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32L432KC can be found here: + +- `STM32L432KC on www.st.com`_ +- `STM32L432 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l432kc board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l432kc/nucleo_l432kc_defconfig` + + +Connections and IOs +=================== + +Nucleo L432KC Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_l432kc_arduino_nano.jpg + :align: center + :alt: Nucleo L432KC Arduino connectors + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- I2C_1_SCL : PB6 +- I2C_1_SDA : PB7 +- PWM_2_CH1 : PA0 +- LD3 : PB3 + +System Clock +------------ + +Nucleo L432KC System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L432KC board has 3 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l432kc`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L432KC board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Nucleo L432KC +---------------------------------------- + +Connect the Nucleo L432KC to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l432kc + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l432kc + :maybe-skip-config: + :goals: debug + +.. _Nucleo L432KC website: + https://www.st.com/en/evaluation-tools/nucleo-l432kc.html + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744.pdf + +.. _STM32L432KC on www.st.com: + https://www.st.com/en/microcontrollers/stm32l432kc.html + +.. _STM32L432 reference manual: + https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l432kc/nucleo_l432kc.dts b/boards/st/nucleo_l432kc/nucleo_l432kc.dts similarity index 100% rename from boards/arm/nucleo_l432kc/nucleo_l432kc.dts rename to boards/st/nucleo_l432kc/nucleo_l432kc.dts diff --git a/boards/arm/nucleo_l432kc/nucleo_l432kc.yaml b/boards/st/nucleo_l432kc/nucleo_l432kc.yaml similarity index 100% rename from boards/arm/nucleo_l432kc/nucleo_l432kc.yaml rename to boards/st/nucleo_l432kc/nucleo_l432kc.yaml diff --git a/boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig b/boards/st/nucleo_l432kc/nucleo_l432kc_defconfig similarity index 85% rename from boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig rename to boards/st/nucleo_l432kc/nucleo_l432kc_defconfig index d4bf42213f4..82ee7285d52 100644 --- a/boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig +++ b/boards/st/nucleo_l432kc/nucleo_l432kc_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L432XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_l432kc/support/openocd.cfg b/boards/st/nucleo_l432kc/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l432kc/support/openocd.cfg rename to boards/st/nucleo_l432kc/support/openocd.cfg diff --git a/boards/st/nucleo_l433rc_p/Kconfig.defconfig b/boards/st/nucleo_l433rc_p/Kconfig.defconfig new file mode 100644 index 00000000000..5db4cd8f6d3 --- /dev/null +++ b/boards/st/nucleo_l433rc_p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32L433RC Nucleo board configuration + +# Copyright (c) 2021 Matija Tudan +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L433RC_P + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L433RC_P diff --git a/boards/st/nucleo_l433rc_p/Kconfig.nucleo_l433rc_p b/boards/st/nucleo_l433rc_p/Kconfig.nucleo_l433rc_p new file mode 100644 index 00000000000..e2e57e6890b --- /dev/null +++ b/boards/st/nucleo_l433rc_p/Kconfig.nucleo_l433rc_p @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Matija Tudan +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L433RC_P + select SOC_STM32L433XX diff --git a/boards/arm/nucleo_l433rc_p/arduino_r3_connector.dtsi b/boards/st/nucleo_l433rc_p/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l433rc_p/arduino_r3_connector.dtsi rename to boards/st/nucleo_l433rc_p/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l433rc_p/board.cmake b/boards/st/nucleo_l433rc_p/board.cmake similarity index 100% rename from boards/arm/nucleo_l433rc_p/board.cmake rename to boards/st/nucleo_l433rc_p/board.cmake diff --git a/boards/st/nucleo_l433rc_p/board.yml b/boards/st/nucleo_l433rc_p/board.yml new file mode 100644 index 00000000000..03c1f3c6f6f --- /dev/null +++ b/boards/st/nucleo_l433rc_p/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l433rc_p + vendor: st + socs: + - name: stm32l433xx diff --git a/boards/arm/nucleo_l433rc_p/doc/img/nucleo_l433rc_p.jpg b/boards/st/nucleo_l433rc_p/doc/img/nucleo_l433rc_p.jpg similarity index 100% rename from boards/arm/nucleo_l433rc_p/doc/img/nucleo_l433rc_p.jpg rename to boards/st/nucleo_l433rc_p/doc/img/nucleo_l433rc_p.jpg diff --git a/boards/arm/nucleo_l433rc_p/doc/img/nucleo_l433rc_p_pinout.jpg b/boards/st/nucleo_l433rc_p/doc/img/nucleo_l433rc_p_pinout.jpg similarity index 100% rename from boards/arm/nucleo_l433rc_p/doc/img/nucleo_l433rc_p_pinout.jpg rename to boards/st/nucleo_l433rc_p/doc/img/nucleo_l433rc_p_pinout.jpg diff --git a/boards/st/nucleo_l433rc_p/doc/index.rst b/boards/st/nucleo_l433rc_p/doc/index.rst new file mode 100644 index 00000000000..8981c68b236 --- /dev/null +++ b/boards/st/nucleo_l433rc_p/doc/index.rst @@ -0,0 +1,234 @@ +.. _nucleo_l433rc_board: + +ST Nucleo L433RC +################ + +Overview +******** + +The Nucleo L433RC board features an ARM Cortex-M4 based STM32L433RC MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L433RC board: + +- STM32 microcontroller in LQFP64 package +- Arduino Uno V3 connectivity +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD4) +- One push-button: RESET + +.. image:: img/nucleo_l433rc_p.jpg + :align: center + :alt: Nucleo L433RC + +More information about the board can be found at the `Nucleo L433RC-P website`_. + +Hardware +******** + +The STM32L433RC SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, + 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 2 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- Up to 21 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 11x timers: + + - 1x 16-bit advanced motor-control + - 1x 32-bit and 2x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 83 fast I/Os, most 5 V-tolerant +- Memories + + - Up to 256 KB single bank Flash, proprietary code readout protection + - 64 KB of SRAM including 16 KB with hardware parity check + - Quad SPI memory interface + +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 2x 12-bit DAC output channels, low-power sample and hold + - 1x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 17x communication interfaces + + - USB 2.0 full-speed crystal less solution with LPM and BCD + - 1x SAI (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART (Stop 2 wake-up) + - 3x SPIs (and 1x Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32L433RC can be found here: + +- `STM32L433RC on www.st.com`_ +- `STM32L432 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l433rc_p board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig` + + +Connections and IOs +=================== + +Nucleo L433RC-P Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_l433rc_p_pinout.jpg + :align: center + :alt: Nucleo L433RC-P + +For more details please refer to `ST Nucleo L433RC-P User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- LPUART_1_TX : PA2 +- LPUART_1_RX : PA3 +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- I2C_1_SCL : PB6 +- I2C_1_SDA : PB7 +- PWM_2_CH1 : PA0 +- LD4 : PB13 +- SPI_1: NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 +- SPI_2: NSS/SCK/MISO/MOSI : PA11/PB13/PB14/PB15 (Arduino SPI) + +System Clock +------------ + +Nucleo L433RC-P System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L433RC-P board has 4 U(S)ARTs and 1 LPUART. The Zephyr console output is assigned +to LPUART1. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l433rc_p`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L433RC-P board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Nucleo L433RC-P +------------------------------------------ + +Connect the Nucleo L433RC-P to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ picocom /dev/ttyACM0 -b 115200 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l433rc_p + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_l433rc_p + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l433rc_p + :maybe-skip-config: + :goals: debug + +.. _Nucleo L433RC-P website: + https://www.st.com/en/evaluation-tools/nucleo-l433rc-p.html + +.. _ST Nucleo L433RC-P User Manual: + https://www.st.com/resource/en/user_manual/dm00387966.pdf + +.. _STM32L433RC on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l433rc.html + +.. _STM32L432 reference manual: + https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l433rc_p/nucleo_l433rc_p.dts b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p.dts similarity index 100% rename from boards/arm/nucleo_l433rc_p/nucleo_l433rc_p.dts rename to boards/st/nucleo_l433rc_p/nucleo_l433rc_p.dts diff --git a/boards/arm/nucleo_l433rc_p/nucleo_l433rc_p.yaml b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p.yaml similarity index 100% rename from boards/arm/nucleo_l433rc_p/nucleo_l433rc_p.yaml rename to boards/st/nucleo_l433rc_p/nucleo_l433rc_p.yaml diff --git a/boards/arm/nucleo_l433rc_p/nucleo_l433rc_p_defconfig b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig similarity index 85% rename from boards/arm/nucleo_l433rc_p/nucleo_l433rc_p_defconfig rename to boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig index 72a116e3fec..82ee7285d52 100644 --- a/boards/arm/nucleo_l433rc_p/nucleo_l433rc_p_defconfig +++ b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L433XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_l433rc_p/support/openocd.cfg b/boards/st/nucleo_l433rc_p/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l433rc_p/support/openocd.cfg rename to boards/st/nucleo_l433rc_p/support/openocd.cfg diff --git a/boards/st/nucleo_l452re/Kconfig.defconfig b/boards/st/nucleo_l452re/Kconfig.defconfig new file mode 100644 index 00000000000..1758af6e18c --- /dev/null +++ b/boards/st/nucleo_l452re/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32L452RE Nucleo board configuration +# +# Copyright (c) 2019 Libre Solar Technologies GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L452RE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L452RE diff --git a/boards/st/nucleo_l452re/Kconfig.nucleo_l452re b/boards/st/nucleo_l452re/Kconfig.nucleo_l452re new file mode 100644 index 00000000000..08df2bfc05f --- /dev/null +++ b/boards/st/nucleo_l452re/Kconfig.nucleo_l452re @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Libre Solar Technologies GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L452RE + select SOC_STM32L452XX diff --git a/boards/arm/nucleo_l452re/arduino_r3_connector.dtsi b/boards/st/nucleo_l452re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l452re/arduino_r3_connector.dtsi rename to boards/st/nucleo_l452re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l452re/board.cmake b/boards/st/nucleo_l452re/board.cmake similarity index 100% rename from boards/arm/nucleo_l452re/board.cmake rename to boards/st/nucleo_l452re/board.cmake diff --git a/boards/st/nucleo_l452re/board.yml b/boards/st/nucleo_l452re/board.yml new file mode 100644 index 00000000000..9bbf9630497 --- /dev/null +++ b/boards/st/nucleo_l452re/board.yml @@ -0,0 +1,7 @@ +board: + name: nucleo_l452re + vendor: st + socs: + - name: stm32l452xx + variants: + - name: p diff --git a/boards/arm/nucleo_l452re/doc/img/nucleo_l452re_p.jpg b/boards/st/nucleo_l452re/doc/img/nucleo_l452re_p.jpg similarity index 100% rename from boards/arm/nucleo_l452re/doc/img/nucleo_l452re_p.jpg rename to boards/st/nucleo_l452re/doc/img/nucleo_l452re_p.jpg diff --git a/boards/arm/nucleo_l452re/doc/img/nucleo_l452re_p_pinout.jpg b/boards/st/nucleo_l452re/doc/img/nucleo_l452re_p_pinout.jpg similarity index 100% rename from boards/arm/nucleo_l452re/doc/img/nucleo_l452re_p_pinout.jpg rename to boards/st/nucleo_l452re/doc/img/nucleo_l452re_p_pinout.jpg diff --git a/boards/arm/nucleo_l452re/doc/img/nucleo_l452re_pinout.jpg b/boards/st/nucleo_l452re/doc/img/nucleo_l452re_pinout.jpg similarity index 100% rename from boards/arm/nucleo_l452re/doc/img/nucleo_l452re_pinout.jpg rename to boards/st/nucleo_l452re/doc/img/nucleo_l452re_pinout.jpg diff --git a/boards/st/nucleo_l452re/doc/index.rst b/boards/st/nucleo_l452re/doc/index.rst new file mode 100644 index 00000000000..57839f931c5 --- /dev/null +++ b/boards/st/nucleo_l452re/doc/index.rst @@ -0,0 +1,266 @@ +.. _nucleo_l452re_board: + +ST Nucleo L452RE +################ + +Overview +******** + +The Nucleo L452RE(-P) boards feature an ARM Cortex-M4 based STM32L452RE MCU +with a wide range of connectivity support and configurations. There are two variants: + +- ST Nucleo L452RE +- ST Nucleo L452RE-P + +Here some highlights of these boards: + +- STM32 microcontroller in LQFP64 package +- Arduino Uno V3 connectivity +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- One push-button: RESET + +.. image:: img/nucleo_l452re_p.jpg + :align: center + :alt: Nucleo L452RE-P + +The main difference between the ST Nucleo L452RE and the L452RE-P (note the missing +"-P" at the end) lays in the External Switched Mode Power Supply (SMPS) included in +the P series. + +More information about the boards can be found at the `Nucleo L452RE website`_ and +the `Nucleo L452RE-P website`_. + +Hardware +******** + +The STM32L452RE SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, + 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 2 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 12x timers: + + - 1x 16-bit advanced motor-control + - 1x 32-bit and 3x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 26 fast I/Os, most 5 V-tolerant +- Memories + + - Up to 512 KB single bank Flash, proprietary code readout protection + - 160 KB of SRAM including 32 KB with hardware parity check + - Quad SPI memory interface + +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 1x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 17x communication interfaces + - USB 2.0 full-speed crystal less solution with LPM and BCD + - 1x SAI (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 3x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x UART (LIN, IrDA, modem) + - 1x LPUART (Stop 2 wake-up) + - 3x SPIs (and 1x Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32L452RE can be found here: + +- `STM32L452RE on www.st.com`_ +- `STM32L452 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l452re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l452re/nucleo_l452re_defconfig` + +And for Nucleo L452RE-P in this defconfig file: +:zephyr_file:`boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig` + + +Connections and IOs +=================== + +Nucleo L452RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_l452re_pinout.jpg + :align: center + :alt: Nucleo L452RE Pinout + +.. image:: img/nucleo_l452re_p_pinout.jpg + :align: center + :alt: Nucleo L452RE-P Pinout + +For more details please refer to `ST Nucleo L452RE User Manual`_ or +`ST Nucleo L452RE-P User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB7 +- PWM_2_CH1 : PA0 +- SPI_NSS : PB6 +- SPI_SCK : PA5 +- SPI_MISO : PA6 +- SPI_MOSI : PA7 +- CAN_TX : PA11 +- CAN_RX : PA12 +- LD2 : PA5 + +System Clock +------------ + +Nucleo L452RE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L452RE board has 3 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l452re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L452RE board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Nucleo L452RE +---------------------------------------- + +Connect the Nucleo L452RE to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l452re + :goals: build flash + +For Nucleo L452RE-P, use this command instead: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l452re/stm32l452xx/p + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l452re + :maybe-skip-config: + :goals: debug + +.. _Nucleo L452RE website: + https://www.st.com/en/evaluation-tools/nucleo-l452re.html + +.. _Nucleo L452RE-P website: + https://www.st.com/en/evaluation-tools/nucleo-l452re-p.html + +.. _ST Nucleo L452RE User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _ST Nucleo L452RE-P User Manual: + https://www.st.com/resource/en/user_manual/dm00387966.pdf + +.. _STM32L452RE on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l452re.html + +.. _STM32L452 reference manual: + https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l452re/nucleo_l452re.dts b/boards/st/nucleo_l452re/nucleo_l452re.dts similarity index 100% rename from boards/arm/nucleo_l452re/nucleo_l452re.dts rename to boards/st/nucleo_l452re/nucleo_l452re.dts diff --git a/boards/arm/nucleo_l452re/nucleo_l452re.yaml b/boards/st/nucleo_l452re/nucleo_l452re.yaml similarity index 100% rename from boards/arm/nucleo_l452re/nucleo_l452re.yaml rename to boards/st/nucleo_l452re/nucleo_l452re.yaml diff --git a/boards/arm/nucleo_l452re/nucleo_l452re_common.dtsi b/boards/st/nucleo_l452re/nucleo_l452re_common.dtsi similarity index 100% rename from boards/arm/nucleo_l452re/nucleo_l452re_common.dtsi rename to boards/st/nucleo_l452re/nucleo_l452re_common.dtsi diff --git a/boards/arm/nucleo_l452re/nucleo_l452re_defconfig b/boards/st/nucleo_l452re/nucleo_l452re_defconfig similarity index 85% rename from boards/arm/nucleo_l452re/nucleo_l452re_defconfig rename to boards/st/nucleo_l452re/nucleo_l452re_defconfig index 14b7ffdd209..94950b2862f 100644 --- a/boards/arm/nucleo_l452re/nucleo_l452re_defconfig +++ b/boards/st/nucleo_l452re/nucleo_l452re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L452XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_l452re/nucleo_l452re_p.dts b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.dts similarity index 100% rename from boards/arm/nucleo_l452re/nucleo_l452re_p.dts rename to boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.dts diff --git a/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml new file mode 100644 index 00000000000..86e8a58034f --- /dev/null +++ b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml @@ -0,0 +1,17 @@ +identifier: nucleo_l452re/stm32l452xx/p +name: ST Nucleo L452RE-P +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 160 +flash: 512 +supported: + - nvs + - pwm + - can + - counter + - spi +vendor: st diff --git a/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig new file mode 100644 index 00000000000..94950b2862f --- /dev/null +++ b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_l452re/st_morpho_connector.dtsi b/boards/st/nucleo_l452re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l452re/st_morpho_connector.dtsi rename to boards/st/nucleo_l452re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_l452re/support/openocd.cfg b/boards/st/nucleo_l452re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l452re/support/openocd.cfg rename to boards/st/nucleo_l452re/support/openocd.cfg diff --git a/boards/st/nucleo_l476rg/Kconfig.defconfig b/boards/st/nucleo_l476rg/Kconfig.defconfig new file mode 100644 index 00000000000..276fdc47b58 --- /dev/null +++ b/boards/st/nucleo_l476rg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32L476RG Nucleo board configuration + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L476RG + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L476RG diff --git a/boards/st/nucleo_l476rg/Kconfig.nucleo_l476rg b/boards/st/nucleo_l476rg/Kconfig.nucleo_l476rg new file mode 100644 index 00000000000..dd3608327d1 --- /dev/null +++ b/boards/st/nucleo_l476rg/Kconfig.nucleo_l476rg @@ -0,0 +1,5 @@ +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L476RG + select SOC_STM32L476XX diff --git a/boards/arm/nucleo_l476rg/arduino_r3_connector.dtsi b/boards/st/nucleo_l476rg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l476rg/arduino_r3_connector.dtsi rename to boards/st/nucleo_l476rg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l476rg/board.cmake b/boards/st/nucleo_l476rg/board.cmake similarity index 100% rename from boards/arm/nucleo_l476rg/board.cmake rename to boards/st/nucleo_l476rg/board.cmake diff --git a/boards/st/nucleo_l476rg/board.yml b/boards/st/nucleo_l476rg/board.yml new file mode 100644 index 00000000000..c6b21713e34 --- /dev/null +++ b/boards/st/nucleo_l476rg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l476rg + vendor: st + socs: + - name: stm32l476xx diff --git a/boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg.jpg b/boards/st/nucleo_l476rg/doc/img/nucleo_l476rg.jpg similarity index 100% rename from boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg.jpg rename to boards/st/nucleo_l476rg/doc/img/nucleo_l476rg.jpg diff --git a/boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg_arduino.jpg b/boards/st/nucleo_l476rg/doc/img/nucleo_l476rg_arduino.jpg similarity index 100% rename from boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg_arduino.jpg rename to boards/st/nucleo_l476rg/doc/img/nucleo_l476rg_arduino.jpg diff --git a/boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg_morpho.jpg b/boards/st/nucleo_l476rg/doc/img/nucleo_l476rg_morpho.jpg similarity index 100% rename from boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg_morpho.jpg rename to boards/st/nucleo_l476rg/doc/img/nucleo_l476rg_morpho.jpg diff --git a/boards/st/nucleo_l476rg/doc/index.rst b/boards/st/nucleo_l476rg/doc/index.rst new file mode 100644 index 00000000000..a45b18b339e --- /dev/null +++ b/boards/st/nucleo_l476rg/doc/index.rst @@ -0,0 +1,243 @@ +.. _nucleo_l476rg_board: + +ST Nucleo L476RG +################ + +Overview +******** + +The Nucleo L476RG board features an ARM Cortex-M4 based STM32L476RG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L476RG board: + + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_l476rg.jpg + :align: center + :alt: Nucleo L476RG + +More information about the board can be found at the `Nucleo L476RG website`_. + +Hardware +******** + +The STM32L476RG SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- LCD 8 x 40 or 4 x 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 128 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface + +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 18x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L476RG can be found here: + +- `STM32L476RG on www.st.com`_ +- `STM32L476 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l476rg board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l476rg/nucleo_l476rg_defconfig` + + +Connections and IOs +=================== + +Nucleo L476RG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_l476rg_arduino.jpg + :align: center + :alt: Nucleo L476RG Arduino connectors +.. image:: img/nucleo_l476rg_morpho.jpg + :align: center + :alt: Nucleo L476RG Morpho connectors + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1 TX/RX : PA9/PA10 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- UART_3 TX/RX : PB10/PB11 +- I2C_1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C_3 SCL/SDA : PC0/PC1 +- SPI_1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- SPI_2 CS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- SPI_3 CS/SCK/MISO/MOSI : PA15/PC10/PC11/PC12 +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD2 : PA5 + +System Clock +------------ + +Nucleo L476RG System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L476RG board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l476rg`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L476RG board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Nucleo L476RG +---------------------------------------- + +Connect the Nucleo L476RG to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l476rg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l476rg + :maybe-skip-config: + :goals: debug + +.. _Nucleo L476RG website: + https://www.st.com/en/evaluation-tools/nucleo-l476rg.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32L476RG on www.st.com: + https://www.st.com/en/microcontrollers/stm32l476rg.html + +.. _STM32L476 reference manual: + https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/nucleo_l476rg/nucleo_l476rg.dts b/boards/st/nucleo_l476rg/nucleo_l476rg.dts similarity index 100% rename from boards/arm/nucleo_l476rg/nucleo_l476rg.dts rename to boards/st/nucleo_l476rg/nucleo_l476rg.dts diff --git a/boards/arm/nucleo_l476rg/nucleo_l476rg.yaml b/boards/st/nucleo_l476rg/nucleo_l476rg.yaml similarity index 100% rename from boards/arm/nucleo_l476rg/nucleo_l476rg.yaml rename to boards/st/nucleo_l476rg/nucleo_l476rg.yaml diff --git a/boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig b/boards/st/nucleo_l476rg/nucleo_l476rg_defconfig similarity index 85% rename from boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig rename to boards/st/nucleo_l476rg/nucleo_l476rg_defconfig index 0ba22d7b6c4..76e7e50d1fa 100644 --- a/boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig +++ b/boards/st/nucleo_l476rg/nucleo_l476rg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L476XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_l476rg/st_morpho_connector.dtsi b/boards/st/nucleo_l476rg/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l476rg/st_morpho_connector.dtsi rename to boards/st/nucleo_l476rg/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_l496zg/support/openocd.cfg b/boards/st/nucleo_l476rg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l496zg/support/openocd.cfg rename to boards/st/nucleo_l476rg/support/openocd.cfg diff --git a/boards/st/nucleo_l496zg/Kconfig.defconfig b/boards/st/nucleo_l496zg/Kconfig.defconfig new file mode 100644 index 00000000000..f15b6d411ec --- /dev/null +++ b/boards/st/nucleo_l496zg/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32L496ZG Nucleo board configuration + +# Copyright (c) 2018 Centaur Analytics, Inc +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L496ZG + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L496ZG diff --git a/boards/st/nucleo_l496zg/Kconfig.nucleo_l496zg b/boards/st/nucleo_l496zg/Kconfig.nucleo_l496zg new file mode 100644 index 00000000000..79dc7f4b042 --- /dev/null +++ b/boards/st/nucleo_l496zg/Kconfig.nucleo_l496zg @@ -0,0 +1,5 @@ +# Copyright (c) 2018-2019 Centaur Analytics, Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L496ZG + select SOC_STM32L496XX diff --git a/boards/arm/nucleo_l496zg/arduino_r3_connector.dtsi b/boards/st/nucleo_l496zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l496zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_l496zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l496zg/board.cmake b/boards/st/nucleo_l496zg/board.cmake similarity index 100% rename from boards/arm/nucleo_l496zg/board.cmake rename to boards/st/nucleo_l496zg/board.cmake diff --git a/boards/st/nucleo_l496zg/board.yml b/boards/st/nucleo_l496zg/board.yml new file mode 100644 index 00000000000..3d1c909cffc --- /dev/null +++ b/boards/st/nucleo_l496zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l496zg + vendor: st + socs: + - name: stm32l496xx diff --git a/boards/arm/nucleo_l496zg/doc/img/nucleo_l496zg.jpg b/boards/st/nucleo_l496zg/doc/img/nucleo_l496zg.jpg similarity index 100% rename from boards/arm/nucleo_l496zg/doc/img/nucleo_l496zg.jpg rename to boards/st/nucleo_l496zg/doc/img/nucleo_l496zg.jpg diff --git a/boards/st/nucleo_l496zg/doc/index.rst b/boards/st/nucleo_l496zg/doc/index.rst new file mode 100644 index 00000000000..da208a4c8d9 --- /dev/null +++ b/boards/st/nucleo_l496zg/doc/index.rst @@ -0,0 +1,244 @@ +.. _nucleo_l496zg_board: + +ST Nucleo L496ZG +################ + +Overview +******** + +The Nucleo L496ZG board features an ARM Cortex-M4 based STM32L496ZG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L476ZG board: + + +- STM32 microcontroller in QFP144 package +- USB OTG FS with Micro-AB connector +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- 8 LEDs: user LEDs (LD1, LD2, LD3), communication LED (LD4), USB + power fault(LD5), power LED (LD6), USB FS OTG (LD7, LD8) +- 2 push buttons: USER and RESET + +.. image:: img/nucleo_l496zg.jpg + :align: center + :alt: Nucleo L496ZG + +More information about the board can be found at the `Nucleo L496ZG website`_. + +Hardware +******** + +The STM32L496ZG SoC provides the following hardware capabilities: + +- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- LCD 8 x 40 or 4 x 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 320 KB of SRAM including 64 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface + +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 20x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 5x U(S)ARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART + - 3x SPIs (4x SPIs with the Quad SPI) + - 2x CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L496ZG can be found here: + +- `STM32L496ZG on www.st.com`_ +- `STM32L496 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l496zg board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | System Window Watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l496zg/nucleo_l496zg_defconfig` + + +Connections and IOs +=================== + +Nucleo L496ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PD5/PD6 +- UART_3 TX/RX : PD8/PD9 +- LPUART_1 TX/RX : PG7/PG8 +- PWM_1_CH1: PE9 +- PWM_1_CH2: PE11 +- PWM_1_CH3: PE13 +- PWM_2_CH1: PA0 +- I2C_1_SCL: PB8 +- I2C_1_SDA: PB7 +- SPI_1_NSS: PD14 +- SPI_1_SCK: PA5 +- SPI_1_MISO: PA6 +- SPI_1_MOSI: PA7 +- USER_PB : PC13 +- LD1 : PC7 +- LD2 : PB7 +- LD3 : PB14 + +System Clock +------------ + +Nucleo L496ZG System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L496ZG board has 5 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l496zg`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L496ZG board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.5. + +Flashing an application to Nucleo L496ZG +---------------------------------------- + +Connect the Nucleo L496ZG to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyUSB0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l496zg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l496zg + :maybe-skip-config: + :goals: debug + +.. _Nucleo L496ZG website: + https://www.st.com/en/evaluation-tools/nucleo-l496zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00368330.pdf + +.. _STM32L496ZG on www.st.com: + https://www.st.com/en/microcontrollers/stm32l496zg.html + +.. _STM32L496 reference manual: + https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/nucleo_l496zg/nucleo_l496zg.dts b/boards/st/nucleo_l496zg/nucleo_l496zg.dts similarity index 100% rename from boards/arm/nucleo_l496zg/nucleo_l496zg.dts rename to boards/st/nucleo_l496zg/nucleo_l496zg.dts diff --git a/boards/arm/nucleo_l496zg/nucleo_l496zg.yaml b/boards/st/nucleo_l496zg/nucleo_l496zg.yaml similarity index 100% rename from boards/arm/nucleo_l496zg/nucleo_l496zg.yaml rename to boards/st/nucleo_l496zg/nucleo_l496zg.yaml diff --git a/boards/arm/nucleo_l496zg/nucleo_l496zg_defconfig b/boards/st/nucleo_l496zg/nucleo_l496zg_defconfig similarity index 85% rename from boards/arm/nucleo_l496zg/nucleo_l496zg_defconfig rename to boards/st/nucleo_l496zg/nucleo_l496zg_defconfig index e195230eb20..5ef11a3cb3f 100644 --- a/boards/arm/nucleo_l496zg/nucleo_l496zg_defconfig +++ b/boards/st/nucleo_l496zg/nucleo_l496zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L496XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_l4a6zg/support/openocd.cfg b/boards/st/nucleo_l496zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l4a6zg/support/openocd.cfg rename to boards/st/nucleo_l496zg/support/openocd.cfg diff --git a/boards/st/nucleo_l4a6zg/Kconfig.defconfig b/boards/st/nucleo_l4a6zg/Kconfig.defconfig new file mode 100644 index 00000000000..a7e0339c369 --- /dev/null +++ b/boards/st/nucleo_l4a6zg/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32L4A6ZG Nucleo board configuration + +# Copyright (c) 2022 Tomislav Milkovic +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L4A6ZG + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L4A6ZG diff --git a/boards/st/nucleo_l4a6zg/Kconfig.nucleo_l4a6zg b/boards/st/nucleo_l4a6zg/Kconfig.nucleo_l4a6zg new file mode 100644 index 00000000000..fb33c9a9a23 --- /dev/null +++ b/boards/st/nucleo_l4a6zg/Kconfig.nucleo_l4a6zg @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Tomislav Milkovic +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L4A6ZG + select SOC_STM32L4A6XX diff --git a/boards/arm/nucleo_l4a6zg/arduino_r3_connector.dtsi b/boards/st/nucleo_l4a6zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l4a6zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_l4a6zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l4a6zg/board.cmake b/boards/st/nucleo_l4a6zg/board.cmake similarity index 100% rename from boards/arm/nucleo_l4a6zg/board.cmake rename to boards/st/nucleo_l4a6zg/board.cmake diff --git a/boards/st/nucleo_l4a6zg/board.yml b/boards/st/nucleo_l4a6zg/board.yml new file mode 100644 index 00000000000..6e935c5d082 --- /dev/null +++ b/boards/st/nucleo_l4a6zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l4a6zg + vendor: st + socs: + - name: stm32l4a6xx diff --git a/boards/st/nucleo_l4a6zg/doc/index.rst b/boards/st/nucleo_l4a6zg/doc/index.rst new file mode 100644 index 00000000000..30cac697dde --- /dev/null +++ b/boards/st/nucleo_l4a6zg/doc/index.rst @@ -0,0 +1,243 @@ +.. _nucleo_l4a6zg_board: + +ST Nucleo L4A6ZG +################ + +Overview +******** + +The Nucleo L4A6ZG board features an ARM Cortex-M4 based STM32L4A6ZG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L4A6ZG board: + + +- STM32 microcontroller in QFP144 package +- USB OTG FS with Micro-AB connector +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- 8 LEDs: user LEDs (LD1, LD2, LD3), communication LED (LD4), USB + power fault(LD5), power LED (LD6), USB FS OTG (LD7, LD8) +- 2 push buttons: USER and RESET + +.. image:: ../../nucleo_l496zg/doc/img/nucleo_l496zg.jpg + :align: center + :alt: Nucleo L4A6ZG + +More information about the board can be found at the `Nucleo L4A6ZG website`_. + +Hardware +******** + +The STM32L4A6ZG SoC provides the following hardware capabilities: + +- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- LCD 8 x 40 or 4 x 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 320 KB of SRAM including 64 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface + +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 20x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 5x U(S)ARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART + - 3x SPIs (4x SPIs with the Quad SPI) + - 2x CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- AES and HASH hardware accelerators +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L4A6ZG can be found here: + +- `STM32L4A6ZG on www.st.com`_ +- `STM32L4A6 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l4a6zg board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | System Window Watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig` + + +Connections and IOs +=================== + +Nucleo L4A6ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- LPUART_1 TX/RX : PG7/PG8 (ST-Link Virtual COM Port) +- UART_3 TX/RX : PD8/PD9 (Arduino Serial) +- I2C_1 SCL/SDA : PB8/PB7 (Arduino I2C) +- SPI_1 SCK/MISO/MOSI/NSS : PA5/PA6/PA7/PD14 (Arduino SPI) +- USER_PB : PC13 +- PWM_15_CH1 : PB14 (Red LED) +- LD1 : PC7 (Green LED) +- LD2 : PB7 (Blue LED) +- LD3 : PB14 (Red LED) + +System Clock +------------ + +Nucleo L4A6ZG system clock could be driven by internal or external oscillator, +as well as main PLL clock. By default, system clock is driven by PLL at 80MHz, which is +driven by 16MHz high speed internal oscillator (HSI). High speed external oscillator +(HSE) is not soldered on the board, so it cannot be used to drive the PLL. + +Serial Port +----------- + +Nucleo L4A6ZG board has 5 UARTs. The Zephyr console output is assigned to LPUART1, +which is connected to the onboard ST-LINK/V2-1. Virtual COM port interface. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l4a6zg`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L4A6ZG board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the OpenOCD version +included in the Zephyr SDK since v0.9.5. + +Flashing an application to Nucleo L4A6ZG +---------------------------------------- + +Connect the Nucleo L4A6ZG to your host computer using the ST-LINK USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyUSB0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l4a6zg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! nucleo_l4a6zg + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l4a6zg + :maybe-skip-config: + :goals: debug + +.. _Nucleo L4A6ZG website: + https://www.st.com/en/evaluation-tools/nucleo-l4a6zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00368330.pdf + +.. _STM32L4A6ZG on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l4a6zg.html + +.. _STM32L4A6 reference manual: + https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/nucleo_l4a6zg/nucleo_l4a6zg.dts b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.dts similarity index 100% rename from boards/arm/nucleo_l4a6zg/nucleo_l4a6zg.dts rename to boards/st/nucleo_l4a6zg/nucleo_l4a6zg.dts diff --git a/boards/arm/nucleo_l4a6zg/nucleo_l4a6zg.yaml b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.yaml similarity index 100% rename from boards/arm/nucleo_l4a6zg/nucleo_l4a6zg.yaml rename to boards/st/nucleo_l4a6zg/nucleo_l4a6zg.yaml diff --git a/boards/arm/nucleo_l4a6zg/nucleo_l4a6zg_defconfig b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig similarity index 85% rename from boards/arm/nucleo_l4a6zg/nucleo_l4a6zg_defconfig rename to boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig index a2e8b6eb212..5ef11a3cb3f 100644 --- a/boards/arm/nucleo_l4a6zg/nucleo_l4a6zg_defconfig +++ b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4A6XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_l4r5zi/support/openocd.cfg b/boards/st/nucleo_l4a6zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l4r5zi/support/openocd.cfg rename to boards/st/nucleo_l4a6zg/support/openocd.cfg diff --git a/boards/st/nucleo_l4r5zi/Kconfig.defconfig b/boards/st/nucleo_l4r5zi/Kconfig.defconfig new file mode 100644 index 00000000000..31b375e87d2 --- /dev/null +++ b/boards/st/nucleo_l4r5zi/Kconfig.defconfig @@ -0,0 +1,22 @@ +# STM32L4R5ZI Nucleo board configuration + +# Copyright (c) 2018 Pushpal Sidhu +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L4R5ZI + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +if NETWORKING + +config USB_DEVICE_STACK + default y + +config USB_DEVICE_NETWORK_EEM + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_L4R5ZI diff --git a/boards/st/nucleo_l4r5zi/Kconfig.nucleo_l4r5zi b/boards/st/nucleo_l4r5zi/Kconfig.nucleo_l4r5zi new file mode 100644 index 00000000000..06fe55dc6b5 --- /dev/null +++ b/boards/st/nucleo_l4r5zi/Kconfig.nucleo_l4r5zi @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Pushpal Sidhu +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L4R5ZI + select SOC_STM32L4R5XX diff --git a/boards/arm/nucleo_l4r5zi/arduino_r3_connector.dtsi b/boards/st/nucleo_l4r5zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l4r5zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_l4r5zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l4r5zi/board.cmake b/boards/st/nucleo_l4r5zi/board.cmake similarity index 100% rename from boards/arm/nucleo_l4r5zi/board.cmake rename to boards/st/nucleo_l4r5zi/board.cmake diff --git a/boards/st/nucleo_l4r5zi/board.yml b/boards/st/nucleo_l4r5zi/board.yml new file mode 100644 index 00000000000..46ead4d8831 --- /dev/null +++ b/boards/st/nucleo_l4r5zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l4r5zi + vendor: st + socs: + - name: stm32l4r5xx diff --git a/boards/arm/nucleo_l4r5zi/doc/img/nucleo144_layout.jpg b/boards/st/nucleo_l4r5zi/doc/img/nucleo144_layout.jpg similarity index 100% rename from boards/arm/nucleo_l4r5zi/doc/img/nucleo144_layout.jpg rename to boards/st/nucleo_l4r5zi/doc/img/nucleo144_layout.jpg diff --git a/boards/arm/nucleo_l4r5zi/doc/img/nucleo_l4r5zi.jpg b/boards/st/nucleo_l4r5zi/doc/img/nucleo_l4r5zi.jpg similarity index 100% rename from boards/arm/nucleo_l4r5zi/doc/img/nucleo_l4r5zi.jpg rename to boards/st/nucleo_l4r5zi/doc/img/nucleo_l4r5zi.jpg diff --git a/boards/st/nucleo_l4r5zi/doc/index.rst b/boards/st/nucleo_l4r5zi/doc/index.rst new file mode 100644 index 00000000000..f449c985a83 --- /dev/null +++ b/boards/st/nucleo_l4r5zi/doc/index.rst @@ -0,0 +1,275 @@ +.. _nucleo_l4r5zi_board: + +ST Nucleo L4R5ZI +################ + +Overview +******** + +The Nucleo L4R5ZI board features an ARM Cortex-M4 based STM32L4R5ZI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L4R5ZI board: + + +- STM32 microcontroller in LQFP144 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three User LEDs: LD1 (Green), LD2 (Blue), LD3 (Red) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_l4r5zi.jpg + :align: center + :alt: Nucleo L4R5ZI + +More information about the board can be found at the `Nucleo L4R5ZI website`_. + +Hardware +******** + +The STM32L4R5ZI SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode + and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive + real-time accelerator (ART Accelerator) allowing 0-wait-state + execution from Flash memory, frequency up to 120 MHz, MPU, 150 + DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - Internal 48 MHz with clock recovery + - 3 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and + rotary touch sensors +- Advanced graphics features + + - Chrom-ART Accelerator™ (DMA2D) for enhanced graphic content creation + - Chrom-GRC™ (GFXMMU) allowing up to 20% of graphic resources optimization + - MIPI® DSI Host controller with two DSI lanes running at up to 500 + Mbits/s each + - LCD-TFT controller + +- 16x timers + + - 2 x 16-bit advanced motor-control + - 2 x 32-bit and 5 x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with + independent supply down to 1.08 V +- Memories + + - 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection + - 640 Kbytes of SRAM including 64 Kbytes with hardware parity check + - External memory interface for static memories supporting SRAM, + PSRAM, NOR, NAND and FRAM memories + - 2 x OctoSPI memory interface + +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + + - 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 μA/Msps + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 20x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (5x SPIs with the dual OctoSPI) + - CAN (2.0B Active) and SDMMC + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- 8- to 14-bit camera interface up to 32 MHz (black and white) or 10 MHz (color) +- Development support: serial wire debug (SWD), JTAG, Embedded Trace + Macrocell (ETM) + +More information about STM32L4R5ZI can be found here: + +- `STM32L4R5ZI on www.st.com`_ +- `STM32L4R5 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l4r5zi board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig` + + +Connections and IOs +=================== + +Nucleo L4R5ZI Board has 8 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo144_layout.jpg + :align: center + :alt: Nucleo L4R5ZI Arduino connectors + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- UART_3_TX : PB10 +- UART_3_RX : PB11 +- I2C_1_SCL : PB6 +- I2C_1_SDA : PB7 +- SPI_1_NSS : PD14 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- SPI_2_NSS : PB12 +- SPI_2_SCK : PB13 +- SPI_2_MISO : PB14 +- SPI_2_MOSI : PB15 +- SPI_3_NSS : PB12 +- SPI_3_SCK : PC10 +- SPI_3_MISO : PC11 +- SPI_3_MOSI : PC12 +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD1 : PC7 +- LD2 : PB7 +- LD3 : PB14 +- USB DM : PA11 +- USB DP : PA12 +- ADC1 : PC0 + +System Clock +------------ + +Nucleo L4R5ZI System Clock could be driven by internal or external +oscillator, as well as main PLL clock. By default, the System clock is +driven by the PLL clock at 80MHz, driven by a 16MHz high speed +internal oscillator. The clock can be boosted to 120MHz if boost mode +is selected. + +Serial Port +----------- + +Nucleo L4R5ZI board has 5 U(S)ARTs. The Zephyr console output is +assigned to UART2. Default settings are 115200 8N1. + +Network interface +----------------- + +Ethernet over USB is configured as the default network interface (EEM) + +Programming and Debugging +************************* + +The NUCLEO-L4R5ZI board includes a ST-LINK/V2 embedded debug tool interface. + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its installation is required to be able to flash the board. + +Alternatively, openocd (provided in Zephyr SDK) or JLink can also be used to +flash the board using the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + +Connect the Nucleo L4R5ZI to your host computer using the USB port. +Then build and flash an application. + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l4r5zi + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +.. _Nucleo L4R5ZI website: + https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00368330.pdf + +.. _STM32L4R5ZI on www.st.com: + https://www.st.com/en/microcontrollers/stm32l4r5zi.html + +.. _STM32L4R5 reference manual: + https://www.st.com/resource/en/reference_manual/DM00310109.pdf + +.. _STM32 ST-LINK utility: + https://www.st.com/content/st_com/en/products/development-tools/software-development-tools/stm32-software-development-tools/stm32-programmers/stsw-link004.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.dts b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.dts similarity index 100% rename from boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.dts rename to boards/st/nucleo_l4r5zi/nucleo_l4r5zi.dts diff --git a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.yaml b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml similarity index 100% rename from boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.yaml rename to boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml diff --git a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig similarity index 85% rename from boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig rename to boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig index 0efb42f55a9..4ba8077edd6 100644 --- a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig +++ b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4R5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/sensortile_box/support/openocd.cfg b/boards/st/nucleo_l4r5zi/support/openocd.cfg similarity index 100% rename from boards/arm/sensortile_box/support/openocd.cfg rename to boards/st/nucleo_l4r5zi/support/openocd.cfg diff --git a/boards/arm/nucleo_l552ze_q/CMakeLists.txt b/boards/st/nucleo_l552ze_q/CMakeLists.txt similarity index 100% rename from boards/arm/nucleo_l552ze_q/CMakeLists.txt rename to boards/st/nucleo_l552ze_q/CMakeLists.txt diff --git a/boards/st/nucleo_l552ze_q/Kconfig.nucleo_l552ze_q b/boards/st/nucleo_l552ze_q/Kconfig.nucleo_l552ze_q new file mode 100644 index 00000000000..22104ed027d --- /dev/null +++ b/boards/st/nucleo_l552ze_q/Kconfig.nucleo_l552ze_q @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L552ZE_Q + select SOC_STM32L552XX diff --git a/boards/arm/nucleo_l552ze_q/arduino_r3_connector.dtsi b/boards/st/nucleo_l552ze_q/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l552ze_q/arduino_r3_connector.dtsi rename to boards/st/nucleo_l552ze_q/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l552ze_q/board.cmake b/boards/st/nucleo_l552ze_q/board.cmake similarity index 100% rename from boards/arm/nucleo_l552ze_q/board.cmake rename to boards/st/nucleo_l552ze_q/board.cmake diff --git a/boards/st/nucleo_l552ze_q/board.yml b/boards/st/nucleo_l552ze_q/board.yml new file mode 100644 index 00000000000..713b695aeba --- /dev/null +++ b/boards/st/nucleo_l552ze_q/board.yml @@ -0,0 +1,7 @@ +board: + name: nucleo_l552ze_q + vendor: st + socs: + - name: stm32l552xx + variants: + - name: ns diff --git a/boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q.jpg b/boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q.jpg similarity index 100% rename from boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q.jpg rename to boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q.jpg diff --git a/boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_left_2020_2_11.jpg b/boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_left_2020_2_11.jpg similarity index 100% rename from boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_left_2020_2_11.jpg rename to boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_left_2020_2_11.jpg diff --git a/boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_right_2020_2_11.jpg b/boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_right_2020_2_11.jpg similarity index 100% rename from boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_right_2020_2_11.jpg rename to boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_right_2020_2_11.jpg diff --git a/boards/arm/nucleo_l552ze_q/doc/nucleol552ze_q.rst b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst similarity index 91% rename from boards/arm/nucleo_l552ze_q/doc/nucleol552ze_q.rst rename to boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst index 65a2df527a9..d4b8f599673 100644 --- a/boards/arm/nucleo_l552ze_q/doc/nucleol552ze_q.rst +++ b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst @@ -168,17 +168,17 @@ The default configuration can be found in the defconfig and dts files: - Common: - - :zephyr_file:`boards/arm/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi` + - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi` - Secure target: - - :zephyr_file:`boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_defconfig` - - :zephyr_file:`boards/arm/nucleo_l552ze_q/nucleo_l552ze_q.dts` + - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig` + - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q.dts` - Non-Secure target: - - :zephyr_file:`boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns_defconfig` - - :zephyr_file:`boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.dts` + - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig` + - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.dts` Zephyr board options ==================== @@ -188,20 +188,20 @@ for building for both Secure and Non-Secure firmware. The BOARD options are summarized below: -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| nucleo_l552ze_q | For building Secure (or Secure-only) firmware | -+----------------------+-----------------------------------------------+ -| nucleo_l552ze_q_ns | For building Non-Secure firmware | -+----------------------+-----------------------------------------------+ ++--------------------------------+-------------------------------------------+ +| BOARD | Description | ++================================+===========================================+ +| nucleo_l552ze_q | For building Trust Zone Disabled firmware | ++--------------------------------+-------------------------------------------+ +| nucleo_l552ze_q/stm32l552xx/ns | For building Non-Secure firmware | ++--------------------------------+-------------------------------------------+ Here are the instructions to build Zephyr with a non-secure configuration, using `tfm_ipc_` sample: .. code-block:: bash - $ west build -b nucleo_l552ze_q_ns samples/tfm_integration/tfm_ipc/ + $ west build -b nucleo_l552ze_q/stm32l552xx/ns samples/tfm_integration/tfm_ipc/ Once done, before flashing, you need to first run a generated script that will set platform option bytes config and erase platform (among others, @@ -332,11 +332,11 @@ Building a secure/non-secure with Arm |reg| TrustZone |reg| The TF-M integration sample :ref:`tfm_ipc` can be run on a ST Nucleo L552ZE Q. In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image -can be generated using ``nucleo_l552ze_q_ns`` as build target. +can be generated using ``nucleo_l552ze_q/stm32l552xx/ns`` as build target. .. code-block:: bash - $ west build -b nucleo_l552ze_q_ns path/to/source/directory + $ west build -b nucleo_l552ze_q/stm32l552xx/ns path/to/source/directory Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script is run automatically in a post-build step to make some required flash layout changes. diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi similarity index 100% rename from boards/arm/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi rename to boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q.dts b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q.dts similarity index 100% rename from boards/arm/nucleo_l552ze_q/nucleo_l552ze_q.dts rename to boards/st/nucleo_l552ze_q/nucleo_l552ze_q.dts diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q.yaml b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q.yaml similarity index 100% rename from boards/arm/nucleo_l552ze_q/nucleo_l552ze_q.yaml rename to boards/st/nucleo_l552ze_q/nucleo_l552ze_q.yaml diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_defconfig b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig similarity index 85% rename from boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_defconfig rename to boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig index aa132c44b32..08e07645470 100644 --- a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_defconfig +++ b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L5X=y -CONFIG_SOC_STM32L552XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.dts b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.dts similarity index 100% rename from boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.dts rename to boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.dts diff --git a/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.yaml b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.yaml new file mode 100644 index 00000000000..186f873ff83 --- /dev/null +++ b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.yaml @@ -0,0 +1,13 @@ +identifier: nucleo_l552ze_q/stm32l552xx/ns +name: ST Nucleo L552ZE Q non secure +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - dac +ram: 192 +flash: 328 +vendor: st diff --git a/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig new file mode 100644 index 00000000000..540ddddfc4e --- /dev/null +++ b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable clock +CONFIG_CLOCK_CONTROL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_l552ze_q/support/openocd.cfg b/boards/st/nucleo_l552ze_q/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l552ze_q/support/openocd.cfg rename to boards/st/nucleo_l552ze_q/support/openocd.cfg diff --git a/boards/arm/nucleo_u575zi_q/CMakeLists.txt b/boards/st/nucleo_u575zi_q/CMakeLists.txt similarity index 100% rename from boards/arm/nucleo_u575zi_q/CMakeLists.txt rename to boards/st/nucleo_u575zi_q/CMakeLists.txt diff --git a/boards/st/nucleo_u575zi_q/Kconfig.nucleo_u575zi_q b/boards/st/nucleo_u575zi_q/Kconfig.nucleo_u575zi_q new file mode 100644 index 00000000000..0093ddbe95d --- /dev/null +++ b/boards/st/nucleo_u575zi_q/Kconfig.nucleo_u575zi_q @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_U575ZI_Q + select SOC_STM32U575XX diff --git a/boards/arm/nucleo_u575zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_u575zi_q/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_u575zi_q/arduino_r3_connector.dtsi rename to boards/st/nucleo_u575zi_q/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_u575zi_q/board.cmake b/boards/st/nucleo_u575zi_q/board.cmake similarity index 100% rename from boards/arm/nucleo_u575zi_q/board.cmake rename to boards/st/nucleo_u575zi_q/board.cmake diff --git a/boards/st/nucleo_u575zi_q/board.yml b/boards/st/nucleo_u575zi_q/board.yml new file mode 100644 index 00000000000..ced9ac720b3 --- /dev/null +++ b/boards/st/nucleo_u575zi_q/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_u575zi_q + vendor: st + socs: + - name: stm32u575xx diff --git a/boards/st/nucleo_u575zi_q/doc/index.rst b/boards/st/nucleo_u575zi_q/doc/index.rst new file mode 100644 index 00000000000..9a7222cb18a --- /dev/null +++ b/boards/st/nucleo_u575zi_q/doc/index.rst @@ -0,0 +1,343 @@ +.. _nucleo_u575zi_q_board: + +ST Nucleo U575ZI Q +################## + +Overview +******** + +The Nucleo U575ZI Q board, featuring an ARM Cortex-M33 based STM32U575ZI MCU, +provides an affordable and flexible way for users to try out new concepts and +build prototypes by choosing from the various combinations of performance and +power consumption features. Here are some highlights of the Nucleo U575ZI Q +board: + + +- STM32U575ZI microcontroller in LQFP144 package +- Internal SMPS to generate V core logic supply +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V3E debugger/programmer +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - ST-Link V3E + +- Three users LEDs +- Two push-buttons: USER and RESET +- USB Type-C |trade| Sink device FS + +Hardware +******** + +The STM32U575xx devices are an ultra-low-power microcontrollers family (STM32U5 +Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. +They operate at a frequency of up to 160 MHz. + +- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1.5 DMPIS/MHz (Drystone 2.1) + - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) + +- Security + + - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals + - Flexible life cycle scheme with RDP (readout protection) and password protected debug + - Root of trust thanks to unique boot entry and secure hide protection area (HDP) + - Secure Firmware Installation thanks to embedded Root Secure Services + - Secure Firmware Update support with TF-M + - HASH hardware accelerator + - Active tampers + - True Random Number Generator NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte One-Time Programmable for user data + +- Clock management: + + - 4 to 50 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + - Internal 48 MHz with clock recovery + +- Power management + + - Embedded regulator (LDO) + - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling + +- RTC with HW calendar and calibration +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- Up to 17 timers and 2 watchdogs + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5 x 16-bit general purpose + - 4x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- ART accelerator + + - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and + external memories: up to 160 MHz, MPU, 240 DMIPS and DSP + - 4-Kbyte data cache for external memories + +- Memories + + - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles + - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON + - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories + - 2 Octo-SPI memory interfaces + +- Rich analog peripherals (independent supply) + + - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling + - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode + - 2 12-bit DAC, low-power sample and hold + - 2 operational amplifiers with built-in PGA + - 2 ultra-low-power comparators + +- Up to 22 communication interfaces + + - USB Type-C / USB power delivery controller + - USB OTG 2.0 full-speed controller + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) + - 1x FDCAN + - 2x SDMMC interface + - 16- and 4-channel DMA controllers, functional in Stop mode + - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with + sound-activity detection + +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| +- True Random Number Generator (RNG) + +- Graphic features + + - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation + - 1 digital camera interface + +- Mathematical co-processor + + - CORDIC for trigonometric functions acceleration + - FMAC (filter mathematical accelerator) + +More information about STM32U575ZI can be found here: + +- `STM32U575ZI on www.st.com`_ +- `STM32U575 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_u575zi_q board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CAN/CANFD | on-chip | canbus | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| BKP SRAM | on-chip | Backup SRAM | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig` + + +Connections and IOs +=================== + +Nucleo U575ZI Q Board has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + + +- CAN/CANFD_TX: PD1 +- CAN/CANFD_RX: PD0 +- DAC1_OUT1 : PA4 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB9 +- I2C_2_SCL : PF1 +- I2C_2_SDA : PF0 +- LD1 : PC7 +- LD2 : PB7 +- LD3 : PG2 +- LPUART_1_TX : PG7 +- LPUART_1_RX : PG8 +- SPI_1_NSS : PA4 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- USER_PB : PC13 + +System Clock +------------ + +Nucleo U575ZI Q System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +160MHz, driven by 4MHz medium speed internal oscillator. + +Serial Port +----------- + +Nucleo U575ZI Q board has 6 U(S)ARTs. The Zephyr console output is assigned to +USART1. Default settings are 115200 8N1. + + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB50`` jumper on the back side of the board. + + +Programming and Debugging +************************* + +Nucleo U575ZI-Q board includes an ST-LINK/V3 embedded debug tool interface. +This probe allows to flash the board using various tools. + +Flashing +======== + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board. + +Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be +used to flash and debug the board if west is told to use it as runner, +which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``. + +For pyocd additional target information needs to be installed. +This can be done by executing the following commands. + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32u5 + + +Flashing an application to Nucleo U575ZI Q +------------------------------------------ + +Connect the Nucleo U575ZI Q to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_u575zi_q + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +Default flasher for this board is openocd. It could be used in the usual way. +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_u575zi_q + :goals: debug + +Building a secure/non-secure with Arm |reg| TrustZone |reg| +=========================================================== + +The TF-M applications can be run on this board, thanks to its Arm |reg| TrustZone |reg| +support. +In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image +can be generated using ``nucleo_u575zi_q_ns`` as build target. + +.. code-block:: bash + + $ west build -b nucleo_u575zi_q_ns path/to/source/directory + +Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script +is run automatically in a post-build step to make some required flash layout changes. + +Once the build is completed, run the following script to initialize the option bytes. + +.. code-block:: bash + + $ build/tfm/regression.sh + +Finally, to flash the board, run: + +.. code-block:: bash + + $ west flash + +Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts +(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` +(which is used for initialization) is available in the PATH. + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00615305.pdf + +.. _STM32U575ZI on www.st.com: + https://www.st.com/en/microcontrollers/stm32u575zi.html + +.. _STM32U575 reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STMicroelectronics customized version of OpenOCD: + https://github.com/STMicroelectronics/OpenOCD diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi similarity index 100% rename from boards/arm/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi rename to boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.dts b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts similarity index 100% rename from boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.dts rename to boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.yaml b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.yaml similarity index 100% rename from boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.yaml rename to boards/st/nucleo_u575zi_q/nucleo_u575zi_q.yaml diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig similarity index 85% rename from boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig rename to boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig index 23eebae7ef0..08e07645470 100644 --- a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig +++ b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U575XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_u575zi_q/support/openocd.cfg b/boards/st/nucleo_u575zi_q/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_u575zi_q/support/openocd.cfg rename to boards/st/nucleo_u575zi_q/support/openocd.cfg diff --git a/boards/arm/nucleo_u5a5zj_q/CMakeLists.txt b/boards/st/nucleo_u5a5zj_q/CMakeLists.txt similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/CMakeLists.txt rename to boards/st/nucleo_u5a5zj_q/CMakeLists.txt diff --git a/boards/st/nucleo_u5a5zj_q/Kconfig.nucleo_u5a5zj_q b/boards/st/nucleo_u5a5zj_q/Kconfig.nucleo_u5a5zj_q new file mode 100644 index 00000000000..58256af223f --- /dev/null +++ b/boards/st/nucleo_u5a5zj_q/Kconfig.nucleo_u5a5zj_q @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_U5A5ZJ_Q + select SOC_STM32U5A5XX diff --git a/boards/arm/nucleo_u5a5zj_q/arduino_r3_connector.dtsi b/boards/st/nucleo_u5a5zj_q/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/arduino_r3_connector.dtsi rename to boards/st/nucleo_u5a5zj_q/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_u5a5zj_q/board.cmake b/boards/st/nucleo_u5a5zj_q/board.cmake similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/board.cmake rename to boards/st/nucleo_u5a5zj_q/board.cmake diff --git a/boards/st/nucleo_u5a5zj_q/board.yml b/boards/st/nucleo_u5a5zj_q/board.yml new file mode 100644 index 00000000000..9e594c30fb1 --- /dev/null +++ b/boards/st/nucleo_u5a5zj_q/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_u5a5zj_q + vendor: st + socs: + - name: stm32u5a5xx diff --git a/boards/st/nucleo_u5a5zj_q/doc/index.rst b/boards/st/nucleo_u5a5zj_q/doc/index.rst new file mode 100644 index 00000000000..9b76919db33 --- /dev/null +++ b/boards/st/nucleo_u5a5zj_q/doc/index.rst @@ -0,0 +1,377 @@ +.. _nucleo_u5a5zj_q_board: + +ST Nucleo U5A5ZJ Q +################## + +Overview +******** + +The Nucleo U5A5ZJ Q board, featuring an ARM Cortex-M33 based STM32U5A5ZJ MCU, +provides an affordable and flexible way for users to try out new concepts and +build prototypes by choosing from the various combinations of performance and +power consumption features. Here are some highlights of the Nucleo U5A5ZJ Q +board: + + +- STM32U5A5ZJ microcontroller in LQFP144 package +- Internal SMPS to generate V core logic supply +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V3E debugger/programmer +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - ST-Link V3E + +- Three users LEDs +- Two push-buttons: USER and RESET +- USB Type-C ™ Sink device FS + +Hardware +******** + +The STM32U5A5xx devices are an ultra-low-power microcontrollers family (STM32U5 +Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. +They operate at a frequency of up to 160 MHz. + +- Includes ST state-of-the-art patented technology +- Ultra-low-power with FlexPowerControl: + + - 1.71 V to 3.6 V power supply + - -40 °C to +85/125 °C temperature range + - Low-power background autonomous mode (LPBAM): autonomous peripherals with + DMA, functional down to Stop 2 mode + - VBAT mode: supply for RTC, 32 x 32-bit backup registers and 2-Kbyte backup SRAM + - 150 nA Shutdown mode (24 wake-up pins) + - 195 nA Standby mode (24 wake-up pins) + - 480 nA Standby mode with RTC + - 2 µA Stop 3 mode with 40-Kbyte SRAM + - 8.2 µA Stop 3 mode with 2.5-Mbyte SRAM + - 4.65 µA Stop 2 mode with 40-Kbyte SRAM + - 17.5 µA Stop 2 mode with 2.5-Mbyte SRAM + - 18.5 µA/MHz Run mode at 3.3 V + +- Core: + + - Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, + and FPU ART Accelerator + - 32-Kbyte ICACHE allowing 0-wait-state execution from flash and external + memories: frequency up to 160 MHz, 240 DMIPS + - 16-Kbyte DCACHE1 for external memories + +- Power management: + + - Embedded regulator (LDO) and SMPSstep-down converter supporting switch + on-the-fly and voltage scaling + +- Benchmarks: + + - 1.5 DMIPS/MHz (Drystone 2.1) + - 655 CoreMark® (4.09 CoreMark®/MHz) + - 369 ULPMark™-CP + - 89 ULPMark™-PP + - 47.2 ULPMark™-CM + - 120000 SecureMark™-TLS + +- Memories: + + - 4-Mbyte flash memory with ECC, 2 banks readwhile-write, including 512 Kbytes + with 100 kcycles + - With SRAM3 ECC off: 2514-Kbyte RAM including 66 Kbytes with ECC + - With SRAM3 ECC on: 2450-Kbyte RAMincluding 322 Kbytes with ECC + - External memory interface supporting SRAM,PSRAM, NOR, NAND, and FRAM memories + - 2 Octo-SPI memory interfaces + - 16-bit HSPI memory interface up to 160 MHz + +- Rich graphic features: + + - Neo-Chrom GPU (GPU2D) accelerating any angle rotation, scaling, and + perspective correct texture mapping + - 16-Kbyte DCACHE2 + - Chrom-ART Accelerator (DMA2D) for smoothmotion and transparency effects + - Chrom-GRC (GFXMMU) allowing up to 20 % of graphic resources optimization + - MIPI® DSI host controller with two DSI lanes running at up to 500 Mbit/s each + - LCD-TFT controller (LTDC) + - Digital camera interface + +- General-purpose input/outputs: + + - Up to 156 fast I/Os with interrupt capability most 5V-tolerant and + up to 14 I/Os with independent supply down to 1.08 V + +- Clock management: + + - 4 to 50 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC (± 1 %) + - Internal low-power 32 kHz RC (± 5 %) + - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one + autotrimmed by LSE (better than ± 0.25 % accuracy) + - Internal 48 MHz + - 5 PLLs for system clock, USB, audio, ADC, DSI + +- Security and cryptography: + + - SESIP3 and PSA Level 3 Certified Assurance Target + - Arm® TrustZone® and securable I/Os, memories, and peripherals + - Flexible life cycle scheme with RDP andpassword-protected debug + - Root of trust thanks to unique boot entry and secure hide-protection area (HDP) + - Secure firmware installation (SFI) thanks to embedded root secure services (RSS) + - Secure data storage with hardware unique key (HUK) + - Secure firmware upgrade support with TF-M + - 2 AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - True random number generator, NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte OTP (one-time programmable) + - Active tampers + +- Up to 17 timers, 2 watchdogs and RTC: + + - 19 timers: 2 16-bit advanced motor-control, 4 32-bit, 3 16-bit general + purpose, 2 16-bit basic, 4 low-power 16-bit (available in Stop mode), + 2 SysTick timers, and 2 watchdogs + - RTC with hardware calendar, alarms, and calibration + +- Up to 25 communication peripherals: + + - 1 USB Type-C®/USB power delivery controller + - 1 USB OTG high-speed with embedded PHY + - 2 SAIs (serial audio interface) + - 6 I2C FM+(1 Mbit/s), SMBus/PMBus™ + - 7 USARTs (ISO 7816, LIN, IrDA, modem) + - 3 SPIs (6x SPIs with OCTOSPI/HSPI) + - 1 CAN FD controller + - 2 SDMMC interfaces + - 1 multifunction digital filter (6 filters) + 1 audio digital filter + with sound-activity detection + - Parallel synchronous slave interface + +- Mathematical coprocessor: + + - CORDIC for trigonometric functions acceleration + - FMAC (filter mathematical accelerator) + +- Rich analog peripherals (independent supply): + + - 2 14-bit ADC 2.5-Msps with hardware oversampling + - 1 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode + - 12-bit DAC (2 channels), low-power sample, and hold, autonomous in Stop 2 mode + - 2 operational amplifiers with built-in PGA + - 2 ultra-low-power comparators + +- ECOPACK2 compliant packages + +More information about STM32U5A5ZJ can be found here: + +- `STM32U5A5ZJ on www.st.com`_ +- `STM32U5A5 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CAN/CANFD | on-chip | canbus | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| BKP SRAM | on-chip | Backup SRAM | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig` + + +Connections and IOs +=================== + +Nucleo U5A5ZJ Q Board has 10 GPIO controllers. These controllers are responsible +for pin muxing, input/output, pull-up, etc. + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + + +- CAN/CANFD_TX: PD1 +- CAN/CANFD_RX: PD0 +- DAC1_OUT1 : PA4 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB9 +- I2C_2_SCL : PF1 +- I2C_2_SDA : PF0 +- LD1 : PC7 +- LD2 : PB7 +- LD3 : PG2 +- LPUART_1_TX : PG7 +- LPUART_1_RX : PG8 +- SPI_1_NSS : PA4 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- USER_PB : PC13 + +System Clock +------------ + +Nucleo U5A5ZJ Q System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +160MHz, driven by 4MHz medium speed internal oscillator. + +Serial Port +----------- + +Nucleo U5A5ZJ Q board has 6 U(S)ARTs. The Zephyr console output is assigned to +USART1. Default settings are 115200 8N1. + + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB50`` jumper on the back side of the board. + + +Programming and Debugging +************************* + +Nucleo U5A5ZJ-Q board includes an ST-LINK/V3 embedded debug tool interface. +This probe allows to flash the board using various tools. + +Flashing +======== + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board. + +Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be +used to flash and debug the board if west is told to use it as runner, +which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``. + +For pyocd additional target information needs to be installed. +This can be done by executing the following commands. + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32u5 + + +Flashing an application to Nucleo U5A5ZJ Q +------------------------------------------ + +Connect the Nucleo U5A5ZJ Q to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_u5a5zj_q + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +Default flasher for this board is openocd. It could be used in the usual way. +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_u5a5zj_q + :goals: debug + +Building a secure/non-secure with Arm ® TrustZone ® +=========================================================== + +The TF-M applications can be run on this board, thanks to its Arm ® TrustZone ® +support. +In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image +can be generated using ``nucleo_u5a5zj_q_ns`` as build target. + +.. code-block:: bash + + $ west build -b nucleo_u5a5zj_q_ns path/to/source/directory + +Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script +is run automatically in a post-build step to make some required flash layout changes. + +Once the build is completed, run the following script to initialize the option bytes. + +.. code-block:: bash + + $ build/tfm/regression.sh + +Finally, to flash the board, run: + +.. code-block:: bash + + $ west flash + +Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts +(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` +(which is used for initialization) is available in the PATH. + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/um2861-stm32u5-nucleo144-board-mb1549-stmicroelectronics.pdf + +.. _STM32U5A5ZJ on www.st.com: + https://www.st.com/en/microcontrollers/stm32u5a5zj.html + +.. _STM32U5A5 reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STMicroelectronics customized version of OpenOCD: + https://github.com/STMicroelectronics/OpenOCD diff --git a/boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi rename to boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi diff --git a/boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts rename to boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts diff --git a/boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml rename to boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml diff --git a/boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig similarity index 85% rename from boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig rename to boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig index 3134af0b6a7..08e07645470 100644 --- a/boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U5A5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_u5a5zj_q/support/openocd.cfg b/boards/st/nucleo_u5a5zj_q/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/support/openocd.cfg rename to boards/st/nucleo_u5a5zj_q/support/openocd.cfg diff --git a/boards/st/nucleo_wb55rg/Kconfig.defconfig b/boards/st/nucleo_wb55rg/Kconfig.defconfig new file mode 100644 index 00000000000..a4822901739 --- /dev/null +++ b/boards/st/nucleo_wb55rg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32WB55RG Nucleo board configuration + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_WB55RG + +choice BT_HCI_BUS_TYPE + default BT_STM32_IPM + depends on BT +endchoice + +endif diff --git a/boards/st/nucleo_wb55rg/Kconfig.nucleo_wb55rg b/boards/st/nucleo_wb55rg/Kconfig.nucleo_wb55rg new file mode 100644 index 00000000000..8ed5f797872 --- /dev/null +++ b/boards/st/nucleo_wb55rg/Kconfig.nucleo_wb55rg @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_WB55RG + select SOC_STM32WB55XX diff --git a/boards/arm/nucleo_wb55rg/arduino_r3_connector.dtsi b/boards/st/nucleo_wb55rg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_wb55rg/arduino_r3_connector.dtsi rename to boards/st/nucleo_wb55rg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_wb55rg/board.cmake b/boards/st/nucleo_wb55rg/board.cmake similarity index 100% rename from boards/arm/nucleo_wb55rg/board.cmake rename to boards/st/nucleo_wb55rg/board.cmake diff --git a/boards/st/nucleo_wb55rg/board.yml b/boards/st/nucleo_wb55rg/board.yml new file mode 100644 index 00000000000..49366ba9e62 --- /dev/null +++ b/boards/st/nucleo_wb55rg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_wb55rg + vendor: st + socs: + - name: stm32wb55xx diff --git a/boards/arm/nucleo_wb55rg/doc/img/nucleowb55rg.jpg b/boards/st/nucleo_wb55rg/doc/img/nucleowb55rg.jpg similarity index 100% rename from boards/arm/nucleo_wb55rg/doc/img/nucleowb55rg.jpg rename to boards/st/nucleo_wb55rg/doc/img/nucleowb55rg.jpg diff --git a/boards/arm/nucleo_wb55rg/doc/nucleo_wb55rg.rst b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst similarity index 99% rename from boards/arm/nucleo_wb55rg/doc/nucleo_wb55rg.rst rename to boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst index 835b99f227f..04bdc9d45ec 100644 --- a/boards/arm/nucleo_wb55rg/doc/nucleo_wb55rg.rst +++ b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst @@ -177,7 +177,7 @@ The Zephyr nucleo_wb55rg board configuration supports the following hardware fea Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: -``boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig`` +:zephyr_file:`boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig` Bluetooth and compatibility with STM32WB Copro Wireless Binaries ================================================================ diff --git a/boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts similarity index 100% rename from boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts rename to boards/st/nucleo_wb55rg/nucleo_wb55rg.dts diff --git a/boards/arm/nucleo_wb55rg/nucleo_wb55rg.yaml b/boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml similarity index 100% rename from boards/arm/nucleo_wb55rg/nucleo_wb55rg.yaml rename to boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml diff --git a/boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig b/boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig similarity index 83% rename from boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig rename to boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig index 9fdd732848e..75373aa997c 100644 --- a/boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig +++ b/boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WBX=y -CONFIG_SOC_STM32WB55XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_wb55rg/support/openocd.cfg b/boards/st/nucleo_wb55rg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_wb55rg/support/openocd.cfg rename to boards/st/nucleo_wb55rg/support/openocd.cfg diff --git a/boards/st/nucleo_wba52cg/Kconfig.defconfig b/boards/st/nucleo_wba52cg/Kconfig.defconfig new file mode 100644 index 00000000000..6bf6d3f610f --- /dev/null +++ b/boards/st/nucleo_wba52cg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32WBA52CG Nucleo board configuration + +# Copyright (c) 2023 STMicroelectronics + +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_WBA52CG + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_WBA52CG diff --git a/boards/st/nucleo_wba52cg/Kconfig.nucleo_wba52cg b/boards/st/nucleo_wba52cg/Kconfig.nucleo_wba52cg new file mode 100644 index 00000000000..515685e5715 --- /dev/null +++ b/boards/st/nucleo_wba52cg/Kconfig.nucleo_wba52cg @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_WBA52CG + select SOC_STM32WBA52XX diff --git a/boards/arm/nucleo_wba52cg/arduino_r3_connector.dtsi b/boards/st/nucleo_wba52cg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_wba52cg/arduino_r3_connector.dtsi rename to boards/st/nucleo_wba52cg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_wba52cg/board.cmake b/boards/st/nucleo_wba52cg/board.cmake similarity index 100% rename from boards/arm/nucleo_wba52cg/board.cmake rename to boards/st/nucleo_wba52cg/board.cmake diff --git a/boards/st/nucleo_wba52cg/board.yml b/boards/st/nucleo_wba52cg/board.yml new file mode 100644 index 00000000000..70950acf34d --- /dev/null +++ b/boards/st/nucleo_wba52cg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_wba52cg + vendor: st + socs: + - name: stm32wba52xx diff --git a/boards/arm/nucleo_wba52cg/doc/img/nucleowba52cg.jpg b/boards/st/nucleo_wba52cg/doc/img/nucleowba52cg.jpg similarity index 100% rename from boards/arm/nucleo_wba52cg/doc/img/nucleowba52cg.jpg rename to boards/st/nucleo_wba52cg/doc/img/nucleowba52cg.jpg diff --git a/boards/arm/nucleo_wba52cg/doc/nucleo_wba52cg.rst b/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst similarity index 98% rename from boards/arm/nucleo_wba52cg/doc/nucleo_wba52cg.rst rename to boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst index db45d48a7fa..cb72fdfb831 100644 --- a/boards/arm/nucleo_wba52cg/doc/nucleo_wba52cg.rst +++ b/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst @@ -183,7 +183,7 @@ The Zephyr nucleo_wba52cg board configuration supports the following hardware fe Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: -``boards/arm/nucleo_wba52cg/nucleo_wba52cg_defconfig`` +:zephyr_file:`boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig` Connections and IOs =================== @@ -233,7 +233,7 @@ For now, openocd support is available only on upstream OpenOCD. You can check In order to use it, you should clone and compile it following usual README guidelines. Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in -:zephyr_file:`boards/arm/nucleo_wba52cg/board.cmake` to point the build +:zephyr_file:`boards/st/nucleo_wba52cg/board.cmake` to point the build to the paths of the OpenOCD binary and its scripts, before including the common openocd.board.cmake file: diff --git a/boards/arm/nucleo_wba52cg/nucleo_wba52cg.dts b/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts similarity index 100% rename from boards/arm/nucleo_wba52cg/nucleo_wba52cg.dts rename to boards/st/nucleo_wba52cg/nucleo_wba52cg.dts diff --git a/boards/arm/nucleo_wba52cg/nucleo_wba52cg.yaml b/boards/st/nucleo_wba52cg/nucleo_wba52cg.yaml similarity index 100% rename from boards/arm/nucleo_wba52cg/nucleo_wba52cg.yaml rename to boards/st/nucleo_wba52cg/nucleo_wba52cg.yaml diff --git a/boards/arm/nucleo_wba52cg/nucleo_wba52cg_defconfig b/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig similarity index 85% rename from boards/arm/nucleo_wba52cg/nucleo_wba52cg_defconfig rename to boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig index 9b917b0fc69..08e07645470 100644 --- a/boards/arm/nucleo_wba52cg/nucleo_wba52cg_defconfig +++ b/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32WBAX=y -CONFIG_SOC_STM32WBA52XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_wba52cg/support/openocd.cfg b/boards/st/nucleo_wba52cg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_wba52cg/support/openocd.cfg rename to boards/st/nucleo_wba52cg/support/openocd.cfg diff --git a/boards/st/nucleo_wba55cg/Kconfig.defconfig b/boards/st/nucleo_wba55cg/Kconfig.defconfig new file mode 100644 index 00000000000..4a4717a5659 --- /dev/null +++ b/boards/st/nucleo_wba55cg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32WBA52CG Nucleo board configuration + +# Copyright (c) 2023 STMicroelectronics + +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_WBA55CG + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_WBA55CG diff --git a/boards/st/nucleo_wba55cg/Kconfig.nucleo_wba55cg b/boards/st/nucleo_wba55cg/Kconfig.nucleo_wba55cg new file mode 100644 index 00000000000..83289b3635b --- /dev/null +++ b/boards/st/nucleo_wba55cg/Kconfig.nucleo_wba55cg @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_WBA55CG + select SOC_STM32WBA55XX diff --git a/boards/arm/nucleo_wba55cg/arduino_r3_connector.dtsi b/boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_wba55cg/arduino_r3_connector.dtsi rename to boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_wba55cg/board.cmake b/boards/st/nucleo_wba55cg/board.cmake similarity index 100% rename from boards/arm/nucleo_wba55cg/board.cmake rename to boards/st/nucleo_wba55cg/board.cmake diff --git a/boards/st/nucleo_wba55cg/board.yml b/boards/st/nucleo_wba55cg/board.yml new file mode 100644 index 00000000000..2fbe6b2bca4 --- /dev/null +++ b/boards/st/nucleo_wba55cg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_wba55cg + vendor: st + socs: + - name: stm32wba55xx diff --git a/boards/arm/nucleo_wba55cg/doc/img/nucleowba55cg.jpg b/boards/st/nucleo_wba55cg/doc/img/nucleowba55cg.jpg similarity index 100% rename from boards/arm/nucleo_wba55cg/doc/img/nucleowba55cg.jpg rename to boards/st/nucleo_wba55cg/doc/img/nucleowba55cg.jpg diff --git a/boards/arm/nucleo_wba55cg/doc/nucleo_wba55cg.rst b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst similarity index 98% rename from boards/arm/nucleo_wba55cg/doc/nucleo_wba55cg.rst rename to boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst index 2ea660da1f1..362d74f0e91 100644 --- a/boards/arm/nucleo_wba55cg/doc/nucleo_wba55cg.rst +++ b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst @@ -181,7 +181,7 @@ The Zephyr nucleo_wba55cg board configuration supports the following hardware fe Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: -``boards/arm/nucleo_wba55cg/nucleo_wba55cg_defconfig`` +:zephyr_file:`boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig` Bluetooh support ---------------- @@ -244,7 +244,7 @@ For now, openocd support is available only on upstream OpenOCD. You can check In order to use it, you should clone and compile it following usual README guidelines. Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in -:zephyr_file:`boards/arm/nucleo_wba55cg/board.cmake` to point the build +:zephyr_file:`boards/st/nucleo_wba55cg/board.cmake` to point the build to the paths of the OpenOCD binary and its scripts, before including the common openocd.board.cmake file: diff --git a/boards/arm/nucleo_wba55cg/nucleo_wba55cg.dts b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts similarity index 100% rename from boards/arm/nucleo_wba55cg/nucleo_wba55cg.dts rename to boards/st/nucleo_wba55cg/nucleo_wba55cg.dts diff --git a/boards/arm/nucleo_wba55cg/nucleo_wba55cg.yaml b/boards/st/nucleo_wba55cg/nucleo_wba55cg.yaml similarity index 100% rename from boards/arm/nucleo_wba55cg/nucleo_wba55cg.yaml rename to boards/st/nucleo_wba55cg/nucleo_wba55cg.yaml diff --git a/boards/arm/nucleo_wba55cg/nucleo_wba55cg_defconfig b/boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig similarity index 88% rename from boards/arm/nucleo_wba55cg/nucleo_wba55cg_defconfig rename to boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig index 2c523d88019..98bb440f4ab 100644 --- a/boards/arm/nucleo_wba55cg/nucleo_wba55cg_defconfig +++ b/boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig @@ -1,9 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2023 STMicroelectronics -CONFIG_SOC_SERIES_STM32WBAX=y -CONFIG_SOC_STM32WBA55XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_wba55cg/support/openocd.cfg b/boards/st/nucleo_wba55cg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_wba55cg/support/openocd.cfg rename to boards/st/nucleo_wba55cg/support/openocd.cfg diff --git a/boards/st/nucleo_wl55jc/Kconfig.nucleo_wl55jc b/boards/st/nucleo_wl55jc/Kconfig.nucleo_wl55jc new file mode 100644 index 00000000000..365b200dee6 --- /dev/null +++ b/boards/st/nucleo_wl55jc/Kconfig.nucleo_wl55jc @@ -0,0 +1,5 @@ +# Copyright (c) 2020 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_WL55JC + select SOC_STM32WL55XX diff --git a/boards/arm/nucleo_wl55jc/arduino_r3_connector.dtsi b/boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_wl55jc/arduino_r3_connector.dtsi rename to boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_wl55jc/board.cmake b/boards/st/nucleo_wl55jc/board.cmake similarity index 100% rename from boards/arm/nucleo_wl55jc/board.cmake rename to boards/st/nucleo_wl55jc/board.cmake diff --git a/boards/st/nucleo_wl55jc/board.yml b/boards/st/nucleo_wl55jc/board.yml new file mode 100644 index 00000000000..930da79b199 --- /dev/null +++ b/boards/st/nucleo_wl55jc/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_wl55jc + vendor: st + socs: + - name: stm32wl55xx diff --git a/boards/arm/nucleo_wl55jc/doc/img/nucleo_wl55jc.jpg b/boards/st/nucleo_wl55jc/doc/img/nucleo_wl55jc.jpg similarity index 100% rename from boards/arm/nucleo_wl55jc/doc/img/nucleo_wl55jc.jpg rename to boards/st/nucleo_wl55jc/doc/img/nucleo_wl55jc.jpg diff --git a/boards/arm/nucleo_wl55jc/doc/nucleo_wl55jc.rst b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst similarity index 98% rename from boards/arm/nucleo_wl55jc/doc/nucleo_wl55jc.rst rename to boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst index 3d569753f15..df32bbc07c0 100644 --- a/boards/arm/nucleo_wl55jc/doc/nucleo_wl55jc.rst +++ b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst @@ -211,10 +211,10 @@ features: Other hardware features are not yet supported on this Zephyr port. -The default configuration can be found in the defconfig and dts files: +The default configuration can be found in: -- :zephyr_file:`boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig` -- :zephyr_file:`boards/arm/nucleo_wl55jc/nucleo_wl55jc.dts` +- :zephyr_file:`boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig` +- :zephyr_file:`boards/st/nucleo_wl55jc/nucleo_wl55jc.dts` Connections and IOs diff --git a/boards/arm/nucleo_wl55jc/nucleo_wl55jc.dts b/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts similarity index 100% rename from boards/arm/nucleo_wl55jc/nucleo_wl55jc.dts rename to boards/st/nucleo_wl55jc/nucleo_wl55jc.dts diff --git a/boards/arm/nucleo_wl55jc/nucleo_wl55jc.yaml b/boards/st/nucleo_wl55jc/nucleo_wl55jc.yaml similarity index 100% rename from boards/arm/nucleo_wl55jc/nucleo_wl55jc.yaml rename to boards/st/nucleo_wl55jc/nucleo_wl55jc.yaml diff --git a/boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig b/boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig similarity index 83% rename from boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig rename to boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig index 813ba6643cc..0d6dc9f80d3 100644 --- a/boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig +++ b/boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WLX=y -CONFIG_SOC_STM32WL55XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_wl55jc/st_morpho_connector.dtsi b/boards/st/nucleo_wl55jc/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_wl55jc/st_morpho_connector.dtsi rename to boards/st/nucleo_wl55jc/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_wl55jc/support/openocd.cfg b/boards/st/nucleo_wl55jc/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_wl55jc/support/openocd.cfg rename to boards/st/nucleo_wl55jc/support/openocd.cfg diff --git a/boards/st/sensortile_box/Kconfig.defconfig b/boards/st/sensortile_box/Kconfig.defconfig new file mode 100644 index 00000000000..29aa7598ef8 --- /dev/null +++ b/boards/st/sensortile_box/Kconfig.defconfig @@ -0,0 +1,31 @@ +# SensorTile.box board configuration + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SENSORTILE_BOX + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +config BT_BLUENRG_ACI + default y +# Disable Flow control +config BT_HCI_ACL_FLOW_CONTROL + default n +config BT_HCI_VS_EXT + default n + +endif # BT + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_SENSORTILE_BOX diff --git a/boards/st/sensortile_box/Kconfig.sensortile_box b/boards/st/sensortile_box/Kconfig.sensortile_box new file mode 100644 index 00000000000..0d7ec6b82af --- /dev/null +++ b/boards/st/sensortile_box/Kconfig.sensortile_box @@ -0,0 +1,5 @@ +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SENSORTILE_BOX + select SOC_STM32L4R9XX diff --git a/boards/arm/96b_carbon/board.cmake b/boards/st/sensortile_box/board.cmake similarity index 100% rename from boards/arm/96b_carbon/board.cmake rename to boards/st/sensortile_box/board.cmake diff --git a/boards/st/sensortile_box/board.yml b/boards/st/sensortile_box/board.yml new file mode 100644 index 00000000000..4ac086b2cb7 --- /dev/null +++ b/boards/st/sensortile_box/board.yml @@ -0,0 +1,5 @@ +board: + name: sensortile_box + vendor: st + socs: + - name: stm32l4r9xx diff --git a/boards/arm/sensortile_box/doc/img/sensortile_box.jpg b/boards/st/sensortile_box/doc/img/sensortile_box.jpg similarity index 100% rename from boards/arm/sensortile_box/doc/img/sensortile_box.jpg rename to boards/st/sensortile_box/doc/img/sensortile_box.jpg diff --git a/boards/arm/sensortile_box/doc/index.rst b/boards/st/sensortile_box/doc/index.rst similarity index 100% rename from boards/arm/sensortile_box/doc/index.rst rename to boards/st/sensortile_box/doc/index.rst diff --git a/boards/arm/sensortile_box/sensortile_box.dts b/boards/st/sensortile_box/sensortile_box.dts similarity index 100% rename from boards/arm/sensortile_box/sensortile_box.dts rename to boards/st/sensortile_box/sensortile_box.dts diff --git a/boards/arm/sensortile_box/sensortile_box.yaml b/boards/st/sensortile_box/sensortile_box.yaml similarity index 100% rename from boards/arm/sensortile_box/sensortile_box.yaml rename to boards/st/sensortile_box/sensortile_box.yaml diff --git a/boards/arm/sensortile_box/sensortile_box_defconfig b/boards/st/sensortile_box/sensortile_box_defconfig similarity index 85% rename from boards/arm/sensortile_box/sensortile_box_defconfig rename to boards/st/sensortile_box/sensortile_box_defconfig index 2970c68d6c9..4ba8077edd6 100644 --- a/boards/arm/sensortile_box/sensortile_box_defconfig +++ b/boards/st/sensortile_box/sensortile_box_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4R9XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/swan_r5/support/openocd.cfg b/boards/st/sensortile_box/support/openocd.cfg similarity index 100% rename from boards/arm/swan_r5/support/openocd.cfg rename to boards/st/sensortile_box/support/openocd.cfg diff --git a/boards/arm/sensortile_box_pro/CMakeLists.txt b/boards/st/sensortile_box_pro/CMakeLists.txt similarity index 100% rename from boards/arm/sensortile_box_pro/CMakeLists.txt rename to boards/st/sensortile_box_pro/CMakeLists.txt diff --git a/boards/st/sensortile_box_pro/Kconfig.defconfig b/boards/st/sensortile_box_pro/Kconfig.defconfig new file mode 100644 index 00000000000..f0271728a9a --- /dev/null +++ b/boards/st/sensortile_box_pro/Kconfig.defconfig @@ -0,0 +1,39 @@ +# SENSORTILE_BOX_PRO board configuration + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SENSORTILE_BOX_PRO + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +config BT_BLUENRG_ACI + default y + +# Disable Flow control +config BT_HCI_ACL_FLOW_CONTROL + default n + +endif # BT + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +if LOG + +# Logger cannot use itself to log +choice USB_CDC_ACM_LOG_LEVEL_CHOICE + default USB_CDC_ACM_LOG_LEVEL_OFF +endchoice + +endif # LOG + +endif # BOARD_SENSORTILE_BOX_PRO diff --git a/boards/st/sensortile_box_pro/Kconfig.sensortile_box_pro b/boards/st/sensortile_box_pro/Kconfig.sensortile_box_pro new file mode 100644 index 00000000000..b0928107887 --- /dev/null +++ b/boards/st/sensortile_box_pro/Kconfig.sensortile_box_pro @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SENSORTILE_BOX_PRO + select SOC_STM32U585XX diff --git a/boards/arm/sensortile_box_pro/board.c b/boards/st/sensortile_box_pro/board.c similarity index 100% rename from boards/arm/sensortile_box_pro/board.c rename to boards/st/sensortile_box_pro/board.c diff --git a/boards/arm/sensortile_box_pro/board.cmake b/boards/st/sensortile_box_pro/board.cmake similarity index 100% rename from boards/arm/sensortile_box_pro/board.cmake rename to boards/st/sensortile_box_pro/board.cmake diff --git a/boards/st/sensortile_box_pro/board.yml b/boards/st/sensortile_box_pro/board.yml new file mode 100644 index 00000000000..d3bb8ca9ee9 --- /dev/null +++ b/boards/st/sensortile_box_pro/board.yml @@ -0,0 +1,5 @@ +board: + name: sensortile_box_pro + vendor: st + socs: + - name: stm32u585xx diff --git a/boards/arm/sensortile_box_pro/doc/img/sensortile_box_pro.jpg b/boards/st/sensortile_box_pro/doc/img/sensortile_box_pro.jpg similarity index 100% rename from boards/arm/sensortile_box_pro/doc/img/sensortile_box_pro.jpg rename to boards/st/sensortile_box_pro/doc/img/sensortile_box_pro.jpg diff --git a/boards/st/sensortile_box_pro/doc/index.rst b/boards/st/sensortile_box_pro/doc/index.rst new file mode 100644 index 00000000000..e98ddace1bb --- /dev/null +++ b/boards/st/sensortile_box_pro/doc/index.rst @@ -0,0 +1,386 @@ +.. _sensortile_box_pro_board: + +ST SensorTile.box PRO +##################### + +Overview +******** + +The STEVAL-MKBOXPRO (SensorTile.box PRO) features an ARM Cortex-M33 based STM32U585AI MCU +and is a ready-to-use box kit for wireless IoT and wearable sensor platforms to help using +and developing apps based on remote motion and environmental sensor data. + +The SensorTile.box PRO board fits into a small plastic box with a long-life rechargeable +battery, and communicates with a standard smartphone through its Bluetooth interface, +providing data coming from the sensors. + +.. image:: img/sensortile_box_pro.jpg + :align: center + :alt: SensorTile.box PRO + +More information about the board can be found at the `SensorTile.box PRO website`_. + +Supported Features +****************** + +The SensorTile.box PRO provides motion, environmental, and audio +sensor data through either the BLE or USB protocols to a host application running +on a smartphone/PC to implement applications such as: + +- Pedometer optimized for belt positioning +- Baby crying detection with Cloud AI learning +- Barometer / environmental monitoring +- Vehicle / goods tracking +- Vibration monitoring +- Compass and inclinometer +- Sensor data logger + +(see `Motion and environmental sensors`_ section for the complete lists of available +sensors on board) + +Hardware +******** + +The STM32U585xx devices are an ultra-low-power microcontrollers family (STM32U5 +Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. +They operate at a frequency of up to 160 MHz. + +- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1.5 DMPIS/MHz (Drystone 2.1) + - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) + +- Security and cryptography + + - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals + - Flexible life cycle scheme with RDP (readout protection) and password protected debug + - Root of trust thanks to unique boot entry and secure hide protection area (HDP) + - Secure Firmware Installation thanks to embedded Root Secure Services + - Secure data storage with hardware unique key (HUK) + - Secure Firmware Update support with TF-M + - 2 AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - Active tampers + - True Random Number Generator NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte One-Time Programmable for user data + - Active tampers + +- Clock management: + + - 4 to 50 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + - Internal 48 MHz with clock recovery + +- Power management + + - Embedded regulator (LDO) + - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling + +- RTC with HW calendar and calibration +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- Up to 17 timers and 2 watchdogs + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5 x 16-bit general purpose + - 4x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- ART accelerator + + - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and + external memories: up to 160 MHz, MPU, 240 DMIPS and DSP + - 4-Kbyte data cache for external memories + +- Memories + + - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles + - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON + - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories + - 2 Octo-SPI memory interfaces + +- Rich analog peripherals (independent supply) + + - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling + - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode + - 12-bit DAC, low-power sample and hold + - 2 operational amplifiers with built-in PGA + - 2 ultra-low-power comparators + +- Up to 22 communication interfaces + + - USB Type-C / USB power delivery controller + - USB OTG 2.0 full-speed controller + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) + - 1x FDCAN + - 2x SDMMC interface + - 16- and 4-channel DMA controllers, functional in Stop mode + - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with + sound-activity detection + +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| +- True Random Number Generator (RNG) + +- Graphic features + + - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation + - 1 digital camera interface + +- Mathematical co-processor + + - CORDIC for trigonometric functions acceleration + - FMAC (filter mathematical accelerator) + + +More information about STM32U585AI can be found here: + +- `STM32U585 on www.st.com`_ +- `STM32U585 reference manual`_ + +Motion and environmental sensors +================================ + + - **LSM6DSV16X** 6-axis inertial measurement unit + (`lsm6dsv16x datasheet`_) + - **LIS2MDL** 3-axis magnetometer + (`lis2mdl datasheet`_) + - **LPS22DF** Altimeter / pressure sensor + (`lps22df datasheet`_) + - **LIS2DU12** 3-axis accelerometer + (`lis2du12 datasheet`_) + - **HTS221** Humidity sensor + (`hts221 datasheet`_) + - **STTS22H** Digital temperature sensor + (`stts22hh datasheet`_) + - **MP23db01HP** Microphone / audio sensor + (`mp23db01hp datasheet`_) + +Connections and IOs +=================== + +- 4x user LEDs + + - **led0** (Green) + - **led1** (Red - shared with BLE) + - **led2** (Yellow) + - **led3** (Blue) + + +- 4x buttons/switch + + - **User BT1** button, available to user application + - **User BT2** / **boot0** button, available to user application + but useful to let the SensorTile.box PRO enter DFU mode + if found pressed after h/w reset (see **rst** button and + `Programming and Debugging`_ section) + - **rst** button, used to reset the board (not available on case) + - **power** switch, used to Power on/off the board + +System Clock +============ + +SensorTile.box PRO System Clock could be driven by internal or external +oscillator, as well as main PLL clock. By default, the System clock is +driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator. +The system clock can be boosted to 120MHz. +The internal AHB/APB1/APB2 AMBA buses are all clocked at 80MHz. + +Serial Port +=========== + +The SensorTile.box PRO has 4 U(S)ARTs. The UART4 is connected to JTAG/SWD connector +and may be used as console. + +USB interface +============= + +SensorTile.box PRO can be connected as a USB device to a PC host through its USB-C connector. +The final application may use it to declare SensorTile.box PRO device as belonging to a +certain standard or vendor class, e.g. a CDC, a mass storage or a composite device with both +functions. + +Console +======= + +There are two possible options for Zephyr console output: + +- through UART4 which is available on SWD connector (JP2). In this case a JTAG adapter + can be used to connect SensorTile.box PRO and have both SWD and console lines available. + + To enable console and shell over UART + + - switch the console lines from cdc_acm to uart4 + (:file:`boards/st/sensortile_box_pro/sensortile_box_pro.dts`) + + - comment out the USB configuration macros + (:file:`boards/st/sensortile_box_pro/sensortile_box_pro_defconfig`) + +.. code-block:: dts + :caption: boards/st/sensortile_box_pro/sensortile_box_pro.dts + + / { + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + //zephyr,console = &cdc_acm_uart0; + //zephyr,shell-uart = &cdc_acm_uart0; + }; + }; + +.. code-block:: Kconfig + :caption: boards/st/sensortile_box_pro/sensortile_box_pro_defconfig + + # Comment out following USB config lines when + # switching console to UART + #CONFIG_USB_DEVICE_STACK=y + #CONFIG_USB_DEVICE_VID=0x0483 + #CONFIG_USB_DEVICE_PID=0x1235 + #CONFIG_USB_DEVICE_PRODUCT="Zephyr CDC SensorTile.box PRO" + #CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y + #CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n + + +- through USB as USB CDC/ACM class. This is the default case present in the board dts file. + +.. code-block:: dts + :caption: boards/st/sensortile_box_pro/sensortile_box_pro.dts + + / { + chosen { + zephyr,console = &cdc_acm_uart0; + }; + }; + + &zephyr_udc0 { + cdc_acm_uart0: cdc_acm_uart0 { + compatible = "zephyr,cdc-acm-uart"; + }; + }; + + + +Console default settings are 115200 8N1. + +Programming and Debugging +************************* + +There are two alternative methods of flashing ST Sensortile.box Pro board: + +1. Using DFU software tools + + This method requires to enter STM32U585 ROM bootloader DFU mode + by powering up (or reset) the board while keeping the BOOT0 button pressed. + No additional hardware is required except a USB-C cable. This method is fully + supported by :ref:`flash-debug-host-tools`. + You can read more about how to enable and use the ROM bootloader by checking + the application note `AN2606`_ (STM32U585xx section). + +2. Using SWD hardware tools + + This method requires to connect additional hardware, like a ST-LINK/V3 + embedded debug tool, to the board SWD connector. + +DFU flashing +============ + +Install dfu-util +---------------- + +It is recommended to use at least v0.9 of dfu-util. The package available in +Debian and Ubuntu can be quite old, so you might have to build dfu-util from source. +Information about how to get the source code and how to build it can be found +at the `DFU-UTIL website`_ + +Flash an Application to SensorTile.box PRO +------------------------------------------ + +While pressing the BOOT0 button, connect the USB-C cable to the USB OTG SensorTile.box PRO +port and to your computer. The board should be forced to enter DFU mode. + +Check that the board is indeed in DFU mode: + +.. code-block:: console + + $ sudo dfu-util -l + dfu-util 0.9 + + Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. + Copyright 2010-2019 Tormod Volden and Stefan Schmidt + This program is Free Software and has ABSOLUTELY NO WARRANTY + Please report bugs to http://sourceforge.net/p/dfu-util/tickets/ + + Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=2, name="@OTP Memory /0x1FFF7000/01*0001Ke", serial="204A325D574D" + Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=1, name="@Option Bytes /0x1FF00000/01*040 e/0x1FF01000/01*040 e", serial="204A325D574D" + Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=0, name="@Internal Flash /0x08000000/512*0004Kg", serial="204A325D574D" + +You should see following confirmation on your Linux host: + +.. code-block:: console + + $ dmesg + usb 2-2: new full-speed USB device number 74 using xhci_hcd + usb 2-2: New USB device found, idVendor=0483, idProduct=df11 + usb 2-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 + usb 2-2: Product: STM32 BOOTLOADER + usb 2-2: Manufacturer: STMicroelectronics + usb 2-2: SerialNumber: 204A325D574D + +You can build and flash the provided sample application +(:ref:`sensortile_box_pro_sample_sensors`) that reads sensors data and outputs +values on the console. + +References +********** + +.. target-notes:: + +.. _SensorTile.box PRO website: + https://www.st.com/en/evaluation-tools/steval-mkboxpro.html + +.. _STM32U585 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html + +.. _STM32U585 reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _lsm6dsv16x datasheet: + https://www.st.com/en/mems-and-sensors/lsm6dsv16x.html + +.. _lis2mdl datasheet: + https://www.st.com/en/mems-and-sensors/lis2mdl.html + +.. _lps22df datasheet: + https://www.st.com/en/mems-and-sensors/lps22df.html + +.. _lis2du12 datasheet: + https://www.st.com/en/mems-and-sensors/lis2du12.html + +.. _hts221 datasheet: + https://www.st.com/en/mems-and-sensors/hts221.html + +.. _stts22hh datasheet: + https://www.st.com/en/mems-and-sensors/stts22h.html + +.. _mp23db01hp datasheet: + https://www.st.com/en/mems-and-sensors/mp23db01hp.html + +.. _AN2606: + http://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf + +.. _DFU-UTIL website: + http://dfu-util.sourceforge.net/ diff --git a/boards/arm/sensortile_box_pro/sensortile_box_pro.dts b/boards/st/sensortile_box_pro/sensortile_box_pro.dts similarity index 100% rename from boards/arm/sensortile_box_pro/sensortile_box_pro.dts rename to boards/st/sensortile_box_pro/sensortile_box_pro.dts diff --git a/boards/arm/sensortile_box_pro/sensortile_box_pro.yaml b/boards/st/sensortile_box_pro/sensortile_box_pro.yaml similarity index 100% rename from boards/arm/sensortile_box_pro/sensortile_box_pro.yaml rename to boards/st/sensortile_box_pro/sensortile_box_pro.yaml diff --git a/boards/arm/sensortile_box_pro/sensortile_box_pro_defconfig b/boards/st/sensortile_box_pro/sensortile_box_pro_defconfig similarity index 92% rename from boards/arm/sensortile_box_pro/sensortile_box_pro_defconfig rename to boards/st/sensortile_box_pro/sensortile_box_pro_defconfig index 7a91dc1c195..a47f372d784 100644 --- a/boards/arm/sensortile_box_pro/sensortile_box_pro_defconfig +++ b/boards/st/sensortile_box_pro/sensortile_box_pro_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U585XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/sensortile_box_pro/support/openocd.cfg b/boards/st/sensortile_box_pro/support/openocd.cfg similarity index 100% rename from boards/arm/sensortile_box_pro/support/openocd.cfg rename to boards/st/sensortile_box_pro/support/openocd.cfg diff --git a/boards/st/steval_fcu001v1/Kconfig.steval_fcu001v1 b/boards/st/steval_fcu001v1/Kconfig.steval_fcu001v1 new file mode 100644 index 00000000000..d726c3f0e92 --- /dev/null +++ b/boards/st/steval_fcu001v1/Kconfig.steval_fcu001v1 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Linumiz +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STEVAL_FCU001V1 + select SOC_STM32F401XC diff --git a/boards/arm/steval_fcu001v1/board.cmake b/boards/st/steval_fcu001v1/board.cmake similarity index 100% rename from boards/arm/steval_fcu001v1/board.cmake rename to boards/st/steval_fcu001v1/board.cmake diff --git a/boards/st/steval_fcu001v1/board.yml b/boards/st/steval_fcu001v1/board.yml new file mode 100644 index 00000000000..16357770fa4 --- /dev/null +++ b/boards/st/steval_fcu001v1/board.yml @@ -0,0 +1,5 @@ +board: + name: steval_fcu001v1 + vendor: st + socs: + - name: stm32f401xc diff --git a/boards/arm/steval_fcu001v1/doc/img/steval_fcu001v1.jpg b/boards/st/steval_fcu001v1/doc/img/steval_fcu001v1.jpg similarity index 100% rename from boards/arm/steval_fcu001v1/doc/img/steval_fcu001v1.jpg rename to boards/st/steval_fcu001v1/doc/img/steval_fcu001v1.jpg diff --git a/boards/st/steval_fcu001v1/doc/index.rst b/boards/st/steval_fcu001v1/doc/index.rst new file mode 100644 index 00000000000..a76f99c6e01 --- /dev/null +++ b/boards/st/steval_fcu001v1/doc/index.rst @@ -0,0 +1,158 @@ +.. _steval_fcu001v1: + +ST STM32 Flight Controller Unit +############################### + +Overview +******** + +The STEVAL-FCU001V1 is a Cortex M4 MCU-based flight controller unit for toy quad-copter drones. + +.. figure:: img/steval_fcu001v1.jpg + :align: center + :alt: STM32 Flight Controller Unit + +Hardware +******** + +STM32 Flight Controller Unit provides the following hardware components: + +- STM32F401CC in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg|-M4 MCU with FPU +- 84MHz max MCU frequency +- VDD from 1.7 V to 3.6 V +- 256 KB FLASH +- 64 KB SRAM +- General Purpose Timers +- Watchdog Timers (2) +- On board sensors: + + - 3D Accelerometer and 3D Gyroscope: LSM6DSL + - 3D Magnetometer: LIS2MDL + - MEMS Pressure sensor: LPS22HD + +- 2 User LEDS +- USART/UART (1) +- I2C (1) +- Bluetooth LE over SPI + +More information about the STM32 Flight Controller Unit +can be found in these documents: + +- `STEVAL_FCU001V1 website`_ +- `STM32F401 reference manual`_ +- `STM32F401CC on www.st.com`_ + +Supported Features +================== + +The Zephyr steval_fcu001v1 board configuration supports the following hardware features: + ++-----------+------------+------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+------------------------------------+ + + +The default configuration can be found in +:zephyr_file:`boards/st/steval_fcu001v1/steval_fcu001v1_defconfig` + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- I2C2 SCL/SDA : PB10/PB3 +- PWM_2_CH1 : PA0 +- LD1 : PB5 +- LD2 : PB4 + +System Clock +============ + +The steval_fcu001v1 system clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the system clock is driven by the PLL clock at 84MHz, +driven by a 16MHz high-speed external clock. + +Serial Port +=========== + +The steval_fcu001v1 board has one UART. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + +I2C +=== + +The steval_fcu001v1 board has one I2C. The default I2C mapping for Zephyr is: + +- I2C2_SCL : PB10 +- I2C2_SDA : PB3 + +Programming and Debugging +************************* + +Applications for the ``steval_fcu001v1`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Flashing Zephyr onto the steval_fcu001v1 board requires an external ST-LINK/V2-1 programmer. +The programmer is attached to the P8 programming header with ARM-JTAG-20-10-Plug-in Adapter. + +Flashing an application to STEVAL_FCU001V1 +------------------------------------------ + +Connect the FT232-to-USB port to host system, and RX, TX, Gnd pins to +the P7 header of the steval_fcu001v1 board. Then run a serial host +program to connect with your steval_fcu001v1 via the FT232 board: + +.. code-block:: console + + $ minicom -D /dev/ttyUSB0 + +Now build and flash an application. Here is an example for :ref:`hello_world` + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: steval_fcu001v1 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! steval_fcu001v1 + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: steval_fcu001v1 + :maybe-skip-config: + :goals: debug + +.. _STEVAL_FCU001V1 website: + https://www.st.com/en/evaluation-tools/steval-fcu001v1.html + +.. _STM32F401CC on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32f401cc.html + +.. _STM32F401 reference manual: + https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/steval_fcu001v1/steval_fcu001v1.dts b/boards/st/steval_fcu001v1/steval_fcu001v1.dts similarity index 100% rename from boards/arm/steval_fcu001v1/steval_fcu001v1.dts rename to boards/st/steval_fcu001v1/steval_fcu001v1.dts diff --git a/boards/arm/steval_fcu001v1/steval_fcu001v1.yaml b/boards/st/steval_fcu001v1/steval_fcu001v1.yaml similarity index 100% rename from boards/arm/steval_fcu001v1/steval_fcu001v1.yaml rename to boards/st/steval_fcu001v1/steval_fcu001v1.yaml diff --git a/boards/arm/steval_fcu001v1/steval_fcu001v1_defconfig b/boards/st/steval_fcu001v1/steval_fcu001v1_defconfig similarity index 81% rename from boards/arm/steval_fcu001v1/steval_fcu001v1_defconfig rename to boards/st/steval_fcu001v1/steval_fcu001v1_defconfig index 53be30e3c52..e4d07bf3184 100644 --- a/boards/arm/steval_fcu001v1/steval_fcu001v1_defconfig +++ b/boards/st/steval_fcu001v1/steval_fcu001v1_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/steval_fcu001v1/support/openocd.cfg b/boards/st/steval_fcu001v1/support/openocd.cfg similarity index 100% rename from boards/arm/steval_fcu001v1/support/openocd.cfg rename to boards/st/steval_fcu001v1/support/openocd.cfg diff --git a/boards/st/stm3210c_eval/Kconfig.stm3210c_eval b/boards/st/stm3210c_eval/Kconfig.stm3210c_eval new file mode 100644 index 00000000000..40baeecc672 --- /dev/null +++ b/boards/st/stm3210c_eval/Kconfig.stm3210c_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM3210C_EVAL + select SOC_STM32F107XC diff --git a/boards/arm/stm3210c_eval/board.cmake b/boards/st/stm3210c_eval/board.cmake similarity index 100% rename from boards/arm/stm3210c_eval/board.cmake rename to boards/st/stm3210c_eval/board.cmake diff --git a/boards/st/stm3210c_eval/board.yml b/boards/st/stm3210c_eval/board.yml new file mode 100644 index 00000000000..bb8003f01ab --- /dev/null +++ b/boards/st/stm3210c_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: stm3210c_eval + vendor: st + socs: + - name: stm32f107xc diff --git a/boards/arm/stm3210c_eval/doc/img/stm3210c_eval.jpg b/boards/st/stm3210c_eval/doc/img/stm3210c_eval.jpg similarity index 100% rename from boards/arm/stm3210c_eval/doc/img/stm3210c_eval.jpg rename to boards/st/stm3210c_eval/doc/img/stm3210c_eval.jpg diff --git a/boards/arm/stm3210c_eval/doc/img/stm3210c_eval_connectors.jpg b/boards/st/stm3210c_eval/doc/img/stm3210c_eval_connectors.jpg similarity index 100% rename from boards/arm/stm3210c_eval/doc/img/stm3210c_eval_connectors.jpg rename to boards/st/stm3210c_eval/doc/img/stm3210c_eval_connectors.jpg diff --git a/boards/st/stm3210c_eval/doc/index.rst b/boards/st/stm3210c_eval/doc/index.rst new file mode 100644 index 00000000000..383a0e2f5fb --- /dev/null +++ b/boards/st/stm3210c_eval/doc/index.rst @@ -0,0 +1,165 @@ +.. _stm3210c_eval_board: + +ST STM3210C Evaluation +###################### + +Overview +******** +The STM3210C-EVAL evaluation board is a complete development platform for STMicroelectronic's +ARM Cortex-M3 core-based STM32F107VCT microcontroller. + +The range of hardware features on the board help you to evaluate all peripherals +(USB-OTG FS, ethernet, motor control, CAN, microSD CardTM, smartcard, USART, +audio DAC, MEMS, EEPROM and more) and develop your own applications. + +Extension headers make it easy to connect a daughterboard or wrapping board for your specific +application. + +.. image:: img/stm3210c_eval.jpg + :align: center + :alt: STM3210C-EVAL + +More information about the board can be found at the `STM3210C-EVAL website`_. + +Hardware +******** + +STM3210C-EVAL provides the following hardware components: + +- Three 5 V power supply options: + - Power jack + - USB connector + - daughterboard +- Boot from user Flash, system memory or SRAM. +- I2S audio DAC, stereo audio jack. +- 2 GByte (or more) microSD CardTM. +- Both type A and B smartcard support. +- I2C compatible serial interface 64 Kbit EEPROM, MEMS and I/O expander. +- RS-232 communication. +- IrDA transceiver. +- USB-OTG full speed, USB microAB connector. +- IEEE-802.3-2002 compliant ethernet connector. +- Two channels of CAN2.0A/B compliant connection. +- Inductor motor control connector. +- JTAG and trace debug support. +- 3.2" 240x320 TFT color LCD with touch screen. +- Joystick with 4-direction control and selector. +- Reset, Wakeup, Tamper and User button. +- 4 color LEDs. +- RTC with backup battery. +- MCU consumption measurement circuit. +- Extension connector for daughterboard or wrapping board. + +More information about STM32F107VCT can be found here: + - `STM32F107VCT reference manual`_ + + +Supported Features +================== + +The Zephyr stm3210c_eval board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm3210c_eval/stm3210c_eval_defconfig`. + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/stm3210c_eval_connectors.jpg + :align: center + :alt: STM3210C_EVAL connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- USER_PB : PB9 +- LED2 : PD13 + +Programming and Debugging +************************* + +Flashing +======== + +STM3210C-EVAL board includes an ST-LINK/V2-1 embedded debug tool interface. +At power-on, the board is in firmware-upgrade mode (also called DFU for +"Device Firmware Upgrade"), allowing the firmware to be updated through the USB. +This interface is supported by the openocd version included in Zephyr SDK. + +Applications for the ``stm3210c_eval`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing an application to STM3210C-EVAL +---------------------------------------- + +Connect the STM3210C-EVAL to your host computer using the USB port, then build +and flash an application in the usual way. + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm3210c_eval + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can run a serial host program to connect with your STM3210C-EVAL board. For +example, on Linux: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm3210c_eval + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM3210C-EVAL website: + https://www.st.com/en/evaluation-tools/stm3210c-eval.html + +.. _STM32F107VCT reference manual: + https://www.st.com/resource/en/reference_manual/CD00171190.pdf diff --git a/boards/arm/stm3210c_eval/stm3210c_eval.dts b/boards/st/stm3210c_eval/stm3210c_eval.dts similarity index 100% rename from boards/arm/stm3210c_eval/stm3210c_eval.dts rename to boards/st/stm3210c_eval/stm3210c_eval.dts diff --git a/boards/arm/stm3210c_eval/stm3210c_eval.yaml b/boards/st/stm3210c_eval/stm3210c_eval.yaml similarity index 100% rename from boards/arm/stm3210c_eval/stm3210c_eval.yaml rename to boards/st/stm3210c_eval/stm3210c_eval.yaml diff --git a/boards/st/stm3210c_eval/stm3210c_eval_defconfig b/boards/st/stm3210c_eval/stm3210c_eval_defconfig new file mode 100644 index 00000000000..5af8b611205 --- /dev/null +++ b/boards/st/stm3210c_eval/stm3210c_eval_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# RCC Controller +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm3210c_eval/support/openocd.cfg b/boards/st/stm3210c_eval/support/openocd.cfg similarity index 100% rename from boards/arm/stm3210c_eval/support/openocd.cfg rename to boards/st/stm3210c_eval/support/openocd.cfg diff --git a/boards/st/stm32373c_eval/Kconfig.stm32373c_eval b/boards/st/stm32373c_eval/Kconfig.stm32373c_eval new file mode 100644 index 00000000000..fc8baa062de --- /dev/null +++ b/boards/st/stm32373c_eval/Kconfig.stm32373c_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32373C_EVAL + select SOC_STM32F373XC diff --git a/boards/arm/stm32373c_eval/board.cmake b/boards/st/stm32373c_eval/board.cmake similarity index 100% rename from boards/arm/stm32373c_eval/board.cmake rename to boards/st/stm32373c_eval/board.cmake diff --git a/boards/st/stm32373c_eval/board.yml b/boards/st/stm32373c_eval/board.yml new file mode 100644 index 00000000000..32da748e9a7 --- /dev/null +++ b/boards/st/stm32373c_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32373c_eval + vendor: st + socs: + - name: stm32f373xc diff --git a/boards/arm/stm32373c_eval/doc/img/stm32373c_eval.jpg b/boards/st/stm32373c_eval/doc/img/stm32373c_eval.jpg similarity index 100% rename from boards/arm/stm32373c_eval/doc/img/stm32373c_eval.jpg rename to boards/st/stm32373c_eval/doc/img/stm32373c_eval.jpg diff --git a/boards/arm/stm32373c_eval/doc/img/stm32373c_eval_connectors.jpg b/boards/st/stm32373c_eval/doc/img/stm32373c_eval_connectors.jpg similarity index 100% rename from boards/arm/stm32373c_eval/doc/img/stm32373c_eval_connectors.jpg rename to boards/st/stm32373c_eval/doc/img/stm32373c_eval_connectors.jpg diff --git a/boards/st/stm32373c_eval/doc/index.rst b/boards/st/stm32373c_eval/doc/index.rst new file mode 100644 index 00000000000..b6895a4bca2 --- /dev/null +++ b/boards/st/stm32373c_eval/doc/index.rst @@ -0,0 +1,159 @@ +.. _stm32373c_eval_board: + +ST STM32373C Evaluation +####################### + +Overview +******** +The STM32373C-EVAL evaluation board is designed as a complete demonstration and development platform for STMicroelectronics ARM Cortex-M4 core-based STM32F373VCT6 microcontroller. + +The full range of hardware features on the board can help the user evaluate all peripherals (USB FS, USART, audio DAC, microphone ADC, dot-matrix LCD, IrDA, LDR, MicroSD card, HDMI CEC, ECG, pressure sensor, CAN, IR transmitter and receiver, EEPROM, touch slider, temperature sensor, etc.) and develop their own applications. + +Extension headers make it possible to easily connect a daughter board or wrapping board for a specific application. + +.. image:: img/stm32373c_eval.jpg + :align: center + :alt: STM32373C-EVAL + +More information about the board can be found at the `STM32373C-EVAL website`_. + +Hardware +******** + +STM32373C-EVAL provides the following hardware components: + +- STM32F373VCT6 microcontroller +- Four 5 V power supply options: + - Power jack + - ST-LINK/V2 USB connector + - User USB connector + - Daughter board +- Audio jack connected to I2 S DAC +- Microphone connected to ADC through an amplifier +- 2-GByte (or more) MicroSD card on SPI +- Three components on I2 C bus: temperature sensor, EEPROM and dual interface RF EEPROM +- RS-232 communication configurable for communication of Flash loader +- IrDA transceiver +- 240x320 TFT color LCD connected to SPI interface +- Joystick with 4-direction control and selector +- Reset, Wakeup or Tamper, and Key buttons +- 4 color user LEDs +- 2 LEDs for MCU power range indicator +- ECG, pressure sensor and PT100 temperature sensor connected to the 16-bit Sigma Delta ADC of STM32F373VCT6 +- Extension connectors for daughter board or wrapping board +- MCU voltage: 3.3 V or adjustable 2.0 V - 3.6 V +- USB FS connector +- Touch slider +- RTC with backup battery +- CAN 2.0 A/B compliant connection +- Light dependent resistor (LDR) +- Two HDMI connectors with DDC and CEC +- IR transmitter and receiver +- Two ADC & DAC input and output signal connectors and one Sigma Delta ADC input signal connector +- Potentiometer +- JTAG/SWD and ETM trace debug support +- Embedded ST-LINK/V2 + +More information about STM32F373VCT6 can be found here: + - `STM32F373VCT6 reference manual`_ + + +Supported Features +================== + +The Zephyr stm32373c_eval board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32373c_eval/stm32373c_eval_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/stm32373c_eval_connectors.jpg + :align: center + :alt: STM32373C_EVAL connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- USER_PB : PA2 +- LED2 : PC1 + +Programming and Debugging +************************* + +Applications for the ``stm32373c_eval`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32373C-EVAL board includes an ST-LINK/V2-1 embedded debug tool interface. +At power-on, the board is in firmware-upgrade mode (also called DFU for +"Device Firmware Upgrade"), allowing the firmware to be updated through the USB. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32373C-EVAL +----------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32373c_eval + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32373c_eval + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32373C-EVAL website: + https://www.st.com/en/evaluation-tools/stm32373c-eval.html + +.. _STM32F373VCT6 reference manual: + https://www.st.com/resource/en/reference_manual/dm00041563.pdf diff --git a/boards/arm/stm32373c_eval/stm32373c_eval.dts b/boards/st/stm32373c_eval/stm32373c_eval.dts similarity index 100% rename from boards/arm/stm32373c_eval/stm32373c_eval.dts rename to boards/st/stm32373c_eval/stm32373c_eval.dts diff --git a/boards/arm/stm32373c_eval/stm32373c_eval.yaml b/boards/st/stm32373c_eval/stm32373c_eval.yaml similarity index 100% rename from boards/arm/stm32373c_eval/stm32373c_eval.yaml rename to boards/st/stm32373c_eval/stm32373c_eval.yaml diff --git a/boards/arm/stm32373c_eval/stm32373c_eval_defconfig b/boards/st/stm32373c_eval/stm32373c_eval_defconfig similarity index 76% rename from boards/arm/stm32373c_eval/stm32373c_eval_defconfig rename to boards/st/stm32373c_eval/stm32373c_eval_defconfig index e61cabb061b..579a5c3fc4e 100644 --- a/boards/arm/stm32373c_eval/stm32373c_eval_defconfig +++ b/boards/st/stm32373c_eval/stm32373c_eval_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F3X=y - -# Platform Configuration -CONFIG_SOC_STM32F373XC=y - # Enable MPU CONFIG_ARM_MPU=y @@ -15,6 +9,7 @@ CONFIG_HW_STACK_PROTECTION=y # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y + # enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/stm32373c_eval/support/openocd.cfg b/boards/st/stm32373c_eval/support/openocd.cfg similarity index 100% rename from boards/arm/stm32373c_eval/support/openocd.cfg rename to boards/st/stm32373c_eval/support/openocd.cfg diff --git a/boards/st/stm32f072_eval/Kconfig.stm32f072_eval b/boards/st/stm32f072_eval/Kconfig.stm32f072_eval new file mode 100644 index 00000000000..b21c49de795 --- /dev/null +++ b/boards/st/stm32f072_eval/Kconfig.stm32f072_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2017 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F072_EVAL + select SOC_STM32F072XB diff --git a/boards/arm/stm32f072_eval/board.cmake b/boards/st/stm32f072_eval/board.cmake similarity index 100% rename from boards/arm/stm32f072_eval/board.cmake rename to boards/st/stm32f072_eval/board.cmake diff --git a/boards/st/stm32f072_eval/board.yml b/boards/st/stm32f072_eval/board.yml new file mode 100644 index 00000000000..43e4ec82854 --- /dev/null +++ b/boards/st/stm32f072_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f072_eval + vendor: st + socs: + - name: stm32f072xb diff --git a/boards/arm/stm32f072_eval/doc/img/stm32f072_eval.jpg b/boards/st/stm32f072_eval/doc/img/stm32f072_eval.jpg similarity index 100% rename from boards/arm/stm32f072_eval/doc/img/stm32f072_eval.jpg rename to boards/st/stm32f072_eval/doc/img/stm32f072_eval.jpg diff --git a/boards/st/stm32f072_eval/doc/index.rst b/boards/st/stm32f072_eval/doc/index.rst new file mode 100644 index 00000000000..998670d4cf2 --- /dev/null +++ b/boards/st/stm32f072_eval/doc/index.rst @@ -0,0 +1,184 @@ +.. _stm32f072_eval_board: + +ST STM32F072 Evaluation +####################### + +Overview +******** + +The STM32F072-EVAL Discovery kit features an ARM Cortex-M0 based STM32F072VBT6 MCU +with a wide range of connectivity support and configurations. +Here are some highlights of the STM32F072-EVAL board: + +- Four 5 V power supply options: power jack, ST-LINK/V2 USB connector, user USB connector, or daughter board +- Stereo audio jack, which supports a headset with microphone connected to DAC and ADC of STM32F072VBT6. +- 2G Byte (or more) SPI interface MicroSD card +- I2C compatible serial interface temperature sensor +- RF E2PROM +- RS232 and RS485 communication +- IrDA transceiver +- IR LED and IR receiver +- SWD debug support, ST-LINK/V2 embedded +- 240x320 TFT color LCD connected to SPI interface of STM32F072VBT6 +- Joystick with 4-direction control and selector +- Reset and tamper buttons +- Four color user LEDs and two LEDs as MCU low power alarm +- Extension connector for daughter board or wrapping board +- MCU voltage choice: fixed 3.3 V or adjustable from 1.65 V to 3.6 V +- USB full-speed connector +- Touch sensing buttons +- RTC with backup battery +- CAN2.0A/B compliant connector +- Light Dependent Resistor (LDR) +- Potentiometer +- Two HDMI connectors with DDC and CEC +- Smart Card slot +- Motor control connector + + +.. image:: img/stm32f072_eval.jpg + :align: center + :alt: STM32F072-EVAL + +Hardware +******** + +STM32F072-EVAL Discovery kit provides the following hardware components: + +- STM32F072VBT6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg| -M0 CPU +- 48 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 128 KB Flash +- 16 KB SRAM with HW parity +- GPIO with external interrupt capability +- one 12-bit ADC with 16 channels +- one 12-bit D/A converters with 2 channels +- RTC +- Advanced-control Timer +- General Purpose Timers (8) +- Watchdog Timers (2) +- USART (4) +- I2C (2) +- SPI (2) +- CAN +- USB 2.0 OTG FS with on-chip PHY +- CRC calculation unit +- DMA Controller +- HDMI CEC Controller +- 24 capacitive sensing channels for touchkey, linear, and rotary touch sensors +- Up to 87 fast I/Os: 68 I/Os with 5V tolerant capability and 19 with independent supply + +More information about STM32F072VB can be found here: + - `STM32F072VB on www.st.com`_ + - `STM32F072 reference manual`_ + +Supported Features +================== + +The Zephyr stm32f072_eval board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f072_eval/stm32f072_eval_defconfig` + + +Pin Mapping +=========== + +STM32F072-EVAL Discovery kit has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to STM32F072-EVAL board User Manual. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- TAMPER_PB : PC13 +- JOYSTICK_RIGHT_PB : PE3 +- JOYSTICK_LEFT_PB : PF2 +- JOYSTICK_UP_PB : PF9 +- JOYSTICK_DOWN_PB : PF10 +- JOYSTICK_SEL_PB : PA0 +- LD1 : PD8 +- LD2 : PD9 +- LD3 : PD10 +- LD4 : PD11 + +System Clock +============ + +STM32F072-EVAL System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 48MHz, +driven by an 8MHz high speed internal clock. + +Serial Port +=========== + +STM32F072-EVAL Discovery kit has up to 4 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f072_eval`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F072-EVAL Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32F072-EVAL +------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f072_eval + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f072_eval + :maybe-skip-config: + :goals: debug + + +.. _STM32F072VB on www.st.com: + https://www.st.com/en/microcontrollers/stm32f072vb.html + +.. _STM32F072 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936.pdf diff --git a/boards/arm/stm32f072_eval/stm32f072_eval.dts b/boards/st/stm32f072_eval/stm32f072_eval.dts similarity index 100% rename from boards/arm/stm32f072_eval/stm32f072_eval.dts rename to boards/st/stm32f072_eval/stm32f072_eval.dts diff --git a/boards/arm/stm32f072_eval/stm32f072_eval.yaml b/boards/st/stm32f072_eval/stm32f072_eval.yaml similarity index 100% rename from boards/arm/stm32f072_eval/stm32f072_eval.yaml rename to boards/st/stm32f072_eval/stm32f072_eval.yaml diff --git a/boards/st/stm32f072_eval/stm32f072_eval_defconfig b/boards/st/stm32f072_eval/stm32f072_eval_defconfig new file mode 100644 index 00000000000..06e8a32bb1f --- /dev/null +++ b/boards/st/stm32f072_eval/stm32f072_eval_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm32f072_eval/support/openocd.cfg b/boards/st/stm32f072_eval/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f072_eval/support/openocd.cfg rename to boards/st/stm32f072_eval/support/openocd.cfg diff --git a/boards/st/stm32f072b_disco/Kconfig.defconfig b/boards/st/stm32f072b_disco/Kconfig.defconfig new file mode 100644 index 00000000000..06d17064665 --- /dev/null +++ b/boards/st/stm32f072b_disco/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32F072B-DISCO board configuration + +# Copyright (c) 2017 Clage GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F072B_DISCO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_STM32F072B_DISCO diff --git a/boards/st/stm32f072b_disco/Kconfig.stm32f072b_disco b/boards/st/stm32f072b_disco/Kconfig.stm32f072b_disco new file mode 100644 index 00000000000..817caf5d7c4 --- /dev/null +++ b/boards/st/stm32f072b_disco/Kconfig.stm32f072b_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Clage GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F072B_DISCO + select SOC_STM32F072XB diff --git a/boards/arm/stm32f072b_disco/board.cmake b/boards/st/stm32f072b_disco/board.cmake similarity index 100% rename from boards/arm/stm32f072b_disco/board.cmake rename to boards/st/stm32f072b_disco/board.cmake diff --git a/boards/st/stm32f072b_disco/board.yml b/boards/st/stm32f072b_disco/board.yml new file mode 100644 index 00000000000..ca3e636655f --- /dev/null +++ b/boards/st/stm32f072b_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f072b_disco + vendor: st + socs: + - name: stm32f072xb diff --git a/boards/arm/stm32f072b_disco/doc/img/stm32f072b_disco.jpg b/boards/st/stm32f072b_disco/doc/img/stm32f072b_disco.jpg similarity index 100% rename from boards/arm/stm32f072b_disco/doc/img/stm32f072b_disco.jpg rename to boards/st/stm32f072b_disco/doc/img/stm32f072b_disco.jpg diff --git a/boards/st/stm32f072b_disco/doc/index.rst b/boards/st/stm32f072b_disco/doc/index.rst new file mode 100644 index 00000000000..d09a8fc47df --- /dev/null +++ b/boards/st/stm32f072b_disco/doc/index.rst @@ -0,0 +1,218 @@ +.. _stm32f072b_disco_board: + +ST STM32F072B Discovery +####################### + +Overview +******** + +The STM32F072B-DISCO Discovery kit features an ARM Cortex-M0 based STM32F072RB +MCU with everything required for beginners and experienced users to get +started quickly. Here are some highlights of the STM32F072B-DISCO board: + +- STM32 microcontroller in LQFP64 package +- Extension header for LQFP64 I/Os for a quick connection to the prototyping + board and easy probing +- On-board ST-LINK/V2, debugger/programmer with SWD connector +- Board power supply: through USB bus or from an external 5 V supply voltage +- External application power supply: 3 V and 5 V + +- Six LEDs: + + - LD1 (red/green) for USB communication + - LD2 (red) for 3.3 V power on + - Four user LEDs: LD3 (orange), LD4 (green), LD5 (red) and LD6 (blue) + +- Two push-buttons: USER and RESET +- USB USER with Mini-B connector +- L3GD20, ST MEMS motion sensor, 3-axis digital output gyroscope +- One linear touch sensor or four touch keys +- RF EEprom daughter board connector + +.. image:: img/stm32f072b_disco.jpg + :align: center + :alt: STM32F072B-DISCO + +More information about the board can be found at the +`STM32F072B-DISCO website`_. + +Hardware +******** + +STM32F072B-DISCO Discovery kit provides the following hardware components: + +- STM32F072RBTT6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg| -M0 CPU +- 48 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 128 KB Flash +- 16 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 39 channels +- 12-bit D/A converters +- RTC +- General Purpose Timers (12) +- USART/UART (4) +- I2C (2) +- SPI (2) +- CAN +- USB 2.0 full speed interface +- DMA Controller +- 24 capacitive sensing channels for touchkey, linear and rotary touch sensors + +More information about STM32F072RB can be found here: + - `STM32F072RB on www.st.com`_ + - `STM32F072xB reference manual`_ + +Supported Features +================== + +The Zephyr stm32f072b_disco board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | SPI controller | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_. + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f072b_disco/stm32f072b_disco_defconfig` + + +Pin Mapping +=========== + +STM32F072B-DISCO Discovery kit has 6 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `STM32F072B-DISCO board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- I2C1_SCL : PB8 +- I2C1_SDA : PB9 +- I2C2_SCL : PB10 +- I2C2_SDA : PB11 +- SPI1_SCK : PB3 +- SPI1_MISO : PB4 +- SPI1_MOSI : PB5 +- USER_PB : PA0 +- LD3 : PC6 +- LD4 : PC8 +- LD5 : PC9 +- LD6 : PC7 +- CAN_RX : PB8 +- CAN_TX : PB9 + +System Clock +============ + +STM32F072B-DISCO System Clock could be driven by internal or external +oscillator, as well as main PLL clock. By default System clock is driven +by PLL clock at 72 MHz, driven by internal 8 MHz oscillator. + +Serial Port +=========== + +STM32F072B-DISCO Discovery kit has up to 4 UARTs. The Zephyr console output +is assigned to UART 1. Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f072b_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F072B-DISCO board includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + + +Flashing an application to STM32F072B-DISCO +------------------------------------------- + +First, connect the STM32F072B-DISCO Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f072b_disco + :goals: build flash + +Run a serial host program to connect with your board. A TTL(3.3V) serial +adapter is required. + +.. code-block:: console + + $ minicom -D /dev/ + +Replace with the port where the serial adapter can be found. +For example, under Linux, /dev/ttyUSB0. + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f072b_disco + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32F072B-DISCO website: + https://www.st.com/en/evaluation-tools/32f072bdiscovery.html + + +.. _STM32F072B-DISCO board User Manual: + https://www.st.com/resource/en/user_manual/dm00099401.pdf + +.. _STM32F072RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32f072rb.html + +.. _STM32F072xB reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936.pdf + +.. _SK Pang CAN breakout board: + https://www.skpang.co.uk/products/can-bus-can-fd-breakout-board-5v-supply-and-5v-logic diff --git a/boards/arm/stm32f072b_disco/stm32f072b_disco.dts b/boards/st/stm32f072b_disco/stm32f072b_disco.dts similarity index 100% rename from boards/arm/stm32f072b_disco/stm32f072b_disco.dts rename to boards/st/stm32f072b_disco/stm32f072b_disco.dts diff --git a/boards/arm/stm32f072b_disco/stm32f072b_disco.yaml b/boards/st/stm32f072b_disco/stm32f072b_disco.yaml similarity index 100% rename from boards/arm/stm32f072b_disco/stm32f072b_disco.yaml rename to boards/st/stm32f072b_disco/stm32f072b_disco.yaml diff --git a/boards/st/stm32f072b_disco/stm32f072b_disco_defconfig b/boards/st/stm32f072b_disco/stm32f072b_disco_defconfig new file mode 100644 index 00000000000..06e8a32bb1f --- /dev/null +++ b/boards/st/stm32f072b_disco/stm32f072b_disco_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm32f072b_disco/support/openocd.cfg b/boards/st/stm32f072b_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f072b_disco/support/openocd.cfg rename to boards/st/stm32f072b_disco/support/openocd.cfg diff --git a/boards/st/stm32f0_disco/Kconfig.stm32f0_disco b/boards/st/stm32f0_disco/Kconfig.stm32f0_disco new file mode 100644 index 00000000000..f3ae1b01772 --- /dev/null +++ b/boards/st/stm32f0_disco/Kconfig.stm32f0_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Nathan Tsoi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F0_DISCO + select SOC_STM32F051X8 diff --git a/boards/arm/stm32f0_disco/board.cmake b/boards/st/stm32f0_disco/board.cmake similarity index 100% rename from boards/arm/stm32f0_disco/board.cmake rename to boards/st/stm32f0_disco/board.cmake diff --git a/boards/st/stm32f0_disco/board.yml b/boards/st/stm32f0_disco/board.yml new file mode 100644 index 00000000000..a195ae98ae7 --- /dev/null +++ b/boards/st/stm32f0_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f0_disco + vendor: st + socs: + - name: stm32f051x8 diff --git a/boards/arm/stm32f0_disco/doc/img/stm32f0_disco.jpg b/boards/st/stm32f0_disco/doc/img/stm32f0_disco.jpg similarity index 100% rename from boards/arm/stm32f0_disco/doc/img/stm32f0_disco.jpg rename to boards/st/stm32f0_disco/doc/img/stm32f0_disco.jpg diff --git a/boards/st/stm32f0_disco/doc/index.rst b/boards/st/stm32f0_disco/doc/index.rst new file mode 100644 index 00000000000..3947600d837 --- /dev/null +++ b/boards/st/stm32f0_disco/doc/index.rst @@ -0,0 +1,143 @@ +.. _stm32f0_disco_board: + +ST STM32F0 Discovery +#################### + +Overview +******** + +The STM32F0 Discovery development board uses an STM32F051R8T6 MCU and +integrates the ST-LINK/V2-1 debugger and programmer. It also comes with a +comprehensive STM32 software HAL library and various packaged software +examples. + +.. image:: img/stm32f0_disco.jpg + :align: center + :alt: STM32F0DISCOVERY + +More information about the board can be found at the `STM32F0DISCOVERY website`_. + +Hardware +******** + +The STM32 Discovery board features: + +- STM32F051R8T6 microcontroller featuring 64 KB Flash memory, 8 KB RAM in an + LQFP64 package +- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone + ST-LINK/V2 (with SWD connector for programming and debugging) +- Board power supply: through USB bus or from an external 5 V supply voltage +- External application power supply: 3 V and 5 V +- Four LEDs: + + - LD1 (red) for 3.3 V power on + - LD2 (red/green) for USB communication + - LD3 (green) for PC9 output + - LD4 (blue) for PC8 output +- Two push buttons (user and reset) +- Extension header for all LQFP64 I/Os for quick connection to prototyping board + and easy probing +- An additional board is provided which can be connected to the extension + connector for even easier prototyping and probing. +- Comprehensive free software including a variety of examples, part of + STM32CubeF0 package or STSW-STM32049 for legacy Standard Libraries usage + +More information about STM32F051R8 can be found in the `STM32F0x8 reference manual`_. + +Supported Features +================== + +The Zephyr stm32f0_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f0_disco/stm32f0_disco_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 + +For more details please refer to `STM32F0DISCOVERY board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``stm32f0_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F0DISCOVERY board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F030R8 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f0_disco + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f0_disco + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32F0DISCOVERY website: + https://www.st.com/en/evaluation-tools/stm32f0discovery.html + +.. _STM32F0x8 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936.pdf + +.. _STM32F0DISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00050135.pdf diff --git a/boards/arm/stm32f0_disco/stm32f0_disco.dts b/boards/st/stm32f0_disco/stm32f0_disco.dts similarity index 100% rename from boards/arm/stm32f0_disco/stm32f0_disco.dts rename to boards/st/stm32f0_disco/stm32f0_disco.dts diff --git a/boards/arm/stm32f0_disco/stm32f0_disco.yaml b/boards/st/stm32f0_disco/stm32f0_disco.yaml similarity index 100% rename from boards/arm/stm32f0_disco/stm32f0_disco.yaml rename to boards/st/stm32f0_disco/stm32f0_disco.yaml diff --git a/boards/arm/stm32f0_disco/stm32f0_disco_defconfig b/boards/st/stm32f0_disco/stm32f0_disco_defconfig similarity index 80% rename from boards/arm/stm32f0_disco/stm32f0_disco_defconfig rename to boards/st/stm32f0_disco/stm32f0_disco_defconfig index f1fd239fa3b..18ac599df25 100644 --- a/boards/arm/stm32f0_disco/stm32f0_disco_defconfig +++ b/boards/st/stm32f0_disco/stm32f0_disco_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F051X8=y - # Kernel Options due to Low Memory (8k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/arm/stm32f0_disco/support/openocd.cfg b/boards/st/stm32f0_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f0_disco/support/openocd.cfg rename to boards/st/stm32f0_disco/support/openocd.cfg diff --git a/boards/st/stm32f103_mini/Kconfig.stm32f103_mini b/boards/st/stm32f103_mini/Kconfig.stm32f103_mini new file mode 100644 index 00000000000..7a9d990870b --- /dev/null +++ b/boards/st/stm32f103_mini/Kconfig.stm32f103_mini @@ -0,0 +1,5 @@ +# Copyright (c) 2020 WuhanStudio +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F103_MINI + select SOC_STM32F103XE diff --git a/boards/arm/stm32f103_mini/board.cmake b/boards/st/stm32f103_mini/board.cmake similarity index 100% rename from boards/arm/stm32f103_mini/board.cmake rename to boards/st/stm32f103_mini/board.cmake diff --git a/boards/st/stm32f103_mini/board.yml b/boards/st/stm32f103_mini/board.yml new file mode 100644 index 00000000000..4ea8f6fbb2d --- /dev/null +++ b/boards/st/stm32f103_mini/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f103_mini + vendor: st + socs: + - name: stm32f103xe diff --git a/boards/arm/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg b/boards/st/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg similarity index 100% rename from boards/arm/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg rename to boards/st/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg diff --git a/boards/arm/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg b/boards/st/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg similarity index 100% rename from boards/arm/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg rename to boards/st/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg diff --git a/boards/arm/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg b/boards/st/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg similarity index 100% rename from boards/arm/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg rename to boards/st/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg diff --git a/boards/st/stm32f103_mini/doc/index.rst b/boards/st/stm32f103_mini/doc/index.rst new file mode 100644 index 00000000000..63d2199e4d0 --- /dev/null +++ b/boards/st/stm32f103_mini/doc/index.rst @@ -0,0 +1,166 @@ +.. _stm32f103_mini_board: + +STM32F103 Mini +################ + +Overview +******** + +The STM32F103_MINI board features an ARM Cortex-M3 based STM32F103RC MCU +with a wide range of connectivity support and configurations. There are +multiple version of this board like ``stm32f103_mini``. + +.. image:: img/stm32f103_mini_yellow.jpg + :align: center + :alt: STM32F103 Mini Yellow + +.. image:: img/stm32f103_mini_blue.jpg + :align: center + :alt: STM32F103 Mini Blue + +Hardware +******** +STM32F103 Mini provides the following hardware components: + +- STM32 microcontroller in QFP64 package + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Two LEDs: + + - User LED (LD1), power LED (LD2) + +- USB re-enumeration capability: + + - Mass storage + +More information about STM32F103RC can be found here: + +- `STM32F103 reference manual`_ +- `STM32F103 data sheet`_ + +Supported Features +================== + +The Zephyr stm32f103_mini board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f103_mini/stm32f103_mini_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/stm32f103_mini_pin.jpg + :align: center + :alt: Nucleo F103RB connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX: PA9/PA10 +- UART_2 TX/RX: PA2/PA3 (ST-Link Virtual COM Port) +- SPI1 NSS/SCK/MISO/MOSI: PA4/PA5/PA6/PA7 +- SPI2 NSS/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 +- I2C1 SDA/SCL: PB9/PB8 +- PWM1_CH1: PA8 +- USER_PB: PC13 +- LD1: PA5 +- USB_DC DM/DP: PA11/PA12 + +System Clock +------------ + +The on-board 8MHz crystal is used to produce a 72MHz system clock with PLL. + +Programming and Debugging +************************* + +Applications for the ``stm32f103_mini`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +There are 2 main entry points for flashing STM32F1X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware such as ST-Link). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. + +Flashing an application to stm32f103 mini +----------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f103_mini + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f103_mini + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32F103 reference manual: + https://www.st.com/resource/en/reference_manual/cd00171190.pdf + +.. _STM32F103 data sheet: + https://www.st.com/resource/en/datasheet/stm32f103rc.pdf diff --git a/boards/arm/stm32f103_mini/stm32f103_mini.dts b/boards/st/stm32f103_mini/stm32f103_mini.dts similarity index 100% rename from boards/arm/stm32f103_mini/stm32f103_mini.dts rename to boards/st/stm32f103_mini/stm32f103_mini.dts diff --git a/boards/arm/stm32f103_mini/stm32f103_mini.yaml b/boards/st/stm32f103_mini/stm32f103_mini.yaml similarity index 100% rename from boards/arm/stm32f103_mini/stm32f103_mini.yaml rename to boards/st/stm32f103_mini/stm32f103_mini.yaml diff --git a/boards/arm/stm32f103_mini/stm32f103_mini_defconfig b/boards/st/stm32f103_mini/stm32f103_mini_defconfig similarity index 81% rename from boards/arm/stm32f103_mini/stm32f103_mini_defconfig rename to boards/st/stm32f103_mini/stm32f103_mini_defconfig index 765fc062bd7..9fd4400ac20 100644 --- a/boards/arm/stm32f103_mini/stm32f103_mini_defconfig +++ b/boards/st/stm32f103_mini/stm32f103_mini_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103XE=y - # enable uart driver CONFIG_SERIAL=y # enable console diff --git a/boards/arm/stm32f103_mini/support/openocd.cfg b/boards/st/stm32f103_mini/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f103_mini/support/openocd.cfg rename to boards/st/stm32f103_mini/support/openocd.cfg diff --git a/boards/st/stm32f3_disco/Kconfig.stm32f3_disco b/boards/st/stm32f3_disco/Kconfig.stm32f3_disco new file mode 100644 index 00000000000..0bddbf55719 --- /dev/null +++ b/boards/st/stm32f3_disco/Kconfig.stm32f3_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2017 I-SENSE group of ICCS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F3_DISCO + select SOC_STM32F303XC diff --git a/boards/arm/stm32f3_disco/board.cmake b/boards/st/stm32f3_disco/board.cmake similarity index 100% rename from boards/arm/stm32f3_disco/board.cmake rename to boards/st/stm32f3_disco/board.cmake diff --git a/boards/st/stm32f3_disco/board.yml b/boards/st/stm32f3_disco/board.yml new file mode 100644 index 00000000000..ae48f138fa5 --- /dev/null +++ b/boards/st/stm32f3_disco/board.yml @@ -0,0 +1,11 @@ +board: + name: stm32f3_disco + vendor: st + revision: + format: letter + default: "B" + revisions: + - name: "B" + - name: "E" + socs: + - name: stm32f303xc diff --git a/boards/arm/stm32f3_disco/doc/img/stm32f3_disco.jpg b/boards/st/stm32f3_disco/doc/img/stm32f3_disco.jpg similarity index 100% rename from boards/arm/stm32f3_disco/doc/img/stm32f3_disco.jpg rename to boards/st/stm32f3_disco/doc/img/stm32f3_disco.jpg diff --git a/boards/st/stm32f3_disco/doc/index.rst b/boards/st/stm32f3_disco/doc/index.rst new file mode 100644 index 00000000000..8862d754fbb --- /dev/null +++ b/boards/st/stm32f3_disco/doc/index.rst @@ -0,0 +1,280 @@ +.. _stm32f3_disco_board: + +ST STM32F3 Discovery +#################### + +Overview +******** + +The STM32F3DISCOVERY Discovery kit features an ARM Cortex-M4 based STM32F303VC +MCU with everything required for beginners and experienced users to get +started quickly. Here are some highlights of the STM32F3DISCOVERY board: + +- STM32 microcontroller in LQFP100 package +- Extension header for all LQFP100 I/Os for quick connection to prototyping + board and easy probing +- On-board, ST-LINK/V2 for PCB version A or B or ST-LINK/V2-B for PCB version + C and newer, debugger/programmer with SWD connector +- Board power supply: through USB bus or from an external 3 V or 5 V supply + voltage +- External application power supply: 3 V and 5 V + +- Ten LEDs: + + - 3.3 V power on (LD1) + - USB communication (LD2) + - Eight user LEDs: red (LD3/LD10), blue (LD4/LD9), orange (LD5/LD9) + and green (LD6/LD7) + +- Two push-buttons: USER and RESET +- USB USER with Mini-B connector +- L3GD20 or I3G4250D, ST MEMS motion sensor, 3-axis digital output gyroscope +- LSM303DLHC or LSM303AGR, ST MEMS system-in-package featuring a 3D digital linear + acceleration sensor and a 3D digital magnetic sensor; + +.. HINT:: + Recent PCB revisions (E and newer) are shipped with I3G4250D and LSM303AGR. + +.. image:: img/stm32f3_disco.jpg + :align: center + :alt: STM32F3DISCOVERY + +More information about the board can be found at the +`STM32F3DISCOVERY website`_. + +Hardware +******** + +STM32F3DISCOVERY Discovery kit provides the following hardware components: + +- STM32F303VCT6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 72 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 256 KB Flash +- 40 KB SRAM +- Routine booster: 8 Kbytes of SRAM on instruction and data bus +- GPIO with external interrupt capability +- 4x12-bit ADC with 39 channels +- 2x12-bit D/A converters +- RTC +- General Purpose Timers (13) +- USART/UART (5) +- I2C (2) +- SPI (3) +- CAN +- USB 2.0 full speed interface +- Infrared transmitter +- DMA Controller + +More information about STM32F303VC can be found here: + - `STM32F303VC on www.st.com`_ + - `STM32F303xC reference manual`_ + +Supported Features +================== + +The Zephyr stm32f3_disco board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN | ++-----------+------------+-------------------------------------+ +| IWDG | on-chip | Independent WatchDoG | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f3_disco/stm32f3_disco_defconfig` + + +Pin Mapping +=========== + +STM32F3DISCOVERY Discovery kit has 6 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `STM32F3DISCOVERY board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PC4 +- UART_1_RX : PC5 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- UART_4_TX : PC10 +- UART_4_RX : PC11 +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PA9 +- I2C2_SDA : PA10 +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 +- CAN1_RX : PD0 +- CAN1_TX : PD1 +- USB_DM : PA11 +- USB_DP : PA12 +- USER_PB : PA0 +- LD3 : PE9 +- LD4 : PE8 +- LD5 : PE10 +- LD6 : PE15 +- LD7 : PE11 +- LD8 : PE14 +- LD9 : PE12 +- LD10 : PE13 +- PWM : PA8 +- ADC1 : PA0 +- DAC1 : PA4 + +System Clock +============ + +STM32F3DISCOVERY System Clock could be driven by internal or external +oscillator, as well as main PLL clock. By default System clock is driven +by PLL clock at 72 MHz, driven by 8 MHz MCO from the ST Link. + +Serial Port +=========== + +STM32F3DISCOVERY Discovery kit has up to 5 UARTs. The Zephyr console output +is assigned to UART1. Default settings are 115200 8N1. + +I2C +=== + +STM32F3DISCOVERY has up to 2 I2Cs. I2C1 is connected to the LSM303DLHC and is +an ultra-compact low-power system-in-package featuring a 3D digital linear +acceleration sensor and a 3D digital magnetic sensor. + +USB +=== +STM32F3DISCOVERY has a USB 2.0 full-speed device interface available through +its mini USB connector (USB USER). + +CAN +=== +The STM32F3DISCOVERY does not have an onboard CAN transceiver. In +order to use the CAN bus on the this board, an external CAN bus +transceiver must be connected to ``PD0`` (``CAN1_RX``) and ``PD1`` +(``CAN1_TX``). + +Programming and Debugging +************************* + +Flashing +======== + +STM32F3DISCOVERY Discovery kit includes a ST-LINK/V2 or ST-LINK/V2-B embedded +debug tool interface. + +Applications for the ``stm32f3_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing an application to STM32F3DISCOVERY +------------------------------------------- + +First, connect the STM32F3DISCOVERY Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f3_disco + :goals: build flash + + +In case you are using a recent PCB revision (E or newer), you have to use an +adapted board definition: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f3_disco@E + :goals: build flash + +Run a serial host program to connect with your board. For PCB version A or B a +TTL(3.3V) serial adapter is required. For PCB version C and newer a Virtual Com +Port (VCP) is available on the USB ST-LINK port. + +.. code-block:: console + + $ minicom -D /dev/ + +Replace with the port where the STM32F3DISCOVERY board can be +found. For example, under Linux, /dev/ttyUSB0. + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f3_disco + :goals: debug + +Again you have to use the adapted command for newer PCB revisions (E and newer): + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f3_disco@E + :goals: debug + +.. _STM32F3DISCOVERY website: + https://www.st.com/en/evaluation-tools/stm32f3discovery.html + +.. _STM32F3DISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00063382.pdf + +.. _STM32F303VC on www.st.com: + https://www.st.com/en/microcontrollers/stm32f303vc.html + +.. _STM32F303xC reference manual: + https://www.st.com/resource/en/reference_manual/dm00043574.pdf diff --git a/boards/arm/stm32f3_disco/stm32f3_disco.dts b/boards/st/stm32f3_disco/stm32f3_disco.dts similarity index 100% rename from boards/arm/stm32f3_disco/stm32f3_disco.dts rename to boards/st/stm32f3_disco/stm32f3_disco.dts diff --git a/boards/st/stm32f3_disco/stm32f3_disco_B.yaml b/boards/st/stm32f3_disco/stm32f3_disco_B.yaml new file mode 100644 index 00000000000..1c87cb7fd36 --- /dev/null +++ b/boards/st/stm32f3_disco/stm32f3_disco_B.yaml @@ -0,0 +1,24 @@ +identifier: stm32f3_disco +name: ST STM32F3 Discovery rev B +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 40 +supported: + - gpio + - i2c + - counter + - spi + - watchdog + - usb_device + - lsm303dlhc + - nvs + - can + - pwm + - adc + - dac + - dma +vendor: st diff --git a/boards/arm/stm32f3_disco/stm32f3_disco_defconfig b/boards/st/stm32f3_disco/stm32f3_disco_defconfig similarity index 85% rename from boards/arm/stm32f3_disco/stm32f3_disco_defconfig rename to boards/st/stm32f3_disco/stm32f3_disco_defconfig index fae0909e840..ed90d066c5a 100644 --- a/boards/arm/stm32f3_disco/stm32f3_disco_defconfig +++ b/boards/st/stm32f3_disco/stm32f3_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F3X=y -CONFIG_SOC_STM32F303XC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f3_disco/stm32f3_disco_E.overlay b/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.overlay similarity index 100% rename from boards/arm/stm32f3_disco/stm32f3_disco_E.overlay rename to boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.overlay diff --git a/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml b/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml new file mode 100644 index 00000000000..13e6b0bf143 --- /dev/null +++ b/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml @@ -0,0 +1,23 @@ +identifier: stm32f3_disco@E +name: ST STM32F3 Discovery rev E +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 40 +supported: + - gpio + - i2c + - counter + - spi + - watchdog + - usb_device + - i3g4250d + - nvs + - can + - pwm + - adc + - dac +vendor: st diff --git a/boards/arm/stm32f3_disco/support/openocd.cfg b/boards/st/stm32f3_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f3_disco/support/openocd.cfg rename to boards/st/stm32f3_disco/support/openocd.cfg diff --git a/boards/st/stm32f411e_disco/Kconfig.stm32f411e_disco b/boards/st/stm32f411e_disco/Kconfig.stm32f411e_disco new file mode 100644 index 00000000000..8ef325c580b --- /dev/null +++ b/boards/st/stm32f411e_disco/Kconfig.stm32f411e_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Fenix Engineering Solutions +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F411E_DISCO + select SOC_STM32F411XE diff --git a/boards/arm/stm32f411e_disco/board.cmake b/boards/st/stm32f411e_disco/board.cmake similarity index 100% rename from boards/arm/stm32f411e_disco/board.cmake rename to boards/st/stm32f411e_disco/board.cmake diff --git a/boards/st/stm32f411e_disco/board.yml b/boards/st/stm32f411e_disco/board.yml new file mode 100644 index 00000000000..f42b1ada4a4 --- /dev/null +++ b/boards/st/stm32f411e_disco/board.yml @@ -0,0 +1,11 @@ +board: + name: stm32f411e_disco + vendor: st + revision: + format: letter + default: "D" + revisions: + - name: "B" + - name: "D" + socs: + - name: stm32f411xe diff --git a/boards/arm/stm32f411e_disco/doc/img/stm32f411e_disco.jpg b/boards/st/stm32f411e_disco/doc/img/stm32f411e_disco.jpg similarity index 100% rename from boards/arm/stm32f411e_disco/doc/img/stm32f411e_disco.jpg rename to boards/st/stm32f411e_disco/doc/img/stm32f411e_disco.jpg diff --git a/boards/st/stm32f411e_disco/doc/index.rst b/boards/st/stm32f411e_disco/doc/index.rst new file mode 100644 index 00000000000..a2e6f02619b --- /dev/null +++ b/boards/st/stm32f411e_disco/doc/index.rst @@ -0,0 +1,188 @@ +.. _stm32f411e_disco_board: + +ST STM32F411E Discovery +####################### + +Overview +******** + +The STM32F411E Discovery kit features an ARM Cortex-M4 based STM32F411VE MCU +with a wide range of connectivity support and configurations. +Here are some highlights of the STM32F411E-DISCO board: + +- STM32F411VET6 microcontroller featuring 512 KB of Flash memory, 128 KB of RAM in an LQFP100 package +- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone STLINK/V2 (with SWD connector for programming and debugging) +- Board power supply: through USB bus or from an external 5 V supply voltage +- External application power supply: 3 V and 5 V +- L3GD20(rev B) or I3G4250D(rev D): ST MEMS motion sensor, 3-axis digital output gyroscope. +- LSM303DLHC(rev B) or LSM303AGR(rev D): ST MEMS system-in-package featuring a 3D digital linear acceleration sensor and a 3D digital magnetic sensor. +- MP45DT02(rev B) or IMP34DT05(rev D), ST MEMS audio sensor, omnidirectional digital microphone +- CS43L22, audio DAC with integrated class D speaker driver +- Eight LEDs: + - LD1 (red/green) for USB communication + - LD2 (red) for 3.3 V power on + - Four user LEDs: + LD3 (orange), LD4 (green), LD5 (red) and LD6 (blue) + - Two USB OTG LEDs: + LD7 (green) VBus and LD8 (red) over-current +- Two pushbuttons (user and reset) +- USB OTG with micro-AB connector +- Extension header for LQFP100 I/Os for a quick connection to the prototyping board and an easy probing + +.. image:: img/stm32f411e_disco.jpg + :align: center + :alt: STM32F411E-DISCO + +More information about the board can be found at the `32F411EDISCOVERY website`_. + +Hardware +******** + +STM32F411E-DISCO Discovery kit provides the following hardware components: + +- STM32F411VET6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 128 KB SRAM +- GPIO with external interrupt capability +- 1x12-bit, 2.4 MSPS ADC with 16 channels +- DMA Controller +- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (3) +- I2C (3) +- SPI/I2S (5) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- CRC calculation unit +- 96-bit unique ID +- RTC + +More information about STM32F411VE can be found here: + - `STM32F411VE website`_ + - `STM32F411x reference manual`_ + +Supported Features +================== + +The Zephyr stm32f411e_disco board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f411e_disco/stm32f411e_disco_defconfig` + + +Pin Mapping +=========== + +STM32F411E-DISCO Discovery kit has 5 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `32F411EDISCOVERY board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- LD3 : PD13 (PWM4 CH2) +- LD4 : PD12 (PWM4 CH1) +- LD5 : PD14 (PWM4 CH3) +- LD6 : PD15 (PWM4 CH4) + +System Clock +============ + +STM32F411E-DISCO System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 100MHz, driven by the internal oscillator. + +Serial Port +=========== + +The STM32F411G Discovery kit has up to 3 UARTs. The Zephyr console output is +assigned to UART2. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``stm32f411e_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F411E-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool +interface. This interface is supported by the openocd version included in +Zephyr SDK. + +Flashing an application to STM32F411E-DISCO +------------------------------------------- + +Connect the STM32F411E-DISCO Discovery kit to your host computer using the +USB port. Then build and flash an application. + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f411e_disco + :goals: build flash + +In case you are using PCB revision B, you have to use an +adapted board definition as the default PCB rev here is D: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f411e_disco@B + :goals: build flash + +You should see the orange led (LD3) blinking every second. + +Debugging +========= + +You can debug applications in the usual way. Here is an example for +the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f411e_disco + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _32F411EDISCOVERY website: + https://www.st.com/en/evaluation-tools/32f411ediscovery.html + +.. _32F411EDISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00148985.pdf + +.. _STM32F411VE website: + https://www.st.com/en/microcontrollers/stm32f411ve.html + +.. _STM32F411x reference manual: + https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco.dts b/boards/st/stm32f411e_disco/stm32f411e_disco.dts similarity index 100% rename from boards/arm/stm32f411e_disco/stm32f411e_disco.dts rename to boards/st/stm32f411e_disco/stm32f411e_disco.dts diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco_defconfig b/boards/st/stm32f411e_disco/stm32f411e_disco_defconfig similarity index 86% rename from boards/arm/stm32f411e_disco/stm32f411e_disco_defconfig rename to boards/st/stm32f411e_disco/stm32f411e_disco_defconfig index 30784f3514d..67896885dac 100644 --- a/boards/arm/stm32f411e_disco/stm32f411e_disco_defconfig +++ b/boards/st/stm32f411e_disco/stm32f411e_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F411XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco_B.overlay b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay similarity index 100% rename from boards/arm/stm32f411e_disco/stm32f411e_disco_B.overlay rename to boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay diff --git a/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.yaml b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.yaml new file mode 100644 index 00000000000..05f3c979f7f --- /dev/null +++ b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.yaml @@ -0,0 +1,11 @@ +identifier: stm32f411e_disco@B +name: ST STM32F411E Discovery +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter +vendor: st diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco.yaml b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_D.yaml similarity index 100% rename from boards/arm/stm32f411e_disco/stm32f411e_disco.yaml rename to boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_D.yaml diff --git a/boards/arm/stm32f411e_disco/support/openocd.cfg b/boards/st/stm32f411e_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f411e_disco/support/openocd.cfg rename to boards/st/stm32f411e_disco/support/openocd.cfg diff --git a/boards/st/stm32f412g_disco/Kconfig.stm32f412g_disco b/boards/st/stm32f412g_disco/Kconfig.stm32f412g_disco new file mode 100644 index 00000000000..ec0581a33df --- /dev/null +++ b/boards/st/stm32f412g_disco/Kconfig.stm32f412g_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Powersoft +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F412G_DISCO + select SOC_STM32F412ZX diff --git a/boards/arm/stm32f412g_disco/arduino_r3_connector.dtsi b/boards/st/stm32f412g_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f412g_disco/arduino_r3_connector.dtsi rename to boards/st/stm32f412g_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f412g_disco/board.cmake b/boards/st/stm32f412g_disco/board.cmake similarity index 100% rename from boards/arm/stm32f412g_disco/board.cmake rename to boards/st/stm32f412g_disco/board.cmake diff --git a/boards/st/stm32f412g_disco/board.yml b/boards/st/stm32f412g_disco/board.yml new file mode 100644 index 00000000000..836972823ad --- /dev/null +++ b/boards/st/stm32f412g_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f412g_disco + vendor: st + socs: + - name: stm32f412zx diff --git a/boards/arm/stm32f412g_disco/doc/img/stm32f412g_disco.jpg b/boards/st/stm32f412g_disco/doc/img/stm32f412g_disco.jpg similarity index 100% rename from boards/arm/stm32f412g_disco/doc/img/stm32f412g_disco.jpg rename to boards/st/stm32f412g_disco/doc/img/stm32f412g_disco.jpg diff --git a/boards/st/stm32f412g_disco/doc/index.rst b/boards/st/stm32f412g_disco/doc/index.rst new file mode 100644 index 00000000000..0443d00b483 --- /dev/null +++ b/boards/st/stm32f412g_disco/doc/index.rst @@ -0,0 +1,201 @@ +.. _stm32f412g_disco_board: + +ST STM32F412G Discovery +####################### + +Overview +******** + +The STM32F412 Discovery kit features an ARM Cortex-M4 based STM32F412ZG MCU +with a wide range of connectivity support and configurations Here are +some highlights of the STM32F412G-DISCO board: + + +- STM32F412ZGT6 microcontroller featuring 1 Mbyte of Flash memory and 256 Kbytes of RAM in an LQFP144 package +- On-board ST-LINK/V2-1 SWD debugger supporting USB re-enumeration capability: + + - USB virtual COM port + - mass storage + - debug port + +- 1.54 inch 240x240 pixel TFT color LCD with parallel interface and capacitive touchscreen +- I2S Audio CODEC, with a stereo headset jack, including analog microphone input and a loudspeaker output +- Stereo digital MEMS microphones +- MicroSD card connector extension +- I2C extension connector +- 128 Mbit Quad-SPI Nor Flash +- Reset button and Joystick +- Four color user LEDs. +- USB OTG FS with Micro-AB connector +- Four power supply options: + + - ST-LINK/V2-1 USB connector + - User USB FS connector + - VIN from Arduino* connectors + - + 5 V from Arduino* connectors + +- Two power supplies for MCU: 2.0 V and 3.3 V +- Compatible with Arduino(tm) Uno revision 3 connectors +- Extension connector for direct access to various features of STM32F412ZGT6 MCU +- Comprehensive free software including a variety of examples, part of STM32Cube package + +.. image:: img/stm32f412g_disco.jpg + :align: center + :alt: STM32F412G-DISCO + +More information about the board can be found at the `32F412GDISCOVERY website`_. + +Hardware +******** + +STM32F469I-DISCO Discovery kit provides the following hardware components: + +- STM32F412ZGT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1 MB Flash +- 256 KB SRAM +- GPIO with external interrupt capability +- LCD parallel interface, 8080/6800 modes +- 1x12-bit ADC with 16 channels +- RTC +- Advanced-control Timer +- General Purpose Timers (12) +- Watchdog Timers (2) +- USART/UART (4) +- I2C (4) +- SPI (5) +- SDIO +- 2xCAN +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F412ZG can be found here: + - `STM32F412ZG on www.st.com`_ + - `STM32F412 reference manual`_ + +Supported Features +================== + +The Zephyr stm32f412g_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f412g_disco/stm32f412g_disco_defconfig` + + +Pin Mapping +=========== + +STM32F412G-DISCO Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F412GDISCOVERY board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- LD1 : PE0 +- LD2 : PE1 +- LD3 : PE2 +- LD4 : PE3 + +System Clock +============ + +STM32F412G-DISCO System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 100MHz, +driven internal oscillator. + +Serial Port +=========== + +The STM32F412G Discovery kit has up to 4 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``stm32f412g_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F412G-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32F412G-DISCO +------------------------------------------- + +Connect the STM32F412G-DISCO Discovery kit to your host computer using +the USB port, then run a serial host program to connect with your +board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f412g_disco + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f412g_disco + :maybe-skip-config: + :goals: debug + +.. _32F412GDISCOVERY website: + https://www.st.com/en/evaluation-tools/32f412gdiscovery.html + +.. _32F412GDISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00275919.pdf + +.. _STM32F412ZG on www.st.com: + https://www.st.com/en/microcontrollers/stm32f412zg.html + +.. _STM32F412 reference manual: + https://www.st.com/resource/en/reference_manual/dm00180369.pdf diff --git a/boards/arm/stm32f412g_disco/stm32f412g_disco.dts b/boards/st/stm32f412g_disco/stm32f412g_disco.dts similarity index 100% rename from boards/arm/stm32f412g_disco/stm32f412g_disco.dts rename to boards/st/stm32f412g_disco/stm32f412g_disco.dts diff --git a/boards/arm/stm32f412g_disco/stm32f412g_disco.yaml b/boards/st/stm32f412g_disco/stm32f412g_disco.yaml similarity index 100% rename from boards/arm/stm32f412g_disco/stm32f412g_disco.yaml rename to boards/st/stm32f412g_disco/stm32f412g_disco.yaml diff --git a/boards/arm/stm32f412g_disco/stm32f412g_disco_defconfig b/boards/st/stm32f412g_disco/stm32f412g_disco_defconfig similarity index 85% rename from boards/arm/stm32f412g_disco/stm32f412g_disco_defconfig rename to boards/st/stm32f412g_disco/stm32f412g_disco_defconfig index 1992a4de58c..0efcd3c8c7e 100644 --- a/boards/arm/stm32f412g_disco/stm32f412g_disco_defconfig +++ b/boards/st/stm32f412g_disco/stm32f412g_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F412ZX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f412g_disco/support/openocd.cfg b/boards/st/stm32f412g_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f412g_disco/support/openocd.cfg rename to boards/st/stm32f412g_disco/support/openocd.cfg diff --git a/boards/st/stm32f429i_disc1/Kconfig.defconfig b/boards/st/stm32f429i_disc1/Kconfig.defconfig new file mode 100644 index 00000000000..1d783097dad --- /dev/null +++ b/boards/st/stm32f429i_disc1/Kconfig.defconfig @@ -0,0 +1,14 @@ +# STM32F4DISCOVERY board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F429I_DISC1 + +config INPUT + default y if DISPLAY + +config MEMC + default y if DISPLAY + +endif # BOARD_STM32F429I_DISC1 diff --git a/boards/st/stm32f429i_disc1/Kconfig.stm32f429i_disc1 b/boards/st/stm32f429i_disc1/Kconfig.stm32f429i_disc1 new file mode 100644 index 00000000000..5af24073ad2 --- /dev/null +++ b/boards/st/stm32f429i_disc1/Kconfig.stm32f429i_disc1 @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F429I_DISC1 + select SOC_STM32F429XX diff --git a/boards/arm/stm32f429i_disc1/board.cmake b/boards/st/stm32f429i_disc1/board.cmake similarity index 100% rename from boards/arm/stm32f429i_disc1/board.cmake rename to boards/st/stm32f429i_disc1/board.cmake diff --git a/boards/st/stm32f429i_disc1/board.yml b/boards/st/stm32f429i_disc1/board.yml new file mode 100644 index 00000000000..e8e33228307 --- /dev/null +++ b/boards/st/stm32f429i_disc1/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f429i_disc1 + vendor: st + socs: + - name: stm32f429xx diff --git a/boards/arm/stm32f429i_disc1/doc/img/stm32f429i_disc1.jpg b/boards/st/stm32f429i_disc1/doc/img/stm32f429i_disc1.jpg similarity index 100% rename from boards/arm/stm32f429i_disc1/doc/img/stm32f429i_disc1.jpg rename to boards/st/stm32f429i_disc1/doc/img/stm32f429i_disc1.jpg diff --git a/boards/st/stm32f429i_disc1/doc/index.rst b/boards/st/stm32f429i_disc1/doc/index.rst new file mode 100644 index 00000000000..c61cfcaa739 --- /dev/null +++ b/boards/st/stm32f429i_disc1/doc/index.rst @@ -0,0 +1,229 @@ +.. _stm32f429i_disc1_board: + +ST STM32F429I Discovery +####################### + +Overview +******** + +The STM32F429I-DISC1 Discovery kit features an ARM Cortex-M4 based STM32F429ZI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the STM32F429I-DISC1 board: + +- STM32 microcontroller in LQFP144 package +- Extension header for all LQFP144 I/Os for quick connection to prototyping board and easy probing +- On-board ST-LINK/V2-B debugger/programmer with SWD connector +- Flexible board power supply: + + - ST-LINK/V2-1 USB connector + - User USB FS connector + - VIN from Arduino* compatible connectors + +- Two push-buttons: USER and RESET +- USB OTG FS with micro-AB connector +- 2.4-inch QVGA LCD with MIPI DSI interface and capacitive touch screen +- 64Mbit SDRAM +- L3GD20, ST-MEMS motion sensor 3-axis digital output gyroscope +- Six LEDs + + - LD1 (red/green) for USB communication + - LD2 (red) for 3.3 V power-on + - Two user LEDs: LD3 (green), LD4 (red) + - Two USB OTG LEDs: LD5 (green) VBUS and LD6 (red) OC (over-current) + +.. image:: img/stm32f429i_disc1.jpg + :align: center + :alt: STM32F429I-DISC1 + +More information about the board can be found at the `STM32F429I-DISC1 website`_. + +Hardware +******** + +The STM32F429I-DISC1 Discovery kit provides the following hardware components: + +- STM32F429ZIT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 180 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 2 MB Flash +- 256+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (4/4) +- I2C (3) +- SPI (6) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F429ZI can be found here: + - `STM32F429ZI on www.st.com`_ + - `STM32F429 Reference Manual`_ + +Supported Features +================== + +The Zephyr stm32f429i_disc1 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| OTG_HS | on-chip | usbotg_hs | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig` + + +Pin Mapping +=========== + +The STM32F429I-DISC1 Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32F429I-DISC1 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- USER_PB : PA0 +- LD3 : PG13 +- LD4 : PG12 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB9 +- I2C_2_SCL : PB10 +- I2C_2_SDA : PB11 +- I2C_3_SCL : PA8 +- I2C_3_SDA : PC9 +- SPI_5_CS : PF6 +- SPI_5_SCK : PF7 +- SPI_5_MISO : PF8 +- SPI_5_MOSI : PF9 +- OTG_HS_ID : PB12 +- OTG_HS_DM : PB14 +- OTG_HS_DP : PB15 + +System Clock +============ + +The STM32F429I-DISC1 System Clock could be driven by an internal or external oscillator, +as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 168MHz, +driven by an 8MHz high speed external clock. + +Serial Port +=========== + +The STM32F429I-DISC1 Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1. +The default communication settings are 115200 8N1. + +USB Port +=========== + +The STM32F429I-DISC1 Discovery kit has a USB FS capable Micro-B port. It is connected to the on-chip +OTG_HS peripheral, but operates in FS mode only since no HS PHY is present. The board supports device +and host OTG operation, but only device mode has been tested with Zephyr at this time. + +Programming and Debugging +************************* + +Applications for the ``stm32f429i_disc1`` board configuration can be built +and flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The STM32F429I-DISC1 Discovery kit includes a ST-LINK/V2-B embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32F429I-DISC1 +------------------------------------------- + +The board is configured to be flashed using west OpenOCD runner. +Alternatively, you can use `STM32CubeProgrammer`_ (after installing it) using the ``--runner`` +(or ``-r``) option: + +.. code-block:: console + + $ west flash --runner stm32cubeprogrammer + +First, connect the STM32F429I-DISC1 Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f429i_disc1 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, press the RESET button (The black one), you should see the following message: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f429i_disc1 + :goals: debug + +.. _STM32F429I-DISC1 website: + https://www.st.com/en/evaluation-tools/32f429idiscovery.html + +.. _STM32F429I-DISC1 board User Manual: + https://www.st.com/web/en/resource/technical/document/user_manual/DM00097320.pdf + +.. _STM32F429ZI on www.st.com: + https://www.st.com/en/microcontrollers/stm32f429-439.html + +.. _STM32F429 Reference Manual: + https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32f429i_disc1/stm32f429i_disc1.dts b/boards/st/stm32f429i_disc1/stm32f429i_disc1.dts similarity index 100% rename from boards/arm/stm32f429i_disc1/stm32f429i_disc1.dts rename to boards/st/stm32f429i_disc1/stm32f429i_disc1.dts diff --git a/boards/arm/stm32f429i_disc1/stm32f429i_disc1.yaml b/boards/st/stm32f429i_disc1/stm32f429i_disc1.yaml similarity index 100% rename from boards/arm/stm32f429i_disc1/stm32f429i_disc1.yaml rename to boards/st/stm32f429i_disc1/stm32f429i_disc1.yaml diff --git a/boards/arm/stm32f429i_disc1/stm32f429i_disc1_defconfig b/boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig similarity index 84% rename from boards/arm/stm32f429i_disc1/stm32f429i_disc1_defconfig rename to boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig index 0e2f562dc03..c729b83e3d0 100644 --- a/boards/arm/stm32f429i_disc1/stm32f429i_disc1_defconfig +++ b/boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F429XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f429i_disc1/support/openocd.cfg b/boards/st/stm32f429i_disc1/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f429i_disc1/support/openocd.cfg rename to boards/st/stm32f429i_disc1/support/openocd.cfg diff --git a/boards/st/stm32f469i_disco/Kconfig.defconfig b/boards/st/stm32f469i_disco/Kconfig.defconfig new file mode 100644 index 00000000000..e8f2fd5b6c9 --- /dev/null +++ b/boards/st/stm32f469i_disco/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32F469I-DISCO board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F469I_DISCO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + + +endif # BOARD_STM32F469I_DISCO diff --git a/boards/st/stm32f469i_disco/Kconfig.stm32f469i_disco b/boards/st/stm32f469i_disco/Kconfig.stm32f469i_disco new file mode 100644 index 00000000000..e63e8858c47 --- /dev/null +++ b/boards/st/stm32f469i_disco/Kconfig.stm32f469i_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F469I_DISCO + select SOC_STM32F469XX diff --git a/boards/arm/stm32f469i_disco/arduino_r3_connector.dtsi b/boards/st/stm32f469i_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f469i_disco/arduino_r3_connector.dtsi rename to boards/st/stm32f469i_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f469i_disco/board.cmake b/boards/st/stm32f469i_disco/board.cmake similarity index 100% rename from boards/arm/stm32f469i_disco/board.cmake rename to boards/st/stm32f469i_disco/board.cmake diff --git a/boards/st/stm32f469i_disco/board.yml b/boards/st/stm32f469i_disco/board.yml new file mode 100644 index 00000000000..2f7407bbc38 --- /dev/null +++ b/boards/st/stm32f469i_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f469i_disco + vendor: st + socs: + - name: stm32f469xx diff --git a/boards/arm/stm32f469i_disco/doc/img/stm32f469i_disco.jpg b/boards/st/stm32f469i_disco/doc/img/stm32f469i_disco.jpg similarity index 100% rename from boards/arm/stm32f469i_disco/doc/img/stm32f469i_disco.jpg rename to boards/st/stm32f469i_disco/doc/img/stm32f469i_disco.jpg diff --git a/boards/st/stm32f469i_disco/doc/index.rst b/boards/st/stm32f469i_disco/doc/index.rst new file mode 100644 index 00000000000..85ebec3778f --- /dev/null +++ b/boards/st/stm32f469i_disco/doc/index.rst @@ -0,0 +1,207 @@ +.. _stm32f469i_disco_board: + +ST STM32F469I Discovery +####################### + +Overview +******** + +The STM32F469 Discovery kit features an ARM Cortex-M4 based STM32F469NI MCU +with a wide range of connectivity support and configurations Here are +some highlights of the STM32F469I-DISCO board: + + +- STM32 microcontroller in BGA216 package +- On-board ST-LINK/V2-1 debugger/programmer, supporting USB reenumeration capability +- Flexible board power supply: + + - ST-LINK/V2-1 USB connector + - User USB FS connector + - VIN from Arduino* compatible connectors + +- Four user LEDs +- Two push-buttons: USER and RESET +- USB OTG FS with micro-AB connector +- 4-inch 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive touch screen +- SAI Audio DAC, with a stereo headphone output jack +- Three MEMS microphones +- MicroSD card connector +- I2C extension connector +- 4Mx32bit SDRAM +- 128-Mbit Quad-SPI NOR Flash +- Expansion connectors and Arduino UNO V3 connectors + +.. image:: img/stm32f469i_disco.jpg + :align: center + :alt: STM32F469I-DISCO + +More information about the board can be found at the `32F469IDISCOVERY website`_. + +Hardware +******** + +STM32F469I-DISCO Discovery kit provides the following hardware components: + +- STM32F469NIH6 in BGA216 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 180 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 2 MB Flash +- 384+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- LCD parallel interface, 8080/6800 modes +- LCD TFT controller supporting up to XGA resolution +- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (8) +- I2C (3) +- SPI (6) +- 1xSAI (serial audio interface) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F469NI can be found here: + - `STM32F469NI on www.st.com`_ + - `STM32F469 reference manual`_ + +Supported Features +================== + +The Zephyr stm32f469i_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| SDIO | on-chip | SD-card controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f469i_disco/stm32f469i_disco_defconfig` + + +Pin Mapping +=========== + +STM32F469I-DISCO Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F469IDISCOVERY board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_3 TX/RX : PB10/PB11 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI2 NSS/SCK/MISO/MOSI : PH6/PD3/PB14/PB15 (Arduino SPI) +- SDIO D0/D1/D2/D3/CLK/Detect : PC8/PC9/PC10/PC11/PC12/PG2 +- USB DM : PA11 +- USB DP : PA12 +- USER_PB : PA0 +- LD1 : PG6 +- LD2 : PD4 +- LD3 : PD5 +- LD4 : PK3 + +System Clock +============ + +STM32F469I-DISCO System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 180MHz, +driven by 8MHz high speed external clock. + +Serial Port +=========== + +The STM32F469 Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART3. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``stm32f469i_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F469I-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32F469I-DISCO +------------------------------------------- + +First, connect the STM32F469I-DISCO Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f469i_disco + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f469i_disco + :goals: debug + + +.. _32F469IDISCOVERY website: + https://www.st.com/en/evaluation-tools/32f469idiscovery.html + +.. _32F469IDISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00218846.pdf + +.. _STM32F469NI on www.st.com: + https://www.st.com/en/microcontrollers/stm32f469ni.html + +.. _STM32F469 reference manual: + https://www.st.com/resource/en/reference_manual/dm00127514.pdf diff --git a/boards/arm/stm32f469i_disco/stm32f469i_disco.dts b/boards/st/stm32f469i_disco/stm32f469i_disco.dts similarity index 100% rename from boards/arm/stm32f469i_disco/stm32f469i_disco.dts rename to boards/st/stm32f469i_disco/stm32f469i_disco.dts diff --git a/boards/arm/stm32f469i_disco/stm32f469i_disco.yaml b/boards/st/stm32f469i_disco/stm32f469i_disco.yaml similarity index 100% rename from boards/arm/stm32f469i_disco/stm32f469i_disco.yaml rename to boards/st/stm32f469i_disco/stm32f469i_disco.yaml diff --git a/boards/arm/stm32f469i_disco/stm32f469i_disco_defconfig b/boards/st/stm32f469i_disco/stm32f469i_disco_defconfig similarity index 84% rename from boards/arm/stm32f469i_disco/stm32f469i_disco_defconfig rename to boards/st/stm32f469i_disco/stm32f469i_disco_defconfig index 94a8f52809e..c729b83e3d0 100644 --- a/boards/arm/stm32f469i_disco/stm32f469i_disco_defconfig +++ b/boards/st/stm32f469i_disco/stm32f469i_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F469XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f469i_disco/support/openocd.cfg b/boards/st/stm32f469i_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f469i_disco/support/openocd.cfg rename to boards/st/stm32f469i_disco/support/openocd.cfg diff --git a/boards/st/stm32f4_disco/Kconfig.stm32f4_disco b/boards/st/stm32f4_disco/Kconfig.stm32f4_disco new file mode 100644 index 00000000000..88d7525c640 --- /dev/null +++ b/boards/st/stm32f4_disco/Kconfig.stm32f4_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F4_DISCO + select SOC_STM32F407XG diff --git a/boards/arm/stm32f4_disco/board.cmake b/boards/st/stm32f4_disco/board.cmake similarity index 100% rename from boards/arm/stm32f4_disco/board.cmake rename to boards/st/stm32f4_disco/board.cmake diff --git a/boards/st/stm32f4_disco/board.yml b/boards/st/stm32f4_disco/board.yml new file mode 100644 index 00000000000..663f8613eec --- /dev/null +++ b/boards/st/stm32f4_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f4_disco + vendor: st + socs: + - name: stm32f407xx diff --git a/boards/arm/stm32f4_disco/doc/img/stm32f4_disco.jpg b/boards/st/stm32f4_disco/doc/img/stm32f4_disco.jpg similarity index 100% rename from boards/arm/stm32f4_disco/doc/img/stm32f4_disco.jpg rename to boards/st/stm32f4_disco/doc/img/stm32f4_disco.jpg diff --git a/boards/st/stm32f4_disco/doc/index.rst b/boards/st/stm32f4_disco/doc/index.rst new file mode 100644 index 00000000000..8839759a3ab --- /dev/null +++ b/boards/st/stm32f4_disco/doc/index.rst @@ -0,0 +1,213 @@ +.. _stm32f4_disco_board: + +ST STM32F4 Discovery +#################### + +Overview +******** + +The STM32F4DISCOVERY Discovery kit features an ARM Cortex-M4 based STM32F407VG MCU +with a wide range of connectivity support and configurations Here are +some highlights of the STM32F4DISCOVERY board: + + +- STM32 microcontroller in LQFP100 package +- Extension header for all LQFP100 I/Os for quick connection to prototyping board and easy probing +- On-board ST-LINK/V2 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Eight LEDs: + + - USB communication (LD1) + - 3.3 V power on (LD2) + - Four user LEDs: orange (LD3), green (LD4), red (LD5), and blue (LD6) + - 2 USB OTG LEDs for VBUS (LD7) and over-current (LD8) + +- Two push-buttons: USER and RESET +- USB OTG FS with micro-AB connector +- LIS302DL or LIS3DSH ST MEMS 3-axis accelerometer +- MP45DT02 ST-MEMS audio sensor omni-directional digital microphone +- CS43L22 audio DAC with integrated class D speaker driver + +.. image:: img/stm32f4_disco.jpg + :align: center + :alt: STM32F4DISCOVERY + +More information about the board can be found at the `STM32F4DISCOVERY website`_. + +Hardware +******** + +STM32F4DISCOVERY Discovery kit provides the following hardware components: + +- STM32F407VGT6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 168 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 1 MB Flash +- 192+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (6) +- I2C (3) +- SPI (3) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F407VG can be found here: + - `STM32F407VG on www.st.com`_ + - `STM32F407 reference manual`_ + +Supported Features +================== + +The Zephyr stm32f4_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_. + Zephyr default configuration uses CAN_2 exclusively, as simultaneous use + of CAN_1 and CAN_2 is not yet supported. + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f4_disco/stm32f4_disco_defconfig` + + +Pin Mapping +=========== + +STM32F4DISCOVERY Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32F4DISCOVERY board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PA0 +- LD3 : PD13 +- LD4 : PD12 +- LD5 : PD14 +- LD6 : PD15 +- USB DM : PA11 +- USB DP : PA12 +- CAN1_RX : PB8 +- CAN1_TX : PB9 +- CAN2_RX : PB5 +- CAN2_TX : PB13 + +System Clock +============ + +STM32F4DISCOVERY System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 168MHz, +driven by 8MHz high speed external clock. + +Serial Port +=========== + +STM32F4DISCOVERY Discovery kit has up to 6 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. +Please note that ST-Link Virtual Com Port is not wired to chip serial port. In order to +enable console output you should use a serial cable and connect it to UART2 pins (PA2/PA3). + + +Programming and Debugging +************************* + +Applications for the ``stm32f4_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F4DISCOVERY Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32F4DISCOVERY +------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f4_disco + :goals: build flash + +You should see user led "LD4" blinking. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f4_disco + :maybe-skip-config: + :goals: debug + +.. _STM32F4DISCOVERY website: + https://www.st.com/en/evaluation-tools/stm32f4discovery.html + +.. _STM32F4DISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00039084.pdf + +.. _STM32F407VG on www.st.com: + https://www.st.com/en/microcontrollers/stm32f407vg.html + +.. _STM32F407 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031020.pdf + +.. _SK Pang CAN breakout board: + https://www.skpang.co.uk/products/can-bus-can-fd-breakout-board-5v-supply-and-3-3v-logic diff --git a/boards/arm/stm32f4_disco/stm32f4_disco.dts b/boards/st/stm32f4_disco/stm32f4_disco.dts similarity index 100% rename from boards/arm/stm32f4_disco/stm32f4_disco.dts rename to boards/st/stm32f4_disco/stm32f4_disco.dts diff --git a/boards/arm/stm32f4_disco/stm32f4_disco.yaml b/boards/st/stm32f4_disco/stm32f4_disco.yaml similarity index 100% rename from boards/arm/stm32f4_disco/stm32f4_disco.yaml rename to boards/st/stm32f4_disco/stm32f4_disco.yaml diff --git a/boards/arm/stm32f4_disco/stm32f4_disco_defconfig b/boards/st/stm32f4_disco/stm32f4_disco_defconfig similarity index 84% rename from boards/arm/stm32f4_disco/stm32f4_disco_defconfig rename to boards/st/stm32f4_disco/stm32f4_disco_defconfig index ad325266c72..c729b83e3d0 100644 --- a/boards/arm/stm32f4_disco/stm32f4_disco_defconfig +++ b/boards/st/stm32f4_disco/stm32f4_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f4_disco/support/openocd.cfg b/boards/st/stm32f4_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f4_disco/support/openocd.cfg rename to boards/st/stm32f4_disco/support/openocd.cfg diff --git a/boards/st/stm32f723e_disco/Kconfig.defconfig b/boards/st/stm32f723e_disco/Kconfig.defconfig new file mode 100644 index 00000000000..607dc58ca36 --- /dev/null +++ b/boards/st/stm32f723e_disco/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32F723E DISCOVERY board configuration + +# Copyright (c) 2018 Aurelien Jarno +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F723E_DISCO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + + +endif # BOARD_STM32F723E_DISCO diff --git a/boards/st/stm32f723e_disco/Kconfig.stm32f723e_disco b/boards/st/stm32f723e_disco/Kconfig.stm32f723e_disco new file mode 100644 index 00000000000..a8caec5cf6f --- /dev/null +++ b/boards/st/stm32f723e_disco/Kconfig.stm32f723e_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Aurelien Jarno +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F723E_DISCO + select SOC_STM32F723XX diff --git a/boards/arm/stm32f723e_disco/arduino_r3_connector.dtsi b/boards/st/stm32f723e_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f723e_disco/arduino_r3_connector.dtsi rename to boards/st/stm32f723e_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f723e_disco/board.cmake b/boards/st/stm32f723e_disco/board.cmake similarity index 100% rename from boards/arm/stm32f723e_disco/board.cmake rename to boards/st/stm32f723e_disco/board.cmake diff --git a/boards/st/stm32f723e_disco/board.yml b/boards/st/stm32f723e_disco/board.yml new file mode 100644 index 00000000000..65248705234 --- /dev/null +++ b/boards/st/stm32f723e_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f723e_disco + vendor: st + socs: + - name: stm32f723xx diff --git a/boards/arm/stm32f723e_disco/doc/img/stm32f723e_disco.jpg b/boards/st/stm32f723e_disco/doc/img/stm32f723e_disco.jpg similarity index 100% rename from boards/arm/stm32f723e_disco/doc/img/stm32f723e_disco.jpg rename to boards/st/stm32f723e_disco/doc/img/stm32f723e_disco.jpg diff --git a/boards/st/stm32f723e_disco/doc/index.rst b/boards/st/stm32f723e_disco/doc/index.rst new file mode 100644 index 00000000000..554c329db81 --- /dev/null +++ b/boards/st/stm32f723e_disco/doc/index.rst @@ -0,0 +1,192 @@ +.. _stm32f723e_disco_board: + +ST STM32F723E Discovery +####################### + +Overview +******** + +The discovery kit enables a wide diversity of applications taking benefit +from audio, multi-sensor support, graphics, security, security, video, +and high-speed connectivity features. Important board features include: + +- STM32F723IEK6 microcontroller featuring 512 Kbytes of Flash memory and 256+16+4 Kbytes of RAM, in BGA176 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- TFT LCD 240x240 pixels with touch panel +- SAI audio codec +- Audio line in and line out jack +- Stereo speaker outputs +- Four ST MEMS microphones +- Two pushbuttons (user and reset) +- 512-Mbit Quad-SPI Flash memory +- 8-Mbit external PSRAM +- USB OTG HS with Micro-AB connectors +- USB OTG FS with Micro-AB connectors + +.. image:: img/stm32f723e_disco.jpg + :align: center + :alt: STM32F723E-DISCO + +More information about the board can be found at the `32F723E-DISCO website`_. + +Hardware +******** + +The STM32F723E Discovery kit provides the following hardware components: + +- STM32F723IEK6 in BGA176 package +- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU +- 216 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 1 MB Flash +- 256+16+4 KB SRAM including 64KB of tightly coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer (2) +- General Purpose Timers (13) +- Watchdog Timers (2) +- USART/UART (8) +- I2C (3) +- SPI (5) +- 2xSAI (serial audio interface) +- SDIO (2) +- CAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and on-chip hi-speed PHY +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F723IEK6 can be found here: + +- `STM32F723IEK6 on www.st.com`_ +- `STM32F72xxx reference manual`_ + +Supported Features +================== + +The Zephyr stm32f723e_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f723e_disco/stm32f723e_disco_defconfig` + +Pin Mapping +=========== + +STM32F723E Discovery kit has 7 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F723E-DISCO board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2 TX/RX : PA2/PA3 (Arduino Serial) +- UART_6 TX/RX : PC6/PC7 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 +- I2C2 SCL/SDA : PH4/PH5 (Arduino I2C) +- I2C3 SCL/SDA : PA8/PH8 +- SPI1 SCK/MISO/MOSI : PA5/PB4/PB5 (Arduino SPI) +- LD1 : PA5 +- LD5 : PA7 +- LD6 : PB1 +- OTG_FS_DM : PA11 +- OTG_FS_DP : PA12 + +System Clock +============ + +The STM32F723E System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven by the PLL +clock at 216MHz, driven by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32F723E Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART6 +which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication +settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f723e_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F723E Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to STM32F723E-DISCO +------------------------------------------- + +First, connect the STM32F723E Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f723e_disco + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f723e_disco + :goals: debug + + +.. _32F723E-DISCO website: + https://www.st.com/en/evaluation-tools/32f723ediscovery.html + +.. _32F723E-DISCO board User Manual: + https://www.st.com/resource/en/user_manual/dm00342318.pdf + +.. _STM32F723IEK6 on www.st.com: + https://www.st.com/en/microcontrollers/stm32f723ie.html + +.. _STM32F72xxx reference manual: + https://www.st.com/resource/en/reference_manual/dm00305990.pdf diff --git a/boards/arm/stm32f723e_disco/stm32f723e_disco.dts b/boards/st/stm32f723e_disco/stm32f723e_disco.dts similarity index 100% rename from boards/arm/stm32f723e_disco/stm32f723e_disco.dts rename to boards/st/stm32f723e_disco/stm32f723e_disco.dts diff --git a/boards/arm/stm32f723e_disco/stm32f723e_disco.yaml b/boards/st/stm32f723e_disco/stm32f723e_disco.yaml similarity index 100% rename from boards/arm/stm32f723e_disco/stm32f723e_disco.yaml rename to boards/st/stm32f723e_disco/stm32f723e_disco.yaml diff --git a/boards/arm/stm32f723e_disco/stm32f723e_disco_defconfig b/boards/st/stm32f723e_disco/stm32f723e_disco_defconfig similarity index 84% rename from boards/arm/stm32f723e_disco/stm32f723e_disco_defconfig rename to boards/st/stm32f723e_disco/stm32f723e_disco_defconfig index 404cd5c1bb1..c729b83e3d0 100644 --- a/boards/arm/stm32f723e_disco/stm32f723e_disco_defconfig +++ b/boards/st/stm32f723e_disco/stm32f723e_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F723XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f723e_disco/support/openocd.cfg b/boards/st/stm32f723e_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f723e_disco/support/openocd.cfg rename to boards/st/stm32f723e_disco/support/openocd.cfg diff --git a/boards/st/stm32f746g_disco/Kconfig.defconfig b/boards/st/stm32f746g_disco/Kconfig.defconfig new file mode 100644 index 00000000000..e617f92308b --- /dev/null +++ b/boards/st/stm32f746g_disco/Kconfig.defconfig @@ -0,0 +1,37 @@ +# STM32F746G DISCOVERY board configuration + +# Copyright (c) 2018 Yurii Hamann +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F746G_DISCO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +config INPUT + default y if LVGL + +if DISPLAY + +# MEMC needs to be enabled in order to store +# display buffer to external SDRAM connected to FMC +config MEMC + default y + +endif # DISPLAY + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +endif # INPUT + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_STM32F746G_DISCO diff --git a/boards/st/stm32f746g_disco/Kconfig.stm32f746g_disco b/boards/st/stm32f746g_disco/Kconfig.stm32f746g_disco new file mode 100644 index 00000000000..3e29d5e0747 --- /dev/null +++ b/boards/st/stm32f746g_disco/Kconfig.stm32f746g_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Yurii Hamann +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F746G_DISCO + select SOC_STM32F746XX diff --git a/boards/arm/stm32f746g_disco/arduino_r3_connector.dtsi b/boards/st/stm32f746g_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f746g_disco/arduino_r3_connector.dtsi rename to boards/st/stm32f746g_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f746g_disco/board.cmake b/boards/st/stm32f746g_disco/board.cmake similarity index 100% rename from boards/arm/stm32f746g_disco/board.cmake rename to boards/st/stm32f746g_disco/board.cmake diff --git a/boards/st/stm32f746g_disco/board.yml b/boards/st/stm32f746g_disco/board.yml new file mode 100644 index 00000000000..3522ea40ac3 --- /dev/null +++ b/boards/st/stm32f746g_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f746g_disco + vendor: st + socs: + - name: stm32f746xx diff --git a/boards/arm/stm32f746g_disco/doc/img/stm32f746g_disco.jpg b/boards/st/stm32f746g_disco/doc/img/stm32f746g_disco.jpg similarity index 100% rename from boards/arm/stm32f746g_disco/doc/img/stm32f746g_disco.jpg rename to boards/st/stm32f746g_disco/doc/img/stm32f746g_disco.jpg diff --git a/boards/st/stm32f746g_disco/doc/index.rst b/boards/st/stm32f746g_disco/doc/index.rst new file mode 100644 index 00000000000..03e71c20b90 --- /dev/null +++ b/boards/st/stm32f746g_disco/doc/index.rst @@ -0,0 +1,243 @@ +.. _stm32f746g_disco_board: + +ST STM32F746G Discovery +####################### + +Overview +******** + +The discovery kit enables a wide diversity of applications taking benefit +from audio, multi-sensor support, graphics, security, security, video, +and high-speed connectivity features. Important board features include: + +- STM32F746NGH6 microcontroller featuring 1 Mbytes of Flash memory and 340 Kbytes of RAM, in BGA216 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- Five power supply options: + + - ST LINK/V2-1 + - USB FS connector + - USB HS connector + - VIN from Arduino connector + - External 5 V from connector + +- Two pushbuttons (user and reset) +- USB functions: virtual COM port, mass storage, debug port +- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen +- SAI audio codec +- Audio line in and line out jack +- Stereo speaker outputs +- Two ST MEMS microphones +- SPDIF RCA input connector +- 128-Mbit Quad-SPI Flash memory +- 128-Mbit SDRAM (64 Mbits accessible) +- Connector for microSD card +- USB OTG HS with Micro-AB connectors +- USB OTG FS with Micro-AB connectors +- Ethernet connector compliant with IEEE-802.3-2002 + +.. image:: img/stm32f746g_disco.jpg + :align: center + :alt: STM32F746G-DISCO + +More information about the board can be found at the `32F746G-DISCO website`_. + +Hardware +******** + +The STM32F746G Discovery kit provides the following hardware components: + +- STM32F746NGH6 in BGA216 package +- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU +- 216 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 2 MB Flash +- 384+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- LCD parallel interface, 8080/6800 modes +- LCD TFT controller supporting up to XGA resolution +- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (8) +- I2C (3) +- SPI (6) +- 1xSAI (serial audio interface) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F746NGH6 can be found here: + +- `STM32F746NGH6 on www.st.com`_ +- `STM32F74xxx reference manual`_ + +Supported Features +================== + +The Zephyr stm32f746g_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | Ethernet | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| LTDC | on-chip | display | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f746g_disco/stm32f746g_disco_defconfig` + +Pin Mapping +=========== + +STM32F746G Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F746G-DISCO board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The STM32F746G Discovery kit features an Arduino Uno V3 connector. Board is +configured as follows + +- UART_1 TX/RX : PA9/PB7 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PC6/PC7 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SDMMC_1 D0/D1/D2/D3/CK/CD/CMD: PC8/PC9/PC10/PC11/PC12/PC13/PD2 +- SPI2 NSS/SCK/MISO/MOSI : PA8/PI1/PB14/PB15 (Arduino SPI) +- PWM_3_CH1 : PB4 +- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 +- USER_PB : PI11 +- LD1 : PI1 +- USB DM : PA11 +- USB DP : PA12 +- FMC SDRAM : + + - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 + - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 + - A14/A15 : PG4/PG5 + - SDNRAS/SDNCAS : PF11/PG15 + - NBL0/NBL1 : PE0/PE1 + - SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3 + +- LTDC : + + - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 + - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 + - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 + - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 + + +System Clock +============ + +The STM32F746G System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven by the PLL +clock at 216MHz, driven by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32F746G Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 +which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication +settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f746g_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F746G Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to STM32F746G +------------------------------------------- + +First, connect the STM32F746G Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f746g_disco + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f746g_disco + :goals: debug + + +.. _32F746G-DISCO website: + https://www.st.com/en/evaluation-tools/32f746gdiscovery.html + +.. _32F746G-DISCO board User Manual: + https://www.st.com/resource/en/user_manual/dm00190424.pdf + +.. _STM32F746NGH6 on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html + +.. _STM32F74xxx reference manual: + https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/stm32f746g_disco/stm32f746g_disco.dts b/boards/st/stm32f746g_disco/stm32f746g_disco.dts similarity index 100% rename from boards/arm/stm32f746g_disco/stm32f746g_disco.dts rename to boards/st/stm32f746g_disco/stm32f746g_disco.dts diff --git a/boards/arm/stm32f746g_disco/stm32f746g_disco.yaml b/boards/st/stm32f746g_disco/stm32f746g_disco.yaml similarity index 100% rename from boards/arm/stm32f746g_disco/stm32f746g_disco.yaml rename to boards/st/stm32f746g_disco/stm32f746g_disco.yaml diff --git a/boards/arm/stm32f746g_disco/stm32f746g_disco_defconfig b/boards/st/stm32f746g_disco/stm32f746g_disco_defconfig similarity index 84% rename from boards/arm/stm32f746g_disco/stm32f746g_disco_defconfig rename to boards/st/stm32f746g_disco/stm32f746g_disco_defconfig index fff57f6d5e4..c729b83e3d0 100644 --- a/boards/arm/stm32f746g_disco/stm32f746g_disco_defconfig +++ b/boards/st/stm32f746g_disco/stm32f746g_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F746XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f746g_disco/support/openocd.cfg b/boards/st/stm32f746g_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f746g_disco/support/openocd.cfg rename to boards/st/stm32f746g_disco/support/openocd.cfg diff --git a/boards/st/stm32f7508_dk/Kconfig.defconfig b/boards/st/stm32f7508_dk/Kconfig.defconfig new file mode 100644 index 00000000000..c43b749d79b --- /dev/null +++ b/boards/st/stm32f7508_dk/Kconfig.defconfig @@ -0,0 +1,37 @@ +# STM32F7508-DK Discovery board configuration + +# Copyright (c) 2022, Rtone. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F7508_DK + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +if DISPLAY + +# MEMC needs to be enabled in order to store +# display buffer to external SDRAM connected to FMC +config MEMC + default y + +endif # DISPLAY + +config INPUT + default y if LVGL + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +endif # INPUT + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_STM32F7508_DK diff --git a/boards/st/stm32f7508_dk/Kconfig.stm32f7508_dk b/boards/st/stm32f7508_dk/Kconfig.stm32f7508_dk new file mode 100644 index 00000000000..8da75f6864a --- /dev/null +++ b/boards/st/stm32f7508_dk/Kconfig.stm32f7508_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2022, Rtone. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F7508_DK + select SOC_STM32F750XX diff --git a/boards/arm/stm32f7508_dk/arduino_r3_connector.dtsi b/boards/st/stm32f7508_dk/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f7508_dk/arduino_r3_connector.dtsi rename to boards/st/stm32f7508_dk/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f7508_dk/board.cmake b/boards/st/stm32f7508_dk/board.cmake similarity index 100% rename from boards/arm/stm32f7508_dk/board.cmake rename to boards/st/stm32f7508_dk/board.cmake diff --git a/boards/st/stm32f7508_dk/board.yml b/boards/st/stm32f7508_dk/board.yml new file mode 100644 index 00000000000..46e12e5a6f0 --- /dev/null +++ b/boards/st/stm32f7508_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f7508_dk + vendor: st + socs: + - name: stm32f750xx diff --git a/boards/arm/stm32f7508_dk/doc/img/stm32f7508_dk.jpg b/boards/st/stm32f7508_dk/doc/img/stm32f7508_dk.jpg similarity index 100% rename from boards/arm/stm32f7508_dk/doc/img/stm32f7508_dk.jpg rename to boards/st/stm32f7508_dk/doc/img/stm32f7508_dk.jpg diff --git a/boards/st/stm32f7508_dk/doc/index.rst b/boards/st/stm32f7508_dk/doc/index.rst new file mode 100644 index 00000000000..0b3737a8761 --- /dev/null +++ b/boards/st/stm32f7508_dk/doc/index.rst @@ -0,0 +1,238 @@ +.. _stm32f7508_dk_board: + +ST STM32F7508-DK Discovery Kit +############################## + +Overview +******** + +The discovery kit enables a wide diversity of applications taking benefit +from audio, multi-sensor support, graphics, security, security, video, +and high-speed connectivity features. Important board features include: + +- STM32F750N8H6 microcontroller featuring 64 Kbytes of Flash memory and 340 Kbytes of RAM, in BGA216 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- Five power supply options: + + - ST LINK/V2-1 + - USB FS connector + - USB HS connector + - VIN from Arduino connector + - External 5 V from connector + +- Two pushbuttons (user and reset) +- USB functions: virtual COM port, mass storage, debug port +- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen +- SAI audio codec +- Audio line in and line out jack +- Two ST MEMS microphones +- SPDIF RCA input connector +- 128-Mbit Quad-SPI Flash memory +- 128-Mbit SDRAM (64 Mbits accessible) +- Connector for microSD card +- USB OTG HS with Micro-AB connectors +- USB OTG FS with Micro-AB connectors +- Ethernet connector compliant with IEEE-802.3-2002 + +.. image:: img/stm32f7508_dk.jpg + :align: center + :alt: STM32F7508-DK + +More information about the board can be found at the `32F7508-DK website`_. + +Hardware +******** + +The STM32F7508-DK Discovery kit provides the following hardware components: + +- STM32F750N8H6 in BGA216 package +- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU +- 216 MHz max CPU frequency +- 64 KB Flash +- 320+16+4 KB SRAM +- GPIO with external interrupt capability +- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen +- 3x12-bit ADC +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (8) +- I2C (4) +- SPI (6) +- 2xSAI (serial audio interface) +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F750x8 can be found here: + +- `STM32F750x8 on www.st.com`_ +- `STM32F74xxx reference manual`_ + +Supported Features +================== + +The Zephyr stm32f7508_dk board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | Ethernet | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| LTDC | on-chip | display | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f7508_dk/stm32f7508_dk_defconfig` + +Pin Mapping +=========== + +STM32F7508-DK Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F7508-DK board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The STM32F7508 Discovery kit features an Arduino Uno V3 connector. Board is +configured as follows + +- UART_1 TX/RX : PA9/PB7 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PC6/PC7 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SDMMC_1 D0/D1/D2/D3/CK/CD/CMD: PC8/PC9/PC10/PC11/PC12/PC13/PD2 +- SPI2 NSS/SCK/MISO/MOSI : PA8/PI1/PB14/PB15 (Arduino SPI) +- PWM_3_CH1 : PB4 +- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 +- USER_PB : PI11 +- LD1 : PI1 +- USB DM : PA11 +- USB DP : PA12 +- FMC SDRAM : + + - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 + - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 + - A14/A15 : PG4/PG5 + - SDNRAS/SDNCAS : PF11/PG15 + - NBL0/NBL1 : PE0/PE1 + - SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3 + +- LTDC : + + - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 + - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 + - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 + - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 + + +System Clock +============ + +The STM32F7508 System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven by the PLL +clock at 216MHz, driven by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32F7508-DK Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 +which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication +settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f7508_dk`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F7508-DK Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to STM32F7508-DK +------------------------------------------- + +First, connect the STM32F746G Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f7508_dk + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f7508_dk + :goals: debug + + +.. _32F7508-DK website: + https://www.st.com/en/evaluation-tools/stm32f7508-dk.html + +.. _32F7508-DK board User Manual: + https://www.st.com/resource/en/user_manual/dm00537062-discovery-kit-for-stm32f7-series-with-stm32f750n8-mcu-stmicroelectronics.pdf + +.. _STM32F750x8 on www.st.com: + https://www.st.com/resource/en/datasheet/stm32f750z8.pdf + +.. _STM32F74xxx reference manual: + https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/stm32f7508_dk/stm32f7508_dk.dts b/boards/st/stm32f7508_dk/stm32f7508_dk.dts similarity index 100% rename from boards/arm/stm32f7508_dk/stm32f7508_dk.dts rename to boards/st/stm32f7508_dk/stm32f7508_dk.dts diff --git a/boards/arm/stm32f7508_dk/stm32f7508_dk.yaml b/boards/st/stm32f7508_dk/stm32f7508_dk.yaml similarity index 100% rename from boards/arm/stm32f7508_dk/stm32f7508_dk.yaml rename to boards/st/stm32f7508_dk/stm32f7508_dk.yaml diff --git a/boards/arm/stm32f7508_dk/stm32f7508_dk_defconfig b/boards/st/stm32f7508_dk/stm32f7508_dk_defconfig similarity index 85% rename from boards/arm/stm32f7508_dk/stm32f7508_dk_defconfig rename to boards/st/stm32f7508_dk/stm32f7508_dk_defconfig index b78ebb9d3a3..18159201a57 100644 --- a/boards/arm/stm32f7508_dk/stm32f7508_dk_defconfig +++ b/boards/st/stm32f7508_dk/stm32f7508_dk_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2022, Rtone. # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F750XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f7508_dk/support/openocd.cfg b/boards/st/stm32f7508_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f7508_dk/support/openocd.cfg rename to boards/st/stm32f7508_dk/support/openocd.cfg diff --git a/boards/st/stm32f769i_disco/Kconfig.defconfig b/boards/st/stm32f769i_disco/Kconfig.defconfig new file mode 100644 index 00000000000..be174cce67f --- /dev/null +++ b/boards/st/stm32f769i_disco/Kconfig.defconfig @@ -0,0 +1,22 @@ +# STM32F769I DISCOVERY board configuration + +# Copyright (c) 2018 Yong Jin +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F769I_DISCO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +config INPUT + default y if LVGL + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_STM32F769I_DISCO diff --git a/boards/st/stm32f769i_disco/Kconfig.stm32f769i_disco b/boards/st/stm32f769i_disco/Kconfig.stm32f769i_disco new file mode 100644 index 00000000000..0041a7a9b69 --- /dev/null +++ b/boards/st/stm32f769i_disco/Kconfig.stm32f769i_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Yong Jin +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F769I_DISCO + select SOC_STM32F769XX diff --git a/boards/arm/stm32f769i_disco/arduino_r3_connector.dtsi b/boards/st/stm32f769i_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f769i_disco/arduino_r3_connector.dtsi rename to boards/st/stm32f769i_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f769i_disco/board.cmake b/boards/st/stm32f769i_disco/board.cmake similarity index 100% rename from boards/arm/stm32f769i_disco/board.cmake rename to boards/st/stm32f769i_disco/board.cmake diff --git a/boards/st/stm32f769i_disco/board.yml b/boards/st/stm32f769i_disco/board.yml new file mode 100644 index 00000000000..de83c60be99 --- /dev/null +++ b/boards/st/stm32f769i_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f769i_disco + vendor: st + socs: + - name: stm32f769xx diff --git a/boards/arm/stm32f769i_disco/doc/img/stm32f769i_disco.jpg b/boards/st/stm32f769i_disco/doc/img/stm32f769i_disco.jpg similarity index 100% rename from boards/arm/stm32f769i_disco/doc/img/stm32f769i_disco.jpg rename to boards/st/stm32f769i_disco/doc/img/stm32f769i_disco.jpg diff --git a/boards/st/stm32f769i_disco/doc/index.rst b/boards/st/stm32f769i_disco/doc/index.rst new file mode 100644 index 00000000000..223c48a9dbe --- /dev/null +++ b/boards/st/stm32f769i_disco/doc/index.rst @@ -0,0 +1,225 @@ +.. _stm32f769i_disco_board: + +ST STM32F769I Discovery +####################### + +Overview +******** + +The discovery kit enables a wide diversity of applications taking benefit +from audio, multi-sensor support, graphics, security, security, video, +and high-speed connectivity features. Important board features include: + +- STM32F769NIH6 microcontroller featuring 2 Mbytes of Flash memory and 512 Kbytes of RAM, in BGA216 package +- On-board ST-LINK/V2-1 supporting USB reenumeration capability +- USB ST-LINK functions: virtual COM port, mass storage, debug port +- Five power supply options: + + - ST LINK/V2-1 + - USB HS connector + - 5 V from RJ45 (Power Over Ethernet) + - 5 V from Arduino™ or external connector + - USB charger + +- 4-inch capacitive touch LCD display with MIPI-DSI connector +- SAI audio codec +- Two audio line jacks, one for input and one for output +- Stereo speaker outputs +- Four ST MEMS microphones on DFSDM inputs +- Two SPDIF RCA input and output connectors +- Two push-buttons (user and reset) +- 512-Mbit Quad-SPI Flash memory +- 128-Mbit SDRAM +- Connector for microSD card +- Wi-Fi or Ext-EEP daughterboard connector +- USB OTG HS with Micro-AB connector +- Ethernet connector compliant with IEEE-802.3-2002 +- Power Over Ethernet based on IEEE 802.3af (Powered Device, 48 V to 5 V, 3 W) +- Power supply output for external applications: 3.3 V or 5 V +- Arduino Uno V3 connectors +- Comprehensive free software including a variety of examples, part of the STM32Cube package +- Supported by a wide choice of integrated development environments + +.. image:: img/stm32f769i_disco.jpg + :align: center + :alt: STM32F769I-DISCO + +More information about the board can be found at the `32F769I-DISCO website`_. + +Hardware +******** + +The STM32F769I Discovery kit provides the following hardware components: + +- STM32F769NIH6 in BGA216 package +- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU +- 216 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 2 MB Flash +- 512 + 16 + 4 KB SRAM +- Flexible external memory controller with up to 32-bit data bus +- Dual mode Quad-SPI +- Chrom-ART Accelerator(DMA2D), graphical hardware accelerator enabling enhanced graphical user interface +- Hardware JPEG codec +- LCD-TFT controller supporting up to XGA resolution +- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- DMA Controller +- General Purpose Timers (15) +- Watchdog Timers (2) +- I2C (4) +- USART/UART (8) +- SPI (6) +- SAI (2) +- CAN (3) +- SDMMC (2) +- SPDIFRX interface +- HDMI-CEC +- MDIO slave interface +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII +- 8- to 14-bit camera interface up to 54 Mbyte/s +- True random number generator +- CRC calculation unit +- RTC: sub-second accuracy, hardware calendar +- 96-bit unique ID + +More information about STM32F769NIH6 can be found here: + +- `STM32F769NIH6 on www.st.com`_ +- `STM32F76xxx reference manual`_ + +Supported Features +================== + +The Zephyr stm32f769i_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | Ethernet | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | flash | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| TOUCH | off-chip | ft5336(FT6202) | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f769i_disco/stm32f769i_disco_defconfig` + +Pin Mapping +=========== + +STM32F769I Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F769I-DISCO board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PC6/PC7 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C4 SCL/SDA : PD12/PB7 (Touchscreen FT6202, PI13 Interrupt Pin) +- SPI2 SCK/MISO/MOSI : PA12/PB14/PB15 (Arduino SPI) +- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 +- LD1 : PJ13 +- LD2 : PJ5 +- LD3 : PA12 +- LD4 : PD4 + +System Clock +============ + +The STM32F769I System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven by the PLL +clock at 216MHz, driven by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32F769I Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 +which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication +settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f769i_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F769I Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to STM32F769I +------------------------------------------- + +First, connect the STM32F769I Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f769i_disco + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f769i_disco + :goals: debug + + +.. _32F769I-DISCO website: + https://www.st.com/en/evaluation-tools/32f769idiscovery.html + +.. _32F769I-DISCO board User Manual: + https://www.st.com/resource/en/user_manual/dm00276557.pdf + +.. _STM32F769NIH6 on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x9/stm32f769ni.html + +.. _STM32F76xxx reference manual: + https://www.st.com/resource/en/reference_manual/dm00224583.pdf diff --git a/boards/arm/stm32f769i_disco/stm32f769i_disco.dts b/boards/st/stm32f769i_disco/stm32f769i_disco.dts similarity index 100% rename from boards/arm/stm32f769i_disco/stm32f769i_disco.dts rename to boards/st/stm32f769i_disco/stm32f769i_disco.dts diff --git a/boards/arm/stm32f769i_disco/stm32f769i_disco.yaml b/boards/st/stm32f769i_disco/stm32f769i_disco.yaml similarity index 100% rename from boards/arm/stm32f769i_disco/stm32f769i_disco.yaml rename to boards/st/stm32f769i_disco/stm32f769i_disco.yaml diff --git a/boards/arm/stm32f769i_disco/stm32f769i_disco_defconfig b/boards/st/stm32f769i_disco/stm32f769i_disco_defconfig similarity index 84% rename from boards/arm/stm32f769i_disco/stm32f769i_disco_defconfig rename to boards/st/stm32f769i_disco/stm32f769i_disco_defconfig index 3a6c65f14b6..c729b83e3d0 100644 --- a/boards/arm/stm32f769i_disco/stm32f769i_disco_defconfig +++ b/boards/st/stm32f769i_disco/stm32f769i_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F769XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f769i_disco/support/openocd.cfg b/boards/st/stm32f769i_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f769i_disco/support/openocd.cfg rename to boards/st/stm32f769i_disco/support/openocd.cfg diff --git a/boards/st/stm32g0316_disco/Kconfig.stm32g0316_disco b/boards/st/stm32g0316_disco/Kconfig.stm32g0316_disco new file mode 100644 index 00000000000..b0f55e7bba7 --- /dev/null +++ b/boards/st/stm32g0316_disco/Kconfig.stm32g0316_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2019 SEAL AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32G0316_DISCO + select SOC_STM32G031XX diff --git a/boards/arm/stm32g0316_disco/board.cmake b/boards/st/stm32g0316_disco/board.cmake similarity index 100% rename from boards/arm/stm32g0316_disco/board.cmake rename to boards/st/stm32g0316_disco/board.cmake diff --git a/boards/st/stm32g0316_disco/board.yml b/boards/st/stm32g0316_disco/board.yml new file mode 100644 index 00000000000..5a67daf81d6 --- /dev/null +++ b/boards/st/stm32g0316_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32g0316_disco + vendor: st + socs: + - name: stm32g031xx diff --git a/boards/arm/stm32g0316_disco/doc/img/stm32g0316_disco.jpg b/boards/st/stm32g0316_disco/doc/img/stm32g0316_disco.jpg similarity index 100% rename from boards/arm/stm32g0316_disco/doc/img/stm32g0316_disco.jpg rename to boards/st/stm32g0316_disco/doc/img/stm32g0316_disco.jpg diff --git a/boards/st/stm32g0316_disco/doc/index.rst b/boards/st/stm32g0316_disco/doc/index.rst new file mode 100644 index 00000000000..6767a115416 --- /dev/null +++ b/boards/st/stm32g0316_disco/doc/index.rst @@ -0,0 +1,134 @@ +.. _stm32g0316_disco_board: + +ST STM32G0316 Discovery +####################### + +Overview +******** + +The STM32G0316-DISCO Discovery kit helps to discover features of STM32G0 in SO8 package. +This discovery kit offers an SO8 to DIL8 module designed with the STM32G031J6 microcontroller +and allows the user to develop applications. It includes an on-board ST-LINK/V2-1 to debug +and program the embedded STM32 microcontroller. + +.. image:: img/stm32g0316_disco.jpg + :align: center + :alt: STM32G0316-DISCO + +Hardware +******** + +- STM32G031J6 Arm |reg| Cortex |reg|-M0+ core-based microcontroller, + featuring 32 Kbytes of Flash memory and 8 Kbytes of SRAM, in an SO8 package +- 1 user LED +- 1 reset/user push-button +- Individual and breakable STM32 SO8 to DIL8 module +- ST-LINK Micro-B USB connector +- DIL8 socket to ease programming of the STM32 MCU +- On-board ST-LINK/V2-1 debugger/programmer + +For more information about the STM32G03x SoC and the STM32G0316-DISCO board, see these ST reference documents: + +- `STM32G031J6 website`_ +- `STM32G031 datasheet`_ +- `STM32G0x1 reference manual`_ +- `STM32G0316-DISCO website`_ + +Supported Features +================== + +The Zephyr stm32g0316_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32g0316_disco/stm32g0316_disco_defconfig` + +Connections and IOs +=================== + +Due to the small number of I/O pins on the SO8 package, multiple die I/Os are bonded +to the same package pins to maximize the number of peripherals which can be used. +Care must be taken not to set two I/Os which are connected together to conflicting +states (e.g. both as outputs, one low, the other high). + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1 TX/RX : PA9/PB7 (pins 5/1) +- USER_PB : PA0 (pin 4) +- LD2 : PA12 (pin 6) + +Programming and Debugging +************************* + +Applications for the ``stm32g0316_disco`` board configuration can be built the +usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). + +Flashing +======== + +The STM32G0316-DISCO board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is not yet supported by the openocd version included in +the Zephyr SDK. Instead, support can be enabled on pyocd by adding "pack" support with +the following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32g031j6 + +Flashing an application to the STM32G0316-DISCO +----------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32g0316_disco + :goals: build flash + +You should see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32g0316_disco + :maybe-skip-config: + :goals: debug + +.. _STM32G031J6 website: + https://www.st.com/en/microcontrollers-microprocessors/stm32g031j6.html + +.. _STM32G031 datasheet: + https://www.st.com/resource/en/datasheet/stm32g031j6.pdf + +.. _STM32G0x1 reference manual: + https://www.st.com/resource/en/reference_manual/dm00371828.pdf + +.. _STM32G0316-DISCO website: + https://www.st.com/en/evaluation-tools/stm32g0316-disco.html diff --git a/boards/arm/stm32g0316_disco/stm32g0316_disco.dts b/boards/st/stm32g0316_disco/stm32g0316_disco.dts similarity index 100% rename from boards/arm/stm32g0316_disco/stm32g0316_disco.dts rename to boards/st/stm32g0316_disco/stm32g0316_disco.dts diff --git a/boards/arm/stm32g0316_disco/stm32g0316_disco.yaml b/boards/st/stm32g0316_disco/stm32g0316_disco.yaml similarity index 100% rename from boards/arm/stm32g0316_disco/stm32g0316_disco.yaml rename to boards/st/stm32g0316_disco/stm32g0316_disco.yaml diff --git a/boards/arm/stm32g0316_disco/stm32g0316_disco_defconfig b/boards/st/stm32g0316_disco/stm32g0316_disco_defconfig similarity index 80% rename from boards/arm/stm32g0316_disco/stm32g0316_disco_defconfig rename to boards/st/stm32g0316_disco/stm32g0316_disco_defconfig index a790e064bf6..f846f1d12a7 100644 --- a/boards/arm/stm32g0316_disco/stm32g0316_disco_defconfig +++ b/boards/st/stm32g0316_disco/stm32g0316_disco_defconfig @@ -1,7 +1,3 @@ -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G031XX=y - # Kernel Options due to Low Memory (8k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/st/stm32g071b_disco/Kconfig.stm32g071b_disco b/boards/st/stm32g071b_disco/Kconfig.stm32g071b_disco new file mode 100644 index 00000000000..78241c936dc --- /dev/null +++ b/boards/st/stm32g071b_disco/Kconfig.stm32g071b_disco @@ -0,0 +1,5 @@ +# Copyright 2021 The Chromium OS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32G071B_DISCO + select SOC_STM32G071XX diff --git a/boards/arm/stm32g071b_disco/board.cmake b/boards/st/stm32g071b_disco/board.cmake similarity index 100% rename from boards/arm/stm32g071b_disco/board.cmake rename to boards/st/stm32g071b_disco/board.cmake diff --git a/boards/st/stm32g071b_disco/board.yml b/boards/st/stm32g071b_disco/board.yml new file mode 100644 index 00000000000..5445391255f --- /dev/null +++ b/boards/st/stm32g071b_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32g071b_disco + vendor: st + socs: + - name: stm32g071xx diff --git a/boards/arm/stm32g071b_disco/doc/img/stm32g071b_disco.jpg b/boards/st/stm32g071b_disco/doc/img/stm32g071b_disco.jpg similarity index 100% rename from boards/arm/stm32g071b_disco/doc/img/stm32g071b_disco.jpg rename to boards/st/stm32g071b_disco/doc/img/stm32g071b_disco.jpg diff --git a/boards/st/stm32g071b_disco/doc/index.rst b/boards/st/stm32g071b_disco/doc/index.rst new file mode 100644 index 00000000000..6047f6d298a --- /dev/null +++ b/boards/st/stm32g071b_disco/doc/index.rst @@ -0,0 +1,169 @@ +.. _stm32g071b_disco_board: + +ST STM32G071B Discovery +####################### + +Overview +******** +The STM32G071B-DISCO Discovery board is a demonstration and development platform +for the STMicroelectronics Arm® Cortex® -M0+ core-based STM32G071RB USB Type-C™ +and Power Delivery microcontroller. The STM32G071B-DISCO Discovery board is +presented with all necessary interfaces for easy connection and +interoperability with other USB Type-C™ devices. The STM32G071B-DISCO Discovery +board is intended for discovery and display of USB Type-C™ port characteristics +such as data role, power role, VBUS and IBUS monitoring. It offers an advanced +user mode when associated with the STM32CubeMonUCPD software GUI and can be used +as a USB Type-C™ and Power Delivery analyzer. + +- STM32G071RBT6 microcontroller featuring 128 Kbytes of Flash memory and + 32 Kbytes of RAM in LQFP64 package +- Plastic case +- 1” 128 x 64 pixels OLED LCD module with SPI interface +- USB Type-C™ interface plug cable and receptacle connector accessible by door + with reed sensor detection +- 3 bidirectional current and power monitors with I2C interface to measure VBUS, + CC1 and CC2 protected and isolated lines +- On-board DC/DC converter to sustain power supply with VBUS varying from 3 V to + 20 V (+/- 5 %) +- 4 user status LEDs about USB Type-C™ configuration +- 3 LEDs for power and ST-LINK communication +- 4-way joystick with selection button +- 1 reset push-button +- Board external connectors: + - USB Type-C™ plug cable + - USB Type-C™ receptacle connector + - 8-pin user extension connector including ADC, SPI, USART and + I2C communication signals + - USB with Micro-AB (ST-LINK) +- Board internal connectors: + - 2 x 8-pin GPIOs free pins from microcontroller + (accessible internally when case is removed) + - USB Type-C™ test points for main signals +- Flexible power-supply options: ST-LINK USB VBUS or USB Type-C™ VBUS +- On-board ST-LINK/V2-1 debugger/programmer with USB enumeration capability: + mass storage, Virtual COM port and debug port + +.. image:: img/stm32g071b_disco.jpg + :align: center + :alt: STM32G071B-DISCO + +More information about the board can be found at the `STM32G071B-DISCO website`_. + + +More information about STM32G071RB can be found here: +- `G071RB on www.st.com`_ +- `STM32G071 reference manual`_ + + +Supported Features +================== + +The Zephyr stm32g071b_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| UCPD | on-chip | ucpd | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32g071b_disco/stm32g071b_disco_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) +- UCPD1 : PA8/PB15 +- BUTTON (JOY_SEL) : PC0 +- BUTTON (JOY_LEFT) : PC1 +- BUTTON (JOY_DOWN) : PC2 +- BUTTON (JOY_RIGHT) : PC3 +- BUTTON (JOY_UP) : PC4 +- LED (TO_REC) : PD9 +- LED (TO_PLUG) : PD8 +- LED (SINK_SPY) : PD5 +- LED (SOURCE) : PC12 +- ENCC1 : PB10 (Enable CC1) +- ENCC2 : PB11 (Enable CC2) +- RDCC1 : PB12 (Enable Door Sense on CC1) + + +For more details please refer to `STM32G0 Discovery board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``stm32g071b_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The STM32G071B Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. + +.. code-block:: console + + $ west flash + +Flashing an application to the STM32G071B_DISCO +----------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32g071b_disco + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32g071b_disco + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32G071B-DISCO website: + https://www.st.com/en/evaluation-tools/stm32g071b-disco.html + +.. _STM32G071 reference manual: + https://www.st.com/resource/en/reference_manual/dm00371828.pdf + +.. _STM32G0 Discovery board User Manual: + https://www.st.com/resource/en/user_manual/dm00496511.pdf + +.. _G071RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32g071rb.html diff --git a/boards/arm/stm32g071b_disco/stm32g071b_disco.dts b/boards/st/stm32g071b_disco/stm32g071b_disco.dts similarity index 100% rename from boards/arm/stm32g071b_disco/stm32g071b_disco.dts rename to boards/st/stm32g071b_disco/stm32g071b_disco.dts diff --git a/boards/arm/stm32g071b_disco/stm32g071b_disco.yaml b/boards/st/stm32g071b_disco/stm32g071b_disco.yaml similarity index 100% rename from boards/arm/stm32g071b_disco/stm32g071b_disco.yaml rename to boards/st/stm32g071b_disco/stm32g071b_disco.yaml diff --git a/boards/arm/stm32g071b_disco/stm32g071b_disco_defconfig b/boards/st/stm32g071b_disco/stm32g071b_disco_defconfig similarity index 85% rename from boards/arm/stm32g071b_disco/stm32g071b_disco_defconfig rename to boards/st/stm32g071b_disco/stm32g071b_disco_defconfig index c4129b26a7f..2554c256697 100644 --- a/boards/arm/stm32g071b_disco/stm32g071b_disco_defconfig +++ b/boards/st/stm32g071b_disco/stm32g071b_disco_defconfig @@ -2,9 +2,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G071XX=y - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/st/stm32g081b_eval/Kconfig.stm32g081b_eval b/boards/st/stm32g081b_eval/Kconfig.stm32g081b_eval new file mode 100644 index 00000000000..0448edcd135 --- /dev/null +++ b/boards/st/stm32g081b_eval/Kconfig.stm32g081b_eval @@ -0,0 +1,5 @@ +# Copyright 2021 The Chromium OS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32G081B_EVAL + select SOC_STM32G081XX diff --git a/boards/arm/stm32g081b_eval/board.cmake b/boards/st/stm32g081b_eval/board.cmake similarity index 100% rename from boards/arm/stm32g081b_eval/board.cmake rename to boards/st/stm32g081b_eval/board.cmake diff --git a/boards/st/stm32g081b_eval/board.yml b/boards/st/stm32g081b_eval/board.yml new file mode 100644 index 00000000000..5cdb22ef9b8 --- /dev/null +++ b/boards/st/stm32g081b_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32g081b_eval + vendor: st + socs: + - name: stm32g081xx diff --git a/boards/arm/stm32g081b_eval/doc/img/stm32g081b_eval.jpg b/boards/st/stm32g081b_eval/doc/img/stm32g081b_eval.jpg similarity index 100% rename from boards/arm/stm32g081b_eval/doc/img/stm32g081b_eval.jpg rename to boards/st/stm32g081b_eval/doc/img/stm32g081b_eval.jpg diff --git a/boards/st/stm32g081b_eval/doc/index.rst b/boards/st/stm32g081b_eval/doc/index.rst new file mode 100644 index 00000000000..5363a2c230a --- /dev/null +++ b/boards/st/stm32g081b_eval/doc/index.rst @@ -0,0 +1,207 @@ +.. _stm32g081b_eval_board: + +ST STM32G081B Evaluation +######################## + +Overview +******** +The STM32G081B-EVAL Evaluation board is a high-end development platform, for +Arm Cortex-M0+ core-based STM32G081RBT6 microcontroller, with USB Type-C and +power delivery controller interfaces (UCPD), compliant with USB type-C r1.2 +and USB PD specification r3.0, two I2Cs, two SPIs, five USARTs, one LP UART, +one 12-bit ADC, two 12-bit DACs, two GP comparators, two LP timers, internal +32 KB SRAM and 128 KB Flash, CEC, SWD debugging support. The full range of +hardware features on the STM32G081B-EVAL Evaluation board includes a mother +board, a legacy peripheral daughterboard and a USB-C and Power Delivery +daughterboard, which help to evaluate all peripherals (USB Type-C connector +with USB PD, motor control connector, RS232, RS485, Audio DAC, microphone ADC, +TFT LCD, IrDA, IR LED, IR receiver, LDR, MicroSD card, CEC on two HDMI +connectors, smart card slot, RF E2PROM & Temperature sensor…), and to develop +applications. + +The board integrates an ST-LINK/V2-1 as an embedded in-circuit debugger and +programmer for the STM32 MCU. The daughterboard and extension connectors +provide an easy way to connect a daughterboard or wrapping board for the +user's specific applications. + +The USB-C and Power Delivery daughterboard +features two independent USB-C ports controlled by an STM32G0. USB-C port 1 +is dual role power (DRP) and can provide up-to 45 W. USB-C Port 2 is sink +only. Both support USB PD protocol and alternate mode functionality. + +Application firmware examples are provided to evaluate the USB-C technology +through various use cases. + + + +- Mother board + - STM32G081RBT6 microcontroller with 128 Kbytes of Flash memory and + 32 Kbytes of RAM in LQFP64 package + - MCU voltage choice fixed 3.3 V or adjustable from 1.65 V to 3.6 V + - I2C compatible serial interface + - RTC with backup battery + - 8-Gbyte or more SPI interface microSD card + - Potentiometer + - 4 color user LEDs and one LED as MCU low-power alarm + - Reset, Tamper and User buttons + - 4-direction control and selection joystick + - Board connectors: + - 5 V power jack + - RS-232 and RS485 communications + - Stereo audio jack including analog microphone input + - microSD card + - Extension I2C connector + - Motor-control connector + - Board extension connectors: + - Daughterboard connectors for legacy peripheral daughter board or + USB-C daughterboard + - Extension connectors for daughterboard or wire-wrap board + - Flexible power-supply options: + - 5 V power jack + - ST-LINK/V2-1 USB connector + - Daughterboard + - On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration + capability: mass storage, virtual COM port and debug port + - Legacy peripheral daughterboard + - IrDA transceiver + - IR LED and IR receiver + - Light dependent resistor (LDR) + - Temperature Sensor + - Board connectors: + - Two HDMI connectors with DDC and CEC + - Smart card slot + - USB-C and Power Delivery daughterboard + - Mux for USB3.1 Gen1 / DisplayPort input and Type-C port1 output + - Mux for Type-C port2 input and DisplayPort output / USB2.0 + - VCONN on Type-C port1 + - USB PD on Type-C port1 + - Board connectors: + - Type-C port1 DRP (dual-role port) + - Type-C port2 Sink + - DisplayPort input + - DisplayPort output + - USB 3.1 Gen1 Type-B receptacle + - USB2.0 Type-A receptacle + - 19 V power jack for USB PD + +.. image:: img/stm32g081b_eval.jpg + :align: center + :alt: STM32G081B-EVAL + +More information about the board can be found at the `STM32G081B-EVAL website`_. + + +More information about STM32G081RB can be found here: +- `G081RB on www.st.com`_ +- `STM32G081 reference manual`_ + + +Supported Features +================== + +The Zephyr stm32g081b_eval board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| UCPD | on-chip + ucpd | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32g081b_eval/stm32g081b_eval_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) +- UCPD2 : PD0/PD2 +- BUTTON (JOY_SEL) : PA0 +- BUTTON (JOY_LEFT) : PC8 +- BUTTON (JOY_DOWN) : PC3 +- BUTTON (JOY_RIGHT) : PC7 +- BUTTON (JOY_UP) : PC2 +- VBUS DISCHARGE : PB14 +- LED1 : PD5 +- LED2 : PD6 +- LED3 : PD8 +- LED4 : PD9 + +For more details please refer to `STM32G0 Evaluation board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``stm32g081b_eval`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The STM32G081B Evaluation board includes an ST-LINK/V2-1 embedded debug tool interface. + +.. code-block:: console + + $ west flash + +Flashing an application to the STM32G081B_EVAL +---------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32g081b_eval + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32g081b_eval + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32G081B-EVAL website: + https://www.st.com/en/evaluation-tools/stm32g081b-eval.html + +.. _STM32G081 reference manual: + https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32G0 Evaluation board User Manual: + https://www.st.com/resource/en/user_manual/um2403-evaluation-board-with-stm32g081rb-mcu-stmicroelectronics.pdf + +.. _G081RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32g081rb.html diff --git a/boards/arm/stm32g081b_eval/stm32g081b_eval.dts b/boards/st/stm32g081b_eval/stm32g081b_eval.dts similarity index 100% rename from boards/arm/stm32g081b_eval/stm32g081b_eval.dts rename to boards/st/stm32g081b_eval/stm32g081b_eval.dts diff --git a/boards/arm/stm32g081b_eval/stm32g081b_eval.yaml b/boards/st/stm32g081b_eval/stm32g081b_eval.yaml similarity index 100% rename from boards/arm/stm32g081b_eval/stm32g081b_eval.yaml rename to boards/st/stm32g081b_eval/stm32g081b_eval.yaml diff --git a/boards/arm/stm32g081b_eval/stm32g081b_eval_defconfig b/boards/st/stm32g081b_eval/stm32g081b_eval_defconfig similarity index 85% rename from boards/arm/stm32g081b_eval/stm32g081b_eval_defconfig rename to boards/st/stm32g081b_eval/stm32g081b_eval_defconfig index cccb164bbcd..2554c256697 100644 --- a/boards/arm/stm32g081b_eval/stm32g081b_eval_defconfig +++ b/boards/st/stm32g081b_eval/stm32g081b_eval_defconfig @@ -2,9 +2,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G081XX=y - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/st/stm32h573i_dk/Kconfig.defconfig b/boards/st/stm32h573i_dk/Kconfig.defconfig new file mode 100644 index 00000000000..b3a733436a9 --- /dev/null +++ b/boards/st/stm32h573i_dk/Kconfig.defconfig @@ -0,0 +1,17 @@ +# STM32H573I DISCOVERY KIT board configuration +# +# Copyright (c) 2023 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_STM32H573I_DK + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_STM32H573I_DK diff --git a/boards/st/stm32h573i_dk/Kconfig.stm32h573i_dk b/boards/st/stm32h573i_dk/Kconfig.stm32h573i_dk new file mode 100644 index 00000000000..633e537e078 --- /dev/null +++ b/boards/st/stm32h573i_dk/Kconfig.stm32h573i_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32H573I_DK + select SOC_STM32H573XX diff --git a/boards/arm/stm32h573i_dk/arduino_r3_connector.dtsi b/boards/st/stm32h573i_dk/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32h573i_dk/arduino_r3_connector.dtsi rename to boards/st/stm32h573i_dk/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32h573i_dk/board.cmake b/boards/st/stm32h573i_dk/board.cmake similarity index 100% rename from boards/arm/stm32h573i_dk/board.cmake rename to boards/st/stm32h573i_dk/board.cmake diff --git a/boards/st/stm32h573i_dk/board.yml b/boards/st/stm32h573i_dk/board.yml new file mode 100644 index 00000000000..e6a08a9197f --- /dev/null +++ b/boards/st/stm32h573i_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32h573i_dk + vendor: st + socs: + - name: stm32h573xx diff --git a/boards/arm/stm32h573i_dk/doc/img/stm32h573i_dk.jpg b/boards/st/stm32h573i_dk/doc/img/stm32h573i_dk.jpg similarity index 100% rename from boards/arm/stm32h573i_dk/doc/img/stm32h573i_dk.jpg rename to boards/st/stm32h573i_dk/doc/img/stm32h573i_dk.jpg diff --git a/boards/st/stm32h573i_dk/doc/index.rst b/boards/st/stm32h573i_dk/doc/index.rst new file mode 100644 index 00000000000..f7e0a7adbbe --- /dev/null +++ b/boards/st/stm32h573i_dk/doc/index.rst @@ -0,0 +1,326 @@ +.. _stm32h573i_dk_board: + +ST STM32H573I-DK Discovery +########################## + +Overview +******** + +The STM32H573I-DK Discovery kit is designed as a complete demonstration and +development platform for STMicroelectronics Arm |reg| Cortex |reg|-M33 core-based +STM32H573IIK3Q microcontroller with TrustZone |reg|. Here are some highlights of +the STM32H573I-DK Discovery board: + + +- STM32H573IIK3Q microcontroller featuring 2 Mbytes of Flash memory and 640 Kbytes of SRAM in 176-pin BGA package +- 1.54-inch 240x240 pixels TFT-LCD with LED backlight and touch panel +- USB Type-C |trade| Host and device with USB power-delivery controller +- SAI Audio DAC stereo with one audio jacks for input/output, +- ST MEMS digital microphone with PDM interface +- Octo-SPI interface connected to 512Mbit Octo-SPI NORFlash memory device (MX25LM51245GXDI00 from MACRONIX) +- 10/100-Mbit Ethernet, +- microSD |trade| +- A Wi‑Fi® add-on board +- Board connectors + + - STMod+ expansion connector with fan-out expansion board for Wi‑Fi |reg|, Grove and mikroBUS |trade| compatible connectors + - Pmod |trade| expansion connector + - Audio MEMS daughterboard expansion connector + - ARDUINO |reg| Uno V3 expansion connector + +- Flexible power-supply options + + - ST-LINK + - USB VBUS + - external sources + +- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: + + - mass storage + - Virtual COM port + - debug port + +- 4 user LEDs +- User and reset push-buttons + +.. image:: img/stm32h573i_dk.jpg + :align: center + :alt: STM32H573I-DK Discovery + +More information about the board can be found at the `STM32H573I-DK Discovery website`_. + +Hardware +******** + +The STM32H573xx devices are an high-performance microcontrollers family (STM32H5 +Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. +They operate at a frequency of up to 250 MHz. + +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 375 DMPIS/MHz (Dhrystone 2.1) + +- Security + + - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension + - Up to 8 configurable SAU regions + - TrustZone |reg| aware and securable peripherals + - Flexible lifecycle scheme with secure debug authentication + - Preconfigured immutable root of trust (ST-iROT) + - SFI (secure firmware installation) + - Secure data storage with hardware unique key (HUK) + - Secure firmware upgrade support with TF-M + - 2x AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - True random number generator, NIST SP800-90B compliant + - 96-bit unique ID + - Active tampers + - True Random Number Generator (RNG) NIST SP800-90B compliant + +- Clock management: + + - 25 MHz crystal oscillator (HSE) + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 64 MHz (HSI) trimmable by software + - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) + - Internal 4 MHz oscillator (CSI), trimmable by software + - Internal 48 MHz (HSI48) with recovery system + - 3 PLLs for system clock, USB, audio, ADC + +- Power management + + - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry + - Embedded SMPS step-down converter + +- RTC with HW calendar, alarms and calibration +- Up to 139 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V +- Up to 16 timers and 2 watchdogs + + - 12x 16-bit + - 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 6x 16-bit low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- Memories + + - Up to 2 MB Flash, 2 banks read-while-write + - 1 Kbyte OTP (one-time programmable) + - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC + - 4 Kbytes of backup SRAM available in the lowest power modes + - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories + - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats + - 2x SD/SDIO/MMC interfaces + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC with up to 5 MSPS in 12-bit + - 2x 12-bit D/A converters + - 1x Digital temperature sensor + +- 34x communication interfaces + + - 1x USB Type-C / USB power-delivery controller + - 1x USB 2.0 full-speed host and device + - 4x I2C FM+ interfaces (SMBus/PMBus) + - 1x I3C interface + - 12x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) + - 1x LP UART + - 6x SPIs including 3 muxed with full-duplex I2S + - 5x additional SPI from 5x USART when configured in Synchronous mode + - 2x SAI + - 2x FDCAN + - 1x SDMMC interface + - 2x 16 channel DMA controllers + - 1x 8- to 14- bit camera interface + - 1x HDMI-CEC + - 1x Ethernel MAC interface with DMA controller + - 1x 16-bit parallel slave synchronous-interface + +- CORDIC for trigonometric functions acceleration +- FMAC (filter mathematical accelerator) +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32H573 can be found here: + +- `STM32H573 on www.st.com`_ +- `STM32H573 reference manual`_ + +Supported Features +================== + +The Zephyr STM32H573I_DK board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | Real Time Clock | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi bus | ++-----------+------------+-------------------------------------+ +| OCTOSPI | on-chip | octospi | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can bus | ++-----------+------------+-------------------------------------+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB full-speed host/device bus | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig and dts files: + +- Secure target: + + - :zephyr_file:`boards/st/stm32h573i_dk/stm32h573i_dk_defconfig` + - :zephyr_file:`boards/st/stm32h573i_dk/stm32h573i_dk.dts` + +Zephyr board options +==================== + +The STM32H573 is an SoC with Cortex-M33 architecture. Zephyr provides support +for building for Secure firmware. + +The BOARD options are summarized below: + ++----------------------+-----------------------------------------------+ +| BOARD | Description | ++======================+===============================================+ +| stm32h573i_dk | For building Secure firmware | ++----------------------+-----------------------------------------------+ + +Connections and IOs +=================== + +STM32H573I-DK Discovery Board has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32H573I-DK Discovery board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART_1 TX/RX : PA9/PA10 (VCP) +- USART_3 TX/RX : PB11/PB10 (Arduino USART3) +- USER_PB : PC13 +- LD1 (green) : PI9 +- DAC1 channel 1 output : PA4 +- ADC1 channel 6 input : PF12 + +System Clock +------------ + +STM32H573I-DK System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +240MHz, driven by 25MHz external oscillator (HSE). + +Serial Port +----------- + +STM32H573I-DK Discovery board has 3 U(S)ARTs. The Zephyr console output is +assigned to USART1. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``stm32h573i_dk`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32H573I-DK Discovery board includes an ST-LINK/V3E embedded debug tool +interface. Support is available on STM32CubeProgrammer V2.13.0. + +Alternatively, this interface will be supported by a next openocd version. + +Flashing an application to STM32H573I-DK Discovery +-------------------------------------------------- + +Connect the STM32H573I-DK Discovery to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h573i_dk + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! stm32h573i_dk + +Debugging +========= + +Waiting for openocd support, debugging could be performed with pyocd which +requires to enable "pack" support with the following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32h5 + +Once installed, you can debug an application in the usual way. Here is an +example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h573i_dk + :maybe-skip-config: + :goals: debug + +.. _STM32H573I-DK Discovery website: + https://www.st.com/en/evaluation-tools/stm32h573i-dk.html + +.. _STM32H573I-DK Discovery board User Manual: + https://www.st.com/en/evaluation-tools/stm32h573i-dk.html + +.. _STM32H573 on www.st.com: + https://www.st.com/en/microcontrollers/stm32h573ii.html + +.. _STM32H573 reference manual: + https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts similarity index 100% rename from boards/arm/stm32h573i_dk/stm32h573i_dk.dts rename to boards/st/stm32h573i_dk/stm32h573i_dk.dts diff --git a/boards/arm/stm32h573i_dk/stm32h573i_dk.yaml b/boards/st/stm32h573i_dk/stm32h573i_dk.yaml similarity index 100% rename from boards/arm/stm32h573i_dk/stm32h573i_dk.yaml rename to boards/st/stm32h573i_dk/stm32h573i_dk.yaml diff --git a/boards/arm/stm32h573i_dk/stm32h573i_dk_defconfig b/boards/st/stm32h573i_dk/stm32h573i_dk_defconfig similarity index 87% rename from boards/arm/stm32h573i_dk/stm32h573i_dk_defconfig rename to boards/st/stm32h573i_dk/stm32h573i_dk_defconfig index a8050bc4e82..c112d04baa0 100644 --- a/boards/arm/stm32h573i_dk/stm32h573i_dk_defconfig +++ b/boards/st/stm32h573i_dk/stm32h573i_dk_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2023 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H5X=y -CONFIG_SOC_STM32H573XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/st/stm32h735g_disco/Kconfig.defconfig b/boards/st/stm32h735g_disco/Kconfig.defconfig new file mode 100644 index 00000000000..9c3777487a3 --- /dev/null +++ b/boards/st/stm32h735g_disco/Kconfig.defconfig @@ -0,0 +1,19 @@ +# STM32H735G DISCOVERY board configuration + +# Copyright (c) 2021 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32H735G_DISCO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_STM32H735G_DISCO diff --git a/boards/st/stm32h735g_disco/Kconfig.stm32h735g_disco b/boards/st/stm32h735g_disco/Kconfig.stm32h735g_disco new file mode 100644 index 00000000000..f2284afee88 --- /dev/null +++ b/boards/st/stm32h735g_disco/Kconfig.stm32h735g_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2021 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32H735G_DISCO + select SOC_STM32H735XX diff --git a/boards/st/stm32h735g_disco/board.cmake b/boards/st/stm32h735g_disco/board.cmake new file mode 100644 index 00000000000..b4beb22525d --- /dev/null +++ b/boards/st/stm32h735g_disco/board.cmake @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2021 SILA Embedded Solutions GmbH + +board_runner_args(jlink "--device=STM32H735IG" "--speed=4000") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h735g_disco/board.yml b/boards/st/stm32h735g_disco/board.yml new file mode 100644 index 00000000000..146a622647e --- /dev/null +++ b/boards/st/stm32h735g_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32h735g_disco + vendor: st + socs: + - name: stm32h735xx diff --git a/boards/arm/stm32h735g_disco/doc/img/stm32h735g_disco.jpg b/boards/st/stm32h735g_disco/doc/img/stm32h735g_disco.jpg similarity index 100% rename from boards/arm/stm32h735g_disco/doc/img/stm32h735g_disco.jpg rename to boards/st/stm32h735g_disco/doc/img/stm32h735g_disco.jpg diff --git a/boards/st/stm32h735g_disco/doc/index.rst b/boards/st/stm32h735g_disco/doc/index.rst new file mode 100644 index 00000000000..bf7605d7766 --- /dev/null +++ b/boards/st/stm32h735g_disco/doc/index.rst @@ -0,0 +1,152 @@ +.. _stm32h735g_disco_board: + +ST STM32H735G Discovery +####################### + +Overview +******** + +The STM32H735G-DK Discovery kit is a complete demonstration and development +platform for Arm® Cortex®-M7 core-based STM32H735IGK6U microcontroller, with +1 Mbyte of Flash memory and 564 Kbytes of SRAM. + +The STM32H735G-DK Discovery kit is used as a reference design for user +application development before porting to the final product, thus simplifying +the application development. + +The full range of hardware features available on the board helps users to enhance +their application development by an evaluation of all the peripherals (such as +USB OTG FS, Ethernet, microSD™ card, USART, CAN FD, SAI audio DAC stereo with +audio jack input and output, MEMS digital microphone, HyperRAM™, +Octo-SPI Flash memory, RGB interface LCD with capacitive touch panel, and others). +ARDUINO® Uno V3, Pmod™ and STMod+ connectors provide easy connection to extension +shields or daughterboards for specific applications. + +STLINK-V3E is integrated into the board, as the embedded in-circuit debugger and +programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H735G-DK board +comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive +software HAL library as well as various software examples. + +.. image:: img/stm32h735g_disco.jpg + :align: center + :alt: STM32H735G-DISCO + +More information about the board can be found at the `STM32H735G-DISCO website`_. +More information about STM32H735 can be found here: + +- `STM32H725/735 on www.st.com`_ +- `STM32H735xx reference manual`_ +- `STM32H735xx datasheet`_ + +Supported Features +================== + +The current Zephyr stm32h735g_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| FDCAN1 | on-chip | CAN-FD Controller | ++-----------+------------+-------------------------------------+ +| FDCAN2 | on-chip | CAN-FD Controller | ++-----------+------------+-------------------------------------+ +| FDCAN2 | on-chip | CAN-FD Controller (disabled by | +| | | default. Solder bridges SB29 and | +| | | SB30 need to be closed for FDCAN3 | +| | | to work) | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32h735g_disco/stm32h735g_disco_defconfig` + +Pin Mapping +=========== + +For more details please refer to `STM32H735G-DISCO website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_7 TX/RX : PF7/PF6 (Arduino Serial) +- LD1 : PC2 +- LD2 : PC3 +- FDCAN1 : CAN + +System Clock +============ + +The STM32H735G System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock +is driven by the PLL clock at 550MHz. PLL clock is feed by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32H735G Discovery kit has up to 6 UARTs. +The Zephyr console output is assigned to UART3 which connected to the onboard ST-LINK/V3.0. Virtual +COM port interface. Default communication settings are 115200 8N1. + + +Programming and Debugging +************************* + +See :ref:`build_an_application` for more information about application builds. + + +Flashing +======== + +Flashing operation will depend on the target to be flashed and the SoC +option bytes configuration. +It is advised to use `STM32CubeProgrammer`_ to check and update option bytes +configuration and flash the ``stm32h735g_disco`` target. + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h735g_disco + :goals: debug + + +.. _STM32H735G-DISCO website: + https://www.st.com/en/evaluation-tools/stm32h735g-dk.html + +.. _STM32H725/735 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h725-735.html + +.. _STM32H735xx reference manual: + https://www.st.com/resource/en/reference_manual/dm00603761-stm32h723733-stm32h725735-and-stm32h730-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32H735xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h735ag.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32h735g_disco/pmod_connector.dtsi b/boards/st/stm32h735g_disco/pmod_connector.dtsi similarity index 100% rename from boards/arm/stm32h735g_disco/pmod_connector.dtsi rename to boards/st/stm32h735g_disco/pmod_connector.dtsi diff --git a/boards/arm/stm32h735g_disco/stm32h735g_disco.dts b/boards/st/stm32h735g_disco/stm32h735g_disco.dts similarity index 100% rename from boards/arm/stm32h735g_disco/stm32h735g_disco.dts rename to boards/st/stm32h735g_disco/stm32h735g_disco.dts diff --git a/boards/arm/stm32h735g_disco/stm32h735g_disco.yaml b/boards/st/stm32h735g_disco/stm32h735g_disco.yaml similarity index 100% rename from boards/arm/stm32h735g_disco/stm32h735g_disco.yaml rename to boards/st/stm32h735g_disco/stm32h735g_disco.yaml diff --git a/boards/arm/stm32h735g_disco/stm32h735g_disco_defconfig b/boards/st/stm32h735g_disco/stm32h735g_disco_defconfig similarity index 76% rename from boards/arm/stm32h735g_disco/stm32h735g_disco_defconfig rename to boards/st/stm32h735g_disco/stm32h735g_disco_defconfig index d8c7d4e78d0..fe5e1092729 100644 --- a/boards/arm/stm32h735g_disco/stm32h735g_disco_defconfig +++ b/boards/st/stm32h735g_disco/stm32h735g_disco_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H735XX=y +# Copyright (c) 2021 SILA Embedded Solutions GmbH # Enable the internal SMPS regulator CONFIG_POWER_SUPPLY_DIRECT_SMPS=y @@ -14,15 +12,15 @@ CONFIG_HW_STACK_PROTECTION=y CONFIG_SERIAL=y -# console +# Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y # Enable Clocks CONFIG_CLOCK_CONTROL=y -# enable pin controller +# Enable pin controller CONFIG_PINCTRL=y diff --git a/boards/arm/stm32h735g_disco/support/openocd.cfg b/boards/st/stm32h735g_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32h735g_disco/support/openocd.cfg rename to boards/st/stm32h735g_disco/support/openocd.cfg diff --git a/boards/arm/stm32h747i_disco/CMakeLists.txt b/boards/st/stm32h747i_disco/CMakeLists.txt similarity index 100% rename from boards/arm/stm32h747i_disco/CMakeLists.txt rename to boards/st/stm32h747i_disco/CMakeLists.txt diff --git a/boards/st/stm32h747i_disco/Kconfig.defconfig b/boards/st/stm32h747i_disco/Kconfig.defconfig new file mode 100644 index 00000000000..68e0fc0b4a0 --- /dev/null +++ b/boards/st/stm32h747i_disco/Kconfig.defconfig @@ -0,0 +1,18 @@ +# STM32H747I DISCOVERY board configuration + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32H747I_DISCO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_STM32H747I_DISCO diff --git a/boards/st/stm32h747i_disco/Kconfig.stm32h747i_disco b/boards/st/stm32h747i_disco/Kconfig.stm32h747i_disco new file mode 100644 index 00000000000..8c6309f909a --- /dev/null +++ b/boards/st/stm32h747i_disco/Kconfig.stm32h747i_disco @@ -0,0 +1,8 @@ +# STM32H747I DISCOVERY board configuration + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32H747I_DISCO + select SOC_STM32H747XX_M7 if BOARD_STM32H747I_DISCO_STM32H747XX_M7 + select SOC_STM32H747XX_M4 if BOARD_STM32H747I_DISCO_STM32H747XX_M4 diff --git a/boards/arm/stm32h747i_disco/arduino_r3_connector.dtsi b/boards/st/stm32h747i_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32h747i_disco/arduino_r3_connector.dtsi rename to boards/st/stm32h747i_disco/arduino_r3_connector.dtsi diff --git a/boards/st/stm32h747i_disco/board.cmake b/boards/st/stm32h747i_disco/board.cmake new file mode 100644 index 00000000000..93b40d3634d --- /dev/null +++ b/boards/st/stm32h747i_disco/board.cmake @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 STMicroelectronics + +if(CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M7) + board_runner_args(jlink "--device=STM32H747ZI_M7") + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m7.cfg") + board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +elseif(CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M4) + board_runner_args(jlink "--device=STM32H747ZI_M4") + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m4.cfg") + board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) +endif() +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h747i_disco/board.yml b/boards/st/stm32h747i_disco/board.yml new file mode 100644 index 00000000000..431d3e4f486 --- /dev/null +++ b/boards/st/stm32h747i_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32h747i_disco + vendor: st + socs: + - name: stm32h747xx diff --git a/boards/arm/stm32h747i_disco/dc_ram.ld b/boards/st/stm32h747i_disco/dc_ram.ld similarity index 100% rename from boards/arm/stm32h747i_disco/dc_ram.ld rename to boards/st/stm32h747i_disco/dc_ram.ld diff --git a/boards/arm/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_1.jpg b/boards/st/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_1.jpg similarity index 100% rename from boards/arm/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_1.jpg rename to boards/st/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_1.jpg diff --git a/boards/arm/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_2.jpg b/boards/st/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_2.jpg similarity index 100% rename from boards/arm/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_2.jpg rename to boards/st/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_2.jpg diff --git a/boards/arm/stm32h747i_disco/doc/img/stm32h747i_disco.jpg b/boards/st/stm32h747i_disco/doc/img/stm32h747i_disco.jpg similarity index 100% rename from boards/arm/stm32h747i_disco/doc/img/stm32h747i_disco.jpg rename to boards/st/stm32h747i_disco/doc/img/stm32h747i_disco.jpg diff --git a/boards/st/stm32h747i_disco/doc/index.rst b/boards/st/stm32h747i_disco/doc/index.rst new file mode 100644 index 00000000000..1f6846d6815 --- /dev/null +++ b/boards/st/stm32h747i_disco/doc/index.rst @@ -0,0 +1,314 @@ +.. _stm32h747i_disco_board: + +ST STM32H747I Discovery +####################### + +Overview +******** + +The discovery kit enables a wide diversity of applications taking benefit +from audio, multi-sensor support, graphics, security, video, +and high-speed connectivity features. + +The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU, +with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, +large set of peripherals, SMPS, and MIPI-DSI. + +Additionally, the board features: + +- On-board ST-LINK/V3E supporting USB reenumeration capability +- USB ST-LINK functions: virtual COM port, mass storage, debug port +- Flexible power-supply options: + + - ST-LINK USB VBUS, USB OTG HS connector, or external sources + +- 4” capacitive touch LCD display module with MIPI® DSI interface +- Ethernet compliant with IEEE802.3-2002 +- USB OTG HS +- Stereo speaker outputs +- ST-MEMS digital microphones +- 2 x 512-Mbit QUAD-SPI NOR Flash memory +- 256-Mbit SDRAM +- 4 color user LEDs +- 1 user and reset push-button +- 4-direction joystick with selection button +- Arduino Uno V3 connectors + +.. image:: img/stm32h747i_disco.jpg + :align: center + :alt: STM32H747I-DISCO + +More information about the board can be found at the `STM32H747I-DISCO website`_. +More information about STM32H747XIH6 can be found here: + +- `STM32H747XI on www.st.com`_ +- `STM32H747xx reference manual`_ +- `STM32H747xx datasheet`_ + +Supported Features +================== + +The current Zephyr stm32h747i_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet (*) | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| IPM | on-chip | virtual mailbox based on HSEM | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | MIPI DSI Host with shield (MP1166) | +| | | st_b_lcd40_dsi1_mb1166 | ++-----------+------------+-------------------------------------+ + +(*) From UM2411 Rev 4: + With the default setting, the Ethernet feature is not working because of + a conflict between ETH_MDC and SAI4_D1 of the MEMs digital microphone. + Make sure you have SB8 closed and SB21 open to get Ethernet working. + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration per core can be found in the defconfig files: +:zephyr_file:`boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig` and +:zephyr_file:`boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig` + +Pin Mapping +=========== + +STM32H747I Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32H747I-DISCO website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) +- UART_8 TX/RX : PJ8/PJ9 (Arduino Serial) +- SPI_5 NSS/SCK/MISO/MOSI : PK1/PK0/PJ11/PJ10 (Arduino SPI) +- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2 +- LD1 : PI12 +- LD2 : PI13 +- LD3 : PI14 +- LD4 : PI15 +- W-UP : PC13 +- J-CENTER : PK2 +- J-DOWN : PK3 +- J-LEFT : PK4 +- J-RIGHT : PK5 +- J-UP : PK6 + +System Clock +============ + +The STM32H747I System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the CPU1 (Cortex-M7) System clock +is driven by the PLL clock at 400MHz, and the CPU2 (Cortex-M4) System clock +is driven at 200MHz. PLL clock is feed by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32H747I Discovery kit has up to 8 UARTs. +Default configuration assigns USART1 and UART8 to the CPU1. The Zephyr console +output is assigned to UART1 which connected to the onboard ST-LINK/V3.0. Virtual +COM port interface. Default communication settings are 115200 8N1. + +Ethernet +======== + +**Disclaimer:** This section is mostly copy-paste of corresponding +`DISCO_H747I modifications for Ethernet`_ mbed blog post. The author of this +article sincerely allowed to use the images and his knowledge about necessary +HW modifications to get Ethernet working with this board. + +To get Ethernet working following HW modifications are required: + +- **SB21**, **SB45** and **R87** should be opened +- **SB22**, **SB44**, **SB17** and **SB8** should be closed + +Following two images shows necessary changes on the board marked: + +.. image:: img/disco_h747i_ethernet_modification_1.jpg + :align: center + :alt: STM32H747I-DISCO - Ethernet modification 1 (**SB44**, **SB45**) + +.. image:: img/disco_h747i_ethernet_modification_2.jpg + :align: center + :alt: STM32H747I-DISCO - Ethernet modification 2 (**SB21**, **R87**, **SB22**, **SB17** and **SB8**) + +Display +======= + +The STM32H747I Discovery kit has a dedicated DSI LCD connector **CN15**, where +the MB1166 (B-LCD40-DSI1) display extension board can be mounted. Enable display +support in Zephyr by adding the shield ``st_b_lcd40_dsi1_mb1166`` to your build +command, for example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/display + :board: stm32h747i_disco/stm32h747xx/m7 + :shield: st_b_lcd40_dsi1_mb1166 + :goals: build flash + +.. note:: + Currently only the older version MB1166-A03 is supported by Zephyr. + The newer version MB1166-A09 does not get initialized correctly (see :github:`60888`). + +Resources sharing +================= + +The dual core nature of STM32H747 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Programming and Debugging +************************* + +Applications for the ``stm32h747i_disco`` board should be built per core target, +using either ``stm32h747i_disco/stm32h747xx/m7`` or ```stm32h747i_disco/stm32h747xx/m4`` as the target. +See :ref:`build_an_application` for more information about application builds. + +.. note:: + + If using OpenOCD you will need a recent development version as the last + official release does not support H7 dualcore yet. + Also, with OpenOCD, sometimes, flashing is not working. It is necessary to + erase the flash (with STM32CubeProgrammer for example) to make it work again. + Debugging with OpenOCD is currently working for this board only with Cortex M7, + not Cortex M4. + + +Flashing +======== + +Flashing operation will depend on the target to be flashed and the SoC +option bytes configuration. +It is advised to use `STM32CubeProgrammer`_ to check and update option bytes +configuration and flash ``stm32h747i_disco/stm32h747xx/m7`` and +``stm32h747i_disco/stm32h747xx/m7`` targets. + +By default: + + - CPU1 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0) + - CPU2 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0) + +Also, default out of the box board configuration enables CM7 and CM4 boot when +board is powered (Option bytes BCM7 and BCM4 are checked). +It is possible to change Option Bytes so that CM7 boots first in stand alone, +and CM7 will wakeup CM4 after clock initialization. +Drivers are able to take into account both Option Bytes configurations +automatically. + +Zephyr flash configuration has been set to meet these default settings. + +Alternatively, west `STM32CubeProgrammer`_ runner can be used, after installing +it, to flash applications for both cores. The target core is detected automatically. + +.. code-block:: console + + $ west flash --runner stm32cubeprogrammer + +Flashing an application to STM32H747I M7 Core +--------------------------------------------- + +First, connect the STM32H747I Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h747i_disco/stm32h747xx/m7 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! stm32h747i_disco + +.. note:: + Sometimes, flashing is not working. It is necessary to erase the flash + (with STM32CubeProgrammer for example) to make it work again. + +Similarly, you can build and flash samples on the M4 target. For this, please +take care of the resource sharing (UART port used for console for instance). + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32h747i_disco/stm32h747xx/m7 + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h747i_disco/stm32h747xx/m7 + :goals: debug + +Debugging with west is currently not available on Cortex M4 side. +In order to debug a Zephyr application on Cortex M4 side, you can use +`STM32CubeIDE`_. + +.. _STM32H747I-DISCO website: + https://www.st.com/en/evaluation-tools/stm32h747i-disco.html + +.. _STM32H747XI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html + +.. _STM32H747xx reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879.pdf + +.. _STM32H747xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h747xi.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _DISCO_H747I modifications for Ethernet: + https://os.mbed.com/teams/ST/wiki/DISCO_H747I-modifications-for-Ethernet + +.. _STM32CubeIDE: + https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/stm32h747i_disco/pmod_connector.dtsi b/boards/st/stm32h747i_disco/pmod_connector.dtsi similarity index 100% rename from boards/arm/stm32h747i_disco/pmod_connector.dtsi rename to boards/st/stm32h747i_disco/pmod_connector.dtsi diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco.dtsi b/boards/st/stm32h747i_disco/stm32h747i_disco.dtsi similarity index 100% rename from boards/arm/stm32h747i_disco/stm32h747i_disco.dtsi rename to boards/st/stm32h747i_disco/stm32h747i_disco.dtsi diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m4.dts b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.dts similarity index 100% rename from boards/arm/stm32h747i_disco/stm32h747i_disco_m4.dts rename to boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.dts diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.yaml b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.yaml new file mode 100644 index 00000000000..2a544e16701 --- /dev/null +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.yaml @@ -0,0 +1,19 @@ +identifier: stm32h747i_disco/stm32h747xx/m4 +name: ST STM32H747I Discovery (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 288 +flash: 1024 +supported: + - arduino_gpio + - gpio +testing: + ignore_tags: + - mpu + - nfc + - net +vendor: st diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig new file mode 100644 index 00000000000..9b540e01f63 --- /dev/null +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 STMicroelectronics + +# Enable GPIO +CONFIG_GPIO=y + +# Clock configuration +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# By default CONSOLE is assigned to m7 +#CONFIG_CONSOLE=y +#CONFIG_UART_CONSOLE=y + +# Enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts similarity index 100% rename from boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts rename to boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml new file mode 100644 index 00000000000..e4b7d1b3334 --- /dev/null +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml @@ -0,0 +1,21 @@ +identifier: stm32h747i_disco/stm32h747xx/m7 +name: ST STM32H747I Discovery (M7) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 1024 +supported: + - arduino_gpio + - gpio + - arduino_spi + - spi + - netif:eth + - qspi + - memc + - usb_cdc + - usb_device +vendor: st diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig new file mode 100644 index 00000000000..69659b1c01e --- /dev/null +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 STMicroelectronics + +# Enable the internal SMPS regulator +CONFIG_POWER_SUPPLY_DIRECT_SMPS=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable clocks +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Disable following to assign serial ports to m4 core + +# Enable uart driver +CONFIG_SERIAL=y +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm32h747i_disco/support/openocd_stm32h747i_disco_m4.cfg b/boards/st/stm32h747i_disco/support/openocd_stm32h747i_disco_m4.cfg similarity index 100% rename from boards/arm/stm32h747i_disco/support/openocd_stm32h747i_disco_m4.cfg rename to boards/st/stm32h747i_disco/support/openocd_stm32h747i_disco_m4.cfg diff --git a/boards/arm/stm32h747i_disco/support/openocd_stm32h747i_disco_m7.cfg b/boards/st/stm32h747i_disco/support/openocd_stm32h747i_disco_m7.cfg similarity index 100% rename from boards/arm/stm32h747i_disco/support/openocd_stm32h747i_disco_m7.cfg rename to boards/st/stm32h747i_disco/support/openocd_stm32h747i_disco_m7.cfg diff --git a/boards/st/stm32h750b_dk/Kconfig.stm32h750b_dk b/boards/st/stm32h750b_dk/Kconfig.stm32h750b_dk new file mode 100644 index 00000000000..b141d9d1b9d --- /dev/null +++ b/boards/st/stm32h750b_dk/Kconfig.stm32h750b_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32H750B_DK + select SOC_STM32H750XX diff --git a/boards/arm/stm32h750b_dk/arduino_r3_connector.dtsi b/boards/st/stm32h750b_dk/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32h750b_dk/arduino_r3_connector.dtsi rename to boards/st/stm32h750b_dk/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32h735g_disco/board.cmake b/boards/st/stm32h750b_dk/board.cmake similarity index 100% rename from boards/arm/stm32h735g_disco/board.cmake rename to boards/st/stm32h750b_dk/board.cmake diff --git a/boards/st/stm32h750b_dk/board.yml b/boards/st/stm32h750b_dk/board.yml new file mode 100644 index 00000000000..95275ee2e42 --- /dev/null +++ b/boards/st/stm32h750b_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32h750b_dk + vendor: st + socs: + - name: stm32h750xx diff --git a/boards/arm/stm32h750b_dk/doc/img/stm32h750b_dk.png b/boards/st/stm32h750b_dk/doc/img/stm32h750b_dk.png similarity index 100% rename from boards/arm/stm32h750b_dk/doc/img/stm32h750b_dk.png rename to boards/st/stm32h750b_dk/doc/img/stm32h750b_dk.png diff --git a/boards/st/stm32h750b_dk/doc/index.rst b/boards/st/stm32h750b_dk/doc/index.rst new file mode 100644 index 00000000000..f295947a334 --- /dev/null +++ b/boards/st/stm32h750b_dk/doc/index.rst @@ -0,0 +1,145 @@ +.. _stm32h750b_dk_board: + +ST STM32H750B Discovery Kit +########################### + +Overview +******** + +The STM32H750B-DK Discovery kit is a complete demonstration and development +platform for Arm® Cortex®-M7 core-based STM32H750XBH6 microcontroller, with +128Kbytes of Flash memory and 1 Mbytes of SRAM. + +The STM32H750B-DK Discovery kit is used as a reference design for user +application development before porting to the final product, thus simplifying +the application development. + +The full range of hardware features available on the board helps users to enhance +their application development by an evaluation of all the peripherals (such as +USB OTG FS, Ethernet, microSD™ card, USART, CAN FD, SAI audio DAC stereo with +audio jack input and output, MEMS digital microphone, HyperRAM™, +Octo-SPI Flash memory, RGB interface LCD with capacitive touch panel, and others). +ARDUINO® Uno V3, Pmod™ and STMod+ connectors provide easy connection to extension +shields or daughterboards for specific applications. + +STLINK-V3E is integrated into the board, as the embedded in-circuit debugger and +programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H750B-DK board +comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive +software HAL library as well as various software examples. + +.. image:: img/stm32h750b_dk.png + :align: center + :alt: STM32H750B-DK + +More information about the board can be found at the `STM32H750B-DK website`_. +More information about STM32H750 can be found here: + +- `STM32H750 on www.st.com`_ +- `STM32H750xx reference manual`_ +- `STM32H750xx datasheet`_ + +Supported Features +================== + +The current Zephyr stm32h750b_dk board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32h750b_dk/stm32h750b_dk_defconfig` + +Pin Mapping +=========== + +For more details please refer to `STM32H750B-DK website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PB10/PB11 (ST-Link Virtual Port Com) +- LD1 : PJ2 +- LD2 : PI13 + +System Clock +============ + +The STM32H750B System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock +is driven by the PLL clock at 480MHz. PLL clock is feed by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32H750B Discovery kit has up to 6 UARTs. +The Zephyr console output is assigned to UART3 which connected to the onboard ST-LINK/V3.0. Virtual +COM port interface. Default communication settings are 115200 8N1. + + +Programming and Debugging +************************* + +See :ref:`build_an_application` for more information about application builds. + + +Flashing +======== + +Connect the STM32H750B-DK to your host computer using the ST-LINK +USB port, then run a serial host program to connect with the board. For example: + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +You can then build and flash applications in the usual way. +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h750b_dk + :goals: build flash + +You should see the following message in the serial host program: + +.. code-block:: console + + $ Hello World! stm32h750b_dk + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h750b_dk + :goals: debug + + +.. _STM32H750B-DK website: + https://www.st.com/en/evaluation-tools/stm32h750b-dk.html + +.. _STM32H750 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html + +.. _STM32H750xx reference manual: + https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32H750xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h750ib.pdf diff --git a/boards/arm/stm32h750b_dk/stm32h750b_dk.dts b/boards/st/stm32h750b_dk/stm32h750b_dk.dts similarity index 100% rename from boards/arm/stm32h750b_dk/stm32h750b_dk.dts rename to boards/st/stm32h750b_dk/stm32h750b_dk.dts diff --git a/boards/arm/stm32h750b_dk/stm32h750b_dk.yaml b/boards/st/stm32h750b_dk/stm32h750b_dk.yaml similarity index 100% rename from boards/arm/stm32h750b_dk/stm32h750b_dk.yaml rename to boards/st/stm32h750b_dk/stm32h750b_dk.yaml diff --git a/boards/arm/stm32h750b_dk/stm32h750b_dk_defconfig b/boards/st/stm32h750b_dk/stm32h750b_dk_defconfig similarity index 88% rename from boards/arm/stm32h750b_dk/stm32h750b_dk_defconfig rename to boards/st/stm32h750b_dk/stm32h750b_dk_defconfig index 64cab9ff714..08add3eb2c6 100644 --- a/boards/arm/stm32h750b_dk/stm32h750b_dk_defconfig +++ b/boards/st/stm32h750b_dk/stm32h750b_dk_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2023 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H750XX=y - # Enable the internal SMPS regulator CONFIG_POWER_SUPPLY_LDO=y diff --git a/boards/arm/stm32h750b_dk/support/openocd.cfg b/boards/st/stm32h750b_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32h750b_dk/support/openocd.cfg rename to boards/st/stm32h750b_dk/support/openocd.cfg diff --git a/boards/st/stm32h7b3i_dk/Kconfig.defconfig b/boards/st/stm32h7b3i_dk/Kconfig.defconfig new file mode 100644 index 00000000000..39101c47f7b --- /dev/null +++ b/boards/st/stm32h7b3i_dk/Kconfig.defconfig @@ -0,0 +1,19 @@ +# STM32H7B3I DISCOVERY KIT board configuration + +# Copyright (c) 2022 Byte-Lab d.o.o. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32H7B3I_DK + +config INPUT + default y if LVGL + +config INPUT_FT5336_INTERRUPT + default y if INPUT_FT5336 + +# MEMC needs to be enabled in order to store +# display buffer to external SDRAM connected to FMC +config MEMC + default y if DISPLAY + +endif # BOARD_STM32H7B3I_DK diff --git a/boards/st/stm32h7b3i_dk/Kconfig.stm32h7b3i_dk b/boards/st/stm32h7b3i_dk/Kconfig.stm32h7b3i_dk new file mode 100644 index 00000000000..c243bf05acd --- /dev/null +++ b/boards/st/stm32h7b3i_dk/Kconfig.stm32h7b3i_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Byte-Lab d.o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32H7B3I_DK + select SOC_STM32H7B3XXQ diff --git a/boards/arm/stm32h7b3i_dk/arduino_r3_connector.dtsi b/boards/st/stm32h7b3i_dk/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32h7b3i_dk/arduino_r3_connector.dtsi rename to boards/st/stm32h7b3i_dk/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32h7b3i_dk/board.cmake b/boards/st/stm32h7b3i_dk/board.cmake similarity index 100% rename from boards/arm/stm32h7b3i_dk/board.cmake rename to boards/st/stm32h7b3i_dk/board.cmake diff --git a/boards/st/stm32h7b3i_dk/board.yml b/boards/st/stm32h7b3i_dk/board.yml new file mode 100644 index 00000000000..5516412eac9 --- /dev/null +++ b/boards/st/stm32h7b3i_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32h7b3i_dk + vendor: st + socs: + - name: stm32h7b3xx diff --git a/boards/arm/stm32h7b3i_dk/doc/img/stm32h7b3i_dk.jpg b/boards/st/stm32h7b3i_dk/doc/img/stm32h7b3i_dk.jpg similarity index 100% rename from boards/arm/stm32h7b3i_dk/doc/img/stm32h7b3i_dk.jpg rename to boards/st/stm32h7b3i_dk/doc/img/stm32h7b3i_dk.jpg diff --git a/boards/st/stm32h7b3i_dk/doc/index.rst b/boards/st/stm32h7b3i_dk/doc/index.rst new file mode 100644 index 00000000000..98f00c34234 --- /dev/null +++ b/boards/st/stm32h7b3i_dk/doc/index.rst @@ -0,0 +1,171 @@ +.. _stm32h7b3i_dk_board: + +ST STM32H7B3I Discovery Kit +########################### + +Overview +******** + +The STM32H7B3I-DK Discovery kit is a complete demonstration and development +platform for STMicroelectronics Arm® Cortex®-M7 core-based STM32H7B3LIH6QU +microcontroller. + +The STM32H7B3I-DK Discovery kit is used as a reference design for user +application development before porting to the final product, thus simplifying +the application development. + +The full range of hardware features available on the board helps users enhance +their application development by an evaluation of almost all peripherals (such as +USB OTG_HS, microSD, USART, FDCAN, audio DAC stereo with audio jack input and output, +camera, SDRAM, Octo-SPI Flash memory and RGB interface LCD with capacitive touch +panel). ARDUINO® Uno V3 connectors provide easy connection to extension shields or +daughterboards for specific applications. + +STLINK-V3E is integrated into the board, as an embedded in-circuit debugger and +programmer for the STM32 MCU and the USB Virtual COM port bridge. The STM32H7B3I-DK +board comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive +software HAL library as well as various software examples. + +.. image:: img/stm32h7b3i_dk.jpg + :align: center + :alt: STM32H7B3I-DK + +More information about the board can be found at the `STM32H7B3I-DK website`_. +More information about STM32H7B3 can be found here: + +- `STM32H7A3/7B3 on www.st.com`_ +- `STM32H7A3/7B3/7B0 reference manual`_ +- `STM32H7B3xI datasheet`_ + +Supported Features +================== + +The current Zephyr stm32h7b3i_dk board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| LTDC | on-chip | display | ++-----------+------------+-------------------------------------+ +| CANFD | on-chip | can | ++-----------+------------+-------------------------------------+ + + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig` + +Pin Mapping +=========== + +For more details please refer to `STM32H7B3I-DK website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) +- UART_4 TX/RX : PH13/PH14 (Arduino Serial) +- I2C4 SCL/SDA : PD12/PD13 (Arduino I2C, Touchscreen FT5336 with PH2 Interrupt Pin) +- SPI2 SCK/MISO/MOSI/NSS : PA12/PB14/PB15/PI0 (Arduino SPI) +- LD1 : PG11 +- LD2 : PG2 +- USER_PB : PC13 +- SDMMC D0/D1/D2/D3/CK/CMD/CD : PC8/PC9/PC10/PC11/PC12/PD2/PI8 +- CANFD RX/TX/WAKE [#]_ : PA11/PA12/PH8 +- FMC SDRAM : + + - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 + - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 + - A14/A15 : PG4/PG5 + - SDNRAS/SDNCAS : PF11/PG15 + - NBL0/NBL1 : PE0/PE1 + - SDCLK/SDNWE/SDCKE1/SDNE1 : PG8/PH5/PH7/PH6 + +- LTDC : + + - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 + - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 + - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 + - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 + + +System Clock +============ + +The STM32H7B3I System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven +by the PLL clock at 280MHz. PLL clock is fed by a 24MHz high speed external clock. + +Serial Port +=========== + +The STM32H7B3I Discovery kit has up to 8 UARTs. +The Zephyr console output is assigned to UART1 which connected to the onboard +ST-LINK/V3.0. Virtual COM port interface. Default communication settings are +115200 8N1. + + +Programming and Debugging +************************* + +See :ref:`build_an_application` for more information about application builds. + + +Flashing +======== + +Flashing operation will depend on the target to be flashed and the SoC +option bytes configuration. +It is advised to use `STM32CubeProgrammer`_ to check and update option bytes +configuration and flash the ``stm32h7b3i_dk`` target. + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h7b3i_dk + :goals: debug + + +.. _STM32H7B3I-DK website: + https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html + +.. _STM32H7A3/7B3 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3-7b3.html + +.. _STM32H7A3/7B3/7B0 reference manual: + https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32H7B3xI datasheet: + https://www.st.com/resource/en/datasheet/stm32h7b3ai.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STM32H7B3I_DK board schematics: + https://www.st.com/resource/en/schematic_pack/mb1332-h7b3i-c02_schematic.pdf + +.. [#] To use CAN, solder bridges SB3, SB4 and SB5 need to be connected. + Take note that CANFD pins are shared with STMOD+ connector (P1), so please check + `STM32H7B3I_DK board schematics`_ for possible collisions if using that connector. diff --git a/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts similarity index 100% rename from boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts rename to boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts diff --git a/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.yaml b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.yaml similarity index 100% rename from boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.yaml rename to boards/st/stm32h7b3i_dk/stm32h7b3i_dk.yaml diff --git a/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk_defconfig b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig similarity index 89% rename from boards/arm/stm32h7b3i_dk/stm32h7b3i_dk_defconfig rename to boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig index 913a1ed5dbd..bb3b8c0178c 100644 --- a/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk_defconfig +++ b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig @@ -2,9 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 # Set SoC present on the board -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H7B3XXQ=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32h7b3i_dk/support/openocd.cfg b/boards/st/stm32h7b3i_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32h7b3i_dk/support/openocd.cfg rename to boards/st/stm32h7b3i_dk/support/openocd.cfg diff --git a/boards/st/stm32l1_disco/Kconfig.stm32l1_disco b/boards/st/stm32l1_disco/Kconfig.stm32l1_disco new file mode 100644 index 00000000000..9e1e0bb01a4 --- /dev/null +++ b/boards/st/stm32l1_disco/Kconfig.stm32l1_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2019 eTactica ehf +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32L1_DISCO + select SOC_STM32L151XB diff --git a/boards/arm/stm32l1_disco/board.cmake b/boards/st/stm32l1_disco/board.cmake similarity index 100% rename from boards/arm/stm32l1_disco/board.cmake rename to boards/st/stm32l1_disco/board.cmake diff --git a/boards/st/stm32l1_disco/board.yml b/boards/st/stm32l1_disco/board.yml new file mode 100644 index 00000000000..bdca72bf548 --- /dev/null +++ b/boards/st/stm32l1_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32l1_disco + vendor: st + socs: + - name: stm32l151xb diff --git a/boards/arm/stm32l1_disco/doc/img/stm32l1_disco.jpg b/boards/st/stm32l1_disco/doc/img/stm32l1_disco.jpg similarity index 100% rename from boards/arm/stm32l1_disco/doc/img/stm32l1_disco.jpg rename to boards/st/stm32l1_disco/doc/img/stm32l1_disco.jpg diff --git a/boards/st/stm32l1_disco/doc/index.rst b/boards/st/stm32l1_disco/doc/index.rst new file mode 100644 index 00000000000..a3b4a30bdfa --- /dev/null +++ b/boards/st/stm32l1_disco/doc/index.rst @@ -0,0 +1,179 @@ +.. _stm32l1_disco_board: + +ST STM32L1 Discovery +#################### + +Overview +******** + +The two generations of the STM32L1 Discovery development boards come with +an integrated ST-LINK/V2 debugger and programmer. The boards have a +24-segment LCD and a touch slider, along with two user LEDs and a user button. +Support circuitry for measuring power consumption is also available. +It also comes with a comprehensive STM32 software HAL library and various +packaged software examples. + +There +are two variants of the board: + +- STM32LDISCOVERY targets STM32L152RBT6, with 128K flash, 16K RAM +- 32L152CDISCOVERY targets STM32L152RCT6, with 256K flash, 32K RAM + +The STM32LDISCOVERY is no longer sold, but was widely available. The current +configuration assumes only 128K flash and 16K RAM, so it builds and runs +on both variants out of the box. + +.. image:: img/stm32l1_disco.jpg + :align: center + :alt: STM32LDISCOVERY + +More information about the board can be found at the `STM32LDISCOVERY website`_. + +Hardware +******** + +The STM32 Discovery board features: + +- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone + ST-LINK/V2 (with SWD connector for programming and debugging) +- Board power supply: through USB bus or from an external 5 V supply voltage +- External application power supply: 3 V and 5 V +- Four LEDs: + + - LD1 (red) for 3.3 V power on + - LD2 (red/green) for USB communication + - LD3 (green) for PC9 output + - LD4 (blue) for PC8 output +- Two push buttons (user and reset) +- Extension header for all LQFP64 I/Os for quick connection to prototyping board + and easy probing + +More information about STM32L151x can be found in the `STM32L1x reference manual`_. + +Supported Features +================== + +The Zephyr stm32l1_disco board configuration supports the following hardware features: + +.. list-table:: Supported hardware + :header-rows: 1 + + * - Interface + - Controller + - Driver/component + * - NVIC + - on-chip + - nested vector interrupt controller + * - UART + - on-chip + - serial port-polling + serial port-interrupt + * - PINMUX + - on-chip + - pinmux + * - GPIO + - on-chip + - gpio + * - CLOCK + - on-chip + - reset and clock control + * - FLASH + - on-chip + - flash memory + * - WATCHDOG + - on-chip + - window watchdog + * - I2C + - on-chip + - i2c + * - SPI + - on-chip + - spi + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32l1_disco/stm32l1_disco_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PB11 +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 + +For more details please refer to `STM32L1DISCOVERY board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``stm32l1_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32L1DISCOVERY board includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application +----------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32l1_disco + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32l1_disco + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32LDISCOVERY website: + https://www.st.com/en/evaluation-tools/32l152cdiscovery.html + +.. _STM32L1x reference manual: + https://www.st.com/resource/en/reference_manual/cd00240193.pdf + +.. _STM32L1DISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00027954.pdf diff --git a/boards/arm/stm32l1_disco/stm32l1_disco.dts b/boards/st/stm32l1_disco/stm32l1_disco.dts similarity index 100% rename from boards/arm/stm32l1_disco/stm32l1_disco.dts rename to boards/st/stm32l1_disco/stm32l1_disco.dts diff --git a/boards/arm/stm32l1_disco/stm32l1_disco.yaml b/boards/st/stm32l1_disco/stm32l1_disco.yaml similarity index 100% rename from boards/arm/stm32l1_disco/stm32l1_disco.yaml rename to boards/st/stm32l1_disco/stm32l1_disco.yaml diff --git a/boards/arm/stm32l1_disco/stm32l1_disco_defconfig b/boards/st/stm32l1_disco/stm32l1_disco_defconfig similarity index 81% rename from boards/arm/stm32l1_disco/stm32l1_disco_defconfig rename to boards/st/stm32l1_disco/stm32l1_disco_defconfig index dfbf82011e5..fd0afcb9d74 100644 --- a/boards/arm/stm32l1_disco/stm32l1_disco_defconfig +++ b/boards/st/stm32l1_disco/stm32l1_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L1X=y -CONFIG_SOC_STM32L151XB=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/stm32l1_disco/support/openocd.cfg b/boards/st/stm32l1_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32l1_disco/support/openocd.cfg rename to boards/st/stm32l1_disco/support/openocd.cfg diff --git a/boards/st/stm32l476g_disco/Kconfig.stm32l476g_disco b/boards/st/stm32l476g_disco/Kconfig.stm32l476g_disco new file mode 100644 index 00000000000..7c062054f44 --- /dev/null +++ b/boards/st/stm32l476g_disco/Kconfig.stm32l476g_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Arthur Sfez +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32L476G_DISCO + select SOC_STM32L476XX diff --git a/boards/arm/stm32l476g_disco/board.cmake b/boards/st/stm32l476g_disco/board.cmake similarity index 100% rename from boards/arm/stm32l476g_disco/board.cmake rename to boards/st/stm32l476g_disco/board.cmake diff --git a/boards/st/stm32l476g_disco/board.yml b/boards/st/stm32l476g_disco/board.yml new file mode 100644 index 00000000000..c82c2c61843 --- /dev/null +++ b/boards/st/stm32l476g_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32l476g_disco + vendor: st + socs: + - name: stm32l476xx diff --git a/boards/arm/stm32l476g_disco/doc/img/stm32l476g_disco.jpg b/boards/st/stm32l476g_disco/doc/img/stm32l476g_disco.jpg similarity index 100% rename from boards/arm/stm32l476g_disco/doc/img/stm32l476g_disco.jpg rename to boards/st/stm32l476g_disco/doc/img/stm32l476g_disco.jpg diff --git a/boards/st/stm32l476g_disco/doc/index.rst b/boards/st/stm32l476g_disco/doc/index.rst new file mode 100644 index 00000000000..ef40802a709 --- /dev/null +++ b/boards/st/stm32l476g_disco/doc/index.rst @@ -0,0 +1,218 @@ +.. _stm32l476g_disco_board: + +ST STM32L476G Discovery +####################### + +Overview +******** + +The STM32L476G Discovery board features an ARM Cortex-M4 based STM32L476VG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the STM32L476G Discovery board: + + +- STM32L476VGT6 microcontroller featuring 1 Mbyte of Flash memory, 128 Kbytes of RAM in LQFP100 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- Three different interfaces supported on USB: + + - Virtual com port + - Mass storage + - Debug port + +- LCD 24 segments, 4 commons in DIP 28 package +- Seven LEDs: + + - LD1 (red/green) for USB communication + - LD2 (red) for 3.3 V power on + - LD3 Over current (red) + - LD4 (red), LD5 (green) two user LEDs + - LD6 (green), LD7 (red) USB OTG FS LEDs + +- Pushbutton (reset) +- Four directions Joystick with selection +- USB OTG FS with micro-AB connector +- SAI Audio DAC, Stereo with output jack +- Digital microphone, accelerometer, magnetometer and gyroscope MEMS +- 128-Mbit Quad-SPI Flash memory +- MCU current ammeter with 4 ranges and auto-calibration +- Connector for external board or RF-EEPROM +- Four power supply options: + - ST-LINK/V2-1 + - USB FS connector + - External 5 V + - CR2032 battery (not provided) + +.. image:: img/stm32l476g_disco.jpg + :align: center + :alt: STM32L476G Discovery + +More information about the board can be found at the `STM32L476G Discovery website`_. + +Hardware +******** + +The STM32L476VG SoC provides the following hardware features: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC +- RTC with HW calendar, alarms and calibration +- LCD 8 x 40 or 4 x 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 128 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators +- 18x communication interfaces + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L476VG can be found here: + - `STM32L476VG on www.st.com`_ + - `STM32L476 reference manual`_ + + +Supported Features +================== + +The Zephyr stm32l476g_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/st/stm32l476g_disco/stm32l476g_disco_defconfig` + + +Connections and IOs +=================== + +STM32L476G Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32L476G Discovery board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- LD4 : PB2 +- LD5 : PE8 + +System Clock +------------ + +STM32L476G Discovery System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +STM32L476G Discovery board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +STM32L476G Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32L476G Discovery +----------------------------------------------- + +Connect the STM32L476G Discovery to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l476g_disco + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l476g_disco + :maybe-skip-config: + :goals: debug + +.. _STM32L476G Discovery website: + https://www.st.com/en/evaluation-tools/32l476gdiscovery.html + +.. _STM32L476G Discovery board User Manual: + https://www.st.com/resource/en/user_manual/dm00172179.pdf + +.. _STM32L476VG on www.st.com: + https://www.st.com/en/microcontrollers/stm32l476vg.html + +.. _STM32L476 reference manual: + https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/stm32l476g_disco/stm32l476g_disco.dts b/boards/st/stm32l476g_disco/stm32l476g_disco.dts similarity index 100% rename from boards/arm/stm32l476g_disco/stm32l476g_disco.dts rename to boards/st/stm32l476g_disco/stm32l476g_disco.dts diff --git a/boards/arm/stm32l476g_disco/stm32l476g_disco.yaml b/boards/st/stm32l476g_disco/stm32l476g_disco.yaml similarity index 100% rename from boards/arm/stm32l476g_disco/stm32l476g_disco.yaml rename to boards/st/stm32l476g_disco/stm32l476g_disco.yaml diff --git a/boards/arm/stm32l476g_disco/stm32l476g_disco_defconfig b/boards/st/stm32l476g_disco/stm32l476g_disco_defconfig similarity index 85% rename from boards/arm/stm32l476g_disco/stm32l476g_disco_defconfig rename to boards/st/stm32l476g_disco/stm32l476g_disco_defconfig index 0f0f47059fe..82ee7285d52 100644 --- a/boards/arm/stm32l476g_disco/stm32l476g_disco_defconfig +++ b/boards/st/stm32l476g_disco/stm32l476g_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L476XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32l476g_disco/support/openocd.cfg b/boards/st/stm32l476g_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32l476g_disco/support/openocd.cfg rename to boards/st/stm32l476g_disco/support/openocd.cfg diff --git a/boards/arm/stm32l496g_disco/CMakeLists.txt b/boards/st/stm32l496g_disco/CMakeLists.txt similarity index 100% rename from boards/arm/stm32l496g_disco/CMakeLists.txt rename to boards/st/stm32l496g_disco/CMakeLists.txt diff --git a/boards/st/stm32l496g_disco/Kconfig.defconfig b/boards/st/stm32l496g_disco/Kconfig.defconfig new file mode 100644 index 00000000000..604ea42983c --- /dev/null +++ b/boards/st/stm32l496g_disco/Kconfig.defconfig @@ -0,0 +1,16 @@ +# STM32L476G Nucleo board configuration + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32L496G_DISCO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_STM32L496G_DISCO diff --git a/boards/st/stm32l496g_disco/Kconfig.stm32l496g_disco b/boards/st/stm32l496g_disco/Kconfig.stm32l496g_disco new file mode 100644 index 00000000000..43f50ffced9 --- /dev/null +++ b/boards/st/stm32l496g_disco/Kconfig.stm32l496g_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Centaur Analytics, Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32L496G_DISCO + select SOC_STM32L496XX diff --git a/boards/arm/stm32l496g_disco/arduino_r3_connector.dtsi b/boards/st/stm32l496g_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32l496g_disco/arduino_r3_connector.dtsi rename to boards/st/stm32l496g_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32l496g_disco/board.cmake b/boards/st/stm32l496g_disco/board.cmake similarity index 100% rename from boards/arm/stm32l496g_disco/board.cmake rename to boards/st/stm32l496g_disco/board.cmake diff --git a/boards/st/stm32l496g_disco/board.yml b/boards/st/stm32l496g_disco/board.yml new file mode 100644 index 00000000000..9d6b18a598d --- /dev/null +++ b/boards/st/stm32l496g_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32l496g_disco + vendor: st + socs: + - name: stm32l496xx diff --git a/boards/arm/stm32l496g_disco/board_adc_vref.c b/boards/st/stm32l496g_disco/board_adc_vref.c similarity index 100% rename from boards/arm/stm32l496g_disco/board_adc_vref.c rename to boards/st/stm32l496g_disco/board_adc_vref.c diff --git a/boards/arm/stm32l496g_disco/doc/img/stm32l496g_disco.jpg b/boards/st/stm32l496g_disco/doc/img/stm32l496g_disco.jpg similarity index 100% rename from boards/arm/stm32l496g_disco/doc/img/stm32l496g_disco.jpg rename to boards/st/stm32l496g_disco/doc/img/stm32l496g_disco.jpg diff --git a/boards/st/stm32l496g_disco/doc/index.rst b/boards/st/stm32l496g_disco/doc/index.rst new file mode 100644 index 00000000000..576c07bc2cc --- /dev/null +++ b/boards/st/stm32l496g_disco/doc/index.rst @@ -0,0 +1,259 @@ +.. _stm32l496g_disco_board: + +ST STM32L496G Discovery +####################### + +Overview +******** + +The STM32L496G Discovery board features an ARM Cortex-M4 based STM32L496AG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the STM32L496G Discovery board: + + +- STM32L496AGI6 microcontroller featuring 1 Mbyte of Flash memory and 320 Kbytes of RAM in an UFBGA169 package +- 1.54 inch 240 x 240 pixel-TFT color LCD with parallel interface +- SAI Audio CODEC, with a stereo headset jack, including analog microphone input +- Stereo digital MEMS microphones +- microSD card connector (card included) +- Camera 8 bit-connector +- 8 Mbit-PSRAM +- IDD measurement +- 64 Mbit-Quad-SPI Flash +- USB OTG FS with Micro-AB connector +- Two types of extension resources: + + - STMod+ and PMOD connectors + - Compatible Arduino* Uno V3 connectors + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- 5 source options for power supply + + - ST-LINK/V2-1 USB connector + - User USB FS connector + - VIN from Arduino connector + - 5 V from Arduino connector + - USB charger + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- 8 LEDs +- Reset push button +- 4 direction-joystick with selection + +.. image:: img/stm32l496g_disco.jpg + :align: center + :alt: STM32L496G Discovery + +More information about the board can be found at the `STM32L496G Discovery website`_. + +Hardware +******** + +The STM32L496AG SoC provides the following hardware capabilities: + +- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, + 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - Internal 48 MHz with clock recovery + - 3 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- LCD 8 x 40 or 4 x 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - 320 KB of SRAM including 64 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR, and NAND memories + - Quad SPI memory interface + +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 20x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 5x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART + - 3x SPIs (4x SPIs with the Quad SPI) + - 2x CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32L496AG can be found in: + +- `STM32L496AG on www.st.com`_ +- `STM32L496 reference manual`_ + +Supported Features +================== + +The Zephyr stm32l496g_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/st/stm32l496g_disco/stm32l496g_disco_defconfig` + + +Connections and IOs +=================== + +STM32L496G Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32L496G Discovery board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PG10 +- UART_2 TX/RX : PA2/PD6 (ST-Link Virtual Port Com) +- LPUART_1 TX/RX : PG7/PG8 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB7 (Arduino I2C) +- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2 +- SPI1 NSS/SCK/MISO/MOSI : PA15/PA5/PB4/PB5 (Arduino SPI) +- USB DM/DP/ID : PA11/PA12/PA10 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB7 +- PWM_2_CH1 : PA0 +- LD2 : PB13 + +System Clock +------------ + +STM32L496G Discovery System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +STM32L496G Discovery board has 5 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +STM32L496G Discovery board includes an ST-LINK/V2-1 embedded debug +tool interface. This interface is supported by openocd version +v0.10.0, which has been available since Zephyr SDK v0.9.2. + +Applications for the ``stm32l496g_disco`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + +Flashing an application to STM32L496G Discovery +----------------------------------------------- + +Connect the STM32L496G Discovery to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l496g_disco + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l496g_disco + :maybe-skip-config: + :goals: debug + +.. _STM32L496G Discovery website: + https://www.st.com/en/evaluation-tools/32l496gdiscovery.html + +.. _STM32L496G Discovery board User Manual: + https://www.st.com/resource/en/user_manual/dm00353127.pdf + +.. _STM32L496AG on www.st.com: + https://www.st.com/en/microcontrollers/stm32l496ag.html + +.. _STM32L496 reference manual: + https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/stm32l496g_disco/stm32l496g_disco.dts b/boards/st/stm32l496g_disco/stm32l496g_disco.dts similarity index 100% rename from boards/arm/stm32l496g_disco/stm32l496g_disco.dts rename to boards/st/stm32l496g_disco/stm32l496g_disco.dts diff --git a/boards/arm/stm32l496g_disco/stm32l496g_disco.yaml b/boards/st/stm32l496g_disco/stm32l496g_disco.yaml similarity index 100% rename from boards/arm/stm32l496g_disco/stm32l496g_disco.yaml rename to boards/st/stm32l496g_disco/stm32l496g_disco.yaml diff --git a/boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig b/boards/st/stm32l496g_disco/stm32l496g_disco_defconfig similarity index 85% rename from boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig rename to boards/st/stm32l496g_disco/stm32l496g_disco_defconfig index d2d940208b5..c7582ad0d95 100644 --- a/boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig +++ b/boards/st/stm32l496g_disco/stm32l496g_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L496XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32l496g_disco/support/openocd.cfg b/boards/st/stm32l496g_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32l496g_disco/support/openocd.cfg rename to boards/st/stm32l496g_disco/support/openocd.cfg diff --git a/boards/st/stm32l4r9i_disco/Kconfig.stm32l4r9i_disco b/boards/st/stm32l4r9i_disco/Kconfig.stm32l4r9i_disco new file mode 100644 index 00000000000..68064303571 --- /dev/null +++ b/boards/st/stm32l4r9i_disco/Kconfig.stm32l4r9i_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32L4R9I_DISCO + select SOC_STM32L4R9XX diff --git a/boards/arm/stm32l4r9i_disco/arduino_r3_connector.dtsi b/boards/st/stm32l4r9i_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32l4r9i_disco/arduino_r3_connector.dtsi rename to boards/st/stm32l4r9i_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32l4r9i_disco/board.cmake b/boards/st/stm32l4r9i_disco/board.cmake similarity index 100% rename from boards/arm/stm32l4r9i_disco/board.cmake rename to boards/st/stm32l4r9i_disco/board.cmake diff --git a/boards/st/stm32l4r9i_disco/board.yml b/boards/st/stm32l4r9i_disco/board.yml new file mode 100644 index 00000000000..267fd87932d --- /dev/null +++ b/boards/st/stm32l4r9i_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32l4r9i_disco + vendor: st + socs: + - name: stm32l4r9xx diff --git a/boards/arm/stm32l4r9i_disco/doc/img/stm32l4r9i_disco.jpg b/boards/st/stm32l4r9i_disco/doc/img/stm32l4r9i_disco.jpg similarity index 100% rename from boards/arm/stm32l4r9i_disco/doc/img/stm32l4r9i_disco.jpg rename to boards/st/stm32l4r9i_disco/doc/img/stm32l4r9i_disco.jpg diff --git a/boards/st/stm32l4r9i_disco/doc/index.rst b/boards/st/stm32l4r9i_disco/doc/index.rst new file mode 100644 index 00000000000..e2053313122 --- /dev/null +++ b/boards/st/stm32l4r9i_disco/doc/index.rst @@ -0,0 +1,150 @@ +.. _stm32l4r9i_disco_board: + +ST STM32L4R9I Discovery +####################### + +Overview +******** + +The 32L4R9IDISCOVERY Discovery kit is a complete demonstration and development platform +for STMicroelectronics Arm® Cortex®-M4 core-based STM32L4R9AI microcontroller. + +Leveraging the innovative ultra-low-power oriented features, 640 Kbytes of embedded RAM, +graphics performance (Chrom-ART Accelerator), and DSI controller offered by the STM32L4R9AI, +the 32L4R9IDISCOVERY Discovery kit enables users to easily prototype applications with +state-of-the-art energy efficiency, as well as stunning audio and graphics rendering with direct +support for AMOLED DSI round LCD display. + +For even more user-friendliness, the on-board ST-LINK/V2-1 debugger provides out-of-the-box +programming and debugging capabilities. + +.. image:: img/stm32l4r9i_disco.jpg + :align: center + :alt: STM32L4R9I-DISCO + +More information about the board can be found at the `STM32L4R9I-DISCOVERY website`_. +More information about STM32L4R9 can be found here: + +- `STM32L4R9/S9 on www.st.com`_ +- `STM32L4+ Series reference manual`_ +- `STM32L4R5xx/R7xx/R9xx datasheet`_ + +Supported Features +================== + +The current Zephyr stm32l4r9i_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | on-chip flash memory; | +| | | external OctoSPI memory | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | Real Time Clock | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | sd/mmc | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig` + + +Pin Mapping +=========== + +For more details, please refer to `STM32L4R9I-DISCOVERY website`_. + +System Clock +============ + +The STM32L4R9AI System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven by +the PLL clock at 120MHz. PLL clock is driven by a 4MHz medium speed internal clock. + +Serial Port +=========== + +The STM32L4R9I Discovery board has up to 6 U(S)ARTs. +The Zephyr console output is assigned to UART2, which is connected to the onboard +ST-LINK Virtual COM port interface. Default communication settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +The STM32L4R9I Discovery board includes an ST-LINK/V2-1 debug tool. + +Applications for the ``stm32l4r9i_disco`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + + +Flashing an application to STM32L4R9I Discovery +----------------------------------------------- + +Connect the STM32L4R9I Discovery to your host computer using the ST-LINK +USB port, then run a serial host program to connect with the board. For example: + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +You can then build and flash applications in the usual way. +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l4r9i_disco + :goals: build flash + +You should see the following message in the serial host program: + +.. code-block:: console + + $ Hello World! stm32l4r9i_disco + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l4r9i_disco + :goals: debug + +.. _STM32L4R9I-DISCOVERY website: + https://www.st.com/en/evaluation-tools/32l4r9idiscovery.html + +.. _STM32L4R9/S9 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l4r9-s9.html + +.. _STM32L4+ Series reference manual: + https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32L4R5xx/R7xx/R9xx datasheet: + https://www.st.com/resource/en/datasheet/stm32l4r5vi.pdf diff --git a/boards/arm/stm32l4r9i_disco/stm32l4r9i_disco.dts b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts similarity index 100% rename from boards/arm/stm32l4r9i_disco/stm32l4r9i_disco.dts rename to boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts diff --git a/boards/arm/stm32l4r9i_disco/stm32l4r9i_disco.yaml b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml similarity index 100% rename from boards/arm/stm32l4r9i_disco/stm32l4r9i_disco.yaml rename to boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml diff --git a/boards/arm/stm32l4r9i_disco/stm32l4r9i_disco_defconfig b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig similarity index 85% rename from boards/arm/stm32l4r9i_disco/stm32l4r9i_disco_defconfig rename to boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig index 546bd3379a8..ac681be2af0 100644 --- a/boards/arm/stm32l4r9i_disco/stm32l4r9i_disco_defconfig +++ b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4R9XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32l4r9i_disco/support/openocd.cfg b/boards/st/stm32l4r9i_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32l4r9i_disco/support/openocd.cfg rename to boards/st/stm32l4r9i_disco/support/openocd.cfg diff --git a/boards/arm/stm32l562e_dk/CMakeLists.txt b/boards/st/stm32l562e_dk/CMakeLists.txt similarity index 100% rename from boards/arm/stm32l562e_dk/CMakeLists.txt rename to boards/st/stm32l562e_dk/CMakeLists.txt diff --git a/boards/st/stm32l562e_dk/Kconfig.defconfig b/boards/st/stm32l562e_dk/Kconfig.defconfig new file mode 100644 index 00000000000..3f15027bb35 --- /dev/null +++ b/boards/st/stm32l562e_dk/Kconfig.defconfig @@ -0,0 +1,29 @@ +# STM32L562E-DK Discovery board configuration + +# Copyright (c) 2020 Yestin Sun +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32L562E_DK + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +config BT_BLUENRG_ACI + default y + +# Disable Flow control +config BT_HCI_ACL_FLOW_CONTROL + default n + +config BT_HCI_VS_EXT + default n + +endif # BT + +endif # BOARD_STM32L562E_DK diff --git a/boards/st/stm32l562e_dk/Kconfig.stm32l562e_dk b/boards/st/stm32l562e_dk/Kconfig.stm32l562e_dk new file mode 100644 index 00000000000..f5b901a2bce --- /dev/null +++ b/boards/st/stm32l562e_dk/Kconfig.stm32l562e_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Yestin Sun +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32L562E_DK + select SOC_STM32L562XX diff --git a/boards/arm/stm32l562e_dk/arduino_r3_connector.dtsi b/boards/st/stm32l562e_dk/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32l562e_dk/arduino_r3_connector.dtsi rename to boards/st/stm32l562e_dk/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32l562e_dk/board.cmake b/boards/st/stm32l562e_dk/board.cmake similarity index 100% rename from boards/arm/stm32l562e_dk/board.cmake rename to boards/st/stm32l562e_dk/board.cmake diff --git a/boards/st/stm32l562e_dk/board.yml b/boards/st/stm32l562e_dk/board.yml new file mode 100644 index 00000000000..225f25adc2e --- /dev/null +++ b/boards/st/stm32l562e_dk/board.yml @@ -0,0 +1,7 @@ +board: + name: stm32l562e_dk + vendor: st + socs: + - name: stm32l562xx + variants: + - name: ns diff --git a/boards/arm/stm32l562e_dk/doc/img/stm32l562e_dk.jpg b/boards/st/stm32l562e_dk/doc/img/stm32l562e_dk.jpg similarity index 100% rename from boards/arm/stm32l562e_dk/doc/img/stm32l562e_dk.jpg rename to boards/st/stm32l562e_dk/doc/img/stm32l562e_dk.jpg diff --git a/boards/st/stm32l562e_dk/doc/index.rst b/boards/st/stm32l562e_dk/doc/index.rst new file mode 100644 index 00000000000..889f0b8d593 --- /dev/null +++ b/boards/st/stm32l562e_dk/doc/index.rst @@ -0,0 +1,387 @@ +.. _stm32l562e_dk_board: + +ST STM32L562E-DK Discovery +########################## + +Overview +******** + +The STM32L562E-DK Discovery kit is designed as a complete demonstration and +development platform for STMicroelectronics Arm |reg| Cortex |reg|-M33 core-based +STM32L562QEI6QU microcontroller with TrustZone |reg|. Here are some highlights of +the STM32L562E-DK Discovery board: + + +- STM32L562QEI6QU microcontroller featuring 512 Kbytes of Flash memory and 256 Kbytes of SRAM in BGA132 package +- 1.54" 240 x 240 pixel-262K color TFT LCD module with parallel interface and touch-control panel +- USB Type-C |trade| Sink device FS +- On-board energy meter: 300 nA to 150 mA measurement range with a dedicated USB interface +- SAI Audio CODEC +- MEMS digital microphones +- 512-Mbit Octal-SPI Flash memory +- Bluetooth |reg| V4.1 Low Energy module +- iNEMO 3D accelerometer and 3D gyroscope +- Board connectors + + - STMod+ expansion connector with fan-out expansion board for Wi‑Fi |reg|, Grove and mikroBUS |trade| compatible connectors + - Pmod |trade| expansion connector + - Audio MEMS daughterboard expansion connector + - ARDUINO |reg| Uno V3 expansion connector + +- Flexible power-supply options + + - ST-LINK + - USB VBUS + - external sources + +- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: + + - mass storage + - Virtual COM port + - debug port + +- 2 user LEDs +- User and reset push-buttons + +.. image:: img/stm32l562e_dk.jpg + :align: center + :alt: STM32L562E-DK Discovery + +More information about the board can be found at the `STM32L562E-DK Discovery website`_. + +Hardware +******** + +The STM32L562xx devices are an ultra-low-power microcontrollers family (STM32L5 +Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. +They operate at a frequency of up to 110 MHz. + +- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 62 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1.5 DMPIS/MHz (Drystone 2.1) + - 442 CoreMark |reg| (4.02 CoreMark |reg| /MHZ) + +- Security + + - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals + - Flexible life cycle scheme with RDP (readout protection) + - Root of trust thanks to unique boot entry and hide protection area (HDP) + - Secure Firmware Installation thanks to embedded Root Secure Services + - Secure Firmware Update support with TF-M + - AES coprocessor + - Public key accelerator + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - Active tamper and protection temperature, voltage and frequency attacks + - True Random Number Generator NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte One-Time Programmable for user data + +- Clock management: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + +- Power management + + - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry + - Embedded SMPS step-down converter + - External SMPS support + +- RTC with HW calendar, alarms and calibration +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Up to 22 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- Up to 16 timers and 2 watchdogs + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 3x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- Memories + + - Up to 512 MB Flash, 2 banks read-while-write + - 512 KB of SRAM including 64 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR, NAND and FRAM memories + - OCTOSPI memory interface + +- Rich analog peripherals (independent supply) + + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + - 4x digital filters for sigma delta modulator + +- 19x communication interfaces + + - USB Type-C / USB power delivery controller + - 2.0 full-speed crystal less solution, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (7x SPIs with USART and OCTOSPI in SPI mode) + - 1xFDCAN + - 1xSDMMC interface + - 2x 14 channel DMA controllers + +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L562QE can be found here: + +- `STM32L562QE on www.st.com`_ +- `STM32L562 reference manual`_ + +Supported Features +================== + +The Zephyr stm32l562e_dk board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | sd/mmc | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| TrustZone | on-chip | Trusted Firmware-M | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig and dts files: + +- Common: + + - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi` + +- Secure target: + + - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_defconfig` + - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk.dts` + +- Non-Secure target: + + - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig` + - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.dts` + +Zephyr board options +==================== + +The STM32L562e is an SoC with Cortex-M33 architecture. Zephyr provides support +for building for both Secure and Non-Secure firmware. + +The BOARD options are summarized below: + ++------------------------------+-------------------------------------------+ +| BOARD | Description | ++==============================+===========================================+ +| stm32l562e_dk | For building Trust Zone Disabled firmware | ++------------------------------+-------------------------------------------+ +| stm32l562e_dk/stm32l562xx/ns | For building Non-Secure firmware | ++------------------------------+-------------------------------------------+ + +Here are the instructions to build Zephyr with a non-secure configuration, +using `tfm_ipc_` sample: + + .. code-block:: bash + + $ west build -b stm32l562e_dk/stm32l562xx/ns samples/tfm_integration/tfm_ipc/ + +Once done, before flashing, you need to first run a generated script that +will set platform option bytes config and erase platform (among others, +option bit TZEN will be set). + + .. code-block:: bash + + $ ./build/tfm/regression.sh + $ west flash + +Please note that, after having run a TFM sample on the board, you will need to +run `./build/tfm/regression.sh` once more to clean up the board from secure +options and get back the platform back to a "normal" state and be able to run +usual, non-TFM, binaries. +Also note that, even then, TZEN will remain set, and you will need to use +STM32CubeProgrammer_ to disable it fully, if required. + +Connections and IOs +=================== + +STM32L562E-DK Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32L562E-DK Discovery board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART_1 TX/RX : PA9/PA10 +- USART_3 TX/RX : PC10/PC11 +- I2C_1 SCL/SDA : PB6/PB7 +- SPI_1 SCK/MISO/MOSI : PG2/PG3/PG4 (BT SPI bus) +- SPI_3 NSS/SCK/MISO/MOSI : PE0/PG9/PB4/PB5 (Arduino SPI) +- USER_PB : PC13 +- LD10 : PG12 +- PWM_2_CH1 : PA0 +- DAC1 : PA4 +- ADC1 : PC4 + +System Clock +------------ + +STM32L562E-DK System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +110MHz, driven by 4MHz medium speed internal oscillator. + +Serial Port +----------- + +STM32L562E-DK Discovery board has 6 U(S)ARTs. The Zephyr console output is +assigned to USART1. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``stm32l562e_dk`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32L562E-DK Discovery board includes an ST-LINK/V3E embedded debug tool +interface. Support can be enabled on pyocd by adding "pack" support with the +following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32l562qe + +Alternatively, this interface is supported by the openocd version +included in the Zephyr SDK since v0.13.1. + +Flashing an application to STM32L562E-DK Discovery +-------------------------------------------------- + +Connect the STM32L562E-DK Discovery to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l562e_dk + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! stm32l562e_dk + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +----------------------------------------------------------------------------- + +The TF-M integration sample :ref:`tfm_ipc` can be run on a ST STM32L562E-DK Discovery. +In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image +can be generated using ``stm32l562e_dk/stm32l562xx/ns`` as build target. + +.. code-block:: bash + + $ west build -b stm32l562e_dk/stm32l562xx/ns path/to/source/directory + +Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script +is run automatically in a post-build step to make some required flash layout changes. + +Once the build is completed, run the following script to initialize the option bytes. + +.. code-block:: bash + + $ build/tfm/regression.sh + +Finally, to flash the board, run: + +.. code-block:: bash + + $ west flash --hex-file build/tfm_merged.hex + +Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts +(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` +(which is used for initialization) is available in the PATH. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l562e_dk + :maybe-skip-config: + :goals: debug + +.. _STM32L562E-DK Discovery website: + https://www.st.com/en/evaluation-tools/stm32l562e-dk.html + +.. _STM32L562E-DK Discovery board User Manual: + https://www.st.com/resource/en/user_manual/dm00635554.pdf + +.. _STM32L562QE on www.st.com: + https://www.st.com/en/microcontrollers/stm32l562qe.html + +.. _STM32L562 reference manual: + https://www.st.com/resource/en/reference_manual/DM00346336.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk.dts b/boards/st/stm32l562e_dk/stm32l562e_dk.dts similarity index 100% rename from boards/arm/stm32l562e_dk/stm32l562e_dk.dts rename to boards/st/stm32l562e_dk/stm32l562e_dk.dts diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk.yaml b/boards/st/stm32l562e_dk/stm32l562e_dk.yaml similarity index 100% rename from boards/arm/stm32l562e_dk/stm32l562e_dk.yaml rename to boards/st/stm32l562e_dk/stm32l562e_dk.yaml diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_common.dtsi b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi similarity index 100% rename from boards/arm/stm32l562e_dk/stm32l562e_dk_common.dtsi rename to boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig b/boards/st/stm32l562e_dk/stm32l562e_dk_defconfig similarity index 85% rename from boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig rename to boards/st/stm32l562e_dk/stm32l562e_dk_defconfig index 6646832e7ef..cf7483088e5 100644 --- a/boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L5X=y -CONFIG_SOC_STM32L562XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_ns.dts b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.dts similarity index 100% rename from boards/arm/stm32l562e_dk/stm32l562e_dk_ns.dts rename to boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.dts diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.yaml b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.yaml new file mode 100644 index 00000000000..c092f8da95d --- /dev/null +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.yaml @@ -0,0 +1,21 @@ +identifier: stm32l562e_dk/stm32l562xx/ns +name: ST STM32L562E-DK Discovery non secure +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - counter + - gpio + - i2c + - lptim + - dac + - spi + - arduino_spi + - sdhc + - usb + - usb_device +ram: 192 +flash: 512 +vendor: st diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig new file mode 100644 index 00000000000..d2035929200 --- /dev/null +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm32l562e_dk/support/openocd.cfg b/boards/st/stm32l562e_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32l562e_dk/support/openocd.cfg rename to boards/st/stm32l562e_dk/support/openocd.cfg diff --git a/boards/st/stm32mp157c_dk2/Kconfig.defconfig b/boards/st/stm32mp157c_dk2/Kconfig.defconfig new file mode 100644 index 00000000000..40490cb49c3 --- /dev/null +++ b/boards/st/stm32mp157c_dk2/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32MP157 discovery board configuration + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32MP157C_DK2 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +config CLOCK_STM32_HSE_CLOCK + default 24000000 + +endif # BOARD_STM32MP157_Dk2 diff --git a/boards/st/stm32mp157c_dk2/Kconfig.stm32mp157c_dk2 b/boards/st/stm32mp157c_dk2/Kconfig.stm32mp157c_dk2 new file mode 100644 index 00000000000..f3befe5bc83 --- /dev/null +++ b/boards/st/stm32mp157c_dk2/Kconfig.stm32mp157c_dk2 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32MP157C_DK2 + select SOC_STM32MP15_M4 diff --git a/boards/arm/stm32mp157c_dk2/arduino_r3_connector.dtsi b/boards/st/stm32mp157c_dk2/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32mp157c_dk2/arduino_r3_connector.dtsi rename to boards/st/stm32mp157c_dk2/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32mp157c_dk2/board.cmake b/boards/st/stm32mp157c_dk2/board.cmake similarity index 100% rename from boards/arm/stm32mp157c_dk2/board.cmake rename to boards/st/stm32mp157c_dk2/board.cmake diff --git a/boards/st/stm32mp157c_dk2/board.yml b/boards/st/stm32mp157c_dk2/board.yml new file mode 100644 index 00000000000..d8ffb9a66b5 --- /dev/null +++ b/boards/st/stm32mp157c_dk2/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32mp157c_dk2 + vendor: st + socs: + - name: stm32mp157cxx diff --git a/boards/arm/stm32mp157c_dk2/doc/img/en.stm32mp157c-dk2.jpg b/boards/st/stm32mp157c_dk2/doc/img/en.stm32mp157c-dk2.jpg similarity index 100% rename from boards/arm/stm32mp157c_dk2/doc/img/en.stm32mp157c-dk2.jpg rename to boards/st/stm32mp157c_dk2/doc/img/en.stm32mp157c-dk2.jpg diff --git a/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst b/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst similarity index 98% rename from boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst rename to boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst index 0b92de76c9a..f8f9a4869e2 100644 --- a/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst +++ b/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst @@ -178,8 +178,8 @@ features: | SPI | on-chip | spi | +-----------+------------+-------------------------------------+ -The default configuration can be found in the defconfig file: -``boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig` Connections and IOs diff --git a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.dts b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.dts similarity index 100% rename from boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.dts rename to boards/st/stm32mp157c_dk2/stm32mp157c_dk2.dts diff --git a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml similarity index 100% rename from boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml rename to boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml diff --git a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig similarity index 89% rename from boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig rename to boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig index 66503dc2406..056ce7eddc0 100644 --- a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig +++ b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32MP1X=y -CONFIG_SOC_STM32MP15_M4=y - # enable GPIO CONFIG_GPIO=y diff --git a/boards/arm/stm32mp157c_dk2/support/openocd.cfg b/boards/st/stm32mp157c_dk2/support/openocd.cfg similarity index 100% rename from boards/arm/stm32mp157c_dk2/support/openocd.cfg rename to boards/st/stm32mp157c_dk2/support/openocd.cfg diff --git a/boards/st/stm32u5a9j_dk/Kconfig.stm32u5a9j_dk b/boards/st/stm32u5a9j_dk/Kconfig.stm32u5a9j_dk new file mode 100644 index 00000000000..2609400aa9e --- /dev/null +++ b/boards/st/stm32u5a9j_dk/Kconfig.stm32u5a9j_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32U5A9J_DK + select SOC_STM32U5A9XX diff --git a/boards/arm/stm32u5a9j_dk/board.cmake b/boards/st/stm32u5a9j_dk/board.cmake similarity index 100% rename from boards/arm/stm32u5a9j_dk/board.cmake rename to boards/st/stm32u5a9j_dk/board.cmake diff --git a/boards/st/stm32u5a9j_dk/board.yml b/boards/st/stm32u5a9j_dk/board.yml new file mode 100644 index 00000000000..93bcec39743 --- /dev/null +++ b/boards/st/stm32u5a9j_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32u5a9j_dk + vendor: st + socs: + - name: stm32u5a9xx diff --git a/boards/arm/stm32u5a9j_dk/doc/img/bottom_view.jpg b/boards/st/stm32u5a9j_dk/doc/img/bottom_view.jpg similarity index 100% rename from boards/arm/stm32u5a9j_dk/doc/img/bottom_view.jpg rename to boards/st/stm32u5a9j_dk/doc/img/bottom_view.jpg diff --git a/boards/arm/stm32u5a9j_dk/doc/img/top_view.jpg b/boards/st/stm32u5a9j_dk/doc/img/top_view.jpg similarity index 100% rename from boards/arm/stm32u5a9j_dk/doc/img/top_view.jpg rename to boards/st/stm32u5a9j_dk/doc/img/top_view.jpg diff --git a/boards/st/stm32u5a9j_dk/doc/index.rst b/boards/st/stm32u5a9j_dk/doc/index.rst new file mode 100644 index 00000000000..aed555a4057 --- /dev/null +++ b/boards/st/stm32u5a9j_dk/doc/index.rst @@ -0,0 +1,198 @@ +.. _stm32u5a9j_dk_board: + +ST STM32U5A9J Discovery Kit +########################### + +Overview +******** + +The STM32U5A9J-DK Discovery kit is a complete demonstration and development +platform for the STM32U5A9NJH6Q microcontroller, featuring an Arm® Cortex®-M33 +core with Arm® TrustZone®. + +Leveraging the innovative ultra-low-power oriented features, 2.5 Mbytes of +embedded SRAM, 4 Mbytes of embedded flash memory, and rich graphics features, +the STM32U5A9J-DK Discovery kit enables users to easily prototype applications +with state-of-the-art energy efficiency, as well as providing stunning and +optimized graphics rendering with the support of the 2.5D NeoChrom Accelerator, +Chrom-ART Accelerator, and Chrom-GRC™ MMU. + +The full range of hardware features available on the board helps users to +enhance their application development by an evaluation of all the peripherals +such as a 2.47-inch RGB 480x480 pixels TFT round LCD module with MIPI DSI® +interface and capacitive touch panel, USB Type-C® HS, Octo-SPI flash memory +device, Hexadeca-SPI PSRAM memory device, eMMC flash memory device, +Time-of-Flight and gesture detection sensor, temperature sensor, and two 2.54 mm +pitch double-row flexible expansion connectors for easy prototyping with +daughterboards for specific applications (USART, LPUART, two SPIs, SAI, three +I2C, SDMMC, ADCs, timers, and GPIOs). + +The STM32U5A9J-DK Discovery kit integrates an STLINK-V3E embedded in-circuit +debugger and programmer for the STM32 microcontroller with a USB Virtual COM +port bridge and comes with the STM32CubeU5 MCU Package, which provides an STM32 +comprehensive software HAL library as well as various software examples. + +.. image:: img/top_view.jpg + :align: center + :alt: STM32U5A9J-DK Top View + +.. image:: img/bottom_view.jpg + :align: center + :alt: STM32U5A9J-DK Bottom View + +More information about the board can be found at the `STM32U5A9J-DK website`_. +More information about STM32U5A9NJH6Q can be found here: + +- `STM32U5A9NJ on www.st.com`_ +- `STM32U5 Series reference manual`_ +- `STM32U5Axxx datasheet`_ + +Supported Features +================== + +The current Zephyr stm32u5a9j_dk board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| LPUART | on-chip | low power uart | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration per core can be found in the defconfig file: +:zephyr_file:`boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig` + +Pin Mapping +=========== + +For more details please refer to `STM32U5A9J-DK board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) +- LD3 : PE0 +- LD4 : PE1 +- User Button: PC13 +- USART_3 TX/RX : PB10/PB11 +- LPUART_1 TX/RX : PG7/PG8 +- I2C1 SCL/SDA : PG14/PG13 +- I2C2 SCL/SDA : PF1/PF0 +- I2C6 SCL/SDA : PD1/PD0 +- SPI2 SCK/MISO/MOSI/CS : PB13/PD3/PD4/PB12 +- SPI3 SCK/MISO/MOSI/CS : PG9/PG10/PG11/PG15 +- ADC1 : channel5 PA0, channel14 PC5 +- ADC2 : channel9 PA4 +- ADC4 : channel5 PF14 + +System Clock +============ + +The STM32U5A9J-DK Discovery kit relies on an HSE oscillator (16 MHz crystal) +and an LSE oscillator (32.768 kHz crystal) as clock references. +Using the HSE (instead of HSI) is mandatory to manage the DSI interface for +the LCD module and the USB high‑speed interface. + +Serial Port +=========== + +The STM32U5A9J Discovery kit has up to 4 USARTs, 2 UARTs, and 1 LPUART. +The Zephyr console output is assigned to USART1 which connected to the onboard +ST-LINK/V3.0. Virtual COM port interface. Default communication settings are +115200 8N1. + + +Programming and Debugging +************************* + +STM32U5A9J Discovery kit includes an ST-LINK/V3 embedded debug tool interface. +This probe allows to flash and debug the board using various tools. + +Flashing +======== + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board., + +Connect the STM32U5A9J Discovery board to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 -b 115200 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32u5a9j_dk + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! stm32u5a9j_dk + +Debugging +========= + +Default debugger for this board is openocd. It could be used in the usual way +with "west debug" command. +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32u5a9j_dk + :goals: debug + + +.. _STM32U5A9J-DK website: + https://www.st.com/en/evaluation-tools/stm32u5a9j-dk.html + +.. _STM32U5A9J-DK board User Manual: + https://www.st.com/resource/en/user_manual/um2967-discovery-kit-with-stm32u5a9nj-mcu-stmicroelectronics.pdf + +.. _STM32U5A9NJ on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32u5a9nj.html + +.. _STM32U5 Series reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32U5Axxx datasheet: + https://www.st.com/resource/en/datasheet/stm32u5a9nj.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STM32U5A9J_DK board schematics: + https://www.st.com/resource/en/schematic_pack/mb1829-u5a9njq-b01-schematic.pdf diff --git a/boards/arm/stm32u5a9j_dk/stm32u5a9j_dk.dts b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts similarity index 100% rename from boards/arm/stm32u5a9j_dk/stm32u5a9j_dk.dts rename to boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts diff --git a/boards/arm/stm32u5a9j_dk/stm32u5a9j_dk.yaml b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.yaml similarity index 100% rename from boards/arm/stm32u5a9j_dk/stm32u5a9j_dk.yaml rename to boards/st/stm32u5a9j_dk/stm32u5a9j_dk.yaml diff --git a/boards/arm/stm32u5a9j_dk/stm32u5a9j_dk_defconfig b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig similarity index 80% rename from boards/arm/stm32u5a9j_dk/stm32u5a9j_dk_defconfig rename to boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig index 71e92cf0450..93c31903765 100644 --- a/boards/arm/stm32u5a9j_dk/stm32u5a9j_dk_defconfig +++ b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2023 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 -# Set SoC present on the board -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U5A9XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32u5a9j_dk/support/openocd.cfg b/boards/st/stm32u5a9j_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32u5a9j_dk/support/openocd.cfg rename to boards/st/stm32u5a9j_dk/support/openocd.cfg diff --git a/boards/st/stm32vl_disco/Kconfig.stm32vl_disco b/boards/st/stm32vl_disco/Kconfig.stm32vl_disco new file mode 100644 index 00000000000..d14fa18d468 --- /dev/null +++ b/boards/st/stm32vl_disco/Kconfig.stm32vl_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Jonas Eriksson, Up to Code AB +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32VL_DISCO + select SOC_STM32F100XB diff --git a/boards/arm/stm32vl_disco/board.cmake b/boards/st/stm32vl_disco/board.cmake similarity index 100% rename from boards/arm/stm32vl_disco/board.cmake rename to boards/st/stm32vl_disco/board.cmake diff --git a/boards/st/stm32vl_disco/board.yml b/boards/st/stm32vl_disco/board.yml new file mode 100644 index 00000000000..15c8b5b3cac --- /dev/null +++ b/boards/st/stm32vl_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32vl_disco + vendor: st + socs: + - name: stm32f100xb diff --git a/boards/arm/stm32vl_disco/doc/img/stm32vl_disco.jpg b/boards/st/stm32vl_disco/doc/img/stm32vl_disco.jpg similarity index 100% rename from boards/arm/stm32vl_disco/doc/img/stm32vl_disco.jpg rename to boards/st/stm32vl_disco/doc/img/stm32vl_disco.jpg diff --git a/boards/st/stm32vl_disco/doc/index.rst b/boards/st/stm32vl_disco/doc/index.rst new file mode 100644 index 00000000000..e676e4ab426 --- /dev/null +++ b/boards/st/stm32vl_disco/doc/index.rst @@ -0,0 +1,188 @@ +.. _stm32vl_disco_board: + +ST STM32VL Discovery +#################### + +Overview +******** + +The STM32 Discovery series comes in many varieties, in this case the "Value +Line" STM32F100x SoC series is showcased. Like other Discovery board, an +integrated ST-LINK debugger and programmer is included (V1), but the only +included I/O devices are two user LEDs and one user button. + +.. image:: img/stm32vl_disco.jpg + :align: center + :alt: STM32VLDISCOVERY + +More information about the board can be found at the `STM32VLDISCOVERY website`_. + +Hardware +******** + +The STM32 Discovery board features: + +- On-board ST-LINK/V1 with selection mode switch to use the kit as a standalone + ST-LINK/V1 (with SWD connector for programming and debugging) +- Board power supply: through USB bus or from an external 5 V supply voltage +- External application power supply: 3 V and 5 V +- Four LEDs: + + - LD1 (red) for 3.3 V power on + - LD2 (red/green) for USB communication + - LD3 (green) for PC9 output + - LD4 (blue) for PC8 output +- Two push buttons (user and reset) +- Extension header for all LQFP64 I/Os for quick connection to prototyping board + and easy probing + +More information about the STM32F100x can be found in the +`STM32F100x reference manual`_ and the `STM32F100x data sheet`_. + +Supported Features +================== + +The Zephyr stm32vl_disco board configuration supports the following hardware features: + +.. list-table:: Supported hardware + :header-rows: 1 + + * - Interface + - Controller + - Driver/component + * - NVIC + - on-chip + - nested vector interrupt controller + * - UART + - on-chip + - serial port-polling + serial port-interrupt + * - PINMUX + - on-chip + - pinmux + * - GPIO + - on-chip + - gpio + * - CLOCK + - on-chip + - reset and clock control + * - FLASH + - on-chip + - flash memory + * - WATCHDOG + - on-chip + - window watchdog + * - I2C + - on-chip + - i2c + * - SPI + - on-chip + - spi + * - ADC + - on-chip + - adc + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32vl_disco/stm32vl_disco_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- UART_3_TX : PB10 +- UART_3_RX : PB11 +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PB11 + +For more details please refer to `STM32VLDISCOVERY board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``stm32vl_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32VLDISCOVERY board includes an ST-LINK/V1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application +----------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32vl_disco + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32vl_disco + :maybe-skip-config: + :goals: debug + +USB mass storage issues +======================= + +The ST-LINK/V1 includes a buggy USB mass storage gadget. To connect to the +ST-LINK from Linux, you might need to ignore the device using modprobe +configuration parameters: + +.. code-block:: shell + + $ echo "options usb-storage quirks=483:3744:i" | sudo tee /etc/modprobe.d/local.conf + $ sudo modprobe -r usb-storage + +References +********** + +.. target-notes:: + +.. _STM32VLDISCOVERY website: + https://www.st.com/en/evaluation-tools/stm32vldiscovery.html + +.. _STM32F100x reference manual: + https://www.st.com/resource/en/reference_manual/cd00246267.pdf + +.. _STM32F100x data sheet: + https://www.st.com/resource/en/datasheet/stm32f100cb.pdf + +.. _STM32VLDISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/cd00267113.pdf diff --git a/boards/arm/stm32vl_disco/stm32vl_disco.dts b/boards/st/stm32vl_disco/stm32vl_disco.dts similarity index 100% rename from boards/arm/stm32vl_disco/stm32vl_disco.dts rename to boards/st/stm32vl_disco/stm32vl_disco.dts diff --git a/boards/arm/stm32vl_disco/stm32vl_disco.yaml b/boards/st/stm32vl_disco/stm32vl_disco.yaml similarity index 100% rename from boards/arm/stm32vl_disco/stm32vl_disco.yaml rename to boards/st/stm32vl_disco/stm32vl_disco.yaml diff --git a/boards/arm/stm32vl_disco/stm32vl_disco_defconfig b/boards/st/stm32vl_disco/stm32vl_disco_defconfig similarity index 80% rename from boards/arm/stm32vl_disco/stm32vl_disco_defconfig rename to boards/st/stm32vl_disco/stm32vl_disco_defconfig index ee2e8b8462a..9472e788675 100644 --- a/boards/arm/stm32vl_disco/stm32vl_disco_defconfig +++ b/boards/st/stm32vl_disco/stm32vl_disco_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Platform Configuration -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F100XB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32vl_disco/support/openocd.cfg b/boards/st/stm32vl_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32vl_disco/support/openocd.cfg rename to boards/st/stm32vl_disco/support/openocd.cfg diff --git a/boards/st/stm32wb5mm_dk/Kconfig.defconfig b/boards/st/stm32wb5mm_dk/Kconfig.defconfig new file mode 100644 index 00000000000..37be19b4d1c --- /dev/null +++ b/boards/st/stm32wb5mm_dk/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32WB5MM-DK Discovery Development board configuration + +# Copyright (c) 2024 Javad Rahimipetroudi +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32WB5MM_DK + +choice BT_HCI_BUS_TYPE + default BT_STM32_IPM + depends on BT +endchoice + +endif diff --git a/boards/st/stm32wb5mm_dk/Kconfig.stm32wb5mm_dk b/boards/st/stm32wb5mm_dk/Kconfig.stm32wb5mm_dk new file mode 100644 index 00000000000..209ab102ba5 --- /dev/null +++ b/boards/st/stm32wb5mm_dk/Kconfig.stm32wb5mm_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Javad Rahimipetroudi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32WB5MM_DK + select SOC_STM32WB55XX diff --git a/boards/arm/stm32wb5mm_dk/board.cmake b/boards/st/stm32wb5mm_dk/board.cmake similarity index 100% rename from boards/arm/stm32wb5mm_dk/board.cmake rename to boards/st/stm32wb5mm_dk/board.cmake diff --git a/boards/st/stm32wb5mm_dk/board.yml b/boards/st/stm32wb5mm_dk/board.yml new file mode 100644 index 00000000000..5df998d28c1 --- /dev/null +++ b/boards/st/stm32wb5mm_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32wb5mm_dk + vendor: st + socs: + - name: stm32wb55xx diff --git a/boards/arm/stm32wb5mm_dk/doc/img/STM32WB5MM_DK.jpg b/boards/st/stm32wb5mm_dk/doc/img/STM32WB5MM_DK.jpg similarity index 100% rename from boards/arm/stm32wb5mm_dk/doc/img/STM32WB5MM_DK.jpg rename to boards/st/stm32wb5mm_dk/doc/img/STM32WB5MM_DK.jpg diff --git a/boards/arm/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst similarity index 99% rename from boards/arm/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst rename to boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst index 61b70106601..a149ea79a36 100644 --- a/boards/arm/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst +++ b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst @@ -126,7 +126,7 @@ The Zephyr STM32WB5MM-DK board configuration supports the following hardware fea Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: -``boards/arm/stm32wb5mm_dk/stm32wb5mm_dk_defconfig`` +:zephyr_file:`boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig` Bluetooth and compatibility with STM32WB Copro Wireless Binaries ================================================================ diff --git a/boards/arm/stm32wb5mm_dk/stm32wb5mm_dk.dts b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts similarity index 100% rename from boards/arm/stm32wb5mm_dk/stm32wb5mm_dk.dts rename to boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts diff --git a/boards/arm/stm32wb5mm_dk/stm32wb5mm_dk.yaml b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml similarity index 100% rename from boards/arm/stm32wb5mm_dk/stm32wb5mm_dk.yaml rename to boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml diff --git a/boards/arm/stm32wb5mm_dk/stm32wb5mm_dk_defconfig b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig similarity index 83% rename from boards/arm/stm32wb5mm_dk/stm32wb5mm_dk_defconfig rename to boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig index 9fdd732848e..75373aa997c 100644 --- a/boards/arm/stm32wb5mm_dk/stm32wb5mm_dk_defconfig +++ b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WBX=y -CONFIG_SOC_STM32WB55XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/stm32wb5mm_dk/support/openocd.cfg b/boards/st/stm32wb5mm_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32wb5mm_dk/support/openocd.cfg rename to boards/st/stm32wb5mm_dk/support/openocd.cfg diff --git a/boards/st/stm32wb5mmg/Kconfig.defconfig b/boards/st/stm32wb5mmg/Kconfig.defconfig new file mode 100644 index 00000000000..e63531f897b --- /dev/null +++ b/boards/st/stm32wb5mmg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32WB5MMG Bluetooth module board configuration + +# Copyright (c) 2024 Javad Rahimipetroudi +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32WB5MMG + +choice BT_HCI_BUS_TYPE + default BT_STM32_IPM + depends on BT +endchoice + +endif diff --git a/boards/st/stm32wb5mmg/Kconfig.stm32wb5mmg b/boards/st/stm32wb5mmg/Kconfig.stm32wb5mmg new file mode 100644 index 00000000000..7e755aa1505 --- /dev/null +++ b/boards/st/stm32wb5mmg/Kconfig.stm32wb5mmg @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Javad Rahimipetroudi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32WB5MMG + select SOC_STM32WB55XX diff --git a/boards/arm/stm32wb5mmg/board.cmake b/boards/st/stm32wb5mmg/board.cmake similarity index 100% rename from boards/arm/stm32wb5mmg/board.cmake rename to boards/st/stm32wb5mmg/board.cmake diff --git a/boards/st/stm32wb5mmg/board.yml b/boards/st/stm32wb5mmg/board.yml new file mode 100644 index 00000000000..dc90a918930 --- /dev/null +++ b/boards/st/stm32wb5mmg/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32wb5mmg + vendor: st + socs: + - name: stm32wb55xx diff --git a/boards/arm/stm32wb5mmg/doc/img/STM32WB5MMG.jpg b/boards/st/stm32wb5mmg/doc/img/STM32WB5MMG.jpg similarity index 100% rename from boards/arm/stm32wb5mmg/doc/img/STM32WB5MMG.jpg rename to boards/st/stm32wb5mmg/doc/img/STM32WB5MMG.jpg diff --git a/boards/arm/stm32wb5mmg/doc/stm32wb5mmg.rst b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst similarity index 99% rename from boards/arm/stm32wb5mmg/doc/stm32wb5mmg.rst rename to boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst index 90561ee1275..13446524535 100644 --- a/boards/arm/stm32wb5mmg/doc/stm32wb5mmg.rst +++ b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst @@ -179,7 +179,7 @@ The Zephyr STM32WB5MMG board configuration supports the following hardware featu Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: -``boards/arm/stm32wb5mmg/stm32wb5mmg_defconfig`` +:zephyr_file:`boards/st/stm32wb5mmg/stm32wb5mmg_defconfig` Bluetooth and compatibility with STM32WB Copro Wireless Binaries ================================================================ diff --git a/boards/arm/stm32wb5mmg/stm32wb5mmg.dts b/boards/st/stm32wb5mmg/stm32wb5mmg.dts similarity index 100% rename from boards/arm/stm32wb5mmg/stm32wb5mmg.dts rename to boards/st/stm32wb5mmg/stm32wb5mmg.dts diff --git a/boards/arm/stm32wb5mmg/stm32wb5mmg.yaml b/boards/st/stm32wb5mmg/stm32wb5mmg.yaml similarity index 100% rename from boards/arm/stm32wb5mmg/stm32wb5mmg.yaml rename to boards/st/stm32wb5mmg/stm32wb5mmg.yaml diff --git a/boards/arm/stm32wb5mmg/stm32wb5mmg_defconfig b/boards/st/stm32wb5mmg/stm32wb5mmg_defconfig similarity index 83% rename from boards/arm/stm32wb5mmg/stm32wb5mmg_defconfig rename to boards/st/stm32wb5mmg/stm32wb5mmg_defconfig index 9fdd732848e..75373aa997c 100644 --- a/boards/arm/stm32wb5mmg/stm32wb5mmg_defconfig +++ b/boards/st/stm32wb5mmg/stm32wb5mmg_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WBX=y -CONFIG_SOC_STM32WB55XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/stm32wb5mmg/support/openocd.cfg b/boards/st/stm32wb5mmg/support/openocd.cfg similarity index 100% rename from boards/arm/stm32wb5mmg/support/openocd.cfg rename to boards/st/stm32wb5mmg/support/openocd.cfg diff --git a/boards/synopsys/em_starterkit/CMakeLists.txt b/boards/synopsys/em_starterkit/CMakeLists.txt new file mode 100644 index 00000000000..b936308cb37 --- /dev/null +++ b/boards/synopsys/em_starterkit/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +if((CONFIG_BOARD_EM_STARTERKIT_EMSK_EM9D OR CONFIG_BOARD_EM_STARTERKIT_EMSK_EM11D) AND "${BOARD_REVISION}" STREQUAL "2.2") + message(FATAL_ERROR "Board revision 2.2 is not supported for this SoC") +endif() + +zephyr_sources(pmodmux.c) +zephyr_sources_ifdef(CONFIG_ARC_MPU_ENABLE arc_mpu_regions.c) diff --git a/boards/synopsys/em_starterkit/Kconfig.defconfig b/boards/synopsys/em_starterkit/Kconfig.defconfig new file mode 100644 index 00000000000..7713228ddb8 --- /dev/null +++ b/boards/synopsys/em_starterkit/Kconfig.defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +if BOARD_EM_STARTERKIT + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 100 + +endif # I2C_DW + +endif # BOARD_EM_STARTERKIT diff --git a/boards/synopsys/em_starterkit/Kconfig.em_starterkit b/boards/synopsys/em_starterkit/Kconfig.em_starterkit new file mode 100644 index 00000000000..33967621dde --- /dev/null +++ b/boards/synopsys/em_starterkit/Kconfig.em_starterkit @@ -0,0 +1,17 @@ +# DesignWare ARC EM Starter Kit board configuration + +# Copyright (c) 2016 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EM_STARTERKIT + select SOC_EMSK + select SOC_EMSK_EM7D if BOARD_EM_STARTERKIT_EMSK_EM7D + select SOC_EMSK_EM9D if BOARD_EM_STARTERKIT_EMSK_EM9D + select SOC_EMSK_EM11D if BOARD_EM_STARTERKIT_EMSK_EM11D + help + The DesignWare ARC EM Starter Kit board is a board + that can host up to 3 different SOC FPGA bit files. + Both version 2.2 and 2.3 firmware have EM7D, EM9D and EM11D configurations. + EM9D using CCM memories and is a Harvard Architecture. + EM7D and EM11D have access to 128MB DRAM and use i-cache and d-cache. + EM7D of EMSK 2.3 supports secure mode. diff --git a/boards/arc/em_starterkit/arc_mpu_regions.c b/boards/synopsys/em_starterkit/arc_mpu_regions.c similarity index 100% rename from boards/arc/em_starterkit/arc_mpu_regions.c rename to boards/synopsys/em_starterkit/arc_mpu_regions.c diff --git a/boards/synopsys/em_starterkit/board.cmake b/boards/synopsys/em_starterkit/board.cmake new file mode 100644 index 00000000000..48fa1722e4d --- /dev/null +++ b/boards/synopsys/em_starterkit/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +board_runner_args(openocd "--use-elf") +board_runner_args(mdb-hw "--jtag=digilent") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/synopsys/em_starterkit/board.dtsi b/boards/synopsys/em_starterkit/board.dtsi new file mode 100644 index 00000000000..f447d53e2fc --- /dev/null +++ b/boards/synopsys/em_starterkit/board.dtsi @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright (c) 2017 Synopsys */ + +#include + +/ { + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + led4 = &led4; + led5 = &led5; + led6 = &led6; + led7 = &led7; + led8 = &led8; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio1 0 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpio1 1 0>; + label = "LED 1"; + }; + led2: led_2 { + gpios = <&gpio1 2 0>; + label = "LED 2"; + }; + led3: led_3 { + gpios = <&gpio1 3 0>; + label = "LED 3"; + }; + led4: led_4 { + gpios = <&gpio1 4 0>; + label = "LED 4"; + }; + led5: led_5 { + gpios = <&gpio1 5 0>; + label = "LED 5"; + }; + led6: led_6 { + gpios = <&gpio1 6 0>; + label = "LED 6"; + }; + led7: led_7 { + gpios = <&gpio1 7 0>; + label = "LED 7"; + }; + led8: led_8 { + gpios = <&gpio1 8 0>; + label = "LED 8"; + }; + + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + label = "Push button switch 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button2: button_2 { + /* gpio flags need validation */ + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "Push button switch 2"; + zephyr,code = ; + }; + switch0: switch_0 { + /* gpio flags need validation */ + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + label = "DIP SW1 - Switch 1"; + zephyr,code = ; + }; + switch1: switch_1 { + /* gpio flags need validation */ + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + label = "DIP SW1 - Switch 2"; + zephyr,code = ; + }; + switch2: switch_2 { + /* gpio flags need validation */ + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + label = "DIP SW1 - Switch 3"; + zephyr,code = ; + }; + switch3: switch_3 { + /* gpio flags need validation */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + label = "DIP SW1 - Switch 4"; + zephyr,code = ; + }; + }; + +}; diff --git a/boards/synopsys/em_starterkit/board.yml b/boards/synopsys/em_starterkit/board.yml new file mode 100644 index 00000000000..b5c30f1ba9d --- /dev/null +++ b/boards/synopsys/em_starterkit/board.yml @@ -0,0 +1,13 @@ +board: + name: em_starterkit + vendor: snps + socs: + - name: emsk_em7d + - name: emsk_em9d + - name: emsk_em11d + revision: + format: major.minor.patch + default: "2.3" + revisions: + - name: "2.2" + - name: "2.3" diff --git a/boards/arc/em_starterkit/doc/em_starterkit.jpg b/boards/synopsys/em_starterkit/doc/em_starterkit.jpg similarity index 100% rename from boards/arc/em_starterkit/doc/em_starterkit.jpg rename to boards/synopsys/em_starterkit/doc/em_starterkit.jpg diff --git a/boards/synopsys/em_starterkit/doc/index.rst b/boards/synopsys/em_starterkit/doc/index.rst new file mode 100644 index 00000000000..9d71b4f7678 --- /dev/null +++ b/boards/synopsys/em_starterkit/doc/index.rst @@ -0,0 +1,318 @@ +.. _em_starterkit: + +DesignWare(R) ARC(R) EM Starter Kit +################################### + +Overview +******** + +The DesignWare(R) ARC(R) EM Starter Kit is a low-cost, versatile solution +enabling rapid software development and software debugging, and profiling +for the ARC EM Family of processors. The EM Family includes the EM4, EM6, +EM5D, EM7D, EM9D, and EM11D cores. The Zephyr RTOS can be used with the +EM Starter Kit. + +.. image:: em_starterkit.jpg + :align: center + :alt: DesignWare(R) ARC(R) EM Starter Kit (synopsys.com) + +The ARC EM Starter Kit consists of a hardware platform, including pre-installed +FPGA images of different ARC EM processor configurations with peripherals. +Documentation for this board can be found at `embARC website`_. + +See also this URL for details about the board: +`Designware ARC EM Starter Kit website`_ . + +The latest version of EM Starter Kit is 2.3, developer can upgrade from +2.0/2.1/2.2 to 2.3 using latest firmware. +The default configuration for EM Starter Kit boards can be found in +:zephyr_file:`boards/synopsys/em_starterkit/em_starterkit_defconfig`. + +The default SoC for this board supported in Zephyr is the EM9D. +This configuration is a Harvard Architecture, with a separate +instruction bus and data bus. Instruction memory is called ICCM +and data memory is called DCCM. The configuration file for EM9D +is found in :zephyr_file:`soc/synopsys/emsk/Kconfig.defconfig.em9d`. + +If you have a larger program, you can select the EM7D or EM11D, which gives +access to 128KB DRAM with i-cache and d-cache. The configuration file for EM7D +is found in :zephyr_file:`soc/synopsys/emsk/Kconfig.defconfig.em7d` and EM11D is +found in :zephyr_file:`soc/synopsys/emsk/Kconfig.defconfig.em11d`. + + +Hardware +******** +Board Layout +============ + +The ARC EM Starter Kit main board has 6 Pmod connectors. These can be configured +to support attachment of GPIO, I2C, UART or SPI devices. + +The board also has a 16MB SPI-FLASH and an SDCard for storage. There are 9 LEDs, +3 buttons, and 4 dip switches that can be used with GPIO. + +The Xilinx Spartan(R)-6 LX150 FPGA can auto-load one of 3 FPGA SoC bit files +which have the EM7D, EM9D, or EM11D SoC. + +Documentation and general information for the board can be found at the +`embARC website`_, which also includes some free sample software. + + +Supported Firmware Versions +=========================== + +The EM Starter Kit has different versions, such as 1.0, 1.1, 2.0, 2.1, +2.2 and 2.3. +In Zephyr, only firmware versions 2.2 and 2.3 are supported. + +Supported Features +================== + +The Zephyr kernel supports multiple hardware features on the EM Starter Kit +through the use of device drivers. + +The EM Starter Kit supports 6 Digilent Pmod(TM) Interfaces, which enables the +use of a large variety of pluggable modules for storage, communications, +sensors, displays, etc. With the Pmod interface, you can prototype your +applications using the Zephyr RTOS. + +The table below shows which drivers are supported and which functionality can +be found on which architectures: + ++-----------+------------+-----+-------+-----------------------+ +| Interface | Controller |EM9D | EM11D | Driver/Component | ++===========+============+=====+=======+=======================+ +| INT | on-chip | Y | Y | interrupt_controller | ++-----------+------------+-----+-------+-----------------------+ +| UART | usb + | Y | Y | serial port-polling; | +| | 2 Pmods | | | serial port-interrupt | ++-----------+------------+-----+-------+-----------------------+ +| SPI | 2 Pmods | Y | Y | spi | ++-----------+------------+-----+-------+-----------------------+ +| ADC | n/a | N | N | adc (can add via Pmod)| ++-----------+------------+-----+-------+-----------------------+ +| I2C | 2 Pmods | Y | Y | i2c | ++-----------+------------+-----+-------+-----------------------+ +| GPIO | 6 Pmods | Y | Y | gpio | ++-----------+------------+-----+-------+-----------------------+ +| PWM | n/a | N | N | pwm | ++-----------+------------+-----+-------+-----------------------+ + +The board has 3 (debounced and interrupting) buttons for use with GPIO, 4 dip +switches, 9 LEDs, SDCard on SPI, and a 16MB SPI-Flash memory. + +The SPI-FLASH driver is supported with sample, which can be found in +``samples/drivers/spi_flash``. + +The SPI-Flash also holds 3 (or 4) separate FPGA CPU bit files, selectable via +dip switch. + +The SPI-Flash is also programmed with a bootloader. The bootloader can copy a +program image from SPI-Flash into executable memory. Zephyr initialization will +copy the initialized data section to the data memory if CONFIG_XIP is used. + + +Programming and Debugging +************************* + +Required Hardware and Software +============================== + +To use Zephyr RTOS applications on the EM Starter Kit board, a few additional +pieces of hardware are required. + +* USB Cable (delivered as part of the ARC EM Starter Kit) + +* The USB cable provides power to the board; however, if the board is to run + standalone, the universal switching power adaptor (110-240V AC to 5V DC), + provided in the package, can be used to power the board. + +* :ref:`The Zephyr SDK ` + +* Terminal emulator software for use with the USB-UART. Suggestion: + `Putty Website`_. + +* (optional) A collection of Pmods. + See `Digilent Pmod Modules`_ or develop your custom interfaces to attach + to the Pmod connector. + +Set up the ARC EM Starter Kit +============================= + +To run Zephyr application on correct arc core of EM Starter Kit, you need to +setup the board correctly. + +* Connect the digilent usb cable from your host to the board. + +* Connect the 5V DC power supply to your board. + +* Select the core configuration of the board by choosing correct dip switch + SW1 settings, then press then FPGA configure button located above the letter + 'C' of the ARC logo on the board. + +* Then the board will be reconfigured with selected core configuration, you + can download and debug Zephyr application now. + +* If you want to know more about how to use this board, you can take a look + at the `ARC EM Starter Kit User Guide`_. + +Set up Zephyr Software +====================== + +Since there are different firmware versions of EM Starter Kit, you need to +choose the proper firmware version supported in Zephyr. + +Three different configurations exist for this board: + +* EM7D: em_starterkit_em7d_defconfig +* EM9D: em_starterkit_defconfig +* EM11D: em_starterkit_em11d_defconfig + + +Building Sample Applications +============================== + +You can try many of the sample applications or tests, but let us discuss +the one called :ref:`hello_world`. +It is found in :zephyr_file:`samples/hello_world`. + +Configuring +----------- + +You may need to write a prj_arc.conf file if the sample doesn't have one. +Next, you can use the menuconfig rule to configure the target. By +specifying ``em_starterkit`` as the board configuration, you can select the ARC +EM Starter Kit board support for Zephyr. + +.. zephyr-app-commands:: + :board: em_starterkit + :zephyr-app: samples/hello_world + :goals: menuconfig + +On this board you will also need to consider the "ARC SoC Selection" and set +it either to EM9D or EM11D. To boot up the EM9D on the board, all dip +switches should be UP except for switch 1. Other configuration choices +are made in the normal way. To boot up the EM11D on the board, +all dip switches should be UP except for switch 2. Next press the button +above the letter C in the "ARC" logo on the silkscreen. + +Building +-------- + +You can build application in the usual way. Refer to +:ref:`build_an_application` for more details. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :board: em_starterkit + :zephyr-app: samples/hello_world + :maybe-skip-config: + :goals: build + +Connecting Serial Output +========================= + +In the default configuration, Zephyr's EM Starter Kit images support +serial output via the UART1 on the board. To enable serial output: + +On your development environment, you will need to: + +* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) +* Specify the tty driver name, for example, on Linux this may be :file:`/dev/ttyUSB1` +* Set the communication settings to: + + +========= ===== +Parameter Value +========= ===== +Baud: 115200 +Data: 8 bits +Parity: None +Stopbits: 1 +========= ===== + +Debugging +========== + +Using the latest version of Zephyr SDK(>=0.9), you can debug and flash +EM Starterkit directly. + +One option is to build and debug the application using the usual +Zephyr build system commands. + +.. zephyr-app-commands:: + :board: em_starterkit + :app: + :goals: debug + +At this point you can do your normal debug session. Set breakpoints and then +'c' to continue into the program. + +The other option is to launch a debug server, as follows. + +.. zephyr-app-commands:: + :board: em_starterkit + :app: + :goals: debugserver + +Then connect to the debug server at the EM Starter Kit from a second +console, from the build directory containing the output :file:`zephyr.elf`. + +.. code-block:: console + + $ cd + $ $ZEPHYR_SDK_INSTALL_DIR/arc-zephyr-elf/bin/arc-zephyr-elf-gdb zephyr.elf + (gdb) target remote localhost:3333 + (gdb) load + (gdb) b main + (gdb) c + +Flashing +======== + +If you just want to download the application to the EM Starter Kit's CCM +or DDR and run, you can do so in the usual way. + +.. zephyr-app-commands:: + :board: em_starterkit + :goals: flash + +This command still uses openocd and gdb to load application elf file +to EM Starter Kit, but it will load application and then run immediately. +If power is lost, the application will also lost due to power loss. + +Most of the time you will not be flashing your program but will instead +debug it using openocd and gdb. The program can be download via the USB +cable into the code and data memories. + +When you are ready to deploy the program so that it boots up automatically +on reset or power-up, you can follow the steps to place the program on +SPI-FLASH. + +For instructions on how to write your program to SPI-FLASH, +refer to the documentation on the ARC EM Starter Kit at the +`embARC website`_, which includes instructions for how to place an +executable image onto the SPI-FLASH in such a way that it is understood +by the bootloader. + +Release Notes +************* + +The following is a list of TODO items: + +* ``GH-2647``: Zephyr needs i-cache API (all targets) +* ``GH-2230``: Zephyr ARC port doesn't yet support nested regular interrupts. +* pinmux driver: Possibly it can be written to configure PMods too. + +References +********** + +.. _embARC website: https://www.embarc.org + +.. _Designware ARC EM Starter Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit + +.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules + +.. _Putty website: http://www.putty.org + +.. _ARC EM Starter Kit User Guide: https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit diff --git a/boards/synopsys/em_starterkit/em_starterkit_defconfig b/boards/synopsys/em_starterkit/em_starterkit_defconfig new file mode 100644 index 00000000000..38979ec4912 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.dts b/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.dts new file mode 100644 index 00000000000..75a23beda8a --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.dts @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "em_starterkit_r23.dtsi" +#include "board.dtsi" + +/ { + model = "em_starterkit-em11d"; + compatible = "snps,em_starterkit-em11d", "snps,em_starterkit"; + + aliases { + uart-0 = &uart0; + uart-1 = &uart1; + uart-2 = &uart2; + }; + + chosen { + zephyr,sram = &ddr0; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + }; + + iccm0: iccm@0 { + compatible = "arc,iccm"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + dccm0: dccm@80000000 { + compatible = "arc,dccm"; + reg = <0x80000000 DT_SIZE_K(64)>; + }; + + xccm@c0000000 { + compatible = "arc,xccm"; + reg = <0xc0000000 DT_SIZE_K(8)>; + }; + + yccm@e0000000 { + compatible = "arc,yccm"; + reg = <0xe0000000 DT_SIZE_K(8)>; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.yaml b/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.yaml new file mode 100644 index 00000000000..3189656c78f --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.yaml @@ -0,0 +1,17 @@ +identifier: em_starterkit/emsk_em11d +name: EM Starterkit EM11D +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +supported: + - i2c + - spi + - gpio +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.dts b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.dts new file mode 100644 index 00000000000..e170df7dd95 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.dts @@ -0,0 +1,5 @@ +/* + * Copyright (c) 2018, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.yaml b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.yaml new file mode 100644 index 00000000000..fe2276e2d73 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.yaml @@ -0,0 +1,17 @@ +identifier: em_starterkit/emsk_em7d +name: EM Starterkit EM7D +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +supported: + - i2c + - spi + - gpio +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_em7d_v22.dts b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.overlay similarity index 100% rename from boards/arc/em_starterkit/em_starterkit_em7d_v22.dts rename to boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.overlay diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.yaml b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.yaml new file mode 100644 index 00000000000..49833304424 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.yaml @@ -0,0 +1,17 @@ +identifier: em_starterkit@2.2/emsk_em7d +name: EM Starterkit EM7D +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +supported: + - i2c + - spi + - gpio +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_em7d.dts b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3.overlay similarity index 100% rename from boards/arc/em_starterkit/em_starterkit_em7d.dts rename to boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3.overlay diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig new file mode 100644 index 00000000000..5ce90449df8 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +CONFIG_ARC_HAS_SECURE=y +CONFIG_TRUSTED_EXECUTION_SECURE=y +CONFIG_INIT_ARCH_HW_AT_BOOT=y diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_defconfig b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_defconfig new file mode 100644 index 00000000000..6685d5f940d --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.dts b/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.dts new file mode 100644 index 00000000000..63f97a13279 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.dts @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "em_starterkit_r23.dtsi" +#include "board.dtsi" + +/ { + model = "em_starterkit-em9d"; + compatible = "snps,em_starterkit-em9d", "snps,em_starterkit"; + + aliases { + uart-0 = &uart0; + uart-1 = &uart1; + uart-2 = &uart2; + }; + + chosen { + zephyr,sram = &dccm0; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + }; + + iccm0: iccm@0 { + compatible = "arc,iccm"; + reg = <0x0 DT_SIZE_K(256)>; + }; + + dccm0: dccm@80000000 { + compatible = "arc,dccm"; + reg = <0x80000000 DT_SIZE_K(128)>; + }; + + xccm@c0000000 { + compatible = "arc,xccm"; + reg = <0xc0000000 DT_SIZE_K(8)>; + }; + + yccm@e0000000 { + compatible = "arc,yccm"; + reg = <0xe0000000 DT_SIZE_K(8)>; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.yaml b/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.yaml new file mode 100644 index 00000000000..34b10ca6d7b --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.yaml @@ -0,0 +1,17 @@ +identifier: em_starterkit/emsk_em9d +name: EM Starterkit +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +supported: + - i2c + - spi + - gpio +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_r22.dtsi b/boards/synopsys/em_starterkit/em_starterkit_r22.dtsi similarity index 100% rename from boards/arc/em_starterkit/em_starterkit_r22.dtsi rename to boards/synopsys/em_starterkit/em_starterkit_r22.dtsi diff --git a/boards/arc/em_starterkit/em_starterkit_r23.dtsi b/boards/synopsys/em_starterkit/em_starterkit_r23.dtsi similarity index 96% rename from boards/arc/em_starterkit/em_starterkit_r23.dtsi rename to boards/synopsys/em_starterkit/em_starterkit_r23.dtsi index ef93abcfd46..3de7425d975 100644 --- a/boards/arc/em_starterkit/em_starterkit_r23.dtsi +++ b/boards/synopsys/em_starterkit/em_starterkit_r23.dtsi @@ -5,6 +5,10 @@ */ / { + aliases { + spi-flash0 = &w25q128bv; + }; + soc { i2c@f0004000 { interrupts = <25 1>; diff --git a/boards/arc/em_starterkit/pmodmux.c b/boards/synopsys/em_starterkit/pmodmux.c similarity index 100% rename from boards/arc/em_starterkit/pmodmux.c rename to boards/synopsys/em_starterkit/pmodmux.c diff --git a/boards/arc/em_starterkit/support/openocd.cfg b/boards/synopsys/em_starterkit/support/openocd.cfg similarity index 100% rename from boards/arc/em_starterkit/support/openocd.cfg rename to boards/synopsys/em_starterkit/support/openocd.cfg diff --git a/boards/arc/emsdp/CMakeLists.txt b/boards/synopsys/emsdp/CMakeLists.txt similarity index 100% rename from boards/arc/emsdp/CMakeLists.txt rename to boards/synopsys/emsdp/CMakeLists.txt diff --git a/boards/synopsys/emsdp/Kconfig.defconfig b/boards/synopsys/emsdp/Kconfig.defconfig new file mode 100644 index 00000000000..cfe387e3f25 --- /dev/null +++ b/boards/synopsys/emsdp/Kconfig.defconfig @@ -0,0 +1,15 @@ +# DesignWare ARC EM Software Development Platform board configuration + +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EMSDP + +if SPI + +config SPI_DW + default y + +endif # SPI + +endif # BOARD_EMSDP diff --git a/boards/synopsys/emsdp/Kconfig.emsdp b/boards/synopsys/emsdp/Kconfig.emsdp new file mode 100644 index 00000000000..55afa1582b6 --- /dev/null +++ b/boards/synopsys/emsdp/Kconfig.emsdp @@ -0,0 +1,21 @@ +# DesignWare ARC EM Software Development Platform board configuration + +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EMSDP + select SOC_ARC_EMSDP + select SOC_EMSDP_EM4 if BOARD_EMSDP_EMSDP_EM4 + select SOC_EMSDP_EM5D if BOARD_EMSDP_EMSDP_EM5D + select SOC_EMSDP_EM6 if BOARD_EMSDP_EMSDP_EM6 + select SOC_EMSDP_EM7D if BOARD_EMSDP_EMSDP_EM7D + select SOC_EMSDP_EM7D_ESP if BOARD_EMSDP_EMSDP_EM7D_ESP + select SOC_EMSDP_EM9D if BOARD_EMSDP_EMSDP_EM9D + select SOC_EMSDP_EM11D if BOARD_EMSDP_EMSDP_EM11D + help + The ARC EM Software Development Platform (emsdp) is an FPGA based + development platform intended to support ARC licenses in developing + their software for the ARC EM processor family and ARC EM Subsystems. + It has the support for ARC EM4, EM5D, EM6, EM7D, EM9D and EM11D + processors. ARC EM Enhanced Security Package (ESP) and ARC EM + Subsystems (DFSS, SCSS, DSS) are also supported. diff --git a/boards/arc/emsdp/arc_mpu_regions.c b/boards/synopsys/emsdp/arc_mpu_regions.c similarity index 100% rename from boards/arc/emsdp/arc_mpu_regions.c rename to boards/synopsys/emsdp/arc_mpu_regions.c diff --git a/boards/arc/em_starterkit/board.cmake b/boards/synopsys/emsdp/board.cmake similarity index 100% rename from boards/arc/em_starterkit/board.cmake rename to boards/synopsys/emsdp/board.cmake diff --git a/boards/arc/emsdp/board.dtsi b/boards/synopsys/emsdp/board.dtsi similarity index 100% rename from boards/arc/emsdp/board.dtsi rename to boards/synopsys/emsdp/board.dtsi diff --git a/boards/synopsys/emsdp/board.yml b/boards/synopsys/emsdp/board.yml new file mode 100644 index 00000000000..463c30bc2fc --- /dev/null +++ b/boards/synopsys/emsdp/board.yml @@ -0,0 +1,11 @@ +board: + name: emsdp + vendor: snps + socs: + - name: emsdp_em4 + - name: emsdp_em5d + - name: emsdp_em6 + - name: emsdp_em7d + - name: emsdp_em7d_esp + - name: emsdp_em9d + - name: emsdp_em11d diff --git a/boards/arc/emsdp/doc/emsdp.jpg b/boards/synopsys/emsdp/doc/emsdp.jpg similarity index 100% rename from boards/arc/emsdp/doc/emsdp.jpg rename to boards/synopsys/emsdp/doc/emsdp.jpg diff --git a/boards/synopsys/emsdp/doc/index.rst b/boards/synopsys/emsdp/doc/index.rst new file mode 100644 index 00000000000..fa4606d98f8 --- /dev/null +++ b/boards/synopsys/emsdp/doc/index.rst @@ -0,0 +1,286 @@ +.. _emsdp: + +DesignWare(R) ARC(R) EM Software Development Platform +##################################################### + +Overview +******** + +The DesignWare® ARC® EM Software Development Platform (SDP) is a flexible platform +for rapid software development on ARC EM processor-based subsystems. It is intended +to accelerate software development and debug of ARC EM processors and subsystems for +a wide range of ultra-low power embedded applications such as IoT, sensor fusion, +and voice applications. + +.. image:: emsdp.jpg + :align: center + :alt: DesignWare(R) ARC(R) EM Software Development Platform (synopsys.com) + +For details about the board, see: `DesignWare ARC EM Software Development Platform +(EM SDP) `__ + + +Hardware +******** + +The EM Software Development Platform supports different core configurations, such as EM4, +EM5D, EM6, EM7D, EM7D+ESP, EM9D, EM11D. The core must be supplied as the variant of the base +board which takes the form ``emsdp/`` whereby core is ``emsdp_em4`` for EM4, +``emsdp_em5D`` for EM5D, ``emsdp_em6`` for EM6, ``emsdp_em7d`` for EM7D, ``emsdp_em7d_esp`` +for EM7D+ESP, ``emsdp_em9d`` for EM9D and ``emsdp_em11d`` for EM11D. + +The following table shows the hardware features supported for different core configuration: + ++-----------+-----+-----+------+------+----------+------+-------+ +| Features | EM4 | EM6 | EM5D | EM7D | EM7D_ESP | EM9D | EM11D | ++===========+=====+=====+======+======+==========+======+=======+ +| Caches | N | Y | N | Y | Y | N | Y | ++-----------+-----+-----+------+------+----------+------+-------+ +| DSP | N | N | Y | Y | Y | Y | Y | ++-----------+-----+-----+------+------+----------+------+-------+ +| XY Memory | N | N | N | N | N | Y | Y | ++-----------+-----+-----+------+------+----------+------+-------+ +| Secure | N | N | N | N | Y | N | N | ++-----------+-----+-----+------+------+----------+------+-------+ + +The table below shows which drivers are currently available in Zephyr. + ++-----------+------------+-------+-----------------------+ +| Interface | Controller | EMSDP | Driver/Component | ++===========+============+=======+=======================+ +| SDIO | on-chip | N | SD-card controller | ++-----------+------------+-------+-----------------------+ +| UART | Arduino + | Y | serial port-polling; | +| | 3 Pmods | | serial port-interrupt | ++-----------+------------+-------+-----------------------+ +| SPI | Arduino + | Y | spi | +| | Pmod + adc | | | ++-----------+------------+-------+-----------------------+ +| ADC | 1 Pmod | N | adc (via spi) | ++-----------+------------+-------+-----------------------+ +| I2C | Arduino + | N | i2c | +| | Pmod | | | ++-----------+------------+-------+-----------------------+ +| GPIO | Arduino + | Y | gpio | +| | Pmod + Pin | | | ++-----------+------------+-------+-----------------------+ +| PWM | Arduino + | N | pwm | +| | Pmod | | | ++-----------+------------+-------+-----------------------+ +| I2S | on-chip | N | Audio interface | ++-----------+------------+-------+-----------------------+ + +Support two 32 MByte Quad-SPI Flash memory, one only contains FPGA image, the other +one is user SPI-FLASH, which is connected via SPI bus and its sample can be found in +``samples/drivers/spi_flash``. + +To configure the FPGA, The ARC EM SDP offers a single USB 2.0 host port, which is +both used to access the FPGAs configuration memory and as a DEBUG/ UART port. + +When connected using the USB cable to a PC, the ARC EM SDP presents itself as a mass +storage device. This allows an FPGA configuration bitstream to be dragged and dropped into +the configuration memory. The FPGA bitstream is automatically loaded into the FPGA device +upon power-on reset, or when the configuration button is pressed. + +For hardware feature details, refer to : `ARC EM Software Development Platform +`__ + +Peripheral driver test and sample +================================= + +``tests/drivers/spi/spi_loopback``: verify DesignWare SPI driver. No need to connect +MISO with MOSI, DW SPI register is configured to internally connect them. This test +use two different speed to verify data transfer with asynchronous functionality. +Note: DW SPI only available on SPI0 and SPI1. + +``samples/drivers/spi_flash``: Verfiy DW SPI and SPI-FLASH on SPI1. First erase the +whole flash then write 4 byte data to the flash. Read from the flash and compare the +result with buffer to check functionality. + +Pinmux interface +================ + +The following pinmux peripheral module standards are supported: + +* Digilent Pmod (3x) + +The ARC EM SDP features three 12-pin Pmod connectors: Pmod_A, Pmod_B, and Pmod_C. +The functionality of the Pmod connectors is programmable and includes GPIO, UART, SPI, +I2C, and PWM (Note: support two type UART Pmod interface: UARTA is newer version). +Multiplexing is controlled by software using the PMOD_MUX_CTRL register. + +* Arduino (1x) + +The ARC EM SDP provides an Arduino shield interface. Multiplexing is controlled by software +using the ARDUINO_MUX_CTRL register. Note: some IO must be programmed in group and can't be +set individually, for details see Table 9 in `EM Software Development Platform user guide`_. + +* MikroBUS (1x) + +Note that since the controllers that are mapped to the MikroBUS are shared with the Arduino +controllers, and therefore the MikroBUS functions are only available when the Arduino +multiplexer ARDUINO_MUX_CTRL is in the default mode (GPIO). + +Programming and Debugging +************************* + +Required Hardware and Software +============================== + +To use Zephyr RTOS applications on the EM Software Development Platform board, +a few additional pieces of hardware are required. + +* A micro USB cable to connect the computer. + +* A universal switching power adaptor (110-240V AC to 12 DC), + provided in the package, which used to power the board. + +* :ref:`The Zephyr SDK ` + +* Terminal emulator software for use with the USB-UART. Suggestion: + `Putty Website`_. + +* (optional) A collection of Pmods, Arduino modules, or Mikro modules. + See `Digilent Pmod Modules`_ or develop your custom interfaces to attach + to the Pmod connector. + +Set up the EM Software Development Platform +=========================================== + +To run Zephyr application on EM Software Development Platform, you need to +setup the board correctly. + +* Connect the 12V DC power supply to your board. + +* Connect the digilent usb cable from your host to the board. + +Set up Zephyr Software +====================== + +Building Sample Applications +============================== + +You can try many of the sample applications or tests, but let us discuss +the one called :ref:`hello_world`. +It is found in :zephyr_file:`samples/hello_world`. + +Configuring +----------- + +You may need to write a prj_arc.conf file if the sample doesn't have one. +Next, you can use the menuconfig rule to configure the target. By specifying +``emsdp`` as the board configuration, you can select the ARC EM Software +Development Platform board support for Zephyr, note that the core also need to +be supplied, for example for the em7d: + +.. zephyr-app-commands:: + :board: emsdp/emsdp_em7d + :zephyr-app: samples/hello_world + :goals: menuconfig + + +Building +-------- + +You can build an application in the usual way. Refer to +:ref:`build_an_application` for more details. Here is an example for +:ref:`hello_world` for the em4. + +.. zephyr-app-commands:: + :board: emsdp/emsdp_em4 + :zephyr-app: samples/hello_world + :maybe-skip-config: + :goals: build + +Connecting Serial Output +========================= + +In the default configuration, Zephyr's EM Software Development Platform images +support serial output via the USB-UART on the board. To enable serial output: + +* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) + +* Specify the tty driver name, for example, on Linux this may be + :file:`/dev/ttyUSB0` + +* Set the communication settings to: + + +========= ===== +Parameter Value +========= ===== +Baud: 115200 +Data: 8 bits +Parity: None +Stopbits: 1 +========= ===== + +Debugging +========== + +Using the latest version of Zephyr SDK(>=0.9), you can debug and flash IoT +Development Kit directly. + +One option is to build and debug the application using the usual +Zephyr build system commands, for example for the em6 + +.. zephyr-app-commands:: + :board: emsdp/emsdp_em6 + :app: + :goals: debug + +At this point you can do your normal debug session. Set breakpoints and then +'c' to continue into the program. + +The other option is to launch a debug server, as follows. + +.. zephyr-app-commands:: + :board: emsdp/emsdp_em6 + :app: + :goals: debugserver + +Then connect to the debug server at the EM Software Development Platform from a +second console, from the build directory containing the output :file:`zephyr.elf`. + +.. code-block:: console + + $ cd + $ $ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/ \ + arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf + (gdb) target remote localhost:3333 + (gdb) load + (gdb) b main + (gdb) c + +Flashing +======== + +If you just want to download the application to the EM Software Development +Platform's CCM and run, you can do so in the usual way. + +.. zephyr-app-commands:: + :board: emsdp/emsdp_em6 + :app: + :goals: flash + +This command still uses openocd and gdb to load the application elf file to EM +Software Development Platform, but it will load the application and immediately run. +If power is removed, the application will be lost since it wasn't written to flash. + +Most of the time you will not be flashing your program but will instead debug +it using openocd and gdb. The program can be download via the USB cable into +the code and data memories. + +References +********** + +.. target-notes:: + +.. _EM Software Development Platform user guide: + https://www.synopsys.com/dw/ipdir.php?ds=arc-em-software-development-platform + +.. _Digilent Pmod Modules: + http://store.digilentinc.com/pmod-modules + +.. _Putty website: + http://www.putty.org diff --git a/boards/arc/emsdp/emsdp-pinctrl.dtsi b/boards/synopsys/emsdp/emsdp-pinctrl.dtsi similarity index 100% rename from boards/arc/emsdp/emsdp-pinctrl.dtsi rename to boards/synopsys/emsdp/emsdp-pinctrl.dtsi diff --git a/boards/arc/emsdp/emsdp_defconfig b/boards/synopsys/emsdp/emsdp_defconfig similarity index 76% rename from boards/arc/emsdp/emsdp_defconfig rename to boards/synopsys/emsdp/emsdp_defconfig index 2480ef52f3b..d8581e40fab 100644 --- a/boards/arc/emsdp/emsdp_defconfig +++ b/boards/synopsys/emsdp/emsdp_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM11D=y -CONFIG_BOARD_EMSDP=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n CONFIG_BUILD_NO_GAP_FILL=y @@ -15,5 +12,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_ARC_MPU_ENABLE=y CONFIG_GPIO=y -CONFIG_SPI=y -CONFIG_PINCTRL=y diff --git a/boards/arc/emsdp/emsdp.dts b/boards/synopsys/emsdp/emsdp_emsdp_em11d.dts similarity index 100% rename from boards/arc/emsdp/emsdp.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em11d.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em11d.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em11d.yaml new file mode 100644 index 00000000000..b9c1868a133 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em11d.yaml @@ -0,0 +1,16 @@ +identifier: emsdp/emsdp_em11d +name: EM Software Development Platform (EM11D) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +supported: + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em11d_defconfig b/boards/synopsys/emsdp/emsdp_emsdp_em11d_defconfig new file mode 100644 index 00000000000..ac2ac3efaaa --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em11d_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI=y +CONFIG_PINCTRL=y diff --git a/boards/arc/emsdp/emsdp_em4.dts b/boards/synopsys/emsdp/emsdp_emsdp_em4.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em4.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em4.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em4.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em4.yaml new file mode 100644 index 00000000000..96f05b3251f --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em4.yaml @@ -0,0 +1,14 @@ +identifier: emsdp/emsdp_em4 +name: EM Software Development Platform (EM4) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/emsdp/emsdp_em5d.dts b/boards/synopsys/emsdp/emsdp_emsdp_em5d.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em5d.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em5d.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em5d.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em5d.yaml new file mode 100644 index 00000000000..91f3c1d1c4e --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em5d.yaml @@ -0,0 +1,14 @@ +identifier: emsdp/emsdp_em5d +name: EM Software Development Platform (EM5D) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em5d_defconfig b/boards/synopsys/emsdp/emsdp_emsdp_em5d_defconfig new file mode 100644 index 00000000000..e3abf3f96b6 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em5d_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em6.dts b/boards/synopsys/emsdp/emsdp_emsdp_em6.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em6.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em6.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em6.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em6.yaml new file mode 100644 index 00000000000..0c74c5b7c21 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em6.yaml @@ -0,0 +1,16 @@ +identifier: emsdp/emsdp_em6 +name: EM Software Development Platform (EM6) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +supported: + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em6_defconfig b/boards/synopsys/emsdp/emsdp_emsdp_em6_defconfig new file mode 100644 index 00000000000..e3abf3f96b6 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em6_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em7d.dts b/boards/synopsys/emsdp/emsdp_emsdp_em7d.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em7d.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em7d.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em7d.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em7d.yaml new file mode 100644 index 00000000000..94dfbdd2af0 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em7d.yaml @@ -0,0 +1,14 @@ +identifier: emsdp/emsdp_em7d +name: EM Software Development Platform (EM7D) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/emsdp/emsdp_em7d_esp.dts b/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em7d_esp.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em7d_esp.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp.yaml new file mode 100644 index 00000000000..fcbc5e24c74 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp.yaml @@ -0,0 +1,16 @@ +identifier: emsdp/emsdp_em7d_esp +name: EM Software Development Platform (EM7D_ESP) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +supported: + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp_defconfig b/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp_defconfig new file mode 100644 index 00000000000..a0da795360a --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARC_HAS_SECURE=y +CONFIG_TRUSTED_EXECUTION_SECURE=y +CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em9d.dts b/boards/synopsys/emsdp/emsdp_emsdp_em9d.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em9d.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em9d.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em9d.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em9d.yaml new file mode 100644 index 00000000000..e22e8d37092 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em9d.yaml @@ -0,0 +1,16 @@ +identifier: emsdp/emsdp_em9d +name: EM Software Development Platform (EM9D) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +supported: + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em9d_defconfig b/boards/synopsys/emsdp/emsdp_emsdp_em9d_defconfig new file mode 100644 index 00000000000..e3abf3f96b6 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em9d_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI=y diff --git a/boards/arc/emsdp/platform.c b/boards/synopsys/emsdp/platform.c similarity index 100% rename from boards/arc/emsdp/platform.c rename to boards/synopsys/emsdp/platform.c diff --git a/boards/arc/emsdp/support/openocd.cfg b/boards/synopsys/emsdp/support/openocd.cfg similarity index 100% rename from boards/arc/emsdp/support/openocd.cfg rename to boards/synopsys/emsdp/support/openocd.cfg diff --git a/boards/arc/hsdk/CMakeLists.txt b/boards/synopsys/hsdk/CMakeLists.txt similarity index 100% rename from boards/arc/hsdk/CMakeLists.txt rename to boards/synopsys/hsdk/CMakeLists.txt diff --git a/boards/synopsys/hsdk/Kconfig.defconfig b/boards/synopsys/hsdk/Kconfig.defconfig new file mode 100644 index 00000000000..65a4731bf53 --- /dev/null +++ b/boards/synopsys/hsdk/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HSDK + +if SPI_DW + +config SPI_DW_ACCESS_WORD_ONLY + default y + +endif # SPI_DW + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 200 + +endif # I2C_DW + +endif # BOARD_HSDK diff --git a/boards/synopsys/hsdk/Kconfig.hsdk b/boards/synopsys/hsdk/Kconfig.hsdk new file mode 100644 index 00000000000..17631e1defb --- /dev/null +++ b/boards/synopsys/hsdk/Kconfig.hsdk @@ -0,0 +1,12 @@ +# DesignWare ARC HS Development Kit board configuration + +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HSDK + select SOC_ARC_HSDK + help + The DesignWare ARC HS Development Kit is a ready-to-use platform for + rapid software development on the ARC HS3x family of processors. It + supports single- and multi-core ARC HS34, HS36 and HS38 processors + and offers a wide range of interfaces diff --git a/boards/synopsys/hsdk/board.cmake b/boards/synopsys/hsdk/board.cmake new file mode 100644 index 00000000000..be0105913d4 --- /dev/null +++ b/boards/synopsys/hsdk/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +board_runner_args(openocd "--use-elf") + +if(${CONFIG_MP_MAX_NUM_CPUS} EQUAL 2) + board_runner_args(openocd "--config=${CMAKE_CURRENT_LIST_DIR}/support/openocd-2-cores.cfg") +endif() + +board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/synopsys/hsdk/board.yml b/boards/synopsys/hsdk/board.yml new file mode 100644 index 00000000000..44363f8a9b8 --- /dev/null +++ b/boards/synopsys/hsdk/board.yml @@ -0,0 +1,7 @@ +board: + name: hsdk + vendor: snps + socs: + - name: arc_hsdk + variants: + - name: 2cores diff --git a/boards/arc/hsdk/doc/arduino_shield_interface.jpg b/boards/synopsys/hsdk/doc/arduino_shield_interface.jpg similarity index 100% rename from boards/arc/hsdk/doc/arduino_shield_interface.jpg rename to boards/synopsys/hsdk/doc/arduino_shield_interface.jpg diff --git a/boards/arc/hsdk/doc/hsdk.jpg b/boards/synopsys/hsdk/doc/hsdk.jpg similarity index 100% rename from boards/arc/hsdk/doc/hsdk.jpg rename to boards/synopsys/hsdk/doc/hsdk.jpg diff --git a/boards/arc/hsdk/doc/index.rst b/boards/synopsys/hsdk/doc/index.rst similarity index 100% rename from boards/arc/hsdk/doc/index.rst rename to boards/synopsys/hsdk/doc/index.rst diff --git a/boards/arc/hsdk/doc/mikrobus_header.jpg b/boards/synopsys/hsdk/doc/mikrobus_header.jpg similarity index 100% rename from boards/arc/hsdk/doc/mikrobus_header.jpg rename to boards/synopsys/hsdk/doc/mikrobus_header.jpg diff --git a/boards/arc/hsdk/doc/pinout_diagram_of_the_pmod.jpg b/boards/synopsys/hsdk/doc/pinout_diagram_of_the_pmod.jpg similarity index 100% rename from boards/arc/hsdk/doc/pinout_diagram_of_the_pmod.jpg rename to boards/synopsys/hsdk/doc/pinout_diagram_of_the_pmod.jpg diff --git a/boards/arc/hsdk/hsdk.dts b/boards/synopsys/hsdk/hsdk.dts similarity index 100% rename from boards/arc/hsdk/hsdk.dts rename to boards/synopsys/hsdk/hsdk.dts diff --git a/boards/arc/hsdk/hsdk.dtsi b/boards/synopsys/hsdk/hsdk.dtsi similarity index 100% rename from boards/arc/hsdk/hsdk.dtsi rename to boards/synopsys/hsdk/hsdk.dtsi diff --git a/boards/arc/hsdk/hsdk.yaml b/boards/synopsys/hsdk/hsdk.yaml similarity index 100% rename from boards/arc/hsdk/hsdk.yaml rename to boards/synopsys/hsdk/hsdk.yaml diff --git a/boards/arc/hsdk/hsdk_2cores.dts b/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores.dts similarity index 100% rename from boards/arc/hsdk/hsdk_2cores.dts rename to boards/synopsys/hsdk/hsdk_arc_hsdk_2cores.dts diff --git a/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores.yaml b/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores.yaml new file mode 100644 index 00000000000..24c50b0b918 --- /dev/null +++ b/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores.yaml @@ -0,0 +1,16 @@ +identifier: hsdk/arc_hsdk/2cores +name: HS Development Kit(2 cores) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools + - arcmwdt +supported: + - smp +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores_defconfig b/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores_defconfig new file mode 100644 index 00000000000..af283689b38 --- /dev/null +++ b/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MP_MAX_NUM_CPUS=2 diff --git a/boards/arc/hsdk/hsdk_defconfig b/boards/synopsys/hsdk/hsdk_defconfig similarity index 87% rename from boards/arc/hsdk/hsdk_defconfig rename to boards/synopsys/hsdk/hsdk_defconfig index 1e6b459fc37..0d17f50041b 100644 --- a/boards/arc/hsdk/hsdk_defconfig +++ b/boards/synopsys/hsdk/hsdk_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ARC_HSDK=y -CONFIG_BOARD_HSDK=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n CONFIG_BUILD_NO_GAP_FILL=y diff --git a/boards/arc/hsdk/platform.c b/boards/synopsys/hsdk/platform.c similarity index 100% rename from boards/arc/hsdk/platform.c rename to boards/synopsys/hsdk/platform.c diff --git a/boards/arc/hsdk/support/openocd-2-cores.cfg b/boards/synopsys/hsdk/support/openocd-2-cores.cfg similarity index 100% rename from boards/arc/hsdk/support/openocd-2-cores.cfg rename to boards/synopsys/hsdk/support/openocd-2-cores.cfg diff --git a/boards/arc/hsdk/support/openocd.cfg b/boards/synopsys/hsdk/support/openocd.cfg similarity index 100% rename from boards/arc/hsdk/support/openocd.cfg rename to boards/synopsys/hsdk/support/openocd.cfg diff --git a/boards/arc/hsdk4xd/CMakeLists.txt b/boards/synopsys/hsdk4xd/CMakeLists.txt similarity index 100% rename from boards/arc/hsdk4xd/CMakeLists.txt rename to boards/synopsys/hsdk4xd/CMakeLists.txt diff --git a/boards/synopsys/hsdk4xd/Kconfig.hsdk4xd b/boards/synopsys/hsdk4xd/Kconfig.hsdk4xd new file mode 100644 index 00000000000..23c57baf0e9 --- /dev/null +++ b/boards/synopsys/hsdk4xd/Kconfig.hsdk4xd @@ -0,0 +1,12 @@ +# DesignWare ARC HSDK4XD Development Kit board configuration + +# Copyright (c) 2023 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HSDK4XD + select SOC_ARC_HSDK4XD + help + The ARC HS4x/4xD Development Kit is a ready-to-use software development + platform for the ARC HS4x/4xD family of processor IP. It includes + a multicore ARC HS4x/HS4xD-based chip and integrates a wide range + of interfaces. diff --git a/boards/synopsys/hsdk4xd/board.cmake b/boards/synopsys/hsdk4xd/board.cmake new file mode 100644 index 00000000000..dd49a483a39 --- /dev/null +++ b/boards/synopsys/hsdk4xd/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd "--use-elf") +board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/synopsys/hsdk4xd/board.yml b/boards/synopsys/hsdk4xd/board.yml new file mode 100644 index 00000000000..70e04fa7e80 --- /dev/null +++ b/boards/synopsys/hsdk4xd/board.yml @@ -0,0 +1,5 @@ +board: + name: hsdk4xd + vendor: snps + socs: + - name: arc_hsdk4xd diff --git a/boards/arc/hsdk4xd/doc/arduino_shield_interface.jpg b/boards/synopsys/hsdk4xd/doc/arduino_shield_interface.jpg similarity index 100% rename from boards/arc/hsdk4xd/doc/arduino_shield_interface.jpg rename to boards/synopsys/hsdk4xd/doc/arduino_shield_interface.jpg diff --git a/boards/arc/hsdk4xd/doc/hsdk4xd.jpg b/boards/synopsys/hsdk4xd/doc/hsdk4xd.jpg similarity index 100% rename from boards/arc/hsdk4xd/doc/hsdk4xd.jpg rename to boards/synopsys/hsdk4xd/doc/hsdk4xd.jpg diff --git a/boards/synopsys/hsdk4xd/doc/index.rst b/boards/synopsys/hsdk4xd/doc/index.rst new file mode 100644 index 00000000000..b373f22cee3 --- /dev/null +++ b/boards/synopsys/hsdk4xd/doc/index.rst @@ -0,0 +1,557 @@ +.. _hsdk4xd: + +DesignWare(R) ARC(R) HS4x/HS4xD Development Kit +############################################### + +Overview +******** + +The ARC HS4x/HS4xD Development Kit is the next revision of :ref:`Synopsys HSDK board `. +It includes a multicore ARC HS4xD-based chip that integrates a wide range of interfaces +including Ethernet, HDMI, WiFi, Bluetooth, USB, SDIO, I2C, SPI, UART, I2S, ADC, PWM and GPIO, +as well as a Think Silicon GPU. + +.. image:: hsdk4xd.jpg + :align: center + :alt: DesignWare(R) ARC(R) HS4x/HS4xD Development Kit (synopsys.com) + +For details about the board, see: `ARC HS4x/HS4xD Development Kit +(HSDK4xD) `__ + +Hardware +******** + +The ARC HSDK4xD has 24 general GPIOs, which divided into 8 groups named from ``GPIO_SEL_0`` to ``GPIO_SEL_7``. +Each sel can configured for different functions, such as: GPIO, UART, SPI, I2C and PWM. We can program +``CREG_GPIO_MUX`` register to do configuration for each sel. Tables below show the bit definition for +``CREG_GPIO_MUX`` register and the details configuration for each pin. + ++--------+-------------+---------+--------------+---------------------------------+ +| Bit | Name | Access | Reset value | Description | ++--------+-------------+---------+--------------+---------------------------------+ +| 2:0 | GPIO_SEL_0 | RW | 0x0 | GPIO mux select for gpio[3:0] | ++--------+-------------+---------+--------------+---------------------------------+ +| 5:3 | GPIO_SEL_1 | RW | 0x0 | GPIO mux select for gpio[7:4] | ++--------+-------------+---------+--------------+---------------------------------+ +| 8:6 | GPIO_SEL_2 | RW | 0x0 | GPIO mux select for gpio[11:8] | ++--------+-------------+---------+--------------+---------------------------------+ +| 11:9 | GPIO_SEL_3 | RW | 0x0 | GPIO mux select for gpio[15:12] | ++--------+-------------+---------+--------------+---------------------------------+ +| 14:12 | GPIO_SEL_4 | RW | 0x0 | GPIO mux select for gpio[17:16] | ++--------+-------------+---------+--------------+---------------------------------+ +| 17:15 | GPIO_SEL_5 | RW | 0x0 | GPIO mux select for gpio[19:18] | ++--------+-------------+---------+--------------+---------------------------------+ +| 20:18 | GPIO_SEL_6 | RW | 0x0 | GPIO mux select for gpio[21:20] | ++--------+-------------+---------+--------------+---------------------------------+ +| 23:21 | GPIO_SEL_7 | RW | 0x0 | GPIO mux select for gpio[23:22] | ++--------+-------------+---------+--------------+---------------------------------+ + ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SELS | GPIO PINS | FUN0 | FUN1 | FUN2 | FUN3 | FUN4 | FUN5 | FUN6 | FUN7 | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL0 | 0 | gpio[0] | uart0_cts | spi1_cs[0] | gpio[0] | gpio[0] | pwm_ch[6] | pwm_ch[6] | pwm_ch[1] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 1 | gpio[1] | uart0_txd | spi1_mosi | gpio[1] | pwm_ch[0] | gpio[1] | pwm_ch[0] | pwm_ch[0] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 2 | gpio[2] | uart0_rxd | spi1 _miso | i2c1_scl | gpio[2] | gpio[2] | gpio[2] | gpio[2] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 3 | gpio[3] | uart0_rts | spi1_clk | i2c1_sda | gpio[3] | gpio[3] | gpio[3] | gpio[3] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL1 | 4 | gpio[4] | uart1_cts | spi2_cs[0] | gpio[4] | gpio[4] | pwm_ch[4] | pwm_ch[4] | pwm_ch[3] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 5 | gpio[5] | uart1_txd | spi2_mosi | gpio[5] | pwm_ch[2] | gpio[5] | pwm_ch[2] | pwm_ch[2] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 6 | gpio[6] | uart1_rxd | spi2_miso | i2c2_scl | gpio[6] | gpio[6] | gpio[6] | gpio[6] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 7 | gpio[7] | uart1_rts | spi2_clk | i2c2_sda | gpio[7] | gpio[7] | gpio[7] | gpio[7] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL2 | 8 | gpio[8] | uart2_cts | spi1_cs[1] | gpio[8] | gpio[8] | pwm_ch[2] | pwm_ch[2] | pwm_ch[5] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 9 | gpio[9] | uart2_txd | spi1_mosi | gpio[9] | pwm_ch[4] | gpio[9] | pwm_ch[4] | pwm_ch[4] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 10 | gpio[10] | uart2_rxd | spi1_miso | i2c1_scl | gpio[10] | gpio[10] | gpio[10] | gpio[10] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 11 | gpio[11] | uart2_rts | spi1_clk | i2c1_sda | gpio[11] | gpio[11] | gpio[11] | gpio[11] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL3 | 12 | gpio[12] | uart0_cts | spi2_cs[1] | gpio[12] | gpio[12] | pwm_ch[0] | pwm_ch[0] | pwm_ch[7] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 13 | gpio[13] | uart0_txd | spi2_mosi | gpio[13] | pwm_ch[6] | gpio[13] | pwm_ch[6] | pwm_ch[6] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 14 | gpio[14] | uart0_rxd | spi2_miso | i2c2_scl | gpio[14] | gpio[14] | gpio[14] | gpio[14] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 15 | gpio[15] | uart0_rts | spi2_clk | i2c2_sda | gpio[15] | gpio[15] | gpio[15] | gpio[15] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL4 | 16 | gpio[16] | uart1_txd | spi1_cs[2] | i2c1_scl | gpio[16] | pwm_fault_0 | gpio[16] | pwm_fault_0 | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 17 | gpio[17] | uart1_rxd | spi1_mosi | i2c1_sda | pwm_ch[0] | pwm_ch[0] | pwm_ch[5] | pwm_ch[5] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL5 | 18 | gpio[18] | uart2_txd | spi1_miso | i2c2_scl | gpio[18] | gpio[18] | gpio[18] | gpio[18] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 19 | gpio[19] | uart2_rxd | spi1_clk | i2c2_sda | gpio[19] | gpio[19] | gpio[19] | gpio[19] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL6 | 20 | gpio[20] | uart0_txd | spi2_cs[2] | i2c1_scl | gpio[20] | pwm_fault_1 | gpio[20] | pwm_fault_1 | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 21 | gpio[21] | uart0_rxd | spi2_mosi | i2c1_sda | pwm_ch[6] | pwm_ch[6] | pwm_ch[3] | pwm_ch[3] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL7 | 22 | gpio[22] | uart2_txd | spi2_miso | i2c2_scl | gpio[22] | gpio[22] | gpio[22] | gpio[22] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 23 | gpio[23] | uart2_rxd | spi2_clk | i2c2_sda | gpio[23] | gpio[23] | gpio[23] | gpio[23] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ + +Digilent Pmod +============= + +The ARC HSDK4xD features two 12-pin Pmod connectors ``Pmod_A`` and ``Pmod_B`` and one 6-pin Pmod connector ``Pmod_C``. +The functionality of the Pmod connectors is programmable and includes GPIO, UART, SPI, I2C and PWM. +The location of the pins on the Pmod connectors is shown in Figure below. Detailed pin descriptions +depending on the pin multiplexer settings are provided in the subsequent sections. + +.. image:: pinout_diagram_of_the_pmod.jpg + :align: center + :alt: Pinout Diagram of the Pmod + +Pmod_A Connector +---------------- + +Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_A`` +connector. The GPIO column is the default assignment after Reset. + ++------+-----------+------------+-------------+-----------+------------+-----------+ +| Pin | GPIO | UART | SPI | I2C | PWM_1 | PWM_2 | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A1 | gpio[8] | uart2_cts | spi1_cs[1] | gpio[8] | gpio[8] | pwm_ch[2] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A2 | gpio[9] | uart2_txd | spi1_mosi | gpio[9] | pwm_ch[4] | gpio[9] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A3 | gpio[10] | uart2_rxd | spi1_miso | i2c1_scl | gpio[10] | gpio[10] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A4 | gpio[11] | uart2_rts | spi1_clk | i2c1_sda | gpio[11] | gpio[11] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A5 | GND | GND | GND | GND | GND | GND | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A7 | gpio[20] | gpio[20] | gpio[20] | gpio[20] | gpio[20] | gpio[20] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A8 | gpio[21] | gpio[21] | gpio[21] | gpio[21] | gpio[21] | gpio[21] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A9 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A10 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A11 | GND | GND | GND | GND | GND | GND | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A12 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | ++------+-----------+------------+-------------+-----------+------------+-----------+ + +Pmod_B Connector +---------------- + +Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_B`` +connector. The GPIO column is the default assignment after Reset. + ++------+-----------+------------+-------------+-----------+------------+-----------+ +| Pin | GPIO | UART | SPI | I2C | PWM_1 | PWM_2 | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B1 | gpio[12] | uart0_cts | spi2_cs[1] | gpio[12] | gpio[12] | pwm_ch[0] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B2 | gpio[13] | uart0_txd | spi2_mosi | gpio[13] | pwm_ch[6] | gpio[13] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B3 | gpio[14] | uart0_rxd | spi2_miso | i2c2_scl | gpio[14] | gpio[14] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B4 | gpio[15] | uart0_rts | spi2_clk | i2c2_sda | gpio[15] | gpio[15] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B5 | GND | GND | GND | GND | GND | GND | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B7 | gpio[22] | gpio[22] | gpio[22] | gpio[22] | gpio[22] | gpio[22] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B8 | gpio[23] | gpio[23] | gpio[23] | gpio[23] | gpio[23] | gpio[23] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B9 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B10 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B11 | GND | GND | GND | GND | GND | GND | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B12 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | ++------+-----------+------------+-------------+-----------+------------+-----------+ + +Pmod_C Connector +---------------- + +Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_C`` +connector. The GPIO column is the default assignment after Reset. + ++------+-----------+------------+-------------+-----------+-----------+ +| Pin | GPIO | UART | SPI | I2C | PWM | ++------+-----------+------------+-------------+-----------+-----------+ +| C1 | gpio[16] | uart1_txd | spi1_cs[2] | i2c1_scl | gpio[16] | ++------+-----------+------------+-------------+-----------+-----------+ +| C2 | gpio[17] | uart1_rxd | spi1_mosi | i2c1_sda | pwm_ch[0] | ++------+-----------+------------+-------------+-----------+-----------+ +| C3 | gpio[18] | uart2_txd | spi1_miso | i2c2_scl | gpio[18] | ++------+-----------+------------+-------------+-----------+-----------+ +| C4 | gpio[19] | uart2_rxd | spi1_clk | i2c2_sda | gpio[19] | ++------+-----------+------------+-------------+-----------+-----------+ +| C5 | GND | GND | GND | GND | GND | ++------+-----------+------------+-------------+-----------+-----------+ +| C6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | ++------+-----------+------------+-------------+-----------+-----------+ + +Mikrobus +======== + +The ARC HSDK4xD features a set of MikroBUS headers. Figure below shows the relevant function assignments, +fully compatible with the MikroBUS standard. Table below shows the pin assignment on the I/O Multiplexer. + +.. image:: mikrobus_header.jpg + :align: center + :alt: mikrobus header + ++-------+-----------------+------+-----------+ +| Pin | I/O | Pin | I/O | ++-------+-----------------+------+-----------+ +| AN | ADC VIN6* | PWM | pwm_ch[0] | ++-------+-----------------+------+-----------+ +| RST | GPX_Port0_bit1 | INT | gpio[16] | ++-------+-----------------+------+-----------+ +| CS | spi2_cs[1] | RX | uart2_rxd | ++-------+-----------------+------+-----------+ +| SCK | spi2_clk | TX | uart2_txd | ++-------+-----------------+------+-----------+ +| MISO | spi2_miso | SCL | i2c2_scl | ++-------+-----------------+------+-----------+ +| MOSI | spi2_mosi | SDA | i2c2_sda | ++-------+-----------------+------+-----------+ + +.. note:: + ADC VIN6 is available through the on-board ADC and is + read though SPI0 using SPI chip select 1. + +Arduino +======= + +The ARC HSDK4xD provides an Arduino shield interface. Figure below shows the relevant +function assignments. The Arduino shield interface is compatible with the Arduino UNO +R3 with the following exceptions: 5 Volt shields are not supported, the IOREF voltage on +the ARC HSDK4xD board is fixed to 3V3. Note that the ICSP header is also not available. Most +shields do not require this ICSP header as the SPI master interface on this ICSP header +is also available on the ``IO10`` to ``IO13`` pins. + +.. image:: arduino_shield_interface.jpg + :align: center + :alt: arduino shield interface + +Table below shows the pin assignment on the I/O Multiplexer. Multiplexing is controlled by software +using the ``CREG_GPIO_MUX`` register (see Pinmux ). After a reset, all ports are configured as GPIO inputs. + ++-------+------------+-----------------+------------+ +| Pin | I/O-1 | I/O-2 | I/O-3 | ++-------+------------+-----------------+------------+ +| AD0 | ADC VIN0* | GPX_port0_bit2 | - | ++-------+------------+-----------------+------------+ +| AD1 | ADC VIN1* | GPX_port0_bit3 | - | ++-------+------------+-----------------+------------+ +| AD2 | ADC VIN2* | GPX_port0_bit4 | - | ++-------+------------+-----------------+------------+ +| AD3 | ADC VIN3* | GPX_port0_bit5 | - | ++-------+------------+-----------------+------------+ +| AD4 | ADC VIN4* | gpio[18] | i2c2_sda | ++-------+------------+-----------------+------------+ +| AD5 | ADC VIN5* | gpio[19] | i2c2_scl | ++-------+------------+-----------------+------------+ +| IO0 | gpio[23] | uart2_rxd | - | ++-------+------------+-----------------+------------+ +| IO1 | gpio[22] | uart2_txd | - | ++-------+------------+-----------------+------------+ +| IO2 | gpio[16] | - | - | ++-------+------------+-----------------+------------+ +| IO3 | gpio[17] | pwm_ch[5] | - | ++-------+------------+-----------------+------------+ +| IO4 | gpio[11] | - | | ++-------+------------+-----------------+------------+ +| IO5 | gpio[9] | pwm_ch[4] | - | ++-------+------------+-----------------+------------+ +| IO6 | gpio[21] | pwm_ch[3] | - | ++-------+------------+-----------------+------------+ +| IO7 | gpio[20] | - | - | ++-------+------------+-----------------+------------+ +| IO8 | gpio[10] | - | - | ++-------+------------+-----------------+------------+ +| IO9 | gpio[8] | pwm_ch[2] | - | ++-------+------------+-----------------+------------+ +| IO10 | gpio[12] | pwm_ch[0] | spi2_cs[1] | ++-------+------------+-----------------+------------+ +| IO11 | gpio[13] | pwm_ch[6] | spi2_mosi | ++-------+------------+-----------------+------------+ +| IO12 | gpio[14] | - | spi2_miso | ++-------+------------+-----------------+------------+ +| IO13 | gpio[15] | - | spi2_clk | ++-------+------------+-----------------+------------+ + +I/O expander +============ + +The ARC HSDK4xD board includes a CY8C9520A I/O expander from `Cypress CY8C9520A +`__. The I/O +expander offers additional GPIO signals and board control signals and can be accessed +through the on-board I2C bus, we have implemented a basic driver for it. +Tables below shows an overview of relevant I/O signals. + ++------------+---------------------------------------------+ +| Pins | Usage | ++------------+---------------------------------------------+ +| port0_bit0 | RS9113 Bluetooth I2S RX enable (active low) | ++------------+---------------------------------------------+ +| port0_bit1 | mikroBUS Reset (active low) | ++------------+---------------------------------------------+ +| port0_bit2 | GPIO for Arduino AD0 | ++------------+---------------------------------------------+ +| port0_bit3 | GPIO for Arduino AD1 | ++------------+---------------------------------------------+ +| port0_bit4 | GPIO for Arduino AD2 | ++------------+---------------------------------------------+ +| port0_bit5 | GPIO for Arduino AD3 | ++------------+---------------------------------------------+ +| port1_bit4 | On-board user LED0 | ++------------+---------------------------------------------+ +| port1_bit5 | On-board user LED1 | ++------------+---------------------------------------------+ +| port1_bit6 | On-board user LED2 | ++------------+---------------------------------------------+ +| port1_bit7 | On-board user LED3 | ++------------+---------------------------------------------+ + +On-board user LEDS +================== + +The ARC HSDK4xD includes 4 user LEDs(active high), which can be controlled through the I/O expander pins. + ++-------+-----------------+ +| LEDs | PINs | ++-------+-----------------+ +| LED0 | GPX_port1_bit4 | ++-------+-----------------+ +| LED1 | GPX_port1_bit5 | ++-------+-----------------+ +| LED2 | GPX_port1_bit6 | ++-------+-----------------+ +| LED3 | GPX_port1_bit7 | ++-------+-----------------+ + +For hardware feature details, refer to : `Designware HS4x/HS4xD Development Kit website +`__. + +Programming and Debugging +************************* + +Required Hardware and Software +============================== + +To use Zephyr RTOS applications on the HS4x/HS4xD Development Kit board, a few +additional pieces of hardware are required. + +* A micro USB cable provides USB-JTAG debug and USB-UART communication + to the board + +* A universal switching power adaptor (110-240V + AC to 12V DC), provided in the package, provides power to the board. + +* :ref:`The Zephyr SDK ` + +* Terminal emulator software for use with the USB-UART. Suggestion: + `Putty Website`_. + +* (optional) A collection of Pmods, Arduino modules, or Mikro modules. + See `Digilent Pmod Modules`_ or develop your custom interfaces to attach + to the Pmod connector. + +Set up the ARC HS4x/HS4xD Development Kit +========================================= + +To run Zephyr application on ARC HS4x/HS4xD Development Kit, you need to +set up the board correctly. + +* Connect the digilent USB cable from your host to the board. + +* Connect the 12V DC power supply to your board + +Set up Zephyr Software +====================== + +Building Sample Applications +============================== + +You can try many of the :ref:`sample applications and demos +`. We'll use :ref:`hello_world`, found in +:zephyr_file:`samples/hello_world` as an example. + +Configuring +----------- + +You may need to write a ``prj.conf`` file if the sample doesn't have one. +Next, you can use the menuconfig rule to configure the target. By specifying +``hsdk4xd`` as the board configuration, you can select the ARC HS4x/HS4xD Development +Kit board support for Zephyr. + +.. zephyr-app-commands:: + :board: hsdk4xd + :zephyr-app: samples/hello_world + :goals: menuconfig + + +Building +-------- + +You can build an application in the usual way. Refer to +:ref:`build_an_application` for more details. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :board: hsdk4xd + :zephyr-app: samples/hello_world + :maybe-skip-config: + :goals: build + + +Connecting Serial Output +========================= + +In the default configuration, Zephyr's HS4x/HS4xD Development Kit images support +serial output via the USB-UART on the board. To enable serial output: + +* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) + +* Specify the tty driver name, for example, on Linux this may be + :file:`/dev/ttyUSB0` + +* Set the communication settings to: + + +========= ===== +Parameter Value +========= ===== +Baud: 115200 +Data: 8 bits +Parity: None +Stopbits: 1 +========= ===== + +Debugging +========== + +Using the latest version of Zephyr SDK(>=0.15.2), you can debug and +flash (run) HS4x/HS4xD Development Kit directly. + +One option is to build and debug the application using the usual +Zephyr build system commands. + +.. zephyr-app-commands:: + :board: hsdk4xd + :app: + :goals: debug + +At this point you can do your normal debug session. Set breakpoints and then +:kbd:`c` to continue into the program. + +The other option is to launch a debug server, as follows. + +.. zephyr-app-commands:: + :board: hsdk4xd + :app: + :goals: debugserver + +Then connect to the debug server at the HS4x/HS4xD Development Kit from a second +console, from the build directory containing the output :file:`zephyr.elf`. + +.. code-block:: console + + $ cd + $ $ZEPHYR_SDK_INSTALL_DIR/arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf + (gdb) target remote localhost:3333 + (gdb) load + (gdb) b main + (gdb) c + +Flashing +======== + +If you just want to download the application to the HS4x/HS4xD Development Kit's DDR +and run, you can do so in the usual way. + +.. zephyr-app-commands:: + :board: hsdk4xd + :app: + :goals: flash + +This command still uses openocd and gdb to load the application elf file to +HS4x/HS4xD Development Kit, but it will load the application and immediately run. If +power is removed, the application will be lost since it wasn't written to flash. + +Most of the time you will not be flashing your program but will instead debug +it using openocd and gdb. The program can be download via the USB cable into +the code and data memories. + +The HS4x/HS4xD Development Kit also supports flashing the Zephyr application +with the U-Boot bootloader, a powerful and flexible tool for loading +an executable from different sources and running it on the target platform. + +The U-Boot implementation for the HS4x/HS4xD Development Kit was further extended with +additional functionality that allows users to better manage the broad +configurability of the HS4x/HS4xD Development Kit + +When you are ready to deploy the program so that it boots up automatically on +reset or power-up, you can follow the steps to place the program on SD card. + +For details, see: `Uboot-HS4x/HS4xD-Command-Reference +`__ + +Supported peripheral +==================== + +The following list indicates the state of HS4x/HS4xD Development Kit peripherals’ support + ++------------+---------+ +| Peripheral | Support | ++------------+---------+ +| ADC | No | ++------------+---------+ +| Bluetooth | No | ++------------+---------+ +| Ethernet | No | ++------------+---------+ +| GPIO | No | ++------------+---------+ +| GPU | No | ++------------+---------+ +| HDMI | No | ++------------+---------+ +| I2C | No | ++------------+---------+ +| I2S | No | ++------------+---------+ +| PWM | No | ++------------+---------+ +| SDIO | No | ++------------+---------+ +| SPI | No | ++------------+---------+ +| UART | Yes | ++------------+---------+ +| USB | No | ++------------+---------+ +| WiFi | No | ++------------+---------+ + +References +********** + +.. _embARC website: https://www.embarc.org + +.. _Designware HS Development Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit + +.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules + +.. _Putty website: http://www.putty.org diff --git a/boards/arc/hsdk4xd/doc/mikrobus_header.jpg b/boards/synopsys/hsdk4xd/doc/mikrobus_header.jpg similarity index 100% rename from boards/arc/hsdk4xd/doc/mikrobus_header.jpg rename to boards/synopsys/hsdk4xd/doc/mikrobus_header.jpg diff --git a/boards/arc/hsdk4xd/doc/pinout_diagram_of_the_pmod.jpg b/boards/synopsys/hsdk4xd/doc/pinout_diagram_of_the_pmod.jpg similarity index 100% rename from boards/arc/hsdk4xd/doc/pinout_diagram_of_the_pmod.jpg rename to boards/synopsys/hsdk4xd/doc/pinout_diagram_of_the_pmod.jpg diff --git a/boards/synopsys/hsdk4xd/hsdk4xd.dts b/boards/synopsys/hsdk4xd/hsdk4xd.dts new file mode 100644 index 00000000000..59792f4d487 --- /dev/null +++ b/boards/synopsys/hsdk4xd/hsdk4xd.dts @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2023, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "hsdk4xd"; + compatible = "snps,hsdk4xd"; + + aliases { + uart-dbg = &uart_dbg; + }; + + chosen { + zephyr,sram = &ddr0; + zephyr,console = &uart_dbg; + zephyr,shell-uart = &uart_dbg; + }; + +}; + +arduino_spi: &spi2 {}; + +&uart_dbg { + status = "okay"; + current-speed = <115200>; +}; + +&creg_gpio { + status = "okay"; +}; diff --git a/boards/arc/hsdk4xd/hsdk4xd.yaml b/boards/synopsys/hsdk4xd/hsdk4xd.yaml similarity index 100% rename from boards/arc/hsdk4xd/hsdk4xd.yaml rename to boards/synopsys/hsdk4xd/hsdk4xd.yaml diff --git a/boards/arc/hsdk4xd/hsdk4xd_defconfig b/boards/synopsys/hsdk4xd/hsdk4xd_defconfig similarity index 86% rename from boards/arc/hsdk4xd/hsdk4xd_defconfig rename to boards/synopsys/hsdk4xd/hsdk4xd_defconfig index 24f79598815..00d8ba6ff0d 100644 --- a/boards/arc/hsdk4xd/hsdk4xd_defconfig +++ b/boards/synopsys/hsdk4xd/hsdk4xd_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ARC_HSDK4XD=y -CONFIG_BOARD_HSDK4XD=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n diff --git a/boards/arc/hsdk4xd/support/openocd.cfg b/boards/synopsys/hsdk4xd/support/openocd.cfg similarity index 100% rename from boards/arc/hsdk4xd/support/openocd.cfg rename to boards/synopsys/hsdk4xd/support/openocd.cfg diff --git a/boards/synopsys/index.rst b/boards/synopsys/index.rst new file mode 100644 index 00000000000..00ef0d70564 --- /dev/null +++ b/boards/synopsys/index.rst @@ -0,0 +1,10 @@ +.. _boards-synopsys: + +Synopsys +######## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arc/qemu_arc/CMakeLists.txt b/boards/synopsys/iotdk/CMakeLists.txt similarity index 100% rename from boards/arc/qemu_arc/CMakeLists.txt rename to boards/synopsys/iotdk/CMakeLists.txt diff --git a/boards/synopsys/iotdk/Kconfig.iotdk b/boards/synopsys/iotdk/Kconfig.iotdk new file mode 100644 index 00000000000..192759678b7 --- /dev/null +++ b/boards/synopsys/iotdk/Kconfig.iotdk @@ -0,0 +1,14 @@ +# DesignWare ARC IoT Development Kit board configuration + +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IOTDK + select SOC_ARC_IOT + help + The DesignWare ARC IoT Development Kit board is a versatile platform that includes the + necessary hardware and software to accelerate software development and debugging of + sensor fusion, voice recognition and face detection designs. It includes a silicon + implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on SMIC's 55-nm + ultra-low power process, and a rich set of peripherals commonly used in IoT designs + such as USB, UART, SPI, I2C, PWM, SDIO and ADCs. diff --git a/boards/arc/iotdk/arc_mpu_regions.c b/boards/synopsys/iotdk/arc_mpu_regions.c similarity index 100% rename from boards/arc/iotdk/arc_mpu_regions.c rename to boards/synopsys/iotdk/arc_mpu_regions.c diff --git a/boards/arc/emsdp/board.cmake b/boards/synopsys/iotdk/board.cmake similarity index 100% rename from boards/arc/emsdp/board.cmake rename to boards/synopsys/iotdk/board.cmake diff --git a/boards/synopsys/iotdk/board.yml b/boards/synopsys/iotdk/board.yml new file mode 100644 index 00000000000..5222ad815cf --- /dev/null +++ b/boards/synopsys/iotdk/board.yml @@ -0,0 +1,5 @@ +board: + name: iotdk + vendor: snps + socs: + - name: arc_iot diff --git a/boards/arc/iotdk/doc/index.rst b/boards/synopsys/iotdk/doc/index.rst similarity index 100% rename from boards/arc/iotdk/doc/index.rst rename to boards/synopsys/iotdk/doc/index.rst diff --git a/boards/arc/iotdk/doc/iotdk.jpg b/boards/synopsys/iotdk/doc/iotdk.jpg similarity index 100% rename from boards/arc/iotdk/doc/iotdk.jpg rename to boards/synopsys/iotdk/doc/iotdk.jpg diff --git a/boards/arc/iotdk/iotdk.dts b/boards/synopsys/iotdk/iotdk.dts similarity index 96% rename from boards/arc/iotdk/iotdk.dts rename to boards/synopsys/iotdk/iotdk.dts index e1bd41db5b6..8a9837d1b2a 100644 --- a/boards/arc/iotdk/iotdk.dts +++ b/boards/synopsys/iotdk/iotdk.dts @@ -8,7 +8,6 @@ #include #include -#include "board.dtsi" / { model = "iotdk"; diff --git a/boards/arc/iotdk/iotdk.yaml b/boards/synopsys/iotdk/iotdk.yaml similarity index 100% rename from boards/arc/iotdk/iotdk.yaml rename to boards/synopsys/iotdk/iotdk.yaml diff --git a/boards/arc/iotdk/iotdk_defconfig b/boards/synopsys/iotdk/iotdk_defconfig similarity index 86% rename from boards/arc/iotdk/iotdk_defconfig rename to boards/synopsys/iotdk/iotdk_defconfig index afb2569dadd..d95ae777729 100644 --- a/boards/arc/iotdk/iotdk_defconfig +++ b/boards/synopsys/iotdk/iotdk_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ARC_IOT=y -CONFIG_BOARD_IOTDK=y CONFIG_XIP=n CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n diff --git a/boards/arc/iotdk/support/openocd.cfg b/boards/synopsys/iotdk/support/openocd.cfg similarity index 100% rename from boards/arc/iotdk/support/openocd.cfg rename to boards/synopsys/iotdk/support/openocd.cfg diff --git a/boards/arc/nsim/CMakeLists.txt b/boards/synopsys/nsim/CMakeLists.txt similarity index 100% rename from boards/arc/nsim/CMakeLists.txt rename to boards/synopsys/nsim/CMakeLists.txt diff --git a/boards/synopsys/nsim/Kconfig b/boards/synopsys/nsim/Kconfig new file mode 100644 index 00000000000..5fefd2b3877 --- /dev/null +++ b/boards/synopsys/nsim/Kconfig @@ -0,0 +1,7 @@ +# DesignWare ARC nSIM simulated platform configuration + +# Copyright (c) 2016, 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NSIM + select HAS_COVERAGE_SUPPORT diff --git a/boards/synopsys/nsim/Kconfig.nsim b/boards/synopsys/nsim/Kconfig.nsim new file mode 100644 index 00000000000..88601b8e48a --- /dev/null +++ b/boards/synopsys/nsim/Kconfig.nsim @@ -0,0 +1,28 @@ +# DesignWare ARC nSIM simulated platform configuration + +# Copyright (c) 2016, 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NSIM + select SOC_NSIM_EM if BOARD_NSIM_NSIM_EM + select SOC_NSIM_EM7D_V22 if BOARD_NSIM_NSIM_EM7D_V22 + select SOC_NSIM_EM11D if BOARD_NSIM_NSIM_EM11D + select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS + select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS_SRAM + select SOC_NSIM_HS_SMP if BOARD_NSIM_NSIM_HS_SMP + select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS_FLASH_XIP + select SOC_NSIM_HS_MPUV6 if BOARD_NSIM_NSIM_HS_MPUV6 + select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS_HOSTLINK + select SOC_NSIM_HS5X if BOARD_NSIM_NSIM_HS5X + select SOC_NSIM_HS5X_SMP if BOARD_NSIM_NSIM_HS5X_SMP + select SOC_NSIM_HS5X_SMP if BOARD_NSIM_NSIM_HS5X_SMP_12CORES + select SOC_NSIM_HS6X if BOARD_NSIM_NSIM_HS6X + select SOC_NSIM_HS6X_SMP if BOARD_NSIM_NSIM_HS6X_SMP + select SOC_NSIM_HS6X_SMP if BOARD_NSIM_NSIM_HS6X_SMP_12CORES + select SOC_NSIM_SEM if BOARD_NSIM_NSIM_SEM + select SOC_NSIM_SEM if BOARD_NSIM_NSIM_SEM_MPU_STACK_GUARD + select SOC_NSIM_VPX5 if BOARD_NSIM_NSIM_VPX5 + help + The DesignWare ARC nSIM board is a virtual board based on + the ARC nSIM simulator. It demonstrates the ARC core features + and a console based on the ns16550 UART model. diff --git a/boards/arc/nsim/arc_mpu_regions.c b/boards/synopsys/nsim/arc_mpu_regions.c similarity index 100% rename from boards/arc/nsim/arc_mpu_regions.c rename to boards/synopsys/nsim/arc_mpu_regions.c diff --git a/boards/arc/nsim/board.cmake b/boards/synopsys/nsim/board.cmake similarity index 100% rename from boards/arc/nsim/board.cmake rename to boards/synopsys/nsim/board.cmake diff --git a/boards/synopsys/nsim/board.yml b/boards/synopsys/nsim/board.yml new file mode 100644 index 00000000000..a5089774c47 --- /dev/null +++ b/boards/synopsys/nsim/board.yml @@ -0,0 +1,28 @@ +board: + name: nsim + vendor: snps + socs: + - name: nsim_em + - name: nsim_em7d_v22 + - name: nsim_em11d + - name: nsim_hs + variants: + - name: sram + - name: smp + - name: flash_xip + - name: mpuv6 + - name: hostlink + - name: nsim_hs5x + variants: + - name: smp + variants: + - name: 12cores + - name: nsim_hs6x + variants: + - name: smp + variants: + - name: 12cores + - name: nsim_sem + variants: + - name: mpu_stack_guard + - name: nsim_vpx5 diff --git a/boards/synopsys/nsim/doc/index.rst b/boards/synopsys/nsim/doc/index.rst new file mode 100644 index 00000000000..3f4a250993a --- /dev/null +++ b/boards/synopsys/nsim/doc/index.rst @@ -0,0 +1,339 @@ +.. _nsim: + +DesignWare ARC nSIM and HAPS FPGA boards +######################################## + +Overview +******** + +This platform can be used to run Zephyr RTOS on the widest possible range of ARC processors in +simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The +platform includes the following features: + +* ARC processor core, which implements ARCv2 or ARCv3 ISA, please refer to + :ref:`here ` for a complete list of ARC processor families which + currently supported +* Virtual serial console (a standard ``ns16550`` UART model) + +ARC processors are known for being highly customizable and some but not all of the configurations +are currently supported in the Zephyr RTOS for ARC, again please refer to +:ref:`here ` for a complete list of supported features. + +There are multiple supported sub-configurations for that platform. Some but not all of currently +available configurations are listed below: + +* ``nsim/nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and + XY-memory +* ``nsim/nsim_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's +* ``nsim/nsim_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options and + XY-memory +* ``nsim/nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4 +* ``nsim/nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3 +* ``nsim/nsim_hs/smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3 +* ``nsim/nsim_vpx5`` - ARCv2 VPX5 core, close to vpx5_integer_full template +* ``nsim/nsim_hs5x`` - 32-bit ARCv3 HS core with rich set of options +* ``nsim/nsim_hs6x`` - 64-bit ARCv3 HS core with rich set of options +* ``nsim/nsim_hs5x/smp/12cores`` - SMP 12 cores 32-bit ARCv3 HS platform +* ``nsim/nsim_hs6x/smp/12cores`` - SMP 12 cores 64-bit ARCv3 HS platform + +.. _board_arc_nsim_prop_args_files: + +It is recommended to look at precise description of a particular sub-configuration in either +``.props`` or ``.args`` files in :zephyr_file:`boards/synopsys/nsim/support/` directory to understand +which options are configured and so will be used on invocation of the simulator. + +In case of single-core configurations it would be ``.props`` file which contains configuration +for nSIM simulator and ``.args`` file which contains configuration for MetaWare debugger (MDB). +Note that these files contain identical HW configuration and meant to be used with the corresponding +tool: ``.props`` file for nSIM simulator and ``.args`` file for MDB (which internally uses nSIM for +simulation anyway). + +.. hint:: + If different behavior is observed during execution or debugging of a particular application + (especially after creation of a new board or modification of the existing one) make sure features + defined in ``.props`` and ``.args`` are semantically identical (unfortunately options of + nSIM & MDB don't exactly match, so care should be taken). + +I.e. for the single-core ``nsim/nsim_hs5x`` platform there are +:zephyr_file:`boards/synopsys/nsim/support/nsim_hs5x.props` and +:zephyr_file:`boards/synopsys/nsim/support/mdb_hs5x.args`. + +For the multi-core configurations there is only ``.args`` file as the multi-core configuration +can only be instantiated with help of MDB. + +I.e. for the multi-core ``nsim/nsim_hs5x/smp`` platform there is only +:zephyr_file:`boards/synopsys/nsim/support/mdb_hs5x_smp.args`. + +.. warning:: + All nSIM/MDB configurations are used for demo and testing purposes. They are not meant to + represent any real system and so might be renamed, removed or modified at any point. + +Programming and Debugging +************************* + +Required Hardware and Software +============================== + +To run single-core Zephyr RTOS applications in simulation on this board, +either `DesignWare ARC nSIM`_ or `DesignWare ARC Free nSIM`_ is required. + +To run multi-core Zephyr RTOS applications in simulation on this board, +`DesignWare ARC nSIM`_ and MetaWare Debugger from `ARC MWDT`_ are required. + +To run Zephyr RTOS applications on FPGA-based `HAPS`_ platform, +MetaWare Debugger from `ARC MWDT`_ is required as well as the HAPS platform itself. + +Building & Running Sample Applications +====================================== + +Most board sub-configurations support building with both GNU and ARC MWDT toolchains, however +there might be exceptions from that, especially for newly added targets. You can check supported +toolchains for the sub-configurations in the corresponding ``.yaml`` file. + +I.e. for the ``nsim/nsim_hs5x`` board we can check :zephyr_file:`boards/synopsys/nsim/nsim_nsim_hs5x.yaml` + +The supported toolchains are listed in ``toolchain:`` array in ``.yaml`` file, where we can find: + +* **zephyr** - implies ARC GNU toolchain from Zephyr SDK. You can find more information about + Zephyr SDK :ref:`here `. +* **cross-compile** - implies ARC GNU cross toolchain, which is not a part of Zephyr SDK. Note that + some (especially new) sub-configurations may declare ``cross-compile`` toolchain support without + ``zephyr`` toolchain support because corresponding target CPU support hasn't been added to Zephyr + SDK yet. You can find more information about its usage here: :ref:`here `. +* **arcmwdt** - implies proprietary ARC MWDT toolchain. You can find more information about its + usage here: :ref:`here `. + +.. note:: + Note that even if both GNU and MWDT toolchain support is declared for the target some tests or + samples can be only built with either GNU or MWDT toolchain due to some features limited to a + particular toolchain. + +Use this configuration to run basic Zephyr applications and kernel tests in +nSIM, for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: nsim_em + :goals: flash + +This will build an image with the synchronization sample app, boot it using +nSIM, and display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.2.0-3948-gd351a024dc87 *** + thread_a: Hello World from cpu 0 on nsim! + thread_b: Hello World from cpu 0 on nsim! + thread_a: Hello World from cpu 0 on nsim! + thread_b: Hello World from cpu 0 on nsim! + thread_a: Hello World from cpu 0 on nsim! + + +.. note:: + To exit the simulator, use :kbd:`Ctrl+]`, then :kbd:`Ctrl+c` + +.. _board_arc_nsim_verbose_build: + +.. tip:: + You can get more details about the building process by running build in verbose mode. It can be + done by passing ``-v`` flag to the west: ``west -v build -b nsim_hs samples/synchronization`` + +You can run applications built for ``nsim`` board not only on nSIM simulation itself, but also on +FPGA based HW platform `HAPS`_. To run previously built application on HAPS do: + +.. code-block:: console + + west flash --runner mdb-hw + +.. note:: + To run on HAPS, in addition to proper build and flash Zephyr image, you need setup HAPS itself + as well as flash proper built FPGA image (aka .bit-file). This instruction doesn't cover those + steps, so you need to follow HAPS manual. + +Debugging +========= + +.. _board_arc_nsim_debugging_mwdt: + +Debugging with MDB +------------------ + +.. note:: + We strongly recommend to debug with MetaWare debugger (MDB) because it: + + * Supports wider range of ARC hardware features + * Allows to debug both single-core and multi-core ``nsim`` targets. + * Allows to debug on `HAPS`_ platform. + +You can use the following command to start GUI debugging when running application on nSIM simulator +(regardless if single- or multi-core configuration is used): + +.. code-block:: console + + west debug --runner mdb-nsim + +You can use the following command to start GUI debugging when running application on `HAPS`_ +platform: + +.. code-block:: console + + west debug --runner mdb-hw + +.. tip:: + The ``west debug`` (as well as ``west flash``) is just a wrapper script and so it's possible to + extract the exact commands which are called in it by running it in verbose mode. For that you + need to pass ``-v`` flag to the wrapper. For example, if you run the following command: + + .. code-block:: console + + west -v debug --runner mdb-nsim + + it will produce the following output (the ``nsim/nsim_hs5x/smp`` configuration was used for that + example): + + .. code-block:: console + + < *snip* > + -- west debug: using runner mdb-nsim + runners.mdb-nsim: mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf + runners.mdb-nsim: mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf + runners.mdb-nsim: mdb -multifiles=core1,core0 -OKN + + From that output it's possible to extract MDB commands used for setting-up the GUI debugging + session: + + .. code-block:: console + + mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf + mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf + mdb -multifiles=core1,core0 -OKN + + Then it's possible to use them directly or in some machinery if required. + + .. warning:: + It is strongly recommended to not rely on the mdb command line options listed above but + extract it yourself for your configuration. + + .. note:: + In case of execution or debugging with MDB on multi-core configuration on nSIM + simulator without ``west flash`` and ``west debug`` wrappers it's necessary to + set :envvar:`NSIM_MULTICORE` environment variable to ``1``. If you are using ``west flash`` or + ``west debug`` it's done automatically by wrappers. + + Without :envvar:`NSIM_MULTICORE` environment variable set to 1, MDB will simulate 2 separate + ARC cores which don't share any memory regions with each other and so SMP-enabled code won't + work as expected. + +Debugging with GDB +------------------ + +.. note:: + Debugging on nSIM via GDB is only supported on single-core configurations (which use standalone + nSIM). However if it's possible to launch application on multi-core nsim target that means you + can simply :ref:`debug with MDB debugger `. + It's the nSIM with ARC GDB restriction, real HW multi-core ARC targets can be debugged with ARC + GDB. + +.. note:: + Currently debugging with GDB is not supported on `HAPS`_ platform. + +.. note:: + The normal ``west debug`` command won't work for debugging applications using nsim boards + because both the nSIM simulator and the debugger (either GDB or MDB) use the same console for + input / output. + In case of GDB debugger it's possible to use a separate terminal windows for GDB and nSIM to + avoid intermixing their output. For the MDB debugger simply use GUI mode. + +After building your application, open two terminal windows. In terminal one, use nSIM to start a GDB +server and wait for a remote connection with following command: + +.. code-block:: console + + west debugserver --runner arc-nsim + +In terminal two, connect to the GDB server using ARC GDB. You can find it in Zephyr SDK: + +* for the ARCv2 targets you should use :file:`arc-zephyr-elf-gdb` +* for the ARCv3 targets you should use :file:`arc64-zephyr-elf-gdb` + +This command loads the symbol table from the elf binary file, for example the +:file:`build/zephyr/zephyr.elf` file: + +.. code-block:: console + + arc-zephyr-elf-gdb -ex 'target remote localhost:3333' -ex load build/zephyr/zephyr.elf + +Now the debug environment has been set up, and it's possible to debug the application with gdb +commands. + +Modifying the configuration +*************************** + +If modification of existing nsim configuration is required or even there's a need in creation of a +new one it's required to maintain alignment between + +* Zephyr OS configuration +* nSIM & MDB configuration +* GNU & MWDT toolchain compiler options + +.. note:: + The ``.tcf`` configuration files are not supported by Zephyr directly. There are multiple + reasons for that. ``.tcf`` perfectly suits building of bare-metal single-thread application - + in that case all the compiler options from ``.tcf`` are passed to the compiler, so all the HW + features are used by the application and optimal code is being generated. + The situation is completely different when multi-thread feature-rich operation system is + considered. Of course it is still possible to build all the code with all the + options from ``.tcf`` - but that may be far from optimal solution. For example, such approach + require so save & restore full register context for all tasks (and sometimes even for + interrupts). And for DSP-enabled or for FPU-enabled systems that leads to dozens of extra + registers save and restore even if the most of the user and kernel tasks don't actually use + DSP or FPU. Instead we prefer to fine-tune the HW features usage which (with all its pros) + require us to maintain them separately from ``.tcf`` configuration. + + +Zephyr OS configuration +======================= + +Zephyr OS configuration is defined via Kconfig and Device tree. These are non ARC-specific +mechanisms which are described in :ref:`board porting guide `. + +It is advised to look for ``_defconfig``, ``.dts`` and +``.yaml`` as an entry point for board configuration. + +nSIM configuration +================== + +nSIM configuration is defined in :ref:`props and args files `. +Generally they are identical to the values from corresponding ``.tcf`` configuration with few +exceptions: + +* The UART model is added (to both ``.props`` and ``.args`` files). +* Options to fine-tuned MDB behavior are added (to ``.args`` files only) to disable MDB profiling + and fine-tune MDB behavior on multi-core systems. + +GNU & MWDT toolchain compiler options +===================================== + +The hardware-specific compiler options are set in corresponding SoC cmake file. For ``nsim`` board +it is :zephyr_file:`soc/synopsys/nsim/CMakeLists.txt`. + +For the GNU toolchain the basic configuration is set via ``-mcpu`` which is defined in generic code +and based on the selected CPU model via Kconfig. It still can be forcefully set to required value +on SoC level. + +For the MWDT toolchain all hardware-specific compiler options are set directly in SoC +``CMakeLists.txt``. + +.. note:: + The non hardware-specific compiler options like optimizations, library selections, C / C++ + language options are still set in Zephyr generic code. It could be observed by + :ref:`running build in verbose mode `. + +References +********** + +.. _Designware ARC nSIM: https://www.synopsys.com/dw/ipdir.php?ds=sim_nsim +.. _DesignWare ARC Free nSIM: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi +.. _HAPS: https://www.synopsys.com/verification/prototyping/haps.html +.. _ARC MWDT: https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware diff --git a/boards/arc/nsim/haps_arcv3_init.c b/boards/synopsys/nsim/haps_arcv3_init.c similarity index 100% rename from boards/arc/nsim/haps_arcv3_init.c rename to boards/synopsys/nsim/haps_arcv3_init.c diff --git a/boards/arc/nsim/nsim-ccm-mem.dtsi b/boards/synopsys/nsim/nsim-ccm-mem.dtsi similarity index 100% rename from boards/arc/nsim/nsim-ccm-mem.dtsi rename to boards/synopsys/nsim/nsim-ccm-mem.dtsi diff --git a/boards/arc/nsim/nsim-flash-sram-mem.dtsi b/boards/synopsys/nsim/nsim-flash-sram-mem.dtsi similarity index 100% rename from boards/arc/nsim/nsim-flash-sram-mem.dtsi rename to boards/synopsys/nsim/nsim-flash-sram-mem.dtsi diff --git a/boards/arc/nsim/nsim-flat-mem.dtsi b/boards/synopsys/nsim/nsim-flat-mem.dtsi similarity index 100% rename from boards/arc/nsim/nsim-flat-mem.dtsi rename to boards/synopsys/nsim/nsim-flat-mem.dtsi diff --git a/boards/arc/nsim/nsim-smp.dtsi b/boards/synopsys/nsim/nsim-smp.dtsi similarity index 100% rename from boards/arc/nsim/nsim-smp.dtsi rename to boards/synopsys/nsim/nsim-smp.dtsi diff --git a/boards/arc/nsim/nsim-uart-hostlink.dtsi b/boards/synopsys/nsim/nsim-uart-hostlink.dtsi similarity index 100% rename from boards/arc/nsim/nsim-uart-hostlink.dtsi rename to boards/synopsys/nsim/nsim-uart-hostlink.dtsi diff --git a/boards/arc/nsim/nsim-uart-ns16550.dtsi b/boards/synopsys/nsim/nsim-uart-ns16550.dtsi similarity index 100% rename from boards/arc/nsim/nsim-uart-ns16550.dtsi rename to boards/synopsys/nsim/nsim-uart-ns16550.dtsi diff --git a/boards/arc/nsim/nsim.dtsi b/boards/synopsys/nsim/nsim.dtsi similarity index 100% rename from boards/arc/nsim/nsim.dtsi rename to boards/synopsys/nsim/nsim.dtsi diff --git a/boards/arc/nsim/nsim_em-sec.dtsi b/boards/synopsys/nsim/nsim_em-sec.dtsi similarity index 100% rename from boards/arc/nsim/nsim_em-sec.dtsi rename to boards/synopsys/nsim/nsim_em-sec.dtsi diff --git a/boards/arc/nsim/nsim_em.dtsi b/boards/synopsys/nsim/nsim_em.dtsi similarity index 100% rename from boards/arc/nsim/nsim_em.dtsi rename to boards/synopsys/nsim/nsim_em.dtsi diff --git a/boards/arc/nsim/nsim_em.dts b/boards/synopsys/nsim/nsim_nsim_em.dts similarity index 100% rename from boards/arc/nsim/nsim_em.dts rename to boards/synopsys/nsim/nsim_nsim_em.dts diff --git a/boards/synopsys/nsim/nsim_nsim_em.yaml b/boards/synopsys/nsim/nsim_nsim_em.yaml new file mode 100644 index 00000000000..7fd973932eb --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_em +name: EM Nsim simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_em11d.dts b/boards/synopsys/nsim/nsim_nsim_em11d.dts similarity index 100% rename from boards/arc/nsim/nsim_em11d.dts rename to boards/synopsys/nsim/nsim_nsim_em11d.dts diff --git a/boards/synopsys/nsim/nsim_nsim_em11d.yaml b/boards/synopsys/nsim/nsim_nsim_em11d.yaml new file mode 100644 index 00000000000..e37aeb2f442 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em11d.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_em11d +name: EM11D Nsim simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_em11d_defconfig b/boards/synopsys/nsim/nsim_nsim_em11d_defconfig new file mode 100644 index 00000000000..1cdf8a0b67e --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em11d_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/arc/nsim/nsim_em7d_v22.dts b/boards/synopsys/nsim/nsim_nsim_em7d_v22.dts similarity index 100% rename from boards/arc/nsim/nsim_em7d_v22.dts rename to boards/synopsys/nsim/nsim_nsim_em7d_v22.dts diff --git a/boards/synopsys/nsim/nsim_nsim_em7d_v22.yaml b/boards/synopsys/nsim/nsim_nsim_em7d_v22.yaml new file mode 100644 index 00000000000..c77c883ccc8 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em7d_v22.yaml @@ -0,0 +1,14 @@ +identifier: nsim/nsim_em7d_v22 +name: EM nSIM simulator (EM7D_v22) +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_em7d_v22_defconfig b/boards/synopsys/nsim/nsim_nsim_em7d_v22_defconfig new file mode 100644 index 00000000000..1cdf8a0b67e --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em7d_v22_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/synopsys/nsim/nsim_nsim_em_defconfig b/boards/synopsys/nsim/nsim_nsim_em_defconfig new file mode 100644 index 00000000000..1cdf8a0b67e --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/arc/nsim/nsim_hs.dts b/boards/synopsys/nsim/nsim_nsim_hs.dts similarity index 100% rename from boards/arc/nsim/nsim_hs.dts rename to boards/synopsys/nsim/nsim_nsim_hs.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs.yaml b/boards/synopsys/nsim/nsim_nsim_hs.yaml new file mode 100644 index 00000000000..2f02bf5c85a --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs +name: HS nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_hs5x.dts b/boards/synopsys/nsim/nsim_nsim_hs5x.dts similarity index 100% rename from boards/arc/nsim/nsim_hs5x.dts rename to boards/synopsys/nsim/nsim_nsim_hs5x.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x.yaml b/boards/synopsys/nsim/nsim_nsim_hs5x.yaml new file mode 100644 index 00000000000..a20ad79a34a --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs5x +name: HS5x nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - arcmwdt + - cross-compile +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x_defconfig b/boards/synopsys/nsim/nsim_nsim_hs5x_defconfig new file mode 100644 index 00000000000..5a48971e06d --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ISA_ARCV3=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arc/nsim/nsim_hs5x_smp.dts b/boards/synopsys/nsim/nsim_nsim_hs5x_smp.dts similarity index 100% rename from boards/arc/nsim/nsim_hs5x_smp.dts rename to boards/synopsys/nsim/nsim_nsim_hs5x_smp.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x_smp.yaml b/boards/synopsys/nsim/nsim_nsim_hs5x_smp.yaml new file mode 100644 index 00000000000..09dcfd014ef --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x_smp.yaml @@ -0,0 +1,18 @@ +identifier: nsim/nsim_hs5x/smp +name: Multi-core HS5x nSIM simulator +type: sim +simulation: mdb-nsim +simulation_exec: mdb +arch: arc +toolchain: + - zephyr + - arcmwdt + - cross-compile +supported: + - smp +testing: + timeout_multiplier: 1.5 + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_hs5x_smp_12cores.dts b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.dts similarity index 100% rename from boards/arc/nsim/nsim_hs5x_smp_12cores.dts rename to boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.yaml b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.yaml new file mode 100644 index 00000000000..63a60a3423a --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.yaml @@ -0,0 +1,17 @@ +identifier: nsim/nsim_hs5x/smp/12cores +name: Multi-core HS5x nSIM simulator (12 cores) +type: sim +simulation: mdb-nsim +simulation_exec: mdb +arch: arc +toolchain: + - zephyr + - arcmwdt + - cross-compile +supported: + - smp +testing: + timeout_multiplier: 4 + ignore_tags: + - net + - bluetooth diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores_defconfig b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores_defconfig new file mode 100644 index 00000000000..cea98ef287a --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MP_MAX_NUM_CPUS=12 diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x_smp_defconfig b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_defconfig new file mode 100644 index 00000000000..112ba7f1bd0 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs6x.dts b/boards/synopsys/nsim/nsim_nsim_hs6x.dts similarity index 100% rename from boards/arc/nsim/nsim_hs6x.dts rename to boards/synopsys/nsim/nsim_nsim_hs6x.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x.yaml b/boards/synopsys/nsim/nsim_nsim_hs6x.yaml new file mode 100644 index 00000000000..08d1fecc9c2 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs6x +name: HS6x nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - arcmwdt + - cross-compile + - zephyr +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x_defconfig b/boards/synopsys/nsim/nsim_nsim_hs6x_defconfig new file mode 100644 index 00000000000..5a48971e06d --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ISA_ARCV3=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arc/nsim/nsim_hs6x_smp.dts b/boards/synopsys/nsim/nsim_nsim_hs6x_smp.dts similarity index 100% rename from boards/arc/nsim/nsim_hs6x_smp.dts rename to boards/synopsys/nsim/nsim_nsim_hs6x_smp.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x_smp.yaml b/boards/synopsys/nsim/nsim_nsim_hs6x_smp.yaml new file mode 100644 index 00000000000..5db80b6afa1 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x_smp.yaml @@ -0,0 +1,18 @@ +identifier: nsim/nsim_hs6x/smp +name: Multi-core HS6x nSIM simulator +type: sim +simulation: mdb-nsim +simulation_exec: mdb +arch: arc +toolchain: + - cross-compile + - zephyr + - arcmwdt +supported: + - smp +testing: + timeout_multiplier: 1.5 + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_hs6x_smp_12cores.dts b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.dts similarity index 100% rename from boards/arc/nsim/nsim_hs6x_smp_12cores.dts rename to boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.yaml b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.yaml new file mode 100644 index 00000000000..085f4bb93d5 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.yaml @@ -0,0 +1,17 @@ +identifier: nsim/nsim_hs6x/smp/12cores +name: Multi-core HS6x nSIM simulator (12 cores) +type: sim +simulation: mdb-nsim +simulation_exec: mdb +arch: arc +toolchain: + - cross-compile + - zephyr + - arcmwdt +supported: + - smp +testing: + timeout_multiplier: 4 + ignore_tags: + - net + - bluetooth diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores_defconfig b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores_defconfig new file mode 100644 index 00000000000..cea98ef287a --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MP_MAX_NUM_CPUS=12 diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x_smp_defconfig b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_defconfig new file mode 100644 index 00000000000..112ba7f1bd0 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/synopsys/nsim/nsim_nsim_hs_defconfig b/boards/synopsys/nsim/nsim_nsim_hs_defconfig new file mode 100644 index 00000000000..123983e3241 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/nsim/nsim_hs_flash_xip.dts b/boards/synopsys/nsim/nsim_nsim_hs_flash_xip.dts similarity index 100% rename from boards/arc/nsim/nsim_hs_flash_xip.dts rename to boards/synopsys/nsim/nsim_nsim_hs_flash_xip.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs_flash_xip.yaml b/boards/synopsys/nsim/nsim_nsim_hs_flash_xip.yaml new file mode 100644 index 00000000000..e39cfe00f9a --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_flash_xip.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs/flash_xip +name: HS nSIM simulator (FLASH XIP) +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_hs_flash_xip_defconfig b/boards/synopsys/nsim/nsim_nsim_hs_flash_xip_defconfig new file mode 100644 index 00000000000..4c4786d7291 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_flash_xip_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=y +CONFIG_HARVARD=n diff --git a/boards/arc/nsim/nsim_hs3x_hostlink.dts b/boards/synopsys/nsim/nsim_nsim_hs_hostlink.dts similarity index 100% rename from boards/arc/nsim/nsim_hs3x_hostlink.dts rename to boards/synopsys/nsim/nsim_nsim_hs_hostlink.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs_hostlink.yaml b/boards/synopsys/nsim/nsim_nsim_hs_hostlink.yaml new file mode 100644 index 00000000000..6a2a224d2e6 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_hostlink.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs/hostlink +name: HS3x nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_hs_mpuv6.dts b/boards/synopsys/nsim/nsim_nsim_hs_mpuv6.dts similarity index 100% rename from boards/arc/nsim/nsim_hs_mpuv6.dts rename to boards/synopsys/nsim/nsim_nsim_hs_mpuv6.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs_mpuv6.yaml b/boards/synopsys/nsim/nsim_nsim_hs_mpuv6.yaml new file mode 100644 index 00000000000..03e5609e703 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_mpuv6.yaml @@ -0,0 +1,16 @@ +identifier: nsim/nsim_hs/mpuv6 +name: HS (with MPU v6) nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_hs_smp.dts b/boards/synopsys/nsim/nsim_nsim_hs_smp.dts similarity index 100% rename from boards/arc/nsim/nsim_hs_smp.dts rename to boards/synopsys/nsim/nsim_nsim_hs_smp.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs_smp.yaml b/boards/synopsys/nsim/nsim_nsim_hs_smp.yaml new file mode 100644 index 00000000000..50f910e3f8c --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_smp.yaml @@ -0,0 +1,19 @@ +identifier: nsim/nsim_hs/smp +name: Multi-core HS nSIM simulator +type: sim +simulation: mdb-nsim +simulation_exec: mdb +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +supported: + - smp +testing: + timeout_multiplier: 1.5 + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_hs_smp_defconfig b/boards/synopsys/nsim/nsim_nsim_hs_smp_defconfig new file mode 100644 index 00000000000..f6818014718 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_smp_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARC_MPU_ENABLE=n +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs_sram.dts b/boards/synopsys/nsim/nsim_nsim_hs_sram.dts similarity index 100% rename from boards/arc/nsim/nsim_hs_sram.dts rename to boards/synopsys/nsim/nsim_nsim_hs_sram.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs_sram.yaml b/boards/synopsys/nsim/nsim_nsim_hs_sram.yaml new file mode 100644 index 00000000000..f2d8a0e8bd9 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_sram.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs/sram +name: HS nSIM simulator (SRAM) +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_hs_sram_defconfig b/boards/synopsys/nsim/nsim_nsim_hs_sram_defconfig new file mode 100644 index 00000000000..fec69adbb50 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_sram_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_HARVARD=n diff --git a/boards/arc/nsim/nsim_sem.dts b/boards/synopsys/nsim/nsim_nsim_sem.dts similarity index 100% rename from boards/arc/nsim/nsim_sem.dts rename to boards/synopsys/nsim/nsim_nsim_sem.dts diff --git a/boards/synopsys/nsim/nsim_nsim_sem.yaml b/boards/synopsys/nsim/nsim_nsim_sem.yaml new file mode 100644 index 00000000000..fadc0783f72 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_sem.yaml @@ -0,0 +1,16 @@ +identifier: nsim/nsim_sem +name: SEM Nsim simulator +type: sim +arch: arc +simulation: nsim +simulation_exec: nsimdrv +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_sem_defconfig b/boards/synopsys/nsim/nsim_nsim_sem_defconfig new file mode 100644 index 00000000000..deb2c9c0571 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_sem_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arc/nsim/nsim_sem_mpu_stack_guard.dts b/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.dts similarity index 100% rename from boards/arc/nsim/nsim_sem_mpu_stack_guard.dts rename to boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.dts diff --git a/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.yaml b/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.yaml new file mode 100644 index 00000000000..986345ab8e0 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_sem/mpu_stack_guard +name: SEM nSIM simulator (stack guard) +type: sim +arch: arc +simulation: nsim +simulation_exec: nsimdrv +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig b/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig new file mode 100644 index 00000000000..8fe546e4302 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARC_HAS_STACK_CHECKING=n diff --git a/boards/arc/nsim/nsim_vpx5.dts b/boards/synopsys/nsim/nsim_nsim_vpx5.dts similarity index 100% rename from boards/arc/nsim/nsim_vpx5.dts rename to boards/synopsys/nsim/nsim_nsim_vpx5.dts diff --git a/boards/synopsys/nsim/nsim_nsim_vpx5.yaml b/boards/synopsys/nsim/nsim_nsim_vpx5.yaml new file mode 100644 index 00000000000..b1169acd111 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_vpx5.yaml @@ -0,0 +1,13 @@ +identifier: nsim/nsim_vpx5 +name: VPX5 nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_vpx5_defconfig b/boards/synopsys/nsim/nsim_nsim_vpx5_defconfig new file mode 100644 index 00000000000..8ba152d9d36 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_vpx5_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arc/nsim/support/mdb_em.args b/boards/synopsys/nsim/support/mdb_em.args similarity index 100% rename from boards/arc/nsim/support/mdb_em.args rename to boards/synopsys/nsim/support/mdb_em.args diff --git a/boards/arc/nsim/support/mdb_em11d.args b/boards/synopsys/nsim/support/mdb_em11d.args similarity index 100% rename from boards/arc/nsim/support/mdb_em11d.args rename to boards/synopsys/nsim/support/mdb_em11d.args diff --git a/boards/arc/nsim/support/mdb_em7d_v22.args b/boards/synopsys/nsim/support/mdb_em7d_v22.args similarity index 100% rename from boards/arc/nsim/support/mdb_em7d_v22.args rename to boards/synopsys/nsim/support/mdb_em7d_v22.args diff --git a/boards/arc/nsim/support/mdb_hs.args b/boards/synopsys/nsim/support/mdb_hs.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs.args rename to boards/synopsys/nsim/support/mdb_hs.args diff --git a/boards/arc/nsim/support/mdb_hs3x_hostlink.args b/boards/synopsys/nsim/support/mdb_hs3x_hostlink.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs3x_hostlink.args rename to boards/synopsys/nsim/support/mdb_hs3x_hostlink.args diff --git a/boards/arc/nsim/support/mdb_hs5x.args b/boards/synopsys/nsim/support/mdb_hs5x.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs5x.args rename to boards/synopsys/nsim/support/mdb_hs5x.args diff --git a/boards/arc/nsim/support/mdb_hs5x_smp.args b/boards/synopsys/nsim/support/mdb_hs5x_smp.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs5x_smp.args rename to boards/synopsys/nsim/support/mdb_hs5x_smp.args diff --git a/boards/arc/nsim/support/mdb_hs5x_smp_12cores.args b/boards/synopsys/nsim/support/mdb_hs5x_smp_12cores.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs5x_smp_12cores.args rename to boards/synopsys/nsim/support/mdb_hs5x_smp_12cores.args diff --git a/boards/arc/nsim/support/mdb_hs6x.args b/boards/synopsys/nsim/support/mdb_hs6x.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs6x.args rename to boards/synopsys/nsim/support/mdb_hs6x.args diff --git a/boards/arc/nsim/support/mdb_hs6x_smp.args b/boards/synopsys/nsim/support/mdb_hs6x_smp.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs6x_smp.args rename to boards/synopsys/nsim/support/mdb_hs6x_smp.args diff --git a/boards/arc/nsim/support/mdb_hs6x_smp_12cores.args b/boards/synopsys/nsim/support/mdb_hs6x_smp_12cores.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs6x_smp_12cores.args rename to boards/synopsys/nsim/support/mdb_hs6x_smp_12cores.args diff --git a/boards/arc/nsim/support/mdb_hs_flash_xip.args b/boards/synopsys/nsim/support/mdb_hs_flash_xip.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs_flash_xip.args rename to boards/synopsys/nsim/support/mdb_hs_flash_xip.args diff --git a/boards/arc/nsim/support/mdb_hs_mpuv6.args b/boards/synopsys/nsim/support/mdb_hs_mpuv6.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs_mpuv6.args rename to boards/synopsys/nsim/support/mdb_hs_mpuv6.args diff --git a/boards/arc/nsim/support/mdb_hs_smp.args b/boards/synopsys/nsim/support/mdb_hs_smp.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs_smp.args rename to boards/synopsys/nsim/support/mdb_hs_smp.args diff --git a/boards/arc/nsim/support/mdb_hs_sram.args b/boards/synopsys/nsim/support/mdb_hs_sram.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs_sram.args rename to boards/synopsys/nsim/support/mdb_hs_sram.args diff --git a/boards/arc/nsim/support/mdb_sem.args b/boards/synopsys/nsim/support/mdb_sem.args similarity index 100% rename from boards/arc/nsim/support/mdb_sem.args rename to boards/synopsys/nsim/support/mdb_sem.args diff --git a/boards/arc/nsim/support/mdb_vpx5.args b/boards/synopsys/nsim/support/mdb_vpx5.args similarity index 100% rename from boards/arc/nsim/support/mdb_vpx5.args rename to boards/synopsys/nsim/support/mdb_vpx5.args diff --git a/boards/arc/nsim/support/nsim_em.props b/boards/synopsys/nsim/support/nsim_em.props similarity index 100% rename from boards/arc/nsim/support/nsim_em.props rename to boards/synopsys/nsim/support/nsim_em.props diff --git a/boards/arc/nsim/support/nsim_em11d.props b/boards/synopsys/nsim/support/nsim_em11d.props similarity index 100% rename from boards/arc/nsim/support/nsim_em11d.props rename to boards/synopsys/nsim/support/nsim_em11d.props diff --git a/boards/arc/nsim/support/nsim_em7d_v22.props b/boards/synopsys/nsim/support/nsim_em7d_v22.props similarity index 100% rename from boards/arc/nsim/support/nsim_em7d_v22.props rename to boards/synopsys/nsim/support/nsim_em7d_v22.props diff --git a/boards/arc/nsim/support/nsim_hs.props b/boards/synopsys/nsim/support/nsim_hs.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs.props rename to boards/synopsys/nsim/support/nsim_hs.props diff --git a/boards/arc/nsim/support/nsim_hs3x_hostlink.props b/boards/synopsys/nsim/support/nsim_hs3x_hostlink.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs3x_hostlink.props rename to boards/synopsys/nsim/support/nsim_hs3x_hostlink.props diff --git a/boards/arc/nsim/support/nsim_hs5x.props b/boards/synopsys/nsim/support/nsim_hs5x.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs5x.props rename to boards/synopsys/nsim/support/nsim_hs5x.props diff --git a/boards/arc/nsim/support/nsim_hs6x.props b/boards/synopsys/nsim/support/nsim_hs6x.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs6x.props rename to boards/synopsys/nsim/support/nsim_hs6x.props diff --git a/boards/arc/nsim/support/nsim_hs_flash_xip.props b/boards/synopsys/nsim/support/nsim_hs_flash_xip.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs_flash_xip.props rename to boards/synopsys/nsim/support/nsim_hs_flash_xip.props diff --git a/boards/arc/nsim/support/nsim_hs_mpuv6.props b/boards/synopsys/nsim/support/nsim_hs_mpuv6.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs_mpuv6.props rename to boards/synopsys/nsim/support/nsim_hs_mpuv6.props diff --git a/boards/arc/nsim/support/nsim_hs_sram.props b/boards/synopsys/nsim/support/nsim_hs_sram.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs_sram.props rename to boards/synopsys/nsim/support/nsim_hs_sram.props diff --git a/boards/arc/nsim/support/nsim_sem.props b/boards/synopsys/nsim/support/nsim_sem.props similarity index 100% rename from boards/arc/nsim/support/nsim_sem.props rename to boards/synopsys/nsim/support/nsim_sem.props diff --git a/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.args b/boards/synopsys/nsim/support/nsim_sem_mpu_stack_guard.args similarity index 100% rename from boards/arc/nsim/support/nsim_sem_mpu_stack_guard.args rename to boards/synopsys/nsim/support/nsim_sem_mpu_stack_guard.args diff --git a/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.props b/boards/synopsys/nsim/support/nsim_sem_mpu_stack_guard.props similarity index 100% rename from boards/arc/nsim/support/nsim_sem_mpu_stack_guard.props rename to boards/synopsys/nsim/support/nsim_sem_mpu_stack_guard.props diff --git a/boards/arc/nsim/support/nsim_vpx5.props b/boards/synopsys/nsim/support/nsim_vpx5.props similarity index 100% rename from boards/arc/nsim/support/nsim_vpx5.props rename to boards/synopsys/nsim/support/nsim_vpx5.props diff --git a/boards/tdk/index.rst b/boards/tdk/index.rst new file mode 100644 index 00000000000..fe11070b5bc --- /dev/null +++ b/boards/tdk/index.rst @@ -0,0 +1,10 @@ +.. _boards-tdk: + +TDK +### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/tdk/robokit1/Kconfig.robokit1 b/boards/tdk/robokit1/Kconfig.robokit1 new file mode 100644 index 00000000000..136a9fe8df1 --- /dev/null +++ b/boards/tdk/robokit1/Kconfig.robokit1 @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Intel Corporation +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ROBOKIT1 + select SOC_SAME70Q21B diff --git a/boards/tdk/robokit1/board.cmake b/boards/tdk/robokit1/board.cmake new file mode 100644 index 00000000000..391006d62de --- /dev/null +++ b/boards/tdk/robokit1/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=ATSAME70Q21") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(openocd --cmd-post-verify "atsamv gpnvm set 1") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/tdk/robokit1/board.yml b/boards/tdk/robokit1/board.yml new file mode 100644 index 00000000000..c97c2a0c940 --- /dev/null +++ b/boards/tdk/robokit1/board.yml @@ -0,0 +1,5 @@ +board: + name: robokit1 + vendor: tdk + socs: + - name: same70q21b diff --git a/boards/arm/tdk_robokit1/doc/img/tdk_robokit1.jpg b/boards/tdk/robokit1/doc/img/tdk_robokit1.jpg similarity index 100% rename from boards/arm/tdk_robokit1/doc/img/tdk_robokit1.jpg rename to boards/tdk/robokit1/doc/img/tdk_robokit1.jpg diff --git a/boards/tdk/robokit1/doc/index.rst b/boards/tdk/robokit1/doc/index.rst new file mode 100644 index 00000000000..ef65431b7e5 --- /dev/null +++ b/boards/tdk/robokit1/doc/index.rst @@ -0,0 +1,184 @@ +.. _robokit1: + +TDK RoboKit 1 +############# + +Overview +******** + +The TDK RoboKit1 is a development board for use primarily with ROS2 and provides a large +number of small ground robotics useful sensors including chirp sensors for time of flight +(e.g. ultrasonic obstacle detection). + +It pairs a 300MHz Cortex-M7 ATSAME70Q21 with an array of TDK sensors and pin headers useful for robotics. + +.. image:: img/tdk_robokit1.jpg + :align: center + :alt: TDK RoboKit1 + +Hardware +******** + +- ATSAME70Q21 ARM Cortex-M7 Processor +- 12 MHz crystal oscillator (Pres) +- 32.768 kHz crystal oscillator +- Micro-AB USB device +- Micro-AB USB debug (Microchip EDBG) interface supporting CMSIS-DAP, Virtual COM Port and Data +- JTAG interface connector +- One reset pushbutton +- One red user LED +- TDK ICM 42688-P 6-Axis 32KHz IMU +- TDK ICP-10111 Pressure Sensor +- TDK NTC Thermistor for Temperature +- AKM AK09918C Magnetometer +- 2 TDK HVCi-4223 Cortex-M3 Dedicated Motor Controller +- 3 TDK ICS-43434 Stereo Microphones +- Connector for Industrial Dual IMU (TDK IIM-46230) +- TDK CH101 Ultrasonic Range Sensor Array (9 Connectors, comes with 3) + +Supported Features +================== + +The TDK RoboKit1 board supports the following hardware +features: + +.. list-table:: + : header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - GPIO + - :kconfig:option:`CONFIG_GPIO_SAM` + - :dtcompatible:`atmel,sam-gpio` + * - USART + - :kconfig:option:`CONFIG_USART_SAM` + - :dtcompatible:`atmel,sam-usart` + * - UART + - :kconfig:option:`CONFIG_UART_SAM` + - :dtcompatible:`atmel,sam-uart` + * - SPI + - :kconfig:option:`CONFIG_SPI_SAM` + - :dtcompatible:`atmel,sam-spi` + * - I2C + - :kconfig:option:`CONFIG_I2C_SAM_TWIHS` + - :dtcompatible:`atmel,sam-i2c-twihs` + * - I2S + - :kconfig:option:`CONFIG_I2S_SAM_SSC` + - :dtcompatible:`atmel,sam-ssc` + * - ADC + - :kconfig:option:`CONFIG_ADC_SAM_AFEC` + - :dtcompatible:`atmel,sam-afec` + * - DAC + - :kconfig:option:`CONFIG_DAC_SAM` + - :dtcompatible:`atmel,sam-dac` + * - PWM + - :kconfig:option:`CONFIG_PWM_SAM` + - :dtcompatible:`atmel,sam-pwm` + * - CAN + - :kconfig:option:`CONFIG_CAN_SAM` + - :dtcompatible:`atmel,sam-can` + * - USB + - :kconfig:option:`CONFIG_USB_DC_SAM_USBHS` + - :dtcompatible:`atmel,sam-usbhs` + * - WATCHDOG + - :kconfig:option:`CONFIG_WDT_SAM` + - :dtcompatible:`atmel,sam-watchdog` + * - NVIC + - N/A + - :dtcompatible:`arm,v7m-nvic` + * - SYSTICK + - N/A + - N/A + * - COUNTER + - :kconfig:option:`CONFIG_COUNTER_SAM_TC` + - :dtcompatible:`atmel,sam-tc` + * - DMA + - :kconfig:option:`CONFIG_DMA_SAM_XDMAC` + - :dtcompatible:`atmel,sam-xdmac` + * - ENTROPY + - :kconfig:option:`CONFIG_ENTROPY_SAM_RNG` + - :dtcompatible:`atmel,sam-trng` + * - HWINFO (reset cause) + - :kconfig:option:`CONFIG_HWINFO_SAM_RSTC` + - :dtcompatible:`atmel,sam-rstc` + * - HWINFO (device id) + - :kconfig:option:`CONFIG_HWINFO_SAM` + - N/A + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/tdk/robokit1/robokit1_defconfig`. + +Connections and IOs +=================== + +The TDK RoboKit Hardware Guide has detailed information about board connections. + +System Clock +============ + +The SAM E70 MCU is configured to use the 12 MHz external oscillator on the board +with the on-chip PLL to generate a 300 MHz system clock. + +Serial Port +=========== + +The ATSAME70Q21 MCU has five UARTs and three USARTs. One of the UARTs is +configured for the console and is available as a Virtual COM Port via the USB2 connector. + +Programming and Debugging +************************* + +Flashing the Zephyr project onto SAM E70 MCU requires the `OpenOCD tool`_. +Both west flash and west debug commands should correctly work with both USB0 and USB1 +connected and the board powered. + +Flashing +======== + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the TDK RoboKit1 board to your host computer using the + USB debug port (USB1), USB2 for a serial console, and remaining micro USB for + power. Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: robokit1 + :goals: build flash + + You should see "Hello World! robokit1" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: robokit1 + :maybe-skip-config: + :goals: debug + +References +********** + +TDK RoboKit1 Product Page: + https://invensense.tdk.com/products/robokit1-dk/ + +.. _OpenOCD tool: + http://openocd.org/ diff --git a/boards/tdk/robokit1/robokit1-common.dtsi b/boards/tdk/robokit1/robokit1-common.dtsi new file mode 100644 index 00000000000..40fa35366a2 --- /dev/null +++ b/boards/tdk/robokit1/robokit1-common.dtsi @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2022 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "robokit1-pinctrl.dtsi" + +/ { + aliases { + led0 = &led_0; + magn0 = &akm09918c; + accel0 = &icm42688; + die-temp0 = &icm42688; + ambient-temp0 = &temp_sensor; + }; + + chosen { + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + led_0: led_0 { + gpios = <&pioa 11 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + led_1: led_1 { + gpios = <&pioa 12 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + led_2: led_2 { + gpios = <&pioa 13 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + led_3: led_3 { + gpios = <&pioa 14 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + temp_sensor: ambient_temp_sensor { + compatible = "epcos,b57861s0103a039"; + io-channels = <&spi_adc 0>; + pullup-uv = <3300000>; + pullup-ohm = <0>; + pulldown-ohm = <10000>; + connected-positive; + }; +}; + +&cpu0 { + clock-frequency = <300000000>; +}; + +&afec0 { + pinctrl-0 = <&afec0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dacc { + status = "okay"; +}; + +&twihs0 { + pinctrl-0 = <&twihs0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&twihs1 { + pinctrl-0 = <&twihs1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&twihs2 { + pinctrl-0 = <&twihs2_default>; + pinctrl-names = "default"; + status = "okay"; + akm09918c: akm09918c@c { + compatible = "asahi-kasei,akm09918c"; + reg = <0xc>; + }; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + dmas = <&xdmac 0 DMA_PERID_SPI0_TX>, <&xdmac 1 DMA_PERID_SPI0_RX>; + dma-names = "tx", "rx"; + cs-gpios =<&pioa 31 GPIO_ACTIVE_LOW>, + <&pioc 31 GPIO_ACTIVE_LOW>; + status = "okay"; + + icm42688: icm42688p@0 { + compatible = "invensense,icm42688"; + reg = <0>; + int-gpios = <&pioc 5 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <24000000>; + accel-hz = <32000>; + accel-fs = <16>; + gyro-hz = <32000>; + gyro-fs = <2000>; + }; + spi_adc: adc@1 { + compatible = "ti,ads7052"; + reg = <1>; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <24000000>; + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_VDD_1"; + zephyr,vref-mv = <3300>; + zephyr,acquisition-time = ; + zephyr,resolution = <14>; + }; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + cs-gpios = <&pioc 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usart2 { + current-speed = <115200>; + pinctrl-0 = <&usart2_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +zephyr_udc0: &usbhs { + status = "okay"; +}; + +&mdio { + pinctrl-0 = <&mdio_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm0 { + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; + status = "okay"; +}; + + +&xdmac { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The first half of sector 0 (64 kbytes) + * is reserved for the bootloader + */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x00010000>; + read-only; + }; + + /* From sector 1 to sector 7 (included): slot0 (896 kbytes) */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 0x000e0000>; + }; + + /* From sector 8 to sector 14 (included): slot1 (896 kbytes) */ + slot1_partition: partition@100000 { + label = "image-1"; + reg = <0x00100000 0x000e0000>; + }; + + /* Sector 15: scratch (128 kbytes) */ + scratch_partition: partition@1e0000 { + label = "image-scratch"; + reg = <0x001e0000 0x00020000>; + }; + }; +}; diff --git a/boards/arm/tdk_robokit1/tdk_robokit1-pinctrl.dtsi b/boards/tdk/robokit1/robokit1-pinctrl.dtsi similarity index 100% rename from boards/arm/tdk_robokit1/tdk_robokit1-pinctrl.dtsi rename to boards/tdk/robokit1/robokit1-pinctrl.dtsi diff --git a/boards/tdk/robokit1/robokit1.dts b/boards/tdk/robokit1/robokit1.dts new file mode 100644 index 00000000000..46d160b2074 --- /dev/null +++ b/boards/tdk/robokit1/robokit1.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2022 Intel Corporation + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +#include "robokit1-common.dtsi" + +/ { + model = "TDK RoboKit1"; + compatible = "tdk,robokit1", "atmel,same70q21b", "atmel,same70"; +}; diff --git a/boards/tdk/robokit1/robokit1.yaml b/boards/tdk/robokit1/robokit1.yaml new file mode 100644 index 00000000000..8cbd19f73a6 --- /dev/null +++ b/boards/tdk/robokit1/robokit1.yaml @@ -0,0 +1,21 @@ +identifier: robokit1 +name: TDK RoboKit1 +type: mcu +arch: arm +flash: 2048 +ram: 384 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - can + - dma + - hwinfo + - gpio + - i2c + - pwm + - spi + - usb_device + - watchdog +vendor: tdk diff --git a/boards/tdk/robokit1/robokit1_defconfig b/boards/tdk/robokit1/robokit1_defconfig new file mode 100644 index 00000000000..0f48eff3adf --- /dev/null +++ b/boards/tdk/robokit1/robokit1_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/tdk_robokit1/support/openocd.cfg b/boards/tdk/robokit1/support/openocd.cfg similarity index 100% rename from boards/arm/tdk_robokit1/support/openocd.cfg rename to boards/tdk/robokit1/support/openocd.cfg diff --git a/boards/technexion/index.rst b/boards/technexion/index.rst new file mode 100644 index 00000000000..31b1d47e448 --- /dev/null +++ b/boards/technexion/index.rst @@ -0,0 +1,10 @@ +.. _boards-technexion: + +TECHNEXION +########## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/technexion/pico_pi/Kconfig.defconfig b/boards/technexion/pico_pi/Kconfig.defconfig new file mode 100644 index 00000000000..aebd510fe61 --- /dev/null +++ b/boards/technexion/pico_pi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Pico-Pi iMX7D M4 board + +# Copyright (c) 2019, Joris Offouga +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PICO_PI + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_PICO_PI diff --git a/boards/technexion/pico_pi/Kconfig.pico_pi b/boards/technexion/pico_pi/Kconfig.pico_pi new file mode 100644 index 00000000000..02def5fdc0e --- /dev/null +++ b/boards/technexion/pico_pi/Kconfig.pico_pi @@ -0,0 +1,7 @@ +# Copyright (c) 2019, Joris Offouga +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PICO_PI + select SOC_PART_NUMBER_MCIMX7D7DVM10SC + select SOC_MCIMX7D_M4 if BOARD_PICO_PI_MCIMX7D_M4 diff --git a/boards/technexion/pico_pi/board.yml b/boards/technexion/pico_pi/board.yml new file mode 100644 index 00000000000..61c6713a925 --- /dev/null +++ b/boards/technexion/pico_pi/board.yml @@ -0,0 +1,5 @@ +board: + name: pico_pi + vendor: technexion + socs: + - name: mcimx7d diff --git a/boards/technexion/pico_pi/doc/index.rst b/boards/technexion/pico_pi/doc/index.rst new file mode 100644 index 00000000000..3b651729227 --- /dev/null +++ b/boards/technexion/pico_pi/doc/index.rst @@ -0,0 +1,239 @@ +.. _pico_pi: + +Pico-Pi i.MX7D - Android Things IoT Development Platform +############################################################# + +Overview +******** + +The i.MX7D SoC is a Hybrid multi-core processor composed of Single Cortex A7 +core and Single Cortex M4 core. +Zephyr was ported to run on the M4 core. In a later release, it will also +communicate with the A7 core (running Linux) via RPmsg. + + +.. image:: pico_pi.jpg + :align: center + :alt: Pico-Pi i.MX7D + +Hardware +******** + +The Pico-Pi Platform is composed of a CPU and IO board. + +Pico-Pi IO Board +================ +- S1 - On/Off (MX7_ONOFF signal) +- Board to board connector : Edison compatible connector (70 configurable pins) +- mikroBUS expansion connector ADC, GPIO, I²C, PWM, SPI, UART) +- 10-pin needle JTAG Connector +- Debug USB exposing One UART +- MIPI DSI 1 lane Connector +- LCD Touch Connector +- Audio Jack: Mic and Stereo Headphone + +Pico-Pi CPU Board +================= + +- CPU i.MX7 Dual with a Single Cortex A7 (1 GHz) core and + Single Cortex M4 (200MHz) core +- Memory + + - RAM -> A7: 4GB + - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) + - Flash -> A7: 8GB eMMC + +For more information about the i.MX7 SoC and Pico-Pi i.MX7D, see these references: + +- `i.MX 7 Series Website`_ +- `i.MX 7 Dual Datasheet`_ +- `i.MX 7 Dual Reference Manual`_ + +Supported Features +================== + +The Pico-Pi i.MX7D configuration supports the following hardware features on the +Cortex M4 Core: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The Pico-Pi board Board was tested with the following pinmux controller +configuration. + ++---------------+---------------------+--------------------------------+ +| Board Name | SoC Name | Usage | ++===============+=====================+================================+ +| UART_TX232 | UART1_TX | UART Console | ++---------------+---------------------+--------------------------------+ +| UART_RX232 | UART1_RX | UART Console | ++---------------+---------------------+--------------------------------+ +| RX_E | UART6_TX | UART (mikroBUS and Edison) | ++---------------+---------------------+--------------------------------+ +| TX_E | UART6_RX | UART (mikroBUS and Edison) | ++---------------+---------------------+--------------------------------+ +| I2CX_SDA_3V | I2C1_SDA | I2C (mikroBUS and Edison) | ++---------------+---------------------+--------------------------------+ +| I2CX_SCL_3V | I2C1_SCL | I2C (mikroBUS and Edison) | ++---------------+---------------------+--------------------------------+ + +System Clock +============ + +The M4 Core is configured to run at a 200 MHz clock speed. + +Serial Port +=========== + +The iMX7D SoC has seven UARTs. The number 6 is configured for the console and +the number 2 is used in the mikroBUS connector. + +Programming and Debugging +************************* + +The Pico-Pi i.MX7D doesn't have QSPI flash for the M4 and it needs to be started by +the A7 core. The A7 core is responsible to load the M4 binary application into +the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and +get the M4 out of reset. +The A7 can perform these steps at bootloader level or after the Linux system +has booted. + +The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and +M4: + ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=======================+========================+=======================+======================+ +| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ + +References +========== + +- `i.MX 7 Dual Reference Manual`_ from page 182 (section 2.1.2 and 2.1.3) +- `Toradex Wiki`_ + + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file :zephyr_file:`boards/technexion/pico_pi/pico_pi_mcimx7d_m4.dts` with +"zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. The available +configurations are: + +.. code-block:: none + + "zephyr,flash" + - &ddr_code + - &tcml_code + - &ocram_code + - &ocram_s_code + - &ocram_pxp_code + - &ocram_epdc_code + + "zephyr,sram" + - &ddr_sys + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + - &ocram_pxp_sys + - &ocram_epdc_sys + + +Below you will find the instructions to load and run Zephyr on M4 from A7 using +u-boot. + +Connect both micro USB interfaces into the PC. This is the A7 console and the +UART6 in the Edison connector is M4 console for Zephyr with both configured to work at 115200 8N1. +The USB interface is used to power the CPU and IO boards and is connected +to the USB OTG interface of the i.MX7D. + +After powering up the platform stop the u-boot execution on the A7 core and +expose the eMMC as mass storage with the following command in the u-boot +prompt: ``ums 0 mmc 0``. Copy the compiled zephyr.bin to the first FAT +partition and remove the mounted device on the PC by issuing a "Ctrl+C" in the +u-boot prompt. +Set the u-boot environment variables and run the zephyr.bin from the +appropriated memory configured in the Zephyr compilation: + +.. code-block:: console + + setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' + # TCML + setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' + setenv bootm4tcml 'run m4tcml && run bootm4' + run bootm4tcml + # TCMU + setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' + setenv bootm4tcmu 'run m4tcmu && run bootm4' + run bootm4tcmu + # OCRAM + setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' + setenv bootm4ocram 'run m4ocram && run bootm4' + run bootm4ocram + # OCRAM_S + setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' + setenv bootm4ocrams 'run m4ocrams && run bootm4' + run bootm4ocrams + # DDR + setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' + setenv bootm4ddr 'run m4ddr && run bootm4' + run bootm4ddr + +:ref:`build_an_application` and :ref:`application_run` for more details). + +References +========== + +- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ +- `J-Link iMX7D Instructions`_ + +.. _i.MX 7 Series Website: + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 + +.. _i.MX 7 Dual Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf + +.. _i.MX 7 Dual Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX7DRM + +.. _J-Link Tools: + https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack + +.. _NXP iMX7D Connect CortexM4.JLinkScript: + https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript + +.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: + https://www.nxp.com/docs/en/application-note/AN5317.pdf + +.. _J-Link iMX7D Instructions: + https://wiki.segger.com/IMX7D + +.. _Toradex Wiki: + https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/pico_pi_m4/doc/pico_pi_m4.jpg b/boards/technexion/pico_pi/doc/pico_pi.jpg similarity index 100% rename from boards/arm/pico_pi_m4/doc/pico_pi_m4.jpg rename to boards/technexion/pico_pi/doc/pico_pi.jpg diff --git a/boards/arm/pico_pi_m4/pico_pi_m4-pinctrl.dtsi b/boards/technexion/pico_pi/pico_pi-pinctrl.dtsi similarity index 100% rename from boards/arm/pico_pi_m4/pico_pi_m4-pinctrl.dtsi rename to boards/technexion/pico_pi/pico_pi-pinctrl.dtsi diff --git a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.dts b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.dts new file mode 100644 index 00000000000..988d5c2e398 --- /dev/null +++ b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.dts @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2019, Joris Offouga + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "pico_pi-pinctrl.dtsi" + +/ { + model = "Pico-Pi IMX7D board"; + compatible = "nxp,mcimx7d_m4"; + + aliases { + uart-6 = &uart6; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart6; + zephyr,shell-uart = &uart6; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&uart5 { + pinctrl-0 = <&uart5_default>; + pinctrl-names = "default"; +}; + +&uart6 { + status = "okay"; + current-speed = <115200>; + modem-mode = <0>; + pinctrl-0 = <&uart6_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_default>; + pinctrl-names = "default"; +}; diff --git a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml new file mode 100644 index 00000000000..7baa570c548 --- /dev/null +++ b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2019, Joris Offouga +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: pico_pi/mcimx7d/m4 +name: Pico-Pi IMX7D +type: mcu +arch: arm +ram: 32 +flash: 32 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig new file mode 100644 index 00000000000..a9f1db5c8a7 --- /dev/null +++ b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2019, Joris Offouga +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_GPIO=n +CONFIG_PINCTRL=y diff --git a/boards/telink/index.rst b/boards/telink/index.rst new file mode 100644 index 00000000000..52bece46290 --- /dev/null +++ b/boards/telink/index.rst @@ -0,0 +1,10 @@ +.. _boards-telink: + +Telink Semiconductor +#################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/telink/tlsr9518adk80d/Kconfig.defconfig b/boards/telink/tlsr9518adk80d/Kconfig.defconfig new file mode 100644 index 00000000000..001ad287586 --- /dev/null +++ b/boards/telink/tlsr9518adk80d/Kconfig.defconfig @@ -0,0 +1,38 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_TLSR9518ADK80D + +config SOC_FLASH_TELINK_B91 + default y if FLASH + +if BT + +# BLE Controller SDK from hal_telink requires +# Telink's toolchain with FPU support +config FPU + default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" + +config BT_HCI_ACL_FLOW_CONTROL + default n + +choice BT_HCI_BUS_TYPE + default BT_B91 +endchoice + +endif # BT + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_DT_CODE_PARTITION + +# Buffer for image writter shall be less(multiple of access alignment) or +# equal to flash page. tlsr9518adk80d boards use external P25Q16 IC as +# flesh memory. Flash page size of the IC is 256 bytes. So that, it is +# maximum image writer buffer size for such kind of boards. +config IMG_BLOCK_BUF_SIZE + default 256 if MCUBOOT_IMG_MANAGER + +endif diff --git a/boards/telink/tlsr9518adk80d/Kconfig.tlsr9518adk80d b/boards/telink/tlsr9518adk80d/Kconfig.tlsr9518adk80d new file mode 100644 index 00000000000..5c88071e686 --- /dev/null +++ b/boards/telink/tlsr9518adk80d/Kconfig.tlsr9518adk80d @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TLSR9518ADK80D + select SOC_TLSR9518 diff --git a/boards/riscv/tlsr9518adk80d/board.cmake b/boards/telink/tlsr9518adk80d/board.cmake similarity index 100% rename from boards/riscv/tlsr9518adk80d/board.cmake rename to boards/telink/tlsr9518adk80d/board.cmake diff --git a/boards/telink/tlsr9518adk80d/board.yml b/boards/telink/tlsr9518adk80d/board.yml new file mode 100644 index 00000000000..b4d45ba665d --- /dev/null +++ b/boards/telink/tlsr9518adk80d/board.yml @@ -0,0 +1,5 @@ +board: + name: tlsr9518adk80d + vendor: telink + socs: + - name: tlsr9518 diff --git a/boards/riscv/tlsr9518adk80d/doc/img/tlsr9518_block_diagram.jpg b/boards/telink/tlsr9518adk80d/doc/img/tlsr9518_block_diagram.jpg similarity index 100% rename from boards/riscv/tlsr9518adk80d/doc/img/tlsr9518_block_diagram.jpg rename to boards/telink/tlsr9518adk80d/doc/img/tlsr9518_block_diagram.jpg diff --git a/boards/riscv/tlsr9518adk80d/doc/img/tlsr9518adk80d.jpg b/boards/telink/tlsr9518adk80d/doc/img/tlsr9518adk80d.jpg similarity index 100% rename from boards/riscv/tlsr9518adk80d/doc/img/tlsr9518adk80d.jpg rename to boards/telink/tlsr9518adk80d/doc/img/tlsr9518adk80d.jpg diff --git a/boards/telink/tlsr9518adk80d/doc/index.rst b/boards/telink/tlsr9518adk80d/doc/index.rst new file mode 100644 index 00000000000..e80db259a77 --- /dev/null +++ b/boards/telink/tlsr9518adk80d/doc/index.rst @@ -0,0 +1,267 @@ +.. _tlsr9518adk80d: + +Telink TLSR9518ADK80D +##################### + +Overview +******** + +The TLSR9518A Generic Starter Kit is a hardware platform which +can be used to verify the `Telink TLSR951x series chipset`_ and develop applications +for several 2.4 GHz air interface standards including Bluetooth 5.2 (Basic data +rate, Enhanced data rate, LE, Indoor positioning and BLE Mesh), +Zigbee 3.0, Homekit, 6LoWPAN, Thread and 2.4 Ghz proprietary. + +.. figure:: img/tlsr9518adk80d.jpg + :align: center + :alt: TLSR9518ADK80D + +More information about the board can be found at the `Telink B91 Generic Starter Kit Hardware Guide`_ website. + +Hardware +******** + +The TLSR9518A SoC integrates a powerful 32-bit RISC-V MCU, DSP, AI Engine, 2.4 GHz ISM Radio, 256 +KB SRAM (128 KB of Data Local Memory and 128 KB of Instruction Local Memory), external Flash memory, +stereo audio codec, 14 bit AUX ADC, analog and digital Microphone input, PWM, flexible IO interfaces, +and other peripheral blocks required for advanced IoT, hearable, and wearable devices. + +.. figure:: img/tlsr9518_block_diagram.jpg + :align: center + :alt: TLSR9518ADK80D_SOC + +The TLSR9518ADK80D default board configuration provides the following hardware components: + +- RF conducted antenna +- 1 MB External Flash memory with reset button +- Chip reset button +- Mini USB interface +- 4-wire JTAG +- 4 LEDs, Key matrix up to 4 keys +- 2 line-in function (Dual Analog microphone supported when switching jumper from microphone path) +- Dual Digital microphone +- Stereo line-out + +Supported Features +================== + +The Zephyr TLSR9518ADK80D board configuration supports the following hardware features: + ++----------------+------------+------------------------------+ +| Interface | Controller | Driver/Component | ++================+============+==============================+ +| PLIC | on-chip | interrupt_controller | ++----------------+------------+------------------------------+ +| RISC-V Machine | on-chip | timer | +| Timer (32 KHz) | | | ++----------------+------------+------------------------------+ +| PINCTRL | on-chip | pinctrl | ++----------------+------------+------------------------------+ +| GPIO | on-chip | gpio | ++----------------+------------+------------------------------+ +| UART | on-chip | serial | ++----------------+------------+------------------------------+ +| PWM | on-chip | pwm | ++----------------+------------+------------------------------+ +| TRNG | on-chip | entropy | ++----------------+------------+------------------------------+ +| FLASH (MSPI) | on-chip | flash | ++----------------+------------+------------------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154, OpenThread | ++----------------+------------+------------------------------+ +| SPI (Master) | on-chip | spi | ++----------------+------------+------------------------------+ +| I2C (Master) | on-chip | i2c | ++----------------+------------+------------------------------+ +| ADC | on-chip | adc | ++----------------+------------+------------------------------+ + +.. note:: + To support "button" example project PC3-KEY3 (J20-19, J20-20) jumper needs to be removed and KEY3 (J20-19) should be connected to VDD3_DCDC (J51-13) externally. + + For the rest example projects use the default jumpers configuration. + +Other hardware features and example projects are not supported yet. + +Limitations +----------- + +- Maximum 3 GPIO pins could be configured to generate interrupts simultaneously. All pins must be related to different ports and use different IRQ numbers. +- DMA mode is not supported by I2C, SPI and Serial Port. +- UART hardware flow control is not implemented. +- SPI Slave mode is not implemented. +- I2C Slave mode is not implemented. + +Default configuration and IOs +============================= + +System Clock +------------ + +The TLSR9518ADK80D board is configured to use the 24 MHz external crystal oscillator +with the on-chip PLL/DIV generating the 48 MHz system clock. +The following values also could be assigned to the system clock in the board DTS file +:zephyr_file:`boards/telink/tlsr9518adk80d/tlsr9518adk80d.dts`: + +- 16000000 +- 24000000 +- 32000000 +- 48000000 +- 64000000 +- 96000000 + +.. code-block:: + + &cpu0 { + clock-frequency = <48000000>; + }; + +PINs Configuration +------------------ + +The TLSR9518A SoC has five GPIO controllers (PORT_A to PORT_E), but only two are +currently enabled (PORT_B for LEDs control and PORT_C for buttons) in the board DTS file: + +- LED0 (blue): PB4, LED1 (green): PB5, LED2 (white): PB6, LED3 (red): PB7 +- Key Matrix SW0: PC2_PC3, SW1: PC2_PC1, SW2: PC0_PC3, SW3: PC0_PC1 + +Peripheral's pins on the SoC are mapped to the following GPIO pins in the +:zephyr_file:`boards/telink/tlsr9518adk80d/tlsr9518adk80d.dts` file: + +- UART0 TX: PB2, RX: PB3 +- UART1 TX: PC6, RX: PC7 +- PWM Channel 0: PB4 +- PSPI CS0: PC4, CLK: PC5, MISO: PC6, MOSI: PC7 +- HSPI CS0: PA1, CLK: PA2, MISO: PA3, MOSI: PA4 +- I2C SCL: PE1, SDA: PE3 + +Serial Port +----------- + +The TLSR9518A SoC has 2 UARTs. The Zephyr console output is assigned to UART0. +The default settings are 115200 8N1. + +Programming and debugging +************************* + +Building +======== + +.. important:: + + These instructions assume you've set up a development environment as + described in the :ref:`getting_started`. + +To build applications using the default RISC-V toolchain from Zephyr SDK, just run the west build command. +Here is an example for the "hello_world" application. + +.. code-block:: console + + # From the root of the zephyr repository + west build -b tlsr9518adk80d samples/hello_world + +To use `Telink RISC-V Linux Toolchain`_, ``ZEPHYR_TOOLCHAIN_VARIANT`` and ``CROSS_COMPILE`` variables need to be set. +In addition ``CONFIG_FPU=y`` must be selected in :zephyr_file:`boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig` file since this +toolchain is compatible only with the float point unit usage. + +.. code-block:: console + + # Set Zephyr toolchain variant to cross-compile + export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + # Specify the Telink RISC-V Toolchain location + export CROSS_COMPILE=~/toolchains/nds32le-elf-mculib-v5f/bin/riscv32-elf- + # From the root of the zephyr repository + west build -b tlsr9518adk80d samples/hello_world + +`Telink RISC-V Linux Toolchain`_ is available on the `Burning and Debugging Tools for TLSR9 Series in Linux`_ page. + +Open a serial terminal with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flash the board, reset and observe the following messages on the selected +serial port: + +.. code-block:: console + + *** Booting Zephyr OS version 2.5.0 *** + Hello World! tlsr9518adk80d + + +Flashing +======== + +To flash the TLSR9518ADK80D board see the sources below: + +- `Burning and Debugging Tools for all Series`_ +- `Burning and Debugging Tools for TLSR9 Series`_ +- `Burning and Debugging Tools for TLSR9 Series in Linux`_ + +It is also possible to use the west flash command, but additional steps are required to set it up: + +- Download `Telink RISC-V Linux Toolchain`_. The toolchain contains tools for the board flashing as well. +- Since the ICEman tool is created for the 32-bit OS version it is necessary to install additional packages in case of the 64-bit OS version. + +.. code-block:: console + + sudo dpkg --add-architecture i386 + sudo apt-get update + sudo apt-get install -y libc6:i386 libncurses5:i386 libstdc++6:i386 + +- Run the "ICEman.sh" script. + +.. code-block:: console + + # From the root of the {path to the Telink RISC-V Linux Toolchain}/ice repository + sudo ./ICEman.sh + +- Now you should be able to run the west flash command with the toolchain path specified (TELINK_TOOLCHAIN_PATH). + +.. code-block:: console + + west flash --telink-tools-path=$TELINK_TOOLCHAIN_PATH + +- You can also run the west flash command without toolchain path specification if add SPI_burn and ICEman to PATH. + +.. code-block:: console + + export PATH=$TELINK_TOOLCHAIN_PATH/flash/bin:"$PATH" + export PATH=$TELINK_TOOLCHAIN_PATH/ice:"$PATH" + +Debugging +========= + +This port supports UART debug and OpenOCD+GDB. The `west debug` command also supported. You may run +it in a simple way, like: + +.. code-block:: console + + west debug + +Or with additional arguments, like: + +.. code-block:: console + + west debug --gdb-port= --gdb-ex= + +Example: + +.. code-block:: console + + west debug --gdb-port=1111 --gdb-ex="-ex monitor reset halt -ex b main -ex continue" + +References +********** + +.. target-notes:: + +.. _Telink TLSR951x series chipset: https://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/ +.. _Telink B91 Generic Starter Kit Hardware Guide: https://wiki.telink-semi.cn/wiki/Hardware/B91_Generic_Starter_Kit_Hardware_Guide/ +.. _Telink RISC-V Linux Toolchain: https://wiki.telink-semi.cn/tools_and_sdk/Tools/IDE/telink_riscv_linux_toolchain.zip +.. _Burning and Debugging Tools for all Series: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/Burning-and-Debugging-Tools-for-all-Series/ +.. _Burning and Debugging Tools for TLSR9 Series: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/Burning-and-Debugging-Tools-for-TLSR9-Series/ +.. _Burning and Debugging Tools for TLSR9 Series in Linux: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/BDT_for_TLSR9_Series_in_Linux/ diff --git a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d-pinctrl.dtsi b/boards/telink/tlsr9518adk80d/tlsr9518adk80d-pinctrl.dtsi similarity index 100% rename from boards/riscv/tlsr9518adk80d/tlsr9518adk80d-pinctrl.dtsi rename to boards/telink/tlsr9518adk80d/tlsr9518adk80d-pinctrl.dtsi diff --git a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts b/boards/telink/tlsr9518adk80d/tlsr9518adk80d.dts similarity index 100% rename from boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts rename to boards/telink/tlsr9518adk80d/tlsr9518adk80d.dts diff --git a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.yaml b/boards/telink/tlsr9518adk80d/tlsr9518adk80d.yaml similarity index 100% rename from boards/riscv/tlsr9518adk80d/tlsr9518adk80d.yaml rename to boards/telink/tlsr9518adk80d/tlsr9518adk80d.yaml diff --git a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig b/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig similarity index 75% rename from boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig rename to boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig index c4cfdfea718..881ec1fdbef 100644 --- a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig +++ b/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2021 Telink Semiconductor # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_TELINK_TLSR951X=y -CONFIG_SOC_TELINK_TLSR9518=y -CONFIG_BOARD_TLSR9518ADK80D=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_HEAP_MEM_POOL_SIZE=4096 diff --git a/boards/ti/cc1352p1_launchxl/CMakeLists.txt b/boards/ti/cc1352p1_launchxl/CMakeLists.txt new file mode 100644 index 00000000000..cdf4f19c873 --- /dev/null +++ b/boards/ti/cc1352p1_launchxl/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board_antenna.c) diff --git a/boards/ti/cc1352p1_launchxl/Kconfig b/boards/ti/cc1352p1_launchxl/Kconfig new file mode 100644 index 00000000000..6981f6fdf8b --- /dev/null +++ b/boards/ti/cc1352p1_launchxl/Kconfig @@ -0,0 +1,16 @@ +# TI CC1352R LaunchXL board + +# Copyright (c) 2021 Florin Stancu +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CC1352P1_LAUNCHXL + +config BOARD_ANTENNA_INIT_PRIO + int "Board antenna switch initialization priority" + default 70 + help + Set the priority for board init, must be greater than + KERNEL_INIT_PRIORITY_DEVICE but smaller than + IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO. + +endif # BOARD_CC1352P1_LAUNCHXL diff --git a/boards/ti/cc1352p1_launchxl/Kconfig.cc1352p1_launchxl b/boards/ti/cc1352p1_launchxl/Kconfig.cc1352p1_launchxl new file mode 100644 index 00000000000..3701bf6e19e --- /dev/null +++ b/boards/ti/cc1352p1_launchxl/Kconfig.cc1352p1_launchxl @@ -0,0 +1,7 @@ +# TI CC1352R LaunchXL board + +# Copyright (c) 2021 Florin Stancu +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC1352P1_LAUNCHXL + select SOC_CC1352P diff --git a/boards/arm/cc1352p1_launchxl/board.cmake b/boards/ti/cc1352p1_launchxl/board.cmake similarity index 100% rename from boards/arm/cc1352p1_launchxl/board.cmake rename to boards/ti/cc1352p1_launchxl/board.cmake diff --git a/boards/ti/cc1352p1_launchxl/board.yml b/boards/ti/cc1352p1_launchxl/board.yml new file mode 100644 index 00000000000..5d9b234947d --- /dev/null +++ b/boards/ti/cc1352p1_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: cc1352p1_launchxl + vendor: ti + socs: + - name: cc1352p diff --git a/boards/arm/cc1352p1_launchxl/board_antenna.c b/boards/ti/cc1352p1_launchxl/board_antenna.c similarity index 100% rename from boards/arm/cc1352p1_launchxl/board_antenna.c rename to boards/ti/cc1352p1_launchxl/board_antenna.c diff --git a/boards/arm/cc1352p1_launchxl/cc1352p1_launchxl-pinctrl.dtsi b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl-pinctrl.dtsi similarity index 100% rename from boards/arm/cc1352p1_launchxl/cc1352p1_launchxl-pinctrl.dtsi rename to boards/ti/cc1352p1_launchxl/cc1352p1_launchxl-pinctrl.dtsi diff --git a/boards/arm/cc1352p1_launchxl/cc1352p1_launchxl.dts b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.dts similarity index 100% rename from boards/arm/cc1352p1_launchxl/cc1352p1_launchxl.dts rename to boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.dts diff --git a/boards/arm/cc1352p1_launchxl/cc1352p1_launchxl.yaml b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.yaml similarity index 100% rename from boards/arm/cc1352p1_launchxl/cc1352p1_launchxl.yaml rename to boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.yaml diff --git a/boards/arm/cc1352p1_launchxl/cc1352p1_launchxl_defconfig b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl_defconfig similarity index 85% rename from boards/arm/cc1352p1_launchxl/cc1352p1_launchxl_defconfig rename to boards/ti/cc1352p1_launchxl/cc1352p1_launchxl_defconfig index 45a87b265cc..42ca455ed33 100644 --- a/boards/arm/cc1352p1_launchxl/cc1352p1_launchxl_defconfig +++ b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_CC13X2_CC26X2=y -CONFIG_SOC_CC1352P=y -CONFIG_BOARD_CC1352P1_LAUNCHXL=y CONFIG_BUILD_OUTPUT_HEX=y # custom callback for the antenna switch CONFIG_CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS=y diff --git a/boards/arm/cc1352p1_launchxl/doc/img/cc1352p1_launchxl.jpg b/boards/ti/cc1352p1_launchxl/doc/img/cc1352p1_launchxl.jpg similarity index 100% rename from boards/arm/cc1352p1_launchxl/doc/img/cc1352p1_launchxl.jpg rename to boards/ti/cc1352p1_launchxl/doc/img/cc1352p1_launchxl.jpg diff --git a/boards/arm/cc1352p1_launchxl/doc/index.rst b/boards/ti/cc1352p1_launchxl/doc/index.rst similarity index 100% rename from boards/arm/cc1352p1_launchxl/doc/index.rst rename to boards/ti/cc1352p1_launchxl/doc/index.rst diff --git a/boards/arm/cc1352p1_launchxl/dts/bindings/skyworks,sky13317.yaml b/boards/ti/cc1352p1_launchxl/dts/bindings/skyworks,sky13317.yaml similarity index 100% rename from boards/arm/cc1352p1_launchxl/dts/bindings/skyworks,sky13317.yaml rename to boards/ti/cc1352p1_launchxl/dts/bindings/skyworks,sky13317.yaml diff --git a/boards/arm/cc1352p1_launchxl/support/openocd.cfg b/boards/ti/cc1352p1_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/cc1352p1_launchxl/support/openocd.cfg rename to boards/ti/cc1352p1_launchxl/support/openocd.cfg diff --git a/boards/ti/cc1352r1_launchxl/Kconfig.cc1352r1_launchxl b/boards/ti/cc1352r1_launchxl/Kconfig.cc1352r1_launchxl new file mode 100644 index 00000000000..609bde5814f --- /dev/null +++ b/boards/ti/cc1352r1_launchxl/Kconfig.cc1352r1_launchxl @@ -0,0 +1,7 @@ +# TI CC1352R LaunchXL board + +# Copyright (c) 2019 Brett Witherspoon +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC1352R1_LAUNCHXL + select SOC_CC1352R diff --git a/boards/arm/cc1352r1_launchxl/board.cmake b/boards/ti/cc1352r1_launchxl/board.cmake similarity index 100% rename from boards/arm/cc1352r1_launchxl/board.cmake rename to boards/ti/cc1352r1_launchxl/board.cmake diff --git a/boards/ti/cc1352r1_launchxl/board.yml b/boards/ti/cc1352r1_launchxl/board.yml new file mode 100644 index 00000000000..a96d6d89a10 --- /dev/null +++ b/boards/ti/cc1352r1_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: cc1352r1_launchxl + vendor: ti + socs: + - name: cc1352r diff --git a/boards/arm/cc1352r1_launchxl/boosterpack_connector.dtsi b/boards/ti/cc1352r1_launchxl/boosterpack_connector.dtsi similarity index 100% rename from boards/arm/cc1352r1_launchxl/boosterpack_connector.dtsi rename to boards/ti/cc1352r1_launchxl/boosterpack_connector.dtsi diff --git a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl-pinctrl.dtsi b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl-pinctrl.dtsi similarity index 100% rename from boards/arm/cc1352r1_launchxl/cc1352r1_launchxl-pinctrl.dtsi rename to boards/ti/cc1352r1_launchxl/cc1352r1_launchxl-pinctrl.dtsi diff --git a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.dts b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.dts similarity index 100% rename from boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.dts rename to boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.dts diff --git a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.yaml b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.yaml similarity index 100% rename from boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.yaml rename to boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.yaml diff --git a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl_defconfig b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl_defconfig similarity index 82% rename from boards/arm/cc1352r1_launchxl/cc1352r1_launchxl_defconfig rename to boards/ti/cc1352r1_launchxl/cc1352r1_launchxl_defconfig index 30e755d99f1..872843de16d 100644 --- a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl_defconfig +++ b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_CC13X2_CC26X2=y -CONFIG_SOC_CC1352R=y -CONFIG_BOARD_CC1352R1_LAUNCHXL=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE=y diff --git a/boards/arm/cc1352r1_launchxl/doc/img/cc1352r1_launchxl.jpg b/boards/ti/cc1352r1_launchxl/doc/img/cc1352r1_launchxl.jpg similarity index 100% rename from boards/arm/cc1352r1_launchxl/doc/img/cc1352r1_launchxl.jpg rename to boards/ti/cc1352r1_launchxl/doc/img/cc1352r1_launchxl.jpg diff --git a/boards/arm/cc1352r1_launchxl/doc/index.rst b/boards/ti/cc1352r1_launchxl/doc/index.rst similarity index 100% rename from boards/arm/cc1352r1_launchxl/doc/index.rst rename to boards/ti/cc1352r1_launchxl/doc/index.rst diff --git a/boards/arm/cc1352r1_launchxl/support/openocd.cfg b/boards/ti/cc1352r1_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/cc1352r1_launchxl/support/openocd.cfg rename to boards/ti/cc1352r1_launchxl/support/openocd.cfg diff --git a/boards/ti/cc1352r_sensortag/Kconfig.cc1352r_sensortag b/boards/ti/cc1352r_sensortag/Kconfig.cc1352r_sensortag new file mode 100644 index 00000000000..49506bd20ba --- /dev/null +++ b/boards/ti/cc1352r_sensortag/Kconfig.cc1352r_sensortag @@ -0,0 +1,8 @@ +# TI CC1352R SensorTag board + +# Copyright (c) 2019 Brett Witherspoon +# Copyright (c) 2020 Friedt Professional Engineering Services, Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC1352R_SENSORTAG + select SOC_CC1352R diff --git a/boards/ti/cc1352r_sensortag/Kconfig.defconfig b/boards/ti/cc1352r_sensortag/Kconfig.defconfig new file mode 100644 index 00000000000..4396ce0fbd3 --- /dev/null +++ b/boards/ti/cc1352r_sensortag/Kconfig.defconfig @@ -0,0 +1,12 @@ +# TI CC1352R SensorTag board + +# Copyright (c) 2019 Brett Witherspoon +# Copyright (c) 2020 Friedt Professional Engineering Services, Inc +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CC1352R_SENSORTAG + +config SPI + default SENSOR + +endif # BOARD_CC1352R_SENSORTAG diff --git a/boards/arm/cc1352r_sensortag/board.cmake b/boards/ti/cc1352r_sensortag/board.cmake similarity index 100% rename from boards/arm/cc1352r_sensortag/board.cmake rename to boards/ti/cc1352r_sensortag/board.cmake diff --git a/boards/ti/cc1352r_sensortag/board.yml b/boards/ti/cc1352r_sensortag/board.yml new file mode 100644 index 00000000000..b359f530fa2 --- /dev/null +++ b/boards/ti/cc1352r_sensortag/board.yml @@ -0,0 +1,5 @@ +board: + name: cc1352r_sensortag + vendor: ti + socs: + - name: cc1352r diff --git a/boards/arm/cc1352r_sensortag/cc1352r_sensortag-pinctrl.dtsi b/boards/ti/cc1352r_sensortag/cc1352r_sensortag-pinctrl.dtsi similarity index 100% rename from boards/arm/cc1352r_sensortag/cc1352r_sensortag-pinctrl.dtsi rename to boards/ti/cc1352r_sensortag/cc1352r_sensortag-pinctrl.dtsi diff --git a/boards/arm/cc1352r_sensortag/cc1352r_sensortag.dts b/boards/ti/cc1352r_sensortag/cc1352r_sensortag.dts similarity index 100% rename from boards/arm/cc1352r_sensortag/cc1352r_sensortag.dts rename to boards/ti/cc1352r_sensortag/cc1352r_sensortag.dts diff --git a/boards/arm/cc1352r_sensortag/cc1352r_sensortag.yaml b/boards/ti/cc1352r_sensortag/cc1352r_sensortag.yaml similarity index 100% rename from boards/arm/cc1352r_sensortag/cc1352r_sensortag.yaml rename to boards/ti/cc1352r_sensortag/cc1352r_sensortag.yaml diff --git a/boards/arm/cc1352r_sensortag/cc1352r_sensortag_defconfig b/boards/ti/cc1352r_sensortag/cc1352r_sensortag_defconfig similarity index 84% rename from boards/arm/cc1352r_sensortag/cc1352r_sensortag_defconfig rename to boards/ti/cc1352r_sensortag/cc1352r_sensortag_defconfig index 6345d158496..2cddbd5af73 100644 --- a/boards/arm/cc1352r_sensortag/cc1352r_sensortag_defconfig +++ b/boards/ti/cc1352r_sensortag/cc1352r_sensortag_defconfig @@ -5,10 +5,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_CC13X2_CC26X2=y -CONFIG_SOC_CC1352R=y -CONFIG_BOARD_CC1352R_SENSORTAG=y - CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE=y CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE=y CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN=15 diff --git a/boards/arm/cc1352r_sensortag/doc/img/cc1352r_sensortag.jpg b/boards/ti/cc1352r_sensortag/doc/img/cc1352r_sensortag.jpg similarity index 100% rename from boards/arm/cc1352r_sensortag/doc/img/cc1352r_sensortag.jpg rename to boards/ti/cc1352r_sensortag/doc/img/cc1352r_sensortag.jpg diff --git a/boards/arm/cc1352r_sensortag/doc/img/launchpad-lpstk-debug.jpg b/boards/ti/cc1352r_sensortag/doc/img/launchpad-lpstk-debug.jpg similarity index 100% rename from boards/arm/cc1352r_sensortag/doc/img/launchpad-lpstk-debug.jpg rename to boards/ti/cc1352r_sensortag/doc/img/launchpad-lpstk-debug.jpg diff --git a/boards/arm/cc1352r_sensortag/doc/index.rst b/boards/ti/cc1352r_sensortag/doc/index.rst similarity index 100% rename from boards/arm/cc1352r_sensortag/doc/index.rst rename to boards/ti/cc1352r_sensortag/doc/index.rst diff --git a/boards/arm/cc1352r_sensortag/support/openocd.cfg b/boards/ti/cc1352r_sensortag/support/openocd.cfg similarity index 100% rename from boards/arm/cc1352r_sensortag/support/openocd.cfg rename to boards/ti/cc1352r_sensortag/support/openocd.cfg diff --git a/boards/ti/cc26x2r1_launchxl/Kconfig.cc26x2r1_launchxl b/boards/ti/cc26x2r1_launchxl/Kconfig.cc26x2r1_launchxl new file mode 100644 index 00000000000..6ad560d1fef --- /dev/null +++ b/boards/ti/cc26x2r1_launchxl/Kconfig.cc26x2r1_launchxl @@ -0,0 +1,7 @@ +# TI CC26x2R1 LaunchXL board + +# Copyright (c) 2019 Brett Witherspoon +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC26X2R1_LAUNCHXL + select SOC_CC2652R diff --git a/boards/arm/cc26x2r1_launchxl/board.cmake b/boards/ti/cc26x2r1_launchxl/board.cmake similarity index 100% rename from boards/arm/cc26x2r1_launchxl/board.cmake rename to boards/ti/cc26x2r1_launchxl/board.cmake diff --git a/boards/ti/cc26x2r1_launchxl/board.yml b/boards/ti/cc26x2r1_launchxl/board.yml new file mode 100644 index 00000000000..3361b2ccff7 --- /dev/null +++ b/boards/ti/cc26x2r1_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: cc26x2r1_launchxl + vendor: ti + socs: + - name: cc2652r diff --git a/boards/arm/cc26x2r1_launchxl/boosterpack_connector.dtsi b/boards/ti/cc26x2r1_launchxl/boosterpack_connector.dtsi similarity index 100% rename from boards/arm/cc26x2r1_launchxl/boosterpack_connector.dtsi rename to boards/ti/cc26x2r1_launchxl/boosterpack_connector.dtsi diff --git a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi similarity index 100% rename from boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi rename to boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi diff --git a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.dts b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.dts similarity index 100% rename from boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.dts rename to boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.dts diff --git a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml similarity index 100% rename from boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml rename to boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml diff --git a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig similarity index 82% rename from boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig rename to boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig index 0906e953e16..d10e7a152e5 100644 --- a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig +++ b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_CC13X2_CC26X2=y -CONFIG_SOC_CC2652R=y -CONFIG_BOARD_CC26X2R1_LAUNCHXL=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE=y diff --git a/boards/arm/cc26x2r1_launchxl/doc/img/cc26x2r1_launchxl.jpg b/boards/ti/cc26x2r1_launchxl/doc/img/cc26x2r1_launchxl.jpg similarity index 100% rename from boards/arm/cc26x2r1_launchxl/doc/img/cc26x2r1_launchxl.jpg rename to boards/ti/cc26x2r1_launchxl/doc/img/cc26x2r1_launchxl.jpg diff --git a/boards/arm/cc26x2r1_launchxl/doc/index.rst b/boards/ti/cc26x2r1_launchxl/doc/index.rst similarity index 100% rename from boards/arm/cc26x2r1_launchxl/doc/index.rst rename to boards/ti/cc26x2r1_launchxl/doc/index.rst diff --git a/boards/arm/cc26x2r1_launchxl/support/openocd.cfg b/boards/ti/cc26x2r1_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/cc26x2r1_launchxl/support/openocd.cfg rename to boards/ti/cc26x2r1_launchxl/support/openocd.cfg diff --git a/boards/ti/cc3220sf_launchxl/CMakeLists.txt b/boards/ti/cc3220sf_launchxl/CMakeLists.txt new file mode 100644 index 00000000000..8bbc4cf2f34 --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2022 Dhruva Gole + +zephyr_library() +zephyr_library_sources(dbghdr.c) diff --git a/boards/ti/cc3220sf_launchxl/Kconfig.cc3220sf_launchxl b/boards/ti/cc3220sf_launchxl/Kconfig.cc3220sf_launchxl new file mode 100644 index 00000000000..36564cdd16f --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/Kconfig.cc3220sf_launchxl @@ -0,0 +1,6 @@ +# TI SimpleLink CC3220SF LaunchXL Board +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2022 Dhruva Gole + +config BOARD_CC3220SF_LAUNCHXL + select SOC_CC3220SF diff --git a/boards/ti/cc3220sf_launchxl/board.cmake b/boards/ti/cc3220sf_launchxl/board.cmake new file mode 100644 index 00000000000..9f0a0bef65e --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2022 Dhruva Gole + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/ti/cc3220sf_launchxl/board.yml b/boards/ti/cc3220sf_launchxl/board.yml new file mode 100644 index 00000000000..f902db4d392 --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: cc3220sf_launchxl + vendor: ti + socs: + - name: cc3220sf diff --git a/boards/arm/cc3220sf_launchxl/boosterpack_connector.dtsi b/boards/ti/cc3220sf_launchxl/boosterpack_connector.dtsi similarity index 100% rename from boards/arm/cc3220sf_launchxl/boosterpack_connector.dtsi rename to boards/ti/cc3220sf_launchxl/boosterpack_connector.dtsi diff --git a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl-pinctrl.dtsi b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl-pinctrl.dtsi similarity index 100% rename from boards/arm/cc3220sf_launchxl/cc3220sf_launchxl-pinctrl.dtsi rename to boards/ti/cc3220sf_launchxl/cc3220sf_launchxl-pinctrl.dtsi diff --git a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.dts b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.dts similarity index 100% rename from boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.dts rename to boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.dts diff --git a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.yaml b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.yaml similarity index 100% rename from boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.yaml rename to boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.yaml diff --git a/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl_defconfig b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl_defconfig new file mode 100644 index 00000000000..8f107f24a0b --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2022 Dhruva Gole + +CONFIG_BUILD_OUTPUT_HEX=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/cc3220sf_launchxl/dbghdr.c b/boards/ti/cc3220sf_launchxl/dbghdr.c similarity index 100% rename from boards/arm/cc3220sf_launchxl/dbghdr.c rename to boards/ti/cc3220sf_launchxl/dbghdr.c diff --git a/boards/ti/cc3220sf_launchxl/doc/index.rst b/boards/ti/cc3220sf_launchxl/doc/index.rst new file mode 100644 index 00000000000..dd58c203daa --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/doc/index.rst @@ -0,0 +1,297 @@ +.. _cc3220sf_launchxl: + +CC3220SF LaunchXL +################# + +Overview +******** +The SimpleLink Wi-Fi CC3220SF LaunchPad development kit (CC3220SF-LAUNCHXL) +highlights CC3220SF, a single-chip wireless microcontroller (MCU) with +1MB internal flash, 4MB external serial flash, 256KB of RAM and enhanced +security features. + +See the `TI CC3220 Product Page`_ for details. + +Features: +========= + +* Two separate execution environments: a user application dedicated ARM + Cortex-M4 MCU and a network processor MCU to run all Wi-Fi and + internet logical layers +* 40-pin LaunchPad standard leveraging the BoosterPack ecosystem +* On-board accelerometer and temperature sensor +* Two buttons and three LEDs for user interaction +* UART through USB to PC +* BoosterPack plug-in module for adding graphical displays, audio + codecs, antenna selection, environmental sensing, and more +* Power from USB for the LaunchPad and optional external BoosterPack +* XDS110-based JTAG emulation with serial port for flash programming + +Details on the CC3220SF LaunchXL development board can be found in the +`CC3220SF LaunchPad Dev Kit Hardware User's Guide`_. + +Hardware +******** + +The CC3220SF SoC has two MCUs: + +#. Applications MCU - an ARM |reg| Cortex |reg|-M4 Core at 80 MHz, with 256Kb RAM, + and access to external serial 4MB flash with bootloader and peripheral + drivers in ROM. + +#. Network Coprocessor (NWP) - a dedicated ARM MCU, which completely + offloads Wi-Fi and internet protocols from the application MCU. + +Complete details of the CC3220SF SoC can be found in the `CC3220 TRM`_. + +Supported Features +================== + +Zephyr has been ported to the Applications MCU, with basic peripheral +driver support. + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| UART | on-chip | serial port-interrupt | ++-----------+------------+-----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-----------------------+ +| SPI_0 | on-chip | Wi-Fi host driver | ++-----------+------------+-----------------------+ + +.. note:: + + For consistency with TI SimpleLink SDK and BoosterPack examples, + the I2C driver defaults to I2C_BITRATE_FAST mode (400 kHz) bus speed + on bootup. + +The accelerometer, temperature sensors, or other peripherals +accessible through the BoosterPack, are not currently supported. + +Programming and Debugging +************************* + +TI officially supports development on the CC3220SF using the TI +`CC3220 SDK`_ on Windows and Linux using TI tools: Code Composer +Studio for debugging and `UniFlash`_ for flashing. + +For Windows developers, see the `CC3220 Getting Started Guide`_ for +instructions on installation of tools, and how to flash the board using +UniFlash. + +Note that zephyr.bin produced by the Zephyr SDK may not load via +UniFlash tool. If encountering difficulties, use the zephyr.elf +file and openocd instead (see below). + +The following instructions are geared towards Linux developers who +prefer command line tools to an IDE. + +Before flashing and debugging the board, there are a few one-time board +setup steps to follow. + +Prerequisites: +============== + +#. Download and install the latest version of `UniFlash`_. +#. Jumper SOP[2..0] (J15) to [010], and connect the USB cable to the PC. + + This should result in a new device "Texas Instruments XDS110 Embed + with CMSIS-DAP" appearing at /dev/ttyACM1 and /dev/ttyACM0. + +#. Update the service pack, and place the board in "Development Mode". + + Setting "Development Mode" enables the JTAG interface, necessary + for subsequent use of OpenOCD and updating XDS110 firmware. + + Follow the instructions in Section 2.4 "Download the Application", + in the `CC3220 Getting Started Guide`_, except for steps 5 and 6 in + Section 2.4.1 which select an MCU image. + +#. Ensure the XDS-110 emulation firmware is updated. + + Download and install the latest `XDS-110 emulation package`_. + + Follow these `xds110 firmware update directions + `_ + + Note that the emulation package install may place the xdsdfu utility + in ``/ccs_base/common/uscif/xds110/``. + +#. Switch Jumper SOP[2..0] (J15) back to [001]. + + Remove power from the board (disconnect USB cable) before switching jumpers. + +#. Install OpenOCD + + You can obtain OpenOCD by following these + :ref:`installing the latest Zephyr SDK instructions `. + + After the installation, add the directory containing the OpenOCD executable + to your environment's PATH variable. For example, use this command in Linux: + + .. code-block:: console + + export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH + + If you had previously installed TI OpenOCD, you can simply switch to use + the one in the Zephyr SDK. If for some reason you wish to continue to use + your TI OpenOCD installation, you can set the OPENOCD and + OPENOCD_DEFAULT_PATH variables in + :zephyr_file:`boards/ti/cc3220sf_launchxl/board.cmake` to point the build + to the paths of the OpenOCD binary and its scripts, before + including the common openocd.board.cmake file: + + .. code-block:: cmake + + set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) + set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +#. Ensure CONFIG_XIP=y (default) is set. + + This locates the program into flash, and sets CONFIG_CC3220SF_DEBUG=y, + which prepends a debug header enabling the flash to persist over + subsequent reboots, bypassing the bootloader flash signature + verification. + + See Section 21.10 "Debugging Flash User Application Using JTAG" of the + `CC3220 TRM`_ for details on the secure flash boot process. + + +Once the above prerequisites are met, applications for the ``_cc3220sf_launchxl`` +board can be built, flashed, and debugged with openocd and gdb per the Zephyr +Application Development Primer (see :ref:`build_an_application` and +:ref:`application_run`). + +Flashing +======== + +To build and flash an application, execute the following commands for : + +.. zephyr-app-commands:: + :zephyr-app: + :board: cc3220sf_launchxl + :goals: flash + +This will load the image into flash. + +To see program output from UART0, connect a separate terminal window: + +.. code-block:: console + + % screen /dev/ttyACM0 115200 8N1 + +Then press the reset button (SW1) on the board to run the program. + +When using OpenOCD from Zephyr SDK to flash the device, you may notice +the program hangs when starting the network processor on the device, if the +program uses it. There is a known issue with how that version of OpenOCD +resets the network processor. You would need to manually hit the reset button +on the board to properly reset the device after flashing. + +Debugging +========= + +To debug a previously flashed image, after resetting the board, use the 'debug' +build target: + +.. zephyr-app-commands:: + :zephyr-app: + :board: cc3220sf_launchxl + :maybe-skip-config: + :goals: debug + + +Wi-Fi Support +************* + +The SimpleLink Host Driver, imported from the SimpleLink SDK, has been ported +to Zephyr, and communicates over a dedicated SPI to the network co-processor. +It is available as a Zephyr Wi-Fi device driver in +:zephyr_file:`drivers/wifi/simplelink`. + +Usage: +====== + +Set :kconfig:option:`CONFIG_WIFI_SIMPLELINK` and :kconfig:option:`CONFIG_WIFI` to ``y`` +to enable Wi-Fi. +See :zephyr_file:`samples/net/wifi/boards/cc3220sf_launchxl.conf`. + +Provisioning: +============= + +SimpleLink provides a few rather sophisticated Wi-Fi provisioning methods. +To keep it simple for Zephyr development and demos, the SimpleLink +"Fast Connect" policy is enabled, with one-shot scanning. +This enables the cc3220sf_launchxl to automatically reconnect to the last +good known access point (AP), without having to restart a scan, and +re-specify the SSID and password. + +To connect to an AP, first run the Zephyr Wi-Fi shell sample application, +and connect to a known AP with SSID and password. + +See :zephyr:code-sample:`wifi-shell` + +Once the connection succeeds, the network co-processor keeps the AP identity in +its persistent memory. Newly loaded Wi-Fi applications then need not explicitly +execute any Wi-Fi scan or connect operations, until the need to change to a new AP. + +Secure Socket Offload +********************* + +The SimpleLink Wi-Fi driver provides socket operations to the Zephyr socket +offload point, enabling Zephyr BSD socket API calls to be directed to the +SimpleLink Wi-Fi driver, by setting :kconfig:option:`CONFIG_NET_SOCKETS_OFFLOAD` +to ``y``. + +Secure socket (TLS) communication is handled as part of the socket APIs, +and enabled by: + +- setting both :kconfig:option:`CONFIG_NET_SOCKETS_SOCKOPT_TLS` + and :kconfig:option:`CONFIG_TLS_CREDENTIAL_FILENAMES` to ``y``, +- using the TI Uniflash tool to program the required certificates and + keys to the secure flash filesystem, and enabling the TI Trusted + Root-Certificate Catalog. + +See :zephyr:code-sample:`sockets-http-get` and +:zephyr_file:`samples/net/sockets/http_get/boards/cc3220sf_launchxl.conf` for an +example. + +See the document `Simplelink Wi-Fi Certificates Handling`_ for details on +using the TI UniFlash tool for certificate programming. + +References +********** + +CC32xx Wiki: + http://processors.wiki.ti.com/index.php/CC31xx_%26_CC32xx + +.. _TI CC3220 Product Page: + http://www.ti.com/product/cc3220 + +.. _CC3220 TRM: + http://www.ti.com/lit/pdf/swru465 + +.. _CC3220 Programmer's Guide: + http://www.ti.com/lit/pdf/swru464 + +.. _CC3220 Getting Started Guide: + http://www.ti.com/lit/pdf/swru461 + +.. _UniFlash: + http://processors.wiki.ti.com/index.php/Category:CCS_UniFlash + +.. _CC3220 SDK: + http://www.ti.com/tool/download/SIMPLELINK-CC3220-SDK + +.. _CC3220SF LaunchPad Dev Kit Hardware User's Guide: + http://www.ti.com/lit/pdf/swru463 + +.. _XDS-110 emulation package: + http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download + +.. _Simplelink Wi-Fi Certificates Handling: + http://www.ti.com/lit/pdf/swpu332 diff --git a/boards/arm/cc3220sf_launchxl/support/openocd.cfg b/boards/ti/cc3220sf_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/cc3220sf_launchxl/support/openocd.cfg rename to boards/ti/cc3220sf_launchxl/support/openocd.cfg diff --git a/boards/arm/cc3220sf_launchxl/CMakeLists.txt b/boards/ti/cc3235sf_launchxl/CMakeLists.txt similarity index 100% rename from boards/arm/cc3220sf_launchxl/CMakeLists.txt rename to boards/ti/cc3235sf_launchxl/CMakeLists.txt diff --git a/boards/ti/cc3235sf_launchxl/Kconfig.cc3235sf_launchxl b/boards/ti/cc3235sf_launchxl/Kconfig.cc3235sf_launchxl new file mode 100644 index 00000000000..c4a04b2d293 --- /dev/null +++ b/boards/ti/cc3235sf_launchxl/Kconfig.cc3235sf_launchxl @@ -0,0 +1,6 @@ +# TI SimpleLink CC3235SF LaunchXL Board +# Copyright (c) 2019, Texas Instruments Incorporated +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC3235SF_LAUNCHXL + select SOC_CC3235SF diff --git a/boards/arm/cc3235sf_launchxl/board.cmake b/boards/ti/cc3235sf_launchxl/board.cmake similarity index 100% rename from boards/arm/cc3235sf_launchxl/board.cmake rename to boards/ti/cc3235sf_launchxl/board.cmake diff --git a/boards/ti/cc3235sf_launchxl/board.yml b/boards/ti/cc3235sf_launchxl/board.yml new file mode 100644 index 00000000000..6cf8104545a --- /dev/null +++ b/boards/ti/cc3235sf_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: cc3235sf_launchxl + vendor: ti + socs: + - name: cc3235sf diff --git a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl-pinctrl.dtsi b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl-pinctrl.dtsi similarity index 100% rename from boards/arm/cc3235sf_launchxl/cc3235sf_launchxl-pinctrl.dtsi rename to boards/ti/cc3235sf_launchxl/cc3235sf_launchxl-pinctrl.dtsi diff --git a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.dts b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.dts similarity index 100% rename from boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.dts rename to boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.dts diff --git a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.yaml b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.yaml similarity index 100% rename from boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.yaml rename to boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.yaml diff --git a/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl_defconfig b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl_defconfig new file mode 100644 index 00000000000..acbb196bc4e --- /dev/null +++ b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/cc3235sf_launchxl/dbghdr.c b/boards/ti/cc3235sf_launchxl/dbghdr.c similarity index 100% rename from boards/arm/cc3235sf_launchxl/dbghdr.c rename to boards/ti/cc3235sf_launchxl/dbghdr.c diff --git a/boards/ti/cc3235sf_launchxl/doc/index.rst b/boards/ti/cc3235sf_launchxl/doc/index.rst new file mode 100644 index 00000000000..cf865b89028 --- /dev/null +++ b/boards/ti/cc3235sf_launchxl/doc/index.rst @@ -0,0 +1,297 @@ +.. _cc3235sf_launchxl: + +CC3235SF LaunchXL +################# + +Overview +******** +The SimpleLink Wi-Fi CC3235SF LaunchPad development kit (CC3235SF-LAUNCHXL) +highlights CC3235SF, a single-chip wireless microcontroller (MCU) with +1MB internal flash, 4MB external serial flash, 256KB of RAM, and enhanced +security features. It supports 802.11 a/b/g/n, both 2.4 GHz and 5 GHz. + +See the `TI CC3235 Product Page`_ for details. + +Features: +========= + +* Two separate execution environments: a user application dedicated ARM + Cortex-M4 MCU and a network processor MCU to run all Wi-Fi and + internet logical layers +* 40-pin LaunchPad standard leveraging the BoosterPack ecosystem +* On-board accelerometer and temperature sensor +* Two buttons and a RGB LED for user interaction +* UART through USB to PC +* BoosterPack plug-in module for adding graphical displays, audio + codecs, antenna selection, environmental sensing, and more +* Power from USB for the LaunchPad and optional external BoosterPack +* XDS110-based JTAG emulation with serial port for flash programming + +Details on the CC3235SF LaunchXL development board can be found in the +`CC3235SF LaunchPad Dev Kit Hardware User's Guide`_. + +Hardware +******** + +The CC3235SF SoC has two MCUs: + +#. Applications MCU - an ARM |reg| Cortex |reg|-M4 Core at 80 MHz, with 256Kb RAM, + and access to external serial 4MB flash with bootloader and peripheral + drivers in ROM. + +#. Network Coprocessor (NWP) - a dedicated ARM MCU, which completely + offloads Wi-Fi and internet protocols from the application MCU. + +Complete details of the CC3235SF SoC can be found in the `CC3235 TRM`_. + +Supported Features +================== + +Zephyr has been ported to the Applications MCU, with basic peripheral +driver support. + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| UART | on-chip | serial port-interrupt | ++-----------+------------+-----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-----------------------+ +| SPI_0 | on-chip | Wi-Fi host driver | ++-----------+------------+-----------------------+ + +.. note:: + + For consistency with TI SimpleLink SDK and BoosterPack examples, + the I2C driver defaults to I2C_BITRATE_FAST mode (400 kHz) bus speed + on bootup. + +The accelerometer, temperature sensors, or other peripherals +accessible through the BoosterPack, are not currently supported. + +Programming and Debugging +************************* + +TI officially supports development on the CC3235SF using the TI +`CC32xx SDK`_ on Windows and Linux using TI tools: Code Composer +Studio for debugging and `UniFlash`_ for flashing. + +For Windows developers, see the `CC32xx Quick Start Guide`_ for +instructions on installation of tools, and how to flash the board using +UniFlash. + +Note that ``zephyr.bin`` produced by the Zephyr SDK may not load via +UniFlash tool. If encountering difficulties, use the ``zephyr.elf`` +file and openocd instead (see below). + +The following instructions are geared towards Linux developers who +prefer command line tools to an IDE. + +Before flashing and debugging the board, there are a few one-time board +setup steps to follow. + +Prerequisites: +============== + +#. Download and install the latest version of `UniFlash`_. +#. Jumper SOP[2..0] (J15) to [010], and connect the USB cable to the PC. + + This should result in a new device "Texas Instruments XDS110 Embed + with CMSIS-DAP" appearing at /dev/ttyACM1 and /dev/ttyACM0. + +#. Update the service pack, and place the board in "Development Mode". + + Setting "Development Mode" enables the JTAG interface, necessary + for subsequent use of OpenOCD and updating XDS110 firmware. + + Follow the instructions in Section 2.4 "Download the Application", + in the `CC32xx Quick Start Guide`_, except for steps 5 and 6 in + Section 2.4.1 which select an MCU image. + +#. Ensure the XDS-110 emulation firmware is updated. + + Download and install the latest `XDS-110 emulation package`_. + + Follow these `xds110 firmware update directions + `_ + + Note that the emulation package install may place the xdsdfu utility + in ``/ccs_base/common/uscif/xds110/``. + +#. Switch Jumper SOP[2..0] (J15) back to [001]. + + Remove power from the board (disconnect USB cable) before switching jumpers. + +#. Install OpenOCD + + You can obtain OpenOCD by following these + :ref:`installing the latest Zephyr SDK instructions `. + + After the installation, add the directory containing the OpenOCD executable + to your environment's PATH variable. For example, use this command in Linux: + + .. code-block:: console + + export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH + + If you had previously installed TI OpenOCD, you can simply switch to use + the one in the Zephyr SDK. If for some reason you wish to continue to use + your TI OpenOCD installation, you can set the OPENOCD and + OPENOCD_DEFAULT_PATH variables in + :zephyr_file:`boards/ti/cc3220sf_launchxl/board.cmake` to point the build + to the paths of the OpenOCD binary and its scripts, before + including the common openocd.board.cmake file: + + .. code-block:: cmake + + set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) + set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +#. Ensure CONFIG_XIP=y (default) is set. + + This locates the program into flash, and sets CONFIG_CC3235SF_DEBUG=y, + which prepends a debug header enabling the flash to persist over + subsequent reboots, bypassing the bootloader flash signature + verification. + + See Section 21.10 "Debugging Flash User Application Using JTAG" of the + `CC3235 TRM`_ for details on the secure flash boot process. + + +Once the above prerequisites are met, applications for the ``_cc3235sf_launchxl`` +board can be built, flashed, and debugged with openocd and gdb per the Zephyr +Application Development Primer (see :ref:`build_an_application` and +:ref:`application_run`). + +Flashing +======== + +To build and flash an application, execute the following commands for : + +.. zephyr-app-commands:: + :zephyr-app: + :board: cc3235sf_launchxl + :goals: flash + +This will load the image into flash. + +To see program output from UART0, connect a separate terminal window: + +.. code-block:: console + + % screen /dev/ttyACM0 115200 8N1 + +Then press the reset button (SW1) on the board to run the program. + +When using OpenOCD from Zephyr SDK to flash the device, you may notice +the program hangs when starting the network processor on the device, if the +program uses it. There is a known issue with how that version of OpenOCD +resets the network processor. You would need to manually hit the reset button +on the board to properly reset the device after flashing. + +Debugging +========= + +To debug a previously flashed image, after resetting the board, use the 'debug' +build target: + +.. zephyr-app-commands:: + :zephyr-app: + :board: cc3235sf_launchxl + :maybe-skip-config: + :goals: debug + + +Wi-Fi Support +************* + +The SimpleLink Host Driver, imported from the SimpleLink SDK, has been ported +to Zephyr, and communicates over a dedicated SPI to the network co-processor. +It is available as a Zephyr Wi-Fi device driver in +:zephyr_file:`drivers/wifi/simplelink`. + +Usage: +====== + +Set :kconfig:option:`CONFIG_WIFI_SIMPLELINK` and :kconfig:option:`CONFIG_WIFI` to ``y`` +to enable Wi-Fi. +See :zephyr_file:`samples/net/wifi/boards/cc3235sf_launchxl.conf`. + +Provisioning: +============= + +SimpleLink provides a few rather sophisticated Wi-Fi provisioning methods. +To keep it simple for Zephyr development and demos, the SimpleLink +"Fast Connect" policy is enabled, with one-shot scanning. +This enables the cc3235sf_launchxl to automatically reconnect to the last +good known access point (AP), without having to restart a scan, and +re-specify the SSID and password. + +To connect to an AP, first run the Zephyr Wi-Fi shell sample application, +and connect to a known AP with SSID and password. + +See :zephyr:code-sample:`wifi-shell` + +Once the connection succeeds, the network co-processor keeps the AP identity in +its persistent memory. Newly loaded Wi-Fi applications then need not explicitly +execute any Wi-Fi scan or connect operations, until the need to change to a new AP. + +Secure Socket Offload +********************* + +The SimpleLink Wi-Fi driver provides socket operations to the Zephyr socket +offload point, enabling Zephyr BSD socket API calls to be directed to the +SimpleLink Wi-Fi driver, by setting :kconfig:option:`CONFIG_NET_SOCKETS_OFFLOAD` +to ``y``. + +Secure socket (TLS) communication is handled as part of the socket APIs, +and enabled by: + +- setting both :kconfig:option:`CONFIG_NET_SOCKETS_SOCKOPT_TLS` + and :kconfig:option:`CONFIG_TLS_CREDENTIAL_FILENAMES` to ``y``, +- using the TI Uniflash tool to program the required certificates and + keys to the secure flash filesystem, and enabling the TI Trusted + Root-Certificate Catalog. + +See :zephyr:code-sample:`sockets-http-get` and +:zephyr_file:`samples/net/sockets/http_get/boards/cc3235sf_launchxl.conf` for an +example. + +See the document `Simplelink Wi-Fi Certificates Handling`_ for details on +using the TI UniFlash tool for certificate programming. + +References +********** + +TI SimpleLink MCUs: + http://www.ti.com/microcontrollers/simplelink-mcus/overview.html + +.. _TI CC3235 Product Page: + http://www.ti.com/product/cc3235SF + +.. _CC3235 TRM: + http://www.ti.com/lit/pdf/swru543 + +.. _CC3x20/CC3x35 SimpleLink Wi-Fi and IoT Network Processor Programmer's Guide: + http://www.ti.com/lit/pdf/swru455 + +.. _CC32xx Quick Start Guide: + http://dev.ti.com/tirex/content/simplelink_cc32xx_sdk_2_40_01_01/docs/simplelink_mcu_sdk/Quick_Start_Guide.html + +.. _UniFlash: + http://processors.wiki.ti.com/index.php/Category:CCS_UniFlash + +.. _CC32xx SDK: + http://www.ti.com/tool/download/SIMPLELINK-CC32xx-SDK/2.40.01.01 + +.. _CC3235SF LaunchPad Dev Kit Hardware User's Guide: + http://www.ti.com/lit/pdf/swru539 + +.. _XDS-110 emulation package: + http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download + +.. _Simplelink Wi-Fi Certificates Handling: + http://www.ti.com/lit/pdf/swpu332 diff --git a/boards/arm/cc3235sf_launchxl/support/openocd.cfg b/boards/ti/cc3235sf_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/cc3235sf_launchxl/support/openocd.cfg rename to boards/ti/cc3235sf_launchxl/support/openocd.cfg diff --git a/boards/ti/index.rst b/boards/ti/index.rst new file mode 100644 index 00000000000..0d78a6e4827 --- /dev/null +++ b/boards/ti/index.rst @@ -0,0 +1,10 @@ +.. _boards-ti: + +Texas Instruments +################# + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/ti/msp_exp432p401r_launchxl/Kconfig.msp_exp432p401r_launchxl b/boards/ti/msp_exp432p401r_launchxl/Kconfig.msp_exp432p401r_launchxl new file mode 100644 index 00000000000..270cc9be561 --- /dev/null +++ b/boards/ti/msp_exp432p401r_launchxl/Kconfig.msp_exp432p401r_launchxl @@ -0,0 +1,6 @@ +# TI SimpleLink MSP-EXP432P401R LaunchXL Development Board +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Linaro + +config BOARD_MSP_EXP432P401R_LAUNCHXL + select SOC_MSP432P401R diff --git a/boards/ti/msp_exp432p401r_launchxl/board.cmake b/boards/ti/msp_exp432p401r_launchxl/board.cmake new file mode 100644 index 00000000000..ca103200fd0 --- /dev/null +++ b/boards/ti/msp_exp432p401r_launchxl/board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Linaro + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/ti/msp_exp432p401r_launchxl/board.yml b/boards/ti/msp_exp432p401r_launchxl/board.yml new file mode 100644 index 00000000000..1e9ed0b7ed3 --- /dev/null +++ b/boards/ti/msp_exp432p401r_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: msp_exp432p401r_launchxl + vendor: ti + socs: + - name: msp432p401r diff --git a/boards/arm/msp_exp432p401r_launchxl/doc/img/msp_exp432p401r_launchxl.jpg b/boards/ti/msp_exp432p401r_launchxl/doc/img/msp_exp432p401r_launchxl.jpg similarity index 100% rename from boards/arm/msp_exp432p401r_launchxl/doc/img/msp_exp432p401r_launchxl.jpg rename to boards/ti/msp_exp432p401r_launchxl/doc/img/msp_exp432p401r_launchxl.jpg diff --git a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst new file mode 100644 index 00000000000..e24d8140a25 --- /dev/null +++ b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst @@ -0,0 +1,152 @@ +.. _msp_exp432p401r_launchxl: + +MSP-EXP432P401R LaunchXL +######################## + +Overview +******** + +The SimpleLink MSP‐EXP432P401R LaunchPad development kit is an easy-to-use evaluation +module for the SimpleLink MSP432P401R microcontroller. It contains everything needed to start +developing on the SimpleLink MSP432 low-power + performance ARM |reg| 32-bit Cortex |reg|-M4F +microcontroller (MCU). + +.. figure:: img/msp_exp432p401r_launchxl.jpg + :align: center + :alt: MSP-EXP432P401R LaunchXL development board + +Features: +========= + +* Low-power ARM Cortex-M4F MSP432P401R +* 40-pin LaunchPad development kit standard that leverages the BoosterPack plug-in module ecosystem +* XDS110-ET, an open-source onboard debug probe featuring EnergyTrace+ technology and application + UART +* Two buttons and two LEDs for user interaction +* Backchannel UART through USB to PC + +Details on the MSP-EXP432P401R LaunchXL development board can be found in the +MSP-EXP432P401R LaunchXL User's Guide. + +Supported Features +================== + +* The on-board 32-kHz crystal allows for lower LPM3 sleep currents and a higher-precision clock source than the + default internal 32-kHz REFOCLK. Therefore, the presence of the crystal allows the full range of low- + power modes to be used. +* The on-board 48-MHz crystal allows the device to run at its maximum operating speed for MCLK and HSMCLK. + +The MSP-EXP432P401R LaunchXL development board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port | ++-----------+------------+-----------------------+ + +More details about the supported peripherals are available in MSP432P4XX TRM +Other hardware features are not currently supported by the Zephyr kernel. + +Building and Flashing +********************* + +Prerequisites: +============== + +#. Ensure the XDS-110 emulation firmware is updated. + + Download and install the latest `XDS-110 emulation package`_. + + Follow these `xds110 firmware update directions + `_ + + Note that the emulation package install may place the xdsdfu utility + in ``/ccs_base/common/uscif/xds110/``. + +#. Install OpenOCD + + You can obtain OpenOCD by following these + :ref:`installing the latest Zephyr SDK instructions `. + + After the installation, add the directory containing the OpenOCD executable + to your environment's PATH variable. For example, use this command in Linux: + + .. code-block:: console + + export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH + + If you had previously installed TI OpenOCD, you can simply switch to use + the one in the Zephyr SDK. If for some reason you wish to continue to use + your TI OpenOCD installation, you can set the OPENOCD and + OPENOCD_DEFAULT_PATH variables in + :zephyr_file:`boards/ti/msp_exp432p401r_launchxl/board.cmake` to point the build + to the paths of the OpenOCD binary and its scripts, before + including the common openocd.board.cmake file: + + .. code-block:: cmake + + set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) + set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +Flashing +======== + +Follow the :ref:`getting_started` instructions for Zephyr application +development. + +For example, to build and flash the :ref:`hello_world` application for the +MSP-EXP432P401R LaunchXL: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: msp_exp432p401r_launchxl + :goals: flash + +This will load the image into flash. + +To see program output from UART0, connect a separate terminal window: + +.. code-block:: console + + % screen /dev/ttyACM0 115200 8N1 + +Then press the reset button (S3) on the board to run the program. + +Debugging +========= + +To debug a previously flashed image, after resetting the board, use the 'debug' +build target: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: msp_exp432p401r_launchxl + :maybe-skip-config: + :goals: debug + +References +********** + +TI MSP432 Wiki: + https://en.wikipedia.org/wiki/TI_MSP432 + +TI MSP432P401R Product Page: + http://www.ti.com/product/msp432p401r + +TI MSP432 SDK: + http://www.ti.com/tool/SIMPLELINK-MSP432-SDK + +.. _UniFlash: + http://processors.wiki.ti.com/index.php/UniFlash_v4_Quick_Guide#Command_Line_Interface + +.. _CCS IDE: + http://www.ti.com/tool/ccstudio + +.. _XDS-110 emulation package: + http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download diff --git a/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts similarity index 93% rename from boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts rename to boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts index c9172dc0db9..d7af9e0e5cb 100644 --- a/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts +++ b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright (c) 2017 Linaro */ /dts-v1/; diff --git a/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml similarity index 100% rename from boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml rename to boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml diff --git a/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig new file mode 100644 index 00000000000..b1a19a007d0 --- /dev/null +++ b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Linaro + +CONFIG_BUILD_OUTPUT_HEX=y + +# Floating point options +CONFIG_FPU=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/msp_exp432p401r_launchxl/support/openocd.cfg b/boards/ti/msp_exp432p401r_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/msp_exp432p401r_launchxl/support/openocd.cfg rename to boards/ti/msp_exp432p401r_launchxl/support/openocd.cfg diff --git a/boards/ti/sk_am62/Kconfig.sk_am62 b/boards/ti/sk_am62/Kconfig.sk_am62 new file mode 100644 index 00000000000..d7e83cba87a --- /dev/null +++ b/boards/ti/sk_am62/Kconfig.sk_am62 @@ -0,0 +1,11 @@ +# Texas Instruments Sitara AM62x-SK-M4 EVM +# +# Copyright (c) 2023 Texas Instruments Incorporated +# Copyright (c) 2023 L Lakshmanan +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SK_AM62_AM6234_M4 + select SOC_AM6234_M4 + help + TI AM62x M4 Starter Kit (SK) Evaluation Module (EVM) diff --git a/boards/ti/sk_am62/board.yml b/boards/ti/sk_am62/board.yml new file mode 100644 index 00000000000..da6e946fe02 --- /dev/null +++ b/boards/ti/sk_am62/board.yml @@ -0,0 +1,5 @@ +board: + name: sk_am62 + vendor: ti + socs: + - name: am6234 diff --git a/boards/arm/am62x_m4/doc/img/sk_am62_angled.webp b/boards/ti/sk_am62/doc/img/sk_am62_angled.webp similarity index 100% rename from boards/arm/am62x_m4/doc/img/sk_am62_angled.webp rename to boards/ti/sk_am62/doc/img/sk_am62_angled.webp diff --git a/boards/ti/sk_am62/doc/index.rst b/boards/ti/sk_am62/doc/index.rst new file mode 100644 index 00000000000..0a93edd1367 --- /dev/null +++ b/boards/ti/sk_am62/doc/index.rst @@ -0,0 +1,138 @@ +.. _sk_am62: + +SK-AM62 M4F Core +################ + +Overview +******** + +The SK-AM62 board configuration is used by Zephyr applications that run on +the TI AM62x platform. The board configuration provides support for the ARM +Cortex-M4F MCU core and the following features: + +- Nested Vector Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) + +The board configuration also enables support for the semihosting debugging console. + +See the `TI AM62X Product Page`_ for details. + +.. figure:: img/sk_am62_angled.webp + :align: center + :alt: TI SK-AM62 EVM + + Texas Instruments SK-AM62 EVM + +Hardware +******** +The SK-AM62 EVM features the AM62x SoC, which is composed of a quad Cortex-A53 +cluster and a single Cortex-M4 core in the MCU domain. Zephyr is ported to run on +the M4F core and the following listed hardware specifications are used: + +- Low-power ARM Cortex-M4F +- Memory + + - 256KB of SRAM + - 2GB of DDR4 + +- Debug + + - XDS110 based JTAG + +Supported Features +================== + +The sk_am62 configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 400 MHz. + +DDR RAM +------- + +The board has 2GB of DDR RAM available. This board configuration +allocates Zephyr 4kB of RAM (only for resource table: 0x9CC00000 to 0x9CC00400). + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +MCU domain UART (MCU_UART0). + +SD Card +******* + +Download TI's official `WIC`_ and flash the WIC file with an etching software +onto an SD-card. This will boot Linux on the A53 application cores of the EVM. +These cores will then load the zephyr binary on the M4 core using remoteproc. + +The default configuration can be found in +:zephyr_file:`boards/ti/sk_am62/sk_am62_am6234_m4_defconfig` + +Flashing +******** + +The board can using remoteproc, and uses the OpenAMP resource table to accomplish this. + +The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. + +To test the M4F core, we build the `hello_world` sample with the following command. + +.. code-block:: console + + # From the root of the Zephyr repository + west build -p -b sk_am62/am6234/m4 samples/hello_world + +This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. + +We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. + +.. code-block:: console + + # Mount the SD card at sdcard for example + sudo mount /dev/sdX sdcard + # copy the elf to the /lib/firmware directory + sudo cp --remove-destination zephyr.elf sdcard/lib/firmware/am62-mcu-m4f0_0-fw + +The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot. + +To allow the board to boot using the SD card, set the boot pins to the SD Card boot mode. Refer to `EVM Setup Page`_. + +After changing the boot mode, the board should go through the boot sequence on powering up. +The binary will run and print Hello world to the MCU_UART0 port. + +References +********** + +AM62x SK EVM TRM: + https://www.ti.com/lit/ug/spruiv7/spruiv7.pdf + +.. _TI AM62X Product Page: + https://www.ti.com/product/AM625 + +.. _WIC: + https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-PvdSyIiioq/08.06.00.42/tisdk-default-image-am62xx-evm.wic.xz + +.. _AM62x SK EVM TRM: + https://www.ti.com/lit/ug/spruiv7/spruiv7.pdf + +.. _EVM Setup Page: + https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/08_06_00_18/exports/docs/api_guide_am62x/EVM_SETUP_PAGE.html diff --git a/boards/arm/am62x_m4/am62x_m4_sk.dts b/boards/ti/sk_am62/sk_am62_am6234_m4.dts similarity index 100% rename from boards/arm/am62x_m4/am62x_m4_sk.dts rename to boards/ti/sk_am62/sk_am62_am6234_m4.dts diff --git a/boards/ti/sk_am62/sk_am62_am6234_m4.yaml b/boards/ti/sk_am62/sk_am62_am6234_m4.yaml new file mode 100644 index 00000000000..d257c6dc98d --- /dev/null +++ b/boards/ti/sk_am62/sk_am62_am6234_m4.yaml @@ -0,0 +1,8 @@ +identifier: sk_am62/am6234/m4 +name: TI AM62X M4 Starter Kit (SK) +type: mcu +arch: arm +toolchain: + - zephyr +ram: 192 +vendor: ti diff --git a/boards/ti/sk_am62/sk_am62_am6234_m4_defconfig b/boards/ti/sk_am62/sk_am62_am6234_m4_defconfig new file mode 100644 index 00000000000..8ed54c6554e --- /dev/null +++ b/boards/ti/sk_am62/sk_am62_am6234_m4_defconfig @@ -0,0 +1,22 @@ +# Texas Instruments Sitara AM62x-SK-M4 EVM +# +# Copyright (c) 2023 Texas Instruments Incorporated +# Copyright (c) 2023 L Lakshmanan +# +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_CORTEX_M_SYSTICK=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Enable Pinctrl +CONFIG_PINCTRL=y + +# Serial Driver +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/toradex/colibri_imx7d/Kconfig.colibri_imx7d b/boards/toradex/colibri_imx7d/Kconfig.colibri_imx7d new file mode 100644 index 00000000000..d17d33cfdf8 --- /dev/null +++ b/boards/toradex/colibri_imx7d/Kconfig.colibri_imx7d @@ -0,0 +1,6 @@ +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_COLIBRI_IMX7D + select SOC_PART_NUMBER_MCIMX7D5EVM10SC + select SOC_MCIMX7D_M4 if BOARD_COLIBRI_IMX7D_MCIMX7D_M4 diff --git a/boards/toradex/colibri_imx7d/Kconfig.defconfig b/boards/toradex/colibri_imx7d/Kconfig.defconfig new file mode 100644 index 00000000000..4f108737fd2 --- /dev/null +++ b/boards/toradex/colibri_imx7d/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Colibri iMX7D M4 board + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_COLIBRI_IMX7D_MCIMX7D_M4 + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + + +endif # BOARD_COLIBRI_IMX7D_MCIMX7D_M4 diff --git a/boards/toradex/colibri_imx7d/board.yml b/boards/toradex/colibri_imx7d/board.yml new file mode 100644 index 00000000000..7a6ffe62495 --- /dev/null +++ b/boards/toradex/colibri_imx7d/board.yml @@ -0,0 +1,5 @@ +board: + name: colibri_imx7d + vendor: toradex + socs: + - name: mcimx7d diff --git a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4-pinctrl.dtsi b/boards/toradex/colibri_imx7d/colibri_imx7d-pinctrl.dtsi similarity index 100% rename from boards/arm/colibri_imx7d_m4/colibri_imx7d_m4-pinctrl.dtsi rename to boards/toradex/colibri_imx7d/colibri_imx7d-pinctrl.dtsi diff --git a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.dts b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.dts new file mode 100644 index 00000000000..c59fac1a0a4 --- /dev/null +++ b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.dts @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2017,2019 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "colibri_imx7d-pinctrl.dtsi" +#include + +/ { + model = "TORADEX Colibri IMX7D board"; + compatible = "nxp,mcimx7d_m4"; + + aliases { + led0 = &green_led; + sw0 = &user_switch_1; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_0 { + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + label = "User LED1"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_switch_1: user_sw_1 { + gpios = <&gpio2 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "User SW1"; + zephyr,code = ; + }; + }; +}; + +&uart2 { + status = "okay"; + current-speed = <115200>; + modem-mode = <64>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; +}; + +&pwm3 { + pinctrl-0 = <&pwm3_default>; + pinctrl-names = "default"; +}; + +&pwm4 { + pinctrl-0 = <&pwm4_default>; + pinctrl-names = "default"; +}; + +&mub { + status = "okay"; +}; diff --git a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml new file mode 100644 index 00000000000..d28eccc9d2b --- /dev/null +++ b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: colibri_imx7d/mcimx7d/m4 +name: TORADEX Colibri IMX7D +type: mcu +arch: arm +ram: 32 +flash: 32 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - pwm +vendor: nxp diff --git a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig new file mode 100644 index 00000000000..a55e01a9fa7 --- /dev/null +++ b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_PINCTRL=y diff --git a/boards/arm/colibri_imx7d_m4/doc/colibri_imx7d_m4.jpg b/boards/toradex/colibri_imx7d/doc/colibri_imx7d.jpg similarity index 100% rename from boards/arm/colibri_imx7d_m4/doc/colibri_imx7d_m4.jpg rename to boards/toradex/colibri_imx7d/doc/colibri_imx7d.jpg diff --git a/boards/toradex/colibri_imx7d/doc/index.rst b/boards/toradex/colibri_imx7d/doc/index.rst new file mode 100644 index 00000000000..22b356fc1c6 --- /dev/null +++ b/boards/toradex/colibri_imx7d/doc/index.rst @@ -0,0 +1,325 @@ +.. _colibri_imx7d: + +NXP i.MX 7 Computer on Module - Colibri iMX7 +############################################ + +Overview +******** + +The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7 +core and Single Cortex M4 core. +Zephyr was ported to run on the M4 core. In a later release, it will also +communicate with the A7 core (running Linux) via RPmsg. + + +.. image:: colibri_imx7d.jpg + :align: center + :alt: Colibri-iMX7 + +Hardware +******** + +- i.MX7 Single/Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core + +- Memory + + - RAM -> A7: 256MB, 512MB and 1GB + - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) + - Flash -> A7: 4Gb eMMC and 512Mb NAND + +- Display + + - RGB 1920x1080x24bpp + - 4-wire Resistive touch + +- Multimedia + + - 1x Camera Parallel Interface + - 1x Analog Audio Line in (Stereo) + - 1x Analog Audio Mic in (Mono) + - 1x Analog Audio Headphone out (Stereo) + +- Connectivity + + - USB 2.0 OTG (High Speed) + - USB 2.0 host (High Speed) + - 10/100 Mbit/s Ethernet PHY + - 4x I2C + - 4x SPI + - 7x UART + - 1x IrDA + - 20x PWM + - Up to 125 GPIO + - 4x Analog Input (12 Bit) + - 2x SDIO/SD/MMC (8 Bit) + - 2x CAN + +For more information about the i.MX 7 SoC, Colibri iMX7 Computer on Module +and Colibri Evaluation Board, see these references: + +- `i.MX 7 Series Website`_ +- `i.MX 7 Dual Datasheet`_ +- `i.MX 7 Dual Reference Manual`_ +- `Colibri iMX7 Website`_ +- `Colibri iMX7 User Guide`_ +- `Colibri iMX7 Datasheet`_ +- `Colibri Evaluation Board Website`_ +- `Colibri Evaluation Board Datasheet`_ + +Supported Features +================== + +The Colibri iMX7D Computer on Module with Colibri Evaluation Board configuration +supports the following hardware features on the Cortex M4 Core: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The Colibri iMX7D Computer on Module with Colibri Evaluation Board +was tested with the following pinmux controller configuration. + ++---------------+-----------------+---------------------------+ +| Board Name | SoC Name | Usage | ++===============+=================+===========================+ +| UART_B RXD | UART2_TXD | UART Console | ++---------------+-----------------+---------------------------+ +| UART_B TXD | UART2_RXD | UART Console | ++---------------+-----------------+---------------------------+ +| SODIMM_135 | GPIO1_IO02 | LED0 | ++---------------+-----------------+---------------------------+ +| SODIMM_133 | GPIO2_IO26 | SW0 | ++---------------+-----------------+---------------------------+ +| SODIMM_194 | I2C4_SDA | I2C_SDA | ++---------------+-----------------+---------------------------+ +| SODIMM_196 | I2C4_SCL | I2C_SCL | ++---------------+-----------------+---------------------------+ +| SODIMM_59 | PWM1/GPIO1_IO08 | PWM | ++---------------+-----------------+---------------------------+ + +System Clock +============ + +The M4 Core is configured to run at a 200 MHz clock speed. + +Serial Port +=========== + +The iMX7D SoC has seven UARTs. The number 2 is configured for the console and +the remaining are not used/tested. + +Programming and Debugging +************************* + +The Colibri iMX7D doesn't have QSPI flash for the M4 and it needs to be started by +the A7 core. The A7 core is responsible to load the M4 binary application into the +RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get +the M4 out of reset. +The A7 can perform these steps at bootloader level or after the Linux system has +booted. + +The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: + ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=======================+========================+=======================+======================+ +| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ + + +References +========== + +- `i.MX 7 Dual Reference Manual`_ from page 190 (section 2.1.2 and 2.1.3) +- `Toradex Wiki`_ + + +At compilation time you have to choose which RAM will be used. This configuration is +done in the file :zephyr_file:`boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.dts` +with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" +properties. The available configurations are: + +.. code-block:: none + + "zephyr,flash" + - &ddr_code + - &tcml_code + - &ocram_code + - &ocram_s_code + - &ocram_pxp_code + - &ocram_epdc_code + + "zephyr,sram" + - &ddr_sys + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + - &ocram_pxp_sys + - &ocram_epdc_sys + + +Below you will find the instructions to load and run Zephyr on M4 from A7 using u-boot. + +Copy the compiled zephyr.bin to the first EXT partition of the SD card and plug into the +board. Power it up and stop the u-boot execution. +Set the u-boot environment variables and run the zephyr.bin from the appropriated memory +configured in the Zephyr compilation: + +.. code-block:: console + + setenv bootm4 'ext4load mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' + # TCML + setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' + setenv bootm4tcml 'run m4tcml && run bootm4' + run bootm4tcml + # TCMU + setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' + setenv bootm4tcmu 'run m4tcmu && run bootm4' + run bootm4tcmu + # OCRAM + setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' + setenv bootm4ocram 'run m4ocram && run bootm4' + run bootm4ocram + # OCRAM_S + setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' + setenv bootm4ocrams 'run m4ocrams && run bootm4' + run bootm4ocrams + # DDR + setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' + setenv bootm4ddr 'run m4ddr && run bootm4' + run bootm4ddr + + +Debugging +========= + +Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. + +To run Zephyr Binary using J-Link create the following script in order to +get the Program Counter and Stack Pointer from zephyr.bin. + +get-pc-sp.sh: + +.. code-block:: console + + #!/bin/sh + + firmware=$1 + + pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') + sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') + + echo pc=$pc + echo sp=$sp + + +Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` + +.. code-block:: console + + pc=00900f01 + sp=00905020 + +Plug in the J-Link into the board and PC and run the J-Link command line tool: + +.. code-block:: console + + /usr/bin/JLinkExe -device Cortex-M4 -if JTAG -speed 4000 -autoconnect 1 -jtagconf -1,-1 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript + +The following steps are necessary to run the zephyr.bin: +1. Put the M4 core in reset +2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) +3. Set PC (Program Counter) +4. Set SP (Stack Pointer) +5. Get the M4 core out of reset + +Issue the following commands inside J-Link commander: + +.. code-block:: console + + w4 0x3039000C 0xAC + loadfile zephyr.bin,0x00900000 + w4 0x00180000 00900f01 + w4 0x00180004 00905020 + w4 0x3039000C 0xAA + +With these mechanisms, applications for the ``colibri_imx7d/imx7d/m4`` board +configuration can be built and debugged in the usual way (see +:ref:`build_an_application` and :ref:`application_run` for more details). + +References +========== + +- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ +- `J-Link iMX7D Instructions`_ + +.. _Colibri Evaluation Board Website: + https://www.toradex.com/products/carrier-board/colibri-evaluation-carrier-board + +.. _Colibri Evaluation Board Datasheet: + https://docs.toradex.com/102284-colibri-evaluation-board-datasheet.pdf + +.. _Colibri iMX7 Website: + https://www.toradex.com/computer-on-modules/colibri-arm-family/nxp-freescale-imx7 + +.. _Colibri iMX7 User Guide: + https://developer.toradex.com/products/colibri-imx7 + +.. _Colibri iMX7 Datasheet: + https://docs.toradex.com/103125-colibri-arm-som-imx7-datasheet.pdf + +.. _i.MX 7 Series Website: + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 + +.. _i.MX 7 Dual Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf + +.. _i.MX 7 Dual Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX7DRM + +.. _J-Link Tools: + https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack + +.. _NXP iMX7D Connect CortexM4.JLinkScript: + https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript + +.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: + https://www.nxp.com/docs/en/application-note/AN5317.pdf + +.. _J-Link iMX7D Instructions: + https://wiki.segger.com/IMX7D + +.. _Toradex Wiki: + https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/toradex/index.rst b/boards/toradex/index.rst new file mode 100644 index 00000000000..1be6d87105a --- /dev/null +++ b/boards/toradex/index.rst @@ -0,0 +1,10 @@ +.. _boards-toradex: + +Toradex +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/toradex/verdin_imx8mp/Kconfig.defconfig b/boards/toradex/verdin_imx8mp/Kconfig.defconfig new file mode 100644 index 00000000000..76903f1d2e1 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/Kconfig.defconfig @@ -0,0 +1,15 @@ +# VERDIN_IMX8MP board defconfig + +# Copyright (c) 2023 Toradex +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_VERDIN_IMX8MP + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_VERDIN_IMX8MP diff --git a/boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp b/boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp new file mode 100644 index 00000000000..41c84eb3690 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp @@ -0,0 +1,9 @@ +# VERDIN_IMX8MP board + +# Copyright (c) 2023 Toradex +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_VERDIN_IMX8MP + select SOC_MIMX8MP_M7 if BOARD_VERDIN_IMX8MP_MIMX8ML8_M7 || BOARD_VERDIN_IMX8MP_MIMX8ML8_M7_DDR + select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm/verdin_imx8mp_m7/board.cmake b/boards/toradex/verdin_imx8mp/board.cmake similarity index 100% rename from boards/arm/verdin_imx8mp_m7/board.cmake rename to boards/toradex/verdin_imx8mp/board.cmake diff --git a/boards/toradex/verdin_imx8mp/board.yml b/boards/toradex/verdin_imx8mp/board.yml new file mode 100644 index 00000000000..6ffbf4561a2 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/board.yml @@ -0,0 +1,8 @@ +board: + name: verdin_imx8mp + vendor: toradex + socs: + - name: mimx8ml8 + variants: + - name: ddr + cpucluster: m7 diff --git a/boards/toradex/verdin_imx8mp/doc/index.rst b/boards/toradex/verdin_imx8mp/doc/index.rst new file mode 100644 index 00000000000..de7751ff0e6 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/doc/index.rst @@ -0,0 +1,304 @@ +.. _verdin_imx8mp: + +Toradex Verdin iMX8M Plus SoM +############################# + +Overview +******** + +The Verdin iMX8M Plus is a Computer on Module (CoM) developed by Toradex. It is based on the NXP® +i.MX 8M Plus family of processors (or System on Chips - SoCs). + +The Verdin iMX8M Plus family consists of: + ++-------------------------------------------------+-----------------------+ +| CoM | SoC | ++=================================================+=======================+ +| Verdin iMX8M Plus Quad 8GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | ++-------------------------------------------------+-----------------------+ +| Verdin iMX8M Plus Quad 4GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | ++-------------------------------------------------+-----------------------+ +| Verdin iMX8M Plus Quad 4GB IT | i.MX 8M Plus Quad | ++-------------------------------------------------+-----------------------+ +| Verdin iMX8M Plus Quad 2GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | ++-------------------------------------------------+-----------------------+ +| Verdin iMX8M Plus QuadLite 1GB IT | i.MX 8M Plus QuadLite | ++-------------------------------------------------+-----------------------+ + +Quoting NXP: + + The i.MX 8M Plus family focuses on machine learning and vision, advanced multimedia, and + industrial automation with high reliability. It is built to meet the needs of Smart Home, + Building, City and Industry 4.0 applications. + +The Verdin iMX8M Plus integrates a total of 4 Arm Cortex™-A53 CPUs, operating at 1.6 GHz, alongside +a single Arm Cortex™-M7F microcontroller operating at 800 MHz. + +.. figure:: verdin_imx8mp_front.jpg + :align: center + :alt: Toradex Verdin iMX8M Plus + + Toradex Verdin iMX8M Plus (Credit: Toradex) + +Regarding the Cortex-A53 cluster, it employs the ARMv8-A architecture as a mid-range and +energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1 +memory system. Moreover, the cluster incorporates a unified L2 cache that offers supplementary +functions. This cache is housed within a single APR region. Facilitating debugging processes, the +cores support both real-time trace through the ETM system and static debugging via JTAG. +Furthermore, the platform features support for real-time trace capabilities, achieved through ARM's +CoreSight ETM modules, and also enables cross-triggering by utilizing CTI and CTM modules. + +The Arm® Cortex®-M7 microcontroller is indicated for Real-time control, combining high-performance +with a minimal interrupt latency. It stands out for its compatibility with existing Cortex-M profile +processors. The microcontroller employs an efficient in-order super-scalar pipeline, allowing +dual-issued instructions such as load/load and load/store pairs, thanks to its multiple memory +interfaces. These interfaces encompass Tightly-Coupled Memory (TCM), Harvard caches, and an AXI +master interface. The Arm Cortex-M7 Platform boasts features like a 32 KB L1 Instruction Cache, 32 +KB L1 Data Cache, Floating Point Unit (FPU) with FPv5 architecture support, and an Internal Trace +(TRC) mechanism. Furthermore, the chip supports 160 IRQs, and integrates crucial Arm CoreSight +components including ETM and CTI, dedicated to facilitating debug and trace functions. + +Hardware +******** + +- SoC name: NXP® i.MX 8M Plus +- CPU Type: 4x Arm Cortex™-A53 (1.6 GHz) +- Microcontroller: 1x Arm Cortex™-M7F (800 MHz) + +- Memory: + + - RAM -> A53: 1GB, 2GB, 4GB or 8GB + - RAM -> M7: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) + - Flash -> A53: Up to 32GB eMMC + +- Connectivity: + + - USB 3.1: 1x Host / 1x OTG (Gen 1) + - USB 2.0: 1x Host / 1x OTG + - Ethernet Gigabit with TSN (+2nd RGMII) + - Wi-Fi Dual-band 802.11ac 2x2 MU-MIMO + - Bluetooth 5 + - 5x I2C + - 3x SPI + - 1 QSPI + - 4x UART + - Up to 92 GPIO + - 4x Analog Input + - 2x CAN (FlexCAN) + +- Multimedia: + + - Neural Processing Unit (NPU) + - Image Signal Processor (ISP) + - 2D and 3D acceleration + - HDMI, MIPI-DSI and MIPI-CSI interface + +For more information about the Verdin iMX8M Plus and the i.MX 8M Plus SoC refer to these links: + +- `i.MX 8M Plus Applications Processor page`_ +- `Verdin iMX8M Plus homepage`_ +- `Verdin iMX8M Plus developer page`_ +- `Verdin Development Board developer page`_ +- `Verdin iMX8M Plus Datasheet`_ +- `Verdin Development Board Datasheet`_ + +Supported Features +================== + +The Zephyr verdin_imx8mp_m7 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + +- :zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig`, if you choose to use + the ITCM memory. + +- :zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig`, if you choose to use + the DDR memory. + +It is recommended to disable peripherals used by the M7 core on the Linux host. + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +UART +---- + +Zephyr is configured to use the UART4 by default, which is connected to the FTDI USB converter on +most Toradex carrier boards. + +This is also the UART connected to WiFi/BT chip in modules that have the WiFi/BT chip. Therefore, if +UART4 is used, WiFI/BT will not work properly. + +If the WiFi/BT is needed, then another UART should be used for Zephyr (UART1 for example). You can +change the UART by changing the ``zephyr,console`` and ``zephyr,shell-uart`` in the +:zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.dts` or +:zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.dts` file. + ++---------------+-----------------+---------------------------+ +| Board Name | SoC Name | Usage | ++===============+=================+===========================+ +| UART_1 | UART1 | General purpose UART | ++---------------+-----------------+---------------------------+ +| UART_4 | UART4 | Cortex-M4 debug UART | ++---------------+-----------------+---------------------------+ + +GPIO +---- + +All the GPIO banks available are enabled in the :zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. + +System Clock +============ + +The M7 Core is configured to run at a 800 MHz clock speed. + +Serial Port +=========== + +The i.MX8M Plus SoC has four UARTs. UART_4 is configured for the console and the remaining are not +used/tested. + +Programming and Debugging +************************* + +The Verdin iMX8M Plus board doesn't have QSPI flash for the M7, and it needs to be started by the +A53 core. The A53 core is responsible to load the M7 binary application into the RAM, put the M7 in +reset, set the M7 Program Counter and Stack Pointer, and get the M7 out of reset. The A53 can +perform these steps at bootloader level or after the Linux system has booted. + +The M7 can use up to 3 different RAMs (currently, only two configurations are supported: ITCM and +DDR). These are the memory mapping for A53 and M7: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the `i.MX 8M Plus Applications Processor Reference +Manual`_ (section 2.1 to 2.3) + +At compilation time you have to choose which RAM will be used. To facilitate this process, there are +two targets available: + +- ``verdin_imx8mp/mimx8ml8/m7``, which uses the ITCM configuration. +- ``verdin_imx8mp/mimx8ml8/m7/ddr``, which uses the DDR configuration. + + +Starting the Cortex-M7 via U-Boot +================================= + +Load and run Zephyr on M7 from A53 using u-boot by copying the compiled ``zephyr.bin`` to the first +FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot +execution at prompt. + +Load the M7 binary onto the desired memory and start its execution using: + +ITCM +==== + +Loading the binary from an EXT4 partition: + +.. code-block:: shell + + ext4load mmc 2:2 ${loadaddr} //zephyr.bin + cp.b ${loadaddr} 0x7e0000 + bootaux 0x7e0000 + +DDR +=== + +Loading the binary from an EXT4 partition: + +.. code-block:: shell + + ext4load mmc 2:2 ${loadaddr} //zephyr.bin + cp.b ${loadaddr} 0x80000000 + bootaux 0x80000000 + +Debugging +========= + +Toradex Verdin iMX8M Plus SoM can be debugged by connecting an external JLink JTAG debugger to the +X56 debug connector and to the PC, or simply connecting a USB-C to X66 on the Verdin Development +Board. Then, the application can be debugged using the usual way. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: verdin_imx8mp/mimx8ml8/m7/ddr + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.4.0-2300-g03905f7e55d2 *** + Hello World! verdin_imx8mp + +References +========== + +- `How to Load Compiled Binaries into Cortex-M`_ +- `Cortex-M JTAG Debugging`_ +- `NXP website`_ + +.. _NXP website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK + +.. _i.MX 8M Plus Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MPRM + +.. _How to Load Compiled Binaries into Cortex-M: + https://developer.toradex.com/software/real-time/cortex-m/how-to-load-binaries + +.. _Cortex-M JTAG Debugging: + https://developer.toradex.com/software/real-time/cortex-m/cortexm-jtag-debugging/ + +.. _i.MX 8M Plus Applications Processor page: + https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-applications-processors/i-mx-8m-plus-arm-cortex-a53-machine-learning-vision-multimedia-and-industrial-iot:IMX8MPLUS + +.. _Verdin iMX8M Plus homepage: + https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus + +.. _Verdin iMX8M Plus developer page: + https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-imx8m-plus + +.. _Verdin Development Board developer page: + https://developer.toradex.com/hardware/verdin-som-family/carrier-boards/verdin-development-board/ + +.. _Verdin iMX8M Plus Datasheet: + https://docs.toradex.com/110977-verdin_imx8m_plus_v1.1_datasheet.pdf + +.. _Verdin Development Board Datasheet: + https://docs.toradex.com/109463-verdin_development_board_datasheet_v1.1.pdf diff --git a/boards/arm/verdin_imx8mp_m7/doc/verdin_imx8mp_front.jpg b/boards/toradex/verdin_imx8mp/doc/verdin_imx8mp_front.jpg similarity index 100% rename from boards/arm/verdin_imx8mp_m7/doc/verdin_imx8mp_front.jpg rename to boards/toradex/verdin_imx8mp/doc/verdin_imx8mp_front.jpg diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7-pinctrl.dtsi b/boards/toradex/verdin_imx8mp/verdin_imx8mp-pinctrl.dtsi similarity index 100% rename from boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7-pinctrl.dtsi rename to boards/toradex/verdin_imx8mp/verdin_imx8mp-pinctrl.dtsi diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.dts b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.dts new file mode 100644 index 00000000000..ad9b0fa7b69 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.dts @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2023 Toradex + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "verdin_imx8mp-pinctrl.dtsi" +#include + +/ { + model = "Toradex Verdin iMX8M Plus M7"; + compatible = "nxp,mimx8mp_evk"; + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&gpio3 { + status = "okay"; +}; + +&mailbox0 { + status = "okay"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.yaml b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.yaml new file mode 100644 index 00000000000..e4e77056bc0 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2023 Toradex +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: verdin_imx8mp/mimx8ml8/m7 +name: Toradex Verdin iMX8M Plus (ITCM) +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.dts b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.dts new file mode 100644 index 00000000000..43db40248ca --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.dts @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2023 Toradex + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "verdin_imx8mp-pinctrl.dtsi" +#include + +/ { + model = "Toradex Verdin iMX8M Plus M7"; + compatible = "nxp,mimx8mp_evk"; + + chosen { + /* DDR */ + zephyr,flash = &ddr_code; + zephyr,sram = &ddr_sys; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&gpio3 { + status = "okay"; +}; + +&mailbox0 { + status = "okay"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.yaml b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.yaml new file mode 100644 index 00000000000..979dbfa498d --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2023 Toradex +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: verdin_imx8mp/mimx8ml8/m7/ddr +name: Toradex Verdin iMX8M Plus (DDR) +type: mcu +arch: arm +ram: 2048 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig new file mode 100644 index 00000000000..0f2a48bcc79 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2023 Toradex +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_CODE_DDR=y +CONFIG_PINCTRL=y diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig new file mode 100644 index 00000000000..c7f1110e266 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2023 Toradex +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_CODE_ITCM=y +CONFIG_PINCTRL=y diff --git a/boards/u-blox/index.rst b/boards/u-blox/index.rst new file mode 100644 index 00000000000..d1fe5fc4f4b --- /dev/null +++ b/boards/u-blox/index.rst @@ -0,0 +1,10 @@ +.. _boards-u-blox: + +u-blox +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/u-blox/ubx_bmd300eval/Kconfig b/boards/u-blox/ubx_bmd300eval/Kconfig new file mode 100644 index 00000000000..361d81b0fed --- /dev/null +++ b/boards/u-blox/ubx_bmd300eval/Kconfig @@ -0,0 +1,10 @@ +# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_BMD300EVAL diff --git a/boards/u-blox/ubx_bmd300eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd300eval/Kconfig.defconfig new file mode 100644 index 00000000000..8ba8ca2d640 --- /dev/null +++ b/boards/u-blox/ubx_bmd300eval/Kconfig.defconfig @@ -0,0 +1,11 @@ +# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD300EVAL + +config BT_CTLR + default BT + +endif # BOARD_UBX_BMD300EVAL diff --git a/boards/u-blox/ubx_bmd300eval/Kconfig.ubx_bmd300eval b/boards/u-blox/ubx_bmd300eval/Kconfig.ubx_bmd300eval new file mode 100644 index 00000000000..1efa727323b --- /dev/null +++ b/boards/u-blox/ubx_bmd300eval/Kconfig.ubx_bmd300eval @@ -0,0 +1,7 @@ +# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD300EVAL + select SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_bmd300eval_nrf52832/board.cmake b/boards/u-blox/ubx_bmd300eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/board.cmake rename to boards/u-blox/ubx_bmd300eval/board.cmake diff --git a/boards/u-blox/ubx_bmd300eval/board.yml b/boards/u-blox/ubx_bmd300eval/board.yml new file mode 100644 index 00000000000..522c0808eed --- /dev/null +++ b/boards/u-blox/ubx_bmd300eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd300eval + vendor: u-blox + socs: + - name: nrf52832 diff --git a/boards/arm/ubx_bmd300eval_nrf52832/doc/img/BMD-30-33-35-36-EVAL.jpg b/boards/u-blox/ubx_bmd300eval/doc/img/BMD-30-33-35-36-EVAL.jpg similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/doc/img/BMD-30-33-35-36-EVAL.jpg rename to boards/u-blox/ubx_bmd300eval/doc/img/BMD-30-33-35-36-EVAL.jpg diff --git a/boards/arm/ubx_bmd300eval_nrf52832/doc/img/bmd-300-eval_pin_out.jpg b/boards/u-blox/ubx_bmd300eval/doc/img/bmd-300-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/doc/img/bmd-300-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd300eval/doc/img/bmd-300-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd300eval/doc/index.rst b/boards/u-blox/ubx_bmd300eval/doc/index.rst new file mode 100644 index 00000000000..43e8d1d9fe9 --- /dev/null +++ b/boards/u-blox/ubx_bmd300eval/doc/index.rst @@ -0,0 +1,397 @@ +.. _ubx_bmd300eval_nrf52832: + +u-blox EVK-BMD-30/35: BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL +################################################################## + +Overview +******** + +The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL hardware provides +support for the u-blox BMD-300, BMD-301, and BMD-350 Bluetooth 5 +modules, based on the Nordic Semiconductor nRF52832 ARM Cortex-M4F +CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/BMD-30-33-35-36-EVAL.jpg + :align: center + :alt: BMD-300-EVAL + + BMD-300-EVAL (Credit: u-blox AG) + +.. note:: + The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL share the same + pin headers and assignments. The boards are different only in + the module used on the board. The BMD-300 and BMD-301 modules + share the same footprint and differ only in the antenna. The + BMD-350 module utilizes the nRF52832 CIAA WLCSP package. + +More information about the BMD-300-EVAL, BMD-301-EVAL, and +BMD-350-EVAL and the respective modules can be found at the +`u-blox website`_. All of the Nordic Semiconductor examples for +the nRF52 DK (nrf52dk_nrf52832) may be used without modification. + +Hardware +******** + +The BMD-300/301/350 module on the board contains an internal +high-frequency oscillator at 32MHz. There is also a low frequency +(slow) oscillator of 32.768kHz. The module itself does not include +the slow crystal; however, the EVAL boards do. + +.. note:: + When targeting a custom design without a slow crystal, + be sure to modify code to utilize the internal RC + oscillator for the slow clock. + +Supported Features +================== + +The BMD-300/301/350-EVAL configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of +BMD-300/301/350-EVAL hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.17 +* LED2 (red) = P0.18 +* LED3 (green) = P0.19 +* LED4 (green) = P0.20 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.13 +* BUTTON2 = SW2 = P0.14 +* BUTTON3 = SW3 = P0.15 +* BUTTON4 = SW4 = P0.16 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-300-eval_pin_out.jpg + :align: center + :alt: BMD-300-EVAL pin-out + + BMD-300-EVAL pin-out (Credit: u-blox AG) + +.. note:: + The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL share + the same pin headers and assignments. + The BMD-300-EVAL is shown here. + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-300/301/350-EVAL + for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 | ++-------+----------------+ +| 2 | P0.09 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.21 / RESET | ++-------+----------------+ +| 8 | P0.01 / XL2 | ++-------+----------------+ +| 9 | P0.00 / XL1 | ++-------+----------------+ +| 10 | GND | ++-------+----------------+ + + +Arduino Headers +--------------- + + +Power (J5) + ++-------+--------------+---------------------------+ +| PIN # | Signal Name | BMD-300/301/350 Functions | ++=======+==============+===========================+ +| 1 | VSHLD | N/A | ++-------+--------------+---------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+---------------------------+ +| 3 | RESET | P0.21 / RESET | ++-------+--------------+---------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+---------------------------+ +| 5 | V5V | N/A | ++-------+--------------+---------------------------+ +| 6 | GND | N/A | ++-------+--------------+---------------------------+ +| 7 | GND | N/A | ++-------+--------------+---------------------------+ +| 8 | N/C | N/A | ++-------+--------------+---------------------------+ + + +Analog in (J8) + ++-------+--------------+---------------------------+ +| PIN # | Signal Name | BMD-300/301/350 Functions | ++=======+==============+===========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+---------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+---------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+---------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+---------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+---------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+---------------------------+ + + +Digital I/O (J7) + ++-------+--------------+---------------------------+ +| PIN # | Signal Name | BMD-300/301/350 Functions | ++=======+==============+===========================+ +| 1 | D7 | P0.18/TRACEDATA[0]/SWO | ++-------+--------------+---------------------------+ +| 2 | D6 | P0.17 | ++-------+--------------+---------------------------+ +| 3 | D5 | P0.16/TRACEDATA[1] | ++-------+--------------+---------------------------+ +| 4 | D4 | P0.15/TRACEDATA[2] | ++-------+--------------+---------------------------+ +| 5 | D3 | P0.14/TRACEDATA[3] | ++-------+--------------+---------------------------+ +| 6 | D2 | P0.13 | ++-------+--------------+---------------------------+ +| 7 | D1 (TX) | P0.12 | ++-------+--------------+---------------------------+ +| 8 | D0 (RX) | P0.11 | ++-------+--------------+---------------------------+ + + +Digital I/O (J6) + ++-------+--------------+---------------------------+ +| PIN # | Signal Name | BMD-300/301/350 Functions | ++=======+==============+===========================+ +| 1 | SCL | P0.27 | ++-------+--------------+---------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+---------------------------+ +| 3 | AREF | P0.02/AIN0 | ++-------+--------------+---------------------------+ +| 4 | GND | N/A | ++-------+--------------+---------------------------+ +| 5 | D13 (SCK) | P0.25 | ++-------+--------------+---------------------------+ +| 6 | D12 (MISO) | P0.24 | ++-------+--------------+---------------------------+ +| 7 | D11 (MOSI) | P0.23 | ++-------+--------------+---------------------------+ +| 8 | D10 (SS) | P0.22 | ++-------+--------------+---------------------------+ +| 9 | D9 | P0.20/TRACECLK | ++-------+--------------+---------------------------+ +| 10 | D8 | P0.19 | ++-------+--------------+---------------------------+ + + +J11 + ++-------+--------------+---------------------------+ +| PIN # | Signal Name | BMD-300/301/350 Functions | ++=======+==============+===========================+ +| 1 | D12 (MISO) | P0.24 | ++-------+--------------+---------------------------+ +| 2 | V5V | N/A | ++-------+--------------+---------------------------+ +| 3 | D13 (SCK) | P0.25 | ++-------+--------------+---------------------------+ +| 4 | D11 (MOSI) | P0.23 | ++-------+--------------+---------------------------+ +| 5 | RESET | N/A | ++-------+--------------+---------------------------+ +| 6 | N/A | N/A | ++-------+--------------+---------------------------+ + + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the +BMD-300/301/350-EVAL can be found. For example, under Linux, +:code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd300eval/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-330-EVAL +************************************************ + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is +running correctly on your board. The button and LED definitions +can be found in :zephyr_file:`boards/ublox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts`. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/en/product/bmd-3035-series-open-cpu diff --git a/boards/arm/thingy52_nrf52832/pre_dt_board.cmake b/boards/u-blox/ubx_bmd300eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/thingy52_nrf52832/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd300eval/pre_dt_board.cmake diff --git a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832-pinctrl.dtsi b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832-pinctrl.dtsi rename to boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.dts b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.dts rename to boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts diff --git a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.yaml b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.yaml similarity index 88% rename from boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.yaml rename to boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.yaml index 09d6a50ed74..910642809d6 100644 --- a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.yaml +++ b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: ubx_bmd300eval_nrf52832 +identifier: ubx_bmd300eval/nrf52832 name: UBX_BMD300EVAL_NRF52832 type: mcu arch: arm diff --git a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832_defconfig b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832_defconfig similarity index 75% rename from boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832_defconfig rename to boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832_defconfig index 0ac55829154..8daa29dc473 100644 --- a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832_defconfig +++ b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_UBX_BMD300EVAL_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_bmd330eval/Kconfig b/boards/u-blox/ubx_bmd330eval/Kconfig new file mode 100644 index 00000000000..af68ffe247b --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/Kconfig @@ -0,0 +1,15 @@ +# BMD-330-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_BMD330EVAL + +# BT_CTLR depends on BT. When BT is enabled we should default to also +# enabling the controller. +config BT_CTLR + default y if BT diff --git a/boards/u-blox/ubx_bmd330eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd330eval/Kconfig.defconfig new file mode 100644 index 00000000000..3f43013dd27 --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/Kconfig.defconfig @@ -0,0 +1,8 @@ +# BMD-330-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD330EVAL + +endif # BOARD_UBX_BMD330EVAL diff --git a/boards/u-blox/ubx_bmd330eval/Kconfig.ubx_bmd330eval b/boards/u-blox/ubx_bmd330eval/Kconfig.ubx_bmd330eval new file mode 100644 index 00000000000..4c556d79277 --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/Kconfig.ubx_bmd330eval @@ -0,0 +1,7 @@ +# BMD-330-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD330EVAL + select SOC_NRF52810_QFAA diff --git a/boards/arm/ubx_bmd330eval_nrf52810/board.cmake b/boards/u-blox/ubx_bmd330eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/board.cmake rename to boards/u-blox/ubx_bmd330eval/board.cmake diff --git a/boards/u-blox/ubx_bmd330eval/board.yml b/boards/u-blox/ubx_bmd330eval/board.yml new file mode 100644 index 00000000000..d50ce8816f7 --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd330eval + vendor: u-blox + socs: + - name: nrf52810 diff --git a/boards/arm/ubx_bmd330eval_nrf52810/doc/img/BMD-30-33-35-36-EVAL.jpg b/boards/u-blox/ubx_bmd330eval/doc/img/BMD-30-33-35-36-EVAL.jpg similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/doc/img/BMD-30-33-35-36-EVAL.jpg rename to boards/u-blox/ubx_bmd330eval/doc/img/BMD-30-33-35-36-EVAL.jpg diff --git a/boards/arm/ubx_bmd330eval_nrf52810/doc/img/bmd-300-eval_pin_out.jpg b/boards/u-blox/ubx_bmd330eval/doc/img/bmd-300-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/doc/img/bmd-300-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd330eval/doc/img/bmd-300-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd330eval/doc/index.rst b/boards/u-blox/ubx_bmd330eval/doc/index.rst new file mode 100644 index 00000000000..d23b576f8f5 --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/doc/index.rst @@ -0,0 +1,388 @@ +.. _ubx_bmd330eval_nrf52810: + +u-blox EVK-BMD-330: BMD-330-EVAL +################################ + +Overview +******** + +The BMD-330-EVAL hardware provides support for the +u-blox BMD-330 Bluetooth 5 module, based on The +Nordic Semiconductor nRF52810 ARM Cortex-M4 CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/BMD-30-33-35-36-EVAL.jpg + :align: center + :alt: BMD-300-EVAL + + BMD-300-EVAL (Credit: u-blox AG) + +.. note:: + The BMD-330-EVAL shares the same pin headers and assignments as the + BMD-300-EVAL. The BMD-300-EVAL is shown here. + +More information about the BMD-330-EVAL and the BMD-330 module +can be found at the `u-blox website`_. All of the Nordic +Semiconductor examples for the nRF52 DK (nrf52dk_nrf52810) +may be used without modification. + +Hardware +******** + +The BMD-330 on the BMD-330-EVAL contains an internal +high-frequency oscillator at 32MHz. There is also a low frequency +(slow) oscillator of 32.768kHz. The BMD-330 itself does not include +the slow crystal; however, the BMD-330-EVAL does. + +.. note:: + When targeting a custom design without a slow crystal, + be sure to modify code to utilize the internal RC + oscillator for the slow clock. + +Supported Features +================== + +The BMD-330-EVAL configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of +BMD-330-EVAL hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.17 +* LED2 (red) = P0.18 +* LED3 (green) = P0.19 +* LED4 (green) = P0.20 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.13 +* BUTTON2 = SW2 = P0.14 +* BUTTON3 = SW3 = P0.15 +* BUTTON4 = SW4 = P0.16 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-300-eval_pin_out.jpg + :align: center + :alt: BMD-300-EVAL pin-out + + BMD-300-EVAL pin-out (Credit: u-blox AG) + +.. note:: + The BMD-330-EVAL shares the same pin headers and assignments + as the BMD-300-EVAL. The BMD-300-EVAL is shown here. + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-330-EVAL + for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 | ++-------+----------------+ +| 2 | P0.09 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.21 / RESET | ++-------+----------------+ +| 8 | P0.01 / XL2 | ++-------+----------------+ +| 9 | P0.00 / XL1 | ++-------+----------------+ +| 10 | GND | ++-------+----------------+ + + +Arduino Headers +--------------- + + +Power (J5) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-330 Functions | ++=======+==============+=========================+ +| 1 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.21 / RESET | ++-------+--------------+-------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ + +Analog in (J8) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-330 Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +Digital I/O (J7) + ++-------+--------------+----------------------------+ +| PIN # | Signal Name | BMD-330 Functions | ++=======+==============+============================+ +| 1 | D7 | P0.18 | ++-------+--------------+----------------------------+ +| 2 | D6 | P0.17 | ++-------+--------------+----------------------------+ +| 3 | D5 | P0.16 | ++-------+--------------+----------------------------+ +| 4 | D4 | P0.15 | ++-------+--------------+----------------------------+ +| 5 | D3 | P0.14 | ++-------+--------------+----------------------------+ +| 6 | D2 | P0.13 | ++-------+--------------+----------------------------+ +| 7 | D1 (TX) | P0.12 | ++-------+--------------+----------------------------+ +| 8 | D0 (RX) | P0.11 | ++-------+--------------+----------------------------+ + +Digital I/O (J6) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-330 Functions | ++=======+==============+=========================+ +| 1 | SCL | P0.27 | ++-------+--------------+-------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 3 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 4 | GND | N/A | ++-------+--------------+-------------------------+ +| 5 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 6 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 7 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 8 | D10 (SS) | P0.22 | ++-------+--------------+-------------------------+ +| 9 | D9 | P0.20 | ++-------+--------------+-------------------------+ +| 10 | D8 | P0.19 | ++-------+--------------+-------------------------+ + +J11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-330 Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the +BMD-330-EVAL can be found. For example, under Linux, +:code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd330eval/nrf52810 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-330-EVAL +************************************************ + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is +running correctly on your board. The button and LED definitions +can be found in :zephyr_file:`boards/ublox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts`. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/en/product/bmd-330-open-cpu diff --git a/boards/arm/ubx_bmd300eval_nrf52832/pre_dt_board.cmake b/boards/u-blox/ubx_bmd330eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd330eval/pre_dt_board.cmake diff --git a/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval.yaml b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval.yaml new file mode 100644 index 00000000000..50d337f1c35 --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval.yaml @@ -0,0 +1,23 @@ +identifier: ubx_bmd330eval/nrf52810 +name: UBX_BMD330EVAL_NRF52810 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 24 +flash: 192 +supported: + - adc + - arduino_gpio + - arduino_i2c + - arduino_spi + - gpio + - counter + - nvs + - i2c + - pwm + - spi + - watchdog +vendor: u-blox diff --git a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810-pinctrl.dtsi b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810-pinctrl.dtsi rename to boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.dts b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.dts rename to boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts diff --git a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810_defconfig b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810_defconfig similarity index 79% rename from boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810_defconfig rename to boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810_defconfig index edfe56e0a15..7107ff3f634 100644 --- a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810_defconfig +++ b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52810_QFAA=y -CONFIG_BOARD_UBX_BMD330EVAL_NRF52810=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_bmd340eval/Kconfig b/boards/u-blox/ubx_bmd340eval/Kconfig new file mode 100644 index 00000000000..6cc0ace7c6e --- /dev/null +++ b/boards/u-blox/ubx_bmd340eval/Kconfig @@ -0,0 +1,10 @@ +# BMD-340-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_BMD340EVAL diff --git a/boards/u-blox/ubx_bmd340eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd340eval/Kconfig.defconfig new file mode 100644 index 00000000000..37b10951309 --- /dev/null +++ b/boards/u-blox/ubx_bmd340eval/Kconfig.defconfig @@ -0,0 +1,11 @@ +# BMD-340-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD340EVAL + +config BT_CTLR + default BT + +endif # BOARD_UBX_BMD340EVAL diff --git a/boards/u-blox/ubx_bmd340eval/Kconfig.ubx_bmd340eval b/boards/u-blox/ubx_bmd340eval/Kconfig.ubx_bmd340eval new file mode 100644 index 00000000000..715be2a855b --- /dev/null +++ b/boards/u-blox/ubx_bmd340eval/Kconfig.ubx_bmd340eval @@ -0,0 +1,7 @@ +# BMD-340-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD340EVAL + select SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_bmd340eval_nrf52840/board.cmake b/boards/u-blox/ubx_bmd340eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/board.cmake rename to boards/u-blox/ubx_bmd340eval/board.cmake diff --git a/boards/u-blox/ubx_bmd340eval/board.yml b/boards/u-blox/ubx_bmd340eval/board.yml new file mode 100644 index 00000000000..2440541fc45 --- /dev/null +++ b/boards/u-blox/ubx_bmd340eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd340eval + vendor: u-blox + socs: + - name: nrf52840 diff --git a/boards/arm/ubx_bmd340eval_nrf52840/doc/img/BMD-34-38-EVAL.jpg b/boards/u-blox/ubx_bmd340eval/doc/img/BMD-34-38-EVAL.jpg similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/doc/img/BMD-34-38-EVAL.jpg rename to boards/u-blox/ubx_bmd340eval/doc/img/BMD-34-38-EVAL.jpg diff --git a/boards/arm/ubx_bmd340eval_nrf52840/doc/img/bmd-340-eval_pin_out.jpg b/boards/u-blox/ubx_bmd340eval/doc/img/bmd-340-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/doc/img/bmd-340-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd340eval/doc/img/bmd-340-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd340eval/doc/index.rst b/boards/u-blox/ubx_bmd340eval/doc/index.rst new file mode 100644 index 00000000000..bb1afcfa7fa --- /dev/null +++ b/boards/u-blox/ubx_bmd340eval/doc/index.rst @@ -0,0 +1,521 @@ +.. _ubx_bmd340eval_nrf52840: + +u-blox EVK-BMD-34/38: BMD-340-EVAL and BMD-341-EVAL +################################################### + +Overview +******** + +The BMD-340-EVAL and BMD-341-EVAL hardware provides support for the +u-blox BMD-340 and BMD-341 Bluetooth 5.0 modules, based on the +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU. the BMD-340 and +BMD-341 are identical in operation except for the antenna. The +BMD-340 has a PCB antenna while the BMD-341 has a U.FL connector. +Both support the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/BMD-34-38-EVAL.jpg + :align: center + :alt: BMD-340-EVAL + + BMD-340-EVAL (Credit: u-blox AG) + +More information about the BMD-340-EVAL, BMD-340 module, BMD-341-EVAL, +and BMD-341 module can be found at the `u-blox website`_. +All of the Nordic Semiconductor examples for the nRF52840 DK +(nrf52840dk_nrf52840) may be used without modification. + +..note:: + The BMD-340 and BMD-341 are identical except for the antenna. + Throughout this board support package, the filenames utilize + the ubx_bmd340eval_nrf52840. + +Hardware +******** + +The BMD-340 on the BMD-340-EVAL (or BMD-341 on the BMD-341-EVAL) +contains an internal high-frequency oscillator at 32MHz. +There is also a low frequency (slow) oscillator of 32.768kHz. +The BMD-340 and BMD-341 do not include the slow crystal; +however, the BMD-340-EVAL and BMD-341-EVAL do. + +.. note:: + + When targeting a custom design without a slow crystal, be sure + to modify code to utilize the internal RC oscillator for the + slow clock. + +Supported Features +================== + +The BMD-340-EVAL and BMD-341-EVAL board configuration supports +the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | IEEE 802.15.4 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of BMD-340-EVAL +and BMD-341-EVAL hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.13 +* LED2 (red) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-340-eval_pin_out.jpg + :align: center + :alt: BMD-340-EVAL pin-out + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-340-EVAL or + BMD-341-EVAL for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + +Debug IN (J26) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | BMD-340_VCC | ++-------+----------------+ +| 2 | BMD-340_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | BMD-340_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | BMD-340_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | GND | ++-------+----------------+ +| 10 | BMD-340_RESET | ++-------+----------------+ + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 / NFC2 | ++-------+----------------+ +| 2 | P0.09 / NFC1 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.01 / XL2 | ++-------+----------------+ +| 8 | P0.00 / XL1 | ++-------+----------------+ + +Auxiliary (J10) + ++-------+-------------------+ +| PIN # | Signal Name | ++=======+===================+ +| 1 | P0.11 / TRACED[2] | ++-------+-------------------+ +| 2 | P0.12 / TRACED[1] | ++-------+-------------------+ +| 3 | P0.13 | ++-------+-------------------+ +| 4 | P0.14 | ++-------+-------------------+ +| 5 | P0.15 | ++-------+-------------------+ +| 6 | P0.16 | ++-------+-------------------+ +| 7 | P0.17 / QSPI_CS | ++-------+-------------------+ +| 8 | P0.18 / RESET | ++-------+-------------------+ +| 9 | P0.19 / QSPI_CLK | ++-------+-------------------+ +| 10 | P0.20 / QSPI_D0 | ++-------+-------------------+ +| 11 | P0.21 / QSPI_D1 | ++-------+-------------------+ +| 12 | P0.22 / QSPI_D2 | ++-------+-------------------+ +| 13 | P0.23 / QSPI_D3 | ++-------+-------------------+ +| 14 | P0.24 | ++-------+-------------------+ +| 15 | P0.25 | ++-------+-------------------+ +| 16 | P1.00 / TRACED[0] | ++-------+-------------------+ +| 17 | P1.09 / TRACED[3] | ++-------+-------------------+ +| 18 | No connection | ++-------+-------------------+ + +Arduino Headers +--------------- + +Power (J5) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-34x Functions | ++=======+==============+=========================+ +| 1 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.18 / RESET | ++-------+--------------+-------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ + +Analog in (J8) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-34x Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +Digital I/O (J7) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-34x Functions | ++=======+==============+=========================+ +| 1 | D7 | P1.08 | ++-------+--------------+-------------------------+ +| 2 | D6 | P1.07 | ++-------+--------------+-------------------------+ +| 3 | D5 | P1.06 | ++-------+--------------+-------------------------+ +| 4 | D4 | P1.05 | ++-------+--------------+-------------------------+ +| 5 | D3 | P1.04 | ++-------+--------------+-------------------------+ +| 6 | D2 | P1.03 | ++-------+--------------+-------------------------+ +| 7 | D1 (TX) | P1.02 | ++-------+--------------+-------------------------+ +| 8 | D0 (RX) | P1.01 | ++-------+--------------+-------------------------+ + +Digital I/O (J6) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-34x Functions | ++=======+==============+=========================+ +| 1 | SCL | P0.27 | ++-------+--------------+-------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 3 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 4 | GND | N/A | ++-------+--------------+-------------------------+ +| 5 | D13 (SCK) | P1.15 | ++-------+--------------+-------------------------+ +| 6 | D12 (MISO) | P1.14 | ++-------+--------------+-------------------------+ +| 7 | D11 (MOSI) | P1.13 | ++-------+--------------+-------------------------+ +| 8 | D10 (SS) | P1.12 | ++-------+--------------+-------------------------+ +| 9 | D9 | P1.11 | ++-------+--------------+-------------------------+ +| 10 | D8 | P1.10 | ++-------+--------------+-------------------------+ + +J11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-34x Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.14 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.15 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.13 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Applications for the BMD-340-EVAL and BMD-341-EVAL board +configurations can be built and flashed in the usual way +(see :ref:`build_an_application` and :ref:`application_run` +for more details); however, the standard debugging targets +are not currently available. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the BMD-340-EVAL +or BMD-341-EVAL can be found. For example, under Linux, +:code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd340eval/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-340-EVAL and BMD-341-EVAL +***************************************************************** + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found +in +:zephyr_file:`boards/ublox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts`. + +Using UART1 +*********** + +The following approach can be used when an application needs to use +more than one UART for connecting peripheral devices: + +1. Add device tree overlay file to the main directory of your + application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is + used for TX + +2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` + +Overlay file naming +=================== + +The file has to be named ``.overlay`` and placed in the app +main directory to be picked up automatically by the device tree +compiler. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the data sheet for the BMD-340 at the `u-blox website`_, Section 2 +'Pin definition'. In the table 3 select the pins marked 'GPIO'. +Note that pins marked as 'Standard drive, low frequency I/O only +(<10 kH' can only be used in under-10KHz applications. +They are not suitable for 115200 speed of UART. + +.. note: + Pins are defined according to the "nRF52" pin number, not the module + pad number. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/docs/UBX-19033353 diff --git a/boards/arm/ubx_bmd330eval_nrf52810/pre_dt_board.cmake b/boards/u-blox/ubx_bmd340eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd340eval/pre_dt_board.cmake diff --git a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840-pinctrl.dtsi b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840-pinctrl.dtsi rename to boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts rename to boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts diff --git a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.yaml b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml similarity index 90% rename from boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.yaml rename to boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml index dbe7c648911..be6ccd190a8 100644 --- a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.yaml +++ b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: ubx_bmd340eval_nrf52840 +identifier: ubx_bmd340eval/nrf52840 name: UBX_BMD340EVAL_NRF52840 type: mcu arch: arm diff --git a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840_defconfig b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840_defconfig similarity index 79% rename from boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840_defconfig rename to boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840_defconfig index f1fd8825b8c..78510eb0204 100644 --- a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840_defconfig +++ b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_UBX_BMD340EVAL_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_bmd345eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd345eval/Kconfig.defconfig new file mode 100644 index 00000000000..21e8ac9b5ca --- /dev/null +++ b/boards/u-blox/ubx_bmd345eval/Kconfig.defconfig @@ -0,0 +1,12 @@ +# BMD-345-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# Copyright (c) 2021 Linumiz +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD345EVAL_NRF52840 + +config BT_CTLR + default BT + +endif # BOARD_UBX_BMD345EVAL_NRF52840 diff --git a/boards/u-blox/ubx_bmd345eval/Kconfig.ubx_bmd345eval b/boards/u-blox/ubx_bmd345eval/Kconfig.ubx_bmd345eval new file mode 100644 index 00000000000..01858fd7dcf --- /dev/null +++ b/boards/u-blox/ubx_bmd345eval/Kconfig.ubx_bmd345eval @@ -0,0 +1,8 @@ +# BMD-340-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# Copyright (c) 2021 Linumiz +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD345EVAL + select SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_bmd345eval_nrf52840/board.cmake b/boards/u-blox/ubx_bmd345eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/board.cmake rename to boards/u-blox/ubx_bmd345eval/board.cmake diff --git a/boards/u-blox/ubx_bmd345eval/board.yml b/boards/u-blox/ubx_bmd345eval/board.yml new file mode 100644 index 00000000000..eec2be0b7d9 --- /dev/null +++ b/boards/u-blox/ubx_bmd345eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd345eval + vendor: u-blox + socs: + - name: nrf52840 diff --git a/boards/arm/ubx_bmd345eval_nrf52840/doc/img/bmd-345-eval_features.jpg b/boards/u-blox/ubx_bmd345eval/doc/img/bmd-345-eval_features.jpg similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/doc/img/bmd-345-eval_features.jpg rename to boards/u-blox/ubx_bmd345eval/doc/img/bmd-345-eval_features.jpg diff --git a/boards/arm/ubx_bmd345eval_nrf52840/doc/img/bmd-345-eval_pin_out.jpg b/boards/u-blox/ubx_bmd345eval/doc/img/bmd-345-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/doc/img/bmd-345-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd345eval/doc/img/bmd-345-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd345eval/doc/index.rst b/boards/u-blox/ubx_bmd345eval/doc/index.rst new file mode 100644 index 00000000000..e63507eb4fc --- /dev/null +++ b/boards/u-blox/ubx_bmd345eval/doc/index.rst @@ -0,0 +1,533 @@ +.. _ubx_bmd345eval_nrf52840: + +u-blox EVK-BMD-34/38: BMD-345-EVAL +################################## + +Overview +******** + +The BMD-345-EVALhardware provides support for the u-blox BMD-345 +Bluetooth 5.0 modules, based on the Nordic Semiconductor nRF52840 +ARM Cortex-M4F CPU and Skyworks RFX2411 Front End Module (FEM), +also known as a Power Amplifier / Low Noise Amplifier (PA/LNA). +Both support the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/bmd-345-eval_features.jpg + :align: center + :alt: BMD 345 EVAL + + BMD-345-EVAL (Credit: ublox AG) + +More information about the BMD-345-EVAL and BMD-345 module can be +found at the `u-blox website`_. + + +Hardware +******** + +The BMD-345 on the BMD-345-EVAL contains an internal high-frequency +oscillator at 32MHz. There is also a low frequency (slow) +oscillator of 32.768kHz. The BMD-345 does not include the slow +crystal; however, the BMD-345-EVAL does. + +.. note:: + + When targeting a custom design without a slow crystal, be sure + to modify code to utilize the internal RC oscillator for the + slow clock. + +Front End Module +================ + +BMD-345 utilizes the Skyworks RFX2411 front end module (FEM). +The FEM provides higher output power and better sensitivity. + +FEM pin assignments +------------------- + ++-------------+--------------+----------+--------+----------+---------+ +| GPIO Number | Signal Name | Shutdown | Bypass | Transmit | Receive | ++=============+==============+==========+========+==========+=========+ +| P1.05 | TX_EN | Low | Low | High | Low | ++-------------+--------------+----------+--------+----------+---------+ +| P1.06 | RX_EN | Low | Low | Low | High | ++-------------+--------------+----------+--------+----------+---------+ +| P1.04 | MODE | Low | High | Low | Low | ++-------------+--------------+----------+--------+----------+---------+ +| P1.02 | A_SEL | Low | Low | Low | Low | ++-------------+--------------+----------+--------+----------+---------+ + +Supported Features +================== + +The BMD-345-EVAL board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | IEEE 802.15.4 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of BMD-345-EVAL +hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.13 +* LED2 (red) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-345-eval_pin_out.jpg + :align: center + :alt: BMD-345-EVAL pin-out + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-340-EVAL or + BMD-341-EVAL for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + +Debug IN (J26) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | BMD-340_VCC | ++-------+----------------+ +| 2 | BMD-340_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | BMD-340_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | BMD-340_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | GND | ++-------+----------------+ +| 10 | BMD-340_RESET | ++-------+----------------+ + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 / NFC2 | ++-------+----------------+ +| 2 | P0.09 / NFC1 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.01 / XL2 | ++-------+----------------+ +| 8 | P0.00 / XL1 | ++-------+----------------+ + +Auxiliary (J10) + ++-------+-------------------+ +| PIN # | Signal Name | ++=======+===================+ +| 1 | P0.11 / TRACED[2] | ++-------+-------------------+ +| 2 | P0.12 / TRACED[1] | ++-------+-------------------+ +| 3 | P0.13 | ++-------+-------------------+ +| 4 | P0.14 | ++-------+-------------------+ +| 5 | P0.15 | ++-------+-------------------+ +| 6 | P0.16 | ++-------+-------------------+ +| 7 | P0.17 / QSPI_CS | ++-------+-------------------+ +| 8 | P0.18 / RESET | ++-------+-------------------+ +| 9 | P0.19 / QSPI_CLK | ++-------+-------------------+ +| 10 | P0.20 / QSPI_D0 | ++-------+-------------------+ +| 11 | P0.21 / QSPI_D1 | ++-------+-------------------+ +| 12 | P0.22 / QSPI_D2 | ++-------+-------------------+ +| 13 | P0.23 / QSPI_D3 | ++-------+-------------------+ +| 14 | P0.24 | ++-------+-------------------+ +| 15 | P0.25 | ++-------+-------------------+ +| 16 | P1.00 / TRACED[0] | ++-------+-------------------+ +| 17 | P1.09 / TRACED[3] | ++-------+-------------------+ +| 18 | No connection | ++-------+-------------------+ + +Arduino Headers +--------------- + +Power (J5) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-345 Functions | ++=======+==============+=========================+ +| 1 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.18 / RESET | ++-------+--------------+-------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ + +Analog in (J8) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-345 Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +Digital I/O (J7) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-345 Functions | ++=======+==============+=========================+ +| 1 | D7 | P1.08 | ++-------+--------------+-------------------------+ +| 2 | D6 | P1.07 | ++-------+--------------+-------------------------+ +| 3 | N/C | N/A | ++-------+--------------+-------------------------+ +| 4 | N/C | N/A | ++-------+--------------+-------------------------+ +| 5 | N/C | N/A | ++-------+--------------+-------------------------+ +| 6 | D2 | P1.03 | ++-------+--------------+-------------------------+ +| 7 | N/C | N/A | ++-------+--------------+-------------------------+ +| 8 | D0 (RX) | P1.01 | ++-------+--------------+-------------------------+ + +Digital I/O (J6) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-345 Functions | ++=======+==============+=========================+ +| 1 | SCL | P0.27 | ++-------+--------------+-------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 3 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 4 | GND | N/A | ++-------+--------------+-------------------------+ +| 5 | D13 (SCK) | P1.15 | ++-------+--------------+-------------------------+ +| 6 | D12 (MISO) | P1.14 | ++-------+--------------+-------------------------+ +| 7 | D11 (MOSI) | P1.13 | ++-------+--------------+-------------------------+ +| 8 | D10 (SS) | P1.12 | ++-------+--------------+-------------------------+ +| 9 | D9 | P1.11 | ++-------+--------------+-------------------------+ +| 10 | D8 | P1.10 | ++-------+--------------+-------------------------+ + +J11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-345 Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.14 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.15 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.13 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Applications for the BMD-345-EVAL board +configurations can be built and flashed in the usual way +(see :ref:`build_an_application` and :ref:`application_run` +for more details); however, the standard debugging targets +are not currently available. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the BMD-345-EVAL +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd345eval/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-345-EVAL +***************************************************************** + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found +in +:zephyr_file:`boards/ublox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts`. + +Using UART1 +*********** + +The following approach can be used when an application needs to use +more than one UART for connecting peripheral devices: + +1. Add device tree overlay file to the main directory of your + application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is + used for TX + +2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` + +Overlay file naming +=================== + +The file has to be named ``.overlay`` and placed in the app +main directory to be picked up automatically by the device tree +compiler. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the data sheet for the BMD-345 at the `u-blox website`_, Section 2 +'Pin definition'. In the table 3 select the pins marked 'GPIO'. +Note that pins marked as 'Standard drive, low frequency I/O only +(<10 kH' can only be used in under-10KHz applications. +They are not suitable for 115200 speed of UART. + +.. note: + Pins are defined according to the "nRF52" pin number, not the module + pad number. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/en/product/bmd-34-series-open-cpu diff --git a/boards/arm/ubx_bmd340eval_nrf52840/pre_dt_board.cmake b/boards/u-blox/ubx_bmd345eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd345eval/pre_dt_board.cmake diff --git a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840-pinctrl.dtsi b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840-pinctrl.dtsi rename to boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.dts b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.dts rename to boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts diff --git a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.yaml b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml similarity index 89% rename from boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.yaml rename to boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml index 7d8201f2093..fa53f794f09 100644 --- a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.yaml +++ b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: ubx_bmd345eval_nrf52840 +identifier: ubx_bmd345eval/nrf52840 name: BMD-345-EVAL type: mcu arch: arm diff --git a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840_defconfig b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840_defconfig similarity index 79% rename from boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840_defconfig rename to boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840_defconfig index 97872745a6d..71e6c0a6d60 100644 --- a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840_defconfig +++ b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_UBX_BMD345EVAL_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_bmd360eval/Kconfig b/boards/u-blox/ubx_bmd360eval/Kconfig new file mode 100644 index 00000000000..89f886d08e4 --- /dev/null +++ b/boards/u-blox/ubx_bmd360eval/Kconfig @@ -0,0 +1,15 @@ +# BMD-360-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_BMD360EVAL + +# BT_CTLR depends on BT. When BT is enabled we should default to also +# enabling the controller. +config BT_CTLR + default y if BT diff --git a/boards/u-blox/ubx_bmd360eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd360eval/Kconfig.defconfig new file mode 100644 index 00000000000..eb35b4bb152 --- /dev/null +++ b/boards/u-blox/ubx_bmd360eval/Kconfig.defconfig @@ -0,0 +1,8 @@ +# BMD-360-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD360EVAL + +endif # BOARD_UBX_BMD360EVAL diff --git a/boards/u-blox/ubx_bmd360eval/Kconfig.ubx_bmd360eval b/boards/u-blox/ubx_bmd360eval/Kconfig.ubx_bmd360eval new file mode 100644 index 00000000000..6661cadd9fa --- /dev/null +++ b/boards/u-blox/ubx_bmd360eval/Kconfig.ubx_bmd360eval @@ -0,0 +1,7 @@ +# BMD-360-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD360EVAL + select SOC_NRF52811_QFAA diff --git a/boards/arm/ubx_bmd360eval_nrf52811/board.cmake b/boards/u-blox/ubx_bmd360eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/board.cmake rename to boards/u-blox/ubx_bmd360eval/board.cmake diff --git a/boards/u-blox/ubx_bmd360eval/board.yml b/boards/u-blox/ubx_bmd360eval/board.yml new file mode 100644 index 00000000000..a06d24dd008 --- /dev/null +++ b/boards/u-blox/ubx_bmd360eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd360eval + vendor: u-blox + socs: + - name: nrf52811 diff --git a/boards/arm/ubx_bmd360eval_nrf52811/doc/img/BMD-30-33-35-36-EVAL.jpg b/boards/u-blox/ubx_bmd360eval/doc/img/BMD-30-33-35-36-EVAL.jpg similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/doc/img/BMD-30-33-35-36-EVAL.jpg rename to boards/u-blox/ubx_bmd360eval/doc/img/BMD-30-33-35-36-EVAL.jpg diff --git a/boards/arm/ubx_bmd360eval_nrf52811/doc/img/bmd-300-eval_pin_out.jpg b/boards/u-blox/ubx_bmd360eval/doc/img/bmd-300-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/doc/img/bmd-300-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd360eval/doc/img/bmd-300-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd360eval/doc/index.rst b/boards/u-blox/ubx_bmd360eval/doc/index.rst new file mode 100644 index 00000000000..9ce29132c13 --- /dev/null +++ b/boards/u-blox/ubx_bmd360eval/doc/index.rst @@ -0,0 +1,386 @@ +.. _ubx_bmd360eval_nrf52811: + +u-blox EVK-BMD-360: BMD-360-EVAL +################################ + +Overview +******** + +The BMD-360-EVAL hardware provides support for the +u-blox BMD-360 Bluetooth 5 module, based on The +Nordic Semiconductor nRF52811 ARM Cortex-M4 CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/BMD-30-33-35-36-EVAL.jpg + :align: center + :alt: BMD-300-EVAL + + BMD-300-EVAL (Credit: u-blox AG) + +.. note:: + The BMD-360-EVAL shares the same pin headers and assignments as the + BMD-300-EVAL. The BMD-300-EVAL is shown here. + +More information about the BMD-360-EVAL and the BMD-360 module +can be found at the `u-blox website`_. + +Hardware +******** + +The BMD-360 on the BMD-360-EVAL contains an internal +high-frequency oscillator at 32MHz. There is also a low frequency +(slow) oscillator of 32.768kHz. The BMD-360 itself does not include +the slow crystal; however, the BMD-360-EVAL does. + +.. note:: + When targeting a custom design without a slow crystal, + be sure to modify code to utilize the internal RC + oscillator for the slow clock. + +Supported Features +================== + +The BMD-360-EVAL configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of +BMD-360-EVAL hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.17 +* LED2 (red) = P0.18 +* LED3 (green) = P0.19 +* LED4 (green) = P0.20 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.13 +* BUTTON2 = SW2 = P0.14 +* BUTTON3 = SW3 = P0.15 +* BUTTON4 = SW4 = P0.16 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-300-eval_pin_out.jpg + :align: center + :alt: BMD-300-EVAL pin-out + + BMD-300-EVAL pin-out (Credit: u-blox AG) + +.. note:: + The BMD-360-EVAL shares the same pin headers and assignments + as the BMD-300-EVAL. The BMD-300-EVAL is shown here. + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-360-EVAL + for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 | ++-------+----------------+ +| 2 | P0.09 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.21 / RESET | ++-------+----------------+ +| 8 | P0.01 / XL2 | ++-------+----------------+ +| 9 | P0.00 / XL1 | ++-------+----------------+ +| 10 | GND | ++-------+----------------+ + + +Arduino Headers +--------------- + + +Power (J5) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-360 Functions | ++=======+==============+=========================+ +| 1 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.21 / RESET | ++-------+--------------+-------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ + +Analog in (J8) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-360 Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +Digital I/O (J7) + ++-------+--------------+----------------------------+ +| PIN # | Signal Name | BMD-360 Functions | ++=======+==============+============================+ +| 1 | D7 | P0.18 | ++-------+--------------+----------------------------+ +| 2 | D6 | P0.17 | ++-------+--------------+----------------------------+ +| 3 | D5 | P0.16 | ++-------+--------------+----------------------------+ +| 4 | D4 | P0.15 | ++-------+--------------+----------------------------+ +| 5 | D3 | P0.14 | ++-------+--------------+----------------------------+ +| 6 | D2 | P0.13 | ++-------+--------------+----------------------------+ +| 7 | D1 (TX) | P0.12 | ++-------+--------------+----------------------------+ +| 8 | D0 (RX) | P0.11 | ++-------+--------------+----------------------------+ + +Digital I/O (J6) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-360 Functions | ++=======+==============+=========================+ +| 1 | SCL | P0.27 | ++-------+--------------+-------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 3 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 4 | GND | N/A | ++-------+--------------+-------------------------+ +| 5 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 6 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 7 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 8 | D10 (SS) | P0.22 | ++-------+--------------+-------------------------+ +| 9 | D9 | P0.20 | ++-------+--------------+-------------------------+ +| 10 | D8 | P0.19 | ++-------+--------------+-------------------------+ + +J11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-360 Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the +BMD-360-EVAL can be found. For example, under Linux, +:code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd360eval/nrf52811 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-360-EVAL +************************************************ + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is +running correctly on your board. The button and LED definitions +can be found in :zephyr_file:`boards/ublox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts`. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/en/product/bmd-360-open-cpu diff --git a/boards/arm/ubx_bmd345eval_nrf52840/pre_dt_board.cmake b/boards/u-blox/ubx_bmd360eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd360eval/pre_dt_board.cmake diff --git a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811-pinctrl.dtsi b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811-pinctrl.dtsi rename to boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.dts b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.dts rename to boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts diff --git a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.yaml b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.yaml similarity index 88% rename from boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.yaml rename to boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.yaml index 3da084eb1ac..4df9c1172f0 100644 --- a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.yaml +++ b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.yaml @@ -1,4 +1,4 @@ -identifier: ubx_bmd360eval_nrf52811 +identifier: ubx_bmd360eval/nrf52811 name: UBX_BMD360EVAL_NRF52811 type: mcu arch: arm diff --git a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811_defconfig b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811_defconfig similarity index 79% rename from boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811_defconfig rename to boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811_defconfig index 6cc16653c74..b2f60844ace 100644 --- a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811_defconfig +++ b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52811_QFAA=y -CONFIG_BOARD_UBX_BMD360EVAL_NRF52811=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_bmd380eval/Kconfig b/boards/u-blox/ubx_bmd380eval/Kconfig new file mode 100644 index 00000000000..def5144ceef --- /dev/null +++ b/boards/u-blox/ubx_bmd380eval/Kconfig @@ -0,0 +1,10 @@ +# BMD-380-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_BMD380EVAL diff --git a/boards/u-blox/ubx_bmd380eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd380eval/Kconfig.defconfig new file mode 100644 index 00000000000..58afb83796f --- /dev/null +++ b/boards/u-blox/ubx_bmd380eval/Kconfig.defconfig @@ -0,0 +1,11 @@ +# BMD-380-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD380EVAL + +config BT_CTLR + default BT + +endif # BOARD_UBX_BMD380EVAL diff --git a/boards/u-blox/ubx_bmd380eval/Kconfig.ubx_bmd380eval b/boards/u-blox/ubx_bmd380eval/Kconfig.ubx_bmd380eval new file mode 100644 index 00000000000..a6c93345379 --- /dev/null +++ b/boards/u-blox/ubx_bmd380eval/Kconfig.ubx_bmd380eval @@ -0,0 +1,10 @@ +# BMD-380-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD380EVAL + select SOC_NRF52840_QIAA + +# should be CKAA, +# but SOC file not yet available from Nordic Semiconductor diff --git a/boards/arm/ubx_bmd380eval_nrf52840/board.cmake b/boards/u-blox/ubx_bmd380eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/board.cmake rename to boards/u-blox/ubx_bmd380eval/board.cmake diff --git a/boards/u-blox/ubx_bmd380eval/board.yml b/boards/u-blox/ubx_bmd380eval/board.yml new file mode 100644 index 00000000000..0f7ec7263e7 --- /dev/null +++ b/boards/u-blox/ubx_bmd380eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd380eval + vendor: u-blox + socs: + - name: nrf52840 diff --git a/boards/arm/ubx_bmd380eval_nrf52840/doc/img/BMD-34-38-EVAL.jpg b/boards/u-blox/ubx_bmd380eval/doc/img/BMD-34-38-EVAL.jpg similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/doc/img/BMD-34-38-EVAL.jpg rename to boards/u-blox/ubx_bmd380eval/doc/img/BMD-34-38-EVAL.jpg diff --git a/boards/arm/ubx_bmd380eval_nrf52840/doc/img/bmd-340-eval_pin_out.jpg b/boards/u-blox/ubx_bmd380eval/doc/img/bmd-340-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/doc/img/bmd-340-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd380eval/doc/img/bmd-340-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd380eval/doc/index.rst b/boards/u-blox/ubx_bmd380eval/doc/index.rst new file mode 100644 index 00000000000..1c89222536e --- /dev/null +++ b/boards/u-blox/ubx_bmd380eval/doc/index.rst @@ -0,0 +1,518 @@ +.. _ubx_bmd380eval_nrf52840: + +u-blox EVK-BMD-34/48: BMD-380-EVAL +################################## + +Overview +******** + +The BMD-380-EVAL hardware provides support for the +u-blox BMD-380 Bluetooth 5.0 module, based on The +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/BMD-34-38-EVAL.jpg + :align: center + :alt: BMD-340-EVAL + + BMD-340-EVAL (Credit: u-blox AG) + +.. note:: + The BMD-380-EVAL shares the same pin headers and assignments as the + BMD-340-EVAL with four exceptions. The BMD-340-EVAL is shown here. + See the pin tables below for the exceptions. + +More information about the BMD-340-EVAL and the BMD-340 module +can be found at the `u-blox website`_. All of the Nordic Semiconductor +examples for the nRF52840 DK (nrf52840dk_nrf52840) may be used without +modification. + +Hardware +******** + +The BMD-380 on the BMD-380-EVAL contains an internal high-frequency +oscillator at 32MHz. There is also a low frequency (slow) oscillator +of 32.768kHz. The BMD-380 itself does not include the slow crystal; +however, the BMD-380-eval does. + +.. note:: + + When targeting a custom design without a slow crystal, be sure + to modify code to utilize the internal RC oscillator for the + slow clock. + +Supported Features +================== + +The BMD-380-EVAL board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | IEEE 802.15.4 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of BMD-380-EVAL +hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.13 +* LED2 (red) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-340-eval_pin_out.jpg + :align: center + :alt: BMD-340-EVAL pin-out + +.. note:: + The BMD-380-EVAL shares the same pin headers and assignments as the + BMD-340-EVAL with four exceptions. The BMD-340-EVAL is shown here. + See the pin tables below for the exceptions. + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-380-EVAL + for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + +Debug IN (J26) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | BMD-340_VCC | ++-------+----------------+ +| 2 | BMD-340_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | BMD-340_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | BMD-340_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | GND | ++-------+----------------+ +| 10 | BMD-340_RESET | ++-------+----------------+ + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 / NFC2 | ++-------+----------------+ +| 2 | P0.09 / NFC1 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.01 / XL2 | ++-------+----------------+ +| 8 | P0.00 / XL1 | ++-------+----------------+ + +Auxiliary (J10) + ++-------+-------------------+ +| PIN # | Signal Name | ++=======+===================+ +| 1 | P0.11 / TRACED[2] | ++-------+-------------------+ +| 2 | P0.12 / TRACED[1] | ++-------+-------------------+ +| 3 | P0.13 | ++-------+-------------------+ +| 4 | P0.14 | ++-------+-------------------+ +| 5 | P0.15 | ++-------+-------------------+ +| 6 | P0.16 | ++-------+-------------------+ +| 7 | P0.17 / QSPI_CS | ++-------+-------------------+ +| 8 | P0.18 / RESET | ++-------+-------------------+ +| 9 | P0.19 / QSPI_CLK | ++-------+-------------------+ +| 10 | P0.20 / QSPI_D0 | ++-------+-------------------+ +| 11 | P0.21 / QSPI_D1 | ++-------+-------------------+ +| 12 | P0.22 / QSPI_D2 | ++-------+-------------------+ +| 13 | P0.23 / QSPI_D3 | ++-------+-------------------+ +| 14 | P0.24 | ++-------+-------------------+ +| 15 | P0.25 | ++-------+-------------------+ +| 16 | P1.00 / TRACED[0] | ++-------+-------------------+ +| 17 | P1.09 / TRACED[3] | ++-------+-------------------+ +| 18 | No connection | ++-------+-------------------+ + +Power (J5) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-380 Functions | ++=======+==============+=========================+ +| 1 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.18 / RESET | ++-------+--------------+-------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ + +Analog in (J8) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-380 Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +Digital I/O (J7) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-380 Functions | ++=======+==============+=========================+ +| 1 | D7 | P1.08 | ++-------+--------------+-------------------------+ +| 2 | - | No connection | ++-------+--------------+-------------------------+ +| 3 | D5 | P1.06 | ++-------+--------------+-------------------------+ +| 4 | D4 | No connection | ++-------+--------------+-------------------------+ +| 5 | - | No connection | ++-------+--------------+-------------------------+ +| 6 | - | No connection | ++-------+--------------+-------------------------+ +| 7 | D1 (TX) | P1.02 | ++-------+--------------+-------------------------+ +| 8 | - | No connection | ++-------+--------------+-------------------------+ + +Digital I/O (J6) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-380 Functions | ++=======+==============+=========================+ +| 1 | SCL | P0.27 | ++-------+--------------+-------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 3 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 4 | GND | N/A | ++-------+--------------+-------------------------+ +| 5 | D13 (SCK) | P1.15 | ++-------+--------------+-------------------------+ +| 6 | D12 (MISO) | P1.14 | ++-------+--------------+-------------------------+ +| 7 | D11 (MOSI) | P1.13 | ++-------+--------------+-------------------------+ +| 8 | D10 (SS) | P1.12 | ++-------+--------------+-------------------------+ +| 9 | D9 | P1.11 | ++-------+--------------+-------------------------+ +| 10 | D8 | P1.10 | ++-------+--------------+-------------------------+ + +J11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-380 Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.14 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.15 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.13 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Applications for the BMD-380-EVAL board configurations can +be built and flashed in the usual way +(see :ref:`build_an_application` and :ref:`application_run` +for more details); however, the standard debugging targets +are not currently available. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the BMD-380-EVAL +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd380eval/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-380-EVAL +************************************************ + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found in +:zephyr_file:`boards/ublox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts`. + +Using UART1 +*********** + +The following approach can be used when an application needs to use +more than one UART for connecting peripheral devices: + +1. Add device tree overlay file to the main directory of your + application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is + used for TX + +2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` + +Overlay file naming +=================== + +The file has to be named ``.overlay`` and placed in the app +main directory to be picked up automatically by the device tree +compiler. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the data sheet for the BMD-380 at the `u-blox website`_, Section 2 +'Pin definition'. In the table 3 select the pins marked 'GPIO'. +Note that pins marked as 'Standard drive, low frequency I/O only +(<10 kH' can only be used in under-10KHz applications. +They are not suitable for 115200 speed of UART. + +.. note: + Pins are defined according to the "nRF52" pin number, not the module + pad number. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/docs/UBX-19039467 diff --git a/boards/arm/ubx_bmd360eval_nrf52811/pre_dt_board.cmake b/boards/u-blox/ubx_bmd380eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd380eval/pre_dt_board.cmake diff --git a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840-pinctrl.dtsi b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840-pinctrl.dtsi rename to boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.dts b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.dts similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.dts rename to boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.dts diff --git a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.yaml b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml similarity index 88% rename from boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.yaml rename to boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml index afd074165c1..15bb236585d 100644 --- a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.yaml +++ b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: ubx_bmd380eval_nrf52840 +identifier: ubx_bmd380eval/nrf52840 name: UBX_BMD380EVAL_NRF52840 type: mcu arch: arm diff --git a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840_defconfig b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840_defconfig similarity index 82% rename from boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840_defconfig rename to boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840_defconfig index 79826cc9974..7d36d059a41 100644 --- a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840_defconfig +++ b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840_defconfig @@ -3,10 +3,7 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y # should be CKAA, but not available yet from Nordic Semiconductor -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_UBX_BMD380EVAL_NRF52840=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/u-blox/ubx_evkannab1/Kconfig b/boards/u-blox/ubx_evkannab1/Kconfig new file mode 100644 index 00000000000..cba82a1d0b2 --- /dev/null +++ b/boards/u-blox/ubx_evkannab1/Kconfig @@ -0,0 +1,10 @@ +# u-blox EVK-ANNA-B1 board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_EVKANNAB1 diff --git a/boards/u-blox/ubx_evkannab1/Kconfig.defconfig b/boards/u-blox/ubx_evkannab1/Kconfig.defconfig new file mode 100644 index 00000000000..e12e7d4ebac --- /dev/null +++ b/boards/u-blox/ubx_evkannab1/Kconfig.defconfig @@ -0,0 +1,11 @@ +# u-blox EVK-ANNA-B1 board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_EVKANNAB1 + +config BT_CTLR + default BT + +endif # BOARD_UBX_EVKANNAB1 diff --git a/boards/u-blox/ubx_evkannab1/Kconfig.ubx_evkannab1 b/boards/u-blox/ubx_evkannab1/Kconfig.ubx_evkannab1 new file mode 100644 index 00000000000..cb43df23647 --- /dev/null +++ b/boards/u-blox/ubx_evkannab1/Kconfig.ubx_evkannab1 @@ -0,0 +1,7 @@ +# u-blox EVK-ANNA-B1 board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_EVKANNAB1 + select SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_evkannab1_nrf52832/board.cmake b/boards/u-blox/ubx_evkannab1/board.cmake similarity index 100% rename from boards/arm/ubx_evkannab1_nrf52832/board.cmake rename to boards/u-blox/ubx_evkannab1/board.cmake diff --git a/boards/u-blox/ubx_evkannab1/board.yml b/boards/u-blox/ubx_evkannab1/board.yml new file mode 100644 index 00000000000..3aeac881aba --- /dev/null +++ b/boards/u-blox/ubx_evkannab1/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_evkannab1 + vendor: u-blox + socs: + - name: nrf52832 diff --git a/boards/arm/ubx_evkannab1_nrf52832/doc/img/EVK-ANNA-B112.jpg b/boards/u-blox/ubx_evkannab1/doc/img/EVK-ANNA-B112.jpg similarity index 100% rename from boards/arm/ubx_evkannab1_nrf52832/doc/img/EVK-ANNA-B112.jpg rename to boards/u-blox/ubx_evkannab1/doc/img/EVK-ANNA-B112.jpg diff --git a/boards/u-blox/ubx_evkannab1/doc/index.rst b/boards/u-blox/ubx_evkannab1/doc/index.rst new file mode 100644 index 00000000000..88ed4f55113 --- /dev/null +++ b/boards/u-blox/ubx_evkannab1/doc/index.rst @@ -0,0 +1,169 @@ +.. _ubx_evkannab1_nrf52832: + +u-blox EVK-ANNA-B11x +#################### + +Overview +******** + +The u-blox ANNA-B1 Evaluation Kit hardware is a Bluetooth low energy +module based on the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU +and has support for the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/EVK-ANNA-B112.jpg + + EVK ANNA-B1 + +More information about the ANNA-B1 module and the EVK-ANNA-B1 +can be found at `ANNA-B1 product page`_ and +`EVK-ANNA-B1 product page`_. + +Supported Features +================== + +The ubx_evkannab1_nrf52832 board configuration supports the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth Low Energy | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `EVK-ANNA-B1 product page`_ and `ANNA-B1 Data Sheet`_ +for a complete list of EVK ANNA-B1 hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.27 +* LED1 (green) = P0.25 +* LED2 (blue) = P0.26 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.25 +* BUTTON2 = SW2 = P0.24 + +General information on module pin numbering +------------------------------------------- + +The numbering of the pins on the module and EVK do not follow the GPIO +numbering on the nRF52832 SoC. Please see the `ANNA-B1 Data Sheet`_ for +information on how to map ANNA-B1 pins to the pin numbering on the +nRF52832 SoC. + +The reason for this is the u-blox module family concept where different +modules share the same pinout and can be interchanged. + +Programming and Debugging +************************* + +Applications for the ``ubx_evkannab1/nrf52832`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); however, the standard +debugging targets are not currently available. + +Flashing +======== + +Build and flash applications as usual (see +:ref:`build_an_application` and :ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +Open a terminal program to the USB Serial Port installed when connecting +the board and listen for output. + +Settings: 115200, 8N1, no flow control. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_evkannab1/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging boards +containing a Nordic Semiconductor chip with a Segger IC. + + +Testing the LEDs and buttons in the EVK NINA-B11x +************************************************* + +There are 2 samples that allow you to test that the buttons (switches) +and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found in +:zephyr_file:`boards/ublox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts`. + +Note that the buttons on the EVK-ANNA-B1 are marked SW1 and SW2, which +are named sw0 and sw1 in the dts file. +Also note that the SW1 button and the green LED are connected on HW level. + + +References +********** + +.. target-notes:: + +.. _ANNA-B1 product page: https://www.u-blox.com/en/product/anna-b112-open-cpu +.. _EVK-ANNA-B1 product page: https://www.u-blox.com/en/product/evk-anna-b112 +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _ANNA-B1 Data Sheet: https://www.u-blox.com/en/docs/UBX-18011707 diff --git a/boards/arm/ubx_bmd380eval_nrf52840/pre_dt_board.cmake b/boards/u-blox/ubx_evkannab1/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/pre_dt_board.cmake rename to boards/u-blox/ubx_evkannab1/pre_dt_board.cmake diff --git a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832-pinctrl.dtsi b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832-pinctrl.dtsi rename to boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832-pinctrl.dtsi diff --git a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.dts b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts similarity index 100% rename from boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.dts rename to boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts diff --git a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.yaml b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.yaml similarity index 88% rename from boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.yaml rename to boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.yaml index 39de6903d44..54af92298d8 100644 --- a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.yaml +++ b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: ubx_evkannab1_nrf52832 +identifier: ubx_evkannab1/nrf52832 name: UBX-EVKANNAB1-NRF52832 type: mcu arch: arm diff --git a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832_defconfig b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832_defconfig similarity index 79% rename from boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832_defconfig rename to boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832_defconfig index 95f9f59739f..5b7bfe0d28c 100644 --- a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832_defconfig +++ b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_UBX_EVKANNAB1_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_evkninab1/Kconfig b/boards/u-blox/ubx_evkninab1/Kconfig new file mode 100644 index 00000000000..280d583f721 --- /dev/null +++ b/boards/u-blox/ubx_evkninab1/Kconfig @@ -0,0 +1,10 @@ +# u-blox EVK NINA-B1 board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_EVKNINAB1 diff --git a/boards/u-blox/ubx_evkninab1/Kconfig.defconfig b/boards/u-blox/ubx_evkninab1/Kconfig.defconfig new file mode 100644 index 00000000000..5f897eb6bb1 --- /dev/null +++ b/boards/u-blox/ubx_evkninab1/Kconfig.defconfig @@ -0,0 +1,11 @@ +# u-blox EVK-NINA-B1 board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_EVKNINAB1 + +config BT_CTLR + default BT + +endif # BOARD_UBX_EVKNINAB1 diff --git a/boards/u-blox/ubx_evkninab1/Kconfig.ubx_evkninab1 b/boards/u-blox/ubx_evkninab1/Kconfig.ubx_evkninab1 new file mode 100644 index 00000000000..b221d0a7d22 --- /dev/null +++ b/boards/u-blox/ubx_evkninab1/Kconfig.ubx_evkninab1 @@ -0,0 +1,7 @@ +# u-blox EVK-NINA-B1 board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_EVKNINAB1 + select SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_evkninab1_nrf52832/board.cmake b/boards/u-blox/ubx_evkninab1/board.cmake similarity index 100% rename from boards/arm/ubx_evkninab1_nrf52832/board.cmake rename to boards/u-blox/ubx_evkninab1/board.cmake diff --git a/boards/u-blox/ubx_evkninab1/board.yml b/boards/u-blox/ubx_evkninab1/board.yml new file mode 100644 index 00000000000..3073c5833d2 --- /dev/null +++ b/boards/u-blox/ubx_evkninab1/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_evkninab1 + vendor: u-blox + socs: + - name: nrf52832 diff --git a/boards/arm/ubx_evkninab1_nrf52832/doc/img/EVK-NINA-B1.jpg b/boards/u-blox/ubx_evkninab1/doc/img/EVK-NINA-B1.jpg similarity index 100% rename from boards/arm/ubx_evkninab1_nrf52832/doc/img/EVK-NINA-B1.jpg rename to boards/u-blox/ubx_evkninab1/doc/img/EVK-NINA-B1.jpg diff --git a/boards/u-blox/ubx_evkninab1/doc/index.rst b/boards/u-blox/ubx_evkninab1/doc/index.rst new file mode 100644 index 00000000000..9b296624ad8 --- /dev/null +++ b/boards/u-blox/ubx_evkninab1/doc/index.rst @@ -0,0 +1,178 @@ +.. _ubx_evkninab1_nrf52832: + +u-blox EVK NINA-B11x +#################### + +Overview +******** + +The u-blox NINA-B1 Evaluation Kit hardware is a Bluetooth +low energy module based on the Nordic Semiconductor nRF52832 +ARM Cortex-M4F CPU and has support for the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/EVK-NINA-B1.jpg + + EVK NINA-B1 + +More information about the NINA-B1 module and the EVK NINA-B1 +can be found at `NINA-B1 product page`_ and +`EVK-NINA-B1 product page`_. + +Supported Features +================== + +The ubx_evkninab1/nrf52832 board configuration supports the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth Low Energy | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +.. note:: + Most Arduino interfaces are supported. Arduino pins + D5 and D8 are not available, so arduino_gpio is + disabled. On the EVK-NINA-B1, these pins are + assigned to SWDIO and SWDCLK, respectively. + +Other hardware features have not been enabled yet for this board. +See `EVK-NINA-B1 product page`_ and `NINA-B1 Data Sheet`_ +for a complete list of EVK NINA-B1 hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.08 +* LED1 (green) = P0.16 +* LED2 (blue) = P0.18 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.16 +* BUTTON2 = SW2 = P0.30 + + +General information on module pin numbering +------------------------------------------- + +The numbering of the pins on the module and EVK do not follow the GPIO +numbering on the nRF52832 SoC. Please see the `NINA-B1 Data Sheet`_ for +information on how to map NINA-B1 pins to the pin numbering on the +nRF52832 SoC. + +The reason for this is the u-blox module family concept where different +modules share the same pinout and can be interchanged, see +`NINA module family Nested design`_. + +Programming and Debugging +************************* + +Applications for the ``ubx_evkninab1/nrf52832`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); however, the standard +debugging targets are not currently available. + +Flashing +======== + +Build and flash applications as usual (see +:ref:`build_an_application` and :ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +Open a terminal program to the USB Serial Port installed when connecting +the board and listen for output. + +Settings: 115200, 8N1, no flow control. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_evkninab1/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging boards +containing a Nordic Semiconductor chip with a Segger IC. + + +Testing the LEDs and buttons in the EVK NINA-B11x +************************************************* + +There are 2 samples that allow you to test that the buttons (switches) +and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found in +:zephyr_file:`boards/ublox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts`. + +Note that the buttons on the EVK-NINA-B1 are marked SW1 and SW2, which +are named sw0 and sw1 in the dts file. +Also note that the SW1 button and the green LED are connected on HW level. + + +References +********** + +.. target-notes:: + +.. _NINA-B1 product page: https://www.u-blox.com/en/product/nina-b1-series-open-cpu +.. _EVK-NINA-B1 product page: https://www.u-blox.com/en/product/evk-nina-b1 +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _NINA-B1 Data Sheet: https://www.u-blox.com/en/docs/UBX-15019243 +.. _NINA module family Nested design: https://www.u-blox.com/en/docs/UBX-17065600 diff --git a/boards/arm/ubx_evkannab1_nrf52832/pre_dt_board.cmake b/boards/u-blox/ubx_evkninab1/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_evkannab1_nrf52832/pre_dt_board.cmake rename to boards/u-blox/ubx_evkninab1/pre_dt_board.cmake diff --git a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832-pinctrl.dtsi b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832-pinctrl.dtsi rename to boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832-pinctrl.dtsi diff --git a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.dts b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts similarity index 100% rename from boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.dts rename to boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts diff --git a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.yaml b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.yaml similarity index 87% rename from boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.yaml rename to boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.yaml index 125efd94a1c..286e66b97cb 100644 --- a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.yaml +++ b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: ubx_evkninab1_nrf52832 +identifier: ubx_evkninab1/nrf52832 name: UBX-EVKNINAB1-NRF52832 type: mcu arch: arm diff --git a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832_defconfig b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832_defconfig similarity index 79% rename from boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832_defconfig rename to boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832_defconfig index c23f9eb7833..9696c89e3d7 100644 --- a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832_defconfig +++ b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_UBX_EVKNINAB1_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_evkninab3/Kconfig b/boards/u-blox/ubx_evkninab3/Kconfig new file mode 100644 index 00000000000..acf0948c5d5 --- /dev/null +++ b/boards/u-blox/ubx_evkninab3/Kconfig @@ -0,0 +1,10 @@ +# EVK-NINA-B3 board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_EVKNINAB3 diff --git a/boards/u-blox/ubx_evkninab3/Kconfig.defconfig b/boards/u-blox/ubx_evkninab3/Kconfig.defconfig new file mode 100644 index 00000000000..2579b835428 --- /dev/null +++ b/boards/u-blox/ubx_evkninab3/Kconfig.defconfig @@ -0,0 +1,11 @@ +# EVK-NINA-B3 board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_EVKNINAB3 + +config BT_CTLR + default BT + +endif # BOARD_UBX_EVKNINAB3 diff --git a/boards/u-blox/ubx_evkninab3/Kconfig.ubx_evkninab3 b/boards/u-blox/ubx_evkninab3/Kconfig.ubx_evkninab3 new file mode 100644 index 00000000000..a9780204794 --- /dev/null +++ b/boards/u-blox/ubx_evkninab3/Kconfig.ubx_evkninab3 @@ -0,0 +1,7 @@ +# EVK-NINA-B3 board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_EVKNINAB3 + select SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_evkninab3_nrf52840/board.cmake b/boards/u-blox/ubx_evkninab3/board.cmake similarity index 100% rename from boards/arm/ubx_evkninab3_nrf52840/board.cmake rename to boards/u-blox/ubx_evkninab3/board.cmake diff --git a/boards/u-blox/ubx_evkninab3/board.yml b/boards/u-blox/ubx_evkninab3/board.yml new file mode 100644 index 00000000000..3914fd28149 --- /dev/null +++ b/boards/u-blox/ubx_evkninab3/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_evkninab3 + vendor: u-blox + socs: + - name: nrf52840 diff --git a/boards/arm/ubx_evkninab3_nrf52840/doc/img/EVK-NINA-B3.jpg b/boards/u-blox/ubx_evkninab3/doc/img/EVK-NINA-B3.jpg similarity index 100% rename from boards/arm/ubx_evkninab3_nrf52840/doc/img/EVK-NINA-B3.jpg rename to boards/u-blox/ubx_evkninab3/doc/img/EVK-NINA-B3.jpg diff --git a/boards/u-blox/ubx_evkninab3/doc/index.rst b/boards/u-blox/ubx_evkninab3/doc/index.rst new file mode 100644 index 00000000000..941c58eccd0 --- /dev/null +++ b/boards/u-blox/ubx_evkninab3/doc/index.rst @@ -0,0 +1,328 @@ +.. _ubx_ninab3_nrf52840: + +u-blox EVK-NINA-B3 +################## + +Overview +******** + +The u-blox EVK-NINA-B30 Development Kit hardware provides support for the +u-blox NINA-B30x Bluetooth 5.0 module, based on the Nordic Semiconductor +nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/EVK-NINA-B3.jpg + :align: center + :alt: EVK-NINA-B3 + + EVK-NINA-B3 (Credit: u-blox AG) + +More information about the EVK-NINA-B3 and the NINA-B30x modules +can be found at the `u-blox website`_. + +Hardware +******** + +The NINA-B30x on the EVK-NINA-B30x contains an internal high-frequency +oscillator at 32MHz as well as a low frequency (slow) oscillator +of 32.768kHz. + + +Supported Features +================== + +The ubx_evkninab3/nrf52840 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | IEEE 802.15.4 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of EVK-NINA-B30x +hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.13 +* LED1 (green) = P0.25 +* LED2 (blue) = P1.00 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.25 +* BUTTON2 = SW2 = P0.2 +* BOOT = SW0 = boot/reset + +External Connectors +------------------- + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the EVK-NINA-B30x + for each header + + +Arduino Headers +--------------- + +Power (J1) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NINA-B30x Functions | ++=======+==============+=========================+ +| 1 | N/C | N/A | ++-------+--------------+-------------------------+ +| 2 | VDD_IO | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.18 / RESET | ++-------+--------------+-------------------------+ +| 4 | 3V3 | N/A | ++-------+--------------+-------------------------+ +| 5 | 5V0 | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | VIN | N/A | ++-------+--------------+-------------------------+ + +Analog in (J2) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NINA-B30x Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.05 / AIN3 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ + +Digital I/O (J3) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NINA-B30x Functions | ++=======+==============+=========================+ +| 8 | D7 | P0.10 | ++-------+--------------+-------------------------+ +| 7 | D6 | P0.09 | ++-------+--------------+-------------------------+ +| 6 | D5 | P0.11 | ++-------+--------------+-------------------------+ +| 5 | D4 | P0.13 | ++-------+--------------+-------------------------+ +| 4 | D3 | P0.31 | ++-------+--------------+-------------------------+ +| 3 | D2 | P1.12 | ++-------+--------------+-------------------------+ +| 2 | D1 (TX) | P1.13 | ++-------+--------------+-------------------------+ +| 1 | D0 (RX) | P0.29 | ++-------+--------------+-------------------------+ + +Digital I/O (J4) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NINA-B30x Functions | ++=======+==============+=========================+ +| 10 | SCL | P0.24 | ++-------+--------------+-------------------------+ +| 9 | SDA | P0.16 | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 6 | D13 (SCK) | P0.07 | ++-------+--------------+-------------------------+ +| 5 | D12 (MISO) | P1.00 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.15 | ++-------+--------------+-------------------------+ +| 3 | D10 (SS) | P0.14 | ++-------+--------------+-------------------------+ +| 2 | D9 | P0.12 | ++-------+--------------+-------------------------+ +| 1 | D8 | P1.09 | ++-------+--------------+-------------------------+ + + +Programming and Debugging +************************* + +Applications for the ``ubx_evkninab3/nrf52840`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); however, the standard +debugging targets are not currently available. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the EVK-NINA-B30x +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_evkninab3/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the EVK-NINA-B30x +************************************************* + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/ublox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts`. + +Using UART1 +*********** + +The following approach can be used when an application needs to use +more than one UART for connecting peripheral devices: + +1. Add device tree overlay file to the main directory of your application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX + +2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` + +Overlay file naming +=================== + +The file has to be named ``.overlay`` and placed in the app main directory to be +picked up automatically by the device tree compiler. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the data sheet for the NINA-B3 at `u-blox website`_, Section 3 'Pin definition'. +In the table 7 select the pins marked 'GPIO_xx'. Note that pins marked as 'Radio sensitive pin' +can only be used in under-10KHz applications. They are not suitable for 115200 speed of UART. + +.. note: + Pins are defined according to the "nRF52" pin number, not the module pad number. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/en/product/nina-b3-series-open-cpu diff --git a/boards/arm/ubx_evkninab1_nrf52832/pre_dt_board.cmake b/boards/u-blox/ubx_evkninab3/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_evkninab1_nrf52832/pre_dt_board.cmake rename to boards/u-blox/ubx_evkninab3/pre_dt_board.cmake diff --git a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840-pinctrl.dtsi b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840-pinctrl.dtsi rename to boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840-pinctrl.dtsi diff --git a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.dts b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts similarity index 100% rename from boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.dts rename to boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts diff --git a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.yaml b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml similarity index 89% rename from boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.yaml rename to boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml index 34590896e55..90d292bc049 100644 --- a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.yaml +++ b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: ubx_evkninab3_nrf52840 +identifier: ubx_evkninab3/nrf52840 name: UBX-EVKNINAB3-NRF52840 type: mcu arch: arm diff --git a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840_defconfig b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840_defconfig similarity index 79% rename from boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840_defconfig rename to boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840_defconfig index 9ccc843efb0..aec93a8b1bc 100644 --- a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840_defconfig +++ b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_UBX_EVKNINAB3_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_evkninab4/Kconfig b/boards/u-blox/ubx_evkninab4/Kconfig new file mode 100644 index 00000000000..b9ef2c7aea6 --- /dev/null +++ b/boards/u-blox/ubx_evkninab4/Kconfig @@ -0,0 +1,10 @@ +# NINA-B4 EVK board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_EVKNINAB4 diff --git a/boards/u-blox/ubx_evkninab4/Kconfig.defconfig b/boards/u-blox/ubx_evkninab4/Kconfig.defconfig new file mode 100644 index 00000000000..c9e958708bf --- /dev/null +++ b/boards/u-blox/ubx_evkninab4/Kconfig.defconfig @@ -0,0 +1,11 @@ +# EVK-NINA-B4 board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_EVKNINAB4 + +config BT_CTLR + default BT + +endif # BOARD_UBX_EVKNINAB4 diff --git a/boards/u-blox/ubx_evkninab4/Kconfig.ubx_evkninab4 b/boards/u-blox/ubx_evkninab4/Kconfig.ubx_evkninab4 new file mode 100644 index 00000000000..f93b20c48dc --- /dev/null +++ b/boards/u-blox/ubx_evkninab4/Kconfig.ubx_evkninab4 @@ -0,0 +1,7 @@ +# NINA-B4 EVK board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_EVKNINAB4 + select SOC_NRF52833_QIAA diff --git a/boards/arm/ubx_evkninab4_nrf52833/board.cmake b/boards/u-blox/ubx_evkninab4/board.cmake similarity index 100% rename from boards/arm/ubx_evkninab4_nrf52833/board.cmake rename to boards/u-blox/ubx_evkninab4/board.cmake diff --git a/boards/u-blox/ubx_evkninab4/board.yml b/boards/u-blox/ubx_evkninab4/board.yml new file mode 100644 index 00000000000..787ae9c4cdf --- /dev/null +++ b/boards/u-blox/ubx_evkninab4/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_evkninab4 + vendor: u-blox + socs: + - name: nrf52833 diff --git a/boards/arm/ubx_evkninab4_nrf52833/doc/img/EVK-NINA-B406_Top_web.jpg b/boards/u-blox/ubx_evkninab4/doc/img/EVK-NINA-B406_Top_web.jpg similarity index 100% rename from boards/arm/ubx_evkninab4_nrf52833/doc/img/EVK-NINA-B406_Top_web.jpg rename to boards/u-blox/ubx_evkninab4/doc/img/EVK-NINA-B406_Top_web.jpg diff --git a/boards/u-blox/ubx_evkninab4/doc/index.rst b/boards/u-blox/ubx_evkninab4/doc/index.rst new file mode 100644 index 00000000000..872b778b7e3 --- /dev/null +++ b/boards/u-blox/ubx_evkninab4/doc/index.rst @@ -0,0 +1,230 @@ +.. _ubx_ninab4_nrf52833: + +u-blox EVK NINA-B40x +#################### + +Overview +******** + +The u-blox NINA-B4 Evaluation Kit hardware is a Bluetooth low energy +module based on the Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU +and has support for the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/EVK-NINA-B406_Top_web.jpg + + EVK NINA-B4 + +More information about the NINA-B4 module and the EVK-NINA-B4 can be +found at `NINA-B40 product page`_ and `EVK-NINA-B4 product page`_. + +Supported Features +================== + +The ubx_evkninab4/nrf52833 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth low energy | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `EVK-NINA-B4 product page`_ and `NINA-B40 Data Sheet`_ +for a complete list of EVK NINA-B4 hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.13 +* LED1 (green) = P1.01 +* LED2 (blue) = P1.00 + +Push buttons +------------ + +* BUTTON1 = SW1 = P1.01 (Shared with green LED) +* BUTTON2 = SW2 = P0.02 + +General information on module pin numbering +------------------------------------------- + +The numbering of the pins on the module and EVK do not follow the GPIO +numbering on the nRF52833 SoC. Please see the `NINA-B40 Data Sheet`_ for +information on how to map NINA-B40 pins to the pin numbering on the +nRF52833 SoC. + +The reason for this is the u-blox module family concept where different +modules share the same pinout and can be interchanged, see +`NINA module family Nested design`_. + +Programming and Debugging +************************* + +Applications for the ``ubx_evkninab4/nrf52833`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); however, the standard +debugging targets are not currently available. + +Flashing +======== + +Build and flash applications as usual (see +:ref:`build_an_application` and :ref:`application_run` for more details) + +Here is an example for the :ref:`hello_world` application. + +Open a terminal program to the USB Serial Port installed when connecting +the board and listen for output. + +Settings: 115200, 8N1, no flow control. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_evkninab4/nrf52833 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging boards +containing a Nordic Semiconductor chip with a Segger IC. + + +Testing the LEDs and buttons in the EVK NINA-B40x +************************************************* + +There are 2 samples that allow you to test that the buttons (switches) +and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found in +:zephyr_file:`boards/ublox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts`. + +Note that the buttons on the EVK-NINA-B4 are marked SW1 and SW2, which +are named sw0 and sw1 in the dts file. +Also note that the SW1 button and the green LED are connected on HW level. + +Using UART1 +*********** + +The following approach can be used when an application needs to use +more than one UART for connecting peripheral devices: + +1. Add device tree overlay file to the main directory of your application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX + +2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` + +Overlay file naming +=================== + +The file has to be named ``.overlay`` and placed in the app main directory to be +picked up automatically by the device tree compiler. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the data sheet for the NINA-B4 at `NINA-B40 Data Sheet`_, Section 3 'Pin definition'. +In the table 7 select the pins marked 'GPIO_xx'. Note that pins marked as 'Radio sensitive pin' +can only be used in under-10KHz applications. They are not suitable for 115200 speed of UART. + +.. note: + Pins are defined according to the "nRF52" pin number, not the module pad number. + + +References +********** + +.. target-notes:: + +.. _NINA-B40 product page: https://www.u-blox.com/en/product/nina-b40-series-open-cpu +.. _EVK-NINA-B4 product page: https://www.u-blox.com/en/product/evk-nina-b4 +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _NINA-B40 Data Sheet: https://www.u-blox.com/en/docs/UBX-19049405 +.. _NINA module family Nested design: https://www.u-blox.com/en/docs/UBX-17065600 diff --git a/boards/arm/ubx_evkninab3_nrf52840/pre_dt_board.cmake b/boards/u-blox/ubx_evkninab4/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_evkninab3_nrf52840/pre_dt_board.cmake rename to boards/u-blox/ubx_evkninab4/pre_dt_board.cmake diff --git a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833-pinctrl.dtsi b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833-pinctrl.dtsi rename to boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833-pinctrl.dtsi diff --git a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.dts b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts similarity index 100% rename from boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.dts rename to boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts diff --git a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.yaml b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.yaml similarity index 87% rename from boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.yaml rename to boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.yaml index 4134fe918c8..f7f8cb355a9 100644 --- a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.yaml +++ b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.yaml @@ -1,4 +1,4 @@ -identifier: ubx_evkninab4_nrf52833 +identifier: ubx_evkninab4/nrf52833 name: EVK-NINA-B4-NRF52833 type: mcu arch: arm diff --git a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833_defconfig b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833_defconfig similarity index 79% rename from boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833_defconfig rename to boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833_defconfig index 80995445718..b1318ad37dc 100644 --- a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833_defconfig +++ b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_UBX_EVKNINAB4_NRF52833=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/udoo/index.rst b/boards/udoo/index.rst new file mode 100644 index 00000000000..aac4e7f711a --- /dev/null +++ b/boards/udoo/index.rst @@ -0,0 +1,10 @@ +.. _boards-udoo: + +UDOO +#### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/udoo/udoo_neo_full/Kconfig.udoo_neo_full b/boards/udoo/udoo_neo_full/Kconfig.udoo_neo_full new file mode 100644 index 00000000000..e0e9d50bd17 --- /dev/null +++ b/boards/udoo/udoo_neo_full/Kconfig.udoo_neo_full @@ -0,0 +1,6 @@ +# Copyright 2018,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UDOO_NEO_FULL + select SOC_PART_NUMBER_MCIMX6X4EVM10AB + select SOC_MCIMX6X_M4 if BOARD_UDOO_NEO_FULL_MCIMX6X_M4 diff --git a/boards/arm/udoo_neo_full_m4/board.cmake b/boards/udoo/udoo_neo_full/board.cmake similarity index 100% rename from boards/arm/udoo_neo_full_m4/board.cmake rename to boards/udoo/udoo_neo_full/board.cmake diff --git a/boards/udoo/udoo_neo_full/board.yml b/boards/udoo/udoo_neo_full/board.yml new file mode 100644 index 00000000000..1c20ebdc15f --- /dev/null +++ b/boards/udoo/udoo_neo_full/board.yml @@ -0,0 +1,5 @@ +board: + name: udoo_neo_full + vendor: udoo + socs: + - name: mcimx6x diff --git a/boards/udoo/udoo_neo_full/doc/index.rst b/boards/udoo/udoo_neo_full/doc/index.rst new file mode 100644 index 00000000000..945c1dcee4a --- /dev/null +++ b/boards/udoo/udoo_neo_full/doc/index.rst @@ -0,0 +1,368 @@ +.. _udoo_neo_full: + +UDOO Neo Full +############# + +Overview +******** + +UDOO Neo Full is an open source Arduino Uno compatible single board computer. +It is equipped with an NXP |reg| i.MX 6SoloX hybrid multicore processor +composed of one ARM |reg| Cortex-A9 core running up to 1 GHz and one Cortex-M4 +core running up to 227 MHz for high CPU performance and real-time response. +Zephyr was ported to run on the Cortex-M4 core only. In a future release, it +will also communicate with the Cortex-A9 core (running Linux) via OpenAMP. + +.. figure:: udoo_neo_full_mcimx6x_m4.jpg + :align: center + :alt: UDOO-Neo-Full + + UDOO Neo Full (Credit: udoo.org) + +Hardware +******** + +- MCIMX6X MCU with a single Cortex-A9 (1 GHz) core and single Cortex-M4 (227 MHz) core + +- Memory + + - 1 GB RAM + - 128 KB OCRAM + - 256 KB L2 cache (can be switched into OCRAM instead) + - 16 KB OCRAM_S + - 32 KB TCML + - 32 KB TCMU + - 32 KB CAAM (secure RAM) + +- A9 Boot Devices + + - NOR flash + - NAND flash + - OneNAND flash + - SD/MMC + - Serial (I2C/SPI) NOR flash and EEPROM + - QuadSPI (QSPI) flash + +- Display + + - Micro HDMI connector + - LVDS display connector + - Touch (I2C signals) + +- Multimedia + + - Integrated 2d/3d graphics controller + - 8-bit parallel interface for analog camera supporting NTSC and PAL + - HDMI audio transmitter + - S/PDIF + - I2S + +- Connectivity + + - USB 2.0 Type A port + - USB OTG (micro-AB connector) + - 10/100 Mbit/s Ethernet PHY + - Wi-Fi 802.11 b/g/n + - Bluetooth 4.0 Low Energy + - 3x UART ports + - 2x CAN Bus interfaces + - 8x PWM signals + - 3x I2C interface + - 1x SPI interface + - 6x multiplexable signals + - 32x GPIO (A9) + - 22x GPIO (M4) + +- Other + + - MicroSD card slot (8-bit SDIO interface) + - Power status LED (green) + - 2x user LED (red and orange) + +- Power + + - 5 V DC Micro USB + - 6-15 V DC jack + - RTC battery connector + +- Debug + + - pads for soldering of JTAG 14-pin connector + +- Sensor + + - 3-Axis Accelerometer + - 3-Axis Magnetometer + - 3-Axis Digital Gyroscope + - 1x Sensor Snap-In I2C connector + +- Expansion port + + - Arduino interface + +For more information about the MCIMX6X SoC and UDOO Neo Full board, +see these references: + +- `NXP i.MX 6SoloX Website`_ +- `NXP i.MX 6SoloX Datasheet`_ +- `NXP i.MX 6SoloX Reference Manual`_ +- `UDOO Neo Website`_ +- `UDOO Neo Getting Started`_ +- `UDOO Neo Documentation`_ +- `UDOO Neo Datasheet`_ +- `UDOO Neo Schematics`_ + +Supported Features +================== + +The UDOO Neo Full board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | general purpose input/output | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The UDOO Neo Full board was tested with the following pinmux +controller configuration. + ++---------------+-----------------+---------------------------+ +| Board Name | SoC Name | Usage | ++===============+=================+===========================+ +| J4 RX | UART5_RX_DATA | UART Console | ++---------------+-----------------+---------------------------+ +| J4 TX | UART5_TX_DATA | UART Console | ++---------------+-----------------+---------------------------+ + +System Clock +============ + +The MCIMX6X SoC is configured to use the 24 MHz external oscillator +on the board with the on-chip PLL to generate core clock. +PLL settings for M4 core are set via code running on the A9 core. + +Serial Port +=========== + +The MCIMX6X SoC has six UARTs. UART5 is configured for the M4 core and the +remaining are used by the A9 core or not used. + +Programming and Debugging +************************* + +The M4 core does not have a flash memory and is not provided a clock +at power-on-reset. Therefore it needs to be started by the A9 core. +The A9 core is responsible to load the M4 binary application into the RAM, +put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get +the M4 out of reset. The A9 can perform these steps at the bootloader level +or after the Linux system has booted. + +The M4 core can use up to 5 different RAMs (some other types of memory like +a secure RAM are not currently implemented in Zephyr). +These are the memory mappings for A9 and M4: + ++------------+-----------------------+-----------------------+-----------------------+ +| Region | Cortex-A9 | Cortex-M4 | Size | ++============+=======================+=======================+=======================+ +| TCML | 0x007F8000-0x007FFFFF | 0x1FFF8000-0x1FFFFFFF | 32 KB | ++------------+-----------------------+-----------------------+-----------------------+ +| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | 32 KB | ++------------+-----------------------+-----------------------+-----------------------+ +| OCRAM_S | 0x008F8000-0x008FBFFF | 0x208F8000-0x208FBFFF | 16 KB | ++------------+-----------------------+-----------------------+-----------------------+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20900000-0x2091FFFF | 128 KB | ++------------+-----------------------+-----------------------+-----------------------+ +| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 2048 MB (1536 for M4) | ++------------+-----------------------+-----------------------+-----------------------+ + +References +========== + +- `NXP i.MX 6SoloX Reference Manual`_ Chapter 2 - Memory Maps + +You have to choose which RAM will be used at compilation time. This configuration +is done in the file :zephyr_file:`boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.dts`. + +If you want to have the code placed in the subregion of a memory, which will +likely be the case when using DDR, select "zephyr,flash=&flash" and set the +DT_FLASH_SIZE macro to determine the region size and DT_FLASH_ADDR to determine +the address where the region begins. + +If you want to have the data placed in the subregion of a memory, which will +likely be the case when using DDR, select "zephyr,sram = &sram", which sets the +CONFIG_SRAM_SIZE macro to determine the region size and +CONFIG_SRAM_BASE_ADDRESS to determine the address where the region begins. + +Otherwise set "zephyr,flash" and/or "zephyr,sram" to one of the predefined +regions: + +.. code-block:: none + + "zephyr,flash" + - &tcml + - &ocram_s + - &ocram + - &ddr + + "zephyr,sram" + - &tcmu + - &ocram_s + - &ocram + - &ddr + +Below you will find the instructions how a Linux user space application running +on the A9 core can be used to load and run Zephyr application on the M4 core. + +The UDOOBuntu Linux distribution contains a `udooneo-m4uploader`_ utility, +but its purpose is to load UDOO Neo "Arduino-like" sketches, so it doesn't +work with Zephyr applications in most cases. The reason is that there is +an exchange of information between this utility and the program running on the +M4 core using hardcoded shared memory locations. The utility writes a flag which +is read by the program running on the M4 core. The program is then supposed to +end safely and write the status to the shared memory location for the main core. +The utility then loads the new application and reads its status from the shared +memory location to determine if it has successfully launched. Since this +functionality is specific for the UDOO Neo "Arduino-like" sketches, it is not +implemented in Zephyr. However Zephyr applications can support it on their own +if planned to be used along with the UDOOBuntu Linux running on the A9 core. +The udooneo-uploader utility calls another executable named +mqx_upload_on_m4SoloX which can be called directly to load Zephyr applications. +Copy the Zephyr binary image into the Linux filesystem and invoke the utility +as a root user: + +.. code-block:: console + + mqx_upload_on_m4SoloX zephyr.bin + +If the output looks like below, the mqx_upload_on_m4SoloX could not read +the status of the stopped application. This is expected if the previously +loaded application is not a UDOO Neo "Arduino-like" sketch and ignores the +shared memory communication: + +.. code-block:: console + + UDOONeo - mqx_upload_on_m4SoloX 1.1.0 + UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 + UDOONeo - Failed to Stop M4 sketch: reboot system ! + +In such situation, the mqx_upload_on_m4SoloX utility has reset the trace flags, +so it will succeed when called again. Then it can have this output below: + +.. code-block:: console + + UDOONeo - mqx_upload_on_m4SoloX 1.1.0 + UDOONeo - FILENAME = zephyr.bin; loadaddr = 0x84000000 + UDOONeo - start - end (0x84000000 - 0x84080000) + UDOONeo - Waiting M4 Run, m4TraceFlags: 000001E0 + UDOONeo - M4 sketch is running + +Or the one below, if the utility cannot read the status flag that the M4 core +applications has started. It can be ignored as the application should be +running, the utility just doesn't know it: + +.. code-block:: console + + UDOONeo - mqx_upload_on_m4SoloX 1.1.0 + UDOONeo - FILENAME = zephyr.bin; loadaddr = 0x84000000 + UDOONeo - start - end (0x84000000 - 0x84080000) + UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 + UDOONeo - Failed to Start M4 sketch: reboot system ! + +The stack pointer and the program counter values are read from the binary. +The memory address where binary will be placed is calculated from the program +counter as its value aligned to 64 KB down, or it can be provided as a second +command line argument: + +.. code-block:: console + + mqx_upload_on_m4SoloX zephyr.bin 0x84000000 + +It is necessary to provide the address if the binary is copied into a memory +region which has different mapping between the A9 and the M4 core. The address +calculated from the stack pointer value in the binary file would be wrong. + +It is possible to modify the mqx_upload_on_m4SoloX utility source code +to not exchange the information with the M4 core application using shared +memory. + +It is also possible to use the `imx-m4fwloader`_ utility to load the M4 core +application. + +One option applicable in UDOOBuntu Linux is to copy the binary file into the +file /var/opt/m4/m4last.fw in the Linux filesystem. The next time the system is +booted, Das U-Boot will load it from there. + +Another option is to directly use Das U-Boot to load the code. + +Debugging +========= + +The UDOO Neo Full board includes pads for soldering the 14-pin JTAG +connector. Zephyr applications running on the M4 core have only been +tested by observing UART console output. + +References +========== + +.. target-notes:: + +.. _UDOO Neo Website: + https://www.udoo.org/udoo-neo/ + +.. _UDOO Neo Getting Started: + https://www.udoo.org/get-started-neo/ + +.. _UDOO Neo Documentation: + https://www.udoo.org/docs-neo + +.. _UDOO Neo Datasheet: + https://www.udoo.org/download/files/datasheets/datasheet_udoo_neo.pdf + +.. _UDOO Neo Schematics: + https://www.udoo.org/download/files/schematics/UDOO_NEO_schematics.pdf + +.. _Udoo Neo Linux or Android Images for the A9 Core: + https://www.udoo.org/downloads/ + +.. _udooneo-m4uploader: + https://github.com/ektor5/udooneo-m4uploader + +.. _imx-m4fwloader: + https://github.com/codeauroraforum/imx-m4fwloader + +.. _NXP i.MX 6SoloX Website: + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-6-processors/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:i.MX6SX + +.. _NXP i.MX 6SoloX Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMX6SXCEC.pdf + +.. _NXP i.MX 6SoloX Reference Manual: + https://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf + +.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: + https://www.nxp.com/docs/en/application-note/AN5317.pdf diff --git a/boards/arm/udoo_neo_full_m4/doc/udoo_neo_full_m4.jpg b/boards/udoo/udoo_neo_full/doc/udoo_neo_full_mcimx6x_m4.jpg similarity index 100% rename from boards/arm/udoo_neo_full_m4/doc/udoo_neo_full_m4.jpg rename to boards/udoo/udoo_neo_full/doc/udoo_neo_full_mcimx6x_m4.jpg diff --git a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4-pinctrl.dtsi b/boards/udoo/udoo_neo_full/udoo_neo_full-pinctrl.dtsi similarity index 100% rename from boards/arm/udoo_neo_full_m4/udoo_neo_full_m4-pinctrl.dtsi rename to boards/udoo/udoo_neo_full/udoo_neo_full-pinctrl.dtsi diff --git a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.dts b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.dts new file mode 100644 index 00000000000..f54b88102cd --- /dev/null +++ b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.dts @@ -0,0 +1,84 @@ +/* + * Copyright 2018,2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/* + * Determines the address and size for code memory which will be applied + * when "zephyr,flash = &flash". Use this to select a custom region, + * usually within DDR. + */ +#define DT_FLASH_SIZE DT_SIZE_K(512) +#define DT_FLASH_ADDR 84000000 /* DT_ADDR will add leading 0x where needed */ + +/* + * Determines the address and size for data memory which will be applied + * when "zephyr,sram = &sram". Use this to select a custom region, + * usually within DDR. + */ +#define DT_SRAM_SIZE DT_SIZE_K(128) +#define DT_SRAM_ADDR 84080000 /* DT_ADDR will add leading 0x where needed */ + +#include +#include "udoo_neo_full-pinctrl.dtsi" + +/ { + model = "UDOO Neo Full board"; + compatible = "nxp,mcmcimx6x_m4"; + + aliases { + led0 = &red_led; + }; + + chosen { + zephyr,flash = &flash; + zephyr,sram = &tcmu; + zephyr,console = &uart5; + zephyr,shell-uart = &uart5; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpio4 6 0>; + label = "User LD1"; + }; + }; +}; + +&uart5 { + status = "okay"; + current-speed = <115200>; + modem-mode = <0>; + pinctrl-0 = <&uart5_default>; + pinctrl-names = "default"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&gpio6 { + status = "okay"; +}; + +&mub { + status = "okay"; +}; + +&epit1 { + status = "okay"; +}; + +&epit2 { + status = "okay"; +}; diff --git a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml new file mode 100644 index 00000000000..4fdd6493309 --- /dev/null +++ b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2018, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: udoo_neo_full/mcimx6x/m4 +name: UDOO Neo Full +type: mcu +arch: arm +ram: 32 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - uart +vendor: nxp diff --git a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig new file mode 100644 index 00000000000..140679e50c3 --- /dev/null +++ b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2018, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=227000000 +CONFIG_PINCTRL=y diff --git a/boards/up/index.rst b/boards/up/index.rst new file mode 100644 index 00000000000..e9397ae5010 --- /dev/null +++ b/boards/up/index.rst @@ -0,0 +1,10 @@ +.. _boards-up: + +UP Bridge the Gap. +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/up/up_squared/CMakeLists.txt b/boards/up/up_squared/CMakeLists.txt new file mode 100644 index 00000000000..ddfd93807ff --- /dev/null +++ b/boards/up/up_squared/CMakeLists.txt @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel Corporation + +zephyr_include_directories(.) + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/up/up_squared/Kconfig.defconfig b/boards/up/up_squared/Kconfig.defconfig new file mode 100644 index 00000000000..78d041976f1 --- /dev/null +++ b/boards/up/up_squared/Kconfig.defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel Corporation + +if BOARD_UP_SQUARED + +config MP_MAX_NUM_CPUS + default 2 if BOARD_UP_SQUARED + +config BUILD_OUTPUT_STRIPPED + default y + +# TSC on this board is 1.5936 GHz, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1593600000 if APIC_TSC_DEADLINE_TIMER + default 1593600000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER +config APIC_TIMER_IRQ + default 24 +config APIC_TIMER_TSC_M + default 3 +config APIC_TIMER_TSC_N + default 249 +endif + +endif # BOARD_UP_SQUARED diff --git a/boards/up/up_squared/Kconfig.up_squared b/boards/up/up_squared/Kconfig.up_squared new file mode 100644 index 00000000000..b6a1427cec7 --- /dev/null +++ b/boards/up/up_squared/Kconfig.up_squared @@ -0,0 +1,5 @@ +# Copyright (c) 2018-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UP_SQUARED + select SOC_APOLLO_LAKE diff --git a/boards/up/up_squared/board.cmake b/boards/up/up_squared/board.cmake new file mode 100644 index 00000000000..896bd4967f0 --- /dev/null +++ b/boards/up/up_squared/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel Corporation + +board_set_flasher_ifnset(misc-flasher) +board_finalize_runner_args(misc-flasher) diff --git a/boards/x86/up_squared/board.h b/boards/up/up_squared/board.h similarity index 100% rename from boards/x86/up_squared/board.h rename to boards/up/up_squared/board.h diff --git a/boards/up/up_squared/board.yml b/boards/up/up_squared/board.yml new file mode 100644 index 00000000000..0955b6967af --- /dev/null +++ b/boards/up/up_squared/board.yml @@ -0,0 +1,4 @@ +board: + name: up_squared + socs: + - name: apollo_lake diff --git a/boards/x86/up_squared/doc/img/up_squared.jpg b/boards/up/up_squared/doc/img/up_squared.jpg similarity index 100% rename from boards/x86/up_squared/doc/img/up_squared.jpg rename to boards/up/up_squared/doc/img/up_squared.jpg diff --git a/boards/up/up_squared/doc/index.rst b/boards/up/up_squared/doc/index.rst new file mode 100644 index 00000000000..62166f2ef38 --- /dev/null +++ b/boards/up/up_squared/doc/index.rst @@ -0,0 +1,125 @@ +.. _up_squared: + +UP Squared +########## + +Overview +******** + +UP |sup2| (UP Squared) is an ultra compact single board computer with high +performance and low power consumption. It features the latest Intel |reg| Apollo +Lake Celeron |trade| and Pentium |trade| Processors with only 4W of Scenario Design Power and +a powerful and flexible Intel |reg| FPGA Altera MAX 10 onboard. + +.. figure:: img/up_squared.jpg + :align: center + :alt: UP Squared + + Up Squared (Credit: https://up-board.org) + +This board configuration enables kernel support for the `UP Squared`_ board. + +.. note:: + This board configuration works on all three variants of `UP Squared`_ + boards containing Intel |reg| Pentium |trade| SoC, + Intel |reg| Celeron |trade| SoC, or Intel |reg| Atom |trade| SoC. + +Hardware +******** + +General information about the board can be found at the `UP Squared`_ website. + +.. include:: ../../../../soc/intel/apollo_lake/doc/supported_features.txt + +GPIO +---- + +GPIOs are exposed through the HAT header, and can be referred using +predefined macros such as ``UP2_HAT_PIN3``. The physical pins are +connected to the on-board FPGA acting as level shifter. Therefore, +to actually utilize these GPIO pins, the function of the pins and +directions (input/output) must be set in the BIOS. This can be +accomplished in BIOS, under menu ``Advanced``, and option +``HAT Configurations``. When a corresponding pin is set to act as +GPIO, there is an option to set the direction of the pin. This needs +to be set accordingly for the GPIO to function properly. + +Connections and IOs +=================== + +Refer to the `UP Squared`_ website and `UP Squared Pinout`_ website +for connection diagrams. + +Programming and Debugging +************************* + +Use the following procedures for booting an image on a UP Squared board. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application on UP Squared: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: up_squared + :goals: build + + .. note:: + + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. + +Booting the UP Squared Board using UEFI +======================================= + +.. include:: ../../../intel/common/efi_boot.rst + :start-after: start_include_here + +.. note:: + Refer to the `UP Squared Serial Console Wiki page + `_ for instructions on how to + connect serial console. + +.. note:: + You can safely ignore this message if it appears: + + .. code-block:: console + + WARNING: no console will be available to OS + +Booting the UP Squared Board over network +========================================= + +.. include:: ../../../intel/common/net_boot.rst + :start-after: start_include_here + +.. note:: + Refer to the `UP Squared Serial Console Wiki page + `_ for instructions on how to + connect serial console. + +.. note:: + To enable PXE boot for Up Squared board do the following: + + #. Enable network from BIOS settings. + + .. code-block:: console + + Advanced -> Network Stack Configuration -> Enable Network Stack -> Enable Ipv4 PXE Support + + #. Make network boot as the first boot option. + + .. code-block:: console + + Boot -> Boot Option #1 : [Network] + +.. _UP Squared: https://www.up-board.org/upsquared/specifications + +.. _UP Squared Pinout: https://wiki.up-community.org/Pinout diff --git a/boards/x86/up_squared/up_squared.dts b/boards/up/up_squared/up_squared.dts similarity index 100% rename from boards/x86/up_squared/up_squared.dts rename to boards/up/up_squared/up_squared.dts diff --git a/boards/x86/up_squared/up_squared.yaml b/boards/up/up_squared/up_squared.yaml similarity index 100% rename from boards/x86/up_squared/up_squared.yaml rename to boards/up/up_squared/up_squared.yaml diff --git a/boards/x86/up_squared/up_squared_defconfig b/boards/up/up_squared/up_squared_defconfig similarity index 83% rename from boards/x86/up_squared/up_squared_defconfig rename to boards/up/up_squared/up_squared_defconfig index d76a6404fab..608e32cdef0 100644 --- a/boards/x86/up_squared/up_squared_defconfig +++ b/boards/up/up_squared/up_squared_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel Corporation -CONFIG_SOC_APOLLO_LAKE=y -CONFIG_BOARD_UP_SQUARED=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/up/up_squared_pro_7000/CMakeLists.txt b/boards/up/up_squared_pro_7000/CMakeLists.txt new file mode 100644 index 00000000000..36ddcdf9d13 --- /dev/null +++ b/boards/up/up_squared_pro_7000/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/up/up_squared_pro_7000/Kconfig.defconfig b/boards/up/up_squared_pro_7000/Kconfig.defconfig new file mode 100644 index 00000000000..84744a7ea3a --- /dev/null +++ b/boards/up/up_squared_pro_7000/Kconfig.defconfig @@ -0,0 +1,64 @@ +# Copyright (c) 2023-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UP_SQUARED_PRO_7000 + +config BUILD_OUTPUT_STRIPPED + default y + +config MP_MAX_NUM_CPUS + default 2 + +# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1900000000 if APIC_TSC_DEADLINE_TIMER + default 1900000000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER + +config APIC_TIMER_IRQ + default 24 +config APIC_TIMER_TSC_M + default 3 +config APIC_TIMER_TSC_N + default 249 +endif + +config ACPI + default y + +if ACPI + +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 64000000 +config MAIN_STACK_SIZE + default 320000 + +if SHELL + +config SHELL_STACK_SIZE + default 320000 +endif # SHELL +endif # ACPI + +if DMA + +config DMA_64BIT + default y + +config DMA_DW_HW_LLI + default n + +config DMA_DW_CHANNEL_COUNT + default 2 + +endif + +config UART_NS16550_INTEL_LPSS_DMA + default y + +config HAS_COVERAGE_SUPPORT + default y + +endif # BOARD_UP_SQUARED_PRO_7000 diff --git a/boards/up/up_squared_pro_7000/Kconfig.up_squared_pro_7000 b/boards/up/up_squared_pro_7000/Kconfig.up_squared_pro_7000 new file mode 100644 index 00000000000..035cc0f888d --- /dev/null +++ b/boards/up/up_squared_pro_7000/Kconfig.up_squared_pro_7000 @@ -0,0 +1,5 @@ +# Copyright (c) 2018-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UP_SQUARED_PRO_7000 + select SOC_ALDER_LAKE diff --git a/boards/x86/up_squared/board.cmake b/boards/up/up_squared_pro_7000/board.cmake similarity index 100% rename from boards/x86/up_squared/board.cmake rename to boards/up/up_squared_pro_7000/board.cmake diff --git a/boards/up/up_squared_pro_7000/board.yml b/boards/up/up_squared_pro_7000/board.yml new file mode 100644 index 00000000000..b929cca9967 --- /dev/null +++ b/boards/up/up_squared_pro_7000/board.yml @@ -0,0 +1,4 @@ +board: + name: up_squared_pro_7000 + socs: + - name: alder_lake diff --git a/boards/x86/intel_adl/doc/up_squared_pro_7000.rst b/boards/up/up_squared_pro_7000/doc/up_squared_pro_7000.rst similarity index 95% rename from boards/x86/intel_adl/doc/up_squared_pro_7000.rst rename to boards/up/up_squared_pro_7000/doc/up_squared_pro_7000.rst index 762340e1049..1b2d6bace7b 100644 --- a/boards/x86/intel_adl/doc/up_squared_pro_7000.rst +++ b/boards/up/up_squared_pro_7000/doc/up_squared_pro_7000.rst @@ -66,13 +66,13 @@ connection setup. Booting the UP Squared Pro 7000 Board using UEFI ================================================ -.. include:: ../../common/efi_boot.rst +.. include:: ../../../intel/common/efi_boot.rst :start-after: start_include_here Booting the UP Squared Pro 7000 Board over network ================================================== -.. include:: ../../common/net_boot.rst +.. include:: ../../../intel/common/net_boot.rst :start-after: start_include_here References diff --git a/boards/x86/intel_adl/up_squared_pro_7000.dts b/boards/up/up_squared_pro_7000/up_squared_pro_7000.dts similarity index 87% rename from boards/x86/intel_adl/up_squared_pro_7000.dts rename to boards/up/up_squared_pro_7000/up_squared_pro_7000.dts index 06d6f8e2330..2b155e22ade 100644 --- a/boards/x86/intel_adl/up_squared_pro_7000.dts +++ b/boards/up/up_squared_pro_7000/up_squared_pro_7000.dts @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "intel_adl.dts" +#include "../../intel/adl/intel_adl.dts" / { model = "UP Squared Pro 7000 board"; diff --git a/boards/x86/intel_adl/up_squared_pro_7000.yaml b/boards/up/up_squared_pro_7000/up_squared_pro_7000.yaml similarity index 100% rename from boards/x86/intel_adl/up_squared_pro_7000.yaml rename to boards/up/up_squared_pro_7000/up_squared_pro_7000.yaml diff --git a/boards/x86/intel_adl/up_squared_pro_7000_defconfig b/boards/up/up_squared_pro_7000/up_squared_pro_7000_defconfig similarity index 79% rename from boards/x86/intel_adl/up_squared_pro_7000_defconfig rename to boards/up/up_squared_pro_7000/up_squared_pro_7000_defconfig index 4c228677a70..fb9be2a4994 100644 --- a/boards/x86/intel_adl/up_squared_pro_7000_defconfig +++ b/boards/up/up_squared_pro_7000/up_squared_pro_7000_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ALDER_LAKE=y -CONFIG_BOARD_UP_SQUARED_PRO_7000=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/vcc-gnd/index.rst b/boards/vcc-gnd/index.rst new file mode 100644 index 00000000000..5a70a862cb9 --- /dev/null +++ b/boards/vcc-gnd/index.rst @@ -0,0 +1,10 @@ +.. _boards-vcc-gnd: + +VCC-GND +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/vcc-gnd/yd_esp32/Kconfig b/boards/vcc-gnd/yd_esp32/Kconfig new file mode 100644 index 00000000000..90193306124 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_YD_ESP32 + select SOC_ESP32_PROCPU if BOARD_YD_ESP32_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_YD_ESP32_ESP32_APPCPU diff --git a/boards/vcc-gnd/yd_esp32/Kconfig.defconfig b/boards/vcc-gnd/yd_esp32/Kconfig.defconfig new file mode 100644 index 00000000000..9b7b408dbef --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/Kconfig.defconfig @@ -0,0 +1,26 @@ +# YD-ESP32 board configuration + +# Copyright (c) 2023 Julio Cesar +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_YD_ESP32_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_YD_ESP32_ESP32_PROCPU + +if BOARD_YD_ESP32_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_YD_ESP32_ESP32_PROCPU diff --git a/boards/vcc-gnd/yd_esp32/Kconfig.sysbuild b/boards/vcc-gnd/yd_esp32/Kconfig.sysbuild new file mode 100644 index 00000000000..3a2d17ac5cf --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/vcc-gnd/yd_esp32/Kconfig.yd_esp32 b/boards/vcc-gnd/yd_esp32/Kconfig.yd_esp32 new file mode 100644 index 00000000000..981d728d09f --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/Kconfig.yd_esp32 @@ -0,0 +1,7 @@ +# YD-ESP32 board configuration + +# Copyright (c) 2023 Julio Cesar +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_YD_ESP32 + select SOC_ESP32_WROOM_32UE_N4 diff --git a/boards/xtensa/xiao_esp32s3/board.cmake b/boards/vcc-gnd/yd_esp32/board.cmake similarity index 100% rename from boards/xtensa/xiao_esp32s3/board.cmake rename to boards/vcc-gnd/yd_esp32/board.cmake diff --git a/boards/vcc-gnd/yd_esp32/board.yml b/boards/vcc-gnd/yd_esp32/board.yml new file mode 100644 index 00000000000..a930386ed84 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/board.yml @@ -0,0 +1,5 @@ +board: + name: yd_esp32 + vendor: vcc-gnd + socs: + - name: esp32 diff --git a/boards/xtensa/yd_esp32/doc/img/yd_esp32.png b/boards/vcc-gnd/yd_esp32/doc/img/yd_esp32.png similarity index 100% rename from boards/xtensa/yd_esp32/doc/img/yd_esp32.png rename to boards/vcc-gnd/yd_esp32/doc/img/yd_esp32.png diff --git a/boards/vcc-gnd/yd_esp32/doc/index.rst b/boards/vcc-gnd/yd_esp32/doc/index.rst new file mode 100644 index 00000000000..e69f7d07704 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/doc/index.rst @@ -0,0 +1,310 @@ +.. _yd_esp32: + +YD-ESP32 +######## + +Overview +******** + +The YD-ESP32 development board is one of VCC-GND® Studio’s official boards. +This board is based on the ESP32-WROOM-32E module, with the ESP32 as the core. + +.. figure:: img/yd_esp32.png + :align: center + :alt: YD-ESP32 + + YD-ESP32 DevKit with ESP32-WROOM-32E Module + +ESP32 +===== + +ESP32 is a series of low cost, low power system on a chip microcontrollers +with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a +Tensilica Xtensa LX6 microprocessor in both dual-core and single-core +variations. ESP32 is created and developed by Espressif Systems, a +Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm +process. [1]_ + +The features include the following: + +- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz +- 520KB of SRAM +- 802.11b/g/n/e/i +- Bluetooth v4.2 BR/EDR and BLE +- Various peripherals: + + - 12-bit ADC with up to 18 channels + - 2x 8-bit DACs + - 10x touch sensors + - Temperature sensor + - 4x SPI + - 2x I2S + - 2x I2C + - 3x UART + - SD/SDIO/MMC host + - Slave (SDIO/SPI) + - Ethernet MAC + - CAN bus 2.0 + - IR (RX/TX) + - Motor PWM + - LED PWM with up to 16 channels + - Hall effect sensor + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) +- 5uA deep sleep current + +Supported Features +================== + +Current Zephyr's YD-ESP32 board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: yd_esp32 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: yd_esp32/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``yd_esp32`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: yd_esp32/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! yd_esp32 + +RGB LED +======= + +The board contains an addressable RGB LED (`XL-5050RGBC-WS2812B`_), driven by GPIO16. +Here is an example of how to test it using the :zephyr:code-sample:`led-ws2812` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/led_ws2812 + :board: yd_esp32/esp32/procpu + :goals: flash + + +.. _`XL-5050RGBC-WS2812B`: http://www.xinglight.cn/index.php?c=show&id=947 + +Debugging +********* + +ESP32 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +On the YD-ESP32 board, the JTAG pins are not run to a +standard connector (e.g. ARM 20-pin) and need to be manually connected +to the external programmer (e.g. a Flyswatter2): + ++------------+-----------+ +| ESP32 pin | JTAG pin | ++============+===========+ +| 3V3 | VTRef | ++------------+-----------+ +| EN | nTRST | ++------------+-----------+ +| IO14 | TMS | ++------------+-----------+ +| IO12 | TDI | ++------------+-----------+ +| GND | GND | ++------------+-----------+ +| IO13 | TCK | ++------------+-----------+ +| IO15 | TDO | ++------------+-----------+ + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: yd_esp32/esp32/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: yd_esp32/esp32/procpu + :goals: debug + +Note on Debugging with GDB Stub +=============================== + +GDB stub is enabled on ESP32. + +* When adding breakpoints, please use hardware breakpoints with command + ``hbreak``. Command ``break`` uses software breakpoints which requires + modifying memory content to insert break/trap instructions. + This does not work as the code is on flash which cannot be randomly + accessed for modification. + +.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html +.. _`OpenOCD`: https://github.com/openocd-org/openocd + +References +********** + +.. [1] https://en.wikipedia.org/wiki/ESP32 +.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf +.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/yd_esp32/support/openocd.cfg b/boards/vcc-gnd/yd_esp32/support/openocd.cfg similarity index 100% rename from boards/xtensa/yd_esp32/support/openocd.cfg rename to boards/vcc-gnd/yd_esp32/support/openocd.cfg diff --git a/boards/xtensa/yd_esp32/yd_esp32-pinctrl.dtsi b/boards/vcc-gnd/yd_esp32/yd_esp32-pinctrl.dtsi similarity index 100% rename from boards/xtensa/yd_esp32/yd_esp32-pinctrl.dtsi rename to boards/vcc-gnd/yd_esp32/yd_esp32-pinctrl.dtsi diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.dts b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.dts new file mode 100644 index 00000000000..6bed6d38402 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "VCC-GND Studio YD-ESP32 APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.yaml b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.yaml new file mode 100644 index 00000000000..018b3c2b727 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: yd_esp32/esp32/appcpu +name: ESP32 DEVKITC WROVER APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu_defconfig b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu_defconfig new file mode 100644 index 00000000000..100bb882567 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.dts b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.dts new file mode 100644 index 00000000000..2e748af71b9 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.dts @@ -0,0 +1,184 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include +#include "yd_esp32-pinctrl.dtsi" +#include + +/ { + model = "VCC-GND Studio YD-ESP32 PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + i2c-0 = &i2c0; + sw0 = &button0; + watchdog0 = &wdt0; + led-strip = &rgb_led; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&pinctrl { + spim2_default: spim2_default { + group2 { + pinmux = ; + output-low; + }; + }; +}; + +&cpu0 { + clock-frequency = ; + cpu-power-states = <&light_sleep &deep_sleep>; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; + + rgb_led: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + + /* SPI */ + reg = <0>; /* ignored, but necessary for SPI bindings */ + spi-max-frequency = <6400000>; + + /* XL-5050RGBC-WS2812B */ + chain-length = <1>; + spi-one-frame = <0xfc>; /* 11111100: 0.937 us high and 0.313 us low */ + spi-zero-frame = <0xc0>; /* 11000000: 0.313 us high and 0.937 us low */ + color-mapping = ; + }; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.yaml b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.yaml new file mode 100644 index 00000000000..b3fc0cdf97d --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.yaml @@ -0,0 +1,24 @@ +identifier: yd_esp32/esp32/procpu +name: YD-ESP32 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - adc + - dac + - gpio + - i2c + - watchdog + - uart + - nvs + - pwm + - dac + - spi + - counter + - entropy +testing: + ignore_tags: + - net + - bluetooth +vendor: vcc-gnd diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu_defconfig b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu_defconfig new file mode 100644 index 00000000000..4fc7d44e085 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Julio Cesar +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/vng/index.rst b/boards/vng/index.rst new file mode 100644 index 00000000000..5d4ab1cecd9 --- /dev/null +++ b/boards/vng/index.rst @@ -0,0 +1,10 @@ +.. _boards-vng: + +VNG Corporation +############### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/vng/nrf51_vbluno51/Kconfig.defconfig b/boards/vng/nrf51_vbluno51/Kconfig.defconfig new file mode 100644 index 00000000000..4957faeb05c --- /dev/null +++ b/boards/vng/nrf51_vbluno51/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF51 VBLUno51 board configuration + +# Copyright (c) 2017 VNG IoT Lab Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF51_VBLUNO51 + +config BT_CTLR + default BT + +endif # BOARD_NRF51_VBLUNO51 diff --git a/boards/vng/nrf51_vbluno51/Kconfig.nrf51_vbluno51 b/boards/vng/nrf51_vbluno51/Kconfig.nrf51_vbluno51 new file mode 100644 index 00000000000..69400c2344c --- /dev/null +++ b/boards/vng/nrf51_vbluno51/Kconfig.nrf51_vbluno51 @@ -0,0 +1,7 @@ +# nRF51-VBLUNO51 board configuration + +# Copyright (c) 2017 VNG IoT Lab Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF51_VBLUNO51 + select SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51_vbluno51/board.cmake b/boards/vng/nrf51_vbluno51/board.cmake similarity index 100% rename from boards/arm/nrf51_vbluno51/board.cmake rename to boards/vng/nrf51_vbluno51/board.cmake diff --git a/boards/vng/nrf51_vbluno51/board.yml b/boards/vng/nrf51_vbluno51/board.yml new file mode 100644 index 00000000000..8e3a9bf9488 --- /dev/null +++ b/boards/vng/nrf51_vbluno51/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf51_vbluno51 + vendor: vngiotlab + socs: + - name: nrf51822 diff --git a/boards/arm/nrf51_vbluno51/doc/img/nrf51_vbluno51.jpg b/boards/vng/nrf51_vbluno51/doc/img/nrf51_vbluno51.jpg similarity index 100% rename from boards/arm/nrf51_vbluno51/doc/img/nrf51_vbluno51.jpg rename to boards/vng/nrf51_vbluno51/doc/img/nrf51_vbluno51.jpg diff --git a/boards/arm/nrf51_vbluno51/doc/img/nrf51_vbluno51_bot.jpg b/boards/vng/nrf51_vbluno51/doc/img/nrf51_vbluno51_bot.jpg similarity index 100% rename from boards/arm/nrf51_vbluno51/doc/img/nrf51_vbluno51_bot.jpg rename to boards/vng/nrf51_vbluno51/doc/img/nrf51_vbluno51_bot.jpg diff --git a/boards/arm/nrf51_vbluno51/doc/img/vbluno51_frizting.jpg b/boards/vng/nrf51_vbluno51/doc/img/vbluno51_frizting.jpg similarity index 100% rename from boards/arm/nrf51_vbluno51/doc/img/vbluno51_frizting.jpg rename to boards/vng/nrf51_vbluno51/doc/img/vbluno51_frizting.jpg diff --git a/boards/arm/nrf51_vbluno51/doc/img/vbluno51_nordic_pinout.jpg b/boards/vng/nrf51_vbluno51/doc/img/vbluno51_nordic_pinout.jpg similarity index 100% rename from boards/arm/nrf51_vbluno51/doc/img/vbluno51_nordic_pinout.jpg rename to boards/vng/nrf51_vbluno51/doc/img/vbluno51_nordic_pinout.jpg diff --git a/boards/arm/nrf51_vbluno51/doc/index.rst b/boards/vng/nrf51_vbluno51/doc/index.rst similarity index 100% rename from boards/arm/nrf51_vbluno51/doc/index.rst rename to boards/vng/nrf51_vbluno51/doc/index.rst diff --git a/boards/arm/nrf51_vbluno51/nrf51_vbluno51-pinctrl.dtsi b/boards/vng/nrf51_vbluno51/nrf51_vbluno51-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf51_vbluno51/nrf51_vbluno51-pinctrl.dtsi rename to boards/vng/nrf51_vbluno51/nrf51_vbluno51-pinctrl.dtsi diff --git a/boards/arm/nrf51_vbluno51/nrf51_vbluno51.dts b/boards/vng/nrf51_vbluno51/nrf51_vbluno51.dts similarity index 100% rename from boards/arm/nrf51_vbluno51/nrf51_vbluno51.dts rename to boards/vng/nrf51_vbluno51/nrf51_vbluno51.dts diff --git a/boards/arm/nrf51_vbluno51/nrf51_vbluno51.yaml b/boards/vng/nrf51_vbluno51/nrf51_vbluno51.yaml similarity index 100% rename from boards/arm/nrf51_vbluno51/nrf51_vbluno51.yaml rename to boards/vng/nrf51_vbluno51/nrf51_vbluno51.yaml diff --git a/boards/vng/nrf51_vbluno51/nrf51_vbluno51_defconfig b/boards/vng/nrf51_vbluno51/nrf51_vbluno51_defconfig new file mode 100644 index 00000000000..1289685e1e8 --- /dev/null +++ b/boards/vng/nrf51_vbluno51/nrf51_vbluno51_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51dongle_nrf51422/pre_dt_board.cmake b/boards/vng/nrf51_vbluno51/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf51dongle_nrf51422/pre_dt_board.cmake rename to boards/vng/nrf51_vbluno51/pre_dt_board.cmake diff --git a/boards/vng/nrf52_vbluno52/Kconfig.defconfig b/boards/vng/nrf52_vbluno52/Kconfig.defconfig new file mode 100644 index 00000000000..700df41dfc6 --- /dev/null +++ b/boards/vng/nrf52_vbluno52/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52 VBLUno52 board configuration + +# Copyright (c) 2017 VNG IoT Lab +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52_VBLUNO52 + +config BT_CTLR + default BT + +endif # BOARD_NRF52_VBLUNO52 diff --git a/boards/vng/nrf52_vbluno52/Kconfig.nrf52_vbluno52 b/boards/vng/nrf52_vbluno52/Kconfig.nrf52_vbluno52 new file mode 100644 index 00000000000..e2d9bec6517 --- /dev/null +++ b/boards/vng/nrf52_vbluno52/Kconfig.nrf52_vbluno52 @@ -0,0 +1,7 @@ +# nRF52 VBLUno52 board configuration +# Copyright (c) 2017 VNG IoT Lab + +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_VBLUNO52 + select SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_vbluno52/board.cmake b/boards/vng/nrf52_vbluno52/board.cmake similarity index 100% rename from boards/arm/nrf52_vbluno52/board.cmake rename to boards/vng/nrf52_vbluno52/board.cmake diff --git a/boards/vng/nrf52_vbluno52/board.yml b/boards/vng/nrf52_vbluno52/board.yml new file mode 100644 index 00000000000..be59c421baa --- /dev/null +++ b/boards/vng/nrf52_vbluno52/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52_vbluno52 + vendor: vngiotlab + socs: + - name: nrf52832 diff --git a/boards/arm/nrf52_vbluno52/doc/img/nrf52_vbluno52.jpg b/boards/vng/nrf52_vbluno52/doc/img/nrf52_vbluno52.jpg similarity index 100% rename from boards/arm/nrf52_vbluno52/doc/img/nrf52_vbluno52.jpg rename to boards/vng/nrf52_vbluno52/doc/img/nrf52_vbluno52.jpg diff --git a/boards/arm/nrf52_vbluno52/doc/index.rst b/boards/vng/nrf52_vbluno52/doc/index.rst similarity index 100% rename from boards/arm/nrf52_vbluno52/doc/index.rst rename to boards/vng/nrf52_vbluno52/doc/index.rst diff --git a/boards/arm/nrf52_vbluno52/nrf52_vbluno52-pinctrl.dtsi b/boards/vng/nrf52_vbluno52/nrf52_vbluno52-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52_vbluno52/nrf52_vbluno52-pinctrl.dtsi rename to boards/vng/nrf52_vbluno52/nrf52_vbluno52-pinctrl.dtsi diff --git a/boards/arm/nrf52_vbluno52/nrf52_vbluno52.dts b/boards/vng/nrf52_vbluno52/nrf52_vbluno52.dts similarity index 100% rename from boards/arm/nrf52_vbluno52/nrf52_vbluno52.dts rename to boards/vng/nrf52_vbluno52/nrf52_vbluno52.dts diff --git a/boards/arm/nrf52_vbluno52/nrf52_vbluno52.yaml b/boards/vng/nrf52_vbluno52/nrf52_vbluno52.yaml similarity index 100% rename from boards/arm/nrf52_vbluno52/nrf52_vbluno52.yaml rename to boards/vng/nrf52_vbluno52/nrf52_vbluno52.yaml diff --git a/boards/vng/nrf52_vbluno52/nrf52_vbluno52_defconfig b/boards/vng/nrf52_vbluno52/nrf52_vbluno52_defconfig new file mode 100644 index 00000000000..7167aca850a --- /dev/null +++ b/boards/vng/nrf52_vbluno52/nrf52_vbluno52_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/ubx_evkninab4_nrf52833/pre_dt_board.cmake b/boards/vng/nrf52_vbluno52/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_evkninab4_nrf52833/pre_dt_board.cmake rename to boards/vng/nrf52_vbluno52/pre_dt_board.cmake diff --git a/boards/waveshare/index.rst b/boards/waveshare/index.rst new file mode 100644 index 00000000000..6acd377cab9 --- /dev/null +++ b/boards/waveshare/index.rst @@ -0,0 +1,10 @@ +.. _boards-waveshare: + +Waveshare Electronics +##################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/waveshare/nrf51_ble400/Kconfig.defconfig b/boards/waveshare/nrf51_ble400/Kconfig.defconfig new file mode 100644 index 00000000000..65d41b852d3 --- /dev/null +++ b/boards/waveshare/nrf51_ble400/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF51 BLE400 board configuration + +# Copyright (c) 2018 Roman Tataurov +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF51_BLE400 + +config BT_CTLR + default BT + +endif # BOARD_NRF51_BLE400 diff --git a/boards/waveshare/nrf51_ble400/Kconfig.nrf51_ble400 b/boards/waveshare/nrf51_ble400/Kconfig.nrf51_ble400 new file mode 100644 index 00000000000..48bb3e49e09 --- /dev/null +++ b/boards/waveshare/nrf51_ble400/Kconfig.nrf51_ble400 @@ -0,0 +1,7 @@ +# nRF51 BLE400 board configuration + +# Copyright (c) 2018 Roman Tataurov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF51_BLE400 + select SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51_ble400/board.cmake b/boards/waveshare/nrf51_ble400/board.cmake similarity index 100% rename from boards/arm/nrf51_ble400/board.cmake rename to boards/waveshare/nrf51_ble400/board.cmake diff --git a/boards/waveshare/nrf51_ble400/board.yml b/boards/waveshare/nrf51_ble400/board.yml new file mode 100644 index 00000000000..d2c7da1f732 --- /dev/null +++ b/boards/waveshare/nrf51_ble400/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf51_ble400 + vendor: waveshare + socs: + - name: nrf51822 diff --git a/boards/arm/nrf51_ble400/doc/img/BLE400-size.jpg b/boards/waveshare/nrf51_ble400/doc/img/BLE400-size.jpg similarity index 100% rename from boards/arm/nrf51_ble400/doc/img/BLE400-size.jpg rename to boards/waveshare/nrf51_ble400/doc/img/BLE400-size.jpg diff --git a/boards/arm/nrf51_ble400/doc/img/Core51822-Compare.jpg b/boards/waveshare/nrf51_ble400/doc/img/Core51822-Compare.jpg similarity index 100% rename from boards/arm/nrf51_ble400/doc/img/Core51822-Compare.jpg rename to boards/waveshare/nrf51_ble400/doc/img/Core51822-Compare.jpg diff --git a/boards/arm/nrf51_ble400/doc/img/Core51822-pin.jpg b/boards/waveshare/nrf51_ble400/doc/img/Core51822-pin.jpg similarity index 100% rename from boards/arm/nrf51_ble400/doc/img/Core51822-pin.jpg rename to boards/waveshare/nrf51_ble400/doc/img/Core51822-pin.jpg diff --git a/boards/arm/nrf51_ble400/doc/img/nrf51_ble400.jpg b/boards/waveshare/nrf51_ble400/doc/img/nrf51_ble400.jpg similarity index 100% rename from boards/arm/nrf51_ble400/doc/img/nrf51_ble400.jpg rename to boards/waveshare/nrf51_ble400/doc/img/nrf51_ble400.jpg diff --git a/boards/waveshare/nrf51_ble400/doc/index.rst b/boards/waveshare/nrf51_ble400/doc/index.rst new file mode 100644 index 00000000000..3bfe06aa204 --- /dev/null +++ b/boards/waveshare/nrf51_ble400/doc/index.rst @@ -0,0 +1,223 @@ +.. _nrf51_ble400: + +Waveshare BLE400 +################# + +Overview +******** + +BLE400 is a motherboard designed for BLE Bluetooth 2.4G Wireless Module. Used together with core board -- Core51822. + +Supported Features +================== + +Motherboard +------------ + +- Onboard battery holder, multi power supplies are available +- All the IOs are accessible for easy expansion +- Integrates CP2102 for debugging +- LEDs and user keys, compatible with other official boards, easy to use + +Core board +---------- + +- Onboard chip: nRF51822 +- Communication distance (open outdoor 1M data rate): 30m +- Frequency range: 2.4GHz +- Operating voltage: 2.0V ~ 3.6V +- Operating temperature: -40℃ ~ 85℃ +- Expansion pinheader: all the I/Os except P0.26 and P0.27 +- Pinheader pitch: 2.00mm +- Antenna: onboard antenna + +Features +======== + +- 2.4 GHz multiprotocol RF transceiver +- ARM® Cortex™-M0 32 bit processor +- 128 bit AES HW encryption +- 256kB flash & 32kB RAM +- Programmable Peripheral Interconnect (PPI) +- Digital interfaces: SPI, I2C, UART +- 10 bit ADC +- Programmable output power: -20 to +4 dBm +- Independent application development and protocol stack +- Fully compatible with NRF24L series +- Pinout compatible with NRF51xxx series +- Global separate power management +- Operating voltage: 1.8 V ~ 3.6 V + +Revision History +================ + +Core board +---------- + +In June of 2015, Core51822 and its variant, Core51822 (B), upgraded the onboard chip to Rev3 (nRF51822_QFAC) that features 32kB RAM. + +.. image:: img/Core51822-Compare.jpg + :align: center + :alt: Compare + +Top: Core51822 +Bottom: Core51822 (B) + +Connections and IOs +==================== + +Motherboard +------------ + +.. image:: img/nrf51_ble400.jpg + :align: center + :alt: BLE400 + +1. Wireless module connector: for easily connecting modules like Core51822 +2. MCU pins expansion connector +3. I2C interface +4. SPI interface +5. 5V/3.3V power input/output: usually used as power output, also common-grounding with other user board +6. USB connector: USB TO UART via onboard converter CP2102 +7. Debugging interface +8. UART interface +9. Battery holder +10. User LEDs +11. User keys +12. Reset button +13. CP2102 +14. USB TO UART jumper +15. LEDs & Keys jumper + +Core board +---------- + +.. image:: img/Core51822-pin.jpg + :align: center + :alt: Core board pinout + +BLE400 dimensions +================= + +.. image:: img/BLE400-size.jpg + :align: center + :alt: BLE400 size + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.18 +* LED1 (red) = P0.19 +* LED2 (red) = P0.20 +* LED3 (red) = P0.21 +* LED4 (red) = P0.22 +* SUSPEND = SUSPEND +* RXD1 = P0.9 +* TXD1 = P0.11 + +Push buttons +------------ + +* KEY1 = P0.16 +* KEY2 = P0.17 +* RESET = SWDIO + +I2C +--- + +* SMBA = P0.02 +* SCL = P0.01 +* SDA = P0.00 + +SPI +--- + +* NSS = P0.30 +* SCK = P0.25 +* MOSI = P0.24 +* MISO = P0.23 + +USART1 +------ + +* RX = P0.05 +* TX = P0.06 +* CTS = P0.07 +* RTS = P0.12 + +UART (USB) +---------- + +* RX = P0.9 +* TX = P0.11 +* CTS = P0.8 +* RTS = P0.10 + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF51 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf51_ble400 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF51 DK +******************************************** + +There are samples below that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +- :zephyr:code-sample:`blinky` +- :zephyr:code-sample:`button` +- :zephyr:code-sample:`fade-led` +- :zephyr:code-sample:`multi-thread-blinky` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/waveshare/nrf51_ble400/nrf51_ble400.dts`. + +References +********** + +.. target-notes:: + +.. _nRF51 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF51-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _Waveshare Wiki BLE400: https://www.waveshare.com/wiki/BLE400 +.. _Waveshare WiKi Core51822: https://www.waveshare.com/wiki/Core51822 +.. _User manual: https://www.waveshare.com/w/upload/b/b7/NRF51822-Eval-Kit-UserManual-EN.pdf +.. _Schematic: https://www.waveshare.com/w/upload/1/1b/BLE400-Schematic.pdf +.. _Code samples: https://www.waveshare.com/w/upload/5/53/NRF51822-Code.7z +.. _Core board schematics: https://www.waveshare.com/w/upload/5/57/Core51822-Schematic.pdf diff --git a/boards/arm/nrf51_ble400/nrf51_ble400-pinctrl.dtsi b/boards/waveshare/nrf51_ble400/nrf51_ble400-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf51_ble400/nrf51_ble400-pinctrl.dtsi rename to boards/waveshare/nrf51_ble400/nrf51_ble400-pinctrl.dtsi diff --git a/boards/arm/nrf51_ble400/nrf51_ble400.dts b/boards/waveshare/nrf51_ble400/nrf51_ble400.dts similarity index 100% rename from boards/arm/nrf51_ble400/nrf51_ble400.dts rename to boards/waveshare/nrf51_ble400/nrf51_ble400.dts diff --git a/boards/arm/nrf51_ble400/nrf51_ble400.yaml b/boards/waveshare/nrf51_ble400/nrf51_ble400.yaml similarity index 100% rename from boards/arm/nrf51_ble400/nrf51_ble400.yaml rename to boards/waveshare/nrf51_ble400/nrf51_ble400.yaml diff --git a/boards/waveshare/nrf51_ble400/nrf51_ble400_defconfig b/boards/waveshare/nrf51_ble400/nrf51_ble400_defconfig new file mode 100644 index 00000000000..1289685e1e8 --- /dev/null +++ b/boards/waveshare/nrf51_ble400/nrf51_ble400_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/qemu_cortex_m0/pre_dt_board.cmake b/boards/waveshare/nrf51_ble400/pre_dt_board.cmake similarity index 100% rename from boards/arm/qemu_cortex_m0/pre_dt_board.cmake rename to boards/waveshare/nrf51_ble400/pre_dt_board.cmake diff --git a/boards/waveshare/open103z/Kconfig.waveshare_open103z b/boards/waveshare/open103z/Kconfig.waveshare_open103z new file mode 100644 index 00000000000..ae0e3f3b4b3 --- /dev/null +++ b/boards/waveshare/open103z/Kconfig.waveshare_open103z @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Stefano Manni +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WAVESHARE_OPEN103Z + select SOC_STM32F103XE diff --git a/boards/arm/waveshare_open103z/board.cmake b/boards/waveshare/open103z/board.cmake similarity index 100% rename from boards/arm/waveshare_open103z/board.cmake rename to boards/waveshare/open103z/board.cmake diff --git a/boards/waveshare/open103z/board.yml b/boards/waveshare/open103z/board.yml new file mode 100644 index 00000000000..7504feebf9f --- /dev/null +++ b/boards/waveshare/open103z/board.yml @@ -0,0 +1,5 @@ +board: + name: waveshare_open103z + vendor: waveshare + socs: + - name: stm32f103xe diff --git a/boards/arm/waveshare_open103z/doc/img/waveshare_connector.PNG b/boards/waveshare/open103z/doc/img/waveshare_connector.PNG similarity index 100% rename from boards/arm/waveshare_open103z/doc/img/waveshare_connector.PNG rename to boards/waveshare/open103z/doc/img/waveshare_connector.PNG diff --git a/boards/arm/waveshare_open103z/doc/img/waveshare_connector_list.PNG b/boards/waveshare/open103z/doc/img/waveshare_connector_list.PNG similarity index 100% rename from boards/arm/waveshare_open103z/doc/img/waveshare_connector_list.PNG rename to boards/waveshare/open103z/doc/img/waveshare_connector_list.PNG diff --git a/boards/arm/waveshare_open103z/doc/img/waveshare_open103z.jpg b/boards/waveshare/open103z/doc/img/waveshare_open103z.jpg similarity index 100% rename from boards/arm/waveshare_open103z/doc/img/waveshare_open103z.jpg rename to boards/waveshare/open103z/doc/img/waveshare_open103z.jpg diff --git a/boards/arm/waveshare_open103z/doc/index.rst b/boards/waveshare/open103z/doc/index.rst similarity index 100% rename from boards/arm/waveshare_open103z/doc/index.rst rename to boards/waveshare/open103z/doc/index.rst diff --git a/boards/arm/waveshare_open103z/support/openocd.cfg b/boards/waveshare/open103z/support/openocd.cfg similarity index 100% rename from boards/arm/waveshare_open103z/support/openocd.cfg rename to boards/waveshare/open103z/support/openocd.cfg diff --git a/boards/arm/waveshare_open103z/waveshare_open103z.dts b/boards/waveshare/open103z/waveshare_open103z.dts similarity index 100% rename from boards/arm/waveshare_open103z/waveshare_open103z.dts rename to boards/waveshare/open103z/waveshare_open103z.dts diff --git a/boards/arm/waveshare_open103z/waveshare_open103z.yaml b/boards/waveshare/open103z/waveshare_open103z.yaml similarity index 100% rename from boards/arm/waveshare_open103z/waveshare_open103z.yaml rename to boards/waveshare/open103z/waveshare_open103z.yaml diff --git a/boards/arm/waveshare_open103z/waveshare_open103z_defconfig b/boards/waveshare/open103z/waveshare_open103z_defconfig similarity index 81% rename from boards/arm/waveshare_open103z/waveshare_open103z_defconfig rename to boards/waveshare/open103z/waveshare_open103z_defconfig index 765fc062bd7..9fd4400ac20 100644 --- a/boards/arm/waveshare_open103z/waveshare_open103z_defconfig +++ b/boards/waveshare/open103z/waveshare_open103z_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103XE=y - # enable uart driver CONFIG_SERIAL=y # enable console diff --git a/boards/we/index.rst b/boards/we/index.rst new file mode 100644 index 00000000000..b7c7b2e468a --- /dev/null +++ b/boards/we/index.rst @@ -0,0 +1,10 @@ +.. _boards-wurth-elektronik: + +Würth Elektronik +################ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/we/ophelia1ev/Kconfig b/boards/we/ophelia1ev/Kconfig new file mode 100644 index 00000000000..2b36398f590 --- /dev/null +++ b/boards/we/ophelia1ev/Kconfig @@ -0,0 +1,10 @@ +# Ophelia-I EV nRF52805 board configuration + +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_WE_OPHELIA1EV diff --git a/boards/we/ophelia1ev/Kconfig.defconfig b/boards/we/ophelia1ev/Kconfig.defconfig new file mode 100644 index 00000000000..c148d677183 --- /dev/null +++ b/boards/we/ophelia1ev/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_WE_OPHELIA1EV + +config BT_CTLR + default BT + +endif diff --git a/boards/we/ophelia1ev/Kconfig.we_ophelia1ev b/boards/we/ophelia1ev/Kconfig.we_ophelia1ev new file mode 100644 index 00000000000..d732cd54cb3 --- /dev/null +++ b/boards/we/ophelia1ev/Kconfig.we_ophelia1ev @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WE_OPHELIA1EV + select SOC_NRF52805_CAAA diff --git a/boards/arm/we_ophelia1ev_nrf52805/board.cmake b/boards/we/ophelia1ev/board.cmake similarity index 100% rename from boards/arm/we_ophelia1ev_nrf52805/board.cmake rename to boards/we/ophelia1ev/board.cmake diff --git a/boards/we/ophelia1ev/board.yml b/boards/we/ophelia1ev/board.yml new file mode 100644 index 00000000000..ac80e1ed6e4 --- /dev/null +++ b/boards/we/ophelia1ev/board.yml @@ -0,0 +1,5 @@ +board: + name: we_ophelia1ev + vendor: wurth + socs: + - name: nrf52805 diff --git a/boards/arm/we_ophelia1ev_nrf52805/doc/img/we_ophelia1ev_nrf52805.jpg b/boards/we/ophelia1ev/doc/img/we_ophelia1ev_nrf52805.jpg similarity index 100% rename from boards/arm/we_ophelia1ev_nrf52805/doc/img/we_ophelia1ev_nrf52805.jpg rename to boards/we/ophelia1ev/doc/img/we_ophelia1ev_nrf52805.jpg diff --git a/boards/we/ophelia1ev/doc/index.rst b/boards/we/ophelia1ev/doc/index.rst new file mode 100644 index 00000000000..d64c32579a5 --- /dev/null +++ b/boards/we/ophelia1ev/doc/index.rst @@ -0,0 +1,115 @@ +.. _we_ophelia1ev_nrf52805: + +Ophelia-I EV NRF52805 +##################### + +Overview +******** + +The we_ophelia1ev_nrf52805 board is an evaluation board of the Ophelia-I radio module. +It provides support for the Nordic Semiconductor nRF52805 ARM CPU and +the following devices: + +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/we_ophelia1ev_nrf52805.jpg + :align: center + :alt: Ophelia-I EV + + Ophelia-I EV (Credit: Würth Elektronik) + +Hardware +******** + +The Ophelia-I uses the internal low frequency RC oscillator +and provides the so called smart antenna connection, that allows +to choose between the module's integrated PCB antenna and an external +antenna that can be connected to the available SMA connector. + +Supported Features +================== + +The we_ophelia1ev_nrf52805 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF52 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: we_ophelia1ev/nrf52805 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +References +********** + +.. target-notes:: + +.. _Ophelia-I radio module website: https://www.we-online.com/katalog/de/OPHELIA-I +.. _nRF52805 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52805 diff --git a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805-pinctrl.dtsi b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805-pinctrl.dtsi similarity index 100% rename from boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805-pinctrl.dtsi rename to boards/we/ophelia1ev/we_ophelia1ev_nrf52805-pinctrl.dtsi diff --git a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805.dts b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.dts similarity index 100% rename from boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805.dts rename to boards/we/ophelia1ev/we_ophelia1ev_nrf52805.dts diff --git a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805.yaml b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.yaml similarity index 88% rename from boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805.yaml rename to boards/we/ophelia1ev/we_ophelia1ev_nrf52805.yaml index b0697278931..5b55a854a0d 100644 --- a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805.yaml +++ b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: we_ophelia1ev_nrf52805 +identifier: we_ophelia1ev/nrf52805 name: we_ophelia1ev_nrf52805 type: mcu arch: arm diff --git a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805_defconfig b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805_defconfig similarity index 79% rename from boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805_defconfig rename to boards/we/ophelia1ev/we_ophelia1ev_nrf52805_defconfig index b81a1a35e4e..b2e4d39984b 100644 --- a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805_defconfig +++ b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52805_CAAA=y -CONFIG_BOARD_WE_OPHELIA1EV_NRF52805=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/we_proteus2ev_nrf52832/Kconfig b/boards/we/proteus2ev/Kconfig similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/Kconfig rename to boards/we/proteus2ev/Kconfig diff --git a/boards/we/proteus2ev/Kconfig.defconfig b/boards/we/proteus2ev/Kconfig.defconfig new file mode 100644 index 00000000000..dcdfd0a06e0 --- /dev/null +++ b/boards/we/proteus2ev/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_WE_PROTEUS2EV_NRF52832 + +config BT_CTLR + default BT + +endif diff --git a/boards/we/proteus2ev/Kconfig.we_proteus2ev b/boards/we/proteus2ev/Kconfig.we_proteus2ev new file mode 100644 index 00000000000..60aa73fb142 --- /dev/null +++ b/boards/we/proteus2ev/Kconfig.we_proteus2ev @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WE_PROTEUS2EV_NRF52832 + select SOC_NRF52832_CIAA diff --git a/boards/arm/we_proteus2ev_nrf52832/board.cmake b/boards/we/proteus2ev/board.cmake similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/board.cmake rename to boards/we/proteus2ev/board.cmake diff --git a/boards/we/proteus2ev/board.yml b/boards/we/proteus2ev/board.yml new file mode 100644 index 00000000000..38cc08204e5 --- /dev/null +++ b/boards/we/proteus2ev/board.yml @@ -0,0 +1,5 @@ +board: + name: we_proteus2ev + vendor: wurth + socs: + - name: nrf52832 diff --git a/boards/arm/we_proteus2ev_nrf52832/doc/img/we_proteus2ev_nrf52832.jpg b/boards/we/proteus2ev/doc/img/we_proteus2ev_nrf52832.jpg similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/doc/img/we_proteus2ev_nrf52832.jpg rename to boards/we/proteus2ev/doc/img/we_proteus2ev_nrf52832.jpg diff --git a/boards/we/proteus2ev/doc/index.rst b/boards/we/proteus2ev/doc/index.rst new file mode 100644 index 00000000000..7bdd621fd90 --- /dev/null +++ b/boards/we/proteus2ev/doc/index.rst @@ -0,0 +1,162 @@ +.. _we_proteus2ev_nrf52832: + +Würth Elektronik Proteus-II-EV +############################## + +Overview +******** + +The Proteus-II-EV hardware provides +support for the Proteus-II radio module that uses the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/we_proteus2ev_nrf52832.jpg + :align: center + :alt: Proteus-II EV + + Proteus-II-EV (Credit: Würth Elektronik) + +More information about the radio module can be found the Würth Elektronik web page https://www.we-online.com/katalog/de/PROTEUS-II . + + +Hardware +******** + +Proteus-II radio module provides only the internal oscillators. The frequency of the slow clock +is 32.768 kHz. The frequency of the main clock is 32 MHz. + +Supported Features +================== + +The we_proteus2ev/nrf52832 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features are not supported by the Zephyr kernel. + +Connections and IOs +=================== + +LED +--- + +* LED1 = P0.00 +* LED2 = P0.01 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.29 + + +Programming and Debugging +************************* + +Applications for the ``we_proteus2ev/nrf52832`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board Proteus-II-EV +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: we_proteus2ev/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the Proteus-II-EV +************************************************* + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/wurth_elektronik/proteus2ev/we_proteus2ev_nrf52832.dts`. + +References +********** + +.. target-notes:: + +.. _Proteus-II radio module website: https://www.we-online.com/katalog/de/PROTEUS-II +.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/we_proteus2ev_nrf52832/pre_dt_board.cmake b/boards/we/proteus2ev/pre_dt_board.cmake similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/pre_dt_board.cmake rename to boards/we/proteus2ev/pre_dt_board.cmake diff --git a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832-pinctrl.dtsi b/boards/we/proteus2ev/we_proteus2ev_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832-pinctrl.dtsi rename to boards/we/proteus2ev/we_proteus2ev_nrf52832-pinctrl.dtsi diff --git a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832.dts b/boards/we/proteus2ev/we_proteus2ev_nrf52832.dts similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832.dts rename to boards/we/proteus2ev/we_proteus2ev_nrf52832.dts diff --git a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832.yaml b/boards/we/proteus2ev/we_proteus2ev_nrf52832.yaml similarity index 88% rename from boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832.yaml rename to boards/we/proteus2ev/we_proteus2ev_nrf52832.yaml index 4cc87992655..e30510176d0 100644 --- a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832.yaml +++ b/boards/we/proteus2ev/we_proteus2ev_nrf52832.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: we_proteus2ev_nrf52832 +identifier: we_proteus2ev/nrf52832 name: we_proteus2ev_nrf52832 type: mcu arch: arm diff --git a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832_defconfig b/boards/we/proteus2ev/we_proteus2ev_nrf52832_defconfig similarity index 81% rename from boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832_defconfig rename to boards/we/proteus2ev/we_proteus2ev_nrf52832_defconfig index 0b4e298d05a..62452ad517e 100644 --- a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832_defconfig +++ b/boards/we/proteus2ev/we_proteus2ev_nrf52832_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_CIAA=y -CONFIG_BOARD_WE_PROTEUS2EV_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/we/proteus3ev/Kconfig b/boards/we/proteus3ev/Kconfig new file mode 100644 index 00000000000..06a2c989d8a --- /dev/null +++ b/boards/we/proteus3ev/Kconfig @@ -0,0 +1,18 @@ +# Proteus-III-EV board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_WE_PROTEUS3EV + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF52X_HV + default y + +endif # BOARD_WE_PROTEUS3EV diff --git a/boards/we/proteus3ev/Kconfig.defconfig b/boards/we/proteus3ev/Kconfig.defconfig new file mode 100644 index 00000000000..ef564abbcbc --- /dev/null +++ b/boards/we/proteus3ev/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_WE_PROTEUS3EV + +config BT_CTLR + default BT + +endif # BOARD_WE_PROTEUS3EV diff --git a/boards/we/proteus3ev/Kconfig.we_proteus3ev b/boards/we/proteus3ev/Kconfig.we_proteus3ev new file mode 100644 index 00000000000..bdc3245f14a --- /dev/null +++ b/boards/we/proteus3ev/Kconfig.we_proteus3ev @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WE_PROTEUS3EV + select SOC_NRF52840_QIAA diff --git a/boards/arm/we_proteus3ev_nrf52840/board.cmake b/boards/we/proteus3ev/board.cmake similarity index 100% rename from boards/arm/we_proteus3ev_nrf52840/board.cmake rename to boards/we/proteus3ev/board.cmake diff --git a/boards/we/proteus3ev/board.yml b/boards/we/proteus3ev/board.yml new file mode 100644 index 00000000000..6def880d7a5 --- /dev/null +++ b/boards/we/proteus3ev/board.yml @@ -0,0 +1,5 @@ +board: + name: we_proteus3ev + vendor: wurth + socs: + - name: nrf52840 diff --git a/boards/arm/we_proteus3ev_nrf52840/doc/img/we_proteus3ev_nrf52840.jpg b/boards/we/proteus3ev/doc/img/we_proteus3ev_nrf52840.jpg similarity index 100% rename from boards/arm/we_proteus3ev_nrf52840/doc/img/we_proteus3ev_nrf52840.jpg rename to boards/we/proteus3ev/doc/img/we_proteus3ev_nrf52840.jpg diff --git a/boards/we/proteus3ev/doc/index.rst b/boards/we/proteus3ev/doc/index.rst new file mode 100644 index 00000000000..59c5116d509 --- /dev/null +++ b/boards/we/proteus3ev/doc/index.rst @@ -0,0 +1,164 @@ +.. _we_proteus3ev_nrf52840: + +Würth Elektronik Proteus-III-EV +############################### + +Overview +******** + +The Proteus-III-EV (evaluation board) hardware provides support +for the Proteus-III radio module that uses the Nordic Semiconductor +nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/we_proteus3ev_nrf52840.jpg + :align: center + :alt: Proteus-III EV + + Proteus-III EV (Credit: Würth Elektronik) + +More information about the radio module can be found the Würth Elektronik +web page https://www.we-online.com/katalog/de/PROTEUS-III . + + +Hardware +******** + +Proteus-III radio module provides only the internal oscillators. The +frequency of the slow clock is 32.768 kHz. The frequency of the main +clock is 32 MHz. + +Supported Features +================== + +The we_proteus3ev/nrf52840 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features are not supported by the Zephyr kernel. + +Connections and IOs +=================== + +LED +--- + +* LED1 = P0.00 +* LED2 = P0.01 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.03 + +Programming and Debugging +************************* + +Applications for the ``we_proteus3ev/nrf52840`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board Proteus-III-EV +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: we_proteus3ev/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +boards with a Segger IC. + +Testing the LEDs and buttons in the Proteus-III-EV +************************************************** + +There are 2 samples that allow you to test that the buttons (switches) and +LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly +on your board. The button and LED definitions can be found in +:zephyr_file:`boards/wurth_elektronik/proteus3ev/we_proteus3ev_nrf52840.dts`. + +References +********** + +.. target-notes:: + +.. _Proteus-III radio module website: https://www.we-online.com/katalog/de/PROTEUS-III +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf diff --git a/boards/arm/we_proteus3ev_nrf52840/pre_dt_board.cmake b/boards/we/proteus3ev/pre_dt_board.cmake similarity index 100% rename from boards/arm/we_proteus3ev_nrf52840/pre_dt_board.cmake rename to boards/we/proteus3ev/pre_dt_board.cmake diff --git a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840-pinctrl.dtsi b/boards/we/proteus3ev/we_proteus3ev_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840-pinctrl.dtsi rename to boards/we/proteus3ev/we_proteus3ev_nrf52840-pinctrl.dtsi diff --git a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.dts b/boards/we/proteus3ev/we_proteus3ev_nrf52840.dts similarity index 100% rename from boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.dts rename to boards/we/proteus3ev/we_proteus3ev_nrf52840.dts diff --git a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.yaml b/boards/we/proteus3ev/we_proteus3ev_nrf52840.yaml similarity index 88% rename from boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.yaml rename to boards/we/proteus3ev/we_proteus3ev_nrf52840.yaml index 544029d3d9c..5a771ca28b3 100644 --- a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.yaml +++ b/boards/we/proteus3ev/we_proteus3ev_nrf52840.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: we_proteus3ev_nrf52840 +identifier: we_proteus3ev/nrf52840 name: we_proteus3ev_nrf52840 type: mcu arch: arm diff --git a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840_defconfig b/boards/we/proteus3ev/we_proteus3ev_nrf52840_defconfig similarity index 81% rename from boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840_defconfig rename to boards/we/proteus3ev/we_proteus3ev_nrf52840_defconfig index a7687b6b541..62452ad517e 100644 --- a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840_defconfig +++ b/boards/we/proteus3ev/we_proteus3ev_nrf52840_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_WE_PROTEUS3EV_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/weact/blackpill_f401cc/Kconfig.blackpill_f401cc b/boards/weact/blackpill_f401cc/Kconfig.blackpill_f401cc new file mode 100644 index 00000000000..10068a79a76 --- /dev/null +++ b/boards/weact/blackpill_f401cc/Kconfig.blackpill_f401cc @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLACKPILL_F401CC + select SOC_STM32F401XC diff --git a/boards/weact/blackpill_f401cc/Kconfig.defconfig b/boards/weact/blackpill_f401cc/Kconfig.defconfig new file mode 100644 index 00000000000..dff0982bd8b --- /dev/null +++ b/boards/weact/blackpill_f401cc/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2022 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# F401CE based Black Pill V3.0+ board board configuration + +if BOARD_BLACKPILL_F401CC + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_BLACKPILL_F401CC diff --git a/boards/arm/blackpill_f401cc/blackpill_f401cc.dts b/boards/weact/blackpill_f401cc/blackpill_f401cc.dts similarity index 100% rename from boards/arm/blackpill_f401cc/blackpill_f401cc.dts rename to boards/weact/blackpill_f401cc/blackpill_f401cc.dts diff --git a/boards/arm/blackpill_f401cc/blackpill_f401cc.yaml b/boards/weact/blackpill_f401cc/blackpill_f401cc.yaml similarity index 100% rename from boards/arm/blackpill_f401cc/blackpill_f401cc.yaml rename to boards/weact/blackpill_f401cc/blackpill_f401cc.yaml diff --git a/boards/arm/blackpill_f401cc/blackpill_f401cc_defconfig b/boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig similarity index 87% rename from boards/arm/blackpill_f401cc/blackpill_f401cc_defconfig rename to boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig index 416cdff51e6..180ea77ffc9 100644 --- a/boards/arm/blackpill_f401cc/blackpill_f401cc_defconfig +++ b/boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2022 Linaro Limited # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/blackpill_f401cc/board.cmake b/boards/weact/blackpill_f401cc/board.cmake similarity index 100% rename from boards/arm/blackpill_f401cc/board.cmake rename to boards/weact/blackpill_f401cc/board.cmake diff --git a/boards/weact/blackpill_f401cc/board.yml b/boards/weact/blackpill_f401cc/board.yml new file mode 100644 index 00000000000..e72de492ef8 --- /dev/null +++ b/boards/weact/blackpill_f401cc/board.yml @@ -0,0 +1,5 @@ +board: + name: blackpill_f401cc + vendor: weact + socs: + - name: stm32f401xc diff --git a/boards/arm/blackpill_f401cc/doc/img/Blackpill_Pinout.jpg b/boards/weact/blackpill_f401cc/doc/img/Blackpill_Pinout.jpg similarity index 100% rename from boards/arm/blackpill_f401cc/doc/img/Blackpill_Pinout.jpg rename to boards/weact/blackpill_f401cc/doc/img/Blackpill_Pinout.jpg diff --git a/boards/arm/blackpill_f401cc/doc/img/blackpill-v3.jpg b/boards/weact/blackpill_f401cc/doc/img/blackpill-v3.jpg similarity index 100% rename from boards/arm/blackpill_f401cc/doc/img/blackpill-v3.jpg rename to boards/weact/blackpill_f401cc/doc/img/blackpill-v3.jpg diff --git a/boards/weact/blackpill_f401cc/doc/index.rst b/boards/weact/blackpill_f401cc/doc/index.rst new file mode 100644 index 00000000000..79e30862e87 --- /dev/null +++ b/boards/weact/blackpill_f401cc/doc/index.rst @@ -0,0 +1,173 @@ +.. _blackpill_f401cc: + +WeAct Studio Black Pill V1.2 +############################ + +Overview +******** + +The WeAct Black Pill V1.2 Board is an extremely low cost and bare-bones +development board featuring the STM32F401CC, see `STM32F401CC website`_. +This is the 48-pin variant of the STM32F401x series, +see `STM32F401x reference manual`_. More info about the board available +`here `_ and on `WeAct Github`_. + +.. image:: img/blackpill-v3.jpg + :align: center + :alt: Black Pill V3.0+ + +Hardware +******** + +The STM32F401CC based Black Pill V3.0+ Board provides the following +hardware components: + +- STM32F401CCU6 in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 84 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 256 KB Flash +- 64 KB SRAM +- GPIO with external interrupt capability +- 1x12-bit, 2.4 MSPS ADC with 16 channels +- DMA Controller +- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (3) +- I2C (3) +- SPI/I2S (5) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- CRC calculation unit +- 96-bit unique ID +- RTC + +Supported Features +================== + +The Zephyr blackpill_f401ce board configuration supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig` + +Pin Mapping +=========== + +Available pins: +--------------- +.. image:: img/Blackpill_Pinout.jpg + :align: center + :alt: Black Pill V1.2 Pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- I2C1 SCL/SDA : PB8/PB9 +- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) +- PWM_4_CH1 : PB6 +- PWM_4_CH2 : PB7 +- ADC_1 : PA1 +- USER_PB : PA0 +- USER_LED : PC13 + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is +32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. + +The default configuration sources the system clock from the PLL, which is +derived from HSE, and is set at 84MHz, which is the maximum possible frequency +to achieve a stable USB clock (42MHz). + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an Application +----------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: blackpill_f401cc + :goals: build flash + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, +and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO +pins on that header. + +References +********** + +.. target-notes:: + +.. _board release notes: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _WeAct Github: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 + +.. _stm32-base-board-page: + https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2.html + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32F401CC website: + https://www.st.com/en/microcontrollers/stm32f401cc.html + +.. _STM32F401x reference manual: + https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/blackpill_f401ce/support/openocd.cfg b/boards/weact/blackpill_f401cc/support/openocd.cfg similarity index 100% rename from boards/arm/blackpill_f401ce/support/openocd.cfg rename to boards/weact/blackpill_f401cc/support/openocd.cfg diff --git a/boards/weact/blackpill_f401ce/Kconfig.blackpill_f401ce b/boards/weact/blackpill_f401ce/Kconfig.blackpill_f401ce new file mode 100644 index 00000000000..9b638f3cd2b --- /dev/null +++ b/boards/weact/blackpill_f401ce/Kconfig.blackpill_f401ce @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Kalyan Sriram +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLACKPILL_F401CE + select SOC_STM32F401XE diff --git a/boards/weact/blackpill_f401ce/Kconfig.defconfig b/boards/weact/blackpill_f401ce/Kconfig.defconfig new file mode 100644 index 00000000000..57ff4a77369 --- /dev/null +++ b/boards/weact/blackpill_f401ce/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2020 Kalyan Sriram +# SPDX-License-Identifier: Apache-2.0 + +# F401CE based Black Pill V3.0+ board board configuration + +if BOARD_BLACKPILL_F401CE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_BLACKPILL_F401CE diff --git a/boards/arm/blackpill_f401ce/blackpill_f401ce.dts b/boards/weact/blackpill_f401ce/blackpill_f401ce.dts similarity index 100% rename from boards/arm/blackpill_f401ce/blackpill_f401ce.dts rename to boards/weact/blackpill_f401ce/blackpill_f401ce.dts diff --git a/boards/arm/blackpill_f401ce/blackpill_f401ce.yaml b/boards/weact/blackpill_f401ce/blackpill_f401ce.yaml similarity index 100% rename from boards/arm/blackpill_f401ce/blackpill_f401ce.yaml rename to boards/weact/blackpill_f401ce/blackpill_f401ce.yaml diff --git a/boards/arm/blackpill_f401ce/blackpill_f401ce_defconfig b/boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig similarity index 86% rename from boards/arm/blackpill_f401ce/blackpill_f401ce_defconfig rename to boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig index e2fdc023a5b..8f08a2bfe96 100644 --- a/boards/arm/blackpill_f401ce/blackpill_f401ce_defconfig +++ b/boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/blackpill_f401ce/board.cmake b/boards/weact/blackpill_f401ce/board.cmake similarity index 100% rename from boards/arm/blackpill_f401ce/board.cmake rename to boards/weact/blackpill_f401ce/board.cmake diff --git a/boards/weact/blackpill_f401ce/board.yml b/boards/weact/blackpill_f401ce/board.yml new file mode 100644 index 00000000000..83d26820943 --- /dev/null +++ b/boards/weact/blackpill_f401ce/board.yml @@ -0,0 +1,5 @@ +board: + name: blackpill_f401ce + vendor: weact + socs: + - name: stm32f401xe diff --git a/boards/arm/blackpill_f401ce/doc/img/Blackpill_Pinout.jpg b/boards/weact/blackpill_f401ce/doc/img/Blackpill_Pinout.jpg similarity index 100% rename from boards/arm/blackpill_f401ce/doc/img/Blackpill_Pinout.jpg rename to boards/weact/blackpill_f401ce/doc/img/Blackpill_Pinout.jpg diff --git a/boards/arm/blackpill_f401ce/doc/img/blackpill-v3.jpg b/boards/weact/blackpill_f401ce/doc/img/blackpill-v3.jpg similarity index 100% rename from boards/arm/blackpill_f401ce/doc/img/blackpill-v3.jpg rename to boards/weact/blackpill_f401ce/doc/img/blackpill-v3.jpg diff --git a/boards/weact/blackpill_f401ce/doc/index.rst b/boards/weact/blackpill_f401ce/doc/index.rst new file mode 100644 index 00000000000..eb4983577ae --- /dev/null +++ b/boards/weact/blackpill_f401ce/doc/index.rst @@ -0,0 +1,178 @@ +.. _blackpill_f401ce: + +WeAct Studio Black Pill V3.0 +############################ + +Overview +******** + +The WeAct Black Pill V3.0 Board is an extremely low cost and bare-bones +development board featuring the STM32F401CE, see `STM32F401CE website`_. +This is the 48-pin variant of the STM32F401x series, +see `STM32F401x reference manual`_. More info about the board available +`here `_ and on `WeAct Github`_. + +.. image:: img/blackpill-v3.jpg + :align: center + :alt: Black Pill V3.0+ + +Hardware +******** + +The STM32F401CE based Black Pill V3.0+ Board provides the following +hardware components: + +- STM32F401CEU6 in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 84 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 96 KB SRAM +- GPIO with external interrupt capability +- 1x12-bit, 2.4 MSPS ADC with 16 channels +- DMA Controller +- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (3) +- I2C (3) +- SPI/I2S (5) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- CRC calculation unit +- 96-bit unique ID +- RTC + +Supported Features +================== + +The Zephyr blackpill_f401ce board configuration supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig` + +Pin Mapping +=========== + +Available pins: +--------------- +.. image:: img/Blackpill_Pinout.jpg + :align: center + :alt: Black Pill V3.0+ Pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- I2C1 SCL/SDA : PB8/PB9 +- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) +- PWM_4_CH1 : PB6 +- PWM_4_CH2 : PB7 +- ADC_1 : PA1 +- USER_PB : PA0 +- USER_LED : PC13 + +Note on SPI pin mapping: According to the `board release notes`_, there was a brief +change for V2.0 specifically where MISO was routed to PB4 for the flash footprint. +This was reverted for V2.1+ so that the flash DO pin was routed back to PA6. If using +V2.0 and en external flash, the pinmux will need to be modified accordingly. + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is +32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. + +The default configuration sources the system clock from the PLL, which is +derived from HSE, and is set at 84MHz, which is the maximum possible frequency +to achieve a stable USB clock (42MHz). + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an Application +----------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: blackpill_f401ce + :goals: build flash + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, +and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO +pins on that header. + +References +********** + +.. target-notes:: + +.. _board release notes: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _WeAct Github: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 + +.. _stm32-base-board-page: + https://stm32-base.org/boards/STM32F401CEU6-WeAct-Black-Pill-V3.0.html + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32F401CE website: + https://www.st.com/en/microcontrollers/stm32f401ce.html + +.. _STM32F401x reference manual: + https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/blackpill_f411ce/support/openocd.cfg b/boards/weact/blackpill_f401ce/support/openocd.cfg similarity index 100% rename from boards/arm/blackpill_f411ce/support/openocd.cfg rename to boards/weact/blackpill_f401ce/support/openocd.cfg diff --git a/boards/weact/blackpill_f411ce/Kconfig.blackpill_f411ce b/boards/weact/blackpill_f411ce/Kconfig.blackpill_f411ce new file mode 100644 index 00000000000..c6d1b632da1 --- /dev/null +++ b/boards/weact/blackpill_f411ce/Kconfig.blackpill_f411ce @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Brian Bradley +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLACKPILL_F411CE + select SOC_STM32F411XE diff --git a/boards/weact/blackpill_f411ce/Kconfig.defconfig b/boards/weact/blackpill_f411ce/Kconfig.defconfig new file mode 100644 index 00000000000..a14284ed4c5 --- /dev/null +++ b/boards/weact/blackpill_f411ce/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2020 Brian Bradley +# SPDX-License-Identifier: Apache-2.0 + +# F411CE based Black Pill V2.0+ board board configuration + +if BOARD_BLACKPILL_F411CE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_BLACKPILL_F411CE diff --git a/boards/arm/blackpill_f411ce/blackpill_f411ce.dts b/boards/weact/blackpill_f411ce/blackpill_f411ce.dts similarity index 100% rename from boards/arm/blackpill_f411ce/blackpill_f411ce.dts rename to boards/weact/blackpill_f411ce/blackpill_f411ce.dts diff --git a/boards/arm/blackpill_f411ce/blackpill_f411ce.yaml b/boards/weact/blackpill_f411ce/blackpill_f411ce.yaml similarity index 100% rename from boards/arm/blackpill_f411ce/blackpill_f411ce.yaml rename to boards/weact/blackpill_f411ce/blackpill_f411ce.yaml diff --git a/boards/arm/blackpill_f411ce/blackpill_f411ce_defconfig b/boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig similarity index 86% rename from boards/arm/blackpill_f411ce/blackpill_f411ce_defconfig rename to boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig index 1c1d2d96925..8f08a2bfe96 100644 --- a/boards/arm/blackpill_f411ce/blackpill_f411ce_defconfig +++ b/boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F411XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/blackpill_f411ce/board.cmake b/boards/weact/blackpill_f411ce/board.cmake similarity index 100% rename from boards/arm/blackpill_f411ce/board.cmake rename to boards/weact/blackpill_f411ce/board.cmake diff --git a/boards/weact/blackpill_f411ce/board.yml b/boards/weact/blackpill_f411ce/board.yml new file mode 100644 index 00000000000..b145c5e7f01 --- /dev/null +++ b/boards/weact/blackpill_f411ce/board.yml @@ -0,0 +1,5 @@ +board: + name: blackpill_f411ce + vendor: weact + socs: + - name: stm32f411xe diff --git a/boards/arm/blackpill_f411ce/doc/img/Blackpill_Pinout.jpg b/boards/weact/blackpill_f411ce/doc/img/Blackpill_Pinout.jpg similarity index 100% rename from boards/arm/blackpill_f411ce/doc/img/Blackpill_Pinout.jpg rename to boards/weact/blackpill_f411ce/doc/img/Blackpill_Pinout.jpg diff --git a/boards/arm/blackpill_f411ce/doc/img/blackpill-v2.jpg b/boards/weact/blackpill_f411ce/doc/img/blackpill-v2.jpg similarity index 100% rename from boards/arm/blackpill_f411ce/doc/img/blackpill-v2.jpg rename to boards/weact/blackpill_f411ce/doc/img/blackpill-v2.jpg diff --git a/boards/weact/blackpill_f411ce/doc/index.rst b/boards/weact/blackpill_f411ce/doc/index.rst new file mode 100644 index 00000000000..f190d7ea64a --- /dev/null +++ b/boards/weact/blackpill_f411ce/doc/index.rst @@ -0,0 +1,178 @@ +.. _blackpill_f411ce: + +WeAct Studio Black Pill V2.0 +############################ + +Overview +******** + +The WeAct Black Pill V2.0 Board is an extremely low cost and bare-bones +development board featuring the STM32F411CE, see `STM32F411CE website`_. +This is the 48-pin variant of the STM32F411x series, +see `STM32F411x reference manual`_. More info about the board available +`here `_ and on `WeAct Github`_. + +.. image:: img/blackpill-v2.jpg + :align: center + :alt: Black Pill V2.0+ + +Hardware +******** + +The STM32F411CE based Black Pill V2.0+ Board provides the following +hardware components: + +- STM32F411CEU6 in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 128 KB SRAM +- GPIO with external interrupt capability +- 1x12-bit, 2.4 MSPS ADC with 16 channels +- DMA Controller +- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (3) +- I2C (3) +- SPI/I2S (5) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- CRC calculation unit +- 96-bit unique ID +- RTC + +Supported Features +================== + +The Zephyr blackpill_f411ce board configuration supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig` + +Pin Mapping +=========== + +Available pins: +--------------- +.. image:: img/Blackpill_Pinout.jpg + :align: center + :alt: Black Pill V2.0+ Pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- I2C1 SCL/SDA : PB8/PB9 +- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) +- PWM_4_CH1 : PB6 +- PWM_4_CH2 : PB7 +- ADC_1 : PA1 +- USER_PB : PA0 +- USER_LED : PC13 + +Note on SPI pin mapping: According to the `board release notes`_, there was a brief +change for V2.0 specifically where MISO was routed to PB4 for the flash footprint. +This was reverted for V2.1+ so that the flash DO pin was routed back to PA6. If using +V2.0 and en external flash, the pinmux will need to be modified accordingly. + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is +32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. + +The default configuration sources the system clock from the PLL, which is +derived from HSE, and is set at 96MHz, which is the maximum possible frequency +to achieve a stable USB clock (48MHz). + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an Application +----------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: blackpill_f411ce + :goals: build flash + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, +and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO +pins on that header. + +References +********** + +.. target-notes:: + +.. _board release notes: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _WeAct Github: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 + +.. _stm32-base-board-page: + https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0.html + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32F411CE website: + https://www.st.com/en/microcontrollers/stm32f411ce.html + +.. _STM32F411x reference manual: + https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/stm32f401_mini/support/openocd.cfg b/boards/weact/blackpill_f411ce/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f401_mini/support/openocd.cfg rename to boards/weact/blackpill_f411ce/support/openocd.cfg diff --git a/boards/weact/index.rst b/boards/weact/index.rst new file mode 100644 index 00000000000..21a31a00312 --- /dev/null +++ b/boards/weact/index.rst @@ -0,0 +1,10 @@ +.. _boards-weact: + +WeAct Studio +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/weact/stm32g431_core/Kconfig.weact_stm32g431_core b/boards/weact/stm32g431_core/Kconfig.weact_stm32g431_core new file mode 100644 index 00000000000..2bd370e9311 --- /dev/null +++ b/boards/weact/stm32g431_core/Kconfig.weact_stm32g431_core @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Andreas Sandberg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WEACT_STM32G431_CORE + select SOC_STM32G431XX diff --git a/boards/arm/weact_stm32g431_core/board.cmake b/boards/weact/stm32g431_core/board.cmake similarity index 100% rename from boards/arm/weact_stm32g431_core/board.cmake rename to boards/weact/stm32g431_core/board.cmake diff --git a/boards/weact/stm32g431_core/board.yml b/boards/weact/stm32g431_core/board.yml new file mode 100644 index 00000000000..359e74ed0d7 --- /dev/null +++ b/boards/weact/stm32g431_core/board.yml @@ -0,0 +1,5 @@ +board: + name: weact_stm32g431_core + vendor: weact + socs: + - name: stm32g431xx diff --git a/boards/weact/stm32g431_core/doc/index.rst b/boards/weact/stm32g431_core/doc/index.rst new file mode 100644 index 00000000000..7ebfbd02b29 --- /dev/null +++ b/boards/weact/stm32g431_core/doc/index.rst @@ -0,0 +1,147 @@ +.. _weact_stm32g431_core: + +WeAct Studio STM32G431 Core Board +################################# + +The WeAct STM32G431 Core Board is a low-cost bare-bones STM32G431-based development +board. See the `STM32G431CB website`_ for more information about the MCU. More information +about the board, including schematics, is available from the `WeAct GitHub`_. + +Modifications USB-C Power Delivery +********************************** + +The board does not support USB-C PD in its standard configuration. To enable USB-C PD, CC1 +and CC2 need to be disconnected from their pull-down resistors and be connected to PB6 and +PB4 respectively. Dead battery support requires PA9 and PA10 to be routed to CC1 and +CC2. VBUS also needs to be connected to the MCU through a voltage divider. + +The pull-downs are disconnected by removing the zero-Ohm resistors on SB8 and SB9 next to +the USB-C connector. SB3, SB5, SB6, and SB7 then need to be closed to connect the CCx +lines to the MCU. The voltage divider is connected to PB2 by closing SB4. + +After these modifications have been made, PA9, PA10, PB2, PB4, and PB6 should be +considered reserved for USB-C and not available for other applications. + +.. warning:: + The internal USB DFU boot loader may not work correctly with machines that respect USB + PD signaling unless dead battery support has been enabled. A USB-C to USB-A adapter or + programming using the SWD port can be used as a workaround. + + +Supported Features +================== + +The Zephyr weact_stm32g431_core board configuration supports the following hardware +features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++------------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++------------+------------+-------------------------------------+ +| UCPD | on-chip | ucpd | ++------------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + +:zephyr_file:`boards/weact/stm32g431_core/weact_stm32g431_core_defconfig` + +Pin Mapping +=========== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA3 +- UCPD1 CCx : PB6/PB4 (not connected by default) +- UCPD1 DBCCx : PA9/PA10 (not connected by default) +- BUTTON (User) : PC13 +- BUTTON (BOOT0) : PB8 +- LED0 : PC6 +- ADC (VBUS) : PB2 + +The ADC is disabled by default since the VBUS voltage divider is not connected in the +board's standard configuration. + + +Hardware Configuration +---------------------- ++---------------+---------+-----------------------------------------------+ +| Solder bridge | Default | Description | ++===============+=========+===============================================+ +| SB1/SB2 | Open | Route PC14/PC15 (LSE) to header | ++---------------+---------+-----------------------------------------------+ +| SB6/SB7 | Open | Connect PB4/PB6 (UCPD1_CCx) to USB-C CCx pins | ++---------------+---------+-----------------------------------------------+ +| SB3/SB5 | Open | Connect PA9/PA10 (UCPD1_DBCCx) to to PB6/PB4 | ++---------------+---------+-----------------------------------------------+ +| SB4 | Open | Connect PB2 to VBUS voltage divider | ++---------------+---------+-----------------------------------------------+ +| SB8/SB9 | Closed | Connect USB-CCx to pull-down resistors | ++---------------+---------+-----------------------------------------------+ +| SB10 | Open | VBUS protection diode bypass | ++---------------+---------+-----------------------------------------------+ + + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is 32.768 +kHz. The frequency of the main clock (HSE) is 8 MHz. + +The default configuration sources the system clock from the PLL, which is derived from +HSE, and is set at 144 MHz. The 48 MHz clock used by the USB interface is derived from the +PLL instead of the internal 48 MHz oscillator. + +Programming and Debugging +************************* + +The MCU is normally programmed using the ROM bootloader or the exposed SWD port. + +Please note that some laptops may not detect the ROM bootloader correctly if the CCx +pull-downs have been disconnected by opening SB8 and SB9 unless dead battery support has +been enabled by closing SB3 and SB5. A USB-C to USB-A adapter can be used as a workaround +if this is a problem. + +Flashing an Application +======================= + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode by +keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. + +The dfu-util runner is supported on this board and so a sample can be built and tested +easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: weact_stm32g431_core + :goals: build flash + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, and +attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO pins on that header. + + +References +********** + +.. target-notes:: + +.. _WeAct GitHub: + https://github.com/WeActStudio/WeActStudio.STM32G431CoreBoard + +.. _STM32G431CB website: + https://www.st.com/en/microcontrollers-microprocessors/stm32g431cb.html + +.. _STM32F401x reference manual: + https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/weact_stm32g431_core/support/openocd.cfg b/boards/weact/stm32g431_core/support/openocd.cfg similarity index 100% rename from boards/arm/weact_stm32g431_core/support/openocd.cfg rename to boards/weact/stm32g431_core/support/openocd.cfg diff --git a/boards/arm/weact_stm32g431_core/weact_stm32g431_core.dts b/boards/weact/stm32g431_core/weact_stm32g431_core.dts similarity index 100% rename from boards/arm/weact_stm32g431_core/weact_stm32g431_core.dts rename to boards/weact/stm32g431_core/weact_stm32g431_core.dts diff --git a/boards/arm/weact_stm32g431_core/weact_stm32g431_core.yaml b/boards/weact/stm32g431_core/weact_stm32g431_core.yaml similarity index 100% rename from boards/arm/weact_stm32g431_core/weact_stm32g431_core.yaml rename to boards/weact/stm32g431_core/weact_stm32g431_core.yaml diff --git a/boards/arm/weact_stm32g431_core/weact_stm32g431_core_defconfig b/boards/weact/stm32g431_core/weact_stm32g431_core_defconfig similarity index 83% rename from boards/arm/weact_stm32g431_core/weact_stm32g431_core_defconfig rename to boards/weact/stm32g431_core/weact_stm32g431_core_defconfig index 0c9d0e2a185..19919b198ca 100644 --- a/boards/arm/weact_stm32g431_core/weact_stm32g431_core_defconfig +++ b/boards/weact/stm32g431_core/weact_stm32g431_core_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_STM32G4X=y -CONFIG_SOC_STM32G431XX=y - CONFIG_CLOCK_CONTROL=y CONFIG_PINCTRL=y diff --git a/boards/wemos/esp32s2_lolin_mini/Kconfig.defconfig b/boards/wemos/esp32s2_lolin_mini/Kconfig.defconfig new file mode 100644 index 00000000000..85fdb266956 --- /dev/null +++ b/boards/wemos/esp32s2_lolin_mini/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ESP32S2 LOLIN S2 MINI board configuration + +# Copyright (c) 2023 Google, LLC +# SPDX-License-Identifier: Apache-2.0 + +config ENTROPY_GENERATOR + default y + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 32768 if WIFI + default 4096 diff --git a/boards/wemos/esp32s2_lolin_mini/Kconfig.esp32s2_lolin_mini b/boards/wemos/esp32s2_lolin_mini/Kconfig.esp32s2_lolin_mini new file mode 100644 index 00000000000..fe7f72a138b --- /dev/null +++ b/boards/wemos/esp32s2_lolin_mini/Kconfig.esp32s2_lolin_mini @@ -0,0 +1,7 @@ +# ESP32S2 LOLIN S2 MINI board configuration + +# Copyright (c) 2023 Google, LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S2_LOLIN_MINI + select SOC_ESP32S2_FN4R2 diff --git a/boards/xtensa/yd_esp32/board.cmake b/boards/wemos/esp32s2_lolin_mini/board.cmake similarity index 100% rename from boards/xtensa/yd_esp32/board.cmake rename to boards/wemos/esp32s2_lolin_mini/board.cmake diff --git a/boards/wemos/esp32s2_lolin_mini/board.yml b/boards/wemos/esp32s2_lolin_mini/board.yml new file mode 100644 index 00000000000..7df1267c214 --- /dev/null +++ b/boards/wemos/esp32s2_lolin_mini/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s2_lolin_mini + vendor: wemos + socs: + - name: esp32s2 diff --git a/boards/xtensa/esp32s2_lolin_mini/doc/img/esp32_s2_lolin_mini.jpg b/boards/wemos/esp32s2_lolin_mini/doc/img/esp32_s2_lolin_mini.jpg similarity index 100% rename from boards/xtensa/esp32s2_lolin_mini/doc/img/esp32_s2_lolin_mini.jpg rename to boards/wemos/esp32s2_lolin_mini/doc/img/esp32_s2_lolin_mini.jpg diff --git a/boards/xtensa/esp32s2_lolin_mini/doc/index.rst b/boards/wemos/esp32s2_lolin_mini/doc/index.rst similarity index 100% rename from boards/xtensa/esp32s2_lolin_mini/doc/index.rst rename to boards/wemos/esp32s2_lolin_mini/doc/index.rst diff --git a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini-pinctrl.dtsi b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini-pinctrl.dtsi rename to boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini-pinctrl.dtsi diff --git a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.dts b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts similarity index 98% rename from boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.dts rename to boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts index 3ce00f8bdb8..53a598ad0de 100644 --- a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.dts +++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts @@ -11,7 +11,7 @@ #include "esp32s2_lolin_mini-pinctrl.dtsi" / { - model = "esp32s2_lolin_mini"; + model = "Wemos ESP32S2-Lolin Mini"; compatible = "espressif,esp32s2"; aliases { diff --git a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml similarity index 93% rename from boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml rename to boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml index 3764f5eddd7..763b8c838f4 100644 --- a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml +++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml @@ -12,3 +12,4 @@ testing: ignore_tags: - net - bluetooth +vendor: wemos diff --git a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig new file mode 100644 index 00000000000..f029cac9e9e --- /dev/null +++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_saola/support/openocd.cfg b/boards/wemos/esp32s2_lolin_mini/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32s2_saola/support/openocd.cfg rename to boards/wemos/esp32s2_lolin_mini/support/openocd.cfg diff --git a/boards/wemos/index.rst b/boards/wemos/index.rst new file mode 100644 index 00000000000..200fbcae8a7 --- /dev/null +++ b/boards/wemos/index.rst @@ -0,0 +1,10 @@ +.. _boards-wemos: + +Wemos +##### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/wiznet/index.rst b/boards/wiznet/index.rst new file mode 100644 index 00000000000..6fe6eeac028 --- /dev/null +++ b/boards/wiznet/index.rst @@ -0,0 +1,10 @@ +.. _boards-wiznet: + +WIZnet +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/wiznet/w5500_evb_pico/Kconfig.defconfig b/boards/wiznet/w5500_evb_pico/Kconfig.defconfig new file mode 100644 index 00000000000..a159b56f52a --- /dev/null +++ b/boards/wiznet/w5500_evb_pico/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2021 Yonatan Schachter +# Copyright (c) 2023 Ian Wakely +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_W5500_EVB_PICO + +config RP2_FLASH_W25Q080 + default y + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_W5500_EVB_PICO diff --git a/boards/wiznet/w5500_evb_pico/Kconfig.w5500_evb_pico b/boards/wiznet/w5500_evb_pico/Kconfig.w5500_evb_pico new file mode 100644 index 00000000000..d6326dffedb --- /dev/null +++ b/boards/wiznet/w5500_evb_pico/Kconfig.w5500_evb_pico @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Yonatan Schachter +# Copyright (c) 2023 Ian Wakely +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_W5500_EVB_PICO + select SOC_RP2040 diff --git a/boards/arm/w5500_evb_pico/board.cmake b/boards/wiznet/w5500_evb_pico/board.cmake similarity index 100% rename from boards/arm/w5500_evb_pico/board.cmake rename to boards/wiznet/w5500_evb_pico/board.cmake diff --git a/boards/wiznet/w5500_evb_pico/board.yml b/boards/wiznet/w5500_evb_pico/board.yml new file mode 100644 index 00000000000..17ce17eea15 --- /dev/null +++ b/boards/wiznet/w5500_evb_pico/board.yml @@ -0,0 +1,5 @@ +board: + name: w5500_evb_pico + vendor: wiznet + socs: + - name: rp2040 diff --git a/boards/arm/w5500_evb_pico/doc/img/w5500_evb_pico_side.png b/boards/wiznet/w5500_evb_pico/doc/img/w5500_evb_pico_side.png similarity index 100% rename from boards/arm/w5500_evb_pico/doc/img/w5500_evb_pico_side.png rename to boards/wiznet/w5500_evb_pico/doc/img/w5500_evb_pico_side.png diff --git a/boards/arm/w5500_evb_pico/doc/index.rst b/boards/wiznet/w5500_evb_pico/doc/index.rst similarity index 100% rename from boards/arm/w5500_evb_pico/doc/index.rst rename to boards/wiznet/w5500_evb_pico/doc/index.rst diff --git a/boards/arm/w5500_evb_pico/support/openocd.cfg b/boards/wiznet/w5500_evb_pico/support/openocd.cfg similarity index 100% rename from boards/arm/w5500_evb_pico/support/openocd.cfg rename to boards/wiznet/w5500_evb_pico/support/openocd.cfg diff --git a/boards/arm/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi b/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi similarity index 100% rename from boards/arm/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi rename to boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi diff --git a/boards/arm/w5500_evb_pico/w5500_evb_pico.dts b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts similarity index 100% rename from boards/arm/w5500_evb_pico/w5500_evb_pico.dts rename to boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts diff --git a/boards/arm/w5500_evb_pico/w5500_evb_pico.yaml b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.yaml similarity index 100% rename from boards/arm/w5500_evb_pico/w5500_evb_pico.yaml rename to boards/wiznet/w5500_evb_pico/w5500_evb_pico.yaml diff --git a/boards/arm/w5500_evb_pico/w5500_evb_pico_defconfig b/boards/wiznet/w5500_evb_pico/w5500_evb_pico_defconfig similarity index 77% rename from boards/arm/w5500_evb_pico/w5500_evb_pico_defconfig rename to boards/wiznet/w5500_evb_pico/w5500_evb_pico_defconfig index ec36f85040c..df003531af9 100644 --- a/boards/arm/w5500_evb_pico/w5500_evb_pico_defconfig +++ b/boards/wiznet/w5500_evb_pico/w5500_evb_pico_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_W5500_EVB_PICO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 CONFIG_SERIAL=y CONFIG_CONSOLE=y diff --git a/boards/x86/acrn/Kconfig.board b/boards/x86/acrn/Kconfig.board deleted file mode 100644 index e8fa3f42987..00000000000 --- a/boards/x86/acrn/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2019 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ACRN - bool "ACRN User OS" - depends on SOC_IA32 - select CPU_HAS_FPU - select X86_64 diff --git a/boards/x86/acrn/Kconfig.defconfig b/boards/x86/acrn/Kconfig.defconfig deleted file mode 100644 index a1a8936e38b..00000000000 --- a/boards/x86/acrn/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACRN - -config BOARD - default "acrn" - depends on BOARD_ACRN - -config MP_MAX_NUM_CPUS - default 2 - -config HEAP_MEM_POOL_ADD_SIZE_ACPI - default 32768 - depends on ACPI - -endif diff --git a/boards/x86/acrn/doc/index.rst b/boards/x86/acrn/doc/index.rst deleted file mode 100644 index 2bdaa96a817..00000000000 --- a/boards/x86/acrn/doc/index.rst +++ /dev/null @@ -1,302 +0,0 @@ -Building and Running Zephyr with ACRN -##################################### - -Zephyr's is capable of running as a guest under the x86 ACRN -hypervisor (see https://projectacrn.org/). The process for getting -this to work is somewhat involved, however. - -ACRN hypervisor supports a hybrid scenario where Zephyr runs in a so- -called "pre-launched" mode. This means Zephyr will access the ACRN -hypervisor directly without involving the SOS VM. This is the most -practical user scenario in the real world because Zephyr's real-time -and safety capability can be assured without influence from other -VMs. The following figure from ACRN's official documentation shows -how a hybrid scenario works: - -.. figure:: ACRN-Hybrid.jpg - :align: center - :alt: ACRN Hybrid User Scenario - :figclass: align-center - - ACRN Hybrid User Scenario - -In this tutorial, we will show you how to build a minimal running instance of Zephyr -and ACRN hypervisor to demonstrate that it works successfully. To learn more about -other features of ACRN, such as building and using the SOS VM or other guest VMs, -please refer to the Getting Started Guide for ACRN: -https://projectacrn.github.io/latest/tutorials/using_hybrid_mode_on_nuc.html - -Build your Zephyr App -********************* - -First, build the Zephyr application you want to run in ACRN as you -normally would, selecting an appropriate board: - - .. code-block:: console - - west build -b acrn_ehl_crb samples/hello_world - -In this tutorial, we will use the Intel Elkhart Lake Reference Board -(`EHL`_ CRB) since it is one of the suggested platforms for this -type of scenario. Use ``acrn_ehl_crb`` as the target board parameter. - -Note the kconfig output in ``build/zephyr/.config``, you will need to -reference that to configure ACRN later. - -The Zephyr build artifact you will need is ``build/zephyr/zephyr.bin``, -which is a raw memory image. Unlike other x86 targets, you do not -want to use ``zephyr.elf``! - -Configure and build ACRN -************************ - -First you need the source code, clone from: - - .. code-block:: console - - git clone https://github.com/projectacrn/acrn-hypervisor - -We suggest that you use versions v2.5.1 or later of the ACRN hypervisor -as they have better support for SMP in Zephyr. - -Like Zephyr, ACRN favors build-time configuration management instead -of runtime probing or control. Unlike Zephyr, ACRN has single large -configuration files instead of small easily-merged configuration -elements like kconfig defconfig files or devicetree includes. You -have to edit a big XML file to match your Zephyr configuration. -Choose an ACRN host config that matches your hardware ("ehl-crb-b" in -this case). Then find the relevant file in -``misc/config_tools/data//hybrid.xml``. - -First, find the list of ```` declarations. Each has an ``id=`` -attribute. For testing Zephyr, you will want to make sure that the -Zephyr image is ID zero. This allows you to launch ACRN with just one -VM image and avoids the need to needlessly copy large Linux blobs into -the boot filesystem. Under currently tested configurations, Zephyr -will always have a "vm_type" tag of "SAFETY_VM". - -Configure Zephyr Memory Layout -============================== - -Next, locate the load address of the Zephyr image and its entry point -address. These have to be configured manually in ACRN. Traditionally -Zephyr distributes itself as an ELF image where these addresses can be -automatically extracted, but ACRN does not know how to do that, it -only knows how to load a single contiguous region of data into memory -and jump to a specific address. - -Find the "..." tag that will look something like this: - - .. code-block:: xml - - - Zephyr - KERNEL_ZEPHYR - Zephyr_RawImage - - - 0x1000 - 0x1000 - - -The ``kern_load_addr`` tag must match the Zephyr LOCORE_BASE symbol -found in include/arch/x86/memory.ld. This is currently 0x1000 and -matches the default ACRN config. - -The ``kern_entry_addr`` tag must match the entry point in the built -``zephyr.elf`` file. You can find this with binutils, for example: - - .. code-block:: console - - $ objdump -f build/zephyr/zephyr.elf - - build/zephyr/zephyr.elf: file format elf64-x86-64 - architecture: i386:x86-64, flags 0x00000012: - EXEC_P, HAS_SYMS - start address 0x0000000000001000 - -By default this entry address is the same, at 0x1000. This has not -always been true of all configurations, however, and will likely -change in the future. - -Configure Zephyr CPUs -===================== - -Now you need to configure the CPU environment ACRN presents to the -guest. By default Zephyr builds in SMP mode, but ACRN's default -configuration gives it only one CPU. Find the value of -``CONFIG_MP_MAX_NUM_CPUS`` in the Zephyr .config file give the guest that -many CPUs in the ```` tag. For example: - - .. code-block:: xml - - - SAFETY_VM - ACRN PRE-LAUNCHED VM0 - - 0 - - - 0 - 1 - - ... - - 0 - 0 - - ... - - -To use SMP, we have to change the pcpu_id of VM0 to 0 and 1. -This configures ACRN to run Zephyr on CPU0 and CPU1. The ACRN hypervisor -and Zephyr application will not boot successfully without this change. -If you plan to run Zephyr with one CPU only, you can skip it. - -Since Zephyr is using CPU0 and CPU1, we also have to change -VM1's configuration so it runs on CPU2 and CPU3. If your ACRN setup has -additional VMs, you should change their configurations as well. - - .. code-block:: xml - - - SOS_VM - ACRN SOS VM - - 0 - - - 2 - 3 - - - 0 - 0 - - ... - - -Note that these indexes are physical CPUs on the host. When -configuring multiple guests, you probably don't want to overlap these -assignments with other guests. But for testing Zephyr simply using -CPUs 0 and 1 works fine. (Note that ehl-crb-b has four physical CPUs, -so configuring all of 0-3 will work fine too, but leave no space for -other guests to have dedicated CPUs). - -Build ACRN -========== - -Once configuration is complete, ACRN builds fairly cleanly: - - .. code-block:: console - - $ make -j BOARD=ehl-crb-b SCENARIO=hybrid - -The only build artifact you need is the ACRN multiboot image in -``build/hypervisor/acrn.bin`` - -Assemble EFI Boot Media -*********************** - -ACRN will boot on the hardware via the GNU GRUB bootloader, which is -itself launched from the EFI firmware. These need to be configured -correctly. - -Locate GRUB -=========== - -First, you will need a GRUB EFI binary that corresponds to your -hardware. In many cases, a simple upstream build from source or a -copy from a friendly Linux distribution will work. In some cases it -will not, however, and GRUB will need to be specially patched for -specific hardware. Contact your hardware support team (pause for -laughter) for clear instructions for how to build a working GRUB. In -practice you may just need to ask around and copy a binary from the -last test that worked for someone. - -Create EFI Boot Filesystem -========================== - -Now attach your boot media (e.g. a USB stick on /dev/sdb, your -hardware may differ!) to a Linux system and create an EFI boot -partition (type code 0xEF) large enough to store your boot artifacts. -This command feeds the relevant commands to fdisk directly, but you -can type them yourself if you like: - - .. code-block:: console - - # for i in n p 1 "" "" t ef w; do echo $i; done | fdisk /dev/sdb - ... - - -Now create a FAT filesystem in the new partition and mount it: - - .. code-block:: console - - # mkfs.vfat -n ACRN_ZEPHYR /dev/sdb1 - # mkdir -p /mnt/acrn - # mount /dev/sdb1 /mnt/acrn - -Copy Images and Configure GRUB -============================== - -ACRN does not have access to a runtime filesystem of its own. It -receives its guest VMs (i.e. zephyr.bin) as GRUB "multiboot" modules. -This means that we must rely on GRUB's filesystem driver. The three -files (GRUB, ACRN and Zephyr) all need to be copied into the -"/efi/boot" directory of the boot media. Note that GRUB must be named -"bootx64.efi" for the firmware to recognize it as the bootloader: - - .. code-block:: console - - # mkdir -p /mnt/acrn/efi/boot - # cp $PATH_TO_GRUB_BINARY /mnt/acrn/efi/boot/bootx64.efi - # cp $ZEPHYR_BASE/build/zephyr/zephyr.bin /mnt/acrn/efi/boot/ - # cp $PATH_TO_ACRN/build/hypervisor/acrn.bin /mnt/acrn/efi/boot/ - -At boot, GRUB will load a "efi/boot/grub.cfg" file for its runtime -configuration instructions (a feature, ironically, that both ACRN and -Zephyr lack!). This needs to load acrn.bin as the boot target and -pass it the zephyr.bin file as its first module (because Zephyr was -configured as ```` above). This minimal configuration will -work fine for all but the weirdest hardware (i.e. "hd0" is virtually -always the boot filesystem from which grub loaded), no need to fiddle -with GRUB plugins or menus or timeouts: - - .. code-block:: console - - # cat > /mnt/acrn/efi/boot/grub.cfg<vm_console 0 - - ----- Entering VM 0 Shell ----- - *** Booting Zephyr OS build v2.6.0-rc1-324-g1a03783861ad *** - Hello World! acrn - - -.. _EHL: https://www.intel.com/content/www/us/en/products/docs/processors/embedded/enhanced-for-iot-platform-brief.html diff --git a/boards/x86/index.rst b/boards/x86/index.rst deleted file mode 100644 index f7321566591..00000000000 --- a/boards/x86/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-x86: - -x86 Boards -########## - -.. toctree:: - :maxdepth: 1 - :glob: - - [!common]*/**/* diff --git a/boards/x86/intel_adl/CMakeLists.txt b/boards/x86/intel_adl/CMakeLists.txt deleted file mode 100644 index 2dc5afcc323..00000000000 --- a/boards/x86/intel_adl/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Create an EFI image -if(CONFIG_BUILD_OUTPUT_EFI) -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py - -c ${CMAKE_C_COMPILER} - -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include - -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf - $<$:--verbose> - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} -) -endif() diff --git a/boards/x86/intel_adl/Kconfig.board b/boards/x86/intel_adl/Kconfig.board deleted file mode 100644 index 591da3261f2..00000000000 --- a/boards/x86/intel_adl/Kconfig.board +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_ADL_CRB - bool "Alder Lake CRB" - depends on SOC_ALDER_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT - -config BOARD_INTEL_ADL_RVP - bool "Alder Lake RVP" - depends on SOC_ALDER_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT - -config BOARD_UP_SQUARED_PRO_7000 - bool "UP SQUARED PRO 7000 board" - depends on SOC_ALDER_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT diff --git a/boards/x86/intel_adl/Kconfig.defconfig b/boards/x86/intel_adl/Kconfig.defconfig deleted file mode 100644 index 5a61d2f552e..00000000000 --- a/boards/x86/intel_adl/Kconfig.defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP || BOARD_UP_SQUARED_PRO_7000 - -config BOARD - default "intel_adl_crb" if BOARD_INTEL_ADL_CRB - default "intel_adl_rvp" if BOARD_INTEL_ADL_RVP - default "up_squared_pro_7000" if BOARD_UP_SQUARED_PRO_7000 - -config BUILD_OUTPUT_STRIPPED - default y - -config MP_MAX_NUM_CPUS - default 2 - -# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1900000000 if APIC_TSC_DEADLINE_TIMER - default 1900000000 if APIC_TIMER_TSC - default 19200000 - -if APIC_TIMER -config APIC_TIMER_IRQ - default 24 -config APIC_TIMER_TSC_M - default 3 -config APIC_TIMER_TSC_N - default 249 -endif - -config ACPI - default y - -if ACPI -config HEAP_MEM_POOL_ADD_SIZE_ACPI - default 64000000 -config MAIN_STACK_SIZE - default 320000 - -if SHELL -config SHELL_STACK_SIZE - default 320000 -endif # SHELL -endif # ACPI - -if DMA -config DMA_64BIT - default y -config DMA_DW_HW_LLI - default n -config DMA_DW_CHANNEL_COUNT - default 2 -endif - -config UART_NS16550_INTEL_LPSS_DMA - default y - -endif # BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP || BOARD_UP_SQUARED_PRO_7000 diff --git a/boards/x86/intel_adl/doc/index.rst b/boards/x86/intel_adl/doc/index.rst deleted file mode 100644 index 63a518248b8..00000000000 --- a/boards/x86/intel_adl/doc/index.rst +++ /dev/null @@ -1,65 +0,0 @@ -.. _intel_adl_n: - -Alder Lake N -############ - -Overview -******** -Alder Lake processor is a 64-bit multi-core processor built on 10-nanometer -technology process. - -Currently supported is N-processor line, Single Chip Platform that consists of -the Processor Die and Alder Lake N Platform Controller Hub (ADL-N PCH) Die on -the same package as Multi-Chip Package (MCP). - -Proposed branding for Adler Lake N is Intel Processor (N100,N200) and -Intel Core i3 (N300, N305). - -Alder Lake N Customer Reference Board (ADL-N CRB) and Alder Lake Reference -Validation Platform (ADL-N RVP) are example implementations of compact single -board computer with high performance for IoT edge devices. - -This board configuration enables kernel support for the Alder Lake N boards. - -Hardware -******** - -General information about the board can be found at the `INTEL_ADL`_ website. - -Connections and IOs -=================== - -Refer to the `INTEL_ADL`_ website for more information. - -Programming and Debugging -************************* -Use the following procedures for booting an image for an Alder Lake N CRB board. - -.. contents:: - :depth: 1 - :local: - :backlinks: top - -Build Zephyr application -======================== - -#. Build a Zephyr application; for instance, to build the ``hello_world`` - application for Alder Lake N CRB: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: intel_adl_crb - :goals: build - - .. note:: - - A Zephyr EFI image file named :file:`zephyr.efi` is automatically - created in the build directory after the application is built. - -Booting the Alder Lake N CRB Board using UEFI -============================================= - -.. include:: ../../common/efi_boot.rst - :start-after: start_include_here - -.. _INTEL_ADL: https://edc.intel.com/content/www/us/en/design/products/platforms/processor-and-core-i3-n-series-datasheet-volume-1-of-2/ diff --git a/boards/x86/intel_ehl/CMakeLists.txt b/boards/x86/intel_ehl/CMakeLists.txt deleted file mode 100644 index 2dc5afcc323..00000000000 --- a/boards/x86/intel_ehl/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Create an EFI image -if(CONFIG_BUILD_OUTPUT_EFI) -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py - -c ${CMAKE_C_COMPILER} - -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include - -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf - $<$:--verbose> - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} -) -endif() diff --git a/boards/x86/intel_ehl/Kconfig.board b/boards/x86/intel_ehl/Kconfig.board deleted file mode 100644 index a04a9973eb0..00000000000 --- a/boards/x86/intel_ehl/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_EHL_CRB - bool "Elkhart Lake CRB" - depends on SOC_ELKHART_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT - -config BOARD_INTEL_EHL_CRB_SBL - bool "Elkhart Lake CRB (with Slim Bootloader)" - depends on SOC_ELKHART_LAKE - select X86_64 diff --git a/boards/x86/intel_ehl/Kconfig.defconfig b/boards/x86/intel_ehl/Kconfig.defconfig deleted file mode 100644 index ae8270faa64..00000000000 --- a/boards/x86/intel_ehl/Kconfig.defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_EHL_CRB || BOARD_INTEL_EHL_CRB_SBL - -config BOARD - default "intel_ehl_crb_sbl" if BOARD_INTEL_EHL_CRB_SBL - default "intel_ehl_crb" - -config BUILD_OUTPUT_STRIPPED - default y - -config MP_MAX_NUM_CPUS - default 2 - -if BOARD_INTEL_EHL_CRB_SBL -config SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN - depends on SHELL_BACKEND_SERIAL - default n -endif - -config HEAP_MEM_POOL_ADD_SIZE_ACPI - default 2097152 - depends on ACPI - -# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1900000000 if APIC_TSC_DEADLINE_TIMER - default 1900000000 if APIC_TIMER_TSC - default 19200000 - -if APIC_TIMER -config APIC_TIMER_IRQ - default 24 -config APIC_TIMER_TSC_M - default 3 -config APIC_TIMER_TSC_N - default 249 -endif - -endif # BOARD_INTEL_EHL_CRB || BOARD_INTEL_EHL_CRB_SBL diff --git a/boards/x86/intel_ehl/doc/index.rst b/boards/x86/intel_ehl/doc/index.rst deleted file mode 100644 index 1aa8f530155..00000000000 --- a/boards/x86/intel_ehl/doc/index.rst +++ /dev/null @@ -1,89 +0,0 @@ -.. _intel_ehl_crb: - -Elkhart Lake CRB -################ - -Overview -******** -Elkhart Lake Reference Board (EHL CRB) is an example implementation of a -compact single board computer with high performance for IoT edge devices. - -This board configuration enables kernel support for the `EHL`_ board. - -.. note:: - This board configuration works on the variant of `EHL`_ - boards containing Intel |reg| Atom |trade| SoC. - -Hardware -******** - -General information about the board can be found at the `EHL`_ website. - -.. include:: ../../../../soc/x86/elkhart_lake/doc/supported_features.txt - - -Connections and IOs -=================== - -Refer to the `EHL`_ website for more information. - -Programming and Debugging -************************* -Use the following procedures for booting an image on a EHL CRB board. - -.. contents:: - :depth: 1 - :local: - :backlinks: top - -Build Zephyr application -======================== - -#. Build a Zephyr application; for instance, to build the ``hello_world`` - application on Elkhart Lake CRB: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: intel_ehl_crb - :goals: build - - .. note:: - - A Zephyr EFI image file named :file:`zephyr.efi` is automatically - created in the build directory after the application is built. - -Booting the Elkhart Lake CRB Board using UEFI -============================================= - -.. include:: ../../common/efi_boot.rst - :start-after: start_include_here - -Booting the Elkhart Lake CRB Board over network -=============================================== - -.. include:: ../../common/net_boot.rst - :start-after: start_include_here - -.. note:: - To enable PXE boot for Elkhart Lake CRB board do the following: - - #. Enable boot from PXE. Go to EFI shell and make sure that the first boot - option is ``UEFI PXEv4``. - - .. code-block:: console - - Shell> bcfg boot dump - Option: 00. Variable: Boot0007 - Desc - UEFI PXEv4 (MAC:6805CABC1997) - DevPath - PciRoot(0x0)/Pci(0x1C,0x0)/Pci(0x0,0x0)/MAC(6805CABC1997,0x0)/IPv4(0.0.0.0) - Optional- Y - ... - - #. If UEFI PXEv4 is not the first boot option use ``bcfg boot mv`` command to - change boot order - - .. code-block:: console - - Shell> bcfg boot mv 7 0 - -.. _EHL: https://www.intel.com/content/www/us/en/products/docs/processors/embedded/enhanced-for-iot-platform-brief.html diff --git a/boards/x86/intel_ish/Kconfig.board b/boards/x86/intel_ish/Kconfig.board deleted file mode 100644 index 77962495a12..00000000000 --- a/boards/x86/intel_ish/Kconfig.board +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_INTEL_ISH_5_4_1 - bool "Intel ISH 5.4.1 board" - depends on SOC_INTEL_ISH_5_4_1 - -config BOARD_INTEL_ISH_5_6_0 - bool "Intel ISH 5.6.0 board" - depends on SOC_INTEL_ISH_5_6_0 - -config BOARD_INTEL_ISH_5_8_0 - bool "Intel ISH 5.8.0 board" - depends on SOC_INTEL_ISH_5_8_0 diff --git a/boards/x86/intel_ish/Kconfig.defconfig b/boards/x86/intel_ish/Kconfig.defconfig deleted file mode 100644 index 1f3d6809643..00000000000 --- a/boards/x86/intel_ish/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_INTEL_ISH_5_4_1 || BOARD_INTEL_ISH_5_6_0 || BOARD_INTEL_ISH_5_8_0 - -config BOARD - default "intel_ish_5_4_1" if BOARD_INTEL_ISH_5_4_1 - default "intel_ish_5_6_0" if BOARD_INTEL_ISH_5_6_0 - default "intel_ish_5_8_0" if BOARD_INTEL_ISH_5_8_0 - -if TEST -config TEST_EXTRA_STACK_SIZE - int - default 1024 -endif # TEST - -config SYS_CLOCK_TICKS_PER_SEC - default 2048 if HPET_TIMER # HPET is 32768 HZ - -endif # BOARD_INTEL_ISH_5_4_1 || BOARD_INTEL_ISH_5_6_0 || BOARD_INTEL_ISH_5_8_0 diff --git a/boards/x86/intel_ish/doc/index.rst b/boards/x86/intel_ish/doc/index.rst deleted file mode 100644 index a3fc6f540dc..00000000000 --- a/boards/x86/intel_ish/doc/index.rst +++ /dev/null @@ -1,79 +0,0 @@ -.. _intel_ish: - -Intel Integrated Sensor Hub (ISH) -################################# - -Overview -******** -Intel Integrated Sensor Hub (ISH) is a lower-power/always-on co-processor -inside many Intel Processors. It helps offload sensor processing tasks from -the core processor for better power saving. - -Hardware -******** - -- LMT MinuteIA Core: - - - 16KB instruction cache and 16KB data cache. - - 640KB SRAM space for code and data - implemented as L2 SRAM. - - 8KB AON RF space for code resident during deep D0i2/3 PG states. - -- Interface-to-Sensor peripherals (I2C, SPI, UART, I3C, GPIO, DMA). -- Inter Process Communications (IPC) to core processor and other IP processors. - -.. include:: ../../../../soc/x86/intel_ish/doc/supported_features.txt - -Programming and Debugging -************************* -Use the following procedures for booting an ISH image on a ADL RVP board -for Chrome. - -.. contents:: - :depth: 1 - :local: - :backlinks: top - -Build Zephyr application -======================== - -#. Build a Zephyr application; for instance, to build the ``hello_world`` - application for ISH 5.4.1 on Intel ADL Processor: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: intel_ish_5_4_1 - :goals: build - - .. note:: - - A Zephyr image file named :file:`ish_fw.bin` is automatically - created in the build directory after the application is built. - -Run ish_fw.bin on ADL RVP board for Chrome -========================================== - -- Power on the ADL RVP board. -- Log in Chrome OS. (Note: the user must have root access right, see `Developer Mode`_) -- Re-mount the root filesystem as read-write: - -.. code-block:: console - - $ mount -o remount,rw / - -- If re-mount fails, execute below commands to Remove rootfs verification: - -.. code-block:: console - - $ /usr/share/vboot/bin/make_dev_ssd.sh --remove_rootfs_verification --partitions - $ reboot - -- Go to the ISH firmware direcoty: - -.. code-block:: console - - $ cd /lib/firmware/intel - -- Relace the file adlrvp_ish.bin with zephyr image built out, ish_fw.bin. -- Reboot, then observe Zephyr log output via ISH UART0. - -.. _Developer Mode: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_mode.md diff --git a/boards/x86/intel_ish/intel_ish_5_4_1_defconfig b/boards/x86/intel_ish/intel_ish_5_4_1_defconfig deleted file mode 100644 index 527466ad337..00000000000 --- a/boards/x86/intel_ish/intel_ish_5_4_1_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_FAMILY_INTEL_ISH=y -CONFIG_SOC_SERIES_INTEL_ISH5=y -CONFIG_SOC_INTEL_ISH_5_4_1=y -CONFIG_BOARD_INTEL_ISH_5_4_1=y - -# uart & console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/x86/intel_ish/intel_ish_5_6_0_defconfig b/boards/x86/intel_ish/intel_ish_5_6_0_defconfig deleted file mode 100644 index 74b00676d39..00000000000 --- a/boards/x86/intel_ish/intel_ish_5_6_0_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_FAMILY_INTEL_ISH=y -CONFIG_SOC_SERIES_INTEL_ISH5=y -CONFIG_SOC_INTEL_ISH_5_6_0=y -CONFIG_BOARD_INTEL_ISH_5_6_0=y - -# uart & console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/x86/intel_ish/intel_ish_5_8_0_defconfig b/boards/x86/intel_ish/intel_ish_5_8_0_defconfig deleted file mode 100644 index ee319557f76..00000000000 --- a/boards/x86/intel_ish/intel_ish_5_8_0_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_FAMILY_INTEL_ISH=y -CONFIG_SOC_SERIES_INTEL_ISH5=y -CONFIG_SOC_INTEL_ISH_5_8_0=y -CONFIG_BOARD_INTEL_ISH_5_8_0=y - -# uart & console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/x86/intel_rpl/CMakeLists.txt b/boards/x86/intel_rpl/CMakeLists.txt deleted file mode 100644 index 2dc5afcc323..00000000000 --- a/boards/x86/intel_rpl/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Create an EFI image -if(CONFIG_BUILD_OUTPUT_EFI) -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py - -c ${CMAKE_C_COMPILER} - -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include - -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf - $<$:--verbose> - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} -) -endif() diff --git a/boards/x86/intel_rpl/Kconfig.board b/boards/x86/intel_rpl/Kconfig.board deleted file mode 100644 index 0424004d10b..00000000000 --- a/boards/x86/intel_rpl/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022-2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_RPL_S_CRB - bool "Raptor Lake S CRB" - depends on SOC_RAPTOR_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT - -config BOARD_INTEL_RPL_P_CRB - bool "Raptor Lake P CRB" - depends on SOC_RAPTOR_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT diff --git a/boards/x86/intel_rpl/Kconfig.defconfig b/boards/x86/intel_rpl/Kconfig.defconfig deleted file mode 100644 index 0458aef89be..00000000000 --- a/boards/x86/intel_rpl/Kconfig.defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# Copyright (c) 2022-2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_RPL_S_CRB || BOARD_INTEL_RPL_P_CRB - -config BOARD - default "intel_rpl_p_crb" if BOARD_INTEL_RPL_P_CRB - default "intel_rpl_s_crb" if BOARD_INTEL_RPL_S_CRB - -config BUILD_OUTPUT_STRIPPED - default y - -config MP_MAX_NUM_CPUS - default 2 - -# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1900000000 if APIC_TSC_DEADLINE_TIMER - default 1900000000 if APIC_TIMER_TSC - default 19200000 - -if APIC_TIMER -config APIC_TIMER_IRQ - default 24 -config APIC_TIMER_TSC_M - default 3 -config APIC_TIMER_TSC_N - default 249 -endif - -config ACPI - default y - -if ACPI -config HEAP_MEM_POOL_ADD_SIZE_ACPI - default 64000000 -config MAIN_STACK_SIZE - default 320000 - -if SHELL -config SHELL_STACK_SIZE - default 320000 -endif # SHELL -endif # ACPI - -if DMA -config DMA_64BIT - default y -config DMA_DW_HW_LLI - default n -config DMA_DW_CHANNEL_COUNT - default 2 -endif - -config UART_NS16550_INTEL_LPSS_DMA - default y if BOARD_INTEL_RPL_S_CRB - -if SHELL -config SHELL_STACK_SIZE - default 320000 -endif - -endif # BOARD_INTEL_RPL_S_CRB || BOARD_INTEL_RPL_P_CRB diff --git a/boards/x86/intel_rpl/doc/index.rst b/boards/x86/intel_rpl/doc/index.rst deleted file mode 100644 index 7c3d7758484..00000000000 --- a/boards/x86/intel_rpl/doc/index.rst +++ /dev/null @@ -1,75 +0,0 @@ -.. _intel_rpl_crb: - -Raptor Lake CRB -############### - -Overview -******** -Raptor Lake processor is a 13th generation 64-bit multi-core processor built -on a 10-nanometer technology process. Raptor Lake is based on a Hybrid -architecture, utilizing P-cores for performance and E-Cores for efficiency. - -Raptor Lake S and Raptor Lake P processor lines are supported. - -The S-Processor line is a 2-Chip Platform that includes the Processor Die and -Platform Controller Hub (PCH-S) Die in the Package. - -The P-Processor line is a 2-Die Multi Chip Package (MCP) that includes the -Processor Die and Platform Controller Hub (PCH-P) Die on the same package as -the Processor Die. - -For more information about Raptor Lake Processor lines, P-cores, and E-cores -please refer to `RPL`_. - -Raptor Lake Customer Reference Board (RPL CRB) is an example implementation of a -compact single board computer with high performance for IoT edge devices. The -supported boards are `intel_rpl_s_crb` and `intel_rpl_p_crb`. - -These board configurations enable kernel support for the supported Raptor Lake -boards. - -Hardware -******** - -General information about the board can be found at the `RPL`_. - -.. include:: ../../../../soc/x86/raptor_lake/doc/supported_features.txt - - -Connections and IOs -=================== - -Refer to the `RPL`_ for more information. - -Programming and Debugging -************************* -Use the following procedures for booting an image on an RPL CRB board. - -.. contents:: - :depth: 1 - :local: - :backlinks: top - -Build Zephyr application -======================== - -#. Build a Zephyr application; for instance, to build the ``hello_world`` - application on Raptor Lake S CRB: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: intel_rpl_s_crb - :goals: build - - .. note:: - - A Zephyr EFI image file named :file:`zephyr.efi` is automatically - created in the build directory after the application is built. - -Booting the Raptor Lake S CRB Board using UEFI -============================================== - -.. include:: ../../common/efi_boot.rst - :start-after: start_include_here - -.. _RPL: https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/ diff --git a/boards/x86/qemu_x86/CMakeLists.txt b/boards/x86/qemu_x86/CMakeLists.txt deleted file mode 100644 index de31c25a82e..00000000000 --- a/boards/x86/qemu_x86/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -if(CONFIG_BOARD_QEMU_X86_64 AND CONFIG_BUILD_OUTPUT_EFI) -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py - -c ${CMAKE_C_COMPILER} - -i ${ZEPHYR_BASE}/include - -o ${CMAKE_OBJCOPY} - -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf - $<$:--verbose> - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} -) -endif() diff --git a/boards/x86/qemu_x86/Kconfig.board b/boards/x86/qemu_x86/Kconfig.board deleted file mode 100644 index 275d1c69757..00000000000 --- a/boards/x86/qemu_x86/Kconfig.board +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_X86 - bool "QEMU x86" - depends on SOC_IA32 - select QEMU_TARGET - select CPU_HAS_FPU - select HAS_COVERAGE_SUPPORT - -config BOARD_QEMU_X86_64 - bool "QEMU x86_64" - depends on SOC_IA32 - select QEMU_TARGET - select X86_64 - select HAS_COVERAGE_SUPPORT - -config BOARD_QEMU_X86_LAKEMONT - bool "QEMU x86 (Lakemont)" - depends on SOC_LAKEMONT - select QEMU_TARGET - select CPU_HAS_FPU - select HAS_COVERAGE_SUPPORT - -config BOARD_QEMU_X86_TINY - bool "QEMU x86 (tiny memory)" - depends on SOC_IA32 - select QEMU_TARGET - select CPU_HAS_FPU - select HAS_COVERAGE_SUPPORT diff --git a/boards/x86/qemu_x86/Kconfig.defconfig b/boards/x86/qemu_x86/Kconfig.defconfig deleted file mode 100644 index 1e2b7af0a4d..00000000000 --- a/boards/x86/qemu_x86/Kconfig.defconfig +++ /dev/null @@ -1,114 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_X86 || BOARD_QEMU_X86_64 || BOARD_QEMU_X86_LAKEMONT || BOARD_QEMU_X86_TINY - -# The EEPROM emulator must be initialized after the flash simulator -config EEPROM_INIT_PRIORITY - default 60 - depends on EEPROM - -config BUILD_OUTPUT_BIN - default n - -endif # BOARD_QEMU_X86 || BOARD_QEMU_X86_64 || BOARD_QEMU_X86_LAKEMONT || BOARD_QEMU_X86_TINY - -if BOARD_QEMU_X86 - -config BOARD - default "qemu_x86" - -config FLASH_SIMULATOR - default y - depends on FLASH - -config KERNEL_VM_SIZE - default 0x10000000 if ACPI - -config MULTIBOOT - default y - -config MULTIBOOT_INFO - default y if MULTIBOOT - -config MULTIBOOT_MEMMAP - default y if MULTIBOOT - -config QEMU_ICOUNT - default n if HPET_TIMER && SHELL - -config QEMU_ICOUNT_SHIFT - default 5 - -endif # BOARD_QEMU_X86 - -if BOARD_QEMU_X86_64 - -config BOARD - default "qemu_x86_64" - -config KERNEL_VM_SIZE - default 0x10000000 if ACPI - -endif # BOARD_QEMU_X86_64 - -if BOARD_QEMU_X86_LAKEMONT - -config BOARD - default "qemu_x86_lakemont" - -config KERNEL_VM_SIZE - default 0x400000 - -config MULTIBOOT - # This is needed for QEMU to load the ELF image - default y - -config X86_PC_COMPATIBLE - # QEMU presents a PC-compatible machine - default y - -config QEMU_ICOUNT - default n if HPET_TIMER && SHELL - -config QEMU_ICOUNT_SHIFT - default 5 - -endif # BOARD_QEMU_X86_LAKEMONT - -if BOARD_QEMU_X86_TINY - -config BOARD - default "qemu_x86_tiny" - -config KERNEL_VM_SIZE - default 0x400000 - -config MULTIBOOT - # This is needed for QEMU to load the ELF image - default y - -config X86_PC_COMPATIBLE - # QEMU presents a PC-compatible machine - default y - -config QEMU_ICOUNT - default n if HPET_TIMER && SHELL - -config QEMU_ICOUNT_SHIFT - default 5 - -config HAVE_CUSTOM_LINKER_SCRIPT - default y - -config CUSTOM_LINKER_SCRIPT - default "${ZEPHYR_BASE}/boards/x86/qemu_x86/qemu_x86_tiny.ld" - -config X86_EXTRA_PAGE_TABLE_PAGES - # This is needed for gen_mmu.py to map the flash into memory - default 2 if DEMAND_PAGING && !LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT - -config DEMAND_PAGING_PAGE_FRAMES_RESERVE - # Need to accommodate the heap for newlib or common malloc in libc-hook.c - default 6 if NEWLIB_LIBC || (COMMON_LIBC_MALLOC && COMMON_LIBC_MALLOC_ARENA_SIZE != 0) - -endif # BOARD_QEMU_X86_TINY diff --git a/boards/x86/qemu_x86/board.cmake b/boards/x86/qemu_x86/board.cmake deleted file mode 100644 index 97a56a92770..00000000000 --- a/boards/x86/qemu_x86/board.cmake +++ /dev/null @@ -1,87 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -if(NOT CONFIG_REBOOT) - set(REBOOT_FLAG -no-reboot) -endif() - -if(CONFIG_X86_64) - set(QEMU_binary_suffix x86_64) - set(QEMU_CPU_TYPE_${ARCH} qemu64,+x2apic) - if("${CONFIG_MP_MAX_NUM_CPUS}" STREQUAL "1") - # icount works with 1 CPU so we can enable it here. - # FIXME: once this works across configs, remove this line and set - # CONFIG_QEMU_ICOUNT_SHIFT in defconfig instead. - list(APPEND QEMU_EXTRA_FLAGS -icount shift=5,align=off,sleep=off -rtc clock=vm) - endif() -else() - set(QEMU_CPU_TYPE_${ARCH} qemu32,+nx,+pae) -endif() - -if(CONFIG_XIP) - # Extra 4MB to emulate flash area - math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024 + 4") -elseif(CONFIG_BOARD_QEMU_X86_TINY AND CONFIG_DEMAND_PAGING - AND NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) - # Flash is at 4MB-8MB, so need this to be large enough - math(EXPR QEMU_MEMORY_SIZE_MB "8") -else() - math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024") -endif() - -set(QEMU_CPU_FLAGS "") -if(CONFIG_X86_MMX) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmx") - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmxext") -endif() -if(CONFIG_X86_SSE) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse") -endif() -if(CONFIG_X86_SSE2) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse2") -endif() -if(CONFIG_X86_SSE3) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "pni") -endif() -if(CONFIG_X86_SSSE3) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "ssse3") -endif() -if(CONFIG_X86_SSE41) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.1") -endif() -if(CONFIG_X86_SSE42) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.2") -endif() -if(CONFIG_X86_SSE4A) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4a") -endif() -if(NOT CONFIG_X86_64 AND CONFIG_CACHE_MANAGEMENT) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "clflush") -endif() - -set(QEMU_FLAGS_${ARCH} - -m ${QEMU_MEMORY_SIZE_MB} - -cpu ${QEMU_CPU_TYPE_${ARCH}}${QEMU_CPU_FLAGS} - -machine q35 - -device isa-debug-exit,iobase=0xf4,iosize=0x04 - ${REBOOT_FLAG} - -nographic - ) - -if(NOT CONFIG_ACPI) - list(APPEND QEMU_FLAGS_${ARCH} -no-acpi) -endif() - -# TODO: Support debug -# board_set_debugger_ifnset(qemu) -# debugserver: QEMU_EXTRA_FLAGS += -s -S -# debugserver: qemu - -if(CONFIG_BOARD_QEMU_X86_TINY AND CONFIG_DEMAND_PAGING - AND NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) - # This is to map the flash so it is accessible. - math(EXPR QEMU_FLASH_SIZE_KB "${CONFIG_FLASH_SIZE} * 1024") - set(X86_EXTRA_GEN_MMU_ARGUMENTS - --map ${CONFIG_FLASH_BASE_ADDRESS},${QEMU_FLASH_SIZE_KB},W) -endif() diff --git a/boards/x86/qemu_x86/qemu_x86_64_nokpti.yaml b/boards/x86/qemu_x86/qemu_x86_64_nokpti.yaml deleted file mode 100644 index 531ebd4d3e1..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_64_nokpti.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: qemu_x86_64_nokpti -name: QEMU Emulation for X86_64 (KPTI disabled) -type: qemu -arch: x86 -toolchain: - - zephyr - - xtools -supported: - - smp -simulation: qemu -testing: - default: true - only_tags: - - kernel - - userspace - ignore_tags: - - benchmark -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_64_nokpti_defconfig b/boards/x86/qemu_x86/qemu_x86_64_nokpti_defconfig deleted file mode 100644 index 1ca8daa5fa1..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_64_nokpti_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86_64=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_DEBUG_INFO=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_X86_MMU=y -CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_QEMU_ICOUNT=n -CONFIG_X86_KPTI=n diff --git a/boards/x86/qemu_x86/qemu_x86_nokpti.yaml b/boards/x86/qemu_x86/qemu_x86_nokpti.yaml deleted file mode 100644 index 75ab0d13d5f..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_nokpti.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: qemu_x86_nokpti -name: QEMU Emulation for X86 (KPTI disabled) -type: qemu -arch: x86 -simulation: qemu -toolchain: - - zephyr - - xtools -testing: - default: true - only_tags: - - kernel - - userspace - ignore_tags: - - benchmark -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_nokpti_defconfig b/boards/x86/qemu_x86/qemu_x86_nokpti_defconfig deleted file mode 100644 index 5423b62b679..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_nokpti_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y -CONFIG_SCHED_SCALABLE=y -CONFIG_WAITQ_SCALABLE=y -CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_X86_KPTI=n diff --git a/boards/x86/qemu_x86/qemu_x86_nommu.dts b/boards/x86/qemu_x86/qemu_x86_nommu.dts deleted file mode 100644 index cac68cd695e..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_nommu.dts +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include "qemu_x86.dts" diff --git a/boards/x86/qemu_x86/qemu_x86_nommu.yaml b/boards/x86/qemu_x86/qemu_x86_nommu.yaml deleted file mode 100644 index 8d7aee97b7e..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_nommu.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_x86_nommu -name: QEMU Emulation for X86 (MMU disabled) -type: qemu -arch: x86 -simulation: qemu -toolchain: - - zephyr - - xtools -testing: - default: true - only_tags: - - kernel - - userspace -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_nommu_defconfig b/boards/x86/qemu_x86/qemu_x86_nommu_defconfig deleted file mode 100644 index d485369c6cb..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_nommu_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_DEBUG_INFO=y diff --git a/boards/x86/qemu_x86/qemu_x86_nopae.yaml b/boards/x86/qemu_x86/qemu_x86_nopae.yaml deleted file mode 100644 index 7dbd449cebc..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_nopae.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: qemu_x86_nopae -name: QEMU Emulation for X86 (32-bit page tables) -type: qemu -arch: x86 -simulation: qemu -toolchain: - - zephyr - - xtools -testing: - default: true - only_tags: - - kernel - - userspace - ignore_tags: - - benchmark -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_nopae_defconfig b/boards/x86/qemu_x86/qemu_x86_nopae_defconfig deleted file mode 100644 index 15a109c056f..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_nopae_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y -CONFIG_SCHED_SCALABLE=y -CONFIG_WAITQ_SCALABLE=y -CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_X86_PAE=n diff --git a/boards/x86/qemu_x86/qemu_x86_tiny_768.conf b/boards/x86/qemu_x86/qemu_x86_tiny_768.conf deleted file mode 100644 index 583d6a85451..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_tiny_768.conf +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Intel Corporation. -# SPDX-License-Identifier: Apache-2.0 - -# Enable coverage regardless since this config for coverage only. -CONFIG_COVERAGE=y - -# Need more stack space due to coverage being enabled. -CONFIG_MAIN_STACK_SIZE=4096 -CONFIG_IDLE_STACK_SIZE=1024 diff --git a/boards/x86/qemu_x86/qemu_x86_tiny_768.overlay b/boards/x86/qemu_x86/qemu_x86_tiny_768.overlay deleted file mode 100644 index bb92000cb41..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_tiny_768.overlay +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Override with 768KB DRAM */ -&dram0 { - reg = < 0x100000 DT_SIZE_K(768) >; -}; diff --git a/boards/x86/qemu_x86/qemu_x86_virt.yaml b/boards/x86/qemu_x86/qemu_x86_virt.yaml deleted file mode 100644 index 1f3eb2fb18b..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_virt.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: qemu_x86_virt -name: QEMU Emulation for X86 (Run in Virtual Address Space) -type: qemu -arch: x86 -simulation: qemu -toolchain: - - zephyr - - xtools -testing: - default: true - only_tags: - - kernel - - userspace - ignore_tags: - - benchmark -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_virt_defconfig b/boards/x86/qemu_x86/qemu_x86_virt_defconfig deleted file mode 100644 index eabfab7a591..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_virt_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y -CONFIG_SCHED_SCALABLE=y -CONFIG_WAITQ_SCALABLE=y -CONFIG_X86_VERY_EARLY_CONSOLE=y - -CONFIG_SRAM_OFFSET=0x100000 -CONFIG_KERNEL_VM_SIZE=0x400000 -CONFIG_KERNEL_VM_BASE=0x40000000 -CONFIG_KERNEL_VM_OFFSET=0 - -CONFIG_LINKER_USE_BOOT_SECTION=y -CONFIG_LINKER_USE_PINNED_SECTION=y diff --git a/boards/x86/qemu_x86/qemu_x86_xip.yaml b/boards/x86/qemu_x86/qemu_x86_xip.yaml deleted file mode 100644 index c33acd4db16..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_xip.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: qemu_x86_xip -name: QEMU Emulation for X86 (XIP enabled) -type: qemu -arch: x86 -simulation: qemu -toolchain: - - zephyr - - xtools -testing: - default: true - only_tags: - - xip -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_xip_defconfig b/boards/x86/qemu_x86/qemu_x86_xip_defconfig deleted file mode 100644 index 42fd2677785..00000000000 --- a/boards/x86/qemu_x86/qemu_x86_xip_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_DEBUG_INFO=y -CONFIG_SCHED_SCALABLE=y -CONFIG_WAITQ_SCALABLE=y -CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_XIP=y diff --git a/boards/x86/qemu_x86/revision.cmake b/boards/x86/qemu_x86/revision.cmake deleted file mode 100644 index 96fc09545a1..00000000000 --- a/boards/x86/qemu_x86/revision.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2022 Intel Corporation. -# SPDX-License-Identifier: Apache-2.0 - -# We can't really do board_check_revision() here -# as it will apply to all qemu_x86* boards. diff --git a/boards/x86/up_squared/CMakeLists.txt b/boards/x86/up_squared/CMakeLists.txt deleted file mode 100644 index 2dc5afcc323..00000000000 --- a/boards/x86/up_squared/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Create an EFI image -if(CONFIG_BUILD_OUTPUT_EFI) -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py - -c ${CMAKE_C_COMPILER} - -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include - -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf - $<$:--verbose> - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} -) -endif() diff --git a/boards/x86/up_squared/Kconfig.board b/boards/x86/up_squared/Kconfig.board deleted file mode 100644 index c25c3e2857d..00000000000 --- a/boards/x86/up_squared/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UP_SQUARED - bool "UP Squared (x86_64)" - depends on SOC_APOLLO_LAKE - select X86_64 diff --git a/boards/x86/up_squared/Kconfig.defconfig b/boards/x86/up_squared/Kconfig.defconfig deleted file mode 100644 index e8eecbcc508..00000000000 --- a/boards/x86/up_squared/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UP_SQUARED - -config BOARD - default "up_squared" - -config MP_MAX_NUM_CPUS - default 2 if BOARD_UP_SQUARED - -config BUILD_OUTPUT_STRIPPED - default y - -# TSC on this board is 1.5936 GHz, HPET and APIC are 19.2 MHz -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1593600000 if APIC_TSC_DEADLINE_TIMER - default 1593600000 if APIC_TIMER_TSC - default 19200000 - -if APIC_TIMER -config APIC_TIMER_IRQ - default 24 -config APIC_TIMER_TSC_M - default 3 -config APIC_TIMER_TSC_N - default 249 -endif - -endif # BOARD_UP_SQUARED diff --git a/boards/x86/up_squared/doc/index.rst b/boards/x86/up_squared/doc/index.rst deleted file mode 100644 index bf40fa16ba2..00000000000 --- a/boards/x86/up_squared/doc/index.rst +++ /dev/null @@ -1,125 +0,0 @@ -.. _up_squared: - -UP Squared -########## - -Overview -******** - -UP |sup2| (UP Squared) is an ultra compact single board computer with high -performance and low power consumption. It features the latest Intel |reg| Apollo -Lake Celeron |trade| and Pentium |trade| Processors with only 4W of Scenario Design Power and -a powerful and flexible Intel |reg| FPGA Altera MAX 10 onboard. - -.. figure:: img/up_squared.jpg - :align: center - :alt: UP Squared - - Up Squared (Credit: https://up-board.org) - -This board configuration enables kernel support for the `UP Squared`_ board. - -.. note:: - This board configuration works on all three variants of `UP Squared`_ - boards containing Intel |reg| Pentium |trade| SoC, - Intel |reg| Celeron |trade| SoC, or Intel |reg| Atom |trade| SoC. - -Hardware -******** - -General information about the board can be found at the `UP Squared`_ website. - -.. include:: ../../../../soc/x86/apollo_lake/doc/supported_features.txt - -GPIO ----- - -GPIOs are exposed through the HAT header, and can be referred using -predefined macros such as ``UP2_HAT_PIN3``. The physical pins are -connected to the on-board FPGA acting as level shifter. Therefore, -to actually utilize these GPIO pins, the function of the pins and -directions (input/output) must be set in the BIOS. This can be -accomplished in BIOS, under menu ``Advanced``, and option -``HAT Configurations``. When a corresponding pin is set to act as -GPIO, there is an option to set the direction of the pin. This needs -to be set accordingly for the GPIO to function properly. - -Connections and IOs -=================== - -Refer to the `UP Squared`_ website and `UP Squared Pinout`_ website -for connection diagrams. - -Programming and Debugging -************************* - -Use the following procedures for booting an image on a UP Squared board. - -.. contents:: - :depth: 1 - :local: - :backlinks: top - -Build Zephyr application -======================== - -#. Build a Zephyr application; for instance, to build the ``hello_world`` - application on UP Squared: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: up_squared - :goals: build - - .. note:: - - A Zephyr EFI image file named :file:`zephyr.efi` is automatically - created in the build directory after the application is built. - -Booting the UP Squared Board using UEFI -======================================= - -.. include:: ../../common/efi_boot.rst - :start-after: start_include_here - -.. note:: - Refer to the `UP Squared Serial Console Wiki page - `_ for instructions on how to - connect serial console. - -.. note:: - You can safely ignore this message if it appears: - - .. code-block:: console - - WARNING: no console will be available to OS - -Booting the UP Squared Board over network -========================================= - -.. include:: ../../common/net_boot.rst - :start-after: start_include_here - -.. note:: - Refer to the `UP Squared Serial Console Wiki page - `_ for instructions on how to - connect serial console. - -.. note:: - To enable PXE boot for Up Squared board do the following: - - #. Enable network from BIOS settings. - - .. code-block:: console - - Advanced -> Network Stack Configuration -> Enable Network Stack -> Enable Ipv4 PXE Support - - #. Make network boot as the first boot option. - - .. code-block:: console - - Boot -> Boot Option #1 : [Network] - -.. _UP Squared: https://www.up-board.org/upsquared/specifications - -.. _UP Squared Pinout: https://wiki.up-community.org/Pinout diff --git a/boards/xen/index.rst b/boards/xen/index.rst new file mode 100644 index 00000000000..4f760a22fbe --- /dev/null +++ b/boards/xen/index.rst @@ -0,0 +1,10 @@ +.. _boards-xen: + +Xen Hypervisor +############## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/xen/xenvm/Kconfig.defconfig b/boards/xen/xenvm/Kconfig.defconfig new file mode 100644 index 00000000000..965dc9cda33 --- /dev/null +++ b/boards/xen/xenvm/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2020 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XENVM + +config BUILD_OUTPUT_BIN + default y + +config HEAP_MEM_POOL_SIZE + default 16384 if BOARD_XENVM_XENVM + +endif # BOARD_XENVM diff --git a/boards/xen/xenvm/Kconfig.xenvm b/boards/xen/xenvm/Kconfig.xenvm new file mode 100644 index 00000000000..e5393bbf957 --- /dev/null +++ b/boards/xen/xenvm/Kconfig.xenvm @@ -0,0 +1,5 @@ +# Copyright (c) 2020 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XENVM + select SOC_XENVM diff --git a/boards/xen/xenvm/board.yml b/boards/xen/xenvm/board.yml new file mode 100644 index 00000000000..5b5aec44c55 --- /dev/null +++ b/boards/xen/xenvm/board.yml @@ -0,0 +1,7 @@ +board: + name: xenvm + vendor: xen + socs: + - name: xenvm + variants: + - name: gicv3 diff --git a/boards/xen/xenvm/doc/index.rst b/boards/xen/xenvm/doc/index.rst new file mode 100644 index 00000000000..88221b582e7 --- /dev/null +++ b/boards/xen/xenvm/doc/index.rst @@ -0,0 +1,187 @@ +.. xenvm: + +ARMv8 Xen Virtual Machine Example +################################# + +Overview +******** + +This board allows to run Zephyr as Xen guest on any ARMv8 board that supports +ARM Virtualization Extensions. This is example configuration, as almost any VM +configuration is unique in many aspects. + +It provides minimal set of devices: + +* ARM Generic timer +* GICv2/GICv3 + +Hardware +******** +Supported Features +================== + +The following hardware features are supported: + ++--------------+-------------+----------------------+ +| Interface | Controller | Driver/Component | ++==============+=============+======================+ +| GIC | virtualized | interrupt controller | ++--------------+-------------+----------------------+ +| ARM TIMER | virtualized | system clock | ++--------------+-------------+----------------------+ + +The kernel currently does not support other hardware features on this platform. + +The default configuration for this board can be found in these files: + +- :zephyr_file:`boards/xen/xenvm/Kconfig.defconfig` +- :zephyr_file:`boards/xen/xenvm/xenvm_defconfig` + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 8.32 MHz. This is the +default value, which should be corrected for user's actual hardware. + +You can determine clock frequency of your ARM Generic Timer by inspecting Xen +boot log: + +:: + + (XEN) [ 0.147541] Generic Timer IRQ: phys=30 hyp=26 virt=27 Freq: 8320 KHz + +Interrupt Controller +-------------------- + +Depending on the version of the GIC on your hardware, you may choose one of the +following board configuration variants: + +- ``xenvm`` selects GICv2 +- ``xenvm//gicv3`` selects GICv3 + +CPU Core type +------------- + +Default core in this configuration is Cortex A72. Depending on yours actual +hardware you might want to change this option in the same way as Interrupt +Controller configuration. + +Known Problems or Limitations +============================== + +Xen configures guests in runtime by providing device tree that describes guest +environment. On other hand, Zephyr uses static configuration that should be know +at build time. So there are chances, that Zephyr image created with default +configuration would not boot on your hardware. In this case you need to update +configuration by altering device tree and Kconfig options. This will be covered +in detail in next section. + +Most of Xen-specific features are not supported at the moment. This includes: +* XenBus (under development) +* Xen PV drivers + +Now only following features are supported: +* Xen Enlighten memory page +* Xen event channels +* Xen PV console (2 versions: regular ring buffer based for DomU and consoleio for Dom0) +* Xen early console_io interface (mainly for debug purposes - requires debug version of Xen) +* Xen grant tables (granting access for own grants and map/unmap foreign grants) + +Building and Running +******************** + +Use this configuration to run basic Zephyr applications and kernel tests as Xen +guest, for example, with the :zephyr:code-sample:`synchronization` sample: + +- if your hardware is based on GICv2: + +.. code-block:: + + $ west build -b xenvm samples/synchronization + +- if your hardware is based on GICv3: + +.. code-block:: + + $ west build -b xenvm//gicv3 samples/synchronization + +This will build an image with the synchronization sample app. Next, you need to +create guest configuration file :code:`zephyr.conf`. There is example: + +.. code-block:: + + kernel="zephyr.bin" + name="zephyr" + vcpus=1 + memory=16 + gic_version="v2" + on_crash="preserve" + +When using ``xenvm//gicv3`` configuration, you need to remove the ``gic_version`` +parameter or set it to ``"v3"``. + +You need to upload both :code:`zephyr.bin` and :code:`zephyr.conf` to your Dom0 +and then you can run Zephyr by issuing + +.. code-block:: + + $ xl create zephyr.conf + +Next you need to attach to PV console: + +.. code-block:: + + $ xl console zephyr + +Also this can be performed via single command: + +.. code-block:: + + $ xl create -c zephyr.conf + +You will see Zephyr output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.4.0-1137-g5803ee1e8183 *** + thread_a: Hello World from cpu 0 on xenvm! + thread_b: Hello World from cpu 0 on xenvm! + thread_a: Hello World from cpu 0 on xenvm! + thread_b: Hello World from cpu 0 on xenvm! + thread_a: Hello World from cpu 0 on xenvm! + +Exit xen virtual console by pressing :kbd:`CTRL+]` + +Updating configuration +********************** + +As was said earlier, Xen describes hardware using device tree and expects that +guest will parse device tree in runtime. On other hand, Zephyr supports only +static, build time configuration. While provided configuration should work on +almost any ARMv8 host running in aarch64 mode, there is no guarantee, that Xen +will not change some values (like RAM base address) in the future. + +Also, frequency of system timer is board specific and should be updated when running +Zephyr xenvm image on new hardware. + +One can make Xen to dump generated DTB by using :code:`LIBXL_DEBUG_DUMP_DTB` +environment variable, like so: + +.. code-block:: + + $ LIBXL_DEBUG_DUMP_DTB=domu-libxl.dtb xl create zephyr.conf + +Then, generated "domu-libxl.dtb" file can be de-compiled using "dtc" tool. + +Use information from de-compiled DTB file to update all related entries in +provided "xenvm.dts" file. If memory layout is also changed, you may need to +update :code:`CONFIG_SRAM_BASE_ADDRESS` as well. + +References +********** + +`Xen ARM with Virtualization Extensions `_ + +`xl.conf (guest configuration file) manual `_ diff --git a/boards/arm64/xenvm/xenvm.dts b/boards/xen/xenvm/xenvm.dts similarity index 100% rename from boards/arm64/xenvm/xenvm.dts rename to boards/xen/xenvm/xenvm.dts diff --git a/boards/arm64/xenvm/xenvm.yaml b/boards/xen/xenvm/xenvm.yaml similarity index 100% rename from boards/arm64/xenvm/xenvm.yaml rename to boards/xen/xenvm/xenvm.yaml diff --git a/boards/arm64/xenvm/xenvm_defconfig b/boards/xen/xenvm/xenvm_defconfig similarity index 77% rename from boards/arm64/xenvm/xenvm_defconfig rename to boards/xen/xenvm/xenvm_defconfig index 39e8a20767c..38885a73413 100644 --- a/boards/arm64/xenvm/xenvm_defconfig +++ b/boards/xen/xenvm/xenvm_defconfig @@ -1,11 +1,7 @@ -CONFIG_SOC_XENVM=y -CONFIG_BOARD_XENVM=y - # Enable UART driver CONFIG_SERIAL=y CONFIG_MAX_XLAT_TABLES=24 -CONFIG_HEAP_MEM_POOL_SIZE=16384 # Enable console CONFIG_CONSOLE=y diff --git a/boards/arm64/xenvm/xenvm_gicv3.dts b/boards/xen/xenvm/xenvm_xenvm_gicv3.dts similarity index 100% rename from boards/arm64/xenvm/xenvm_gicv3.dts rename to boards/xen/xenvm/xenvm_xenvm_gicv3.dts diff --git a/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml b/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml new file mode 100644 index 00000000000..a680dd6d0cf --- /dev/null +++ b/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml @@ -0,0 +1,9 @@ +identifier: xenvm/xenvm/gicv3 +name: ARMv8 Xen Virtual Machine With GICv3 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 16384 +vendor: xen diff --git a/boards/xtensa/esp32_devkitc_wroom/Kconfig.board b/boards/xtensa/esp32_devkitc_wroom/Kconfig.board deleted file mode 100644 index a295f3bfc50..00000000000 --- a/boards/xtensa/esp32_devkitc_wroom/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32_DEVKITC_WROOM - bool "ESP32-DEVKITC-WROOM Development Board" - depends on SOC_SERIES_ESP32 - -config BOARD_ESP32_DEVKITC_WROOM_APPCPU - bool "ESP32 Board configuration for APPCPU (core 1)." - depends on SOC_SERIES_ESP32 && SOC_ESP32_APPCPU - -choice SOC_PART_NUMBER - default SOC_ESP32_WROOM_32UE_N4 -endchoice diff --git a/boards/xtensa/esp32_devkitc_wroom/Kconfig.defconfig b/boards/xtensa/esp32_devkitc_wroom/Kconfig.defconfig deleted file mode 100644 index aadb2d833f8..00000000000 --- a/boards/xtensa/esp32_devkitc_wroom/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# ESP32 board configuration - -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ESP32_DEVKITC_WROOM - -config BOARD - default "esp32_devkitc_wroom" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -endif # BOARD_ESP32_DEVKITC_WROOM - -if BOARD_ESP32_DEVKITC_WROOM_APPCPU - -config BOARD - default "esp32_devkitc_wroom_appcpu" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 4096 - -config KERNEL_BIN_NAME - default "esp32_appcpu_firmware" - -endif # BOARD_ESP32_DEVKITC_WROOM_APPCPU - -config ENTROPY_GENERATOR - default y diff --git a/boards/xtensa/esp32_devkitc_wroom/doc/index.rst b/boards/xtensa/esp32_devkitc_wroom/doc/index.rst deleted file mode 100644 index ceeb7d38ba9..00000000000 --- a/boards/xtensa/esp32_devkitc_wroom/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _esp32_devkitc_wroom: - -ESP32-DEVKITC-WROOM -################### - -Overview -******** - -ESP32-DEVKITC-WROOM is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a -Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32-WROOM is created and developed by Espressif Systems, a -Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. [1]_ - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz -- 520KB of SRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- Various peripherals: - - - 12-bit ADC with up to 18 channels - - 2x 8-bit DACs - - 10x touch sensors - - Temperature sensor - - 4x SPI - - 2x I2S - - 2x I2C - - 3x UART - - SD/SDIO/MMC host - - Slave (SDIO/SPI) - - Ethernet MAC - - CAN bus 2.0 - - IR (RX/TX) - - Motor PWM - - LED PWM with up to 16 channels - - Hall effect sensor - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -- 5uA deep sleep current - -.. figure:: img/esp32_devkitc_wroom.jpg - :align: center - :alt: ESP32-DEVKITC-WROOM - - ESP32-DevKitC-WROOM-32D DK - -Asymmetric Multiprocessing (AMP) -******************************** - -ESP32-DEVKITC-WROOM allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode -and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. - -Supported Features -================== - -Current Zephyr's ESP32-WROOM board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom - :goals: build - -The usual ``flash`` target will work with the ``esp32_devkitc_wroom`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32_devkitc_wroom - -Debugging ---------- - -ESP32-DEVKITC-WROOM support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -On the ESP-WROOM-32 DevKitC board, the JTAG pins are not run to a -standard connector (e.g. ARM 20-pin) and need to be manually connected -to the external programmer (e.g. a Flyswatter2): - -+------------+-----------+ -| ESP32 pin | JTAG pin | -+============+===========+ -| 3V3 | VTRef | -+------------+-----------+ -| EN | nTRST | -+------------+-----------+ -| IO14 | TMS | -+------------+-----------+ -| IO12 | TDI | -+------------+-----------+ -| GND | GND | -+------------+-----------+ -| IO13 | TCK | -+------------+-----------+ -| IO15 | TDO | -+------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom - :goals: debug - -Note on Debugging with GDB Stub -=============================== - -GDB stub is enabled on ESP32. - -* When adding breakpoints, please use hardware breakpoints with command - ``hbreak``. Command ``break`` uses software breakpoints which requires - modifying memory content to insert break/trap instructions. - This does not work as the code is on flash which cannot be randomly - accessed for modification. - -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD`: https://github.com/openocd-org/openocd - -References -********** - -.. [1] https://en.wikipedia.org/wiki/ESP32 -.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.dts b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.dts deleted file mode 100644 index a33384c2a5c..00000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.dts +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32_devkitc_wroom-pinctrl.dtsi" -#include -#include - -/ { - model = "Espressif ESP32-DEVKITC-WROOM-32D"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - sw0 = &button0; - watchdog0 = &wdt0; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&touch { - debounce-interval-ms = <30>; - href-microvolt = <2700000>; - lref-microvolt = <500000>; - href-atten-microvolt = <1000000>; - filter-mode = ; - filter-debounce-cnt = <1>; - filter-noise-thr = ; - filter-jitter-step = <4>; - filter-smooth-level = ; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&trng0 { - status = "okay"; -}; - -&psram0 { - status = "disabled"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.yaml b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.yaml deleted file mode 100644 index 19155f8a0d1..00000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.yaml +++ /dev/null @@ -1,25 +0,0 @@ -identifier: esp32_devkitc_wroom -name: ESP32-DevkitC-WROOM-32D -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - watchdog - - uart - - nvs - - pwm - - dac - - spi - - counter - - entropy - - input -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts deleted file mode 100644 index c58f39cd444..00000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include - -/ { - model = "esp32_wroom_appcpu"; - compatible = "espressif,esp32_appcpu"; - - chosen { - zephyr,sram = &sram0; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&trng0 { - status = "okay"; -}; diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml deleted file mode 100644 index 02f9916ef90..00000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: esp32_devkitc_wroom_appcpu -name: ESP32 DEVKITC WROOM APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp -vendor: espressif diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig deleted file mode 100644 index 81406ae4c49..00000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ESP32=y -CONFIG_SOC_ESP32_APPCPU=y -CONFIG_BOARD_ESP32_DEVKITC_WROOM_APPCPU=y - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_defconfig b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_defconfig deleted file mode 100644 index ead6203b86e..00000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32_DEVKITC_WROOM=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32_devkitc_wrover/Kconfig.board b/boards/xtensa/esp32_devkitc_wrover/Kconfig.board deleted file mode 100644 index 20e59ac10fe..00000000000 --- a/boards/xtensa/esp32_devkitc_wrover/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32_DEVKITC_WROVER - bool "ESP32-DEVKITC-WROVER-E Development board" - depends on SOC_SERIES_ESP32 - -config BOARD_ESP32_DEVKITC_WROVER_APPCPU - bool "ESP32 Board configuration for APPCPU (core 1)." - depends on SOC_SERIES_ESP32 && SOC_ESP32_APPCPU - -choice SOC_PART_NUMBER - default SOC_ESP32_WROVER_E_N4R8 -endchoice diff --git a/boards/xtensa/esp32_devkitc_wrover/Kconfig.defconfig b/boards/xtensa/esp32_devkitc_wrover/Kconfig.defconfig deleted file mode 100644 index 84b365c2b77..00000000000 --- a/boards/xtensa/esp32_devkitc_wrover/Kconfig.defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ESP32_DEVKITC_WROVER - -config BOARD - default "esp32_devkitc_wrover" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -endif # BOARD_ESP32_DEVKITC_WROVER - -if BOARD_ESP32_DEVKITC_WROVER_APPCPU - -config BOARD - default "esp32_devkitc_wrover_appcpu" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 4096 - -config KERNEL_BIN_NAME - default "esp32_appcpu_firmware" -endif - -config ENTROPY_GENERATOR - default y diff --git a/boards/xtensa/esp32_devkitc_wrover/doc/index.rst b/boards/xtensa/esp32_devkitc_wrover/doc/index.rst deleted file mode 100644 index ec59ab5c640..00000000000 --- a/boards/xtensa/esp32_devkitc_wrover/doc/index.rst +++ /dev/null @@ -1,296 +0,0 @@ -.. _esp32_devkitc_wrover: - -ESP32-DEVKITC-WROVER -#################### - -Overview -******** - -ESP32 is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a -Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32 is created and developed by Espressif Systems, a -Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. [1]_ - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz -- 520KB of SRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- Various peripherals: - - - 12-bit ADC with up to 18 channels - - 2x 8-bit DACs - - 10x touch sensors - - Temperature sensor - - 4x SPI - - 2x I2S - - 2x I2C - - 3x UART - - SD/SDIO/MMC host - - Slave (SDIO/SPI) - - Ethernet MAC - - CAN bus 2.0 - - IR (RX/TX) - - Motor PWM - - LED PWM with up to 16 channels - - Hall effect sensor - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -- 5uA deep sleep current - -.. figure:: img/esp32_devkitc_wrover.jpg - :align: center - :alt: ESP32-DEVKITC-WROVER - - ESP32-DevKitC-WROVER-IE - -Asymmetric Multiprocessing (AMP) -******************************** - -ESP32-DEVKITC-WROVER allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode -and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. - -Supported Features -================== - -Current Zephyr's ESP32-devkitc board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: build - -The usual ``flash`` target will work with the ``esp32_devkitc_wrover`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32_devkitc_wrover - -Debugging -********* - -ESP32 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -On the ESP-WROOM-32 DevKitC board, the JTAG pins are not run to a -standard connector (e.g. ARM 20-pin) and need to be manually connected -to the external programmer (e.g. a Flyswatter2): - -+------------+-----------+ -| ESP32 pin | JTAG pin | -+============+===========+ -| 3V3 | VTRef | -+------------+-----------+ -| EN | nTRST | -+------------+-----------+ -| IO14 | TMS | -+------------+-----------+ -| IO12 | TDI | -+------------+-----------+ -| GND | GND | -+------------+-----------+ -| IO13 | TCK | -+------------+-----------+ -| IO15 | TDO | -+------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: debug - -Note on Debugging with GDB Stub -=============================== - -GDB stub is enabled on ESP32. - -* When adding breakpoints, please use hardware breakpoints with command - ``hbreak``. Command ``break`` uses software breakpoints which requires - modifying memory content to insert break/trap instructions. - This does not work as the code is on flash which cannot be randomly - accessed for modification. - -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD`: https://github.com/openocd-org/openocd - -References -********** - -.. [1] https://en.wikipedia.org/wiki/ESP32 -.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.dts b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.dts deleted file mode 100644 index d62fe5ccfb8..00000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.dts +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32_devkitc_wrover-pinctrl.dtsi" -#include -#include - -/ { - model = "Espressif ESP32-DEVKITC-WROVER-E"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - sw0 = &button0; - watchdog0 = &wdt0; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&touch { - debounce-interval-ms = <30>; - href-microvolt = <2700000>; - lref-microvolt = <500000>; - href-atten-microvolt = <1000000>; - filter-mode = ; - filter-debounce-cnt = <1>; - filter-noise-thr = ; - filter-jitter-step = <4>; - filter-smooth-level = ; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.yaml b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.yaml deleted file mode 100644 index df56a1dbc55..00000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.yaml +++ /dev/null @@ -1,25 +0,0 @@ -identifier: esp32_devkitc_wrover -name: ESP32-DevkitC-WROVER-E -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - watchdog - - uart - - nvs - - pwm - - dac - - spi - - counter - - entropy - - input -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts deleted file mode 100644 index 2b6f0626356..00000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include - -/ { - model = "esp32_wrover_appcpu"; - compatible = "espressif,esp32_appcpu"; - - chosen { - zephyr,sram = &sram0; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&trng0 { - status = "okay"; -}; diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml deleted file mode 100644 index 03fe6a111a6..00000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: esp32_devkitc_wrover_appcpu -name: ESP32 DEVKITC WROVER APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp -vendor: espressif diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig deleted file mode 100644 index 5363f493882..00000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ESP32=y -CONFIG_SOC_ESP32_APPCPU=y -CONFIG_BOARD_ESP32_DEVKITC_WROVER_APPCPU=y - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_defconfig b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_defconfig deleted file mode 100644 index ad08ccede28..00000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32_DEVKITC_WROVER=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32_ethernet_kit/Kconfig.board b/boards/xtensa/esp32_ethernet_kit/Kconfig.board deleted file mode 100644 index 28a8995bbdf..00000000000 --- a/boards/xtensa/esp32_ethernet_kit/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32-ETHERNET-KIT board configuration - -# Copyright (c) 2022 Grant Ramsay -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32_ETHERNET_KIT - bool "ESP32-ETHERNET-KIT Development Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROVER_E_N4R8 -endchoice diff --git a/boards/xtensa/esp32_ethernet_kit/Kconfig.defconfig b/boards/xtensa/esp32_ethernet_kit/Kconfig.defconfig deleted file mode 100644 index 8797780b74e..00000000000 --- a/boards/xtensa/esp32_ethernet_kit/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# ESP32-ETHERNET-KIT board configuration - -# Copyright (c) 2022 Grant Ramsay -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32_ethernet_kit" - depends on BOARD_ESP32_ETHERNET_KIT - -config ESP_SPIRAM - default y - -choice SPIRAM_TYPE - default SPIRAM_TYPE_ESPPSRAM64 -endchoice - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/esp32_ethernet_kit/doc/index.rst b/boards/xtensa/esp32_ethernet_kit/doc/index.rst deleted file mode 100644 index 7159681dccd..00000000000 --- a/boards/xtensa/esp32_ethernet_kit/doc/index.rst +++ /dev/null @@ -1,623 +0,0 @@ -.. _esp32_ethernet_kit: - -ESP32-ETHERNET-KIT -################## - -The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables -Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide -more flexible power supply options, the ESP32-Ethernet-Kit also supports power -over Ethernet (PoE). - -.. _get-started-esp32-ethernet-kit-v1.2-overview: - -.. figure:: img/esp32-ethernet-kit-v1.2-overview.jpg - :align: center - :alt: ESP32-Ethernet-Kit V1.2 - :figclass: align-center - - ESP32-Ethernet-Kit V1.2 Overview - -Overview -******** - -ESP32-Ethernet-Kit is an ESP32-based development board produced by -`Espressif `_. - -It consists of two development boards, the Ethernet board A and the PoE -board B. The `Ethernet board (A)`_ contains Bluetooth/Wi-Fi dual-mode -ESP32-WROVER-E module and IP101GRI, a Single Port 10/100 Fast Ethernet -Transceiver (PHY). The `PoE board (B)`_ provides power over Ethernet -functionality. The A board can work independently, without the board B -installed. - -.. _get-started-esp32-ethernet-kit-v1.2: - -.. figure:: img/esp32-ethernet-kit-v1.2.jpg - :align: center - :alt: ESP32-Ethernet-Kit V1.2 - :figclass: align-center - - ESP32-Ethernet-Kit V1.2 - -For the application loading and monitoring, the Ethernet board (A) also -features FTDI FT2232H chip - an advanced multi-interface USB bridge. -This chip enables to use JTAG for direct debugging of ESP32 through the -USB interface without a separate JTAG debugger. - - -Functionality Overview -====================== - -The block diagram below shows the main components of ESP32-Ethernet-Kit -and their interconnections. - -.. figure:: img/esp32-ethernet-kit-v1.1-block-diagram.jpg - :align: center - :alt: ESP32-Ethernet-Kit block diagram - :figclass: align-center - - ESP32-Ethernet-Kit block diagram - - -Functional Description ----------------------- - -The following figures and tables describe the key components, interfaces, -and controls of the ESP32-Ethernet-Kit. - -.. _get-started-esp32-ethernet-kit-a-v1.2-layout: - - -Ethernet Board (A) -^^^^^^^^^^^^^^^^^^ - -.. figure:: img/esp32-ethernet-kit-a-v1.2-layout.jpg - :align: center - :alt: ESP32-Ethernet-Kit V1.2 - :figclass: align-center - - ESP32-Ethernet-Kit - Ethernet board (A) layout - -The table below provides description starting from the picture's top right -corner and going clockwise. - -.. list-table:: Table 1 Component Description - :widths: 40 150 - :header-rows: 1 - - * - Key Component - - Description - * - ESP32-WROVER-E - - This ESP32 module features 64-Mbit PSRAM for flexible extended storage - and data processing capabilities. - * - GPIO Header 2 - - Five unpopulated through-hole solder pads to provide access to selected - GPIOs of ESP32. For details, see `GPIO Header 2`_. - * - Function Switch - - A 4-bit DIP switch used to configure the functionality of selected GPIOs - of ESP32. For details see `Function Switch`_. - * - Tx/Rx LEDs - - Two LEDs to show the status of UART transmission. - * - FT2232H - - The FT2232H chip serves as a multi-protocol USB-to-serial bridge which - can be programmed and controlled via USB to provide communication with - ESP32. FT2232H also features USB-to-JTAG interface which is available - on channel A of the chip, while USB-to-serial is on channel B. - The FT2232H chip enhances user-friendliness in terms of application - development and debugging. See - `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_. - * - USB Port - - USB interface. Power supply for the board as well as the communication - interface between a computer and the board. - * - Power Switch - - Power On/Off Switch. Toggling the switch to **5V0** position powers the - board on, toggling to **GND** position powers the board off. - * - 5V Input - - The 5 V power supply interface can be more convenient when the board is - operating autonomously (not connected to a computer). - * - 5V Power On LED - - This red LED turns on when power is supplied to the board, either from - USB or 5 V Input. - * - DC/DC Converter - - Provided DC 5 V to 3.3 V conversion, output current up to 2 A. - * - Board B Connectors - - A pair male and female header pins for mounting the `PoE board (B)`_ - * - IP101GRI (PHY) - - The physical layer (PHY) connection to the Ethernet cable is - implemented using the - `IP101GRI `_ - chip. The connection between PHY and ESP32 is done through the reduced - media-independent interface (RMII), a variant of the media-independent - interface `(MII) `_ - standard. The PHY supports the IEEE 802.3/802.3u standard of 10/100 - Mbps. - * - RJ45 Port - - Ethernet network data transmission port. - * - Magnetics Module - - The Magnetics are part of the Ethernet specification to protect against - faults and transients, including rejection of common mode signals - between the transceiver IC and the cable. The magnetics also provide - galvanic isolation between the transceiver and the Ethernet device. - * - Link/Activity LEDs - - Two LEDs (green and red) that respectively indicate the "Link" and - "Activity" statuses of the PHY. - * - BOOT Button - - Download button. Holding down **BOOT** and then pressing **EN** - initiates Firmware Download mode for downloading firmware through the - serial port. - * - EN Button - - Reset button. - * - GPIO Header 1 - - This header provides six unpopulated through-hole solder pads connected - to spare GPIOs of ESP32. For details, see `GPIO Header 1`_. - -PoE Board (B) -^^^^^^^^^^^^^ - -This board coverts power delivered over the Ethernet cable (PoE) to provide a -power supply for the Ethernet board (A). The main components of the PoE board -(B) are shown on the block diagram under `Functionality Overview`_. - -The PoE board (B) has the following features: - -* Support for IEEE 802.3at -* Power output: 5 V, 1.4 A - -To take advantage of the PoE functionality the **RJ45 Port** of the Ethernet -board (A) should be connected with an Ethernet cable to a switch that supports -PoE. When the Ethernet board (A) detects 5 V power output from the PoE board -(B), the USB power will be automatically cut off. - -.. figure:: img/esp32-ethernet-kit-b-v1.0-layout.jpg - :align: center - :alt: ESP32-Ethernet-Kit - PoE board (B) - :figclass: align-center - - ESP32-Ethernet-Kit - PoE board (B) layout - -.. list-table:: Table PoE board (B) - :widths: 40 150 - :header-rows: 1 - - * - Key Component - - Description - * - Board A Connector - - Four female (left) and four male (right) header pins for connecting the - PoE board (B) to `Ethernet board (A)`_. The pins on the left accept - power coming from a PoE switch. The pins on the right deliver 5 V power - supply to the Ethernet board (A). - * - External Power Terminals - - Optional power supply (26.6 ~ 54 V) to the PoE board (B). - -.. _get-started-esp32-ethernet-kit-v1.2-setup-options: - - -Setup Options -============= - -This section describes options to configure the ESP32-Ethernet-Kit hardware. - - -Function Switch ---------------- - -When in On position, this DIP switch is routing listed GPIOs to FT2232H to -provide JTAG functionality. When in Off position, the GPIOs may be used for -other purposes. - -======= ================ -DIP SW GPIO Pin -======= ================ - 1 GPIO13 - 2 GPIO12 - 3 GPIO15 - 4 GPIO14 -======= ================ - - -RMII Clock Selection --------------------- - -The ethernet MAC and PHY under RMII working mode need a common 50 MHz -reference clock (i.e. RMII clock) that can be provided either externally, -or generated from internal ESP32 APLL (not recommended). - -.. note:: - - For additional information on the RMII clock selection, please refer to - `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_, - sheet 2, location D2. - - -RMII Clock Sourced Externally by PHY -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -By default, the ESP32-Ethernet-Kit is configured to provide RMII clock for the -IP101GRI PHY's 50M_CLKO output. The clock signal is generated by the frequency -multiplication of 25 MHz crystal connected to the PHY. For details, please see -the figure below. - -.. figure:: img/esp32-ethernet-kit-rmii-clk-from-phy.jpg - :align: center - :alt: RMII Clock from IP101GRI PHY - :figclass: align-center - - RMII Clock from IP101GRI PHY - -Please note that the PHY is reset on power up by pulling the RESET_N signal -down with a resistor. ESP32 should assert RESET_N high with GPIO5 to enable -PHY. Only this can ensure the power-up of system. Otherwise ESP32 may enter -download mode (when the clock signal of REF_CLK_50M is at a high logic level -during the GPIO0 power-up sampling phase). - - -RMII Clock Sourced Internally from ESP32's APLL -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Another option is to source the RMII Clock from internal ESP32 APLL, see -figure below. The clock signal coming from GPIO0 is first inverted, to account -for transmission line delay, and then supplied to the PHY. - -.. figure:: img/esp32-ethernet-kit-rmii-clk-to-phy.jpg - :align: center - :alt: RMII Clock from ESP Internal APLL - :figclass: align-center - - RMII Clock from ESP Internal APLL - -To implement this option, users need to remove or add some RC components on -the board. For details please refer to -`ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_, -sheet 2, location D2. Please note that if the APLL is already used for other -purposes (e.g. I2S peripheral), then you have no choice but use an external -RMII clock. - - -GPIO Allocation ---------------- - -This section describes allocation of ESP32 GPIOs to specific interfaces or -functions of the ESP32-Ethernet-Kit. - - -IP101GRI (PHY) Interface -^^^^^^^^^^^^^^^^^^^^^^^^ - -The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table -below. Implementation of ESP32-Ethernet-Kit defaults to Reduced -Media-Independent Interface (RMII). - -==== ================ =============== -No. ESP32 Pin (MAC) IP101GRI (PHY) -==== ================ =============== -*RMII Interface* ---------------------------------------- - 1 GPIO21 TX_EN - 2 GPIO19 TXD[0] - 3 GPIO22 TXD[1] - 4 GPIO25 RXD[0] - 5 GPIO26 RXD[1] - 6 GPIO27 CRS_DV - 7 GPIO0 REF_CLK ----- ---------------- --------------- -*Serial Management Interface* ---------------------------------------- - 8 GPIO23 MDC - 9 GPIO18 MDIO ----- ---------------- --------------- -*PHY Reset* ---------------------------------------- -10 GPIO5 Reset_N -==== ================ =============== - -.. note:: - - The allocation of all pins under the ESP32's *RMII Interface* is fixed and - cannot be changed either through IO MUX or GPIO Matrix. REF_CLK can only - be selected from GPIO0, GPIO16 or GPIO17 and it can not be changed through - GPIO Matrix. - - -GPIO Header 1 -^^^^^^^^^^^^^ - -This header exposes some GPIOs that are not used elsewhere on the -ESP32-Ethernet-Kit. - -==== ================ -No. ESP32 Pin -==== ================ - 1 GPIO32 - 2 GPIO33 - 3 GPIO34 - 4 GPIO35 - 5 GPIO36 - 6 GPIO39 -==== ================ - - -GPIO Header 2 -^^^^^^^^^^^^^ - -This header contains GPIOs that may be used for other purposes depending on -scenarios described in column "Comments". - -==== ========== ==================== -No. ESP32 Pin Comments -==== ========== ==================== - 1 GPIO17 See note 1 - 2 GPIO16 See note 1 - 3 GPIO4 - 4 GPIO2 - 5 GPIO13 See note 2 - 6 GPIO12 See note 2 - 7 GPIO15 See note 2 - 8 GPIO14 See note 2 - 9 GND Ground -10 3V3 3.3 V power supply -==== ========== ==================== - -.. note:: - - 1. The ESP32 pins GPIO16 and GPIO17 are not broken out to the - ESP32-WROVER-E module and therefore not available for use. If you need - to use these pins, please solder a module without PSRAM memory inside, - e.g. the ESP32-WROOM-32D or ESP32-SOLO-1. - - 2. Functionality depends on the settings of the `Function Switch`_. - - -GPIO Allocation Summary -^^^^^^^^^^^^^^^^^^^^^^^ - -.. csv-table:: - :header: ESP32-WROVER-E,IP101GRI,UART,JTAG,GPIO,Comments - - S_VP,,,,IO36, - S_VN,,,,IO39, - IO34,,,,IO34, - IO35,,,,IO35, - IO32,,,,IO32, - IO33,,,,IO33, - IO25,RXD[0],,,, - IO26,RXD[1],,,, - IO27,CRS_DV,,,, - IO14,,,TMS,IO14, - IO12,,,TDI,IO12, - IO13,,,TCK,IO13, - IO15,,,TDO,IO15, - IO2,,,,IO2, - IO0,REF_CLK,,,,See note 1 - IO4,,,,IO4, - IO16,,,,IO16 (NC),See note 2 - IO17,,,,IO17 (NC),See note 2 - IO5,Reset_N,,,,See note 1 - IO18,MDIO,,,, - IO19,TXD[0],,,, - IO21,TX_EN,,,, - RXD0,,RXD,,, - TXD0,,TXD,,, - IO22,TXD[1],,,, - IO23,MDC,,,, - -.. note:: - - 1. To prevent the power-on state of the GPIO0 from being affected by the - clock output on the PHY side, the RESET_N signal to PHY defaults to - low, turning the clock output off. After power-on you can control - RESET_N with GPIO5 to turn the clock output on. See also - `RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off - the clock output through RESET_N, it is recommended to use a crystal - module that can be disabled/enabled externally. Similarly like when - using RESET_N, the oscillator module should be disabled by default and - turned on by ESP32 after power-up. For a reference design please see - `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_. - - 2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the - ESP32-WROVER-E module and therefore not available for use. If you need - to use these pins, please solder a module without PSRAM memory inside, - e.g. the ESP32-WROOM-32D or ESP32-SOLO-1. - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32_ethernet_kit - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_ethernet_kit - :goals: build - -The usual ``flash`` target will work with the ``esp32_ethernet_kit`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_ethernet_kit - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32_ethernet_kit - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_ethernet_kit - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_ethernet_kit - :goals: debug - - -Enabling Ethernet -***************** - -Enable Ethernet MAC, PHY and MDIO; add these to your device tree overlay: - -.. code-block:: devicetree - - ð { - status = "okay"; - }; - - &phy { - status = "okay"; - }; - - &mdio { - status = "okay"; - }; - -Enable Ethernet in KConfig: - -.. code-block:: cfg - - CONFIG_ETH_ESP32=y - CONFIG_NETWORKING=y - CONFIG_NET_L2_ETHERNET=y - -Board Init -========== - -RESET_N (GPIO5) is automatically set high to enable the Ethernet PHY -during board initialization (board_init.c) - -Related Documents -***************** - -* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic `_ (PDF) -* `ESP32-Ethernet-Kit PoE Board (B) Schematic `_ (PDF) -* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) PCB Layout `_ (PDF) -* `ESP32-Ethernet-Kit PoE Board (B) PCB Layout `_ (PDF) -* `ESP32 Datasheet `_ (PDF) -* `ESP32-WROVER-E Datasheet `_ (PDF) -* `OpenOCD ESP32 `_ diff --git a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.dts b/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.dts deleted file mode 100644 index 50b01b88b2f..00000000000 --- a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.dts +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2022 Grant Ramsay - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32_ethernet_kit-pinctrl.dtsi" - -/ { - model = "esp32"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - watchdog0 = &wdt0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_default>; - pinctrl-names = "default"; - - phy: ethernet-phy@1 { - compatible = "ethernet-phy"; - status = "disabled"; - reg = <1>; - }; -}; - -ð { - phy-handle = <&phy>; -}; diff --git a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.yaml b/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.yaml deleted file mode 100644 index 8f1167e1fac..00000000000 --- a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: esp32_ethernet_kit -name: ESP32 ETHERNET KIT -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - watchdog - - uart - - nvs - - pwm -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig b/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig deleted file mode 100644 index a9c99bec06b..00000000000 --- a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32_ETHERNET_KIT=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_franzininho/Kconfig.board b/boards/xtensa/esp32s2_franzininho/Kconfig.board deleted file mode 100644 index 7b52b4d88b1..00000000000 --- a/boards/xtensa/esp32s2_franzininho/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32S2 Franzininho board configuration - -# Copyright (c) 2022 Felipe Neves -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32S2_FRANZININHO - bool "ESP32S2 Franzininho Board" - depends on SOC_SERIES_ESP32S2 - -choice SOC_PART_NUMBER - default SOC_ESP32S2_WROOM -endchoice diff --git a/boards/xtensa/esp32s2_franzininho/Kconfig.defconfig b/boards/xtensa/esp32s2_franzininho/Kconfig.defconfig deleted file mode 100644 index 2319c0061e4..00000000000 --- a/boards/xtensa/esp32s2_franzininho/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# ESP32S2 Franzininho board configuration - -# Copyright (c) 2022 Felipe Neves -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32s2_franzininho" - depends on BOARD_ESP32S2_FRANZININHO - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 32768 if WIFI - default 4096 diff --git a/boards/xtensa/esp32s2_franzininho/doc/index.rst b/boards/xtensa/esp32s2_franzininho/doc/index.rst deleted file mode 100644 index 684fbf5dd5c..00000000000 --- a/boards/xtensa/esp32s2_franzininho/doc/index.rst +++ /dev/null @@ -1,174 +0,0 @@ -.. _esp32s2_franzininho: - -ESP32-S2 Franzininho -#################### - -Overview -******** - -Franzininho is an educational development board based on ESP32-S2 which is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, -designed to be secure and cost-effective, with a high performance and a rich set of IO capabilities. [1]_ - -The features include the following: - -- RSA-3072-based secure boot -- AES-XTS-256-based flash encryption -- Protected private key and device secrets from software access -- Cryptographic accelerators for enhanced performance -- Protection against physical fault injection attacks -- Various peripherals: - - - 43x programmable GPIOs - - 14x configurable capacitive touch GPIOs - - USB OTG - - LCD interface - - camera interface - - SPI - - I2S - - UART - - ADC - - DAC - - LED PWM with up to 8 channels - -.. figure:: img/esp32_s2_franzininho.jpg - :align: center - :alt: ESP32-S2 FRANZININHO - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32s2_franzininho - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_franzininho - :goals: build - -The usual ``flash`` target will work with the ``esp32s2_franzininho`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_franzininho - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32s2_franzininho - -References -********** - -.. [1] https://www.espressif.com/en/products/socs/esp32-s2 -.. _`ESP32S2 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf -.. _`ESP32S2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig b/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig deleted file mode 100644 index 6d95a2f5567..00000000000 --- a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - - -CONFIG_BOARD_ESP32S2_FRANZININHO=y -CONFIG_SOC_SERIES_ESP32S2=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_lolin_mini/Kconfig.board b/boards/xtensa/esp32s2_lolin_mini/Kconfig.board deleted file mode 100644 index 1f567f3f42b..00000000000 --- a/boards/xtensa/esp32s2_lolin_mini/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32S2 LOLIN S2 MINI board configuration - -# Copyright (c) 2023 Google, LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32S2_LOLIN_MINI - bool "ESP32S2 Lolin Mini Board" - depends on SOC_SERIES_ESP32S2 - -choice SOC_PART_NUMBER - default SOC_ESP32S2_FN4R2 -endchoice diff --git a/boards/xtensa/esp32s2_lolin_mini/Kconfig.defconfig b/boards/xtensa/esp32s2_lolin_mini/Kconfig.defconfig deleted file mode 100644 index 709b0d5b53b..00000000000 --- a/boards/xtensa/esp32s2_lolin_mini/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# ESP32S2 LOLIN S2 MINI board configuration - -# Copyright (c) 2023 Google, LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32s2_lolin_mini" - depends on BOARD_ESP32S2_LOLIN_MINI - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 32768 if WIFI - default 4096 diff --git a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig b/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig deleted file mode 100644 index c8c04460dbe..00000000000 --- a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32S2_LOLIN_MINI=y -CONFIG_SOC_SERIES_ESP32S2=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_saola/Kconfig.board b/boards/xtensa/esp32s2_saola/Kconfig.board deleted file mode 100644 index 7d9e3a717ae..00000000000 --- a/boards/xtensa/esp32s2_saola/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32S2_SAOLA - bool "ESP32S2 Saola Board" - depends on SOC_SERIES_ESP32S2 - -choice SOC_PART_NUMBER - default SOC_ESP32S2_WROVER_N4R2 -endchoice diff --git a/boards/xtensa/esp32s2_saola/Kconfig.defconfig b/boards/xtensa/esp32s2_saola/Kconfig.defconfig deleted file mode 100644 index 8b160c02935..00000000000 --- a/boards/xtensa/esp32s2_saola/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# ESP32S2 Saola board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32s2_saola" - depends on BOARD_ESP32S2_SAOLA - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 32768 if WIFI - default 4096 diff --git a/boards/xtensa/esp32s2_saola/doc/index.rst b/boards/xtensa/esp32s2_saola/doc/index.rst deleted file mode 100644 index f52594c6649..00000000000 --- a/boards/xtensa/esp32s2_saola/doc/index.rst +++ /dev/null @@ -1,249 +0,0 @@ -.. _esp32s2_saola: - -ESP32-S2 -######## - -Overview -******** - -ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be secure and -cost-effective, with a high performance and a rich set of IO capabilities. [1]_ - -The features include the following: - -- RSA-3072-based secure boot -- AES-XTS-256-based flash encryption -- Protected private key and device secrets from software access -- Cryptographic accelerators for enhanced performance -- Protection against physical fault injection attacks -- Various peripherals: - - - 43x programmable GPIOs - - 14x configurable capacitive touch GPIOs - - USB OTG - - LCD interface - - camera interface - - SPI - - I2S - - UART - - ADC - - DAC - - LED PWM with up to 8 channels - -Supported Features -================== - -Current Zephyr's ESP32-S2-saola board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32s2_saola - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_saola - :goals: build - -The usual ``flash`` target will work with the ``esp32s2_saola`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_saola - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32s2_saola - -Debugging -********* - -ESP32-S2 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -The following table shows the pin mapping between ESP32-S2 board and JTAG interface. - -+---------------+-----------+ -| ESP32 pin | JTAG pin | -+===============+===========+ -| MTDO / GPIO40 | TDO | -+---------------+-----------+ -| MTDI / GPIO41 | TDI | -+---------------+-----------+ -| MTCK / GPIO39 | TCK | -+---------------+-----------+ -| MTMS / GPIO42 | TMS | -+---------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S2`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_saola - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_saola - :goals: debug - -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html - - -References -********** - -.. [1] https://www.espressif.com/en/products/socs/esp32-s2 -.. _ESP32-S2 Saola User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html -.. _ESP32S2 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf -.. _ESP32S2 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig b/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig deleted file mode 100644 index c7bacdd2ec6..00000000000 --- a/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32S2_SAOLA=y -CONFIG_SOC_SERIES_ESP32S2=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s3_devkitm/Kconfig.board b/boards/xtensa/esp32s3_devkitm/Kconfig.board deleted file mode 100644 index 3f899740c0d..00000000000 --- a/boards/xtensa/esp32s3_devkitm/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -# ESP32S3 DevKitM board configuration -config BOARD_ESP32S3_DEVKITM - bool "ESP32S3 DevKitM Board" - depends on SOC_SERIES_ESP32S3 - -config BOARD_ESP32S3_DEVKITM_APPCPU - bool "ESP32S3 Board configuration for APPCPU (core 1)." - depends on SOC_SERIES_ESP32S3 && SOC_ESP32S3_APPCPU - -choice SOC_PART_NUMBER - default SOC_ESP32S3_MINI_N8 -endchoice diff --git a/boards/xtensa/esp32s3_devkitm/Kconfig.defconfig b/boards/xtensa/esp32s3_devkitm/Kconfig.defconfig deleted file mode 100644 index 54a01595721..00000000000 --- a/boards/xtensa/esp32s3_devkitm/Kconfig.defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# ESP32S3 DevKitM board configuration - -# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ESP32S3_DEVKITM - -config BOARD - default "esp32s3_devkitm" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -endif - -if BOARD_ESP32S3_DEVKITM_APPCPU - -config BOARD - default "esp32s3_devkitm_appcpu" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - def_int 4096 - -config KERNEL_BIN_NAME - default "esp32_appcpu_firmware" -endif - -config ENTROPY_GENERATOR - default y diff --git a/boards/xtensa/esp32s3_devkitm/doc/index.rst b/boards/xtensa/esp32s3_devkitm/doc/index.rst deleted file mode 100644 index 851246a75d4..00000000000 --- a/boards/xtensa/esp32s3_devkitm/doc/index.rst +++ /dev/null @@ -1,286 +0,0 @@ -.. _esp32s3_devkitm: - -ESP32S3-DevKitM -############### - -Overview -******** - -The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1 -or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi -and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitM`_ - -Hardware -******** - -ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi -and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor -(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, -RF module, and numerous peripherals. - -ESP32-S3 DevKitM includes the following features: - -- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz -- Additional vector instructions support for AI acceleration -- 512KB of SRAM -- 384KB of ROM -- Wi-Fi 802.11b/g/n -- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate - -Digital interfaces: - -- 45 programmable GPIOs -- 4x SPI -- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411 -- 1x DVP 8-bit ~16-bit camera interface -- 3x UART -- 2x I2C -- 2x I2S -- 1x RMT (TX/RX) -- 1x pulse counter -- LED PWM controller, up to 8 channels -- 1x full-speed USB OTG -- 1x USB Serial/JTAG controller -- 2x MCPWM -- 1x SDIO host controller with 2 slots -- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels -- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) -- Addressable RGB LED, driven by GPIO48. - -Analog interfaces: - -- 2x 12-bit SAR ADCs, up to 20 channels -- 1x temperature sensor -- 14x touch sensing IOs - -Timers: - -- 4x 54-bit general-purpose timers -- 1x 52-bit system timer -- 3x watchdog timers - -Low Power: - -- Power Management Unit with five power modes -- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM - -Security: - -- Secure boot -- Flash encryption -- 4-Kbit OTP, up to 1792 bits for users -- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) - -Asymmetric Multiprocessing (AMP) -******************************** - -ESP32S3-DevKitM allows 2 different applications to be executed in ESP32-S3 SoC. Due to its dual-core -architecture, each core can be enabled to execute customized tasks in stand-alone mode -and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. - -For more information, check the datasheet at `ESP32-S3 Datasheet`_. - -Supported Features -================== - -Current Zephyr's ESP32-S3-DevKitM board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI/CAN | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32s3_devkitm - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_devkitm - :goals: build - -The usual ``flash`` target will work with the ``esp32s3_devkitm`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_devkitm - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32s3_devkitm - -Debugging -********* - -ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32-S3`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_devkitm - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_devkitm - :goals: debug - -.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`ESP32-S3 DevKitM`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html - -References -********** - -.. _ESP32-S3 DevKitM User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html -.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf -.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts deleted file mode 100644 index 640304ee00f..00000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32s3_devkitm-pinctrl.dtsi" -#include -#include - -/ { - model = "esp32s3_devkitm"; - compatible = "espressif,esp32s3"; - - aliases { - i2c-0 = &i2c0; - watchdog0 = &wdt0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - uart-0 = &uart0; - sw0 = &button0; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&touch { - debounce-interval-ms = <30>; - href-microvolt = <2700000>; - lref-microvolt = <500000>; - href-atten-microvolt = <1000000>; - filter-mode = ; - filter-debounce-cnt = <1>; - filter-noise-thr = ; - filter-jitter-step = <4>; - filter-smooth-level = ; -}; - -&i2c0 { - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&i2c1 { - clock-frequency = ; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&twai { - pinctrl-0 = <&twai_default>; - pinctrl-names = "default"; - bus-speed = <125000>; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&wdt0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&usb_serial { - status = "disabled"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml deleted file mode 100644 index cce4cb8b82e..00000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: esp32s3_devkitm -name: ESP32-S3 DevKitM -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - can - - counter - - watchdog - - entropy - - pwm - - dma - - input -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts deleted file mode 100644 index ae68f094e14..00000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -/ { - model = "esp32s3_appcpu"; - compatible = "espressif,esp32s3_appcpu"; - - chosen { - zephyr,sram = &sram0; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&trng0 { - status = "okay"; -}; - -&ipm0 { - status = "okay"; -}; diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.yaml b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.yaml deleted file mode 100644 index b6145d0f965..00000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.yaml +++ /dev/null @@ -1,26 +0,0 @@ -identifier: esp32s3_devkitm_appcpu -name: ESP32S3 DEVKITM APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig deleted file mode 100644 index e554a951263..00000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ESP32S3=y -CONFIG_SOC_ESP32S3_APPCPU=y -CONFIG_BOARD_ESP32S3_DEVKITM_APPCPU=y - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig deleted file mode 100644 index 1f8b52aa360..00000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32S3_DEVKITM=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32s3_luatos_core/Kconfig.board b/boards/xtensa/esp32s3_luatos_core/Kconfig.board deleted file mode 100644 index 05e726bb4a0..00000000000 --- a/boards/xtensa/esp32s3_luatos_core/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -# ESP32S3 Core board configuration -config BOARD_ESP32S3_LUATOS_CORE - bool "ESP32S3 LuatOS Core Board with ch343 enabled" - depends on SOC_SERIES_ESP32S3 - -config BOARD_ESP32S3_LUATOS_CORE_USB - bool "ESP32S3 LuatOS Core Board with ch343 disabled" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_MINI_N8 -endchoice diff --git a/boards/xtensa/esp32s3_luatos_core/Kconfig.defconfig b/boards/xtensa/esp32s3_luatos_core/Kconfig.defconfig deleted file mode 100644 index 35d4a9bc3fc..00000000000 --- a/boards/xtensa/esp32s3_luatos_core/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# ESP32S3 Core board configuration - -# Copyright (c) 2023 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32s3_luatos_core" - depends on BOARD_ESP32S3_LUATOS_CORE || BOARD_ESP32S3_LUATOS_CORE_USB - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/esp32s3_luatos_core/doc/index.rst b/boards/xtensa/esp32s3_luatos_core/doc/index.rst deleted file mode 100644 index 9160a20fcf4..00000000000 --- a/boards/xtensa/esp32s3_luatos_core/doc/index.rst +++ /dev/null @@ -1,292 +0,0 @@ -.. _esp32s3_luatos_core: - -ESP32S3-Luatos-Core -################### - -Overview -******** - -The ESP32S3-LUATOS-CORE development board is a compact board based on Espressif ESP32-S3. -The board comes equipped with a 2.4GHz antenna and supports both Wi-Fi and Bluetooth functionalities. -For more information, check `ESP32S3-LUATOS-CORE`_ (chinese) - -.. image:: img/esp32s3_luatos_core.jpg - :align: center - :alt: esp32s3_luatos_core - -Hardware -******** - -ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi -and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor -(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, -RF module, and numerous peripherals. - -ESP32S3-LUATOS-CORE includes the following features: - -- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz -- Additional vector instructions support for AI acceleration -- 512KB of SRAM -- 384KB of ROM -- 8MB of PSRAM -- 16MB of FLASH -- Wi-Fi 802.11b/g/n -- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate - -Digital interfaces: - -- 4x SPI -- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411 -- 1x DVP 8-bit ~16-bit camera interface -- 3x UART -- 2x I2C -- 2x I2S -- 1x RMT (TX/RX) -- 1x pulse counter -- LED PWM controller, up to 8 channels -- 1x USB Port with USB switcher, supporting following modes: - - 1x full-speed USB OTG or 1x USB Serial/JTAG controller - - USB to serial chip CH343 -- 2x MCPWM -- 1x SDIO host controller with 2 slots -- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels -- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) -- 2x Blue LED - -Analog interfaces: - -- 2x 12-bit SAR ADCs, up to 20 channels - -Timers: - -- 4x 54-bit general-purpose timers -- 1x 52-bit system timer -- 3x watchdog timers - -Low Power: - -- Power Management Unit with five power modes -- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM - -Security: - -- Secure boot -- Flash encryption -- 4-Kbit OTP, up to 1792 bits for users -- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) - -For more information, check the datasheet at `ESP32-S3 Datasheet`_. - -.. image:: img/esp32s3_luatos_core_pinout.jpg - :align: center - :alt: esp32s3_luatos_core_pinout - -Supported Features -================== - -Current Zephyr's ESP32S3-LUATOS-Core board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI/CAN | on-chip | can | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32s3_luatos_core - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_luatos_core - :goals: build - -If CH343 chip is disabled, You need use the following command to build: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_luatos_core_usb - :goals: build - -The usual ``flash`` target will work with the ``esp32s3_luatos_core`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_luatos_core - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32s3_luatos_core - -Debugging -********* - -ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32-S3`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_luatos_core - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_luatos_core - :goals: debug - -.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`ESP32S3-LUATOS-CORE`: https://wiki.luatos.com/chips/esp32s3/board.html - -References -********** - -.. _ESP32S3-LUATOS-CORE User Guide: https://wiki.luatos.com/chips/esp32s3/board.html -.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf -.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.dts b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.dts deleted file mode 100644 index fea76fca3b7..00000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2023 YuLong Yao - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include "esp32s3_luatos_core.dtsi" - -/ { - model = "esp32s3_luatos_core"; - compatible = "espressif,esp32s3"; - - aliases { - led0 = &led0; - led1 = &led1; - i2c-0 = &i2c0; - watchdog0 = &wdt0; - uart-0 = &uart0; - sw0 = &button0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.yaml b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.yaml deleted file mode 100644 index eb850a58f95..00000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: esp32s3_luatos_core -name: ESP32-S3 Core -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - can - - counter - - watchdog - - entropy - - pwm - - dma -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_defconfig b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_defconfig deleted file mode 100644 index 59a3ecc3c4d..00000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32S3_LUATOS_CORE=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.dts b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.dts deleted file mode 100644 index 686c977e36f..00000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2023 YuLong Yao - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include "esp32s3_luatos_core.dtsi" - -/ { - model = "esp32s3_luatos_core"; - compatible = "espressif,esp32s3"; - - aliases { - led0 = &led0; - led1 = &led1; - i2c-0 = &i2c0; - watchdog0 = &wdt0; - uart-0 = &usb_serial; - sw0 = &button0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - }; -}; - -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "disabled"; -}; diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.yaml b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.yaml deleted file mode 100644 index a8680bb6544..00000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: esp32s3_luatos_core_usb -name: ESP32-S3 Core USB -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - can - - counter - - watchdog - - entropy - - pwm - - dma -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb_defconfig b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb_defconfig deleted file mode 100644 index 59a3ecc3c4d..00000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32S3_LUATOS_CORE=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp_wrover_kit/Kconfig.board b/boards/xtensa/esp_wrover_kit/Kconfig.board deleted file mode 100644 index eb255c7ec55..00000000000 --- a/boards/xtensa/esp_wrover_kit/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ESP-WROVER-KIT board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP_WROVER_KIT - bool "ESP-WROVER-KIT Development Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROVER_E_N4R8 -endchoice diff --git a/boards/xtensa/esp_wrover_kit/Kconfig.defconfig b/boards/xtensa/esp_wrover_kit/Kconfig.defconfig deleted file mode 100644 index 378b557eb7f..00000000000 --- a/boards/xtensa/esp_wrover_kit/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# ESP-WROVER-KIT board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp_wrover_kit" - depends on BOARD_ESP_WROVER_KIT - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -config DISK_DRIVER_SDMMC - default y diff --git a/boards/xtensa/esp_wrover_kit/doc/index.rst b/boards/xtensa/esp_wrover_kit/doc/index.rst deleted file mode 100644 index 0154f2c9ad9..00000000000 --- a/boards/xtensa/esp_wrover_kit/doc/index.rst +++ /dev/null @@ -1,658 +0,0 @@ -.. _esp_wrover_kit: - -ESP-WROVER-KIT -############## - -Overview -******** - -ESP-WROVER-KIT is an ESP32-based development board produced by `Espressif `_. - -ESP-WROVER-KIT features the following integrated components: - -- ESP32-WROVER-E module -- LCD screen -- MicroSD card slot - -Its another distinguishing feature is the embedded FTDI FT2232HL chip - an advanced multi-interface -USB bridge. This chip enables to use JTAG for direct debugging of ESP32 through the USB interface -without a separate JTAG debugger. ESP-WROVER-KIT makes development convenient, easy, and -cost-effective. - -Most of the ESP32 I/O pins are broken out to the board's pin headers for easy access. - -.. note:: - - ESP32's GPIO16 and GPIO17 are used as chip select and clock signals for PSRAM. By default, the two - GPIOs are not broken out to the board's pin headers in order to ensure reliable performance. - -Functionality Overview -********************** - -The block diagram below shows the main components of ESP-WROVER-KIT and their interconnections. - -.. image:: img/esp-wrover-kit-block-diagram.jpg - :align: center - :alt: ESP-WROVER-KIT - -Functional Description -********************** - -The following two figures and the table below describe the key components, interfaces, and controls -of the ESP-WROVER-KIT board. - -.. figure:: img/esp-wrover-kit-v4.1-layout-front.jpg - :align: center - :alt: esp wrover front - - ESP-WROVER-KIT board layout - front - -.. _esp wrover back: - -.. figure:: img/esp-wrover-kit-v4.1-layout-back.jpg - :align: center - :alt: esp wrover back - - ESP-WROVER-KIT board layout - back - -The table below provides description in the following manner: -- Starting from the first picture’s top right corner and going clockwise -- Then moving on to the second picture - -+------------------+-------------------------------------------------------------------------+ -| Key Component | Description | -+==================+=========================================================================+ -| FT2232 | The FT2232 chip serves as a multi-protocol USB-to-serial bridge | -| | which can be programmed and controlled via USB to provide | -| | communication with ESP32. FT2232 also features USB-to-JTAG | -| | interface which is available on channel A of the chip, while USB-to- | -| | serial is on channel B. The FT2232 chip enhances user-friendliness in | -| | terms of application development and debugging. See `ESP-WROVER-KIT | -| | V4.1 schematic | -| | `_. | -+------------------+-------------------------------------------------------------------------+ -| 32.768 kHz | External precision 32.768 kHz crystal oscillator serves as a clock with | -| | low-power consumption while the chip is in Deep-sleep mode. | -+------------------+-------------------------------------------------------------------------+ -| 0R | Zero-ohm resistor intended as a placeholder for a current shunt, can | -| | be desoldered or replaced with a current shunt to facilitate the | -| | measurement of ESP32’s current consumption in different modes. | -+------------------+-------------------------------------------------------------------------+ -| ESP32-WROVER-E | This ESP32 module features 64-Mbit PSRAM for flexible extended | -| module | storage and data processing capabilities. | -+------------------+-------------------------------------------------------------------------+ -| Diagnostic LEDs | Four red LEDs connected to the GPIO pins of FT2232. Intended for | -| | future use. | -+------------------+-------------------------------------------------------------------------+ -| UART | Serial port. The serial TX/RX signals of FT2232 and ESP32 are broken | -| | out to the inward and outward sides of JP2 respectively. By default, | -| | these pairs of pins are connected with jumpers. To use ESP32’s serial | -| | interface, remove the jumpers and connect another external serial | -| | device to the respective pins. | -+------------------+-------------------------------------------------------------------------+ -| SPI | By default, ESP32 uses its SPI interface to access flash and PSRAM | -| | memory inside the module. Use these pins to connect ESP32 to | -| | another SPI device. In this case, an extra chip select (CS) signal is | -| | needed. Please note that the voltage of this interface is 3.3 V. | -+------------------+-------------------------------------------------------------------------+ -| CTS/RTS | Serial port flow control signals: the pins are not connected to the | -| | circuitry by default. To enable them, short the respective pins of JP14 | -| | with jumpers. | -+------------------+-------------------------------------------------------------------------+ -| JTAG | JTAG interface. JTAG signals of FT2232 and ESP32 are broken out to | -| | the inward and outward sides of JP2 respectively. By default, these | -| | pairs of pins are disconnected. To enable JTAG, short the respective | -| | pins with jumpers as shown in Section | -| | :ref:`Setup Options` | -+------------------+-------------------------------------------------------------------------+ -| USB Port | USB interface. Power supply for the board as well as the | -| | communication interface between a computer and the board. | -+------------------+-------------------------------------------------------------------------+ -| EN Button | Reset button. | -+------------------+-------------------------------------------------------------------------+ -| BOOT Button | Download button. Holding down Boot and then pressing EN initiates | -| | Firmware Download mode for downloading firmware through the | -+------------------+-------------------------------------------------------------------------+ -| Power Switch | Power On/Off Switch. Toggling toward the Boot button powers the | -| | board on, toggling away from Boot powers the board off. | -+------------------+-------------------------------------------------------------------------+ -| Power Selector | Power supply selector interface. The board can be powered either via | -| | USB or via the 5V Input interface. Select the power source with a | -| | jumper. For more details, see Section Setup Options, jumper header | -| | JP7. | -+------------------+-------------------------------------------------------------------------+ -| 5V input | 5V power supply interface for a standard coaxial power connector, | -| | 5.5 x 2.1 mm, center positive. This interface can be more convenient | -| | when the board is operating autonomously (not connected to a | -| | computer). | -+------------------+-------------------------------------------------------------------------+ -| 5V Power On LED | This red LED turns on when power is supplied to the board, either | -| | from USB or 5V Input. | -+------------------+-------------------------------------------------------------------------+ -| LDO | NCP1117(1A). 5V-to-3.3V LDO. NCP1117 can provide a maximum | -| | current of 1A. The LDO on the board has a fixed output voltage. | -| | Although, the user can install an LDO with adjustable output voltage. | -| | For details, please refer to `ESP-WROVER-KIT V4.1 schematic | -| | `_. | -+------------------+-------------------------------------------------------------------------+ -| Camera Connector | Camera interface, a standard OV7670 camera module. | -+------------------+-------------------------------------------------------------------------+ -| RGB LED | Red, green and blue (RGB) light emitting diodes (LEDs), can be | -| | controlled by pulse width modulation (PWM). | -+------------------+-------------------------------------------------------------------------+ -| I/O Connector | All the pins on the ESP32 module are broken out to pin headers. You | -| | can program ESP32 to enable multiple functions, such as PWM, ADC, | -| | DAC, I2C, I2S, SPI, etc. | -+------------------+-------------------------------------------------------------------------+ -| MicroSD Card | Useful for developing applications that access MicroSD card for data | -| Slot | storage and retrieval. | -+------------------+-------------------------------------------------------------------------+ -| LCD | Support for mounting and interfacing a 3.2” SPI (standard 4-wire | -| | Serial Peripheral Interface) LCD, as shown on figure | -| | :ref:`ESP-WROVER-KIT board layout - back` | -+------------------+-------------------------------------------------------------------------+ - -.. _setup options: - -Setup Options -************* - -There are three jumper blocks available to set up the board functionality. The most frequently -required options are listed in the table below. - -.. |jmpextpwr| image:: img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg - -.. |jmpusbpwr| image:: img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg - -.. |jmpjtag| image:: img/esp-wrover-kit-v4.1-jp2-jtag.jpg - -.. |jmpuart| image:: img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg - -.. |jmpctrl| image:: img/esp-wrover-kit-v4.1-jp14.jpg - -+------------------+--------------------------------------------------------------+ -| Header | Jumper Setting | Description of Functionality | -+========+================+=======================================================+ -| JP7 | |jmpextpwr| | Power ESP-WROVER-KIT via an external power supply | -+--------+----------------+-------------------------------------------------------+ -| JP7 | |jmpusbpwr| | Power ESP-WROVER-KIT via USB | -+--------+----------------+-------------------------------------------------------+ -| JP2 | |jmpjtag| | Enable JTAG functionality | -+--------+----------------+-------------------------------------------------------+ -| JP2 | |jmpuart| | Enable UART communication | -+--------+----------------+-------------------------------------------------------+ -| JP14 | |jmpctrl| | Enable RTS/CTS flow control for serial communication | -+--------+----------------+-------------------------------------------------------+ - -Allocation of ESP32 Pins -************************ - -Some pins / terminals of ESP32 are allocated for use with the onboard or external hardware. If -that hardware is not used, e.g., nothing is plugged into the Camera (JP4) header, then these -GPIOs can be used for other purposes. - -Some of the pins, such as GPIO0 or GPIO2, have multiple functions and some of them are shared -among onboard and external peripheral devices. Certain combinations of peripherals cannot work -together. For example, it is not possible to do JTAG debugging of an application that is using -SD card, because several pins are shared by JTAG and the SD card slot. - -In other cases, peripherals can coexist under certain conditions. This is applicable to, for -example, LCD screen and SD card that share only a single pin GPIO21. This pin is used to provide -D/C (Data / Control) signal for the LCD as well as the Card Detect signal read from the SD card -slot. If the card detect functionality is not essential, then it may be disabled by removing R167, -so both LCD and SD may operate together. - -For more details on which pins are shared among which peripherals, please refer to the table in -the next section. - -Main I/O Connector / JP1 -************************ - -The JP1 connector consists of 14x2 male pins whose functions are shown in the middle two “I/O” -columns of the table below. The two “Shared With” columns on both sides describe where else on -the board a certain GPIO is used. - -+-------------------+------+------+----------------------+ -| Shared With | I/O | I/O | Shared With | -+===================+======+======+======================+ -| n/a | 3.3V | GND | n/a | -+-------------------+------+------+----------------------+ -| NC/XTAL | IO32 | IO33 | NC/XTAL | -+-------------------+------+------+----------------------+ -| JTAG, MicroSD | IO12 | IO13 | JTAG, MicroSD | -+-------------------+------+------+----------------------+ -| JTAG, MicroSD | IO14 | IO27 | Camera | -+-------------------+------+------+----------------------+ -| Camera | IO26 | IO25 | Camera, LCD | -+-------------------+------+------+----------------------+ -| Camera | IO35 | IO34 | Camera | -+-------------------+------+------+----------------------+ -| Camera | IO39 | IO36 | Camera | -+-------------------+------+------+----------------------+ -| JTAG | EN | IO23 | Camera, LCD | -+-------------------+------+------+----------------------+ -| Camera, LCD | IO22 | IO21 | Camera, LCD, MicroSD | -+-------------------+------+------+----------------------+ -| Camera, LCD | IO19 | IO18 | Camera, LCD | -+-------------------+------+------+----------------------+ -| Camera, LCD | IO5 | IO17 | PSRAM | -+-------------------+------+------+----------------------+ -| PSRAM | IO16 | IO4 | LED, Camera, MicroSD | -+-------------------+------+------+----------------------+ -| Camera, LED, Boot | IO0 | IO2 | LED, MicroSD | -+-------------------+------+------+----------------------+ -| JTAG, MicroSD | IO15 | 5V | | -+-------------------+------+------+----------------------+ - -Legend: - - - NC/XTAL - 32.768 kHz Oscillator - - JTAG - JTAG / JP2 - - Boot - Boot button / SW2 - - Camera - Camera / JP4 - - LED - RGB LED - - MicroSD - MicroSD Card / J4 - - LCD - LCD / U5 - - PSRAM - ESP32-WROVER-E’s PSRAM - -32.768 kHz Oscillator -********************* - -+---+-----------+ -| . | ESP32 Pin | -+===+===========+ -| 1 | GPIO32 | -+---+-----------+ -| 2 | GPIO33 | -+---+-----------+ - -.. note:: - - Since GPIO32 and GPIO33 are connected to the oscillator by default, they are not connected to - the JP1 I/O connector to maintain signal integrity. This allocation may be changed from the - oscillator to JP1 by desoldering the zero-ohm resistors from positions R11 / R23 and re- - soldering them to positions R12 / R24. - -SPI Flash / JP2 -*************** - -+---+--------------+ -| . | ESP32 Pin | -+===+==============+ -| 1 | CLK / GPIO6 | -+---+--------------+ -| 2 | SD0 / GPIO7 | -+---+--------------+ -| 3 | SD1 / GPIO8 | -+---+--------------+ -| 4 | SD2 / GPIO9 | -+---+--------------+ -| 5 | SD3 / GPIO10 | -+---+--------------+ -| 6 | CDM / GPIO11 | -+---+--------------+ - -.. important:: - The module’s flash bus is connected to the jumper block JP2 through zero-ohm resistors R140 ~ - R145. If the flash memory needs to operate at the frequency of 80 MHz, for reasons such as - improving the integrity of bus signals, you can desolder these resistors to disconnect the - module’s flash bus from the pin header JP2. - -JTAG / JP2 -********** - -+---+---------------+-------------+ -| . | ESP32 Pin | JTAG Signal | -+===+===============+=============+ -| 1 | EN | TRST_N | -+---+---------------+-------------+ -| 2 | MTMS / GPIO14 | TMS | -+---+---------------+-------------+ -| 3 | MTDO / GPIO15 | TDO | -+---+---------------+-------------+ -| 4 | MTDI / GPIO12 | TDI | -+---+---------------+-------------+ -| 5 | MTCK / GPIO13 | TCK | -+---+---------------+-------------+ - -Camera / JP4 -************ - -+----+-----------+-----------------------------+ -| . | ESP32 Pin | Camera Signal | -+====+===========+=============================+ -| 1 | n/a | 3.3V | -+----+-----------+-----------------------------+ -| 2 | n/a | Ground | -+----+-----------+-----------------------------+ -| 3 | GPIO27 | SIO_C / SCCB Clock | -+----+-----------+-----------------------------+ -| 4 | GPIO26 | SIO_D / SCCB Data | -+----+-----------+-----------------------------+ -| 5 | GPIO25 | VSYNC / Vertical Sync | -+----+-----------+-----------------------------+ -| 6 | GPIO23 | HREF / Horizontal Reference | -+----+-----------+-----------------------------+ -| 7 | GPIO22 | PCLK / Pixel Clock | -+----+-----------+-----------------------------+ -| 8 | GPIO21 | XCLK / System Clock | -+----+-----------+-----------------------------+ -| 9 | GPIO35 | D7 / Pixel Data Bit 7 | -+----+-----------+-----------------------------+ -| 10 | GPIO34 | D6 / Pixel Data Bit 6 | -+----+-----------+-----------------------------+ -| 11 | GPIO39 | D5 / Pixel Data Bit 5 | -+----+-----------+-----------------------------+ -| 12 | GPIO36 | D4 / Pixel Data Bit 4 | -+----+-----------+-----------------------------+ -| 13 | GPIO19 | D3 / Pixel Data Bit 3 | -+----+-----------+-----------------------------+ -| 14 | GPIO18 | D2 / Pixel Data Bit 2 | -+----+-----------+-----------------------------+ -| 15 | GPIO5 | D1 / Pixel Data Bit 1 | -+----+-----------+-----------------------------+ -| 16 | GPIO4 | D0 / Pixel Data Bit 0 | -+----+-----------+-----------------------------+ -| 17 | GPIO0 | RESET / Camera Reset | -+----+-----------+-----------------------------+ -| 18 | n/a | PWDN / Camera Power Down | -+----+-----------+-----------------------------+ - -- Signals D0 .. D7 denote camera data bus - -RGB LED -******* - -+----+-----------+---------+ -| . | ESP32 Pin | RGB LED | -+====+===========+=========+ -| 1 | GPIO0 | Red | -+----+-----------+---------+ -| 2 | GPIO2 | Green | -+----+-----------+---------+ -| 3 | GPIO4 | Blue | -+----+-----------+---------+ - -MicroSD Card -************ - -+---+---------------+----------------+ -| . | ESP32 Pin | MicroSD Signal | -+===+===============+================+ -| 1 | MTDI / GPIO12 | DATA2 | -+---+---------------+----------------+ -| 2 | MTCK / GPIO13 | CD / DATA3 | -+---+---------------+----------------+ -| 3 | MTDO / GPIO15 | CMD | -+---+---------------+----------------+ -| 4 | MTMS / GPIO14 | CLK | -+---+---------------+----------------+ -| 5 | GPIO2 | DATA0 | -+---+---------------+----------------+ -| 6 | GPIO4 | DATA1 | -+---+---------------+----------------+ -| 7 | GPIO21 | Card Detect | -+---+---------------+----------------+ - -LCD / U5 -******** - -+---+-----------+------------+ -| . | ESP32 Pin | LCD Signal | -+===+===========+============+ -| 1 | GPIO18 | RESET | -+---+-----------+------------+ -| 2 | GPIO19 | SCL | -+---+-----------+------------+ -| 3 | GPIO21 | D/C | -+---+-----------+------------+ -| 4 | GPIO22 | CS | -+---+-----------+------------+ -| 5 | GPIO23 | SDA | -+---+-----------+------------+ -| 6 | GPIO25 | SDO | -+---+-----------+------------+ -| 7 | GPIO5 | Backlight | -+---+-----------+------------+ - -Start Application Development -***************************** - -Before powering up your ESP-WROVER-KIT, please make sure that the board is in good -condition with no obvious signs of damage. - -Initial Setup -************* - -Please set only the following jumpers shown in the pictures below: - -- Select USB as the power source using the jumper block JP7. -- Enable UART communication using the jumper block JP2. - -+------------------------+---------------------------+ -| Power up from USB port | Enable UART communication | -+========+===============+===========================+ -| |jmpusbpwr| | |jmpuart| | -+------------------------+---------------------------+ - -Do not install any other jumpers. - -Turn the Power Switch to ON, the 5V Power On LED should light up. - -Supported Features -================== - -Current Zephyr's ESP32-Wrover-Kit board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp_wrover_kit - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp_wrover_kit - :goals: build - -The usual ``flash`` target will work with the ``esp_wrover_kit`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp_wrover_kit - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp_wrover_kit - -Debugging -********* - -ESP32 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -On the ESP-WROVER-KIT board, the JTAG pins are connected internally to -a USB serial port on the same device as the console. These boards -require no external hardware and are debuggable as-is. The JTAG -signals, however, must be jumpered closed to connect the internal -controller (the default is to leave them disconnected). The jumper -headers are on the right side of the board as viewed from the power -switch, next to similar headers for SPI and UART. See -`ESP-WROVER-32 V3 Getting Started Guide`_ for details. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp_wrover_kit - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp_wrover_kit - :goals: debug - -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`ESP-WROVER-32 V3 Getting Started Guide`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/esp32/get-started-wrover-kit.html - -Related Documents -***************** - -.. _ESP-WROVER-KIT V4.1 schematics: https://dl.espressif.com/dl/schematics/ESP-WROVER-KIT_V4_1.pdf (PDF) -.. _ESP-WROVER-KIT V4.1 layout: https://dl.espressif.com/dl/schematics/ESP-WROVER-KIT_V4.1.dxf (DXF) -.. _ESP32 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf (PDF) -.. _ESP32-WROVER-E Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf (PDF) -.. _ESP32 Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp_wrover_kit/esp_wrover_kit.dts b/boards/xtensa/esp_wrover_kit/esp_wrover_kit.dts deleted file mode 100644 index 3a31d745d63..00000000000 --- a/boards/xtensa/esp_wrover_kit/esp_wrover_kit.dts +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp_wrover_kit-pinctrl.dtsi" - -/ { - model = "esp32"; - compatible = "espressif,esp32"; - - aliases { - led0 = &blue_led; - led1 = &green_led; - led2 = &red_led; - pwm-led0 = &pwm_led_red; - pwm-led1 = &pwm_led_green; - pwm-led2 = &pwm_led_blue; - red-pwm-led = &pwm_led_red; - green-pwm-led = &pwm_led_green; - blue-pwm-led = &pwm_led_blue; - uart-0 = &uart0; - i2c-0 = &i2c0; - watchdog0 = &wdt0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,display = &ili9341; - }; - - leds { - compatible = "gpio-leds"; - - blue_led: led_0 { - gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - label = "Blue - LED0"; - }; - - green_led: led_1 { - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - label = "Green - LED1"; - }; - - red_led: led_2 { - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - label = "Red - LED2"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led_red: pwm_led_0 { - label = "Red PWM LED"; - pwms = <&ledc0 0 PWM_HZ(100) PWM_POLARITY_NORMAL>; - }; - pwm_led_green: pwm_led_1 { - label = "Green PWM LED"; - pwms = <&ledc0 1 PWM_HZ(100) PWM_POLARITY_NORMAL>; - }; - pwm_led_blue: pwm_led_2 { - label = "Blue PWM LED"; - pwms = <&ledc0 2 PWM_HZ(100) PWM_POLARITY_NORMAL>; - }; - }; - - mipi_dbi { - compatible = "zephyr,mipi-dbi-spi"; - dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - spi-dev = <&spi3>; - write-only; - #address-cells = <1>; - #size-cells = <0>; - - ili9341: ili9341@0 { - compatible = "ilitek,ili9341"; - mipi-max-frequency = <25000000>; - reg = <0>; - pixel-format = <0>; - rotation = <0>; - width = <240>; - height = <320>; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; - - /* FIXME: should be part of the display node */ - lcd-backlight { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - output-low; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&ledc0 { - pinctrl-0 = <&ledc0_default>; - pinctrl-names = "default"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - channel0@0 { - reg = <0x0>; - timer = <0>; - }; - channel1@1 { - reg = <0x1>; - timer = <1>; - }; - channel2@2 { - reg = <0x2>; - timer = <2>; - }; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/esp_wrover_kit/esp_wrover_kit.yaml b/boards/xtensa/esp_wrover_kit/esp_wrover_kit.yaml deleted file mode 100644 index 3d1b9921904..00000000000 --- a/boards/xtensa/esp_wrover_kit/esp_wrover_kit.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: esp_wrover_kit -name: ESP WROVER KIT -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - watchdog - - uart - - nvs - - pwm - - spi - - counter - - entropy -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig b/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig deleted file mode 100644 index f2b8f7b663c..00000000000 --- a/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP_WROVER_KIT=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.board b/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.board deleted file mode 100644 index b364fad83fd..00000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# HELTEC ESP32 board configuration - -# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HELTEC_WIFI_LORA32 - bool "HELTEC WiFi LoRa 32 (V2) Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_D0WD_V3 -endchoice diff --git a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.defconfig b/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.defconfig deleted file mode 100644 index eaf538cd281..00000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# HELTEC board configuration - -# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "heltec_wifi_lora32" - depends on BOARD_HELTEC_WIFI_LORA32 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/heltec_wifi_lora32_v2/doc/index.rst b/boards/xtensa/heltec_wifi_lora32_v2/doc/index.rst deleted file mode 100644 index 1029b21dd60..00000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/doc/index.rst +++ /dev/null @@ -1,208 +0,0 @@ -.. _heltec_wifi_lora32_v2: - -Heltec WiFi LoRa 32 (V2) -######################## - -Overview -******** - -Heltec WiFi LoRa 32 is a classic IoT dev-board designed & produced by Heltec Automation(TM), it's a highly -integrated product based on ESP32 + SX127x, it has Wi-Fi, BLE, LoRa functions, also Li-Po battery management -system, 0.96" OLED are also included. [1]_ - -The features include the following: - -- Microprocessor: ESP32 (dual-core 32-bit MCU + ULP core) -- LoRa node chip SX1276/SX1278 -- Micro USB interface with a complete voltage regulator, ESD protection, short circuit protection, - RF shielding, and other protection measures -- Onboard SH1.25-2 battery interface, integrated lithium battery management system -- Integrated WiFi, LoRa, Bluetooth three network connections, onboard Wi-Fi, Bluetooth dedicated 2.4GHz - metal 3D antenna, reserved IPEX (U.FL) interface for LoRa use -- Onboard 0.96-inch 128*64 dot matrix OLED display -- Integrated CP2102 USB to serial port chip - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: heltec_wifi_lora32_v2 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wifi_lora32_v2 - :goals: build - -The usual ``flash`` target will work with the ``heltec_wifi_lora32_v2`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wifi_lora32_v2 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! heltec_wifi_lora32_v2 - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wifi_lora32_v2 - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wifi_lora32_v2 - :goals: debug - -Utilizing Hardware Features -*************************** - -Onboard OLED display -==================== - -The onboard OLED display is of type ``ssd1306``, has 128*64 pixels and is -connected via I2C. It can therefore be used by enabling the -:ref:`ssd1306_128_shield` as shown in the following for the :zephyr:code-sample:`lvgl` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/subsys/display/lvgl - :board: heltec_wifi_lora32_v2 - :shield: ssd1306_128x64 - :goals: flash - -References -********** - -- `Heltec WiFi LoRa (v2) Pinout Diagram `_ -- `Heltec WiFi LoRa (v2) Schematic Diagrams `_ -- `ESP32 Toolchain `_ -- `esptool documentation `_ -- `OpenOCD ESP32 `_ - -.. [1] https://heltec.org/project/wifi-lora-32/ diff --git a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.dts b/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.dts deleted file mode 100644 index 636f1afd354..00000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.dts +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "heltec_wifi_lora32_v2-pinctrl.dtsi" -#include - -/ { - model = "heltec_wifi_lora32"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - led0 = &led0; - sw0 = &button0; - watchdog0 = &wdt0; - lora0 = &lora0; - }; - - leds { - compatible = "gpio-leds"; - led0: led { - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - label = "White LED"; - }; - - vext: vext { - gpios = <&gpio0 21 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "External VCC"; - }; - - oledrst: oledrst { - gpios = <&gpio0 16 (GPIO_PULL_UP | GPIO_ACTIVE_HIGH)>; - label = "OLED Reset"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "PRG Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; - cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - lora0: lora@0 { - compatible = "semtech,sx1276"; - reg = <0>; - reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - dio-gpios = - /* SX1276 D0 -> GPIO26 */ - <&gpio0 26 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, - /* SX1276 D1 -> GPIO35 */ - <&gpio1 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, - /* SX1276 D1 -> GPIO34 */ - <&gpio1 2 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; - spi-max-frequency = <1000000>; - power-amplifier-output = "pa-boost"; - }; -}; - -&flash0 { - /* the board is using plain d0wd SoC part without the flash - * so any additional flash size should be defined at the board level - */ - reg = <0x0 DT_SIZE_M(8)>; - - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - -/* Required by the ssd1306_128x64 shield which enables the OLED display */ -arduino_i2c: &i2c0 {}; diff --git a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.yaml b/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.yaml deleted file mode 100644 index 740755b5e6a..00000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: heltec_wifi_lora32_v2 -name: HELTEC WiFi LoRa 32 (V2) Board -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - watchdog - - uart - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig b/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig deleted file mode 100644 index ac8cf88d749..00000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_HELTEC_WIFI_LORA32=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.board b/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.board deleted file mode 100644 index a590916109d..00000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# Heltec Wireless Stick Lite (V3) board configuration - -# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) -# Copyright (c) 2023 The Zephyr Project Contributors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HELTEC_WIRELESS_STICK_LITE - bool "Heltec Wireless Stick Lite (V3) Board" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_FN8 -endchoice diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.defconfig b/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.defconfig deleted file mode 100644 index ea79f62e2fa..00000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Heltec Wireless Stick Lite (V3) board configuration - -# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) -# Copyright (c) 2023 The Zephyr Project Contributors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "heltec_wireless_stick_lite_v3" - depends on BOARD_HELTEC_WIRELESS_STICK_LITE - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/doc/index.rst b/boards/xtensa/heltec_wireless_stick_lite_v3/doc/index.rst deleted file mode 100644 index 24170d4cb1b..00000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/doc/index.rst +++ /dev/null @@ -1,306 +0,0 @@ -.. heltec_wireless_stick_lite_v3: - -HelTec Wireless Stick Lite (V3) -############################### - -Overview -******** - -HelTec Wireless Stick Lite (V3) is a development board with Wi-Fi, Bluetooth and LoRa support. It is designed and produced by HelTec Automation(TM). [1]_ - -.. figure:: heltec_wireless_stick_lite_v3.webp - :width: 400px - :align: center - :alt: HelTec Wireless Stick Lite (V3) - - HelTec Wireless Stick Lite (V3) (Credit: Chengdu HelTec Automation Technology Co., Ltd.) - -Hardware -******** - -The main hardware features are: - -- ESP32-S3FN8 low-power MCU-based SoC (dual-core Xtensa® 32-bit LX7 microprocessor, five stage pipeline rack Structure, main frequency up to 240 MHz). -- Semtech SX1262 LoRa node chip -- Type-C USB interface with a complete voltage regulator, ESD protection, short circuit protection, RF shielding, and other protection measures (note: you need an USB-A to USB-C cable if you want to power-up the board from USB). -- Onboard SH1.25-2 battery interface, integrated lithium battery management system (charge and discharge management, overcharge protection, battery power detection, USB / battery power automatic switching). -- Integrated WiFi and Bluetooth interfaces with 2.4GHz metal spring antenna and reserved IPEX (U.FL) interface for LoRa use. -- Integrated CP2102 USB to serial port chip, convenient for program downloading, debugging information printing. -- Good RF circuit design and low-power design. - -Supported Features -================== -- LoRa via SPI -- UART0 (USB Serial via CP2102) -- UART1 -- I2C -- CAN (optional, need to enable) -- PWM LED -- User Switch / Button - -Connections and IOs -=================== - -.. figure:: heltec_wireless_stick_lite_v3_pinout.webp - :width: 600px - :align: center - :alt: HelTec Wireless Stick Lite (V3) Pinout - - Pinout (Credit: Chengdu HelTec Automation Technology Co., Ltd.) - -.. table:: HelTec Wireless Stick Lite (V3) Pinout - :widths: auto - - +--------+---------+-----------------------------+ - | Header | Function| Description | - +========+=========+=============================+ - | J2.1 | Ve | | - +--------+---------+-----------------------------+ - | J2.2 | GND | | - +--------+---------+-----------------------------+ - | J2.3 | | | - +--------+---------+-----------------------------+ - | J2.4 | U0RXD | Zephyr Console+Shell | - +--------+---------+-----------------------------+ - | J2.5 | U0TXD | Zephyr Console+Shell | - +--------+---------+-----------------------------+ - | J2.6 | | | - +--------+---------+-----------------------------+ - | J2.7 | | | - +--------+---------+-----------------------------+ - | J2.8 | GPIO35 | PWM LED Control | - +--------+---------+-----------------------------+ - | J2.9 | GPIO36 | Vext Control | - +--------+---------+-----------------------------+ - | J2.10 | GPIO37 | ADC Control | - +--------+---------+-----------------------------+ - | J2.11 | | | - +--------+---------+-----------------------------+ - | J2.12 | GPIO39 | | - +--------+---------+-----------------------------+ - | J2.13 | GPIO40 | | - +--------+---------+-----------------------------+ - | J2.14 | GPIO41 | | - +--------+---------+-----------------------------+ - | J2.15 | GPIO42 | | - +--------+---------+-----------------------------+ - | J2.16 | GPIO45 | | - +--------+---------+-----------------------------+ - | J2.17 | GPIO46 | | - +--------+---------+-----------------------------+ - | J2.18 | ADC1_CH0| Battery Voltage Measurement | - +--------+---------+-----------------------------+ - | J2.19 | | | - +--------+---------+-----------------------------+ - | J2.20 | | | - +--------+---------+-----------------------------+ - | J3.1 | 5V | | - +--------+---------+-----------------------------+ - | J3.2 | 3V3 | | - +--------+---------+-----------------------------+ - | J3.3 | GND | | - +--------+---------+-----------------------------+ - | J3.4 | GPIO47 | | - +--------+---------+-----------------------------+ - | J3.5 | GPIO48 | | - +--------+---------+-----------------------------+ - | J3.6 | GPIO0 | User Switch | - +--------+---------+-----------------------------+ - | J3.7 | | | - +--------+---------+-----------------------------+ - | J3.8 | | | - +--------+---------+-----------------------------+ - | J3.9 | U1RXD | UART 1 | - +--------+---------+-----------------------------+ - | J3.10 | GPIO21 | | - +--------+---------+-----------------------------+ - | J3.11 | | | - +--------+---------+-----------------------------+ - | J3.12 | U1TXD | UART 1 | - +--------+---------+-----------------------------+ - | J3.13 | | | - +--------+---------+-----------------------------+ - | J3.14 | NC | Reset Switch | - +--------+---------+-----------------------------+ - | J3.15 | | | - +--------+---------+-----------------------------+ - | J3.16 | | | - +--------+---------+-----------------------------+ - | J3.17 | | | - +--------+---------+-----------------------------+ - | J3.18 | | | - +--------+---------+-----------------------------+ - | J3.19 | TWAI_TX | CAN (optional) | - +--------+---------+-----------------------------+ - | J3.20 | TWAI_RX | CAN (optional) | - +--------+---------+-----------------------------+ - - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Programming and Debugging -************************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the EPS32-S3 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: heltec_wireless_stick_lite_v3 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32S3 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wireless_stick_lite_v3 - :goals: build - -The usual ``flash`` target will work with the ``heltec_wireless_stick_lite_v3`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wireless_stick_lite_v3 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! heltec_wireless_stick_lite_v3 - -Debugging -========= - -As with much custom hardware, the ESP32S3 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wireless_stick_lite_v3 - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wireless_stick_lite_v3 - :goals: debug - -References -********** - -- `Heltec Wireless Stick Lite (v3) Pinout Diagram `_ -- `Heltec Wireless Stick Lite (v3) Schematic Diagrams `_ -- `ESP-IDF Programming Guide `_ -- `esptool documentation `_ -- `OpenOCD ESP32 `_ - -.. [1] https://heltec.org/project/wireless-stick-lite-v2/ diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.dts b/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.dts deleted file mode 100644 index 9a23a008c2f..00000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.dts +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * Copyright (c) 2023 The Zephyr Project Contributors - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "heltec_wireless_stick_lite_v3-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "heltec_wireless_stick_lite_v3"; - compatible = "espressif,esp32s3"; - - aliases { - pwm-0 = &ledc0; - pwm-led0 = &pwm_led_white; - uart-0 = &uart0; - uart-1 = &uart1; - i2c-0 = &i2c0; - lora0 = &lora0; - sw0 = &button0; - watchdog0 = &wdt0; - }; - - leds { - compatible = "gpio-leds"; - - vext: vext { - gpios = <&gpio0 36 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Vext Control"; - }; - - adc: adc { - gpios = <&gpio0 37 GPIO_ACTIVE_LOW>; - label = "ADC Control"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led_white: pwm_led_gpio0_35 { - label = "White PWM LED"; - pwms = <&ledc0 0 PWM_MSEC(10) PWM_POLARITY_NORMAL>; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "USER SW"; - zephyr,code = ; - }; - }; - - vbatt { - compatible = "voltage-divider"; - io-channels = <&adc1 0>; - output-ohms = <100000>; - full-ohms = <(100000 + 390000)>; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&adc1 { - status ="okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&ledc0 { - pinctrl-0 = <&ledc0_default>; - pinctrl-names = "default"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - channel0@0 { - reg = <0x0>; - timer = <0>; - }; -}; - -&i2c0 { - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; - lora0: lora@0 { - compatible = "semtech,sx1262"; - reg = <0>; - reset-gpios = <&gpio0 12 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; - busy-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - dio1-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - dio2-tx-enable; - dio3-tcxo-voltage = ; - tcxo-power-startup-delay-ms = <5>; - spi-max-frequency = <16000000>; - }; -}; - -&twai { - pinctrl-0 = <&twai_default>; - pinctrl-names = "default"; - bus-speed = <125000>; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.yaml b/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.yaml deleted file mode 100644 index 05c89b6d984..00000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: heltec_wireless_stick_lite_v3 -name: Heltec Wireless Stick Lite (V3) -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - can - - counter - - watchdog - - entropy - - pwm - - dma - - lora -testing: - ignore_tags: - - net - - bluetooth diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_defconfig b/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_defconfig deleted file mode 100644 index a32ddde0422..00000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_HELTEC_WIRELESS_STICK_LITE=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CLOCK_CONTROL=y -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_PWM=y -CONFIG_SERIAL=y -CONFIG_SPI=y -CONFIG_UART_CONSOLE=y diff --git a/boards/xtensa/index.rst b/boards/xtensa/index.rst deleted file mode 100644 index efe46624acf..00000000000 --- a/boards/xtensa/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-xtensa: - -Xtensa Boards -############# - -.. toctree:: - :maxdepth: 1 - :glob: - - **/index diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.board b/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.board deleted file mode 100644 index d51735c9caa..00000000000 --- a/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_ADSP_ACE15_MTPM - bool "Intel ADSP ACE 1.5 Meteor PCH M" - depends on SOC_SERIES_INTEL_ACE diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.defconfig b/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.defconfig deleted file mode 100644 index ca7aa07cd95..00000000000 --- a/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_ADSP_ACE15_MTPM - -config BOARD - default "intel_adsp_ace15_mtpm" - -if DAI_INTEL_SSP - -config DAI_SSP_HAS_POWER_CONTROL - def_bool y - -endif - -endif # BOARD_INTEL_ADSP_ACE15_MTPM diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/board.cmake b/boards/xtensa/intel_adsp_ace15_mtpm/board.cmake deleted file mode 100644 index e9778da4d84..00000000000 --- a/boards/xtensa/intel_adsp_ace15_mtpm/board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -board_set_rimage_target(mtl) - -set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace15_mtpm/board.cmake") - -board_finalize_runner_args(intel_adsp) diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm_defconfig b/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm_defconfig deleted file mode 100644 index b544d3db403..00000000000 --- a/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_SOC_SERIES_INTEL_ACE=y -CONFIG_SOC_INTEL_ACE15_MTPM=y -CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_MM_DRV=y -CONFIG_CRYPTO=y - -CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/pre_dt_board.cmake b/boards/xtensa/intel_adsp_ace15_mtpm/pre_dt_board.cmake deleted file mode 100644 index 7a471ca8758..00000000000 --- a/boards/xtensa/intel_adsp_ace15_mtpm/pre_dt_board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - dmic0: dmic0@10000 & dmic1: dmic1@10000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board b/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board deleted file mode 100644 index 26994dfb6c5..00000000000 --- a/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_ADSP_ACE20_LNL - bool "Intel ADSP ACE 2.0 Lunar Lake PCH" - depends on SOC_SERIES_INTEL_ACE diff --git a/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig b/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig deleted file mode 100644 index 756481eba01..00000000000 --- a/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_ADSP_ACE20_LNL - -config BOARD - default "intel_adsp_ace20_lnl" - -endif # BOARD_INTEL_ADSP_ACE20_LNL diff --git a/boards/xtensa/intel_adsp_ace20_lnl/board.cmake b/boards/xtensa/intel_adsp_ace20_lnl/board.cmake deleted file mode 100644 index 04d679fba02..00000000000 --- a/boards/xtensa/intel_adsp_ace20_lnl/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS acesim) - -board_set_rimage_target(lnl) - -set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace20_lnl/board.cmake") diff --git a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig b/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig deleted file mode 100644 index 9be759e2e9a..00000000000 --- a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_SOC_SERIES_INTEL_ACE=y -CONFIG_SOC_INTEL_ACE20_LNL=y -CONFIG_BOARD_INTEL_ADSP_ACE20_LNL=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_MM_DRV=y -CONFIG_MM_DRV_INTEL_ADSP_MTL_TLB=y - -CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/xtensa/intel_adsp_cavs25/Kconfig.board b/boards/xtensa/intel_adsp_cavs25/Kconfig.board deleted file mode 100644 index 275d43b3c77..00000000000 --- a/boards/xtensa/intel_adsp_cavs25/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_ADSP_CAVS25 - bool "Intel ADSP CAVS 2.5" - depends on SOC_SERIES_INTEL_ADSP_CAVS - -config BOARD_INTEL_ADSP_CAVS25_TGPH - bool "Intel ADSP CAVS 2.5 for Tiger Lake H PCH" - depends on SOC_SERIES_INTEL_ADSP_CAVS diff --git a/boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig b/boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig deleted file mode 100644 index 03d5c7a1ad3..00000000000 --- a/boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_ADSP_CAVS25 || BOARD_INTEL_ADSP_CAVS25_TGPH - -config BOARD - default "intel_adsp_cavs25" if BOARD_INTEL_ADSP_CAVS25 - default "intel_adsp_cavs25_tgph" if BOARD_INTEL_ADSP_CAVS25_TGPH - - - -if DAI_INTEL_SSP - -config DAI_SSP_HAS_POWER_CONTROL - def_bool y - -endif - -endif # BOARD_INTEL_ADSP_CAVS25 || BOARD_INTEL_ADSP_CAVS25_TGPH diff --git a/boards/xtensa/intel_adsp_cavs25/board.cmake b/boards/xtensa/intel_adsp_cavs25/board.cmake deleted file mode 100644 index 1bdb2698c12..00000000000 --- a/boards/xtensa/intel_adsp_cavs25/board.cmake +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if($ENV{CAVS_OLD_FLASHER}) - board_set_flasher_ifnset(misc-flasher) - board_finalize_runner_args(misc-flasher) -endif() - -board_set_flasher_ifnset(intel_adsp) - -set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in cavs25/board.cmake") - -if(CONFIG_BOARD_INTEL_ADSP_CAVS25) -board_set_rimage_target(tgl) -endif() - -if(CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH) -board_set_rimage_target(tgl-h) -endif() - -board_finalize_runner_args(intel_adsp) diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig deleted file mode 100644 index 2787e3649f9..00000000000 --- a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_SOC_INTEL_CAVS_V25=y -CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH=y -CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y - - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_XTENSA_RESET_VECTOR=y - -CONFIG_XTENSA_USE_CORE_CRT1=y - -CONFIG_MULTI_LEVEL_INTERRUPTS=y -CONFIG_2ND_LEVEL_INTERRUPTS=y - -CONFIG_BUILD_OUTPUT_BIN=n - -CONFIG_DAI_SSP_HAS_POWER_CONTROL=y - -CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/xtensa/intel_adsp_cavs25/pre_dt_board.cmake b/boards/xtensa/intel_adsp_cavs25/pre_dt_board.cmake deleted file mode 100644 index 7a471ca8758..00000000000 --- a/boards/xtensa/intel_adsp_cavs25/pre_dt_board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - dmic0: dmic0@10000 & dmic1: dmic1@10000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/xtensa/kincony_kc868_a32/Kconfig.board b/boards/xtensa/kincony_kc868_a32/Kconfig.board deleted file mode 100644 index 098f377092b..00000000000 --- a/boards/xtensa/kincony_kc868_a32/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Bartosz Bilas -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_KINCONY_KC868_A32 - bool "KINCONY KC868-A32 Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROOM_32UE_N4 -endchoice diff --git a/boards/xtensa/kincony_kc868_a32/Kconfig.defconfig b/boards/xtensa/kincony_kc868_a32/Kconfig.defconfig deleted file mode 100644 index 85e02264b5a..00000000000 --- a/boards/xtensa/kincony_kc868_a32/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Bartosz Bilas -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "kincony_kc868_a32" - depends on BOARD_KINCONY_KC868_A32 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_SIZE - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/xtensa/kincony_kc868_a32/doc/index.rst b/boards/xtensa/kincony_kc868_a32/doc/index.rst deleted file mode 100644 index dfd4797701b..00000000000 --- a/boards/xtensa/kincony_kc868_a32/doc/index.rst +++ /dev/null @@ -1,97 +0,0 @@ -.. _kincony_kc868_a32: - -KINCONY KC868-A32 -################# - -Overview -******** - -Kincony KC868-A32 is a home automation relay module based on the -Espressif ESP-WROOM-32 module with all its inherent capabilities -(Wi-Fi, Bluetooth, etc.) - -The features include the following: - -- 32 digital optoisolated inputs “dry contact” -- 4 analog inputs 0-5 V -- 32 relays 220 V, 10 A (COM, NO, NC) -- RS485 interface -- I2C connector -- Connector GSM/HMI -- Ethernet LAN8270A -- USB Type-B connector for programming and filling firmware -- RESET and DOWNLOAD buttons -- Powered by 12V DC - -.. figure:: img/kincony_kc868_a32.jpg - :align: center - :alt: KINCONCY-KC868-A32 - - KINCONCY-KC868-A32 - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: kincony_kc868_a32 - :goals: build - -The usual ``flash`` target will work with the ``kincony_kc868_a32`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: kincony_kc868_a32 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! kincony_kc868_a32 - -Enabling Ethernet -***************** - -Enable Ethernet in KConfig: - -.. code-block:: cfg - - CONFIG_NETWORKING=y - CONFIG_NET_L2_ETHERNET=y - CONFIG_MDIO=y - -References -********** - -.. _KINCONY KC868-A32 User Guide: https://www.kincony.com/arduino-esp32-32-channel-relay-module-kc868-a32.html diff --git a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.dts b/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.dts deleted file mode 100644 index 2690ae75b24..00000000000 --- a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.dts +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (c) 2023 Bartosz Bilas - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "kincony_kc868_a32-pinctrl.dtsi" - -/ { - model = "Kincony KC868-A32"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - watchdog0 = &wdt0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 13 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - - i2c0_pcf8574@21 { - compatible = "nxp,pcf857x"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c0_pcf8574@22 { - compatible = "nxp,pcf857x"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c0_pcf8574@24 { - compatible = "nxp,pcf857x"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c0_pcf8574@25 { - compatible = "nxp,pcf857x"; - reg = <0x25>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 5 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; - - i2c1_pcf8574@21 { - compatible = "nxp,pcf857x"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c1_pcf8574@22 { - compatible = "nxp,pcf857x"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c1_pcf8574@24 { - compatible = "nxp,pcf857x"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c1_pcf8574@25 { - compatible = "nxp,pcf857x"; - reg = <0x25>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_default>; - pinctrl-names = "default"; - status = "okay"; - - phy: ethernet-phy@0 { - compatible = "ethernet-phy"; - status = "okay"; - reg = <0>; - }; -}; - -ð { - status = "okay"; - phy-handle = <&phy>; - ref-clk-output-gpios = <&gpio0 17 0>; -}; - -&psram0 { - status = "disabled"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.yaml b/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.yaml deleted file mode 100644 index 72577b2572a..00000000000 --- a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: kincony_kc868_a32 -name: KINCONY-KC868-A32 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - watchdog - - uart - - nvs - - counter - - entropy -testing: - ignore_tags: - - net - - bluetooth -vendor: kincony diff --git a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32_defconfig b/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32_defconfig deleted file mode 100644 index 7bb4a23e794..00000000000 --- a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) Bartosz Bilas -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_KINCONY_KC868_A32=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y -CONFIG_I2C=y diff --git a/boards/xtensa/m5stack_atoms3/Kconfig.board b/boards/xtensa/m5stack_atoms3/Kconfig.board deleted file mode 100644 index 726e31773e2..00000000000 --- a/boards/xtensa/m5stack_atoms3/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5Stack AtomS3 board configuration - -# Copyright (c) 2023 Benjamin Cabé -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_M5STACK_ATOMS3 - bool "M5Stack AtomS3 Development Board" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_FN8 -endchoice diff --git a/boards/xtensa/m5stack_atoms3/Kconfig.defconfig b/boards/xtensa/m5stack_atoms3/Kconfig.defconfig deleted file mode 100644 index 94f209758eb..00000000000 --- a/boards/xtensa/m5stack_atoms3/Kconfig.defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# M5Stack AtomS3 board configuration -# Copyright (c) 2023 Benjamin Cabé -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_M5STACK_ATOMS3 - -config BOARD - default "m5stack_atoms3" - depends on BOARD_M5STACK_ATOMS3 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 65536 if BT - default 4096 - -config KERNEL_MEM_POOL - default y - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -config LV_COLOR_16_SWAP - default y if LVGL - -endif # BOARD_M5STACK_ATOMS3 diff --git a/boards/xtensa/m5stack_atoms3/doc/index.rst b/boards/xtensa/m5stack_atoms3/doc/index.rst deleted file mode 100644 index 2dd229be436..00000000000 --- a/boards/xtensa/m5stack_atoms3/doc/index.rst +++ /dev/null @@ -1,136 +0,0 @@ -.. _m5stack_atoms3: - -M5Stack AtomS3 -############## - -Overview -******** - -M5Stack AtomS3 is an ESP32-based development board from M5Stack. - -It features the following integrated components: - -- ESP32-S3FN8 chip (240MHz dual core, Wi-Fi/BLE 5.0) -- 512KB of SRAM -- 384KB of ROM -- 8MB of Flash -- LCD IPS TFT 0.85", 128x128 px screen (ST7789 compatible) -- 6-axis IMU MPU6886 -- Infrared emitter - - -.. figure:: img/m5stack_atoms3.webp - :align: center - :alt: M5Stack AtomS3 - - M5Stack AtomS3 - - -Supported Features -================== - -The Zephyr m5stack_atoms3 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - - -Start Application Development -***************************** - -Before powering up your M5Stack AtomS3, please make sure that the board is in good -condition with no obvious signs of damage. - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: shell - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_atoms3 - :goals: build - -The usual ``flash`` target will work with the ``m5stack_atoms3`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_atoms3 - :goals: flash - -The baud rate of 921600bps is set by default. If experiencing issues when flashing, -try using different values by using ``--esp-baud-rate `` option during -``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). - -You can also open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! m5stack_atoms3 - -Debugging ---------- - -M5Stack AtomS3 debugging is not supported due to pinout limitations. - -Related Documents -***************** - -- `M5Stack AtomS3 schematic `_ -- `ESP32S3 Datasheet `_ diff --git a/boards/xtensa/m5stack_atoms3/m5stack_atoms3.dts b/boards/xtensa/m5stack_atoms3/m5stack_atoms3.dts deleted file mode 100644 index 72ebd81b42f..00000000000 --- a/boards/xtensa/m5stack_atoms3/m5stack_atoms3.dts +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2023 Benjamin Cabé - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "m5stack_atoms3-pinctrl.dtsi" -#include "grove_connectors.dtsi" -#include - -/ { - model = "M5Stack AtomS3"; - compatible = "m5stack,atoms3"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,display = &st7789v; - }; - - aliases { - sw0 = &user_button_0; - watchdog0 = &wdt0; - accel0 = &mpu6886; - }; - - gpio_keys { - compatible = "gpio-keys"; - - /* This is the button that's underneath the LCD display */ - user_button_0: button_0 { - label = "User button 0"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; // G42 - zephyr,code = ; - }; - }; - - /* Regulators */ - lcd_backlight_en { - compatible = "regulator-fixed"; - regulator-name = "lcd_backlight_enable"; - enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - - mpu6886: mpu6886@68 { - compatible = "invensense,mpu6050"; - reg = <0x68>; - status = "okay"; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&trng0 { - status = "okay"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; - - st7789v: st7789v@0 { - compatible = "sitronix,st7789v"; - reg = <0>; - spi-max-frequency = <27000000>; - cmd-data-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; /* G33 */ - reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* G34 */ - - width = <128>; - height = <128>; - x-offset = <2>; - y-offset = <1>; - - vcom = <0x28>; - gctrl = <0x35>; - vrhs = <0x10>; - vdvs = <0x20>; - mdac = <0x00>; - gamma = <0x01>; - colmod = <0x55>; - lcm = <0x0c>; - porch-param = [0c 0c 00 33 33]; - cmd2en-param = [5a 69 02 00]; - pwctrl1-param = [a4 a1]; - pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; - nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; - ram-param = [00 E0]; - rgb-param = [40 02 14]; - }; - -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/m5stack_atoms3/m5stack_atoms3.yaml b/boards/xtensa/m5stack_atoms3/m5stack_atoms3.yaml deleted file mode 100644 index ed34b2f551d..00000000000 --- a/boards/xtensa/m5stack_atoms3/m5stack_atoms3.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: m5stack_atoms3 -name: M5Stack AtomS3 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - spi - - watchdog - - regulator - - uart - - pinmux - - nvs - - display -testing: - ignore_tags: - - net - - bluetooth -vendor: m5stack diff --git a/boards/xtensa/m5stack_atoms3/m5stack_atoms3_defconfig b/boards/xtensa/m5stack_atoms3/m5stack_atoms3_defconfig deleted file mode 100644 index 1000271dbe5..00000000000 --- a/boards/xtensa/m5stack_atoms3/m5stack_atoms3_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_M5STACK_ATOMS3=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_GPIO=y -CONFIG_REGULATOR=y # for LCD backlight - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/xtensa/m5stack_atoms3_lite/Kconfig.board b/boards/xtensa/m5stack_atoms3_lite/Kconfig.board deleted file mode 100644 index 2c77718895e..00000000000 --- a/boards/xtensa/m5stack_atoms3_lite/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5Stack AtomS3 Lite board configuration -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -# M5Stack AtomS3 Lite -config BOARD_M5STACK_ATOMS3_LITE - bool "M5Stack AtomS3 Lite Development Board" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_FN8 -endchoice diff --git a/boards/xtensa/m5stack_atoms3_lite/Kconfig.defconfig b/boards/xtensa/m5stack_atoms3_lite/Kconfig.defconfig deleted file mode 100644 index 8f982cec80b..00000000000 --- a/boards/xtensa/m5stack_atoms3_lite/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# M5Stack AtomS3 Lite board configuration -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_M5STACK_ATOMS3_LITE - -config BOARD - default "m5stack_atoms3_lite" - depends on BOARD_M5STACK_ATOMS3_LITE - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 98304 if WIFI - default 65536 if BT - default 4096 - -config KERNEL_MEM_POOL - default y - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice -endif # BOARD_M5STACK_ATOMS3_LITE diff --git a/boards/xtensa/m5stack_atoms3_lite/doc/index.rst b/boards/xtensa/m5stack_atoms3_lite/doc/index.rst deleted file mode 100644 index c51f580aa62..00000000000 --- a/boards/xtensa/m5stack_atoms3_lite/doc/index.rst +++ /dev/null @@ -1,134 +0,0 @@ -.. _m5stack_atoms3_lite: - -M5Stack AtomS3 Lite -################### - -Overview -******** - -M5Stack AtomS3 Lite is an ESP32-based development board from M5Stack. - -It features the following integrated components: - -- ESP32-S3FN8 chip (240MHz dual core, Wi-Fi/BLE 5.0) -- 512KB of SRAM -- 384KB of ROM -- 8MB of Flash -- RGB Status-LED - - -.. figure:: img/m5stack_atoms3_lite.webp - :align: center - :alt: M5Stack AtomS3 Lite - - M5Stack AtomS3 Lite - - -Supported Features -================== - -The Zephyr m5stack_atoms3_lite board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - - -Start Application Development -***************************** - -Before powering up your M5Stack AtomS3 Lite, please make sure that the board is in good -condition with no obvious signs of damage. - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: shell - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_atoms3_lite - :goals: build - -The usual ``flash`` target will work with the ``m5stack_atoms3_lite`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_atoms3_lite - :goals: flash - -The baud rate of 921600bps is set by default. If experiencing issues when flashing, -try using different values by using ``--esp-baud-rate `` option during -``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). - -You can also open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! m5stack_atoms3_lite - -Debugging ---------- - -M5Stack AtomS3 Lite debugging is not supported due to pinout limitations. - -Related Documents -***************** - -- `M5Stack AtomS3 Lite schematic `_ -- `ESP32S3 Datasheet `_ diff --git a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.dts b/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.dts deleted file mode 100644 index 51b65cfba0c..00000000000 --- a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.dts +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2023 Benjamin Cabé - * Copyright (c) 2023 Martin Kiepfer - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "m5stack_atoms3_lite-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "M5Stack AtomS3 Lite"; - compatible = "m5stack,atoms3_lite"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - sw0 = &user_button_0; - watchdog0 = &wdt0; - i2c-0 = &i2c0; - led-strip = &status_rgb_led; - }; - - buttons { - compatible = "gpio-keys"; - debounce-interval-ms = <100>; - user_button_0: button_0 { - label = "User button 0"; - gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&usb_serial { - status = "okay"; -}; -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&trng0 { - status = "okay"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - line-idle-low; - pinctrl-0 = <&spim3_ws2812_led>; - pinctrl-names = "default"; - - status_rgb_led: ws2812@0 { - compatible = "worldsemi,ws2812-spi"; - reg = <0>; - spi-max-frequency = ; - - chain-length = <1>; - color-mapping = , - , - ; - spi-one-frame = ; - spi-zero-frame = ; - }; -}; -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.yaml b/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.yaml deleted file mode 100644 index 82426e35fe6..00000000000 --- a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: m5stack_atoms3_lite -name: M5Stack AtomS3-Lite -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - counter - - watchdog - - entropy - - pwm - - pinmux - - nvs - - dma -testing: - ignore_tags: - - net - - bluetooth -vendor: m5stack diff --git a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite_defconfig b/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite_defconfig deleted file mode 100644 index 18468290e06..00000000000 --- a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_M5STACK_ATOMS3_LITE=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/m5stack_core2/Kconfig.board b/boards/xtensa/m5stack_core2/Kconfig.board deleted file mode 100644 index 9b48a15c24d..00000000000 --- a/boards/xtensa/m5stack_core2/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5Stack Core2 board configuration - -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_M5STACK_CORE2 - bool "M5Stack Core2 Development Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_D0WD_V3 -endchoice diff --git a/boards/xtensa/m5stack_core2/Kconfig.defconfig b/boards/xtensa/m5stack_core2/Kconfig.defconfig deleted file mode 100644 index 15dfc61483a..00000000000 --- a/boards/xtensa/m5stack_core2/Kconfig.defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# M5Stack Core2 board configuration -# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_M5STACK_CORE2 - -config BOARD - default "m5stack_core2" - depends on BOARD_M5STACK_CORE2 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 65536 if BT - default 4096 - -config KERNEL_MEM_POOL - default y - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -config REGULATOR_AXP192_INIT_PRIORITY - default 81 - -config GPIO_HOGS_INIT_PRIORITY - default 82 - -config INPUT_FT5336_INTERRUPT - default y if INPUT - -config INPUT - default y - -config LV_COLOR_16_SWAP - default y if LVGL - -# Increase initialization priority of MIPI DBI device, so that it initializes -# after the GPIO controller -if MIPI_DBI - -config MIPI_DBI_INIT_PRIORITY - default 82 - -endif # MIPI_DBI - -endif # BOARD_M5STACK_CORE2 diff --git a/boards/xtensa/m5stack_core2/doc/index.rst b/boards/xtensa/m5stack_core2/doc/index.rst deleted file mode 100644 index 11fd9b9826e..00000000000 --- a/boards/xtensa/m5stack_core2/doc/index.rst +++ /dev/null @@ -1,197 +0,0 @@ -.. _m5stack_core2: - -M5Stack Core2 -############# - -Overview -******** - -M5Stack Core2 is an ESP32-based development board from M5Stack. It is the successor for the Core module. - -M5Stack Core2 features the following integrated components: - -- ESP32-D0WDQ6-V3 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi) -- PSRAM 8MB -- Flash 16MB -- LCD IPS TFT 2", 320x240 px screen (ILI9342C) -- Touch screen (FT6336U) -- PMU AXP192 -- Audio NS4168 amplifier (1W-092 speaker) -- Vibration motor -- RTC BM8563 -- USB CP2104 -- SD-Card slot -- IMO 6-axis IMU MPU6886 -- MIC SPM1423 -- Battery 390mAh 3,7V - -.. figure:: img/m5stack_core2.webp - :align: center - :alt: M5Stack-Core2 - :width: 400 px - - M5Stack-Core2 module - -Functional Description -********************** - -The following table below describes the key components, interfaces, and controls -of the M5Stack Core2 board. - -.. _M5Core2 Schematic: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/schematic/Core/CORE2_V1.0_SCH.pdf -.. _MPU-ESP32: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/esp32_datasheet_en_v3.9.pdf -.. _TOUCH-FT6336U: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/Ft6336GU_Firmware%20外部寄存器_20151112-%20EN.xlsx -.. _SND-NS4168: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/NS4168_CN_datasheet.pdf -.. _MPU-6886: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/MPU-6886-000193%2Bv1.1_GHIC_en.pdf -.. _LCD-ILI9342C: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/ILI9342C-ILITEK.pdf -.. _SPM-1423: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SPM1423HM4H-B_datasheet_en.pdf -.. _RTC-BM8563: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/BM8563_V1.1_cn.pdf -.. _SY7088: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SY7088-Silergy.pdf -.. _PMU-AXP192: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/AXP192_datasheet_en.pdf -.. _VIB-1072_RFN01: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/1027RFN01-33d.pdf - -+------------------+--------------------------------------------------------------------------+------------+ -| Key Component | Description | Status | -+==================+==========================================================================+============+ -|| ESP32-D0WDQ6-V2 || This `MPU-ESP32`_ module provides complete Wi-Fi and Bluetooth || supported | -|| module || functionalities and integrates a 16-MB SPI flash. || | -+------------------+--------------------------------------------------------------------------+------------+ -|| 32.768 kHz RTC || External precision 32.768 kHz crystal oscillator serves as a clock with || supported | -|| || low-power consumption while the chip is in Deep-sleep mode. || | -+------------------+--------------------------------------------------------------------------+------------+ -| Status LED | One user LED connected to the GPIO pin. | supported | -+------------------+--------------------------------------------------------------------------+------------+ -|| USB Port || USB interface. Power supply for the board as well as the || supported | -|| || communication interface between a computer and the board. || | -|| || Contains: TypeC x 1, GROVE(I2C+I/O+UART) x 1 || | -+------------------+--------------------------------------------------------------------------+------------+ -| Reset button | Reset button | supported | -+------------------+--------------------------------------------------------------------------+------------+ -| Power Switch | Power on/off button. | supported | -+------------------+--------------------------------------------------------------------------+------------+ -|| LCD screen || Built-in LCD TFT display \(`LCD-ILI9342C`_, 2", 320x240 px\) || supported | -|| || controlled via SPI interface || | -+------------------+--------------------------------------------------------------------------+------------+ -| SD-Card slot | SD-Card connection via SPI-mode. | supported | -+------------------+--------------------------------------------------------------------------+------------+ -|| 6-axis IMU || The `MPU-6886`_ is a 6-axis motion tracker (6DOF IMU) device that || todo | -|| MPU6886 || combines a 3-axis gyroscope and a 3-axis accelerometer. || | -|| || For details please refer to :ref:`m5stack_core2_ext` || | -+------------------+--------------------------------------------------------------------------+------------+ -|| Built-in || The `SPM-1423`_ I2S driven microphone. || todo | -|| microphone || || | -+------------------+--------------------------------------------------------------------------+------------+ -| Built-in speaker | 1W speaker for audio output via I2S interface. | todo | -+------------------+--------------------------------------------------------------------------+------------+ - -Supported Features -================== - -The Zephyr m5stack_core2 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - - -Start Application Development -***************************** - -Before powering up your M5Stack Core2, please make sure that the board is in good -condition with no obvious signs of damage. - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_core2 - :goals: build - -The usual ``flash`` target will work with the ``m5stack_core2`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_core2 - :goals: flash - -The baud rate of 921600bps is set by default. If experiencing issues when flashing, -try using different values by using ``--esp-baud-rate `` option during -``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). - -You can also open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! m5stack_core2 - -Debugging ---------- - -M5Stack Core2 debugging is not supported due to pinout limitations. - -Related Documents -***************** - -- `M5StickC PLUS schematic `_ (WEBP) -- `ESP32-PICO-D4 Datasheet `_ (PDF) -- `M5StickC PLUS docs `_ -- `ESP32 Datasheet `_ (PDF) -- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stack_core2/m5stack_core2.dts b/boards/xtensa/m5stack_core2/m5stack_core2.dts deleted file mode 100644 index 17cbe3fe638..00000000000 --- a/boards/xtensa/m5stack_core2/m5stack_core2.dts +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) 2023 Martin Kiepfer - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "m5stack_core2-pinctrl.dtsi" -#include "grove_connectors.dtsi" -#include "m5stack_mbus_connectors.dtsi" -#include -#include - -/ { - model = "M5Stack Core2"; - compatible = "m5stack,core2"; - - aliases { - pwr-led = &pwr_led; - uart-0 = &uart0; - i2c-0 = &i2c0; - watchdog0 = &wdt0; - rtc = &pfc8563_rtc; - led0 = &led_pwr; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,display = &ili9342c; - zephyr,code-partition = &slot0_partition; - zephyr,rtc = &pfc8563_rtc; - }; - - leds { - compatible = "gpio-leds"; - led_pwr: led_pwr { - gpios = <&axp192_gpio 1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; - label = "Power LED"; - }; - }; - - lvgl_pointer { - compatible = "zephyr,lvgl-pointer-input"; - input = <&ft5336_touch>; - swap-xy; - }; - - mipi_dbi { - compatible = "zephyr,mipi-dbi-spi"; - dc-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - reset-gpios = <&axp192_gpio 4 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; - spi-dev = <&spi3>; - write-only; - #address-cells = <1>; - #size-cells = <0>; - - ili9342c: ili9342c@0 { - compatible = "ilitek,ili9342c"; - mipi-max-frequency = <30000000>; - reg = <0>; - vin-supply = <&lcd_bg>; - pixel-format = ; - display-inversion; - width = <320>; - height = <240>; - rotation = <0>; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&psram0 { - reg = <0x3f800000 DT_SIZE_M(8)>; - status = "disabled"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_tx_gpio1 &uart0_rx_gpio3>; - pinctrl-names = "default"; -}; - -&uart1 { - status = "disabled"; - current-speed = <115200>; - pinctrl-0 = <&uart1_rx_gpio33 &uart1_tx_gpio32>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - scl-timeout-us = <0>; - pinctrl-names = "default"; - - pfc8563_rtc: pfc8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - status = "okay"; - }; - - axp192_pmic: axp192@34 { - compatible = "x-powers,axp192"; - reg = <0x34>; - status = "okay"; - - axp192_regulator: axp192_regulator { - compatible = "x-powers,axp192-regulator"; - status = "okay"; - - vdd_mcu: DCDC1 { - regulator-init-microvolt = <3350000>; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; - regulator-initial-mode = ; - regulator-boot-on; - regulator-always-on; - }; - - lcd_bg: DCDC3 { - regulator-init-microvolt = <2800000>; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - v_peri: LDO2 { - regulator-init-microvolt = <3300000>; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - vib_motor: LDO3 { - regulator-init-microvolt = <2800000>; - }; - }; - - axp192_gpio: axp192_gpio { - compatible = "x-powers,axp192-gpio"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <5>; - status = "okay"; - - pwr_led: axp192_gpio1 { - gpio-hog; - gpios = <1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; - output-high; - line-name = "pwr-led"; - }; - - bus_pwr_en: axp192_gpio0 { - gpio-hog; - gpios = <0 0>; - input; - }; - }; - }; - - ft5336_touch: ft5336@38 { - compatible = "focaltech,ft5336"; - reg = <0x38>; - int-gpios = <&gpio1 7 0>; - }; -}; - -&i2c1 { - status = "disabled"; - clock-frequency = ; - sda-gpios = <&gpio1 0 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio1 1 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; - dma-enabled; - clock-frequency = <20000000>; - cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>, - <&gpio0 4 GPIO_ACTIVE_LOW>; - - sdhc0: sdhc@1 { - compatible = "zephyr,sdhc-spi-slot"; - reg = <1>; - status = "okay"; - spi-max-frequency = <20000000>; - mmc { - compatible = "zephyr,sdmmc-disk"; - status = "okay"; - }; - - }; -}; - - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - reg = <0 DT_SIZE_M(16)>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - /* 14MB storage */ - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00db0000>; - }; - }; -}; diff --git a/boards/xtensa/m5stack_core2/m5stack_core2.yaml b/boards/xtensa/m5stack_core2/m5stack_core2.yaml deleted file mode 100644 index 78b361e8834..00000000000 --- a/boards/xtensa/m5stack_core2/m5stack_core2.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: m5stack_core2 -name: M5Stack Core2 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - spi - - watchdog - - regulator - - uart - - pinmux - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: m5stack diff --git a/boards/xtensa/m5stack_core2/m5stack_core2_defconfig b/boards/xtensa/m5stack_core2/m5stack_core2_defconfig deleted file mode 100644 index 10fde73b477..00000000000 --- a/boards/xtensa/m5stack_core2/m5stack_core2_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_M5STACK_CORE2=y - -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_ESP_HEAP_MEM_POOL_REGION_1_SIZE=0 - -CONFIG_GPIO=y - -CONFIG_REGULATOR=y - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -# for debugging -CONFIG_SHELL=y diff --git a/boards/xtensa/m5stack_stamps3/Kconfig.board b/boards/xtensa/m5stack_stamps3/Kconfig.board deleted file mode 100644 index 1f22500830e..00000000000 --- a/boards/xtensa/m5stack_stamps3/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5Stack StampS3 board configuration - -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_M5STACK_STAMPS3 - bool "M5Stack StampS3 Development Board" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_FN8 -endchoice diff --git a/boards/xtensa/m5stack_stamps3/Kconfig.defconfig b/boards/xtensa/m5stack_stamps3/Kconfig.defconfig deleted file mode 100644 index f451db3e231..00000000000 --- a/boards/xtensa/m5stack_stamps3/Kconfig.defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# M5Stack StampS3 board configuration -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_M5STACK_STAMPS3 - -config BOARD - default "m5stack_stamps3" - depends on BOARD_M5STACK_STAMPS3 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 98304 if WIFI - default 65536 if BT - default 4096 - -config KERNEL_MEM_POOL - default y - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -endif # BOARD_M5STACK_STAMPS3 diff --git a/boards/xtensa/m5stack_stamps3/doc/index.rst b/boards/xtensa/m5stack_stamps3/doc/index.rst deleted file mode 100644 index 75c660de803..00000000000 --- a/boards/xtensa/m5stack_stamps3/doc/index.rst +++ /dev/null @@ -1,199 +0,0 @@ -.. _m5stack_stamps3: - -M5Stack StampS3 -############### - -Overview -******** - -M5Stack StampS3 is an ESP32-based development board from M5Stack. -It features the following integrated components: - -- ESP32-S3FN8 chip (240MHz dual core) -- 512KB SRAM -- 384KB ROM -- 8MB Flash -- Wi-Fi -- Bluetooth -- User-Button - -.. figure:: img/m5stack_stamps3.webp - :align: center - :alt: M5Stack StampS3 - :width: 400 px - - M5Stack StampS3 module - -Functional Description -********************** - -The following table below describes the key components, interfaces, and controls -of the M5Stack StampS3 module. - -+---------------+-----------------------------------------------------------------+-----------+ -| Key Component | Description | Status | -+===============+=================================================================+===========+ -| ESP32-S3FN8 | This MPU-ESP32S3 module provides complete Wi-Fi and Bluetooth | supported | -| module | functionalities and integrates a 8MB flash. | | -+---------------+-----------------------------------------------------------------+-----------+ -| Status LED | One user LED connected via :dtcompatible:`worldsemi,ws2812-spi` | supported | -| | interface (``led-strip``). | | -+---------------+-----------------------------------------------------------------+-----------+ -| USB Port | USB interface. Power supply for the board as well as the | supported | -| | communication interface between a computer and the board. | | -+---------------+-----------------------------------------------------------------+-----------+ -| User button | User button (``sw0``) | supported | -+---------------+-----------------------------------------------------------------+-----------+ - -Main connector header -===================== - -The Zephyr m5stack_stamps3 board can be used on various applications. It -therefore publishes a header definition to be used in different shields: -:dtcompatible:`m5stack,stamps3-header`. - -.. figure:: img/m5stack_stamps3_header.webp - :align: center - :alt: M5Stack StampS3 Header - :width: 400 px - - M5Stack StampS3 connector header - -Following interfaces are being exported for this header: - -- ``m5stack_stamps3_clkout0``: PWM output with 2 channels (0 and 2). -- ``m5stack_stamps3_spilcd``: SPI interface for interfacing LCDs. Consists of a - CLK, MOSI and CS signal. -- ``m5stack_stamps3_i2c0`` and ``m5stack_stamps3_i2c1``: I2C interfaces (SDA, SCL). -- ``m5stack_stamps3_uart0``: UART interface (RXD, TXD). -- ``m5stack_stamps3_header``: All GPIOs are of course accessible via main header - definition. - -+-----+-----------------------------------------+-----+---------------------------------+ -| Pin | Functions | Pin | Functions | -+=====+=========================================+=====+=================================+ -| 1 | | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 2 | | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 3 | ``m5stack_stamps3_clkout0`` - Channel 0 | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 4 | | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 5 | ``m5stack_stamps3_spilcd`` - MOSI | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 6 | ``m5stack_stamps3_spilcd`` - CLK | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 7 | ``m5stack_stamps3_spilcd`` - CS | 28 | **3V3** | -+-----+-----------------------------------------+-----+---------------------------------+ -| 8 | | 27 | ``m5stack_stamps3_uart0`` - TXD | -+-----+-----------------------------------------+-----+---------------------------------+ -| 9 | ``m5stack_stamps3_clkout0`` - Channel 2 | 26 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 10 | | 25 | ``m5stack_stamps3_uart0`` - RXD | -+-----+-----------------------------------------+-----+---------------------------------+ -| 11 | **GND** | 24 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 12 | ``m5stack_stamps3_i2c1`` - SDA | 23 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 13 | **5V** | 22 | **EN** | -+-----+-----------------------------------------+-----+---------------------------------+ -| 14 | ``m5stack_stamps3_i2c1`` - SCL | 21 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 15 | ``m5stack_stamps3_i2c0`` - SDA | 20 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 16 | | 19 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 17 | ``m5stack_stamps3_i2c0`` - SCL | 18 | **GND** | -+-----+-----------------------------------------+-----+---------------------------------+ - -Power supply -============ - -M5Stack StampS3 requires a single 5V input power supply. The module internally -features a DCDC (MUN3CAD01-SC) to generate the 3.3V needed for the MCU. - -The **EN** signal (Pin 22) is an active low signal to enable the **3V3** power -supply. If this pin is pulled low this main 3.3V power supply for the MCU will be -deactivated. It is internally equipped with a pull-up and can hence be left open -if unused. - -Start Application Development -***************************** - -Before powering up your M5Stack StampS3, please make sure that the board is in good -condition with no obvious signs of damage. - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_stamps3 - :goals: build - -The usual ``flash`` target will work with the ``m5stack_stamps3`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_stamps3 - :goals: flash - -The baud rate of 921600bps is set by default. If experiencing issues when flashing, -try using different values by using ``--esp-baud-rate `` option during -``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). - -You can also open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! m5stack_stamps3 - -Debugging ---------- - -M5Stack StampS3 exports a JTAG-interface via Pins 19 (MTCK), 21 (MTDO), 23 -(MTDI), 25 (MTMS). - -.. note:: - - Please note that additional JTAG equipment is needed to utilize JTAG. Refer to - the ESP32S3 datasheet and the M5Stack StampS3 documentation for details. - -Related Documents -***************** - -- `M5Stack StampS3 schematic `_ -- `M5Stack StampS3 `_ -- `ESP32 Datasheet `_ (PDF) -- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stack_stamps3/m5stack_stamps3.dts b/boards/xtensa/m5stack_stamps3/m5stack_stamps3.dts deleted file mode 100644 index b4087e31bd9..00000000000 --- a/boards/xtensa/m5stack_stamps3/m5stack_stamps3.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2023 Martin Kiepfer - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "m5stack_stamps3-pinctrl.dtsi" -#include "m5stack_stamps3_connectors.dtsi" -#include -#include -#include -#include - -/ { - model = "M5Stack StampS3"; - compatible = "m5stack,stamps3"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - sw0 = &user_button_0; - watchdog0 = &wdt0; - //pwm-0 = &ledc0; - i2c-0 = &i2c0; - led-strip = &status_rgb_led; - }; - - gpio_keys { - compatible = "gpio-keys"; - - /* This is the button that's underneath the LCD display */ - user_button_0: button_0 { - label = "User button 0"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&trng0 { - status = "okay"; -}; - -&mcpwm0 { - status = "okay"; - pinctrl-0 = <&mcpwm0_default>; - pinctrl-names = "default"; - prescale = <255>; - prescale-timer0 = <100>; - prescale-timer1 = <100>; -}; - -&ledc0 { - pinctrl-0 = <&ledc0_default>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - channel0@0 { - reg = <0x0>; - timer = <0>; - }; - channel0@1 { - reg = <0x1>; - timer = <0>; - }; -}; - - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - line-idle-low; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; - - status_rgb_led: ws2812@0 { - compatible = "worldsemi,ws2812-spi"; - reg = <0x0>; - spi-max-frequency = ; - - chain-length = <1>; - color-mapping = , - , - ; - spi-one-frame = ; - spi-zero-frame = ; - reset-delay = <250>; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/m5stack_stamps3/m5stack_stamps3.yaml b/boards/xtensa/m5stack_stamps3/m5stack_stamps3.yaml deleted file mode 100644 index f5275cabe05..00000000000 --- a/boards/xtensa/m5stack_stamps3/m5stack_stamps3.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: m5stack_stamps3 -name: M5Stack StampS3 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - spi - - watchdog - - uart - - pwm - - pinmux - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: m5stack diff --git a/boards/xtensa/m5stack_stamps3/m5stack_stamps3_defconfig b/boards/xtensa/m5stack_stamps3/m5stack_stamps3_defconfig deleted file mode 100644 index 34f489623bc..00000000000 --- a/boards/xtensa/m5stack_stamps3/m5stack_stamps3_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_M5STACK_STAMPS3=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_GPIO=y - -CONFIG_CONSOLE=y -CONFIG_PWM=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/m5stickc_plus/Kconfig.board b/boards/xtensa/m5stickc_plus/Kconfig.board deleted file mode 100644 index 91e31bc9595..00000000000 --- a/boards/xtensa/m5stickc_plus/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5StickC PLUS board configuration - -# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_M5STICKC_PLUS - bool "M5StickC PLUS Development Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_PICO_D4 -endchoice diff --git a/boards/xtensa/m5stickc_plus/Kconfig.defconfig b/boards/xtensa/m5stickc_plus/Kconfig.defconfig deleted file mode 100644 index a9e73202781..00000000000 --- a/boards/xtensa/m5stickc_plus/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# M5StickC PLUS board configuration - -# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "m5stickc_plus" - depends on BOARD_M5STICKC_PLUS - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/m5stickc_plus/doc/index.rst b/boards/xtensa/m5stickc_plus/doc/index.rst deleted file mode 100644 index 1b042f4f30f..00000000000 --- a/boards/xtensa/m5stickc_plus/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ -.. _m5stickc_plus: - -M5StickC PLUS -############# - -Overview -******** - -M5StickC PLUS, one of the core devices in M5Stacks product series, is an ESP32-based development board. - -M5StickC PLUS features the following integrated components: - -- ESP32-PICO-D4 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi) -- ST7789v2, LCD TFT 1.14", 135x240 px screen -- IMU MPU-6886 -- SPM-1423 microphone -- RTC BM8563 -- PMU AXP192 -- 120 mAh 3,7 V battery - -Some of the ESP32 I/O pins are broken out to the board's pin headers for easy access. - -Functional Description -********************** - -The following table below describes the key components, interfaces, and controls -of the M5StickC PLUS board. - -.. _ST7789v2: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/ST7789V.pdf -.. _MPU-6886: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/MPU-6886-000193%2Bv1.1_GHIC_en.pdf -.. _ESP32-PICO-D4: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/esp32-pico-d4_datasheet_en.pdf -.. _SPM-1423: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SPM1423HM4H-B_datasheet_en.pdf - -+------------------+-------------------------------------------------------------------------+ -| Key Component | Description | -+==================+=========================================================================+ -| 32.768 kHz RTC | External precision 32.768 kHz crystal oscillator serves as a clock with | -| | low-power consumption while the chip is in Deep-sleep mode. | -+------------------+-------------------------------------------------------------------------+ -| ESP32-PICO-D4 | This `ESP32-PICO-D4`_ module provides complete Wi-Fi and Bluetooth | -| module | functionalities and integrates a 4-MB SPI flash. | -+------------------+-------------------------------------------------------------------------+ -| Diagnostic LED | One user LED connected to the GPIO pin. | -+------------------+-------------------------------------------------------------------------+ -| USB Port | USB interface. Power supply for the board as well as the | -| | communication interface between a computer and the board. | -| | Contains: TypeC x 1, GROVE(I2C+I/O+UART) x 1 | -+------------------+-------------------------------------------------------------------------+ -| Power Switch | Power on/off button. | -+------------------+-------------------------------------------------------------------------+ -| A/B user buttons | Two push buttons intended for any user use. | -+------------------+-------------------------------------------------------------------------+ -| LCD screen | Built-in LCD TFT display \(`ST7789v2`_, 1.14", 135x240 px\) controlled | -| | by the SPI interface | -+------------------+-------------------------------------------------------------------------+ -| MPU-6886 | The `MPU-6886`_ is a 6-axis MotionTracking device that combines a | -| | 3-axis gyroscope and a 3-axis accelerometer. | -+------------------+-------------------------------------------------------------------------+ -| Built-in | The `SPM-1423`_ I2S driven microphone. | -| microphone | | -+------------------+-------------------------------------------------------------------------+ - - -Start Application Development -***************************** - -Before powering up your M5StickC PLUS, please make sure that the board is in good -condition with no obvious signs of damage. - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: m5stickc_plus - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stickc_plus - :goals: build - -The usual ``flash`` target will work with the ``m5stickc_plus`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stickc_plus - :goals: flash - -The default baud rate for the M5StickC PLUS is set to 1500000bps. If experiencing issues when flashing, -try using different values by using ``--esp-baud-rate `` option during -``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). - -You can also open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! m5stickc_plus - -Debugging -********* - -M5StickC PLUS debugging is not supported due to pinout limitations. - -Related Documents -***************** - -- `M5StickC PLUS schematic `_ (WEBP) -- `ESP32-PICO-D4 Datasheet `_ (PDF) -- `M5StickC PLUS docs `_ -- `ESP32 Datasheet `_ (PDF) -- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stickc_plus/m5stickc_plus.dts b/boards/xtensa/m5stickc_plus/m5stickc_plus.dts deleted file mode 100644 index 6737973adae..00000000000 --- a/boards/xtensa/m5stickc_plus/m5stickc_plus.dts +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "m5stickc_plus-pinctrl.dtsi" -#include - -/ { - model = "M5StickC Plus"; - compatible = "m5stack,m5stickc-plus"; - - aliases { - led0 = &red_led; - sw0 = &user_button_0; - sw1 = &user_button_1; - uart-0 = &uart0; - i2c-0 = &i2c0; - watchdog0 = &wdt0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - - red_led: led_0 { - gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - label = "Red - LED0"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user_button_0: button_0 { - label = "User button 0"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_1: button_1 { - label = "User button 1"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_tx_gpio1 &uart0_rx_gpio3>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -/* IMU MPU-6886, RTC BM8563, PMU AXP192 */ -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_sda_gpio21 &i2c0_scl_gpio22>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_miso_gpio12 &spim2_mosi_gpio11 - &spim2_sclk_gpio14 &spim2_csel_gpio16>; - pinctrl-names = "default"; -}; - -/* LCD TFT 1.14", 135x240 px, ST7789v2 */ -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_miso_gpio25 &spim3_mosi_gpio15 - &spim3_sclk_gpio13 &spim3_csel_gpio5>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/m5stickc_plus/m5stickc_plus.yaml b/boards/xtensa/m5stickc_plus/m5stickc_plus.yaml deleted file mode 100644 index 821770c2be4..00000000000 --- a/boards/xtensa/m5stickc_plus/m5stickc_plus.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: m5stickc_plus -name: M5StickC PLUS -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - spi - - watchdog - - uart - - pinmux - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: m5stack diff --git a/boards/xtensa/m5stickc_plus/m5stickc_plus_defconfig b/boards/xtensa/m5stickc_plus/m5stickc_plus_defconfig deleted file mode 100644 index cc30c956baf..00000000000 --- a/boards/xtensa/m5stickc_plus/m5stickc_plus_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_M5STICKC_PLUS=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y -CONFIG_I2C=y diff --git a/boards/xtensa/nxp_adsp_imx8/Kconfig.board b/boards/xtensa/nxp_adsp_imx8/Kconfig.board deleted file mode 100644 index 4bb4f564040..00000000000 --- a/boards/xtensa/nxp_adsp_imx8/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NXP_ADSP_IMX8 - bool "NXP ADSP i.MX8" - depends on SOC_SERIES_NXP_IMX8 - select SOC_PART_NUMBER_MIMX8QM6AVUFF diff --git a/boards/xtensa/nxp_adsp_imx8/Kconfig.defconfig b/boards/xtensa/nxp_adsp_imx8/Kconfig.defconfig deleted file mode 100644 index 04aa0aa6ed3..00000000000 --- a/boards/xtensa/nxp_adsp_imx8/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NXP_ADSP_IMX8 - -config BOARD - default "nxp_adsp_imx8" - -endif # BOARD_NXP_ADSP_IMX8 diff --git a/boards/xtensa/nxp_adsp_imx8/board.cmake b/boards/xtensa/nxp_adsp_imx8/board.cmake deleted file mode 100644 index 7ae22465082..00000000000 --- a/boards/xtensa/nxp_adsp_imx8/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(misc-flasher) -board_finalize_runner_args(misc-flasher) - -board_set_rimage_target(imx8) diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.dts b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.dts deleted file mode 100644 index a17690109ec..00000000000 --- a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2021 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "nxp_adsp_imx8-pinctrl.dtsi" - -/ { - model = "nxp_adsp_imx8"; - compatible = "nxp"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - }; -}; - -&lpuart2 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&lpuart2_default>; - pinctrl-names = "default"; -}; diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.yaml b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.yaml deleted file mode 100644 index b2ab9b227a9..00000000000 --- a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: nxp_adsp_imx8 -name: i.MX8 DSP -type: mcu -arch: xtensa -toolchain: - - zephyr -testing: - only_tags: - - kernel - - sof -vendor: nxp diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8_defconfig b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8_defconfig deleted file mode 100644 index a16d8be5e2e..00000000000 --- a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=3072 - -# board/soc-related configurations -CONFIG_SOC_SERIES_NXP_IMX8=y -CONFIG_SOC_MIMX8QM_ADSP=y -CONFIG_BOARD_NXP_ADSP_IMX8=y - -CONFIG_LOG=y - -# TODO: maybe move this to SOF? -CONFIG_DYNAMIC_INTERRUPTS=y -CONFIG_BUILD_OUTPUT_BIN=n - -# clock-related configurations -CONFIG_CLOCK_CONTROL=y - -# serial-related configurations -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/xtensa/nxp_adsp_imx8m/Kconfig.board b/boards/xtensa/nxp_adsp_imx8m/Kconfig.board deleted file mode 100644 index b84a08cc12f..00000000000 --- a/boards/xtensa/nxp_adsp_imx8m/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NXP_ADSP_IMX8M - bool "NXP i.MX8M Plus EVK Audio DSP" - depends on SOC_SERIES_NXP_IMX8M - select SOC_PART_NUMBER_MIMX8ML8DVNLZ - select SOC_PART_NUMBER_MIMX8ML8CVNKZ diff --git a/boards/xtensa/nxp_adsp_imx8m/Kconfig.defconfig b/boards/xtensa/nxp_adsp_imx8m/Kconfig.defconfig deleted file mode 100644 index 344449dd744..00000000000 --- a/boards/xtensa/nxp_adsp_imx8m/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021, 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NXP_ADSP_IMX8M - -config BOARD - default "nxp_adsp_imx8m" - -endif # BOARD_NXP_ADSP_IMX8M diff --git a/boards/xtensa/nxp_adsp_imx8m/board.cmake b/boards/xtensa/nxp_adsp_imx8m/board.cmake deleted file mode 100644 index 4fb52dc2d29..00000000000 --- a/boards/xtensa/nxp_adsp_imx8m/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(misc-flasher) -board_finalize_runner_args(misc-flasher) - -board_set_rimage_target(imx8m) diff --git a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.dts b/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.dts deleted file mode 100644 index 6a0d7508deb..00000000000 --- a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.dts +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2021, 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include - -/ { - model = "nxp_adsp_imx8m"; - compatible = "nxp"; - - chosen { - zephyr,sram = &sram0; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&pinctrl { - uart4_default: uart4_default { - group0 { - pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, - <&iomuxc_uart4_txd_uart_tx_uart4_tx>; - bias-pull-up; - slew-rate = "slow"; - drive-strength = "x1"; - }; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; diff --git a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.yaml b/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.yaml deleted file mode 100644 index ef0bbdfe0ff..00000000000 --- a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: nxp_adsp_imx8m -name: NXP i.MX8M Plus EVK Audio DSP -type: mcu -arch: xtensa -toolchain: - - xcc - - xt-clang - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - mcumgr -vendor: nxp diff --git a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m_defconfig b/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m_defconfig deleted file mode 100644 index 72ccd09f55a..00000000000 --- a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NXP_IMX8M=y -CONFIG_SOC_MIMX8M_ADSP=y -CONFIG_BOARD_NXP_ADSP_IMX8M=y - -# size of stack for initialization and main thread -CONFIG_MAIN_STACK_SIZE=3072 - -# enable logger -CONFIG_LOG=y - -# no need for a "raw" binary zephyr/zephyr.bin in the build directory -CONFIG_BUILD_OUTPUT_BIN=n - -# enable uart driver -CONFIG_SERIAL=y - -# clock configuration -CONFIG_CLOCK_CONTROL=y - -# console (remote proc console by default) -CONFIG_CONSOLE=y - -# uart console (overrides remote proc console) -CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.board b/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.board deleted file mode 100644 index d9a1ff65953..00000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NXP_ADSP_IMX8ULP - bool "NXP ADSP i.MX8ULP" diff --git a/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.defconfig b/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.defconfig deleted file mode 100644 index 431515d5961..00000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NXP_ADSP_IMX8ULP - -config BOARD - default "nxp_adsp_imx8ulp" - -endif # BOARD_NXP_ADSP_IMX8ULP diff --git a/boards/xtensa/nxp_adsp_imx8ulp/board.cmake b/boards/xtensa/nxp_adsp_imx8ulp/board.cmake deleted file mode 100644 index e05fbc891e5..00000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(misc-flasher) -board_finalize_runner_args(misc-flasher) - -board_set_rimage_target(imx8ulp) diff --git a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.dts b/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.dts deleted file mode 100644 index d584097cb03..00000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - model = "nxp_adsp_imx8ulp"; - compatible = "nxp"; - - chosen { - zephyr,sram = &sram0; - }; -}; diff --git a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.yaml b/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.yaml deleted file mode 100644 index e71105631da..00000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.yaml +++ /dev/null @@ -1,10 +0,0 @@ -identifier: nxp_adsp_imx8ulp -name: i.MX8ULP DSP -type: mcu -arch: xtensa -toolchain: - - zephyr -testing: - only_tags: - - kernel - - sof diff --git a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp_defconfig b/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp_defconfig deleted file mode 100644 index cc1911c615c..00000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NXP_IMX8ULP=y -CONFIG_SOC_NXP_IMX8ULP=y -CONFIG_BOARD_NXP_ADSP_IMX8ULP=y - -CONFIG_BUILD_OUTPUT_BIN=n - -CONFIG_DYNAMIC_INTERRUPTS=y - -CONFIG_LOG=y diff --git a/boards/xtensa/nxp_adsp_imx8x/Kconfig.board b/boards/xtensa/nxp_adsp_imx8x/Kconfig.board deleted file mode 100644 index 7d5336ce7a7..00000000000 --- a/boards/xtensa/nxp_adsp_imx8x/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NXP_ADSP_IMX8X - bool "NXP ADSP i.MX8X" - depends on SOC_SERIES_NXP_IMX8 - select SOC_PART_NUMBER_MIMX8QX6AVLFZ diff --git a/boards/xtensa/nxp_adsp_imx8x/Kconfig.defconfig b/boards/xtensa/nxp_adsp_imx8x/Kconfig.defconfig deleted file mode 100644 index a985696286a..00000000000 --- a/boards/xtensa/nxp_adsp_imx8x/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NXP_ADSP_IMX8X - -config BOARD - default "nxp_adsp_imx8x" - -endif # BOARD_NXP_ADSP_IMX8X diff --git a/boards/xtensa/nxp_adsp_imx8x/board.cmake b/boards/xtensa/nxp_adsp_imx8x/board.cmake deleted file mode 100644 index 7ae22465082..00000000000 --- a/boards/xtensa/nxp_adsp_imx8x/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(misc-flasher) -board_finalize_runner_args(misc-flasher) - -board_set_rimage_target(imx8) diff --git a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.dts b/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.dts deleted file mode 100644 index 5aa0e59ebdd..00000000000 --- a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2021 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "nxp_adsp_imx8x-pinctrl.dtsi" - -/ { - model = "nxp_adsp_imx8x"; - compatible = "nxp"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - }; -}; - -&lpuart2 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&lpuart2_default>; - pinctrl-names = "default"; -}; diff --git a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.yaml b/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.yaml deleted file mode 100644 index a343b8843c8..00000000000 --- a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: nxp_adsp_imx8x -name: i.MX8X DSP -type: mcu -arch: xtensa -toolchain: - - zephyr -testing: - only_tags: - - kernel - - sof -vendor: nxp diff --git a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x_defconfig b/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x_defconfig deleted file mode 100644 index 0635e78adf8..00000000000 --- a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=3072 - -# board/soc-related configurations -CONFIG_SOC_SERIES_NXP_IMX8=y -CONFIG_SOC_MIMX8QXP_ADSP=y -CONFIG_BOARD_NXP_ADSP_IMX8X=y - -CONFIG_LOG=y - -# TODO: maybe move this to SOF? -CONFIG_DYNAMIC_INTERRUPTS=y -CONFIG_BUILD_OUTPUT_BIN=n - -# clock-related configurations -CONFIG_CLOCK_CONTROL=y - -# serial-related configurations -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/xtensa/nxp_adsp_rt595/Kconfig b/boards/xtensa/nxp_adsp_rt595/Kconfig deleted file mode 100644 index 3c787188a9b..00000000000 --- a/boards/xtensa/nxp_adsp_rt595/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -DT_ADSP_RESET_MEM := $(dt_nodelabel_path,adsp_reset) -DT_ADSP_DATA_MEM := $(dt_nodelabel_path,adsp_data) -DT_ADSP_TEXT_MEM := $(dt_nodelabel_path,adsp_text) - -if BOARD_NXP_ADSP_RT595 - -config RT595_ADSP_STACK_SIZE - hex "Boot time stack size" - default 0x1000 - help - Stack space is reserved at the end of the RT595_ADSP_DATA_MEM - region, starting at RT595_ADSP_DATA_MEM_ADDR - RT595_ADSP_STACK_SIZE - -config RT595_ADSP_RESET_MEM_ADDR - hex - default $(dt_node_reg_addr_hex,$(DT_ADSP_RESET_MEM)) - -config RT595_ADSP_RESET_MEM_SIZE - hex - default $(dt_node_reg_size_hex,$(DT_ADSP_RESET_MEM)) - -config RT595_ADSP_DATA_MEM_ADDR - hex - default $(dt_node_reg_addr_hex,$(DT_ADSP_DATA_MEM)) - -config RT595_ADSP_DATA_MEM_SIZE - hex - default $(dt_node_reg_size_hex,$(DT_ADSP_DATA_MEM)) - -config RT595_ADSP_TEXT_MEM_ADDR - hex - default $(dt_node_reg_addr_hex,$(DT_ADSP_TEXT_MEM)) - -config RT595_ADSP_TEXT_MEM_SIZE - hex - default $(dt_node_reg_size_hex,$(DT_ADSP_TEXT_MEM)) - -endif # BOARD_NXP_ADSP_RT595 diff --git a/boards/xtensa/nxp_adsp_rt595/Kconfig.board b/boards/xtensa/nxp_adsp_rt595/Kconfig.board deleted file mode 100644 index a88eb58638f..00000000000 --- a/boards/xtensa/nxp_adsp_rt595/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NXP_ADSP_RT595 - bool "NXP ADSP RT595" - depends on SOC_SERIES_NXP_RT5XX diff --git a/boards/xtensa/nxp_adsp_rt595/Kconfig.defconfig b/boards/xtensa/nxp_adsp_rt595/Kconfig.defconfig deleted file mode 100644 index 7ffe782d28b..00000000000 --- a/boards/xtensa/nxp_adsp_rt595/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NXP_ADSP_RT595 - -config BOARD - default "nxp_adsp_rt595" - -endif # BOARD_NXP_ADSP_RT595 diff --git a/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595.yaml b/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595.yaml deleted file mode 100644 index 09f61405d94..00000000000 --- a/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595.yaml +++ /dev/null @@ -1,10 +0,0 @@ -identifier: nxp_adsp_rt595 -name: i.MXRT595 DSP -type: mcu -arch: xtensa -toolchain: - - zephyr -testing: - only_tags: - - kernel -vendor: nxp diff --git a/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595_defconfig b/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595_defconfig deleted file mode 100644 index 0e80f8a41a6..00000000000 --- a/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_SOC_SERIES_NXP_RT5XX=y -CONFIG_SOC_NXP_RT595=y -CONFIG_BOARD_NXP_ADSP_RT595=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY=y diff --git a/boards/xtensa/odroid_go/Kconfig.board b/boards/xtensa/odroid_go/Kconfig.board deleted file mode 100644 index f815a4e7e88..00000000000 --- a/boards/xtensa/odroid_go/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ODROID-GO Game Kit configuration - -# Copyright (c) 2019 Yannis Damigos -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ODROID_GO - bool "ODROID-GO Game Kit" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROVER_E_N16R2 -endchoice diff --git a/boards/xtensa/odroid_go/Kconfig.defconfig b/boards/xtensa/odroid_go/Kconfig.defconfig deleted file mode 100644 index 1827d83a041..00000000000 --- a/boards/xtensa/odroid_go/Kconfig.defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# ODROID-GO Game Kit configuration - -# Copyright (c) 2019 Yannis Damigos -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "odroid_go" - depends on BOARD_ODROID_GO - -config DISK_DRIVER_SDMMC - default y if DISK_ACCESS - -config SPI - default y if DISK_DRIVER_SDMMC - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/odroid_go/doc/index.rst b/boards/xtensa/odroid_go/doc/index.rst deleted file mode 100644 index 933c167f535..00000000000 --- a/boards/xtensa/odroid_go/doc/index.rst +++ /dev/null @@ -1,245 +0,0 @@ -.. _odroid_go: - -ODROID-GO -######### - -Overview -******** - -ODROID-GO Game Kit is a "Do it yourself" ("DIY") portable game console by -HardKernel. It features a custom ESP32-WROVER with 16 MB flash and it operates -from 80 MHz - 240 MHz [1]_. - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 80 - 240MHz -- 4 MB of PSRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- 2.4 inch 320x240 TFT LCD -- Speaker -- Micro SD card slot -- Micro USB port (battery charging and USB_UART data communication -- Input Buttons (Menu, Volume, Select, Start, A, B, Direction Pad) -- Expansion port (I2C, GPIO, SPI) -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) - -.. figure:: img/odroid_go.jpg - :align: center - :alt: ODROID-GO - - ODROID-Go Game Kit - -External Connector -================== - -+-------+------------------+-------------------------+ -| PIN # | Signal Name | ESP32-WROVER Functions | -+=======+==================+=========================+ -| 1 | GND | GND | -+-------+------------------+-------------------------+ -| 2 | VSPI.SCK (IO18) | GPIO18, VSPICLK | -+-------+------------------+-------------------------+ -| 3 | IO12 | GPIO12 | -+-------+------------------+-------------------------+ -| 4 | IO15 | GPIO15, ADC2_CH3 | -+-------+------------------+-------------------------+ -| 5 | IO4 | GPIO4, ADC2_CH0 | -+-------+------------------+-------------------------+ -| 6 | P3V3 | 3.3 V | -+-------+------------------+-------------------------+ -| 7 | VSPI.MISO (IO19) | GPIO19, VSPIQ | -+-------+------------------+-------------------------+ -| 8 | VSPI.MOSI (IO23) | GPIO23, VSPID | -+-------+------------------+-------------------------+ -| 9 | N.C | N/A | -+-------+------------------+-------------------------+ -| 10 | VBUS | USB VBUS (5V) | -+-------+------------------+-------------------------+ - -Supported Features -================== - -The Zephyr odroid_go board configuration supports the following hardware -features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ - - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: odroid_go - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: odroid_go - :goals: build - -The usual ``flash`` target will work with the ``odroid_go`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: odroid_go - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! odroid_go - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: odroid_go - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: odroid_go - :goals: debug - -References -********** - -.. target-notes:: - -.. [1] https://wiki.odroid.com/odroid_go/odroid_go -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/xtensa/odroid_go/odroid_go.dts b/boards/xtensa/odroid_go/odroid_go.dts deleted file mode 100644 index 31ceee79d3c..00000000000 --- a/boards/xtensa/odroid_go/odroid_go.dts +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2019 Yannis Damigos - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "odroid_go-pinctrl.dtsi" -#include - -/ { - model = "ODROID-GO Game Kit"; - compatible = "hardkernel,odroid_go", "espressif,esp32"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,display = &ili9341; - }; - - leds { - compatible = "gpio-leds"; - blue_led: led { - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - label = "Status Led"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - menu_button: menu_button { - label = "Menu"; - gpios = <&gpio0 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - volume_button: volume_button { - label = "Volume"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - select_button: select_button { - label = "Select"; - gpios = <&gpio0 27 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - a_button: a_button { - label = "A"; - gpios = <&gpio1 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - b_button: b_button { - label = "B"; - gpios = <&gpio1 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - start_button: start_button { - label = "Start"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; - - lcd_backlight_en { - compatible = "regulator-fixed"; - regulator-name = "lcd_backlight_enable"; - enable-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - aliases { - uart-0 = &uart0; - led0 = &blue_led; - sw0 = &menu_button; - watchdog0 = &wdt0; - }; - - mipi_dbi { - compatible = "zephyr,mipi-dbi-spi"; - dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - spi-dev = <&spi3>; - write-only; - #address-cells = <1>; - #size-cells = <0>; - - ili9341: ili9341@0 { - compatible = "ilitek,ili9341"; - mipi-max-frequency = <25000000>; - pixel-format = <0>; - reg = <0>; - rotation = <270>; - width = <320>; - height = <240>; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; - - blue-led-disable { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-low; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; - - sdhc0: sdhc@1 { - compatible = "zephyr,sdhc-spi-slot"; - reg = <1>; - status = "okay"; - mmc { - compatible = "zephyr,sdmmc-disk"; - status = "okay"; - }; - spi-max-frequency = <20000000>; - }; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/odroid_go/odroid_go.yaml b/boards/xtensa/odroid_go/odroid_go.yaml deleted file mode 100644 index 8a487018654..00000000000 --- a/boards/xtensa/odroid_go/odroid_go.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: odroid_go -name: ODROID-GO -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - spi - - watchdog - - uart - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: hardkernel diff --git a/boards/xtensa/odroid_go/odroid_go_defconfig b/boards/xtensa/odroid_go/odroid_go_defconfig deleted file mode 100644 index 3bda04a1ed3..00000000000 --- a/boards/xtensa/odroid_go/odroid_go_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ODROID_GO=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y - -# required to enable LCD backlight -CONFIG_REGULATOR=y diff --git a/boards/xtensa/olimex_esp32_evb/Kconfig.board b/boards/xtensa/olimex_esp32_evb/Kconfig.board deleted file mode 100644 index 7bb6c2295b7..00000000000 --- a/boards/xtensa/olimex_esp32_evb/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Olimex ESP32-EVB board configuration - -# Copyright (c) 2022 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_ESP32_EVB - bool "Olimex ESP32-EVB" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROVER_E_N8R2 -endchoice diff --git a/boards/xtensa/olimex_esp32_evb/Kconfig.defconfig b/boards/xtensa/olimex_esp32_evb/Kconfig.defconfig deleted file mode 100644 index 6aca00ecad5..00000000000 --- a/boards/xtensa/olimex_esp32_evb/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Olimex ESP32-EVB board configuration - -# Copyright (c) 2022 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_ESP32_EVB - -config BOARD - default "olimex_esp32_evb" - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -endif # BOARD_OLIMEX_ESP32_EVB diff --git a/boards/xtensa/olimex_esp32_evb/doc/index.rst b/boards/xtensa/olimex_esp32_evb/doc/index.rst deleted file mode 100644 index 3bc02a82295..00000000000 --- a/boards/xtensa/olimex_esp32_evb/doc/index.rst +++ /dev/null @@ -1,265 +0,0 @@ -.. _olimex_esp32_evb: - -Olimex ESP32-EVB -################ - -Overview -******** - -The Olimex ESP32-EVB is an OSHW certified, open-source IoT board based on the -Espressif ESP32-WROOM-32E/UE module. It has a wired 100Mbit/s Ethernet Interface, -Bluetooth LE, WiFi, infrared remote control, and CAN connectivity. Two relays -allows switching power appliances on and off. - -The board can operate from a single LiPo backup battery as it has an internal -LiPo battery charger. There is no step-up converter, so relays, CAN, and USB -power does not work when running off battery. - -.. figure:: ESP32-EVB.jpg - :align: center - :alt: ESP32-EVB - - ESP32-EVB (Credit: Olimex) - -Hardware -******** - -- ESP32-WROOM-32E/UE module with 4MB flash. -- On-board programmer, CH340T USB-to-UART -- WiFi, Bluetooth LE connectivity. -- 100Mbit/s Ethernet interface, Microchip LAN8710A PHY. -- MicroSD card slot. -- 2 x 10A/250VAC (15A/120VAC 15A/24VDC) relays with connectors and status LEDs. -- CAN interface, Microchip MCP2562-E high-speed CAN transceiver. -- IR receiver and transmitter, up to 5 meters distance. -- BL4054B LiPo battery charger with status LEDs for stand-alone operation during - power outages. -- Power jack for external 5VDC power supply. -- Univeral EXTension (UEXT) connector for connecting UEXT modules. -- User push button. -- 40 pin GPIO connector with all ESP32 pins. - -For more information about the ESP32-EVB and the ESP32-WROOM-32E/UE module, see -these reference documents: - -- `ESP32-EVB Website`_ -- `ESP32-EVB Schematic`_ -- `ESP32-EVB GitHub Repository`_ -- `ESP32-WROOM32-E/UE Datasheet`_ - -Supported Features -****************** - -The olimex_esp32_evb board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| EFUSE | on-chip | hwinfo, device ID | -+-----------+------------+-------------------------------------+ -| FLASH | module | External flash | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | I2C | -+-----------+------------+-------------------------------------+ -| INTERRUPT | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| IO_MUX | on-chip | pinctrl | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| TIMG | on-chip | counter | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| TWAI | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | uart | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| WiFi | on-chip | WiFi | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig``. - -Other hardware features are not currently supported by the port. - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: olimex_esp32_evb - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: olimex_esp32_evb - :goals: build - -The usual ``flash`` target will work with the ``olimex_esp32_evb`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: olimex_esp32_evb - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! olimex_esp32_evb - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: olimex_esp32_evb - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: olimex_esp32_evb - :goals: debug - -References -********** - -.. _ESP32-EVB Website: - https://www.olimex.com/Products/IoT/ESP32/ESP32-EVB/open-source-hardware - -.. _ESP32-EVB Schematic: - https://github.com/OLIMEX/ESP32-EVB/raw/master/HARDWARE/REV-I/ESP32-EVB_Rev_I.pdf - -.. _ESP32-EVB GitHub Repository: - https://github.com/OLIMEX/ESP32-EVB - -.. _ESP32-WROOM32-E/UE Datasheet: - https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32e_esp32-wroom-32ue_datasheet_en.pdf - -.. _OpenOCD ESP32: - https://github.com/espressif/openocd-esp32/releases diff --git a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb.yaml b/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb.yaml deleted file mode 100644 index 83320db1529..00000000000 --- a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: olimex_esp32_evb -name: Olimex ESP32-EVB -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - can - - counter - - gpio - - hwinfo - - i2c - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: olimex diff --git a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig b/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig deleted file mode 100644 index a89b387d084..00000000000 --- a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_OLIMEX_ESP32_EVB=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/qemu_xtensa/Kconfig b/boards/xtensa/qemu_xtensa/Kconfig deleted file mode 100644 index 2ecdedbd716..00000000000 --- a/boards/xtensa/qemu_xtensa/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Xtensa Qemu board configuration - -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/xtensa/qemu_xtensa/Kconfig.board b/boards/xtensa/qemu_xtensa/Kconfig.board deleted file mode 100644 index 34cdf44a15c..00000000000 --- a/boards/xtensa/qemu_xtensa/Kconfig.board +++ /dev/null @@ -1,17 +0,0 @@ -# XTENSA board configuration - -# Copyright (c) 2017, 2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_XTENSA - bool "Xtensa emulation using QEMU" - depends on SOC_XTENSA_DC233C - select QEMU_TARGET - select ARCH_SUPPORTS_COREDUMP - -config BOARD_QEMU_XTENSA_MMU - bool "Xtensa emulation using QEMU with MMU" - depends on SOC_XTENSA_DC233C - select QEMU_TARGET - select ARCH_SUPPORTS_COREDUMP - select XTENSA_MMU diff --git a/boards/xtensa/qemu_xtensa/Kconfig.defconfig b/boards/xtensa/qemu_xtensa/Kconfig.defconfig deleted file mode 100644 index a6beed9151c..00000000000 --- a/boards/xtensa/qemu_xtensa/Kconfig.defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2017, 2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_XTENSA - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_xtensa" - -config IPM_CONSOLE_STACK_SIZE - default 2048 if IPM_CONSOLE_RECEIVER - -endif # BOARD_QEMU_XTENSA - -if BOARD_QEMU_XTENSA_MMU - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_xtensa_mmu" - -config IPM_CONSOLE_STACK_SIZE - default 2048 if IPM_CONSOLE_RECEIVER - -endif # BOARD_QEMU_XTENSA diff --git a/boards/xtensa/qemu_xtensa/board.cmake b/boards/xtensa/qemu_xtensa/board.cmake deleted file mode 100644 index 56a6c358be4..00000000000 --- a/boards/xtensa/qemu_xtensa/board.cmake +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -if(CONFIG_BOARD_QEMU_XTENSA OR CONFIG_BOARD_QEMU_XTENSA_MMU) - set(QEMU_CPU_TYPE_${ARCH} dc233c) - - set(QEMU_FLAGS_${ARCH} - -machine sim -semihosting -nographic -cpu dc233c - ) -endif() - -# TODO: Support debug -# board_set_debugger_ifnset(qemu) -# debugserver: QEMU_EXTRA_FLAGS += -s -S -# debugserver: qemu diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu.yaml b/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu.yaml deleted file mode 100644 index aa2ef7692d4..00000000000 --- a/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: qemu_xtensa_mmu -name: QEMU Emulation for Xtensa with MMU -type: qemu -simulation: qemu -arch: xtensa -toolchain: - - zephyr - - xtools -testing: - default: true - ignore_tags: - - net - - bluetooth diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu_defconfig b/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu_defconfig deleted file mode 100644 index 6587737bd88..00000000000 --- a/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_BOARD_QEMU_XTENSA_MMU=y -CONFIG_CONSOLE=y -CONFIG_SOC_XTENSA_DC233C=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 -CONFIG_STACK_SENTINEL=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_SIMULATOR_XTENSA=y -CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/xtensa/xiao_esp32s3/Kconfig.board b/boards/xtensa/xiao_esp32s3/Kconfig.board deleted file mode 100644 index 99669d929e3..00000000000 --- a/boards/xtensa/xiao_esp32s3/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# XIAO ESP32S3 board configuration - -# Copyright (c) 2023 Seeed Studio inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_XIAO_ESP32S3 - bool "XIAO ESP32S3 Board" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_WROOM_N8R8 -endchoice diff --git a/boards/xtensa/xiao_esp32s3/Kconfig.defconfig b/boards/xtensa/xiao_esp32s3/Kconfig.defconfig deleted file mode 100644 index 3bc3e999189..00000000000 --- a/boards/xtensa/xiao_esp32s3/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2023 Seeed Studio inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "xiao_esp32s3" - depends on BOARD_XIAO_ESP32S3 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/xiao_esp32s3/doc/index.rst b/boards/xtensa/xiao_esp32s3/doc/index.rst deleted file mode 100644 index 62a5eb69eba..00000000000 --- a/boards/xtensa/xiao_esp32s3/doc/index.rst +++ /dev/null @@ -1,243 +0,0 @@ -.. _xiao_esp32s3: - -XIAO ESP32S3 -############ - -Overview -******** - -Seeed Studio XIAO ESP32S3 is an IoT mini development board based on the -Espressif ESP32-S3 WiFi/Bluetooth dual-mode chip. - -For more details see the `Seeed Studio XIAO ESP32S3`_ wiki page. - -.. figure:: img/xiao_esp32s3.jpg - :align: center - :alt: XIAO ESP32S3 - - XIAO ESP32S3 - -Hardware -******** - -This board is based on the ESP32-S3 with 8MB of flash, WiFi and BLE support. It -has an USB-C port for programming and debugging, integrated battery charging -and an U.FL external antenna connector. It is based on a standard XIAO 14 pin -pinout. - -ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi -and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor -(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, -RF module, and numerous peripherals. - -Supported Features -================== - -Current Zephyr's XIAO ESP32S3 board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI/CAN | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ - -Connections and IOs -=================== - -The board uses a standard XIAO pinout, the default pin mapping is the following: - -.. figure:: img/xiao_esp32s3_pinout.jpg - :align: center - :alt: XIAO ESP32S3 Pinout - - XIAO ESP32S3 Pinout - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: xiao_esp32s3 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3 - :goals: build - -The usual ``flash`` target will work with the ``xiao_esp32s3`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! xiao_esp32s3 - -Debugging -********* - -ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32-S3`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3 - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3 - :goals: debug -.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ -.. _`OpenOCD`: https://github.com/openocd-org/openocd - -References -********** - -.. target-notes:: - -.. _`Seeed Studio XIAO ESP32S3`: https://wiki.seeedstudio.com/xiao_esp32s3_getting_started/ diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3.dts b/boards/xtensa/xiao_esp32s3/xiao_esp32s3.dts deleted file mode 100644 index a4592b26bce..00000000000 --- a/boards/xtensa/xiao_esp32s3/xiao_esp32s3.dts +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2023 Seeed Studio inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "xiao_esp32s3-pinctrl.dtsi" -#include "seeed_xiao_connector.dtsi" - -/ { - model = "Seeed XIAO ESP32S3"; - compatible = "seeed,xiao-esp32s3"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - i2c-0 = &i2c0; - watchdog0 = &wdt0; - led0 = &led0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - label = "BUILTIN LED"; - }; - }; - -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&trng0 { - status = "okay"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&twai { - pinctrl-0 = <&twai_default>; - pinctrl-names = "default"; - bus-speed = <125000>; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3.yaml b/boards/xtensa/xiao_esp32s3/xiao_esp32s3.yaml deleted file mode 100644 index 59ddcaec1e1..00000000000 --- a/boards/xtensa/xiao_esp32s3/xiao_esp32s3.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: xiao_esp32s3 -name: XIAO ESP32S3 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - can - - counter - - watchdog - - entropy - - pwm - - dma -testing: - ignore_tags: - - net - - bluetooth -vendor: seeed diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig b/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig deleted file mode 100644 index 978da251a58..00000000000 --- a/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_XIAO_ESP32S3=y -CONFIG_SOC_SERIES_ESP32S3=y -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/xtensa/xt-sim/Kconfig.board b/boards/xtensa/xt-sim/Kconfig.board deleted file mode 100644 index d67c68417a9..00000000000 --- a/boards/xtensa/xt-sim/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# XTENSA board configuration - -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_XT_SIM - bool "Xtensa Development ISS" - depends on SIMULATOR_XTENSA diff --git a/boards/xtensa/xt-sim/Kconfig.defconfig b/boards/xtensa/xt-sim/Kconfig.defconfig deleted file mode 100644 index ab2d5e9f13b..00000000000 --- a/boards/xtensa/xt-sim/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "xt-sim" - -config IPM_CONSOLE_STACK_SIZE - default 2048 if IPM_CONSOLE_RECEIVER diff --git a/boards/xtensa/yd_esp32/Kconfig.board b/boards/xtensa/yd_esp32/Kconfig.board deleted file mode 100644 index 843b2b38627..00000000000 --- a/boards/xtensa/yd_esp32/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# YD-ESP32 board configuration - -# Copyright (c) 2023 Julio Cesar -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_YD_ESP32 - bool "YD-ESP32 Development Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROOM_32UE_N4 -endchoice diff --git a/boards/xtensa/yd_esp32/Kconfig.defconfig b/boards/xtensa/yd_esp32/Kconfig.defconfig deleted file mode 100644 index 4807671ca79..00000000000 --- a/boards/xtensa/yd_esp32/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# YD-ESP32 board configuration - -# Copyright (c) 2023 Julio Cesar -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "yd_esp32" - depends on BOARD_YD_ESP32 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/yd_esp32/doc/index.rst b/boards/xtensa/yd_esp32/doc/index.rst deleted file mode 100644 index c49bdc0cb60..00000000000 --- a/boards/xtensa/yd_esp32/doc/index.rst +++ /dev/null @@ -1,310 +0,0 @@ -.. _yd_esp32: - -YD-ESP32 -######## - -Overview -******** - -The YD-ESP32 development board is one of VCC-GND® Studio’s official boards. -This board is based on the ESP32-WROOM-32E module, with the ESP32 as the core. - -.. figure:: img/yd_esp32.png - :align: center - :alt: YD-ESP32 - - YD-ESP32 DevKit with ESP32-WROOM-32E Module - -ESP32 -===== - -ESP32 is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a -Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32 is created and developed by Espressif Systems, a -Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. [1]_ - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz -- 520KB of SRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- Various peripherals: - - - 12-bit ADC with up to 18 channels - - 2x 8-bit DACs - - 10x touch sensors - - Temperature sensor - - 4x SPI - - 2x I2S - - 2x I2C - - 3x UART - - SD/SDIO/MMC host - - Slave (SDIO/SPI) - - Ethernet MAC - - CAN bus 2.0 - - IR (RX/TX) - - Motor PWM - - LED PWM with up to 16 channels - - Hall effect sensor - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -- 5uA deep sleep current - -Supported Features -================== - -Current Zephyr's YD-ESP32 board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: yd_esp32 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: yd_esp32 - :goals: build - -The usual ``flash`` target will work with the ``yd_esp32`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: yd_esp32 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! yd_esp32 - -RGB LED -======= - -The board contains an addressable RGB LED (`XL-5050RGBC-WS2812B`_), driven by GPIO16. -Here is an example of how to test it using the :zephyr:code-sample:`led-ws2812` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_ws2812 - :board: yd_esp32 - :goals: flash - - -.. _`XL-5050RGBC-WS2812B`: http://www.xinglight.cn/index.php?c=show&id=947 - -Debugging -********* - -ESP32 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -On the YD-ESP32 board, the JTAG pins are not run to a -standard connector (e.g. ARM 20-pin) and need to be manually connected -to the external programmer (e.g. a Flyswatter2): - -+------------+-----------+ -| ESP32 pin | JTAG pin | -+============+===========+ -| 3V3 | VTRef | -+------------+-----------+ -| EN | nTRST | -+------------+-----------+ -| IO14 | TMS | -+------------+-----------+ -| IO12 | TDI | -+------------+-----------+ -| GND | GND | -+------------+-----------+ -| IO13 | TCK | -+------------+-----------+ -| IO15 | TDO | -+------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: yd_esp32 - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: yd_esp32 - :goals: debug - -Note on Debugging with GDB Stub -=============================== - -GDB stub is enabled on ESP32. - -* When adding breakpoints, please use hardware breakpoints with command - ``hbreak``. Command ``break`` uses software breakpoints which requires - modifying memory content to insert break/trap instructions. - This does not work as the code is on flash which cannot be randomly - accessed for modification. - -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD`: https://github.com/openocd-org/openocd - -References -********** - -.. [1] https://en.wikipedia.org/wiki/ESP32 -.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/yd_esp32/yd_esp32.dts b/boards/xtensa/yd_esp32/yd_esp32.dts deleted file mode 100644 index 9442e5009e4..00000000000 --- a/boards/xtensa/yd_esp32/yd_esp32.dts +++ /dev/null @@ -1,184 +0,0 @@ -/* - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include -#include "yd_esp32-pinctrl.dtsi" -#include - -/ { - model = "VCC-GND Studio YD-ESP32"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - sw0 = &button0; - watchdog0 = &wdt0; - led-strip = &rgb_led; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&pinctrl { - spim2_default: spim2_default { - group2 { - pinmux = ; - output-low; - }; - }; -}; - -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; - - rgb_led: ws2812@0 { - compatible = "worldsemi,ws2812-spi"; - - /* SPI */ - reg = <0>; /* ignored, but necessary for SPI bindings */ - spi-max-frequency = <6400000>; - - /* XL-5050RGBC-WS2812B */ - chain-length = <1>; - spi-one-frame = <0xfc>; /* 11111100: 0.937 us high and 0.313 us low */ - spi-zero-frame = <0xc0>; /* 11000000: 0.313 us high and 0.937 us low */ - color-mapping = ; - }; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/yd_esp32/yd_esp32.yaml b/boards/xtensa/yd_esp32/yd_esp32.yaml deleted file mode 100644 index 2a73436066b..00000000000 --- a/boards/xtensa/yd_esp32/yd_esp32.yaml +++ /dev/null @@ -1,24 +0,0 @@ -identifier: yd_esp32 -name: YD-ESP32 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - watchdog - - uart - - nvs - - pwm - - dac - - spi - - counter - - entropy -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/yd_esp32/yd_esp32_defconfig b/boards/xtensa/yd_esp32/yd_esp32_defconfig deleted file mode 100644 index c90b1c17d15..00000000000 --- a/boards/xtensa/yd_esp32/yd_esp32_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Julio Cesar -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_YD_ESP32=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/cmake/compiler/gcc/target_arc.cmake b/cmake/compiler/gcc/target_arc.cmake index cf3d0909917..e18fa468f16 100644 --- a/cmake/compiler/gcc/target_arc.cmake +++ b/cmake/compiler/gcc/target_arc.cmake @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -if(EXISTS ${SOC_DIR}/${ARCH}/${SOC_PATH}/tune_build_ops.cmake) - include(${SOC_DIR}/${ARCH}/${SOC_PATH}/tune_build_ops.cmake) +if(EXISTS ${SOC_FULL_DIR}/tune_build_ops.cmake) + include(${SOC_FULL_DIR}/tune_build_ops.cmake) endif() if(NOT DEFINED GCC_ARC_TUNED_CPU) diff --git a/cmake/modules/FindDeprecated.cmake b/cmake/modules/FindDeprecated.cmake index 875f243b034..bad0ab6ffe7 100644 --- a/cmake/modules/FindDeprecated.cmake +++ b/cmake/modules/FindDeprecated.cmake @@ -112,7 +112,7 @@ if("SEARCHED_LINKER_SCRIPT" IN_LIST Deprecated_FIND_COMPONENTS) set(LINKER_SCRIPT ${BOARD_DIR}/linker.ld) if(NOT EXISTS ${LINKER_SCRIPT}) # If not available, try an SoC specific linker file - set(LINKER_SCRIPT ${SOC_DIR}/${ARCH}/${SOC_PATH}/linker.ld) + set(LINKER_SCRIPT ${SOC_FULL_DIR}/linker.ld) endif() message(DEPRECATION "Pre-defined `linker.ld` script is deprecated. Please set " diff --git a/cmake/modules/FindHostTools.cmake b/cmake/modules/FindHostTools.cmake index b2d5257642d..8d3c9eccaaf 100644 --- a/cmake/modules/FindHostTools.cmake +++ b/cmake/modules/FindHostTools.cmake @@ -65,8 +65,9 @@ find_program(BOSSAC bossac) # in the mcuboot repository if that's present in some cases) find_program(IMGTOOL imgtool) -# Pick host system's toolchain if we are targeting posix -if("${ARCH}" STREQUAL "posix" OR "${ARCH}" STREQUAL "unit_testing") +# Default to the host system's toolchain if we are targeting a host based target +if((${BOARD_DIR} MATCHES "boards\/native") OR ("${ARCH}" STREQUAL "posix") + OR ("${BOARD}" STREQUAL "unit_testing")) if(NOT "${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "llvm") set(ZEPHYR_TOOLCHAIN_VARIANT "host") endif() diff --git a/cmake/modules/arch.cmake b/cmake/modules/arch.cmake deleted file mode 100644 index 806b5c12b58..00000000000 --- a/cmake/modules/arch.cmake +++ /dev/null @@ -1,48 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2022, Nordic Semiconductor ASA - -# Configure ARCH settings based on board directory and arch root. -# -# This CMake module will set the following variables in the build system based -# on board directory and arch root. -# -# If no implementation is available for the current arch an error will be raised. -# -# Outcome: -# The following variables will be defined when this CMake module completes: -# -# - ARCH: Name of the arch in use. -# - ARCH_DIR: Directory containing the arch implementation. -# - ARCH_ROOT: ARCH_ROOT with ZEPHYR_BASE appended -# -# Variable dependencies: -# - ARCH_ROOT: CMake list of arch roots containing arch implementations -# - BOARD_DIR: CMake variable specifying the directory of the selected BOARD -# -# Variables set by this module and not mentioned above are considered internal -# use only and may be removed, renamed, or re-purposed without prior notice. - -include_guard(GLOBAL) - -# 'ARCH_ROOT' is a prioritized list of directories where archs may be -# found. It always includes ${ZEPHYR_BASE} at the lowest priority (except for unittesting). -if(NOT unittest IN_LIST Zephyr_FIND_COMPONENTS) - list(APPEND ARCH_ROOT ${ZEPHYR_BASE}) -endif() - -cmake_path(GET BOARD_DIR PARENT_PATH board_arch_dir) -cmake_path(GET board_arch_dir FILENAME ARCH) - -foreach(root ${ARCH_ROOT}) - if(EXISTS ${root}/arch/${ARCH}/CMakeLists.txt) - set(ARCH_DIR ${root}/arch) - break() - endif() -endforeach() - -if(NOT ARCH_DIR) - message(FATAL_ERROR "Could not find ARCH=${ARCH} for BOARD=${BOARD}, \ -please check your installation. ARCH roots searched: \n\ -${ARCH_ROOT}") -endif() diff --git a/cmake/modules/arch_v1.cmake b/cmake/modules/arch_v1.cmake new file mode 100644 index 00000000000..613182f0723 --- /dev/null +++ b/cmake/modules/arch_v1.cmake @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2022, Nordic Semiconductor ASA + +# +# This CMake module is only valid for hw model v1. +# In hw model v1, then arch is determined by the board folder structure. +# +# Configure ARCH settings based on board directory and arch root. +# +# This CMake module will set the following variables in the build system based +# on board directory and arch root. +# +# If no implementation is available for the current arch an error will be raised. +# +# Outcome: +# The following variables will be defined when this CMake module completes: +# +# - ARCH: Name of the arch in use. +# - ARCH_DIR: Directory containing the arch implementation. +# - ARCH_ROOT: ARCH_ROOT with ZEPHYR_BASE appended +# +# Variable dependencies: +# - ARCH_ROOT: CMake list of arch roots containing arch implementations +# - BOARD_DIR: CMake variable specifying the directory of the selected BOARD +# +# Variables set by this module and not mentioned above are considered internal +# use only and may be removed, renamed, or re-purposed without prior notice. + +include_guard(GLOBAL) + +if(HWMv1) + # 'ARCH_ROOT' is a prioritized list of directories where archs may be + # found. It always includes ${ZEPHYR_BASE} at the lowest priority (except for unittesting). + if(NOT unittest IN_LIST Zephyr_FIND_COMPONENTS) + list(APPEND ARCH_ROOT ${ZEPHYR_BASE}) + endif() + + cmake_path(GET BOARD_DIR PARENT_PATH board_arch_dir) + cmake_path(GET board_arch_dir FILENAME ARCH) + + foreach(root ${ARCH_ROOT}) + if(EXISTS ${root}/arch/${ARCH}/CMakeLists.txt) + set(ARCH_DIR ${root}/arch) + break() + endif() + endforeach() + + if(NOT ARCH_DIR) + message(FATAL_ERROR "Could not find ARCH=${ARCH} for BOARD=${BOARD}, \ +please check your installation. ARCH roots searched: \n\ +${ARCH_ROOT}") + endif() +endif() diff --git a/cmake/modules/arch_v2.cmake b/cmake/modules/arch_v2.cmake new file mode 100644 index 00000000000..8ad03724745 --- /dev/null +++ b/cmake/modules/arch_v2.cmake @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023, Nordic Semiconductor ASA + +# +# Configure ARCH settings based on KConfig settings and arch root. +# +# This CMake module will set the following variables in the build system based +# on board directory and arch root. +# +# If no implementation is available for the current arch an error will be raised. +# +# Outcome: +# The following variables will be defined when this CMake module completes: +# +# - ARCH: Name of the arch in use. +# - ARCH_DIR: Directory containing the arch implementation. +# - ARCH_ROOT: ARCH_ROOT with ZEPHYR_BASE appended +# +# Variable dependencies: +# - ARCH_ROOT: CMake list of arch roots containing arch implementations +# +# Variables set by this module and not mentioned above are considered internal +# use only and may be removed, renamed, or re-purposed without prior notice. + +include_guard(GLOBAL) + +if(HWMv2) + # HWMv2 obtains arch from Kconfig for the given Board / SoC variant because + # the Board / SoC path is no longer sufficient for determine the arch + # (read: multi-core and multi-arch SoC). + set(ARCH ${CONFIG_ARCH}) + string(TOUPPER "${ARCH}" arch_upper) + + if(NOT ARCH) + message(FATAL_ERROR "ARCH not defined. Check that BOARD=${BOARD}, is selecting " + "an appropriate SoC in Kconfig, SoC=${CONFIG_SOC}, and that the SoC " + "is selecting the correct architecture." + ) + endif() + + cmake_path(GET ARCH_V2_${arch_upper}_DIR PARENT_PATH ARCH_DIR) + if(NOT ARCH_DIR) + message(FATAL_ERROR "Could not find ARCH=${ARCH} for BOARD=${BOARD}, \ +please check your installation. ARCH roots searched: \n\ +${ARCH_ROOT}") + endif() +endif() diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index 77f61c32f7b..0854653445d 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -61,27 +61,61 @@ if(NOT unittest IN_LIST Zephyr_FIND_COMPONENTS) list(APPEND BOARD_ROOT ${ZEPHYR_BASE}) endif() -string(FIND "${BOARD}" "@" REVISION_SEPARATOR_INDEX) -if(NOT (REVISION_SEPARATOR_INDEX EQUAL -1)) - math(EXPR BOARD_REVISION_INDEX "${REVISION_SEPARATOR_INDEX} + 1") - string(SUBSTRING ${BOARD} ${BOARD_REVISION_INDEX} -1 BOARD_REVISION) - string(SUBSTRING ${BOARD} 0 ${REVISION_SEPARATOR_INDEX} BOARD) -endif() +# Helper function for parsing a board's name, revision, and identifier, +# from one input variable to three separate output variables. +function(parse_board_components board_in name_out revision_out identifier_out) + if(NOT "${${board_in}}" MATCHES "^([^@/]+)(@[^@/]+)?(/[^@]+)?$") + message(FATAL_ERROR + "Invalid revision / identifier format for ${board_in} (${${board_in}}). " + "Valid format is: @/" + ) + endif() + string(REPLACE "@" "" board_revision "${CMAKE_MATCH_2}") + + set(${name_out} ${CMAKE_MATCH_1} PARENT_SCOPE) + set(${revision_out} ${board_revision} PARENT_SCOPE) + set(${identifier_out} ${CMAKE_MATCH_3} PARENT_SCOPE) +endfunction() + +parse_board_components(BOARD BOARD BOARD_REVISION BOARD_IDENTIFIER) zephyr_get(ZEPHYR_BOARD_ALIASES) if(DEFINED ZEPHYR_BOARD_ALIASES) include(${ZEPHYR_BOARD_ALIASES}) if(${BOARD}_BOARD_ALIAS) set(BOARD_ALIAS ${BOARD} CACHE STRING "Board alias, provided by user") - set(BOARD ${${BOARD}_BOARD_ALIAS}) + parse_board_components(${BOARD}_BOARD_ALIAS BOARD BOARD_ALIAS_REVISION BOARD_ALIAS_IDENTIFIER) message(STATUS "Aliased BOARD=${BOARD_ALIAS} changed to ${BOARD}") + if(NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION ${BOARD_ALIAS_REVISION}) + endif() + set(BOARD_IDENTIFIER ${BOARD_ALIAS_IDENTIFIER}${BOARD_IDENTIFIER}) endif() endif() + include(${ZEPHYR_BASE}/boards/deprecated.cmake) if(${BOARD}_DEPRECATED) set(BOARD_DEPRECATED ${BOARD} CACHE STRING "Deprecated board name, provided by user") - set(BOARD ${${BOARD}_DEPRECATED}) + parse_board_components(${BOARD}_DEPRECATED BOARD BOARD_DEPRECATED_REVISION BOARD_DEPRECATED_IDENTIFIER) message(WARNING "Deprecated BOARD=${BOARD_DEPRECATED} name specified, board automatically changed to: ${BOARD}.") + if(DEFINED BOARD_DEPRECATED_REVISION) + if(DEFINED BOARD_REVISION) + message(FATAL_ERROR + "Invalid board revision: ${BOARD_REVISION}\n" + "Deprecated board '${BOARD_DEPRECATED}' is now implemented as a revision of another board " + "(${BOARD}@${BOARD_DEPRECATED_REVISION}), so the specified revision does not apply. " + "Please consult the documentation for '${BOARD}' to see how to build for the new board." + ) + endif() + set(BOARD_REVISION ${BOARD_DEPRECATED_REVISION}) + endif() + if(DEFINED BOARD_IDENTIFIER) + message(FATAL_ERROR + "Deprecated boards cannot have board identifiers: ${BOARD_DEPRECATED}${BOARD_IDENTIFIER}.\n" + "Please consult the documentation for '${BOARD}' to see how to build for the new board." + ) + endif() + set(BOARD_IDENTIFIER ${BOARD_DEPRECATED_IDENTIFIER}) endif() zephyr_boilerplate_watch(BOARD) @@ -95,41 +129,166 @@ Hints: - if your board directory is '/foo/bar/boards//my_board' then add '/foo/bar' to BOARD_ROOT, not the entire board directory - if in doubt, use absolute paths") endif() +endforeach() + +if((HWMv1 AND NOT EXISTS ${BOARD_DIR}/${BOARD}_defconfig) + OR (HWMv2 AND NOT EXISTS ${BOARD_DIR}/board.yml)) + message(WARNING "BOARD_DIR: ${BOARD_DIR} has been moved or deleted. " + "Trying to find new location." + ) + set(BOARD_DIR BOARD_DIR-NOTFOUND CACHE PATH "Path to a file." FORCE) +endif() + +# Prepare list boards command. +# This command is used for locating the board dir as well as printing all boards +# in the system in the following cases: +# - User specifies an invalid BOARD +# - User invokes ' boards' target +list(TRANSFORM ARCH_ROOT PREPEND "--arch-root=" OUTPUT_VARIABLE arch_root_args) +list(TRANSFORM BOARD_ROOT PREPEND "--board-root=" OUTPUT_VARIABLE board_root_args) +list(TRANSFORM SOC_ROOT PREPEND "--soc-root=" OUTPUT_VARIABLE soc_root_args) + +set(list_boards_commands + COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/list_boards.py + ${arch_root_args} ${board_root_args} --arch-root=${ZEPHYR_BASE} + ${soc_root_args} --soc-root=${ZEPHYR_BASE} +) + +if(NOT BOARD_DIR) + if(BOARD_ALIAS) + execute_process(${list_boards_commands} --board=${BOARD_ALIAS} --cmakeformat={DIR} + OUTPUT_VARIABLE ret_board + ERROR_VARIABLE err_board + RESULT_VARIABLE ret_val + ) + string(STRIP "${ret_board}" ret_board) + cmake_parse_arguments(BOARD_HIDDEN "" "DIR" "" ${ret_board}) + set(BOARD_HIDDEN_DIR ${BOARD_HIDDEN_DIR} CACHE PATH "Path to a folder." FORCE) - # NB: find_path will return immediately if the output variable is - # already set - if (BOARD_ALIAS) - find_path(BOARD_HIDDEN_DIR - NAMES ${BOARD_ALIAS}_defconfig - PATHS ${root}/boards/*/* - NO_DEFAULT_PATH - ) if(BOARD_HIDDEN_DIR) message("Board alias ${BOARD_ALIAS} is hiding the real board of same name") endif() endif() - if(BOARD_DIR AND NOT EXISTS ${BOARD_DIR}/${BOARD}_defconfig) - message(WARNING "BOARD_DIR: ${BOARD_DIR} has been moved or deleted. " - "Trying to find new location." - ) - set(BOARD_DIR BOARD_DIR-NOTFOUND CACHE PATH "Path to a file." FORCE) +endif() + +set(format_str "{NAME}\;{DIR}\;{HWM}\;") +set(format_str "${format_str}{REVISION_FORMAT}\;{REVISION_DEFAULT}\;{REVISION_EXACT}\;") +set(format_str "${format_str}{REVISIONS}\;{SOCS}\;{IDENTIFIERS}") + +if(BOARD_DIR) + set(board_dir_arg "--board-dir=${BOARD_DIR}") +endif() +execute_process(${list_boards_commands} --board=${BOARD} ${board_dir_arg} + --cmakeformat=${format_str} + OUTPUT_VARIABLE ret_board + ERROR_VARIABLE err_board + RESULT_VARIABLE ret_val +) +if(ret_val) + message(FATAL_ERROR "Error finding board: ${BOARD}\nError message: ${err_board}") +endif() + +if(NOT "${ret_board}" STREQUAL "") + string(STRIP "${ret_board}" ret_board) + set(single_val "NAME;DIR;HWM;REVISION_FORMAT;REVISION_DEFAULT;REVISION_EXACT") + set(multi_val "REVISIONS;SOCS;IDENTIFIERS") + cmake_parse_arguments(BOARD "" "${single_val}" "${multi_val}" ${ret_board}) + set(BOARD_DIR ${BOARD_DIR} CACHE PATH "Board directory for board (${BOARD})" FORCE) + + # Create two CMake variables identifying the hw model. + # CMake variable: HWM=[v1,v2] + # CMake variable: HWMv1=True, when HWMv1 is in use. + # CMake variable: HWMv2=True, when HWMv2 is in use. + set(HWM ${BOARD_HWM} CACHE INTERNAL "Zephyr hardware model version") + set(HWM${HWM} True CACHE INTERNAL "Zephyr hardware model") +elseif(BOARD_DIR) + message(FATAL_ERROR "Error finding board: ${BOARD} in ${BOARD_DIR}.\n" + "This indicates the board has been removed, renamed, or placed at a new location.\n" + "Please run a pristine build." + ) +else() + message("No board named '${BOARD}' found.\n\n" + "Please choose one of the following boards:\n" + ) + execute_process(${list_boards_commands}) + unset(CACHED_BOARD CACHE) + message(FATAL_ERROR "Invalid BOARD; see above.") +endif() + +if(HWMv1 AND DEFINED BOARD_IDENTIFIER) + message(FATAL_ERROR + "Board '${BOARD}' does not support board identifiers, ${BOARD}${BOARD_IDENTIFIER}.\n" + "Please specify board without an identifier.\n" + ) +endif() + +cmake_path(IS_PREFIX ZEPHYR_BASE "${BOARD_DIR}" NORMALIZE in_zephyr_tree) +if(NOT in_zephyr_tree) + set(USING_OUT_OF_TREE_BOARD 1) +endif() + +if(HWMv1) + if(EXISTS ${BOARD_DIR}/revision.cmake) + # Board provides revision handling. + include(${BOARD_DIR}/revision.cmake) + elseif(BOARD_REVISION) + message(WARNING "Board revision ${BOARD_REVISION} specified for ${BOARD}, \ + but board has no revision so revision will be ignored.") endif() - find_path(BOARD_DIR - NAMES ${BOARD}_defconfig - PATHS ${root}/boards/*/* - NO_DEFAULT_PATH +elseif(HWMv2) + if(BOARD_REVISION_FORMAT) + if(BOARD_REVISION_FORMAT STREQUAL "custom") + include(${BOARD_DIR}/revision.cmake) + else() + if(EXISTS ${BOARD_DIR}/revision.cmake) + message(WARNING + "revision.cmake ignored, revision.cmake is only used for revision format: 'custom'" + ) + endif() + + string(TOUPPER "${BOARD_REVISION_FORMAT}" rev_format) + if(BOARD_REVISION_EXACT) + set(rev_exact EXACT) + endif() + + board_check_revision( + FORMAT ${rev_format} + DEFAULT_REVISION ${BOARD_REVISION_DEFAULT} + VALID_REVISIONS ${BOARD_REVISIONS} + ${rev_exact} + ) + endif() + elseif(DEFINED BOARD_REVISION) + if(EXISTS ${BOARD_DIR}/revision.cmake) + message(WARNING + "revision.cmake is not used, revisions must be defined in '${BOARD_DIR}/board.yml'" + ) + endif() + + message(FATAL_ERROR "Invalid board revision: ${BOARD_REVISION}\n" + "Board '${BOARD}' does not define any revisions." ) - if(BOARD_DIR AND NOT (${root} STREQUAL ${ZEPHYR_BASE})) - set(USING_OUT_OF_TREE_BOARD 1) endif() -endforeach() -if(EXISTS ${BOARD_DIR}/revision.cmake) - # Board provides revision handling. - include(${BOARD_DIR}/revision.cmake) -elseif(BOARD_REVISION) - message(WARNING "Board revision ${BOARD_REVISION} specified for ${BOARD}, \ - but board has no revision so revision will be ignored.") + if(BOARD_IDENTIFIERS) + # Allow users to omit the SoC when building for a board with a single SoC. + list(LENGTH BOARD_SOCS socs_length) + if(NOT DEFINED BOARD_IDENTIFIER AND socs_length EQUAL 1) + set(BOARD_IDENTIFIER "/${BOARD_SOCS}") + elseif("${BOARD_IDENTIFIER}" MATCHES "^//.*" AND socs_length EQUAL 1) + string(REGEX REPLACE "^//" "/${BOARD_SOCS}/" BOARD_IDENTIFIER "${BOARD_IDENTIFIER}") + endif() + + if(NOT ("${BOARD}${BOARD_IDENTIFIER}" IN_LIST BOARD_IDENTIFIERS)) + string(REPLACE ";" "\n" BOARD_IDENTIFIERS "${BOARD_IDENTIFIERS}") + unset(CACHED_BOARD CACHE) + message(FATAL_ERROR "Board identifier `${BOARD_IDENTIFIER}` for board \ + `${BOARD}` not found. Please specify a valid board.\n" + "Valid board identifiers for ${BOARD_NAME} are:\n${BOARD_IDENTIFIERS}\n") + endif() + endif() +else() + message(FATAL_ERROR "Unknown hw model (${HWM}) for board: ${BOARD}.") endif() set(board_message "Board: ${BOARD}") @@ -144,29 +303,13 @@ if(DEFINED BOARD_REVISION) string(REPLACE "." "_" BOARD_REVISION_STRING ${BOARD_REVISION}) endif() -message(STATUS "${board_message}") - -# Prepare boards usage command printing. -# This command prints all boards in the system in the following cases: -# - User specifies an invalid BOARD -# - User invokes ' boards' target -list(TRANSFORM ARCH_ROOT PREPEND "--arch-root=" OUTPUT_VARIABLE arch_root_args) -list(TRANSFORM BOARD_ROOT PREPEND "--board-root=" OUTPUT_VARIABLE board_root_args) - -set(list_boards_commands - COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/list_boards.py - ${arch_root_args} ${board_root_args} --arch-root=${ZEPHYR_BASE} -) - -if(NOT BOARD_DIR) - message("No board named '${BOARD}' found.\n\n" - "Please choose one of the following boards:\n" - ) - execute_process(${list_boards_commands}) - unset(CACHED_BOARD CACHE) - message(FATAL_ERROR "Invalid BOARD; see above.") +if(DEFINED BOARD_IDENTIFIER) + string(REGEX REPLACE "^/" "identifier: " board_message_identifier "${BOARD_IDENTIFIER}") + set(board_message "${board_message}, ${board_message_identifier}") endif() +message(STATUS "${board_message}") + add_custom_target(boards ${list_boards_commands} USES_TERMINAL) # Board extensions are enabled by default diff --git a/cmake/modules/configuration_files.cmake b/cmake/modules/configuration_files.cmake index 4f2e469ab79..e23110b88b7 100644 --- a/cmake/modules/configuration_files.cmake +++ b/cmake/modules/configuration_files.cmake @@ -77,8 +77,15 @@ zephyr_file(CONF_FILES ${APPLICATION_CONFIG_DIR}/boards DTS APP_BOARD_DTS SUFFIX zephyr_get(DTC_OVERLAY_FILE SYSBUILD LOCAL) if(NOT DEFINED DTC_OVERLAY_FILE) + zephyr_build_string(board_overlay_strings + BOARD ${BOARD} + BOARD_IDENTIFIER ${BOARD_IDENTIFIER} + MERGE + ) + list(TRANSFORM board_overlay_strings APPEND ".overlay") + zephyr_file(CONF_FILES ${APPLICATION_CONFIG_DIR} DTS DTC_OVERLAY_FILE - NAMES "${APP_BOARD_DTS};${BOARD}.overlay;app.overlay" SUFFIX ${FILE_SUFFIX}) + NAMES "${APP_BOARD_DTS};${board_overlay_strings};app.overlay" SUFFIX ${FILE_SUFFIX}) endif() set(DTC_OVERLAY_FILE ${DTC_OVERLAY_FILE} CACHE STRING "If desired, you can \ diff --git a/cmake/modules/dts.cmake b/cmake/modules/dts.cmake index 23659c18692..bf19e602f6d 100644 --- a/cmake/modules/dts.cmake +++ b/cmake/modules/dts.cmake @@ -122,11 +122,26 @@ set(DTS_CMAKE ${PROJECT_BINARY_DIR}/dts.cmake) # modules. set(VENDOR_PREFIXES dts/bindings/vendor-prefixes.txt) -set_ifndef(DTS_SOURCE ${BOARD_DIR}/${BOARD}.dts) +if(NOT DEFINED DTS_SOURCE) + zephyr_build_string(dts_board_string BOARD ${BOARD} BOARD_IDENTIFIER ${BOARD_IDENTIFIER} MERGE) + foreach(str ${dts_board_string}) + if(EXISTS ${BOARD_DIR}/${str}.dts) + set(DTS_SOURCE ${BOARD_DIR}/${str}.dts) + break() + endif() + endforeach() +endif() + if(EXISTS ${DTS_SOURCE}) # We found a devicetree. Check for a board revision overlay. - if(DEFINED BOARD_REVISION AND EXISTS ${BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.overlay) - list(APPEND DTS_SOURCE ${BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.overlay) + if(DEFINED BOARD_REVISION) + zephyr_build_string(dts_board_string BOARD ${BOARD} + BOARD_IDENTIFIER ${BOARD_IDENTIFIER} + BOARD_REVISION ${BOARD_REVISION} + ) + if(EXISTS ${BOARD_DIR}/${dts_board_string}.overlay) + list(APPEND DTS_SOURCE ${BOARD_DIR}/${dts_board_string}.overlay) + endif() endif() else() # If we don't have a devicetree, provide an empty stub diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index e636a2cb473..4e8f454711b 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -1510,18 +1510,38 @@ endfunction() # # This is a common function to ensure that build strings are always created # in a uniform way. +# A single string is returned containing the full build string constructed from +# all arguments. +# +# When MERGE is supplied a list of build strings will be returned with the full +# build string as first item in the list. +# The full order of build strings returned in the list will be: +# - Full build string, including identifier and revision +# - Build string with board variants removed in addition +# - Build string with cpuset removed in addition +# - Build string with soc removed in addition +# +# If BUILD is supplied, then build type will be appended to each entry in the +# list above. +# If REVISION is supplied or obtained as system wide setting a build string +# with the sanitized revision string will be added in addition to the +# non-revisioned entry for each entry. # # Usage: # zephyr_build_string( # BOARD +# [BOARD_IDENTIFIER ] # [BOARD_REVISION ] # [BUILD ] +# [MERGE [REVERSE]] # ) # # : Output variable where the build string will be returned. # BOARD : Board name to use when creating the build string. # BOARD_REVISION : Board revision to use when creating the build string. # BUILD : Build type to use when creating the build string. +# MERGE: Return a list of build identifiers instead of a single build string. +# REVERSE: Reverse the list before returning it. # # Examples # calling @@ -1532,10 +1552,20 @@ endfunction() # zephyr_build_string(build_string BOARD alpha BOARD_REVISION 1.0.0 BUILD debug) # will return the string `alpha_1_0_0_debug` in `build_string` parameter. # +# calling +# zephyr_build_string(build_string BOARD alpha BOARD_IDENTIFIER /soc/bar) +# will return the string `alpha_soc_bar` in `build_string` parameter. +# +# calling +# zephyr_build_string(build_string BOARD alpha BOARD_REVISION 1.0.0 BOARD_IDENTIFIER /soc/bar MERGE) +# will return a list of the following strings +# `alpha_soc_bar_1_0_0;alpha_soc_bar;alpha_soc_1_0_0;alpha_soc;alpha_1_0_0;alpha` in `build_string` parameter. +# function(zephyr_build_string outvar) - set(single_args BOARD BOARD_REVISION BUILD) + set(options MERGE REVERSE) + set(single_args BOARD BOARD_IDENTIFIER BOARD_REVISION BUILD) - cmake_parse_arguments(BUILD_STR "" "${single_args}" "" ${ARGN}) + cmake_parse_arguments(BUILD_STR "${options}" "${single_args}" "" ${ARGN}) if(BUILD_STR_UNPARSED_ARGUMENTS) message(FATAL_ERROR "zephyr_build_string(${ARGV0} ...) given unknown arguments:" @@ -1550,15 +1580,37 @@ function(zephyr_build_string outvar) ) endif() - set(${outvar} ${BUILD_STR_BOARD}) + if(DEFINED BUILD_STR_BOARD_IDENTIFIER AND NOT BUILD_STR_BOARD) + message(FATAL_ERROR + "zephyr_build_string(${ARGV0} BOARD_IDENTIFIER ${BUILD_STR_BOARD_IDENTIFIER} ...)" + " given without BOARD argument, please specify BOARD" + ) + endif() + + string(REPLACE "/" ";" str_segment_list "${BUILD_STR_BOARD}${BUILD_STR_BOARD_IDENTIFIER}") + string(REPLACE "." "_" revision_string "${BUILD_STR_BOARD_REVISION}") + + string(JOIN "_" ${outvar} ${str_segment_list} ${revision_string} ${BUILD_STR_BUILD}) - if(DEFINED BUILD_STR_BOARD_REVISION) - string(REPLACE "." "_" revision_string ${BUILD_STR_BOARD_REVISION}) - set(${outvar} "${${outvar}}_${revision_string}") + if(BUILD_STR_MERGE) + if(DEFINED BUILD_STR_BOARD_REVISION) + string(JOIN "_" variant_string ${str_segment_list} ${BUILD_STR_BUILD}) + list(APPEND ${outvar} "${variant_string}") + endif() + list(POP_BACK str_segment_list) + while(NOT str_segment_list STREQUAL "") + if(DEFINED BUILD_STR_BOARD_REVISION) + string(JOIN "_" variant_string ${str_segment_list} ${revision_string} ${BUILD_STR_BUILD}) + list(APPEND ${outvar} "${variant_string}") + endif() + string(JOIN "_" variant_string ${str_segment_list} ${BUILD_STR_BUILD}) + list(APPEND ${outvar} "${variant_string}") + list(POP_BACK str_segment_list) + endwhile() endif() - if(BUILD_STR_BUILD) - set(${outvar} "${${outvar}}_${BUILD_STR_BUILD}") + if(BUILD_STR_REVERSE) + list(REVERSE ${outvar}) endif() # This updates the provided outvar in parent scope (callers scope) @@ -2362,7 +2414,7 @@ endfunction() # Usage: # print(BOARD) # -# will print: "BOARD: nrf52dk_nrf52832" +# will print: "BOARD: nrf52dk" function(print arg) message(STATUS "${arg}: ${${arg}}") endfunction() @@ -2436,6 +2488,7 @@ endfunction() # files are returned. Configuration files will be: # - DTS: Overlay files (.overlay) # - Kconfig: Config fragments (.conf) +# - defconfig: defconfig files (_defconfig) # The conf file search will return existing configuration # files for the current board. # CONF_FILES takes the following additional arguments: @@ -2454,6 +2507,7 @@ endfunction() # # DTS : List to append DTS overlay files in to # KCONF : List to append Kconfig fragment files in to +# DEFCONF : List to append _defconfig files in to # BUILD : Build type to include for search. # For example: # BUILD debug, will look for _debug.conf @@ -2477,7 +2531,7 @@ Please provide one of following: APPLICATION_ROOT, CONF_FILES") set(single_args APPLICATION_ROOT) elseif(${ARGV0} STREQUAL CONF_FILES) set(options REQUIRED) - set(single_args BOARD BOARD_REVISION DTS KCONF BUILD SUFFIX) + set(single_args BOARD BOARD_REVISION BOARD_IDENTIFIER DTS KCONF DEFCONFIG BUILD SUFFIX) set(multi_args CONF_FILES NAMES) endif() @@ -2535,24 +2589,23 @@ Relative paths are only allowed with `-D${ARGV1}=`") if(DEFINED BOARD_REVISION) set(FILE_BOARD_REVISION ${BOARD_REVISION}) endif() + + if(DEFINED BOARD_IDENTIFIER) + set(FILE_BOARD_IDENTIFIER ${BOARD_IDENTIFIER}) + endif() endif() if(FILE_NAMES) set(dts_filename_list ${FILE_NAMES}) set(kconf_filename_list ${FILE_NAMES}) else() - zephyr_build_string(filename - BOARD ${FILE_BOARD} - BUILD ${FILE_BUILD} - ) - set(filename_list ${filename}) - - zephyr_build_string(filename + zephyr_build_string(filename_list BOARD ${FILE_BOARD} BOARD_REVISION ${FILE_BOARD_REVISION} + BOARD_IDENTIFIER ${FILE_BOARD_IDENTIFIER} BUILD ${FILE_BUILD} + MERGE REVERSE ) - list(APPEND filename_list ${filename}) list(REMOVE_DUPLICATES filename_list) set(dts_filename_list ${filename_list}) list(TRANSFORM dts_filename_list APPEND ".overlay") @@ -2636,6 +2689,19 @@ Relative paths are only allowed with `-D${ARGV1}=`") message(DEPRECATION "prj_.conf was deprecated after Zephyr 3.5," " you should switch to using -DFILE_SUFFIX instead") endif() + + if(FILE_DEFCONFIG) + foreach(path ${FILE_CONF_FILES}) + foreach(filename ${filename_list}) + if(EXISTS ${path}/${filename}_defconfig) + list(APPEND ${FILE_DEFCONFIG} ${path}/${filename}_defconfig) + endif() + endforeach() + endforeach() + + # This updates the provided list in parent scope (callers scope) + set(${FILE_DEFCONFIG} ${${FILE_DEFCONFIG}} PARENT_SCOPE) + endif() endif() endfunction() diff --git a/cmake/modules/hwm_v2.cmake b/cmake/modules/hwm_v2.cmake new file mode 100644 index 00000000000..38af4083fb1 --- /dev/null +++ b/cmake/modules/hwm_v2.cmake @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023, Nordic Semiconductor ASA + +# This CMake module works together with the list_hardware.py script to obtain +# all archs and SoC implementations defined in the Zephyr build system. +# +# The result from list_hardware.py is then used to generate Kconfig files for +# the build system. +# +# The following files are generated in '/soc' +# - Kconfig.defconfig: Contains references to SoC defconfig files for Zephyr integration. +# - Kconfig: Contains references to regular SoC Kconfig files for Zephyr integration. +# - Kconfig.soc: Contains references to generic SoC Kconfig files. +# +# The following file is generated in '/arch' +# - Kconfig: Contains references to regular arch Kconfig files for Zephyr integration. + +include_guard(GLOBAL) + +if(NOT HWMv2) + return() +endif() + +# Internal helper function for creation of Kconfig files. +function(kconfig_gen bin_dir file dirs) + file(MAKE_DIRECTORY "${bin_dir}") + set(kconfig_file ${bin_dir}/${file}) + foreach(dir ${dirs}) + cmake_path(CONVERT "${dir}" TO_CMAKE_PATH_LIST dir) + file(APPEND ${kconfig_file} "osource \"${dir}/${file}\"\n") + endforeach() +endfunction() + +# 'SOC_ROOT' and 'ARCH_ROOT' are prioritized lists of directories where their +# implementations may be found. It always includes ${ZEPHYR_BASE}/[arch|soc] +# at the lowest priority. +list(APPEND SOC_ROOT ${ZEPHYR_BASE}) +list(APPEND ARCH_ROOT ${ZEPHYR_BASE}) + +list(TRANSFORM ARCH_ROOT PREPEND "--arch-root=" OUTPUT_VARIABLE arch_root_args) +list(TRANSFORM SOC_ROOT PREPEND "--soc-root=" OUTPUT_VARIABLE soc_root_args) + +execute_process(COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/list_hardware.py + ${arch_root_args} ${soc_root_args} + --archs --socs + --cmakeformat={TYPE}\;{NAME}\;{DIR}\;{HWM} + OUTPUT_VARIABLE ret_hw + ERROR_VARIABLE err_hw + RESULT_VARIABLE ret_val +) +if(ret_val) + message(FATAL_ERROR "Error listing hardware.\nError message: ${err_hw}") +endif() + +set(kconfig_soc_source_dir) + +while(TRUE) + string(FIND "${ret_hw}" "\n" idx REVERSE) + math(EXPR start "${idx} + 1") + string(SUBSTRING "${ret_hw}" ${start} -1 line) + string(SUBSTRING "${ret_hw}" 0 ${idx} ret_hw) + + cmake_parse_arguments(HWM "" "TYPE" "" ${line}) + if(HWM_TYPE STREQUAL "arch") + cmake_parse_arguments(ARCH_V2 "" "NAME;DIR" "" ${line}) + + list(APPEND kconfig_arch_source_dir "${ARCH_V2_DIR}") + list(APPEND ARCH_V2_NAME_LIST ${ARCH_V2_NAME}) + string(TOUPPER "${ARCH_V2_NAME}" ARCH_V2_NAME_UPPER) + set(ARCH_V2_${ARCH_V2_NAME_UPPER}_DIR ${ARCH_V2_DIR}) + elseif(HWM_TYPE MATCHES "^soc|^series|^family") + cmake_parse_arguments(SOC_V2 "" "NAME;DIR;HWM" "" ${line}) + + list(APPEND kconfig_soc_source_dir "${SOC_V2_DIR}") + + if(HWM_TYPE STREQUAL "soc") + set(setting_name SOC_${SOC_V2_NAME}_DIR) + else() + set(setting_name SOC_${HWM_TYPE}_${SOC_V2_NAME}_DIR) + endif() + # We support both SOC_foo_DIR and SOC_FOO_DIR. + set(${setting_name} ${SOC_V2_DIR}) + string(TOUPPER ${setting_name} setting_name) + set(${setting_name} ${SOC_V2_DIR}) + endif() + + if(idx EQUAL -1) + break() + endif() +endwhile() +list(REMOVE_DUPLICATES kconfig_soc_source_dir) + +# Support multiple ARCH_ROOT and SOC_ROOT +set(arch_kconfig_file Kconfig) +set(soc_defconfig_file Kconfig.defconfig) +set(soc_zephyr_file Kconfig) +set(soc_kconfig_file Kconfig.soc) +set(arch_kconfig_header "# Load arch Kconfig descriptions.\n") +set(defconfig_header "# Load Zephyr SoC Kconfig defconfig.\n") +set(soc_zephyr_header "# Load Zephyr SoC Kconfig descriptions.\n") +set(soc_kconfig_header "# Load SoC Kconfig descriptions.\n") +file(WRITE ${KCONFIG_BINARY_DIR}/arch/${arch_kconfig_file} "${arch_kconfig_header}") +file(WRITE ${KCONFIG_BINARY_DIR}/soc/${soc_defconfig_file} "${defconfig_header}") +file(WRITE ${KCONFIG_BINARY_DIR}/soc/${soc_zephyr_file} "${soc_zephyr_header}") +file(WRITE ${KCONFIG_BINARY_DIR}/soc/${soc_kconfig_file} "${soc_kconfig_header}") + +kconfig_gen("${KCONFIG_BINARY_DIR}/arch" "${arch_kconfig_file}" "${kconfig_arch_source_dir}") +kconfig_gen("${KCONFIG_BINARY_DIR}/soc" "${soc_defconfig_file}" "${kconfig_soc_source_dir}") +kconfig_gen("${KCONFIG_BINARY_DIR}/soc" "${soc_zephyr_file}" "${kconfig_soc_source_dir}") +kconfig_gen("${KCONFIG_BINARY_DIR}/soc" "${soc_kconfig_file}" "${kconfig_soc_source_dir}") + +# Clear variables created by cmake_parse_arguments +unset(SOC_V2_NAME) +unset(SOC_V2_DIR) +unset(SOC_V2_HWM) +unset(ARCH_V2_NAME) +unset(ARCH_V2_DIR) diff --git a/cmake/modules/kconfig.cmake b/cmake/modules/kconfig.cmake index f355bf2beb5..ae11892750a 100644 --- a/cmake/modules/kconfig.cmake +++ b/cmake/modules/kconfig.cmake @@ -22,23 +22,30 @@ set_ifndef(KCONFIG_NAMESPACE "CONFIG") set_ifndef(KCONFIG_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}/Kconfig) file(MAKE_DIRECTORY ${KCONFIG_BINARY_DIR}) -# Support multiple SOC_ROOT, remove ZEPHYR_BASE as that is always sourced. -set(kconfig_soc_root ${SOC_ROOT}) -list(REMOVE_ITEM kconfig_soc_root ${ZEPHYR_BASE}) -set(OPERATION WRITE) -foreach(root ${kconfig_soc_root}) - file(${OPERATION} ${KCONFIG_BINARY_DIR}/Kconfig.soc.defconfig - "osource \"${root}/soc/$(ARCH)/*/Kconfig.defconfig\"\n" - ) - file(${OPERATION} ${KCONFIG_BINARY_DIR}/Kconfig.soc - "osource \"${root}/soc/$(ARCH)/*/Kconfig.soc\"\n" - ) - file(${OPERATION} ${KCONFIG_BINARY_DIR}/Kconfig.soc.arch - "osource \"${root}/soc/$(ARCH)/Kconfig\"\n" - "osource \"${root}/soc/$(ARCH)/*/Kconfig\"\n" - ) - set(OPERATION APPEND) -endforeach() +if(HWMv1) + # Support multiple SOC_ROOT + file(MAKE_DIRECTORY ${KCONFIG_BINARY_DIR}/soc) + set(kconfig_soc_root ${BOARD_ROOT}) + list(REMOVE_ITEM kconfig_soc_root ${ZEPHYR_BASE}) + set(soc_defconfig_file ${KCONFIG_BINARY_DIR}/soc/Kconfig.defconfig) + + # This loads Zephyr base SoC root defconfigs + file(WRITE ${soc_defconfig_file} "osource \"soc/soc_legacy/$(ARCH)/*/Kconfig.defconfig\"\n") + + set(OPERATION WRITE) + foreach(root ${kconfig_soc_root}) + file(APPEND ${soc_defconfig_file} + "osource \"${root}/soc/soc_legacy/$(ARCH)/*/Kconfig.defconfig\"\n") + file(${OPERATION} ${KCONFIG_BINARY_DIR}/soc/Kconfig.soc.choice + "osource \"${root}/soc/soc_legacy/$(ARCH)/*/Kconfig.soc\"\n" + ) + file(${OPERATION} ${KCONFIG_BINARY_DIR}/soc/Kconfig.soc.arch + "osource \"${root}/soc/soc_legacy/$(ARCH)/Kconfig\"\n" + "osource \"${root}/soc/soc_legacy/$(ARCH)/*/Kconfig\"\n" + ) + set(OPERATION APPEND) + endforeach() +endif() # Support multiple shields in BOARD_ROOT, remove ZEPHYR_BASE as that is always sourced. set(kconfig_board_root ${BOARD_ROOT}) @@ -67,10 +74,23 @@ else() set(KCONFIG_ROOT ${ZEPHYR_BASE}/Kconfig) endif() -set_ifndef(BOARD_DEFCONFIG ${BOARD_DIR}/${BOARD}_defconfig) -if((DEFINED BOARD_REVISION) AND EXISTS ${BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.conf) - set_ifndef(BOARD_REVISION_CONFIG ${BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.conf) +if(NOT DEFINED BOARD_DEFCONFIG) + zephyr_file(CONF_FILES ${BOARD_DIR} DEFCONFIG BOARD_DEFCONFIG) endif() + +if(DEFINED BOARD_REVISION) + zephyr_build_string(config_board_string + BOARD ${BOARD} + BOARD_IDENTIFIER ${BOARD_IDENTIFIER} + BOARD_REVISION ${BOARD_REVISION} + ) + set(board_rev_file ${config_board_string}) + if(EXISTS ${BOARD_DIR}/${board_rev_file}.conf) + message(DEPRECATION "Use of '${board_rev_file}.conf' is deprecated, please switch to '${board_rev_file}_defconfig'") + set_ifndef(BOARD_REVISION_CONFIG ${BOARD_DIR}/${board_rev_file}.conf) + endif() +endif() + set(DOTCONFIG ${PROJECT_BINARY_DIR}/.config) set(PARSED_KCONFIG_SOURCES_TXT ${PROJECT_BINARY_DIR}/kconfig/sources.txt) @@ -137,12 +157,11 @@ set(COMMON_KCONFIG_ENV_SETTINGS APP_VERSION_TWEAK_STRING=${APP_VERSION_TWEAK_STRING} CONFIG_=${KCONFIG_NAMESPACE}_ KCONFIG_CONFIG=${DOTCONFIG} - # Set environment variables so that Kconfig can prune Kconfig source - # files for other architectures - ARCH=${ARCH} - ARCH_DIR=${ARCH_DIR} BOARD_DIR=${BOARD_DIR} + BOARD=${BOARD} BOARD_REVISION=${BOARD_REVISION} + BOARD_IDENTIFIER=${BOARD_IDENTIFIER} + HWM_SCHEME=${HWM} KCONFIG_BINARY_DIR=${KCONFIG_BINARY_DIR} APPLICATION_SOURCE_DIR=${APPLICATION_SOURCE_DIR} ZEPHYR_TOOLCHAIN_VARIANT=${ZEPHYR_TOOLCHAIN_VARIANT} @@ -154,6 +173,21 @@ set(COMMON_KCONFIG_ENV_SETTINGS ${ZEPHYR_KCONFIG_MODULES_DIR} ) +if(HWMv1) + list(APPEND COMMON_KCONFIG_ENV_SETTINGS + ARCH=${ARCH} + ARCH_DIR=${ARCH_DIR} + ) +else() + # For HWMv2 we should in future generate a Kconfig.arch.v2 which instead + # glob-sources all arch roots, but for Zephyr itself, the current approach is + # sufficient. + list(APPEND COMMON_KCONFIG_ENV_SETTINGS + ARCH=* + ARCH_DIR=${ZEPHYR_BASE}/arch + ) +endif() + # Allow out-of-tree users to add their own Kconfig python frontend # targets by appending targets to the CMake list # 'EXTRA_KCONFIG_TARGETS' and setting variables named diff --git a/cmake/modules/pre_dt.cmake b/cmake/modules/pre_dt.cmake index b19fd7f7fb5..4e062b2b970 100644 --- a/cmake/modules/pre_dt.cmake +++ b/cmake/modules/pre_dt.cmake @@ -62,6 +62,14 @@ function(pre_dt_module_run) # Finalize DTS_ROOT. list(REMOVE_DUPLICATES DTS_ROOT) + if(HWMv1) + set(arch_include dts/${ARCH}) + else() + foreach(arch ${ARCH_V2_NAME_LIST}) + list(APPEND arch_include dts/${arch}) + endforeach() + endif() + # Finalize DTS_ROOT_SYSTEM_INCLUDE_DIRS. set(DTS_ROOT_SYSTEM_INCLUDE_DIRS) foreach(dts_root ${DTS_ROOT}) @@ -69,7 +77,7 @@ function(pre_dt_module_run) include include/zephyr dts/common - dts/${ARCH} + ${arch_include} dts ) get_filename_component(full_path ${dts_root}/${dts_root_path} REALPATH) diff --git a/cmake/modules/soc.cmake b/cmake/modules/soc.cmake deleted file mode 100644 index 5253620b6b9..00000000000 --- a/cmake/modules/soc.cmake +++ /dev/null @@ -1,71 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021, Nordic Semiconductor ASA - -# Configure SoC settings based on Kconfig settings and SoC root. -# -# This CMake module will set the following variables in the build system based -# on Kconfig settings and selected SoC. -# -# If no implementation is available for the selected SoC an error will be raised. -# -# Outcome: -# The following variables will be defined when this CMake module completes: -# -# - SOC_NAME: Name of the SoC in use, identical to CONFIG_SOC -# - SOC_SERIES: Name of the SoC series in use, identical to CONFIG_SOC_SERIES -# - SOC_FAMILY: Name of the SoC family, identical to CONFIG_SOC_FAMILY -# - SOC_PATH: Path fragment defined by either SOC_NAME or SOC_FAMILY/SOC_SERIES. -# - SOC_DIR: Directory containing the SoC implementation -# - SOC_ROOT: SOC_ROOT with ZEPHYR_BASE appended -# -# Variable dependencies: -# - SOC_ROOT: CMake list of SoC roots containing SoC implementations -# -# Variables set by this module and not mentioned above are considered internal -# use only and may be removed, renamed, or re-purposed without prior notice. - -include_guard(GLOBAL) - -include(kconfig) - -# 'SOC_ROOT' is a prioritized list of directories where socs may be -# found. It always includes ${ZEPHYR_BASE}/soc at the lowest priority. -list(APPEND SOC_ROOT ${ZEPHYR_BASE}) - -set(SOC_NAME ${CONFIG_SOC}) -set(SOC_SERIES ${CONFIG_SOC_SERIES}) -set(SOC_TOOLCHAIN_NAME ${CONFIG_SOC_TOOLCHAIN_NAME}) -set(SOC_FAMILY ${CONFIG_SOC_FAMILY}) - -if("${SOC_SERIES}" STREQUAL "") - set(SOC_PATH ${SOC_NAME}) -else() - set(SOC_PATH ${SOC_FAMILY}/${SOC_SERIES}) -endif() - -# Use SOC to search for a 'CMakeLists.txt' file. -# e.g. zephyr/soc/xtensa/intel_adsp/CMakeLists.txt. -foreach(root ${SOC_ROOT}) - # Check that the root looks reasonable. - if(NOT IS_DIRECTORY "${root}/soc") - message(WARNING "\nSOC_ROOT element(s) without a 'soc' subdirectory: -${root} -Hints: - - if your SoC family directory is '/foo/bar/soc//my_soc_family', then add '/foo/bar' to SOC_ROOT, not the entire SoC family path - - if in doubt, use absolute paths\n") - endif() - - if(EXISTS ${root}/soc/${ARCH}/${SOC_PATH}) - set(SOC_DIR ${root}/soc) - break() - endif() -endforeach() - -if(NOT SOC_DIR) - message(FATAL_ERROR "Could not find SOC=${SOC_NAME} for BOARD=${BOARD},\n" - "please check your installation.\n" - "SOC roots searched:\n" - "${SOC_ROOT}\n" - ) -endif() diff --git a/cmake/modules/soc_v1.cmake b/cmake/modules/soc_v1.cmake new file mode 100644 index 00000000000..1bba9536c0c --- /dev/null +++ b/cmake/modules/soc_v1.cmake @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021, Nordic Semiconductor ASA + +# Configure SoC settings based on Kconfig settings and SoC root. +# +# This CMake module will set the following variables in the build system based +# on Kconfig settings and selected SoC. +# +# If no implementation is available for the selected SoC an error will be raised. +# +# Outcome: +# The following variables will be defined when this CMake module completes: +# +# - SOC_NAME: Name of the SoC in use, identical to CONFIG_SOC +# - SOC_SERIES: Name of the SoC series in use, identical to CONFIG_SOC_SERIES +# - SOC_FAMILY: Name of the SoC family, identical to CONFIG_SOC_FAMILY +# - SOC_PATH: Path fragment defined by either SOC_NAME or SOC_FAMILY/SOC_SERIES. +# - SOC_DIR: Directory containing the SoC implementation +# - SOC_ROOT: SOC_ROOT with ZEPHYR_BASE appended +# +# Variable dependencies: +# - SOC_ROOT: CMake list of SoC roots containing SoC implementations +# +# Variables set by this module and not mentioned above are considered internal +# use only and may be removed, renamed, or re-purposed without prior notice. + +include_guard(GLOBAL) + +include(kconfig) + +if(HWMv1) + # 'SOC_ROOT' is a prioritized list of directories where socs may be + # found. It always includes ${ZEPHYR_BASE}/soc at the lowest priority. + list(APPEND SOC_ROOT ${ZEPHYR_BASE}) + + set(SOC_NAME ${CONFIG_SOC}) + set(SOC_SERIES ${CONFIG_SOC_SERIES}) + set(SOC_TOOLCHAIN_NAME ${CONFIG_SOC_TOOLCHAIN_NAME}) + set(SOC_FAMILY ${CONFIG_SOC_FAMILY}) + + if("${SOC_SERIES}" STREQUAL "") + set(SOC_PATH ${SOC_NAME}) + else() + set(SOC_PATH ${SOC_FAMILY}/${SOC_SERIES}) + endif() + + # Use SOC to search for a 'CMakeLists.txt' file. + # e.g. zephyr/soc/xtensa/intel_adsp/CMakeLists.txt. + foreach(root ${SOC_ROOT}) + # Check that the root looks reasonable. + if(NOT IS_DIRECTORY "${root}/soc") + message(WARNING "\nSOC_ROOT element(s) without a 'soc' subdirectory: + ${root} + Hints: + - if your SoC family directory is '/foo/bar/soc//my_soc_family', then add '/foo/bar' to SOC_ROOT, not the entire SoC family path + - if in doubt, use absolute paths\n") + endif() + + if(EXISTS ${root}/soc/${ARCH}/${SOC_PATH}) + set(SOC_DIR ${root}/soc) + break() + elseif(EXISTS ${root}/soc/soc_legacy/${ARCH}/${SOC_PATH}) + set(SOC_DIR ${root}/soc/soc_legacy) + break() + endif() + endforeach() + + if(NOT SOC_DIR) + message(FATAL_ERROR "Could not find SOC=${SOC_NAME} for BOARD=${BOARD},\n" + "please check your installation.\n" + "SOC roots searched:\n" + "${SOC_ROOT}\n" + ) + endif() + + set(SOC_FULL_DIR ${SOC_DIR}/${ARCH}/${SOC_PATH}) +endif() diff --git a/cmake/modules/soc_v2.cmake b/cmake/modules/soc_v2.cmake new file mode 100644 index 00000000000..866958e1f80 --- /dev/null +++ b/cmake/modules/soc_v2.cmake @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021, Nordic Semiconductor ASA + +# Configure SoC settings based on Kconfig settings. +# +# This CMake module will set the following variables in the build system based +# on Kconfig settings for the selected SoC. +# +# Outcome: +# The following variables will be defined when this CMake module completes: +# +# - SOC_NAME: Name of the SoC in use, identical to CONFIG_SOC +# - SOC_SERIES: Name of the SoC series in use, identical to CONFIG_SOC_SERIES +# - SOC_FAMILY: Name of the SoC family, identical to CONFIG_SOC_FAMILY +# +# Variables set by this module and not mentioned above are considered internal +# use only and may be removed, renamed, or re-purposed without prior notice. + +include_guard(GLOBAL) + +include(kconfig) + +if(HWMv2) + set(SOC_NAME ${CONFIG_SOC}) + set(SOC_SERIES ${CONFIG_SOC_SERIES}) + set(SOC_TOOLCHAIN_NAME ${CONFIG_SOC_TOOLCHAIN_NAME}) + set(SOC_FAMILY ${CONFIG_SOC_FAMILY}) + set(SOC_V2_DIR ${SOC_${SOC_NAME}_DIR}) + set(SOC_FULL_DIR ${SOC_V2_DIR}) +endif() diff --git a/cmake/modules/unittest.cmake b/cmake/modules/unittest.cmake index 8853f5a5b0c..2551f41832a 100644 --- a/cmake/modules/unittest.cmake +++ b/cmake/modules/unittest.cmake @@ -4,7 +4,7 @@ cmake_minimum_required(VERSION 3.20.0) include(root) include(boards) -include(arch) +include(arch_v1) include(configuration_files) include(west) diff --git a/cmake/modules/zephyr_default.cmake b/cmake/modules/zephyr_default.cmake index 98a580c3a2d..7472331255b 100644 --- a/cmake/modules/zephyr_default.cmake +++ b/cmake/modules/zephyr_default.cmake @@ -96,7 +96,8 @@ list(APPEND zephyr_cmake_modules zephyr_module) list(APPEND zephyr_cmake_modules boards) list(APPEND zephyr_cmake_modules shields) list(APPEND zephyr_cmake_modules snippets) -list(APPEND zephyr_cmake_modules arch) +list(APPEND zephyr_cmake_modules arch_v1) +list(APPEND zephyr_cmake_modules hwm_v2) list(APPEND zephyr_cmake_modules configuration_files) list(APPEND zephyr_cmake_modules generated_file_directories) @@ -108,7 +109,9 @@ list(APPEND zephyr_cmake_modules "\${pre_dt_board}") # kconfig and dts should be available at the same time. list(APPEND zephyr_cmake_modules dts) list(APPEND zephyr_cmake_modules kconfig) -list(APPEND zephyr_cmake_modules soc) +list(APPEND zephyr_cmake_modules arch_v2) +list(APPEND zephyr_cmake_modules soc_v1) +list(APPEND zephyr_cmake_modules soc_v2) foreach(component ${SUB_COMPONENTS}) if(NOT ${component} IN_LIST zephyr_cmake_modules) diff --git a/doc/_extensions/zephyr/kconfig/__init__.py b/doc/_extensions/zephyr/kconfig/__init__.py index c4042e298ad..c268ac474f9 100644 --- a/doc/_extensions/zephyr/kconfig/__init__.py +++ b/doc/_extensions/zephyr/kconfig/__init__.py @@ -28,8 +28,10 @@ ${BASE_PATH}/modules/${MODULE_NAME}/Kconfig. """ +import argparse import json import os +import re import sys from itertools import chain from pathlib import Path @@ -61,6 +63,8 @@ sys.path.insert(0, str(KCONFIGLIB)) import kconfiglib +import list_boards +import list_hardware import zephyr_module @@ -83,6 +87,47 @@ def kconfig_load(app: Sphinx) -> Tuple[kconfiglib.Kconfig, Dict[str, str]]: with open(Path(td) / "Kconfig.dts", "w") as f: f.write(kconfig) + (Path(td) / 'soc').mkdir(exist_ok=True) + root_args = argparse.Namespace(**{'soc_roots': [Path(ZEPHYR_BASE)]}) + v2_systems = list_hardware.find_v2_systems(root_args) + + soc_folders = {soc.folder for soc in v2_systems.get_socs()} + with open(Path(td) / "soc" / "Kconfig.defconfig", "w") as f: + f.write('') + + with open(Path(td) / "soc" / "Kconfig.soc", "w") as f: + for folder in soc_folders: + f.write('source "' + os.path.join(folder, 'Kconfig.soc') + '"\n') + + with open(Path(td) / "soc" / "Kconfig", "w") as f: + for folder in soc_folders: + f.write('osource "' + os.path.join(folder, 'Kconfig') + '"\n') + + (Path(td) / 'arch').mkdir(exist_ok=True) + root_args = argparse.Namespace(**{'arch_roots': [Path(ZEPHYR_BASE)], 'arch': None}) + v2_archs = list_hardware.find_v2_archs(root_args) + kconfig = "" + for arch in v2_archs['archs']: + kconfig += 'source "' + str(Path(arch['path']) / 'Kconfig') + '"\n' + with open(Path(td) / "arch" / "Kconfig", "w") as f: + f.write(kconfig) + + (Path(td) / 'boards').mkdir(exist_ok=True) + root_args = argparse.Namespace(**{'board_roots': [Path(ZEPHYR_BASE)], + 'soc_roots': [Path(ZEPHYR_BASE)], 'board': None}) + v2_boards = list_boards.find_v2_boards(root_args) + + with open(Path(td) / "boards" / "Kconfig.boards", "w") as f: + for board in v2_boards: + board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", board.name).upper() + f.write('config ' + board_str + '\n') + f.write('\t bool\n') + for identifier in list_boards.board_v2_identifiers(board): + board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", identifier).upper() + f.write('config ' + board_str + '\n') + f.write('\t bool\n') + f.write('source "' + os.path.join(board.dir, 'Kconfig.') + board.name + '"\n\n') + # base environment os.environ["ZEPHYR_BASE"] = str(ZEPHYR_BASE) os.environ["srctree"] = str(ZEPHYR_BASE) @@ -91,8 +136,11 @@ def kconfig_load(app: Sphinx) -> Tuple[kconfiglib.Kconfig, Dict[str, str]]: # include all archs and boards os.environ["ARCH_DIR"] = "arch" - os.environ["ARCH"] = "*" - os.environ["BOARD_DIR"] = "boards/*/*" + os.environ["ARCH"] = "[!v][!2]*" + os.environ["HWM_SCHEME"] = "v2" + + os.environ["BOARD"] = "boards" + os.environ["BOARD_DIR"] = str(Path(td) / "boards") # insert external Kconfigs to the environment module_paths = dict() diff --git a/doc/connectivity/bluetooth/autopts/autopts-win10.rst b/doc/connectivity/bluetooth/autopts/autopts-win10.rst index 54b609ef1fd..ff308261f44 100644 --- a/doc/connectivity/bluetooth/autopts/autopts-win10.rst +++ b/doc/connectivity/bluetooth/autopts/autopts-win10.rst @@ -116,7 +116,7 @@ Build the auto-pts tester app .. code-block:: - west build -p auto -b nrf52840dk_nrf52840 zephyr/tests/bluetooth/tester/ + west build -p auto -b nrf52840dk/nrf52840 zephyr/tests/bluetooth/tester/ You can display flashing options with: diff --git a/doc/develop/beyond-GSG.rst b/doc/develop/beyond-GSG.rst index 8f5361d8512..8c965877a43 100644 --- a/doc/develop/beyond-GSG.rst +++ b/doc/develop/beyond-GSG.rst @@ -163,8 +163,8 @@ supported by a CMake file with content like this: # Variable foo_BOARD_ALIAS=bar replaces BOARD=foo with BOARD=bar and # sets BOARD_ALIAS=foo in the CMake cache. - set(pca10028_BOARD_ALIAS nrf51dk_nrf51422) - set(pca10056_BOARD_ALIAS nrf52840dk_nrf52840) + set(pca10028_BOARD_ALIAS nrf51dk/nrf51822) + set(pca10056_BOARD_ALIAS nrf52840dk/nrf52840) set(k64f_BOARD_ALIAS frdm_k64f) set(sltb004a_BOARD_ALIAS efr32mg_sltb004a) diff --git a/doc/develop/flash_debug/nordic_segger.rst b/doc/develop/flash_debug/nordic_segger.rst index 918d0051aa2..92e2c31d5fc 100644 --- a/doc/develop/flash_debug/nordic_segger.rst +++ b/doc/develop/flash_debug/nordic_segger.rst @@ -63,7 +63,7 @@ Where ```` is either 1 for nRF51-based boards or 2 for nRF52-based boards nrfjprog --program outdir//zephyr.hex -f nrf5 -Where: ```` is the board name you used in the BOARD directive when building (for example nrf52dk_nrf52832) +Where: ```` is the board name you used in the BOARD directive when building (for example nrf52dk/nrf52832) and ```` is either 1 for nRF51-based boards or 2 for nRF52-based boards * Reset and start Zephyr: diff --git a/doc/develop/getting_started/index.rst b/doc/develop/getting_started/index.rst index c2974509ca8..39e68ba6a02 100644 --- a/doc/develop/getting_started/index.rst +++ b/doc/develop/getting_started/index.rst @@ -560,6 +560,17 @@ users. Users may also use the ``-p auto`` option, which will use heuristics to determine if a pristine build is required, such as when building another sample. +.. note:: + + A board may contain one or multiple SoCs, Also, each SoC may contain one or + more CPU clusters. + When building for such boards it is necessary to specify the SoC or CPU + cluster for which the sample must be built. + For example to build :zephyr:code-sample:`blinky` for the ``cpuapp`` core on + the :ref:`nRF5340DK ` the board must be provided as: + ``nrf5340dk/nrf5340/cpuapp``. Also read :ref:`board_and_identifiers` for more + details. + Flash the Sample **************** diff --git a/doc/develop/sca/sparse.rst b/doc/develop/sca/sparse.rst index 38b720d4448..4af699fc343 100644 --- a/doc/develop/sca/sparse.rst +++ b/doc/develop/sca/sparse.rst @@ -23,4 +23,4 @@ called with a ``-DZEPHYR_SCA_VARIANT=sparse`` parameter, e.g. .. code-block:: shell - west build -d hello -b intel_adsp_cavs25 zephyr/samples/hello_world -- -DZEPHYR_SCA_VARIANT=sparse + west build -d hello -b intel_adsp/cavs25 zephyr/samples/hello_world -- -DZEPHYR_SCA_VARIANT=sparse diff --git a/doc/develop/test/coverage.rst b/doc/develop/test/coverage.rst index 60faffa1a90..5c86adda1b3 100644 --- a/doc/develop/test/coverage.rst +++ b/doc/develop/test/coverage.rst @@ -49,7 +49,7 @@ These steps will produce an HTML coverage report for a single application. 1. Build the code with CONFIG_COVERAGE=y. .. zephyr-app-commands:: - :board: mps2_an385 + :board: mps2/an385 :gen-args: -DCONFIG_COVERAGE=y -DCONFIG_COVERAGE_DUMP=y :goals: build :compact: diff --git a/doc/develop/test/twister.rst b/doc/develop/test/twister.rst index faa8c475b2d..f84fc73b99c 100644 --- a/doc/develop/test/twister.rst +++ b/doc/develop/test/twister.rst @@ -839,7 +839,7 @@ In this case you can run twister with the following options: .. code-block:: bash scripts/twister --device-testing --device-serial-pty "script.py" \ - -p intel_adsp_cavs25 -T tests/kernel + -p intel_adsp/cavs25 -T tests/kernel .. group-tab:: Windows @@ -923,7 +923,7 @@ devices, for example: Any options marked as ``unknown`` need to be changed and set with the correct values, in the above example the platform names, the products and the runners need to be replaced with the correct values corresponding to the connected hardware. -In this example we are using a reel_board and an nrf52840dk_nrf52840: +In this example we are using a reel_board and an nrf52840dk/nrf52840: .. tabs:: @@ -940,7 +940,7 @@ In this example we are using a reel_board and an nrf52840dk_nrf52840: baud: 9600 - connected: true id: 000683759358 - platform: nrf52840dk_nrf52840 + platform: nrf52840dk/nrf52840 product: J-Link runner: nrfjprog serial: /dev/cu.usbmodem0006837593581 @@ -959,7 +959,7 @@ In this example we are using a reel_board and an nrf52840dk_nrf52840: baud: 9600 - connected: true id: 000683759358 - platform: nrf52840dk_nrf52840 + platform: nrf52840dk/nrf52840 product: J-Link runner: nrfjprog serial: COM2 @@ -1008,7 +1008,7 @@ hardware map: - connected: true id: None - platform: intel_adsp_cavs25 + platform: intel_adsp/cavs25 product: None runner: intel_adsp serial_pty: path/to/script.py @@ -1029,7 +1029,7 @@ work. It is equivalent to following west and twister commands. west flash --remote-host remote_host_ip_addr --key /path/to/key.pem - twister -p intel_adsp_cavs25 --device-testing --device-serial-pty script.py + twister -p intel_adsp/cavs25 --device-testing --device-serial-pty script.py --west-flash="--remote-host=remote_host_ip_addr,--key=/path/to/key.pem" .. group-tab:: Windows @@ -1092,12 +1092,12 @@ example: fixtures: - gpio_loopback id: 000683290670 - notes: An nrf5340dk_nrf5340 is detected as an nrf52840dk_nrf52840 with no serial + notes: An nrf5340dk/nrf5340 is detected as an nrf52840dk/nrf52840 with no serial port, and three serial ports with an unknown platform. The board id of the serial ports is not the same as the board id of the development kit. If you regenerate this file you will need to update serial to reference the third port, and platform - to nrf5340dk_nrf5340_cpuapp or another supported board target. - platform: nrf52840dk_nrf52840 + to nrf5340dk/nrf5340/cpuapp or another supported board target. + platform: nrf52840dk/nrf52840 product: J-Link runner: jlink serial: null diff --git a/doc/hardware/porting/board_porting.rst b/doc/hardware/porting/board_porting.rst index 5be561aecb2..c45b2a7bb54 100644 --- a/doc/hardware/porting/board_porting.rst +++ b/doc/hardware/porting/board_porting.rst @@ -8,17 +8,78 @@ directory* with various files in it. Files in the board directory inherit support for at least one SoC and all of its features. Therefore, Zephyr must support your :term:`SoC` as well. +.. _board_and_identifiers: + +Board and board identifiers +*************************** + +A board may be a physical piece of hardware or an emulated board. +Furthermore a board may contain one or multiple SoCs. Also, each SoC may contain +one or multiple CPU clusters. A CPU cluster refers to a group of CPU cores. +Only CPU cores of same architecture can be in the same cluster. In the case +where a physical SoC considers a CPU cluster to contain CPU cores of different +architectures then those must be modelled as multiple clusters, where all CPU +cores within a cluster is having the same architecture. +It is possible to have only a single CPU core within a CPU cluster. + +It's possible to define variants for dedicated use-cases. +Examples of such use-cases are: + +- Variant which enables non-secure builds for SoCs containing a security + processor. +- Variant enabling / changing the type of RAM used in by the build. + +A ``/`` is used as separator between the board name and the following: +SoC, CPU cluster, and variant identifiers. + +If a board contains only a single core SoC, then the SoC can be omitted when +building. + +Let's say there is a board named ``plank`` with a single-core SoC ``soc1``. +The board including the identifier is: ``plank/soc1``. + +As ``plank`` is a single SoC board, then the following is sufficient: ``plank`` +to use as board when building. + +If ``plank`` defines board variants, then those are identified by appending the +``/`` name after the SoC, for example to build for the ``foo`` variant, +use: ``plank/soc1/foo``, and if omitting the SoC use: ``plank//foo``. +Here the double ``//`` indicates to the build system that the SoC has been +omitted. + +So to build hello world for ``plank``, variant ``foo``, you can do: + +.. code-block:: console + + west build -b plank//foo samples/hello_world + +When using multi-core SoCs, the CPU cluster is identified after the SoC +identifier. + +If ``soc1`` above has two cores, ``first`` and ``second``, then those are +identified as: ``plank/soc1/first`` and ``plank/soc1/second``. + +And similar to before, if the board has only a single SoC, the SoC can be +omitted, that is ``plank//first`` and ``plank//second`` is an identical short +form. + +.. _hw_support_hierarchy: + Boards, SoCs, etc. ****************** Zephyr's hardware support hierarchy has these layers, from most to least specific: -- Board: a particular CPU instance and its peripherals in a concrete hardware - specification +- Board: a specific board which usually corresponds to a physical board. + A board may contain multiple SoCs. + A build targets a specific CPU cluster on a board which has multiple + CPUs, be these in different SOCs or in a SOC with multiple AMP CPU + clusters. - SoC: the exact system on a chip the board's CPU is part of - SoC series: a smaller group of tightly related SoCs - SoC family: a wider group of SoCs with similar characteristics +- CPU Cluster: a cluster of one or more CPU cores. - CPU core: a particular CPU in an architecture - Architecture: an instruction set architecture @@ -34,39 +95,26 @@ You can visualize the hierarchy like this: Here are some examples. Notice how the SoC series and family levels are not always used. -.. list-table:: - :header-rows: 1 - - * - Board - - SoC - - SoC series - - SoC family - - CPU core - - Architecture - * - :ref:`nrf52dk_nrf52832 ` - - nRF52832 - - nRF52 - - Nordic nRF5 - - Arm Cortex-M4 - - Arm - * - :ref:`frdm_k64f ` - - MK64F12 - - Kinetis K6x - - NXP Kinetis - - Arm Cortex-M4 - - Arm - * - :ref:`stm32h747i_disco ` - - STM32H747XI - - STM32H7 - - STMicro STM32 - - Arm Cortex-M7 - - Arm - * - :ref:`rv32m1_vega_ri5cy ` - - RV32M1 - - (Not used) - - (Not used) - - RI5CY - - RISC-V +.. table:: + + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + | Board | Identifier | SoC | SoC Series | SoC family | CPU core | Architecture | + +============================================+=======================+=============+===============+===============+================+==============+ + | :ref:`nrf52dk ` | /nrf52832 | nRF52832 | nRF52 | Nordic nRF | Arm Cortex-M4 | Arm | + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + | :ref:`frdm_k64f ` | /mk64f12 | MK64F12 | Kinetis K6x | NXP Kinetis | Arm Cortex-M4 | Arm | + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + | :ref:`rv32m1_vega ` | /openisa_rv32m1/ri5cy | RV32M1 | (Not used) | (Not used) | RI5CY | RISC-V | + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + | :ref:`nrf5340dk ` | /nrf5340/cpuapp | nRF5340 | nRF53 | Nordic nRF | Arm Cortex-M33 | Arm | + | +-----------------------+-------------+---------------+---------------+----------------+--------------+ + | | /nrf5340/cpunet | nRF5340 | nRF53 | Nordic nRF | Arm Cortex-M33 | Arm | + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + | :ref:`mimx8mp_evk ` | /mimx8m/a53 | i.MX8M Plus | i.MXM8M A53 | NXP i.MX | Arm Cortex-A53 | Arm64 | + | +-----------------------+-------------+---------------+---------------+----------------+--------------+ + | | /mimx8m/m7 | i.MX8M Plus | i.MXM8MM M4 | NXP i.MX | Arm Cortex-M7 | Arm | + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + Make sure your SoC is supported ******************************* @@ -78,7 +126,7 @@ Start by making sure your SoC is supported by Zephyr. If it is, it's time to board documentation to find out for sure. - asking your SoC vendor -If you need to add SoC, CPU core, or even architecture support, this is the +If you need to add a SoC, CPU cluster, or even architecture support, this is the wrong page, but here is some general advice. Architecture @@ -107,7 +155,7 @@ Zephyr SoC support files are in architecture-specific subdirectories of When adding a new SoC family or series for a vendor that already has SoC support within Zephyr, please try to extract common functionality into shared files to avoid duplication. If there is no support for your vendor yet, you can -add it in a new directory ``zephyr/soc//``; please use +add it in a new directory ``zephyr/soc//``; please use self-explanatory directory names. .. _create-your-board-directory: @@ -123,52 +171,72 @@ You need to give your board a unique name. Run ``west boards`` for a list of names that are already taken, and pick something new. Let's say your board is called ``plank`` (please don't actually use that name). -Start by creating the board directory ``zephyr/boards//plank``, where -```` is your SoC's architecture subdirectory. (You don't have to put your +Start by creating the board directory ``zephyr/boards//plank``, where +```` is your vendor subdirectory. (You don't have to put your board directory in the zephyr repository, but it's the easiest way to get started. See :ref:`custom_board_definition` for documentation on moving your board directory to a separate repository once it's working.) +.. note:: + A ```` subdirectory is mandatory if contributing your board + to Zephyr, but if your board is placed in a local repo, then any folder + structure under ``/boards`` is permitted. + If the vendor is defined in the list in + :zephyr_file:`dts/bindings/vendor-prefixes.txt` then you must use + that vendor prefix as ````. ``others`` may be used as vendor prefix if + the vendor is not defined. + .. note:: The board directory name does not need to match the name of the board. Multiple boards can even defined be in one directory. - For example, for boards with multi-core SoC, a logical board might be created - for each core following the naming scheme `_`, with definitions - for all of these different boards defined inside the same directory. This and - similar schemes are common for upstream vendor boards. Your board directory should look like this: .. code-block:: none - boards//plank + boards//plank + ├── board.yml ├── board.cmake ├── CMakeLists.txt ├── doc │   ├── plank.png │   └── index.rst - ├── Kconfig.board + ├── Kconfig.plank ├── Kconfig.defconfig ├── plank_defconfig + ├── plank__defconfig ├── plank.dts + ├── plank_.dts └── plank.yaml Replace ``plank`` with your board's name, of course. The mandatory files are: -#. :file:`plank.dts`: a hardware description in :ref:`devicetree - ` format. This declares your SoC, connectors, and any - other hardware components such as LEDs, buttons, sensors, or communication - peripherals (USB, BLE controller, etc). +#. :file:`board.yml`: a YAML file describing the high-level meta data of the + boards such as the boards names, their SoCs, and variants. + CPU clusters for multi-core SoCs are not described in this file as they are + inherited from the SoC's YAML description. + +#. :file:`plank.dts` or :file:`plank_.dts`: a hardware description + in :ref:`devicetree ` format. This declares your SoC, connectors, + and any other hardware components such as LEDs, buttons, sensors, or + communication peripherals (USB, BLE controller, etc). + +#. :file:`Kconfig.plank`: the base software configuration for selecting SoC and + other board and SoC related settings. Kconfig settings outside of the board + and SoC tree must not be selected. To select general Zephyr Kconfig settings + the :file:`Kconfig` file must be used. -#. :file:`Kconfig.board`, :file:`Kconfig.defconfig`, :file:`plank_defconfig`: - software configuration in :ref:`kconfig` formats. This provides default - settings for software features and peripheral drivers. The optional files are: +- :file:`Kconfig`, :file:`Kconfig.defconfig` software configuration in + :ref:`kconfig` formats. This provides default settings for software features + and peripheral drivers. +- :file:`plank_defconfig` and :file:`plank__defconfig`: software + configuration in Kconfig ``.conf`` format. - :file:`board.cmake`: used for :ref:`flash-and-debug-support` - :file:`CMakeLists.txt`: if you need to add additional source files to your build. @@ -178,12 +246,70 @@ The optional files are: - :file:`plank.yaml`: a YAML file with miscellaneous metadata used by the :ref:`twister_script`. +Board identifiers of the form ``//`` are sanitized so +that ``/`` is replaced with ``_`` when used for filenames, for example: +``soc1/foo`` becomes ``soc1_foo`` when used in filenames. + +.. _board_description: + +Write your board YAML +********************* + +The board YAML file describes the board at a high level. +This includes the SoC, board variants, and board revisions. + +Detailed configurations, such as hardware description and configuration are done +in devicetree and Kconfig. + +The skeleton of the board YAML file is: + +.. code-block:: yaml + + board: + name: + vendor: + revision: + format: + default: + exact: + revisions: + - name: + - name: + ... + socs: + - name: + variants: + - name: + - name: + variants: + - name: + ... + - name: + ... + +It is possible to have multiple boards located in the board folder. +If multiple boards are placed in the same board folder, then the file +:file:`board.yml` must describe those in a list as: + +.. code-block:: yaml + + boards: + - name: + vendor: + ... + - name: + vendor: + ... + ... + + .. _default_board_configuration: Write your devicetree ********************* -The devicetree file :file:`boards//plank/plank.dts` describes your board +The devicetree file :file:`boards//plank/plank.dts` or +:file:`boards//plank/plank_.dts` describes your board hardware in the Devicetree Source (DTS) format (as usual, change ``plank`` to your board's name). If you're new to devicetree, see :ref:`devicetree-intro`. @@ -195,48 +321,59 @@ In general, :file:`plank.dts` should look like this: #include / { - model = "A human readable name"; - compatible = "yourcompany,plank"; - - chosen { - zephyr,console = &your_uart_console; - zephyr,sram = &your_memory_node; - /* other chosen settings for your hardware */ - }; - - /* - * Your board-specific hardware: buttons, LEDs, sensors, etc. - */ - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = < /* GPIO your LED is hooked up to */ >; - label = "LED 0"; - }; - /* ... other LEDs ... */ - }; - - buttons { - compatible = "gpio-keys"; - /* ... your button definitions ... */ - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; /* now you support the blinky sample! */ - /* other aliases go here */ - }; + model = "A human readable name"; + compatible = "yourcompany,plank"; + + chosen { + zephyr,console = &your_uart_console; + zephyr,sram = &your_memory_node; + /* other chosen settings for your hardware */ + }; + + /* + * Your board-specific hardware: buttons, LEDs, sensors, etc. + */ + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = < /* GPIO your LED is hooked up to */ >; + label = "LED 0"; + }; + /* ... other LEDs ... */ + }; + + buttons { + compatible = "gpio-keys"; + /* ... your button definitions ... */ + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; /* now you support the blinky sample! */ + /* other aliases go here */ + }; }; &some_peripheral_you_want_to_enable { /* like a GPIO or SPI controller */ - status = "okay"; + status = "okay"; }; &another_peripheral_you_want { - status = "okay"; + status = "okay"; }; +Only one ``.dts`` file will be used, and the most specific file which exists +will be used. + +This means that if both :file:`plank.dts` and :file:`plank_soc1_foo.dts` exist, +then when building for ``plank`` / ``plank/soc1``, then :file:`plank.dts` is +used. When building for ``plank//foo`` / ``plank/soc1/foo`` the +:file:`plank_soc1_foo.dts` is used. + +This allows board maintainers to write a base devicetree file for the board +or write specific devicetree files for a given board's SoC or variant. + If you're in a hurry, simple hardware can usually be supported by copy/paste followed by trial and error. If you want to understand details, you will need to read the rest of the devicetree documentation and the devicetree @@ -273,9 +410,9 @@ follows (with unimportant parts skipped): .. code-block:: devicetree can0: can@40024000 { - ... - status = "disabled"; - ... + ... + status = "disabled"; + ... }; It is up to the board :file:`.dts` or application overlay files to enable these @@ -289,8 +426,8 @@ controller and sets the bus speed: .. code-block:: devicetree &can0 { - status = "okay"; - bus-speed = <125000>; + status = "okay"; + bus-speed = <125000>; }; The ``&can0 { ... };`` syntax adds/overrides properties on the node with label @@ -300,6 +437,8 @@ Other examples of board-specific customization is pointing properties in ``aliases`` and ``chosen`` to the right nodes (see :ref:`dt-alias-chosen`), and making GPIO/pinmux assignments. +.. _board_kconfig_files: + Write Kconfig files ******************* @@ -310,33 +449,61 @@ application for it. Setting Kconfig configuration values is documented in detail in :ref:`setting_configuration_values`. -There are three mandatory Kconfig files in the board directory for a board -named ``plank``: +There is one mandatory Kconfig file in the board directory, and several optional +files for a board named ``plank``: .. code-block:: none - boards//plank - ├── Kconfig.board + boards//plank + ├── Kconfig + ├── Kconfig.plank ├── Kconfig.defconfig - └── plank_defconfig + ├── plank_defconfig + └── plank__defconfig + +:file:`Kconfig.plank` + A shared Kconfig file which can be sourced both in Zephyr Kconfig and sysbuild + Kconfig trees. -:file:`Kconfig.board` - Included by :zephyr_file:`boards/Kconfig` to include your board - in the list of options. + This file selects the SoC in the Kconfig tree and potential other SoC related + Kconfig settings. This file must not select anything outside the re-usable + Kconfig board and SoC trees. - This should at least contain a definition for a ``BOARD_PLANK`` option, - which looks something like this: + A :file:`Kconfig.plank` may look like this: .. code-block:: kconfig config BOARD_PLANK - bool "Plank board" - depends on SOC_SERIES_YOUR_SOC_SERIES_HERE - select SOC_PART_NUMBER_ABCDEFGH + select SOC_SOC1 + + The Kconfig symbols :kconfig:option:`BOARD_` and + :kconfig:option:`BOARD_` are constructed by the build + system, therefore no type shall be defined in above code snippet. + +:file:`Kconfig` + Included by :zephyr_file:`boards/Kconfig`. + + This file can add Kconfig settings which are specific to the current board. + + Not all boards have a :file:`Kconfig` file. + + A board specific setting should be defining a custom setting and usually with + a prompt, like this: + + .. code-block:: kconfig + + config BOARD_FEATURE + bool "Board specific feature" + + If the setting name is identical to an existing Kconfig setting in Zephyr and + only modifies the default value of said setting, then + :file:`Kconfig.defconfig` should be used instead. :file:`Kconfig.defconfig` Board-specific default values for Kconfig options. + Not all boards have a :file:`Kconfig.defconfig` file. + The entire file should be inside an ``if BOARD_PLANK`` / ``endif`` pair of lines, like this: @@ -347,35 +514,42 @@ named ``plank``: # Always set CONFIG_BOARD here. This isn't meant to be customized, # but is set as a "default" due to Kconfig language restrictions. config BOARD - default "plank" + default "plank" # Other options you want enabled by default go next. Examples: config FOO - default y + default y if NETWORKING config SOC_ETHERNET_DRIVER - default y + default y endif # NETWORKING endif # BOARD_PLANK -:file:`plank_defconfig` +:file:`plank_defconfig` / :file:`plank__defconfig` A Kconfig fragment that is merged as-is into the final build directory :file:`.config` whenever an application is compiled for your board. - You should at least select your board's SOC and do any mandatory settings for - your system clock, console, etc. The results are architecture-specific, but - typically look something like this: + If both the common :file:`plank_defconfig` file and one or more board + identifier specific :file:`plank__defconfig` files exist, then + all matching files will be used. + This allows you to place configuration which is common for all board SoCs, + CPU clusters, and board variants in the base :file:`plank_defconfig` and only + place the adjustments specific for a given SoC or board variant in the + :file:`plank__defconfig`. + + The ``_defconfig`` should contain mandatory settings for your system clock, + console, etc. The results are architecture-specific, but typically look + something like this: .. code-block:: cfg - CONFIG_SOC_${VENDOR_XYZ3000}=y # select your SoC CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 # set up your clock, etc CONFIG_SERIAL=y -:file:`plank_x_y_z.conf` +:file:`plank_x_y_z_defconfig` / :file:`plank__x_y_z_defconfig` A Kconfig fragment that is merged as-is into the final build directory :file:`.config` whenever an application is compiled for your board revision ``x.y.z``. @@ -523,90 +697,37 @@ Multiple board revisions See :ref:`application_board_version` for basics on this feature from the user perspective. -To create a new board revision for the ``plank`` board, create these additional -files in the board folder: - -.. code-block:: none - - boards//plank - ├── plank_.conf # optional - ├── plank_.overlay # optional - └── revision.cmake - -When the user builds for board ``plank@``: +Board revisions are described in the ``revision`` entry of the +:file:`board.yml`. -- The optional Kconfig settings specified in the file - :file:`plank_.conf` will be merged into the board's default Kconfig - configuration. +.. code-block:: yaml -- The optional devicetree overlay :file:`plank_.overlay` will be added - to the common :file:`plank.dts` devicetree file + board: + revision: + format: + default: + exact: + revisions: + - name: + - name: -- The :file:`revision.cmake` file controls how the Zephyr build system matches - the ``@`` string specified by the user when building an - application for the board. +Zephyr natively supports the following revision formats: -Currently, ```` can be either a numeric ``MAJOR.MINOR.PATCH`` style -revision like ``1.5.0``, an integer number like ``1``, or single letter like -``A``, ``B``, etc. Zephyr provides a CMake board extension function, -``board_check_revision()``, to make it easy to match either style from -:file:`revision.cmake`. +- ``major.minor.patch``: match a three digit revision, such as ``1.2.3``. +- ``number``: matches integer revisions +- ``letter``: matches single letter revisions from ``A`` to ``Z`` only -Valid board revisions may be specified as arguments to the -``board_check_revision()`` function, like: - -.. code-block:: cmake - - board_check_revision(FORMAT MAJOR.MINOR.PATCH - VALID_REVISIONS 0.1.0 0.3.0 ... - ) - -.. note:: - ``VALID_REVISIONS`` can be omitted if all valid revisions have specific - Kconfig fragments, such as ``_0_1_0.conf``, ``_0_3_0.conf``. - This allows you to just place Kconfig revision fragments in the board - folder and not have to keep the corresponding ``VALID_REVISIONS`` in sync. - -The following sections describe how to support these styles of revision -numbers. - -MAJOR.MINOR.PATCH revisions -=========================== - -Let's say you want to add support for revisions ``0.5.0``, ``1.0.0``, and -``1.5.0`` of the ``plank`` board with both Kconfig fragments and devicetree -overlays. Create :file:`revision.cmake` with -``board_check_revision(FORMAT MAJOR.MINOR.PATCH)``, and create the following -additional files in the board directory: - -.. code-block:: none - - boards//plank - ├── plank_0_5_0.conf - ├── plank_0_5_0.overlay - ├── plank_1_0_0.conf - ├── plank_1_0_0.overlay - ├── plank_1_5_0.conf - ├── plank_1_5_0.overlay - └── revision.cmake - -Notice how the board files have changed periods (".") in the revision number to -underscores ("_"). +.. _board_fuzzy_revision_matching: Fuzzy revision matching ------------------------ - -To support "fuzzy" ``MAJOR.MINOR.PATCH`` revision matching for the ``plank`` -board, use the following code in :file:`revision.cmake`: - -.. code-block:: cmake +======================= - board_check_revision(FORMAT MAJOR.MINOR.PATCH) +Fuzzy revision matching is enabled per default. If the user selects a revision between those available, the closest revision number that is not larger than the user's choice is used. For example, if the -user builds for ``plank@0.7.0``, the build system will target revision -``0.5.0``. +board ``plank`` defines revisions ``0.5.0``, and ``1.5.0`` and the user builds +for ``plank@0.7.0``, the build system will target revision ``0.5.0``. The build system will print this at CMake configuration time: @@ -617,149 +738,107 @@ The build system will print this at CMake configuration time: This allows you to only create revision configuration files for board revision numbers that introduce incompatible changes. -Any revision less than the minimum defined will be treated as an error. - -You may use ``0.0.0`` as a minimum revision to build for by creating the file -:file:`plank_0_0_0.conf` in the board directory. This will be used for any -revision lower than ``0.5.0``, for example if the user builds for -``plank@0.1.0``. +Similar for ``letter`` where revision ``A``, ``D``, and ``F`` could be defined +and the user builds for ``plank@E``, the build system will target revision ``D`` +. Exact revision matching ------------------------ - -Alternatively, the ``EXACT`` keyword can be given to ``board_check_revision()`` -in :file:`revision.cmake` to allow exact matches only, like this: +======================= -.. code-block:: cmake +Exact revision matching is enabled when ``exact: true`` is specified in the +revision section in :file:`board.yml`. - board_check_revision(FORMAT MAJOR.MINOR.PATCH EXACT) - -With this :file:`revision.cmake`, building for ``plank@0.7.0`` in the above -example will result in the following error message: +When exact is defined then building for ``plank@0.7.0`` in the above example +will result in the following error message: .. code-block:: console Board revision `0.7.0` not found. Please specify a valid board revision. -Letter revision matching -======================== +Board revision configuration adjustment +======================================= -Let's say instead that you need to support revisions ``A``, ``B``, and ``C`` of -the ``plank`` board. Create the following additional files in the board -directory: +When the user builds for board ``plank@`` it is possible to make +adjustments to the board's normal configuration. -.. code-block:: none +As described in the :ref:`default_board_configuration` and +:ref:`board_kconfig_files` sections the board default configuration is created +from the files :file:`.dts` / :file:`_.dts` and +:file:`_defconfig` / :file:`__defconfig`. +When building for a specific board revision, the above files are used as a +starting point and the following board files will be used in addition: - boards//plank - ├── plank_A.conf - ├── plank_A.overlay - ├── plank_B.conf - ├── plank_B.overlay - ├── plank_C.conf - ├── plank_C.overlay - └── revision.cmake +- :file:`___defconfig`: a specific revision + defconfig which is only used for the board and SOC / variants identified by + ``_``. -And add the following to :file:`revision.cmake`: +- :file:`__defconfig`: a specific revision defconfig which is + used for the board regardless of the SOC / variants. -.. code-block:: cmake +- :file:`__.overlay`: a specific revision dts + overlay which is only used for the board and SOC / variants identified by + ``_``. - board_check_revision(FORMAT LETTER) +- :file:`_.overlay`: a specific revision dts overlay which is + used for the board regardless of the SOC / variants. -Number revision matching -======================== +This split allows boards with multiple SoCs, multi-core SoCs, or variants to +place common revision adjustments which apply to all SoCs and variants in a +single file, while still providing the ability to place SoC or variant specific +adjustments in a dedicated revision file. -Let's say instead that you need to support revisions ``1``, ``2``, and ``3`` of -the ``plank`` board. Create the following additional files in the board -directory: +Using the ``plank`` board from previous sections, then we could have the following +revision adjustments: .. code-block:: none - boards//plank - ├── plank_1.conf - ├── plank_1.overlay - ├── plank_2.conf - ├── plank_2.overlay - ├── plank_3.conf - ├── plank_3.overlay - └── revision.cmake + boards/zephyr/plank + ├── plank_0_5_0_defconfig # Kconfig adjustment for all plank board identifiers on revision 0.5.0 + ├── plank_0_5_0.overlay # DTS overlay for all plank board identifiers on revision 0.5.0 + └── plank_soc1_foo_1_5_0_defconfig # Kconfig adjustment for plank board when building for soc1 variant foo on revision 1.5.0 -And add the following to :file:`revision.cmake`: +Custom revision.cmake files +*************************** -.. code-block:: cmake +Some boards may not use board revisions supported natively by Zephyr. +For example string revisions. - board_check_revision(FORMAT NUMBER) +One reason why Zephyr doesn't support string revisions is that strings can take +many forms and it's not always clear if the given strings are just strings, such +as ``blue``, ``green``, ``red``, etc. or if they provide an order which can be +matched against higher or lower revisions, such as ``alpha``, ``beta```, +``gamma``. -board_check_revision() details -============================== +Due to the sheer number of possibilities with strings, including the possibility +of doing regex matches internally, then string revisions must be done using +``custom`` revision type. -.. code-block:: cmake +To indicate to the build system that ``custom`` revisions are used, the format +field in the ``revision`` section of the :file:`board.yml` must be written as: - board_check_revision(FORMAT - [OPTIONAL EXACT] - [DEFAULT_REVISION ] - [HIGHEST_REVISION ] - [VALID_REVISIONS [ ...]] - ) - -This function supports the following arguments: - -* ``FORMAT LETTER``: matches single letter revisions from ``A`` to ``Z`` only -* ``FORMAT NUMBER``: matches integer revisions -* ``FORMAT MAJOR.MINOR.PATCH``: matches exactly three digits. The command line - allows for loose typing, that is ``-DBOARD=@1`` and - ``-DBOARD=@1.0`` will be handled as ``-DBOARD=@1.0.0``. - Kconfig fragment and devicetree overlay files must use full numbering to avoid - ambiguity, so only :file:`_1_0_0.conf` and - :file:`_1_0_0.overlay` are allowed. - -* ``OPTIONAL``: if given, a revision is not required to be specified. - If the revision is not supplied, the base board is used with no overlays. - Can be combined with ``EXACT``, in which case providing the revision is - optional, but if given the ``EXACT`` rules apply. Mutually exclusive with - ``DEFAULT_REVISION``. - -* ``EXACT``: if given, the revision is required to be an exact match. - Otherwise, the closest matching revision not greater than the user's choice - will be selected. - -* ``DEFAULT_REVISION ``: if given, ```` is the default - revision to use when user has not selected a revision number. If not given, - the build system prints an error when the user does not specify a board - revision. - -* ``HIGHEST_REVISION``: if given, specifies the highest valid revision for a - board. This can be used to ensure that a newer board cannot be used with an - older Zephyr. For example, if the current board directory supports revisions - 0.x.0-0.99.99 and 1.0.0-1.99.99, and it is expected that the implementation - will not work with board revision 2.0.0, then giving ``HIGHEST_REVISION - 1.99.99`` causes an error if the user builds using ``@2.0.0``. - -* ``VALID_REVISIONS``: if given, specifies a list of revisions that are valid - for this board. If this argument is not given, then each Kconfig fragment of - the form ``_.conf`` in the board folder will be used as a - valid revision for the board. - -.. _porting_custom_board_revisions: +.. code-block:: yaml -Custom revision.cmake files -*************************** + board: + revision: + format: custom + +When using custom revisions then a :file:`revision.cmake` must be created in the +board directory. -Some boards may not use board revisions supported by -``board_check_revision()``. To support revisions of any type, the file -:file:`revision.cmake` can implement custom revision matching without calling -``board_check_revision()``. +The :file:`revision.cmake` will be included by the build system when building +for the board and it is the responsibility of the file to validate the revision +specified by the user. + +The :makevar:`BOARD_REVISION` variable holds the revision value specified by the +user. To signal to the build system that it should use a different revision than the one specified by the user, :file:`revision.cmake` can set the variable ``ACTIVE_BOARD_REVISION`` to the revision to use instead. The corresponding Kconfig files and devicetree overlays must be named -:file:`_.conf` and +:file:`__defconfig` and :file:`_.overlay`. -For example, if the user builds for ``plank@zero``, :file:`revision.cmake` can -set ``ACTIVE_BOARD_REVISION`` to ``one`` to use the files -:file:`plank_one.conf` and :file:`plank_one.overlay`. - .. _contributing-your-board: Contributing your board diff --git a/doc/services/device_mgmt/mcumgr.rst b/doc/services/device_mgmt/mcumgr.rst index 0b21ce0771a..6d4d575baa1 100644 --- a/doc/services/device_mgmt/mcumgr.rst +++ b/doc/services/device_mgmt/mcumgr.rst @@ -319,7 +319,7 @@ On boards where a J-Link OB is present which has both CDC and MSC (virtual Mass Storage Device, also known as drag-and-drop) support, the MSD functionality can prevent MCUmgr commands over the CDC UART port from working due to how USB endpoints are configured in the J-Link firmware (for example on the -:ref:`Nordic nrf52840dk_nrf52840 board `) because of +:ref:`Nordic nrf52840dk/nrf52840 board `) because of limiting the maximum packet size (most likely to occur when using image management commands for updating firmware). This issue can be resolved by disabling MSD functionality on the J-Link device, follow the diff --git a/doc/services/tfm/requirements.rst b/doc/services/tfm/requirements.rst index 58f573821e4..13795986875 100644 --- a/doc/services/tfm/requirements.rst +++ b/doc/services/tfm/requirements.rst @@ -13,19 +13,19 @@ The following are some of the boards that can be used with TF-M: * - :ref:`mps3_an547_board` - ``mps3_an547_ns`` (qemu supported) * - :ref:`bl5340_dvk` - - ``bl5340_dvk_cpuapp_ns`` + - ``bl5340_dvk/nrf5340/cpuapp/ns`` * - :ref:`lpcxpresso55s69` - ``lpcxpresso55s69_ns`` * - :ref:`nrf9160dk_nrf9160` - - ``nrf9160dk_nrf9160_ns`` + - ``nrf9160dk/nrf9160/ns`` * - :ref:`nrf5340dk_nrf5340` - - ``nrf5340dk_nrf5340_cpuapp_ns`` + - ``nrf5340dk/nrf5340/cpuapp/ns`` * - :ref:`b_u585i_iot02a_board` - - ``b_u585i_iot02a_ns`` + - ``b_u585i_iot02a/stm32u585xx/ns`` * - :ref:`nucleo_l552ze_q_board` - - ``nucleo_l552ze_q_ns`` + - ``nucleo_l552ze_q/stm32l552xx/ns`` * - :ref:`stm32l562e_dk_board` - - ``stm32l562e_dk_ns`` + - ``stm32l562e_dk/stm32l562xx/ns`` * - :ref:`v2m_musca_b1_board` - ``v2m_musca_b1_ns`` * - :ref:`v2m_musca_s1_board` diff --git a/drivers/can/Kconfig.mcux b/drivers/can/Kconfig.mcux index 7df67684e8a..e995a19ab6f 100644 --- a/drivers/can/Kconfig.mcux +++ b/drivers/can/Kconfig.mcux @@ -31,9 +31,9 @@ config CAN_MCUX_FLEXCAN_WAIT_TIMEOUT config CAN_MAX_MB int "Maximum number of message buffers for concurrent active instances" default 16 - depends on SOC_SERIES_S32K3XX || SOC_SERIES_S32K1XX - range 1 96 if SOC_SERIES_S32K3XX - range 1 32 if SOC_SERIES_S32K1XX && !SOC_S32K142W && !SOC_S32K144W + depends on SOC_SERIES_S32K3 || SOC_SERIES_S32K1 + range 1 96 if SOC_SERIES_S32K3 + range 1 32 if SOC_SERIES_S32K1 && !SOC_S32K142W && !SOC_S32K144W range 1 64 if SOC_S32K142W || SOC_S32K144W help Defines maximum number of message buffers for concurrent active instances. @@ -42,10 +42,10 @@ config CAN_MAX_FILTER int "Maximum number of concurrent active RX filters" default 5 range 1 15 if SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_KINETIS_K6X - range 1 13 if SOC_SERIES_IMX_RT && CAN_MCUX_FLEXCAN_FD - range 1 63 if SOC_SERIES_IMX_RT - range 1 96 if SOC_SERIES_S32K3XX - range 1 32 if SOC_SERIES_S32K1XX && !SOC_S32K142W && !SOC_S32K144W + range 1 13 if (SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX) && CAN_MCUX_FLEXCAN_FD + range 1 63 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + range 1 96 if SOC_SERIES_S32K3 + range 1 32 if SOC_SERIES_S32K1 && !SOC_S32K142W && !SOC_S32K144W range 1 64 if SOC_S32K142W || SOC_S32K144W help Defines maximum number of concurrent active RX filters diff --git a/drivers/clock_control/Kconfig.rcar b/drivers/clock_control/Kconfig.rcar index 0caa0723554..2947c3da6f4 100644 --- a/drivers/clock_control/Kconfig.rcar +++ b/drivers/clock_control/Kconfig.rcar @@ -4,6 +4,6 @@ config CLOCK_CONTROL_RCAR_CPG_MSSR bool "RCar CPG MSSR driver" default y - depends on SOC_FAMILY_RCAR + depends on SOC_FAMILY_RENESAS_RCAR help Enable support for Renesas RCar CPG MSSR driver. diff --git a/drivers/clock_control/Kconfig.smartbond b/drivers/clock_control/Kconfig.smartbond index a8e2d2f86fc..d20907c6001 100644 --- a/drivers/clock_control/Kconfig.smartbond +++ b/drivers/clock_control/Kconfig.smartbond @@ -5,6 +5,6 @@ config CLOCK_CONTROL_SMARTBOND bool "Smartbond Clock Control" - depends on SOC_FAMILY_SMARTBOND + depends on SOC_FAMILY_RENESAS_SMARTBOND help Enable driver for Clock Control subsystem found in SmartBond diff --git a/drivers/clock_control/clock_control_mchp_xec.c b/drivers/clock_control/clock_control_mchp_xec.c index ae79ae1b416..11b0b54ac41 100644 --- a/drivers/clock_control/clock_control_mchp_xec.c +++ b/drivers/clock_control/clock_control_mchp_xec.c @@ -122,7 +122,7 @@ struct pcr_hw_regs { #define XEC_CC_PCR_CLK32K_SRC_PIN 2 #define XEC_CC_PCR_CLK32K_SRC_OFF 3 -#ifdef CONFIG_SOC_SERIES_MEC1501X +#ifdef CONFIG_SOC_SERIES_MEC15XX #define XEC_CC_PCR3_CRYPTO_MASK (BIT(26) | BIT(27) | BIT(28)) #else #define XEC_CC_PCR3_CRYPTO_MASK BIT(26) @@ -263,7 +263,7 @@ static int periph_clk_src_using_pin(enum periph_clk32k_src src) } } -#ifdef CONFIG_SOC_SERIES_MEC1501X +#ifdef CONFIG_SOC_SERIES_MEC15XX /* MEC15xx uses the same 32KHz source for both PLL and Peripheral 32K clock domains. * We ignore the peripheral clock source. * If XTAL is selected (parallel) or single-ended the external 32KHz MUST stay on @@ -915,7 +915,7 @@ static inline int xec_clock_control_off(const struct device *dev, */ static uint32_t get_turbo_clock(const struct device *dev) { -#ifdef CONFIG_SOC_SERIES_MEC1501X +#ifdef CONFIG_SOC_SERIES_MEC15XX ARG_UNUSED(dev); return MHZ(48); @@ -1079,7 +1079,7 @@ const struct xec_pcr_config pcr_xec_config = { (uint16_t)DT_INST_PROP_OR(0, pll_lock_timeout_ms, XEC_CC_DFLT_PLL_LOCK_WAIT_MS), .period_min = (uint16_t)DT_INST_PROP_OR(0, clk32kmon_period_min, CNT32K_TMIN), .period_max = (uint16_t)DT_INST_PROP_OR(0, clk32kmon_period_max, CNT32K_TMAX), - .core_clk_div = (uint8_t)DT_INST_PROP_OR(0, core_clk_div, CONFIG_SOC_MEC172X_PROC_CLK_DIV), + .core_clk_div = (uint8_t)DT_INST_PROP_OR(0, core_clk_div, CONFIG_SOC_MEC_PROC_CLK_DIV), .xtal_se = (uint8_t)DT_INST_PROP_OR(0, xtal_single_ended, 0), .max_dc_va = (uint8_t)DT_INST_PROP_OR(0, clk32kmon_duty_cycle_var_max, CNT32K_DUTY_MAX), .min_valid = (uint8_t)DT_INST_PROP_OR(0, clk32kmon_valid_min, CNT32K_VAL_MIN), diff --git a/drivers/clock_control/clock_control_mcux_ccm.c b/drivers/clock_control/clock_control_mcux_ccm.c index 6245788961c..14959446d89 100644 --- a/drivers/clock_control/clock_control_mcux_ccm.c +++ b/drivers/clock_control/clock_control_mcux_ccm.c @@ -353,7 +353,7 @@ static int CCM_SET_FUNC_ATTR mcux_ccm_set_subsys_rate(const struct device *dev, case IMX_CCM_FLEXSPI_CLK: __fallthrough; case IMX_CCM_FLEXSPI2_CLK: -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI) /* The SOC is using the FlexSPI for XIP. Therefore, * the FlexSPI itself must be managed within the function, * which is SOC specific. diff --git a/drivers/clock_control/clock_control_mcux_ccm_rev2.c b/drivers/clock_control/clock_control_mcux_ccm_rev2.c index c99741a78f2..a30a3b93491 100644 --- a/drivers/clock_control/clock_control_mcux_ccm_rev2.c +++ b/drivers/clock_control/clock_control_mcux_ccm_rev2.c @@ -115,7 +115,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, break; #endif -#if defined(CONFIG_SOC_MIMX93_A55) && defined(CONFIG_DAI_NXP_SAI) +#if defined(CONFIG_SOC_MIMX9352_A55) && defined(CONFIG_DAI_NXP_SAI) case IMX_CCM_SAI1_CLK: case IMX_CCM_SAI2_CLK: case IMX_CCM_SAI3_CLK: @@ -144,7 +144,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, default: return -EINVAL; } -#ifdef CONFIG_SOC_MIMX93_A55 +#ifdef CONFIG_SOC_MIMX9352_A55 *rate = CLOCK_GetIpFreq(clock_root); #else *rate = CLOCK_GetRootClockFreq(clock_root); @@ -173,7 +173,7 @@ static int CCM_SET_FUNC_ATTR mcux_ccm_set_subsys_rate(const struct device *dev, case IMX_CCM_FLEXSPI_CLK: __fallthrough; case IMX_CCM_FLEXSPI2_CLK: -#if defined(CONFIG_SOC_SERIES_IMX_RT11XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI) +#if defined(CONFIG_SOC_SERIES_IMXRT11XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI) /* The SOC is using the FlexSPI for XIP. Therefore, * the FlexSPI itself must be managed within the function, * which is SOC specific. diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index a0a7db57d28..5386b41ed04 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -27,7 +27,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev, if ((uint32_t)sub_system == MCUX_MRT_CLK) { #if defined(CONFIG_SOC_FAMILY_LPC) CLOCK_EnableClock(kCLOCK_Mrt); -#elif defined(CONFIG_SOC_FAMILY_IMX) +#elif defined(CONFIG_SOC_FAMILY_NXP_IMXRT) CLOCK_EnableClock(kCLOCK_Mrt0); #endif } diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index 9d76004c92f..871b1d50a3a 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -90,8 +90,8 @@ /* Datasheet maximum frequency definitions */ #if defined(CONFIG_SOC_STM32H743XX) ||\ - defined(CONFIG_SOC_STM32H745XX) ||\ - defined(CONFIG_SOC_STM32H747XX) ||\ + defined(CONFIG_SOC_STM32H745XX_M7) || defined(CONFIG_SOC_STM32H745XX_M4) ||\ + defined(CONFIG_SOC_STM32H747XX_M7) || defined(CONFIG_SOC_STM32H747XX_M4) ||\ defined(CONFIG_SOC_STM32H750XX) ||\ defined(CONFIG_SOC_STM32H753XX) /* All h7 SoC with maximum 480MHz SYSCLK */ diff --git a/drivers/counter/counter_cmos.c b/drivers/counter/counter_cmos.c index 3edd718b9fe..00645bc71b0 100644 --- a/drivers/counter/counter_cmos.c +++ b/drivers/counter/counter_cmos.c @@ -11,11 +11,12 @@ * crossing clock domains (no pun intended). Use accordingly. */ -#define DT_DRV_COMPAT motorola_mc146818 - +#include #include #include -#include +#include + +#define DT_DRV_COMPAT motorola_mc146818 /* The "CMOS" device is accessed via an address latch and data port. */ diff --git a/drivers/dai/intel/dmic/dmic.c b/drivers/dai/intel/dmic/dmic.c index 3da5fb8c538..f65c554cf98 100644 --- a/drivers/dai/intel/dmic/dmic.c +++ b/drivers/dai/intel/dmic/dmic.c @@ -570,7 +570,7 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic) dai_dmic_start_fifo_packers(dmic, dmic->dai_config_params.dai_index); for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) { -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, CIC_CONTROL_SOFT_RESET, 0); @@ -621,7 +621,7 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic) FIELD_PREP(FIR_CONTROL_START, start_fir)); } -#ifndef CONFIG_SOC_SERIES_INTEL_ACE +#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE /* Clear soft reset for all/used PDM controllers. This should * start capture in sync. */ diff --git a/drivers/dai/intel/dmic/dmic_nhlt.c b/drivers/dai/intel/dmic/dmic_nhlt.c index 3d803da33b9..c7fe48e1432 100644 --- a/drivers/dai/intel/dmic/dmic_nhlt.c +++ b/drivers/dai/intel/dmic/dmic_nhlt.c @@ -175,7 +175,7 @@ static int dai_nhlt_update_rate(struct dai_intel_dmic *dmic, const int clock_sou return 0; } -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE static int dai_ipm_source_to_enable(struct dai_intel_dmic *dmic, int *count, int pdm_count, int stereo, int source_pdm) @@ -426,7 +426,7 @@ static inline int dai_dmic_set_clock(const struct dai_intel_dmic *dmic, const ui static int print_outcontrol(uint32_t val) { int bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE int bf9, bf10, bf11, bf12, bf13; #endif uint32_t ref; @@ -447,7 +447,7 @@ static int print_outcontrol(uint32_t val) return -EINVAL; } -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE bf9 = FIELD_GET(OUTCONTROL_IPM_SOURCE_1, val); bf10 = FIELD_GET(OUTCONTROL_IPM_SOURCE_2, val); bf11 = FIELD_GET(OUTCONTROL_IPM_SOURCE_3, val); @@ -487,7 +487,7 @@ static void print_cic_control(uint32_t val) bf4 = FIELD_GET(CIC_CONTROL_MIC_B_POLARITY, val); bf5 = FIELD_GET(CIC_CONTROL_MIC_A_POLARITY, val); bf6 = FIELD_GET(CIC_CONTROL_MIC_MUTE, val); -#ifndef CONFIG_SOC_SERIES_INTEL_ACE +#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE bf7 = FIELD_GET(CIC_CONTROL_STEREO_MODE, val); #else bf7 = -1; @@ -503,7 +503,7 @@ static void print_cic_control(uint32_t val) FIELD_PREP(CIC_CONTROL_MIC_B_POLARITY, bf4) | FIELD_PREP(CIC_CONTROL_MIC_A_POLARITY, bf5) | FIELD_PREP(CIC_CONTROL_MIC_MUTE, bf6) -#ifndef CONFIG_SOC_SERIES_INTEL_ACE +#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE | FIELD_PREP(CIC_CONTROL_STEREO_MODE, bf7) #endif ; @@ -520,7 +520,7 @@ static void print_fir_control(uint32_t val) bf1 = FIELD_GET(FIR_CONTROL_START, val); bf2 = FIELD_GET(FIR_CONTROL_ARRAY_START_EN, val); -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE bf3 = FIELD_GET(FIR_CONTROL_PERIODIC_START_EN, val); #else bf3 = -1; @@ -534,7 +534,7 @@ static void print_fir_control(uint32_t val) LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6); ref = FIELD_PREP(FIR_CONTROL_START, bf1) | FIELD_PREP(FIR_CONTROL_ARRAY_START_EN, bf2) | -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE FIELD_PREP(FIR_CONTROL_PERIODIC_START_EN, bf3) | #endif FIELD_PREP(FIR_CONTROL_DCCOMP, bf4) | @@ -561,7 +561,7 @@ static void print_pdm_ctrl(const struct nhlt_pdm_ctrl_cfg *pdm_cfg) val = pdm_cfg->mic_control; -#ifndef CONFIG_SOC_SERIES_INTEL_ACE +#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE bf1 = FIELD_GET(MIC_CONTROL_PDM_SKEW, val); #else bf1 = -1; @@ -797,7 +797,7 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf } } -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE ret = dai_nhlt_dmic_dai_params_get(dmic, dmic_cfg->clock_source); #else ret = dai_nhlt_dmic_dai_params_get(dmic); diff --git a/drivers/dai/intel/ssp/Kconfig.ssp b/drivers/dai/intel/ssp/Kconfig.ssp index c44d4c4ec23..adb88e7645b 100644 --- a/drivers/dai/intel/ssp/Kconfig.ssp +++ b/drivers/dai/intel/ssp/Kconfig.ssp @@ -15,7 +15,7 @@ config DAI_INTEL_SSP config DAI_SSP_HAS_POWER_CONTROL bool "DAI ssp pm_runtime en/dis ssp power" - default y if SOC_SERIES_INTEL_ACE + default y if SOC_SERIES_INTEL_ADSP_ACE depends on DAI_INTEL_SSP if DAI_INTEL_SSP diff --git a/drivers/dai/intel/ssp/ssp.c b/drivers/dai/intel/ssp/ssp.c index 682077a6d73..447a31c235f 100644 --- a/drivers/dai/intel/ssp/ssp.c +++ b/drivers/dai/intel/ssp/ssp.c @@ -1607,7 +1607,7 @@ static int dai_ssp_check_aux_data(struct ssp_intel_aux_tlv *aux_tlv, int aux_len size = sizeof(struct ssp_intel_ext_ctl); break; case SSP_LINK_CLK_SOURCE: -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE size = sizeof(struct ssp_intel_link_ctl); break; #else @@ -1642,7 +1642,7 @@ static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_con struct ssp_intel_node_ctl *node; struct ssp_intel_sync_ctl *sync; struct ssp_intel_ext_ctl *ext; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE struct ssp_intel_link_ctl *link; #endif uint8_t *aux_ptr; @@ -1698,7 +1698,7 @@ static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_con LOG_INF("ext ext_data %u", ext->ext_data); break; case SSP_LINK_CLK_SOURCE: -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE link = (struct ssp_intel_link_ctl *)&aux_tlv->val; #if CONFIG_SOC_INTEL_ACE15_MTPM diff --git a/drivers/dai/intel/ssp/ssp.h b/drivers/dai/intel/ssp/ssp.h index 0d53c0c6159..5a187730dd5 100644 --- a/drivers/dai/intel/ssp/ssp.h +++ b/drivers/dai/intel/ssp/ssp.h @@ -236,7 +236,7 @@ #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE /** \brief Offset of MCLK Divider Control Register. */ #define MN_MDIVCTRL 0x100 diff --git a/drivers/disk/nvme/nvme_controller.c b/drivers/disk/nvme/nvme_controller.c index 699df325add..e58a1baa734 100644 --- a/drivers/disk/nvme/nvme_controller.c +++ b/drivers/disk/nvme/nvme_controller.c @@ -13,7 +13,6 @@ LOG_MODULE_REGISTER(nvme, CONFIG_NVME_LOG_LEVEL); #include -#include #include #include diff --git a/drivers/dma/Kconfig.intel_adsp_gpdma b/drivers/dma/Kconfig.intel_adsp_gpdma index 4e26ca5d93b..9fa7f3baed5 100644 --- a/drivers/dma/Kconfig.intel_adsp_gpdma +++ b/drivers/dma/Kconfig.intel_adsp_gpdma @@ -21,7 +21,7 @@ config DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP config DMA_INTEL_ADSP_GPDMA_HAS_LLP bool "Intel ADSP GPDMA Linear Link Position Feature" - default y if SOC_SERIES_INTEL_ACE + default y if SOC_SERIES_INTEL_ADSP_ACE help Intel ADSP GPDMA may optionally have a linear link position feature. diff --git a/drivers/dma/Kconfig.mcux_edma b/drivers/dma/Kconfig.mcux_edma index d1e513e3c13..6abf1cba489 100644 --- a/drivers/dma/Kconfig.mcux_edma +++ b/drivers/dma/Kconfig.mcux_edma @@ -28,10 +28,10 @@ config DMA_TCD_QUEUE_SIZE config DMA_MCUX_TEST_SLOT_START int "test slot start num" - depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K3XX) + depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K3) default 58 if SOC_SERIES_KINETIS_K6X default 60 if SOC_SERIES_KINETIS_KE1XF - default 62 if SOC_SERIES_S32K3XX + default 62 if SOC_SERIES_S32K3 help test slot start num diff --git a/drivers/dma/dma_intel_adsp_gpdma.c b/drivers/dma/dma_intel_adsp_gpdma.c index e2927471050..5e3850244d9 100644 --- a/drivers/dma/dma_intel_adsp_gpdma.c +++ b/drivers/dma/dma_intel_adsp_gpdma.c @@ -162,7 +162,7 @@ static int intel_adsp_gpdma_config(const struct device *dev, uint32_t channel, static int intel_adsp_gpdma_start(const struct device *dev, uint32_t channel) { int ret = 0; -#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ACE +#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ADSP_ACE bool first_use = false; enum pm_device_state state; @@ -187,7 +187,7 @@ static int intel_adsp_gpdma_start(const struct device *dev, uint32_t channel) intel_adsp_gpdma_llp_disable(dev, channel); } -#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ACE +#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ADSP_ACE /* Device usage is counted by the calls of dw_dma_start and dw_dma_stop. For the first use, * we need to make sure that the pm_device_runtime_get and pm_device_runtime_put functions * calls are balanced. @@ -246,7 +246,7 @@ static void intel_adsp_gpdma_clock_enable(const struct device *dev) uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET; uint32_t val; - if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE)) { + if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_ADSP_ACE)) { val = sys_read32(reg) | GPDMA_CTL_DCGD; } else { val = GPDMA_CTL_FDCGB; @@ -258,7 +258,7 @@ static void intel_adsp_gpdma_clock_enable(const struct device *dev) #ifdef CONFIG_PM_DEVICE static void intel_adsp_gpdma_clock_disable(const struct device *dev) { -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET; uint32_t val = sys_read32(reg) & ~GPDMA_CTL_DCGD; @@ -271,7 +271,7 @@ static void intel_adsp_gpdma_clock_disable(const struct device *dev) static void intel_adsp_gpdma_claim_ownership(const struct device *dev) { #ifdef CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET; uint32_t val = sys_read32(reg) | GPDMA_OSEL(0x3); @@ -281,7 +281,7 @@ static void intel_adsp_gpdma_claim_ownership(const struct device *dev) sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG, DSP_INIT_LPGPDMA(0)); sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG, DSP_INIT_LPGPDMA(1)); ARG_UNUSED(dev); -#endif /* CONFIG_SOC_SERIES_INTEL_ACE */ +#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */ #endif /* CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP */ } @@ -289,7 +289,7 @@ static void intel_adsp_gpdma_claim_ownership(const struct device *dev) static void intel_adsp_gpdma_release_ownership(const struct device *dev) { #ifdef CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET; uint32_t val = sys_read32(reg) & ~GPDMA_OSEL(0x3); @@ -298,12 +298,12 @@ static void intel_adsp_gpdma_release_ownership(const struct device *dev) /* CHECKME: Do CAVS platforms set ownership over DMA, * if yes, add support for it releasing. */ -#endif /* CONFIG_SOC_SERIES_INTEL_ACE */ +#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */ #endif /* CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP */ } #endif -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE static int intel_adsp_gpdma_enable(const struct device *dev) { const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; @@ -329,14 +329,14 @@ static int intel_adsp_gpdma_disable(const struct device *dev) return 0; } #endif /* CONFIG_PM_DEVICE */ -#endif /* CONFIG_SOC_SERIES_INTEL_ACE */ +#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */ static int intel_adsp_gpdma_power_on(const struct device *dev) { const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; int ret; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE /* Power up */ ret = intel_adsp_gpdma_enable(dev); @@ -377,12 +377,12 @@ static int intel_adsp_gpdma_power_off(const struct device *dev) /* Relesing DMA ownership*/ intel_adsp_gpdma_release_ownership(dev); -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE /* Power down */ return intel_adsp_gpdma_disable(dev); #else return 0; -#endif /* CONFIG_SOC_SERIES_INTEL_ACE */ +#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */ } #endif /* CONFIG_PM_DEVICE */ @@ -423,7 +423,7 @@ int intel_adsp_gpdma_get_attribute(const struct device *dev, uint32_t type, uint return 0; } -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE static inline void ace_gpdma_intc_unmask(void) { ACE_DINT[0].ie[ACE_INTL_GPDMA] = BIT(0); @@ -444,7 +444,7 @@ int intel_adsp_gpdma_init(const struct device *dev) ace_gpdma_intc_unmask(); -#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ACE +#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ADSP_ACE if (pm_device_on_power_domain(dev)) { pm_device_init_off(dev); } else { diff --git a/drivers/dma/dma_intel_adsp_hda_host_in.c b/drivers/dma/dma_intel_adsp_hda_host_in.c index a999c7fbba6..a6114b05404 100644 --- a/drivers/dma/dma_intel_adsp_hda_host_in.c +++ b/drivers/dma/dma_intel_adsp_hda_host_in.c @@ -49,7 +49,8 @@ static const struct dma_driver_api intel_adsp_hda_dma_host_in_api = { DEVICE_DT_INST_GET(inst), \ DT_INST_IRQ(inst, sense)); \ irq_enable(DT_INST_IRQN(inst)); \ - IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE, (ACE_DINT[0].ie[ACE_INTL_HDAHIDMA] = 1;)) \ + IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ADSP_ACE, \ + (ACE_DINT[0].ie[ACE_INTL_HDAHIDMA] = 1;)) \ } DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_HDA_DMA_HOST_IN_INIT) diff --git a/drivers/dma/dma_intel_adsp_hda_host_out.c b/drivers/dma/dma_intel_adsp_hda_host_out.c index cb7d9137a1a..f06d177ed29 100644 --- a/drivers/dma/dma_intel_adsp_hda_host_out.c +++ b/drivers/dma/dma_intel_adsp_hda_host_out.c @@ -53,7 +53,8 @@ static const struct dma_driver_api intel_adsp_hda_dma_host_out_api = { DEVICE_DT_INST_GET(inst), \ DT_INST_IRQ(inst, sense)); \ irq_enable(DT_INST_IRQN(inst)); \ - IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE, (ACE_DINT[0].ie[ACE_INTL_HDAHODMA] = 1;)) \ + IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ADSP_ACE, \ + (ACE_DINT[0].ie[ACE_INTL_HDAHODMA] = 1;)) \ } DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_HDA_DMA_HOST_OUT_INIT) diff --git a/drivers/espi/Kconfig.xec b/drivers/espi/Kconfig.xec index b110f91cfb0..b1752285c59 100644 --- a/drivers/espi/Kconfig.xec +++ b/drivers/espi/Kconfig.xec @@ -39,7 +39,7 @@ config ESPI_PERIPHERAL_UART config ESPI_PERIPHERAL_UART_SOC_MAPPING int "SoC port exposed as logical eSPI UART" - default 2 if SOC_SERIES_MEC1501X + default 2 if SOC_SERIES_MEC15XX default 1 if SOC_SERIES_MEC172X depends on ESPI_PERIPHERAL_UART help @@ -66,7 +66,7 @@ config ESPI_FLASH_BUFFER_SIZE config ESPI_SAF_XEC bool "XEC Microchip ESPI SAF driver" default y - depends on SOC_SERIES_MEC1501X + depends on SOC_SERIES_MEC15XX depends on DT_HAS_MICROCHIP_XEC_ESPI_SAF_ENABLED help Enable the Microchip XEC SAF ESPI driver for MEC15xx family. diff --git a/drivers/ethernet/Kconfig.mcux b/drivers/ethernet/Kconfig.mcux index 8996d7239ff..c9b8e4fb6f2 100644 --- a/drivers/ethernet/Kconfig.mcux +++ b/drivers/ethernet/Kconfig.mcux @@ -94,8 +94,8 @@ if PTP_CLOCK_MCUX config ETH_MCUX_PTP_CLOCK_SRC_HZ int "Frequency of the clock source for the PTP timer" default 50000000 if SOC_SERIES_KINETIS_K6X - default 50000000 if SOC_SERIES_IMX_RT10XX - default 24000000 if SOC_SERIES_IMX_RT11XX + default 50000000 if SOC_SERIES_IMXRT10XX + default 24000000 if SOC_SERIES_IMXRT11XX help Set the frequency in Hz sourced to the PTP timer. If the value is set properly, the timer will be accurate. diff --git a/drivers/ethernet/eth_mcux.c b/drivers/ethernet/eth_mcux.c index 02f3a830495..a00b7ff57cc 100644 --- a/drivers/ethernet/eth_mcux.c +++ b/drivers/ethernet/eth_mcux.c @@ -396,7 +396,7 @@ static void eth_mcux_phy_start(struct eth_context *context) k_work_submit(&context->phy_work); break; #endif -#if defined(CONFIG_SOC_SERIES_IMX_RT) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) context->phy_state = eth_mcux_phy_state_initial; #else context->phy_state = eth_mcux_phy_state_reset; @@ -453,7 +453,7 @@ static void eth_mcux_phy_event(struct eth_context *context) uint32_t status; #endif bool link_up; -#if defined(CONFIG_SOC_SERIES_IMX_RT) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) status_t res; uint16_t ctrl2; #endif @@ -466,7 +466,7 @@ static void eth_mcux_phy_event(struct eth_context *context) #endif switch (context->phy_state) { case eth_mcux_phy_state_initial: -#if defined(CONFIG_SOC_SERIES_IMX_RT) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) ENET_DisableInterrupts(context->base, ENET_EIR_MII_MASK); res = PHY_Read(context->phy_handle, PHY_CONTROL2_REG, &ctrl2); ENET_EnableInterrupts(context->base, ENET_EIR_MII_MASK); @@ -481,7 +481,7 @@ static void eth_mcux_phy_event(struct eth_context *context) ctrl2); } context->phy_state = eth_mcux_phy_state_reset; -#endif /* CONFIG_SOC_SERIES_IMX_RT */ +#endif #if defined(CONFIG_ETH_MCUX_NO_PHY_SMI) /* * When the iface is available proceed with the eth link setup, @@ -633,7 +633,7 @@ static void eth_mcux_delayed_phy_work(struct k_work *item) static void eth_mcux_phy_setup(struct eth_context *context) { -#if defined(CONFIG_SOC_SERIES_IMX_RT) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) status_t res; uint16_t oms_override; @@ -1024,14 +1024,14 @@ static void eth_mcux_init(const struct device *dev) context->phy_state = eth_mcux_phy_state_initial; context->phy_handle->ops = &phyksz8081_ops; -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) sys_clock = CLOCK_GetFreq(kCLOCK_IpgClk); #endif #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) sys_clock = CLOCK_GetFreq(kCLOCK_EnetPll1Clk); #endif -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) sys_clock = CLOCK_GetRootClockFreq(kCLOCK_Root_Bus); #else sys_clock = CLOCK_GetFreq(kCLOCK_CoreSysClk); @@ -1391,9 +1391,9 @@ static void eth_mcux_err_isr(const struct device *dev) } #endif -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) #define ETH_MCUX_UNIQUE_ID (OCOTP->CFG1 ^ OCOTP->CFG2) -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) #define ETH_MCUX_UNIQUE_ID (OCOTP->FUSEN[40].FUSE) #elif defined(CONFIG_SOC_SERIES_KINETIS_K6X) #define ETH_MCUX_UNIQUE_ID (SIM->UIDH ^ SIM->UIDMH ^ SIM->UIDML ^ SIM->UIDL) diff --git a/drivers/ethernet/eth_nxp_enet.c b/drivers/ethernet/eth_nxp_enet.c index 244867dddf6..864a488f554 100644 --- a/drivers/ethernet/eth_nxp_enet.c +++ b/drivers/ethernet/eth_nxp_enet.c @@ -772,9 +772,9 @@ static const struct ethernet_api api_funcs = { #define FREESCALE_OUI_B1 0x04 #define FREESCALE_OUI_B2 0x9f -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) #define ETH_NXP_ENET_UNIQUE_ID (OCOTP->CFG1 ^ OCOTP->CFG2) -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) #define ETH_NXP_ENET_UNIQUE_ID (OCOTP->FUSEN[40].FUSE) #elif defined(CONFIG_SOC_SERIES_KINETIS_K6X) #define ETH_NXP_ENET_UNIQUE_ID (SIM->UIDH ^ SIM->UIDMH ^ SIM->UIDML ^ SIM->UIDL) diff --git a/drivers/ethernet/eth_nxp_s32_gmac.c b/drivers/ethernet/eth_nxp_s32_gmac.c index 67a725d1fc5..e6efb3f72c7 100644 --- a/drivers/ethernet/eth_nxp_s32_gmac.c +++ b/drivers/ethernet/eth_nxp_s32_gmac.c @@ -147,7 +147,7 @@ static void phy_link_state_changed(const struct device *pdev, } } -#if defined(CONFIG_SOC_SERIES_S32K3XX) +#if defined(CONFIG_SOC_SERIES_S32K3) static int select_phy_interface(Gmac_Ip_MiiModeType mode) { uint32_t regval; @@ -174,7 +174,7 @@ static int select_phy_interface(Gmac_Ip_MiiModeType mode) } #else #error "SoC not supported" -#endif /* CONFIG_SOC_SERIES_S32K3XX */ +#endif /* CONFIG_SOC_SERIES_S32K3 */ static int eth_nxp_s32_init(const struct device *dev) { diff --git a/drivers/ethernet/eth_sam_gmac.c b/drivers/ethernet/eth_sam_gmac.c index 80d43f3616c..1b559a9e0dc 100644 --- a/drivers/ethernet/eth_sam_gmac.c +++ b/drivers/ethernet/eth_sam_gmac.c @@ -19,7 +19,7 @@ * - no statistics collection */ -#if defined(CONFIG_SOC_FAMILY_SAM) +#if defined(CONFIG_SOC_FAMILY_ATMEL_SAM) #define DT_DRV_COMPAT atmel_sam_gmac #else #define DT_DRV_COMPAT atmel_sam0_gmac @@ -51,7 +51,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME); #include "eth.h" -#ifdef CONFIG_SOC_FAMILY_SAM0 +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM0 #include "eth_sam0_gmac.h" #endif @@ -97,9 +97,9 @@ static inline void dcache_clean(uint32_t addr, uint32_t size) #define dcache_clean(addr, size) #endif -#ifdef CONFIG_SOC_FAMILY_SAM0 +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM0 #define MCK_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#elif CONFIG_SOC_FAMILY_SAM +#elif CONFIG_SOC_FAMILY_ATMEL_SAM #define MCK_FREQ_HZ SOC_ATMEL_SAM_MCK_FREQ_HZ #else #error Unsupported SoC family @@ -1796,7 +1796,7 @@ static int eth_initialize(const struct device *dev) cfg->config_func(); -#ifdef CONFIG_SOC_FAMILY_SAM +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM /* Enable GMAC module's clock */ (void)clock_control_on(SAM_DT_PMC_CONTROLLER, (clock_control_subsys_t)&cfg->clock_cfg); @@ -2235,7 +2235,7 @@ PINCTRL_DT_INST_DEFINE(0); static const struct eth_sam_dev_cfg eth0_config = { .regs = (Gmac *)DT_INST_REG_ADDR(0), .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), -#ifdef CONFIG_SOC_FAMILY_SAM +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM .clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(0), #endif .config_func = eth0_irq_config, diff --git a/drivers/ethernet/eth_sam_gmac_priv.h b/drivers/ethernet/eth_sam_gmac_priv.h index 21765d5c57f..8fd5a2b257b 100644 --- a/drivers/ethernet/eth_sam_gmac_priv.h +++ b/drivers/ethernet/eth_sam_gmac_priv.h @@ -261,7 +261,7 @@ struct gmac_queue { /* Device constant configuration parameters */ struct eth_sam_dev_cfg { Gmac *regs; -#ifdef CONFIG_SOC_FAMILY_SAM +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM const struct atmel_sam_pmc_config clock_cfg; #endif const struct pinctrl_dev_config *pcfg; diff --git a/drivers/flash/Kconfig.it8xxx2 b/drivers/flash/Kconfig.it8xxx2 index 0302e01e61d..50b881335a4 100644 --- a/drivers/flash/Kconfig.it8xxx2 +++ b/drivers/flash/Kconfig.it8xxx2 @@ -8,6 +8,9 @@ config SOC_FLASH_ITE_IT8XXX2 default y depends on DT_HAS_ITE_IT8XXX2_FLASH_CONTROLLER_ENABLED select SOC_IT8XXX2_USE_ILM + select FLASH_HAS_PAGE_LAYOUT + select FLASH_HAS_DRIVER_ENABLED + select HAS_FLASH_LOAD_OFFSET help The flash driver includes support for read, write and erase flash operations. It also supports protection. diff --git a/drivers/flash/Kconfig.mcux b/drivers/flash/Kconfig.mcux index ec7f5be22b2..52e7220595b 100644 --- a/drivers/flash/Kconfig.mcux +++ b/drivers/flash/Kconfig.mcux @@ -101,30 +101,4 @@ config FLASH_MCUX_FLEXSPI_HYPERFLASH_WRITE_BUFFER This prevents faults when the data to write would be located on the flash itself. -if FLASH_MCUX_FLEXSPI_XIP - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - prompt "FlexSPI drivers relocation target" - default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM - help - Select the location to run the FlexSPI drivers when using - the flash API. - -config FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM - bool "ITCM" - select CODE_DATA_RELOCATION - -config FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM - bool "RAM" - select CODE_DATA_RELOCATION_SRAM - -endchoice - -config FLASH_MCUX_FLEXSPI_XIP_MEM - string - default "ITCM" if FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM - default "RAM" if FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM - -endif # FLASH_MCUX_FLEXSPI_XIP - endif # HAS_MCUX_FLEXSPI diff --git a/drivers/gpio/gpio_mcux_igpio.c b/drivers/gpio/gpio_mcux_igpio.c index fbb8d85b6fb..91ed22b4422 100644 --- a/drivers/gpio/gpio_mcux_igpio.c +++ b/drivers/gpio/gpio_mcux_igpio.c @@ -72,7 +72,7 @@ static int mcux_igpio_configure(const struct device *dev, (volatile uint32_t *)config->pin_muxes[cfg_idx].config_register; uint32_t reg = *gpio_cfg_reg; -#ifdef CONFIG_SOC_SERIES_IMX_RT10XX +#ifdef CONFIG_SOC_SERIES_IMXRT10XX if ((flags & GPIO_SINGLE_ENDED) != 0) { /* Set ODE bit */ reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK; @@ -92,7 +92,7 @@ static int mcux_igpio_configure(const struct device *dev, /* Set pin to keeper */ reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK; } -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) if (config->pin_muxes[pin].pue_mux) { /* PUE type register layout (GPIO_AD pins) */ if ((flags & GPIO_SINGLE_ENDED) != 0) { @@ -152,7 +152,7 @@ static int mcux_igpio_configure(const struct device *dev, } -#elif defined(CONFIG_SOC_SERIES_IMX8MQ_M4) +#elif defined(CONFIG_SOC_MIMX8MQ6_M4) if ((flags & GPIO_SINGLE_ENDED) != 0) { /* Set ODE bit */ reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT); @@ -184,7 +184,7 @@ static int mcux_igpio_configure(const struct device *dev, /* Set pin to highz */ reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT); } -#endif /* CONFIG_SOC_SERIES_IMX_RT10XX */ +#endif /* CONFIG_SOC_SERIES_IMXRT10XX */ memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg.pinmux)); /* cfg register will be set by pinctrl_configure_pins */ diff --git a/drivers/hwinfo/Kconfig b/drivers/hwinfo/Kconfig index 84afbefd84f..81888bd3a78 100644 --- a/drivers/hwinfo/Kconfig +++ b/drivers/hwinfo/Kconfig @@ -66,7 +66,7 @@ config HWINFO_STM32 config HWINFO_NRF bool "NRF device ID" default y - depends on SOC_FAMILY_NRF + depends on SOC_FAMILY_NORDIC_NRF depends on NRF_SOC_SECURE_SUPPORTED help Enable Nordic NRF hwinfo driver. @@ -109,7 +109,7 @@ config HWINFO_MCUX_SYSCON config HWINFO_IMXRT bool "NXP i.mx RT device ID" default y - depends on SOC_SERIES_IMX_RT + depends on SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX help Enable NXP i.mx RT hwinfo driver. @@ -124,14 +124,14 @@ config HWINFO_RPI_PICO config HWINFO_SAM_RSTC bool "Atmel SAM reset cause" default y - depends on SOC_FAMILY_SAM && !SOC_SERIES_SAM4L + depends on SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L help Enable Atmel SAM reset cause hwinfo driver. config HWINFO_SAM bool "Atmel SAM device ID" default y - depends on SOC_FAMILY_SAM && !SOC_SERIES_SAM4L + depends on SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L help Enable Atmel SAM device ID hwinfo driver. @@ -145,28 +145,28 @@ config HWINFO_SAM4L config HWINFO_SAM0 bool "Atmel SAM0 device ID" default y - depends on SOC_FAMILY_SAM0 + depends on SOC_FAMILY_ATMEL_SAM0 help Enable Atmel SAM0 hwinfo driver. config HWINFO_SMARTBOND bool "Smartbond device reset cause" default y - depends on SOC_FAMILY_SMARTBOND + depends on SOC_FAMILY_RENESAS_SMARTBOND help Enable Smartbond reset cause hwinfo driver. config HWINFO_ESP32 bool "ESP32 device ID" default y - depends on SOC_FAMILY_ESP32 + depends on SOC_FAMILY_ESPRESSIF_ESP32 help Enable ESP32 hwinfo driver. config HWINFO_LITEX bool "LiteX device ID" default y - depends on SOC_RISCV32_LITEX_VEXRISCV + depends on SOC_LITEX_VEXRISCV help Enable LiteX hwinfo driver @@ -180,7 +180,7 @@ config HWINFO_PSOC6 config HWINFO_GECKO bool "GECKO hwinfo" default y - depends on SOC_FAMILY_EXX32 && !SOC_SERIES_EFR32MG21 && !SOC_SERIES_EFR32BG22 + depends on SOC_VENDOR_SILABS && !SOC_SERIES_EFR32MG21 && !SOC_SERIES_EFR32BG22 select SOC_GECKO_RMU help Enable Silabs GECKO hwinfo driver. diff --git a/drivers/hwinfo/hwinfo_imxrt.c b/drivers/hwinfo/hwinfo_imxrt.c index 79cc613d51f..ea748482f76 100644 --- a/drivers/hwinfo/hwinfo_imxrt.c +++ b/drivers/hwinfo/hwinfo_imxrt.c @@ -17,7 +17,7 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) { struct imxrt_uid dev_id; -#ifdef CONFIG_SOC_SERIES_IMX_RT11XX +#ifdef CONFIG_SOC_SERIES_IMXRT11XX dev_id.id[0] = sys_cpu_to_be32(OCOTP->FUSEN[17].FUSE); dev_id.id[1] = sys_cpu_to_be32(OCOTP->FUSEN[16].FUSE); #else diff --git a/drivers/i2c/Kconfig.nrfx b/drivers/i2c/Kconfig.nrfx index 78967177a3a..6898d6e42a9 100644 --- a/drivers/i2c/Kconfig.nrfx +++ b/drivers/i2c/Kconfig.nrfx @@ -6,7 +6,7 @@ menuconfig I2C_NRFX bool "nRF TWI nrfx drivers" default y - depends on SOC_FAMILY_NRF + depends on SOC_FAMILY_NORDIC_NRF depends on MULTITHREADING select PINCTRL help diff --git a/drivers/i2s/i2s_mcux_sai.c b/drivers/i2s/i2s_mcux_sai.c index 08bcdbb6343..1ab1677c46a 100644 --- a/drivers/i2s/i2s_mcux_sai.c +++ b/drivers/i2s/i2s_mcux_sai.c @@ -1148,13 +1148,13 @@ static void audio_clock_settings(const struct device *dev) imxrt_audio_codec_pll_init(clock_name, dev_cfg->clk_src, dev_cfg->clk_pre_div, dev_cfg->clk_src_div); - #ifdef CONFIG_SOC_SERIES_IMX_RT11XX + #ifdef CONFIG_SOC_SERIES_IMXRT11XX audioPllConfig.loopDivider = dev_cfg->pll_lp; audioPllConfig.postDivider = dev_cfg->pll_pd; audioPllConfig.numerator = dev_cfg->pll_num; audioPllConfig.denominator = dev_cfg->pll_den; audioPllConfig.ssEnable = false; - #elif defined CONFIG_SOC_SERIES_IMX_RT10XX + #elif defined CONFIG_SOC_SERIES_IMXRT10XX audioPllConfig.src = dev_cfg->pll_src; audioPllConfig.loopDivider = dev_cfg->pll_lp; audioPllConfig.postDivider = dev_cfg->pll_pd; diff --git a/drivers/interrupt_controller/Kconfig.esp32 b/drivers/interrupt_controller/Kconfig.esp32 index dd8599bfbd2..1d88fcb1966 100644 --- a/drivers/interrupt_controller/Kconfig.esp32 +++ b/drivers/interrupt_controller/Kconfig.esp32 @@ -5,7 +5,7 @@ config INTC_ESP32 bool "Interrupt allocator for Xtensa-based Espressif SoCs" - default y if SOC_FAMILY_ESP32 && !SOC_SERIES_ESP32C3 + default y if SOC_FAMILY_ESPRESSIF_ESP32 && !SOC_SERIES_ESP32C3 help Enable custom interrupt allocator for Espressif SoCs based on Xtensa architecture. diff --git a/drivers/led/led_mchp_xec.c b/drivers/led/led_mchp_xec.c index db8bffb83f7..588a8bc2642 100644 --- a/drivers/led/led_mchp_xec.c +++ b/drivers/led/led_mchp_xec.c @@ -12,7 +12,7 @@ */ #include -#ifndef CONFIG_SOC_SERIES_MEC1501X +#ifndef CONFIG_SOC_SERIES_MEC15XX #include #include #endif @@ -207,7 +207,7 @@ static int xec_bbled_off(const struct device *dev, uint32_t led) return 0; } -#ifdef CONFIG_SOC_SERIES_MEC1501X +#ifdef CONFIG_SOC_SERIES_MEC15XX static inline void xec_bbled_slp_en_clr(const struct device *dev) { const struct xec_bbled_config * const cfg = dev->config; diff --git a/drivers/mdio/mdio_sam.c b/drivers/mdio/mdio_sam.c index 5665057f7c9..216e0dd80f4 100644 --- a/drivers/mdio/mdio_sam.c +++ b/drivers/mdio/mdio_sam.c @@ -21,7 +21,7 @@ LOG_MODULE_REGISTER(mdio_sam, CONFIG_MDIO_LOG_LEVEL); /* GMAC */ -#ifdef CONFIG_SOC_FAMILY_SAM0 +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM0 #define GMAC_MAN MAN.reg #define GMAC_NSR NSR.reg #define GMAC_NCR NCR.reg @@ -34,7 +34,7 @@ struct mdio_sam_dev_data { struct mdio_sam_dev_config { Gmac * const regs; const struct pinctrl_dev_config *pcfg; -#ifdef CONFIG_SOC_FAMILY_SAM +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM const struct atmel_sam_pmc_config clock_cfg; #endif }; @@ -144,7 +144,7 @@ static int mdio_sam_initialize(const struct device *dev) k_sem_init(&data->sem, 1, 1); -#ifdef CONFIG_SOC_FAMILY_SAM +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM /* Enable GMAC module's clock */ (void) clock_control_on(SAM_DT_PMC_CONTROLLER, (clock_control_subsys_t) &cfg->clock_cfg); #else @@ -168,7 +168,7 @@ static const struct mdio_driver_api mdio_sam_driver_api = { }; #define MDIO_SAM_CLOCK(n) \ - COND_CODE_1(CONFIG_SOC_FAMILY_SAM, \ + COND_CODE_1(CONFIG_SOC_FAMILY_ATMEL_SAM, \ (.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n),), () \ ) diff --git a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c index 51d176a5fef..b78a247ae01 100644 --- a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c +++ b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c @@ -94,7 +94,7 @@ static uint32_t get_hpsram_bank_idx(uintptr_t pa) */ static uint16_t flags_to_tlb_perms(uint32_t flags) { -#if defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) uint16_t perms = 0; if ((flags & SYS_MM_MEM_PERM_RW) == SYS_MM_MEM_PERM_RW) { @@ -111,7 +111,7 @@ static uint16_t flags_to_tlb_perms(uint32_t flags) #endif } -#if defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) /** * Convert TLB entry permission bits to the SYS_MM_MEM_PERM_* flags. * @@ -136,7 +136,7 @@ static uint16_t tlb_perms_to_flags(uint16_t perms) static int sys_mm_drv_hpsram_pwr(uint32_t bank_idx, bool enable, bool non_blocking) { -#if defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) if (bank_idx > ace_hpsram_get_bank_count()) { return -1; } @@ -484,7 +484,7 @@ int sys_mm_drv_page_flag_get(void *virt, uint32_t *flags) ARG_UNUSED(virt); int ret = 0; -#if defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) uint16_t *tlb_entries = UINT_TO_POINTER(TLB_BASE); uint16_t ent; diff --git a/drivers/pinctrl/pinctrl_gecko.c b/drivers/pinctrl/pinctrl_gecko.c index cdb1118768f..0573ef3a40c 100644 --- a/drivers/pinctrl/pinctrl_gecko.c +++ b/drivers/pinctrl/pinctrl_gecko.c @@ -12,7 +12,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp { USART_TypeDef *base = (USART_TypeDef *)reg; uint8_t loc; -#ifdef CONFIG_SOC_GECKO_SERIES1 +#ifdef CONFIG_SOC_FAMILY_SILABS_S1 LEUART_TypeDef *lebase = (LEUART_TypeDef *)reg; #else int usart_num = USART_NUM(base); @@ -50,7 +50,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp txpin.out); break; -#ifdef CONFIG_SOC_GECKO_SERIES1 +#ifdef CONFIG_SOC_FAMILY_SILABS_S1 case GECKO_FUN_UART_RTS: pin_config.mode = gpioModePushPull; pin_config.out = 1; @@ -100,7 +100,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp lebase->ROUTELOC0 &= ~_LEUART_ROUTELOC0_TXLOC_MASK; lebase->ROUTELOC0 |= (loc << _LEUART_ROUTELOC0_TXLOC_SHIFT); break; -#else /* CONFIG_SOC_GECKO_SERIES1 */ +#else /* CONFIG_SOC_FAMILY_SILABS_S1 */ case GECKO_FUN_UART_LOC: #ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION /* For SOCs with configurable pin_cfg locations (set in SOC Kconfig) */ @@ -156,11 +156,11 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp } #endif /* UART_GECKO_HW_FLOW_CONTROL */ break; -#endif /* CONFIG_SOC_GECKO_SERIES1 */ +#endif /* CONFIG_SOC_FAMILY_SILABS_S1 */ #endif /* CONFIG_UART_GECKO */ #ifdef CONFIG_SPI_GECKO -#ifdef CONFIG_SOC_GECKO_SERIES1 +#ifdef CONFIG_SOC_FAMILY_SILABS_S1 case GECKO_FUN_SPIM_SCK: pin_config.mode = gpioModePushPull; pin_config.out = 1; @@ -241,7 +241,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_CSLOC_SHIFT); break; -#else /* CONFIG_SOC_GECKO_SERIES1 */ +#else /* CONFIG_SOC_FAMILY_SILABS_S1 */ case GECKO_FUN_SPI_SCK: pin_config.mode = gpioModePushPull; pin_config.out = 1; @@ -274,7 +274,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode, pin_config.out); break; -#endif /* CONFIG_SOC_GECKO_SERIES1 */ +#endif /* CONFIG_SOC_FAMILY_SILABS_S1 */ #endif /* CONFIG_SPI_GECKO */ default: diff --git a/drivers/pinctrl/pinctrl_imx.c b/drivers/pinctrl/pinctrl_imx.c index 8959ff4cb58..2996657914c 100644 --- a/drivers/pinctrl/pinctrl_imx.c +++ b/drivers/pinctrl/pinctrl_imx.c @@ -19,7 +19,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uint32_t input_daisy = pins[i].pinmux.input_daisy; uint32_t config_register = pins[i].pinmux.config_register; uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags; -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) || defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) volatile uint32_t *gpr_register = (volatile uint32_t *)((uintptr_t)pins[i].pinmux.gpr_register); if (gpr_register) { @@ -33,7 +33,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, } #endif -#ifdef CONFIG_SOC_MIMX93_A55 +#ifdef CONFIG_SOC_MIMX9352_A55 sys_write32(IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) | IOMUXC1_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)), (mem_addr_t)mux_register); @@ -65,17 +65,17 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, static int imx_pinctrl_init(void) { -#ifdef CONFIG_SOC_SERIES_IMX_RT +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) CLOCK_EnableClock(kCLOCK_Iomuxc); -#ifdef CONFIG_SOC_SERIES_IMX_RT10XX +#ifdef CONFIG_SOC_SERIES_IMXRT10XX CLOCK_EnableClock(kCLOCK_IomuxcSnvs); CLOCK_EnableClock(kCLOCK_IomuxcGpr); -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr); -#endif /* CONFIG_SOC_SERIES_IMX_RT10XX */ +#endif /* CONFIG_SOC_SERIES_IMXRT10XX */ #elif defined(CONFIG_SOC_MIMX8MQ6) CLOCK_EnableClock(kCLOCK_Iomux); -#endif /* CONFIG_SOC_SERIES_IMX_RT */ +#endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */ return 0; } diff --git a/drivers/ps2/Kconfig.xec b/drivers/ps2/Kconfig.xec index 86643b11e84..79dd43cfdcc 100644 --- a/drivers/ps2/Kconfig.xec +++ b/drivers/ps2/Kconfig.xec @@ -5,7 +5,7 @@ config PS2_XEC bool "XEC Microchip PS2 driver" - depends on SOC_FAMILY_MEC && ESPI_PERIPHERAL_8042_KBC + depends on SOC_FAMILY_MICROCHIP_MEC && ESPI_PERIPHERAL_8042_KBC select PINCTRL help Enable the Microchip XEC PS2 IO driver. The driver also diff --git a/drivers/pwm/Kconfig.rcar b/drivers/pwm/Kconfig.rcar index 39d5eeb1c4f..bf8bd912b6a 100644 --- a/drivers/pwm/Kconfig.rcar +++ b/drivers/pwm/Kconfig.rcar @@ -6,7 +6,7 @@ config PWM_RCAR bool "Renesas R-Car PWM Driver" default y - depends on SOC_FAMILY_RCAR + depends on SOC_FAMILY_RENESAS_RCAR depends on DT_HAS_RENESAS_PWM_RCAR_ENABLED help Enable Renesas R-Car PWM Driver. diff --git a/drivers/sensor/mchp_tach_xec/Kconfig b/drivers/sensor/mchp_tach_xec/Kconfig index d0ce0827e40..870f05944b5 100644 --- a/drivers/sensor/mchp_tach_xec/Kconfig +++ b/drivers/sensor/mchp_tach_xec/Kconfig @@ -7,7 +7,7 @@ config TACH_XEC bool "XEC Tachometer sensor" default y depends on DT_HAS_MICROCHIP_XEC_TACH_ENABLED - depends on SOC_FAMILY_MEC + depends on SOC_FAMILY_MICROCHIP_MEC select PINCTRL help Enable the Microchip XEC tachometer sensor. diff --git a/drivers/sensor/qdec_sam/Kconfig b/drivers/sensor/qdec_sam/Kconfig index 32f05769537..45daf9e56a5 100644 --- a/drivers/sensor/qdec_sam/Kconfig +++ b/drivers/sensor/qdec_sam/Kconfig @@ -8,6 +8,6 @@ config QDEC_SAM bool "Atmel SAM QDEC driver" default y depends on DT_HAS_ATMEL_SAM_TC_QDEC_ENABLED - depends on SOC_FAMILY_SAM + depends on SOC_FAMILY_ATMEL_SAM help Atmel SAM MCU family Quadrature Decoder (TC) driver. diff --git a/drivers/serial/Kconfig.gecko b/drivers/serial/Kconfig.gecko index 2330fd401c7..8bc311cd523 100644 --- a/drivers/serial/Kconfig.gecko +++ b/drivers/serial/Kconfig.gecko @@ -10,6 +10,6 @@ config UART_GECKO select SERIAL_HAS_DRIVER select SERIAL_SUPPORT_INTERRUPT select SOC_GECKO_USART - select PINCTRL if SOC_GECKO_SERIES1 + select PINCTRL if SOC_FAMILY_SILABS_S1 help Enable the Gecko uart driver. diff --git a/drivers/serial/uart_mcux_flexcomm.c b/drivers/serial/uart_mcux_flexcomm.c index 4332b20cb91..a15ba82873a 100644 --- a/drivers/serial/uart_mcux_flexcomm.c +++ b/drivers/serial/uart_mcux_flexcomm.c @@ -813,7 +813,7 @@ static void mcux_flexcomm_uart_dma_rx_callback(const struct device *dma_device, data->rx_data.offset = 0; } -#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || defined(CONFIG_SOC_SERIES_IMX_RT6XX) +#if defined(CONFIG_SOC_SERIES_IMXRT5XX) || defined(CONFIG_SOC_SERIES_IMXRT6XX) /* * This functions calculates the inputmux connection value * needed by INPUTMUX_EnableSignal to allow the UART's DMA @@ -825,7 +825,7 @@ static uint32_t fc_uart_calc_inmux_connection(uint8_t channel, DMA_Type *base) uint32_t chmux_sel = 0; uint32_t chmux_val = 0; -#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) +#if defined(CONFIG_SOC_SERIES_IMXRT5XX) uint32_t chmux_sel_id = 0; if (base == (DMA_Type *)DMA0_BASE) { @@ -902,7 +902,7 @@ static int flexcomm_uart_async_init(const struct device *dev) USART_EnableRxDMA(config->base, false); /* Route DMA requests */ -#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || defined(CONFIG_SOC_SERIES_IMX_RT6XX) +#if defined(CONFIG_SOC_SERIES_IMXRT5XX) || defined(CONFIG_SOC_SERIES_IMXRT6XX) /* RT 3 digit uses input mux to route DMA requests from * the UART peripheral to a hardware designated DMA channel */ diff --git a/drivers/spi/Kconfig.nrfx b/drivers/spi/Kconfig.nrfx index 0ee1c03065b..4d158b935a7 100644 --- a/drivers/spi/Kconfig.nrfx +++ b/drivers/spi/Kconfig.nrfx @@ -4,7 +4,7 @@ menuconfig SPI_NRFX bool "nRF SPI nrfx drivers" default y - depends on SOC_FAMILY_NRF + depends on SOC_FAMILY_NORDIC_NRF depends on MULTITHREADING select PINCTRL help diff --git a/drivers/timer/Kconfig.gecko b/drivers/timer/Kconfig.gecko index 7a14af67e6a..cd53f9977b5 100644 --- a/drivers/timer/Kconfig.gecko +++ b/drivers/timer/Kconfig.gecko @@ -3,7 +3,7 @@ config GECKO_BURTC_TIMER bool "SiLabs Gecko BURTC system clock driver" - depends on SOC_GECKO_SERIES2 + depends on SOC_FAMILY_SILABS_S2 depends on DT_HAS_SILABS_GECKO_BURTC_ENABLED select SOC_GECKO_BURTC select TICKLESS_CAPABLE diff --git a/drivers/timer/Kconfig.x86 b/drivers/timer/Kconfig.x86 index aa5f1a9c6d6..ea6d4a216b7 100644 --- a/drivers/timer/Kconfig.x86 +++ b/drivers/timer/Kconfig.x86 @@ -5,7 +5,7 @@ choice prompt "Default System Timer" - default HPET_TIMER if SOC_FAMILY_INTEL_ISH || SOC_IA32 || SOC_LAKEMONT + default HPET_TIMER if SOC_FAMILY_INTEL_ISH || SOC_ATOM || SOC_LAKEMONT default APIC_TSC_DEADLINE_TIMER depends on X86 help diff --git a/drivers/timer/hpet.c b/drivers/timer/hpet.c index 8a7134a762e..de2abf757f8 100644 --- a/drivers/timer/hpet.c +++ b/drivers/timer/hpet.c @@ -14,8 +14,6 @@ #include -#include - /** * @file * @brief HPET (High Precision Event Timers) driver diff --git a/drivers/timer/intel_adsp_timer.c b/drivers/timer/intel_adsp_timer.c index 116a512f8fe..330e5bbd425 100644 --- a/drivers/timer/intel_adsp_timer.c +++ b/drivers/timer/intel_adsp_timer.c @@ -27,7 +27,7 @@ #define COMPARATOR_IDX 0 /* 0 or 1 */ -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE #define TIMER_IRQ ACE_IRQ_TO_ZEPHYR(ACE_INTL_TTS) #else #define TIMER_IRQ DSP_WCT_IRQ(COMPARATOR_IDX) @@ -198,7 +198,7 @@ static void irq_init(void) * (for per-core control) above the interrupt controller. * Drivers need to do that part. */ -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE ACE_DINT[cpu].ie[ACE_INTL_TTS] |= BIT(COMPARATOR_IDX + 1); sys_write32(sys_read32(DSPWCTCS_ADDR) | ADSP_SHIM_DSPWCTCS_TTIE(COMPARATOR_IDX), DSPWCTCS_ADDR); diff --git a/drivers/timer/mchp_xec_rtos_timer.c b/drivers/timer/mchp_xec_rtos_timer.c index 18be700d5a4..b57fee45a39 100644 --- a/drivers/timer/mchp_xec_rtos_timer.c +++ b/drivers/timer/mchp_xec_rtos_timer.c @@ -420,7 +420,7 @@ static int sys_clock_driver_init(void) | MCHP_BTMR_CTRL_COUNT_UP | (47UL << MCHP_BTMR_CTRL_PRESCALE_POS)); -#if CONFIG_SOC_SERIES_MEC1501X +#if CONFIG_SOC_SERIES_MEC15XX mchp_pcr_periph_slp_ctrl(PCR_B32TMR0, 0); #else PCR_XEC_REGS->SLP_EN[BTMR32_0_PCR_REG_IDX] &= ~BIT(BTMR32_0_PCR_BITPOS); diff --git a/drivers/usb/device/usb_dc_mcux.c b/drivers/usb/device/usb_dc_mcux.c index 0667486b628..a4e979d206b 100644 --- a/drivers/usb/device/usb_dc_mcux.c +++ b/drivers/usb/device/usb_dc_mcux.c @@ -76,8 +76,8 @@ static void usb_isr_handler(void); BUILD_ASSERT(NUM_INSTS <= 1, "Only one USB device supported"); /* Controller ID is for HAL usage */ -#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || \ - defined(CONFIG_SOC_SERIES_IMX_RT6XX) || \ +#if defined(CONFIG_SOC_SERIES_IMXRT5XX) || \ + defined(CONFIG_SOC_SERIES_IMXRT6XX) || \ defined(CONFIG_SOC_LPC55S28) || \ defined(CONFIG_SOC_LPC55S16) #define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0 @@ -89,7 +89,7 @@ BUILD_ASSERT(NUM_INSTS <= 1, "Only one USB device supported"); #elif DT_NODE_HAS_STATUS(DT_NODELABEL(usbfs), okay) #define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0 #endif /* LPC55s69 */ -#elif defined(CONFIG_SOC_SERIES_IMX_RT) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) #if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) #define CONTROLLER_ID kUSB_ControllerEhci0 #elif DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) diff --git a/dts/arm/intel_socfpga_std/socfpga_cyclone5.dtsi b/dts/arm/intel_socfpga_std/socfpga_cyclonev.dtsi similarity index 100% rename from dts/arm/intel_socfpga_std/socfpga_cyclone5.dtsi rename to dts/arm/intel_socfpga_std/socfpga_cyclonev.dtsi diff --git a/dts/arm/seeed/lora-e5.dtsi b/dts/arm/seeed_studio/lora-e5.dtsi similarity index 100% rename from dts/arm/seeed/lora-e5.dtsi rename to dts/arm/seeed_studio/lora-e5.dtsi diff --git a/dts/arm/st/f0/stm32f071.dtsi b/dts/arm/st/f0/stm32f071.dtsi index b9547808738..35156176e11 100644 --- a/dts/arm/st/f0/stm32f071.dtsi +++ b/dts/arm/st/f0/stm32f071.dtsi @@ -7,6 +7,15 @@ #include / { + clocks { + clk_hsi48: clk-hsi48 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + status = "disabled"; + }; + }; + soc { compatible = "st,stm32f071", "st,stm32f0", "simple-bus"; @@ -16,15 +25,6 @@ }; }; - clocks { - clk_hsi48: clk-hsi48 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = ; - status = "disabled"; - }; - }; - pinctrl: pin-controller@48000000 { gpioe: gpio@48001000 { compatible = "st,stm32-gpio"; diff --git a/dts/arm/st/f0/stm32f091.dtsi b/dts/arm/st/f0/stm32f091.dtsi index b1ad8f0646e..67497b09d8d 100644 --- a/dts/arm/st/f0/stm32f091.dtsi +++ b/dts/arm/st/f0/stm32f091.dtsi @@ -43,9 +43,9 @@ status = "disabled"; }; - usart8: serial@40011C00 { + usart8: serial@40011c00 { compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40011C00 0x400>; + reg = <0x40011c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>; resets = <&rctl STM32_RESET(APB2, 7U)>; interrupts = <29 0>; diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index ce372c6ed7f..1b5ebf3b30a 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -10,6 +10,8 @@ # # +# zephyr-keep-sorted-start +96boards 96Boards aaeon AAEON Technology Inc. abb ABB abilis Abilis Systems @@ -17,9 +19,10 @@ abracon Abracon Corporation abt ShenZhen Asia Better Technology Ltd. acer Acer Inc. acme Acme Systems srl +aconno aconno GmbH +actinius Actinius B.V. actions Actions Semiconductor Co., Ltd. active-semi Active-Semi International Inc -actinius Actinius B.V. ad Avionic Design GmbH adafruit Adafruit Industries, LLC adapteva Adapteva, Inc. @@ -31,6 +34,7 @@ aeroflexgaisler Aeroflex Gaisler AB aesop AESOP Embedded Forum al Annapurna Labs alcatel Alcatel +alientek Alientek allegro Allegro DVT allo Allo.com allwinner Allwinner Technology Co., Ltd. @@ -38,9 +42,9 @@ alphascale AlphaScale Integrated Circuits Systems, Inc. alps Alps Electric Co., Ltd. alt Altus-Escon-Company BV altr Altera Corp. -ambiq Ambiq Micro, Inc. amarula Amarula Solutions amazon Amazon.com, Inc. +ambiq Ambiq Micro, Inc. amcc Applied Micro Circuits Corporation (APM, formally AMCC) amd Advanced Micro Devices (AMD), Inc. amediatech Shenzhen Amediatech Technology Co., Ltd @@ -58,8 +62,8 @@ apm Applied Micro Circuits Corporation (APM) apple Apple Inc. aptina Aptina Imaging arasan Arasan Chip Systems -archermind ArcherMind Technology (Nanjing) Co., Ltd. arc Synopsys, Inc. (formerly ARC International PLC) +archermind ArcherMind Technology (Nanjing) Co., Ltd. arctic Arctic Sand arcx arcx Inc. / Archronix Inc. arduino Arduino @@ -69,11 +73,12 @@ armadeus ARMadeus Systems SARL arrow Arrow Electronics artesyn Artesyn Embedded Technologies Inc. asahi-kasei Asahi Kasei Corp. -asmedia ASMedia Technology Inc. asc All Sensors Corporation +asmedia ASMedia Technology Inc. aspeed ASPEED Technology Inc. asus AsusTek Computer Inc. atlas Atlas Scientific LLC +atmarktechno Atmark Techno, Inc. atmel Atmel Corporation auo AU Optronics Corporation auvidea Auvidea GmbH @@ -88,6 +93,8 @@ azoteq Azoteq (Pty) Ltd azw Shenzhen AZW Technology Co., Ltd. baikal BAIKAL ELECTRONICS, JSC bananapi BIPAI KEJI LIMITED +bbc BBC +bcdevices Blue Clover Devices beacon Compass Electronics Group, LLC beagle BeagleBoard.org Foundation bhf Beckhoff Automation GmbH & Co. KG @@ -97,11 +104,11 @@ blutek BluTek Power boe BOE Technology Group Co., Ltd. bosch Bosch Sensortec GmbH boundary Boundary Devices Inc. -broadmobi Shanghai Broadmobi Communication Technology Co.,Ltd. brcm Broadcom Corporation +broadmobi Shanghai Broadmobi Communication Technology Co.,Ltd. +bticino Bticino International buffalo Buffalo, Inc. bur B&R Industrial Automation GmbH -bticino Bticino International calaosystems CALAO Systems SAS calxeda Calxeda canaan Canaan, Inc. @@ -124,6 +131,7 @@ chrp Common Hardware Reference Platform chunghwa Chunghwa Picture Tubes Ltd. chuwi Chuwi Innovation Ltd. ciaa Computadora Industrial Abierta Argentina +circuitdojo Circuit Dojo cirrus Cirrus Logic, Inc. cisco Cisco Systems, Inc. cloudengines Cloud Engines, Inc. @@ -131,6 +139,7 @@ cnm Chips&Media, Inc. cnxt Conexant Systems, Inc. colorfly Colorful GRP, Shenzhen Xueyushi Technology Ltd. compulab CompuLab Ltd. +contextualelectronics Contextual Electronics coreriver CORERIVER Semiconductor Co.,Ltd. corpro Chengdu Corpro Technology Co., Ltd. cortina Cortina Systems, Inc. @@ -173,12 +182,14 @@ ea Embedded Artists AB ebang Zhejiang Ebang Communication Co., Ltd ebs-systart EBS-SYSTART GmbH ebv EBV Elektronik +ebyte Chengdu Ebyte Electronic Technology eckelmann Eckelmann AG edt Emerging Display Technologies eeti eGalax_eMPIA Technology Inc efinix Efinix Inc einfochips Einfochips elan Elan Microelectronic Corp. +electronut Electronut Labs element14 Element14 (A Premier Farnell Company) elgin Elgin S/A. elida Shenzhen Elida Technology Co., Ltd. @@ -188,6 +199,7 @@ emlid Emlid, Ltd. emmicro EM Microelectronic empire-electronix Empire Electronix emtrion emtrion GmbH +enclustra Enclustra endless Endless Mobile, Inc. ene ENE Technology, Inc. energymicro Silicon Laboratories (formerly Energy Micro AS) @@ -232,7 +244,7 @@ gd GigaDevice Semiconductor ge General Electric Company geekbuying GeekBuying gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. -GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. +gefanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. gemei Gemei Digital Technology Co., Ltd. geniatech Geniatech, Inc. giantec Giantec Semiconductor, Inc. @@ -252,6 +264,7 @@ hamamatsu Hamamatsu Photonics K.K. hannstar HannStar Display Corporation haoyu Haoyu Microelectronic Co. Ltd. hardkernel Hardkernel Co., Ltd +heltec Chengdu Heltec Automation Technology Co., Ltd. hideep HiDeep Inc. himax Himax Technologies, Inc. hirschmann Hirschmann Automation and Control GmbH @@ -259,13 +272,14 @@ hisilicon Hisilicon Limited. hit Hitachi Ltd. hitex Hitex Development Tools holt Holt Integrated Circuits, Inc. +holtek Holtek Semiconductor, Inc. +holyiot Shenzhen Holyiot Technology Co., Ltd. honestar Honestar Technologies Co., Ltd. honeywell Honeywell hoperf HOPERF Microelectronics Co. Ltd hoperun Jiangsu HopeRun Software Co., Ltd. hp Hewlett Packard hsg HannStar Display Co. -holtek Holtek Semiconductor, Inc. hugsun Shenzhen Hugsun Technology Co. Ltd. hwacom HwaCom Systems Inc. hycon Hycon Technology Corp. @@ -285,15 +299,15 @@ incircuit In-Circuit GmbH inet-tek Shenzhen iNet Mobile Internet Technology Co., Ltd infineon Infineon Technologies inforce Inforce Computing -inventek Inventek Systems -ivo InfoVision Optoelectronics Kunshan Co. Ltd. ingenic Ingenic Semiconductor +innblue innblue UG innolux Innolux Corporation inside-secure INSIDE Secure inspur Inspur Corporation intel Intel Corporation intercontrol Inter Control Group invensense InvenSense Inc. +inventek Inventek Systems inversepath Inverse Path iom Iomega Corporation isee ISEE 2007 S.L. @@ -302,18 +316,20 @@ isil Intersil issi Integrated Silicon Solutions Inc. ite ITE Tech. Inc. itead ITEAD Intelligent Systems Co.Ltd +ivo InfoVision Optoelectronics Kunshan Co. Ltd. iwave iWave Systems Technologies Pvt. Ltd. jdi Japan Display Inc. jedec JEDEC Solid State Technology Association jesurun Shenzhen Jesurun Electronics Business Dept. -jianda Jiandangjing Technology Co., Ltd. jhd Shenzhen Jinghua Displays Electronics Co., Ltd. +jianda Jiandangjing Technology Co., Ltd. kam Kamstrup A/S karo Ka-Ro electronics GmbH keithkoep Keith & Koep GmbH keymile Keymile GmbH khadas Khadas kiebackpeter Kieback & Peter GmbH +kincony KinCony Electronics Co., Ltd. kinetic Kinetic Technologies kingdisplay King & Display Technology Co., Ltd. kingnovel Kingnovel Technology Co., Ltd. @@ -357,10 +373,13 @@ loongson Loongson Technology Corporation Limited lowrisc lowRISC Community Interest Company lsi LSI Corp. (LSI Logic) ltr LiteOn OptoElectronics +luatos LuatOS Team lwn Liebherr-Werk Nenzing GmbH lxa Linux Automation GmbH m5stack M5Stack macnica Macnica Americas +madmachine Shenzhen FeiKaiTe Technology Co., Ltd. +makerdiary Shenzhen Zaowubang Technology Co., Ltd. mantix Mantix Display Technology Co.,Ltd. mapleboard Mapleboard.org marvell Marvell Technology Group Ltd. @@ -409,6 +428,7 @@ mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) multi-inno Multi-Inno Technology Co.,Ltd mundoreader Mundo Reader S.L. murata Murata Manufacturing Co., Ltd. +mxchip Shanghai MXCHIP Information Technology Co., Ltd. mxicy Macronix International Co., Ltd. myir MYIR Tech Limited national National Semiconductor @@ -420,9 +440,9 @@ netron-dy Netron DY netronix Netronix, Inc. netxeon Shenzhen Netxeon Technology CO., LTD neweast Guangdong Neweast Optoelectronics CO., LTD +newhaven Newhaven Display International nexbox Nexbox nextthing Next Thing Co. -newhaven Newhaven Display International ni National Instruments nintendo Nintendo nlt NLT Technologies, Ltd. @@ -430,8 +450,8 @@ nokia Nokia nordic Nordic Semiconductor noritake Noritake Co., Inc. Electronics Division novtech NovTech, Inc. -nutsboard NutsBoard nuclei Nuclei System Technology +nutsboard NutsBoard nuvoton Nuvoton Technology Corporation nvd New Vision Display nvidia NVIDIA @@ -442,7 +462,6 @@ okaya Okaya Electric America, Inc. oki Oki Electric Industry Co., Ltd. olimex OLIMEX Ltd. olpc One Laptop Per Child -ovti OmniVision Technologies Co., Ltd. onion Onion Corporation onnn ON Semiconductor Corp. ontat On Tat Industrial Company @@ -453,19 +472,20 @@ openrisc OpenRISC.io openthread OpenThread.io option Option NV oranth Shenzhen Oranth Technology Co., Ltd. -ORCL Oracle Corporation +orcl Oracle Corporation orisetech Orise Technology ortustech Ortus Technology Co., Ltd. osddisplays OSD Displays ouya Ouya Inc. overkiz Overkiz SAS ovti OmniVision Technologies +ovti OmniVision Technologies Co., Ltd. oxsemi Oxford Semiconductor, Ltd. ozzmaker OzzMaker panasonic Panasonic Corporation parade Parade Technologies Inc. -particle Particle.io parallax Parallax Inc. +particle Particle.io pda Precision Design Associates, Inc. pericom Pericom Technology Inc. pervasive Pervasive Displays, Inc. @@ -476,6 +496,7 @@ pine64 Pine64 pineriver Shenzhen PineRiver Designs Co., Ltd. pixart PixArt Imaging Inc. pixcir PIXCIR MICROELECTRONICS Co., Ltd +pjrc PJRC plantower Plantower Co., Ltd plathome Plat'Home Co., Ltd. plda PLDA @@ -499,38 +520,41 @@ qca Qualcomm Atheros, Inc. qcom Qualcomm Technologies, Inc qemu QEMU, a generic and open source machine emulator and virtualizer qi Qi Hardware -qihua Chengdu Kaixuan Information Technology Co., Ltd. qiaodian QiaoDian XianShi Corporation +qihua Chengdu Kaixuan Information Technology Co., Ltd. qnap QNAP Systems, Inc. qorvo Qorvo, Inc. quectel Quectel Wireless Solutions Co., Ltd. quicklogic QuickLogic Corp. radxa Radxa raidsonic RaidSonic Technology GmbH +rakwireless RAKwireless Technology Limited ralink Mediatek/Ralink Technology Corp. ramtron Ramtron International raspberrypi Raspberry Pi Foundation raydium Raydium Semiconductor Corp. +raytac Raytac Corporation rda Unisoc Communications, Inc. realtek Realtek Semiconductor Corp. remarkable reMarkable AS renesas Renesas Electronics Corporation renode Antmicro's open source simulation and virtual development framework -rex iMX6 Rex Project rervision Shenzhen Rervision Technology Co., Ltd. revotics Revolution Robotics, Inc. (Revotics) +rex iMX6 Rex Project richtek Richtek Technology Corporation ricoh Ricoh Co. Ltd. rikomagic Rikomagic Tech Corp. Ltd -riscv RISC-V Foundation riot Embest RIoT +riscv RISC-V Foundation rockchip Fuzhou Rockchip Electronics Co., Ltd rocktech ROCKTECH DISPLAYS LIMITED rohm ROHM Semiconductor Co., Ltd ronbo Ronbo Electronics +ronoth Ronoth roofull Shenzhen Roofull Technology Co, Ltd -ruuvi Ruuvi Innovations Ltd (Oy) roseapplepi RoseapplePi.org +ruuvi Ruuvi Innovations Ltd (Oy) samsung Samsung Semiconductor samtec Samtec/Softing company sancloud Sancloud Ltd @@ -538,11 +562,12 @@ sandisk Sandisk Corporation satoz Satoz International Co., Ltd sbs Smart Battery System sc Space Cubics, LLC -sciosense Sciosense B.V. schindler Schindler +sciosense Sciosense B.V. seagate Seagate Technology PLC -segger SEGGER Microcontroller GmbH +seco SECO S.p.A. seeed Seeed Technology Co., Ltd +segger SEGGER Microcontroller GmbH seirobotics Shenzhen SEI Robotics Co., Ltd semtech Semtech Corporation sensirion Sensirion AG @@ -556,6 +581,7 @@ shimafuji Shimafuji Electric, Inc. shiratech Shiratech Solutions si-en Si-En Technology Ltd. si-linux Silicon Linux Corporation +siemens Siemens AG sifive SiFive, Inc. sigma Sigma Designs, Inc. sii Seiko Instruments, Inc. @@ -566,7 +592,7 @@ silergy Silergy Corp. silex-insight Silex Insight siliconfile Siliconfile Technologies lnc. siliconmitus Silicon Mitus, Inc. -siemens Siemens AG +silvaco Silvaco, Inc. simcom SIMCom Wireless Solutions Co., LTD simtek Cypress Semiconductor Corporation (Simtek Corporation) sinlinx Sinlinx Electronics Technology Co., LTD @@ -580,12 +606,13 @@ skyworks Skyworks Solutions, Inc. smartlabs SmartLabs LLC smsc Standard Microsystems Corporation snps Synopsys, Inc. -starfive StarFive Technology Co. Ltd. sochip Shenzhen SoChip Technology Co., Ltd. socionext Socionext Inc. +solderparty Solder Party AB solidrun SolidRun solomon Solomon Systech Limited sony Sony Corporation +spacecubics Space Cubics, LLC spansion Spansion Inc. sparkfun SparkFun Electronics sprd Spreadtrum Communications Inc. @@ -593,16 +620,16 @@ sqn Sequans Communications sst Silicon Storage Technology, Inc. sstar Xiamen Xingchen(SigmaStar) Technology Co., Ltd. (formerly part of MStar Semiconductor, Inc.) st STMicroelectronics +st-ericsson ST-Ericsson +starfive StarFive Technology Co. Ltd. starry Starry Electronic Technology (ShenZhen) Co., LTD startek Startek ste ST-Ericsson stericsson ST-Ericsson -st-ericsson ST-Ericsson summit Summit microelectronics sunchip Shenzhen Sunchip Technology Co., Ltd -SUNW Sun Microsystems, Inc +sunw Sun Microsystems, Inc supermicro Super Micro Computer, Inc. -silvaco Silvaco, Inc. swir Sierra Wireless syna Synaptics Inc. synology Synology, Inc. @@ -615,10 +642,10 @@ tdk TDK Corporation. tdo Shangai Top Display Optoelectronics Co., Ltd technexion TechNexion technologic Technologic Systems +techstar Shenzhen Techstar Electronics Co., Ltd. telink Telink Semiconductor telit Telit Cinterion tempo Tempo Semiconductor -techstar Shenzhen Techstar Electronics Co., Ltd. terasic Terasic Inc. tfc Three Five Corp thine THine Electronics, Inc. @@ -641,13 +668,12 @@ tq TQ-Systems GmbH tronfy Tronfy tronsmart Tronsmart truly Truly Semiconductors Limited -visionox Visionox tsd Theobroma Systems Design und Consulting GmbH tyan Tyan Computer Corporation u-blox u-blox u-boot U-Boot bootloader -ucrobotics uCRobotics ubnt Ubiquiti Networks +ucrobotics uCRobotics udoo Udoo ugoos Ugoos Industrial Co., Ltd. ultrachip UltraChip Inc. @@ -660,15 +686,18 @@ v3 V3 Semiconductor vaisala Vaisala vamrs Vamrs Ltd. variscite Variscite Ltd. +vcc-gnd VCC-GND Studio vdl Van der Laan b.v. via VIA Technologies, Inc. videostrong Videostrong Technology Co., Ltd. virtio Virtual I/O Device Specification, developed by the OASIS consortium virtual Used for virtual device without specific vendor. vishay Vishay Intertechnology, Inc +visionox Visionox vitesse Vitesse Semiconductor Corporation vivante Vivante Corporation vnd A stand-in for a real vendor which can be used in examples and tests +vngiotlab VNGIoTLab vocore VoCore Studio voipac Voipac Technologies s.r.o. vot Vision Optical Technology Co., Ltd. @@ -678,6 +707,7 @@ waveshare Waveshare Electronics wd Western Digital Corp. we Würth Elektronik GmbH. weact WeAct Studio +wemos WEMOS Electronics wetek WeTek Electronics, limited. wexler Wexler whwave Shenzhen whwave Electronics, Inc. @@ -693,6 +723,7 @@ wnc Wistron NeWeb Corporation wobo Wobo wolfson Cirrus Logic, Inc. (formerly Wolfson Microelectronics plc) worldsemi Worldsemi Co., Limited +wurth Wurth Elektronik x-powers X-Powers xen Xen Hypervisor xes Extreme Engineering Solutions (X-ES) @@ -714,8 +745,8 @@ yna YSH & ATIL yones-toptech Yones Toptech Co., Ltd. ys Shenzhen Yashi Changhua Intelligent Technology Co., Ltd. ysoft Y Soft Corporation a.s. -zealz Zealz zarlink Zarlink Semiconductor +zealz Zealz zeitec ZEITEC Semiconductor Co., LTD. zephyr Zephyr-specific binding zidoo Shenzhen Zidoo Technology Co., Ltd. @@ -724,3 +755,4 @@ zinitix Zinitix Co., Ltd zkmagic Shenzhen Zkmagic Technology Co., Ltd. zte ZTE Corp. zyxel ZyXEL Communications Corp. +# zephyr-keep-sorted-stop diff --git a/dts/x86/intel/ia32.dtsi b/dts/x86/intel/atom.dtsi similarity index 100% rename from dts/x86/intel/ia32.dtsi rename to dts/x86/intel/atom.dtsi diff --git a/include/zephyr/drivers/pinctrl/pinctrl_soc_sam_common.h b/include/zephyr/drivers/pinctrl/pinctrl_soc_sam_common.h index 2dc7e53b13e..214b08b26f5 100644 --- a/include/zephyr/drivers/pinctrl/pinctrl_soc_sam_common.h +++ b/include/zephyr/drivers/pinctrl/pinctrl_soc_sam_common.h @@ -38,14 +38,14 @@ typedef uint32_t pinctrl_soc_pin_t; * @param prop Property name. * @param idx Property entry index. */ -#if defined(CONFIG_SOC_FAMILY_SAM) +#if defined(CONFIG_SOC_FAMILY_ATMEL_SAM) #define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ ((DT_PROP_BY_IDX(node_id, prop, idx) << SAM_PINCTRL_PINMUX_POS) \ | (DT_PROP(node_id, bias_pull_up) << SAM_PINCTRL_PULLUP_POS) \ | (DT_PROP(node_id, bias_pull_down) << SAM_PINCTRL_PULLDOWN_POS) \ | (DT_PROP(node_id, drive_open_drain) << SAM_PINCTRL_OPENDRAIN_POS) \ ), -#else /* CONFIG_SOC_FAMILY_SAM0 */ +#else /* CONFIG_SOC_FAMILY_ATMEL_SAM0 */ #define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ ((DT_PROP_BY_IDX(node_id, prop, idx) << SAM_PINCTRL_PINMUX_POS) \ | (DT_PROP(node_id, bias_pull_up) << SAM_PINCTRL_PULLUP_POS) \ diff --git a/modules/Kconfig.atmel b/modules/Kconfig.atmel index 980762585dd..a5605146ad9 100644 --- a/modules/Kconfig.atmel +++ b/modules/Kconfig.atmel @@ -6,7 +6,7 @@ config ASF bool select HAS_CMSIS_CORE - depends on SOC_FAMILY_SAM || SOC_FAMILY_SAM0 + depends on SOC_FAMILY_ATMEL_SAM || SOC_FAMILY_ATMEL_SAM0 config ATMEL_WINC1500 bool diff --git a/modules/Kconfig.esp32 b/modules/Kconfig.esp32 index 4022f7534b0..eec39d1dbf7 100644 --- a/modules/Kconfig.esp32 +++ b/modules/Kconfig.esp32 @@ -3,4 +3,4 @@ config HAS_ESPRESSIF_HAL bool - depends on SOC_FAMILY_ESP32 + depends on SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/modules/Kconfig.imx b/modules/Kconfig.imx index 5b387f1e9a5..80e4b3434a5 100644 --- a/modules/Kconfig.imx +++ b/modules/Kconfig.imx @@ -6,7 +6,7 @@ config HAS_IMX_HAL bool select HAS_CMSIS_CORE - depends on SOC_FAMILY_IMX + depends on SOC_FAMILY_NXP_IMX if HAS_IMX_HAL diff --git a/modules/Kconfig.infineon b/modules/Kconfig.infineon index 7ca374f4f32..fc39318c8b2 100644 --- a/modules/Kconfig.infineon +++ b/modules/Kconfig.infineon @@ -6,7 +6,7 @@ config HAS_XMCLIB bool select HAS_CMSIS_CORE - depends on SOC_FAMILY_XMC + depends on SOC_FAMILY_INFINEON_XMC if HAS_XMCLIB diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux index fb5b18a63d3..21658c1ebd0 100644 --- a/modules/Kconfig.mcux +++ b/modules/Kconfig.mcux @@ -5,11 +5,16 @@ config HAS_MCUX bool - depends on SOC_FAMILY_KINETIS || SOC_FAMILY_IMX || SOC_FAMILY_LPC || \ - SOC_FAMILY_NXP_ADSP || SOC_FAMILY_NXP_S32 - + depends on SOC_FAMILY_KINETIS || SOC_FAMILY_NXP_IMX || SOC_FAMILY_LPC || \ + SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT if HAS_MCUX +config MCUX_CORE_SUFFIX + string + help + String describing the core identifer used by MCUX SDK when using + dual core parts + config HAS_MCUX_12B1MSPS_SAR bool help diff --git a/modules/Kconfig.silabs b/modules/Kconfig.silabs index 8abab8b1dd7..0078bfc0b98 100644 --- a/modules/Kconfig.silabs +++ b/modules/Kconfig.silabs @@ -6,4 +6,4 @@ config HAS_SILABS_GECKO bool select HAS_CMSIS_CORE - depends on SOC_FAMILY_EXX32 + depends on SOC_VENDOR_SILABS diff --git a/modules/Kconfig.vega b/modules/Kconfig.vega index 2e4fbf01cad..ba16ae5c523 100644 --- a/modules/Kconfig.vega +++ b/modules/Kconfig.vega @@ -3,7 +3,7 @@ config VEGA_SDK_HAL bool "RV32M1 VEGA SDK support" - depends on SOC_OPENISA_RV32M1_RISCV32 + depends on SOC_OPENISA_RV32M1 config HAS_RV32M1_LPUART bool diff --git a/modules/hal_nxp/CMakeLists.txt b/modules/hal_nxp/CMakeLists.txt index 01e6d58ccae..2f2e53d22ea 100644 --- a/modules/hal_nxp/CMakeLists.txt +++ b/modules/hal_nxp/CMakeLists.txt @@ -15,4 +15,12 @@ if(CONFIG_HAS_MCUX OR CONFIG_HAS_IMX_HAL OR CONFIG_HAS_NXP_S32_HAL) zephyr_compile_definitions_ifdef(CONFIG_CAN_MCUX_FLEXCAN FLEXCAN_WAIT_TIMEOUT=${CONFIG_CAN_MCUX_FLEXCAN_WAIT_TIMEOUT}) + + if(CONFIG_CPU_HAS_DCACHE) + zephyr_compile_definitions_ifdef(CONFIG_ENTROPY_MCUX_CAAM CACHE_MODE_WRITE_THROUGH) + endif() + + if(CONFIG_NOCACHE_MEMORY) + zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER DATA_SECTION_IS_CACHEABLE=1) + endif() endif() diff --git a/modules/trusted-firmware-m/CMakeLists.txt b/modules/trusted-firmware-m/CMakeLists.txt index 2ca875c4df2..146d1751203 100644 --- a/modules/trusted-firmware-m/CMakeLists.txt +++ b/modules/trusted-firmware-m/CMakeLists.txt @@ -201,7 +201,7 @@ if (CONFIG_BUILD_WITH_TFM) ${TFM_INTERFACE_SOURCE_DIR}/tfm_ps_api.c ${TFM_INTERFACE_SOURCE_DIR}/tfm_tz_psa_ns_api.c - # Specific to nordic_nrf platform + # Specific to nordic platform ${TFM_INTERFACE_SOURCE_DIR}/tfm_ioctl_core_ns_api.c ) @@ -226,7 +226,7 @@ if (CONFIG_BUILD_WITH_TFM) string(REPLACE "toolchain" "toolchain_ns" TFM_TOOLCHAIN_NS_FILE ${TFM_TOOLCHAIN_FILE}) - if(CONFIG_BOARD_LPCXPRESSO55S69_CPU0) + if(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0) # Supply path to NXP HAL sources used for TF-M build set(TFM_PLATFORM_NXP_HAL_FILE_PATH ${ZEPHYR_TRUSTED_FIRMWARE_M_MODULE_DIR}/platform/ext/target/nxp/) list(APPEND TFM_CMAKE_ARGS -DTFM_PLATFORM_NXP_HAL_FILE_PATH=${TFM_PLATFORM_NXP_HAL_FILE_PATH}) @@ -358,7 +358,7 @@ if (CONFIG_BUILD_WITH_TFM) zephyr_library_sources(${TFM_INTERFACE_SOURCE_DIR}/tfm_tz_psa_ns_api.c) - if(CONFIG_SOC_FAMILY_NRF) + if(CONFIG_SOC_FAMILY_NORDIC_NRF) zephyr_library_sources_ifdef(CONFIG_TFM_PARTITION_PLATFORM ${TFM_INTERFACE_SOURCE_DIR}/tfm_ioctl_core_ns_api.c) endif() diff --git a/modules/trusted-firmware-m/Kconfig.tfm b/modules/trusted-firmware-m/Kconfig.tfm index 277dd8a8d09..6d3b8a40c04 100644 --- a/modules/trusted-firmware-m/Kconfig.tfm +++ b/modules/trusted-firmware-m/Kconfig.tfm @@ -9,17 +9,17 @@ config ZEPHYR_TRUSTED_FIRMWARE_M_MODULE config TFM_BOARD string - default "nxp/lpcxpresso55s69" if BOARD_LPCXPRESSO55S69_CPU0 + default "nxp/lpcxpresso55s69" if BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 default "arm/mps2/an521" if BOARD_MPS2_AN521_CPU0_NS default "arm/mps3/an547" if BOARD_MPS3_AN547 default "stm/b_u585i_iot02a" if BOARD_B_U585I_IOT02A default "stm/nucleo_l552ze_q" if BOARD_NUCLEO_L552ZE_Q default "stm/stm32l562e_dk" if BOARD_STM32L562E_DK - default "arm/musca_b1" if BOARD_MUSCA_B1 - default "arm/musca_s1" if BOARD_MUSCA_S1 - default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic_nrf/nrf9160" if SOC_NRF9160 - default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic_nrf/nrf9120" if SOC_NRF9120 - default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp" if SOC_NRF5340_CPUAPP + default "arm/musca_b1" if BOARD_V2M_MUSCA_B1 + default "arm/musca_s1" if BOARD_V2M_MUSCA_S1 + default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf9160" if SOC_NRF9160 + default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf9120" if SOC_NRF9120 + default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf5340_cpuapp" if SOC_NRF5340_CPUAPP help The board name used for building TFM. Building with TFM requires that TFM has been ported to the given board/SoC. @@ -43,7 +43,7 @@ menuconfig BUILD_WITH_TFM them, are generated during the normal Zephyr build process. Notes: - Building with the "_ns" BOARD variant (e.g. "mps2_an521_ns") + Building with the "/ns" BOARD variant (e.g. "mps2/an521/cpu0/ns") ensures that CONFIG_TRUSTED_EXECUTION_NONSECURE is enabled. By default we allow Zephyr preemptible threads be preempted diff --git a/modules/trusted-firmware-m/nordic_nrf/CMakeLists.txt b/modules/trusted-firmware-m/nordic/CMakeLists.txt similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/CMakeLists.txt rename to modules/trusted-firmware-m/nordic/CMakeLists.txt diff --git a/modules/trusted-firmware-m/nordic_nrf/include/RTE_Device.h b/modules/trusted-firmware-m/nordic/include/RTE_Device.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/RTE_Device.h rename to modules/trusted-firmware-m/nordic/include/RTE_Device.h diff --git a/modules/trusted-firmware-m/nordic_nrf/include/device_cfg.h b/modules/trusted-firmware-m/nordic/include/device_cfg.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/device_cfg.h rename to modules/trusted-firmware-m/nordic/include/device_cfg.h diff --git a/modules/trusted-firmware-m/nordic_nrf/include/tfm_ioctl_api.h b/modules/trusted-firmware-m/nordic/include/tfm_ioctl_api.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/tfm_ioctl_api.h rename to modules/trusted-firmware-m/nordic/include/tfm_ioctl_api.h diff --git a/modules/trusted-firmware-m/nordic_nrf/include/tfm_peripherals_config.h b/modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/tfm_peripherals_config.h rename to modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h diff --git a/modules/trusted-firmware-m/nordic_nrf/include/tfm_read_ranges.h b/modules/trusted-firmware-m/nordic/include/tfm_read_ranges.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/tfm_read_ranges.h rename to modules/trusted-firmware-m/nordic/include/tfm_read_ranges.h diff --git a/modules/trusted-firmware-m/nordic_nrf/include/util/array.h b/modules/trusted-firmware-m/nordic/include/util/array.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/util/array.h rename to modules/trusted-firmware-m/nordic/include/util/array.h diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/CMakeLists.txt b/modules/trusted-firmware-m/nordic/nrf5340_cpuapp/CMakeLists.txt similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/CMakeLists.txt rename to modules/trusted-firmware-m/nordic/nrf5340_cpuapp/CMakeLists.txt diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/config.cmake b/modules/trusted-firmware-m/nordic/nrf5340_cpuapp/config.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/config.cmake rename to modules/trusted-firmware-m/nordic/nrf5340_cpuapp/config.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/cpuarch.cmake b/modules/trusted-firmware-m/nordic/nrf5340_cpuapp/cpuarch.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/cpuarch.cmake rename to modules/trusted-firmware-m/nordic/nrf5340_cpuapp/cpuarch.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/ns/cpuarch_ns.cmake b/modules/trusted-firmware-m/nordic/nrf5340_cpuapp/ns/cpuarch_ns.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/ns/cpuarch_ns.cmake rename to modules/trusted-firmware-m/nordic/nrf5340_cpuapp/ns/cpuarch_ns.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9120/CMakeLists.txt b/modules/trusted-firmware-m/nordic/nrf9120/CMakeLists.txt similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9120/CMakeLists.txt rename to modules/trusted-firmware-m/nordic/nrf9120/CMakeLists.txt diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9120/config.cmake b/modules/trusted-firmware-m/nordic/nrf9120/config.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9120/config.cmake rename to modules/trusted-firmware-m/nordic/nrf9120/config.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9120/cpuarch.cmake b/modules/trusted-firmware-m/nordic/nrf9120/cpuarch.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9120/cpuarch.cmake rename to modules/trusted-firmware-m/nordic/nrf9120/cpuarch.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9120/ns/cpuarch_ns.cmake b/modules/trusted-firmware-m/nordic/nrf9120/ns/cpuarch_ns.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9120/ns/cpuarch_ns.cmake rename to modules/trusted-firmware-m/nordic/nrf9120/ns/cpuarch_ns.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9160/CMakeLists.txt b/modules/trusted-firmware-m/nordic/nrf9160/CMakeLists.txt similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9160/CMakeLists.txt rename to modules/trusted-firmware-m/nordic/nrf9160/CMakeLists.txt diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9160/config.cmake b/modules/trusted-firmware-m/nordic/nrf9160/config.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9160/config.cmake rename to modules/trusted-firmware-m/nordic/nrf9160/config.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9160/cpuarch.cmake b/modules/trusted-firmware-m/nordic/nrf9160/cpuarch.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9160/cpuarch.cmake rename to modules/trusted-firmware-m/nordic/nrf9160/cpuarch.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9160/ns/cpuarch_ns.cmake b/modules/trusted-firmware-m/nordic/nrf9160/ns/cpuarch_ns.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9160/ns/cpuarch_ns.cmake rename to modules/trusted-firmware-m/nordic/nrf9160/ns/cpuarch_ns.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/ns/CMakeLists.txt b/modules/trusted-firmware-m/nordic/ns/CMakeLists.txt similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/ns/CMakeLists.txt rename to modules/trusted-firmware-m/nordic/ns/CMakeLists.txt diff --git a/modules/trusted-firmware-m/nordic_nrf/src/tfm_hal_platform.c b/modules/trusted-firmware-m/nordic/src/tfm_hal_platform.c similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/src/tfm_hal_platform.c rename to modules/trusted-firmware-m/nordic/src/tfm_hal_platform.c diff --git a/modules/trusted-firmware-m/nordic_nrf/src/tfm_platform_system.c b/modules/trusted-firmware-m/nordic/src/tfm_platform_system.c similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/src/tfm_platform_system.c rename to modules/trusted-firmware-m/nordic/src/tfm_platform_system.c diff --git a/samples/application_development/code_relocation_nocopy/README.rst b/samples/application_development/code_relocation_nocopy/README.rst index 8ad98bb8af7..f8ac178a7e9 100644 --- a/samples/application_development/code_relocation_nocopy/README.rst +++ b/samples/application_development/code_relocation_nocopy/README.rst @@ -27,7 +27,7 @@ To build and flash the application (including the external memory part): .. zephyr-app-commands:: :zephyr-app: samples/application_development/code_relocation_nocopy - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build flash :compact: @@ -41,4 +41,4 @@ Execution output: Address of var_ext_sram_data 0x200000a0 (10) Address of function_in_sram 0x20000001 Address of var_sram_data 0x200000a4 (10) - Hello World! nrf5340dk_nrf5340_cpuapp + Hello World! nrf5340dk/nrf5340/cpuapp diff --git a/samples/application_development/code_relocation_nocopy/sample.yaml b/samples/application_development/code_relocation_nocopy/sample.yaml index 2504f0838c9..b9415221e24 100644 --- a/samples/application_development/code_relocation_nocopy/sample.yaml +++ b/samples/application_development/code_relocation_nocopy/sample.yaml @@ -5,7 +5,7 @@ tests: sample.application_development.code_relocation_nocopy: platform_allow: - qemu_cortex_m3 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp integration_platforms: - qemu_cortex_m3 tags: linker diff --git a/samples/application_development/sysbuild/with_mcuboot/README.rst b/samples/application_development/sysbuild/with_mcuboot/README.rst index 293236146bb..2f9078cab9c 100644 --- a/samples/application_development/sysbuild/with_mcuboot/README.rst +++ b/samples/application_development/sysbuild/with_mcuboot/README.rst @@ -45,7 +45,7 @@ Execution output: *** Booting Zephyr OS build v3.2.0-rc3-209-gdcf4201d3573 *** *** Booting Zephyr OS build v3.2.0-rc3-209-gdcf4201d3573 *** Address of sample 0xc000 - Hello sysbuild with mcuboot! nrf52840dk_nrf52840 + Hello sysbuild with mcuboot! nrf52840dk The first ``Booting Zephyr OS build`` is printed by MCUboot itself and the following lines are printed by the ``with_mcuboot`` sample. diff --git a/samples/application_development/sysbuild/with_mcuboot/sample.yaml b/samples/application_development/sysbuild/with_mcuboot/sample.yaml index 90aea4e0541..785bc0d2400 100644 --- a/samples/application_development/sysbuild/with_mcuboot/sample.yaml +++ b/samples/application_development/sysbuild/with_mcuboot/sample.yaml @@ -8,9 +8,9 @@ tests: # filtering support, see discussion in #49552. platform_allow: - reel_board - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: mcuboot harness: console harness_config: diff --git a/samples/arch/smp/pktqueue/sample.yaml b/samples/arch/smp/pktqueue/sample.yaml index 890d36653d6..f819e6ce576 100644 --- a/samples/arch/smp/pktqueue/sample.yaml +++ b/samples/arch/smp/pktqueue/sample.yaml @@ -18,13 +18,5 @@ tests: depends_on: - smp filter: (CONFIG_MP_MAX_NUM_CPUS > 1) - platform_exclude: - - esp32_devkitc_wroom - - esp_wrover_kit - - esp32_ethernet_kit - - heltec_wifi_lora32_v2 - - m5stickc_plus - - odroid_go - - olimex_esp32_evb integration_platforms: - qemu_x86_64 diff --git a/samples/basic/blinky_pwm/README.rst b/samples/basic/blinky_pwm/README.rst index f31c65982fb..5999e9063b4 100644 --- a/samples/basic/blinky_pwm/README.rst +++ b/samples/basic/blinky_pwm/README.rst @@ -67,11 +67,11 @@ To build and flash this sample for the :ref:`nrf52840dk_nrf52840`: .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky_pwm - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: -Change ``nrf52840dk_nrf52840`` appropriately for other supported boards. +Change ``nrf52840dk/nrf52840`` appropriately for other supported boards. After flashing, the sample starts blinking the LED as described above. It also prints information to the board's console. diff --git a/samples/basic/blinky_pwm/boards/mimxrt685_evk_cm33.overlay b/samples/basic/blinky_pwm/boards/mimxrt685_evk.overlay similarity index 100% rename from samples/basic/blinky_pwm/boards/mimxrt685_evk_cm33.overlay rename to samples/basic/blinky_pwm/boards/mimxrt685_evk.overlay diff --git a/samples/basic/blinky_pwm/boards/rcar_h3ulcb_cr7.overlay b/samples/basic/blinky_pwm/boards/rcar_h3ulcb_r8a77951_r7.overlay similarity index 100% rename from samples/basic/blinky_pwm/boards/rcar_h3ulcb_cr7.overlay rename to samples/basic/blinky_pwm/boards/rcar_h3ulcb_r8a77951_r7.overlay diff --git a/samples/basic/blinky_pwm/boards/rpi_pico.overlay b/samples/basic/blinky_pwm/boards/rpi_pico.overlay index c3a3f1ff5d3..2487fc181f1 100644 --- a/samples/basic/blinky_pwm/boards/rpi_pico.overlay +++ b/samples/basic/blinky_pwm/boards/rpi_pico.overlay @@ -1,3 +1,11 @@ +/* The rpi_pico/rp2040/w doesn't have a pwm. */ +/* Use the HAS_DT_PWM defined by the based board to identify when this overlay is valid */ +#if HAS_DT_PWM_LED + +&{/pwm_leds} { + status = "okay"; +}; + &pwm_led0 { status = "okay"; }; @@ -7,3 +15,5 @@ divider-frac-4 = <15>; divider-int-4 = <255>; }; + +#endif diff --git a/samples/basic/button/sample.yaml b/samples/basic/button/sample.yaml index b0c748d6be2..b2d76330fcf 100644 --- a/samples/basic/button/sample.yaml +++ b/samples/basic/button/sample.yaml @@ -7,6 +7,6 @@ tests: - gpio filter: dt_enabled_alias_with_parent_compat("sw0", "gpio-keys") integration_platforms: - - nrf52833dk_nrf52820 + - nrf52833dk/nrf52820 depends_on: gpio harness: button diff --git a/samples/basic/fade_led/README.rst b/samples/basic/fade_led/README.rst index 4e855548704..2b569f6d5a5 100644 --- a/samples/basic/fade_led/README.rst +++ b/samples/basic/fade_led/README.rst @@ -28,11 +28,11 @@ To build and flash this sample for the :ref:`nrf52840dk_nrf52840`: .. zephyr-app-commands:: :zephyr-app: samples/basic/fade_led - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: -Change ``nrf52840dk_nrf52840`` appropriately for other supported boards. +Change ``nrf52840dk/nrf52840`` appropriately for other supported boards. After flashing, the sample starts fading the LED as described above. It also prints information to the board's console. diff --git a/samples/basic/fade_led/sample.yaml b/samples/basic/fade_led/sample.yaml index f141f4abfc3..eae1afefe5b 100644 --- a/samples/basic/fade_led/sample.yaml +++ b/samples/basic/fade_led/sample.yaml @@ -9,4 +9,4 @@ tests: harness: led filter: dt_alias_exists("pwm-led0") and dt_compat_enabled("pwm-leds") integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 diff --git a/samples/basic/hash_map/sample.yaml b/samples/basic/hash_map/sample.yaml index 9e1ee6558ca..dad9af8a994 100644 --- a/samples/basic/hash_map/sample.yaml +++ b/samples/basic/hash_map/sample.yaml @@ -10,7 +10,7 @@ common: min_ram: 24 integration_platforms: - qemu_x86_64 - - mps2_an385 + - mps2/an385 harness: console harness_config: type: one_line diff --git a/samples/basic/minimal/sample.yaml b/samples/basic/minimal/sample.yaml index ed934859f37..54e0d718bdc 100644 --- a/samples/basic/minimal/sample.yaml +++ b/samples/basic/minimal/sample.yaml @@ -15,8 +15,8 @@ tests: platform_allow: - reel_board - frdm_k64f - - mps2_an385 - - nrf51dk_nrf51422 + - mps2/an385 + - nrf51dk/nrf51822 - nucleo_f429zi - disco_l475_iot1 integration_platforms: @@ -27,8 +27,8 @@ tests: platform_allow: - reel_board - frdm_k64f - - mps2_an385 - - nrf51dk_nrf51422 + - mps2/an385 + - nrf51dk/nrf51822 - nucleo_f429zi - disco_l475_iot1 sample.minimal.mt-no-preempt-no-timers.arm: @@ -37,8 +37,8 @@ tests: platform_allow: - reel_board - frdm_k64f - - mps2_an385 - - nrf51dk_nrf51422 + - mps2/an385 + - nrf51dk/nrf51822 - nucleo_f429zi - disco_l475_iot1 sample.minimal.no-mt.arm: @@ -47,8 +47,8 @@ tests: platform_allow: - reel_board - frdm_k64f - - mps2_an385 - - nrf51dk_nrf51422 + - mps2/an385 + - nrf51dk/nrf51822 - nucleo_f429zi - disco_l475_iot1 sample.minimal.no-mt-no-timers.arm: @@ -57,8 +57,8 @@ tests: platform_allow: - reel_board - frdm_k64f - - mps2_an385 - - nrf51dk_nrf51422 + - mps2/an385 + - nrf51dk/nrf51822 - nucleo_f429zi - disco_l475_iot1 sample.minimal.mt.x86: @@ -88,7 +88,7 @@ tests: tags: - kernel integration_platforms: - - qemu_arc_em + - qemu_arc/qemu_arc_em sample.minimal.riscv.runtime: extra_args: - CONF_FILE='common-runtime.conf;no-timers.conf;no-mt.conf;riscv.conf' diff --git a/samples/basic/rgb_led/README.rst b/samples/basic/rgb_led/README.rst index 11cc5d6e646..b3dca648d57 100644 --- a/samples/basic/rgb_led/README.rst +++ b/samples/basic/rgb_led/README.rst @@ -39,7 +39,7 @@ an unsupported board: Unsupported board: green-pwm-led devicetree alias is not defined Unsupported board: blue-pwm-led devicetree alias is not defined -See :zephyr_file:`boards/arm/hexiwear_k64/hexiwear_k64.dts` for an example +See :zephyr_file:`boards/nxp/hexiwear/hexiwear_mk64f12.dts` for an example :file:`BOARD.dts` file which supports this sample. Wiring @@ -53,12 +53,12 @@ Otherwise, LEDs should be connected to the appropriate PWM channels. Building and Running ******************** -For example, to build and flash this board for :ref:`hexiwear_k64`: +For example, to build and flash this board for :ref:`hexiwear`: .. zephyr-app-commands:: :zephyr-app: samples/basic/rgb_led - :board: hexiwear_k64 + :board: hexiwear/mk64f12 :goals: build flash :compact: -Change ``hexiwear_k64`` appropriately for other supported boards. +Change ``hexiwear/mk64f12`` appropriately for other supported boards. diff --git a/samples/basic/threads/README.rst b/samples/basic/threads/README.rst index 1ade8e9d360..f58c886fdd2 100644 --- a/samples/basic/threads/README.rst +++ b/samples/basic/threads/README.rst @@ -47,8 +47,8 @@ For example, to build this sample for :ref:`96b_carbon_board`: .. zephyr-app-commands:: :zephyr-app: samples/basic/threads - :board: 96b_carbon + :board: 96b_carbon/stm32f401xe :goals: build flash :compact: -Change ``96b_carbon`` appropriately for other supported boards. +Change ``96b_carbon/stm32f401xe`` appropriately for other supported boards. diff --git a/samples/basic/threads/sample.yaml b/samples/basic/threads/sample.yaml index d76669c9263..0d3acce55fd 100644 --- a/samples/basic/threads/sample.yaml +++ b/samples/basic/threads/sample.yaml @@ -10,7 +10,7 @@ tests: filter: dt_enabled_alias_with_parent_compat("led0", "gpio-leds") and dt_enabled_alias_with_parent_compat("led1", "gpio-leds") integration_platforms: - - nrf52833dk_nrf52820 + - nrf52833dk/nrf52820 depends_on: gpio harness: console harness_config: diff --git a/samples/bluetooth/beacon/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/beacon/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/beacon/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/beacon/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/beacon/sample.yaml b/samples/bluetooth/beacon/sample.yaml index 062c71f7259..9073de8c1fc 100644 --- a/samples/bluetooth/beacon/sample.yaml +++ b/samples/bluetooth/beacon/sample.yaml @@ -6,7 +6,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 @@ -14,5 +14,5 @@ tests: sample.bluetooth.beacon-coex: extra_args: CONF_FILE="prj-coex.conf" harness: bluetooth - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/bluetooth.rst b/samples/bluetooth/bluetooth.rst index 0b59b9626b4..35b49bfd0ab 100644 --- a/samples/bluetooth/bluetooth.rst +++ b/samples/bluetooth/bluetooth.rst @@ -17,8 +17,8 @@ documentation and are prefixed with :literal:`hci_` in their folder names. .. note:: If you want to run any bluetooth sample on the nRF5340 device (build using - ``-DBOARD=nrf5340dk_nrf5340_cpuapp`` or - ``-DBOARD=nrf5340dk_nrf5340_cpuapp_ns``) you must also build + ``-DBOARD=nrf5340dk/nrf5340/cpuapp`` or + ``-DBOARD=nrf5340dk/nrf5340/cpuapp/ns``) you must also build and program the corresponding sample for the nRF5340 network core :ref:`bluetooth-hci-ipc-sample` which implements the Bluetooth Low Energy controller. diff --git a/samples/bluetooth/broadcast_audio_assistant/README.rst b/samples/bluetooth/broadcast_audio_assistant/README.rst index faff37a6e22..e0a7ec5a012 100644 --- a/samples/bluetooth/broadcast_audio_assistant/README.rst +++ b/samples/bluetooth/broadcast_audio_assistant/README.rst @@ -52,5 +52,5 @@ Building for an nrf52840dk .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_assistant/ - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build diff --git a/samples/bluetooth/broadcast_audio_assistant/sample.yaml b/samples/bluetooth/broadcast_audio_assistant/sample.yaml index 8481ebeeeb4..cc36702ac4d 100644 --- a/samples/bluetooth/broadcast_audio_assistant/sample.yaml +++ b/samples/bluetooth/broadcast_audio_assistant/sample.yaml @@ -5,7 +5,7 @@ tests: sample.bluetooth.broadcast_audio_assistant: harness: bluetooth platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild b/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild index f434010f81d..d609fd0ec85 100644 --- a/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild +++ b/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/broadcast_audio_sink/README.rst b/samples/bluetooth/broadcast_audio_sink/README.rst index aca5d18bb94..3c2d8d39d17 100644 --- a/samples/bluetooth/broadcast_audio_sink/README.rst +++ b/samples/bluetooth/broadcast_audio_sink/README.rst @@ -41,7 +41,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_sink/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -49,7 +49,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_sink/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/broadcast_audio_sink/sample.yaml b/samples/bluetooth/broadcast_audio_sink/sample.yaml index e81b86de3e0..1df6e582baa 100644 --- a/samples/bluetooth/broadcast_audio_sink/sample.yaml +++ b/samples/bluetooth/broadcast_audio_sink/sample.yaml @@ -7,21 +7,21 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - nrf5340bsim_nrf5340_cpuapp integration_platforms: - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: bluetooth sysbuild: true sample.bluetooth.broadcast_audio_sink.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 integration_platforms: - nrf52_bsim - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52833 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild b/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild index f434010f81d..d609fd0ec85 100644 --- a/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild +++ b/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/broadcast_audio_source/README.rst b/samples/bluetooth/broadcast_audio_source/README.rst index 1c36236231b..515eb64177e 100644 --- a/samples/bluetooth/broadcast_audio_source/README.rst +++ b/samples/bluetooth/broadcast_audio_source/README.rst @@ -40,7 +40,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_source/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -48,7 +48,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_source/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/broadcast_audio_source/sample.yaml b/samples/bluetooth/broadcast_audio_source/sample.yaml index 3c554803409..4df6ed34f54 100644 --- a/samples/bluetooth/broadcast_audio_source/sample.yaml +++ b/samples/bluetooth/broadcast_audio_source/sample.yaml @@ -7,23 +7,23 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - nrf5340bsim_nrf5340_cpuapp integration_platforms: - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: bluetooth sysbuild: true sample.bluetooth.broadcast_audio_source.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 - - nrf52840dongle_nrf52840 + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 + - nrf52840dongle/nrf52840 integration_platforms: - nrf52_bsim - - nrf52833dk_nrf52833 - - nrf52840dongle_nrf52840 + - nrf52833dk/nrf52833 + - nrf52840dongle/nrf52840 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/broadcaster/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/broadcaster/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/broadcaster/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/broadcaster/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/broadcaster/sample.yaml b/samples/bluetooth/broadcaster/sample.yaml index d0ee925d9c7..7556e2aba7f 100644 --- a/samples/bluetooth/broadcaster/sample.yaml +++ b/samples/bluetooth/broadcaster/sample.yaml @@ -6,8 +6,8 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/broadcaster_multiple/sample.yaml b/samples/bluetooth/broadcaster_multiple/sample.yaml index a3b95d62946..96e274f5514 100644 --- a/samples/bluetooth/broadcaster_multiple/sample.yaml +++ b/samples/bluetooth/broadcaster_multiple/sample.yaml @@ -6,9 +6,9 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/central/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/central/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/central/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/central/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/central_hr/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/central_hr/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/central_hr/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/central_hr/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/central_ht/sample.yaml b/samples/bluetooth/central_ht/sample.yaml index b9838607cad..f41b2289705 100644 --- a/samples/bluetooth/central_ht/sample.yaml +++ b/samples/bluetooth/central_ht/sample.yaml @@ -6,8 +6,8 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/central_multilink/sample.yaml b/samples/bluetooth/central_multilink/sample.yaml index 112533a784f..bca1027d37f 100644 --- a/samples/bluetooth/central_multilink/sample.yaml +++ b/samples/bluetooth/central_multilink/sample.yaml @@ -6,7 +6,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_cortex_m3 tags: bluetooth diff --git a/samples/bluetooth/central_otc/sample.yaml b/samples/bluetooth/central_otc/sample.yaml index ac49056252f..4d7221bd653 100644 --- a/samples/bluetooth/central_otc/sample.yaml +++ b/samples/bluetooth/central_otc/sample.yaml @@ -4,9 +4,9 @@ tests: sample.bluetooth.central_otc: harness: bluetooth platform_allow: - - nrf21540dk_nrf52840 - - nrf52840dk_nrf52840 - - nrf52833dk_nrf52833 + - nrf21540dk/nrf52840 + - nrf52840dk/nrf52840 + - nrf52833dk/nrf52833 tags: bluetooth integration_platforms: - - nrf21540dk_nrf52840 + - nrf21540dk/nrf52840 diff --git a/samples/bluetooth/direction_finding_central/README.rst b/samples/bluetooth/direction_finding_central/README.rst index 07a5d1c52be..1a6d6519dcf 100644 --- a/samples/bluetooth/direction_finding_central/README.rst +++ b/samples/bluetooth/direction_finding_central/README.rst @@ -26,12 +26,12 @@ Building and Running By default the application supports Angle of Arrival and Angle of Departure mode. To use Angle of Departure mode only, build this application as follows, -changing ``nrf52833dk_nrf52833`` as needed for your board: +changing ``nrf52833dk/nrf52833`` as needed for your board: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/direction_finding_central :host-os: unix - :board: nrf52833dk_nrf52833 + :board: nrf52833dk/nrf52833 :gen-args: -DEXTRA_CONF_FILE=overlay-aod.conf :goals: build flash :compact: diff --git a/samples/bluetooth/direction_finding_central/sample.yaml b/samples/bluetooth/direction_finding_central/sample.yaml index e46c5b623a1..b0c94537b51 100644 --- a/samples/bluetooth/direction_finding_central/sample.yaml +++ b/samples/bluetooth/direction_finding_central/sample.yaml @@ -6,23 +6,23 @@ tests: sample.bluetooth.direction_finding.central: harness: bluetooth platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp sample.bluetooth.direction_finding.central.aod: harness: bluetooth extra_args: OVERLAY_CONFIG="overlay-aod.conf" platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/direction_finding_connectionless_rx/README.rst b/samples/bluetooth/direction_finding_connectionless_rx/README.rst index ad8416dd537..c9380c6e7e6 100644 --- a/samples/bluetooth/direction_finding_connectionless_rx/README.rst +++ b/samples/bluetooth/direction_finding_connectionless_rx/README.rst @@ -26,12 +26,12 @@ Building and Running By default the application supports Angle of Arrival and Angle of Departure mode. To use Angle of Departure mode only, build this application as follows, -changing ``nrf52833dk_nrf52833`` as needed for your board: +changing ``nrf52833dk/nrf52833`` as needed for your board: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/direction_finding_connectionless_rx :host-os: unix - :board: nrf52833dk_nrf52833 + :board: nrf52833dk/nrf52833 :gen-args: -DEXTRA_CONF_FILE=overlay-aod.conf :goals: build flash :compact: diff --git a/samples/bluetooth/direction_finding_connectionless_rx/sample.yaml b/samples/bluetooth/direction_finding_connectionless_rx/sample.yaml index 4aa2f2f76ea..1c79df41275 100644 --- a/samples/bluetooth/direction_finding_connectionless_rx/sample.yaml +++ b/samples/bluetooth/direction_finding_connectionless_rx/sample.yaml @@ -4,22 +4,22 @@ tests: sample.bluetooth.direction_finding_connectionless_rx: harness: bluetooth platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp sample.bluetooth.direction_finding_connectionless_rx.aod: harness: bluetooth extra_args: OVERLAY_CONFIG="overlay-aod.conf" platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/direction_finding_connectionless_tx/README.rst b/samples/bluetooth/direction_finding_connectionless_tx/README.rst index 6fe3dd68722..8ccd97d9251 100644 --- a/samples/bluetooth/direction_finding_connectionless_tx/README.rst +++ b/samples/bluetooth/direction_finding_connectionless_tx/README.rst @@ -26,12 +26,12 @@ By default the application supports Angle of Arrival (AoA) and Angle of Departure (AoD) mode. To use Angle of Arrival mode only, build this application as follows, changing -``nrf52833dk_nrf52833`` as needed for your board: +``nrf52833dk/nrf52833`` as needed for your board: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/direction_finding_connectionless_tx :host-os: unix - :board: nrf52833dk_nrf52833 + :board: nrf52833dk/nrf52833 :gen-args: -DEXTRA_CONF_FILE=overlay-aoa.conf :goals: build flash :compact: diff --git a/samples/bluetooth/direction_finding_connectionless_tx/sample.yaml b/samples/bluetooth/direction_finding_connectionless_tx/sample.yaml index 06b29cb3e31..1ea189f5088 100644 --- a/samples/bluetooth/direction_finding_connectionless_tx/sample.yaml +++ b/samples/bluetooth/direction_finding_connectionless_tx/sample.yaml @@ -4,22 +4,22 @@ tests: sample.bluetooth.direction_finding_connectionless: harness: bluetooth platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp sample.bluetooth.direction_finding_connectionless.aoa: harness: bluetooth extra_args: OVERLAY_CONFIG="overlay-aoa.conf" platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/direction_finding_peripheral/README.rst b/samples/bluetooth/direction_finding_peripheral/README.rst index 75cc5b9a917..68d709173d9 100644 --- a/samples/bluetooth/direction_finding_peripheral/README.rst +++ b/samples/bluetooth/direction_finding_peripheral/README.rst @@ -25,12 +25,12 @@ Building and Running By default the application supports Angle of Arrival and Angle of Departure mode. To use Angle of Arrival mode only, build this application as follows, -changing ``nrf52833dk_nrf52833`` as needed for your board: +changing ``nrf52833dk/nrf52833`` as needed for your board: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/direction_finding_peripheral :host-os: unix - :board: nrf52833dk_nrf52833 + :board: nrf52833dk/nrf52833 :gen-args: -DEXTRA_CONF_FILE=overlay-aoa.conf :goals: build flash :compact: diff --git a/samples/bluetooth/direction_finding_peripheral/sample.yaml b/samples/bluetooth/direction_finding_peripheral/sample.yaml index 71e00710ef5..126355a735f 100644 --- a/samples/bluetooth/direction_finding_peripheral/sample.yaml +++ b/samples/bluetooth/direction_finding_peripheral/sample.yaml @@ -6,23 +6,23 @@ tests: sample.bluetooth.direction_finding.peripheral: harness: bluetooth platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp sample.bluetooth.direction_finding.peripheral.aod: harness: bluetooth extra_args: OVERLAY_CONFIG="overlay-aoa.conf" platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/eddystone/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/eddystone/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/eddystone/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/eddystone/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/encrypted_advertising/central/sample.yaml b/samples/bluetooth/encrypted_advertising/central/sample.yaml index b26b5f8ac2a..d14ef45444b 100644 --- a/samples/bluetooth/encrypted_advertising/central/sample.yaml +++ b/samples/bluetooth/encrypted_advertising/central/sample.yaml @@ -3,5 +3,5 @@ sample: tests: sample.bluetooth.central_ead: harness: bluetooth - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/encrypted_advertising/peripheral/sample.yaml b/samples/bluetooth/encrypted_advertising/peripheral/sample.yaml index d948e618336..94ff3ee3a9d 100644 --- a/samples/bluetooth/encrypted_advertising/peripheral/sample.yaml +++ b/samples/bluetooth/encrypted_advertising/peripheral/sample.yaml @@ -3,5 +3,5 @@ sample: tests: sample.bluetooth.peripheral_ead: harness: bluetooth - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/extended_adv/advertiser/sample.yaml b/samples/bluetooth/extended_adv/advertiser/sample.yaml index 06b723062ce..b93a44f3180 100644 --- a/samples/bluetooth/extended_adv/advertiser/sample.yaml +++ b/samples/bluetooth/extended_adv/advertiser/sample.yaml @@ -3,5 +3,5 @@ sample: tests: sample.bluetooth.extended_advertising.advertiser: harness: bluetooth - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/extended_adv/scanner/sample.yaml b/samples/bluetooth/extended_adv/scanner/sample.yaml index 7cb06719dff..e9f72f20bcd 100644 --- a/samples/bluetooth/extended_adv/scanner/sample.yaml +++ b/samples/bluetooth/extended_adv/scanner/sample.yaml @@ -3,5 +3,5 @@ sample: tests: sample.bluetooth.extended_advertising.scanner: harness: bluetooth - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/hci_ipc/sample.yaml b/samples/bluetooth/hci_ipc/sample.yaml index e05a5d384d2..e0612025e6d 100644 --- a/samples/bluetooth/hci_ipc/sample.yaml +++ b/samples/bluetooth/hci_ipc/sample.yaml @@ -6,91 +6,91 @@ tests: harness: bluetooth tags: bluetooth platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso_broadcast.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso_receive.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.bis.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_bis-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso_central.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_iso_central-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso_peripheral.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_iso_peripheral-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.cis.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_cis-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_iso-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.df.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: - CONF_FILE="nrf5340_cpunet_df-bt_ll_sw_split.conf" - DTC_OVERLAY_FILE="nrf5340_cpunet_df-bt_ll_sw_split.overlay" - platform_allow: nrf5340dk_nrf5340_cpunet + platform_allow: nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.df.no_phy_coded.bt_ll_sw_split: harness: bluetooth tags: bluetooth @@ -98,13 +98,13 @@ tests: - CONF_FILE="nrf5340_cpunet_df-bt_ll_sw_split.conf" - DTC_OVERLAY_FILE="nrf5340_cpunet_df-bt_ll_sw_split.overlay" - CONFIG_BT_CTLR_PHY_CODED=n - platform_allow: nrf5340dk_nrf5340_cpunet + platform_allow: nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.mesh.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_bt_mesh-bt_ll_sw_split.conf" - platform_allow: nrf5340dk_nrf5340_cpunet + platform_allow: nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet diff --git a/samples/bluetooth/hci_pwr_ctrl/sample.yaml b/samples/bluetooth/hci_pwr_ctrl/sample.yaml index dc68b809a1b..67733b7edd0 100644 --- a/samples/bluetooth/hci_pwr_ctrl/sample.yaml +++ b/samples/bluetooth/hci_pwr_ctrl/sample.yaml @@ -5,8 +5,8 @@ tests: harness: bluetooth platform_allow: - bbc_microbit - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 - qemu_cortex_m3 - qemu_x86 tags: bluetooth diff --git a/samples/bluetooth/hci_spi/boards/nrf51dk_nrf51422.overlay b/samples/bluetooth/hci_spi/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/bluetooth/hci_spi/boards/nrf51dk_nrf51422.overlay rename to samples/bluetooth/hci_spi/boards/nrf51dk_nrf51822.overlay diff --git a/samples/bluetooth/hci_spi/sample.yaml b/samples/bluetooth/hci_spi/sample.yaml index 25e86d93001..37d66fdb80a 100644 --- a/samples/bluetooth/hci_spi/sample.yaml +++ b/samples/bluetooth/hci_spi/sample.yaml @@ -5,11 +5,11 @@ tests: sample.bluetooth.hci_spi: harness: bluetooth platform_allow: - - 96b_carbon_nrf51 - - nrf51dk_nrf51422 + - 96b_carbon/nrf51822 + - nrf51dk/nrf51822 integration_platforms: - - 96b_carbon_nrf51 - - nrf51dk_nrf51422 + - 96b_carbon/nrf51822 + - nrf51dk/nrf51822 tags: - bluetooth - spi diff --git a/samples/bluetooth/hci_uart/README.rst b/samples/bluetooth/hci_uart/README.rst index 0beb105035d..a7a82fc8d01 100644 --- a/samples/bluetooth/hci_uart/README.rst +++ b/samples/bluetooth/hci_uart/README.rst @@ -50,7 +50,7 @@ For example, to build for the nRF52832 Development Kit: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/hci_uart - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash .. _bluetooth-hci-uart-qemu-posix: @@ -135,12 +135,12 @@ required hardware configuration for the Radio. .. code-block:: console - west build samples/bluetooth/hci_uart -b nrf52833dk_nrf52833@df -- -DCONFIG_BT_CTLR_DF=y + west build samples/bluetooth/hci_uart -b nrf52833dk/nrf52833@df -- -DCONFIG_BT_CTLR_DF=y You can use following targets: -* ``nrf5340dk_nrf5340_cpunet@df`` -* ``nrf52833dk_nrf52833@df`` +* ``nrf5340dk/nrf5340/cpunet@df`` +* ``nrf52833dk/nrf52833@df`` Check the :ref:`bluetooth_direction_finding_connectionless_rx` and the :ref:`bluetooth_direction_finding_connectionless_tx` for more details. diff --git a/samples/bluetooth/hci_uart/boards/nrf51dk_nrf51422.conf b/samples/bluetooth/hci_uart/boards/nrf51dk_nrf51822.conf similarity index 100% rename from samples/bluetooth/hci_uart/boards/nrf51dk_nrf51422.conf rename to samples/bluetooth/hci_uart/boards/nrf51dk_nrf51822.conf diff --git a/samples/bluetooth/hci_uart/boards/nrf51dk_nrf51422.overlay b/samples/bluetooth/hci_uart/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/bluetooth/hci_uart/boards/nrf51dk_nrf51422.overlay rename to samples/bluetooth/hci_uart/boards/nrf51dk_nrf51822.overlay diff --git a/samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51422.conf b/samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51822.conf similarity index 100% rename from samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51422.conf rename to samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51822.conf diff --git a/samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51422.overlay b/samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51822.overlay similarity index 100% rename from samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51422.overlay rename to samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51822.overlay diff --git a/samples/bluetooth/hci_uart/boards/rv32m1_vega_ri5cy.conf b/samples/bluetooth/hci_uart/boards/rv32m1_vega_openisa_rv32m1_ri5cy.conf similarity index 100% rename from samples/bluetooth/hci_uart/boards/rv32m1_vega_ri5cy.conf rename to samples/bluetooth/hci_uart/boards/rv32m1_vega_openisa_rv32m1_ri5cy.conf diff --git a/samples/bluetooth/hci_uart/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/hci_uart/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/hci_uart/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/hci_uart/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/hci_uart/sample.yaml b/samples/bluetooth/hci_uart/sample.yaml index c24ae0f68f5..033a16c0cb1 100644 --- a/samples/bluetooth/hci_uart/sample.yaml +++ b/samples/bluetooth/hci_uart/sample.yaml @@ -5,13 +5,13 @@ tests: sample.bluetooth.hci_uart.nrf5: harness: bluetooth platform_allow: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: - uart - bluetooth sample.bluetooth.hci_uart.nrf52833.df: harness: bluetooth - platform_allow: nrf52833dk_nrf52833 + platform_allow: nrf52833dk/nrf52833 extra_args: DTC_OVERLAY_FILE=./boards/nrf52833dk_nrf52833_df.overlay extra_configs: - CONFIG_BT_CTLR_DF=y @@ -20,7 +20,7 @@ tests: - bluetooth sample.bluetooth.hci_uart.nrf5340_netcore.df: harness: bluetooth - platform_allow: nrf5340dk_nrf5340_cpunet + platform_allow: nrf5340dk/nrf5340/cpunet extra_args: DTC_OVERLAY_FILE=./boards/nrf5340dk_nrf5340_cpunet_df.overlay extra_configs: - CONFIG_BT_CTLR_DF=y @@ -29,7 +29,7 @@ tests: - bluetooth sample.bluetooth.hci_uart.nrf52833.df.iq_report: harness: bluetooth - platform_allow: nrf52833dk_nrf52833 + platform_allow: nrf52833dk/nrf52833 extra_args: DTC_OVERLAY_FILE=./boards/nrf52833dk_nrf52833_df.overlay extra_configs: - CONFIG_BT_CTLR_DF=y @@ -39,7 +39,7 @@ tests: - bluetooth sample.bluetooth.hci_uart.nrf5340_netcore.df.iq_report: harness: bluetooth - platform_allow: nrf5340dk_nrf5340_cpunet + platform_allow: nrf5340dk/nrf5340/cpunet extra_args: DTC_OVERLAY_FILE=./boards/nrf5340dk_nrf5340_cpunet_df.overlay extra_configs: - CONFIG_BT_CTLR_DF=y @@ -49,9 +49,9 @@ tests: - bluetooth sample.bluetooth.hci_uart.nrf52833.all: harness: bluetooth - platform_allow: nrf52833dk_nrf52833 + platform_allow: nrf52833dk/nrf52833 integration_platforms: - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52833 extra_args: - OVERLAY_CONFIG=overlay-all-bt_ll_sw_split.conf - DTC_OVERLAY_FILE=./boards/nrf52833dk_nrf52833_df.overlay diff --git a/samples/bluetooth/hci_uart_async/README.rst b/samples/bluetooth/hci_uart_async/README.rst index f5caf0f965d..7dbb4bbbdb6 100644 --- a/samples/bluetooth/hci_uart_async/README.rst +++ b/samples/bluetooth/hci_uart_async/README.rst @@ -47,7 +47,7 @@ For example, to build for the nRF52832 Development Kit: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/hci_uart_async - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash .. _bluetooth-hci-uart-async-qemu-posix: diff --git a/samples/bluetooth/hci_uart_async/sample.yaml b/samples/bluetooth/hci_uart_async/sample.yaml index d0db2b90385..7faad998c6f 100644 --- a/samples/bluetooth/hci_uart_async/sample.yaml +++ b/samples/bluetooth/hci_uart_async/sample.yaml @@ -13,7 +13,7 @@ tests: sample.bluetooth.hci_uart_async.nrf5: harness: bluetooth platform_allow: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: - uart - bluetooth diff --git a/samples/bluetooth/hci_usb/sample.yaml b/samples/bluetooth/hci_usb/sample.yaml index 9848aed2430..7e34cf68f53 100644 --- a/samples/bluetooth/hci_usb/sample.yaml +++ b/samples/bluetooth/hci_usb/sample.yaml @@ -20,4 +20,4 @@ tests: - usb - bluetooth extra_args: CONF_FILE="usbd_next_prj.conf" - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 diff --git a/samples/bluetooth/hci_usb_h4/sample.yaml b/samples/bluetooth/hci_usb_h4/sample.yaml index afc6e2429cb..b8b9d6d91b6 100644 --- a/samples/bluetooth/hci_usb_h4/sample.yaml +++ b/samples/bluetooth/hci_usb_h4/sample.yaml @@ -10,4 +10,4 @@ tests: - usb - bluetooth # FIXME: exclude due to build error - platform_exclude: 96b_carbon stm32l562e_dk + platform_exclude: 96b_carbon/stm32f401xe stm32l562e_dk diff --git a/samples/bluetooth/ibeacon/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/ibeacon/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/ibeacon/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/ibeacon/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/ipsp/README.rst b/samples/bluetooth/ipsp/README.rst index 36da6dae4d7..2ec160d2a22 100644 --- a/samples/bluetooth/ipsp/README.rst +++ b/samples/bluetooth/ipsp/README.rst @@ -18,7 +18,7 @@ Sample can be built and executed for the nRF52840 DK NRF52840 as follows: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/ipsp - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: @@ -27,7 +27,7 @@ To build a debug version, with logging and shell support, use the config file .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/ipsp - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :conf: prj_dbg.conf :goals: build flash :compact: @@ -43,7 +43,7 @@ Building and Running for Linux kernels released before 4.12 .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/ipsp - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :conf: "prj_zep1656.conf" :goals: build flash :compact: diff --git a/samples/bluetooth/ipsp/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/ipsp/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/ipsp/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/ipsp/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/iso_broadcast/sample.yaml b/samples/bluetooth/iso_broadcast/sample.yaml index 0961f5621c0..10fb481688c 100644 --- a/samples/bluetooth/iso_broadcast/sample.yaml +++ b/samples/bluetooth/iso_broadcast/sample.yaml @@ -7,7 +7,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 integration_platforms: - qemu_cortex_m3 tags: bluetooth @@ -17,8 +17,8 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/iso_broadcast_benchmark/sample.yaml b/samples/bluetooth/iso_broadcast_benchmark/sample.yaml index 0c22b5f597a..d9804ac7029 100644 --- a/samples/bluetooth/iso_broadcast_benchmark/sample.yaml +++ b/samples/bluetooth/iso_broadcast_benchmark/sample.yaml @@ -5,9 +5,9 @@ tests: sample.bluetooth.iso_broadcast_benchmark: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340_audio_dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340_audio_dk/nrf5340/cpuapp integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/iso_connected_benchmark/sample.yaml b/samples/bluetooth/iso_connected_benchmark/sample.yaml index 7c7ca228c99..fd4eb7d9615 100644 --- a/samples/bluetooth/iso_connected_benchmark/sample.yaml +++ b/samples/bluetooth/iso_connected_benchmark/sample.yaml @@ -5,6 +5,6 @@ tests: sample.bluetooth.iso_connected_benchmark: build_only: true platform_allow: - - nrf5340dk_nrf5340_cpuapp - - nrf5340_audio_dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp + - nrf5340_audio_dk/nrf5340/cpuapp tags: bluetooth diff --git a/samples/bluetooth/iso_receive/sample.yaml b/samples/bluetooth/iso_receive/sample.yaml index 7d4fbabf5e9..2a065b7baa2 100644 --- a/samples/bluetooth/iso_receive/sample.yaml +++ b/samples/bluetooth/iso_receive/sample.yaml @@ -7,7 +7,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 integration_platforms: - qemu_cortex_m3 tags: bluetooth @@ -17,8 +17,8 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/mesh/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/mesh/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/mesh/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/mesh/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/mesh/sample.yaml b/samples/bluetooth/mesh/sample.yaml index cbb474cd92f..7ad548623f7 100644 --- a/samples/bluetooth/mesh/sample.yaml +++ b/samples/bluetooth/mesh/sample.yaml @@ -6,8 +6,8 @@ tests: platform_allow: - bbc_microbit - qemu_x86 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp_ns + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp/ns integration_platforms: - qemu_x86 tags: bluetooth diff --git a/samples/bluetooth/mesh_demo/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/mesh_demo/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/mesh_demo/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/mesh_demo/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/mesh_demo/sample.yaml b/samples/bluetooth/mesh_demo/sample.yaml index adcb1af05cb..255793f5657 100644 --- a/samples/bluetooth/mesh_demo/sample.yaml +++ b/samples/bluetooth/mesh_demo/sample.yaml @@ -6,8 +6,8 @@ tests: platform_allow: - bbc_microbit - qemu_x86 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp_ns + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp/ns integration_platforms: - qemu_x86 - bbc_microbit diff --git a/samples/bluetooth/mesh_provisioner/sample.yaml b/samples/bluetooth/mesh_provisioner/sample.yaml index abaaf79aae3..4e122b08a6c 100644 --- a/samples/bluetooth/mesh_provisioner/sample.yaml +++ b/samples/bluetooth/mesh_provisioner/sample.yaml @@ -5,8 +5,8 @@ tests: harness: bluetooth platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp_ns + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp/ns integration_platforms: - qemu_x86 tags: bluetooth diff --git a/samples/bluetooth/observer/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/observer/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/observer/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/observer/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/observer/sample.yaml b/samples/bluetooth/observer/sample.yaml index b6ef4d4bb34..b60ccc9fe8e 100644 --- a/samples/bluetooth/observer/sample.yaml +++ b/samples/bluetooth/observer/sample.yaml @@ -6,7 +6,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_cortex_m3 tags: bluetooth @@ -16,7 +16,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/periodic_adv/sample.yaml b/samples/bluetooth/periodic_adv/sample.yaml index b37f7ccd13f..f9018ff09ef 100644 --- a/samples/bluetooth/periodic_adv/sample.yaml +++ b/samples/bluetooth/periodic_adv/sample.yaml @@ -7,7 +7,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/periodic_adv_conn/sample.yaml b/samples/bluetooth/periodic_adv_conn/sample.yaml index 985c1665b26..cfc9d0522f4 100644 --- a/samples/bluetooth/periodic_adv_conn/sample.yaml +++ b/samples/bluetooth/periodic_adv_conn/sample.yaml @@ -6,10 +6,10 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_BT_CTLR=n - CONFIG_BT_NO_DRIVER=y diff --git a/samples/bluetooth/periodic_adv_rsp/sample.yaml b/samples/bluetooth/periodic_adv_rsp/sample.yaml index f249ca55257..dcb37b9fe4a 100644 --- a/samples/bluetooth/periodic_adv_rsp/sample.yaml +++ b/samples/bluetooth/periodic_adv_rsp/sample.yaml @@ -6,10 +6,10 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_BT_CTLR=n - CONFIG_BT_NO_DRIVER=y diff --git a/samples/bluetooth/periodic_sync/sample.yaml b/samples/bluetooth/periodic_sync/sample.yaml index 3417c2096f4..5e54024ff7b 100644 --- a/samples/bluetooth/periodic_sync/sample.yaml +++ b/samples/bluetooth/periodic_sync/sample.yaml @@ -7,7 +7,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/periodic_sync_conn/sample.yaml b/samples/bluetooth/periodic_sync_conn/sample.yaml index bb6f83acd59..e7aca788eea 100644 --- a/samples/bluetooth/periodic_sync_conn/sample.yaml +++ b/samples/bluetooth/periodic_sync_conn/sample.yaml @@ -6,10 +6,10 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_BT_CTLR=n - CONFIG_BT_NO_DRIVER=y diff --git a/samples/bluetooth/periodic_sync_rsp/sample.yaml b/samples/bluetooth/periodic_sync_rsp/sample.yaml index 68c84563ce4..c0f073b19e0 100644 --- a/samples/bluetooth/periodic_sync_rsp/sample.yaml +++ b/samples/bluetooth/periodic_sync_rsp/sample.yaml @@ -6,10 +6,10 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_BT_CTLR=n - CONFIG_BT_NO_DRIVER=y diff --git a/samples/bluetooth/peripheral/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_csc/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_csc/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_csc/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_csc/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_dis/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_dis/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_dis/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_dis/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_esp/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_esp/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_esp/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_esp/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_hids/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_hids/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_hids/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_hids/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_hr/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_hr/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_hr/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_hr/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_hr/sample.yaml b/samples/bluetooth/peripheral_hr/sample.yaml index be557da8611..71a19327c60 100644 --- a/samples/bluetooth/peripheral_hr/sample.yaml +++ b/samples/bluetooth/peripheral_hr/sample.yaml @@ -10,8 +10,8 @@ tests: integration_platforms: - qemu_cortex_m3 tags: bluetooth - sample.bluetooth.peripheral_hr_rv32m1_vega_ri5cy: - platform_allow: rv32m1_vega_ri5cy + sample.bluetooth.peripheral_hr_rv32m1_vega_openisa_rv32m1_ri5cy: + platform_allow: rv32m1_vega/openisa_rv32m1/ri5cy tags: bluetooth build_only: true sample.bluetooth.peripheral_hr.frdm_kw41z_shield: diff --git a/samples/bluetooth/peripheral_ht/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_ht/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_ht/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_ht/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_ht/sample.yaml b/samples/bluetooth/peripheral_ht/sample.yaml index c539113907b..4ff509843e0 100644 --- a/samples/bluetooth/peripheral_ht/sample.yaml +++ b/samples/bluetooth/peripheral_ht/sample.yaml @@ -7,8 +7,8 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/peripheral_identity/sample.yaml b/samples/bluetooth/peripheral_identity/sample.yaml index 58fbc0e26f0..8bb4b277e6b 100644 --- a/samples/bluetooth/peripheral_identity/sample.yaml +++ b/samples/bluetooth/peripheral_identity/sample.yaml @@ -8,7 +8,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/peripheral_sc_only/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_sc_only/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_sc_only/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_sc_only/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild b/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild index f434010f81d..d609fd0ec85 100644 --- a/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild +++ b/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/public_broadcast_sink/README.rst b/samples/bluetooth/public_broadcast_sink/README.rst index 5f47bcd05ab..2ec0e41e7e5 100644 --- a/samples/bluetooth/public_broadcast_sink/README.rst +++ b/samples/bluetooth/public_broadcast_sink/README.rst @@ -38,7 +38,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/public_broadcast_sink/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -46,7 +46,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/public_broadcast_sink/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/public_broadcast_sink/sample.yaml b/samples/bluetooth/public_broadcast_sink/sample.yaml index 8b81f4cc364..3f2302aa4b1 100644 --- a/samples/bluetooth/public_broadcast_sink/sample.yaml +++ b/samples/bluetooth/public_broadcast_sink/sample.yaml @@ -7,21 +7,21 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - nrf5340bsim_nrf5340_cpuapp integration_platforms: - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: bluetooth sysbuild: true sample.bluetooth.public_broadcast_sink.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 integration_platforms: - nrf52_bsim - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52833 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild b/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild index f434010f81d..d609fd0ec85 100644 --- a/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild +++ b/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/public_broadcast_source/README.rst b/samples/bluetooth/public_broadcast_source/README.rst index 9111cd3f614..d0d1cf44afa 100644 --- a/samples/bluetooth/public_broadcast_source/README.rst +++ b/samples/bluetooth/public_broadcast_source/README.rst @@ -38,7 +38,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/public_broadcast_source/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -46,7 +46,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/public_broadcast_source/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/public_broadcast_source/sample.yaml b/samples/bluetooth/public_broadcast_source/sample.yaml index eb2bd5dc79b..f4f1fc435f7 100644 --- a/samples/bluetooth/public_broadcast_source/sample.yaml +++ b/samples/bluetooth/public_broadcast_source/sample.yaml @@ -7,21 +7,21 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - nrf5340bsim_nrf5340_cpuapp integration_platforms: - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: bluetooth sysbuild: true sample.bluetooth.public_broadcast_source.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 integration_platforms: - nrf52_bsim - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52833 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/scan_adv/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/scan_adv/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/scan_adv/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/scan_adv/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild b/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild index f434010f81d..d609fd0ec85 100644 --- a/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild +++ b/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/unicast_audio_client/README.rst b/samples/bluetooth/unicast_audio_client/README.rst index 3735aff4ebd..19e7cdf8679 100644 --- a/samples/bluetooth/unicast_audio_client/README.rst +++ b/samples/bluetooth/unicast_audio_client/README.rst @@ -32,7 +32,7 @@ Building for an nrf52840dk .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_client/ - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :gen-args: -DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf @@ -44,7 +44,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_client/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -52,7 +52,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_server/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/unicast_audio_client/sample.yaml b/samples/bluetooth/unicast_audio_client/sample.yaml index 76ff71f350b..1b488d9eb94 100644 --- a/samples/bluetooth/unicast_audio_client/sample.yaml +++ b/samples/bluetooth/unicast_audio_client/sample.yaml @@ -8,19 +8,19 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf5340bsim_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - native_sim tags: bluetooth integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp sysbuild: true sample.bluetooth.audio_unicast_client.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild b/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild index f434010f81d..d609fd0ec85 100644 --- a/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild +++ b/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/unicast_audio_server/README.rst b/samples/bluetooth/unicast_audio_server/README.rst index 79a06244839..9caeac854a7 100644 --- a/samples/bluetooth/unicast_audio_server/README.rst +++ b/samples/bluetooth/unicast_audio_server/README.rst @@ -32,7 +32,7 @@ Building for an nrf52840dk .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_server/ - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :gen-args: -DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf @@ -44,7 +44,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_server/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -52,7 +52,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_server/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/unicast_audio_server/sample.yaml b/samples/bluetooth/unicast_audio_server/sample.yaml index 0c7496e288b..0ff20f735d7 100644 --- a/samples/bluetooth/unicast_audio_server/sample.yaml +++ b/samples/bluetooth/unicast_audio_server/sample.yaml @@ -8,19 +8,19 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf5340bsim_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - native_sim tags: bluetooth integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp sysbuild: true sample.bluetooth.audio_unicast_server.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/boards/arc_secure_services/em_starterkit_em7d_normal_defconfig b/samples/boards/arc_secure_services/em_starterkit_em7d_normal_defconfig index 059ce331b60..cfa607745c6 100644 --- a/samples/boards/arc_secure_services/em_starterkit_em7d_normal_defconfig +++ b/samples/boards/arc_secure_services/em_starterkit_em7d_normal_defconfig @@ -1,7 +1,6 @@ CONFIG_SOC_EMSK=y CONFIG_SOC_EMSK_EM7D=y CONFIG_BOARD_EM_STARTERKIT=y -CONFIG_BOARD_EM_STARTERKIT_R23=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n CONFIG_BUILD_NO_GAP_FILL=y diff --git a/samples/boards/arc_secure_services/sample.yaml b/samples/boards/arc_secure_services/sample.yaml index 8e99393eb77..8b6be234339 100644 --- a/samples/boards/arc_secure_services/sample.yaml +++ b/samples/boards/arc_secure_services/sample.yaml @@ -7,10 +7,10 @@ tests: # Requires multiple kernels in an AMP config. See README.rst build_only: true platform_allow: - - nsim_sem - - em_starterkit_em7d + - nsim/nsim_sem + - em_starterkit/emsk_em7d integration_platforms: - - nsim_sem + - nsim/nsim_sem tags: secure harness: console harness_config: diff --git a/samples/boards/esp32/deep_sleep/README.rst b/samples/boards/esp32/deep_sleep/README.rst index a5de4def742..ac73969915b 100644 --- a/samples/boards/esp32/deep_sleep/README.rst +++ b/samples/boards/esp32/deep_sleep/README.rst @@ -51,7 +51,7 @@ Building, Flashing and Running .. zephyr-app-commands:: :zephyr-app: samples/boards/esp32/deep_sleep - :board: esp32_devkitc_wroom + :board: esp32_devkitc_wroom/esp32/procpu :goals: build flash :compact: diff --git a/samples/boards/esp32/ethernet/sample.yaml b/samples/boards/esp32/ethernet/sample.yaml index 2280fec7c7c..35f9b4a44af 100644 --- a/samples/boards/esp32/ethernet/sample.yaml +++ b/samples/boards/esp32/ethernet/sample.yaml @@ -3,5 +3,5 @@ sample: name: ESP32 Ethernet tests: sample.board.esp32.ethernet: - platform_allow: esp32_ethernet_kit + platform_allow: esp32_ethernet_kit/esp32/procpu tags: esp32 diff --git a/samples/boards/esp32/flash_encryption/sample.yaml b/samples/boards/esp32/flash_encryption/sample.yaml index 84749b99108..26e7f309f09 100644 --- a/samples/boards/esp32/flash_encryption/sample.yaml +++ b/samples/boards/esp32/flash_encryption/sample.yaml @@ -4,7 +4,7 @@ sample: tests: sample.board.esp32: platform_allow: - - esp32_devkitc_wroom - - esp32_devkitc_wrover - - yd_esp32 + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu + - yd_esp32/esp32/procpu tags: esp32 diff --git a/samples/boards/esp32/flash_memory_mapped/sample.yaml b/samples/boards/esp32/flash_memory_mapped/sample.yaml index c8601961d94..83ccc9f4101 100644 --- a/samples/boards/esp32/flash_memory_mapped/sample.yaml +++ b/samples/boards/esp32/flash_memory_mapped/sample.yaml @@ -4,7 +4,7 @@ sample: tests: sample.board.esp32.flash_memory_mapped: platform_allow: - - esp32_devkitc_wroom + - esp32_devkitc_wroom/esp32/procpu - esp32c3_devkitm - - esp32s3_devkitm + - esp32s3_devkitm/esp32s3/procpu tags: esp32 diff --git a/samples/boards/esp32/light_sleep/README.rst b/samples/boards/esp32/light_sleep/README.rst index 581e9a352b9..72f58c2b418 100644 --- a/samples/boards/esp32/light_sleep/README.rst +++ b/samples/boards/esp32/light_sleep/README.rst @@ -31,7 +31,7 @@ Building, Flashing and Running .. zephyr-app-commands:: :zephyr-app: samples/boards/esp32/light_sleep - :board: esp32_devkitc_wroom + :board: esp32_devkitc_wroom/esp32/procpu :goals: build flash :compact: diff --git a/samples/boards/esp32/spiram_test/sample.yaml b/samples/boards/esp32/spiram_test/sample.yaml index d8cbfaa62d7..20c01a3028a 100644 --- a/samples/boards/esp32/spiram_test/sample.yaml +++ b/samples/boards/esp32/spiram_test/sample.yaml @@ -3,5 +3,5 @@ sample: name: spiram_test tests: sample.board.esp32.spiram: - platform_allow: esp32_devkitc_wrover + platform_allow: esp32_devkitc_wrover/esp32/procpu tags: esp32 diff --git a/samples/boards/intel_adsp/code_relocation/README.rst b/samples/boards/intel_adsp/code_relocation/README.rst index 3ab0025f3c5..84797018e7c 100644 --- a/samples/boards/intel_adsp/code_relocation/README.rst +++ b/samples/boards/intel_adsp/code_relocation/README.rst @@ -20,7 +20,7 @@ This application can be built and executed as follows: .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: intel_adsp_cavs25 + :board: intel_adsp/cavs25 :goals: build :compact: diff --git a/samples/boards/intel_adsp/code_relocation/sample.yaml b/samples/boards/intel_adsp/code_relocation/sample.yaml index 5fab5d98767..6c0dfd6c756 100644 --- a/samples/boards/intel_adsp/code_relocation/sample.yaml +++ b/samples/boards/intel_adsp/code_relocation/sample.yaml @@ -3,5 +3,5 @@ sample: name: cavs_code_reloc tests: sample.intel_adsp.code_relocation: - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 tags: linker diff --git a/samples/boards/mimxrt1170_evk_cm7/magic_addr/sample.yaml b/samples/boards/mimxrt1170_evk_cm7/magic_addr/sample.yaml index 10e876847f7..462a1d165e5 100644 --- a/samples/boards/mimxrt1170_evk_cm7/magic_addr/sample.yaml +++ b/samples/boards/mimxrt1170_evk_cm7/magic_addr/sample.yaml @@ -3,10 +3,10 @@ sample: name: magic addr common: integration_platforms: - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 tests: sample.boards.mimxrt1170_evk.magic_addr: platform_allow: - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 diff --git a/samples/boards/mimxrt1170_evk_cm7/magic_addr/src/main.c b/samples/boards/mimxrt1170_evk_cm7/magic_addr/src/main.c index 6856ca8f10f..f44c3f23923 100644 --- a/samples/boards/mimxrt1170_evk_cm7/magic_addr/src/main.c +++ b/samples/boards/mimxrt1170_evk_cm7/magic_addr/src/main.c @@ -27,7 +27,6 @@ void flexram_magic_addr_isr_cb(enum memc_flexram_interrupt_cause cause, } } - int main(void) { memc_flexram_register_callback(flexram_magic_addr_isr_cb, NULL); diff --git a/samples/boards/mimxrt595_evk/system_off/CMakeLists.txt b/samples/boards/mimxrt595_evk/system_off/CMakeLists.txt new file mode 100644 index 00000000000..97d8abdea0e --- /dev/null +++ b/samples/boards/mimxrt595_evk/system_off/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright 2022, NXP +# +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(mimxrt595_evk_system_off) + +target_sources(app PRIVATE src/main.c) diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/Kconfig b/samples/boards/mimxrt595_evk/system_off/Kconfig similarity index 100% rename from samples/boards/mimxrt595_evk_cm33/system_off/Kconfig rename to samples/boards/mimxrt595_evk/system_off/Kconfig diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/README.rst b/samples/boards/mimxrt595_evk/system_off/README.rst similarity index 98% rename from samples/boards/mimxrt595_evk_cm33/system_off/README.rst rename to samples/boards/mimxrt595_evk/system_off/README.rst index 00d0aeaf910..edec7a0b104 100644 --- a/samples/boards/mimxrt595_evk_cm33/system_off/README.rst +++ b/samples/boards/mimxrt595_evk/system_off/README.rst @@ -22,8 +22,8 @@ Building, Flashing and Running ****************************** .. zephyr-app-commands:: - :zephyr-app: samples/boards/mimxrt595_evk_cm33/system_off - :board: mimxrt595_evk_cm33 + :zephyr-app: samples/boards/mimxrt595_evk/system_off + :board: mimxrt595_evk/mimxrt595s/cm33 :goals: build flash :compact: diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/app.overlay b/samples/boards/mimxrt595_evk/system_off/app.overlay similarity index 100% rename from samples/boards/mimxrt595_evk_cm33/system_off/app.overlay rename to samples/boards/mimxrt595_evk/system_off/app.overlay diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/prj.conf b/samples/boards/mimxrt595_evk/system_off/prj.conf similarity index 100% rename from samples/boards/mimxrt595_evk_cm33/system_off/prj.conf rename to samples/boards/mimxrt595_evk/system_off/prj.conf diff --git a/samples/boards/mimxrt595_evk/system_off/sample.yaml b/samples/boards/mimxrt595_evk/system_off/sample.yaml new file mode 100644 index 00000000000..5d85a280a3e --- /dev/null +++ b/samples/boards/mimxrt595_evk/system_off/sample.yaml @@ -0,0 +1,13 @@ +# +# Copyright 2022, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +sample: + name: Deep Power Down State Sample for mimxrt595_evk +common: + tags: power +tests: + sample.boards.mimxrt595_evk.system_off: + build_only: true + platform_allow: mimxrt595_evk/mimxrt595s/cm33 diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/src/main.c b/samples/boards/mimxrt595_evk/system_off/src/main.c similarity index 100% rename from samples/boards/mimxrt595_evk_cm33/system_off/src/main.c rename to samples/boards/mimxrt595_evk/system_off/src/main.c diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/CMakeLists.txt b/samples/boards/mimxrt595_evk_cm33/system_off/CMakeLists.txt deleted file mode 100644 index 44e9ad4d6cd..00000000000 --- a/samples/boards/mimxrt595_evk_cm33/system_off/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(mimxrt595_evk_cm33_system_off) - -target_sources(app PRIVATE src/main.c) diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/sample.yaml b/samples/boards/mimxrt595_evk_cm33/system_off/sample.yaml deleted file mode 100644 index 58c906414b3..00000000000 --- a/samples/boards/mimxrt595_evk_cm33/system_off/sample.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# -sample: - name: Deep Power Down State Sample for mimxrt595_evk -common: - tags: power -tests: - sample.boards.mimxrt595_evk_cm33.system_off: - build_only: true - platform_allow: mimxrt595_evk_cm33 diff --git a/samples/boards/nrf/battery/README.rst b/samples/boards/nrf/battery/README.rst index 7f73ecabecf..323e5609640 100644 --- a/samples/boards/nrf/battery/README.rst +++ b/samples/boards/nrf/battery/README.rst @@ -73,7 +73,7 @@ The code can be found in :zephyr_file:`samples/boards/nrf/battery`. .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/battery - :board: thingy52_nrf52832 + :board: thingy52/nrf52832 :goals: build flash :compact: diff --git a/samples/boards/nrf/battery/sample.yaml b/samples/boards/nrf/battery/sample.yaml index e662296b0df..61e696f6c13 100644 --- a/samples/boards/nrf/battery/sample.yaml +++ b/samples/boards/nrf/battery/sample.yaml @@ -5,7 +5,7 @@ tests: build_only: true platform_allow: - particle_xenon - - thingy52_nrf52832 + - thingy52/nrf52832 tags: battery integration_platforms: - particle_xenon diff --git a/samples/boards/nrf/clock_skew/README.rst b/samples/boards/nrf/clock_skew/README.rst index 7891ab075b6..a6861d47056 100644 --- a/samples/boards/nrf/clock_skew/README.rst +++ b/samples/boards/nrf/clock_skew/README.rst @@ -28,7 +28,7 @@ Building, Flashing and Running .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/clock_skew - :board: nrf52dk_nrf52840 + :board: nrf52dk/nrf52832 :goals: build flash :compact: diff --git a/samples/boards/nrf/clock_skew/sample.yaml b/samples/boards/nrf/clock_skew/sample.yaml index 2b1eae0a6aa..3da8823ea51 100644 --- a/samples/boards/nrf/clock_skew/sample.yaml +++ b/samples/boards/nrf/clock_skew/sample.yaml @@ -4,9 +4,9 @@ tests: sample.boards.nrf.clock_skew: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 tags: power integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/samples/boards/nrf/dynamic_pinctrl/README.rst b/samples/boards/nrf/dynamic_pinctrl/README.rst index f44a58c3563..b98c4482353 100644 --- a/samples/boards/nrf/dynamic_pinctrl/README.rst +++ b/samples/boards/nrf/dynamic_pinctrl/README.rst @@ -53,7 +53,7 @@ You can build this application for the nRF52840 DK as follows: .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/dynamic_pinctrl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/boards/nrf/dynamic_pinctrl/sample.yaml b/samples/boards/nrf/dynamic_pinctrl/sample.yaml index b8f38be6ae3..03ccf19ec7e 100644 --- a/samples/boards/nrf/dynamic_pinctrl/sample.yaml +++ b/samples/boards/nrf/dynamic_pinctrl/sample.yaml @@ -4,6 +4,6 @@ sample: tests: sample.boards.nrf.dynamic_pinctrl: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml b/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml index d99dcceaa32..f1a7fae2a9a 100644 --- a/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml +++ b/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml @@ -6,5 +6,5 @@ tests: sample.boards.nrf.802154_rpmsg: build_only: true platform_allow: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet diff --git a/samples/boards/nrf/mesh/onoff-app/README.rst b/samples/boards/nrf/mesh/onoff-app/README.rst index 35e37d6a599..70d3e3bb1eb 100644 --- a/samples/boards/nrf/mesh/onoff-app/README.rst +++ b/samples/boards/nrf/mesh/onoff-app/README.rst @@ -38,7 +38,7 @@ Requirements ************ This sample has been tested on the Nordic nRF52840-PDK board, but would -likely also run on the nrf52dk_nrf52832 board. +likely also run on the nrf52dk/nrf52832 board. Building and Running ******************** @@ -50,7 +50,7 @@ The following commands build the application. .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/mesh/onoff-app - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/boards/nrf/mesh/onoff-app/sample.yaml b/samples/boards/nrf/mesh/onoff-app/sample.yaml index af80fff7fb6..bdc6f023a5b 100644 --- a/samples/boards/nrf/mesh/onoff-app/sample.yaml +++ b/samples/boards/nrf/mesh/onoff-app/sample.yaml @@ -2,6 +2,6 @@ sample: name: Bluetooth Mesh tests: sample.bluetooth.mesh.onoff: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth harness: bluetooth diff --git a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/README.rst b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/README.rst index f33bf1e7761..911e4b41430 100644 --- a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/README.rst +++ b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/README.rst @@ -55,7 +55,7 @@ also publish its relevant status. Requirements ************ This sample has been tested on the Nordic nRF52840-PDK board, but would -likely also run on the nrf52dk_nrf52832 board. +likely also run on the nrf52dk/nrf52832 board. Building and Running ******************** @@ -66,7 +66,7 @@ The following commands build the application. .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/mesh/onoff_level_lighting_vnd_app - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/sample.yaml b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/sample.yaml index ba0c0c0c1d3..d10821ca92e 100644 --- a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/sample.yaml +++ b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/sample.yaml @@ -2,6 +2,6 @@ sample: name: Bluetooth Mesh tests: sample.bluetooth.mesh.onoff_level_lighting_vnd: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth harness: bluetooth diff --git a/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt b/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt index 432f5497009..a09354a9e05 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt +++ b/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt @@ -7,7 +7,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp") OR +if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpuapp")) message(INFO " ${BOARD} used for Application Core") else() diff --git a/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild b/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild index b6dc3d0a6d0..e6d2ccd9930 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild +++ b/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild @@ -6,5 +6,5 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" diff --git a/samples/boards/nrf/nrf53_sync_rtc/README.rst b/samples/boards/nrf/nrf53_sync_rtc/README.rst index 0b2fd2a22fa..7d2a2945ffc 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/README.rst +++ b/samples/boards/nrf/nrf53_sync_rtc/README.rst @@ -22,12 +22,12 @@ interrupt handling. For simplicity and low latency sample is not using more sophisticated IPM protocols. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/nrf53_sync_rtc - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: flash :flash-args: --hex-file build/nrf53_sync_rtc/zephyr/zephyr.hex :west-args: --sysbuild diff --git a/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt b/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt index feced555bc7..341d961d8f0 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt +++ b/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt @@ -7,7 +7,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpunet") OR +if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpunet")) message(INFO " ${BOARD} used for Network Core") else() diff --git a/samples/boards/nrf/nrf53_sync_rtc/sample.yaml b/samples/boards/nrf/nrf53_sync_rtc/sample.yaml index d1905e0cc47..95e0471073f 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/sample.yaml +++ b/samples/boards/nrf/nrf53_sync_rtc/sample.yaml @@ -7,9 +7,9 @@ common: tests: sample.boards.nrf.nrf53_sync_rtc.real_hw: platform_allow: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp harness: remote sample.boards.nrf.nrf53_sync_rtc.simu: platform_allow: diff --git a/samples/boards/nrf/nrfx/README.rst b/samples/boards/nrf/nrfx/README.rst index e993ebe935b..d03e155e105 100644 --- a/samples/boards/nrf/nrfx/README.rst +++ b/samples/boards/nrf/nrfx/README.rst @@ -29,7 +29,7 @@ Requirements ************ This sample has been tested on the NordicSemiconductor nRF9160 DK -(nrf9160dk_nrf9160) and nRF52840 DK (nrf52840dk_nrf52840) boards. +(nrf9160dk/nrf9160) and nRF52840 DK (nrf52840dk/nrf52840) boards. Building and Running ******************** @@ -40,7 +40,7 @@ To build and flash the application: .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/nrfx - :board: nrf9160dk_nrf9160 + :board: nrf9160dk/nrf9160 :goals: build flash :compact: diff --git a/samples/boards/nrf/nrfx/sample.yaml b/samples/boards/nrf/nrfx/sample.yaml index f20fe8203e1..5483d1d9be0 100644 --- a/samples/boards/nrf/nrfx/sample.yaml +++ b/samples/boards/nrf/nrfx/sample.yaml @@ -3,10 +3,10 @@ sample: tests: sample.boards.nrf.nrfx: platform_allow: - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: board harness: console harness_config: diff --git a/samples/boards/nrf/nrfx_prs/README.rst b/samples/boards/nrf/nrfx_prs/README.rst index 0924eecd85f..8151a7cf5c5 100644 --- a/samples/boards/nrf/nrfx_prs/README.rst +++ b/samples/boards/nrf/nrfx_prs/README.rst @@ -38,7 +38,7 @@ Requirements ************ This sample has been tested on the Nordic Semiconductor nRF9160 DK -(nrf9160dk_nrf9160) and nRF5340 DK (nrf5340dk_nrf5340_cpuapp) boards. +(nrf9160dk/nrf9160) and nRF5340 DK (nrf5340dk/nrf5340/cpuapp) boards. Building and Running ******************** @@ -49,7 +49,7 @@ To build and flash the application: .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/nrfx_prs - :board: nrf9160dk_nrf9160 + :board: nrf9160dk/nrf9160 :goals: build flash :compact: diff --git a/samples/boards/nrf/nrfx_prs/boards/nrf9160dk_nrf9160.overlay b/samples/boards/nrf/nrfx_prs/boards/nrf9160dk_nrf9160.overlay index ee851e77b24..535d8272d45 100644 --- a/samples/boards/nrf/nrfx_prs/boards/nrf9160dk_nrf9160.overlay +++ b/samples/boards/nrf/nrfx_prs/boards/nrf9160dk_nrf9160.overlay @@ -79,7 +79,7 @@ pinctrl-names = "default"; }; -/* This node also needs to be disabled, as in the default nrf9160dk_nrf9160 +/* This node also needs to be disabled, as in the default nrf9160dk/nrf9160 * board configuration it uses the same pin numbers that are above assigned * to the spi1 node (17, 18, and 19). */ diff --git a/samples/boards/nrf/nrfx_prs/sample.yaml b/samples/boards/nrf/nrfx_prs/sample.yaml index 9a15c276859..149dd172483 100644 --- a/samples/boards/nrf/nrfx_prs/sample.yaml +++ b/samples/boards/nrf/nrfx_prs/sample.yaml @@ -3,11 +3,11 @@ sample: tests: sample.boards.nrf.nrfx_prs: platform_allow: - - nrf5340dk_nrf5340_cpuapp - - nrf9160dk_nrf9160 + - nrf5340dk/nrf5340/cpuapp + - nrf9160dk/nrf9160 integration_platforms: - - nrf5340dk_nrf5340_cpuapp - - nrf9160dk_nrf9160 + - nrf5340dk/nrf5340/cpuapp + - nrf9160dk/nrf9160 tags: nrfx harness: console harness_config: diff --git a/samples/boards/nrf/system_off/README.rst b/samples/boards/nrf/system_off/README.rst index 8d5636be0f9..fa1bacb110f 100644 --- a/samples/boards/nrf/system_off/README.rst +++ b/samples/boards/nrf/system_off/README.rst @@ -33,5 +33,5 @@ nRF52 core output *** Booting Zephyr OS build v2.3.0-rc1-204-g5f2eb85f728d *** - nrf52dk_nrf52832 system off demo + nrf52dk system off demo Entering system off; press sw0 to restart diff --git a/samples/boards/nrf/system_off/sample.yaml b/samples/boards/nrf/system_off/sample.yaml index 84a61f427b7..0a58d8fc009 100644 --- a/samples/boards/nrf/system_off/sample.yaml +++ b/samples/boards/nrf/system_off/sample.yaml @@ -3,18 +3,18 @@ sample: common: tags: power integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tests: sample.boards.nrf.system_off: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 sample.boards.nrf.system_off.retained: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 extra_configs: - CONFIG_APP_RETENTION=y diff --git a/samples/boards/nxp_s32/netc/README.rst b/samples/boards/nxp_s32/netc/README.rst index f779dcffed9..f8dca18f3be 100644 --- a/samples/boards/nxp_s32/netc/README.rst +++ b/samples/boards/nxp_s32/netc/README.rst @@ -36,7 +36,7 @@ To build and run the sample application for use-case 1: .. zephyr-app-commands:: :zephyr-app: samples/boards/nxp_s32/netc - :board: s32z270dc2_rtu0_r52 + :board: s32z2xxdc2/s32z270/rtu0 :goals: build flash Once started, you should see the network interface details, for example: @@ -59,7 +59,7 @@ To build and run the sample application for use-case 2: .. zephyr-app-commands:: :zephyr-app: samples/boards/nxp_s32/netc - :board: s32z270dc2_rtu0_r52 + :board: s32z2xxdc2/s32z270/rtu0 :goals: build flash :gen-args: -DDTC_OVERLAY_FILE="./vsi-and-psi.overlay" diff --git a/samples/boards/nxp_s32/netc/sample.yaml b/samples/boards/nxp_s32/netc/sample.yaml index 8329b04d134..9adf63fd16d 100644 --- a/samples/boards/nxp_s32/netc/sample.yaml +++ b/samples/boards/nxp_s32/netc/sample.yaml @@ -2,7 +2,9 @@ sample: description: Sample for show-casing the different use-cases of NXP S32 NETC driver name: NXP S32 NETC sample common: - platform_allow: s32z270dc2_rtu0_r52 + platform_allow: + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu0 depends_on: netif tags: net tests: diff --git a/samples/boards/stm32/ccm/README.rst b/samples/boards/stm32/ccm/README.rst index 3b5cc0a961e..76959722d7a 100644 --- a/samples/boards/stm32/ccm/README.rst +++ b/samples/boards/stm32/ccm/README.rst @@ -36,7 +36,7 @@ board's DTS file ``chosen`` section: For example the olimex STM32 E407 DTS file looks like this: -.. literalinclude:: ../../../../boards/arm/olimex_stm32_e407/olimex_stm32_e407.dts +.. literalinclude:: ../../../../boards/olimex/stm32_e407/olimex_stm32_e407.dts :linenos: Building and Running diff --git a/samples/boards/stm32/h7_dual_core/README.rst b/samples/boards/stm32/h7_dual_core/README.rst index 2fb5aa63f4f..eba0db90dfb 100644 --- a/samples/boards/stm32/h7_dual_core/README.rst +++ b/samples/boards/stm32/h7_dual_core/README.rst @@ -10,18 +10,18 @@ Blinky led triggered by mailbox new message. Building and Running ******************** -Build for stm32h747i_disco_m7: +Build for stm32h747i_disco/stm32h747xx/m7: .. zephyr-app-commands:: :zephyr-app: samples/boards/stm32/h7_dual_core - :board: stm32h747i_disco_m7 + :board: stm32h747i_disco/stm32h747xx/m7 :goals: build -Build for stm32h747i_disco_m4: +Build for stm32h747i_disco/stm32h747xx/m4: .. zephyr-app-commands:: :zephyr-app: samples/boards/stm32/h7_dual_core - :board: stm32h747i_disco_m4 + :board: stm32h747i_disco/stm32h747xx/m4 :goals: build Sample Output diff --git a/samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_m4.overlay b/samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_stm32h747xx_m4.overlay similarity index 100% rename from samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_m4.overlay rename to samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_stm32h747xx_m4.overlay diff --git a/samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_m7.overlay b/samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_m7.overlay rename to samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/samples/boards/up_squared/gpio_counter/CMakeLists.txt b/samples/boards/up_squared/gpio_counter/CMakeLists.txt index 82a09134bf4..be34f4fe1fd 100644 --- a/samples/boards/up_squared/gpio_counter/CMakeLists.txt +++ b/samples/boards/up_squared/gpio_counter/CMakeLists.txt @@ -6,4 +6,3 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) project(gpio_counter) target_sources(app PRIVATE src/main.c) -zephyr_include_directories(${ZEPHYR_BASE}/boards/x86/up_squared) diff --git a/samples/compression/lz4/README.rst b/samples/compression/lz4/README.rst index 18045284130..0188b52afe9 100644 --- a/samples/compression/lz4/README.rst +++ b/samples/compression/lz4/README.rst @@ -12,12 +12,12 @@ compress & decompress the user data to the console. Building and Running ******************** -The sample can be built and executed on nrf52840dk_nrf52840 as follows: +The sample can be built and executed on nrf52840dk/nrf52840 as follows: .. zephyr-app-commands:: :zephyr-app: samples/compression/lz4 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: -To build for another board, change "nrf52840dk_nrf52840" above to that board's name. +To build for another board, change "nrf52840dk/nrf52840" above to that board's name. diff --git a/samples/compression/lz4/sample.yaml b/samples/compression/lz4/sample.yaml index f9758f26984..a5c36ff7a8e 100644 --- a/samples/compression/lz4/sample.yaml +++ b/samples/compression/lz4/sample.yaml @@ -17,7 +17,7 @@ common: tests: sample.compression.lz4: integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_riscv64 tags: - compression diff --git a/samples/drivers/adc/boards/longan_nano_lite.overlay b/samples/drivers/adc/boards/longan_nano_gd32vf103_lite.overlay similarity index 100% rename from samples/drivers/adc/boards/longan_nano_lite.overlay rename to samples/drivers/adc/boards/longan_nano_gd32vf103_lite.overlay diff --git a/samples/drivers/adc/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/samples/drivers/adc/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay new file mode 100644 index 00000000000..a27042020df --- /dev/null +++ b/samples/drivers/adc/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -0,0 +1,34 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright 2021,2023 NXP + */ + +#include + +/ { + zephyr,user { + /* adjust channel number according to pinmux in board.dts */ + io-channels = <&lpadc0 0>; + }; +}; + +&lpadc0 { + #address-cells = <1>; + #size-cells = <0>; + + /* + * To use this sample: + * - Connect LPADC0 CH0 signal to voltage between 0~1.8V (J9 pin 10) + */ + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_EXTERNAL0"; + zephyr,vref-mv = <1800>; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,input-positive = ; + }; +}; diff --git a/samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay b/samples/drivers/adc/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay rename to samples/drivers/adc/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/samples/drivers/adc/boards/mimxrt1170_evkb_cm7.overlay b/samples/drivers/adc/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from samples/drivers/adc/boards/mimxrt1170_evkb_cm7.overlay rename to samples/drivers/adc/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/samples/drivers/adc/boards/mimxrt595_evk_cm33.overlay b/samples/drivers/adc/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from samples/drivers/adc/boards/mimxrt595_evk_cm33.overlay rename to samples/drivers/adc/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/samples/drivers/adc/boards/mimxrt685_evk_cm33.overlay b/samples/drivers/adc/boards/mimxrt685_evk.overlay similarity index 100% rename from samples/drivers/adc/boards/mimxrt685_evk_cm33.overlay rename to samples/drivers/adc/boards/mimxrt685_evk.overlay diff --git a/samples/drivers/adc/boards/nrf51dk_nrf51422.overlay b/samples/drivers/adc/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/drivers/adc/boards/nrf51dk_nrf51422.overlay rename to samples/drivers/adc/boards/nrf51dk_nrf51822.overlay diff --git a/samples/drivers/adc/boards/tdk_robokit1.overlay b/samples/drivers/adc/boards/robokit1.overlay similarity index 100% rename from samples/drivers/adc/boards/tdk_robokit1.overlay rename to samples/drivers/adc/boards/robokit1.overlay diff --git a/samples/drivers/adc/boards/sam_e70_xplained.overlay b/samples/drivers/adc/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from samples/drivers/adc/boards/sam_e70_xplained.overlay rename to samples/drivers/adc/boards/sam_e70_xplained_same70q21.overlay diff --git a/samples/drivers/adc/boards/sam_v71_xult.overlay b/samples/drivers/adc/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from samples/drivers/adc/boards/sam_v71_xult.overlay rename to samples/drivers/adc/boards/sam_v71_xult_samv71q21.overlay diff --git a/samples/drivers/adc/boards/atsamc21n_xpro.overlay b/samples/drivers/adc/boards/samc21n_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsamc21n_xpro.overlay rename to samples/drivers/adc/boards/samc21n_xpro.overlay diff --git a/samples/drivers/adc/boards/atsamd21_xpro.overlay b/samples/drivers/adc/boards/samd21_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsamd21_xpro.overlay rename to samples/drivers/adc/boards/samd21_xpro.overlay diff --git a/samples/drivers/adc/boards/atsame54_xpro.overlay b/samples/drivers/adc/boards/same54_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsame54_xpro.overlay rename to samples/drivers/adc/boards/same54_xpro.overlay diff --git a/samples/drivers/adc/boards/atsaml21_xpro.overlay b/samples/drivers/adc/boards/saml21_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsaml21_xpro.overlay rename to samples/drivers/adc/boards/saml21_xpro.overlay diff --git a/samples/drivers/adc/boards/atsamr21_xpro.overlay b/samples/drivers/adc/boards/samr21_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsamr21_xpro.overlay rename to samples/drivers/adc/boards/samr21_xpro.overlay diff --git a/samples/drivers/adc/boards/atsamr34_xpro.overlay b/samples/drivers/adc/boards/samr34_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsamr34_xpro.overlay rename to samples/drivers/adc/boards/samr34_xpro.overlay diff --git a/samples/drivers/adc/sample.yaml b/samples/drivers/adc/sample.yaml index 2ed1681a0e0..7b523ea062c 100644 --- a/samples/drivers/adc/sample.yaml +++ b/samples/drivers/adc/sample.yaml @@ -13,25 +13,25 @@ tests: - cy8cproto_063_ble - stm32l496g_disco - stm32h735g_disco - - nrf51dk_nrf51422 - - nrf52840dk_nrf52840 + - nrf51dk/nrf51822 + - nrf52840dk/nrf52840 - mec172xevb_assy6906 - gd32f350r_eval - gd32f450i_eval - gd32vf103v_eval - gd32f403z_eval - - esp32_devkitc_wroom - - esp32_devkitc_wrover + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu - esp32s2_saola - esp32c3_devkitm - gd32l233r_eval - lpcxpresso55s36 - mr_canhubk3 - longan_nano - - longan_nano_lite + - longan_nano/gd32vf103/lite integration_platforms: - nucleo_l073rz - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 harness: console timeout: 10 harness_config: diff --git a/samples/drivers/audio/dmic/README.rst b/samples/drivers/audio/dmic/README.rst index 3e1463795c0..1382ff0a9ce 100644 --- a/samples/drivers/audio/dmic/README.rst +++ b/samples/drivers/audio/dmic/README.rst @@ -17,8 +17,8 @@ Requirements The device to be used by the sample is specified by defining a devicetree node label named ``dmic_dev``. -The sample has been tested on :ref:`nrf52840dk_nrf52840` (nrf52840dk_nrf52840) -and :ref:`nrf5340dk_nrf5340` (nrf5340dk_nrf5340_cpuapp), and provides overlay +The sample has been tested on :ref:`nrf52840dk_nrf52840` (nrf52840dk/nrf52840) +and :ref:`nrf5340dk_nrf5340` (nrf5340dk/nrf5340/cpuapp), and provides overlay files for both of these boards. Building and Running @@ -30,6 +30,6 @@ To build and flash the application: .. zephyr-app-commands:: :zephyr-app: samples/drivers/audio/dmic - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/drivers/audio/dmic/boards/mimxrt595_evk_cm33.overlay b/samples/drivers/audio/dmic/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from samples/drivers/audio/dmic/boards/mimxrt595_evk_cm33.overlay rename to samples/drivers/audio/dmic/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/samples/drivers/audio/dmic/sample.yaml b/samples/drivers/audio/dmic/sample.yaml index 07a086518ec..8cc5464b781 100644 --- a/samples/drivers/audio/dmic/sample.yaml +++ b/samples/drivers/audio/dmic/sample.yaml @@ -5,8 +5,8 @@ tests: tags: dmic filter: dt_nodelabel_enabled("dmic_dev") integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp harness: console harness_config: type: multi_line diff --git a/samples/drivers/can/counter/README.rst b/samples/drivers/can/counter/README.rst index 6addd47b714..3b66661a714 100644 --- a/samples/drivers/can/counter/README.rst +++ b/samples/drivers/can/counter/README.rst @@ -38,12 +38,12 @@ For the NXP TWR-KE18F board: Stand alone CAN controller ========================== -For the nrf52dk_nrf52832 board combined with the DFRobot CAN bus V2.0 shield that +For the nrf52dk/nrf52832 board combined with the DFRobot CAN bus V2.0 shield that provides the MCP2515 CAN controller: .. zephyr-app-commands:: :zephyr-app: samples/drivers/can/counter - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :shield: dfrobot_can_bus_v2_0 :goals: build flash diff --git a/samples/drivers/clock_control_xec/src/main.c b/samples/drivers/clock_control_xec/src/main.c index d4462bb882b..21d598fa501 100644 --- a/samples/drivers/clock_control_xec/src/main.c +++ b/samples/drivers/clock_control_xec/src/main.c @@ -17,7 +17,7 @@ LOG_MODULE_REGISTER(clock32k, CONFIG_CLOCK_CONTROL_LOG_LEVEL); #include -#ifdef CONFIG_SOC_SERIES_MEC1501X +#ifdef CONFIG_SOC_SERIES_MEC15XX static void pcr_clock_regs(void) { struct pcr_regs *pcr = ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 0)); diff --git a/samples/drivers/counter/alarm/boards/bl5340_dvk_cpuapp.conf b/samples/drivers/counter/alarm/boards/bl5340_dvk_nrf5340_cpuapp.conf similarity index 100% rename from samples/drivers/counter/alarm/boards/bl5340_dvk_cpuapp.conf rename to samples/drivers/counter/alarm/boards/bl5340_dvk_nrf5340_cpuapp.conf diff --git a/samples/drivers/counter/alarm/boards/bl5340_dvk_cpuapp.overlay b/samples/drivers/counter/alarm/boards/bl5340_dvk_nrf5340_cpuapp.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/bl5340_dvk_cpuapp.overlay rename to samples/drivers/counter/alarm/boards/bl5340_dvk_nrf5340_cpuapp.overlay diff --git a/samples/drivers/counter/alarm/boards/nrf51dk_nrf51422.overlay b/samples/drivers/counter/alarm/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/nrf51dk_nrf51422.overlay rename to samples/drivers/counter/alarm/boards/nrf51dk_nrf51822.overlay diff --git a/samples/drivers/counter/alarm/boards/s32z270dc2_rtu0_r52.overlay b/samples/drivers/counter/alarm/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/s32z270dc2_rtu0_r52.overlay rename to samples/drivers/counter/alarm/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/samples/drivers/counter/alarm/boards/s32z270dc2_rtu1_r52.overlay b/samples/drivers/counter/alarm/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/s32z270dc2_rtu1_r52.overlay rename to samples/drivers/counter/alarm/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/samples/drivers/counter/alarm/boards/sam_e70_xplained.overlay b/samples/drivers/counter/alarm/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/sam_e70_xplained.overlay rename to samples/drivers/counter/alarm/boards/sam_e70_xplained_same70q21.overlay diff --git a/samples/drivers/counter/alarm/boards/sam_e70b_xplained.overlay b/samples/drivers/counter/alarm/boards/sam_e70_xplained_same70q21b.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/sam_e70b_xplained.overlay rename to samples/drivers/counter/alarm/boards/sam_e70_xplained_same70q21b.overlay diff --git a/samples/drivers/counter/alarm/boards/sam_v71_xult.overlay b/samples/drivers/counter/alarm/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/sam_v71_xult.overlay rename to samples/drivers/counter/alarm/boards/sam_v71_xult_samv71q21.overlay diff --git a/samples/drivers/counter/alarm/boards/sam_v71b_xult.overlay b/samples/drivers/counter/alarm/boards/sam_v71_xult_samv71q21b.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/sam_v71b_xult.overlay rename to samples/drivers/counter/alarm/boards/sam_v71_xult_samv71q21b.overlay diff --git a/samples/drivers/counter/alarm/boards/stm32l562e_dk_ns.conf b/samples/drivers/counter/alarm/boards/stm32l562e_dk_stm32l562xx_ns.conf similarity index 100% rename from samples/drivers/counter/alarm/boards/stm32l562e_dk_ns.conf rename to samples/drivers/counter/alarm/boards/stm32l562e_dk_stm32l562xx_ns.conf diff --git a/samples/drivers/counter/alarm/sample.yaml b/samples/drivers/counter/alarm/sample.yaml index fe81529a45b..6b93637ccaa 100644 --- a/samples/drivers/counter/alarm/sample.yaml +++ b/samples/drivers/counter/alarm/sample.yaml @@ -8,12 +8,12 @@ tests: harness: console platform_allow: - nucleo_f746zg - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - atsamd20_xpro - - bl5340_dvk_cpuapp + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - samd20_xpro + - bl5340_dvk/nrf5340/cpuapp - gd32e103v_eval - gd32e507z_eval - gd32f403z_eval diff --git a/samples/drivers/counter/alarm/src/main.c b/samples/drivers/counter/alarm/src/main.c index 9eee4d3fba2..2b009068ba9 100644 --- a/samples/drivers/counter/alarm/src/main.c +++ b/samples/drivers/counter/alarm/src/main.c @@ -15,9 +15,9 @@ struct counter_alarm_cfg alarm_cfg; -#if defined(CONFIG_BOARD_ATSAMD20_XPRO) +#if defined(CONFIG_BOARD_SAMD20_XPRO) #define TIMER DT_NODELABEL(tc4) -#elif defined(CONFIG_SOC_FAMILY_SAM) +#elif defined(CONFIG_SOC_FAMILY_ATMEL_SAM) #define TIMER DT_NODELABEL(tc0) #elif defined(CONFIG_COUNTER_MICROCHIP_MCP7940N) #define TIMER DT_NODELABEL(extrtc0) diff --git a/samples/drivers/counter/maxim_ds3231/boards/nrf51dk_nrf51422.overlay b/samples/drivers/counter/maxim_ds3231/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/drivers/counter/maxim_ds3231/boards/nrf51dk_nrf51422.overlay rename to samples/drivers/counter/maxim_ds3231/boards/nrf51dk_nrf51822.overlay diff --git a/samples/drivers/counter/maxim_ds3231/sample.yaml b/samples/drivers/counter/maxim_ds3231/sample.yaml index 4e9c209047c..bf32d825e7a 100644 --- a/samples/drivers/counter/maxim_ds3231/sample.yaml +++ b/samples/drivers/counter/maxim_ds3231/sample.yaml @@ -8,7 +8,7 @@ tests: platform_allow: - efr32mg_sltb004a - frdm_k64f - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 - nucleo_l476rg - particle_xenon integration_platforms: diff --git a/samples/drivers/dac/README.rst b/samples/drivers/dac/README.rst index 2803abd8ba7..a9983494389 100644 --- a/samples/drivers/dac/README.rst +++ b/samples/drivers/dac/README.rst @@ -171,7 +171,7 @@ built and executed for the :ref:`bl5340_dvk` as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/dac - :board: bl5340_dvk_cpuapp + :board: bl5340_dvk/nrf5340/cpuapp :goals: build flash :compact: @@ -206,7 +206,7 @@ also can run for the .. zephyr-app-commands:: :zephyr-app: samples/drivers/dac - :board: longan_nano_lite + :board: longan_nano/gd32vf103/lite :goals: build flash :compact: diff --git a/samples/drivers/dac/boards/bl5340_dvk_cpuapp.overlay b/samples/drivers/dac/boards/bl5340_dvk_nrf5340_cpuapp.overlay similarity index 100% rename from samples/drivers/dac/boards/bl5340_dvk_cpuapp.overlay rename to samples/drivers/dac/boards/bl5340_dvk_nrf5340_cpuapp.overlay diff --git a/samples/drivers/dac/boards/longan_nano_lite.overlay b/samples/drivers/dac/boards/longan_nano_gd32vf103_lite.overlay similarity index 100% rename from samples/drivers/dac/boards/longan_nano_lite.overlay rename to samples/drivers/dac/boards/longan_nano_gd32vf103_lite.overlay diff --git a/samples/drivers/dac/boards/sam_e70_xplained.overlay b/samples/drivers/dac/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from samples/drivers/dac/boards/sam_e70_xplained.overlay rename to samples/drivers/dac/boards/sam_e70_xplained_same70q21.overlay diff --git a/samples/drivers/dac/boards/sam_e70b_xplained.overlay b/samples/drivers/dac/boards/sam_e70_xplained_same70q21b.overlay similarity index 100% rename from samples/drivers/dac/boards/sam_e70b_xplained.overlay rename to samples/drivers/dac/boards/sam_e70_xplained_same70q21b.overlay diff --git a/samples/drivers/dac/boards/sam_v71_xult.overlay b/samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from samples/drivers/dac/boards/sam_v71_xult.overlay rename to samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay diff --git a/samples/drivers/dac/boards/sam_v71b_xult.overlay b/samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay similarity index 100% rename from samples/drivers/dac/boards/sam_v71b_xult.overlay rename to samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay diff --git a/samples/drivers/dac/sample.yaml b/samples/drivers/dac/sample.yaml index 8ac2943ecfc..e83c20d5fc0 100644 --- a/samples/drivers/dac/sample.yaml +++ b/samples/drivers/dac/sample.yaml @@ -9,18 +9,18 @@ tests: - bl652_dvk - bl653_dvk - bl654_dvk - - bl5340_dvk_cpuapp + - bl5340_dvk/nrf5340/cpuapp - disco_l475_iot1 - - esp32_devkitc_wroom - - esp32_devkitc_wrover + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu - esp32s2_saola - frdm_k22f - frdm_k64f - gd32a503v_eval - gd32e103v_eval - gd32f450i_eval - - longan_nano_lite - longan_nano + - longan_nano/gd32vf103/lite - nucleo_f091rc - nucleo_f207zg - nucleo_f429zi @@ -35,10 +35,10 @@ tests: - nucleo_l552ze_q - nucleo_u575zi_q - nucleo_wl55jc - - sam_e70_xplained - - sam_e70b_xplained - - sam_v71_xult - - sam_v71b_xult + - sam_e70_xplained/same70q21 + - sam_e70_xplained/same70q21b + - sam_v71_xult/samv71q21 + - sam_v71_xult/samv71q21b - stm32f3_disco - stm32l562e_dk - twr_ke18f diff --git a/samples/drivers/display/README.rst b/samples/drivers/display/README.rst index 872a0b5f5d2..68a25e1b996 100644 --- a/samples/drivers/display/README.rst +++ b/samples/drivers/display/README.rst @@ -25,7 +25,7 @@ Below is an example on how to build for a :ref:`nrf52840dk_nrf52840` board with .. zephyr-app-commands:: :zephyr-app: samples/drivers/display - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :shield: adafruit_2_8_tft_touch_v2 :compact: diff --git a/samples/drivers/display/boards/mimxrt1170_evk_cm7.conf b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from samples/drivers/display/boards/mimxrt1170_evk_cm7.conf rename to samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000..072545354b9 --- /dev/null +++ b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,7 @@ +# +# Copyright 2023, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_HEAP_MEM_POOL_SIZE=4194304 diff --git a/samples/drivers/display/boards/mimxrt595_evk_cm33.conf b/samples/drivers/display/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from samples/drivers/display/boards/mimxrt595_evk_cm33.conf rename to samples/drivers/display/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/samples/drivers/display/sample.yaml b/samples/drivers/display/sample.yaml index 579773f3c8c..e1d938eda05 100644 --- a/samples/drivers/display/sample.yaml +++ b/samples/drivers/display/sample.yaml @@ -9,8 +9,8 @@ tests: - arduino_spi platform_exclude: - reel_board - - reel_board_v2 - - ubx_evkannab1_nrf52832 + - reel_board@2 + - ubx_evkannab1/nrf52832 - stm32f769i_disco - pan1781_evb - pan1782_evb @@ -23,7 +23,7 @@ tests: harness_config: fixture: fixture_display sample.display.shield.ssd1306_128x32: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=ssd1306_128x32 tags: - display @@ -32,7 +32,7 @@ tests: harness_config: fixture: fixture_display sample.display.shield.ssd1306_128x64: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=ssd1306_128x64 tags: - display @@ -41,19 +41,19 @@ tests: harness_config: fixture: fixture_display sample.display.shield.waveshare_epaper_gdeh0213b1: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=waveshare_epaper_gdeh0213b1 harness: console harness_config: fixture: fixture_display sample.display.shield.waveshare_epaper_gdew042t2: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=waveshare_epaper_gdew042t2 harness: console harness_config: fixture: fixture_display sample.display.st7789v_tl019fqv01: - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 extra_args: SHIELD=st7789v_tl019fqv01 tags: - display @@ -62,7 +62,7 @@ tests: harness_config: fixture: fixture_display sample.display.st7789v_waveshare_240x240: - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 extra_args: SHIELD=st7789v_waveshare_240x240 tags: - display @@ -71,7 +71,7 @@ tests: harness_config: fixture: fixture_display sample.display.ls013b7dh03: - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 extra_args: SHIELD=ls013b7dh03 tags: - display @@ -80,7 +80,7 @@ tests: harness_config: fixture: fixture_display sample.display.st7735r_ada_160x128: - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 extra_args: SHIELD=st7735r_ada_160x128 tags: - display @@ -95,7 +95,7 @@ tests: harness_config: fixture: fixture_display sample.display.mcux_dcnano_lcdif: - platform_allow: mimxrt595_evk_cm33 + platform_allow: mimxrt595_evk/mimxrt595s/cm33 tags: display harness: console extra_args: SHIELD=rk055hdmipi4m @@ -118,7 +118,7 @@ tests: - CONFIG_TEST=y tags: display sample.display.max7219: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=max7219_8x8 tags: - display @@ -127,7 +127,7 @@ tests: harness_config: fixture: fixture_display sample.display.st_b_lcd40_dsi1_mb1166: - platform_allow: stm32h747i_disco_m7 + platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: SHIELD=st_b_lcd40_dsi1_mb1166 tags: - display @@ -136,7 +136,7 @@ tests: harness_config: fixture: fixture_display sample.display.g1120b0mipi: - platform_allow: mimxrt595_evk_cm33 + platform_allow: mimxrt595_evk/mimxrt595s/cm33 tags: display harness: console extra_args: SHIELD=g1120b0mipi diff --git a/samples/drivers/eeprom/README.rst b/samples/drivers/eeprom/README.rst index 079a3ebb469..5381444bac5 100644 --- a/samples/drivers/eeprom/README.rst +++ b/samples/drivers/eeprom/README.rst @@ -30,7 +30,7 @@ as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/eeprom - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :shield: x_nucleo_eeprma2 :compact: diff --git a/samples/drivers/eeprom/sample.yaml b/samples/drivers/eeprom/sample.yaml index c9dfa7dd071..1c592eb8781 100644 --- a/samples/drivers/eeprom/sample.yaml +++ b/samples/drivers/eeprom/sample.yaml @@ -26,9 +26,9 @@ tests: - arduino_i2c - arduino_spi platform_exclude: - - ubx_evkannab1_nrf52832 - - sam_v71_xult - - sam_v71b_xult + - ubx_evkannab1/nrf52832 + - sam_v71_xult/samv71q21 + - sam_v71_xult/samv71q21b - pan1781_evb - pan1782_evb - pan1770_evb diff --git a/samples/drivers/flash_shell/sample.yaml b/samples/drivers/flash_shell/sample.yaml index 2734a63c7de..cd19cdad656 100644 --- a/samples/drivers/flash_shell/sample.yaml +++ b/samples/drivers/flash_shell/sample.yaml @@ -8,11 +8,11 @@ tests: - shell filter: CONFIG_FLASH_HAS_DRIVER_ENABLED platform_exclude: - - nucleo_h745zi_q_m4 - - stm32h747i_disco_m4 + - nucleo_h745zi_q/stm32h745xx/m4 + - stm32h747i_disco/stm32h747xx/m4 - gd32f350r_eval - - arduino_portenta_h7_m4 - - arduino_giga_r1_m4 + - arduino_portenta_h7/stm32h747xx/m4 + - arduino_giga_r1/stm32h747xx/m4 harness: keyboard min_ram: 12 integration_platforms: diff --git a/samples/drivers/ht16k33/README.rst b/samples/drivers/ht16k33/README.rst index 06fcc50a697..f0bde1a1079 100644 --- a/samples/drivers/ht16k33/README.rst +++ b/samples/drivers/ht16k33/README.rst @@ -28,7 +28,7 @@ connect an HT16K33 LED driver at address 0x70 on the I2C-0 bus. .. zephyr-app-commands:: :zephyr-app: samples/drivers/ht16k33 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/drivers/ht16k33/sample.yaml b/samples/drivers/ht16k33/sample.yaml index ed0ed04acd6..3bb0107b60b 100644 --- a/samples/drivers/ht16k33/sample.yaml +++ b/samples/drivers/ht16k33/sample.yaml @@ -3,6 +3,6 @@ sample: name: HT16K33 sample tests: sample.drivers.ht16k33: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 harness: TBD tags: LED diff --git a/samples/drivers/i2s/echo/README.rst b/samples/drivers/i2s/echo/README.rst index 8f7838d6298..6dfb674c1e2 100644 --- a/samples/drivers/i2s/echo/README.rst +++ b/samples/drivers/i2s/echo/README.rst @@ -22,8 +22,8 @@ a devicetree node label named ``i2s_rxtx`` or separate node labels ``i2s_rx`` and ``i2s_tx`` if separate I2S devices are to be used for the RX and TX streams. -This sample has been tested on :ref:`nrf52840dk_nrf52840` (nrf52840dk_nrf52840) -and :ref:`nrf5340dk_nrf5340` (nrf5340dk_nrf5340_cpuapp), using the Audio Codec +This sample has been tested on :ref:`nrf52840dk_nrf52840` (nrf52840dk/nrf52840) +and :ref:`nrf5340dk_nrf5340` (nrf5340dk/nrf5340/cpuapp), using the Audio Codec Shield, and provides overlay files for both of these boards. More information about the used shield and the CODEC itself can be found here: @@ -40,7 +40,7 @@ To build and flash the application: .. zephyr-app-commands:: :zephyr-app: samples/drivers/i2s/echo - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/drivers/i2s/echo/sample.yaml b/samples/drivers/i2s/echo/sample.yaml index f5ce0e58dd0..ca9c7bc859b 100644 --- a/samples/drivers/i2s/echo/sample.yaml +++ b/samples/drivers/i2s/echo/sample.yaml @@ -6,8 +6,8 @@ tests: filter: dt_nodelabel_enabled("i2s_rxtx") or (dt_nodelabel_enabled("i2s_rx") and dt_nodelabel_enabled("i2s_tx")) integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp platform_exclude: litex_vexriscv harness: console harness_config: diff --git a/samples/drivers/ipm/ipm_esp32/CMakeLists.txt b/samples/drivers/ipm/ipm_esp32/CMakeLists.txt index 83869676324..c4399df8a92 100644 --- a/samples/drivers/ipm/ipm_esp32/CMakeLists.txt +++ b/samples/drivers/ipm/ipm_esp32/CMakeLists.txt @@ -4,12 +4,12 @@ cmake_minimum_required(VERSION 3.20.0) set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/ipm_esp32_appcpu-prefix/src/ipm_esp32_appcpu-build/zephyr) -if("${BOARD}" STREQUAL "esp32_devkitc_wrover") - set(BOARD_REMOTE "esp32_devkitc_wrover_appcpu") -elseif("${BOARD}" STREQUAL "esp32_devkitc_wroom") - set(BOARD_REMOTE "esp32_devkitc_wroom_appcpu") -elseif("${BOARD}" STREQUAL "esp32s3_devkitm") - set(BOARD_REMOTE "esp32s3_devkitm_appcpu") +if("${BOARD}" STREQUAL "esp32_devkitc_wrover/esp32/procpu") + set(BOARD_REMOTE "esp32_devkitc_wrover/esp32/appcpu") +elseif("${BOARD}" STREQUAL "esp32_devkitc_wroom/esp32/procpu") + set(BOARD_REMOTE "esp32_devkitc_wroom/esp32/appcpu") +elseif("${BOARD}" STREQUAL "esp32s3_devkitm/esp32s3/procpu") + set(BOARD_REMOTE "esp32s3_devkitm/esp32s3/appcpu") else() message(FATAL_ERROR "${BOARD} was not supported for this sample") endif() diff --git a/samples/drivers/ipm/ipm_esp32/README.rst b/samples/drivers/ipm/ipm_esp32/README.rst index 3219ee7b307..5deb498b2f9 100644 --- a/samples/drivers/ipm/ipm_esp32/README.rst +++ b/samples/drivers/ipm/ipm_esp32/README.rst @@ -26,7 +26,7 @@ Build the ESP32 IPM sample code as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_esp32 - :board: esp32_devkitc_wroom + :board: esp32_devkitc_wroom/esp32/procpu :goals: build :compact: diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom.conf b/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom.conf deleted file mode 100644 index 0bef3d481fd..00000000000 --- a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SOC_ESP32_PROCPU=y diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom.overlay b/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom_esp32_procpu.overlay similarity index 100% rename from samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom.overlay rename to samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom_esp32_procpu.overlay diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover.conf b/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover.conf deleted file mode 100644 index 0bef3d481fd..00000000000 --- a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SOC_ESP32_PROCPU=y diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover.overlay b/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover_esp32_procpu.overlay similarity index 100% rename from samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover.overlay rename to samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover_esp32_procpu.overlay diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm.conf b/samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm.conf deleted file mode 100644 index a8ee714a955..00000000000 --- a/samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SOC_ESP32S3_PROCPU=y diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm.overlay b/samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm_esp32s3_procpu.overlay similarity index 100% rename from samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm.overlay rename to samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm_esp32s3_procpu.overlay diff --git a/samples/drivers/ipm/ipm_esp32/boards/yd_esp32.overlay b/samples/drivers/ipm/ipm_esp32/boards/yd_esp32_esp32_procpu.overlay similarity index 100% rename from samples/drivers/ipm/ipm_esp32/boards/yd_esp32.overlay rename to samples/drivers/ipm/ipm_esp32/boards/yd_esp32_esp32_procpu.overlay diff --git a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wroom_appcpu.overlay b/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wroom_appcpu.overlay deleted file mode 100644 index 80f7950333f..00000000000 --- a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wroom_appcpu.overlay +++ /dev/null @@ -1,3 +0,0 @@ -&ipm0 { - status = "okay"; -}; diff --git a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wrover_appcpu.overlay b/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wrover_appcpu.overlay deleted file mode 100644 index 80f7950333f..00000000000 --- a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wrover_appcpu.overlay +++ /dev/null @@ -1,3 +0,0 @@ -&ipm0 { - status = "okay"; -}; diff --git a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32s3_dekvitm_appcpu.overlay b/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32s3_dekvitm_appcpu.overlay deleted file mode 100644 index 80f7950333f..00000000000 --- a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32s3_dekvitm_appcpu.overlay +++ /dev/null @@ -1,3 +0,0 @@ -&ipm0 { - status = "okay"; -}; diff --git a/samples/drivers/ipm/ipm_esp32/sample.yaml b/samples/drivers/ipm/ipm_esp32/sample.yaml index 0e7384093e5..68ef394450c 100644 --- a/samples/drivers/ipm/ipm_esp32/sample.yaml +++ b/samples/drivers/ipm/ipm_esp32/sample.yaml @@ -2,7 +2,10 @@ sample: name: ESP32 IPM Sample tests: sample.ipm.ipm_esp32: - platform_allow: esp32_devkitc_wroom esp32_devkitc_wrover + platform_allow: + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu tags: - samples - ipm + skip: true diff --git a/samples/drivers/ipm/ipm_imx/README.rst b/samples/drivers/ipm/ipm_imx/README.rst index 570f7115362..ecffdbede07 100644 --- a/samples/drivers/ipm/ipm_imx/README.rst +++ b/samples/drivers/ipm/ipm_imx/README.rst @@ -35,11 +35,11 @@ It can be built as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_imx - :board: udoo_neo_full_m4 + :board: udoo_neo_full/mcimx6x/m4 :goals: build flash :compact: -Follow the instructions in the :ref:`udoo_neo_full_m4` board documentation +Follow the instructions in the :ref:`udoo_neo_full` board documentation for how to load the Zephyr binary to the desired core and execute it. Building and Running the Linux Code diff --git a/samples/drivers/ipm/ipm_imx/sample.yaml b/samples/drivers/ipm/ipm_imx/sample.yaml index 227faf7a8dc..b6adc4db10f 100644 --- a/samples/drivers/ipm/ipm_imx/sample.yaml +++ b/samples/drivers/ipm/ipm_imx/sample.yaml @@ -5,13 +5,13 @@ sample: tests: sample.ipm.ipm_imx: build_only: true - filter: CONFIG_SOC_FAMILY_IMX + filter: CONFIG_SOC_FAMILY_NXP_IMX platform_allow: - - udoo_neo_full_m4 - - colibri_imx7d_m4 - - warp7_m4 + - udoo_neo_full/mcimx6x/m4 + - colibri_imx7d/mcimx7d/m4 + - warp7/mcimx7d/m4 integration_platforms: - - udoo_neo_full_m4 + - udoo_neo_full/mcimx6x/m4 tags: - samples - ipm diff --git a/samples/drivers/ipm/ipm_mcux/Kconfig.sysbuild b/samples/drivers/ipm/ipm_mcux/Kconfig.sysbuild index 208a052f83d..242d25e0f68 100644 --- a/samples/drivers/ipm/ipm_mcux/Kconfig.sysbuild +++ b/samples/drivers/ipm/ipm_mcux/Kconfig.sysbuild @@ -6,5 +6,5 @@ source "share/sysbuild/Kconfig" config IPM_REMOTE_BOARD string - default "lpcxpresso54114_m0" if $(BOARD) = "lpcxpresso54114_m4" - default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" + default "lpcxpresso54114/lpc54114/m0" if $(BOARD) = "lpcxpresso54114" + default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" diff --git a/samples/drivers/ipm/ipm_mcux/README.rst b/samples/drivers/ipm/ipm_mcux/README.rst index 1fcd1e9818e..887437403f5 100644 --- a/samples/drivers/ipm/ipm_mcux/README.rst +++ b/samples/drivers/ipm/ipm_mcux/README.rst @@ -21,21 +21,21 @@ Requirements - :ref:`lpcxpresso54114` board - :ref:`lpcxpresso55s69` board -Building the application for lpcxpresso54114_m4 -*********************************************** +Building the application for lpcxpresso54114/lpc54114/m4 +******************************************************** .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_mcux - :board: lpcxpresso54114_m4 + :board: lpcxpresso54114/lpc54114/m4 :goals: debug -Building the application for lpcxpresso55s69_cpu0 -************************************************* +Building the application for lpcxpresso55s69/lpc55s69/cpu0 +********************************************************** .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_mcux - :board: lpcxpresso55s69_cpu0 + :board: lpcxpresso55s69/lpc55s69/cpu0 :goals: debug Running diff --git a/samples/drivers/ipm/ipm_mcux/boards/lpcxpresso54114_m4.conf b/samples/drivers/ipm/ipm_mcux/boards/lpcxpresso54114_lpc54114_m4.conf similarity index 100% rename from samples/drivers/ipm/ipm_mcux/boards/lpcxpresso54114_m4.conf rename to samples/drivers/ipm/ipm_mcux/boards/lpcxpresso54114_lpc54114_m4.conf diff --git a/samples/drivers/ipm/ipm_mcux/remote/sample.yaml b/samples/drivers/ipm/ipm_mcux/remote/sample.yaml index 2daa7126308..82d8dc9e3de 100644 --- a/samples/drivers/ipm/ipm_mcux/remote/sample.yaml +++ b/samples/drivers/ipm/ipm_mcux/remote/sample.yaml @@ -5,9 +5,9 @@ sample: tests: sample.ipm.ipm_mcux.remote: platform_allow: - - lpcxpresso54114_m0 - - lpcxpresso55s69_cpu1 + - lpcxpresso54114/lpc54114/m0 + - lpcxpresso55s69/lpc55s69/cpu1 integration_platforms: - - lpcxpresso54114_m0 + - lpcxpresso54114/lpc54114/m0 tags: ipm harness: remote diff --git a/samples/drivers/ipm/ipm_mcux/sample.yaml b/samples/drivers/ipm/ipm_mcux/sample.yaml index 6d46791d7a4..4df4045e454 100644 --- a/samples/drivers/ipm/ipm_mcux/sample.yaml +++ b/samples/drivers/ipm/ipm_mcux/sample.yaml @@ -5,10 +5,10 @@ sample: tests: sample.ipm.ipm_mcux: platform_allow: - - lpcxpresso54114_m4 - - lpcxpresso55s69_cpu0 + - lpcxpresso54114/lpc54114/m4 + - lpcxpresso55s69/lpc55s69/cpu0 integration_platforms: - - lpcxpresso54114_m4 + - lpcxpresso54114/lpc54114/m4 tags: ipm harness: console sysbuild: true diff --git a/samples/drivers/ipm/ipm_mhu_dual_core/README.rst b/samples/drivers/ipm/ipm_mhu_dual_core/README.rst index fc6414d83ff..750b32fd0a0 100644 --- a/samples/drivers/ipm/ipm_mhu_dual_core/README.rst +++ b/samples/drivers/ipm/ipm_mhu_dual_core/README.rst @@ -27,7 +27,7 @@ It can be built and executed on Musca B1 CPU 0 as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_mhu_dual_core - :board: v2m_musca_b1 + :board: v2m_musca_b1/musca_b1 :goals: run :compact: @@ -36,7 +36,7 @@ It can be built and executed on Musca B1 CPU 1 as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_mhu_dual_core - :board: v2m_musca_b1_ns + :board: v2m_musca_b1/musca_b1/ns :goals: run :compact: diff --git a/samples/drivers/ipm/ipm_mhu_dual_core/sample.yaml b/samples/drivers/ipm/ipm_mhu_dual_core/sample.yaml index 935f5ced8d3..83473ed088d 100644 --- a/samples/drivers/ipm/ipm_mhu_dual_core/sample.yaml +++ b/samples/drivers/ipm/ipm_mhu_dual_core/sample.yaml @@ -5,7 +5,7 @@ tests: sample.ipm.ipm_mhu_dual_core: tags: ipm platform_allow: - - v2m_musca_b1 - - v2m_musca_b1_ns + - v2m_musca_b1/musca_b1 + - v2m_musca_b1/musca_b1/ns integration_platforms: - - v2m_musca_b1 + - v2m_musca_b1/musca_b1 diff --git a/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay b/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay index 68086d46fc7..e9bbc3fbf37 100644 --- a/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay +++ b/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay @@ -10,7 +10,7 @@ status = "disabled"; }; -/* The mx25, on nrf52840dk_nrf52840, uses pins for spi0, spi1, spi2 and spi3 +/* The mx25, on nrf52840dk/nrf52840, uses pins for spi0, spi1, spi2 and spi3 * to provide quad-spi feature. In individual specifications each of the spi * notes define own clock source (SCK), but spi2 shares the same clock source * as qspi configuration, which is pin (0,19). That is why spi2 is used here diff --git a/samples/drivers/jesd216/sample.yaml b/samples/drivers/jesd216/sample.yaml index c50ce41d0f3..4ab18259153 100644 --- a/samples/drivers/jesd216/sample.yaml +++ b/samples/drivers/jesd216/sample.yaml @@ -17,17 +17,17 @@ tests: - hifive1 - hifive_unleashed - hifive_unmatched - - mimxrt1170_evk_cm7 - - mimxrt1170_evk_cm4 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1170_evk/mimxrt1176/cm4 filter: dt_compat_enabled("jedec,spi-nor") depends_on: spi sample.drivers.jesd216.nrf52840dk_spi: extra_args: - DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_spi.overlay - OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_spi.conf - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.drivers.stm32.jesd216: filter: dt_compat_enabled("st,stm32-ospi-nor") or dt_compat_enabled("st,stm32-qspi-nor") depends_on: spi diff --git a/samples/drivers/lcd_hd44780/src/main.c b/samples/drivers/lcd_hd44780/src/main.c index 19f873e52d4..3210f9c0305 100644 --- a/samples/drivers/lcd_hd44780/src/main.c +++ b/samples/drivers/lcd_hd44780/src/main.c @@ -70,14 +70,13 @@ #include #include - -#if defined(CONFIG_SOC_PART_NUMBER_SAM3X8E) +#if defined(CONFIG_SOC_SAM3X8E) #define GPIO_NODE DT_NODELABEL(pioc) #else #error "Unsupported GPIO driver" #endif -#if defined(CONFIG_SOC_PART_NUMBER_SAM3X8E) +#if defined(CONFIG_SOC_SAM3X8E) /* Define GPIO OUT to LCD */ #define GPIO_PIN_PC12_D0 12 /* PC12 - pin 51 */ #define GPIO_PIN_PC13_D1 13 /* PC13 - pin 50 */ diff --git a/samples/drivers/led_lp5562/README.rst b/samples/drivers/led_lp5562/README.rst index 4848455ab32..62994f5e7a5 100644 --- a/samples/drivers/led_lp5562/README.rst +++ b/samples/drivers/led_lp5562/README.rst @@ -35,7 +35,7 @@ a LP5562 LED driver on the bus I2C0 at the address 0x30. .. zephyr-app-commands:: :zephyr-app: samples/drivers/led_lp5562 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/drivers/led_lp5562/sample.yaml b/samples/drivers/led_lp5562/sample.yaml index 24b46765155..128258cb9be 100644 --- a/samples/drivers/led_lp5562/sample.yaml +++ b/samples/drivers/led_lp5562/sample.yaml @@ -3,6 +3,6 @@ sample: name: LP5562 sample tests: sample.drivers.led.lp5562: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: led harness: TBD diff --git a/samples/drivers/led_lp5569/README.rst b/samples/drivers/led_lp5569/README.rst index f9d0f5febd9..456bc2baaad 100644 --- a/samples/drivers/led_lp5569/README.rst +++ b/samples/drivers/led_lp5569/README.rst @@ -18,7 +18,7 @@ a LP5569 LED controller on the bus I2C0 at the address 0x32. .. zephyr-app-commands:: :zephyr-app: samples/drivers/led_lp5569 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/drivers/led_lp5569/sample.yaml b/samples/drivers/led_lp5569/sample.yaml index 40d8f24ace1..25b03a87b31 100644 --- a/samples/drivers/led_lp5569/sample.yaml +++ b/samples/drivers/led_lp5569/sample.yaml @@ -3,5 +3,5 @@ sample: name: LP5569 sample tests: sample.drivers.led.lp5569: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: led diff --git a/samples/drivers/led_lpd8806/boards/96b_carbon.conf b/samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.conf similarity index 100% rename from samples/drivers/led_lpd8806/boards/96b_carbon.conf rename to samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.conf diff --git a/samples/drivers/led_lpd8806/boards/96b_carbon.overlay b/samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.overlay similarity index 100% rename from samples/drivers/led_lpd8806/boards/96b_carbon.overlay rename to samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.overlay diff --git a/samples/drivers/led_lpd8806/sample.yaml b/samples/drivers/led_lpd8806/sample.yaml index cca50ea3751..7d0e66d79ba 100644 --- a/samples/drivers/led_lpd8806/sample.yaml +++ b/samples/drivers/led_lpd8806/sample.yaml @@ -3,5 +3,5 @@ sample: name: LPD880x sample tests: sample.drivers.led.lpd8806: - platform_allow: 96b_carbon + platform_allow: 96b_carbon/stm32f401xe tags: LED diff --git a/samples/drivers/led_sx1509b_intensity/README.rst b/samples/drivers/led_sx1509b_intensity/README.rst index 2fdeee737ac..2ed8eb826ec 100644 --- a/samples/drivers/led_sx1509b_intensity/README.rst +++ b/samples/drivers/led_sx1509b_intensity/README.rst @@ -15,7 +15,7 @@ Building and Running .. zephyr-app-commands:: :zephyr-app: samples/drivers/led_sx1509b_intensity - :board: thingy52_nrf52832 + :board: thingy52/nrf52832 :goals: build flash :compact: diff --git a/samples/drivers/led_sx1509b_intensity/sample.yaml b/samples/drivers/led_sx1509b_intensity/sample.yaml index 9893d3a0969..532626276b7 100644 --- a/samples/drivers/led_sx1509b_intensity/sample.yaml +++ b/samples/drivers/led_sx1509b_intensity/sample.yaml @@ -9,6 +9,6 @@ sample: name: SX1509B intensity sample tests: sample.drivers.led.sx1509b_intensity: - platform_allow: thingy52_nrf52832 + platform_allow: thingy52/nrf52832 tags: LED depends_on: i2c diff --git a/samples/drivers/led_ws2812/README.rst b/samples/drivers/led_ws2812/README.rst index 183875520f2..d41bad1e207 100644 --- a/samples/drivers/led_ws2812/README.rst +++ b/samples/drivers/led_ws2812/README.rst @@ -69,7 +69,7 @@ To make sure the sample is set up properly for building, you must: For example devicetree configurations for each compatible, see :zephyr_file:`samples/drivers/led_ws2812/boards/thingy52_nrf52832.overlay`, :zephyr_file:`samples/drivers/led_ws2812/boards/nrf52dk_nrf52832.overlay` and -:zephyr_file:`samples/drivers/led_ws2812/boards/nrf51dk_nrf51422.overlay`. +:zephyr_file:`samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay`. Some boards are already supported out of the box; see the :file:`boards` directory for this sample for details. @@ -101,15 +101,14 @@ This sample uses different drivers depending on the selected board: I2S driver: -- thingy52_nrf52832 -- nrf5340dk_nrf5340 (3.3V logic level, a logic level shifter may be required) +- thingy52/nrf52832 +- nrf5340dk/nrf5340 (3.3V logic level, a logic level shifter may be required) - should work for other boards featuring an nRF5340 host processor SPI driver: - mimxrt1050_evk -- mimxrt1050_evk_qspi -- nrf52dk_nrf52832 +- nrf52dk/nrf52832 - nucleo_f070rb - nucleo_g071rb - nucleo_h743zi @@ -118,7 +117,7 @@ SPI driver: GPIO driver (cortex-M0 only): - bbc_microbit -- nrf51dk_nrf51422 +- nrf51dk/nrf51822 References ********** diff --git a/samples/drivers/led_ws2812/boards/nrf51dk_nrf51422.conf b/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf similarity index 100% rename from samples/drivers/led_ws2812/boards/nrf51dk_nrf51422.conf rename to samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf diff --git a/samples/drivers/led_ws2812/boards/nrf51dk_nrf51422.overlay b/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/nrf51dk_nrf51422.overlay rename to samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay diff --git a/samples/drivers/mbox/CMakeLists.txt b/samples/drivers/mbox/CMakeLists.txt index ec79db9deed..382aefad0dd 100644 --- a/samples/drivers/mbox/CMakeLists.txt +++ b/samples/drivers/mbox/CMakeLists.txt @@ -11,13 +11,13 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr) -if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp") OR +if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpuapp") OR - ("${BOARD}" STREQUAL "adp_xc7k_ae350") OR - ("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm7") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu0")) + ("${BOARD}" STREQUAL "adp_xc7k") OR + ("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69")) message(STATUS "${BOARD} compile as Main in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/Kconfig.sysbuild b/samples/drivers/mbox/Kconfig.sysbuild index a17dd56ee55..53f83ddeb9e 100644 --- a/samples/drivers/mbox/Kconfig.sysbuild +++ b/samples/drivers/mbox/Kconfig.sysbuild @@ -7,10 +7,10 @@ source "share/sysbuild/Kconfig" config REMOTE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" - default "adp_xc7k_ae350" if $(BOARD) = "adp_xc7k_ae350" - default "mimxrt1170_evkb_cm4" if $(BOARD) = "mimxrt1170_evkb_cm7" - default "mimxrt1170_evk_cm4" if $(BOARD) = "mimxrt1170_evk_cm7" - default "mimxrt1160_evk_cm4" if $(BOARD) = "mimxrt1160_evk_cm7" - default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" + default "adp_xc7k/ae350" if $(BOARD) = "adp_xc7k" + default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb" + default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" + default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" + default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" diff --git a/samples/drivers/mbox/README.rst b/samples/drivers/mbox/README.rst index cee903710f7..e4ab895ade4 100644 --- a/samples/drivers/mbox/README.rst +++ b/samples/drivers/mbox/README.rst @@ -14,12 +14,12 @@ Building and Running The sample can be built and executed on boards supporting MBOX. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/drivers/mbox/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: debug :west-args: --sysbuild diff --git a/samples/drivers/mbox/boards/lpcxpresso55s69_cpu0.conf b/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from samples/drivers/mbox/boards/lpcxpresso55s69_cpu0.conf rename to samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/samples/drivers/mbox/boards/lpcxpresso55s69_cpu0.overlay b/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from samples/drivers/mbox/boards/lpcxpresso55s69_cpu0.overlay rename to samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_cm7.conf b/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.conf similarity index 100% rename from samples/drivers/mbox/boards/mimxrt1170_evk_cm7.conf rename to samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.conf diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_cm7.overlay b/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from samples/drivers/mbox/boards/mimxrt1170_evk_cm7.overlay rename to samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_cm7.conf b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from samples/drivers/mbox_data/boards/mimxrt1170_evk_cm7.conf rename to samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/samples/drivers/mbox/boards/mimxrt1170_evkb_cm7.overlay b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from samples/drivers/mbox/boards/mimxrt1170_evkb_cm7.overlay rename to samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000..0dfb100ed70 --- /dev/null +++ b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_SECOND_CORE_MCUX=y +CONFIG_INCLUDE_REMOTE_DIR=y diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay new file mode 100644 index 00000000000..942f67ba6a9 --- /dev/null +++ b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -0,0 +1,29 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c48000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c48000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c48000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; diff --git a/samples/drivers/mbox/remote/CMakeLists.txt b/samples/drivers/mbox/remote/CMakeLists.txt index 2c7c8fff29e..5fbec71ce41 100644 --- a/samples/drivers/mbox/remote/CMakeLists.txt +++ b/samples/drivers/mbox/remote/CMakeLists.txt @@ -9,13 +9,13 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpunet") OR +if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpunet") OR - ("${BOARD}" STREQUAL "mimxrt1170_evkb_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm4") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu1") OR - ("${BOARD}" STREQUAL "adp_xc7k_ae350")) + ("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69") OR + ("${BOARD}" STREQUAL "adp_xc7k")) message(STATUS "${BOARD} compile as remote in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/remote/boards/lpcxpresso55s69_cpu1.conf b/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf similarity index 100% rename from samples/drivers/mbox/remote/boards/lpcxpresso55s69_cpu1.conf rename to samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf diff --git a/samples/drivers/mbox/remote/boards/lpcxpresso55s69_cpu1.overlay b/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay similarity index 100% rename from samples/drivers/mbox/remote/boards/lpcxpresso55s69_cpu1.overlay rename to samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay diff --git a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000..0d36a72aec6 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000..cc05e9b96c1 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,48 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000..0d36a72aec6 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000..cc05e9b96c1 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,48 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000..0d36a72aec6 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000..392141712a9 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,49 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; + +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml index e38deda55d3..1e0feb4e3f0 100644 --- a/samples/drivers/mbox/sample.yaml +++ b/samples/drivers/mbox/sample.yaml @@ -6,14 +6,14 @@ common: tests: sample.drivers.mbox.real_hw: platform_allow: - - nrf5340dk_nrf5340_cpuapp - - adp_xc7k_ae350 - - mimxrt1170_evkb_cm7 - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 - - lpcxpresso55s69_cpu0 + - nrf5340dk/nrf5340/cpuapp + - adp_xc7k/ae350 + - mimxrt1170_evk@B/mimxrt1176/cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp harness: console harness_config: type: multi_line diff --git a/samples/drivers/mbox/sysbuild.cmake b/samples/drivers/mbox/sysbuild.cmake index 063f6157ddb..2e7d69d9da5 100644 --- a/samples/drivers/mbox/sysbuild.cmake +++ b/samples/drivers/mbox/sysbuild.cmake @@ -23,7 +23,7 @@ native_simulator_set_final_executable(${DEFAULT_IMAGE}) if ("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7" OR "${BOARD}" STREQUAL "mimxrt1170_evk_cm7" OR "${BOARD}" STREQUAL "mimxrt1160_evk_cm7" OR - "${BOARD}" STREQUAL "lpcxpresso55s69_cpu0" + "${BOARD}" STREQUAL "lpcxpresso55s69" ) # For these NXP boards the main core application is dependent on # 'zephyr_image_info.h' generated by remote application. diff --git a/samples/drivers/mbox_data/CMakeLists.txt b/samples/drivers/mbox_data/CMakeLists.txt index a410ac3d214..fa444f592df 100644 --- a/samples/drivers/mbox_data/CMakeLists.txt +++ b/samples/drivers/mbox_data/CMakeLists.txt @@ -9,10 +9,10 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr) -if(("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm7") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu0")) +if(("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69")) message(STATUS "${BOARD} compile as Main in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox_data/Kconfig.sysbuild b/samples/drivers/mbox_data/Kconfig.sysbuild index 2ddab228177..66a4e929ae2 100644 --- a/samples/drivers/mbox_data/Kconfig.sysbuild +++ b/samples/drivers/mbox_data/Kconfig.sysbuild @@ -6,7 +6,7 @@ source "share/sysbuild/Kconfig" config REMOTE_BOARD string - default "mimxrt1170_evkb_cm4" if $(BOARD) = "mimxrt1170_evkb_cm7" - default "mimxrt1170_evk_cm4" if $(BOARD) = "mimxrt1170_evk_cm7" - default "mimxrt1160_evk_cm4" if $(BOARD) = "mimxrt1160_evk_cm7" - default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" + default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb" + default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" + default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" + default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" diff --git a/samples/drivers/mbox_data/boards/lpcxpresso55s69_cpu0.conf b/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from samples/drivers/mbox_data/boards/lpcxpresso55s69_cpu0.conf rename to samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/samples/drivers/mbox_data/boards/lpcxpresso55s69_cpu0.overlay b/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from samples/drivers/mbox_data/boards/lpcxpresso55s69_cpu0.overlay rename to samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_cm7.conf b/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf similarity index 100% rename from tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_cm7.conf rename to samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from samples/drivers/mbox_data/boards/mimxrt1170_evk_cm7.overlay rename to samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000..583b4950360 --- /dev/null +++ b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evkb_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from samples/drivers/mbox_data/boards/mimxrt1170_evkb_cm7.overlay rename to samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000..0dfb100ed70 --- /dev/null +++ b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_SECOND_CORE_MCUX=y +CONFIG_INCLUDE_REMOTE_DIR=y diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_cm7.overlay rename to samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/samples/drivers/mbox_data/remote/CMakeLists.txt b/samples/drivers/mbox_data/remote/CMakeLists.txt index 47e1cae8628..234d58a2164 100644 --- a/samples/drivers/mbox_data/remote/CMakeLists.txt +++ b/samples/drivers/mbox_data/remote/CMakeLists.txt @@ -7,10 +7,10 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(("${BOARD}" STREQUAL "mimxrt1170_evkb_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm4") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu1")) +if(("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69")) message(STATUS "${BOARD} compile as remote in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_cpu1.conf b/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf similarity index 100% rename from samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_cpu1.conf rename to samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf diff --git a/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_cpu1.overlay b/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay similarity index 100% rename from samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_cpu1.overlay rename to samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000..0d36a72aec6 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000..3f6115b9c58 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,54 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000..0d36a72aec6 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000..3f6115b9c58 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,54 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000..0d36a72aec6 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000..e3576826702 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,55 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; + +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox_data/sample.yaml b/samples/drivers/mbox_data/sample.yaml index b4a1e23a9bc..53390b5b16a 100644 --- a/samples/drivers/mbox_data/sample.yaml +++ b/samples/drivers/mbox_data/sample.yaml @@ -6,13 +6,13 @@ common: tests: sample.drivers.mbox_data.real_hw: platform_allow: - - mimxrt1170_evkb_cm7 - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 - - lpcxpresso55s69_cpu0 + - mimxrt1170_evk@B/mimxrt1176/cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 integration_platforms: - - mimxrt1160_evk_cm7 - - lpcxpresso55s69_cpu0 + - mimxrt1160_evk/mimxrt1166/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 harness: console harness_config: type: multi_line diff --git a/samples/drivers/memc/README.rst b/samples/drivers/memc/README.rst index 814b7e949fc..fbfcc08c606 100644 --- a/samples/drivers/memc/README.rst +++ b/samples/drivers/memc/README.rst @@ -23,11 +23,11 @@ This application can be built and executed on an RT595 EVK as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/memc :host-os: unix - :board: mimxrt595_evk_cm33 + :board: mimxrt595_evk/mimxrt595s/cm33 :goals: run :compact: -To build for another board, change "mimxrt595_evk_cm33" above to that +To build for another board, change "mimxrt595_evk/mimxrt595s/cm33" above to that board's name. Sample Output diff --git a/samples/drivers/memc/boards/mimxrt595_evk_cm33.overlay b/samples/drivers/memc/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from samples/drivers/memc/boards/mimxrt595_evk_cm33.overlay rename to samples/drivers/memc/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/samples/drivers/memc/sample.yaml b/samples/drivers/memc/sample.yaml index 2ffbc370252..d9fa753edf5 100644 --- a/samples/drivers/memc/sample.yaml +++ b/samples/drivers/memc/sample.yaml @@ -5,7 +5,7 @@ common: tags: memc filter: dt_alias_exists("sram-ext") integration_platforms: - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 harness: console harness_config: type: one_line diff --git a/samples/drivers/misc/ft800/README.rst b/samples/drivers/misc/ft800/README.rst index 5c72c3641e6..64e0742c759 100644 --- a/samples/drivers/misc/ft800/README.rst +++ b/samples/drivers/misc/ft800/README.rst @@ -33,7 +33,7 @@ described below: .. zephyr-app-commands:: :zephyr-app: samples/drivers/misc/ft800 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: flash :compact: @@ -42,7 +42,7 @@ below: .. zephyr-app-commands:: :zephyr-app: samples/drivers/misc/ft800 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: ftdi_vm800c :goals: flash :compact: diff --git a/samples/drivers/misc/ft800/sample.yaml b/samples/drivers/misc/ft800/sample.yaml index e9f89259e27..4d475ed8734 100644 --- a/samples/drivers/misc/ft800/sample.yaml +++ b/samples/drivers/misc/ft800/sample.yaml @@ -6,7 +6,7 @@ tests: - drivers - display depends_on: spi - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=ftdi_vm800c harness: display harness_config: diff --git a/samples/drivers/soc_flash_nrf/README.rst b/samples/drivers/soc_flash_nrf/README.rst index 2ee87739aad..2b69d8d6cb6 100644 --- a/samples/drivers/soc_flash_nrf/README.rst +++ b/samples/drivers/soc_flash_nrf/README.rst @@ -27,7 +27,7 @@ or `slot1_ns_partition`, when the Kconfig option is selected. .. zephyr-app-commands:: :zephyr-app: samples/drivers/soc_flash_nrf - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/drivers/soc_flash_nrf/sample.yaml b/samples/drivers/soc_flash_nrf/sample.yaml index d1f635ca93f..bdec7c607cc 100644 --- a/samples/drivers/soc_flash_nrf/sample.yaml +++ b/samples/drivers/soc_flash_nrf/sample.yaml @@ -3,11 +3,11 @@ sample: tests: sample.drivers.flash.soc_flash_nrf: platform_allow: - - nrf52dk_nrf52832 - - nrf9160dk_nrf9160 - - nrf9160dk_nrf9160_ns + - nrf52dk/nrf52832 + - nrf9160dk/nrf9160 + - nrf9160dk/nrf9160/ns integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: - flash - drivers diff --git a/samples/drivers/spi_bitbang/README.rst b/samples/drivers/spi_bitbang/README.rst index a8ff597f002..35a784139ee 100644 --- a/samples/drivers/spi_bitbang/README.rst +++ b/samples/drivers/spi_bitbang/README.rst @@ -25,7 +25,7 @@ test for receive data. .. zephyr-app-commands:: :zephyr-app: samples/drivers/spi_bitbang - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/drivers/spi_bitbang/sample.yaml b/samples/drivers/spi_bitbang/sample.yaml index cc0941d3b02..57fb178b093 100644 --- a/samples/drivers/spi_bitbang/sample.yaml +++ b/samples/drivers/spi_bitbang/sample.yaml @@ -6,7 +6,7 @@ tests: - drivers - spi - gpio - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 depends_on: gpio harness: console harness_config: diff --git a/samples/drivers/spi_flash/README.rst b/samples/drivers/spi_flash/README.rst index 6f2e81959be..3767444b3a2 100644 --- a/samples/drivers/spi_flash/README.rst +++ b/samples/drivers/spi_flash/README.rst @@ -25,7 +25,7 @@ The application will build only for a target that has a :ref:`devicetree ` section of the native_sim board diff --git a/samples/drivers/w1/scanner/README.rst b/samples/drivers/w1/scanner/README.rst index 325b02f528c..e9f460975eb 100644 --- a/samples/drivers/w1/scanner/README.rst +++ b/samples/drivers/w1/scanner/README.rst @@ -19,7 +19,7 @@ enable and configure the drivers. .. zephyr-app-commands:: :zephyr-app: samples/drivers/w1/scanner - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :gen-args: -DDTC_OVERLAY_FILE=w1_serial.overlay :goals: build flash :compact: diff --git a/samples/drivers/w1/scanner/sample.yaml b/samples/drivers/w1/scanner/sample.yaml index c05df2c59e2..9a610bf63f1 100644 --- a/samples/drivers/w1/scanner/sample.yaml +++ b/samples/drivers/w1/scanner/sample.yaml @@ -8,7 +8,7 @@ tests: sample.drivers.w1.scanner.ds2482-800: depends_on: arduino_i2c extra_args: DTC_OVERLAY_FILE=ds2482-800.overlay - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 harness_config: type: one_line regex: @@ -18,7 +18,7 @@ tests: depends_on: arduino_i2c extra_args: DTC_OVERLAY_FILE=ds2484.overlay platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nucleo_g0b1re harness_config: type: one_line @@ -29,7 +29,7 @@ tests: depends_on: arduino_i2c extra_args: DTC_OVERLAY_FILE=ds2485.overlay platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nucleo_g0b1re harness_config: type: one_line @@ -41,7 +41,7 @@ tests: - arduino_serial extra_args: DTC_OVERLAY_FILE=w1_serial.overlay platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nucleo_g0b1re harness_config: type: one_line diff --git a/samples/drivers/watchdog/sample.yaml b/samples/drivers/watchdog/sample.yaml index f3e11dda9b5..4297f28d77a 100644 --- a/samples/drivers/watchdog/sample.yaml +++ b/samples/drivers/watchdog/sample.yaml @@ -16,12 +16,12 @@ common: depends_on: watchdog tests: sample.drivers.watchdog: - filter: not (CONFIG_SOC_FAMILY_STM32 or CONFIG_SOC_FAMILY_GD32 or SOC_SERIES_GD32VF103) + filter: not (CONFIG_SOC_FAMILY_STM32 or CONFIG_SOC_FAMILY_GD_GD32 or SOC_SERIES_GD32VF103) platform_exclude: - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 - - s32z270dc2_rtu0_r52@D - - s32z270dc2_rtu1_r52@D + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 sample.drivers.watchdog.stm32_wwdg: extra_args: DTC_OVERLAY_FILE=boards/stm32_wwdg.overlay filter: dt_compat_enabled("st,stm32-window-watchdog") @@ -106,7 +106,7 @@ tests: sample.drivers.watchdog.s32z270dc2_r52: build_only: true platform_allow: - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 - - s32z270dc2_rtu0_r52@D - - s32z270dc2_rtu1_r52@D + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 diff --git a/samples/fuel_gauge/max17048/sample.yaml b/samples/fuel_gauge/max17048/sample.yaml index 0ae4d6c7f3d..82d2b537b81 100644 --- a/samples/fuel_gauge/max17048/sample.yaml +++ b/samples/fuel_gauge/max17048/sample.yaml @@ -3,7 +3,7 @@ sample: tests: sample.sensor.max17048: build_only: true - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: fuel_gauge diff --git a/samples/kernel/metairq_dispatch/sample.yaml b/samples/kernel/metairq_dispatch/sample.yaml index 82090751b33..38431c15c57 100644 --- a/samples/kernel/metairq_dispatch/sample.yaml +++ b/samples/kernel/metairq_dispatch/sample.yaml @@ -6,7 +6,7 @@ common: tags: - kernel integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 harness: console harness_config: diff --git a/samples/modules/canopennode/sample.yaml b/samples/modules/canopennode/sample.yaml index 279fdf46c28..7cc95c0ed17 100644 --- a/samples/modules/canopennode/sample.yaml +++ b/samples/modules/canopennode/sample.yaml @@ -20,7 +20,7 @@ tests: platform_exclude: - nucleo_h723zg - nucleo_h743zi - - nucleo_h745zi_q + - nucleo_h745zi_q/stm32h745xx/m7 - nucleo_h753zi sample.modules.canopennode.program_download: sysbuild: true diff --git a/samples/modules/lvgl/demos/boards/mimxrt1170_evk_cm7.conf b/samples/modules/lvgl/demos/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from samples/modules/lvgl/demos/boards/mimxrt1170_evk_cm7.conf rename to samples/modules/lvgl/demos/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/samples/modules/lvgl/demos/sample.yaml b/samples/modules/lvgl/demos/sample.yaml index bd7461dd46c..4184f7df1af 100644 --- a/samples/modules/lvgl/demos/sample.yaml +++ b/samples/modules/lvgl/demos/sample.yaml @@ -25,7 +25,7 @@ tests: extra_configs: - CONFIG_LV_Z_DEMO_WIDGETS=y sample.modules.lvgl.demos.st_b_lcd40_dsi1_mb1166: - platform_allow: stm32h747i_disco_m7 + platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: SHIELD=st_b_lcd40_dsi1_mb1166 harness: console harness_config: diff --git a/samples/modules/tflite-micro/hello_world/README.rst b/samples/modules/tflite-micro/hello_world/README.rst index 9d6fff4db93..6b639da4473 100644 --- a/samples/modules/tflite-micro/hello_world/README.rst +++ b/samples/modules/tflite-micro/hello_world/README.rst @@ -58,7 +58,7 @@ the `PATH` variable, then building and testing can be done with following commands. ``` -$ west build -p auto -b mps3_an547 samples/modules/tflite-micro/hello_world/ -T sample.tensorflow.helloworld.cmsis_nn +$ west build -p auto -b mps3/an547 samples/modules/tflite-micro/hello_world/ -T sample.tensorflow.helloworld.cmsis_nn $ FVP_Corstone_SSE-300_Ethos-U55 build/zephyr/zephyr.elf ``` diff --git a/samples/modules/tflite-micro/hello_world/sample.yaml b/samples/modules/tflite-micro/hello_world/sample.yaml index bfd142f6702..000db6fffe2 100644 --- a/samples/modules/tflite-micro/hello_world/sample.yaml +++ b/samples/modules/tflite-micro/hello_world/sample.yaml @@ -23,6 +23,6 @@ tests: filter: CONFIG_FULL_LIBC_SUPPORTED sample.tensorflow.helloworld.cmsis_nn: tags: tensorflow - platform_allow: mps3_an547 + platform_allow: mps3/an547 extra_configs: - CONFIG_TENSORFLOW_LITE_MICRO_CMSIS_NN_KERNELS=y diff --git a/samples/modules/tflite-micro/tflm_ethosu/README.rst b/samples/modules/tflite-micro/tflm_ethosu/README.rst index 0156ce8636c..3ebefa36095 100644 --- a/samples/modules/tflite-micro/tflm_ethosu/README.rst +++ b/samples/modules/tflite-micro/tflm_ethosu/README.rst @@ -33,5 +33,5 @@ commands. .. code-block:: bash - $ west build -b mps3_an547 zephyr/samples/modules/tflite-micro/tflm_ethosu + $ west build -b mps3/an547 zephyr/samples/modules/tflite-micro/tflm_ethosu $ FVP_Corstone_SSE-300_Ethos-U55 build/zephyr/zephyr.elf diff --git a/samples/modules/tflite-micro/tflm_ethosu/sample.yaml b/samples/modules/tflite-micro/tflm_ethosu/sample.yaml index e1ff20cbd0f..6e0342e6a56 100644 --- a/samples/modules/tflite-micro/tflm_ethosu/sample.yaml +++ b/samples/modules/tflite-micro/tflm_ethosu/sample.yaml @@ -10,4 +10,4 @@ tests: filter: dt_compat_enabled("arm,ethos-u") build_only: true integration_platforms: - - mps3_an547 + - mps3/an547 diff --git a/samples/modules/thrift/hello/client/sample.yaml b/samples/modules/thrift/hello/client/sample.yaml index 64ba41fe5e1..6a1ef0caecd 100644 --- a/samples/modules/thrift/hello/client/sample.yaml +++ b/samples/modules/thrift/hello/client/sample.yaml @@ -10,7 +10,7 @@ common: modules: - thrift platform_allow: - - mps2_an385 + - mps2/an385 - qemu_x86_64 integration_platforms: - qemu_x86_64 diff --git a/samples/modules/thrift/hello/server/sample.yaml b/samples/modules/thrift/hello/server/sample.yaml index 16b70a6b710..02bfe323d01 100644 --- a/samples/modules/thrift/hello/server/sample.yaml +++ b/samples/modules/thrift/hello/server/sample.yaml @@ -10,7 +10,7 @@ common: modules: - thrift platform_allow: - - mps2_an385 + - mps2/an385 - qemu_x86_64 integration_platforms: - qemu_x86_64 diff --git a/samples/net/cloud/mqtt_azure/sample.yaml b/samples/net/cloud/mqtt_azure/sample.yaml index ffa3e866895..0513b8e0c2a 100644 --- a/samples/net/cloud/mqtt_azure/sample.yaml +++ b/samples/net/cloud/mqtt_azure/sample.yaml @@ -7,7 +7,7 @@ tests: sample.net.cloud.mqtt_azure: harness: net platform_allow: - - sam_e70_xplained + - sam_e70_xplained/same70q21 - frdm_k64f - qemu_x86 integration_platforms: diff --git a/samples/net/cloud/tagoio_http_post/README.rst b/samples/net/cloud/tagoio_http_post/README.rst index dc0f2b9da6c..30778353c50 100644 --- a/samples/net/cloud/tagoio_http_post/README.rst +++ b/samples/net/cloud/tagoio_http_post/README.rst @@ -51,7 +51,7 @@ tagoio-http-client sample application with minimal configuration: .. zephyr-app-commands:: :zephyr-app: samples/net/cloud/tagoio_http_post - :board: [sam4e_xpro | sam_v71_xult | frdm_k64f | nucleo_f767zi] + :board: [sam4e_xpro | sam_v71_xult/samv71q21 | frdm_k64f | nucleo_f767zi] :goals: build flash :compact: @@ -75,7 +75,7 @@ need fill ``CONFIG_TAGOIO_HTTP_WIFI_SSID`` with your wifi network SSID and .. zephyr-app-commands:: :zephyr-app: samples/net/cloud/tagoio_http_post - :board: [sam_v71_xult | frdm_k64f | nucleo_f767zi] + :board: [sam_v71_xult/samv71q21 | frdm_k64f | nucleo_f767zi] :shield: [esp_8266_arduino | inventek_eswifi_arduino_uart] :gen-args: -DEXTRA_CONF_FILE=overlay-wifi.conf :goals: build flash diff --git a/samples/net/gptp/boards/sam_e70_xplained.conf b/samples/net/gptp/boards/sam_e70_xplained_same70q21.conf similarity index 100% rename from samples/net/gptp/boards/sam_e70_xplained.conf rename to samples/net/gptp/boards/sam_e70_xplained_same70q21.conf diff --git a/samples/net/gptp/sample.yaml b/samples/net/gptp/sample.yaml index e65327ef47a..02591c22a6b 100644 --- a/samples/net/gptp/sample.yaml +++ b/samples/net/gptp/sample.yaml @@ -10,14 +10,14 @@ tests: sample.net.gptp: platform_allow: - frdm_k64f - - sam_e70_xplained + - sam_e70_xplained/same70q21 - native_posix - native_posix_64 - native_sim - native_sim_64 - nucleo_f767zi - nucleo_h743zi - - nucleo_h745zi_q_m7 + - nucleo_h745zi_q/stm32h745xx/m7 depends_on: netif integration_platforms: - frdm_k64f diff --git a/samples/net/ipv4_autoconf/boards/sam_e70_xplained.conf b/samples/net/ipv4_autoconf/boards/sam_e70_xplained.conf deleted file mode 100644 index ce81ebf899e..00000000000 --- a/samples/net/ipv4_autoconf/boards/sam_e70_xplained.conf +++ /dev/null @@ -1,6 +0,0 @@ -# sam_e70_xplained board need more buffers, otherwise it fails to build - -CONFIG_NET_PKT_RX_COUNT=20 -CONFIG_NET_PKT_TX_COUNT=20 -CONFIG_NET_BUF_RX_COUNT=30 -CONFIG_NET_BUF_TX_COUNT=30 diff --git a/samples/net/ipv4_autoconf/boards/sam_e70_xplained_same70q21.conf b/samples/net/ipv4_autoconf/boards/sam_e70_xplained_same70q21.conf new file mode 100644 index 00000000000..e89285e418c --- /dev/null +++ b/samples/net/ipv4_autoconf/boards/sam_e70_xplained_same70q21.conf @@ -0,0 +1,6 @@ +# sam_e70_xplained/same70q21 board need more buffers, otherwise it fails to build + +CONFIG_NET_PKT_RX_COUNT=20 +CONFIG_NET_PKT_TX_COUNT=20 +CONFIG_NET_BUF_RX_COUNT=30 +CONFIG_NET_BUF_TX_COUNT=30 diff --git a/samples/net/lwm2m_client/sample.yaml b/samples/net/lwm2m_client/sample.yaml index 9c0cada2c1f..29fccca4416 100644 --- a/samples/net/lwm2m_client/sample.yaml +++ b/samples/net/lwm2m_client/sample.yaml @@ -56,7 +56,7 @@ tests: harness: net extra_args: OVERLAY_CONFIG=overlay-bt.conf platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - disco_l475_iot1 tags: - net @@ -80,7 +80,7 @@ tests: extra_args: SHIELD=wnc_m14a2a platform_allow: - frdm_k64f - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - frdm_k64f tags: diff --git a/samples/net/openthread/coprocessor/README.rst b/samples/net/openthread/coprocessor/README.rst index 9ba9fc62f0d..5fbf49c8368 100644 --- a/samples/net/openthread/coprocessor/README.rst +++ b/samples/net/openthread/coprocessor/README.rst @@ -37,17 +37,17 @@ Build the OpenThread NCP sample application which uses CDC ACM UART device: .. zephyr-app-commands:: :zephyr-app: samples/net/openthread/coprocessor - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :gen-args: -DDTC_OVERLAY_FILE=usb.overlay -DEXTRA_CONF_FILE=overlay-usb-nrf-br.conf :compact: -Example building for the nrf52840dk_nrf52840 for RCP: +Example building for the nrf52840dk/nrf52840 for RCP: .. zephyr-app-commands:: :zephyr-app: samples/net/openthread/coprocessor :host-os: unix - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :conf: "prj.conf overlay-rcp.conf" :goals: run :compact: diff --git a/samples/net/openthread/coprocessor/sample.yaml b/samples/net/openthread/coprocessor/sample.yaml index d8159481aac..bf2f2a55b32 100644 --- a/samples/net/openthread/coprocessor/sample.yaml +++ b/samples/net/openthread/coprocessor/sample.yaml @@ -12,18 +12,18 @@ tests: sample.net.openthread.coprocessor: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52833dk_nrf52833 + - nrf52840dk/nrf52840 + - nrf52833dk/nrf52833 - tlsr9518adk80d integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.net.openthread.coprocessor.usb: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52833dk_nrf52833 + - nrf52840dk/nrf52840 + - nrf52833dk/nrf52833 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: ci_build extra_args: - OVERLAY_CONFIG=overlay-usb-nrf-br.conf @@ -31,9 +31,9 @@ tests: sample.openthread.coprocessor.rcp: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52833dk_nrf52833 + - nrf52840dk/nrf52840 + - nrf52833dk/nrf52833 - tlsr9518adk80d integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_args: OVERLAY_CONFIG=overlay-rcp.conf diff --git a/samples/net/sockets/dumb_http_server/sample.yaml b/samples/net/sockets/dumb_http_server/sample.yaml index 13fd552b8aa..23eee0b0d48 100644 --- a/samples/net/sockets/dumb_http_server/sample.yaml +++ b/samples/net/sockets/dumb_http_server/sample.yaml @@ -9,7 +9,7 @@ common: tags: - net - socket - platform_exclude: intel_adsp_cavs25 + platform_exclude: intel_adsp/cavs25 tests: sample.net.sockets.dumb_http_server: extra_configs: diff --git a/samples/net/sockets/echo_client/README.rst b/samples/net/sockets/echo_client/README.rst index ce9ccf2532b..e142cd8b02f 100644 --- a/samples/net/sockets/echo_client/README.rst +++ b/samples/net/sockets/echo_client/README.rst @@ -60,12 +60,12 @@ Build echo-client sample application like this: :goals: build :compact: -Example building for the nrf52840dk_nrf52840 with OpenThread support: +Example building for the nrf52840dk/nrf52840 with OpenThread support: .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_client :host-os: unix - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :conf: "prj.conf overlay-ot.conf" :goals: run :compact: @@ -75,7 +75,7 @@ Example building for the IEEE 802.15.4 RF2XX transceiver: .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_client :host-os: unix - :board: [atsamr21_xpro | sam4s_xplained | sam_v71_xult] + :board: [samr21_xpro | sam4s_xplained | sam_v71_xult/samv71q21] :gen-args: -DEXTRA_CONF_FILE=overlay-802154.conf :goals: build flash :compact: diff --git a/samples/net/sockets/echo_client/boards/atsamr21_xpro.conf b/samples/net/sockets/echo_client/boards/samr21_xpro.conf similarity index 100% rename from samples/net/sockets/echo_client/boards/atsamr21_xpro.conf rename to samples/net/sockets/echo_client/boards/samr21_xpro.conf diff --git a/samples/net/sockets/echo_client/sample.yaml b/samples/net/sockets/echo_client/sample.yaml index 7c37257e420..008920a33bf 100644 --- a/samples/net/sockets/echo_client/sample.yaml +++ b/samples/net/sockets/echo_client/sample.yaml @@ -13,7 +13,7 @@ tests: platform_allow: - qemu_x86 - frdm_k64f - - sam_e70_xplained + - sam_e70_xplained/same70q21 - qemu_cortex_m3 - frdm_kw41z integration_platforms: @@ -23,7 +23,7 @@ tests: platform_allow: qemu_x86 sample.net.sockets.echo_client.802154.rf2xx: extra_args: OVERLAY_CONFIG="overlay-802154.conf" - platform_allow: atsamr21_xpro + platform_allow: samr21_xpro sample.net.sockets.echo_client.802154.rf2xx.xplained: extra_args: - SHIELD=atmel_rf2xx_xplained @@ -35,33 +35,33 @@ tests: - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - sam4e_xpro - - sam_v71_xult + - sam_v71_xult/samv71q21 integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_client.802154.rf2xx.legacy: extra_args: - SHIELD=atmel_rf2xx_legacy - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - sam4e_xpro - - sam_v71_xult + - sam_v71_xult/samv71q21 integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_client.802154.rf2xx.arduino: extra_args: - SHIELD=atmel_rf2xx_arduino - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - - sam_v71_xult + - sam_v71_xult/samv71q21 - frdm_k64f - nucleo_f767zi integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_client.802154.rf2xx.mikrobus: extra_args: - SHIELD=atmel_rf2xx_mikrobus - OVERLAY_CONFIG="overlay-802154.conf" - platform_allow: lpcxpresso55s69_ns + platform_allow: lpcxpresso55s69/lpc55s69/cpu0/ns sample.net.sockets.echo_client.bt: extra_args: OVERLAY_CONFIG="overlay-bt.conf" platform_allow: qemu_x86 @@ -73,14 +73,14 @@ tests: platform_allow: frdm_k64f sample.net.sockets.echo_client.nrf_802154: extra_args: OVERLAY_CONFIG="overlay-802154.conf" - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 sample.net.sockets.echo_client.nrf_openthread: extra_args: OVERLAY_CONFIG="overlay-ot.conf" slow: true tags: - net - openthread - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC sample.net.sockets.echo_client.b91_802154: extra_args: OVERLAY_CONFIG="overlay-802154.conf" diff --git a/samples/net/sockets/echo_server/README.rst b/samples/net/sockets/echo_server/README.rst index 20ce37e7991..0d87359e7b1 100644 --- a/samples/net/sockets/echo_server/README.rst +++ b/samples/net/sockets/echo_server/README.rst @@ -64,22 +64,22 @@ Build echo-server sample application like this: :goals: build :compact: -Example building for the nrf52840dk_nrf52840 with OpenThread support: +Example building for the nrf52840dk/nrf52840 with OpenThread support: .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_server :host-os: unix - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :conf: "prj.conf overlay-ot.conf" :goals: run :compact: -Example building for the atsamr21_xpro with RF2XX driver support: +Example building for the samr21_xpro with RF2XX driver support: .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_server :host-os: unix - :board: [atsamr21_xpro | sam4e_xpro | sam_v71_xult] + :board: [samr21_xpro | sam4e_xpro | sam_v71_xult/samv71q21] :gen-args: -DEXTRA_CONF_FILE=overlay-802154.conf :goals: build flash :compact: diff --git a/samples/net/sockets/echo_server/boards/atsamr21_xpro.conf b/samples/net/sockets/echo_server/boards/samr21_xpro.conf similarity index 100% rename from samples/net/sockets/echo_server/boards/atsamr21_xpro.conf rename to samples/net/sockets/echo_server/boards/samr21_xpro.conf diff --git a/samples/net/sockets/echo_server/sample.yaml b/samples/net/sockets/echo_server/sample.yaml index 1174797d04a..a04c96fe4a0 100644 --- a/samples/net/sockets/echo_server/sample.yaml +++ b/samples/net/sockets/echo_server/sample.yaml @@ -13,7 +13,7 @@ tests: platform_allow: - qemu_x86 - qemu_x86_64 - - sam_e70_xplained + - sam_e70_xplained/same70q21 - frdm_k64f - qemu_cortex_m3 - frdm_kw41z @@ -36,33 +36,33 @@ tests: - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - sam4e_xpro - - sam_v71_xult + - sam_v71_xult/samv71q21 integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_server.802154.rf2xx.legacy: extra_args: - SHIELD=atmel_rf2xx_legacy - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - sam4e_xpro - - sam_v71_xult + - sam_v71_xult/samv71q21 integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_server.802154.rf2xx.arduino: extra_args: - SHIELD=atmel_rf2xx_arduino - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - - sam_v71_xult + - sam_v71_xult/samv71q21 - frdm_k64f - nucleo_f767zi integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_server.802154.rf2xx.mikrobus: extra_args: - SHIELD=atmel_rf2xx_mikrobus - OVERLAY_CONFIG="overlay-802154.conf" - platform_allow: lpcxpresso55s69_ns + platform_allow: lpcxpresso55s69/lpc55s69/cpu0/ns sample.net.sockets.echo_server.bt: extra_args: OVERLAY_CONFIG="overlay-bt.conf" platform_allow: qemu_x86 @@ -74,7 +74,7 @@ tests: platform_allow: frdm_k64f sample.net.sockets.echo_server.nrf_802154: extra_args: OVERLAY_CONFIG="overlay-802154.conf" - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 sample.net.sockets.echo_server.b91_802154: extra_args: OVERLAY_CONFIG="overlay-802154.conf" platform_allow: tlsr9518adk80d @@ -91,7 +91,7 @@ tests: tags: - net - openthread - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC sample.net.sockets.echo_server.b91_openthread: extra_args: OVERLAY_CONFIG="overlay-ot.conf" @@ -122,7 +122,7 @@ tests: sample.net.sockets.echo_server.smsc911x: extra_args: OVERLAY_CONFIG="overlay-smsc911x.conf" tags: net - platform_allow: mps2_an385 + platform_allow: mps2/an385 sample.net.sockets.echo_server.userspace: extra_args: - CONFIG_USERSPACE=y diff --git a/samples/net/sockets/txtime/README.rst b/samples/net/sockets/txtime/README.rst index 46979ce68bb..d0eb9ad0827 100644 --- a/samples/net/sockets/txtime/README.rst +++ b/samples/net/sockets/txtime/README.rst @@ -11,7 +11,7 @@ This sample is a simple UDP sender/receiver which will set the SO_TXTIME socket option and expects the Ethernet driver to send the data when the TX time is expected. The application requires that the board has PTP clock support. A simulated PTP clock is -provided for qemu_x86 board. Also frdm_k64f and sam_e70_xplained boards +provided for qemu_x86 board. Also frdm_k64f and sam_e70_xplained/same70q21 boards are supported. Other mcux or gmac Ethernet driver based boards should work too. User can control how long the application should wait between packets sent by diff --git a/samples/net/sockets/websocket_client/sample.yaml b/samples/net/sockets/websocket_client/sample.yaml index 41ea3a113e9..a0472b856f9 100644 --- a/samples/net/sockets/websocket_client/sample.yaml +++ b/samples/net/sockets/websocket_client/sample.yaml @@ -12,5 +12,5 @@ sample: name: websocket_client tests: sample.net.sockets.websocket_client: - platform_exclude: intel_adsp_cavs25 + platform_exclude: intel_adsp/cavs25 harness: net diff --git a/samples/net/wifi/sample.yaml b/samples/net/wifi/sample.yaml index a199e23b636..c3bbdc08416 100644 --- a/samples/net/wifi/sample.yaml +++ b/samples/net/wifi/sample.yaml @@ -16,7 +16,7 @@ tests: - cc3220sf_launchxl sample.net.wifi.mikroe_wifi_bt_click: extra_args: SHIELD=mikroe_wifi_bt_click_mikrobus - platform_allow: lpcxpresso55s69_cpu0 + platform_allow: lpcxpresso55s69/lpc55s69/cpu0 sample.net.wifi.esp_8266: extra_args: SHIELD=esp_8266 platform_allow: sam4e_xpro diff --git a/samples/net/wpan_serial/README.rst b/samples/net/wpan_serial/README.rst index 3bcf5dbb4d4..7edaf3b2a97 100644 --- a/samples/net/wpan_serial/README.rst +++ b/samples/net/wpan_serial/README.rst @@ -51,7 +51,7 @@ Building and Running .. zephyr-app-commands:: :zephyr-app: samples/net/wpan_serial - :board: atsamr21_xpro + :board: samr21_xpro :goals: build flash :compact: diff --git a/samples/net/wpan_serial/sample.yaml b/samples/net/wpan_serial/sample.yaml index c9ff33d9a42..ac48bc12789 100644 --- a/samples/net/wpan_serial/sample.yaml +++ b/samples/net/wpan_serial/sample.yaml @@ -9,8 +9,8 @@ common: tests: sample.net.wpan.serial: filter: dt_chosen_enabled("zephyr,ieee802154") - platform_exclude: thingy53_nrf5340_cpuapp_ns raytac_mdbt53_db_40_nrf5340_cpuapp_ns - raytac_mdbt53_db_40_nrf5340_cpuapp + platform_exclude: thingy53/nrf5340/cpuapp/ns raytac_mdbt53_db_40/nrf5340/cpuapp/ns + raytac_mdbt53_db_40/nrf5340/cpuapp sample.net.wpan_serial.frdm_cr20a: extra_args: SHIELD=frdm_cr20a platform_allow: frdm_k64f diff --git a/samples/net/wpanusb/README.rst b/samples/net/wpanusb/README.rst index 27c6c2bae72..4c594d359ea 100644 --- a/samples/net/wpanusb/README.rst +++ b/samples/net/wpanusb/README.rst @@ -17,7 +17,7 @@ Requirements ************ - a Zephyr board with supported 802.15.4 radio and supported USB driver - (such as the :ref:`nrf52840dk_nrf52840` or :ref:`atsamr21_xpro`) + (such as the :ref:`nrf52840dk_nrf52840` or :ref:`samr21_xpro`) connected via USB to a Linux host - wpanusb Linux kernel driver (in the process of being open sourced) - wpan-tools (available for all Linux distributions) @@ -48,7 +48,7 @@ Example building for the Nordic nRF52840 Development Kit: .. zephyr-app-commands:: :zephyr-app: samples/net/wpanusb - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/net/wpanusb/sample.yaml b/samples/net/wpanusb/sample.yaml index bf16524ea72..43371d8c44c 100644 --- a/samples/net/wpanusb/sample.yaml +++ b/samples/net/wpanusb/sample.yaml @@ -9,8 +9,8 @@ common: tests: sample.net.wpanusb: filter: dt_chosen_enabled("zephyr,ieee802154") - platform_exclude: thingy53_nrf5340_cpuapp_ns raytac_mdbt53_db_40_nrf5340_cpuapp_ns - raytac_mdbt53_db_40_nrf5340_cpuapp + platform_exclude: thingy53/nrf5340/cpuapp/ns raytac_mdbt53_db_40/nrf5340/cpuapp/ns + raytac_mdbt53_db_40/nrf5340/cpuapp sample.net.wpanusb_frdm_cr20a: extra_args: SHIELD=frdm_cr20a platform_allow: frdm_k64f diff --git a/samples/net/zperf/boards/mimxrt1170_evk_cm7.conf b/samples/net/zperf/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from samples/net/zperf/boards/mimxrt1170_evk_cm7.conf rename to samples/net/zperf/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/samples/net/zperf/sample.yaml b/samples/net/zperf/sample.yaml index 99b8f50d31a..b3aa90f569f 100644 --- a/samples/net/zperf/sample.yaml +++ b/samples/net/zperf/sample.yaml @@ -6,7 +6,7 @@ common: platform_exclude: - native_posix - native_posix_64 - - sam_e70_xplained + - sam_e70_xplained/same70q21 min_ram: 64 sample: description: Network performance measurement tool for Zephyr @@ -44,7 +44,7 @@ tests: harness: net extra_args: OVERLAY_CONFIG="overlay-usbd_next_ecm.conf" DTC_OVERLAY_FILE="usbd_next_ecm.overlay" - platform_allow: nrf52840dk_nrf52840 frdm_k64f + platform_allow: nrf52840dk/nrf52840 frdm_k64f tags: usb net zperf depends_on: usb_device sample.net.zperf.netusb_eem: @@ -91,5 +91,5 @@ tests: - mimxrt1064_evk - mimxrt1024_evk - frdm_k64f - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 diff --git a/samples/posix/eventfd/sample.yaml b/samples/posix/eventfd/sample.yaml index 8e1e16b4eb7..f4db0db5ae8 100644 --- a/samples/posix/eventfd/sample.yaml +++ b/samples/posix/eventfd/sample.yaml @@ -6,7 +6,7 @@ common: tags: posix platform_exclude: m2gl025_miv integration_platforms: - - mps2_an385 + - mps2/an385 tests: sample.posix.eventfd: min_ram: 32 diff --git a/samples/sensor/accel_polling/sample.yaml b/samples/sensor/accel_polling/sample.yaml index 2b51c2f0e8a..3dac2474dcf 100644 --- a/samples/sensor/accel_polling/sample.yaml +++ b/samples/sensor/accel_polling/sample.yaml @@ -12,16 +12,16 @@ tests: \\(\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*\\)$" integration_platforms: - cc1352r_sensortag # adxl362 - - blueclover_plt_demo_v2_nrf52832 # bmi270 + - blueclover_plt_demo_v2/nrf52832 # bmi270 - frdm_kl25z # mma8451q - lpcxpresso55s28 # mma8652fc - bbc_microbit # mmc8653fc - frdm_k64f # fxos8700 - - sparkfun_thing_plus_nrf9160 # lis2dh - - thingy52_nrf52832 # lis2dh12 + - sparkfun_thing_plus/nrf9160 # lis2dh + - thingy52/nrf52832 # lis2dh12 - stm32f411e_disco # lsm303agr_accel - stm32f3_disco # lsm303dlhc_accel - - bl5340_dvk_cpuapp # lis3dh + - bl5340_dvk/nrf5340/cpuapp # lis3dh - b_l4s5i_iot01a # lsm6dsl - sensortile_box # lis2dw12, lsm6dso, iisdhhc - - thingy53_nrf5340_cpuapp # adxl362, bmi270 + - thingy53/nrf5340/cpuapp # adxl362, bmi270 diff --git a/samples/sensor/adt7420/README.rst b/samples/sensor/adt7420/README.rst index f1620ef0b13..762195bdcef 100644 --- a/samples/sensor/adt7420/README.rst +++ b/samples/sensor/adt7420/README.rst @@ -41,7 +41,7 @@ In this example below the :ref:`nrf52dk_nrf52832` board is used. .. zephyr-app-commands:: :zephyr-app: samples/sensor/adt7420 - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash Sample Output diff --git a/samples/sensor/bme680/README.rst b/samples/sensor/bme680/README.rst index c070cf64f4c..b02cf4fe497 100644 --- a/samples/sensor/bme680/README.rst +++ b/samples/sensor/bme680/README.rst @@ -35,7 +35,7 @@ In this example below the :ref:`nrf52840dk_nrf52840` board is used. .. zephyr-app-commands:: :zephyr-app: samples/sensor/bme680 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash Sample Output diff --git a/samples/sensor/bme680/sample.yaml b/samples/sensor/bme680/sample.yaml index b862d26d80b..4ef00482d72 100644 --- a/samples/sensor/bme680/sample.yaml +++ b/samples/sensor/bme680/sample.yaml @@ -7,7 +7,7 @@ tests: - samples - sensor integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 platform_allow: - - nrf52840dk_nrf52840 - - adafruit_feather_nrf52840 + - nrf52840dk/nrf52840 + - adafruit_feather/nrf52840 diff --git a/samples/sensor/bmi270/README.rst b/samples/sensor/bmi270/README.rst index 056c306dcda..d638549258d 100644 --- a/samples/sensor/bmi270/README.rst +++ b/samples/sensor/bmi270/README.rst @@ -34,7 +34,7 @@ In this example below the :ref:`nrf52840dk_nrf52840` board is used. .. zephyr-app-commands:: :zephyr-app: samples/sensor/bmi270 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash Sample Output diff --git a/samples/sensor/bq274xx/README.rst b/samples/sensor/bq274xx/README.rst index 53e8dc482b7..82ee54b01e8 100644 --- a/samples/sensor/bq274xx/README.rst +++ b/samples/sensor/bq274xx/README.rst @@ -25,7 +25,7 @@ from BQ274XX sensor and prints this information to the UART console. Requirements ************ -- nrf9160_innblue22 board with BQ274XX sensor `BQ274XX Sensor`_ +- innblue22/nrf9160 board with BQ274XX sensor `BQ274XX Sensor`_ Building and Running ******************** @@ -34,7 +34,7 @@ Build this sample using the following commands: .. zephyr-app-commands:: :zephyr-app: samples/sensor/bq274xx - :board: nrf9160_innblue22 + :board: innblue22/nrf9160 :goals: build flash References diff --git a/samples/sensor/bq274xx/sample.yaml b/samples/sensor/bq274xx/sample.yaml index 1912a288b19..8b3020a2536 100644 --- a/samples/sensor/bq274xx/sample.yaml +++ b/samples/sensor/bq274xx/sample.yaml @@ -4,16 +4,16 @@ sample: tests: sample.sensor.bq274xx: harness: sensor - platform_allow: nrf9160_innblue22 + platform_allow: innblue22/nrf9160 integration_platforms: - - nrf9160_innblue22 + - innblue22/nrf9160 tags: sensors depends_on: i2c sample.sensor.bq274xx_without_int_gpios: harness: sensor - platform_allow: nrf9160_innblue22 + platform_allow: innblue22/nrf9160 integration_platforms: - - nrf9160_innblue22 + - innblue22/nrf9160 tags: sensors depends_on: i2c extra_configs: diff --git a/samples/sensor/ccs811/README.rst b/samples/sensor/ccs811/README.rst index 771c50e4eae..38258db5c64 100644 --- a/samples/sensor/ccs811/README.rst +++ b/samples/sensor/ccs811/README.rst @@ -17,12 +17,12 @@ human presence. Building and Running ******************** -Building and Running on thingy52_nrf52832 +Building and Running on thingy52/nrf52832 ========================================= .. zephyr-app-commands:: :zephyr-app: samples/sensor/ccs811 - :board: thingy52_nrf52832 + :board: thingy52/nrf52832 :goals: build flash :compact: @@ -32,7 +32,7 @@ Sample Output The sample output below is from a `Nordic Thingy:52 `_ -(thingy52_nrf52832) that includes this sensor (and others). +(thingy52/nrf52832) that includes this sensor (and others). After a soft reset, there is a 5-second startup period where readings are unstable, and then we can see steady reported measurements of about 400 ppm eC02 and 0 ppb eTVOC. diff --git a/samples/sensor/ccs811/sample.yaml b/samples/sensor/ccs811/sample.yaml index 44540e5aeb6..838eb82b514 100644 --- a/samples/sensor/ccs811/sample.yaml +++ b/samples/sensor/ccs811/sample.yaml @@ -12,7 +12,7 @@ tests: harness: sensor tags: sensors platform_allow: - - thingy52_nrf52832 + - thingy52/nrf52832 - efr32mg_sltb004a integration_platforms: - efr32mg_sltb004a diff --git a/samples/sensor/dht/README.rst b/samples/sensor/dht/README.rst index 20fc3276215..d99a7278e9c 100644 --- a/samples/sensor/dht/README.rst +++ b/samples/sensor/dht/README.rst @@ -24,7 +24,7 @@ build this sample app using: .. zephyr-app-commands:: :zephyr-app: samples/sensor/dht - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash Sample Output diff --git a/samples/sensor/dht/sample.yaml b/samples/sensor/dht/sample.yaml index ad74cb83d9c..bf73aeedd11 100644 --- a/samples/sensor/dht/sample.yaml +++ b/samples/sensor/dht/sample.yaml @@ -11,7 +11,7 @@ sample: tests: sample.sensor.dht: build_only: true - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: sensors diff --git a/samples/sensor/die_temp_polling/boards/nrf51dk_nrf51422.overlay b/samples/sensor/die_temp_polling/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/sensor/die_temp_polling/boards/nrf51dk_nrf51422.overlay rename to samples/sensor/die_temp_polling/boards/nrf51dk_nrf51822.overlay diff --git a/samples/sensor/dps310/README.rst b/samples/sensor/dps310/README.rst index 57ad36d2982..440a43896b6 100644 --- a/samples/sensor/dps310/README.rst +++ b/samples/sensor/dps310/README.rst @@ -18,12 +18,12 @@ This sample application uses an DPS310 sensor connected to a board via I2C. Connect the sensor pins according to the connection diagram given in the `dps310 datasheet`_ at page 18 figure 7. -Build and flash this sample (for example, for the nrf52840dk_nrf52840 board) +Build and flash this sample (for example, for the nrf52840dk/nrf52840 board) using these commands: .. zephyr-app-commands:: :zephyr-app: samples/sensor/dps310 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: flash :compact: diff --git a/samples/sensor/ds18b20/sample.yaml b/samples/sensor/ds18b20/sample.yaml index fb8001758a1..4969db03164 100644 --- a/samples/sensor/ds18b20/sample.yaml +++ b/samples/sensor/ds18b20/sample.yaml @@ -7,10 +7,10 @@ tests: sample.sensor.ds18b20.w1_serial: platform_allow: - nucleo_g0b1re - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - nucleo_g0b1re - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 harness_config: type: one_line regex: diff --git a/samples/sensor/fdc2x1x/README.rst b/samples/sensor/fdc2x1x/README.rst index 5ab5ea6ca1f..626310e6b3f 100644 --- a/samples/sensor/fdc2x1x/README.rst +++ b/samples/sensor/fdc2x1x/README.rst @@ -50,7 +50,7 @@ you can use as a reference for other platforms. .. zephyr-app-commands:: :zephyr-app: samples/sensor/fdc2x1x - :board: nrf9160dk_nrf9160 + :board: nrf9160dk/nrf9160 :goals: build flash :compact: diff --git a/samples/sensor/fdc2x1x/sample.yaml b/samples/sensor/fdc2x1x/sample.yaml index 1cf1e2d8441..e8e61a66466 100644 --- a/samples/sensor/fdc2x1x/sample.yaml +++ b/samples/sensor/fdc2x1x/sample.yaml @@ -5,6 +5,6 @@ tests: sample.sensor.fdc2x1x: harness: sensor tags: sensors - platform_allow: nrf9160dk_nrf9160 + platform_allow: nrf9160dk/nrf9160 integration_platforms: - - nrf9160dk_nrf9160 + - nrf9160dk/nrf9160 diff --git a/samples/sensor/fxas21002/README.rst b/samples/sensor/fxas21002/README.rst index 014a27f12f9..3281e29b830 100644 --- a/samples/sensor/fxas21002/README.rst +++ b/samples/sensor/fxas21002/README.rst @@ -13,12 +13,12 @@ Building and Running ******************** This project outputs sensor data to the console. It requires an fxas21002 -sensor, which is present on the :ref:`hexiwear_k64` board. It does not work on +sensor, which is present on the :ref:`hexiwear` board. It does not work on QEMU. .. zephyr-app-commands:: :zephyr-app: samples/sensor/fxas21002 - :board: hexiwear_k64 + :board: hexiwear/mk64f12 :goals: build :compact: diff --git a/samples/sensor/fxas21002/sample.yaml b/samples/sensor/fxas21002/sample.yaml index 8f598b8f7bc..c43306c3d0b 100644 --- a/samples/sensor/fxas21002/sample.yaml +++ b/samples/sensor/fxas21002/sample.yaml @@ -4,6 +4,6 @@ tests: sample.sensor.fxas21002: harness: sensor tags: sensors - platform_allow: hexiwear_k64 + platform_allow: hexiwear/mk64f12 integration_platforms: - - hexiwear_k64 + - hexiwear/mk64f12 diff --git a/samples/sensor/fxos8700/README.rst b/samples/sensor/fxos8700/README.rst index c6aec0921fc..0c0fa8af66a 100644 --- a/samples/sensor/fxos8700/README.rst +++ b/samples/sensor/fxos8700/README.rst @@ -15,7 +15,7 @@ Building and Running This project outputs sensor data to the console. FXOS8700 sensor is present on the :ref:`frdm_k64f`, :ref:`frdm_k22f`, -:ref:`frdm_kw41z`, :ref:`hexiwear_k64`, and :ref:`twr_ke18f` boards. +:ref:`frdm_kw41z`, :ref:`hexiwear`, and :ref:`twr_ke18f` boards. Accelerometer only devices are present on the :ref:`frdm_kl25z`, :ref:`bbc_microbit`, and :ref:`reel_board` boards. It does not work on QEMU. @@ -117,7 +117,7 @@ Sample can be built and executed for the MIMXRT685-EVK as follows: .. zephyr-app-commands:: :zephyr-app: samples/sensor/fxos8700 - :board: mimxrt685_evk_cm33 + :board: mimxrt685_evk :goals: build flash :compact: @@ -129,7 +129,7 @@ Sample can be built and executed for the MIMXRT595-EVK as follows: .. zephyr-app-commands:: :zephyr-app: samples/sensor/fxos8700 - :board: mimxrt595_evk_cm33 + :board: mimxrt595_evk/mimxrt595s/cm33 :goals: build flash :compact: diff --git a/samples/sensor/fxos8700/boards/mimxrt1170_evk_cm7.conf b/samples/sensor/fxos8700/boards/mimxrt1160_evk_mimxrt1166_cm4.conf similarity index 100% rename from samples/sensor/fxos8700/boards/mimxrt1170_evk_cm7.conf rename to samples/sensor/fxos8700/boards/mimxrt1160_evk_mimxrt1166_cm4.conf diff --git a/samples/sensor/fxos8700/boards/mimxrt1160_evk_mimxrt1166_cm7.conf b/samples/sensor/fxos8700/boards/mimxrt1160_evk_mimxrt1166_cm7.conf new file mode 100644 index 00000000000..16c619082c6 --- /dev/null +++ b/samples/sensor/fxos8700/boards/mimxrt1160_evk_mimxrt1166_cm7.conf @@ -0,0 +1,2 @@ +CONFIG_FXOS8700_TRIGGER_OWN_THREAD=n +CONFIG_FXOS8700_TRIGGER_NONE=y diff --git a/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000..16c619082c6 --- /dev/null +++ b/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,2 @@ +CONFIG_FXOS8700_TRIGGER_OWN_THREAD=n +CONFIG_FXOS8700_TRIGGER_NONE=y diff --git a/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000..16c619082c6 --- /dev/null +++ b/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,2 @@ +CONFIG_FXOS8700_TRIGGER_OWN_THREAD=n +CONFIG_FXOS8700_TRIGGER_NONE=y diff --git a/samples/sensor/fxos8700/sample.yaml b/samples/sensor/fxos8700/sample.yaml index d0e9e27d4db..29215833f63 100644 --- a/samples/sensor/fxos8700/sample.yaml +++ b/samples/sensor/fxos8700/sample.yaml @@ -10,16 +10,16 @@ tests: sample.sensor.fxos8700.hybrid: platform_allow: - frdm_k64f - - hexiwear_k64 - - warp7_m4 + - hexiwear/mk64f12 + - warp7/mcimx7d/m4 - frdm_kw41z - - rv32m1_vega_ri5cy + - rv32m1_vega/openisa_rv32m1/ri5cy - twr_ke18f - lpcxpresso55s16 - - mimxrt685_evk_cm33 + - mimxrt685_evk - frdm_k22f - mimxrt1024_evk - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 integration_platforms: - frdm_k64f extra_configs: @@ -32,10 +32,10 @@ tests: platform_allow: - frdm_kl25z - bbc_microbit - - lpcxpresso55s69_cpu0 + - lpcxpresso55s69/lpc55s69/cpu0 - reel_board - - mimxrt685_evk_cm33 - - mimxrt595_evk_cm33 + - mimxrt685_evk + - mimxrt595_evk/mimxrt595s/cm33 integration_platforms: - bbc_microbit extra_args: CONF_FILE=prj_accel.conf diff --git a/samples/sensor/grove_light/sample.yaml b/samples/sensor/grove_light/sample.yaml index 3eb1083a883..24e020f7fb5 100644 --- a/samples/sensor/grove_light/sample.yaml +++ b/samples/sensor/grove_light/sample.yaml @@ -9,8 +9,8 @@ tests: - sensor - grove - light - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 harness: grove depends_on: adc diff --git a/samples/sensor/grove_temperature/sample.yaml b/samples/sensor/grove_temperature/sample.yaml index 83035b9b9fb..4669a8de56b 100644 --- a/samples/sensor/grove_temperature/sample.yaml +++ b/samples/sensor/grove_temperature/sample.yaml @@ -10,8 +10,8 @@ tests: - sensor - grove - temperature - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 harness: grove depends_on: adc diff --git a/samples/sensor/grow_r502a/README.rst b/samples/sensor/grow_r502a/README.rst index 0b71517bc38..032be38bfff 100644 --- a/samples/sensor/grow_r502a/README.rst +++ b/samples/sensor/grow_r502a/README.rst @@ -42,7 +42,7 @@ build this sample app using: .. zephyr-app-commands:: :zephyr-app: samples/sensor/grow_r502a - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash Sample Output diff --git a/samples/sensor/icm42605/README.rst b/samples/sensor/icm42605/README.rst index a438f0dfbf5..6723a15d0a2 100644 --- a/samples/sensor/icm42605/README.rst +++ b/samples/sensor/icm42605/README.rst @@ -26,7 +26,7 @@ build this sample app using: .. zephyr-app-commands:: :zephyr-app: samples/sensor/icm42605 - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash Sample Output diff --git a/samples/sensor/icm42605/sample.yaml b/samples/sensor/icm42605/sample.yaml index 763a914e6fd..43e49982c45 100644 --- a/samples/sensor/icm42605/sample.yaml +++ b/samples/sensor/icm42605/sample.yaml @@ -9,7 +9,7 @@ sample: tests: sample.sensor.icm42605: build_only: true - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: sensors diff --git a/samples/sensor/isl29035/README.rst b/samples/sensor/isl29035/README.rst index 10acaef6396..675bc1f143c 100644 --- a/samples/sensor/isl29035/README.rst +++ b/samples/sensor/isl29035/README.rst @@ -27,7 +27,7 @@ Building and Running .. zephyr-app-commands:: :zephyr-app: samples/sensor/isl29035 - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build :compact: diff --git a/samples/sensor/isl29035/sample.yaml b/samples/sensor/isl29035/sample.yaml index 8ef21237dba..086e4eec8cf 100644 --- a/samples/sensor/isl29035/sample.yaml +++ b/samples/sensor/isl29035/sample.yaml @@ -4,6 +4,6 @@ tests: sample.sensor.isl29035: tags: sensors depends_on: i2c - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 diff --git a/samples/sensor/lps22hh/README.rst b/samples/sensor/lps22hh/README.rst index ad0e780a076..dc1ca12cd79 100644 --- a/samples/sensor/lps22hh/README.rst +++ b/samples/sensor/lps22hh/README.rst @@ -27,7 +27,7 @@ sensor, which is present on the X-NUCLEO-IKS01A3 shield. .. zephyr-app-commands:: :zephyr-app: samples/sensor/lps22hh - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :shield: x_nucleo_iks01a3 :goals: build :compact: diff --git a/samples/sensor/lps22hh_i3c/README.rst b/samples/sensor/lps22hh_i3c/README.rst index 1f4ff486241..5e8b1d4dff5 100644 --- a/samples/sensor/lps22hh_i3c/README.rst +++ b/samples/sensor/lps22hh_i3c/README.rst @@ -37,20 +37,20 @@ sensor (for example, the one on evaluation board STEVALMKI192-V1). resulting in the sample not being able to communicate with the sensor. -Building on mimxrt685_evk_cm33 board +Building on mimxrt685_evk board ==================================== .. zephyr-app-commands:: :zephyr-app: samples/sensor/lps22hh_i3c :host-os: unix - :board: mimxrt685_evk_cm33 + :board: mimxrt685_evk :goals: build :compact: Board Preparations ================== -mimxrt685_evk_cm33 +mimxrt685_evk ------------------ On the board :ref:`mimxrt685_evk`, the I3C pins are exposed on the J18 diff --git a/samples/sensor/lps22hh_i3c/boards/mimxrt685_evk_cm33.overlay b/samples/sensor/lps22hh_i3c/boards/mimxrt685_evk.overlay similarity index 100% rename from samples/sensor/lps22hh_i3c/boards/mimxrt685_evk_cm33.overlay rename to samples/sensor/lps22hh_i3c/boards/mimxrt685_evk.overlay diff --git a/samples/sensor/lsm6dsl/README.rst b/samples/sensor/lsm6dsl/README.rst index e75cbe773db..0ca5303bd2b 100644 --- a/samples/sensor/lsm6dsl/README.rst +++ b/samples/sensor/lsm6dsl/README.rst @@ -48,13 +48,13 @@ Building on disco_l475_iot1 board :goals: build :compact: -Building on nrf52840dk_nrf52840 board with x-nucleo-iks01a2 shield +Building on nrf52840dk/nrf52840 board with x-nucleo-iks01a2 shield ================================================================== .. zephyr-app-commands:: :zephyr-app: samples/sensor/lsm6dsl :host-os: unix - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: x_nucleo_iks01a2 :goals: build :compact: diff --git a/samples/sensor/lsm6dso_i2c_on_i3c/README.rst b/samples/sensor/lsm6dso_i2c_on_i3c/README.rst index a4e42306d58..872d244364b 100644 --- a/samples/sensor/lsm6dso_i2c_on_i3c/README.rst +++ b/samples/sensor/lsm6dso_i2c_on_i3c/README.rst @@ -28,20 +28,20 @@ Building and Running This project outputs sensor data to the console. It requires an LSM6DSO sensor (for example, the one on evaluation board STEVAL-MKI196V1). -Building on mimxrt685_evk_cm33 board +Building on mimxrt685_evk board ==================================== .. zephyr-app-commands:: :zephyr-app: samples/sensor/lsm6dso_i2c_on_i3c :host-os: unix - :board: mimxrt685_evk_cm33 + :board: mimxrt685_evk :goals: build :compact: Board Preparations ================== -mimxrt685_evk_cm33 +mimxrt685_evk ------------------ On the board :ref:`mimxrt685_evk`, the I3C pins are exposed on the J18 diff --git a/samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk_cm33.overlay b/samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk.overlay similarity index 100% rename from samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk_cm33.overlay rename to samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk.overlay diff --git a/samples/sensor/magn_polling/sample.yaml b/samples/sensor/magn_polling/sample.yaml index 97aa17419f3..8c44c0c74dd 100644 --- a/samples/sensor/magn_polling/sample.yaml +++ b/samples/sensor/magn_polling/sample.yaml @@ -7,7 +7,7 @@ tests: filter: dt_alias_exists("magn0") integration_platforms: - frdm_k64f # fxos8700 - - thingy53_nrf5340_cpuapp # bmm150 + - thingy53/nrf5340/cpuapp # bmm150 - sensortile_box # lis2mdl - stm32f411e_disco # lsm303agr_magn - stm32f3_disco # lsm303dlhc_magn diff --git a/samples/sensor/max17262/README.rst b/samples/sensor/max17262/README.rst index d5403994527..b73b411903f 100644 --- a/samples/sensor/max17262/README.rst +++ b/samples/sensor/max17262/README.rst @@ -32,7 +32,7 @@ Connect the sensor pins according to the connection diagram given in the .. zephyr-app-commands:: :zephyr-app: samples/sensor/max17262 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/sensor/max17262/sample.yaml b/samples/sensor/max17262/sample.yaml index ac403802235..d87c4a5a896 100644 --- a/samples/sensor/max17262/sample.yaml +++ b/samples/sensor/max17262/sample.yaml @@ -7,7 +7,7 @@ tests: depends_on: arduino_i2c harness: console tags: sensors - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 harness_config: type: one_line regex: diff --git a/samples/sensor/max30101/README.rst b/samples/sensor/max30101/README.rst index 446231ef0a3..3d7aa9e8be5 100644 --- a/samples/sensor/max30101/README.rst +++ b/samples/sensor/max30101/README.rst @@ -12,14 +12,14 @@ rate sensor. Building and Running ******************** -This project configures the max30101 sensor on the :ref:`hexiwear_k64` board to +This project configures the max30101 sensor on the :ref:`hexiwear` board to enable the green LED and measure the reflected light with a photodiode. The raw ADC data prints to the console. Further processing (not included in this sample) is required to extract a heart rate signal from the light measurement. .. zephyr-app-commands:: :zephyr-app: samples/sensor/max30101 - :board: hexiwear_k64 + :board: hexiwear/mk64f12 :goals: build :compact: diff --git a/samples/sensor/max30101/boards/hexiwear_k64.overlay b/samples/sensor/max30101/boards/hexiwear_mk64f12.overlay similarity index 100% rename from samples/sensor/max30101/boards/hexiwear_k64.overlay rename to samples/sensor/max30101/boards/hexiwear_mk64f12.overlay diff --git a/samples/sensor/max30101/sample.yaml b/samples/sensor/max30101/sample.yaml index f1d82339432..abe92a10d24 100644 --- a/samples/sensor/max30101/sample.yaml +++ b/samples/sensor/max30101/sample.yaml @@ -5,7 +5,7 @@ tests: sample.sensor.max30101: harness: sensor tags: sensors - platform_allow: hexiwear_k64 + platform_allow: hexiwear/mk64f12 depends_on: i2c integration_platforms: - - hexiwear_k64 + - hexiwear/mk64f12 diff --git a/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_cm7.overlay b/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay similarity index 100% rename from samples/sensor/mcux_acmp/boards/mimxrt1170_evk_cm7.overlay rename to samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay diff --git a/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000..b7aa1131ec7 --- /dev/null +++ b/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,22 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + acmp1_default: acmp1_default { + group0 { + pinmux = <&iomuxc_gpio_ad_01_acmp1_in2>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + }; +}; + +&acmp1 { + status = "okay"; + pinctrl-0 = <&acmp1_default>; + pinctrl-names = "default"; +}; diff --git a/samples/sensor/mcux_acmp/sample.yaml b/samples/sensor/mcux_acmp/sample.yaml index 3f47cfcd1b5..6c4e0bb314f 100644 --- a/samples/sensor/mcux_acmp/sample.yaml +++ b/samples/sensor/mcux_acmp/sample.yaml @@ -4,8 +4,8 @@ sample: common: platform_allow: - twr_ke18f - - mimxrt1170_evk_cm7 - - mimxrt1170_evk_cm4 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1170_evk/mimxrt1176/cm4 integration_platforms: - twr_ke18f tags: diff --git a/samples/sensor/mcux_acmp/src/main.c b/samples/sensor/mcux_acmp/src/main.c index f6960168b8f..a1475d145c0 100644 --- a/samples/sensor/mcux_acmp/src/main.c +++ b/samples/sensor/mcux_acmp/src/main.c @@ -16,7 +16,7 @@ #define ACMP_POSITIVE 5 #define ACMP_NEGATIVE 5 #define ACMP_DAC_VREF 0 -#elif (defined(CONFIG_BOARD_MIMXRT1170_EVK_CM7) || defined(CONFIG_BOARD_MIMXRT1170_EVK_CM4)) +#elif defined(CONFIG_BOARD_MIMXRT1170_EVK) #define ACMP_NODE DT_NODELABEL(acmp1) #define ACMP_POSITIVE 2 #define ACMP_NEGATIVE 7 diff --git a/samples/sensor/mpu6050/README.rst b/samples/sensor/mpu6050/README.rst index 793323f73a2..52550218808 100644 --- a/samples/sensor/mpu6050/README.rst +++ b/samples/sensor/mpu6050/README.rst @@ -28,7 +28,7 @@ build this sample app using: .. zephyr-app-commands:: :zephyr-app: samples/sensor/mpu6050 - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash Sample Output diff --git a/samples/sensor/mpu6050/sample.yaml b/samples/sensor/mpu6050/sample.yaml index 1633dd4b64f..5a9ed1e2803 100644 --- a/samples/sensor/mpu6050/sample.yaml +++ b/samples/sensor/mpu6050/sample.yaml @@ -9,7 +9,7 @@ sample: tests: sample.sensor.mpu6050: build_only: true - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 tags: sensors integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 diff --git a/samples/sensor/ms5837/README.rst b/samples/sensor/ms5837/README.rst index 03bf40dc188..dd1b0a99564 100644 --- a/samples/sensor/ms5837/README.rst +++ b/samples/sensor/ms5837/README.rst @@ -37,7 +37,7 @@ Build this sample using the following commands: .. zephyr-app-commands:: :zephyr-app: samples/sensor/ms5837 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/sensor/ms5837/sample.yaml b/samples/sensor/ms5837/sample.yaml index 59adc486e64..2e3b50a9a57 100644 --- a/samples/sensor/ms5837/sample.yaml +++ b/samples/sensor/ms5837/sample.yaml @@ -4,7 +4,7 @@ sample: tests: sample.sensor.ms5837: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: sensors diff --git a/samples/sensor/proximity_polling/sample.yaml b/samples/sensor/proximity_polling/sample.yaml index 8a5d8bb9307..35ef1647b22 100644 --- a/samples/sensor/proximity_polling/sample.yaml +++ b/samples/sensor/proximity_polling/sample.yaml @@ -8,4 +8,4 @@ tests: - proximity filter: dt_alias_exists("prox-sensor0") integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/samples/sensor/qdec/sample.yaml b/samples/sensor/qdec/sample.yaml index 5849f3e00c7..cbd90ba6f3e 100644 --- a/samples/sensor/qdec/sample.yaml +++ b/samples/sensor/qdec/sample.yaml @@ -18,10 +18,10 @@ tests: fixture: fixture_mech_encoder sample.sensor.nrf_qdec_sensor: platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp harness_config: fixture: gpio_loopback diff --git a/samples/sensor/sensor_shell/boards/tdk_robokit1.conf b/samples/sensor/sensor_shell/boards/robokit1.conf similarity index 100% rename from samples/sensor/sensor_shell/boards/tdk_robokit1.conf rename to samples/sensor/sensor_shell/boards/robokit1.conf diff --git a/samples/sensor/sht3xd/sample.yaml b/samples/sensor/sht3xd/sample.yaml index 5d729754653..0319ba3a7e2 100644 --- a/samples/sensor/sht3xd/sample.yaml +++ b/samples/sensor/sht3xd/sample.yaml @@ -11,10 +11,10 @@ common: - efr32mg_sltb004a - frdm_k64f - nrf51_ble400 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nucleo_l476rg integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: sensors build_only: true tests: diff --git a/samples/sensor/thermometer/README.rst b/samples/sensor/thermometer/README.rst index e37ad7b016b..255425fc22e 100644 --- a/samples/sensor/thermometer/README.rst +++ b/samples/sensor/thermometer/README.rst @@ -18,17 +18,17 @@ VOUT pin connected to the ADC input pin. .. _`MCP970X Sensor`: http://ww1.microchip.com/downloads/en/devicedoc/20001942g.pdf -An overlay is provided for the nrf52840dk_nrf52840 board with the +An overlay is provided for the nrf52840dk/nrf52840 board with the sensor connected to pin AIN7. Building and Running ******************** -To build for the nrf52840dk_nrf52840 board use: +To build for the nrf52840dk/nrf52840 board use: .. zephyr-app-commands:: :zephyr-app: samples/sensor/thermometer - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: @@ -36,7 +36,7 @@ To build for the nrf52840dk_nrf52840 board use: To build for other boards and ambient temperature sensors, enable the sensor node that supports ``SENSOR_CHAN_AMBIENT_TEMP`` and use an overlay to create an alias named ``ambient-temp0`` to link to the node. See the overlay used for the -``nrf52840dk_nrf52840`` board within this sample: +``nrf52840dk/nrf52840`` board within this sample: ``boards/nrf52840dk_nrf52840.overlay`` diff --git a/samples/sensor/thermometer/sample.yaml b/samples/sensor/thermometer/sample.yaml index 64a4de64380..8acb9f72576 100644 --- a/samples/sensor/thermometer/sample.yaml +++ b/samples/sensor/thermometer/sample.yaml @@ -5,5 +5,5 @@ tests: tags: sensors harness: sensor integration_platforms: - - nrf52840dk_nrf52840 - platform_allow: nrf52840dk_nrf52840 frdm_k22f + - nrf52840dk/nrf52840 + platform_allow: nrf52840dk/nrf52840 frdm_k22f diff --git a/samples/shields/npm1300_ek/doc/index.rst b/samples/shields/npm1300_ek/doc/index.rst index f32f301104a..4761ba6f8a2 100644 --- a/samples/shields/npm1300_ek/doc/index.rst +++ b/samples/shields/npm1300_ek/doc/index.rst @@ -28,7 +28,7 @@ building for the nRF52 DK, the following command can be used: .. zephyr-app-commands:: :zephyr-app: samples/shields/npm1300_ek - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build :compact: diff --git a/samples/shields/npm1300_ek/sample.yaml b/samples/shields/npm1300_ek/sample.yaml index 20e16d50238..de89e80d79e 100644 --- a/samples/shields/npm1300_ek/sample.yaml +++ b/samples/shields/npm1300_ek/sample.yaml @@ -5,7 +5,7 @@ sample: name: nPM1300 EK tests: sample.shields.npm1300_ek: - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 harness: shield tags: shield extra_args: SHIELD=npm1300_ek diff --git a/samples/shields/npm6001_ek/doc/index.rst b/samples/shields/npm6001_ek/doc/index.rst index cb3fab7016d..13e4f64ce29 100644 --- a/samples/shields/npm6001_ek/doc/index.rst +++ b/samples/shields/npm6001_ek/doc/index.rst @@ -34,7 +34,7 @@ building for the nRF52840 DK, the following command can be used: .. zephyr-app-commands:: :zephyr-app: samples/shields/npm6001_ek - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/shields/x_nucleo_iks01a2/standard/README.rst b/samples/shields/x_nucleo_iks01a2/standard/README.rst index ccfedc1cfcb..fb0b8af84a8 100644 --- a/samples/shields/x_nucleo_iks01a2/standard/README.rst +++ b/samples/shields/x_nucleo_iks01a2/standard/README.rst @@ -22,8 +22,8 @@ stacked on a board with an Arduino connector. The board's I2C must be configured for the I2C Arduino connector in the devicetree. See for example the :ref:`nucleo_f401re_board` board source code: -- :zephyr_file:`boards/arm/nucleo_f401re/nucleo_f401re.dts` -- :zephyr_file:`boards/arm/nucleo_f401re/arduino_r3_connector.dtsi` +- :zephyr_file:`boards/st/nucleo_f401re/nucleo_f401re.dts` +- :zephyr_file:`boards/st/nucleo_f401re/arduino_r3_connector.dtsi` Please note that this sample can't be used with boards already supporting one of the sensors available on the shield (such as disco_l475_iot1) as zephyr diff --git a/samples/shields/x_nucleo_iks02a1/microphone/README.rst b/samples/shields/x_nucleo_iks02a1/microphone/README.rst index adc6831c81d..ee9a222c79f 100644 --- a/samples/shields/x_nucleo_iks02a1/microphone/README.rst +++ b/samples/shields/x_nucleo_iks02a1/microphone/README.rst @@ -52,11 +52,11 @@ To build the sample you can use following command: building the sample is the I2S output clock frequency configuration. For example, for nucleo_f411re board, we have the following file that configures the I2SPLL and have a dependency on HSE/HSI: - :zephyr_file:`boards/shields/x_nucleo_iks02a1/boards/nucleo_f411re.defconfig` + :zephyr_file:`boards/shields/x_nucleo_iks02a1/boards/nucleo_f411re.overlay` The user is invited to to verify which osci is configured on the used host board defconfig file and calculate the final I2SClk frequency, e.g. - :zephyr_file:`boards/arm/nucleo_f411re/nucleo_f411re.dts` + :zephyr_file:`boards/st/nucleo_f411re/nucleo_f411re.dts` Sample Output diff --git a/samples/shields/x_nucleo_iks02a1/sensorhub/README.rst b/samples/shields/x_nucleo_iks02a1/sensorhub/README.rst index e8b17efc65c..699c63e92eb 100644 --- a/samples/shields/x_nucleo_iks02a1/sensorhub/README.rst +++ b/samples/shields/x_nucleo_iks02a1/sensorhub/README.rst @@ -31,8 +31,8 @@ configured for the I2C Arduino connector (both for pin muxing and devicetree). See for example the :ref:`nucleo_f401re_board` board source code: -- :zephyr_file:`boards/arm/nucleo_f401re/nucleo_f401re.dts` -- :zephyr_file:`boards/arm/nucleo_f401re/pinmux.c` +- :zephyr_file:`boards/st/nucleo_f401re/nucleo_f401re.dts` +- :zephyr_file:`boards/st/nucleo_f401re/pinmux.c` Please note that this sample can't be used with boards already supporting one of the sensors available on the shield (such as disco_l475_iot1) diff --git a/samples/subsys/console/echo/sample.yaml b/samples/subsys/console/echo/sample.yaml index 9e94abe6656..e1fa3f8ac46 100644 --- a/samples/subsys/console/echo/sample.yaml +++ b/samples/subsys/console/echo/sample.yaml @@ -3,7 +3,7 @@ sample: tests: sample.console.echo: integration_platforms: - - mps2_an385 + - mps2/an385 filter: CONFIG_UART_CONSOLE and CONFIG_SERIAL_SUPPORT_INTERRUPT tags: console harness: keyboard diff --git a/samples/subsys/console/getchar/sample.yaml b/samples/subsys/console/getchar/sample.yaml index d7117eea6ab..4a4ffcb5978 100644 --- a/samples/subsys/console/getchar/sample.yaml +++ b/samples/subsys/console/getchar/sample.yaml @@ -3,7 +3,7 @@ sample: tests: sample.console.getchar: integration_platforms: - - mps2_an385 + - mps2/an385 filter: CONFIG_UART_CONSOLE and CONFIG_SERIAL_SUPPORT_INTERRUPT tags: console harness: keyboard diff --git a/samples/subsys/console/getline/sample.yaml b/samples/subsys/console/getline/sample.yaml index 820d6190079..9d7e6b72325 100644 --- a/samples/subsys/console/getline/sample.yaml +++ b/samples/subsys/console/getline/sample.yaml @@ -3,7 +3,7 @@ sample: tests: sample.console.getline: integration_platforms: - - mps2_an385 + - mps2/an385 filter: CONFIG_UART_CONSOLE and CONFIG_SERIAL_SUPPORT_INTERRUPT tags: console harness: keyboard diff --git a/samples/subsys/display/cfb/boards/reel_board_v2.conf b/samples/subsys/display/cfb/boards/reel_board_v2.conf deleted file mode 100644 index 5616bfc48d7..00000000000 --- a/samples/subsys/display/cfb/boards/reel_board_v2.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SPI=y diff --git a/samples/subsys/display/lvgl/README.rst b/samples/subsys/display/lvgl/README.rst index be5eecd9db1..34b58f4c866 100644 --- a/samples/subsys/display/lvgl/README.rst +++ b/samples/subsys/display/lvgl/README.rst @@ -68,7 +68,7 @@ Example building for :ref:`nrf52840dk_nrf52840`: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: adafruit_2_8_tft_touch_v2 :goals: build flash diff --git a/samples/subsys/display/lvgl/boards/mimxrt1170_evk_cm7.conf b/samples/subsys/display/lvgl/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from samples/subsys/display/lvgl/boards/mimxrt1170_evk_cm7.conf rename to samples/subsys/display/lvgl/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/samples/subsys/display/lvgl/sample.yaml b/samples/subsys/display/lvgl/sample.yaml index 3c6e56cdfe1..7d8eb7a3b1b 100644 --- a/samples/subsys/display/lvgl/sample.yaml +++ b/samples/subsys/display/lvgl/sample.yaml @@ -36,12 +36,12 @@ tests: - lvgl extra_args: SHIELD="rk055hdmipi4m" platform_allow: - - mimxrt1170_evk_cm7 - - mimxrt595_evk_cm33 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt595_evk/mimxrt595s/cm33 integration_platforms: - - mimxrt1170_evk_cm7 + - mimxrt1170_evk/mimxrt1176/cm7 sample.subsys.display.lvgl.st_b_lcd40_dsi1_mb1166: - platform_allow: stm32h747i_disco_m7 + platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: SHIELD=st_b_lcd40_dsi1_mb1166 harness: console harness_config: diff --git a/samples/subsys/fs/format/README.rst b/samples/subsys/fs/format/README.rst index 1801af34306..fdcc575ec00 100644 --- a/samples/subsys/fs/format/README.rst +++ b/samples/subsys/fs/format/README.rst @@ -18,7 +18,7 @@ Building and running To run this sample, build it for the desired board and scenario and flash it. -The Flash scenario is supported on the nrf52dk_nrf52832 board. +The Flash scenario is supported on the nrf52dk/nrf52832 board. The RAM disk scenario is supported on the mimxrt1064_evk board. To build the RAM disk sample, the configuration `prj_ram.conf` needs to be used by setting `CONF_FILE=prj_ram.conf`. @@ -26,7 +26,7 @@ The Flash sample for the nrf 52DK board can be build as follow: .. zephyr-app-commands:: :zephyr-app: samples/subsys/fs/format - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash :compact: diff --git a/samples/subsys/fs/format/sample.yaml b/samples/subsys/fs/format/sample.yaml index aafe86f7989..897c95c348e 100644 --- a/samples/subsys/fs/format/sample.yaml +++ b/samples/subsys/fs/format/sample.yaml @@ -5,7 +5,7 @@ tests: platform_allow: - native_posix - native_sim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 build_only: true tags: filesystem sample.filesystem.format.fat_fs: diff --git a/samples/subsys/fs/fs_sample/README.rst b/samples/subsys/fs/fs_sample/README.rst index e53068b92c7..f51d1db9c2c 100644 --- a/samples/subsys/fs/fs_sample/README.rst +++ b/samples/subsys/fs/fs_sample/README.rst @@ -28,20 +28,20 @@ For the FAT FS to work with internal flash, the device needs to support erase pages of size <= 4096 bytes and have at least 64kiB of flash available for FAT FS partition alone. Currently the following boards are supported: -``nrf52840dk_nrf52840`` +``nrf52840dk/nrf52840`` Requirements for setting up FAT FS on external flash **************************************************** This type of configuration requires external flash device to be available on DK board. Currently following boards support the configuration: -``nrf52840dk_nrf52840`` by ``nrf52840dk_nrf52840_qspi`` configuration. +``nrf52840dk/nrf52840`` by ``nrf52840dk_nrf52840_qspi`` configuration. Building and Running FAT samples ******************************** Boards with default configurations, for example ``arduino_mkrzero`` or -``nrf52840dk_nrf52840`` using internal flash can be build using command: +``nrf52840dk/nrf52840`` using internal flash can be build using command: .. zephyr-app-commands:: :zephyr-app: samples/subsys/fs/fs_sample @@ -52,12 +52,12 @@ Boards with default configurations, for example ``arduino_mkrzero`` or Where used example board ``nrf52840_blip`` should be replaced with desired board. In case when some more specific configuration is to be used for a given board, -for example ``nrf52840dk_nrf52840`` with MX25 device over QSPI, configuration +for example ``nrf52840dk/nrf52840`` with MX25 device over QSPI, configuration and DTS overlays need to be also selected. The command would look like this: .. zephyr-app-commands:: :zephyr-app: samples/subsys/fs/fs_sample - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :gen-args: -DEXTRA_CONF_FILE=nrf52840dk_nrf52840_qspi.conf -DDTC_OVERLAY_FILE=nrf52840dk_nrf52840_qspi.overlay :goals: build :compact: @@ -73,7 +73,7 @@ sample lists them out on the debug serial output. Building and Running EXT2 samples ********************************* -Ext2 sample can be build for ``hifive_unmatched`` or ``bl5340_dvk_cpuapp``. Because +Ext2 sample can be build for ``hifive_unmatched`` or ``bl5340_dvk/nrf5340/cpuapp``. Because FAT is default file system for this sample, additional flags must be passed to build the sample. diff --git a/samples/subsys/fs/fs_sample/boards/stm32h747i_disco_m7.conf b/samples/subsys/fs/fs_sample/boards/stm32h747i_disco_stm32h747xx_m7.conf similarity index 100% rename from samples/subsys/fs/fs_sample/boards/stm32h747i_disco_m7.conf rename to samples/subsys/fs/fs_sample/boards/stm32h747i_disco_stm32h747xx_m7.conf diff --git a/samples/subsys/fs/fs_sample/boards/stm32h747i_disco_m7.overlay b/samples/subsys/fs/fs_sample/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from samples/subsys/fs/fs_sample/boards/stm32h747i_disco_m7.overlay rename to samples/subsys/fs/fs_sample/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/samples/subsys/fs/fs_sample/sample.yaml b/samples/subsys/fs/fs_sample/sample.yaml index 58c0cf62361..22d47ca3b26 100644 --- a/samples/subsys/fs/fs_sample/sample.yaml +++ b/samples/subsys/fs/fs_sample/sample.yaml @@ -30,10 +30,10 @@ tests: fixture: fixture_shield_adafruit_2_8_tft_touch_v2 sample.filesystem.fat_fs.nrf52840dk_nrf52840: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 sample.filesystem.fat_fs.nrf52840dk_nrf52840.qspi: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_qspi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_qspi.overlay @@ -46,9 +46,7 @@ tests: simulation_exclude: - renode extra_args: CONF_FILE="prj_ext.conf" - platform_allow: hifive_unmatched bl5340_dvk_cpuapp + platform_allow: hifive_unmatched bl5340_dvk/nrf5340/cpuapp sample.filesystem.fat_fs.stm32h747i_disco_m7_sdmmc: build_only: true - platform_allow: stm32h747i_disco_m7 - extra_args: - - OVERLAY_CONFIG=boards/stm32h747i_disco_m7.conf + platform_allow: stm32h747i_disco/stm32h747xx/m7 diff --git a/samples/subsys/fs/littlefs/README.rst b/samples/subsys/fs/littlefs/README.rst index 40911001dda..69be12cfefe 100644 --- a/samples/subsys/fs/littlefs/README.rst +++ b/samples/subsys/fs/littlefs/README.rst @@ -112,7 +112,7 @@ On this device the file system will be placed in the SOC flash. .. zephyr-app-commands:: :zephyr-app: samples/subsys/fs/littlefs - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/subsys/fs/littlefs/boards/lpcxpresso55s69_cpu0.conf b/samples/subsys/fs/littlefs/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from samples/subsys/fs/littlefs/boards/lpcxpresso55s69_cpu0.conf rename to samples/subsys/fs/littlefs/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay b/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay index 3b06e8e97a3..8cb06841754 100644 --- a/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay +++ b/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay @@ -10,7 +10,7 @@ status = "disabled"; }; -/* The mx25, on nrf52840dk_nrf52840, uses pins for spi0, spi1, spi2 and spi3 +/* The mx25, on nrf52840dk/nrf52840, uses pins for spi0, spi1, spi2 and spi3 * to provide quad-spi feature. In individual specifications each of the spi * notes define own clock source (SCK), but spi2 shares the same clock source * as qspi configuration, which is pin (0,19). That is why spi2 is used here diff --git a/samples/subsys/fs/littlefs/boards/stm32h747i_disco_m7.conf b/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.conf similarity index 100% rename from samples/subsys/fs/littlefs/boards/stm32h747i_disco_m7.conf rename to samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.conf diff --git a/samples/subsys/fs/littlefs/boards/stm32h747i_disco_m7.overlay b/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from samples/subsys/fs/littlefs/boards/stm32h747i_disco_m7.overlay rename to samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/samples/subsys/fs/littlefs/sample.yaml b/samples/subsys/fs/littlefs/sample.yaml index cee42827173..6ba8e33e5a7 100644 --- a/samples/subsys/fs/littlefs/sample.yaml +++ b/samples/subsys/fs/littlefs/sample.yaml @@ -8,35 +8,34 @@ tests: sample.filesystem.littlefs: build_only: true platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - particle_xenon - disco_l475_iot1 - - mimxrt685_evk_cm33 + - mimxrt685_evk - mimxrt1060_evk - mimxrt1064_evk - qemu_x86 - native_posix - native_sim - - mimxrt1160_evk_cm7 - - lpcxpresso55s69_cpu0 + - mimxrt1160_evk/mimxrt1166/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 - mr_canhubk3 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.filesystem.littlefs.nrf52840dk_spi: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_spi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_spi.overlay sample.filesystem.littlefs.nrf52840dk_qspi: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_qspi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_qspi.overlay sample.filesystem.littlefs.stm32h747i_disco_m7_sdmmc: build_only: true - platform_allow: stm32h747i_disco_m7 + platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: - - OVERLAY_CONFIG=boards/stm32h747i_disco_m7.conf - CONF_FILE=prj_blk.conf diff --git a/samples/subsys/input/input_dump/README.rst b/samples/subsys/input/input_dump/README.rst index 0492f02b831..e16649382b2 100644 --- a/samples/subsys/input/input_dump/README.rst +++ b/samples/subsys/input/input_dump/README.rst @@ -17,11 +17,11 @@ The samples works on any board with an input driver defined in the board devicet Building and Running ******************** -Build and flash as follows, changing ``nrf52dk_nrf52832`` for your board: +Build and flash as follows, changing ``nrf52dk/nrf52832`` for your board: .. zephyr-app-commands:: :zephyr-app: samples/subsys/input/input_dump - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash :compact: diff --git a/samples/subsys/ipc/ipc_service/icmsg/CMakeLists.txt b/samples/subsys/ipc/ipc_service/icmsg/CMakeLists.txt index 2d9d62bdf23..215648de38a 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/CMakeLists.txt +++ b/samples/subsys/ipc/ipc_service/icmsg/CMakeLists.txt @@ -8,7 +8,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(NOT ("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp")) +if(NOT ("${BOARD}" STREQUAL "nrf5340dk")) message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/subsys/ipc/ipc_service/icmsg/Kconfig.sysbuild b/samples/subsys/ipc/ipc_service/icmsg/Kconfig.sysbuild index 47884745130..d0849e37dde 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/Kconfig.sysbuild +++ b/samples/subsys/ipc/ipc_service/icmsg/Kconfig.sysbuild @@ -6,4 +6,4 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" diff --git a/samples/subsys/ipc/ipc_service/icmsg/README.rst b/samples/subsys/ipc/ipc_service/icmsg/README.rst index c12c4107075..897fa2503b0 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/README.rst +++ b/samples/subsys/ipc/ipc_service/icmsg/README.rst @@ -11,12 +11,12 @@ This application demonstrates how to use IPC Service and the icmsg backend with Zephyr. It is designed to demonstrate how to integrate it with Zephyr both from a build perspective and code. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/ipc_service/icmsg - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: debug :west-args: --sysbuild diff --git a/samples/subsys/ipc/ipc_service/icmsg/sample.yaml b/samples/subsys/ipc/ipc_service/icmsg/sample.yaml index b54fc7f8962..af1f172d709 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/sample.yaml +++ b/samples/subsys/ipc/ipc_service/icmsg/sample.yaml @@ -2,9 +2,9 @@ sample: name: IPC Service example integration (icmsg backend) tests: sample.ipc.icmsg: - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: ipc sysbuild: true harness: remote diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/CMakeLists.txt b/samples/subsys/ipc/ipc_service/multi_endpoint/CMakeLists.txt index b342f550616..0b8090dd500 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/CMakeLists.txt +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/CMakeLists.txt @@ -8,7 +8,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(NOT ("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp")) +if(NOT ("${BOARD}" STREQUAL "nrf5340dk")) message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/Kconfig.sysbuild b/samples/subsys/ipc/ipc_service/multi_endpoint/Kconfig.sysbuild index 47884745130..d0849e37dde 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/Kconfig.sysbuild +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/Kconfig.sysbuild @@ -6,4 +6,4 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/README.rst b/samples/subsys/ipc/ipc_service/multi_endpoint/README.rst index faff69e007f..c3d0c2019fe 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/README.rst +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/README.rst @@ -7,12 +7,12 @@ This application demonstrates how to use IPC Service with multiple endpoints. By default, it uses the ``icmsg_me`` backend. You can also configure it to use the ``icbmsg`` backend. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/ipc_service/multi_endpoint - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: debug Open a serial terminal (for example Minicom or PuTTY) and connect the board with the following settings: @@ -68,6 +68,6 @@ overlay files as follows: .. code-block:: console - west build -b nrf5340dk_nrf5340_cpuapp --sysbuild -- \ + west build -b nrf5340dk/nrf5340/cpuapp --sysbuild -- \ -DDTC_OVERLAY_FILE=boards/nrf5340dk_nrf5340_cpuapp_icbmsg.overlay \ -Dremote_DTC_OVERLAY_FILE=boards/nrf5340dk_nrf5340_cpunet_icbmsg.overlay diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/sample.yaml b/samples/subsys/ipc/ipc_service/multi_endpoint/sample.yaml index fdb3c707d8e..401bbf51735 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/sample.yaml +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/sample.yaml @@ -2,16 +2,16 @@ sample: name: IPC Service example integration (icmsg multi endpoint backend) tests: sample.ipc.multi_endpoint: - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: ipc sysbuild: true harness: remote sample.ipc.multi_endpoint.icbmsg: - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: ipc sysbuild: true extra_args: diff --git a/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt b/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt index 6af69691e1e..eb26f752c96 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt +++ b/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt @@ -8,7 +8,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(NOT ("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp")) +if(NOT ("${BOARD}" STREQUAL "nrf5340dk")) message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild b/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild index 47884745130..d0849e37dde 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild +++ b/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild @@ -6,4 +6,4 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" diff --git a/samples/subsys/ipc/ipc_service/static_vrings/README.rst b/samples/subsys/ipc/ipc_service/static_vrings/README.rst index 7fbed84cad8..97cd8c823b2 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/README.rst +++ b/samples/subsys/ipc/ipc_service/static_vrings/README.rst @@ -11,12 +11,12 @@ This application demonstrates how to use IPC Service and the static vrings backend with Zephyr. It is designed to demonstrate how to integrate it with Zephyr both from a build perspective and code. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/ipc_service/static_vrings - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: debug :west-args: --sysbuild diff --git a/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml b/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml index 3e57abf32eb..f776f90adb9 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml +++ b/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml @@ -2,9 +2,9 @@ sample: name: IPC Service example integration (OpenAMP static_vrings backend) tests: sample.ipc.static_vrings: - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: ipc sysbuild: true harness: remote diff --git a/samples/subsys/ipc/openamp/Kconfig.sysbuild b/samples/subsys/ipc/openamp/Kconfig.sysbuild index 7a7963ad16f..9063dacafa1 100644 --- a/samples/subsys/ipc/openamp/Kconfig.sysbuild +++ b/samples/subsys/ipc/openamp/Kconfig.sysbuild @@ -6,10 +6,10 @@ source "share/sysbuild/Kconfig" config OPENAMP_REMOTE_BOARD string - default "lpcxpresso54114_m0" if $(BOARD) = "lpcxpresso54114_m4" - default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" - default "mps2_an521_remote" if $(BOARD) = "mps2_an521" - default "v2m_musca_b1_ns" if $(BOARD) = "v2m_musca_b1" - default "mimxrt1170_evk_cm4" if $(BOARD) = "mimxrt1170_evk_cm7" - default "mimxrt1160_evk_cm4" if $(BOARD) = "mimxrt1160_evk_cm7" - default "mimxrt1170_evkb_cm4" if $(BOARD) = "mimxrt1170_evkb_cm7" + default "lpcxpresso54114/lpc54114/m0" if $(BOARD) = "lpcxpresso54114" + default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" + default "mps2/an521/cpu1" if $(BOARD) = "mps2" + default "v2m_musca_b1/musca_b1/ns" if $(BOARD) = "v2m_musca_b1" + default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" + default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" + default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb" diff --git a/samples/subsys/ipc/openamp/README.rst b/samples/subsys/ipc/openamp/README.rst index 1ad79dff354..a75ef69017d 100644 --- a/samples/subsys/ipc/openamp/README.rst +++ b/samples/subsys/ipc/openamp/README.rst @@ -17,34 +17,34 @@ Building the application for lpcxpresso54114_m4 .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp - :board: lpcxpresso54114_m4 + :board: lpcxpresso54114/lpc54114/m4 :goals: debug :west-args: --sysbuild -Building the application for lpcxpresso55s69_cpu0 -************************************************* +Building the application for lpcxpresso55s69/lpc55s69/cpu0 +********************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp - :board: lpcxpresso55s69_cpu0 + :board: lpcxpresso55s69/lpc55s69/cpu0 :goals: debug :west-args: --sysbuild -Building the application for mps2_an521 -*************************************** +Building the application for mps2/an521/cpu0 +******************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp - :board: mps2_an521 + :board: mps2/an521/cpu0 :goals: debug :west-args: --sysbuild -Building the application for v2m_musca_b1 -***************************************** +Building the application for v2m_musca_b1/musca_b1 +************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp - :board: v2m_musca_b1 + :board: v2m_musca_b1/musca_b1 :goals: debug :west-args: --sysbuild diff --git a/samples/subsys/ipc/openamp/boards/lpcxpresso54114_m4.conf b/samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.conf similarity index 100% rename from samples/subsys/ipc/openamp/boards/lpcxpresso54114_m4.conf rename to samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.conf diff --git a/samples/subsys/ipc/openamp/boards/lpcxpresso54114_m4.overlay b/samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.overlay similarity index 100% rename from samples/subsys/ipc/openamp/boards/lpcxpresso54114_m4.overlay rename to samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.overlay diff --git a/samples/subsys/ipc/openamp/boards/lpcxpresso55s69_cpu0.conf b/samples/subsys/ipc/openamp/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from samples/subsys/ipc/openamp/boards/lpcxpresso55s69_cpu0.conf rename to samples/subsys/ipc/openamp/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/samples/subsys/ipc/openamp/boards/lpcxpresso55s69_cpu0.overlay b/samples/subsys/ipc/openamp/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from samples/subsys/ipc/openamp/boards/lpcxpresso55s69_cpu0.overlay rename to samples/subsys/ipc/openamp/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.conf b/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.conf similarity index 100% rename from samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.conf rename to samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.conf diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.overlay rename to samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000..630a1933d62 --- /dev/null +++ b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,2 @@ +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000..7facea692cb --- /dev/null +++ b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + chosen { + zephyr,ipc_shm = &ocram2_overlay; + }; + + /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory. + * Define a subset of the OCRAM2 region for demo to use + * Note that shared memory must have specific MPU attributes set. + */ + ocram2_overlay: memory@202c0000{ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x202c0000 DT_SIZE_K(16)>; + zephyr,memory-region="OCRAM2_OVERLAY"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; +}; diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000..ae8dba8cc21 --- /dev/null +++ b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,7 @@ +# +# Copyright 2023, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evkb_cm7.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from samples/subsys/ipc/openamp/boards/mimxrt1170_evkb_cm7.overlay rename to samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_m0.conf b/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.conf similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_m0.conf rename to samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.conf diff --git a/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_m0.overlay b/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.overlay similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_m0.overlay rename to samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.overlay diff --git a/samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_cpu1.conf b/samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_cpu1.conf rename to samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf diff --git a/samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_cpu1.overlay b/samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_cpu1.overlay rename to samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000..4dfc4a60b76 --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,3 @@ +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000..87159192cf2 --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,51 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + /* Switch to lpuart2, since primary core uses lpuart1 */ + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + zephyr,ipc_shm = &ocram2_overlay; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + }; + + /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory. + * Define a subset of the OCRAM2 region for demo to use + * Note that shared memory must have specific MPU attributes set + */ + ocram2_overlay: memory@202c0000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x202c0000 DT_SIZE_K(16)>; + zephyr,memory-region="OCRAM2_OVERLAY"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000..4dfc4a60b76 --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,3 @@ +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000..87159192cf2 --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,51 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + /* Switch to lpuart2, since primary core uses lpuart1 */ + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + zephyr,ipc_shm = &ocram2_overlay; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + }; + + /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory. + * Define a subset of the OCRAM2 region for demo to use + * Note that shared memory must have specific MPU attributes set + */ + ocram2_overlay: memory@202c0000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x202c0000 DT_SIZE_K(16)>; + zephyr,memory-region="OCRAM2_OVERLAY"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000..7b43b448c72 --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,8 @@ +# +# Copyright 2023, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000..72510d26166 --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,49 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + /* Switch to lpuart2, since primary core uses lpuart1 */ + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + zephyr,ipc_shm = &ocram2_overlay; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + }; + + /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory. + * Define a subset of the OCRAM2 region for demo to use + * Note that shared memory must have specific MPU attributes set + */ + ocram2_overlay: memory@202c0000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x202c0000 DT_SIZE_K(16)>; + zephyr,memory-region="OCRAM2_OVERLAY"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/subsys/ipc/openamp/remote/boards/mps2_an521_remote.overlay b/samples/subsys/ipc/openamp/remote/boards/mps2_an521_cpu1.overlay similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/mps2_an521_remote.overlay rename to samples/subsys/ipc/openamp/remote/boards/mps2_an521_cpu1.overlay diff --git a/samples/subsys/ipc/openamp/remote/boards/v2m_musca_b1_ns.overlay b/samples/subsys/ipc/openamp/remote/boards/v2m_musca_b1_musca_b1_ns.overlay similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/v2m_musca_b1_ns.overlay rename to samples/subsys/ipc/openamp/remote/boards/v2m_musca_b1_musca_b1_ns.overlay diff --git a/samples/subsys/ipc/openamp/remote/sample.yaml b/samples/subsys/ipc/openamp/remote/sample.yaml index 60a8d38681d..906449cfdc3 100644 --- a/samples/subsys/ipc/openamp/remote/sample.yaml +++ b/samples/subsys/ipc/openamp/remote/sample.yaml @@ -4,9 +4,9 @@ sample: tests: sample.ipc.openamp.remote: platform_allow: - - lpcxpresso54114_m0 - - lpcxpresso55s69_cpu1 + - lpcxpresso54114/lpc54114/m0 + - lpcxpresso55s69/lpc55s69/cpu1 integration_platforms: - - lpcxpresso54114_m0 + - lpcxpresso54114/lpc54114/m0 tags: ipm harness: remote diff --git a/samples/subsys/ipc/openamp/sample.yaml b/samples/subsys/ipc/openamp/sample.yaml index 7a6635f72b4..63268230d9b 100644 --- a/samples/subsys/ipc/openamp/sample.yaml +++ b/samples/subsys/ipc/openamp/sample.yaml @@ -4,12 +4,12 @@ sample: tests: sample.ipc.openamp: platform_allow: - - lpcxpresso54114_m4 - - lpcxpresso55s69_cpu0 - - mps2_an521 - - v2m_musca_b1 + - lpcxpresso54114/lpc54114/m4 + - lpcxpresso55s69/lpc55s69/cpu0 + - mps2/an521/cpu0 + - v2m_musca_b1/musca_b1 integration_platforms: - - mps2_an521 + - mps2/an521/cpu0 tags: ipm harness: console sysbuild: true diff --git a/samples/subsys/ipc/openamp_rsc_table/boards/nxp_adsp_imx8m.conf b/samples/subsys/ipc/openamp_rsc_table/boards/imx8mp_evk_mimx8ml8_adsp.conf similarity index 100% rename from samples/subsys/ipc/openamp_rsc_table/boards/nxp_adsp_imx8m.conf rename to samples/subsys/ipc/openamp_rsc_table/boards/imx8mp_evk_mimx8ml8_adsp.conf diff --git a/samples/subsys/ipc/openamp_rsc_table/boards/nxp_adsp_imx8m.overlay b/samples/subsys/ipc/openamp_rsc_table/boards/imx8mp_evk_mimx8ml8_adsp.overlay similarity index 100% rename from samples/subsys/ipc/openamp_rsc_table/boards/nxp_adsp_imx8m.overlay rename to samples/subsys/ipc/openamp_rsc_table/boards/imx8mp_evk_mimx8ml8_adsp.overlay diff --git a/samples/subsys/ipc/openamp_rsc_table/sample.yaml b/samples/subsys/ipc/openamp_rsc_table/sample.yaml index 3c9d58d3202..d1c94c10585 100644 --- a/samples/subsys/ipc/openamp_rsc_table/sample.yaml +++ b/samples/subsys/ipc/openamp_rsc_table/sample.yaml @@ -7,8 +7,8 @@ tests: build_only: true platform_allow: - stm32mp157c_dk2 - - nxp_adsp_imx8m + - imx8mp_evk/mimx8ml8/adsp integration_platforms: - stm32mp157c_dk2 - - nxp_adsp_imx8m + - imx8mp_evk/mimx8ml8/adsp tags: ipm diff --git a/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild b/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild index 9dec2087f95..9af87af157f 100644 --- a/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild +++ b/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild @@ -5,10 +5,10 @@ source "share/sysbuild/Kconfig" config RPMSG_REMOTE_BOARD -string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "bl5340_dvk_cpunet" if $(BOARD) = "bl5340_dvk_cpuapp" - default "lpcxpresso54114_m0" if $(BOARD) = "lpcxpresso54114_m4" + string + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" + default "bl5340_dvk/nrf5340/cpunet" if $(BOARD) = "bl5340_dvk" + default "lpcxpresso54114/lpc54114/m0" if $(BOARD) = "lpcxpresso54114" default "mps2_an521_remote" if $(BOARD) = "mps2_an521" default "v2m_musca_b1_ns" if $(BOARD) = "v2m_musca_b1" default "esp32_devkitc_wroom_appcpu" if $(BOARD) = "esp32_devkitc_wroom" diff --git a/samples/subsys/ipc/rpmsg_service/README.rst b/samples/subsys/ipc/rpmsg_service/README.rst index 0c63b8dc3bb..6ff5a61be80 100644 --- a/samples/subsys/ipc/rpmsg_service/README.rst +++ b/samples/subsys/ipc/rpmsg_service/README.rst @@ -15,28 +15,28 @@ perspective and code. Note that the remote and primary image core images can be flashed independently, but sysbuild must be used in order to flash them in one step. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/rpmsg_service - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: debug -Building the application for mps2_an521 -*************************************** +Building the application for mps2/an521/cpu0 +******************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/rpmsg_service - :board: mps2_an521 + :board: mps2/an521/cpu0 :goals: debug -Building the application for v2m_musca_b1 -***************************************** +Building the application for v2m_musca_b1/musca_b1 +************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/rpmsg_service - :board: v2m_musca_b1 + :board: v2m_musca_b1/musca_b1 :goals: debug Open a serial terminal (minicom, putty, etc.) and connect the board with the @@ -77,17 +77,17 @@ serial port, one is master another is remote: Remote core received a message: 98 RPMsg Service demo ended. -Building the application for bl5340_dvk_cpuapp -********************************************** +Building the application for bl5340_dvk/nrf5340/cpuapp +****************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/rpmsg_service - :board: bl5340_dvk_cpuapp + :board: bl5340_dvk/nrf5340/cpuapp :goals: debug .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/rpmsg_service - :board: bl5340_dvk_cpunet + :board: bl5340_dvk/nrf5340/cpunet :goals: debug Open a serial terminal (for example Minicom or PuTTY) and connect to the board diff --git a/samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_cpuapp.conf b/samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_nrf5340_cpuapp.conf similarity index 100% rename from samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_cpuapp.conf rename to samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_nrf5340_cpuapp.conf diff --git a/samples/subsys/ipc/rpmsg_service/remote/boards/mps2_an521_remote.overlay b/samples/subsys/ipc/rpmsg_service/remote/boards/mps2_an521_cpu1.overlay similarity index 100% rename from samples/subsys/ipc/rpmsg_service/remote/boards/mps2_an521_remote.overlay rename to samples/subsys/ipc/rpmsg_service/remote/boards/mps2_an521_cpu1.overlay diff --git a/samples/subsys/ipc/rpmsg_service/remote/boards/v2m_musca_b1_ns.overlay b/samples/subsys/ipc/rpmsg_service/remote/boards/v2m_musca_b1_musca_b1_ns.overlay similarity index 100% rename from samples/subsys/ipc/rpmsg_service/remote/boards/v2m_musca_b1_ns.overlay rename to samples/subsys/ipc/rpmsg_service/remote/boards/v2m_musca_b1_musca_b1_ns.overlay diff --git a/samples/subsys/llext/shell_loader/README.rst b/samples/subsys/llext/shell_loader/README.rst index 583299028be..5062222ff2b 100644 --- a/samples/subsys/llext/shell_loader/README.rst +++ b/samples/subsys/llext/shell_loader/README.rst @@ -20,7 +20,7 @@ Building .. zephyr-app-commands:: :zephyr-app: samples/subsys/llext/shell_loader - :board: tdk_robokit1 + :board: robokit1 :goals: build :compact: diff --git a/samples/subsys/llext/shell_loader/sample.yaml b/samples/subsys/llext/shell_loader/sample.yaml index 3cf54e45020..2af28551af5 100644 --- a/samples/subsys/llext/shell_loader/sample.yaml +++ b/samples/subsys/llext/shell_loader/sample.yaml @@ -3,9 +3,9 @@ common: arch_allow: - arm - xtensa - filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE_R52 + filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE platform_exclude: - - nuvoton_pfm_m487 # See #63167 + - numaker_pfm_m487 # See #63167 sample: description: Loadable extensions with shell sample name: Extension loader shell diff --git a/samples/subsys/logging/dictionary/sample.yaml b/samples/subsys/logging/dictionary/sample.yaml index a135f70df2f..6bbe7622c0e 100644 --- a/samples/subsys/logging/dictionary/sample.yaml +++ b/samples/subsys/logging/dictionary/sample.yaml @@ -30,9 +30,9 @@ tests: sample.logger.basic.dictionary.uart_async_frontend: build_only: true tags: logging - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_LOG_BACKEND_UART=n - CONFIG_LOG_BACKEND_RTT=n @@ -44,9 +44,9 @@ tests: sample.logger.basic.dictionary.uart_frontend_rt: build_only: true tags: logging - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp extra_configs: - CONFIG_SHELL=y - CONFIG_LOG_RUNTIME_FILTERING=y diff --git a/samples/subsys/logging/logger/sample.yaml b/samples/subsys/logging/logger/sample.yaml index 8ef962daeb9..3d822076685 100644 --- a/samples/subsys/logging/logger/sample.yaml +++ b/samples/subsys/logging/logger/sample.yaml @@ -31,7 +31,7 @@ tests: sample.logger.usermode: integration_platforms: - - mps2_an385 + - mps2/an385 platform_exclude: - ip_k66f - bl652_dvk diff --git a/samples/subsys/logging/multidomain/CMakeLists.txt b/samples/subsys/logging/multidomain/CMakeLists.txt index a0cc842a6a8..d800a86fac2 100644 --- a/samples/subsys/logging/multidomain/CMakeLists.txt +++ b/samples/subsys/logging/multidomain/CMakeLists.txt @@ -8,7 +8,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(NOT(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp") +if(NOT(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpuapp"))) message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/subsys/logging/multidomain/Kconfig.sysbuild b/samples/subsys/logging/multidomain/Kconfig.sysbuild index b6dc3d0a6d0..e6d2ccd9930 100644 --- a/samples/subsys/logging/multidomain/Kconfig.sysbuild +++ b/samples/subsys/logging/multidomain/Kconfig.sysbuild @@ -6,5 +6,5 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" diff --git a/samples/subsys/logging/multidomain/sample.yaml b/samples/subsys/logging/multidomain/sample.yaml index 79523c9951a..9d0075017fa 100644 --- a/samples/subsys/logging/multidomain/sample.yaml +++ b/samples/subsys/logging/multidomain/sample.yaml @@ -6,9 +6,9 @@ common: tests: sample.logging.multidomain.ipc_static_vrings.hw: platform_allow: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp build_only: true sample.logging.multidomain.ipc_static_vrings.simu: platform_allow: diff --git a/samples/subsys/logging/syst/sample.yaml b/samples/subsys/logging/syst/sample.yaml index 4501d5740e3..8c4681c4fe8 100644 --- a/samples/subsys/logging/syst/sample.yaml +++ b/samples/subsys/logging/syst/sample.yaml @@ -15,7 +15,7 @@ tests: sample.logger.syst.deferred: toolchain_exclude: xcc integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 extra_args: OVERLAY_CONFIG=overlay_deferred.conf harness: console @@ -38,7 +38,7 @@ tests: extra_args: OVERLAY_CONFIG=overlay_immediate.conf integration_platforms: - qemu_x86 - - sam_e70_xplained + - sam_e70_xplained/same70q21 harness: console harness_config: type: multi_line @@ -95,7 +95,7 @@ tests: sample.logger.syst.immediate_cpp: toolchain_exclude: xcc integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 harness: console harness_config: diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/README.rst b/samples/subsys/mgmt/mcumgr/smp_svr/README.rst index c24103815af..ce5cd64561d 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/README.rst +++ b/samples/subsys/mgmt/mcumgr/smp_svr/README.rst @@ -90,7 +90,7 @@ Zephyr. The ``smp_svr`` sample comes in different flavours. .. code-block:: console west build \ - -b nrf52dk_nrf52832 \ + -b nrf52dk/nrf52832 \ samples/subsys/mgmt/mcumgr/smp_svr \ -- \ -DEXTRA_CONF_FILE=overlay-bt.conf @@ -114,7 +114,7 @@ Zephyr. The ``smp_svr`` sample comes in different flavours. .. code-block:: console west build \ - -b nrf52840dk_nrf52840 \ + -b nrf52840dk/nrf52840 \ samples/subsys/mgmt/mcumgr/smp_svr \ -- \ -DEXTRA_CONF_FILE=overlay-cdc.conf \ diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml index a13270e5845..007179b2f80 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml +++ b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml @@ -8,13 +8,13 @@ tests: sample.mcumgr.smp_svr.bt: extra_args: OVERLAY_CONFIG="overlay-bt.conf" platform_allow: - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 sample.mcumgr.smp_svr.udp: extra_args: OVERLAY_CONFIG="overlay-udp.conf" platform_allow: frdm_k64f @@ -25,24 +25,24 @@ tests: - OVERLAY_CONFIG="overlay-cdc.conf" - DTC_OVERLAY_FILE="usb.overlay" platform_allow: - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp - pinnacle_100_dvk integration_platforms: - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp sample.mcumgr.smp_svr.serial: extra_args: OVERLAY_CONFIG="overlay-serial.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 # In mcuboot_flags test overlay-serial.conf is used for convenience as it is the simplest # transport. Transport does not affect flags so it does not really matter which is selected, # flags should affect any transport the same way. @@ -51,44 +51,44 @@ tests: extra_configs: - CONFIG_MCUBOOT_BOOTLOADER_MODE_DIRECT_XIP_WITH_REVERT=y platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.mcumgr.smp_svr.serial-console: extra_args: OVERLAY_CONFIG="overlay-serial-console.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.mcumgr.smp_svr.shell: extra_args: OVERLAY_CONFIG="overlay-shell.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - mimxrt1060_evk - mimxrt1064_evk - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - mimxrt1060_evk - mimxrt1064_evk sample.mcumgr.smp_svr.shell_mgmt: extra_args: OVERLAY_CONFIG="overlay-shell-mgmt.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.mcumgr.smp_svr.fs: extra_args: OVERLAY_CONFIG="overlay-fs.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/samples/subsys/mgmt/osdp/control_panel/sample.yaml b/samples/subsys/mgmt/osdp/control_panel/sample.yaml index 5fecf6ad24a..d527c7a7d15 100644 --- a/samples/subsys/mgmt/osdp/control_panel/sample.yaml +++ b/samples/subsys/mgmt/osdp/control_panel/sample.yaml @@ -8,7 +8,8 @@ common: dt_chosen_enabled("zephyr,osdp-uart") and CONFIG_SERIAL harness: osdp integration_platforms: - - stm32_min_dev_black + - stm32_min_dev@black + - stm32_min_dev@blue tests: sample.mgmt.osdp.control_panel: extra_args: CONF_FILE=prj.conf diff --git a/samples/subsys/mgmt/osdp/peripheral_device/sample.yaml b/samples/subsys/mgmt/osdp/peripheral_device/sample.yaml index 994ea535e3f..724f468a2ae 100644 --- a/samples/subsys/mgmt/osdp/peripheral_device/sample.yaml +++ b/samples/subsys/mgmt/osdp/peripheral_device/sample.yaml @@ -8,7 +8,8 @@ common: dt_chosen_enabled("zephyr,osdp-uart") and CONFIG_SERIAL harness: osdp integration_platforms: - - stm32_min_dev_black + - stm32_min_dev@black + - stm32_min_dev@blue tests: sample.mgmt.osdp.peripheral_device: extra_args: CONF_FILE=prj.conf diff --git a/samples/subsys/mgmt/updatehub/README.rst b/samples/subsys/mgmt/updatehub/README.rst index ad29354146e..f502e1a1795 100644 --- a/samples/subsys/mgmt/updatehub/README.rst +++ b/samples/subsys/mgmt/updatehub/README.rst @@ -188,7 +188,7 @@ for details. .. zephyr-app-commands:: :zephyr-app: zephyr/samples/subsys/mgmt/updatehub - :board: [ frdm_k64f | nrf52840dk_nrf52840 | nucleo_f767zi ] + :board: [ frdm_k64f | nrf52840dk/nrf52840 | nucleo_f767zi ] :build-dir: app :gen-args: -DEXTRA_CONF_FILE="overlay-wifi.conf;overlay-prj.conf" :shield: esp_8266_arduino @@ -208,7 +208,7 @@ uses PPP over GSM modem, see :zephyr:code-sample:`gsm-modem` sample application. .. zephyr-app-commands:: :zephyr-app: zephyr/samples/subsys/mgmt/updatehub - :board: [ frdm_k64f | nrf52840dk_nrf52840 | nucleo_f767zi ] + :board: [ frdm_k64f | nrf52840dk/nrf52840 | nucleo_f767zi ] :build-dir: app :gen-args: -DEXTRA_CONF_FILE="overlay-modem.conf;overlay-prj.conf" \ -DDTC_OVERLAY_FILE=arduino.overlay @@ -227,7 +227,7 @@ tested with both native linux driver and ``atusb`` and with ``wpanusb`` sample. .. zephyr-app-commands:: :zephyr-app: zephyr/samples/subsys/mgmt/updatehub - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :build-dir: app :gen-args: -DEXTRA_CONF_FILE="overlay-802154.conf;overlay-prj.conf" :goals: build @@ -255,7 +255,7 @@ tested with native linux driver and an USB dongle. .. zephyr-app-commands:: :zephyr-app: zephyr/samples/subsys/mgmt/updatehub - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :build-dir: app :gen-args: -DEXTRA_CONF_FILE="overlay-ipsp.conf;overlay-prj.conf" :goals: build @@ -273,7 +273,7 @@ gateway was tested using two boards with OpenThread 1.1.1 on NCP mode. .. zephyr-app-commands:: :zephyr-app: zephyr/samples/subsys/mgmt/updatehub - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :build-dir: app :gen-args: -DEXTRA_CONF_FILE="overlay-ot.conf;overlay-prj.conf" :goals: build diff --git a/samples/subsys/modbus/rtu_client/sample.yaml b/samples/subsys/modbus/rtu_client/sample.yaml index 0ff16e34204..006e76f9702 100644 --- a/samples/subsys/modbus/rtu_client/sample.yaml +++ b/samples/subsys/modbus/rtu_client/sample.yaml @@ -4,10 +4,10 @@ tests: sample.modbus.rtu_client: build_only: true platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - uart - modbus diff --git a/samples/subsys/modbus/rtu_server/README.rst b/samples/subsys/modbus/rtu_server/README.rst index 289aa73ea7b..aae880b7865 100644 --- a/samples/subsys/modbus/rtu_server/README.rst +++ b/samples/subsys/modbus/rtu_server/README.rst @@ -58,7 +58,7 @@ The following commands build and flash RTU server sample. .. zephyr-app-commands:: :zephyr-app: samples/subsys/modbus/rtu_server - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: @@ -66,7 +66,7 @@ The following commands build and flash RTU server sample using CDC ACM UART. .. zephyr-app-commands:: :zephyr-app: samples/subsys/modbus/rtu_server - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :gen-args: -DDTC_OVERLAY_FILE=cdc-acm.overlay -DEXTRA_CONF_FILE=overlay-cdc-acm.conf :compact: diff --git a/samples/subsys/modbus/rtu_server/sample.yaml b/samples/subsys/modbus/rtu_server/sample.yaml index cdc239211b2..76f1eba7f44 100644 --- a/samples/subsys/modbus/rtu_server/sample.yaml +++ b/samples/subsys/modbus/rtu_server/sample.yaml @@ -4,10 +4,10 @@ tests: sample.modbus.rtu_server: build_only: true platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - uart - modbus @@ -20,10 +20,10 @@ tests: sample.modbus.rtu_server.cdc_acm: build_only: true platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - usb - modbus diff --git a/samples/subsys/nvs/README.rst b/samples/subsys/nvs/README.rst index ac1df6f9cf7..c9912631614 100644 --- a/samples/subsys/nvs/README.rst +++ b/samples/subsys/nvs/README.rst @@ -23,11 +23,11 @@ Building and Running This sample can be found under :zephyr_file:`samples/subsys/nvs` in the Zephyr tree. The sample can be build for several platforms, the following commands build the -application for the nrf51dk_nrf51422 board. +application for the nrf51dk/nrf51822 board. .. zephyr-app-commands:: :zephyr-app: samples/subsys/nvs - :board: nrf51dk_nrf51422 + :board: nrf51dk/nrf51822 :goals: build flash :compact: diff --git a/samples/subsys/nvs/sample.yaml b/samples/subsys/nvs/sample.yaml index e2249e9f3eb..051edc635f9 100644 --- a/samples/subsys/nvs/sample.yaml +++ b/samples/subsys/nvs/sample.yaml @@ -7,7 +7,7 @@ tests: depends_on: nvs platform_exclude: qemu_x86 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 harness: console harness_config: type: multi_line diff --git a/samples/subsys/pm/device_pm/sample.yaml b/samples/subsys/pm/device_pm/sample.yaml index 13a57cd4b2a..ee91d4678fa 100644 --- a/samples/subsys/pm/device_pm/sample.yaml +++ b/samples/subsys/pm/device_pm/sample.yaml @@ -3,10 +3,10 @@ sample: tests: sample.power.ospm.dev_idle_pm: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 - qemu_x86 - - mps2_an385 + - mps2/an385 integration_platforms: - qemu_x86 tags: power diff --git a/samples/subsys/portability/cmsis_rtos_v2/timer_synchronization/sample.yaml b/samples/subsys/portability/cmsis_rtos_v2/timer_synchronization/sample.yaml index f4a8ad690cf..f3ef6778395 100644 --- a/samples/subsys/portability/cmsis_rtos_v2/timer_synchronization/sample.yaml +++ b/samples/subsys/portability/cmsis_rtos_v2/timer_synchronization/sample.yaml @@ -5,7 +5,7 @@ tests: integration_platforms: - native_sim platform_exclude: - - qemu_arc_hs5x # See issue #62405 + - qemu_arc/qemu_arc_hs5x # See issue #62405 tags: cmsis_rtos min_ram: 32 min_flash: 34 diff --git a/samples/subsys/settings/README.rst b/samples/subsys/settings/README.rst index 82f8b797e86..c126ca1d0da 100644 --- a/samples/subsys/settings/README.rst +++ b/samples/subsys/settings/README.rst @@ -16,7 +16,7 @@ register them. Requirements ************ -* A board with settings support, for instance: nrf52840dk_nrf52840 +* A board with settings support, for instance: nrf52840dk/nrf52840 * Or qemu_x86 target Building and Running diff --git a/samples/subsys/shell/fs/sample.yaml b/samples/subsys/shell/fs/sample.yaml index 2f30aad68bb..e065b4e27eb 100644 --- a/samples/subsys/shell/fs/sample.yaml +++ b/samples/subsys/shell/fs/sample.yaml @@ -25,7 +25,7 @@ tests: sample.filesystem.shell.flash_load: tags: - flash_load - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 extra_args: CONF_FILE=prj_flash_load.conf integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 diff --git a/samples/subsys/shell/shell_module/sample.yaml b/samples/subsys/shell/shell_module/sample.yaml index 95ac36bc6b3..ceba72d6842 100644 --- a/samples/subsys/shell/shell_module/sample.yaml +++ b/samples/subsys/shell/shell_module/sample.yaml @@ -43,7 +43,7 @@ tests: harness: keyboard extra_args: CONF_FILE="prj_minimal_rtt.conf" integration_platforms: - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52833 sample.shell.shell_module.login: filter: CONFIG_SERIAL and dt_chosen_enabled("zephyr,shell-uart") tags: shell diff --git a/samples/subsys/task_wdt/sample.yaml b/samples/subsys/task_wdt/sample.yaml index 334d6e3a24f..fc4ca93776b 100644 --- a/samples/subsys/task_wdt/sample.yaml +++ b/samples/subsys/task_wdt/sample.yaml @@ -17,8 +17,10 @@ common: - "Task watchdog sample application." depends_on: watchdog platform_exclude: - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 tests: sample.task_wdt: integration_platforms: diff --git a/samples/subsys/tracing/README.rst b/samples/subsys/tracing/README.rst index 299ab0a751d..89c3ac1eb5f 100644 --- a/samples/subsys/tracing/README.rst +++ b/samples/subsys/tracing/README.rst @@ -19,7 +19,7 @@ Build a UART-tracing image with: .. zephyr-app-commands:: :zephyr-app: samples/subsys/tracing - :board: mps2_an521 + :board: mps2/an521 :conf: "prj_uart.conf" :goals: build :compact: @@ -28,7 +28,7 @@ or: .. zephyr-app-commands:: :zephyr-app: samples/subsys/tracing - :board: mps2_an521 + :board: mps2/an521 :conf: "prj_uart_ctf.conf" :goals: build :compact: @@ -44,7 +44,7 @@ Build a USB-tracing image with: .. zephyr-app-commands:: :zephyr-app: samples/subsys/tracing - :board: sam_e70_xplained + :board: sam_e70_xplained/same70q21 :conf: "prj_usb.conf" :goals: build :compact: @@ -53,7 +53,7 @@ or: .. zephyr-app-commands:: :zephyr-app: samples/subsys/tracing - :board: sam_e70_xplained + :board: sam_e70_xplained/same70q21 :conf: "prj_usb_ctf.conf" :goals: build :compact: diff --git a/samples/subsys/tracing/sample.yaml b/samples/subsys/tracing/sample.yaml index 23db8876cee..877ea096b58 100644 --- a/samples/subsys/tracing/sample.yaml +++ b/samples/subsys/tracing/sample.yaml @@ -23,11 +23,11 @@ tests: - "sys_trace_.*_user.*" sample.tracing.format.sysview: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - mimxrt1050_evk - mimxrt1064_evk integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_args: CONF_FILE="prj_sysview.conf" sample.tracing.osawareness.openocd: arch_exclude: @@ -45,7 +45,7 @@ tests: extra_args: CONF_FILE="prj_uart.conf" filter: dt_chosen_enabled("zephyr,tracing-uart") sample.tracing.transport.usb: - platform_allow: sam_e70_xplained + platform_allow: sam_e70_xplained/same70q21 depends_on: usb_device extra_args: CONF_FILE="prj_usb.conf" sample.tracing.transport.uart.ctf: @@ -57,7 +57,7 @@ tests: extra_args: CONF_FILE="prj_uart_ctf.conf" filter: dt_chosen_enabled("zephyr,tracing-uart") sample.tracing.transport.usb.ctf: - platform_allow: sam_e70_xplained + platform_allow: sam_e70_xplained/same70q21 depends_on: usb_device extra_args: CONF_FILE="prj_usb_ctf.conf" sample.tracing.transport.native: diff --git a/samples/subsys/usb/audio/headphones_microphone/sample.yaml b/samples/subsys/usb/audio/headphones_microphone/sample.yaml index dde503ee1ea..16420c75f44 100644 --- a/samples/subsys/usb/audio/headphones_microphone/sample.yaml +++ b/samples/subsys/usb/audio/headphones_microphone/sample.yaml @@ -6,8 +6,8 @@ tests: tags: usb arch_exclude: posix integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp harness: console harness_config: type: multi_line diff --git a/samples/subsys/usb/audio/headset/sample.yaml b/samples/subsys/usb/audio/headset/sample.yaml index 83a20596db7..6c61a4ce7ef 100644 --- a/samples/subsys/usb/audio/headset/sample.yaml +++ b/samples/subsys/usb/audio/headset/sample.yaml @@ -6,8 +6,8 @@ tests: tags: usb arch_exclude: posix integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp harness: console harness_config: type: multi_line diff --git a/samples/subsys/usb/cdc_acm/sample.yaml b/samples/subsys/usb/cdc_acm/sample.yaml index 61b72fa41ef..85dc6b7af27 100644 --- a/samples/subsys/usb/cdc_acm/sample.yaml +++ b/samples/subsys/usb/cdc_acm/sample.yaml @@ -15,9 +15,9 @@ tests: tags: usb extra_args: CONF_FILE="usbd_next_prj.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f - - 96b_carbon + - 96b_carbon/stm32f401xe harness: console harness_config: type: one_line diff --git a/samples/subsys/usb/dfu/README.rst b/samples/subsys/usb/dfu/README.rst index 0ca87d7a8cf..04e0fbf332d 100644 --- a/samples/subsys/usb/dfu/README.rst +++ b/samples/subsys/usb/dfu/README.rst @@ -39,7 +39,7 @@ For example: .. code-block:: console - west build -b nrf52840dk_nrf52840 zephyr/samples/subsys/usb/dfu -d build-dfu -- \ + west build -b nrf52840dk/nrf52840 zephyr/samples/subsys/usb/dfu -d build-dfu -- \ -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"bootloader/mcuboot/root-rsa-2048.pem\" Build and flash MCUboot bootloader for Zephyr project as it is described in @@ -53,7 +53,7 @@ in :ref:`mcuboot`). For example: .. code-block:: console - west build -b nrf52840dk_nrf52840 zephyr/samples/hello_world -d build-hello_world -- \ + west build -b nrf52840dk/nrf52840 zephyr/samples/hello_world -d build-hello_world -- \ -DCONFIG_BOOTLOADER_MCUBOOT=y '-DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE="bootloader/mcuboot/root-rsa-2048.pem"' Testing @@ -88,7 +88,7 @@ showing this output to the console: I: Bootloader chainload address offset: 0xc000 I: Jumping to the first image slot *** Booting Zephyr OS build zephyr-v3.0.0-361-gb987e6daa2f9 *** - Hello World! nrf52840dk_nrf52840 + Hello World! nrf52840dk Reset the SoC again and MCUboot should revert the images and boot @@ -128,7 +128,7 @@ Both symbols can be enabled with the :file:`overlay-permanent-download.conf` ove .. code-block:: console - west build -b nrf52840dk_nrf52840 zephyr/samples/subsys/usb/dfu -d build-dfu -- \ + west build -b nrf52840dk/nrf52840 zephyr/samples/subsys/usb/dfu -d build-dfu -- \ -DCONFIG_BOOTLOADER_MCUBOOT=y '-DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE="bootloader/mcuboot/root-rsa-2048.pem"' \ -DEXTRA_CONF_FILE=overlay-permanent-download.conf @@ -150,7 +150,7 @@ Note the ``Swap type: perm``. I: Bootloader chainload address offset: 0xc000 I: Jumping to the first image slot *** Booting Zephyr OS build zephyr-v3.0.0-361-gb987e6daa2f9 *** - Hello World! nrf52840dk_nrf52840 + Hello World! nrf52840dk .. _MCUboot GitHub repo: https://github.com/zephyrproject-rtos/mcuboot diff --git a/samples/subsys/usb/dfu/sample.yaml b/samples/subsys/usb/dfu/sample.yaml index f74c6327c86..1700b087473 100644 --- a/samples/subsys/usb/dfu/sample.yaml +++ b/samples/subsys/usb/dfu/sample.yaml @@ -6,26 +6,26 @@ common: arch_exclude: posix platform_exclude: - mimxrt1010_evk - - mimxrt1050_evk_qspi + - mimxrt1050_evk@qspi - mimxrt1020_evk - mimxrt1015_evk - mimxrt1060_evk - sam4l_ek - mimxrt1050_evk - - mimxrt1060_evk_hyperflash + - mimxrt1060_evk@hyperflash - nucleo_f207zg - teensy40 - teensy41 - b_u585i_iot02a - frdm_kl25z - - lpcxpresso55s69_cpu0 - - stm32l562e_dk_ns + - lpcxpresso55s69/lpc55s69/cpu0 + - stm32l562e_dk/stm32l562xx/ns depends_on: usb_device filter: dt_label_with_parent_compat_enabled("slot0_partition", "fixed-partitions") and dt_label_with_parent_compat_enabled("slot1_partition", "fixed-partitions") and dt_chosen_enabled("zephyr,flash-controller") and CONFIG_FLASH_HAS_DRIVER_ENABLED integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f tests: sample.usb.dfu: diff --git a/samples/subsys/usb/hid-cdc/README.rst b/samples/subsys/usb/hid-cdc/README.rst index 403785ef25e..e0678d9d173 100644 --- a/samples/subsys/usb/hid-cdc/README.rst +++ b/samples/subsys/usb/hid-cdc/README.rst @@ -42,7 +42,7 @@ for the :ref:`nrf52840dk_nrf52840` board: .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/hid-cdc - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/subsys/usb/hid-cdc/sample.yaml b/samples/subsys/usb/hid-cdc/sample.yaml index 15ee2d5a47d..acc25a0ac1a 100644 --- a/samples/subsys/usb/hid-cdc/sample.yaml +++ b/samples/subsys/usb/hid-cdc/sample.yaml @@ -4,9 +4,9 @@ tests: sample.usb.hid-cdc: depends_on: usb_device platform_allow: - - nrf52840dk_nrf52840 - - nrf52840dongle_nrf52840 + - nrf52840dk/nrf52840 + - nrf52840dongle/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 harness: button tags: usb diff --git a/samples/subsys/usb/mass/README.rst b/samples/subsys/usb/mass/README.rst index 1c2011f363f..64b6293cbdd 100644 --- a/samples/subsys/usb/mass/README.rst +++ b/samples/subsys/usb/mass/README.rst @@ -61,7 +61,7 @@ to use the external 16 MiBi QSPI flash chip with a 2 MiBy FAT partition. .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/mass - :board: adafruit_feather_nrf52840 + :board: adafruit_feather/nrf52840 :gen-args: -DCONFIG_APP_MSC_STORAGE_FLASH_FATFS=y :goals: build :compact: @@ -128,7 +128,7 @@ be connected to SPI using e.g. a shield, example can be built as follows: .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/mass - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: waveshare_epaper_gdeh0154a07 :gen-args: -DCONFIG_APP_MSC_STORAGE_SDCARD=y :goals: build @@ -162,7 +162,7 @@ This board configures to use the external 64 MiBi QSPI flash chip with a .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/mass - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :gen-args: -DCONFIG_APP_MSC_STORAGE_FLASH_LITTLEFS=y :goals: build :compact: diff --git a/samples/subsys/usb/mass/boards/stm32l562e_dk_ns.conf b/samples/subsys/usb/mass/boards/stm32l562e_dk_stm32l562xx_ns.conf similarity index 100% rename from samples/subsys/usb/mass/boards/stm32l562e_dk_ns.conf rename to samples/subsys/usb/mass/boards/stm32l562e_dk_stm32l562xx_ns.conf diff --git a/samples/subsys/usb/mass/sample.yaml b/samples/subsys/usb/mass/sample.yaml index 9149012a212..d7c2c32bc59 100644 --- a/samples/subsys/usb/mass/sample.yaml +++ b/samples/subsys/usb/mass/sample.yaml @@ -23,7 +23,7 @@ tests: min_ram: 128 depends_on: usb_device platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f extra_args: - CONF_FILE="usbd_next_prj.conf" @@ -66,11 +66,11 @@ tests: depends_on: usb_device filter: dt_compat_enabled("nordic,qspi-nor") platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - adafruit_feather_nrf52840 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - adafruit_feather/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_LOG_DEFAULT_LEVEL=3 - CONFIG_APP_MSC_STORAGE_FLASH_FATFS=y @@ -91,11 +91,11 @@ tests: depends_on: usb_device filter: dt_compat_enabled("nordic,qspi-nor") platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - adafruit_feather_nrf52840 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - adafruit_feather/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_args: CONF_FILE="usbd_next_prj.conf" extra_configs: - CONFIG_LOG_DEFAULT_LEVEL=3 @@ -138,11 +138,11 @@ tests: depends_on: usb_device filter: dt_compat_enabled("nordic,qspi-nor") platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - adafruit_feather_nrf52840 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - adafruit_feather/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_LOG_DEFAULT_LEVEL=3 - CONFIG_APP_MSC_STORAGE_FLASH_LITTLEFS=y diff --git a/samples/subsys/usb/shell/README.rst b/samples/subsys/usb/shell/README.rst index 0e368187c79..9f2ddb8898d 100644 --- a/samples/subsys/usb/shell/README.rst +++ b/samples/subsys/usb/shell/README.rst @@ -28,7 +28,7 @@ currently it is only MAX3421E. The example can be built as follows: .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/shell - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: sparkfun_max3421e :gen-args: -DCONFIG_UHC_DRIVER=y -DCONFIG_USB_HOST_STACK=y :goals: flash @@ -40,7 +40,7 @@ the platform has already defined or not `zephyr_uhc0` or `zephyr_udc0` nodelabel .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/shell - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :gen-args: -DEXTRA_CONF_FILE=virtual.conf -DDTC_OVERLAY_FILE=virtual.overlay :goals: flash :compact: diff --git a/samples/subsys/usb/shell/sample.yaml b/samples/subsys/usb/shell/sample.yaml index fa09a7769d1..834044da3df 100644 --- a/samples/subsys/usb/shell/sample.yaml +++ b/samples/subsys/usb/shell/sample.yaml @@ -3,7 +3,7 @@ sample: tests: sample.usbd.shell: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f depends_on: usb_device harness: keyboard @@ -17,7 +17,7 @@ tests: - CONF_FILE="device_and_host_prj.conf" - SHIELD="sparkfun_max3421e" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f build_only: true sample.usbh.shell.virtual: diff --git a/samples/subsys/usb/uac2_explicit_feedback/README.rst b/samples/subsys/usb/uac2_explicit_feedback/README.rst index 8d9ff40dc7a..dd6ec13908e 100644 --- a/samples/subsys/usb/uac2_explicit_feedback/README.rst +++ b/samples/subsys/usb/uac2_explicit_feedback/README.rst @@ -59,6 +59,6 @@ To build and flash the application: .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/uac2_explicit_feedback - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build flash :compact: diff --git a/samples/subsys/usb/uac2_explicit_feedback/sample.yaml b/samples/subsys/usb/uac2_explicit_feedback/sample.yaml index c1f851c009b..c9d54574701 100644 --- a/samples/subsys/usb/uac2_explicit_feedback/sample.yaml +++ b/samples/subsys/usb/uac2_explicit_feedback/sample.yaml @@ -6,5 +6,5 @@ tests: - usb_device - i2s tags: usb i2s - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp harness: TBD diff --git a/samples/subsys/zbus/benchmark/README.rst b/samples/subsys/zbus/benchmark/README.rst index 52a7d864481..2db3e7d23ff 100644 --- a/samples/subsys/zbus/benchmark/README.rst +++ b/samples/subsys/zbus/benchmark/README.rst @@ -56,9 +56,9 @@ The complete benchmark command using Robot framework is: .. code-block:: console - robot --variable serial_port:/dev/ttyACM0 --variable board:nrf52dk_nrf52832 -d /tmp/benchmark_out benchmark_256KB.robot + robot --variable serial_port:/dev/ttyACM0 --variable board:nrf52dk/nrf52832 -d /tmp/benchmark_out benchmark_256KB.robot -An example of execution using the ``nrf52dk_nrf52832`` board would generate a file like this: +An example of execution using the ``nrf52dk/nrf52832`` board would generate a file like this: .. code-block:: diff --git a/samples/subsys/zbus/benchmark/benchmark_256KB.robot b/samples/subsys/zbus/benchmark/benchmark_256KB.robot index db2ab59d6a4..810438f3098 100644 --- a/samples/subsys/zbus/benchmark/benchmark_256KB.robot +++ b/samples/subsys/zbus/benchmark/benchmark_256KB.robot @@ -9,7 +9,7 @@ Suite Teardown Terminate All Processes kill=True *** Variables *** ${csv_file} zbus_dyn_benchmark_256kb.csv -${board} hifive1_revb +${board} hifive1@B ${serial_port} /dev/ttyACM0 diff --git a/samples/subsys/zbus/dyn_channel/sample.yaml b/samples/subsys/zbus/dyn_channel/sample.yaml index 478516474f1..3a2f9fb0c70 100644 --- a/samples/subsys/zbus/dyn_channel/sample.yaml +++ b/samples/subsys/zbus/dyn_channel/sample.yaml @@ -68,4 +68,4 @@ tests: tags: zbus integration_platforms: - qemu_x86 - - mps2_an521 + - mps2/an521/cpu0 diff --git a/samples/subsys/zbus/remote_mock/boards/hifive1_revb.conf b/samples/subsys/zbus/remote_mock/boards/hifive1_fe310_B.conf similarity index 100% rename from samples/subsys/zbus/remote_mock/boards/hifive1_revb.conf rename to samples/subsys/zbus/remote_mock/boards/hifive1_fe310_B.conf diff --git a/samples/subsys/zbus/remote_mock/boards/hifive1_revb.overlay b/samples/subsys/zbus/remote_mock/boards/hifive1_fe310_B.overlay similarity index 100% rename from samples/subsys/zbus/remote_mock/boards/hifive1_revb.overlay rename to samples/subsys/zbus/remote_mock/boards/hifive1_fe310_B.overlay diff --git a/samples/subsys/zbus/remote_mock/sample.yaml b/samples/subsys/zbus/remote_mock/sample.yaml index 1b632901ed2..75898cc1644 100644 --- a/samples/subsys/zbus/remote_mock/sample.yaml +++ b/samples/subsys/zbus/remote_mock/sample.yaml @@ -7,6 +7,6 @@ tests: platform_allow: - native_posix - native_sim - - hifive1_revb + - hifive1@B integration_platforms: - native_sim diff --git a/samples/subsys/zbus/uart_bridge/boards/hifive1_revb.conf b/samples/subsys/zbus/uart_bridge/boards/hifive1_fe310_B.conf similarity index 100% rename from samples/subsys/zbus/uart_bridge/boards/hifive1_revb.conf rename to samples/subsys/zbus/uart_bridge/boards/hifive1_fe310_B.conf diff --git a/samples/subsys/zbus/uart_bridge/boards/hifive1_revb.overlay b/samples/subsys/zbus/uart_bridge/boards/hifive1_fe310_B.overlay similarity index 100% rename from samples/subsys/zbus/uart_bridge/boards/hifive1_revb.overlay rename to samples/subsys/zbus/uart_bridge/boards/hifive1_fe310_B.overlay diff --git a/samples/tfm_integration/psa_crypto/README.rst b/samples/tfm_integration/psa_crypto/README.rst index baef7287bb0..2173cc35643 100644 --- a/samples/tfm_integration/psa_crypto/README.rst +++ b/samples/tfm_integration/psa_crypto/README.rst @@ -84,14 +84,14 @@ On MPS2+ AN521: =============== 1. Build Zephyr with a non-secure configuration - (``-DBOARD=mps2_an521_ns``). + (``-DBOARD=mps2/an521/cpu0/ns``). Using ``west`` .. code-block:: bash cd - west build -p -b mps2_an521_ns samples/tfm_integration/psa_crypto + west build -p -b mps2/an521/cpu0/ns samples/tfm_integration/psa_crypto Using ``cmake`` and ``ninja`` @@ -100,7 +100,7 @@ On MPS2+ AN521: cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=mps2_an521_ns .. + cmake -GNinja -DBOARD=mps2/an521/cpu0/ns .. ninja Using ``cmake`` and ``make`` @@ -110,7 +110,7 @@ On MPS2+ AN521: cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -DBOARD=mps2_an521_ns .. + cmake -DBOARD=mps2/an521/cpu0/ns .. make 2. Copy application binary files (mcuboot.bin and tfm_sign.bin) to @@ -137,7 +137,7 @@ On MPS2+ AN521: On QEMU: ======== -Build Zephyr with a non-secure configuration (``-DBOARD=mps2_an521_ns``) +Build Zephyr with a non-secure configuration (``-DBOARD=mps2/an521/cpu0/ns``) and run it in qemu via the ``run`` command. Using ``west`` @@ -145,7 +145,7 @@ and run it in qemu via the ``run`` command. .. code-block:: bash cd - west build -p -b mps2_an521_ns samples/tfm_integration/psa_crypto -t run + west build -p -b mps2/an521/cpu0/ns samples/tfm_integration/psa_crypto -t run Using ``cmake`` and ``ninja`` @@ -154,7 +154,7 @@ and run it in qemu via the ``run`` command. cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=mps2_an521_ns .. + cmake -GNinja -DBOARD=mps2/an521/cpu0/ns .. ninja run Using ``cmake`` and ``make`` @@ -164,7 +164,7 @@ and run it in qemu via the ``run`` command. cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -DBOARD=mps2_an521_ns .. + cmake -DBOARD=mps2/an521/cpu0/ns .. make run On LPCxpresso55S69: @@ -198,7 +198,7 @@ On nRF5340 and nRF9160: ======================= Build Zephyr with a non-secure configuration -(``-DBOARD=nrf5340dk_nrf5340_cpuapp_ns`` or ``-DBOARD=nrf9160dk_nrf9160_ns``). +(``-DBOARD=nrf5340dk/nrf5340/cpuapp/ns`` or ``-DBOARD=nrf9160dk/nrf9160/ns``). Example, for nRF9160, using ``cmake`` and ``ninja`` @@ -207,7 +207,7 @@ Build Zephyr with a non-secure configuration cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=nrf9160dk_nrf9160_ns .. + cmake -GNinja -DBOARD=nrf9160dk/nrf9160/ns .. If building with BL2 (MCUboot bootloader) enabled, manually flash the MCUboot bootloader image binary (``bl2.hex``). @@ -230,7 +230,7 @@ On BL5340: ========== Build Zephyr with a non-secure configuration -(``-DBOARD=bl5340_dvk_cpuapp_ns``). +(``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``). Example using ``cmake`` and ``ninja`` @@ -239,7 +239,7 @@ Build Zephyr with a non-secure configuration cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=bl5340_dvk_cpuapp_ns .. + cmake -GNinja -DBOARD=bl5340_dvk/nrf5340/cpuapp/ns .. Flash the concatenated TF-M + Zephyr binary. diff --git a/samples/tfm_integration/psa_crypto/sample.yaml b/samples/tfm_integration/psa_crypto/sample.yaml index 45c9940b021..3f25acf88f3 100644 --- a/samples/tfm_integration/psa_crypto/sample.yaml +++ b/samples/tfm_integration/psa_crypto/sample.yaml @@ -11,9 +11,9 @@ tests: - crypto - csr - mcuboot - platform_allow: mps2_an521_ns v2m_musca_s1_ns - nrf5340dk_nrf5340_cpuapp_ns nrf9160dk_nrf9160_ns - stm32l562e_dk_ns bl5340_dvk_cpuapp_ns + platform_allow: mps2/an521/cpu0/ns v2m_musca_s1/musca_s1/ns + nrf5340dk/nrf5340/cpuapp/ns nrf9160dk/nrf9160/ns + stm32l562e_dk/stm32l562xx/ns bl5340_dvk/nrf5340/cpuapp/ns harness: console harness_config: type: multi_line diff --git a/samples/tfm_integration/psa_protected_storage/README.rst b/samples/tfm_integration/psa_protected_storage/README.rst index 1600fde5f53..67c72440b1b 100644 --- a/samples/tfm_integration/psa_protected_storage/README.rst +++ b/samples/tfm_integration/psa_protected_storage/README.rst @@ -46,7 +46,7 @@ Following is an example based on ``west build`` .. code-block:: bash - $ west build samples/tfm_integration/psa_protected_storage/ -p -b mps2_an521_ns -t run + $ west build samples/tfm_integration/psa_protected_storage/ -p -b mps2/an521/cpu0/ns -t run Sample Output ============= diff --git a/samples/tfm_integration/psa_protected_storage/sample.yaml b/samples/tfm_integration/psa_protected_storage/sample.yaml index 83ddde86758..4c3e2b277a9 100644 --- a/samples/tfm_integration/psa_protected_storage/sample.yaml +++ b/samples/tfm_integration/psa_protected_storage/sample.yaml @@ -4,13 +4,13 @@ sample: common: tags: psa platform_allow: - - mps2_an521_ns - - v2m_musca_s1_ns - - nrf5340dk_nrf5340_cpuapp_ns - - nrf9160dk_nrf9160_ns - - bl5340_dvk_cpuapp_ns + - mps2/an521/cpu0/ns + - v2m_musca_s1/musca_s1/ns + - nrf5340dk/nrf5340/cpuapp/ns + - nrf9160dk/nrf9160/ns + - bl5340_dvk/nrf5340/cpuapp/ns integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns harness: console harness_config: type: multi_line diff --git a/samples/tfm_integration/tfm_ipc/README.rst b/samples/tfm_integration/tfm_ipc/README.rst index dc5233c7fc5..839f5f99523 100644 --- a/samples/tfm_integration/tfm_ipc/README.rst +++ b/samples/tfm_integration/tfm_ipc/README.rst @@ -33,21 +33,21 @@ executed on MPS2+ AN521 and ST Nucleo L552ZE Q. On MPS2+ AN521: =============== -#. Build Zephyr with a non-secure configuration (``-DBOARD=mps2_an521_ns``). +#. Build Zephyr with a non-secure configuration (``-DBOARD=mps2/an521/cpu0/ns``). .. code-block:: bash cd $ZEPHYR_ROOT/samples/tfm_integration/tfm_ipc/ mkdir build cd build - cmake -DBOARD=mps2_an521_ns .. + cmake -DBOARD=mps2/an521/cpu0/ns .. make You can also use west as follows: .. code-block:: bash - $ west build -p -b mps2_an521_ns zephyr/samples/tfm_integration/tfm_ipc + $ west build -p -b mps2/an521/cpu0/ns zephyr/samples/tfm_integration/tfm_ipc #. Copy application binary files (mcuboot.bin and tfm_sign.bin) to ``/SOFTWARE/``. @@ -82,7 +82,7 @@ folder to update the ``-DGNUARM_PATH=/opt/toolchain/arm-none-eabi`` path. On QEMU: ======== -The MPS2+ AN521 target (``mps2_an521_ns``), which is based on a +The MPS2+ AN521 target (``mps2/an521/cpu0/ns``), which is based on a dual core ARM Cortex-M33 setup, also allows you to run TF-M tests using QEMU if you don't have access to a supported ARMv8-M development board. @@ -99,7 +99,7 @@ ninja or make, adding the ``run`` commands: .. code-block:: bash - $ west build -b mps2_an521_ns zephyr/samples/tfm_integration/tfm_ipc -t run + $ west build -b mps2/an521/cpu0/ns zephyr/samples/tfm_integration/tfm_ipc -t run Or, post build: @@ -118,7 +118,7 @@ Build Zephyr with a non-secure configuration: .. code-block:: bash - $ west build -b nucleo_l552ze_q_ns samples/tfm_integration/tfm_ipc/ + $ west build -b nucleo_l552ze_q/stm32l552xx/ns samples/tfm_integration/tfm_ipc/ Example, for building non-secure configuration for STM32L562E-DK Discovery @@ -171,7 +171,7 @@ On nRF5340 and nRF9160: ======================= Build Zephyr with a non-secure configuration -(``-DBOARD=nrf5340dk_nrf5340_cpuapp_ns`` or ``-DBOARD=nrf9160dk_nrf9160_ns``). +(``-DBOARD=nrf5340dk/nrf5340/cpuapp/ns`` or ``-DBOARD=nrf9160dk/nrf9160/ns``). Example, for nRF9160, using ``cmake`` and ``ninja`` @@ -180,7 +180,7 @@ Build Zephyr with a non-secure configuration cd /samples/tfm_integration/tfm_ipc/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=nrf9160dk_nrf9160_ns .. + cmake -GNinja -DBOARD=nrf9160dk/nrf9160/ns .. If building with BL2 (MCUboot bootloader) enabled, manually flash the MCUboot bootloader image binary (``bl2.hex``). @@ -203,7 +203,7 @@ On BL5340: ========== Build Zephyr with a non-secure configuration -(``-DBOARD=bl5340_dvk_cpuapp_ns``). +(``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``). Example using ``cmake`` and ``ninja`` @@ -212,7 +212,7 @@ Build Zephyr with a non-secure configuration cd /samples/tfm_integration/tfm_ipc/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=bl5340_dvk_cpuapp_ns .. + cmake -GNinja -DBOARD=bl5340_dvk/nrf5340/cpuapp/ns .. Flash the concatenated TF-M + Zephyr binary. diff --git a/samples/tfm_integration/tfm_ipc/boards/nucleo_l552ze_q_ns.overlay b/samples/tfm_integration/tfm_ipc/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay similarity index 100% rename from samples/tfm_integration/tfm_ipc/boards/nucleo_l552ze_q_ns.overlay rename to samples/tfm_integration/tfm_ipc/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay diff --git a/samples/tfm_integration/tfm_ipc/sample.yaml b/samples/tfm_integration/tfm_ipc/sample.yaml index 4537b5c48dc..0d141f4555c 100644 --- a/samples/tfm_integration/tfm_ipc/sample.yaml +++ b/samples/tfm_integration/tfm_ipc/sample.yaml @@ -9,16 +9,16 @@ tests: - trusted-firmware-m - mcuboot platform_allow: - - mps2_an521_ns - - nrf5340dk_nrf5340_cpuapp_ns - - nrf9160dk_nrf9160_ns - - nucleo_l552ze_q_ns - - stm32l562e_dk_ns - - v2m_musca_s1_ns - - bl5340_dvk_cpuapp_ns - - b_u585i_iot02a_ns + - mps2/an521/cpu0/ns + - nrf5340dk/nrf5340/cpuapp/ns + - nrf9160dk/nrf9160/ns + - nucleo_l552ze_q/stm32l552xx/ns + - stm32l562e_dk/stm32l562xx/ns + - v2m_musca_s1/musca_s1/ns + - bl5340_dvk/nrf5340/cpuapp/ns + - b_u585i_iot02a/stm32u585xx/ns integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns harness: console harness_config: type: multi_line @@ -31,7 +31,7 @@ tests: tags: - introduction - trusted-firmware-m - platform_allow: mps2_an521_ns + platform_allow: mps2/an521/cpu0/ns extra_configs: - CONFIG_TFM_BL2=n harness: console diff --git a/samples/tfm_integration/tfm_psa_test/README.rst b/samples/tfm_integration/tfm_psa_test/README.rst index 1060629baba..73944b6ec65 100644 --- a/samples/tfm_integration/tfm_psa_test/README.rst +++ b/samples/tfm_integration/tfm_psa_test/README.rst @@ -32,7 +32,7 @@ You can indicate the desired test suite at build time via a config flag: .. code-block:: bash $ west build samples/tfm_integration/tfm_psa_test/ \ - -p -b mps2_an521_ns -t run -- \ + -p -b mps2/an521/cpu0/ns -t run -- \ -DCONFIG_TFM_PSA_TEST_STORAGE=y Note that not all test suites are valid on all boards. @@ -50,7 +50,7 @@ Following is an example based on ``west build`` .. code-block:: bash - $ west build samples/tfm_integration/tfm_psa_test/ -p -b mps2_an521_ns -t run -- -DCONFIG_TFM_PSA_TEST_STORAGE=y + $ west build samples/tfm_integration/tfm_psa_test/ -p -b mps2/an521/cpu0/ns -t run -- -DCONFIG_TFM_PSA_TEST_STORAGE=y Sample Output ============= diff --git a/samples/tfm_integration/tfm_psa_test/sample.yaml b/samples/tfm_integration/tfm_psa_test/sample.yaml index df8ae92a372..d924e704618 100644 --- a/samples/tfm_integration/tfm_psa_test/sample.yaml +++ b/samples/tfm_integration/tfm_psa_test/sample.yaml @@ -3,16 +3,16 @@ common: - trusted-firmware-m - mcuboot platform_allow: - - mps2_an521_ns - - nrf5340dk_nrf5340_cpuapp_ns - - nrf9160dk_nrf9160_ns - - nrf9161dk_nrf9161_ns - - v2m_musca_s1_ns + - mps2/an521/cpu0/ns + - nrf5340dk/nrf5340/cpuapp/ns + - nrf9160dk/nrf9160/ns + - nrf9161dk/nrf9161/ns + - v2m_musca_s1/musca_s1/ns modules: - psa-arch-tests - tf-m-tests integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns harness: console harness_config: type: multi_line diff --git a/samples/tfm_integration/tfm_regression_test/README.rst b/samples/tfm_integration/tfm_regression_test/README.rst index e5e634bb4bc..2257414344f 100644 --- a/samples/tfm_integration/tfm_regression_test/README.rst +++ b/samples/tfm_integration/tfm_regression_test/README.rst @@ -34,7 +34,7 @@ Following is an example based on ``west build`` .. code-block:: bash - $ west build samples/tfm_integration/tfm_regression_test/ -p -b mps2_an521_ns -t run + $ west build samples/tfm_integration/tfm_regression_test/ -p -b mps2/an521/cpu0/ns -t run Sample Output ============= diff --git a/samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_ns.overlay b/samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay similarity index 100% rename from samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_ns.overlay rename to samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay diff --git a/samples/tfm_integration/tfm_regression_test/sample.yaml b/samples/tfm_integration/tfm_regression_test/sample.yaml index e5612d909c8..61af265e77b 100644 --- a/samples/tfm_integration/tfm_regression_test/sample.yaml +++ b/samples/tfm_integration/tfm_regression_test/sample.yaml @@ -5,12 +5,12 @@ common: modules: - psa-arch-tests platform_allow: - - nrf5340dk_nrf5340_cpuapp_ns - - nrf9160dk_nrf9160_ns - - nrf9161dk_nrf9161_ns - - v2m_musca_s1_ns + - nrf5340dk/nrf5340/cpuapp/ns + - nrf9160dk/nrf9160/ns + - nrf9161dk/nrf9161/ns + - v2m_musca_s1/musca_s1/ns integration_platforms: - - nrf5340dk_nrf5340_cpuapp_ns + - nrf5340dk/nrf5340/cpuapp/ns harness: console harness_config: type: multi_line diff --git a/samples/tfm_integration/tfm_secure_partition/sample.yaml b/samples/tfm_integration/tfm_secure_partition/sample.yaml index 06cb3bc2e96..7cd36b08475 100644 --- a/samples/tfm_integration/tfm_secure_partition/sample.yaml +++ b/samples/tfm_integration/tfm_secure_partition/sample.yaml @@ -2,12 +2,12 @@ common: tags: - trusted-firmware-m platform_allow: - - mps2_an521_ns - - v2m_musca_s1_ns - - nrf5340dk_nrf5340_cpuapp_ns - - nrf9160dk_nrf9160_ns + - mps2/an521/cpu0/ns + - v2m_musca_s1/musca_s1/ns + - nrf5340dk/nrf5340/cpuapp/ns + - nrf9160dk/nrf9160/ns integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns harness: console harness_config: type: multi_line diff --git a/samples/userspace/hello_world_user/sample.yaml b/samples/userspace/hello_world_user/sample.yaml index b40042f71f5..297ee8e9062 100644 --- a/samples/userspace/hello_world_user/sample.yaml +++ b/samples/userspace/hello_world_user/sample.yaml @@ -4,7 +4,7 @@ sample: name: hello world user common: integration_platforms: - - mps2_an385 + - mps2/an385 tags: introduction harness: console harness_config: @@ -17,5 +17,5 @@ tests: arch_exclude: - posix platform_exclude: - - qemu_xtensa_mmu + - qemu_xtensa/dc233c/mmu tags: introduction diff --git a/samples/userspace/prod_consumer/sample.yaml b/samples/userspace/prod_consumer/sample.yaml index 232fdd31f06..f316d26ef49 100644 --- a/samples/userspace/prod_consumer/sample.yaml +++ b/samples/userspace/prod_consumer/sample.yaml @@ -3,7 +3,7 @@ sample: name: producer-consumer common: integration_platforms: - - mps2_an385 + - mps2/an385 tags: userspace harness: console harness_config: diff --git a/samples/userspace/shared_mem/README.rst b/samples/userspace/shared_mem/README.rst index 7ed6328e66f..7c9db36f243 100644 --- a/samples/userspace/shared_mem/README.rst +++ b/samples/userspace/shared_mem/README.rst @@ -17,7 +17,7 @@ Requirements The sample is dependent on the subsystem app_memory, and it will not run on boards that do not support the subsystem. The sample -was tested on the following boards qemu_x86,frdm_k64, an 96b_carbon. +was tested on the following boards qemu_x86,frdm_k64, and ``96b_carbon/stm32f401xe``. Building and Running ******************** diff --git a/samples/userspace/shared_mem/sample.yaml b/samples/userspace/shared_mem/sample.yaml index 5b42ae2b7e3..e53d93490fd 100644 --- a/samples/userspace/shared_mem/sample.yaml +++ b/samples/userspace/shared_mem/sample.yaml @@ -4,7 +4,7 @@ sample: name: protected memory common: integration_platforms: - - mps2_an385 + - mps2/an385 tags: userspace harness: console harness_config: diff --git a/samples/userspace/syscall_perf/sample.yaml b/samples/userspace/syscall_perf/sample.yaml index 8f27b925d64..69830fd8946 100644 --- a/samples/userspace/syscall_perf/sample.yaml +++ b/samples/userspace/syscall_perf/sample.yaml @@ -13,4 +13,4 @@ tests: filter: CONFIG_ARCH_HAS_USERSPACE arch_allow: riscv integration_platforms: - - hifive1_revb + - hifive1@B diff --git a/scripts/ci/Kconfig.board.v2 b/scripts/ci/Kconfig.board.v2 new file mode 100644 index 00000000000..e1335cafe39 --- /dev/null +++ b/scripts/ci/Kconfig.board.v2 @@ -0,0 +1,10 @@ +# Kconfig top-level ci for compliance testing Kconfig tree for boards / SoC v2 scheme. +# +# Copyright (c) 2022 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 + +mainmenu "Zephyr board / SoC v2 Configuration" + +source "boards/Kconfig.v2" +source "soc/Kconfig.v2" diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index 6985896d018..dcad0ca51b9 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -29,6 +29,8 @@ sys.path.insert(0, str(Path(__file__).resolve().parents[1])) from get_maintainer import Maintainers, MaintainersError +import list_boards +import list_hardware logger = None @@ -226,6 +228,40 @@ def run(self): self.failure(output) +class BoardYmlCheck(ComplianceTest): + """ + Check the board.yml files + """ + name = "BoardYml" + doc = "Check the board.yml file format" + path_hint = "" + + def check_board_file(self, file, vendor_prefixes): + """Validate a single board file.""" + with open(file) as fp: + for line_num, line in enumerate(fp.readlines(), start=1): + if "vendor:" in line: + _, vnd = line.strip().split(":", 2) + vnd = vnd.strip() + if vnd not in vendor_prefixes: + desc = f"invalid vendor: {vnd}" + self.fmtd_failure("error", "BoardYml", file, line_num, + desc=desc) + + def run(self): + vendor_prefixes = ["others"] + with open(os.path.join(ZEPHYR_BASE, "dts", "bindings", "vendor-prefixes.txt")) as fp: + for line in fp.readlines(): + line = line.strip() + if not line or line.startswith("#"): + continue + vendor, _ = line.split("\t", 2) + vendor_prefixes.append(vendor) + + path = Path(ZEPHYR_BASE) + for file in path.glob("**/board.yml"): + self.check_board_file(file, vendor_prefixes) + class DevicetreeBindingsCheck(ComplianceTest): """ Checks if we are introducing any unwanted properties in Devicetree Bindings. @@ -273,16 +309,17 @@ class KconfigCheck(ComplianceTest): doc = "See https://docs.zephyrproject.org/latest/build/kconfig/tips.html for more details." path_hint = "" - def run(self, full=True, no_modules=False): + def run(self, full=True, no_modules=False, filename="Kconfig", hwm=None): self.no_modules = no_modules - kconf = self.parse_kconfig() + kconf = self.parse_kconfig(filename=filename, hwm=hwm) self.check_top_menu_not_too_long(kconf) self.check_no_pointless_menuconfigs(kconf) self.check_no_undef_within_kconfig(kconf) self.check_no_redefined_in_defconfig(kconf) self.check_no_enable_in_boolean_prompt(kconf) + self.check_soc_name_sync(kconf) if full: self.check_no_undef_outside_kconfig(kconf) @@ -360,8 +397,98 @@ def get_kconfig_dts(self, kconfig_dts_file, settings_file): except subprocess.CalledProcessError as ex: self.error(ex.output.decode("utf-8")) + def get_v1_model_syms(self, kconfig_v1_file, kconfig_v1_syms_file): + """ + Generate a symbol define Kconfig file. + This function creates a file with all Kconfig symbol definitions from + old boards model so that those symbols will not appear as undefined + symbols in hardware model v2. + + This is needed to complete Kconfig compliance tests. + """ + os.environ['HWM_SCHEME'] = 'v1' + # 'kconfiglib' is global + # pylint: disable=undefined-variable + + try: + kconf_v1 = kconfiglib.Kconfig(filename=kconfig_v1_file, warn=False) + except kconfiglib.KconfigError as e: + self.failure(str(e)) + raise EndTest + + with open(kconfig_v1_syms_file, 'w') as fp_kconfig_v1_syms_file: + for s in kconf_v1.defined_syms: + if s.type != kconfiglib.UNKNOWN: + fp_kconfig_v1_syms_file.write('config ' + s.name) + fp_kconfig_v1_syms_file.write('\n\t' + kconfiglib.TYPE_TO_STR[s.type]) + fp_kconfig_v1_syms_file.write('\n\n') + + def get_v2_model(self, kconfig_dir): + """ + Get lists of v2 boards and SoCs and put them in a file that is parsed by + Kconfig - def parse_kconfig(self): + This is needed to complete Kconfig sanity tests. + """ + os.environ['HWM_SCHEME'] = 'v2' + kconfig_file = os.path.join(kconfig_dir, 'boards', 'Kconfig') + kconfig_boards_file = os.path.join(kconfig_dir, 'boards', 'Kconfig.boards') + kconfig_defconfig_file = os.path.join(kconfig_dir, 'boards', 'Kconfig.defconfig') + + root_args = argparse.Namespace(**{'board_roots': [Path(ZEPHYR_BASE)], + 'soc_roots': [Path(ZEPHYR_BASE)], 'board': None}) + v2_boards = list_boards.find_v2_boards(root_args) + + with open(kconfig_defconfig_file, 'w') as fp: + for board in v2_boards: + fp.write('osource "' + os.path.join(board.dir, 'Kconfig.defconfig') + '"\n') + + with open(kconfig_boards_file, 'w') as fp: + for board in v2_boards: + board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", board.name).upper() + fp.write('config ' + board_str + '\n') + fp.write('\t bool\n') + for identifier in list_boards.board_v2_identifiers(board): + board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", identifier).upper() + fp.write('config ' + board_str + '\n') + fp.write('\t bool\n') + fp.write('source "' + os.path.join(board.dir, 'Kconfig.') + board.name + '"\n\n') + + with open(kconfig_file, 'w') as fp: + fp.write('osource "' + os.path.join(kconfig_dir, 'boards', 'Kconfig.syms.v1') + '"\n') + for board in v2_boards: + fp.write('osource "' + os.path.join(board.dir, 'Kconfig') + '"\n') + + kconfig_defconfig_file = os.path.join(kconfig_dir, 'soc', 'Kconfig.defconfig') + kconfig_soc_file = os.path.join(kconfig_dir, 'soc', 'Kconfig.soc') + kconfig_file = os.path.join(kconfig_dir, 'soc', 'Kconfig') + + root_args = argparse.Namespace(**{'soc_roots': [Path(ZEPHYR_BASE)]}) + v2_systems = list_hardware.find_v2_systems(root_args) + + soc_folders = {soc.folder for soc in v2_systems.get_socs()} + with open(kconfig_defconfig_file, 'w') as fp: + for folder in soc_folders: + fp.write('osource "' + os.path.join(folder, 'Kconfig.defconfig') + '"\n') + + with open(kconfig_soc_file, 'w') as fp: + for folder in soc_folders: + fp.write('source "' + os.path.join(folder, 'Kconfig.soc') + '"\n') + + with open(kconfig_file, 'w') as fp: + for folder in soc_folders: + fp.write('source "' + os.path.join(folder, 'Kconfig') + '"\n') + + kconfig_file = os.path.join(kconfig_dir, 'arch', 'Kconfig') + + root_args = argparse.Namespace(**{'arch_roots': [Path(ZEPHYR_BASE)], 'arch': None}) + v2_archs = list_hardware.find_v2_archs(root_args) + + with open(kconfig_file, 'w') as fp: + for arch in v2_archs['archs']: + fp.write('source "' + os.path.join(arch['path'], 'Kconfig') + '"\n') + + def parse_kconfig(self, filename="Kconfig", hwm=None): """ Returns a kconfiglib.Kconfig object for the Kconfig files. We reuse this object for all tests to avoid having to reparse for each test. @@ -386,7 +513,7 @@ def parse_kconfig(self): # Parse the entire Kconfig tree, to make sure we see all symbols os.environ["SOC_DIR"] = "soc/" os.environ["ARCH_DIR"] = "arch/" - os.environ["BOARD_DIR"] = "boards/*/*" + os.environ["BOARD"] = "boards" os.environ["ARCH"] = "*" os.environ["KCONFIG_BINARY_DIR"] = kconfiglib_dir os.environ['DEVICETREE_CONF'] = "dummy" @@ -403,6 +530,15 @@ def parse_kconfig(self): self.get_kconfig_dts(os.path.join(kconfiglib_dir, "Kconfig.dts"), os.path.join(kconfiglib_dir, "settings_file.txt")) + # To make compliance work with old hw model and HWMv2 simultaneously. + kconfiglib_boards_dir = os.path.join(kconfiglib_dir, 'boards') + os.makedirs(kconfiglib_boards_dir, exist_ok=True) + os.makedirs(os.path.join(kconfiglib_dir, 'soc'), exist_ok=True) + os.makedirs(os.path.join(kconfiglib_dir, 'arch'), exist_ok=True) + + os.environ["BOARD_DIR"] = kconfiglib_boards_dir + self.get_v2_model(kconfiglib_dir) + # Tells Kconfiglib to generate warnings for all references to undefined # symbols within Kconfig files os.environ["KCONFIG_WARN_UNDEF"] = "y" @@ -412,7 +548,7 @@ def parse_kconfig(self): # them: so some warnings might get printed # twice. "warn_to_stderr=False" could unfortunately cause # some (other) warnings to never be printed. - return kconfiglib.Kconfig() + return kconfiglib.Kconfig(filename=filename) except kconfiglib.KconfigError as e: self.failure(str(e)) raise EndTest @@ -444,7 +580,6 @@ def get_defined_syms(self, kconf): return set([sym.name for sym in kconf_syms] + re.findall(regex, grep_stdout, re.MULTILINE)) - def check_top_menu_not_too_long(self, kconf): """ Checks that there aren't too many items in the top-level menu (which @@ -545,6 +680,34 @@ def check_no_undef_within_kconfig(self, kconf): if undef_ref_warnings: self.failure(f"Undefined Kconfig symbols:\n\n {undef_ref_warnings}") + def check_soc_name_sync(self, kconf): + root_args = argparse.Namespace(**{'soc_roots': [Path(ZEPHYR_BASE)]}) + v2_systems = list_hardware.find_v2_systems(root_args) + + soc_names = {soc.name for soc in v2_systems.get_socs()} + + soc_kconfig_names = set() + for node in kconf.node_iter(): + # 'kconfiglib' is global + # pylint: disable=undefined-variable + if isinstance(node.item, kconfiglib.Symbol) and node.item.name == "SOC": + n = node.item + for d in n.defaults: + soc_kconfig_names.add(d[0].name) + + soc_name_warnings = [] + for name in soc_names: + if name not in soc_kconfig_names: + soc_name_warnings.append(f"soc name: {name} not found in CONFIG_SOC defaults.") + + if soc_name_warnings: + soc_name_warning_str = '\n'.join(soc_name_warnings) + self.failure(f''' +Missing SoC names or CONFIG_SOC vs soc.yml out of sync: + +{soc_name_warning_str} +''') + def check_no_undef_outside_kconfig(self, kconf): """ Checks that there are no references to undefined Kconfig symbols @@ -639,6 +802,7 @@ def check_no_undef_outside_kconfig(self, kconf): # toolchain Kconfig which is sourced based on # Zephyr toolchain variant and therefore not # visible to compliance. + "BOARD_", # Used as regex in scripts/utils/board_v1_to_v2.py "BOOT_ENCRYPTION_KEY_FILE", # Used in sysbuild "BOOT_ENCRYPT_IMAGE", # Used in sysbuild "BINDESC_", # Used in documentation as a prefix @@ -718,6 +882,7 @@ def check_no_undef_outside_kconfig(self, kconf): "LOG_BACKEND_MOCK_OUTPUT_SYST", #Referenced in testcase.yaml of log_syst test "SEL", "SHIFT", + "SOC_SERIES_", # Used as regex in scripts/utils/board_v1_to_v2.py "SOC_WATCH", # Issue 13749 "SOME_BOOL", "SOME_INT", @@ -773,6 +938,23 @@ def run(self): super().run(full=False, no_modules=True) +class KconfigHWMv2Check(KconfigCheck, ComplianceTest): + """ + This runs the Kconfig test for board and SoC v2 scheme. + This check ensures that all symbols inside the v2 scheme is also defined + within the same tree. + This ensures the board and SoC trees are fully self-contained and reusable. + """ + name = "KconfigHWMv2" + doc = "See https://docs.zephyrproject.org/latest/guides/kconfig/index.html for more details." + + def run(self): + # Use dedicated Kconfig board / soc v2 scheme file. + # This file sources only v2 scheme tree. + kconfig_file = os.path.join(os.path.dirname(__file__), "Kconfig.board.v2") + super().run(full=False, hwm="v2", filename=kconfig_file) + + class Nits(ComplianceTest): """ Checks various nits in added/modified files. Doesn't check stuff that's @@ -1222,6 +1404,8 @@ def check_file(self, file, fp): start_marker = f"{self.MARKER}-start" stop_marker = f"{self.MARKER}-stop" + start_line = None + stop_line = None for line_num, line in enumerate(fp.readlines(), start=1): if start_marker in line: @@ -1231,15 +1415,18 @@ def check_file(self, file, fp): desc=desc) in_block = True block_data = "" + start_line = line_num + 1 elif stop_marker in line: if not in_block: desc = f"{stop_marker} without {start_marker}" self.fmtd_failure("error", "KeepSorted", file, line_num, desc=desc) in_block = False + stop_line = line_num - 1 if not self.block_is_sorted(block_data): - desc = f"sorted block is not sorted" + desc = (f"sorted block is not sorted, sort by running: " + + f"\"ex -s -c '{start_line},{stop_line} sort i|x' {file}\"") self.fmtd_failure("error", "KeepSorted", file, line_num, desc=desc) elif not line.strip() or line.startswith("#"): diff --git a/scripts/ci/test_plan.py b/scripts/ci/test_plan.py index 216cfe5b9ba..26787496a7c 100755 --- a/scripts/ci/test_plan.py +++ b/scripts/ci/test_plan.py @@ -226,7 +226,8 @@ def find_boards(self): roots.append(repository_path) # Look for boards in monitored repositories - lb_args = argparse.Namespace(**{ 'arch_roots': roots, 'board_roots': roots}) + lb_args = argparse.Namespace(**{'arch_roots': roots, 'board_roots': roots, 'board': None, + 'board_dir': None}) known_boards = list_boards.find_boards(lb_args) for b in boards: name_re = re.compile(b) diff --git a/scripts/footprint/plan.txt b/scripts/footprint/plan.txt index 948a430c62e..8e3f5b1b089 100644 --- a/scripts/footprint/plan.txt +++ b/scripts/footprint/plan.txt @@ -2,8 +2,8 @@ footprints,default,frdm_k64f,tests/benchmarks/footprints, footprints,userspace,frdm_k64f,tests/benchmarks/footprints,-DCONF_FILE=prj_userspace.conf footprints,default,disco_l475_iot1,tests/benchmarks/footprints, footprints,userspace,disco_l475_iot1,tests/benchmarks/footprints,-DCONF_FILE=prj_userspace.conf -footprints,default,nrf5340dk_nrf5340_cpuapp,tests/benchmarks/footprints, -footprints,default,nrf51dk_nrf51422,tests/benchmarks/footprints, +footprints,default,nrf5340dk/nrf5340/cpuapp,tests/benchmarks/footprints, +footprints,default,nrf51dk/nrf51822,tests/benchmarks/footprints, footprints,default,altera_max10,tests/benchmarks/footprints, footprints,default,hifive1_revb,tests/benchmarks/footprints, footprints,default,intel_ehl_crb,tests/benchmarks/footprints, @@ -14,17 +14,17 @@ footprints,power-management,it8xxx2_evb,tests/benchmarks/footprints,-DCONF_FILE= footprints,power-management,iotdk,tests/benchmarks/footprints,-DCONF_FILE=prj_pm.conf echo_client,default,frdm_k64f,samples/net/sockets/echo_client, echo_server,default,frdm_k64f,samples/net/sockets/echo_server, -bt_beacon,default,nrf52840dk_nrf52840,samples/bluetooth/beacon, -bt_peripheral,default,nrf52840dk_nrf52840,samples/bluetooth/peripheral, -bt_central_hr,default,nrf52840dk_nrf52840,samples/bluetooth/central_hr, +bt_beacon,default,nrf52840dk/nrf52840,samples/bluetooth/beacon, +bt_peripheral,default,nrf52840dk/nrf52840,samples/bluetooth/peripheral, +bt_central_hr,default,nrf52840dk/nrf52840,samples/bluetooth/central_hr, bt_mesh_demo,default,bbc_microbit,samples/bluetooth/mesh_demo, -bt_hap_ha,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/hap_ha, -bt_unicast_audio_client,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/unicast_audio_client, -bt_unicast_audio_server,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/unicast_audio_server, -bt_tmap_central,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/tmap_central, -bt_tmap_peripheral,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/tmap_peripheral, -bt_tmap_bms,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/tmap_bms, -bt_tmap_bmr,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/tmap_bmr, -bt_hci_ipc,default,nrf5340dk_nrf5340_cpunet,samples/bluetooth/hci_ipc, -bt_hci_ipc,iso-broadcast,nrf5340dk_nrf5340_cpunet,samples/bluetooth/hci_ipc,-DCONF_FILE=nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf -bt_hci_ipc,iso-receive,nrf5340dk_nrf5340_cpunet,samples/bluetooth/hci_ipc,-DCONF_FILE=nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf +bt_hap_ha,default,nrf5340dk/nrf5340_cpuapp,samples/bluetooth/hap_ha, +bt_unicast_audio_client,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/unicast_audio_client, +bt_unicast_audio_server,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/unicast_audio_server, +bt_tmap_central,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/tmap_central, +bt_tmap_peripheral,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/tmap_peripheral, +bt_tmap_bms,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/tmap_bms, +bt_tmap_bmr,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/tmap_bmr, +bt_hci_ipc,default,nrf5340dk/nrf5340/cpunet,samples/bluetooth/hci_ipc, +bt_hci_ipc,iso-broadcast,nrf5340dk/nrf5340/cpunet,samples/bluetooth/hci_ipc,-DCONF_FILE=nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf +bt_hci_ipc,iso-receive,nrf5340dk/nrf5340/cpunet,samples/bluetooth/hci_ipc,-DCONF_FILE=nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf diff --git a/scripts/kconfig/kconfigfunctions.py b/scripts/kconfig/kconfigfunctions.py index 71200b7f955..bb4b4dd519f 100644 --- a/scripts/kconfig/kconfigfunctions.py +++ b/scripts/kconfig/kconfigfunctions.py @@ -6,6 +6,7 @@ import inspect import os import pickle +import re import sys from pathlib import Path @@ -840,6 +841,17 @@ def dt_gpio_hogs_enabled(kconf, _): return "n" + +def sanitize_upper(kconf, _, string): + """ + Sanitize the string, so that the string only contains alpha-numeric + characters or underscores. All non-alpha-numeric characters are replaced + with an underscore, '_'. + When string has been sanitized it will be converted into upper case. + """ + return re.sub(r'[^a-zA-Z0-9_]', '_', string).upper() + + def shields_list_contains(kconf, _, shield): """ Return "n" if cmake environment variable 'SHIELD_AS_LIST' doesn't exist. @@ -907,5 +919,6 @@ def shields_list_contains(kconf, _, shield): "dt_gpio_hogs_enabled": (dt_gpio_hogs_enabled, 0, 0), "dt_chosen_partition_addr_int": (dt_chosen_partition_addr, 1, 3), "dt_chosen_partition_addr_hex": (dt_chosen_partition_addr, 1, 3), + "sanitize_upper": (sanitize_upper, 1, 1), "shields_list_contains": (shields_list_contains, 1, 1), } diff --git a/scripts/list_boards.py b/scripts/list_boards.py index 4c7c87cad45..55fbe970d74 100755 --- a/scripts/list_boards.py +++ b/scripts/list_boards.py @@ -5,9 +5,20 @@ import argparse from collections import defaultdict +from dataclasses import dataclass, field import itertools from pathlib import Path -from typing import NamedTuple +import pykwalify.core +import sys +from typing import List +import yaml +import list_hardware + +BOARD_SCHEMA_PATH = str(Path(__file__).parent / 'schemas' / 'board-schema.yml') +with open(BOARD_SCHEMA_PATH, 'r') as f: + board_schema = yaml.safe_load(f.read()) + +BOARD_YML = 'board.yml' # # This is shared code between the build system's 'boards' target @@ -18,10 +29,73 @@ # 'ninja boards' in a build directory without west installed.) # -class Board(NamedTuple): +@dataclass +class Revision: + name: str + variants: List[str] = field(default_factory=list) + + @staticmethod + def from_dict(revision): + revisions = [] + for r in revision.get('revisions', []): + revisions.append(Revision.from_dict(r)) + return Revision(revision['name'], revisions) + + + +@dataclass +class Variant: + name: str + variants: List[str] = field(default_factory=list) + + @staticmethod + def from_dict(variant): + variants = [] + for v in variant.get('variants', []): + variants.append(Variant.from_dict(v)) + return Variant(variant['name'], variants) + + +@dataclass +class Cpucluster: + name: str + variants: List[str] = field(default_factory=list) + + +@dataclass +class Soc: + name: str + cpuclusters: List[str] = field(default_factory=list) + variants: List[str] = field(default_factory=list) + + @staticmethod + def from_soc(soc, variants): + if soc is None: + return None + if soc.cpuclusters: + cpus = [] + for c in soc.cpuclusters: + cpus.append(Cpucluster(c, + [Variant.from_dict(v) for v in variants if c == v['cpucluster']] + )) + return Soc(soc.name, cpuclusters=cpus) + return Soc(soc.name, variants=[Variant.from_dict(v) for v in variants]) + + +@dataclass(frozen=True) +class Board: name: str - arch: str dir: Path + hwm: str + arch: str = None + vendor: str = None + revision_format: str = None + revision_default: str = None + revision_exact: bool = False + revisions: List[str] = field(default_factory=list, compare=False) + socs: List[Soc] = field(default_factory=list, compare=False) + variants: List[str] = field(default_factory=list, compare=False) + def board_key(board): return board.name @@ -40,8 +114,11 @@ def find_arch2board_set(args): ret = defaultdict(set) for root in args.board_roots: - for arch, boards in find_arch2board_set_in(root, arches).items(): - ret[arch] |= boards + for arch, boards in find_arch2board_set_in(root, arches, args.board_dir).items(): + if args.board is not None: + ret[arch] |= {b for b in boards if b.name == args.board} + else: + ret[arch] |= boards return ret @@ -68,30 +145,107 @@ def find_arches_in(root): return ret -def find_arch2board_set_in(root, arches): +def find_arch2board_set_in(root, arches, board_dir): ret = defaultdict(set) boards = root / 'boards' for arch in arches: - if not (boards / arch).is_dir(): + if not (boards / "boards_legacy" / arch).is_dir(): continue - for maybe_board in (boards / arch).iterdir(): + for maybe_board in (boards / "boards_legacy" / arch).iterdir(): if not maybe_board.is_dir(): continue + if board_dir is not None and board_dir != maybe_board: + continue for maybe_defconfig in maybe_board.iterdir(): file_name = maybe_defconfig.name if file_name.endswith('_defconfig'): board_name = file_name[:-len('_defconfig')] - ret[arch].add(Board(board_name, arch, maybe_board)) + ret[arch].add(Board(board_name, maybe_board, 'v1', arch=arch)) return ret + +def load_v2_boards(board_name, board_yml, systems): + boards = [] + if board_yml.is_file(): + with board_yml.open('r') as f: + b = yaml.safe_load(f.read()) + + try: + pykwalify.core.Core(source_data=b, schema_data=board_schema).validate() + except pykwalify.errors.SchemaError as e: + sys.exit('ERROR: Malformed "build" section in file: {}\n{}' + .format(board_yml.as_posix(), e)) + + mutual_exclusive = {'board', 'boards'} + if len(mutual_exclusive - b.keys()) < 1: + sys.exit(f'ERROR: Malformed content in file: {board_yml.as_posix()}\n' + f'{mutual_exclusive} are mutual exclusive at this level.') + + board_array = b.get('boards', [ b.get('board', None) ]) + for board in board_array: + if board_name is not None: + if board['name'] != board_name: + # Not the board we're looking for, ignore. + continue + + board_revision = board.get('revision') + if board_revision is not None and board_revision.get('format') != 'custom': + if board_revision.get('default') is None: + sys.exit(f'ERROR: Malformed "board" section in file: {board_yml.as_posix()}\n' + "Cannot find required key 'default'. Path: '/board/revision.'") + if board_revision.get('revisions') is None: + sys.exit(f'ERROR: Malformed "board" section in file: {board_yml.as_posix()}\n' + "Cannot find required key 'revisions'. Path: '/board/revision.'") + + mutual_exclusive = {'socs', 'variants'} + if len(mutual_exclusive - board.keys()) < 1: + sys.exit(f'ERROR: Malformed "board" section in file: {board_yml.as_posix()}\n' + f'{mutual_exclusive} are mutual exclusive at this level.') + socs = [Soc.from_soc(systems.get_soc(s['name']), s.get('variants', [])) + for s in board.get('socs', {})] + + board = Board( + name=board['name'], + dir=board_yml.parent, + vendor=board.get('vendor'), + revision_format=board.get('revision', {}).get('format'), + revision_default=board.get('revision', {}).get('default'), + revision_exact=board.get('revision', {}).get('exact', False), + revisions=[Revision.from_dict(v) for v in + board.get('revision', {}).get('revisions', [])], + socs=socs, + variants=[Variant.from_dict(v) for v in board.get('variants', [])], + hwm='v2', + ) + boards.append(board) + return boards + + +def find_v2_boards(args): + root_args = argparse.Namespace(**{'soc_roots': args.soc_roots}) + systems = list_hardware.find_v2_systems(root_args) + + boards = [] + board_files = [] + for root in args.board_roots: + board_files.extend((root / 'boards').rglob(BOARD_YML)) + + for board_yml in board_files: + b = load_v2_boards(args.board, board_yml, systems) + boards.extend(b) + return boards + + def parse_args(): parser = argparse.ArgumentParser(allow_abbrev=False) add_args(parser) + add_args_formatting(parser) return parser.parse_args() + def add_args(parser): # Remember to update west-completion.bash if you add or remove # flags @@ -101,12 +255,112 @@ def add_args(parser): parser.add_argument("--board-root", dest='board_roots', default=[], type=Path, action='append', help='add a board root, may be given more than once') + parser.add_argument("--soc-root", dest='soc_roots', default=[], + type=Path, action='append', + help='add a soc root, may be given more than once') + parser.add_argument("--board", dest='board', default=None, + help='lookup the specific board, fail if not found') + parser.add_argument("--board-dir", default=None, type=Path, + help='Only look for boards at the specific location') + + +def add_args_formatting(parser): + parser.add_argument("--cmakeformat", default=None, + help='''CMake Format string to use to list each board''') + -def dump_boards(arch2boards): +def variant_v2_identifiers(variant, identifier): + identifiers = [identifier + '/' + variant.name] + for v in variant.variants: + identifiers.extend(variant_v2_identifiers(v, identifier + '/' + variant.name)) + return identifiers + + +def board_v2_identifiers(board): + identifiers = [] + + for s in board.socs: + if s.cpuclusters: + for c in s.cpuclusters: + id_str = board.name + '/' + s.name + '/' + c.name + identifiers.append(id_str) + for v in c.variants: + identifiers.extend(variant_v2_identifiers(v, id_str)) + else: + id_str = board.name + '/' + s.name + identifiers.append(id_str) + for v in s.variants: + identifiers.extend(variant_v2_identifiers(v, id_str)) + + if not board.socs: + identifiers.append(board.name) + + for v in board.variants: + identifiers.extend(variant_v2_identifiers(v, board.name)) + return identifiers + + +def board_v2_identifiers_csv(board): + # Return in csv (comma separated value) format + return ",".join(board_v2_identifiers(board)) + + +def dump_v2_boards(args): + if args.board_dir: + root_args = argparse.Namespace(**{'soc_roots': args.soc_roots}) + systems = list_hardware.find_v2_systems(root_args) + boards = load_v2_boards(args.board, args.board_dir / BOARD_YML, systems) + else: + boards = find_v2_boards(args) + + for b in boards: + identifiers = board_v2_identifiers(b) + if args.cmakeformat is not None: + notfound = lambda x: x or 'NOTFOUND' + info = args.cmakeformat.format( + NAME='NAME;' + b.name, + DIR='DIR;' + str(b.dir.as_posix()), + VENDOR='VENDOR;' + notfound(b.vendor), + HWM='HWM;' + b.hwm, + REVISION_DEFAULT='REVISION_DEFAULT;' + notfound(b.revision_default), + REVISION_FORMAT='REVISION_FORMAT;' + notfound(b.revision_format), + REVISION_EXACT='REVISION_EXACT;' + str(b.revision_exact), + REVISIONS='REVISIONS;' + ';'.join( + [x.name for x in b.revisions]), + SOCS='SOCS;' + ';'.join([s.name for s in b.socs]), + IDENTIFIERS='IDENTIFIERS;' + ';'.join(identifiers) + ) + print(info) + else: + print(f'{b.name}') + + +def dump_boards(args): + arch2boards = find_arch2boards(args) for arch, boards in arch2boards.items(): - print(f'{arch}:') + if args.cmakeformat is None: + print(f'{arch}:') for board in boards: - print(f' {board.name}') + if args.cmakeformat is not None: + info = args.cmakeformat.format( + NAME='NAME;' + board.name, + DIR='DIR;' + str(board.dir.as_posix()), + HWM='HWM;' + board.hwm, + VENDOR='VENDOR;NOTFOUND', + REVISION_DEFAULT='REVISION_DEFAULT;NOTFOUND', + REVISION_FORMAT='REVISION_FORMAT;NOTFOUND', + REVISION_EXACT='REVISION_EXACT;NOTFOUND', + REVISIONS='REVISIONS;NOTFOUND', + VARIANT_DEFAULT='VARIANT_DEFAULT;NOTFOUND', + SOCS='SOCS;', + IDENTIFIERS='IDENTIFIERS;' + ) + print(info) + else: + print(f' {board.name}') + if __name__ == '__main__': - dump_boards(find_arch2boards(parse_args())) + args = parse_args() + dump_boards(args) + dump_v2_boards(args) diff --git a/scripts/list_hardware.py b/scripts/list_hardware.py new file mode 100755 index 00000000000..d43cfb29c39 --- /dev/null +++ b/scripts/list_hardware.py @@ -0,0 +1,283 @@ +#!/usr/bin/env python3 + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +import argparse +from dataclasses import dataclass +from pathlib import Path, PurePath +import pykwalify.core +import sys +from typing import List +import yaml + + +SOC_SCHEMA_PATH = str(Path(__file__).parent / 'schemas' / 'soc-schema.yml') +with open(SOC_SCHEMA_PATH, 'r') as f: + soc_schema = yaml.safe_load(f.read()) + +ARCH_SCHEMA_PATH = str(Path(__file__).parent / 'schemas' / 'arch-schema.yml') +with open(ARCH_SCHEMA_PATH, 'r') as f: + arch_schema = yaml.safe_load(f.read()) + +SOC_YML = 'soc.yml' +ARCHS_YML_PATH = PurePath('arch/archs.yml') + +class Systems: + + def __init__(self, folder='', soc_yaml=None): + self._socs = [] + self._series = [] + self._families = [] + + if soc_yaml is None: + return + + try: + data = yaml.safe_load(soc_yaml) + pykwalify.core.Core(source_data=data, + schema_data=soc_schema).validate() + except (yaml.YAMLError, pykwalify.errors.SchemaError) as e: + sys.exit(f'ERROR: Malformed yaml {soc_yaml.as_posix()}', e) + + for f in data.get('family', []): + family = Family(f['name'], folder, [], []) + for s in f.get('series', []): + series = Series(s['name'], folder, f['name'], []) + socs = [(Soc(soc['name'], + [c['name'] for c in soc.get('cpuclusters', [])], + folder, s['name'], f['name'])) + for soc in s.get('socs', [])] + series.socs.extend(socs) + self._series.append(series) + self._socs.extend(socs) + family.series.append(series) + family.socs.extend(socs) + socs = [(Soc(soc['name'], + [c['name'] for c in soc.get('cpuclusters', [])], + folder, None, f['name'])) + for soc in f.get('socs', [])] + self._socs.extend(socs) + self._families.append(family) + + for s in data.get('series', []): + series = Series(s['name'], folder, '', []) + socs = [(Soc(soc['name'], + [c['name'] for c in soc.get('cpuclusters', [])], + folder, s['name'], '')) + for soc in s.get('socs', [])] + series.socs.extend(socs) + self._series.append(series) + self._socs.extend(socs) + + socs = [(Soc(soc['name'], + [c['name'] for c in soc.get('cpuclusters', [])], + folder, '', '')) + for soc in data.get('socs', [])] + self._socs.extend(socs) + + @staticmethod + def from_file(socs_file): + '''Load SoCs from a soc.yml file. + ''' + try: + with open(socs_file, 'r') as f: + socs_yaml = f.read() + except FileNotFoundError as e: + sys.exit(f'ERROR: socs.yml file not found: {socs_file.as_posix()}', e) + + return Systems(str(socs_file.parent), socs_yaml) + + @staticmethod + def from_yaml(socs_yaml): + '''Load socs from a string with YAML contents. + ''' + return Systems('', socs_yaml) + + def extend(self, systems): + self._families.extend(systems.get_families()) + self._series.extend(systems.get_series()) + self._socs.extend(systems.get_socs()) + + def get_families(self): + return self._families + + def get_series(self): + return self._series + + def get_socs(self): + return self._socs + + def get_soc(self, name): + try: + return next(s for s in self._socs if s.name == name) + except StopIteration: + sys.exit(f"ERROR: SoC '{name}' is not found, please ensure that the SoC exists " + f"and that soc-root containing '{name}' has been correctly defined.") + + +@dataclass +class Soc: + name: str + cpuclusters: List[str] + folder: str + series: str = '' + family: str = '' + + +@dataclass +class Series: + name: str + folder: str + family: str + socs: List[Soc] + + +@dataclass +class Family: + name: str + folder: str + series: List[Series] + socs: List[Soc] + + +def find_v2_archs(args): + ret = {'archs': []} + for root in args.arch_roots: + archs_yml = root / ARCHS_YML_PATH + + if Path(archs_yml).is_file(): + with Path(archs_yml).open('r') as f: + archs = yaml.safe_load(f.read()) + + try: + pykwalify.core.Core(source_data=archs, schema_data=arch_schema).validate() + except pykwalify.errors.SchemaError as e: + sys.exit('ERROR: Malformed "build" section in file: {}\n{}' + .format(archs_yml.as_posix(), e)) + + if args.arch is not None: + archs = {'archs': list(filter( + lambda arch: arch.get('name') == args.arch, archs['archs']))} + for arch in archs['archs']: + arch.update({'path': root / 'arch' / arch['path']}) + arch.update({'hwm': 'v2'}) + arch.update({'type': 'arch'}) + + ret['archs'].extend(archs['archs']) + + return ret + + +def find_v2_systems(args): + yml_files = [] + systems = Systems() + for root in args.soc_roots: + yml_files.extend((root / 'soc').rglob(SOC_YML)) + + for soc_yml in yml_files: + if soc_yml.is_file(): + systems.extend(Systems.from_file(soc_yml)) + + return systems + + +def parse_args(): + parser = argparse.ArgumentParser(allow_abbrev=False) + add_args(parser) + return parser.parse_args() + + +def add_args(parser): + default_fmt = '{name}' + + parser.add_argument("--soc-root", dest='soc_roots', default=[], + type=Path, action='append', + help='add a SoC root, may be given more than once') + parser.add_argument("--soc", default=None, help='lookup the specific soc') + parser.add_argument("--soc-series", default=None, help='lookup the specific soc series') + parser.add_argument("--soc-family", default=None, help='lookup the specific family') + parser.add_argument("--socs", action='store_true', help='lookup all socs') + parser.add_argument("--arch-root", dest='arch_roots', default=[], + type=Path, action='append', + help='add a arch root, may be given more than once') + parser.add_argument("--arch", default=None, help='lookup the specific arch') + parser.add_argument("--archs", action='store_true', help='lookup all archs') + parser.add_argument("--format", default=default_fmt, + help='''Format string to use to list each soc.''') + parser.add_argument("--cmakeformat", default=None, + help='''CMake format string to use to list each arch/soc.''') + + +def dump_v2_archs(args): + archs = find_v2_archs(args) + + for arch in archs['archs']: + if args.cmakeformat is not None: + info = args.cmakeformat.format( + TYPE='TYPE;' + arch['type'], + NAME='NAME;' + arch['name'], + DIR='DIR;' + str(arch['path'].as_posix()), + HWM='HWM;' + arch['hwm'], + # Below is non exising for arch but is defined here to support + # common formatting string. + SERIES='', + FAMILY='', + ARCH='', + VENDOR='' + ) + else: + info = args.format.format( + type=arch.get('type'), + name=arch.get('name'), + dir=arch.get('path'), + hwm=arch.get('hwm'), + # Below is non exising for arch but is defined here to support + # common formatting string. + series='', + family='', + arch='', + vendor='' + ) + + print(info) + + +def dump_v2_system(args, type, system): + if args.cmakeformat is not None: + info = args.cmakeformat.format( + TYPE='TYPE;' + type, + NAME='NAME;' + system.name, + DIR='DIR;' + Path(system.folder).as_posix(), + HWM='HWM;' + 'v2' + ) + else: + info = args.format.format( + type=type, + name=system.name, + dir=system.folder, + hwm='v2' + ) + + print(info) + + +def dump_v2_systems(args): + systems = find_v2_systems(args) + + for f in systems.get_families(): + dump_v2_system(args, 'family', f) + + for s in systems.get_series(): + dump_v2_system(args, 'series', s) + + for s in systems.get_socs(): + dump_v2_system(args, 'soc', s) + + +if __name__ == '__main__': + args = parse_args() + if any([args.socs, args.soc, args.soc_series, args.soc_family]): + dump_v2_systems(args) + if args.archs or args.arch is not None: + dump_v2_archs(args) diff --git a/scripts/pylib/pytest-twister-harness/README.rst b/scripts/pylib/pytest-twister-harness/README.rst index 860b7cd645d..2c7baf4e892 100644 --- a/scripts/pylib/pytest-twister-harness/README.rst +++ b/scripts/pylib/pytest-twister-harness/README.rst @@ -24,7 +24,7 @@ Run exemplary test shell application by Twister: ./scripts/twister -p native_sim -p qemu_x86 -T samples/subsys/testsuite/pytest/shell # hardware - ./scripts/twister -p nrf52840dk_nrf52840 --device-testing --device-serial /dev/ttyACM0 -T samples/subsys/testsuite/pytest/shell + ./scripts/twister -p nrf52840dk/nrf52840 --device-testing --device-serial /dev/ttyACM0 -T samples/subsys/testsuite/pytest/shell or build shell application by west and call pytest directly: @@ -43,5 +43,5 @@ or build shell application by west and call pytest directly: pytest --twister-harness --device-type=qemu --build-dir=build -p twister_harness.plugin # hardware - west build -p -b nrf52840dk_nrf52840 + west build -p -b nrf52840dk/nrf52840 pytest --twister-harness --device-type=hardware --device-serial=/dev/ttyACM0 --build-dir=build -p twister_harness.plugin diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py index dbd3465aba1..0c5cf2ab839 100644 --- a/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py +++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py @@ -51,7 +51,7 @@ def pytest_addoption(parser: pytest.Parser): ) twister_harness_group.addoption( '--platform', - help='Name of used platform (qemu_x86, nrf52840dk_nrf52840, etc.).' + help='Name of used platform (qemu_x86, nrf52840dk/nrf52840, etc.).' ) twister_harness_group.addoption( '--device-serial', diff --git a/scripts/pylib/twister/boards/unit/unit_testing/board.yml b/scripts/pylib/twister/boards/unit/unit_testing/board.yml new file mode 100644 index 00000000000..c3427dc0c65 --- /dev/null +++ b/scripts/pylib/twister/boards/unit/unit_testing/board.yml @@ -0,0 +1,5 @@ +board: + name: unit_testing + vendor: zephyr + socs: + - name: unit_testing diff --git a/scripts/pylib/twister/soc/unit/unit_testing/soc.yml b/scripts/pylib/twister/soc/unit/unit_testing/soc.yml new file mode 100644 index 00000000000..b965aa6a6f6 --- /dev/null +++ b/scripts/pylib/twister/soc/unit/unit_testing/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: unit_testing diff --git a/scripts/pylib/twister/twisterlib/platform.py b/scripts/pylib/twister/twisterlib/platform.py index d6123b2a5be..91c1df83428 100644 --- a/scripts/pylib/twister/twisterlib/platform.py +++ b/scripts/pylib/twister/twisterlib/platform.py @@ -52,6 +52,7 @@ def load(self, platform_file): data = scp.data self.name = data['identifier'] + self.normalized_name = self.name.replace("/", "_") self.twister = data.get("twister", True) # if no RAM size is specified by the board, take a default of 128K self.ram = data.get("ram", 128) diff --git a/scripts/pylib/twister/twisterlib/reports.py b/scripts/pylib/twister/twisterlib/reports.py index 3d4b155fa9d..001ee7d5092 100644 --- a/scripts/pylib/twister/twisterlib/reports.py +++ b/scripts/pylib/twister/twisterlib/reports.py @@ -545,13 +545,13 @@ def save_reports(self, name, suffix, report_dir, no_update, platform_reports): def target_report(self, json_file, outdir, suffix): - platforms = {inst.platform.name for _, inst in self.instances.items()} + platforms = {inst.platform for _, inst in self.instances.items()} for platform in platforms: if suffix: - filename = os.path.join(outdir,"{}_{}.xml".format(platform, suffix)) - json_platform_file = os.path.join(outdir,"{}_{}.json".format(platform, suffix)) + filename = os.path.join(outdir,"{}_{}.xml".format(platform.normalized_name, suffix)) + json_platform_file = os.path.join(outdir,"{}_{}.json".format(platform.normalized_name, suffix)) else: - filename = os.path.join(outdir,"{}.xml".format(platform)) - json_platform_file = os.path.join(outdir,"{}.json".format(platform)) - self.xunit_report(json_file, filename, platform, full_report=True) - self.json_report(json_platform_file, version=self.env.version, platform=platform) + filename = os.path.join(outdir,"{}.xml".format(platform.normalized_name)) + json_platform_file = os.path.join(outdir,"{}.json".format(platform.normalized_name)) + self.xunit_report(json_file, filename, platform.name, full_report=True) + self.json_report(json_platform_file, version=self.env.version, platform=platform.name) diff --git a/scripts/pylib/twister/twisterlib/testinstance.py b/scripts/pylib/twister/twisterlib/testinstance.py index 3b307e41cf2..e11f8eddfdb 100644 --- a/scripts/pylib/twister/twisterlib/testinstance.py +++ b/scripts/pylib/twister/twisterlib/testinstance.py @@ -56,13 +56,13 @@ def __init__(self, testsuite, platform, outdir): self.name = os.path.join(platform.name, testsuite.name) self.dut = None + if testsuite.detailed_test_id: - self.build_dir = os.path.join(outdir, platform.name, testsuite.name) + self.build_dir = os.path.join(outdir, platform.normalized_name, testsuite.name) else: # if suite is not in zephyr, keep only the part after ".." in reconstructed dir structure source_dir_rel = testsuite.source_dir_rel.rsplit(os.pardir+os.path.sep, 1)[-1] - self.build_dir = os.path.join(outdir, platform.name, source_dir_rel, testsuite.name) - + self.build_dir = os.path.join(outdir, platform.normalized_name, source_dir_rel, testsuite.name) self.run_id = self._get_run_id() self.domains = None diff --git a/scripts/pylib/twister/twisterlib/testplan.py b/scripts/pylib/twister/twisterlib/testplan.py index 782ceb0608c..5966e223180 100755 --- a/scripts/pylib/twister/twisterlib/testplan.py +++ b/scripts/pylib/twister/twisterlib/testplan.py @@ -18,6 +18,7 @@ import random import snippets from pathlib import Path +from argparse import Namespace logger = logging.getLogger('twister') logger.setLevel(logging.DEBUG) @@ -34,7 +35,7 @@ from twisterlib.testinstance import TestInstance from twisterlib.quarantine import Quarantine - +import list_boards from zephyr_module import parse_modules ZEPHYR_BASE = os.getenv("ZEPHYR_BASE") @@ -398,13 +399,25 @@ def info(what): def add_configurations(self): - for board_root in self.env.board_roots: - board_root = os.path.abspath(board_root) - logger.debug("Reading platform configuration files under %s..." % - board_root) + board_dirs = set() + # Create a list of board roots as defined by the build system in general + # Note, internally in twister a board root includes the `boards` folder + # but in Zephyr build system, the board root is without the `boards` in folder path. + board_roots = [Path(os.path.dirname(root)) for root in self.env.board_roots] + lb_args = Namespace(arch_roots=[Path(ZEPHYR_BASE)], soc_roots=[Path(ZEPHYR_BASE), + Path(ZEPHYR_BASE) / 'scripts' / 'pylib' / 'twister'], + board_roots=board_roots, board=None, board_dir=None) + v1_boards = list_boards.find_boards(lb_args) + v2_boards = list_boards.find_v2_boards(lb_args) + for b in v1_boards: + board_dirs.add(b.dir) + for b in v2_boards: + board_dirs.add(b.dir) + logger.debug("Reading platform configuration files under %s..." % self.env.board_roots) - platform_config = self.test_config.get('platforms', {}) - for file in glob.glob(os.path.join(board_root, "*", "*", "*.yaml")): + platform_config = self.test_config.get('platforms', {}) + for folder in board_dirs: + for file in glob.glob(os.path.join(folder, "*.yaml")): try: platform = Platform() platform.load(file) @@ -447,6 +460,7 @@ def add_configurations(self): platform_revision = copy.deepcopy(platform) revision = revision.replace("_", ".") platform_revision.name = f"{platform.name}@{revision}" + platform_revision.normalized_name = platform_revision.name.replace("/", "_") platform_revision.default = False self.platforms.append(platform_revision) diff --git a/scripts/schemas/arch-schema.yml b/scripts/schemas/arch-schema.yml new file mode 100644 index 00000000000..e1228ee1519 --- /dev/null +++ b/scripts/schemas/arch-schema.yml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023, Nordic Semiconductor ASA + +## A pykwalify schema for basic validation of the structure of a +## arch metadata YAML file. +## +# The archs.yml file is a simple list of key value pairs containing architectures +# and their location which is used by the build system. +type: map +mapping: + archs: + required: true + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + desc: Name of the arch + path: + required: true + type: str + desc: Location of the arch implementation relative to the archs.yml file. + comment: + required: false + type: str + desc: Free form comment with extra information regarding the arch. diff --git a/scripts/schemas/board-schema.yml b/scripts/schemas/board-schema.yml new file mode 100644 index 00000000000..6a9262bf8f5 --- /dev/null +++ b/scripts/schemas/board-schema.yml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023, Nordic Semiconductor ASA + +## A pykwalify schema for basic validation of the structure of a +## board metadata YAML file. +## +# The board.yml file is a simple list of key value pairs containing board +# information like: name, vendor, socs, variants. +schema;variant-schema: + required: false + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + cpucluster: + required: false + type: str + variants: + required: false + include: variant-schema + +schema;board-schema: + type: map + mapping: + name: + required: true + type: str + desc: Name of the board + vendor: + required: false + type: str + desc: SoC family of the SoC on the board. + revision: + required: false + type: map + mapping: + format: + required: true + type: str + enum: + ["major.minor.patch", "letter", "number", "custom"] + default: + required: false # This field is required when 'format' != 'custom' + type: str + exact: + required: false + type: bool + revisions: + required: false # This field is required when 'format' != 'custom' + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + socs: + required: true + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + variants: + include: variant-schema + +type: map +mapping: + board: + include: board-schema + boards: + type: seq + sequence: + - include: board-schema diff --git a/scripts/schemas/soc-schema.yml b/scripts/schemas/soc-schema.yml new file mode 100644 index 00000000000..dd62ee3c17d --- /dev/null +++ b/scripts/schemas/soc-schema.yml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023, Nordic Semiconductor ASA + +## A pykwalify schema for basic validation of the structure of a SoC +## metadata YAML file. +## +# The soc.yml file is a simple list of key value pairs containing SoCs +# located and the current structure level. +schema;cpucluster-schema: + required: false + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + +schema;soc-schema: + required: false + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + cpuclusters: + include: cpucluster-schema + +schema;series-schema: + required: false + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + socs: + required: false + include: soc-schema + +type: map +mapping: + family: + required: false + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + series: + include: series-schema + socs: + include: soc-schema + series: + include: series-schema + socs: + include: soc-schema + vendor: + required: false + type: str + desc: SoC series of the SoC. + This field is of informational use and can be used for filtering of SoCs. + comment: + required: false + type: str + desc: Free form comment with extra information regarding the SoC. diff --git a/scripts/snippets.py b/scripts/snippets.py index 78ab896e85b..48733ee3b55 100644 --- a/scripts/snippets.py +++ b/scripts/snippets.py @@ -159,11 +159,11 @@ def print_appends_for_board(self, board: str, appends: Appends): board_re = board[1:-1] self.print(f'''\ # Appends for board regular expression '{board_re}' -if("${{BOARD}}" MATCHES "^{board_re}$")''') +if("${{BOARD}}${{BOARD_IDENTIFIER}}" MATCHES "^{board_re}$")''') else: self.print(f'''\ # Appends for board '{board}' -if("${{BOARD}}" STREQUAL "{board}")''') +if("${{BOARD}}${{BOARD_IDENTIFIER}}" STREQUAL "{board}")''') self.print_appends(appends, 1) self.print('endif()') diff --git a/scripts/tests/twister_blackbox/test_report.py b/scripts/tests/twister_blackbox/test_report.py index 56d1bc3e098..5d120be727e 100644 --- a/scripts/tests/twister_blackbox/test_report.py +++ b/scripts/tests/twister_blackbox/test_report.py @@ -26,9 +26,9 @@ class TestReport: TESTDATA_1 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64'], + ['qemu_x86', 'mps2/an385'], [ - 'qemu_x86_64.xml', 'qemu_x86.xml', + 'qemu_x86.xml', 'mps2_an385.xml', 'testplan.json', 'twister.json', 'twister.log', 'twister_report.xml', 'twister_suite_report.xml', 'twister.xml' @@ -38,9 +38,9 @@ class TestReport: TESTDATA_2 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64'], + ['qemu_x86', 'mps2/an385'], [ - 'qemu_x86_64_TEST.xml', 'qemu_x86_TEST.xml', + 'mps2_an385_TEST.xml', 'qemu_x86_TEST.xml', 'twister_TEST.json', 'twister_TEST_report.xml', 'twister_TEST_suite_report.xml', 'twister_TEST.xml' ] @@ -49,7 +49,7 @@ class TestReport: TESTDATA_3 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64'], + ['qemu_x86', 'mps2/an385'], ['--report-name', 'abcd'], [ 'abcd.json', 'abcd_report.xml', @@ -58,20 +58,20 @@ class TestReport: ), ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64'], + ['qemu_x86', 'mps2/an385'], ['--report-name', '1234', '--platform-reports'], [ - 'qemu_x86_64.xml', 'qemu_x86.xml', + 'mps2_an385.xml', 'qemu_x86.xml', '1234.json', '1234_report.xml', '1234_suite_report.xml', '1234.xml' ] ), ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64'], + ['qemu_x86', 'mps2/an385'], ['--report-name', 'Final', '--platform-reports', '--report-suffix=Test'], [ - 'qemu_x86_64_Test.xml', 'qemu_x86_Test.xml', + 'mps2_an385_Test.xml', 'qemu_x86_Test.xml', 'Final_Test.json', 'Final_Test_report.xml', 'Final_Test_suite_report.xml', 'Final_Test.xml' ] @@ -182,7 +182,7 @@ def test_platform_reports(self, capfd, out_path, test_path, test_platforms, file pytest.fail(f"Unsupported file type: '{path}'") for f_platform in test_platforms: - platform_path = os.path.join(out_path, f_platform) + platform_path = os.path.join(out_path, f_platform.replace("/", "_")) assert os.path.exists(platform_path), f'file not found {f_platform}' assert str(sys_exit.value) == '0' diff --git a/scripts/utils/board_v1_to_v2.py b/scripts/utils/board_v1_to_v2.py new file mode 100644 index 00000000000..da84efb2ef9 --- /dev/null +++ b/scripts/utils/board_v1_to_v2.py @@ -0,0 +1,215 @@ +#!/usr/bin/env python +""" +Utility script to assist in the migration of a board from hardware model v1 +(HWMv1) to hardware model v2 (HWMv2). + +.. warning:: + This script is not a complete migration tool. It is meant to assist in the + migration process, but it does not handle all cases. + +This script requires the following arguments: + +- ``-b|--board``: The name of the board to migrate. +- ``-g|--group``: The group the board belongs to. This is used to group a set of + boards in the same folder. In HWMv2, the boards are no longer organized by + architecture. +- ``-v|--vendor``: The vendor name. +- ``-s|--soc``: The SoC name. + +In some cases, the new board name will differ from the old board name. For +example, the old board name may have the SoC name as a suffix, while in HWMv2, +this is no longer needed. In such cases, ``-n|--new-board`` needs to be +provided. + +For boards with variants, ``--variants`` needs to be provided. + +For out-of-tree boards, provide ``--board-root`` pointing to the custom board +root. + +Copyright (c) 2023 Nordic Semiconductor ASA +SPDX-License-Identifier: Apache-2.0 +""" + +import argparse +from pathlib import Path +import re +import sys + +import ruamel.yaml + + +ZEPHYR_BASE = Path(__file__).parents[2] + + +def board_v1_to_v2(board_root, board, new_board, group, vendor, soc, variants): + try: + board_path = next(board_root.glob(f"boards/*/{board}")) + except StopIteration: + sys.exit(f"Board not found: {board}") + + new_board_path = board_root / "boards" / group / new_board + if new_board_path.exists(): + print("New board already exists, updating board with additional SoC") + if not soc: + sys.exit("No SoC provided") + + new_board_path.mkdir(parents=True, exist_ok=True) + + print("Moving files to the new board folder...") + for f in board_path.iterdir(): + f_new = new_board_path / f.name + if f_new.exists(): + print(f"Skipping existing file: {f_new}") + continue + f.rename(f_new) + + print("Creating or updating board.yaml...") + board_settings_file = new_board_path / "board.yml" + if not board_settings_file.exists(): + board_settings = { + "board": { + "name": new_board, + "vendor": vendor, + "socs": [] + } + } + else: + with open(board_settings_file) as f: + yaml = ruamel.yaml.YAML(typ='safe', pure=True) + board_settings = yaml.load(f) # pylint: disable=assignment-from-no-return + + soc = {"name": soc} + if variants: + soc["variants"] = [{"name": variant} for variant in variants] + + board_settings["board"]["socs"].append(soc) + + yaml = ruamel.yaml.YAML() + yaml.indent(sequence=4, offset=2) + with open(board_settings_file, "w") as f: + yaml.dump(board_settings, f) + + print(f"Updating {board}_defconfig...") + board_defconfig_file = new_board_path / f"{board}_defconfig" + with open(board_defconfig_file) as f: + board_soc_settings = [] + board_defconfig = "" + + dropped_line = False + for line in f.readlines(): + m = re.match(r"^CONFIG_BOARD_.*$", line) + if m: + dropped_line = True + continue + + m = re.match(r"^CONFIG_(SOC_[A-Z0-9_]+).*$", line) + if m: + dropped_line = True + if not re.match(r"^CONFIG_SOC_SERIES_.*$", line): + board_soc_settings.append(m.group(1)) + continue + + if dropped_line and re.match(r"^$", line): + continue + + dropped_line = False + board_defconfig += line + + with open(board_defconfig_file, "w") as f: + f.write(board_defconfig) + + print("Updating Kconfig.defconfig...") + board_kconfig_defconfig_file = new_board_path / "Kconfig.defconfig" + with open(board_kconfig_defconfig_file) as f: + board_kconfig_defconfig = "" + has_kconfig_defconfig_entries = False + + in_board = False + for line in f.readlines(): + # drop "config BOARD" entry from Kconfig.defconfig + m = re.match(r"^config BOARD$", line) + if m: + in_board = True + continue + + if in_board and re.match(r"^\s+.*$", line): + continue + + in_board = False + + m = re.match(r"^config .*$", line) + if m: + has_kconfig_defconfig_entries = True + + m = re.match(rf"^(.*)BOARD_{board.upper()}(.*)$", line) + if m: + board_kconfig_defconfig += ( + m.group(1) + "BOARD_" + new_board.upper() + m.group(2) + "\n" + ) + continue + + board_kconfig_defconfig += line + + if has_kconfig_defconfig_entries: + with open(board_kconfig_defconfig_file, "w") as f: + f.write(board_kconfig_defconfig) + else: + print("Removing empty Kconfig.defconfig after update...") + board_kconfig_defconfig_file.unlink() + + print(f"Creating or updating Kconfig.{new_board}...") + board_kconfig_file = new_board_path / "Kconfig.board" + copyright = None + with open(board_kconfig_file) as f: + for line in f.readlines(): + if "Copyright" in line: + copyright = line + new_board_kconfig_file = new_board_path / f"Kconfig.{new_board}" + header = "# SPDX-License-Identifier: Apache-2.0\n" + if copyright is not None: + header = copyright + header + selects = "\n\t" + "\n\t".join(["select " + setting for setting in board_soc_settings]) + "\n" + if not new_board_kconfig_file.exists(): + with open(new_board_kconfig_file, "w") as f: + f.write( + header + + f"\nconfig BOARD_{new_board.upper()}{selects}" + ) + else: + with open(new_board_kconfig_file, "a") as f: + f.write(selects) + + print("Removing old Kconfig.board...") + board_kconfig_file.unlink() + + print("Conversion done!") + + +if __name__ == "__main__": + parser = argparse.ArgumentParser(allow_abbrev=False) + + parser.add_argument( + "--board-root", + type=Path, + default=ZEPHYR_BASE, + help="Board root", + ) + + parser.add_argument("-b", "--board", type=str, required=True, help="Board name") + parser.add_argument("-n", "--new-board", type=str, help="New board name") + parser.add_argument("-g", "--group", type=str, required=True, help="Board group") + parser.add_argument("-v", "--vendor", type=str, required=True, help="Vendor name") + parser.add_argument("-s", "--soc", type=str, required=True, help="Board SoC") + parser.add_argument("--variants", nargs="+", default=[], help="Board variants") + + args = parser.parse_args() + + board_v1_to_v2( + args.board_root, + args.board, + args.new_board or args.board, + args.group, + args.vendor, + args.soc, + args.variants, + ) diff --git a/scripts/west_commands/boards.py b/scripts/west_commands/boards.py index 39238756f61..d7fc2838bc2 100644 --- a/scripts/west_commands/boards.py +++ b/scripts/west_commands/boards.py @@ -49,6 +49,7 @@ def do_add_parser(self, parser_adder): The following arguments are available: - name: board name + - identifiers: board identifiers - arch: board architecture - dir: directory that contains the board definition ''')) @@ -72,6 +73,7 @@ def do_run(self, args, _): name_re = None args.arch_roots = [ZEPHYR_BASE] + args.soc_roots = [ZEPHYR_BASE] modules_board_roots = [ZEPHYR_BASE] for module in zephyr_module.parse_modules(ZEPHYR_BASE, self.manifest): @@ -85,4 +87,10 @@ def do_run(self, args, _): if name_re is not None and not name_re.search(board.name): continue log.inf(args.format.format(name=board.name, arch=board.arch, - dir=board.dir)) + dir=board.dir, hwm=board.hwm, identifiers='')) + + for board in list_boards.find_v2_boards(args): + if name_re is not None and not name_re.search(board.name): + continue + log.inf(args.format.format(name=board.name, dir=board.dir, hwm=board.hwm, + identifiers=list_boards.board_v2_identifiers_csv(board))) diff --git a/scripts/west_commands/completion/west-completion.bash b/scripts/west_commands/completion/west-completion.bash index ca3f5669d05..2ccc4446ad3 100644 --- a/scripts/west_commands/completion/west-completion.bash +++ b/scripts/west_commands/completion/west-completion.bash @@ -392,7 +392,8 @@ __set_comp_west_projs() __set_comp_west_boards() { - __set_comp "$(__west_x boards --format={name} "$@")" + boards="$(__west_x boards --format={identifiers} "$@")\n$(__west_x boards --format={name} "$@")" + __set_comp ${boards//,/\ } } __comp_west_west() @@ -660,6 +661,7 @@ __comp_west_boards() local dir_opts=" --arch-root --board-root + --soc-root " all_opts="$dir_opts $other_opts" diff --git a/scripts/west_commands/completion/west-completion.fish b/scripts/west_commands/completion/west-completion.fish index 92dbc65c800..33c6942dd8e 100644 --- a/scripts/west_commands/completion/west-completion.fish +++ b/scripts/west_commands/completion/west-completion.fish @@ -196,11 +196,21 @@ function __zephyr_west_complete_help end function __zephyr_west_complete_board + # HWMv1 set -l boards (west 2>/dev/null boards --format="{name} {arch}") for board in $boards set -l b (string split " " $board) printf "%s\n" $b[1]\t"$b[2]" end + + # HWMv2 + set -l boards (west 2>/dev/null boards --format="{identifiers}") + for board in $boards + set -l b (string split "," $board) + for variant in $b + printf "%s\n" $variant[1] + end + end end # disable file completion, if an option need it, it should use '--force-files' @@ -292,6 +302,7 @@ complete -c west -n "__zephyr_west_seen_subcommand_from boards" -o f -l format - complete -c west -n "__zephyr_west_seen_subcommand_from boards" -o n -l name -d "name regex" complete -c west -n "__zephyr_west_seen_subcommand_from boards" -l arch-root -xa "(__zephyr_west_complete_directories)" -d "add an arch root" complete -c west -n "__zephyr_west_seen_subcommand_from boards" -l board-root -xa "(__zephyr_west_complete_directories)" -d "add a board root" +complete -c west -n "__zephyr_west_seen_subcommand_from boards" -l soc-root -xa "(__zephyr_west_complete_directories)" -d "add a soc root" # build complete -c west -n "__zephyr_west_use_subcommand; and __zephyr_west_check_if_in_workspace" -ra build -d "compile a Zephyr application" diff --git a/scripts/west_commands/completion/west-completion.zsh b/scripts/west_commands/completion/west-completion.zsh index b3a881288c0..000b43a87b3 100644 --- a/scripts/west_commands/completion/west-completion.zsh +++ b/scripts/west_commands/completion/west-completion.zsh @@ -102,7 +102,11 @@ _get_west_projs() { } _get_west_boards() { - _west_boards=($(__west_x boards --format={name})) + _west_boards="$(__west_x boards --format={identifiers})\n$(__west_x boards --format={name})" + _west_boards=${_west_boards//$'\n'/\ } + _west_boards=${_west_boards//,/\ } + _west_boards=(${(@s/ /)_west_boards}) + _describe 'boards' _west_boards } @@ -214,6 +218,7 @@ _west_boards() { {-n,--name}'[name regex]:regex:' '*--arch-root[Add an arch root]:arch root:_directories' '*--board-root[Add a board root]:board root:_directories' + '*--soc-root[Add a soc root]:soc root:_directories' ) _arguments -S $opts diff --git a/scripts/west_commands/runners/core.py b/scripts/west_commands/runners/core.py index 9b3ca51d900..21a60edc1a0 100644 --- a/scripts/west_commands/runners/core.py +++ b/scripts/west_commands/runners/core.py @@ -362,7 +362,7 @@ class ZephyrBinaryRunner(abc.ABC): This class provides an API for these commands. Every subclass is called a 'runner' for short. Each runner has a name (like 'pyocd'), and declares commands it can handle (like - 'flash'). Boards (like 'nrf52dk_nrf52832') declare which runner(s) + 'flash'). Boards (like 'nrf52dk/nrf52832') declare which runner(s) are compatible with them to the Zephyr build system, along with information on how to configure the runner to work with the board. diff --git a/scripts/west_commands/runners/intel_adsp.py b/scripts/west_commands/runners/intel_adsp.py index f7587331dc3..24552c8f61c 100644 --- a/scripts/west_commands/runners/intel_adsp.py +++ b/scripts/west_commands/runners/intel_adsp.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022 Intel Corporation +# Copyright (c) 2022-2024 Intel Corporation # # SPDX-License-Identifier: Apache-2.0 @@ -14,7 +14,7 @@ from runners.core import ZephyrBinaryRunner, RunnerCaps from zephyr_ext_common import ZEPHYR_BASE -DEFAULT_CAVSTOOL='soc/xtensa/intel_adsp/tools/cavstool_client.py' +DEFAULT_CAVSTOOL='soc/intel/intel_adsp/tools/cavstool_client.py' class SignParamError(argparse.Action): 'User-friendly feedback when trying to sign with west flash' @@ -78,7 +78,7 @@ def do_create(cls, cfg, args): def do_run(self, command, **kwargs): self.logger.info('Starting Intel ADSP runner') - if re.search("intel_adsp", self.platform): + if re.search("adsp", self.platform): self.require(self.cavstool) self.flash(**kwargs) else: diff --git a/share/sysbuild/cmake/modules/sysbuild_extensions.cmake b/share/sysbuild/cmake/modules/sysbuild_extensions.cmake index 9de1ea0f47f..05cde48a0e0 100644 --- a/share/sysbuild/cmake/modules/sysbuild_extensions.cmake +++ b/share/sysbuild/cmake/modules/sysbuild_extensions.cmake @@ -146,9 +146,9 @@ function(sysbuild_cache) endif() endforeach() if(DEFINED BOARD_REVISION) - list(APPEND sysbuild_cache_strings "BOARD:STRING=${BOARD}@${BOARD_REVISION}\n") + list(APPEND sysbuild_cache_strings "BOARD:STRING=${BOARD}@${BOARD_REVISION}${BOARD_IDENTIFIER}\n") else() - list(APPEND sysbuild_cache_strings "BOARD:STRING=${BOARD}\n") + list(APPEND sysbuild_cache_strings "BOARD:STRING=${BOARD}${BOARD_IDENTIFIER}\n") endif() list(APPEND sysbuild_cache_strings "SYSBUILD_NAME:STRING=${SB_CACHE_APPLICATION}\n") diff --git a/snippets/nordic-ppr/snippet.yml b/snippets/nordic-ppr/snippet.yml index 9e1f20bb757..ce8c3437c4c 100644 --- a/snippets/nordic-ppr/snippet.yml +++ b/snippets/nordic-ppr/snippet.yml @@ -3,6 +3,6 @@ append: EXTRA_DTC_OVERLAY_FILE: nordic-ppr.overlay boards: - nrf54h20pdk_nrf54h20_cpuapp: + nrf54h20pdk/nrf54h20/cpuapp: append: EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20pdk_nrf54h20_cpuapp.overlay diff --git a/snippets/xen_dom0/boards/rcar_h3ulcb_ca57.overlay b/snippets/xen_dom0/boards/rcar_h3ulcb_r8a77951_a57.overlay similarity index 100% rename from snippets/xen_dom0/boards/rcar_h3ulcb_ca57.overlay rename to snippets/xen_dom0/boards/rcar_h3ulcb_r8a77951_a57.overlay diff --git a/snippets/xen_dom0/boards/rcar_salvator_xs_m3.overlay b/snippets/xen_dom0/boards/rcar_salvator_xs.overlay similarity index 100% rename from snippets/xen_dom0/boards/rcar_salvator_xs_m3.overlay rename to snippets/xen_dom0/boards/rcar_salvator_xs.overlay diff --git a/snippets/xen_dom0/snippet.yml b/snippets/xen_dom0/snippet.yml index cb6fddeaccd..84d13bf77c1 100644 --- a/snippets/xen_dom0/snippet.yml +++ b/snippets/xen_dom0/snippet.yml @@ -4,12 +4,12 @@ append: EXTRA_CONF_FILE: xen_dom0.conf boards: - qemu_cortex_a53: + qemu_cortex_a53/qemu_cortex_a53: append: EXTRA_DTC_OVERLAY_FILE: boards/qemu_cortex_a53.overlay - rcar_h3ulcb_ca57: + rcar_h3ulcb/r8a77951/a57: append: - EXTRA_DTC_OVERLAY_FILE: boards/rcar_h3ulcb_ca57.overlay - rcar_salvator_xs_m3: + EXTRA_DTC_OVERLAY_FILE: boards/rcar_h3ulcb_r8a77951_a57.overlay + rcar_salvator_xs/r8a77961: append: - EXTRA_DTC_OVERLAY_FILE: boards/rcar_salvator_xs_m3.overlay + EXTRA_DTC_OVERLAY_FILE: boards/rcar_salvator_xs.overlay diff --git a/soc/CMakeLists.txt b/soc/CMakeLists.txt index d55bd63f496..f9d754cfbb3 100644 --- a/soc/CMakeLists.txt +++ b/soc/CMakeLists.txt @@ -11,8 +11,38 @@ unset(_SOC_IS_IN_TREE) add_subdirectory(common) -if(EXISTS ${SOC_DIR}/${ARCH}/CMakeLists.txt) - add_subdirectory(${SOC_DIR}/${ARCH} soc/${ARCH}) -else() - add_subdirectory(${SOC_DIR}/${ARCH}/${SOC_PATH} soc/${ARCH}/${SOC_PATH}) +if(HWMv1) + if(EXISTS ${SOC_DIR}/${ARCH}/CMakeLists.txt) + add_subdirectory(${SOC_DIR}/${ARCH} soc/${ARCH}) + else() + add_subdirectory(${SOC_DIR}/${ARCH}/${SOC_PATH} soc/${ARCH}/${SOC_PATH}) + endif() +elseif(HWMv2) + # Below is inclusion of HWMv2 SoC CMake lists. + string(TOUPPER SOC_FAMILY_${SOC_FAMILY}_DIR family_setting_dir) + string(TOUPPER SOC_SERIES_${SOC_SERIES}_DIR series_setting_dir) + string(TOUPPER SOC_${SOC_NAME}_DIR soc_setting_dir) + + if(DEFINED ${soc_setting_dir}) + add_subdirectory(${${soc_setting_dir}} soc/${SOC_NAME}) + elseif(DEFINED ${series_setting_dir}) + add_subdirectory(${${series_setting_dir}} soc/${SOC_SERIES}) + elseif(DEFINED ${family_setting_dir}) + add_subdirectory(${${family_setting_dir}} soc/${SOC_FAMILY}) + else() + message(FATAL_ERROR "No CMakeLists.txt file found for SoC: ${SOC_NAME}, " + "series: ${SOC_SERIES}, family: ${SOC_FAMILY}") + endif() + + # Include all SoC roots except Zephyr, as we are already in the Zephyr SoC root. + set(local_soc_root ${SOC_ROOT}) + list(REMOVE_ITEM local_soc_root ${ZEPHYR_BASE}) + foreach(root ${local_soc_root}) + cmake_path(GET root FILENAME name) + # A SoC root for HWMv1 may not contain a CMakeLists.txt file on this so + # let's check for existence before including. + if(EXISTS ${root}/soc/CMakeLists.txt) + add_subdirectory(${root}/soc soc/${name}) + endif() + endforeach() endif() diff --git a/soc/Kconfig b/soc/Kconfig index 33c2d0c29a4..0063021c3e3 100644 --- a/soc/Kconfig +++ b/soc/Kconfig @@ -1,21 +1,22 @@ # SPDX-License-Identifier: Apache-2.0 -choice - prompt "SoC/CPU/Configuration Selection" +# Only v1 model has choice for SoC selection, therefore the optional source +# Sourced here and not in Kconfig.v1 to keep current SoC/CPU selection menu +# side-by-side with "Hardware Configuration" in the menu structure. +orsource "Kconfig.$(HWM_SCHEME).choice" -# This loads custom SoC root Kconfig (only available if custom SoC root are defined) -osource "$(KCONFIG_BINARY_DIR)/Kconfig.soc" -# This loads Zephyr base SoC root Kconfig -osource "soc/$(ARCH)/*/Kconfig.soc" +menu "Hardware Configuration" -endchoice +rsource "Kconfig.$(HWM_SCHEME)" -menu "Hardware Configuration" -# This loads custom SoC root Kconfig (only available if custom SoC root are defined) -osource "$(KCONFIG_BINARY_DIR)/Kconfig.soc.arch" -# This loads Zephyr base SoC Kconfigs -osource "soc/$(ARCH)/Kconfig" -osource "soc/$(ARCH)/*/Kconfig" +# This loads Zephyr base SoC Kconfigs for both hw model v1 and v2 +osource "soc/soc_legacy/$(ARCH)/Kconfig" + +# Source Zephyr Kconfig specifics from SoC roots. +osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig" + +# Source common Kconfig file +osource "soc/common/Kconfig" module = SOC module-str = SOC @@ -44,10 +45,6 @@ config SOC_COMPATIBLE_NRF5340_CPUNET config SOC_COMPATIBLE_NRF5340_CPUAPP bool -# -# SOC_*_LD: SoC specific Linker script additions -# - config SOC_DEPRECATED_RELEASE string help diff --git a/soc/Kconfig.v1 b/soc/Kconfig.v1 new file mode 100644 index 00000000000..f3762b8c6e2 --- /dev/null +++ b/soc/Kconfig.v1 @@ -0,0 +1,27 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +config SOC + string + help + SoC name. The value of this setting must be defined by the selected + SoC for hw model v2. + +config SOC_SERIES + string + help + SoC series. The value of this setting must be defined by the selected + SoC if the SoC belongs to a common series. + +config SOC_FAMILY + string + help + SoC family. The value of this setting must be defined by the selected + SoC if the SoC belongs to a SoC family. Usually a SoC family also + indicates the vendor of the SoC. + +# This loads custom SoC root Kconfig (only available if custom SoC root are defined) +osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig.soc.arch" +# This loads Zephyr base SoC Kconfigs +osource "soc/soc_legacy/$(ARCH)/*/Kconfig" diff --git a/soc/Kconfig.v1.choice b/soc/Kconfig.v1.choice new file mode 100644 index 00000000000..f3424f71196 --- /dev/null +++ b/soc/Kconfig.v1.choice @@ -0,0 +1,13 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "SoC/CPU/Configuration Selection" + +# This loads custom SoC root Kconfig (only available if custom SoC root are defined) +osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig.soc.choice" +# This loads Zephyr base SoC scheme v1 root Kconfig +osource "soc/soc_legacy/$(ARCH)/*/Kconfig.soc" + +endchoice diff --git a/soc/Kconfig.v2 b/soc/Kconfig.v2 new file mode 100644 index 00000000000..40008123a02 --- /dev/null +++ b/soc/Kconfig.v2 @@ -0,0 +1,39 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +# Load all SoCs. +# SoCs that has transitioned to SoC scheme v2 are promptless, and thus +# unselectable by the user or through configuration files. +# +# SoC that are still using scheme v1 are still having a prompt but is loaded as +# they offer board maintainers the possibility to use board scheme v2. + +config SOC + string + help + SoC name. The value of this setting must be defined by the selected + SoC for hw model v2. + +config SOC_SERIES + string + help + SoC series. The value of this setting must be defined by the selected + SoC if the SoC belongs to a common series. + +config SOC_FAMILY + string + help + SoC family. The value of this setting must be defined by the selected + SoC if the SoC belongs to a SoC family. Usually a SoC family also + indicates the vendor of the SoC. + +config SOC_PART_NUMBER + string + help + This string holds the full part number of the SoC. It is a hidden option + that you should not set directly. The part number selection choice defines + the default value for this string. + +# Source all Kconfig HWMv2 from SoC roots. +source "$(KCONFIG_BINARY_DIR)/soc/Kconfig.soc" diff --git a/soc/altr/qemu_nios2/CMakeLists.txt b/soc/altr/qemu_nios2/CMakeLists.txt new file mode 100644 index 00000000000..8afc2e70196 --- /dev/null +++ b/soc/altr/qemu_nios2/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/altr/qemu_nios2/Kconfig b/soc/altr/qemu_nios2/Kconfig new file mode 100644 index 00000000000..3d64aa15b77 --- /dev/null +++ b/soc/altr/qemu_nios2/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_NIOS2 + select NIOS2 + select HAS_MUL_INSTRUCTION + select HAS_DIV_INSTRUCTION + select HAS_MULX_INSTRUCTION diff --git a/soc/altr/qemu_nios2/Kconfig.defconfig b/soc/altr/qemu_nios2/Kconfig.defconfig new file mode 100644 index 00000000000..7584fb7af4b --- /dev/null +++ b/soc/altr/qemu_nios2/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_QEMU_NIOS2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 50000000 + +endif diff --git a/soc/altr/qemu_nios2/Kconfig.soc b/soc/altr/qemu_nios2/Kconfig.soc new file mode 100644 index 00000000000..1455b3ae7ac --- /dev/null +++ b/soc/altr/qemu_nios2/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_NIOS2 + bool + +config SOC + default "qemu_nios2" if SOC_QEMU_NIOS2 diff --git a/soc/nios2/nios2-qemu/include/layout.h b/soc/altr/qemu_nios2/include/layout.h similarity index 100% rename from soc/nios2/nios2-qemu/include/layout.h rename to soc/altr/qemu_nios2/include/layout.h diff --git a/soc/nios2/nios2-qemu/include/linker.h b/soc/altr/qemu_nios2/include/linker.h similarity index 100% rename from soc/nios2/nios2-qemu/include/linker.h rename to soc/altr/qemu_nios2/include/linker.h diff --git a/soc/nios2/nios2-qemu/include/system.h b/soc/altr/qemu_nios2/include/system.h similarity index 100% rename from soc/nios2/nios2-qemu/include/system.h rename to soc/altr/qemu_nios2/include/system.h diff --git a/soc/nios2/nios2-qemu/linker.ld b/soc/altr/qemu_nios2/linker.ld similarity index 100% rename from soc/nios2/nios2-qemu/linker.ld rename to soc/altr/qemu_nios2/linker.ld diff --git a/soc/nios2/nios2-qemu/soc.h b/soc/altr/qemu_nios2/soc.h similarity index 100% rename from soc/nios2/nios2-qemu/soc.h rename to soc/altr/qemu_nios2/soc.h diff --git a/soc/altr/qemu_nios2/soc.yml b/soc/altr/qemu_nios2/soc.yml new file mode 100644 index 00000000000..414892bcc3f --- /dev/null +++ b/soc/altr/qemu_nios2/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: qemu_nios2 diff --git a/soc/altr/zephyr_nios2f/CMakeLists.txt b/soc/altr/zephyr_nios2f/CMakeLists.txt new file mode 100644 index 00000000000..3277239a967 --- /dev/null +++ b/soc/altr/zephyr_nios2f/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2016 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/altr/zephyr_nios2f/Kconfig b/soc/altr/zephyr_nios2f/Kconfig new file mode 100644 index 00000000000..6aa5654f7b5 --- /dev/null +++ b/soc/altr/zephyr_nios2f/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2016 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ZEPHYR_NIOS2F + select NIOS2 + select HAS_MUL_INSTRUCTION + select HAS_DIV_INSTRUCTION diff --git a/soc/altr/zephyr_nios2f/Kconfig.defconfig b/soc/altr/zephyr_nios2f/Kconfig.defconfig new file mode 100644 index 00000000000..5f021107cac --- /dev/null +++ b/soc/altr/zephyr_nios2f/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2016 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ZEPHYR_NIOS2F + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 50000000 + +config ALTERA_AVALON_SYSID + def_bool y + +config ALTERA_AVALON_QSPI + def_bool y + depends on SOC_FLASH_NIOS2_QSPI + +config ALTERA_AVALON_I2C + def_bool y + depends on I2C_NIOS2 + +config ALTERA_AVALON_MSGDMA + def_bool y + depends on DMA_NIOS2_MSGDMA + +endif # SOC_ZEPHYR_NIOS2F diff --git a/soc/altr/zephyr_nios2f/Kconfig.soc b/soc/altr/zephyr_nios2f/Kconfig.soc new file mode 100644 index 00000000000..b976d0b4795 --- /dev/null +++ b/soc/altr/zephyr_nios2f/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2016 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ZEPHYR_NIOS2F + bool + +config SOC + default "zephyr_nios2f" if SOC_ZEPHYR_NIOS2F diff --git a/soc/nios2/nios2f-zephyr/cpu/README b/soc/altr/zephyr_nios2f/cpu/README similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/README rename to soc/altr/zephyr_nios2f/cpu/README diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qpf b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qpf similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qpf rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qpf diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qsf b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsf similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qsf rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsf diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qsys b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsys similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qsys rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsys diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sopcinfo b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sopcinfo similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sopcinfo rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sopcinfo diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da_top.v b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da_top.v similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da_top.v rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da_top.v diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_timing.sdc b/soc/altr/zephyr_nios2f/cpu/ghrd_timing.sdc similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_timing.sdc rename to soc/altr/zephyr_nios2f/cpu/ghrd_timing.sdc diff --git a/soc/nios2/nios2f-zephyr/include/layout.h b/soc/altr/zephyr_nios2f/include/layout.h similarity index 100% rename from soc/nios2/nios2f-zephyr/include/layout.h rename to soc/altr/zephyr_nios2f/include/layout.h diff --git a/soc/nios2/nios2f-zephyr/include/linker.h b/soc/altr/zephyr_nios2f/include/linker.h similarity index 100% rename from soc/nios2/nios2f-zephyr/include/linker.h rename to soc/altr/zephyr_nios2f/include/linker.h diff --git a/soc/nios2/nios2f-zephyr/include/system.h b/soc/altr/zephyr_nios2f/include/system.h similarity index 100% rename from soc/nios2/nios2f-zephyr/include/system.h rename to soc/altr/zephyr_nios2f/include/system.h diff --git a/soc/nios2/nios2f-zephyr/linker.ld b/soc/altr/zephyr_nios2f/linker.ld similarity index 100% rename from soc/nios2/nios2f-zephyr/linker.ld rename to soc/altr/zephyr_nios2f/linker.ld diff --git a/soc/nios2/nios2f-zephyr/soc.h b/soc/altr/zephyr_nios2f/soc.h similarity index 100% rename from soc/nios2/nios2f-zephyr/soc.h rename to soc/altr/zephyr_nios2f/soc.h diff --git a/soc/altr/zephyr_nios2f/soc.yml b/soc/altr/zephyr_nios2f/soc.yml new file mode 100644 index 00000000000..156e865a4cb --- /dev/null +++ b/soc/altr/zephyr_nios2f/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: zephyr_nios2f diff --git a/soc/arm/ambiq/CMakeLists.txt b/soc/ambiq/CMakeLists.txt similarity index 100% rename from soc/arm/ambiq/CMakeLists.txt rename to soc/ambiq/CMakeLists.txt diff --git a/soc/ambiq/Kconfig b/soc/ambiq/Kconfig new file mode 100644 index 00000000000..ec2fa612922 --- /dev/null +++ b/soc/ambiq/Kconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro + +if SOC_FAMILY_AMBIQ + +rsource "*/Kconfig" + +endif # SOC_FAMILY_AMBIQ diff --git a/soc/ambiq/Kconfig.defconfig b/soc/ambiq/Kconfig.defconfig new file mode 100644 index 00000000000..2d0efbe5424 --- /dev/null +++ b/soc/ambiq/Kconfig.defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro + +if SOC_FAMILY_AMBIQ + +rsource "*/Kconfig.defconfig" + +config CORTEX_M_SYSTICK + default n if AMBIQ_STIMER_TIMER + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 if AMBIQ_STIMER_TIMER + +endif # SOC_FAMILY_AMBIQ diff --git a/soc/ambiq/Kconfig.soc b/soc/ambiq/Kconfig.soc new file mode 100644 index 00000000000..ba6d5302abb --- /dev/null +++ b/soc/ambiq/Kconfig.soc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro + +config SOC_FAMILY_AMBIQ + bool + +config SOC_FAMILY + default "ambiq" if SOC_FAMILY_AMBIQ + +rsource "*/Kconfig.soc" diff --git a/soc/ambiq/apollo4x/CMakeLists.txt b/soc/ambiq/apollo4x/CMakeLists.txt new file mode 100644 index 00000000000..19f7fa032af --- /dev/null +++ b/soc/ambiq/apollo4x/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Antmicro +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ambiq/apollo4x/Kconfig b/soc/ambiq/apollo4x/Kconfig new file mode 100644 index 00000000000..a224512cd08 --- /dev/null +++ b/soc/ambiq/apollo4x/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro +# Copyright (c) 2023 Ambiq Micro Inc. + +config SOC_SERIES_APOLLO4X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_SWO + select AMBIQ_HAL diff --git a/soc/ambiq/apollo4x/Kconfig.defconfig b/soc/ambiq/apollo4x/Kconfig.defconfig new file mode 100644 index 00000000000..182adf42cd5 --- /dev/null +++ b/soc/ambiq/apollo4x/Kconfig.defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro + +if SOC_SERIES_APOLLO4X + +rsource "Kconfig.defconfig.apollo4*" + +endif # SOC_SERIES_APOLLO4X diff --git a/soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4p b/soc/ambiq/apollo4x/Kconfig.defconfig.apollo4p similarity index 100% rename from soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4p rename to soc/ambiq/apollo4x/Kconfig.defconfig.apollo4p diff --git a/soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue b/soc/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue similarity index 100% rename from soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue rename to soc/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue diff --git a/soc/ambiq/apollo4x/Kconfig.soc b/soc/ambiq/apollo4x/Kconfig.soc new file mode 100644 index 00000000000..fe06f28a7a8 --- /dev/null +++ b/soc/ambiq/apollo4x/Kconfig.soc @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro +# Copyright (c) 2023 Ambiq Micro Inc. + +config SOC_SERIES_APOLLO4X + bool + select SOC_FAMILY_AMBIQ + help + Apollo4 Series MCU + +config SOC_APOLLO4P + bool + select SOC_SERIES_APOLLO4X + help + Apollo4P + +config SOC_APOLLO4P_BLUE + bool + select SOC_SERIES_APOLLO4X + help + Apollo4 Blue Plus + +config SOC_SERIES + default "apollo4x" if SOC_SERIES_APOLLO4X + +config SOC + default "apollo4p" if SOC_APOLLO4P + default "apollo4p_blue" if SOC_APOLLO4P_BLUE diff --git a/soc/arm/ambiq/apollo4x/pinctrl_soc.h b/soc/ambiq/apollo4x/pinctrl_soc.h similarity index 100% rename from soc/arm/ambiq/apollo4x/pinctrl_soc.h rename to soc/ambiq/apollo4x/pinctrl_soc.h diff --git a/soc/arm/ambiq/apollo4x/soc.c b/soc/ambiq/apollo4x/soc.c similarity index 100% rename from soc/arm/ambiq/apollo4x/soc.c rename to soc/ambiq/apollo4x/soc.c diff --git a/soc/arm/ambiq/apollo4x/soc.h b/soc/ambiq/apollo4x/soc.h similarity index 100% rename from soc/arm/ambiq/apollo4x/soc.h rename to soc/ambiq/apollo4x/soc.h diff --git a/soc/ambiq/soc.yml b/soc/ambiq/soc.yml new file mode 100644 index 00000000000..2fd2f06529f --- /dev/null +++ b/soc/ambiq/soc.yml @@ -0,0 +1,7 @@ +family: +- name: ambiq + series: + - name: apollo4x + socs: + - name: apollo4p + - name: apollo4p_blue diff --git a/soc/riscv/andes_v5/CMakeLists.txt b/soc/andestech/CMakeLists.txt similarity index 100% rename from soc/riscv/andes_v5/CMakeLists.txt rename to soc/andestech/CMakeLists.txt diff --git a/soc/andestech/Kconfig b/soc/andestech/Kconfig new file mode 100644 index 00000000000..f050c5b55db --- /dev/null +++ b/soc/andestech/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ANDES_V5 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ANDES_V5 diff --git a/soc/andestech/Kconfig.defconfig b/soc/andestech/Kconfig.defconfig new file mode 100644 index 00000000000..1560bc1c4fd --- /dev/null +++ b/soc/andestech/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ANDES_V5 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_ANDES_V5 diff --git a/soc/andestech/Kconfig.soc b/soc/andestech/Kconfig.soc new file mode 100644 index 00000000000..56bfb37f633 --- /dev/null +++ b/soc/andestech/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ANDES_V5 + bool + +config SOC_FAMILY + default "andes_v5" if SOC_FAMILY_ANDES_V5 + +rsource "*/Kconfig.soc" diff --git a/soc/riscv/andes_v5/ae350/CMakeLists.txt b/soc/andestech/ae350/CMakeLists.txt similarity index 100% rename from soc/riscv/andes_v5/ae350/CMakeLists.txt rename to soc/andestech/ae350/CMakeLists.txt diff --git a/soc/andestech/ae350/Kconfig b/soc/andestech/ae350/Kconfig new file mode 100644 index 00000000000..1a0a2443492 --- /dev/null +++ b/soc/andestech/ae350/Kconfig @@ -0,0 +1,122 @@ +# Copyright (c) 2021 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ANDES_AE350 + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + +config SOC_ANDES_AE350 + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select RISCV_PMP + +if SOC_SERIES_ANDES_AE350 + +choice +prompt "Base CPU ISA options" +default RV32I_CPU + +config RV32I_CPU + bool "RISCV32 CPU ISA" + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + +config RV32E_CPU + bool "RISCV32E CPU ISA" + select RISCV_ISA_RV32E + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + +config RV64I_CPU + bool "RISCV64 CPU ISA" + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select 64BIT + +endchoice + +choice +prompt "FPU options" +default NO_FPU + +config NO_FPU + bool "No FPU" + +config SINGLE_PRECISION_FPU + bool "Single precision FPU" + select CPU_HAS_FPU + +config DOUBLE_PRECISION_FPU + bool "Double precision FPU" + select CPU_HAS_FPU_DOUBLE_PRECISION + +endchoice + +config SOC_ANDES_V5_HWDSP + bool "AndeStar V5 DSP ISA" + select RISCV_SOC_CONTEXT_SAVE + depends on !RISCV_GENERIC_TOOLCHAIN + help + This option enables the AndeStar v5 hardware DSP, in order to + support using the DSP instructions. + +config SOC_ANDES_V5_PFT + bool "Andes V5 PowerBrake extension" + default y + select RISCV_SOC_CONTEXT_SAVE + help + The PowerBrake extension throttles performance by reducing instruction + executing rate. + +config SOC_ANDES_V5_EXECIT + bool "Andes V5 EXEC.IT extension" + depends on RISCV_ISA_EXT_C + depends on !RISCV_GENERIC_TOOLCHAIN + depends on !LINKER_USE_NO_RELAX + help + The EXEC.IT extension (Execution on Instruction Table) generate + a look-up table and replaces suitable 32-bit instructions with + the 16-bit "exec.it ". + +config SOC_ANDES_V5_PMA + bool "Andes V5 Physical Memory Attribute (PMA)" + select ARCH_HAS_NOCACHE_MEMORY_SUPPORT + help + This option enables the Andes V5 PMA, in order to support SW to + configure physical memory attribute by PMA CSRs. The address + matching of Andes V5 PMA is like RISC-V PMP NAPOT mode + (power-of-two alignment). + +config SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE + int + depends on SOC_ANDES_V5_PMA + default 4096 + help + Minimum size (and alignment) of an PMA region. Use this symbol + to guarantee minimum size and alignment of PMA regions. + +# Workaround for not being able to have commas in macro arguments +DT_ANDESTECH_L2C := andestech,l2c + +config SOC_ANDES_V5_L2C + bool + default $(dt_compat_enabled,$(DT_ANDESTECH_L2C)) + +config SOC_ANDES_V5_IOCP + bool "Andes V5 I/O Coherence Port (IOCP)" + depends on SOC_ANDES_V5_L2C + depends on DCACHE + help + Support Andes V5 I/O Coherence Port to handle cache coherency + between cache and external non-caching master, such as DMA + controller. + +endif # SOC_SERIES_ANDES_AE350 diff --git a/soc/andestech/ae350/Kconfig.defconfig b/soc/andestech/ae350/Kconfig.defconfig new file mode 100644 index 00000000000..ba36eddc354 --- /dev/null +++ b/soc/andestech/ae350/Kconfig.defconfig @@ -0,0 +1,39 @@ +# Copyright (c) 2021 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ANDES_AE350 + +# Kconfig picks the first default with a satisfied condition. +# SoC defaults should be parsed before SoC Series defaults, because SoCs usually +# overrides SoC Series values. +rsource "Kconfig.defconfig.ae*" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 60000000 + +config KERNEL_ENTRY + default "entry" + +config RISCV_GENERIC_TOOLCHAIN + default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" + default n + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 52 + +config NUM_IRQS + default 64 + +endif # SOC_SERIES_ANDES_AE350 diff --git a/soc/riscv/andes_v5/ae350/Kconfig.defconfig.ae350 b/soc/andestech/ae350/Kconfig.defconfig.ae350 similarity index 93% rename from soc/riscv/andes_v5/ae350/Kconfig.defconfig.ae350 rename to soc/andestech/ae350/Kconfig.defconfig.ae350 index fee73684b71..ba661c96e63 100644 --- a/soc/riscv/andes_v5/ae350/Kconfig.defconfig.ae350 +++ b/soc/andestech/ae350/Kconfig.defconfig.ae350 @@ -3,9 +3,6 @@ if SOC_ANDES_AE350 -config SOC - default "ae350" - config SYS_CLOCK_TICKS_PER_SEC default 100 if (!ICACHE || XIP) diff --git a/soc/andestech/ae350/Kconfig.soc b/soc/andestech/ae350/Kconfig.soc new file mode 100644 index 00000000000..be7310adcc2 --- /dev/null +++ b/soc/andestech/ae350/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2021 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ANDES_AE350 + bool + select SOC_FAMILY_ANDES_V5 + help + Andes V5 AE350 SoC Series Implementation" + +config SOC_ANDES_AE350 + bool + select SOC_SERIES_ANDES_AE350 + help + Andes AE350 SoC implementation" + +config SOC_SERIES + default "ae350" if SOC_SERIES_ANDES_AE350 + +config SOC + default "ae350" if SOC_ANDES_AE350 diff --git a/soc/riscv/andes_v5/ae350/common_linker/execit.ld b/soc/andestech/ae350/common_linker/execit.ld similarity index 100% rename from soc/riscv/andes_v5/ae350/common_linker/execit.ld rename to soc/andestech/ae350/common_linker/execit.ld diff --git a/soc/riscv/andes_v5/ae350/common_linker/init.ld b/soc/andestech/ae350/common_linker/init.ld similarity index 100% rename from soc/riscv/andes_v5/ae350/common_linker/init.ld rename to soc/andestech/ae350/common_linker/init.ld diff --git a/soc/riscv/andes_v5/ae350/common_linker/ram_start_nonzero.ld b/soc/andestech/ae350/common_linker/ram_start_nonzero.ld similarity index 100% rename from soc/riscv/andes_v5/ae350/common_linker/ram_start_nonzero.ld rename to soc/andestech/ae350/common_linker/ram_start_nonzero.ld diff --git a/soc/riscv/andes_v5/ae350/l2_cache.c b/soc/andestech/ae350/l2_cache.c similarity index 100% rename from soc/riscv/andes_v5/ae350/l2_cache.c rename to soc/andestech/ae350/l2_cache.c diff --git a/soc/riscv/andes_v5/ae350/linker.ld b/soc/andestech/ae350/linker.ld similarity index 100% rename from soc/riscv/andes_v5/ae350/linker.ld rename to soc/andestech/ae350/linker.ld diff --git a/soc/riscv/andes_v5/ae350/pma.c b/soc/andestech/ae350/pma.c similarity index 100% rename from soc/riscv/andes_v5/ae350/pma.c rename to soc/andestech/ae350/pma.c diff --git a/soc/riscv/andes_v5/ae350/soc_context.h b/soc/andestech/ae350/soc_context.h similarity index 100% rename from soc/riscv/andes_v5/ae350/soc_context.h rename to soc/andestech/ae350/soc_context.h diff --git a/soc/riscv/andes_v5/ae350/soc_irq.S b/soc/andestech/ae350/soc_irq.S similarity index 100% rename from soc/riscv/andes_v5/ae350/soc_irq.S rename to soc/andestech/ae350/soc_irq.S diff --git a/soc/riscv/andes_v5/ae350/soc_offsets.h b/soc/andestech/ae350/soc_offsets.h similarity index 100% rename from soc/riscv/andes_v5/ae350/soc_offsets.h rename to soc/andestech/ae350/soc_offsets.h diff --git a/soc/riscv/andes_v5/ae350/soc_v5.h b/soc/andestech/ae350/soc_v5.h similarity index 100% rename from soc/riscv/andes_v5/ae350/soc_v5.h rename to soc/andestech/ae350/soc_v5.h diff --git a/soc/riscv/andes_v5/ae350/start.S b/soc/andestech/ae350/start.S similarity index 100% rename from soc/riscv/andes_v5/ae350/start.S rename to soc/andestech/ae350/start.S diff --git a/soc/andestech/soc.yml b/soc/andestech/soc.yml new file mode 100644 index 00000000000..be842155259 --- /dev/null +++ b/soc/andestech/soc.yml @@ -0,0 +1,6 @@ +family: +- name: andes_v5 + series: + - name: ae350 + socs: + - name: ae350 diff --git a/soc/arc/snps_arc_hsdk/Kconfig.defconfig b/soc/arc/snps_arc_hsdk/Kconfig.defconfig deleted file mode 100644 index 44791dc680a..00000000000 --- a/soc/arc/snps_arc_hsdk/Kconfig.defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARC_HSDK - -config SOC - default "snps_arc_hsdk" - -config CPU_HS3X - default y - -config NUM_IRQ_PRIO_LEVELS - # This processor supports 2 priority levels: - # 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs). - default 2 - -config NUM_IRQS - # must be > the highest interrupt number used - default 88 - -config RGF_NUM_BANKS - default 2 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 500000000 - -config ARC_FIRQ - default y - -config CODE_DENSITY - default y - -config ARCV2_TIMER_IRQ_PRIORITY - default 1 - -config ARC_CONNECT - default y - -config MP_MAX_NUM_CPUS - default 4 - -config UART_NS16550_ACCESS_WORD_ONLY - default y - depends on UART_NS16550 - -config ARC_HAS_ACCL_REGS - default y - -endif # ARC_HSDK diff --git a/soc/arc/snps_arc_hsdk/Kconfig.soc b/soc/arc/snps_arc_hsdk/Kconfig.soc deleted file mode 100644 index 93791fdb088..00000000000 --- a/soc/arc/snps_arc_hsdk/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ARC_HSDK - bool "Synopsys ARC HSDK SoC" - select ARC - select CPU_HAS_FPU diff --git a/soc/arc/snps_arc_hsdk4xd/CMakeLists.txt b/soc/arc/snps_arc_hsdk4xd/CMakeLists.txt deleted file mode 100644 index 0c13259ca2b..00000000000 --- a/soc/arc/snps_arc_hsdk4xd/CMakeLists.txt +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(COMPILER STREQUAL gcc) - # GNU compiler options - zephyr_compile_options(-mno-sdata) - zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpud_all) -else() - # MWDT compiler options - zephyr_compile_options(-arcv2hs -core4 -Xdual_issue -Xcode_density -Hrgf_banked_regs=32 -HL - -Xatomic -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist - -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc -Hld_cycles=2) - - zephyr_compile_options_ifdef(CONFIG_FPU -Xfpu_mac -Xfpud_div) - - zephyr_ld_options(-Hlib=hs48_slc_full) -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arc/snps_arc_hsdk4xd/Kconfig.defconfig b/soc/arc/snps_arc_hsdk4xd/Kconfig.defconfig deleted file mode 100644 index 1b70bce3721..00000000000 --- a/soc/arc/snps_arc_hsdk4xd/Kconfig.defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright (c) 2023 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARC_HSDK4XD - -config SOC - default "snps_arc_hsdk4xd" - -config CPU_HS4X - default y - -config NUM_IRQ_PRIO_LEVELS - # This processor supports 2 priority levels: - # 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs). - default 2 - -config NUM_IRQS - # must be > the highest interrupt number used - default 88 - -config RGF_NUM_BANKS - # Actually cpu has 4 banks but zephys currently supports up to 2 - default 2 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 500000000 - -config ARC_FIRQ - default y - -config CODE_DENSITY - default y - -config ARCV2_TIMER_IRQ_PRIORITY - default 1 - -config ARC_CONNECT - default y - -config MP_MAX_NUM_CPUS - default 4 - -config UART_NS16550_ACCESS_WORD_ONLY - default y - depends on UART_NS16550 - -config ARC_HAS_ACCL_REGS - default y - -config ARC_EARLY_SOC_INIT - default y - -config ARC_HAS_STACK_CHECKING - default n - -endif # SOC_ARC_HS4XD diff --git a/soc/arc/snps_arc_hsdk4xd/Kconfig.soc b/soc/arc/snps_arc_hsdk4xd/Kconfig.soc deleted file mode 100644 index 6354c659d30..00000000000 --- a/soc/arc/snps_arc_hsdk4xd/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ARC_HSDK4XD - bool "Synopsys ARC HSDK4XD SoC" - select ARC - select CPU_HAS_FPU - select CPU_HAS_DSP diff --git a/soc/arc/snps_arc_iot/Kconfig.defconfig b/soc/arc/snps_arc_iot/Kconfig.defconfig deleted file mode 100644 index 202697a7cf9..00000000000 --- a/soc/arc/snps_arc_iot/Kconfig.defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARC_IOT - -config SOC - default "snps_arc_iot" - -config CPU_EM4_FPUS - default y - -config NUM_IRQ_PRIO_LEVELS - # This processor supports 4 priority levels: - # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). - default 4 - -config ARC_MPU_VER - default 2 - -config NUM_IRQS - # must be > the highest interrupt number used - default 95 - -config RGF_NUM_BANKS - default 2 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 144000000 - -config HARVARD - default y - -config ARC_FIRQ - default y - -endif # ARC_IOT diff --git a/soc/arc/snps_arc_iot/Kconfig.soc b/soc/arc/snps_arc_iot/Kconfig.soc deleted file mode 100644 index f9793b27354..00000000000 --- a/soc/arc/snps_arc_iot/Kconfig.soc +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ARC_IOT - bool "Synopsys ARC IoT SoC" - select ARC - select CPU_HAS_MPU - select CPU_HAS_FPU diff --git a/soc/arc/snps_emsdp/CMakeLists.txt b/soc/arc/snps_emsdp/CMakeLists.txt deleted file mode 100644 index 04466b802c0..00000000000 --- a/soc/arc/snps_emsdp/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata) - -if(CONFIG_SOC_EMSDP_EM4) - zephyr_compile_options(-mmpy-option=3 -mno-div-rem) -elseif(CONFIG_SOC_EMSDP_EM6) - zephyr_compile_options(-mmpy-option=3 -mno-div-rem) -elseif(CONFIG_SOC_EMSDP_EM5D) - zephyr_compile_options(-mmpy-option=6) -elseif(CONFIG_SOC_EMSDP_EM7D) - zephyr_compile_options(-mmpy-option=6) -elseif(CONFIG_SOC_EMSDP_EM7D_ESP) - zephyr_compile_options(-mmpy-option=6) -elseif(CONFIG_SOC_EMSDP_EM9D) - zephyr_compile_options(-mmpy-option=6) - zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpus_all) -elseif(CONFIG_SOC_EMSDP_EM11D) - zephyr_compile_options(-mmpy-option=6) - zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all) -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arc/snps_emsdp/Kconfig b/soc/arc/snps_emsdp/Kconfig deleted file mode 100644 index b8f6888433f..00000000000 --- a/soc/arc/snps_emsdp/Kconfig +++ /dev/null @@ -1,43 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARC EM Software Development Platform Core Selection" - default SOC_EMSDP_EM11D - depends on SOC_ARC_EMSDP - -config SOC_EMSDP_EM4 - bool "Synopsys ARC EM4 of EMSDP" - select CPU_HAS_MPU - -config SOC_EMSDP_EM6 - bool "Synopsys ARC EM6 of EMSDP" - select CPU_HAS_MPU - -config SOC_EMSDP_EM5D - bool "Synopsys ARC EM5D of EMSDP" - select CPU_HAS_MPU - select CPU_HAS_FPU - -config SOC_EMSDP_EM7D - bool "Synopsys ARC EM7D of EMSDP" - select CPU_HAS_MPU - select CPU_HAS_FPU - -config SOC_EMSDP_EM7D_ESP - bool "Synopsys ARC EM7D+ESP of EMSDP" - select CPU_HAS_MPU - select CPU_HAS_FPU - select ARC_HAS_SECURE - -config SOC_EMSDP_EM9D - bool "Synopsys ARC EM9D of EMSDP" - select CPU_HAS_MPU - select CPU_HAS_FPU - -config SOC_EMSDP_EM11D - bool "Synopsys ARC EM11D of EMSDP" - select CPU_HAS_MPU - select CPU_HAS_FPU - -endchoice diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig b/soc/arc/snps_emsdp/Kconfig.defconfig deleted file mode 100644 index 0e04f92315a..00000000000 --- a/soc/arc/snps_emsdp/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARC_EMSDP - -config SOC - default "snps_emsdp" - -config NUM_IRQ_PRIO_LEVELS - # This processor supports 4 priority levels: - # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). - default 4 - -source "soc/arc/snps_emsdp/Kconfig.defconfig.em4" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em5d" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em6" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em7d" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em7d_esp" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em9d" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em11d" - - -endif # SOC_ARC_EMSDP diff --git a/soc/arc/snps_emsdp/Kconfig.soc b/soc/arc/snps_emsdp/Kconfig.soc deleted file mode 100644 index ed0a2f88e20..00000000000 --- a/soc/arc/snps_emsdp/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ARC_EMSDP - bool "Synopsys ARC EM Software Development Platform" - select ARC diff --git a/soc/arc/snps_emsk/CMakeLists.txt b/soc/arc/snps_emsk/CMakeLists.txt deleted file mode 100644 index 8e8ef5865ca..00000000000 --- a/soc/arc/snps_emsk/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata -mmpy-option=6) - -if(CONFIG_SOC_EMSK_EM9D) -zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpus_all) -elseif(CONFIG_SOC_EMSK_EM11D) -zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all) -endif() - -zephyr_sources(soc_config.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arc/snps_emsk/Kconfig b/soc/arc/snps_emsk/Kconfig deleted file mode 100644 index b1f0f7e54aa..00000000000 --- a/soc/arc/snps_emsk/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARC EM Starter Kit Core Selection" - default SOC_EMSK_EM7D - depends on SOC_EMSK - -config SOC_EMSK_EM7D - bool "Synopsys ARC EM7D of EMSK" - select CPU_HAS_MPU - -config SOC_EMSK_EM11D - bool "Synopsys ARC EM11D of EMSK" - select CPU_HAS_FPU - -config SOC_EMSK_EM9D - bool "Synopsys ARC EM9D of EMSK" - select CPU_HAS_FPU - -endchoice diff --git a/soc/arc/snps_emsk/Kconfig.defconfig b/soc/arc/snps_emsk/Kconfig.defconfig deleted file mode 100644 index 4d25c7b634b..00000000000 --- a/soc/arc/snps_emsk/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_EMSK - -config SOC - default "snps_emsk" - -source "soc/arc/snps_emsk/Kconfig.defconfig.em7d" -source "soc/arc/snps_emsk/Kconfig.defconfig.em11d" -source "soc/arc/snps_emsk/Kconfig.defconfig.em9d" - -endif # SOC_EMSK diff --git a/soc/arc/snps_emsk/Kconfig.defconfig.em7d b/soc/arc/snps_emsk/Kconfig.defconfig.em7d deleted file mode 100644 index 24f744b91af..00000000000 --- a/soc/arc/snps_emsk/Kconfig.defconfig.em7d +++ /dev/null @@ -1,55 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_EMSK_EM7D - -config CPU_EM4_DMIPS - default y - -config NUM_IRQ_PRIO_LEVELS - # This processor supports 4 priority levels: - # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). - default 4 - -config NUM_IRQS - # must be > the highest interrupt number used - default 38 if BOARD_EM_STARTERKIT_R23 - default 36 if BOARD_EM_STARTERKIT_R22 - -config ARC_MPU_VER - default 4 if BOARD_EM_STARTERKIT_R23 - default 2 if BOARD_EM_STARTERKIT_R22 - -config RGF_NUM_BANKS - default 1 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 25000000 if BOARD_EM_STARTERKIT_R23 - default 30000000 if BOARD_EM_STARTERKIT_R22 - -config HARVARD - default y - -config ARC_FIRQ - default n if BOARD_EM_STARTERKIT_R23 - default y if BOARD_EM_STARTERKIT_R22 - -config CACHE_MANAGEMENT - default y - -if (ARC_MPU_VER = 2) - -config MAIN_STACK_SIZE - default 2048 - -config IDLE_STACK_SIZE - default 2048 - -config ZTEST_STACK_SIZE - default 2048 - depends on ZTEST - -endif # ARC_MPU_VER - -endif # SOC_EMSK_EM7D diff --git a/soc/arc/snps_emsk/Kconfig.soc b/soc/arc/snps_emsk/Kconfig.soc deleted file mode 100644 index d172c4144a7..00000000000 --- a/soc/arc/snps_emsk/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_EMSK - bool "Synopsys ARC EM Starter Kit SoC" - select ARC diff --git a/soc/arc/snps_nsim/Kconfig b/soc/arc/snps_nsim/Kconfig deleted file mode 100644 index cdf2ec69cae..00000000000 --- a/soc/arc/snps_nsim/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARC nSIM SoC Selection" - default SOC_NSIM_EM - depends on SOC_NSIM - -config SOC_NSIM_EM - bool "Synopsys ARC EM in nSIM" - select CPU_HAS_MPU - -config SOC_NSIM_EM7D_V22 - bool "Synopsys ARC EM7D_V22 in nSIM" - select CPU_HAS_MPU - select CPU_HAS_FPU - -config SOC_NSIM_EM11D - bool "Synopsys ARC EM11D in nSIM" - select CPU_HAS_MPU - select CPU_HAS_DSP - -config SOC_NSIM_SEM - bool "Synopsys ARC SEM in nSIM" - select CPU_HAS_MPU - select CPU_HAS_FPU - select ARC_HAS_SECURE - -config SOC_NSIM_HS - bool "Synopsys ARC HS in nSIM" - select CPU_HAS_FPU - select CPU_HAS_MPU - -config SOC_NSIM_HS_SMP - bool "Multi-core Synopsys ARC HS in nSIM" - select CPU_HAS_FPU - -config SOC_NSIM_HS_MPUV6 - bool "Synopsys ARC HS with MPU v6 in nSIM" - select CPU_HAS_MPU - select CPU_HAS_FPU - -config SOC_NSIM_VPX5 - bool "Synopsys ARC VPX5 in nSIM" - -config SOC_NSIM_HS6X - bool "Synopsys ARC HS6x in nSIM" - -config SOC_NSIM_HS6X_SMP - bool "Multi-core Synopsys ARC HS6x in nSIM" - -config SOC_NSIM_HS5X - bool "Synopsys ARC HS5x in nSIM" - -config SOC_NSIM_HS5X_SMP - bool "Multi-core Synopsys ARC HS5x in nSIM" - -endchoice diff --git a/soc/arc/snps_nsim/Kconfig.defconfig b/soc/arc/snps_nsim/Kconfig.defconfig deleted file mode 100644 index 69f8d9f440f..00000000000 --- a/soc/arc/snps_nsim/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NSIM - -config SOC - default "snps_nsim" - -config XIP - default n - -source "soc/arc/snps_nsim/Kconfig.defconfig.em" -source "soc/arc/snps_nsim/Kconfig.defconfig.em11d" -source "soc/arc/snps_nsim/Kconfig.defconfig.em7d_v22" -source "soc/arc/snps_nsim/Kconfig.defconfig.sem" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs_smp" -source "soc/arc/snps_nsim/Kconfig.defconfig.vpx5" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs_mpuv6" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs5x" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs5x_smp" - -endif # SOC_NSIM diff --git a/soc/arc/snps_nsim/Kconfig.soc b/soc/arc/snps_nsim/Kconfig.soc deleted file mode 100644 index 69e9fdce863..00000000000 --- a/soc/arc/snps_nsim/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NSIM - bool "Synopsys nSIM simulator for ARC cores" - select ARC diff --git a/soc/arc/snps_qemu/CMakeLists.txt b/soc/arc/snps_qemu/CMakeLists.txt deleted file mode 100644 index a05efdfa22d..00000000000 --- a/soc/arc/snps_qemu/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(COMPILER STREQUAL gcc) - zephyr_compile_options(-mcpu=${GCC_M_CPU}) - - zephyr_compile_options_ifdef(CONFIG_ISA_ARCV2 -mno-sdata) - -else() - - zephyr_compile_options_ifdef(CONFIG_SOC_QEMU_ARC_HS -arcv2hs -core2 -Xatomic - -Xunaligned -Xcode_density -Xswap -Xbitscan - -Xmpy_option=qmpyh -Xshift_assist -Xbarrel_shifter - -Xtimer0 -Xtimer1) - - zephyr_ld_option_ifdef(CONFIG_SOC_QEMU_ARC_HS -Hlib=hs38_full) - - if(NOT CONFIG_SOC_QEMU_ARC_HS) - message(WARNING "QEMU ARC platforms other than HS are not supported yet with MW toolchain") - endif() - -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arc/snps_qemu/Kconfig b/soc/arc/snps_qemu/Kconfig deleted file mode 100644 index 3146c6c5e91..00000000000 --- a/soc/arc/snps_qemu/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2020 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARC QEMU SoC Selection" - default SOC_QEMU_ARC_HS - depends on SOC_QEMU_ARC - -config SOC_QEMU_ARC_EM - bool "Synopsys ARC EM in QEMU" - -config SOC_QEMU_ARC_HS - bool "Synopsys ARC HS in QEMU" - -config SOC_QEMU_ARC_HS6X - bool "Synopsys ARC HS6x in QEMU" - -config SOC_QEMU_ARC_HS5X - bool "Synopsys ARC HS5x in QEMU" - -endchoice diff --git a/soc/arc/snps_qemu/Kconfig.defconfig b/soc/arc/snps_qemu/Kconfig.defconfig deleted file mode 100644 index 25b03b3375f..00000000000 --- a/soc/arc/snps_qemu/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright (c) 2020 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_ARC - -config SOC - string - default "snps_qemu" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 10000000 - -config RGF_NUM_BANKS - default 1 - -config ARC_FIRQ - default n - -config NUM_IRQ_PRIO_LEVELS - default 15 - -config NUM_IRQS - default 26 - -# Technically ARC HS supports MPUv3, but not v2. But given MPUv3 -# is the same as v2 but with minimal region size of 32 bytes, we -# may assume MPUv3 is just a subset of MPUv2. - -config ARC_MPU_VER - default 2 - -source "soc/arc/snps_qemu/Kconfig.defconfig.em" -source "soc/arc/snps_qemu/Kconfig.defconfig.hs" -source "soc/arc/snps_qemu/Kconfig.defconfig.hs5x" -source "soc/arc/snps_qemu/Kconfig.defconfig.hs6x" - -endif diff --git a/soc/arc/snps_qemu/Kconfig.defconfig.em b/soc/arc/snps_qemu/Kconfig.defconfig.em deleted file mode 100644 index 6123c3a9c69..00000000000 --- a/soc/arc/snps_qemu/Kconfig.defconfig.em +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_ARC_EM - -config CPU_EM4 - default y - -endif diff --git a/soc/arc/snps_qemu/Kconfig.defconfig.hs b/soc/arc/snps_qemu/Kconfig.defconfig.hs deleted file mode 100644 index cabb99713e3..00000000000 --- a/soc/arc/snps_qemu/Kconfig.defconfig.hs +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_ARC_HS - -config CPU_HS3X - default y - -endif diff --git a/soc/arc/snps_qemu/Kconfig.defconfig.hs5x b/soc/arc/snps_qemu/Kconfig.defconfig.hs5x deleted file mode 100644 index 502a78299c3..00000000000 --- a/soc/arc/snps_qemu/Kconfig.defconfig.hs5x +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_ARC_HS5X - -config CPU_HS5X - default y - -endif diff --git a/soc/arc/snps_qemu/Kconfig.defconfig.hs6x b/soc/arc/snps_qemu/Kconfig.defconfig.hs6x deleted file mode 100644 index 1b4d6884ee1..00000000000 --- a/soc/arc/snps_qemu/Kconfig.defconfig.hs6x +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_ARC_HS6X - -config CPU_HS6X - default y - -endif diff --git a/soc/arc/snps_qemu/Kconfig.soc b/soc/arc/snps_qemu/Kconfig.soc deleted file mode 100644 index 1d3a6c2335c..00000000000 --- a/soc/arc/snps_qemu/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2020 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_ARC - bool "QEMU emulation of ARC cores" - select ARC - select CPU_HAS_MPU diff --git a/soc/arm/CMakeLists.txt b/soc/arm/CMakeLists.txt index b826da926ca..e2bba115e17 100644 --- a/soc/arm/CMakeLists.txt +++ b/soc/arm/CMakeLists.txt @@ -1,7 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) +if(DEFINED SOC_SERIES) + add_subdirectory(${SOC_SERIES}) else() add_subdirectory(${SOC_NAME}) endif() diff --git a/soc/arm/Kconfig b/soc/arm/Kconfig index 461f0b41f84..44ffc5d2b39 100644 --- a/soc/arm/Kconfig +++ b/soc/arm/Kconfig @@ -1,53 +1,8 @@ -# General options signifying CPU capabilities of ARM SoCs - -# Copyright (c) 2018 Nordic Semiconductor ASA. +# Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -config CPU_HAS_ARM_MPU - bool - select CPU_HAS_MPU - help - This option is enabled when the CPU has a Memory Protection Unit (MPU) - in ARM flavor. - -config CPU_HAS_NXP_MPU - bool - select CPU_HAS_MPU - help - This option is enabled when the CPU has a Memory Protection Unit (MPU) - in NXP flavor. - -config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - bool "Custom fixed SoC MPU region definition" - help - If enabled, this option signifies that the SoC will - define and configure its own fixed MPU regions in the - SoC definition. These fixed MPU regions are currently - used to set Flash and SRAM default access policies and - they are programmed at boot time. - -config CPU_HAS_ARM_SAU - bool - select CPU_HAS_TEE - help - MCU implements the ARM Security Attribution Unit (SAU). - -config CPU_HAS_NRF_IDAU - bool - select CPU_HAS_TEE - help - MCU implements the nRF (vendor-specific) Security Attribution Unit. - (IDAU: "Implementation-Defined Attribution Unit", in accordance with - ARM terminology). +if SOC_FAMILY_ARM || SOC_FAMILY_ARM64 -config HAS_SWO - bool - help - When enabled, indicates that SoC has an SWO output +rsource "*/Kconfig" -config SOC_PART_NUMBER - string - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. +endif # SOC_FAMILY_ARM || SOC_FAMILY_ARM64 diff --git a/soc/arm/Kconfig.defconfig b/soc/arm/Kconfig.defconfig new file mode 100644 index 00000000000..d25284634e3 --- /dev/null +++ b/soc/arm/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ARM || SOC_FAMILY_ARM64 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_ARM || SOC_FAMILY_ARM64 diff --git a/soc/arm/Kconfig.soc b/soc/arm/Kconfig.soc new file mode 100644 index 00000000000..159cb16c43c --- /dev/null +++ b/soc/arm/Kconfig.soc @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ARM + bool + +config SOC_FAMILY_ARM64 + bool + +config SOC_FAMILY + default "arm" if SOC_FAMILY_ARM + default "arm64" if SOC_FAMILY_ARM64 + +rsource "*/Kconfig.soc" diff --git a/soc/arm/ambiq/Kconfig b/soc/arm/ambiq/Kconfig deleted file mode 100644 index eba0a01db71..00000000000 --- a/soc/arm/ambiq/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -config SOC_FAMILY_AMBIQ - bool - -if SOC_FAMILY_AMBIQ - -config SOC_FAMILY - string - default "ambiq" - -source "soc/arm/ambiq/*/Kconfig.soc" - -endif # SOC_FAMILY_AMBIQ diff --git a/soc/arm/ambiq/Kconfig.defconfig b/soc/arm/ambiq/Kconfig.defconfig deleted file mode 100644 index b3102f50375..00000000000 --- a/soc/arm/ambiq/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -source "soc/arm/ambiq/*/Kconfig.defconfig.series" - -config CORTEX_M_SYSTICK - default n if AMBIQ_STIMER_TIMER - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 if AMBIQ_STIMER_TIMER diff --git a/soc/arm/ambiq/Kconfig.soc b/soc/arm/ambiq/Kconfig.soc deleted file mode 100644 index e1e31309730..00000000000 --- a/soc/arm/ambiq/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -source "soc/arm/ambiq/*/Kconfig.series" diff --git a/soc/arm/ambiq/apollo4x/CMakeLists.txt b/soc/arm/ambiq/apollo4x/CMakeLists.txt deleted file mode 100644 index a82fe0a51f3..00000000000 --- a/soc/arm/ambiq/apollo4x/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Antmicro -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources(soc.c) -zephyr_include_directories(${ZEPHYR_BASE}/soc/arm/common/cortex_m) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ambiq/apollo4x/Kconfig.defconfig.series b/soc/arm/ambiq/apollo4x/Kconfig.defconfig.series deleted file mode 100644 index f933eb5d1c4..00000000000 --- a/soc/arm/ambiq/apollo4x/Kconfig.defconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -if SOC_SERIES_APOLLO4X - -source "soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4*" - -config SOC_SERIES - default "apollo4x" - -endif # SOC_SERIES_APOLLO4X diff --git a/soc/arm/ambiq/apollo4x/Kconfig.series b/soc/arm/ambiq/apollo4x/Kconfig.series deleted file mode 100644 index a9e72567206..00000000000 --- a/soc/arm/ambiq/apollo4x/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -# Ambiq Apollo4 MCU Series - -config SOC_SERIES_APOLLO4X - bool "Apollo4 Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_AMBIQ - select HAS_SWO - select AMBIQ_HAL - help - Enable support for Apollo4 MCU series diff --git a/soc/arm/ambiq/apollo4x/Kconfig.soc b/soc/arm/ambiq/apollo4x/Kconfig.soc deleted file mode 100644 index a9b5cf00824..00000000000 --- a/soc/arm/ambiq/apollo4x/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro -# Copyright (c) 2023 Ambiq Micro Inc. - -choice - prompt "Ambiq Apollo4X Selection" - depends on SOC_SERIES_APOLLO4X - -config SOC_APOLLO4P - bool "Apollo4P" - -config SOC_APOLLO4P_BLUE - bool "Apollo4 Blue Plus" - -endchoice diff --git a/soc/arm/arm/Kconfig b/soc/arm/arm/Kconfig deleted file mode 100644 index de5b5d581cb..00000000000 --- a/soc/arm/arm/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ARM - bool - -if SOC_FAMILY_ARM -config SOC_FAMILY - string - default "arm" - -source "soc/arm/arm/*/Kconfig.soc" -endif # SOC_FAMILY_ARM diff --git a/soc/arm/arm/Kconfig.defconfig b/soc/arm/arm/Kconfig.defconfig deleted file mode 100644 index 54abe04110d..00000000000 --- a/soc/arm/arm/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/arm/*/Kconfig.defconfig.series" diff --git a/soc/arm/arm/Kconfig.soc b/soc/arm/arm/Kconfig.soc deleted file mode 100644 index 60ee8580718..00000000000 --- a/soc/arm/arm/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/arm/*/Kconfig.series" diff --git a/soc/arm/arm/beetle/CMakeLists.txt b/soc/arm/arm/beetle/CMakeLists.txt deleted file mode 100644 index e911f5faab5..00000000000 --- a/soc/arm/arm/beetle/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/beetle/Kconfig.defconfig.beetle_r0 b/soc/arm/arm/beetle/Kconfig.defconfig.beetle_r0 deleted file mode 100644 index ae6d93ca0cc..00000000000 --- a/soc/arm/arm/beetle/Kconfig.defconfig.beetle_r0 +++ /dev/null @@ -1,8 +0,0 @@ -# ARM LTD Beetle SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "beetle_r0" - depends on SOC_BEETLE_R0 diff --git a/soc/arm/arm/beetle/Kconfig.defconfig.series b/soc/arm/arm/beetle/Kconfig.defconfig.series deleted file mode 100644 index 2c2f58634a0..00000000000 --- a/soc/arm/arm/beetle/Kconfig.defconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# ARM LTD Beetle SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_BEETLE - -source "soc/arm/arm/beetle/Kconfig.defconfig.beetle*" - -config SOC_SERIES - default "beetle" - -config NUM_IRQS - default 45 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 24000000 - -config CLOCK_CONTROL_INIT_PRIORITY - default 1 - depends on CLOCK_CONTROL - -endif # SOC_SERIES_BEETLE diff --git a/soc/arm/arm/beetle/Kconfig.series b/soc/arm/arm/beetle/Kconfig.series deleted file mode 100644 index 2217f282cf0..00000000000 --- a/soc/arm/arm/beetle/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# ARM LTD Beetle SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_BEETLE - bool "Arm Beetle MCU Series" - select ARM - select CPU_CORTEX_M3 - select SOC_FAMILY_ARM - select CPU_HAS_ARM_MPU - select CPU_CORTEX_M_HAS_DWT - help - Enable support for Beetle MCU Series diff --git a/soc/arm/arm/beetle/Kconfig.soc b/soc/arm/arm/beetle/Kconfig.soc deleted file mode 100644 index e577ee7060e..00000000000 --- a/soc/arm/arm/beetle/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# ARM LTD Beetle SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM Beetle SoC" - depends on SOC_SERIES_BEETLE - -config SOC_BEETLE_R0 - bool "ARM BEETLE R0" - -endchoice diff --git a/soc/arm/arm/designstart/CMakeLists.txt b/soc/arm/arm/designstart/CMakeLists.txt deleted file mode 100644 index 5d2598e239b..00000000000 --- a/soc/arm/arm/designstart/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m1 b/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m1 deleted file mode 100644 index 8c6052ffa2d..00000000000 --- a/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m1 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARM_DESIGNSTART_FPGA_CORTEX_M1 - -config SOC - default "designstart_cortex_m1" - -endif # SOC_ARM_DESIGNSTART_FPGA_CORTEX_M1 diff --git a/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m3 b/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m3 deleted file mode 100644 index 49275b57afe..00000000000 --- a/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m3 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3 - -config SOC - default "designstart_cortex_m3" - -endif # SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/soc/arm/arm/designstart/Kconfig.defconfig.series b/soc/arm/arm/designstart/Kconfig.defconfig.series deleted file mode 100644 index de0c30c9cf6..00000000000 --- a/soc/arm/arm/designstart/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ARM_DESIGNSTART - -config SOC_SERIES - default "designstart" - -source "soc/arm/arm/designstart/Kconfig.defconfig.cortex*" - -endif # SOC_SERIES_ARM_DESIGNSTART diff --git a/soc/arm/arm/designstart/Kconfig.series b/soc/arm/arm/designstart/Kconfig.series deleted file mode 100644 index 23c49edc8c6..00000000000 --- a/soc/arm/arm/designstart/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ARM_DESIGNSTART - bool "Arm DesignStart SoC Series" - select ARM - select SOC_FAMILY_ARM - help - Enable support for the ARM DesignStart SoC Series diff --git a/soc/arm/arm/designstart/Kconfig.soc b/soc/arm/arm/designstart/Kconfig.soc deleted file mode 100644 index 00ce3c7a4eb..00000000000 --- a/soc/arm/arm/designstart/Kconfig.soc +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM DesignStart SoCs" - depends on SOC_SERIES_ARM_DESIGNSTART - -config SOC_ARM_DESIGNSTART_FPGA_CORTEX_M1 - bool "ARM Cortex-M1 DesignStart FPGA" - select CPU_CORTEX_M1 - imply XIP - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -config SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3 - bool "ARM Cortex-M3 DesignStart FPGA" - select CPU_CORTEX_M3 - imply XIP - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -endchoice diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/CMakeLists.txt b/soc/arm/arm/fvp_aemv8r_aarch32/CMakeLists.txt deleted file mode 100644 index d9264843fae..00000000000 --- a/soc/arm/arm/fvp_aemv8r_aarch32/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c) -zephyr_library_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.defconfig.series b/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.defconfig.series deleted file mode 100644 index d884d3e5494..00000000000 --- a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.defconfig.series +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_FVP_AEMV8R_AARCH32 - -config SOC_SERIES - default "fvp_aemv8r_aarch32" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config NUM_IRQS - default 128 - -if SOC_FVP_AEMV8R_AARCH32 - -config SOC - default "fvp_aemv8r_aarch32" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config MAX_DOMAIN_PARTITIONS - default 24 if USERSPACE - -endif # SOC_FVP_AEMV8R_AARCH32 - -endif # SOC_SERIES_FVP_AEMV8R_AARCH32 diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.series b/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.series deleted file mode 100644 index 2479afe4130..00000000000 --- a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_FVP_AEMV8R_AARCH32 - bool "ARM FVP AEMv8R AArch32 Series" - select ARM - select SOC_FAMILY_ARM - help - Enable support for ARM FVP AEMv8R AArch32 Series diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.soc b/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.soc deleted file mode 100644 index 6993cfe715a..00000000000 --- a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.soc +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM FVP AEMv8R AArch32 SoCs" - depends on SOC_SERIES_FVP_AEMV8R_AARCH32 - -config SOC_FVP_AEMV8R_AARCH32 - bool "ARM FVP AEMv8R aarch32 simulation" - select CPU_CORTEX_R52 - select CPU_HAS_ARM_MPU - select CPU_HAS_MPU - select VFP_DP_D32_FP16_FMAC if !USE_SWITCH - select GIC_V3 - select GIC_SINGLE_SECURITY_STATE - select PLATFORM_SPECIFIC_INIT - -endchoice diff --git a/soc/arm/arm/mps2/CMakeLists.txt b/soc/arm/arm/mps2/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9..00000000000 --- a/soc/arm/arm/mps2/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an385 b/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an385 deleted file mode 100644 index 3f0e09b3b78..00000000000 --- a/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an385 +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MPS2_AN385 - -config SOC - default "mps2_an385" - -config NUM_IRQS - default 32 - -endif diff --git a/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an521 b/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an521 deleted file mode 100644 index a4bd9aea47f..00000000000 --- a/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an521 +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2018-2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MPS2_AN521 - -config SOC - default "mps2_an521" - -config NUM_IRQS - default 96 - -endif diff --git a/soc/arm/arm/mps2/Kconfig.defconfig.series b/soc/arm/arm/mps2/Kconfig.defconfig.series deleted file mode 100644 index 62234279c14..00000000000 --- a/soc/arm/arm/mps2/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MPS2 - -config SOC_SERIES - default "mps2" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 25000000 - -source "soc/arm/arm/mps2/Kconfig.defconfig.mps2*" - -endif # SOC_SERIES_MPS2 diff --git a/soc/arm/arm/mps2/Kconfig.series b/soc/arm/arm/mps2/Kconfig.series deleted file mode 100644 index c8715c21c83..00000000000 --- a/soc/arm/arm/mps2/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MPS2 - bool "Arm MPS2 MCU Series" - select ARM - select SOC_FAMILY_ARM - select GPIO_MMIO32 if GPIO - help - Enable support for ARM MPS2 MCU Series diff --git a/soc/arm/arm/mps2/Kconfig.soc b/soc/arm/arm/mps2/Kconfig.soc deleted file mode 100644 index 6a01c0d27fa..00000000000 --- a/soc/arm/arm/mps2/Kconfig.soc +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2017-2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_MPS2_AN521 - bool - select CPU_CORTEX_M33 - select CPU_HAS_ARM_MPU - -choice - prompt "ARM MPS2 SoCs" - depends on SOC_SERIES_MPS2 - -config SOC_MPS2_AN385 - bool "ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)" - select CPU_CORTEX_M3 - select CPU_HAS_ARM_MPU - -config SOC_MPS2_AN521_CPU0 - bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU0" - select SOC_MPS2_AN521 - select CPU_HAS_ARM_SAU - -config SOC_MPS2_AN521_CPU1 - bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU1" - select SOC_MPS2_AN521 - select CPU_HAS_FPU - select ARMV8_M_DSP - -endchoice diff --git a/soc/arm/arm/mps2/soc.c b/soc/arm/arm/mps2/soc.c deleted file mode 100644 index 76edaa388f5..00000000000 --- a/soc/arm/arm/mps2/soc.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2017 Linaro Limited - * - * Initial contents based on soc/arm/ti_lm3s6965/soc.c which is: - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - - -/* Setup GPIO drivers for accessing FPGAIO registers */ -#define FPGAIO_NODE(n) DT_INST(n, arm_mps2_fpgaio_gpio) -#define FPGAIO_INIT(n) \ - GPIO_MMIO32_INIT(FPGAIO_NODE(n), \ - DT_REG_ADDR(FPGAIO_NODE(n)), \ - BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios))) - -/* We expect there to be 3 arm,mps2-fpgaio-gpio devices: - * led0, button, and misc - */ -FPGAIO_INIT(0); -FPGAIO_INIT(1); -FPGAIO_INIT(2); - -/* (Secure System Control) Base Address */ -#define SSE_200_SYSTEM_CTRL_S_BASE (0x50021000UL) -#define SSE_200_SYSTEM_CTRL_INITSVTOR1 (SSE_200_SYSTEM_CTRL_S_BASE + 0x114) -#define SSE_200_SYSTEM_CTRL_CPU_WAIT (SSE_200_SYSTEM_CTRL_S_BASE + 0x118) -#define SSE_200_CPU_ID_UNIT_BASE (0x5001F000UL) - -/* The base address that the application image will start at on the secondary - * (non-TrustZone) Cortex-M33 mcu. - */ -#define CPU1_FLASH_ADDRESS (0x38B000) - -/* The memory map offset for the application image, which is used - * to determine the location of the reset vector at startup. - */ -#define CPU1_FLASH_OFFSET (0x10000000) - -/** - * @brief Wake up CPU 1 from another CPU, this is platform specific. - */ -void wakeup_cpu1(void) -{ - /* Set the Initial Secure Reset Vector Register for CPU 1 */ - *(uint32_t *)(SSE_200_SYSTEM_CTRL_INITSVTOR1) = - (uint32_t)_vector_start + - CPU1_FLASH_ADDRESS - - CPU1_FLASH_OFFSET; - - /* Set the CPU Boot wait control after reset */ - *(uint32_t *)(SSE_200_SYSTEM_CTRL_CPU_WAIT) = 0; -} - -/** - * @brief Get the current CPU ID, this is platform specific. - * - * @return Current CPU ID - */ -uint32_t sse_200_platform_get_cpu_id(void) -{ - volatile uint32_t *p_cpu_id = (volatile uint32_t *)SSE_200_CPU_ID_UNIT_BASE; - - return (uint32_t)*p_cpu_id; -} diff --git a/soc/arm/arm/mps3/CMakeLists.txt b/soc/arm/arm/mps3/CMakeLists.txt deleted file mode 100644 index d82e1bc62c5..00000000000 --- a/soc/arm/arm/mps3/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/mps3/Kconfig.defconfig.series b/soc/arm/arm/mps3/Kconfig.defconfig.series deleted file mode 100644 index 6cd25168380..00000000000 --- a/soc/arm/arm/mps3/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MPS3 - -config SOC_SERIES - default "mps3" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 25000000 - -source "soc/arm/arm/mps3/Kconfig.defconfig.mps3*" - -endif # SOC_SERIES_MPS3 diff --git a/soc/arm/arm/mps3/Kconfig.series b/soc/arm/arm/mps3/Kconfig.series deleted file mode 100644 index 2b73ade4a69..00000000000 --- a/soc/arm/arm/mps3/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MPS3 - bool "Arm MPS3 MCU Series" - select ARM - select SOC_FAMILY_ARM - select GPIO_MMIO32 if GPIO - help - Enable support for ARM MPS3 MCU Series diff --git a/soc/arm/arm/mps3/Kconfig.soc b/soc/arm/arm/mps3/Kconfig.soc deleted file mode 100644 index ae577fa549b..00000000000 --- a/soc/arm/arm/mps3/Kconfig.soc +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2017-2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Arm MPS3 SoCs" - depends on SOC_SERIES_MPS3 - -config SOC_MPS3_AN547 - bool "Arm Cortex-M55 SSE-300 on MPS3 (AN547)" - select CPU_CORTEX_M55 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARMV8_1_M_MVEI - select ARMV8_1_M_MVEF - select ARMV8_1_M_PMU - -endchoice - -config ARMV8_1_M_PMU_EVENTCNT - int - default 8 if SOC_MPS3_AN547 diff --git a/soc/arm/arm/musca_b1/CMakeLists.txt b/soc/arm/arm/musca_b1/CMakeLists.txt deleted file mode 100644 index 9c8a3b15eb2..00000000000 --- a/soc/arm/arm/musca_b1/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2018 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/musca_b1/Kconfig.defconfig.musca_b1 b/soc/arm/arm/musca_b1/Kconfig.defconfig.musca_b1 deleted file mode 100644 index 59fac252df4..00000000000 --- a/soc/arm/arm/musca_b1/Kconfig.defconfig.musca_b1 +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_V2M_MUSCA_B1 - -config SOC - default "musca_b1" - -config NUM_IRQS - default 96 - -endif diff --git a/soc/arm/arm/musca_b1/Kconfig.defconfig.series b/soc/arm/arm/musca_b1/Kconfig.defconfig.series deleted file mode 100644 index 356f945dc56..00000000000 --- a/soc/arm/arm/musca_b1/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MUSCA_B1 - -config SOC_SERIES - default "musca_b1" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 40000000 - -source "soc/arm/arm/musca_b1/Kconfig.defconfig.musca_b1" - -endif # SOC_SERIES_MUSCA_B1 diff --git a/soc/arm/arm/musca_b1/Kconfig.series b/soc/arm/arm/musca_b1/Kconfig.series deleted file mode 100644 index 1a74a623f8d..00000000000 --- a/soc/arm/arm/musca_b1/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MUSCA_B1 - bool "Arm v2m MUSCA B1 MCU Series" - select ARM - select SOC_FAMILY_ARM - select BUILD_OUTPUT_HEX - help - Enable support for arm V2M Musca B1 MCU Series diff --git a/soc/arm/arm/musca_b1/Kconfig.soc b/soc/arm/arm/musca_b1/Kconfig.soc deleted file mode 100644 index da7ae30698a..00000000000 --- a/soc/arm/arm/musca_b1/Kconfig.soc +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM Musca B1 SoCs" - depends on SOC_SERIES_MUSCA_B1 - -config SOC_V2M_MUSCA_B1 - bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-B1" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_CORTEX_M_HAS_DWT - -endchoice diff --git a/soc/arm/arm/musca_s1/CMakeLists.txt b/soc/arm/arm/musca_s1/CMakeLists.txt deleted file mode 100644 index 51df24c9b73..00000000000 --- a/soc/arm/arm/musca_s1/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2018 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/musca_s1/Kconfig.defconfig.musca_s1 b/soc/arm/arm/musca_s1/Kconfig.defconfig.musca_s1 deleted file mode 100644 index e0a0336c9ed..00000000000 --- a/soc/arm/arm/musca_s1/Kconfig.defconfig.musca_s1 +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2019-2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_V2M_MUSCA_S1 - -config SOC - default "musca_s1" - -config NUM_IRQS - default 96 - -endif diff --git a/soc/arm/arm/musca_s1/Kconfig.defconfig.series b/soc/arm/arm/musca_s1/Kconfig.defconfig.series deleted file mode 100644 index ae4e31a0e72..00000000000 --- a/soc/arm/arm/musca_s1/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2019-2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MUSCA_S1 - -config SOC_SERIES - default "musca_s1" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 50000000 - -source "soc/arm/arm/musca_s1/Kconfig.defconfig.musca_s1" - -endif # SOC_SERIES_MUSCA_S1 diff --git a/soc/arm/arm/musca_s1/Kconfig.series b/soc/arm/arm/musca_s1/Kconfig.series deleted file mode 100644 index 95b054e3d8a..00000000000 --- a/soc/arm/arm/musca_s1/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2019-2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MUSCA_S1 - bool "Arm v2m MUSCA-S1 MCU Series" - select ARM - select SOC_FAMILY_ARM - select BUILD_OUTPUT_HEX - help - Enable support for Arm V2M Musca-S1 MCU Series diff --git a/soc/arm/arm/musca_s1/Kconfig.soc b/soc/arm/arm/musca_s1/Kconfig.soc deleted file mode 100644 index 0c0763fae2a..00000000000 --- a/soc/arm/arm/musca_s1/Kconfig.soc +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2019-2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM Musca-S1 SoCs" - depends on SOC_SERIES_MUSCA_S1 - -config SOC_V2M_MUSCA_S1 - bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-S1" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select ARMV8_M_DSP - -endchoice diff --git a/soc/arm/aspeed/Kconfig b/soc/arm/aspeed/Kconfig deleted file mode 100644 index 78df65d605b..00000000000 --- a/soc/arm/aspeed/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -config SOC_FAMILY_ASPEED - select PLATFORM_SPECIFIC_INIT - bool - -if SOC_FAMILY_ASPEED - -config SOC_FAMILY - string - default "aspeed" - -source "soc/arm/aspeed/*/Kconfig.soc" - -endif # SOC_FAMILY_ASPEED diff --git a/soc/arm/aspeed/Kconfig.defconfig b/soc/arm/aspeed/Kconfig.defconfig deleted file mode 100644 index bbfbf4de751..00000000000 --- a/soc/arm/aspeed/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -source "soc/arm/aspeed/*/Kconfig.defconfig.series" diff --git a/soc/arm/aspeed/Kconfig.soc b/soc/arm/aspeed/Kconfig.soc deleted file mode 100644 index 3bd886a676a..00000000000 --- a/soc/arm/aspeed/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -source "soc/arm/aspeed/*/Kconfig.series" diff --git a/soc/arm/aspeed/ast10x0/CMakeLists.txt b/soc/arm/aspeed/ast10x0/CMakeLists.txt deleted file mode 100644 index 0d73ca4ba34..00000000000 --- a/soc/arm/aspeed/ast10x0/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2021 ASPEED Technology Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources(soc.c) -zephyr_include_directories(${ZEPHYR_BASE}/soc/arm/common/cortex_m) -zephyr_linker_sources(ROM_START SORT_KEY 0x1sboot sboot.ld) -zephyr_linker_sources(RAM_SECTIONS nocache.ld) - -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/${SOC_SERIES}/tools/gen_uart_booting_image.py - ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin - ${PROJECT_BINARY_DIR}/uart_${CONFIG_KERNEL_BIN_NAME}.bin -) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/aspeed/ast10x0/Kconfig.defconfig.series b/soc/arm/aspeed/ast10x0/Kconfig.defconfig.series deleted file mode 100644 index a6440b71d9d..00000000000 --- a/soc/arm/aspeed/ast10x0/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -if SOC_SERIES_AST10X0 - -source "soc/arm/aspeed/ast10x0/Kconfig.defconfig.ast10*0" - -config SOC_SERIES - default "ast10x0" - -config ICACHE_LINE_SIZE - default 32 - -config DCACHE_LINE_SIZE - default 32 - -choice CACHE_TYPE - default EXTERNAL_CACHE -endchoice - -endif # SOC_SERIES_AST10X0 diff --git a/soc/arm/aspeed/ast10x0/Kconfig.series b/soc/arm/aspeed/ast10x0/Kconfig.series deleted file mode 100644 index e4d0fdcd056..00000000000 --- a/soc/arm/aspeed/ast10x0/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -config SOC_SERIES_AST10X0 - bool "Aspeed AST10X0 Series" - select ARM - select CPU_CORTEX_M4 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_ASPEED - select SYSCON - select CACHE - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CACHE_MANAGEMENT - select CACHE_ASPEED - help - Enable support for ASPEED AST10X0 series diff --git a/soc/arm/aspeed/ast10x0/Kconfig.soc b/soc/arm/aspeed/ast10x0/Kconfig.soc deleted file mode 100644 index 84436257625..00000000000 --- a/soc/arm/aspeed/ast10x0/Kconfig.soc +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -choice - prompt "ASPEED AST10X0 Selection" - depends on SOC_SERIES_AST10X0 - -config SOC_AST1030 - bool "AST1030" - -endchoice - -config SRAM_NC_SIZE - int "noncached SRAM Size in kB" - help - The non-cached SRAM size in kB. The default value comes from reg[1] - of /chosen/zephyr,sram in devicetree. The user should generally avoid - changing it via menuconfig or in configuration files. - -config SRAM_NC_BASE_ADDRESS - hex "noncached SRAM Base Address" - help - The non-cached SRAM base address. The default value comes from from - reg[1] of /chosen/zephyr,sram in devicetree. The user should - generally avoid changing it via menuconfig or in configuration files. diff --git a/soc/arm/atmel_sam/CMakeLists.txt b/soc/arm/atmel_sam/CMakeLists.txt deleted file mode 100644 index d02e74e706b..00000000000 --- a/soc/arm/atmel_sam/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Makefile - Atmel SAM MCU family -# -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 -# - -add_subdirectory(${SOC_SERIES}) -add_subdirectory_ifdef(CONFIG_ASF common) diff --git a/soc/arm/atmel_sam/Kconfig b/soc/arm/atmel_sam/Kconfig deleted file mode 100644 index 963d90a450e..00000000000 --- a/soc/arm/atmel_sam/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Atmel SAM MCU family configuration options - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_SAM - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_SAM - -config SOC_FAMILY - string - default "atmel_sam" - -# Select SoC Part No. and configuration options -source "soc/arm/atmel_sam/*/Kconfig.soc" - -endif # SOC_FAMILY_SAM diff --git a/soc/arm/atmel_sam/Kconfig.defconfig b/soc/arm/atmel_sam/Kconfig.defconfig deleted file mode 100644 index f8a0e1ed576..00000000000 --- a/soc/arm/atmel_sam/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Atmel SAM MCU family default configuration options - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/atmel_sam/*/Kconfig.defconfig.series" - -if SOC_FAMILY_SAM - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config CLOCK_CONTROL - default y - -config PINCTRL - default y - -config WATCHDOG - default y - -endif # SOC_FAMILY_SAM diff --git a/soc/arm/atmel_sam/Kconfig.soc b/soc/arm/atmel_sam/Kconfig.soc deleted file mode 100644 index 688cd650b7f..00000000000 --- a/soc/arm/atmel_sam/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Atmel SAM MCU series selection - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/atmel_sam/*/Kconfig.series" diff --git a/soc/arm/atmel_sam/common/CMakeLists.txt b/soc/arm/atmel_sam/common/CMakeLists.txt deleted file mode 100644 index 3fe8bdd1d6d..00000000000 --- a/soc/arm/atmel_sam/common/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_pmc.c) -zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_gpio.c) -zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_supc.c) -zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_power.c) -zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_poweroff.c) - -zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_pm.c) -zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_gpio.c) -zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_poweroff.c) diff --git a/soc/arm/atmel_sam/sam3x/CMakeLists.txt b/soc/arm/atmel_sam/sam3x/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9..00000000000 --- a/soc/arm/atmel_sam/sam3x/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/sam3x/Kconfig.defconfig.series b/soc/arm/atmel_sam/sam3x/Kconfig.defconfig.series deleted file mode 100644 index 7873880dc58..00000000000 --- a/soc/arm/atmel_sam/sam3x/Kconfig.defconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Atmel SAM3X MCU series configuration options - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2016 Intel Corporation. -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAM3X - -config SOC_SERIES - default "sam3x" - -config SOC_PART_NUMBER - default "sam3x4c" if SOC_PART_NUMBER_SAM3X4C - default "sam3x4e" if SOC_PART_NUMBER_SAM3X4E - default "sam3x8c" if SOC_PART_NUMBER_SAM3X8C - default "sam3x8e" if SOC_PART_NUMBER_SAM3X8E - default "sam3x8h" if SOC_PART_NUMBER_SAM3X8H - -# -# SAM3 family has total 45 peripherals capable of -# generating interrupts. -# -config NUM_IRQS - default 45 - -endif # SOC_SERIES_SAM3X diff --git a/soc/arm/atmel_sam/sam3x/Kconfig.series b/soc/arm/atmel_sam/sam3x/Kconfig.series deleted file mode 100644 index 08a3781b6d3..00000000000 --- a/soc/arm/atmel_sam/sam3x/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Atmel SAM3X MCU series - -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# Copyright (c) 2016 Intel Corporation. -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAM3X - bool "Atmel SAM3X MCU" - select ARM - select CPU_CORTEX_M3 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select SOC_FAMILY_SAM - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_POWEROFF - help - Enable support for Atmel SAM3X Cortex-M3 microcontrollers. - Part No.: SAM3X8E diff --git a/soc/arm/atmel_sam/sam3x/Kconfig.soc b/soc/arm/atmel_sam/sam3x/Kconfig.soc deleted file mode 100644 index 1e9a203396a..00000000000 --- a/soc/arm/atmel_sam/sam3x/Kconfig.soc +++ /dev/null @@ -1,89 +0,0 @@ -# Atmel SAM3X MCU series - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2016 Intel Corporation. -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAM3X MCU Selection" - depends on SOC_SERIES_SAM3X - - config SOC_PART_NUMBER_SAM3X4C - bool "SAM3X4C" - config SOC_PART_NUMBER_SAM3X4E - bool "SAM3X4E" - config SOC_PART_NUMBER_SAM3X8C - bool "SAM3X8C" - config SOC_PART_NUMBER_SAM3X8E - bool "SAM3X8E" - config SOC_PART_NUMBER_SAM3X8H - bool "SAM3X8H" -endchoice - -if SOC_SERIES_SAM3X - -config SOC_ATMEL_SAM3X_EXT_SLCK - bool "Atmel SAM3 to use external crystal oscillator for slow clock" - help - Says y if you want to use external 32 kHz crystal - oscillator to drive the slow clock. Note that this - adds a few seconds to boot time, as the crystal - needs to stabilize after power-up. - - Says n if you do not need accurate and precise timers. - The slow clock will be driven by the internal fast - RC oscillator running at 32 kHz. - -config SOC_ATMEL_SAM3X_EXT_MAINCK - bool "Atmel SAM3 to use external crystal oscillator for main clock" - help - The main clock is being used to drive the PLL, and - thus driving the processor clock. - - Says y if you want to use external crystal oscillator - to drive the main clock. Note that this adds about - a second to boot time, as the crystal needs to - stabilize after power-up. - - The crystal used here can be from 3 to 20 MHz. - - Says n here will use the internal fast RC oscillator - running at 12 MHz. - -config SOC_ATMEL_SAM3X_PLLA_MULA - hex - default 0x06 - help - This is the multiplier (MULA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 6, and DIVA == 1, - PLL is running at 7 times of main clock. - -config SOC_ATMEL_SAM3X_PLLA_DIVA - hex - default 0x01 - help - This is the divider (DIVA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 6, and DIVA == 1, - PLL is running at 7 times of main clock. - -config SOC_ATMEL_SAM3X_WAIT_MODE - bool "Atmel SAM3 goes to Wait mode instead of Sleep mode" - depends on SOC_ATMEL_SAM3X_EXT_MAINCK - default y if DEBUG - help - For JTAG debugging CPU clock (HCLK) should not stop. In order - to achieve this, make CPU go to Wait mode instead of Sleep - mode while using external crystal oscillator for main clock. - -endif # SOC_SERIES_SAM3X diff --git a/soc/arm/atmel_sam/sam3x/soc.c b/soc/arm/atmel_sam/sam3x/soc.c deleted file mode 100644 index 9a20d566375..00000000000 --- a/soc/arm/atmel_sam/sam3x/soc.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2023 Gerson Fernando Budke - * Copyright (c) 2023 Basalte bv - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Atmel SAM3X MCU series initialization code - * - * This module provides routines to initialize and support board-level hardware - * for the Atmel SAM3X series processor. - */ - -#include -#include -#include - -/** - * @brief Setup various clocks on SoC at boot time. - * - * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. - * It is assumed that the relevant registers are at their reset value. - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Switch the main clock to the internal OSC with 12MHz */ - soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); - - /* Switch MCK (Master Clock) to the main clock */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); - - EFC0->EEFC_FMR = EEFC_FMR_FWS(0); - EFC1->EEFC_FMR = EEFC_FMR_FWS(0); - - soc_pmc_enable_clock_failure_detector(); - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_SLCK)) { - soc_supc_slow_clock_select_crystal_osc(); - } - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK)) { - /* - * Setup main external crystal oscillator. - */ - - /* We select maximum setup time. - * While start up time could be shortened - * this optimization is not deemed - * critical now. - */ - soc_pmc_switch_mainck_to_xtal(false, 0xff); - } - - /* - * Set FWS (Flash Wait State) value before increasing Master Clock - * (MCK) frequency. - * TODO: set FWS based on the actual MCK frequency and VDDCORE value - * rather than maximum supported 84 MHz at standard VDDCORE=1.8V - */ - EFC0->EEFC_FMR = EEFC_FMR_FWS(4); - EFC1->EEFC_FMR = EEFC_FMR_FWS(4); - - /* - * Setup PLLA - */ - - /* - * PLL clock = Main * (MULA + 1) / DIVA - * - * By default, MULA == 6, DIVA == 1. - * With main crystal running at 12 MHz, - * PLL = 12 * (6 + 1) / 1 = 84 MHz - * - * With Processor Clock prescaler at 1 - * Processor Clock (HCLK) = 84 MHz. - */ - soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM3X_PLLA_MULA, 0x3Fu, - CONFIG_SOC_ATMEL_SAM3X_PLLA_DIVA); - - /* - * Final setup of the Master Clock - */ - - /* prescaler has to be set before PLL lock */ - soc_pmc_mck_set_prescaler(1); - - /* Select PLL as Master Clock source. */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); - - /* Disable internal fast RC if we have an external crystal oscillator */ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK)) { - soc_pmc_osc_disable_fastrc(); - } -} - -void z_arm_platform_init(void) -{ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_WAIT_MODE)) { - /* - * Instruct CPU to enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG. - */ - soc_pmc_enable_waitmode(); - } - /* Setup system clocks */ - clock_init(); -} diff --git a/soc/arm/atmel_sam/sam3x/soc.h b/soc/arm/atmel_sam/sam3x/soc.h deleted file mode 100644 index 3fe78a7e6ba..00000000000 --- a/soc/arm/atmel_sam/sam3x/soc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Register access macros for the Atmel SAM3X MCU. - * - * This file provides register access macros for the Atmel SAM3X MCU, HAL - * drivers for core peripherals as well as symbols specific to Atmel SAM family. - */ - -#ifndef _ATMEL_SAM3X_SOC_H_ -#define _ATMEL_SAM3X_SOC_H_ - -#ifndef _ASMLANGUAGE - - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined CONFIG_SOC_PART_NUMBER_SAM3X4C -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAM3X4E -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAM3X8C -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAM3X8E -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAM3X8H -#include -#else -#error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/soc_supc.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ - -#endif /* _ASMLANGUAGE */ - -#endif /* _ATMEL_SAM3X_SOC_H_ */ diff --git a/soc/arm/atmel_sam/sam4e/CMakeLists.txt b/soc/arm/atmel_sam/sam4e/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9..00000000000 --- a/soc/arm/atmel_sam/sam4e/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/sam4e/Kconfig.defconfig.series b/soc/arm/atmel_sam/sam4e/Kconfig.defconfig.series deleted file mode 100644 index 779c0d5dbed..00000000000 --- a/soc/arm/atmel_sam/sam4e/Kconfig.defconfig.series +++ /dev/null @@ -1,33 +0,0 @@ -# Atmel SAM4E MCU series configuration options - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# Copyright (c) 2019 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAM4E - -config SOC_SERIES - default "sam4e" - -config SOC_PART_NUMBER - default "sam4e16e" if SOC_PART_NUMBER_SAM4E16E - default "sam4e16c" if SOC_PART_NUMBER_SAM4E16C - default "sam4e8e" if SOC_PART_NUMBER_SAM4E8E - default "sam4e8c" if SOC_PART_NUMBER_SAM4E8C - -# -# SAM4E family has total 47 peripherals capable of -# generating interrupts. -# -config NUM_IRQS - default 47 - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # SOC_SERIES_SAM4E diff --git a/soc/arm/atmel_sam/sam4e/Kconfig.series b/soc/arm/atmel_sam/sam4e/Kconfig.series deleted file mode 100644 index 93cc0e20a48..00000000000 --- a/soc/arm/atmel_sam/sam4e/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Atmel SAM4E MCU series - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# Copyright (c) 2019-2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAM4E - bool "Atmel SAM4E MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select SOC_FAMILY_SAM - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_POWEROFF - help - Enable support for Atmel SAM4E Cortex-M4 microcontrollers. - Part No.: SAM4E16E, SAM4E16C, SAM4E8E, SAM4E8C diff --git a/soc/arm/atmel_sam/sam4e/Kconfig.soc b/soc/arm/atmel_sam/sam4e/Kconfig.soc deleted file mode 100644 index e48e8de0170..00000000000 --- a/soc/arm/atmel_sam/sam4e/Kconfig.soc +++ /dev/null @@ -1,91 +0,0 @@ -# Atmel SAM4E MCU series - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# Copyright (c) 2019 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAM4E MCU Selection" - depends on SOC_SERIES_SAM4E - - config SOC_PART_NUMBER_SAM4E16E - bool "SAM4E16E" - - config SOC_PART_NUMBER_SAM4E16C - bool "SAM4E16C" - - config SOC_PART_NUMBER_SAM4E8E - bool "SAM4E8E" - - config SOC_PART_NUMBER_SAM4E8C - bool "SAM4E8C" - -endchoice - -if SOC_SERIES_SAM4E - -config SOC_ATMEL_SAM4E_EXT_SLCK - bool "Atmel SAM4E to use external crystal oscillator for slow clock" - help - Says y if you want to use external 32 kHz crystal - oscillator to drive the slow clock. Note that this - adds a few seconds to boot time, as the crystal - needs to stabilize after power-up. - - Says n if you do not need accurate and precise timers. - The slow clock will be driven by the internal fast - RC oscillator running at 32 kHz. - -config SOC_ATMEL_SAM4E_EXT_MAINCK - bool "Atmel SAM4E to use external crystal oscillator for main clock" - help - The main clock is being used to drive the PLL, and - thus driving the processor clock. - - Says y if you want to use external crystal oscillator - to drive the main clock. Note that this adds about - a second to boot time, as the crystal needs to - stabilize after power-up. - - The crystal used here can be from 3 to 20 MHz. - - Says n here will use the internal fast RC oscillator - running at 12 MHz. - -config SOC_ATMEL_SAM4E_PLLA_MULA - hex "PLL MULA" - default 0x09 - help - This is the multiplier (MULA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 9, and DIVA == 1, - PLL is running at 10 times of main clock. - -config SOC_ATMEL_SAM4E_PLLA_DIVA - hex "PLL DIVA" - default 0x01 - help - This is the divider (DIVA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 9, and DIVA == 1, - PLL is running at 10 times of main clock. - -config SOC_ATMEL_SAM4E_WAIT_MODE - bool "Atmel SAM4E goes to Wait mode instead of Sleep mode" - depends on SOC_ATMEL_SAM4E_EXT_MAINCK - default y if DEBUG - help - For JTAG debugging CPU clock (HCLK) should not stop. In order - to achieve this, make CPU go to Wait mode instead of Sleep - mode while using external crystal oscillator for main clock. - -endif # SOC_SERIES_SAM4E diff --git a/soc/arm/atmel_sam/sam4e/soc.c b/soc/arm/atmel_sam/sam4e/soc.c deleted file mode 100644 index b1c8174fddc..00000000000 --- a/soc/arm/atmel_sam/sam4e/soc.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2019-2023 Gerson Fernando Budke - * Copyright (c) 2023 Basalte bv - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Atmel SAM4E MCU series initialization code - * - * This module provides routines to initialize and support board-level hardware - * for the Atmel SAM4E series processor. - */ - -#include -#include -#include - -/** - * @brief Setup various clock on SoC at boot time. - * - * Setup the SoC clocks according to section 28.12 in datasheet. - * - * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. - * It is assumed that the relevant registers are at their reset value. - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Switch the main clock to the internal OSC with 12MHz */ - soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); - - /* Switch MCK (Master Clock) to the main clock */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); - - EFC->EEFC_FMR = EEFC_FMR_FWS(0); - - soc_pmc_enable_clock_failure_detector(); - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_SLCK)) { - soc_supc_slow_clock_select_crystal_osc(); - } - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK)) { - /* - * Setup main external crystal oscillator. - */ - - /* We select maximum setup time. - * While start up time could be shortened - * this optimization is not deemed - * critical now. - */ - soc_pmc_switch_mainck_to_xtal(false, 0xff); - } - - /* - * Set FWS (Flash Wait State) value before increasing Master Clock - * (MCK) frequency. Look at table 44.73 in the SAM4E datasheet. - * This is set to the highest number of read cycles because it won't - * hurt lower clock frequencies. However, a high frequency with too - * few read cycles could cause flash read problems. FWS 5 (6 cycles) - * is the safe setting for all of this SoCs usable frequencies. - */ - EFC->EEFC_FMR = EEFC_FMR_FWS(5); - - /* - * Setup PLLA - */ - soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM4E_PLLA_MULA, 0x3Fu, - CONFIG_SOC_ATMEL_SAM4E_PLLA_DIVA); - - /* - * Final setup of the Master Clock - */ - - /* prescaler has to be set before PLL lock */ - soc_pmc_mck_set_prescaler(1); - - /* Select PLL as Master Clock source. */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); - - /* Disable internal fast RC if we have an external crystal oscillator */ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK)) { - soc_pmc_osc_disable_fastrc(); - } -} - -void z_arm_platform_init(void) -{ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_WAIT_MODE)) { - /* - * Instruct CPU to enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG. - */ - soc_pmc_enable_waitmode(); - } - /* Setup system clocks. */ - clock_init(); -} diff --git a/soc/arm/atmel_sam/sam4e/soc.h b/soc/arm/atmel_sam/sam4e/soc.h deleted file mode 100644 index 290653e148a..00000000000 --- a/soc/arm/atmel_sam/sam4e/soc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2019-2020 Gerson Fernando Budke - * Copyright (c) 2018 Vincent van der Locht - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file SoC configuration macros for the Atmel SAM4E family processors. - */ - -#ifndef _ATMEL_SAM4E_SOC_H_ -#define _ATMEL_SAM4E_SOC_H_ - -#include - -#ifndef _ASMLANGUAGE - - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined(CONFIG_SOC_PART_NUMBER_SAM4E16E) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E16C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E8E) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E8C) -#include -#else -#error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/soc_supc.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ - -#endif /* !_ASMLANGUAGE */ - -#endif /* _ATMEL_SAM4E_SOC_H_ */ diff --git a/soc/arm/atmel_sam/sam4l/CMakeLists.txt b/soc/arm/atmel_sam/sam4l/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9..00000000000 --- a/soc/arm/atmel_sam/sam4l/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/sam4l/Kconfig.defconfig.series b/soc/arm/atmel_sam/sam4l/Kconfig.defconfig.series deleted file mode 100644 index 71fc855d112..00000000000 --- a/soc/arm/atmel_sam/sam4l/Kconfig.defconfig.series +++ /dev/null @@ -1,44 +0,0 @@ -# Copyright (c) 2020 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAM4L - -config SOC_SERIES - default "sam4l" - -config SOC_PART_NUMBER - default "sam4ls8c" if SOC_PART_NUMBER_SAM4LS8C - default "sam4ls8b" if SOC_PART_NUMBER_SAM4LS8B - default "sam4ls8a" if SOC_PART_NUMBER_SAM4LS8A - default "sam4ls4c" if SOC_PART_NUMBER_SAM4LS4C - default "sam4ls4b" if SOC_PART_NUMBER_SAM4LS4B - default "sam4ls4a" if SOC_PART_NUMBER_SAM4LS4A - default "sam4ls2c" if SOC_PART_NUMBER_SAM4LS2C - default "sam4ls2b" if SOC_PART_NUMBER_SAM4LS2B - default "sam4ls2a" if SOC_PART_NUMBER_SAM4LS2A - default "sam4lc8c" if SOC_PART_NUMBER_SAM4LC8C - default "sam4lc8b" if SOC_PART_NUMBER_SAM4LC8B - default "sam4lc8a" if SOC_PART_NUMBER_SAM4LC8A - default "sam4lc4c" if SOC_PART_NUMBER_SAM4LC4C - default "sam4lc4b" if SOC_PART_NUMBER_SAM4LC4B - default "sam4lc4a" if SOC_PART_NUMBER_SAM4LC4A - default "sam4lc2c" if SOC_PART_NUMBER_SAM4LC2C - default "sam4lc2b" if SOC_PART_NUMBER_SAM4LC2B - default "sam4lc2a" if SOC_PART_NUMBER_SAM4LC2A - -# -# SAM4L family has total 43 peripherals capable of -# generating interrupts. -# -config NUM_IRQS - default 80 - -# Configure default device drivers. If a feature is supported by more than one -# device driver the default configuration will be placed in the board defconfig -# file. - -config USART_SAM - default y - depends on SERIAL - -endif # SOC_SERIES_SAM4L diff --git a/soc/arm/atmel_sam/sam4l/Kconfig.series b/soc/arm/atmel_sam/sam4l/Kconfig.series deleted file mode 100644 index 0a8192f5bd9..00000000000 --- a/soc/arm/atmel_sam/sam4l/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2020-2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAM4L - bool "Atmel SAM4L MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select SOC_FAMILY_SAM - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_POWEROFF - help - Enable support for Atmel SAM4L Cortex-M4 microcontrollers. - Part No.: SAM4LS8C, SAM4LS8B, SAM4LS8A, SAM4LS4C, SAM4LS4B, - SAM4LS4A, SAM4LS2C, SAM4LS2B, SAM4LS2A, SAM4LC8C, SAM4LC8B, - SAM4LC8A, SAM4LC4C, SAM4LC4B, SAM4LC4A SAM4LC2C, SAM4LC2B, - SAM4LC2A diff --git a/soc/arm/atmel_sam/sam4l/Kconfig.soc b/soc/arm/atmel_sam/sam4l/Kconfig.soc deleted file mode 100644 index 358cfc76042..00000000000 --- a/soc/arm/atmel_sam/sam4l/Kconfig.soc +++ /dev/null @@ -1,61 +0,0 @@ -# Copyright (c) 2020 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAM4L MCU Selection" - depends on SOC_SERIES_SAM4L - - config SOC_PART_NUMBER_SAM4LS8C - bool "SAM4LS8C" - - config SOC_PART_NUMBER_SAM4LS8B - bool "SAM4LS8B" - - config SOC_PART_NUMBER_SAM4LS8A - bool "SAM4LS8A" - - config SOC_PART_NUMBER_SAM4LS4C - bool "SAM4LS4C" - - config SOC_PART_NUMBER_SAM4LS4B - bool "SAM4LS4B" - - config SOC_PART_NUMBER_SAM4LS4A - bool "SAM4LS4A" - - config SOC_PART_NUMBER_SAM4LS2C - bool "SAM4LS2C" - - config SOC_PART_NUMBER_SAM4LS2B - bool "SAM4LS2B" - - config SOC_PART_NUMBER_SAM4LS2A - bool "SAM4LS2A" - - config SOC_PART_NUMBER_SAM4LC8C - bool "SAM4LC8C" - - config SOC_PART_NUMBER_SAM4LC8B - bool "SAM4LC8B" - - config SOC_PART_NUMBER_SAM4LC8A - bool "SAM4LC8A" - - config SOC_PART_NUMBER_SAM4LC4C - bool "SAM4LC4C" - - config SOC_PART_NUMBER_SAM4LC4B - bool "SAM4LC4B" - - config SOC_PART_NUMBER_SAM4LC4A - bool "SAM4LC4A" - - config SOC_PART_NUMBER_SAM4LC2C - bool "SAM4LC2C" - - config SOC_PART_NUMBER_SAM4LC2B - bool "SAM4LC2B" - - config SOC_PART_NUMBER_SAM4LC2A - bool "SAM4LC2A" -endchoice diff --git a/soc/arm/atmel_sam/sam4l/soc.h b/soc/arm/atmel_sam/sam4l/soc.h deleted file mode 100644 index f044fc8363c..00000000000 --- a/soc/arm/atmel_sam/sam4l/soc.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2020 Gerson Fernando Budke - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file SoC configuration macros for the Atmel SAM4L family processors. - */ - -#ifndef _ATMEL_SAM4L_SOC_H_ -#define _ATMEL_SAM4L_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined(CONFIG_SOC_PART_NUMBER_SAM4LS8C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS8B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS8A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2A) -#include -#else -#error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ - -/** Oscillator identifiers - * External Oscillator 0 - * External 32 kHz oscillator - * Internal 32 kHz RC oscillator - * Internal 80 MHz RC oscillator - * Internal 4-8-12 MHz RCFAST oscillator - * Internal 1 MHz RC oscillator - * Internal System RC oscillator - */ -#define OSC_ID_OSC0 0 -#define OSC_ID_OSC32 1 -#define OSC_ID_RC32K 2 -#define OSC_ID_RC80M 3 -#define OSC_ID_RCFAST 4 -#define OSC_ID_RC1M 5 -#define OSC_ID_RCSYS 6 - -/** System clock source - * System RC oscillator - * Oscillator 0 - * Phase Locked Loop 0 - * Digital Frequency Locked Loop - * 80 MHz RC oscillator - * 4-8-12 MHz RC oscillator - * 1 MHz RC oscillator - */ -#define OSC_SRC_RCSYS 0 -#define OSC_SRC_OSC0 1 -#define OSC_SRC_PLL0 2 -#define OSC_SRC_DFLL 3 -#define OSC_SRC_RC80M 4 -#define OSC_SRC_RCFAST 5 -#define OSC_SRC_RC1M 6 - -#define PM_CLOCK_MASK(bus, per) ((bus << 5) + per) - -/** Bus index of maskable module clocks. Peripheral ids are defined out of - * order. It start from PBA up to PBD, then move to HSB, and finally CPU. - */ -#define PM_CLK_GRP_CPU 5 -#define PM_CLK_GRP_HSB 4 -#define PM_CLK_GRP_PBA 0 -#define PM_CLK_GRP_PBB 1 -#define PM_CLK_GRP_PBC 2 -#define PM_CLK_GRP_PBD 3 - -/** Clocks derived from the CPU clock - */ -#define SYSCLK_OCD 0 - -/** Clocks derived from the HSB clock - */ -#define SYSCLK_PDCA_HSB 0 -#define SYSCLK_HFLASHC_DATA 1 -#define SYSCLK_HRAMC1_DATA 2 -#define SYSCLK_USBC_DATA 3 -#define SYSCLK_CRCCU_DATA 4 -#define SYSCLK_PBA_BRIDGE 5 -#define SYSCLK_PBB_BRIDGE 6 -#define SYSCLK_PBC_BRIDGE 7 -#define SYSCLK_PBD_BRIDGE 8 -#define SYSCLK_AESA_HSB 9 - -/** Clocks derived from the PBA clock - */ -#define SYSCLK_IISC 0 -#define SYSCLK_SPI 1 -#define SYSCLK_TC0 2 -#define SYSCLK_TC1 3 -#define SYSCLK_TWIM0 4 -#define SYSCLK_TWIS0 5 -#define SYSCLK_TWIM1 6 -#define SYSCLK_TWIS1 7 -#define SYSCLK_USART0 8 -#define SYSCLK_USART1 9 -#define SYSCLK_USART2 10 -#define SYSCLK_USART3 11 -#define SYSCLK_ADCIFE 12 -#define SYSCLK_DACC 13 -#define SYSCLK_ACIFC 14 -#define SYSCLK_GLOC 15 -#define SYSCLK_ABDACB 16 -#define SYSCLK_TRNG 17 -#define SYSCLK_PARC 18 -#define SYSCLK_CATB 19 -#define SYSCLK_TWIM2 21 -#define SYSCLK_TWIM3 22 -#define SYSCLK_LCDCA 23 - -/** Clocks derived from the PBB clock - */ -#define SYSCLK_HFLASHC_REGS 0 -#define SYSCLK_HRAMC1_REGS 1 -#define SYSCLK_HMATRIX 2 -#define SYSCLK_PDCA_PB 3 -#define SYSCLK_CRCCU_REGS 4 -#define SYSCLK_USBC_REGS 5 -#define SYSCLK_PEVC 6 - -/** Clocks derived from the PBC clock - */ -#define SYSCLK_PM 0 -#define SYSCLK_CHIPID 1 -#define SYSCLK_SCIF 2 -#define SYSCLK_FREQM 3 -#define SYSCLK_GPIO 4 - -/** Clocks derived from the PBD clock - */ -#define SYSCLK_BPM 0 -#define SYSCLK_BSCIF 1 -#define SYSCLK_AST 2 -#define SYSCLK_WDT 3 -#define SYSCLK_EIC 4 -#define SYSCLK_PICOUART 5 - -/** Divided clock mask derived from the PBA clock - */ -#define PBA_DIVMASK_TIMER_CLOCK2 (1u << 0) -#define PBA_DIVMASK_TIMER_CLOCK3 (1u << 2) -#define PBA_DIVMASK_CLK_USART (1u << 2) -#define PBA_DIVMASK_TIMER_CLOCK4 (1u << 4) -#define PBA_DIVMASK_TIMER_CLOCK5 (1u << 6) -#define PBA_DIVMASK_Msk (0x7Fu << 0) - -/** Generic Clock Instances - * 0- DFLLIF main reference and GCLK0 pin (CLK_DFLLIF_REF) - * 1- DFLLIF dithering and SSG reference and GCLK1 pin (CLK_DFLLIF_DITHER) - * 2- AST and GCLK2 pin - * 3- CATB and GCLK3 pin - * 4- AESA - * 5- GLOC, TC0 and RC32KIFB_REF - * 6- ABDACB and IISC - * 7- USBC - * 8- TC1 and PEVC[0] - * 9- PLL0 and PEVC[1] - * 10- ADCIFE - * 11- Master generic clock. Can be used as source for other generic clocks. - */ -#define GEN_CLK_DFLL_REF 0 -#define GEN_CLK_DFLL_DITHER 1 -#define GEN_CLK_AST 2 -#define GEN_CLK_CATB 3 -#define GEN_CLK_AESA 4 -#define GEN_CLK_GLOC 5 -#define GEN_CLK_ABDACB 6 -#define GEN_CLK_USBC 7 -#define GEN_CLK_TC1_PEVC0 8 -#define GEN_CLK_PLL0_PEVC1 9 -#define GEN_CLK_ADCIFE 10 -#define GEN_CLK_MASTER_GEN 11 - -#endif /* !_ASMLANGUAGE */ - -#endif /* _ATMEL_SAM4L_SOC_H_ */ diff --git a/soc/arm/atmel_sam/sam4s/CMakeLists.txt b/soc/arm/atmel_sam/sam4s/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9..00000000000 --- a/soc/arm/atmel_sam/sam4s/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/sam4s/Kconfig.defconfig.series b/soc/arm/atmel_sam/sam4s/Kconfig.defconfig.series deleted file mode 100644 index 78afd905d63..00000000000 --- a/soc/arm/atmel_sam/sam4s/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Atmel SAM4S MCU series configuration options - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAM4S - -config SOC_SERIES - default "sam4s" - -config SOC_PART_NUMBER - default "sam4s16c" if SOC_PART_NUMBER_SAM4S16C - default "sam4sa16c" if SOC_PART_NUMBER_SAM4SA16C - default "sam4s16b" if SOC_PART_NUMBER_SAM4S16B - default "sam4s8c" if SOC_PART_NUMBER_SAM4S8C - default "sam4s8b" if SOC_PART_NUMBER_SAM4S8B - default "sam4s4c" if SOC_PART_NUMBER_SAM4S4C - default "sam4s4b" if SOC_PART_NUMBER_SAM4S4B - default "sam4s4a" if SOC_PART_NUMBER_SAM4S4A - default "sam4s2c" if SOC_PART_NUMBER_SAM4S2C - default "sam4s2b" if SOC_PART_NUMBER_SAM4S2B - default "sam4s2a" if SOC_PART_NUMBER_SAM4S2A - -# -# SAM4S family has total 35 peripherals capable of -# generating interrupts. -# -config NUM_IRQS - default 35 - -endif # SOC_SERIES_SAM4S diff --git a/soc/arm/atmel_sam/sam4s/Kconfig.series b/soc/arm/atmel_sam/sam4s/Kconfig.series deleted file mode 100644 index f591d96ba88..00000000000 --- a/soc/arm/atmel_sam/sam4s/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Atmel SAM4S MCU series - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# Copyright (c) 2020-2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAM4S - bool "Atmel SAM4S MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select SOC_FAMILY_SAM - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_POWEROFF - help - Enable support for Atmel SAM4S Cortex-M4 microcontrollers. - Part No.: SAM4S16C, SAM4S16B, SAM4S8C, SAM4S8B, - SAM4S4C, SAM4S4B, SAM4S4A, SAM4S2C, SAM4S2B, SAM4S2A diff --git a/soc/arm/atmel_sam/sam4s/Kconfig.soc b/soc/arm/atmel_sam/sam4s/Kconfig.soc deleted file mode 100644 index c8c9dd9e21e..00000000000 --- a/soc/arm/atmel_sam/sam4s/Kconfig.soc +++ /dev/null @@ -1,111 +0,0 @@ -# Atmel SAM4S MCU series - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAM4S MCU Selection" - depends on SOC_SERIES_SAM4S - - config SOC_PART_NUMBER_SAM4S16C - bool "SAM4S16C" - - config SOC_PART_NUMBER_SAM4SA16C - bool "SAM4SA16C" - - config SOC_PART_NUMBER_SAM4S16B - bool "SAM4S16B" - - config SOC_PART_NUMBER_SAM4S8C - bool "SAM4S8C" - - config SOC_PART_NUMBER_SAM4S8B - bool "SAM4S8B" - - config SOC_PART_NUMBER_SAM4S4C - bool "SAM4S4C" - - config SOC_PART_NUMBER_SAM4S4B - bool "SAM4S4B" - - config SOC_PART_NUMBER_SAM4S4A - bool "SAM4S4A" - - config SOC_PART_NUMBER_SAM4S2C - bool "SAM4S2C" - - config SOC_PART_NUMBER_SAM4S2B - bool "SAM4S2B" - - config SOC_PART_NUMBER_SAM4S2A - bool "SAM4S2A" - -endchoice - -if SOC_SERIES_SAM4S - -config SOC_ATMEL_SAM4S_EXT_SLCK - bool "Atmel SAM4S to use external crystal oscillator for slow clock" - help - Says y if you want to use external 32 kHz crystal - oscillator to drive the slow clock. Note that this - adds a few seconds to boot time, as the crystal - needs to stabilize after power-up. - - Says n if you do not need accurate and precise timers. - The slow clock will be driven by the internal fast - RC oscillator running at 32 kHz. - -config SOC_ATMEL_SAM4S_EXT_MAINCK - bool "Atmel SAM4S to use external crystal oscillator for main clock" - help - The main clock is being used to drive the PLL, and - thus driving the processor clock. - - Says y if you want to use external crystal oscillator - to drive the main clock. Note that this adds about - a second to boot time, as the crystal needs to - stabilize after power-up. - - The crystal used here can be from 3 to 20 MHz. - - Says n here will use the internal fast RC oscillator - running at 12 MHz. - -config SOC_ATMEL_SAM4S_PLLA_MULA - hex "PLL MULA" - default 0x09 - help - This is the multiplier (MULA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 9, and DIVA == 1, - PLL is running at 10 times of main clock. - -config SOC_ATMEL_SAM4S_PLLA_DIVA - hex "PLL DIVA" - default 0x01 - help - This is the divider (DIVA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 9, and DIVA == 1, - PLL is running at 10 times of main clock. - -config SOC_ATMEL_SAM4S_WAIT_MODE - bool "Atmel SAM4S goes to Wait mode instead of Sleep mode" - depends on SOC_ATMEL_SAM4S_EXT_MAINCK - default y if DEBUG - help - For JTAG debugging CPU clock (HCLK) should not stop. In order - to achieve this, make CPU go to Wait mode instead of Sleep - mode while using external crystal oscillator for main clock. - -endif # SOC_SERIES_SAM4S diff --git a/soc/arm/atmel_sam/sam4s/soc.c b/soc/arm/atmel_sam/sam4s/soc.c deleted file mode 100644 index 5efaa35e894..00000000000 --- a/soc/arm/atmel_sam/sam4s/soc.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2023 Gerson Fernando Budke - * Copyright (c) 2023 Basalte bv - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Atmel SAM4S MCU series initialization code - * - * This module provides routines to initialize and support board-level hardware - * for the Atmel SAM4S series processor. - */ - -#include -#include -#include - -/** - * @brief Setup various clock on SoC at boot time. - * - * Setup the SoC clocks according to section 28.12 in datasheet. - * - * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. - * It is assumed that the relevant registers are at their reset value. - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Switch the main clock to the internal OSC with 12MHz */ - soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); - - /* Switch MCK (Master Clock) to the main clock */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); - - EFC0->EEFC_FMR = EEFC_FMR_FWS(0); -#if defined(ID_EFC1) - EFC1->EEFC_FMR = EEFC_FMR_FWS(0); -#endif - - soc_pmc_enable_clock_failure_detector(); - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_SLCK)) { - soc_supc_slow_clock_select_crystal_osc(); - } - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK)) { - /* - * Setup main external crystal oscillator. - */ - - /* We select maximum setup time. - * While start up time could be shortened - * this optimization is not deemed - * critical now. - */ - soc_pmc_switch_mainck_to_xtal(false, 0xff); - } - - /* - * Set FWS (Flash Wait State) value before increasing Master Clock - * (MCK) frequency. Look at table 44.73 in the SAM4S datasheet. - * This is set to the highest number of read cycles because it won't - * hurt lower clock frequencies. However, a high frequency with too - * few read cycles could cause flash read problems. FWS 5 (6 cycles) - * is the safe setting for all of this SoCs usable frequencies. - */ - EFC0->EEFC_FMR = EEFC_FMR_FWS(5); -#if defined(ID_EFC1) - EFC1->EEFC_FMR = EEFC_FMR_FWS(5); -#endif - - /* - * Setup PLLA - */ - soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM4S_PLLA_MULA, 0x3Fu, - CONFIG_SOC_ATMEL_SAM4S_PLLA_DIVA); - - /* - * Final setup of the Master Clock - */ - - /* prescaler has to be set before PLL lock */ - soc_pmc_mck_set_prescaler(1); - - /* Select PLL as Master Clock source. */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); - - /* Disable internal fast RC if we have an external crystal oscillator */ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK)) { - soc_pmc_osc_disable_fastrc(); - } -} - -void z_arm_platform_init(void) -{ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_WAIT_MODE)) { - /* - * Instruct CPU to enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG. - */ - soc_pmc_enable_waitmode(); - } - - /* Setup system clocks. */ - clock_init(); -} diff --git a/soc/arm/atmel_sam/sam4s/soc.h b/soc/arm/atmel_sam/sam4s/soc.h deleted file mode 100644 index ec3ab20471e..00000000000 --- a/soc/arm/atmel_sam/sam4s/soc.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2020 Gerson Fernando Budke - * Copyright (c) 2018 Vincent van der Locht - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file SoC configuration macros for the Atmel SAM4S family processors. - */ - -#ifndef _ATMEL_SAM4S_SOC_H_ -#define _ATMEL_SAM4S_SOC_H_ - -#include - -#ifndef _ASMLANGUAGE - - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined(CONFIG_SOC_PART_NUMBER_SAM4S16C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4SA16C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S8C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S8B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S4C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S4B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S4A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S2C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S2B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S2A) -#include -#else -#error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/soc_supc.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ - -#endif /* !_ASMLANGUAGE */ - -#endif /* _ATMEL_SAM4S_SOC_H_ */ diff --git a/soc/arm/atmel_sam/same70/CMakeLists.txt b/soc/arm/atmel_sam/same70/CMakeLists.txt deleted file mode 100644 index 8373266d4ec..00000000000 --- a/soc/arm/atmel_sam/same70/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - soc_config.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/same70/Kconfig.defconfig.series b/soc/arm/atmel_sam/same70/Kconfig.defconfig.series deleted file mode 100644 index f024e0d0616..00000000000 --- a/soc/arm/atmel_sam/same70/Kconfig.defconfig.series +++ /dev/null @@ -1,41 +0,0 @@ -# Atmel SAM E70 MCU series configuration options - -# Copyright (c) 2016 Piotr Mienkowski -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAME70 - -config SOC_SERIES - default "same70" - -config SOC_PART_NUMBER - default "same70q21" if SOC_PART_NUMBER_SAME70Q21 - default "same70q20" if SOC_PART_NUMBER_SAME70Q20 - default "same70q19" if SOC_PART_NUMBER_SAME70Q19 - default "same70n21" if SOC_PART_NUMBER_SAME70N21 - default "same70n20" if SOC_PART_NUMBER_SAME70N20 - default "same70n19" if SOC_PART_NUMBER_SAME70N19 - default "same70j21" if SOC_PART_NUMBER_SAME70J21 - default "same70j20" if SOC_PART_NUMBER_SAME70J20 - default "same70j19" if SOC_PART_NUMBER_SAME70J19 - default "same70q21b" if SOC_PART_NUMBER_SAME70Q21B - default "same70q20b" if SOC_PART_NUMBER_SAME70Q20B - default "same70q19b" if SOC_PART_NUMBER_SAME70Q19B - default "same70n21b" if SOC_PART_NUMBER_SAME70N21B - default "same70n20b" if SOC_PART_NUMBER_SAME70N20B - default "same70n19b" if SOC_PART_NUMBER_SAME70N19B - default "same70j21b" if SOC_PART_NUMBER_SAME70J21B - default "same70j20b" if SOC_PART_NUMBER_SAME70J20B - default "same70j19b" if SOC_PART_NUMBER_SAME70J19B - -# -# SAM E70 family has in total 71 peripherals capable of generating interrupts -# for the revision A and 74 for the revision B (not all Peripheral Identifiers -# are used). -# -config NUM_IRQS - default 74 if SOC_ATMEL_SAME70_REVB - default 71 - -endif # SOC_SERIES_SAME70 diff --git a/soc/arm/atmel_sam/same70/Kconfig.series b/soc/arm/atmel_sam/same70/Kconfig.series deleted file mode 100644 index 4e7d6aa396e..00000000000 --- a/soc/arm/atmel_sam/same70/Kconfig.series +++ /dev/null @@ -1,28 +0,0 @@ -# Atmel SAM E70 MCU series - -# Copyright (c) 2016 Piotr Mienkowski -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAME70 - bool "Atmel SAME70 MCU" - select ARM - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select SOC_FAMILY_SAM - select INIT_ARCH_HW_AT_BOOT - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_SWO - select XIP - select HAS_POWEROFF - help - Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers. - Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20, - SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21, SAME70J19B, SAME70J20B, - SAME70J21B, SAME70N19B, SAME70N20B, SAME70N21B, SAME70Q19B, - SAME70Q20B, SAME70Q21B diff --git a/soc/arm/atmel_sam/same70/Kconfig.soc b/soc/arm/atmel_sam/same70/Kconfig.soc deleted file mode 100644 index c396e1e59d7..00000000000 --- a/soc/arm/atmel_sam/same70/Kconfig.soc +++ /dev/null @@ -1,167 +0,0 @@ -# Atmel SAM E70 MCU series - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAME70 MCU Selection" - depends on SOC_SERIES_SAME70 - - config SOC_PART_NUMBER_SAME70Q21 - bool "SAME70Q21" - - config SOC_PART_NUMBER_SAME70Q20 - bool "SAME70Q20" - - config SOC_PART_NUMBER_SAME70Q19 - bool "SAME70Q19" - - config SOC_PART_NUMBER_SAME70N21 - bool "SAME70N21" - - config SOC_PART_NUMBER_SAME70N20 - bool "SAME70N20" - - config SOC_PART_NUMBER_SAME70N19 - bool "SAME70N19" - - config SOC_PART_NUMBER_SAME70J21 - bool "SAME70J21" - - config SOC_PART_NUMBER_SAME70J20 - bool "SAME70J20" - - config SOC_PART_NUMBER_SAME70J19 - bool "SAME70J19" - - config SOC_PART_NUMBER_SAME70Q21B - bool "SAME70Q21B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70Q20B - bool "SAME70Q20B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70Q19B - bool "SAME70Q19B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70N21B - bool "SAME70N21B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70N20B - bool "SAME70N20B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70N19B - bool "SAME70N19B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70J21B - bool "SAME70J21B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70J20B - bool "SAME70J20B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70J19B - bool "SAME70J19B" - select SOC_ATMEL_SAME70_REVB -endchoice - -if SOC_SERIES_SAME70 - -config SOC_ATMEL_SAME70_REVB - bool - -config SOC_ATMEL_SAME70_EXT_SLCK - bool "Use external crystal oscillator for slow clock" - help - Say y if you want to use external 32 kHz crystal - oscillator to drive the slow clock. Note that this - adds a few seconds to boot time, as the crystal - needs to stabilize after power-up. - - Says n if you do not need accurate and precise timers. - The slow clock will be driven by the internal fast - RC oscillator running at 32 kHz. - -config SOC_ATMEL_SAME70_EXT_MAINCK - bool "Use external crystal oscillator for main clock" - help - The main clock is being used to drive the PLL, and - thus driving the processor clock. - - Say y if you want to use external crystal oscillator - to drive the main clock. Note that this adds about - a second to boot time, as the crystal needs to - stabilize after power-up. - - The crystal used here can be from 3 to 20 MHz. - - Says n here will use the internal fast RC oscillator - running at 12 MHz. - -config SOC_ATMEL_SAME70_MDIV - int "MDIV" - default 2 - range 1 4 - help - This divisor defines a ratio between processor clock (HCLK) - and master clock (MCK): - MCK = HCLK / MDIV - -config SOC_ATMEL_SAME70_PLLA_MULA - int "PLL MULA" - default 24 - range 1 62 - help - This is the multiplier MULA used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - Setting MULA=0 would disable PLL at boot, this is currently - not supported. - - With default of MULA == 24, and DIVA == 1, - PLL is running at 25 times the main clock frequency. - -config SOC_ATMEL_SAME70_PLLA_DIVA - int "PLL DIVA" - default 1 - range 1 255 - help - This is the divider DIVA used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - Setting DIVA=0 would disable PLL at boot, this is currently - not supported. - - With default of MULA == 24, and DIVA == 1, - PLL is running at 25 times the main clock frequency. - -config SOC_ATMEL_SAME70_WAIT_MODE - bool "Go to Wait mode instead of Sleep mode" - depends on SOC_ATMEL_SAME70_EXT_MAINCK - default y if DEBUG - help - For JTAG debugging CPU clock (HCLK) should not stop. In order - to achieve this, make CPU go to Wait mode instead of Sleep - mode while using external crystal oscillator for main clock. - -config SOC_ATMEL_SAME70_DISABLE_ERASE_PIN - bool "Disable ERASE pin" - help - At reset ERASE pin is configured in System IO mode. Asserting the ERASE - pin at '1' will completely erase Flash memory. Setting this option will - switch the pin to general IO mode giving control of the pin to the GPIO - module. - -endif # SOC_SERIES_SAME70 diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c deleted file mode 100644 index 02ebce73c6d..00000000000 --- a/soc/arm/atmel_sam/same70/soc.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2016 Piotr Mienkowski - * Copyright (c) 2023 Gerson Fernando Budke - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Atmel SAM E70 MCU initialization code - * - * This file provides routines to initialize and support board-level hardware - * for the Atmel SAM E70 MCU. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL -LOG_MODULE_REGISTER(soc); - -/** - * @brief Setup various clocks on SoC at boot time. - * - * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. - * It is assumed that the relevant registers are at their reset value. - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Switch the main clock to the internal OSC with 12MHz */ - soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); - - /* Switch MCK (Master Clock) to the main clock */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); - - EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; - - soc_pmc_enable_clock_failure_detector(); - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_SLCK)) { - soc_supc_slow_clock_select_crystal_osc(); - } - - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK)) { - /* - * Setup main external crystal oscillator. - */ - - /* We select maximum setup time. - * While start up time could be shortened - * this optimization is not deemed - * critical now. - */ - soc_pmc_switch_mainck_to_xtal(false, 0xff); - } - - /* - * Set FWS (Flash Wait State) value before increasing Master Clock - * (MCK) frequency. - * TODO: set FWS based on the actual MCK frequency and VDDIO value - * rather than maximum supported 150 MHz at standard VDDIO=2.7V - */ - EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; - - /* - * Setup PLLA - */ - - /* - * PLL clock = Main * (MULA + 1) / DIVA - * - * By default, MULA == 24, DIVA == 1. - * With main crystal running at 12 MHz, - * PLL = 12 * (24 + 1) / 1 = 300 MHz - * - * With Processor Clock prescaler at 1 - * Processor Clock (HCLK)=300 MHz. - */ - soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAME70_PLLA_MULA, 0x3Fu, - CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA); - - - soc_pmc_enable_upllck(0x3Fu); - - /* - * Final setup of the Master Clock - */ - - /* Setting PLLA as MCK, first prescaler, then divider and source last */ - soc_pmc_mck_set_prescaler(1); - soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAME70_MDIV); - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); - - - /* Disable internal fast RC if we have an external crystal oscillator */ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK)) { - soc_pmc_osc_disable_fastrc(); - } -} - -void z_arm_platform_init(void) -{ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_WAIT_MODE)) { - /* - * Instruct CPU to enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG. - */ - soc_pmc_enable_waitmode(); - } - - /* - * DTCM is enabled by default at reset, therefore we have to disable - * it first to get the caches into a state where then the - * sys_cache*-functions can enable them, if requested by the - * configuration. - */ - SCB_DisableDCache(); - - /* - * Enable the caches only if configured to do so. - */ - sys_cache_instr_enable(); - sys_cache_data_enable(); - - /* Setup system clocks */ - clock_init(); -} - -/** - * @brief Perform basic hardware initialization at boot. - * - * This needs to be run at the very beginning. - * So the init priority has to be 0 (zero). - * - * @return 0 - */ -static int atmel_same70_init(void) -{ - /* Check that the CHIP CIDR matches the HAL one */ - if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { - LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", - (uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR); - } - - return 0; -} - -SYS_INIT(atmel_same70_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/atmel_sam/same70/soc.h b/soc/arm/atmel_sam/same70/soc.h deleted file mode 100644 index ad72b4d2ef0..00000000000 --- a/soc/arm/atmel_sam/same70/soc.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2016 Piotr Mienkowski - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Register access macros for the Atmel SAM E70 MCU. - * - * This file provides register access macros for the Atmel SAM E70 MCU, HAL - * drivers for core peripherals as well as symbols specific to Atmel SAM family. - */ - -#ifndef _ATMEL_SAME70_SOC_H_ -#define _ATMEL_SAME70_SOC_H_ - -#include - -#ifndef _ASMLANGUAGE - - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined CONFIG_SOC_PART_NUMBER_SAME70J19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70J20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70J21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70J19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70J20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70J21B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N21B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q21B -#include -#else - #error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/soc_supc.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ \ - (SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAME70_MDIV) - -/** UTMI PLL clock (UPLLCK) Frequency */ -#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480) - -#endif /* _ASMLANGUAGE */ - -#endif /* _ATMEL_SAME70_SOC_H_ */ diff --git a/soc/arm/atmel_sam/same70/soc_config.c b/soc/arm/atmel_sam/same70/soc_config.c deleted file mode 100644 index 27d71da4920..00000000000 --- a/soc/arm/atmel_sam/same70/soc_config.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2016 Piotr Mienkowski - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief System module to support early Atmel SAM E70 MCU configuration - */ - -#include -#include -#include -#include - -/** - * @brief Perform SoC configuration at boot. - * - * This should be run early during the boot process but after basic hardware - * initialization is done. - * - * @return 0 - */ -static int atmel_same70_config(void) -{ -#ifdef CONFIG_SOC_ATMEL_SAME70_DISABLE_ERASE_PIN - /* Disable ERASE function on PB12 pin, this is controlled by Bus Matrix */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; -#endif - - /* In Cortex-M based SoCs JTAG interface can be used to perform - * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug - * interface therefore there is no harm done by disabling the JTAG TDI - * pin by default. - */ - /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; - -#ifdef CONFIG_LOG_BACKEND_SWO - /* Disable PCK3 clock used by ETM module */ - PMC->PMC_SCDR = PMC_SCDR_PCK3; - while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { - ; - } - /* Select PLLA clock as PCK3 clock */ - PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; - /* Enable PCK3 clock */ - PMC->PMC_SCER = PMC_SCER_PCK3; - /* Wait for PCK3 setup to complete */ - while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { - ; - } - /* Enable TDO/TRACESWO function on PB5 pin */ - MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5; -#else - /* Disable TDO/TRACESWO function on PB5 pin */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5; -#endif - - return 0; -} - -SYS_INIT(atmel_same70_config, PRE_KERNEL_1, 1); diff --git a/soc/arm/atmel_sam/samv71/CMakeLists.txt b/soc/arm/atmel_sam/samv71/CMakeLists.txt deleted file mode 100644 index 8373266d4ec..00000000000 --- a/soc/arm/atmel_sam/samv71/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - soc_config.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series b/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series deleted file mode 100644 index 5209139f61c..00000000000 --- a/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series +++ /dev/null @@ -1,41 +0,0 @@ -# Atmel SAM V71 MCU series configuration options - -# Copyright (c) 2016 Piotr Mienkowski -# Copyright (c) 2019-2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMV71 - -config SOC_SERIES - default "samv71" - -config SOC_PART_NUMBER - default "samv71q21" if SOC_PART_NUMBER_SAMV71Q21 - default "samv71q20" if SOC_PART_NUMBER_SAMV71Q20 - default "samv71q19" if SOC_PART_NUMBER_SAMV71Q19 - default "samv71n21" if SOC_PART_NUMBER_SAMV71N21 - default "samv71n20" if SOC_PART_NUMBER_SAMV71N20 - default "samv71n19" if SOC_PART_NUMBER_SAMV71N19 - default "samv71j21" if SOC_PART_NUMBER_SAMV71J21 - default "samv71j20" if SOC_PART_NUMBER_SAMV71J20 - default "samv71j19" if SOC_PART_NUMBER_SAMV71J19 - default "samv71q21b" if SOC_PART_NUMBER_SAMV71Q21B - default "samv71q20b" if SOC_PART_NUMBER_SAMV71Q20B - default "samv71q19b" if SOC_PART_NUMBER_SAMV71Q19B - default "samv71n21b" if SOC_PART_NUMBER_SAMV71N21B - default "samv71n20b" if SOC_PART_NUMBER_SAMV71N20B - default "samv71n19b" if SOC_PART_NUMBER_SAMV71N19B - default "samv71j21b" if SOC_PART_NUMBER_SAMV71J21B - default "samv71j20b" if SOC_PART_NUMBER_SAMV71J20B - default "samv71j19b" if SOC_PART_NUMBER_SAMV71J19B - -# -# SAM V71 family has in total 71 peripherals capable of generating interrupts -# for the revision A and 74 for the revision B (not all Peripheral Identifiers -# are used). -# -config NUM_IRQS - default 74 if SOC_ATMEL_SAMV71_REVB - default 71 - -endif # SOC_SERIES_SAMV71 diff --git a/soc/arm/atmel_sam/samv71/Kconfig.series b/soc/arm/atmel_sam/samv71/Kconfig.series deleted file mode 100644 index cadee35acb5..00000000000 --- a/soc/arm/atmel_sam/samv71/Kconfig.series +++ /dev/null @@ -1,28 +0,0 @@ -# Atmel SAM V71 MCU series - -# Copyright (c) 2016 Piotr Mienkowski -# Copyright (c) 2019-2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMV71 - bool "Atmel SAMV71 MCU" - select ARM - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select SOC_FAMILY_SAM - select INIT_ARCH_HW_AT_BOOT - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_SWO - select XIP - select HAS_POWEROFF - help - Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers. - Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20, - SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B, - SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B, - SAMV71Q20B, SAMV71Q21B diff --git a/soc/arm/atmel_sam/samv71/Kconfig.soc b/soc/arm/atmel_sam/samv71/Kconfig.soc deleted file mode 100644 index c8e7d60438c..00000000000 --- a/soc/arm/atmel_sam/samv71/Kconfig.soc +++ /dev/null @@ -1,168 +0,0 @@ -# Atmel SAM V71 MCU series - -# Copyright (c) 2019 Gerson Fernando Budke -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMV71 MCU Selection" - depends on SOC_SERIES_SAMV71 - - config SOC_PART_NUMBER_SAMV71Q21 - bool "SAMV71Q21" - - config SOC_PART_NUMBER_SAMV71Q20 - bool "SAMV71Q20" - - config SOC_PART_NUMBER_SAMV71Q19 - bool "SAMV71Q19" - - config SOC_PART_NUMBER_SAMV71N21 - bool "SAMV71N21" - - config SOC_PART_NUMBER_SAMV71N20 - bool "SAMV71N20" - - config SOC_PART_NUMBER_SAMV71N19 - bool "SAMV71N19" - - config SOC_PART_NUMBER_SAMV71J21 - bool "SAMV71J21" - - config SOC_PART_NUMBER_SAMV71J20 - bool "SAMV71J20" - - config SOC_PART_NUMBER_SAMV71J19 - bool "SAMV71J19" - - config SOC_PART_NUMBER_SAMV71Q21B - bool "SAMV71Q21B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71Q20B - bool "SAMV71Q20B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71Q19B - bool "SAMV71Q19B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71N21B - bool "SAMV71N21B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71N20B - bool "SAMV71N20B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71N19B - bool "SAMV71N19B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71J21B - bool "SAMV71J21B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71J20B - bool "SAMV71J20B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71J19B - bool "SAMV71J19B" - select SOC_ATMEL_SAMV71_REVB -endchoice - -if SOC_SERIES_SAMV71 - -config SOC_ATMEL_SAMV71_REVB - bool - -config SOC_ATMEL_SAMV71_EXT_SLCK - bool "Use external crystal oscillator for slow clock" - help - Say y if you want to use external 32 kHz crystal - oscillator to drive the slow clock. Note that this - adds a few seconds to boot time, as the crystal - needs to stabilize after power-up. - - Says n if you do not need accurate and precise timers. - The slow clock will be driven by the internal fast - RC oscillator running at 32 kHz. - -config SOC_ATMEL_SAMV71_EXT_MAINCK - bool "Use external crystal oscillator for main clock" - help - The main clock is being used to drive the PLL, and - thus driving the processor clock. - - Say y if you want to use external crystal oscillator - to drive the main clock. Note that this adds about - a second to boot time, as the crystal needs to - stabilize after power-up. - - The crystal used here can be from 3 to 20 MHz. - - Says n here will use the internal fast RC oscillator - running at 12 MHz. - -config SOC_ATMEL_SAMV71_MDIV - int "MDIV" - default 2 - range 1 4 - help - This divisor defines a ratio between processor clock (HCLK) - and master clock (MCK): - MCK = HCLK / MDIV - -config SOC_ATMEL_SAMV71_PLLA_MULA - int "PLL MULA" - default 24 - range 1 62 - help - This is the multiplier MULA used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - Setting MULA=0 would disable PLL at boot, this is currently - not supported. - - With default of MULA == 24, and DIVA == 1, - PLL is running at 25 times the main clock frequency. - -config SOC_ATMEL_SAMV71_PLLA_DIVA - int "PLL DIVA" - default 1 - range 1 255 - help - This is the divider DIVA used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - Setting DIVA=0 would disable PLL at boot, this is currently - not supported. - - With default of MULA == 24, and DIVA == 1, - PLL is running at 25 times the main clock frequency. - -config SOC_ATMEL_SAMV71_WAIT_MODE - bool "Go to Wait mode instead of Sleep mode" - depends on SOC_ATMEL_SAMV71_EXT_MAINCK - default y if DEBUG - help - For JTAG debugging CPU clock (HCLK) should not stop. In order - to achieve this, make CPU go to Wait mode instead of Sleep - mode while using external crystal oscillator for main clock. - -config SOC_ATMEL_SAMV71_DISABLE_ERASE_PIN - bool "Disable ERASE pin" - help - At reset ERASE pin is configured in System IO mode. Asserting the ERASE - pin at '1' will completely erase Flash memory. Setting this option will - switch the pin to general IO mode giving control of the pin to the GPIO - module. - -endif # SOC_SERIES_SAMV71 diff --git a/soc/arm/atmel_sam/samv71/soc.c b/soc/arm/atmel_sam/samv71/soc.c deleted file mode 100644 index 6e82b9fe2f6..00000000000 --- a/soc/arm/atmel_sam/samv71/soc.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2016 Piotr Mienkowski - * Copyright (c) 2019-2023 Gerson Fernando Budke - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Atmel SAM V71 MCU initialization code - * - * This file provides routines to initialize and support board-level hardware - * for the Atmel SAM V71 MCU. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL -LOG_MODULE_REGISTER(soc); - -/** - * @brief Setup various clocks on SoC at boot time. - * - * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. - * It is assumed that the relevant registers are at their reset value. - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Switch the main clock to the internal OSC with 12MHz */ - soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); - - /* Switch MCK (Master Clock) to the main clock */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); - - EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; - - soc_pmc_enable_clock_failure_detector(); - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_EXT_SLCK)) { - soc_supc_slow_clock_select_crystal_osc(); - } - - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK)) { - /* - * Setup main external crystal oscillator. - */ - - /* We select maximum setup time. - * While start up time could be shortened - * this optimization is not deemed - * critical now. - */ - soc_pmc_switch_mainck_to_xtal(false, 0xff); - } - - /* - * Set FWS (Flash Wait State) value before increasing Master Clock - * (MCK) frequency. - * TODO: set FWS based on the actual MCK frequency and VDDIO value - * rather than maximum supported 150 MHz at standard VDDIO=2.7V - */ - EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; - - /* - * Setup PLLA - */ - - /* - * PLL clock = Main * (MULA + 1) / DIVA - * - * By default, MULA == 24, DIVA == 1. - * With main crystal running at 12 MHz, - * PLL = 12 * (24 + 1) / 1 = 300 MHz - * - * With Processor Clock prescaler at 1 - * Processor Clock (HCLK)=300 MHz. - */ - soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAMV71_PLLA_MULA, 0x3Fu, - CONFIG_SOC_ATMEL_SAMV71_PLLA_DIVA); - - - soc_pmc_enable_upllck(0x3Fu); - - /* - * Final setup of the Master Clock - */ - - /* Setting PLLA as MCK, first prescaler, then divider and source last */ - soc_pmc_mck_set_prescaler(1); - soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAMV71_MDIV); - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); - - /* Disable internal fast RC if we have an external crystal oscillator */ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK)) { - soc_pmc_osc_disable_fastrc(); - } -} - -void z_arm_platform_init(void) -{ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_WAIT_MODE)) { - /* - * Instruct CPU to enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG. - */ - soc_pmc_enable_waitmode(); - } - - /* - * DTCM is enabled by default at reset, therefore we have to disable - * it first to get the caches into a state where then the - * sys_cache*-functions can enable them, if requested by the - * configuration. - */ - SCB_DisableDCache(); - - /* - * Enable the caches only if configured to do so. - */ - sys_cache_instr_enable(); - sys_cache_data_enable(); - - /* Setup system clocks */ - clock_init(); -} - -/** - * @brief Perform basic hardware initialization at boot. - * - * This needs to be run at the very beginning. - * So the init priority has to be 0 (zero). - * - * @return 0 - */ -static int atmel_samv71_init(void) -{ - /* Check that the CHIP CIDR matches the HAL one */ - if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { - LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", - (uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR); - } - - return 0; -} - -SYS_INIT(atmel_samv71_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/atmel_sam/samv71/soc.h b/soc/arm/atmel_sam/samv71/soc.h deleted file mode 100644 index 4c85be42136..00000000000 --- a/soc/arm/atmel_sam/samv71/soc.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2019 Gerson Fernando Budke - * Copyright (c) 2016 Piotr Mienkowski - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Register access macros for the Atmel SAM V71 MCU. - * - * This file provides register access macros for the Atmel SAM V71 MCU, HAL - * drivers for core peripherals as well as symbols specific to Atmel SAM family. - */ - -#ifndef _ATMEL_SAMV71_SOC_H_ -#define _ATMEL_SAMV71_SOC_H_ - -#include - -#ifndef _ASMLANGUAGE - - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined CONFIG_SOC_PART_NUMBER_SAMV71J19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J21B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N21B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q21B -#include -#else - #error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/soc_supc.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ \ - (SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAMV71_MDIV) - -/** UTMI PLL clock (UPLLCK) Frequency */ -#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480) - -#endif /* _ASMLANGUAGE */ - -#include "pwm_fixup.h" - -#endif /* _ATMEL_SAMV71_SOC_H_ */ diff --git a/soc/arm/atmel_sam/samv71/soc_config.c b/soc/arm/atmel_sam/samv71/soc_config.c deleted file mode 100644 index 2bcff027539..00000000000 --- a/soc/arm/atmel_sam/samv71/soc_config.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2019 Gerson Fernando Budke - * Copyright (c) 2016 Piotr Mienkowski - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief System module to support early Atmel SAM V71 MCU configuration - */ - -#include -#include -#include -#include - -/** - * @brief Perform SoC configuration at boot. - * - * This should be run early during the boot process but after basic hardware - * initialization is done. - * - * @return 0 - */ -static int atmel_samv71_config(void) -{ -#ifdef CONFIG_SOC_ATMEL_SAMV71_DISABLE_ERASE_PIN - /* Disable ERASE function on PB12 pin, this is controlled by Bus - * Matrix - */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; -#endif - - /* In Cortex-M based SoCs JTAG interface can be used to perform - * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug - * interface therefore there is no harm done by disabling the JTAG TDI - * pin by default. - */ - /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix - */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; - -#ifdef CONFIG_LOG_BACKEND_SWO - /* Disable PCK3 clock used by ETM module */ - PMC->PMC_SCDR = PMC_SCDR_PCK3; - while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { - ; - } - /* Select PLLA clock as PCK3 clock */ - PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; - /* Enable PCK3 clock */ - PMC->PMC_SCER = PMC_SCER_PCK3; - /* Wait for PCK3 setup to complete */ - while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { - ; - } - /* Enable TDO/TRACESWO function on PB5 pin */ - MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5; -#else - /* Disable TDO/TRACESWO function on PB5 pin */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5; -#endif - - return 0; -} - -SYS_INIT(atmel_samv71_config, PRE_KERNEL_1, 1); diff --git a/soc/arm/atmel_sam0/CMakeLists.txt b/soc/arm/atmel_sam0/CMakeLists.txt deleted file mode 100644 index 1af186063c9..00000000000 --- a/soc/arm/atmel_sam0/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Makefile - Atmel SAM0 MCU family -# -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -add_subdirectory(common) diff --git a/soc/arm/atmel_sam0/Kconfig b/soc/arm/atmel_sam0/Kconfig deleted file mode 100644 index 47c8d180027..00000000000 --- a/soc/arm/atmel_sam0/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Atmel SAM0 MCU family configuration options - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_SAM0 - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_SAM0 - -config SOC_FAMILY - string - default "atmel_sam0" - -source "soc/arm/atmel_sam0/common/Kconfig.samc2x" -source "soc/arm/atmel_sam0/common/Kconfig.saml2x" -source "soc/arm/atmel_sam0/common/Kconfig.samd2x" -source "soc/arm/atmel_sam0/common/Kconfig.samd5x" -source "soc/arm/atmel_sam0/*/Kconfig.soc" -source "soc/arm/atmel_sam0/Kconfig.soc.revisions" - -endif diff --git a/soc/arm/atmel_sam0/Kconfig.defconfig b/soc/arm/atmel_sam0/Kconfig.defconfig deleted file mode 100644 index b4f25f92c75..00000000000 --- a/soc/arm/atmel_sam0/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Atmel SAM0 MCU family default configuration options - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/atmel_sam0/*/Kconfig.defconfig.series" - -if SOC_FAMILY_SAM0 - -config PINCTRL - default y - -endif # SOC_FAMILY_SAM0 diff --git a/soc/arm/atmel_sam0/Kconfig.soc b/soc/arm/atmel_sam0/Kconfig.soc deleted file mode 100644 index 8e81395f5e3..00000000000 --- a/soc/arm/atmel_sam0/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Atmel SAM0 MCU series selection - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/atmel_sam0/*/Kconfig.series" diff --git a/soc/arm/atmel_sam0/Kconfig.soc.revisions b/soc/arm/atmel_sam0/Kconfig.soc.revisions deleted file mode 100644 index a152528ac7b..00000000000 --- a/soc/arm/atmel_sam0/Kconfig.soc.revisions +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_REVISION_N - bool - -config SOC_SERIES_REVISION - string - default "n" if SOC_SERIES_REVISION_N - default "" diff --git a/soc/arm/atmel_sam0/common/Kconfig.defconfig.series b/soc/arm/atmel_sam0/common/Kconfig.defconfig.series deleted file mode 100644 index 8d9068424fd..00000000000 --- a/soc/arm/atmel_sam0/common/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAM0 MCU family configuration options - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_SAM0 - -config HWINFO_SAM0 - default HWINFO - -if USB_DEVICE_DRIVER - -config HEAP_MEM_POOL_ADD_SIZE_SOC - def_int 1024 - -endif # USB_DEVICE_DRIVER - -endif # SOC_FAMILY_SAM0 diff --git a/soc/arm/atmel_sam0/common/Kconfig.samc2x b/soc/arm/atmel_sam0/common/Kconfig.samc2x deleted file mode 100644 index 3fca87f23ce..00000000000 --- a/soc/arm/atmel_sam0/common/Kconfig.samc2x +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMC20 || SOC_SERIES_SAMC21 - -endif diff --git a/soc/arm/atmel_sam0/samc20/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samc20/Kconfig.defconfig.series deleted file mode 100644 index 05a52d3af2a..00000000000 --- a/soc/arm/atmel_sam0/samc20/Kconfig.defconfig.series +++ /dev/null @@ -1,35 +0,0 @@ -# Atmel SAMC MCU series configuration options - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMC20 - -config SOC_SERIES - default "samc20" - -config SOC_PART_NUMBER - default "samc20e15a" if SOC_PART_NUMBER_SAMC20E15A - default "samc20e16a" if SOC_PART_NUMBER_SAMC20E16A - default "samc20e17a" if SOC_PART_NUMBER_SAMC20E17A - default "samc20e18a" if SOC_PART_NUMBER_SAMC20E18A - default "samc20g15a" if SOC_PART_NUMBER_SAMC20G15A - default "samc20g16a" if SOC_PART_NUMBER_SAMC20G16A - default "samc20g17a" if SOC_PART_NUMBER_SAMC20G17A - default "samc20g18a" if SOC_PART_NUMBER_SAMC20G18A - default "samc20j15a" if SOC_PART_NUMBER_SAMC20J15A - default "samc20j16a" if SOC_PART_NUMBER_SAMC20J16A - default "samc20j17a" if SOC_PART_NUMBER_SAMC20J17A - default "samc20j17au" if SOC_PART_NUMBER_SAMC20J17AU - default "samc20j18a" if SOC_PART_NUMBER_SAMC20J18A - default "samc20j18au" if SOC_PART_NUMBER_SAMC20J18AU - default "samc20n17a" if SOC_PART_NUMBER_SAMC20N17A - default "samc20n18a" if SOC_PART_NUMBER_SAMC20N18A - -config NUM_IRQS - default 32 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -endif # SOC_SERIES_SAMC20 diff --git a/soc/arm/atmel_sam0/samc20/Kconfig.series b/soc/arm/atmel_sam0/samc20/Kconfig.series deleted file mode 100644 index 4406e1bead4..00000000000 --- a/soc/arm/atmel_sam0/samc20/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMC20 MCU series - -# Copyright (c) 2022 Kamil Serwus -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMC20 - bool "Atmel SAMC20 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMC20 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samc20/Kconfig.soc b/soc/arm/atmel_sam0/samc20/Kconfig.soc deleted file mode 100644 index 9ccd4ca2714..00000000000 --- a/soc/arm/atmel_sam0/samc20/Kconfig.soc +++ /dev/null @@ -1,60 +0,0 @@ -# Atmel SAMC MCU series - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMC20 MCU Selection" - depends on SOC_SERIES_SAMC20 - -config SOC_PART_NUMBER_SAMC20E15A - bool "SAMC20E15A" - -config SOC_PART_NUMBER_SAMC20E16A - bool "SAMC20E16A" - -config SOC_PART_NUMBER_SAMC20E17A - bool "SAMC20E17A" - -config SOC_PART_NUMBER_SAMC20E18A - bool "SAMC20E18A" - -config SOC_PART_NUMBER_SAMC20G15A - bool "SAMC20G15A" - -config SOC_PART_NUMBER_SAMC20G16A - bool "SAMC20G16A" - -config SOC_PART_NUMBER_SAMC20G17A - bool "SAMC20G17A" - -config SOC_PART_NUMBER_SAMC20G18A - bool "SAMC20G18A" - -config SOC_PART_NUMBER_SAMC20J15A - bool "SAMC20J15A" - -config SOC_PART_NUMBER_SAMC20J16A - bool "SAMC20J16A" - -config SOC_PART_NUMBER_SAMC20J17A - bool "SAMC20J17A" - -config SOC_PART_NUMBER_SAMC20J17AU - bool "SAMC20J17AU" - -config SOC_PART_NUMBER_SAMC20J18A - bool "SAMC20J18A" - -config SOC_PART_NUMBER_SAMC20J18AU - bool "SAMC20J18AU" - -config SOC_PART_NUMBER_SAMC20N17A - bool "SAMC20N17A" - select SOC_SERIES_REVISION_N - -config SOC_PART_NUMBER_SAMC20N18A - bool "SAMC20N18A" - select SOC_SERIES_REVISION_N - -endchoice diff --git a/soc/arm/atmel_sam0/samc20/soc.h b/soc/arm/atmel_sam0/samc20/soc.h deleted file mode 100644 index 026479c31a5..00000000000 --- a/soc/arm/atmel_sam0/samc20/soc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2022 Kamil Serwus - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMC_SOC_H_ -#define _ATMEL_SAMC_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAMC20E15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J17AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J18AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20N17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20N18A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC48M_FREQ_HZ 48000000 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMD51_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samc21/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samc21/Kconfig.defconfig.series deleted file mode 100644 index bc1c4431737..00000000000 --- a/soc/arm/atmel_sam0/samc21/Kconfig.defconfig.series +++ /dev/null @@ -1,35 +0,0 @@ -# Atmel SAMC MCU series configuration options - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMC21 - -config SOC_SERIES - default "samc21" - -config SOC_PART_NUMBER - default "samc21e15a" if SOC_PART_NUMBER_SAMC21E15A - default "samc21e16a" if SOC_PART_NUMBER_SAMC21E16A - default "samc21e17a" if SOC_PART_NUMBER_SAMC21E17A - default "samc21e18a" if SOC_PART_NUMBER_SAMC21E18A - default "samc21g15a" if SOC_PART_NUMBER_SAMC21G15A - default "samc21g16a" if SOC_PART_NUMBER_SAMC21G16A - default "samc21g17a" if SOC_PART_NUMBER_SAMC21G17A - default "samc21g18a" if SOC_PART_NUMBER_SAMC21G18A - default "samc21j15a" if SOC_PART_NUMBER_SAMC21J15A - default "samc21j16a" if SOC_PART_NUMBER_SAMC21J16A - default "samc21j17a" if SOC_PART_NUMBER_SAMC21J17A - default "samc21j17au" if SOC_PART_NUMBER_SAMC21J17AU - default "samc21j18a" if SOC_PART_NUMBER_SAMC21J18A - default "samc21j18au" if SOC_PART_NUMBER_SAMC21J18AU - default "samc21n17a" if SOC_PART_NUMBER_SAMC21N17A - default "samc21n18a" if SOC_PART_NUMBER_SAMC21N18A - -config NUM_IRQS - default 32 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -endif # SOC_SERIES_SAMC21 diff --git a/soc/arm/atmel_sam0/samc21/Kconfig.series b/soc/arm/atmel_sam0/samc21/Kconfig.series deleted file mode 100644 index acb83679e18..00000000000 --- a/soc/arm/atmel_sam0/samc21/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAMC21 MCU series - -# Copyright (c) 2022 Kamil Serwus -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMC21 - bool "Atmel SAMC21 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select CPU_HAS_ARM_MPU - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMC21 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samc21/Kconfig.soc b/soc/arm/atmel_sam0/samc21/Kconfig.soc deleted file mode 100644 index f3f324abf6c..00000000000 --- a/soc/arm/atmel_sam0/samc21/Kconfig.soc +++ /dev/null @@ -1,60 +0,0 @@ -# Atmel SAMC MCU series - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMC21 MCU Selection" - depends on SOC_SERIES_SAMC21 - -config SOC_PART_NUMBER_SAMC21E15A - bool "SAMC21E15A" - -config SOC_PART_NUMBER_SAMC21E16A - bool "SAMC21E16A" - -config SOC_PART_NUMBER_SAMC21E17A - bool "SAMC21E17A" - -config SOC_PART_NUMBER_SAMC21E18A - bool "SAMC21E18A" - -config SOC_PART_NUMBER_SAMC21G15A - bool "SAMC21G15A" - -config SOC_PART_NUMBER_SAMC21G16A - bool "SAMC21G16A" - -config SOC_PART_NUMBER_SAMC21G17A - bool "SAMC21G17A" - -config SOC_PART_NUMBER_SAMC21G18A - bool "SAMC21G18A" - -config SOC_PART_NUMBER_SAMC21J15A - bool "SAMC21J15A" - -config SOC_PART_NUMBER_SAMC21J16A - bool "SAMC21J16A" - -config SOC_PART_NUMBER_SAMC21J17A - bool "SAMC21J17A" - -config SOC_PART_NUMBER_SAMC21J17AU - bool "SAMC21J17AU" - -config SOC_PART_NUMBER_SAMC21J18A - bool "SAMC21J18A" - -config SOC_PART_NUMBER_SAMC21J18AU - bool "SAMC21J18AU" - -config SOC_PART_NUMBER_SAMC21N17A - bool "SAMC21N17A" - select SOC_SERIES_REVISION_N - -config SOC_PART_NUMBER_SAMC21N18A - bool "SAMC21N18A" - select SOC_SERIES_REVISION_N - -endchoice diff --git a/soc/arm/atmel_sam0/samc21/soc.h b/soc/arm/atmel_sam0/samc21/soc.h deleted file mode 100644 index 56e33169150..00000000000 --- a/soc/arm/atmel_sam0/samc21/soc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2022 Kamil Serwus - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMC_SOC_H_ -#define _ATMEL_SAMC_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAMC21E15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J17AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J18AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21N17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21N18A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC48M_FREQ_HZ 48000000 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMD51_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samd20/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samd20/Kconfig.defconfig.series deleted file mode 100644 index f08047ae1ca..00000000000 --- a/soc/arm/atmel_sam0/samd20/Kconfig.defconfig.series +++ /dev/null @@ -1,36 +0,0 @@ -# Atmel SAMD MCU series configuration options - -# Copyright (c) 2018 Sean Nyekjaer -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMD20 - -config SOC_SERIES - default "samd20" - -config SOC_PART_NUMBER - default "samd20e14" if SOC_PART_NUMBER_SAMD20E14 - default "samd20e15" if SOC_PART_NUMBER_SAMD20E15 - default "samd20e16" if SOC_PART_NUMBER_SAMD20E16 - default "samd20e17" if SOC_PART_NUMBER_SAMD20E17 - default "samd20e18" if SOC_PART_NUMBER_SAMD20E18 - default "samd20g14" if SOC_PART_NUMBER_SAMD20G14 - default "samd20g15" if SOC_PART_NUMBER_SAMD20G15 - default "samd20g16" if SOC_PART_NUMBER_SAMD20G16 - default "samd20g17" if SOC_PART_NUMBER_SAMD20G17 - default "samd20g17u" if SOC_PART_NUMBER_SAMD20G17U - default "samd20g18" if SOC_PART_NUMBER_SAMD20G18 - default "samd20g18u" if SOC_PART_NUMBER_SAMD20G18U - default "samd20j14" if SOC_PART_NUMBER_SAMD20J14 - default "samd20j15" if SOC_PART_NUMBER_SAMD20J15 - default "samd20j16" if SOC_PART_NUMBER_SAMD20J16 - default "samd20j17" if SOC_PART_NUMBER_SAMD20J17 - default "samd20j18" if SOC_PART_NUMBER_SAMD20J18 - -config NUM_IRQS - default 25 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -endif # SOC_SERIES_SAMD20 diff --git a/soc/arm/atmel_sam0/samd20/Kconfig.series b/soc/arm/atmel_sam0/samd20/Kconfig.series deleted file mode 100644 index 2ec93b4954c..00000000000 --- a/soc/arm/atmel_sam0/samd20/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMD20 MCU series - -# Copyright (c) 2018 Sean Nyekjaer -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMD20 - bool "Atmel SAMD20 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMD20 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samd20/Kconfig.soc b/soc/arm/atmel_sam0/samd20/Kconfig.soc deleted file mode 100644 index 6cfc12f1f02..00000000000 --- a/soc/arm/atmel_sam0/samd20/Kconfig.soc +++ /dev/null @@ -1,61 +0,0 @@ -# Atmel SAMD MCU series - -# Copyright (c) 2018 Sean Nyekjaer -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMD20 MCU Selection" - depends on SOC_SERIES_SAMD20 - -config SOC_PART_NUMBER_SAMD20E14 - bool "SAMD20E14" - -config SOC_PART_NUMBER_SAMD20E15 - bool "SAMD20E15" - -config SOC_PART_NUMBER_SAMD20E16 - bool "SAMD20E16" - -config SOC_PART_NUMBER_SAMD20E17 - bool "SAMD20E17" - -config SOC_PART_NUMBER_SAMD20E18 - bool "SAMD20E18" - -config SOC_PART_NUMBER_SAMD20G14 - bool "SAMD20G14" - -config SOC_PART_NUMBER_SAMD20G15 - bool "SAMD20G15" - -config SOC_PART_NUMBER_SAMD20G16 - bool "SAMD20G16" - -config SOC_PART_NUMBER_SAMD20G17 - bool "SAMD20G17" - -config SOC_PART_NUMBER_SAMD20G17U - bool "SAMD20G17U" - -config SOC_PART_NUMBER_SAMD20G18 - bool "SAMD20G18" - -config SOC_PART_NUMBER_SAMD20G18U - bool "SAMD20G18U" - -config SOC_PART_NUMBER_SAMD20J14 - bool "SAMD20J14" - -config SOC_PART_NUMBER_SAMD20J15 - bool "SAMD20J15" - -config SOC_PART_NUMBER_SAMD20J16 - bool "SAMD20J16" - -config SOC_PART_NUMBER_SAMD20J17 - bool "SAMD20J17" - -config SOC_PART_NUMBER_SAMD20J18 - bool "SAMD20J18" - -endchoice diff --git a/soc/arm/atmel_sam0/samd20/soc.h b/soc/arm/atmel_sam0/samd20/soc.h deleted file mode 100644 index 7101e4e5315..00000000000 --- a/soc/arm/atmel_sam0/samd20/soc.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2018 Sean Nyekjaer - * Copyright (c) 2023 Ionut Catalin Pavel - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMD_SOC_H_ -#define _ATMEL_SAMD_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - -#if defined(CONFIG_SOC_PART_NUMBER_SAMD20E14) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E15) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E16) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E17) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E18) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G14) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G15) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G16) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G17) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G17U) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G18) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G18U) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J14) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J15) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J16) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J17) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J18) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ - -/** Known values */ -#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 -#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 - -/** GCLK1 source frequency selector */ -#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -/** Dividers and frequency for GCLK0 */ -#define SOC_ATMEL_SAM0_GCLK0_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -/** DFLL48M output frequency */ -#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ - (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) - -/** Dividers and frequency for GCLK1 */ -#define SOC_ATMEL_SAM0_GCLK1_DIV \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) - -/** DFLL48M output multiplier */ -#define SOC_ATMEL_SAM0_DFLL48M_MUL \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) - -/** Frequency for GCLK2 */ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ - -/** Dividers and frequency for GCLK3 */ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMD_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samd21/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samd21/Kconfig.defconfig.series deleted file mode 100644 index 085a0c5e60d..00000000000 --- a/soc/arm/atmel_sam0/samd21/Kconfig.defconfig.series +++ /dev/null @@ -1,33 +0,0 @@ -# Atmel SAMD MCU series configuration options - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMD21 - -config SOC_SERIES - default "samd21" - -config SOC_PART_NUMBER - default "samd21e15a" if SOC_PART_NUMBER_SAMD21E15A - default "samd21e16a" if SOC_PART_NUMBER_SAMD21E16A - default "samd21e17a" if SOC_PART_NUMBER_SAMD21E17A - default "samd21e18a" if SOC_PART_NUMBER_SAMD21E18A - default "samd21g15a" if SOC_PART_NUMBER_SAMD21G15A - default "samd21g16a" if SOC_PART_NUMBER_SAMD21G16A - default "samd21g17a" if SOC_PART_NUMBER_SAMD21G17A - default "samd21g17au" if SOC_PART_NUMBER_SAMD21G17AU - default "samd21g18a" if SOC_PART_NUMBER_SAMD21G18A - default "samd21g18au" if SOC_PART_NUMBER_SAMD21G18AU - default "samd21j15a" if SOC_PART_NUMBER_SAMD21J15A - default "samd21j16a" if SOC_PART_NUMBER_SAMD21J16A - default "samd21j17a" if SOC_PART_NUMBER_SAMD21J17A - default "samd21j18a" if SOC_PART_NUMBER_SAMD21J18A - -config NUM_IRQS - default 28 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -endif # SOC_SERIES_SAMD21 diff --git a/soc/arm/atmel_sam0/samd21/Kconfig.series b/soc/arm/atmel_sam0/samd21/Kconfig.series deleted file mode 100644 index b947c755a7a..00000000000 --- a/soc/arm/atmel_sam0/samd21/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMD21 MCU series - -# Copyright (c) 2017 Google LLC. -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMD21 - bool "Atmel SAMD21 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMD21 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samd21/Kconfig.soc b/soc/arm/atmel_sam0/samd21/Kconfig.soc deleted file mode 100644 index 51ffa5d6322..00000000000 --- a/soc/arm/atmel_sam0/samd21/Kconfig.soc +++ /dev/null @@ -1,52 +0,0 @@ -# Atmel SAMD MCU series - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMD21 MCU Selection" - depends on SOC_SERIES_SAMD21 - -config SOC_PART_NUMBER_SAMD21E15A - bool "SAMD21E15A" - -config SOC_PART_NUMBER_SAMD21E16A - bool "SAMD21E16A" - -config SOC_PART_NUMBER_SAMD21E17A - bool "SAMD21E17A" - -config SOC_PART_NUMBER_SAMD21E18A - bool "SAMD21E18A" - -config SOC_PART_NUMBER_SAMD21G15A - bool "SAMD21G15A" - -config SOC_PART_NUMBER_SAMD21G16A - bool "SAMD21G16A" - -config SOC_PART_NUMBER_SAMD21G17A - bool "SAMD21G17A" - -config SOC_PART_NUMBER_SAMD21G17AU - bool "SAMD21G17AU" - -config SOC_PART_NUMBER_SAMD21G18A - bool "SAMD21G18A" - -config SOC_PART_NUMBER_SAMD21G18AU - bool "SAMD21G18AU" - -config SOC_PART_NUMBER_SAMD21J15A - bool "SAMD21J15A" - -config SOC_PART_NUMBER_SAMD21J16A - bool "SAMD21J16A" - -config SOC_PART_NUMBER_SAMD21J17A - bool "SAMD21J17A" - -config SOC_PART_NUMBER_SAMD21J18A - bool "SAMD21J18A" - -endchoice diff --git a/soc/arm/atmel_sam0/samd21/soc.h b/soc/arm/atmel_sam0/samd21/soc.h deleted file mode 100644 index c4a33a95a54..00000000000 --- a/soc/arm/atmel_sam0/samd21/soc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2017 Google LLC. - * Copyright (c) 2023 Ionut Catalin Pavel - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMD_SOC_H_ -#define _ATMEL_SAMD_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - -#if defined(CONFIG_SOC_PART_NUMBER_SAMD21E15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21E16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21E17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21E18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G17AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G18AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J18A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ - -/** Known values */ -#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 -#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 - -/** GCLK1 source frequency selector */ -#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -/** Dividers and frequency for GCLK0 */ -#define SOC_ATMEL_SAM0_GCLK0_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -/** DFLL48M output frequency */ -#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ - (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) - -/** Dividers and frequency for GCLK1 */ -#define SOC_ATMEL_SAM0_GCLK1_DIV \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) - -/** DFLL48M output multiplier */ -#define SOC_ATMEL_SAM0_DFLL48M_MUL \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) - -/** Frequency for GCLK2 */ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ - -/** Dividers and frequency for GCLK3 */ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMD_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samd51/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samd51/Kconfig.defconfig.series deleted file mode 100644 index fb90434abd8..00000000000 --- a/soc/arm/atmel_sam0/samd51/Kconfig.defconfig.series +++ /dev/null @@ -1,35 +0,0 @@ -# Atmel SAMD51 MCU series configuration options - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMD51 - -config SOC_SERIES - string - default "samd51" - -config SOC_PART_NUMBER - string - default "samd51g18a" if SOC_PART_NUMBER_SAMD51G18A - default "samd51g19a" if SOC_PART_NUMBER_SAMD51G19A - default "samd51j18a" if SOC_PART_NUMBER_SAMD51J18A - default "samd51j19a" if SOC_PART_NUMBER_SAMD51J19A - default "samd51j20a" if SOC_PART_NUMBER_SAMD51J20A - default "samd51n19a" if SOC_PART_NUMBER_SAMD51N19A - default "samd51n20a" if SOC_PART_NUMBER_SAMD51N20A - default "samd51p19a" if SOC_PART_NUMBER_SAMD51P19A - default "samd51p20a" if SOC_PART_NUMBER_SAMD51P20A - -config NUM_IRQS - int - default 137 - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 120000000 - -endif # SOC_SERIES_SAMD51 diff --git a/soc/arm/atmel_sam0/samd51/Kconfig.series b/soc/arm/atmel_sam0/samd51/Kconfig.series deleted file mode 100644 index c85832735d8..00000000000 --- a/soc/arm/atmel_sam0/samd51/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAMD51 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMD51 - bool "Atmel SAMD51 MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMD51 Cortex-M4F microcontrollers. diff --git a/soc/arm/atmel_sam0/samd51/Kconfig.soc b/soc/arm/atmel_sam0/samd51/Kconfig.soc deleted file mode 100644 index 043ccdcab1a..00000000000 --- a/soc/arm/atmel_sam0/samd51/Kconfig.soc +++ /dev/null @@ -1,37 +0,0 @@ -# Atmel SAMD51 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMD51 MCU Selection" - depends on SOC_SERIES_SAMD51 - -config SOC_PART_NUMBER_SAMD51G18A - bool "SAMD51G18A" - -config SOC_PART_NUMBER_SAMD51G19A - bool "SAMD51G19A" - -config SOC_PART_NUMBER_SAMD51J18A - bool "SAMD51J18A" - -config SOC_PART_NUMBER_SAMD51J19A - bool "SAMD51J19A" - -config SOC_PART_NUMBER_SAMD51J20A - bool "SAMD51J20A" - -config SOC_PART_NUMBER_SAMD51N19A - bool "SAMD51N19A" - -config SOC_PART_NUMBER_SAMD51N20A - bool "SAMD51N20A" - -config SOC_PART_NUMBER_SAMD51P19A - bool "SAMD51P19A" - -config SOC_PART_NUMBER_SAMD51P20A - bool "SAMD51P20A" - -endchoice diff --git a/soc/arm/atmel_sam0/samd51/soc.h b/soc/arm/atmel_sam0/samd51/soc.h deleted file mode 100644 index 48a3b64ef8e..00000000000 --- a/soc/arm/atmel_sam0/samd51/soc.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2019 ML!PA Consulting GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMD51_SOC_H_ -#define _ATMEL_SAMD51_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAMD51G18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51G19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51J18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51J19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51J20A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51N19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51N20A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51P19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51P20A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "sercom_fixup_samd5x.h" -#include "tc_fixup_samd5x.h" -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 - -#endif /* _ATMEL_SAMD51_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/same51/Kconfig.defconfig.series b/soc/arm/atmel_sam0/same51/Kconfig.defconfig.series deleted file mode 100644 index 4b30d635aa2..00000000000 --- a/soc/arm/atmel_sam0/same51/Kconfig.defconfig.series +++ /dev/null @@ -1,31 +0,0 @@ -# Atmel SAME51 MCU series configuration options - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAME51 - -config SOC_SERIES - string - default "same51" - -config SOC_PART_NUMBER - string - default "same51j18a" if SOC_PART_NUMBER_SAME51J18A - default "same51j19a" if SOC_PART_NUMBER_SAME51J19A - default "same51j20a" if SOC_PART_NUMBER_SAME51J20A - default "same51n19a" if SOC_PART_NUMBER_SAME51N19A - default "same51n20a" if SOC_PART_NUMBER_SAME51N20A - -config NUM_IRQS - int - default 137 - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 120000000 - -endif # SOC_SERIES_SAME51 diff --git a/soc/arm/atmel_sam0/same51/Kconfig.series b/soc/arm/atmel_sam0/same51/Kconfig.series deleted file mode 100644 index ced8b081fbe..00000000000 --- a/soc/arm/atmel_sam0/same51/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAME51 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAME51 - bool "Atmel SAME51 MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAME51 Cortex-M4F microcontrollers. diff --git a/soc/arm/atmel_sam0/same51/Kconfig.soc b/soc/arm/atmel_sam0/same51/Kconfig.soc deleted file mode 100644 index 08b3db89456..00000000000 --- a/soc/arm/atmel_sam0/same51/Kconfig.soc +++ /dev/null @@ -1,25 +0,0 @@ -# Atmel SAME51 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAME51 MCU Selection" - depends on SOC_SERIES_SAME51 - -config SOC_PART_NUMBER_SAME51J18A - bool "SAME51J18A" - -config SOC_PART_NUMBER_SAME51J19A - bool "SAME51J19A" - -config SOC_PART_NUMBER_SAME51J20A - bool "SAME51J20A" - -config SOC_PART_NUMBER_SAME51N19A - bool "SAME51N19A" - -config SOC_PART_NUMBER_SAME51N20A - bool "SAME51N20A" - -endchoice diff --git a/soc/arm/atmel_sam0/same51/soc.h b/soc/arm/atmel_sam0/same51/soc.h deleted file mode 100644 index 746a001be69..00000000000 --- a/soc/arm/atmel_sam0/same51/soc.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2019 ML!PA Consulting GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAME51_SOC_H_ -#define _ATMEL_SAME51_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAME51J18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME51J19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME51J20A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME51N19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME51N20A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "sercom_fixup_samd5x.h" -#include "tc_fixup_samd5x.h" -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_DFLL48_FREQ_HZ 48000000 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 - -#endif /* _ATMEL_SAME51_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/same53/Kconfig.defconfig.series b/soc/arm/atmel_sam0/same53/Kconfig.defconfig.series deleted file mode 100644 index f49d2741b3d..00000000000 --- a/soc/arm/atmel_sam0/same53/Kconfig.defconfig.series +++ /dev/null @@ -1,31 +0,0 @@ -# Atmel SAME53 MCU series configuration options - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAME53 - -config SOC_SERIES - string - default "same53" - -config SOC_PART_NUMBER - string - default "same53j18a" if SOC_PART_NUMBER_SAME53J18A - default "same53j19a" if SOC_PART_NUMBER_SAME53J19A - default "same53j20a" if SOC_PART_NUMBER_SAME53J20A - default "same53n19a" if SOC_PART_NUMBER_SAME53N19A - default "same53n20a" if SOC_PART_NUMBER_SAME53N20A - -config NUM_IRQS - int - default 137 - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 120000000 - -endif # SOC_SERIES_SAME53 diff --git a/soc/arm/atmel_sam0/same53/Kconfig.series b/soc/arm/atmel_sam0/same53/Kconfig.series deleted file mode 100644 index a90a89229cb..00000000000 --- a/soc/arm/atmel_sam0/same53/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAME53 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAME53 - bool "Atmel SAME53 MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAME53 Cortex-M4F microcontrollers. diff --git a/soc/arm/atmel_sam0/same53/Kconfig.soc b/soc/arm/atmel_sam0/same53/Kconfig.soc deleted file mode 100644 index f59797204fe..00000000000 --- a/soc/arm/atmel_sam0/same53/Kconfig.soc +++ /dev/null @@ -1,25 +0,0 @@ -# Atmel SAME53 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAME53 MCU Selection" - depends on SOC_SERIES_SAME53 - -config SOC_PART_NUMBER_SAME53J18A - bool "SAME53J18A" - -config SOC_PART_NUMBER_SAME53J19A - bool "SAME53J19A" - -config SOC_PART_NUMBER_SAME53J20A - bool "SAME53J20A" - -config SOC_PART_NUMBER_SAME53N19A - bool "SAME53N19A" - -config SOC_PART_NUMBER_SAME53N20A - bool "SAME53N20A" - -endchoice diff --git a/soc/arm/atmel_sam0/same53/soc.h b/soc/arm/atmel_sam0/same53/soc.h deleted file mode 100644 index f3b1e460e33..00000000000 --- a/soc/arm/atmel_sam0/same53/soc.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2019 ML!PA Consulting GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAME53_SOC_H_ -#define _ATMEL_SAME53_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAME53J18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME53J19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME53J20A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME53N19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME53N20A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "sercom_fixup_samd5x.h" -#include "tc_fixup_samd5x.h" -#include "gmac_fixup_samd5x.h" -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 - -#endif /* _ATMEL_SAME53_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/same54/Kconfig.defconfig.series b/soc/arm/atmel_sam0/same54/Kconfig.defconfig.series deleted file mode 100644 index f2b3f9844a7..00000000000 --- a/soc/arm/atmel_sam0/same54/Kconfig.defconfig.series +++ /dev/null @@ -1,30 +0,0 @@ -# Atmel SAME MCU series configuration options - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAME54 - -config SOC_SERIES - string - default "same54" - -config SOC_PART_NUMBER - string - default "same54n19a" if SOC_PART_NUMBER_SAME54N19A - default "same54n20a" if SOC_PART_NUMBER_SAME54N20A - default "same54p19a" if SOC_PART_NUMBER_SAME54P19A - default "same54p20a" if SOC_PART_NUMBER_SAME54P20A - -config NUM_IRQS - int - default 137 - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 120000000 - -endif # SOC_SERIES_SAME54 diff --git a/soc/arm/atmel_sam0/same54/Kconfig.series b/soc/arm/atmel_sam0/same54/Kconfig.series deleted file mode 100644 index 5840a5e3515..00000000000 --- a/soc/arm/atmel_sam0/same54/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAME54 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAME54 - bool "Atmel SAME54 MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAME54 Cortex-M4F microcontrollers. diff --git a/soc/arm/atmel_sam0/same54/Kconfig.soc b/soc/arm/atmel_sam0/same54/Kconfig.soc deleted file mode 100644 index 35db63eab80..00000000000 --- a/soc/arm/atmel_sam0/same54/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# Atmel SAME MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAME54 MCU Selection" - depends on SOC_SERIES_SAME54 - -config SOC_PART_NUMBER_SAME54N19A - bool "SAME54N19A" - -config SOC_PART_NUMBER_SAME54N20A - bool "SAME54N20A" - -config SOC_PART_NUMBER_SAME54P19A - bool "SAME54P19A" - -config SOC_PART_NUMBER_SAME54P20A - bool "SAME54P20A" - -endchoice diff --git a/soc/arm/atmel_sam0/same54/soc.h b/soc/arm/atmel_sam0/same54/soc.h deleted file mode 100644 index b62eead707e..00000000000 --- a/soc/arm/atmel_sam0/same54/soc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2019 ML!PA Consulting GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAME54_SOC_H_ -#define _ATMEL_SAME54_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAME54N19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME54N20A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME54P19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME54P20A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "sercom_fixup_samd5x.h" -#include "tc_fixup_samd5x.h" -#include "gmac_fixup_samd5x.h" -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_DFLL48_FREQ_HZ 48000000 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 - -#endif /* _ATMEL_SAME54_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/saml21/Kconfig.defconfig.series b/soc/arm/atmel_sam0/saml21/Kconfig.defconfig.series deleted file mode 100644 index 23bfcb70262..00000000000 --- a/soc/arm/atmel_sam0/saml21/Kconfig.defconfig.series +++ /dev/null @@ -1,31 +0,0 @@ -# Atmel SAML MCU series configuration options - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAML21 - -config SOC_SERIES - default "saml21" - -config SOC_PART_NUMBER - default "saml21e15b" if SOC_PART_NUMBER_SAML21E15B - default "saml21e16b" if SOC_PART_NUMBER_SAML21E16B - default "saml21e17b" if SOC_PART_NUMBER_SAML21E17B - default "saml21e18b" if SOC_PART_NUMBER_SAML21E18B - default "saml21g16b" if SOC_PART_NUMBER_SAML21G16B - default "saml21g17b" if SOC_PART_NUMBER_SAML21G17B - default "saml21g18b" if SOC_PART_NUMBER_SAML21G18B - default "saml21j16b" if SOC_PART_NUMBER_SAML21J16B - default "saml21j17b" if SOC_PART_NUMBER_SAML21J17B - default "saml21j17bu" if SOC_PART_NUMBER_SAML21J17BU - default "saml21j18b" if SOC_PART_NUMBER_SAML21J18B - default "saml21j18bu" if SOC_PART_NUMBER_SAML21J18BU - -config NUM_IRQS - default 29 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -endif # SOC_SERIES_SAML21 diff --git a/soc/arm/atmel_sam0/saml21/Kconfig.series b/soc/arm/atmel_sam0/saml21/Kconfig.series deleted file mode 100644 index 662120102bb..00000000000 --- a/soc/arm/atmel_sam0/saml21/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAML21 MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAML21 - bool "Atmel SAML21 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAML21 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/saml21/Kconfig.soc b/soc/arm/atmel_sam0/saml21/Kconfig.soc deleted file mode 100644 index f6ab97367a9..00000000000 --- a/soc/arm/atmel_sam0/saml21/Kconfig.soc +++ /dev/null @@ -1,46 +0,0 @@ -# Atmel SAML MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAML21 MCU Selection" - depends on SOC_SERIES_SAML21 - -config SOC_PART_NUMBER_SAML21E15B - bool "SAML21E15B" - -config SOC_PART_NUMBER_SAML21E16B - bool "SAML21E16B" - -config SOC_PART_NUMBER_SAML21E17B - bool "SAML21E17B" - -config SOC_PART_NUMBER_SAML21E18B - bool "SAML21E18B" - -config SOC_PART_NUMBER_SAML21G16B - bool "SAML21G16B" - -config SOC_PART_NUMBER_SAML21G17B - bool "SAML21G17B" - -config SOC_PART_NUMBER_SAML21G18B - bool "SAML21G18B" - -config SOC_PART_NUMBER_SAML21J16B - bool "SAML21J16B" - -config SOC_PART_NUMBER_SAML21J17B - bool "SAML21J17B" - -config SOC_PART_NUMBER_SAML21J17BU - bool "SAML21J17BU" - -config SOC_PART_NUMBER_SAML21J18B - bool "SAML21J18B" - -config SOC_PART_NUMBER_SAML21J18BU - bool "SAML21J18BU" - -endchoice diff --git a/soc/arm/atmel_sam0/saml21/soc.h b/soc/arm/atmel_sam0/saml21/soc.h deleted file mode 100644 index de6b80dee61..00000000000 --- a/soc/arm/atmel_sam0/saml21/soc.h +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright (c) 2021 Argentum Systems Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAML_SOC_H_ -#define _ATMEL_SAML_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#if defined(CONFIG_SOC_PART_NUMBER_SAML21E15B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21E16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21E17B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21E18B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21G16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21G17B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21G18B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J17B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J17BU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J18B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J18BU) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 - -#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAML_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samr21/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samr21/Kconfig.defconfig.series deleted file mode 100644 index de04abe7755..00000000000 --- a/soc/arm/atmel_sam0/samr21/Kconfig.defconfig.series +++ /dev/null @@ -1,26 +0,0 @@ -# Atmel SAMR21 MCU series configuration options - -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMR21 - -config SOC_SERIES - default "samr21" - -config SOC_PART_NUMBER - default "samr21e16a" if SOC_PART_NUMBER_SAMR21E16A - default "samr21e17a" if SOC_PART_NUMBER_SAMR21E17A - default "samr21e18a" if SOC_PART_NUMBER_SAMR21E18A - default "samr21e19a" if SOC_PART_NUMBER_SAMR21E19A - default "samr21g16a" if SOC_PART_NUMBER_SAMR21G16A - default "samr21g17a" if SOC_PART_NUMBER_SAMR21G17A - default "samr21g18a" if SOC_PART_NUMBER_SAMR21G18A - -config NUM_IRQS - default 28 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -endif # SOC_SERIES_SAMR21 diff --git a/soc/arm/atmel_sam0/samr21/Kconfig.series b/soc/arm/atmel_sam0/samr21/Kconfig.series deleted file mode 100644 index 8dd60e5f650..00000000000 --- a/soc/arm/atmel_sam0/samr21/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMR21 MCU series - -# Copyright (c) 2017 Google LLC. -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMR21 - bool "Atmel SAMR21 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMR21 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samr21/Kconfig.soc b/soc/arm/atmel_sam0/samr21/Kconfig.soc deleted file mode 100644 index 98fb2781818..00000000000 --- a/soc/arm/atmel_sam0/samr21/Kconfig.soc +++ /dev/null @@ -1,31 +0,0 @@ -# Atmel SAMR21 MCU series - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMR21 MCU Selection" - depends on SOC_SERIES_SAMR21 - -config SOC_PART_NUMBER_SAMR21E16A - bool "SAMR21E16A" - -config SOC_PART_NUMBER_SAMR21E17A - bool "SAMR21E17A" - -config SOC_PART_NUMBER_SAMR21E18A - bool "SAMR21E18A" - -config SOC_PART_NUMBER_SAMR21E19A - bool "SAMR21E19A" - -config SOC_PART_NUMBER_SAMR21G16A - bool "SAMR21G16A" - -config SOC_PART_NUMBER_SAMR21G17A - bool "SAMR21G17A" - -config SOC_PART_NUMBER_SAMR21G18A - bool "SAMR21G18A" - -endchoice diff --git a/soc/arm/atmel_sam0/samr21/soc.h b/soc/arm/atmel_sam0/samr21/soc.h deleted file mode 100644 index 0e19aa9b45d..00000000000 --- a/soc/arm/atmel_sam0/samr21/soc.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2017 Google LLC. - * Copyright (c) 2023 Ionut Catalin Pavel - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_ATMEL_SAMR21_SOC_H_ -#define ZEPHYR_ATMEL_SAMR21_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - -#if defined(CONFIG_SOC_PART_NUMBER_SAMR21E16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G18A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ - -/** Known values */ -#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 -#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 - -/** GCLK1 source frequency selector */ -#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -/** Dividers and frequency for GCLK0 */ -#define SOC_ATMEL_SAM0_GCLK0_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -/** DFLL48M output frequency */ -#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ - (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) - -/** Dividers and frequency for GCLK1 */ -#define SOC_ATMEL_SAM0_GCLK1_DIV \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) - -/** DFLL48M output multiplier */ -#define SOC_ATMEL_SAM0_DFLL48M_MUL \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) - -/** Frequency for GCLK2 */ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ - -/** Dividers and frequency for GCLK3 */ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* ZEPHYR_ATMEL_SAMR21_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samr34/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samr34/Kconfig.defconfig.series deleted file mode 100644 index 96ca593b5a9..00000000000 --- a/soc/arm/atmel_sam0/samr34/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# Atmel SAML MCU series configuration options - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMR34 - -config SOC_SERIES - default "samr34" - -config SOC_PART_NUMBER - default "samr34j16b" if SOC_PART_NUMBER_SAMR34J16B - default "samr34j17b" if SOC_PART_NUMBER_SAMR34J17B - default "samr34j18b" if SOC_PART_NUMBER_SAMR34J18B - -config NUM_IRQS - default 23 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -endif # SOC_SERIES_SAMR34 diff --git a/soc/arm/atmel_sam0/samr34/Kconfig.series b/soc/arm/atmel_sam0/samr34/Kconfig.series deleted file mode 100644 index d3be127ac16..00000000000 --- a/soc/arm/atmel_sam0/samr34/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMR34 MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMR34 - bool "Atmel SAMR34 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMR34 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samr34/Kconfig.soc b/soc/arm/atmel_sam0/samr34/Kconfig.soc deleted file mode 100644 index 088d56b7109..00000000000 --- a/soc/arm/atmel_sam0/samr34/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Atmel SAMR MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMR34 MCU Selection" - depends on SOC_SERIES_SAMR34 - -config SOC_PART_NUMBER_SAMR34J16B - bool "SAMR34J16B" - -config SOC_PART_NUMBER_SAMR34J17B - bool "SAMR34J17B" - -config SOC_PART_NUMBER_SAMR34J18B - bool "SAMR34J18B" - -endchoice diff --git a/soc/arm/atmel_sam0/samr34/soc.h b/soc/arm/atmel_sam0/samr34/soc.h deleted file mode 100644 index 2da117cf14e..00000000000 --- a/soc/arm/atmel_sam0/samr34/soc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright (c) 2021 Argentum Systems Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMR_SOC_H_ -#define _ATMEL_SAMR_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - -#if defined(CONFIG_SOC_PART_NUMBER_SAMR34J16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR34J17B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR34J18B) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 - -#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMR_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samr35/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samr35/Kconfig.defconfig.series deleted file mode 100644 index edc7636d96d..00000000000 --- a/soc/arm/atmel_sam0/samr35/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# Atmel SAML MCU series configuration options - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMR35 - -config SOC_SERIES - default "samr35" - -config SOC_PART_NUMBER - default "samr35j16b" if SOC_PART_NUMBER_SAMR35J16B - default "samr35j17b" if SOC_PART_NUMBER_SAMR35J17B - default "samr35j18b" if SOC_PART_NUMBER_SAMR35J18B - -config NUM_IRQS - default 23 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -endif # SOC_SERIES_SAMR35 diff --git a/soc/arm/atmel_sam0/samr35/Kconfig.series b/soc/arm/atmel_sam0/samr35/Kconfig.series deleted file mode 100644 index d55718d8524..00000000000 --- a/soc/arm/atmel_sam0/samr35/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMR35 MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMR35 - bool "Atmel SAMR35 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMR35 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samr35/Kconfig.soc b/soc/arm/atmel_sam0/samr35/Kconfig.soc deleted file mode 100644 index ceb95243806..00000000000 --- a/soc/arm/atmel_sam0/samr35/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Atmel SAMR MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAM35 MCU Selection" - depends on SOC_SERIES_SAMR35 - -config SOC_PART_NUMBER_SAMR35J16B - bool "SAMR35J16B" - -config SOC_PART_NUMBER_SAMR35J17B - bool "SAMR35J17B" - -config SOC_PART_NUMBER_SAMR35J18B - bool "SAMR35J18B" - -endchoice diff --git a/soc/arm/atmel_sam0/samr35/soc.h b/soc/arm/atmel_sam0/samr35/soc.h deleted file mode 100644 index db3fd85b865..00000000000 --- a/soc/arm/atmel_sam0/samr35/soc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright (c) 2021 Argentum Systems Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMR_SOC_H_ -#define _ATMEL_SAMR_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - -#if defined(CONFIG_SOC_PART_NUMBER_SAMR35J16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR35J17B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR35J18B) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 - -#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMR_SOC_H_ */ diff --git a/soc/arm/bcm_vk/Kconfig b/soc/arm/bcm_vk/Kconfig deleted file mode 100644 index ae6122bd247..00000000000 --- a/soc/arm/bcm_vk/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -config SOC_FAMILY_BCMVK - bool - -if SOC_FAMILY_BCMVK -config SOC_FAMILY - string - default "bcm_vk" - -source "soc/arm/bcm_vk/*/Kconfig.soc" - -endif diff --git a/soc/arm/bcm_vk/Kconfig.defconfig b/soc/arm/bcm_vk/Kconfig.defconfig deleted file mode 100644 index 1258ea005a3..00000000000 --- a/soc/arm/bcm_vk/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -source "soc/arm/bcm_vk/*/Kconfig.defconfig.series" diff --git a/soc/arm/bcm_vk/Kconfig.soc b/soc/arm/bcm_vk/Kconfig.soc deleted file mode 100644 index ce1114d2227..00000000000 --- a/soc/arm/bcm_vk/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -source "soc/arm/bcm_vk/*/Kconfig.series" diff --git a/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.series b/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.series deleted file mode 100644 index b3de9e87746..00000000000 --- a/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -if SOC_SERIES_VALKYRIE - -config SOC_SERIES - default "valkyrie" - -config NUM_IRQS - int - default 240 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 500000000 - -source "soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.valkyrie*" - -endif # SOC_SERIES_VALKYRIE diff --git a/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.valkyrie_bcm58400 b/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.valkyrie_bcm58400 deleted file mode 100644 index 9b5d7a45a26..00000000000 --- a/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.valkyrie_bcm58400 +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. - -config SOC - default "BCM58400" - depends on SOC_BCM58400 diff --git a/soc/arm/bcm_vk/valkyrie/Kconfig.series b/soc/arm/bcm_vk/valkyrie/Kconfig.series deleted file mode 100644 index ca4542b5e89..00000000000 --- a/soc/arm/bcm_vk/valkyrie/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -config SOC_SERIES_VALKYRIE - bool "Broadcom Valkyrie Series" - select ARM - select CPU_CORTEX_M7 - select SOC_FAMILY_BCMVK - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_HAS_ARM_MPU - help - Enable support for Broadcom Valkyrie Series diff --git a/soc/arm/bcm_vk/valkyrie/Kconfig.soc b/soc/arm/bcm_vk/valkyrie/Kconfig.soc deleted file mode 100644 index 76f3ac196ee..00000000000 --- a/soc/arm/bcm_vk/valkyrie/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -choice -prompt "Broadcom Valkyrie SoC" -depends on SOC_SERIES_VALKYRIE - -config SOC_BCM58400 - bool "Broadcom BCM58400" -endchoice diff --git a/soc/arm/bcm_vk/viper/CMakeLists.txt b/soc/arm/bcm_vk/viper/CMakeLists.txt deleted file mode 100644 index b81c75442e1..00000000000 --- a/soc/arm/bcm_vk/viper/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_sources( - soc.c -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/bcm_vk/viper/Kconfig.defconfig.series b/soc/arm/bcm_vk/viper/Kconfig.defconfig.series deleted file mode 100644 index 98623b5c6a5..00000000000 --- a/soc/arm/bcm_vk/viper/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_VIPER - -config SOC_SERIES - default "viper" - -source "soc/arm/bcm_vk/viper/Kconfig.defconfig.viper*" - -endif # SOC_SERIES_VIPER diff --git a/soc/arm/bcm_vk/viper/Kconfig.series b/soc/arm/bcm_vk/viper/Kconfig.series deleted file mode 100644 index 90a9c162e2f..00000000000 --- a/soc/arm/bcm_vk/viper/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_VIPER - bool "Broadcom Viper Series" - select ARM - select SOC_FAMILY_BCMVK - help - Enable support for Broadcom Viper Series. diff --git a/soc/arm/bcm_vk/viper/Kconfig.soc b/soc/arm/bcm_vk/viper/Kconfig.soc deleted file mode 100644 index b72e9dd736a..00000000000 --- a/soc/arm/bcm_vk/viper/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Broadcom Viper SoC" -depends on SOC_SERIES_VIPER - -config SOC_BCM58402_M7 - bool "Broadcom BCM58402 M7" - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_HAS_ARM_MPU - -endchoice diff --git a/soc/arm/arm/beetle/CMSDK_BEETLE.h b/soc/arm/beetle/CMSDK_BEETLE.h similarity index 100% rename from soc/arm/arm/beetle/CMSDK_BEETLE.h rename to soc/arm/beetle/CMSDK_BEETLE.h diff --git a/soc/arm/beetle/CMakeLists.txt b/soc/arm/beetle/CMakeLists.txt new file mode 100644 index 00000000000..7cad91bdc85 --- /dev/null +++ b/soc/arm/beetle/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + power.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/beetle/Kconfig b/soc/arm/beetle/Kconfig new file mode 100644 index 00000000000..19de2b1717c --- /dev/null +++ b/soc/arm/beetle/Kconfig @@ -0,0 +1,10 @@ +# ARM LTD Beetle SoC configuration options + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_BEETLE + select ARM + select CPU_CORTEX_M3 + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_DWT diff --git a/soc/arm/beetle/Kconfig.defconfig b/soc/arm/beetle/Kconfig.defconfig new file mode 100644 index 00000000000..4052632978b --- /dev/null +++ b/soc/arm/beetle/Kconfig.defconfig @@ -0,0 +1,18 @@ +# ARM LTD Beetle SoC configuration options + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_BEETLE + +config NUM_IRQS + default 45 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 24000000 + +config CLOCK_CONTROL_INIT_PRIORITY + default 1 + depends on CLOCK_CONTROL + +endif # SOC_SERIES_BEETLE diff --git a/soc/arm/beetle/Kconfig.soc b/soc/arm/beetle/Kconfig.soc new file mode 100644 index 00000000000..9b28a76106b --- /dev/null +++ b/soc/arm/beetle/Kconfig.soc @@ -0,0 +1,22 @@ +# ARM LTD Beetle SoC configuration options + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_BEETLE + bool + select SOC_FAMILY_ARM + help + Enable support for Beetle MCU Series + +config SOC_BEETLE_R0 + bool + select SOC_SERIES_BEETLE + help + ARM BEETLE R0 + +config SOC_SERIES + default "beetle" if SOC_SERIES_BEETLE + +config SOC + default "beetle_r0" if SOC_BEETLE_R0 diff --git a/soc/arm/arm/beetle/power.c b/soc/arm/beetle/power.c similarity index 100% rename from soc/arm/arm/beetle/power.c rename to soc/arm/beetle/power.c diff --git a/soc/arm/arm/beetle/soc.c b/soc/arm/beetle/soc.c similarity index 100% rename from soc/arm/arm/beetle/soc.c rename to soc/arm/beetle/soc.c diff --git a/soc/arm/arm/beetle/soc.h b/soc/arm/beetle/soc.h similarity index 100% rename from soc/arm/arm/beetle/soc.h rename to soc/arm/beetle/soc.h diff --git a/soc/arm/beetle/soc.yml b/soc/arm/beetle/soc.yml new file mode 100644 index 00000000000..20bbf8445fd --- /dev/null +++ b/soc/arm/beetle/soc.yml @@ -0,0 +1,4 @@ +series: +- name: beetle + socs: + - name: beetle_r0 diff --git a/soc/arm/arm/beetle/soc_irq.h b/soc/arm/beetle/soc_irq.h similarity index 100% rename from soc/arm/arm/beetle/soc_irq.h rename to soc/arm/beetle/soc_irq.h diff --git a/soc/arm/arm/beetle/soc_pins.h b/soc/arm/beetle/soc_pins.h similarity index 100% rename from soc/arm/arm/beetle/soc_pins.h rename to soc/arm/beetle/soc_pins.h diff --git a/soc/arm/arm/beetle/soc_pll.h b/soc/arm/beetle/soc_pll.h similarity index 100% rename from soc/arm/arm/beetle/soc_pll.h rename to soc/arm/beetle/soc_pll.h diff --git a/soc/arm/arm/beetle/soc_power.h b/soc/arm/beetle/soc_power.h similarity index 100% rename from soc/arm/arm/beetle/soc_power.h rename to soc/arm/beetle/soc_power.h diff --git a/soc/arm/arm/beetle/soc_registers.h b/soc/arm/beetle/soc_registers.h similarity index 100% rename from soc/arm/arm/beetle/soc_registers.h rename to soc/arm/beetle/soc_registers.h diff --git a/soc/arm/cypress/CMakeLists.txt b/soc/arm/cypress/CMakeLists.txt deleted file mode 100644 index 95451afda66..00000000000 --- a/soc/arm/cypress/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -add_subdirectory(${SOC_SERIES}) -add_subdirectory(common) diff --git a/soc/arm/cypress/Kconfig b/soc/arm/cypress/Kconfig deleted file mode 100644 index cb76ccb1090..00000000000 --- a/soc/arm/cypress/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Cypress PSoC6 MCU Selection" - depends on SOC_SERIES_PSOC62 || \ - SOC_SERIES_PSOC63 - -config SOC_PSOC6_M0 - bool "SOC_PSOC6_M0" - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select CPU_HAS_ARM_MPU - -config SOC_PSOC6_M4 - bool "SOC_PSOC6_M4" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - -endchoice - -config SOC_PSOC6_M0_ENABLES_M4 - bool "Dual-core support [activate Cortex-M4]" - depends on SOC_PSOC6_M0 - help - Cortex-M0 CPU should boot Cortex-M4 - -config SOC_FAMILY_PSOC6 - bool - -if SOC_FAMILY_PSOC6 - -config SOC_FAMILY - string - default "cypress" - -source "soc/arm/cypress/*/Kconfig.soc" - -endif # SOC_FAMILY_PSOC6 diff --git a/soc/arm/cypress/Kconfig.defconfig b/soc/arm/cypress/Kconfig.defconfig deleted file mode 100644 index 74310b9ea01..00000000000 --- a/soc/arm/cypress/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2018, Cypress -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/cypress/*/Kconfig.defconfig.series" diff --git a/soc/arm/cypress/Kconfig.soc b/soc/arm/cypress/Kconfig.soc deleted file mode 100644 index 04e3e203b2f..00000000000 --- a/soc/arm/cypress/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2018, Cypress -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/cypress/*/Kconfig.series" diff --git a/soc/arm/cypress/psoc6/CMakeLists.txt b/soc/arm/cypress/psoc6/CMakeLists.txt deleted file mode 100644 index e2ea2eb6ae1..00000000000 --- a/soc/arm/cypress/psoc6/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_include_directories(.) -zephyr_sources( - soc.c -) - -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 NOINIT noinit.ld) -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 RWDATA rwdata.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m0 b/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m0 deleted file mode 100644 index 7e97640dc79..00000000000 --- a/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m0 +++ /dev/null @@ -1,14 +0,0 @@ -# Cypress PSoC6 CM0 platform configuration options - -# Copyright (c) 2018, Cypress -# SPDX-License-Identifier: Apache-2.0 - -if SOC_PSOC6_M0 - -config SOC - default "psoc6_m0" - -config NUM_IRQS - default 32 - -endif # SOC_PSOC6_M0 diff --git a/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m4 b/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m4 deleted file mode 100644 index 0b4f3e0a4fe..00000000000 --- a/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m4 +++ /dev/null @@ -1,14 +0,0 @@ -# Cypress PSoC6 CM4 platform configuration options - -# Copyright (c) 2018, Cypress -# SPDX-License-Identifier: Apache-2.0 - -if SOC_PSOC6_M4 - -config SOC - default "psoc6_m4" - -config NUM_IRQS - default 147 - -endif # SOC_PSOC6_M4 diff --git a/soc/arm/cypress/psoc6/Kconfig.defconfig.series b/soc/arm/cypress/psoc6/Kconfig.defconfig.series deleted file mode 100644 index 36dfd19d566..00000000000 --- a/soc/arm/cypress/psoc6/Kconfig.defconfig.series +++ /dev/null @@ -1,25 +0,0 @@ -# Cypress Semiconductor PSoC6 series configuration options - -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_PSOC62 || \ - SOC_SERIES_PSOC63 - -config SOC_SERIES - default "psoc6" - -config SOC_PART_NUMBER - default "CY8C6247BZI_D54" if SOC_PART_NUMBER_CY8C6247BZI_D54 - -config SOC_PART_NUMBER - default "CY8C6347BZI_BLD53" if SOC_PART_NUMBER_CY8C6347BZI_BLD53 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 50000000 - -source "soc/arm/cypress/psoc6/Kconfig.defconfig.psoc*" - -endif # SOC_SERIES_PSOC62 || \ - # SOC_SERIES_PSOC63 diff --git a/soc/arm/cypress/psoc6/Kconfig.series b/soc/arm/cypress/psoc6/Kconfig.series deleted file mode 100644 index 35eb08685e1..00000000000 --- a/soc/arm/cypress/psoc6/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Cypress PSoC6 MCU line - -# Copyright (c) 2018, Cypress Semiconductor -# Copyright (c) 2020, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_PSOC62 - bool "Cypress PSoC6 series MCU - Standard" - select ARM - select SOC_FAMILY_PSOC6 - select HAS_CYPRESS_DRIVERS - help - Enable support for Cypress PSoC6 MCU series - -config SOC_SERIES_PSOC63 - bool "Cypress PSoC6 series MCU - Bluetooth Low Energy" - select ARM - select SOC_FAMILY_PSOC6 - select HAS_CYPRESS_DRIVERS - help - Enable support for Cypress PSoC6-BLE MCU series diff --git a/soc/arm/cypress/psoc6/Kconfig.soc b/soc/arm/cypress/psoc6/Kconfig.soc deleted file mode 100644 index 49db89979e0..00000000000 --- a/soc/arm/cypress/psoc6/Kconfig.soc +++ /dev/null @@ -1,20 +0,0 @@ -# Cypress PSOC6 MCU line - -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Cypress PSoC6 MCU Selection" - depends on SOC_SERIES_PSOC62 || \ - SOC_SERIES_PSOC63 - -config SOC_PART_NUMBER_CY8C6247BZI_D54 - bool "CY8C6247BZI_D54" - depends on SOC_SERIES_PSOC62 - -config SOC_PART_NUMBER_CY8C6347BZI_BLD53 - bool "CY8C6347BZI_BLD53" - depends on SOC_SERIES_PSOC63 - -endchoice diff --git a/soc/arm/bcm_vk/valkyrie/CMakeLists.txt b/soc/arm/designstart/CMakeLists.txt similarity index 100% rename from soc/arm/bcm_vk/valkyrie/CMakeLists.txt rename to soc/arm/designstart/CMakeLists.txt diff --git a/soc/arm/designstart/Kconfig b/soc/arm/designstart/Kconfig new file mode 100644 index 00000000000..5ccdcaf661c --- /dev/null +++ b/soc/arm/designstart/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_DESIGNSTART + select ARM + +config SOC_DESIGNSTART_FPGA_CORTEX_M1 + select CPU_CORTEX_M1 + imply XIP + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +config SOC_DESIGNSTART_FPGA_CORTEX_M3 + select CPU_CORTEX_M3 + imply XIP + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE diff --git a/soc/arm/designstart/Kconfig.soc b/soc/arm/designstart/Kconfig.soc new file mode 100644 index 00000000000..19ceaea64e6 --- /dev/null +++ b/soc/arm/designstart/Kconfig.soc @@ -0,0 +1,27 @@ +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_DESIGNSTART + bool + select SOC_FAMILY_ARM + help + ARM DesignStart SoC Series + +config SOC_DESIGNSTART_FPGA_CORTEX_M1 + bool + select SOC_SERIES_DESIGNSTART + help + ARM Cortex-M1 DesignStart FPGA + +config SOC_DESIGNSTART_FPGA_CORTEX_M3 + bool + select SOC_SERIES_DESIGNSTART + help + ARM Cortex-M3 DesignStart FPGA + +config SOC_SERIES + default "designstart" if SOC_SERIES_DESIGNSTART + +config SOC + default "designstart_fpga_cortex_m1" if SOC_DESIGNSTART_FPGA_CORTEX_M1 + default "designstart_fpga_cortex_m3" if SOC_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/soc/arm/arm/designstart/soc.h b/soc/arm/designstart/soc.h similarity index 100% rename from soc/arm/arm/designstart/soc.h rename to soc/arm/designstart/soc.h diff --git a/soc/arm/fvp_aemv8a/CMakeLists.txt b/soc/arm/fvp_aemv8a/CMakeLists.txt new file mode 100644 index 00000000000..35d88056740 --- /dev/null +++ b/soc/arm/fvp_aemv8a/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/fvp_aemv8a/Kconfig b/soc/arm/fvp_aemv8a/Kconfig new file mode 100644 index 00000000000..879ff0030db --- /dev/null +++ b/soc/arm/fvp_aemv8a/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2021 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_FVP_AEMV8A + select ARM64 + help + Enable support for ARM FVP AEMv8A AArch64 Series + +config SOC_FVP_BASE_REVC_2XAEMV8A + select CPU_CORTEX_A53 diff --git a/soc/arm/fvp_aemv8a/Kconfig.defconfig b/soc/arm/fvp_aemv8a/Kconfig.defconfig new file mode 100644 index 00000000000..38c672c7675 --- /dev/null +++ b/soc/arm/fvp_aemv8a/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2021 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_FVP_AEMV8A + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 + +config NUM_IRQS + default 16384 if GIC_V3_ITS + default 128 if !GIC_V3_ITS + +if SOC_FVP_BASE_REVC_2XAEMV8A + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +endif # SOC_FVP_BASE_REVC_2XAEMV8A + +endif # SOC_SERIES_FVP_AEMV8A diff --git a/soc/arm/fvp_aemv8a/Kconfig.soc b/soc/arm/fvp_aemv8a/Kconfig.soc new file mode 100644 index 00000000000..bf773915674 --- /dev/null +++ b/soc/arm/fvp_aemv8a/Kconfig.soc @@ -0,0 +1,15 @@ +# Copyright (c) 2021 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_FVP_AEMV8A + bool + select SOC_FAMILY_ARM64 + +config SOC_FVP_BASE_REVC_2XAEMV8A + bool + +config SOC + default "fvp_base_revc_2xaemv8a" if SOC_FVP_BASE_REVC_2XAEMV8A + +config SOC_SERIES + default "fvp_aemv8a" if SOC_SERIES_FVP_AEMV8A diff --git a/soc/arm64/arm/fvp_aemv8a/mmu_regions.c b/soc/arm/fvp_aemv8a/mmu_regions.c similarity index 100% rename from soc/arm64/arm/fvp_aemv8a/mmu_regions.c rename to soc/arm/fvp_aemv8a/mmu_regions.c diff --git a/soc/arm/fvp_aemv8r/CMakeLists.txt b/soc/arm/fvp_aemv8r/CMakeLists.txt new file mode 100644 index 00000000000..09a01f47ebd --- /dev/null +++ b/soc/arm/fvp_aemv8r/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +if(CONFIG_SOC_FVP_AEMV8R_AARCH64) + zephyr_library_sources(aarch64/soc.c) + zephyr_library_sources_ifdef(CONFIG_ARM_MPU aarch64/arm_mpu_regions.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_FVP_AEMV8R_AARCH32) + zephyr_library_sources_ifdef(CONFIG_ARM_MPU aarch32/arm_mpu_regions.c) + zephyr_library_sources(aarch32/soc.c) + zephyr_include_directories(aarch32) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/arm/fvp_aemv8r/Kconfig b/soc/arm/fvp_aemv8r/Kconfig new file mode 100644 index 00000000000..7713ed672be --- /dev/null +++ b/soc/arm/fvp_aemv8r/Kconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FVP_AEMV8R_AARCH64 + select CPU_CORTEX_R82 + select CPU_HAS_MPU + select GIC_SINGLE_SECURITY_STATE + select ARM64 + +config SOC_FVP_AEMV8R_AARCH32 + select CPU_CORTEX_R52 + select CPU_HAS_ARM_MPU + select CPU_HAS_MPU + select VFP_DP_D32_FP16_FMAC if !USE_SWITCH + select GIC_V3 + select GIC_SINGLE_SECURITY_STATE + select PLATFORM_SPECIFIC_INIT + select ARM diff --git a/soc/arm/fvp_aemv8r/Kconfig.defconfig b/soc/arm/fvp_aemv8r/Kconfig.defconfig new file mode 100644 index 00000000000..8fd46271f2c --- /dev/null +++ b/soc/arm/fvp_aemv8r/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_FVP_AEMV8R + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 + +config NUM_IRQS + default 128 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config MAX_DOMAIN_PARTITIONS + default 8 if SOC_FVP_AEMV8R_AARCH64 + default 24 if USERSPACE && SOC_FVP_AEMV8R_AARCH32 + +endif # SOC_SERIES_FVP_AEMV8R diff --git a/soc/arm/fvp_aemv8r/Kconfig.soc b/soc/arm/fvp_aemv8r/Kconfig.soc new file mode 100644 index 00000000000..296de41643b --- /dev/null +++ b/soc/arm/fvp_aemv8r/Kconfig.soc @@ -0,0 +1,33 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_FVP_AEMV8R + bool + help + Enable support for ARM FVP AEMv8R AArch64 Series + +config SOC_FVP_AEMV8R_AARCH64 + bool + select SOC_SERIES_FVP_AEMV8R + select SOC_FAMILY_ARM64 + +config SOC_FVP_AEMV8R_AARCH32 + bool + select SOC_SERIES_FVP_AEMV8R + select SOC_FAMILY_ARM + +config SOC_FVP_AEMV8R_SIMULATE_CPU_PM + bool "Simulate CPU Power Management for FVP_BaseR_AEMv8R" + depends on SOC_FVP_AEMV8R_AARCH64 + help + It simulates the cpu power management function for + FVP_BaseR_AEMv8R. When zephyr kernel try to bring up secondary + core through pm_cpu_on(), it always succeeds because + it indeed bring up secondary core successfully. + +config SOC_SERIES + default "fvp_aemv8r" if SOC_SERIES_FVP_AEMV8R + +config SOC + default "fvp_aemv8r_aarch64" if SOC_FVP_AEMV8R_AARCH64 + default "fvp_aemv8r_aarch32" if SOC_FVP_AEMV8R_AARCH32 diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/arm_mpu_regions.c b/soc/arm/fvp_aemv8r/aarch32/arm_mpu_regions.c similarity index 100% rename from soc/arm/arm/fvp_aemv8r_aarch32/arm_mpu_regions.c rename to soc/arm/fvp_aemv8r/aarch32/arm_mpu_regions.c diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/soc.c b/soc/arm/fvp_aemv8r/aarch32/soc.c similarity index 100% rename from soc/arm/arm/fvp_aemv8r_aarch32/soc.c rename to soc/arm/fvp_aemv8r/aarch32/soc.c diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/soc.h b/soc/arm/fvp_aemv8r/aarch32/soc.h similarity index 100% rename from soc/arm/arm/fvp_aemv8r_aarch32/soc.h rename to soc/arm/fvp_aemv8r/aarch32/soc.h diff --git a/soc/arm64/arm/fvp_aemv8r/arm_mpu_regions.c b/soc/arm/fvp_aemv8r/aarch64/arm_mpu_regions.c similarity index 100% rename from soc/arm64/arm/fvp_aemv8r/arm_mpu_regions.c rename to soc/arm/fvp_aemv8r/aarch64/arm_mpu_regions.c diff --git a/soc/arm64/arm/fvp_aemv8r/soc.c b/soc/arm/fvp_aemv8r/aarch64/soc.c similarity index 100% rename from soc/arm64/arm/fvp_aemv8r/soc.c rename to soc/arm/fvp_aemv8r/aarch64/soc.c diff --git a/soc/arm/gd_gd32/Kconfig b/soc/arm/gd_gd32/Kconfig deleted file mode 100644 index 69f21b210d0..00000000000 --- a/soc/arm/gd_gd32/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_GD32 - bool - select HAS_GD32_HAL - select BUILD_OUTPUT_HEX - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -config SOC_FAMILY - string - default "gd_gd32" - depends on SOC_FAMILY_GD32 - -config SOC_FAMILY_GD32_ARM - bool - select SOC_FAMILY_GD32 - -if SOC_FAMILY_GD32_ARM - -source "soc/arm/gd_gd32/*/Kconfig.soc" - -endif # SOC_FAMILY_GD32_ARM diff --git a/soc/arm/gd_gd32/Kconfig.defconfig b/soc/arm/gd_gd32/Kconfig.defconfig deleted file mode 100644 index b6fae5d43ec..00000000000 --- a/soc/arm/gd_gd32/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_GD32 - -source "soc/arm/gd_gd32/*/Kconfig.defconfig.series" - -config PINCTRL - default y - -config RESET - default y - -config CLOCK_CONTROL - default y - -endif # SOC_FAMILY_GD32 diff --git a/soc/arm/gd_gd32/Kconfig.soc b/soc/arm/gd_gd32/Kconfig.soc deleted file mode 100644 index 20a2f4c8cb4..00000000000 --- a/soc/arm/gd_gd32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/gd_gd32/*/Kconfig.series" diff --git a/soc/arm/gd_gd32/common/pinctrl_soc.h b/soc/arm/gd_gd32/common/pinctrl_soc.h deleted file mode 100644 index 608dd00e95e..00000000000 --- a/soc/arm/gd_gd32/common/pinctrl_soc.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2021 Teslabs Engineering S.L. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * Gigadevice SoC specific helpers for pinctrl driver - */ - -#ifndef ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_ -#define ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_ - -#include - -#endif /* ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.series deleted file mode 100644 index 0b250325c45..00000000000 --- a/soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32A50X - -source "soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32a50x" - -endif # SOC_SERIES_GD32A50X diff --git a/soc/arm/gd_gd32/gd32a50x/Kconfig.series b/soc/arm/gd_gd32/gd32a50x/Kconfig.series deleted file mode 100644 index 2488c643727..00000000000 --- a/soc/arm/gd_gd32/gd32a50x/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32A50X - bool "GigaDevice GD32A50X series Cortex-M33 MCU" - select ARM - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CPU_CORTEX_M33 - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AF_PINMUX - select GD32_HAS_IRC_40K - select PLATFORM_SPECIFIC_INIT - help - Enable support for GigaDevice GD32A50X MCU series diff --git a/soc/arm/gd_gd32/gd32a50x/Kconfig.soc b/soc/arm/gd_gd32/gd32a50x/Kconfig.soc deleted file mode 100644 index 6601c77c11a..00000000000 --- a/soc/arm/gd_gd32/gd32a50x/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32A50X MCU Selection" - depends on SOC_SERIES_GD32A50X - - config SOC_GD32A503 - bool "gd32a503" - -endchoice diff --git a/soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.series deleted file mode 100644 index f16328e1e70..00000000000 --- a/soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32E10X - -source "soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32e10x" - -endif # SOC_SERIES_GD32E10X diff --git a/soc/arm/gd_gd32/gd32e10x/Kconfig.series b/soc/arm/gd_gd32/gd32e10x/Kconfig.series deleted file mode 100644 index 010e649671c..00000000000 --- a/soc/arm/gd_gd32/gd32e10x/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32E10X - bool "GigaDevice GD32E10X series Cortex-M4F MCU" - select ARM - select CPU_HAS_FPU - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AFIO_PINMUX - select GD32_HAS_IRC_40K - help - Enable support for GigaDevice GD32E10X MCU series diff --git a/soc/arm/gd_gd32/gd32e10x/Kconfig.soc b/soc/arm/gd_gd32/gd32e10x/Kconfig.soc deleted file mode 100644 index 42e6cd14d99..00000000000 --- a/soc/arm/gd_gd32/gd32e10x/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32E103 MCU Selection" - depends on SOC_SERIES_GD32E10X - - config SOC_GD32E103 - bool "gd32e103" -endchoice diff --git a/soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.series deleted file mode 100644 index f771aea44d9..00000000000 --- a/soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32E50X - -source "soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32e50x" - -endif # SOC_SERIES_GD32E50X diff --git a/soc/arm/gd_gd32/gd32e50x/Kconfig.series b/soc/arm/gd_gd32/gd32e50x/Kconfig.series deleted file mode 100644 index 546ca456793..00000000000 --- a/soc/arm/gd_gd32/gd32e50x/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32E50X - bool "GigaDevice GD32E50X series Cortex-M33 MCU" - select ARM - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select CPU_CORTEX_M33 - select ARMV8_M_DSP - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AFIO_PINMUX - select GD32_HAS_IRC_40K - help - Enable support for GigaDevice GD32E50X MCU series diff --git a/soc/arm/gd_gd32/gd32e50x/Kconfig.soc b/soc/arm/gd_gd32/gd32e50x/Kconfig.soc deleted file mode 100644 index 98494f0dab4..00000000000 --- a/soc/arm/gd_gd32/gd32e50x/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32E50X MCU Selection" - depends on SOC_SERIES_GD32E50X - - config SOC_GD32E507 - bool "gd32e507" - -endchoice diff --git a/soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.series deleted file mode 100644 index 4852255d255..00000000000 --- a/soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32F3X0 - -source "soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32f3x0" - -endif # SOC_SERIES_GD32F3X0 diff --git a/soc/arm/gd_gd32/gd32f3x0/Kconfig.series b/soc/arm/gd_gd32/gd32f3x0/Kconfig.series deleted file mode 100644 index 123d26a6f7a..00000000000 --- a/soc/arm/gd_gd32/gd32f3x0/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32F3X0 - bool "GigaDevice GD32F3X0 series Cortex-M4F MCU" - select ARM - select CPU_HAS_FPU - select CPU_CORTEX_M4 - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AF_PINMUX - select GD32_HAS_IRC_40K - help - Enable support for GigaDevice GD32F3X0 MCU series diff --git a/soc/arm/gd_gd32/gd32f3x0/Kconfig.soc b/soc/arm/gd_gd32/gd32f3x0/Kconfig.soc deleted file mode 100644 index 1acbaaf4ae0..00000000000 --- a/soc/arm/gd_gd32/gd32f3x0/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32F3X0 MCU Selection" - depends on SOC_SERIES_GD32F3X0 - - config SOC_GD32F350 - bool "gd32f350" -endchoice diff --git a/soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.series deleted file mode 100644 index 8923e1582a3..00000000000 --- a/soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32F403 - -source "soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.gd32f403" - -config SOC_SERIES - default "gd32f403" - -endif # SOC_SERIES_GD32F403 diff --git a/soc/arm/gd_gd32/gd32f403/Kconfig.series b/soc/arm/gd_gd32/gd32f403/Kconfig.series deleted file mode 100644 index 86c57f224f7..00000000000 --- a/soc/arm/gd_gd32/gd32f403/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32F403 - bool "GigaDevice GD32F403 series Cortex-M4F MCU" - select ARM - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AFIO_PINMUX - select GD32_HAS_IRC_40K - help - Enable support for GigaDevice GD32F403 MCU series diff --git a/soc/arm/gd_gd32/gd32f403/Kconfig.soc b/soc/arm/gd_gd32/gd32f403/Kconfig.soc deleted file mode 100644 index 17e960ce40c..00000000000 --- a/soc/arm/gd_gd32/gd32f403/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32F403 MCU Selection" - depends on SOC_SERIES_GD32F403 - - config SOC_GD32F403 - bool "gd32f403" - -endchoice diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.series deleted file mode 100644 index a4ccaed4e80..00000000000 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32F4XX - -source "soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32f4xx" - -endif # SOC_SERIES_GD32F4XX diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.series b/soc/arm/gd_gd32/gd32f4xx/Kconfig.series deleted file mode 100644 index 9b1d74dfa97..00000000000 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32F4XX - bool "GigaDevice GD32F4XX series Cortex-M4F MCU" - select ARM - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select CPU_CORTEX_M4 - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AF_PINMUX - select GD32_HAS_IRC_32K - help - Enable support for GigaDevice GD32F4XX MCU series diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.soc b/soc/arm/gd_gd32/gd32f4xx/Kconfig.soc deleted file mode 100644 index d0cfda3817c..00000000000 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.soc +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32F4XX MCU Selection" - depends on SOC_SERIES_GD32F4XX - - config SOC_GD32F405 - bool "gd32f405" - - config SOC_GD32F407 - bool "gd32f407" - - config SOC_GD32F450 - bool "gd32f450" - - config SOC_GD32F470 - bool "gd32f470" - -endchoice diff --git a/soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.series deleted file mode 100644 index 36a6476dbfb..00000000000 --- a/soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32L23X - -source "soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32l23x" - -endif # SOC_SERIES_GD32L23X diff --git a/soc/arm/gd_gd32/gd32l23x/Kconfig.series b/soc/arm/gd_gd32/gd32l23x/Kconfig.series deleted file mode 100644 index d6125ca4152..00000000000 --- a/soc/arm/gd_gd32/gd32l23x/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32L23X - bool "GigaDevice GD32L23X series Cortex-M23 MCU" - select ARM - select CPU_CORTEX_M23 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AF_PINMUX - select GD32_HAS_IRC_32K - help - Enable support for GigaDevice GD32L23X MCU series diff --git a/soc/arm/gd_gd32/gd32l23x/Kconfig.soc b/soc/arm/gd_gd32/gd32l23x/Kconfig.soc deleted file mode 100644 index 927ef4158fa..00000000000 --- a/soc/arm/gd_gd32/gd32l23x/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32L23X MCU Selection" - depends on SOC_SERIES_GD32L23X - - config SOC_GD32L233 - bool "gd32l233" -endchoice diff --git a/soc/arm/infineon_cat1/CMakeLists.txt b/soc/arm/infineon_cat1/CMakeLists.txt deleted file mode 100644 index 83da7b62c08..00000000000 --- a/soc/arm/infineon_cat1/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(common/) -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/infineon_cat1/Kconfig b/soc/arm/infineon_cat1/Kconfig deleted file mode 100644 index c0c79bb00f9..00000000000 --- a/soc/arm/infineon_cat1/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - - -config SOC_FAMILY_INFINEON_CAT1 - bool - -config SOC_FAMILY_INFINEON_CAT1A - bool - -if SOC_FAMILY_INFINEON_CAT1 -source "soc/arm/infineon_cat1/*/Kconfig.soc" - -config SOC_FAMILY - string - default "infineon_cat1" - -endif # SOC_FAMILY_INFINEON_CAT1 diff --git a/soc/arm/infineon_cat1/Kconfig.defconfig b/soc/arm/infineon_cat1/Kconfig.defconfig deleted file mode 100644 index 28567181600..00000000000 --- a/soc/arm/infineon_cat1/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/infineon_cat1/*/Kconfig.defconfig" diff --git a/soc/arm/infineon_cat1/Kconfig.soc b/soc/arm/infineon_cat1/Kconfig.soc deleted file mode 100644 index 5d34753aa6a..00000000000 --- a/soc/arm/infineon_cat1/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/infineon_cat1/*/Kconfig.series" diff --git a/soc/arm/infineon_cat1/psoc6/CMakeLists.txt b/soc/arm/infineon_cat1/psoc6/CMakeLists.txt deleted file mode 100644 index 26c9fb8cd9c..00000000000 --- a/soc/arm/infineon_cat1/psoc6/CMakeLists.txt +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) -zephyr_include_directories(.) - -# Add sections -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 NOINIT noinit.ld) - -# Add section for cm0p image ROM -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ROM_START SORT_KEY 0x0cm0p rom_cm0image.ld) - -# Add section for cm0p image RAM -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAM_SECTIONS SORT_KEY 0 ram_cm0image.ld) - -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAMFUNC_SECTION SORT_KEY 0 ram_func.ld) - -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 RODATA SORT_KEY 0 rom.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig deleted file mode 100644 index f7bf4bc8076..00000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_INFINEON_CAT1 -source "soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.*" - -config SOC_SERIES - default "psoc6" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE - hex - default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP - -config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE - hex - default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP - -endif # SOC_FAMILY_INFINEON_CAT1A diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc deleted file mode 100644 index f0aa02e7536..00000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.*" diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_01 b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_01 deleted file mode 100644 index 7452cb797ef..00000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_01 +++ /dev/null @@ -1,77 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_01 based MCU default configuration - -if SOC_DIE_PSOC6_01 - -config NUM_IRQS - default 32 if CPU_CORTEX_M0PLUS - default 147 if CPU_CORTEX_M4 - -config SOC - default "CY8C6036BZI_F04" if SOC_CY8C6036BZI_F04 - default "CY8C6016BZI_F04" if SOC_CY8C6016BZI_F04 - default "CY8C6116BZI_F54" if SOC_CY8C6116BZI_F54 - default "CY8C6136BZI_F14" if SOC_CY8C6136BZI_F14 - default "CY8C6136BZI_F34" if SOC_CY8C6136BZI_F34 - default "CY8C6137BZI_F14" if SOC_CY8C6137BZI_F14 - default "CY8C6137BZI_F34" if SOC_CY8C6137BZI_F34 - default "CY8C6137BZI_F54" if SOC_CY8C6137BZI_F54 - default "CY8C6117BZI_F34" if SOC_CY8C6117BZI_F34 - default "CY8C6246BZI_D04" if SOC_CY8C6246BZI_D04 - default "CY8C6247BZI_D44" if SOC_CY8C6247BZI_D44 - default "CY8C6247BZI_D34" if SOC_CY8C6247BZI_D34 - default "CY8C6247BZI_D54" if SOC_CY8C6247BZI_D54 - default "CY8C6336BZI_BLF03" if SOC_CY8C6336BZI_BLF03 - default "CY8C6316BZI_BLF03" if SOC_CY8C6316BZI_BLF03 - default "CY8C6316BZI_BLF53" if SOC_CY8C6316BZI_BLF53 - default "CY8C6336BZI_BLD13" if SOC_CY8C6336BZI_BLD13 - default "CY8C6347BZI_BLD43" if SOC_CY8C6347BZI_BLD43 - default "CY8C6347BZI_BLD33" if SOC_CY8C6347BZI_BLD33 - default "CY8C6347BZI_BLD53" if SOC_CY8C6347BZI_BLD53 - default "CY8C6347FMI_BLD13" if SOC_CY8C6347FMI_BLD13 - default "CY8C6347FMI_BLD43" if SOC_CY8C6347FMI_BLD43 - default "CY8C6347FMI_BLD33" if SOC_CY8C6347FMI_BLD33 - default "CY8C6347FMI_BLD53" if SOC_CY8C6347FMI_BLD53 - default "CY8C6137FDI_F02" if SOC_CY8C6137FDI_F02 - default "CY8C6117FDI_F02" if SOC_CY8C6117FDI_F02 - default "CY8C6247FDI_D02" if SOC_CY8C6247FDI_D02 - default "CY8C6247FDI_D32" if SOC_CY8C6247FDI_D32 - default "CY8C6336BZI_BUD13" if SOC_CY8C6336BZI_BUD13 - default "CY8C6347BZI_BUD43" if SOC_CY8C6347BZI_BUD43 - default "CY8C6347BZI_BUD33" if SOC_CY8C6347BZI_BUD33 - default "CY8C6347BZI_BUD53" if SOC_CY8C6347BZI_BUD53 - default "CY8C6337BZI_BLF13" if SOC_CY8C6337BZI_BLF13 - default "CY8C6136FDI_F42" if SOC_CY8C6136FDI_F42 - default "CY8C6247FDI_D52" if SOC_CY8C6247FDI_D52 - default "CY8C6136FTI_F42" if SOC_CY8C6136FTI_F42 - default "CY8C6247FTI_D52" if SOC_CY8C6247FTI_D52 - default "CY8C6247BZI_AUD54" if SOC_CY8C6247BZI_AUD54 - default "CY8C6336BZI_BLF04" if SOC_CY8C6336BZI_BLF04 - default "CY8C6316BZI_BLF04" if SOC_CY8C6316BZI_BLF04 - default "CY8C6316BZI_BLF54" if SOC_CY8C6316BZI_BLF54 - default "CY8C6336BZI_BLD14" if SOC_CY8C6336BZI_BLD14 - default "CY8C6347BZI_BLD44" if SOC_CY8C6347BZI_BLD44 - default "CY8C6347BZI_BLD34" if SOC_CY8C6347BZI_BLD34 - default "CY8C6347BZI_BLD54" if SOC_CY8C6347BZI_BLD54 - default "CY8C6247BFI_D54" if SOC_CY8C6247BFI_D54 - default "CYBLE_416045_02_device" if SOC_CYBLE_416045_02 - default "CY8C6347FMI_BUD53" if SOC_CY8C6347FMI_BUD53 - default "CY8C6347FMI_BUD13" if SOC_CY8C6347FMI_BUD13 - default "CY8C6347FMI_BUD43" if SOC_CY8C6347FMI_BUD43 - default "CY8C6347FMI_BUD33" if SOC_CY8C6347FMI_BUD33 - default "CY8C6137WI_F54" if SOC_CY8C6137WI_F54 - default "CY8C6117WI_F34" if SOC_CY8C6117WI_F34 - default "CY8C6247WI_D54" if SOC_CY8C6247WI_D54 - default "CY8C6336LQI_BLF02" if SOC_CY8C6336LQI_BLF02 - default "CY8C6336LQI_BLF42" if SOC_CY8C6336LQI_BLF42 - default "CY8C6347LQI_BLD52" if SOC_CY8C6347LQI_BLD52 - default "CYB06447BZI_BLD54" if SOC_CYB06447BZI_BLD54 - default "CYB06447BZI_BLD53" if SOC_CYB06447BZI_BLD53 - default "CYB06447BZI_D54" if SOC_CYB06447BZI_D54 - -# add additional die specific params - -endif # SOC_DIE_PSOC6_01 diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_02 b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_02 deleted file mode 100644 index 087d5e05978..00000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_02 +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_02 based MCU default configuration - -if SOC_DIE_PSOC6_02 - -config NUM_IRQS - default 32 if CPU_CORTEX_M0PLUS - default 168 if CPU_CORTEX_M4 - -config SOC - default "CYB0644ABZI_S2D44" if SOC_CYB0644ABZI_S2D44 - default "CYS0644ABZI_S2D44" if SOC_CYS0644ABZI_S2D44 - default "CY8C624ABZI_S2D44A0" if SOC_CY8C624ABZI_S2D44A0 - default "CY8C624ABZI_S2D44" if SOC_CY8C624ABZI_S2D44 - default "CY8C624AAZI_S2D44" if SOC_CY8C624AAZI_S2D44 - default "CY8C624AFNI_S2D43" if SOC_CY8C624AFNI_S2D43 - default "CY8C624ABZI_S2D04" if SOC_CY8C624ABZI_S2D04 - default "CY8C624ABZI_S2D14" if SOC_CY8C624ABZI_S2D14 - default "CY8C624AAZI_S2D14" if SOC_CY8C624AAZI_S2D14 - default "CY8C6248AZI_S2D14" if SOC_CY8C6248AZI_S2D14 - default "CY8C6248BZI_S2D44" if SOC_CY8C6248BZI_S2D44 - default "CY8C6248AZI_S2D44" if SOC_CY8C6248AZI_S2D44 - default "CY8C6248FNI_S2D43" if SOC_CY8C6248FNI_S2D43 - default "CY8C614ABZI_S2F04" if SOC_CY8C614ABZI_S2F04 - default "CY8C614AAZI_S2F04" if SOC_CY8C614AAZI_S2F04 - default "CY8C614AFNI_S2F03" if SOC_CY8C614AFNI_S2F03 - default "CY8C614AAZI_S2F14" if SOC_CY8C614AAZI_S2F14 - default "CY8C614ABZI_S2F44" if SOC_CY8C614ABZI_S2F44 - default "CY8C614AAZI_S2F44" if SOC_CY8C614AAZI_S2F44 - default "CY8C614AFNI_S2F43" if SOC_CY8C614AFNI_S2F43 - default "CY8C6148BZI_S2F44" if SOC_CY8C6148BZI_S2F44 - default "CY8C6148AZI_S2F44" if SOC_CY8C6148AZI_S2F44 - default "CY8C6148FNI_S2F43" if SOC_CY8C6148FNI_S2F43 - default "CY8C624ABZI_D44" if SOC_CY8C624ABZI_D44 - default "CY8C624ALQI_S2D42" if SOC_CY8C624ALQI_S2D42 - default "CY8C624ALQI_S2D02" if SOC_CY8C624ALQI_S2D02 - default "CY8C6248LQI_S2D42" if SOC_CY8C6248LQI_S2D42 - default "CY8C6248LQI_S2D02" if SOC_CY8C6248LQI_S2D02 - default "CY8C614ALQI_S2F42" if SOC_CY8C614ALQI_S2F42 - default "CY8C614ALQI_S2F02" if SOC_CY8C614ALQI_S2F02 - default "CY8C6148LQI_S2F42" if SOC_CY8C6148LQI_S2F42 - default "CY8C6148LQI_S2F02" if SOC_CY8C6148LQI_S2F02 - -# add additional die specific params - -endif # SOC_DIE_PSOC6_02 diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_04 b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_04 deleted file mode 100644 index 622a0af848f..00000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_04 +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# Copyright (c) David Ullmann -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_04 based MCU default configuration - -if SOC_DIE_PSOC6_04 - -config NUM_IRQS - default 16 if CPU_CORTEX_M0PLUS - default 175 if CPU_CORTEX_M4 - -config SOC - default "CY8C6244AZI_S4D92" if SOC_CY8C6244AZI_S4D92 - default "CY8C6244LQI_S4D92" if SOC_CY8C6244LQI_S4D92 - default "CY8C6244AZI_S4D93" if SOC_CY8C6244AZI_S4D93 - default "CY8C6244AZI_S4D82" if SOC_CY8C6244AZI_S4D82 - default "CY8C6244LQI_S4D82" if SOC_CY8C6244LQI_S4D82 - default "CY8C6244AZI_S4D83" if SOC_CY8C6244AZI_S4D83 - default "CY8C6244AZI_S4D62" if SOC_CY8C6244AZI_S4D62 - default "CY8C6244LQI_S4D62" if SOC_CY8C6244LQI_S4D62 - default "CY8C6244AZI_S4D12" if SOC_CY8C6244AZI_S4D12 - default "CY8C6244LQI_S4D12" if SOC_CY8C6244LQI_S4D12 - default "CY8C6144AZI_S4F92" if SOC_CY8C6144AZI_S4F92 - default "CY8C6144LQI_S4F92" if SOC_CY8C6144LQI_S4F92 - default "CY8C6144AZI_S4F93" if SOC_CY8C6144AZI_S4F93 - default "CY8C6144AZI_S4F82" if SOC_CY8C6144AZI_S4F82 - default "CY8C6144LQI_S4F82" if SOC_CY8C6144LQI_S4F82 - default "CY8C6144AZI_S4F83" if SOC_CY8C6144AZI_S4F83 - default "CY8C6144AZI_S4F62" if SOC_CY8C6144AZI_S4F62 - default "CY8C6144LQI_S4F62" if SOC_CY8C6144LQI_S4F62 - default "CY8C6144AZI_S4F12" if SOC_CY8C6144AZI_S4F12 - default "CY8C6144LQI_S4F12" if SOC_CY8C6144LQI_S4F12 - - -endif # SOC_DIE_PSOC6_04 diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.series b/soc/arm/infineon_cat1/psoc6/Kconfig.series deleted file mode 100644 index e86402da73b..00000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.series +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Cypress PSoC™ 6 MCU lines -config SOC_SERIES_PSOC_60 - bool "Infineon PSoC™ 60 series MCU(Value Line)" - select SOC_FAMILY_INFINEON_CAT1 - help - Enable support for Infineon PSoC™ 60 MCU series - -config SOC_SERIES_PSOC_61 - bool "Infineon PSoC™ 61 series MCU (Programmable Line)" - select SOC_FAMILY_INFINEON_CAT1 - help - Enable support for Infineon PSoC™ 61 MCU series - -config SOC_SERIES_PSOC_62 - bool "Infineon PSoC™ 62 series MCU (Performance Line)" - select SOC_FAMILY_INFINEON_CAT1 - help - Enable support for Infineon PSoC™ 62 MCU series - -config SOC_SERIES_PSOC_63 - bool "Infineon PSoC™ 63 series MCU (Connectivity Line)" - select SOC_FAMILY_INFINEON_CAT1 - help - Enable support for Infineon PSoC™ 63 MCU series - -config SOC_SERIES_PSOC_64 - bool "Infineon PSoC™ 64 series MCU (Security Line)" - select SOC_FAMILY_INFINEON_CAT1 - help - Enable support for Infineon PSoC™ 64 MCU series diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.soc b/soc/arm/infineon_cat1/psoc6/Kconfig.soc deleted file mode 100644 index d1652cca840..00000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.soc +++ /dev/null @@ -1,117 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6 die -config SOC_DIE_PSOC6 - bool - select ARM - select CPU_CORTEX_M4 - select CPU_HAS_ARM_MPU - select SOC_FAMILY_INFINEON_CAT1A - select DYNAMIC_INTERRUPTS - select CPU_HAS_FPU - -# Infineon PSoC6_01 die -config SOC_DIE_PSOC6_01 - bool - select SOC_DIE_PSOC6 - -# Infineon PSoC6_02 die -config SOC_DIE_PSOC6_02 - bool - select SOC_DIE_PSOC6 - -# Infineon PSoC6_03 die -config SOC_DIE_PSOC6_03 - bool - select SOC_DIE_PSOC6 - -# Infineon PSoC6_04 die -config SOC_DIE_PSOC6_04 - bool - select SOC_DIE_PSOC6 - -# Infineon soc packages -config SOC_PACKAGE_PSOC6_01_124_BGA - bool - -config SOC_PACKAGE_PSOC6_01_116_BGA_BLE - bool - -config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE - bool - -config SOC_PACKAGE_PSOC6_01_80_WLCSP - bool - -config SOC_PACKAGE_PSOC6_01_116_BGA_USB - bool - -config SOC_PACKAGE_PSOC6_01_124_BGA_SIP - bool - -config SOC_PACKAGE_PSOC6_01_43_SMT - bool - -config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB - bool - -config SOC_PACKAGE_PSOC6_01_68_QFN_BLE - bool - -config SOC_PACKAGE_PSOC6_02_124_BGA - bool - -config SOC_PACKAGE_PSOC6_02_128_TQFP - bool - -config SOC_PACKAGE_PSOC6_02_100_WLCSP - bool - -config SOC_PACKAGE_PSOC6_02_68_QFN - bool - -config SOC_PACKAGE_PSOC6_03_100_TQFP - bool - -config SOC_PACKAGE_PSOC6_03_68_QFN - bool - -config SOC_PACKAGE_PSOC6_03_49_WLCSP - bool - -config SOC_PACKAGE_PSOC6_04_64_TQFP - bool - -config SOC_PACKAGE_PSOC6_04_68_QFN - bool - -config SOC_PACKAGE_PSOC6_04_80_TQFP - bool - -## Infineon MCUs -choice - prompt "MPN" - osource "soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_*" -endchoice - -if SOC_FAMILY_INFINEON_CAT1A -## PSoC™ 6 Cortex M0+ prebuilt images -choice - prompt "PSoC™ 6 Cortex M0+ prebuilt images" - help - Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSoC™ 6 - dual-core MCU. The image is responsible for booting the Cortex-M4 on the device. - -config SOC_PSOC6_CM0P_IMAGE_SLEEP - bool "DeepSleep" - help - DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSoC™ 6 BLE - dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4 - application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4 - linker script. - -endchoice - -endif # SOC_FAMILY_INFINEON_CAT1A diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_01 b/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_01 deleted file mode 100644 index 1ae22e52ef7..00000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_01 +++ /dev/null @@ -1,365 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_01 series MCUs - -config SOC_CY8C6036BZI_F04 - bool "CY8C6036BZI_F04" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_60 - -config SOC_CY8C6016BZI_F04 - bool "CY8C6016BZI_F04" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_60 - -config SOC_CY8C6116BZI_F54 - bool "CY8C6116BZI_F54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6136BZI_F14 - bool "CY8C6136BZI_F14" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6136BZI_F34 - bool "CY8C6136BZI_F34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6137BZI_F14 - bool "CY8C6137BZI_F14" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6137BZI_F34 - bool "CY8C6137BZI_F34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6137BZI_F54 - bool "CY8C6137BZI_F54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6117BZI_F34 - bool "CY8C6117BZI_F34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6246BZI_D04 - bool "CY8C6246BZI_D04" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6247BZI_D44 - bool "CY8C6247BZI_D44" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6247BZI_D34 - bool "CY8C6247BZI_D34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6247BZI_D54 - bool "CY8C6247BZI_D54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6336BZI_BLF03 - bool "CY8C6336BZI_BLF03" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6316BZI_BLF03 - bool "CY8C6316BZI_BLF03" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6316BZI_BLF53 - bool "CY8C6316BZI_BLF53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6336BZI_BLD13 - bool "CY8C6336BZI_BLD13" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD43 - bool "CY8C6347BZI_BLD43" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD33 - bool "CY8C6347BZI_BLD33" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD53 - bool "CY8C6347BZI_BLD53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BLD13 - bool "CY8C6347FMI_BLD13" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BLD43 - bool "CY8C6347FMI_BLD43" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BLD33 - bool "CY8C6347FMI_BLD33" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BLD53 - bool "CY8C6347FMI_BLD53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6137FDI_F02 - bool "CY8C6137FDI_F02" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6117FDI_F02 - bool "CY8C6117FDI_F02" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6247FDI_D02 - bool "CY8C6247FDI_D02" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6247FDI_D32 - bool "CY8C6247FDI_D32" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6336BZI_BUD13 - bool "CY8C6336BZI_BUD13" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BUD43 - bool "CY8C6347BZI_BUD43" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BUD33 - bool "CY8C6347BZI_BUD33" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BUD53 - bool "CY8C6347BZI_BUD53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6337BZI_BLF13 - bool "CY8C6337BZI_BLF13" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6136FDI_F42 - bool "CY8C6136FDI_F42" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6247FDI_D52 - bool "CY8C6247FDI_D52" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6136FTI_F42 - bool "CY8C6136FTI_F42" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6247FTI_D52 - bool "CY8C6247FTI_D52" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6247BZI_AUD54 - bool "CY8C6247BZI_AUD54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6336BZI_BLF04 - bool "CY8C6336BZI_BLF04" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6316BZI_BLF04 - bool "CY8C6316BZI_BLF04" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6316BZI_BLF54 - bool "CY8C6316BZI_BLF54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6336BZI_BLD14 - bool "CY8C6336BZI_BLD14" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD44 - bool "CY8C6347BZI_BLD44" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD34 - bool "CY8C6347BZI_BLD34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD54 - bool "CY8C6347BZI_BLD54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6247BFI_D54 - bool "CY8C6247BFI_D54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CYBLE_416045_02 - bool "CYBLE_416045_02" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BUD53 - bool "CY8C6347FMI_BUD53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BUD13 - bool "CY8C6347FMI_BUD13" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BUD43 - bool "CY8C6347FMI_BUD43" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BUD33 - bool "CY8C6347FMI_BUD33" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6137WI_F54 - bool "CY8C6137WI_F54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6117WI_F34 - bool "CY8C6117WI_F34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6247WI_D54 - bool "CY8C6247WI_D54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6336LQI_BLF02 - bool "CY8C6336LQI_BLF02" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_68_QFN_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6336LQI_BLF42 - bool "CY8C6336LQI_BLF42" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_68_QFN_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347LQI_BLD52 - bool "CY8C6347LQI_BLD52" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_68_QFN_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CYB06447BZI_BLD54 - bool "CYB06447BZI_BLD54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_64 - -config SOC_CYB06447BZI_BLD53 - bool "CYB06447BZI_BLD53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_64 - -config SOC_CYB06447BZI_D54 - bool "CYB06447BZI_D54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_64 diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_02 b/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_02 deleted file mode 100644 index c9e9a92ba2d..00000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_02 +++ /dev/null @@ -1,197 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_02 series MCUs - -config SOC_CYB0644ABZI_S2D44 - bool "CYB0644ABZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_64 - -config SOC_CYS0644ABZI_S2D44 - bool "CYS0644ABZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_64 - -config SOC_CY8C624ABZI_S2D44A0 - bool "CY8C624ABZI_S2D44A0" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624ABZI_S2D44 - bool "CY8C624ABZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624AAZI_S2D44 - bool "CY8C624AAZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624AFNI_S2D43 - bool "CY8C624AFNI_S2D43" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_100_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624ABZI_S2D04 - bool "CY8C624ABZI_S2D04" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624ABZI_S2D14 - bool "CY8C624ABZI_S2D14" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624AAZI_S2D14 - bool "CY8C624AAZI_S2D14" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248AZI_S2D14 - bool "CY8C6248AZI_S2D14" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248BZI_S2D44 - bool "CY8C6248BZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248AZI_S2D44 - bool "CY8C6248AZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248FNI_S2D43 - bool "CY8C6248FNI_S2D43" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_100_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C614ABZI_S2F04 - bool "CY8C614ABZI_S2F04" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614AAZI_S2F04 - bool "CY8C614AAZI_S2F04" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614AFNI_S2F03 - bool "CY8C614AFNI_S2F03" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_100_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614AAZI_S2F14 - bool "CY8C614AAZI_S2F14" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614ABZI_S2F44 - bool "CY8C614ABZI_S2F44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614AAZI_S2F44 - bool "CY8C614AAZI_S2F44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614AFNI_S2F43 - bool "CY8C614AFNI_S2F43" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_100_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6148BZI_S2F44 - bool "CY8C6148BZI_S2F44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6148AZI_S2F44 - bool "CY8C6148AZI_S2F44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6148FNI_S2F43 - bool "CY8C6148FNI_S2F43" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_100_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C624ABZI_D44 - bool "CY8C624ABZI_D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624ALQI_S2D42 - bool "CY8C624ALQI_S2D42" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624ALQI_S2D02 - bool "CY8C624ALQI_S2D02" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248LQI_S2D42 - bool "CY8C6248LQI_S2D42" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248LQI_S2D02 - bool "CY8C6248LQI_S2D02" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C614ALQI_S2F42 - bool "CY8C614ALQI_S2F42" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614ALQI_S2F02 - bool "CY8C614ALQI_S2F02" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6148LQI_S2F42 - bool "CY8C6148LQI_S2F42" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6148LQI_S2F02 - bool "CY8C6148LQI_S2F02" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_61 diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_04 b/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_04 deleted file mode 100644 index b18e8ecaa82..00000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_04 +++ /dev/null @@ -1,125 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_04 series MCUs - -config SOC_CY8C6244AZI_S4D92 - bool "CY8C6244AZI_S4D92" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244LQI_S4D92 - bool "CY8C6244LQI_S4D92" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244AZI_S4D93 - bool "CY8C6244AZI_S4D93" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_80_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244AZI_S4D82 - bool "CY8C6244AZI_S4D82" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244LQI_S4D82 - bool "CY8C6244LQI_S4D82" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244AZI_S4D83 - bool "CY8C6244AZI_S4D83" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_80_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244AZI_S4D62 - bool "CY8C6244AZI_S4D62" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244LQI_S4D62 - bool "CY8C6244LQI_S4D62" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244AZI_S4D12 - bool "CY8C6244AZI_S4D12" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244LQI_S4D12 - bool "CY8C6244LQI_S4D12" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6144AZI_S4F92 - bool "CY8C6144AZI_S4F92" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144LQI_S4F92 - bool "CY8C6144LQI_S4F92" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144AZI_S4F93 - bool "CY8C6144AZI_S4F93" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_80_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144AZI_S4F82 - bool "CY8C6144AZI_S4F82" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144LQI_S4F82 - bool "CY8C6144LQI_S4F82" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144AZI_S4F83 - bool "CY8C6144AZI_S4F83" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_80_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144AZI_S4F62 - bool "CY8C6144AZI_S4F62" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144LQI_S4F62 - bool "CY8C6144LQI_S4F62" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144AZI_S4F12 - bool "CY8C6144AZI_S4F12" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144LQI_S4F12 - bool "CY8C6144LQI_S4F12" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_61 diff --git a/soc/arm/infineon_xmc/4xxx/CMakeLists.txt b/soc/arm/infineon_xmc/4xxx/CMakeLists.txt deleted file mode 100644 index 8216f9a09ee..00000000000 --- a/soc/arm/infineon_xmc/4xxx/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -zephyr_sources(soc.c) -zephyr_linker_sources(NOINIT noinit.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.series b/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.series deleted file mode 100644 index 2e92bd626bf..00000000000 --- a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# XMC 4xxx series configuration options -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -if SOC_SERIES_XMC_4XXX - -config SOC_SERIES - default "4xxx" - -config NUM_IRQS - default 112 - -source "soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc*" - -endif # SOC_SERIES_XMC_4XXX diff --git a/soc/arm/infineon_xmc/4xxx/Kconfig.series b/soc/arm/infineon_xmc/4xxx/Kconfig.series deleted file mode 100644 index 7c7f9a85496..00000000000 --- a/soc/arm/infineon_xmc/4xxx/Kconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# XMC4xxx MCU series -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_XMC_4XXX - bool "XMC 4xxx Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_XMC - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select HAS_XMCLIB_UART - select HAS_XMCLIB_FLASH - select HAS_XMCLIB_ERU - select HAS_XMCLIB_VADC - select HAS_XMCLIB_DMA - select HAS_XMCLIB_SPI - select HAS_XMCLIB_I2C - select HAS_XMCLIB_CCU - select HAS_XMCLIB_WDT - select HAS_XMCLIB_ETH - select HAS_XMCLIB_CAN - help - Enable support for XMC 4xxx MCU series diff --git a/soc/arm/infineon_xmc/4xxx/Kconfig.soc b/soc/arm/infineon_xmc/4xxx/Kconfig.soc deleted file mode 100644 index 83fd92a23d3..00000000000 --- a/soc/arm/infineon_xmc/4xxx/Kconfig.soc +++ /dev/null @@ -1,38 +0,0 @@ -# XMC 4xxx MCU line -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "XMC 4xxx MCU Selection" - depends on SOC_SERIES_XMC_4XXX - -config SOC_XMC4500 - bool "SOC_XMC4500" - select HAS_XMCLIB - -config SOC_XMC4700 - bool "SOC_XMC4700" - select HAS_XMCLIB - -endchoice - -if SOC_SERIES_XMC_4XXX - -config SOC_PART_NUMBER_F100X1024 - bool - -config SOC_PART_NUMBER_F144X2048 - bool - -config SOC_PART_NUMBER_XMC_4XXX - string - default "F100x1024" if SOC_PART_NUMBER_F100X1024 - default "F144x2048" if SOC_PART_NUMBER_F144X2048 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_XMC_4XXX diff --git a/soc/arm/infineon_xmc/Kconfig b/soc/arm/infineon_xmc/Kconfig deleted file mode 100644 index 8252399754b..00000000000 --- a/soc/arm/infineon_xmc/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -config SOC_FAMILY_XMC - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select PLATFORM_SPECIFIC_INIT - -if SOC_FAMILY_XMC - -config SOC_FAMILY - string - default "infineon_xmc" - -source "soc/arm/infineon_xmc/*/Kconfig.soc" - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_XMC_4XXX if SOC_SERIES_XMC_4XXX - -endif # SOC_FAMILY_XMC diff --git a/soc/arm/infineon_xmc/Kconfig.defconfig b/soc/arm/infineon_xmc/Kconfig.defconfig deleted file mode 100644 index b7cd34f591a..00000000000 --- a/soc/arm/infineon_xmc/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -source "soc/arm/infineon_xmc/*/Kconfig.defconfig.series" - -if SOC_FAMILY_XMC - -config PINCTRL - default y - -endif # SOC_FAMILY_XMC diff --git a/soc/arm/infineon_xmc/Kconfig.soc b/soc/arm/infineon_xmc/Kconfig.soc deleted file mode 100644 index 05f2c3841c4..00000000000 --- a/soc/arm/infineon_xmc/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -source "soc/arm/infineon_xmc/*/Kconfig.series" diff --git a/soc/arm/intel_socfpga_std/CMakeLists.txt b/soc/arm/intel_socfpga_std/CMakeLists.txt deleted file mode 100644 index b2e4b540bf8..00000000000 --- a/soc/arm/intel_socfpga_std/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Intel Cyclone V SoC - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/intel_socfpga_std/Kconfig b/soc/arm/intel_socfpga_std/Kconfig deleted file mode 100644 index 22729a46343..00000000000 --- a/soc/arm/intel_socfpga_std/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support to Cyclone V SoC FPGA - -config SOC_FAMILY_INTEL_SOCFPGA_STD - bool - -if SOC_FAMILY_INTEL_SOCFPGA_STD -config SOC_FAMILY - string - default "intel_socfpga_std" - -source "soc/arm/intel_socfpga_std/*/Kconfig.soc" -endif diff --git a/soc/arm/intel_socfpga_std/Kconfig.defconfig b/soc/arm/intel_socfpga_std/Kconfig.defconfig deleted file mode 100644 index 1d1155a3c1b..00000000000 --- a/soc/arm/intel_socfpga_std/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC FPGA - -source "soc/arm/intel_socfpga_std/*/Kconfig.defconfig.series" diff --git a/soc/arm/intel_socfpga_std/Kconfig.soc b/soc/arm/intel_socfpga_std/Kconfig.soc deleted file mode 100644 index 207fa5a5c69..00000000000 --- a/soc/arm/intel_socfpga_std/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC FPGA - -source "soc/arm/intel_socfpga_std/*/Kconfig.series" diff --git a/soc/arm/intel_socfpga_std/cyclonev/CMakeLists.txt b/soc/arm/intel_socfpga_std/cyclonev/CMakeLists.txt deleted file mode 100644 index 4b94d9047e4..00000000000 --- a/soc/arm/intel_socfpga_std/cyclonev/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC FPGA - -zephyr_include_directories(.) -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev b/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev deleted file mode 100644 index e627daf0f39..00000000000 --- a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC FPGA - -if SOC_CYCLONE5 - -config SOC - default "intel_socfpga_std_cyclonev" - -config NUM_IRQS - int - default 211 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 231250000 - -endif diff --git a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.series b/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.series deleted file mode 100644 index bdca517d2c3..00000000000 --- a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC FPGA - -if SOC_SERIES_CYCLONE5 - -config SOC_SERIES - default "cyclonev" - -source "soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev*" - -endif # SOC_SERIES_CYCLONE5 diff --git a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.series b/soc/arm/intel_socfpga_std/cyclonev/Kconfig.series deleted file mode 100644 index e9fba7bdba2..00000000000 --- a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description -# Adding configuration options for Cyclone V SoC FPGA - -config SOC_SERIES_CYCLONE5 - bool "Intel SoC FPGA Cyclone5 Series" - select ARM - select CPU_CORTEX_A9 - select SOC_FAMILY_INTEL_SOCFPGA_STD - select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER - select ARCH_HAS_RESERVED_PAGE_FRAMES - help - Support for Intel SoC FPGA Series diff --git a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.soc b/soc/arm/intel_socfpga_std/cyclonev/Kconfig.soc deleted file mode 100644 index 8851d9e17b2..00000000000 --- a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support to Cyclone V SoC FPGA - -choice - prompt "Intel SoC FPGA Cyclone5" - depends on SOC_SERIES_CYCLONE5 - -config SOC_CYCLONE5 - bool "Intel SoC FPGA Cyclone5" -endchoice diff --git a/soc/arm/microchip_mec/Kconfig b/soc/arm/microchip_mec/Kconfig deleted file mode 100644 index 017344ab470..00000000000 --- a/soc/arm/microchip_mec/Kconfig +++ /dev/null @@ -1,222 +0,0 @@ -# Microchip MEC MCU line - -# Copyright (c) 2018, Intel Corporation -# Copyright (c) 2022, Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_MEC - bool - -if SOC_FAMILY_MEC -config SOC_FAMILY - string - default "microchip_mec" - -menuconfig MCHP_MEC_UNSIGNED_HEADER - bool "Create an unsigned output binary with MCHP MEC binary header" - help - On Microchip MEC series chip, the ROM code loads firmware image from flash - to RAM using a TAG to locate a Header which specifies the location and - size of the firmware image. Enable this to invoke the mec_spi_gen tool - which generates an SPI image with TAG, Header, and firmware binary. This - tool does not produce a signed image which can be authenticated by the - Boot-ROM. Use the full Microchip SPI image generator program for - authentication and all other Boot-ROM loader features. Refer to the MCHP - EVB boards for an example. - -if MCHP_MEC_UNSIGNED_HEADER - -config MCHP_MEC_HEADER_CHIP - string - default "mec152x" if SOC_SERIES_MEC1501X - default "mec172x" if SOC_SERIES_MEC172X - -choice MCHP_MEC_HEADER_SPI_FREQ_MHZ_CHOICE - prompt "Clock rate to use for SPI flash" - default MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 - help - This selects the SPI clock frequency that will be used for loading - firmware binary from flash to RAM. - -config MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 - bool "SPI flash clock rate of 12 MHz" - -config MCHP_MEC_HEADER_SPI_FREQ_MHZ_16 - bool "SPI flash clock rate of 16 MHz" - -config MCHP_MEC_HEADER_SPI_FREQ_MHZ_24 - bool "SPI flash clock rate of 24 MHz" - -config MCHP_MEC_HEADER_SPI_FREQ_MHZ_48 - bool "SPI flash clock rate of 48 MHz" - -endchoice - -config MCHP_MEC_HEADER_SPI_FREQ_MHZ - int - default 12 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 - default 25 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_16 - default 24 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_24 - default 48 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_48 - -choice MCHP_MEC_HEADER_SPI_READ_MODE_CHOICE - prompt "Reading mode used by the SPI flash" - default MCHP_MEC_HEADER_SPI_READ_MODE_FAST - help - This sets the reading mode that can be used by the SPI flash. - Reading modes supported are normal, fast, dual, and quad. - -config MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL - bool "SPI flash operates full-duplex with frequency (< 25 MHz)" - -config MCHP_MEC_HEADER_SPI_READ_MODE_FAST - bool "SPI flash operates full-duplex with fast reading mode" - -config MCHP_MEC_HEADER_SPI_READ_MODE_DUAL - bool "SPI flash operates with dual data reading mode" - -config MCHP_MEC_HEADER_SPI_READ_MODE_QUAD - bool "SPI flash operates with quad data reading mode" - -endchoice - -config MCHP_MEC_HEADER_SPI_READ_MODE - string - default "slow" if MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL - default "fast" if MCHP_MEC_HEADER_SPI_READ_MODE_FAST - default "dual" if MCHP_MEC_HEADER_SPI_READ_MODE_DUAL - default "quad" if MCHP_MEC_HEADER_SPI_READ_MODE_QUAD - -choice MCHP_MEC_HEADER_FLASH_SIZE_CHOICE - prompt "Flash size" - default MCHP_MEC_HEADER_FLASH_SIZE_16M - help - This sets the SPI flash size. - -config MCHP_MEC_HEADER_FLASH_SIZE_256K - bool "SPI flash size 256K Bytes" - help - The SPI flash size is 256K Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_512K - bool "SPI flash size 512K Bytes" - help - The SPI flash size is 512K Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_1M - bool "SPI flash size 1M Bytes" - help - The SPI flash size is 1M Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_2M - bool "SPI flash size 2M Bytes" - help - The SPI flash size is 2M Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_4M - bool "SPI flash size 4M Bytes" - help - The SPI flash size is 4M Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_8M - bool "SPI flash size 8M Bytes" - help - The SPI flash size is 8M Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_16M - bool "SPI flash size 16M Bytes" - help - The SPI flash size is 16M Bytes. - -endchoice - -config MCHP_MEC_HEADER_FLASH_SIZE - int - default 256 if MCHP_MEC_HEADER_FLASH_SIZE_256K - default 512 if MCHP_MEC_HEADER_FLASH_SIZE_512K - default 1024 if MCHP_MEC_HEADER_FLASH_SIZE_1M - default 2048 if MCHP_MEC_HEADER_FLASH_SIZE_2M - default 4096 if MCHP_MEC_HEADER_FLASH_SIZE_4M - default 8192 if MCHP_MEC_HEADER_FLASH_SIZE_8M - default 16384 if MCHP_MEC_HEADER_FLASH_SIZE_16M - -choice MCHP_MEC_HEADER_SPI_DRVSTR_CHOICE - prompt "Flash drive strength" - default MCHP_MEC_HEADER_SPI_DRVSTR_1X - help - This sets the SPI flash size. - -config MCHP_MEC_HEADER_SPI_DRVSTR_1X - bool "SPI flash drive strength multiplier 1" - help - The SPI flash size is 256K Bytes. - -config MCHP_MEC_HEADER_SPI_DRVSTR_2X - bool "SPI flash drive strength multiplier 2" - help - The SPI flash size is 256K Bytes. - -config MCHP_MEC_HEADER_SPI_DRVSTR_4X - bool "SPI flash drive strength multiplier 4" - help - The SPI flash size is 512K Bytes. - -config MCHP_MEC_HEADER_SPI_DRVSTR_6X - bool "SPI flash drive strength multiplier 6" - help - The SPI flash size is 1M Bytes. - -endchoice - -config MCHP_MEC_HEADER_SPI_DRVSTR - string - default "1x" if MCHP_MEC_HEADER_SPI_DRVSTR_1X - default "2x" if MCHP_MEC_HEADER_SPI_DRVSTR_2X - default "4x" if MCHP_MEC_HEADER_SPI_DRVSTR_4X - default "6x" if MCHP_MEC_HEADER_SPI_DRVSTR_6X - -choice MCHP_MEC_HEADER_SPI_SLEW_RATE_CHOICE - prompt "Slew rate of SPI pins" - default MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW - help - This sets the slew rate of the SPI pins. Default is slow - slew rate which is 1/2 the AHB clock rate. Fast slew is the - AHB clock rate. - -config MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW - bool "SPI pins slew rate is 1/2 AHB frequency" - -config MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST - bool "SPI pins slew rate is 1x AHB frequency" - -endchoice - -config MCHP_MEC_HEADER_SPI_SLEW_RATE - string - default "slow" if MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW - default "fast" if MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST - -config MCHP_MEC_HEADER_FLASH_SPI_MODE - int "Flash SPI Mode" - range 0 7 - default 0 - help - This three bit value corresponds to the QMSPI controllers clock idle and - input/output data phases. Bits[0:2] are CPOL:CPHA_MOSI:CPHA_MISO. Refer - to the data sheet. Default value is 0 corresponding to SPI Mode 0 - signalling. - Setting this field to 0 selects mode 0, CPOL=0, CPHA_MOSI=0, CPHA_MISO=0 - Setting this filed to 7 selects mode 3, CPOL=1, CPHA_MOSI=1, CPHA_MISO=1 - -config MCHP_HEADER_VERBOSE_OUTPUT - bool "Debug console output" - default n - help - Enable print output from SPI generator script for debug - -endif # MCHP_MEC_UNSIGNED_HEADER - -# Select SoC Part No. and configuration options -source "soc/arm/microchip_mec/*/Kconfig.soc" - -endif # SOC_FAMILY_MEC diff --git a/soc/arm/microchip_mec/Kconfig.defconfig b/soc/arm/microchip_mec/Kconfig.defconfig deleted file mode 100644 index f23bddaa1ed..00000000000 --- a/soc/arm/microchip_mec/Kconfig.defconfig +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/microchip_mec/*/Kconfig.defconfig.series" diff --git a/soc/arm/microchip_mec/Kconfig.soc b/soc/arm/microchip_mec/Kconfig.soc deleted file mode 100644 index 85734699608..00000000000 --- a/soc/arm/microchip_mec/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Microchip MEC172x, MEC1501 MCU line - -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/microchip_mec/*/Kconfig.series" diff --git a/soc/arm/microchip_mec/common/CMakeLists.txt b/soc/arm/microchip_mec/common/CMakeLists.txt deleted file mode 100644 index fe1dc724ec9..00000000000 --- a/soc/arm/microchip_mec/common/CMakeLists.txt +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_MEC172X - soc_i2c.c -) - -if (DEFINED CONFIG_MCHP_HEADER_VERBOSE_OUTPUT) - set(MCHP_HEADER_VERBOSE_OPTION "-v") -endif() - -if (DEFINED CONFIG_MCHP_MEC_UNSIGNED_HEADER) - set(MCHP_MEC_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.mchp.bin) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/spigen/mec_spi_gen.py - -i ${KERNEL_BIN_NAME} - -o ${MCHP_MEC_BIN_NAME} - -c ${CONFIG_MCHP_MEC_HEADER_CHIP} - -s ${CONFIG_MCHP_MEC_HEADER_FLASH_SIZE} - -f ${CONFIG_MCHP_MEC_HEADER_SPI_FREQ_MHZ} - -r ${CONFIG_MCHP_MEC_HEADER_SPI_READ_MODE} - -m ${CONFIG_MCHP_MEC_HEADER_FLASH_SPI_MODE} - --drvstr ${CONFIG_MCHP_MEC_HEADER_SPI_DRVSTR} - --slewrate ${CONFIG_MCHP_MEC_HEADER_SPI_SLEW_RATE} - ${MCHP_HEADER_VERBOSE_OPTION} - ) -endif() diff --git a/soc/arm/microchip_mec/mec1501/CMakeLists.txt b/soc/arm/microchip_mec/mec1501/CMakeLists.txt deleted file mode 100644 index e92250a6989..00000000000 --- a/soc/arm/microchip_mec/mec1501/CMakeLists.txt +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (c) 2019, Microchip Technology Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - device_power.c - power.c - ) - -if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) - if(CONFIG_TIMING_FUNCTIONS) - # Use MEC15xx timing calculations only if DWT is not present - if(NOT CONFIG_CORTEX_M_DWT) - zephyr_library_sources(timing.c) - endif() - endif() -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/microchip_mec/mec1501/Kconfig.defconfig.series b/soc/arm/microchip_mec/mec1501/Kconfig.defconfig.series deleted file mode 100644 index bb0f205afca..00000000000 --- a/soc/arm/microchip_mec/mec1501/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Microchip MEC MCU series configuration options - -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MEC1501X - -config SOC_SERIES - default "mec1501" - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts - # All NVIC external sources. - default 174 - -source "soc/arm/microchip_mec/mec1501/Kconfig.defconfig.mec1501*" - -if RTOS_TIMER - -config SOC_HAS_TIMING_FUNCTIONS - default y if !CORTEX_M_DWT - -config ARCH_HAS_CUSTOM_BUSY_WAIT - default y - -endif # RTOS_TIMER - -config CORTEX_M_SYSTICK - depends on !RTOS_TIMER - -endif # SOC_SERIES_MEC1501X diff --git a/soc/arm/microchip_mec/mec1501/Kconfig.series b/soc/arm/microchip_mec/mec1501/Kconfig.series deleted file mode 100644 index 92dc6f3f8f9..00000000000 --- a/soc/arm/microchip_mec/mec1501/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Microchip MEC1501 MCU core series - -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MEC1501X - bool "Microchip MEC1501X Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select SOC_FAMILY_MEC - select HAS_PM - help - Enable support for Microchip MEC Cortex-M4 MCU series diff --git a/soc/arm/microchip_mec/mec1501/Kconfig.soc b/soc/arm/microchip_mec/mec1501/Kconfig.soc deleted file mode 100644 index 51db7329f98..00000000000 --- a/soc/arm/microchip_mec/mec1501/Kconfig.soc +++ /dev/null @@ -1,97 +0,0 @@ -# Microchip MEC1501 MCU core series - -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "MEC1501 Selection" - depends on SOC_SERIES_MEC1501X - -config SOC_MEC1501_HSZ - bool "MEC1501_HSZ" - select HAS_MEC_HAL - -endchoice - -config RTOS_TIMER - bool "MEC1501 RTOS timer" - -config SOC_MEC1501_PROC_CLK_DIV - int "PROC_CLK_DIV" - default 1 - range 1 48 - help - This divisor defines a ratio between processor clock (HCLK) - and master clock (MCK): - HCLK = MCK / PROC_CLK_DIV - Allowed divider values: 1, 3, 4, 16, and 48. - -config SOC_MEC1501_VTR3_1_8V - bool "VTR3 power rail is tied to 1.8V" - help - Set this is if VTR3 power sourcejumper in the board is changed. - -config SOC_MEC1501_VCI_PINS_AS_GPIOS - bool "Use VCI block pins as GPIOS" - default y - help - By default these pins are not GPIOs, but HW controlled. - Set this if VCI pin block HW logic is not required in the board - design. - -choice - prompt "MEC1501 debug interface general configuration" - default SOC_MEC1501_DEBUG_WITHOUT_TRACING - depends on SOC_SERIES_MEC1501X - help - Select Debug SoC interface support for MEC15xx SoC family - - config SOC_MEC1501_DEBUG_DISABLED - bool "Disable debug support" - help - Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST# - pin is ignored. All other JTAG pins can be used as GPIOs - or other non-JTAG alternate functions. - - config SOC_MEC1501_DEBUG_WITHOUT_TRACING - bool "Debug support via Serial wire debug" - help - JTAG port in SWD mode. UART2 and ADC00-03 can be used. - - config SOC_MEC1501_DEBUG_AND_TRACING - bool "Debug support via Serial wire debug with tracing enabled" - help - JTAG port is enabled in SWD mode. Refer to tracing options - to see if ADC00-03 can be used or not. - -endchoice - -choice - prompt "MEC1501 debug interface trace configuration" - default SOC_MEC1501_DEBUG_AND_ETM_TRACING - depends on SOC_MEC1501_DEBUG_AND_TRACING - help - Select tracing mode for debug interface - - config SOC_MEC1501_DEBUG_AND_ETM_TRACING - bool "Debug support via Serial wire debug" - help - JTAG port in SWD mode and SWV as tracing method. - UART2 can be used, but ADC00-03 cannot. - - config SOC_MEC1501_DEBUG_AND_SWV_TRACING - bool "debug support via Serial Wire Debug and Viewer" - help - JTAG port in SWD mode and SWV as tracing method. - UART2 cannot be used. ADC00-03 can be used. -endchoice - -# GPIO initialization depends on SOC initialization, which happen at -# CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, so GPIO_INIT_PRIORITY needs to be -# higher than that. -if GPIO - -config GPIO_INIT_PRIORITY - default 41 - -endif # GPIO diff --git a/soc/arm/microchip_mec/mec172x/CMakeLists.txt b/soc/arm/microchip_mec/mec172x/CMakeLists.txt deleted file mode 100644 index 59f3b5e4d2b..00000000000 --- a/soc/arm/microchip_mec/mec172x/CMakeLists.txt +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (c) 2021, Microchip Technology Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -if(CONFIG_PM) - zephyr_library_sources(power.c device_power.c) -endif() - -if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) - if(CONFIG_TIMING_FUNCTIONS) - # Use MEC172x timing calculations only if DWT is not present - if(NOT CONFIG_CORTEX_M_DWT) - zephyr_library_sources(timing.c) - endif() - endif() -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.series b/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.series deleted file mode 100644 index d23de11262d..00000000000 --- a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.series +++ /dev/null @@ -1,36 +0,0 @@ -# Microchip MEC MCU series configuration options - -# Copyright (c) 2021 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MEC172X - -config SOC_SERIES - default "mec172x" - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts - # All NVIC external sources. - default 181 - -source "soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172x*" - -if RTOS_TIMER - -config SOC_HAS_TIMING_FUNCTIONS - default y if !CORTEX_M_DWT - -config ARCH_HAS_CUSTOM_BUSY_WAIT - default y - -endif # RTOS_TIMER - -config CORTEX_M_SYSTICK - depends on !RTOS_TIMER - -config PS2_XEC - default y - depends on PS2 - -endif # SOC_SERIES_MEC172X diff --git a/soc/arm/microchip_mec/mec172x/Kconfig.series b/soc/arm/microchip_mec/mec172x/Kconfig.series deleted file mode 100644 index cb62a2bbfa9..00000000000 --- a/soc/arm/microchip_mec/mec172x/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Microchip MEC172X MCU core series - -# Copyright (c) 2021 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MEC172X - bool "Microchip MEC172X Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_MEC - select HAS_SWO - select HAS_PM - help - Enable support for Microchip MEC Cortex-M4F MCU series diff --git a/soc/arm/microchip_mec/mec172x/Kconfig.soc b/soc/arm/microchip_mec/mec172x/Kconfig.soc deleted file mode 100644 index d5f256605d0..00000000000 --- a/soc/arm/microchip_mec/mec172x/Kconfig.soc +++ /dev/null @@ -1,84 +0,0 @@ -# Microchip MEC172x MCU core series - -# Copyright (c) 2021 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "MEC172x Selection" - depends on SOC_SERIES_MEC172X - -config SOC_MEC172X_NSZ - bool "MEC172X_NSZ" -config SOC_MEC172X_NLJ - bool "MEC172X_NLJ" - -endchoice - -config RTOS_TIMER - bool "MEC172x RTOS Timer(32KHz) as kernel timer" - -config SOC_MEC172X_PROC_CLK_DIV - int "PROC_CLK_DIV" - default 1 - range 1 48 - help - This divisor defines a ratio between processor clock (HCLK) - and main 96 MHz clock (MCK): - HCLK = MCK / PROC_CLK_DIV - Allowed divider values: 1, 3, 4, 16, and 48. - -choice - prompt "MEC172x debug interface general configuration" - default SOC_MEC172X_DEBUG_WITHOUT_TRACING - depends on SOC_SERIES_MEC172X - help - Select Debug SoC interface support for MEC172X SoC family - - config SOC_MEC172X_DEBUG_DISABLED - bool "Disable debug support" - help - Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST# - pin is ignored. All other JTAG pins can be used as GPIOs - or other non-JTAG alternate functions. - - config SOC_MEC172X_DEBUG_WITHOUT_TRACING - bool "Debug support via Serial wire debug" - help - JTAG port in SWD mode. I2C09 and ADC00-03 can be used. - - config SOC_MEC172X_DEBUG_AND_TRACING - bool "Debug support via Serial wire debug with tracing enabled" - help - JTAG port is enabled in SWD mode. Refer to tracing options - to see if ADC00-03 can be used or not. -endchoice - -choice - prompt "MEC172X debug interface trace configuration" - default SOC_MEC172X_DEBUG_AND_ETM_TRACING - depends on SOC_MEC172X_DEBUG_AND_TRACING - help - Select tracing mode for debug interface - - config SOC_MEC172X_DEBUG_AND_ETM_TRACING - bool "Debug support via Serial wire debug" - help - JTAG port in SWD mode and ETM as tracing method. - I2C09 can be used, but ADC00-03 cannot. - - config SOC_MEC172X_DEBUG_AND_SWV_TRACING - bool "debug support via Serial Wire Debug and Viewer" - help - JTAG port in SWD mode and SWV as tracing method. - I2C09 cannot be used. ADC00-03 can be used. -endchoice - -# GPIO initialization depends on ECIA initialization, which happen at -# CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, so GPIO_INIT_PRIORITY needs to be -# higher than that. -if GPIO - -config GPIO_INIT_PRIORITY - default 41 - -endif # GPIO diff --git a/soc/arm/mps2/CMakeLists.txt b/soc/arm/mps2/CMakeLists.txt new file mode 100644 index 00000000000..5beaeea5684 --- /dev/null +++ b/soc/arm/mps2/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/mps2/Kconfig b/soc/arm/mps2/Kconfig new file mode 100644 index 00000000000..248be2250a2 --- /dev/null +++ b/soc/arm/mps2/Kconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2017-2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MPS2 + select ARM + select GPIO_MMIO32 if GPIO + +config SOC_MPS2_AN521 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + +config SOC_MPS2_AN385 + select CPU_CORTEX_M3 + select CPU_HAS_ARM_MPU + +config SOC_MPS2_AN521_CPU0 + select CPU_HAS_ARM_SAU + +config SOC_MPS2_AN521_CPU1 + select CPU_HAS_FPU + select ARMV8_M_DSP diff --git a/soc/arm/mps2/Kconfig.defconfig b/soc/arm/mps2/Kconfig.defconfig new file mode 100644 index 00000000000..3804dd60709 --- /dev/null +++ b/soc/arm/mps2/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MPS2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_MPS2 diff --git a/soc/arm/mps2/Kconfig.defconfig.an385 b/soc/arm/mps2/Kconfig.defconfig.an385 new file mode 100644 index 00000000000..fbcec3977f1 --- /dev/null +++ b/soc/arm/mps2/Kconfig.defconfig.an385 @@ -0,0 +1,9 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MPS2_AN385 + +config NUM_IRQS + default 32 + +endif diff --git a/soc/arm/mps2/Kconfig.defconfig.an521 b/soc/arm/mps2/Kconfig.defconfig.an521 new file mode 100644 index 00000000000..944bdf4f067 --- /dev/null +++ b/soc/arm/mps2/Kconfig.defconfig.an521 @@ -0,0 +1,9 @@ +# Copyright (c) 2018-2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MPS2_AN521 + +config NUM_IRQS + default 96 + +endif diff --git a/soc/arm/mps2/Kconfig.soc b/soc/arm/mps2/Kconfig.soc new file mode 100644 index 00000000000..bc9fa98fdcc --- /dev/null +++ b/soc/arm/mps2/Kconfig.soc @@ -0,0 +1,37 @@ +# Copyright (c) 2017-2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MPS2 + bool + select SOC_FAMILY_ARM + help + Enable support for ARM MPS2 MCU Series + +config SOC_MPS2_AN385 + bool + select SOC_SERIES_MPS2 + help + ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385) + +config SOC_MPS2_AN521 + bool + select SOC_SERIES_MPS2 + +config SOC_MPS2_AN521_CPU0 + bool + select SOC_MPS2_AN521 + help + ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU0 + +config SOC_MPS2_AN521_CPU1 + bool + select SOC_MPS2_AN521 + help + ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU1 + +config SOC_SERIES + default "mps2" if SOC_SERIES_MPS2 + +config SOC + default "an385" if SOC_MPS2_AN385 + default "an521" if SOC_MPS2_AN521 diff --git a/soc/arm/mps2/soc.c b/soc/arm/mps2/soc.c new file mode 100644 index 00000000000..343330d4515 --- /dev/null +++ b/soc/arm/mps2/soc.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * Initial contents based on soc/soc_legacy/arm/ti_lm3s6965/soc.c which is: + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + + +/* Setup GPIO drivers for accessing FPGAIO registers */ +#define FPGAIO_NODE(n) DT_INST(n, arm_mps2_fpgaio_gpio) +#define FPGAIO_INIT(n) \ + GPIO_MMIO32_INIT(FPGAIO_NODE(n), \ + DT_REG_ADDR(FPGAIO_NODE(n)), \ + BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios))) + +/* We expect there to be 3 arm,mps2-fpgaio-gpio devices: + * led0, button, and misc + */ +FPGAIO_INIT(0); +FPGAIO_INIT(1); +FPGAIO_INIT(2); + +/* (Secure System Control) Base Address */ +#define SSE_200_SYSTEM_CTRL_S_BASE (0x50021000UL) +#define SSE_200_SYSTEM_CTRL_INITSVTOR1 (SSE_200_SYSTEM_CTRL_S_BASE + 0x114) +#define SSE_200_SYSTEM_CTRL_CPU_WAIT (SSE_200_SYSTEM_CTRL_S_BASE + 0x118) +#define SSE_200_CPU_ID_UNIT_BASE (0x5001F000UL) + +/* The base address that the application image will start at on the secondary + * (non-TrustZone) Cortex-M33 mcu. + */ +#define CPU1_FLASH_ADDRESS (0x38B000) + +/* The memory map offset for the application image, which is used + * to determine the location of the reset vector at startup. + */ +#define CPU1_FLASH_OFFSET (0x10000000) + +/** + * @brief Wake up CPU 1 from another CPU, this is platform specific. + */ +void wakeup_cpu1(void) +{ + /* Set the Initial Secure Reset Vector Register for CPU 1 */ + *(uint32_t *)(SSE_200_SYSTEM_CTRL_INITSVTOR1) = + (uint32_t)_vector_start + + CPU1_FLASH_ADDRESS - + CPU1_FLASH_OFFSET; + + /* Set the CPU Boot wait control after reset */ + *(uint32_t *)(SSE_200_SYSTEM_CTRL_CPU_WAIT) = 0; +} + +/** + * @brief Get the current CPU ID, this is platform specific. + * + * @return Current CPU ID + */ +uint32_t sse_200_platform_get_cpu_id(void) +{ + volatile uint32_t *p_cpu_id = (volatile uint32_t *)SSE_200_CPU_ID_UNIT_BASE; + + return (uint32_t)*p_cpu_id; +} diff --git a/soc/arm/arm/mps2/soc.h b/soc/arm/mps2/soc.h similarity index 100% rename from soc/arm/arm/mps2/soc.h rename to soc/arm/mps2/soc.h diff --git a/soc/arm/arm/mps2/soc_registers.h b/soc/arm/mps2/soc_registers.h similarity index 100% rename from soc/arm/arm/mps2/soc_registers.h rename to soc/arm/mps2/soc_registers.h diff --git a/soc/arm/mps3/CMakeLists.txt b/soc/arm/mps3/CMakeLists.txt new file mode 100644 index 00000000000..3cf33caa58d --- /dev/null +++ b/soc/arm/mps3/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/mps3/Kconfig b/soc/arm/mps3/Kconfig new file mode 100644 index 00000000000..06c1af46d5d --- /dev/null +++ b/soc/arm/mps3/Kconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2017-2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MPS3 + select ARM + select GPIO_MMIO32 if GPIO + +config SOC_MPS3_AN547 + select CPU_CORTEX_M55 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARMV8_1_M_MVEI + select ARMV8_1_M_MVEF + select ARMV8_1_M_PMU + +config ARMV8_1_M_PMU_EVENTCNT + int + default 8 if SOC_MPS3_AN547 diff --git a/soc/arm/mps3/Kconfig.defconfig b/soc/arm/mps3/Kconfig.defconfig new file mode 100644 index 00000000000..449b87d33a1 --- /dev/null +++ b/soc/arm/mps3/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MPS3 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 + +rsource "Kconfig.defconfig.mps3*" + +endif # SOC_SERIES_MPS3 diff --git a/soc/arm/arm/mps3/Kconfig.defconfig.mps3_an547 b/soc/arm/mps3/Kconfig.defconfig.mps3_an547 similarity index 79% rename from soc/arm/arm/mps3/Kconfig.defconfig.mps3_an547 rename to soc/arm/mps3/Kconfig.defconfig.mps3_an547 index 870bbb46c0b..0961808eae2 100644 --- a/soc/arm/arm/mps3/Kconfig.defconfig.mps3_an547 +++ b/soc/arm/mps3/Kconfig.defconfig.mps3_an547 @@ -3,9 +3,6 @@ if SOC_MPS3_AN547 -config SOC - default "mps3_an547" - config NUM_IRQS default 128 diff --git a/soc/arm/mps3/Kconfig.soc b/soc/arm/mps3/Kconfig.soc new file mode 100644 index 00000000000..99bb1fb78c4 --- /dev/null +++ b/soc/arm/mps3/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2017-2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MPS3 + bool + select SOC_FAMILY_ARM + help + Enable support for ARM MPS3 MCU Series + +config SOC_SERIES + default "mps3" if SOC_SERIES_MPS3 + +config SOC_MPS3_AN547 + bool + select SOC_SERIES_MPS3 + +config SOC + default "an547" if SOC_MPS3_AN547 diff --git a/soc/arm/arm/mps3/soc.c b/soc/arm/mps3/soc.c similarity index 100% rename from soc/arm/arm/mps3/soc.c rename to soc/arm/mps3/soc.c diff --git a/soc/arm/arm/mps3/soc.h b/soc/arm/mps3/soc.h similarity index 100% rename from soc/arm/arm/mps3/soc.h rename to soc/arm/mps3/soc.h diff --git a/soc/arm/musca/CMakeLists.txt b/soc/arm/musca/CMakeLists.txt new file mode 100644 index 00000000000..988efa18758 --- /dev/null +++ b/soc/arm/musca/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_V2M_MUSCA_B1) + zephyr_sources(b1/soc.c) + zephyr_include_directories(b1) +elseif(CONFIG_SOC_V2M_MUSCA_S1) + zephyr_include_directories(s1) +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/musca/Kconfig b/soc/arm/musca/Kconfig new file mode 100644 index 00000000000..83abe182c1e --- /dev/null +++ b/soc/arm/musca/Kconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MUSCA + select ARM + select BUILD_OUTPUT_HEX + +config SOC_V2M_MUSCA_B1 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_DWT + +config SOC_V2M_MUSCA_S1 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select ARMV8_M_DSP diff --git a/soc/arm/musca/Kconfig.defconfig b/soc/arm/musca/Kconfig.defconfig new file mode 100644 index 00000000000..8f457d9d50b --- /dev/null +++ b/soc/arm/musca/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 40000000 if SOC_V2M_MUSCA_B1 + default 50000000 if SOC_V2M_MUSCA_S1 + +config NUM_IRQS + default 96 if SOC_SERIES_MUSCA diff --git a/soc/arm/musca/Kconfig.soc b/soc/arm/musca/Kconfig.soc new file mode 100644 index 00000000000..3c81f3d5713 --- /dev/null +++ b/soc/arm/musca/Kconfig.soc @@ -0,0 +1,27 @@ +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MUSCA + bool + select SOC_FAMILY_ARM + help + ARM v2m MUSCA MCU Series + +config SOC_V2M_MUSCA_B1 + bool + select SOC_SERIES_MUSCA + help + ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-B1 + +config SOC_V2M_MUSCA_S1 + bool + select SOC_SERIES_MUSCA + help + ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-S1 + +config SOC_SERIES + default "musca" if SOC_SERIES_MUSCA + +config SOC + default "musca_b1" if SOC_V2M_MUSCA_B1 + default "musca_s1" if SOC_V2M_MUSCA_S1 diff --git a/soc/arm/arm/musca_b1/soc.c b/soc/arm/musca/b1/soc.c similarity index 100% rename from soc/arm/arm/musca_b1/soc.c rename to soc/arm/musca/b1/soc.c diff --git a/soc/arm/arm/musca_b1/soc.h b/soc/arm/musca/b1/soc.h similarity index 100% rename from soc/arm/arm/musca_b1/soc.h rename to soc/arm/musca/b1/soc.h diff --git a/soc/arm/arm/musca_b1/system_cmsdk_musca_b1.h b/soc/arm/musca/b1/system_cmsdk_musca_b1.h similarity index 100% rename from soc/arm/arm/musca_b1/system_cmsdk_musca_b1.h rename to soc/arm/musca/b1/system_cmsdk_musca_b1.h diff --git a/soc/arm/arm/musca_s1/soc.h b/soc/arm/musca/s1/soc.h similarity index 100% rename from soc/arm/arm/musca_s1/soc.h rename to soc/arm/musca/s1/soc.h diff --git a/soc/arm/arm/musca_s1/system_cmsdk_musca_s1.h b/soc/arm/musca/s1/system_cmsdk_musca_s1.h similarity index 100% rename from soc/arm/arm/musca_s1/system_cmsdk_musca_s1.h rename to soc/arm/musca/s1/system_cmsdk_musca_s1.h diff --git a/soc/arm/nordic_nrf/CMakeLists.txt b/soc/arm/nordic_nrf/CMakeLists.txt deleted file mode 100644 index bd7725404b8..00000000000 --- a/soc/arm/nordic_nrf/CMakeLists.txt +++ /dev/null @@ -1,34 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -add_subdirectory(${SOC_SERIES}) -add_subdirectory(common) - -zephyr_library_sources( - validate_base_addresses.c - validate_enabled_instances.c - ) - -if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) - if(CONFIG_TIMING_FUNCTIONS) - # Use nRF-specific timing calculations only if DWT is not present - if(NOT CONFIG_CORTEX_M_DWT) - zephyr_library_sources(timing.c) - endif() - endif() -endif() - -if(CONFIG_BUILD_WITH_TFM) - set_property(TARGET zephyr_property_target - APPEND PROPERTY TFM_CMAKE_OPTIONS -DHAL_NORDIC_PATH=${ZEPHYR_HAL_NORDIC_MODULE_DIR} - ) - - set_property(TARGET zephyr_property_target - APPEND PROPERTY TFM_CMAKE_OPTIONS -DZEPHYR_BASE=${ZEPHYR_BASE} - ) - - set_property(TARGET zephyr_property_target - APPEND PROPERTY TFM_CMAKE_OPTIONS -DNRF_NS_STORAGE=${CONFIG_TFM_NRF_NS_STORAGE} - ) -endif() diff --git a/soc/arm/nordic_nrf/Kconfig b/soc/arm/nordic_nrf/Kconfig deleted file mode 100644 index b2d164e7c78..00000000000 --- a/soc/arm/nordic_nrf/Kconfig +++ /dev/null @@ -1,175 +0,0 @@ -# Nordic Semiconductor nRFx MCU line - -# Copyright (c) 2016-2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_NRF - select SOC_COMPATIBLE_NRF - select PLATFORM_SPECIFIC_INIT - bool - -if SOC_FAMILY_NRF -config SOC_FAMILY - string - default "nordic_nrf" - -source "soc/common/nordic_nrf/Kconfig.peripherals" -source "soc/arm/nordic_nrf/*/Kconfig.soc" - -config NRF_SOC_SECURE_SUPPORTED - def_bool !TRUSTED_EXECUTION_NONSECURE || (BUILD_WITH_TFM && TFM_PARTITION_PLATFORM) - depends on !SOC_SERIES_NRF54HX - help - Hidden function to indicate that that the soc_secure functions are - available. - The functions are always available when not in non-secure. - For non-secure the functions must redirect to secure services exposed - by the secure firmware. - -config BUILD_WITH_TFM - default y if TRUSTED_EXECUTION_NONSECURE - help - By default, if we build for a Non-Secure version of the board, - enable building with TF-M as the Secure Execution Environment. - -if BUILD_WITH_TFM - -config TFM_FLASH_MERGED_BINARY - default y - help - By default, if we build with TF-M, instruct build system to - flash the combined TF-M (Secure) & Zephyr (Non Secure) image - -config TFM_LOG_LEVEL_SILENCE - default y if !$(dt_nodelabel_has_prop,uart1,pinctrl-names) - help - Disable TF-M secure output if the uart1 node has not assigned GPIO - pins using pinctrl. - -config TFM_NRF_NS_STORAGE - bool "TF-M non-secure storage partition" - default y - -endif # BUILD_WITH_TFM - - -config NRF_MPU_FLASH_REGION_SIZE - hex - default 0x1000 - depends on HAS_HW_NRF_MPU - help - FLASH region size for the NRF_MPU peripheral. - -config NRF_BPROT_FLASH_REGION_SIZE - hex - default $(dt_node_int_prop_hex,$(DT_CHOSEN_ZEPHYR_FLASH),erase-block-size) - depends on HAS_HW_NRF_BPROT - help - FLASH region size for the NRF_BPROT peripheral (nRF52). - -config NRF_ACL_FLASH_REGION_SIZE - hex - default $(dt_node_int_prop_hex,$(DT_CHOSEN_ZEPHYR_FLASH),erase-block-size) - depends on HAS_HW_NRF_ACL - help - FLASH region size for the NRF_ACL peripheral. - -config NFCT_PINS_AS_GPIOS - bool "[DEPRECATED] NFCT pins as GPIOs" - depends on $(dt_has_compat,$(DT_COMPAT_NORDIC_NRF_NFCT)) - select DEPRECATED - help - Two pins are usually reserved for NFC in SoCs that implement the - NFCT peripheral. This option switches them to normal GPIO mode. - HW enabling happens once in the device lifetime, during the first - system startup. Disabling this option will not switch back these - pins to NFCT mode. Doing this requires UICR erase prior to - flashing device using the image which has this option disabled. - - NFC pins in nRF52 series: P0.09 and P0.10 - NFC pins in nRF5340: P0.02 and P0.03 - - This option is deprecated, please use devicetree to configure NFCT - pins as GPIOS like this: - - &uicr { - nfct-pins-as-gpios; - }; - -choice NRF_APPROTECT_HANDLING - bool "APPROTECT handling" - depends on SOC_SERIES_NRF52X || SOC_NRF5340_CPUNET || \ - (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) || \ - SOC_SERIES_NRF91X - default NRF_APPROTECT_USE_UICR - help - Specifies how the SystemInit() function should handle the APPROTECT - mechanism. - -config NRF_APPROTECT_USE_UICR - bool "Use UICR" - help - When this option is selected, the SystemInit() function loads the - firmware branch state of the APPROTECT mechanism from UICR, so if - UICR->APPROTECT is disabled, CTRLAP->APPROTECT will be disabled. - -config NRF_APPROTECT_LOCK - bool "Lock" - help - When this option is selected, the SystemInit() function locks - the firmware branch of the APPROTECT mechanism, preventing it - from being opened. - -config NRF_APPROTECT_USER_HANDLING - bool "Allow user handling" - depends on !SOC_SERIES_NRF52X - help - When this option is selected, the SystemInit() function does not - touch the APPROTECT mechanism, allowing the user code to handle it - at later stages, for example, to implement authenticated debug. - -endchoice - -choice NRF_SECURE_APPROTECT_HANDLING - bool "Secure APPROTECT handling" - depends on (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) - default NRF_SECURE_APPROTECT_USE_UICR - help - Specifies how the SystemInit() function should handle the secure - APPROTECT mechanism. - -config NRF_SECURE_APPROTECT_USE_UICR - bool "Use UICR" - help - When this option is selected, the SystemInit() function loads the - firmware branch state of the secure APPROTECT mechanism from UICR, - so if UICR->SECUREAPPROTECT is disabled, CTRLAP->SECUREAPPROTECT - will be disabled. - -config NRF_SECURE_APPROTECT_LOCK - bool "Lock" - help - When this option is selected, the SystemInit() function locks the - firmware branch of the secure APPROTECT mechanism, preventing it - from being opened. - -config NRF_SECURE_APPROTECT_USER_HANDLING - bool "Allow user handling" - depends on !SOC_SERIES_NRF52X - help - When this option is selected, the SystemInit() function does not - touch the secure APPROTECT mechanism, allowing the user code to - handle it at later stages, for example, to implement authenticated - debug. - -endchoice - -config NRF_TRACE_PORT - bool "nRF TPIU" - depends on !SOC_SERIES_NRF51X - help - Enable this option to initialize the TPIU (Trace Port Interface - Unit) for tracing using a hardware probe. If disabled, the trace - pins will be used as GPIO. - -endif # SOC_FAMILY_NRF diff --git a/soc/arm/nordic_nrf/Kconfig.defconfig b/soc/arm/nordic_nrf/Kconfig.defconfig deleted file mode 100644 index ad3c97443ff..00000000000 --- a/soc/arm/nordic_nrf/Kconfig.defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# Nordic Semiconductor nRFx MCU line - -# Copyright (c) 2016-2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_NRF - -source "soc/arm/nordic_nrf/*/Kconfig.defconfig.series" - -# If the kernel has timer support, enable clock control -if SYS_CLOCK_EXISTS - -config CLOCK_CONTROL - default y if !SOC_SERIES_NRF54HX - -endif # SYS_CLOCK_EXISTS - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 if NRF_GRTC_TIMER - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 128 if !TICKLESS_KERNEL - default 10000 if NRF_GRTC_TIMER - default 32768 - -config ARCH_HAS_CUSTOM_BUSY_WAIT - default y if !QEMU_TARGET - -config BUILD_OUTPUT_HEX - default y - -if !CORTEX_M_DWT && NRF_RTC_TIMER -config SOC_HAS_TIMING_FUNCTIONS - default y -endif - -config GPIO - default y - depends on SPI - -config UART_USE_RUNTIME_CONFIGURE - default n - -endif # SOC_FAMILY_NRF diff --git a/soc/arm/nordic_nrf/Kconfig.soc b/soc/arm/nordic_nrf/Kconfig.soc deleted file mode 100644 index 1eda7294674..00000000000 --- a/soc/arm/nordic_nrf/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Nordic Semiconductor nRFx MCU line - -# Copyright (c) 2016-2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nordic_nrf/*/Kconfig.series" diff --git a/soc/arm/nordic_nrf/common/CMakeLists.txt b/soc/arm/nordic_nrf/common/CMakeLists.txt deleted file mode 100644 index ea05f3d369e..00000000000 --- a/soc/arm/nordic_nrf/common/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_NRF soc_nrf_common.S) -zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -zephyr_include_directories(.) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") - -if (CONFIG_TFM_PARTITION_PLATFORM) - zephyr_library_sources(soc_secure.c) - zephyr_library_include_directories( - $/api_ns/interface/include - ) -endif() diff --git a/soc/arm/nordic_nrf/nrf51/CMakeLists.txt b/soc/arm/nordic_nrf/nrf51/CMakeLists.txt deleted file mode 100644 index 35d47fb252b..00000000000 --- a/soc/arm/nordic_nrf/nrf51/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(soc.c) diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAA b/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAA deleted file mode 100644 index ada60bd28f4..00000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAA +++ /dev/null @@ -1,9 +0,0 @@ -# Nordic Semiconductor nRF51822 MCU - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "nRF51822_QFAA" - depends on SOC_NRF51822_QFAA diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAB b/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAB deleted file mode 100644 index a1027b4cfd8..00000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAB +++ /dev/null @@ -1,9 +0,0 @@ -# Nordic Semiconductor nRF51822 MCU - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "nRF51822_QFAB" - depends on SOC_NRF51822_QFAB diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAC b/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAC deleted file mode 100644 index 7f92c991dec..00000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAC +++ /dev/null @@ -1,9 +0,0 @@ -# Nordic Semiconductor nRF51822 MCU - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "nRF51822_QFAC" - depends on SOC_NRF51822_QFAC diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.series deleted file mode 100644 index a4053bf7fed..00000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Nordic Semiconductor nRF51 MCU line - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF51X - -source "soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51*" - -config SOC_SERIES - default "nrf51" - -config NUM_IRQS - default 26 - -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - -endif # SOC_SERIES_NRF51X diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.series b/soc/arm/nordic_nrf/nrf51/Kconfig.series deleted file mode 100644 index c484d44fc30..00000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF51 MCU line - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF51X - bool "Nordic Semiconductor nRF51 series MCU" - select ARM - select CPU_CORTEX_M0 - select SOC_FAMILY_NRF - imply XIP - select HAS_NRFX - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_POWEROFF - help - Enable support for NRF51 MCU series diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.soc b/soc/arm/nordic_nrf/nrf51/Kconfig.soc deleted file mode 100644 index aa42e2a729a..00000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Nordic Semiconductor nRF51 MCU line - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "nRF51x MCU Selection" - depends on SOC_SERIES_NRF51X - -config SOC_NRF51822_QFAA - bool "NRF51822_QFAA" - -config SOC_NRF51822_QFAB - bool "NRF51822_QFAB" - -config SOC_NRF51822_QFAC - bool "NRF51822_QFAC" - -endchoice diff --git a/soc/arm/nordic_nrf/nrf52/CMakeLists.txt b/soc/arm/nordic_nrf/nrf52/CMakeLists.txt deleted file mode 100644 index 1b7d4d5257a..00000000000 --- a/soc/arm/nordic_nrf/nrf52/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(soc.c) - -if(CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 AND CONFIG_SPI_NRFX_SPIM) - message(WARNING "Both SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 and an NRF SPIM driver are enabled, therefore PAN 58 will apply if RXD.MAXCNT == 1 and TXD.MAXCNT <= 1") -endif() - -if(CONFIG_SOC_NRF52832) - if(NOT CONFIG_NRF52_ANOMALY_109_WORKAROUND) - if (CONFIG_NRFX_SPIS OR CONFIG_NRFX_SPIM OR CONFIG_NRFX_TWIM OR CONFIG_NRFX_PWM) - message(WARNING "NRF52_ANOMALY_109_WORKAROUND disabled with SPIS, SPIM, TWIM or PWM enabled. This will occasionally cause the first byte transmitted to be incorrect") - endif() - endif() -endif() diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.series deleted file mode 100644 index 2e89a5130a6..00000000000 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF52 MCU line - -# Copyright (c) 2016-2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF52X - -source "soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52*" - -config SOC_SERIES - default "nrf52" - -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - -endif # SOC_SERIES_NRF52X diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.series b/soc/arm/nordic_nrf/nrf52/Kconfig.series deleted file mode 100644 index d47089cd595..00000000000 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# Nordic Semiconductor nRF52 MCU line - -# Copyright (c) 2016-2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF52X - bool "Nordic Semiconductor nRF52 series MCU" - select ARM - select SOC_COMPATIBLE_NRF52X - select CPU_CORTEX_M4 - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NRF - imply XIP - select HAS_NRFX - select HAS_NORDIC_DRIVERS - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_SWO - select HAS_POWEROFF - help - Enable support for NRF52 MCU series diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.soc b/soc/arm/nordic_nrf/nrf52/Kconfig.soc deleted file mode 100644 index de6a16129d3..00000000000 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.soc +++ /dev/null @@ -1,158 +0,0 @@ -# Nordic Semiconductor nRF52 MCU line - -# Copyright (c) 2016-2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF52X - -config SOC_NRF52805 - bool - -config SOC_NRF52810 - bool - -config SOC_NRF52811 - bool - -config SOC_NRF52820 - bool - -config SOC_NRF52832 - bool - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - -config SOC_NRF52833 - bool - select SOC_COMPATIBLE_NRF52833 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - -config SOC_NRF52840 - bool - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - -choice - prompt "nRF52x MCU Selection" - -config SOC_NRF52805_CAAA - bool "NRF52805_CAAA" - select SOC_NRF52805 - -config SOC_NRF52810_QFAA - bool "NRF52810_QFAA" - select SOC_NRF52810 - -config SOC_NRF52811_QFAA - bool "NRF52811_QFAA" - select SOC_NRF52811 - -config SOC_NRF52820_QDAA - bool "NRF52820_QDAA" - select SOC_NRF52820 - -config SOC_NRF52832_CIAA - bool "NRF52832_CIAA" - select SOC_NRF52832 - -config SOC_NRF52832_QFAA - bool "NRF52832_QFAA" - select SOC_NRF52832 - -config SOC_NRF52832_QFAB - bool "NRF52832_QFAB" - select SOC_NRF52832 - -config SOC_NRF52833_QDAA - bool "NRF52833_QDAA" - select SOC_NRF52833 - -config SOC_NRF52833_QIAA - bool "NRF52833_QIAA" - select SOC_NRF52833 - -config SOC_NRF52840_QFAA - bool "NRF52840_QFAA" - select SOC_NRF52840 - -config SOC_NRF52840_QIAA - bool "NRF52840_QIAA" - select SOC_NRF52840 - -endchoice - -config SOC_DCDC_NRF52X - bool - help - Enable nRF52 series System on Chip DC/DC converter. - -config SOC_DCDC_NRF52X_HV - bool - depends on SOC_NRF52840_QIAA - help - Enable nRF52 series System on Chip High Voltage DC/DC converter. - -config GPIO_AS_PINRESET - bool "[DEPRECATED] GPIO as pin reset (reset button)" - select DEPRECATED - help - This option is deprecated, use devicetree instead. Example - configuration: - - &uicr { - gpio-as-nreset; - }; - -config NRF_ENABLE_ICACHE - bool "The instruction cache (I-Cache)" - depends on SOC_NRF52832 || SOC_NRF52833 || SOC_NRF52840 - default y - -config NRF52_ANOMALY_132_DELAY_US - int "Anomaly 132 workaround delay (microseconds)" - default 330 - range 0 330 - depends on NRF52_ANOMALY_132_WORKAROUND - help - Due to Anomaly 132 LF RC source may not start if restarted in certain - window after stopping (230 us to 330 us). Software reset also stops the - clock so if clock is initiated in certain window, the clock may also fail - to start at reboot. A delay is added before starting LF clock to ensure - that anomaly conditions are not met. Delay should be long enough to ensure - that clock is started later than 330 us after reset. If crystal oscillator - (XO) is used then low frequency clock initially starts with RC and then - seamlessly switches to XO which has much longer startup time thus, - depending on application, workaround may also need to be applied. - Additional drivers initialization increases initialization time and delay - may be shortened. Workaround is disabled by setting delay to 0. - -config NRF52_ANOMALY_198_WORKAROUND - bool "Anomaly 198 workaround" - default y - depends on SOC_NRF52840 - depends on NRFX_SPIM3 - help - This anomaly applies to IC revisions "Engineering B" up to "3", the most - recent one. - -config NRF52_ANOMALY_109_WORKAROUND - bool "Anomaly 109 workaround" - default y - depends on SOC_NRF52832 - depends on NRFX_SPIS || NRFX_SPIM || NRFX_TWIM || NRFX_PWM - help - Due to Anomaly 109 the first byte sent out by these peripherals is - sometimes wrong. This occurs when the system enters IDLE and stops the - 64MHz clock at the same time as the peripheral that is using DMA is started. - This anomaly applies to IC revisions up to "3", the most recent one. - -config NRF52_ANOMALY_109_WORKAROUND_EGU_INSTANCE - int "Anomaly 109 workaround EGU instance" - depends on NRF52_ANOMALY_109_WORKAROUND - range 0 5 - default 5 - help - EGU instance used by the nRF52 Anomaly 109 workaround for PWM. - -endif # SOC_SERIES_NRF52X diff --git a/soc/arm/nordic_nrf/nrf53/CMakeLists.txt b/soc/arm/nordic_nrf/nrf53/CMakeLists.txt deleted file mode 100644 index be275df68f5..00000000000 --- a/soc/arm/nordic_nrf/nrf53/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(soc.c) - -zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC sync_rtc.c) - -if (CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED AND - NOT CONFIG_SYS_CLOCK_EXISTS) - message(WARNING " - Your application may be affected by the anomaly 160 that concerns the - nRF5340 SoC. The related workaround cannot be applied, because your - application has the system clock disabled (CONFIG_SYS_CLOCK_EXISTS=n). - Consider enabling the system clock to apply the workaround. - " " - At your own risk, you can suppress this warning by setting - CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED=n.") -endif() diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.series deleted file mode 100644 index 7e5660cf514..00000000000 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF53 MCU line - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF53X - -source "soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf53*" - -config SOC_SERIES - default "nrf53" - -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - -endif # SOC_SERIES_NRF53X diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.series b/soc/arm/nordic_nrf/nrf53/Kconfig.series deleted file mode 100644 index 28d1c10fc1e..00000000000 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# Nordic Semiconductor nRF53 MCU line - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF53X - bool "Nordic Semiconductor nRF53 series MCU" - select ARM - select SOC_COMPATIBLE_NRF53X - select CPU_CORTEX_M33 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NRF - imply XIP - select HAS_NRFX - select HAS_NORDIC_DRIVERS - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_SWO - help - Enable support for NRF53 MCU series diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.soc b/soc/arm/nordic_nrf/nrf53/Kconfig.soc deleted file mode 100644 index 3ecf09ecd92..00000000000 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.soc +++ /dev/null @@ -1,225 +0,0 @@ -# Nordic Semiconductor nRF53 MCU line - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF53X -config SOC_NRF5340_CPUAPP - bool - select CPU_HAS_NRF_IDAU - select CPU_HAS_FPU - select ARMV8_M_DSP - select HAS_POWEROFF - select SOC_COMPATIBLE_NRF5340_CPUAPP - imply SOC_NRF53_RTC_PRETICK - imply SOC_NRF53_ANOMALY_168_WORKAROUND - -config SOC_NRF5340_CPUNET - bool - select SOC_COMPATIBLE_NRF5340_CPUNET - imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED - imply SOC_NRF53_RTC_PRETICK if !WDT_NRFX - imply SOC_NRF53_ANOMALY_168_WORKAROUND - -choice - prompt "nRF53x MCU Selection" - -config SOC_NRF5340_CPUAPP_QKAA - bool "NRF5340_CPUAPP_QKAA" - select SOC_NRF5340_CPUAPP - -config SOC_NRF5340_CPUNET_QKAA - bool "NRF5340_CPUNET_QKAA" - select SOC_NRF5340_CPUNET - -endchoice - -config SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED - bool "Workaround for nRF5340 anomaly 160" - imply SOC_NRF53_ANOMALY_160_WORKAROUND - help - Indicates that the workaround for the anomaly 160 that affects - the nRF5340 SoC should be applied. - This option is enabled by default for the Application MCU when - DC/DC mode is enabled for the VREGMAIN or VREGRADIO regulator - and always for the Network MCU. - If this option is enabled, but the workaround cannot be applied, - because the system clock is disabled, a related cmake warning is - issued. - -config SOC_NRF53_ANOMALY_160_WORKAROUND - bool - depends on SYS_CLOCK_EXISTS - select ARM_ON_ENTER_CPU_IDLE_HOOK - -config SOC_NRF53_RTC_PRETICK - bool "Pre-tick workaround for nRF5340 anomaly 165" - depends on (SYS_CLOCK_EXISTS && SOC_NRF5340_CPUNET) || SOC_NRF5340_CPUAPP - select NRFX_DPPI - select ARM_ON_ENTER_CPU_IDLE_HOOK if SOC_NRF5340_CPUNET - select ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK if SOC_NRF5340_CPUNET - help - Indicates that the pre-tick workaround for the anomaly 165 that affects - the nRF5340 SoC should be applied. The workaround applies to wake ups caused - by EVENTS_COMPARE and EVENTS_OVRFLW on RTC0 and RTC1 for which interrupts are - enabled through INTENSET register. The case when these events are generated - by EVTEN but without interrupts enabled through INTENSET is not handled. - The EVENTS_TICK event is not handled. - -if SOC_NRF53_RTC_PRETICK - -config SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET - int "IPC 0 channel for RTC pretick" - range 0 15 - default 10 - -config SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET - int "IPC 1 channel for RTC pretick" - range 0 15 - default 11 - -endif - -config SOC_NRF53_ANOMALY_168_WORKAROUND - bool "Workaround for nRF5340 anomaly 168" - select ARM_ON_EXIT_CPU_IDLE - help - Indicates that the workaround for the anomaly 168 that affects - the nRF5340 SoC should be applied. - The workaround involves execution of 8 NOP instructions when the CPU - exist its idle state (when the WFI/WFE instruction returns) and it is - enabled by default for both the application and network core. - -config SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM - bool "Extend the workaround to execution at 128 MHz from RAM" - depends on SOC_NRF53_ANOMALY_168_WORKAROUND && SOC_NRF5340_CPUAPP - help - Indicates that the anomaly 168 workaround is to be extended to cover - also a specific case when the WFI/WFE instruction is executed at 128 - MHz from RAM. Then, 26 instead of 8 NOP instructions needs to be - executed after WFI/WFE. This extension is not enabled by default. - -if SOC_NRF5340_CPUAPP - -config SOC_DCDC_NRF53X_APP - bool - imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED - help - Enable nRF53 series System on Chip Application MCU DC/DC converter. - -config SOC_DCDC_NRF53X_NET - bool - imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED - help - Enable nRF53 series System on Chip Network MCU DC/DC converter. - -config SOC_DCDC_NRF53X_HV - bool - help - Enable nRF53 series System on Chip High Voltage DC/DC converter. - -config NRF_SPU_FLASH_REGION_SIZE - hex - default 0x4000 - help - FLASH region size for the NRF_SPU peripheral - -config NRF_SPU_RAM_REGION_SIZE - hex - default 0x2000 - help - RAM region size for the NRF_SPU peripheral - -config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 - bool - depends on NRF_SOC_SECURE_SUPPORTED - help - hidden option for including the nRF GPIO pin forwarding - -if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM - -config SOC_ENABLE_LFXO - bool "LFXO" - default y - help - Enable the low-frequency oscillator (LFXO) functionality on XL1 and - XL2 pins. - This option must be enabled if either application or network core is - to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular - GPIOs. - -choice SOC_LFXO_LOAD_CAPACITANCE - prompt "LFXO load capacitance" - depends on SOC_ENABLE_LFXO - default SOC_LFXO_CAP_INT_7PF - -config SOC_LFXO_CAP_EXTERNAL - bool "Use external load capacitors" - -config SOC_LFXO_CAP_INT_6PF - bool "6 pF internal load capacitance" - -config SOC_LFXO_CAP_INT_7PF - bool "7 pF internal load capacitance" - -config SOC_LFXO_CAP_INT_9PF - bool "9 pF internal load capacitance" - -endchoice - -choice SOC_HFXO_LOAD_CAPACITANCE - prompt "HFXO load capacitance" - default SOC_HFXO_CAP_DEFAULT - -config SOC_HFXO_CAP_DEFAULT - bool "SoC default" - help - When this option is used, the SoC initialization routine does not - touch the XOSC32MCAPS register value, so the default setting for - the SoC is in effect. Please note that this may not necessarily be - the reset value (0) for the register, as the register can be set - during the device trimming in the SystemInit() function. - -config SOC_HFXO_CAP_EXTERNAL - bool "Use external load capacitors" - -config SOC_HFXO_CAP_INTERNAL - bool "Use internal load capacitors" - depends on NRF_SOC_SECURE_SUPPORTED - -endchoice - -config SOC_HFXO_CAP_INT_VALUE_X2 - int "Doubled value of HFXO internal load capacitors (in pF)" - depends on SOC_HFXO_CAP_INTERNAL - range 14 40 - help - Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps - can be enabled on pins XC1 and XC2. This option specifies doubled - capacitance value for the two capacitors. Set it to 14 to get 7.0 pF - for each capacitor, 15 to get 7.5 pF, and so on. - -endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM - -endif # SOC_NRF5340_CPUAPP - - -config NRF_ENABLE_CACHE - bool "Cache" - depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \ - || SOC_NRF5340_CPUNET - default y - help - Instruction and Data cache is available on nRF5340 CPUAPP - (Application MCU). It may only be accessed by Secure code. - - Instruction cache only (I-Cache) is available in nRF5340 - CPUNET (Network MCU). - -config BUILD_WITH_TFM - # TF-M nRF53 platform enables the cache unconditionally. - select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP - -rsource "Kconfig.sync_rtc" - -endif # SOC_SERIES_NRF53X diff --git a/soc/arm/nordic_nrf/nrf54h/CMakeLists.txt b/soc/arm/nordic_nrf/nrf54h/CMakeLists.txt deleted file mode 100644 index 8b4df42fa55..00000000000 --- a/soc/arm/nordic_nrf/nrf54h/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(soc.c) - -# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes -# for the image correctly -zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld) diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp deleted file mode 100644 index d90f87c0b89..00000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF54H20 Application MCU - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF54H20_ENGA_CPUAPP - -config SOC - default "nrf54h20_enga_cpuapp" - -config NUM_IRQS - default 471 - -config NRF_REGTOOL_GENERATE_UICR - default y - -endif # SOC_NRF54H20_ENGA_CPUAPP diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpurad b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpurad deleted file mode 100644 index 6aae8c3a105..00000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpurad +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF54H20 Radio MCU - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF54H20_ENGA_CPURAD - -config SOC - default "nrf54h20_enga_cpurad" - -config NUM_IRQS - default 471 - -config NRF_REGTOOL_GENERATE_UICR - default y - -endif # SOC_NRF54H20_ENGA_CPURAD diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.series deleted file mode 100644 index ddc902d213e..00000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Nordic Semiconductor nRF54H MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF54HX - -rsource "Kconfig.defconfig.nrf54h*" - -config SOC_SERIES - default "nrf54h" - -config CACHE_NRF_CACHE - default y if EXTERNAL_CACHE - -endif # SOC_SERIES_NRF54HX diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.series b/soc/arm/nordic_nrf/nrf54h/Kconfig.series deleted file mode 100644 index 0b896f477ac..00000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Nordic Semiconductor nRF54H MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF54HX - bool "Nordic Semiconductor nRF54H series MCU" - select ARM - select ARMV8_M_DSP - select CPU_CORTEX_M33 - select SOC_FAMILY_NRF - select HAS_NRFX - select HAS_NORDIC_DRIVERS - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - help - Enable support for nRF54H MCU series diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.soc b/soc/arm/nordic_nrf/nrf54h/Kconfig.soc deleted file mode 100644 index 9c065e79eaf..00000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.soc +++ /dev/null @@ -1,37 +0,0 @@ -# Nordic Semiconductor nRF54H MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NRF54H20 - bool "nRF54H20" - depends on SOC_SERIES_NRF54HX - -if SOC_NRF54H20 - -choice - prompt "nRF54H20 MCU Selection" - -config SOC_NRF54H20_ENGA_CPUAPP - bool "nRF54H20 ENGA CPUAPP" - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CPU_HAS_FPU - -config SOC_NRF54H20_ENGA_CPURAD - bool "nRF54H20 ENGA CPURAD" - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CPU_HAS_FPU - -endchoice - -config NRF_ENABLE_ICACHE - bool "Instruction cache (I-Cache)" - default y - -endif # SOC_NRF54H20 diff --git a/soc/arm/nordic_nrf/nrf54l/CMakeLists.txt b/soc/arm/nordic_nrf/nrf54l/CMakeLists.txt deleted file mode 100644 index 33036acce8f..00000000000 --- a/soc/arm/nordic_nrf/nrf54l/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources( - soc.c - ../validate_rram_partitions.c) - -if (CONFIG_ELV_GRTC_LFXO_ALLOWED) - message(WARNING "WARNING! ELV mode feature is EXPERIMENTAL and may brick your device!") -endif() diff --git a/soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.series deleted file mode 100644 index 6c0a5bc606d..00000000000 --- a/soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Nordic Semiconductor nRF54L MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF54LX - -rsource "Kconfig.defconfig.nrf54l*" - -config SOC_SERIES - default "nrf54l" - -config CORTEX_M_SYSTICK - default !NRF_GRTC_TIMER - -config CACHE_NRF_CACHE - default y if EXTERNAL_CACHE - -endif # SOC_SERIES_NRF54LX diff --git a/soc/arm/nordic_nrf/nrf54l/Kconfig.series b/soc/arm/nordic_nrf/nrf54l/Kconfig.series deleted file mode 100644 index a9367a0bf36..00000000000 --- a/soc/arm/nordic_nrf/nrf54l/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Nordic Semiconductor nRF54L MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF54LX - bool "Nordic Semiconductor nRF54L series MCU" - select HAS_NRFX - select HAS_NORDIC_DRIVERS - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select SOC_FAMILY_NRF - help - Enable support for nRF54L MCU series diff --git a/soc/arm/nordic_nrf/nrf54l/Kconfig.soc b/soc/arm/nordic_nrf/nrf54l/Kconfig.soc deleted file mode 100644 index c42c8cfc9b3..00000000000 --- a/soc/arm/nordic_nrf/nrf54l/Kconfig.soc +++ /dev/null @@ -1,70 +0,0 @@ -# Nordic Semiconductor nRF54 MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF54LX - -config SOC_NRF54L15 - bool "NRF54L15" - -config SOC_NRF54L15_ENGA - bool "NRF54L15 ENGA" - select SOC_NRF54L15 - -config SOC_NRF54L15_ENGA_CPUAPP - bool "NRF54L15 ENGA CPUAPP" - select ARM - select ARMV8_M_DSP - select CPU_CORTEX_M33 - select CPU_HAS_ARM_MPU - select CPU_HAS_ICACHE - select CPU_HAS_ARM_SAU - select CPU_HAS_FPU - select HAS_HW_NRF_RADIO_IEEE802154 - select HAS_POWEROFF - select SOC_NRF54L15_ENGA - -config SOC_NRF54LX_SKIP_CLOCK_CONFIG - bool "Skip clock frequency configuration in system initialization" - help - With this option, the CPU clock frequency is not set during system initialization. - The CPU runs with the default, hardware-selected frequency. - -config SOC_NRF_FORCE_CONSTLAT - bool "Force constant-latency mode" - help - In constant latency mode the CPU wakeup latency and the PPI task response - will be constant and kept at a minimum. This is secured by forcing a set - of base resources on while in sleep. The advantage of having a constant - and predictable latency will be at the cost of having increased power consumption. - -config SOC_NRF54L_VREG_MAIN_DCDC - bool "NRF54L DC/DC converter." - help - To enable, an inductor must be connected to the DC/DC converter pin. - -config SOC_NRF54L_NORMAL_VOLTAGE_MODE - bool "NRF54L Normal Voltage Mode." - -config SOC_NRF54L_GLITCHDET_WORKAROUND - bool "Workaround that disables glitch detector" - default y - help - Temporary workaround - disabling glitch detector to limit power consumption. - -if NRF_GRTC_TIMER - -config ELV_GRTC_LFXO_ALLOWED - bool - depends on NRF_GRTC_SLEEP_ALLOWED - select EXPERIMENTAL - help - This feature allows using ELV mode when GRTC operates with the LFXO as - a low-frequency clock source. The LFXO is automatically activated when - preparing to system-off. - WARNING! This feature is EXPERIMENTAL and may brick your device! - -endif # NRF_GRTC_TIMER - -endif # SOC_SERIES_NRF54LX diff --git a/soc/arm/nordic_nrf/nrf91/CMakeLists.txt b/soc/arm/nordic_nrf/nrf91/CMakeLists.txt deleted file mode 100644 index 35d47fb252b..00000000000 --- a/soc/arm/nordic_nrf/nrf91/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(soc.c) diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.series deleted file mode 100644 index 6d6cccab999..00000000000 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF91 MCU line - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF91X - -source "soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf91*" - -config SOC_SERIES - default "nrf91" - -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - -endif # SOC_SERIES_NRF91X diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.series b/soc/arm/nordic_nrf/nrf91/Kconfig.series deleted file mode 100644 index 1be69c377e5..00000000000 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.series +++ /dev/null @@ -1,35 +0,0 @@ -# Nordic Semiconductor nRF91 MCU line - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF91X - bool "Nordic Semiconductor nRF91 series MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_NRF_IDAU - select CPU_HAS_FPU - select ARMV8_M_DSP - select SOC_FAMILY_NRF - imply XIP - select HAS_NRFX - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_POWEROFF - help - Enable support for NRF91 MCU series - -if SOC_SERIES_NRF91X -config NRF_SPU_FLASH_REGION_SIZE - hex - default 0x8000 - help - FLASH region size for the NRF_SPU peripheral - -config NRF_SPU_RAM_REGION_SIZE - hex - default 0x2000 - help - RAM region size for the NRF_SPU peripheral -endif diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.soc b/soc/arm/nordic_nrf/nrf91/Kconfig.soc deleted file mode 100644 index 0267ada4850..00000000000 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.soc +++ /dev/null @@ -1,47 +0,0 @@ -# Nordic Semiconductor nRF91 MCU line - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF91X - -config SOC_NRF9120 - bool - -config SOC_NRF9160 - bool - -choice - prompt "nRF91x MCU Selection" - -config SOC_NRF9160_SICA - bool "NRF9160_SICA" - select SOC_NRF9160 - -# The nRF9161 is technically a SiP (System-in-Package) that consists of -# the nRF9120 SoC and additional components like PMIC, FEM, and XTAL, -# so for nrfx/MDK the nRF9120 SoC is to be indicated as the build target, -# but since the nRF9161 is what a user can actually see on a board, using -# only nRF9120 in the Zephyr build infrastructure might be confusing. -# That's why in the top level of SoC definitions (for user-configurable -# options in Kconfig, for example) the nRF9161 term is used and nRF9120 -# underneath. -config SOC_NRF9161_LACA - bool "NRF9161_LACA" - select SOC_NRF9120 - -config SOC_NRF9131_LACA - bool "NRF9131_LACA" - select SOC_NRF9120 - -config SOC_NRF9151_LACA - bool "NRF9151_LACA" - select SOC_NRF9120 - -endchoice - -config NRF_ENABLE_ICACHE - bool "Instruction cache (I-Cache)" - default y - -endif # SOC_SERIES_NRF91X diff --git a/soc/arm/nuvoton_npcx/Kconfig b/soc/arm/nuvoton_npcx/Kconfig deleted file mode 100644 index 1e27a6c4608..00000000000 --- a/soc/arm/nuvoton_npcx/Kconfig +++ /dev/null @@ -1,195 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_NPCX - bool - -if SOC_FAMILY_NPCX -config SOC_FAMILY - string - default "nuvoton_npcx" - -menuconfig NPCX_HEADER - bool "The output binary with NPCX binary header" - help - On NPCX series chip, the NPCX ROM code loads firmware image from flash - to RAM by the firmware binary header setting. Enable this to invoke - the 'ecst' which generates the NPCX firmware header. - -if NPCX_HEADER - -config NPCX_IMAGE_OUTPUT_BIN - bool "Build npcx binary in BIN format" - default y - help - Build a "raw" binary zephyr/zephyr.npcx.bin in the build directory. - The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. - -config NPCX_IMAGE_OUTPUT_HEX - bool "Build npcx binary in HEX format" - depends on NPCX_IMAGE_OUTPUT_BIN - help - Build an HEX binary zephyr/zephyr.npcx.hex in the build directory. - This is generated from the npcx BIN image. - The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. - -config NPCX_HEADER_CHIP - string - default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC - default "npcx7m7" if SOC_NPCX7M7FC - default "npcx9m3" if SOC_NPCX9M3F - default "npcx9m6" if SOC_NPCX9M6F - default "npcx9m7" if SOC_NPCX9M7F - default "npcx9mfp" if SOC_NPCX9MFP - default "npcx4m3" if SOC_NPCX4M3F - default "npcx4m8" if SOC_NPCX4M8F - -choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE - prompt "Clock rate to use for SPI flash" - default NPCX_HEADER_SPI_MAX_CLOCK_20 - help - This selects the max clock rate that will be used for loading firmware - binary from flash to RAM. - -config NPCX_HEADER_SPI_MAX_CLOCK_20 - bool "SPI flash max clock rate of 20 MHz" - -config NPCX_HEADER_SPI_MAX_CLOCK_25 - bool "SPI flash max clock rate of 25 MHz" - -config NPCX_HEADER_SPI_MAX_CLOCK_33 - bool "SPI flash max clock rate of 33 MHz" - depends on !SOC_SERIES_NPCX9 - -config NPCX_HEADER_SPI_MAX_CLOCK_40 - bool "SPI flash max clock rate of 40 MHz" - -config NPCX_HEADER_SPI_MAX_CLOCK_50 - bool "SPI flash max clock rate of 50 MHz" -endchoice - -config NPCX_HEADER_SPI_MAX_CLOCK - int - default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20 - default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25 - default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33 - default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40 - default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50 - -choice NPCX_HEADER_SPI_READ_MODE_CHOICE - prompt "Reading mode used by the SPI flash" - default NPCX_HEADER_SPI_READ_MODE_NORMAL - help - This sets the reading mode that can be used by the SPI flash. - Reading modes supported are normal, fast, dual, and quad. - -config NPCX_HEADER_SPI_READ_MODE_NORMAL - bool "SPI flash operates with normal reading mode" - -config NPCX_HEADER_SPI_READ_MODE_FAST - bool "SPI flash operates with fast reading mode" - -config NPCX_HEADER_SPI_READ_MODE_DUAL - bool "SPI flash operates with dual reading mode" - -config NPCX_HEADER_SPI_READ_MODE_QUAD - bool "SPI flash operates with quad reading mode" -endchoice - -config NPCX_HEADER_SPI_READ_MODE - string - default "normal" if NPCX_HEADER_SPI_READ_MODE_NORMAL - default "fast" if NPCX_HEADER_SPI_READ_MODE_FAST - default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL - default "quad" if NPCX_HEADER_SPI_READ_MODE_QUAD - -choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE - prompt "Core clock to SPI flash clock ratio" - default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 - help - This sets the clock ratio (core clock / SPI clock) - -config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 - bool "NPCX SPI clock ratio 1" - help - The SPI flash clock has the same frequency as the core clock. - -config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2 - bool "NPCX SPI clock ratio 2" - help - The core clock frequency is twice the flash clock frequency. -endchoice - -config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO - int - default 1 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 - default 2 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2 - -config NPCX_HEADER_ENABLE_HEADER_CRC - bool "Header crc check" - help - When enabled, the header will be verified at boot using a crc - checksum. - -config NPCX_HEADER_ENABLE_FIRMWARE_CRC - bool "Firmware image crc check" - help - When enabled, the firmware image will be verified at boot using a - crc checksum. - -choice NPCX_HEADER_FLASH_SIZE_CHOICE - prompt "Flash size" - default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \ - SOC_SERIES_NPCX9 - default NPCX_HEADER_FLASH_SIZE_16M - help - This sets the SPI flash size. - -config NPCX_HEADER_FLASH_SIZE_0P5M_1M - bool "SPI flash size 0.5M or 1M Bytes" - help - The SPI flash size is 0.5M or 1M Bytes. - -config NPCX_HEADER_FLASH_SIZE_2M - bool "SPI flash size 2M Bytes" - help - The SPI flash size is 2M Bytes. - -config NPCX_HEADER_FLASH_SIZE_4M - bool "SPI flash size 4M Bytes" - help - The SPI flash size is 4M Bytes. - -config NPCX_HEADER_FLASH_SIZE_8M - bool "SPI flash size 8M Bytes" - help - The SPI flash size is 8M Bytes. - -config NPCX_HEADER_FLASH_SIZE_16M - bool "SPI flash size 16M Bytes" - help - The SPI flash size is 16M Bytes. -endchoice - -config NPCX_HEADER_FLASH_SIZE - int - default 1 if NPCX_HEADER_FLASH_SIZE_0P5M_1M - default 2 if NPCX_HEADER_FLASH_SIZE_2M - default 4 if NPCX_HEADER_FLASH_SIZE_4M - default 8 if NPCX_HEADER_FLASH_SIZE_8M - default 16 if NPCX_HEADER_FLASH_SIZE_16M - -endif # NPCX_HEADER - -# Select SoC Part No. and configuration options -source "soc/arm/nuvoton_npcx/*/Kconfig.soc" - -config NPCX_PM_TRACE - bool "Trace System Power Management in NPCX family" - depends on PM - help - Internal config to enable runtime power management traces. - -endif # SOC_FAMILY_NPCX diff --git a/soc/arm/nuvoton_npcx/Kconfig.defconfig b/soc/arm/nuvoton_npcx/Kconfig.defconfig deleted file mode 100644 index 0dcfc62eb23..00000000000 --- a/soc/arm/nuvoton_npcx/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nuvoton_npcx/*/Kconfig.defconfig.series" diff --git a/soc/arm/nuvoton_npcx/Kconfig.soc b/soc/arm/nuvoton_npcx/Kconfig.soc deleted file mode 100644 index 6cf9e5b9828..00000000000 --- a/soc/arm/nuvoton_npcx/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nuvoton_npcx/*/Kconfig.series" diff --git a/soc/arm/nuvoton_npcx/common/CMakeLists.txt b/soc/arm/nuvoton_npcx/common/CMakeLists.txt deleted file mode 100644 index d541efa0e4e..00000000000 --- a/soc/arm/nuvoton_npcx/common/CMakeLists.txt +++ /dev/null @@ -1,47 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_sources_ifdef(CONFIG_PM power.c) -zephyr_sources( - scfg.c - registers.c -) - -# Check for disabling header CRC. -if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_HEADER_CRC) - set(NPCX_HEADER_HCRC "-nohcrc") -endif() - -# Check for disabling firmware CRC. -if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_FIRMWARE_CRC) - set(NPCX_HEADER_FCRC "-nofcrc") -endif() - -if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_BIN) - set(NPCX_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.bin) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/ecst/ecst.py - -i ${KERNEL_BIN_NAME} - -o ${NPCX_BIN_NAME} - ${NPCX_HEADER_HCRC} ${NPCX_HEADER_FCRC} - -chip ${CONFIG_NPCX_HEADER_CHIP} - -flashsize ${CONFIG_NPCX_HEADER_FLASH_SIZE} - -spiclkratio ${CONFIG_NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO} - -spimaxclk ${CONFIG_NPCX_HEADER_SPI_MAX_CLOCK} - -spireadmode ${CONFIG_NPCX_HEADER_SPI_READ_MODE} - ) - if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_HEX) - set(NPCX_HEX_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.hex) - # Property magic which makes west flash choose right file. - set_property(TARGET runners_yaml_props_target PROPERTY hex_file "${CONFIG_KERNEL_BIN_NAME}.npcx.hex") - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND $ - $ - $binary - $ihex - $${NPCX_BIN_NAME} - $${NPCX_HEX_NAME} - $ - ) - endif() -endif() diff --git a/soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt b/soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt deleted file mode 100644 index 158ae5cbbc7..00000000000 --- a/soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_sources( - soc.c -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f deleted file mode 100644 index d56b4fac925..00000000000 --- a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX4M3F - -config SOC - default "npcx4m3f" - -endif # SOC_NPCX4M3F diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f deleted file mode 100644 index 00ba5b3b623..00000000000 --- a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX4M8F - -config SOC - default "npcx4m8f" - -endif # SOC_NPCX4M8F diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series deleted file mode 100644 index 1b692cf7621..00000000000 --- a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NPCX4 - -config SOC_SERIES - default "npcx4" - -config NUM_IRQS - default 128 - -config CORTEX_M_SYSTICK - default !NPCX_ITIM_TIMER - -config ESPI_TAF_NPCX - default y - depends on ESPI_SAF - -source "soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4*" - -endif # SOC_SERIES_NPCX4 diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.series b/soc/arm/nuvoton_npcx/npcx4/Kconfig.series deleted file mode 100644 index 1585ace4e98..00000000000 --- a/soc/arm/nuvoton_npcx/npcx4/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller NPCX4 series - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NPCX4 - bool "Nuvoton NPCX4 Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NPCX - select HAS_PM - help - Enable support for Nuvoton NPCX4 series diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.soc b/soc/arm/nuvoton_npcx/npcx4/Kconfig.soc deleted file mode 100644 index 3e5f5e1d195..00000000000 --- a/soc/arm/nuvoton_npcx/npcx4/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# Nuvoton NPCX4 EC series - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NPCX4 Selection" - depends on SOC_SERIES_NPCX4 - -config SOC_NPCX4M3F - bool "NPCX4M3F" - -config SOC_NPCX4M8F - bool "NPCX4M8F" - -endchoice diff --git a/soc/arm/nuvoton_npcx/npcx7/CMakeLists.txt b/soc/arm/nuvoton_npcx/npcx7/CMakeLists.txt deleted file mode 100644 index 01792bf9fce..00000000000 --- a/soc/arm/nuvoton_npcx/npcx7/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_sources( - soc.c -) - -zephyr_sources_ifdef( - CONFIG_ARM_MPU - mpu_regions.c -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fb b/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fb deleted file mode 100644 index 84f429d2211..00000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fb +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX7M6FB - -config SOC - default "npcx7m6fb" - -endif # SOC_NPCX7M6FB diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fc b/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fc deleted file mode 100644 index 54d4fbc9b9d..00000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fc +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX7M6FC - -config SOC - default "npcx7m6fc" - -endif # SOC_NPCX7M6FC diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m7fc b/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m7fc deleted file mode 100644 index a038a5df9bb..00000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m7fc +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX7M7FC - -config SOC - default "npcx7m7fc" - -endif # SOC_NPCX7M7FC diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series b/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series deleted file mode 100644 index 9b12678dc8e..00000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NPCX7 - -config SOC_SERIES - default "npcx7" - -config NUM_IRQS - default 64 - -config CORTEX_M_SYSTICK - default !NPCX_ITIM_TIMER - -source "soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7*" - -endif # SOC_SERIES_NPCX7 diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.series b/soc/arm/nuvoton_npcx/npcx7/Kconfig.series deleted file mode 100644 index 8f8898388cf..00000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller NPCX7 series - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NPCX7 - bool "Nuvoton NPCX7 Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NPCX - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - select HAS_PM - help - Enable support for Nuvoton NPCX7 series diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.soc b/soc/arm/nuvoton_npcx/npcx7/Kconfig.soc deleted file mode 100644 index efb7c8ff321..00000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Nuvoton NPCX7 EC series - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NPCX7 Selection" - depends on SOC_SERIES_NPCX7 - -config SOC_NPCX7M6FB - bool "NPCX7M6FB" - -config SOC_NPCX7M6FC - bool "NPCX7M6FC" - -config SOC_NPCX7M7FC - bool "NPCX7M7FC" - -endchoice diff --git a/soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt b/soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt deleted file mode 100644 index 56f793d0580..00000000000 --- a/soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m3f b/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m3f deleted file mode 100644 index f9696aa2fc9..00000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m3f +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX9M3F - -config SOC - default "npcx9m3f" - -endif # SOC_NPCX9M3F diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m6f b/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m6f deleted file mode 100644 index 9bdb30c57ce..00000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m6f +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX9M6F - -config SOC - default "npcx9m6f" - -endif # SOC_NPCX9M6F diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m7f b/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m7f deleted file mode 100644 index 391554865c7..00000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m7f +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2022 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX9M7F - -config SOC - default "npcx9m7f" - -endif # SOC_NPCX9M7F diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9mfp b/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9mfp deleted file mode 100644 index 170c3deceaa..00000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9mfp +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX9MFP - -config SOC - default "npcx9mfp" - -endif # SOC_NPCX9MFP diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.series b/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.series deleted file mode 100644 index 6487b70cf59..00000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NPCX9 - -config SOC_SERIES - default "npcx9" - -config NUM_IRQS - default 64 - -config CORTEX_M_SYSTICK - default !NPCX_ITIM_TIMER - -source "soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9*" - -endif # SOC_SERIES_NPCX9 diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.series b/soc/arm/nuvoton_npcx/npcx9/Kconfig.series deleted file mode 100644 index 82423b37059..00000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller NPCX9 series - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NPCX9 - bool "Nuvoton NPCX9 Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NPCX - select HAS_PM - help - Enable support for Nuvoton NPCX9 series diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.soc b/soc/arm/nuvoton_npcx/npcx9/Kconfig.soc deleted file mode 100644 index dbebc40d52d..00000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# Nuvoton NPCX9 EC series - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NPCX9 Selection" - depends on SOC_SERIES_NPCX9 - -config SOC_NPCX9M3F - bool "NPCX9M3F" - -config SOC_NPCX9M6F - bool "NPCX9M6F" - -config SOC_NPCX9M7F - bool "NPCX9M7F" - -config SOC_NPCX9MFP - bool "NPCX9MFP" - -endchoice diff --git a/soc/arm/nuvoton_numaker/Kconfig b/soc/arm/nuvoton_numaker/Kconfig deleted file mode 100644 index e9b668ec911..00000000000 --- a/soc/arm/nuvoton_numaker/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - - -config SOC_FAMILY_NUMAKER - select PLATFORM_SPECIFIC_INIT - bool - -if SOC_FAMILY_NUMAKER - -config SOC_FAMILY - string - default "nuvoton_numaker" - -source "soc/arm/nuvoton_numaker/*/Kconfig.soc" - -endif # SOC_FAMILY_NUMAKER diff --git a/soc/arm/nuvoton_numaker/Kconfig.defconfig b/soc/arm/nuvoton_numaker/Kconfig.defconfig deleted file mode 100644 index 72d91af7c01..00000000000 --- a/soc/arm/nuvoton_numaker/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nuvoton_numaker/*/Kconfig.defconfig.series" - -if SOC_FAMILY_NUMAKER - -config RESET - default y - -endif diff --git a/soc/arm/nuvoton_numaker/Kconfig.soc b/soc/arm/nuvoton_numaker/Kconfig.soc deleted file mode 100644 index 8e3ff44930a..00000000000 --- a/soc/arm/nuvoton_numaker/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nuvoton_numaker/*/Kconfig.series" diff --git a/soc/arm/nuvoton_numaker/m46x/CMakeLists.txt b/soc/arm/nuvoton_numaker/m46x/CMakeLists.txt deleted file mode 100644 index 2fa91b640cf..00000000000 --- a/soc/arm/nuvoton_numaker/m46x/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.series b/soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.series deleted file mode 100644 index 8bf1440b0ae..00000000000 --- a/soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_M46X - -source "soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.m46*" - -config SOC_SERIES - default "m46x" - -endif # SOC_SERIES_M46X diff --git a/soc/arm/nuvoton_numaker/m46x/Kconfig.series b/soc/arm/nuvoton_numaker/m46x/Kconfig.series deleted file mode 100644 index 381312bee1a..00000000000 --- a/soc/arm/nuvoton_numaker/m46x/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_M46X - bool "Nuvoton M46X Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CORTEX_M_SYSTICK if SYS_CLOCK_EXISTS - select SOC_FAMILY_NUMAKER - help - Enable support for Nuvoton M46X MCU series diff --git a/soc/arm/nuvoton_numaker/m46x/Kconfig.soc b/soc/arm/nuvoton_numaker/m46x/Kconfig.soc deleted file mode 100644 index 898d23bcece..00000000000 --- a/soc/arm/nuvoton_numaker/m46x/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Nuvoton M46X MCU Selection" - depends on SOC_SERIES_M46X - -config SOC_M467 - bool "M467" - select HAS_NUMAKER_HAL - -endchoice diff --git a/soc/arm/nuvoton_numicro/Kconfig b/soc/arm/nuvoton_numicro/Kconfig deleted file mode 100644 index a45654ac935..00000000000 --- a/soc/arm/nuvoton_numicro/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -config SOC_FAMILY_NUMICRO - select PLATFORM_SPECIFIC_INIT - bool - -if SOC_FAMILY_NUMICRO -config SOC_FAMILY - string - default "nuvoton_numicro" - -source "soc/arm/nuvoton_numicro/*/Kconfig.soc" - -endif # SOC_FAMILY_NUMICRO diff --git a/soc/arm/nuvoton_numicro/Kconfig.defconfig b/soc/arm/nuvoton_numicro/Kconfig.defconfig deleted file mode 100644 index 1786f2b0d5f..00000000000 --- a/soc/arm/nuvoton_numicro/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -source "soc/arm/nuvoton_numicro/*/Kconfig.defconfig.series" diff --git a/soc/arm/nuvoton_numicro/Kconfig.soc b/soc/arm/nuvoton_numicro/Kconfig.soc deleted file mode 100644 index 4345be93264..00000000000 --- a/soc/arm/nuvoton_numicro/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -source "soc/arm/nuvoton_numicro/*/Kconfig.series" diff --git a/soc/arm/nuvoton_numicro/m48x/CMakeLists.txt b/soc/arm/nuvoton_numicro/m48x/CMakeLists.txt deleted file mode 100644 index 322465a92ce..00000000000 --- a/soc/arm/nuvoton_numicro/m48x/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.series b/soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.series deleted file mode 100644 index ba545478814..00000000000 --- a/soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -if SOC_SERIES_M48X - -source "soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.m48*" - -config SOC_SERIES - default "m48x" - -endif # SOC_SERIES_M48X diff --git a/soc/arm/nuvoton_numicro/m48x/Kconfig.series b/soc/arm/nuvoton_numicro/m48x/Kconfig.series deleted file mode 100644 index 5e79ddfab9a..00000000000 --- a/soc/arm/nuvoton_numicro/m48x/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -config SOC_SERIES_M48X - bool "Nuvoton M48X Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NUMICRO - help - Enable support for NUVOTON M48X MCU series diff --git a/soc/arm/nuvoton_numicro/m48x/Kconfig.soc b/soc/arm/nuvoton_numicro/m48x/Kconfig.soc deleted file mode 100644 index cf8ca3d13c5..00000000000 --- a/soc/arm/nuvoton_numicro/m48x/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -choice - prompt "NUVOTON M48X MCU Selection" - depends on SOC_SERIES_M48X - -config SOC_M487 - bool "M487" - select HAS_NUMICRO_HAL - -endchoice diff --git a/soc/arm/nxp_imx/CMakeLists.txt b/soc/arm/nxp_imx/CMakeLists.txt deleted file mode 100644 index 00c429b533c..00000000000 --- a/soc/arm/nxp_imx/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/nxp_imx/Kconfig b/soc/arm/nxp_imx/Kconfig deleted file mode 100644 index cd77ab5c717..00000000000 --- a/soc/arm/nxp_imx/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -# Copyright (c) 2017-2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_IMX - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_IMX - -config SOC_FAMILY - string - default "nxp_imx" - - -# Used for default value in FLASH_MCUX_FLEXSPI_XIP -DT_CHOSEN_Z_FLASH := zephyr,flash -DT_COMPAT_FLEXSPI := nxp,imx-flexspi -# Macros to shorten Kconfig definitions -DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) -DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) - - -source "soc/arm/nxp_imx/*/Kconfig.soc" - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_IMX_RT5XX if SOC_SERIES_IMX_RT5XX - default SOC_PART_NUMBER_IMX_RT6XX if SOC_SERIES_IMX_RT6XX - default SOC_PART_NUMBER_IMX_RT if SOC_SERIES_IMX_RT - default SOC_PART_NUMBER_IMX_6X_M4 if SOC_SERIES_IMX_6X_M4 - default SOC_PART_NUMBER_IMX7_M4 if SOC_SERIES_IMX7_M4 - default SOC_PART_NUMBER_IMX8MM_M4 if SOC_SERIES_IMX8MM_M4 - default SOC_PART_NUMBER_IMX8ML_M7 if SOC_SERIES_IMX8ML_M7 - default SOC_PART_NUMBER_IMX8MQ_M4 if SOC_SERIES_IMX8MQ_M4 - -config FLASH_MCUX_FLEXSPI_XIP - bool "MCUX FlexSPI flash access with xip" - default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) - depends on (CODE_FLEXSPI || CODE_FLEXSPI2 || SOC_SERIES_IMX_RT6XX || SOC_SERIES_IMX_RT5XX) - select XIP - help - Allows for the soc to safely initialize the clocks for the - FlexSpi when planning to execute code in FlexSpi Memory. - - -endif # SOC_FAMILY_IMX diff --git a/soc/arm/nxp_imx/Kconfig.defconfig b/soc/arm/nxp_imx/Kconfig.defconfig deleted file mode 100644 index 7e27aff32fc..00000000000 --- a/soc/arm/nxp_imx/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SERIAL_INIT_PRIORITY - default 55 - depends on SERIAL - -source "soc/arm/nxp_imx/*/Kconfig.defconfig.series" diff --git a/soc/arm/nxp_imx/Kconfig.soc b/soc/arm/nxp_imx/Kconfig.soc deleted file mode 100644 index ccc5b2dc9ec..00000000000 --- a/soc/arm/nxp_imx/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_imx/*/Kconfig.series" diff --git a/soc/arm/nxp_imx/mcimx6x_m4/CMakeLists.txt b/soc/arm/nxp_imx/mcimx6x_m4/CMakeLists.txt deleted file mode 100644 index ee28789fe7d..00000000000 --- a/soc/arm/nxp_imx/mcimx6x_m4/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - soc_clk_freq.c -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 deleted file mode 100644 index d8f09a6d8b1..00000000000 --- a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 +++ /dev/null @@ -1,14 +0,0 @@ -# i.MX 6SoloX - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MCIMX6X_M4 - -config SOC - default "mcimx6x" - -config FPU - default y - -endif # SOC_MCIMX6X_M4 diff --git a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.series b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.series deleted file mode 100644 index aa2a90633f8..00000000000 --- a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# i.MX 6SoloX M4 core series - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX_6X_M4 - -config SOC_SERIES - default "mcimx6x_m4" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 128 - -config PINCTRL_IMX - default y if HAS_IMX_IOMUXC - depends on PINCTRL - -source "soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4" - -endif # SOC_SERIES_IMX_6X_M4 diff --git a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.series b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.series deleted file mode 100644 index 7279ac8596e..00000000000 --- a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# i.MX 6SoloX M4 core series - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX_6X_M4 - bool "i.MX 6SoloX M4 Core Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select HAS_IMX_HAL - select SOC_FAMILY_IMX - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CLOCK_CONTROL - help - Enable support for M4 core of i.MX 6SoloX MCU series diff --git a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc deleted file mode 100644 index 028d4f09212..00000000000 --- a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc +++ /dev/null @@ -1,85 +0,0 @@ -# i.MX 6SoloX M4 core series - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "i.MX 6SoloX Selection" - depends on SOC_SERIES_IMX_6X_M4 - -config SOC_MCIMX6X_M4 - bool "SOC_MCIMX6X_M4" - select HAS_IMX_HAL - select HAS_IMX_GPIO - select HAS_IMX_EPIT - select HAS_IMX_I2C - select HAS_IMX_IOMUXC - -endchoice - -if SOC_SERIES_IMX_6X_M4 - -config SOC_PART_NUMBER_MCIMX6X1EVK10AB - bool - -config SOC_PART_NUMBER_MCIMX6X1EVK10AC - bool - -config SOC_PART_NUMBER_MCIMX6X3EVK10AB - bool - -config SOC_PART_NUMBER_MCIMX6X3EVK10AC - bool - -config SOC_PART_NUMBER_MCIMX6X1EVO10AB - bool - -config SOC_PART_NUMBER_MCIMX6X1EVO10AC - bool - -config SOC_PART_NUMBER_MCIMX6X3EVO10AB - bool - -config SOC_PART_NUMBER_MCIMX6X3EVO10AC - bool - -config SOC_PART_NUMBER_MCIMX6X2EVN10AB - bool - -config SOC_PART_NUMBER_MCIMX6X2EVN10AC - bool - -config SOC_PART_NUMBER_MCIMX6X3EVN10AB - bool - -config SOC_PART_NUMBER_MCIMX6X3EVN10AC - bool - -config SOC_PART_NUMBER_MCIMX6X4EVM10AB - bool - -config SOC_PART_NUMBER_MCIMX6X4EVM10AC - bool - -config SOC_PART_NUMBER_IMX_6X_M4 - string - default "MCIMX6X1EVK10AB" if SOC_PART_NUMBER_MCIMX6X1EVK10AB - default "MCIMX6X1EVK10AC" if SOC_PART_NUMBER_MCIMX6X1EVK10AC - default "MCIMX6X3EVK10AB" if SOC_PART_NUMBER_MCIMX6X3EVK10AB - default "MCIMX6X3EVK10AC" if SOC_PART_NUMBER_MCIMX6X3EVK10AC - default "MCIMX6X1EVO10AB" if SOC_PART_NUMBER_MCIMX6X1EVO10AB - default "MCIMX6X1EVO10AC" if SOC_PART_NUMBER_MCIMX6X1EVO10AC - default "MCIMX6X3EVO10AB" if SOC_PART_NUMBER_MCIMX6X3EVO10AB - default "MCIMX6X3EVO10AC" if SOC_PART_NUMBER_MCIMX6X3EVO10AC - default "MCIMX6X2EVN10AB" if SOC_PART_NUMBER_MCIMX6X2EVN10AB - default "MCIMX6X2EVN10AC" if SOC_PART_NUMBER_MCIMX6X2EVN10AC - default "MCIMX6X3EVN10AB" if SOC_PART_NUMBER_MCIMX6X3EVN10AB - default "MCIMX6X3EVN10AC" if SOC_PART_NUMBER_MCIMX6X3EVN10AC - default "MCIMX6X4EVM10AB" if SOC_PART_NUMBER_MCIMX6X4EVM10AB - default "MCIMX6X4EVM10AC" if SOC_PART_NUMBER_MCIMX6X4EVM10AC - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_IMX_6X_M4 diff --git a/soc/arm/nxp_imx/mcimx7_m4/CMakeLists.txt b/soc/arm/nxp_imx/mcimx7_m4/CMakeLists.txt deleted file mode 100644 index e5c7ae22fd6..00000000000 --- a/soc/arm/nxp_imx/mcimx7_m4/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - soc_clk_freq.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4 b/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4 deleted file mode 100644 index 60def652e34..00000000000 --- a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4 +++ /dev/null @@ -1,17 +0,0 @@ -# iMX7 M4 core series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MCIMX7_M4 - -config SOC - default "mcimx7d" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 200000000 - -config GPIO - default y - -endif # SOC_MCIMX7_M4 diff --git a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.series b/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.series deleted file mode 100644 index 8e53a01f6d4..00000000000 --- a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# iMX7 M4 core series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX7_M4 - -config SOC_SERIES - default "mcimx7_m4" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 127 - -config PINCTRL_IMX - default y if HAS_IMX_IOMUXC - depends on PINCTRL - -source "soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4" - -endif # SOC_SERIES_IMX7_M4 diff --git a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.series b/soc/arm/nxp_imx/mcimx7_m4/Kconfig.series deleted file mode 100644 index e7ae54bcbda..00000000000 --- a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# iMX7 M4 core series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX7_M4 - bool "i.MX7 M4 Core Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_IMX - select CLOCK_CONTROL - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - help - Enable support for i.MX7 M4 MCU series diff --git a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.soc b/soc/arm/nxp_imx/mcimx7_m4/Kconfig.soc deleted file mode 100644 index 38d593fc85e..00000000000 --- a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.soc +++ /dev/null @@ -1,40 +0,0 @@ -# iMX7 M4 core series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "i.MX7 M4 Selection" - depends on SOC_SERIES_IMX7_M4 - -config SOC_MCIMX7_M4 - bool "SOC_MCIMX7_M4" - select HAS_IMX_HAL - select HAS_IMX_GPIO - select HAS_IMX_I2C - select HAS_IMX_IOMUXC - -endchoice - -if SOC_MCIMX7_M4 - -config SOC_PART_NUMBER_MCIMX7D7DVM10SC - bool - -config SOC_PART_NUMBER_MCIMX7D5EVM10SC - bool - -config SOC_PART_NUMBER_MCIMX7S3DVK08SA - bool - -config SOC_PART_NUMBER_IMX7_M4 - string - default "MCIMX7D7DVM10SC" if SOC_PART_NUMBER_MCIMX7D7DVM10SC - default "MCIMX7D5EVM10SC" if SOC_PART_NUMBER_MCIMX7D5EVM10SC - default "MCIMX7S3DVK08SA" if SOC_PART_NUMBER_MCIMX7S3DVK08SA - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_IMX7_M4 diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/CMakeLists.txt b/soc/arm/nxp_imx/mimx8ml8_m7/CMakeLists.txt deleted file mode 100644 index 3dce744104f..00000000000 --- a/soc/arm/nxp_imx/mimx8ml8_m7/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_sources( - soc.c - mpu_regions.c -) - -if(CONFIG_OPENAMP_RSC_TABLE) - zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) - zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.mimx8ml8_m7 b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.mimx8ml8_m7 deleted file mode 100644 index 8b92477601c..00000000000 --- a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.mimx8ml8_m7 +++ /dev/null @@ -1,43 +0,0 @@ -# MIMX8ML8 SoC defconfig - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8ML8 - -config SOC - string - default "mimx8ml8" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 800000000 - -config GPIO - default y - -config IPM_IMX - default y - depends on IPM - -if CODE_ITCM - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/itcm@0,0,K) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/itcm@0) - -endif # CODE_ITCM - -if CODE_DDR - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/code@80000000,0,K) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/code@80000000) - -endif # CODE_DDR - -endif # SOC_MIMX8ML8 diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.series b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.series deleted file mode 100644 index 01d49fdf49b..00000000000 --- a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# i.MX8ML M7 SoC series defconfig - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX8ML_M7 - -config SOC_SERIES - default "mimx8ml8_m7" - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 159 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -source "soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.mimx8ml8_m7" - -endif # SOC_SERIES_IMX8ML_M7 diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.series b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.series deleted file mode 100644 index f1eb1fd40fd..00000000000 --- a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# i.MX8ML M7 core series - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX8ML_M7 - bool "i.MX8ML M7 Core Series" - select ARM - select CPU_CORTEX_M7 - select SOC_FAMILY_IMX - select CPU_HAS_FPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select INIT_VIDEO_PLL - help - Enable support for i.MX8ML M7 MCU series diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc deleted file mode 100644 index 224a112a67f..00000000000 --- a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc +++ /dev/null @@ -1,50 +0,0 @@ -# i.MX8ML M7 SoC series - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "i.MX8ML M7 Selection" -depends on SOC_SERIES_IMX8ML_M7 - -config SOC_MIMX8ML8 - bool "SOC_MIMX8ML8" - select HAS_MCUX - select HAS_MCUX_CCM - select HAS_MCUX_RDC - select CPU_HAS_ARM_MPU - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - select ARM_MPU - select HAS_MCUX_IGPIO - select HAS_MCUX_IOMUXC - -endchoice - -if SOC_SERIES_IMX8ML_M7 - -config SOC_PART_NUMBER_MIMX8ML8DVNLZ - bool - -config SOC_PART_NUMBER_IMX8ML_M7 - string - default "MIMX8ML8DVNLZ" if SOC_PART_NUMBER_MIMX8ML8DVNLZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -choice CODE_LOCATION - prompt "Code location selection" - -config CODE_ITCM - bool "Link code into internal instruction tightly coupled memory (ITCM)" - -config CODE_DDR - bool "Link code into DDR memory" - -endchoice - -config INIT_VIDEO_PLL - bool "Initialize Video PLL" - -endif # SOC_SERIES_IMX8ML_M7 diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/CMakeLists.txt b/soc/arm/nxp_imx/mimx8mm6_m4/CMakeLists.txt deleted file mode 100644 index ef0ba73b159..00000000000 --- a/soc/arm/nxp_imx/mimx8mm6_m4/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2020, Manivannan Sadhasivam -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -if(CONFIG_OPENAMP_RSC_TABLE) - zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) - zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.mimx8mm6_m4 b/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.mimx8mm6_m4 deleted file mode 100644 index 70e75a6bfce..00000000000 --- a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.mimx8mm6_m4 +++ /dev/null @@ -1,20 +0,0 @@ -# MIMX8MM6 SoC defconfig - -# Copyright (c) 2020, Manivannan Sadhasivam -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8MM6 - -config SOC - string - default "mimx8mm6" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 400000000 - -config IPM_IMX - default y - depends on IPM - -endif # SOC_MIMX8MM6 diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.series b/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.series deleted file mode 100644 index e9a6760962b..00000000000 --- a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# i.MX8MM M4 SoC series defconfig - -# Copyright (c) 2020, Manivannan Sadhasivam -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX8MM_M4 - -config SOC_SERIES - default "mimx8mm6_m4" - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 127 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -source "soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.mimx8mm6_m4" - -endif # SOC_SERIES_IMX8MM_M4 diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.series b/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.series deleted file mode 100644 index f860a7fbd26..00000000000 --- a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# i.MX8MM M4 core series - -# Copyright (c) 2020, Manivannan Sadhasivam -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX8MM_M4 - bool "i.MX8MM M4 Core Series" - select ARM - select CPU_CORTEX_M4 - select SOC_FAMILY_IMX - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - help - Enable support for i.MX8MM M4 MCU series diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.soc b/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.soc deleted file mode 100644 index 94d41bb544a..00000000000 --- a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.soc +++ /dev/null @@ -1,33 +0,0 @@ -# i.MX8MM M4 SoC series - -# Copyright (c) 2020, Manivannan Sadhasivam -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "i.MX8MM M4 Selection" -depends on SOC_SERIES_IMX8MM_M4 - -config SOC_MIMX8MM6 - bool "SOC_MIMX8MM6" - select HAS_MCUX - select HAS_MCUX_CCM - select HAS_MCUX_RDC - select HAS_MCUX_IGPIO - select HAS_MCUX_IOMUXC - -endchoice - -if SOC_SERIES_IMX8MM_M4 - -config SOC_PART_NUMBER_MIMX8MM6DVTLZ - bool - -config SOC_PART_NUMBER_IMX8MM_M4 - string - default "MIMX8MM6DVTLZ" if SOC_PART_NUMBER_MIMX8MM6DVTLZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_IMX8MM_M4 diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/CMakeLists.txt b/soc/arm/nxp_imx/mimx8mq6_m4/CMakeLists.txt deleted file mode 100644 index 9555fd57a89..00000000000 --- a/soc/arm/nxp_imx/mimx8mq6_m4/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2021, Kwon Tae-young -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4 b/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4 deleted file mode 100644 index be244e4b61c..00000000000 --- a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4 +++ /dev/null @@ -1,20 +0,0 @@ -# MIMX8MQ6 SoC defconfig - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8MQ6 - -config SOC - string - default "mimx8mq6" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 266000000 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -endif # SOC_MIMX8MQ6 diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.series b/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.series deleted file mode 100644 index e5e8ed6d6de..00000000000 --- a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# i.MX8MQ M4 SoC series defconfig - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX8MQ_M4 - -config SOC_SERIES - default "mimx8mq6_m4" - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 127 - -source "soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4" - -endif # SOC_SERIES_IMX8MQ_M4 diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.series b/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.series deleted file mode 100644 index 3933037c3a0..00000000000 --- a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# i.MX8MQ M4 core series - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX8MQ_M4 - bool "i.MX8MQ M4 Core Series" - select ARM - select CPU_CORTEX_M4 - select SOC_FAMILY_IMX - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - help - Enable support for i.MX8MQ M4 MCU series diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.soc b/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.soc deleted file mode 100644 index 0165a4d2a19..00000000000 --- a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.soc +++ /dev/null @@ -1,32 +0,0 @@ -# i.MX8MQ M4 SoC series - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "i.MX8MQ M4 Selection" - depends on SOC_SERIES_IMX8MQ_M4 - -config SOC_MIMX8MQ6 - bool "SOC_MIMX8MQ6" - select HAS_MCUX - select HAS_MCUX_CCM - select HAS_MCUX_RDC - select HAS_MCUX_IOMUXC - -endchoice - -if SOC_SERIES_IMX8MQ_M4 - -config SOC_PART_NUMBER_MIMX8MQ6DVAJZ - bool - -config SOC_PART_NUMBER_IMX8MQ_M4 - string - default "MIMX8MQ6DVAJZ" if SOC_PART_NUMBER_MIMX8MQ6DVAJZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_IMX8MQ_M4 diff --git a/soc/arm/nxp_imx/rt/CMakeLists.txt b/soc/arm/nxp_imx/rt/CMakeLists.txt deleted file mode 100644 index a8f1d00765a..00000000000 --- a/soc/arm/nxp_imx/rt/CMakeLists.txt +++ /dev/null @@ -1,76 +0,0 @@ -# -# Copyright (c) 2017-2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# -zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT11XX soc_rt11xx.c) -zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT10XX soc_rt10xx.c) - -zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER - ROM_START SORT_KEY 0 boot_header.ld) - -# Add custom mpu regions -zephyr_sources(mpu_regions.c) - -zephyr_linker_section_configure( - SECTION .rom_start - INPUT ".boot_hdr.conf" - OFFSET ${CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET} - KEEP - PRIO 10 -) - -if(CONFIG_DEVICE_CONFIGURATION_DATA) - set(boot_hdr_dcd_data_section ".boot_hdr.dcd_data") -endif() - -if(CONFIG_PM) - zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT11XX power_rt11xx.c) -endif() - -if (CONFIG_SOC_SERIES_IMX_RT10XX AND CONFIG_MEMC_MCUX_FLEXSPI) - zephyr_sources(flexspi_rt10xx.c) - if (CONFIG_FLASH_MCUX_FLEXSPI_XIP) - zephyr_code_relocate(FILES flexspi_rt10xx.c LOCATION ITCM_TEXT) - endif() -endif () - - -if (CONFIG_SOC_SERIES_IMX_RT11XX AND CONFIG_MEMC_MCUX_FLEXSPI) - zephyr_sources(flexspi_rt11xx.c) - if (CONFIG_FLASH_MCUX_FLEXSPI_XIP) - zephyr_code_relocate(FILES flexspi_rt11xx.c LOCATION ITCM_TEXT) - endif() -endif () - -if (CONFIG_PM AND CONFIG_SOC_SERIES_IMX_RT10XX) - zephyr_sources(power_rt10xx.c) - zephyr_code_relocate(FILES power_rt10xx.c LOCATION ITCM_TEXT) - if (CONFIG_SOC_MIMXRT1064) - zephyr_sources(lpm_rt1064.c) - zephyr_code_relocate(FILES lpm_rt1064.c LOCATION ITCM_TEXT) - endif() -endif() - -zephyr_compile_definitions( - XIP_EXTERNAL_FLASH -) - -zephyr_compile_definitions_ifdef(CONFIG_ENTROPY_MCUX_CAAM CACHE_MODE_WRITE_THROUGH) - -zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER DATA_SECTION_IS_CACHEABLE=1) - -# flexram header -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc) - -zephyr_linker_section_configure( - SECTION .rom_start - INPUT ".boot_hdr.ivt" - ".boot_hdr.data" - ${boot_hdr_dcd_data_section} - OFFSET ${CONFIG_IMAGE_VECTOR_TABLE_OFFSET} - KEEP - PRIO 11 -) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1010 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1010 deleted file mode 100644 index 3ff5ee2ae89..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1010 +++ /dev/null @@ -1,24 +0,0 @@ -# i.MX RT1010 - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1011 - -config SOC - string - default "mimxrt1011" - -config NUM_IRQS - default 80 - -config DCDC_VALUE - default 0x12 - -config GPIO - default y - -config FLEXSPI_CONFIG_BLOCK_OFFSET - default 0x400 - -endif # SOC_MIMXRT1010 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015 deleted file mode 100644 index dac14a43468..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1015 - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1015 - -config SOC - default "mimxrt1015" - -config NUM_IRQS - default 142 - -config DCDC_VALUE - default 0x12 - -config GPIO - default y - -endif # SOC_MIMXRT1015 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1021 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1021 deleted file mode 100644 index b941b4a37a6..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1021 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1021 - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1021 - -config SOC - default "mimxrt1021" - -config NUM_IRQS - default 142 - -config DCDC_VALUE - default 0x12 - -config GPIO - default y - -endif # SOC_MIMXRT1021 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1024 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1024 deleted file mode 100644 index aa08f04f2d0..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1024 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1024 - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1024 - -config SOC - default "mimxrt1024" - -config NUM_IRQS - default 142 - -config DCDC_VALUE - default 0x12 - -config GPIO - default y - -endif # SOC_MIMXRT1024 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1042 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1042 deleted file mode 100644 index 878e70e27d2..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1042 +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1042 - -config SOC - default "mimxrt1042" - -config NUM_IRQS - default 157 - -config GPIO - default y - -# Set DCDC to 1.275V for 600 MHz AHB operation -config DCDC_VALUE - default 0x13 - -endif # SOC_MIMXRT1042 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052 deleted file mode 100644 index dc4c0189cad..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052 +++ /dev/null @@ -1,17 +0,0 @@ -# i.MX RT1052 - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1052 - -config SOC - default "mimxrt1052" - -config NUM_IRQS - default 160 - -config GPIO - default y - -endif # SOC_MIMXRT1052 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1062 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1062 deleted file mode 100644 index 5866a4a7c33..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1062 +++ /dev/null @@ -1,17 +0,0 @@ -# i.MX RT1062 - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1062 - -config SOC - default "mimxrt1062" - -config NUM_IRQS - default 160 - -config GPIO - default y - -endif # SOC_MIMXRT1062 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1064 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1064 deleted file mode 100644 index a31c7dbd39b..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1064 +++ /dev/null @@ -1,17 +0,0 @@ -# i.MX RT1064 - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1064 - -config SOC - default "mimxrt1064" - -config NUM_IRQS - default 160 - -config GPIO - default y - -endif # SOC_MIMXRT1064 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm4 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm4 deleted file mode 100644 index c3043d93523..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm4 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1160 CM4 - -# Copyright (c) 2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1166_CM4 - -config SOC - default "mimxrt1166_cm4" - -config NUM_IRQS - default 218 - -config GPIO - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 240000000 if CORTEX_M_SYSTICK - -endif # SOC_MIMXRT1166_CM4 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm7 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm7 deleted file mode 100644 index e26825f98a8..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm7 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1160 CM7 - -# Copyright (c) 2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1166_CM7 - -config SOC - default "mimxrt1166_cm7" - -config NUM_IRQS - default 218 - -config GPIO - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 600000000 if CORTEX_M_SYSTICK - -endif # SOC_MIMXRT1166_CM7 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm4 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm4 deleted file mode 100644 index 9df2704af34..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm4 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1170 CM4 - -# Copyright (c) 2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1176_CM4 - -config SOC - default "mimxrt1176_cm4" - -config NUM_IRQS - default 218 - -config GPIO - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 400000000 if CORTEX_M_SYSTICK - -endif # SOC_MIMXRT1170_CM4 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm7 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm7 deleted file mode 100644 index f829da5de87..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm7 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1170 CM7 - -# Copyright (c) 2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1176_CM7 - -config SOC - default "mimxrt1176_cm7" - -config NUM_IRQS - default 218 - -config GPIO - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 996000000 if CORTEX_M_SYSTICK - -endif # SOC_MIMXRT1176_CM7 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.series b/soc/arm/nxp_imx/rt/Kconfig.defconfig.series deleted file mode 100644 index 61f537a402d..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.series +++ /dev/null @@ -1,146 +0,0 @@ -# i.MX RT series - -# Copyright (c) 2017-2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX_RT - -config SOC_SERIES - default "rt" - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -config ADC_MCUX_12B1MSPS_SAR - default y if HAS_MCUX_12B1MSPS_SAR - depends on ADC - -config LOG_BACKEND_SWO_FREQ_HZ - default 7500000 - depends on LOG_BACKEND_SWO - -if FLASH_MCUX_FLEXSPI_XIP - -# Avoid RWW hazards by defaulting logging to disabled -choice FLASH_LOG_LEVEL_CHOICE - default FLASH_LOG_LEVEL_OFF -endchoice - -choice MEMC_LOG_LEVEL_CHOICE - default MEMC_LOG_LEVEL_OFF -endchoice - -endif - -# set the tick per sec as a divider of the GPT clock source -config SYS_CLOCK_TICKS_PER_SEC - default 4096 if MCUX_GPT_TIMER - -DT_SYSCLK_PATH := $(dt_nodelabel_path,sysclk) - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,$(DT_SYSCLK_PATH),clock-frequency) if SOC_SERIES_IMX_RT10XX && CORTEX_M_SYSTICK - default 32768 if MCUX_GPT_TIMER - -# Disable systick if using MCUX_GPT_TIMER, as they will conflict -config CORTEX_M_SYSTICK - default n if MCUX_GPT_TIMER - -config PM_MCUX_GPC - default y if HAS_MCUX_GPC - depends on SOC_SERIES_IMX_RT11XX && PM - -# Don't allow SOC to sleep after tests complete when PM is enabled -config ZTEST_NO_YIELD - default y if (ZTEST && PM) - -if SOC_SERIES_IMX_RT10XX && PM - -config CODE_DATA_RELOCATION - default y - -config PM_MCUX_GPC - default y if HAS_MCUX_GPC - -config PM_MCUX_DCDC - default y if HAS_MCUX_DCDC - -config PM_MCUX_PMU - default y if HAS_MCUX_PMU - -endif # SOC_SERIES_IMX_RT10XX && PM - -if ETH_NXP_ENET - -config SYSTEM_WORKQUEUE_STACK_SIZE - default 1560 - -endif # ETH_NXP_ENET - -DT_CHOSEN_Z_FLASH := zephyr,flash -DT_COMPAT_FLEXSPI := nxp,imx-flexspi - -DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) -DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) - -DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) -DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ - if $(DT_FLASH_PARENT_IS_FLEXSPI) - -config FLASH_SIZE - default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ - if $(DT_FLASH_HAS_SIZE_PROP) - -config MEMC - default y - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_EHCI -endchoice - -DT_CHOSEN_Z_DTCM := zephyr,dtcm - -choice SEGGER_RTT_SECTION - default SEGGER_RTT_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) - depends on USE_SEGGER_RTT -endchoice - -choice SEGGER_SYSVIEW_SECTION - default SEGGER_SYSVIEW_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) - depends on SEGGER_SYSTEMVIEW -endchoice - -# -# MBEDTLS is larger but much faster than TinyCrypt so choose wisely -# -config MBEDTLS -#config TINYCRYPT - default y if CSPRNG_ENABLED - depends on ENTROPY_GENERATOR - -if MBEDTLS -# -# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than -# what the ztest_thread_stack defaults to. -# -config TEST_EXTRA_STACK_SIZE - int - default 1024 -endif # MBEDTLS - -# Enable cache management features when using M7 core, since these parts -# have L1 instruction and data caches that should be enabled at boot -config CACHE_MANAGEMENT - default y if CPU_CORTEX_M7 - -source "soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt*" - -endif # SOC_SERIES_IMX_RT diff --git a/soc/arm/nxp_imx/rt/Kconfig.series b/soc/arm/nxp_imx/rt/Kconfig.series deleted file mode 100644 index 65edffe3cd5..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# iMX RT series - -# Copyright (c) 2017-2021,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX_RT - bool "i.MX RT Series" - select ARM - select SOC_FAMILY_IMX - select CLOCK_CONTROL - select HAS_PM - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - help - Enable support for i.MX RT MCU series diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc deleted file mode 100644 index cbc00915046..00000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.soc +++ /dev/null @@ -1,837 +0,0 @@ -# i.MX RT series - -# Copyright 2017-2021,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "i.MX RT Selection" - depends on SOC_SERIES_IMX_RT - -config SOC_MIMXRT1011 - bool "SOC_MIMXRT1011" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_TRNG - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select INIT_ENET_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_EDMA - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1015 - bool "SOC_MIMXRT1015" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_TRNG - select CPU_HAS_FPU - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ENET_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_EDMA - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1021 - bool "SOC_MIMXRT1021" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_SEMC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ENET_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_PWM - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1024 - bool "SOC_MIMXRT1024" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_SEMC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ENET_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_SRC - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1042 - bool "SOC_MIMXRT1042" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_FLEXSPI - select HAS_MCUX_SEMC - select HAS_MCUX_IGPIO - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select HAS_MCUX_EDMA - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1051 - bool "SOC_MIMXRT1051" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_SEMC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_CSI - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1052 - bool "SOC_MIMXRT1052" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ELCDIF - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_SEMC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_CSI - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_PWM - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_MCUX_SRC - select HAS_SWO - select HAS_MCUX_XBARA - -config SOC_MIMXRT1061 - bool "SOC_MIMXRT1061" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_SEMC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_CSI - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1062 - bool "SOC_MIMXRT1062" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ELCDIF - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_PWM - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_QTMR - select HAS_MCUX_SEMC - select HAS_MCUX_SNVS - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_CSI - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_I2S - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_MCUX_ADC_ETC - select HAS_MCUX_SRC - select HAS_SWO - select HAS_MCUX_XBARA - -config SOC_MIMXRT1064 - bool "SOC_MIMXRT1064" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ELCDIF - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_PWM - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_QTMR - select HAS_MCUX_SEMC - select HAS_MCUX_SNVS - select HAS_MCUX_SRC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_CSI - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1176_CM7 - bool "SOC_MIMXRT1176_CM7" - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select SOC_SERIES_IMX_RT11XX - select HAS_MCUX_CACHE - select HAS_MCUX - select HAS_MCUX_SEMC - select HAS_MCUX_CCM_REV2 - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPADC - select HAS_MCUX_LPUART - select HAS_MCUX_ELCDIF - select HAS_MCUX_MIPI_DSI - select HAS_MCUX_GPT - select HAS_MCUX_FLEXSPI - select HAS_MCUX_FLEXCAN - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select INIT_VIDEO_PLL - select HAS_MCUX_EDMA - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - select BYPASS_LDO_LPSR - select ADJUST_LDO - select HAS_MCUX_PWM - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_ENET - select HAS_MCUX_GPC - select HAS_MCUX_I2S - select HAS_MCUX_USB_EHCI - select HAS_MCUX_ACMP - select HAS_MCUX_SRC_V2 - select HAS_MCUX_IOMUXC - select HAS_MCUX_XBARA - select HAS_SWO - -config SOC_MIMXRT1176_CM4 - bool "SOC_MIMXRT1176_CM4" - select CPU_CORTEX_M4 - select SOC_SERIES_IMX_RT11XX - select HAS_MCUX_CACHE - select HAS_MCUX - select HAS_MCUX_SEMC - select HAS_MCUX_CCM_REV2 - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_FLEXSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select INIT_VIDEO_PLL - select HAS_MCUX_EDMA - select HAS_MCUX_PWM - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_ENET - select HAS_MCUX_GPC - select HAS_MCUX_I2S - select HAS_MCUX_ACMP - select HAS_MCUX_SRC_V2 - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1166_CM7 - bool "SOC_MIMXRT1166_CM7" - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select SOC_SERIES_IMX_RT11XX - select HAS_MCUX_CACHE - select HAS_MCUX - select HAS_MCUX_SEMC - select HAS_MCUX_CCM_REV2 - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPADC - select HAS_MCUX_LPUART - select HAS_MCUX_FLEXSPI - select HAS_MCUX_GPT - select HAS_MCUX_FLEXCAN - select CPU_HAS_ARM_MPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select INIT_ARM_PLL - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select INIT_VIDEO_PLL - select HAS_MCUX_EDMA - select CPU_HAS_FPU_DOUBLE_PRECISION - select BYPASS_LDO_LPSR - select ADJUST_LDO - select HAS_MCUX_PWM - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_ENET - select HAS_MCUX_GPC - select HAS_MCUX_USB_EHCI - select HAS_MCUX_SRC_V2 - select HAS_MCUX_IOMUXC - select HAS_SWO - - -config SOC_MIMXRT1166_CM4 - bool "SOC_MIMXRT1166_CM4" - select CPU_CORTEX_M4 - select SOC_SERIES_IMX_RT11XX - select HAS_MCUX_CACHE - select HAS_MCUX - select HAS_MCUX_SEMC - select HAS_MCUX_CCM_REV2 - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_FLEXSPI - select HAS_MCUX_GPT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select INIT_ARM_PLL - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select INIT_VIDEO_PLL - select HAS_MCUX_EDMA - select HAS_MCUX_PWM - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_ENET - select HAS_MCUX_GPC - select HAS_MCUX_SRC_V2 - select HAS_MCUX_IOMUXC - select HAS_SWO - -endchoice - -if SOC_SERIES_IMX_RT - -config SOC_PART_NUMBER_MIMXRT1011CAE4A - bool - -config SOC_PART_NUMBER_MIMXRT1011DAE5A - bool - -config SOC_PART_NUMBER_MIMXRT1015CAF4A - bool - -config SOC_PART_NUMBER_MIMXRT1015DAF5A - bool - -config SOC_PART_NUMBER_MIMXRT1021CAF4A - bool - -config SOC_PART_NUMBER_MIMXRT1021CAG4A - bool - -config SOC_PART_NUMBER_MIMXRT1021DAF5A - bool - -config SOC_PART_NUMBER_MIMXRT1021DAG5A - bool - -config SOC_PART_NUMBER_MIMXRT1024CAG4A - bool - -config SOC_PART_NUMBER_MIMXRT1024DAG5A - bool - -config SOC_PART_NUMBER_MIMXRT1041DFP6B - bool - -config SOC_PART_NUMBER_MIMXRT1041DJM6B - bool - -config SOC_PART_NUMBER_MIMXRT1041XFP5B - bool - -config SOC_PART_NUMBER_MIMXRT1041XJM5B - bool - -config SOC_PART_NUMBER_MIMXRT1042DFP6B - bool - -config SOC_PART_NUMBER_MIMXRT1042DJM6B - bool - -config SOC_PART_NUMBER_MIMXRT1042XFP5B - bool - -config SOC_PART_NUMBER_MIMXRT1042XJM5B - bool - -config SOC_PART_NUMBER_MIMXRT1051CVL5A - bool - -config SOC_PART_NUMBER_MIMXRT1051DVL6A - bool - -config SOC_PART_NUMBER_MIMXRT1052CVJ5B - bool - -config SOC_PART_NUMBER_MIMXRT1052CVL5A - bool - -config SOC_PART_NUMBER_MIMXRT1052CVL5B - bool - -config SOC_PART_NUMBER_MIMXRT1052DVJ6B - bool - -config SOC_PART_NUMBER_MIMXRT1052DVL6A - bool - -config SOC_PART_NUMBER_MIMXRT1052DVL6B - bool - -config SOC_PART_NUMBER_MIMXRT1061CVL5A - bool - -config SOC_PART_NUMBER_MIMXRT1061DVL6A - bool - -config SOC_PART_NUMBER_MIMXRT1062CVJ5A - bool - -config SOC_PART_NUMBER_MIMXRT1062CVJ5B - bool - -config SOC_PART_NUMBER_MIMXRT1062CVL5A - bool - -config SOC_PART_NUMBER_MIMXRT1062DVJ6A - bool - -config SOC_PART_NUMBER_MIMXRT1062DVL6A - bool - -config SOC_PART_NUMBER_MIMXRT1064CVL5A - bool - -config SOC_PART_NUMBER_MIMXRT1064DVL6A - bool - -config SOC_PART_NUMBER_MIMXRT1166DVM6A - bool - -config SOC_PART_NUMBER_MIMXRT1176AVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1176CVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1176DVMAA - bool - -config SOC_PART_NUMBER_MIMXRT1175AVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1175CVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1175DVMAA - bool - -config SOC_PART_NUMBER_MIMXRT1173CVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1172AVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1172CVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1172DVMAA - bool - -config SOC_PART_NUMBER_MIMXRT1171AVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1171CVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1171DVMAA - bool - -config SOC_PART_NUMBER_IMX_RT - string - default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A - default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A - default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A - default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A - default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A - default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A - default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A - default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A - default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A - default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A - default "MIMXRT1041DFP6B" if SOC_PART_NUMBER_MIMXRT1041DFP6B - default "MIMXRT1041DJM6B" if SOC_PART_NUMBER_MIMXRT1041DJM6B - default "MIMXRT1041XFP5B" if SOC_PART_NUMBER_MIMXRT1041XFP5B - default "MIMXRT1041XJM5B" if SOC_PART_NUMBER_MIMXRT1041XJM5B - default "MIMXRT1042DFP6B" if SOC_PART_NUMBER_MIMXRT1042DFP6B - default "MIMXRT1042DJM6B" if SOC_PART_NUMBER_MIMXRT1042DJM6B - default "MIMXRT1042XFP5B" if SOC_PART_NUMBER_MIMXRT1042XFP5B - default "MIMXRT1042XJM5B" if SOC_PART_NUMBER_MIMXRT1042XJM5B - default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A - default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A - default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B - default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A - default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B - default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B - default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A - default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B - default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A - default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A - default "MIMXRT1062CVJ5A" if SOC_PART_NUMBER_MIMXRT1062CVJ5A - default "MIMXRT1062CVJ5B" if SOC_PART_NUMBER_MIMXRT1062CVJ5B - default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A - default "MIMXRT1062DVJ6A" if SOC_PART_NUMBER_MIMXRT1062DVJ6A - default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A - default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A - default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A - default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A - default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A - default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA - default "MIMXRT1166DVM6A" if SOC_PART_NUMBER_MIMXRT1166DVM6A - default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A - default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A - default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA - default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A - default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A - default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A - default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA - default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A - default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A - default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_SERIES_IMX_RT10XX - bool "i.MX RT 10XX Series" - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select PLATFORM_SPECIFIC_INIT - -config SOC_SERIES_IMX_RT11XX - bool "i.MX RT 11XX Series" - select PLATFORM_SPECIFIC_INIT - -config INIT_ARM_PLL - bool "Initialize ARM PLL" - -config INIT_VIDEO_PLL - bool "Initialize Video PLL" - -config INIT_ENET_PLL - bool - help - If y, the Ethernet PLL is initialized. Always enabled on e.g. - MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection - for MIMXRT1021"). - -config DCDC_VALUE - hex "DCDC value for VDD_SOC" - default 0x13 - -config ADJUST_DCDC - bool "Adjust internal DCDC output" - default y if SOC_SERIES_IMX_RT11XX - -config BYPASS_LDO_LPSR - bool "Bypass LDO lpsr" - -config ADJUST_LDO - bool "Adjust LDO setting" - -config PM_MCUX_GPC - bool "MCUX general power controller driver" - -config PM_MCUX_DCDC - bool "MCUX dcdc converter module driver" - -config PM_MCUX_PMU - bool "MCUX power management unit driver" - -menuconfig NXP_IMX_RT_BOOT_HEADER - bool "Boot header" - depends on (!BOOTLOADER_MCUBOOT) && CPU_CORTEX_M7 - help - Enable data structures required by the boot ROM to boot the - application from an external flash device. - -if NXP_IMX_RT_BOOT_HEADER - -choice BOOT_DEVICE - prompt "Boot device selection" - default BOOT_FLEXSPI_NOR - -config BOOT_FLEXSPI_NOR - bool "FlexSPI serial NOR" - -config BOOT_FLEXSPI_NAND - bool "FlexSPI serial NAND" - -config BOOT_SEMC_NOR - bool "SEMC parallel NOR" - -config BOOT_SEMC_NAND - bool "SEMC parallel NAND" - -endchoice - -config FLEXSPI_CONFIG_BLOCK_OFFSET - hex "FlexSPI config block offset" - default 0x0 if BOOT_FLEXSPI_NOR - help - FlexSPI configuration block consists of parameters regarding specific - flash devices including read command sequence, quad mode enablement - sequence (optional), etc. The boot ROM expects FlexSPI configuration - parameter to be presented in serial nor flash. - -config IMAGE_VECTOR_TABLE_OFFSET - hex "Image vector table offset" - default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR - default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND - help - The Image Vector Table (IVT) provides the boot ROM with pointers to - the application entry point and device configuration data. The boot - ROM requires a fixed IVT offset for each type of boot device. - -config DEVICE_CONFIGURATION_DATA - bool "Device configuration data" - help - Device configuration data (DCD) provides a sequence of commands to - the boot ROM to initialize components such as an SDRAM. This is - useful if your application expects components like SDRAM to be - initialized at boot time. - -endif # NXP_IMX_RT_BOOT_HEADER - -choice CODE_LOCATION - prompt "Code location selection" - default CODE_ITCM - -config CODE_SEMC - bool "Link code into external SEMC-controlled memory" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -config CODE_ITCM - bool "Link code into internal instruction tightly coupled memory (ITCM)" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -config CODE_FLEXSPI - bool "Link code into external FlexSPI-controlled memory" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -config CODE_FLEXSPI2 - bool "Link code into internal FlexSPI-controlled memory" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -config CODE_SRAM0 - bool "Link code into RAM_L memory (RAM_L)" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -config CODE_OCRAM - bool "Link code into OCRAM memory (OCRAM-M4)" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -endchoice - -config NXP_IMX_EXTERNAL_SDRAM - bool "Allow access to external SDRAM region" - help - Enable access to external SDRAM region managed by the SEMC. This - setting should be enabled when the application uses SDRAM, or - an MPU region will be defined to disable cached access to the - SDRAM memory space. - -config NXP_IMX_RT_ROM_RAMLOADER - depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMX_RT_BOOT_HEADER - # Required so that debugger will load image to correct offset - select BUILD_OUTPUT_HEX - bool "Create output image that IMX RT ROM can load from FlexSPI to ram" - help - Builds an output image that the IMX RT BootROM can load from the - FlexSPI boot device into RAM region. The image will be loaded - from FLEXSPI into the region specified by `zephyr,flash` node. - -# Setup LMA adjustment if using the RAMLOADER feature of ROM -FLASH_CHOSEN := zephyr,flash -FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) -FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) -config BUILD_OUTPUT_ADJUST_LMA - default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER - -config SECOND_CORE_MCUX - bool "Dual core operation on the RT11xx series" - depends on SOC_SERIES_IMX_RT11XX - help - Indicates the second core will be enabled, and the part will run - in dual core mode. Enables dual core operation on the RT11xx series, - by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU. - The M4 image will be loaded from flash into RAM based off a - generated header specifying the VMA and LMA of each memory section - to load - -endif # SOC_SERIES_IMX_RT diff --git a/soc/arm/nxp_imx/rt/boot_header.ld b/soc/arm/nxp_imx/rt/boot_header.ld deleted file mode 100644 index 501fde9fd4a..00000000000 --- a/soc/arm/nxp_imx/rt/boot_header.ld +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2019 NXP - * Copyright (c) 2019 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET; -KEEP(*(.boot_hdr.conf)) -. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; -KEEP(*(.boot_hdr.ivt)) -KEEP(*(.boot_hdr.data)) -#ifdef CONFIG_DEVICE_CONFIGURATION_DATA - KEEP(*(.boot_hdr.dcd_data)) -#endif diff --git a/soc/arm/nxp_imx/rt/linker.ld b/soc/arm/nxp_imx/rt/linker.ld deleted file mode 100644 index e4d5ad56db0..00000000000 --- a/soc/arm/nxp_imx/rt/linker.ld +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2014 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - - #include - -#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) - -MEMORY - { -#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0) - SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0)) -#endif - } - -#include diff --git a/soc/arm/nxp_imx/rt/pinctrl_soc.h b/soc/arm/nxp_imx/rt/pinctrl_soc.h deleted file mode 100644 index 81ea64f385f..00000000000 --- a/soc/arm/nxp_imx/rt/pinctrl_soc.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2022, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ -#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) -#include "pinctrl_rt10xx.h" -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) -#include "pinctrl_rt11xx.h" -#endif - -#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ */ diff --git a/soc/arm/nxp_imx/rt/power_rt10xx.c b/soc/arm/nxp_imx/rt/power_rt10xx.c deleted file mode 100644 index dea16d99570..00000000000 --- a/soc/arm/nxp_imx/rt/power_rt10xx.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2021 NXP - * - * SPDX-License-Identifier: Apache-2.0 - * - * Note: this file is linked to RAM. Any functions called while preparing for - * sleep mode must be defined within this file, or linked to RAM. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "power_rt10xx.h" - -LOG_MODULE_REGISTER(soc_power, CONFIG_SOC_LOG_LEVEL); - - -static struct clock_callbacks lpm_clock_hooks; - -/* - * Boards with RT10XX SOCs can register callbacks to set their clocks into - * normal/full speed mode, low speed mode, and low power mode. - * If callbacks are present, the low power subsystem will disable - * PLLs for power savings when entering low power states. - */ -void imxrt_clock_pm_callbacks_register(struct clock_callbacks *callbacks) -{ - /* If run callback is set, low power must be as well. */ - __ASSERT_NO_MSG(callbacks && callbacks->clock_set_run && callbacks->clock_set_low_power); - lpm_clock_hooks.clock_set_run = callbacks->clock_set_run; - lpm_clock_hooks.clock_set_low_power = callbacks->clock_set_low_power; - if (callbacks->clock_lpm_init) { - lpm_clock_hooks.clock_lpm_init = callbacks->clock_lpm_init; - } -} - -static void lpm_set_sleep_mode_config(clock_mode_t mode) -{ - uint32_t clpcr; - - /* Set GPC wakeup config to GPT timer interrupt */ - GPC_EnableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_gpt_hw_timer))); - /* - * ERR050143: CCM: When improper low-power sequence is used, - * the SoC enters low power mode before the ARM core executes WFI. - * - * Software workaround: - * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending - * by setting IOMUXC_GPR_GPR1_GINT. - * 2) Software should then unmask IRQ #41 in GPC before setting CCM - * Low-Power mode. - * 3) Software should mask IRQ #41 right after CCM Low-Power mode - * is set (set bits 0-1 of CCM_CLPCR). - */ - GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); - clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); - /* Note: if CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK is set, - * debugger will not connect in sleep mode - */ - /* Set clock control module to transfer system to idle mode */ - clpcr |= CCM_CLPCR_LPM(mode) | CCM_CLPCR_MASK_SCU_IDLE_MASK | - CCM_CLPCR_MASK_L2CC_IDLE_MASK | - CCM_CLPCR_STBY_COUNT_MASK | - CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK; -#ifndef CONFIG_SOC_MIMXRT1011 - /* RT1011 does not include handshake bits */ - clpcr |= CCM_CLPCR_BYPASS_LPM_HS0_MASK | CCM_CLPCR_BYPASS_LPM_HS1_MASK; -#endif - CCM->CLPCR = clpcr; - GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); -} - -static void lpm_enter_soft_off_mode(void) -{ - /* Enable the SNVS RTC as a wakeup source from soft-off mode, in case an RTC alarm - * was set. - */ - GPC_EnableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_imx_snvs_rtc))); - SNVS->LPCR |= SNVS_LPCR_TOP_MASK; -} - -static void lpm_enter_sleep_mode(clock_mode_t mode) -{ - /* FIXME: When this function is entered the Kernel has disabled - * interrupts using BASEPRI register. This is incorrect as it prevents - * waking up from any interrupt which priority is not 0. Work around the - * issue and disable interrupts using PRIMASK register as recommended - * by ARM. - */ - - /* Set PRIMASK */ - __disable_irq(); - /* Set BASEPRI to 0 */ - irq_unlock(0); - barrier_dsync_fence_full(); - barrier_isync_fence_full(); - - if (mode == kCLOCK_ModeWait) { - /* Clear the SLEEPDEEP bit to go into sleep mode (WAIT) */ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - } else { - /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - } - /* WFI instruction will start entry into WAIT/STOP mode */ - __WFI(); - -} - -static void lpm_set_run_mode_config(void) -{ - /* Clear GPC wakeup source */ - GPC_DisableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_gpt_hw_timer))); - CCM->CLPCR &= ~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK); -} - -/* Toggle the analog bandgap reference circuitry on and off */ -static void bandgap_set(bool on) -{ - if (on) { - /* Enable bandgap in PMU */ - PMU->MISC0_CLR = PMU_MISC0_REFTOP_PWD_MASK; - /* Wait for it to stabilize */ - while ((PMU->MISC0 & PMU_MISC0_REFTOP_VBGUP_MASK) == 0) { - - } - /* Disable low power bandgap */ - XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; - } else { - /* Disable bandgap in PMU and switch to low power one */ - XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; - PMU->MISC0_SET = PMU_MISC0_REFTOP_PWD_MASK; - } -} - -/* Should only be used if core clocks have been reduced- drops SOC voltage */ -static void lpm_drop_voltage(void) -{ - /* Move to the internal RC oscillator, since we are using low power clocks */ - CLOCK_InitRcOsc24M(); - /* Switch to internal RC oscillator */ - CLOCK_SwitchOsc(kCLOCK_RcOsc); - CLOCK_DeinitExternalClk(); - /* - * Change to 1.075V SOC voltage. If you are experiencing issues with - * low power mode stability, try raising this voltage value. - */ - DCDC_AdjustRunTargetVoltage(DCDC, 0xB); - /* Enable 2.5 and 1.1V weak regulators */ - PMU_2P5EnableWeakRegulator(PMU, true); - PMU_1P1EnableWeakRegulator(PMU, true); - /* Disable normal regulators */ - PMU_2P5EnableOutput(PMU, false); - PMU_1P1EnableOutput(PMU, false); - /* Disable analog bandgap */ - bandgap_set(false); -} - -/* Undo the changes made by lpm_drop_voltage so clocks can be raised */ -static void lpm_raise_voltage(void) -{ - /* Enable analog bandgap */ - bandgap_set(true); - /* Enable regulator LDOs */ - PMU_2P5EnableOutput(PMU, true); - PMU_1P1EnableOutput(PMU, true); - /* Disable weak LDOs */ - PMU_2P5EnableWeakRegulator(PMU, false); - PMU_1P1EnableWeakRegulator(PMU, false); - /* Change to 1.275V SOC voltage */ - DCDC_AdjustRunTargetVoltage(DCDC, 0x13); - /* Move to the external RC oscillator */ - CLOCK_InitExternalClk(0); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); -} - - -/* Sets device into low power mode */ -void pm_state_set(enum pm_state state, uint8_t substate_id) -{ - ARG_UNUSED(substate_id); - - switch (state) { - case PM_STATE_RUNTIME_IDLE: - LOG_DBG("entering PM state runtime idle"); - lpm_set_sleep_mode_config(kCLOCK_ModeWait); - lpm_enter_sleep_mode(kCLOCK_ModeWait); - break; - case PM_STATE_SUSPEND_TO_IDLE: - LOG_DBG("entering PM state suspend to idle"); - if (lpm_clock_hooks.clock_set_low_power) { - /* Drop the SOC clocks to low power mode, and decrease core voltage */ - lpm_clock_hooks.clock_set_low_power(); - lpm_drop_voltage(); - } - lpm_set_sleep_mode_config(kCLOCK_ModeWait); - lpm_enter_sleep_mode(kCLOCK_ModeWait); - break; - case PM_STATE_SOFT_OFF: - LOG_DBG("Entering PM state soft off"); - lpm_enter_soft_off_mode(); - break; - default: - return; - } -} - -/* Handle SOC specific activity after Low Power Mode Exit */ -void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) -{ - ARG_UNUSED(substate_id); - - /* Set run mode config after wakeup */ - switch (state) { - case PM_STATE_RUNTIME_IDLE: - lpm_set_run_mode_config(); - LOG_DBG("exited PM state runtime idle"); - break; - case PM_STATE_SUSPEND_TO_IDLE: - lpm_set_run_mode_config(); - if (lpm_clock_hooks.clock_set_run) { - /* Raise core voltage and restore SOC clocks */ - lpm_raise_voltage(); - lpm_clock_hooks.clock_set_run(); - } - LOG_DBG("exited PM state suspend to idle"); - break; - default: - break; - } - /* Clear PRIMASK after wakeup */ - __enable_irq(); -} - -/* Initialize power system */ -static int rt10xx_power_init(void) -{ - dcdc_internal_regulator_config_t reg_config; - - - /* Ensure clocks to ARM core memory will not be gated in low power mode - * if interrupt is pending - */ - CCM->CGPR |= CCM_CGPR_INT_MEM_CLK_LPM_MASK; - - if (lpm_clock_hooks.clock_lpm_init) { - lpm_clock_hooks.clock_lpm_init(); - } - - /* Errata ERR050143 */ - IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_GINT_MASK; - - /* Configure DCDC */ - DCDC_BootIntoDCM(DCDC); - /* Set target voltage for low power mode to 0.925V*/ - DCDC_AdjustLowPowerTargetVoltage(DCDC, 0x1); - /* Reconfigure DCDC to disable internal load resistor */ - reg_config.enableLoadResistor = false; - reg_config.feedbackPoint = 0x1; /* 1.0V with 1.3V reference voltage */ - DCDC_SetInternalRegulatorConfig(DCDC, ®_config); - - /* Enable high gate drive on power FETs to reduce leakage current */ - PMU_CoreEnableIncreaseGateDrive(PMU, true); - - - return 0; -} - -SYS_INIT(rt10xx_power_init, PRE_KERNEL_2, 0); diff --git a/soc/arm/nxp_imx/rt/soc.h b/soc/arm/nxp_imx/rt/soc.h deleted file mode 100644 index e5129c947d0..00000000000 --- a/soc/arm/nxp_imx/rt/soc.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2017, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _SOC__H_ -#define _SOC__H_ - -#include - -#ifndef _ASMLANGUAGE - -#include - -/* Add include for DTS generated information */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if CONFIG_I2S_MCUX_SAI -void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, - uint32_t clk_pre_div, uint32_t clk_src_div); - -#endif - -#if CONFIG_MIPI_DSI -void imxrt_pre_init_display_interface(void); - -void imxrt_post_init_display_interface(void); -#endif - -#ifdef CONFIG_MEMC -uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* !_ASMLANGUAGE */ - -#endif /* _SOC__H_ */ diff --git a/soc/arm/nxp_imx/rt/soc_rt10xx.c b/soc/arm/nxp_imx/rt/soc_rt10xx.c deleted file mode 100644 index dd6e534be23..00000000000 --- a/soc/arm/nxp_imx/rt/soc_rt10xx.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright 2017-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#include -#endif -#include -#include -#if CONFIG_USB_DC_NXP_EHCI -#include "usb_phy.h" -#include "usb.h" -#endif - -#include "memc_nxp_flexram.h" - -#include - -#define CCM_NODE DT_INST(0, nxp_imx_ccm) - -#define BUILD_ASSERT_PODF_IN_RANGE(podf, a, b) \ - BUILD_ASSERT(DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) >= (a) && \ - DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) <= (b), \ - #podf " is out of supported range (" #a ", " #b ")") - -#ifdef CONFIG_INIT_ARM_PLL -/* ARM PLL configuration for RUN mode */ -const clock_arm_pll_config_t armPllConfig = { - .loopDivider = 100U -}; -#endif - -#if CONFIG_USB_DC_NXP_EHCI -/* USB PHY condfiguration */ -#define BOARD_USB_PHY_D_CAL (0x0CU) -#define BOARD_USB_PHY_TXCAL45DP (0x06U) -#define BOARD_USB_PHY_TXCAL45DM (0x06U) -#endif - -#ifdef CONFIG_INIT_ENET_PLL -/* ENET PLL configuration for RUN mode */ -const clock_enet_pll_config_t ethPllConfig = { -#if defined(CONFIG_SOC_MIMXRT1011) || \ - defined(CONFIG_SOC_MIMXRT1015) || \ - defined(CONFIG_SOC_MIMXRT1021) || \ - defined(CONFIG_SOC_MIMXRT1024) - .enableClkOutput500M = true, -#endif -#if defined(CONFIG_ETH_NXP_ENET) || defined(CONFIG_ETH_MCUX) -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) - .enableClkOutput = true, -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) - .enableClkOutput1 = true, -#endif -#endif -#if defined(CONFIG_PTP_CLOCK_MCUX) - .enableClkOutput25M = true, -#else - .enableClkOutput25M = false, -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) - .loopDivider = 1, -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) - .loopDivider1 = 1, -#endif -}; -#endif - -#if CONFIG_USB_DC_NXP_EHCI - usb_phy_config_struct_t usbPhyConfig = { - BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, - }; -#endif - -#ifdef CONFIG_INIT_VIDEO_PLL -const clock_video_pll_config_t videoPllConfig = { - .loopDivider = 31, - .postDivider = 8, - .numerator = 0, - .denominator = 0, -}; -#endif - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -const __imx_boot_data_section BOOT_DATA_T boot_data = { -#ifdef CONFIG_XIP - .start = CONFIG_FLASH_BASE_ADDRESS, - .size = (uint32_t)&_flash_used, -#else - .start = CONFIG_SRAM_BASE_ADDRESS, - .size = (uint32_t)&_image_ram_size, -#endif - .plugin = PLUGIN_FLAG, - .placeholder = 0xFFFFFFFF, -}; - -const __imx_boot_ivt_section ivt image_vector_table = { - .hdr = IVT_HEADER, - .entry = (uint32_t) _vector_start, - .reserved1 = IVT_RSVD, -#ifdef CONFIG_DEVICE_CONFIGURATION_DATA - .dcd = (uint32_t) dcd_data, -#else - .dcd = (uint32_t) NULL, -#endif - .boot_data = (uint32_t) &boot_data, - .self = (uint32_t) &image_vector_table, - .csf = (uint32_t)CSF_ADDRESS, - .reserved2 = IVT_RSVD, -}; -#endif - -/** - * @brief Initialize the system clock - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Boot ROM did initialize the XTAL, here we only sets external XTAL - * OSC freq - */ - CLOCK_SetXtalFreq(DT_PROP(DT_CLOCKS_CTLR_BY_NAME(CCM_NODE, xtal), - clock_frequency)); - CLOCK_SetRtcXtalFreq(DT_PROP(DT_CLOCKS_CTLR_BY_NAME(CCM_NODE, rtc_xtal), - clock_frequency)); - - /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); - - /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); - - /* Setting the VDD_SOC value. - */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != - (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { - ; - } - -#ifdef CONFIG_INIT_ARM_PLL - CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */ -#endif -#ifdef CONFIG_INIT_ENET_PLL - CLOCK_InitEnetPll(ðPllConfig); -#endif -#ifdef CONFIG_INIT_VIDEO_PLL - CLOCK_InitVideoPll(&videoPllConfig); -#endif - -#if DT_NODE_EXISTS(DT_CHILD(CCM_NODE, arm_podf)) - /* Set ARM PODF */ - BUILD_ASSERT_PODF_IN_RANGE(arm_podf, 1, 8); - CLOCK_SetDiv(kCLOCK_ArmDiv, DT_PROP(DT_CHILD(CCM_NODE, arm_podf), clock_div) - 1); -#endif - /* Set AHB PODF */ - BUILD_ASSERT_PODF_IN_RANGE(ahb_podf, 1, 8); - CLOCK_SetDiv(kCLOCK_AhbDiv, DT_PROP(DT_CHILD(CCM_NODE, ahb_podf), clock_div) - 1); - /* Set IPG PODF */ - BUILD_ASSERT_PODF_IN_RANGE(ipg_podf, 1, 4); - CLOCK_SetDiv(kCLOCK_IpgDiv, DT_PROP(DT_CHILD(CCM_NODE, ipg_podf), clock_div) - 1); - - /* Set PRE_PERIPH_CLK to PLL1, 1200M */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); - - /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); - -#ifdef CONFIG_UART_MCUX_LPUART - /* Configure UART divider to default */ - CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ -#endif - -#ifdef CONFIG_I2C_MCUX_LPI2C - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); /* Set I2C source as USB1 PLL 480M */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5); /* Set I2C divider to 6 */ -#endif - -#ifdef CONFIG_SPI_MCUX_LPSPI - CLOCK_SetMux(kCLOCK_LpspiMux, 1); /* Set SPI source to USB1 PFD0 720M */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 7); /* Set SPI divider to 8 */ -#endif - -#ifdef CONFIG_DISPLAY_MCUX_ELCDIF - /* MUX selects video PLL, which is initialized to 93MHz */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 2); - /* Divide output by 2 */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 1); - /* Set final div based on LCDIF clock-frequency */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, - ((CLOCK_GetPllFreq(kCLOCK_PllVideo) / 2) / - DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), - clock_frequency)) - 1); -#endif - - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET -#if CONFIG_ETH_MCUX_RMII_EXT_CLK - /* Enable clock input for ENET1 */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, false); -#else - /* Enable clock output for ENET1 */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); -#endif -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) && CONFIG_NET_L2_ETHERNET - /* Set ENET2 ref clock to be generated by External OSC,*/ - /* direction as output and frequency to 50MHz */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2TxClkOutputDir | - kIOMUXC_GPR_ENET2RefClkMode, true); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI - CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); - CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); - USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && CONFIG_USB_DC_NXP_EHCI - CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); - CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); - USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC - /* Configure USDHC clock source and divider */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U); - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U); - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U); - CLOCK_EnableClock(kCLOCK_Usdhc1); -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_IMX_USDHC - /* Configure USDHC clock source and divider */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U); - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1U); - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 1U); - CLOCK_EnableClock(kCLOCK_Usdhc2); -#endif - -#ifdef CONFIG_VIDEO_MCUX_CSI - CLOCK_EnableClock(kCLOCK_Csi); /* Disable CSI clock gate */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 0); /* Set CSI divider to 1 */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); /* Set CSI source to OSC 24M */ -#endif -#ifdef CONFIG_CAN_MCUX_FLEXCAN - CLOCK_SetDiv(kCLOCK_CanDiv, 1); /* Set CAN_CLK_PODF. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); /* Set Can clock source. */ -#endif - -#ifdef CONFIG_LOG_BACKEND_SWO - /* Enable ARM trace clock to enable SWO output */ - CLOCK_EnableClock(kCLOCK_Trace); - /* Divide root clock output by 3 */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Source clock from 528MHz system PLL */ - CLOCK_SetMux(kCLOCK_TraceMux, 0); -#endif - - /* Keep the system clock running so SYSTICK can wake up the system from - * wfi. - */ - CLOCK_SetMode(kCLOCK_ModeRun); - -} - -#if CONFIG_I2S_MCUX_SAI -void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, - uint32_t clk_pre_div, uint32_t clk_src_div) -{ - switch (clock_name) { - case IMX_CCM_SAI1_CLK: - CLOCK_SetMux(kCLOCK_Sai1Mux, clk_src); - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, clk_pre_div); - CLOCK_SetDiv(kCLOCK_Sai1Div, clk_src_div); - break; - case IMX_CCM_SAI2_CLK: - CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src); - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, clk_pre_div); - CLOCK_SetDiv(kCLOCK_Sai2Div, clk_src_div); - break; - case IMX_CCM_SAI3_CLK: - CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src); - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, clk_pre_div); - CLOCK_SetDiv(kCLOCK_Sai2Div, clk_src_div); - break; - default: - return; - } -} -#endif - -/** - * - * @brief Perform basic hardware initialization - * - * Initialize the interrupt controller device drivers. - * Also initialize the timer device driver, if required. - * - * @return 0 - */ - -static int imxrt_init(void) -{ - sys_cache_instr_enable(); - sys_cache_data_enable(); - - /* Initialize system clock */ - clock_init(); - - return 0; -} - -#ifdef CONFIG_PLATFORM_SPECIFIC_INIT -void z_arm_platform_init(void) -{ - /* Call CMSIS SystemInit */ - SystemInit(); - -#if defined(FLEXRAM_RUNTIME_BANKS_USED) - /* Configure flexram if not running from RAM */ - memc_flexram_dt_partition(); -#endif -} -#endif - -SYS_INIT(imxrt_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_imx/rt/soc_rt11xx.c b/soc/arm/nxp_imx/rt/soc_rt11xx.c deleted file mode 100644 index 3adedde8d38..00000000000 --- a/soc/arm/nxp_imx/rt/soc_rt11xx.c +++ /dev/null @@ -1,728 +0,0 @@ -/* - * Copyright 2021-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#include -#endif -#include -#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) -#include -/* Memcpy macro to copy segments from secondary core image stored in flash - * to RAM section that secondary core boots from. - * n is the segment number, as defined in zephyr_image_info.h - */ -#define MEMCPY_SEGMENT(n, _) \ - memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_ ## n) - ADJUSTED_LMA), \ - (uint32_t *)(SEGMENT_LMA_ADDRESS_ ## n), \ - (SEGMENT_SIZE_ ## n)) -#endif -#if CONFIG_USB_DC_NXP_EHCI -#include "usb_phy.h" -#include "usb.h" -#endif -#include "memc_nxp_flexram.h" - -#include - -#define DUAL_CORE_MU_ENABLED \ - (CONFIG_SECOND_CORE_MCUX && CONFIG_IPM && CONFIG_IPM_IMX) - -#if DUAL_CORE_MU_ENABLED -/* Dual core mode is enabled, and messaging unit is present */ -#include -#define BOOT_FLAG 0x1U -#define MU_BASE (MU_Type *)DT_REG_ADDR(DT_INST(0, nxp_imx_mu)) -#endif - -#if CONFIG_USB_DC_NXP_EHCI /* USB PHY configuration */ -#define BOARD_USB_PHY_D_CAL (0x07U) -#define BOARD_USB_PHY_TXCAL45DP (0x06U) -#define BOARD_USB_PHY_TXCAL45DM (0x06U) -#endif - -#ifdef CONFIG_INIT_ARM_PLL -static const clock_arm_pll_config_t armPllConfig = { -#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1176_CM7) - /* resulting frequency: 24 * (166/(2* 2)) = 984MHz */ - /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ - .postDivider = kCLOCK_PllPostDiv2, - /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ - .loopDivider = 166, -#elif defined(CONFIG_SOC_MIMXRT1166_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM7) - /* resulting frequency: 24 * (200/(2 * 4)) = 600MHz */ - /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ - .postDivider = kCLOCK_PllPostDiv4, - /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ - .loopDivider = 200, -#else - #error "Unknown SOC, no pll configuration defined" -#endif -}; -#endif - -static const clock_sys_pll2_config_t sysPll2Config = { - /* Denominator of spread spectrum */ - .mfd = 268435455, - /* Spread spectrum parameter */ - .ss = NULL, - /* Enable spread spectrum or not */ - .ssEnable = false, -}; - -#ifdef CONFIG_INIT_ENET_PLL -static const clock_sys_pll1_config_t sysPll1Config = { - .pllDiv2En = true, -}; -#endif - -#ifdef CONFIG_INIT_VIDEO_PLL -static const clock_video_pll_config_t videoPllConfig = { - /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */ - .loopDivider = 41, - /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */ - .postDivider = 0, - /* - * 30 bit numerator of fractional loop divider, - * Fout = Fin * ( loopDivider + numerator / denominator ) - */ - .numerator = 1, - /* - * 30 bit denominator of fractional loop divider, - * Fout = Fin * ( loopDivider + numerator / denominator ) - */ - .denominator = 960000, - /* Spread spectrum parameter */ - .ss = NULL, - /* Enable spread spectrum or not */ - .ssEnable = false, -}; -#endif - -#if CONFIG_USB_DC_NXP_EHCI - usb_phy_config_struct_t usbPhyConfig = { - BOARD_USB_PHY_D_CAL, - BOARD_USB_PHY_TXCAL45DP, - BOARD_USB_PHY_TXCAL45DM, - }; -#endif - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -const __imx_boot_data_section BOOT_DATA_T boot_data = { -#ifdef CONFIG_XIP - .start = CONFIG_FLASH_BASE_ADDRESS, - .size = (uint32_t)&_flash_used, -#else - .start = CONFIG_SRAM_BASE_ADDRESS, - .size = (uint32_t)&_image_ram_size, -#endif - .plugin = PLUGIN_FLAG, - .placeholder = 0xFFFFFFFF, -}; - -extern char __start[]; -const __imx_boot_ivt_section ivt image_vector_table = { - .hdr = IVT_HEADER, - .entry = (uint32_t) __start, - .reserved1 = IVT_RSVD, -#ifdef CONFIG_DEVICE_CONFIGURATION_DATA - .dcd = (uint32_t) dcd_data, -#else - .dcd = (uint32_t) NULL, -#endif - .boot_data = (uint32_t) &boot_data, - .self = (uint32_t) &image_vector_table, - .csf = (uint32_t)CSF_ADDRESS, - .reserved2 = IVT_RSVD, -}; -#endif - -/** - * @brief Initialize the system clock - */ -static ALWAYS_INLINE void clock_init(void) -{ - clock_root_config_t rootCfg = {0}; - -#if CONFIG_ADJUST_DCDC - DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V); -#endif - -/* RT1160 does not have Forward Body Biasing on the CM7 core */ -#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1176_CM7) - /* Check if FBB need to be enabled in OverDrive(OD) mode */ - if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) { - PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true); - } else { - PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false); - } -#endif - -#if CONFIG_BYPASS_LDO_LPSR - PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true); - PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true); -#endif - -#if CONFIG_ADJUST_LDO - pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig; - pmu_static_lpsr_dig_config_t lpsrDigConfig; - - if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & - ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL) { - PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig); - PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig); - } - - if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & - ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL) { - PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig); - lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V; - PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig); - } -#endif - - /* PLL LDO shall be enabled first before enable PLLs */ - - /* Config CLK_1M */ - CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); - - /* Init OSC RC 16M */ - ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK; - - /* Init OSC RC 400M */ - CLOCK_OSC_EnableOscRc400M(); - CLOCK_OSC_GateOscRc400M(true); - - /* Init OSC RC 48M */ - CLOCK_OSC_EnableOsc48M(true); - CLOCK_OSC_EnableOsc48MDiv2(true); - - /* Config OSC 24M */ - ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | - ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | - ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | - ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | - ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); - - /* Wait for 24M OSC to be stable. */ - while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != - (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) { - } - - rootCfg.div = 1; - -#ifdef CONFIG_CPU_CORTEX_M7 - /* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ - rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); - - rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); -#endif - -#if CONFIG_CPU_CORTEX_M4 - rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); - - rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); -#endif - - /* - * If DCD is used, please make sure the clock source of SEMC is not - * changed in the following PLL/PFD configuration code. - */ - -#ifdef CONFIG_INIT_ARM_PLL - /* Init Arm Pll. */ - CLOCK_InitArmPll(&armPllConfig); -#endif - -#ifdef CONFIG_INIT_ENET_PLL - CLOCK_InitSysPll1(&sysPll1Config); -#else - /* Bypass Sys Pll1. */ - CLOCK_SetPllBypass(kCLOCK_PllSys1, true); - - /* DeInit Sys Pll1. */ - CLOCK_DeinitSysPll1(); -#endif - - /* Init Sys Pll2. */ - CLOCK_InitSysPll2(&sysPll2Config); - - /* Init System Pll2 pfd0. */ - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); - - /* Init System Pll2 pfd1. */ - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); - - /* Init System Pll2 pfd2. */ - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); - - /* Init System Pll2 pfd3. */ -#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24); -#else - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); -#endif - - /* Init Sys Pll3. */ - CLOCK_InitSysPll3(); - - /* Init System Pll3 pfd0. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13); - - /* Init System Pll3 pfd1. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17); - - /* Init System Pll3 pfd2. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32); - - /* Init System Pll3 pfd3. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22); - -#ifdef CONFIG_INIT_VIDEO_PLL - /* Init Video Pll. */ - CLOCK_InitVideoPll(&videoPllConfig); -#endif - - /* Module clock root configurations. */ - /* Configure M7 using ARM_PLL_CLK */ -#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) - rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); -#endif - -#if defined(CONFIG_SOC_MIMXRT1166_CM4) - /* Configure M4 using SYS_PLL3_CLK */ - rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); -#elif defined(CONFIG_SOC_MIMXRT1176_CM4) - /* Configure M4 using SYS_PLL3_CLK_PFD3_CLK */ - rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); -#endif - - /* Configure BUS using SYS_PLL3_CLK */ -#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET - /* Configure root bus clock at 198M */ - rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); -#elif defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) - /* Keep root bus clock at default 240M */ - rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); -#endif - - /* Configure BUS_LPSR using SYS_PLL3_CLK */ -#if defined(CONFIG_SOC_MIMXRT1176_CM4) - rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; - rootCfg.div = 3; - CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); -#elif defined(CONFIG_SOC_MIMXRT1166_CM4) - rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; - rootCfg.div = 4; - CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); -#endif - - /* Configure CSSYS using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg); - - /* Configure CSTRACE using SYS_PLL2_CLK */ - rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out; - rootCfg.div = 4; - CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg); - - /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */ -#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM4) - rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg); -#endif - - /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */ -#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) - rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 240; - CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); -#endif - -#ifdef CONFIG_UART_MCUX_LPUART - /* Configure Lpuart1 using SysPll2*/ - rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out; - rootCfg.div = 22; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg); - - /* Configure Lpuart2 using SysPll2*/ - rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out; - rootCfg.div = 22; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg); -#endif - -#ifdef CONFIG_I2C_MCUX_LPI2C - /* Configure Lpi2c1 using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg); - - /* Configure Lpi2c5 using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg); -#endif - - -#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) - /* 50 MHz ENET clock */ - rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2; - rootCfg.div = 10; - CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); -#if CONFIG_ETH_MCUX_RMII_EXT_CLK - /* Set ENET_REF_CLK as an input driven by PHY */ - IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U); - IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U); -#else - /* Set ENET_REF_CLK as an output driven by ENET1_CLK_ROOT */ - IOMUXC_GPR->GPR4 |= (IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U) | - IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U)); -#endif -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet1g), okay) - /* - * 50 MHz clock for 10/100Mbit RMII PHY - - * operate ENET1G just like ENET peripheral - */ - rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2; - rootCfg.div = 10; - CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); -#if CONFIG_ETH_MCUX_RMII_EXT_CLK - /* Set ENET1G_REF_CLK as an input driven by PHY */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U); - IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U); -#else - /* Set ENET1G_REF_CLK as an output driven by ENET2_CLK_ROOT */ - IOMUXC_GPR->GPR5 |= (IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U) | - IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U)); -#endif -#endif -#endif - -#ifdef CONFIG_PTP_CLOCK_MCUX - /* 24MHz PTP clock */ - rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg); -#endif - -#ifdef CONFIG_SPI_MCUX_LPSPI - /* Configure lpspi using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg); -#endif - -#ifdef CONFIG_CAN_MCUX_FLEXCAN -#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan1), okay) - /* Configure CAN1 using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan3), okay) - /* Configure CAN1 using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); -#endif -#endif - -#ifdef CONFIG_MCUX_ACMP -#if DT_NODE_HAS_STATUS(DT_NODELABEL(acmp1), okay) - /* Configure ACMP1 using Osc48MDiv2*/ - rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); -#endif -#endif - -#ifdef CONFIG_DISPLAY_MCUX_ELCDIF - rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out; - /* - * PLL2 is fixed at 528MHz. Use desired panel clock clock to - * calculate LCDIF clock. - */ - rootCfg.div = ((SYS_PLL2_FREQ / - DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), - clock_frequency)) + 1); - CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg); -#endif - -#ifdef CONFIG_COUNTER_MCUX_GPT - rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI - CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); - CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); - USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && CONFIG_USB_DC_NXP_EHCI - CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); - CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); - USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig); -#endif - -#if CONFIG_IMX_USDHC -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) - /* Configure USDHC1 using SysPll2Pfd2*/ - rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); - CLOCK_EnableClock(kCLOCK_Usdhc1); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) - /* Configure USDHC2 using SysPll2Pfd2*/ - rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); - CLOCK_EnableClock(kCLOCK_Usdhc2); -#endif -#endif - -#if !(defined(CONFIG_CODE_FLEXSPI) || defined(CONFIG_CODE_FLEXSPI2)) && \ - defined(CONFIG_MEMC_MCUX_FLEXSPI) && \ - DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay) - /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg); -#endif - - /* Keep core clock ungated during WFI */ - CCM->GPR_PRIVATE1_SET = 0x1; - /* Keep the system clock running so SYSTICK can wake up the system from - * wfi. - */ - GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_0, kGPC_RunMode); - GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_1, kGPC_RunMode); - GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_0, false); - GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_1, false); - -#if !defined(CONFIG_PM) - /* Enable the AHB clock while the CM7 is sleeping to allow debug access - * to TCM - */ - IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK; -#endif -} - -#if CONFIG_I2S_MCUX_SAI -void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, - uint32_t clk_pre_div, uint32_t clk_src_div) -{ - ARG_UNUSED(clk_pre_div); - - switch (clock_name) { - case IMX_CCM_SAI1_CLK: - CLOCK_SetRootClockMux(kCLOCK_Root_Sai1, clk_src); - CLOCK_SetRootClockDiv(kCLOCK_Root_Sai1, clk_src_div); - break; - case IMX_CCM_SAI2_CLK: - CLOCK_SetRootClockMux(kCLOCK_Root_Sai2, clk_src); - CLOCK_SetRootClockDiv(kCLOCK_Root_Sai2, clk_src_div); - break; - case IMX_CCM_SAI3_CLK: - CLOCK_SetRootClockMux(kCLOCK_Root_Sai3, clk_src); - CLOCK_SetRootClockDiv(kCLOCK_Root_Sai3, clk_src_div); - break; - case IMX_CCM_SAI4_CLK: - CLOCK_SetRootClockMux(kCLOCK_Root_Sai4, clk_src); - CLOCK_SetRootClockDiv(kCLOCK_Root_Sai4, clk_src_div); - break; - default: - return; - } -} -#endif - -#if CONFIG_MIPI_DSI -void imxrt_pre_init_display_interface(void) -{ - /* elcdif output to MIPI DSI */ - CLOCK_EnableClock(kCLOCK_Video_Mux); - VIDEO_MUX->VID_MUX_CTRL.CLR = VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK; - - /* Power on and isolation off. */ - PGMC_BPC4->BPC_POWER_CTRL |= (PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK | - PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK); - - /* Assert MIPI reset. */ - IOMUXC_GPR->GPR62 &= ~(IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK | - IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK | - IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK | - IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK); - - /* setup clock */ - const clock_root_config_t mipiEscClockConfig = { - .clockOff = false, - .mux = 4, - .div = 11, - }; - - CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &mipiEscClockConfig); - - /* TX esc clock */ - const clock_group_config_t mipiEscClockGroupConfig = { - .clockOff = false, - .resetDiv = 2, - .div0 = 2, - }; - - CLOCK_SetGroupConfig(kCLOCK_Group_MipiDsi, &mipiEscClockGroupConfig); - - const clock_root_config_t mipiDphyRefClockConfig = { - .clockOff = false, - .mux = 1, - .div = 1, - }; - - CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &mipiDphyRefClockConfig); - - /* Deassert PCLK and ESC reset. */ - IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK | - IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK); -} - -void imxrt_post_init_display_interface(void) -{ - /* deassert BYTE and DBI reset */ - IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK | - IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK); -} - -#endif - -/** - * - * @brief Perform basic hardware initialization - * - * Initialize the interrupt controller device drivers. - * Also initialize the timer device driver, if required. - * If dual core operation is enabled, the second core image will be loaded to RAM - * - * @return 0 - */ - -static int imxrt_init(void) -{ -#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) - /** - * Copy CM4 core from flash to memory. Note that depending on where the - * user decided to store CM4 code, this is likely going to read from the - * flexspi while using XIP. Provided we DO NOT WRITE TO THE FLEXSPI, - * this operation is safe. - * - * Note that this copy MUST occur before enabling the M7 caching to - * ensure the data is written directly to RAM (since the M4 core will use it) - */ - LISTIFY(SEGMENT_NUM, MEMCPY_SEGMENT, (;)); - /* Set the boot address for the second core */ - uint32_t boot_address = (uint32_t)(DT_REG_ADDR(DT_CHOSEN(zephyr_cpu1_region))); - /* Set VTOR for the CM4 core */ - IOMUXC_LPSR_GPR->GPR0 = IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(boot_address >> 3u); - IOMUXC_LPSR_GPR->GPR1 = IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(boot_address >> 16u); -#endif - -#if DUAL_CORE_MU_ENABLED && CONFIG_CPU_CORTEX_M4 - /* Set boot flag in messaging unit to indicate boot to primary core */ - MU_SetFlags(MU_BASE, BOOT_FLAG); -#endif - - -#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) - sys_cache_instr_enable(); - sys_cache_data_enable(); -#endif - - /* Initialize system clock */ - clock_init(); - - return 0; -} - -#ifdef CONFIG_PLATFORM_SPECIFIC_INIT -void z_arm_platform_init(void) -{ - SystemInit(); - -#if defined(FLEXRAM_RUNTIME_BANKS_USED) - /* Configure flexram if not running from RAM */ - memc_flexram_dt_partition(); -#endif -} -#endif - -SYS_INIT(imxrt_init, PRE_KERNEL_1, 0); - -#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) -/** - * @brief Kickoff secondary core. - * - * Kick the secondary core out of reset and wait for it to indicate boot. The - * core image was already copied to RAM (and the boot address was set) in - * imxrt_init() - * - * @return 0 - */ -static int second_core_boot(void) -{ - /* Kick CM4 core out of reset */ - SRC->CTRL_M4CORE = SRC_CTRL_M4CORE_SW_RESET_MASK; - SRC->SCR |= SRC_SCR_BT_RELEASE_M4_MASK; -#if DUAL_CORE_MU_ENABLED - /* Wait for the secondary core to start up and set boot flag in - * imxrt_init - */ - while (MU_GetFlags(MU_BASE) != BOOT_FLAG) { - /* Wait for secondary core to set flag */ - } -#endif - return 0; -} - -SYS_INIT(second_core_boot, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); -#endif diff --git a/soc/arm/nxp_imx/rt5xx/CMakeLists.txt b/soc/arm/nxp_imx/rt5xx/CMakeLists.txt deleted file mode 100644 index e12f2e9ae18..00000000000 --- a/soc/arm/nxp_imx/rt5xx/CMakeLists.txt +++ /dev/null @@ -1,33 +0,0 @@ -# -# Copyright (c) 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_compile_definitions(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) - -zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) - -zephyr_sources( - soc.c - flash_clock_setup.c - ) - -zephyr_sources_ifdef(CONFIG_PM power.c) - -zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) - -zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT5XX_BOOT_HEADER - ROM_START SORT_KEY 0 boot_header.ld) - -zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER - SECTIONS usb.ld) - -zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33 b/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33 deleted file mode 100644 index f8419fc3b1a..00000000000 --- a/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33 +++ /dev/null @@ -1,40 +0,0 @@ -# NXP MIMXRT5XX platform configuration options - -# Copyright (c) 2022, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT595S_CM33 - -config SOC - default "mimxrt595s_cm33" - -if MCUX_OS_TIMER - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -endif # MCUX_OS_TIMER - -if CORTEX_M_SYSTICK - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 250105263 - -endif # CORTEX_M_SYSTICK - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -# Enable the MEMC FlexSPI driver when using device power -# management so we can reconfigure the FlexSPI pins to -# save power. The MEMC FlexSPI driver is enabled when we -# enable the Flash subsystem, however we would like to -# reconfigure the FlexSPI pins even when the Flash driver -# is disabled, hence MEMC is selected when PM_DEVICE -# is turned on. -config MEMC - default y if PM_DEVICE - select MEMC_MCUX_FLEXSPI - -endif # SOC_MIMXRT685S_CM33 diff --git a/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.series b/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.series deleted file mode 100644 index b277f621d0a..00000000000 --- a/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.series +++ /dev/null @@ -1,82 +0,0 @@ -# i.MX RT5XX series configuration options - -# Copyright (c) 2022-2024, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX_RT5XX - -config SOC_SERIES - default "rt5xx" - -config ROM_START_OFFSET - default 0x1200 if NXP_IMX_RT5XX_BOOT_HEADER - -# The PVT Sensor uses IRQ #75. For more details, see -# https://www.nxp.com/design/design-center/software/embedded-software/application-software-packs/application-software-pack-dynamic-voltage-scaling-using-pvt-sensor:APP-SW-PACK-DVS-PVT-SENSOR -config NUM_IRQS - default 76 - -config ZTEST_NO_YIELD - default y if (PM && ZTEST) - -# The base address is determined from the zephyr,flash node with the following -# precedence: -# FlexSPI base address (if flash node is on a FlexSPI bus) -# node reg property (used for memory regions such as SRAM) - -# Workaround for not being able to have commas in macro arguments - -DT_CHOSEN_Z_FLASH := zephyr,flash -DT_COMPAT_FLEXSPI := nxp,imx-flexspi - -# Macros to shorten Kconfig definitions -DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) -DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ - if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -# The RT5xx has no internal flash. If the flash node has a size property, -# use that over the reg property. This is used for the external flash -# present on the board. Otherwise, fallback to the reg property -config FLASH_SIZE - default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ - if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -if FLASH_MCUX_FLEXSPI_XIP - -# Avoid RWW hazards by defaulting logging to disabled -choice FLASH_LOG_LEVEL_CHOICE - default FLASH_LOG_LEVEL_OFF -endchoice - -choice MEMC_LOG_LEVEL_CHOICE - default MEMC_LOG_LEVEL_OFF -endchoice - -endif - -# -# MBEDTLS is larger but much faster than TinyCrypt so choose wisely -# -config MBEDTLS -#config TINYCRYPT - default y if CSPRNG_ENABLED - depends on ENTROPY_GENERATOR - -if MBEDTLS -# -# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than -# what the ztest_thread_stack defaults to. -# -config TEST_EXTRA_STACK_SIZE - int - default 1024 -endif # MBEDTLS - -source "soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt5*" - -endif # SOC_SERIES_MIMXRT5XX diff --git a/soc/arm/nxp_imx/rt5xx/Kconfig.series b/soc/arm/nxp_imx/rt5xx/Kconfig.series deleted file mode 100644 index 96568031651..00000000000 --- a/soc/arm/nxp_imx/rt5xx/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# i.MX RT5XX Series - -# Copyright (c) 2022, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX_RT5XX - bool "i.MX RT5XX Series Family MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_IMX - select CLOCK_CONTROL - select HAS_PM - select HAS_POWEROFF - help - Enable support for i.MX RT5XX Series MCU series diff --git a/soc/arm/nxp_imx/rt5xx/Kconfig.soc b/soc/arm/nxp_imx/rt5xx/Kconfig.soc deleted file mode 100644 index 35b86c2e903..00000000000 --- a/soc/arm/nxp_imx/rt5xx/Kconfig.soc +++ /dev/null @@ -1,156 +0,0 @@ -# i.MX RT5XX Series - -# Copyright 2022-2023, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "i.MX RT5XX Series MCU Selection" - depends on SOC_SERIES_IMX_RT5XX - -config SOC_MIMXRT595S_CM33 - bool "SOC_MIMXRT595S M33" - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select PLATFORM_SPECIFIC_INIT - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CPU_CORTEX_M_HAS_SYSTICK - select HAS_MCUX - select HAS_MCUX_SYSCON - select HAS_MCUX_FLEXCOMM - select HAS_MCUX_FLEXSPI - select HAS_MCUX_CACHE - select HAS_MCUX_LPC_DMA - select HAS_MCUX_LPADC - select HAS_MCUX_OS_TIMER - select HAS_MCUX_LPC_RTC - select HAS_MCUX_TRNG - select HAS_MCUX_SCTIMER - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_USB_LPCIP3511 - select HAS_MCUX_CTIMER -endchoice - -if SOC_SERIES_IMX_RT5XX - -config SOC_PART_NUMBER_MIMXRT533SFFOC - bool - -config SOC_PART_NUMBER_MIMXRT555SFFOC - bool - -config SOC_PART_NUMBER_MIMXRT595SFFOC - bool - -config SOC_PART_NUMBER_MIMXRT533SFAWC - bool - -config SOC_PART_NUMBER_MIMXRT555SFAWC - bool - -config SOC_PART_NUMBER_MIMXRT595SFAWC - bool - -config SOC_PART_NUMBER_IMX_RT5XX - string - default "MIMXRT533SFAWC" if SOC_PART_NUMBER_MIMXRT533SFAWC - default "MIMXRT555SFAWC" if SOC_PART_NUMBER_MIMXRT555SFAWC - default "MIMXRT595SFAWC" if SOC_PART_NUMBER_MIMXRT595SFAWC - default "MIMXRT533SFFOC" if SOC_PART_NUMBER_MIMXRT533SFFOC - default "MIMXRT555SFFOC" if SOC_PART_NUMBER_MIMXRT555SFFOC - default "MIMXRT595SFFOC" if SOC_PART_NUMBER_MIMXRT595SFFOC - - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -menuconfig NXP_IMX_RT5XX_BOOT_HEADER - bool "The boot header" - depends on !BOOTLOADER_MCUBOOT - help - Enable data structures required by the boot ROM to boot the - application from an external flash device. - -if NXP_IMX_RT5XX_BOOT_HEADER - -choice BOOT_DEVICE - prompt "Boot device selection" - default BOOT_FLEXSPI_NOR - -config BOOT_FLEXSPI_NOR - bool "FlexSPI serial NOR" - -endchoice - -config FLASH_CONFIG_OFFSET - hex "Flash config data offset" - default 0x400 - help - The flash config offset provides the boot ROM with the on-board - flash type and parameters. The boot ROM requires a fixed flash config - offset for FlexSPI device. - -config IMAGE_VECTOR_TABLE_OFFSET - hex "Image vector table offset" - default 0x1000 - help - The Image Vector Table (IVT) provides the boot ROM with pointers to - the application entry point and device configuration data. The boot - ROM requires a fixed IVT offset for each type of boot device. - -config NXP_IMX_RT_ROM_RAMLOADER - depends on !FLASH_MCUX_FLEXSPI_XIP - # Required so that debugger will load image to correct offset - select BUILD_OUTPUT_HEX - bool "Create output image that IMX RT ROM can load from FlexSPI to ram" - help - Builds an output image that the IMX RT BootROM can load from the - FlexSPI boot device into RAM region. The image will be loaded - from FLEXSPI0 into the region specified by `zephyr,flash` node. - -# Setup LMA adjustment if using the RAMLOADER feature of ROM -FLASH_CHOSEN := zephyr,flash -FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) -FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1) -config BUILD_OUTPUT_ADJUST_LMA - default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER - -endif # NXP_IMX_RT5XX_BOOT_HEADER - - - -config IMXRT5XX_CODE_CACHE - bool "Code cache" - default y - help - Enable code cache for FlexSPI region at boot. If this Kconfig is - cleared, the CACHE64 controller will be disabled during SOC init - -choice FLEXCOMM0_CLK_SRC - prompt "Clock source for Flexcomm0" - default FLEXCOMM0_CLK_SRC_FRG - -config FLEXCOMM0_CLK_SRC_FRG - bool "FRG is source of Flexcomm0 clock" - -config FLEXCOMM0_CLK_SRC_FRO - bool "FRO_DIV4 is source of Flexcomm0 clock" - -endchoice - -choice MIPI_DPHY_CLK_SRC - prompt "Clock source for MIPI DPHY" - default MIPI_DPHY_CLK_SRC_AUX1_PLL - -config MIPI_DPHY_CLK_SRC_AUX1_PLL - bool "AUX1_PLL is source of MIPI_DPHY clock" - -config MIPI_DPHY_CLK_SRC_FRO - bool "FRO 192/96M is source of MIPI_DPHY clock" - -endchoice - -endif # SOC_SERIES_IMX_RT5XX diff --git a/soc/arm/nxp_imx/rt5xx/boot_header.ld b/soc/arm/nxp_imx/rt5xx/boot_header.ld deleted file mode 100644 index 43683f6c7be..00000000000 --- a/soc/arm/nxp_imx/rt5xx/boot_header.ld +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -. = CONFIG_FLASH_CONFIG_OFFSET; -KEEP(*(.flash_conf)) -. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; -KEEP(*(.boot_hdr.ivt)) diff --git a/soc/arm/nxp_imx/rt5xx/soc.c b/soc/arm/nxp_imx/rt5xx/soc.c deleted file mode 100644 index ca2a89cd553..00000000000 --- a/soc/arm/nxp_imx/rt5xx/soc.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * Copyright 2022-2023, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief System/hardware module for NXP RT5XX platform - * - * This module provides routines to initialize and support board-level - * hardware for the RT5XX platforms. - */ - -#include -#include -#include -#include -#include "fsl_power.h" -#include "fsl_clock.h" -#include - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP -#include "flash_clock_setup.h" -#endif - -#if CONFIG_USB_DC_NXP_LPCIP3511 -#include "usb_phy.h" -#include "usb.h" -#endif - -/* Board System oscillator settling time in us */ -#define BOARD_SYSOSC_SETTLING_US 100U -/* Board xtal frequency in Hz */ -#define BOARD_XTAL_SYS_CLK_HZ 24000000U -/* Core clock frequency: 198000000Hz */ -#define CLOCK_INIT_CORE_CLOCK 198000000U - -#define CTIMER_CLOCK_SOURCE(node_id) \ - TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source)) -#define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val) -#define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val) -#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id)); - -const clock_sys_pll_config_t g_sysPllConfig_clock_init = { - /* OSC clock */ - .sys_pll_src = kCLOCK_SysPllXtalIn, - /* Numerator of the SYSPLL0 fractional loop divider is 0 */ - .numerator = 0, - /* Denominator of the SYSPLL0 fractional loop divider is 1 */ - .denominator = 1, - /* Divide by 22 */ - .sys_pll_mult = kCLOCK_SysPllMult22 -}; - -const clock_audio_pll_config_t g_audioPllConfig_clock_init = { - /* OSC clock */ - .audio_pll_src = kCLOCK_AudioPllXtalIn, - /* Numerator of the Audio PLL fractional loop divider is 0 */ - .numerator = 5040, - /* Denominator of the Audio PLL fractional loop divider is 1 */ - .denominator = 27000, - /* Divide by 22 */ - .audio_pll_mult = kCLOCK_AudioPllMult22 -}; - -const clock_frg_clk_config_t g_frg0Config_clock_init = { - .num = 0, - .sfg_clock_src = kCLOCK_FrgPllDiv, - .divider = 255U, - .mult = 0 -}; - -const clock_frg_clk_config_t g_frg12Config_clock_init = { - .num = 12, - .sfg_clock_src = kCLOCK_FrgMainClk, - .divider = 255U, - .mult = 167 -}; - -#if CONFIG_USB_DC_NXP_LPCIP3511 -/* USB PHY condfiguration */ -#define BOARD_USB_PHY_D_CAL (0x0CU) -#define BOARD_USB_PHY_TXCAL45DP (0x06U) -#define BOARD_USB_PHY_TXCAL45DM (0x06U) -#endif - -/* System clock frequency. */ -extern uint32_t SystemCoreClock; -/* Main stack pointer */ -extern char z_main_stack[]; - -#ifdef CONFIG_NXP_IMX_RT5XX_BOOT_HEADER -extern char _flash_used[]; - -extern void z_arm_reset(void); -extern void z_arm_nmi(void); -extern void z_arm_hard_fault(void); -extern void z_arm_mpu_fault(void); -extern void z_arm_bus_fault(void); -extern void z_arm_usage_fault(void); -extern void z_arm_secure_fault(void); -extern void z_arm_svc(void); -extern void z_arm_debug_monitor(void); -extern void z_arm_pendsv(void); -extern void sys_clock_isr(void); -extern void z_arm_exc_spurious(void); - -__imx_boot_ivt_section void (* const image_vector_table[])(void) = { - (void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */ - z_arm_reset, /* 0x04 */ - z_arm_nmi, /* 0x08 */ - z_arm_hard_fault, /* 0x0C */ - z_arm_mpu_fault, /* 0x10 */ - z_arm_bus_fault, /* 0x14 */ - z_arm_usage_fault, /* 0x18 */ -#if defined(CONFIG_ARM_SECURE_FIRMWARE) - z_arm_secure_fault, /* 0x1C */ -#else - z_arm_exc_spurious, -#endif /* CONFIG_ARM_SECURE_FIRMWARE */ - (void (*)())_flash_used, /* 0x20, imageLength. */ - 0, /* 0x24, imageType (Plain Image) */ - 0, /* 0x28, authBlockOffset/crcChecksum */ - z_arm_svc, /* 0x2C */ - z_arm_debug_monitor, /* 0x30 */ - (void (*)())image_vector_table, /* 0x34, imageLoadAddress. */ - z_arm_pendsv, /* 0x38 */ -#if defined(CONFIG_SYS_CLOCK_EXISTS) && \ - defined(CONFIG_CORTEX_M_SYSTICK_INSTALL_ISR) - sys_clock_isr, /* 0x3C */ -#else - z_arm_exc_spurious, -#endif -}; -#endif /* CONFIG_NXP_IMX_RT5XX_BOOT_HEADER */ - -#if CONFIG_USB_DC_NXP_LPCIP3511 - -static void usb_device_clock_init(void) -{ - uint8_t usbClockDiv = 1; - uint32_t usbClockFreq; - usb_phy_config_struct_t phyConfig = { - BOARD_USB_PHY_D_CAL, - BOARD_USB_PHY_TXCAL45DP, - BOARD_USB_PHY_TXCAL45DM, - }; - - /* Make sure USBHS ram buffer and usb1 phy has power up */ - POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM); - POWER_ApplyPD(); - - RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_DEVICE_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_HOST_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_SRAM_RST_SHIFT_RSTn); - - /* enable usb ip clock */ - CLOCK_EnableUsbHs0DeviceClock(kOSC_CLK_to_USB_CLK, usbClockDiv); - /* save usb ip clock freq*/ - usbClockFreq = g_xtalFreq / usbClockDiv; - CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4); - /* enable usb ram clock */ - CLOCK_EnableClock(kCLOCK_UsbhsSram); - /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ - CLOCK_EnableUsbHs0PhyPllClock(kOSC_CLK_to_USB_CLK, usbClockFreq); - - /* USB PHY initialization */ - USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, BOARD_XTAL_SYS_CLK_HZ, &phyConfig); - -#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM) - for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++) { - ((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U; - } -#endif - - /* The following code should run after phy initialization and should wait - * some microseconds to make sure utmi clock valid - */ - /* enable usb1 host clock */ - CLOCK_EnableClock(kCLOCK_UsbhsHost); - /* Wait until host_needclk de-asserts */ - while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { - __ASM("nop"); - } - /* According to reference mannual, device mode setting has to be set by access - * usb host register - */ - USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; - /* disable usb1 host clock */ - CLOCK_DisableClock(kCLOCK_UsbhsHost); -} - -#endif - -void z_arm_platform_init(void) -{ -#ifndef CONFIG_NXP_IMX_RT5XX_BOOT_HEADER - /* - * If boot did not proceed using a boot header, we should not assume - * the core is in reset state. Disable the MPU and correctly - * set the stack pointer, since we are about to push to - * the stack when we call SystemInit - */ - /* Clear stack limit registers */ - __set_MSPLIM(0); - __set_PSPLIM(0); - /* Disable MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - /* Set stack pointer */ - __set_MSP((uint32_t)(z_main_stack + CONFIG_MAIN_STACK_SIZE)); -#endif /* !CONFIG_NXP_IMX_RT5XX_BOOT_HEADER */ - /* This is provided by the SDK */ - SystemInit(); -} - -/* Weak so that board can override with their own clock init routine. */ -void __weak rt5xx_clock_init(void) -{ - /* Configure LPOSC 1M */ - /* Power on LPOSC (1MHz) */ - POWER_DisablePD(kPDRUNCFG_PD_LPOSC); - /* Wait until LPOSC stable */ - CLOCK_EnableLpOscClk(); - - /* Configure FRO clock source */ - /* Power on FRO (192MHz or 96MHz) */ - POWER_DisablePD(kPDRUNCFG_PD_FFRO); - /* FRO_DIV1 is always enabled and used as Main clock during PLL update. */ - /* Enable all FRO outputs */ - CLOCK_EnableFroClk(kCLOCK_FroAllOutEn); - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP - /* - * Call function flexspi_clock_safe_config() to move FlexSPI clock to a stable - * clock source to avoid instruction/data fetch issue when updating PLL and Main - * clock if XIP(execute code on FLEXSPI memory). - */ - flexspi_clock_safe_config(); -#endif - - /* Let CPU run on FRO with divider 2 for safe switching. */ - CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2); - CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK); - - /* Configure SYSOSC clock source. */ - /* Power on SYSXTAL */ - POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); - /* Updated XTAL oscillator settling time */ - POWER_UpdateOscSettlingTime(BOARD_SYSOSC_SETTLING_US); - /* Enable system OSC */ - CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US); - /* Sets external XTAL OSC freq */ - CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ); - - /* Configure SysPLL0 clock source. */ - CLOCK_InitSysPll(&g_sysPllConfig_clock_init); - /* Enable MAIN PLL clock */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 24); - /* Enable AUX0 PLL clock */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - - /* Configure Audio PLL clock source. */ - CLOCK_InitAudioPll(&g_audioPllConfig_clock_init); - /* Enable Audio PLL clock */ - CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); - - /* Set SYSCPUAHBCLKDIV divider to value 2 */ - CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); - - /* Setup FRG0 clock */ - CLOCK_SetFRGClock(&g_frg0Config_clock_init); - /* Setup FRG12 clock */ - CLOCK_SetFRGClock(&g_frg12Config_clock_init); - - /* Set up clock selectors - Attach clocks to the peripheries. */ - /* Switch MAIN_CLK to MAIN_PLL */ - CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); - /* Switch SYSTICK_CLK to MAIN_CLK_DIV */ - CLOCK_AttachClk(kMAIN_CLK_DIV_to_SYSTICK_CLK); -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay) - #ifdef CONFIG_FLEXCOMM0_CLK_SRC_FRG - /* Switch FLEXCOMM0 to FRG */ - CLOCK_AttachClk(kFRG_to_FLEXCOMM0); - #elif defined(CONFIG_FLEXCOMM0_CLK_SRC_FRO) - CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM0); - #endif -#endif -#if CONFIG_USB_DC_NXP_LPCIP3511 - usb_device_clock_init(); -#endif - -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay) && CONFIG_I2S) - /* attach AUDIO PLL clock to FLEXCOMM1 (I2S1) */ - CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM1); -#endif -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay) && CONFIG_I2S) - /* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */ - CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay) - /* Switch FLEXCOMM4 to FRO_DIV4 */ - CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM4); -#endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(i3c0), nxp_mcux_i3c, okay) - /* Attach main clock to I3C, divider will be set in i3c_mcux.c */ - CLOCK_AttachClk(kMAIN_CLK_to_I3C_CLK); - CLOCK_AttachClk(kLPOSC_to_I3C_TC_CLK); -#endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(hs_spi1), nxp_lpc_spi, okay) - CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM16); -#endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm12), nxp_lpc_usart, okay) - /* Switch FLEXCOMM12 to FRG */ - CLOCK_AttachClk(kFRG_to_FLEXCOMM12); -#endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pmic_i2c), nxp_lpc_i2c, okay) - CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM15); -#endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lcdif), nxp_dcnano_lcdif, okay) && CONFIG_DISPLAY - POWER_DisablePD(kPDRUNCFG_APD_DCNANO_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_DCNANO_SRAM); - POWER_ApplyPD(); - - CLOCK_AttachClk(kAUX0_PLL_to_DCPIXEL_CLK); - /* Note- pixel clock follows formula - * (height + VSW + VFP + VBP) * (width + HSW + HFP + HBP) * frame rate. - * this means the clock divider will vary depending on - * the attached display. - * - * The root clock used here is the AUX0 PLL (PLL0 PFD2). - */ - CLOCK_SetClkDiv(kCLOCK_DivDcPixelClk, - ((CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / - DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), - clock_frequency)) + 1)); - - CLOCK_EnableClock(kCLOCK_DisplayCtrl); - RESET_ClearPeripheralReset(kDISP_CTRL_RST_SHIFT_RSTn); - - CLOCK_EnableClock(kCLOCK_AxiSwitch); - RESET_ClearPeripheralReset(kAXI_SWITCH_RST_SHIFT_RSTn); -#if defined(CONFIG_MEMC) && DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexspi2), \ - nxp_imx_flexspi, okay) - /* Enable write-through for FlexSPI1 space */ - CACHE64_POLSEL0->REG1_TOP = 0x27FFFC00U; - CACHE64_POLSEL0->POLSEL = 0x11U; -#endif -#endif - - /* Switch CLKOUT to FRO_DIV2 */ - CLOCK_AttachClk(kFRO_DIV2_to_CLKOUT); - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC - /* Make sure USDHC ram buffer has been power up*/ - POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM); - POWER_DisablePD(kPDRUNCFG_PD_LPOSC); - POWER_ApplyPD(); - - /* usdhc depend on 32K clock also */ - CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK); - CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK); - CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1); - CLOCK_EnableClock(kCLOCK_Sdio0); - RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(smartdma), okay) && CONFIG_DMA_MCUX_SMARTDMA - /* Power up SMARTDMA ram */ - POWER_DisablePD(kPDRUNCFG_APD_SMARTDMA_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_SMARTDMA_SRAM); - POWER_ApplyPD(); - - RESET_ClearPeripheralReset(kSMART_DMA_RST_SHIFT_RSTn); - CLOCK_EnableClock(kCLOCK_Smartdma); -#endif - - DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP) - - /* Set up dividers. */ - /* Set AUDIOPLLCLKDIV divider to value 15 */ - CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); - /* Set FRGPLLCLKDIV divider to value 11 */ - CLOCK_SetClkDiv(kCLOCK_DivPLLFRGClk, 11U); - /* Set SYSTICKFCLKDIV divider to value 2 */ - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 2U); - /* Set PFC0DIV divider to value 2 */ - CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); - /* Set PFC1DIV divider to value 4 */ - CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4U); - /* Set CLKOUTFCLKDIV divider to value 100 */ - CLOCK_SetClkDiv(kCLOCK_DivClockOut, 100U); - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP - /* - * Call function flexspi_setup_clock() to set user configured clock source/divider - * for FlexSPI. - */ - flexspi_setup_clock(FLEXSPI0, 0U, 2U); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexspi2), nxp_imx_flexspi, okay) - /* Power up FlexSPI1 SRAM */ - POWER_DisablePD(kPDRUNCFG_APD_FLEXSPI1_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_FLEXSPI1_SRAM); - POWER_ApplyPD(); - /* Setup clock frequency for FlexSPI1 */ - CLOCK_AttachClk(kMAIN_CLK_to_FLEXSPI1_CLK); - CLOCK_SetClkDiv(kCLOCK_DivFlexspi1Clk, 1); - /* Reset peripheral module */ - RESET_PeripheralReset(kFLEXSPI1_RST_SHIFT_RSTn); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpadc0), nxp_lpc_lpadc, okay) - SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK; - SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK; - RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); - CLOCK_AttachClk(kFRO_DIV4_to_ADC_CLK); - CLOCK_SetClkDiv(kCLOCK_DivAdcClk, 1); -#endif - -#if CONFIG_COUNTER_NXP_MRT - RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay) - /* Using the Audio PLL as input clock leads to better clock dividers - * for typical PCM sample rates ({8,16,24,32,48,96} kHz. - */ - /* DMIC source from audio pll, divider 8, 24.576M/8=3.072MHZ - * Select Audio PLL as clock source. This should produce a bit clock - * of 3.072MHZ - */ - CLOCK_AttachClk(kAUDIO_PLL_to_DMIC); - CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 8); - -#endif - - /* Set SystemCoreClock variable. */ - SystemCoreClock = CLOCK_INIT_CORE_CLOCK; - - /* Set main clock to FRO as deep sleep clock by default. */ - POWER_SetDeepSleepClock(kDeepSleepClk_Fro); -} - -#if CONFIG_MIPI_DSI -/* Weak so board can override this function */ -void __weak imxrt_pre_init_display_interface(void) -{ - /* Assert MIPI DPHY reset. */ - RESET_SetPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); - POWER_DisablePD(kPDRUNCFG_APD_MIPIDSI_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_MIPIDSI_SRAM); - POWER_DisablePD(kPDRUNCFG_PD_MIPIDSI); - POWER_ApplyPD(); - - /* RxClkEsc max 60MHz, TxClkEsc 12 to 20MHz. */ - CLOCK_AttachClk(kFRO_DIV1_to_MIPI_DPHYESC_CLK); - /* RxClkEsc = 192MHz / 4 = 48MHz. */ - CLOCK_SetClkDiv(kCLOCK_DivDphyEscRxClk, 4); - /* TxClkEsc = 192MHz / 4 / 3 = 16MHz. */ - CLOCK_SetClkDiv(kCLOCK_DivDphyEscTxClk, 3); - - /* - * The DPHY bit clock must be fast enough to send out the pixels, - * it should be larger than: - * - * (Pixel clock * bit per output pixel) / number of MIPI data lane - * - * DPHY supports up to 895.1MHz bit clock. - * We set the divider of the PFD3 output of the SYSPLL, which has a - * fixed multiplied of 18, and use this output frequency for the DPHY. - */ - -#ifdef CONFIG_MIPI_DPHY_CLK_SRC_AUX1_PLL - /* Note: AUX1 PLL clock is system pll clock * 18 / pfd. - * system pll clock is configured at 528MHz by default. - */ - CLOCK_AttachClk(kAUX1_PLL_to_MIPI_DPHY_CLK); - CLOCK_InitSysPfd(kCLOCK_Pfd3, - ((CLOCK_GetSysPllFreq() * 18ull) / - ((unsigned long long)(DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock))))); - CLOCK_SetClkDiv(kCLOCK_DivDphyClk, 1); -#elif defined(CONFIG_MIPI_DPHY_CLK_SRC_FRO) - CLOCK_AttachClk(kFRO_DIV1_to_MIPI_DPHY_CLK); - CLOCK_SetClkDiv(kCLOCK_DivDphyClk, - (CLK_FRO_CLK / DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock))); -#endif - /* Clear DSI control reset (Note that DPHY reset is cleared later)*/ - RESET_ClearPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn); -} - -void __weak imxrt_post_init_display_interface(void) -{ - /* Deassert MIPI DPHY reset. */ - RESET_ClearPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); -} - -void __weak imxrt_deinit_display_interface(void) -{ - /* Assert MIPI DPHY and DSI reset */ - RESET_SetPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); - RESET_SetPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn); - /* Remove clock from DPHY */ - CLOCK_AttachClk(kNONE_to_MIPI_DPHY_CLK); -} - - -#endif - -/** - * - * @brief Perform basic hardware initialization - * - * Initialize the interrupt controller device drivers. - * Also initialize the timer device driver, if required. - * - * @return 0 - */ -static int nxp_rt500_init(void) -{ - /* Initialize clocks with tool generated code */ - rt5xx_clock_init(); - -#ifndef CONFIG_IMXRT5XX_CODE_CACHE - CACHE64_DisableCache(CACHE64_CTRL0); -#endif - - /* Some ROM versions may have errata leaving these pins in a non-reset state, - * which can often cause power leakage on most expected board designs, - * restore the reset state here and leave the pin configuration up to board/user DT - */ - IOPCTL->PIO[1][15] = 0; - IOPCTL->PIO[3][28] = 0; - IOPCTL->PIO[3][29] = 0; - - return 0; -} - -SYS_INIT(nxp_rt500_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_imx/rt6xx/CMakeLists.txt b/soc/arm/nxp_imx/rt6xx/CMakeLists.txt deleted file mode 100644 index 57d5cb3fd04..00000000000 --- a/soc/arm/nxp_imx/rt6xx/CMakeLists.txt +++ /dev/null @@ -1,36 +0,0 @@ -# -# Copyright (c) 2020, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -zephyr_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_XIP - flash_clock_setup.c - ) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) - -zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) - -zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT6XX_BOOT_HEADER - ROM_START SORT_KEY 0 boot_header.ld) - -zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER - SECTIONS usb.ld) - -if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) - zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM) -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt685_cm33 b/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt685_cm33 deleted file mode 100644 index 47670d0b6ae..00000000000 --- a/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt685_cm33 +++ /dev/null @@ -1,32 +0,0 @@ -# NXP MIMXRT6XX platform configuration options - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT685S_CM33 - -config SOC - default "mimxrt685s_cm33" - -config I2S_MCUX_FLEXCOMM - select INIT_AUDIO_PLL - -if MCUX_OS_TIMER - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -endif # MCUX_OS_TIMER - -if CORTEX_M_SYSTICK - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 250105263 - -endif # CORTEX_M_SYSTICK - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -endif # SOC_MIMXRT685S_CM33 diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series b/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series deleted file mode 100644 index 7bcbc4e8e80..00000000000 --- a/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series +++ /dev/null @@ -1,81 +0,0 @@ -# i.MX RT6XX series configuration options - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX_RT6XX - -config SOC_SERIES - default "rt6xx" - -config ROM_START_OFFSET - default 0x1200 if NXP_IMX_RT6XX_BOOT_HEADER - -config NUM_IRQS - default 60 - -config ZTEST_NO_YIELD - default y if (ZTEST && PM) - - -# The base address is determined from the zephyr,flash node with the following -# precedence: -# FlexSPI base address (if flash node is on a FlexSPI bus) -# node reg property (used for memory regions such as SRAM) - -# Workaround for not being able to have commas in macro arguments - -DT_CHOSEN_Z_FLASH := zephyr,flash -DT_COMPAT_FLEXSPI := nxp,imx-flexspi - -# Macros to shorten Kconfig definitions -DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) -DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ - if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -# The RT6xx has no internal flash. If the flash node has a size property, -# use that over the reg property. This is used for the external flash -# present on the board. Otherwise, fallback to the reg property -config FLASH_SIZE - default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ - if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -if FLASH_MCUX_FLEXSPI_XIP - -# Avoid RWW hazards by defaulting logging to disabled -choice FLASH_LOG_LEVEL_CHOICE - default FLASH_LOG_LEVEL_OFF -endchoice - -choice MEMC_LOG_LEVEL_CHOICE - default MEMC_LOG_LEVEL_OFF -endchoice - -endif - -# -# MBEDTLS is larger but much faster than TinyCrypt so choose wisely -# -config MBEDTLS -#config TINYCRYPT - default y if CSPRNG_ENABLED - depends on ENTROPY_GENERATOR - -if MBEDTLS -# -# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than -# what the ztest_thread_stack defaults to. -# -config TEST_EXTRA_STACK_SIZE - int - default 1024 -endif # MBEDTLS - -source "soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt6*" - -endif # SOC_SERIES_MIMXRT6XX diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.series b/soc/arm/nxp_imx/rt6xx/Kconfig.series deleted file mode 100644 index bcbf86ff6bf..00000000000 --- a/soc/arm/nxp_imx/rt6xx/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# i.MX RT6XX Series - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX_RT6XX - bool "i.MX RT6XX Series Family MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_IMX - select CLOCK_CONTROL - select CODE_DATA_RELOCATION_SRAM if FLASH_MCUX_FLEXSPI_XIP - select PLATFORM_SPECIFIC_INIT - select HAS_PM - help - Enable support for i.MX RT6XX Series MCU series diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.soc b/soc/arm/nxp_imx/rt6xx/Kconfig.soc deleted file mode 100644 index e2222ab3214..00000000000 --- a/soc/arm/nxp_imx/rt6xx/Kconfig.soc +++ /dev/null @@ -1,136 +0,0 @@ -# i.MX RT6XX Series - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "i.MX RT6XX Series MCU Selection" - depends on SOC_SERIES_IMX_RT6XX - -config SOC_MIMXRT685S_CM33 - bool "SOC_MIMXRT685S M33" - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CPU_CORTEX_M_HAS_SYSTICK - select HAS_MCUX - select HAS_MCUX_SYSCON - select HAS_MCUX_FLEXCOMM - select HAS_MCUX_FLEXSPI - select HAS_MCUX_CACHE - select HAS_MCUX_LPC_DMA - select HAS_MCUX_LPADC - select HAS_MCUX_OS_TIMER - select HAS_MCUX_LPC_RTC - select HAS_MCUX_TRNG - select HAS_MCUX_SCTIMER - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select INIT_SYS_PLL - select HAS_MCUX_USB_LPCIP3511 - select HAS_MCUX_CTIMER -endchoice - -if SOC_SERIES_IMX_RT6XX - -config SOC_PART_NUMBER_MIMXRT685SFVKB - bool - -config SOC_PART_NUMBER_MIMXRT685SFFOB - bool - -config SOC_PART_NUMBER_MIMXRT685SFAWBR - bool - -config SOC_PART_NUMBER_IMX_RT6XX - string - default "MIMXRT685SFVKB" if SOC_PART_NUMBER_MIMXRT685SFVKB - default "MIMXRT685SFFOB" if SOC_PART_NUMBER_MIMXRT685SFFOB - default "MIMXRT685SFAWBR" if SOC_PART_NUMBER_MIMXRT685SFAWBR - - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -config INIT_SYS_PLL - bool "Initialize SYS PLL" - -config INIT_AUDIO_PLL - bool "Initialize Audio PLL" - -config XTAL_SYS_CLK_HZ - int "External oscillator frequency" - help - Set the external oscillator frequency in Hz. This should be set by the - board's defconfig. - -config SYSOSC_SETTLING_US - int "System oscillator settling time" - help - Set the board system oscillator settling time in us. This should be set by the - board's defconfig. - -menuconfig NXP_IMX_RT6XX_BOOT_HEADER - bool "Boot header" - depends on !BOOTLOADER_MCUBOOT - help - Enable data structures required by the boot ROM to boot the - application from an external flash device. - -if NXP_IMX_RT6XX_BOOT_HEADER - -choice BOOT_DEVICE - prompt "Boot device selection" - default BOOT_FLEXSPI_NOR - -config BOOT_FLEXSPI_NOR - bool "FlexSPI serial NOR" - -endchoice - -config FLASH_CONFIG_OFFSET - hex "Flash config data offset" - default 0x400 - help - The flash config offset provides the boot ROM with the on-board - flash type and parameters. The boot ROM requires a fixed flash config - offset for FlexSPI device. - -config IMAGE_VECTOR_TABLE_OFFSET - hex "Image vector table offset" - default 0x1000 - help - The Image Vector Table (IVT) provides the boot ROM with pointers to - the application entry point and device configuration data. The boot - ROM requires a fixed IVT offset for each type of boot device. - -config NXP_IMX_RT_ROM_RAMLOADER - depends on !FLASH_MCUX_FLEXSPI_XIP - # Required so that debugger will load image to correct offset - select BUILD_OUTPUT_HEX - bool "Create output image that IMX RT ROM can load from FlexSPI to ram" - help - Builds an output image that the IMX RT BootROM can load from the - FlexSPI boot device into RAM region. The image will be loaded - from FLEXSPI into the region specified by `zephyr,flash` node. - -# Setup LMA adjustment if using the RAMLOADER feature of ROM -FLASH_CHOSEN := zephyr,flash -FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) -FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1) -config BUILD_OUTPUT_ADJUST_LMA - default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER - -endif # NXP_IMX_RT6XX_BOOT_HEADER - -config IMXRT6XX_CODE_CACHE - bool "Code cache" - default y - help - Enable code cache for FlexSPI region at boot. If this Kconfig is - cleared, the CACHE64 controller will be disabled during SOC init - -endif # SOC_SERIES_IMX_RT6XX diff --git a/soc/arm/nxp_imx/rt6xx/boot_header.ld b/soc/arm/nxp_imx/rt6xx/boot_header.ld deleted file mode 100644 index b2b0eda70e3..00000000000 --- a/soc/arm/nxp_imx/rt6xx/boot_header.ld +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2020 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -. = CONFIG_FLASH_CONFIG_OFFSET; -KEEP(*(.flash_conf)) -. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; -KEEP(*(.boot_hdr.ivt)) diff --git a/soc/arm/nxp_imx/rt6xx/soc.c b/soc/arm/nxp_imx/rt6xx/soc.c deleted file mode 100644 index 165cf92e234..00000000000 --- a/soc/arm/nxp_imx/rt6xx/soc.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * Copyright 2020-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief System/hardware module for nxp_lpc55s69 platform - * - * This module provides routines to initialize and support board-level - * hardware for the nxp_lpc55s69 platform. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP -#include "flash_clock_setup.h" -#endif - -#if CONFIG_USB_DC_NXP_LPCIP3511 -#include "usb_phy.h" -#include "usb.h" -#endif - -/* Core clock frequency: 250105263Hz */ -#define CLOCK_INIT_CORE_CLOCK 250105263U - -#define SYSTEM_IS_XIP_FLEXSPI() \ - ((((uint32_t)nxp_rt600_init >= 0x08000000U) && \ - ((uint32_t)nxp_rt600_init < 0x10000000U)) || \ - (((uint32_t)nxp_rt600_init >= 0x18000000U) && \ - ((uint32_t)nxp_rt600_init < 0x20000000U))) - -#define CTIMER_CLOCK_SOURCE(node_id) \ - TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source)) -#define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val) -#define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val) -#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id)); - -#ifdef CONFIG_INIT_SYS_PLL -const clock_sys_pll_config_t g_sysPllConfig = { - .sys_pll_src = kCLOCK_SysPllXtalIn, - .numerator = 0, - .denominator = 1, - .sys_pll_mult = kCLOCK_SysPllMult22 -}; -#endif - -#ifdef CONFIG_INIT_AUDIO_PLL -const clock_audio_pll_config_t g_audioPllConfig = { - .audio_pll_src = kCLOCK_AudioPllXtalIn, - .numerator = 5040, - .denominator = 27000, - .audio_pll_mult = kCLOCK_AudioPllMult22 -}; -#endif - -#if CONFIG_USB_DC_NXP_LPCIP3511 -/* USB PHY condfiguration */ -#define BOARD_USB_PHY_D_CAL (0x0CU) -#define BOARD_USB_PHY_TXCAL45DP (0x06U) -#define BOARD_USB_PHY_TXCAL45DM (0x06U) -#endif - -/* System clock frequency. */ -extern uint32_t SystemCoreClock; -/* Main stack pointer */ -extern char z_main_stack[]; - -#ifdef CONFIG_NXP_IMX_RT6XX_BOOT_HEADER -extern char _flash_used[]; -extern void z_arm_reset(void); -extern void z_arm_nmi(void); -extern void z_arm_hard_fault(void); -extern void z_arm_mpu_fault(void); -extern void z_arm_bus_fault(void); -extern void z_arm_usage_fault(void); -extern void z_arm_secure_fault(void); -extern void z_arm_svc(void); -extern void z_arm_debug_monitor(void); -extern void z_arm_pendsv(void); -extern void sys_clock_isr(void); -extern void z_arm_exc_spurious(void); - -__imx_boot_ivt_section void (* const image_vector_table[])(void) = { - (void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */ - z_arm_reset, /* 0x04 */ - z_arm_nmi, /* 0x08 */ - z_arm_hard_fault, /* 0x0C */ - z_arm_mpu_fault, /* 0x10 */ - z_arm_bus_fault, /* 0x14 */ - z_arm_usage_fault, /* 0x18 */ -#if defined(CONFIG_ARM_SECURE_FIRMWARE) - z_arm_secure_fault, /* 0x1C */ -#else - z_arm_exc_spurious, -#endif /* CONFIG_ARM_SECURE_FIRMWARE */ - (void (*)())_flash_used, /* 0x20, imageLength. */ - 0, /* 0x24, imageType (Plain Image) */ - 0, /* 0x28, authBlockOffset/crcChecksum */ - z_arm_svc, /* 0x2C */ - z_arm_debug_monitor, /* 0x30 */ - (void (*)())image_vector_table, /* 0x34, imageLoadAddress. */ - z_arm_pendsv, /* 0x38 */ -#if defined(CONFIG_SYS_CLOCK_EXISTS) && \ - defined(CONFIG_CORTEX_M_SYSTICK_INSTALL_ISR) - sys_clock_isr, /* 0x3C */ -#else - z_arm_exc_spurious, -#endif -}; -#endif /* CONFIG_NXP_IMX_RT6XX_BOOT_HEADER */ - -#if CONFIG_USB_DC_NXP_LPCIP3511 - -static void usb_device_clock_init(void) -{ - uint8_t usbClockDiv = 1; - uint32_t usbClockFreq; - usb_phy_config_struct_t phyConfig = { - BOARD_USB_PHY_D_CAL, - BOARD_USB_PHY_TXCAL45DP, - BOARD_USB_PHY_TXCAL45DM, - }; - - /* enable USB IP clock */ - CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 5); - CLOCK_AttachClk(kXTALIN_CLK_to_USB_CLK); - CLOCK_SetClkDiv(kCLOCK_DivUsbHsFclk, usbClockDiv); - CLOCK_EnableUsbhsDeviceClock(); - RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_DEVICE_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_HOST_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_SRAM_RST_SHIFT_RSTn); - /*Make sure USBHS ram buffer has power up*/ - POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM); - POWER_ApplyPD(); - - /* save usb ip clock freq*/ - usbClockFreq = g_xtalFreq / usbClockDiv; - /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ - CLOCK_EnableUsbHs0PhyPllClock(kXTALIN_CLK_to_USB_CLK, usbClockFreq); - -#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM) - for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++) { - ((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U; - } -#endif - USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, CLK_XTAL_OSC_CLK, &phyConfig); - - /* the following code should run after phy initialization and - * should wait some microseconds to make sure utmi clock valid - */ - /* enable usb1 host clock */ - CLOCK_EnableClock(kCLOCK_UsbhsHost); - /* Wait until host_needclk de-asserts */ - while (SYSCTL0->USBCLKSTAT & SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_MASK) { - __ASM("nop"); - } - /* According to reference mannual, device mode setting has to be set by - * access usb host register - */ - USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; - /* disable usb1 host clock */ - CLOCK_DisableClock(kCLOCK_UsbhsHost); -} - -#endif - -/** - * @brief Initialize the system clock - */ -static ALWAYS_INLINE void clock_init(void) -{ -#ifdef CONFIG_SOC_MIMXRT685S_CM33 - /* Configure LPOSC clock*/ - POWER_DisablePD(kPDRUNCFG_PD_LPOSC); - /* Configure FFRO clock */ - POWER_DisablePD(kPDRUNCFG_PD_FFRO); - CLOCK_EnableFfroClk(kCLOCK_Ffro48M); - /* Configure SFRO clock */ - POWER_DisablePD(kPDRUNCFG_PD_SFRO); - CLOCK_EnableSfroClk(); - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP - /* - * Call function flexspi_clock_safe_config() to move FlexSPI clock to a stable - * clock source to avoid instruction/data fetch issue when updating PLL and Main - * clock if XIP(execute code on FLEXSPI memory). - */ - flexspi_clock_safe_config(); -#endif - - /* Let CPU run on FFRO for safe switching. */ - CLOCK_AttachClk(kFFRO_to_MAIN_CLK); - - /* Configure SYSOSC clock source */ - POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); - POWER_UpdateOscSettlingTime(CONFIG_SYSOSC_SETTLING_US); - CLOCK_EnableSysOscClk(true, true, CONFIG_SYSOSC_SETTLING_US); - CLOCK_SetXtalFreq(CONFIG_XTAL_SYS_CLK_HZ); - -#ifdef CONFIG_INIT_SYS_PLL - /* Configure SysPLL0 clock source */ - CLOCK_InitSysPll(&g_sysPllConfig); - CLOCK_InitSysPfd(kCLOCK_Pfd0, 19); - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); -#endif - -#ifdef CONFIG_INIT_AUDIO_PLL - /* Configure Audio PLL clock source */ - CLOCK_InitAudioPll(&g_audioPllConfig); - CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); - CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); -#endif - - /* Set SYSCPUAHBCLKDIV divider to value 2 */ - CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); - - /* Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); - - /* Set up dividers */ - /* Set PFC0DIV divider to value 2 */ - CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); - /* Set FRGPLLCLKDIV divider to value 12 */ - CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U); - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay) - CLOCK_AttachClk(kSFRO_to_FLEXCOMM0); -#endif - -#if CONFIG_USB_DC_NXP_LPCIP3511 - usb_device_clock_init(); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2c, okay) - CLOCK_AttachClk(kSFRO_to_FLEXCOMM2); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pmic_i2c), nxp_lpc_i2c, okay) - CLOCK_AttachClk(kFFRO_to_FLEXCOMM15); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_usart, okay) - CLOCK_AttachClk(kSFRO_to_FLEXCOMM4); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_spi, okay) - CLOCK_AttachClk(kFFRO_to_FLEXCOMM5); -#endif - -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay)) - /* attach AUDIO PLL clock to FLEXCOMM1 (I2S1) */ - CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM1); -#endif -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay)) - /* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */ - CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3); -#endif - -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt0), nxp_lpc_wwdt, okay)) - CLOCK_AttachClk(kLPOSC_to_WDT0_CLK); -#else - /* Allowed to select none if not being used for watchdog to - * reduce power - */ - CLOCK_AttachClk(kNONE_to_WDT0_CLK); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC - /* Make sure USDHC ram buffer has been power up*/ - POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM); - POWER_DisablePD(kPDRUNCFG_PD_LPOSC); - POWER_ApplyPD(); - - /* usdhc depend on 32K clock also */ - CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK); - CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK); - CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1); - CLOCK_EnableClock(kCLOCK_Sdio0); - RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn); -#endif - - DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP) - DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP) - -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(i3c0), nxp_mcux_i3c, okay)) - CLOCK_AttachClk(kFFRO_to_I3C_CLK); - CLOCK_AttachClk(kLPOSC_to_I3C_TC_CLK); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpadc0), nxp_lpc_lpadc, okay) - SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK; - SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK; - RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); - CLOCK_AttachClk(kSFRO_to_ADC_CLK); - CLOCK_SetClkDiv(kCLOCK_DivAdcClk, DT_PROP(DT_NODELABEL(lpadc0), clk_divider)); -#endif - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP - /* - * Call function flexspi_setup_clock() to set user configured clock source/divider - * for FlexSPI. - */ - flexspi_setup_clock(FLEXSPI, 1U, 9U); -#endif - -#if CONFIG_COUNTER_NXP_MRT - RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn); -#endif - - /* Set SystemCoreClock variable. */ - SystemCoreClock = CLOCK_INIT_CORE_CLOCK; - -#endif /* CONFIG_SOC_MIMXRT685S_CM33 */ -} - -#if (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC) - -void imxrt_usdhc_pinmux(uint16_t nusdhc, bool init, - uint32_t speed, uint32_t strength) -{ - -} - -void imxrt_usdhc_dat3_pull(bool pullup) -{ - -} -#endif - -/** - * - * @brief Perform basic hardware initialization - * - * Initialize the interrupt controller device drivers. - * Also initialize the timer device driver, if required. - * - * @return 0 - */ - -static int nxp_rt600_init(void) -{ - /* Initialize clock */ - clock_init(); - -#ifndef CONFIG_IMXRT6XX_CODE_CACHE - CACHE64_DisableCache(CACHE64); -#endif - - return 0; -} - -#ifdef CONFIG_PLATFORM_SPECIFIC_INIT - -void z_arm_platform_init(void) -{ -#ifndef CONFIG_NXP_IMX_RT6XX_BOOT_HEADER - /* - * If boot did not proceed using a boot header, we should not assume - * the core is in reset state. Disable the MPU and correctly - * set the stack pointer, since we are about to push to - * the stack when we call SystemInit - */ - /* Clear stack limit registers */ - __set_MSPLIM(0); - __set_PSPLIM(0); - /* Disable MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - /* Set stack pointer */ - __set_MSP((uint32_t)(z_main_stack + CONFIG_MAIN_STACK_SIZE)); -#endif /* !CONFIG_NXP_IMX_RT5XX_BOOT_HEADER */ - /* This is provided by the SDK */ - SystemInit(); -} - -#endif - -SYS_INIT(nxp_rt600_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_kinetis/Kconfig b/soc/arm/nxp_kinetis/Kconfig deleted file mode 100644 index 251bc13ef91..00000000000 --- a/soc/arm/nxp_kinetis/Kconfig +++ /dev/null @@ -1,168 +0,0 @@ -# Copyright (c) 2016 Intel Corporation -# Copyright (c) 2016, Freescale Semiconductor, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_KINETIS - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_KINETIS - -config SOC_FAMILY - string - default "nxp_kinetis" - -source "soc/arm/nxp_kinetis/*/Kconfig.soc" - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_KINETIS_K2X if SOC_SERIES_KINETIS_K2X - default SOC_PART_NUMBER_KINETIS_K6X if SOC_SERIES_KINETIS_K6X - default SOC_PART_NUMBER_KINETIS_K8X if SOC_SERIES_KINETIS_K8X - default SOC_PART_NUMBER_KINETIS_KWX if SOC_SERIES_KINETIS_KWX - default SOC_PART_NUMBER_KINETIS_KL2X if SOC_SERIES_KINETIS_KL2X - default SOC_PART_NUMBER_KINETIS_KE1XF if SOC_SERIES_KINETIS_KE1XF - default SOC_PART_NUMBER_KINETIS_KV5X if SOC_SERIES_KINETIS_KV5X - -config HAS_OSC - bool - help - Set if the oscillator (OSC) module is present in the SoC. - -config HAS_MCG - bool - help - Set if the multipurpose clock generator (MCG) module is present in the SoC. - -if HAS_OSC - -choice - prompt "Oscillator Mode Selection" - default OSC_EXTERNAL - -config OSC_EXTERNAL - bool "External reference clock" - help - Set this option to use the oscillator in external reference clock mode. - -config OSC_LOW_POWER - bool "Low power oscillator" - help - Set this option to use the oscillator in low-power mode. - -config OSC_HIGH_GAIN - bool "High gain oscillator" - help - Set this option to use the oscillator in high-gain mode. - -endchoice - -config OSC_XTAL0_FREQ - int "External oscillator frequency" - help - Set the external oscillator frequency in Hz. This should be set by the - board's defconfig. - -endif # HAS_OSC - -if HAS_MCG - -config MCG_PRDIV0 - hex "PLL external reference divider" - range 0 0x18 - default 0 - help - Selects the amount to divide down the external reference clock for the PLL. - The resulting frequency must be in the range of 2 MHz to 4 MHz. - -config MCG_VDIV0 - hex "VCO 0 divider" - range 0 0x1F - default 0 - help - Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits - establish the multiplication factor (M) applied to the reference clock - frequency. - -config MCG_FCRDIV - int "Fast internal reference clock divider" - range 0 7 - default 1 - help - Selects the amount to divide down the fast internal reference clock. The - resulting frequency must be in the range 31.25 kHz to 4 MHz. - -config MCG_FRDIV - int "FLL external reference divider" - range 0 7 - default 0 - help - Selects the amount to divide down the external reference clock for the - FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 - kHz. - -endif # HAS_MCG - -config KINETIS_FLASH_CONFIG - bool "Kinetis flash configuration field" - default y if XIP && !BOOTLOADER_MCUBOOT - help - Include the 16-byte flash configuration field that stores default - protection settings (loaded on reset) and security information that - allows the MCU to restrict access to the FTFx module. - -if KINETIS_FLASH_CONFIG - -config KINETIS_FLASH_CONFIG_OFFSET - hex "Kinetis flash configuration field offset" - default 0x400 - -config KINETIS_FLASH_CONFIG_FSEC - hex "Flash security byte (FSEC)" - range 0 0xff - default 0xfe - help - Configures the reset value of the FSEC register, which includes - backdoor key access, mass erase, factory access, and flash security - options. - -config KINETIS_FLASH_CONFIG_FOPT - hex "Flash nonvolatile option byte (FOPT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FOPT register, which includes boot, - NMI, and EzPort options. - -config KINETIS_FLASH_CONFIG_FEPROT - hex "EEPROM protection byte (FEPROT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FEPROT register for FlexNVM - devices. For program flash only devices, this byte is reserved. - -config KINETIS_FLASH_CONFIG_FDPROT - hex "Data flash protection byte (FDPROT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FDPROT register for FlexNVM - devices. For program flash only devices, this byte is reserved. - -endif # KINETIS_FLASH_CONFIG - -config WDOG_ENABLE_AT_BOOT - bool "Keep watchdog timer enabled at boot" - help - Leave SOC watchdog timer enabled at boot. The specific timeout - and clock configuration of the watchdog at boot is SOC dependent. - Note: if the watchdog timer is enabled at boot, the user will - need to configure the watchdog using z_arm_watchdog_init, as - the SOC requires watchdog configuration before initial expiration - -# Enable watchdog configuration function if watchdog is left enabled at boot -config WDOG_INIT - bool - default WDOG_ENABLE_AT_BOOT - -endif # SOC_FAMILY_KINETIS diff --git a/soc/arm/nxp_kinetis/Kconfig.defconfig b/soc/arm/nxp_kinetis/Kconfig.defconfig deleted file mode 100644 index 1a117657c05..00000000000 --- a/soc/arm/nxp_kinetis/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SERIAL_INIT_PRIORITY - default 55 - depends on SERIAL - -config ADC_INIT_PRIORITY - default 80 if ADC_MCUX_ADC16_ENABLE_EDMA - depends on ADC - -source "soc/arm/nxp_kinetis/*/Kconfig.defconfig.series" diff --git a/soc/arm/nxp_kinetis/Kconfig.soc b/soc/arm/nxp_kinetis/Kconfig.soc deleted file mode 100644 index 0a207260af3..00000000000 --- a/soc/arm/nxp_kinetis/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2016 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_kinetis/*/Kconfig.series" diff --git a/soc/arm/nxp_kinetis/k2x/CMakeLists.txt b/soc/arm/nxp_kinetis/k2x/CMakeLists.txt deleted file mode 100644 index 8ff38d089ce..00000000000 --- a/soc/arm/nxp_kinetis/k2x/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2018 Prevas A/S - -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -if(DEFINED CONFIG_ARM_MPU AND DEFINED CONFIG_CPU_HAS_NXP_MPU) - # MK22F12 series MCUs have NXP MPU - zephyr_sources(nxp_mpu_regions.c) -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22f12 b/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22f12 deleted file mode 100644 index 01f0ec78f2f..00000000000 --- a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22f12 +++ /dev/null @@ -1,17 +0,0 @@ -# FSL FRDM K22F platform configuration options - -# Copyright (c) 2018 Prevas A/S -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MK22F51212 - -config SOC - default "mk22f51212" - -config GPIO - default y - -config NUM_IRQS - default 74 - -endif # SOC_MK22F12 diff --git a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22fx12 b/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22fx12 deleted file mode 100644 index 963fdf87162..00000000000 --- a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22fx12 +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2023 Daniel DeGrasse -# SPDX-License-Identifier: Apache-2.0 - -# Kinetis MK22FX12 configuration options - -if SOC_MK22F12 - -config SOC - default "mk22f12" - -config NUM_IRQS - default 81 - -config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - default y - -endif # SOC_MK22F12 diff --git a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.series deleted file mode 100644 index 254fd251014..00000000000 --- a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Kinetis K2x series configuration options - -# Copyright (c) 2018 Prevas A/S -# Copyright (c) 2019 Thomas Burdick - -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_KINETIS_K2X - -config SOC_SERIES - default "k2x" - -source "soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk*" - -endif # SOC_SERIES_KINETIS_K2X diff --git a/soc/arm/nxp_kinetis/k2x/Kconfig.series b/soc/arm/nxp_kinetis/k2x/Kconfig.series deleted file mode 100644 index be22027b46a..00000000000 --- a/soc/arm/nxp_kinetis/k2x/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Kinetis K2X MCU line - -# Copyright (c) 2018 Prevas A/S -# Copyright (c) 2019 Thomas Burdick - -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_KINETIS_K2X - bool "Kinetis K2x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_KINETIS - select CLOCK_CONTROL - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis K2x MCU series diff --git a/soc/arm/nxp_kinetis/k2x/Kconfig.soc b/soc/arm/nxp_kinetis/k2x/Kconfig.soc deleted file mode 100644 index 0535ac2e684..00000000000 --- a/soc/arm/nxp_kinetis/k2x/Kconfig.soc +++ /dev/null @@ -1,69 +0,0 @@ -# Kinetis K2X MCU line - -# Copyright (c) 2018 Prevas A/S -# Copyright (c) 2019 Thomas Burdick - -# -# SPDX-License-Identifier: Apache-2.0 -# - -choice - prompt "Kinetis K2x MCU Selection" - depends on SOC_SERIES_KINETIS_K2X - -config SOC_MK22F51212 - bool "SOC_MK22F51212" - select HAS_MCUX - select HAS_MCUX_SMC - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select CPU_HAS_FPU - select HAS_MCUX_DAC - select HAS_MCUX_RCM - -# Note- the MK22F12 SKU is a legacy SOC, no longer officially supported by -# NXP's MCUX SDK, and not recommended for new designs. -config SOC_MK22F12 - bool "SOC_MK22F12" - select HAS_MCUX - select HAS_MCUX_SMC - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select CPU_HAS_FPU - select HAS_MCUX_DAC - select HAS_MCUX_RCM - select CPU_HAS_NXP_MPU - -endchoice - -if SOC_SERIES_KINETIS_K2X - -config SOC_PART_NUMBER_MK22FN512VLH12 - bool - -config SOC_PART_NUMBER_MK22FX512AVLK12 - bool - -config SOC_PART_NUMBER_MK22FX512VLQ12 - bool - -config SOC_PART_NUMBER_KINETIS_K2X - string - default "MK22FN512VLH12" if SOC_PART_NUMBER_MK22FN512VLH12 - default "MK22FX512VLQ12" if SOC_PART_NUMBER_MK22FX512VLQ12 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_KINETIS_K2X diff --git a/soc/arm/nxp_kinetis/k6x/CMakeLists.txt b/soc/arm/nxp_kinetis/k6x/CMakeLists.txt deleted file mode 100644 index 8cf7a11f62e..00000000000 --- a/soc/arm/nxp_kinetis/k6x/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) -zephyr_sources_ifdef( - CONFIG_ARM_MPU - nxp_mpu_regions.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk64f12 b/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk64f12 deleted file mode 100644 index f8c2c7db12e..00000000000 --- a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk64f12 +++ /dev/null @@ -1,21 +0,0 @@ -# FSL FRDM K64F platform configuration options - -# Copyright (c) 2014-2016 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MK64F12 - -config SOC - default "mk64f12" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 86 - -config GPIO - default y - -config SPI - default n - -endif # SOC_MK64F12 diff --git a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk66f18 b/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk66f18 deleted file mode 100644 index 3aa88788009..00000000000 --- a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk66f18 +++ /dev/null @@ -1,18 +0,0 @@ -# FSL SEGGER K66F platform configuration options - -# Copyright (c) 2020 DENX Software Engineering GmbH, 2021 Electromaticus LLC, 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MK66F18 - -config SOC - default "mk66f18" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 100 - -config GPIO - default y - -endif # SOC_MK66F18 diff --git a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.series deleted file mode 100644 index 4593295961c..00000000000 --- a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Kinetis K6x series configuration options - -# Copyright (c) 2014-2016 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_K6X - -config SOC_SERIES - default "k6x" - -config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - default y - -source "soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk*" - -endif # SOC_SERIES_KINETIS_K6X diff --git a/soc/arm/nxp_kinetis/k6x/Kconfig.series b/soc/arm/nxp_kinetis/k6x/Kconfig.series deleted file mode 100644 index df24b5d600e..00000000000 --- a/soc/arm/nxp_kinetis/k6x/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Kinetis K6X MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_K6X - bool "Kinetis K6x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_KINETIS - select CPU_HAS_NXP_MPU - select HAS_MCUX_PIT - select CLOCK_CONTROL - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis K6x MCU series diff --git a/soc/arm/nxp_kinetis/k6x/Kconfig.soc b/soc/arm/nxp_kinetis/k6x/Kconfig.soc deleted file mode 100644 index 42a0cb6891b..00000000000 --- a/soc/arm/nxp_kinetis/k6x/Kconfig.soc +++ /dev/null @@ -1,110 +0,0 @@ -# Kinetis K6X MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis K6x MCU Selection" - depends on SOC_SERIES_KINETIS_K6X - -config SOC_MK64F12 - bool "SOC_MK64F12" - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_ENET - select HAS_MCUX_FLEXCAN - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select CPU_HAS_FPU - select HAS_MCUX_RTC - select HAS_MCUX_DAC - select HAS_MCUX_EDMA - select HAS_MCUX_RCM - -config SOC_MK66F18 - bool "SOC_MK66F18" - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_ENET - select HAS_MCUX_FLEXCAN - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select CPU_HAS_FPU - select HAS_MCUX_RTC - select HAS_MCUX_DAC - select HAS_MCUX_EDMA - select HAS_MCUX_RCM - select HAS_MCUX_LPUART - -endchoice - -if SOC_SERIES_KINETIS_K6X - -config SOC_PART_NUMBER_MK64FN1M0CAJ12 - bool - -config SOC_PART_NUMBER_MK64FN1M0VDC12 - bool - -config SOC_PART_NUMBER_MK64FN1M0VLL12 - bool - -config SOC_PART_NUMBER_MK64FN1M0VLQ12 - bool - -config SOC_PART_NUMBER_MK64FN1M0VMD12 - bool - -config SOC_PART_NUMBER_MK64FX512VDC12 - bool - -config SOC_PART_NUMBER_MK64FX512VLL12 - bool - -config SOC_PART_NUMBER_MK64FX512VLQ12 - bool - -config SOC_PART_NUMBER_MK64FX512VMD12 - bool - -config SOC_PART_NUMBER_MK66FN2M0VMD18 - bool - -config SOC_PART_NUMBER_MK66FN2M0VLQ18 - bool - -config SOC_PART_NUMBER_KINETIS_K6X - string - default "MK64FN1M0CAJ12" if SOC_PART_NUMBER_MK64FN1M0CAJ12 - default "MK64FN1M0VDC12" if SOC_PART_NUMBER_MK64FN1M0VDC12 - default "MK64FN1M0VLL12" if SOC_PART_NUMBER_MK64FN1M0VLL12 - default "MK64FN1M0VLQ12" if SOC_PART_NUMBER_MK64FN1M0VLQ12 - default "MK64FN1M0VMD12" if SOC_PART_NUMBER_MK64FN1M0VMD12 - default "MK64FX512VDC12" if SOC_PART_NUMBER_MK64FX512VDC12 - default "MK64FX512VLL12" if SOC_PART_NUMBER_MK64FX512VLL12 - default "MK64FX512VLQ12" if SOC_PART_NUMBER_MK64FX512VLQ12 - default "MK64FX512VMD12" if SOC_PART_NUMBER_MK64FX512VMD12 - default "MK66FN2M0VMD18" if SOC_PART_NUMBER_MK66FN2M0VMD18 - default "MK66FN2M0VLQ18" if SOC_PART_NUMBER_MK66FN2M0VLQ18 - - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config K6X_HSRUN - bool "High Speed RUN mode" - depends on SOC_MK66F18 - default y - help - This options enables support for High Speed RUN mode on K66F SoC. - -endif # SOC_SERIES_KINETIS_K6X diff --git a/soc/arm/nxp_kinetis/k8x/CMakeLists.txt b/soc/arm/nxp_kinetis/k8x/CMakeLists.txt deleted file mode 100644 index 8cf7a11f62e..00000000000 --- a/soc/arm/nxp_kinetis/k8x/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) -zephyr_sources_ifdef( - CONFIG_ARM_MPU - nxp_mpu_regions.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk80f25615 b/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk80f25615 deleted file mode 100644 index 4dfa011ce26..00000000000 --- a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk80f25615 +++ /dev/null @@ -1,8 +0,0 @@ -# Kinetis K80F25615 configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "mk80f25615" - depends on SOC_MK80F25615 diff --git a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk82f25615 b/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk82f25615 deleted file mode 100644 index 4a7a81d73cb..00000000000 --- a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk82f25615 +++ /dev/null @@ -1,8 +0,0 @@ -# Kinetis K82F25615 configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "mk82f25615" - depends on SOC_MK82F25615 diff --git a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.series deleted file mode 100644 index 3f300ac61dc..00000000000 --- a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Kinetis K8x series configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_K8X - -config SOC_SERIES - default "k8x" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 106 - -config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - default y - -config KINETIS_FLASH_CONFIG_FOPT - default 0x3f - depends on KINETIS_FLASH_CONFIG - -config GPIO - default y - -source "soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk*" - -endif # SOC_SERIES_KINETIS_K8X diff --git a/soc/arm/nxp_kinetis/k8x/Kconfig.series b/soc/arm/nxp_kinetis/k8x/Kconfig.series deleted file mode 100644 index 537a65bf117..00000000000 --- a/soc/arm/nxp_kinetis/k8x/Kconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Kinetis K8x series MCU - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_K8X - bool "Kinetis K8x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_KINETIS - select CPU_HAS_NXP_MPU - select CPU_HAS_FPU - select CLOCK_CONTROL - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_LPUART - select HAS_MCUX_PIT - select HAS_MCUX_RTC - select HAS_MCUX_SIM - select HAS_MCUX_TRNG - select HAS_OSC - select HAS_MCG - select HAS_MCUX_EDMA - select HAS_MCUX_PIT - select HAS_MCUX_RCM - select HAS_MCUX_CACHE - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis K8x MCU series diff --git a/soc/arm/nxp_kinetis/k8x/Kconfig.soc b/soc/arm/nxp_kinetis/k8x/Kconfig.soc deleted file mode 100644 index b7127ad1bd4..00000000000 --- a/soc/arm/nxp_kinetis/k8x/Kconfig.soc +++ /dev/null @@ -1,72 +0,0 @@ -# Kinetis K8x series MCU - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis K8x MCU Selection" - depends on SOC_SERIES_KINETIS_K8X - -config SOC_MK80F25615 - bool "MK80F25615" - -config SOC_MK82F25615 - bool "MK82F25615" - -endchoice - -if SOC_SERIES_KINETIS_K8X - -config SOC_PART_NUMBER_MK80FN256VDC15 - bool - -config SOC_PART_NUMBER_MK80FN256VLL15 - bool - -config SOC_PART_NUMBER_MK82FN256VDC15 - bool - -config SOC_PART_NUMBER_MK82FN256VLL15 - bool - -config SOC_PART_NUMBER_KINETIS_K8X - string - default "MK80FN256VDC15" if SOC_PART_NUMBER_MK80FN256VDC15 - default "MK80FN256VLL15" if SOC_PART_NUMBER_MK80FN256VLL15 - default "MK82FN256VDC15" if SOC_PART_NUMBER_MK82FN256VDC15 - default "MK82FN256VLL15" if SOC_PART_NUMBER_MK82FN256VLL15 - help - This string holds the full part number of the SoC. It is a - hidden option that you should not set directly. The part - number selection choice defines the default value for this - string. - -config K8X_CORE_CLOCK_DIVIDER - int "Freescale K8x core clock divider" - default 1 - help - This option specifies the divide value for the K8x processor core clock - from the system clock. - -config K8X_BUS_CLOCK_DIVIDER - int "Freescale K8x bus clock divider" - default 2 - help - This option specifies the divide value for the K8x bus clock from the - system clock. - -config K8X_FLEXBUS_CLOCK_DIVIDER - int "Freescale K8x FlexBus clock divider" - default 2 - help - This option specifies the divide value for the K8x FlexBus clock from the - system clock. - -config K8X_FLASH_CLOCK_DIVIDER - int "Freescale K8x flash clock divider" - default 5 - help - This option specifies the divide value for the K8x flash clock from the - system clock. - -endif # SOC_SERIES_KINETIS_K8X diff --git a/soc/arm/nxp_kinetis/ke1xf/CMakeLists.txt b/soc/arm/nxp_kinetis/ke1xf/CMakeLists.txt deleted file mode 100644 index ccbf2208d5a..00000000000 --- a/soc/arm/nxp_kinetis/ke1xf/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) -zephyr_sources_ifdef( - CONFIG_ARM_MPU - nxp_mpu_regions.c - ) -zephyr_sources_ifdef( - CONFIG_PM - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke14f16 b/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke14f16 deleted file mode 100644 index 801bfbf158a..00000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke14f16 +++ /dev/null @@ -1,8 +0,0 @@ -# Kinetis KE14F16 configuration options - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "mke14f16" - depends on SOC_MKE14F16 diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke16f16 b/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke16f16 deleted file mode 100644 index 9c53760952b..00000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke16f16 +++ /dev/null @@ -1,11 +0,0 @@ -# Kinetis KE16F16 configuration options - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKE16F16 - -config SOC - default "mke16f16" - -endif # SOC_MKE16F16 diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke18f16 b/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke18f16 deleted file mode 100644 index 555839e3586..00000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke18f16 +++ /dev/null @@ -1,11 +0,0 @@ -# Kinetis KE18F16 configuration options - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKE18F16 - -config SOC - default "mke18f16" - -endif # SOC_MKE18F16 diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.series deleted file mode 100644 index 28fb7e44b68..00000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.series +++ /dev/null @@ -1,41 +0,0 @@ -# Kinetis KE1xF series configuration options - -# Copyright (c) 2019-2021 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_KE1XF - -config SOC_SERIES - default "ke1xf" - -config MCUX_LPTMR_TIMER - default y if PM - -config CORTEX_M_SYSTICK - default n if MCUX_LPTMR_TIMER - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK - default $(dt_node_int_prop_int,/soc/lptmr@40040000,clock-frequency) if MCUX_LPTMR_TIMER - -config NUM_IRQS - # must be >= the highest interrupt number used - default 91 - -config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - default y - -config KINETIS_FLASH_CONFIG_FOPT - default 0x7d - depends on KINETIS_FLASH_CONFIG - -config PWM_MCUX_PWT - default y - depends on PWM_CAPTURE - -config GPIO - default y - -source "soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke*" - -endif # SOC_SERIES_KINETIS_KE1XF diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.series b/soc/arm/nxp_kinetis/ke1xf/Kconfig.series deleted file mode 100644 index 640bc4ec8fd..00000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.series +++ /dev/null @@ -1,37 +0,0 @@ -# Kinetis KE1xF series MCU - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_KE1XF - bool "Kinetis KE1xF Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_KINETIS - select CPU_HAS_NXP_MPU - select CPU_HAS_FPU - select CLOCK_CONTROL - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_FTFX - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_PCC - select HAS_MCUX_RTC - select HAS_MCUX_SIM - select HAS_MCUX_ADC12 - select HAS_MCUX_SCG - select HAS_MCUX_WDOG32 - select HAS_MCUX_FTM - select HAS_MCUX_LPTMR - select HAS_MCUX_DAC32 - select HAS_MCUX_EDMA - select HAS_MCUX_ACMP - select HAS_MCUX_PWT - select HAS_MCUX_RCM - select PLATFORM_SPECIFIC_INIT - select HAS_PM - help - Enable support for Kinetis KE1xF MCU series diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.soc b/soc/arm/nxp_kinetis/ke1xf/Kconfig.soc deleted file mode 100644 index dec70f364f0..00000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.soc +++ /dev/null @@ -1,103 +0,0 @@ -# Kinetis KE1xF MCU line - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis KE1xF MCU Selection" - depends on SOC_SERIES_KINETIS_KE1XF - -config SOC_MKE14F16 - bool "MKE14F16" - -config SOC_MKE16F16 - bool "MKE16F16" - select HAS_MCUX_FLEXCAN - -config SOC_MKE18F16 - bool "MKE18F16" - select HAS_MCUX_FLEXCAN - -endchoice - -if SOC_SERIES_KINETIS_KE1XF - -config SOC_PART_NUMBER_MKE14F256VLH16 - bool - -config SOC_PART_NUMBER_MKE14F256VLL16 - bool - -config SOC_PART_NUMBER_MKE14F512VLH16 - bool - -config SOC_PART_NUMBER_MKE14F512VLL16 - bool - -config SOC_PART_NUMBER_MKE16F256VLH16 - bool - -config SOC_PART_NUMBER_MKE16F256VLL16 - bool - -config SOC_PART_NUMBER_MKE16F512VLH16 - bool - -config SOC_PART_NUMBER_MKE16F512VLL16 - bool - -config SOC_PART_NUMBER_MKE18F256VLH16 - bool - -config SOC_PART_NUMBER_MKE18F256VLL16 - bool - -config SOC_PART_NUMBER_MKE18F512VLH16 - bool - -config SOC_PART_NUMBER_MKE18F512VLL16 - bool - -config SOC_PART_NUMBER_KINETIS_KE1XF - string - default "MKE14F256VLH16" if SOC_PART_NUMBER_MKE14F256VLH16 - default "MKE14F256VLL16" if SOC_PART_NUMBER_MKE14F256VLL16 - default "MKE14F512VLH16" if SOC_PART_NUMBER_MKE14F512VLH16 - default "MKE14F512VLL16" if SOC_PART_NUMBER_MKE14F512VLL16 - default "MKE16F256VLH16" if SOC_PART_NUMBER_MKE16F256VLH16 - default "MKE16F256VLL16" if SOC_PART_NUMBER_MKE16F256VLL16 - default "MKE16F512VLH16" if SOC_PART_NUMBER_MKE16F512VLH16 - default "MKE16F512VLL16" if SOC_PART_NUMBER_MKE16F512VLL16 - default "MKE18F256VLH16" if SOC_PART_NUMBER_MKE18F256VLH16 - default "MKE18F256VLL16" if SOC_PART_NUMBER_MKE18F256VLL16 - default "MKE18F512VLH16" if SOC_PART_NUMBER_MKE18F512VLH16 - default "MKE18F512VLL16" if SOC_PART_NUMBER_MKE18F512VLL16 - help - This string holds the full part number of the SoC. It is a - hidden option that you should not set directly. The part - number selection choice defines the default value for this - string. - -config WDOG_ENABLE_AT_BOOT - bool "Keep watchdog timer enabled at boot" - help - Keep the watchdog timer enabled at boot with the internal - 128kHz LPO clock (and a prescaler of 256) as clock - source. The application can take over control of the - watchdog timer after boot and install a different timeout, - if needed. - -config WDOG_INITIAL_TIMEOUT - int "Initial timeout for the watchdog timer in milliseconds" - depends on WDOG_ENABLE_AT_BOOT && WDOG_INIT - range 2 131070 - default 2048 - help - Initial timeout value for the watchdog timer in - milliseconds. - -config KINETIS_KE1XF_ENABLE_CODE_CACHE - bool "Code cache" - default y - -endif # SOC_SERIES_KINETIS_KE1XF diff --git a/soc/arm/nxp_kinetis/kl2x/CMakeLists.txt b/soc/arm/nxp_kinetis/kl2x/CMakeLists.txt deleted file mode 100644 index 268f065fb12..00000000000 --- a/soc/arm/nxp_kinetis/kl2x/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 b/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 deleted file mode 100644 index 25fb897a470..00000000000 --- a/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 +++ /dev/null @@ -1,14 +0,0 @@ -# Kinetis KL2x SoC configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKL25Z4 - -config SOC - default "mkl25z4" - -config NUM_IRQS - default 32 - -endif # SOC_MKL25Z diff --git a/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.series deleted file mode 100644 index d117f4bfb7e..00000000000 --- a/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Kinetis KL2x series configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_KL2X - -config SOC_SERIES - default "kl2x" - -source "soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.mk*" - -endif # SOC_SERIES_KINETIS_KL2X diff --git a/soc/arm/nxp_kinetis/kl2x/Kconfig.series b/soc/arm/nxp_kinetis/kl2x/Kconfig.series deleted file mode 100644 index 3c606c7db27..00000000000 --- a/soc/arm/nxp_kinetis/kl2x/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Kinetis KL2x MCU series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_KL2X - bool "Kinetis KL2x Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select SOC_FAMILY_KINETIS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select CLOCK_CONTROL - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis KL2x MCU series diff --git a/soc/arm/nxp_kinetis/kl2x/Kconfig.soc b/soc/arm/nxp_kinetis/kl2x/Kconfig.soc deleted file mode 100644 index 66d6bce9c8f..00000000000 --- a/soc/arm/nxp_kinetis/kl2x/Kconfig.soc +++ /dev/null @@ -1,81 +0,0 @@ -# Kinetis KL2x MCU series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis KL2x MCU Selection" - depends on SOC_SERIES_KINETIS_KL2X - -config SOC_MKL25Z4 - bool "SOC_MKL25Z4" - select CPU_CORTEX_M0PLUS - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_LPSCI - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - -endchoice - -if SOC_SERIES_KINETIS_KL2X - -config SOC_PART_NUMBER_MKL25Z32VFM4 - bool - -config SOC_PART_NUMBER_MKL25Z64VFM4 - bool - -config SOC_PART_NUMBER_MKL25Z128VFM4 - bool - -config SOC_PART_NUMBER_MKL25Z32VFT4 - bool - -config SOC_PART_NUMBER_MKL25Z64VFT4 - bool - -config SOC_PART_NUMBER_MKL25Z128VFT4 - bool - -config SOC_PART_NUMBER_MKL25Z32VLH4 - bool - -config SOC_PART_NUMBER_MKL25Z64VLH4 - bool - -config SOC_PART_NUMBER_MKL25Z128VLH4 - bool - -config SOC_PART_NUMBER_MKL25Z32VLK4 - bool - -config SOC_PART_NUMBER_MKL25Z64VLK4 - bool - -config SOC_PART_NUMBER_MKL25Z128VLK4 - bool - -config SOC_PART_NUMBER_KINETIS_KL2X - string - default "MKL25Z32VFM4" if SOC_PART_NUMBER_MKL25Z32VFM4 - default "MKL25Z64VFM4" if SOC_PART_NUMBER_MKL25Z64VFM4 - default "MKL25Z128VFM4" if SOC_PART_NUMBER_MKL25Z128VFM4 - default "MKL25Z32VFT4" if SOC_PART_NUMBER_MKL25Z32VFT4 - default "MKL25Z64VFT4" if SOC_PART_NUMBER_MKL25Z64VFT4 - default "MKL25Z128VFT4" if SOC_PART_NUMBER_MKL25Z128VFT4 - default "MKL25Z32VLH4" if SOC_PART_NUMBER_MKL25Z32VLH4 - default "MKL25Z64VLH4" if SOC_PART_NUMBER_MKL25Z64VLH4 - default "MKL25Z128VLH4" if SOC_PART_NUMBER_MKL25Z128VLH4 - default "MKL25Z32VLK4" if SOC_PART_NUMBER_MKL25Z32VLK4 - default "MKL25Z64VLK4" if SOC_PART_NUMBER_MKL25Z64VLK4 - default "MKL25Z128VLK4" if SOC_PART_NUMBER_MKL25Z128VLK4 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_KINETIS_KL2X diff --git a/soc/arm/nxp_kinetis/kv5x/CMakeLists.txt b/soc/arm/nxp_kinetis/kv5x/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9..00000000000 --- a/soc/arm/nxp_kinetis/kv5x/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv56f24 b/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv56f24 deleted file mode 100644 index 88ac4d75c58..00000000000 --- a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv56f24 +++ /dev/null @@ -1,8 +0,0 @@ -# Kinetis KV56F24 configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "mkv56f24" - depends on SOC_MKV56F24 diff --git a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv58f24 b/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv58f24 deleted file mode 100644 index 5f186f3cdef..00000000000 --- a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv58f24 +++ /dev/null @@ -1,8 +0,0 @@ -# Kinetis KV58F24 configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "mkv58f24" - depends on SOC_MKV58F24 diff --git a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.series deleted file mode 100644 index 4e9ba8ce5a3..00000000000 --- a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# Kinetis KV5x series configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_KV5X - -config SOC_SERIES - default "kv5x" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 121 - -config GPIO - default y - -source "soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv*" - -endif # SOC_SERIES_KINETIS_KV5X diff --git a/soc/arm/nxp_kinetis/kv5x/Kconfig.series b/soc/arm/nxp_kinetis/kv5x/Kconfig.series deleted file mode 100644 index 0df355a5823..00000000000 --- a/soc/arm/nxp_kinetis/kv5x/Kconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Kinetis KV5x series MCU - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_KV5X - bool "Kinetis KV5x Series MCU" - select ARM - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_KINETIS - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CLOCK_CONTROL - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis KV5x MCU series diff --git a/soc/arm/nxp_kinetis/kv5x/Kconfig.soc b/soc/arm/nxp_kinetis/kv5x/Kconfig.soc deleted file mode 100644 index dd69ca523b0..00000000000 --- a/soc/arm/nxp_kinetis/kv5x/Kconfig.soc +++ /dev/null @@ -1,60 +0,0 @@ -# Kinetis KV5x series MCU - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis KV5x MCU Selection" - depends on SOC_SERIES_KINETIS_KV5X - -config SOC_MKV56F24 - bool "MKV56F24" - -config SOC_MKV58F24 - bool "MKV58F24" - -endchoice - -if SOC_SERIES_KINETIS_KV5X - -config SOC_PART_NUMBER_MKV56F512VLL24 - bool - -config SOC_PART_NUMBER_MKV56F512VLQ24 - bool - -config SOC_PART_NUMBER_MKV56F1M0VLL24 - bool - -config SOC_PART_NUMBER_MKV56F1M0VLQ24 - bool - -config SOC_PART_NUMBER_MKV58F512VLL24 - bool - -config SOC_PART_NUMBER_MKV58F512VLQ24 - bool - -config SOC_PART_NUMBER_MKV58F1M0VLL24 - bool - -config SOC_PART_NUMBER_MKV58F1M0VLQ24 - bool - -config SOC_PART_NUMBER_KINETIS_KV5X - string - default "MKV56F512VLL24" if SOC_PART_NUMBER_MKV56F512VLL24 - default "MKV56F512VLQ24" if SOC_PART_NUMBER_MKV56F512VLQ24 - default "MKV56F1M0VLL24" if SOC_PART_NUMBER_MKV56F1M0VLL24 - default "MKV56F1M0VLQ24" if SOC_PART_NUMBER_MKV56F1M0VLQ24 - default "MKV58F512VLL24" if SOC_PART_NUMBER_MKV58F512VLL24 - default "MKV58F512VLQ24" if SOC_PART_NUMBER_MKV58F512VLQ24 - default "MKV58F1M0VLL24" if SOC_PART_NUMBER_MKV58F1M0VLL24 - default "MKV58F1M0VLQ24" if SOC_PART_NUMBER_MKV58F1M0VLQ24 - help - This string holds the full part number of the SoC. It is a - hidden option that you should not set directly. The part - number selection choice defines the default value for this - string. - -endif # SOC_SERIES_KINETIS_KV5X diff --git a/soc/arm/nxp_kinetis/kwx/CMakeLists.txt b/soc/arm/nxp_kinetis/kwx/CMakeLists.txt deleted file mode 100644 index d414d72a63a..00000000000 --- a/soc/arm/nxp_kinetis/kwx/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources_ifdef(CONFIG_SOC_MKW24D5 soc_kw2xd.c) -zephyr_sources_ifdef(CONFIG_SOC_MKW22D5 soc_kw2xd.c) -zephyr_sources_ifdef(CONFIG_SOC_MKW41Z4 soc_kw4xz.c) -zephyr_sources_ifdef(CONFIG_SOC_MKW40Z4 soc_kw4xz.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw2xd512 b/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw2xd512 deleted file mode 100644 index b497baf9291..00000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw2xd512 +++ /dev/null @@ -1,22 +0,0 @@ -# Kinetis KW2xD SoC configuration options - -# Copyright (c) 2017, Phytec Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKW22D5 || SOC_MKW24D5 - -config SOC - default "mkw22d5" - depends on SOC_MKW22D5 - -config SOC - default "mkw24d5" - depends on SOC_MKW24D5 - -config NUM_IRQS - default 65 - -config SPI - default y - -endif # SOC_MKW2xD512 diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw40z4 b/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw40z4 deleted file mode 100644 index d865c6def04..00000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw40z4 +++ /dev/null @@ -1,24 +0,0 @@ -# Kinetis KWx SoC configuration options - -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKW40Z4 - -config SOC - default "mkw40z4" - -config NUM_IRQS - default 32 - -choice CSPRNG_GENERATOR_CHOICE - default CTR_DRBG_CSPRNG_GENERATOR -endchoice - -choice RNG_GENERATOR_CHOICE - default XOSHIRO_RANDOM_GENERATOR -endchoice - -config TINYCRYPT - default y - -endif # SOC_MKW40Z4 diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4 b/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4 deleted file mode 100644 index c87b1a5b5b0..00000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4 +++ /dev/null @@ -1,42 +0,0 @@ -# Kinetis KWx SoC configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKW41Z4 - -config SOC - default "mkw41z4" - -config NUM_IRQS - default 32 - -if NETWORKING - -config NET_L2_IEEE802154 - default y - depends on !NET_L2_OPENTHREAD - -endif # NETWORKING - -choice CSPRNG_GENERATOR_CHOICE - default CTR_DRBG_CSPRNG_GENERATOR -endchoice - -# -# MBEDTLS is larger but much faster than TinyCrypt so choose wisely -# -#config MBEDTLS -config TINYCRYPT - default y - depends on ENTROPY_GENERATOR - -# -# KW41Z TRNG entropy source cannot be used as a Hardware RNG source so -# use XOSHIRO for PRNG -# -choice RNG_GENERATOR_CHOICE - default XOSHIRO_RANDOM_GENERATOR -endchoice - -endif # SOC_MKW41Z4 diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.series deleted file mode 100644 index e653088f70d..00000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Kinetis KWx series configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_KWX - -config SOC_SERIES - default "kwx" - -source "soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mk*" - -endif # SOC_SERIES_KINETIS_KWX diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.series b/soc/arm/nxp_kinetis/kwx/Kconfig.series deleted file mode 100644 index 36ba7b54c21..00000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Kinetis KWx MCU series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_KWX - bool "Kinetis KWx Series MCU" - select ARM - select SOC_FAMILY_KINETIS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select CLOCK_CONTROL - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis KWx MCU series diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.soc b/soc/arm/nxp_kinetis/kwx/Kconfig.soc deleted file mode 100644 index 525637d7f1e..00000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.soc +++ /dev/null @@ -1,96 +0,0 @@ -# Kinetis KWx MCU series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis KWx MCU Selection" - depends on SOC_SERIES_KINETIS_KWX - -config SOC_MKW22D5 - bool "SOC_MKW22D5" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - -config SOC_MKW24D5 - bool "SOC_MKW24D5" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - -config SOC_MKW40Z4 - bool "SOC_MKW40Z4" - select CPU_CORTEX_M0PLUS - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_LPUART - select HAS_MCUX_SIM - select HAS_MCUX_TRNG - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - -config SOC_MKW41Z4 - bool "SOC_MKW41Z4" - select CPU_CORTEX_M0PLUS - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_LPUART - select HAS_MCUX_RTC - select HAS_MCUX_SIM - select HAS_MCUX_TPM - select HAS_MCUX_TRNG - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - -endchoice - -if SOC_SERIES_KINETIS_KWX - -config SOC_PART_NUMBER_MKW22D512VHA5 - bool - -config SOC_PART_NUMBER_MKW24D512VHA5 - bool - -config SOC_PART_NUMBER_MKW40Z160VHT4 - bool - -config SOC_PART_NUMBER_MKW41Z256VHT4 - bool - -config SOC_PART_NUMBER_MKW41Z512VHT4 - bool - -config SOC_PART_NUMBER_KINETIS_KWX - string - default "MKW22D512VHA5" if SOC_PART_NUMBER_MKW22D512VHA5 - default "MKW24D512VHA5" if SOC_PART_NUMBER_MKW24D512VHA5 - default "MKW40Z160VHT4" if SOC_PART_NUMBER_MKW40Z160VHT4 - default "MKW41Z256VHT4" if SOC_PART_NUMBER_MKW41Z256VHT4 - default "MKW41Z512VHT4" if SOC_PART_NUMBER_MKW41Z512VHT4 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_KINETIS_KWX diff --git a/soc/arm/nxp_lpc/Kconfig b/soc/arm/nxp_lpc/Kconfig deleted file mode 100644 index 45d31a8c6c0..00000000000 --- a/soc/arm/nxp_lpc/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_LPC - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_LPC - -config SOC_FAMILY - string - default "nxp_lpc" - -source "soc/arm/nxp_lpc/*/Kconfig.soc" - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_LPC54XXX if SOC_SERIES_LPC54XXX - default SOC_PART_NUMBER_LPC55XXX if SOC_SERIES_LPC55XXX - default SOC_PART_NUMBER_LPC11U6X if SOC_SERIES_LPC11U6X - default SOC_PART_NUMBER_LPC51U68 if SOC_SERIES_LPC51U68 - -endif # SOC_FAMILY_LPC diff --git a/soc/arm/nxp_lpc/Kconfig.defconfig b/soc/arm/nxp_lpc/Kconfig.defconfig deleted file mode 100644 index cf1250bfa84..00000000000 --- a/soc/arm/nxp_lpc/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_lpc/*/Kconfig.defconfig.series" - -config SERIAL_INIT_PRIORITY - default 55 - depends on SERIAL diff --git a/soc/arm/nxp_lpc/Kconfig.soc b/soc/arm/nxp_lpc/Kconfig.soc deleted file mode 100644 index 5538bbfd297..00000000000 --- a/soc/arm/nxp_lpc/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_lpc/*/Kconfig.series" diff --git a/soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt b/soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt deleted file mode 100644 index e9a04818a93..00000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u66 b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u66 deleted file mode 100644 index 92f023fffb2..00000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u66 +++ /dev/null @@ -1,11 +0,0 @@ -# NXP LPC11U66 platform configuration options - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC11U66 - -config SOC - default "lpc11u66" - -endif # SOC_LPC11U66 diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u67 b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u67 deleted file mode 100644 index 08f6c9438f8..00000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u67 +++ /dev/null @@ -1,11 +0,0 @@ -# NXP LPC11U67 platform configuration options - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC11U67 - -config SOC - default "lpc11u67" - -endif # SOC_LPC11U67 diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u68 b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u68 deleted file mode 100644 index 010402e73a3..00000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u68 +++ /dev/null @@ -1,11 +0,0 @@ -# NXP LPC11U68 platform configuration options - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC11U68 - -config SOC - default "lpc11u68" - -endif # SOC_LPC11U68 diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.series b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.series deleted file mode 100644 index 0845fedf612..00000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# LPC11U6X series configuration options - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_LPC11U6X - -source "soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lp*" - -config SOC_SERIES - default "lpc11u6x" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 40 - -endif # SOC_SERIES_LPC11U6X diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.series b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.series deleted file mode 100644 index 5eb64a392ec..00000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# LPC LPC11U6X MCU line - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_LPC11U6X - bool "LPC LPC11U6X Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select SOC_FAMILY_LPC - select PINCTRL - select CLOCK_CONTROL - help - Enable support for LPC LPC11U6X MCU series diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.soc b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.soc deleted file mode 100644 index 9dd0ad19c1f..00000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.soc +++ /dev/null @@ -1,52 +0,0 @@ -# LPC LPC11U6x MCU line - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "LPC LPC11U6X MCU Selection" - depends on SOC_SERIES_LPC11U6X - -config SOC_LPC11U68 - bool "SOC_LPC11U68" - -config SOC_LPC11U67 - bool "SOC_LPC11U67" - -config SOC_LPC11U66 - bool "SOC_LPC11U66" - -endchoice - -if SOC_SERIES_LPC11U6X - -config SOC_PART_NUMBER_LPC11U66JBD48 - bool -config SOC_PART_NUMBER_LPC11U67JBD48 - bool -config SOC_PART_NUMBER_LPC11U67JBD64 - bool -config SOC_PART_NUMBER_LPC11U67JBD100 - bool -config SOC_PART_NUMBER_LPC11U68JBD48 - bool -config SOC_PART_NUMBER_LPC11U68JBD64 - bool -config SOC_PART_NUMBER_LPC11U68JBD100 - bool - -config SOC_PART_NUMBER_LPC11U6X - string - default "LPC11U66JBD48" if SOC_PART_NUMBER_LPC11U66JBD48 - default "LPC11U67JBD48" if SOC_PART_NUMBER_LPC11U67JBD48 - default "LPC11U67JBD64" if SOC_PART_NUMBER_LPC11U67JBD64 - default "LPC11U67JBD100" if SOC_PART_NUMBER_LPC11U67JBD100 - default "LPC11U68JBD48" if SOC_PART_NUMBER_LPC11U68JBD48 - default "LPC11U68JBD64" if SOC_PART_NUMBER_LPC11U68JBD64 - default "LPC11U68JBD100" if SOC_PART_NUMBER_LPC11U68JBD100 - - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. -endif # SOC_SERIES_LPC11U6X diff --git a/soc/arm/nxp_lpc/lpc51u68/CMakeLists.txt b/soc/arm/nxp_lpc/lpc51u68/CMakeLists.txt deleted file mode 100644 index a0b6a030303..00000000000 --- a/soc/arm/nxp_lpc/lpc51u68/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2021 metraTec GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# -zephyr_library() - -zephyr_library_sources(soc.c) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_lpc/lpc51u68/Kconfig.defconfig.series b/soc/arm/nxp_lpc/lpc51u68/Kconfig.defconfig.series deleted file mode 100644 index fb2e30d3a6e..00000000000 --- a/soc/arm/nxp_lpc/lpc51u68/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# LPC51U68 series configuration options - -# Copyright (c) 2021 metraTec GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_LPC51U68 - -config SOC_SERIES - default "lpc51u68" - -config NUM_IRQS - # must be >= the highest interrupt number used. - default 32 - -config SOC - default "lpc51u68" - -config SOC_FLASH_LPC - default y - depends on FLASH - -endif diff --git a/soc/arm/nxp_lpc/lpc51u68/Kconfig.series b/soc/arm/nxp_lpc/lpc51u68/Kconfig.series deleted file mode 100644 index 8b1a9dd18b1..00000000000 --- a/soc/arm/nxp_lpc/lpc51u68/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# LPC LPC51U68 Series - -# Copyright (c) 2021 metraTec GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_LPC51U68 - bool "LPC LPC51U68 Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select HAS_MCUX - select HAS_MCUX_FLEXCOMM - select HAS_MCUX_SYSCON - select HAS_MCUX_SCTIMER - select SOC_FAMILY_LPC - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select PLATFORM_SPECIFIC_INIT - help - Enable support for LPC LPC51U68 MCU Series diff --git a/soc/arm/nxp_lpc/lpc51u68/Kconfig.soc b/soc/arm/nxp_lpc/lpc51u68/Kconfig.soc deleted file mode 100644 index e6290615c2c..00000000000 --- a/soc/arm/nxp_lpc/lpc51u68/Kconfig.soc +++ /dev/null @@ -1,27 +0,0 @@ -# LPC LPC51U68 MCU line - -# Copyright (c) 2021 metraTec GmbH -# SPDX-License Identifier: Apache-2.0 - -config SOC_LPC51U68 - bool "SOC_LPC51U68" - depends on SOC_SERIES_LPC51U68 - select CLOCK_CONTROL - -if SOC_SERIES_LPC51U68 - -config SOC_PART_NUMBER_LPC51U68JBD48 - bool -config SOC_PART_NUMBER_LPC51U68JBD64 - bool - -config SOC_PART_NUMBER_LPC51U68 - string - default "LPC51U68JBD48" if SOC_PART_NUMBER_LPC51U68JBD48 - default "LPC51U68JBD64" if SOC_PART_NUMBER_LPC51U68JBD64 - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -endif # SOC_SERIES_LPC51U68 diff --git a/soc/arm/nxp_lpc/lpc54xxx/CMakeLists.txt b/soc/arm/nxp_lpc/lpc54xxx/CMakeLists.txt deleted file mode 100644 index fda5d9532e8..00000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# -zephyr_library() - -zephyr_library_sources(soc.c) -zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT gcc/startup_LPC54114_cm4.S) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) - - -# CMSIS SystemInit allows us to skip enabling clock to SRAM2 bank via -# this compiler definition -if(NOT DEFINED CONFIG_LPC54XXX_SRAM2_CLOCK) -zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1) -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0 b/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0 deleted file mode 100644 index fc46266c3a8..00000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0 +++ /dev/null @@ -1,14 +0,0 @@ -# NXP LPC54114 M0 platform configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC54114_M0 - -config SOC - default "lpc54114_m0" - -config GPIO - default n - -endif # SOC_LPC54114_M0 diff --git a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m4 b/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m4 deleted file mode 100644 index 703ed8a6cf0..00000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m4 +++ /dev/null @@ -1,11 +0,0 @@ -# NXP LPC54114 platform configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC54114_M4 - -config SOC - default "lpc54114" - -endif # SOC_LPC54114_M4 diff --git a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.series b/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.series deleted file mode 100644 index f719b183f76..00000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# LPC54XXX series configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_LPC54XXX - -config SOC_SERIES - default "lpc54xxx" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 40 - -source "soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lp*" - -endif # SOC_SERIES_LPC54XXX diff --git a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.series b/soc/arm/nxp_lpc/lpc54xxx/Kconfig.series deleted file mode 100644 index eece2a1293f..00000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# LPC LPC54XXX MCU line - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_LPC54XXX - bool "LPC LPC54xxx Series MCU" - select ARM - select HAS_MCUX - select HAS_MCUX_FLEXCOMM - select HAS_MCUX_SYSCON - select SOC_FAMILY_LPC - select CPU_CORTEX_M_HAS_SYSTICK - select PLATFORM_SPECIFIC_INIT - help - Enable support for LPC LPC54XXX MCU series diff --git a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc b/soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc deleted file mode 100644 index e71bc8f451e..00000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc +++ /dev/null @@ -1,78 +0,0 @@ -# LPC LPC54XXX MCU line - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "LPC LPC54XXX MCU Selection" - depends on SOC_SERIES_LPC54XXX - -config SOC_LPC54114_M4 - bool "SOC_LPC54114_M4" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select PLATFORM_SPECIFIC_INIT - select CLOCK_CONTROL - select HAS_MCUX_IAP_LEGACY - -config SOC_LPC54114_M0 - bool "SOC_LPC54114_M0" - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_VTOR - select CLOCK_CONTROL - -endchoice - -if SOC_SERIES_LPC54XXX - -config SOC_PART_NUMBER_LPC54114J256BD64 - bool - -config SOC_PART_NUMBER_LPC54XXX - string - default "LPC54114J256BD64" if SOC_PART_NUMBER_LPC54114J256BD64 - - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -config SECOND_CORE_MCUX - bool "LPC54114 Cortex-M0 second core" - depends on HAS_MCUX - help - Driver for second core startup - -config SECOND_CORE_BOOT_ADDRESS_MCUX - depends on SECOND_CORE_MCUX - hex "Address the second core will boot at" - default 0x20010000 - help - This is the address the second core will boot from. Additionally this - address is where we will copy the SECOND_IMAGE to. We default this to - the base of SRAM1. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition - -# Move the LMA address of second core into flash -config BUILD_OUTPUT_ADJUST_LMA - depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 - default "-0x20010000+\ - $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))" - -config BUILD_OUTPUT_INFO_HEADER - default y - depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 - -config LPC54XXX_SRAM2_CLOCK - bool "Clock LPC54XXX SRAM2" - default y - help - SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit - will enable the clock to this RAM bank. Disable this Kconfig to leave - this ram bank untouched out of reset. - -endif # SOC_SERIES_LPC54XXX diff --git a/soc/arm/nxp_lpc/lpc55xxx/CMakeLists.txt b/soc/arm/nxp_lpc/lpc55xxx/CMakeLists.txt deleted file mode 100644 index fb58ca649f2..00000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/CMakeLists.txt +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# -zephyr_library() - -zephyr_library_sources(soc.c) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) -if(DEFINED CONFIG_LPC55XXX_USB_RAM) -zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER - SECTIONS usb.ld) - -zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) -endif() - -# CMSIS SystemInit allows us to skip enabling clock to SRAM banks via -# this compiler definition -if(NOT DEFINED CONFIG_LPC55XXX_SRAM_CLOCKS) -zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1) -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S06 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S06 deleted file mode 100644 index 94f479b9b9f..00000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S06 +++ /dev/null @@ -1,14 +0,0 @@ -# NXP LPC55S06 platform configuration options - -# Copyright (c) 2022 metraTec -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S06 - -config SOC - default "lpc55S06" - -config LPC55XXX_USB_RAM - default n - -endif # SOC_LPC55S06 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16 deleted file mode 100644 index 4f93fffb586..00000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16 +++ /dev/null @@ -1,19 +0,0 @@ -# NXP LPC55S16 platform configuration options - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S16 - -config SOC - default "lpc55S16" - -config CAN_MCUX_MCAN - default y - depends on CAN - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -endif # SOC_LPC55S16 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S28 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S28 deleted file mode 100644 index 4dd2f605dd6..00000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S28 +++ /dev/null @@ -1,15 +0,0 @@ -# NXP LPC55S28 platform configuration options - -# Copyright (c) 2020 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S28 - -config SOC - default "lpc55S28" - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -endif # SOC_LPC55S28 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S36 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S36 deleted file mode 100644 index a83bdf55313..00000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S36 +++ /dev/null @@ -1,18 +0,0 @@ -# NXP LPC55S36 platform configuration options - -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S36 - -config SOC - default "lpc55S36" - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -config LPC55XXX_USB_RAM - default n - -endif # SOC_LPC55S36 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0 deleted file mode 100644 index 4963ad86a75..00000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0 +++ /dev/null @@ -1,23 +0,0 @@ -# NXP LPC55XXX CPU0 platform configuration options - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S69_CPU0 - -config SOC - default "lpc55S69_cpu0" - -config SOC_FLASH_MCUX - default y - depends on FLASH - depends on !TRUSTED_EXECUTION_NONSECURE - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -config I2S_MCUX_FLEXCOMM - select INIT_PLL0 - -endif # SOC_LPC55S69_CPU0 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu1 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu1 deleted file mode 100644 index c061c7b83d8..00000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu1 +++ /dev/null @@ -1,17 +0,0 @@ -# NXP LPC55S69 CPU1 platform configuration options - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S69_CPU1 - -config SOC - default "lpc55S69_cpu1" - -config GPIO - default y - -config SERIAL - default n - -endif # SOC_LPC55S69_CPU1 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.series b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.series deleted file mode 100644 index 05a0f086b95..00000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# LPC55XXX series configuration options - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_LPC55XXX - -config SOC_SERIES - default "lpc55xxx" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 60 - -source "soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lp*" - -endif # SOC_SERIES_LPC55XXX diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.series b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.series deleted file mode 100644 index 733bf9ecc34..00000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# LPC LPC55XXX Series - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_LPC55XXX - bool "LPC5500 Series Family MCU" - select ARM - select HAS_MCUX - select HAS_MCUX_FLEXCOMM - select HAS_MCUX_SYSCON - select HAS_MCUX_WWDT - select SOC_FAMILY_LPC - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_DWT - select PLATFORM_SPECIFIC_INIT - help - Enable support for LPC5500 Series MCU series diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc deleted file mode 100644 index c8c3cae3c49..00000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc +++ /dev/null @@ -1,177 +0,0 @@ -# LPC LPC55XXX Series - -# Copyright 2019, 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "LPC5500 Series MCU Selection" - depends on SOC_SERIES_LPC55XXX - -config SOC_LPC55S06 - bool "SOC_LPC55S06 M33" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CLOCK_CONTROL - select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE - select HAS_MCUX_RNG - -config SOC_LPC55S16 - bool "SOC_LPC55S16 M33" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CLOCK_CONTROL - select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE - select HAS_MCUX_MCAN - select HAS_MCUX_RNG - -config SOC_LPC55S28 - bool "SOC_LPC55S28 M33" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CLOCK_CONTROL - select HAS_MCUX_IAP - select HAS_MCUX_LPADC - select HAS_MCUX_LPC_DMA - select HAS_MCUX_RNG - -config SOC_LPC55S36 - bool "SOC_LPC55S36 M33" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CLOCK_CONTROL - select HAS_MCUX_MCAN - select HAS_MCUX_PWM - -config SOC_LPC55S69_CPU0 - bool "SOC_LPC55S69 M33 [CPU 0]" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CLOCK_CONTROL - select HAS_MCUX_IAP - select HAS_MCUX_LPADC - select HAS_MCUX_LPC_DMA - select HAS_MCUX_USB_LPCIP3511 - select HAS_MCUX_CTIMER - select HAS_MCUX_SCTIMER - select HAS_MCUX_RNG - -config SOC_LPC55S69_CPU1 - bool "SOC_LPC55S69 M33 [CPU 1]" - select CPU_CORTEX_M33 - -endchoice - -if SOC_SERIES_LPC55XXX - -config SOC_PART_NUMBER_LPC55S06JBD64 - bool - -config SOC_PART_NUMBER_LPC55S16JBD64 - bool - -config SOC_PART_NUMBER_LPC55S16JBD100 - bool - -config SOC_PART_NUMBER_LPC55S28JBD100 - bool - -config SOC_PART_NUMBER_LPC55S36JBD100 - bool - -config SOC_PART_NUMBER_LPC55S69JBD100 - bool - -config SOC_PART_NUMBER_LPC55S69JET98 - bool - -config SOC_PART_NUMBER_LPC55XXX - string - default "LPC55S06JBD64" if SOC_PART_NUMBER_LPC55S06JBD64 - default "LPC55S16JBD64" if SOC_PART_NUMBER_LPC55S16JBD64 - default "LPC55S16JBD100" if SOC_PART_NUMBER_LPC55S16JBD100 - default "LPC55S28JBD100" if SOC_PART_NUMBER_LPC55S28JBD100 - default "LPC55S36JBD100" if SOC_PART_NUMBER_LPC55S36JBD100 - default "LPC55S69JBD100" if SOC_PART_NUMBER_LPC55S69JBD100 - default "LPC55S69JET98" if SOC_PART_NUMBER_LPC55S69JET98 - - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -config INIT_PLL0 - bool "Initialize PLL0" - -config INIT_PLL1 - bool "Initialize PLL1" - default "y" - depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM) - help - In the LPC55XXX Family, this is currently being used to set the - core clock value at it's highest frequency which clocks at 150MHz. - Note that flash programming operations are limited to 100MHz, and - this PLL should not be used as the core clock in those cases. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 144000000 if INIT_PLL1 - default 96000000 - -config SECOND_CORE_MCUX - bool "LPC55xxx's second core" - depends on HAS_MCUX - help - Indicates the second core will be enabled, and the part will run - in dual core mode. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition - -config SECOND_CORE_BOOT_ADDRESS_MCUX - depends on SECOND_CORE_MCUX - hex "Address the second core will boot at" - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION)) - help - This is the address the second core will boot from. - -# Move the LMA for the second core image to be in the flash region of primary -# core, so that JLink flash will load it correctly. -config BUILD_OUTPUT_ADJUST_LMA - depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1 - default "0x10000000" - -config LPC55XXX_SRAM_CLOCKS - bool "CLock LPC SRAM banks" - default y - help - SRAM controllers 1,2,3, and 4 are disabled at reset. - By default, CMSIS SystemInit will enable the clock to these RAM banks. - Disable this Kconfig to leave the ram banks untouched out of reset. - -config LPC55XXX_USB_RAM - bool - default y - help - Some SoC's in the LPC5500 Series do have a dedicated USB RAM. - By default, USB RAM is assumed to be present. - Disable this Kconfig in case there is no dedicated USB RAM. - -endif # SOC_SERIES_LPC55XXX diff --git a/soc/arm/nxp_s32/Kconfig b/soc/arm/nxp_s32/Kconfig deleted file mode 100644 index d014315e4d7..00000000000 --- a/soc/arm/nxp_s32/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_NXP_S32 - bool - -if SOC_FAMILY_NXP_S32 - -config SOC_FAMILY - string - default "nxp_s32" - -config NXP_S32_FUNC_RESET_THRESHOLD - int "Functional Reset Escalation threshold" - default 15 - range 0 15 - help - If the value of this option is 0, the Functional reset escalation - function is disabled. Any other value is the number of Functional - resets that causes a Destructive reset, if the FRET register isn't - written to beforehand. - Default to maximum threshold (hardware reset value). - -config NXP_S32_DEST_RESET_THRESHOLD - int "Destructive Reset Escalation threshold" - default 0 - range 0 15 - help - If the value of this field is 0, the Destructive reset escalation - function is disabled. Any other value is the number of Destructive - resets which keeps the chip in the reset state until the next power-on - reset triggers a new reset sequence, if the DRET register isn't - written to beforehand. - Default to disabled (hardware reset value). - -source "soc/arm/nxp_s32/*/Kconfig.soc" - -endif # SOC_FAMILY_NXP_S32 diff --git a/soc/arm/nxp_s32/Kconfig.defconfig b/soc/arm/nxp_s32/Kconfig.defconfig deleted file mode 100644 index 49c9a142934..00000000000 --- a/soc/arm/nxp_s32/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_s32/*/Kconfig.defconfig.series" diff --git a/soc/arm/nxp_s32/Kconfig.soc b/soc/arm/nxp_s32/Kconfig.soc deleted file mode 100644 index 85c8414b5ee..00000000000 --- a/soc/arm/nxp_s32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_s32/*/Kconfig.series" diff --git a/soc/arm/nxp_s32/common/CMakeLists.txt b/soc/arm/nxp_s32/common/CMakeLists.txt deleted file mode 100644 index 6142be7ab64..00000000000 --- a/soc/arm/nxp_s32/common/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_sources(osif.c) -zephyr_sources_ifdef(CONFIG_SOC_SERIES_S32K3XX power_soc.c) diff --git a/soc/arm/nxp_s32/s32k1/CMakeLists.txt b/soc/arm/nxp_s32/s32k1/CMakeLists.txt deleted file mode 100644 index ff8085fc5c1..00000000000 --- a/soc/arm/nxp_s32/s32k1/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") - -zephyr_sources(soc.c) -zephyr_sources_ifdef(CONFIG_ARM_MPU nxp_mpu_regions.c) - -zephyr_sources_ifdef(CONFIG_NXP_S32_FLASH_CONFIG flash_configuration.c) -zephyr_linker_sources_ifdef(CONFIG_NXP_S32_FLASH_CONFIG ROM_START SORT_KEY 0x1 flash_config.ld) diff --git a/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.s32k146 b/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.s32k146 deleted file mode 100644 index 522710112dc..00000000000 --- a/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.s32k146 +++ /dev/null @@ -1,14 +0,0 @@ -# NXP S32K146 - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_S32K146 - -config SOC - default "s32k146" - -config FPU - default y - -endif # SOC_S32K146 diff --git a/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.series b/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.series deleted file mode 100644 index 49dfd9f31cf..00000000000 --- a/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# NXP S32K1XX MCU series - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_S32K1XX - -config SOC_SERIES - default "s32k1" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 80000000 - -config NUM_IRQS - default 239 if CPU_CORTEX_M4 - default 47 if CPU_CORTEX_M0PLUS - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -# The S32K1xx have 8 MPU regions, which is not enough for both HW stack protection -# and userspace. Only enable HW stack protection if userspace is not enabled. -config HW_STACK_PROTECTION - default y if !USERSPACE - -source "soc/arm/nxp_s32/s32k1/Kconfig.defconfig.s32k1*" - -endif # SOC_SERIES_S32K1XX diff --git a/soc/arm/nxp_s32/s32k1/Kconfig.series b/soc/arm/nxp_s32/s32k1/Kconfig.series deleted file mode 100644 index 31102f347fd..00000000000 --- a/soc/arm/nxp_s32/s32k1/Kconfig.series +++ /dev/null @@ -1,24 +0,0 @@ -# NXP S32K1XX MCU series - -# Copyright 2023-2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_S32K1XX - bool "NXP S32K1XX MCU series" - select ARM - select SOC_FAMILY_NXP_S32 - select HAS_NXP_S32_HAL - select HAS_MCUX - select CPU_HAS_NXP_MPU - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - select MPU_ALLOW_FLASH_WRITE if !XIP - select CLOCK_CONTROL - select HAS_MCUX_LPUART - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_FTM - select HAS_MCUX_FLEXCAN - select HAS_MCUX_WDOG32 - select HAS_MCUX_RTC - help - Enable support for NXP S32K1XX MCU series. diff --git a/soc/arm/nxp_s32/s32k1/Kconfig.soc b/soc/arm/nxp_s32/s32k1/Kconfig.soc deleted file mode 100644 index 78caf49f677..00000000000 --- a/soc/arm/nxp_s32/s32k1/Kconfig.soc +++ /dev/null @@ -1,445 +0,0 @@ -# NXP S32K1XX MCUs line - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP S32K1XX MCU selection" - depends on SOC_SERIES_S32K1XX - -config SOC_S32K116 - bool "S32K116" - select CPU_CORTEX_M0PLUS - -config SOC_S32K118 - bool "S32K118" - select CPU_CORTEX_M0PLUS - -config SOC_S32K142 - bool "S32K142" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -config SOC_S32K142W - bool "S32K142W" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -config SOC_S32K144 - bool "S32K144" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -config SOC_S32K144W - bool "S32K144W" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -config SOC_S32K146 - bool "S32K146" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -config SOC_S32K148 - bool "S32K148" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -endchoice - -if SOC_SERIES_S32K1XX - -config SOC_PART_NUMBER_FS32K116LAT0MFMT - bool - -config SOC_PART_NUMBER_FS32K116LAT0MLFR - bool - -config SOC_PART_NUMBER_FS32K116LAT0MLFT - bool - -config SOC_PART_NUMBER_FS32K116LIT0VFMT - bool - -config SOC_PART_NUMBER_FS32K116LIT0VLFT - bool - -config SOC_PART_NUMBER_FS32K118LAT0MLFR - bool - -config SOC_PART_NUMBER_FS32K118LAT0MLFT - bool - -config SOC_PART_NUMBER_FS32K118LAT0MLHR - bool - -config SOC_PART_NUMBER_FS32K118LAT0MLHT - bool - -config SOC_PART_NUMBER_FS32K118LIT0VLFT - bool - -config SOC_PART_NUMBER_FS32K142HAT0MLFT - bool - -config SOC_PART_NUMBER_FS32K142HAT0MLHT - bool - -config SOC_PART_NUMBER_FS32K142HAT0MLLR - bool - -config SOC_PART_NUMBER_FS32K142HAT0MLLT - bool - -config SOC_PART_NUMBER_FS32K142HVT0VLHT - bool - -config SOC_PART_NUMBER_FS32K142UAT0VLFT - bool - -config SOC_PART_NUMBER_FS32K142UAT0VLHR - bool - -config SOC_PART_NUMBER_FS32K142UAT0VLHT - bool - -config SOC_PART_NUMBER_FS32K142UAT0VLLR - bool - -config SOC_PART_NUMBER_FS32K142UAT0VLLT - bool - -config SOC_PART_NUMBER_FS32K142UIT0VLHT - bool - -config SOC_PART_NUMBER_FS32K142WAT0WLFT - bool - -config SOC_PART_NUMBER_FS32K142WAT0WLHT - bool - -config SOC_PART_NUMBER_FS32K144HAT0MLFT - bool - -config SOC_PART_NUMBER_FS32K144HAT0MLHR - bool - -config SOC_PART_NUMBER_FS32K144HAT0MLHT - bool - -config SOC_PART_NUMBER_FS32K144HAT0MLLR - bool - -config SOC_PART_NUMBER_FS32K144HAT0MLLT - bool - -config SOC_PART_NUMBER_FS32K144HAT0MMHR - bool - -config SOC_PART_NUMBER_FS32K144HAT0MMHT - bool - -config SOC_PART_NUMBER_FS32K144HVT0VLHR - bool - -config SOC_PART_NUMBER_FS32K144HVT0VLHT - bool - -config SOC_PART_NUMBER_FS32K144HXT0VLHT - bool - -config SOC_PART_NUMBER_FS32K144HXT0VLLT - bool - -config SOC_PART_NUMBER_FS32K144UAT0VLFT - bool - -config SOC_PART_NUMBER_FS32K144UAT0VLHR - bool - -config SOC_PART_NUMBER_FS32K144UAT0VLHT - bool - -config SOC_PART_NUMBER_FS32K144UAT0VLLT - bool - -config SOC_PART_NUMBER_FS32K144UAT0VMHR - bool - -config SOC_PART_NUMBER_FS32K144UAT0VMHT - bool - -config SOC_PART_NUMBER_FS32K144UIT0VLHT - bool - -config SOC_PART_NUMBER_FS32K144ULT0VLHT - bool - -config SOC_PART_NUMBER_FS32K144ULT0VLLR - bool - -config SOC_PART_NUMBER_FS32K144ULT0VLLT - bool - -config SOC_PART_NUMBER_FS32K144WAT0WLFT - bool - -config SOC_PART_NUMBER_FS32K144WAT0WLHT - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLHR - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLHT - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLLR - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLLT - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLQR - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLQT - bool - -config SOC_PART_NUMBER_FS32K146HAT0MMHR - bool - -config SOC_PART_NUMBER_FS32K146HAT0MMHT - bool - -config SOC_PART_NUMBER_FS32K146HVT0VLHT - bool - -config SOC_PART_NUMBER_FS32K146HXT0VLLT - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLHR - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLHT - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLLR - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLLT - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLQR - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLQT - bool - -config SOC_PART_NUMBER_FS32K146UAT0VMHR - bool - -config SOC_PART_NUMBER_FS32K146UAT0VMHT - bool - -config SOC_PART_NUMBER_FS32K146UIT0VLLT - bool - -config SOC_PART_NUMBER_FS32K146ULT0VLLT - bool - -config SOC_PART_NUMBER_FS32K148HAT0MLLR - bool - -config SOC_PART_NUMBER_FS32K148HAT0MLLT - bool - -config SOC_PART_NUMBER_FS32K148HAT0MLQR - bool - -config SOC_PART_NUMBER_FS32K148HAT0MLQT - bool - -config SOC_PART_NUMBER_FS32K148HAT0MLUT - bool - -config SOC_PART_NUMBER_FS32K148HAT0MMHT - bool - -config SOC_PART_NUMBER_FS32K148UGT0VLQT - bool - -config SOC_PART_NUMBER_FS32K148UIT0VLQT - bool - -config SOC_PART_NUMBER_FS32K148UJT0VLLT - bool - -config SOC_PART_NUMBER_FS32K148UJT0VLQT - bool - -config SOC_PART_NUMBER_FS32K148UJT0VLUT - bool - -config SOC_PART_NUMBER_FS32K148UJT0VMHR - bool - -config SOC_PART_NUMBER_FS32K148UJT0VMHT - bool - -config SOC_PART_NUMBER_S32K1XX - string - default "FS32K116LAT0MFMT" if SOC_PART_NUMBER_FS32K116LAT0MFMT - default "FS32K116LAT0MLFR" if SOC_PART_NUMBER_FS32K116LAT0MLFR - default "FS32K116LAT0MLFT" if SOC_PART_NUMBER_FS32K116LAT0MLFT - default "FS32K116LIT0VFMT" if SOC_PART_NUMBER_FS32K116LIT0VFMT - default "FS32K116LIT0VLFT" if SOC_PART_NUMBER_FS32K116LIT0VLFT - default "FS32K118LAT0MLFR" if SOC_PART_NUMBER_FS32K118LAT0MLFR - default "FS32K118LAT0MLFT" if SOC_PART_NUMBER_FS32K118LAT0MLFT - default "FS32K118LAT0MLHR" if SOC_PART_NUMBER_FS32K118LAT0MLHR - default "FS32K118LAT0MLHT" if SOC_PART_NUMBER_FS32K118LAT0MLHT - default "FS32K118LIT0VLFT" if SOC_PART_NUMBER_FS32K118LIT0VLFT - default "FS32K142HAT0MLFT" if SOC_PART_NUMBER_FS32K142HAT0MLFT - default "FS32K142HAT0MLHT" if SOC_PART_NUMBER_FS32K142HAT0MLHT - default "FS32K142HAT0MLLR" if SOC_PART_NUMBER_FS32K142HAT0MLLR - default "FS32K142HAT0MLLT" if SOC_PART_NUMBER_FS32K142HAT0MLLT - default "FS32K142HVT0VLHT" if SOC_PART_NUMBER_FS32K142HVT0VLHT - default "FS32K142UAT0VLFT" if SOC_PART_NUMBER_FS32K142UAT0VLFT - default "FS32K142UAT0VLHR" if SOC_PART_NUMBER_FS32K142UAT0VLHR - default "FS32K142UAT0VLHT" if SOC_PART_NUMBER_FS32K142UAT0VLHT - default "FS32K142UAT0VLLR" if SOC_PART_NUMBER_FS32K142UAT0VLLR - default "FS32K142UAT0VLLT" if SOC_PART_NUMBER_FS32K142UAT0VLLT - default "FS32K142UIT0VLHT" if SOC_PART_NUMBER_FS32K142UIT0VLHT - default "FS32K142WAT0WLFT" if SOC_PART_NUMBER_FS32K142WAT0WLFT - default "FS32K142WAT0WLHT" if SOC_PART_NUMBER_FS32K142WAT0WLHT - default "FS32K144HAT0MLFT" if SOC_PART_NUMBER_FS32K144HAT0MLFT - default "FS32K144HAT0MLHR" if SOC_PART_NUMBER_FS32K144HAT0MLHR - default "FS32K144HAT0MLHT" if SOC_PART_NUMBER_FS32K144HAT0MLHT - default "FS32K144HAT0MLLR" if SOC_PART_NUMBER_FS32K144HAT0MLLR - default "FS32K144HAT0MLLT" if SOC_PART_NUMBER_FS32K144HAT0MLLT - default "FS32K144HAT0MMHR" if SOC_PART_NUMBER_FS32K144HAT0MMHR - default "FS32K144HAT0MMHT" if SOC_PART_NUMBER_FS32K144HAT0MMHT - default "FS32K144HVT0VLHR" if SOC_PART_NUMBER_FS32K144HVT0VLHR - default "FS32K144HVT0VLHT" if SOC_PART_NUMBER_FS32K144HVT0VLHT - default "FS32K144HXT0VLHT" if SOC_PART_NUMBER_FS32K144HXT0VLHT - default "FS32K144HXT0VLLT" if SOC_PART_NUMBER_FS32K144HXT0VLLT - default "FS32K144UAT0VLFT" if SOC_PART_NUMBER_FS32K144UAT0VLFT - default "FS32K144UAT0VLHR" if SOC_PART_NUMBER_FS32K144UAT0VLHR - default "FS32K144UAT0VLHT" if SOC_PART_NUMBER_FS32K144UAT0VLHT - default "FS32K144UAT0VLLT" if SOC_PART_NUMBER_FS32K144UAT0VLLT - default "FS32K144UAT0VMHR" if SOC_PART_NUMBER_FS32K144UAT0VMHR - default "FS32K144UAT0VMHT" if SOC_PART_NUMBER_FS32K144UAT0VMHT - default "FS32K144UIT0VLHT" if SOC_PART_NUMBER_FS32K144UIT0VLHT - default "FS32K144ULT0VLHT" if SOC_PART_NUMBER_FS32K144ULT0VLHT - default "FS32K144ULT0VLLR" if SOC_PART_NUMBER_FS32K144ULT0VLLR - default "FS32K144ULT0VLLT" if SOC_PART_NUMBER_FS32K144ULT0VLLT - default "FS32K144WAT0WLFT" if SOC_PART_NUMBER_FS32K144WAT0WLFT - default "FS32K144WAT0WLHT" if SOC_PART_NUMBER_FS32K144WAT0WLHT - default "FS32K146HAT0MLHR" if SOC_PART_NUMBER_FS32K146HAT0MLHR - default "FS32K146HAT0MLHT" if SOC_PART_NUMBER_FS32K146HAT0MLHT - default "FS32K146HAT0MLLR" if SOC_PART_NUMBER_FS32K146HAT0MLLR - default "FS32K146HAT0MLLT" if SOC_PART_NUMBER_FS32K146HAT0MLLT - default "FS32K146HAT0MLQR" if SOC_PART_NUMBER_FS32K146HAT0MLQR - default "FS32K146HAT0MLQT" if SOC_PART_NUMBER_FS32K146HAT0MLQT - default "FS32K146HAT0MMHR" if SOC_PART_NUMBER_FS32K146HAT0MMHR - default "FS32K146HAT0MMHT" if SOC_PART_NUMBER_FS32K146HAT0MMHT - default "FS32K146HVT0VLHT" if SOC_PART_NUMBER_FS32K146HVT0VLHT - default "FS32K146HXT0VLLT" if SOC_PART_NUMBER_FS32K146HXT0VLLT - default "FS32K146UAT0VLHR" if SOC_PART_NUMBER_FS32K146UAT0VLHR - default "FS32K146UAT0VLHT" if SOC_PART_NUMBER_FS32K146UAT0VLHT - default "FS32K146UAT0VLLR" if SOC_PART_NUMBER_FS32K146UAT0VLLR - default "FS32K146UAT0VLLT" if SOC_PART_NUMBER_FS32K146UAT0VLLT - default "FS32K146UAT0VLQR" if SOC_PART_NUMBER_FS32K146UAT0VLQR - default "FS32K146UAT0VLQT" if SOC_PART_NUMBER_FS32K146UAT0VLQT - default "FS32K146UAT0VMHR" if SOC_PART_NUMBER_FS32K146UAT0VMHR - default "FS32K146UAT0VMHT" if SOC_PART_NUMBER_FS32K146UAT0VMHT - default "FS32K146UIT0VLLT" if SOC_PART_NUMBER_FS32K146UIT0VLLT - default "FS32K146ULT0VLLT" if SOC_PART_NUMBER_FS32K146ULT0VLLT - default "FS32K148HAT0MLLR" if SOC_PART_NUMBER_FS32K148HAT0MLLR - default "FS32K148HAT0MLLT" if SOC_PART_NUMBER_FS32K148HAT0MLLT - default "FS32K148HAT0MLQR" if SOC_PART_NUMBER_FS32K148HAT0MLQR - default "FS32K148HAT0MLQT" if SOC_PART_NUMBER_FS32K148HAT0MLQT - default "FS32K148HAT0MLUT" if SOC_PART_NUMBER_FS32K148HAT0MLUT - default "FS32K148HAT0MMHT" if SOC_PART_NUMBER_FS32K148HAT0MMHT - default "FS32K148UGT0VLQT" if SOC_PART_NUMBER_FS32K148UGT0VLQT - default "FS32K148UIT0VLQT" if SOC_PART_NUMBER_FS32K148UIT0VLQT - default "FS32K148UJT0VLLT" if SOC_PART_NUMBER_FS32K148UJT0VLLT - default "FS32K148UJT0VLQT" if SOC_PART_NUMBER_FS32K148UJT0VLQT - default "FS32K148UJT0VLUT" if SOC_PART_NUMBER_FS32K148UJT0VLUT - default "FS32K148UJT0VMHR" if SOC_PART_NUMBER_FS32K148UJT0VMHR - default "FS32K148UJT0VMHT" if SOC_PART_NUMBER_FS32K148UJT0VMHT - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config WDOG_INIT - bool - default y - -config NXP_S32_FLASH_CONFIG - bool "NXP S32 flash configuration field" - default y if XIP && !BOOTLOADER_MCUBOOT - help - Include the 16-byte flash configuration field that stores default - protection settings (loaded on reset) and security information that - allows the MCU to restrict access to the FTFx module. - -if NXP_S32_FLASH_CONFIG - -config NXP_S32_FLASH_CONFIG_OFFSET - hex "NXP S32 flash configuration field offset" - default 0x400 - -config NXP_S32_FLASH_CONFIG_FSEC - hex "Flash security byte (FSEC)" - range 0 0xff - default 0xfe - help - Configures the reset value of the FSEC register, which includes - backdoor key access, mass erase, factory access, and flash security - options. - -config NXP_S32_FLASH_CONFIG_FOPT - hex "Flash nonvolatile option byte (FOPT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FOPT register, which includes boot, - NMI, and EzPort options. - -config NXP_S32_FLASH_CONFIG_FEPROT - hex "EEPROM protection byte (FEPROT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FEPROT register for FlexNVM - devices. For program flash only devices, this byte is reserved. - -config NXP_S32_FLASH_CONFIG_FDPROT - hex "Data flash protection byte (FDPROT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FDPROT register for FlexNVM - devices. For program flash only devices, this byte is reserved. - -endif # NXP_S32_FLASH_CONFIG - -config NXP_S32_ENABLE_CODE_CACHE - bool "Code cache" - default y - depends on HAS_MCUX_CACHE - -endif # SOC_SERIES_S32K1XX diff --git a/soc/arm/nxp_s32/s32k1/soc.c b/soc/arm/nxp_s32/s32k1/soc.c deleted file mode 100644 index bed85dbc91d..00000000000 --- a/soc/arm/nxp_s32/s32k1/soc.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2023 NXP - * - * Based on zephyr/soc/arm/nxp_kinetis/ke1xf/soc.c, which is: - * Copyright (c) 2019-2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#include -#include - -#if defined(CONFIG_HAS_MCUX_CACHE) -#include -#endif - -#if defined(CONFIG_WDOG_INIT) -void z_arm_watchdog_init(void) -{ - /* - * NOTE: DO NOT SINGLE STEP THROUGH THIS SECTION!!! Watchdog - * reconfiguration must take place within 128 bus clocks from - * unlocking. Single stepping through the code will cause the - * watchdog to close the unlock window again. - */ - if ((IP_WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U) { - IP_WDOG->CNT = WDOG_UPDATE_KEY; - } else { - IP_WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU; - IP_WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU; - } - while (!(IP_WDOG->CS & WDOG_CS_ULK_MASK)) { - ; - } - - IP_WDOG->TOVAL = 0xFFFFU; - IP_WDOG->CS = (uint32_t) ((IP_WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; - - /* Wait for new configuration to take effect */ - while (!(IP_WDOG->CS & WDOG_CS_RCS_MASK)) { - ; - } -} -#endif /* CONFIG_WDOG_INIT */ - -static int soc_init(void) -{ -#if !defined(CONFIG_ARM_MPU) - uint32_t tmp; - - /* - * Disable memory protection and clear slave port errors. - * Note that the S32K1xx does not implement the optional Arm MPU but - * instead the Soc includes its own NXP MPU module. - */ - tmp = IP_MPU->CESR; - tmp &= ~MPU_CESR_VLD_MASK; - tmp |= MPU_CESR_SPERR0_MASK | MPU_CESR_SPERR1_MASK - | MPU_CESR_SPERR2_MASK | MPU_CESR_SPERR3_MASK; - IP_MPU->CESR = tmp; -#endif /* !CONFIG_ARM_MPU */ - -#if defined(CONFIG_HAS_MCUX_CACHE) && defined(CONFIG_NXP_S32_ENABLE_CODE_CACHE) - L1CACHE_EnableCodeCache(); - barrier_isync_fence_full(); -#endif - - OsIf_Init(NULL); - - return 0; -} - -SYS_INIT(soc_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_s32/s32k3/CMakeLists.txt b/soc/arm/nxp_s32/s32k3/CMakeLists.txt deleted file mode 100644 index d65a1a2e73b..00000000000 --- a/soc/arm/nxp_s32/s32k3/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_sources(soc.c) -zephyr_library_sources_ifdef(CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS mpu_regions.c) -zephyr_linker_sources(SECTIONS sections.ld) -zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT s32k3xx_startup.S) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.s32k344 b/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.s32k344 deleted file mode 100644 index b1b534f6102..00000000000 --- a/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.s32k344 +++ /dev/null @@ -1,14 +0,0 @@ -# NXP S32K344 - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_S32K344 - -config SOC - default "s32k344" - -config FPU - default y - -endif # SOC_S32K344 diff --git a/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.series b/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.series deleted file mode 100644 index 2307571611a..00000000000 --- a/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.series +++ /dev/null @@ -1,40 +0,0 @@ -# NXP S32K3XX MCU series - -# Copyright 2023-2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_S32K3XX - -config SOC_SERIES - default "s32k3" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 2000000 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 239 - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -if NET_L2_ETHERNET - -config NET_TCP_CHECKSUM - default n - -config NET_UDP_CHECKSUM - default n - -endif # NET_L2_ETHERNET - -config CACHE_MANAGEMENT - default y - -source "soc/arm/nxp_s32/s32k3/Kconfig.defconfig.s32k*" - -endif # SOC_SERIES_S32K3XX diff --git a/soc/arm/nxp_s32/s32k3/Kconfig.series b/soc/arm/nxp_s32/s32k3/Kconfig.series deleted file mode 100644 index ac90439b644..00000000000 --- a/soc/arm/nxp_s32/s32k3/Kconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# NXP S32K3XX MCU series - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_S32K3XX - bool "NXP S32K3XX MCU series" - select ARM - select CPU_CORTEX_M7 - select SOC_FAMILY_NXP_S32 - select HAS_NXP_S32_HAL - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - select PLATFORM_SPECIFIC_INIT if XIP - select USE_DT_CODE_PARTITION if XIP - select CLOCK_CONTROL - select HAS_MCUX - select HAS_MCUX_LPUART - select HAS_MCUX_FLEXCAN - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_CACHE - help - Enable support for NXP S32K3XX MCU series. diff --git a/soc/arm/nxp_s32/s32k3/Kconfig.soc b/soc/arm/nxp_s32/s32k3/Kconfig.soc deleted file mode 100644 index 6b8f4e3a883..00000000000 --- a/soc/arm/nxp_s32/s32k3/Kconfig.soc +++ /dev/null @@ -1,61 +0,0 @@ -# NXP S32K3XX MCU series - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP S32K3XX MCU selection" - depends on SOC_SERIES_S32K3XX - -config SOC_S32K344 - bool "s32k344" - -endchoice - -if SOC_SERIES_S32K3XX - -config SOC_PART_NUMBER_PS32K344EHVPBS - bool - -config SOC_PART_NUMBER - string - default "PS32K344EHVPBS" if SOC_PART_NUMBER_PS32K344EHVPBS - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config IVT_HEADER_OFFSET - hex - depends on XIP - default $(dt_node_reg_addr_hex,$(dt_nodelabel_path,ivt_header)) - help - The offset address from flash base address for ivt header - -config IVT_HEADER_SIZE - hex - depends on XIP - default $(dt_node_reg_size_hex,$(dt_nodelabel_path,ivt_header)) - help - Size of ivt header region - -config NXP_S32_PMC_LMEN - bool "Last Mile regulator" - default y if CLOCK_CONTROL - help - Enables the Last Mile regulator, which regulates an external 1.5V - voltage on V15 down to the core and logic supply (V11 power domain), - which is typically 1.1V. - When enabling PLL as system clock, the PMC last mile regulator should - be enabled. - -config NXP_S32_PMC_LMBCTLEN - bool "External BCTL regulator for V15" - depends on NXP_S32_PMC_LMEN - help - This option must be selected if an external BJT between VDD_HV_A and - V15 is used on the PCB. The base of this BJT must be connected to the - VRC_CTRL pin and is controlled by the PMC to regulate a voltage of - 1.5V on V15 pin. - -endif diff --git a/soc/arm/nxp_s32/s32ze/CMakeLists.txt b/soc/arm/nxp_s32/s32ze/CMakeLists.txt deleted file mode 100644 index d0eb4cf78b1..00000000000 --- a/soc/arm/nxp_s32/s32ze/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources( - soc.c -) - -zephyr_library_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27 b/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27 deleted file mode 100644 index 2a88861fc98..00000000000 --- a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_S32Z27_R52 - -config SOC - default "s32z27" - -endif # SOC_S32Z27_R52 diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series b/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series deleted file mode 100644 index a418c054792..00000000000 --- a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series +++ /dev/null @@ -1,45 +0,0 @@ -# NXP S32Z/E MCUs family default configuration - -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_S32ZE_R52 - -config SOC_SERIES - default "s32ze" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 991 - -config FPU - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 2000000 - -config MAIN_STACK_SIZE - default 1024 - -if !XIP -config FLASH_SIZE - default 0 - -config FLASH_BASE_ADDRESS - default 0 -endif # !XIP - -if NET_L2_ETHERNET - -# NETC drops TCP/UDP packets with invalid checksum -config NET_TCP_CHECKSUM - default n - -config NET_UDP_CHECKSUM - default n - -endif # NET_L2_ETHERNET - -source "soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32*" - -endif # SOC_SERIES_S32ZE_R52 diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.series b/soc/arm/nxp_s32/s32ze/Kconfig.series deleted file mode 100644 index c1f2d3606ec..00000000000 --- a/soc/arm/nxp_s32/s32ze/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# NXP S32Z/E MCUs family - -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_S32ZE_R52 - bool "NXP S32Z/E series" - select ARM - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select CPU_CORTEX_R52 - select CPU_HAS_DCLS - select CPU_HAS_ARM_MPU - select GIC_SINGLE_SECURITY_STATE - select VFP_DP_D16 - select PLATFORM_SPECIFIC_INIT - select SOC_FAMILY_NXP_S32 - select CLOCK_CONTROL - select HAS_MCUX - select HAS_MCUX_PIT - help - Enable support for NXP S32Z/E MCUs family on Cortex-R52 cores. diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.soc b/soc/arm/nxp_s32/s32ze/Kconfig.soc deleted file mode 100644 index 790751362d3..00000000000 --- a/soc/arm/nxp_s32/s32ze/Kconfig.soc +++ /dev/null @@ -1,35 +0,0 @@ -# NXP S32Z/E MCUs family - -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP S32Z/E MCUs family SoC selection" - depends on SOC_SERIES_S32ZE_R52 - -config SOC_S32Z27_R52 - bool "SOC_S32Z27_R52" - select HAS_NXP_S32_HAL - -endchoice - -if SOC_SERIES_S32ZE_R52 - -config SOC_PART_NUMBER_S32Z27 - bool - -config SOC_PART_NUMBER - string - default "S32Z27" if SOC_PART_NUMBER_S32Z27 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config NXP_S32_RTU_INDEX - int - range 0 1 - help - This option indicates the index of the target RTU (Real-Time Unit) subsystem. - -endif # SOC_SERIES_S32ZE_R52 diff --git a/soc/arm/nxp_s32/s32ze/soc.h b/soc/arm/nxp_s32/s32ze/soc.h deleted file mode 100644 index e042ebe8af9..00000000000 --- a/soc/arm/nxp_s32/s32ze/soc.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2022-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _NXP_S32_S32ZE_SOC_H_ -#define _NXP_S32_S32ZE_SOC_H_ - -/* Do not let CMSIS to handle GIC */ -#define __GIC_PRESENT 0 - -#if defined(CONFIG_SOC_S32Z27_R52) -#include -#else -#error "SoC not supported" -#endif - -#if defined(CONFIG_CMSIS_RTOS_V2) -#include -#endif - -/* Aliases for peripheral base addresses */ - -/* SIUL2 */ -#define IP_SIUL2_2_BASE 0U /* instance does not exist on this SoC */ - -/* LINFlexD*/ -#define IP_LINFLEX_12_BASE IP_MSC_0_LIN_BASE - -/* SWT */ -#define IP_SWT_0_BASE IP_CE_SWT_0_BASE -#define IP_SWT_1_BASE IP_CE_SWT_1_BASE -#define IP_SWT_2_BASE IP_RTU0__SWT_0_BASE -#define IP_SWT_3_BASE IP_RTU0__SWT_1_BASE -#define IP_SWT_4_BASE IP_RTU0__SWT_2_BASE -#define IP_SWT_5_BASE IP_RTU0__SWT_3_BASE -#define IP_SWT_6_BASE IP_RTU0__SWT_4_BASE -#define IP_SWT_7_BASE IP_RTU1__SWT_0_BASE -#define IP_SWT_8_BASE IP_RTU1__SWT_1_BASE -#define IP_SWT_9_BASE IP_RTU1__SWT_2_BASE -#define IP_SWT_10_BASE IP_RTU1__SWT_3_BASE -#define IP_SWT_11_BASE IP_RTU1__SWT_4_BASE -#define IP_SWT_12_BASE IP_SMU__SWT_BASE - -/* STM */ -#define IP_STM_0_BASE IP_CE_STM_0_BASE -#define IP_STM_1_BASE IP_CE_STM_1_BASE -#define IP_STM_2_BASE IP_CE_STM_2_BASE -#define IP_STM_3_BASE IP_RTU0__STM_0_BASE -#define IP_STM_4_BASE IP_RTU0__STM_1_BASE -#define IP_STM_5_BASE IP_RTU0__STM_2_BASE -#define IP_STM_6_BASE IP_RTU0__STM_3_BASE -#define IP_STM_7_BASE IP_RTU1__STM_0_BASE -#define IP_STM_8_BASE IP_RTU1__STM_1_BASE -#define IP_STM_9_BASE IP_RTU1__STM_2_BASE -#define IP_STM_10_BASE IP_RTU1__STM_3_BASE -#define IP_STM_11_BASE IP_SMU__STM_0_BASE -#define IP_STM_12_BASE IP_SMU__STM_2_BASE - -/* NETC */ -#define IP_NETC_EMDIO_0_BASE IP_NETC__EMDIO_BASE_BASE - -/* MRU */ -#define IP_MRU_0_BASE IP_RTU0__MRU_0_BASE -#define IP_MRU_1_BASE IP_RTU0__MRU_1_BASE -#define IP_MRU_2_BASE IP_RTU0__MRU_2_BASE -#define IP_MRU_3_BASE IP_RTU0__MRU_3_BASE -#define IP_MRU_4_BASE IP_RTU1__MRU_0_BASE -#define IP_MRU_5_BASE IP_RTU1__MRU_1_BASE -#define IP_MRU_6_BASE IP_RTU1__MRU_2_BASE -#define IP_MRU_7_BASE IP_RTU1__MRU_3_BASE - -#endif /* _NXP_S32_S32ZE_SOC_H_ */ diff --git a/soc/arm/qemu_cortex_a53/CMakeLists.txt b/soc/arm/qemu_cortex_a53/CMakeLists.txt new file mode 100644 index 00000000000..35d88056740 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/qemu_cortex_a53/Kconfig b/soc/arm/qemu_cortex_a53/Kconfig new file mode 100644 index 00000000000..2520e012af7 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_CORTEX_A53 + select ARM64 + select CPU_CORTEX_A53 + select QEMU_TARGET diff --git a/soc/arm/qemu_cortex_a53/Kconfig.defconfig b/soc/arm/qemu_cortex_a53/Kconfig.defconfig new file mode 100644 index 00000000000..9d628ef3b59 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +if SOC_QEMU_CORTEX_A53 + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + # - LPIs (starting at 8192) if GIC_V3_ITS is used + default 16384 if GIC_V3_ITS + default 220 if !GIC_V3_ITS + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 62500000 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +endif # SOC_QEMU_CORTEX_A53 diff --git a/soc/arm/qemu_cortex_a53/Kconfig.soc b/soc/arm/qemu_cortex_a53/Kconfig.soc new file mode 100644 index 00000000000..e9d9c6640b6 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_CORTEX_A53 + bool + select SOC_FAMILY_ARM64 + +config SOC + default "qemu_cortex_a53" if SOC_QEMU_CORTEX_A53 diff --git a/soc/arm64/qemu_cortex_a53/mmu_regions.c b/soc/arm/qemu_cortex_a53/mmu_regions.c similarity index 100% rename from soc/arm64/qemu_cortex_a53/mmu_regions.c rename to soc/arm/qemu_cortex_a53/mmu_regions.c diff --git a/soc/arm64/qemu_virt_arm64/CMakeLists.txt b/soc/arm/qemu_virt_arm64/CMakeLists.txt similarity index 100% rename from soc/arm64/qemu_virt_arm64/CMakeLists.txt rename to soc/arm/qemu_virt_arm64/CMakeLists.txt diff --git a/soc/arm/qemu_virt_arm64/Kconfig b/soc/arm/qemu_virt_arm64/Kconfig new file mode 100644 index 00000000000..7c5f7aee6f9 --- /dev/null +++ b/soc/arm/qemu_virt_arm64/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Huawei France Technologies SAS +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_ARM64 + select ARM64 + select CPU_CORTEX_A + select ARMV8_A diff --git a/soc/arm/qemu_virt_arm64/Kconfig.defconfig b/soc/arm/qemu_virt_arm64/Kconfig.defconfig new file mode 100644 index 00000000000..e1a38613040 --- /dev/null +++ b/soc/arm/qemu_virt_arm64/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2022 Huawei France Technologies SAS +# SPDX-License-Identifier: Apache-2.0 + +if SOC_QEMU_VIRT_ARM64 + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + # - LPIs (starting at 8192) if GIC_V3_ITS is used + default 16384 if GIC_V3_ITS + default 220 if !GIC_V3_ITS + +# Dummy value, read at runtime +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +endif # SOC_QEMU_VIRT_ARM64 diff --git a/soc/arm/qemu_virt_arm64/Kconfig.soc b/soc/arm/qemu_virt_arm64/Kconfig.soc new file mode 100644 index 00000000000..e539b4a40cd --- /dev/null +++ b/soc/arm/qemu_virt_arm64/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Huawei France Technologies SAS +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_ARM64 + bool + select SOC_FAMILY_ARM64 + +config SOC + default "qemu_virt_arm64" if SOC_QEMU_VIRT_ARM64 diff --git a/soc/arm64/qemu_virt_arm64/mmu_regions.c b/soc/arm/qemu_virt_arm64/mmu_regions.c similarity index 100% rename from soc/arm64/qemu_virt_arm64/mmu_regions.c rename to soc/arm/qemu_virt_arm64/mmu_regions.c diff --git a/soc/arm/quicklogic_eos_s3/CMakeLists.txt b/soc/arm/quicklogic_eos_s3/CMakeLists.txt deleted file mode 100644 index 224b298c409..00000000000 --- a/soc/arm/quicklogic_eos_s3/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/quicklogic_eos_s3/Kconfig b/soc/arm/quicklogic_eos_s3/Kconfig deleted file mode 100644 index d2f7c006428..00000000000 --- a/soc/arm/quicklogic_eos_s3/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_EOS_S3 - bool diff --git a/soc/arm/quicklogic_eos_s3/Kconfig.defconfig b/soc/arm/quicklogic_eos_s3/Kconfig.defconfig deleted file mode 100644 index d09a30ca53e..00000000000 --- a/soc/arm/quicklogic_eos_s3/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_EOS_S3 - -config SOC - default "quicklogic_eos_s3" - -config NUM_IRQS - default 52 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 61440000 - -if SERIAL - -config UART_INTERRUPT_DRIVEN - default y - -endif # SERIAL - -endif # SOC_EOS_S3 diff --git a/soc/arm/quicklogic_eos_s3/Kconfig.soc b/soc/arm/quicklogic_eos_s3/Kconfig.soc deleted file mode 100644 index e555933430b..00000000000 --- a/soc/arm/quicklogic_eos_s3/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_EOS_S3 - bool "QuickLogic EOS S3 SoC" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select EOS_S3_HAL diff --git a/soc/arm/renesas_ra/Kconfig b/soc/arm/renesas_ra/Kconfig deleted file mode 100644 index 628b75a93de..00000000000 --- a/soc/arm/renesas_ra/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_RA - bool - -if SOC_FAMILY_RA - -config SOC_FAMILY - string - default "renesas_ra" - -config SERIES_SPECIFIC_SOC_INIT - bool "Use series specific initialize" - -source "soc/arm/renesas_ra/*/Kconfig.soc" - -endif # SOC_FAMILY_RA diff --git a/soc/arm/renesas_ra/Kconfig.defconfig b/soc/arm/renesas_ra/Kconfig.defconfig deleted file mode 100644 index e5e211a94b3..00000000000 --- a/soc/arm/renesas_ra/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/renesas_ra/*/Kconfig.defconfig.series" diff --git a/soc/arm/renesas_ra/Kconfig.soc b/soc/arm/renesas_ra/Kconfig.soc deleted file mode 100644 index 2652ee94d2e..00000000000 --- a/soc/arm/renesas_ra/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/renesas_ra/*/Kconfig.series" diff --git a/soc/arm/renesas_ra/ra4m1/CMakeLists.txt b/soc/arm/renesas_ra/ra4m1/CMakeLists.txt deleted file mode 100644 index 4debbfdbf8a..00000000000 --- a/soc/arm/renesas_ra/ra4m1/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.r7fa4m1xxxxxx b/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.r7fa4m1xxxxxx deleted file mode 100644 index c138e20d85c..00000000000 --- a/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.r7fa4m1xxxxxx +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if SOC_R7FA4M1AB3CFM - -config SOC - default "r7fa4m1ab3cfm" - -endif # SOC_R7FA4M1AB3CFM diff --git a/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.series b/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.series deleted file mode 100644 index 99e8e3f639d..00000000000 --- a/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RA4M1 - -rsource "Kconfig.defconfig.r7fa4*" - -config SOC_SERIES - default "ra4m1" - -config NUM_IRQS - default 32 - -endif # SOC_SERIES_RA4M1 diff --git a/soc/arm/renesas_ra/ra4m1/Kconfig.series b/soc/arm/renesas_ra/ra4m1/Kconfig.series deleted file mode 100644 index 7307a2d26c0..00000000000 --- a/soc/arm/renesas_ra/ra4m1/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RA4M1 - bool "Renesas RA4M1" - select ARM - select CPU_CORTEX_M4 - select CPU_HAS_ARM_MPU - select CPU_CORTEX_M_HAS_SYSTICK - select DYNAMIC_INTERRUPTS - select SOC_FAMILY_RA - select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME - select XIP diff --git a/soc/arm/renesas_ra/ra4m1/Kconfig.soc b/soc/arm/renesas_ra/ra4m1/Kconfig.soc deleted file mode 100644 index a7b402fd291..00000000000 --- a/soc/arm/renesas_ra/ra4m1/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Renesas RA4M1 SoC Selection" - depends on SOC_SERIES_RA4M1 - -config SOC_R7FA4M1AB3CFM - bool "R7FA4M1AB3CFM" - -endchoice diff --git a/soc/arm/renesas_ra/ra4m1/linker.ld b/soc/arm/renesas_ra/ra4m1/linker.ld deleted file mode 100644 index 44d5ee51889..00000000000 --- a/soc/arm/renesas_ra/ra4m1/linker.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#include diff --git a/soc/arm/renesas_rcar/Kconfig b/soc/arm/renesas_rcar/Kconfig deleted file mode 100644 index d97ae6b987e..00000000000 --- a/soc/arm/renesas_rcar/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Renesas R-Car SoC line - -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_RCAR - bool - -if SOC_FAMILY_RCAR - -config SOC_FAMILY - string - default "renesas_rcar" - -source "soc/arm/renesas_rcar/*/Kconfig.soc" - -endif # SOC_FAMILY_RCAR diff --git a/soc/arm/renesas_rcar/Kconfig.defconfig b/soc/arm/renesas_rcar/Kconfig.defconfig deleted file mode 100644 index 604ac57ba70..00000000000 --- a/soc/arm/renesas_rcar/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/renesas_rcar/*/Kconfig.defconfig.series" diff --git a/soc/arm/renesas_rcar/Kconfig.soc b/soc/arm/renesas_rcar/Kconfig.soc deleted file mode 100644 index 930e18649e1..00000000000 --- a/soc/arm/renesas_rcar/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Renesas R-Car SoC line - -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - - -source "soc/arm/renesas_rcar/*/Kconfig.series" diff --git a/soc/arm/renesas_rcar/gen3/CMakeLists.txt b/soc/arm/renesas_rcar/gen3/CMakeLists.txt deleted file mode 100644 index 4356fe77d51..00000000000 --- a/soc/arm/renesas_rcar/gen3/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c -) -zephyr_library_sources_ifdef(CONFIG_SOC_R8A77951 pfc_r8a77951.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 b/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 deleted file mode 100644 index ba218a4caa6..00000000000 --- a/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if SOC_R8A77951 - -config SOC - default "r8a77951" - -endif # SOC_R8A77951 diff --git a/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.series b/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.series deleted file mode 100644 index 6bb84ee421b..00000000000 --- a/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Renesas R-Car Gen3 SoC line - -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RCAR_GEN3 - -config SOC_SERIES - default "gen3" - -config NUM_IRQS - default 512 - -config PINCTRL - default y - -endif # SOC_SERIES_RCAR_GEN3 diff --git a/soc/arm/renesas_rcar/gen3/Kconfig.series b/soc/arm/renesas_rcar/gen3/Kconfig.series deleted file mode 100644 index 717f9881bf9..00000000000 --- a/soc/arm/renesas_rcar/gen3/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RCAR_GEN3 - bool "Renesas RCAR Gen3 Cortex R7" - select ARM - select CPU_CORTEX_R7 - select PLATFORM_SPECIFIC_INIT - select CPU_HAS_DCLS - select SOC_FAMILY_RCAR - select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL - help - Enable support for Renesas RCar Gen3 SoC series diff --git a/soc/arm/renesas_rcar/gen3/Kconfig.soc b/soc/arm/renesas_rcar/gen3/Kconfig.soc deleted file mode 100644 index c8596486343..00000000000 --- a/soc/arm/renesas_rcar/gen3/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Renesas RCar SoC Selection" - depends on SOC_SERIES_RCAR_GEN3 - -config SOC_R8A77951 - bool "R8A77951" - -endchoice diff --git a/soc/arm/renesas_rcar/gen4/CMakeLists.txt b/soc/arm/renesas_rcar/gen4/CMakeLists.txt deleted file mode 100644 index 906bfdecfba..00000000000 --- a/soc/arm/renesas_rcar/gen4/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c) diff --git a/soc/arm/renesas_rcar/gen4/Kconfig.defconfig.series b/soc/arm/renesas_rcar/gen4/Kconfig.defconfig.series deleted file mode 100644 index 36218fe504f..00000000000 --- a/soc/arm/renesas_rcar/gen4/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Renesas R-Car Gen4 SoC line - -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RCAR_GEN4 - -source "soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779*" - -config SOC_SERIES - default "gen4" - -endif # SOC_SERIES_RCAR_GEN4 diff --git a/soc/arm/renesas_rcar/gen4/Kconfig.series b/soc/arm/renesas_rcar/gen4/Kconfig.series deleted file mode 100644 index 606b2c50e43..00000000000 --- a/soc/arm/renesas_rcar/gen4/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RCAR_GEN4 - bool "Renesas R-Car Gen4 Cortex R52" - select ARM - select CPU_CORTEX_R52 - select GIC_SINGLE_SECURITY_STATE - select SOC_FAMILY_RCAR - select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL - select ARM_ARCH_TIMER - help - Enable support for Renesas R-Car Gen4 SoC series diff --git a/soc/arm/renesas_rcar/gen4/Kconfig.soc b/soc/arm/renesas_rcar/gen4/Kconfig.soc deleted file mode 100644 index 5c443d6101e..00000000000 --- a/soc/arm/renesas_rcar/gen4/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Renesas RCar SoC Selection" - depends on SOC_SERIES_RCAR_GEN4 - -config SOC_R8A779F0 - bool "r8a779f0" - -endchoice diff --git a/soc/arm/renesas_rcar/gen4/linker.ld b/soc/arm/renesas_rcar/gen4/linker.ld deleted file mode 100644 index a51ff84991f..00000000000 --- a/soc/arm/renesas_rcar/gen4/linker.ld +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2023 IoT.bzh - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include diff --git a/soc/arm/renesas_rzt2m/CMakeLists.txt b/soc/arm/renesas_rzt2m/CMakeLists.txt deleted file mode 100644 index 05fd66ec83c..00000000000 --- a/soc/arm/renesas_rzt2m/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) diff --git a/soc/arm/renesas_rzt2m/Kconfig b/soc/arm/renesas_rzt2m/Kconfig deleted file mode 100644 index fc2f6e81c4e..00000000000 --- a/soc/arm/renesas_rzt2m/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RENESAS_RZT2M - bool - -if SOC_RENESAS_RZT2M - -config SOC_PART_NUMBER_R9A07G075 - bool - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_R9A07G075 - -endif # SOC_RENESAS_RZT2M diff --git a/soc/arm/renesas_rzt2m/Kconfig.defconfig b/soc/arm/renesas_rzt2m/Kconfig.defconfig deleted file mode 100644 index 72f828d4351..00000000000 --- a/soc/arm/renesas_rzt2m/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_RENESAS_RZT2M - -config SOC - default "renesas_rzt2m" - -config NUM_IRQS - default 994 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 20000000 - -config FPU - default y - -config FLASH_SIZE - default 0 - -config FLASH_BASE_ADDRESS - default 0 - -endif # SOC_RENESAS_RZT2M diff --git a/soc/arm/renesas_rzt2m/Kconfig.soc b/soc/arm/renesas_rzt2m/Kconfig.soc deleted file mode 100644 index 0275833b792..00000000000 --- a/soc/arm/renesas_rzt2m/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RENESAS_RZT2M - bool "Renesas RZ/T2M MCU" - select ARM - select CPU_CORTEX_R52 - select CPU_HAS_ARM_MPU - select GIC_V3 - select GIC_SINGLE_SECURITY_STATE - select ARM_ARCH_TIMER - select SYSCON diff --git a/soc/arm/renesas_smartbond/Kconfig b/soc/arm/renesas_smartbond/Kconfig deleted file mode 100644 index 1fd4e25a6a1..00000000000 --- a/soc/arm/renesas_smartbond/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_SMARTBOND - bool - select ARM - select CPU_CORTEX_M33 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_SMARTBOND -config SOC_FAMILY - string - default "renesas_smartbond" - -source "soc/arm/renesas_smartbond/*/Kconfig.soc" - -endif # SOC_FAMILY_SMARTBOND diff --git a/soc/arm/renesas_smartbond/Kconfig.defconfig b/soc/arm/renesas_smartbond/Kconfig.defconfig deleted file mode 100644 index 54728dd5038..00000000000 --- a/soc/arm/renesas_smartbond/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_SMARTBOND - -source "soc/arm/renesas_smartbond/*/Kconfig.defconfig.series" - -config PINCTRL - default y - -endif # SOC_FAMILY_SMARTBOND diff --git a/soc/arm/renesas_smartbond/Kconfig.soc b/soc/arm/renesas_smartbond/Kconfig.soc deleted file mode 100644 index 6d91625f815..00000000000 --- a/soc/arm/renesas_smartbond/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/renesas_smartbond/*/Kconfig.series" diff --git a/soc/arm/renesas_smartbond/da1469x/CMakeLists.txt b/soc/arm/renesas_smartbond/da1469x/CMakeLists.txt deleted file mode 100644 index 115f3a34028..00000000000 --- a/soc/arm/renesas_smartbond/da1469x/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_linker_sources( - RAM_SECTIONS - SORT_KEY 0 - intvect_reserved.ld -) -zephyr_library() -zephyr_library_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14695 b/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14695 deleted file mode 100644 index 101e275b79f..00000000000 --- a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14695 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Renesas Electronics Corporation and/or its affiliates -# SPDX-License-Identifier: Apache-2.0 - -if SOC_DA14695 - -config SOC - default "da14695" - -endif # SOC_DA14695 diff --git a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14699 b/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14699 deleted file mode 100644 index f723336d864..00000000000 --- a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14699 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_DA14699 - -config SOC - default "da14699" - -endif # SOC_DA14699 diff --git a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.series b/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.series deleted file mode 100644 index 801ae9ac9e4..00000000000 --- a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_DA1469X - -source "soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da1469*" - -config SOC_SERIES - default "da1469x" - -config NUM_IRQS - default 40 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config SRAM_VECTOR_TABLE - default y - -config USE_DT_CODE_PARTITION - default y if MCUBOOT - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config FLASH_LOAD_OFFSET - default 0x2400 if !USE_DT_CODE_PARTITION - -config PLATFORM_SPECIFIC_INIT - default y - -endif # SOC_SERIES_DA1469X diff --git a/soc/arm/renesas_smartbond/da1469x/Kconfig.series b/soc/arm/renesas_smartbond/da1469x/Kconfig.series deleted file mode 100644 index c3672a9ecaf..00000000000 --- a/soc/arm/renesas_smartbond/da1469x/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_DA1469X - bool "Renesas SmartBond(tm) DA1469x series MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CPU_CORTEX_M_HAS_SYSTICK - select ARMV8_M_DSP - select SOC_FAMILY_SMARTBOND - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select CLOCK_CONTROL - select CLOCK_CONTROL_SMARTBOND - help - Enable support for Renesas SmartBond(tm) DA1469x MCU series diff --git a/soc/arm/renesas_smartbond/da1469x/Kconfig.soc b/soc/arm/renesas_smartbond/da1469x/Kconfig.soc deleted file mode 100644 index b1e7eddb850..00000000000 --- a/soc/arm/renesas_smartbond/da1469x/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022-2023 Renesas Electronics Corporation and/or its affiliates -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Renesas SmartBond(tm) DA1469x MCU selection" - depends on SOC_SERIES_DA1469X - -config SOC_DA14699 - bool "DA14699" - -config SOC_DA14695 - bool "DA14695" - -endchoice diff --git a/soc/arm/rpi_pico/CMakeLists.txt b/soc/arm/rpi_pico/CMakeLists.txt deleted file mode 100644 index 226f3bd626f..00000000000 --- a/soc/arm/rpi_pico/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/rpi_pico/Kconfig b/soc/arm/rpi_pico/Kconfig deleted file mode 100644 index 7d0f4215aad..00000000000 --- a/soc/arm/rpi_pico/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Raspberry Pi (RP) MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_RPI_PICO - bool - -if SOC_FAMILY_RPI_PICO - -config SOC_FAMILY - string - default "rpi_pico" - -source "soc/arm/rpi_pico/*/Kconfig.soc" - -endif # SOC_FAMILY_RPI_PICO diff --git a/soc/arm/rpi_pico/Kconfig.defconfig b/soc/arm/rpi_pico/Kconfig.defconfig deleted file mode 100644 index 468d4545c5b..00000000000 --- a/soc/arm/rpi_pico/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Raspberry Pi (RP) MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_RPI_PICO - -source "soc/arm/rpi_pico/*/Kconfig.defconfig.series" - -config PINCTRL - default y - -endif # SOC_FAMILY_RPI_PICO diff --git a/soc/arm/rpi_pico/Kconfig.soc b/soc/arm/rpi_pico/Kconfig.soc deleted file mode 100644 index d53c18307e0..00000000000 --- a/soc/arm/rpi_pico/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Raspberry Pi (RP) MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/rpi_pico/*/Kconfig.series" diff --git a/soc/arm/rpi_pico/rp2/CMakeLists.txt b/soc/arm/rpi_pico/rp2/CMakeLists.txt deleted file mode 100644 index 119517e5e1c..00000000000 --- a/soc/arm/rpi_pico/rp2/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/rpi_pico/rp2/Kconfig.defconfig.series b/soc/arm/rpi_pico/rp2/Kconfig.defconfig.series deleted file mode 100644 index 7df057ae441..00000000000 --- a/soc/arm/rpi_pico/rp2/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Raspberry Pi RP2XXX MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RP2XXX - -source "soc/arm/rpi_pico/rp2/Kconfig.defconfig.rp2*" - -config SOC_SERIES - default "rp2" - -config NUM_IRQS - default 26 - -endif # SOC_SERIES_RP2XXX diff --git a/soc/arm/rpi_pico/rp2/Kconfig.series b/soc/arm/rpi_pico/rp2/Kconfig.series deleted file mode 100644 index 35795a8d893..00000000000 --- a/soc/arm/rpi_pico/rp2/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Raspberry Pi RP2XXX MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RP2XXX - bool "Raspberry Pi RP2 series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select CPU_HAS_ARM_MPU - select SOC_FAMILY_RPI_PICO - select HAS_RPI_PICO - select XIP - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - help - Enable support for Raspberry Pi RP2 MCU series diff --git a/soc/arm/rpi_pico/rp2/Kconfig.soc b/soc/arm/rpi_pico/rp2/Kconfig.soc deleted file mode 100644 index 601182672db..00000000000 --- a/soc/arm/rpi_pico/rp2/Kconfig.soc +++ /dev/null @@ -1,50 +0,0 @@ -# Raspberry Pi RP2XXX MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "RP2xxx MCU Selection" - depends on SOC_SERIES_RP2XXX - -config SOC_RP2040 - bool "Raspberry Pi RP2040" - -endchoice - -config RP2_REQUIRES_SECOND_STAGE_BOOT - bool - default y if FLASH_LOAD_OFFSET = 0x100 - -# Flash type used by the SoC. The board should select the one used. - -config RP2_FLASH_W25Q080 - bool - help - Configure RP2 to use a W25Q080 flash chip, or similar. Should be selected - by the board definition, not the user. - -config RP2_FLASH_GENERIC_03H - bool - help - Configure RP2 to use a flash chip supporting the standard 03h command. - Should be selected by the board definition, not the user. - -config RP2_FLASH_IS25LP080 - bool - help - Configure RP2 to use a IS25LP080 flash chip, or similar. Should be selected - by the board definition, not the user. - -config RP2_FLASH_W25X10CL - bool - help - Configure RP2 to use a W25X10CL flash chip, or similar. Should be selected - by the board definition, not the user. - -config RP2_FLASH_AT25SF128A - bool - help - Configure RP2 to use a AT25SF128A flash chip, or similar. Should be selected - by the board definition, not the user. diff --git a/soc/arm/silabs_exx32/CMakeLists.txt b/soc/arm/silabs_exx32/CMakeLists.txt deleted file mode 100644 index 1a7c03d378e..00000000000 --- a/soc/arm/silabs_exx32/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(common) diff --git a/soc/arm/silabs_exx32/Kconfig b/soc/arm/silabs_exx32/Kconfig deleted file mode 100644 index 60bda813903..00000000000 --- a/soc/arm/silabs_exx32/Kconfig +++ /dev/null @@ -1,352 +0,0 @@ -# Copyright (c) 2017 Christian Taedcke -# Copyright (c) 2018 Gil Benkoe -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_EXX32 - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select BUILD_OUTPUT_HEX - -if SOC_FAMILY_EXX32 - -config SOC_FAMILY - string - default "silabs_exx32" - -source "soc/arm/silabs_exx32/*/Kconfig.soc" - -config SOC_PART_NUMBER - string - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_GECKO_SERIES0 - bool - help - Set if we're building for Gecko Series 0 SoC. - This is equivalent of _SILICON_LABS_32B_SERIES_0 definition in HAL - code. - -config SOC_GECKO_SERIES1 - bool - help - Set if we're building for Gecko Series 1 SoC. - This is equivalent of _SILICON_LABS_32B_SERIES_1 definition in HAL - code. - -config SOC_GECKO_SERIES2 - bool - help - Set if we're building for Gecko Series 2 SoC. - This is equivalent of _SILICON_LABS_32B_SERIES_2 definition in HAL - code. - -config SOC_GECKO_BURTC - bool - help - Set if the Back-Up Real Time Counter (BURTC) HAL module is used. - -config SOC_GECKO_CORE - bool - default y - help - Set if the Core interrupt handling (CORE) HAL module is used. - -config SOC_GECKO_ADC - bool - help - Set if the Analog to Digital Converter (ADC) HAL module is used. - -config SOC_GECKO_IADC - bool - help - Set if the Incremental Analog to Digital Converter (IADC) HAL module is used. - -config SOC_GECKO_CRYOTIMER - bool - help - Set if the Ultra Low Energy Timer/Counter (CRYOTIMER) HAL module is used. - -config SOC_GECKO_EMU - bool - help - Set if the Energy Management Unit (EMU) HAL module is used. - -config SOC_GECKO_GPIO - bool - help - Set if the General Purpose Input/Output (GPIO) HAL module is used. - -config SOC_GECKO_I2C - bool - help - Set if the Inter-Integrated Circuit Interface (I2C) HAL module is used. - -config SOC_GECKO_LETIMER - bool - help - Set if the Low Energy Timer (LETIMER) HAL module is used. - -config SOC_GECKO_LEUART - bool - help - Set if the Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) - HAL module is used. - -config SOC_GECKO_MSC - bool - help - Set if the Memory System Controller (MSC) HAL module is used. - -config SOC_GECKO_PRS - bool - help - Set if the Peripheral Reflex System (PRS) HAL module is used. - -config SOC_GECKO_RMU - bool - help - Set if the Reset Management Unit (RMU) HAL module is used. - -config SOC_GECKO_RTC - bool - help - Set if the Real Time Counter (RTC) HAL module is used. - -config SOC_GECKO_RTCC - bool - help - Set if the Real Time Counter and Calendar (RTCC) HAL module is used. - -config SOC_GECKO_SE - bool - help - Set if the Secure Element (SE) HAL module is used. - -config SOC_GECKO_TIMER - bool - help - Set if the Timer/Counter (TIMER) HAL module is used. - -config SOC_GECKO_USART - bool - help - Set if the Universal Synchronous Asynchronous Receiver/Transmitter (USART) - HAL module is used. - -config SOC_GECKO_WDOG - bool - help - Set if the Watchdog Timer (WDOG) HAL module is used. - -config SOC_GECKO_TRNG - bool - help - Set if the SoC has a True Random Number Generator (TRNG) module. - -if PM - -config SOC_GECKO_PM_BACKEND_PMGR - bool - depends on SOC_GECKO_DEV_INIT - default y if SOC_GECKO_SERIES2 - help - Implement PM using sl_power_manager service from Gecko SDK - -config SOC_GECKO_PM_BACKEND_EMU - bool - default y if !SOC_GECKO_PM_BACKEND_PMGR - help - Implement PM using direct calls to EMU driver in emlib - -endif - -config SOC_GECKO_EMU_DCDC - bool "SoC DC/DC regulator" - select SOC_GECKO_EMU - help - Enable the on chip DC/DC regulator - -choice SOC_GECKO_EMU_DCDC_MODE - prompt "DC/DC mode" - depends on SOC_GECKO_EMU_DCDC - help - Select power configuration mode of the on chip DC/DC converter. - - config SOC_GECKO_EMU_DCDC_MODE_UNCONFIGURED - bool "Initial / Unconfigured" - - config SOC_GECKO_EMU_DCDC_MODE_ON - bool "DC/DC On" - - config SOC_GECKO_EMU_DCDC_MODE_OFF - bool "DC/DC Off" - - config SOC_GECKO_EMU_DCDC_MODE_BYPASS - bool "Bypass" -endchoice - -config CRYPTO_ACC_GECKO_TRNG - bool - help - Enable Entropy driver based on the CRYPTO_ACC module for Silicon Labs - Gecko chips. - -config SOC_GECKO_DEV_INIT - bool - help - Use the device initialization routines from the device_init service - in Silicon Labs HAL. These routines initialize and tune HFXOs, - configures DPLLs and manages the Energy Management Unit. - - Disabling these services may negatively impact counter and timer - routines in EXX32 series SoCs. - -config COUNTER_GECKO_STIMER - bool - help - Enable counter driver based on the Sleep Timer driver for Silicon Labs - Gecko chips. - -config SOC_GECKO_CMU - bool - help - Set if the clock management unit (CMU) is present in the SoC. - -if SOC_GECKO_CMU - -config CMU_NEED_LFXO - bool - help - Set if LFXO oscillator should be configured and enabled, potentially - in on-demand mode, after SoC is initialized. - -choice - prompt "High Frequency Clock Selection" - default CMU_HFCLK_HFXO - -config CMU_HFCLK_HFXO - bool "External high frequency crystal oscillator" - help - Set this option to use the external high frequency crystal oscillator - as high frequency clock. - -config CMU_HFCLK_LFXO - bool "External low frequency crystal oscillator" - select CMU_NEED_LFXO - help - Set this option to use the external low frequency crystal oscillator - as high frequency clock. - -config CMU_HFCLK_HFRCO - bool "Internal high frequency RC oscillator" - help - Set this option to use the internal high frequency RC oscillator as high frequency clock. - -endchoice - - -choice - prompt "BURTC Clock Selection" - depends on SOC_GECKO_BURTC - default CMU_BURTCCLK_LFRCO - -config CMU_BURTCCLK_LFXO - bool "LFXO - external low frequency crystal oscillator" - select CMU_NEED_LFXO - help - Set this option to use LFXO - the external low freqency crystal oscillator - as BURTC clock. - Frequency is set by external crystal, typically 32.768 kHz. - -config CMU_BURTCCLK_LFRCO - bool "LFRCO - internal low frequency RC oscillator" - help - Set this option to use LFRCO - the internal low freqency RC oscillator - as BURTC clock. - Frequency is approximately 32.768 kHz. - -config CMU_BURTCCLK_ULFRCO - bool "ULFRCO - internal ultra low frequency RC oscillator" - help - Set this option to use ULFRCO - the external low freqency crystal oscillator - as BURTC clock. - Frequency is approximately 1 kHz. - -endchoice - - -config CMU_HFXO_FREQ - int "External high frequency oscillator frequency" - help - Set the external high frequency oscillator frequency in Hz. This should be set by the - board's defconfig. - -config CMU_LFXO_FREQ - int "External low frequency oscillator frequency" - help - Set the external low frequency oscillator frequency in Hz. This should be set by the - board's defconfig. - -config CMU_HFRCO_FREQ - int "Internal high frequency RC oscillator frequency" - default 0 - depends on SOC_GECKO_HAS_HFRCO_FREQRANGE - help - Set the internal high frequency RC oscillator frequency in Hz. This should be set by the - board's defconfig. Only supported values may be used here. Setting this to 0, skips the - configuration of the high frequency RC oscillator completely. This may be desired, if - the bootloader already configured it properly or the device's default clock source should - be used with it's default configuration. - -endif # SOC_GECKO_CMU - -config SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - bool - help - If enabled, indicates that SoC allows to configure individual pin - locations. This is supported by e.g. efr32fg1p, efr32mg12p series. - If disabled, indicates that pin locations are configured in groups. - This is supported by e.g. efm32hg, efm32wg series. - -config SOC_GECKO_HAS_ERRATA_RTCC_E201 - bool - help - Set if the SoC is affected by errata RTCC_E201: - "When the RTCC is configured with a prescaler, the CCV1 top value enable - feature enabled by setting CCV1TOP in RTCC_CTRL fails to wrap the counter - when RTCC_CNT is equal to RTCC_CC1_CCV, as intended." - -config SOC_GECKO_HAS_HFRCO_FREQRANGE - bool - help - If enabled, indicates that configuration of HFRCO frequency for this SOC is supported - via FREQRANGE field. This is supported for e.g. efr32fg1p, efr32mg12p series. - If disabled, indicates that configuration of HFRCO frequency for corresponding SOC - is not supported via this field. This is the case for e.g. efm32hg, efm32wg series. - -config SOC_GECKO_HAS_RADIO - bool - help - If enabled, indicates that the SoC has a Radio PHY. - -config SOC_GECKO_USE_RAIL - bool "Use RAIL (Radio Abstraction Interface Layer)" - depends on SOC_GECKO_HAS_RADIO - help - RAIL (Radio Abstraction Interface Layer) is a library needed to use the EFR radio - hardware. This option enable the proper set of features to allow to properly compile - with the RAIL blob. - -config SOC_GECKO_CUSTOM_RADIO_PHY - bool "Use RAIL for custom radio phy packet sending and receiving" - depends on SOC_GECKO_HAS_RADIO - select SOC_GECKO_USE_RAIL - help - If enabled, RAIL can be used for user generated custom radio phy - management, sending and receiving packets on radio phy. User has - to provide the radio_config.c and radio_config.h files for the phy. - -endif # SOC_FAMILY_EXX32 diff --git a/soc/arm/silabs_exx32/Kconfig.defconfig b/soc/arm/silabs_exx32/Kconfig.defconfig deleted file mode 100644 index 8f582653b3c..00000000000 --- a/soc/arm/silabs_exx32/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_EXX32 - -source "soc/arm/silabs_exx32/*/Kconfig.defconfig.series" - -config SOC_GECKO_EMU - default y - select SOC_GECKO_CORE - depends on PM - -config CORTEX_M_SYSTICK - default n if GECKO_BURTC_TIMER - -# With sl_power_manager, pm_state_set()'s stack footrpting is noticeably -# large, especially with logs enabled. Since it is called from IDLE task, -# its stack size has to be increased -config IDLE_STACK_SIZE - default 512 if SOC_GECKO_PM_BACKEND_PMGR - -endif diff --git a/soc/arm/silabs_exx32/Kconfig.soc b/soc/arm/silabs_exx32/Kconfig.soc deleted file mode 100644 index c5e43b652ef..00000000000 --- a/soc/arm/silabs_exx32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2017 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/silabs_exx32/*/Kconfig.series" diff --git a/soc/arm/silabs_exx32/common/pinctrl_soc.h b/soc/arm/silabs_exx32/common/pinctrl_soc.h deleted file mode 100644 index 8cfad9d4688..00000000000 --- a/soc/arm/silabs_exx32/common/pinctrl_soc.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2022 Silicon Labs - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * Silabs SoC specific helpers for pinctrl driver - */ - -#ifndef ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ -#define ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ - -#include - -#include -#if CONFIG_SOC_GECKO_SERIES1 -#include -#else -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** @cond INTERNAL_HIDDEN */ - -/** Type for gecko pin. */ -typedef uint32_t pinctrl_soc_pin_t; - -/** - * @brief Utility macro to initialize each pin. - * - * @param node_id Node identifier. - * @param prop Property name. - * @param idx Property entry index. - */ -#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) (DT_PROP_BY_IDX(node_id, prop, idx)), - -/** - * @brief Utility macro to initialize state pins contained in a given property. - * - * @param node_id Node identifier. - * @param prop Property name describing state pins. - */ -#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ - { \ - DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, psels, \ - Z_PINCTRL_STATE_PIN_INIT) \ - } - -/** - * @brief Utility macro to obtain pin function. - * - * @param pincfg Pin configuration bit field. - */ -#define GECKO_GET_FUN(pincfg) (((pincfg) >> GECKO_FUN_POS) & GECKO_FUN_MSK) - -/** - * @brief Utility macro to obtain port configuration. - * - * @param pincfg port configuration bit field. - */ -#define GECKO_GET_PORT(pincfg) (((pincfg) >> GECKO_PORT_POS) & GECKO_PORT_MSK) - -/** - * @brief Utility macro to obtain pin configuration. - * - * @param pincfg pin configuration bit field. - */ -#define GECKO_GET_PIN(pincfg) (((pincfg) >> GECKO_PIN_POS) & GECKO_PIN_MSK) - -/** - * @brief Utility macro to obtain location configuration. - * - * @param pincfg Loc configuration bit field. - */ -#define GECKO_GET_LOC(pincfg) (((pincfg) >> GECKO_LOC_POS) & GECKO_LOC_MSK) - -/** - * @brief Utility macro to obtain speed configuration. - * - * @param pincfg speed configuration bit field. - */ -#define GECKO_GET_SPEED(pincfg) (((pincfg) >> GECKO_SPEED_POS) & GECKO_SPEED_MSK) - -/** @endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/arm/silabs_exx32/common/soc.c b/soc/arm/silabs_exx32/common/soc.c deleted file mode 100644 index 0aab80ea06b..00000000000 --- a/soc/arm/silabs_exx32/common/soc.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (c) 2018, Christian Taedcke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Common SoC initialization for the EXX32 - */ - -#include -#include -#include - -#include -#include -#include -#include -#include - -#ifdef CONFIG_SOC_GECKO_DEV_INIT -#include -#include -#include -#include -#include - -#ifdef CONFIG_PM -#include -#include -#endif - -#endif - -LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); - -#ifdef CONFIG_CMU_HFCLK_HFXO -/** - * @brief Initialization parameters for the external high frequency oscillator - */ -static CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT; -#endif - -#ifdef CONFIG_CMU_NEED_LFXO -/** - * @brief Initialization parameters for the external low frequency oscillator - */ -static CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT; - -static void init_lfxo(void) -{ - /* - * Configuring LFXO disables it, so we can do that only if it's not - * used as a SYSCLK/HFCLK source. - */ -#if defined(_SILICON_LABS_32B_SERIES_2) - if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_LFXO) { - /* - * Check if device has LFXO configuration info in DEVINFO - * See AN0016.2 - */ - if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_LFXOCALVAL) == - DEVINFO_MODULEINFO_LFXOCALVAL_VALID) { - lfxoInit.capTune = - (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK) >> - _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT; - } - CMU_LFXOInit(&lfxoInit); - } -#else - if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO) { - CMU_LFXOInit(&lfxoInit); - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - } -#endif /* _SILICON_LABS_32B_SERIES_2 */ - SystemLFXOClockSet(CONFIG_CMU_LFXO_FREQ); -} - -#endif /* CONFIG_CMU_NEED_LFXO */ - -/** - * @brief Initialize the system clock - */ -static ALWAYS_INLINE void clock_init(void) -{ -#ifdef CONFIG_CMU_HFCLK_HFXO -#if defined(_SILICON_LABS_32B_SERIES_2) - if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_HFXO) { - /* - * Check if device has HFXO configuration info in DEVINFO - * See AN0016.2 - */ - if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_HFXOCALVAL) == - DEVINFO_MODULEINFO_HFXOCALVAL_VALID) { - hfxoInit.ctuneXoAna = - (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK) >> - _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT; - hfxoInit.ctuneXiAna = - (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) >> - _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT; - } - - CMU_HFXOInit(&hfxoInit); - CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFXO); - } - - SystemHFXOClockSet(CONFIG_CMU_HFXO_FREQ); -#else - if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO) { - CMU_HFXOInit(&hfxoInit); - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); - } - SystemHFXOClockSet(CONFIG_CMU_HFXO_FREQ); - CMU_OscillatorEnable(cmuOsc_HFRCO, false, false); -#endif /* _SILICON_LABS_32B_SERIES_2 */ -#elif (defined CONFIG_CMU_HFCLK_LFXO) - /* LFXO should've been already brought up by init_lfxo() */ -#if defined(_SILICON_LABS_32B_SERIES_2) - CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_LFXO); -#else - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_LFXO); - CMU_OscillatorEnable(cmuOsc_HFRCO, false, false); -#endif /* _SILICON_LABS_32B_SERIES_2 */ -#elif (defined CONFIG_CMU_HFCLK_HFRCO) - /* - * This is the default clock, the controller starts with - */ - -#ifdef CONFIG_SOC_GECKO_HAS_HFRCO_FREQRANGE - if (CONFIG_CMU_HFRCO_FREQ) { - /* Setting system HFRCO frequency */ - CMU_HFRCOBandSet(CONFIG_CMU_HFRCO_FREQ); - - /* Using HFRCO as high frequency clock, HFCLK */ - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); - } -#endif -#else -#error "Unsupported clock source for HFCLK selected" -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2) - /* Enable the High Frequency Peripheral Clock */ - CMU_ClockEnable(cmuClock_PCLK, true); -#else - /* Enable the High Frequency Peripheral Clock */ - CMU_ClockEnable(cmuClock_HFPER, true); -#endif /* _SILICON_LABS_32B_SERIES_2 */ - -#if defined(CONFIG_GPIO_GECKO) || defined(CONFIG_LOG_BACKEND_SWO) - CMU_ClockEnable(cmuClock_GPIO, true); -#endif -} - -#ifdef CONFIG_SOC_GECKO_EMU_DCDC -static ALWAYS_INLINE void dcdc_init(void) -{ -#if defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_UNCONFIGURED) - /* Nothing to do, leave DC/DC converter in unconfigured, safe state. */ -#elif defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON) || defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_BYPASS) - EMU_DCDCInit_TypeDef init_cfg = EMU_DCDCINIT_DEFAULT; -#if defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_BYPASS) - init_cfg.dcdcMode = emuDcdcMode_Bypass; -#endif - EMU_DCDCInit(&init_cfg); -#elif defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_OFF) - EMU_DCDCPowerOff(); -#else -#error "Unsupported power configuration mode of the on chip DC/DC converter." -#endif -} -#endif - -#ifdef CONFIG_LOG_BACKEND_SWO -static void swo_init(void) -{ - struct soc_gpio_pin pin_swo = PIN_SWO; - -#if defined(_SILICON_LABS_32B_SERIES_2) - GPIO->TRACEROUTEPEN = GPIO_TRACEROUTEPEN_SWVPEN; -#else - /* Select HFCLK as the debug trace clock */ - CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; - -#if defined(_GPIO_ROUTEPEN_MASK) - /* Enable Serial wire output pin */ - GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN; - /* Set SWO location */ - GPIO->ROUTELOC0 = SWO_LOCATION << _GPIO_ROUTELOC0_SWVLOC_SHIFT; -#else - GPIO->ROUTE = GPIO_ROUTE_SWOPEN | (SWO_LOCATION << 8); -#endif -#endif /* _SILICON_LABS_32B_SERIES_2 */ - - GPIO_PinModeSet(pin_swo.port, pin_swo.pin, pin_swo.mode, pin_swo.out); -} -#endif /* CONFIG_LOG_BACKEND_SWO */ - -/** - * @brief Perform basic hardware initialization - * - * Initialize the interrupt controller device drivers. - * Also initialize the timer device driver, if required. - * - * @return 0 - */ -static int silabs_exx32_init(void) -{ - /* handle chip errata */ - CHIP_Init(); - -#ifdef CONFIG_CMU_NEED_LFXO - init_lfxo(); -#endif - -#ifdef CONFIG_SOC_GECKO_DEV_INIT - sl_device_init_dcdc(); - sl_device_init_hfxo(); - sl_device_init_dpll(); - sl_device_init_emu(); - -#ifdef CONFIG_PM - sl_power_manager_init(); - sl_hfxo_manager_init(); -#endif - -#else /* !CONFIG_SOC_GECKO_DEV_INIT */ - -#ifdef CONFIG_SOC_GECKO_EMU_DCDC - dcdc_init(); -#endif - - /* Initialize system clock according to CONFIG_CMU settings */ - clock_init(); - -#ifdef CONFIG_LOG_BACKEND_SWO - /* Configure SWO debug output */ - swo_init(); -#endif -#endif /* !CONFIG_SOC_GECKO_DEV_INIT */ - - return 0; -} - -SYS_INIT(silabs_exx32_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/silabs_exx32/common/soc_gpio.h b/soc/arm/silabs_exx32/common/soc_gpio.h deleted file mode 100644 index e030c3bc32e..00000000000 --- a/soc/arm/silabs_exx32/common/soc_gpio.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2017 Christian Taedcke - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Silabs EXX32 MCU family General Purpose Input Output (GPIO) - * module HAL driver. - */ - -#ifndef _SILABS_EXX32_SOC_GPIO_H_ -#define _SILABS_EXX32_SOC_GPIO_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct soc_gpio_pin { - GPIO_Port_TypeDef port; /** GPIO port */ - unsigned int pin; /** GPIO pin on the port */ - GPIO_Mode_TypeDef mode; /** mode of the pin, e.g. gpioModeInput */ - unsigned int out; /** out register value */ -}; - -#ifdef __cplusplus -} -#endif - -#endif /* _SILABS_EXX32_SOC_GPIO_H_ */ diff --git a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.efm32gg11b b/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.efm32gg11b deleted file mode 100644 index da0d6b66b91..00000000000 --- a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.efm32gg11b +++ /dev/null @@ -1,8 +0,0 @@ -# Silicon Labs EFM32GG-STK3701A platform configuration options -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_GECKO - default y - depends on GPIO || LOG_BACKEND_SWO diff --git a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.series deleted file mode 100644 index 951969f99fb..00000000000 --- a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# EFM32GG11B series configuration options -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32GG11B - -config SOC_SERIES - default "efm32gg11b" - -config SOC_PART_NUMBER - default "EFM32GG11B820F2048GL192" if SOC_PART_NUMBER_EFM32GG11B820F2048GL192 - default "EFM32GG11B820F2048GM64" if SOC_PART_NUMBER_EFM32GG11B820F2048GM64 - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 68 - -source "soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.efm32gg11b" - -endif # SOC_SERIES_EFM32GG11B diff --git a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.series b/soc/arm/silabs_exx32/efm32gg11b/Kconfig.series deleted file mode 100644 index 34fa472c23d..00000000000 --- a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# EFM32GG11B MCU line -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32GG11B - bool "EFM32GG11B Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_TRNG - select SOC_GECKO_SERIES1 - help - Enable support for EFM32 GiantGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.soc b/soc/arm/silabs_exx32/efm32gg11b/Kconfig.soc deleted file mode 100644 index 573989bd877..00000000000 --- a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# EFM32GG11B (Giant Gecko) MCU line -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32GG11B820F2048GL192 - bool - depends on SOC_SERIES_EFM32GG11B - -config SOC_PART_NUMBER_EFM32GG11B820F2048GM64 - bool - depends on SOC_SERIES_EFM32GG11B diff --git a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.efm32gg12b b/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.efm32gg12b deleted file mode 100644 index ce234528a58..00000000000 --- a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.efm32gg12b +++ /dev/null @@ -1,7 +0,0 @@ -# Silicon Labs EFM32GG12B (Giant Gecko) platform configuration options -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_GECKO - default y - depends on GPIO || LOG_BACKEND_SWO diff --git a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.series deleted file mode 100644 index 469b3057310..00000000000 --- a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# EFM32GG12B series configuration options -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32GG12B - -config SOC_SERIES - default "efm32gg12b" - -config SOC_PART_NUMBER - default "EFM32GG12B810F1024GM64" if SOC_PART_NUMBER_EFM32GG12B810F1024GM64 - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 68 - -source "soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.efm32gg12b" - -endif # SOC_SERIES_EFM32GG12B diff --git a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.series b/soc/arm/silabs_exx32/efm32gg12b/Kconfig.series deleted file mode 100644 index e8dcf52cf17..00000000000 --- a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# EFM32GG12B (Giant Gecko) MCU line -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32GG12B - bool "EFM32GG12B Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_TRNG - select SOC_GECKO_SERIES1 - help - Enable support for EFM32 GiantGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.soc b/soc/arm/silabs_exx32/efm32gg12b/Kconfig.soc deleted file mode 100644 index 72cdf1bf226..00000000000 --- a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# EFM32GG12B (Giant Gecko) MCU line -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32GG12B810F1024GM64 - bool - depends on SOC_SERIES_EFM32GG12B diff --git a/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.series deleted file mode 100644 index f854f0d99ae..00000000000 --- a/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# EFM32HG series configuration options - -# Copyright (c) 2018 Christian Taedcke -# Copyright (c) 2018 Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32HG - -config SOC_SERIES - default "efm32hg" - -config SOC_PART_NUMBER - default "EFM32HG322F64" if SOC_PART_NUMBER_EFM32HG322F64 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 20 - -endif # SOC_SERIES_EFM32HG diff --git a/soc/arm/silabs_exx32/efm32hg/Kconfig.series b/soc/arm/silabs_exx32/efm32hg/Kconfig.series deleted file mode 100644 index d17c24fbcdb..00000000000 --- a/soc/arm/silabs_exx32/efm32hg/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# EFM32HG MCU line - -# Copyright (c) 2018 Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32HG - bool "EFM32HG Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select SOC_FAMILY_EXX32 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select HAS_SILABS_GECKO - select SOC_GECKO_CMU - select SOC_GECKO_GPIO - select HAS_PM - select SOC_GECKO_SERIES0 - help - Enable support for EFM32 Happy Gecko MCU series diff --git a/soc/arm/silabs_exx32/efm32hg/Kconfig.soc b/soc/arm/silabs_exx32/efm32hg/Kconfig.soc deleted file mode 100644 index 3c040b5bff1..00000000000 --- a/soc/arm/silabs_exx32/efm32hg/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32HG (Happy Gecko) MCU line - -# Copyright (c) 2018 Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32HG322F64 - bool - depends on SOC_SERIES_EFM32HG diff --git a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32jg12b/Kconfig.defconfig.series deleted file mode 100644 index fd7d88352a1..00000000000 --- a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFM32JG12B series configuration options - -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32JG12B - -config SOC_SERIES - default "efm32jg12b" - -config SOC_PART_NUMBER - default "EFM32JG12B500F1024GL125" if SOC_PART_NUMBER_EFM32JG12B500F1024GL125 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 50 - -endif # SOC_SERIES_EFM32JG12B diff --git a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.series b/soc/arm/silabs_exx32/efm32jg12b/Kconfig.series deleted file mode 100644 index c82872f4eec..00000000000 --- a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# EFM32JG12B MCU line - -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32JG12B - bool "EFM32JG12B Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M3 - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_SERIES1 - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_TRNG - select HAS_PM - help - Enable support for EFM32 JadeGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.soc b/soc/arm/silabs_exx32/efm32jg12b/Kconfig.soc deleted file mode 100644 index d7644df075d..00000000000 --- a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32JG12B (Jade Gecko) MCU line - -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32JG12B500F1024GL125 - bool - depends on SOC_SERIES_EFM32JG12B diff --git a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32pg12b/Kconfig.defconfig.series deleted file mode 100644 index 33fe5a913ab..00000000000 --- a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFM32PG12B series configuration options - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32PG12B - -config SOC_SERIES - default "efm32pg12b" - -config SOC_PART_NUMBER - default "EFM32PG12B500F1024GL125" if SOC_PART_NUMBER_EFM32PG12B500F1024GL125 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 50 - -endif # SOC_SERIES_EFM32PG12B diff --git a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.series b/soc/arm/silabs_exx32/efm32pg12b/Kconfig.series deleted file mode 100644 index 0ab448b6fb7..00000000000 --- a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.series +++ /dev/null @@ -1,26 +0,0 @@ -# EFM32PG12B MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32PG12B - bool "EFM32PG12B Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_SERIES1 - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_TRNG - select SOC_GECKO_ADC - select HAS_PM - help - Enable support for EFM32 PearlGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.soc b/soc/arm/silabs_exx32/efm32pg12b/Kconfig.soc deleted file mode 100644 index 94e499cd4d0..00000000000 --- a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32PG12B (Pearl Gecko) MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32PG12B500F1024GL125 - bool - depends on SOC_SERIES_EFM32PG12B diff --git a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32pg1b/Kconfig.defconfig.series deleted file mode 100644 index c65044482b3..00000000000 --- a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFM32PG1B series configuration options - -# Copyright (c) 2020 Rafael Dias Menezes -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32PG1B - -config SOC_SERIES - default "efm32pg1b" - -config SOC_PART_NUMBER - default "EFM32PG1B200F256GM48" if SOC_PART_NUMBER_EFM32PG1B200F256GM48 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 34 - -endif # SOC_SERIES_EFM32PG1B diff --git a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.series b/soc/arm/silabs_exx32/efm32pg1b/Kconfig.series deleted file mode 100644 index 5a22fa29908..00000000000 --- a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.series +++ /dev/null @@ -1,24 +0,0 @@ -# EFM32PG1B MCU line - -# Copyright (c) 2020 Rafael Dias Menezes -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32PG1B - bool "EFM32PG1B Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select HAS_PM - select SOC_GECKO_SERIES1 - help - Enable support for EFM32 PearlGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.soc b/soc/arm/silabs_exx32/efm32pg1b/Kconfig.soc deleted file mode 100644 index b303eb9dc8e..00000000000 --- a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32PG1B (Pearl Gecko) MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32PG1B200F256GM48 - bool - depends on SOC_SERIES_EFM32PG1B diff --git a/soc/arm/silabs_exx32/efm32wg/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32wg/Kconfig.defconfig.series deleted file mode 100644 index 1d9bd93db5e..00000000000 --- a/soc/arm/silabs_exx32/efm32wg/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFM32WG series configuration options - -# Copyright (c) 2017 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32WG - -config SOC_SERIES - default "efm32wg" - -config SOC_PART_NUMBER - default "EFM32WG990F256" if SOC_PART_NUMBER_EFM32WG990F256 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 39 - -endif # SOC_SERIES_EFM32WG diff --git a/soc/arm/silabs_exx32/efm32wg/Kconfig.series b/soc/arm/silabs_exx32/efm32wg/Kconfig.series deleted file mode 100644 index 99dfba375d1..00000000000 --- a/soc/arm/silabs_exx32/efm32wg/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# EFM32WG MCU line - -# Copyright (c) 2017 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32WG - bool "EFM32WG Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select HAS_SILABS_GECKO - select SOC_GECKO_CMU - select SOC_GECKO_GPIO - select HAS_PM - select SOC_GECKO_SERIES0 - help - Enable support for EFM32 WonderGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32wg/Kconfig.soc b/soc/arm/silabs_exx32/efm32wg/Kconfig.soc deleted file mode 100644 index 0c579f591c7..00000000000 --- a/soc/arm/silabs_exx32/efm32wg/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32WG (Wonder Gecko) MCU line - -# Copyright (c) 2017 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32WG990F256 - bool - depends on SOC_SERIES_EFM32WG diff --git a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.series deleted file mode 100644 index 3d3ecc5a5b7..00000000000 --- a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Silicon Labs EFR32BG13P (Blue Gecko) MCU configuration options - -# Copyright (c) 2020 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32BG13P - -config SOC_SERIES - default "efr32bg13p" - -config SOC_PART_NUMBER - default "EFR32BG13P632F512GM48" if SOC_PART_NUMBER_EFR32BG13P632F512GM48 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 47 - -endif # SOC_SERIES_EFR32BG13P diff --git a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.series b/soc/arm/silabs_exx32/efr32bg13p/Kconfig.series deleted file mode 100644 index f48d53d861e..00000000000 --- a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.series +++ /dev/null @@ -1,24 +0,0 @@ -# Silicon Labs EFR32BG13P (Blue Gecko) MCU - -# Copyright (c) 2020 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32BG13P - bool "EFR32BG13P Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select HAS_PM - select SOC_GECKO_SERIES1 - help - Enable support for EFR32BG13P Blue Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.soc b/soc/arm/silabs_exx32/efr32bg13p/Kconfig.soc deleted file mode 100644 index e6ceb2f47c3..00000000000 --- a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Silicon Labs EFR32BG13P (Blue Gecko) MCU series - -# Copyright (c) 2020 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32BG13P - -config SOC_PART_NUMBER_EFR32BG13P632F512GM48 - bool - -endif # SOC_SERIES_EFR32BG13P diff --git a/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.efr32bg22 b/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.efr32bg22 deleted file mode 100644 index 7600ace022b..00000000000 --- a/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.efr32bg22 +++ /dev/null @@ -1,7 +0,0 @@ -# Silicon Labs EFR32BG22 (Blue Gecko) MCU configuration options - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_GECKO - default y diff --git a/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.series deleted file mode 100644 index 377366c65f3..00000000000 --- a/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.series +++ /dev/null @@ -1,24 +0,0 @@ -# Silicon Labs EFR32BG22 (Blue Gecko) MCU configuration options - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32BG22 - -config SOC_SERIES - default "efr32bg22" - -config SOC_PART_NUMBER - default "EFR32BG22C224F512IM40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 60 - -config PM - select COUNTER - select UART_INTERRUPT_DRIVEN - -source "soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.efr32bg22" - -endif # SOC_SERIES_EFR32BG22 diff --git a/soc/arm/silabs_exx32/efr32bg22/Kconfig.series b/soc/arm/silabs_exx32/efr32bg22/Kconfig.series deleted file mode 100644 index 278f702ebac..00000000000 --- a/soc/arm/silabs_exx32/efr32bg22/Kconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Silicon Labs EFR32BG22 (Blue Gecko) MCU - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32BG22 - bool "EFR32BG22P Series MCU" - select ARM - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CPU_CORTEX_M33 - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_FPU - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_SERIES2 - select SOC_GECKO_GPIO - select SOC_GECKO_CMU - select SOC_GECKO_CORE - select SOC_GECKO_DEV_INIT - select SOC_GECKO_SE - select HAS_PM - help - Enable support for EFR32BG22 Blue Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32bg22/Kconfig.soc b/soc/arm/silabs_exx32/efr32bg22/Kconfig.soc deleted file mode 100644 index 51c8f0b7092..00000000000 --- a/soc/arm/silabs_exx32/efr32bg22/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Silicon Labs EFR32BG22 (Blue Gecko) MCU series - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32BG22C224F512IM40 - bool - depends on SOC_SERIES_EFR32BG22 diff --git a/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.efr32bg27 b/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.efr32bg27 deleted file mode 100644 index 6b33d3ea25e..00000000000 --- a/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.efr32bg27 +++ /dev/null @@ -1,7 +0,0 @@ -# Silicon Labs EFR32BG27 (Blue Gecko) MCU configuration options - -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_GECKO - default y diff --git a/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.series deleted file mode 100644 index 9d010dba824..00000000000 --- a/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# Silicon Labs EFR32BG27 (Blue Gecko) MCU configuration options - -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32BG27 - -config SOC_SERIES - default "efr32bg27" - -config SOC_PART_NUMBER - default "EFR32BG27C140F768IM40" if SOC_PART_NUMBER_EFR32BG27C140F768IM40 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 66 - -config PM - select COUNTER - -source "soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.efr32bg27" - -endif # SOC_SERIES_EFR32BG27 diff --git a/soc/arm/silabs_exx32/efr32bg27/Kconfig.series b/soc/arm/silabs_exx32/efr32bg27/Kconfig.series deleted file mode 100644 index d826c4d121c..00000000000 --- a/soc/arm/silabs_exx32/efr32bg27/Kconfig.series +++ /dev/null @@ -1,26 +0,0 @@ -# Silicon Labs EFR32BG27 (Blue Gecko) MCU - -# Copyright (c) Antmicro 2023 -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32BG27 - bool "EFR32BG27 Series MCU" - select ARM - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CPU_CORTEX_M33 - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_FPU - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_SERIES2 - select SOC_GECKO_CMU - select SOC_GECKO_CORE - select SOC_GECKO_DEV_INIT - select SOC_GECKO_SE - select HAS_PM - help - Enable support for EFR32BG27 Blue Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32bg27/Kconfig.soc b/soc/arm/silabs_exx32/efr32bg27/Kconfig.soc deleted file mode 100644 index f2b9fe5b342..00000000000 --- a/soc/arm/silabs_exx32/efr32bg27/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Silicon Labs EFR32BG27 (Blue Gecko) MCU series - -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32BG27C140F768IM40 - bool - depends on SOC_SERIES_EFR32BG27 diff --git a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32fg13p/Kconfig.defconfig.series deleted file mode 100644 index 2010356d363..00000000000 --- a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFR32FG13P series configuration options - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32FG13P - -config SOC_SERIES - default "efr32fg13p" - -config SOC_PART_NUMBER - default "EFR32FG13P233F512GM48" if SOC_PART_NUMBER_EFR32FG13P233F512GM48 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 45 - -endif # SOC_SERIES_EFR32FG13P diff --git a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.series b/soc/arm/silabs_exx32/efr32fg13p/Kconfig.series deleted file mode 100644 index 11074d6f586..00000000000 --- a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.series +++ /dev/null @@ -1,25 +0,0 @@ -# EFR32FG13P MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32FG13P - bool "EFR32FG13P Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_GPIO - select SOC_GECKO_HAS_ERRATA_RTCC_E201 - select HAS_PM - select SOC_GECKO_SERIES1 - help - Enable support for EFR32 FlexGecko MCU series diff --git a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.soc b/soc/arm/silabs_exx32/efr32fg13p/Kconfig.soc deleted file mode 100644 index e79517fb536..00000000000 --- a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFR32FG13P (Flex Gecko) MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32FG13P233F512GM48 - bool - depends on SOC_SERIES_EFR32FG13P diff --git a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32fg1p/Kconfig.defconfig.series deleted file mode 100644 index cb47bf677b2..00000000000 --- a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFR32FG1P series configuration options - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32FG1P - -config SOC_SERIES - default "efr32fg1p" - -config SOC_PART_NUMBER - default "EFR32FG1P133F256GM48" if SOC_PART_NUMBER_EFR32FG1P133F256GM48 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 33 - -endif # SOC_SERIES_EFR32FG1P diff --git a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.series b/soc/arm/silabs_exx32/efr32fg1p/Kconfig.series deleted file mode 100644 index 8d453472de4..00000000000 --- a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.series +++ /dev/null @@ -1,25 +0,0 @@ -# EFR32FG1P MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32FG1P - bool "EFR32FG1P Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_GPIO - select SOC_GECKO_HAS_ERRATA_RTCC_E201 - select HAS_PM - select SOC_GECKO_SERIES1 - help - Enable support for EFR32 FlexGecko MCU series diff --git a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.soc b/soc/arm/silabs_exx32/efr32fg1p/Kconfig.soc deleted file mode 100644 index 212db5e6117..00000000000 --- a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFR32FG1P (Flex Gecko) MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32FG1P133F256GM48 - bool - depends on SOC_SERIES_EFR32FG1P diff --git a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.series deleted file mode 100644 index 6f20bfbe57e..00000000000 --- a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# EFM32WG series configuration options - -# Copyright (c) 2018 Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32MG12P - -config SOC_SERIES - default "efr32mg12p" - -config SOC_PART_NUMBER - default "EFR32MG12P332F1024GL125" if SOC_PART_NUMBER_EFR32MG12P332F1024GL125 - default "EFR32MG12P432F1024GL125" if SOC_PART_NUMBER_EFR32MG12P432F1024GL125 - default "EFR32MG12P433F1024GM68" if SOC_PART_NUMBER_EFR32MG12P433F1024GM68 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 49 - -endif # SOC_SERIES_EFR32MG12P diff --git a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.series b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.series deleted file mode 100644 index 23426e8ce20..00000000000 --- a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.series +++ /dev/null @@ -1,26 +0,0 @@ -# EFR32MG12P MCU line - -# Copyright (c) 2018 Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32MG12P - bool "EFR32MG12P Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_TRNG - select HAS_PM - select SOC_GECKO_SERIES1 - help - Enable support for EFR32 Mighty Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc deleted file mode 100644 index b171553e638..00000000000 --- a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# EFR32MG12P (Mighty Gecko) MCU line - -# Copyright (c) 2018 Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32MG12P332F1024GL125 - bool - depends on SOC_SERIES_EFR32MG12P - -config SOC_PART_NUMBER_EFR32MG12P433F1024GM68 - bool - depends on SOC_SERIES_EFR32MG12P - -config SOC_PART_NUMBER_EFR32MG12P432F1024GL125 - bool - depends on SOC_SERIES_EFR32MG12P diff --git a/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.efr32mg21 b/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.efr32mg21 deleted file mode 100644 index 1844935f015..00000000000 --- a/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.efr32mg21 +++ /dev/null @@ -1,8 +0,0 @@ -# Silicon Labs EFR32MG21 (Mighty Gecko) MCU configuration options - -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_GECKO - default y - depends on GPIO || LOG_BACKEND_SWO diff --git a/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.series deleted file mode 100644 index 61933d374f2..00000000000 --- a/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Silicon Labs EFR32MG21 (Might Gecko) series configuration options - -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32MG21 - -config SOC_SERIES - default "efr32mg21" - -config SOC_PART_NUMBER - default "EFR32MG21A020F1024IM32" if SOC_PART_NUMBER_EFR32MG21A020F1024IM32 - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 61 - -source "soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.efr32mg21" - -endif # SOC_SERIES_EFR32MG21 diff --git a/soc/arm/silabs_exx32/efr32mg21/Kconfig.series b/soc/arm/silabs_exx32/efr32mg21/Kconfig.series deleted file mode 100644 index 731658d29e3..00000000000 --- a/soc/arm/silabs_exx32/efr32mg21/Kconfig.series +++ /dev/null @@ -1,26 +0,0 @@ -# Silicon Labs EFR32MG21 (Mighty Gecko) MCU - -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32MG21 - bool "EFR32MG21 Series MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_CORTEX_M_HAS_DWT - select ARMV8_M_DSP - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_SERIES2 - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_SE - select HAS_PM - help - Enable support for EFR32MG21 Mighty Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32mg21/Kconfig.soc b/soc/arm/silabs_exx32/efr32mg21/Kconfig.soc deleted file mode 100644 index eb216bc355f..00000000000 --- a/soc/arm/silabs_exx32/efr32mg21/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Silicon Labs EFR32MG21 (Mighty Gecko) MCU line - -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32MG21A020F1024IM32 - bool - depends on SOC_SERIES_EFR32MG21 diff --git a/soc/arm/silabs_exx32/efr32mg21/soc.h b/soc/arm/silabs_exx32/efr32mg21/soc.h deleted file mode 100644 index 16117e9e62e..00000000000 --- a/soc/arm/silabs_exx32/efr32mg21/soc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Board configuration macros for the EFR32MG21 SoC - * - */ - -#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_H -#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_H - -#include - -#ifndef _ASMLANGUAGE - -#include - -#include "soc_pinmap.h" -#include "../common/soc_gpio.h" - - -#endif /* !_ASMLANGUAGE */ - -#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_H */ diff --git a/soc/arm/silabs_exx32/efr32mg21/soc_pinmap.h b/soc/arm/silabs_exx32/efr32mg21/soc_pinmap.h deleted file mode 100644 index 3ebef365a32..00000000000 --- a/soc/arm/silabs_exx32/efr32mg21/soc_pinmap.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Silabs EFR32MG21 MCU pin definitions. - * - * This file contains pin configuration data required by different MCU - * modules to correctly configure GPIO controller. - */ - -#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_PINMAP_H_ -#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_PINMAP_H_ - -#include - -#ifdef CONFIG_LOG_BACKEND_SWO -#define PIN_SWO { gpioPortA, 3, gpioModePushPull, 1 } -#endif /* CONFIG_LOG_BACKEND_SWO */ - -#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_PINMAP_H_ */ diff --git a/soc/arm/silabs_exx32/efr32mg24/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32mg24/Kconfig.defconfig.series deleted file mode 100644 index ec3e460c355..00000000000 --- a/soc/arm/silabs_exx32/efr32mg24/Kconfig.defconfig.series +++ /dev/null @@ -1,29 +0,0 @@ -# Silicon Labs EFR32MG24 (Mighty Gecko) MCU configuration options - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32MG24 - -config SOC_SERIES - default "efr32mg24" - -config SOC_PART_NUMBER - default "EFR32MG24B220F1536IM48" if SOC_PART_NUMBER_EFR32MG24B220F1536IM48 - default "EFR32MG24B310F1536IM48" if SOC_PART_NUMBER_EFR32MG24B310F1536IM48 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 75 - -config PM - default n - select COUNTER - select UART_INTERRUPT_DRIVEN if SERIAL_SUPPORT_INTERRUPT - -choice PM_POLICY - default PM_POLICY_DEFAULT - depends on PM -endchoice - -endif # SOC_SERIES_EFR32MG24 diff --git a/soc/arm/silabs_exx32/efr32mg24/Kconfig.series b/soc/arm/silabs_exx32/efr32mg24/Kconfig.series deleted file mode 100644 index a57d2237b3d..00000000000 --- a/soc/arm/silabs_exx32/efr32mg24/Kconfig.series +++ /dev/null @@ -1,28 +0,0 @@ -# Silicon Labs EFR32MG24 (Mighty Gecko) MCU - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32MG24 - bool "EFR32MG24 Series MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_CORTEX_M_HAS_DWT - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_SERIES2 - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_DEV_INIT - select SOC_GECKO_SE - select HAS_PM - help - Enable support for EFR32MG24 Mighty Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32mg24/Kconfig.soc b/soc/arm/silabs_exx32/efr32mg24/Kconfig.soc deleted file mode 100644 index 14d5c18d498..00000000000 --- a/soc/arm/silabs_exx32/efr32mg24/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Silicon Labs EFR32MG24 (Mighty Gecko) MCU line - -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32MG24B220F1536IM48 - bool - depends on SOC_SERIES_EFR32MG24 - -config SOC_PART_NUMBER_EFR32MG24B310F1536IM48 - bool - depends on SOC_SERIES_EFR32MG24 diff --git a/soc/arm/silabs_exx32/efr32mg24/soc.h b/soc/arm/silabs_exx32/efr32mg24/soc.h deleted file mode 100644 index a2fd5478c27..00000000000 --- a/soc/arm/silabs_exx32/efr32mg24/soc.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Board configuration macros for the EFR32MG24 SoC - * - */ - -#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_H -#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_H - -#include - -#ifndef _ASMLANGUAGE - -#include - -#include "soc_pinmap.h" -#include "../common/soc_gpio.h" - -/* Add include for DTS generated information */ -#include - -#endif /* !_ASMLANGUAGE */ - -#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_H */ diff --git a/soc/arm/silabs_exx32/efr32mg24/soc_pinmap.h b/soc/arm/silabs_exx32/efr32mg24/soc_pinmap.h deleted file mode 100644 index 6961aeba60d..00000000000 --- a/soc/arm/silabs_exx32/efr32mg24/soc_pinmap.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Silabs EFR32MG24 MCU pin definitions. - * - * This file contains pin configuration data required by different MCU - * modules to correctly configure GPIO controller. - */ - -#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_PINMAP_H_ -#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_PINMAP_H_ - -#include - -#ifdef CONFIG_LOG_BACKEND_SWO -#define PIN_SWO { gpioPortA, 3, gpioModePushPull, 1 } -#endif /* CONFIG_LOG_BACKEND_SWO */ - -#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_PINMAP_H_ */ diff --git a/soc/arm/soc.yml b/soc/arm/soc.yml new file mode 100644 index 00000000000..c0b2456501e --- /dev/null +++ b/soc/arm/soc.yml @@ -0,0 +1,33 @@ +family: +- name: arm + series: + - name: mps2 + socs: + - name: an385 + - name: an521 + cpuclusters: + - name: cpu0 + - name: cpu1 + - name: mps3 + socs: + - name: an547 + - name: musca + socs: + - name: musca_b1 + - name: musca_s1 + - name: designstart + socs: + - name: designstart_fpga_cortex_m1 + - name: designstart_fpga_cortex_m3 +- name: arm64 + series: + - name: fvp_aemv8a + socs: + - name: fvp_base_revc_2xaemv8a + - name: fvp_aemv8r + socs: + - name: fvp_aemv8r_aarch64 + - name: fvp_aemv8r_aarch32 + socs: + - name: qemu_cortex_a53 + - name: qemu_virt_arm64 diff --git a/soc/arm/st_stm32/CMakeLists.txt b/soc/arm/st_stm32/CMakeLists.txt deleted file mode 100644 index 639eff51a00..00000000000 --- a/soc/arm/st_stm32/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) -add_subdirectory(common) - -zephyr_include_directories(common) diff --git a/soc/arm/st_stm32/Kconfig b/soc/arm/st_stm32/Kconfig deleted file mode 100644 index dcdb22ca26b..00000000000 --- a/soc/arm/st_stm32/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -# ST Microelectronics STM32 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_STM32 - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select STM32_ENABLE_DEBUG_SLEEP_STOP if DEBUG || ZTEST - select BUILD_OUTPUT_HEX - -if SOC_FAMILY_STM32 - -config SOC_FAMILY - string - default "st_stm32" - -config STM32_ENABLE_DEBUG_SLEEP_STOP - bool "Allow debugger attach in stop/sleep Mode" - help - Some STM32 parts disable the DBGMCU in sleep/stop modes because - of power consumption. As a side-effects this prevents - debuggers from attaching w/o resetting the target. This - effectivly destroys the use-case of `west attach`. Also - SEGGER RTT and similar technologies need this. - -source "soc/arm/st_stm32/*/Kconfig.soc" - -endif # SOC_FAMILY_STM32 diff --git a/soc/arm/st_stm32/Kconfig.defconfig b/soc/arm/st_stm32/Kconfig.defconfig deleted file mode 100644 index b5232ae4579..00000000000 --- a/soc/arm/st_stm32/Kconfig.defconfig +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/st_stm32/*/Kconfig.defconfig.series" diff --git a/soc/arm/st_stm32/Kconfig.soc b/soc/arm/st_stm32/Kconfig.soc deleted file mode 100644 index b9ea04e5b1c..00000000000 --- a/soc/arm/st_stm32/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# ST Microelectronics STM32 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/st_stm32/*/Kconfig.series" diff --git a/soc/arm/st_stm32/common/CMakeLists.txt b/soc/arm/st_stm32/common/CMakeLists.txt deleted file mode 100644 index af898951cc5..00000000000 --- a/soc/arm/st_stm32/common/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(stm32cube_hal.c) - -zephyr_linker_sources_ifdef(CONFIG_STM32_CCM SECTIONS ccm.ld) - -zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c) -zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld) - -zephyr_sources(soc_config.c) - -if (NOT CONFIG_DEBUG AND CONFIG_PM) - zephyr_sources_ifdef(CONFIG_DT_HAS_SWJ_CONNECTOR_ENABLED pm_debug_swj.c) -endif() diff --git a/soc/arm/st_stm32/common/Kconfig.defconfig.series b/soc/arm/st_stm32/common/Kconfig.defconfig.series deleted file mode 100644 index 5b586516d83..00000000000 --- a/soc/arm/st_stm32/common/Kconfig.defconfig.series +++ /dev/null @@ -1,65 +0,0 @@ -# ST Microelectronics STM32 all MCU lines - -# Copyright (c) 2017, I-SENSE group of ICCS -# SPDX-License-Identifier: Apache-2.0 - -# Here are set all the Kconfig symbols common to the whole STM32 family - -if SOC_FAMILY_STM32 - -config CORTEX_M_SYSTICK - default n if STM32_LPTIM_TIMER - -DT_STM32_RCC_PATH := $(dt_nodelabel_path,rcc) -DT_STM32_RCC_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_RCC_PATH),clock-frequency) - -DT_ST_PRESCALER := st,prescaler -DT_STM32_LPTIM_PATH := $(dt_nodelabel_path,stm32_lp_tick_source) - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" - -if LOG_BACKEND_SWO - -config LOG_BACKEND_SWO_REF_FREQ_HZ - default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" - -endif # LOG_BACKEND_SWO - -# set the tick per sec as a divider of the LPTIM clock source -# with a minimum value of 4096 for SYS_CLOCK_TICKS_PER_SEC to keep -# SYS_CLOCK_TICKS_PER_SEC not too high compared to the LPTIM counter clock -config SYS_CLOCK_TICKS_PER_SEC - default 4096 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16 - default 2048 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16 - default 1024 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32 - default 512 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64 - default 256 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128 - depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSE - -config SYS_CLOCK_TICKS_PER_SEC - default 4000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16 - default 2000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16 - default 1000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32 - default 500 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64 - default 250 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128 - depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSI - -choice STM32_LPTIM_CLOCK - default STM32_LPTIM_CLOCK_LSE if "$(dt_node_ph_array_prop_int,$(DT_STM32_LPTIM_PATH),clocks,1,bus)" = 2 - default STM32_LPTIM_CLOCK_LSI if "$(dt_node_ph_array_prop_int,$(DT_STM32_LPTIM_PATH),clocks,1,bus)" = 3 -endchoice - -config CLOCK_CONTROL_STM32_CUBE - default y - depends on CLOCK_CONTROL - -config CLOCK_CONTROL_INIT_PRIORITY - default 1 - depends on CLOCK_CONTROL - -config MEMC_STM32 - default y - depends on MEMC - -endif # SOC_FAMILY_STM32 diff --git a/soc/arm/st_stm32/common/Kconfig.soc b/soc/arm/st_stm32/common/Kconfig.soc deleted file mode 100644 index 2fd9084cc55..00000000000 --- a/soc/arm/st_stm32/common/Kconfig.soc +++ /dev/null @@ -1,72 +0,0 @@ -# ST Microelectronics Common Kconfig - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CCM := zephyr,ccm - -config STM32_CCM - def_bool $(dt_chosen_enabled,$(DT_CHOSEN_Z_CCM)) - -config STM32_BACKUP_SRAM - bool "STM32 Backup SRAM" - depends on DT_HAS_ST_STM32_BACKUP_SRAM_ENABLED - help - Enable support for STM32 backup SRAM. - -config USE_STM32_ASSERT - depends on ASSERT - bool "STM32Cube HAL and LL drivers asserts" - help - Enable asserts in STM32Cube HAL and LL drivers. - -config SWJ_ANALOG_PRIORITY - int "SWJ DP port to analog routine initialization priority" - default 49 - help - Initialization priority of the routine within the PRE_KERNEL1 level. - This priority must be greater than GPIO_INIT_PRIORITY and lower than - UART_INIT_PRIORITY. - -choice POWER_SUPPLY_CHOICE - prompt "STM32 power supply configuration" - default POWER_SUPPLY_LDO - depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32U5X || \ - SOC_STM32WBA55XX - -config POWER_SUPPLY_LDO - bool "LDO supply" - -config POWER_SUPPLY_DIRECT_SMPS - bool "Direct SMPS supply" - -config POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO - bool "SMPS 1.8V supplies LDO (no external supply)" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO - bool "SMPS 2.5V supplies LDO (no external supply)" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO - bool "External SMPS 1.8V supply, supplies LDO" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO - bool "External SMPS 2.5V supply, supplies LDO" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT - bool "External SMPS 1.8V supply and bypass" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT - bool "External SMPS 2.5V supply and bypass" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_EXTERNAL_SOURCE - bool "Bypass" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -endchoice diff --git a/soc/arm/st_stm32/common/pm_debug_swj.c b/soc/arm/st_stm32/common/pm_debug_swj.c deleted file mode 100644 index 5897670e5f6..00000000000 --- a/soc/arm/st_stm32/common/pm_debug_swj.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2023 STMicroelectronics - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#define SWJ_NODE DT_NODELABEL(swj_port) - -PINCTRL_DT_DEFINE(SWJ_NODE); - -const struct pinctrl_dev_config *swj_pcfg = PINCTRL_DT_DEV_CONFIG_GET(SWJ_NODE); - -/* - * Serial Wire / JTAG port pins are enabled as part of SoC default configuration. - * When debug access is not needed and in case power consumption performance is - * expected, configure matching pins to analog in order to save power. - */ - -static int swj_to_analog(void) -{ - int err; - - /* Set Serial Wire / JTAG port pins to analog mode */ - err = pinctrl_apply_state(swj_pcfg, PINCTRL_STATE_SLEEP); - if (err < 0) { - __ASSERT(0, "SWJ pinctrl setup failed"); - return err; - } - - return 0; -} - -/* Run this routine as the earliest pin configuration in the target, - * to avoid potential conflicts with devices accessing SWJ-DG pins for - * their own needs. - */ -SYS_INIT(swj_to_analog, PRE_KERNEL_1, CONFIG_SWJ_ANALOG_PRIORITY); diff --git a/soc/arm/st_stm32/stm32c0/CMakeLists.txt b/soc/arm/st_stm32/stm32c0/CMakeLists.txt deleted file mode 100644 index e02052e3946..00000000000 --- a/soc/arm/st_stm32/stm32c0/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32c0/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32c0/Kconfig.defconfig.series deleted file mode 100644 index d4ee373c091..00000000000 --- a/soc/arm/st_stm32/stm32c0/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# STMicroelectronics STM32C0 MCU line - -# Copyright (c) 2023 Benjamin Björnsson -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32C0X - -source "soc/arm/st_stm32/stm32c0/Kconfig.defconfig.stm32c0*" - -config SOC_SERIES - default "stm32c0" - -endif # SOC_SERIES_STM32C0X diff --git a/soc/arm/st_stm32/stm32c0/Kconfig.series b/soc/arm/st_stm32/stm32c0/Kconfig.series deleted file mode 100644 index cc69099a6c6..00000000000 --- a/soc/arm/st_stm32/stm32c0/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# STMicroelectronics STM32C0 MCU series - -# Copyright (c) 2023 Benjamin Björnsson -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32C0X - bool "STM32C0x Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_VTOR - select CPU_HAS_ARM_MPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_CORTEX_M_HAS_SYSTICK - help - Enable support for STM32C0 MCU series diff --git a/soc/arm/st_stm32/stm32c0/Kconfig.soc b/soc/arm/st_stm32/stm32c0/Kconfig.soc deleted file mode 100644 index e54678aefff..00000000000 --- a/soc/arm/st_stm32/stm32c0/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# STMicroelectronics STM32C0 MCU line - -# Copyright (c) 2023 Benjamin Björnsson -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32C0x MCU Selection" - depends on SOC_SERIES_STM32C0X - -config SOC_STM32C031XX - bool "STM32C031XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32f0/CMakeLists.txt b/soc/arm/st_stm32/stm32f0/CMakeLists.txt deleted file mode 100644 index 914e395d27a..00000000000 --- a/soc/arm/st_stm32/stm32f0/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# The vector table must be placed at the start of SRAM -zephyr_linker_sources_ifdef(CONFIG_SRAM_VECTOR_TABLE - RAM_SECTIONS - SORT_KEY 0 - sram_vector_table.ld -) -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.series deleted file mode 100644 index c69b3116767..00000000000 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# ST Microelectronics STM32F0 MCU line - -# Copyright (c) 2017 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F0 series - -if SOC_SERIES_STM32F0X - -source "soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f0*" - -config SOC_SERIES - default "stm32f0" - -config SRAM_VECTOR_TABLE - default y - -# adjust the fallback because of the LSI oscaillator characteristics -config TASK_WDT_HW_FALLBACK_DELAY - depends on TASK_WDT_HW_FALLBACK - default 100 - -endif # SOC_SERIES_STM32F0X diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x4 b/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x4 deleted file mode 100644 index 28616f29a2c..00000000000 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x4 +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2019 Antony Pavlov -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F030X4 - -# STM32F0 Cube package advises to use 'stm32f030x6' code -# for both STM32F030x4 and STM32F030x6 SoC variants. -config SOC - default "stm32f030x6" - -config NUM_IRQS - default 28 - -endif # SOC_STM32F030X4 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.series b/soc/arm/st_stm32/stm32f0/Kconfig.series deleted file mode 100644 index ac4e6ced15f..00000000000 --- a/soc/arm/st_stm32/stm32f0/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32F0 MCU series - -# Copyright (c) 2017 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F0X - bool "STM32F0x Series MCU" - select ARM - select CPU_CORTEX_M0 - select CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP - select SOC_FAMILY_STM32 - select CPU_CORTEX_M_HAS_SYSTICK - select HAS_STM32CUBE - help - Enable support for STM32F0 MCU series diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.soc b/soc/arm/st_stm32/stm32f0/Kconfig.soc deleted file mode 100644 index eb82615bb09..00000000000 --- a/soc/arm/st_stm32/stm32f0/Kconfig.soc +++ /dev/null @@ -1,46 +0,0 @@ -# ST Microelectronics STM32F0 MCU line - -# Copyright (c) 2017 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F0x MCU Selection" - depends on SOC_SERIES_STM32F0X - -config SOC_STM32F030X4 - bool "STM32F030X4" - -config SOC_STM32F030X6 - bool "STM32F030X6" - -config SOC_STM32F030X8 - bool "STM32F030X8" - -config SOC_STM32F030XC - bool "STM32F030XC" - -config SOC_STM32F031X6 - bool "STM32F031X6" - -config SOC_STM32F042X6 - bool "STM32F042X6" - -config SOC_STM32F051X8 - bool "STM32F051X8" - -config SOC_STM32F070XB - bool "STM32F070XB" - -config SOC_STM32F072X8 - bool "STM32F072X8" - -config SOC_STM32F072XB - bool "STM32F072XB" - -config SOC_STM32F091XC - bool "STM32F091XC" - -config SOC_STM32F098XX - bool "STM32F098XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32f1/CMakeLists.txt b/soc/arm/st_stm32/stm32f1/CMakeLists.txt deleted file mode 100644 index e02052e3946..00000000000 --- a/soc/arm/st_stm32/stm32f1/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.series deleted file mode 100644 index 5a56f271009..00000000000 --- a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32F1 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F1 series - -if SOC_SERIES_STM32F1X - -source "soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f1*" - -config SOC_SERIES - default "stm32f1" - -# adjust the fallback because of the LSI oscaillator characteristics -config TASK_WDT_HW_FALLBACK_DELAY - depends on TASK_WDT_HW_FALLBACK - default 200 - -endif # SOC_SERIES_STM32F1X diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.series b/soc/arm/st_stm32/stm32f1/Kconfig.series deleted file mode 100644 index 7e9428cd9ca..00000000000 --- a/soc/arm/st_stm32/stm32f1/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32F1 MCU series - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F1X - bool "STM32F1x Series MCU" - select ARM - select CPU_CORTEX_M3 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select HAS_SWO - help - Enable support for STM32F1 MCU series diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.soc b/soc/arm/st_stm32/stm32f1/Kconfig.soc deleted file mode 100644 index 82f9b5100e5..00000000000 --- a/soc/arm/st_stm32/stm32f1/Kconfig.soc +++ /dev/null @@ -1,59 +0,0 @@ -# ST Microelectronics STM32F1 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F1x MCU Selection" - depends on SOC_SERIES_STM32F1X - -config SOC_STM32F100XB - bool "STM32F100XB" - -config SOC_STM32F100XE - bool "STM32F100XE" - -config SOC_STM32F103XE - bool "STM32F103XE" - select SOC_STM32F10X_DENSITY_DEVICE - -config SOC_STM32F103XB - bool "STM32F103XB" - select SOC_STM32F10X_DENSITY_DEVICE - -config SOC_STM32F103X8 - bool "STM32F103X8" - select SOC_STM32F10X_DENSITY_DEVICE - -config SOC_STM32F105XB - bool "STM32F105XB" - select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE - -config SOC_STM32F105XC - bool "STM32F105XC" - select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE - -config SOC_STM32F107XC - bool "STM32F107XC" - select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE - -endchoice - -config SOC_STM32F10X_DENSITY_DEVICE - bool - help - STM32F101xx, STM32F102xx, STM32F103xx: - * Low density Value line devices - * Medium density Value line devices - * High density Value line devices - * XL-density devices Value line devices - -config SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE - bool - help - Connectivity line devices are STM32F105xx and STM32F107xx - microcontrollers. They are intended for applications where - connectivity and real-time performances are required such as - industrial control, control panels for security applications, UPS or - home audio. For STM32F107xx also the Ethernet MAC is available. diff --git a/soc/arm/st_stm32/stm32f2/CMakeLists.txt b/soc/arm/st_stm32/stm32f2/CMakeLists.txt deleted file mode 100644 index e02052e3946..00000000000 --- a/soc/arm/st_stm32/stm32f2/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.series deleted file mode 100644 index 580d4d60084..00000000000 --- a/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32F2 MCU line - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F2 series - -if SOC_SERIES_STM32F2X - -source "soc/arm/st_stm32/stm32f2/Kconfig.defconfig.stm32f2*" - -config SOC_SERIES - default "stm32f2" - -endif # SOC_SERIES_STM32F2X diff --git a/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.stm32f205xx b/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.stm32f205xx deleted file mode 100644 index 46b8acb5286..00000000000 --- a/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.stm32f205xx +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics stm32f205 MCU - -# Copyright (c) 2021 Manuel Forcen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F207XX - -config SOC - default "STM32F207xx" - -config NUM_IRQS - default 81 - -endif diff --git a/soc/arm/st_stm32/stm32f2/Kconfig.series b/soc/arm/st_stm32/stm32f2/Kconfig.series deleted file mode 100644 index 8d2abe1bdfc..00000000000 --- a/soc/arm/st_stm32/stm32f2/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32F2X MCU series - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F2X - bool "STM32F2x Series MCU" - select ARM - select CPU_CORTEX_M3 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select HAS_SWO - select CPU_HAS_ARM_MPU - help - Enable support for stm32f2 MCU series diff --git a/soc/arm/st_stm32/stm32f2/Kconfig.soc b/soc/arm/st_stm32/stm32f2/Kconfig.soc deleted file mode 100644 index 5c6bd453731..00000000000 --- a/soc/arm/st_stm32/stm32f2/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics stm32f2 MCU line - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F2X MCU Selection" - depends on SOC_SERIES_STM32F2X - -config SOC_STM32F207XX - bool "STM32F207XX" - -config SOC_STM32F205XX - bool "STM32F205XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32f3/CMakeLists.txt b/soc/arm/st_stm32/stm32f3/CMakeLists.txt deleted file mode 100644 index e02052e3946..00000000000 --- a/soc/arm/st_stm32/stm32f3/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.series deleted file mode 100644 index 3ed5fd99d14..00000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32F3 MCU line - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F3 series - -if SOC_SERIES_STM32F3X - -source "soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f3*" - -config SOC_SERIES - default "stm32f3" - -endif # SOC_SERIES_STM32F3X diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302x8 b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302x8 deleted file mode 100644 index 8de2724b831..00000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302x8 +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32F302X8 MCU - -# Copyright (c) 2018 Seitz & Associates -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F302X8 - -config SOC - default "stm32f302x8" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F302X8 diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302xc b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302xc deleted file mode 100644 index 5cf16dec891..00000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302xc +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32F302XC MCU - -# Copyright (c) 2022, SECO Spa -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F302XC - -config SOC - default "stm32f302xc" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F302XC diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303xe b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303xe deleted file mode 100644 index 93d98a16cae..00000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303xe +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32F303XC MCU - -# Copyright (c) 2020 Paul M. Bendixen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F303XE - -config SOC - default "stm32f303xe" - -config NUM_IRQS - default 85 - -endif # SOC_STM32F303XE diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f334x8 b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f334x8 deleted file mode 100644 index dfa82aafe94..00000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f334x8 +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32F334X8 MCU - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F334X8 - -config SOC - default "stm32f334x8" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F334X8 diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f373xc b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f373xc deleted file mode 100644 index 713506da309..00000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f373xc +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32F373XC MCU - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F373XC - -config SOC - default "stm32f373xc" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F373XC diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.series b/soc/arm/st_stm32/stm32f3/Kconfig.series deleted file mode 100644 index aab81eb94a9..00000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32F3 MCU series - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F3X - bool "STM32F3x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select CPU_HAS_FPU - select HAS_STM32CUBE - select HAS_SWO - help - Enable support for STM32F3 MCU series diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.soc b/soc/arm/st_stm32/stm32f3/Kconfig.soc deleted file mode 100644 index 20af2538ba5..00000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.soc +++ /dev/null @@ -1,39 +0,0 @@ -# ST Microelectronics STM32F3 MCU line - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F3x MCU Selection" - depends on SOC_SERIES_STM32F3X - -config SOC_STM32F302X8 - bool "STM32F302X8" - -config SOC_STM32F302XC - bool "STM32F302XC" - select CPU_HAS_ARM_MPU - -config SOC_STM32F303X8 - bool "STM32F303X8" - -config SOC_STM32F303XB - bool "STM32F303XB" - select CPU_HAS_ARM_MPU - -config SOC_STM32F303XC - bool "STM32F303XC" - select CPU_HAS_ARM_MPU - -config SOC_STM32F303XE - bool "STM32F303XE" - select CPU_HAS_ARM_MPU - -config SOC_STM32F334X8 - bool "STM32F334X8" - -config SOC_STM32F373XC - bool "STM32F373XC" - select CPU_HAS_ARM_MPU - -endchoice diff --git a/soc/arm/st_stm32/stm32f4/CMakeLists.txt b/soc/arm/st_stm32/stm32f4/CMakeLists.txt deleted file mode 100644 index 021708b9d02..00000000000 --- a/soc/arm/st_stm32/stm32f4/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.series deleted file mode 100644 index 63725609480..00000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.series +++ /dev/null @@ -1,33 +0,0 @@ -# ST Microelectronics STM32F4 MCU line - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F4 series - -if SOC_SERIES_STM32F4X - -source "soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f4*" - -config SOC_SERIES - default "stm32f4" - -# adjust the fallback because of the LSI oscaillator characteristics -config TASK_WDT_HW_FALLBACK_DELAY - depends on TASK_WDT_HW_FALLBACK - default 200 - -if PM - -config COUNTER - default y - -config COUNTER_RTC_STM32_SUBSECONDS - default y if DT_HAS_ST_STM32_RTC_ENABLED - -config IDLE_STACK_SIZE - default 512 - -endif # PM - -endif # SOC_SERIES_STM32F4X diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f405xx b/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f405xx deleted file mode 100644 index 2d516b61bc1..00000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f405xx +++ /dev/null @@ -1,14 +0,0 @@ -# ST STM32F405XX MCU configuration options - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F405XG - -config SOC - default "stm32f405xx" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F405XG diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f407xx b/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f407xx deleted file mode 100644 index c63a7c0c6ab..00000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f407xx +++ /dev/null @@ -1,24 +0,0 @@ -# ST STM32F407XX MCU configuration options - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F407XE - -config SOC - default "stm32f407xx" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F407XE - -if SOC_STM32F407XG - -config SOC - default "stm32f407xx" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F407XG diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412xx b/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412xx deleted file mode 100644 index f66b53c2296..00000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412xx +++ /dev/null @@ -1,34 +0,0 @@ -# ST STM32F412XX MCU configuration options - -# Copyright (c) 2021 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F412CX - -config SOC - default "stm32f412cx" - -config NUM_IRQS - default 97 - -endif # SOC_STM32F412CX - -if SOC_STM32F412VX - -config SOC - default "stm32f412vx" - -config NUM_IRQS - default 97 - -endif # SOC_STM32F412VX - -if SOC_STM32F412ZX - -config SOC - default "stm32f412zx" - -config NUM_IRQS - default 97 - -endif # SOC_STM32F412ZX diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.series b/soc/arm/st_stm32/stm32f4/Kconfig.series deleted file mode 100644 index a4e65c97784..00000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# ST Microelectronics STM32F4 MCU series - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F4X - bool "STM32F4x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select HAS_SWO - select HAS_PM - help - Enable support for STM32F4 MCU series diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.soc b/soc/arm/st_stm32/stm32f4/Kconfig.soc deleted file mode 100644 index ff7dea082ef..00000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.soc +++ /dev/null @@ -1,70 +0,0 @@ -# ST Microelectronics STM32F4 MCU line - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F4x MCU Selection" - depends on SOC_SERIES_STM32F4X - -config SOC_STM32F401XC - bool "STM32F401XC" - -config SOC_STM32F401XE - bool "STM32F401XE" - -config SOC_STM32F405XG - bool "STM32F405XG" - -config SOC_STM32F407XE - bool "STM32F407XE" - -config SOC_STM32F407XG - bool "STM32F407XG" - -config SOC_STM32F410RX - bool "STM32F410RX" - -config SOC_STM32F411XE - bool "STM32F411XE" - -config SOC_STM32F412CX - bool "STM32F412CX" - -config SOC_STM32F412RX - bool "STM32F412RX" - -config SOC_STM32F412VX - bool "STM32F412VX" - -config SOC_STM32F412ZX - bool "STM32F412ZX" - -config SOC_STM32F413XX - bool "STM32F413XX" - -config SOC_STM32F415XX - bool "STM32F415XX" - -config SOC_STM32F417XX - bool "STM32F417XX" - -config SOC_STM32F423XX - bool "STM32F423XX" - -config SOC_STM32F427XX - bool "STM32F427XI" - -config SOC_STM32F429XX - bool "STM32F429XI" - -config SOC_STM32F437XX - bool "STM32F437XX" - -config SOC_STM32F446XX - bool "STM32F446XX" - -config SOC_STM32F469XX - bool "STM32F469XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32f7/CMakeLists.txt b/soc/arm/st_stm32/stm32f7/CMakeLists.txt deleted file mode 100644 index e02052e3946..00000000000 --- a/soc/arm/st_stm32/stm32f7/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.series deleted file mode 100644 index 55af12c6678..00000000000 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32F7 MCU line - -# Copyright (c) 2018 Yurii Hamann -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F7 series - -if SOC_SERIES_STM32F7X - -source "soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f7*" - -config SOC_SERIES - default "stm32f7" - -endif # SOC_SERIES_STM32F7X diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.series b/soc/arm/st_stm32/stm32f7/Kconfig.series deleted file mode 100644 index a298fa2b579..00000000000 --- a/soc/arm/st_stm32/stm32f7/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# ST Microelectronics STM32F7 MCU series - -# Copyright (c) 2018 Yurii Hamann -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F7X - bool "STM32F7x Series MCU" - select ARM - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select HAS_SWO - help - Enable support for STM32F7 MCU series diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.soc b/soc/arm/st_stm32/stm32f7/Kconfig.soc deleted file mode 100644 index c83a9962a60..00000000000 --- a/soc/arm/st_stm32/stm32f7/Kconfig.soc +++ /dev/null @@ -1,43 +0,0 @@ -# ST Microelectronics STM32F7 MCU line - -# Copyright (c) 2018 Yurii Hamann -# Copyright (c) 2022, Rtone. -# Copyright (c) 2023, Rahul Arasikere. -# Copyright (c) 2023 Evan Perry Grove -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F7x MCU Selection" - depends on SOC_SERIES_STM32F7X - -config SOC_STM32F722XX - bool "STM32F722XX" - -config SOC_STM32F723XX - bool "STM32F723XX" - -config SOC_STM32F745XX - bool "STM32F745XX" - -config SOC_STM32F746XX - bool "STM32F746XX" - -config SOC_STM32F756XX - bool "STM32F756XX" - -config SOC_STM32F750XX - bool "STM32F750XX" - -config SOC_STM32F765XX - bool "STM32F765XX" - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32F767XX - bool "STM32F767XX" - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32F769XX - bool "STM32F769XX" - select CPU_HAS_FPU_DOUBLE_PRECISION - -endchoice diff --git a/soc/arm/st_stm32/stm32g0/CMakeLists.txt b/soc/arm/st_stm32/stm32g0/CMakeLists.txt deleted file mode 100644 index 85869a31ddf..00000000000 --- a/soc/arm/st_stm32/stm32g0/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2021 G-Technologies Sdn. Bhd. -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series deleted file mode 100644 index 1fc5e19565a..00000000000 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# STMicroelectronics STM32G0 MCU line - -# Copyright (c) 2019 Philippe Retornaz -# Copyright (c) 2019 STMicroelectronics -# Copyright (c) 2021 G-Technologies Sdn. Bhd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32G0X - -source "soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0*" - -config SOC_SERIES - default "stm32g0" - -endif # SOC_SERIES_STM32G0X diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.series b/soc/arm/st_stm32/stm32g0/Kconfig.series deleted file mode 100644 index acdb926ef61..00000000000 --- a/soc/arm/st_stm32/stm32g0/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# STMicroelectronics STM32G0 MCU series - -# Copyright (c) 2019 Philippe Retornaz -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32G0X - bool "STM32G0x Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_VTOR - select CPU_HAS_ARM_MPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_CORTEX_M_HAS_SYSTICK - select HAS_PM - help - Enable support for STM32G0 MCU series diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.soc b/soc/arm/st_stm32/stm32g0/Kconfig.soc deleted file mode 100644 index 592290e2fb9..00000000000 --- a/soc/arm/st_stm32/stm32g0/Kconfig.soc +++ /dev/null @@ -1,48 +0,0 @@ -# STMicroelectronics STM32G0 MCU line - -# Copyright (c) 2019 Philippe Retornaz -# Copyright (c) 2019 STMicroelectronics -# Copyright (c) 2020 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32G0x MCU Selection" - depends on SOC_SERIES_STM32G0X - -config SOC_STM32G030XX - bool "STM32G030XX" - -config SOC_STM32G031XX - bool "STM32G031XX" - -config SOC_STM32G041XX - bool "STM32G041XX" - -config SOC_STM32G050XX - bool "STM32G050XX" - -config SOC_STM32G051XX - bool "STM32G051XX" - -config SOC_STM32G061XX - bool "STM32G061XX" - -config SOC_STM32G070XX - bool "STM32G070XX" - -config SOC_STM32G071XX - bool "STM32G071XX" - -config SOC_STM32G081XX - bool "STM32G081XX" - -config SOC_STM32G0B0XX - bool "STM32G0B0XX" - -config SOC_STM32G0B1XX - bool "STM32G0B1XX" - -config SOC_STM32G0C1XX - bool "STM32G0C1XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32g4/CMakeLists.txt b/soc/arm/st_stm32/stm32g4/CMakeLists.txt deleted file mode 100644 index 04911a6a2e4..00000000000 --- a/soc/arm/st_stm32/stm32g4/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series deleted file mode 100644 index 14ca585fc11..00000000000 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# STMicroelectronics STM32G4 MCU line - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32G4X - -source "soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g4*" - -config SOC_SERIES - default "stm32g4" - -if PM -config PM_DEVICE - default y - -config STM32_LPTIM_TIMER - default y -endif # PM - -endif # SOC_SERIES_STM32G4X diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g431rb b/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g431rb deleted file mode 100644 index 90a68ce0b6d..00000000000 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g431rb +++ /dev/null @@ -1,14 +0,0 @@ -# STMicroelectronics STM32G431RB MCU - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32G431XX - -config SOC - default "stm32g431xx" - -config NUM_IRQS - default 102 - -endif # SOC_STM32G431XX diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g474re b/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g474re deleted file mode 100644 index 78bca517cc1..00000000000 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g474re +++ /dev/null @@ -1,14 +0,0 @@ -# STMicroelectronics STM32G474RE MCU - -# Copyright (c) 2019 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32G474XX - -config SOC - default "stm32g474xx" - -config NUM_IRQS - default 102 - -endif # SOC_STM32G474XX diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.series b/soc/arm/st_stm32/stm32g4/Kconfig.series deleted file mode 100644 index f04432c3ee3..00000000000 --- a/soc/arm/st_stm32/stm32g4/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# STMicroelectronics STM32G4 MCU series - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32G4X - bool "STM32G4x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL - select HAS_PM - select HAS_SWO - help - Enable support for STM32G4 MCU series diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.soc b/soc/arm/st_stm32/stm32g4/Kconfig.soc deleted file mode 100644 index 9868522fc31..00000000000 --- a/soc/arm/st_stm32/stm32g4/Kconfig.soc +++ /dev/null @@ -1,34 +0,0 @@ -# STMicroelectronics STM32G4 MCU line - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32G4x MCU Selection" - depends on SOC_SERIES_STM32G4X - -config SOC_STM32G4A1XX - bool "STM32G4A1XX" - -config SOC_STM32G431XX - bool "STM32G431XX" - -config SOC_STM32G441XX - bool "STM32G441XX" - -config SOC_STM32G473XX - bool "STM32G473XX" - -config SOC_STM32G474XX - bool "STM32G474XX" - -config SOC_STM32G483XX - bool "STM32G483XX" - -config SOC_STM32G484XX - bool "STM32G484XX" - -config SOC_STM32G491XX - bool "STM32G491XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32g4/soc.c b/soc/arm/st_stm32/stm32g4/soc.c deleted file mode 100644 index 94600c48327..00000000000 --- a/soc/arm/st_stm32/stm32g4/soc.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2019 Richard Osterloh - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief System/hardware module for STM32G4 processor - */ - -#include -#include -#include - -#include -#if defined(PWR_CR3_UCPD_DBDIS) -#include -#include -#endif /* PWR_CR3_UCPD_DBDIS */ - -/** - * @brief Perform basic hardware initialization at boot. - * - * This needs to be run from the very beginning. - * So the init priority has to be 0 (zero). - * - * @return 0 - */ -static int stm32g4_init(void) -{ - /* Update CMSIS SystemCoreClock variable (HCLK) */ - /* At reset, system core clock is set to 16 MHz from HSI */ - SystemCoreClock = 16000000; - - /* allow reflashing board */ - LL_DBGMCU_EnableDBGSleepMode(); - -#if defined(PWR_CR3_UCPD_DBDIS) - /* Disable USB Type-C dead battery pull-down behavior */ - LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); - LL_PWR_DisableUCPDDeadBattery(); -#endif /* PWR_CR3_UCPD_DBDIS */ - return 0; -} - -SYS_INIT(stm32g4_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/st_stm32/stm32h5/CMakeLists.txt b/soc/arm/st_stm32/stm32h5/CMakeLists.txt deleted file mode 100644 index e02052e3946..00000000000 --- a/soc/arm/st_stm32/stm32h5/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.series deleted file mode 100644 index 201694ed708..00000000000 --- a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32H5 MCU line - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32H5X - -source "soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h5*" - -config SOC_SERIES - default "stm32h5" - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -endif # SOC_SERIES_STM32H5X diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.series b/soc/arm/st_stm32/stm32h5/Kconfig.series deleted file mode 100644 index cb84b08b250..00000000000 --- a/soc/arm/st_stm32/stm32h5/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32H5 MCU series - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32H5X - bool "STM32H5x Series MCU" - select ARM - select CPU_CORTEX_M33 - select SOC_FAMILY_STM32 - select ARM_TRUSTZONE_M if !SOC_STM32H503XX - select CPU_HAS_ARM_SAU if !SOC_STM32H503XX - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CPU_CORTEX_M_HAS_DWT - select HAS_STM32CUBE - select HAS_SWO - help - Enable support for STM32H5 MCU series diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.soc b/soc/arm/st_stm32/stm32h5/Kconfig.soc deleted file mode 100644 index 3bf6a3605c0..00000000000 --- a/soc/arm/st_stm32/stm32h5/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# ST Microelectronics STM32H5 MCU line - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "STM32H5x MCU Selection" -depends on SOC_SERIES_STM32H5X - -config SOC_STM32H503XX - bool "STM32H503XX" - -config SOC_STM32H562XX - bool "STM32H562XX" - -config SOC_STM32H563XX - bool "STM32H563XX" - -config SOC_STM32H573XX - bool "STM32H573XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32h7/CMakeLists.txt b/soc/arm/st_stm32/stm32h7/CMakeLists.txt deleted file mode 100644 index d1ae6c3325d..00000000000 --- a/soc/arm/st_stm32/stm32h7/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c) -zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M4 soc_m4.c) - -zephyr_sources(mpu_regions.c) -zephyr_linker_sources(SECTIONS sections.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.series deleted file mode 100644 index 14e35234ea1..00000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32H7 MCU line - -# Copyright (c) 2019 Linaro Limited -# Copyright (c) 2022 SILA Embedded Solutions GmbH -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32H7 series - -if SOC_SERIES_STM32H7X - -source "soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7*" - -config SOC_SERIES - default "stm32h7" - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - default 0x0 if !BOOTLOADER_MCUBOOT - -endif # SOC_SERIES_STM32H7X diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h745xx b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h745xx deleted file mode 100644 index c6279b99028..00000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h745xx +++ /dev/null @@ -1,14 +0,0 @@ -# ST STM32H745X MCU configuration options - -# Copyright (c) 2020 Alexander Kozhinov -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32H745XX - -config SOC - default "stm32h745xx" - -config NUM_IRQS - default 150 - -endif # SOC_STM32H745XX diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h747xx b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h747xx deleted file mode 100644 index 73b7c9ea7ce..00000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h747xx +++ /dev/null @@ -1,14 +0,0 @@ -# ST STM32H747X MCU configuration options - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32H747XX - -config SOC - default "stm32h747xx" - -config NUM_IRQS - default 150 - -endif # SOC_STM32H747XX diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7a3xx b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7a3xx deleted file mode 100644 index e82faa90bda..00000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7a3xx +++ /dev/null @@ -1,15 +0,0 @@ -# ST STM32H7A3X MCU configuration options - -# Copyright (c) 2021 Electrolance Solutions -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32H7A3XX || SOC_STM32H7A3XXQ - -config SOC - default "stm32h7a3xxQ" if SOC_STM32H7A3XXQ - default "stm32h7a3xx" if SOC_STM32H7A3XX - -config NUM_IRQS - default 155 - -endif # SOC_STM32H7A3XX || SOC_STM32H7A3XXQ diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b0xx b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b0xx deleted file mode 100644 index 10502135014..00000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b0xx +++ /dev/null @@ -1,15 +0,0 @@ -# ST STM32H7B0XX MCU configuration options - -# Copyright (c) 2023 Charles Dias -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32H7B0XX || SOC_STM32H7B0XXQ - -config SOC - default "stm32h7b0xxQ" if SOC_STM32H7B0XXQ - default "stm32h7b0xx" if SOC_STM32H7B0XX - -config NUM_IRQS - default 155 - -endif # SOC_STM32H7B0XX || SOC_STM32H7B0XXQ diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b3xx b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b3xx deleted file mode 100644 index 941c6ad5e50..00000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b3xx +++ /dev/null @@ -1,15 +0,0 @@ -# ST STM32H7B3X MCU configuration options - -# Copyright (c) 2022 Byte-Lab d.o.o -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32H7B3XX || SOC_STM32H7B3XXQ - -config SOC - default "stm32h7b3xxQ" if SOC_STM32H7B3XXQ - default "stm32h7b3xx" if SOC_STM32H7B3XX - -config NUM_IRQS - default 155 - -endif # SOC_STM32H7B3XX || SOC_STM32H7B3XXQ diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.series b/soc/arm/st_stm32/stm32h7/Kconfig.series deleted file mode 100644 index 061a23856c2..00000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# ST Microelectronics STM32H7 MCU series - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32H7X - bool "STM32H7x Series MCU" - select ARM - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select HAS_SWO - select USE_STM32_HAL_CORTEX - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - help - Enable support for STM32H7 MCU series diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.soc b/soc/arm/st_stm32/stm32h7/Kconfig.soc deleted file mode 100644 index 4f7441a6fdc..00000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.soc +++ /dev/null @@ -1,132 +0,0 @@ -# ST Microelectronics STM32H7 MCU line - -# Copyright (c) 2019 Linaro Limited -# Copyright (c) 2020 Teslabs Engineering S.L. -# Copyright (c) 2021 Electrolance Solutions -# SPDX-License-Identifier: Apache-2.0 - -config STM32H7_DUAL_CORE - bool "Dual Core" - depends on SOC_SERIES_STM32H7X - -choice - prompt "STM32H7x MCU Selection" - depends on SOC_SERIES_STM32H7X - -config SOC_STM32H723XX - bool "STM32H723XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H725XX - bool "STM32H725XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H730XX - bool "STM32H730XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H730XXQ - bool "STM32H730XXQ" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H735XX - bool "STM32H735XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H743XX - bool "STM32H743XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H745XX - bool "STM32H745XX" - select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7 - select CPU_HAS_ICACHE if CPU_CORTEX_M7 - select CPU_HAS_DCACHE if CPU_CORTEX_M7 - select STM32H7_DUAL_CORE - -config SOC_STM32H747XX - bool "STM32H747XX" - select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7 - select CPU_HAS_ICACHE if CPU_CORTEX_M7 - select CPU_HAS_DCACHE if CPU_CORTEX_M7 - select STM32H7_DUAL_CORE - -config SOC_STM32H750XX - bool "STM32H750XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H753XX - bool "STM32H753XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7A3XX - bool "STM32H7A3XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7A3XXQ - bool "STM32H7A3XXQ" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7B0XX - bool "STM32H7B0XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7B0XXQ - bool "STM32H7B0XXQ" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7B3XX - bool "STM32H7B3XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7B3XXQ - bool "STM32H7B3XXQ" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -endchoice - -config STM32H7_BOOT_M4_AT_INIT - bool "Boot M4 core during M7 init independent of option byte BCM4." - default y diff --git a/soc/arm/st_stm32/stm32l0/CMakeLists.txt b/soc/arm/st_stm32/stm32l0/CMakeLists.txt deleted file mode 100644 index 0fd5073770d..00000000000 --- a/soc/arm/st_stm32/stm32l0/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.series deleted file mode 100644 index 1f9dbd93338..00000000000 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32L0 MCU line - -# Copyright (c) 2018 Endre Karlson -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32L0 series - -if SOC_SERIES_STM32L0X - -source "soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l0*" - -config SOC_SERIES - default "stm32l0" - -# adjust the fallback because of the LSI oscaillator characteristics -config TASK_WDT_HW_FALLBACK_DELAY - depends on TASK_WDT_HW_FALLBACK - default 200 - -endif # SOC_SERIES_STM32L0X diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.series b/soc/arm/st_stm32/stm32l0/Kconfig.series deleted file mode 100644 index 950c72d4aa7..00000000000 --- a/soc/arm/st_stm32/stm32l0/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32L0 MCU series - -# Copyright (c) 2018 Endre Karlson -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32L0X - bool "STM32L0x Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_CORTEX_M_HAS_SYSTICK - select HAS_PM - help - Enable support for STM32L0 MCU series diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.soc b/soc/arm/st_stm32/stm32l0/Kconfig.soc deleted file mode 100644 index 0baab0cf2b9..00000000000 --- a/soc/arm/st_stm32/stm32l0/Kconfig.soc +++ /dev/null @@ -1,55 +0,0 @@ -# ST Microelectronics STM32L0 MCU line - -# Copyright (c) 2018 Endre Karlson -# Copyright (c) 2021 Nomono AS -# Copyright (c) 2023 OS Systems -# -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32L0x MCU Selection" - depends on SOC_SERIES_STM32L0X - -config SOC_STM32L010X4 - bool "STM32L010X4" - -config SOC_STM32L010X6 - bool "STM32L010X6" - -config SOC_STM32L010X8 - bool "STM32L010X8" - -config SOC_STM32L010XB - bool "STM32L010XB" - -config SOC_STM32L011XX - bool "STM32L011XX" - -config SOC_STM32L031XX - bool "STM32L031XX" - -config SOC_STM32L051XX - bool "STM32L051XX" - select CPU_HAS_ARM_MPU - -config SOC_STM32L053XX - bool "STM32L053XX" - select CPU_HAS_ARM_MPU - -config SOC_STM32L071XX - bool "STM32L071XX" - select CPU_HAS_ARM_MPU - -config SOC_STM32L072XX - bool "STM32L072XX" - select CPU_HAS_ARM_MPU - -config SOC_STM32L073XX - bool "STM32L073XX" - select CPU_HAS_ARM_MPU - -config SOC_STM32L081XX - bool "STM32L081XX" - select CPU_HAS_ARM_MPU - -endchoice diff --git a/soc/arm/st_stm32/stm32l1/CMakeLists.txt b/soc/arm/st_stm32/stm32l1/CMakeLists.txt deleted file mode 100644 index 68bf00e81c1..00000000000 --- a/soc/arm/st_stm32/stm32l1/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.series deleted file mode 100644 index 873acabf34c..00000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# ST Microelectronics STM32L1 MCU line - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32L1X - -source "soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l1*" - -config SOC_SERIES - default "stm32l1" - -# adjust the fallback because of the LSI oscaillator characteristics -config TASK_WDT_HW_FALLBACK_DELAY - depends on TASK_WDT_HW_FALLBACK - default 200 - -endif # SOC_SERIES_STM32L1X diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151x8a b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151x8a deleted file mode 100644 index cebe7f6b32c..00000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151x8a +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32L151X8-A MCU - -# Copyright (c) 2019 eTactica ehf -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32L151X8A - -config SOC - default "stm32l151x8a" - -config NUM_IRQS - default 45 - -endif # SOC_STM32L151X8A diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xb b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xb deleted file mode 100644 index f86cb99e14b..00000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xb +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32L151XB MCU - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32L151XB - -config SOC - default "stm32l151xb" - -config NUM_IRQS - default 45 - -endif # SOC_STM32L151XB diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xba b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xba deleted file mode 100644 index b93b1e9dd28..00000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xba +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32L151XB-A MCU - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32L151XBA - -config SOC - default "stm32l151xba" - -config NUM_IRQS - default 45 - -endif # SOC_STM32L151XBA diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xc b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xc deleted file mode 100644 index af0ce69ba01..00000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xc +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32L151XC MCU - -# Copyright (c) 2020 Abel Sensors -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32L151XC - -config SOC - default "stm32l151xc" - -# Based on stm32cube number of interrupts+1, not datasheet -config NUM_IRQS - default 57 - -endif # SOC_STM32L151XC diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xc b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xc deleted file mode 100644 index c0f87fe11ff..00000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xc +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32L152XC MCU - -# Copyright (c) 2020 Abel Sensors -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32L152XC - -config SOC - string - default "stm32l152xc" - -config NUM_IRQS - int - default 57 - -endif # SOC_STM32L152XC diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.series b/soc/arm/st_stm32/stm32l1/Kconfig.series deleted file mode 100644 index d21881d6128..00000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32L1 MCU series - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32L1X - bool "STM32L1x Series MCU" - select ARM - select CPU_CORTEX_M3 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select HAS_SWO - select CPU_HAS_ARM_MPU - help - Enable support for STM32L1 MCU series diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.soc b/soc/arm/st_stm32/stm32l1/Kconfig.soc deleted file mode 100644 index 07cffb5b3b0..00000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.soc +++ /dev/null @@ -1,28 +0,0 @@ -# ST Microelectronics STM32L1 MCU line - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32L1x MCU Selection" - depends on SOC_SERIES_STM32L1X - -config SOC_STM32L151X8A - bool "STM32L151X8A" - -config SOC_STM32L151XB - bool "STM32L151XB" - -config SOC_STM32L151XBA - bool "STM32L151XBA" - -config SOC_STM32L151XC - bool "STM32L151XC" - -config SOC_STM32L152XC - bool "STM32L152XC" - -config SOC_STM32L152XE - bool "STM32L152XE" - -endchoice diff --git a/soc/arm/st_stm32/stm32l4/CMakeLists.txt b/soc/arm/st_stm32/stm32l4/CMakeLists.txt deleted file mode 100644 index 94edc262274..00000000000 --- a/soc/arm/st_stm32/stm32l4/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.series deleted file mode 100644 index 481726f0b72..00000000000 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32L4 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32L4 series - -if SOC_SERIES_STM32L4X - -source "soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4*" - -config SOC_SERIES - default "stm32l4" - -endif # SOC_SERIES_STM32L4X diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.series b/soc/arm/st_stm32/stm32l4/Kconfig.series deleted file mode 100644 index 6ac4f1e704c..00000000000 --- a/soc/arm/st_stm32/stm32l4/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32L4 MCU series - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32L4X - bool "STM32L4x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select HAS_SWO - select HAS_PM - select HAS_POWEROFF - help - Enable support for STM32L4 MCU series diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.soc b/soc/arm/st_stm32/stm32l4/Kconfig.soc deleted file mode 100644 index 9719ff4b73d..00000000000 --- a/soc/arm/st_stm32/stm32l4/Kconfig.soc +++ /dev/null @@ -1,70 +0,0 @@ -# ST Microelectronics STM32L4 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# Copyright (c) 2019 Centaur Analytics, Inc -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32L4x MCU Selection" - depends on SOC_SERIES_STM32L4X - -config SOC_STM32L476XX - bool "STM32L476XX" - -config SOC_STM32L486XX - bool "STM32L486XX" - -config SOC_STM32L496XX - bool "STM32L496XX" - -config SOC_STM32L4A6XX - bool "STM32L4A6XX" - -config SOC_STM32L412XX - bool "STM32L412XX" - -config SOC_STM32L422XX - bool "STM32L422XX" - -config SOC_STM32L431XX - bool "STM32L431XX" - -config SOC_STM32L432XX - bool "STM32L432XX" - -config SOC_STM32L433XX - bool "STM32L433XX" - -config SOC_STM32L451XX - bool "STM32L451XX" - -config SOC_STM32L452XX - bool "STM32L452XX" - -config SOC_STM32L462XX - bool "STM32L462XX" - -config SOC_STM32L475XX - bool "STM32L475XX" - -config SOC_STM32L4P5XX - bool "STM32L4P5XX" - -config SOC_STM32L4Q5XX - bool "STM32L4Q5XX" - -config SOC_STM32L4S5XX - bool "STM32L4S5XX" - -config SOC_STM32L4R5XX - bool "STM32L4R5XX" - -config SOC_STM32L4R9XX - bool "STM32L4R9XX" - -config SOC_STM32L471XX - bool "STM32L471XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32l5/CMakeLists.txt b/soc/arm/st_stm32/stm32l5/CMakeLists.txt deleted file mode 100644 index 0fd5073770d..00000000000 --- a/soc/arm/st_stm32/stm32l5/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.series deleted file mode 100644 index 0b92f5dda29..00000000000 --- a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# ST Microelectronics STM32L5 MCU line - -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32L5X - -source "soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l5*" - -config SOC_SERIES - default "stm32l5" - -endif # SOC_SERIES_STM32L5X diff --git a/soc/arm/st_stm32/stm32l5/Kconfig.series b/soc/arm/st_stm32/stm32l5/Kconfig.series deleted file mode 100644 index ffee96473c3..00000000000 --- a/soc/arm/st_stm32/stm32l5/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32L5 MCU series - -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32L5X - bool "STM32L5x Series MCU" - select ARM - select CPU_CORTEX_M33 - select SOC_FAMILY_STM32 - select ARM_TRUSTZONE_M - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CPU_CORTEX_M_HAS_DWT - select HAS_STM32CUBE - select HAS_PM - help - Enable support for STM32L5 MCU series diff --git a/soc/arm/st_stm32/stm32l5/Kconfig.soc b/soc/arm/st_stm32/stm32l5/Kconfig.soc deleted file mode 100644 index c93746ca488..00000000000 --- a/soc/arm/st_stm32/stm32l5/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32L5 MCU line - -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "STM32L5x MCU Selection" -depends on SOC_SERIES_STM32L5X - -config SOC_STM32L552XX - bool "STM32L552XX" - -config SOC_STM32L562XX - bool "STM32L562XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32mp1/CMakeLists.txt b/soc/arm/st_stm32/stm32mp1/CMakeLists.txt deleted file mode 100644 index 7805c0ffbf2..00000000000 --- a/soc/arm/st_stm32/stm32mp1/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2019 STMicroelectronics -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series deleted file mode 100644 index 72c6b452c5d..00000000000 --- a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# ST Microelectronics STM32MP1 MCU/MPU line - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32MP1X - -source "soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.stm32mp15_m4" - -config SOC_SERIES - default "stm32mp1" - -endif # SOC_SERIES_STM32MP1X diff --git a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.stm32mp15_m4 b/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.stm32mp15_m4 deleted file mode 100644 index 20dd43378f7..00000000000 --- a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.stm32mp15_m4 +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32MP157C_M4 MCU - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32MP15_M4 - -config SOC - default "stm32mp157cxx" - -config NUM_IRQS - default 150 - -endif # SOC_STM32MP15_M4 diff --git a/soc/arm/st_stm32/stm32mp1/Kconfig.series b/soc/arm/st_stm32/stm32mp1/Kconfig.series deleted file mode 100644 index c1576a7ee17..00000000000 --- a/soc/arm/st_stm32/stm32mp1/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# ST Microelectronics STM32MP1 MPU series - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32MP1X - bool "STM32MP15 Series MPU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select OPENAMP_RSC_TABLE if RAM_CONSOLE - help - Enable support for STM32MP1 MPU series diff --git a/soc/arm/st_stm32/stm32mp1/Kconfig.soc b/soc/arm/st_stm32/stm32mp1/Kconfig.soc deleted file mode 100644 index 18e4202ae5f..00000000000 --- a/soc/arm/st_stm32/stm32mp1/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# ST Microelectronics STM32MP1 MPU line - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32MP1 MPU Selection" - depends on SOC_SERIES_STM32MP1X - -config SOC_STM32MP15_M4 - bool "STM32MP15_M4" - -endchoice diff --git a/soc/arm/st_stm32/stm32u5/CMakeLists.txt b/soc/arm/st_stm32/stm32u5/CMakeLists.txt deleted file mode 100644 index 94edc262274..00000000000 --- a/soc/arm/st_stm32/stm32u5/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.series deleted file mode 100644 index e867bd5f4c9..00000000000 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32U5 MCU line - -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32U5X - -source "soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5*" - -config SOC_SERIES - default "stm32u5" - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -endif # SOC_SERIES_STM32U5X diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.series b/soc/arm/st_stm32/stm32u5/Kconfig.series deleted file mode 100644 index 81094811b38..00000000000 --- a/soc/arm/st_stm32/stm32u5/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# ST Microelectronics STM32U5 MCU series - -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32U5X - bool "STM32U5x Series MCU" - select ARM - select CPU_CORTEX_M33 - select SOC_FAMILY_STM32 - select ARM_TRUSTZONE_M - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CPU_CORTEX_M_HAS_DWT - select HAS_STM32CUBE - select HAS_PM - select HAS_POWEROFF - help - Enable support for STM32U5 MCU series diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.soc b/soc/arm/st_stm32/stm32u5/Kconfig.soc deleted file mode 100644 index ec8c964ad3e..00000000000 --- a/soc/arm/st_stm32/stm32u5/Kconfig.soc +++ /dev/null @@ -1,30 +0,0 @@ -# ST Microelectronics STM32U5 MCU line - -# Copyright (c) 2021 Linaro Limited -# Copyright (c) 2023 PSICONTROL nv -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "STM32U5x MCU Selection" -depends on SOC_SERIES_STM32U5X - -config SOC_STM32U575XX - bool "STM32U575XX" - -config SOC_STM32U585XX - bool "STM32U585XX" - -config SOC_STM32U595XX - bool "STM32U595XX" - -config SOC_STM32U599XX - bool "STM32U599XX" - -config SOC_STM32U5A5XX - bool "STM32U5A5XX" - -config SOC_STM32U5A9XX - bool "STM32U5A9XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32wb/CMakeLists.txt b/soc/arm/st_stm32/stm32wb/CMakeLists.txt deleted file mode 100644 index 32ce62ee530..00000000000 --- a/soc/arm/st_stm32/stm32wb/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_linker_sources_ifdef(CONFIG_BT_STM32_IPM - SECTIONS - ipm.ld - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series deleted file mode 100644 index 748d91394e5..00000000000 --- a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32WB MCU line - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32WBX - -source "soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb*" - -config SOC_SERIES - default "stm32wb" - -config BT_USER_PHY_UPDATE - default y if BT - -endif # SOC_SERIES_STM32WBX diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.series b/soc/arm/st_stm32/stm32wb/Kconfig.series deleted file mode 100644 index a0192ae4e6c..00000000000 --- a/soc/arm/st_stm32/stm32wb/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# ST Microelectronics STM32WB MCU series - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32WBX - bool "STM32WBx Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select HAS_SWO - select HAS_PM - select HAS_POWEROFF - help - Enable support for STM32WB MCU series diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.soc b/soc/arm/st_stm32/stm32wb/Kconfig.soc deleted file mode 100644 index df65225d311..00000000000 --- a/soc/arm/st_stm32/stm32wb/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# ST Microelectronics STM32WB MCU line - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32WBx MCU Selection" - depends on SOC_SERIES_STM32WBX - -config SOC_STM32WB55XX - bool "STM32WB55XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32wba/CMakeLists.txt b/soc/arm/st_stm32/stm32wba/CMakeLists.txt deleted file mode 100644 index d26c143f8f6..00000000000 --- a/soc/arm/st_stm32/stm32wba/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -if(CONFIG_BT_STM32WBA) - zephyr_include_directories(hci_if) - - zephyr_sources(hci_if/linklayer_plat.c) - zephyr_sources(hci_if/bleplat.c) - zephyr_sources(hci_if/host_stack_if.c) - zephyr_sources(hci_if/ll_sys_if.c) - zephyr_sources(hci_if/stm32_timer.c) -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.series deleted file mode 100644 index 340b62049e8..00000000000 --- a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.series +++ /dev/null @@ -1,64 +0,0 @@ -# ST Microelectronics STM32WBA MCU line - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32WBAX - -source "soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba*" - -config SOC_SERIES - default "stm32wba" - -config STM32_LPTIM_TIMER - default y if PM - -choice BT_HCI_BUS_TYPE - default BT_STM32WBA - depends on BT -endchoice - -config BT_STM32WBA - select DYNAMIC_INTERRUPTS - select DYNAMIC_DIRECT_INTERRUPTS - select ENTROPY_GENERATOR - select USE_STM32_HAL_RAMCFG - -if BT_STM32WBA - -choice LIBC_IMPLEMENTATION - default NEWLIB_LIBC -endchoice - -choice LINKER_ORPHAN_CONFIGURATION - default LINKER_ORPHAN_SECTION_PLACE -endchoice - -config ENTROPY_STM32_CLK_CHECK - default n - -endif - -if PM_S2RAM - -config COUNTER - default y - -config COUNTER_RTC_STM32_SUBSECONDS - default y - -config STM32_LPTIM_STDBY_TIMER - default y - -config TICKLESS_KERNEL - default y - -config COUNTER_RTC_STM32_SAVE_VALUE_BETWEEN_RESETS - default y - -config IDLE_STACK_SIZE - default 512 - -endif - -endif # SOC_SERIES_STM32WBAX diff --git a/soc/arm/st_stm32/stm32wba/Kconfig.series b/soc/arm/st_stm32/stm32wba/Kconfig.series deleted file mode 100644 index 5cdaaa7e672..00000000000 --- a/soc/arm/st_stm32/stm32wba/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# ST Microelectronics STM32WBA MCU series - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32WBAX - bool "STM32WBAx Series MCU" - select ARM - select CPU_CORTEX_M33 - select SOC_FAMILY_STM32 - select ARM_TRUSTZONE_M - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CPU_CORTEX_M_HAS_DWT - select HAS_STM32CUBE - select USE_STM32_HAL_PWR_EX - select HAS_PM - help - Enable support for STM32WBA MCU series diff --git a/soc/arm/st_stm32/stm32wba/Kconfig.soc b/soc/arm/st_stm32/stm32wba/Kconfig.soc deleted file mode 100644 index 75f48454b1c..00000000000 --- a/soc/arm/st_stm32/stm32wba/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32WBA MCU line - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "STM32WBAx MCU Selection" -depends on SOC_SERIES_STM32WBAX - -config SOC_STM32WBA52XX - bool "STM32WBA52XX" - -config SOC_STM32WBA55XX - bool "STM32WBA55XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32wl/CMakeLists.txt b/soc/arm/st_stm32/stm32wl/CMakeLists.txt deleted file mode 100644 index af44cc273e1..00000000000 --- a/soc/arm/st_stm32/stm32wl/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources(soc.c) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.series deleted file mode 100644 index be9e5eb2ca6..00000000000 --- a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# STMicroelectronics STM32WL MCU line - -# Copyright (c) 2020 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32WLX - -source "soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl*" - -config SOC_SERIES - default "stm32wl" - -endif # SOC_SERIES_STM32WLX diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.series b/soc/arm/st_stm32/stm32wl/Kconfig.series deleted file mode 100644 index 066deab4e92..00000000000 --- a/soc/arm/st_stm32/stm32wl/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# STMicroelectronics STM32WL MCU series - -# Copyright (c) 2020 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32WLX - bool "STM32WLx Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL - select HAS_PM - select HAS_POWEROFF - help - Enable support for STM32WL MCU series diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.soc b/soc/arm/st_stm32/stm32wl/Kconfig.soc deleted file mode 100644 index 1664c36cb42..00000000000 --- a/soc/arm/st_stm32/stm32wl/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# STMicroelectronics STM32WL MCU line - -# Copyright (c) 2020 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32WLx MCU Selection" - depends on SOC_SERIES_STM32WLX - -config SOC_STM32WLE4XX - bool "STM32WLE4XX" - -config SOC_STM32WLE5XX - bool "STM32WLE5XX" - -config SOC_STM32WL54XX - bool "STM32WL54XX" - -config SOC_STM32WL55XX - bool "STM32WL55XX" - -endchoice diff --git a/soc/arm/ti_k3/CMakeLists.txt b/soc/arm/ti_k3/CMakeLists.txt deleted file mode 100644 index 4f789e9b56e..00000000000 --- a/soc/arm/ti_k3/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/ti_k3/Kconfig b/soc/arm/ti_k3/Kconfig deleted file mode 100644 index 89a5b8813a5..00000000000 --- a/soc/arm/ti_k3/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_TI_K3 - bool - -if SOC_FAMILY_TI_K3 - -config SOC_FAMILY - string - default "ti_k3" - -source "soc/arm/ti_k3/*/Kconfig.soc" - -endif # SOC_FAMILY_TI_K3 diff --git a/soc/arm/ti_k3/Kconfig.defconfig b/soc/arm/ti_k3/Kconfig.defconfig deleted file mode 100644 index 0b983592ad4..00000000000 --- a/soc/arm/ti_k3/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/ti_k3/*/Kconfig.defconfig.series" diff --git a/soc/arm/ti_k3/Kconfig.soc b/soc/arm/ti_k3/Kconfig.soc deleted file mode 100644 index 89379428827..00000000000 --- a/soc/arm/ti_k3/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/ti_k3/*/Kconfig.series" diff --git a/soc/arm/ti_k3/am62x_m4/CMakeLists.txt b/soc/arm/ti_k3/am62x_m4/CMakeLists.txt deleted file mode 100644 index bc9b13ea188..00000000000 --- a/soc/arm/ti_k3/am62x_m4/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) - -if(CONFIG_OPENAMP_RSC_TABLE) - zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) - zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.am62xm4 b/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.am62xm4 deleted file mode 100644 index 688efcd841f..00000000000 --- a/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.am62xm4 +++ /dev/null @@ -1,13 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_AM62x_M4 - -config SOC - default "am62x_m4" - -endif diff --git a/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.series b/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.series deleted file mode 100644 index d85c54d9c00..00000000000 --- a/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.series +++ /dev/null @@ -1,52 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_AM62X_M4 - -source "soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.am62xm4*" - -config SOC_SERIES - default "am62x_m4" - -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - default 64 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 400000000 - -config PINCTRL - default y - -if SERIAL - -config UART_NS16550 - default y - -config UART_NS16550_TI_K3 - default y - -choice UART_NS16550_VARIANT - default UART_NS16550_VARIANT_NS16750 -endchoice - -endif # SERIAL - -config BUILD_OUTPUT_BIN - default n - -source "soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.am62*" - -endif # SOC_SERIES_AM62X_M4 diff --git a/soc/arm/ti_k3/am62x_m4/Kconfig.series b/soc/arm/ti_k3/am62x_m4/Kconfig.series deleted file mode 100644 index 0e675950067..00000000000 --- a/soc/arm/ti_k3/am62x_m4/Kconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_AM62X_M4 - bool "TI AM62X M4 Core Series" - select SOC_FAMILY_TI_K3 - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_SYSTICK - select DYNAMIC_INTERRUPTS - select CPU_CORTEX_M_HAS_DWT - select OPENAMP_RSC_TABLE - select UART_NS16550_ACCESS_WORD_ONLY - select EXTERNAL_ADDRESS_TRANSLATION - select MM_DRV - select MM_TI_RAT - help - Enable support for AM62X M4 Series. diff --git a/soc/arm/ti_k3/am62x_m4/Kconfig.soc b/soc/arm/ti_k3/am62x_m4/Kconfig.soc deleted file mode 100644 index b0eec320f17..00000000000 --- a/soc/arm/ti_k3/am62x_m4/Kconfig.soc +++ /dev/null @@ -1,28 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "TI AM62X M4 Selection" -depends on SOC_SERIES_AM62X_M4 - -config SOC_AM62x_M4 - bool "TI AM62x M4" - select SOC_PART_NUMBER_AM62x - -endchoice - -config SOC_PART_NUMBER_AM62x - bool - -config SOC_PART_NUMBER_AM62X_M4 - string - default "AM62x" if SOC_PART_NUMBER_AM62x - help - Full part number of the SoC. Do not select directly. - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_AM62X_M4 if SOC_SERIES_AM62X_M4 diff --git a/soc/arm/ti_k3/pinctrl_soc.h b/soc/arm/ti_k3/pinctrl_soc.h deleted file mode 100644 index d85797bc2b2..00000000000 --- a/soc/arm/ti_k3/pinctrl_soc.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2023 Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_SOC_ARM_TI_K3_PINCTRL_SOC_H_ -#define ZEPHYR_SOC_ARM_TI_K3_PINCTRL_SOC_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct pinctrl_soc_pin { - uint32_t offset; - uint32_t value; -}; - -typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; - -#define TI_K3_DT_PIN(node_id) \ - { \ - .offset = DT_PROP_BY_IDX(node_id, pinmux, 0), \ - .value = DT_PROP_BY_IDX(node_id, pinmux, 1) \ - }, - -#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ - TI_K3_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)) - -#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ - { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_SOC_ARM_TI_K3_PINCTRL_SOC_H_ */ diff --git a/soc/arm/ti_lm3s6965/CMakeLists.txt b/soc/arm/ti_lm3s6965/CMakeLists.txt deleted file mode 100644 index c76906ff5c3..00000000000 --- a/soc/arm/ti_lm3s6965/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_sources( - soc_config.c - reboot.S - sys_arch_reboot.c - ) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/arm/include - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_lm3s6965/Kconfig b/soc/arm/ti_lm3s6965/Kconfig deleted file mode 100644 index dd181a943cb..00000000000 --- a/soc/arm/ti_lm3s6965/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# TI LM3S6965 platform configuration options - -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_TI_LM3S6965_QEMU - def_bool y - depends on SOC_TI_LM3S6965 - # Platform has only been tested on QEMU, not on real hardware, so always - # assume it is used for a QEMU target. diff --git a/soc/arm/ti_lm3s6965/Kconfig.defconfig b/soc/arm/ti_lm3s6965/Kconfig.defconfig deleted file mode 100644 index 6c8a17a15f4..00000000000 --- a/soc/arm/ti_lm3s6965/Kconfig.defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# TI LM3S6965 platform configuration options - -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_TI_LM3S6965 - -config SOC - default "ti_lm3s6965" - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts and ethernet interrupts - default 43 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 12000000 - -if UART_STELLARIS - -config UART_STELLARIS_PORT_0 - default y - -config UART_STELLARIS_PORT_1 - default y - -config UART_STELLARIS_PORT_2 - default y - -endif # UART_STELLARIS - -endif diff --git a/soc/arm/ti_lm3s6965/Kconfig.soc b/soc/arm/ti_lm3s6965/Kconfig.soc deleted file mode 100644 index e37f9868dac..00000000000 --- a/soc/arm/ti_lm3s6965/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_TI_LM3S6965 - bool "TI LM3S6965" - select ARM - select CPU_CORTEX_M3 - select CPU_CORTEX_M_HAS_DWT diff --git a/soc/arm/ti_simplelink/CMakeLists.txt b/soc/arm/ti_simplelink/CMakeLists.txt deleted file mode 100644 index 226f3bd626f..00000000000 --- a/soc/arm/ti_simplelink/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/ti_simplelink/Kconfig b/soc/arm/ti_simplelink/Kconfig deleted file mode 100644 index e35796ee121..00000000000 --- a/soc/arm/ti_simplelink/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Texas Instruments SimpleLink Family - -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_TISIMPLELINK - bool - -if SOC_FAMILY_TISIMPLELINK - -config SOC_FAMILY - string - default "ti_simplelink" - -source "soc/arm/ti_simplelink/*/Kconfig.soc" - -config HAS_TI_CCFG - bool - help - Selected when CCFG (Customer Configuration) registers - appear at the end of flash - -endif # SOC_FAMILY_TISIMPLELINK diff --git a/soc/arm/ti_simplelink/Kconfig.defconfig b/soc/arm/ti_simplelink/Kconfig.defconfig deleted file mode 100644 index 6e5e652b5a8..00000000000 --- a/soc/arm/ti_simplelink/Kconfig.defconfig +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/ti_simplelink/*/Kconfig.defconfig.series" diff --git a/soc/arm/ti_simplelink/Kconfig.soc b/soc/arm/ti_simplelink/Kconfig.soc deleted file mode 100644 index 780aad1009e..00000000000 --- a/soc/arm/ti_simplelink/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Texas Instruments SimpleLink Family - -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/ti_simplelink/*/Kconfig.series" diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/CMakeLists.txt b/soc/arm/ti_simplelink/cc13x2_cc26x2/CMakeLists.txt deleted file mode 100644 index bf52a055e3b..00000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2019 Brett Witherspoon -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) -zephyr_sources(ccfg.c) - -if(CONFIG_PM OR CONFIG_PM_DEVICE OR CONFIG_POWEROFF) - zephyr_library_sources(power.c) -endif() -zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -zephyr_linker_sources_ifdef(CONFIG_HAS_TI_CCFG SECTIONS ccfg.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc1352r b/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc1352r deleted file mode 100644 index 10ab6b10f75..00000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc1352r +++ /dev/null @@ -1,9 +0,0 @@ -# Texas Instruments SimpleLink CC1352R -# -# Copyright (c) 2019 Brett Witherspoon -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "cc1352r" - depends on SOC_CC1352R diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc2652r b/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc2652r deleted file mode 100644 index 9d7eff99698..00000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc2652r +++ /dev/null @@ -1,8 +0,0 @@ -# Texas Instruments SimpleLink CC2652R - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "cc2652r" - depends on SOC_CC2652R diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.series b/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.series deleted file mode 100644 index 9fc6aeafc9b..00000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.series +++ /dev/null @@ -1,47 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_CC13X2_CC26X2 - -source "soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc*" - -config SOC_SERIES - default "cc13x2_cc26x2" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -# Note that when using the RTC as system clock, this needs to be 32768 -# to reduce truncation errors from accumulating due to conversion to/from -# time, ticks, and HW cycles -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -config NUM_IRQS - default 38 - -if IEEE802154 - -config IEEE802154_CC13XX_CC26XX - # required for linking with PowerCC26X2_config in - # soc/arm/ti_simplelink/cc13x2_cc26x2/power.c - select PM - -config IEEE802154_CC13XX_CC26XX_SUB_GHZ - # required for linking with PowerCC26X2_config in - # soc/arm/ti_simplelink/cc13x2_cc26x2/power.c - select PM - -endif # IEEE802154 - -if BT - -config BLE_CC13XX_CC26XX - bool - default y - -endif # BT - -endif # SOC_SERIES_CC13X2_CC26X2 diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.series b/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.series deleted file mode 100644 index b7d26a70539..00000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_CC13X2_CC26X2 - bool "TI SimpleLink Family CC13x2 / CC26x2" - select ARM - select CPU_CORTEX_M4 - select CPU_HAS_ARM_MPU - select DYNAMIC_INTERRUPTS - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_TISIMPLELINK - select HAS_CC13X2_CC26X2_SDK - select HAS_TI_CCFG if !BOOTLOADER_MCUBOOT - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_PM - select HAS_POWEROFF - help - Enable support for TI SimpleLink CC13x2 / CC26x2 SoCs diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.soc b/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.soc deleted file mode 100644 index 920fb7e5e90..00000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.soc +++ /dev/null @@ -1,68 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "TI SimpleLink MCU Selection" - depends on SOC_SERIES_CC13X2_CC26X2 - -config SOC_CC2652R - bool "CC2652R" - -config SOC_CC2652P - bool "CC2652P" - -config SOC_CC1352R - bool "CC1352R" - -config SOC_CC1352P - bool "CC1352P" - -endchoice - -menu "Customer Configuration (CCFG)" -depends on SOC_SERIES_CC13X2_CC26X2 - -config CC13X2_CC26X2_BOOST_MODE - bool "Radio boost mode (VDDR_HH)" - help - Enable the radio boost mode +14dBm (sets CCFG_FORCE_VDDR_HH to 1). - -config CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS - bool "Board defines custom RFCC26XX hwAttrs structure" - help - The board defines its own RFCC26XX_hwAttrs structure (e.g., for - custom antenna switching callback). - -config CC13X2_CC26X2_BOOTLOADER_ENABLE - bool "ROM bootloader" - help - Enable the serial bootloader which resides in ROM on CC13xx / CC26xx - devices. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - bool "ROM bootloader backdoor" - depends on CC13X2_CC26X2_BOOTLOADER_ENABLE - help - Enable the ROM bootloader backdoor which starts the bootloader if the - associated pin is at the correct logic level on reset. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN - int "ROM bootloader backdoor pin" - depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - range 0 255 - default 255 - help - Set the pin that is level checked if the bootloader backdoor is - enabled. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_LEVEL - int "ROM bootloader backdoor level" - depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - range 0 1 - default 0 - help - Set the active level of the pin selected for the bootloader backdoor. - -endmenu diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt deleted file mode 100644 index 4194f426221..00000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2022 Vaishnav Achath -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) -zephyr_sources(ccfg.c) - -zephyr_library_sources_ifdef(CONFIG_PM power.c) -zephyr_library_sources_ifdef(CONFIG_PM_DEVICE power.c) - -zephyr_linker_sources_ifdef(CONFIG_HAS_TI_CCFG SECTIONS ccfg.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc1352r7 b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc1352r7 deleted file mode 100644 index fabdeedf2d6..00000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc1352r7 +++ /dev/null @@ -1,9 +0,0 @@ -# Texas Instruments SimpleLink CC1352R -# -# Copyright (c) 2022 Vaishnav Achath -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "cc1352r7" - depends on SOC_CC1352R7 diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc2652r7 b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc2652r7 deleted file mode 100644 index 2ba4afb8767..00000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc2652r7 +++ /dev/null @@ -1,8 +0,0 @@ -# Texas Instruments SimpleLink CC2652R - -# Copyright (c) 2022 Vaishnav Achath -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "cc2652r7" - depends on SOC_CC2652R7 diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.series b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.series deleted file mode 100644 index ede32e92701..00000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.series +++ /dev/null @@ -1,47 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2022 Vaishnav Achath -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_CC13X2X7_CC26X2X7 - -source "soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc*" - -config SOC_SERIES - default "cc13x2x7_cc26x2x7" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -# Note that when using the RTC as system clock, this needs to be 32768 -# to reduce truncation errors from accumulating due to conversion to/from -# time, ticks, and HW cycles -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -config NUM_IRQS - default 38 - -if IEEE802154 - -config IEEE802154_CC13XX_CC26XX - # required for linking with PowerCC26X2_config in - # soc/arm/ti_simplelink/cc13x2_cc26x2/power.c - select PM - -config IEEE802154_CC13XX_CC26XX_SUB_GHZ - # required for linking with PowerCC26X2_config in - # soc/arm/ti_simplelink/cc13x2_cc26x2/power.c - select PM - -endif # IEEE802154 - -if BT - -config BLE_CC13XX_CC26XX - bool - default y - -endif # BT - -endif # SOC_SERIES_CC13X2X7_CC26X2X7 diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.series b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.series deleted file mode 100644 index 773b3b85253..00000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2022 Vaishnav Achath -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_CC13X2X7_CC26X2X7 - bool "TI SimpleLink Family CC13x2x7/ CC26x2x7" - select ARM - select CPU_CORTEX_M4 - select CPU_HAS_ARM_MPU - select DYNAMIC_INTERRUPTS - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_TISIMPLELINK - select HAS_CC13X2X7_CC26X2X7_SDK - select HAS_TI_CCFG if !BOOTLOADER_MCUBOOT - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_PM - help - Enable support for TI SimpleLink CC13x2x7 / CC26x2x7 SoCs diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.soc b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.soc deleted file mode 100644 index 96bd6cfce94..00000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.soc +++ /dev/null @@ -1,75 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2022 Vaishnav Achath -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "TI SimpleLink MCU Selection" - depends on SOC_SERIES_CC13X2X7_CC26X2X7 - -config SOC_CC2652R7 - bool "CC2652R7" - -config SOC_CC1352R7 - bool "CC1352R7" - -config SOC_CC2652P7 - bool "CC2652P7" - -config SOC_CC1352P7 - bool "CC1352P7" - -endchoice - -menu "Customer Configuration (CCFG)" -depends on SOC_SERIES_CC13X2X7_CC26X2X7 - -config CC13X2_CC26X2_BOOST_MODE - bool "Radio boost mode (VDDR_HH)" - help - Enable the radio boost mode +14dBm (sets CCFG_FORCE_VDDR_HH to 1). - -config CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS - bool "Board defines custom RFCC26XX hwAttrs structure" - help - The board defines its own RFCC26XX_hwAttrs structure (e.g., for - custom antenna switching callback). - -config CC13X2_CC26X2_BOOTLOADER_ENABLE - bool "ROM bootloader" - help - Enable the serial bootloader which resides in ROM on CC13xx / CC26xx - devices. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - bool "ROM bootloader backdoor" - depends on CC13X2_CC26X2_BOOTLOADER_ENABLE - help - Enable the ROM bootloader backdoor which starts the bootloader if the - associated pin is at the correct logic level on reset. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN - int "ROM bootloader backdoor pin" - depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - range 0 255 - default 255 - help - Set the pin that is level checked if the bootloader backdoor is - enabled. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_LEVEL - int "ROM bootloader backdoor level" - depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - range 0 1 - default 0 - help - Set the active level of the pin selected for the bootloader backdoor. - -config CC13X2_CC26X2_XOSC_CAPARRAY_DELTA - hex "Cap array tuning delta" - range 0 0xFF - default 0xD5 - help - Enable a specific cap array tunning delta. - -endmenu diff --git a/soc/arm/ti_simplelink/cc32xx/CMakeLists.txt b/soc/arm/ti_simplelink/cc32xx/CMakeLists.txt deleted file mode 100644 index 9d704214718..00000000000 --- a/soc/arm/ti_simplelink/cc32xx/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) -zephyr_include_directories(.) - -if (DEFINED CONFIG_CC3220SF_DEBUG OR DEFINED CONFIG_CC3235SF_DEBUG) - zephyr_linker_sources(ROM_START SORT_KEY 0 cc32xx_debug.ld) -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.series b/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.series deleted file mode 100644 index cd586e9fb4c..00000000000 --- a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# TI SimpleLink Family - -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_CC32XX - -source "soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc32*" - -config SOC_SERIES - default "cc32xx" - -endif # SOC_SERIES_CC32XX diff --git a/soc/arm/ti_simplelink/cc32xx/Kconfig.series b/soc/arm/ti_simplelink/cc32xx/Kconfig.series deleted file mode 100644 index 5c7344d26e4..00000000000 --- a/soc/arm/ti_simplelink/cc32xx/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# TI SimpleLink CC32xx - -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_CC32XX - bool "TI SimpleLink Family" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select DYNAMIC_INTERRUPTS - select SOC_FAMILY_TISIMPLELINK - help - Enable support for TI SimpleLink CC32xx diff --git a/soc/arm/ti_simplelink/cc32xx/Kconfig.soc b/soc/arm/ti_simplelink/cc32xx/Kconfig.soc deleted file mode 100644 index 5746cb835b9..00000000000 --- a/soc/arm/ti_simplelink/cc32xx/Kconfig.soc +++ /dev/null @@ -1,27 +0,0 @@ -# Texas Instruments CC32XX - -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "TI SimpleLink MCU Selection" - depends on SOC_SERIES_CC32XX - -config SOC_CC3220SF - bool "CC3220SF" - select HAS_CC3220SDK - -config SOC_CC3235SF - bool "CC3235SF" - select HAS_CC3220SDK - -endchoice - -config CC3220SF_DEBUG - bool "Prepend debug header, disabling flash verification" if XIP - default XIP - depends on SOC_CC3220SF - -config CC3235SF_DEBUG - bool "Prepend debug header, disabling flash verification" if XIP - default XIP - depends on SOC_CC3235SF diff --git a/soc/arm/ti_simplelink/msp432p4xx/CMakeLists.txt b/soc/arm/ti_simplelink/msp432p4xx/CMakeLists.txt deleted file mode 100644 index d93f837e79e..00000000000 --- a/soc/arm/ti_simplelink/msp432p4xx/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_compile_definitions(-D__MSP432P401R__) -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.series b/soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.series deleted file mode 100644 index 55bf2827f12..00000000000 --- a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# TI SimpleLink MSP432P4XX - -# Copyright (c) 2017, Linaro Ltd -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MSP432P4XX - -source "soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.msp432p4*" - -config SOC_SERIES - default "msp432p4xx" - -endif # SOC_SERIES_MSP432P4XX diff --git a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.series b/soc/arm/ti_simplelink/msp432p4xx/Kconfig.series deleted file mode 100644 index 8af48672ed2..00000000000 --- a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# TI SimpleLink MSP432P4XX - -# Copyright (c) 2017, Linaro Ltd -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MSP432P4XX - bool "TI SimpleLink Family MSP432P4XX" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select DYNAMIC_INTERRUPTS - select SOC_FAMILY_TISIMPLELINK - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - help - Enable support for TI SimpleLink MSP432P4XX. diff --git a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.soc b/soc/arm/ti_simplelink/msp432p4xx/Kconfig.soc deleted file mode 100644 index 4b3aa5c2086..00000000000 --- a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# Texas Instruments MSP432P401R - -# Copyright (c) 2017, Linaro Ltd -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "TI SimpleLink MCU Selection" - depends on SOC_SERIES_MSP432P4XX - -config SOC_MSP432P401R - bool "MSP432P401R" - select HAS_MSP432P4XXSDK -endchoice diff --git a/soc/arm/xilinx_zynq7000/Kconfig b/soc/arm/xilinx_zynq7000/Kconfig deleted file mode 100644 index f9cfab4b58d..00000000000 --- a/soc/arm/xilinx_zynq7000/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_FAMILY_XILINX_ZYNQ7000 - bool - -if SOC_FAMILY_XILINX_ZYNQ7000 - -config SOC_FAMILY - string - default "xilinx_zynq7000" - -source "soc/arm/xilinx_zynq7000/*/Kconfig.soc" - -endif # SOC_FAMILY_XILINX_ZYNQ7000 diff --git a/soc/arm/xilinx_zynq7000/Kconfig.defconfig b/soc/arm/xilinx_zynq7000/Kconfig.defconfig deleted file mode 100644 index 6370018edf2..00000000000 --- a/soc/arm/xilinx_zynq7000/Kconfig.defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm/xilinx_zynq7000/*/Kconfig.defconfig.series" - -if SOC_FAMILY_XILINX_ZYNQ7000 - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 96 - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config PLATFORM_SPECIFIC_INIT - default y - -endif # SOC_FAMILY_XILINX_ZYNQ7000 diff --git a/soc/arm/xilinx_zynq7000/Kconfig.soc b/soc/arm/xilinx_zynq7000/Kconfig.soc deleted file mode 100644 index 94bee4dc052..00000000000 --- a/soc/arm/xilinx_zynq7000/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm/xilinx_zynq7000/*/Kconfig.series" diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/CMakeLists.txt b/soc/arm/xilinx_zynq7000/xc7zxxx/CMakeLists.txt deleted file mode 100644 index d47bcfb128f..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.series b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.series deleted file mode 100644 index 2df9c08aef7..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_XILINX_XC7ZXXX - -rsource "Kconfig.defconfig.xc7z*" - -config SOC_SERIES - default "xc7zxxx" - -# Zephyr does not support SMP on aarch32 yet, so we default to 1 CPU core -config MP_MAX_NUM_CPUS - default 1 - -endif # SOC_SERIES_XILINX_XC7ZXXX diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z010 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z010 deleted file mode 100644 index 22c46c7c026..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z010 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z010" - depends on SOC_XILINX_XC7Z010 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z015 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z015 deleted file mode 100644 index 357330de387..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z015 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z015" - depends on SOC_XILINX_XC7Z015 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z020 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z020 deleted file mode 100644 index a0d9cf9d1aa..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z020 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z020" - depends on SOC_XILINX_XC7Z020 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z030 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z030 deleted file mode 100644 index 41be9856cea..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z030 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z030" - depends on SOC_XILINX_XC7Z030 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z035 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z035 deleted file mode 100644 index 078721b96fd..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z035 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z035" - depends on SOC_XILINX_XC7Z035 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z045 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z045 deleted file mode 100644 index 26fb3ed5b5b..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z045 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z045" - depends on SOC_XILINX_XC7Z045 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z100 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z100 deleted file mode 100644 index ef8d7194242..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z100 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z100" - depends on SOC_XILINX_XC7Z100 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.series b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.series deleted file mode 100644 index 5a2f0966aad..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_XILINX_XC7ZXXX - bool "Xilinx Zynq-7000 (XC7Zxxx) SoC series" - select SOC_FAMILY_XILINX_ZYNQ7000 - select ARM - select CPU_CORTEX_A9 - select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER - help - Enable support for the Xilinx Zynq-7000 (XC7Zxxx) - SoC series (dual core ARM Cortex-A9). diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.soc b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.soc deleted file mode 100644 index 3bb2523fbf6..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.soc +++ /dev/null @@ -1,60 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# -# Device data: comp. -# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable -# - -choice - prompt "XC7Zxxx SoC Selection" - depends on SOC_SERIES_XILINX_XC7ZXXX - -config SOC_XILINX_XC7Z010 - bool "XC7Z010" - help - 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, - 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins. - -config SOC_XILINX_XC7Z015 - bool "XC7Z015" - help - 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, - 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins, - up to 4 transceivers. - -config SOC_XILINX_XC7Z020 - bool "XC7Z020" - help - 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, - 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins. - -config SOC_XILINX_XC7Z030 - bool "XC7Z030" - help - 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, - 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins, - up to 4 transceivers. - -config SOC_XILINX_XC7Z035 - bool "XC7Z035" - help - 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, - 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins, - up to 16 transceivers. - -config SOC_XILINX_XC7Z045 - bool "XC7Z045" - help - 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, - 350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins, - up to 16 transceivers. - -config SOC_XILINX_XC7Z100 - bool "XC7Z100" - help - 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, - 444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins, - up to 16 transceivers. - -endchoice diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/CMakeLists.txt b/soc/arm/xilinx_zynq7000/xc7zxxxs/CMakeLists.txt deleted file mode 100644 index d47bcfb128f..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.series b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.series deleted file mode 100644 index f59211e7a34..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_XILINX_XC7ZXXXS - -rsource "Kconfig.defconfig.xc7z*" - -config SOC_SERIES - default "xc7zxxxs" - -config MP_MAX_NUM_CPUS - default 1 - -endif # SOC_SERIES_XILINX_XC7ZXXXS diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z007s b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z007s deleted file mode 100644 index aec3ecdca63..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z007s +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z007S" - depends on SOC_XILINX_XC7Z007S diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z012s b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z012s deleted file mode 100644 index 597fd1aacd8..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z012s +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z012S" - depends on SOC_XILINX_XC7Z012S diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z014s b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z014s deleted file mode 100644 index f01ddc5b782..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z014s +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z014S" - depends on SOC_XILINX_XC7Z014S diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.series b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.series deleted file mode 100644 index 3045a856016..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_XILINX_XC7ZXXXS - bool "Xilinx Zynq-7000S (XC7ZxxxS) SoC series" - select SOC_FAMILY_XILINX_ZYNQ7000 - select ARM - select CPU_CORTEX_A9 - select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER - help - Enable support for the Xilinx Zynq-7000S (XC7ZxxxS) - SoC series (single core ARM Cortex-A9). diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.soc b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.soc deleted file mode 100644 index d69f790f7dd..00000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.soc +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# -# Device data: comp. -# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable -# - -choice - prompt "XC7ZxxxS SoC Selection" - depends on SOC_SERIES_XILINX_XC7ZXXXS - -config SOC_XILINX_XC7Z007S - bool "XC7Z007S" - help - 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, - 23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins. - -config SOC_XILINX_XC7Z012S - bool "XC7Z012S" - help - 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, - 55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins, - up to 4 transceivers. - -config SOC_XILINX_XC7Z014S - bool "XC7Z014S" - help - 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, - 65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins. - -endchoice diff --git a/soc/arm/xilinx_zynqmp/CMakeLists.txt b/soc/arm/xilinx_zynqmp/CMakeLists.txt deleted file mode 100644 index 65bf778779b..00000000000 --- a/soc/arm/xilinx_zynqmp/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c -) -zephyr_sources_ifdef( - CONFIG_ARM_MPU - arm_mpu_regions.c -) - -if(CONFIG_SOC_XILINX_ZYNQMP_RPU) - set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") -endif() diff --git a/soc/arm/xilinx_zynqmp/Kconfig b/soc/arm/xilinx_zynqmp/Kconfig deleted file mode 100644 index 7c72b2d5046..00000000000 --- a/soc/arm/xilinx_zynqmp/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2019 Stephanos Ioannidis -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XILINX_ZYNQMP - bool diff --git a/soc/arm/xilinx_zynqmp/Kconfig.defconfig b/soc/arm/xilinx_zynqmp/Kconfig.defconfig deleted file mode 100644 index ad294bbeda7..00000000000 --- a/soc/arm/xilinx_zynqmp/Kconfig.defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# Copyright (c) 2019 Stephanos Ioannidis -# SPDX-License-Identifier: Apache-2.0 - -if SOC_XILINX_ZYNQMP - -config SOC - default "xilinx_zynqmp" - -if SOC_XILINX_ZYNQMP_RPU - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts - default 220 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 5000000 - -endif # SOC_XILINX_ZYNQMP_RPU - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -endif # SOC_XILINX_ZYNQMP diff --git a/soc/arm/xilinx_zynqmp/Kconfig.soc b/soc/arm/xilinx_zynqmp/Kconfig.soc deleted file mode 100644 index 6d80f61c68e..00000000000 --- a/soc/arm/xilinx_zynqmp/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# Copyright (c) 2019 Stephanos Ioannidis -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XILINX_ZYNQMP_RPU - bool "Xilinx ZynqMP RPU" - select ARM - select CPU_CORTEX_R5 - select SOC_XILINX_ZYNQMP - select PLATFORM_SPECIFIC_INIT - select CPU_HAS_ARM_MPU - select VFP_DP_D16 diff --git a/soc/arm64/CMakeLists.txt b/soc/arm64/CMakeLists.txt deleted file mode 100644 index b826da926ca..00000000000 --- a/soc/arm64/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) -else() - add_subdirectory(${SOC_NAME}) -endif() diff --git a/soc/arm64/Kconfig b/soc/arm64/Kconfig deleted file mode 100644 index a24f8b35034..00000000000 --- a/soc/arm64/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -# General options signifying CPU capabilities of ARM64 SoCs - -# Copyright (c) 2018 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER - string - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. diff --git a/soc/arm64/arm/CMakeLists.txt b/soc/arm64/arm/CMakeLists.txt deleted file mode 100644 index 23fca810f55..00000000000 --- a/soc/arm64/arm/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/arm/Kconfig b/soc/arm64/arm/Kconfig deleted file mode 100644 index cbdb14c1ae2..00000000000 --- a/soc/arm64/arm/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ARM64 - bool - -if SOC_FAMILY_ARM64 -config SOC_FAMILY - string - default "arm" - -source "soc/arm64/arm/*/Kconfig.soc" -endif # SOC_FAMILY_ARM diff --git a/soc/arm64/arm/Kconfig.defconfig b/soc/arm64/arm/Kconfig.defconfig deleted file mode 100644 index f68deebf103..00000000000 --- a/soc/arm64/arm/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/arm/*/Kconfig.defconfig.series" diff --git a/soc/arm64/arm/Kconfig.soc b/soc/arm64/arm/Kconfig.soc deleted file mode 100644 index 24e67555b41..00000000000 --- a/soc/arm64/arm/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/arm/*/Kconfig.series" diff --git a/soc/arm64/arm/fvp_aemv8a/CMakeLists.txt b/soc/arm64/arm/fvp_aemv8a/CMakeLists.txt deleted file mode 100644 index b28d8b24523..00000000000 --- a/soc/arm64/arm/fvp_aemv8a/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/arm/fvp_aemv8a/Kconfig.defconfig.series b/soc/arm64/arm/fvp_aemv8a/Kconfig.defconfig.series deleted file mode 100644 index 00eb592da2a..00000000000 --- a/soc/arm64/arm/fvp_aemv8a/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2021 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_FVP_AEMV8A - -config SOC_SERIES - default "fvp_aemv8a" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config NUM_IRQS - default 16384 if GIC_V3_ITS - default 128 if !GIC_V3_ITS - -if SOC_FVP_BASE_REVC_2XAEMV8A - -config SOC - default "fvp_base_revc_2xaemv8a" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -endif # SOC_FVP_BASE_REVC_2XAEMV8A - -endif # SOC_SERIES_FVP_AEMV8A diff --git a/soc/arm64/arm/fvp_aemv8a/Kconfig.series b/soc/arm64/arm/fvp_aemv8a/Kconfig.series deleted file mode 100644 index 27517028bbe..00000000000 --- a/soc/arm64/arm/fvp_aemv8a/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_FVP_AEMV8A - bool "ARM FVP AEMv8A AArch64 Series" - select ARM64 - select SOC_FAMILY_ARM64 - help - Enable support for ARM FVP AEMv8A AArch64 Series diff --git a/soc/arm64/arm/fvp_aemv8a/Kconfig.soc b/soc/arm64/arm/fvp_aemv8a/Kconfig.soc deleted file mode 100644 index 9dec5155581..00000000000 --- a/soc/arm64/arm/fvp_aemv8a/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM FVP AEMv8A AArch64 SoCs" - depends on SOC_SERIES_FVP_AEMV8A - -config SOC_FVP_BASE_REVC_2XAEMV8A - bool "ARM FVP Base RevC 2xAEMv8A AArch64 simulation" - select CPU_CORTEX_A53 - -endchoice diff --git a/soc/arm64/arm/fvp_aemv8r/CMakeLists.txt b/soc/arm64/arm/fvp_aemv8r/CMakeLists.txt deleted file mode 100644 index ce116cb936e..00000000000 --- a/soc/arm64/arm/fvp_aemv8r/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 -zephyr_library_sources( - soc.c -) - -zephyr_library_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/arm/fvp_aemv8r/Kconfig.defconfig.series b/soc/arm64/arm/fvp_aemv8r/Kconfig.defconfig.series deleted file mode 100644 index ecc3aef5fdd..00000000000 --- a/soc/arm64/arm/fvp_aemv8r/Kconfig.defconfig.series +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_FVP_AEMV8R - -config SOC_SERIES - default "fvp_aemv8r" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config NUM_IRQS - default 128 - -if SOC_FVP_AEMV8R_AARCH64 - -config SOC - default "fvp_aemv8r_aarch64" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config MAX_DOMAIN_PARTITIONS - default 8 - -endif # SOC_FVP_AEMV8R_AARCH64 - -endif # SOC_SERIES_FVP_AEMV8R diff --git a/soc/arm64/arm/fvp_aemv8r/Kconfig.series b/soc/arm64/arm/fvp_aemv8r/Kconfig.series deleted file mode 100644 index cf2f75a18b2..00000000000 --- a/soc/arm64/arm/fvp_aemv8r/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_FVP_AEMV8R - bool "ARM FVP AEMv8R AArch64 Series" - select ARM64 - select SOC_FAMILY_ARM64 - help - Enable support for ARM FVP AEMv8R AArch64 Series diff --git a/soc/arm64/arm/fvp_aemv8r/Kconfig.soc b/soc/arm64/arm/fvp_aemv8r/Kconfig.soc deleted file mode 100644 index 724c37b1182..00000000000 --- a/soc/arm64/arm/fvp_aemv8r/Kconfig.soc +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM FVP AEMv8R AArch64 SoCs" - depends on SOC_SERIES_FVP_AEMV8R - -config SOC_FVP_AEMV8R_AARCH64 - bool "ARM FVP AEMv8R aarch64 simulation" - select CPU_CORTEX_R82 - select CPU_HAS_MPU - select GIC_SINGLE_SECURITY_STATE - -endchoice - -config SOC_FVP_AEMV8R_SIMULATE_CPU_PM - bool "Simulate CPU Power Management for FVP_BaseR_AEMv8R" - default n - help - It simulates the cpu power management function for - FVP_BaseR_AEMv8R. When zephyr kernel try to bring up secondary - core through pm_cpu_on(), it always succeeds because - it indeed bring up secondary core successfully. diff --git a/soc/arm64/bcm2711/Kconfig.defconfig b/soc/arm64/bcm2711/Kconfig.defconfig deleted file mode 100644 index 0016ca57d03..00000000000 --- a/soc/arm64/bcm2711/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2023 honglin leng -# SPDX-License-Identifier: Apache-2.0 - -if SOC_BCM2711 - -config SOC - default "bcm2711" - -config NUM_IRQS - int - default 260 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 54000000 - -endif diff --git a/soc/arm64/bcm2711/Kconfig.soc b/soc/arm64/bcm2711/Kconfig.soc deleted file mode 100644 index 4e1b69462ea..00000000000 --- a/soc/arm64/bcm2711/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2023 honglin leng -# SPDX-License-Identifier: Apache-2.0 - -config SOC_BCM2711 - bool "bcm2711" - select ARM64 - select CPU_CORTEX_A72 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS diff --git a/soc/arm64/bcm_vk/CMakeLists.txt b/soc/arm64/bcm_vk/CMakeLists.txt deleted file mode 100644 index 226f3bd626f..00000000000 --- a/soc/arm64/bcm_vk/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/bcm_vk/Kconfig b/soc/arm64/bcm_vk/Kconfig deleted file mode 100644 index 04312d5b77d..00000000000 --- a/soc/arm64/bcm_vk/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -config SOC_FAMILY_BCMVK - bool - -if SOC_FAMILY_BCMVK -config SOC_FAMILY - string - default "bcm_vk" - -source "soc/arm64/bcm_vk/*/Kconfig.soc" - -endif diff --git a/soc/arm64/bcm_vk/Kconfig.defconfig b/soc/arm64/bcm_vk/Kconfig.defconfig deleted file mode 100644 index b498c95832b..00000000000 --- a/soc/arm64/bcm_vk/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -source "soc/arm64/bcm_vk/*/Kconfig.defconfig.series" diff --git a/soc/arm64/bcm_vk/Kconfig.soc b/soc/arm64/bcm_vk/Kconfig.soc deleted file mode 100644 index 38103238ca7..00000000000 --- a/soc/arm64/bcm_vk/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -source "soc/arm64/bcm_vk/*/Kconfig.series" diff --git a/soc/arm64/bcm_vk/viper/CMakeLists.txt b/soc/arm64/bcm_vk/viper/CMakeLists.txt deleted file mode 100644 index 93f8b45bc82..00000000000 --- a/soc/arm64/bcm_vk/viper/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_sources( - soc.c -) -zephyr_sources_ifdef(CONFIG_SOC_BCM58402_A72 plat_core.c) - -zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/bcm_vk/viper/Kconfig.defconfig.series b/soc/arm64/bcm_vk/viper/Kconfig.defconfig.series deleted file mode 100644 index 831c516416e..00000000000 --- a/soc/arm64/bcm_vk/viper/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_VIPER - -config SOC_SERIES - default "viper" - -source "soc/arm64/bcm_vk/viper/Kconfig.defconfig.viper*" - -endif # SOC_SERIES_VIPER diff --git a/soc/arm64/bcm_vk/viper/Kconfig.series b/soc/arm64/bcm_vk/viper/Kconfig.series deleted file mode 100644 index a972a7e0d2b..00000000000 --- a/soc/arm64/bcm_vk/viper/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_VIPER - bool "Broadcom Viper Series" - select ARM64 - select SOC_FAMILY_BCMVK - help - Enable support for Broadcom Viper Series. diff --git a/soc/arm64/bcm_vk/viper/Kconfig.soc b/soc/arm64/bcm_vk/viper/Kconfig.soc deleted file mode 100644 index 96a9f6cf26a..00000000000 --- a/soc/arm64/bcm_vk/viper/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Broadcom Viper SoC" -depends on SOC_SERIES_VIPER - -config SOC_BCM58402_A72 - bool "Broadcom BCM58402 A72" - select ARM64 - select CPU_CORTEX_A72 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - -endchoice diff --git a/soc/arm64/intel_socfpga/Kconfig b/soc/arm64/intel_socfpga/Kconfig deleted file mode 100644 index 289c186cba3..00000000000 --- a/soc/arm64/intel_socfpga/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_INTEL_SOCFPGA - bool - -if SOC_FAMILY_INTEL_SOCFPGA -config SOC_FAMILY - string - default "intel_socfpga" - -source "soc/arm64/intel_socfpga/*/Kconfig.soc" -endif diff --git a/soc/arm64/intel_socfpga/Kconfig.defconfig b/soc/arm64/intel_socfpga/Kconfig.defconfig deleted file mode 100644 index 58652897d93..00000000000 --- a/soc/arm64/intel_socfpga/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/intel_socfpga/*/Kconfig.defconfig.series" diff --git a/soc/arm64/intel_socfpga/Kconfig.soc b/soc/arm64/intel_socfpga/Kconfig.soc deleted file mode 100644 index 20fdd2fd438..00000000000 --- a/soc/arm64/intel_socfpga/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/intel_socfpga/*/Kconfig.series" diff --git a/soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.series b/soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.series deleted file mode 100644 index 6a457bb2255..00000000000 --- a/soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_AGILEX - -config SOC_SERIES - default "agilex" - -source "soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex*" - -endif # SOC_SERIES_AGILEX diff --git a/soc/arm64/intel_socfpga/agilex/Kconfig.series b/soc/arm64/intel_socfpga/agilex/Kconfig.series deleted file mode 100644 index f1266db5bae..00000000000 --- a/soc/arm64/intel_socfpga/agilex/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_AGILEX - bool "Intel SoC FPGA Agilex Series" - select ARM64 - select CPU_CORTEX_A53 - select SOC_FAMILY_INTEL_SOCFPGA - help - Enable support for Intel SoC FPGA Series diff --git a/soc/arm64/intel_socfpga/agilex/Kconfig.soc b/soc/arm64/intel_socfpga/agilex/Kconfig.soc deleted file mode 100644 index e87636f1af3..00000000000 --- a/soc/arm64/intel_socfpga/agilex/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Intel SoC FPGA Agilex" -depends on SOC_SERIES_AGILEX - -config SOC_AGILEX - bool "Intel SoC FPGA Agilex" -endchoice diff --git a/soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.series b/soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.series deleted file mode 100644 index 6a511cdfd6e..00000000000 --- a/soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_AGILEX5 - -config SOC_SERIES - default "agilex5" - -source "soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5*" - -endif # SOC_SERIES_AGILEX5 diff --git a/soc/arm64/intel_socfpga/agilex5/Kconfig.series b/soc/arm64/intel_socfpga/agilex5/Kconfig.series deleted file mode 100644 index c64c38dc557..00000000000 --- a/soc/arm64/intel_socfpga/agilex5/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_AGILEX5 - bool "Intel SoC FPGA Agilex5 Series" - select ARM64 - select CPU_CORTEX_A76_A55 - select SOC_FAMILY_INTEL_SOCFPGA - help - Enable support for Intel SoC FPGA Series diff --git a/soc/arm64/intel_socfpga/agilex5/Kconfig.soc b/soc/arm64/intel_socfpga/agilex5/Kconfig.soc deleted file mode 100644 index bb75833db9e..00000000000 --- a/soc/arm64/intel_socfpga/agilex5/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Intel SoC FPGA Agilex5" -depends on SOC_SERIES_AGILEX5 - -config SOC_AGILEX5 - bool "Intel SoC FPGA Agilex5" -endchoice diff --git a/soc/arm64/nxp_imx/CMakeLists.txt b/soc/arm64/nxp_imx/CMakeLists.txt deleted file mode 100644 index fed279096cc..00000000000 --- a/soc/arm64/nxp_imx/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/nxp_imx/Kconfig b/soc/arm64/nxp_imx/Kconfig deleted file mode 100644 index c1fbf2dfc1e..00000000000 --- a/soc/arm64/nxp_imx/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2017-2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_IMX - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_IMX - -config SOC_FAMILY - string - default "nxp_imx" - -source "soc/arm64/nxp_imx/*/Kconfig.soc" - -endif # SOC_FAMILY_IMX diff --git a/soc/arm64/nxp_imx/Kconfig.defconfig b/soc/arm64/nxp_imx/Kconfig.defconfig deleted file mode 100644 index e4ec0b9e0fe..00000000000 --- a/soc/arm64/nxp_imx/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/nxp_imx/*/Kconfig.defconfig.series" diff --git a/soc/arm64/nxp_imx/Kconfig.soc b/soc/arm64/nxp_imx/Kconfig.soc deleted file mode 100644 index bd111bf4c9d..00000000000 --- a/soc/arm64/nxp_imx/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/nxp_imx/*/Kconfig.series" diff --git a/soc/arm64/nxp_imx/mimx8m/CMakeLists.txt b/soc/arm64/nxp_imx/mimx8m/CMakeLists.txt deleted file mode 100644 index 032c4a8642d..00000000000 --- a/soc/arm64/nxp_imx/mimx8m/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) - -zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mm b/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mm deleted file mode 100644 index a77d9f837df..00000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mm +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2020-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8MM_A53 - -config SOC - default "mimx8mm6_ca53" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - int - default 240 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 8000000 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -endif diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mn b/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mn deleted file mode 100644 index c6c2837d74d..00000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mn +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8MN_A53 - -config SOC - default "mimx8mn6_ca53" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - int - default 240 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 8000000 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -endif diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mp b/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mp deleted file mode 100644 index ebdfa764a69..00000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mp +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2021-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8MP_A53 - -config SOC - default "mimx8ml8_ca53" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - int - default 240 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 8000000 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -endif diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.series b/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.series deleted file mode 100644 index 51aed03b198..00000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2020-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MIMX8M_A53 - -config SOC_SERIES - default "mimx8m" - -source "soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8m*" - -endif # SOC_SERIES_MIMX8M_A53 diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.series b/soc/arm64/nxp_imx/mimx8m/Kconfig.series deleted file mode 100644 index cbb0cb99f52..00000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2020-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MIMX8M_A53 - bool "NXP i.MX8M A53 Core Series" - select ARM64 - select SOC_FAMILY_IMX - help - Enable support for i.MX8M A53 Series. diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.soc b/soc/arm64/nxp_imx/mimx8m/Kconfig.soc deleted file mode 100644 index 8c29bb50c96..00000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.soc +++ /dev/null @@ -1,93 +0,0 @@ -# Copyright 2020-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "NXP i.MX8M A53 Selection" -depends on SOC_SERIES_MIMX8M_A53 - -config SOC_MIMX8MM_A53 - bool "NXP i.MX8MM A53" - select ARM64 - select CPU_CORTEX_A53 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select HAS_MCUX if CLOCK_CONTROL - select HAS_MCUX_CCM if CLOCK_CONTROL - select HAS_MCUX_IOMUXC if PINCTRL - -config SOC_MIMX8MP_A53 - bool "NXP i.MX8MP A53" - select ARM64 - select CPU_CORTEX_A53 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select HAS_MCUX if CLOCK_CONTROL - select HAS_MCUX_CCM if CLOCK_CONTROL - select HAS_MCUX_IOMUXC if PINCTRL - -config SOC_MIMX8MN_A53 - bool "NXP i.MX8MN A53" - select ARM64 - select CPU_CORTEX_A53 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select HAS_MCUX if CLOCK_CONTROL - select HAS_MCUX_CCM if CLOCK_CONTROL - select HAS_MCUX_IOMUXC if PINCTRL - -endchoice - -config SOC_PART_NUMBER_MIMX8ML8DVNLZ - bool - -config SOC_PART_NUMBER_MIMX8MP_A53 - string - default "MIMX8ML8DVNLZ_ca53" if SOC_PART_NUMBER_MIMX8ML8DVNLZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_PART_NUMBER_MIMX8MM6DVTLZ - bool - -config SOC_PART_NUMBER_MIMX8MM6CVTKZ - bool - -config SOC_PART_NUMBER_MIMX8MM_A53 - string - default "MIMX8MM6DVTLZ_ca53" if SOC_PART_NUMBER_MIMX8MM6DVTLZ - default "MIMX8MM6CVTKZ_ca53" if SOC_PART_NUMBER_MIMX8MM6CVTKZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -if SOC_MIMX8MN_A53 - -config SOC_PART_NUMBER_MIMX8MN6DVTJZ - bool - -config SOC_PART_NUMBER_MIMX8MN6DUCJZ - bool - -config SOC_PART_NUMBER_MIMX8MN6CVTIZ - bool - -config SOC_PART_NUMBER_MIMX8MN6CUCIZ - bool - -config SOC_PART_NUMBER_MIMX8MN_A53 - string - default "MIMX8MN6DVTJZ_ca53" if SOC_PART_NUMBER_MIMX8MN6DVTJZ - default "MIMX8MN6DUCJZ_ca53" if SOC_PART_NUMBER_MIMX8MN6DUCJZ - default "MIMX8MN6CVTIZ_ca53" if SOC_PART_NUMBER_MIMX8MN6CVTIZ - default "MIMX8MN6CUCIZ_ca53" if SOC_PART_NUMBER_MIMX8MN6CUCIZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_MIMX8MN_A53 - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_MIMX8MP_A53 if SOC_MIMX8MP_A53 - default SOC_PART_NUMBER_MIMX8MM_A53 if SOC_MIMX8MM_A53 - default SOC_PART_NUMBER_MIMX8MN_A53 if SOC_MIMX8MN_A53 diff --git a/soc/arm64/nxp_imx/mimx9/CMakeLists.txt b/soc/arm64/nxp_imx/mimx9/CMakeLists.txt deleted file mode 100644 index 77a9500f5b7..00000000000 --- a/soc/arm64/nxp_imx/mimx9/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) - -zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.mimx93 b/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.mimx93 deleted file mode 100644 index 45e67de35ed..00000000000 --- a/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.mimx93 +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX93_A55 - -config SOC - default "mimx9352_ca55" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - int - default 240 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 24000000 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -endif diff --git a/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.series b/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.series deleted file mode 100644 index 83a587bddc8..00000000000 --- a/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MIMX9_A55 - -config SOC_SERIES - default "mimx9" - -source "soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.mimx9*" - -endif # SOC_SERIES_MIMX9_A55 diff --git a/soc/arm64/nxp_imx/mimx9/Kconfig.series b/soc/arm64/nxp_imx/mimx9/Kconfig.series deleted file mode 100644 index 2998e0161c3..00000000000 --- a/soc/arm64/nxp_imx/mimx9/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MIMX9_A55 - bool "NXP i.MX9 A55 Core Series" - select ARM64 - select SOC_FAMILY_IMX - help - Enable support for i.MX9 A55 Series. diff --git a/soc/arm64/nxp_imx/mimx9/Kconfig.soc b/soc/arm64/nxp_imx/mimx9/Kconfig.soc deleted file mode 100644 index 3f38d40131f..00000000000 --- a/soc/arm64/nxp_imx/mimx9/Kconfig.soc +++ /dev/null @@ -1,35 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "NXP i.MX9 A55 Selection" -depends on SOC_SERIES_MIMX9_A55 - -config SOC_MIMX93_A55 - bool "NXP i.MX93 A55" - select ARM64 - select CPU_CORTEX_A55 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select HAS_MCUX if CLOCK_CONTROL - select HAS_MCUX_CCM_REV2 if CLOCK_CONTROL - select HAS_MCUX_IOMUXC if PINCTRL - -endchoice - -config SOC_PART_NUMBER_MIMX9352CVUXK - bool - -config SOC_PART_NUMBER_MIMX9352DVUXM - bool - -config SOC_PART_NUMBER_MIMX93_A55 - string - default "MIMX9352CVUXK_ca55" if SOC_PART_NUMBER_MIMX9352CVUXK - default "MIMX9352DVUXM_ca55" if SOC_PART_NUMBER_MIMX9352DVUXM - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_MIMX93_A55 if SOC_MIMX93_A55 diff --git a/soc/arm64/nxp_layerscape/Kconfig b/soc/arm64/nxp_layerscape/Kconfig deleted file mode 100644 index ac299386195..00000000000 --- a/soc/arm64/nxp_layerscape/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_FAMILY_LS - bool - -if SOC_FAMILY_LS - -config SOC_FAMILY - string - default "nxp_layerscape" - -source "soc/arm64/nxp_layerscape/*/Kconfig.soc" - -config SOC_PART_NUMBER - default "LS1046A" if SOC_SERIES_LS1046A - -endif # SOC_FAMILY_LS diff --git a/soc/arm64/nxp_layerscape/Kconfig.defconfig b/soc/arm64/nxp_layerscape/Kconfig.defconfig deleted file mode 100644 index 15f1964dd99..00000000000 --- a/soc/arm64/nxp_layerscape/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm64/nxp_layerscape/*/Kconfig.defconfig.series" diff --git a/soc/arm64/nxp_layerscape/Kconfig.soc b/soc/arm64/nxp_layerscape/Kconfig.soc deleted file mode 100644 index e2ab956ce7f..00000000000 --- a/soc/arm64/nxp_layerscape/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm64/nxp_layerscape/*/Kconfig.series" diff --git a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.ls1046a b/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.ls1046a deleted file mode 100644 index 86e02eb67d5..00000000000 --- a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.ls1046a +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_LS1046A - -config SOC - default "ls1046a" - -config NUM_IRQS - int - default 240 - -config FLASH_SIZE - default 0 - -config FLASH_BASE_ADDRESS - default 0 - -endif diff --git a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.series b/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.series deleted file mode 100644 index 727b4287eea..00000000000 --- a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_LS1046A - -config SOC_SERIES - default "ls1046a" - -source "soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.ls1046a" - -endif # SOC_SERIES_LS1046A diff --git a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.series b/soc/arm64/nxp_layerscape/ls1046a/Kconfig.series deleted file mode 100644 index 259a51f51dd..00000000000 --- a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_LS1046A - bool "NXP LS1046A Series" - select ARM64 - select SOC_FAMILY_LS - help - Enable support for NXP ls1046a Series. diff --git a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.soc b/soc/arm64/nxp_layerscape/ls1046a/Kconfig.soc deleted file mode 100644 index be9ea607c82..00000000000 --- a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.soc +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -choice -prompt "NXP Layerscpae LS1046A SoC" -depends on SOC_SERIES_LS1046A - -config SOC_LS1046A - bool "NXP ls1046a" - select ARM64 - select CPU_CORTEX_A72 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - -endchoice diff --git a/soc/arm64/qemu_cortex_a53/CMakeLists.txt b/soc/arm64/qemu_cortex_a53/CMakeLists.txt deleted file mode 100644 index b28d8b24523..00000000000 --- a/soc/arm64/qemu_cortex_a53/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/qemu_cortex_a53/Kconfig.defconfig b/soc/arm64/qemu_cortex_a53/Kconfig.defconfig deleted file mode 100644 index dca1544f7c5..00000000000 --- a/soc/arm64/qemu_cortex_a53/Kconfig.defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_CORTEX_A53 - -config SOC - default "qemu_cortex_a53" - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts - # - LPIs (starting at 8192) if GIC_V3_ITS is used - default 16384 if GIC_V3_ITS - default 220 if !GIC_V3_ITS - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 62500000 - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -endif # SOC_QEMU_CORTEX_A53 diff --git a/soc/arm64/qemu_cortex_a53/Kconfig.soc b/soc/arm64/qemu_cortex_a53/Kconfig.soc deleted file mode 100644 index 4aac3e811b5..00000000000 --- a/soc/arm64/qemu_cortex_a53/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_CORTEX_A53 - bool "QEMU virt platform (cortex-a53)" - select ARM64 - select CPU_CORTEX_A53 diff --git a/soc/arm64/qemu_virt_arm64/Kconfig.defconfig b/soc/arm64/qemu_virt_arm64/Kconfig.defconfig deleted file mode 100644 index 14c6c333450..00000000000 --- a/soc/arm64/qemu_virt_arm64/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2022 Huawei France Technologies SAS -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_VIRT_ARM64 - -config SOC - default "qemu_virt_arm64" - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts - # - LPIs (starting at 8192) if GIC_V3_ITS is used - default 16384 if GIC_V3_ITS - default 220 if !GIC_V3_ITS - -# Dummy value, read at runtime -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1 - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -endif # SOC_QEMU_VIRT_ARM64 diff --git a/soc/arm64/qemu_virt_arm64/Kconfig.soc b/soc/arm64/qemu_virt_arm64/Kconfig.soc deleted file mode 100644 index 109e8e3270a..00000000000 --- a/soc/arm64/qemu_virt_arm64/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Huawei France Technologies SAS -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_VIRT_ARM64 - bool "QEMU virt platform (AArch64 for KVM)" - select ARM64 - select CPU_CORTEX_A - select ARMV8_A diff --git a/soc/arm64/renesas_rcar/CMakeLists.txt b/soc/arm64/renesas_rcar/CMakeLists.txt deleted file mode 100644 index ce47b609a9a..00000000000 --- a/soc/arm64/renesas_rcar/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/renesas_rcar/Kconfig b/soc/arm64/renesas_rcar/Kconfig deleted file mode 100644 index 413523e23a7..00000000000 --- a/soc/arm64/renesas_rcar/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Renesas R-Car SoC line - -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_RCAR - bool - -if SOC_FAMILY_RCAR - -config SOC_FAMILY - string - default "renesas_rcar" - -source "soc/arm64/renesas_rcar/*/Kconfig.soc" - -endif # SOC_FAMILY_RCAR diff --git a/soc/arm64/renesas_rcar/Kconfig.defconfig b/soc/arm64/renesas_rcar/Kconfig.defconfig deleted file mode 100644 index fa39233d8dc..00000000000 --- a/soc/arm64/renesas_rcar/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/renesas_rcar/*/Kconfig.defconfig.series" diff --git a/soc/arm64/renesas_rcar/Kconfig.soc b/soc/arm64/renesas_rcar/Kconfig.soc deleted file mode 100644 index 3e191b56f35..00000000000 --- a/soc/arm64/renesas_rcar/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Renesas R-Car SoC line - -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/renesas_rcar/*/Kconfig.series" diff --git a/soc/arm64/renesas_rcar/gen3/CMakeLists.txt b/soc/arm64/renesas_rcar/gen3/CMakeLists.txt deleted file mode 100644 index 16dcc07b754..00000000000 --- a/soc/arm64/renesas_rcar/gen3/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_SOC_ARM64_R8A77951 pfc_r8a77951.c) -zephyr_library_sources_ifdef(CONFIG_SOC_R8A77961 pfc_r8a77961.c) -zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 b/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 deleted file mode 100644 index 3df374f2893..00000000000 --- a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARM64_R8A77951 - -config SOC - default "r8a77951" - -endif # SOC_ARM64_R8A77951 diff --git a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77961 b/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77961 deleted file mode 100644 index 573e7b102fb..00000000000 --- a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77961 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if SOC_R8A77961 - -config SOC - default "r8a77961" - -endif # SOC_R8A77961 diff --git a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.series b/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.series deleted file mode 100644 index 369d1beedb8..00000000000 --- a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Renesas R-Car Gen3 SoC line - -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RCAR_GEN3 - -config SOC_SERIES - default "gen3" - -config NUM_IRQS - int - default 240 - -config PINCTRL - default y - -endif # SOC_SERIES_RCAR_GEN3 diff --git a/soc/arm64/renesas_rcar/gen3/Kconfig.series b/soc/arm64/renesas_rcar/gen3/Kconfig.series deleted file mode 100644 index a5c33c2a23c..00000000000 --- a/soc/arm64/renesas_rcar/gen3/Kconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RCAR_GEN3 - bool "Renesas RCAR Gen3 Cortex A" - select ARM64 - select CPU_CORTEX_A57 - select SOC_FAMILY_RCAR - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL - help - Enable support for Renesas RCar Gen3 SoC series diff --git a/soc/arm64/renesas_rcar/gen3/Kconfig.soc b/soc/arm64/renesas_rcar/gen3/Kconfig.soc deleted file mode 100644 index 4be06397bd1..00000000000 --- a/soc/arm64/renesas_rcar/gen3/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Renesas RCar SoC Selection" - depends on SOC_SERIES_RCAR_GEN3 - -config SOC_ARM64_R8A77951 - bool "R8A77951" - -config SOC_R8A77961 - bool "R8A77961" - -endchoice diff --git a/soc/arm64/renesas_rcar/gen3/pfc_r8a77951.c b/soc/arm64/renesas_rcar/gen3/pfc_r8a77951.c deleted file mode 100644 index 2d5c02316ef..00000000000 --- a/soc/arm64/renesas_rcar/gen3/pfc_r8a77951.c +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (c) 2021 IoT.bzh - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#include "pinctrl_soc.h" -#include - -const struct pfc_drive_reg pfc_drive_regs[] = { - /* DRVCTRL0 */ - { 0x0300, { - { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ - { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ - { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ - { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ - { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ - { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ - } }, - /* DRVCTRL1 */ - { 0x0304, { - { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ - { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ - { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ - { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ - { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ - { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ - { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ - } }, - /* DRVCTRL2 */ - { 0x0308, { - { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ - { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ - { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ - { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ - { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ - { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ - { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ - { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ - } }, - /* DRVCTRL3 */ - { 0x030c, { - { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ - { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ - { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ - { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ - } }, - /* DRVCTRL4 */ - { 0x0310, { - { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ - { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ - { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ - { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ - { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ - { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ - { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ - { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ - } }, - /* DRVCTRL5 */ - { 0x0314, { - { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ - { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ - { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ - { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ - { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ - { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ - { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ - { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ - } }, - /* DRVCTRL6 */ - { 0x0318, { - { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ - { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ - { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ - { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ - { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ - { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ - { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ - { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ - } }, - /* DRVCTRL7 */ - { 0x031c, { - { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ - { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ - { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ - { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ - { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ - { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ - { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ - { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ - } }, - /* DRVCTRL8 */ - { 0x0320, { - { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ - { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ - { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ - { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ - { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ - { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ - { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ - { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ - } }, - /* DRVCTRL9 */ - { 0x0324, { - { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ - { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ - { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ - { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ - { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ - { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ - { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ - } }, - /* DRVCTRL10 */ - { 0x0328, { - { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ - { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ - { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ - { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ - { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ - { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ - { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ - { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ - } }, - /* DRVCTRL11 */ - { 0x032c, { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ - } }, - /* DRVCTRL12 */ - { 0x0330, { - { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ - { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ - { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ - { PIN_TMS, 4, 2 }, /* TMS */ - } }, - /* DRVCTRL13 */ - { 0x0334, { - { PIN_TDO, 28, 2 }, /* TDO */ - { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ - } }, - /* DRVCTRL14 */ - { 0x0338, { - { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ - { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ - { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ - { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ - { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ - { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ - { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ - { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ - } }, - /* DRVCTRL15 */ - { 0x033c, { - { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ - { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ - { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ - { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ - { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ - { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ - { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ - { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ - } }, - /* DRVCTRL16 */ - { 0x0340, { - { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ - { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ - { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ - { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ - { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ - { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ - { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ - { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ - } }, - /* DRVCTRL17 */ - { 0x0344, { - { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ - { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ - { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ - { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ - { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ - { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ - { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ - { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ - } }, - /* DRVCTRL18 */ - { 0x0348, { - { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ - { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ - { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ - { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ - { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ - { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ - { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ - { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ - } }, - /* DRVCTRL19 */ - { 0x034c, { - { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ - { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ - { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ - { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ - { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ - { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ - { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ - { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ - } }, - /* DRVCTRL20 */ - { 0x0350, { - { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ - { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ - { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ - { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ - { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ - { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ - { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ - } }, - /* DRVCTRL21 */ - { 0x0354, { - { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ - { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ - { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ - { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ - { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ - { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ - { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ - } }, - /* DRVCTRL22 */ - { 0x0358, { - { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ - { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ - { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ - { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ - { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ - { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ - { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ - { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ - } }, - /* DRVCTRL23 */ - { 0x035c, { - { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ - { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ - { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ - { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ - { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ - { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ - { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ - { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ - } }, - /* DRVCTRL24 */ - { 0x0360, { - { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ - { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ - { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ - { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ - { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */ - { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */ - } }, - { }, -}; - -#define PFC_BIAS_REG(r1, r2) \ - .puen = r1, \ - .pud = r2, \ - .pins = - -const struct pfc_bias_reg pfc_bias_regs[] = { - { PFC_BIAS_REG(0x0400, 0x0440) { /* PUEN0, PUD0 */ - [0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ - [1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ - [2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ - [3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ - [4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ - [5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ - [6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ - [7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ - [8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ - [9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ - [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ - [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ - [12] = PIN_RPC_INT_N, /* RPC_INT# */ - [13] = PIN_RPC_WP_N, /* RPC_WP# */ - [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ - [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ - [16] = PIN_AVB_RXC, /* AVB_RXC */ - [17] = PIN_AVB_RD0, /* AVB_RD0 */ - [18] = PIN_AVB_RD1, /* AVB_RD1 */ - [19] = PIN_AVB_RD2, /* AVB_RD2 */ - [20] = PIN_AVB_RD3, /* AVB_RD3 */ - [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ - [22] = PIN_AVB_TXC, /* AVB_TXC */ - [23] = PIN_AVB_TD0, /* AVB_TD0 */ - [24] = PIN_AVB_TD1, /* AVB_TD1 */ - [25] = PIN_AVB_TD2, /* AVB_TD2 */ - [26] = PIN_AVB_TD3, /* AVB_TD3 */ - [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ - [28] = PIN_AVB_MDIO, /* AVB_MDIO */ - [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ - [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ - [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ - } }, - { PFC_BIAS_REG(0x0404, 0x0444) { /* PUEN1, PUD1 */ - [0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ - [1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ - [2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ - [3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ - [4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ - [5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ - [6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ - [7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ - [8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ - [9] = RCAR_GP_PIN(2, 6), /* PWM0 */ - [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ - [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ - [12] = RCAR_GP_PIN(1, 0), /* A0 */ - [13] = RCAR_GP_PIN(1, 1), /* A1 */ - [14] = RCAR_GP_PIN(1, 2), /* A2 */ - [15] = RCAR_GP_PIN(1, 3), /* A3 */ - [16] = RCAR_GP_PIN(1, 4), /* A4 */ - [17] = RCAR_GP_PIN(1, 5), /* A5 */ - [18] = RCAR_GP_PIN(1, 6), /* A6 */ - [19] = RCAR_GP_PIN(1, 7), /* A7 */ - [20] = RCAR_GP_PIN(1, 8), /* A8 */ - [21] = RCAR_GP_PIN(1, 9), /* A9 */ - [22] = RCAR_GP_PIN(1, 10), /* A10 */ - [23] = RCAR_GP_PIN(1, 11), /* A11 */ - [24] = RCAR_GP_PIN(1, 12), /* A12 */ - [25] = RCAR_GP_PIN(1, 13), /* A13 */ - [26] = RCAR_GP_PIN(1, 14), /* A14 */ - [27] = RCAR_GP_PIN(1, 15), /* A15 */ - [28] = RCAR_GP_PIN(1, 16), /* A16 */ - [29] = RCAR_GP_PIN(1, 17), /* A17 */ - [30] = RCAR_GP_PIN(1, 18), /* A18 */ - [31] = RCAR_GP_PIN(1, 19), /* A19 */ - } }, - { PFC_BIAS_REG(0x0408, 0x0448) { /* PUEN2, PUD2 */ - [0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ - [1] = RCAR_GP_PIN(1, 20), /* CS0_N */ - [2] = RCAR_GP_PIN(1, 21), /* CS1_N */ - [3] = RCAR_GP_PIN(1, 22), /* BS_N */ - [4] = RCAR_GP_PIN(1, 23), /* RD_N */ - [5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ - [6] = RCAR_GP_PIN(1, 25), /* WE0_N */ - [7] = RCAR_GP_PIN(1, 26), /* WE1_N */ - [8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [9] = PIN_PRESETOUT_N, /* PRESETOUT# */ - [10] = RCAR_GP_PIN(0, 0), /* D0 */ - [11] = RCAR_GP_PIN(0, 1), /* D1 */ - [12] = RCAR_GP_PIN(0, 2), /* D2 */ - [13] = RCAR_GP_PIN(0, 3), /* D3 */ - [14] = RCAR_GP_PIN(0, 4), /* D4 */ - [15] = RCAR_GP_PIN(0, 5), /* D5 */ - [16] = RCAR_GP_PIN(0, 6), /* D6 */ - [17] = RCAR_GP_PIN(0, 7), /* D7 */ - [18] = RCAR_GP_PIN(0, 8), /* D8 */ - [19] = RCAR_GP_PIN(0, 9), /* D9 */ - [20] = RCAR_GP_PIN(0, 10), /* D10 */ - [21] = RCAR_GP_PIN(0, 11), /* D11 */ - [22] = RCAR_GP_PIN(0, 12), /* D12 */ - [23] = RCAR_GP_PIN(0, 13), /* D13 */ - [24] = RCAR_GP_PIN(0, 14), /* D14 */ - [25] = RCAR_GP_PIN(0, 15), /* D15 */ - [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ - [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ - [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ - [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ - } }, - { PFC_BIAS_REG(0x040c, 0x044c) { /* PUEN3, PUD3 */ - [0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ - [1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ - [2] = PIN_FSCLKST_N, /* FSCLKST# */ - [3] = PIN_EXTALR, /* EXTALR*/ - [4] = PIN_TRST_N, /* TRST# */ - [5] = PIN_TCK, /* TCK */ - [6] = PIN_TMS, /* TMS */ - [7] = PIN_TDI, /* TDI */ - [8] = PIN_NONE, - [9] = PIN_ASEBRK, /* ASEBRK */ - [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ - [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ - [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ - [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ - [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ - [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ - [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ - [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ - [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ - [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ - [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ - [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ - [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ - [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ - [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ - [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ - [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ - [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ - [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ - [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ - [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ - [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ - } }, - { PFC_BIAS_REG(0x0410, 0x0450) { /* PUEN4, PUD4 */ - [0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ - [1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ - [2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ - [3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ - [4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ - [5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ - [6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ - [7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ - [8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ - [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ - [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ - [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ - [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ - [13] = RCAR_GP_PIN(5, 1), /* RX0 */ - [14] = RCAR_GP_PIN(5, 2), /* TX0 */ - [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ - [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ - [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ - [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ - [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ - [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ - [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ - [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ - [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ - [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ - [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ - [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ - [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ - [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ - [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ - [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ - [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ - } }, - { PFC_BIAS_REG(0x0414, 0x0454) { /* PUEN5, PUD5 */ - [0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ - [1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ - [2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ - [3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ - [4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ - [5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [6] = PIN_MLB_REF, /* MLB_REF */ - [7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ - [8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ - [9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ - [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ - [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ - [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ - [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ - [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ - [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ - [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ - [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ - [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ - [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ - [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ - [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ - [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ - [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ - [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ - [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ - [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ - [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ - [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ - [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ - [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ - [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ - } }, - { PFC_BIAS_REG(0x0418, 0x0458) { /* PUEN6, PUD6 */ - [0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ - [1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ - [2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ - [3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ - [4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ - [5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ - [6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */ - [7] = PIN_NONE, - [8] = PIN_NONE, - [9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, - } }, - { /* sentinel */ }, -}; -const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void) -{ - return pfc_bias_regs; -} -const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void) -{ - return pfc_drive_regs; -} - -int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index) -{ - /* There is only one register on Gen 3 */ - *reg_index = 0; - return 0; -} diff --git a/soc/arm64/rockchip/CMakeLists.txt b/soc/arm64/rockchip/CMakeLists.txt deleted file mode 100644 index a002d302cf6..00000000000 --- a/soc/arm64/rockchip/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/rockchip/Kconfig b/soc/arm64/rockchip/Kconfig deleted file mode 100644 index e0b4b937c79..00000000000 --- a/soc/arm64/rockchip/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright 2021 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_FAMILY_ROCKCHIP - bool - -if SOC_FAMILY_ROCKCHIP - -config SOC_FAMILY - string - default "rockchip" - -source "soc/arm64/rockchip/*/Kconfig.soc" - -config SOC_PART_NUMBER - default "RK3399" if SOC_SERIES_RK3399 - default "RK3568" if SOC_SERIES_RK3568 - -endif # SOC_FAMILY_ROCKCHIP diff --git a/soc/arm64/rockchip/Kconfig.defconfig b/soc/arm64/rockchip/Kconfig.defconfig deleted file mode 100644 index 64ee55264d7..00000000000 --- a/soc/arm64/rockchip/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2021 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm64/rockchip/*/Kconfig.defconfig.series" diff --git a/soc/arm64/rockchip/Kconfig.soc b/soc/arm64/rockchip/Kconfig.soc deleted file mode 100644 index 19bbc3f798f..00000000000 --- a/soc/arm64/rockchip/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm64/rockchip/*/Kconfig.series" diff --git a/soc/arm64/rockchip/rk3399/Kconfig.defconfig.series b/soc/arm64/rockchip/rk3399/Kconfig.defconfig.series deleted file mode 100644 index 0bedfa01d8d..00000000000 --- a/soc/arm64/rockchip/rk3399/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_RK3399 - -config SOC_SERIES - default "rk3399" - -source "soc/arm64/rockchip/rk3399/Kconfig.defconfig.rk3399" - -endif # SOC_SERIES_RK3399 diff --git a/soc/arm64/rockchip/rk3399/Kconfig.series b/soc/arm64/rockchip/rk3399/Kconfig.series deleted file mode 100644 index 71b2e5e4851..00000000000 --- a/soc/arm64/rockchip/rk3399/Kconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_RK3399 - bool "Rockchip RK3399 Series" - select ARM64 - select SOC_FAMILY_ROCKCHIP - help - Enable support for Rockchip RK3399 Series. diff --git a/soc/arm64/rockchip/rk3399/Kconfig.soc b/soc/arm64/rockchip/rk3399/Kconfig.soc deleted file mode 100644 index 74fb8b6d7d8..00000000000 --- a/soc/arm64/rockchip/rk3399/Kconfig.soc +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -choice -prompt "Rockchip RK3399 SoC" -depends on SOC_SERIES_RK3399 - -config SOC_RK3399 - bool "Rockchip RK3399" - select ARM64 - select CPU_CORTEX_A53 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - -endchoice diff --git a/soc/arm64/rockchip/rk3568/CMakeLists.txt b/soc/arm64/rockchip/rk3568/CMakeLists.txt deleted file mode 100644 index 2cf9a407f84..00000000000 --- a/soc/arm64/rockchip/rk3568/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) diff --git a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.series b/soc/arm64/rockchip/rk3568/Kconfig.defconfig.series deleted file mode 100644 index 96279038e4a..00000000000 --- a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyr -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RK3568 - -config SOC_SERIES - default "rk3568" - -source "soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568" - -endif # SOC_SERIES_RK3568 diff --git a/soc/arm64/rockchip/rk3568/Kconfig.series b/soc/arm64/rockchip/rk3568/Kconfig.series deleted file mode 100644 index 15909e5bff0..00000000000 --- a/soc/arm64/rockchip/rk3568/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyrs -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RK3568 - bool "Rockchip RK3568 Series" - select ARM64 - select SOC_FAMILY_ROCKCHIP - help - Enable support for RK3568 Series. diff --git a/soc/arm64/rockchip/rk3568/Kconfig.soc b/soc/arm64/rockchip/rk3568/Kconfig.soc deleted file mode 100644 index 7bb2be41909..00000000000 --- a/soc/arm64/rockchip/rk3568/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyr -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Rockchip RK3568 SoC" -depends on SOC_SERIES_RK3568 - -config SOC_RK3568 - bool "Rockchip rk3568" - select ARM64 - select CPU_CORTEX_A55 - select ARM_ARCH_TIMER - select GIC_V3 - -endchoice diff --git a/soc/arm64/rockchip/rk3568/linker.ld b/soc/arm64/rockchip/rk3568/linker.ld deleted file mode 100644 index f1b07809e1f..00000000000 --- a/soc/arm64/rockchip/rk3568/linker.ld +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright 2020 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include diff --git a/soc/arm64/ti_k3/CMakeLists.txt b/soc/arm64/ti_k3/CMakeLists.txt deleted file mode 100644 index f16a8498786..00000000000 --- a/soc/arm64/ti_k3/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/ti_k3/Kconfig b/soc/arm64/ti_k3/Kconfig deleted file mode 100644 index 081632c0b88..00000000000 --- a/soc/arm64/ti_k3/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_TI_K3 - bool - -if SOC_FAMILY_TI_K3 - -config SOC_FAMILY - string - default "ti_k3" - -source "soc/arm64/ti_k3/*/Kconfig.soc" - -endif # SOC_FAMILY_TI_K3 diff --git a/soc/arm64/ti_k3/Kconfig.defconfig b/soc/arm64/ti_k3/Kconfig.defconfig deleted file mode 100644 index 18eeadee4e0..00000000000 --- a/soc/arm64/ti_k3/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/ti_k3/*/Kconfig.defconfig.series" diff --git a/soc/arm64/ti_k3/Kconfig.soc b/soc/arm64/ti_k3/Kconfig.soc deleted file mode 100644 index 7d48f5cee1d..00000000000 --- a/soc/arm64/ti_k3/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/ti_k3/*/Kconfig.series" diff --git a/soc/arm64/ti_k3/am6x/CMakeLists.txt b/soc/arm64/ti_k3/am6x/CMakeLists.txt deleted file mode 100644 index 491cafbec22..00000000000 --- a/soc/arm64/ti_k3/am6x/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/ti_k3/am6x/Kconfig.defconfig.am6234 b/soc/arm64/ti_k3/am6x/Kconfig.defconfig.am6234 deleted file mode 100644 index a22567299c5..00000000000 --- a/soc/arm64/ti_k3/am6x/Kconfig.defconfig.am6234 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -if SOC_AM6234_A53 - -config SOC - default "am6234" - -endif # SOC_AM6234_A53 diff --git a/soc/arm64/ti_k3/am6x/Kconfig.defconfig.series b/soc/arm64/ti_k3/am6x/Kconfig.defconfig.series deleted file mode 100644 index 066acc7d668..00000000000 --- a/soc/arm64/ti_k3/am6x/Kconfig.defconfig.series +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_AM6X_A53 - -config SOC_SERIES - default "am6x" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - int - default 280 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 200000000 - -config PINCTRL - default y - -if SERIAL - -config UART_NS16550 - default y - -choice UART_NS16550_VARIANT - default UART_NS16550_VARIANT_NS16750 -endchoice - -endif # SERIAL - -source "soc/arm64/ti_k3/am6x/Kconfig.defconfig.am62*" - -endif # SOC_SERIES_AM6X_A53 diff --git a/soc/arm64/ti_k3/am6x/Kconfig.series b/soc/arm64/ti_k3/am6x/Kconfig.series deleted file mode 100644 index 1de6052d9ed..00000000000 --- a/soc/arm64/ti_k3/am6x/Kconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_AM6X_A53 - bool "TI AM6X A53 Core Series" - select SOC_FAMILY_TI_K3 - select ARM64 - select CPU_CORTEX_A53 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - help - Enable support for AM6X A53 Series. diff --git a/soc/arm64/ti_k3/am6x/Kconfig.soc b/soc/arm64/ti_k3/am6x/Kconfig.soc deleted file mode 100644 index 74dbb7fedae..00000000000 --- a/soc/arm64/ti_k3/am6x/Kconfig.soc +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "TI AM6X A53 Selection" -depends on SOC_SERIES_AM6X_A53 - -config SOC_AM6234_A53 - bool "TI AM6234 A53" - select SOC_PART_NUMBER_AM6234 - -endchoice - -config SOC_PART_NUMBER_AM6234 - bool - -config SOC_PART_NUMBER_AM6X_A53 - string - default "AM6234" if SOC_PART_NUMBER_AM6234 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_AM6X_A53 if SOC_SERIES_AM6X_A53 diff --git a/soc/arm64/xenvm/Kconfig.defconfig b/soc/arm64/xenvm/Kconfig.defconfig deleted file mode 100644 index 4a88b6bed93..00000000000 --- a/soc/arm64/xenvm/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright 2020 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if SOC_XENVM - -config SOC - default "xenvm" - -config NUM_IRQS - int - default 500 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 8320000 - -# We need at least 16M of virtual address space to map memory of Xen node -# 32M should be enough for basic use-cases -config KERNEL_VM_SIZE - default 0x2000000 - -endif diff --git a/soc/arm64/xenvm/Kconfig.soc b/soc/arm64/xenvm/Kconfig.soc deleted file mode 100644 index 00f1bf0ca31..00000000000 --- a/soc/arm64/xenvm/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2020 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XENVM - bool "Xen virtual machine on aarch64" - select ARM64 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select CPU_CORTEX_A72 diff --git a/soc/arm/aspeed/CMakeLists.txt b/soc/aspeed/CMakeLists.txt similarity index 100% rename from soc/arm/aspeed/CMakeLists.txt rename to soc/aspeed/CMakeLists.txt diff --git a/soc/aspeed/Kconfig b/soc/aspeed/Kconfig new file mode 100644 index 00000000000..5d28220c246 --- /dev/null +++ b/soc/aspeed/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +config SOC_FAMILY_ASPEED + select PLATFORM_SPECIFIC_INIT + +if SOC_FAMILY_ASPEED + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ASPEED diff --git a/soc/aspeed/Kconfig.defconfig b/soc/aspeed/Kconfig.defconfig new file mode 100644 index 00000000000..c0d309927f1 --- /dev/null +++ b/soc/aspeed/Kconfig.defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +if SOC_FAMILY_ASPEED + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_ASPEED diff --git a/soc/aspeed/Kconfig.soc b/soc/aspeed/Kconfig.soc new file mode 100644 index 00000000000..546bd4db95b --- /dev/null +++ b/soc/aspeed/Kconfig.soc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +config SOC_FAMILY_ASPEED + bool + +config SOC_FAMILY + default "aspeed" if SOC_FAMILY_ASPEED + +rsource "*/Kconfig.soc" diff --git a/soc/arm/aspeed/aspeed_util.h b/soc/aspeed/aspeed_util.h similarity index 100% rename from soc/arm/aspeed/aspeed_util.h rename to soc/aspeed/aspeed_util.h diff --git a/soc/aspeed/ast10x0/CMakeLists.txt b/soc/aspeed/ast10x0/CMakeLists.txt new file mode 100644 index 00000000000..c7de81fc8f1 --- /dev/null +++ b/soc/aspeed/ast10x0/CMakeLists.txt @@ -0,0 +1,18 @@ +# Copyright (c) 2021 ASPEED Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) +zephyr_include_directories(.) +zephyr_linker_sources(ROM_START SORT_KEY 0x1sboot sboot.ld) +zephyr_linker_sources(RAM_SECTIONS nocache.ld) + +string(TOUPPER "${SOC_NAME}" soc_name_upper) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${SOC_${soc_name_upper}_DIR}/${SOC_SERIES}/tools/gen_uart_booting_image.py + ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin + ${PROJECT_BINARY_DIR}/uart_${CONFIG_KERNEL_BIN_NAME}.bin +) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/aspeed/ast10x0/Kconfig b/soc/aspeed/ast10x0/Kconfig new file mode 100644 index 00000000000..847980d6b27 --- /dev/null +++ b/soc/aspeed/ast10x0/Kconfig @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +config SOC_SERIES_AST10X0 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SYSCON + select CACHE + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CACHE_MANAGEMENT + select CACHE_ASPEED + +if SOC_SERIES_AST10X0 + +config SRAM_NC_SIZE + int "noncached SRAM Size in kB" + help + The non-cached SRAM size in kB. The default value comes from reg[1] + of /chosen/zephyr,sram in devicetree. The user should generally avoid + changing it via menuconfig or in configuration files. + +config SRAM_NC_BASE_ADDRESS + hex "noncached SRAM Base Address" + help + The non-cached SRAM base address. The default value comes from from + reg[1] of /chosen/zephyr,sram in devicetree. The user should + generally avoid changing it via menuconfig or in configuration files. + +endif # SOC_SERIES_AST10X0 diff --git a/soc/aspeed/ast10x0/Kconfig.defconfig b/soc/aspeed/ast10x0/Kconfig.defconfig new file mode 100644 index 00000000000..6b8b4a07558 --- /dev/null +++ b/soc/aspeed/ast10x0/Kconfig.defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +if SOC_SERIES_AST10X0 + +rsource "Kconfig.defconfig.ast10*0" + +config ICACHE_LINE_SIZE + default 32 + +config DCACHE_LINE_SIZE + default 32 + +choice CACHE_TYPE + default EXTERNAL_CACHE +endchoice + +endif # SOC_SERIES_AST10X0 diff --git a/soc/arm/aspeed/ast10x0/Kconfig.defconfig.ast1030 b/soc/aspeed/ast10x0/Kconfig.defconfig.ast1030 similarity index 100% rename from soc/arm/aspeed/ast10x0/Kconfig.defconfig.ast1030 rename to soc/aspeed/ast10x0/Kconfig.defconfig.ast1030 diff --git a/soc/aspeed/ast10x0/Kconfig.soc b/soc/aspeed/ast10x0/Kconfig.soc new file mode 100644 index 00000000000..5bc45abc901 --- /dev/null +++ b/soc/aspeed/ast10x0/Kconfig.soc @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +config SOC_SERIES_AST10X0 + bool + select SOC_FAMILY_ASPEED + help + Enable support for ASPEED AST10X0 series + +config SOC_AST1030 + bool + select SOC_SERIES_AST10X0 + help + AST1030 + +config SOC_SERIES + default "ast10x0" if SOC_SERIES_AST10X0 + +config SOC + default "ast1030" if SOC_AST1030 diff --git a/soc/arm/aspeed/ast10x0/linker.ld b/soc/aspeed/ast10x0/linker.ld similarity index 100% rename from soc/arm/aspeed/ast10x0/linker.ld rename to soc/aspeed/ast10x0/linker.ld diff --git a/soc/arm/aspeed/ast10x0/nocache.ld b/soc/aspeed/ast10x0/nocache.ld similarity index 100% rename from soc/arm/aspeed/ast10x0/nocache.ld rename to soc/aspeed/ast10x0/nocache.ld diff --git a/soc/arm/aspeed/ast10x0/sboot.ld b/soc/aspeed/ast10x0/sboot.ld similarity index 100% rename from soc/arm/aspeed/ast10x0/sboot.ld rename to soc/aspeed/ast10x0/sboot.ld diff --git a/soc/arm/aspeed/ast10x0/soc.c b/soc/aspeed/ast10x0/soc.c similarity index 100% rename from soc/arm/aspeed/ast10x0/soc.c rename to soc/aspeed/ast10x0/soc.c diff --git a/soc/arm/aspeed/ast10x0/soc.h b/soc/aspeed/ast10x0/soc.h similarity index 100% rename from soc/arm/aspeed/ast10x0/soc.h rename to soc/aspeed/ast10x0/soc.h diff --git a/soc/arm/aspeed/ast10x0/tools/gen_uart_booting_image.py b/soc/aspeed/ast10x0/tools/gen_uart_booting_image.py similarity index 100% rename from soc/arm/aspeed/ast10x0/tools/gen_uart_booting_image.py rename to soc/aspeed/ast10x0/tools/gen_uart_booting_image.py diff --git a/soc/aspeed/soc.yml b/soc/aspeed/soc.yml new file mode 100644 index 00000000000..48e8d78efd3 --- /dev/null +++ b/soc/aspeed/soc.yml @@ -0,0 +1,6 @@ +family: + - name: aspeed + series: + - name: ast10x0 + socs: + - name: ast1030 diff --git a/soc/atmel/sam/CMakeLists.txt b/soc/atmel/sam/CMakeLists.txt new file mode 100644 index 00000000000..b379b725d92 --- /dev/null +++ b/soc/atmel/sam/CMakeLists.txt @@ -0,0 +1,9 @@ +# Makefile - Atmel SAM MCU family +# +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +# + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) diff --git a/soc/atmel/sam/Kconfig b/soc/atmel/sam/Kconfig new file mode 100644 index 00000000000..68228c4d3e7 --- /dev/null +++ b/soc/atmel/sam/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ATMEL_SAM + select ASF + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +if SOC_FAMILY_ATMEL_SAM + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ATMEL_SAM diff --git a/soc/atmel/sam/Kconfig.defconfig b/soc/atmel/sam/Kconfig.defconfig new file mode 100644 index 00000000000..49ad6145223 --- /dev/null +++ b/soc/atmel/sam/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Atmel SAM MCU family default configuration options + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ATMEL_SAM + +rsource "*/Kconfig.defconfig" + +config CLOCK_CONTROL + default y + +config GPIO + default y + +config PINCTRL + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config WATCHDOG + default y + +endif # SOC_FAMILY_ATMEL_SAM diff --git a/soc/atmel/sam/Kconfig.soc b/soc/atmel/sam/Kconfig.soc new file mode 100644 index 00000000000..5f65786c86b --- /dev/null +++ b/soc/atmel/sam/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ATMEL_SAM + bool + +config SOC_FAMILY + default "atmel_sam" if SOC_FAMILY_ATMEL_SAM + +rsource "*/Kconfig.soc" diff --git a/soc/atmel/sam/common/CMakeLists.txt b/soc/atmel/sam/common/CMakeLists.txt new file mode 100644 index 00000000000..8f53f047230 --- /dev/null +++ b/soc/atmel/sam/common/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_pmc.c) +zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_gpio.c) +zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_supc.c) +zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_power.c) +zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_poweroff.c) + +zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_pm.c) +zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_gpio.c) +zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_poweroff.c) diff --git a/soc/atmel/sam/common/Kconfig b/soc/atmel/sam/common/Kconfig new file mode 100644 index 00000000000..2642a40eda7 --- /dev/null +++ b/soc/atmel/sam/common/Kconfig @@ -0,0 +1,96 @@ +# Atmel SAM MCU series general configuration options + +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L + +menu "Clocks" + +config SOC_ATMEL_SAM_EXT_SLCK + bool "Use external crystal oscillator for slow clock" + help + Says y if you want to use external 32 kHz crystal oscillator to drive + the slow clock. Note that this adds a few seconds to boot time, as the + crystal needs to stabilize after power-up. + + Says n if you do not need accurate and precise timers. The slow clock + will be driven by the internal fast RC oscillator running at 32 kHz. + +config SOC_ATMEL_SAM_EXT_MAINCK + bool "Use external crystal oscillator for main clock" + default y + help + The main clock is being used to drive the PLL, and thus driving the + processor clock. + + Says y if you want to use external crystal oscillator to drive the + main clock. Note that this adds about a second to boot time, as the + crystal needs to stabilize after power-up. + + The crystal used here can be from 3 to 20 MHz. + + Says n here will use the internal fast RC oscillator running at 12 MHz. + +menu "PLL A" + +config SOC_ATMEL_SAM_PLLA_MULA + int "PLL MULA" + default 6 if SOC_SERIES_SAM3X + default 9 if SOC_SERIES_SAM4S || SOC_SERIES_SAM4E + default 24 if SOC_SERIES_SAME70 || SOC_SERIES_SAMV71 + range 1 62 + help + This is the multiplier (MULA) used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings for a particular board. + + With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times + the main clock frequency. + +config SOC_ATMEL_SAM_PLLA_DIVA + int "PLL DIVA" + default 1 + range 1 255 + help + This is the divider (DIVA) used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings + for a particular board. + + With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times + the main clock frequency. + +config SOC_ATMEL_SAM_MDIV + int "MDIV" + depends on SOC_SERIES_SAME70 || SOC_SERIES_SAMV71 + default 2 + range 1 4 + help + This divisor defines a ratio between processor clock (HCLK) + and master clock (MCK) where the maximum value is 150MHz: + MCK = HCLK / MDIV + +endmenu # PLL A +endmenu # clocks + +config SOC_ATMEL_SAM_WAIT_MODE + bool "CPU goes to Wait mode instead of Sleep mode" + depends on SOC_ATMEL_SAM_EXT_MAINCK + default y if DEBUG + help + For JTAG debugging CPU clock (HCLK) should not stop. In order to + achieve this, make CPU go to Wait mode instead of Sleep mode while + using external crystal oscillator for main clock. + +config SOC_ATMEL_SAM_DISABLE_ERASE_PIN + bool "Disable ERASE pin" + help + At reset ERASE pin is configured in System IO mode. Asserting the + ERASE pin at '1' will completely erase Flash memory. Setting this + option will switch the pin to general IO mode giving control of the + pin to the GPIO module. + +endif # SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L diff --git a/soc/arm/atmel_sam/common/atmel_sam_dt.h b/soc/atmel/sam/common/atmel_sam_dt.h similarity index 100% rename from soc/arm/atmel_sam/common/atmel_sam_dt.h rename to soc/atmel/sam/common/atmel_sam_dt.h diff --git a/soc/arm/atmel_sam/common/pinctrl_soc.h b/soc/atmel/sam/common/pinctrl_soc.h similarity index 100% rename from soc/arm/atmel_sam/common/pinctrl_soc.h rename to soc/atmel/sam/common/pinctrl_soc.h diff --git a/soc/arm/atmel_sam/common/pwm_fixup.h b/soc/atmel/sam/common/pwm_fixup.h similarity index 100% rename from soc/arm/atmel_sam/common/pwm_fixup.h rename to soc/atmel/sam/common/pwm_fixup.h diff --git a/soc/arm/atmel_sam/common/soc_gpio.c b/soc/atmel/sam/common/soc_gpio.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_gpio.c rename to soc/atmel/sam/common/soc_gpio.c diff --git a/soc/arm/atmel_sam/common/soc_gpio.h b/soc/atmel/sam/common/soc_gpio.h similarity index 100% rename from soc/arm/atmel_sam/common/soc_gpio.h rename to soc/atmel/sam/common/soc_gpio.h diff --git a/soc/arm/atmel_sam/common/soc_pmc.c b/soc/atmel/sam/common/soc_pmc.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_pmc.c rename to soc/atmel/sam/common/soc_pmc.c diff --git a/soc/arm/atmel_sam/common/soc_pmc.h b/soc/atmel/sam/common/soc_pmc.h similarity index 100% rename from soc/arm/atmel_sam/common/soc_pmc.h rename to soc/atmel/sam/common/soc_pmc.h diff --git a/soc/arm/atmel_sam/common/soc_power.c b/soc/atmel/sam/common/soc_power.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_power.c rename to soc/atmel/sam/common/soc_power.c diff --git a/soc/arm/atmel_sam/common/soc_poweroff.c b/soc/atmel/sam/common/soc_poweroff.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_poweroff.c rename to soc/atmel/sam/common/soc_poweroff.c diff --git a/soc/arm/atmel_sam/common/soc_sam4l_gpio.c b/soc/atmel/sam/common/soc_sam4l_gpio.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_sam4l_gpio.c rename to soc/atmel/sam/common/soc_sam4l_gpio.c diff --git a/soc/arm/atmel_sam/common/soc_sam4l_pm.c b/soc/atmel/sam/common/soc_sam4l_pm.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_sam4l_pm.c rename to soc/atmel/sam/common/soc_sam4l_pm.c diff --git a/soc/arm/atmel_sam/common/soc_sam4l_poweroff.c b/soc/atmel/sam/common/soc_sam4l_poweroff.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_sam4l_poweroff.c rename to soc/atmel/sam/common/soc_sam4l_poweroff.c diff --git a/soc/arm/atmel_sam/common/soc_supc.c b/soc/atmel/sam/common/soc_supc.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_supc.c rename to soc/atmel/sam/common/soc_supc.c diff --git a/soc/arm/atmel_sam/common/soc_supc.h b/soc/atmel/sam/common/soc_supc.h similarity index 100% rename from soc/arm/atmel_sam/common/soc_supc.h rename to soc/atmel/sam/common/soc_supc.h diff --git a/soc/atmel/sam/sam3x/CMakeLists.txt b/soc/atmel/sam/sam3x/CMakeLists.txt new file mode 100644 index 00000000000..6a01266941a --- /dev/null +++ b/soc/atmel/sam/sam3x/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/sam3x/Kconfig b/soc/atmel/sam/sam3x/Kconfig new file mode 100644 index 00000000000..1f66f4ef398 --- /dev/null +++ b/soc/atmel/sam/sam3x/Kconfig @@ -0,0 +1,15 @@ +# Atmel SAM3X MCU series + +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# Copyright (c) 2016 Intel Corporation. +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM3X + select ARM + select CPU_CORTEX_M3 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select PLATFORM_SPECIFIC_INIT + select HAS_POWEROFF diff --git a/soc/atmel/sam/sam3x/Kconfig.defconfig b/soc/atmel/sam/sam3x/Kconfig.defconfig new file mode 100644 index 00000000000..7a41eb6fad7 --- /dev/null +++ b/soc/atmel/sam/sam3x/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Atmel SAM3X MCU series configuration options + +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# Copyright (c) 2016 Intel Corporation. +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAM3X + +config NUM_IRQS + default 45 + +endif # SOC_SERIES_SAM3X diff --git a/soc/atmel/sam/sam3x/Kconfig.soc b/soc/atmel/sam/sam3x/Kconfig.soc new file mode 100644 index 00000000000..7ab817c8891 --- /dev/null +++ b/soc/atmel/sam/sam3x/Kconfig.soc @@ -0,0 +1,43 @@ +# Atmel SAM3X MCU series + +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# Copyright (c) 2016 Intel Corporation. +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM3X + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM3X MCU Series + +config SOC_SERIES + default "sam3x" if SOC_SERIES_SAM3X + +config SOC_SAM3X4C + bool + select SOC_SERIES_SAM3X + +config SOC_SAM3X4E + bool + select SOC_SERIES_SAM3X + +config SOC_SAM3X8C + bool + select SOC_SERIES_SAM3X + +config SOC_SAM3X8E + bool + select SOC_SERIES_SAM3X + +config SOC_SAM3X8H + bool + select SOC_SERIES_SAM3X + +config SOC + default "sam3x4c" if SOC_SAM3X4C + default "sam3x4e" if SOC_SAM3X4E + default "sam3x8c" if SOC_SAM3X8C + default "sam3x8e" if SOC_SAM3X8E + default "sam3x8h" if SOC_SAM3X8H diff --git a/soc/atmel/sam/sam3x/soc.c b/soc/atmel/sam/sam3x/soc.c new file mode 100644 index 00000000000..08e803c4f1d --- /dev/null +++ b/soc/atmel/sam/sam3x/soc.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2023 Basalte bv + * Copyright (c) 2023-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Atmel SAM3X MCU series initialization code + * + * This module provides routines to initialize and support board-level hardware + * for the Atmel SAM3X series processor. + */ + +#include +#include +#include + +/** + * @brief Setup various clocks on SoC at boot time. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Switch the main clock to the internal OSC with 12MHz */ + soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); + + /* Switch MCK (Master Clock) to the main clock */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); + + EFC0->EEFC_FMR = EEFC_FMR_FWS(0); + EFC1->EEFC_FMR = EEFC_FMR_FWS(0); + + soc_pmc_enable_clock_failure_detector(); + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) { + soc_supc_slow_clock_select_crystal_osc(); + } + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + /* + * Setup main external crystal oscillator. + */ + + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + soc_pmc_switch_mainck_to_xtal(false, 0xff); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. + * TODO: set FWS based on the actual MCK frequency and VDDCORE value + * rather than maximum supported 84 MHz at standard VDDCORE=1.8V + */ + EFC0->EEFC_FMR = EEFC_FMR_FWS(4); + EFC1->EEFC_FMR = EEFC_FMR_FWS(4); + + /* + * Setup PLLA + */ + + /* + * PLL clock = Main * (MULA + 1) / DIVA + * + * By default, MULA == 6, DIVA == 1. + * With main crystal running at 12 MHz, + * PLL = 12 * (6 + 1) / 1 = 84 MHz + * + * With Processor Clock prescaler at 1 + * Processor Clock (HCLK) = 84 MHz. + */ + soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu, + CONFIG_SOC_ATMEL_SAM_PLLA_DIVA); + + /* + * Final setup of the Master Clock + */ + + /* prescaler has to be set before PLL lock */ + soc_pmc_mck_set_prescaler(1); + + /* Select PLL as Master Clock source. */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); + + /* Disable internal fast RC if we have an external crystal oscillator */ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + soc_pmc_osc_disable_fastrc(); + } +} + +void z_arm_platform_init(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) { + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + soc_pmc_enable_waitmode(); + } + /* Setup system clocks */ + clock_init(); +} diff --git a/soc/atmel/sam/sam3x/soc.h b/soc/atmel/sam/sam3x/soc.h new file mode 100644 index 00000000000..b47450ac052 --- /dev/null +++ b/soc/atmel/sam/sam3x/soc.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Register access macros for the Atmel SAM3X MCU. + * + * This file provides register access macros for the Atmel SAM3X MCU, HAL + * drivers for core peripherals as well as symbols specific to Atmel SAM family. + */ + +#ifndef _SOC_ATMEL_SAM_SAM3X_SOC_H_ +#define _SOC_ATMEL_SAM_SAM3X_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAM3X4C) +#include +#elif defined(CONFIG_SOC_SAM3X4E) +#include +#elif defined(CONFIG_SOC_SAM3X8C) +#include +#elif defined(CONFIG_SOC_SAM3X8E) +#include +#elif defined(CONFIG_SOC_SAM3X8H) +#include +#else +#error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/soc_supc.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ + +#endif /* _ASMLANGUAGE */ + +#endif /* _SOC_ATMEL_SAM_SAM3X_SOC_H_ */ diff --git a/soc/atmel/sam/sam4e/CMakeLists.txt b/soc/atmel/sam/sam4e/CMakeLists.txt new file mode 100644 index 00000000000..6a01266941a --- /dev/null +++ b/soc/atmel/sam/sam4e/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/sam4e/Kconfig b/soc/atmel/sam/sam4e/Kconfig new file mode 100644 index 00000000000..57441f1eaef --- /dev/null +++ b/soc/atmel/sam/sam4e/Kconfig @@ -0,0 +1,15 @@ +# Atmel SAM4E MCU series + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4E + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT + select HAS_POWEROFF diff --git a/soc/atmel/sam/sam4e/Kconfig.defconfig b/soc/atmel/sam/sam4e/Kconfig.defconfig new file mode 100644 index 00000000000..bb3d457731d --- /dev/null +++ b/soc/atmel/sam/sam4e/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Atmel SAM4E MCU series configuration options + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAM4E + +config NUM_IRQS + default 47 + +endif # SOC_SERIES_SAM4E diff --git a/soc/atmel/sam/sam4e/Kconfig.soc b/soc/atmel/sam/sam4e/Kconfig.soc new file mode 100644 index 00000000000..5cbc0c8781c --- /dev/null +++ b/soc/atmel/sam/sam4e/Kconfig.soc @@ -0,0 +1,37 @@ +# Atmel SAM4E MCU series + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4E + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM4E MCU series + +config SOC_SERIES + default "sam4e" if SOC_SERIES_SAM4E + +config SOC_SAM4E16E + bool + select SOC_SERIES_SAM4E + +config SOC_SAM4E16C + bool + select SOC_SERIES_SAM4E + +config SOC_SAM4E8E + bool + select SOC_SERIES_SAM4E + +config SOC_SAM4E8C + bool + select SOC_SERIES_SAM4E + +config SOC + default "sam4e16e" if SOC_SAM4E16E + default "sam4e16c" if SOC_SAM4E16C + default "sam4e8e" if SOC_SAM4E8E + default "sam4e8c" if SOC_SAM4E8C diff --git a/soc/atmel/sam/sam4e/soc.c b/soc/atmel/sam/sam4e/soc.c new file mode 100644 index 00000000000..82468f48738 --- /dev/null +++ b/soc/atmel/sam/sam4e/soc.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2019-2024 Gerson Fernando Budke + * Copyright (c) 2023 Basalte bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Atmel SAM4E MCU series initialization code + * + * This module provides routines to initialize and support board-level hardware + * for the Atmel SAM4E series processor. + */ + +#include +#include +#include + +/** + * @brief Setup various clock on SoC at boot time. + * + * Setup the SoC clocks according to section 28.12 in datasheet. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Switch the main clock to the internal OSC with 12MHz */ + soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); + + /* Switch MCK (Master Clock) to the main clock */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); + + EFC->EEFC_FMR = EEFC_FMR_FWS(0); + + soc_pmc_enable_clock_failure_detector(); + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) { + soc_supc_slow_clock_select_crystal_osc(); + } + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + /* + * Setup main external crystal oscillator. + */ + + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + soc_pmc_switch_mainck_to_xtal(false, 0xff); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. Look at table 44.73 in the SAM4E datasheet. + * This is set to the highest number of read cycles because it won't + * hurt lower clock frequencies. However, a high frequency with too + * few read cycles could cause flash read problems. FWS 5 (6 cycles) + * is the safe setting for all of this SoCs usable frequencies. + */ + EFC->EEFC_FMR = EEFC_FMR_FWS(5); + + /* + * Setup PLLA + */ + soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu, + CONFIG_SOC_ATMEL_SAM_PLLA_DIVA); + + /* + * Final setup of the Master Clock + */ + + /* prescaler has to be set before PLL lock */ + soc_pmc_mck_set_prescaler(1); + + /* Select PLL as Master Clock source. */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); + + /* Disable internal fast RC if we have an external crystal oscillator */ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + soc_pmc_osc_disable_fastrc(); + } +} + +void z_arm_platform_init(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) { + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + soc_pmc_enable_waitmode(); + } + /* Setup system clocks. */ + clock_init(); +} diff --git a/soc/atmel/sam/sam4e/soc.h b/soc/atmel/sam/sam4e/soc.h new file mode 100644 index 00000000000..78b42a231c0 --- /dev/null +++ b/soc/atmel/sam/sam4e/soc.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2018 Vincent van der Locht + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2019-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Atmel SAM4E family processors. + */ + +#ifndef _SOC_ATMEL_SAM_SAM4E_SOC_H_ +#define _SOC_ATMEL_SAM_SAM4E_SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAM4E16E) +#include +#elif defined(CONFIG_SOC_SAM4E16C) +#include +#elif defined(CONFIG_SOC_SAM4E8E) +#include +#elif defined(CONFIG_SOC_SAM4E8C) +#include +#else +#error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/soc_supc.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC_ATMEL_SAM_SAM4E_SOC_H_ */ diff --git a/soc/atmel/sam/sam4l/CMakeLists.txt b/soc/atmel/sam/sam4l/CMakeLists.txt new file mode 100644 index 00000000000..6a01266941a --- /dev/null +++ b/soc/atmel/sam/sam4l/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/sam4l/Kconfig b/soc/atmel/sam/sam4l/Kconfig new file mode 100644 index 00000000000..15ad8ba2583 --- /dev/null +++ b/soc/atmel/sam/sam4l/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2020-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4L + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select PLATFORM_SPECIFIC_INIT + select HAS_POWEROFF diff --git a/soc/atmel/sam/sam4l/Kconfig.defconfig b/soc/atmel/sam/sam4l/Kconfig.defconfig new file mode 100644 index 00000000000..72116af1342 --- /dev/null +++ b/soc/atmel/sam/sam4l/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2020-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAM4L + +config NUM_IRQS + default 80 + +endif # SOC_SERIES_SAM4L diff --git a/soc/atmel/sam/sam4l/Kconfig.soc b/soc/atmel/sam/sam4l/Kconfig.soc new file mode 100644 index 00000000000..e622f8a70d1 --- /dev/null +++ b/soc/atmel/sam/sam4l/Kconfig.soc @@ -0,0 +1,107 @@ +# Copyright (c) 2020-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4L + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM4L Cortex-M4 microcontrollers. + Part No.: SAM4LS8C, SAM4LS8B, SAM4LS8A, SAM4LS4C, SAM4LS4B, + SAM4LS4A, SAM4LS2C, SAM4LS2B, SAM4LS2A, SAM4LC8C, SAM4LC8B, + SAM4LC8A, SAM4LC4C, SAM4LC4B, SAM4LC4A SAM4LC2C, SAM4LC2B, + SAM4LC2A + +config SOC_SERIES + default "sam4l" if SOC_SERIES_SAM4L + +config SOC_SAM4LS2A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS2B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS2C + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS4A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS4B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS4C + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS8A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS8B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS8C + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC2A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC2B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC2C + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC4A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC4B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC4C + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC8A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC8B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC8C + bool + select SOC_SERIES_SAM4L + +config SOC + default "sam4ls2a" if SOC_SAM4LS2A + default "sam4ls2b" if SOC_SAM4LS2B + default "sam4ls2c" if SOC_SAM4LS2C + default "sam4ls4a" if SOC_SAM4LS4A + default "sam4ls4b" if SOC_SAM4LS4B + default "sam4ls4c" if SOC_SAM4LS4C + default "sam4ls8a" if SOC_SAM4LS8A + default "sam4ls8b" if SOC_SAM4LS8B + default "sam4ls8c" if SOC_SAM4LS8C + default "sam4lc2a" if SOC_SAM4LC2A + default "sam4lc2b" if SOC_SAM4LC2B + default "sam4lc2c" if SOC_SAM4LC2C + default "sam4lc4a" if SOC_SAM4LC4A + default "sam4lc4b" if SOC_SAM4LC4B + default "sam4lc4c" if SOC_SAM4LC4C + default "sam4lc8a" if SOC_SAM4LC8A + default "sam4lc8b" if SOC_SAM4LC8B + default "sam4lc8c" if SOC_SAM4LC8C diff --git a/soc/arm/atmel_sam/sam4l/soc.c b/soc/atmel/sam/sam4l/soc.c similarity index 100% rename from soc/arm/atmel_sam/sam4l/soc.c rename to soc/atmel/sam/sam4l/soc.c diff --git a/soc/atmel/sam/sam4l/soc.h b/soc/atmel/sam/sam4l/soc.h new file mode 100644 index 00000000000..329178aa288 --- /dev/null +++ b/soc/atmel/sam/sam4l/soc.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2020-2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Atmel SAM4L family processors. + */ + +#ifndef _SOC_ATMEL_SAM_SAM4L_SOC_H_ +#define _SOC_ATMEL_SAM_SAM4L_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAM4LS8C) +#include +#elif defined(CONFIG_SOC_SAM4LS8B) +#include +#elif defined(CONFIG_SOC_SAM4LS8A) +#include +#elif defined(CONFIG_SOC_SAM4LS4C) +#include +#elif defined(CONFIG_SOC_SAM4LS4B) +#include +#elif defined(CONFIG_SOC_SAM4LS4A) +#include +#elif defined(CONFIG_SOC_SAM4LS2C) +#include +#elif defined(CONFIG_SOC_SAM4LS2B) +#include +#elif defined(CONFIG_SOC_SAM4LS2A) +#include +#elif defined(CONFIG_SOC_SAM4LC8C) +#include +#elif defined(CONFIG_SOC_SAM4LC8B) +#include +#elif defined(CONFIG_SOC_SAM4LC8A) +#include +#elif defined(CONFIG_SOC_SAM4LC4C) +#include +#elif defined(CONFIG_SOC_SAM4LC4B) +#include +#elif defined(CONFIG_SOC_SAM4LC4A) +#include +#elif defined(CONFIG_SOC_SAM4LC2C) +#include +#elif defined(CONFIG_SOC_SAM4LC2B) +#include +#elif defined(CONFIG_SOC_SAM4LC2A) +#include +#else +#error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ + +/** Oscillator identifiers + * External Oscillator 0 + * External 32 kHz oscillator + * Internal 32 kHz RC oscillator + * Internal 80 MHz RC oscillator + * Internal 4-8-12 MHz RCFAST oscillator + * Internal 1 MHz RC oscillator + * Internal System RC oscillator + */ +#define OSC_ID_OSC0 0 +#define OSC_ID_OSC32 1 +#define OSC_ID_RC32K 2 +#define OSC_ID_RC80M 3 +#define OSC_ID_RCFAST 4 +#define OSC_ID_RC1M 5 +#define OSC_ID_RCSYS 6 + +/** System clock source + * System RC oscillator + * Oscillator 0 + * Phase Locked Loop 0 + * Digital Frequency Locked Loop + * 80 MHz RC oscillator + * 4-8-12 MHz RC oscillator + * 1 MHz RC oscillator + */ +#define OSC_SRC_RCSYS 0 +#define OSC_SRC_OSC0 1 +#define OSC_SRC_PLL0 2 +#define OSC_SRC_DFLL 3 +#define OSC_SRC_RC80M 4 +#define OSC_SRC_RCFAST 5 +#define OSC_SRC_RC1M 6 + +#define PM_CLOCK_MASK(bus, per) ((bus << 5) + per) + +/** Bus index of maskable module clocks. Peripheral ids are defined out of + * order. It start from PBA up to PBD, then move to HSB, and finally CPU. + */ +#define PM_CLK_GRP_CPU 5 +#define PM_CLK_GRP_HSB 4 +#define PM_CLK_GRP_PBA 0 +#define PM_CLK_GRP_PBB 1 +#define PM_CLK_GRP_PBC 2 +#define PM_CLK_GRP_PBD 3 + +/** Clocks derived from the CPU clock + */ +#define SYSCLK_OCD 0 + +/** Clocks derived from the HSB clock + */ +#define SYSCLK_PDCA_HSB 0 +#define SYSCLK_HFLASHC_DATA 1 +#define SYSCLK_HRAMC1_DATA 2 +#define SYSCLK_USBC_DATA 3 +#define SYSCLK_CRCCU_DATA 4 +#define SYSCLK_PBA_BRIDGE 5 +#define SYSCLK_PBB_BRIDGE 6 +#define SYSCLK_PBC_BRIDGE 7 +#define SYSCLK_PBD_BRIDGE 8 +#define SYSCLK_AESA_HSB 9 + +/** Clocks derived from the PBA clock + */ +#define SYSCLK_IISC 0 +#define SYSCLK_SPI 1 +#define SYSCLK_TC0 2 +#define SYSCLK_TC1 3 +#define SYSCLK_TWIM0 4 +#define SYSCLK_TWIS0 5 +#define SYSCLK_TWIM1 6 +#define SYSCLK_TWIS1 7 +#define SYSCLK_USART0 8 +#define SYSCLK_USART1 9 +#define SYSCLK_USART2 10 +#define SYSCLK_USART3 11 +#define SYSCLK_ADCIFE 12 +#define SYSCLK_DACC 13 +#define SYSCLK_ACIFC 14 +#define SYSCLK_GLOC 15 +#define SYSCLK_ABDACB 16 +#define SYSCLK_TRNG 17 +#define SYSCLK_PARC 18 +#define SYSCLK_CATB 19 +#define SYSCLK_TWIM2 21 +#define SYSCLK_TWIM3 22 +#define SYSCLK_LCDCA 23 + +/** Clocks derived from the PBB clock + */ +#define SYSCLK_HFLASHC_REGS 0 +#define SYSCLK_HRAMC1_REGS 1 +#define SYSCLK_HMATRIX 2 +#define SYSCLK_PDCA_PB 3 +#define SYSCLK_CRCCU_REGS 4 +#define SYSCLK_USBC_REGS 5 +#define SYSCLK_PEVC 6 + +/** Clocks derived from the PBC clock + */ +#define SYSCLK_PM 0 +#define SYSCLK_CHIPID 1 +#define SYSCLK_SCIF 2 +#define SYSCLK_FREQM 3 +#define SYSCLK_GPIO 4 + +/** Clocks derived from the PBD clock + */ +#define SYSCLK_BPM 0 +#define SYSCLK_BSCIF 1 +#define SYSCLK_AST 2 +#define SYSCLK_WDT 3 +#define SYSCLK_EIC 4 +#define SYSCLK_PICOUART 5 + +/** Divided clock mask derived from the PBA clock + */ +#define PBA_DIVMASK_TIMER_CLOCK2 (1u << 0) +#define PBA_DIVMASK_TIMER_CLOCK3 (1u << 2) +#define PBA_DIVMASK_CLK_USART (1u << 2) +#define PBA_DIVMASK_TIMER_CLOCK4 (1u << 4) +#define PBA_DIVMASK_TIMER_CLOCK5 (1u << 6) +#define PBA_DIVMASK_Msk (0x7Fu << 0) + +/** Generic Clock Instances + * 0- DFLLIF main reference and GCLK0 pin (CLK_DFLLIF_REF) + * 1- DFLLIF dithering and SSG reference and GCLK1 pin (CLK_DFLLIF_DITHER) + * 2- AST and GCLK2 pin + * 3- CATB and GCLK3 pin + * 4- AESA + * 5- GLOC, TC0 and RC32KIFB_REF + * 6- ABDACB and IISC + * 7- USBC + * 8- TC1 and PEVC[0] + * 9- PLL0 and PEVC[1] + * 10- ADCIFE + * 11- Master generic clock. Can be used as source for other generic clocks. + */ +#define GEN_CLK_DFLL_REF 0 +#define GEN_CLK_DFLL_DITHER 1 +#define GEN_CLK_AST 2 +#define GEN_CLK_CATB 3 +#define GEN_CLK_AESA 4 +#define GEN_CLK_GLOC 5 +#define GEN_CLK_ABDACB 6 +#define GEN_CLK_USBC 7 +#define GEN_CLK_TC1_PEVC0 8 +#define GEN_CLK_PLL0_PEVC1 9 +#define GEN_CLK_ADCIFE 10 +#define GEN_CLK_MASTER_GEN 11 + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC_ATMEL_SAM_SAM4L_SOC_H_ */ diff --git a/soc/atmel/sam/sam4s/CMakeLists.txt b/soc/atmel/sam/sam4s/CMakeLists.txt new file mode 100644 index 00000000000..6a01266941a --- /dev/null +++ b/soc/atmel/sam/sam4s/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/sam4s/Kconfig b/soc/atmel/sam/sam4s/Kconfig new file mode 100644 index 00000000000..26836bc509b --- /dev/null +++ b/soc/atmel/sam/sam4s/Kconfig @@ -0,0 +1,14 @@ +# Atmel SAM4S MCU series + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2020-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4S + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select PLATFORM_SPECIFIC_INIT + select HAS_POWEROFF diff --git a/soc/atmel/sam/sam4s/Kconfig.defconfig b/soc/atmel/sam/sam4s/Kconfig.defconfig new file mode 100644 index 00000000000..bc78f97f404 --- /dev/null +++ b/soc/atmel/sam/sam4s/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Atmel SAM4S MCU series configuration options + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAM4S + +config NUM_IRQS + default 35 + +endif # SOC_SERIES_SAM4S diff --git a/soc/atmel/sam/sam4s/Kconfig.soc b/soc/atmel/sam/sam4s/Kconfig.soc new file mode 100644 index 00000000000..3e3cf5bb3b7 --- /dev/null +++ b/soc/atmel/sam/sam4s/Kconfig.soc @@ -0,0 +1,74 @@ +# Atmel SAM4S MCU series + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4S + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM4S Cortex-M4 microcontrollers. + Part No.: SAM4S16C, SAM4S16B, SAM4S8C, SAM4S8B, + SAM4S4C, SAM4S4B, SAM4S4A, SAM4S2C, SAM4S2B, SAM4S2A + +config SOC_SERIES + default "sam4s" if SOC_SERIES_SAM4S + +config SOC_SAM4S2A + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S2B + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S2C + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S4A + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S4B + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S4C + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S8B + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S8C + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S16B + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S16C + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4SA16C + bool + select SOC_SERIES_SAM4S + +config SOC + default "sam4s2a" if SOC_SAM4S2A + default "sam4s2b" if SOC_SAM4S2B + default "sam4s2c" if SOC_SAM4S2C + default "sam4s4a" if SOC_SAM4S4A + default "sam4s4b" if SOC_SAM4S4B + default "sam4s4c" if SOC_SAM4S4C + default "sam4s8b" if SOC_SAM4S8B + default "sam4s8c" if SOC_SAM4S8C + default "sam4s16b" if SOC_SAM4S16B + default "sam4s16c" if SOC_SAM4S16C + default "sam4sa16c" if SOC_SAM4SA16C diff --git a/soc/atmel/sam/sam4s/soc.c b/soc/atmel/sam/sam4s/soc.c new file mode 100644 index 00000000000..09c42eae391 --- /dev/null +++ b/soc/atmel/sam/sam4s/soc.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2023 Basalte bv + * Copyright (c) 2023-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Atmel SAM4S MCU series initialization code + * + * This module provides routines to initialize and support board-level hardware + * for the Atmel SAM4S series processor. + */ + +#include +#include +#include + +/** + * @brief Setup various clock on SoC at boot time. + * + * Setup the SoC clocks according to section 28.12 in datasheet. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Switch the main clock to the internal OSC with 12MHz */ + soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); + + /* Switch MCK (Master Clock) to the main clock */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); + + EFC0->EEFC_FMR = EEFC_FMR_FWS(0); +#if defined(ID_EFC1) + EFC1->EEFC_FMR = EEFC_FMR_FWS(0); +#endif + + soc_pmc_enable_clock_failure_detector(); + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) { + soc_supc_slow_clock_select_crystal_osc(); + } + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + /* + * Setup main external crystal oscillator. + */ + + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + soc_pmc_switch_mainck_to_xtal(false, 0xff); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. Look at table 44.73 in the SAM4S datasheet. + * This is set to the highest number of read cycles because it won't + * hurt lower clock frequencies. However, a high frequency with too + * few read cycles could cause flash read problems. FWS 5 (6 cycles) + * is the safe setting for all of this SoCs usable frequencies. + */ + EFC0->EEFC_FMR = EEFC_FMR_FWS(5); +#if defined(ID_EFC1) + EFC1->EEFC_FMR = EEFC_FMR_FWS(5); +#endif + + /* + * Setup PLLA + */ + soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu, + CONFIG_SOC_ATMEL_SAM_PLLA_DIVA); + + /* + * Final setup of the Master Clock + */ + + /* prescaler has to be set before PLL lock */ + soc_pmc_mck_set_prescaler(1); + + /* Select PLL as Master Clock source. */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); + + /* Disable internal fast RC if we have an external crystal oscillator */ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + soc_pmc_osc_disable_fastrc(); + } +} + +void z_arm_platform_init(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) { + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + soc_pmc_enable_waitmode(); + } + + /* Setup system clocks. */ + clock_init(); +} diff --git a/soc/atmel/sam/sam4s/soc.h b/soc/atmel/sam/sam4s/soc.h new file mode 100644 index 00000000000..f74692d6ba8 --- /dev/null +++ b/soc/atmel/sam/sam4s/soc.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2018 Vincent van der Locht + * Copyright (c) 2020-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Atmel SAM4S family processors. + */ + +#ifndef _SOC_ATMEL_SAM_SAM4S_SOC_H_ +#define _SOC_ATMEL_SAM_SAM4S_SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAM4S16C) +#include +#elif defined(CONFIG_SOC_SAM4SA16C) +#include +#elif defined(CONFIG_SOC_SAM4S16B) +#include +#elif defined(CONFIG_SOC_SAM4S8C) +#include +#elif defined(CONFIG_SOC_SAM4S8B) +#include +#elif defined(CONFIG_SOC_SAM4S4C) +#include +#elif defined(CONFIG_SOC_SAM4S4B) +#include +#elif defined(CONFIG_SOC_SAM4S4A) +#include +#elif defined(CONFIG_SOC_SAM4S2C) +#include +#elif defined(CONFIG_SOC_SAM4S2B) +#include +#elif defined(CONFIG_SOC_SAM4S2A) +#include +#else +#error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/soc_supc.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC_ATMEL_SAM_SAM4S_SOC_H_ */ diff --git a/soc/atmel/sam/same70/CMakeLists.txt b/soc/atmel/sam/same70/CMakeLists.txt new file mode 100644 index 00000000000..2ed685c2f6f --- /dev/null +++ b/soc/atmel/sam/same70/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + soc_config.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/same70/Kconfig b/soc/atmel/sam/same70/Kconfig new file mode 100644 index 00000000000..f799cd43c69 --- /dev/null +++ b/soc/atmel/sam/same70/Kconfig @@ -0,0 +1,19 @@ +# Atmel SAM E70 MCU series + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME70 + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select INIT_ARCH_HW_AT_BOOT + select PLATFORM_SPECIFIC_INIT + select HAS_SWO + select XIP + select HAS_POWEROFF diff --git a/soc/atmel/sam/same70/Kconfig.defconfig b/soc/atmel/sam/same70/Kconfig.defconfig new file mode 100644 index 00000000000..6d2a78218c2 --- /dev/null +++ b/soc/atmel/sam/same70/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Atmel SAM E70 MCU series configuration options + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAME70 + +config NUM_IRQS + default 74 if SOC_ATMEL_SAME70_REVB + default 71 + +endif # SOC_SERIES_SAME70 diff --git a/soc/atmel/sam/same70/Kconfig.soc b/soc/atmel/sam/same70/Kconfig.soc new file mode 100644 index 00000000000..1cef18f21f1 --- /dev/null +++ b/soc/atmel/sam/same70/Kconfig.soc @@ -0,0 +1,122 @@ +# Atmel SAM E70 MCU series + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME70 + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers. + Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20, + SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21, SAME70J19B, SAME70J20B, + SAME70J21B, SAME70N19B, SAME70N20B, SAME70N21B, SAME70Q19B, + SAME70Q20B, SAME70Q21B + +config SOC_ATMEL_SAME70_REVB + bool + +config SOC_SERIES + default "same70" if SOC_SERIES_SAME70 + +config SOC_SAME70J19 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70J20 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70J21 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70N19 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70N20 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70N21 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70Q19 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70Q20 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70Q21 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70J19B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70J20B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70J21B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70N19B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70N20B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70N21B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70Q19B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70Q20B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70Q21B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC + default "same70j19" if SOC_SAME70J19 + default "same70j20" if SOC_SAME70J20 + default "same70j21" if SOC_SAME70J21 + default "same70n19" if SOC_SAME70N19 + default "same70n20" if SOC_SAME70N20 + default "same70n21" if SOC_SAME70N21 + default "same70q19" if SOC_SAME70Q19 + default "same70q20" if SOC_SAME70Q20 + default "same70q21" if SOC_SAME70Q21 + default "same70j19b" if SOC_SAME70J19B + default "same70j20b" if SOC_SAME70J20B + default "same70j21b" if SOC_SAME70J21B + default "same70n19b" if SOC_SAME70N19B + default "same70n20b" if SOC_SAME70N20B + default "same70n21b" if SOC_SAME70N21B + default "same70q19b" if SOC_SAME70Q19B + default "same70q20b" if SOC_SAME70Q20B + default "same70q21b" if SOC_SAME70Q21B diff --git a/soc/atmel/sam/same70/soc.c b/soc/atmel/sam/same70/soc.c new file mode 100644 index 00000000000..ba3a44e875a --- /dev/null +++ b/soc/atmel/sam/same70/soc.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2023-2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Atmel SAM E70 MCU initialization code + * + * This file provides routines to initialize and support board-level hardware + * for the Atmel SAM E70 MCU. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL +LOG_MODULE_REGISTER(soc); + +/** + * @brief Setup various clocks on SoC at boot time. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Switch the main clock to the internal OSC with 12MHz */ + soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); + + /* Switch MCK (Master Clock) to the main clock */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); + + EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; + + soc_pmc_enable_clock_failure_detector(); + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) { + soc_supc_slow_clock_select_crystal_osc(); + } + + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + /* + * Setup main external crystal oscillator. + */ + + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + soc_pmc_switch_mainck_to_xtal(false, 0xff); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. + * TODO: set FWS based on the actual MCK frequency and VDDIO value + * rather than maximum supported 150 MHz at standard VDDIO=2.7V + */ + EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; + + /* + * Setup PLLA + */ + + /* + * PLL clock = Main * (MULA + 1) / DIVA + * + * By default, MULA == 24, DIVA == 1. + * With main crystal running at 12 MHz, + * PLL = 12 * (24 + 1) / 1 = 300 MHz + * + * With Processor Clock prescaler at 1 + * Processor Clock (HCLK)=300 MHz. + */ + soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu, + CONFIG_SOC_ATMEL_SAM_PLLA_DIVA); + + + soc_pmc_enable_upllck(0x3Fu); + + /* + * Final setup of the Master Clock + */ + + /* Setting PLLA as MCK, first prescaler, then divider and source last */ + soc_pmc_mck_set_prescaler(1); + soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV); + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); + + + /* Disable internal fast RC if we have an external crystal oscillator */ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + soc_pmc_osc_disable_fastrc(); + } +} + +void z_arm_platform_init(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) { + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + soc_pmc_enable_waitmode(); + } + + /* + * DTCM is enabled by default at reset, therefore we have to disable + * it first to get the caches into a state where then the + * sys_cache*-functions can enable them, if requested by the + * configuration. + */ + SCB_DisableDCache(); + + /* + * Enable the caches only if configured to do so. + */ + sys_cache_instr_enable(); + sys_cache_data_enable(); + + /* Setup system clocks */ + clock_init(); +} + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run at the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int atmel_same70_init(void) +{ + /* Check that the CHIP CIDR matches the HAL one */ + if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { + LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", + (uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR); + } + + return 0; +} + +SYS_INIT(atmel_same70_init, PRE_KERNEL_1, 0); diff --git a/soc/atmel/sam/same70/soc.h b/soc/atmel/sam/same70/soc.h new file mode 100644 index 00000000000..92cec70d926 --- /dev/null +++ b/soc/atmel/sam/same70/soc.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Register access macros for the Atmel SAM E70 MCU. + * + * This file provides register access macros for the Atmel SAM E70 MCU, HAL + * drivers for core peripherals as well as symbols specific to Atmel SAM family. + */ + +#ifndef _SOC_ATMEL_SAM_SAME70_SOC_H_ +#define _SOC_ATMEL_SAM_SAME70_SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAME70J19) +#include +#elif defined(CONFIG_SOC_SAME70J20) +#include +#elif defined(CONFIG_SOC_SAME70J21) +#include +#elif defined(CONFIG_SOC_SAME70N19) +#include +#elif defined(CONFIG_SOC_SAME70N20) +#include +#elif defined(CONFIG_SOC_SAME70N21) +#include +#elif defined(CONFIG_SOC_SAME70Q19) +#include +#elif defined(CONFIG_SOC_SAME70Q20) +#include +#elif defined(CONFIG_SOC_SAME70Q21) +#include +#elif defined(CONFIG_SOC_SAME70J19B) +#include +#elif defined(CONFIG_SOC_SAME70J20B) +#include +#elif defined(CONFIG_SOC_SAME70J21B) +#include +#elif defined(CONFIG_SOC_SAME70N19B) +#include +#elif defined(CONFIG_SOC_SAME70N20B) +#include +#elif defined(CONFIG_SOC_SAME70N21B) +#include +#elif defined(CONFIG_SOC_SAME70Q19B) +#include +#elif defined(CONFIG_SOC_SAME70Q20B) +#include +#elif defined(CONFIG_SOC_SAME70Q21B) +#include +#else + #error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/soc_supc.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ \ + (SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM_MDIV) + +/** UTMI PLL clock (UPLLCK) Frequency */ +#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480) + +#endif /* _ASMLANGUAGE */ + +#endif /* _SOC_ATMEL_SAM_SAME70_SOC_H_ */ diff --git a/soc/atmel/sam/same70/soc_config.c b/soc/atmel/sam/same70/soc_config.c new file mode 100644 index 00000000000..cd1f8b80d76 --- /dev/null +++ b/soc/atmel/sam/same70/soc_config.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief System module to support early Atmel SAM E70 MCU configuration + */ + +#include +#include +#include +#include + +/** + * @brief Perform SoC configuration at boot. + * + * This should be run early during the boot process but after basic hardware + * initialization is done. + * + * @return 0 + */ +static int atmel_same70_config(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) { + /* Disable ERASE function on PB12 pin, this is controlled + * by Bus Matrix + */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; + } + + /* In Cortex-M based SoCs JTAG interface can be used to perform + * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug + * interface therefore there is no harm done by disabling the JTAG TDI + * pin by default. + */ + /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; + + if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) { + /* Disable PCK3 clock used by ETM module */ + PMC->PMC_SCDR = PMC_SCDR_PCK3; + while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { + ; + } + /* Select PLLA clock as PCK3 clock */ + PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; + /* Enable PCK3 clock */ + PMC->PMC_SCER = PMC_SCER_PCK3; + /* Wait for PCK3 setup to complete */ + while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { + ; + } + /* Enable TDO/TRACESWO function on PB5 pin */ + MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5; + } else { + /* Disable TDO/TRACESWO function on PB5 pin */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5; + } + + return 0; +} + +SYS_INIT(atmel_same70_config, PRE_KERNEL_1, 1); diff --git a/soc/atmel/sam/samv71/CMakeLists.txt b/soc/atmel/sam/samv71/CMakeLists.txt new file mode 100644 index 00000000000..2ed685c2f6f --- /dev/null +++ b/soc/atmel/sam/samv71/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + soc_config.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/samv71/Kconfig b/soc/atmel/sam/samv71/Kconfig new file mode 100644 index 00000000000..682adb4a715 --- /dev/null +++ b/soc/atmel/sam/samv71/Kconfig @@ -0,0 +1,19 @@ +# Atmel SAM V71 MCU series + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMV71 + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select INIT_ARCH_HW_AT_BOOT + select PLATFORM_SPECIFIC_INIT + select HAS_SWO + select XIP + select HAS_POWEROFF diff --git a/soc/atmel/sam/samv71/Kconfig.defconfig b/soc/atmel/sam/samv71/Kconfig.defconfig new file mode 100644 index 00000000000..2eefe71ec55 --- /dev/null +++ b/soc/atmel/sam/samv71/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Atmel SAM V71 MCU series configuration options + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMV71 + +config NUM_IRQS + default 74 if SOC_ATMEL_SAMV71_REVB + default 71 + +endif # SOC_SERIES_SAMV71 diff --git a/soc/atmel/sam/samv71/Kconfig.soc b/soc/atmel/sam/samv71/Kconfig.soc new file mode 100644 index 00000000000..180ed60c49d --- /dev/null +++ b/soc/atmel/sam/samv71/Kconfig.soc @@ -0,0 +1,122 @@ +# Atmel SAM V71 MCU series + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMV71 + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers. + Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20, + SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B, + SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B, + SAMV71Q20B, SAMV71Q21B + +config SOC_ATMEL_SAMV71_REVB + bool + +config SOC_SERIES + default "samv71" if SOC_SERIES_SAMV71 + +config SOC_SAMV71J19 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71J20 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71J21 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71N19 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71N20 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71N21 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71Q19 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71Q20 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71Q21 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71J19B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71J20B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71J21B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71N19B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71N20B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71N21B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71Q19B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71Q20B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71Q21B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC + default "samv71j19" if SOC_SAMV71J19 + default "samv71j20" if SOC_SAMV71J20 + default "samv71j21" if SOC_SAMV71J21 + default "samv71n19" if SOC_SAMV71N19 + default "samv71n20" if SOC_SAMV71N20 + default "samv71n21" if SOC_SAMV71N21 + default "samv71q19" if SOC_SAMV71Q19 + default "samv71q20" if SOC_SAMV71Q20 + default "samv71q21" if SOC_SAMV71Q21 + default "samv71j19b" if SOC_SAMV71J19B + default "samv71j20b" if SOC_SAMV71J20B + default "samv71j21b" if SOC_SAMV71J21B + default "samv71n19b" if SOC_SAMV71N19B + default "samv71n20b" if SOC_SAMV71N20B + default "samv71n21b" if SOC_SAMV71N21B + default "samv71q19b" if SOC_SAMV71Q19B + default "samv71q20b" if SOC_SAMV71Q20B + default "samv71q21b" if SOC_SAMV71Q21B diff --git a/soc/atmel/sam/samv71/soc.c b/soc/atmel/sam/samv71/soc.c new file mode 100644 index 00000000000..c1b58bc126e --- /dev/null +++ b/soc/atmel/sam/samv71/soc.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2019-2023 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Atmel SAM V71 MCU initialization code + * + * This file provides routines to initialize and support board-level hardware + * for the Atmel SAM V71 MCU. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL +LOG_MODULE_REGISTER(soc); + +/** + * @brief Setup various clocks on SoC at boot time. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Switch the main clock to the internal OSC with 12MHz */ + soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); + + /* Switch MCK (Master Clock) to the main clock */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); + + EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; + + soc_pmc_enable_clock_failure_detector(); + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) { + soc_supc_slow_clock_select_crystal_osc(); + } + + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + /* + * Setup main external crystal oscillator. + */ + + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + soc_pmc_switch_mainck_to_xtal(false, 0xff); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. + * TODO: set FWS based on the actual MCK frequency and VDDIO value + * rather than maximum supported 150 MHz at standard VDDIO=2.7V + */ + EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; + + /* + * Setup PLLA + */ + + /* + * PLL clock = Main * (MULA + 1) / DIVA + * + * By default, MULA == 24, DIVA == 1. + * With main crystal running at 12 MHz, + * PLL = 12 * (24 + 1) / 1 = 300 MHz + * + * With Processor Clock prescaler at 1 + * Processor Clock (HCLK)=300 MHz. + */ + soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu, + CONFIG_SOC_ATMEL_SAM_PLLA_DIVA); + + + soc_pmc_enable_upllck(0x3Fu); + + /* + * Final setup of the Master Clock + */ + + /* Setting PLLA as MCK, first prescaler, then divider and source last */ + soc_pmc_mck_set_prescaler(1); + soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV); + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); + + /* Disable internal fast RC if we have an external crystal oscillator */ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + soc_pmc_osc_disable_fastrc(); + } +} + +void z_arm_platform_init(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) { + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + soc_pmc_enable_waitmode(); + } + + /* + * DTCM is enabled by default at reset, therefore we have to disable + * it first to get the caches into a state where then the + * sys_cache*-functions can enable them, if requested by the + * configuration. + */ + SCB_DisableDCache(); + + /* + * Enable the caches only if configured to do so. + */ + sys_cache_instr_enable(); + sys_cache_data_enable(); + + /* Setup system clocks */ + clock_init(); +} + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run at the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int atmel_samv71_init(void) +{ + /* Check that the CHIP CIDR matches the HAL one */ + if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { + LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", + (uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR); + } + + return 0; +} + +SYS_INIT(atmel_samv71_init, PRE_KERNEL_1, 0); diff --git a/soc/atmel/sam/samv71/soc.h b/soc/atmel/sam/samv71/soc.h new file mode 100644 index 00000000000..8b54125bce5 --- /dev/null +++ b/soc/atmel/sam/samv71/soc.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2019-2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Register access macros for the Atmel SAM V71 MCU. + * + * This file provides register access macros for the Atmel SAM V71 MCU, HAL + * drivers for core peripherals as well as symbols specific to Atmel SAM family. + */ + +#ifndef _SOC_ATMEL_SAM_SAMV71_SOC_H_ +#define _SOC_ATMEL_SAM_SAMV71_SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAMV71J19) +#include +#elif defined(CONFIG_SOC_SAMV71J20) +#include +#elif defined(CONFIG_SOC_SAMV71J21) +#include +#elif defined(CONFIG_SOC_SAMV71N19) +#include +#elif defined(CONFIG_SOC_SAMV71N20) +#include +#elif defined(CONFIG_SOC_SAMV71N21) +#include +#elif defined(CONFIG_SOC_SAMV71Q19) +#include +#elif defined(CONFIG_SOC_SAMV71Q20) +#include +#elif defined(CONFIG_SOC_SAMV71Q21) +#include +#elif defined(CONFIG_SOC_SAMV71J19B) +#include +#elif defined(CONFIG_SOC_SAMV71J20B) +#include +#elif defined(CONFIG_SOC_SAMV71J21B) +#include +#elif defined(CONFIG_SOC_SAMV71N19B) +#include +#elif defined(CONFIG_SOC_SAMV71N20B) +#include +#elif defined(CONFIG_SOC_SAMV71N21B) +#include +#elif defined(CONFIG_SOC_SAMV71Q19B) +#include +#elif defined(CONFIG_SOC_SAMV71Q20B) +#include +#elif defined(CONFIG_SOC_SAMV71Q21B) +#include +#else + #error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/soc_supc.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ \ + (SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM_MDIV) + +/** UTMI PLL clock (UPLLCK) Frequency */ +#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480) + +#endif /* _ASMLANGUAGE */ + +#include "pwm_fixup.h" + +#endif /* _SOC_ATMEL_SAM_SAMV71_SOC_H_ */ diff --git a/soc/atmel/sam/samv71/soc_config.c b/soc/atmel/sam/samv71/soc_config.c new file mode 100644 index 00000000000..51638a997b3 --- /dev/null +++ b/soc/atmel/sam/samv71/soc_config.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2019-2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief System module to support early Atmel SAM V71 MCU configuration + */ + +#include +#include +#include +#include + +/** + * @brief Perform SoC configuration at boot. + * + * This should be run early during the boot process but after basic hardware + * initialization is done. + * + * @return 0 + */ +static int atmel_samv71_config(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) { + /* Disable ERASE function on PB12 pin, this is controlled + * by Bus Matrix + */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; + } + + /* In Cortex-M based SoCs JTAG interface can be used to perform + * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug + * interface therefore there is no harm done by disabling the JTAG TDI + * pin by default. + */ + /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix + */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; + + if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) { + /* Disable PCK3 clock used by ETM module */ + PMC->PMC_SCDR = PMC_SCDR_PCK3; + while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { + ; + } + /* Select PLLA clock as PCK3 clock */ + PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; + /* Enable PCK3 clock */ + PMC->PMC_SCER = PMC_SCER_PCK3; + /* Wait for PCK3 setup to complete */ + while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { + ; + } + /* Enable TDO/TRACESWO function on PB5 pin */ + MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5; + } else { + /* Disable TDO/TRACESWO function on PB5 pin */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5; + } + + return 0; +} + +SYS_INIT(atmel_samv71_config, PRE_KERNEL_1, 1); diff --git a/soc/atmel/sam/soc.yml b/soc/atmel/sam/soc.yml new file mode 100644 index 00000000000..9d95bcdf147 --- /dev/null +++ b/soc/atmel/sam/soc.yml @@ -0,0 +1,89 @@ +family: +- name: atmel_sam + series: + - name: sam3x + socs: + - name: sam3x4c + - name: sam3x4e + - name: sam3x8c + - name: sam3x8e + - name: sam3x8h + - name: sam4e + socs: + - name: sam4e8c + - name: sam4e8e + - name: sam4e16c + - name: sam4e16e + - name: sam4l + socs: + - name: sam4ls2a + - name: sam4ls2b + - name: sam4ls2c + - name: sam4ls4a + - name: sam4ls4b + - name: sam4ls4c + - name: sam4ls8a + - name: sam4ls8b + - name: sam4ls8c + - name: sam4lc2a + - name: sam4lc2b + - name: sam4lc2c + - name: sam4lc4a + - name: sam4lc4b + - name: sam4lc4c + - name: sam4lc8a + - name: sam4lc8b + - name: sam4lc8c + - name: sam4s + socs: + - name: sam4s2a + - name: sam4s2b + - name: sam4s2c + - name: sam4s4a + - name: sam4s4b + - name: sam4s4c + - name: sam4s8b + - name: sam4s8c + - name: sam4s16b + - name: sam4s16c + - name: sam4sa16c + - name: same70 + socs: + - name: same70j19 + - name: same70j20 + - name: same70j21 + - name: same70n19 + - name: same70n20 + - name: same70n21 + - name: same70q19 + - name: same70q20 + - name: same70q21 + - name: same70j19b + - name: same70j20b + - name: same70j21b + - name: same70n19b + - name: same70n20b + - name: same70n21b + - name: same70q19b + - name: same70q20b + - name: same70q21b + - name: samv71 + socs: + - name: samv71j19 + - name: samv71j20 + - name: samv71j21 + - name: samv71n19 + - name: samv71n20 + - name: samv71n21 + - name: samv71q19 + - name: samv71q20 + - name: samv71q21 + - name: samv71j19b + - name: samv71j20b + - name: samv71j21b + - name: samv71n19b + - name: samv71n20b + - name: samv71n21b + - name: samv71q19b + - name: samv71q20b + - name: samv71q21b diff --git a/soc/atmel/sam0/CMakeLists.txt b/soc/atmel/sam0/CMakeLists.txt new file mode 100644 index 00000000000..377651e4f4d --- /dev/null +++ b/soc/atmel/sam0/CMakeLists.txt @@ -0,0 +1,10 @@ +# Makefile - Atmel SAM0 MCU family +# +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) diff --git a/soc/atmel/sam0/Kconfig b/soc/atmel/sam0/Kconfig new file mode 100644 index 00000000000..f5d2f29b879 --- /dev/null +++ b/soc/atmel/sam0/Kconfig @@ -0,0 +1,16 @@ +# Atmel SAM0 MCU family configuration options + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ATMEL_SAM0 + select ASF + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +if SOC_FAMILY_ATMEL_SAM0 + +rsource "common/Kconfig.sam*" +rsource "*/Kconfig" + +endif # SOC_FAMILY_ATMEL_SAM0 diff --git a/soc/atmel/sam0/Kconfig.defconfig b/soc/atmel/sam0/Kconfig.defconfig new file mode 100644 index 00000000000..2980bbe87c4 --- /dev/null +++ b/soc/atmel/sam0/Kconfig.defconfig @@ -0,0 +1,30 @@ +# Atmel SAM0 MCU family default configuration options + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ATMEL_SAM0 + +rsource "*/Kconfig.defconfig" + +config GPIO + default y + +config HWINFO_SAM0 + default HWINFO + +config PINCTRL + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +if USB_DEVICE_DRIVER + +config HEAP_MEM_POOL_ADD_SIZE_SOC + def_int 1024 + +endif # USB_DEVICE_DRIVER + +endif # SOC_FAMILY_ATMEL_SAM0 diff --git a/soc/atmel/sam0/Kconfig.soc b/soc/atmel/sam0/Kconfig.soc new file mode 100644 index 00000000000..96697d51625 --- /dev/null +++ b/soc/atmel/sam0/Kconfig.soc @@ -0,0 +1,21 @@ +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2022-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ATMEL_SAM0 + bool + +config SOC_FAMILY + default "atmel_sam0" if SOC_FAMILY_ATMEL_SAM0 + +config SOC_SERIES_REVISION_N + bool + depends on SOC_FAMILY_ATMEL_SAM0 + +config SOC_SERIES_REVISION + string + default "n" if SOC_SERIES_REVISION_N + default "" + depends on SOC_FAMILY_ATMEL_SAM0 + +rsource "*/Kconfig.soc" diff --git a/soc/arm/atmel_sam0/common/CMakeLists.txt b/soc/atmel/sam0/common/CMakeLists.txt similarity index 100% rename from soc/arm/atmel_sam0/common/CMakeLists.txt rename to soc/atmel/sam0/common/CMakeLists.txt diff --git a/soc/arm/atmel_sam0/common/Kconfig.samd2x b/soc/atmel/sam0/common/Kconfig.samd2x similarity index 100% rename from soc/arm/atmel_sam0/common/Kconfig.samd2x rename to soc/atmel/sam0/common/Kconfig.samd2x diff --git a/soc/arm/atmel_sam0/common/Kconfig.samd5x b/soc/atmel/sam0/common/Kconfig.samd5x similarity index 75% rename from soc/arm/atmel_sam0/common/Kconfig.samd5x rename to soc/atmel/sam0/common/Kconfig.samd5x index fabb588379c..dd05fe605d1 100644 --- a/soc/arm/atmel_sam0/common/Kconfig.samd5x +++ b/soc/atmel/sam0/common/Kconfig.samd5x @@ -12,10 +12,17 @@ config SOC_ATMEL_SAMD5X_XOSC32K choice prompt "Main clock source" + default SOC_ATMEL_SAMD5X_DEFAULT_AS_MAIN help Selects the clock that the main clocks, such as the CPU clock and AHB clock, will be derived from. +config SOC_ATMEL_SAMD5X_DEFAULT_AS_MAIN + bool "DEFAULT" + help + This choice will leave all clocks to their current state. + This can be the default reset state or a state set by a bootloader. + config SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN depends on SOC_ATMEL_SAMD5X_XOSC32K bool "XOSC32K" diff --git a/soc/arm/atmel_sam0/common/Kconfig.saml2x b/soc/atmel/sam0/common/Kconfig.saml2x similarity index 100% rename from soc/arm/atmel_sam0/common/Kconfig.saml2x rename to soc/atmel/sam0/common/Kconfig.saml2x index 7dfa137678a..d250f1adaf0 100644 --- a/soc/arm/atmel_sam0/common/Kconfig.saml2x +++ b/soc/atmel/sam0/common/Kconfig.saml2x @@ -71,8 +71,6 @@ config SOC_ATMEL_SAML_OSC16M_AS_MAIN endchoice -endif # SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35 - config SOC_ATMEL_SAMR3X_RADIO_OFF_SETUP bool "Configure LoRa radio pins if not in use" default y if !LORA @@ -84,3 +82,5 @@ config SOC_ATMEL_SAMR3X_RADIO_OFF_SETUP further reduce power consumption, radio can be kept in reset state by keeping nRST pin low. When enabling this option, both CS and nRST will be configured high and low, respectively. + +endif # SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35 diff --git a/soc/arm/atmel_sam0/common/adc_fixup_sam0.h b/soc/atmel/sam0/common/adc_fixup_sam0.h similarity index 100% rename from soc/arm/atmel_sam0/common/adc_fixup_sam0.h rename to soc/atmel/sam0/common/adc_fixup_sam0.h diff --git a/soc/arm/atmel_sam0/common/atmel_sam0_dt.h b/soc/atmel/sam0/common/atmel_sam0_dt.h similarity index 100% rename from soc/arm/atmel_sam0/common/atmel_sam0_dt.h rename to soc/atmel/sam0/common/atmel_sam0_dt.h diff --git a/soc/arm/atmel_sam0/common/bossa.c b/soc/atmel/sam0/common/bossa.c similarity index 100% rename from soc/arm/atmel_sam0/common/bossa.c rename to soc/atmel/sam0/common/bossa.c diff --git a/soc/arm/atmel_sam0/common/gmac_fixup_samd5x.h b/soc/atmel/sam0/common/gmac_fixup_samd5x.h similarity index 100% rename from soc/arm/atmel_sam0/common/gmac_fixup_samd5x.h rename to soc/atmel/sam0/common/gmac_fixup_samd5x.h diff --git a/soc/arm/atmel_sam0/common/pinctrl_soc.h b/soc/atmel/sam0/common/pinctrl_soc.h similarity index 100% rename from soc/arm/atmel_sam0/common/pinctrl_soc.h rename to soc/atmel/sam0/common/pinctrl_soc.h diff --git a/soc/arm/atmel_sam0/common/sercom_fixup_samd5x.h b/soc/atmel/sam0/common/sercom_fixup_samd5x.h similarity index 100% rename from soc/arm/atmel_sam0/common/sercom_fixup_samd5x.h rename to soc/atmel/sam0/common/sercom_fixup_samd5x.h diff --git a/soc/arm/atmel_sam0/common/soc_port.c b/soc/atmel/sam0/common/soc_port.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_port.c rename to soc/atmel/sam0/common/soc_port.c diff --git a/soc/arm/atmel_sam0/common/soc_port.h b/soc/atmel/sam0/common/soc_port.h similarity index 100% rename from soc/arm/atmel_sam0/common/soc_port.h rename to soc/atmel/sam0/common/soc_port.h diff --git a/soc/arm/atmel_sam0/common/soc_samc2x.c b/soc/atmel/sam0/common/soc_samc2x.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_samc2x.c rename to soc/atmel/sam0/common/soc_samc2x.c diff --git a/soc/arm/atmel_sam0/common/soc_samd2x.c b/soc/atmel/sam0/common/soc_samd2x.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_samd2x.c rename to soc/atmel/sam0/common/soc_samd2x.c diff --git a/soc/arm/atmel_sam0/common/soc_samd5x.c b/soc/atmel/sam0/common/soc_samd5x.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_samd5x.c rename to soc/atmel/sam0/common/soc_samd5x.c diff --git a/soc/arm/atmel_sam0/common/soc_saml2x.c b/soc/atmel/sam0/common/soc_saml2x.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_saml2x.c rename to soc/atmel/sam0/common/soc_saml2x.c diff --git a/soc/arm/atmel_sam0/common/soc_samr3x_radio_off.c b/soc/atmel/sam0/common/soc_samr3x_radio_off.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_samr3x_radio_off.c rename to soc/atmel/sam0/common/soc_samr3x_radio_off.c diff --git a/soc/arm/atmel_sam0/common/tc_fixup_samd5x.h b/soc/atmel/sam0/common/tc_fixup_samd5x.h similarity index 100% rename from soc/arm/atmel_sam0/common/tc_fixup_samd5x.h rename to soc/atmel/sam0/common/tc_fixup_samd5x.h diff --git a/soc/atmel/sam0/samc20/CMakeLists.txt b/soc/atmel/sam0/samc20/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/samc20/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samc20/Kconfig b/soc/atmel/sam0/samc20/Kconfig new file mode 100644 index 00000000000..8c9345e000f --- /dev/null +++ b/soc/atmel/sam0/samc20/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMC20 MCU series + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMC20 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samc20/Kconfig.defconfig b/soc/atmel/sam0/samc20/Kconfig.defconfig new file mode 100644 index 00000000000..ed71a4412be --- /dev/null +++ b/soc/atmel/sam0/samc20/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMC20 MCU series configuration options + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMC20 + +config NUM_IRQS + default 32 + +endif # SOC_SERIES_SAMC20 diff --git a/soc/atmel/sam0/samc20/Kconfig.soc b/soc/atmel/sam0/samc20/Kconfig.soc new file mode 100644 index 00000000000..b64c915745d --- /dev/null +++ b/soc/atmel/sam0/samc20/Kconfig.soc @@ -0,0 +1,98 @@ +# Atmel SAMC20 MCU series + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMC20 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMC20 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samc20" if SOC_SERIES_SAMC20 + +config SOC_SAMC20E15A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20E16A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20E17A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20E18A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20G15A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20G16A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20G17A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20G18A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J15A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J16A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J17A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J18A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J17AU + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J18AU + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20N17A + bool + select SOC_SERIES_SAMC20 + select SOC_SERIES_REVISION_N + +config SOC_SAMC20N18A + bool + select SOC_SERIES_SAMC20 + select SOC_SERIES_REVISION_N + +config SOC + default "samc20e15a" if SOC_SAMC20E15A + default "samc20e16a" if SOC_SAMC20E16A + default "samc20e17a" if SOC_SAMC20E17A + default "samc20e18a" if SOC_SAMC20E18A + default "samc20g15a" if SOC_SAMC20G15A + default "samc20g16a" if SOC_SAMC20G16A + default "samc20g17a" if SOC_SAMC20G17A + default "samc20g18a" if SOC_SAMC20G18A + default "samc20j15a" if SOC_SAMC20J15A + default "samc20j16a" if SOC_SAMC20J16A + default "samc20j17a" if SOC_SAMC20J17A + default "samc20j18a" if SOC_SAMC20J18A + default "samc20j17au" if SOC_SAMC20J17AU + default "samc20j18au" if SOC_SAMC20J18AU + default "samc20n17a" if SOC_SAMC20N17A + default "samc20n18a" if SOC_SAMC20N18A diff --git a/soc/atmel/sam0/samc20/soc.h b/soc/atmel/sam0/samc20/soc.h new file mode 100644 index 00000000000..fbf967444f9 --- /dev/null +++ b/soc/atmel/sam0/samc20/soc.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMC20_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMC20_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMC20E15A) +#include +#elif defined(CONFIG_SOC_SAMC20E16A) +#include +#elif defined(CONFIG_SOC_SAMC20E17A) +#include +#elif defined(CONFIG_SOC_SAMC20E18A) +#include +#elif defined(CONFIG_SOC_SAMC20G15A) +#include +#elif defined(CONFIG_SOC_SAMC20G16A) +#include +#elif defined(CONFIG_SOC_SAMC20G17A) +#include +#elif defined(CONFIG_SOC_SAMC20G18A) +#include +#elif defined(CONFIG_SOC_SAMC20J15A) +#include +#elif defined(CONFIG_SOC_SAMC20J16A) +#include +#elif defined(CONFIG_SOC_SAMC20J17A) +#include +#elif defined(CONFIG_SOC_SAMC20J18A) +#include +#elif defined(CONFIG_SOC_SAMC20J17AU) +#include +#elif defined(CONFIG_SOC_SAMC20J18AU) +#include +#elif defined(CONFIG_SOC_SAMC20N17A) +#include +#elif defined(CONFIG_SOC_SAMC20N18A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC48M_FREQ_HZ 48000000 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMC20_SOC_H_ */ diff --git a/soc/atmel/sam0/samc21/CMakeLists.txt b/soc/atmel/sam0/samc21/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/samc21/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samc21/Kconfig b/soc/atmel/sam0/samc21/Kconfig new file mode 100644 index 00000000000..51637a0b4ba --- /dev/null +++ b/soc/atmel/sam0/samc21/Kconfig @@ -0,0 +1,13 @@ +# Atmel SAMC21 MCU series + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMC21 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samc21/Kconfig.defconfig b/soc/atmel/sam0/samc21/Kconfig.defconfig new file mode 100644 index 00000000000..cafc565f48e --- /dev/null +++ b/soc/atmel/sam0/samc21/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMC21 MCU series configuration options + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMC21 + +config NUM_IRQS + default 32 + +endif # SOC_SERIES_SAMC21 diff --git a/soc/atmel/sam0/samc21/Kconfig.soc b/soc/atmel/sam0/samc21/Kconfig.soc new file mode 100644 index 00000000000..4ccf0e6bdde --- /dev/null +++ b/soc/atmel/sam0/samc21/Kconfig.soc @@ -0,0 +1,98 @@ +# Atmel SAMC21 MCU series + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMC21 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMC21 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samc21" if SOC_SERIES_SAMC21 + +config SOC_SAMC21E15A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21E16A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21E17A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21E18A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21G15A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21G16A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21G17A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21G18A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J15A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J16A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J17A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J18A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J17AU + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J18AU + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21N17A + bool + select SOC_SERIES_SAMC21 + select SOC_SERIES_REVISION_N + +config SOC_SAMC21N18A + bool + select SOC_SERIES_SAMC21 + select SOC_SERIES_REVISION_N + +config SOC + default "samc21e15a" if SOC_SAMC21E15A + default "samc21e16a" if SOC_SAMC21E16A + default "samc21e17a" if SOC_SAMC21E17A + default "samc21e18a" if SOC_SAMC21E18A + default "samc21g15a" if SOC_SAMC21G15A + default "samc21g16a" if SOC_SAMC21G16A + default "samc21g17a" if SOC_SAMC21G17A + default "samc21g18a" if SOC_SAMC21G18A + default "samc21j15a" if SOC_SAMC21J15A + default "samc21j16a" if SOC_SAMC21J16A + default "samc21j17a" if SOC_SAMC21J17A + default "samc21j18a" if SOC_SAMC21J18A + default "samc21j17au" if SOC_SAMC21J17AU + default "samc21j18au" if SOC_SAMC21J18AU + default "samc21n17a" if SOC_SAMC21N17A + default "samc21n18a" if SOC_SAMC21N18A diff --git a/soc/atmel/sam0/samc21/soc.h b/soc/atmel/sam0/samc21/soc.h new file mode 100644 index 00000000000..ad29ad71383 --- /dev/null +++ b/soc/atmel/sam0/samc21/soc.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMC21_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMC21_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMC21E15A) +#include +#elif defined(CONFIG_SOC_SAMC21E16A) +#include +#elif defined(CONFIG_SOC_SAMC21E17A) +#include +#elif defined(CONFIG_SOC_SAMC21E18A) +#include +#elif defined(CONFIG_SOC_SAMC21G15A) +#include +#elif defined(CONFIG_SOC_SAMC21G16A) +#include +#elif defined(CONFIG_SOC_SAMC21G17A) +#include +#elif defined(CONFIG_SOC_SAMC21G18A) +#include +#elif defined(CONFIG_SOC_SAMC21J15A) +#include +#elif defined(CONFIG_SOC_SAMC21J16A) +#include +#elif defined(CONFIG_SOC_SAMC21J17A) +#include +#elif defined(CONFIG_SOC_SAMC21J18A) +#include +#elif defined(CONFIG_SOC_SAMC21J17AU) +#include +#elif defined(CONFIG_SOC_SAMC21J18AU) +#include +#elif defined(CONFIG_SOC_SAMC21N17A) +#include +#elif defined(CONFIG_SOC_SAMC21N18A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC48M_FREQ_HZ 48000000 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMC21_SOC_H_ */ diff --git a/soc/atmel/sam0/samd20/CMakeLists.txt b/soc/atmel/sam0/samd20/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/samd20/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samd20/Kconfig b/soc/atmel/sam0/samd20/Kconfig new file mode 100644 index 00000000000..1fea4396b5f --- /dev/null +++ b/soc/atmel/sam0/samd20/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMD20 MCU series + +# Copyright (c) 2018 Sean Nyekjaer +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD20 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samd20/Kconfig.defconfig b/soc/atmel/sam0/samd20/Kconfig.defconfig new file mode 100644 index 00000000000..26e007d98b9 --- /dev/null +++ b/soc/atmel/sam0/samd20/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMD20 MCU series configuration options + +# Copyright (c) 2018 Sean Nyekjaer +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMD20 + +config NUM_IRQS + default 25 + +endif # SOC_SERIES_SAMD20 diff --git a/soc/atmel/sam0/samd20/Kconfig.soc b/soc/atmel/sam0/samd20/Kconfig.soc new file mode 100644 index 00000000000..0c629653f0b --- /dev/null +++ b/soc/atmel/sam0/samd20/Kconfig.soc @@ -0,0 +1,100 @@ +# Atmel SAMD20 MCU series + +# Copyright (c) 2018 Sean Nyekjaer +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD20 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMD20 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samd20" if SOC_SERIES_SAMD20 + +config SOC_SAMD20E14 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20E15 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20E16 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20E17 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20E18 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G14 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G15 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G16 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G17 + bool + +config SOC_SAMD20G18 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G17U + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G18U + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20J14 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20J15 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20J16 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20J17 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20J18 + bool + select SOC_SERIES_SAMD20 + +config SOC + default "samd20e14" if SOC_SAMD20E14 + default "samd20e15" if SOC_SAMD20E15 + default "samd20e16" if SOC_SAMD20E16 + default "samd20e17" if SOC_SAMD20E17 + default "samd20e18" if SOC_SAMD20E18 + default "samd20g14" if SOC_SAMD20G14 + default "samd20g15" if SOC_SAMD20G15 + default "samd20g16" if SOC_SAMD20G16 + default "samd20g17" if SOC_SAMD20G17 + default "samd20g18" if SOC_SAMD20G18 + default "samd20g17u" if SOC_SAMD20G17U + default "samd20g18u" if SOC_SAMD20G18U + default "samd20j14" if SOC_SAMD20J14 + default "samd20j15" if SOC_SAMD20J15 + default "samd20j16" if SOC_SAMD20J16 + default "samd20j17" if SOC_SAMD20J17 + default "samd20j18" if SOC_SAMD20J18 diff --git a/soc/atmel/sam0/samd20/soc.h b/soc/atmel/sam0/samd20/soc.h new file mode 100644 index 00000000000..9fed14706f8 --- /dev/null +++ b/soc/atmel/sam0/samd20/soc.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2018 Sean Nyekjaer + * Copyright (c) 2023 Ionut Catalin Pavel + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMD20_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMD20_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMD20E14) +#include +#elif defined(CONFIG_SOC_SAMD20E15) +#include +#elif defined(CONFIG_SOC_SAMD20E16) +#include +#elif defined(CONFIG_SOC_SAMD20E17) +#include +#elif defined(CONFIG_SOC_SAMD20E18) +#include +#elif defined(CONFIG_SOC_SAMD20G14) +#include +#elif defined(CONFIG_SOC_SAMD20G15) +#include +#elif defined(CONFIG_SOC_SAMD20G16) +#include +#elif defined(CONFIG_SOC_SAMD20G17) +#include +#elif defined(CONFIG_SOC_SAMD20G18) +#include +#elif defined(CONFIG_SOC_SAMD20G17U) +#include +#elif defined(CONFIG_SOC_SAMD20G18U) +#include +#elif defined(CONFIG_SOC_SAMD20J14) +#include +#elif defined(CONFIG_SOC_SAMD20J15) +#include +#elif defined(CONFIG_SOC_SAMD20J16) +#include +#elif defined(CONFIG_SOC_SAMD20J17) +#include +#elif defined(CONFIG_SOC_SAMD20J18) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ + +/** Known values */ +#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 +#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 + +/** GCLK1 source frequency selector */ +#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +/** Dividers and frequency for GCLK0 */ +#define SOC_ATMEL_SAM0_GCLK0_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +/** DFLL48M output frequency */ +#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ + (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) + +/** Dividers and frequency for GCLK1 */ +#define SOC_ATMEL_SAM0_GCLK1_DIV \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) + +/** DFLL48M output multiplier */ +#define SOC_ATMEL_SAM0_DFLL48M_MUL \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) + +/** Frequency for GCLK2 */ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ + +/** Dividers and frequency for GCLK3 */ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMD20_SOC_H_ */ diff --git a/soc/atmel/sam0/samd21/CMakeLists.txt b/soc/atmel/sam0/samd21/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/samd21/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samd21/Kconfig b/soc/atmel/sam0/samd21/Kconfig new file mode 100644 index 00000000000..f968f52246a --- /dev/null +++ b/soc/atmel/sam0/samd21/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMD21 MCU series + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD21 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samd21/Kconfig.defconfig b/soc/atmel/sam0/samd21/Kconfig.defconfig new file mode 100644 index 00000000000..f077951fdcb --- /dev/null +++ b/soc/atmel/sam0/samd21/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMD21 MCU series configuration options + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMD21 + +config NUM_IRQS + default 28 + +endif # SOC_SERIES_SAMD21 diff --git a/soc/atmel/sam0/samd21/Kconfig.soc b/soc/atmel/sam0/samd21/Kconfig.soc new file mode 100644 index 00000000000..70d3df11ad3 --- /dev/null +++ b/soc/atmel/sam0/samd21/Kconfig.soc @@ -0,0 +1,90 @@ +# Atmel SAMD21 MCU series + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD21 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMD21 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samd21" if SOC_SERIES_SAMD21 + +config SOC_SAMD21E15A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21E16A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21E17A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21E18A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21E19A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G15A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G16A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G17A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G18A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G17AU + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G18AU + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21J15A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21J16A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21J17A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21J18A + bool + select SOC_SERIES_SAMD21 + +config SOC + default "samd21e15a" if SOC_SAMD21E15A + default "samd21e16a" if SOC_SAMD21E16A + default "samd21e17a" if SOC_SAMD21E17A + default "samd21e18a" if SOC_SAMD21E18A + default "samd21g15a" if SOC_SAMD21G15A + default "samd21g16a" if SOC_SAMD21G16A + default "samd21g17a" if SOC_SAMD21G17A + default "samd21g18a" if SOC_SAMD21G18A + default "samd21g17au" if SOC_SAMD21G17AU + default "samd21g18au" if SOC_SAMD21G18AU + default "samd21j15a" if SOC_SAMD21J15A + default "samd21j16a" if SOC_SAMD21J16A + default "samd21j17a" if SOC_SAMD21J17A + default "samd21j18a" if SOC_SAMD21J18A diff --git a/soc/atmel/sam0/samd21/soc.h b/soc/atmel/sam0/samd21/soc.h new file mode 100644 index 00000000000..db93c5a954d --- /dev/null +++ b/soc/atmel/sam0/samd21/soc.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2017 Google LLC. + * Copyright (c) 2023 Ionut Catalin Pavel + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMD21_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMD21_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMD21E15A) +#include +#elif defined(CONFIG_SOC_SAMD21E16A) +#include +#elif defined(CONFIG_SOC_SAMD21E17A) +#include +#elif defined(CONFIG_SOC_SAMD21E18A) +#include +#elif defined(CONFIG_SOC_SAMD21G15A) +#include +#elif defined(CONFIG_SOC_SAMD21G16A) +#include +#elif defined(CONFIG_SOC_SAMD21G17A) +#include +#elif defined(CONFIG_SOC_SAMD21G18A) +#include +#elif defined(CONFIG_SOC_SAMD21G17AU) +#include +#elif defined(CONFIG_SOC_SAMD21G18AU) +#include +#elif defined(CONFIG_SOC_SAMD21J15A) +#include +#elif defined(CONFIG_SOC_SAMD21J16A) +#include +#elif defined(CONFIG_SOC_SAMD21J17A) +#include +#elif defined(CONFIG_SOC_SAMD21J18A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ + +/** Known values */ +#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 +#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 + +/** GCLK1 source frequency selector */ +#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +/** Dividers and frequency for GCLK0 */ +#define SOC_ATMEL_SAM0_GCLK0_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +/** DFLL48M output frequency */ +#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ + (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) + +/** Dividers and frequency for GCLK1 */ +#define SOC_ATMEL_SAM0_GCLK1_DIV \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) + +/** DFLL48M output multiplier */ +#define SOC_ATMEL_SAM0_DFLL48M_MUL \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) + +/** Frequency for GCLK2 */ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ + +/** Dividers and frequency for GCLK3 */ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMD21_SOC_H_ */ diff --git a/soc/atmel/sam0/samd51/CMakeLists.txt b/soc/atmel/sam0/samd51/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/samd51/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samd51/Kconfig b/soc/atmel/sam0/samd51/Kconfig new file mode 100644 index 00000000000..fb846ef9c64 --- /dev/null +++ b/soc/atmel/sam0/samd51/Kconfig @@ -0,0 +1,13 @@ +# Atmel SAMD51 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD51 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samd51/Kconfig.defconfig b/soc/atmel/sam0/samd51/Kconfig.defconfig new file mode 100644 index 00000000000..c37eb407f4d --- /dev/null +++ b/soc/atmel/sam0/samd51/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Atmel SAMD51 MCU series configuration options + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMD51 + +config NUM_IRQS + int + default 137 + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_SAMD51 diff --git a/soc/atmel/sam0/samd51/Kconfig.soc b/soc/atmel/sam0/samd51/Kconfig.soc new file mode 100644 index 00000000000..efb67a92851 --- /dev/null +++ b/soc/atmel/sam0/samd51/Kconfig.soc @@ -0,0 +1,62 @@ +# Atmel SAMD51 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD51 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMD51 Cortex-M4F microcontrollers. + +config SOC_SERIES + default "samd51" if SOC_SERIES_SAMD51 + +config SOC_SAMD51G18A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51G19A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51J18A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51J19A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51J20A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51N19A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51N20A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51P19A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51P20A + bool + select SOC_SERIES_SAMD51 + +config SOC + string + default "samd51g18a" if SOC_SAMD51G18A + default "samd51g19a" if SOC_SAMD51G19A + default "samd51j18a" if SOC_SAMD51J18A + default "samd51j19a" if SOC_SAMD51J19A + default "samd51j20a" if SOC_SAMD51J20A + default "samd51n19a" if SOC_SAMD51N19A + default "samd51n20a" if SOC_SAMD51N20A + default "samd51p19a" if SOC_SAMD51P19A + default "samd51p20a" if SOC_SAMD51P20A diff --git a/soc/atmel/sam0/samd51/soc.h b/soc/atmel/sam0/samd51/soc.h new file mode 100644 index 00000000000..1ca64486f44 --- /dev/null +++ b/soc/atmel/sam0/samd51/soc.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2019 ML!PA Consulting GmbH + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMD51_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMD51_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMD51G18A) +#include +#elif defined(CONFIG_SOC_SAMD51G19A) +#include +#elif defined(CONFIG_SOC_SAMD51J18A) +#include +#elif defined(CONFIG_SOC_SAMD51J19A) +#include +#elif defined(CONFIG_SOC_SAMD51J20A) +#include +#elif defined(CONFIG_SOC_SAMD51N19A) +#include +#elif defined(CONFIG_SOC_SAMD51N20A) +#include +#elif defined(CONFIG_SOC_SAMD51P19A) +#include +#elif defined(CONFIG_SOC_SAMD51P20A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "sercom_fixup_samd5x.h" +#include "tc_fixup_samd5x.h" +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 + +#endif /* _SOC_ATMEL_SAM0_SAMD51_SOC_H_ */ diff --git a/soc/atmel/sam0/same51/CMakeLists.txt b/soc/atmel/sam0/same51/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/same51/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/same51/Kconfig b/soc/atmel/sam0/same51/Kconfig new file mode 100644 index 00000000000..35aa9996a7b --- /dev/null +++ b/soc/atmel/sam0/same51/Kconfig @@ -0,0 +1,13 @@ +# Atmel SAME51 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME51 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/same51/Kconfig.defconfig b/soc/atmel/sam0/same51/Kconfig.defconfig new file mode 100644 index 00000000000..302b528ab4f --- /dev/null +++ b/soc/atmel/sam0/same51/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Atmel SAME51 MCU series configuration options + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAME51 + +config NUM_IRQS + default 137 + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_SAME51 diff --git a/soc/atmel/sam0/same51/Kconfig.soc b/soc/atmel/sam0/same51/Kconfig.soc new file mode 100644 index 00000000000..4d858515f36 --- /dev/null +++ b/soc/atmel/sam0/same51/Kconfig.soc @@ -0,0 +1,41 @@ +# Atmel SAME51 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME51 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAME51 Cortex-M4F microcontrollers. + +config SOC_SERIES + default "same51" if SOC_SERIES_SAME51 + +config SOC_SAME51J18A + bool + select SOC_SERIES_SAME51 + +config SOC_SAME51J19A + bool + select SOC_SERIES_SAME51 + +config SOC_SAME51J20A + bool + select SOC_SERIES_SAME51 + +config SOC_SAME51N19A + bool + select SOC_SERIES_SAME51 + +config SOC_SAME51N20A + bool + select SOC_SERIES_SAME51 + +config SOC + default "same51j18a" if SOC_SAME51J18A + default "same51j19a" if SOC_SAME51J19A + default "same51j20a" if SOC_SAME51J20A + default "same51n19a" if SOC_SAME51N19A + default "same51n20a" if SOC_SAME51N20A diff --git a/soc/atmel/sam0/same51/soc.h b/soc/atmel/sam0/same51/soc.h new file mode 100644 index 00000000000..8c55ceda812 --- /dev/null +++ b/soc/atmel/sam0/same51/soc.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2019 ML!PA Consulting GmbH + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAME51_SOC_H_ +#define _SOC_ATMEL_SAM0_SAME51_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + + +#if defined(CONFIG_SOC_SAME51J18A) +#include +#elif defined(CONFIG_SOC_SAME51J19A) +#include +#elif defined(CONFIG_SOC_SAME51J20A) +#include +#elif defined(CONFIG_SOC_SAME51N19A) +#include +#elif defined(CONFIG_SOC_SAME51N20A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "sercom_fixup_samd5x.h" +#include "tc_fixup_samd5x.h" +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_DFLL48_FREQ_HZ 48000000 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 + +#endif /* _SOC_ATMEL_SAM0_SAME51_SOC_H_ */ diff --git a/soc/atmel/sam0/same53/CMakeLists.txt b/soc/atmel/sam0/same53/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/same53/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/same53/Kconfig b/soc/atmel/sam0/same53/Kconfig new file mode 100644 index 00000000000..670f155e926 --- /dev/null +++ b/soc/atmel/sam0/same53/Kconfig @@ -0,0 +1,13 @@ +# Atmel SAME53 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME53 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/same53/Kconfig.defconfig b/soc/atmel/sam0/same53/Kconfig.defconfig new file mode 100644 index 00000000000..80f00943b5b --- /dev/null +++ b/soc/atmel/sam0/same53/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Atmel SAME53 MCU series configuration options + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAME53 + +config NUM_IRQS + default 137 + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_SAME53 diff --git a/soc/atmel/sam0/same53/Kconfig.soc b/soc/atmel/sam0/same53/Kconfig.soc new file mode 100644 index 00000000000..f52e7ced3ae --- /dev/null +++ b/soc/atmel/sam0/same53/Kconfig.soc @@ -0,0 +1,41 @@ +# Atmel SAME53 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME53 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAME53 Cortex-M4F microcontrollers. + +config SOC_SERIES + default "same53" if SOC_SERIES_SAME53 + +config SOC_SAME53J18A + bool + select SOC_SERIES_SAME53 + +config SOC_SAME53J19A + bool + select SOC_SERIES_SAME53 + +config SOC_SAME53J20A + bool + select SOC_SERIES_SAME53 + +config SOC_SAME53N19A + bool + select SOC_SERIES_SAME53 + +config SOC_SAME53N20A + bool + select SOC_SERIES_SAME53 + +config SOC + default "same53j18a" if SOC_SAME53J18A + default "same53j19a" if SOC_SAME53J19A + default "same53j20a" if SOC_SAME53J20A + default "same53n19a" if SOC_SAME53N19A + default "same53n20a" if SOC_SAME53N20A diff --git a/soc/atmel/sam0/same53/soc.h b/soc/atmel/sam0/same53/soc.h new file mode 100644 index 00000000000..de08740a9a0 --- /dev/null +++ b/soc/atmel/sam0/same53/soc.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2019 ML!PA Consulting GmbH + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAME53_SOC_H_ +#define _SOC_ATMEL_SAM0_SAME53_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAME53J18A) +#include +#elif defined(CONFIG_SOC_SAME53J19A) +#include +#elif defined(CONFIG_SOC_SAME53J20A) +#include +#elif defined(CONFIG_SOC_SAME53N19A) +#include +#elif defined(CONFIG_SOC_SAME53N20A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "sercom_fixup_samd5x.h" +#include "tc_fixup_samd5x.h" +#include "gmac_fixup_samd5x.h" +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 + +#endif /* _SOC_ATMEL_SAM0_SAME53_SOC_H_ */ diff --git a/soc/atmel/sam0/same54/CMakeLists.txt b/soc/atmel/sam0/same54/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/same54/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/same54/Kconfig b/soc/atmel/sam0/same54/Kconfig new file mode 100644 index 00000000000..2bd2359eb2e --- /dev/null +++ b/soc/atmel/sam0/same54/Kconfig @@ -0,0 +1,13 @@ +# Atmel SAME54 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME54 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/same54/Kconfig.defconfig b/soc/atmel/sam0/same54/Kconfig.defconfig new file mode 100644 index 00000000000..53555ebce1d --- /dev/null +++ b/soc/atmel/sam0/same54/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Atmel SAME54 MCU series configuration options + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAME54 + +config NUM_IRQS + default 137 + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_SAME54 diff --git a/soc/atmel/sam0/same54/Kconfig.soc b/soc/atmel/sam0/same54/Kconfig.soc new file mode 100644 index 00000000000..1c7621764fa --- /dev/null +++ b/soc/atmel/sam0/same54/Kconfig.soc @@ -0,0 +1,36 @@ +# Atmel SAME54 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME54 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAME54 Cortex-M4F microcontrollers. + +config SOC_SERIES + default "same54" if SOC_SERIES_SAME54 + +config SOC_SAME54N19A + bool + select SOC_SERIES_SAME54 + +config SOC_SAME54N20A + bool + select SOC_SERIES_SAME54 + +config SOC_SAME54P19A + bool + select SOC_SERIES_SAME54 + +config SOC_SAME54P20A + bool + select SOC_SERIES_SAME54 + +config SOC + default "same54n19a" if SOC_SAME54N19A + default "same54n20a" if SOC_SAME54N20A + default "same54p19a" if SOC_SAME54P19A + default "same54p20a" if SOC_SAME54P20A diff --git a/soc/atmel/sam0/same54/soc.h b/soc/atmel/sam0/same54/soc.h new file mode 100644 index 00000000000..b47f5278c09 --- /dev/null +++ b/soc/atmel/sam0/same54/soc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2019 ML!PA Consulting GmbH + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAME54_SOC_H_ +#define _SOC_ATMEL_SAM0_SAME54_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAME54N19A) +#include +#elif defined(CONFIG_SOC_SAME54N20A) +#include +#elif defined(CONFIG_SOC_SAME54P19A) +#include +#elif defined(CONFIG_SOC_SAME54P20A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "sercom_fixup_samd5x.h" +#include "tc_fixup_samd5x.h" +#include "gmac_fixup_samd5x.h" +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_DFLL48_FREQ_HZ 48000000 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 + +#endif /* _SOC_ATMEL_SAM0_SAME54_SOC_H_ */ diff --git a/soc/atmel/sam0/saml21/CMakeLists.txt b/soc/atmel/sam0/saml21/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/saml21/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/saml21/Kconfig b/soc/atmel/sam0/saml21/Kconfig new file mode 100644 index 00000000000..1fbc5336a57 --- /dev/null +++ b/soc/atmel/sam0/saml21/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAML21 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAML21 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/saml21/Kconfig.defconfig b/soc/atmel/sam0/saml21/Kconfig.defconfig new file mode 100644 index 00000000000..19ecbdf5cad --- /dev/null +++ b/soc/atmel/sam0/saml21/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAML21 MCU series configuration options + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAML21 + +config NUM_IRQS + default 29 + +endif # SOC_SERIES_SAML21 diff --git a/soc/atmel/sam0/saml21/Kconfig.soc b/soc/atmel/sam0/saml21/Kconfig.soc new file mode 100644 index 00000000000..c833a172766 --- /dev/null +++ b/soc/atmel/sam0/saml21/Kconfig.soc @@ -0,0 +1,76 @@ +# Atmel SAML21 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAML21 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAML21 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "saml21" if SOC_SERIES_SAML21 + +config SOC_SAML21E15B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21E16B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21E17B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21E18B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21G16B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21G17B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21G18B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21J16B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21J17B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21J18B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21J17BU + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21J18BU + bool + select SOC_SERIES_SAML21 + +config SOC + default "saml21e15b" if SOC_SAML21E15B + default "saml21e16b" if SOC_SAML21E16B + default "saml21e17b" if SOC_SAML21E17B + default "saml21e18b" if SOC_SAML21E18B + default "saml21g16b" if SOC_SAML21G16B + default "saml21g17b" if SOC_SAML21G17B + default "saml21g18b" if SOC_SAML21G18B + default "saml21j16b" if SOC_SAML21J16B + default "saml21j17b" if SOC_SAML21J17B + default "saml21j18b" if SOC_SAML21J18B + default "saml21j17bu" if SOC_SAML21J17BU + default "saml21j18bu" if SOC_SAML21J18BU diff --git a/soc/atmel/sam0/saml21/soc.h b/soc/atmel/sam0/saml21/soc.h new file mode 100644 index 00000000000..40c9444d96c --- /dev/null +++ b/soc/atmel/sam0/saml21/soc.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAML21_SOC_H_ +#define _SOC_ATMEL_SAM0_SAML21_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#if defined(CONFIG_SOC_SAML21E15B) +#include +#elif defined(CONFIG_SOC_SAML21E16B) +#include +#elif defined(CONFIG_SOC_SAML21E17B) +#include +#elif defined(CONFIG_SOC_SAML21E18B) +#include +#elif defined(CONFIG_SOC_SAML21G16B) +#include +#elif defined(CONFIG_SOC_SAML21G17B) +#include +#elif defined(CONFIG_SOC_SAML21G18B) +#include +#elif defined(CONFIG_SOC_SAML21J16B) +#include +#elif defined(CONFIG_SOC_SAML21J17B) +#include +#elif defined(CONFIG_SOC_SAML21J18B) +#include +#elif defined(CONFIG_SOC_SAML21J17BU) +#include +#elif defined(CONFIG_SOC_SAML21J18BU) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 + +#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAML21_SOC_H_ */ diff --git a/soc/atmel/sam0/samr21/CMakeLists.txt b/soc/atmel/sam0/samr21/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/samr21/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samr21/Kconfig b/soc/atmel/sam0/samr21/Kconfig new file mode 100644 index 00000000000..823be5d13ea --- /dev/null +++ b/soc/atmel/sam0/samr21/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMR21 MCU series + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR21 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samr21/Kconfig.defconfig b/soc/atmel/sam0/samr21/Kconfig.defconfig new file mode 100644 index 00000000000..cc93f0a3818 --- /dev/null +++ b/soc/atmel/sam0/samr21/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMR21 MCU series configuration options + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMR21 + +config NUM_IRQS + default 28 + +endif # SOC_SERIES_SAMR21 diff --git a/soc/atmel/sam0/samr21/Kconfig.soc b/soc/atmel/sam0/samr21/Kconfig.soc new file mode 100644 index 00000000000..e0e08cb05a0 --- /dev/null +++ b/soc/atmel/sam0/samr21/Kconfig.soc @@ -0,0 +1,51 @@ +# Atmel SAMR21 MCU series + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR21 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMR21 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samr21" if SOC_SERIES_SAMR21 + +config SOC_SAMR21E16A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21E17A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21E18A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21E19A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21G16A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21G17A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21G18A + bool + select SOC_SERIES_SAMR21 + +config SOC + default "samr21e16a" if SOC_SAMR21E16A + default "samr21e17a" if SOC_SAMR21E17A + default "samr21e18a" if SOC_SAMR21E18A + default "samr21e19a" if SOC_SAMR21E19A + default "samr21g16a" if SOC_SAMR21G16A + default "samr21g17a" if SOC_SAMR21G17A + default "samr21g18a" if SOC_SAMR21G18A diff --git a/soc/atmel/sam0/samr21/soc.h b/soc/atmel/sam0/samr21/soc.h new file mode 100644 index 00000000000..c3dad347372 --- /dev/null +++ b/soc/atmel/sam0/samr21/soc.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2017 Google LLC. + * Copyright (c) 2023 Ionut Catalin Pavel + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMR21_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMR21_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMR21E16A) +#include +#elif defined(CONFIG_SOC_SAMR21E17A) +#include +#elif defined(CONFIG_SOC_SAMR21E18A) +#include +#elif defined(CONFIG_SOC_SAMR21E19A) +#include +#elif defined(CONFIG_SOC_SAMR21G16A) +#include +#elif defined(CONFIG_SOC_SAMR21G17A) +#include +#elif defined(CONFIG_SOC_SAMR21G18A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ + +/** Known values */ +#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 +#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 + +/** GCLK1 source frequency selector */ +#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +/** Dividers and frequency for GCLK0 */ +#define SOC_ATMEL_SAM0_GCLK0_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +/** DFLL48M output frequency */ +#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ + (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) + +/** Dividers and frequency for GCLK1 */ +#define SOC_ATMEL_SAM0_GCLK1_DIV \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) + +/** DFLL48M output multiplier */ +#define SOC_ATMEL_SAM0_DFLL48M_MUL \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) + +/** Frequency for GCLK2 */ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ + +/** Dividers and frequency for GCLK3 */ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMR21_SOC_H_ */ diff --git a/soc/atmel/sam0/samr34/CMakeLists.txt b/soc/atmel/sam0/samr34/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/samr34/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samr34/Kconfig b/soc/atmel/sam0/samr34/Kconfig new file mode 100644 index 00000000000..05675901e4f --- /dev/null +++ b/soc/atmel/sam0/samr34/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMR34 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR34 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samr34/Kconfig.defconfig b/soc/atmel/sam0/samr34/Kconfig.defconfig new file mode 100644 index 00000000000..b7ea78a2c2e --- /dev/null +++ b/soc/atmel/sam0/samr34/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAML MCU series configuration options + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMR34 + +config NUM_IRQS + default 23 + +endif # SOC_SERIES_SAMR34 diff --git a/soc/atmel/sam0/samr34/Kconfig.soc b/soc/atmel/sam0/samr34/Kconfig.soc new file mode 100644 index 00000000000..23ddaa16b67 --- /dev/null +++ b/soc/atmel/sam0/samr34/Kconfig.soc @@ -0,0 +1,31 @@ +# Atmel SAMR34 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR34 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMR34 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samr34" if SOC_SERIES_SAMR34 + +config SOC_SAMR34J16B + bool + select SOC_SERIES_SAMR34 + +config SOC_SAMR34J17B + bool + select SOC_SERIES_SAMR34 + +config SOC_SAMR34J18B + bool + select SOC_SERIES_SAMR34 + +config SOC + default "samr34j16b" if SOC_SAMR34J16B + default "samr34j17b" if SOC_SAMR34J17B + default "samr34j18b" if SOC_SAMR34J18B diff --git a/soc/atmel/sam0/samr34/soc.h b/soc/atmel/sam0/samr34/soc.h new file mode 100644 index 00000000000..06699440d74 --- /dev/null +++ b/soc/atmel/sam0/samr34/soc.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMR34_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMR34_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMR34J16B) +#include +#elif defined(CONFIG_SOC_SAMR34J17B) +#include +#elif defined(CONFIG_SOC_SAMR34J18B) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 + +#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMR34_SOC_H_ */ diff --git a/soc/atmel/sam0/samr35/CMakeLists.txt b/soc/atmel/sam0/samr35/CMakeLists.txt new file mode 100644 index 00000000000..c7c4bb53ac1 --- /dev/null +++ b/soc/atmel/sam0/samr35/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samr35/Kconfig b/soc/atmel/sam0/samr35/Kconfig new file mode 100644 index 00000000000..c5fa8e5d048 --- /dev/null +++ b/soc/atmel/sam0/samr35/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMR35 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR35 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samr35/Kconfig.defconfig b/soc/atmel/sam0/samr35/Kconfig.defconfig new file mode 100644 index 00000000000..26ac6d74ff4 --- /dev/null +++ b/soc/atmel/sam0/samr35/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMR35 MCU series configuration options + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMR35 + +config NUM_IRQS + default 23 + +endif # SOC_SERIES_SAMR35 diff --git a/soc/atmel/sam0/samr35/Kconfig.soc b/soc/atmel/sam0/samr35/Kconfig.soc new file mode 100644 index 00000000000..13042dfeda6 --- /dev/null +++ b/soc/atmel/sam0/samr35/Kconfig.soc @@ -0,0 +1,31 @@ +# Atmel SAMR35 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR35 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMR35 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samr35" if SOC_SERIES_SAMR35 + +config SOC_SAMR35J16B + bool + select SOC_SERIES_SAMR35 + +config SOC_SAMR35J17B + bool + select SOC_SERIES_SAMR35 + +config SOC_SAMR35J18B + bool + select SOC_SERIES_SAMR35 + +config SOC + default "samr35j16b" if SOC_SAMR35J16B + default "samr35j17b" if SOC_SAMR35J17B + default "samr35j18b" if SOC_SAMR35J18B diff --git a/soc/atmel/sam0/samr35/soc.h b/soc/atmel/sam0/samr35/soc.h new file mode 100644 index 00000000000..24d2a4d1591 --- /dev/null +++ b/soc/atmel/sam0/samr35/soc.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMR35_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMR35_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMR35J16B) +#include +#elif defined(CONFIG_SOC_SAMR35J17B) +#include +#elif defined(CONFIG_SOC_SAMR35J18B) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 + +#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMR35_SOC_H_ */ diff --git a/soc/atmel/sam0/soc.yml b/soc/atmel/sam0/soc.yml new file mode 100644 index 00000000000..d0cfa94f7ca --- /dev/null +++ b/soc/atmel/sam0/soc.yml @@ -0,0 +1,138 @@ +family: +- name: atmel_sam0 + series: + - name: samc20 + socs: + - name: samc20e15a + - name: samc20e16a + - name: samc20e17a + - name: samc20e18a + - name: samc20g15a + - name: samc20g16a + - name: samc20g17a + - name: samc20g18a + - name: samc20j15a + - name: samc20j16a + - name: samc20j17a + - name: samc20j18a + - name: samc20j17au + - name: samc20j18au + - name: samc20n17a + - name: samc20n18a + - name: samc21 + socs: + - name: samc21e15a + - name: samc21e16a + - name: samc21e17a + - name: samc21e18a + - name: samc21g15a + - name: samc21g16a + - name: samc21g17a + - name: samc21g18a + - name: samc21j15a + - name: samc21j16a + - name: samc21j17a + - name: samc21j18a + - name: samc21j17au + - name: samc21j18au + - name: samc21n17a + - name: samc21n18a + - name: samd20 + socs: + - name: samd20e14 + - name: samd20e15 + - name: samd20e16 + - name: samd20e17 + - name: samd20e18 + - name: samd20g14 + - name: samd20g15 + - name: samd20g16 + - name: samd20g17 + - name: samd20g18 + - name: samd20g17u + - name: samd20g18u + - name: samd20j14 + - name: samd20j15 + - name: samd20j16 + - name: samd20j17 + - name: samd20j18 + - name: samd21 + socs: + - name: samd21e15a + - name: samd21e16a + - name: samd21e17a + - name: samd21e18a + - name: samd21g15a + - name: samd21g16a + - name: samd21g17a + - name: samd21g18a + - name: samd21g17au + - name: samd21g18au + - name: samd21j15a + - name: samd21j16a + - name: samd21j17a + - name: samd21j18a + - name: samd51 + socs: + - name: samd51g18a + - name: samd51g19a + - name: samd51j18a + - name: samd51j19a + - name: samd51j20a + - name: samd51n19a + - name: samd51n20a + - name: samd51p19a + - name: samd51p20a + - name: same51 + socs: + - name: same51j18a + - name: same51j19a + - name: same51j20a + - name: same51n19a + - name: same51n20a + - name: same53 + socs: + - name: same53j18a + - name: same53j19a + - name: same53j20a + - name: same53n19a + - name: same53n20a + - name: same54 + socs: + - name: same54n19a + - name: same54n20a + - name: same54p19a + - name: same54p20a + - name: saml21 + socs: + - name: saml21e15b + - name: saml21e16b + - name: saml21e17b + - name: saml21e18b + - name: saml21g16b + - name: saml21g17b + - name: saml21g18b + - name: saml21j16b + - name: saml21j17b + - name: saml21j18b + - name: saml21j17bu + - name: saml21j18bu + - name: samr21 + socs: + - name: samr21e16a + - name: samr21e17a + - name: samr21e18a + - name: samr21e19a + - name: samr21g16a + - name: samr21g17a + - name: samr21g18a + - name: samr34 + socs: + - name: samr34j16b + - name: samr34j17b + - name: samr34j18b + - name: samr35 + socs: + - name: samr35j16b + - name: samr35j17b + - name: samr35j18b diff --git a/soc/arm64/bcm2711/CMakeLists.txt b/soc/brcm/bcm2711/CMakeLists.txt similarity index 100% rename from soc/arm64/bcm2711/CMakeLists.txt rename to soc/brcm/bcm2711/CMakeLists.txt diff --git a/soc/brcm/bcm2711/Kconfig b/soc/brcm/bcm2711/Kconfig new file mode 100644 index 00000000000..2cfb4b2e4e4 --- /dev/null +++ b/soc/brcm/bcm2711/Kconfig @@ -0,0 +1,7 @@ +# Copyright 2023 honglin leng +# SPDX-License-Identifier: Apache-2.0 + +config SOC_BCM2711 + select ARM64 + select CPU_CORTEX_A72 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS diff --git a/soc/brcm/bcm2711/Kconfig.defconfig b/soc/brcm/bcm2711/Kconfig.defconfig new file mode 100644 index 00000000000..21776e5ef16 --- /dev/null +++ b/soc/brcm/bcm2711/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Copyright 2023 honglin leng +# SPDX-License-Identifier: Apache-2.0 + +if SOC_BCM2711 + +config NUM_IRQS + int + default 260 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 54000000 + +endif diff --git a/soc/brcm/bcm2711/Kconfig.soc b/soc/brcm/bcm2711/Kconfig.soc new file mode 100644 index 00000000000..d3c79214257 --- /dev/null +++ b/soc/brcm/bcm2711/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright 2023 honglin leng +# SPDX-License-Identifier: Apache-2.0 + +config SOC_BCM2711 + bool + +config SOC + default "bcm2711" if SOC_BCM2711 diff --git a/soc/arm64/bcm2711/mmu_regions.c b/soc/brcm/bcm2711/mmu_regions.c similarity index 100% rename from soc/arm64/bcm2711/mmu_regions.c rename to soc/brcm/bcm2711/mmu_regions.c diff --git a/soc/brcm/bcm2711/soc.yml b/soc/brcm/bcm2711/soc.yml new file mode 100644 index 00000000000..ebe1b40e7a0 --- /dev/null +++ b/soc/brcm/bcm2711/soc.yml @@ -0,0 +1,4 @@ +series: +- name: bcm2711 + socs: + - name: bcm2711 diff --git a/soc/arm/arm/CMakeLists.txt b/soc/brcm/bcmvk/CMakeLists.txt similarity index 100% rename from soc/arm/arm/CMakeLists.txt rename to soc/brcm/bcmvk/CMakeLists.txt diff --git a/soc/brcm/bcmvk/Kconfig b/soc/brcm/bcmvk/Kconfig new file mode 100644 index 00000000000..c51095bb23f --- /dev/null +++ b/soc/brcm/bcmvk/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +if SOC_FAMILY_BCMVK + +rsource "*/Kconfig" + +endif diff --git a/soc/brcm/bcmvk/Kconfig.defconfig b/soc/brcm/bcmvk/Kconfig.defconfig new file mode 100644 index 00000000000..ddbe24a6428 --- /dev/null +++ b/soc/brcm/bcmvk/Kconfig.defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +if SOC_FAMILY_BCMVK + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_BCMVK diff --git a/soc/brcm/bcmvk/Kconfig.soc b/soc/brcm/bcmvk/Kconfig.soc new file mode 100644 index 00000000000..28e14f0e13d --- /dev/null +++ b/soc/brcm/bcmvk/Kconfig.soc @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +config SOC_FAMILY_BCMVK + bool + +config SOC_FAMILY + default "bcmvk" if SOC_FAMILY_BCMVK + +rsource "*/Kconfig.soc" diff --git a/soc/brcm/bcmvk/soc.yml b/soc/brcm/bcmvk/soc.yml new file mode 100644 index 00000000000..2b0b7d27a37 --- /dev/null +++ b/soc/brcm/bcmvk/soc.yml @@ -0,0 +1,12 @@ +family: + - name: bcmvk + series: + - name: valkyrie + socs: + - name: bcm58400 + - name: viper + socs: + - name: bcm58402 + cpuclusters: + - name: m7 + - name: a72 diff --git a/soc/brcm/bcmvk/valkyrie/CMakeLists.txt b/soc/brcm/bcmvk/valkyrie/CMakeLists.txt new file mode 100644 index 00000000000..f5ca7d6435e --- /dev/null +++ b/soc/brcm/bcmvk/valkyrie/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/brcm/bcmvk/valkyrie/Kconfig b/soc/brcm/bcmvk/valkyrie/Kconfig new file mode 100644 index 00000000000..9ce1feb9faa --- /dev/null +++ b/soc/brcm/bcmvk/valkyrie/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +config SOC_SERIES_VALKYRIE + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_HAS_ARM_MPU diff --git a/soc/brcm/bcmvk/valkyrie/Kconfig.defconfig b/soc/brcm/bcmvk/valkyrie/Kconfig.defconfig new file mode 100644 index 00000000000..5312999e214 --- /dev/null +++ b/soc/brcm/bcmvk/valkyrie/Kconfig.defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +if SOC_SERIES_VALKYRIE + +config NUM_IRQS + int + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 500000000 + +endif # SOC_SERIES_VALKYRIE diff --git a/soc/brcm/bcmvk/valkyrie/Kconfig.soc b/soc/brcm/bcmvk/valkyrie/Kconfig.soc new file mode 100644 index 00000000000..79bcd0e755c --- /dev/null +++ b/soc/brcm/bcmvk/valkyrie/Kconfig.soc @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +config SOC_SERIES_VALKYRIE + bool + select SOC_FAMILY_BCMVK + help + Enable support for Broadcom Valkyrie Series + +config SOC_BCM58400 + bool + select SOC_SERIES_VALKYRIE + help + Broadcom BCM58400 + +config SOC_SERIES + default "valkyrie" if SOC_SERIES_VALKYRIE + +config SOC + default "bcm58400" if SOC_BCM58400 diff --git a/soc/arm/bcm_vk/valkyrie/soc.h b/soc/brcm/bcmvk/valkyrie/soc.h similarity index 100% rename from soc/arm/bcm_vk/valkyrie/soc.h rename to soc/brcm/bcmvk/valkyrie/soc.h diff --git a/soc/brcm/bcmvk/viper/CMakeLists.txt b/soc/brcm/bcmvk/viper/CMakeLists.txt new file mode 100644 index 00000000000..1a24bb86500 --- /dev/null +++ b/soc/brcm/bcmvk/viper/CMakeLists.txt @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_BCM58402_A72) + zephyr_include_directories(a72) + + zephyr_sources( + a72/soc.c + a72/plat_core.c + ) + + zephyr_sources_ifdef(CONFIG_ARM_MMU a72/mmu_regions.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_BCM58402_M7) + zephyr_include_directories(m7) + zephyr_sources(m7/soc.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/brcm/bcmvk/viper/Kconfig b/soc/brcm/bcmvk/viper/Kconfig new file mode 100644 index 00000000000..e6266d10456 --- /dev/null +++ b/soc/brcm/bcmvk/viper/Kconfig @@ -0,0 +1,13 @@ +# Copyright 2020 Broadcom +# SPDX-License-Identifier: Apache-2.0 + +config SOC_BCM58402_M7 + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_HAS_ARM_MPU + +config SOC_BCM58402_A72 + select ARM64 + select CPU_CORTEX_A72 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS diff --git a/soc/brcm/bcmvk/viper/Kconfig.defconfig b/soc/brcm/bcmvk/viper/Kconfig.defconfig new file mode 100644 index 00000000000..a0354a2c591 --- /dev/null +++ b/soc/brcm/bcmvk/viper/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright 2020 Broadcom +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_VIPER + +rsource "Kconfig.defconfig.viper*" + +endif # SOC_SERIES_VIPER diff --git a/soc/arm64/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_a72 b/soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_a72 similarity index 83% rename from soc/arm64/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_a72 rename to soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_a72 index 495490a996b..dba58d12f85 100644 --- a/soc/arm64/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_a72 +++ b/soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_a72 @@ -3,9 +3,6 @@ if SOC_BCM58402_A72 -config SOC - default "bcm58402_a72" - config NUM_IRQS int default 260 diff --git a/soc/arm/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_m7 b/soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_m7 similarity index 84% rename from soc/arm/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_m7 rename to soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_m7 index 15345da6150..16acf0d29b7 100644 --- a/soc/arm/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_m7 +++ b/soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_m7 @@ -3,9 +3,6 @@ if SOC_BCM58402_M7 -config SOC - default "bcm58402_m7" - config NUM_IRQS int default 240 diff --git a/soc/brcm/bcmvk/viper/Kconfig.soc b/soc/brcm/bcmvk/viper/Kconfig.soc new file mode 100644 index 00000000000..18af3700460 --- /dev/null +++ b/soc/brcm/bcmvk/viper/Kconfig.soc @@ -0,0 +1,26 @@ +# Copyright 2020 Broadcom +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_VIPER + bool + select SOC_FAMILY_BCMVK + help + Enable support for Broadcom Viper Series. + +config SOC_BCM58402_M7 + bool + select SOC_SERIES_VIPER + help + Broadcom BCM58402 M7 + +config SOC_BCM58402_A72 + bool + select SOC_SERIES_VIPER + help + Broadcom BCM58402 A72 + +config SOC_SERIES + default "viper" if SOC_SERIES_VIPER + +config SOC + default "bcm58402" if SOC_BCM58402_M7 || SOC_BCM58402_A72 diff --git a/soc/arm64/bcm_vk/viper/mmu_regions.c b/soc/brcm/bcmvk/viper/a72/mmu_regions.c similarity index 100% rename from soc/arm64/bcm_vk/viper/mmu_regions.c rename to soc/brcm/bcmvk/viper/a72/mmu_regions.c diff --git a/soc/arm64/bcm_vk/viper/plat_core.c b/soc/brcm/bcmvk/viper/a72/plat_core.c similarity index 100% rename from soc/arm64/bcm_vk/viper/plat_core.c rename to soc/brcm/bcmvk/viper/a72/plat_core.c diff --git a/soc/arm64/bcm_vk/viper/soc.c b/soc/brcm/bcmvk/viper/a72/soc.c similarity index 100% rename from soc/arm64/bcm_vk/viper/soc.c rename to soc/brcm/bcmvk/viper/a72/soc.c diff --git a/soc/arm64/bcm_vk/viper/soc.h b/soc/brcm/bcmvk/viper/a72/soc.h similarity index 100% rename from soc/arm64/bcm_vk/viper/soc.h rename to soc/brcm/bcmvk/viper/a72/soc.h diff --git a/soc/arm/bcm_vk/viper/soc.c b/soc/brcm/bcmvk/viper/m7/soc.c similarity index 100% rename from soc/arm/bcm_vk/viper/soc.c rename to soc/brcm/bcmvk/viper/m7/soc.c diff --git a/soc/arm/bcm_vk/viper/soc.h b/soc/brcm/bcmvk/viper/m7/soc.h similarity index 100% rename from soc/arm/bcm_vk/viper/soc.h rename to soc/brcm/bcmvk/viper/m7/soc.h diff --git a/soc/xtensa/dc233c/CMakeLists.txt b/soc/cdns/dc233c/CMakeLists.txt similarity index 100% rename from soc/xtensa/dc233c/CMakeLists.txt rename to soc/cdns/dc233c/CMakeLists.txt diff --git a/soc/cdns/dc233c/Kconfig b/soc/cdns/dc233c/Kconfig new file mode 100644 index 00000000000..01ffa1c92ca --- /dev/null +++ b/soc/cdns/dc233c/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2017, 2023 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XTENSA_DC233C + select XTENSA + select XTENSA_HAL + select ARCH_HAS_THREAD_LOCAL_STORAGE + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_MMU + select ARCH_HAS_RESERVED_PAGE_FRAMES if XTENSA_MMU + select ARCH_HAS_USERSPACE if XTENSA_MMU + select XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP if XTENSA_MMU diff --git a/soc/cdns/dc233c/Kconfig.defconfig b/soc/cdns/dc233c/Kconfig.defconfig new file mode 100644 index 00000000000..c872936a044 --- /dev/null +++ b/soc/cdns/dc233c/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 Cadence Design Systems, Inc. +# Copyright (c) 2023 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_XTENSA_DC233C + +config XTENSA_MMU_NUM_L2_TABLES + int + default 48 if XTENSA_MMU + +# Both SRAM_OFFSET and KERNEL_VM_OFFSET are set at 1MB. +# This is to allow VECBASE to be mapped permanently +# via TLB way 4 (which covers 1MB). +config SRAM_OFFSET + hex + default 0x100000 if XTENSA_MMU + default 0x2400 + +config KERNEL_VM_OFFSET + hex + default 0x100000 + +endif diff --git a/soc/cdns/dc233c/Kconfig.soc b/soc/cdns/dc233c/Kconfig.soc new file mode 100644 index 00000000000..b39e7537b72 --- /dev/null +++ b/soc/cdns/dc233c/Kconfig.soc @@ -0,0 +1,13 @@ +# Copyright (c) 2017, 2023 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XTENSA_DC233C + bool + +config SOC + default "dc233c" if SOC_XTENSA_DC233C + +config SOC_TOOLCHAIN_NAME + string + default "dc233c" if SOC_XTENSA_DC233C diff --git a/soc/xtensa/dc233c/include/_soc_inthandlers.h b/soc/cdns/dc233c/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/dc233c/include/_soc_inthandlers.h rename to soc/cdns/dc233c/include/_soc_inthandlers.h diff --git a/soc/xtensa/dc233c/include/backtrace_helpers.h b/soc/cdns/dc233c/include/backtrace_helpers.h similarity index 100% rename from soc/xtensa/dc233c/include/backtrace_helpers.h rename to soc/cdns/dc233c/include/backtrace_helpers.h diff --git a/soc/xtensa/dc233c/include/xtensa-dc233c.ld b/soc/cdns/dc233c/include/xtensa-dc233c.ld similarity index 100% rename from soc/xtensa/dc233c/include/xtensa-dc233c.ld rename to soc/cdns/dc233c/include/xtensa-dc233c.ld diff --git a/soc/xtensa/dc233c/mmu.c b/soc/cdns/dc233c/mmu.c similarity index 100% rename from soc/xtensa/dc233c/mmu.c rename to soc/cdns/dc233c/mmu.c diff --git a/soc/cdns/dc233c/soc.yml b/soc/cdns/dc233c/soc.yml new file mode 100644 index 00000000000..ee6c461bc5e --- /dev/null +++ b/soc/cdns/dc233c/soc.yml @@ -0,0 +1,4 @@ +series: +- name: dc233c + socs: + - name: dc233c diff --git a/soc/xtensa/sample_controller/CMakeLists.txt b/soc/cdns/xtensa_sample_controller/CMakeLists.txt similarity index 100% rename from soc/xtensa/sample_controller/CMakeLists.txt rename to soc/cdns/xtensa_sample_controller/CMakeLists.txt diff --git a/soc/cdns/xtensa_sample_controller/Kconfig b/soc/cdns/xtensa_sample_controller/Kconfig new file mode 100644 index 00000000000..2e14ded4bc0 --- /dev/null +++ b/soc/cdns/xtensa_sample_controller/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2017 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XTENSA_SAMPLE_CONTROLLER + select XTENSA + select XTENSA_HAL + select ARCH_SUPPORTS_COREDUMP diff --git a/soc/cdns/xtensa_sample_controller/Kconfig.soc b/soc/cdns/xtensa_sample_controller/Kconfig.soc new file mode 100644 index 00000000000..e8231c183e8 --- /dev/null +++ b/soc/cdns/xtensa_sample_controller/Kconfig.soc @@ -0,0 +1,12 @@ +# Copyright (c) 2017 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XTENSA_SAMPLE_CONTROLLER + bool + +config SOC + default "xtensa_sample_controller" if SOC_XTENSA_SAMPLE_CONTROLLER + +config SOC_TOOLCHAIN_NAME + string + default "sample_controller" if SOC_XTENSA_SAMPLE_CONTROLLER diff --git a/soc/xtensa/sample_controller/include/_soc_inthandlers.h b/soc/cdns/xtensa_sample_controller/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/sample_controller/include/_soc_inthandlers.h rename to soc/cdns/xtensa_sample_controller/include/_soc_inthandlers.h diff --git a/soc/xtensa/sample_controller/include/xtensa-sample-controller.ld b/soc/cdns/xtensa_sample_controller/include/xtensa-sample-controller.ld similarity index 100% rename from soc/xtensa/sample_controller/include/xtensa-sample-controller.ld rename to soc/cdns/xtensa_sample_controller/include/xtensa-sample-controller.ld diff --git a/soc/cdns/xtensa_sample_controller/soc.yml b/soc/cdns/xtensa_sample_controller/soc.yml new file mode 100644 index 00000000000..52062a2ecfc --- /dev/null +++ b/soc/cdns/xtensa_sample_controller/soc.yml @@ -0,0 +1,4 @@ +series: +- name: xtensa_sample_controller + socs: + - name: xtensa_sample_controller diff --git a/soc/common/CMakeLists.txt b/soc/common/CMakeLists.txt index d9abad218cd..8deca3ca0e0 100644 --- a/soc/common/CMakeLists.txt +++ b/soc/common/CMakeLists.txt @@ -1,4 +1,4 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -add_subdirectory_ifdef(CONFIG_SOC_FAMILY_NRF nordic_nrf) +add_subdirectory_ifdef(CONFIG_RISCV_PRIVILEGED riscv-privileged) diff --git a/soc/common/Kconfig b/soc/common/Kconfig new file mode 100644 index 00000000000..3f8105b3689 --- /dev/null +++ b/soc/common/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if RISCV_PRIVILEGED + +rsource "riscv-privileged/Kconfig" + +endif # RISCV_PRIVILEGED diff --git a/soc/common/nordic_nrf/CMakeLists.txt b/soc/common/nordic_nrf/CMakeLists.txt deleted file mode 100644 index 6f397a07fab..00000000000 --- a/soc/common/nordic_nrf/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) diff --git a/soc/riscv/common/riscv-privileged/CMakeLists.txt b/soc/common/riscv-privileged/CMakeLists.txt similarity index 100% rename from soc/riscv/common/riscv-privileged/CMakeLists.txt rename to soc/common/riscv-privileged/CMakeLists.txt diff --git a/soc/riscv/common/riscv-privileged/Kconfig b/soc/common/riscv-privileged/Kconfig similarity index 100% rename from soc/riscv/common/riscv-privileged/Kconfig rename to soc/common/riscv-privileged/Kconfig diff --git a/soc/riscv/common/riscv-privileged/soc_common_irq.c b/soc/common/riscv-privileged/soc_common_irq.c similarity index 100% rename from soc/riscv/common/riscv-privileged/soc_common_irq.c rename to soc/common/riscv-privileged/soc_common_irq.c diff --git a/soc/riscv/common/riscv-privileged/soc_irq.S b/soc/common/riscv-privileged/soc_irq.S similarity index 100% rename from soc/riscv/common/riscv-privileged/soc_irq.S rename to soc/common/riscv-privileged/soc_irq.S diff --git a/soc/riscv/common/riscv-privileged/vector.S b/soc/common/riscv-privileged/vector.S similarity index 100% rename from soc/riscv/common/riscv-privileged/vector.S rename to soc/common/riscv-privileged/vector.S diff --git a/soc/cypress/CMakeLists.txt b/soc/cypress/CMakeLists.txt new file mode 100644 index 00000000000..e55e3139740 --- /dev/null +++ b/soc/cypress/CMakeLists.txt @@ -0,0 +1,8 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +add_subdirectory(psoc6) diff --git a/soc/cypress/Kconfig b/soc/cypress/Kconfig new file mode 100644 index 00000000000..8c645cb1d7b --- /dev/null +++ b/soc/cypress/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1 diff --git a/soc/cypress/Kconfig.defconfig b/soc/cypress/Kconfig.defconfig new file mode 100644 index 00000000000..1e382579c5f --- /dev/null +++ b/soc/cypress/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2018, Cypress +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1 diff --git a/soc/cypress/Kconfig.soc b/soc/cypress/Kconfig.soc new file mode 100644 index 00000000000..140274c4e26 --- /dev/null +++ b/soc/cypress/Kconfig.soc @@ -0,0 +1,17 @@ +# Copyright (c) 2018, Cypress +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_PSOC6 + bool + +config SOC_FAMILY_INFINEON_CAT1 + bool + +config SOC_FAMILY_INFINEON_CAT1A + bool + +config SOC_FAMILY + default "psoc6" if SOC_FAMILY_PSOC6 + default "infineon_cat1" if SOC_FAMILY_INFINEON_CAT1 + +rsource "*/Kconfig.soc" diff --git a/soc/cypress/psoc6/CMakeLists.txt b/soc/cypress/psoc6/CMakeLists.txt new file mode 100644 index 00000000000..f7a4bd016ad --- /dev/null +++ b/soc/cypress/psoc6/CMakeLists.txt @@ -0,0 +1,32 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_SERIES_PSOC62 OR CONFIG_SOC_SERIES_PSOC63) + add_subdirectory(old/common) + zephyr_include_directories(old) + zephyr_sources(old/soc.c) + + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 NOINIT old/noinit.ld) + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 RWDATA old/rwdata.ld) +else() + zephyr_include_directories(new) + zephyr_include_directories(new/common) + zephyr_sources(new/soc.c) + + # Add sections + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 NOINIT new/noinit.ld) + + # Add section for cm0p image ROM + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ROM_START SORT_KEY 0x0cm0p new/rom_cm0image.ld) + + # Add section for cm0p image RAM + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAM_SECTIONS SORT_KEY 0 new/ram_cm0image.ld) + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAMFUNC_SECTION SORT_KEY 0 new/ram_func.ld) + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 RODATA SORT_KEY 0 new/rom.ld) +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/cypress/psoc6/Kconfig b/soc/cypress/psoc6/Kconfig new file mode 100644 index 00000000000..78c412cc3ef --- /dev/null +++ b/soc/cypress/psoc6/Kconfig @@ -0,0 +1,58 @@ +# Cypress Semiconductor PSoC6 series configuration options +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PSOC62_PSOC63 + bool + select ARM + select HAS_CYPRESS_DRIVERS + select CPU_CORTEX_M0PLUS if SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + select CPU_CORTEX_M_HAS_SYSTICK if SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + select CPU_CORTEX_M_HAS_VTOR if SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + select CPU_HAS_ARM_MPU if SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + select CPU_CORTEX_M4 if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + select CPU_CORTEX_M_HAS_DWT if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + select CPU_CORTEX_M_HAS_SYSTICK if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + select CPU_HAS_ARM_MPU if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + select CPU_HAS_FPU if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + +config SOC_SERIES_PSOC62 + select SOC_SERIES_PSOC62_PSOC63 + +config SOC_SERIES_PSOC63 + select SOC_SERIES_PSOC62_PSOC63 + +config SOC_PSOC6_M0_ENABLES_M4 + bool "Dual-core support [activate Cortex-M4]" + depends on SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + help + Cortex-M0 CPU should boot Cortex-M4 + +config SOC_DIE_PSOC6 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select DYNAMIC_INTERRUPTS + select CPU_HAS_FPU + +if SOC_FAMILY_INFINEON_CAT1A + +## PSoC™ 6 Cortex M0+ prebuilt images +choice + prompt "PSoC™ 6 Cortex M0+ prebuilt images" + help + Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSoC™ 6 + dual-core MCU. The image is responsible for booting the Cortex-M4 on the device. + +config SOC_PSOC6_CM0P_IMAGE_SLEEP + bool "DeepSleep" + help + DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSoC™ 6 BLE + dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4 + application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4 + linker script. + +endchoice + +endif # SOC_FAMILY_INFINEON_CAT1A diff --git a/soc/cypress/psoc6/Kconfig.defconfig b/soc/cypress/psoc6/Kconfig.defconfig new file mode 100644 index 00000000000..a5995c61a0c --- /dev/null +++ b/soc/cypress/psoc6/Kconfig.defconfig @@ -0,0 +1,30 @@ +# Cypress Semiconductor PSoC6 series configuration options +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_PSOC62 || SOC_SERIES_PSOC63 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 50000000 + +rsource "old/Kconfig.defconfig.psoc*" + +endif # SOC_SERIES_PSOC62 || SOC_SERIES_PSOC63 + +if SOC_FAMILY_INFINEON_CAT1 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 + +config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE + hex + default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP + +config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE + hex + default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP + +rsource "new/Kconfig.defconfig.psoc6*" + +endif # SOC_FAMILY_INFINEON_CAT1 diff --git a/soc/cypress/psoc6/Kconfig.soc b/soc/cypress/psoc6/Kconfig.soc new file mode 100644 index 00000000000..b644b123a07 --- /dev/null +++ b/soc/cypress/psoc6/Kconfig.soc @@ -0,0 +1,1074 @@ +# Cypress Semiconductor PSoC6 series configuration options +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PSOC6 + bool + select SOC_FAMILY_INFINEON_CAT1 + +config SOC_SERIES_PSOC62 + bool + select SOC_FAMILY_PSOC6 + help + Enable support for Cypress PSoC6 MCU series + +config SOC_SERIES_PSOC63 + bool + select SOC_FAMILY_PSOC6 + help + Enable support for Cypress PSoC6-BLE MCU series + +# Cypress PSoC™ 6 MCU lines +config SOC_SERIES_PSOC_60 + bool + select SOC_SERIES_PSOC6 + help + Enable support for Infineon PSoC™ 60 MCU series + +config SOC_SERIES_PSOC_61 + bool + select SOC_SERIES_PSOC6 + help + Enable support for Infineon PSoC™ 61 MCU series + +config SOC_SERIES_PSOC_62 + bool + select SOC_SERIES_PSOC6 + help + Enable support for Infineon PSoC™ 62 MCU series + +config SOC_SERIES_PSOC_63 + bool + select SOC_SERIES_PSOC6 + help + Enable support for Infineon PSoC™ 63 MCU series + +config SOC_SERIES_PSOC_64 + bool + select SOC_SERIES_PSOC6 + help + Enable support for Infineon PSoC™ 64 MCU series + +config SOC_CY8C6247_M0 + bool + select SOC_SERIES_PSOC62 + +config SOC_CY8C6247_M4 + bool + select SOC_SERIES_PSOC62 + +config SOC_CY8C6347_M0 + bool + select SOC_SERIES_PSOC63 + +config SOC_CY8C6347_M4 + bool + select SOC_SERIES_PSOC63 + +config SOC_PART_NUMBER_CY8C6247BZI_D54 + bool + depends on SOC_SERIES_PSOC62 + help + CY8C6247BZI_D54 + +config SOC_PART_NUMBER_CY8C6347BZI_BLD53 + bool + depends on SOC_SERIES_PSOC63 + help + CY8C6347BZI_BLD53 + +# Infineon PSoC6 die +config SOC_DIE_PSOC6 + bool + select SOC_FAMILY_INFINEON_CAT1A + +# Infineon PSoC6_01 die +config SOC_DIE_PSOC6_01 + bool + select SOC_DIE_PSOC6 + +# Infineon PSoC6_02 die +config SOC_DIE_PSOC6_02 + bool + select SOC_DIE_PSOC6 + +# Infineon PSoC6_03 die +config SOC_DIE_PSOC6_03 + bool + select SOC_DIE_PSOC6 + +# Infineon PSoC6_04 die +config SOC_DIE_PSOC6_04 + bool + select SOC_DIE_PSOC6 + +# Infineon soc packages +config SOC_PACKAGE_PSOC6_01_124_BGA + bool + +config SOC_PACKAGE_PSOC6_01_116_BGA_BLE + bool + +config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE + bool + +config SOC_PACKAGE_PSOC6_01_80_WLCSP + bool + +config SOC_PACKAGE_PSOC6_01_116_BGA_USB + bool + +config SOC_PACKAGE_PSOC6_01_124_BGA_SIP + bool + +config SOC_PACKAGE_PSOC6_01_43_SMT + bool + +config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB + bool + +config SOC_PACKAGE_PSOC6_01_68_QFN_BLE + bool + +config SOC_PACKAGE_PSOC6_02_124_BGA + bool + +config SOC_PACKAGE_PSOC6_02_128_TQFP + bool + +config SOC_PACKAGE_PSOC6_02_100_WLCSP + bool + +config SOC_PACKAGE_PSOC6_02_68_QFN + bool + +config SOC_PACKAGE_PSOC6_03_100_TQFP + bool + +config SOC_PACKAGE_PSOC6_03_68_QFN + bool + +config SOC_PACKAGE_PSOC6_03_49_WLCSP + bool + +config SOC_PACKAGE_PSOC6_04_64_TQFP + bool + +config SOC_PACKAGE_PSOC6_04_68_QFN + bool + +config SOC_PACKAGE_PSOC6_04_80_TQFP + bool + +# Infineon PSoC6_01 series MCUs +config SOC_CY8C6036BZI_F04 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_60 + +config SOC_CY8C6016BZI_F04 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_60 + +config SOC_CY8C6116BZI_F54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6136BZI_F14 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6136BZI_F34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6137BZI_F14 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6137BZI_F34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6137BZI_F54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6117BZI_F34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6246BZI_D04 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6247BZI_D44 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6247BZI_D34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6247BZI_D54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6336BZI_BLF03 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6316BZI_BLF03 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6316BZI_BLF53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6336BZI_BLD13 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD43 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD33 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BLD13 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BLD43 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BLD33 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BLD53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6137FDI_F02 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6117FDI_F02 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6247FDI_D02 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6247FDI_D32 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6336BZI_BUD13 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BUD43 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BUD33 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BUD53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6337BZI_BLF13 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6136FDI_F42 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6247FDI_D52 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6136FTI_F42 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6247FTI_D52 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6247BZI_AUD54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6336BZI_BLF04 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6316BZI_BLF04 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6316BZI_BLF54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6336BZI_BLD14 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD44 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6247BFI_D54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CYBLE_416045_02 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BUD53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BUD13 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BUD43 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BUD33 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6137WI_F54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6117WI_F34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6247WI_D54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6336LQI_BLF02 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_68_QFN_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6336LQI_BLF42 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_68_QFN_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347LQI_BLD52 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_68_QFN_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CYB06447BZI_BLD54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_64 + +config SOC_CYB06447BZI_BLD53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_64 + +config SOC_CYB06447BZI_D54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_64 + +# Infineon PSoC6_02 series MCUs +config SOC_CYB0644ABZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_64 + +config SOC_CYS0644ABZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_64 + +config SOC_CY8C624ABZI_S2D44A0 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624ABZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624AAZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624AFNI_S2D43 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_100_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624ABZI_S2D04 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624ABZI_S2D14 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624AAZI_S2D14 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248AZI_S2D14 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248BZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248AZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248FNI_S2D43 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_100_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C614ABZI_S2F04 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614AAZI_S2F04 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614AFNI_S2F03 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_100_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614AAZI_S2F14 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614ABZI_S2F44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614AAZI_S2F44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614AFNI_S2F43 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_100_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6148BZI_S2F44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6148AZI_S2F44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6148FNI_S2F43 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_100_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C624ABZI_D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624ALQI_S2D42 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624ALQI_S2D02 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248LQI_S2D42 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248LQI_S2D02 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C614ALQI_S2F42 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614ALQI_S2F02 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6148LQI_S2F42 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6148LQI_S2F02 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_61 + +# Infineon PSoC6_04 series MCUs +config SOC_CY8C6244AZI_S4D92 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244LQI_S4D92 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244AZI_S4D93 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_80_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244AZI_S4D82 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244LQI_S4D82 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244AZI_S4D83 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_80_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244AZI_S4D62 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244LQI_S4D62 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244AZI_S4D12 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244LQI_S4D12 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6144AZI_S4F92 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144LQI_S4F92 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144AZI_S4F93 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_80_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144AZI_S4F82 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144LQI_S4F82 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144AZI_S4F83 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_80_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144AZI_S4F62 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144LQI_S4F62 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144AZI_S4F12 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144LQI_S4F12 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_SERIES + default "psoc62" if SOC_SERIES_PSOC62 + default "psoc63" if SOC_SERIES_PSOC63 + default "psoc6" if SOC_SERIES_PSOC6 + +config SOC + default "cy8c6247" if SOC_CY8C6247_M0 || SOC_CY8C6247_M4 + default "cy8c6347" if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + default "cy8c6036bzi_f04" if SOC_CY8C6036BZI_F04 + default "cy8c6016bzi_f04" if SOC_CY8C6016BZI_F04 + default "cy8c6116bzi_f54" if SOC_CY8C6116BZI_F54 + default "cy8c6136bzi_f14" if SOC_CY8C6136BZI_F14 + default "cy8c6136bzi_f34" if SOC_CY8C6136BZI_F34 + default "cy8c6137bzi_f14" if SOC_CY8C6137BZI_F14 + default "cy8c6137bzi_f34" if SOC_CY8C6137BZI_F34 + default "cy8c6137bzi_f54" if SOC_CY8C6137BZI_F54 + default "cy8c6117bzi_f34" if SOC_CY8C6117BZI_F34 + default "cy8c6246bzi_d04" if SOC_CY8C6246BZI_D04 + default "cy8c6247bzi_d44" if SOC_CY8C6247BZI_D44 + default "cy8c6247bzi_d34" if SOC_CY8C6247BZI_D34 + default "cy8c6247bzi_d54" if SOC_CY8C6247BZI_D54 + default "cy8c6336bzi_blf03" if SOC_CY8C6336BZI_BLF03 + default "cy8c6316bzi_blf03" if SOC_CY8C6316BZI_BLF03 + default "cy8c6316bzi_blf53" if SOC_CY8C6316BZI_BLF53 + default "cy8c6336bzi_bld13" if SOC_CY8C6336BZI_BLD13 + default "cy8c6347bzi_bld43" if SOC_CY8C6347BZI_BLD43 + default "cy8c6347bzi_bld33" if SOC_CY8C6347BZI_BLD33 + default "cy8c6347bzi_bld53" if SOC_CY8C6347BZI_BLD53 + default "cy8c6347fmi_bld13" if SOC_CY8C6347FMI_BLD13 + default "cy8c6347fmi_bld43" if SOC_CY8C6347FMI_BLD43 + default "cy8c6347fmi_bld33" if SOC_CY8C6347FMI_BLD33 + default "cy8c6347fmi_bld53" if SOC_CY8C6347FMI_BLD53 + default "cy8c6137fdi_f02" if SOC_CY8C6137FDI_F02 + default "cy8c6117fdi_f02" if SOC_CY8C6117FDI_F02 + default "cy8c6247fdi_d02" if SOC_CY8C6247FDI_D02 + default "cy8c6247fdi_d32" if SOC_CY8C6247FDI_D32 + default "cy8c6336bzi_bud13" if SOC_CY8C6336BZI_BUD13 + default "cy8c6347bzi_bud43" if SOC_CY8C6347BZI_BUD43 + default "cy8c6347bzi_bud33" if SOC_CY8C6347BZI_BUD33 + default "cy8c6347bzi_bud53" if SOC_CY8C6347BZI_BUD53 + default "cy8c6337bzi_blf13" if SOC_CY8C6337BZI_BLF13 + default "cy8c6136fdi_f42" if SOC_CY8C6136FDI_F42 + default "cy8c6247fdi_d52" if SOC_CY8C6247FDI_D52 + default "cy8c6136fti_f42" if SOC_CY8C6136FTI_F42 + default "cy8c6247fti_d52" if SOC_CY8C6247FTI_D52 + default "cy8c6247bzi_aud54" if SOC_CY8C6247BZI_AUD54 + default "cy8c6336bzi_blf04" if SOC_CY8C6336BZI_BLF04 + default "cy8c6316bzi_blf04" if SOC_CY8C6316BZI_BLF04 + default "cy8c6316bzi_blf54" if SOC_CY8C6316BZI_BLF54 + default "cy8c6336bzi_bld14" if SOC_CY8C6336BZI_BLD14 + default "cy8c6347bzi_bld44" if SOC_CY8C6347BZI_BLD44 + default "cy8c6347bzi_bld34" if SOC_CY8C6347BZI_BLD34 + default "cy8c6347bzi_bld54" if SOC_CY8C6347BZI_BLD54 + default "cy8c6247bfi_d54" if SOC_CY8C6247BFI_D54 + default "cyble_416045_02" if SOC_CYBLE_416045_02 + default "cy8c6347fmi_bud53" if SOC_CY8C6347FMI_BUD53 + default "cy8c6347fmi_bud13" if SOC_CY8C6347FMI_BUD13 + default "cy8c6347fmi_bud43" if SOC_CY8C6347FMI_BUD43 + default "cy8c6347fmi_bud33" if SOC_CY8C6347FMI_BUD33 + default "cy8c6137wi_f54" if SOC_CY8C6137WI_F54 + default "cy8c6117wi_f34" if SOC_CY8C6117WI_F34 + default "cy8c6247wi_d54" if SOC_CY8C6247WI_D54 + default "cy8c6336lqi_blf02" if SOC_CY8C6336LQI_BLF02 + default "cy8c6336lqi_blf42" if SOC_CY8C6336LQI_BLF42 + default "cy8c6347lqi_bld52" if SOC_CY8C6347LQI_BLD52 + default "cyb06447bzi_bld54" if SOC_CYB06447BZI_BLD54 + default "cyb06447bzi_bld53" if SOC_CYB06447BZI_BLD53 + default "cyb06447bzi_d54" if SOC_CYB06447BZI_D54 + default "cyb0644abzi_s2d44" if SOC_CYB0644ABZI_S2D44 + default "cys0644abzi_s2d44" if SOC_CYS0644ABZI_S2D44 + default "cy8c624abzi_s2d44a0" if SOC_CY8C624ABZI_S2D44A0 + default "cy8c624abzi_s2d44" if SOC_CY8C624ABZI_S2D44 + default "cy8c624aazi_s2d44" if SOC_CY8C624AAZI_S2D44 + default "cy8c624afni_s2d43" if SOC_CY8C624AFNI_S2D43 + default "cy8c624abzi_s2d04" if SOC_CY8C624ABZI_S2D04 + default "cy8c624abzi_s2d14" if SOC_CY8C624ABZI_S2D14 + default "cy8c624aazi_s2d14" if SOC_CY8C624AAZI_S2D14 + default "cy8c6248azi_s2d14" if SOC_CY8C6248AZI_S2D14 + default "cy8c6248bzi_s2d44" if SOC_CY8C6248BZI_S2D44 + default "cy8c6248azi_s2d44" if SOC_CY8C6248AZI_S2D44 + default "cy8c6248fni_s2d43" if SOC_CY8C6248FNI_S2D43 + default "cy8c614abzi_s2f04" if SOC_CY8C614ABZI_S2F04 + default "cy8c614aazi_s2f04" if SOC_CY8C614AAZI_S2F04 + default "cy8c614afni_s2f03" if SOC_CY8C614AFNI_S2F03 + default "cy8c614aazi_s2f14" if SOC_CY8C614AAZI_S2F14 + default "cy8c614abzi_s2f44" if SOC_CY8C614ABZI_S2F44 + default "cy8c614aazi_s2f44" if SOC_CY8C614AAZI_S2F44 + default "cy8c614afni_s2f43" if SOC_CY8C614AFNI_S2F43 + default "cy8c6148bzi_s2f44" if SOC_CY8C6148BZI_S2F44 + default "cy8c6148azi_s2f44" if SOC_CY8C6148AZI_S2F44 + default "cy8c6148fni_s2f43" if SOC_CY8C6148FNI_S2F43 + default "cy8c624abzi_d44" if SOC_CY8C624ABZI_D44 + default "cy8c624alqi_s2d42" if SOC_CY8C624ALQI_S2D42 + default "cy8c624alqi_s2d02" if SOC_CY8C624ALQI_S2D02 + default "cy8c6248lqi_s2d42" if SOC_CY8C6248LQI_S2D42 + default "cy8c6248lqi_s2d02" if SOC_CY8C6248LQI_S2D02 + default "cy8c614alqi_s2f42" if SOC_CY8C614ALQI_S2F42 + default "cy8c614alqi_s2f02" if SOC_CY8C614ALQI_S2F02 + default "cy8c6148lqi_s2f42" if SOC_CY8C6148LQI_S2F42 + default "cy8c6148lqi_s2f02" if SOC_CY8C6148LQI_S2F02 + default "cy8c6244azi_s4d92" if SOC_CY8C6244AZI_S4D92 + default "cy8c6244lqi_s4d92" if SOC_CY8C6244LQI_S4D92 + default "cy8c6244azi_s4d93" if SOC_CY8C6244AZI_S4D93 + default "cy8c6244azi_s4d82" if SOC_CY8C6244AZI_S4D82 + default "cy8c6244lqi_s4d82" if SOC_CY8C6244LQI_S4D82 + default "cy8c6244azi_s4d83" if SOC_CY8C6244AZI_S4D83 + default "cy8c6244azi_s4d62" if SOC_CY8C6244AZI_S4D62 + default "cy8c6244lqi_s4d62" if SOC_CY8C6244LQI_S4D62 + default "cy8c6244azi_s4d12" if SOC_CY8C6244AZI_S4D12 + default "cy8c6244lqi_s4d12" if SOC_CY8C6244LQI_S4D12 + default "cy8c6144azi_s4f92" if SOC_CY8C6144AZI_S4F92 + default "cy8c6144lqi_s4f92" if SOC_CY8C6144LQI_S4F92 + default "cy8c6144azi_s4f93" if SOC_CY8C6144AZI_S4F93 + default "cy8c6144azi_s4f82" if SOC_CY8C6144AZI_S4F82 + default "cy8c6144lqi_s4f82" if SOC_CY8C6144LQI_S4F82 + default "cy8c6144azi_s4f83" if SOC_CY8C6144AZI_S4F83 + default "cy8c6144azi_s4f62" if SOC_CY8C6144AZI_S4F62 + default "cy8c6144lqi_s4f62" if SOC_CY8C6144LQI_S4F62 + default "cy8c6144azi_s4f12" if SOC_CY8C6144AZI_S4F12 + default "cy8c6144lqi_s4f12" if SOC_CY8C6144LQI_S4F12 + +config SOC_PART_NUMBER + default "CY8C6247BZI_D54" if SOC_PART_NUMBER_CY8C6247BZI_D54 + default "CY8C6347BZI_BLD53" if SOC_PART_NUMBER_CY8C6347BZI_BLD53 + default "CY8C6036BZI_F04" if SOC_CY8C6036BZI_F04 + default "CY8C6016BZI_F04" if SOC_CY8C6016BZI_F04 + default "CY8C6116BZI_F54" if SOC_CY8C6116BZI_F54 + default "CY8C6136BZI_F14" if SOC_CY8C6136BZI_F14 + default "CY8C6136BZI_F34" if SOC_CY8C6136BZI_F34 + default "CY8C6137BZI_F14" if SOC_CY8C6137BZI_F14 + default "CY8C6137BZI_F34" if SOC_CY8C6137BZI_F34 + default "CY8C6137BZI_F54" if SOC_CY8C6137BZI_F54 + default "CY8C6117BZI_F34" if SOC_CY8C6117BZI_F34 + default "CY8C6246BZI_D04" if SOC_CY8C6246BZI_D04 + default "CY8C6247BZI_D44" if SOC_CY8C6247BZI_D44 + default "CY8C6247BZI_D34" if SOC_CY8C6247BZI_D34 + default "CY8C6247BZI_D54" if SOC_CY8C6247BZI_D54 + default "CY8C6336BZI_BLF03" if SOC_CY8C6336BZI_BLF03 + default "CY8C6316BZI_BLF03" if SOC_CY8C6316BZI_BLF03 + default "CY8C6316BZI_BLF53" if SOC_CY8C6316BZI_BLF53 + default "CY8C6336BZI_BLD13" if SOC_CY8C6336BZI_BLD13 + default "CY8C6347BZI_BLD43" if SOC_CY8C6347BZI_BLD43 + default "CY8C6347BZI_BLD33" if SOC_CY8C6347BZI_BLD33 + default "CY8C6347BZI_BLD53" if SOC_CY8C6347BZI_BLD53 + default "CY8C6347FMI_BLD13" if SOC_CY8C6347FMI_BLD13 + default "CY8C6347FMI_BLD43" if SOC_CY8C6347FMI_BLD43 + default "CY8C6347FMI_BLD33" if SOC_CY8C6347FMI_BLD33 + default "CY8C6347FMI_BLD53" if SOC_CY8C6347FMI_BLD53 + default "CY8C6137FDI_F02" if SOC_CY8C6137FDI_F02 + default "CY8C6117FDI_F02" if SOC_CY8C6117FDI_F02 + default "CY8C6247FDI_D02" if SOC_CY8C6247FDI_D02 + default "CY8C6247FDI_D32" if SOC_CY8C6247FDI_D32 + default "CY8C6336BZI_BUD13" if SOC_CY8C6336BZI_BUD13 + default "CY8C6347BZI_BUD43" if SOC_CY8C6347BZI_BUD43 + default "CY8C6347BZI_BUD33" if SOC_CY8C6347BZI_BUD33 + default "CY8C6347BZI_BUD53" if SOC_CY8C6347BZI_BUD53 + default "CY8C6337BZI_BLF13" if SOC_CY8C6337BZI_BLF13 + default "CY8C6136FDI_F42" if SOC_CY8C6136FDI_F42 + default "CY8C6247FDI_D52" if SOC_CY8C6247FDI_D52 + default "CY8C6136FTI_F42" if SOC_CY8C6136FTI_F42 + default "CY8C6247FTI_D52" if SOC_CY8C6247FTI_D52 + default "CY8C6247BZI_AUD54" if SOC_CY8C6247BZI_AUD54 + default "CY8C6336BZI_BLF04" if SOC_CY8C6336BZI_BLF04 + default "CY8C6316BZI_BLF04" if SOC_CY8C6316BZI_BLF04 + default "CY8C6316BZI_BLF54" if SOC_CY8C6316BZI_BLF54 + default "CY8C6336BZI_BLD14" if SOC_CY8C6336BZI_BLD14 + default "CY8C6347BZI_BLD44" if SOC_CY8C6347BZI_BLD44 + default "CY8C6347BZI_BLD34" if SOC_CY8C6347BZI_BLD34 + default "CY8C6347BZI_BLD54" if SOC_CY8C6347BZI_BLD54 + default "CY8C6247BFI_D54" if SOC_CY8C6247BFI_D54 + default "CYBLE_416045_02_device" if SOC_CYBLE_416045_02 + default "CY8C6347FMI_BUD53" if SOC_CY8C6347FMI_BUD53 + default "CY8C6347FMI_BUD13" if SOC_CY8C6347FMI_BUD13 + default "CY8C6347FMI_BUD43" if SOC_CY8C6347FMI_BUD43 + default "CY8C6347FMI_BUD33" if SOC_CY8C6347FMI_BUD33 + default "CY8C6137WI_F54" if SOC_CY8C6137WI_F54 + default "CY8C6117WI_F34" if SOC_CY8C6117WI_F34 + default "CY8C6247WI_D54" if SOC_CY8C6247WI_D54 + default "CY8C6336LQI_BLF02" if SOC_CY8C6336LQI_BLF02 + default "CY8C6336LQI_BLF42" if SOC_CY8C6336LQI_BLF42 + default "CY8C6347LQI_BLD52" if SOC_CY8C6347LQI_BLD52 + default "CYB06447BZI_BLD54" if SOC_CYB06447BZI_BLD54 + default "CYB06447BZI_BLD53" if SOC_CYB06447BZI_BLD53 + default "CYB06447BZI_D54" if SOC_CYB06447BZI_D54 + default "CYB0644ABZI_S2D44" if SOC_CYB0644ABZI_S2D44 + default "CYS0644ABZI_S2D44" if SOC_CYS0644ABZI_S2D44 + default "CY8C624ABZI_S2D44A0" if SOC_CY8C624ABZI_S2D44A0 + default "CY8C624ABZI_S2D44" if SOC_CY8C624ABZI_S2D44 + default "CY8C624AAZI_S2D44" if SOC_CY8C624AAZI_S2D44 + default "CY8C624AFNI_S2D43" if SOC_CY8C624AFNI_S2D43 + default "CY8C624ABZI_S2D04" if SOC_CY8C624ABZI_S2D04 + default "CY8C624ABZI_S2D14" if SOC_CY8C624ABZI_S2D14 + default "CY8C624AAZI_S2D14" if SOC_CY8C624AAZI_S2D14 + default "CY8C6248AZI_S2D14" if SOC_CY8C6248AZI_S2D14 + default "CY8C6248BZI_S2D44" if SOC_CY8C6248BZI_S2D44 + default "CY8C6248AZI_S2D44" if SOC_CY8C6248AZI_S2D44 + default "CY8C6248FNI_S2D43" if SOC_CY8C6248FNI_S2D43 + default "CY8C614ABZI_S2F04" if SOC_CY8C614ABZI_S2F04 + default "CY8C614AAZI_S2F04" if SOC_CY8C614AAZI_S2F04 + default "CY8C614AFNI_S2F03" if SOC_CY8C614AFNI_S2F03 + default "CY8C614AAZI_S2F14" if SOC_CY8C614AAZI_S2F14 + default "CY8C614ABZI_S2F44" if SOC_CY8C614ABZI_S2F44 + default "CY8C614AAZI_S2F44" if SOC_CY8C614AAZI_S2F44 + default "CY8C614AFNI_S2F43" if SOC_CY8C614AFNI_S2F43 + default "CY8C6148BZI_S2F44" if SOC_CY8C6148BZI_S2F44 + default "CY8C6148AZI_S2F44" if SOC_CY8C6148AZI_S2F44 + default "CY8C6148FNI_S2F43" if SOC_CY8C6148FNI_S2F43 + default "CY8C624ABZI_D44" if SOC_CY8C624ABZI_D44 + default "CY8C624ALQI_S2D42" if SOC_CY8C624ALQI_S2D42 + default "CY8C624ALQI_S2D02" if SOC_CY8C624ALQI_S2D02 + default "CY8C6248LQI_S2D42" if SOC_CY8C6248LQI_S2D42 + default "CY8C6248LQI_S2D02" if SOC_CY8C6248LQI_S2D02 + default "CY8C614ALQI_S2F42" if SOC_CY8C614ALQI_S2F42 + default "CY8C614ALQI_S2F02" if SOC_CY8C614ALQI_S2F02 + default "CY8C6148LQI_S2F42" if SOC_CY8C6148LQI_S2F42 + default "CY8C6148LQI_S2F02" if SOC_CY8C6148LQI_S2F02 + default "CY8C6244AZI_S4D92" if SOC_CY8C6244AZI_S4D92 + default "CY8C6244LQI_S4D92" if SOC_CY8C6244LQI_S4D92 + default "CY8C6244AZI_S4D93" if SOC_CY8C6244AZI_S4D93 + default "CY8C6244AZI_S4D82" if SOC_CY8C6244AZI_S4D82 + default "CY8C6244LQI_S4D82" if SOC_CY8C6244LQI_S4D82 + default "CY8C6244AZI_S4D83" if SOC_CY8C6244AZI_S4D83 + default "CY8C6244AZI_S4D62" if SOC_CY8C6244AZI_S4D62 + default "CY8C6244LQI_S4D62" if SOC_CY8C6244LQI_S4D62 + default "CY8C6244AZI_S4D12" if SOC_CY8C6244AZI_S4D12 + default "CY8C6244LQI_S4D12" if SOC_CY8C6244LQI_S4D12 + default "CY8C6144AZI_S4F92" if SOC_CY8C6144AZI_S4F92 + default "CY8C6144LQI_S4F92" if SOC_CY8C6144LQI_S4F92 + default "CY8C6144AZI_S4F93" if SOC_CY8C6144AZI_S4F93 + default "CY8C6144AZI_S4F82" if SOC_CY8C6144AZI_S4F82 + default "CY8C6144LQI_S4F82" if SOC_CY8C6144LQI_S4F82 + default "CY8C6144AZI_S4F83" if SOC_CY8C6144AZI_S4F83 + default "CY8C6144AZI_S4F62" if SOC_CY8C6144AZI_S4F62 + default "CY8C6144LQI_S4F62" if SOC_CY8C6144LQI_S4F62 + default "CY8C6144AZI_S4F12" if SOC_CY8C6144AZI_S4F12 + default "CY8C6144LQI_S4F12" if SOC_CY8C6144LQI_S4F12 diff --git a/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_01 b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_01 new file mode 100644 index 00000000000..3120bfdded2 --- /dev/null +++ b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_01 @@ -0,0 +1,15 @@ +# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Infineon PSoC6_01 based MCU default configuration + +if SOC_DIE_PSOC6_01 + +config NUM_IRQS + default 32 if CPU_CORTEX_M0PLUS + default 147 if CPU_CORTEX_M4 + +# add additional die specific params + +endif # SOC_DIE_PSOC6_01 diff --git a/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_02 b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_02 new file mode 100644 index 00000000000..b50a91cff1e --- /dev/null +++ b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_02 @@ -0,0 +1,15 @@ +# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Infineon PSoC6_02 based MCU default configuration + +if SOC_DIE_PSOC6_02 + +config NUM_IRQS + default 32 if CPU_CORTEX_M0PLUS + default 168 if CPU_CORTEX_M4 + +# add additional die specific params + +endif # SOC_DIE_PSOC6_02 diff --git a/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_04 b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_04 new file mode 100644 index 00000000000..30908b188a7 --- /dev/null +++ b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_04 @@ -0,0 +1,14 @@ +# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation +# Copyright (c) David Ullmann +# SPDX-License-Identifier: Apache-2.0 + +# Infineon PSoC6_04 based MCU default configuration + +if SOC_DIE_PSOC6_04 + +config NUM_IRQS + default 16 if CPU_CORTEX_M0PLUS + default 175 if CPU_CORTEX_M4 + +endif # SOC_DIE_PSOC6_04 diff --git a/soc/arm/infineon_cat1/common/pinctrl_soc.h b/soc/cypress/psoc6/new/common/pinctrl_soc.h similarity index 100% rename from soc/arm/infineon_cat1/common/pinctrl_soc.h rename to soc/cypress/psoc6/new/common/pinctrl_soc.h diff --git a/soc/arm/infineon_cat1/psoc6/noinit.ld b/soc/cypress/psoc6/new/noinit.ld similarity index 100% rename from soc/arm/infineon_cat1/psoc6/noinit.ld rename to soc/cypress/psoc6/new/noinit.ld diff --git a/soc/arm/infineon_cat1/psoc6/ram_cm0image.ld b/soc/cypress/psoc6/new/ram_cm0image.ld similarity index 100% rename from soc/arm/infineon_cat1/psoc6/ram_cm0image.ld rename to soc/cypress/psoc6/new/ram_cm0image.ld diff --git a/soc/arm/infineon_cat1/psoc6/ram_func.ld b/soc/cypress/psoc6/new/ram_func.ld similarity index 100% rename from soc/arm/infineon_cat1/psoc6/ram_func.ld rename to soc/cypress/psoc6/new/ram_func.ld diff --git a/soc/arm/infineon_cat1/psoc6/rom.ld b/soc/cypress/psoc6/new/rom.ld similarity index 100% rename from soc/arm/infineon_cat1/psoc6/rom.ld rename to soc/cypress/psoc6/new/rom.ld diff --git a/soc/arm/infineon_cat1/psoc6/rom_cm0image.ld b/soc/cypress/psoc6/new/rom_cm0image.ld similarity index 100% rename from soc/arm/infineon_cat1/psoc6/rom_cm0image.ld rename to soc/cypress/psoc6/new/rom_cm0image.ld diff --git a/soc/arm/infineon_cat1/psoc6/soc.c b/soc/cypress/psoc6/new/soc.c similarity index 100% rename from soc/arm/infineon_cat1/psoc6/soc.c rename to soc/cypress/psoc6/new/soc.c diff --git a/soc/arm/infineon_cat1/psoc6/soc.h b/soc/cypress/psoc6/new/soc.h similarity index 100% rename from soc/arm/infineon_cat1/psoc6/soc.h rename to soc/cypress/psoc6/new/soc.h diff --git a/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m0 b/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m0 new file mode 100644 index 00000000000..df5e232dc0f --- /dev/null +++ b/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m0 @@ -0,0 +1,10 @@ +# Cypress PSoC6 CM0 platform configuration options +# Copyright (c) 2018, Cypress +# SPDX-License-Identifier: Apache-2.0 + +if SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + +config NUM_IRQS + default 32 + +endif # SOC_CY8C6247_M0 || SOC_CY8C6347_M0 diff --git a/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m4 b/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m4 new file mode 100644 index 00000000000..975ea4fa7fb --- /dev/null +++ b/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m4 @@ -0,0 +1,10 @@ +# Cypress PSoC6 CM4 platform configuration options +# Copyright (c) 2018, Cypress +# SPDX-License-Identifier: Apache-2.0 + +if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + +config NUM_IRQS + default 147 + +endif # SOC_CY8C6247_M4 || SOC_CY8C6347_M4 diff --git a/soc/arm/cypress/common/CMakeLists.txt b/soc/cypress/psoc6/old/common/CMakeLists.txt similarity index 100% rename from soc/arm/cypress/common/CMakeLists.txt rename to soc/cypress/psoc6/old/common/CMakeLists.txt diff --git a/soc/arm/cypress/common/cypress_psoc6_dt.h b/soc/cypress/psoc6/old/common/cypress_psoc6_dt.h similarity index 100% rename from soc/arm/cypress/common/cypress_psoc6_dt.h rename to soc/cypress/psoc6/old/common/cypress_psoc6_dt.h diff --git a/soc/arm/cypress/common/soc_gpio.c b/soc/cypress/psoc6/old/common/soc_gpio.c similarity index 100% rename from soc/arm/cypress/common/soc_gpio.c rename to soc/cypress/psoc6/old/common/soc_gpio.c diff --git a/soc/arm/cypress/common/soc_gpio.h b/soc/cypress/psoc6/old/common/soc_gpio.h similarity index 100% rename from soc/arm/cypress/common/soc_gpio.h rename to soc/cypress/psoc6/old/common/soc_gpio.h diff --git a/soc/arm/cypress/psoc6/noinit.ld b/soc/cypress/psoc6/old/noinit.ld similarity index 100% rename from soc/arm/cypress/psoc6/noinit.ld rename to soc/cypress/psoc6/old/noinit.ld diff --git a/soc/arm/cypress/psoc6/rwdata.ld b/soc/cypress/psoc6/old/rwdata.ld similarity index 100% rename from soc/arm/cypress/psoc6/rwdata.ld rename to soc/cypress/psoc6/old/rwdata.ld diff --git a/soc/arm/cypress/psoc6/soc.c b/soc/cypress/psoc6/old/soc.c similarity index 100% rename from soc/arm/cypress/psoc6/soc.c rename to soc/cypress/psoc6/old/soc.c diff --git a/soc/arm/cypress/psoc6/soc.h b/soc/cypress/psoc6/old/soc.h similarity index 100% rename from soc/arm/cypress/psoc6/soc.h rename to soc/cypress/psoc6/old/soc.h diff --git a/soc/cypress/soc.yml b/soc/cypress/soc.yml new file mode 100644 index 00000000000..c973ed24b94 --- /dev/null +++ b/soc/cypress/soc.yml @@ -0,0 +1,131 @@ +family: +- name: psoc6 + series: + - name: psoc62 + socs: + - name: cy8c6247 + cpuclusters: + - name: m0 + - name: m4 + - name: psoc63 + socs: + - name: cy8c6347 + cpuclusters: + - name: m0 + - name: m4 +- name: infineon_cat1 + series: + - name: psoc6 + socs: + - name: cy8c6036bzi_f04 + - name: cy8c6016bzi_f04 + - name: cy8c6116bzi_f54 + - name: cy8c6136bzi_f14 + - name: cy8c6136bzi_f34 + - name: cy8c6137bzi_f14 + - name: cy8c6137bzi_f34 + - name: cy8c6137bzi_f54 + - name: cy8c6117bzi_f34 + - name: cy8c6246bzi_d04 + - name: cy8c6247bzi_d44 + - name: cy8c6247bzi_d34 + - name: cy8c6247bzi_d54 + - name: cy8c6336bzi_blf03 + - name: cy8c6316bzi_blf03 + - name: cy8c6316bzi_blf53 + - name: cy8c6336bzi_bld13 + - name: cy8c6347bzi_bld43 + - name: cy8c6347bzi_bld33 + - name: cy8c6347bzi_bld53 + - name: cy8c6347fmi_bld13 + - name: cy8c6347fmi_bld43 + - name: cy8c6347fmi_bld33 + - name: cy8c6347fmi_bld53 + - name: cy8c6137fdi_f02 + - name: cy8c6117fdi_f02 + - name: cy8c6247fdi_d02 + - name: cy8c6247fdi_d32 + - name: cy8c6336bzi_bud13 + - name: cy8c6347bzi_bud43 + - name: cy8c6347bzi_bud33 + - name: cy8c6347bzi_bud53 + - name: cy8c6337bzi_blf13 + - name: cy8c6136fdi_f42 + - name: cy8c6247fdi_d52 + - name: cy8c6136fti_f42 + - name: cy8c6247fti_d52 + - name: cy8c6247bzi_aud54 + - name: cy8c6336bzi_blf04 + - name: cy8c6316bzi_blf04 + - name: cy8c6316bzi_blf54 + - name: cy8c6336bzi_bld14 + - name: cy8c6347bzi_bld44 + - name: cy8c6347bzi_bld34 + - name: cy8c6347bzi_bld54 + - name: cy8c6247bfi_d54 + - name: cyble_416045_02 + - name: cy8c6347fmi_bud53 + - name: cy8c6347fmi_bud13 + - name: cy8c6347fmi_bud43 + - name: cy8c6347fmi_bud33 + - name: cy8c6137wi_f54 + - name: cy8c6117wi_f34 + - name: cy8c6247wi_d54 + - name: cy8c6336lqi_blf02 + - name: cy8c6336lqi_blf42 + - name: cy8c6347lqi_bld52 + - name: cyb06447bzi_bld54 + - name: cyb06447bzi_bld53 + - name: cyb06447bzi_d54 + - name: cyb0644abzi_s2d44 + - name: cys0644abzi_s2d44 + - name: cy8c624abzi_s2d44a0 + - name: cy8c624abzi_s2d44 + - name: cy8c624aazi_s2d44 + - name: cy8c624afni_s2d43 + - name: cy8c624abzi_s2d04 + - name: cy8c624abzi_s2d14 + - name: cy8c624aazi_s2d14 + - name: cy8c6248azi_s2d14 + - name: cy8c6248bzi_s2d44 + - name: cy8c6248azi_s2d44 + - name: cy8c6248fni_s2d43 + - name: cy8c614abzi_s2f04 + - name: cy8c614aazi_s2f04 + - name: cy8c614afni_s2f03 + - name: cy8c614aazi_s2f14 + - name: cy8c614abzi_s2f44 + - name: cy8c614aazi_s2f44 + - name: cy8c614afni_s2f43 + - name: cy8c6148bzi_s2f44 + - name: cy8c6148azi_s2f44 + - name: cy8c6148fni_s2f43 + - name: cy8c624abzi_d44 + - name: cy8c624alqi_s2d42 + - name: cy8c624alqi_s2d02 + - name: cy8c6248lqi_s2d42 + - name: cy8c6248lqi_s2d02 + - name: cy8c614alqi_s2f42 + - name: cy8c614alqi_s2f02 + - name: cy8c6148lqi_s2f42 + - name: cy8c6148lqi_s2f02 + - name: cy8c6244azi_s4d92 + - name: cy8c6244lqi_s4d92 + - name: cy8c6244azi_s4d93 + - name: cy8c6244azi_s4d82 + - name: cy8c6244lqi_s4d82 + - name: cy8c6244azi_s4d83 + - name: cy8c6244azi_s4d62 + - name: cy8c6244lqi_s4d62 + - name: cy8c6244azi_s4d12 + - name: cy8c6244lqi_s4d12 + - name: cy8c6144azi_s4f92 + - name: cy8c6144lqi_s4f92 + - name: cy8c6144azi_s4f93 + - name: cy8c6144azi_s4f82 + - name: cy8c6144lqi_s4f82 + - name: cy8c6144azi_s4f83 + - name: cy8c6144azi_s4f62 + - name: cy8c6144lqi_s4f62 + - name: cy8c6144azi_s4f12 + - name: cy8c6144lqi_s4f12 diff --git a/soc/riscv/efinix_sapphire/CMakeLists.txt b/soc/efinix/sapphire/CMakeLists.txt similarity index 100% rename from soc/riscv/efinix_sapphire/CMakeLists.txt rename to soc/efinix/sapphire/CMakeLists.txt diff --git a/soc/efinix/sapphire/Kconfig b/soc/efinix/sapphire/Kconfig new file mode 100644 index 00000000000..4617e7383c5 --- /dev/null +++ b/soc/efinix/sapphire/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EFINIX_SAPPHIRE + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC diff --git a/soc/efinix/sapphire/Kconfig.defconfig b/soc/efinix/sapphire/Kconfig.defconfig new file mode 100644 index 00000000000..75325b2fa55 --- /dev/null +++ b/soc/efinix/sapphire/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_EFINIX_SAPPHIRE + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 + +config RISCV_SOC_INTERRUPT_INIT + bool + default y + +config NUM_IRQS + int + default 36 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +endif # SOC_EFINIX_SAPPHIRE diff --git a/soc/efinix/sapphire/Kconfig.soc b/soc/efinix/sapphire/Kconfig.soc new file mode 100644 index 00000000000..5ab00455e4a --- /dev/null +++ b/soc/efinix/sapphire/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EFINIX_SAPPHIRE + bool + help + Efinix Sapphire VexRiscv system implementation + +config SOC + default "efinix_sapphire" if SOC_EFINIX_SAPPHIRE diff --git a/soc/efinix/sapphire/soc.yml b/soc/efinix/sapphire/soc.yml new file mode 100644 index 00000000000..d976114557a --- /dev/null +++ b/soc/efinix/sapphire/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: efinix_sapphire diff --git a/soc/espressif/CMakeLists.txt b/soc/espressif/CMakeLists.txt new file mode 100644 index 00000000000..5f7b7d6579f --- /dev/null +++ b/soc/espressif/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) diff --git a/soc/espressif/Kconfig b/soc/espressif/Kconfig new file mode 100644 index 00000000000..3c96a64bff6 --- /dev/null +++ b/soc/espressif/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ESPRESSIF_ESP32 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/Kconfig.defconfig b/soc/espressif/Kconfig.defconfig new file mode 100644 index 00000000000..86ab7f1bd64 --- /dev/null +++ b/soc/espressif/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ESPRESSIF_ESP32 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/Kconfig.soc b/soc/espressif/Kconfig.soc new file mode 100644 index 00000000000..4ad01dec79d --- /dev/null +++ b/soc/espressif/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ESPRESSIF_ESP32 + bool + +config SOC_FAMILY + default "espressif_esp32" if SOC_FAMILY_ESPRESSIF_ESP32 + +rsource "*/Kconfig.soc" diff --git a/soc/espressif/common/CMakeLists.txt b/soc/espressif/common/CMakeLists.txt new file mode 100644 index 00000000000..9cd2b6747ac --- /dev/null +++ b/soc/espressif/common/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_SERIES_ESP32 OR CONFIG_SOC_SERIES_ESP32S2 OR CONFIG_SOC_SERIES_ESP32S3) + zephyr_include_directories(include) +endif() diff --git a/soc/espressif/common/Kconfig b/soc/espressif/common/Kconfig new file mode 100644 index 00000000000..34d3c153c06 --- /dev/null +++ b/soc/espressif/common/Kconfig @@ -0,0 +1,215 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config ESPTOOLPY_FLASHFREQ_80M + bool + +config FLASH_SIZE + int + +config FLASH_BASE_ADDRESS + hex + +if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + +config ESP_SPIRAM + bool "Support for external, SPI-connected RAM" + help + This enables support for an external SPI RAM chip, connected in + parallel with the main SPI flash chip. + +config ESP_HEAP_MIN_EXTRAM_THRESHOLD + int "Minimum threshold for external RAM allocation" + default 8192 + range 1024 131072 + depends on ESP_SPIRAM + help + Threshold to decide if memory will be allocated from DRAM + or SPIRAM. If value of allocation size is less than this value, + memory will be allocated from internal RAM. + +config ESP_HEAP_SEARCH_ALL_REGIONS + bool "Search for all available heap regions" + depends on ESP_SPIRAM + default y + help + This configuration enables searching all available heap + regions. If the region of desired capability is exhausted, + memory will be allocated from other available region. + +config ESP_SPIRAM_HEAP_SIZE + int "Size of SPIRAM heap" + default 262134 if SYS_HEAP_SMALL_ONLY + default 1048576 if !SYS_HEAP_SMALL_ONLY + depends on ESP_SPIRAM + help + Specify size of SPIRAM heap. + +menu "SPI RAM config" + depends on ESP_SPIRAM + +choice SPIRAM_MODE + prompt "Mode (QUAD/OCT) of SPI RAM chip in use" + default SPIRAM_MODE_QUAD + +config SPIRAM_MODE_QUAD + bool "Quad Mode PSRAM" + +endchoice # SPIRAM_MODE + +choice SPIRAM_TYPE + prompt "Type of SPI RAM chip in use" + depends on ESP_SPIRAM + default SPIRAM_TYPE_ESPPSRAM16 + +config SPIRAM_TYPE_ESPPSRAM16 + bool "ESP-PSRAM16 or APS1604" + +config SPIRAM_TYPE_ESPPSRAM32 + bool "ESP-PSRAM32 or IS25WP032" + +config SPIRAM_TYPE_ESPPSRAM64 + bool "ESP-PSRAM64 or LY68L6400" + +endchoice # SPIRAM_TYPE + +config ESP_SPIRAM_SIZE + int "Size of SPIRAM part" + default 2097152 if SPIRAM_TYPE_ESPPSRAM16 + default 4194304 if SPIRAM_TYPE_ESPPSRAM32 + default 8388608 if SPIRAM_TYPE_ESPPSRAM64 + help + Specify size of SPIRAM part. + NOTE: If SPIRAM size is greater than 4MB, only + lower 4MB can be allocated using k_malloc(). + +choice SPIRAM_SPEED + prompt "Set RAM clock speed" + default SPIRAM_SPEED_40M + help + Select the speed for the SPI RAM chip. + If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: + + 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz + 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz + 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz + + Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host + will be occupied by the system. Which SPI host to use can be selected by the config item + SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The + option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. + (ESPTOOLPY_FLASHFREQ_79M is true) + +config SPIRAM_SPEED_26M + bool "26MHz clock speed" + depends on SOC_SERIES_ESP32S2 + +config SPIRAM_SPEED_20M + bool "20MHz clock speed" + depends on SOC_SERIES_ESP32S2 + +config SPIRAM_SPEED_40M + bool "40MHz clock speed" + +config SPIRAM_SPEED_80M + depends on ESPTOOLPY_FLASHFREQ_80M + bool "80MHz clock speed" + +config SPIRAM_SPEED_120M + depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3 + bool "120MHz clock speed" + +endchoice # SPIRAM_SPEED + +menu "PSRAM clock and cs IO for ESP32-DOWD" + +config D0WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 17 + help + The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use + 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D0WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 16 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use + 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endmenu # PSRAM clock and cs IO for ESP32-DOWD + +menu "PSRAM clock and cs IO for ESP32-D2WD" + +config D2WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 9 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D2WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endmenu # PSRAM clock and cs IO for ESP32-D2WD + +menu "PSRAM clock and cs IO for ESP32-PICO" + +config PICO_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. + + For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock + IO. + For the reference hardware design, please refer to + https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf + +endmenu # PSRAM clock and cs IO for ESP32-PICO + +config SPIRAM_CUSTOM_SPIWP_SD3_PIN + bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" + default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5 + default n + help + This setting is only used if the SPI flash pins have been overridden by setting the eFuses + SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. + + When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka + ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI + mode, so a WP pin setting is necessary. + + If this config item is set to N (default), the correct WP pin will be automatically used for any + Espressif chip or module with integrated flash. If a custom setting is needed, set this config item + to Y and specify the GPIO number connected to the WP pin. + + When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin + configured in the bootloader. + +config SPIRAM_SPIWP_SD3_PIN + int "Custom SPI PSRAM WP(SD3) Pin" + range 0 33 + default 7 + help + The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored + + If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this + value to the GPIO number of the SPIRAM WP pin. + +config SPIRAM + bool + default y + +endmenu # SPI RAM config + +endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 diff --git a/soc/espressif/common/Kconfig.defconfig b/soc/espressif/common/Kconfig.defconfig new file mode 100644 index 00000000000..62f930b0283 --- /dev/null +++ b/soc/espressif/common/Kconfig.defconfig @@ -0,0 +1,103 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32C3 + +config GEN_ISR_TABLES + default y + +config GEN_SW_ISR_TABLE + default y + +config GEN_IRQ_VECTOR_TABLE + default n + +config DYNAMIC_INTERRUPTS + default y + +config ISR_STACK_SIZE + default 2048 + +config ATOMIC_OPERATIONS_C + default y + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 16000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config CLOCK_CONTROL + default y + +if BOOTLOADER_MCUBOOT + +config HAS_FLASH_LOAD_OFFSET + default y + +config MCUBOOT_GENERATE_UNSIGNED_IMAGE + default y + +config MCUBOOT_GENERATE_CONFIRMED_IMAGE + default y + +config ROM_START_OFFSET + default 0x20 + +endif # BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_ESP32C3 + +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + +# Xtensa default options for ESP32 family +config XTENSA_RESET_VECTOR + default n + +config XTENSA_USE_CORE_CRT1 + default n + +config GEN_ISR_TABLES + default y + +config GEN_IRQ_VECTOR_TABLE + default n + +config CLOCK_CONTROL + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +if BOOTLOADER_MCUBOOT + +config HAS_FLASH_LOAD_OFFSET + default y + +config MCUBOOT_GENERATE_UNSIGNED_IMAGE + default y + +config MCUBOOT_GENERATE_CONFIRMED_IMAGE + default y + +config ROM_START_OFFSET + default 0x20 + +endif # BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 diff --git a/soc/xtensa/espressif_esp32/common/include/_soc_inthandlers.h b/soc/espressif/common/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/espressif_esp32/common/include/_soc_inthandlers.h rename to soc/espressif/common/include/_soc_inthandlers.h diff --git a/soc/xtensa/espressif_esp32/common/include/gdbstub/soc.h b/soc/espressif/common/include/gdbstub/soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/common/include/gdbstub/soc.h rename to soc/espressif/common/include/gdbstub/soc.h diff --git a/soc/espressif/esp32/CMakeLists.txt b/soc/espressif/esp32/CMakeLists.txt new file mode 100644 index 00000000000..537c7c76acc --- /dev/null +++ b/soc/espressif/esp32/CMakeLists.txt @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_ESP32_APPCPU) + zephyr_sources(soc_appcpu.c) +else() + zephyr_sources( + soc.c + loader.c + esp32-mp.c + ) +endif() + +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) + +zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c) + +zephyr_library_sources_ifdef(CONFIG_PM power.c) +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +# get flash size to use in esptool as string +math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") + +if(CONFIG_BOOTLOADER_ESP_IDF) + include(ExternalProject) + + ## we use hello-world project, but I think any can be used. + set(espidf_components_dir ${ESP_IDF_PATH}/components) + set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) + set(espidf_build_dir ${espidf_prefix}/build) + + ExternalProject_Add( + EspIdfBootloader + PREFIX ${espidf_prefix} + SOURCE_DIR ${espidf_components_dir}/bootloader/subproject + BINARY_DIR ${espidf_build_dir}/bootloader + CONFIGURE_COMMAND + ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} + -S ${espidf_components_dir}/bootloader/subproject + -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} + -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} + -DPYTHON=${PYTHON_EXECUTABLE} + BUILD_COMMAND + ${CMAKE_COMMAND} --build . + INSTALL_COMMAND "" # This particular build system has no install command + ) + + ExternalProject_Add( + EspPartitionTable + SOURCE_DIR ${espidf_components_dir}/partition_table + BINARY_DIR ${espidf_build_dir} + CONFIGURE_COMMAND "" + BUILD_COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q + --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin + INSTALL_COMMAND "" + ) + + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + add_dependencies(app EspIdfBootloader EspPartitionTable) + + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") +endif() + +if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + ARGS --chip esp32 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) + endif() + + if(CONFIG_MCUBOOT) + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") + endif() +endif() + +## When building for APPCPU +if(CONFIG_SOC_ESP32_APPCPU) + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py + ARGS -i ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c + -a "esp32_appcpu_fw_array") + endif() +else() + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + # get code-partition slot0 address + dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") + dt_reg_addr(img_0_off PATH ${dts_partition_path}) + + # get code-partition boot address + dt_nodelabel(dts_partition_path NODELABEL "boot_partition") + dt_reg_addr(boot_off PATH ${dts_partition_path}) + + board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") + board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") +endif() + +if(CONFIG_MCUBOOT) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_ESP32_APPCPU) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "") +else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") +endif() diff --git a/soc/espressif/esp32/Kconfig b/soc/espressif/esp32/Kconfig new file mode 100644 index 00000000000..bbcd17d1fb0 --- /dev/null +++ b/soc/espressif/esp32/Kconfig @@ -0,0 +1,263 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32 + select XTENSA + select CLOCK_CONTROL + select DYNAMIC_INTERRUPTS + select ARCH_HAS_GDBSTUB + select ARCH_SUPPORTS_COREDUMP + select PINCTRL + select XIP if !MCUBOOT + select HAS_ESPRESSIF_HAL + select CPU_HAS_FPU + select HAS_PM + select HAS_POWEROFF + +if SOC_SERIES_ESP32 + +config IDF_TARGET_ESP32 + bool "ESP32 as target board" + default y + +config ESP32_APPCPU_IRAM + hex "ESP32 APPCPU IRAM size" + depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU + default 0x20000 + help + Defines APPCPU IRAM area in bytes. + +config ESP32_APPCPU_DRAM + hex "ESP32 APPCPU DRAM size" + depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU + default 0x10000 + help + Defines APPCPU DRAM area in bytes. + +config SOC_ESP32_PROCPU + bool + help + This hidden configuration defines that build is targeted for PROCPU (core 0). + +config SOC_ESP32_APPCPU + bool + help + This hidden configuration defines that build is targeted for APPCPU (core 1). + +config SOC_ENABLE_APPCPU + bool + default y + depends on IPM && SOC_ESP32_PROCPU + help + This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled. + +config ESP_SYSTEM_RTC_EXT_XTAL + bool + +config ESP_SYSTEM_RTC_EXT_OSC + bool + +config ESP32_BT_RESERVE_DRAM + hex "Bluetooth controller reserved RAM region" + default 0xdb5c if BT + default 0 + +config ESP_HEAP_MEM_POOL_REGION_1_SIZE + int "Internal DRAM region 1 mempool size" + default 0 if MCUBOOT + default 1024 if SOC_ESP32_PROCPU + default 49152 + help + ESP32 has two banks of size 192K and 128K which can be used + as DRAM, system heap allocates area from region 0. + This configuration can be used to add memory from region 1 + to heap and can be allocated using k_malloc. + +choice ESP32_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32_RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + - "Internal 150kHz oscillator" option provides lowest deep sleep current + consumption, and does not require extra external components. However + frequency stability with respect to temperature is poor, so time may + drift in deep/light sleep modes. + - "External 32kHz crystal" provides better frequency stability, at the + expense of slightly higher (1uA) deep sleep current consumption. + - "External 32kHz oscillator" allows using 32kHz clock generated by an + external circuit. In this case, external clock signal must be connected + to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, + and <1V in case of square wave signal. Common mode voltage should be + 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. + Additionally, 1nF capacitor must be connected between 32K_XP pin and + ground. 32K_XP pin can not be used as a GPIO in this case. + - "Internal 8.5MHz oscillator divided by 256" option results in higher + deep sleep current (by 5uA) but has better frequency stability than + the internal 150kHz oscillator. It does not require external components. + +config ESP32_RTC_CLK_SRC_INT_RC + bool "Internal 150kHz RC oscillator" + +config ESP32_RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config ESP32_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XN pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config ESP32_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" + +endchoice # ESP32_RTC_CLK_SRC + +config ESP32_RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 + default 1024 if ESP32_RTC_CLK_SRC_INT_RC + range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 + range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +config ESP32_RTC_XTAL_CAL_RETRY + int "Number of attempts to repeat 32k XTAL calibration" + default 1 + depends on ESP32_RTC_CLK_SRC_EXT_CRYS + help + Number of attempts to repeat 32k XTAL calibration + before giving up and switching to the internal RC. + Increase this option if the 32k crystal oscillator + does not start and switches to internal RC. + +config ESP32_DEEP_SLEEP_WAKEUP_DELAY + int "Extra delay in deep sleep wake stub (in us)" + default 2000 + range 0 5000 + help + When ESP32 exits deep sleep, the CPU and the flash chip are powered on + at the same time. CPU will run deep sleep stub first, and then + proceed to load code from flash. Some flash chips need sufficient + time to pass between power on and first read operation. By default, + without any extra delay, this time is approximately 900us, although + some flash chip types need more than that. + + By default extra delay is set to 2000us. When optimizing startup time + for applications which require it, this value may be reduced. + + If you are seeing "flash read err, 1000" message printed to the + console after deep sleep reset, try increasing this value. + +choice ESP32_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or + derived from a single base MAC address. If the number of universal MAC addresses is four, + all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally + administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) + to the final octet of the base MAC address. If the number of universal MAC addresses is two, + only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. + These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. + The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. + These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. + When using the default (Espressif-assigned) base MAC address, either setting can be used. + When using a custom universal MAC address range, the correct setting will depend on the + allocation of MAC addresses in this range (either 2 or 4 per device.) + +config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_BT + +config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + bool "Four" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + select ESP_MAC_ADDR_UNIVERSE_BT + select ESP_MAC_ADDR_UNIVERSE_ETH + +endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES + +config ESP_MAC_ADDR_UNIVERSE_WIFI_AP + bool + +config ESP_MAC_ADDR_UNIVERSE_WIFI_STA + bool + +config ESP_MAC_ADDR_UNIVERSE_BT + bool + +config ESP_MAC_ADDR_UNIVERSE_ETH + bool + +config ESP32_UNIVERSAL_MAC_ADDRESSES + int + default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + +config ESP32_PHY_MAX_WIFI_TX_POWER + int "Max WiFi/BLE TX power (dBm)" + range 10 20 + default 20 + help + Set maximum transmit power for WiFi radio. Actual transmit power for high + data rates may be lower than this setting. + +config ESP32_PHY_MAX_TX_POWER + int + default ESP32_PHY_MAX_WIFI_TX_POWER + +config ESP32_EMAC + bool + default y if ETH_ESP32 + default y if MDIO_ESP32 + default n + help + Hidden option to enable the ESP32 Ethernet MAC driver. + Both Ethernet and MDIO depend on this driver. + This option allows enabling MDIO independently of Ethernet. + +if ESP32_EMAC + +config ETH_DMA_BUFFER_SIZE + int "Ethernet DMA buffer size (Byte)" + range 256 1600 + default 512 + help + Set the size of each buffer used by Ethernet MAC DMA. + +config ETH_DMA_RX_BUFFER_NUM + int "Amount of Ethernet DMA Rx buffers" + range 3 30 + default 10 + help + Number of DMA receive buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE. + Larger number of buffers could increase throughput somehow. + +config ETH_DMA_TX_BUFFER_NUM + int "Amount of Ethernet DMA Tx buffers" + range 3 30 + default 10 + help + Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE. + Larger number of buffers could increase throughput somehow. + +endif # ESP32_EMAC config + +endif # SOC_SERIES_ESP32 diff --git a/soc/espressif/esp32/Kconfig.defconfig b/soc/espressif/esp32/Kconfig.defconfig new file mode 100644 index 00000000000..7d793d2ecaa --- /dev/null +++ b/soc/espressif/esp32/Kconfig.defconfig @@ -0,0 +1,46 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32 + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@3ff42000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@3ff42000/flash@0) + +if SMP + +config SCHED_IPI_SUPPORTED + default y + +config SCHED_CPU_MASK + default y + +config MP_MAX_NUM_CPUS + default 2 + +endif # SMP config + +if GDBSTUB + +# ESP32 GDB expects 420 bytes G-packet. +# So double for hexadecimal digits. +config GDBSTUB_BUF_SZ + default 840 if GDBSTUB + +endif # GDBSTUB config + +endif # SOC_SERIES_ESP32 config diff --git a/soc/espressif/esp32/Kconfig.soc b/soc/espressif/esp32/Kconfig.soc new file mode 100644 index 00000000000..08aa0c413b4 --- /dev/null +++ b/soc/espressif/esp32/Kconfig.soc @@ -0,0 +1,153 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32 + bool + select SOC_FAMILY_ESPRESSIF_ESP32 + help + ESP32 Series + +config SOC_ESP32_D0WD_V3 + bool + select SOC_ESP32 + help + ESP32_D0WD_V3 + +config SOC_ESP32_D0WDR2_V3 + bool + select SOC_ESP32 + help + ESP32_D0WDR2_V3 + +config SOC_ESP32_U4WDH + bool + select SOC_ESP32 + help + ESP32_U4WDH + +config SOC_ESP32_PICO_V3 + bool + select SOC_ESP32 + help + ESP32_PICO_V3 + +config SOC_ESP32_PICO_V3_02 + bool + select SOC_ESP32 + help + ESP32_PICO_V3_02 + +config SOC_ESP32_PICO_D4 + bool + select SOC_ESP32 + help + ESP32_PICO_D4 + +# SiP with external flash / psram +config SOC_ESP32_WROOM_DA_N4 + bool + select SOC_ESP32 + help + ESP32_WROOM_DA_N4 + +config SOC_ESP32_WROOM_DA_N8 + bool + select SOC_ESP32 + help + ESP32_WROOM_DA_N8 + +config SOC_ESP32_WROOM_DA_N16 + bool + select SOC_ESP32 + help + ESP32_WROOM_DA_N16 + +config SOC_ESP32_WROOM_32UE_N4 + bool + select SOC_ESP32 + help + ESP32_WROOM_32UE_N4 + +config SOC_ESP32_WROOM_32UE_N8 + bool + select SOC_ESP32 + help + ESP32_WROOM_32UE_N8 + +config SOC_ESP32_WROOM_32UE_N16 + bool + select SOC_ESP32 + help + ESP32_WROOM_32UE_N16 + +config SOC_ESP32_WROVER_E_N4R2 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N4R2 + +config SOC_ESP32_WROVER_E_N8R2 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N8R2 + +config SOC_ESP32_WROVER_E_N16R2 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N16R2 + +config SOC_ESP32_WROVER_E_N4R8 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N4R8 + +config SOC_ESP32_WROVER_E_N8R8 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N8R8 + +config SOC_ESP32_WROVER_E_N16R8 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N16R8 + +config SOC_ESP32 + bool + select SOC_SERIES_ESP32 + help + ESP32 + +config SOC_SERIES + default "esp32" if SOC_SERIES_ESP32 + +config SOC + default "esp32" if SOC_SERIES_ESP32 + +config SOC_PART_NUMBER + default "ESP32_D0WD_V3" if SOC_ESP32_D0WD_V3 + default "ESP32_D0WDR2_V3" if SOC_ESP32_D0WDR2_V3 + default "ESP32_U4WDH" if SOC_ESP32_U4WDH + default "ESP32_PICO_V3" if SOC_ESP32_PICO_V3 + default "ESP32_PICO_V3_02" if SOC_ESP32_PICO_V3_02 + default "ESP32_PICO_D4" if SOC_ESP32_PICO_D4 + default "ESP32_WROOM_DA_N4" if SOC_ESP32_WROOM_DA_N4 + default "ESP32_WROOM_DA_N8" if SOC_ESP32_WROOM_DA_N8 + default "ESP32_WROOM_DA_N16" if SOC_ESP32_WROOM_DA_N16 + default "ESP32_WROOM_32UE_N4" if SOC_ESP32_WROOM_32UE_N4 + default "ESP32_WROOM_32UE_N8" if SOC_ESP32_WROOM_32UE_N8 + default "ESP32_WROOM_32UE_N16" if SOC_ESP32_WROOM_32UE_N16 + default "ESP32_WROVER_E_N4R2" if SOC_ESP32_WROVER_E_N4R2 + default "ESP32_WROVER_E_N8R2" if SOC_ESP32_WROVER_E_N8R2 + default "ESP32_WROVER_E_N16R2" if SOC_ESP32_WROVER_E_N16R2 + default "ESP32_WROVER_E_N4R8" if SOC_ESP32_WROVER_E_N4R8 + default "ESP32_WROVER_E_N8R8" if SOC_ESP32_WROVER_E_N8R8 + default "ESP32_WROVER_E_N16R8" if SOC_ESP32_WROVER_E_N16R8 + +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32" if SOC_SERIES_ESP32 diff --git a/soc/espressif/esp32/default.ld b/soc/espressif/esp32/default.ld new file mode 100644 index 00000000000..a3577757dcd --- /dev/null +++ b/soc/espressif/esp32/default.ld @@ -0,0 +1,583 @@ +/* + * Copyright (c) 2016 Cadence Design Systems, Inc. + * Copyright (c) 2017 Intel Corporation + * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * Linker script for the Xtensa platform. + */ + +#include +#include +#include +#include + +#define RAMABLE_REGION dram0_0_seg +#ifndef CONFIG_SOC_ENABLE_APPCPU +#define RAMABLE_REGION_1 dram0_1_seg +#else +#define RAMABLE_REGION_1 dram0_0_seg +#endif +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define FLASH_CODE_REGION irom0_0_seg + +#define ROMABLE_REGION ROM + +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x400000 +#endif + +#ifdef CONFIG_BOOTLOADER_ESP_IDF +#define IROM_SEG_ORG 0x400D0020 +#define IROM_SEG_LEN FLASH_SIZE-0x20 +#define IROM_SEG_ALIGN 0x4 +#else +#define IROM_SEG_ORG 0x400D0000 +#define IROM_SEG_LEN FLASH_SIZE +#define IROM_SEG_ALIGN 0x10000 +#endif +#define IRAM_SEG_LEN 0x20000 + +/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. + * Executing directly from LMA is not possible. */ +#undef GROUP_ROM_LINK_IN +#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion + +MEMORY +{ + mcuboot_hdr (RX): org = 0x0, len = 0x20 + metadata (RX): org = 0x20, len = 0x20 + ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 + + #ifdef CONFIG_SOC_ENABLE_APPCPU + iram0_0_seg(RX): org = 0x40080000, len = 0x08000 + #else + iram0_0_seg(RX): org = 0x40080000, len = IRAM_SEG_LEN + #endif + + irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN + /* + * Following is DRAM memory split with reserved address ranges in ESP32: + * + * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions) + * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage) + * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU) + * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU) + * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage) + * + * FIXME: + * - Utilize available memory regions to full capacity + */ + dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM + + #ifdef CONFIG_SOC_ENABLE_APPCPU + dram0_shm0_seg(RW): org = 0x3FFE5230, len = 2K /* shared RAM reserved for IPM */ + dram0_sem0_seg(RW): org = 0x3FFE5A30, len = 8 /* shared data reserved for IPM data header */ + dram0_1_seg(RW): org = 0x3FFE5A38, len = 0K /* for AMP builds dram0_1 is reserved for network core */ + #else + dram0_1_seg(RW): org = 0x3FFE5230, len = 0x1BCB0 - 0xEE0 /* skip data for APP CPU initialization usage */ + #endif + + /* DROM is the first segment placed in generated binary. + * MCUboot binary for ESP32 has image header of 0x20 bytes. + * Additional load header of 0x20 bytes are appended to the image. + * Hence, an offset of 0x40 is added to DROM segment origin. + */ + drom0_0_seg(R): org = 0x3F400040, len = 0x400000 - 0x40 + rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000 + rtc_slow_seg(RW): org = 0x50000000, len = 0x1000 +#if defined(CONFIG_ESP_SPIRAM) + ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE +#endif +#ifdef CONFIG_GEN_ISR_TABLES + IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 +#endif +} + +/* Default entry point: */ +PROVIDE ( _ResetVector = 0x40000400 ); +ENTRY(CONFIG_KERNEL_ENTRY) + +_rom_store_table = 0; + +PROVIDE(_memmap_vecbase_reset = 0x40000450); +PROVIDE(_memmap_reset_vector = 0x40000400); + +SECTIONS +{ + /* Reserve space for MCUboot header in the binary */ + .mcuboot_header : + { + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + } > mcuboot_hdr + .metadata : + { + /* Magic byte for load header */ + LONG(0xace637d3) + + /* Application entry point address */ + KEEP(*(.entry_addr)) + + /* IRAM metadata: + * - Destination address (VMA) for IRAM region + * - Flash offset (LMA) for start of IRAM region + * - Size of IRAM region + */ + + LONG(ADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.vectors)) + LONG(LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - LOADADDR(.iram0.vectors)) + + /* DRAM metadata: + * - Destination address (VMA) for DRAM region + * - Flash offset (LMA) for start of DRAM region + * - Size of DRAM region + */ + + LONG(ADDR(.dram0.data)) + LONG(LOADADDR(.dram0.data)) + LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) + } > metadata + +#include + + _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); + _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; + _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); + + /* NOTE: .rodata section should be the first section in the linker script and no + * other section should appear before .rodata section. This is the requirement + * to align ROM section to 64K page offset. + * Adding .rodata as first section helps to reduce size of generated binary by + * few kBs. + */ + SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + { + __rodata_region_start = ABSOLUTE(.); + + . = ALIGN(4); + #include + + . = ALIGN(4); + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata) + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + *(.rodata_wlog) + *(.rodata_wlog*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + SECTION_PROLOGUE(_RODATA_SECTION_END,,) + { + . = ALIGN(4); + _image_rodata_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + _image_dram_start = LOADADDR(.dram0.data); + _image_dram_size = LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - _image_dram_start; + _image_dram_vaddr = ADDR(.dram0.data); + + .dram0.data : + { + __data_start = ABSOLUTE(.); + + _btdm_data_start = ABSOLUTE(.); + *libbtdm_app.a:(.data .data.*) + . = ALIGN (4); + _btdm_data_end = ABSOLUTE(.); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + /* rodata for panic handler(libarch__xtensa__core.a) and all + * dependent functions should be placed in DRAM to avoid issue + * when flash cache is disabled */ + *libarch__xtensa__core.a:(.rodata .rodata.*) + *libkernel.a:fatal.*(.rodata .rodata.*) + *libkernel.a:init.*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:loader.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ + #pragma push_macro("GROUP_ROM_LINK_IN") + #undef GROUP_ROM_LINK_IN + #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN + #include + #pragma pop_macro("GROUP_ROM_LINK_IN") + + .dram0.end : + { + . = ALIGN(4); + #include + . = ALIGN(4); + _end = ABSOLUTE(.); + __data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + _image_iram_start = LOADADDR(.iram0.vectors); + _image_iram_size = LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - _image_iram_start; + _image_iram_vaddr = ADDR(.iram0.vectors); + + /* Send .iram0 code to iram */ + .iram0.vectors : ALIGN(4) + { + /* Vectors go to IRAM */ + _init_start = ABSOLUTE(.); + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + + /* This goes here, not at top of linker script, so addr2line finds it last, + and uses it in preference to the first symbol in IRAM */ + _iram_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) + { + /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + *libesp32.a:panic.*(.literal .text .literal.* .text.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) + *libkernel.a:(.literal .text .literal.* .text.*) + *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) + *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) + *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) + *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) + *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) + *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) + *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) + *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) + *libc.a:*(.literal .text .literal.* .text.*) + *libphy.a:( .phyiram .phyiram.*) + *libgcov.a:(.literal .text .literal.* .text.*) + +#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) + *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) +#endif + +#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) + *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) + *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) +#endif + + _iram_text_end = ABSOLUTE(.); + . = ALIGN(4); + _iram_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + /* RTC fast memory holds RTC wake stub code, + including from any source file named rtc_wake_stub*.c + */ + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + *rtc_wake_stub*.o(.literal .text .literal.* .text.*) + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + + /* RTC slow memory holds RTC wake stub + data/rodata, including from any source file + named rtc_wake_stub*.c + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + *(.rtc.data) + *(.rtc.rodata) + *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) + _rtc_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.o(.bss .bss.*) + *rtc_wake_stub*.o(COMMON) + _rtc_bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(rtc_slow_seg) + + /* This section located in RTC SLOW Memory area. + It holds data marked with RTC_SLOW_ATTR attribute. + See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } > rtc_slow_seg + + /* Get size of rtc slow data */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + +#if defined(CONFIG_ESP_SPIRAM) + .ext_ram.bss (NOLOAD): + { + _ext_ram_data_start = ABSOLUTE(.); + +#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) + *libdrivers__wifi.a:(.noinit .noinit.*) + *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) + *libsubsys__net__lib__config.a:(.noinit .noinit.*) + *libsubsys__net__ip.a:(.noinit .noinit.*) + *libsubsys__net.a:(.noinit .noinit.*) +#endif + _spiram_heap_start = ABSOLUTE(.); + . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; + + *(.ext_ram.bss*) + + _ext_ram_data_end = ABSOLUTE(.); + } GROUP_LINK_IN(ext_ram_seg) +#endif + + /* Shared RAM */ + SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); /* required by bluetooth library */ + __bss_start = ABSOLUTE(.); + + _btdm_bss_start = ABSOLUTE(.); + *libbtdm_app.a:(.bss .bss.* COMMON) + . = ALIGN (4); + _btdm_bss_end = ABSOLUTE(.); + + /* Buffer for system heap should be placed in dram0_0_seg */ + *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap) + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + __bss_end = ABSOLUTE(.); + _end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), + "DRAM segment data does not fit.") + + SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) + { + . = ALIGN (8); + *(.noinit) + *(.noinit.*) + . = ALIGN (8); + } GROUP_LINK_IN(RAMABLE_REGION_1) + + _image_irom_start = LOADADDR(.flash.text); + _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; + _image_irom_vaddr = ADDR(.flash.text); + + .flash.text : ALIGN(IROM_SEG_ALIGN) + { + _stext = .; + _text_start = ABSOLUTE(.); + +#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) + *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) +#endif + +#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) + *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) + *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) +#endif + + *(.literal .text .literal.* .text.*) + . = ALIGN(4); + _text_end = ABSOLUTE(.); + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + resolved by addr2line in preference to the first symbol in + the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) + +_heap_sentry = 0x3ffe3f20; + +#include + + .xtensa.info 0 : { *(.xtensa.info) } + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } + +#ifdef CONFIG_GEN_ISR_TABLES +#include +#endif + +} + +ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), + "IRAM0 segment data does not fit.") + +#if defined(CONFIG_ESP_SPIRAM) +ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), + "External SPIRAM overflowed.") +#endif /* CONFIG_ESP_SPIRAM */ diff --git a/soc/xtensa/espressif_esp32/esp32/default_appcpu.ld b/soc/espressif/esp32/default_appcpu.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/default_appcpu.ld rename to soc/espressif/esp32/default_appcpu.ld diff --git a/soc/xtensa/espressif_esp32/esp32/esp32-mp.c b/soc/espressif/esp32/esp32-mp.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/esp32-mp.c rename to soc/espressif/esp32/esp32-mp.c diff --git a/soc/xtensa/espressif_esp32/esp32/gdbstub.c b/soc/espressif/esp32/gdbstub.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/gdbstub.c rename to soc/espressif/esp32/gdbstub.c diff --git a/soc/xtensa/espressif_esp32/esp32/loader.c b/soc/espressif/esp32/loader.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/loader.c rename to soc/espressif/esp32/loader.c diff --git a/soc/xtensa/espressif_esp32/esp32/mcuboot.ld b/soc/espressif/esp32/mcuboot.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/mcuboot.ld rename to soc/espressif/esp32/mcuboot.ld diff --git a/soc/xtensa/espressif_esp32/esp32/newlib_fix.c b/soc/espressif/esp32/newlib_fix.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/newlib_fix.c rename to soc/espressif/esp32/newlib_fix.c diff --git a/soc/xtensa/espressif_esp32/esp32/pinctrl_soc.h b/soc/espressif/esp32/pinctrl_soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/pinctrl_soc.h rename to soc/espressif/esp32/pinctrl_soc.h diff --git a/soc/xtensa/espressif_esp32/esp32/power.c b/soc/espressif/esp32/power.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/power.c rename to soc/espressif/esp32/power.c diff --git a/soc/xtensa/espressif_esp32/esp32/poweroff.c b/soc/espressif/esp32/poweroff.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/poweroff.c rename to soc/espressif/esp32/poweroff.c diff --git a/soc/espressif/esp32/soc.c b/soc/espressif/esp32/soc.c new file mode 100644 index 00000000000..8e1a8ff737a --- /dev/null +++ b/soc/espressif/esp32/soc.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Include esp-idf headers first to avoid redefining BIT() macro */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "esp_private/system_internal.h" +#include "esp32/rom/cache.h" +#include "hal/soc_ll.h" +#include "soc/cpu.h" +#include "soc/gpio_periph.h" +#include "esp_spi_flash.h" +#include "esp_err.h" +#include "esp_timer.h" +#include "esp32/spiram.h" +#include "esp_app_format.h" +#include "hal/wdt_hal.h" + +#ifndef CONFIG_SOC_ENABLE_APPCPU +#include "esp_clk_internal.h" +#endif /* CONFIG_SOC_ENABLE_APPCPU */ + +#ifdef CONFIG_MCUBOOT +#include "bootloader_init.h" +#endif /* CONFIG_MCUBOOT */ +#include + +extern void z_cstart(void); +extern void esp_reset_reason_init(void); + +#ifdef CONFIG_SOC_ENABLE_APPCPU +extern const unsigned char esp32_appcpu_fw_array[]; + +void IRAM_ATTR esp_start_appcpu(void) +{ + esp_image_header_t *header = (esp_image_header_t *)&esp32_appcpu_fw_array[0]; + esp_image_segment_header_t *segment = + (esp_image_segment_header_t *)&esp32_appcpu_fw_array[sizeof(esp_image_header_t)]; + uint8_t *segment_payload; + uint32_t entry_addr = header->entry_addr; + uint32_t idx = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t); + + for (int i = 0; i < header->segment_count; i++) { + segment_payload = (uint8_t *)&esp32_appcpu_fw_array[idx]; + + if (segment->load_addr >= SOC_IRAM_LOW && segment->load_addr < SOC_IRAM_HIGH) { + /* IRAM segment only accepts 4 byte access, avoid memcpy usage here */ + volatile uint32_t *src = (volatile uint32_t *)segment_payload; + volatile uint32_t *dst = (volatile uint32_t *)segment->load_addr; + + for (int j = 0; j < segment->data_len / 4; j++) { + dst[j] = src[j]; + } + } else if (segment->load_addr >= SOC_DRAM_LOW && + segment->load_addr < SOC_DRAM_HIGH) { + + memcpy((void *)segment->load_addr, (const void *)segment_payload, + segment->data_len); + } + + idx += segment->data_len; + segment = (esp_image_segment_header_t *)&esp32_appcpu_fw_array[idx]; + idx += sizeof(esp_image_segment_header_t); + } + + esp_appcpu_start((void *)entry_addr); +} +#endif /* CONFIG_SOC_ENABLE_APPCPU */ + +/* + * This is written in C rather than assembly since, during the port bring up, + * Zephyr is being booted by the Espressif bootloader. With it, the C stack + * is already set up. + */ +void __attribute__((section(".iram1"))) __esp_platform_start(void) +{ + extern uint32_t _init_start; + + /* Move the exception vector table to IRAM. */ + __asm__ __volatile__ ( + "wsr %0, vecbase" + : + : "r"(&_init_start)); + + z_bss_zero(); + + __asm__ __volatile__ ( + "" + : + : "g"(&__bss_start) + : "memory"); + + /* Disable normal interrupts. */ + __asm__ __volatile__ ( + "wsr %0, PS" + : + : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); + + /* Initialize the architecture CPU pointer. Some of the + * initialization code wants a valid _current before + * arch_kernel_init() is invoked. + */ + __asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); + + esp_reset_reason_init(); + +#ifdef CONFIG_MCUBOOT + /* MCUboot early initialisation. */ + if (bootloader_init()) { + abort(); + } +#else + /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check + * on startup sequence related issues in application. Hence disable that + * as we are about to start Zephyr environment. + */ + wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; + + wdt_hal_write_protect_disable(&rtc_wdt_ctx); + wdt_hal_disable(&rtc_wdt_ctx); + wdt_hal_write_protect_enable(&rtc_wdt_ctx); + +#ifdef CONFIG_SOC_ESP32_APPCPU + /* Configures the CPU clock, RTC slow and fast clocks, and performs + * RTC slow clock calibration. + */ + esp_clk_init(); +#endif + + esp_timer_early_init(); + +#if CONFIG_SOC_ENABLE_APPCPU + /* start the ESP32 APP CPU */ + esp_start_appcpu(); +#endif + +#if CONFIG_ESP_SPIRAM + esp_err_t err = esp_spiram_init(); + + if (err != ESP_OK) { + printk("Failed to Initialize SPIRAM, aborting.\n"); + abort(); + } + esp_spiram_init_cache(); + if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { + printk("SPIRAM size is less than configured size, aborting.\n"); + abort(); + } +#endif + +/* Scheduler is not started at this point. Hence, guard functions + * must be initialized after esp_spiram_init_cache which internally + * uses guard functions. Setting guard functions before SPIRAM + * cache initialization will result in a crash. + */ +#if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM + spi_flash_guard_set(&g_flash_guard_default_ops); +#endif + +#endif /* CONFIG_MCUBOOT */ + + esp_intr_initialize(); + + /* Start Zephyr */ + z_cstart(); + + CODE_UNREACHABLE; +} + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int IRAM_ATTR arch_printk_char_out(int c) +{ + if (c == '\n') { + esp_rom_uart_tx_one_char('\r'); + } + esp_rom_uart_tx_one_char(c); + return 0; +} + +void sys_arch_reboot(int type) +{ + esp_restart_noos(); +} + +void IRAM_ATTR esp_restart_noos(void) +{ + /* Disable interrupts */ + z_xt_ints_off(0xFFFFFFFF); + + const uint32_t core_id = cpu_hal_get_core_id(); + const uint32_t other_core_id = (core_id == 0) ? 1 : 0; + + soc_ll_reset_core(other_core_id); + soc_ll_stall_core(other_core_id); + + /* Flush any data left in UART FIFOs */ + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + esp_rom_uart_tx_wait_idle(2); + + /* Disable cache */ + Cache_Read_Disable(0); + Cache_Read_Disable(1); + + /* 2nd stage bootloader reconfigures SPI flash signals. */ + /* Reset them to the defaults expected by ROM */ + WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); + + /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ + DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, + DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | + DPORT_BT_RST | DPORT_BTMAC_RST | + DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | + DPORT_EMAC_RST | DPORT_MACPWR_RST | + DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); + DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); + + /* Reset timer/spi/uart */ + DPORT_SET_PERI_REG_MASK( + DPORT_PERIP_RST_EN_REG, + /* UART TX FIFO cannot be reset correctly on ESP32, */ + /* so reset the UART memory by DPORT here. */ + DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | + DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); + DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); + + /* Clear entry point for APP CPU */ + DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0); + + /* Reset CPUs */ + if (core_id == 0) { + /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ + soc_ll_reset_core(1); + soc_ll_reset_core(0); + } else { + /* Running on APP CPU: need to reset PRO CPU and unstall it, */ + /* then reset APP CPU */ + soc_ll_reset_core(0); + soc_ll_stall_core(0); + soc_ll_reset_core(1); + } + + while (true) { + ; + } +} diff --git a/soc/xtensa/espressif_esp32/esp32/soc.h b/soc/espressif/esp32/soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/soc.h rename to soc/espressif/esp32/soc.h diff --git a/soc/xtensa/espressif_esp32/esp32/soc_appcpu.c b/soc/espressif/esp32/soc_appcpu.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/soc_appcpu.c rename to soc/espressif/esp32/soc_appcpu.c diff --git a/soc/espressif/esp32c3/CMakeLists.txt b/soc/espressif/esp32c3/CMakeLists.txt new file mode 100644 index 00000000000..3ea38bd5287 --- /dev/null +++ b/soc/espressif/esp32c3/CMakeLists.txt @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + vectors.S + soc_irq.S + soc_irq.c + soc.c + loader.c + ) + +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_PM power.c) +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +# get code-partition slot0 address +dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") +dt_reg_addr(img_0_off PATH ${dts_partition_path}) + +# get code-partition boot address +dt_nodelabel(dts_partition_path NODELABEL "boot_partition") +dt_reg_addr(boot_off PATH ${dts_partition_path}) + +# get flash size to use in esptool as string +math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") + +if(CONFIG_BOOTLOADER_ESP_IDF) + include(ExternalProject) + + ## we use hello-world project, but I think any can be used. + set(espidf_components_dir ${ESP_IDF_PATH}/components) + set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) + set(espidf_build_dir ${espidf_prefix}/build) + + ExternalProject_Add( + EspIdfBootloader + PREFIX ${espidf_prefix} + SOURCE_DIR ${espidf_components_dir}/bootloader/subproject + BINARY_DIR ${espidf_build_dir}/bootloader + CONFIGURE_COMMAND + ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} + -S ${espidf_components_dir}/bootloader/subproject + -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} + -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} + -DPYTHON=${PYTHON_EXECUTABLE} + BUILD_COMMAND + ${CMAKE_COMMAND} --build . + INSTALL_COMMAND "" # This particular build system has no install command + ) + + ExternalProject_Add( + EspPartitionTable + SOURCE_DIR ${espidf_components_dir}/partition_table + BINARY_DIR ${espidf_build_dir} + CONFIGURE_COMMAND "" + BUILD_COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q + --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin + INSTALL_COMMAND "" + ) + + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + add_dependencies(app EspIdfBootloader EspPartitionTable) + + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + +endif() + +if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) + endif() + + if(CONFIG_MCUBOOT) + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") + endif() + +endif() + +board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") + +board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + +if(CONFIG_MCUBOOT) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") +else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") +endif() diff --git a/soc/espressif/esp32c3/Kconfig b/soc/espressif/esp32c3/Kconfig new file mode 100644 index 00000000000..6533ba0b5d6 --- /dev/null +++ b/soc/espressif/esp32c3/Kconfig @@ -0,0 +1,97 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32C3 + select RISCV + select RISCV_GP + select DYNAMIC_INTERRUPTS + select CLOCK_CONTROL + select PINCTRL + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select HAS_ESPRESSIF_HAL + select XIP if !MCUBOOT + select HAS_PM + select HAS_POWEROFF + +if SOC_SERIES_ESP32C3 + +config IDF_TARGET_ESP32C3 + bool "ESP32C3 as target board" + default y + +config ESP_SYSTEM_RTC_EXT_XTAL + bool + +config ESP_SYSTEM_RTC_EXT_OSC + bool + +choice ESP32C3_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32C3_RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + +config ESP32C3_RTC_CLK_SRC_INT_RC + bool "Internal 150kHz RC oscillator" + +config ESP32C3_RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config ESP32C3_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XP pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config ESP32C3_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" + +endchoice # ESP32C3_RTC_CLK_SRC + +config ESP32C3_RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 + default 1024 if ESP32C3_RTC_CLK_SRC_INT_RC + range 0 27000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 + range 0 32766 if ESP32C3_RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +config ESP32_PHY_MAX_WIFI_TX_POWER + int "Max WiFi TX power (dBm)" + range 10 20 + default 20 + help + Set maximum transmit power for WiFi radio. Actual transmit power for high + data rates may be lower than this setting. + +config ESP32_PHY_MAX_TX_POWER + int + default ESP32_PHY_MAX_WIFI_TX_POWER + +config MAC_BB_PD + bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled" + depends on SOC_SERIES_ESP32C3 && TICKLESS_KERNEL + default n + help + If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered + down when PHY is disabled. Enabling this setting reduces power consumption + by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only), + 2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth). + +endif # SOC_SERIES_ESP32C3 diff --git a/soc/espressif/esp32c3/Kconfig.defconfig b/soc/espressif/esp32c3/Kconfig.defconfig new file mode 100644 index 00000000000..ce148c66d48 --- /dev/null +++ b/soc/espressif/esp32c3/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32C3 + +config NUM_IRQS + default 62 + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) + +endif # SOC_SERIES_ESP32C3 diff --git a/soc/espressif/esp32c3/Kconfig.soc b/soc/espressif/esp32c3/Kconfig.soc new file mode 100644 index 00000000000..ec98aaa3d96 --- /dev/null +++ b/soc/espressif/esp32c3/Kconfig.soc @@ -0,0 +1,51 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32C3 + bool + select SOC_FAMILY_ESPRESSIF_ESP32 + help + ESP32C3 + +config SOC_ESP32C3_FX4 + bool + select SOC_ESP32C3 + help + ESP32C3_FX4 + +config SOC_ESP32C3_MINI_N4 + bool + select SOC_ESP32C3 + help + ESP32C3_MINI_N4 + +config SOC_ESP32C3_WROOM_02_N4 + bool + select SOC_ESP32C3 + help + ESP32C3_WROOM_02_N4 + +config SOC_ESP32C3_WROOM_02_N8 + bool + select SOC_ESP32C3 + help + ESP32C3_WROOM_02_N8 + +config SOC_ESP32C3 + bool + select SOC_SERIES_ESP32C3 + help + ESP32C3 + +config SOC_SERIES + default "esp32c3" if SOC_SERIES_ESP32C3 + +config SOC + default "esp32c3" if SOC_SERIES_ESP32C3 + +config SOC_PART_NUMBER + default "ESP32C3_FX4" if SOC_ESP32C3_FX4 + default "ESP32C3_MINI_N4" if SOC_ESP32C3_MINI_N4 + default "ESP32C3_WROOM_02_N4" if SOC_ESP32C3_WROOM_02_N4 + default "ESP32C3_WROOM_02_N8" if SOC_ESP32C3_WROOM_02_N8 + default "ESP32C3" if SOC_ESP32C3 diff --git a/soc/riscv/espressif_esp32/esp32c3/default.ld b/soc/espressif/esp32c3/default.ld similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/default.ld rename to soc/espressif/esp32c3/default.ld diff --git a/soc/riscv/espressif_esp32/esp32c3/loader.c b/soc/espressif/esp32c3/loader.c similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/loader.c rename to soc/espressif/esp32c3/loader.c diff --git a/soc/riscv/espressif_esp32/esp32c3/mcuboot.ld b/soc/espressif/esp32c3/mcuboot.ld similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/mcuboot.ld rename to soc/espressif/esp32c3/mcuboot.ld diff --git a/soc/riscv/espressif_esp32/esp32c3/pinctrl_soc.h b/soc/espressif/esp32c3/pinctrl_soc.h similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/pinctrl_soc.h rename to soc/espressif/esp32c3/pinctrl_soc.h diff --git a/soc/riscv/espressif_esp32/esp32c3/power.c b/soc/espressif/esp32c3/power.c similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/power.c rename to soc/espressif/esp32c3/power.c diff --git a/soc/riscv/espressif_esp32/esp32c3/poweroff.c b/soc/espressif/esp32c3/poweroff.c similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/poweroff.c rename to soc/espressif/esp32c3/poweroff.c diff --git a/soc/riscv/espressif_esp32/esp32c3/soc.c b/soc/espressif/esp32c3/soc.c similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/soc.c rename to soc/espressif/esp32c3/soc.c diff --git a/soc/riscv/espressif_esp32/esp32c3/soc.h b/soc/espressif/esp32c3/soc.h similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/soc.h rename to soc/espressif/esp32c3/soc.h diff --git a/soc/riscv/espressif_esp32/esp32c3/soc_irq.S b/soc/espressif/esp32c3/soc_irq.S similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/soc_irq.S rename to soc/espressif/esp32c3/soc_irq.S diff --git a/soc/riscv/espressif_esp32/esp32c3/soc_irq.c b/soc/espressif/esp32c3/soc_irq.c similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/soc_irq.c rename to soc/espressif/esp32c3/soc_irq.c diff --git a/soc/riscv/espressif_esp32/esp32c3/vectors.S b/soc/espressif/esp32c3/vectors.S similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/vectors.S rename to soc/espressif/esp32c3/vectors.S diff --git a/soc/espressif/esp32s2/CMakeLists.txt b/soc/espressif/esp32s2/CMakeLists.txt new file mode 100644 index 00000000000..1c840ce2289 --- /dev/null +++ b/soc/espressif/esp32s2/CMakeLists.txt @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + soc_cache.c + loader.c + ) + +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) + +zephyr_library_sources_ifdef(CONFIG_PM power.c) +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +# get code-partition slot0 address +dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") +dt_reg_addr(img_0_off PATH ${dts_partition_path}) + +# get code-partition boot address +dt_nodelabel(dts_partition_path NODELABEL "boot_partition") +dt_reg_addr(boot_off PATH ${dts_partition_path}) + +# get flash size to use in esptool as string +math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") + +if(CONFIG_BOOTLOADER_ESP_IDF) + include(ExternalProject) + + ## we use hello-world project, but I think any can be used. + set(espidf_components_dir ${ESP_IDF_PATH}/components) + set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) + set(espidf_build_dir ${espidf_prefix}/build) + + ExternalProject_Add( + EspIdfBootloader + PREFIX ${espidf_prefix} + SOURCE_DIR ${espidf_components_dir}/bootloader/subproject + BINARY_DIR ${espidf_build_dir}/bootloader + CONFIGURE_COMMAND + ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} + -S ${espidf_components_dir}/bootloader/subproject + -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} + -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} + -DPYTHON=${PYTHON_EXECUTABLE} + BUILD_COMMAND + ${CMAKE_COMMAND} --build . + INSTALL_COMMAND "" # This particular build system has no install command + ) + + ExternalProject_Add( + EspPartitionTable + SOURCE_DIR ${espidf_components_dir}/partition_table + BINARY_DIR ${espidf_build_dir} + CONFIGURE_COMMAND "" + BUILD_COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q + --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin + INSTALL_COMMAND "" + ) + + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + add_dependencies(app EspIdfBootloader EspPartitionTable) + + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + +endif() + +if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + ARGS --chip esp32s2 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) + endif() + + if(CONFIG_MCUBOOT) + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") + endif() + +endif() + +board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") + +board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + +if(CONFIG_MCUBOOT) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") +else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") +endif() diff --git a/soc/espressif/esp32s2/Kconfig b/soc/espressif/esp32s2/Kconfig new file mode 100644 index 00000000000..1c657c4e1b5 --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig @@ -0,0 +1,228 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32S2 + select XTENSA + select ATOMIC_OPERATIONS_C + select DYNAMIC_INTERRUPTS + select CLOCK_CONTROL + select PINCTRL + select XIP if !MCUBOOT + select HAS_ESPRESSIF_HAL + select ARCH_SUPPORTS_COREDUMP + select HAS_PM + select HAS_POWEROFF + +if SOC_SERIES_ESP32S2 + +config IDF_TARGET_ESP32S2 + bool "ESP32S2 as target SOC" + default y + +config ESP_SYSTEM_RTC_EXT_XTAL + bool + +config ESP_SYSTEM_RTC_EXT_OSC + bool + +choice ESP32S2_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32S2_RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + - "Internal 90kHz oscillator" option provides lowest deep sleep current + consumption, and does not require extra external components. However + frequency stability with respect to temperature is poor, so time may + drift in deep/light sleep modes. + - "External 32kHz crystal" provides better frequency stability, at the + expense of slightly higher (1uA) deep sleep current consumption. + - "External 32kHz oscillator" allows using 32kHz clock generated by an + external circuit. In this case, external clock signal must be connected + to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, + and <1V in case of square wave signal. Common mode voltage should be + 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. + Additionally, 1nF capacitor must be connected between 32K_XP pin and + ground. 32K_XP pin can not be used as a GPIO in this case. + - "Internal 8MHz oscillator divided by 256" option results in higher + deep sleep current (by 5uA) but has better frequency stability than + the internal 90kHz oscillator. It does not require external components. + +config ESP32S2_RTC_CLK_SRC_INT_RC + bool "Internal 90kHz RC oscillator" + +config ESP32S2_RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config ESP32S2_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XN pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config ESP32S2_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" + +endchoice + +config ESP32S2_RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS || ESP32S2_RTC_CLK_SRC_EXT_OSC || ESP32S2_RTC_CLK_SRC_INT_8MD256 + default 576 if ESP32S2_RTC_CLK_SRC_INT_RC + range 0 125000 + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +menu "Cache config" + +choice + prompt "Instruction cache line size" + default ESP32S2_INSTRUCTION_CACHE_LINE_32B + + config ESP32S2_INSTRUCTION_CACHE_LINE_16B + bool "16 Bytes" + + config ESP32S2_INSTRUCTION_CACHE_LINE_32B + bool "32 Bytes" + +endchoice + +choice + prompt "Instruction cache size" + default ESP32S2_INSTRUCTION_CACHE_8KB + + config ESP32S2_INSTRUCTION_CACHE_8KB + bool "8KB instruction cache size" + + config ESP32S2_INSTRUCTION_CACHE_16KB + bool "16KB instruction cache size" + +endchoice + +choice + prompt "Data cache size" + default ESP32S2_DATA_CACHE_0KB if !ESP_SPIRAM + default ESP32S2_DATA_CACHE_8KB if ESP_SPIRAM + + config ESP32S2_DATA_CACHE_0KB + bool "0KB data cache size" + + config ESP32S2_DATA_CACHE_8KB + bool "8KB data cache size" + + config ESP32S2_DATA_CACHE_16KB + bool "16KB data cache size" + +endchoice + +choice + prompt "Data cache line size" + default ESP32S2_DATA_CACHE_LINE_32B + + config ESP32S2_DATA_CACHE_LINE_16B + bool "16 Bytes" + + config ESP32S2_DATA_CACHE_LINE_32B + bool "32 Bytes" + +endchoice + +config ESP32S2_INSTRUCTION_CACHE_SIZE + hex + default 0x4000 if ESP32S2_INSTRUCTION_CACHE_16KB + default 0x2000 + +config ESP32S2_DATA_CACHE_SIZE + hex + default 0x2000 if ESP32S2_DATA_CACHE_8KB + default 0x4000 if ESP32S2_DATA_CACHE_16KB + default 0x0000 + +endmenu # Cache config + +menu "PSRAM clock and cs IO for ESP32-S2" + depends on ESP_SPIRAM + +config DEFAULT_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 30 + help + The PSRAM CLOCK IO can be any unused GPIO, user can config + it based on hardware design. + +config DEFAULT_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 26 + help + The PSRAM CS IO can be any unused GPIO, user can config it + based on hardware design. + +endmenu # PSRAM clock and cs IO for ESP32S2 + +choice ESP32S2_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or + derived from a single base MAC address. If the number of universal MAC addresses is two, + all interfaces (WiFi station, WiFi softap) receive a universally administered MAC + address. + They are generated sequentially by adding 0, and 1 (respectively) to the final octet of + the base MAC address. If the number of universal MAC addresses is one, only WiFi station + receives a universally administered MAC address. + The WiFi softap receives local MAC addresses. It's derived from the universal WiFi + station MAC addresses. + When using the default (Espressif-assigned) base MAC address, either setting can be used. + When using a custom universal MAC address range, the correct setting will depend on the + allocation of MAC addresses in this range (either 1 or 2 per device). + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE + bool "One" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + +endchoice # ESP32S2_UNIVERSAL_MAC_ADDRESSES + +config ESP_MAC_ADDR_UNIVERSE_WIFI_AP + bool + +config ESP_MAC_ADDR_UNIVERSE_WIFI_STA + bool + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES + int + default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE + default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + +config ESP32_PHY_MAX_WIFI_TX_POWER + int "Max WiFi TX power (dBm)" + range 10 20 + default 20 + help + Set maximum transmit power for WiFi radio. Actual transmit power for high + data rates may be lower than this setting. + +config ESP32_PHY_MAX_TX_POWER + int + default ESP32_PHY_MAX_WIFI_TX_POWER + +endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/Kconfig.defconfig b/soc/espressif/esp32s2/Kconfig.defconfig new file mode 100644 index 00000000000..6daf53e76df --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S2 + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) + +endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s2/Kconfig.defconfig.series b/soc/espressif/esp32s2/Kconfig.defconfig.series new file mode 100644 index 00000000000..50ddbd72704 --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig.defconfig.series @@ -0,0 +1,27 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config MP_MAX_NUM_CPUS + default 1 + +config ISR_STACK_SIZE + default 2048 + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) + +endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/Kconfig.soc b/soc/espressif/esp32s2/Kconfig.soc new file mode 100644 index 00000000000..17b801087f9 --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig.soc @@ -0,0 +1,126 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32S2 + bool + select SOC_FAMILY_ESPRESSIF_ESP32 + help + ESP32-S2 Series + +config SOC_ESP32S2_R2 + bool + select SOC_ESP32S2 + help + ESP32S2_R2 + +config SOC_ESP32S2_FH2 + bool + select SOC_ESP32S2 + help + ESP32S2_FH2 + +config SOC_ESP32S2_FH4 + bool + select SOC_ESP32S2 + help + ESP32S2_FH4 + +config SOC_ESP32S2_FN4R2 + bool + select SOC_ESP32S2 + help + ESP32S2_FN4R2 + +# SiP with external flash / psram +config SOC_ESP32S2_SOLO_N4 + bool + select SOC_ESP32S2 + help + ESP32S2_SOLO_N4 + +config SOC_ESP32S2_SOLO_N8 + bool + select SOC_ESP32S2 + help + ESP32S2_SOLO_N8 + +config SOC_ESP32S2_SOLO_N16 + bool + select SOC_ESP32S2 + help + ESP32S2_SOLO_N16 + +config SOC_ESP32S2_SOLO_N4R2 + bool + select SOC_ESP32S2 + help + ESP32S2_SOLO_N4R2 + +config SOC_ESP32S2_MINI_N4 + bool + select SOC_ESP32S2 + help + ESP32S2_MINI_N4 + +config SOC_ESP32S2_MINI_N4R2 + bool + select SOC_ESP32S2 + help + ESP32S2_MINI_N4R2 + +config SOC_ESP32S2_WROOM + bool + select SOC_ESP32S2 + help + ESP32S2_WROOM + +config SOC_ESP32S2_WROVER_N4R2 + bool + select SOC_ESP32S2 + help + ESP32S2_WROVER_N4R2 + +config SOC_ESP32S2_WROVER_N8R2 + bool + select SOC_ESP32S2 + help + ESP32S2_WROVER_N8R2 + +config SOC_ESP32S2_WROVER_N16R2 + bool + select SOC_ESP32S2 + help + ESP32S2_WROVER_N16R2 + +config SOC_ESP32S2 + bool + select SOC_SERIES_ESP32S2 + help + ESP32S2 + +config SOC_SERIES + default "esp32s2" if SOC_SERIES_ESP32S2 + +config SOC + default "esp32s2" if SOC_SERIES_ESP32S2 + +config SOC_PART_NUMBER + default "ESP32S2" if SOC_ESP32S2 + default "ESP32S2_R2" if SOC_ESP32S2_R2 + default "ESP32S2_FH2" if SOC_ESP32S2_FH2 + default "ESP32S2_FH4" if SOC_ESP32S2_FH4 + default "ESP32S2_FN4R2" if SOC_ESP32S2_FN4R2 + default "ESP32S2_SOLO_N4" if SOC_ESP32S2_SOLO_N4 + default "ESP32S2_SOLO_N8" if SOC_ESP32S2_SOLO_N8 + default "ESP32S2_SOLO_N16" if SOC_ESP32S2_SOLO_N16 + default "ESP32S2_SOLO_N4R2" if SOC_ESP32S2_SOLO_N4R2 + default "ESP32S2_MINI_N4" if SOC_ESP32S2_MINI_N4 + default "ESP32S2_MINI_N4R2" if SOC_ESP32S2_MINI_N4R2 + default "ESP32S2_WROOM" if SOC_ESP32S2_WROOM + default "ESP32S2_WROVER_N4R2" if SOC_ESP32S2_WROVER_N4R2 + default "ESP32S2_WROVER_N8R2" if SOC_ESP32S2_WROVER_N8R2 + default "ESP32S2_WROVER_N16R2" if SOC_ESP32S2_WROVER_N16R2 + +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32s2" if SOC_SERIES_ESP32S2 diff --git a/soc/xtensa/espressif_esp32/esp32s2/default.ld b/soc/espressif/esp32s2/default.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/default.ld rename to soc/espressif/esp32s2/default.ld diff --git a/soc/xtensa/espressif_esp32/esp32s2/loader.c b/soc/espressif/esp32s2/loader.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/loader.c rename to soc/espressif/esp32s2/loader.c diff --git a/soc/xtensa/espressif_esp32/esp32s2/mcuboot.ld b/soc/espressif/esp32s2/mcuboot.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/mcuboot.ld rename to soc/espressif/esp32s2/mcuboot.ld diff --git a/soc/xtensa/espressif_esp32/esp32s2/newlib_fix.c b/soc/espressif/esp32s2/newlib_fix.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/newlib_fix.c rename to soc/espressif/esp32s2/newlib_fix.c diff --git a/soc/xtensa/espressif_esp32/esp32s2/pinctrl_soc.h b/soc/espressif/esp32s2/pinctrl_soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/pinctrl_soc.h rename to soc/espressif/esp32s2/pinctrl_soc.h diff --git a/soc/xtensa/espressif_esp32/esp32s2/power.c b/soc/espressif/esp32s2/power.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/power.c rename to soc/espressif/esp32s2/power.c diff --git a/soc/xtensa/espressif_esp32/esp32s2/poweroff.c b/soc/espressif/esp32s2/poweroff.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/poweroff.c rename to soc/espressif/esp32s2/poweroff.c diff --git a/soc/xtensa/espressif_esp32/esp32s2/soc.c b/soc/espressif/esp32s2/soc.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/soc.c rename to soc/espressif/esp32s2/soc.c diff --git a/soc/xtensa/espressif_esp32/esp32s2/soc.h b/soc/espressif/esp32s2/soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/soc.h rename to soc/espressif/esp32s2/soc.h diff --git a/soc/xtensa/espressif_esp32/esp32s2/soc_cache.c b/soc/espressif/esp32s2/soc_cache.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/soc_cache.c rename to soc/espressif/esp32s2/soc_cache.c diff --git a/soc/espressif/esp32s3/CMakeLists.txt b/soc/espressif/esp32s3/CMakeLists.txt new file mode 100644 index 00000000000..75b9f0a3d7e --- /dev/null +++ b/soc/espressif/esp32s3/CMakeLists.txt @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_ESP32S3_APPCPU) + zephyr_sources(soc_appcpu.c) +else() + zephyr_sources( + soc.c + soc_cache.c + loader.c + esp32s3-mp.c + ) +endif() + +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) + +# get flash size to use in esptool as string +math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") + +if(CONFIG_BOOTLOADER_ESP_IDF) + include(ExternalProject) + + ## we use hello-world project, but I think any can be used. + set(espidf_components_dir ${ESP_IDF_PATH}/components) + set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) + set(espidf_build_dir ${espidf_prefix}/build) + + ExternalProject_Add( + EspIdfBootloader + PREFIX ${espidf_prefix} + SOURCE_DIR ${espidf_components_dir}/bootloader/subproject + BINARY_DIR ${espidf_build_dir}/bootloader + CONFIGURE_COMMAND + ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} + -S ${espidf_components_dir}/bootloader/subproject + -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} + -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} + -DPYTHON=${PYTHON_EXECUTABLE} + BUILD_COMMAND + ${CMAKE_COMMAND} --build . + INSTALL_COMMAND "" # This particular build system has no install command + ) + + ExternalProject_Add( + EspPartitionTable + SOURCE_DIR ${espidf_components_dir}/partition_table + BINARY_DIR ${espidf_build_dir} + CONFIGURE_COMMAND "" + BUILD_COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q + --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin + INSTALL_COMMAND "" + ) + + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + add_dependencies(app EspIdfBootloader EspPartitionTable) + + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + +endif() + +if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + ARGS --chip esp32s3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) + endif() + + if(CONFIG_MCUBOOT) + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") + endif() +endif() + +## When building for APPCPU +if(CONFIG_SOC_ESP32S3_APPCPU) + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py + ARGS -i ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c + -a "esp32s3_appcpu_fw_array") + endif() +else() + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + # get code-partition slot0 address + dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") + dt_reg_addr(img_0_off PATH ${dts_partition_path}) + + # get code-partition boot address + dt_nodelabel(dts_partition_path NODELABEL "boot_partition") + dt_reg_addr(boot_off PATH ${dts_partition_path}) + + board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") + + board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") +endif() + +if(CONFIG_MCUBOOT) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_ESP32S3_APPCPU) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "") +else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") +endif() diff --git a/soc/espressif/esp32s3/Kconfig b/soc/espressif/esp32s3/Kconfig new file mode 100644 index 00000000000..70fcfbb9144 --- /dev/null +++ b/soc/espressif/esp32s3/Kconfig @@ -0,0 +1,313 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32S3 + select XTENSA + select DYNAMIC_INTERRUPTS + select ARCH_SUPPORTS_COREDUMP + select CLOCK_CONTROL + select PINCTRL + select XIP if !MCUBOOT + select HAS_ESPRESSIF_HAL + select CPU_HAS_FPU + +if SOC_SERIES_ESP32S3 + +config IDF_TARGET_ESP32S3 + bool "ESP32S3 as target SOC" + default y + +config ESP32S3_APPCPU_IRAM + hex "ESP32S3 APPCPU IRAM size" + depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU + default 0x20000 + help + Defines APPCPU IRAM area in bytes. + +config ESP32S3_APPCPU_DRAM + hex "ESP32S3 APPCPU DRAM size" + depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU + default 0x10000 + help + Defines APPCPU DRAM area in bytes. + +config SOC_ESP32S3_PROCPU + bool + help + This hidden configuration defines that build is targeted for PROCPU (core 0). + +config SOC_ESP32S3_APPCPU + bool + help + This hidden configuration defines that build is targeted for APPCPU (core 1). + +config SOC_ENABLE_APPCPU + bool + default y + depends on IPM && SOC_ESP32S3_PROCPU + help + This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled. + +choice ESP32S3_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32S3_RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + config ESP32S3_RTC_CLK_SRC_INT_RC + bool "Internal 150kHz RC oscillator" + config ESP32S3_RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + config ESP32S3_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XP pin" + select ESP_SYSTEM_RTC_EXT_OSC + config ESP32S3_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" +endchoice + +config ESP32S3_RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 + default 1024 if ESP32S3_RTC_CLK_SRC_INT_RC + range 0 27000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 + range 0 32766 if ESP32S3_RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +choice ESP32_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or + derived from a single base MAC address. If the number of universal MAC addresses is four, + all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally + administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) + to the final octet of the base MAC address. If the number of universal MAC addresses is two, + only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. + These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. + The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. + These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. + When using the default (Espressif-assigned) base MAC address, either setting can be used. + When using a custom universal MAC address range, the correct setting will depend on the + allocation of MAC addresses in this range (either 2 or 4 per device.) + +config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_BT + +config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + bool "Four" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + select ESP_MAC_ADDR_UNIVERSE_BT + select ESP_MAC_ADDR_UNIVERSE_ETH + +endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES + +config ESP_MAC_ADDR_UNIVERSE_WIFI_AP + bool + +config ESP_MAC_ADDR_UNIVERSE_WIFI_STA + bool + +config ESP_MAC_ADDR_UNIVERSE_BT + bool + +config ESP_MAC_ADDR_UNIVERSE_ETH + bool + +config ESP32_UNIVERSAL_MAC_ADDRESSES + int + default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + +config ESP32_PHY_MAX_WIFI_TX_POWER + int "Max WiFi/BLE TX power (dBm)" + range 10 20 + default 20 + help + Set maximum transmit power for WiFi radio. Actual transmit power for high + data rates may be lower than this setting. + +config ESP32_PHY_MAX_TX_POWER + int + default ESP32_PHY_MAX_WIFI_TX_POWER + +menu "Cache config" + +choice ESP32S3_INSTRUCTION_CACHE_SIZE + prompt "Instruction cache size" + default ESP32S3_INSTRUCTION_CACHE_16KB + help + Instruction cache size to be set on application startup. + If you use 16KB instruction cache rather than 32KB instruction cache, + then the other 16KB will be managed by heap allocator. + + config ESP32S3_INSTRUCTION_CACHE_16KB + bool "16KB" + config ESP32S3_INSTRUCTION_CACHE_32KB + bool "32KB" +endchoice + +config ESP32S3_INSTRUCTION_CACHE_SIZE + hex + default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB + default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB + +choice ESP32S3_ICACHE_ASSOCIATED_WAYS + prompt "Instruction cache associated ways" + default ESP32S3_INSTRUCTION_CACHE_8WAYS + help + Instruction cache associated ways to be set on application startup. + + config ESP32S3_INSTRUCTION_CACHE_4WAYS + bool "4 ways" + config ESP32S3_INSTRUCTION_CACHE_8WAYS + bool "8 ways" +endchoice + +config ESP32S3_ICACHE_ASSOCIATED_WAYS + int + default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS + default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS + +choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE + prompt "Instruction cache line size" + default ESP32S3_INSTRUCTION_CACHE_LINE_32B + help + Instruction cache line size to be set on application startup. + + config ESP32S3_INSTRUCTION_CACHE_LINE_16B + bool "16 Bytes" + depends on ESP32S3_INSTRUCTION_CACHE_16KB + config ESP32S3_INSTRUCTION_CACHE_LINE_32B + bool "32 Bytes" +endchoice + +config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE + int + default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B + default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B + +config ESP32S3_INSTRUCTION_CACHE_WRAP + bool "Define instruction cache wrap mode" + help + If enabled, instruction cache will use wrap mode to read spi flash or spi ram. + The wrap length equals to ESP32S3_INSTRUCTION_CACHE_LINE_SIZE. + However, it depends on complex conditions. + +choice ESP32S3_DATA_CACHE_SIZE + prompt "Data cache size" + default ESP32S3_DATA_CACHE_32KB + help + Data cache size to be set on application startup. + If you use 32KB data cache rather than 64KB data cache, + the other 32KB will be added to the heap. + + config ESP32S3_DATA_CACHE_16KB + bool "16KB" + config ESP32S3_DATA_CACHE_32KB + bool "32KB" + config ESP32S3_DATA_CACHE_64KB + bool "64KB" +endchoice + +config ESP32S3_DATA_CACHE_SIZE + hex + # For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup + default 0x8000 if ESP32S3_DATA_CACHE_16KB + default 0x8000 if ESP32S3_DATA_CACHE_32KB + default 0x10000 if ESP32S3_DATA_CACHE_64KB + +choice ESP32S3_DCACHE_ASSOCIATED_WAYS + prompt "Data cache associated ways" + default ESP32S3_DATA_CACHE_8WAYS + help + Data cache associated ways to be set on application startup. + + config ESP32S3_DATA_CACHE_4WAYS + bool "4 ways" + config ESP32S3_DATA_CACHE_8WAYS + bool "8 ways" +endchoice + +config ESP32S3_DCACHE_ASSOCIATED_WAYS + int + default 4 if ESP32S3_DATA_CACHE_4WAYS + default 8 if ESP32S3_DATA_CACHE_8WAYS + +choice ESP32S3_DATA_CACHE_LINE_SIZE + prompt "Data cache line size" + default ESP32S3_DATA_CACHE_LINE_32B + help + Data cache line size to be set on application startup. + + config ESP32S3_DATA_CACHE_LINE_16B + bool "16 Bytes" + depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB + config ESP32S3_DATA_CACHE_LINE_32B + bool "32 Bytes" + config ESP32S3_DATA_CACHE_LINE_64B + bool "64 Bytes" +endchoice + +config ESP32S3_DATA_CACHE_LINE_SIZE + int + default 16 if ESP32S3_DATA_CACHE_LINE_16B + default 32 if ESP32S3_DATA_CACHE_LINE_32B + default 64 if ESP32S3_DATA_CACHE_LINE_64B + +config ESP32S3_DATA_CACHE_WRAP + bool "Define data cache wrap mode" + help + If enabled, data cache will use wrap mode to read spi flash or spi ram. + The wrap length equals to ESP32S3_DATA_CACHE_LINE_SIZE. + However, it depends on complex conditions. + +config MAC_BB_PD + bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled" + depends on SOC_SERIES_ESP32S3 && TICKLESS_KERNEL + default n + help + If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered + down when PHY is disabled. Enabling this setting reduces power consumption + by a small amount but increases RAM use by approximat + +endmenu # Cache config + +menu "PSRAM Clock and CS IO for ESP32S3" + depends on ESP_SPIRAM + +config DEFAULT_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 30 + help + The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design. + +config DEFAULT_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 26 + help + The PSRAM CS IO can be any unused GPIO, please refer to your hardware design. + +endmenu # PSRAM clock and cs IO for ESP32S3 + +endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/Kconfig.defconfig b/soc/espressif/esp32s3/Kconfig.defconfig new file mode 100644 index 00000000000..07f719a0bcc --- /dev/null +++ b/soc/espressif/esp32s3/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S3 + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) + +endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/Kconfig.soc b/soc/espressif/esp32s3/Kconfig.soc new file mode 100644 index 00000000000..6c0c1896c37 --- /dev/null +++ b/soc/espressif/esp32s3/Kconfig.soc @@ -0,0 +1,146 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32S3 + bool + select SOC_FAMILY_ESPRESSIF_ESP32 + help + ESP32-S3 Series + +config SOC_ESP32S3_R2 + bool + select SOC_ESP32S3 + help + ESP32S3_R2 + +config SOC_ESP32S3_R8 + bool + select SOC_ESP32S3 + help + ESP32S3_R8 + +config SOC_ESP32S3_R8V + bool + select SOC_ESP32S3 + help + ESP32S3_R8V + +config SOC_ESP32S3_FN8 + bool + select SOC_ESP32S3 + help + ESP32S3_FN8 + +config SOC_ESP32S3_PICO_N8R2 + bool + select SOC_ESP32S3 + help + ESP32S3_PICO_N8R2 + +config SOC_ESP32S3_PICO_N8R8 + bool + select SOC_ESP32S3 + help + ESP32S3_PICO_N8R8 + +# SiP with flash and/or psram +config SOC_ESP32S3_MINI_N8 + bool + select SOC_ESP32S3 + help + ESP32S3_MINI_N8 + +config SOC_ESP32S3_MINI_N4R2 + bool + select SOC_ESP32S3 + help + ESP32S3_MINI_N4R2 + +config SOC_ESP32S3_WROOM_N4 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N4 + +config SOC_ESP32S3_WROOM_N8 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N8 + +config SOC_ESP32S3_WROOM_N16 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N16 + +config SOC_ESP32S3_WROOM_N4R8 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N4R8 + +config SOC_ESP32S3_WROOM_N8R8 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N8R8 + +config SOC_ESP32S3_WROOM_N16R8 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N16R8 + +config SOC_ESP32S3_WROOM_N4R2 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N4R2 + +config SOC_ESP32S3_WROOM_N8R2 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N8R2 + +config SOC_ESP32S3_WROOM_N16R2 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N16R2 + +config SOC_ESP32S3 + bool + select SOC_SERIES_ESP32S3 + help + ESP32S3 + +config SOC_SERIES + default "esp32s3" if SOC_SERIES_ESP32S3 + +config SOC + default "esp32s3" if SOC_SERIES_ESP32S3 + +config SOC_PART_NUMBER + default "ESP32S3_R2" if SOC_ESP32S3_R2 + default "ESP32S3_R8" if SOC_ESP32S3_R8 + default "ESP32S3_R8V" if SOC_ESP32S3_R8V + default "ESP32S3_FN8" if SOC_ESP32S3_FN8 + default "ESP32S3_PICO_N8R2" if SOC_ESP32S3_PICO_N8R2 + default "ESP32S3_PICO_N8R8" if SOC_ESP32S3_PICO_N8R8 + default "ESP32S3_MINI_N8" if SOC_ESP32S3_MINI_N8 + default "ESP32S3_MINI_N4R2" if SOC_ESP32S3_MINI_N4R2 + default "ESP32S3_WROOM_N4" if SOC_ESP32S3_WROOM_N4 + default "ESP32S3_WROOM_N8" if SOC_ESP32S3_WROOM_N8 + default "ESP32S3_WROOM_N16" if SOC_ESP32S3_WROOM_N16 + default "ESP32S3_WROOM_N4R8" if SOC_ESP32S3_WROOM_N4R8 + default "ESP32S3_WROOM_N8R8" if SOC_ESP32S3_WROOM_N8R8 + default "ESP32S3_WROOM_N16R8" if SOC_ESP32S3_WROOM_N16R8 + default "ESP32S3_WROOM_N4R2" if SOC_ESP32S3_WROOM_N4R2 + default "ESP32S3_WROOM_N8R2" if SOC_ESP32S3_WROOM_N8R2 + default "ESP32S3_WROOM_N16R2" if SOC_ESP32S3_WROOM_N16R2 + +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32s3" if SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/default.ld b/soc/espressif/esp32s3/default.ld new file mode 100644 index 00000000000..7c8aff31767 --- /dev/null +++ b/soc/espressif/esp32s3/default.ld @@ -0,0 +1,693 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * Linker script for the ESP32S3 platform. + */ + +#include +#include +#include +#include + +#define SRAM_IRAM_START 0x40370000 +#define SRAM_DIRAM_I_START 0x40378000 +/* SRAM_IRAM_END is equivalent 2nd stage bootloader iram_loader_seg + start address (that should not be overlapped) */ +#define SRAM_IRAM_END 0x403BA000 +#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START) + +#define SRAM_DRAM_START 0x3FC88000 +#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET) +#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START) + +#define ICACHE_SIZE 0x8000 +#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) +#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) + +#define DCACHE_SIZE 0x10000 +#define SRAM_DRAM_ORG (SRAM_DRAM_START) + +#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE + +#define FLASH_CODE_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define RAMABLE_REGION dram0_0_seg +#define ROMABLE_REGION ROM + +#define EXT_RAM_ORG (0x3E000000 - CONFIG_ESP_SPIRAM_SIZE) + +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x800000 +#endif + +#ifdef CONFIG_BOOTLOADER_ESP_IDF +#define IROM_SEG_ORG 0x42000020 +#define IROM_SEG_LEN FLASH_SIZE-0x20 +#else +#define IROM_SEG_ORG 0x42000000 +#define IROM_SEG_LEN FLASH_SIZE +#endif + +#ifdef CONFIG_SOC_ENABLE_APPCPU +#define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM +#define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM +#else +#define APPCPU_IRAM_SIZE 0x0 +#define APPCPU_DRAM_SIZE 0x0 +#endif + +#define IROM_SEG_ALIGN 0x10000 + +/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. + * Executing directly from LMA is not possible. */ +#undef GROUP_ROM_LINK_IN +#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion + +MEMORY +{ + mcuboot_hdr (RX): org = 0x0, len = 0x20 + metadata (RX): org = 0x20, len = 0x20 + ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 + iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE - APPCPU_IRAM_SIZE + dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN - APPCPU_DRAM_SIZE + + irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN + + /* DROM is the first segment placed in generated binary. + * MCUboot binary for ESP32 has image header of 0x20 bytes. + * Additional load header of 0x20 bytes are appended to the image. + * Hence, an offset of 0x40 is added to DROM segment origin. + */ + drom0_0_seg(R): org = 0x3C000040, len = FLASH_SIZE - 0x40 + /** + * `extern_ram_seg` and `drom0_0_seg` share the same bus and the address region. + * so we allocate `extern_ram_seg` at the end of the address region. + */ +#if defined(CONFIG_ESP_SPIRAM) + ext_ram_seg(RWX): org = EXT_RAM_ORG, len = CONFIG_ESP_SPIRAM_SIZE +#endif + + /* RTC fast memory (executable). Persists over deep sleep. + */ + rtc_iram_seg(RWX): org = 0x600fe000, len = 0x2000 + + /* RTC fast memory (same block as above), viewed from data bus + */ + rtc_data_seg(RW): org = 0x600fe000, len = 0x2000 + + /* RTC slow memory (data accessible). Persists over deep sleep. + */ + rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 + +#ifdef CONFIG_GEN_ISR_TABLES + IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 +#endif +} + +/* Default entry point: */ +ENTRY(CONFIG_KERNEL_ENTRY) + +SECTIONS +{ + /* Reserve space for MCUboot header in the binary */ + .mcuboot_header : + { + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + } > mcuboot_hdr + .metadata : + { + /* Magic byte for load header */ + LONG(0xace637d3) + + /* Application entry point address */ + KEEP(*(.entry_addr)) + + /* IRAM metadata: + * - Destination address (VMA) for IRAM region + * - Flash offset (LMA) for start of IRAM region + * - Size of IRAM region + */ + LONG(ADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors)) + + /* DRAM metadata: + * - Destination address (VMA) for DRAM region + * - Flash offset (LMA) for start of DRAM region + * - Size of DRAM region + */ + LONG(ADDR(.dram0.data)) + LONG(LOADADDR(.dram0.data)) + LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) + } > metadata + + #include + + _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); + _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; + _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); + + /* NOTE: .rodata section should be the first section in the linker script and no + * other section should appear before .rodata section. This is the requirement + * to align ROM section to 64K page offset. + * Adding .rodata as first section helps to reduce size of generated binary by + * few kBs. + */ + SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(0x10)) + { + _rodata_reserved_start = ABSOLUTE(.); + _rodata_start = ABSOLUTE(.); + + *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ + *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ + + __rodata_region_start = ABSOLUTE(.); + . = ALIGN(4); + #include + + . = ALIGN(4); + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata) + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + *(.rodata_wlog) + *(.rodata_wlog*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + SECTION_PROLOGUE(_RODATA_SECTION_END,,ALIGN(0x10)) + { + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN(16); + _image_rodata_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + +#if defined(CONFIG_ESP_SPIRAM) + /* This section holds .ext_ram.bss data, and will be put in PSRAM */ + .ext_ram.bss (NOLOAD) : + { + _ext_ram_data_start = ABSOLUTE(.); + _ext_ram_bss_start = ABSOLUTE(.); + *(.ext_ram.bss*) + . = ALIGN(4); + _ext_ram_bss_end = ABSOLUTE(.); + } > ext_ram_seg + + .ext_ram_noinit (NOLOAD) : + { +#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) + *libdrivers__wifi.a:(.noinit .noinit.*) + *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) + *libsubsys__net__lib__config.a:(.noinit .noinit.*) + *libsubsys__net__ip.a:(.noinit .noinit.*) + *libsubsys__net.a:(.noinit .noinit.*) +#endif + _spiram_heap_start = ABSOLUTE(.); + . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; + + _ext_ram_data_end = ABSOLUTE(.); + } > ext_ram_seg +#endif + + /* Send .iram0 code to iram */ + .iram0.vectors : ALIGN(4) + { + _iram_start = ABSOLUTE(.); + /* Vectors go to IRAM */ + _init_start = ABSOLUTE(.); + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + _invalid_pc_placeholder = ABSOLUTE(.); + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + .iram0.text : ALIGN(4) + { + /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + *libesp32.a:panic.*(.literal .text .literal.* .text.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) + *libkernel.a:(.literal .text .literal.* .text.*) + *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) + *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) + *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) + *libzephyr.a:spiram*.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_timing*.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash*.*(.literal .text .literal.* .text.*) + *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) + *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) + *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) + *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) + *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) + *libc.a:*(.literal .text .literal.* .text.*) + *libphy.a:(.phyiram .phyiram.*) + *libgcov.a:(.literal .text .literal.* .text.*) + +#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) + *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) +#endif + +#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) + *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) + *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) +#endif + + . = ALIGN(4) + 16; + + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : + { + /* ESP32-S3 memprot requires 16B padding for possible CPU + * prefetch and 256B alignment for PMS split lines */ + . = ALIGN(16); + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + + /* This section is required to skip .iram0.text area because iram0_0_seg and + * dram0_0_seg reflect the same address space on different buses. + */ + .dram0.dummy (NOLOAD): + { + . = ALIGN (8); + . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM_DIRAM_I_START) - SRAM_DIRAM_I_START; + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Shared RAM */ + SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); /* required by bluetooth library */ + __bss_start = ABSOLUTE(.); + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + __bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + + SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) + { + . = ALIGN(8); + *(.noinit) + *(.noinit.*) + . = ALIGN(8) ; + } GROUP_LINK_IN(RAMABLE_REGION) + + .dram0.data : + { + . = ALIGN (8); + __data_start = ABSOLUTE(.); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + /* rodata for panic handler(libarch__xtensa__core.a) and all + * dependent functions should be placed in DRAM to avoid issue + * when flash cache is disabled */ + *libarch__xtensa__core.a:(.rodata .rodata.*) + *libkernel.a:fatal.*(.rodata .rodata.*) + *libkernel.a:init.*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:loader.*(.rodata .rodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ + #pragma push_macro("GROUP_ROM_LINK_IN") + #undef GROUP_ROM_LINK_IN + #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN + #include + #pragma pop_macro("GROUP_ROM_LINK_IN") + + .dram0.end : + { + . = ALIGN(4); + + #include + + . = ALIGN(4); + _end = ABSOLUTE(.); + __data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + _image_irom_start = LOADADDR(.flash.text); + _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; + _image_irom_vaddr = ADDR(.flash.text); + + .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN) + { + . = SIZEOF(_RODATA_SECTION_NAME); + . = ALIGN(IROM_SEG_ALIGN) + 0x20; + } GROUP_LINK_IN(FLASH_CODE_REGION) + + .flash.text : ALIGN(IROM_SEG_ALIGN) + { + _stext = .; + _text_start = ABSOLUTE(.); + +#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) + *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) +#endif + +#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) + *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) + *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) +#endif + + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + *(.literal .text .literal.* .text.*) + + /* CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) + + /* RTC fast memory holds RTC wake stub code, + * including from any source file named rtc_wake_stub*.c + */ + .rtc.text : + { + . = ALIGN(4); + _rtc_text_start = ABSOLUTE(.); + *(.rtc.literal .rtc.text) + *(.rtc.entry.text) + *rtc_wake_stub*.*(.literal .text .literal.* .text.*) + _rtc_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + + /* This section is required to skip rtc.text area because rtc_iram_seg and + * rtc_data_seg are reflect the same address space on different buses. + */ + .rtc.dummy : + { + _rtc_dummy_start = ABSOLUTE(.); + _rtc_fast_start = ABSOLUTE(.); + . = SIZEOF(.rtc.text); + _rtc_dummy_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) + + /* This section located in RTC FAST Memory area. + * It holds data marked with RTC_FAST_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_fast : + { + . = ALIGN(4); + _rtc_force_fast_start = ABSOLUTE(.); + + *(.rtc.force_fast .rtc.force_fast.*) + . = ALIGN(4) ; + _rtc_force_fast_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) + + /* RTC data section holds RTC wake stub + * data/rodata, including from any source file + * named rtc_wake_stub*.c and the data marked with + * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + *(.rtc.data) + *(.rtc.rodata) + *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) + _rtc_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.*(.bss .bss.*) + *rtc_wake_stub*.*(COMMON) + + *(.rtc.data) + *(.rtc.rodata) + + _rtc_bss_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.*(.bss .bss.*) + *rtc_wake_stub*.*(COMMON) + + _rtc_bss_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* This section holds data that should not be initialized at power up + * and will be retained during deep sleep. + * User data marked with RTC_NOINIT_ATTR will be placed + * into this section. See the file "esp_attr.h" for more information. + */ + .rtc_noinit (NOLOAD): + { + . = ALIGN(4); + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* Get size of rtc slow data based on rtc_data_location alias */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + _rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start); + + ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") + ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") + +#ifdef CONFIG_GEN_ISR_TABLES +#include +#endif + +_heap_sentry = 0x3fceb910; + +#include + + .xtensa.info 0 : { *(.xtensa.info) } + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } + +} + +ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), + "IRAM0 segment data does not fit.") + +#if defined(CONFIG_ESP_SPIRAM) +ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), + "External SPIRAM overflowed.") +#endif /* CONFIG_ESP_SPIRAM */ diff --git a/soc/xtensa/espressif_esp32/esp32s3/default_appcpu.ld b/soc/espressif/esp32s3/default_appcpu.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/default_appcpu.ld rename to soc/espressif/esp32s3/default_appcpu.ld diff --git a/soc/xtensa/espressif_esp32/esp32s3/esp32s3-mp.c b/soc/espressif/esp32s3/esp32s3-mp.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/esp32s3-mp.c rename to soc/espressif/esp32s3/esp32s3-mp.c diff --git a/soc/xtensa/espressif_esp32/esp32s3/loader.c b/soc/espressif/esp32s3/loader.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/loader.c rename to soc/espressif/esp32s3/loader.c diff --git a/soc/xtensa/espressif_esp32/esp32s3/mcuboot.ld b/soc/espressif/esp32s3/mcuboot.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/mcuboot.ld rename to soc/espressif/esp32s3/mcuboot.ld diff --git a/soc/xtensa/espressif_esp32/esp32s3/newlib_fix.c b/soc/espressif/esp32s3/newlib_fix.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/newlib_fix.c rename to soc/espressif/esp32s3/newlib_fix.c diff --git a/soc/xtensa/espressif_esp32/esp32s3/pinctrl_soc.h b/soc/espressif/esp32s3/pinctrl_soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/pinctrl_soc.h rename to soc/espressif/esp32s3/pinctrl_soc.h diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c new file mode 100644 index 00000000000..d41732db14e --- /dev/null +++ b/soc/espressif/esp32s3/soc.c @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Include esp-idf headers first to avoid redefining BIT() macro */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "esp_private/system_internal.h" +#include "esp32s3/rom/cache.h" +#include "esp32s3/rom/rtc.h" +#include "soc/syscon_reg.h" +#include "hal/soc_ll.h" +#include "hal/wdt_hal.h" +#include "soc/cpu.h" +#include "soc/gpio_periph.h" +#include "esp_spi_flash.h" +#include "esp_err.h" +#include "esp_timer.h" +#include "esp_app_format.h" +#include "esp_clk_internal.h" + +#include "esp32s3/spiram.h" + +#ifdef CONFIG_MCUBOOT +#include "bootloader_init.h" +#endif /* CONFIG_MCUBOOT */ +#include + +#if CONFIG_ESP_SPIRAM +extern int _ext_ram_bss_start; +extern int _ext_ram_bss_end; +#endif + +extern void z_cstart(void); +extern void esp_reset_reason_init(void); + +#if CONFIG_SOC_ENABLE_APPCPU +extern const unsigned char esp32s3_appcpu_fw_array[]; + +void IRAM_ATTR esp_start_appcpu(void) +{ + esp_image_header_t *header = (esp_image_header_t *)&esp32s3_appcpu_fw_array[0]; + esp_image_segment_header_t *segment = + (esp_image_segment_header_t *)&esp32s3_appcpu_fw_array[sizeof(esp_image_header_t)]; + uint8_t *segment_payload; + uint32_t entry_addr = header->entry_addr; + uint32_t idx = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t); + + for (int i = 0; i < header->segment_count; i++) { + segment_payload = (uint8_t *)&esp32s3_appcpu_fw_array[idx]; + + if (segment->load_addr >= SOC_IRAM_LOW && segment->load_addr < SOC_IRAM_HIGH) { + /* IRAM segment only accepts 4 byte access, avoid memcpy usage here */ + volatile uint32_t *src = (volatile uint32_t *)segment_payload; + volatile uint32_t *dst = (volatile uint32_t *)segment->load_addr; + + for (int i = 0; i < segment->data_len / 4; i++) { + dst[i] = src[i]; + } + + } else if (segment->load_addr >= SOC_DRAM_LOW && + segment->load_addr < SOC_DRAM_HIGH) { + memcpy((void *)segment->load_addr, (const void *)segment_payload, + segment->data_len); + } + + idx += segment->data_len; + segment = (esp_image_segment_header_t *)&esp32s3_appcpu_fw_array[idx]; + idx += sizeof(esp_image_segment_header_t); + } + + esp_appcpu_start((void *)entry_addr); +} +#endif /* CONFIG_SOC_ENABLE_APPCPU */ + +#ifndef CONFIG_MCUBOOT +/* + * This function is a container for SoC patches + * that needs to be applied during the startup. + */ +static void IRAM_ATTR esp_errata(void) +{ + /* Handle the clock gating fix */ + REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); + /* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING + * signals to ensure that the App core stops running in single-core mode. + */ + REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL); + REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); + + /* Handle the Dcache case following the IDF startup code */ +#if CONFIG_ESP32S3_DATA_CACHE_16KB + Cache_Invalidate_DCache_All(); + Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000); +#endif +} +#endif /* CONFIG_MCUBOOT */ + +/* + * This is written in C rather than assembly since, during the port bring up, + * Zephyr is being booted by the Espressif bootloader. With it, the C stack + * is already set up. + */ +void IRAM_ATTR __esp_platform_start(void) +{ + extern uint32_t _init_start; + + /* Move the exception vector table to IRAM. */ + __asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start)); + + z_bss_zero(); + + /* Disable normal interrupts. */ + __asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); + + /* Initialize the architecture CPU pointer. Some of the + * initialization code wants a valid _current before + * arch_kernel_init() is invoked. + */ + __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); + +#ifdef CONFIG_MCUBOOT + /* MCUboot early initialisation. */ + if (bootloader_init()) { + abort(); + } +#else + /* Configure the mode of instruction cache : cache size, cache line size. */ + esp_config_instruction_cache_mode(); + + /* If we need use SPIRAM, we should use data cache. + * Configure the mode of data : cache size, cache line size. + */ + esp_config_data_cache_mode(); + + /* Apply SoC patches */ + esp_errata(); + +#if CONFIG_ESP_SPIRAM + esp_err_t err = esp_spiram_init(); + + if (err != ESP_OK) { + printk("Failed to Initialize external RAM, aborting.\n"); + abort(); + } + + esp_spiram_init_cache(); + if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { + printk("External RAM size is less than configured, aborting.\n"); + abort(); + } + + if (!esp_spiram_test()) { + printk("External RAM failed memory test!\n"); + abort(); + } + + memset(&_ext_ram_bss_start, 0, + (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); + +#endif /* CONFIG_ESP_SPIRAM */ + + /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence + * related issues in application. Hence disable that as we are about to start + * Zephyr environment. + */ + wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; + + wdt_hal_write_protect_disable(&rtc_wdt_ctx); + wdt_hal_disable(&rtc_wdt_ctx); + wdt_hal_write_protect_enable(&rtc_wdt_ctx); + + esp_reset_reason_init(); + + esp_clk_init(); + + esp_timer_early_init(); + +#if CONFIG_SOC_ENABLE_APPCPU + /* start the ESP32S3 APP CPU */ + esp_start_appcpu(); +#endif + +#if CONFIG_SOC_FLASH_ESP32 + spi_flash_guard_set(&g_flash_guard_default_ops); +#endif +#endif /* CONFIG_MCUBOOT */ + + esp_intr_initialize(); + + /* Start Zephyr */ + z_cstart(); + + CODE_UNREACHABLE; +} + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int IRAM_ATTR arch_printk_char_out(int c) +{ + if (c == '\n') { + esp_rom_uart_tx_one_char('\r'); + } + esp_rom_uart_tx_one_char(c); + return 0; +} + +void sys_arch_reboot(int type) +{ + esp_restart_noos(); +} + +void IRAM_ATTR esp_restart_noos(void) +{ + /* disable interrupts */ + z_xt_ints_off(0xFFFFFFFF); + + /* enable RTC watchdog for 1 second */ + wdt_hal_context_t wdt_ctx; + uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); + + wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false); + wdt_hal_write_protect_disable(&wdt_ctx); + wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); + wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); + + /* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */ + wdt_hal_set_flashboot_en(&wdt_ctx, true); + wdt_hal_write_protect_enable(&wdt_ctx); + + /* disable TG0/TG1 watchdogs */ + wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; + + wdt_hal_write_protect_disable(&wdt0_context); + wdt_hal_disable(&wdt0_context); + wdt_hal_write_protect_enable(&wdt0_context); + + wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; + + wdt_hal_write_protect_disable(&wdt1_context); + wdt_hal_disable(&wdt1_context); + wdt_hal_write_protect_enable(&wdt1_context); + + /* Flush any data left in UART FIFOs */ + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + esp_rom_uart_tx_wait_idle(2); + + /* Disable cache */ + Cache_Disable_ICache(); + Cache_Disable_DCache(); + + const uint32_t core_id = cpu_hal_get_core_id(); +#if CONFIG_SMP + const uint32_t other_core_id = (core_id == 0) ? 1 : 0; + + soc_ll_reset_core(other_core_id); + soc_ll_stall_core(other_core_id); +#endif + + /* 2nd stage bootloader reconfigures SPI flash signals. */ + /* Reset them to the defaults expected by ROM */ + WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); + + /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ + SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, + SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST | + SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_SDIO_HOST_RST | + SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | + SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST); + REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); + + /* Reset timer/spi/uart */ + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | + SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); + + /* Reset DMA */ + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); + + SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + + rtc_clk_cpu_freq_set_xtal(); + + /* Reset CPUs */ + if (core_id == 0) { + /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ + soc_ll_reset_core(1); + soc_ll_reset_core(0); + } else { + /* Running on APP CPU: need to reset PRO CPU and unstall it, */ + /* then reset APP CPU */ + soc_ll_reset_core(0); + soc_ll_stall_core(0); + soc_ll_reset_core(1); + } + + while (true) { + ; + } +} diff --git a/soc/xtensa/espressif_esp32/esp32s3/soc.h b/soc/espressif/esp32s3/soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/soc.h rename to soc/espressif/esp32s3/soc.h diff --git a/soc/xtensa/espressif_esp32/esp32s3/soc_appcpu.c b/soc/espressif/esp32s3/soc_appcpu.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/soc_appcpu.c rename to soc/espressif/esp32s3/soc_appcpu.c diff --git a/soc/xtensa/espressif_esp32/esp32s3/soc_cache.c b/soc/espressif/esp32s3/soc_cache.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/soc_cache.c rename to soc/espressif/esp32s3/soc_cache.c diff --git a/soc/espressif/soc.yml b/soc/espressif/soc.yml new file mode 100644 index 00000000000..13f6092e311 --- /dev/null +++ b/soc/espressif/soc.yml @@ -0,0 +1,21 @@ +family: +- name: espressif_esp32 + series: + - name: esp32 + socs: + - name: esp32 + cpuclusters: + - name: procpu + - name: appcpu + - name: esp32s2 + socs: + - name: esp32s2 + - name: esp32s3 + socs: + - name: esp32s3 + cpuclusters: + - name: procpu + - name: appcpu + - name: esp32c3 + socs: + - name: esp32c3 diff --git a/soc/gaisler/Kconfig b/soc/gaisler/Kconfig new file mode 100644 index 00000000000..2a8eb9b88e0 --- /dev/null +++ b/soc/gaisler/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SPARC_CASA + bool + default y if SPARC diff --git a/soc/gaisler/Kconfig.soc b/soc/gaisler/Kconfig.soc new file mode 100644 index 00000000000..000f2a774af --- /dev/null +++ b/soc/gaisler/Kconfig.soc @@ -0,0 +1,5 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SPARC_LEON + bool diff --git a/soc/gaisler/gr716a/CMakeLists.txt b/soc/gaisler/gr716a/CMakeLists.txt new file mode 100644 index 00000000000..f33677ad301 --- /dev/null +++ b/soc/gaisler/gr716a/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(../leon3/idle.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/gaisler/gr716a/Kconfig b/soc/gaisler/gr716a/Kconfig new file mode 100644 index 00000000000..6613952b104 --- /dev/null +++ b/soc/gaisler/gr716a/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SOC_GR716A + select SPARC + select SOC_SPARC_LEON + select CPU_HAS_FPU + +rsource "../Kconfig" diff --git a/soc/gaisler/gr716a/Kconfig.defconfig b/soc/gaisler/gr716a/Kconfig.defconfig new file mode 100644 index 00000000000..c6913964fd8 --- /dev/null +++ b/soc/gaisler/gr716a/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +if SOC_GR716A + +config SPARC_NWIN + default 31 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 50000000 + +if FLASH + +config SPI + default y + +config SPI_NOR + default y + +config SPI_GRLIB_SPIMCTRL + default y + +endif + +endif diff --git a/soc/gaisler/gr716a/Kconfig.soc b/soc/gaisler/gr716a/Kconfig.soc new file mode 100644 index 00000000000..0eded2f8419 --- /dev/null +++ b/soc/gaisler/gr716a/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SOC_GR716A + bool + +config SOC + default "gr716a" if SOC_GR716A + +rsource "../Kconfig.soc" diff --git a/soc/sparc/gr716a/linker.ld b/soc/gaisler/gr716a/linker.ld similarity index 100% rename from soc/sparc/gr716a/linker.ld rename to soc/gaisler/gr716a/linker.ld diff --git a/soc/sparc/gr716a/soc.h b/soc/gaisler/gr716a/soc.h similarity index 100% rename from soc/sparc/gr716a/soc.h rename to soc/gaisler/gr716a/soc.h diff --git a/soc/gaisler/gr716a/soc.yml b/soc/gaisler/gr716a/soc.yml new file mode 100644 index 00000000000..e61d3a2a188 --- /dev/null +++ b/soc/gaisler/gr716a/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: gr716a diff --git a/soc/gaisler/leon3/CMakeLists.txt b/soc/gaisler/leon3/CMakeLists.txt new file mode 100644 index 00000000000..7b5ea47c82d --- /dev/null +++ b/soc/gaisler/leon3/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(idle.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/gaisler/leon3/Kconfig b/soc/gaisler/leon3/Kconfig new file mode 100644 index 00000000000..106bf077569 --- /dev/null +++ b/soc/gaisler/leon3/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LEON3 + select SPARC + select SOC_SPARC_LEON + +rsource "../Kconfig" diff --git a/soc/gaisler/leon3/Kconfig.defconfig b/soc/gaisler/leon3/Kconfig.defconfig new file mode 100644 index 00000000000..d93676360d1 --- /dev/null +++ b/soc/gaisler/leon3/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +if SOC_LEON3 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 40000000 + +endif diff --git a/soc/gaisler/leon3/Kconfig.soc b/soc/gaisler/leon3/Kconfig.soc new file mode 100644 index 00000000000..e0e9222c456 --- /dev/null +++ b/soc/gaisler/leon3/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LEON3 + bool + +config SOC + default "leon3" if SOC_LEON3 + +rsource "../Kconfig.soc" diff --git a/soc/sparc/leon3/idle.c b/soc/gaisler/leon3/idle.c similarity index 100% rename from soc/sparc/leon3/idle.c rename to soc/gaisler/leon3/idle.c diff --git a/soc/sparc/leon3/linker.ld b/soc/gaisler/leon3/linker.ld similarity index 100% rename from soc/sparc/leon3/linker.ld rename to soc/gaisler/leon3/linker.ld diff --git a/soc/sparc/leon3/soc.h b/soc/gaisler/leon3/soc.h similarity index 100% rename from soc/sparc/leon3/soc.h rename to soc/gaisler/leon3/soc.h diff --git a/soc/gaisler/leon3/soc.yml b/soc/gaisler/leon3/soc.yml new file mode 100644 index 00000000000..f780ea08f81 --- /dev/null +++ b/soc/gaisler/leon3/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: leon3 diff --git a/soc/arm/gd_gd32/CMakeLists.txt b/soc/gd/gd32/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/CMakeLists.txt rename to soc/gd/gd32/CMakeLists.txt diff --git a/soc/gd/gd32/Kconfig b/soc/gd/gd32/Kconfig new file mode 100644 index 00000000000..a94d20b3b1a --- /dev/null +++ b/soc/gd/gd32/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_GD_GD32 + select HAS_GD32_HAL + select BUILD_OUTPUT_HEX + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +if SOC_FAMILY_GD_GD32 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_GD_GD32 diff --git a/soc/gd/gd32/Kconfig.defconfig b/soc/gd/gd32/Kconfig.defconfig new file mode 100644 index 00000000000..345f14c0629 --- /dev/null +++ b/soc/gd/gd32/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_GD_GD32 + +rsource "*/Kconfig.defconfig.series" + +config PINCTRL + default y + +config RESET + default y + +config CLOCK_CONTROL + default y + +endif # SOC_FAMILY_GD_GD32 diff --git a/soc/gd/gd32/Kconfig.soc b/soc/gd/gd32/Kconfig.soc new file mode 100644 index 00000000000..3b4f6c616b6 --- /dev/null +++ b/soc/gd/gd32/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_GD_GD32 + bool + +config SOC_FAMILY + default "gd_gd32" if SOC_FAMILY_GD_GD32 + +rsource "*/Kconfig.soc" diff --git a/soc/arm/gd_gd32/common/CMakeLists.txt b/soc/gd/gd32/common/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/common/CMakeLists.txt rename to soc/gd/gd32/common/CMakeLists.txt diff --git a/include/zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h b/soc/gd/gd32/common/pinctrl_soc.h similarity index 100% rename from include/zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h rename to soc/gd/gd32/common/pinctrl_soc.h diff --git a/soc/arm/gd_gd32/gd32a50x/CMakeLists.txt b/soc/gd/gd32/gd32a50x/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32a50x/CMakeLists.txt rename to soc/gd/gd32/gd32a50x/CMakeLists.txt diff --git a/soc/gd/gd32/gd32a50x/Kconfig b/soc/gd/gd32/gd32a50x/Kconfig new file mode 100644 index 00000000000..8cd903e86ad --- /dev/null +++ b/soc/gd/gd32/gd32a50x/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32A50X + select ARM + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select GD32_HAS_AF_PINMUX + select GD32_HAS_IRC_40K + select PLATFORM_SPECIFIC_INIT diff --git a/soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.gd32a503 b/soc/gd/gd32/gd32a50x/Kconfig.defconfig.gd32a503 similarity index 85% rename from soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.gd32a503 rename to soc/gd/gd32/gd32a50x/Kconfig.defconfig.gd32a503 index a714d56cb61..6b54ab05e61 100644 --- a/soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.gd32a503 +++ b/soc/gd/gd32/gd32a50x/Kconfig.defconfig.gd32a503 @@ -1,11 +1,12 @@ # Copyright (c) 2022 YuLong Yao # SPDX-License-Identifier: Apache-2.0 -config SOC - default "gd32a503" +if SOC_GD32A503 config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) config NUM_IRQS default 82 + +endif # SOC_GD32A503 diff --git a/soc/gd/gd32/gd32a50x/Kconfig.defconfig.series b/soc/gd/gd32/gd32a50x/Kconfig.defconfig.series new file mode 100644 index 00000000000..f54d52b13c9 --- /dev/null +++ b/soc/gd/gd32/gd32a50x/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32A50X + +config SOC_SERIES + default "gd32a50x" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32A50X diff --git a/soc/gd/gd32/gd32a50x/Kconfig.soc b/soc/gd/gd32/gd32a50x/Kconfig.soc new file mode 100644 index 00000000000..26345d8cbf0 --- /dev/null +++ b/soc/gd/gd32/gd32a50x/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32A50X + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32A50X MCU series + +config SOC_SERIES + default "gd32a50x" if SOC_SERIES_GD32A50X + +config SOC_GD32A503 + bool + select SOC_SERIES_GD32A50X + +config SOC + default "gd32a503" if SOC_GD32A503 diff --git a/soc/arm/gd_gd32/gd32a50x/gd32_regs.h b/soc/gd/gd32/gd32a50x/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32a50x/gd32_regs.h rename to soc/gd/gd32/gd32a50x/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32a50x/soc.c b/soc/gd/gd32/gd32a50x/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32a50x/soc.c rename to soc/gd/gd32/gd32a50x/soc.c diff --git a/soc/arm/gd_gd32/gd32a50x/soc.h b/soc/gd/gd32/gd32a50x/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32a50x/soc.h rename to soc/gd/gd32/gd32a50x/soc.h diff --git a/soc/arm/gd_gd32/gd32e10x/CMakeLists.txt b/soc/gd/gd32/gd32e10x/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32e10x/CMakeLists.txt rename to soc/gd/gd32/gd32e10x/CMakeLists.txt diff --git a/soc/gd/gd32/gd32e10x/Kconfig b/soc/gd/gd32/gd32e10x/Kconfig new file mode 100644 index 00000000000..6b83464fd71 --- /dev/null +++ b/soc/gd/gd32/gd32e10x/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32E10X + select ARM + select CPU_HAS_FPU + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select GD32_HAS_AFIO_PINMUX + select GD32_HAS_IRC_40K diff --git a/soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.gd32e103 b/soc/gd/gd32/gd32e10x/Kconfig.defconfig.gd32e103 similarity index 85% rename from soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.gd32e103 rename to soc/gd/gd32/gd32e10x/Kconfig.defconfig.gd32e103 index 38dfedb9cd0..d1b9801bb9a 100644 --- a/soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.gd32e103 +++ b/soc/gd/gd32/gd32e10x/Kconfig.defconfig.gd32e103 @@ -1,11 +1,12 @@ # Copyright (c) 2021 YuLong Yao # SPDX-License-Identifier: Apache-2.0 -config SOC - default "gd32e103" +if SOC_GD32E103 config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) config NUM_IRQS default 83 + +endif # SOC_GD32E103 diff --git a/soc/gd/gd32/gd32e10x/Kconfig.defconfig.series b/soc/gd/gd32/gd32e10x/Kconfig.defconfig.series new file mode 100644 index 00000000000..2aec533c23c --- /dev/null +++ b/soc/gd/gd32/gd32e10x/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32E10X + +config SOC_SERIES + default "gd32e10x" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32E10X diff --git a/soc/gd/gd32/gd32e10x/Kconfig.soc b/soc/gd/gd32/gd32e10x/Kconfig.soc new file mode 100644 index 00000000000..8108580bba6 --- /dev/null +++ b/soc/gd/gd32/gd32e10x/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32E10X + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32E10X MCU series + +config SOC_SERIES + default "gd32e10x" if SOC_SERIES_GD32E10X + +config SOC_GD32E103 + bool + select SOC_SERIES_GD32E10X + +config SOC + default "gd32e103" if SOC_GD32E103 diff --git a/soc/arm/gd_gd32/gd32e10x/gd32_regs.h b/soc/gd/gd32/gd32e10x/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32e10x/gd32_regs.h rename to soc/gd/gd32/gd32e10x/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32e10x/soc.c b/soc/gd/gd32/gd32e10x/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32e10x/soc.c rename to soc/gd/gd32/gd32e10x/soc.c diff --git a/soc/arm/gd_gd32/gd32e10x/soc.h b/soc/gd/gd32/gd32e10x/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32e10x/soc.h rename to soc/gd/gd32/gd32e10x/soc.h diff --git a/soc/arm/gd_gd32/gd32e50x/CMakeLists.txt b/soc/gd/gd32/gd32e50x/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32e50x/CMakeLists.txt rename to soc/gd/gd32/gd32e50x/CMakeLists.txt diff --git a/soc/gd/gd32/gd32e50x/Kconfig b/soc/gd/gd32/gd32e50x/Kconfig new file mode 100644 index 00000000000..d0672660e85 --- /dev/null +++ b/soc/gd/gd32/gd32e50x/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32E50X + select ARM + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select CPU_CORTEX_M33 + select ARMV8_M_DSP + select GD32_HAS_AFIO_PINMUX + select GD32_HAS_IRC_40K diff --git a/soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.gd32e507 b/soc/gd/gd32/gd32e50x/Kconfig.defconfig.gd32e507 similarity index 88% rename from soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.gd32e507 rename to soc/gd/gd32/gd32e50x/Kconfig.defconfig.gd32e507 index b9d9bbb5697..b2b15f6ce00 100644 --- a/soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.gd32e507 +++ b/soc/gd/gd32/gd32e50x/Kconfig.defconfig.gd32e507 @@ -3,9 +3,6 @@ if SOC_GD32E507 -config SOC - default "gd32e507" - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/gd/gd32/gd32e50x/Kconfig.defconfig.series b/soc/gd/gd32/gd32e50x/Kconfig.defconfig.series new file mode 100644 index 00000000000..1b9f8b98150 --- /dev/null +++ b/soc/gd/gd32/gd32e50x/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32E50X + +config SOC_SERIES + default "gd32e50x" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32E50X diff --git a/soc/gd/gd32/gd32e50x/Kconfig.soc b/soc/gd/gd32/gd32e50x/Kconfig.soc new file mode 100644 index 00000000000..4523d95e5c2 --- /dev/null +++ b/soc/gd/gd32/gd32e50x/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32E50X + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32E50X MCU series + +config SOC_SERIES + default "gd32e50x" if SOC_SERIES_GD32E50X + +config SOC_GD32E507 + bool + select SOC_SERIES_GD32E50X + +config SOC + default "gd32e507" if SOC_GD32E507 diff --git a/soc/arm/gd_gd32/gd32e50x/gd32_regs.h b/soc/gd/gd32/gd32e50x/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32e50x/gd32_regs.h rename to soc/gd/gd32/gd32e50x/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32e50x/soc.c b/soc/gd/gd32/gd32e50x/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32e50x/soc.c rename to soc/gd/gd32/gd32e50x/soc.c diff --git a/soc/arm/gd_gd32/gd32e50x/soc.h b/soc/gd/gd32/gd32e50x/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32e50x/soc.h rename to soc/gd/gd32/gd32e50x/soc.h diff --git a/soc/arm/gd_gd32/gd32f3x0/CMakeLists.txt b/soc/gd/gd32/gd32f3x0/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32f3x0/CMakeLists.txt rename to soc/gd/gd32/gd32f3x0/CMakeLists.txt diff --git a/soc/gd/gd32/gd32f3x0/Kconfig b/soc/gd/gd32/gd32f3x0/Kconfig new file mode 100644 index 00000000000..e2e9bff6ba1 --- /dev/null +++ b/soc/gd/gd32/gd32f3x0/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F3X0 + select ARM + select CPU_HAS_FPU + select CPU_CORTEX_M4 + select GD32_HAS_AF_PINMUX + select GD32_HAS_IRC_40K diff --git a/soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.gd32f350 b/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.gd32f350 similarity index 83% rename from soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.gd32f350 rename to soc/gd/gd32/gd32f3x0/Kconfig.defconfig.gd32f350 index 6cd1ca9ec8b..ced9dc7095d 100644 --- a/soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.gd32f350 +++ b/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.gd32f350 @@ -1,11 +1,12 @@ # Copyright (c) 2021 BrainCo Inc. # SPDX-License-Identifier: Apache-2.0 -config SOC - default "gd32f350" +if SOC_GD32F350 config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) config NUM_IRQS default 68 + +endif # SOC_GD32F350 diff --git a/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.series b/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.series new file mode 100644 index 00000000000..0bb139d227f --- /dev/null +++ b/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32F3X0 + +config SOC_SERIES + default "gd32f3x0" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32F3X0 diff --git a/soc/gd/gd32/gd32f3x0/Kconfig.soc b/soc/gd/gd32/gd32f3x0/Kconfig.soc new file mode 100644 index 00000000000..5f3f00dd638 --- /dev/null +++ b/soc/gd/gd32/gd32f3x0/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F3X0 + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32F3X0 MCU series + +config SOC_SERIES + default "gd32f3x0" if SOC_SERIES_GD32F3X0 + +config SOC_GD32F350 + bool + select SOC_SERIES_GD32F3X0 + +config SOC + default "gd32f350" if SOC_GD32F350 diff --git a/soc/arm/gd_gd32/gd32f3x0/gd32_regs.h b/soc/gd/gd32/gd32f3x0/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32f3x0/gd32_regs.h rename to soc/gd/gd32/gd32f3x0/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32f3x0/soc.c b/soc/gd/gd32/gd32f3x0/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32f3x0/soc.c rename to soc/gd/gd32/gd32f3x0/soc.c diff --git a/soc/arm/gd_gd32/gd32f3x0/soc.h b/soc/gd/gd32/gd32f3x0/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32f3x0/soc.h rename to soc/gd/gd32/gd32f3x0/soc.h diff --git a/soc/arm/gd_gd32/gd32f403/CMakeLists.txt b/soc/gd/gd32/gd32f403/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32f403/CMakeLists.txt rename to soc/gd/gd32/gd32f403/CMakeLists.txt diff --git a/soc/gd/gd32/gd32f403/Kconfig b/soc/gd/gd32/gd32f403/Kconfig new file mode 100644 index 00000000000..c4b31a0e41d --- /dev/null +++ b/soc/gd/gd32/gd32f403/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F403 + select ARM + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select GD32_HAS_AFIO_PINMUX + select GD32_HAS_IRC_40K diff --git a/soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.gd32f403 b/soc/gd/gd32/gd32f403/Kconfig.defconfig.gd32f403 similarity index 84% rename from soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.gd32f403 rename to soc/gd/gd32/gd32f403/Kconfig.defconfig.gd32f403 index f3bc4ac2209..2a08dbfb61c 100644 --- a/soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.gd32f403 +++ b/soc/gd/gd32/gd32f403/Kconfig.defconfig.gd32f403 @@ -1,11 +1,12 @@ # Copyright (c) 2021, ATL Electronics # SPDX-License-Identifier: Apache-2.0 -config SOC - default "gd32f403" +if SOC_GD32F403 config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) config NUM_IRQS default 68 + +endif # SOC_GD32F403 diff --git a/soc/gd/gd32/gd32f403/Kconfig.defconfig.series b/soc/gd/gd32/gd32f403/Kconfig.defconfig.series new file mode 100644 index 00000000000..6a316658f9f --- /dev/null +++ b/soc/gd/gd32/gd32f403/Kconfig.defconfig.series @@ -0,0 +1,8 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32F403 + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32F403 diff --git a/soc/gd/gd32/gd32f403/Kconfig.soc b/soc/gd/gd32/gd32f403/Kconfig.soc new file mode 100644 index 00000000000..b377b95c086 --- /dev/null +++ b/soc/gd/gd32/gd32f403/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F403 + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32F403 MCU series + +config SOC_SERIES + default "gd32f403" if SOC_SERIES_GD32F403 + +config SOC_GD32F403 + bool + select SOC_SERIES_GD32F403 + +config SOC + default "gd32f403" if SOC_GD32F403 diff --git a/soc/arm/gd_gd32/gd32f403/gd32_regs.h b/soc/gd/gd32/gd32f403/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32f403/gd32_regs.h rename to soc/gd/gd32/gd32f403/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32f403/soc.c b/soc/gd/gd32/gd32f403/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32f403/soc.c rename to soc/gd/gd32/gd32f403/soc.c diff --git a/soc/arm/gd_gd32/gd32f403/soc.h b/soc/gd/gd32/gd32f403/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32f403/soc.h rename to soc/gd/gd32/gd32f403/soc.h diff --git a/soc/arm/gd_gd32/gd32f4xx/CMakeLists.txt b/soc/gd/gd32/gd32f4xx/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32f4xx/CMakeLists.txt rename to soc/gd/gd32/gd32f4xx/CMakeLists.txt diff --git a/soc/gd/gd32/gd32f4xx/Kconfig b/soc/gd/gd32/gd32f4xx/Kconfig new file mode 100644 index 00000000000..efc8455e116 --- /dev/null +++ b/soc/gd/gd32/gd32f4xx/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F4XX + select ARM + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select CPU_CORTEX_M4 + select GD32_HAS_AF_PINMUX + select GD32_HAS_IRC_32K diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f405 b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f405 similarity index 88% rename from soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f405 rename to soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f405 index 966bf8e80ac..cb70828b022 100644 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f405 +++ b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f405 @@ -3,9 +3,6 @@ if SOC_GD32F405 -config SOC - default "gd32f405" - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f407 b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f407 similarity index 89% rename from soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f407 rename to soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f407 index 202bb0f5b2e..2fc1491a5db 100644 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f407 +++ b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f407 @@ -3,9 +3,6 @@ if SOC_GD32F407 -config SOC - default "gd32f407" - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f450 b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f450 similarity index 88% rename from soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f450 rename to soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f450 index a4fd9ff66af..22d593989a2 100644 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f450 +++ b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f450 @@ -3,9 +3,6 @@ if SOC_GD32F450 -config SOC - default "gd32f450" - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f470 b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f470 similarity index 87% rename from soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f470 rename to soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f470 index 3ddc0122dc0..3656a3acc0b 100644 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f470 +++ b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f470 @@ -3,9 +3,6 @@ if SOC_GD32F470 -config SOC - default "gd32f470" - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.series b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.series new file mode 100644 index 00000000000..aa626c9523f --- /dev/null +++ b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32F4XX + +config SOC_SERIES + default "gd32f4xx" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32F4XX diff --git a/soc/gd/gd32/gd32f4xx/Kconfig.soc b/soc/gd/gd32/gd32f4xx/Kconfig.soc new file mode 100644 index 00000000000..fde68179bc9 --- /dev/null +++ b/soc/gd/gd32/gd32f4xx/Kconfig.soc @@ -0,0 +1,34 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# Copyright (c) 2022, Rtone. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F4XX + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32F4XX MCU series + +config SOC_SERIES + default "gd32f4xx" if SOC_SERIES_GD32F4XX + +config SOC_GD32F405 + bool + select SOC_SERIES_GD32F4XX + +config SOC_GD32F407 + bool + select SOC_SERIES_GD32F4XX + +config SOC_GD32F450 + bool + select SOC_SERIES_GD32F4XX + +config SOC_GD32F470 + bool + select SOC_SERIES_GD32F4XX + +config SOC + default "gd32f405" if SOC_GD32F405 + default "gd32f407" if SOC_GD32F407 + default "gd32f450" if SOC_GD32F450 + default "gd32f470" if SOC_GD32F470 diff --git a/soc/arm/gd_gd32/gd32f4xx/gd32_regs.h b/soc/gd/gd32/gd32f4xx/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32f4xx/gd32_regs.h rename to soc/gd/gd32/gd32f4xx/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32f4xx/soc.c b/soc/gd/gd32/gd32f4xx/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32f4xx/soc.c rename to soc/gd/gd32/gd32f4xx/soc.c diff --git a/soc/arm/gd_gd32/gd32f4xx/soc.h b/soc/gd/gd32/gd32f4xx/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32f4xx/soc.h rename to soc/gd/gd32/gd32f4xx/soc.h diff --git a/soc/arm/gd_gd32/gd32l23x/CMakeLists.txt b/soc/gd/gd32/gd32l23x/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32l23x/CMakeLists.txt rename to soc/gd/gd32/gd32l23x/CMakeLists.txt diff --git a/soc/gd/gd32/gd32l23x/Kconfig b/soc/gd/gd32/gd32l23x/Kconfig new file mode 100644 index 00000000000..5155d89ea15 --- /dev/null +++ b/soc/gd/gd32/gd32l23x/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2022 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32L23X + select ARM + select CPU_CORTEX_M23 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select GD32_HAS_AF_PINMUX + select GD32_HAS_IRC_32K diff --git a/soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.gd32l233 b/soc/gd/gd32/gd32l23x/Kconfig.defconfig.gd32l233 similarity index 83% rename from soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.gd32l233 rename to soc/gd/gd32/gd32l23x/Kconfig.defconfig.gd32l233 index 31ad6d9034e..bec843575d7 100644 --- a/soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.gd32l233 +++ b/soc/gd/gd32/gd32l23x/Kconfig.defconfig.gd32l233 @@ -1,11 +1,12 @@ # Copyright (c) 2022 BrainCo Inc. # SPDX-License-Identifier: Apache-2.0 -config SOC - default "gd32l233" +if SOC_GD32L233 config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) config NUM_IRQS default 69 + +endif # SOC_GD32L233 diff --git a/soc/gd/gd32/gd32l23x/Kconfig.defconfig.series b/soc/gd/gd32/gd32l23x/Kconfig.defconfig.series new file mode 100644 index 00000000000..bc8b2aa4cde --- /dev/null +++ b/soc/gd/gd32/gd32l23x/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2022 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32L23X + +config SOC_SERIES + default "gd32l23x" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32L23X diff --git a/soc/gd/gd32/gd32l23x/Kconfig.soc b/soc/gd/gd32/gd32l23x/Kconfig.soc new file mode 100644 index 00000000000..da3a950aa25 --- /dev/null +++ b/soc/gd/gd32/gd32l23x/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2022 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32L23X + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32L23X MCU series + +config SOC_SERIES + default "gd32l23x" if SOC_SERIES_GD32L23X + +config SOC_GD32L233 + bool + select SOC_SERIES_GD32L23X + +config SOC + default "gd32l233" if SOC_GD32L233 diff --git a/soc/arm/gd_gd32/gd32l23x/gd32_regs.h b/soc/gd/gd32/gd32l23x/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32l23x/gd32_regs.h rename to soc/gd/gd32/gd32l23x/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32l23x/soc.c b/soc/gd/gd32/gd32l23x/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32l23x/soc.c rename to soc/gd/gd32/gd32l23x/soc.c diff --git a/soc/arm/gd_gd32/gd32l23x/soc.h b/soc/gd/gd32/gd32l23x/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32l23x/soc.h rename to soc/gd/gd32/gd32l23x/soc.h diff --git a/soc/gd/gd32/gd32vf103/CMakeLists.txt b/soc/gd/gd32/gd32vf103/CMakeLists.txt new file mode 100644 index 00000000000..6778c0a4f1b --- /dev/null +++ b/soc/gd/gd32/gd32vf103/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2021 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(entry.S) +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/gd/gd32/gd32vf103/Kconfig b/soc/gd/gd32/gd32vf103/Kconfig new file mode 100644 index 00000000000..d206100c53e --- /dev/null +++ b/soc/gd/gd32/gd32vf103/Kconfig @@ -0,0 +1,20 @@ +# GD32VF103 SOC implementation + +# Copyright (c) 2021 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32VF103 + select RISCV + select RISCV_PRIVILEGED + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_HAS_CLIC + select ATOMIC_OPERATIONS_C + select INCLUDE_RESET_VECTOR + select GD32_HAS_AFIO_PINMUX + select GD32_HAS_IRC_40K + select XIP diff --git a/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103 b/soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103 similarity index 86% rename from soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103 rename to soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103 index d37b27ffbf0..714741364bb 100644 --- a/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103 +++ b/soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103 @@ -3,9 +3,6 @@ if SOC_GD32VF103 -config SOC - default "gd32vf103" - config KERNEL_ENTRY default "__nuclei_start" @@ -30,15 +27,6 @@ config NUM_IRQS config 2ND_LEVEL_INTERRUPTS default y -config PINCTRL - default y - -config RESET - default y - -config CLOCK_CONTROL - default y - config ARCH_IRQ_VECTOR_TABLE_ALIGN default 512 if NUCLEI_ECLIC diff --git a/soc/gd/gd32/gd32vf103/Kconfig.defconfig.series b/soc/gd/gd32/gd32vf103/Kconfig.defconfig.series new file mode 100644 index 00000000000..78a912701d9 --- /dev/null +++ b/soc/gd/gd32/gd32vf103/Kconfig.defconfig.series @@ -0,0 +1,8 @@ +# Copyright (c) 2021 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32VF103 + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32VF103 diff --git a/soc/gd/gd32/gd32vf103/Kconfig.soc b/soc/gd/gd32/gd32vf103/Kconfig.soc new file mode 100644 index 00000000000..c692e914ad1 --- /dev/null +++ b/soc/gd/gd32/gd32vf103/Kconfig.soc @@ -0,0 +1,20 @@ +# GD32VF103 SOC configuration options + +# Copyright (c) 2021 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32VF103 + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32VF103 MCU series + +config SOC_SERIES + default "gd32vf103" if SOC_SERIES_GD32VF103 + +config SOC_GD32VF103 + bool + select SOC_SERIES_GD32VF103 + +config SOC + default "gd32vf103" if SOC_GD32VF103 diff --git a/soc/riscv/gd_gd32/gd32vf103/entry.S b/soc/gd/gd32/gd32vf103/entry.S similarity index 100% rename from soc/riscv/gd_gd32/gd32vf103/entry.S rename to soc/gd/gd32/gd32vf103/entry.S diff --git a/soc/riscv/gd_gd32/gd32vf103/gd32_regs.h b/soc/gd/gd32/gd32vf103/gd32_regs.h similarity index 100% rename from soc/riscv/gd_gd32/gd32vf103/gd32_regs.h rename to soc/gd/gd32/gd32vf103/gd32_regs.h diff --git a/soc/riscv/gd_gd32/gd32vf103/init.ld b/soc/gd/gd32/gd32vf103/init.ld similarity index 100% rename from soc/riscv/gd_gd32/gd32vf103/init.ld rename to soc/gd/gd32/gd32vf103/init.ld diff --git a/soc/riscv/gd_gd32/gd32vf103/nuclei_csr.h b/soc/gd/gd32/gd32vf103/nuclei_csr.h similarity index 100% rename from soc/riscv/gd_gd32/gd32vf103/nuclei_csr.h rename to soc/gd/gd32/gd32vf103/nuclei_csr.h diff --git a/soc/riscv/gd_gd32/gd32vf103/soc.c b/soc/gd/gd32/gd32vf103/soc.c similarity index 100% rename from soc/riscv/gd_gd32/gd32vf103/soc.c rename to soc/gd/gd32/gd32vf103/soc.c diff --git a/soc/gd/gd32/soc.yml b/soc/gd/gd32/soc.yml new file mode 100644 index 00000000000..22339687e19 --- /dev/null +++ b/soc/gd/gd32/soc.yml @@ -0,0 +1,30 @@ +family: +- name: gd_gd32 + series: + - name: gd32a50x + socs: + - name: gd32a503 + - name: gd32e10x + socs: + - name: gd32e103 + - name: gd32e50x + socs: + - name: gd32e507 + - name: gd32f3x0 + socs: + - name: gd32f350 + - name: gd32f4xx + socs: + - name: gd32f405 + - name: gd32f407 + - name: gd32f450 + - name: gd32f470 + - name: gd32f403 + socs: + - name: gd32f403 + - name: gd32l23x + socs: + - name: gd32l233 + - name: gd32vf103 + socs: + - name: gd32vf103 diff --git a/soc/arm/infineon_xmc/CMakeLists.txt b/soc/infineon/xmc/CMakeLists.txt similarity index 100% rename from soc/arm/infineon_xmc/CMakeLists.txt rename to soc/infineon/xmc/CMakeLists.txt diff --git a/soc/infineon/xmc/Kconfig b/soc/infineon/xmc/Kconfig new file mode 100644 index 00000000000..8720e3a27b2 --- /dev/null +++ b/soc/infineon/xmc/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +config SOC_FAMILY_INFINEON_XMC + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select PLATFORM_SPECIFIC_INIT + +if SOC_FAMILY_INFINEON_XMC + +rsource "*/Kconfig" + +endif # SOC_FAMILY_INFINEON_XMC diff --git a/soc/infineon/xmc/Kconfig.defconfig b/soc/infineon/xmc/Kconfig.defconfig new file mode 100644 index 00000000000..10a5e55986a --- /dev/null +++ b/soc/infineon/xmc/Kconfig.defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +if SOC_FAMILY_INFINEON_XMC + +rsource "*/Kconfig.defconfig" + +config PINCTRL + default y + +endif # SOC_FAMILY_INFINEON_XMC diff --git a/soc/infineon/xmc/Kconfig.soc b/soc/infineon/xmc/Kconfig.soc new file mode 100644 index 00000000000..f0abf738dca --- /dev/null +++ b/soc/infineon/xmc/Kconfig.soc @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +config SOC_FAMILY_INFINEON_XMC + bool + +config SOC_FAMILY + default "infineon_xmc" if SOC_FAMILY_INFINEON_XMC + +rsource "*/Kconfig.soc" diff --git a/soc/infineon/xmc/soc.yml b/soc/infineon/xmc/soc.yml new file mode 100644 index 00000000000..758e3c730d2 --- /dev/null +++ b/soc/infineon/xmc/soc.yml @@ -0,0 +1,7 @@ +family: +- name: infineon_xmc + series: + - name: xmc4xxx + socs: + - name: xmc4500 + - name: xmc4700 diff --git a/soc/infineon/xmc/xmc4xxx/CMakeLists.txt b/soc/infineon/xmc/xmc4xxx/CMakeLists.txt new file mode 100644 index 00000000000..811731b51bc --- /dev/null +++ b/soc/infineon/xmc/xmc4xxx/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +zephyr_sources(soc.c) +zephyr_include_directories(.) +zephyr_linker_sources(NOINIT noinit.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/infineon/xmc/xmc4xxx/Kconfig b/soc/infineon/xmc/xmc4xxx/Kconfig new file mode 100644 index 00000000000..21f4c7b5cb3 --- /dev/null +++ b/soc/infineon/xmc/xmc4xxx/Kconfig @@ -0,0 +1,24 @@ +# XMC 4xxx MCU line +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_XMC4XXX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select HAS_XMCLIB + select HAS_XMCLIB_UART + select HAS_XMCLIB_FLASH + select HAS_XMCLIB_ERU + select HAS_XMCLIB_VADC + select HAS_XMCLIB_DMA + select HAS_XMCLIB_SPI + select HAS_XMCLIB_I2C + select HAS_XMCLIB_CCU + select HAS_XMCLIB_WDT + select HAS_XMCLIB_ETH + select HAS_XMCLIB_CAN diff --git a/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig new file mode 100644 index 00000000000..eec3dc0daf8 --- /dev/null +++ b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# XMC 4xxx series configuration options +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +if SOC_SERIES_XMC4XXX + +config NUM_IRQS + default 112 + +rsource "Kconfig.defconfig.xmc*" + +endif # SOC_SERIES_XMC4XXX diff --git a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4500 b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4500 similarity index 90% rename from soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4500 rename to soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4500 index 7bb9ffc2b1f..17e2caf1dbb 100644 --- a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4500 +++ b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4500 @@ -6,9 +6,6 @@ if SOC_XMC4500 -config SOC - default "XMC4500" - config SYS_CLOCK_HW_CYCLES_PER_SEC default 120000000 diff --git a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4700 b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4700 similarity index 89% rename from soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4700 rename to soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4700 index febf1b38ab1..a17429330a1 100644 --- a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4700 +++ b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4700 @@ -5,9 +5,6 @@ if SOC_XMC4700 -config SOC - default "XMC4700" - config SYS_CLOCK_HW_CYCLES_PER_SEC default 144000000 diff --git a/soc/infineon/xmc/xmc4xxx/Kconfig.soc b/soc/infineon/xmc/xmc4xxx/Kconfig.soc new file mode 100644 index 00000000000..726e433b10b --- /dev/null +++ b/soc/infineon/xmc/xmc4xxx/Kconfig.soc @@ -0,0 +1,40 @@ +# XMC 4xxx MCU line +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_XMC4XXX + bool + select SOC_FAMILY_INFINEON_XMC + help + XMC 4xxx Series MCU + +config SOC_XMC4500 + bool + select SOC_SERIES_XMC4XXX + help + SOC_XMC4500 + +config SOC_XMC4700 + bool + select SOC_SERIES_XMC4XXX + help + SOC_XMC4700 + +config SOC_PART_NUMBER_F100X1024 + bool + +config SOC_PART_NUMBER_F144X2048 + bool + +config SOC_SERIES + default "xmc4xxx" if SOC_SERIES_XMC4XXX + +config SOC + default "xmc4500" if SOC_XMC4500 + default "xmc4700" if SOC_XMC4700 + +config SOC_PART_NUMBER + default "F100x1024" if SOC_PART_NUMBER_F100X1024 + default "F144x2048" if SOC_PART_NUMBER_F144X2048 diff --git a/soc/arm/infineon_xmc/4xxx/noinit.ld b/soc/infineon/xmc/xmc4xxx/noinit.ld similarity index 100% rename from soc/arm/infineon_xmc/4xxx/noinit.ld rename to soc/infineon/xmc/xmc4xxx/noinit.ld diff --git a/soc/arm/infineon_xmc/4xxx/pinctrl_soc.h b/soc/infineon/xmc/xmc4xxx/pinctrl_soc.h similarity index 100% rename from soc/arm/infineon_xmc/4xxx/pinctrl_soc.h rename to soc/infineon/xmc/xmc4xxx/pinctrl_soc.h diff --git a/soc/arm/infineon_xmc/4xxx/soc.c b/soc/infineon/xmc/xmc4xxx/soc.c similarity index 100% rename from soc/arm/infineon_xmc/4xxx/soc.c rename to soc/infineon/xmc/xmc4xxx/soc.c diff --git a/soc/arm/infineon_xmc/4xxx/soc.h b/soc/infineon/xmc/xmc4xxx/soc.h similarity index 100% rename from soc/arm/infineon_xmc/4xxx/soc.h rename to soc/infineon/xmc/xmc4xxx/soc.h diff --git a/soc/intel/alder_lake/CMakeLists.txt b/soc/intel/alder_lake/CMakeLists.txt new file mode 100644 index 00000000000..7db5fbabfc0 --- /dev/null +++ b/soc/intel/alder_lake/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library() +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_cc_option(-march=goldmont) + +zephyr_library_sources(cpu.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/alder_lake/Kconfig b/soc/intel/alder_lake/Kconfig new file mode 100644 index 00000000000..1e8808cae13 --- /dev/null +++ b/soc/intel/alder_lake/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ALDER_LAKE + select X86 + select X86_64 + select CPU_ATOM + select PCIE + select PCIE_MSI + select DYNAMIC_INTERRUPTS + select X86_MMU diff --git a/soc/intel/alder_lake/Kconfig.defconfig b/soc/intel/alder_lake/Kconfig.defconfig new file mode 100644 index 00000000000..ea70a8d5405 --- /dev/null +++ b/soc/intel/alder_lake/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Alder Lake SoC configuration options + +# Copyright (c) 2018-2024 Intel Corporation +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ALDER_LAKE + +config PCIE_MMIO_CFG + default y + +config X86_DYNAMIC_IRQ_STUBS + default 16 + depends on DYNAMIC_INTERRUPTS + +endif # SOC_ALDER_LAKE diff --git a/soc/intel/alder_lake/Kconfig.soc b/soc/intel/alder_lake/Kconfig.soc new file mode 100644 index 00000000000..b808d0d74bb --- /dev/null +++ b/soc/intel/alder_lake/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ALDER_LAKE + bool + +config SOC + default "alder_lake" if SOC_ALDER_LAKE diff --git a/soc/x86/alder_lake/cpu.c b/soc/intel/alder_lake/cpu.c similarity index 100% rename from soc/x86/alder_lake/cpu.c rename to soc/intel/alder_lake/cpu.c diff --git a/soc/x86/alder_lake/doc/supported_features.txt b/soc/intel/alder_lake/doc/supported_features.txt similarity index 100% rename from soc/x86/alder_lake/doc/supported_features.txt rename to soc/intel/alder_lake/doc/supported_features.txt diff --git a/soc/x86/alder_lake/linker.ld b/soc/intel/alder_lake/linker.ld similarity index 100% rename from soc/x86/alder_lake/linker.ld rename to soc/intel/alder_lake/linker.ld diff --git a/soc/x86/alder_lake/soc.h b/soc/intel/alder_lake/soc.h similarity index 100% rename from soc/x86/alder_lake/soc.h rename to soc/intel/alder_lake/soc.h diff --git a/soc/intel/alder_lake/soc.yml b/soc/intel/alder_lake/soc.yml new file mode 100644 index 00000000000..04c9d8b5eb9 --- /dev/null +++ b/soc/intel/alder_lake/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Alder Lake SoC" +socs: +- name: alder_lake diff --git a/soc/x86/alder_lake/soc_gpio.h b/soc/intel/alder_lake/soc_gpio.h similarity index 100% rename from soc/x86/alder_lake/soc_gpio.h rename to soc/intel/alder_lake/soc_gpio.h diff --git a/soc/intel/apollo_lake/CMakeLists.txt b/soc/intel/apollo_lake/CMakeLists.txt new file mode 100644 index 00000000000..7db5fbabfc0 --- /dev/null +++ b/soc/intel/apollo_lake/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library() +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_cc_option(-march=goldmont) + +zephyr_library_sources(cpu.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/apollo_lake/Kconfig b/soc/intel/apollo_lake/Kconfig new file mode 100644 index 00000000000..51a410b7fc7 --- /dev/null +++ b/soc/intel/apollo_lake/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_APOLLO_LAKE + select X86 + select X86_64 + select CPU_APOLLO_LAKE + select PCIE + select PCIE_MSI + select DYNAMIC_INTERRUPTS + select X86_MMU + select ARCH_HAS_RESERVED_PAGE_FRAMES diff --git a/soc/intel/apollo_lake/Kconfig.defconfig b/soc/intel/apollo_lake/Kconfig.defconfig new file mode 100644 index 00000000000..7ea881ce59e --- /dev/null +++ b/soc/intel/apollo_lake/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Apollo Lake SoC configuration options + +# Copyright (c) 2018-2019 Intel Corporation +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_APOLLO_LAKE + +config PCIE_MMIO_CFG + default y + +if APIC_TIMER + +config APIC_TIMER_IRQ + default 24 + +config APIC_TIMER_TSC + default y + +endif # APIC_TIMER + +config X86_DYNAMIC_IRQ_STUBS + default 16 + depends on DYNAMIC_INTERRUPTS + +endif # SOC_APOLLO_LAKE diff --git a/soc/intel/apollo_lake/Kconfig.soc b/soc/intel/apollo_lake/Kconfig.soc new file mode 100644 index 00000000000..0d45667d46f --- /dev/null +++ b/soc/intel/apollo_lake/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_APOLLO_LAKE + bool + +config SOC + default "apollo_lake" if SOC_APOLLO_LAKE diff --git a/soc/x86/apollo_lake/cpu.c b/soc/intel/apollo_lake/cpu.c similarity index 100% rename from soc/x86/apollo_lake/cpu.c rename to soc/intel/apollo_lake/cpu.c diff --git a/soc/x86/apollo_lake/doc/supported_features.txt b/soc/intel/apollo_lake/doc/supported_features.txt similarity index 100% rename from soc/x86/apollo_lake/doc/supported_features.txt rename to soc/intel/apollo_lake/doc/supported_features.txt diff --git a/soc/x86/apollo_lake/linker.ld b/soc/intel/apollo_lake/linker.ld similarity index 100% rename from soc/x86/apollo_lake/linker.ld rename to soc/intel/apollo_lake/linker.ld diff --git a/soc/x86/apollo_lake/soc.h b/soc/intel/apollo_lake/soc.h similarity index 100% rename from soc/x86/apollo_lake/soc.h rename to soc/intel/apollo_lake/soc.h diff --git a/soc/intel/apollo_lake/soc.yml b/soc/intel/apollo_lake/soc.yml new file mode 100644 index 00000000000..0e1d16f9746 --- /dev/null +++ b/soc/intel/apollo_lake/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Apollo Lake SoC" +socs: +- name: apollo_lake diff --git a/soc/x86/apollo_lake/soc_gpio.h b/soc/intel/apollo_lake/soc_gpio.h similarity index 100% rename from soc/x86/apollo_lake/soc_gpio.h rename to soc/intel/apollo_lake/soc_gpio.h diff --git a/soc/intel/atom/CMakeLists.txt b/soc/intel/atom/CMakeLists.txt new file mode 100644 index 00000000000..9bb60341f1b --- /dev/null +++ b/soc/intel/atom/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2011-2014, Wind River Systems, Inc. + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/atom/Kconfig b/soc/intel/atom/Kconfig new file mode 100644 index 00000000000..bc0d509eb70 --- /dev/null +++ b/soc/intel/atom/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2011-2014, Wind River Systems, Inc. + +config SOC_ATOM + select X86 + select CPU_ATOM + imply X86_MMU + select ARCH_HAS_RESERVED_PAGE_FRAMES diff --git a/soc/intel/atom/Kconfig.defconfig b/soc/intel/atom/Kconfig.defconfig new file mode 100644 index 00000000000..35b7deb8e07 --- /dev/null +++ b/soc/intel/atom/Kconfig.defconfig @@ -0,0 +1,11 @@ +# ATOM SoC configuration options + +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ATOM + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 if HPET_TIMER + +endif diff --git a/soc/intel/atom/Kconfig.soc b/soc/intel/atom/Kconfig.soc new file mode 100644 index 00000000000..63c130640eb --- /dev/null +++ b/soc/intel/atom/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Intel Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ATOM + bool + +config SOC + default "atom" if SOC_ATOM diff --git a/soc/x86/ia32/linker.ld b/soc/intel/atom/linker.ld similarity index 100% rename from soc/x86/ia32/linker.ld rename to soc/intel/atom/linker.ld diff --git a/soc/intel/atom/soc.yml b/soc/intel/atom/soc.yml new file mode 100644 index 00000000000..456cfe068d7 --- /dev/null +++ b/soc/intel/atom/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Atom SoC" +socs: +- name: atom diff --git a/soc/intel/elkhart_lake/CMakeLists.txt b/soc/intel/elkhart_lake/CMakeLists.txt new file mode 100644 index 00000000000..7db5fbabfc0 --- /dev/null +++ b/soc/intel/elkhart_lake/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library() +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_cc_option(-march=goldmont) + +zephyr_library_sources(cpu.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/elkhart_lake/Kconfig b/soc/intel/elkhart_lake/Kconfig new file mode 100644 index 00000000000..6678f3c56e9 --- /dev/null +++ b/soc/intel/elkhart_lake/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ELKHART_LAKE + select X86 + select X86_64 + select CPU_ATOM + select PCIE + select PCIE_MSI + select DYNAMIC_INTERRUPTS + select X86_MMU diff --git a/soc/intel/elkhart_lake/Kconfig.defconfig b/soc/intel/elkhart_lake/Kconfig.defconfig new file mode 100644 index 00000000000..c48e6f9d1d8 --- /dev/null +++ b/soc/intel/elkhart_lake/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Elkhart Lake SoC configuration options + +# Copyright (c) 2018-2020 Intel Corporation +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ELKHART_LAKE + +config PCIE_MMIO_CFG + default y + +config X86_DYNAMIC_IRQ_STUBS + default 16 + depends on DYNAMIC_INTERRUPTS + +endif # SOC_ELKHART_LAKE diff --git a/soc/intel/elkhart_lake/Kconfig.soc b/soc/intel/elkhart_lake/Kconfig.soc new file mode 100644 index 00000000000..ff1b82106b6 --- /dev/null +++ b/soc/intel/elkhart_lake/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ELKHART_LAKE + bool + +config SOC + default "elkhart_lake" if SOC_ELKHART_LAKE diff --git a/soc/x86/elkhart_lake/cpu.c b/soc/intel/elkhart_lake/cpu.c similarity index 100% rename from soc/x86/elkhart_lake/cpu.c rename to soc/intel/elkhart_lake/cpu.c diff --git a/soc/x86/elkhart_lake/doc/supported_features.txt b/soc/intel/elkhart_lake/doc/supported_features.txt similarity index 100% rename from soc/x86/elkhart_lake/doc/supported_features.txt rename to soc/intel/elkhart_lake/doc/supported_features.txt diff --git a/soc/x86/elkhart_lake/linker.ld b/soc/intel/elkhart_lake/linker.ld similarity index 100% rename from soc/x86/elkhart_lake/linker.ld rename to soc/intel/elkhart_lake/linker.ld diff --git a/soc/x86/elkhart_lake/soc.h b/soc/intel/elkhart_lake/soc.h similarity index 100% rename from soc/x86/elkhart_lake/soc.h rename to soc/intel/elkhart_lake/soc.h diff --git a/soc/intel/elkhart_lake/soc.yml b/soc/intel/elkhart_lake/soc.yml new file mode 100644 index 00000000000..08a7dbb3854 --- /dev/null +++ b/soc/intel/elkhart_lake/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Elkhart Lake SoC" +socs: +- name: elkhart_lake diff --git a/soc/x86/elkhart_lake/soc_gpio.h b/soc/intel/elkhart_lake/soc_gpio.h similarity index 100% rename from soc/x86/elkhart_lake/soc_gpio.h rename to soc/intel/elkhart_lake/soc_gpio.h diff --git a/soc/intel/intel_adsp/CMakeLists.txt b/soc/intel/intel_adsp/CMakeLists.txt new file mode 100644 index 00000000000..45c97d34cfa --- /dev/null +++ b/soc/intel/intel_adsp/CMakeLists.txt @@ -0,0 +1,17 @@ +# Intel ADSP SoCs family CMake file +# +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(common) + +add_subdirectory(common) +if(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) + zephyr_include_directories(ace) + add_subdirectory(ace) +endif() +if(CONFIG_INTEL_ADSP_CAVS) + zephyr_include_directories(cavs) + add_subdirectory(cavs) +endif() +zephyr_include_directories(common/include) diff --git a/soc/intel/intel_adsp/Kconfig b/soc/intel/intel_adsp/Kconfig new file mode 100644 index 00000000000..135fecb575a --- /dev/null +++ b/soc/intel/intel_adsp/Kconfig @@ -0,0 +1,132 @@ +# Intel CAVS SoC family configuration options +# +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_ADSP + select WINSTREAM + select ARCH_SUPPORTS_COREDUMP + select CPU_HAS_DCACHE + select ARCH_HAS_USERSPACE if XTENSA_MMU + select CPU_CACHE_INCOHERENT + +if SOC_FAMILY_INTEL_ADSP + +rsource "*/Kconfig" + +DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc +DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc + +config INTEL_ADSP_IPC + bool "Driver for the host IPC interrupt delivery" + default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HOST_IPC)) if !SOF + default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_IDC)) if !SOF + help + Driver for the host IPC interrupt delivery mechanism. + Currently SOF has its own driver for this hardware. + +config MEMORY_WIN_0_SIZE + int "Size of memory window 0" + default 8192 + help + Size of memory window 0. + + This window is used for firmware status & outbox/uplink mbox. + +config MEMORY_WIN_1_SIZE + int "Size of memory window 1" + default 8192 + help + Size of memory window 1. + + This window is used for inbox/downlink mbox. + +config MEMORY_WIN_2_SIZE + int "Size of memory window 2" + default 8192 + help + Size of memory window 2. + + This window is used for debug. + +config MEMORY_WIN_3_SIZE + int "Size of memory window 3" + default 8192 + help + Size of memory window 3. + + This window is used for trace. + +config ADSP_CLOCK + bool + help + Driver for the CAVS clocks. Allow type of clock (and + thus frequency) to be chosen. + +config HP_SRAM_RESERVE + int "Bytes to reserve at start of HP-SRAM" + default 65536 + help + Bytes to reserve at the start of HP-SRAM. Zephyr will not + place any symbols here, though the host windows have + addresses here. The SOF application also makes direct use + of this region, so be very careful changing this value. + +config ADSP_TRACE_SIMCALL + bool "Emit SIMCALL output in addition to window tracing" + help + When true, the trace_out layer will also use a SIMCALL + instruction to emit the passed data to the standard output + of an enclosing simulator process. All window contents will + remain identical. + +config ADSP_NEED_POWER_ON_CACHE + bool + help + Need to power cache SRAM banks on. + +config ADSP_INIT_HPSRAM + bool + default y + help + Need to init HP SRAM. + +config ADSP_POWER_DOWN_HPSRAM + bool + default n if ZTEST + default y + help + Switch off HP SRAM during power down. + +config ADSP_DISABLE_L2CACHE_AT_BOOT + bool + +config ADSP_IMR_CONTEXT_SAVE + bool "Saves FW context into IMR before core is shut down" + default n + help + When true, FW will store its entire context into IMR before + entering D3 state. Later this context can be used to FW restore + when Host power up DSP again. + +config XTENSA_CPU_IDLE_SPIN + bool "Use busy loop for k_cpu_idle" + help + Use a spin loop instead of WAITI for the CPU idle state. + +config XTENSA_WAITI_BUG + bool "Workaround sequence for WAITI bug on LX6" + help + SOF traditionally contains this workaround on its ADSP + platforms which prefixes a WAITI entry with 128 NOP + instructions followed by an ISYNC and EXTW. + +config ADSP_IDLE_CLOCK_GATING + bool "DSP clock gating in Idle" + help + When true, FW will run with enabled clock gating. This options change + HW configuration of a DSP. Evry time core goes to the WAITI state + (wait for interrupt) during idle, the clock can be gated (however, this + does not mean that this will happen). + +endif # SOC_FAMILY_INTEL_ADSP diff --git a/soc/intel/intel_adsp/Kconfig.defconfig b/soc/intel/intel_adsp/Kconfig.defconfig new file mode 100644 index 00000000000..d76faf02def --- /dev/null +++ b/soc/intel/intel_adsp/Kconfig.defconfig @@ -0,0 +1,51 @@ +# Intel CAVS SoC family default configuration options +# +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_ADSP + +rsource "*/Kconfig.defconfig.series" + +# A workaround for HWMv2 to recover SOF arch/xtensa defaults overridden by arch/host. +if SOF +config CORE_COUNT + int + default MP_MAX_NUM_CPUS +endif + +config XTENSA_RPO_CACHE + def_bool y + +# console can't handle the amount of data coming from many tests, so introduce +# a delay beween testcases. +if ZTEST +config ZTEST_TEST_DELAY_MS + default 100 +endif + +if XTENSA_RPO_CACHE +config XTENSA_CACHED_REGION + default 5 + +config XTENSA_UNCACHED_REGION + default 4 + +endif # XTENSA_RPO_CACHE + +config CONSOLE + def_bool y + +if CONSOLE +config WINSTREAM_CONSOLE + def_bool y +endif + +config CACHE_MANAGEMENT + def_bool y + +choice CACHE_TYPE + default ARCH_CACHE +endchoice + +endif # SOC_FAMILY_INTEL_ADSP diff --git a/soc/intel/intel_adsp/Kconfig.soc b/soc/intel/intel_adsp/Kconfig.soc new file mode 100644 index 00000000000..9df1c63e1a9 --- /dev/null +++ b/soc/intel/intel_adsp/Kconfig.soc @@ -0,0 +1,12 @@ +# Intel CAVS SoC series selection +# +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_ADSP + bool + +config SOC_FAMILY + default "intel_adsp" if SOC_FAMILY_INTEL_ADSP + +rsource "*/Kconfig.soc" diff --git a/soc/intel/intel_adsp/ace/CMakeLists.txt b/soc/intel/intel_adsp/ace/CMakeLists.txt new file mode 100644 index 00000000000..78d3d5b9d1e --- /dev/null +++ b/soc/intel/intel_adsp/ace/CMakeLists.txt @@ -0,0 +1,22 @@ +# Intel ACE SoC family CMake file +# +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + + +zephyr_library_sources( + sram.c + multiprocessing.c + irq.c + power_down.S + power.c + boot.c + timestamp.c + ) + +zephyr_include_directories(include) +zephyr_include_directories(include/${SOC_TOOLCHAIN_NAME}) +zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget.c) +zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget_messages.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/intel_adsp/ace/Kconfig b/soc/intel/intel_adsp/ace/Kconfig new file mode 100644 index 00000000000..162d34daa34 --- /dev/null +++ b/soc/intel/intel_adsp/ace/Kconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2022-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_INTEL_ADSP_ACE + select XTENSA + select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")) + select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" + select ARCH_HAS_COHERENCE + select SCHED_IPI_SUPPORTED + select DW_ICTL_ACE + select SOC_HAS_RUNTIME_NUM_CPUS + select HAS_PM + +config SOC_INTEL_COMM_WIDGET + bool "Intel Communication Widget driver" + default y + depends on DT_HAS_INTEL_ADSP_COMMUNICATION_WIDGET_ENABLED + help + Select this to enable Intel Communication Widget driver. + DSP Communication Widget is a device for generic sideband message transmit/receive. diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm new file mode 100644 index 00000000000..c9c536f56dd --- /dev/null +++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm @@ -0,0 +1,9 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_INTEL_ACE15_MTPM + +config MP_MAX_NUM_CPUS + default 3 + +endif diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl new file mode 100644 index 00000000000..2a70da4ac5e --- /dev/null +++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl @@ -0,0 +1,9 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_INTEL_ACE20_LNL + +config MP_MAX_NUM_CPUS + default 5 + +endif diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.series b/soc/intel/intel_adsp/ace/Kconfig.defconfig.series new file mode 100644 index 00000000000..85d64c3bd0c --- /dev/null +++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.series @@ -0,0 +1,65 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_INTEL_ADSP_ACE + +config SMP + default y + +config POWER_DOMAIN + default y + +# MTL leaves the upper mapping in the same spot as cAVS, but moves the +# lower one inexplicably. +config XTENSA_UNCACHED_REGION + default 2 + +# Parameters for gen_isr_tables.py: + +config 2ND_LVL_INTR_00_OFFSET + default 4 + +config MULTI_LEVEL_INTERRUPTS + default y + +config MAX_IRQ_PER_AGGREGATOR + default 29 + +config NUM_2ND_LEVEL_AGGREGATORS + default 1 + +config 2ND_LVL_ISR_TBL_OFFSET + default 9 + +config 2ND_LEVEL_INTERRUPTS + default y + +config XTENSA_TIMER + default n + +config XTENSA_TIMER_ID + default 0 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 393216000 if XTENSA_TIMER + default 38400000 if INTEL_ADSP_TIMER + +config SYS_CLOCK_TICKS_PER_SEC + default 12000 + +config XTENSA_CCOUNT_HZ + default 393216000 + +config DYNAMIC_INTERRUPTS + default y + +if LOG + +config LOG_BACKEND_ADSP + default y + +endif # LOG + +rsource "Kconfig.defconfig.ace*" + +endif # SOC_SERIES_INTEL_ADSP_ACE diff --git a/soc/intel/intel_adsp/ace/Kconfig.soc b/soc/intel/intel_adsp/ace/Kconfig.soc new file mode 100644 index 00000000000..3cab72f8f51 --- /dev/null +++ b/soc/intel/intel_adsp/ace/Kconfig.soc @@ -0,0 +1,31 @@ +# Copyright (c) 2022-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_INTEL_ADSP_ACE + bool + select SOC_FAMILY_INTEL_ADSP + help + Intel ADSP ACE + +config SOC_INTEL_ACE15_MTPM + bool + select SOC_SERIES_INTEL_ADSP_ACE + help + ACE 1.5 Meteor Lake PCH M + +config SOC_INTEL_ACE20_LNL + bool + select SOC_SERIES_INTEL_ADSP_ACE + help + ACE 2.0 Lunar Lake PCH + +config SOC_SERIES + default "intel_adsp_ace" if SOC_SERIES_INTEL_ADSP_ACE + +config SOC_TOOLCHAIN_NAME + default "intel_ace15_mtpm" if SOC_SERIES_INTEL_ADSP_ACE + +config SOC + default "ace15_mtpm" if SOC_INTEL_ACE15_MTPM + default "ace20_lnl" if SOC_INTEL_ACE20_LNL diff --git a/soc/xtensa/intel_adsp/ace/_soc_inthandlers.h b/soc/intel/intel_adsp/ace/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/_soc_inthandlers.h rename to soc/intel/intel_adsp/ace/_soc_inthandlers.h diff --git a/soc/xtensa/intel_adsp/ace/ace-link.ld b/soc/intel/intel_adsp/ace/ace-link.ld similarity index 100% rename from soc/xtensa/intel_adsp/ace/ace-link.ld rename to soc/intel/intel_adsp/ace/ace-link.ld diff --git a/soc/xtensa/intel_adsp/ace/asm_memory_management.h b/soc/intel/intel_adsp/ace/asm_memory_management.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/asm_memory_management.h rename to soc/intel/intel_adsp/ace/asm_memory_management.h diff --git a/soc/xtensa/intel_adsp/ace/boot.c b/soc/intel/intel_adsp/ace/boot.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/boot.c rename to soc/intel/intel_adsp/ace/boot.c diff --git a/soc/xtensa/intel_adsp/ace/comm_widget.c b/soc/intel/intel_adsp/ace/comm_widget.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/comm_widget.c rename to soc/intel/intel_adsp/ace/comm_widget.c diff --git a/soc/xtensa/intel_adsp/ace/comm_widget.h b/soc/intel/intel_adsp/ace/comm_widget.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/comm_widget.h rename to soc/intel/intel_adsp/ace/comm_widget.h diff --git a/soc/xtensa/intel_adsp/ace/comm_widget_messages.c b/soc/intel/intel_adsp/ace/comm_widget_messages.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/comm_widget_messages.c rename to soc/intel/intel_adsp/ace/comm_widget_messages.c diff --git a/soc/xtensa/intel_adsp/ace/include/adsp_imr_layout.h b/soc/intel/intel_adsp/ace/include/adsp_imr_layout.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/adsp_imr_layout.h rename to soc/intel/intel_adsp/ace/include/adsp_imr_layout.h diff --git a/soc/xtensa/intel_adsp/ace/include/adsp_timestamp.h b/soc/intel/intel_adsp/ace/include/adsp_timestamp.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/adsp_timestamp.h rename to soc/intel/intel_adsp/ace/include/adsp_timestamp.h diff --git a/soc/xtensa/intel_adsp/ace/include/dmic_regs.h b/soc/intel/intel_adsp/ace/include/dmic_regs.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/dmic_regs.h rename to soc/intel/intel_adsp/ace/include/dmic_regs.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_comm_widget.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_comm_widget.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_comm_widget.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_comm_widget.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_interrupt.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_interrupt.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_interrupt.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_interrupt.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_ipc_regs.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_ipc_regs.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_ipc_regs.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_ipc_regs.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_watchdog.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_watchdog.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_watchdog.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_watchdog.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/dmic_regs_ace1x.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/dmic_regs_ace1x.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/dmic_regs_ace1x.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/dmic_regs_ace1x.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_boot.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_boot.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_boot.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_boot.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_interrupt.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_interrupt.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_interrupt.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_interrupt.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_ipc_regs.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_ipc_regs.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_ipc_regs.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_ipc_regs.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory_regions.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory_regions.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory_regions.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory_regions.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_shim.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_shim.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_shim.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_shim.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/dmic_regs_ace2x.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/dmic_regs_ace2x.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/dmic_regs_ace2x.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/dmic_regs_ace2x.h diff --git a/soc/xtensa/intel_adsp/ace/irq.c b/soc/intel/intel_adsp/ace/irq.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/irq.c rename to soc/intel/intel_adsp/ace/irq.c diff --git a/soc/xtensa/intel_adsp/ace/linker.ld b/soc/intel/intel_adsp/ace/linker.ld similarity index 100% rename from soc/xtensa/intel_adsp/ace/linker.ld rename to soc/intel/intel_adsp/ace/linker.ld diff --git a/soc/xtensa/intel_adsp/ace/multiprocessing.c b/soc/intel/intel_adsp/ace/multiprocessing.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/multiprocessing.c rename to soc/intel/intel_adsp/ace/multiprocessing.c diff --git a/soc/xtensa/intel_adsp/ace/pmc_interface.h b/soc/intel/intel_adsp/ace/pmc_interface.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/pmc_interface.h rename to soc/intel/intel_adsp/ace/pmc_interface.h diff --git a/soc/xtensa/intel_adsp/ace/power.c b/soc/intel/intel_adsp/ace/power.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/power.c rename to soc/intel/intel_adsp/ace/power.c diff --git a/soc/xtensa/intel_adsp/ace/power_down.S b/soc/intel/intel_adsp/ace/power_down.S similarity index 100% rename from soc/xtensa/intel_adsp/ace/power_down.S rename to soc/intel/intel_adsp/ace/power_down.S diff --git a/soc/xtensa/intel_adsp/ace/sram.c b/soc/intel/intel_adsp/ace/sram.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/sram.c rename to soc/intel/intel_adsp/ace/sram.c diff --git a/soc/xtensa/intel_adsp/ace/timestamp.c b/soc/intel/intel_adsp/ace/timestamp.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/timestamp.c rename to soc/intel/intel_adsp/ace/timestamp.c diff --git a/soc/intel/intel_adsp/cavs/CMakeLists.txt b/soc/intel/intel_adsp/cavs/CMakeLists.txt new file mode 100644 index 00000000000..5c253147aee --- /dev/null +++ b/soc/intel/intel_adsp/cavs/CMakeLists.txt @@ -0,0 +1,22 @@ +# Intel ADSP SoCs family CMake file +# +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) +zephyr_include_directories(include/${SOC_TOOLCHAIN_NAME}) +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_library_sources( + sram.c + power.c + power_down_cavs.S + ) + +if(CONFIG_SMP OR CONFIG_MP_MAX_NUM_CPUS GREATER 1) + zephyr_library_sources(multiprocessing.c) +endif() + +zephyr_library_sources_ifdef(CONFIG_CAVS_ICTL irq.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/include/xtensa-cavs-linker.ld CACHE INTERNAL "") diff --git a/soc/intel/intel_adsp/cavs/Kconfig b/soc/intel/intel_adsp/cavs/Kconfig new file mode 100644 index 00000000000..01d325cc325 --- /dev/null +++ b/soc/intel/intel_adsp/cavs/Kconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2017,2022-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_INTEL_ADSP_CAVS + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")) + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" + select ATOMIC_OPERATIONS_ARCH if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xcc" + select ARCH_HAS_COHERENCE + select HAS_PM + +config SOC_INTEL_CAVS_V25 + select XTENSA_WAITI_BUG + select SCHED_IPI_SUPPORTED diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 b/soc/intel/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 similarity index 88% rename from soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 rename to soc/intel/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 index f983aa27bb7..ad6fa8baac6 100644 --- a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 +++ b/soc/intel/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 @@ -1,15 +1,8 @@ -# Copyright (c) 2020,2022 Intel Corporation +# Copyright (c) 2020,2022-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 if SOC_INTEL_CAVS_V25 -config SOC_TOOLCHAIN_NAME - string - default "intel_tgl_adsp" - -config SOC - default "intel_tgl_adsp" - # For backward compatibility, to be removed config SOC_SERIES_INTEL_CAVS_V25 def_bool y diff --git a/soc/intel/intel_adsp/cavs/Kconfig.defconfig.series b/soc/intel/intel_adsp/cavs/Kconfig.defconfig.series new file mode 100644 index 00000000000..6b39e8bc930 --- /dev/null +++ b/soc/intel/intel_adsp/cavs/Kconfig.defconfig.series @@ -0,0 +1,47 @@ +# Copyright (c) 2020-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_INTEL_ADSP_CAVS + +config INTEL_ADSP_CAVS + def_bool y + +rsource "Kconfig.defconfig.cavs*" + +config DMA_INTEL_ADSP_GPDMA + default y + depends on DMA + +config XTENSA_CCOUNT_HZ + default 400000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 50000 + +config SMP + default y + +config XTENSA_TIMER + default n + +config KERNEL_ENTRY + default "_MainEntry" + +config MULTI_LEVEL_INTERRUPTS + default y + +config 2ND_LEVEL_INTERRUPTS + default y + +config DYNAMIC_INTERRUPTS + default y + +if LOG + +config LOG_BACKEND_ADSP + default y + +endif # LOG + +endif # SOC_SERIES_INTEL_ADSP_CAVS diff --git a/soc/intel/intel_adsp/cavs/Kconfig.soc b/soc/intel/intel_adsp/cavs/Kconfig.soc new file mode 100644 index 00000000000..40bac2f99cc --- /dev/null +++ b/soc/intel/intel_adsp/cavs/Kconfig.soc @@ -0,0 +1,24 @@ +# Copyright (c) 2020-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_INTEL_ADSP_CAVS + bool + select SOC_FAMILY_INTEL_ADSP + help + Intel ADSP CAVS + +config SOC_SERIES + default "intel_adsp_cavs" if SOC_SERIES_INTEL_ADSP_CAVS + +config SOC_INTEL_CAVS_V25 + bool + select SOC_SERIES_INTEL_ADSP_CAVS + help + Intel Tiger Lake + +config SOC + default "cavs25" if SOC_INTEL_CAVS_V25 + +config SOC_TOOLCHAIN_NAME + default "intel_tgl_adsp" if SOC_INTEL_CAVS_V25 diff --git a/soc/xtensa/intel_adsp/common/include/_soc_inthandlers.h b/soc/intel/intel_adsp/cavs/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/_soc_inthandlers.h rename to soc/intel/intel_adsp/cavs/_soc_inthandlers.h diff --git a/soc/xtensa/intel_adsp/cavs/asm_ldo_management.h b/soc/intel/intel_adsp/cavs/asm_ldo_management.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/asm_ldo_management.h rename to soc/intel/intel_adsp/cavs/asm_ldo_management.h diff --git a/soc/xtensa/intel_adsp/cavs/asm_memory_management.h b/soc/intel/intel_adsp/cavs/asm_memory_management.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/asm_memory_management.h rename to soc/intel/intel_adsp/cavs/asm_memory_management.h diff --git a/soc/xtensa/intel_adsp/cavs/include/adsp_interrupt.h b/soc/intel/intel_adsp/cavs/include/adsp_interrupt.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/adsp_interrupt.h rename to soc/intel/intel_adsp/cavs/include/adsp_interrupt.h diff --git a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_imr_layout.h b/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_imr_layout.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_imr_layout.h rename to soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_imr_layout.h diff --git a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_ipc_regs.h b/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_ipc_regs.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_ipc_regs.h rename to soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_ipc_regs.h diff --git a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h b/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h rename to soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h diff --git a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h b/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h rename to soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h diff --git a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h b/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h rename to soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h diff --git a/soc/xtensa/intel_adsp/cavs/include/xtensa-cavs-linker.ld b/soc/intel/intel_adsp/cavs/include/xtensa-cavs-linker.ld similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/xtensa-cavs-linker.ld rename to soc/intel/intel_adsp/cavs/include/xtensa-cavs-linker.ld diff --git a/soc/xtensa/intel_adsp/cavs/irq.c b/soc/intel/intel_adsp/cavs/irq.c similarity index 100% rename from soc/xtensa/intel_adsp/cavs/irq.c rename to soc/intel/intel_adsp/cavs/irq.c diff --git a/soc/xtensa/intel_adsp/cavs/multiprocessing.c b/soc/intel/intel_adsp/cavs/multiprocessing.c similarity index 100% rename from soc/xtensa/intel_adsp/cavs/multiprocessing.c rename to soc/intel/intel_adsp/cavs/multiprocessing.c diff --git a/soc/xtensa/intel_adsp/cavs/power.c b/soc/intel/intel_adsp/cavs/power.c similarity index 100% rename from soc/xtensa/intel_adsp/cavs/power.c rename to soc/intel/intel_adsp/cavs/power.c diff --git a/soc/xtensa/intel_adsp/cavs/power_down_cavs.S b/soc/intel/intel_adsp/cavs/power_down_cavs.S similarity index 100% rename from soc/xtensa/intel_adsp/cavs/power_down_cavs.S rename to soc/intel/intel_adsp/cavs/power_down_cavs.S diff --git a/soc/xtensa/intel_adsp/cavs/sram.c b/soc/intel/intel_adsp/cavs/sram.c similarity index 100% rename from soc/xtensa/intel_adsp/cavs/sram.c rename to soc/intel/intel_adsp/cavs/sram.c diff --git a/soc/intel/intel_adsp/common/CMakeLists.txt b/soc/intel/intel_adsp/common/CMakeLists.txt new file mode 100644 index 00000000000..11d8ca67c8b --- /dev/null +++ b/soc/intel/intel_adsp/common/CMakeLists.txt @@ -0,0 +1,149 @@ +# Intel CAVS SoC family CMake file +# +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_interface_library_named(INTEL_ADSP_COMMON) + +zephyr_library_named(intel_adsp_common) +zephyr_include_directories(include) +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_library_sources_ifdef(CONFIG_INTEL_ADSP_IPC ipc.c) + +zephyr_library_sources( + rimage_modules.c + boot.c + soc.c + mem_window.c + boot_complete.c + ) + +zephyr_library_sources_ifdef(CONFIG_ADSP_CLOCK clk.c) + +if(CONFIG_SMP OR CONFIG_MP_MAX_NUM_CPUS GREATER 1) + zephyr_library_sources(multiprocessing.c) +endif() + +zephyr_library_link_libraries(INTEL_ADSP_COMMON) + +target_include_directories(INTEL_ADSP_COMMON INTERFACE include) +target_link_libraries(INTEL_ADSP_COMMON INTERFACE intel_adsp_common) + +set(KERNEL_REMAPPED ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}-remapped.elf) +set(EXTMAN ${CMAKE_BINARY_DIR}/zephyr/extman.bin) + +if(${CMAKE_HOST_WIN32}) + set(NULL_FILE nul) +elseif(${CMAKE_HOST_UNIX}) + set(NULL_FILE /dev/null) +endif() + +# Generate rimage modules from the base kernel ELF file. Note the +# warning squashing on the objcopy steps. Binutils has a misfeature +# where if the copy removes all the sections from an input ELF program +# header (our link generates lots of phdrs because of the disjoint +# cacheability addresses), it will warn about an "empty" segment even +# though it was TOLD to drop the contents! +# +# Also note that rimage is picky with section flags: it will try to +# include a section in the output data (even its own metadata in +# .module!) if it has any of ALLOC, WRITABLE or EXEC flags in the ELF +# file. The GNU linker will set these automatically based on the +# flags of the sections coming out of C code, so this is fragile and +# breaks easily. Set noload flags explicitly here. +add_custom_target( + gen_modules ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod +) + +add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod + COMMENT "Extracting .mod(ule) files for rimage" + DEPENDS ${ZEPHYR_FINAL_EXECUTABLE} ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} + + # The .fw_metadata section may not be present (xcc's older linker + # will remove it if empty). Extract it here (which will create an + # empty file if not present) and add it back when we generate the + # main.mod file below. + COMMAND ${CMAKE_OBJCOPY} -O binary --only-section=.fw_metadata + ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}.elf ${EXTMAN} + + # Remap uncached section addresses so they appear contiguous + COMMAND ${CMAKE_COMMAND} -E + copy ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}.elf ${KERNEL_REMAPPED} + + # Extract modules for rimage + COMMAND ${CMAKE_OBJCOPY} + --only-section .imr + --only-section .imrdata + --only-section .module.boot + --set-section-flags .module.boot=noload,readonly + --rename-section .module.boot=.module + ${KERNEL_REMAPPED} ${CMAKE_BINARY_DIR}/zephyr/boot.mod 2>${NULL_FILE} + + # Remove .fw_metadata here... + COMMAND ${CMAKE_OBJCOPY} + --remove-section .imr + --remove-section .imrdata + --remove-section .module.boot + --remove-section .fw_metadata + --set-section-flags .module.main=noload,readonly + --set-section-flags .static_uuid_entries=noload,readonly + --set-section-flags .static_log_entries=noload,readonly + --rename-section .module.main=.module + ${KERNEL_REMAPPED} ${CMAKE_BINARY_DIR}/zephyr/main.mod 2>${NULL_FILE} + + # ...and copy it back in + COMMAND ${CMAKE_OBJCOPY} + --add-section .fw_metadata=${EXTMAN} + --set-section-flags .fw_metadata=noload,readonly + ${CMAKE_BINARY_DIR}/zephyr/main.mod + ${CMAKE_BINARY_DIR}/zephyr/main.mod 2>${NULL_FILE} +) + +if(CONFIG_BUILD_OUTPUT_STRIPPED) +add_custom_command( + COMMENT "strip main.mod" + APPEND OUTPUT ${CMAKE_BINARY_DIR}/zephyr/main.mod + COMMAND $ + $ + $ + $${CMAKE_BINARY_DIR}/zephyr/main.mod + $${CMAKE_BINARY_DIR}/zephyr/main-stripped.mod + $ +) +endif() + + +# west sign +add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri +) + +# If some of your board(s) need to override default rimage parameters +# then you can define WEST_SIGN_OPTS in boards/my/board/board.cmake. +# Example: +# +# set(WEST_SIGN_OPTS -- -c "/home/sweet home/rimage/config/abc.toml" -i 4) + +# Parameters after the double dash -- are passed through to rimage. For +# other ways to override default rimage parameters check +# boards/intel/adsp/doc/intel_adsp_generic.rst + +# Warning: because `west sign` can also be used interactively, using +# ${WEST_SIGN_OPTS} like this has _higher_ precedence than `west config +# rimage.extra-args`! Avoid overriding default rimage parameters in +# multiple places to avoid unexpected precedence rules. +add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + # Use --if-tool-available so we don't force every CI to install + # rimage. We don't want to break build-only and other tests that don't + # require signing. When rimage is missing, `west flash` fails with a + # clear "zephyr.ri missing" error with an "rimage not found" warning + # from west sign immediately before it. + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS gen_modules + ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod +) diff --git a/soc/xtensa/intel_adsp/common/boot.c b/soc/intel/intel_adsp/common/boot.c similarity index 98% rename from soc/xtensa/intel_adsp/common/boot.c rename to soc/intel/intel_adsp/common/boot.c index 75eed9d63b0..ad7f91eec7d 100644 --- a/soc/xtensa/intel_adsp/common/boot.c +++ b/soc/intel/intel_adsp/common/boot.c @@ -44,7 +44,7 @@ #define MANIFEST_SEGMENT_COUNT 3 /* FIXME: Use Kconfig or some other means */ -#if !defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if !defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) #define RESET_MEMORY_HOLE #endif diff --git a/soc/xtensa/intel_adsp/common/boot_complete.c b/soc/intel/intel_adsp/common/boot_complete.c similarity index 100% rename from soc/xtensa/intel_adsp/common/boot_complete.c rename to soc/intel/intel_adsp/common/boot_complete.c diff --git a/soc/xtensa/intel_adsp/common/clk.c b/soc/intel/intel_adsp/common/clk.c similarity index 96% rename from soc/xtensa/intel_adsp/common/clk.c rename to soc/intel/intel_adsp/common/clk.c index 0f3f3d32b80..f9a35a3c018 100644 --- a/soc/xtensa/intel_adsp/common/clk.c +++ b/soc/intel/intel_adsp/common/clk.c @@ -26,7 +26,7 @@ static void select_cpu_clock_hw(uint32_t freq_idx) { uint32_t enc = adsp_clock_freq_enc[freq_idx]; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE uint32_t clk_ctl = ADSP_CLKCTL; clk_ctl &= ~ADSP_CLKCTL_OSC_SOURCE_MASK; @@ -89,7 +89,7 @@ void adsp_clock_init(void) int i; #ifdef ADSP_CLOCK_HAS_WOVCRO -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE ACE_DfPMCCU.dfclkctl |= ACE_CLKCTL_WOVCRO; if (ACE_DfPMCCU.dfclkctl & ACE_CLKCTL_WOVCRO) { ACE_DfPMCCU.dfclkctl = ACE_DfPMCCU.dfclkctl & ~ACE_CLKCTL_WOVCRO; @@ -103,7 +103,7 @@ void adsp_clock_init(void) } else { platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_LPRO; } -#endif /* CONFIG_SOC_SERIES_INTEL_ACE */ +#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */ #endif /* ADSP_CLOCK_HAS_WOVCRO */ unsigned int num_cpus = arch_num_cpus(); diff --git a/soc/xtensa/intel_adsp/common/include/adsp-vectors.h b/soc/intel/intel_adsp/common/include/adsp-vectors.h similarity index 95% rename from soc/xtensa/intel_adsp/common/include/adsp-vectors.h rename to soc/intel/intel_adsp/common/include/adsp-vectors.h index 383dce93aa3..01e660e43ea 100644 --- a/soc/xtensa/intel_adsp/common/include/adsp-vectors.h +++ b/soc/intel/intel_adsp/common/include/adsp-vectors.h @@ -24,13 +24,13 @@ #define INTLEVEL4_VECTOR_PADDR_SRAM \ (VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL4_VECOFS) -#ifndef SOC_SERIES_INTEL_ACE +#ifndef SOC_SERIES_INTEL_ADSP_ACE #define INTLEVEL5_VECTOR_PADDR_SRAM \ (VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL5_VECOFS) #define INTLEVEL6_VECTOR_PADDR_SRAM \ (VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL6_VECOFS) -#endif /* SOC_SERIES_INTEL_ACE */ +#endif /* SOC_SERIES_INTEL_ADSP_ACE */ #define INTLEVEL7_VECTOR_PADDR_SRAM \ diff --git a/soc/xtensa/intel_adsp/common/include/adsp_clk.h b/soc/intel/intel_adsp/common/include/adsp_clk.h similarity index 98% rename from soc/xtensa/intel_adsp/common/include/adsp_clk.h rename to soc/intel/intel_adsp/common/include/adsp_clk.h index 34d7c21822d..ccfb5cdc7e7 100644 --- a/soc/xtensa/intel_adsp/common/include/adsp_clk.h +++ b/soc/intel/intel_adsp/common/include/adsp_clk.h @@ -36,7 +36,7 @@ int adsp_clock_set_cpu_freq(uint32_t freq_idx); struct adsp_cpu_clock_info *adsp_cpu_clocks_get(void); /* Device tree defined constants */ -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE #define ADSP_CLKCTL ACE_DfPMCCU.dfclkctl #else #define ADSP_CLKCTL CAVS_SHIM.clkctl diff --git a/soc/xtensa/intel_adsp/common/include/adsp_debug_window.h b/soc/intel/intel_adsp/common/include/adsp_debug_window.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/adsp_debug_window.h rename to soc/intel/intel_adsp/common/include/adsp_debug_window.h diff --git a/soc/xtensa/intel_adsp/common/include/cavs-idc.h b/soc/intel/intel_adsp/common/include/cavs-idc.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/cavs-idc.h rename to soc/intel/intel_adsp/common/include/cavs-idc.h diff --git a/soc/xtensa/intel_adsp/common/include/cavstool.h b/soc/intel/intel_adsp/common/include/cavstool.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/cavstool.h rename to soc/intel/intel_adsp/common/include/cavstool.h diff --git a/soc/xtensa/intel_adsp/common/include/cpu_init.h b/soc/intel/intel_adsp/common/include/cpu_init.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/cpu_init.h rename to soc/intel/intel_adsp/common/include/cpu_init.h diff --git a/soc/xtensa/intel_adsp/common/include/debug_helpers.h b/soc/intel/intel_adsp/common/include/debug_helpers.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/debug_helpers.h rename to soc/intel/intel_adsp/common/include/debug_helpers.h diff --git a/soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h b/soc/intel/intel_adsp/common/include/intel_adsp_hda.h similarity index 99% rename from soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h rename to soc/intel/intel_adsp/common/include/intel_adsp_hda.h index f56c77e2523..628a84cd1a0 100644 --- a/soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h +++ b/soc/intel/intel_adsp/common/include/intel_adsp_hda.h @@ -446,14 +446,14 @@ static inline void intel_adsp_hda_disable_buffer_interrupt(uint32_t base, uint32 static inline void intel_adsp_force_dmi_l0_state(void) { -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE ACE_DfPMCCH.svcfg |= ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT; #endif } static inline void intel_adsp_allow_dmi_l1_state(void) { -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE ACE_DfPMCCH.svcfg &= ~(ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT); #endif } diff --git a/soc/xtensa/intel_adsp/common/include/intel_adsp_ipc.h b/soc/intel/intel_adsp/common/include/intel_adsp_ipc.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/intel_adsp_ipc.h rename to soc/intel/intel_adsp/common/include/intel_adsp_ipc.h diff --git a/soc/xtensa/intel_adsp/common/include/intel_adsp_ipc_devtree.h b/soc/intel/intel_adsp/common/include/intel_adsp_ipc_devtree.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/intel_adsp_ipc_devtree.h rename to soc/intel/intel_adsp/common/include/intel_adsp_ipc_devtree.h diff --git a/soc/xtensa/intel_adsp/common/include/manifest.h b/soc/intel/intel_adsp/common/include/manifest.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/manifest.h rename to soc/intel/intel_adsp/common/include/manifest.h diff --git a/soc/xtensa/intel_adsp/common/include/mem_window.h b/soc/intel/intel_adsp/common/include/mem_window.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/mem_window.h rename to soc/intel/intel_adsp/common/include/mem_window.h diff --git a/soc/xtensa/intel_adsp/common/include/soc.h b/soc/intel/intel_adsp/common/include/soc.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/soc.h rename to soc/intel/intel_adsp/common/include/soc.h diff --git a/soc/xtensa/intel_adsp/common/include/soc_util.h b/soc/intel/intel_adsp/common/include/soc_util.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/soc_util.h rename to soc/intel/intel_adsp/common/include/soc_util.h diff --git a/soc/xtensa/intel_adsp/common/ipc.c b/soc/intel/intel_adsp/common/ipc.c similarity index 98% rename from soc/xtensa/intel_adsp/common/ipc.c rename to soc/intel/intel_adsp/common/ipc.c index 6ae1956ffac..a73d696a68a 100644 --- a/soc/xtensa/intel_adsp/common/ipc.c +++ b/soc/intel/intel_adsp/common/ipc.c @@ -55,7 +55,7 @@ void z_intel_adsp_ipc_isr(const void *devarg) regs->tdr = INTEL_ADSP_IPC_BUSY; if (done) { -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; #else regs->tda = INTEL_ADSP_IPC_DONE; @@ -100,7 +100,7 @@ int intel_adsp_ipc_init(const struct device *dev) */ config->regs->tdr = INTEL_ADSP_IPC_BUSY; config->regs->ida = INTEL_ADSP_IPC_DONE; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE config->regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; #else config->regs->tda = INTEL_ADSP_IPC_DONE; @@ -115,7 +115,7 @@ void intel_adsp_ipc_complete(const struct device *dev) { const struct intel_adsp_ipc_config *config = dev->config; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE config->regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; #else config->regs->tda = INTEL_ADSP_IPC_DONE; @@ -208,7 +208,7 @@ void intel_adsp_ipc_send_message_emergency(const struct device *dev, uint32_t da #if DT_NODE_EXISTS(INTEL_ADSP_IPC_HOST_DTNODE) -#if defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) static inline void ace_ipc_intc_unmask(void) { ACE_DINT[0].ie[ACE_INTL_HIPC] = BIT(0); diff --git a/soc/xtensa/intel_adsp/common/mem_window.c b/soc/intel/intel_adsp/common/mem_window.c similarity index 100% rename from soc/xtensa/intel_adsp/common/mem_window.c rename to soc/intel/intel_adsp/common/mem_window.c diff --git a/soc/xtensa/intel_adsp/common/multiprocessing.c b/soc/intel/intel_adsp/common/multiprocessing.c similarity index 100% rename from soc/xtensa/intel_adsp/common/multiprocessing.c rename to soc/intel/intel_adsp/common/multiprocessing.c diff --git a/soc/xtensa/intel_adsp/common/rimage_modules.c b/soc/intel/intel_adsp/common/rimage_modules.c similarity index 100% rename from soc/xtensa/intel_adsp/common/rimage_modules.c rename to soc/intel/intel_adsp/common/rimage_modules.c diff --git a/soc/xtensa/intel_adsp/common/soc.c b/soc/intel/intel_adsp/common/soc.c similarity index 100% rename from soc/xtensa/intel_adsp/common/soc.c rename to soc/intel/intel_adsp/common/soc.c diff --git a/soc/intel/intel_adsp/soc.yml b/soc/intel/intel_adsp/soc.yml new file mode 100644 index 00000000000..757750eeb37 --- /dev/null +++ b/soc/intel/intel_adsp/soc.yml @@ -0,0 +1,10 @@ +family: + - name: intel_adsp + series: + - name: intel_adsp_ace + socs: + - name: ace15_mtpm + - name: ace20_lnl + - name: intel_adsp_cavs + socs: + - name: cavs25 diff --git a/soc/xtensa/intel_adsp/tools/acetool.py b/soc/intel/intel_adsp/tools/acetool.py similarity index 99% rename from soc/xtensa/intel_adsp/tools/acetool.py rename to soc/intel/intel_adsp/tools/acetool.py index 0d0897c0234..9dd184b9685 100755 --- a/soc/xtensa/intel_adsp/tools/acetool.py +++ b/soc/intel/intel_adsp/tools/acetool.py @@ -35,6 +35,8 @@ INBOX_OFFSET = (512 + (1 * 128)) * 1024 WINSTREAM_OFFSET = WINDOW_BASE + WINDOW_STRIDE*3 +# pylint: disable=duplicate-code + # ADSPCS bits CRST = 0 CSTALL = 8 diff --git a/soc/xtensa/intel_adsp/tools/cavstool.py b/soc/intel/intel_adsp/tools/cavstool.py similarity index 99% rename from soc/xtensa/intel_adsp/tools/cavstool.py rename to soc/intel/intel_adsp/tools/cavstool.py index a28d3c20321..97ce9134379 100755 --- a/soc/xtensa/intel_adsp/tools/cavstool.py +++ b/soc/intel/intel_adsp/tools/cavstool.py @@ -31,6 +31,8 @@ INBOX_OFFSET = (512 + (1 * 128)) * 1024 WINSTREAM_OFFSET = (512 + (3 * 128)) * 1024 +# pylint: disable=duplicate-code + # ADSPCS bits CRST = 0 CSTALL = 8 diff --git a/soc/xtensa/intel_adsp/tools/cavstool_client.py b/soc/intel/intel_adsp/tools/cavstool_client.py similarity index 100% rename from soc/xtensa/intel_adsp/tools/cavstool_client.py rename to soc/intel/intel_adsp/tools/cavstool_client.py diff --git a/soc/xtensa/intel_adsp/tools/cavstwist.sh b/soc/intel/intel_adsp/tools/cavstwist.sh similarity index 94% rename from soc/xtensa/intel_adsp/tools/cavstwist.sh rename to soc/intel/intel_adsp/tools/cavstwist.sh index d965ff26ca3..89af3434317 100755 --- a/soc/xtensa/intel_adsp/tools/cavstwist.sh +++ b/soc/intel/intel_adsp/tools/cavstwist.sh @@ -1,5 +1,5 @@ #!/bin/sh -# Copyright (c) 2022 Intel Corporation +# Copyright (c) 2022-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 set -e @@ -12,9 +12,9 @@ set -e # export CAVS_KEY=$HOME/otc_private_key_3k.pem # export CAVS_RIMAGE=$HOME/rimage # -# twister -p intel_adsp_cavs25 --device-testing \ -# --device-serial-pty=$ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstwist.sh \ -# --west-flash=$ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstwist.sh +# twister -p intel_adsp/cavs25 --device-testing \ +# --device-serial-pty=$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstwist.sh \ +# --west-flash=$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstwist.sh # # The CAVS_OLD_FLASHER is necessary because now the client-server-based # cavstool works by default. This is to tell the build system to use @@ -80,7 +80,7 @@ fi ######################################################################## -CAVSTOOL=$ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstool.py +CAVSTOOL=$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstool.py IMAGE=$ZEPHYR_BASE/_cavstmp.ri IMAGE2=$ZEPHYR_BASE/_cavstmp2.ri diff --git a/soc/xtensa/intel_adsp/tools/remote-fw-service.py b/soc/intel/intel_adsp/tools/remote-fw-service.py similarity index 99% rename from soc/xtensa/intel_adsp/tools/remote-fw-service.py rename to soc/intel/intel_adsp/tools/remote-fw-service.py index 21e3569721c..1d68a7db2a1 100755 --- a/soc/xtensa/intel_adsp/tools/remote-fw-service.py +++ b/soc/intel/intel_adsp/tools/remote-fw-service.py @@ -17,6 +17,8 @@ # Global variable use to sync between log and request services. runner = None +# pylint: disable=duplicate-code + # INADDR_ANY as default HOST = '' PORT_LOG = 9999 diff --git a/soc/x86/intel_ish/CMakeLists.txt b/soc/intel/intel_ish/CMakeLists.txt similarity index 100% rename from soc/x86/intel_ish/CMakeLists.txt rename to soc/intel/intel_ish/CMakeLists.txt diff --git a/soc/intel/intel_ish/Kconfig b/soc/intel/intel_ish/Kconfig new file mode 100644 index 00000000000..31568e85d65 --- /dev/null +++ b/soc/intel/intel_ish/Kconfig @@ -0,0 +1,15 @@ +# Intel ISH family configuration options +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_ISH + select X86 + select X86_NO_SPECULATIVE_VULNERABILITIES + select IOAPIC + select LOAPIC + select CPU_HAS_FPU + select INTEL_HAL + select HAS_PM + select HAS_COVERAGE_SUPPORT diff --git a/soc/intel/intel_ish/Kconfig.defconfig b/soc/intel/intel_ish/Kconfig.defconfig new file mode 100644 index 00000000000..e944782809e --- /dev/null +++ b/soc/intel/intel_ish/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Intel ISH family default configuration options +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_ISH + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 if HPET_TIMER + +config X86_VERY_EARLY_CONSOLE + default n + +config SRAM_OFFSET + hex + default 0x0 + +# Target platforms are not PC-compatible +# (e.g. without BIOS, ACPI, CMOS, etc.). +config X86_PC_COMPATIBLE + default n + +rsource "*/Kconfig.defconfig.series" + +endif # SOC_FAMILY_INTEL_ISH diff --git a/soc/intel/intel_ish/Kconfig.soc b/soc/intel/intel_ish/Kconfig.soc new file mode 100644 index 00000000000..c08d5f15f4a --- /dev/null +++ b/soc/intel/intel_ish/Kconfig.soc @@ -0,0 +1,13 @@ +# Intel ISH family selection +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_ISH + bool + +config SOC_FAMILY + default "intel_ish" if SOC_FAMILY_INTEL_ISH + +rsource "*/Kconfig.soc" diff --git a/soc/x86/intel_ish/doc/supported_features.txt b/soc/intel/intel_ish/doc/supported_features.txt similarity index 100% rename from soc/x86/intel_ish/doc/supported_features.txt rename to soc/intel/intel_ish/doc/supported_features.txt diff --git a/soc/intel/intel_ish/intel_ish5/CMakeLists.txt b/soc/intel/intel_ish/intel_ish5/CMakeLists.txt new file mode 100644 index 00000000000..dce4b9cc906 --- /dev/null +++ b/soc/intel/intel_ish/intel_ish5/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(.) + +zephyr_cc_option(-march=pentium -mtune=i486) + +zephyr_sources(soc.c) +add_subdirectory_ifdef(CONFIG_PM pm) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") + +include(../utils/build_ish_firmware.cmake) diff --git a/soc/intel/intel_ish/intel_ish5/Kconfig.defconfig.series b/soc/intel/intel_ish/intel_ish5/Kconfig.defconfig.series new file mode 100644 index 00000000000..8b8fea9f29a --- /dev/null +++ b/soc/intel/intel_ish/intel_ish5/Kconfig.defconfig.series @@ -0,0 +1,10 @@ +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_INTEL_ISH5 + +rsource "pm/Kconfig.pm" + +endif # SOC_SERIES_INTEL_ISH5 diff --git a/soc/intel/intel_ish/intel_ish5/Kconfig.soc b/soc/intel/intel_ish/intel_ish5/Kconfig.soc new file mode 100644 index 00000000000..37c1990ca3f --- /dev/null +++ b/soc/intel/intel_ish/intel_ish5/Kconfig.soc @@ -0,0 +1,27 @@ +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_INTEL_ISH5 + bool + select SOC_FAMILY_INTEL_ISH + +config SOC_SERIES + default "intel_ish5" if SOC_SERIES_INTEL_ISH5 + +config SOC_INTEL_ISH_5_4_1 + bool + select SOC_SERIES_INTEL_ISH5 + +config SOC_INTEL_ISH_5_6_0 + bool + select SOC_SERIES_INTEL_ISH5 + +config SOC_INTEL_ISH_5_8_0 + bool + select SOC_SERIES_INTEL_ISH5 + +config SOC + default "intel_ish_5_4_1" if SOC_INTEL_ISH_5_4_1 + default "intel_ish_5_6_0" if SOC_INTEL_ISH_5_6_0 + default "intel_ish_5_8_0" if SOC_INTEL_ISH_5_8_0 diff --git a/soc/x86/intel_ish/intel_ish5/linker.ld b/soc/intel/intel_ish/intel_ish5/linker.ld similarity index 100% rename from soc/x86/intel_ish/intel_ish5/linker.ld rename to soc/intel/intel_ish/intel_ish5/linker.ld diff --git a/soc/x86/intel_ish/intel_ish5/pm/CMakeLists.txt b/soc/intel/intel_ish/intel_ish5/pm/CMakeLists.txt similarity index 100% rename from soc/x86/intel_ish/intel_ish5/pm/CMakeLists.txt rename to soc/intel/intel_ish/intel_ish5/pm/CMakeLists.txt diff --git a/soc/x86/intel_ish/intel_ish5/pm/Kconfig.pm b/soc/intel/intel_ish/intel_ish5/pm/Kconfig.pm similarity index 100% rename from soc/x86/intel_ish/intel_ish5/pm/Kconfig.pm rename to soc/intel/intel_ish/intel_ish5/pm/Kconfig.pm diff --git a/soc/x86/intel_ish/intel_ish5/pm/power.c b/soc/intel/intel_ish/intel_ish5/pm/power.c similarity index 100% rename from soc/x86/intel_ish/intel_ish5/pm/power.c rename to soc/intel/intel_ish/intel_ish5/pm/power.c diff --git a/soc/x86/intel_ish/intel_ish5/soc.c b/soc/intel/intel_ish/intel_ish5/soc.c similarity index 100% rename from soc/x86/intel_ish/intel_ish5/soc.c rename to soc/intel/intel_ish/intel_ish5/soc.c diff --git a/soc/x86/intel_ish/intel_ish5/soc.h b/soc/intel/intel_ish/intel_ish5/soc.h similarity index 100% rename from soc/x86/intel_ish/intel_ish5/soc.h rename to soc/intel/intel_ish/intel_ish5/soc.h diff --git a/soc/intel/intel_ish/soc.yml b/soc/intel/intel_ish/soc.yml new file mode 100644 index 00000000000..ff1330c85f5 --- /dev/null +++ b/soc/intel/intel_ish/soc.yml @@ -0,0 +1,8 @@ +family: + - name: intel_ish + series: + - name: intel_ish5 + socs: + - name: intel_ish_5_4_1 + - name: intel_ish_5_6_0 + - name: intel_ish_5_8_0 diff --git a/soc/x86/intel_ish/utils/build_ish_firmware.cmake b/soc/intel/intel_ish/utils/build_ish_firmware.cmake similarity index 100% rename from soc/x86/intel_ish/utils/build_ish_firmware.cmake rename to soc/intel/intel_ish/utils/build_ish_firmware.cmake diff --git a/soc/x86/intel_ish/utils/build_ish_firmware.py b/soc/intel/intel_ish/utils/build_ish_firmware.py similarity index 100% rename from soc/x86/intel_ish/utils/build_ish_firmware.py rename to soc/intel/intel_ish/utils/build_ish_firmware.py diff --git a/soc/intel/intel_niosv/CMakeLists.txt b/soc/intel/intel_niosv/CMakeLists.txt new file mode 100644 index 00000000000..c75ca7f4eb3 --- /dev/null +++ b/soc/intel/intel_niosv/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/intel/intel_niosv/Kconfig b/soc/intel/intel_niosv/Kconfig new file mode 100644 index 00000000000..a3221149249 --- /dev/null +++ b/soc/intel/intel_niosv/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_NIOSV + +rsource "*/Kconfig" + +endif # SOC_FAMILY_INTEL_NIOSV diff --git a/soc/intel/intel_niosv/Kconfig.defconfig b/soc/intel/intel_niosv/Kconfig.defconfig new file mode 100644 index 00000000000..b9ae19a1244 --- /dev/null +++ b/soc/intel/intel_niosv/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_NIOSV + +rsource "*/Kconfig.defconfig.series" + +endif diff --git a/soc/intel/intel_niosv/Kconfig.soc b/soc/intel/intel_niosv/Kconfig.soc new file mode 100644 index 00000000000..1d1d2ebe658 --- /dev/null +++ b/soc/intel/intel_niosv/Kconfig.soc @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_NIOSV + bool + +config SOC_FAMILY + default "intel_niosv" if SOC_FAMILY_INTEL_NIOSV + +rsource "*/Kconfig.soc" diff --git a/soc/riscv/intel_niosv/niosv/CMakeLists.txt b/soc/intel/intel_niosv/niosv/CMakeLists.txt similarity index 100% rename from soc/riscv/intel_niosv/niosv/CMakeLists.txt rename to soc/intel/intel_niosv/niosv/CMakeLists.txt diff --git a/soc/intel/intel_niosv/niosv/Kconfig b/soc/intel/intel_niosv/niosv/Kconfig new file mode 100644 index 00000000000..6d479238501 --- /dev/null +++ b/soc/intel/intel_niosv/niosv/Kconfig @@ -0,0 +1,22 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NIOSV + select RISCV + select RISCV_PRIVILEGED + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + +config SOC_NIOSV_M + help + Intel FPGA NIOSV Microcontroller Core Processor + +config SOC_NIOSV_G + select RISCV_ISA_EXT_M + help + Intel FPGA NIOSV General Purpose Processor diff --git a/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series b/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series new file mode 100644 index 00000000000..4d859d24e4e --- /dev/null +++ b/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series @@ -0,0 +1,19 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NIOSV + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config NUM_IRQS # Platform interrupts IRQs index start from index 16 + default 32 + +config RISCV_GP + default y + +config RISCV_SOC_INTERRUPT_INIT + default y + +endif # SOC_SERIES_NIOSV diff --git a/soc/intel/intel_niosv/niosv/Kconfig.soc b/soc/intel/intel_niosv/niosv/Kconfig.soc new file mode 100644 index 00000000000..89574f455fa --- /dev/null +++ b/soc/intel/intel_niosv/niosv/Kconfig.soc @@ -0,0 +1,28 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NIOSV + bool + select SOC_FAMILY_INTEL_NIOSV + help + Intel FPGA NIOSV + +config SOC_SERIES + default "niosv" if SOC_SERIES_NIOSV + +config SOC_NIOSV_M + bool + select SOC_SERIES_NIOSV + help + Intel FPGA NIOSV Microcontroller Core Processor + +config SOC_NIOSV_G + bool + select SOC_SERIES_NIOSV + help + Intel FPGA NIOSV General Purpose Processor + +config SOC + default "niosv_m" if SOC_NIOSV_M + default "niosv_g" if SOC_NIOSV_G diff --git a/soc/riscv/intel_niosv/niosv/linker.ld b/soc/intel/intel_niosv/niosv/linker.ld similarity index 100% rename from soc/riscv/intel_niosv/niosv/linker.ld rename to soc/intel/intel_niosv/niosv/linker.ld diff --git a/soc/intel/intel_niosv/soc.yml b/soc/intel/intel_niosv/soc.yml new file mode 100644 index 00000000000..8dd39822936 --- /dev/null +++ b/soc/intel/intel_niosv/soc.yml @@ -0,0 +1,7 @@ +family: + - name: intel_niosv + series: + - name: niosv + socs: + - name: niosv_g + - name: niosv_m diff --git a/soc/arm64/intel_socfpga/CMakeLists.txt b/soc/intel/intel_socfpga/CMakeLists.txt similarity index 100% rename from soc/arm64/intel_socfpga/CMakeLists.txt rename to soc/intel/intel_socfpga/CMakeLists.txt diff --git a/soc/intel/intel_socfpga/Kconfig b/soc/intel/intel_socfpga/Kconfig new file mode 100644 index 00000000000..c2ea0711414 --- /dev/null +++ b/soc/intel/intel_socfpga/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_SOCFPGA + +rsource "*/Kconfig" + +endif # SOC_FAMILY_INTEL_SOCFPGA diff --git a/soc/intel/intel_socfpga/Kconfig.defconfig b/soc/intel/intel_socfpga/Kconfig.defconfig new file mode 100644 index 00000000000..2b8ba3d8830 --- /dev/null +++ b/soc/intel/intel_socfpga/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_SOCFPGA + +rsource "*/Kconfig.defconfig.series" + +endif # SOC_FAMILY_INTEL_SOCFPGA diff --git a/soc/intel/intel_socfpga/Kconfig.soc b/soc/intel/intel_socfpga/Kconfig.soc new file mode 100644 index 00000000000..2fbdd5797fe --- /dev/null +++ b/soc/intel/intel_socfpga/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_SOCFPGA + bool + +config SOC_FAMILY + default "intel_socfpga" if SOC_FAMILY_INTEL_SOCFPGA + +rsource "*/Kconfig.soc" diff --git a/soc/arm64/intel_socfpga/agilex/CMakeLists.txt b/soc/intel/intel_socfpga/agilex/CMakeLists.txt similarity index 100% rename from soc/arm64/intel_socfpga/agilex/CMakeLists.txt rename to soc/intel/intel_socfpga/agilex/CMakeLists.txt diff --git a/soc/intel/intel_socfpga/agilex/Kconfig b/soc/intel/intel_socfpga/agilex/Kconfig new file mode 100644 index 00000000000..ee59d3528f0 --- /dev/null +++ b/soc/intel/intel_socfpga/agilex/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AGILEX + select ARM64 + select CPU_CORTEX_A53 diff --git a/soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex b/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.agilex similarity index 77% rename from soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex rename to soc/intel/intel_socfpga/agilex/Kconfig.defconfig.agilex index 302b0d779a1..4b147ff0df3 100644 --- a/soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex +++ b/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.agilex @@ -1,11 +1,8 @@ -# Copyright (c) 2021 Intel Corporation +# Copyright (c) 2021-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 if SOC_AGILEX -config SOC - default "intel_socfpga_agilex" - # must be >= the highest interrupt number used # - include the UART interrupts 173 or 204 config NUM_IRQS diff --git a/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.series b/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.series new file mode 100644 index 00000000000..c99f6232858 --- /dev/null +++ b/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.series @@ -0,0 +1,8 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_AGILEX + +rsource "Kconfig.defconfig.agilex*" + +endif # SOC_SERIES_AGILEX diff --git a/soc/intel/intel_socfpga/agilex/Kconfig.soc b/soc/intel/intel_socfpga/agilex/Kconfig.soc new file mode 100644 index 00000000000..c83b1b452f4 --- /dev/null +++ b/soc/intel/intel_socfpga/agilex/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AGILEX + bool + select SOC_FAMILY_INTEL_SOCFPGA + help + Intel SoC FPGA Agilex Series + +config SOC_SERIES + default "agilex" if SOC_SERIES_AGILEX + +config SOC_AGILEX + bool + select SOC_SERIES_AGILEX + help + Intel SoC FPGA Agilex + +config SOC + default "agilex" if SOC_AGILEX diff --git a/soc/arm64/intel_socfpga/agilex/mmu_regions.c b/soc/intel/intel_socfpga/agilex/mmu_regions.c similarity index 100% rename from soc/arm64/intel_socfpga/agilex/mmu_regions.c rename to soc/intel/intel_socfpga/agilex/mmu_regions.c diff --git a/soc/arm64/intel_socfpga/agilex5/CMakeLists.txt b/soc/intel/intel_socfpga/agilex5/CMakeLists.txt similarity index 100% rename from soc/arm64/intel_socfpga/agilex5/CMakeLists.txt rename to soc/intel/intel_socfpga/agilex5/CMakeLists.txt diff --git a/soc/intel/intel_socfpga/agilex5/Kconfig b/soc/intel/intel_socfpga/agilex5/Kconfig new file mode 100644 index 00000000000..5b8b4716ff9 --- /dev/null +++ b/soc/intel/intel_socfpga/agilex5/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AGILEX5 + select ARM64 + select CPU_CORTEX_A76_A55 diff --git a/soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 b/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 similarity index 77% rename from soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 rename to soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 index d34c7880cd4..c072f0c84d7 100644 --- a/soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 +++ b/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 @@ -1,11 +1,8 @@ -# Copyright (c) 2022 Intel Corporation +# Copyright (c) 2022-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 if SOC_AGILEX5 -config SOC - default "intel_socfpga_agilex5" - # must be >= the highest interrupt number used # - include the UART interrupts 173 or 204 config NUM_IRQS diff --git a/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.series b/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.series new file mode 100644 index 00000000000..4f2167d4320 --- /dev/null +++ b/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.series @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_AGILEX5 + +rsource "Kconfig.defconfig.agilex5*" + +endif # SOC_SERIES_AGILEX5 diff --git a/soc/intel/intel_socfpga/agilex5/Kconfig.soc b/soc/intel/intel_socfpga/agilex5/Kconfig.soc new file mode 100644 index 00000000000..4ca2d603326 --- /dev/null +++ b/soc/intel/intel_socfpga/agilex5/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AGILEX5 + bool + select SOC_FAMILY_INTEL_SOCFPGA + help + Intel SoC FPGA Agilex5 Series + +config SOC_SERIES + default "agilex5" if SOC_SERIES_AGILEX5 + +config SOC_AGILEX5 + bool + select SOC_SERIES_AGILEX5 + help + Intel SoC FPGA Agilex5 + +config SOC + default "agilex5" if SOC_AGILEX5 diff --git a/soc/arm64/intel_socfpga/agilex5/mmu_regions.c b/soc/intel/intel_socfpga/agilex5/mmu_regions.c similarity index 100% rename from soc/arm64/intel_socfpga/agilex5/mmu_regions.c rename to soc/intel/intel_socfpga/agilex5/mmu_regions.c diff --git a/soc/arm64/intel_socfpga/common/CMakeLists.txt b/soc/intel/intel_socfpga/common/CMakeLists.txt similarity index 100% rename from soc/arm64/intel_socfpga/common/CMakeLists.txt rename to soc/intel/intel_socfpga/common/CMakeLists.txt diff --git a/soc/arm64/intel_socfpga/common/socfpga_handoff.h b/soc/intel/intel_socfpga/common/socfpga_handoff.h similarity index 100% rename from soc/arm64/intel_socfpga/common/socfpga_handoff.h rename to soc/intel/intel_socfpga/common/socfpga_handoff.h diff --git a/soc/arm64/intel_socfpga/common/socfpga_system_manager.h b/soc/intel/intel_socfpga/common/socfpga_system_manager.h similarity index 100% rename from soc/arm64/intel_socfpga/common/socfpga_system_manager.h rename to soc/intel/intel_socfpga/common/socfpga_system_manager.h diff --git a/soc/intel/intel_socfpga/soc.yml b/soc/intel/intel_socfpga/soc.yml new file mode 100644 index 00000000000..2d3afd3f35e --- /dev/null +++ b/soc/intel/intel_socfpga/soc.yml @@ -0,0 +1,9 @@ +family: + - name: intel_socfpga + series: + - name: agilex + socs: + - name: agilex + - name: agilex5 + socs: + - name: agilex5 diff --git a/soc/intel/intel_socfpga_std/CMakeLists.txt b/soc/intel/intel_socfpga_std/CMakeLists.txt new file mode 100644 index 00000000000..9d71fff8650 --- /dev/null +++ b/soc/intel/intel_socfpga_std/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/intel/intel_socfpga_std/Kconfig b/soc/intel/intel_socfpga_std/Kconfig new file mode 100644 index 00000000000..7d788402691 --- /dev/null +++ b/soc/intel/intel_socfpga_std/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_SOCFPGA_STD + +rsource "*/Kconfig" + +endif # SOC_FAMILY_INTEL_SOCFPGA_STD diff --git a/soc/intel/intel_socfpga_std/Kconfig.defconfig b/soc/intel/intel_socfpga_std/Kconfig.defconfig new file mode 100644 index 00000000000..7fa7a378185 --- /dev/null +++ b/soc/intel/intel_socfpga_std/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_SOCFPGA_STD + +rsource "*/Kconfig.defconfig.series" + +endif # SOC_FAMILY_INTEL_SOCFPGA_STD diff --git a/soc/intel/intel_socfpga_std/Kconfig.soc b/soc/intel/intel_socfpga_std/Kconfig.soc new file mode 100644 index 00000000000..48ed74e216e --- /dev/null +++ b/soc/intel/intel_socfpga_std/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_SOCFPGA_STD + bool + +config SOC_FAMILY + default "intel_socfpga_std" if SOC_FAMILY_INTEL_SOCFPGA_STD + +rsource "*/Kconfig.soc" diff --git a/soc/intel/intel_socfpga_std/cyclonev/CMakeLists.txt b/soc/intel/intel_socfpga_std/cyclonev/CMakeLists.txt new file mode 100644 index 00000000000..698b0ad13b8 --- /dev/null +++ b/soc/intel/intel_socfpga_std/cyclonev/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_sources(soc.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/intel_socfpga_std/cyclonev/Kconfig b/soc/intel/intel_socfpga_std/cyclonev/Kconfig new file mode 100644 index 00000000000..81c51390586 --- /dev/null +++ b/soc/intel/intel_socfpga_std/cyclonev/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CYCLONEV + select ARM + select CPU_CORTEX_A9 + select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER + select ARCH_HAS_RESERVED_PAGE_FRAMES diff --git a/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev new file mode 100644 index 00000000000..c127406f628 --- /dev/null +++ b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev @@ -0,0 +1,14 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_CYCLONEV + +config NUM_IRQS + int + default 211 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 231250000 + +endif diff --git a/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.series b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.series new file mode 100644 index 00000000000..39865caf593 --- /dev/null +++ b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.series @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CYCLONEV + +rsource "Kconfig.defconfig.cyclonev*" + +endif # SOC_SERIES_CYCLONEV diff --git a/soc/intel/intel_socfpga_std/cyclonev/Kconfig.soc b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.soc new file mode 100644 index 00000000000..16811037566 --- /dev/null +++ b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CYCLONEV + bool + select SOC_FAMILY_INTEL_SOCFPGA_STD + help + Intel SoC FPGA Cyclone V Series + +config SOC_SERIES + default "cyclonev" if SOC_SERIES_CYCLONEV + +config SOC_CYCLONEV + bool + select SOC_SERIES_CYCLONEV + help + Intel SoC FPGA Cyclone V + +config SOC + default "cyclonev" if SOC_CYCLONEV diff --git a/soc/arm/intel_socfpga_std/cyclonev/soc.c b/soc/intel/intel_socfpga_std/cyclonev/soc.c similarity index 100% rename from soc/arm/intel_socfpga_std/cyclonev/soc.c rename to soc/intel/intel_socfpga_std/cyclonev/soc.c diff --git a/soc/arm/intel_socfpga_std/cyclonev/soc.h b/soc/intel/intel_socfpga_std/cyclonev/soc.h similarity index 100% rename from soc/arm/intel_socfpga_std/cyclonev/soc.h rename to soc/intel/intel_socfpga_std/cyclonev/soc.h diff --git a/soc/intel/intel_socfpga_std/soc.yml b/soc/intel/intel_socfpga_std/soc.yml new file mode 100644 index 00000000000..dde15921931 --- /dev/null +++ b/soc/intel/intel_socfpga_std/soc.yml @@ -0,0 +1,6 @@ +family: + - name: intel_socfpga_std + series: + - name: cyclonev + socs: + - name: cyclonev diff --git a/soc/intel/lakemont/CMakeLists.txt b/soc/intel/lakemont/CMakeLists.txt new file mode 100644 index 00000000000..b9f29fef9ca --- /dev/null +++ b/soc/intel/lakemont/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2021-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_cc_option(-march=pentium) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/lakemont/Kconfig b/soc/intel/lakemont/Kconfig new file mode 100644 index 00000000000..42727fddd5a --- /dev/null +++ b/soc/intel/lakemont/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LAKEMONT + select X86 + select CPU_LAKEMONT + select X86_MMU if FPU + select X86_SSE if FPU + select X86_SSE2 if FPU + select X86_SSE3 if FPU + select X86_SSSE3 if FPU + select ARCH_HAS_USERSPACE diff --git a/soc/intel/lakemont/Kconfig.defconfig b/soc/intel/lakemont/Kconfig.defconfig new file mode 100644 index 00000000000..4f5f85f6b3c --- /dev/null +++ b/soc/intel/lakemont/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2021-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_LAKEMONT + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +# Can be enabled once UART is defined in board +# configuration. +config X86_VERY_EARLY_CONSOLE + default n + +# Target platforms are usually not PC-compatible +# (e.g. without BIOS, ACPI, etc.). +config X86_PC_COMPATIBLE + default n + +endif diff --git a/soc/intel/lakemont/Kconfig.soc b/soc/intel/lakemont/Kconfig.soc new file mode 100644 index 00000000000..da45232a653 --- /dev/null +++ b/soc/intel/lakemont/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2021-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LAKEMONT + bool + +config SOC + default "lakemont" if SOC_LAKEMONT diff --git a/soc/x86/atom/linker.ld b/soc/intel/lakemont/linker.ld similarity index 100% rename from soc/x86/atom/linker.ld rename to soc/intel/lakemont/linker.ld diff --git a/soc/x86/lakemont/soc.h b/soc/intel/lakemont/soc.h similarity index 100% rename from soc/x86/lakemont/soc.h rename to soc/intel/lakemont/soc.h diff --git a/soc/intel/lakemont/soc.yml b/soc/intel/lakemont/soc.yml new file mode 100644 index 00000000000..f6a59074592 --- /dev/null +++ b/soc/intel/lakemont/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Lakemont SoC" +socs: +- name: lakemont diff --git a/soc/intel/raptor_lake/CMakeLists.txt b/soc/intel/raptor_lake/CMakeLists.txt new file mode 100644 index 00000000000..b3d7da79222 --- /dev/null +++ b/soc/intel/raptor_lake/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_cc_option(-march=goldmont) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/raptor_lake/Kconfig b/soc/intel/raptor_lake/Kconfig new file mode 100644 index 00000000000..96ead4ae034 --- /dev/null +++ b/soc/intel/raptor_lake/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RAPTOR_LAKE + select X86 + select X86_64 + select CPU_ATOM + select PCIE + select PCIE_MSI + select DYNAMIC_INTERRUPTS + select X86_MMU diff --git a/soc/intel/raptor_lake/Kconfig.defconfig b/soc/intel/raptor_lake/Kconfig.defconfig new file mode 100644 index 00000000000..35761581eec --- /dev/null +++ b/soc/intel/raptor_lake/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Raptor Lake SoC configuration options + +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_RAPTOR_LAKE + +config PCIE_MMIO_CFG + default y + +config X86_DYNAMIC_IRQ_STUBS + default 16 + depends on DYNAMIC_INTERRUPTS + +endif # SOC_RAPTOR_LAKE diff --git a/soc/intel/raptor_lake/Kconfig.soc b/soc/intel/raptor_lake/Kconfig.soc new file mode 100644 index 00000000000..9aa2d7ee5e2 --- /dev/null +++ b/soc/intel/raptor_lake/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RAPTOR_LAKE + bool + +config SOC + default "raptor_lake" if SOC_RAPTOR_LAKE diff --git a/soc/x86/raptor_lake/doc/supported_features.txt b/soc/intel/raptor_lake/doc/supported_features.txt similarity index 100% rename from soc/x86/raptor_lake/doc/supported_features.txt rename to soc/intel/raptor_lake/doc/supported_features.txt diff --git a/soc/x86/raptor_lake/linker.ld b/soc/intel/raptor_lake/linker.ld similarity index 100% rename from soc/x86/raptor_lake/linker.ld rename to soc/intel/raptor_lake/linker.ld diff --git a/soc/x86/raptor_lake/soc.h b/soc/intel/raptor_lake/soc.h similarity index 100% rename from soc/x86/raptor_lake/soc.h rename to soc/intel/raptor_lake/soc.h diff --git a/soc/intel/raptor_lake/soc.yml b/soc/intel/raptor_lake/soc.yml new file mode 100644 index 00000000000..66e1e391143 --- /dev/null +++ b/soc/intel/raptor_lake/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Raptor Lake SoC" +socs: +- name: raptor_lake diff --git a/soc/x86/raptor_lake/soc_gpio.h b/soc/intel/raptor_lake/soc_gpio.h similarity index 100% rename from soc/x86/raptor_lake/soc_gpio.h rename to soc/intel/raptor_lake/soc_gpio.h diff --git a/soc/riscv/ite_ec/CMakeLists.txt b/soc/ite/ec/CMakeLists.txt similarity index 100% rename from soc/riscv/ite_ec/CMakeLists.txt rename to soc/ite/ec/CMakeLists.txt diff --git a/soc/ite/ec/Kconfig b/soc/ite/ec/Kconfig new file mode 100644 index 00000000000..a496a62d69f --- /dev/null +++ b/soc/ite/ec/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ITE_EC + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ITE_EC diff --git a/soc/ite/ec/Kconfig.defconfig b/soc/ite/ec/Kconfig.defconfig new file mode 100644 index 00000000000..646437f9c53 --- /dev/null +++ b/soc/ite/ec/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ITE_EC + +rsource "*/Kconfig.defconfig.series" + +endif # SOC_FAMILY_ITE_EC diff --git a/soc/ite/ec/Kconfig.soc b/soc/ite/ec/Kconfig.soc new file mode 100644 index 00000000000..f75e4de0039 --- /dev/null +++ b/soc/ite/ec/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ITE_EC + bool + +config SOC_FAMILY + default "ite_ec" if SOC_FAMILY_ITE_EC + +rsource "*/Kconfig.soc" diff --git a/soc/riscv/ite_ec/common/CMakeLists.txt b/soc/ite/ec/common/CMakeLists.txt similarity index 100% rename from soc/riscv/ite_ec/common/CMakeLists.txt rename to soc/ite/ec/common/CMakeLists.txt diff --git a/soc/riscv/ite_ec/common/check_regs.c b/soc/ite/ec/common/check_regs.c similarity index 100% rename from soc/riscv/ite_ec/common/check_regs.c rename to soc/ite/ec/common/check_regs.c diff --git a/soc/riscv/ite_ec/common/chip_chipregs.h b/soc/ite/ec/common/chip_chipregs.h similarity index 100% rename from soc/riscv/ite_ec/common/chip_chipregs.h rename to soc/ite/ec/common/chip_chipregs.h diff --git a/soc/riscv/ite_ec/common/pinctrl_soc.h b/soc/ite/ec/common/pinctrl_soc.h similarity index 100% rename from soc/riscv/ite_ec/common/pinctrl_soc.h rename to soc/ite/ec/common/pinctrl_soc.h diff --git a/soc/riscv/ite_ec/common/policy.c b/soc/ite/ec/common/policy.c similarity index 100% rename from soc/riscv/ite_ec/common/policy.c rename to soc/ite/ec/common/policy.c diff --git a/soc/riscv/ite_ec/common/power.c b/soc/ite/ec/common/power.c similarity index 100% rename from soc/riscv/ite_ec/common/power.c rename to soc/ite/ec/common/power.c diff --git a/soc/riscv/ite_ec/common/soc_common.h b/soc/ite/ec/common/soc_common.h similarity index 100% rename from soc/riscv/ite_ec/common/soc_common.h rename to soc/ite/ec/common/soc_common.h diff --git a/soc/riscv/ite_ec/common/soc_common_irq.c b/soc/ite/ec/common/soc_common_irq.c similarity index 100% rename from soc/riscv/ite_ec/common/soc_common_irq.c rename to soc/ite/ec/common/soc_common_irq.c diff --git a/soc/riscv/ite_ec/common/soc_dt.h b/soc/ite/ec/common/soc_dt.h similarity index 100% rename from soc/riscv/ite_ec/common/soc_dt.h rename to soc/ite/ec/common/soc_dt.h diff --git a/soc/riscv/ite_ec/common/soc_espi.h b/soc/ite/ec/common/soc_espi.h similarity index 100% rename from soc/riscv/ite_ec/common/soc_espi.h rename to soc/ite/ec/common/soc_espi.h diff --git a/soc/riscv/ite_ec/common/soc_irq.S b/soc/ite/ec/common/soc_irq.S similarity index 100% rename from soc/riscv/ite_ec/common/soc_irq.S rename to soc/ite/ec/common/soc_irq.S diff --git a/soc/riscv/ite_ec/common/vector.S b/soc/ite/ec/common/vector.S similarity index 100% rename from soc/riscv/ite_ec/common/vector.S rename to soc/ite/ec/common/vector.S diff --git a/soc/ite/ec/it8xxx2/CMakeLists.txt b/soc/ite/ec/it8xxx2/CMakeLists.txt new file mode 100644 index 00000000000..425642c1727 --- /dev/null +++ b/soc/ite/ec/it8xxx2/CMakeLists.txt @@ -0,0 +1,9 @@ +zephyr_sources(soc.c) +zephyr_include_directories(.) + +zephyr_library_sources_ifndef(CONFIG_RISCV_ISA_EXT_M __arithmetic.S) +zephyr_sources_ifdef(CONFIG_SOC_IT8XXX2_USE_ILM ilm.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld + CACHE INTERNAL "SoC Linker script ${SOC_NAME}" +) diff --git a/soc/ite/ec/it8xxx2/Kconfig b/soc/ite/ec/it8xxx2/Kconfig new file mode 100644 index 00000000000..0c65a11c27a --- /dev/null +++ b/soc/ite/ec/it8xxx2/Kconfig @@ -0,0 +1,154 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ITE_IT8XXX2 + select CPU_HAS_FPU if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M + select HAS_PM + +if SOC_SERIES_ITE_IT8XXX2 + +config SOC_IT8XXX2 + select RISCV + select ATOMIC_OPERATIONS_BUILTIN + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + # Workaround mul instruction bug, see: + # https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf + select RISCV_ISA_EXT_M if !(SOC_IT81302_BX || SOC_IT81202_BX) + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + +config SOC_IT8XXX2_REG_SET_V1 + bool + help + This option is selected by a variable of which soc, and will + determine the register for the IT81xx2 specification. + +config SOC_IT8XXX2_REG_SET_V2 + bool + help + This option is selected by a variable of which soc, and will + determine the register for the IT82xx2 specification. + +config SOC_IT81302_BX + select SOC_IT8XXX2_REG_SET_V1 + +config SOC_IT81202_BX + select SOC_IT8XXX2_REG_SET_V1 + +config SOC_IT81302_CX + select SOC_IT8XXX2_REG_SET_V1 + +config SOC_IT81202_CX + select SOC_IT8XXX2_REG_SET_V1 + +config SOC_IT82202_AX + select SOC_IT8XXX2_REG_SET_V2 + select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED + +config SOC_IT82302_AX + select SOC_IT8XXX2_REG_SET_V2 + select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED + +config SOC_IT82002_AW + select SOC_IT8XXX2_REG_SET_V2 + select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED + +config SOC_IT8XXX2_PLL_FLASH_48M + bool "Flash frequency is 48MHz" + default y + select FLASH + help + Change frequency of PLL, CPU, and flash to 48MHz during initialization. + + Set n to use the default settings. + (PLL and CPU run at 48MHz, flash frequency is 16MHz) + +config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN + bool "The pins of GPIO group K and L aren't bonding with pad" + default y + help + On IT81202 (128-pins package), the pins of GPIO group K and L aren't + bonding with pad. So we configure these pins as internal pull-down + at default to prevent leakage current due to floating. + +config SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW + bool "The GPIOH7 isn't bonding with pad and is left floating internally" + default y + help + On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left + floating internally. We need to enable internal pull-down for the pin + to prevent leakage current, but IT81202/IT81302 doesn't have the + capability to pull it down. We can only set it as output low, + so we enable output low for it at initialization to prevent leakage. + +config SOC_IT8XXX2_CPU_IDLE_GATING + bool + help + This option determines whether the entering CPU idle mode can be + gated by individual drivers. When this option is disabled, CPU idle + mode is always permitted. + +config SOC_IT8XXX2_EC_BUS_24MHZ + bool "EC bus is 24MHz" + help + Raise EC bus to 24MHz (default is 8MHz). + This reduces read/write EC registers latency by 50%. + NOTE: There is limitation to enabling this config on it81xx2 series. + The clock_frequency of ite,it8xxx2-i2c node (i2c0, i2c1, and i2c2) will + be fixed at 400KHz. + +choice + prompt "Clock source for PLL reference clock" + +config SOC_IT8XXX2_INT_32K + bool "Use the +/-2.3% internal clock generator" + +config SOC_IT8XXX2_EXT_32K + bool "Use external 32.768 kHz clock source" + +endchoice + +config SOC_IT8XXX2_USE_ILM + bool + default y + help + If enabled, Instruction Local Memory (ILM) will be configured to execute + code placed in the .__ram_code section out of RAM. This consumes RAM in + blocks of 4 kilobytes, but performance of code in ILM is much more + predictable than executing from Flash directly, and some code (such as code + that writes to the internal Flash) must execute out of RAM. + +config SOC_IT8XXX2_EXCEPTIONS_IN_RAM + bool "Place exception handling code in RAM" + default y + select SOC_IT8XXX2_USE_ILM + help + Place exception handling (ISR entry/exit and related) code in ILM, which + has more reliable performance characteristics than executing directly from + Flash. This can significantly improve performance when under I-cache + pressure. + +config SOC_IT8XXX2_SHA256_HW_ACCELERATE + bool "HW SHA256 calculation" + help + IT8XXX2 HW support sha256 calculation, and its calculation is faster than FW. + We place SHA256 message, hash and key data (total 512bytes) in RAM. + If we enable this config, because HW limits, the sha256 data must place in + first 4KB of RAM. + +DT_CHOSEN_ZEPHYR_FLASH := zephyr,flash + +config SOC_IT8XXX2_FLASH_SIZE_BYTES + hex + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_ZEPHYR_FLASH)) + help + Total size of writable flash. + +config ILM_MAX_SIZE + int "ILM Size in kB" + default 60 if SOC_IT81202_CX || SOC_IT81302_CX + default SRAM_SIZE + +endif # SOC_SERIES_ITE_IT8XXX2 diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202bx b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202bx similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202bx rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202bx index 78a33afc9d5..a643011e6b4 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202bx +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202bx @@ -3,9 +3,6 @@ if SOC_IT81202_BX -config SOC - default "it81202bx" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default y diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202cx b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202cx similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202cx rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202cx index c7d8d590653..e9b5d1d5eb6 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202cx +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202cx @@ -3,9 +3,6 @@ if SOC_IT81202_CX -config SOC - default "it81202cx" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default y diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302bx b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302bx similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302bx rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302bx index 00429d7f124..051d40f1e4b 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302bx +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302bx @@ -3,9 +3,6 @@ if SOC_IT81302_BX -config SOC - default "it81302bx" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default n diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302cx b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302cx similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302cx rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302cx index 0adc5809b72..06fb93d78df 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302cx +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302cx @@ -3,9 +3,6 @@ if SOC_IT81302_CX -config SOC - default "it81302cx" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default n diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82002aw b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82002aw similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82002aw rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it82002aw index 1edba5f674e..30e2db747b3 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82002aw +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82002aw @@ -3,9 +3,6 @@ if SOC_IT82002_AW -config SOC - default "it82002aw" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default y diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82202ax b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82202ax similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82202ax rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it82202ax index 8195c2b57fb..99343db0b37 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82202ax +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82202ax @@ -3,9 +3,6 @@ if SOC_IT82202_AX -config SOC - default "it82202ax" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default y diff --git a/soc/ite/ec/it8xxx2/Kconfig.defconfig.series b/soc/ite/ec/it8xxx2/Kconfig.defconfig.series new file mode 100644 index 00000000000..98fbee6c0c1 --- /dev/null +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.series @@ -0,0 +1,56 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ITE_IT8XXX2 + +config RISCV_GP + default y + +config ARCH_HAS_CUSTOM_BUSY_WAIT + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 4096 + +config UART_NS16550_WA_ISR_REENABLE_INTERRUPT + default y + depends on UART_NS16550 + +config FLASH_INIT_PRIORITY + default 0 + +config IT8XXX2_PLL_SEQUENCE_PRIORITY + int + default 1 + depends on SOC_IT8XXX2_PLL_FLASH_48M + +config VCMP_IT8XXX2_INIT_PRIORITY + default 91 if VCMP_IT8XXX2_WORKQUEUE + +config PINCTRL + default y + +config NUM_IRQS + default 185 + +config DYNAMIC_INTERRUPTS + default y + +config GEN_ISR_TABLES + default y + +config GEN_IRQ_START_VECTOR + default 0 + +config GEN_SW_ISR_TABLE + default y + +config RISCV_SOC_INTERRUPT_INIT + default y + +rsource "Kconfig.defconfig.it8*" + +endif # SOC_SERIES_ITE_IT8XXX2 diff --git a/soc/ite/ec/it8xxx2/Kconfig.soc b/soc/ite/ec/it8xxx2/Kconfig.soc new file mode 100644 index 00000000000..aba69c55346 --- /dev/null +++ b/soc/ite/ec/it8xxx2/Kconfig.soc @@ -0,0 +1,52 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ITE_IT8XXX2 + bool + select SOC_FAMILY_ITE_EC + help + Enable support for ITE IT8XXX2 + +config SOC_IT8XXX2 + bool + select SOC_SERIES_ITE_IT8XXX2 + +config SOC_IT81302_BX + bool + select SOC_IT8XXX2 + +config SOC_IT81202_BX + bool + select SOC_IT8XXX2 + +config SOC_IT81302_CX + bool + select SOC_IT8XXX2 + +config SOC_IT81202_CX + bool + select SOC_IT8XXX2 + +config SOC_IT82202_AX + bool + select SOC_IT8XXX2 + +config SOC_IT82302_AX + bool + select SOC_IT8XXX2 + +config SOC_IT82002_AW + bool + select SOC_IT8XXX2 + +config SOC_SERIES + default "it8xxx2" if SOC_SERIES_ITE_IT8XXX2 + +config SOC + default "it81202bx" if SOC_IT81202_BX + default "it81202cx" if SOC_IT81202_CX + default "it81302bx" if SOC_IT81302_BX + default "it81302cx" if SOC_IT81302_CX + default "it82002aw" if SOC_IT82002_AW + default "it82202ax" if SOC_IT82202_AX + default "it82302ax" if SOC_IT82302_AX diff --git a/soc/riscv/ite_ec/it8xxx2/__arithmetic.S b/soc/ite/ec/it8xxx2/__arithmetic.S similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/__arithmetic.S rename to soc/ite/ec/it8xxx2/__arithmetic.S diff --git a/soc/riscv/ite_ec/it8xxx2/ilm.c b/soc/ite/ec/it8xxx2/ilm.c similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/ilm.c rename to soc/ite/ec/it8xxx2/ilm.c diff --git a/soc/riscv/ite_ec/it8xxx2/ilm.h b/soc/ite/ec/it8xxx2/ilm.h similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/ilm.h rename to soc/ite/ec/it8xxx2/ilm.h diff --git a/soc/riscv/ite_ec/it8xxx2/linker.ld b/soc/ite/ec/it8xxx2/linker.ld similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/linker.ld rename to soc/ite/ec/it8xxx2/linker.ld diff --git a/soc/riscv/ite_ec/it8xxx2/soc.c b/soc/ite/ec/it8xxx2/soc.c similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/soc.c rename to soc/ite/ec/it8xxx2/soc.c diff --git a/soc/riscv/ite_ec/it8xxx2/soc.h b/soc/ite/ec/it8xxx2/soc.h similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/soc.h rename to soc/ite/ec/it8xxx2/soc.h diff --git a/soc/ite/ec/soc.yml b/soc/ite/ec/soc.yml new file mode 100644 index 00000000000..c2ffdd222db --- /dev/null +++ b/soc/ite/ec/soc.yml @@ -0,0 +1,12 @@ +family: + - name: ite_ec + series: + - name: it8xxxx + socs: + - name: it81202bx + - name: it81202cx + - name: it81302bx + - name: it81302cx + - name: it82002aw + - name: it82202ax + - name: it82302ax diff --git a/soc/litex/litex_vexriscv/CMakeLists.txt b/soc/litex/litex_vexriscv/CMakeLists.txt new file mode 100644 index 00000000000..3272d0359a1 --- /dev/null +++ b/soc/litex/litex_vexriscv/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (c) 2018 - 2019 Antmicro +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + ${ZEPHYR_BASE}/soc/common/riscv-privileged/soc_irq.S + ${ZEPHYR_BASE}/soc/common/riscv-privileged/vector.S +) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/litex/litex_vexriscv/Kconfig b/soc/litex/litex_vexriscv/Kconfig new file mode 100644 index 00000000000..b13181f0177 --- /dev/null +++ b/soc/litex/litex_vexriscv/Kconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2018 - 2019 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LITEX_VEXRISCV + select RISCV + select ATOMIC_OPERATIONS_C + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + +if SOC_LITEX_VEXRISCV + +config LITEX_CSR_DATA_WIDTH + int "Select Control/Status register width" + default 32 + +endif # SOC_LITEX_VEXRISCV diff --git a/soc/litex/litex_vexriscv/Kconfig.defconfig b/soc/litex/litex_vexriscv/Kconfig.defconfig new file mode 100644 index 00000000000..d2bb5c9ae73 --- /dev/null +++ b/soc/litex/litex_vexriscv/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2018 - 2019 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_LITEX_VEXRISCV + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 + +config NUM_IRQS + default 12 + +endif # SOC_LITEX_VEXRISCV diff --git a/soc/litex/litex_vexriscv/Kconfig.soc b/soc/litex/litex_vexriscv/Kconfig.soc new file mode 100644 index 00000000000..4c0c80717b4 --- /dev/null +++ b/soc/litex/litex_vexriscv/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2018 - 2019 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LITEX_VEXRISCV + bool + help + LiteX VexRiscv system implementation + +config SOC + default "litex_vexriscv" if SOC_LITEX_VEXRISCV diff --git a/soc/riscv/litex_vexriscv/soc.h b/soc/litex/litex_vexriscv/soc.h similarity index 100% rename from soc/riscv/litex_vexriscv/soc.h rename to soc/litex/litex_vexriscv/soc.h diff --git a/soc/litex/litex_vexriscv/soc.yml b/soc/litex/litex_vexriscv/soc.yml new file mode 100644 index 00000000000..322f95a9e8d --- /dev/null +++ b/soc/litex/litex_vexriscv/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: litex_vexriscv diff --git a/soc/riscv/opentitan/CMakeLists.txt b/soc/lowrisc/opentitan/CMakeLists.txt similarity index 100% rename from soc/riscv/opentitan/CMakeLists.txt rename to soc/lowrisc/opentitan/CMakeLists.txt diff --git a/soc/lowrisc/opentitan/Kconfig b/soc/lowrisc/opentitan/Kconfig new file mode 100644 index 00000000000..25670a967c6 --- /dev/null +++ b/soc/lowrisc/opentitan/Kconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2023 Rivos Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_OPENTITAN + select ATOMIC_OPERATIONS_C + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_ISA_EXT_ZBA + select RISCV_ISA_EXT_ZBB + select RISCV_ISA_EXT_ZBC + select RISCV_ISA_EXT_ZBS + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + # OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode. + select RISCV_VECTORED_MODE + select GEN_IRQ_VECTOR_TABLE diff --git a/soc/lowrisc/opentitan/Kconfig.defconfig b/soc/lowrisc/opentitan/Kconfig.defconfig new file mode 100644 index 00000000000..b77a9405fbe --- /dev/null +++ b/soc/lowrisc/opentitan/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Rivos Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_OPENTITAN + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 32 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config NUM_IRQS + default 256 + +endif # SOC_OPENTITAN diff --git a/soc/lowrisc/opentitan/Kconfig.soc b/soc/lowrisc/opentitan/Kconfig.soc new file mode 100644 index 00000000000..bf5ff0780e9 --- /dev/null +++ b/soc/lowrisc/opentitan/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2023 Rivos Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_OPENTITAN + bool + +config SOC + default "opentitan" if SOC_OPENTITAN diff --git a/soc/riscv/opentitan/rom_header.S b/soc/lowrisc/opentitan/rom_header.S similarity index 100% rename from soc/riscv/opentitan/rom_header.S rename to soc/lowrisc/opentitan/rom_header.S diff --git a/soc/riscv/opentitan/rom_header.ld b/soc/lowrisc/opentitan/rom_header.ld similarity index 100% rename from soc/riscv/opentitan/rom_header.ld rename to soc/lowrisc/opentitan/rom_header.ld diff --git a/soc/riscv/opentitan/soc.c b/soc/lowrisc/opentitan/soc.c similarity index 100% rename from soc/riscv/opentitan/soc.c rename to soc/lowrisc/opentitan/soc.c diff --git a/soc/lowrisc/opentitan/soc.yml b/soc/lowrisc/opentitan/soc.yml new file mode 100644 index 00000000000..51ebb26a55c --- /dev/null +++ b/soc/lowrisc/opentitan/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: opentitan diff --git a/soc/arm/microchip_mec/CMakeLists.txt b/soc/microchip/mec/CMakeLists.txt similarity index 100% rename from soc/arm/microchip_mec/CMakeLists.txt rename to soc/microchip/mec/CMakeLists.txt diff --git a/soc/microchip/mec/Kconfig b/soc/microchip/mec/Kconfig new file mode 100644 index 00000000000..1b5ccda45e0 --- /dev/null +++ b/soc/microchip/mec/Kconfig @@ -0,0 +1,226 @@ +# Microchip MEC MCU line + +# Copyright (c) 2018, Intel Corporation +# Copyright (c) 2022, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_MEC + +menuconfig MCHP_MEC_UNSIGNED_HEADER + bool "Create an unsigned output binary with MCHP MEC binary header" + help + On Microchip MEC series chip, the ROM code loads firmware image from flash + to RAM using a TAG to locate a Header which specifies the location and + size of the firmware image. Enable this to invoke the mec_spi_gen tool + which generates an SPI image with TAG, Header, and firmware binary. This + tool does not produce a signed image which can be authenticated by the + Boot-ROM. Use the full Microchip SPI image generator program for + authentication and all other Boot-ROM loader features. Refer to the MCHP + EVB boards for an example. + +if MCHP_MEC_UNSIGNED_HEADER + +config MCHP_MEC_HEADER_CHIP + string + default "mec15xx" if SOC_SERIES_MEC15XX + default "mec172x" if SOC_SERIES_MEC172X + +choice MCHP_MEC_HEADER_SPI_FREQ_MHZ_CHOICE + prompt "Clock rate to use for SPI flash" + default MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 + help + This selects the SPI clock frequency that will be used for loading + firmware binary from flash to RAM. + +config MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 + bool "SPI flash clock rate of 12 MHz" + +config MCHP_MEC_HEADER_SPI_FREQ_MHZ_16 + bool "SPI flash clock rate of 16 MHz" + +config MCHP_MEC_HEADER_SPI_FREQ_MHZ_24 + bool "SPI flash clock rate of 24 MHz" + +config MCHP_MEC_HEADER_SPI_FREQ_MHZ_48 + bool "SPI flash clock rate of 48 MHz" + +endchoice + +config MCHP_MEC_HEADER_SPI_FREQ_MHZ + int + default 12 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 + default 25 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_16 + default 24 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_24 + default 48 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_48 + +choice MCHP_MEC_HEADER_SPI_READ_MODE_CHOICE + prompt "Reading mode used by the SPI flash" + default MCHP_MEC_HEADER_SPI_READ_MODE_FAST + help + This sets the reading mode that can be used by the SPI flash. + Reading modes supported are normal, fast, dual, and quad. + +config MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL + bool "SPI flash operates full-duplex with frequency (< 25 MHz)" + +config MCHP_MEC_HEADER_SPI_READ_MODE_FAST + bool "SPI flash operates full-duplex with fast reading mode" + +config MCHP_MEC_HEADER_SPI_READ_MODE_DUAL + bool "SPI flash operates with dual data reading mode" + +config MCHP_MEC_HEADER_SPI_READ_MODE_QUAD + bool "SPI flash operates with quad data reading mode" + +endchoice + +config MCHP_MEC_HEADER_SPI_READ_MODE + string + default "slow" if MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL + default "fast" if MCHP_MEC_HEADER_SPI_READ_MODE_FAST + default "dual" if MCHP_MEC_HEADER_SPI_READ_MODE_DUAL + default "quad" if MCHP_MEC_HEADER_SPI_READ_MODE_QUAD + +choice MCHP_MEC_HEADER_FLASH_SIZE_CHOICE + prompt "Flash size" + default MCHP_MEC_HEADER_FLASH_SIZE_16M + help + This sets the SPI flash size. + +config MCHP_MEC_HEADER_FLASH_SIZE_256K + bool "SPI flash size 256K Bytes" + help + The SPI flash size is 256K Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_512K + bool "SPI flash size 512K Bytes" + help + The SPI flash size is 512K Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_1M + bool "SPI flash size 1M Bytes" + help + The SPI flash size is 1M Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_2M + bool "SPI flash size 2M Bytes" + help + The SPI flash size is 2M Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_4M + bool "SPI flash size 4M Bytes" + help + The SPI flash size is 4M Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_8M + bool "SPI flash size 8M Bytes" + help + The SPI flash size is 8M Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_16M + bool "SPI flash size 16M Bytes" + help + The SPI flash size is 16M Bytes. + +endchoice + +config MCHP_MEC_HEADER_FLASH_SIZE + int + default 256 if MCHP_MEC_HEADER_FLASH_SIZE_256K + default 512 if MCHP_MEC_HEADER_FLASH_SIZE_512K + default 1024 if MCHP_MEC_HEADER_FLASH_SIZE_1M + default 2048 if MCHP_MEC_HEADER_FLASH_SIZE_2M + default 4096 if MCHP_MEC_HEADER_FLASH_SIZE_4M + default 8192 if MCHP_MEC_HEADER_FLASH_SIZE_8M + default 16384 if MCHP_MEC_HEADER_FLASH_SIZE_16M + +choice MCHP_MEC_HEADER_SPI_DRVSTR_CHOICE + prompt "Flash drive strength" + default MCHP_MEC_HEADER_SPI_DRVSTR_1X + help + This sets the SPI flash size. + +config MCHP_MEC_HEADER_SPI_DRVSTR_1X + bool "SPI flash drive strength multiplier 1" + help + The SPI flash size is 256K Bytes. + +config MCHP_MEC_HEADER_SPI_DRVSTR_2X + bool "SPI flash drive strength multiplier 2" + help + The SPI flash size is 256K Bytes. + +config MCHP_MEC_HEADER_SPI_DRVSTR_4X + bool "SPI flash drive strength multiplier 4" + help + The SPI flash size is 512K Bytes. + +config MCHP_MEC_HEADER_SPI_DRVSTR_6X + bool "SPI flash drive strength multiplier 6" + help + The SPI flash size is 1M Bytes. + +endchoice + +config MCHP_MEC_HEADER_SPI_DRVSTR + string + default "1x" if MCHP_MEC_HEADER_SPI_DRVSTR_1X + default "2x" if MCHP_MEC_HEADER_SPI_DRVSTR_2X + default "4x" if MCHP_MEC_HEADER_SPI_DRVSTR_4X + default "6x" if MCHP_MEC_HEADER_SPI_DRVSTR_6X + +choice MCHP_MEC_HEADER_SPI_SLEW_RATE_CHOICE + prompt "Slew rate of SPI pins" + default MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW + help + This sets the slew rate of the SPI pins. Default is slow + slew rate which is 1/2 the AHB clock rate. Fast slew is the + AHB clock rate. + +config MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW + bool "SPI pins slew rate is 1/2 AHB frequency" + +config MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST + bool "SPI pins slew rate is 1x AHB frequency" + +endchoice + +config MCHP_MEC_HEADER_SPI_SLEW_RATE + string + default "slow" if MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW + default "fast" if MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST + +config MCHP_MEC_HEADER_FLASH_SPI_MODE + int "Flash SPI Mode" + range 0 7 + default 0 + help + This three bit value corresponds to the QMSPI controllers clock idle and + input/output data phases. Bits[0:2] are CPOL:CPHA_MOSI:CPHA_MISO. Refer + to the data sheet. Default value is 0 corresponding to SPI Mode 0 + signalling. + Setting this field to 0 selects mode 0, CPOL=0, CPHA_MOSI=0, CPHA_MISO=0 + Setting this filed to 7 selects mode 3, CPOL=1, CPHA_MOSI=1, CPHA_MISO=1 + +config MCHP_HEADER_VERBOSE_OUTPUT + bool "Debug console output" + default n + help + Enable print output from SPI generator script for debug + +endif # MCHP_MEC_UNSIGNED_HEADER + +config SOC_MEC_PROC_CLK_DIV + int "PROC_CLK_DIV" + default 1 + range 1 48 + help + This divisor defines a ratio between processor clock (HCLK) + and main 96 MHz clock (MCK): + HCLK = MCK / PROC_CLK_DIV + Allowed divider values: 1, 3, 4, 16, and 48. + +# Select SoC Part No. and configuration options +rsource "*/Kconfig" + +endif # SOC_FAMILY_MICROCHIP_MEC diff --git a/soc/microchip/mec/Kconfig.defconfig b/soc/microchip/mec/Kconfig.defconfig new file mode 100644 index 00000000000..26163d390c9 --- /dev/null +++ b/soc/microchip/mec/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_MEC + +rsource "*/Kconfig.defconfig.series" + +endif # SOC_FAMILY_MICROCHIP_MEC diff --git a/soc/microchip/mec/Kconfig.soc b/soc/microchip/mec/Kconfig.soc new file mode 100644 index 00000000000..5d1cb955c52 --- /dev/null +++ b/soc/microchip/mec/Kconfig.soc @@ -0,0 +1,12 @@ +# Microchip MEC172x, MEC1501 MCU line + +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_MICROCHIP_MEC + bool + +config SOC_FAMILY + default "microchip_mec" if SOC_FAMILY_MICROCHIP_MEC + +rsource "*/Kconfig.soc" diff --git a/soc/microchip/mec/common/CMakeLists.txt b/soc/microchip/mec/common/CMakeLists.txt new file mode 100644 index 00000000000..0fe0c9f3d8b --- /dev/null +++ b/soc/microchip/mec/common/CMakeLists.txt @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_MEC172X + soc_i2c.c +) + +if (DEFINED CONFIG_MCHP_HEADER_VERBOSE_OUTPUT) + set(MCHP_HEADER_VERBOSE_OPTION "-v") +endif() + +if (DEFINED CONFIG_MCHP_MEC_UNSIGNED_HEADER) + set(MCHP_MEC_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.mchp.bin) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/soc/microchip/mec/common/spigen/mec_spi_gen.py + -i ${KERNEL_BIN_NAME} + -o ${MCHP_MEC_BIN_NAME} + -c ${CONFIG_MCHP_MEC_HEADER_CHIP} + -s ${CONFIG_MCHP_MEC_HEADER_FLASH_SIZE} + -f ${CONFIG_MCHP_MEC_HEADER_SPI_FREQ_MHZ} + -r ${CONFIG_MCHP_MEC_HEADER_SPI_READ_MODE} + -m ${CONFIG_MCHP_MEC_HEADER_FLASH_SPI_MODE} + --drvstr ${CONFIG_MCHP_MEC_HEADER_SPI_DRVSTR} + --slewrate ${CONFIG_MCHP_MEC_HEADER_SPI_SLEW_RATE} + ${MCHP_HEADER_VERBOSE_OPTION} + ) +endif() diff --git a/soc/arm/microchip_mec/common/pinctrl_soc.h b/soc/microchip/mec/common/pinctrl_soc.h similarity index 100% rename from soc/arm/microchip_mec/common/pinctrl_soc.h rename to soc/microchip/mec/common/pinctrl_soc.h diff --git a/soc/arm/microchip_mec/common/reg/mec_acpi_ec.h b/soc/microchip/mec/common/reg/mec_acpi_ec.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_acpi_ec.h rename to soc/microchip/mec/common/reg/mec_acpi_ec.h diff --git a/soc/arm/microchip_mec/common/reg/mec_adc.h b/soc/microchip/mec/common/reg/mec_adc.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_adc.h rename to soc/microchip/mec/common/reg/mec_adc.h diff --git a/soc/arm/microchip_mec/common/reg/mec_global_cfg.h b/soc/microchip/mec/common/reg/mec_global_cfg.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_global_cfg.h rename to soc/microchip/mec/common/reg/mec_global_cfg.h diff --git a/soc/arm/microchip_mec/common/reg/mec_gpio.h b/soc/microchip/mec/common/reg/mec_gpio.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_gpio.h rename to soc/microchip/mec/common/reg/mec_gpio.h diff --git a/soc/arm/microchip_mec/common/reg/mec_kbc.h b/soc/microchip/mec/common/reg/mec_kbc.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_kbc.h rename to soc/microchip/mec/common/reg/mec_kbc.h diff --git a/soc/arm/microchip_mec/common/reg/mec_keyscan.h b/soc/microchip/mec/common/reg/mec_keyscan.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_keyscan.h rename to soc/microchip/mec/common/reg/mec_keyscan.h diff --git a/soc/arm/microchip_mec/common/reg/mec_peci.h b/soc/microchip/mec/common/reg/mec_peci.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_peci.h rename to soc/microchip/mec/common/reg/mec_peci.h diff --git a/soc/arm/microchip_mec/common/reg/mec_ps2.h b/soc/microchip/mec/common/reg/mec_ps2.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_ps2.h rename to soc/microchip/mec/common/reg/mec_ps2.h diff --git a/soc/arm/microchip_mec/common/reg/mec_pwm.h b/soc/microchip/mec/common/reg/mec_pwm.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_pwm.h rename to soc/microchip/mec/common/reg/mec_pwm.h diff --git a/soc/arm/microchip_mec/common/reg/mec_tach.h b/soc/microchip/mec/common/reg/mec_tach.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_tach.h rename to soc/microchip/mec/common/reg/mec_tach.h diff --git a/soc/arm/microchip_mec/common/reg/mec_tfdp.h b/soc/microchip/mec/common/reg/mec_tfdp.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_tfdp.h rename to soc/microchip/mec/common/reg/mec_tfdp.h diff --git a/soc/arm/microchip_mec/common/reg/mec_timers.h b/soc/microchip/mec/common/reg/mec_timers.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_timers.h rename to soc/microchip/mec/common/reg/mec_timers.h diff --git a/soc/arm/microchip_mec/common/reg/mec_uart.h b/soc/microchip/mec/common/reg/mec_uart.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_uart.h rename to soc/microchip/mec/common/reg/mec_uart.h diff --git a/soc/arm/microchip_mec/common/reg/mec_vci.h b/soc/microchip/mec/common/reg/mec_vci.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_vci.h rename to soc/microchip/mec/common/reg/mec_vci.h diff --git a/soc/arm/microchip_mec/common/reg/mec_wdt.h b/soc/microchip/mec/common/reg/mec_wdt.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_wdt.h rename to soc/microchip/mec/common/reg/mec_wdt.h diff --git a/soc/arm/microchip_mec/common/soc_dt.h b/soc/microchip/mec/common/soc_dt.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_dt.h rename to soc/microchip/mec/common/soc_dt.h diff --git a/soc/arm/microchip_mec/common/soc_espi_channels.h b/soc/microchip/mec/common/soc_espi_channels.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_espi_channels.h rename to soc/microchip/mec/common/soc_espi_channels.h diff --git a/soc/arm/microchip_mec/common/soc_gpio.h b/soc/microchip/mec/common/soc_gpio.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_gpio.h rename to soc/microchip/mec/common/soc_gpio.h diff --git a/soc/arm/microchip_mec/common/soc_i2c.c b/soc/microchip/mec/common/soc_i2c.c similarity index 99% rename from soc/arm/microchip_mec/common/soc_i2c.c rename to soc/microchip/mec/common/soc_i2c.c index 0e33437af98..162a06695b4 100644 --- a/soc/arm/microchip_mec/common/soc_i2c.c +++ b/soc/microchip/mec/common/soc_i2c.c @@ -32,7 +32,7 @@ struct mec_i2c_port { * TODO: MEC15xx and MEC172x handle ports with alternate pins. */ static const struct mec_i2c_port mec_i2c_ports[] = { -#if defined(CONFIG_SOC_SERIES_MEC172X) || defined(CONFIG_SOC_SERIES_MEC1501X) +#if defined(CONFIG_SOC_SERIES_MEC172X) || defined(CONFIG_SOC_SERIES_MEC15XX) { 0004, 1, 0003, 1 }, { 0131, 1, 0130, 1 }, /* VTR2. ALT on eSPI VTR3 {0073, 2, 0072, 2} */ { 0155, 1, 0154, 1 }, diff --git a/soc/arm/microchip_mec/common/soc_i2c.h b/soc/microchip/mec/common/soc_i2c.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_i2c.h rename to soc/microchip/mec/common/soc_i2c.h diff --git a/soc/arm/microchip_mec/common/soc_pcr.h b/soc/microchip/mec/common/soc_pcr.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_pcr.h rename to soc/microchip/mec/common/soc_pcr.h diff --git a/soc/arm/microchip_mec/common/soc_pins.h b/soc/microchip/mec/common/soc_pins.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_pins.h rename to soc/microchip/mec/common/soc_pins.h diff --git a/soc/arm/microchip_mec/common/spigen/mec_spi_gen.py b/soc/microchip/mec/common/spigen/mec_spi_gen.py similarity index 99% rename from soc/arm/microchip_mec/common/spigen/mec_spi_gen.py rename to soc/microchip/mec/common/spigen/mec_spi_gen.py index 41721d4bf31..b45a51cf55b 100755 --- a/soc/arm/microchip_mec/common/spigen/mec_spi_gen.py +++ b/soc/microchip/mec/common/spigen/mec_spi_gen.py @@ -68,7 +68,7 @@ 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d] CHIP_DICT = { - 'mec152x': { 'sram_base': 0xe0000, 'sram_size': 0x40000, 'header_ver': 2 }, + 'mec15xx': { 'sram_base': 0xe0000, 'sram_size': 0x40000, 'header_ver': 2 }, 'mec172x': { 'sram_base': 0xc0000, 'sram_size': 0x68000, 'header_ver': 3 }, } @@ -123,7 +123,7 @@ def build_header(chip, spi_config, hdr_spi_loc, pld_spi_loc, pld_entry_addr, pld """Build MEC152x/MEC172x Boot-ROM SPI image header Args: - chip: mec152x or mec172x + chip: mec15xx or mec172x spi_config: spi configuration hdr_spi_loc: Header location in SPI Image pld_spi_loc: Payload(FW binary) location in SPI Image @@ -242,9 +242,9 @@ def parse_args(): parser.add_argument("-c", type=str, dest="chip", - choices = ["mec152x", "mec172x"], + choices = ["mec15xx", "mec172x"], default="mec172x", - help="Chip name: mec172x(default) or mec152x") + help="Chip name: mec172x(default) or mec15xx") parser.add_argument("-i", type=str, dest="infilename", diff --git a/soc/microchip/mec/mec15xx/CMakeLists.txt b/soc/microchip/mec/mec15xx/CMakeLists.txt new file mode 100644 index 00000000000..8649cbb15fb --- /dev/null +++ b/soc/microchip/mec/mec15xx/CMakeLists.txt @@ -0,0 +1,24 @@ +# +# Copyright (c) 2019, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) +zephyr_include_directories(.) + +zephyr_sources_ifdef(CONFIG_PM + device_power.c + power.c + ) + +if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) + if(CONFIG_TIMING_FUNCTIONS) + # Use MEC15xx timing calculations only if DWT is not present + if(NOT CONFIG_CORTEX_M_DWT) + zephyr_library_sources(timing.c) + endif() + endif() +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/microchip/mec/mec15xx/Kconfig b/soc/microchip/mec/mec15xx/Kconfig new file mode 100644 index 00000000000..d00e938a6d1 --- /dev/null +++ b/soc/microchip/mec/mec15xx/Kconfig @@ -0,0 +1,101 @@ +# Microchip MEC1501 MCU core series + +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MEC15XX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select HAS_PM + +config SOC_MEC1501_HSZ + select HAS_MEC_HAL + +if SOC_SERIES_MEC15XX + +config RTOS_TIMER + bool "MEC1501 RTOS timer" + +config SOC_MEC1501_PROC_CLK_DIV + int "PROC_CLK_DIV" + default 1 + range 1 48 + help + This divisor defines a ratio between processor clock (HCLK) + and master clock (MCK): + HCLK = MCK / PROC_CLK_DIV + Allowed divider values: 1, 3, 4, 16, and 48. + +config SOC_MEC1501_VTR3_1_8V + bool "VTR3 power rail is tied to 1.8V" + help + Set this is if VTR3 power sourcejumper in the board is changed. + +config SOC_MEC1501_VCI_PINS_AS_GPIOS + bool "Use VCI block pins as GPIOS" + default y + help + By default these pins are not GPIOs, but HW controlled. + Set this if VCI pin block HW logic is not required in the board + design. + +choice + prompt "MEC1501 debug interface general configuration" + default SOC_MEC1501_DEBUG_WITHOUT_TRACING + depends on SOC_SERIES_MEC15XX + help + Select Debug SoC interface support for MEC15xx SoC family + + config SOC_MEC1501_DEBUG_DISABLED + bool "Disable debug support" + help + Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST# + pin is ignored. All other JTAG pins can be used as GPIOs + or other non-JTAG alternate functions. + + config SOC_MEC1501_DEBUG_WITHOUT_TRACING + bool "Debug support via Serial wire debug" + help + JTAG port in SWD mode. UART2 and ADC00-03 can be used. + + config SOC_MEC1501_DEBUG_AND_TRACING + bool "Debug support via Serial wire debug with tracing enabled" + help + JTAG port is enabled in SWD mode. Refer to tracing options + to see if ADC00-03 can be used or not. + +endchoice + +choice + prompt "MEC1501 debug interface trace configuration" + default SOC_MEC1501_DEBUG_AND_ETM_TRACING + depends on SOC_MEC1501_DEBUG_AND_TRACING + help + Select tracing mode for debug interface + + config SOC_MEC1501_DEBUG_AND_ETM_TRACING + bool "Debug support via Serial wire debug" + help + JTAG port in SWD mode and SWV as tracing method. + UART2 can be used, but ADC00-03 cannot. + + config SOC_MEC1501_DEBUG_AND_SWV_TRACING + bool "debug support via Serial Wire Debug and Viewer" + help + JTAG port in SWD mode and SWV as tracing method. + UART2 cannot be used. ADC00-03 can be used. +endchoice + +# GPIO initialization depends on SOC initialization, which happen at +# CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, so GPIO_INIT_PRIORITY needs to be +# higher than that. +if GPIO + +config GPIO_INIT_PRIORITY + default 41 + +endif # GPIO + +endif # SOC_SERIES_MEC15XX diff --git a/soc/arm/microchip_mec/mec1501/Kconfig.defconfig.mec1501hsz b/soc/microchip/mec/mec15xx/Kconfig.defconfig.mec1501hsz similarity index 88% rename from soc/arm/microchip_mec/mec1501/Kconfig.defconfig.mec1501hsz rename to soc/microchip/mec/mec15xx/Kconfig.defconfig.mec1501hsz index 052a198be50..d14e63d5e1f 100644 --- a/soc/arm/microchip_mec/mec1501/Kconfig.defconfig.mec1501hsz +++ b/soc/microchip/mec/mec15xx/Kconfig.defconfig.mec1501hsz @@ -5,9 +5,6 @@ if SOC_MEC1501_HSZ -config SOC - default "mec1501hsz" - config GPIO default y diff --git a/soc/microchip/mec/mec15xx/Kconfig.defconfig.series b/soc/microchip/mec/mec15xx/Kconfig.defconfig.series new file mode 100644 index 00000000000..d12e7023128 --- /dev/null +++ b/soc/microchip/mec/mec15xx/Kconfig.defconfig.series @@ -0,0 +1,29 @@ +# Microchip MEC MCU series configuration options + +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MEC15XX + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + # All NVIC external sources. + default 174 + +rsource "Kconfig.defconfig.mec1501*" + +if RTOS_TIMER + +config SOC_HAS_TIMING_FUNCTIONS + default y if !CORTEX_M_DWT + +config ARCH_HAS_CUSTOM_BUSY_WAIT + default y + +endif # RTOS_TIMER + +config CORTEX_M_SYSTICK + depends on !RTOS_TIMER + +endif # SOC_SERIES_MEC15XX diff --git a/soc/microchip/mec/mec15xx/Kconfig.soc b/soc/microchip/mec/mec15xx/Kconfig.soc new file mode 100644 index 00000000000..7d081a0b24a --- /dev/null +++ b/soc/microchip/mec/mec15xx/Kconfig.soc @@ -0,0 +1,20 @@ +# Microchip MEC1501 MCU core series + +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MEC15XX + bool + select SOC_FAMILY_MICROCHIP_MEC + help + Enable support for Microchip MEC Cortex-M4 MCU series + +config SOC_SERIES + default "mec15xx" if SOC_SERIES_MEC15XX + +config SOC_MEC1501_HSZ + bool + select SOC_SERIES_MEC15XX + +config SOC + default "mec1501_hsz" if SOC_MEC1501_HSZ diff --git a/soc/arm/microchip_mec/mec1501/device_power.c b/soc/microchip/mec/mec15xx/device_power.c similarity index 100% rename from soc/arm/microchip_mec/mec1501/device_power.c rename to soc/microchip/mec/mec15xx/device_power.c diff --git a/soc/arm/microchip_mec/mec1501/device_power.h b/soc/microchip/mec/mec15xx/device_power.h similarity index 100% rename from soc/arm/microchip_mec/mec1501/device_power.h rename to soc/microchip/mec/mec15xx/device_power.h diff --git a/soc/arm/microchip_mec/mec1501/power.c b/soc/microchip/mec/mec15xx/power.c similarity index 100% rename from soc/arm/microchip_mec/mec1501/power.c rename to soc/microchip/mec/mec15xx/power.c diff --git a/soc/arm/microchip_mec/mec1501/soc.c b/soc/microchip/mec/mec15xx/soc.c similarity index 100% rename from soc/arm/microchip_mec/mec1501/soc.c rename to soc/microchip/mec/mec15xx/soc.c diff --git a/soc/arm/microchip_mec/mec1501/soc.h b/soc/microchip/mec/mec15xx/soc.h similarity index 100% rename from soc/arm/microchip_mec/mec1501/soc.h rename to soc/microchip/mec/mec15xx/soc.h diff --git a/soc/arm/microchip_mec/mec1501/soc_espi_saf_v1.h b/soc/microchip/mec/mec15xx/soc_espi_saf_v1.h similarity index 100% rename from soc/arm/microchip_mec/mec1501/soc_espi_saf_v1.h rename to soc/microchip/mec/mec15xx/soc_espi_saf_v1.h diff --git a/soc/arm/microchip_mec/mec1501/timing.c b/soc/microchip/mec/mec15xx/timing.c similarity index 100% rename from soc/arm/microchip_mec/mec1501/timing.c rename to soc/microchip/mec/mec15xx/timing.c diff --git a/soc/microchip/mec/mec172x/CMakeLists.txt b/soc/microchip/mec/mec172x/CMakeLists.txt new file mode 100644 index 00000000000..b776b78c41d --- /dev/null +++ b/soc/microchip/mec/mec172x/CMakeLists.txt @@ -0,0 +1,24 @@ +# +# Copyright (c) 2021, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources(soc.c) +zephyr_include_directories(.) + +if(CONFIG_PM) + zephyr_library_sources(power.c device_power.c) +endif() + +if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) + if(CONFIG_TIMING_FUNCTIONS) + # Use MEC172x timing calculations only if DWT is not present + if(NOT CONFIG_CORTEX_M_DWT) + zephyr_library_sources(timing.c) + endif() + endif() +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/microchip/mec/mec172x/Kconfig b/soc/microchip/mec/mec172x/Kconfig new file mode 100644 index 00000000000..c529d83fc31 --- /dev/null +++ b/soc/microchip/mec/mec172x/Kconfig @@ -0,0 +1,76 @@ +# Microchip MEC172X MCU core series + +# Copyright (c) 2021 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MEC172X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_SWO + select HAS_PM + +if SOC_SERIES_MEC172X + +config RTOS_TIMER + bool "MEC172x RTOS Timer(32KHz) as kernel timer" + +choice + prompt "MEC172x debug interface general configuration" + default SOC_MEC172X_DEBUG_WITHOUT_TRACING + depends on SOC_SERIES_MEC172X + help + Select Debug SoC interface support for MEC172X SoC family + + config SOC_MEC172X_DEBUG_DISABLED + bool "Disable debug support" + help + Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST# + pin is ignored. All other JTAG pins can be used as GPIOs + or other non-JTAG alternate functions. + + config SOC_MEC172X_DEBUG_WITHOUT_TRACING + bool "Debug support via Serial wire debug" + help + JTAG port in SWD mode. I2C09 and ADC00-03 can be used. + + config SOC_MEC172X_DEBUG_AND_TRACING + bool "Debug support via Serial wire debug with tracing enabled" + help + JTAG port is enabled in SWD mode. Refer to tracing options + to see if ADC00-03 can be used or not. +endchoice + +choice + prompt "MEC172X debug interface trace configuration" + default SOC_MEC172X_DEBUG_AND_ETM_TRACING + depends on SOC_MEC172X_DEBUG_AND_TRACING + help + Select tracing mode for debug interface + + config SOC_MEC172X_DEBUG_AND_ETM_TRACING + bool "Debug support via Serial wire debug" + help + JTAG port in SWD mode and ETM as tracing method. + I2C09 can be used, but ADC00-03 cannot. + + config SOC_MEC172X_DEBUG_AND_SWV_TRACING + bool "debug support via Serial Wire Debug and Viewer" + help + JTAG port in SWD mode and SWV as tracing method. + I2C09 cannot be used. ADC00-03 can be used. +endchoice + +# GPIO initialization depends on ECIA initialization, which happen at +# CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, so GPIO_INIT_PRIORITY needs to be +# higher than that. +if GPIO + +config GPIO_INIT_PRIORITY + default 41 + +endif # GPIO + +endif # SOC_SERIES_MEC172X diff --git a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnlj b/soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnlj similarity index 89% rename from soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnlj rename to soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnlj index ad97e3bc5ef..daa19b0883c 100644 --- a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnlj +++ b/soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnlj @@ -5,9 +5,6 @@ if SOC_MEC172X_NLJ -config SOC - default "mec172xnlj" - config GPIO default y diff --git a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnsz b/soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnsz similarity index 84% rename from soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnsz rename to soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnsz index b218798465d..1f1c19e5624 100644 --- a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnsz +++ b/soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnsz @@ -5,9 +5,6 @@ if SOC_MEC172X_NSZ -config SOC - default "mec172xnsz" - config GPIO default y diff --git a/soc/microchip/mec/mec172x/Kconfig.defconfig.series b/soc/microchip/mec/mec172x/Kconfig.defconfig.series new file mode 100644 index 00000000000..016d13b6818 --- /dev/null +++ b/soc/microchip/mec/mec172x/Kconfig.defconfig.series @@ -0,0 +1,33 @@ +# Microchip MEC MCU series configuration options + +# Copyright (c) 2021 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MEC172X + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + # All NVIC external sources. + default 181 + +rsource "Kconfig.defconfig.mec172x*" + +if RTOS_TIMER + +config SOC_HAS_TIMING_FUNCTIONS + default y if !CORTEX_M_DWT + +config ARCH_HAS_CUSTOM_BUSY_WAIT + default y + +endif # RTOS_TIMER + +config CORTEX_M_SYSTICK + depends on !RTOS_TIMER + +config PS2_XEC + default y + depends on PS2 + +endif # SOC_SERIES_MEC172X diff --git a/soc/microchip/mec/mec172x/Kconfig.soc b/soc/microchip/mec/mec172x/Kconfig.soc new file mode 100644 index 00000000000..ac91b5177e3 --- /dev/null +++ b/soc/microchip/mec/mec172x/Kconfig.soc @@ -0,0 +1,25 @@ +# Microchip MEC172x MCU core series + +# Copyright (c) 2021 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MEC172X + bool + select SOC_FAMILY_MICROCHIP_MEC + help + Enable support for Microchip MEC Cortex-M4F MCU series + +config SOC_SERIES + default "mec172x" if SOC_SERIES_MEC172X + +config SOC_MEC172X_NSZ + bool + select SOC_SERIES_MEC172X + +config SOC_MEC172X_NLJ + bool + select SOC_SERIES_MEC172X + +config SOC + default "mec172x_nsz" if SOC_MEC172X_NSZ + default "mec172x_nlj" if SOC_MEC172X_NLJ diff --git a/soc/arm/microchip_mec/mec172x/device_power.c b/soc/microchip/mec/mec172x/device_power.c similarity index 100% rename from soc/arm/microchip_mec/mec172x/device_power.c rename to soc/microchip/mec/mec172x/device_power.c diff --git a/soc/arm/microchip_mec/mec172x/device_power.h b/soc/microchip/mec/mec172x/device_power.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/device_power.h rename to soc/microchip/mec/mec172x/device_power.h diff --git a/soc/arm/microchip_mec/mec172x/power.c b/soc/microchip/mec/mec172x/power.c similarity index 100% rename from soc/arm/microchip_mec/mec172x/power.c rename to soc/microchip/mec/mec172x/power.c diff --git a/soc/arm/microchip_mec/mec172x/reg/gpio_pkg_lj.h b/soc/microchip/mec/mec172x/reg/gpio_pkg_lj.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/gpio_pkg_lj.h rename to soc/microchip/mec/mec172x/reg/gpio_pkg_lj.h diff --git a/soc/arm/microchip_mec/mec172x/reg/gpio_pkg_sz.h b/soc/microchip/mec/mec172x/reg/gpio_pkg_sz.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/gpio_pkg_sz.h rename to soc/microchip/mec/mec172x/reg/gpio_pkg_sz.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_defs.h b/soc/microchip/mec/mec172x/reg/mec172x_defs.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_defs.h rename to soc/microchip/mec/mec172x/reg/mec172x_defs.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_ecia.h b/soc/microchip/mec/mec172x/reg/mec172x_ecia.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_ecia.h rename to soc/microchip/mec/mec172x/reg/mec172x_ecia.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_ecs.h b/soc/microchip/mec/mec172x/reg/mec172x_ecs.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_ecs.h rename to soc/microchip/mec/mec172x/reg/mec172x_ecs.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_emi.h b/soc/microchip/mec/mec172x/reg/mec172x_emi.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_emi.h rename to soc/microchip/mec/mec172x/reg/mec172x_emi.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_espi_iom.h b/soc/microchip/mec/mec172x/reg/mec172x_espi_iom.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_espi_iom.h rename to soc/microchip/mec/mec172x/reg/mec172x_espi_iom.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_espi_saf.h b/soc/microchip/mec/mec172x/reg/mec172x_espi_saf.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_espi_saf.h rename to soc/microchip/mec/mec172x/reg/mec172x_espi_saf.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_espi_vw.h b/soc/microchip/mec/mec172x/reg/mec172x_espi_vw.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_espi_vw.h rename to soc/microchip/mec/mec172x/reg/mec172x_espi_vw.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_gpio.h b/soc/microchip/mec/mec172x/reg/mec172x_gpio.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_gpio.h rename to soc/microchip/mec/mec172x/reg/mec172x_gpio.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_i2c_smb.h b/soc/microchip/mec/mec172x/reg/mec172x_i2c_smb.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_i2c_smb.h rename to soc/microchip/mec/mec172x/reg/mec172x_i2c_smb.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_p80bd.h b/soc/microchip/mec/mec172x/reg/mec172x_p80bd.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_p80bd.h rename to soc/microchip/mec/mec172x/reg/mec172x_p80bd.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_pcr.h b/soc/microchip/mec/mec172x/reg/mec172x_pcr.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_pcr.h rename to soc/microchip/mec/mec172x/reg/mec172x_pcr.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_qspi.h b/soc/microchip/mec/mec172x/reg/mec172x_qspi.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_qspi.h rename to soc/microchip/mec/mec172x/reg/mec172x_qspi.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_vbat.h b/soc/microchip/mec/mec172x/reg/mec172x_vbat.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_vbat.h rename to soc/microchip/mec/mec172x/reg/mec172x_vbat.h diff --git a/soc/arm/microchip_mec/mec172x/soc.c b/soc/microchip/mec/mec172x/soc.c similarity index 100% rename from soc/arm/microchip_mec/mec172x/soc.c rename to soc/microchip/mec/mec172x/soc.c diff --git a/soc/arm/microchip_mec/mec172x/soc.h b/soc/microchip/mec/mec172x/soc.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/soc.h rename to soc/microchip/mec/mec172x/soc.h diff --git a/soc/arm/microchip_mec/mec172x/soc_espi_saf_v2.h b/soc/microchip/mec/mec172x/soc_espi_saf_v2.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/soc_espi_saf_v2.h rename to soc/microchip/mec/mec172x/soc_espi_saf_v2.h diff --git a/soc/arm/microchip_mec/mec172x/soc_power_debug.h b/soc/microchip/mec/mec172x/soc_power_debug.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/soc_power_debug.h rename to soc/microchip/mec/mec172x/soc_power_debug.h diff --git a/soc/arm/microchip_mec/mec172x/timing.c b/soc/microchip/mec/mec172x/timing.c similarity index 100% rename from soc/arm/microchip_mec/mec172x/timing.c rename to soc/microchip/mec/mec172x/timing.c diff --git a/soc/microchip/mec/soc.yml b/soc/microchip/mec/soc.yml new file mode 100644 index 00000000000..6c20b24ff9f --- /dev/null +++ b/soc/microchip/mec/soc.yml @@ -0,0 +1,10 @@ +family: +- name: microchip_mec + series: + - name: mec15xx + socs: + - name: mec1501_hsz + - name: mec172x + socs: + - name: mec172x_nsz + - name: mec172x_nlj diff --git a/soc/riscv/gd_gd32/CMakeLists.txt b/soc/microchip/miv/CMakeLists.txt similarity index 100% rename from soc/riscv/gd_gd32/CMakeLists.txt rename to soc/microchip/miv/CMakeLists.txt diff --git a/soc/microchip/miv/Kconfig b/soc/microchip/miv/Kconfig new file mode 100644 index 00000000000..d509a538927 --- /dev/null +++ b/soc/microchip/miv/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_MIV + +rsource "*/Kconfig" + +endif # SOC_FAMILY_MICROCHIP_MIV diff --git a/soc/microchip/miv/Kconfig.defconfig b/soc/microchip/miv/Kconfig.defconfig new file mode 100644 index 00000000000..b63f842dd57 --- /dev/null +++ b/soc/microchip/miv/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_MIV + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_MICROCHIP_MIV diff --git a/soc/microchip/miv/Kconfig.soc b/soc/microchip/miv/Kconfig.soc new file mode 100644 index 00000000000..5725ff29b19 --- /dev/null +++ b/soc/microchip/miv/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_MICROCHIP_MIV + bool + +config SOC_FAMILY + default "microchip_miv" if SOC_FAMILY_MICROCHIP_MIV + +rsource "*/Kconfig.soc" diff --git a/soc/microchip/miv/miv/CMakeLists.txt b/soc/microchip/miv/miv/CMakeLists.txt new file mode 100644 index 00000000000..ee3378886b8 --- /dev/null +++ b/soc/microchip/miv/miv/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Antmicro + +zephyr_sources() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/microchip/miv/miv/Kconfig b/soc/microchip/miv/miv/Kconfig new file mode 100644 index 00000000000..132818de4e7 --- /dev/null +++ b/soc/microchip/miv/miv/Kconfig @@ -0,0 +1,18 @@ +# RISCV32_MIV configuration options + +# Copyright (c) 2018 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MIV + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + +config SOC_MIV + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/microchip/miv/miv/Kconfig.defconfig b/soc/microchip/miv/miv/Kconfig.defconfig new file mode 100644 index 00000000000..4e2653f5cd0 --- /dev/null +++ b/soc/microchip/miv/miv/Kconfig.defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Antmicro + +if SOC_SERIES_MIV + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 4000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 30 + +config NUM_IRQS + default 42 + +endif # SOC_SERIES_MIV diff --git a/soc/microchip/miv/miv/Kconfig.soc b/soc/microchip/miv/miv/Kconfig.soc new file mode 100644 index 00000000000..7e2eafe118e --- /dev/null +++ b/soc/microchip/miv/miv/Kconfig.soc @@ -0,0 +1,22 @@ +# RISCV32_MIV configuration options + +# Copyright (c) 2018 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MIV + bool + select SOC_FAMILY_MICROCHIP_MIV + help + Microchip Mi-V implementation# + +config SOC_MIV + bool + select SOC_SERIES_MIV + help + Microchip Mi-V system implementation + +config SOC_SERIES + default "miv" if SOC_SERIES_MIV + +config SOC + default "miv" if SOC_MIV diff --git a/soc/riscv/microchip_miv/miv/CMakeLists.txt b/soc/microchip/miv/polarfire/CMakeLists.txt similarity index 100% rename from soc/riscv/microchip_miv/miv/CMakeLists.txt rename to soc/microchip/miv/polarfire/CMakeLists.txt diff --git a/soc/microchip/miv/polarfire/Kconfig b/soc/microchip/miv/polarfire/Kconfig new file mode 100644 index 00000000000..b57d0ee92fb --- /dev/null +++ b/soc/microchip/miv/polarfire/Kconfig @@ -0,0 +1,28 @@ +# RISCV64_MIV Microchip Polarfire SOC configuration options + +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_POLARFIRE + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + +config SOC_POLARFIRE + select ATOMIC_OPERATIONS_BUILTIN + select RISCV_GP + select USE_SWITCH_SUPPORTED + select USE_SWITCH + select CPU_HAS_FPU + select SCHED_IPI_SUPPORTED + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + +config MPFS_HAL + depends on SOC_POLARFIRE + bool "Microchip Polarfire SOC hardware abstracton layer" + select HAS_MPFS_HAL diff --git a/soc/microchip/miv/polarfire/Kconfig.defconfig b/soc/microchip/miv/polarfire/Kconfig.defconfig new file mode 100644 index 00000000000..113a3bd6acb --- /dev/null +++ b/soc/microchip/miv/polarfire/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_POLARFIRE + +# MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock... + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 13 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 186 + +config NUM_IRQS + default 186 + +endif # SOC_SERIES_POLARFIRE diff --git a/soc/microchip/miv/polarfire/Kconfig.soc b/soc/microchip/miv/polarfire/Kconfig.soc new file mode 100644 index 00000000000..ce44e8b8ada --- /dev/null +++ b/soc/microchip/miv/polarfire/Kconfig.soc @@ -0,0 +1,22 @@ +# RISCV64_MIV Microchip Polarfire SOC configuration options + +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_POLARFIRE + bool + select SOC_FAMILY_MICROCHIP_MIV + help + Microchip RV64 implementation + +config SOC_POLARFIRE + bool + select SOC_SERIES_POLARFIRE + help + Microchip MPFS system implementation + +config SOC_SERIES + default "polarfire" if SOC_SERIES_POLARFIRE + +config SOC + default "polarfire" if SOC_POLARFIRE diff --git a/soc/microchip/miv/soc.yml b/soc/microchip/miv/soc.yml new file mode 100644 index 00000000000..11f30cffc32 --- /dev/null +++ b/soc/microchip/miv/soc.yml @@ -0,0 +1,9 @@ +family: +- name: microchip_miv + series: + - name: miv + socs: + - name: miv + - name: polarfire + socs: + - name: polarfire diff --git a/soc/mips/CMakeLists.txt b/soc/mips/CMakeLists.txt deleted file mode 100644 index f4733688cca..00000000000 --- a/soc/mips/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) -else() - add_subdirectory(${SOC_NAME}) -endif() diff --git a/soc/mips/qemu_malta/CMakeLists.txt b/soc/mips/qemu_malta/CMakeLists.txt deleted file mode 100644 index 351ffebf5b5..00000000000 --- a/soc/mips/qemu_malta/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2020, 2021 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_compile_options( - -mips32 - ${TOOLCHAIN_C_FLAGS} -) - -zephyr_sources( - vector.S -) - -zephyr_ld_options( - -mips32 - ${TOOLCHAIN_LD_FLAGS} -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/mips/linker.ld CACHE INTERNAL "") diff --git a/soc/mips/qemu_malta/Kconfig.defconfig b/soc/mips/qemu_malta/Kconfig.defconfig deleted file mode 100644 index c2811c31ac6..00000000000 --- a/soc/mips/qemu_malta/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2020 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_MALTA - -config SOC - default "qemu_malta" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 200000000 - -config NUM_IRQS - default 8 - -endif # SOC_QEMU_MALTA diff --git a/soc/mips/qemu_malta/Kconfig.soc b/soc/mips/qemu_malta/Kconfig.soc deleted file mode 100644 index d18a881bd0a..00000000000 --- a/soc/mips/qemu_malta/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2020 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_MALTA - bool "MIPS Qemu Malta implementation" - select MIPS diff --git a/soc/native/inf_clock/CMakeLists.txt b/soc/native/inf_clock/CMakeLists.txt new file mode 100644 index 00000000000..7f9d09b2c34 --- /dev/null +++ b/soc/native/inf_clock/CMakeLists.txt @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +zephyr_library() + +zephyr_library_compile_definitions(NO_POSIX_CHEATS) + +zephyr_library_sources( + soc.c + native_tasks.c + ) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/posix/include + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/posix/linker.ld CACHE INTERNAL "") diff --git a/soc/native/inf_clock/Kconfig b/soc/native/inf_clock/Kconfig new file mode 100644 index 00000000000..4453d3dbccc --- /dev/null +++ b/soc/native/inf_clock/Kconfig @@ -0,0 +1,57 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_POSIX + select ARCH_POSIX + select CPU_HAS_FPU + +if SOC_POSIX + +config NATIVE_SIMULATOR_MCU_N + int "CPU Number this image targets" + range 0 15 + default 0 + depends on NATIVE_LIBRARY + help + Which native simulator microcontroller/CPU number is this image targeting. + This option is only applicable for targets which use the + native simulator as their runner. + +config NATIVE_SIMULATOR_NUMBER_MCUS + int "Total number of MCUs this target has" + range 1 16 + default 1 + depends on NATIVE_LIBRARY + help + How many AMP MCUs does this target have in total. + +config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX + int "Which CPU is the primary/preferred" + default 0 + depends on NATIVE_LIBRARY + help + On a multi MCU device, which MCU is the preferred one. + This MCU will for example have its tests command line parameters presented + without any prefix. Note that an MCU being primary does not imply it will be + the first one to boot, or even that it will boot automatically. + +config NATIVE_SIMULATOR_EXTRA_IMAGE_PATHS + string "Other cores images to include" + depends on NATIVE_LIBRARY + help + This option can be used to provide the native simulator with other MCUs/Cores images which have + been produced by either other Zephyr builds or different OS builds. + So you can, for ex., use this application build to produce one core image, and at the same time + have it produce the final link with the native simulator runner and the other MCU images. + +config NATIVE_SIMULATOR_AUTOSTART_MCU + bool "Auto-start this MCU" + depends on NATIVE_LIBRARY + help + Automatically start the MCU this Zephyr image is built for during HW boot, + even if in other circumstances this MCU would not start automatically (for ex. because + another core is meant to release its reset). + If that MCU was, by HW design, going to start at HW boot anyhow, this option does nothing. + This option is meant to facilitate development. + +endif # SOC_POSIX diff --git a/soc/native/inf_clock/Kconfig.soc b/soc/native/inf_clock/Kconfig.soc new file mode 100644 index 00000000000..62667c55a97 --- /dev/null +++ b/soc/native/inf_clock/Kconfig.soc @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +config SOC_POSIX + bool + help + SOC for to the POSIX arch. It emulates a CPU running at an infinitely fast + clock. That means the CPU will always run in zero time until completion after + each wake reason (e.g. interrupts), before going back to idle. Note that an + infinite loop in the code which does not sleep the CPU will cause the process + to appear "hung", as simulated time does not advance while the CPU does not + sleep. Therefore do not use busy waits while waiting for something to happen + (if needed use k_busy_wait()). + Note that the interrupt handling is provided by the board. + +config SOC + default "native" if SOC_POSIX diff --git a/soc/posix/inf_clock/native_tasks.c b/soc/native/inf_clock/native_tasks.c similarity index 100% rename from soc/posix/inf_clock/native_tasks.c rename to soc/native/inf_clock/native_tasks.c diff --git a/soc/posix/inf_clock/posix_board_if.h b/soc/native/inf_clock/posix_board_if.h similarity index 100% rename from soc/posix/inf_clock/posix_board_if.h rename to soc/native/inf_clock/posix_board_if.h diff --git a/soc/posix/inf_clock/posix_native_task.h b/soc/native/inf_clock/posix_native_task.h similarity index 100% rename from soc/posix/inf_clock/posix_native_task.h rename to soc/native/inf_clock/posix_native_task.h diff --git a/soc/posix/inf_clock/posix_soc.h b/soc/native/inf_clock/posix_soc.h similarity index 100% rename from soc/posix/inf_clock/posix_soc.h rename to soc/native/inf_clock/posix_soc.h diff --git a/soc/posix/inf_clock/soc.c b/soc/native/inf_clock/soc.c similarity index 100% rename from soc/posix/inf_clock/soc.c rename to soc/native/inf_clock/soc.c diff --git a/soc/posix/inf_clock/soc.h b/soc/native/inf_clock/soc.h similarity index 100% rename from soc/posix/inf_clock/soc.h rename to soc/native/inf_clock/soc.h diff --git a/soc/native/inf_clock/soc.yml b/soc/native/inf_clock/soc.yml new file mode 100644 index 00000000000..67eb6b9f61b --- /dev/null +++ b/soc/native/inf_clock/soc.yml @@ -0,0 +1,4 @@ +family: +- name: native + socs: + - name: native diff --git a/soc/posix/inf_clock/soc_irq.h b/soc/native/inf_clock/soc_irq.h similarity index 100% rename from soc/posix/inf_clock/soc_irq.h rename to soc/native/inf_clock/soc_irq.h diff --git a/soc/riscv/neorv32/CMakeLists.txt b/soc/neorv32/CMakeLists.txt similarity index 100% rename from soc/riscv/neorv32/CMakeLists.txt rename to soc/neorv32/CMakeLists.txt diff --git a/soc/neorv32/Kconfig b/soc/neorv32/Kconfig new file mode 100644 index 00000000000..6df6c6d2b7c --- /dev/null +++ b/soc/neorv32/Kconfig @@ -0,0 +1,35 @@ +# Copyright (c) 2021 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NEORV32 + select RISCV + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_PRIVILEGED + +if SOC_NEORV32 + +config SOC_NEORV32_V1_8_6 + bool "v1.8.6" + # NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO + select ATOMIC_OPERATIONS_C + +config SOC_NEORV32_VERSION + hex + default 0x01080600 if SOC_NEORV32_V1_8_6 + help + The targeted NEORV32 version as BCD-coded number. The format is + identical to that of the NEORV32 Machine implementation ID (mimpid) + register. + +config SOC_NEORV32_ISA_C + bool "RISC-V ISA Extension \"C\"" + select RISCV_ISA_EXT_C + help + Enable this if the NEORV32 CPU implementation supports the RISC-V ISA + "C" extension (Compressed Instructions). + +endif # SOC_NEORV32 diff --git a/soc/neorv32/Kconfig.defconfig b/soc/neorv32/Kconfig.defconfig new file mode 100644 index 00000000000..67d458f7398 --- /dev/null +++ b/soc/neorv32/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2021 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NEORV32 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if RISCV_MACHINE_TIMER + +config NUM_IRQS + default 32 + +config RISCV_GP + default y + +config SYSCON + default y + +config SERIAL_INIT_PRIORITY + default 55 + depends on SERIAL + +config ENTROPY_INIT_PRIORITY + default 55 + depends on ENTROPY_GENERATOR + +endif # SOC_NEORV32 diff --git a/soc/neorv32/Kconfig.soc b/soc/neorv32/Kconfig.soc new file mode 100644 index 00000000000..37a28ec7b44 --- /dev/null +++ b/soc/neorv32/Kconfig.soc @@ -0,0 +1,22 @@ +# Copyright (c) 2021 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NEORV32 + bool + help + NEORV32 Processor (SoC). + + The NEORV32 CPU implementation must have the following RISC-V ISA + extensions enabled in order to support Zephyr: + - M (Integer Multiplication and Division) + - Zicsr (Control and Status Register (CSR) Instructions) + + The following NEORV32 CPU ISA extensions are not currently supported + by Zephyr and can safely be disabled: + - A (Atomic Instructions) + - E (Embedded, only 16 integer registers) + - Zbb (Basic Bit Manipulation) + - Zfinx (Floating Point in Integer Registers) + +config SOC + default "neorv32" if SOC_NEORV32 diff --git a/soc/riscv/neorv32/linker.ld b/soc/neorv32/linker.ld similarity index 100% rename from soc/riscv/neorv32/linker.ld rename to soc/neorv32/linker.ld diff --git a/soc/riscv/neorv32/reset.S b/soc/neorv32/reset.S similarity index 100% rename from soc/riscv/neorv32/reset.S rename to soc/neorv32/reset.S diff --git a/soc/riscv/neorv32/soc.c b/soc/neorv32/soc.c similarity index 100% rename from soc/riscv/neorv32/soc.c rename to soc/neorv32/soc.c diff --git a/soc/riscv/neorv32/soc.h b/soc/neorv32/soc.h similarity index 100% rename from soc/riscv/neorv32/soc.h rename to soc/neorv32/soc.h diff --git a/soc/neorv32/soc.yml b/soc/neorv32/soc.yml new file mode 100644 index 00000000000..c2e51c22777 --- /dev/null +++ b/soc/neorv32/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: neorv32 diff --git a/soc/riscv/neorv32/soc_irq.S b/soc/neorv32/soc_irq.S similarity index 100% rename from soc/riscv/neorv32/soc_irq.S rename to soc/neorv32/soc_irq.S diff --git a/soc/nios2/nios2-qemu/CMakeLists.txt b/soc/nios2/nios2-qemu/CMakeLists.txt deleted file mode 100644 index b6dd454d035..00000000000 --- a/soc/nios2/nios2-qemu/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(include) -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nios2/nios2-qemu/Kconfig.defconfig b/soc/nios2/nios2-qemu/Kconfig.defconfig deleted file mode 100644 index 453af05cd8c..00000000000 --- a/soc/nios2/nios2-qemu/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NIOS2_QEMU - -config SOC - default "nios2-qemu" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 50000000 - -endif diff --git a/soc/nios2/nios2-qemu/Kconfig.soc b/soc/nios2/nios2-qemu/Kconfig.soc deleted file mode 100644 index 0f670e4e4c6..00000000000 --- a/soc/nios2/nios2-qemu/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NIOS2_QEMU - bool "Nios II - Experimental QEMU emulation" - select NIOS2 - select HAS_MUL_INSTRUCTION - select HAS_DIV_INSTRUCTION - select HAS_MULX_INSTRUCTION diff --git a/soc/nios2/nios2f-zephyr/CMakeLists.txt b/soc/nios2/nios2f-zephyr/CMakeLists.txt deleted file mode 100644 index 789c4c81fc9..00000000000 --- a/soc/nios2/nios2f-zephyr/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(include) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nios2/nios2f-zephyr/Kconfig.defconfig b/soc/nios2/nios2f-zephyr/Kconfig.defconfig deleted file mode 100644 index 3ffa3f9e14b..00000000000 --- a/soc/nios2/nios2f-zephyr/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NIOS2F_ZEPHYR - -config SOC - default "nios2f-zephyr" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 50000000 - -config ALTERA_AVALON_SYSID - def_bool y - -config ALTERA_AVALON_QSPI - def_bool y - depends on SOC_FLASH_NIOS2_QSPI - -config ALTERA_AVALON_I2C - def_bool y - depends on I2C_NIOS2 - -config ALTERA_AVALON_MSGDMA - def_bool y - depends on DMA_NIOS2_MSGDMA - -endif # SOC_NIOS2F_ZEPHYR diff --git a/soc/nios2/nios2f-zephyr/Kconfig.soc b/soc/nios2/nios2f-zephyr/Kconfig.soc deleted file mode 100644 index 15e12382631..00000000000 --- a/soc/nios2/nios2f-zephyr/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NIOS2F_ZEPHYR - bool "Nios IIf - Zephyr Golden Configuration" - select NIOS2 - select HAS_MUL_INSTRUCTION - select HAS_DIV_INSTRUCTION diff --git a/soc/nordic/CMakeLists.txt b/soc/nordic/CMakeLists.txt new file mode 100644 index 00000000000..9e0619772e2 --- /dev/null +++ b/soc/nordic/CMakeLists.txt @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +if(CONFIG_ARM) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "SoC Linker script") + + zephyr_library_sources( + validate_base_addresses.c + validate_enabled_instances.c + ) +endif() + +if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) + if(CONFIG_TIMING_FUNCTIONS) + # Use nRF-specific timing calculations only if DWT is not present + if(NOT CONFIG_CORTEX_M_DWT) + zephyr_library_sources(timing.c) + endif() + endif() +endif() + +if(CONFIG_BUILD_WITH_TFM) + set_property(TARGET zephyr_property_target + APPEND PROPERTY TFM_CMAKE_OPTIONS -DHAL_NORDIC_PATH=${ZEPHYR_HAL_NORDIC_MODULE_DIR} + ) + + set_property(TARGET zephyr_property_target + APPEND PROPERTY TFM_CMAKE_OPTIONS -DZEPHYR_BASE=${ZEPHYR_BASE} + ) + + set_property(TARGET zephyr_property_target + APPEND PROPERTY TFM_CMAKE_OPTIONS -DNRF_NS_STORAGE=${CONFIG_TFM_NRF_NS_STORAGE} + ) +endif() + +add_subdirectory(${SOC_SERIES}) +add_subdirectory(common) diff --git a/soc/nordic/Kconfig b/soc/nordic/Kconfig new file mode 100644 index 00000000000..ca0a152272e --- /dev/null +++ b/soc/nordic/Kconfig @@ -0,0 +1,174 @@ +# Nordic Semiconductor nRFx MCU line + +# Copyright (c) 2016-2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# This file is contains Zephyr build system Kconfig references and is not +# re-usable outside the Zephyr tree. + +config SOC_FAMILY_NORDIC_NRF + select SOC_COMPATIBLE_NRF + select PLATFORM_SPECIFIC_INIT if ARM + +if SOC_FAMILY_NORDIC_NRF + +rsource "common/Kconfig.peripherals" +rsource "*/Kconfig" + +config NRF_SOC_SECURE_SUPPORTED + def_bool !TRUSTED_EXECUTION_NONSECURE || (BUILD_WITH_TFM && TFM_PARTITION_PLATFORM) + depends on !SOC_SERIES_NRF54HX + help + Hidden function to indicate that that the soc_secure functions are + available. + The functions are always available when not in non-secure. + For non-secure the functions must redirect to secure services exposed + by the secure firmware. + +config BUILD_WITH_TFM + default y if TRUSTED_EXECUTION_NONSECURE + help + By default, if we build for a Non-Secure version of the board, + enable building with TF-M as the Secure Execution Environment. + +if BUILD_WITH_TFM + +config TFM_FLASH_MERGED_BINARY + default y + help + By default, if we build with TF-M, instruct build system to + flash the combined TF-M (Secure) & Zephyr (Non Secure) image + +config TFM_LOG_LEVEL_SILENCE + default y if !$(dt_nodelabel_has_prop,uart1,pinctrl-names) + help + Disable TF-M secure output if the uart1 node has not assigned GPIO + pins using pinctrl. + +config TFM_NRF_NS_STORAGE + bool "TF-M non-secure storage partition" + default y + +endif # BUILD_WITH_TFM + + +config NRF_MPU_FLASH_REGION_SIZE + hex + default 0x1000 + depends on HAS_HW_NRF_MPU + help + FLASH region size for the NRF_MPU peripheral. + +config NRF_BPROT_FLASH_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_CHOSEN_ZEPHYR_FLASH),erase-block-size) + depends on HAS_HW_NRF_BPROT + help + FLASH region size for the NRF_BPROT peripheral (nRF52). + +config NRF_ACL_FLASH_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_CHOSEN_ZEPHYR_FLASH),erase-block-size) + depends on HAS_HW_NRF_ACL + help + FLASH region size for the NRF_ACL peripheral. + +config NFCT_PINS_AS_GPIOS + bool "[DEPRECATED] NFCT pins as GPIOs" + depends on $(dt_has_compat,$(DT_COMPAT_NORDIC_NRF_NFCT)) + select DEPRECATED + help + Two pins are usually reserved for NFC in SoCs that implement the + NFCT peripheral. This option switches them to normal GPIO mode. + HW enabling happens once in the device lifetime, during the first + system startup. Disabling this option will not switch back these + pins to NFCT mode. Doing this requires UICR erase prior to + flashing device using the image which has this option disabled. + + NFC pins in nRF52 series: P0.09 and P0.10 + NFC pins in nRF5340: P0.02 and P0.03 + + This option is deprecated, please use devicetree to configure NFCT + pins as GPIOS like this: + + &uicr { + nfct-pins-as-gpios; + }; + +choice NRF_APPROTECT_HANDLING + bool "APPROTECT handling" + depends on SOC_SERIES_NRF52X || SOC_NRF5340_CPUNET || \ + (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) || \ + SOC_SERIES_NRF91X + default NRF_APPROTECT_USE_UICR + help + Specifies how the SystemInit() function should handle the APPROTECT + mechanism. + +config NRF_APPROTECT_USE_UICR + bool "Use UICR" + help + When this option is selected, the SystemInit() function loads the + firmware branch state of the APPROTECT mechanism from UICR, so if + UICR->APPROTECT is disabled, CTRLAP->APPROTECT will be disabled. + +config NRF_APPROTECT_LOCK + bool "Lock" + help + When this option is selected, the SystemInit() function locks + the firmware branch of the APPROTECT mechanism, preventing it + from being opened. + +config NRF_APPROTECT_USER_HANDLING + bool "Allow user handling" + depends on !SOC_SERIES_NRF52X + help + When this option is selected, the SystemInit() function does not + touch the APPROTECT mechanism, allowing the user code to handle it + at later stages, for example, to implement authenticated debug. + +endchoice + +choice NRF_SECURE_APPROTECT_HANDLING + bool "Secure APPROTECT handling" + depends on (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) + default NRF_SECURE_APPROTECT_USE_UICR + help + Specifies how the SystemInit() function should handle the secure + APPROTECT mechanism. + +config NRF_SECURE_APPROTECT_USE_UICR + bool "Use UICR" + help + When this option is selected, the SystemInit() function loads the + firmware branch state of the secure APPROTECT mechanism from UICR, + so if UICR->SECUREAPPROTECT is disabled, CTRLAP->SECUREAPPROTECT + will be disabled. + +config NRF_SECURE_APPROTECT_LOCK + bool "Lock" + help + When this option is selected, the SystemInit() function locks the + firmware branch of the secure APPROTECT mechanism, preventing it + from being opened. + +config NRF_SECURE_APPROTECT_USER_HANDLING + bool "Allow user handling" + depends on !SOC_SERIES_NRF52X + help + When this option is selected, the SystemInit() function does not + touch the secure APPROTECT mechanism, allowing the user code to + handle it at later stages, for example, to implement authenticated + debug. + +endchoice + +config NRF_TRACE_PORT + bool "nRF TPIU" + depends on !SOC_SERIES_NRF51X + help + Enable this option to initialize the TPIU (Trace Port Interface + Unit) for tracing using a hardware probe. If disabled, the trace + pins will be used as GPIO. + +endif # SOC_FAMILY_NORDIC_NRF diff --git a/soc/nordic/Kconfig.defconfig b/soc/nordic/Kconfig.defconfig new file mode 100644 index 00000000000..5e7e9c5a09d --- /dev/null +++ b/soc/nordic/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Nordic Semiconductor nRFx MCU line + +# Copyright (c) 2016-2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NORDIC_NRF + +rsource "*/Kconfig.defconfig" + +# If the kernel has timer support, enable clock control +if SYS_CLOCK_EXISTS + +config CLOCK_CONTROL + default y if !SOC_SERIES_NRF54HX + +endif # SYS_CLOCK_EXISTS + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 if NRF_GRTC_TIMER + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 128 if !TICKLESS_KERNEL + default 10000 if NRF_GRTC_TIMER + default 32768 + +config ARCH_HAS_CUSTOM_BUSY_WAIT + default y if ARM && !QEMU_TARGET + +config BUILD_OUTPUT_HEX + default y + +if !CORTEX_M_DWT && NRF_RTC_TIMER +config SOC_HAS_TIMING_FUNCTIONS + default y +endif + +config GPIO + default y + depends on SPI + +config UART_USE_RUNTIME_CONFIGURE + default n + +endif # SOC_FAMILY_NORDIC_NRF diff --git a/soc/nordic/Kconfig.soc b/soc/nordic/Kconfig.soc new file mode 100644 index 00000000000..2e47fcb4736 --- /dev/null +++ b/soc/nordic/Kconfig.soc @@ -0,0 +1,59 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +# This file contains Zephyr hw module v2 Kconfig description for +# Nordic Semiconductor SoCs. +# The hw model v2 is generic and contains no Kconfig references outside its own +# tree structure and is therefore reusable in Kconfig trees outside a Zephyr build. + +config SOC_SERIES + default "nrf51" if SOC_SERIES_NRF51X + default "nrf52" if SOC_SERIES_NRF52X + default "nrf53" if SOC_SERIES_NRF53X + default "nrf54h" if SOC_SERIES_NRF54HX + default "nrf54l" if SOC_SERIES_NRF54LX + default "nrf91" if SOC_SERIES_NRF91X + +config SOC_FAMILY_NORDIC_NRF + bool + +config SOC_FAMILY + default "nordic_nrf" if SOC_FAMILY_NORDIC_NRF + +config SOC_SERIES_NRF51X + bool + help + Enable support for NRF51 MCU series + +config SOC_SERIES_NRF52X + bool + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF52 MCU series + +config SOC_SERIES_NRF53X + bool + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF53 MCU series + +config SOC_SERIES_NRF54HX + bool + select SOC_FAMILY_NORDIC_NRF + help + Nordic Semiconductor nRF54H series MCU + +config SOC_SERIES_NRF54LX + bool + select SOC_FAMILY_NORDIC_NRF + help + Nordic Semiconductor nRF54L series MCU + +config SOC_SERIES_NRF91X + bool + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF91 MCU series + +rsource "*/Kconfig.soc" diff --git a/soc/nordic/common/CMakeLists.txt b/soc/nordic/common/CMakeLists.txt new file mode 100644 index 00000000000..d3cb84fd451 --- /dev/null +++ b/soc/nordic/common/CMakeLists.txt @@ -0,0 +1,19 @@ +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr) + +if(CONFIG_ARM AND CONFIG_SOC_FAMILY_NORDIC_NRF) + zephyr_library_sources(soc_nrf_common.S) +endif() + +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_include_directories(.) + +if(CONFIG_TFM_PARTITION_PLATFORM) + zephyr_library_sources(soc_secure.c) + zephyr_library_include_directories( + $/api_ns/interface/include + ) +endif() diff --git a/soc/nordic/common/Kconfig b/soc/nordic/common/Kconfig new file mode 100644 index 00000000000..54e2356c6af --- /dev/null +++ b/soc/nordic/common/Kconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +rsource "vpr/Kconfig" diff --git a/soc/nordic/common/Kconfig.defconfig b/soc/nordic/common/Kconfig.defconfig new file mode 100644 index 00000000000..077a73ad24d --- /dev/null +++ b/soc/nordic/common/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if RISCV_CORE_NORDIC_VPR + +rsource "vpr/Kconfig.defconfig" + +endif # RISCV_CORE_NORDIC_VPR diff --git a/soc/common/nordic_nrf/Kconfig.peripherals b/soc/nordic/common/Kconfig.peripherals similarity index 100% rename from soc/common/nordic_nrf/Kconfig.peripherals rename to soc/nordic/common/Kconfig.peripherals diff --git a/soc/common/nordic_nrf/pinctrl_soc.h b/soc/nordic/common/pinctrl_soc.h similarity index 100% rename from soc/common/nordic_nrf/pinctrl_soc.h rename to soc/nordic/common/pinctrl_soc.h diff --git a/soc/arm/nordic_nrf/common/poweroff.c b/soc/nordic/common/poweroff.c similarity index 100% rename from soc/arm/nordic_nrf/common/poweroff.c rename to soc/nordic/common/poweroff.c diff --git a/soc/arm/nordic_nrf/common/soc_nrf_common.S b/soc/nordic/common/soc_nrf_common.S similarity index 100% rename from soc/arm/nordic_nrf/common/soc_nrf_common.S rename to soc/nordic/common/soc_nrf_common.S diff --git a/soc/arm/nordic_nrf/common/soc_nrf_common.h b/soc/nordic/common/soc_nrf_common.h similarity index 100% rename from soc/arm/nordic_nrf/common/soc_nrf_common.h rename to soc/nordic/common/soc_nrf_common.h diff --git a/soc/arm/nordic_nrf/common/soc_secure.c b/soc/nordic/common/soc_secure.c similarity index 100% rename from soc/arm/nordic_nrf/common/soc_secure.c rename to soc/nordic/common/soc_secure.c diff --git a/soc/arm/nordic_nrf/common/soc_secure.h b/soc/nordic/common/soc_secure.h similarity index 100% rename from soc/arm/nordic_nrf/common/soc_secure.h rename to soc/nordic/common/soc_secure.h diff --git a/soc/nordic/common/vpr/CMakeLists.txt b/soc/nordic/common/vpr/CMakeLists.txt new file mode 100644 index 00000000000..f69b830b465 --- /dev/null +++ b/soc/nordic/common/vpr/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library_sources(soc_irq.S soc_irq.c vector.S) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/nordic_nrf/common/vpr/Kconfig b/soc/nordic/common/vpr/Kconfig similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/Kconfig rename to soc/nordic/common/vpr/Kconfig diff --git a/soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig b/soc/nordic/common/vpr/Kconfig.defconfig similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig rename to soc/nordic/common/vpr/Kconfig.defconfig diff --git a/soc/riscv/nordic_nrf/common/vpr/soc_context.h b/soc/nordic/common/vpr/soc_context.h similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/soc_context.h rename to soc/nordic/common/vpr/soc_context.h diff --git a/soc/riscv/nordic_nrf/common/vpr/soc_irq.S b/soc/nordic/common/vpr/soc_irq.S similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/soc_irq.S rename to soc/nordic/common/vpr/soc_irq.S diff --git a/soc/riscv/nordic_nrf/common/vpr/soc_irq.c b/soc/nordic/common/vpr/soc_irq.c similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/soc_irq.c rename to soc/nordic/common/vpr/soc_irq.c diff --git a/soc/riscv/nordic_nrf/common/vpr/soc_isr_stacking.h b/soc/nordic/common/vpr/soc_isr_stacking.h similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/soc_isr_stacking.h rename to soc/nordic/common/vpr/soc_isr_stacking.h diff --git a/soc/riscv/nordic_nrf/common/vpr/soc_offsets.h b/soc/nordic/common/vpr/soc_offsets.h similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/soc_offsets.h rename to soc/nordic/common/vpr/soc_offsets.h diff --git a/soc/riscv/nordic_nrf/common/vpr/vector.S b/soc/nordic/common/vpr/vector.S similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/vector.S rename to soc/nordic/common/vpr/vector.S diff --git a/soc/nordic/nrf51/CMakeLists.txt b/soc/nordic/nrf51/CMakeLists.txt new file mode 100644 index 00000000000..53398751982 --- /dev/null +++ b/soc/nordic/nrf51/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources(soc.c) +zephyr_include_directories(.) diff --git a/soc/nordic/nrf51/Kconfig b/soc/nordic/nrf51/Kconfig new file mode 100644 index 00000000000..e212c7ecd66 --- /dev/null +++ b/soc/nordic/nrf51/Kconfig @@ -0,0 +1,13 @@ +# Nordic Semiconductor nRF51 MCU line + +# Copyright (c) 2016 Linaro Limited +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF51X + select ARM + select CPU_CORTEX_M0 + imply XIP + select HAS_NRFX + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_POWEROFF diff --git a/soc/nordic/nrf51/Kconfig.defconfig b/soc/nordic/nrf51/Kconfig.defconfig new file mode 100644 index 00000000000..0168531e1d5 --- /dev/null +++ b/soc/nordic/nrf51/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Nordic Semiconductor nRF51 MCU line + +# Copyright (c) 2016 Linaro Limited +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF51X + +config NUM_IRQS + default 26 + +# If the kernel has timer support, enable the timer +config NRF_RTC_TIMER + default y if SYS_CLOCK_EXISTS + +endif # SOC_SERIES_NRF51X diff --git a/soc/nordic/nrf51/Kconfig.soc b/soc/nordic/nrf51/Kconfig.soc new file mode 100644 index 00000000000..c19da7a18a1 --- /dev/null +++ b/soc/nordic/nrf51/Kconfig.soc @@ -0,0 +1,24 @@ +# Nordic Semiconductor nRF51 MCU line + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF51X + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF51 MCU series + +config SOC_NRF51822_QFAA + bool + select SOC_SERIES_NRF51X + +config SOC_NRF51822_QFAB + bool + select SOC_SERIES_NRF51X + +config SOC_NRF51822_QFAC + bool + select SOC_SERIES_NRF51X + +config SOC + default "nrf51822" if SOC_NRF51822_QFAA || SOC_NRF51822_QFAB || SOC_NRF51822_QFAC diff --git a/soc/arm/nordic_nrf/nrf51/soc.c b/soc/nordic/nrf51/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf51/soc.c rename to soc/nordic/nrf51/soc.c diff --git a/soc/arm/nordic_nrf/nrf51/soc.h b/soc/nordic/nrf51/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf51/soc.h rename to soc/nordic/nrf51/soc.h diff --git a/soc/nordic/nrf52/CMakeLists.txt b/soc/nordic/nrf52/CMakeLists.txt new file mode 100644 index 00000000000..6b01a1ffc77 --- /dev/null +++ b/soc/nordic/nrf52/CMakeLists.txt @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources(soc.c) +zephyr_include_directories(.) + +if(CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 AND CONFIG_SPI_NRFX_SPIM) + message(WARNING "Both SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 and an NRF SPIM driver are enabled, therefore PAN 58 will apply if RXD.MAXCNT == 1 and TXD.MAXCNT <= 1") +endif() + +if(CONFIG_SOC_NRF52832) + if(NOT CONFIG_NRF52_ANOMALY_109_WORKAROUND) + if (CONFIG_NRFX_SPIS OR CONFIG_NRFX_SPIM OR CONFIG_NRFX_TWIM OR CONFIG_NRFX_PWM) + message(WARNING "NRF52_ANOMALY_109_WORKAROUND disabled with SPIS, SPIM, TWIM or PWM enabled. This will occasionally cause the first byte transmitted to be incorrect") + endif() + endif() +endif() diff --git a/soc/nordic/nrf52/Kconfig b/soc/nordic/nrf52/Kconfig new file mode 100644 index 00000000000..b248b972f94 --- /dev/null +++ b/soc/nordic/nrf52/Kconfig @@ -0,0 +1,106 @@ +# Nordic Semiconductor nRF52 MCU line + +# Copyright (c) 2016-2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF52X + select ARM + select SOC_COMPATIBLE_NRF52X + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + imply XIP + select HAS_NRFX + select HAS_NORDIC_DRIVERS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_SWO + select HAS_POWEROFF + +config SOC_NRF52832 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + +config SOC_NRF52833 + select SOC_COMPATIBLE_NRF52833 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + +config SOC_NRF52840 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + +if SOC_SERIES_NRF52X + +config SOC_DCDC_NRF52X + bool + help + Enable nRF52 series System on Chip DC/DC converter. + +config SOC_DCDC_NRF52X_HV + bool + depends on SOC_NRF52840_QIAA + help + Enable nRF52 series System on Chip High Voltage DC/DC converter. + +config GPIO_AS_PINRESET + bool "[DEPRECATED] GPIO as pin reset (reset button)" + select DEPRECATED + help + This option is deprecated, use devicetree instead. Example + configuration: + + &uicr { + gpio-as-nreset; + }; + +config NRF_ENABLE_ICACHE + bool "The instruction cache (I-Cache)" + depends on SOC_NRF52832 || SOC_NRF52833 || SOC_NRF52840 + default y + +config NRF52_ANOMALY_132_DELAY_US + int "Anomaly 132 workaround delay (microseconds)" + default 330 + range 0 330 + depends on NRF52_ANOMALY_132_WORKAROUND + help + Due to Anomaly 132 LF RC source may not start if restarted in certain + window after stopping (230 us to 330 us). Software reset also stops the + clock so if clock is initiated in certain window, the clock may also fail + to start at reboot. A delay is added before starting LF clock to ensure + that anomaly conditions are not met. Delay should be long enough to ensure + that clock is started later than 330 us after reset. If crystal oscillator + (XO) is used then low frequency clock initially starts with RC and then + seamlessly switches to XO which has much longer startup time thus, + depending on application, workaround may also need to be applied. + Additional drivers initialization increases initialization time and delay + may be shortened. Workaround is disabled by setting delay to 0. + +config NRF52_ANOMALY_198_WORKAROUND + bool "Anomaly 198 workaround" + default y + depends on SOC_NRF52840 + depends on NRFX_SPIM3 + help + This anomaly applies to IC revisions "Engineering B" up to "3", the most + recent one. + +config NRF52_ANOMALY_109_WORKAROUND + bool "Anomaly 109 workaround" + default y + depends on SOC_NRF52832 + depends on NRFX_SPIS || NRFX_SPIM || NRFX_TWIM || NRFX_PWM + help + Due to Anomaly 109 the first byte sent out by these peripherals is + sometimes wrong. This occurs when the system enters IDLE and stops the + 64MHz clock at the same time as the peripheral that is using DMA is started. + This anomaly applies to IC revisions up to "3", the most recent one. + +config NRF52_ANOMALY_109_WORKAROUND_EGU_INSTANCE + int "Anomaly 109 workaround EGU instance" + depends on NRF52_ANOMALY_109_WORKAROUND + range 0 5 + default 5 + help + EGU instance used by the nRF52 Anomaly 109 workaround for PWM. + +endif # SOC_SERIES_NRF52X diff --git a/soc/nordic/nrf52/Kconfig.defconfig b/soc/nordic/nrf52/Kconfig.defconfig new file mode 100644 index 00000000000..eed012878e2 --- /dev/null +++ b/soc/nordic/nrf52/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF52 MCU line + +# Copyright (c) 2016-2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF52X + +rsource "Kconfig.defconfig.nrf52*" + +# If the kernel has timer support, enable the timer +config NRF_RTC_TIMER + default y if SYS_CLOCK_EXISTS + +endif # SOC_SERIES_NRF52X diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52805_CAAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52805_CAAA similarity index 84% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52805_CAAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52805_CAAA index 25bf9b4e68f..684276ebb54 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52805_CAAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52805_CAAA @@ -5,9 +5,6 @@ if SOC_NRF52805_CAAA -config SOC - default "nRF52805_CAAA" - config NUM_IRQS default 26 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52810_QFAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52810_QFAA similarity index 84% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52810_QFAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52810_QFAA index 1b5a7b5c314..7f87637b92f 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52810_QFAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52810_QFAA @@ -5,9 +5,6 @@ if SOC_NRF52810_QFAA -config SOC - default "nRF52810_QFAA" - config NUM_IRQS default 30 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52811_QFAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52811_QFAA similarity index 84% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52811_QFAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52811_QFAA index 7b291305208..bc4c757e6f8 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52811_QFAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52811_QFAA @@ -5,9 +5,6 @@ if SOC_NRF52811_QFAA -config SOC - default "nRF52811_QFAA" - config NUM_IRQS default 30 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52820_QDAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52820_QDAA similarity index 81% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52820_QDAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52820_QDAA index 4aa761b93be..2db0291afad 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52820_QDAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52820_QDAA @@ -5,10 +5,6 @@ if SOC_NRF52820_QDAA -config SOC - string - default "nRF52820_QDAA" - config NUM_IRQS int default 40 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_CIAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_CIAA similarity index 87% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_CIAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52832_CIAA index 4060453badc..4f9101f4c61 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_CIAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_CIAA @@ -5,9 +5,6 @@ if SOC_NRF52832_CIAA -config SOC - default "nRF52832_CIAA" - config NUM_IRQS default 39 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAA similarity index 87% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAA index cc48aaeaccb..b579b1e3ed0 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAA @@ -5,9 +5,6 @@ if SOC_NRF52832_QFAA -config SOC - default "nRF52832_QFAA" - config NUM_IRQS default 39 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAB b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAB similarity index 87% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAB rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAB index 2b9491cae3b..1c494d222c9 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAB +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAB @@ -5,9 +5,6 @@ if SOC_NRF52832_QFAB -config SOC - default "nRF52832_QFAB" - config NUM_IRQS default 39 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QDAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QDAA similarity index 81% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QDAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QDAA index 237bee5813a..055544288e4 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QDAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QDAA @@ -5,10 +5,6 @@ if SOC_NRF52833_QDAA -config SOC - string - default "nRF52833_QDAA" - config NUM_IRQS int default 48 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QIAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QIAA similarity index 81% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QIAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QIAA index 6256b30e741..add0c89503b 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QIAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QIAA @@ -5,10 +5,6 @@ if SOC_NRF52833_QIAA -config SOC - string - default "nRF52833_QIAA" - config NUM_IRQS int default 48 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QFAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QFAA similarity index 84% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QFAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QFAA index 451fea911b4..877e553cd23 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QFAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QFAA @@ -5,9 +5,6 @@ if SOC_NRF52840_QFAA -config SOC - default "nRF52840_QFAA" - config NUM_IRQS default 48 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QIAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QIAA similarity index 84% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QIAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QIAA index 62ca5e76cbd..a2ac50ca5dd 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QIAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QIAA @@ -5,9 +5,6 @@ if SOC_NRF52840_QIAA -config SOC - default "nRF52840_QIAA" - config NUM_IRQS default 48 diff --git a/soc/nordic/nrf52/Kconfig.soc b/soc/nordic/nrf52/Kconfig.soc new file mode 100644 index 00000000000..24a5249205d --- /dev/null +++ b/soc/nordic/nrf52/Kconfig.soc @@ -0,0 +1,90 @@ +# Nordic Semiconductor nRF52 MCU line, Zephyr hw model v2 compliant + +# Copyright (c) 2022-2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF52X + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF52 MCU series + +config SOC_NRF52805 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52810 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52811 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52820 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52832 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52833 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52840 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52805_CAAA + bool + select SOC_NRF52805 + +config SOC_NRF52810_QFAA + bool + select SOC_NRF52810 + +config SOC_NRF52811_QFAA + bool + select SOC_NRF52811 + +config SOC_NRF52820_QDAA + bool + select SOC_NRF52820 + +config SOC_NRF52832_CIAA + bool + select SOC_NRF52832 + +config SOC_NRF52832_QFAA + bool + select SOC_NRF52832 + +config SOC_NRF52832_QFAB + bool + select SOC_NRF52832 + +config SOC_NRF52833_QDAA + bool + select SOC_NRF52833 + +config SOC_NRF52833_QIAA + bool + select SOC_NRF52833 + +config SOC_NRF52840_QFAA + bool + select SOC_NRF52840 + +config SOC_NRF52840_QIAA + bool + select SOC_NRF52840 + +config SOC + default "nrf52805" if SOC_NRF52805_CAAA + default "nrf52810" if SOC_NRF52810_QFAA + default "nrf52811" if SOC_NRF52811_QFAA + default "nrf52820" if SOC_NRF52820_QDAA + default "nrf52832" if SOC_NRF52832_CIAA || SOC_NRF52832_QFAA || SOC_NRF52832_QFAB + default "nrf52833" if SOC_NRF52833_QDAA || SOC_NRF52833_QIAA + default "nrf52840" if SOC_NRF52840_QFAA || SOC_NRF52840_QIAA diff --git a/soc/arm/nordic_nrf/nrf52/soc.c b/soc/nordic/nrf52/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf52/soc.c rename to soc/nordic/nrf52/soc.c diff --git a/soc/arm/nordic_nrf/nrf52/soc.h b/soc/nordic/nrf52/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf52/soc.h rename to soc/nordic/nrf52/soc.h diff --git a/soc/nordic/nrf53/CMakeLists.txt b/soc/nordic/nrf53/CMakeLists.txt new file mode 100644 index 00000000000..0e8b1e69a29 --- /dev/null +++ b/soc/nordic/nrf53/CMakeLists.txt @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources(soc.c) +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC sync_rtc.c) + +if (CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED AND + NOT CONFIG_SYS_CLOCK_EXISTS) + message(WARNING " + Your application may be affected by the anomaly 160 that concerns the + nRF5340 SoC. The related workaround cannot be applied, because your + application has the system clock disabled (CONFIG_SYS_CLOCK_EXISTS=n). + Consider enabling the system clock to apply the workaround. + " " + At your own risk, you can suppress this warning by setting + CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED=n.") +endif() diff --git a/soc/nordic/nrf53/Kconfig b/soc/nordic/nrf53/Kconfig new file mode 100644 index 00000000000..7ef9546058d --- /dev/null +++ b/soc/nordic/nrf53/Kconfig @@ -0,0 +1,227 @@ +# Nordic Semiconductor nRF53 MCU line + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF53X + bool + select ARM + select SOC_COMPATIBLE_NRF53X + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + imply XIP + select HAS_NRFX + select HAS_NORDIC_DRIVERS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_SWO + help + Enable support for NRF53 MCU series + +config SOC_NRF5340_CPUAPP + select CPU_HAS_NRF_IDAU + select CPU_HAS_FPU + select ARMV8_M_DSP + select HAS_POWEROFF + select SOC_COMPATIBLE_NRF5340_CPUAPP + imply SOC_NRF53_RTC_PRETICK + imply SOC_NRF53_ANOMALY_168_WORKAROUND + +config SOC_NRF5340_CPUNET + select ARM_ON_EXIT_CPU_IDLE + select SOC_COMPATIBLE_NRF5340_CPUNET + imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED + imply SOC_NRF53_RTC_PRETICK if !WDT_NRFX + imply SOC_NRF53_ANOMALY_168_WORKAROUND + +if SOC_SERIES_NRF53X + +config SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED + bool "Workaround for nRF5340 anomaly 160" + imply SOC_NRF53_ANOMALY_160_WORKAROUND + help + Indicates that the workaround for the anomaly 160 that affects + the nRF5340 SoC should be applied. + This option is enabled by default for the Application MCU when + DC/DC mode is enabled for the VREGMAIN or VREGRADIO regulator + and always for the Network MCU. + If this option is enabled, but the workaround cannot be applied, + because the system clock is disabled, a related cmake warning is + issued. + +config SOC_NRF53_ANOMALY_160_WORKAROUND + bool + depends on SYS_CLOCK_EXISTS + select ARM_ON_ENTER_CPU_IDLE_HOOK + +config SOC_NRF53_ANOMALY_168_WORKAROUND + bool "Workaround for nRF5340 anomaly 168" + select ARM_ON_EXIT_CPU_IDLE + help + Indicates that the workaround for the anomaly 168 that affects + the nRF5340 SoC should be applied. + The workaround involves execution of 8 NOP instructions when the CPU + exist its idle state (when the WFI/WFE instruction returns) and it is + enabled by default for both the application and network core. + +config SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM + bool "Extend the workaround to execution at 128 MHz from RAM" + depends on SOC_NRF53_ANOMALY_168_WORKAROUND && SOC_NRF5340_CPUAPP + help + Indicates that the anomaly 168 workaround is to be extended to cover + also a specific case when the WFI/WFE instruction is executed at 128 + MHz from RAM. Then, 26 instead of 8 NOP instructions needs to be + executed after WFI/WFE. This extension is not enabled by default. + +config SOC_NRF53_RTC_PRETICK + bool "Pre-tick workaround for nRF5340 anomaly 165" + depends on (SYS_CLOCK_EXISTS && SOC_NRF5340_CPUNET) || SOC_NRF5340_CPUAPP + select NRFX_DPPI + select ARM_ON_ENTER_CPU_IDLE_HOOK if SOC_NRF5340_CPUNET + select ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK if SOC_NRF5340_CPUNET + help + Indicates that the pre-tick workaround for the anomaly 165 that affects + the nRF5340 SoC should be applied. The workaround applies to wake ups caused + by EVENTS_COMPARE and EVENTS_OVRFLW on RTC0 and RTC1 for which interrupts are + enabled through INTENSET register. The case when these events are generated + by EVTEN but without interrupts enabled through INTENSET is not handled. + The EVENTS_TICK event is not handled. + +if SOC_NRF53_RTC_PRETICK + +config SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET + int "IPC 0 channel for RTC pretick" + range 0 15 + default 10 + +config SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET + int "IPC 1 channel for RTC pretick" + range 0 15 + default 11 + +endif + +if SOC_NRF5340_CPUAPP + +config SOC_DCDC_NRF53X_APP + bool + imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED + help + Enable nRF53 series System on Chip Application MCU DC/DC converter. + +config SOC_DCDC_NRF53X_NET + bool + imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED + help + Enable nRF53 series System on Chip Network MCU DC/DC converter. + +config SOC_DCDC_NRF53X_HV + bool + help + Enable nRF53 series System on Chip High Voltage DC/DC converter. + +config NRF_SPU_FLASH_REGION_SIZE + hex + default 0x4000 + help + FLASH region size for the NRF_SPU peripheral + +config NRF_SPU_RAM_REGION_SIZE + hex + default 0x2000 + help + RAM region size for the NRF_SPU peripheral + +config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 + bool + depends on NRF_SOC_SECURE_SUPPORTED + help + hidden option for including the nRF GPIO pin forwarding + +if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM + +config SOC_ENABLE_LFXO + bool "LFXO" + default y + help + Enable the low-frequency oscillator (LFXO) functionality on XL1 and + XL2 pins. + This option must be enabled if either application or network core is + to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular + GPIOs. + +choice SOC_LFXO_LOAD_CAPACITANCE + prompt "LFXO load capacitance" + depends on SOC_ENABLE_LFXO + default SOC_LFXO_CAP_INT_7PF + +config SOC_LFXO_CAP_EXTERNAL + bool "Use external load capacitors" + +config SOC_LFXO_CAP_INT_6PF + bool "6 pF internal load capacitance" + +config SOC_LFXO_CAP_INT_7PF + bool "7 pF internal load capacitance" + +config SOC_LFXO_CAP_INT_9PF + bool "9 pF internal load capacitance" + +endchoice + +choice SOC_HFXO_LOAD_CAPACITANCE + prompt "HFXO load capacitance" + default SOC_HFXO_CAP_DEFAULT + +config SOC_HFXO_CAP_DEFAULT + bool "SoC default" + help + When this option is used, the SoC initialization routine does not + touch the XOSC32MCAPS register value, so the default setting for + the SoC is in effect. Please note that this may not necessarily be + the reset value (0) for the register, as the register can be set + during the device trimming in the SystemInit() function. + +config SOC_HFXO_CAP_EXTERNAL + bool "Use external load capacitors" + +config SOC_HFXO_CAP_INTERNAL + bool "Use internal load capacitors" + depends on NRF_SOC_SECURE_SUPPORTED + +endchoice + +config SOC_HFXO_CAP_INT_VALUE_X2 + int "Doubled value of HFXO internal load capacitors (in pF)" + depends on SOC_HFXO_CAP_INTERNAL + range 14 40 + help + Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps + can be enabled on pins XC1 and XC2. This option specifies doubled + capacitance value for the two capacitors. Set it to 14 to get 7.0 pF + for each capacitor, 15 to get 7.5 pF, and so on. + +endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM + +endif # SOC_NRF5340_CPUAPP + + +config NRF_ENABLE_CACHE + bool "Cache" + depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \ + || SOC_NRF5340_CPUNET + default y + help + Instruction and Data cache is available on nRF5340 CPUAPP + (Application MCU). It may only be accessed by Secure code. + + Instruction cache only (I-Cache) is available in nRF5340 + CPUNET (Network MCU). + +config BUILD_WITH_TFM + # TF-M nRF53 platform enables the cache unconditionally. + select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP + +rsource "Kconfig.sync_rtc" + +endif # SOC_SERIES_NRF53X diff --git a/soc/nordic/nrf53/Kconfig.defconfig b/soc/nordic/nrf53/Kconfig.defconfig new file mode 100644 index 00000000000..d41e2e57f58 --- /dev/null +++ b/soc/nordic/nrf53/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF53 MCU line + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF53X + +rsource "Kconfig.defconfig.nrf53*" + +# If the kernel has timer support, enable the timer +config NRF_RTC_TIMER + default y if SYS_CLOCK_EXISTS + +endif # SOC_SERIES_NRF53X diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA b/soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA similarity index 91% rename from soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA rename to soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA index f0f7f5a7d84..ab74bd6a9fb 100644 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA +++ b/soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA @@ -5,9 +5,6 @@ if SOC_NRF5340_CPUAPP_QKAA -config SOC - default "nRF5340_CPUAPP_QKAA" - config NUM_IRQS default 69 diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA b/soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA similarity index 90% rename from soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA rename to soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA index 0c60adc04f3..41961784daf 100644 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA +++ b/soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA @@ -5,9 +5,6 @@ if SOC_NRF5340_CPUNET_QKAA -config SOC - default "nRF5340_CPUNET_QKAA" - config NUM_IRQS default 30 diff --git a/soc/nordic/nrf53/Kconfig.soc b/soc/nordic/nrf53/Kconfig.soc new file mode 100644 index 00000000000..ff32aabf7fe --- /dev/null +++ b/soc/nordic/nrf53/Kconfig.soc @@ -0,0 +1,29 @@ +# Nordic Semiconductor nRF52 MCU line, Zephyr hw model v2 compliant + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF53X + bool + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF53 MCU series + +config SOC_NRF5340_CPUAPP + bool + select SOC_SERIES_NRF53X + +config SOC_NRF5340_CPUNET + bool + select SOC_SERIES_NRF53X + +config SOC_NRF5340_CPUAPP_QKAA + bool + select SOC_NRF5340_CPUAPP + +config SOC_NRF5340_CPUNET_QKAA + bool + select SOC_NRF5340_CPUNET + +config SOC + default "nrf5340" if SOC_NRF5340_CPUAPP_QKAA || SOC_NRF5340_CPUNET_QKAA diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.sync_rtc b/soc/nordic/nrf53/Kconfig.sync_rtc similarity index 100% rename from soc/arm/nordic_nrf/nrf53/Kconfig.sync_rtc rename to soc/nordic/nrf53/Kconfig.sync_rtc diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.sync_rtc_ipm b/soc/nordic/nrf53/Kconfig.sync_rtc_ipm similarity index 100% rename from soc/arm/nordic_nrf/nrf53/Kconfig.sync_rtc_ipm rename to soc/nordic/nrf53/Kconfig.sync_rtc_ipm diff --git a/soc/arm/nordic_nrf/nrf53/soc.c b/soc/nordic/nrf53/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf53/soc.c rename to soc/nordic/nrf53/soc.c diff --git a/soc/arm/nordic_nrf/nrf53/soc.h b/soc/nordic/nrf53/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf53/soc.h rename to soc/nordic/nrf53/soc.h diff --git a/soc/arm/nordic_nrf/nrf53/soc_cpu_idle.h b/soc/nordic/nrf53/soc_cpu_idle.h similarity index 100% rename from soc/arm/nordic_nrf/nrf53/soc_cpu_idle.h rename to soc/nordic/nrf53/soc_cpu_idle.h diff --git a/soc/arm/nordic_nrf/nrf53/sync_rtc.c b/soc/nordic/nrf53/sync_rtc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf53/sync_rtc.c rename to soc/nordic/nrf53/sync_rtc.c diff --git a/soc/nordic/nrf54h/CMakeLists.txt b/soc/nordic/nrf54h/CMakeLists.txt new file mode 100644 index 00000000000..67a6dab6f8a --- /dev/null +++ b/soc/nordic/nrf54h/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF54H20_ENGA_CPUAPP OR CONFIG_SOC_NRF54H20_ENGA_CPURAD) + zephyr_include_directories(.) + zephyr_library_sources(soc.c) +endif() + +# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes +# for the image correctly +zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld) diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig new file mode 100644 index 00000000000..d9d5b0789f9 --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig @@ -0,0 +1,41 @@ +# Nordic Semiconductor nRF54H MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF54HX + select HAS_NRFX + select HAS_NORDIC_DRIVERS + +config SOC_NRF54H20_ENGA_CPUAPP + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_FPU + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +config SOC_NRF54H20_ENGA_CPURAD + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_FPU + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +config SOC_NRF54H20_ENGA_CPUPPR + depends on RISCV_CORE_NORDIC_VPR + +if SOC_NRF54H20 + +config NRF_ENABLE_ICACHE + bool "Instruction cache (I-Cache)" + default y + +endif # SOC_NRF54H20 diff --git a/soc/nordic/nrf54h/Kconfig.defconfig b/soc/nordic/nrf54h/Kconfig.defconfig new file mode 100644 index 00000000000..72ba234e883 --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Nordic Semiconductor nRF54H MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF54HX + +rsource "Kconfig.defconfig.nrf54h*" + +if ARM + +config CACHE_NRF_CACHE + default y if EXTERNAL_CACHE + +endif # ARM + +if RISCV + +DT_CHOSEN_Z_SRAM = zephyr,sram +DT_CHOSEN_Z_CODE = zephyr,code-partition + +config BUILD_OUTPUT_ADJUST_LMA + depends on !XIP + default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_Z_CODE)) - \ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))" + +config BUILD_OUTPUT_HEX + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 if NRF_GRTC_TIMER + default 32768 if NRF_RTC_TIMER + +endif # RISCV + +endif # SOC_SERIES_NRF54HX diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp new file mode 100644 index 00000000000..af261c3e0a3 --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF54H20 Application MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF54H20_ENGA_CPUAPP + +config NUM_IRQS + default 471 + +config NRF_REGTOOL_GENERATE_UICR + default y + +endif # SOC_NRF54H20_ENGA_CPUAPP diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr similarity index 83% rename from soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr rename to soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr index a36d24c72ae..3d48375b97d 100644 --- a/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr @@ -3,9 +3,6 @@ if SOC_NRF54H20_ENGA_CPUPPR -config SOC - default "nrf54h20_enga_cpuppr" - config NUM_IRQS default 496 diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad new file mode 100644 index 00000000000..e83eea71b48 --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF54H20 Radio MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF54H20_ENGA_CPURAD + +config NUM_IRQS + default 471 + +config NRF_REGTOOL_GENERATE_UICR + default y + +endif # SOC_NRF54H20_ENGA_CPURAD diff --git a/soc/nordic/nrf54h/Kconfig.soc b/soc/nordic/nrf54h/Kconfig.soc new file mode 100644 index 00000000000..7ea87db22a4 --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig.soc @@ -0,0 +1,31 @@ +# Nordic Semiconductor nRF54H MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NRF54H20 + bool + select SOC_SERIES_NRF54HX + help + nRF54H20 + +config SOC_NRF54H20_ENGA_CPUAPP + bool + select SOC_NRF54H20 + help + nRF54H20 ENGA CPUAPP + +config SOC_NRF54H20_ENGA_CPURAD + bool + select SOC_NRF54H20 + help + nRF54H20 ENGA CPURAD + +config SOC_NRF54H20_ENGA_CPUPPR + bool + select SOC_NRF54H20 + help + nRF54H20 ENGA CPUPPR + +config SOC + default "nrf54h20" if SOC_NRF54H20 diff --git a/soc/arm/nordic_nrf/nrf54h/align.ld b/soc/nordic/nrf54h/align.ld similarity index 100% rename from soc/arm/nordic_nrf/nrf54h/align.ld rename to soc/nordic/nrf54h/align.ld diff --git a/soc/arm/nordic_nrf/nrf54h/soc.c b/soc/nordic/nrf54h/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf54h/soc.c rename to soc/nordic/nrf54h/soc.c diff --git a/soc/arm/nordic_nrf/nrf54h/soc.h b/soc/nordic/nrf54h/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf54h/soc.h rename to soc/nordic/nrf54h/soc.h diff --git a/soc/nordic/nrf54l/CMakeLists.txt b/soc/nordic/nrf54l/CMakeLists.txt new file mode 100644 index 00000000000..f1c18291fc6 --- /dev/null +++ b/soc/nordic/nrf54l/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources( + soc.c + ../validate_rram_partitions.c + ) +zephyr_include_directories(.) + +if(CONFIG_ELV_GRTC_LFXO_ALLOWED) + message(WARNING "WARNING! ELV mode feature is EXPERIMENTAL and may brick your device!") +endif() diff --git a/soc/nordic/nrf54l/Kconfig b/soc/nordic/nrf54l/Kconfig new file mode 100644 index 00000000000..6841e1478f7 --- /dev/null +++ b/soc/nordic/nrf54l/Kconfig @@ -0,0 +1,66 @@ +# Nordic Semiconductor nRF54 MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF54LX + select HAS_NRFX + select HAS_NORDIC_DRIVERS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +config SOC_NRF54L15_ENGA_CPUAPP + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ICACHE + select CPU_HAS_ARM_SAU + select CPU_HAS_FPU + select HAS_HW_NRF_RADIO_IEEE802154 + select HAS_POWEROFF + +if SOC_SERIES_NRF54LX + +config SOC_NRF54LX_SKIP_CLOCK_CONFIG + bool "Skip clock frequency configuration in system initialization" + help + With this option, the CPU clock frequency is not set during system initialization. + The CPU runs with the default, hardware-selected frequency. + +config SOC_NRF_FORCE_CONSTLAT + bool "Force constant-latency mode" + help + In constant latency mode the CPU wakeup latency and the PPI task response + will be constant and kept at a minimum. This is secured by forcing a set + of base resources on while in sleep. The advantage of having a constant + and predictable latency will be at the cost of having increased power consumption. + +config SOC_NRF54L_VREG_MAIN_DCDC + bool "NRF54L DC/DC converter." + help + To enable, an inductor must be connected to the DC/DC converter pin. + +config SOC_NRF54L_NORMAL_VOLTAGE_MODE + bool "NRF54L Normal Voltage Mode." + +config SOC_NRF54L_GLITCHDET_WORKAROUND + bool "Workaround that disables glitch detector" + default y + help + Temporary workaround - disabling glitch detector to limit power consumption. + +if NRF_GRTC_TIMER + +config ELV_GRTC_LFXO_ALLOWED + bool + depends on NRF_GRTC_SLEEP_ALLOWED + select EXPERIMENTAL + help + This feature allows using ELV mode when GRTC operates with the LFXO as + a low-frequency clock source. The LFXO is automatically activated when + preparing to system-off. + WARNING! This feature is EXPERIMENTAL and may brick your device! + +endif # NRF_GRTC_TIMER + +endif # SOC_SERIES_NRF54LX diff --git a/soc/nordic/nrf54l/Kconfig.defconfig b/soc/nordic/nrf54l/Kconfig.defconfig new file mode 100644 index 00000000000..39ed9025ea0 --- /dev/null +++ b/soc/nordic/nrf54l/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Nordic Semiconductor nRF54L MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF54LX + +rsource "Kconfig.defconfig.nrf54l*" + +config CORTEX_M_SYSTICK + default !NRF_GRTC_TIMER + +config CACHE_NRF_CACHE + default y if EXTERNAL_CACHE + +endif # SOC_SERIES_NRF54LX diff --git a/soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp b/soc/nordic/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp similarity index 84% rename from soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp rename to soc/nordic/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp index d19df604c02..80957abfdd7 100644 --- a/soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp +++ b/soc/nordic/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp @@ -5,10 +5,6 @@ if SOC_NRF54L15_ENGA_CPUAPP -config SOC - string - default "nrf54l15_cpuapp" - config NUM_IRQS default 271 diff --git a/soc/nordic/nrf54l/Kconfig.soc b/soc/nordic/nrf54l/Kconfig.soc new file mode 100644 index 00000000000..05ce9db0a3e --- /dev/null +++ b/soc/nordic/nrf54l/Kconfig.soc @@ -0,0 +1,25 @@ +# Nordic Semiconductor nRF54L MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NRF54L15 + bool + select SOC_SERIES_NRF54LX + help + NRF54L15 + +config SOC_NRF54L15_ENGA + bool + select SOC_NRF54L15 + help + NRF54L15 ENGA + +config SOC_NRF54L15_ENGA_CPUAPP + bool + select SOC_NRF54L15_ENGA + help + NRF54L15 ENGA CPUAPP + +config SOC + default "nrf54l15" if SOC_NRF54L15 diff --git a/soc/arm/nordic_nrf/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf54l/soc.c rename to soc/nordic/nrf54l/soc.c diff --git a/soc/arm/nordic_nrf/nrf54l/soc.h b/soc/nordic/nrf54l/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf54l/soc.h rename to soc/nordic/nrf54l/soc.h diff --git a/soc/nordic/nrf91/CMakeLists.txt b/soc/nordic/nrf91/CMakeLists.txt new file mode 100644 index 00000000000..53398751982 --- /dev/null +++ b/soc/nordic/nrf91/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources(soc.c) +zephyr_include_directories(.) diff --git a/soc/nordic/nrf91/Kconfig b/soc/nordic/nrf91/Kconfig new file mode 100644 index 00000000000..ed38eff73a2 --- /dev/null +++ b/soc/nordic/nrf91/Kconfig @@ -0,0 +1,37 @@ +# Nordic Semiconductor nRF91 MCU line + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF91X + select ARM + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_NRF_IDAU + select CPU_HAS_FPU + select ARMV8_M_DSP + imply XIP + select HAS_NRFX + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_POWEROFF + +if SOC_SERIES_NRF91X + +config NRF_SPU_FLASH_REGION_SIZE + hex + default 0x8000 + help + FLASH region size for the NRF_SPU peripheral + +config NRF_SPU_RAM_REGION_SIZE + hex + default 0x2000 + help + RAM region size for the NRF_SPU peripheral + +config NRF_ENABLE_ICACHE + bool "Instruction cache (I-Cache)" + default y + +endif # SOC_SERIES_NRF91X diff --git a/soc/nordic/nrf91/Kconfig.defconfig b/soc/nordic/nrf91/Kconfig.defconfig new file mode 100644 index 00000000000..e28213fc873 --- /dev/null +++ b/soc/nordic/nrf91/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF91 MCU line + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF91X + +rsource "Kconfig.defconfig.nrf91*" + +# If the kernel has timer support, enable the timer +config NRF_RTC_TIMER + default y if SYS_CLOCK_EXISTS + +endif # SOC_SERIES_NRF91X diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9131_LACA b/soc/nordic/nrf91/Kconfig.defconfig.nrf9131_LACA similarity index 84% rename from soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9131_LACA rename to soc/nordic/nrf91/Kconfig.defconfig.nrf9131_LACA index c5004045935..b34a8d2384b 100644 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9131_LACA +++ b/soc/nordic/nrf91/Kconfig.defconfig.nrf9131_LACA @@ -5,9 +5,6 @@ if SOC_NRF9131_LACA -config SOC - default "nRF9131_LACA" - config NUM_IRQS default 65 diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9151_LACA b/soc/nordic/nrf91/Kconfig.defconfig.nrf9151_LACA similarity index 84% rename from soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9151_LACA rename to soc/nordic/nrf91/Kconfig.defconfig.nrf9151_LACA index 1b3ea88e359..f505e4154bf 100644 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9151_LACA +++ b/soc/nordic/nrf91/Kconfig.defconfig.nrf9151_LACA @@ -5,9 +5,6 @@ if SOC_NRF9151_LACA -config SOC - default "nRF9151_LACA" - config NUM_IRQS default 65 diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9160_SICA b/soc/nordic/nrf91/Kconfig.defconfig.nrf9160_SICA similarity index 84% rename from soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9160_SICA rename to soc/nordic/nrf91/Kconfig.defconfig.nrf9160_SICA index e8440846d2e..5970464a6bd 100644 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9160_SICA +++ b/soc/nordic/nrf91/Kconfig.defconfig.nrf9160_SICA @@ -5,9 +5,6 @@ if SOC_NRF9160_SICA -config SOC - default "nRF9160_SICA" - config NUM_IRQS default 65 diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9161_LACA b/soc/nordic/nrf91/Kconfig.defconfig.nrf9161_LACA similarity index 84% rename from soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9161_LACA rename to soc/nordic/nrf91/Kconfig.defconfig.nrf9161_LACA index 3358e961203..1a4d4b863b2 100644 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9161_LACA +++ b/soc/nordic/nrf91/Kconfig.defconfig.nrf9161_LACA @@ -5,9 +5,6 @@ if SOC_NRF9161_LACA -config SOC - default "nRF9161_LACA" - config NUM_IRQS default 65 diff --git a/soc/nordic/nrf91/Kconfig.soc b/soc/nordic/nrf91/Kconfig.soc new file mode 100644 index 00000000000..452c353a109 --- /dev/null +++ b/soc/nordic/nrf91/Kconfig.soc @@ -0,0 +1,47 @@ +# Nordic Semiconductor nRF91 MCU line + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF91X + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF91 MCU series + +config SOC_NRF9120 + bool + select SOC_SERIES_NRF91X + +config SOC_NRF9131_LACA + bool + select SOC_NRF9120 + +config SOC_NRF9151_LACA + bool + select SOC_NRF9120 + +config SOC_NRF9160 + bool + select SOC_SERIES_NRF91X + +config SOC_NRF9160_SICA + bool + select SOC_NRF9160 + +# The nRF9161 is technically a SiP (System-in-Package) that consists of +# the nRF9120 SoC and additional components like PMIC, FEM, and XTAL, +# so for nrfx/MDK the nRF9120 SoC is to be indicated as the build target, +# but since the nRF9161 is what a user can actually see on a board, using +# only nRF9120 in the Zephyr build infrastructure might be confusing. +# That's why in the top level of SoC definitions (for user-configurable +# options in Kconfig, for example) the nRF9161 term is used and nRF9120 +# underneath. +config SOC_NRF9161_LACA + bool + select SOC_NRF9120 + +config SOC + default "nrf9131" if SOC_NRF9131_LACA + default "nrf9151" if SOC_NRF9151_LACA + default "nrf9160" if SOC_NRF9160_SICA + default "nrf9161" if SOC_NRF9161_LACA diff --git a/soc/arm/nordic_nrf/nrf91/soc.c b/soc/nordic/nrf91/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf91/soc.c rename to soc/nordic/nrf91/soc.c diff --git a/soc/arm/nordic_nrf/nrf91/soc.h b/soc/nordic/nrf91/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf91/soc.h rename to soc/nordic/nrf91/soc.h diff --git a/soc/nordic/soc.yml b/soc/nordic/soc.yml new file mode 100644 index 00000000000..87f35a46558 --- /dev/null +++ b/soc/nordic/soc.yml @@ -0,0 +1,39 @@ +family: +- name: nordic_nrf + series: + - name: nrf51 + socs: + - name: nrf51822 + - name: nrf52 + socs: + - name: nrf52805 + - name: nrf52810 + - name: nrf52811 + - name: nrf52820 + - name: nrf52832 + - name: nrf52833 + - name: nrf52840 + - name: nrf53 + socs: + - name: nrf5340 + cpuclusters: + - name: cpuapp + - name: cpunet + - name: nrf54l + socs: + - name: nrf54l15 + cpuclusters: + - name: cpuapp + - name: nrf54h + socs: + - name: nrf54h20 + cpuclusters: + - name: cpuapp + - name: cpurad + - name: cpuppr + - name: nrf91 + socs: + - name: nrf9131 + - name: nrf9151 + - name: nrf9160 + - name: nrf9161 diff --git a/soc/arm/nordic_nrf/timing.c b/soc/nordic/timing.c similarity index 100% rename from soc/arm/nordic_nrf/timing.c rename to soc/nordic/timing.c diff --git a/soc/arm/nordic_nrf/validate_base_addresses.c b/soc/nordic/validate_base_addresses.c similarity index 99% rename from soc/arm/nordic_nrf/validate_base_addresses.c rename to soc/nordic/validate_base_addresses.c index 28ec231b132..79083d630dd 100644 --- a/soc/arm/nordic_nrf/validate_base_addresses.c +++ b/soc/nordic/validate_base_addresses.c @@ -5,9 +5,10 @@ */ #include -#include #include +#include + /* * Account for MDK inconsistencies */ diff --git a/soc/arm/nordic_nrf/validate_enabled_instances.c b/soc/nordic/validate_enabled_instances.c similarity index 100% rename from soc/arm/nordic_nrf/validate_enabled_instances.c rename to soc/nordic/validate_enabled_instances.c diff --git a/soc/arm/nordic_nrf/validate_rram_partitions.c b/soc/nordic/validate_rram_partitions.c similarity index 100% rename from soc/arm/nordic_nrf/validate_rram_partitions.c rename to soc/nordic/validate_rram_partitions.c diff --git a/soc/arm/nuvoton_npcx/CMakeLists.txt b/soc/nuvoton/npcx/CMakeLists.txt similarity index 100% rename from soc/arm/nuvoton_npcx/CMakeLists.txt rename to soc/nuvoton/npcx/CMakeLists.txt diff --git a/soc/nuvoton/npcx/Kconfig b/soc/nuvoton/npcx/Kconfig new file mode 100644 index 00000000000..bb3e92738bc --- /dev/null +++ b/soc/nuvoton/npcx/Kconfig @@ -0,0 +1,189 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NPCX + +menuconfig NPCX_HEADER + bool "The output binary with NPCX binary header" + help + On NPCX series chip, the NPCX ROM code loads firmware image from flash + to RAM by the firmware binary header setting. Enable this to invoke + the 'ecst' which generates the NPCX firmware header. + +if NPCX_HEADER + +config NPCX_IMAGE_OUTPUT_BIN + bool "Build npcx binary in BIN format" + default y + help + Build a "raw" binary zephyr/zephyr.npcx.bin in the build directory. + The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. + +config NPCX_IMAGE_OUTPUT_HEX + bool "Build npcx binary in HEX format" + depends on NPCX_IMAGE_OUTPUT_BIN + help + Build an HEX binary zephyr/zephyr.npcx.hex in the build directory. + This is generated from the npcx BIN image. + The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. + +config NPCX_HEADER_CHIP + string + default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC + default "npcx7m7" if SOC_NPCX7M7FC + default "npcx9m3" if SOC_NPCX9M3F + default "npcx9m6" if SOC_NPCX9M6F + default "npcx9m7" if SOC_NPCX9M7F + default "npcx9mfp" if SOC_NPCX9MFP + default "npcx4m3" if SOC_NPCX4M3F + default "npcx4m8" if SOC_NPCX4M8F + +choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE + prompt "Clock rate to use for SPI flash" + default NPCX_HEADER_SPI_MAX_CLOCK_20 + help + This selects the max clock rate that will be used for loading firmware + binary from flash to RAM. + +config NPCX_HEADER_SPI_MAX_CLOCK_20 + bool "SPI flash max clock rate of 20 MHz" + +config NPCX_HEADER_SPI_MAX_CLOCK_25 + bool "SPI flash max clock rate of 25 MHz" + +config NPCX_HEADER_SPI_MAX_CLOCK_33 + bool "SPI flash max clock rate of 33 MHz" + depends on !SOC_SERIES_NPCX9 + +config NPCX_HEADER_SPI_MAX_CLOCK_40 + bool "SPI flash max clock rate of 40 MHz" + +config NPCX_HEADER_SPI_MAX_CLOCK_50 + bool "SPI flash max clock rate of 50 MHz" +endchoice + +config NPCX_HEADER_SPI_MAX_CLOCK + int + default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20 + default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25 + default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33 + default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40 + default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50 + +choice NPCX_HEADER_SPI_READ_MODE_CHOICE + prompt "Reading mode used by the SPI flash" + default NPCX_HEADER_SPI_READ_MODE_NORMAL + help + This sets the reading mode that can be used by the SPI flash. + Reading modes supported are normal, fast, dual, and quad. + +config NPCX_HEADER_SPI_READ_MODE_NORMAL + bool "SPI flash operates with normal reading mode" + +config NPCX_HEADER_SPI_READ_MODE_FAST + bool "SPI flash operates with fast reading mode" + +config NPCX_HEADER_SPI_READ_MODE_DUAL + bool "SPI flash operates with dual reading mode" + +config NPCX_HEADER_SPI_READ_MODE_QUAD + bool "SPI flash operates with quad reading mode" +endchoice + +config NPCX_HEADER_SPI_READ_MODE + string + default "normal" if NPCX_HEADER_SPI_READ_MODE_NORMAL + default "fast" if NPCX_HEADER_SPI_READ_MODE_FAST + default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL + default "quad" if NPCX_HEADER_SPI_READ_MODE_QUAD + +choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE + prompt "Core clock to SPI flash clock ratio" + default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 + help + This sets the clock ratio (core clock / SPI clock) + +config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 + bool "NPCX SPI clock ratio 1" + help + The SPI flash clock has the same frequency as the core clock. + +config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2 + bool "NPCX SPI clock ratio 2" + help + The core clock frequency is twice the flash clock frequency. +endchoice + +config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO + int + default 1 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 + default 2 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2 + +config NPCX_HEADER_ENABLE_HEADER_CRC + bool "Header crc check" + help + When enabled, the header will be verified at boot using a crc + checksum. + +config NPCX_HEADER_ENABLE_FIRMWARE_CRC + bool "Firmware image crc check" + help + When enabled, the firmware image will be verified at boot using a + crc checksum. + +choice NPCX_HEADER_FLASH_SIZE_CHOICE + prompt "Flash size" + default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \ + SOC_SERIES_NPCX9 + default NPCX_HEADER_FLASH_SIZE_16M + help + This sets the SPI flash size. + +config NPCX_HEADER_FLASH_SIZE_0P5M_1M + bool "SPI flash size 0.5M or 1M Bytes" + help + The SPI flash size is 0.5M or 1M Bytes. + +config NPCX_HEADER_FLASH_SIZE_2M + bool "SPI flash size 2M Bytes" + help + The SPI flash size is 2M Bytes. + +config NPCX_HEADER_FLASH_SIZE_4M + bool "SPI flash size 4M Bytes" + help + The SPI flash size is 4M Bytes. + +config NPCX_HEADER_FLASH_SIZE_8M + bool "SPI flash size 8M Bytes" + help + The SPI flash size is 8M Bytes. + +config NPCX_HEADER_FLASH_SIZE_16M + bool "SPI flash size 16M Bytes" + help + The SPI flash size is 16M Bytes. +endchoice + +config NPCX_HEADER_FLASH_SIZE + int + default 1 if NPCX_HEADER_FLASH_SIZE_0P5M_1M + default 2 if NPCX_HEADER_FLASH_SIZE_2M + default 4 if NPCX_HEADER_FLASH_SIZE_4M + default 8 if NPCX_HEADER_FLASH_SIZE_8M + default 16 if NPCX_HEADER_FLASH_SIZE_16M + +endif # NPCX_HEADER + +config NPCX_PM_TRACE + bool "Trace System Power Management in NPCX family" + depends on PM + help + Internal config to enable runtime power management traces. + +endif # SOC_FAMILY_NPCX + +# Select SoC Part No. and configuration options +rsource "*/Kconfig" diff --git a/soc/nuvoton/npcx/Kconfig.defconfig b/soc/nuvoton/npcx/Kconfig.defconfig new file mode 100644 index 00000000000..0c47d708313 --- /dev/null +++ b/soc/nuvoton/npcx/Kconfig.defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NPCX + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_NPCX diff --git a/soc/nuvoton/npcx/Kconfig.soc b/soc/nuvoton/npcx/Kconfig.soc new file mode 100644 index 00000000000..1c8002f8553 --- /dev/null +++ b/soc/nuvoton/npcx/Kconfig.soc @@ -0,0 +1,12 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NPCX + bool + +config SOC_FAMILY + default "nuvoton_npcx" if SOC_FAMILY_NPCX + +rsource "*/Kconfig.soc" diff --git a/soc/nuvoton/npcx/common/CMakeLists.txt b/soc/nuvoton/npcx/common/CMakeLists.txt new file mode 100644 index 00000000000..86780d1ad68 --- /dev/null +++ b/soc/nuvoton/npcx/common/CMakeLists.txt @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_sources_ifdef(CONFIG_PM power.c) +zephyr_sources( + scfg.c + registers.c +) + +# Check for disabling header CRC. +if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_HEADER_CRC) + set(NPCX_HEADER_HCRC "-nohcrc") +endif() + +# Check for disabling firmware CRC. +if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_FIRMWARE_CRC) + set(NPCX_HEADER_FCRC "-nofcrc") +endif() + +if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_BIN) + set(NPCX_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.bin) + string(TOUPPER "${SOC_NAME}" soc_name_upper) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${SOC_${soc_name_upper}_DIR}/common/ecst/ecst.py + -i ${KERNEL_BIN_NAME} + -o ${NPCX_BIN_NAME} + ${NPCX_HEADER_HCRC} ${NPCX_HEADER_FCRC} + -chip ${CONFIG_NPCX_HEADER_CHIP} + -flashsize ${CONFIG_NPCX_HEADER_FLASH_SIZE} + -spiclkratio ${CONFIG_NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO} + -spimaxclk ${CONFIG_NPCX_HEADER_SPI_MAX_CLOCK} + -spireadmode ${CONFIG_NPCX_HEADER_SPI_READ_MODE} + ) + if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_HEX) + set(NPCX_HEX_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.hex) + # Property magic which makes west flash choose right file. + set_property(TARGET runners_yaml_props_target PROPERTY hex_file "${CONFIG_KERNEL_BIN_NAME}.npcx.hex") + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND $ + $ + $binary + $ihex + $${NPCX_BIN_NAME} + $${NPCX_HEX_NAME} + $ + ) + endif() +endif() diff --git a/soc/arm/nuvoton_npcx/common/ecst/ecst.py b/soc/nuvoton/npcx/common/ecst/ecst.py similarity index 100% rename from soc/arm/nuvoton_npcx/common/ecst/ecst.py rename to soc/nuvoton/npcx/common/ecst/ecst.py diff --git a/soc/arm/nuvoton_npcx/common/ecst/ecst_args.py b/soc/nuvoton/npcx/common/ecst/ecst_args.py similarity index 100% rename from soc/arm/nuvoton_npcx/common/ecst/ecst_args.py rename to soc/nuvoton/npcx/common/ecst/ecst_args.py diff --git a/soc/arm/nuvoton_npcx/common/pinctrl_soc.h b/soc/nuvoton/npcx/common/pinctrl_soc.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/pinctrl_soc.h rename to soc/nuvoton/npcx/common/pinctrl_soc.h diff --git a/soc/arm/nuvoton_npcx/common/power.c b/soc/nuvoton/npcx/common/power.c similarity index 100% rename from soc/arm/nuvoton_npcx/common/power.c rename to soc/nuvoton/npcx/common/power.c diff --git a/soc/arm/nuvoton_npcx/common/reg/reg_access.h b/soc/nuvoton/npcx/common/reg/reg_access.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/reg/reg_access.h rename to soc/nuvoton/npcx/common/reg/reg_access.h diff --git a/soc/arm/nuvoton_npcx/common/reg/reg_def.h b/soc/nuvoton/npcx/common/reg/reg_def.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/reg/reg_def.h rename to soc/nuvoton/npcx/common/reg/reg_def.h diff --git a/soc/arm/nuvoton_npcx/common/registers.c b/soc/nuvoton/npcx/common/registers.c similarity index 100% rename from soc/arm/nuvoton_npcx/common/registers.c rename to soc/nuvoton/npcx/common/registers.c diff --git a/soc/arm/nuvoton_npcx/common/scfg.c b/soc/nuvoton/npcx/common/scfg.c similarity index 100% rename from soc/arm/nuvoton_npcx/common/scfg.c rename to soc/nuvoton/npcx/common/scfg.c diff --git a/soc/arm/nuvoton_npcx/common/soc_clock.h b/soc/nuvoton/npcx/common/soc_clock.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_clock.h rename to soc/nuvoton/npcx/common/soc_clock.h diff --git a/soc/arm/nuvoton_npcx/common/soc_dbg.h b/soc/nuvoton/npcx/common/soc_dbg.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_dbg.h rename to soc/nuvoton/npcx/common/soc_dbg.h diff --git a/soc/arm/nuvoton_npcx/common/soc_dt.h b/soc/nuvoton/npcx/common/soc_dt.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_dt.h rename to soc/nuvoton/npcx/common/soc_dt.h diff --git a/soc/arm/nuvoton_npcx/common/soc_espi.h b/soc/nuvoton/npcx/common/soc_espi.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_espi.h rename to soc/nuvoton/npcx/common/soc_espi.h diff --git a/soc/arm/nuvoton_npcx/common/soc_espi_taf.h b/soc/nuvoton/npcx/common/soc_espi_taf.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_espi_taf.h rename to soc/nuvoton/npcx/common/soc_espi_taf.h diff --git a/soc/arm/nuvoton_npcx/common/soc_gpio.h b/soc/nuvoton/npcx/common/soc_gpio.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_gpio.h rename to soc/nuvoton/npcx/common/soc_gpio.h diff --git a/soc/arm/nuvoton_npcx/common/soc_host.h b/soc/nuvoton/npcx/common/soc_host.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_host.h rename to soc/nuvoton/npcx/common/soc_host.h diff --git a/soc/arm/nuvoton_npcx/common/soc_miwu.h b/soc/nuvoton/npcx/common/soc_miwu.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_miwu.h rename to soc/nuvoton/npcx/common/soc_miwu.h diff --git a/soc/arm/nuvoton_npcx/common/soc_pins.h b/soc/nuvoton/npcx/common/soc_pins.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_pins.h rename to soc/nuvoton/npcx/common/soc_pins.h diff --git a/soc/arm/nuvoton_npcx/common/soc_power.h b/soc/nuvoton/npcx/common/soc_power.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_power.h rename to soc/nuvoton/npcx/common/soc_power.h diff --git a/soc/nuvoton/npcx/npcx4/CMakeLists.txt b/soc/nuvoton/npcx/npcx4/CMakeLists.txt new file mode 100644 index 00000000000..ea6ef98230a --- /dev/null +++ b/soc/nuvoton/npcx/npcx4/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories( + . + ${ZEPHYR_BASE}/drivers +) + +zephyr_sources( + soc.c +) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/npcx/npcx4/Kconfig b/soc/nuvoton/npcx/npcx4/Kconfig new file mode 100644 index 00000000000..0983b7c7eff --- /dev/null +++ b/soc/nuvoton/npcx/npcx4/Kconfig @@ -0,0 +1,12 @@ +# Nuvoton NPCX4 EC series + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX4 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_PM diff --git a/soc/nuvoton/npcx/npcx4/Kconfig.defconfig b/soc/nuvoton/npcx/npcx4/Kconfig.defconfig new file mode 100644 index 00000000000..1c4be7c3a57 --- /dev/null +++ b/soc/nuvoton/npcx/npcx4/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NPCX4 + +config NUM_IRQS + default 128 + +config CORTEX_M_SYSTICK + default !NPCX_ITIM_TIMER + +config ESPI_TAF_NPCX + default y + depends on ESPI_SAF + +endif # SOC_SERIES_NPCX4 diff --git a/soc/nuvoton/npcx/npcx4/Kconfig.soc b/soc/nuvoton/npcx/npcx4/Kconfig.soc new file mode 100644 index 00000000000..e825bc7fc6f --- /dev/null +++ b/soc/nuvoton/npcx/npcx4/Kconfig.soc @@ -0,0 +1,29 @@ +# Nuvoton NPCX4 EC series + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX4 + bool + select SOC_FAMILY_NPCX + help + Enable support for Nuvoton NPCX4 series + +config SOC_NPCX4M3F + bool + select SOC_SERIES_NPCX4 + help + NPCX4M3F + +config SOC_NPCX4M8F + bool + select SOC_SERIES_NPCX4 + help + NPCX4M8F + +config SOC_SERIES + default "npcx4" if SOC_SERIES_NPCX4 + +config SOC + default "npcx4m3f" if SOC_NPCX4M3F + default "npcx4m8f" if SOC_NPCX4M8F diff --git a/soc/arm/nuvoton_npcx/npcx4/soc.c b/soc/nuvoton/npcx/npcx4/soc.c similarity index 100% rename from soc/arm/nuvoton_npcx/npcx4/soc.c rename to soc/nuvoton/npcx/npcx4/soc.c diff --git a/soc/arm/nuvoton_npcx/npcx4/soc.h b/soc/nuvoton/npcx/npcx4/soc.h similarity index 100% rename from soc/arm/nuvoton_npcx/npcx4/soc.h rename to soc/nuvoton/npcx/npcx4/soc.h diff --git a/soc/nuvoton/npcx/npcx7/CMakeLists.txt b/soc/nuvoton/npcx/npcx7/CMakeLists.txt new file mode 100644 index 00000000000..7b96d5d5507 --- /dev/null +++ b/soc/nuvoton/npcx/npcx7/CMakeLists.txt @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories( + . + ${ZEPHYR_BASE}/drivers +) + +zephyr_sources( + soc.c +) + +zephyr_sources_ifdef( + CONFIG_ARM_MPU + mpu_regions.c +) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/npcx/npcx7/Kconfig b/soc/nuvoton/npcx/npcx7/Kconfig new file mode 100644 index 00000000000..55e5a1c50c0 --- /dev/null +++ b/soc/nuvoton/npcx/npcx7/Kconfig @@ -0,0 +1,13 @@ +# Nuvoton Cortex-M4 Embedded Controller NPCX7 series + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX7 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select HAS_PM diff --git a/soc/nuvoton/npcx/npcx7/Kconfig.defconfig b/soc/nuvoton/npcx/npcx7/Kconfig.defconfig new file mode 100644 index 00000000000..76682e0a48a --- /dev/null +++ b/soc/nuvoton/npcx/npcx7/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NPCX7 + +config NUM_IRQS + default 64 + +config CORTEX_M_SYSTICK + default !NPCX_ITIM_TIMER + +endif # SOC_SERIES_NPCX7 diff --git a/soc/nuvoton/npcx/npcx7/Kconfig.soc b/soc/nuvoton/npcx/npcx7/Kconfig.soc new file mode 100644 index 00000000000..ca2bb268d23 --- /dev/null +++ b/soc/nuvoton/npcx/npcx7/Kconfig.soc @@ -0,0 +1,36 @@ +# Nuvoton Cortex-M4 Embedded Controller NPCX7 series + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX7 + bool + select SOC_FAMILY_NPCX + help + Enable support for Nuvoton NPCX7 series + +config SOC_NPCX7M6FB + bool + select SOC_SERIES_NPCX7 + help + NPCX7M6FB + +config SOC_NPCX7M6FC + bool + select SOC_SERIES_NPCX7 + help + NPCX7M6FC + +config SOC_NPCX7M7FC + bool + select SOC_SERIES_NPCX7 + help + NPCX7M7FC + +config SOC_SERIES + default "npcx7" if SOC_SERIES_NPCX7 + +config SOC + default "npcx7m6fb" if SOC_NPCX7M6FB + default "npcx7m6fc" if SOC_NPCX7M6FC + default "npcx7m7fc" if SOC_NPCX7M7FC diff --git a/soc/arm/nuvoton_npcx/npcx7/mpu_regions.c b/soc/nuvoton/npcx/npcx7/mpu_regions.c similarity index 100% rename from soc/arm/nuvoton_npcx/npcx7/mpu_regions.c rename to soc/nuvoton/npcx/npcx7/mpu_regions.c diff --git a/soc/arm/nuvoton_npcx/npcx7/soc.c b/soc/nuvoton/npcx/npcx7/soc.c similarity index 100% rename from soc/arm/nuvoton_npcx/npcx7/soc.c rename to soc/nuvoton/npcx/npcx7/soc.c diff --git a/soc/arm/nuvoton_npcx/npcx7/soc.h b/soc/nuvoton/npcx/npcx7/soc.h similarity index 100% rename from soc/arm/nuvoton_npcx/npcx7/soc.h rename to soc/nuvoton/npcx/npcx7/soc.h diff --git a/soc/nuvoton/npcx/npcx9/CMakeLists.txt b/soc/nuvoton/npcx/npcx9/CMakeLists.txt new file mode 100644 index 00000000000..7137403126d --- /dev/null +++ b/soc/nuvoton/npcx/npcx9/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories( + . + ${ZEPHYR_BASE}/drivers +) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/npcx/npcx9/Kconfig b/soc/nuvoton/npcx/npcx9/Kconfig new file mode 100644 index 00000000000..25cee4381b7 --- /dev/null +++ b/soc/nuvoton/npcx/npcx9/Kconfig @@ -0,0 +1,13 @@ +# Nuvoton Cortex-M4 Embedded Controller NPCX9 series + +# Copyright (c) 2021 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX9 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_FAMILY_NPCX + select HAS_PM diff --git a/soc/nuvoton/npcx/npcx9/Kconfig.defconfig b/soc/nuvoton/npcx/npcx9/Kconfig.defconfig new file mode 100644 index 00000000000..1f7da8453cb --- /dev/null +++ b/soc/nuvoton/npcx/npcx9/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2021 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NPCX9 + +config NUM_IRQS + default 64 + +config CORTEX_M_SYSTICK + default !NPCX_ITIM_TIMER + +endif # SOC_SERIES_NPCX9 diff --git a/soc/nuvoton/npcx/npcx9/Kconfig.soc b/soc/nuvoton/npcx/npcx9/Kconfig.soc new file mode 100644 index 00000000000..30f045eb0bf --- /dev/null +++ b/soc/nuvoton/npcx/npcx9/Kconfig.soc @@ -0,0 +1,43 @@ +# Nuvoton Cortex-M4 Embedded Controller NPCX9 series + +# Copyright (c) 2021 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX9 + bool + select SOC_FAMILY_NPCX + help + Enable support for Nuvoton NPCX9 series + +config SOC_NPCX9M3F + bool + select SOC_SERIES_NPCX9 + help + NPCX9M3F + +config SOC_NPCX9M6F + bool + select SOC_SERIES_NPCX9 + help + NPCX9M6F + +config SOC_NPCX9M7F + bool + select SOC_SERIES_NPCX9 + help + NPCX9M7F + +config SOC_NPCX9MFP + bool + select SOC_SERIES_NPCX9 + help + NPCX9MFP + +config SOC_SERIES + default "npcx9" if SOC_SERIES_NPCX9 + +config SOC + default "npcx9m3f" if SOC_NPCX9M3F + default "npcx9m6f" if SOC_NPCX9M6F + default "npcx9m7f" if SOC_NPCX9M7F + default "npcx9mfp" if SOC_NPCX9MFP diff --git a/soc/arm/nuvoton_npcx/npcx9/soc.h b/soc/nuvoton/npcx/npcx9/soc.h similarity index 100% rename from soc/arm/nuvoton_npcx/npcx9/soc.h rename to soc/nuvoton/npcx/npcx9/soc.h diff --git a/soc/nuvoton/npcx/soc.yml b/soc/nuvoton/npcx/soc.yml new file mode 100644 index 00000000000..2aab050969c --- /dev/null +++ b/soc/nuvoton/npcx/soc.yml @@ -0,0 +1,18 @@ +family: +- name: npcx + series: + - name: npcx4 + socs: + - name: npcx4m3f + - name: npcx4m8f + - name: npcx7 + socs: + - name: npcx7m6fb + - name: npcx7m6fc + - name: npcx7m7fc + - name: npcx9 + socs: + - name: npcx9m3f + - name: npcx9m6f + - name: npcx9m7f + - name: npcx9mfp diff --git a/soc/arm/nuvoton_numaker/CMakeLists.txt b/soc/nuvoton/numaker/CMakeLists.txt similarity index 100% rename from soc/arm/nuvoton_numaker/CMakeLists.txt rename to soc/nuvoton/numaker/CMakeLists.txt diff --git a/soc/nuvoton/numaker/Kconfig b/soc/nuvoton/numaker/Kconfig new file mode 100644 index 00000000000..d2a03b31a4d --- /dev/null +++ b/soc/nuvoton/numaker/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NUMAKER + select PLATFORM_SPECIFIC_INIT + +if SOC_FAMILY_NUMAKER + +rsource "*/Kconfig" + +endif # SOC_FAMILY_NUMAKER diff --git a/soc/nuvoton/numaker/Kconfig.defconfig b/soc/nuvoton/numaker/Kconfig.defconfig new file mode 100644 index 00000000000..43cb3e9c43b --- /dev/null +++ b/soc/nuvoton/numaker/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NUMAKER + +rsource "*/Kconfig.defconfig" + +config RESET + default y + +endif diff --git a/soc/nuvoton/numaker/Kconfig.soc b/soc/nuvoton/numaker/Kconfig.soc new file mode 100644 index 00000000000..8b09b99bd58 --- /dev/null +++ b/soc/nuvoton/numaker/Kconfig.soc @@ -0,0 +1,11 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NUMAKER + bool + +config SOC_FAMILY + default "numaker" if SOC_FAMILY_NUMAKER + +rsource "*/Kconfig.soc" diff --git a/soc/arm/nuvoton_numaker/common/pinctrl_soc.h b/soc/nuvoton/numaker/common/pinctrl_soc.h similarity index 100% rename from soc/arm/nuvoton_numaker/common/pinctrl_soc.h rename to soc/nuvoton/numaker/common/pinctrl_soc.h diff --git a/soc/nuvoton/numaker/m46x/CMakeLists.txt b/soc/nuvoton/numaker/m46x/CMakeLists.txt new file mode 100644 index 00000000000..58be053241b --- /dev/null +++ b/soc/nuvoton/numaker/m46x/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/numaker/m46x/Kconfig b/soc/nuvoton/numaker/m46x/Kconfig new file mode 100644 index 00000000000..408b3067bd8 --- /dev/null +++ b/soc/nuvoton/numaker/m46x/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_M46X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CORTEX_M_SYSTICK if SYS_CLOCK_EXISTS + +config SOC_M467 + select HAS_NUMAKER_HAL diff --git a/soc/nuvoton/numaker/m46x/Kconfig.defconfig b/soc/nuvoton/numaker/m46x/Kconfig.defconfig new file mode 100644 index 00000000000..71e6c62340b --- /dev/null +++ b/soc/nuvoton/numaker/m46x/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_M46X + +rsource "Kconfig.defconfig.m46*" + +endif # SOC_SERIES_M46X diff --git a/soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.m467 b/soc/nuvoton/numaker/m46x/Kconfig.defconfig.m467 similarity index 100% rename from soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.m467 rename to soc/nuvoton/numaker/m46x/Kconfig.defconfig.m467 diff --git a/soc/nuvoton/numaker/m46x/Kconfig.soc b/soc/nuvoton/numaker/m46x/Kconfig.soc new file mode 100644 index 00000000000..c1207a117a2 --- /dev/null +++ b/soc/nuvoton/numaker/m46x/Kconfig.soc @@ -0,0 +1,19 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_M46X + bool + select SOC_FAMILY_NUMAKER + help + Enable support for Nuvoton M46X MCU series + +config SOC_M467 + bool + select SOC_SERIES_M46X + +config SOC_SERIES + default "m46x" if SOC_SERIES_M46X + +config SOC + default "m467" if SOC_M467 diff --git a/soc/arm/nuvoton_numaker/m46x/soc.c b/soc/nuvoton/numaker/m46x/soc.c similarity index 100% rename from soc/arm/nuvoton_numaker/m46x/soc.c rename to soc/nuvoton/numaker/m46x/soc.c diff --git a/soc/arm/nuvoton_numaker/m46x/soc.h b/soc/nuvoton/numaker/m46x/soc.h similarity index 100% rename from soc/arm/nuvoton_numaker/m46x/soc.h rename to soc/nuvoton/numaker/m46x/soc.h diff --git a/soc/nuvoton/numaker/soc.yml b/soc/nuvoton/numaker/soc.yml new file mode 100644 index 00000000000..cad8f6d1fc4 --- /dev/null +++ b/soc/nuvoton/numaker/soc.yml @@ -0,0 +1,6 @@ +family: +- name: numaker + series: + - name: m46x + socs: + - name: m467 diff --git a/soc/arm/nuvoton_numicro/CMakeLists.txt b/soc/nuvoton/numicro/CMakeLists.txt similarity index 100% rename from soc/arm/nuvoton_numicro/CMakeLists.txt rename to soc/nuvoton/numicro/CMakeLists.txt diff --git a/soc/nuvoton/numicro/Kconfig b/soc/nuvoton/numicro/Kconfig new file mode 100644 index 00000000000..6f80bd23cf7 --- /dev/null +++ b/soc/nuvoton/numicro/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +config SOC_FAMILY_NUMICRO + select PLATFORM_SPECIFIC_INIT + +if SOC_FAMILY_NUMICRO + +rsource "*/Kconfig" + +endif # SOC_FAMILY_NUMICRO diff --git a/soc/nuvoton/numicro/Kconfig.defconfig b/soc/nuvoton/numicro/Kconfig.defconfig new file mode 100644 index 00000000000..b5973c5c00a --- /dev/null +++ b/soc/nuvoton/numicro/Kconfig.defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +if SOC_FAMILY_NUMICRO + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_NUMICRO diff --git a/soc/nuvoton/numicro/Kconfig.soc b/soc/nuvoton/numicro/Kconfig.soc new file mode 100644 index 00000000000..157191afeb9 --- /dev/null +++ b/soc/nuvoton/numicro/Kconfig.soc @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +config SOC_FAMILY_NUMICRO + bool + +config SOC_FAMILY + default "numicro" if SOC_FAMILY_NUMICRO + +rsource "*/Kconfig.soc" diff --git a/soc/arm/nuvoton_numicro/common/pinctrl_soc.h b/soc/nuvoton/numicro/common/pinctrl_soc.h similarity index 100% rename from soc/arm/nuvoton_numicro/common/pinctrl_soc.h rename to soc/nuvoton/numicro/common/pinctrl_soc.h diff --git a/soc/nuvoton/numicro/m48x/CMakeLists.txt b/soc/nuvoton/numicro/m48x/CMakeLists.txt new file mode 100644 index 00000000000..71fa70ed04b --- /dev/null +++ b/soc/nuvoton/numicro/m48x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/numicro/m48x/Kconfig b/soc/nuvoton/numicro/m48x/Kconfig new file mode 100644 index 00000000000..6a14e945244 --- /dev/null +++ b/soc/nuvoton/numicro/m48x/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +config SOC_SERIES_M48X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + +config SOC_M487 + select HAS_NUMICRO_HAL diff --git a/soc/nuvoton/numicro/m48x/Kconfig.defconfig b/soc/nuvoton/numicro/m48x/Kconfig.defconfig new file mode 100644 index 00000000000..9833529015e --- /dev/null +++ b/soc/nuvoton/numicro/m48x/Kconfig.defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +if SOC_SERIES_M48X + +rsource "Kconfig.defconfig.m48*" + +endif # SOC_SERIES_M48X diff --git a/soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.m487 b/soc/nuvoton/numicro/m48x/Kconfig.defconfig.m487 similarity index 100% rename from soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.m487 rename to soc/nuvoton/numicro/m48x/Kconfig.defconfig.m487 diff --git a/soc/nuvoton/numicro/m48x/Kconfig.soc b/soc/nuvoton/numicro/m48x/Kconfig.soc new file mode 100644 index 00000000000..8d0efbe0237 --- /dev/null +++ b/soc/nuvoton/numicro/m48x/Kconfig.soc @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +config SOC_SERIES_M48X + bool + select SOC_FAMILY_NUMICRO + help + Enable support for NUVOTON M48X MCU series + +config SOC_M487 + bool + select SOC_SERIES_M48X + +config SOC_SERIES + default "m48x" if SOC_SERIES_M48X + +config SOC + default "m487" if SOC_M487 diff --git a/soc/arm/nuvoton_numicro/m48x/soc.c b/soc/nuvoton/numicro/m48x/soc.c similarity index 100% rename from soc/arm/nuvoton_numicro/m48x/soc.c rename to soc/nuvoton/numicro/m48x/soc.c diff --git a/soc/arm/nuvoton_numicro/m48x/soc.h b/soc/nuvoton/numicro/m48x/soc.h similarity index 100% rename from soc/arm/nuvoton_numicro/m48x/soc.h rename to soc/nuvoton/numicro/m48x/soc.h diff --git a/soc/nuvoton/numicro/soc.yml b/soc/nuvoton/numicro/soc.yml new file mode 100644 index 00000000000..9812e29e4b0 --- /dev/null +++ b/soc/nuvoton/numicro/soc.yml @@ -0,0 +1,6 @@ +family: +- name: numicro + series: + - name: m48x + socs: + - name: m487 diff --git a/soc/nxp/imx/CMakeLists.txt b/soc/nxp/imx/CMakeLists.txt new file mode 100644 index 00000000000..f14f2e1e116 --- /dev/null +++ b/soc/nxp/imx/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) + +zephyr_include_directories(.) +zephyr_include_directories(${SOC_SERIES}) + +zephyr_include_directories(${SOC_SERIES}/include) diff --git a/soc/nxp/imx/Kconfig b/soc/nxp/imx/Kconfig new file mode 100644 index 00000000000..9fba09a031e --- /dev/null +++ b/soc/nxp/imx/Kconfig @@ -0,0 +1,13 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_IMX + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +if SOC_FAMILY_NXP_IMX + +# Source series Kconfig files first, so SOCs +# can override the defaults given here +rsource "*/Kconfig" + +endif # SOC_FAMILY_NXP_IMX diff --git a/soc/nxp/imx/Kconfig.defconfig b/soc/nxp/imx/Kconfig.defconfig new file mode 100644 index 00000000000..a6063878317 --- /dev/null +++ b/soc/nxp/imx/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NXP_IMX + +# Source series Kconfig files first, so SoCs +# can override the defaults given here +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_NXP_IMX diff --git a/soc/nxp/imx/Kconfig.soc b/soc/nxp/imx/Kconfig.soc new file mode 100644 index 00000000000..d0418fce746 --- /dev/null +++ b/soc/nxp/imx/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_IMX + bool + +config SOC_FAMILY + default "nxp_imx" if SOC_FAMILY_NXP_IMX + +rsource "*/Kconfig.soc" diff --git a/soc/nxp/imx/imx6sx/CMakeLists.txt b/soc/nxp/imx/imx6sx/CMakeLists.txt new file mode 100644 index 00000000000..8bebaa89bee --- /dev/null +++ b/soc/nxp/imx/imx6sx/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright 2018,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c + soc_clk_freq.c +) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imx/imx6sx/Kconfig b/soc/nxp/imx/imx6sx/Kconfig new file mode 100644 index 00000000000..901b2c90a64 --- /dev/null +++ b/soc/nxp/imx/imx6sx/Kconfig @@ -0,0 +1,18 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX6SX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select HAS_IMX_HAL + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CLOCK_CONTROL + +config SOC_MCIMX6X_M4 + select HAS_IMX_HAL + select HAS_IMX_GPIO + select HAS_IMX_EPIT + select HAS_IMX_I2C + select HAS_IMX_IOMUXC diff --git a/soc/nxp/imx/imx6sx/Kconfig.defconfig b/soc/nxp/imx/imx6sx/Kconfig.defconfig new file mode 100644 index 00000000000..e2683c90fa1 --- /dev/null +++ b/soc/nxp/imx/imx6sx/Kconfig.defconfig @@ -0,0 +1,18 @@ +# i.MX 6SoloX core series + +# Copyright 2018,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX6SX + +config NUM_IRQS + # must be >= the highest interrupt number used + default 128 + +config PINCTRL_IMX + default y if HAS_IMX_IOMUXC + depends on PINCTRL + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_IMX6SX diff --git a/soc/nxp/imx/imx6sx/Kconfig.defconfig.mcimx6x_m4 b/soc/nxp/imx/imx6sx/Kconfig.defconfig.mcimx6x_m4 new file mode 100644 index 00000000000..9a925ade2f6 --- /dev/null +++ b/soc/nxp/imx/imx6sx/Kconfig.defconfig.mcimx6x_m4 @@ -0,0 +1,11 @@ +# i.MX 6SoloX + +# Copyright 2018,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MCIMX6X_M4 + +config FPU + default y + +endif # SOC_MCIMX6X_M4 diff --git a/soc/nxp/imx/imx6sx/Kconfig.soc b/soc/nxp/imx/imx6sx/Kconfig.soc new file mode 100644 index 00000000000..e6f968bb9e3 --- /dev/null +++ b/soc/nxp/imx/imx6sx/Kconfig.soc @@ -0,0 +1,83 @@ +# i.MX 6SoloX core series + +# Copyright 2018,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + + +config SOC_SERIES_IMX6SX + bool + select SOC_FAMILY_NXP_IMX + +config SOC_MCIMX6X + bool + select SOC_SERIES_IMX6SX + +config SOC_MCIMX6X_M4 + select SOC_MCIMX6X + bool + help + NXP iMX6 SoloX M4 core + +config SOC_SERIES + default "imx6sx" if SOC_SERIES_IMX6SX + +config SOC + default "mcimx6x" if SOC_MCIMX6X + +config SOC_PART_NUMBER_MCIMX6X1EVK10AB + bool + +config SOC_PART_NUMBER_MCIMX6X1EVK10AC + bool + +config SOC_PART_NUMBER_MCIMX6X3EVK10AB + bool + +config SOC_PART_NUMBER_MCIMX6X3EVK10AC + bool + +config SOC_PART_NUMBER_MCIMX6X1EVO10AB + bool + +config SOC_PART_NUMBER_MCIMX6X1EVO10AC + bool + +config SOC_PART_NUMBER_MCIMX6X3EVO10AB + bool + +config SOC_PART_NUMBER_MCIMX6X3EVO10AC + bool + +config SOC_PART_NUMBER_MCIMX6X2EVN10AB + bool + +config SOC_PART_NUMBER_MCIMX6X2EVN10AC + bool + +config SOC_PART_NUMBER_MCIMX6X3EVN10AB + bool + +config SOC_PART_NUMBER_MCIMX6X3EVN10AC + bool + +config SOC_PART_NUMBER_MCIMX6X4EVM10AB + bool + +config SOC_PART_NUMBER_MCIMX6X4EVM10AC + bool + +config SOC_PART_NUMBER + default "MCIMX6X1EVK10AB" if SOC_PART_NUMBER_MCIMX6X1EVK10AB + default "MCIMX6X1EVK10AC" if SOC_PART_NUMBER_MCIMX6X1EVK10AC + default "MCIMX6X3EVK10AB" if SOC_PART_NUMBER_MCIMX6X3EVK10AB + default "MCIMX6X3EVK10AC" if SOC_PART_NUMBER_MCIMX6X3EVK10AC + default "MCIMX6X1EVO10AB" if SOC_PART_NUMBER_MCIMX6X1EVO10AB + default "MCIMX6X1EVO10AC" if SOC_PART_NUMBER_MCIMX6X1EVO10AC + default "MCIMX6X3EVO10AB" if SOC_PART_NUMBER_MCIMX6X3EVO10AB + default "MCIMX6X3EVO10AC" if SOC_PART_NUMBER_MCIMX6X3EVO10AC + default "MCIMX6X2EVN10AB" if SOC_PART_NUMBER_MCIMX6X2EVN10AB + default "MCIMX6X2EVN10AC" if SOC_PART_NUMBER_MCIMX6X2EVN10AC + default "MCIMX6X3EVN10AB" if SOC_PART_NUMBER_MCIMX6X3EVN10AB + default "MCIMX6X3EVN10AC" if SOC_PART_NUMBER_MCIMX6X3EVN10AC + default "MCIMX6X4EVM10AB" if SOC_PART_NUMBER_MCIMX6X4EVM10AB + default "MCIMX6X4EVM10AC" if SOC_PART_NUMBER_MCIMX6X4EVM10AC diff --git a/soc/arm/nxp_imx/mcimx6x_m4/pinctrl_soc.h b/soc/nxp/imx/imx6sx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/mcimx6x_m4/pinctrl_soc.h rename to soc/nxp/imx/imx6sx/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc.c b/soc/nxp/imx/imx6sx/soc.c similarity index 100% rename from soc/arm/nxp_imx/mcimx6x_m4/soc.c rename to soc/nxp/imx/imx6sx/soc.c diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc.h b/soc/nxp/imx/imx6sx/soc.h similarity index 100% rename from soc/arm/nxp_imx/mcimx6x_m4/soc.h rename to soc/nxp/imx/imx6sx/soc.h diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc_clk_freq.c b/soc/nxp/imx/imx6sx/soc_clk_freq.c similarity index 100% rename from soc/arm/nxp_imx/mcimx6x_m4/soc_clk_freq.c rename to soc/nxp/imx/imx6sx/soc_clk_freq.c diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc_clk_freq.h b/soc/nxp/imx/imx6sx/soc_clk_freq.h similarity index 100% rename from soc/arm/nxp_imx/mcimx6x_m4/soc_clk_freq.h rename to soc/nxp/imx/imx6sx/soc_clk_freq.h diff --git a/soc/nxp/imx/imx7d/CMakeLists.txt b/soc/nxp/imx/imx7d/CMakeLists.txt new file mode 100644 index 00000000000..1c34ea54c88 --- /dev/null +++ b/soc/nxp/imx/imx7d/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright 2017,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c + soc_clk_freq.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imx/imx7d/Kconfig b/soc/nxp/imx/imx7d/Kconfig new file mode 100644 index 00000000000..fbebe524242 --- /dev/null +++ b/soc/nxp/imx/imx7d/Kconfig @@ -0,0 +1,16 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX7D + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CLOCK_CONTROL + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + +config SOC_MCIMX7D_M4 + select HAS_IMX_HAL + select HAS_IMX_GPIO + select HAS_IMX_I2C + select HAS_IMX_IOMUXC diff --git a/soc/nxp/imx/imx7d/Kconfig.defconfig b/soc/nxp/imx/imx7d/Kconfig.defconfig new file mode 100644 index 00000000000..2fa2f371ab0 --- /dev/null +++ b/soc/nxp/imx/imx7d/Kconfig.defconfig @@ -0,0 +1,18 @@ +# iMX7 core series + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX7D + +config NUM_IRQS + # must be >= the highest interrupt number used + default 127 + +config PINCTRL_IMX + default y if HAS_IMX_IOMUXC + depends on PINCTRL + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_IMX7D diff --git a/soc/nxp/imx/imx7d/Kconfig.defconfig.mcimx7d_m4 b/soc/nxp/imx/imx7d/Kconfig.defconfig.mcimx7d_m4 new file mode 100644 index 00000000000..2e9d5e71d9d --- /dev/null +++ b/soc/nxp/imx/imx7d/Kconfig.defconfig.mcimx7d_m4 @@ -0,0 +1,14 @@ +# iMX7 M4 core series + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MCIMX7D_M4 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 200000000 + +config GPIO + default y + +endif # SOC_MCIMX7D_M4 diff --git a/soc/nxp/imx/imx7d/Kconfig.soc b/soc/nxp/imx/imx7d/Kconfig.soc new file mode 100644 index 00000000000..d7040cdaedb --- /dev/null +++ b/soc/nxp/imx/imx7d/Kconfig.soc @@ -0,0 +1,40 @@ +# iMX7D core series + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX7D + bool + select SOC_FAMILY_NXP_IMX + help + Enable support for iMX7D MCU series + +config SOC_MCIMX7D + bool + select SOC_SERIES_IMX7D + +config SOC_MCIMX7D_M4 + bool + select SOC_MCIMX7D + help + NXP iMX7 Dual M4 Core + +config SOC_SERIES + default "imx7d" if SOC_SERIES_IMX7D + +config SOC + default "mcimx7d" if SOC_MCIMX7D + +config SOC_PART_NUMBER_MCIMX7D7DVM10SC + bool + +config SOC_PART_NUMBER_MCIMX7D5EVM10SC + bool + +config SOC_PART_NUMBER_MCIMX7S3DVK08SA + bool + +config SOC_PART_NUMBER + default "MCIMX7D7DVM10SC" if SOC_PART_NUMBER_MCIMX7D7DVM10SC + default "MCIMX7D5EVM10SC" if SOC_PART_NUMBER_MCIMX7D5EVM10SC + default "MCIMX7S3DVK08SA" if SOC_PART_NUMBER_MCIMX7S3DVK08SA diff --git a/soc/arm/nxp_imx/mcimx7_m4/pinctrl_soc.h b/soc/nxp/imx/imx7d/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/mcimx7_m4/pinctrl_soc.h rename to soc/nxp/imx/imx7d/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/mcimx7_m4/soc.c b/soc/nxp/imx/imx7d/soc.c similarity index 100% rename from soc/arm/nxp_imx/mcimx7_m4/soc.c rename to soc/nxp/imx/imx7d/soc.c diff --git a/soc/arm/nxp_imx/mcimx7_m4/soc.h b/soc/nxp/imx/imx7d/soc.h similarity index 100% rename from soc/arm/nxp_imx/mcimx7_m4/soc.h rename to soc/nxp/imx/imx7d/soc.h diff --git a/soc/arm/nxp_imx/mcimx7_m4/soc_clk_freq.c b/soc/nxp/imx/imx7d/soc_clk_freq.c similarity index 100% rename from soc/arm/nxp_imx/mcimx7_m4/soc_clk_freq.c rename to soc/nxp/imx/imx7d/soc_clk_freq.c diff --git a/soc/arm/nxp_imx/mcimx7_m4/soc_clk_freq.h b/soc/nxp/imx/imx7d/soc_clk_freq.h similarity index 100% rename from soc/arm/nxp_imx/mcimx7_m4/soc_clk_freq.h rename to soc/nxp/imx/imx7d/soc_clk_freq.h diff --git a/soc/nxp/imx/imx8/CMakeLists.txt b/soc/nxp/imx/imx8/CMakeLists.txt new file mode 100644 index 00000000000..209de9c95ad --- /dev/null +++ b/soc/nxp/imx/imx8/CMakeLists.txt @@ -0,0 +1,27 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX8QM_ADSP) + zephyr_include_directories(adsp) + add_subdirectory(adsp) + + zephyr_sources( + adsp/pinctrl_soc.h + ) + + # west sign + + # See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt + add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + ) + + add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} + ) + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/nxp/imx/imx8/Kconfig b/soc/nxp/imx/imx8/Kconfig new file mode 100644 index 00000000000..e7993616bbd --- /dev/null +++ b/soc/nxp/imx/imx8/Kconfig @@ -0,0 +1,15 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX8QM_ADSP + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + select ATOMIC_OPERATIONS_BUILTIN + select GEN_ISR_TABLES + select XTENSA_SMALL_VECTOR_TABLE_ENTRY + select HAS_MCUX + +config MCUX_CORE_SUFFIX + default "_dsp" if SOC_MIMX8QM_ADSP diff --git a/soc/nxp/imx/imx8/Kconfig.defconfig b/soc/nxp/imx/imx8/Kconfig.defconfig new file mode 100644 index 00000000000..203c43b1214 --- /dev/null +++ b/soc/nxp/imx/imx8/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX8 + +if SOC_MIMX8QM_ADSP + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 666000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 50000 + +config DCACHE_LINE_SIZE + default 128 + +config GEN_IRQ_VECTOR_TABLE + default n + +config CACHE_MANAGEMENT + default y + +config SMP + default n + +config XTENSA_TIMER + default y + +config KERNEL_ENTRY + default "__start" + +config MULTI_LEVEL_INTERRUPTS + default n + +config 2ND_LEVEL_INTERRUPTS + default n + +# To prevent test uses TEST_LOGGING_MINIMAL +config TEST_LOGGING_DEFAULTS + default n + depends on TEST + +endif # SOC_MIMX8QM_ADSP + +endif # SOC_SERIES_IMX8 diff --git a/soc/nxp/imx/imx8/Kconfig.soc b/soc/nxp/imx/imx8/Kconfig.soc new file mode 100644 index 00000000000..46903a8437d --- /dev/null +++ b/soc/nxp/imx/imx8/Kconfig.soc @@ -0,0 +1,32 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX8 + bool + select SOC_FAMILY_NXP_IMX + +config SOC_SERIES + default "imx8" if SOC_SERIES_IMX8 + +config SOC_MIMX8QM + bool + select SOC_SERIES_IMX8 + +config SOC + default "mimx8qm6" if SOC_MIMX8QM + +config SOC_MIMX8QM_ADSP + bool + select SOC_MIMX8QM + help + Enable support for NXP i.MX 8QM Audio DSP + +config SOC_TOOLCHAIN_NAME + string + default "nxp_imx_adsp" if SOC_MIMX8QM_ADSP + +config SOC_PART_NUMBER_MIMX8QM6AVUFF + bool + +config SOC_PART_NUMBER + default "MIMX8QM6AVUFF" if SOC_PART_NUMBER_MIMX8QM6AVUFF diff --git a/soc/nxp/imx/imx8/adsp/CMakeLists.txt b/soc/nxp/imx/imx8/adsp/CMakeLists.txt new file mode 100644 index 00000000000..a91c5991412 --- /dev/null +++ b/soc/nxp/imx/imx8/adsp/CMakeLists.txt @@ -0,0 +1,6 @@ +# NXP SoC family CMake file +# +# Copyright (c) 2021, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) diff --git a/soc/xtensa/nxp_adsp/imx8/include/_soc_inthandlers.h b/soc/nxp/imx/imx8/adsp/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8/include/_soc_inthandlers.h rename to soc/nxp/imx/imx8/adsp/_soc_inthandlers.h diff --git a/soc/xtensa/nxp_adsp/common/include/adsp/cache.h b/soc/nxp/imx/imx8/adsp/include/adsp/cache.h similarity index 100% rename from soc/xtensa/nxp_adsp/common/include/adsp/cache.h rename to soc/nxp/imx/imx8/adsp/include/adsp/cache.h diff --git a/soc/xtensa/nxp_adsp/common/include/adsp/io.h b/soc/nxp/imx/imx8/adsp/include/adsp/io.h similarity index 100% rename from soc/xtensa/nxp_adsp/common/include/adsp/io.h rename to soc/nxp/imx/imx8/adsp/include/adsp/io.h diff --git a/soc/xtensa/nxp_adsp/common/include/soc.h b/soc/nxp/imx/imx8/adsp/include/soc.h similarity index 100% rename from soc/xtensa/nxp_adsp/common/include/soc.h rename to soc/nxp/imx/imx8/adsp/include/soc.h diff --git a/soc/xtensa/nxp_adsp/imx8/linker.ld b/soc/nxp/imx/imx8/adsp/linker.ld similarity index 100% rename from soc/xtensa/nxp_adsp/imx8/linker.ld rename to soc/nxp/imx/imx8/adsp/linker.ld diff --git a/soc/xtensa/nxp_adsp/imx8/include/memory.h b/soc/nxp/imx/imx8/adsp/memory.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8/include/memory.h rename to soc/nxp/imx/imx8/adsp/memory.h diff --git a/soc/xtensa/nxp_adsp/imx8/pinctrl_soc.h b/soc/nxp/imx/imx8/adsp/pinctrl_soc.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8/pinctrl_soc.h rename to soc/nxp/imx/imx8/adsp/pinctrl_soc.h diff --git a/soc/nxp/imx/imx8m/CMakeLists.txt b/soc/nxp/imx/imx8m/CMakeLists.txt new file mode 100644 index 00000000000..8f319c6827a --- /dev/null +++ b/soc/nxp/imx/imx8m/CMakeLists.txt @@ -0,0 +1,52 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX8MP_ADSP) + zephyr_include_directories(adsp) + add_subdirectory(adsp) + + zephyr_sources( + adsp/pinctrl_soc.h + ) + + # west sign + + # See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt + add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + ) + + add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} + ) + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "") +endif() + +if(CONFIG_SOC_MIMX8ML8_A53 OR CONFIG_SOC_MIMX8MM6_A53 OR CONFIG_SOC_MIMX8MN6_A53) + zephyr_include_directories(.) + zephyr_include_directories(a53) + + zephyr_sources( + a53/pinctrl_soc.h + ) + + zephyr_sources_ifdef(CONFIG_ARM_MMU a53/mmu_regions.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +endif() + +if(CONFIG_SOC_MIMX8MM6_M4) + add_subdirectory(m4_mini) +endif() + +if(CONFIG_SOC_MIMX8MQ6_M4) + add_subdirectory(m4_quad) +endif() + +if(CONFIG_SOC_MIMX8MP_M7) + add_subdirectory(m7) +endif() diff --git a/soc/nxp/imx/imx8m/Kconfig b/soc/nxp/imx/imx8m/Kconfig new file mode 100644 index 00000000000..ed796a8c2da --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig @@ -0,0 +1,98 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX8MM6_A53 + select ARM64 + select CPU_CORTEX_A53 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + +config SOC_MIMX8MM6_M4 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_MCUX + select HAS_MCUX_CCM + select HAS_MCUX_RDC + select HAS_MCUX_IGPIO + select HAS_MCUX_IOMUXC + +config SOC_MIMX8ML8_A53 + select ARM64 + select CPU_CORTEX_A53 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + +config SOC_MIMX8MN6_A53 + select ARM64 + select CPU_CORTEX_A53 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + +config SOC_MIMX8MP_ADSP + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + select ATOMIC_OPERATIONS_BUILTIN + select GEN_ISR_TABLES + select XTENSA_SMALL_VECTOR_TABLE_ENTRY + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + select PINCTRL_IMX if HAS_MCUX_IOMUXC + +config SOC_MIMX8MP_M7 + select ARM + select CPU_CORTEX_M7 + select CPU_HAS_FPU + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select INIT_VIDEO_PLL + select HAS_MCUX + select HAS_MCUX_CCM + select HAS_MCUX_RDC + select CPU_HAS_ARM_MPU + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select ARM_MPU + select HAS_MCUX_IGPIO + select HAS_MCUX_IOMUXC + +config SOC_MIMX8MQ6_M4 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_MCUX + select HAS_MCUX_CCM + select HAS_MCUX_RDC + select HAS_MCUX_IOMUXC + +config MCUX_CORE_SUFFIX + default "_ca53" if SOC_MIMX8MM6_A53 || SOC_MIMX8MN6_A53 || SOC_MIMX8ML8_A53 + default "_dsp" if SOC_MIMX8MP_ADSP + +if SOC_MIMX8MP_M7 + +choice CODE_LOCATION + prompt "Code location selection" + +config CODE_ITCM + bool "Link code into internal instruction tightly coupled memory (ITCM)" + +config CODE_DDR + bool "Link code into DDR memory" + +endchoice + +config INIT_VIDEO_PLL + bool "Initialize Video PLL" + +endif # SOC_MIMX8MP_M7 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig b/soc/nxp/imx/imx8m/Kconfig.defconfig new file mode 100644 index 00000000000..d2e42646343 --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX8M + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_IMX8M diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 new file mode 100644 index 00000000000..acd7d02761d --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 @@ -0,0 +1,53 @@ +# MIMX8ML8 SoC defconfig + +# Copyright (c) 2021, Laird Connectivity +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8MP_M7 + +config SOC + string + default "mimx8ml8" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 800000000 + +config GPIO + default y + +config IPM_IMX + default y + depends on IPM + +if CODE_ITCM + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/itcm@0,0,K) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/itcm@0) + +endif # CODE_ITCM + +if CODE_DDR + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/code@80000000,0,K) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/code@80000000) + +endif # CODE_DDR + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 159 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif # SOC_MIMX8MP_M7 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp new file mode 100644 index 00000000000..6c29a2975f7 --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp @@ -0,0 +1,48 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX8M + +if SOC_MIMX8MP_ADSP + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 800000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 50000 + +config DCACHE_LINE_SIZE + default 128 + +config GEN_IRQ_VECTOR_TABLE + default n + +config CACHE_MANAGEMENT + default y + +config SMP + default n + +config XTENSA_TIMER + default y + +config KERNEL_ENTRY + default "__start" + +config MULTI_LEVEL_INTERRUPTS + default n + +config 2ND_LEVEL_INTERRUPTS + default n + +config DYNAMIC_INTERRUPTS + default y + +# To prevent test uses TEST_LOGGING_MINIMAL +config TEST_LOGGING_DEFAULTS + default n + depends on TEST + +endif # SOC_MIMX8MP_ADSP + +endif # SOC_SERIES_IMX8M diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.a53 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.a53 new file mode 100644 index 00000000000..39ce520f5ab --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.a53 @@ -0,0 +1,27 @@ +# Copyright 2020-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8MM6_A53 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + int + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 8000000 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.m4 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.m4 new file mode 100644 index 00000000000..02f068af04f --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.m4 @@ -0,0 +1,26 @@ +# MIMX8MM6 M4 SoC defconfig + +# Copyright (c) 2020, Manivannan Sadhasivam +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8MM6_M4 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 400000000 + +config IPM_IMX + default y + depends on IPM + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 127 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif # SOC_MIMX8MM6_M4 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn.a53 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn.a53 new file mode 100644 index 00000000000..f48c3187b19 --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn.a53 @@ -0,0 +1,27 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8MN6_A53 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + int + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 8000000 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mp.a53 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mp.a53 new file mode 100644 index 00000000000..23edb44e9dd --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mp.a53 @@ -0,0 +1,27 @@ +# Copyright 2021-2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8ML8_A53 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + int + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 8000000 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4 new file mode 100644 index 00000000000..0f9e144bfde --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4 @@ -0,0 +1,22 @@ +# MIMX8MQ6 M4 SoC defconfig + +# Copyright (c) 2021, Kwon Tae-young +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8MQ6_M4 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 266000000 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 127 + +endif # SOC_MIMX8MQ6_M4 diff --git a/soc/nxp/imx/imx8m/Kconfig.soc b/soc/nxp/imx/imx8m/Kconfig.soc new file mode 100644 index 00000000000..79471279a75 --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.soc @@ -0,0 +1,115 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX8M + bool + select SOC_FAMILY_NXP_IMX + +config SOC_SERIES + default "imx8m" if SOC_SERIES_IMX8M + +config SOC_MIMX8MP + bool + select SOC_SERIES_IMX8M + +config SOC_MIMX8MM6 + bool + select SOC_SERIES_IMX8M + +config SOC_MIMX8MM6_A53 + bool + select SOC_MIMX8MM6 + help + NXP i.MX8MM A53 + +config SOC_MIMX8MM6_M4 + bool + select SOC_MIMX8MM6 + help + NXP i.MX8MM M4 + +config SOC_MIMX8MP + bool + select SOC_SERIES_IMX8M + +config SOC_MIMX8ML8_A53 + bool + select SOC_MIMX8MP + help + NXP i.MX8MP A53 + +config SOC_MIMX8MP_ADSP + bool + select SOC_MIMX8MP + help + Enable support for NXP i.MX 8MPLUS Audio DSP + +config SOC_MIMX8MP_M7 + bool + select SOC_MIMX8MP + help + Enable support for NXP i.MX 8MPLUS M7 MCU + +config SOC_MIMX8MQ6 + bool + select SOC_SERIES_IMX8M + +config SOC_MIMX8MQ6_M4 + bool + select SOC_MIMX8MQ6 + help + Enable support for NXP i.MX 8M Quad M4 MCU + +config SOC_TOOLCHAIN_NAME + string + default "nxp_imx8m_adsp" if SOC_MIMX8MP_ADSP + +config SOC_MIMX8MN6 + bool + select SOC_SERIES_IMX8M + +config SOC_MIMX8MN6_A53 + bool + select SOC_MIMX8MN6 + help + NXP i.MX8MN A53 + +config SOC + default "mimx8mm6" if SOC_MIMX8MM6 + default "mimx8mn6" if SOC_MIMX8MN6 + default "mimx8ml8" if SOC_MIMX8MP + default "mimx8mq6" if SOC_MIMX8MQ6 + +config SOC_PART_NUMBER_MIMX8ML8DVNLZ + bool + +config SOC_PART_NUMBER_MIMX8MM6DVTLZ + bool + +config SOC_PART_NUMBER_MIMX8MM6CVTKZ + bool + +config SOC_PART_NUMBER_MIMX8MN6DVTJZ + bool + +config SOC_PART_NUMBER_MIMX8MN6DUCJZ + bool + +config SOC_PART_NUMBER_MIMX8MN6CVTIZ + bool + +config SOC_PART_NUMBER_MIMX8MN6CUCIZ + bool + +config SOC_PART_NUMBER_MIMX8MQ6DVAJZ + bool + +config SOC_PART_NUMBER + default "MIMX8ML8DVNLZ" if SOC_PART_NUMBER_MIMX8ML8DVNLZ + default "MIMX8MM6DVTLZ" if SOC_PART_NUMBER_MIMX8MM6DVTLZ + default "MIMX8MM6CVTKZ" if SOC_PART_NUMBER_MIMX8MM6CVTKZ + default "MIMX8MN6DVTJZ" if SOC_PART_NUMBER_MIMX8MN6DVTJZ + default "MIMX8MN6DUCJZ" if SOC_PART_NUMBER_MIMX8MN6DUCJZ + default "MIMX8MN6CVTIZ" if SOC_PART_NUMBER_MIMX8MN6CVTIZ + default "MIMX8MN6CUCIZ" if SOC_PART_NUMBER_MIMX8MN6CUCIZ + default "MIMX8MQ6DVAJZ" if SOC_PART_NUMBER_MIMX8MQ6DVAJZ diff --git a/soc/arm64/nxp_imx/mimx8m/mmu_regions.c b/soc/nxp/imx/imx8m/a53/mmu_regions.c similarity index 100% rename from soc/arm64/nxp_imx/mimx8m/mmu_regions.c rename to soc/nxp/imx/imx8m/a53/mmu_regions.c diff --git a/soc/arm64/nxp_imx/mimx8m/pinctrl_soc.h b/soc/nxp/imx/imx8m/a53/pinctrl_soc.h similarity index 100% rename from soc/arm64/nxp_imx/mimx8m/pinctrl_soc.h rename to soc/nxp/imx/imx8m/a53/pinctrl_soc.h diff --git a/soc/nxp/imx/imx8m/adsp/CMakeLists.txt b/soc/nxp/imx/imx8m/adsp/CMakeLists.txt new file mode 100644 index 00000000000..a91c5991412 --- /dev/null +++ b/soc/nxp/imx/imx8m/adsp/CMakeLists.txt @@ -0,0 +1,6 @@ +# NXP SoC family CMake file +# +# Copyright (c) 2021, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) diff --git a/soc/xtensa/nxp_adsp/imx8m/include/_soc_inthandlers.h b/soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8m/include/_soc_inthandlers.h rename to soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h diff --git a/soc/nxp/imx/imx8m/adsp/include/adsp/cache.h b/soc/nxp/imx/imx8m/adsp/include/adsp/cache.h new file mode 100644 index 00000000000..067c0890140 --- /dev/null +++ b/soc/nxp/imx/imx8m/adsp/include/adsp/cache.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __COMMON_ADSP_CACHE_H__ +#define __COMMON_ADSP_CACHE_H__ + +#include + +#endif diff --git a/soc/nxp/imx/imx8m/adsp/include/adsp/io.h b/soc/nxp/imx/imx8m/adsp/include/adsp/io.h new file mode 100644 index 00000000000..3d1f0ed98d5 --- /dev/null +++ b/soc/nxp/imx/imx8m/adsp/include/adsp/io.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INCLUDE_IO__ +#define __INCLUDE_IO__ + +#include +#include +#include +#include + +static inline uint32_t io_reg_read(uint32_t reg) +{ + return sys_read32(reg); +} + +static inline void io_reg_write(uint32_t reg, uint32_t val) +{ + sys_write32(val, reg); +} + +static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, + uint32_t value) +{ + io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); +} + +static inline uint16_t io_reg_read16(uint32_t reg) +{ + return sys_read16(reg); +} + +static inline void io_reg_write16(uint32_t reg, uint16_t val) +{ + sys_write16(val, reg); +} + +#endif diff --git a/soc/nxp/imx/imx8m/adsp/include/soc.h b/soc/nxp/imx/imx8m/adsp/include/soc.h new file mode 100644 index 00000000000..89ee9d96a52 --- /dev/null +++ b/soc/nxp/imx/imx8m/adsp/include/soc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include + +#ifndef __INC_IMX_SOC_H +#define __INC_IMX_SOC_H + +/* Macros related to interrupt handling */ +#define XTENSA_IRQ_NUM_SHIFT 0 +#define XTENSA_IRQ_NUM_MASK 0xff + +/* + * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00. + * + * 1. Peripheral Register bit offset. + */ +#define XTENSA_IRQ_NUMBER(_irq) \ + ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) + +extern void z_soc_irq_enable(uint32_t irq); +extern void z_soc_irq_disable(uint32_t irq); +extern int z_soc_irq_is_enabled(unsigned int irq); + +#endif /* __INC_IMX_SOC_H */ diff --git a/soc/xtensa/nxp_adsp/imx8m/linker.ld b/soc/nxp/imx/imx8m/adsp/linker.ld similarity index 100% rename from soc/xtensa/nxp_adsp/imx8m/linker.ld rename to soc/nxp/imx/imx8m/adsp/linker.ld diff --git a/soc/xtensa/nxp_adsp/imx8m/include/memory.h b/soc/nxp/imx/imx8m/adsp/memory.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8m/include/memory.h rename to soc/nxp/imx/imx8m/adsp/memory.h diff --git a/soc/xtensa/nxp_adsp/imx8m/include/pinctrl_soc.h b/soc/nxp/imx/imx8m/adsp/pinctrl_soc.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8m/include/pinctrl_soc.h rename to soc/nxp/imx/imx8m/adsp/pinctrl_soc.h diff --git a/soc/nxp/imx/imx8m/m4_mini/CMakeLists.txt b/soc/nxp/imx/imx8m/m4_mini/CMakeLists.txt new file mode 100644 index 00000000000..44a0caa5c78 --- /dev/null +++ b/soc/nxp/imx/imx8m/m4_mini/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# Copyright (c) 2020, Manivannan Sadhasivam +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +if(CONFIG_OPENAMP_RSC_TABLE) + zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) + zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") +endif() + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/linker.ld b/soc/nxp/imx/imx8m/m4_mini/linker.ld similarity index 100% rename from soc/arm/nxp_imx/mimx8mm6_m4/linker.ld rename to soc/nxp/imx/imx8m/m4_mini/linker.ld diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/pinctrl_soc.h b/soc/nxp/imx/imx8m/m4_mini/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8mm6_m4/pinctrl_soc.h rename to soc/nxp/imx/imx8m/m4_mini/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/soc.c b/soc/nxp/imx/imx8m/m4_mini/soc.c similarity index 100% rename from soc/arm/nxp_imx/mimx8mm6_m4/soc.c rename to soc/nxp/imx/imx8m/m4_mini/soc.c diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/soc.h b/soc/nxp/imx/imx8m/m4_mini/soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8mm6_m4/soc.h rename to soc/nxp/imx/imx8m/m4_mini/soc.h diff --git a/soc/nxp/imx/imx8m/m4_quad/CMakeLists.txt b/soc/nxp/imx/imx8m/m4_quad/CMakeLists.txt new file mode 100644 index 00000000000..2d5bd4a9f30 --- /dev/null +++ b/soc/nxp/imx/imx8m/m4_quad/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (c) 2021, Kwon Tae-young +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c + ) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/pinctrl_soc.h b/soc/nxp/imx/imx8m/m4_quad/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8mq6_m4/pinctrl_soc.h rename to soc/nxp/imx/imx8m/m4_quad/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/soc.c b/soc/nxp/imx/imx8m/m4_quad/soc.c similarity index 100% rename from soc/arm/nxp_imx/mimx8mq6_m4/soc.c rename to soc/nxp/imx/imx8m/m4_quad/soc.c diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/soc.h b/soc/nxp/imx/imx8m/m4_quad/soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8mq6_m4/soc.h rename to soc/nxp/imx/imx8m/m4_quad/soc.h diff --git a/soc/nxp/imx/imx8m/m7/CMakeLists.txt b/soc/nxp/imx/imx8m/m7/CMakeLists.txt new file mode 100644 index 00000000000..8b2c33a6294 --- /dev/null +++ b/soc/nxp/imx/imx8m/m7/CMakeLists.txt @@ -0,0 +1,21 @@ +# +# Copyright (c) 2021, Laird Connectivity +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_include_directories(.) + +zephyr_sources( + soc.c + mpu_regions.c +) + +if(CONFIG_OPENAMP_RSC_TABLE) + zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) + zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") +endif() + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/linker.ld b/soc/nxp/imx/imx8m/m7/linker.ld similarity index 100% rename from soc/arm/nxp_imx/mimx8ml8_m7/linker.ld rename to soc/nxp/imx/imx8m/m7/linker.ld diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/mpu_regions.c b/soc/nxp/imx/imx8m/m7/mpu_regions.c similarity index 100% rename from soc/arm/nxp_imx/mimx8ml8_m7/mpu_regions.c rename to soc/nxp/imx/imx8m/m7/mpu_regions.c diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/pinctrl_soc.h b/soc/nxp/imx/imx8m/m7/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8ml8_m7/pinctrl_soc.h rename to soc/nxp/imx/imx8m/m7/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/soc.c b/soc/nxp/imx/imx8m/m7/soc.c similarity index 100% rename from soc/arm/nxp_imx/mimx8ml8_m7/soc.c rename to soc/nxp/imx/imx8m/m7/soc.c diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/soc.h b/soc/nxp/imx/imx8m/m7/soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8ml8_m7/soc.h rename to soc/nxp/imx/imx8m/m7/soc.h diff --git a/soc/nxp/imx/imx8ulp/CMakeLists.txt b/soc/nxp/imx/imx8ulp/CMakeLists.txt new file mode 100644 index 00000000000..55a73218273 --- /dev/null +++ b/soc/nxp/imx/imx8ulp/CMakeLists.txt @@ -0,0 +1,23 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX8ULP_ADSP) + zephyr_include_directories(adsp) + add_subdirectory(adsp) + + # west sign + + # See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt + add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + ) + + add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} + ) + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/nxp/imx/imx8ulp/Kconfig b/soc/nxp/imx/imx8ulp/Kconfig new file mode 100644 index 00000000000..5bee7c22107 --- /dev/null +++ b/soc/nxp/imx/imx8ulp/Kconfig @@ -0,0 +1,11 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX8ULP_ADSP + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + select ATOMIC_OPERATIONS_BUILTIN + select GEN_ISR_TABLES + select XTENSA_SMALL_VECTOR_TABLE_ENTRY diff --git a/soc/nxp/imx/imx8ulp/Kconfig.defconfig b/soc/nxp/imx/imx8ulp/Kconfig.defconfig new file mode 100644 index 00000000000..424892563af --- /dev/null +++ b/soc/nxp/imx/imx8ulp/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX8ULP + +if SOC_MIMX8ULP_ADSP + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 528000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 50000 + +config DCACHE_LINE_SIZE + default 128 + +config GEN_IRQ_VECTOR_TABLE + default n + +config CACHE_MANAGEMENT + default y + +config SMP + default n + +config XTENSA_TIMER + default y + +config KERNEL_ENTRY + default "__start" + +config MULTI_LEVEL_INTERRUPTS + default n + +config 2ND_LEVEL_INTERRUPTS + default n + +# To prevent test uses TEST_LOGGING_MINIMAL +config TEST_LOGGING_DEFAULTS + default n + depends on TEST + +endif # SOC_MIMX8ULP_ADSP + +endif # SOC_SERIES_IMX8ULP diff --git a/soc/nxp/imx/imx8ulp/Kconfig.soc b/soc/nxp/imx/imx8ulp/Kconfig.soc new file mode 100644 index 00000000000..b7d4cadef7c --- /dev/null +++ b/soc/nxp/imx/imx8ulp/Kconfig.soc @@ -0,0 +1,26 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX8ULP + bool + select SOC_FAMILY_NXP_IMX + +config SOC_SERIES + default "imx8ulp" if SOC_SERIES_IMX8ULP + +config SOC_MIMX8ULP + bool + select SOC_SERIES_IMX8ULP + +config SOC + default "imx8ulp" if SOC_MIMX8ULP + +config SOC_MIMX8ULP_ADSP + bool + select SOC_MIMX8ULP + help + Enable support for NXP i.MX 8ULP Audio DSP + +config SOC_TOOLCHAIN_NAME + string + default "nxp_imx8ulp_adsp" if SOC_MIMX8ULP_ADSP diff --git a/soc/nxp/imx/imx8ulp/adsp/CMakeLists.txt b/soc/nxp/imx/imx8ulp/adsp/CMakeLists.txt new file mode 100644 index 00000000000..a91c5991412 --- /dev/null +++ b/soc/nxp/imx/imx8ulp/adsp/CMakeLists.txt @@ -0,0 +1,6 @@ +# NXP SoC family CMake file +# +# Copyright (c) 2021, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) diff --git a/soc/xtensa/nxp_adsp/imx8ulp/include/_soc_inthandlers.h b/soc/nxp/imx/imx8ulp/adsp/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8ulp/include/_soc_inthandlers.h rename to soc/nxp/imx/imx8ulp/adsp/_soc_inthandlers.h diff --git a/soc/nxp/imx/imx8ulp/adsp/include/adsp/cache.h b/soc/nxp/imx/imx8ulp/adsp/include/adsp/cache.h new file mode 100644 index 00000000000..067c0890140 --- /dev/null +++ b/soc/nxp/imx/imx8ulp/adsp/include/adsp/cache.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __COMMON_ADSP_CACHE_H__ +#define __COMMON_ADSP_CACHE_H__ + +#include + +#endif diff --git a/soc/nxp/imx/imx8ulp/adsp/include/adsp/io.h b/soc/nxp/imx/imx8ulp/adsp/include/adsp/io.h new file mode 100644 index 00000000000..3d1f0ed98d5 --- /dev/null +++ b/soc/nxp/imx/imx8ulp/adsp/include/adsp/io.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INCLUDE_IO__ +#define __INCLUDE_IO__ + +#include +#include +#include +#include + +static inline uint32_t io_reg_read(uint32_t reg) +{ + return sys_read32(reg); +} + +static inline void io_reg_write(uint32_t reg, uint32_t val) +{ + sys_write32(val, reg); +} + +static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, + uint32_t value) +{ + io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); +} + +static inline uint16_t io_reg_read16(uint32_t reg) +{ + return sys_read16(reg); +} + +static inline void io_reg_write16(uint32_t reg, uint16_t val) +{ + sys_write16(val, reg); +} + +#endif diff --git a/soc/nxp/imx/imx8ulp/adsp/include/soc.h b/soc/nxp/imx/imx8ulp/adsp/include/soc.h new file mode 100644 index 00000000000..89ee9d96a52 --- /dev/null +++ b/soc/nxp/imx/imx8ulp/adsp/include/soc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include + +#ifndef __INC_IMX_SOC_H +#define __INC_IMX_SOC_H + +/* Macros related to interrupt handling */ +#define XTENSA_IRQ_NUM_SHIFT 0 +#define XTENSA_IRQ_NUM_MASK 0xff + +/* + * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00. + * + * 1. Peripheral Register bit offset. + */ +#define XTENSA_IRQ_NUMBER(_irq) \ + ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) + +extern void z_soc_irq_enable(uint32_t irq); +extern void z_soc_irq_disable(uint32_t irq); +extern int z_soc_irq_is_enabled(unsigned int irq); + +#endif /* __INC_IMX_SOC_H */ diff --git a/soc/xtensa/nxp_adsp/imx8ulp/linker.ld b/soc/nxp/imx/imx8ulp/adsp/linker.ld similarity index 100% rename from soc/xtensa/nxp_adsp/imx8ulp/linker.ld rename to soc/nxp/imx/imx8ulp/adsp/linker.ld diff --git a/soc/xtensa/nxp_adsp/imx8ulp/include/memory.h b/soc/nxp/imx/imx8ulp/adsp/memory.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8ulp/include/memory.h rename to soc/nxp/imx/imx8ulp/adsp/memory.h diff --git a/soc/nxp/imx/imx8x/CMakeLists.txt b/soc/nxp/imx/imx8x/CMakeLists.txt new file mode 100644 index 00000000000..af445cb9e57 --- /dev/null +++ b/soc/nxp/imx/imx8x/CMakeLists.txt @@ -0,0 +1,27 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX8QXP_ADSP) + zephyr_include_directories(adsp) + add_subdirectory(adsp) + + zephyr_sources( + adsp/pinctrl_soc.h + ) + + # west sign + + # See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt + add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + ) + + add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} + ) + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/nxp/imx/imx8x/Kconfig b/soc/nxp/imx/imx8x/Kconfig new file mode 100644 index 00000000000..b5c9a4e446e --- /dev/null +++ b/soc/nxp/imx/imx8x/Kconfig @@ -0,0 +1,15 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX8QXP_ADSP + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + select ATOMIC_OPERATIONS_BUILTIN + select GEN_ISR_TABLES + select XTENSA_SMALL_VECTOR_TABLE_ENTRY + select HAS_MCUX + +config MCUX_CORE_SUFFIX + default "_dsp" if SOC_MIMX8QXP_ADSP diff --git a/soc/nxp/imx/imx8x/Kconfig.defconfig b/soc/nxp/imx/imx8x/Kconfig.defconfig new file mode 100644 index 00000000000..2e3699d9532 --- /dev/null +++ b/soc/nxp/imx/imx8x/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX8X + +if SOC_MIMX8QXP_ADSP + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 640000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 50000 + +config DCACHE_LINE_SIZE + default 128 + +config GEN_IRQ_VECTOR_TABLE + default n + +config CACHE_MANAGEMENT + default y + +config SMP + default n + +config XTENSA_TIMER + default y + +config KERNEL_ENTRY + default "__start" + +config MULTI_LEVEL_INTERRUPTS + default n + +config 2ND_LEVEL_INTERRUPTS + default n + +# To prevent test uses TEST_LOGGING_MINIMAL +config TEST_LOGGING_DEFAULTS + default n + depends on TEST + +endif # SOC_MIMX8QXP_ADSP + +endif # SOC_SERIES_IMX8X diff --git a/soc/nxp/imx/imx8x/Kconfig.soc b/soc/nxp/imx/imx8x/Kconfig.soc new file mode 100644 index 00000000000..dc3c3de187f --- /dev/null +++ b/soc/nxp/imx/imx8x/Kconfig.soc @@ -0,0 +1,36 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX8X + bool + select SOC_FAMILY_NXP_IMX + +config SOC_SERIES + default "imx8x" if SOC_SERIES_IMX8X + +config SOC_MIMX8QXP + bool + select SOC_SERIES_IMX8X + +config SOC + default "mimx8qx6" if SOC_MIMX8QXP + +config SOC_MIMX8QXP_ADSP + bool + select SOC_MIMX8QXP + help + Enable support for NXP i.MX 8QXP Audio DSP + +config SOC_TOOLCHAIN_NAME + string + default "nxp_imx_adsp" if SOC_MIMX8QXP_ADSP + +config SOC_PART_NUMBER_MIMX8QX6AVLFZ + bool + +config SOC_PART_NUMBER_MIMX8QX6CVLDZ + bool + +config SOC_PART_NUMBER + default "MIMX8QX6AVLFZ" if SOC_PART_NUMBER_MIMX8QX6AVLFZ + default "MIMX8QX6CVLDZ" if SOC_PART_NUMBER_MIMX8QX6CVLDZ diff --git a/soc/nxp/imx/imx8x/adsp/CMakeLists.txt b/soc/nxp/imx/imx8x/adsp/CMakeLists.txt new file mode 100644 index 00000000000..a91c5991412 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/CMakeLists.txt @@ -0,0 +1,6 @@ +# NXP SoC family CMake file +# +# Copyright (c) 2021, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) diff --git a/soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h b/soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h new file mode 100644 index 00000000000..daa9cfe668b --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + * + * Functions here are designed to produce efficient code to + * search an Xtensa bitmask of interrupts, inspecting only those bits + * declared to be associated with a given interrupt level. Each + * dispatcher will handle exactly one flagged interrupt, in numerical + * order (low bits first) and will return a mask of that bit that can + * then be cleared by the calling code. Unrecognized bits for the + * level will invoke an error handler. + */ + +#include +#include +#include + +#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif + +static inline int _xtensa_handle_one_int1(unsigned int mask) +{ + int irq; + + if (mask & BIT(8)) { + mask = BIT(8); + irq = 8; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int2(unsigned int mask) +{ + int irq; + int i = 0; + + mask &= XCHAL_INTLEVEL2_MASK; + for (i = 0; i <= 31; i++) + if (mask & BIT(i)) { + mask = BIT(i); + irq = i; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int3(unsigned int mask) +{ + int irq; + + if (mask & BIT(1)) { + mask = BIT(1); + irq = 1; + goto handle_irq; + } + if (mask & BIT(3)) { + mask = BIT(3); + irq = 3; + goto handle_irq; + } + if (mask & BIT(31)) { + mask = BIT(31); + irq = 31; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int5(unsigned int mask) +{ + int irq; + + if (mask & BIT(0)) { + mask = BIT(0); + irq = 0; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int0(unsigned int mask) +{ + return 0; +} + +static inline int _xtensa_handle_one_int4(unsigned int mask) +{ + return 0; +} + +static inline int _xtensa_handle_one_int6(unsigned int mask) +{ + return 0; +} + +static inline int _xtensa_handle_one_int7(unsigned int mask) +{ + return 0; +} diff --git a/soc/nxp/imx/imx8x/adsp/include/adsp/cache.h b/soc/nxp/imx/imx8x/adsp/include/adsp/cache.h new file mode 100644 index 00000000000..067c0890140 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/include/adsp/cache.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __COMMON_ADSP_CACHE_H__ +#define __COMMON_ADSP_CACHE_H__ + +#include + +#endif diff --git a/soc/nxp/imx/imx8x/adsp/include/adsp/io.h b/soc/nxp/imx/imx8x/adsp/include/adsp/io.h new file mode 100644 index 00000000000..3d1f0ed98d5 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/include/adsp/io.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INCLUDE_IO__ +#define __INCLUDE_IO__ + +#include +#include +#include +#include + +static inline uint32_t io_reg_read(uint32_t reg) +{ + return sys_read32(reg); +} + +static inline void io_reg_write(uint32_t reg, uint32_t val) +{ + sys_write32(val, reg); +} + +static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, + uint32_t value) +{ + io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); +} + +static inline uint16_t io_reg_read16(uint32_t reg) +{ + return sys_read16(reg); +} + +static inline void io_reg_write16(uint32_t reg, uint16_t val) +{ + sys_write16(val, reg); +} + +#endif diff --git a/soc/nxp/imx/imx8x/adsp/include/soc.h b/soc/nxp/imx/imx8x/adsp/include/soc.h new file mode 100644 index 00000000000..89ee9d96a52 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/include/soc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include + +#ifndef __INC_IMX_SOC_H +#define __INC_IMX_SOC_H + +/* Macros related to interrupt handling */ +#define XTENSA_IRQ_NUM_SHIFT 0 +#define XTENSA_IRQ_NUM_MASK 0xff + +/* + * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00. + * + * 1. Peripheral Register bit offset. + */ +#define XTENSA_IRQ_NUMBER(_irq) \ + ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) + +extern void z_soc_irq_enable(uint32_t irq); +extern void z_soc_irq_disable(uint32_t irq); +extern int z_soc_irq_is_enabled(unsigned int irq); + +#endif /* __INC_IMX_SOC_H */ diff --git a/soc/nxp/imx/imx8x/adsp/linker.ld b/soc/nxp/imx/imx8x/adsp/linker.ld new file mode 100644 index 00000000000..52d3a46b238 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/linker.ld @@ -0,0 +1,517 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * Linker script for the NXP i.MX8 platform + */ + +OUTPUT_ARCH(xtensa) + +#include +#include +#include +#include + +#include +#include + +PROVIDE(__memctl_default = 0x00000000); +PROVIDE(_MemErrorHandler = 0x00000000); + +#define RAMABLE_REGION sdram0 :sdram0_phdr +#define ROMABLE_REGION sdram0 :sdram0_phdr + +MEMORY +{ + vector_reset_text : + org = XCHAL_RESET_VECTOR0_PADDR_IRAM, + len = MEM_RESET_TEXT_SIZE + vector_reset_lit : + org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE, + len = MEM_RESET_LIT_SIZE + vector_base_text : + org = XCHAL_VECBASE_RESET_PADDR_IRAM, + len = MEM_VECBASE_LIT_SIZE + vector_int2_lit : + org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_int2_text : + org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_int3_lit : + org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_int3_text : + org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_int4_lit : + org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_int4_text : + org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_int5_lit : + org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_int5_text : + org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_kernel_lit : + org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_kernel_text : + org = XCHAL_KERNEL_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_user_lit : + org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_user_text : + org = XCHAL_USER_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_double_lit : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_double_text : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + iram_text_start : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE, + len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE) + sdram0 : + org = SDRAM0_BASE, + len = SDRAM0_SIZE + sdram1 : + org = SDRAM1_BASE + SOF_MAILBOX_SIZE, + len = SDRAM1_SIZE - SOF_MAILBOX_SIZE +#ifdef CONFIG_GEN_ISR_TABLES + IDT_LIST : + org = IDT_BASE, + len = IDT_SIZE +#endif + + static_uuid_entries_seg (!ari) : + org = UUID_ENTRY_ELF_BASE, + len = UUID_ENTRY_ELF_SIZE + static_log_entries_seg (!ari) : + org = LOG_ENTRY_ELF_BASE, + len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE +} + +PHDRS +{ + vector_reset_text_phdr PT_LOAD; + vector_reset_lit_phdr PT_LOAD; + vector_base_text_phdr PT_LOAD; + vector_base_lit_phdr PT_LOAD; + vector_int2_text_phdr PT_LOAD; + vector_int2_lit_phdr PT_LOAD; + vector_int3_text_phdr PT_LOAD; + vector_int3_lit_phdr PT_LOAD; + vector_int4_text_phdr PT_LOAD; + vector_int4_lit_phdr PT_LOAD; + vector_int5_text_phdr PT_LOAD; + vector_int5_lit_phdr PT_LOAD; + vector_kernel_text_phdr PT_LOAD; + vector_kernel_lit_phdr PT_LOAD; + vector_user_text_phdr PT_LOAD; + vector_user_lit_phdr PT_LOAD; + vector_double_text_phdr PT_LOAD; + vector_double_lit_phdr PT_LOAD; + iram_text_start_phdr PT_LOAD; + sdram0_phdr PT_LOAD; + sdram1_phdr PT_LOAD; + static_uuid_entries_phdr PT_NOTE; + static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; +} + +_rom_store_table = 0; + +PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR); + +ENTRY(CONFIG_KERNEL_ENTRY) + +/* Various memory-map dependent cache attribute settings: */ +_memmap_cacheattr_wb_base = 0x44024000; +_memmap_cacheattr_wt_base = 0x11021000; +_memmap_cacheattr_bp_base = 0x22022000; +_memmap_cacheattr_unused_mask = 0x00F00FFF; +_memmap_cacheattr_wb_trapnull = 0x4422422F; +_memmap_cacheattr_wba_trapnull = 0x4422422F; +_memmap_cacheattr_wbna_trapnull = 0x25222222; +_memmap_cacheattr_wt_trapnull = 0x1122122F; +_memmap_cacheattr_bp_trapnull = 0x2222222F; +_memmap_cacheattr_wb_strict = 0x44F24FFF; +_memmap_cacheattr_wt_strict = 0x11F21FFF; +_memmap_cacheattr_bp_strict = 0x22F22FFF; +_memmap_cacheattr_wb_allvalid = 0x44224222; +_memmap_cacheattr_wt_allvalid = 0x11221222; +_memmap_cacheattr_bp_allvalid = 0x22222222; +/* + * Every 512M in 4GB space has dedicate cache attribute. + * 1: write through + * 2: cache bypass + * 4: write back + * F: invalid access + */ +_memmap_cacheattr_imx8_wt_allvalid = 0x22212222; +PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_imx8_wt_allvalid); + +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) + +SECTIONS +{ + +#include + .ResetVector.text : ALIGN(4) + { + _ResetVector_text_start = ABSOLUTE(.); + KEEP (*(.ResetVector.text)) + _ResetVector_text_end = ABSOLUTE(.); + } >vector_reset_text :vector_reset_text_phdr + + .ResetVector.literal : ALIGN(4) + { + _ResetVector_literal_start = ABSOLUTE(.); + *(.ResetVector.literal) + _ResetVector_literal_end = ABSOLUTE(.); + } >vector_reset_lit :vector_reset_lit_phdr + + .WindowVectors.text : ALIGN(4) + { + _WindowVectors_text_start = ABSOLUTE(.); + KEEP (*(.WindowVectors.text)) + _WindowVectors_text_end = ABSOLUTE(.); + } >vector_base_text :vector_base_text_phdr + + .Level2InterruptVector.literal : ALIGN(4) + { + _Level2InterruptVector_literal_start = ABSOLUTE(.); + *(.Level2InterruptVector.literal) + _Level2InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int2_lit :vector_int2_lit_phdr + + .Level2InterruptVector.text : ALIGN(4) + { + _Level2InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level2InterruptVector.text)) + _Level2InterruptVector_text_end = ABSOLUTE(.); + } >vector_int2_text :vector_int2_text_phdr + + .Level3InterruptVector.literal : ALIGN(4) + { + _Level3InterruptVector_literal_start = ABSOLUTE(.); + *(.Level3InterruptVector.literal) + _Level3InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int3_lit :vector_int3_lit_phdr + + .Level3InterruptVector.text : ALIGN(4) + { + _Level3InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level3InterruptVector.text)) + _Level3InterruptVector_text_end = ABSOLUTE(.); + } >vector_int3_text :vector_int3_text_phdr + + .DebugExceptionVector.literal : ALIGN(4) + { + _DebugExceptionVector_literal_start = ABSOLUTE(.); + *(.DebugExceptionVector.literal) + _DebugExceptionVector_literal_end = ABSOLUTE(.); + } >vector_int4_lit :vector_int4_lit_phdr + + .DebugExceptionVector.text : ALIGN(4) + { + _DebugExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DebugExceptionVector.text)) + _DebugExceptionVector_text_end = ABSOLUTE(.); + } >vector_int4_text :vector_int4_text_phdr + + .NMIExceptionVector.literal : ALIGN(4) + { + _NMIExceptionVector_literal_start = ABSOLUTE(.); + *(.NMIExceptionVector.literal) + _NMIExceptionVector_literal_end = ABSOLUTE(.); + } >vector_int5_lit :vector_int5_lit_phdr + + .NMIExceptionVector.text : ALIGN(4) + { + _NMIExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.NMIExceptionVector.text)) + _NMIExceptionVector_text_end = ABSOLUTE(.); + } >vector_int5_text :vector_int5_text_phdr + + .KernelExceptionVector.literal : ALIGN(4) + { + _KernelExceptionVector_literal_start = ABSOLUTE(.); + *(.KernelExceptionVector.literal) + _KernelExceptionVector_literal_end = ABSOLUTE(.); + } >vector_kernel_lit :vector_kernel_lit_phdr + + .KernelExceptionVector.text : ALIGN(4) + { + _KernelExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.KernelExceptionVector.text)) + _KernelExceptionVector_text_end = ABSOLUTE(.); + } >vector_kernel_text :vector_kernel_text_phdr + + .UserExceptionVector.literal : ALIGN(4) + { + _UserExceptionVector_literal_start = ABSOLUTE(.); + *(.UserExceptionVector.literal) + _UserExceptionVector_literal_end = ABSOLUTE(.); + } >vector_user_lit :vector_user_lit_phdr + + .UserExceptionVector.text : ALIGN(4) + { + _UserExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.UserExceptionVector.text)) + _UserExceptionVector_text_end = ABSOLUTE(.); + } >vector_user_text :vector_user_text_phdr + + .DoubleExceptionVector.literal : ALIGN(4) + { + _DoubleExceptionVector_literal_start = ABSOLUTE(.); + *(.DoubleExceptionVector.literal) + _DoubleExceptionVector_literal_end = ABSOLUTE(.); + } >vector_double_lit :vector_double_lit_phdr + + .DoubleExceptionVector.text : ALIGN(4) + { + _DoubleExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DoubleExceptionVector.text)) + _DoubleExceptionVector_text_end = ABSOLUTE(.); + } >vector_double_text :vector_double_text_phdr + + .iram.text : ALIGN(4) + { + _stext = .; + _iram_text_start = ABSOLUTE(.); + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + _iram_text_end = ABSOLUTE(.); + } >iram_text_start :iram_text_start_phdr + + .rodata : ALIGN(4) + { + __rodata_region_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + KEEP (*(.xt_except_table)) + KEEP (*(.gcc_except_table .gcc_except_table.*)) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + KEEP (*(.eh_frame)) + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + _bss_table_start = ABSOLUTE(.); + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + __rodata_region_end = ABSOLUTE(.); + } >sdram0 :sdram0_phdr + + .module_init : ALIGN(4) + { + _module_init_start = ABSOLUTE(.); + *(*.initcall) + _module_init_end = ABSOLUTE(.); + } >sdram0 :sdram0_phdr + + .text : ALIGN(4) + { + _stext = .; + __text_region_start = ABSOLUTE(.); + KEEP (*(.ResetVector.text)) + *(.ResetVector.literal) + *(.entry.text) + *(.init.literal) + KEEP(*(.init)) + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.fini.literal) + KEEP(*(.fini)) + *(.gnu.version) + __text_region_end = ABSOLUTE(.); + _etext = .; + } >sdram0 :sdram0_phdr + +#include + + .fw_ready : ALIGN(4) + { + KEEP(*(".fw_ready")); + KEEP (*(.fw_ready_metadata)) + } >sdram0 :sdram0_phdr + + .noinit : ALIGN(4) + { + *(.noinit) + *(.noinit.*) + } >sdram0 :sdram0_phdr + + .data : ALIGN(4) + { + __data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + KEEP(*(.gnu.linkonce.d.*personality*)) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + KEEP(*(.jcr)) + _trace_ctx_start = ABSOLUTE(.); + *(.trace_ctx) + _trace_ctx_end = ABSOLUTE(.); + . = ALIGN(4); + *(.gna_model) + __data_end = ABSOLUTE(.); + . = ALIGN(4096); + } >sdram0 :sdram0_phdr + + .lit4 : ALIGN(4) + { + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + } >sdram0 :sdram0_phdr + +#include + + .bss (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } >sdram0 :sdram0_phdr + + .heap_mem (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _heap_mem_start = ABSOLUTE(.); + *(*.heap_mem) + _heap_mem_end = ABSOLUTE(.); + } >sdram1 :sdram1_phdr + + /* stack */ + _end = ALIGN (8); + PROVIDE(end = ALIGN (8)); + + __stack = SDRAM1_BASE + SDRAM1_SIZE; + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .debug_ranges 0 : { *(.debug_ranges) } + .xtensa.info 0 : { *(.xtensa.info) } + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } +#ifdef CONFIG_GEN_ISR_TABLES +#include +#endif + + .static_uuid_entries (COPY) : ALIGN(1024) + { + *(*.static_uuids) + } > static_uuid_entries_seg :static_uuid_entries_phdr + + .static_log_entries (COPY) : ALIGN(1024) + { + *(*.static_log*) + } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr +} diff --git a/soc/nxp/imx/imx8x/adsp/memory.h b/soc/nxp/imx/imx8x/adsp/memory.h new file mode 100644 index 00000000000..56bac21c780 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/memory.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ +#define ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ + +#define IRAM_RESERVE_HEADER_SPACE 0x400 + +#define IRAM_BASE 0x596f8000 +#define IRAM_SIZE 0x800 + +#define SDRAM0_BASE 0x92400000 +#define SDRAM0_SIZE 0x800000 + +#define SDRAM1_BASE 0x92C00000 +#define SDRAM1_SIZE 0x800000 + +/* The reset vector address in SRAM and its size */ +#define MEM_RESET_TEXT_SIZE 0x2e0 +#define MEM_RESET_LIT_SIZE 0x120 + +/* This is the base address of all the vectors defined in IRAM */ +#define XCHAL_VECBASE_RESET_PADDR_IRAM \ + (IRAM_BASE + IRAM_RESERVE_HEADER_SPACE) + +#define MEM_VECBASE_LIT_SIZE 0x178 + +/* + * EXCEPTIONS and VECTORS + */ +#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x596F8000 + +/* Vector and literal sizes */ +#define MEM_VECT_LIT_SIZE 0x4 +#define MEM_VECT_TEXT_SIZE 0x1C +#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\ + MEM_VECT_LIT_SIZE) + +/* The addresses of the vectors. + * Only the mem_error vector continues to point to its ROM address. + */ +#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C) + +#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C) + +#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC) + +#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC) + +#define XCHAL_KERNEL_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC) + +#define XCHAL_USER_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C) + +#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C) + +/* Location for the intList section which is later used to construct the + * Interrupt Descriptor Table (IDT). This is a bogus address as this + * section will be stripped off in the final image. + */ +#define IDT_BASE (IRAM_BASE + IRAM_SIZE) + +/* size of the Interrupt Descriptor Table (IDT) */ +#define IDT_SIZE 0x2000 + +/* physical DSP addresses */ +#define IRAM_BASE 0x596f8000 +#define IRAM_SIZE 0x800 + +#define DRAM0_BASE 0x596e8000 +#define DRAM0_SIZE 0x8000 + +#define DRAM1_BASE 0x596f0000 +#define DRAM1_SIZE 0x8000 + +#define SDRAM0_BASE 0x92400000 +#define SDRAM0_SIZE 0x800000 + +#define SDRAM1_BASE 0x92C00000 +#define SDRAM1_SIZE 0x800000 + +#define XSHAL_MU13_SIDEB_BYPASS_PADDR 0x5D310000 +#define MU_BASE XSHAL_MU13_SIDEB_BYPASS_PADDR + +#define EDMA0_BASE 0x59200000 +#define EDMA0_SIZE 0x10000 + +#define ESAI_BASE 0x59010000 +#define ESAI_SIZE 0x00010000 + +#define SAI_1_BASE 0x59050000 +#define SAI_1_SIZE 0x00010000 + +#define UUID_ENTRY_ELF_BASE 0x1FFFA000 +#define UUID_ENTRY_ELF_SIZE 0x6000 + +#define LOG_ENTRY_ELF_BASE 0x20000000 +#define LOG_ENTRY_ELF_SIZE 0x2000000 + +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE 0x2000000 + +/* + * The Heap and Stack on i.MX8 are organized like this :- + * + * +--------------------------------------------------------------------------+ + * | Offset | Region | Size | + * +---------------------+----------------+-----------------------------------+ + * | SDRAM_BASE | RO Data | SOF_DATA_SIZE | + * | | Data | | + * | | BSS | | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_END | Stack | SOF_STACK_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_BASE | | | + * +---------------------+----------------+-----------------------------------+ + */ + +#define SRAM_OUTBOX_BASE SDRAM1_BASE +#define SRAM_OUTBOX_SIZE 0x1000 +#define SRAM_OUTBOX_OFFSET 0 + +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x1000 +#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE + +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_DEBUG_SIZE 0x800 +#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE) + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 +#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE) + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 +#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE) + +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#define SRAM_TRACE_SIZE 0x1000 +#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE) + +#define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \ + + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \ + + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE) + +#endif /* ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ */ diff --git a/soc/nxp/imx/imx8x/adsp/pinctrl_soc.h b/soc/nxp/imx/imx8x/adsp/pinctrl_soc.h new file mode 100644 index 00000000000..ac748220b56 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/pinctrl_soc.h @@ -0,0 +1,41 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct pinctrl_soc_pinmux { + uint32_t pad; + uint32_t mux; +}; + +typedef struct pinctrl_soc_pinmux pinctrl_soc_pin_t; + +#define IMX8_PINMUX(n) \ +{ \ + .pad = DT_PROP_BY_IDX(n, pinmux, 0), \ + .mux = DT_PROP_BY_IDX(n, pinmux, 1), \ +}, + +#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx)\ + IMX8_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ + DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_PINMUX) }; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_ */ diff --git a/soc/nxp/imx/imx9/CMakeLists.txt b/soc/nxp/imx/imx9/CMakeLists.txt new file mode 100644 index 00000000000..dc7d1917a16 --- /dev/null +++ b/soc/nxp/imx/imx9/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX9352_A55) + zephyr_include_directories(.) + zephyr_include_directories(a55) + + zephyr_sources_ifdef(CONFIG_ARM_MMU a55/mmu_regions.c) + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/a55/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/nxp/imx/imx9/Kconfig b/soc/nxp/imx/imx9/Kconfig new file mode 100644 index 00000000000..5ea7bed7653 --- /dev/null +++ b/soc/nxp/imx/imx9/Kconfig @@ -0,0 +1,13 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX9352_A55 + select ARM64 + select CPU_CORTEX_A55 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM_REV2 if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + +config MCUX_CORE_SUFFIX + default "_ca55" if SOC_MIMX9352_A55 diff --git a/soc/nxp/imx/imx9/Kconfig.defconfig b/soc/nxp/imx/imx9/Kconfig.defconfig new file mode 100644 index 00000000000..0556f9e915f --- /dev/null +++ b/soc/nxp/imx/imx9/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX9 + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_IMX9 diff --git a/soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.a55 b/soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.a55 new file mode 100644 index 00000000000..f53cc12c0f0 --- /dev/null +++ b/soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.a55 @@ -0,0 +1,27 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX9352_A55 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + int + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 24000000 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif diff --git a/soc/nxp/imx/imx9/Kconfig.soc b/soc/nxp/imx/imx9/Kconfig.soc new file mode 100644 index 00000000000..667e3fc1f0b --- /dev/null +++ b/soc/nxp/imx/imx9/Kconfig.soc @@ -0,0 +1,32 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX9 + bool + select SOC_FAMILY_NXP_IMX + +config SOC_MIMX9352 + bool + select SOC_SERIES_IMX9 + +config SOC_MIMX9352_A55 + bool + select SOC_MIMX9352 + help + NXP i.MX93 A55 + +config SOC_PART_NUMBER_MIMX9352CVUXK + bool + +config SOC_PART_NUMBER_MIMX9352DVUXM + bool + +config SOC_PART_NUMBER + default "MIMX9352CVUXK" if SOC_PART_NUMBER_MIMX9352CVUXK + default "MIMX9352DVUXM" if SOC_PART_NUMBER_MIMX9352DVUXM + +config SOC + default "mimx9352" if SOC_MIMX9352 + +config SOC_SERIES + default "imx9" if SOC_SERIES_IMX9 diff --git a/soc/arm64/nxp_imx/mimx9/linker.ld b/soc/nxp/imx/imx9/a55/linker.ld similarity index 100% rename from soc/arm64/nxp_imx/mimx9/linker.ld rename to soc/nxp/imx/imx9/a55/linker.ld diff --git a/soc/arm64/nxp_imx/mimx9/mmu_regions.c b/soc/nxp/imx/imx9/a55/mmu_regions.c similarity index 100% rename from soc/arm64/nxp_imx/mimx9/mmu_regions.c rename to soc/nxp/imx/imx9/a55/mmu_regions.c diff --git a/soc/arm64/nxp_imx/mimx9/pinctrl_soc.h b/soc/nxp/imx/imx9/pinctrl_soc.h similarity index 100% rename from soc/arm64/nxp_imx/mimx9/pinctrl_soc.h rename to soc/nxp/imx/imx9/pinctrl_soc.h diff --git a/soc/nxp/imx/soc.yml b/soc/nxp/imx/soc.yml new file mode 100644 index 00000000000..c1a4c16b37b --- /dev/null +++ b/soc/nxp/imx/soc.yml @@ -0,0 +1,62 @@ +family: +- name: nxp_imx + series: + - name: imx8 + socs: + - name: mimx8qm6 + cpuclusters: + - name: adsp + - name: a72 + - name: a53 + - name: m4 + - name: imx8x + socs: + - name: mimx8qx6 + cpuclusters: + - name: adsp + - name: a35 + - name: m4 + - name: imx8ulp + socs: + - name: imx8ulp + cpuclusters: + - name: adsp + - name: f1_dsp + - name: a35 + - name: imx8m + socs: + - name: mimx8ml8 + cpuclusters: + - name: adsp + - name: a53 + - name: m7 + - name: mimx8mm6 + cpuclusters: + - name: a53 + - name: m4 + - name: mimx8mn6 + cpuclusters: + - name: a53 + - name: m7 + - name: mimx8mq6 + cpuclusters: + - name: a53 + - name: m4 + - name: imx9 + socs: + - name: mimx9352 + cpuclusters: + - name: a55 + - name: m33 + - name: imx6sx + socs: + - name: mcimx6x + cpuclusters: + - name: a9 + - name: m4 + - name: imx7d + socs: + - name: mcimx7d + cpuclusters: + - name: a7 + - name: m4 diff --git a/soc/nxp/imxrt/CMakeLists.txt b/soc/nxp/imxrt/CMakeLists.txt new file mode 100644 index 00000000000..25cd1b81554 --- /dev/null +++ b/soc/nxp/imxrt/CMakeLists.txt @@ -0,0 +1,42 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) + +zephyr_include_directories(.) +zephyr_include_directories(${SOC_SERIES}) + +zephyr_linker_sources_ifdef(CONFIG_NXP_IMXRT_BOOT_HEADER + ROM_START SORT_KEY 0 boot_header.ld) + +if(CONFIG_SOC_SERIES_IMXRT10XX OR CONFIG_SOC_SERIES_IMXRT11XX) + if(CONFIG_DEVICE_CONFIGURATION_DATA) + set(boot_hdr_dcd_data_section ".boot_hdr.dcd_data") + endif() + zephyr_sources(mpu_regions.c) + zephyr_linker_section_configure( + SECTION .rom_start + INPUT ".boot_hdr.conf" + OFFSET ${CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET} + KEEP + PRIO 10 + ) + zephyr_linker_section_configure( + SECTION .rom_start + INPUT ".boot_hdr.ivt" + ".boot_hdr.data" + ${boot_hdr_dcd_data_section} + OFFSET ${CONFIG_IMAGE_VECTOR_TABLE_OFFSET} + KEEP + PRIO 11 + ) + zephyr_compile_definitions(XIP_EXTERNAL_FLASH) +endif() + +if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMXRT5XX) + zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER SECTIONS usb.ld) +endif() + +if(CONFIG_MEMC) + zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc) +endif() diff --git a/soc/nxp/imxrt/Kconfig b/soc/nxp/imxrt/Kconfig new file mode 100644 index 00000000000..6306520fd38 --- /dev/null +++ b/soc/nxp/imxrt/Kconfig @@ -0,0 +1,190 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_IMXRT + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_PM + +if SOC_FAMILY_NXP_IMXRT + +# Source series Kconfig files first, so SOCs +# can override the defaults given here +rsource "*/Kconfig" + +# Used for default value in FLASH_MCUX_FLEXSPI_XIP +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi +# Macros to shorten Kconfig definitions +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +config FLASH_MCUX_FLEXSPI_XIP + bool "MCUX FlexSPI flash access with xip" + default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) + select XIP + help + Allows for the soc to safely initialize the clocks for the + FlexSpi when planning to execute code in FlexSpi Memory. + +if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + prompt "FlexSPI drivers relocation target" + default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM + help + Select the location to run the FlexSPI drivers when using + the flash API. + +config FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM + bool "ITCM" + select CODE_DATA_RELOCATION + +config FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM + bool "RAM" + select CODE_DATA_RELOCATION_SRAM + +endchoice + +config FLASH_MCUX_FLEXSPI_XIP_MEM + string + default "ITCM" if FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM + default "RAM" if FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM + +endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +# Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig +# should be set elsewhere, since the determination of which SOC core +# requires the boot header is SOC specific. +config NXP_IMXRT_BOOT_HEADER + bool "Boot header" + default y + depends on !(BOOTLOADER_MCUBOOT || SECOND_CORE_MCUX) + help + Enable data structures required by the boot ROM to boot the + application from an external flash device. + +if NXP_IMXRT_BOOT_HEADER + +choice BOOT_DEVICE + prompt "Boot device" + default BOOT_FLEXSPI_NOR + +config BOOT_FLEXSPI_NOR + bool "FlexSPI serial NOR" + depends on HAS_MCUX_FLEXSPI + +config BOOT_FLEXSPI_NAND + bool "FlexSPI serial NAND" + depends on HAS_MCUX_FLEXSPI + +config BOOT_SEMC_NOR + bool "SEMC parallel NOR" + depends on HAS_MCUX_SEMC + +config BOOT_SEMC_NAND + bool "SEMC parallel NAND" + depends on HAS_MCUX_SEMC + +endchoice # BOOT_DEVICE + +config FLEXSPI_CONFIG_BLOCK_OFFSET + hex "FlexSPI config block offset" + default 0x400 if SOC_SERIES_IMXRT5XX || SOC_SERIES_IMXRT6XX + default 0x0 if BOOT_FLEXSPI_NOR + help + FlexSPI configuration block consists of parameters regarding specific + flash devices including read command sequence, quad mode enablement + sequence (optional), etc. The boot ROM expects FlexSPI configuration + parameter to be presented in serial nor flash. + +config IMAGE_VECTOR_TABLE_OFFSET + hex "Image vector table offset" + default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR + default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND + help + The Image Vector Table (IVT) provides the boot ROM with pointers to + the application entry point and device configuration data. The boot + ROM requires a fixed IVT offset for each type of boot device. + +config DEVICE_CONFIGURATION_DATA + bool "Device configuration data" + help + Device configuration data (DCD) provides a sequence of commands to + the boot ROM to initialize components such as an SDRAM. This is + useful if your application expects components like SDRAM to be + initialized at boot time. + + +endif # NXP_IMXRT_BOOT_HEADER + +config NXP_IMX_EXTERNAL_SDRAM + bool "Allow access to external SDRAM region" + help + Enable access to external SDRAM region managed by the SEMC. This + setting should be enabled when the application uses SDRAM, or + an MPU region will be defined to disable cached access to the + SDRAM memory space. + +config NXP_IMX_RT_ROM_RAMLOADER + depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMXRT_BOOT_HEADER + # Required so that debugger will load image to correct offset + select BUILD_OUTPUT_HEX + bool "Create output image that IMX RT ROM can load from FlexSPI to ram" + help + Builds an output image that the IMX RT BootROM can load from the + FlexSPI boot device into RAM region. The image will be loaded + from FLEXSPI into the region specified by `zephyr,flash` node. + +# Setup LMA adjustment if using the RAMLOADER feature of ROM +FLASH_CHOSEN := zephyr,flash +FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) +FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) +config BUILD_OUTPUT_ADJUST_LMA + default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER + +config SECOND_CORE_MCUX + bool "Dual core operation on the RT11xx series" + depends on SOC_SERIES_IMXRT11XX + help + Indicates the second core will be enabled, and the part will run + in dual core mode. Enables dual core operation on the RT11xx series, + by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU. + The M4 image will be loaded from flash into RAM based off a + generated header specifying the VMA and LMA of each memory section + to load + + +config FLEXSPI_CONFIG_BLOCK_OFFSET + hex + default 0x400 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + +if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + +config PM_MCUX_GPC + bool "MCUX general power controller driver" + +config PM_MCUX_DCDC + bool "MCUX dcdc converter module driver" + +config PM_MCUX_PMU + bool "MCUX power management unit driver" + +config DCDC_VALUE + hex "DCDC value for VDD_SOC" + +config INIT_ARM_PLL + bool "Initialize ARM PLL" + +config INIT_VIDEO_PLL + bool "Initialize Video PLL" + +config INIT_ENET_PLL + bool + help + If y, the Ethernet PLL is initialized. Always enabled on e.g. + MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection + for MIMXRT1021"). + +endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + +endif # SOC_FAMILY_NXP_IMXRT diff --git a/soc/nxp/imxrt/Kconfig.defconfig b/soc/nxp/imxrt/Kconfig.defconfig new file mode 100644 index 00000000000..36f048c7f3c --- /dev/null +++ b/soc/nxp/imxrt/Kconfig.defconfig @@ -0,0 +1,152 @@ +# Copyright 2017-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NXP_IMXRT + +# Source series Kconfig files first, so SOCs +# can override the defaults given here +rsource "*/Kconfig.defconfig" + +if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + +config SERIAL_INIT_PRIORITY + default 55 if SERIAL + depends on SERIAL + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +config ADC_MCUX_12B1MSPS_SAR + default y if HAS_MCUX_12B1MSPS_SAR + depends on ADC + +config LOG_BACKEND_SWO_FREQ_HZ + default 7500000 + depends on LOG_BACKEND_SWO + +# set the tick per sec as a divider of the GPT clock source +config SYS_CLOCK_TICKS_PER_SEC + default 4096 if MCUX_GPT_TIMER + +DT_SYSCLK_PATH := $(dt_nodelabel_path,sysclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_SYSCLK_PATH),clock-frequency) if SOC_SERIES_IMXRT10XX && CORTEX_M_SYSTICK + default 32768 if MCUX_GPT_TIMER + +# Disable systick if using MCUX_GPT_TIMER, as they will conflict +config CORTEX_M_SYSTICK + default n if MCUX_GPT_TIMER + +config PM_MCUX_GPC + default y if HAS_MCUX_GPC + depends on SOC_SERIES_IMXRT11XX && PM + +# Don't allow SOC to sleep after tests complete when PM is enabled +config ZTEST_NO_YIELD + default y if (ZTEST && PM) + +if SOC_SERIES_IMXRT10XX && PM + +config CODE_DATA_RELOCATION + default y + +config PM_MCUX_GPC + default y if HAS_MCUX_GPC + +config PM_MCUX_DCDC + default y if HAS_MCUX_DCDC + +config PM_MCUX_PMU + default y if HAS_MCUX_PMU + +endif # SOC_SERIES_IMXRT10XX && PM + +if ETH_NXP_ENET + +config SYSTEM_WORKQUEUE_STACK_SIZE + default 1560 + +endif # ETH_NXP_ENET + +config MEMC + default y + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_EHCI +endchoice + +DT_CHOSEN_Z_DTCM := zephyr,dtcm + +choice SEGGER_RTT_SECTION + default SEGGER_RTT_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) + depends on USE_SEGGER_RTT +endchoice + +choice SEGGER_SYSVIEW_SECTION + default SEGGER_SYSVIEW_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) + depends on SEGGER_SYSTEMVIEW +endchoice + +# +# MBEDTLS is larger but much faster than TinyCrypt so choose wisely +# +config MBEDTLS +#config TINYCRYPT + default y if CSPRNG_ENABLED + depends on ENTROPY_GENERATOR + +if MBEDTLS +# +# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than +# what the ztest_thread_stack defaults to. +# +config TEST_EXTRA_STACK_SIZE + int + default 1024 +endif # MBEDTLS + +# Enable cache management features when using M7 core, since these parts +# have L1 instruction and data caches that should be enabled at boot +config CACHE_MANAGEMENT + default y if CPU_CORTEX_M7 + +endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + +# Logic to set flash size for all IMXRT parts +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi + +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) +DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(DT_FLASH_PARENT_IS_FLEXSPI) + +config FLASH_SIZE + default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ + if $(DT_FLASH_HAS_SIZE_PROP) + +if FLASH_MCUX_FLEXSPI_XIP + +# Avoid RWW hazards by defaulting logging to disabled +choice FLASH_LOG_LEVEL_CHOICE + default FLASH_LOG_LEVEL_OFF +endchoice + +choice MEMC_LOG_LEVEL_CHOICE + default MEMC_LOG_LEVEL_OFF +endchoice + +endif + +endif # SOC_FAMILY_NXP_IMXRT diff --git a/soc/nxp/imxrt/Kconfig.soc b/soc/nxp/imxrt/Kconfig.soc new file mode 100644 index 00000000000..a12e7f5917e --- /dev/null +++ b/soc/nxp/imxrt/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_IMXRT + bool + +config SOC_FAMILY + default "nxp_imxrt" if SOC_FAMILY_NXP_IMXRT + +rsource "*/Kconfig.soc" diff --git a/soc/nxp/imxrt/boot_header.ld b/soc/nxp/imxrt/boot_header.ld new file mode 100644 index 00000000000..e46fa5789e3 --- /dev/null +++ b/soc/nxp/imxrt/boot_header.ld @@ -0,0 +1,21 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET; +#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) +KEEP(*(.boot_hdr.conf)) +#endif +#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) +KEEP(*(.flash_conf)) +#endif +. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; +KEEP(*(.boot_hdr.ivt)) +#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) +KEEP(*(.boot_hdr.data)) +#ifdef CONFIG_DEVICE_CONFIGURATION_DATA + KEEP(*(.boot_hdr.dcd_data)) +#endif /* CONFIG_DEVICE_CONFIGURATION_DATA */ +#endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */ diff --git a/soc/arm/nxp_imx/rt/flexspi_nor_config.h b/soc/nxp/imxrt/flexspi_nor_config.h similarity index 99% rename from soc/arm/nxp_imx/rt/flexspi_nor_config.h rename to soc/nxp/imxrt/flexspi_nor_config.h index 3eac1ce548c..34ce949936f 100644 --- a/soc/arm/nxp_imx/rt/flexspi_nor_config.h +++ b/soc/nxp/imxrt/flexspi_nor_config.h @@ -91,7 +91,7 @@ enum { kFlexSpiSerialClk_133MHz = 7, }; #elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052) || \ - defined(CONFIG_SOC_SERIES_IMX_RT11XX) + defined(CONFIG_SOC_SERIES_IMXRT11XX) enum { kFlexSpiSerialClk_30MHz = 1, kFlexSpiSerialClk_50MHz = 2, diff --git a/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt new file mode 100644 index 00000000000..5eb0d46c0f3 --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt @@ -0,0 +1,27 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) + +if(CONFIG_PM) + zephyr_sources(power.c) + zephyr_code_relocate(FILES power.c LOCATION ITCM_TEXT) + if(CONFIG_SOC_MIMXRT1064) + zephyr_sources(lpm_rt1064.c) + zephyr_code_relocate(FILES lpm_rt1064 LOCATION ITCM_TEXT) + endif() +endif() + +if(CONFIG_MEMC_MCUX_FLEXSPI) + zephyr_sources(flexspi.c) + if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) + zephyr_code_relocate(FILES flexspi.c LOCATION ITCM_TEXT) + endif() +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imxrt/imxrt10xx/Kconfig b/soc/nxp/imxrt/imxrt10xx/Kconfig new file mode 100644 index 00000000000..7884383b3a6 --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/Kconfig @@ -0,0 +1,150 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT10XX + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select PLATFORM_SPECIFIC_INIT + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select ARM + select CLOCK_CONTROL + select HAS_MCUX + select HAS_MCUX_CACHE + select HAS_MCUX_12B1MSPS_SAR if !SOC_MIMXRT1042 + select HAS_MCUX_CCM if !SOC_MIMXRT1042 + select HAS_MCUX_FLEXSPI + select HAS_MCUX_IGPIO + select HAS_MCUX_LPI2C if !SOC_MIMXRT1042 + select HAS_MCUX_LPSPI if !SOC_MIMXRT1042 + select HAS_MCUX_LPUART if !SOC_MIMXRT1042 + select HAS_MCUX_GPT if !SOC_MIMXRT1042 + select HAS_MCUX_TRNG if !SOC_MIMXRT1042 + select HAS_MCUX_EDMA + select HAS_MCUX_GPC + select HAS_MCUX_IOMUXC + select HAS_MCUX_PMU + select HAS_MCUX_DCDC + select HAS_MCUX_USB_EHCI + select HAS_SWO + +config SOC_MIMXRT1011 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select INIT_ENET_PLL + +config SOC_MIMXRT1015 + select CPU_HAS_FPU + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ENET_PLL + +config SOC_MIMXRT1021 + select HAS_MCUX_ENET + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ENET_PLL + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_FLEXCAN + select HAS_MCUX_PWM + +config SOC_MIMXRT1024 + select HAS_MCUX_ENET + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ENET_PLL + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_FLEXCAN + select HAS_MCUX_SRC + +config SOC_MIMXRT1042 + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + +config SOC_MIMXRT1051 + select HAS_MCUX_ENET + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_CSI + select HAS_MCUX_FLEXCAN + +config SOC_MIMXRT1052 + select HAS_MCUX_ELCDIF + select HAS_MCUX_ENET + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF + select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_CSI + select HAS_MCUX_FLEXCAN + select HAS_MCUX_PWM + select HAS_MCUX_SRC + select HAS_MCUX_XBARA + +config SOC_MIMXRT1061 + select HAS_MCUX_ENET + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_CSI + select HAS_MCUX_FLEXCAN + +config SOC_MIMXRT1062 + select HAS_MCUX_ELCDIF + select HAS_MCUX_ENET + select HAS_MCUX_PWM + select HAS_MCUX_QTMR + select HAS_MCUX_SEMC + select HAS_MCUX_SNVS + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF + select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_CSI + select HAS_MCUX_FLEXCAN + select HAS_MCUX_I2S + select HAS_MCUX_ADC_ETC + select HAS_MCUX_SRC + select HAS_MCUX_XBARA + +config SOC_MIMXRT1064 + select HAS_MCUX_ELCDIF + select HAS_MCUX_ENET + select HAS_MCUX_PWM + select HAS_MCUX_QTMR + select HAS_MCUX_SEMC + select HAS_MCUX_SNVS + select HAS_MCUX_SRC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF + select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_CSI + select HAS_MCUX_FLEXCAN + select HAS_SWO diff --git a/soc/nxp/imxrt/imxrt10xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt10xx/Kconfig.defconfig new file mode 100644 index 00000000000..b93d77ef775 --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + + +if SOC_SERIES_IMXRT10XX + +config NUM_IRQS + default 80 if SOC_MIMXRT1011 + default 142 if SOC_MIMXRT1015 || \ + SOC_MIMXRT1021 || \ + SOC_MIMXRT1024 + default 157 if SOC_MIMXRT1042 + default 160 if SOC_MIMXRT1052 || \ + SOC_MIMXRT1062 || \ + SOC_MIMXRT1064 + +config DCDC_VALUE + default 0x12 if SOC_MIMXRT1011 || \ + SOC_MIMXRT1015 || \ + SOC_MIMXRT1021 || \ + SOC_MIMXRT1024 + default 0x13 + +config GPIO + default y + + +endif # SOC_SERIES_IMXRT10XX diff --git a/soc/nxp/imxrt/imxrt10xx/Kconfig.soc b/soc/nxp/imxrt/imxrt10xx/Kconfig.soc new file mode 100644 index 00000000000..4aa203c79f5 --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/Kconfig.soc @@ -0,0 +1,238 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT10XX + bool + select SOC_FAMILY_NXP_IMXRT + +config SOC_SERIES + default "imxrt10xx" if SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1011 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1015 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1021 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1024 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1042 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1051 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1052 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1061 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1062 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1064 + bool + select SOC_SERIES_IMXRT10XX + +config SOC + default "mimxrt1011" if SOC_MIMXRT1011 + default "mimxrt1015" if SOC_MIMXRT1015 + default "mimxrt1021" if SOC_MIMXRT1021 + default "mimxrt1024" if SOC_MIMXRT1024 + default "mimxrt1042" if SOC_MIMXRT1042 + default "mimxrt1051" if SOC_MIMXRT1051 + default "mimxrt1052" if SOC_MIMXRT1052 + default "mimxrt1061" if SOC_MIMXRT1061 + default "mimxrt1062" if SOC_MIMXRT1062 + default "mimxrt1064" if SOC_MIMXRT1064 + +config SOC_PART_NUMBER_MIMXRT1011CAE4A + bool + select SOC_MIMXRT1011 + +config SOC_PART_NUMBER_MIMXRT1011DAE5A + bool + select SOC_MIMXRT1011 + +config SOC_PART_NUMBER_MIMXRT1015CAF4A + bool + select SOC_MIMXRT1015 + +config SOC_PART_NUMBER_MIMXRT1015DAF5A + bool + select SOC_MIMXRT1015 + +config SOC_PART_NUMBER_MIMXRT1021CAF4A + bool + select SOC_MIMXRT1021 + +config SOC_PART_NUMBER_MIMXRT1021CAG4A + bool + select SOC_MIMXRT1021 + +config SOC_PART_NUMBER_MIMXRT1021DAF5A + bool + select SOC_MIMXRT1021 + +config SOC_PART_NUMBER_MIMXRT1021DAG5A + bool + select SOC_MIMXRT1021 + +config SOC_PART_NUMBER_MIMXRT1024CAG4A + bool + select SOC_MIMXRT1024 + +config SOC_PART_NUMBER_MIMXRT1024DAG5A + bool + select SOC_MIMXRT1024 + +config SOC_PART_NUMBER_MIMXRT1041DFP6B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1041DJM6B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1041XFP5B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1041XJM5B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1042DFP6B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1042DJM6B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1042XFP5B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1042XJM5B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1051CVL5A + bool + select SOC_MIMXRT1051 + +config SOC_PART_NUMBER_MIMXRT1051DVL6A + bool + select SOC_MIMXRT1051 + +config SOC_PART_NUMBER_MIMXRT1052CVJ5B + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1052CVL5A + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1052CVL5B + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1052DVJ6B + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1052DVL6A + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1052DVL6B + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1061CVL5A + bool + select SOC_MIMXRT1061 + +config SOC_PART_NUMBER_MIMXRT1061DVL6A + bool + select SOC_MIMXRT1061 + +config SOC_PART_NUMBER_MIMXRT1062CVJ5A + bool + select SOC_MIMXRT1062 + +config SOC_PART_NUMBER_MIMXRT1062CVJ5B + bool + select SOC_MIMXRT1062 + +config SOC_PART_NUMBER_MIMXRT1062CVL5A + bool + select SOC_MIMXRT1062 + +config SOC_PART_NUMBER_MIMXRT1062DVJ6A + bool + select SOC_MIMXRT1062 + +config SOC_PART_NUMBER_MIMXRT1062DVL6A + bool + select SOC_MIMXRT1062 + +config SOC_PART_NUMBER_MIMXRT1064CVL5A + bool + select SOC_MIMXRT1064 + +config SOC_PART_NUMBER_MIMXRT1064DVL6A + bool + select SOC_MIMXRT1064 + +config SOC_PART_NUMBER + default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A + default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A + default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A + default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A + default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A + default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A + default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A + default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A + default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A + default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A + default "MIMXRT1041DFP6B" if SOC_PART_NUMBER_MIMXRT1041DFP6B + default "MIMXRT1041DJM6B" if SOC_PART_NUMBER_MIMXRT1041DJM6B + default "MIMXRT1041XFP5B" if SOC_PART_NUMBER_MIMXRT1041XFP5B + default "MIMXRT1041XJM5B" if SOC_PART_NUMBER_MIMXRT1041XJM5B + default "MIMXRT1042DFP6B" if SOC_PART_NUMBER_MIMXRT1042DFP6B + default "MIMXRT1042DJM6B" if SOC_PART_NUMBER_MIMXRT1042DJM6B + default "MIMXRT1042XFP5B" if SOC_PART_NUMBER_MIMXRT1042XFP5B + default "MIMXRT1042XJM5B" if SOC_PART_NUMBER_MIMXRT1042XJM5B + default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A + default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A + default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B + default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A + default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B + default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B + default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A + default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B + default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A + default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A + default "MIMXRT1062CVJ5A" if SOC_PART_NUMBER_MIMXRT1062CVJ5A + default "MIMXRT1062CVJ5B" if SOC_PART_NUMBER_MIMXRT1062CVJ5B + default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A + default "MIMXRT1062DVJ6A" if SOC_PART_NUMBER_MIMXRT1062DVJ6A + default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A + default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A + default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A diff --git a/soc/arm/nxp_imx/rt/flexspi_rt10xx.c b/soc/nxp/imxrt/imxrt10xx/flexspi.c similarity index 100% rename from soc/arm/nxp_imx/rt/flexspi_rt10xx.c rename to soc/nxp/imxrt/imxrt10xx/flexspi.c diff --git a/soc/nxp/imxrt/imxrt10xx/linker.ld b/soc/nxp/imxrt/imxrt10xx/linker.ld new file mode 100644 index 00000000000..a7e5123804c --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/linker.ld @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + + +#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) + +MEMORY + { + +#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0) + SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0)) +#endif + + } + +#include diff --git a/soc/arm/nxp_imx/rt/lpm_rt1064.c b/soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c similarity index 96% rename from soc/arm/nxp_imx/rt/lpm_rt1064.c rename to soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c index e4f76bb19bd..42d1110b3ca 100644 --- a/soc/arm/nxp_imx/rt/lpm_rt1064.c +++ b/soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c @@ -8,7 +8,7 @@ */ #include -#include +#include #include #include @@ -117,7 +117,7 @@ static void clock_init_usb1_pll(const clock_usb_pll_config_t *config) static void flexspi_enter_critical(void) { -#if CONFIG_CODE_FLEXSPI2 +#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash))) /* Wait for flexspi to be inactive, and gate the clock */ while (!((FLEXSPI2->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI2->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) { @@ -126,7 +126,9 @@ static void flexspi_enter_critical(void) /* Disable clock gate of flexspi2. */ CCM->CCGR7 &= (~CCM_CCGR7_CG1_MASK); -#elif CONFIG_CODE_FLEXSPI +#endif + +#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash))) /* Wait for flexspi to be inactive, and gate the clock */ while (!((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) { @@ -140,7 +142,7 @@ static void flexspi_enter_critical(void) static void flexspi_exit_critical(void) { -#if CONFIG_CODE_FLEXSPI2 +#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash))) /* Enable clock gate of flexspi2. */ CCM->CCGR7 |= (CCM_CCGR7_CG1_MASK); @@ -151,7 +153,7 @@ static void flexspi_exit_critical(void) while (!((FLEXSPI2->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI2->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) { } -#elif CONFIG_CODE_FLEXSPI +#elif DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash))) /* Enable clock of flexspi. */ CCM->CCGR6 |= CCM_CCGR6_CG5_MASK; @@ -209,10 +211,10 @@ void clock_full_power(void) #endif /* Set Flexspi divider before increasing frequency of PLL3 PDF0. */ -#if CONFIG_CODE_FLEXSPI +#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash))) clock_set_div(kCLOCK_FlexspiDiv, flexspi_div); clock_set_mux(kCLOCK_FlexspiMux, 3); -#elif CONFIG_CODE_FLEXSPI2 +#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash))) clock_set_div(kCLOCK_Flexspi2Div, flexspi_div); clock_set_mux(kCLOCK_Flexspi2Mux, 1); #endif @@ -255,11 +257,11 @@ void clock_low_power(void) CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_ENABLE_MASK; CCM_ANALOG->PFD_480_CLR = CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK; /* Change flexspi to use PLL3 PFD0 with no divisor (24M flexspi clock) */ -#if CONFIG_CODE_FLEXSPI +#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash))) clock_set_div(kCLOCK_FlexspiDiv, 0); /* FLEXSPI1 mux to PLL3 PFD0 BYPASS */ clock_set_mux(kCLOCK_FlexspiMux, 3); -#elif CONFIG_CODE_FLEXSPI2 +#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash))) clock_set_div(kCLOCK_Flexspi2Div, 0); /* FLEXSPI2 mux to PLL3 PFD0 BYPASS */ clock_set_mux(kCLOCK_Flexspi2Mux, 1); diff --git a/soc/arm/nxp_imx/rt/pinctrl_rt10xx.h b/soc/nxp/imxrt/imxrt10xx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/rt/pinctrl_rt10xx.h rename to soc/nxp/imxrt/imxrt10xx/pinctrl_soc.h diff --git a/soc/nxp/imxrt/imxrt10xx/power.c b/soc/nxp/imxrt/imxrt10xx/power.c new file mode 100644 index 00000000000..fac3180c0db --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/power.c @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Note: this file is linked to RAM. Any functions called while preparing for + * sleep mode must be defined within this file, or linked to RAM. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "power.h" + +LOG_MODULE_REGISTER(soc_power, CONFIG_SOC_LOG_LEVEL); + + +static struct clock_callbacks lpm_clock_hooks; + +/* + * Boards with RT10XX SOCs can register callbacks to set their clocks into + * normal/full speed mode, low speed mode, and low power mode. + * If callbacks are present, the low power subsystem will disable + * PLLs for power savings when entering low power states. + */ +void imxrt_clock_pm_callbacks_register(struct clock_callbacks *callbacks) +{ + /* If run callback is set, low power must be as well. */ + __ASSERT_NO_MSG(callbacks && callbacks->clock_set_run && callbacks->clock_set_low_power); + lpm_clock_hooks.clock_set_run = callbacks->clock_set_run; + lpm_clock_hooks.clock_set_low_power = callbacks->clock_set_low_power; + if (callbacks->clock_lpm_init) { + lpm_clock_hooks.clock_lpm_init = callbacks->clock_lpm_init; + } +} + +static void lpm_set_sleep_mode_config(clock_mode_t mode) +{ + uint32_t clpcr; + + /* Set GPC wakeup config to GPT timer interrupt */ + GPC_EnableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_gpt_hw_timer))); + /* + * ERR050143: CCM: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending + * by setting IOMUXC_GPR_GPR1_GINT. + * 2) Software should then unmask IRQ #41 in GPC before setting CCM + * Low-Power mode. + * 3) Software should mask IRQ #41 right after CCM Low-Power mode + * is set (set bits 0-1 of CCM_CLPCR). + */ + GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); + clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); + /* Note: if CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK is set, + * debugger will not connect in sleep mode + */ + /* Set clock control module to transfer system to idle mode */ + clpcr |= CCM_CLPCR_LPM(mode) | CCM_CLPCR_MASK_SCU_IDLE_MASK | + CCM_CLPCR_MASK_L2CC_IDLE_MASK | + CCM_CLPCR_STBY_COUNT_MASK | + CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK; +#ifndef CONFIG_SOC_MIMXRT1011 + /* RT1011 does not include handshake bits */ + clpcr |= CCM_CLPCR_BYPASS_LPM_HS0_MASK | CCM_CLPCR_BYPASS_LPM_HS1_MASK; +#endif + CCM->CLPCR = clpcr; + GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); +} + +static void lpm_enter_soft_off_mode(void) +{ + /* Enable the SNVS RTC as a wakeup source from soft-off mode, in case an RTC alarm + * was set. + */ + GPC_EnableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_imx_snvs_rtc))); + SNVS->LPCR |= SNVS_LPCR_TOP_MASK; +} + +static void lpm_enter_sleep_mode(clock_mode_t mode) +{ + /* FIXME: When this function is entered the Kernel has disabled + * interrupts using BASEPRI register. This is incorrect as it prevents + * waking up from any interrupt which priority is not 0. Work around the + * issue and disable interrupts using PRIMASK register as recommended + * by ARM. + */ + + /* Set PRIMASK */ + __disable_irq(); + /* Set BASEPRI to 0 */ + irq_unlock(0); + barrier_dsync_fence_full(); + barrier_isync_fence_full(); + + if (mode == kCLOCK_ModeWait) { + /* Clear the SLEEPDEEP bit to go into sleep mode (WAIT) */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + } else { + /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + } + /* WFI instruction will start entry into WAIT/STOP mode */ + __WFI(); + +} + +static void lpm_set_run_mode_config(void) +{ + /* Clear GPC wakeup source */ + GPC_DisableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_gpt_hw_timer))); + CCM->CLPCR &= ~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK); +} + +/* Toggle the analog bandgap reference circuitry on and off */ +static void bandgap_set(bool on) +{ + if (on) { + /* Enable bandgap in PMU */ + PMU->MISC0_CLR = PMU_MISC0_REFTOP_PWD_MASK; + /* Wait for it to stabilize */ + while ((PMU->MISC0 & PMU_MISC0_REFTOP_VBGUP_MASK) == 0) { + + } + /* Disable low power bandgap */ + XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; + } else { + /* Disable bandgap in PMU and switch to low power one */ + XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; + PMU->MISC0_SET = PMU_MISC0_REFTOP_PWD_MASK; + } +} + +/* Should only be used if core clocks have been reduced- drops SOC voltage */ +static void lpm_drop_voltage(void) +{ + /* Move to the internal RC oscillator, since we are using low power clocks */ + CLOCK_InitRcOsc24M(); + /* Switch to internal RC oscillator */ + CLOCK_SwitchOsc(kCLOCK_RcOsc); + CLOCK_DeinitExternalClk(); + /* + * Change to 1.075V SOC voltage. If you are experiencing issues with + * low power mode stability, try raising this voltage value. + */ + DCDC_AdjustRunTargetVoltage(DCDC, 0xB); + /* Enable 2.5 and 1.1V weak regulators */ + PMU_2P5EnableWeakRegulator(PMU, true); + PMU_1P1EnableWeakRegulator(PMU, true); + /* Disable normal regulators */ + PMU_2P5EnableOutput(PMU, false); + PMU_1P1EnableOutput(PMU, false); + /* Disable analog bandgap */ + bandgap_set(false); +} + +/* Undo the changes made by lpm_drop_voltage so clocks can be raised */ +static void lpm_raise_voltage(void) +{ + /* Enable analog bandgap */ + bandgap_set(true); + /* Enable regulator LDOs */ + PMU_2P5EnableOutput(PMU, true); + PMU_1P1EnableOutput(PMU, true); + /* Disable weak LDOs */ + PMU_2P5EnableWeakRegulator(PMU, false); + PMU_1P1EnableWeakRegulator(PMU, false); + /* Change to 1.275V SOC voltage */ + DCDC_AdjustRunTargetVoltage(DCDC, 0x13); + /* Move to the external RC oscillator */ + CLOCK_InitExternalClk(0); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); +} + + +/* Sets device into low power mode */ +void pm_state_set(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(substate_id); + + switch (state) { + case PM_STATE_RUNTIME_IDLE: + LOG_DBG("entering PM state runtime idle"); + lpm_set_sleep_mode_config(kCLOCK_ModeWait); + lpm_enter_sleep_mode(kCLOCK_ModeWait); + break; + case PM_STATE_SUSPEND_TO_IDLE: + LOG_DBG("entering PM state suspend to idle"); + if (lpm_clock_hooks.clock_set_low_power) { + /* Drop the SOC clocks to low power mode, and decrease core voltage */ + lpm_clock_hooks.clock_set_low_power(); + lpm_drop_voltage(); + } + lpm_set_sleep_mode_config(kCLOCK_ModeWait); + lpm_enter_sleep_mode(kCLOCK_ModeWait); + break; + case PM_STATE_SOFT_OFF: + LOG_DBG("Entering PM state soft off"); + lpm_enter_soft_off_mode(); + break; + default: + return; + } +} + +/* Handle SOC specific activity after Low Power Mode Exit */ +void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(substate_id); + + /* Set run mode config after wakeup */ + switch (state) { + case PM_STATE_RUNTIME_IDLE: + lpm_set_run_mode_config(); + LOG_DBG("exited PM state runtime idle"); + break; + case PM_STATE_SUSPEND_TO_IDLE: + lpm_set_run_mode_config(); + if (lpm_clock_hooks.clock_set_run) { + /* Raise core voltage and restore SOC clocks */ + lpm_raise_voltage(); + lpm_clock_hooks.clock_set_run(); + } + LOG_DBG("exited PM state suspend to idle"); + break; + default: + break; + } + /* Clear PRIMASK after wakeup */ + __enable_irq(); +} + +/* Initialize power system */ +static int rt10xx_power_init(void) +{ + dcdc_internal_regulator_config_t reg_config; + + + /* Ensure clocks to ARM core memory will not be gated in low power mode + * if interrupt is pending + */ + CCM->CGPR |= CCM_CGPR_INT_MEM_CLK_LPM_MASK; + + if (lpm_clock_hooks.clock_lpm_init) { + lpm_clock_hooks.clock_lpm_init(); + } + + /* Errata ERR050143 */ + IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_GINT_MASK; + + /* Configure DCDC */ + DCDC_BootIntoDCM(DCDC); + /* Set target voltage for low power mode to 0.925V*/ + DCDC_AdjustLowPowerTargetVoltage(DCDC, 0x1); + /* Reconfigure DCDC to disable internal load resistor */ + reg_config.enableLoadResistor = false; + reg_config.feedbackPoint = 0x1; /* 1.0V with 1.3V reference voltage */ + DCDC_SetInternalRegulatorConfig(DCDC, ®_config); + + /* Enable high gate drive on power FETs to reduce leakage current */ + PMU_CoreEnableIncreaseGateDrive(PMU, true); + + + return 0; +} + +SYS_INIT(rt10xx_power_init, PRE_KERNEL_2, 0); diff --git a/soc/arm/nxp_imx/rt/power_rt10xx.h b/soc/nxp/imxrt/imxrt10xx/power.h similarity index 100% rename from soc/arm/nxp_imx/rt/power_rt10xx.h rename to soc/nxp/imxrt/imxrt10xx/power.h diff --git a/soc/nxp/imxrt/imxrt10xx/soc.c b/soc/nxp/imxrt/imxrt10xx/soc.c new file mode 100644 index 00000000000..0e4bae616a6 --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/soc.c @@ -0,0 +1,344 @@ +/* + * Copyright 2017-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#include +#endif +#include +#include +#if CONFIG_USB_DC_NXP_EHCI +#include "usb_phy.h" +#include "usb.h" +#endif + +#include "memc_nxp_flexram.h" + +#include + +#define CCM_NODE DT_INST(0, nxp_imx_ccm) + +#define BUILD_ASSERT_PODF_IN_RANGE(podf, a, b) \ + BUILD_ASSERT(DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) >= (a) && \ + DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) <= (b), \ + #podf " is out of supported range (" #a ", " #b ")") + +#ifdef CONFIG_INIT_ARM_PLL +/* ARM PLL configuration for RUN mode */ +const clock_arm_pll_config_t armPllConfig = { + .loopDivider = 100U +}; +#endif + +#if CONFIG_USB_DC_NXP_EHCI +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) +#endif + +#ifdef CONFIG_INIT_ENET_PLL +/* ENET PLL configuration for RUN mode */ +const clock_enet_pll_config_t ethPllConfig = { +#if defined(CONFIG_SOC_MIMXRT1011) || \ + defined(CONFIG_SOC_MIMXRT1015) || \ + defined(CONFIG_SOC_MIMXRT1021) || \ + defined(CONFIG_SOC_MIMXRT1024) + .enableClkOutput500M = true, +#endif +#if defined(CONFIG_ETH_NXP_ENET) || defined(CONFIG_ETH_MCUX) +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) + .enableClkOutput = true, +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) + .enableClkOutput1 = true, +#endif +#endif +#if defined(CONFIG_PTP_CLOCK_MCUX) + .enableClkOutput25M = true, +#else + .enableClkOutput25M = false, +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) + .loopDivider = 1, +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) + .loopDivider1 = 1, +#endif +}; +#endif + +#if CONFIG_USB_DC_NXP_EHCI + usb_phy_config_struct_t usbPhyConfig = { + BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, + }; +#endif + +#ifdef CONFIG_INIT_VIDEO_PLL +const clock_video_pll_config_t videoPllConfig = { + .loopDivider = 31, + .postDivider = 8, + .numerator = 0, + .denominator = 0, +}; +#endif + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +const __imx_boot_data_section BOOT_DATA_T boot_data = { +#ifdef CONFIG_XIP + .start = CONFIG_FLASH_BASE_ADDRESS, + .size = (uint32_t)&_flash_used, +#else + .start = CONFIG_SRAM_BASE_ADDRESS, + .size = (uint32_t)&_image_ram_size, +#endif + .plugin = PLUGIN_FLAG, + .placeholder = 0xFFFFFFFF, +}; + +const __imx_boot_ivt_section ivt image_vector_table = { + .hdr = IVT_HEADER, + .entry = (uint32_t) _vector_start, + .reserved1 = IVT_RSVD, +#ifdef CONFIG_DEVICE_CONFIGURATION_DATA + .dcd = (uint32_t) dcd_data, +#else + .dcd = (uint32_t) NULL, +#endif + .boot_data = (uint32_t) &boot_data, + .self = (uint32_t) &image_vector_table, + .csf = (uint32_t)CSF_ADDRESS, + .reserved2 = IVT_RSVD, +}; +#endif + +/** + * @brief Initialize the system clock + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Boot ROM did initialize the XTAL, here we only sets external XTAL + * OSC freq + */ + CLOCK_SetXtalFreq(DT_PROP(DT_CLOCKS_CTLR_BY_NAME(CCM_NODE, xtal), + clock_frequency)); + CLOCK_SetRtcXtalFreq(DT_PROP(DT_CLOCKS_CTLR_BY_NAME(CCM_NODE, rtc_xtal), + clock_frequency)); + + /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); + + /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); + + /* Setting the VDD_SOC value. + */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != + (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { + ; + } + +#ifdef CONFIG_INIT_ARM_PLL + CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */ +#endif +#ifdef CONFIG_INIT_ENET_PLL + CLOCK_InitEnetPll(ðPllConfig); +#endif +#ifdef CONFIG_INIT_VIDEO_PLL + CLOCK_InitVideoPll(&videoPllConfig); +#endif + +#if DT_NODE_EXISTS(DT_CHILD(CCM_NODE, arm_podf)) + /* Set ARM PODF */ + BUILD_ASSERT_PODF_IN_RANGE(arm_podf, 1, 8); + CLOCK_SetDiv(kCLOCK_ArmDiv, DT_PROP(DT_CHILD(CCM_NODE, arm_podf), clock_div) - 1); +#endif + /* Set AHB PODF */ + BUILD_ASSERT_PODF_IN_RANGE(ahb_podf, 1, 8); + CLOCK_SetDiv(kCLOCK_AhbDiv, DT_PROP(DT_CHILD(CCM_NODE, ahb_podf), clock_div) - 1); + /* Set IPG PODF */ + BUILD_ASSERT_PODF_IN_RANGE(ipg_podf, 1, 4); + CLOCK_SetDiv(kCLOCK_IpgDiv, DT_PROP(DT_CHILD(CCM_NODE, ipg_podf), clock_div) - 1); + + /* Set PRE_PERIPH_CLK to PLL1, 1200M */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); + + /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); + +#ifdef CONFIG_UART_MCUX_LPUART + /* Configure UART divider to default */ + CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ +#endif + +#ifdef CONFIG_I2C_MCUX_LPI2C + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); /* Set I2C source as USB1 PLL 480M */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5); /* Set I2C divider to 6 */ +#endif + +#ifdef CONFIG_SPI_MCUX_LPSPI + CLOCK_SetMux(kCLOCK_LpspiMux, 1); /* Set SPI source to USB1 PFD0 720M */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 7); /* Set SPI divider to 8 */ +#endif + +#ifdef CONFIG_DISPLAY_MCUX_ELCDIF + /* MUX selects video PLL, which is initialized to 93MHz */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 2); + /* Divide output by 2 */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 1); + /* Set final div based on LCDIF clock-frequency */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, + ((CLOCK_GetPllFreq(kCLOCK_PllVideo) / 2) / + DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), + clock_frequency)) - 1); +#endif + + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET +#if CONFIG_ETH_MCUX_RMII_EXT_CLK + /* Enable clock input for ENET1 */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, false); +#else + /* Enable clock output for ENET1 */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); +#endif +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) && CONFIG_NET_L2_ETHERNET + /* Set ENET2 ref clock to be generated by External OSC,*/ + /* direction as output and frequency to 50MHz */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2TxClkOutputDir | + kIOMUXC_GPR_ENET2RefClkMode, true); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); + USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && CONFIG_USB_DC_NXP_EHCI + CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); + CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); + USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC + /* Configure USDHC clock source and divider */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U); + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U); + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U); + CLOCK_EnableClock(kCLOCK_Usdhc1); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_IMX_USDHC + /* Configure USDHC clock source and divider */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U); + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1U); + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 1U); + CLOCK_EnableClock(kCLOCK_Usdhc2); +#endif + +#ifdef CONFIG_VIDEO_MCUX_CSI + CLOCK_EnableClock(kCLOCK_Csi); /* Disable CSI clock gate */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 0); /* Set CSI divider to 1 */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); /* Set CSI source to OSC 24M */ +#endif +#ifdef CONFIG_CAN_MCUX_FLEXCAN + CLOCK_SetDiv(kCLOCK_CanDiv, 1); /* Set CAN_CLK_PODF. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); /* Set Can clock source. */ +#endif + +#ifdef CONFIG_LOG_BACKEND_SWO + /* Enable ARM trace clock to enable SWO output */ + CLOCK_EnableClock(kCLOCK_Trace); + /* Divide root clock output by 3 */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Source clock from 528MHz system PLL */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); +#endif + + /* Keep the system clock running so SYSTICK can wake up the system from + * wfi. + */ + CLOCK_SetMode(kCLOCK_ModeRun); + +} + +#if CONFIG_I2S_MCUX_SAI +void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, + uint32_t clk_pre_div, uint32_t clk_src_div) +{ + switch (clock_name) { + case IMX_CCM_SAI1_CLK: + CLOCK_SetMux(kCLOCK_Sai1Mux, clk_src); + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, clk_pre_div); + CLOCK_SetDiv(kCLOCK_Sai1Div, clk_src_div); + break; + case IMX_CCM_SAI2_CLK: + CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src); + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, clk_pre_div); + CLOCK_SetDiv(kCLOCK_Sai2Div, clk_src_div); + break; + case IMX_CCM_SAI3_CLK: + CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src); + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, clk_pre_div); + CLOCK_SetDiv(kCLOCK_Sai2Div, clk_src_div); + break; + default: + return; + } +} +#endif + +/** + * + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * + * @return 0 + */ + +static int imxrt_init(void) +{ + sys_cache_instr_enable(); + sys_cache_data_enable(); + + /* Initialize system clock */ + clock_init(); + + return 0; +} + +#ifdef CONFIG_PLATFORM_SPECIFIC_INIT +void z_arm_platform_init(void) +{ + /* Call CMSIS SystemInit */ + SystemInit(); + +#if defined(FLEXRAM_RUNTIME_BANKS_USED) + /* Configure flexram if not running from RAM */ + memc_flexram_dt_partition(); +#endif +} +#endif + +SYS_INIT(imxrt_init, PRE_KERNEL_1, 0); diff --git a/soc/nxp/imxrt/imxrt10xx/soc.h b/soc/nxp/imxrt/imxrt10xx/soc.h new file mode 100644 index 00000000000..88b34454179 --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/soc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#include + +#ifndef _ASMLANGUAGE + +#include + +/* Add include for DTS generated information */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_I2S_MCUX_SAI +void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, + uint32_t clk_pre_div, uint32_t clk_src_div); + +#endif + +#if CONFIG_MIPI_DSI +void imxrt_pre_init_display_interface(void); + +void imxrt_post_init_display_interface(void); +#endif + +void flexspi_clock_set_div(uint32_t value); +uint32_t flexspi_clock_get_freq(void); + +#ifdef CONFIG_MEMC +uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/soc/nxp/imxrt/imxrt11xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt11xx/CMakeLists.txt new file mode 100644 index 00000000000..49636be86e6 --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) +zephyr_sources_ifdef(CONFIG_PM power.c) + +zephyr_include_directories(.) + +if(CONFIG_MEMC_MCUX_FLEXSPI) + zephyr_sources(flexspi.c) + if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) + zephyr_code_relocate(FILES flexspi.c LOCATION ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT) + endif() +endif() + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imxrt/imxrt11xx/Kconfig b/soc/nxp/imxrt/imxrt11xx/Kconfig new file mode 100644 index 00000000000..064c28ea238 --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/Kconfig @@ -0,0 +1,75 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT11XX + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select CPU_CORTEX_M_HAS_DWT + select PLATFORM_SPECIFIC_INIT + select ARM + select CLOCK_CONTROL + select HAS_MCUX_CACHE + select HAS_MCUX + select HAS_MCUX_SEMC + select HAS_MCUX_CCM_REV2 + select HAS_MCUX_IGPIO + select HAS_MCUX_LPI2C + select HAS_MCUX_LPSPI + select HAS_MCUX_LPADC + select HAS_MCUX_LPUART + select HAS_MCUX_ELCDIF + select HAS_MCUX_MIPI_DSI + select HAS_MCUX_GPT + select HAS_MCUX_FLEXSPI + select HAS_MCUX_FLEXCAN + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER + select INIT_VIDEO_PLL + select HAS_MCUX_EDMA + select CPU_HAS_ICACHE if CPU_CORTEX_M7 + select CPU_HAS_DCACHE if CPU_CORTEX_M7 + select CPU_HAS_FPU + select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7 + select BYPASS_LDO_LPSR + select ADJUST_LDO + select HAS_MCUX_PWM + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_ENET + select HAS_MCUX_GPC + select HAS_MCUX_I2S + select HAS_MCUX_USB_EHCI + select HAS_MCUX_ACMP + select HAS_MCUX_SRC_V2 + select HAS_MCUX_IOMUXC + select HAS_MCUX_XBARA + select HAS_SWO + +config SOC_MIMXRT1176_CM4 + select CPU_CORTEX_M4 + +config SOC_MIMXRT1176_CM7 + select CPU_CORTEX_M7 + +config SOC_MIMXRT1166_CM4 + select CPU_CORTEX_M4 + +config SOC_MIMXRT1166_CM7 + select CPU_CORTEX_M7 + +if SOC_SERIES_IMXRT11XX + +config MCUX_CORE_SUFFIX + default "_cm7" if SOC_MIMXRT1176_CM7 || SOC_MIMXRT1166_CM7 + default "_cm4" if SOC_MIMXRT1176_CM4 || SOC_MIMXRT1166_CM4 + +config BYPASS_LDO_LPSR + bool "Bypass LDO lpsr" + +config ADJUST_LDO + bool "Adjust LDO setting" + +config ADJUST_DCDC + bool "Adjust internal DCDC output" + +endif # SOC_SERIES_IMXRT11XX diff --git a/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig new file mode 100644 index 00000000000..b66e4ff851c --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig @@ -0,0 +1,35 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMXRT11XX + +config NUM_IRQS + default 218 + +config GPIO + default y + +if CORTEX_M_SYSTICK + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 996000000 if SOC_MIMXRT1176_CM7 + default 600000000 if SOC_MIMXRT1166_CM7 + default 400000000 if SOC_MIMXRT1176_CM4 + default 240000000 if SOC_MIMXRT1166_CM4 + +endif # CORTEX_M_SYSTICK + +config DCDC_VALUE + default 0x13 + +config FLEXSPI_CONFIG_BLOCK_OFFSET + default 0x400 if BOOT_FLEXSPI_NOR + +if SECOND_CORE_MCUX + +# RT Boot header is only needed on primary core +config NXP_IMXRT_BOOT_HEADER + depends on CPU_CORTEX_M7 + +endif +endif diff --git a/soc/nxp/imxrt/imxrt11xx/Kconfig.soc b/soc/nxp/imxrt/imxrt11xx/Kconfig.soc new file mode 100644 index 00000000000..1ae193120fd --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/Kconfig.soc @@ -0,0 +1,95 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT11XX + bool + select SOC_FAMILY_NXP_IMXRT + +config SOC_SERIES + default "imxrt11xx" if SOC_SERIES_IMXRT11XX + +config SOC_MIMXRT1166 + bool + select SOC_SERIES_IMXRT11XX + +config SOC_MIMXRT1176 + bool + select SOC_SERIES_IMXRT11XX + +config SOC_MIMXRT1166_CM4 + bool + select SOC_MIMXRT1166 + +config SOC_MIMXRT1166_CM7 + bool + select SOC_MIMXRT1166 + +config SOC_MIMXRT1176_CM4 + bool + select SOC_MIMXRT1176 + +config SOC_MIMXRT1176_CM7 + bool + select SOC_MIMXRT1176 + +config SOC + default "mimxrt1166" if SOC_MIMXRT1166 + default "mimxrt1176" if SOC_MIMXRT1176 + +config SOC_PART_NUMBER_MIMXRT1166DVM6A + bool + +config SOC_PART_NUMBER_MIMXRT1176AVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1176CVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1176DVMAA + bool + +config SOC_PART_NUMBER_MIMXRT1175AVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1175CVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1175DVMAA + bool + +config SOC_PART_NUMBER_MIMXRT1173CVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1172AVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1172CVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1172DVMAA + bool + +config SOC_PART_NUMBER_MIMXRT1171AVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1171CVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1171DVMAA + bool + +config SOC_PART_NUMBER + default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A + default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A + default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA + default "MIMXRT1166DVM6A" if SOC_PART_NUMBER_MIMXRT1166DVM6A + default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A + default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A + default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA + default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A + default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A + default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A + default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA + default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A + default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A + default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA diff --git a/soc/arm/nxp_imx/rt/flexspi_rt11xx.c b/soc/nxp/imxrt/imxrt11xx/flexspi.c similarity index 100% rename from soc/arm/nxp_imx/rt/flexspi_rt11xx.c rename to soc/nxp/imxrt/imxrt11xx/flexspi.c diff --git a/soc/nxp/imxrt/imxrt11xx/linker.ld b/soc/nxp/imxrt/imxrt11xx/linker.ld new file mode 100644 index 00000000000..a7e5123804c --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/linker.ld @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + + +#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) + +MEMORY + { + +#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0) + SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0)) +#endif + + } + +#include diff --git a/soc/arm/nxp_imx/rt/pinctrl_rt11xx.h b/soc/nxp/imxrt/imxrt11xx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/rt/pinctrl_rt11xx.h rename to soc/nxp/imxrt/imxrt11xx/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/rt/power_rt11xx.c b/soc/nxp/imxrt/imxrt11xx/power.c similarity index 100% rename from soc/arm/nxp_imx/rt/power_rt11xx.c rename to soc/nxp/imxrt/imxrt11xx/power.c diff --git a/soc/arm/nxp_imx/rt/power_rt11xx.h b/soc/nxp/imxrt/imxrt11xx/power.h similarity index 100% rename from soc/arm/nxp_imx/rt/power_rt11xx.h rename to soc/nxp/imxrt/imxrt11xx/power.h diff --git a/soc/nxp/imxrt/imxrt11xx/soc.c b/soc/nxp/imxrt/imxrt11xx/soc.c new file mode 100644 index 00000000000..065039f38a2 --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/soc.c @@ -0,0 +1,728 @@ +/* + * Copyright 2021-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#include +#endif +#include +#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) +#include +/* Memcpy macro to copy segments from secondary core image stored in flash + * to RAM section that secondary core boots from. + * n is the segment number, as defined in zephyr_image_info.h + */ +#define MEMCPY_SEGMENT(n, _) \ + memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_ ## n) - ADJUSTED_LMA), \ + (uint32_t *)(SEGMENT_LMA_ADDRESS_ ## n), \ + (SEGMENT_SIZE_ ## n)) +#endif +#if CONFIG_USB_DC_NXP_EHCI +#include "usb_phy.h" +#include "usb.h" +#endif +#include "memc_nxp_flexram.h" + +#include + +#define DUAL_CORE_MU_ENABLED \ + (CONFIG_SECOND_CORE_MCUX && CONFIG_IPM && CONFIG_IPM_IMX) + +#if DUAL_CORE_MU_ENABLED +/* Dual core mode is enabled, and messaging unit is present */ +#include +#define BOOT_FLAG 0x1U +#define MU_BASE (MU_Type *)DT_REG_ADDR(DT_INST(0, nxp_imx_mu)) +#endif + +#if CONFIG_USB_DC_NXP_EHCI /* USB PHY configuration */ +#define BOARD_USB_PHY_D_CAL (0x07U) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) +#endif + +#ifdef CONFIG_INIT_ARM_PLL +static const clock_arm_pll_config_t armPllConfig = { +#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1176_CM7) + /* resulting frequency: 24 * (166/(2* 2)) = 984MHz */ + /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .postDivider = kCLOCK_PllPostDiv2, + /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + .loopDivider = 166, +#elif defined(CONFIG_SOC_MIMXRT1166_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM7) + /* resulting frequency: 24 * (200/(2 * 4)) = 600MHz */ + /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .postDivider = kCLOCK_PllPostDiv4, + /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + .loopDivider = 200, +#else + #error "Unknown SOC, no pll configuration defined" +#endif +}; +#endif + +static const clock_sys_pll2_config_t sysPll2Config = { + /* Denominator of spread spectrum */ + .mfd = 268435455, + /* Spread spectrum parameter */ + .ss = NULL, + /* Enable spread spectrum or not */ + .ssEnable = false, +}; + +#ifdef CONFIG_INIT_ENET_PLL +static const clock_sys_pll1_config_t sysPll1Config = { + .pllDiv2En = true, +}; +#endif + +#ifdef CONFIG_INIT_VIDEO_PLL +static const clock_video_pll_config_t videoPllConfig = { + /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */ + .loopDivider = 41, + /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */ + .postDivider = 0, + /* + * 30 bit numerator of fractional loop divider, + * Fout = Fin * ( loopDivider + numerator / denominator ) + */ + .numerator = 1, + /* + * 30 bit denominator of fractional loop divider, + * Fout = Fin * ( loopDivider + numerator / denominator ) + */ + .denominator = 960000, + /* Spread spectrum parameter */ + .ss = NULL, + /* Enable spread spectrum or not */ + .ssEnable = false, +}; +#endif + +#if CONFIG_USB_DC_NXP_EHCI + usb_phy_config_struct_t usbPhyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; +#endif + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +const __imx_boot_data_section BOOT_DATA_T boot_data = { +#ifdef CONFIG_XIP + .start = CONFIG_FLASH_BASE_ADDRESS, + .size = (uint32_t)&_flash_used, +#else + .start = CONFIG_SRAM_BASE_ADDRESS, + .size = (uint32_t)&_image_ram_size, +#endif + .plugin = PLUGIN_FLAG, + .placeholder = 0xFFFFFFFF, +}; + +extern char __start[]; +const __imx_boot_ivt_section ivt image_vector_table = { + .hdr = IVT_HEADER, + .entry = (uint32_t) __start, + .reserved1 = IVT_RSVD, +#ifdef CONFIG_DEVICE_CONFIGURATION_DATA + .dcd = (uint32_t) dcd_data, +#else + .dcd = (uint32_t) NULL, +#endif + .boot_data = (uint32_t) &boot_data, + .self = (uint32_t) &image_vector_table, + .csf = (uint32_t)CSF_ADDRESS, + .reserved2 = IVT_RSVD, +}; +#endif + +/** + * @brief Initialize the system clock + */ +static ALWAYS_INLINE void clock_init(void) +{ + clock_root_config_t rootCfg = {0}; + +#if CONFIG_ADJUST_DCDC + DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V); +#endif + +/* RT1160 does not have Forward Body Biasing on the CM7 core */ +#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1176_CM7) + /* Check if FBB need to be enabled in OverDrive(OD) mode */ + if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) { + PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true); + } else { + PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false); + } +#endif + +#if CONFIG_BYPASS_LDO_LPSR + PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true); + PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true); +#endif + +#if CONFIG_ADJUST_LDO + pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig; + pmu_static_lpsr_dig_config_t lpsrDigConfig; + + if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & + ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL) { + PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig); + PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig); + } + + if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & + ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL) { + PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig); + lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V; + PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig); + } +#endif + + /* PLL LDO shall be enabled first before enable PLLs */ + + /* Config CLK_1M */ + CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); + + /* Init OSC RC 16M */ + ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK; + + /* Init OSC RC 400M */ + CLOCK_OSC_EnableOscRc400M(); + CLOCK_OSC_GateOscRc400M(true); + + /* Init OSC RC 48M */ + CLOCK_OSC_EnableOsc48M(true); + CLOCK_OSC_EnableOsc48MDiv2(true); + + /* Config OSC 24M */ + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | + ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | + ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | + ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | + ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); + + /* Wait for 24M OSC to be stable. */ + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) { + } + + rootCfg.div = 1; + +#ifdef CONFIG_CPU_CORTEX_M7 + /* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); + + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + +#if CONFIG_CPU_CORTEX_M4 + rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); + + rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); +#endif + + /* + * If DCD is used, please make sure the clock source of SEMC is not + * changed in the following PLL/PFD configuration code. + */ + +#ifdef CONFIG_INIT_ARM_PLL + /* Init Arm Pll. */ + CLOCK_InitArmPll(&armPllConfig); +#endif + +#ifdef CONFIG_INIT_ENET_PLL + CLOCK_InitSysPll1(&sysPll1Config); +#else + /* Bypass Sys Pll1. */ + CLOCK_SetPllBypass(kCLOCK_PllSys1, true); + + /* DeInit Sys Pll1. */ + CLOCK_DeinitSysPll1(); +#endif + + /* Init Sys Pll2. */ + CLOCK_InitSysPll2(&sysPll2Config); + + /* Init System Pll2 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); + + /* Init System Pll2 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); + + /* Init System Pll2 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + + /* Init System Pll2 pfd3. */ +#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24); +#else + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); +#endif + + /* Init Sys Pll3. */ + CLOCK_InitSysPll3(); + + /* Init System Pll3 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13); + + /* Init System Pll3 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17); + + /* Init System Pll3 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32); + + /* Init System Pll3 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22); + +#ifdef CONFIG_INIT_VIDEO_PLL + /* Init Video Pll. */ + CLOCK_InitVideoPll(&videoPllConfig); +#endif + + /* Module clock root configurations. */ + /* Configure M7 using ARM_PLL_CLK */ +#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + +#if defined(CONFIG_SOC_MIMXRT1166_CM4) + /* Configure M4 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); +#elif defined(CONFIG_SOC_MIMXRT1176_CM4) + /* Configure M4 using SYS_PLL3_CLK_PFD3_CLK */ + rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); +#endif + + /* Configure BUS using SYS_PLL3_CLK */ +#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET + /* Configure root bus clock at 198M */ + rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); +#elif defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) + /* Keep root bus clock at default 240M */ + rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); +#endif + + /* Configure BUS_LPSR using SYS_PLL3_CLK */ +#if defined(CONFIG_SOC_MIMXRT1176_CM4) + rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); +#elif defined(CONFIG_SOC_MIMXRT1166_CM4) + rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); +#endif + + /* Configure CSSYS using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg); + + /* Configure CSTRACE using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg); + + /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */ +#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM4) + rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg); +#endif + + /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */ +#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + +#ifdef CONFIG_UART_MCUX_LPUART + /* Configure Lpuart1 using SysPll2*/ + rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out; + rootCfg.div = 22; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg); + + /* Configure Lpuart2 using SysPll2*/ + rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out; + rootCfg.div = 22; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg); +#endif + +#ifdef CONFIG_I2C_MCUX_LPI2C + /* Configure Lpi2c1 using Osc48MDiv2 */ + rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg); + + /* Configure Lpi2c5 using Osc48MDiv2 */ + rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg); +#endif + + +#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) + /* 50 MHz ENET clock */ + rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); +#if CONFIG_ETH_MCUX_RMII_EXT_CLK + /* Set ENET_REF_CLK as an input driven by PHY */ + IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U); + IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U); +#else + /* Set ENET_REF_CLK as an output driven by ENET1_CLK_ROOT */ + IOMUXC_GPR->GPR4 |= (IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U) | + IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U)); +#endif +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet1g), okay) + /* + * 50 MHz clock for 10/100Mbit RMII PHY - + * operate ENET1G just like ENET peripheral + */ + rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); +#if CONFIG_ETH_MCUX_RMII_EXT_CLK + /* Set ENET1G_REF_CLK as an input driven by PHY */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U); + IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U); +#else + /* Set ENET1G_REF_CLK as an output driven by ENET2_CLK_ROOT */ + IOMUXC_GPR->GPR5 |= (IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U) | + IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U)); +#endif +#endif +#endif + +#ifdef CONFIG_PTP_CLOCK_MCUX + /* 24MHz PTP clock */ + rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg); +#endif + +#ifdef CONFIG_SPI_MCUX_LPSPI + /* Configure lpspi using Osc48MDiv2 */ + rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg); +#endif + +#ifdef CONFIG_CAN_MCUX_FLEXCAN +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan1), okay) + /* Configure CAN1 using Osc48MDiv2 */ + rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan3), okay) + /* Configure CAN1 using Osc48MDiv2 */ + rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); +#endif +#endif + +#ifdef CONFIG_MCUX_ACMP +#if DT_NODE_HAS_STATUS(DT_NODELABEL(acmp1), okay) + /* Configure ACMP1 using Osc48MDiv2*/ + rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); +#endif +#endif + +#ifdef CONFIG_DISPLAY_MCUX_ELCDIF + rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out; + /* + * PLL2 is fixed at 528MHz. Use desired panel clock clock to + * calculate LCDIF clock. + */ + rootCfg.div = ((SYS_PLL2_FREQ / + DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), + clock_frequency)) + 1); + CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg); +#endif + +#ifdef CONFIG_COUNTER_MCUX_GPT + rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); + USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && CONFIG_USB_DC_NXP_EHCI + CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); + CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); + USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig); +#endif + +#if CONFIG_IMX_USDHC +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) + /* Configure USDHC1 using SysPll2Pfd2*/ + rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + CLOCK_EnableClock(kCLOCK_Usdhc1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) + /* Configure USDHC2 using SysPll2Pfd2*/ + rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); + CLOCK_EnableClock(kCLOCK_Usdhc2); +#endif +#endif + +#if !(DT_NODE_HAS_COMPAT(DT_CHOSEN(flash), nxp_imx_flexspi)) && \ + defined(CONFIG_MEMC_MCUX_FLEXSPI) && \ + DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay) + /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg); +#endif + + /* Keep core clock ungated during WFI */ + CCM->GPR_PRIVATE1_SET = 0x1; + /* Keep the system clock running so SYSTICK can wake up the system from + * wfi. + */ + GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_0, kGPC_RunMode); + GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_1, kGPC_RunMode); + GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_0, false); + GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_1, false); + +#if !defined(CONFIG_PM) + /* Enable the AHB clock while the CM7 is sleeping to allow debug access + * to TCM + */ + IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK; +#endif +} + +#if CONFIG_I2S_MCUX_SAI +void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, + uint32_t clk_pre_div, uint32_t clk_src_div) +{ + ARG_UNUSED(clk_pre_div); + + switch (clock_name) { + case IMX_CCM_SAI1_CLK: + CLOCK_SetRootClockMux(kCLOCK_Root_Sai1, clk_src); + CLOCK_SetRootClockDiv(kCLOCK_Root_Sai1, clk_src_div); + break; + case IMX_CCM_SAI2_CLK: + CLOCK_SetRootClockMux(kCLOCK_Root_Sai2, clk_src); + CLOCK_SetRootClockDiv(kCLOCK_Root_Sai2, clk_src_div); + break; + case IMX_CCM_SAI3_CLK: + CLOCK_SetRootClockMux(kCLOCK_Root_Sai3, clk_src); + CLOCK_SetRootClockDiv(kCLOCK_Root_Sai3, clk_src_div); + break; + case IMX_CCM_SAI4_CLK: + CLOCK_SetRootClockMux(kCLOCK_Root_Sai4, clk_src); + CLOCK_SetRootClockDiv(kCLOCK_Root_Sai4, clk_src_div); + break; + default: + return; + } +} +#endif + +#if CONFIG_MIPI_DSI +void imxrt_pre_init_display_interface(void) +{ + /* elcdif output to MIPI DSI */ + CLOCK_EnableClock(kCLOCK_Video_Mux); + VIDEO_MUX->VID_MUX_CTRL.CLR = VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK; + + /* Power on and isolation off. */ + PGMC_BPC4->BPC_POWER_CTRL |= (PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK | + PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK); + + /* Assert MIPI reset. */ + IOMUXC_GPR->GPR62 &= ~(IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK | + IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK | + IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK | + IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK); + + /* setup clock */ + const clock_root_config_t mipiEscClockConfig = { + .clockOff = false, + .mux = 4, + .div = 11, + }; + + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &mipiEscClockConfig); + + /* TX esc clock */ + const clock_group_config_t mipiEscClockGroupConfig = { + .clockOff = false, + .resetDiv = 2, + .div0 = 2, + }; + + CLOCK_SetGroupConfig(kCLOCK_Group_MipiDsi, &mipiEscClockGroupConfig); + + const clock_root_config_t mipiDphyRefClockConfig = { + .clockOff = false, + .mux = 1, + .div = 1, + }; + + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &mipiDphyRefClockConfig); + + /* Deassert PCLK and ESC reset. */ + IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK | + IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK); +} + +void imxrt_post_init_display_interface(void) +{ + /* deassert BYTE and DBI reset */ + IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK | + IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK); +} + +#endif + +/** + * + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * If dual core operation is enabled, the second core image will be loaded to RAM + * + * @return 0 + */ + +static int imxrt_init(void) +{ +#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) + /** + * Copy CM4 core from flash to memory. Note that depending on where the + * user decided to store CM4 code, this is likely going to read from the + * flexspi while using XIP. Provided we DO NOT WRITE TO THE FLEXSPI, + * this operation is safe. + * + * Note that this copy MUST occur before enabling the M7 caching to + * ensure the data is written directly to RAM (since the M4 core will use it) + */ + LISTIFY(SEGMENT_NUM, MEMCPY_SEGMENT, (;)); + /* Set the boot address for the second core */ + uint32_t boot_address = (uint32_t)(DT_REG_ADDR(DT_CHOSEN(zephyr_cpu1_region))); + /* Set VTOR for the CM4 core */ + IOMUXC_LPSR_GPR->GPR0 = IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(boot_address >> 3u); + IOMUXC_LPSR_GPR->GPR1 = IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(boot_address >> 16u); +#endif + +#if DUAL_CORE_MU_ENABLED && CONFIG_CPU_CORTEX_M4 + /* Set boot flag in messaging unit to indicate boot to primary core */ + MU_SetFlags(MU_BASE, BOOT_FLAG); +#endif + + +#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) + sys_cache_instr_enable(); + sys_cache_data_enable(); +#endif + + /* Initialize system clock */ + clock_init(); + + return 0; +} + +#ifdef CONFIG_PLATFORM_SPECIFIC_INIT +void z_arm_platform_init(void) +{ + SystemInit(); + +#if defined(FLEXRAM_RUNTIME_BANKS_USED) + /* Configure flexram if not running from RAM */ + memc_flexram_dt_partition(); +#endif +} +#endif + +SYS_INIT(imxrt_init, PRE_KERNEL_1, 0); + +#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) +/** + * @brief Kickoff secondary core. + * + * Kick the secondary core out of reset and wait for it to indicate boot. The + * core image was already copied to RAM (and the boot address was set) in + * imxrt_init() + * + * @return 0 + */ +static int second_core_boot(void) +{ + /* Kick CM4 core out of reset */ + SRC->CTRL_M4CORE = SRC_CTRL_M4CORE_SW_RESET_MASK; + SRC->SCR |= SRC_SCR_BT_RELEASE_M4_MASK; +#if DUAL_CORE_MU_ENABLED + /* Wait for the secondary core to start up and set boot flag in + * imxrt_init + */ + while (MU_GetFlags(MU_BASE) != BOOT_FLAG) { + /* Wait for secondary core to set flag */ + } +#endif + return 0; +} + +SYS_INIT(second_core_boot, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +#endif diff --git a/soc/nxp/imxrt/imxrt11xx/soc.h b/soc/nxp/imxrt/imxrt11xx/soc.h new file mode 100644 index 00000000000..88b34454179 --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/soc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#include + +#ifndef _ASMLANGUAGE + +#include + +/* Add include for DTS generated information */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_I2S_MCUX_SAI +void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, + uint32_t clk_pre_div, uint32_t clk_src_div); + +#endif + +#if CONFIG_MIPI_DSI +void imxrt_pre_init_display_interface(void); + +void imxrt_post_init_display_interface(void); +#endif + +void flexspi_clock_set_div(uint32_t value); +uint32_t flexspi_clock_get_freq(void); + +#ifdef CONFIG_MEMC +uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/soc/nxp/imxrt/imxrt5xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt5xx/CMakeLists.txt new file mode 100644 index 00000000000..36e3874a8dc --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMXRT595S_CM33) + add_subdirectory(cm33) +elseif(CONFIG_SOC_MIMXRT595S_F1) + add_subdirectory(f1) +endif() diff --git a/soc/nxp/imxrt/imxrt5xx/Kconfig b/soc/nxp/imxrt/imxrt5xx/Kconfig new file mode 100644 index 00000000000..75f695d5cc5 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/Kconfig @@ -0,0 +1,85 @@ +# Copyright 2024 NXP +# Copyright (c) 2023 Google LLC. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMXRT595S_CM33 + select CPU_CORTEX_M33 + select CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select ARM + select HAS_PM + select HAS_POWEROFF + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_MCUX + select HAS_MCUX_SYSCON + select HAS_MCUX_FLEXCOMM + select HAS_MCUX_FLEXSPI + select HAS_MCUX_CACHE + select HAS_MCUX_LPC_DMA + select HAS_MCUX_LPADC + select HAS_MCUX_OS_TIMER + select HAS_MCUX_LPC_RTC + select HAS_MCUX_TRNG + select HAS_MCUX_SCTIMER + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_USB_LPCIP3511 + select HAS_MCUX_CTIMER + +config SOC_MIMXRT595S_F1 + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + +if SOC_SERIES_IMXRT5XX + +if NXP_IMXRT_BOOT_HEADER + +config IMAGE_VECTOR_TABLE_OFFSET + default 0x1000 + +endif # NXP_IMXRT_BOOT_HEADER + +config IMXRT5XX_CODE_CACHE + bool "Code cache" + default y + help + Enable code cache for FlexSPI region at boot. If this Kconfig is + cleared, the CACHE64 controller will be disabled during SOC init + +choice FLEXCOMM0_CLK_SRC + prompt "Clock source for Flexcomm0" + default FLEXCOMM0_CLK_SRC_FRG + +config FLEXCOMM0_CLK_SRC_FRG + bool "FRG is source of Flexcomm0 clock" + +config FLEXCOMM0_CLK_SRC_FRO + bool "FRO_DIV4 is source of Flexcomm0 clock" + +endchoice + +choice MIPI_DPHY_CLK_SRC + prompt "Clock source for MIPI DPHY" + default MIPI_DPHY_CLK_SRC_AUX1_PLL + +config MIPI_DPHY_CLK_SRC_AUX1_PLL + bool "AUX1_PLL is source of MIPI_DPHY clock" + +config MIPI_DPHY_CLK_SRC_FRO + bool "FRO 192/96M is source of MIPI_DPHY clock" + +endchoice + +config MCUX_CORE_SUFFIX + default "_cm33" if SOC_MIMXRT595S_CM33 + default "_dsp" if SOC_MIMXRT595S_F1 + +endif # SOC_SERIES_IMXRT5XX diff --git a/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig new file mode 100644 index 00000000000..e99289a1320 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig @@ -0,0 +1,119 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMXRT595S_CM33 + +config ROM_START_OFFSET + default 0x1200 if NXP_IMXRT_BOOT_HEADER + +# The PVT Sensor uses IRQ #75. For more details, see +# https://www.nxp.com/design/design-center/software/embedded-software/application-software-packs/application-software-pack-dynamic-voltage-scaling-using-pvt-sensor:APP-SW-PACK-DVS-PVT-SENSOR +config NUM_IRQS + default 76 + +config ZTEST_NO_YIELD + default y if (PM && ZTEST) + +# Code relocation is needed for flash clock setup +config CODE_DATA_RELOCATION_SRAM + default y + +# +# MBEDTLS is larger but much faster than TinyCrypt so choose wisely +# +config MBEDTLS +#config TINYCRYPT + default y if CSPRNG_ENABLED + depends on ENTROPY_GENERATOR + +if MBEDTLS +# +# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than +# what the ztest_thread_stack defaults to. +# +config TEST_EXTRA_STACK_SIZE + int + default 1024 +endif # MBEDTLS + +if MCUX_OS_TIMER + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +endif # MCUX_OS_TIMER + +if CORTEX_M_SYSTICK + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 250105263 + +endif # CORTEX_M_SYSTICK + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +if PM_DEVICE +# Enable the MEMC FlexSPI driver when using device power +# management so we can reconfigure the FlexSPI pins to +# save power. The MEMC FlexSPI driver is enabled when we +# enable the Flash subsystem, however we would like to +# reconfigure the FlexSPI pins even when the Flash driver +# is disabled, hence MEMC is selected when PM_DEVICE +# is turned on. +config MEMC + default y + select MEMC_MCUX_FLEXSPI + +endif + +endif # SOC_MIMXRT595S_CM33 + +if SOC_MIMXRT595S_F1 + +config SMP + default n + +config XTENSA_TIMER + default y + +config KERNEL_ENTRY + default "__start" + +config MULTI_LEVEL_INTERRUPTS + default n + +config 2ND_LEVEL_INTERRUPTS + default n + +# To prevent test uses TEST_LOGGING_MINIMAL +config TEST_LOGGING_DEFAULTS + default n + depends on TEST + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 198000000 + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config DYNAMIC_INTERRUPTS + default n + +config CACHE + default n + +config DCACHE + default n + +config CACHE_MANAGEMENT + default n + +config LOG + default n + +endif # SOC_MIMXRT595S_F1 diff --git a/soc/nxp/imxrt/imxrt5xx/Kconfig.soc b/soc/nxp/imxrt/imxrt5xx/Kconfig.soc new file mode 100644 index 00000000000..6b2c58f5753 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/Kconfig.soc @@ -0,0 +1,60 @@ +# i.MX RT5XX Series + +# Copyright 2022-2024, NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT5XX + bool + select SOC_FAMILY_NXP_IMXRT + +config SOC_MIMXRT595S + bool + select SOC_SERIES_IMXRT5XX + +config SOC_MIMXRT595S_CM33 + bool + select SOC_MIMXRT595S + help + NXP RT5xx CM33 core + +config SOC_MIMXRT595S_F1 + bool + select SOC_MIMXRT595S + help + NXP RT5xx ADSP Series + +config SOC_SERIES + default "imxrt5xx" if SOC_SERIES_IMXRT5XX + +config SOC + default "mimxrt595s" if SOC_MIMXRT595S + +config SOC_TOOLCHAIN_NAME + string + default "nxp_rt500_adsp" if SOC_MIMXRT595S_F1 + +config SOC_PART_NUMBER_MIMXRT533SFFOC + bool + +config SOC_PART_NUMBER_MIMXRT555SFFOC + bool + +config SOC_PART_NUMBER_MIMXRT595SFFOC + bool + +config SOC_PART_NUMBER_MIMXRT533SFAWC + bool + +config SOC_PART_NUMBER_MIMXRT555SFAWC + bool + +config SOC_PART_NUMBER_MIMXRT595SFAWC + bool + +config SOC_PART_NUMBER + default "MIMXRT533SFAWC" if SOC_PART_NUMBER_MIMXRT533SFAWC + default "MIMXRT555SFAWC" if SOC_PART_NUMBER_MIMXRT555SFAWC + default "MIMXRT595SFAWC" if SOC_PART_NUMBER_MIMXRT595SFAWC + default "MIMXRT533SFFOC" if SOC_PART_NUMBER_MIMXRT533SFFOC + default "MIMXRT555SFFOC" if SOC_PART_NUMBER_MIMXRT555SFFOC + default "MIMXRT595SFFOC" if SOC_PART_NUMBER_MIMXRT595SFFOC diff --git a/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt b/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt new file mode 100644 index 00000000000..c47971c8ccc --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt @@ -0,0 +1,29 @@ +# +# Copyright 2022,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_compile_definitions(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) + +zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + flash_clock_setup.c + ) + +zephyr_sources_ifdef(CONFIG_PM power.c) + +zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) + +zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/rt5xx/flash_clock_setup.c b/soc/nxp/imxrt/imxrt5xx/cm33/flash_clock_setup.c similarity index 100% rename from soc/arm/nxp_imx/rt5xx/flash_clock_setup.c rename to soc/nxp/imxrt/imxrt5xx/cm33/flash_clock_setup.c diff --git a/soc/arm/nxp_imx/rt5xx/flash_clock_setup.h b/soc/nxp/imxrt/imxrt5xx/cm33/flash_clock_setup.h similarity index 100% rename from soc/arm/nxp_imx/rt5xx/flash_clock_setup.h rename to soc/nxp/imxrt/imxrt5xx/cm33/flash_clock_setup.h diff --git a/soc/arm/nxp_imx/rt5xx/linker.ld b/soc/nxp/imxrt/imxrt5xx/cm33/linker.ld similarity index 100% rename from soc/arm/nxp_imx/rt5xx/linker.ld rename to soc/nxp/imxrt/imxrt5xx/cm33/linker.ld diff --git a/soc/arm/nxp_imx/rt5xx/pinctrl_soc.h b/soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/rt5xx/pinctrl_soc.h rename to soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/rt5xx/power.c b/soc/nxp/imxrt/imxrt5xx/cm33/power.c similarity index 100% rename from soc/arm/nxp_imx/rt5xx/power.c rename to soc/nxp/imxrt/imxrt5xx/cm33/power.c diff --git a/soc/arm/nxp_imx/rt5xx/poweroff.c b/soc/nxp/imxrt/imxrt5xx/cm33/poweroff.c similarity index 100% rename from soc/arm/nxp_imx/rt5xx/poweroff.c rename to soc/nxp/imxrt/imxrt5xx/cm33/poweroff.c diff --git a/soc/nxp/imxrt/imxrt5xx/cm33/soc.c b/soc/nxp/imxrt/imxrt5xx/cm33/soc.c new file mode 100644 index 00000000000..4b420ea46d4 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/cm33/soc.c @@ -0,0 +1,544 @@ +/* + * Copyright 2022-2023, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for NXP RT5XX platform + * + * This module provides routines to initialize and support board-level + * hardware for the RT5XX platforms. + */ + +#include +#include +#include +#include +#include "fsl_power.h" +#include "fsl_clock.h" +#include + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP +#include "flash_clock_setup.h" +#endif + +#if CONFIG_USB_DC_NXP_LPCIP3511 +#include "usb_phy.h" +#include "usb.h" +#endif + +/* Board System oscillator settling time in us */ +#define BOARD_SYSOSC_SETTLING_US 100U +/* Board xtal frequency in Hz */ +#define BOARD_XTAL_SYS_CLK_HZ 24000000U +/* Core clock frequency: 198000000Hz */ +#define CLOCK_INIT_CORE_CLOCK 198000000U + +#define CTIMER_CLOCK_SOURCE(node_id) \ + TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source)) +#define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val) +#define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val) +#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id)); + +const clock_sys_pll_config_t g_sysPllConfig_clock_init = { + /* OSC clock */ + .sys_pll_src = kCLOCK_SysPllXtalIn, + /* Numerator of the SYSPLL0 fractional loop divider is 0 */ + .numerator = 0, + /* Denominator of the SYSPLL0 fractional loop divider is 1 */ + .denominator = 1, + /* Divide by 22 */ + .sys_pll_mult = kCLOCK_SysPllMult22 +}; + +const clock_audio_pll_config_t g_audioPllConfig_clock_init = { + /* OSC clock */ + .audio_pll_src = kCLOCK_AudioPllXtalIn, + /* Numerator of the Audio PLL fractional loop divider is 0 */ + .numerator = 5040, + /* Denominator of the Audio PLL fractional loop divider is 1 */ + .denominator = 27000, + /* Divide by 22 */ + .audio_pll_mult = kCLOCK_AudioPllMult22 +}; + +const clock_frg_clk_config_t g_frg0Config_clock_init = { + .num = 0, + .sfg_clock_src = kCLOCK_FrgPllDiv, + .divider = 255U, + .mult = 0 +}; + +const clock_frg_clk_config_t g_frg12Config_clock_init = { + .num = 12, + .sfg_clock_src = kCLOCK_FrgMainClk, + .divider = 255U, + .mult = 167 +}; + +#if CONFIG_USB_DC_NXP_LPCIP3511 +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) +#endif + +/* System clock frequency. */ +extern uint32_t SystemCoreClock; +/* Main stack pointer */ +extern char z_main_stack[]; + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +extern char _flash_used[]; + +extern void z_arm_reset(void); +extern void z_arm_nmi(void); +extern void z_arm_hard_fault(void); +extern void z_arm_mpu_fault(void); +extern void z_arm_bus_fault(void); +extern void z_arm_usage_fault(void); +extern void z_arm_secure_fault(void); +extern void z_arm_svc(void); +extern void z_arm_debug_monitor(void); +extern void z_arm_pendsv(void); +extern void sys_clock_isr(void); +extern void z_arm_exc_spurious(void); + +__imx_boot_ivt_section void (* const image_vector_table[])(void) = { + (void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */ + z_arm_reset, /* 0x04 */ + z_arm_nmi, /* 0x08 */ + z_arm_hard_fault, /* 0x0C */ + z_arm_mpu_fault, /* 0x10 */ + z_arm_bus_fault, /* 0x14 */ + z_arm_usage_fault, /* 0x18 */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + z_arm_secure_fault, /* 0x1C */ +#else + z_arm_exc_spurious, +#endif /* CONFIG_ARM_SECURE_FIRMWARE */ + (void (*)())_flash_used, /* 0x20, imageLength. */ + 0, /* 0x24, imageType (Plain Image) */ + 0, /* 0x28, authBlockOffset/crcChecksum */ + z_arm_svc, /* 0x2C */ + z_arm_debug_monitor, /* 0x30 */ + (void (*)())image_vector_table, /* 0x34, imageLoadAddress. */ + z_arm_pendsv, /* 0x38 */ +#if defined(CONFIG_SYS_CLOCK_EXISTS) && \ + defined(CONFIG_CORTEX_M_SYSTICK_INSTALL_ISR) + sys_clock_isr, /* 0x3C */ +#else + z_arm_exc_spurious, +#endif +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ + +#if CONFIG_USB_DC_NXP_LPCIP3511 + +static void usb_device_clock_init(void) +{ + uint8_t usbClockDiv = 1; + uint32_t usbClockFreq; + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; + + /* Make sure USBHS ram buffer and usb1 phy has power up */ + POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM); + POWER_ApplyPD(); + + RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_DEVICE_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_HOST_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_SRAM_RST_SHIFT_RSTn); + + /* enable usb ip clock */ + CLOCK_EnableUsbHs0DeviceClock(kOSC_CLK_to_USB_CLK, usbClockDiv); + /* save usb ip clock freq*/ + usbClockFreq = g_xtalFreq / usbClockDiv; + CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4); + /* enable usb ram clock */ + CLOCK_EnableClock(kCLOCK_UsbhsSram); + /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ + CLOCK_EnableUsbHs0PhyPllClock(kOSC_CLK_to_USB_CLK, usbClockFreq); + + /* USB PHY initialization */ + USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, BOARD_XTAL_SYS_CLK_HZ, &phyConfig); + +#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM) + for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++) { + ((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U; + } +#endif + + /* The following code should run after phy initialization and should wait + * some microseconds to make sure utmi clock valid + */ + /* enable usb1 host clock */ + CLOCK_EnableClock(kCLOCK_UsbhsHost); + /* Wait until host_needclk de-asserts */ + while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { + __ASM("nop"); + } + /* According to reference mannual, device mode setting has to be set by access + * usb host register + */ + USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; + /* disable usb1 host clock */ + CLOCK_DisableClock(kCLOCK_UsbhsHost); +} + +#endif + +void z_arm_platform_init(void) +{ +#ifndef CONFIG_NXP_IMXRT_BOOT_HEADER + /* + * If boot did not proceed using a boot header, we should not assume + * the core is in reset state. Disable the MPU and correctly + * set the stack pointer, since we are about to push to + * the stack when we call SystemInit + */ + /* Clear stack limit registers */ + __set_MSPLIM(0); + __set_PSPLIM(0); + /* Disable MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + /* Set stack pointer */ + __set_MSP((uint32_t)(z_main_stack + CONFIG_MAIN_STACK_SIZE)); +#endif /* !CONFIG_NXP_IMXRT_BOOT_HEADER */ + /* This is provided by the SDK */ + SystemInit(); +} + +/* Weak so that board can override with their own clock init routine. */ +void __weak rt5xx_clock_init(void) +{ + /* Configure LPOSC 1M */ + /* Power on LPOSC (1MHz) */ + POWER_DisablePD(kPDRUNCFG_PD_LPOSC); + /* Wait until LPOSC stable */ + CLOCK_EnableLpOscClk(); + + /* Configure FRO clock source */ + /* Power on FRO (192MHz or 96MHz) */ + POWER_DisablePD(kPDRUNCFG_PD_FFRO); + /* FRO_DIV1 is always enabled and used as Main clock during PLL update. */ + /* Enable all FRO outputs */ + CLOCK_EnableFroClk(kCLOCK_FroAllOutEn); + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP + /* + * Call function flexspi_clock_safe_config() to move FlexSPI clock to a stable + * clock source to avoid instruction/data fetch issue when updating PLL and Main + * clock if XIP(execute code on FLEXSPI memory). + */ + flexspi_clock_safe_config(); +#endif + + /* Let CPU run on FRO with divider 2 for safe switching. */ + CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2); + CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK); + + /* Configure SYSOSC clock source. */ + /* Power on SYSXTAL */ + POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); + /* Updated XTAL oscillator settling time */ + POWER_UpdateOscSettlingTime(BOARD_SYSOSC_SETTLING_US); + /* Enable system OSC */ + CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US); + /* Sets external XTAL OSC freq */ + CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ); + + /* Configure SysPLL0 clock source. */ + CLOCK_InitSysPll(&g_sysPllConfig_clock_init); + /* Enable MAIN PLL clock */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 24); + /* Enable AUX0 PLL clock */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + + /* Configure Audio PLL clock source. */ + CLOCK_InitAudioPll(&g_audioPllConfig_clock_init); + /* Enable Audio PLL clock */ + CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); + + /* Set SYSCPUAHBCLKDIV divider to value 2 */ + CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); + + /* Setup FRG0 clock */ + CLOCK_SetFRGClock(&g_frg0Config_clock_init); + /* Setup FRG12 clock */ + CLOCK_SetFRGClock(&g_frg12Config_clock_init); + + /* Set up clock selectors - Attach clocks to the peripheries. */ + /* Switch MAIN_CLK to MAIN_PLL */ + CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); + /* Switch SYSTICK_CLK to MAIN_CLK_DIV */ + CLOCK_AttachClk(kMAIN_CLK_DIV_to_SYSTICK_CLK); +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay) + #ifdef CONFIG_FLEXCOMM0_CLK_SRC_FRG + /* Switch FLEXCOMM0 to FRG */ + CLOCK_AttachClk(kFRG_to_FLEXCOMM0); + #elif defined(CONFIG_FLEXCOMM0_CLK_SRC_FRO) + CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM0); + #endif +#endif +#if CONFIG_USB_DC_NXP_LPCIP3511 + usb_device_clock_init(); +#endif + +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay) && CONFIG_I2S) + /* attach AUDIO PLL clock to FLEXCOMM1 (I2S1) */ + CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM1); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay) && CONFIG_I2S) + /* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */ + CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay) + /* Switch FLEXCOMM4 to FRO_DIV4 */ + CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM4); +#endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(i3c0), nxp_mcux_i3c, okay) + /* Attach main clock to I3C, divider will be set in i3c_mcux.c */ + CLOCK_AttachClk(kMAIN_CLK_to_I3C_CLK); + CLOCK_AttachClk(kLPOSC_to_I3C_TC_CLK); +#endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(hs_spi1), nxp_lpc_spi, okay) + CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM16); +#endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm12), nxp_lpc_usart, okay) + /* Switch FLEXCOMM12 to FRG */ + CLOCK_AttachClk(kFRG_to_FLEXCOMM12); +#endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pmic_i2c), nxp_lpc_i2c, okay) + CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM15); +#endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lcdif), nxp_dcnano_lcdif, okay) && CONFIG_DISPLAY + POWER_DisablePD(kPDRUNCFG_APD_DCNANO_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_DCNANO_SRAM); + POWER_ApplyPD(); + + CLOCK_AttachClk(kAUX0_PLL_to_DCPIXEL_CLK); + /* Note- pixel clock follows formula + * (height + VSW + VFP + VBP) * (width + HSW + HFP + HBP) * frame rate. + * this means the clock divider will vary depending on + * the attached display. + * + * The root clock used here is the AUX0 PLL (PLL0 PFD2). + */ + CLOCK_SetClkDiv(kCLOCK_DivDcPixelClk, + ((CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / + DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), + clock_frequency)) + 1)); + + CLOCK_EnableClock(kCLOCK_DisplayCtrl); + RESET_ClearPeripheralReset(kDISP_CTRL_RST_SHIFT_RSTn); + + CLOCK_EnableClock(kCLOCK_AxiSwitch); + RESET_ClearPeripheralReset(kAXI_SWITCH_RST_SHIFT_RSTn); +#if defined(CONFIG_MEMC) && DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexspi2), \ + nxp_imx_flexspi, okay) + /* Enable write-through for FlexSPI1 space */ + CACHE64_POLSEL0->REG1_TOP = 0x27FFFC00U; + CACHE64_POLSEL0->POLSEL = 0x11U; +#endif +#endif + + /* Switch CLKOUT to FRO_DIV2 */ + CLOCK_AttachClk(kFRO_DIV2_to_CLKOUT); + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC + /* Make sure USDHC ram buffer has been power up*/ + POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PD_LPOSC); + POWER_ApplyPD(); + + /* usdhc depend on 32K clock also */ + CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK); + CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK); + CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1); + CLOCK_EnableClock(kCLOCK_Sdio0); + RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(smartdma), okay) && CONFIG_DMA_MCUX_SMARTDMA + /* Power up SMARTDMA ram */ + POWER_DisablePD(kPDRUNCFG_APD_SMARTDMA_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_SMARTDMA_SRAM); + POWER_ApplyPD(); + + RESET_ClearPeripheralReset(kSMART_DMA_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_Smartdma); +#endif + + DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP) + + /* Set up dividers. */ + /* Set AUDIOPLLCLKDIV divider to value 15 */ + CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); + /* Set FRGPLLCLKDIV divider to value 11 */ + CLOCK_SetClkDiv(kCLOCK_DivPLLFRGClk, 11U); + /* Set SYSTICKFCLKDIV divider to value 2 */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 2U); + /* Set PFC0DIV divider to value 2 */ + CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); + /* Set PFC1DIV divider to value 4 */ + CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4U); + /* Set CLKOUTFCLKDIV divider to value 100 */ + CLOCK_SetClkDiv(kCLOCK_DivClockOut, 100U); + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP + /* + * Call function flexspi_setup_clock() to set user configured clock source/divider + * for FlexSPI. + */ + flexspi_setup_clock(FLEXSPI0, 0U, 2U); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexspi2), nxp_imx_flexspi, okay) + /* Power up FlexSPI1 SRAM */ + POWER_DisablePD(kPDRUNCFG_APD_FLEXSPI1_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_FLEXSPI1_SRAM); + POWER_ApplyPD(); + /* Setup clock frequency for FlexSPI1 */ + CLOCK_AttachClk(kMAIN_CLK_to_FLEXSPI1_CLK); + CLOCK_SetClkDiv(kCLOCK_DivFlexspi1Clk, 1); + /* Reset peripheral module */ + RESET_PeripheralReset(kFLEXSPI1_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpadc0), nxp_lpc_lpadc, okay) + SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK; + SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK; + RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); + CLOCK_AttachClk(kFRO_DIV4_to_ADC_CLK); + CLOCK_SetClkDiv(kCLOCK_DivAdcClk, 1); +#endif + +#if CONFIG_COUNTER_NXP_MRT + RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay) + /* Using the Audio PLL as input clock leads to better clock dividers + * for typical PCM sample rates ({8,16,24,32,48,96} kHz. + */ + /* DMIC source from audio pll, divider 8, 24.576M/8=3.072MHZ + * Select Audio PLL as clock source. This should produce a bit clock + * of 3.072MHZ + */ + CLOCK_AttachClk(kAUDIO_PLL_to_DMIC); + CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 8); + +#endif + + /* Set SystemCoreClock variable. */ + SystemCoreClock = CLOCK_INIT_CORE_CLOCK; + + /* Set main clock to FRO as deep sleep clock by default. */ + POWER_SetDeepSleepClock(kDeepSleepClk_Fro); +} + +#if CONFIG_MIPI_DSI +/* Weak so board can override this function */ +void __weak imxrt_pre_init_display_interface(void) +{ + /* Assert MIPI DPHY reset. */ + RESET_SetPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); + POWER_DisablePD(kPDRUNCFG_APD_MIPIDSI_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_MIPIDSI_SRAM); + POWER_DisablePD(kPDRUNCFG_PD_MIPIDSI); + POWER_ApplyPD(); + + /* RxClkEsc max 60MHz, TxClkEsc 12 to 20MHz. */ + CLOCK_AttachClk(kFRO_DIV1_to_MIPI_DPHYESC_CLK); + /* RxClkEsc = 192MHz / 4 = 48MHz. */ + CLOCK_SetClkDiv(kCLOCK_DivDphyEscRxClk, 4); + /* TxClkEsc = 192MHz / 4 / 3 = 16MHz. */ + CLOCK_SetClkDiv(kCLOCK_DivDphyEscTxClk, 3); + + /* + * The DPHY bit clock must be fast enough to send out the pixels, + * it should be larger than: + * + * (Pixel clock * bit per output pixel) / number of MIPI data lane + * + * DPHY supports up to 895.1MHz bit clock. + * We set the divider of the PFD3 output of the SYSPLL, which has a + * fixed multiplied of 18, and use this output frequency for the DPHY. + */ + +#ifdef CONFIG_MIPI_DPHY_CLK_SRC_AUX1_PLL + /* Note: AUX1 PLL clock is system pll clock * 18 / pfd. + * system pll clock is configured at 528MHz by default. + */ + CLOCK_AttachClk(kAUX1_PLL_to_MIPI_DPHY_CLK); + CLOCK_InitSysPfd(kCLOCK_Pfd3, + ((CLOCK_GetSysPllFreq() * 18ull) / + ((unsigned long long)(DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock))))); + CLOCK_SetClkDiv(kCLOCK_DivDphyClk, 1); +#elif defined(CONFIG_MIPI_DPHY_CLK_SRC_FRO) + CLOCK_AttachClk(kFRO_DIV1_to_MIPI_DPHY_CLK); + CLOCK_SetClkDiv(kCLOCK_DivDphyClk, + (CLK_FRO_CLK / DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock))); +#endif + /* Clear DSI control reset (Note that DPHY reset is cleared later)*/ + RESET_ClearPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn); +} + +void __weak imxrt_post_init_display_interface(void) +{ + /* Deassert MIPI DPHY reset. */ + RESET_ClearPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); +} + +void __weak imxrt_deinit_display_interface(void) +{ + /* Assert MIPI DPHY and DSI reset */ + RESET_SetPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); + RESET_SetPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn); + /* Remove clock from DPHY */ + CLOCK_AttachClk(kNONE_to_MIPI_DPHY_CLK); +} + + +#endif + +/** + * + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * + * @return 0 + */ +static int nxp_rt500_init(void) +{ + /* Initialize clocks with tool generated code */ + rt5xx_clock_init(); + +#ifndef CONFIG_IMXRT5XX_CODE_CACHE + CACHE64_DisableCache(CACHE64_CTRL0); +#endif + + /* Some ROM versions may have errata leaving these pins in a non-reset state, + * which can often cause power leakage on most expected board designs, + * restore the reset state here and leave the pin configuration up to board/user DT + */ + IOPCTL->PIO[1][15] = 0; + IOPCTL->PIO[3][28] = 0; + IOPCTL->PIO[3][29] = 0; + + return 0; +} + +SYS_INIT(nxp_rt500_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_imx/rt5xx/soc.h b/soc/nxp/imxrt/imxrt5xx/cm33/soc.h similarity index 100% rename from soc/arm/nxp_imx/rt5xx/soc.h rename to soc/nxp/imxrt/imxrt5xx/cm33/soc.h diff --git a/soc/arm/nxp_imx/rt5xx/usb.ld b/soc/nxp/imxrt/imxrt5xx/cm33/usb.ld similarity index 100% rename from soc/arm/nxp_imx/rt5xx/usb.ld rename to soc/nxp/imxrt/imxrt5xx/cm33/usb.ld diff --git a/soc/nxp/imxrt/imxrt5xx/f1/CMakeLists.txt b/soc/nxp/imxrt/imxrt5xx/f1/CMakeLists.txt new file mode 100644 index 00000000000..f54b5dd53a4 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/f1/CMakeLists.txt @@ -0,0 +1,23 @@ +# NXP RT SoC family CMake file +# +# Copyright (c) 2021 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_compile_definitions(CPU_MIMXRT595SFFOC_dsp) + +zephyr_include_directories(include) + +# west sign + +add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri +) + +add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} +) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/xtensa/nxp_adsp/rt5xx/include/_soc_inthandlers.h b/soc/nxp/imxrt/imxrt5xx/f1/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/nxp_adsp/rt5xx/include/_soc_inthandlers.h rename to soc/nxp/imxrt/imxrt5xx/f1/include/_soc_inthandlers.h diff --git a/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/cache.h b/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/cache.h new file mode 100644 index 00000000000..067c0890140 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/cache.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __COMMON_ADSP_CACHE_H__ +#define __COMMON_ADSP_CACHE_H__ + +#include + +#endif diff --git a/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/io.h b/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/io.h new file mode 100644 index 00000000000..3d1f0ed98d5 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/io.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INCLUDE_IO__ +#define __INCLUDE_IO__ + +#include +#include +#include +#include + +static inline uint32_t io_reg_read(uint32_t reg) +{ + return sys_read32(reg); +} + +static inline void io_reg_write(uint32_t reg, uint32_t val) +{ + sys_write32(val, reg); +} + +static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, + uint32_t value) +{ + io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); +} + +static inline uint16_t io_reg_read16(uint32_t reg) +{ + return sys_read16(reg); +} + +static inline void io_reg_write16(uint32_t reg, uint16_t val) +{ + sys_write16(val, reg); +} + +#endif diff --git a/soc/nxp/imxrt/imxrt5xx/f1/include/soc.h b/soc/nxp/imxrt/imxrt5xx/f1/include/soc.h new file mode 100644 index 00000000000..89ee9d96a52 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/f1/include/soc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include + +#ifndef __INC_IMX_SOC_H +#define __INC_IMX_SOC_H + +/* Macros related to interrupt handling */ +#define XTENSA_IRQ_NUM_SHIFT 0 +#define XTENSA_IRQ_NUM_MASK 0xff + +/* + * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00. + * + * 1. Peripheral Register bit offset. + */ +#define XTENSA_IRQ_NUMBER(_irq) \ + ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) + +extern void z_soc_irq_enable(uint32_t irq); +extern void z_soc_irq_disable(uint32_t irq); +extern int z_soc_irq_is_enabled(unsigned int irq); + +#endif /* __INC_IMX_SOC_H */ diff --git a/soc/xtensa/nxp_adsp/rt5xx/include/soc/memory.h b/soc/nxp/imxrt/imxrt5xx/f1/include/soc/memory.h similarity index 100% rename from soc/xtensa/nxp_adsp/rt5xx/include/soc/memory.h rename to soc/nxp/imxrt/imxrt5xx/f1/include/soc/memory.h diff --git a/soc/xtensa/nxp_adsp/rt5xx/linker.ld b/soc/nxp/imxrt/imxrt5xx/f1/linker.ld similarity index 100% rename from soc/xtensa/nxp_adsp/rt5xx/linker.ld rename to soc/nxp/imxrt/imxrt5xx/f1/linker.ld diff --git a/soc/nxp/imxrt/imxrt6xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt6xx/CMakeLists.txt new file mode 100644 index 00000000000..7ed2c42c708 --- /dev/null +++ b/soc/nxp/imxrt/imxrt6xx/CMakeLists.txt @@ -0,0 +1,26 @@ +# +# Copyright (c) 2020, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(.) + +zephyr_sources(soc.c) + +zephyr_sources_ifdef(CONFIG_PM power.c) + +zephyr_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_XIP flash_clock_setup.c) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) + +zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) + +if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) + zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM) +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig b/soc/nxp/imxrt/imxrt6xx/Kconfig new file mode 100644 index 00000000000..eeeb3ab7af4 --- /dev/null +++ b/soc/nxp/imxrt/imxrt6xx/Kconfig @@ -0,0 +1,65 @@ +# Copyright 2020, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT6XX + select ARM + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select CLOCK_CONTROL + select CODE_DATA_RELOCATION_SRAM if FLASH_MCUX_FLEXSPI_XIP + select PLATFORM_SPECIFIC_INIT + select HAS_PM + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_MCUX + select HAS_MCUX_SYSCON + select HAS_MCUX_FLEXCOMM + select HAS_MCUX_FLEXSPI + select HAS_MCUX_CACHE + select HAS_MCUX_LPC_DMA + select HAS_MCUX_LPADC + select HAS_MCUX_OS_TIMER + select HAS_MCUX_LPC_RTC + select HAS_MCUX_TRNG + select HAS_MCUX_SCTIMER + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select INIT_SYS_PLL + select HAS_MCUX_USB_LPCIP3511 + select HAS_MCUX_CTIMER + +if SOC_SERIES_IMXRT6XX + +config MCUX_CORE_SUFFIX + default "_cm33" if SOC_MIMXRT685S_CM33 + +config INIT_SYS_PLL + bool "Initialize SYS PLL" + +config INIT_AUDIO_PLL + bool "Initialize Audio PLL" + +config XTAL_SYS_CLK_HZ + int "External oscillator frequency" + help + Set the external oscillator frequency in Hz. This should be set by the + board's defconfig. + +config SYSOSC_SETTLING_US + int "System oscillator settling time" + help + Set the board system oscillator settling time in us. This should be set by the + board's defconfig. + +config IMXRT6XX_CODE_CACHE + bool "Code cache" + default y + help + Enable code cache for FlexSPI region at boot. If this Kconfig is + cleared, the CACHE64 controller will be disabled during SOC init + +endif diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig new file mode 100644 index 00000000000..2133577418d --- /dev/null +++ b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig @@ -0,0 +1,113 @@ +# i.MX RT6XX series configuration options + +# Copyright 2020, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMXRT6XX + +# alias for hal +config SOC_SERIES_IMX_RT6XX + bool + default y + +# another alias for hal +config SOC_SERIES_IMXRT_6XX + bool + default y + +config ROM_START_OFFSET + default 0x1200 if NXP_IMXRT_BOOT_HEADER + +config NUM_IRQS + default 60 + +config ZTEST_NO_YIELD + default y if (ZTEST && PM) + +# Setup LMA adjustment if using the RAMLOADER feature of ROM +FLASH_CHOSEN := zephyr,flash +FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) +FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1) +config BUILD_OUTPUT_ADJUST_LMA + default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER + +# The base address is determined from the zephyr,flash node with the following +# precedence: +# FlexSPI base address (if flash node is on a FlexSPI bus) +# node reg property (used for memory regions such as SRAM) + +# Workaround for not being able to have commas in macro arguments + +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi + +# Macros to shorten Kconfig definitions +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +# The RT6xx has no internal flash. If the flash node has a size property, +# use that over the reg property. This is used for the external flash +# present on the board. Otherwise, fallback to the reg property +config FLASH_SIZE + default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ + if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +if FLASH_MCUX_FLEXSPI_XIP + +# Avoid RWW hazards by defaulting logging to disabled +choice FLASH_LOG_LEVEL_CHOICE + default FLASH_LOG_LEVEL_OFF +endchoice + +choice MEMC_LOG_LEVEL_CHOICE + default MEMC_LOG_LEVEL_OFF +endchoice + +endif + +# +# MBEDTLS is larger but much faster than TinyCrypt so choose wisely +# +config MBEDTLS +#config TINYCRYPT + default y if CSPRNG_ENABLED + depends on ENTROPY_GENERATOR + +if MBEDTLS +# +# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than +# what the ztest_thread_stack defaults to. +# +config TEST_EXTRA_STACK_SIZE + int + default 1024 +endif # MBEDTLS + +config I2S_MCUX_FLEXCOMM + select INIT_AUDIO_PLL + +if MCUX_OS_TIMER + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +endif # MCUX_OS_TIMER + +if CORTEX_M_SYSTICK + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 250105263 + +endif # CORTEX_M_SYSTICK + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +endif # SOC_SERIES_MIMXRT6XX diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig.soc b/soc/nxp/imxrt/imxrt6xx/Kconfig.soc new file mode 100644 index 00000000000..14cb945b36e --- /dev/null +++ b/soc/nxp/imxrt/imxrt6xx/Kconfig.soc @@ -0,0 +1,33 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT6XX + bool + select SOC_FAMILY_NXP_IMXRT + +config SOC_SERIES + default "imxrt6xx" if SOC_SERIES_IMXRT6XX + +config SOC_MIMXRT685S_CM33 + bool + select SOC_SERIES_IMXRT6XX + +config SOC + default "mimxrt685s" if SOC_MIMXRT685S_CM33 + +config SOC_PART_NUMBER_MIMXRT685SFVKB + bool + select SOC_MIMXRT685S_CM33 + +config SOC_PART_NUMBER_MIMXRT685SFFOB + bool + select SOC_MIMXRT685S_CM33 + +config SOC_PART_NUMBER_MIMXRT685SFAWBR + bool + select SOC_MIMXRT685S_CM33 + +config SOC_PART_NUMBER + default "MIMXRT685SFVKB" if SOC_PART_NUMBER_MIMXRT685SFVKB + default "MIMXRT685SFFOB" if SOC_PART_NUMBER_MIMXRT685SFFOB + default "MIMXRT685SFAWBR" if SOC_PART_NUMBER_MIMXRT685SFAWBR diff --git a/soc/arm/nxp_imx/rt6xx/flash_clock_setup.c b/soc/nxp/imxrt/imxrt6xx/flash_clock_setup.c similarity index 100% rename from soc/arm/nxp_imx/rt6xx/flash_clock_setup.c rename to soc/nxp/imxrt/imxrt6xx/flash_clock_setup.c diff --git a/soc/arm/nxp_imx/rt6xx/flash_clock_setup.h b/soc/nxp/imxrt/imxrt6xx/flash_clock_setup.h similarity index 100% rename from soc/arm/nxp_imx/rt6xx/flash_clock_setup.h rename to soc/nxp/imxrt/imxrt6xx/flash_clock_setup.h diff --git a/soc/arm/nxp_imx/rt6xx/pinctrl_soc.h b/soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/rt6xx/pinctrl_soc.h rename to soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/rt6xx/power.c b/soc/nxp/imxrt/imxrt6xx/power.c similarity index 100% rename from soc/arm/nxp_imx/rt6xx/power.c rename to soc/nxp/imxrt/imxrt6xx/power.c diff --git a/soc/nxp/imxrt/imxrt6xx/soc.c b/soc/nxp/imxrt/imxrt6xx/soc.c new file mode 100644 index 00000000000..de658a285be --- /dev/null +++ b/soc/nxp/imxrt/imxrt6xx/soc.c @@ -0,0 +1,395 @@ +/* + * Copyright 2020-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for nxp_lpc55s69 platform + * + * This module provides routines to initialize and support board-level + * hardware for the nxp_lpc55s69 platform. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP +#include "flash_clock_setup.h" +#endif + +#if CONFIG_USB_DC_NXP_LPCIP3511 +#include "usb_phy.h" +#include "usb.h" +#endif + +/* Core clock frequency: 250105263Hz */ +#define CLOCK_INIT_CORE_CLOCK 250105263U + +#define SYSTEM_IS_XIP_FLEXSPI() \ + ((((uint32_t)nxp_rt600_init >= 0x08000000U) && \ + ((uint32_t)nxp_rt600_init < 0x10000000U)) || \ + (((uint32_t)nxp_rt600_init >= 0x18000000U) && \ + ((uint32_t)nxp_rt600_init < 0x20000000U))) + +#define CTIMER_CLOCK_SOURCE(node_id) \ + TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source)) +#define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val) +#define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val) +#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id)); + +#ifdef CONFIG_INIT_SYS_PLL +const clock_sys_pll_config_t g_sysPllConfig = { + .sys_pll_src = kCLOCK_SysPllXtalIn, + .numerator = 0, + .denominator = 1, + .sys_pll_mult = kCLOCK_SysPllMult22 +}; +#endif + +#ifdef CONFIG_INIT_AUDIO_PLL +const clock_audio_pll_config_t g_audioPllConfig = { + .audio_pll_src = kCLOCK_AudioPllXtalIn, + .numerator = 5040, + .denominator = 27000, + .audio_pll_mult = kCLOCK_AudioPllMult22 +}; +#endif + +#if CONFIG_USB_DC_NXP_LPCIP3511 +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) +#endif + +/* System clock frequency. */ +extern uint32_t SystemCoreClock; +/* Main stack pointer */ +extern char z_main_stack[]; + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +extern char _flash_used[]; +extern void z_arm_reset(void); +extern void z_arm_nmi(void); +extern void z_arm_hard_fault(void); +extern void z_arm_mpu_fault(void); +extern void z_arm_bus_fault(void); +extern void z_arm_usage_fault(void); +extern void z_arm_secure_fault(void); +extern void z_arm_svc(void); +extern void z_arm_debug_monitor(void); +extern void z_arm_pendsv(void); +extern void sys_clock_isr(void); +extern void z_arm_exc_spurious(void); + +__imx_boot_ivt_section void (* const image_vector_table[])(void) = { + (void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */ + z_arm_reset, /* 0x04 */ + z_arm_nmi, /* 0x08 */ + z_arm_hard_fault, /* 0x0C */ + z_arm_mpu_fault, /* 0x10 */ + z_arm_bus_fault, /* 0x14 */ + z_arm_usage_fault, /* 0x18 */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + z_arm_secure_fault, /* 0x1C */ +#else + z_arm_exc_spurious, +#endif /* CONFIG_ARM_SECURE_FIRMWARE */ + (void (*)())_flash_used, /* 0x20, imageLength. */ + 0, /* 0x24, imageType (Plain Image) */ + 0, /* 0x28, authBlockOffset/crcChecksum */ + z_arm_svc, /* 0x2C */ + z_arm_debug_monitor, /* 0x30 */ + (void (*)())image_vector_table, /* 0x34, imageLoadAddress. */ + z_arm_pendsv, /* 0x38 */ +#if defined(CONFIG_SYS_CLOCK_EXISTS) && \ + defined(CONFIG_CORTEX_M_SYSTICK_INSTALL_ISR) + sys_clock_isr, /* 0x3C */ +#else + z_arm_exc_spurious, +#endif +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ + +#if CONFIG_USB_DC_NXP_LPCIP3511 + +static void usb_device_clock_init(void) +{ + uint8_t usbClockDiv = 1; + uint32_t usbClockFreq; + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; + + /* enable USB IP clock */ + CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 5); + CLOCK_AttachClk(kXTALIN_CLK_to_USB_CLK); + CLOCK_SetClkDiv(kCLOCK_DivUsbHsFclk, usbClockDiv); + CLOCK_EnableUsbhsDeviceClock(); + RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_DEVICE_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_HOST_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_SRAM_RST_SHIFT_RSTn); + /*Make sure USBHS ram buffer has power up*/ + POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM); + POWER_ApplyPD(); + + /* save usb ip clock freq*/ + usbClockFreq = g_xtalFreq / usbClockDiv; + /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ + CLOCK_EnableUsbHs0PhyPllClock(kXTALIN_CLK_to_USB_CLK, usbClockFreq); + +#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM) + for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++) { + ((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U; + } +#endif + USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, CLK_XTAL_OSC_CLK, &phyConfig); + + /* the following code should run after phy initialization and + * should wait some microseconds to make sure utmi clock valid + */ + /* enable usb1 host clock */ + CLOCK_EnableClock(kCLOCK_UsbhsHost); + /* Wait until host_needclk de-asserts */ + while (SYSCTL0->USBCLKSTAT & SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_MASK) { + __ASM("nop"); + } + /* According to reference mannual, device mode setting has to be set by + * access usb host register + */ + USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; + /* disable usb1 host clock */ + CLOCK_DisableClock(kCLOCK_UsbhsHost); +} + +#endif + +/** + * @brief Initialize the system clock + */ +static ALWAYS_INLINE void clock_init(void) +{ +#ifdef CONFIG_SOC_MIMXRT685S_CM33 + /* Configure LPOSC clock*/ + POWER_DisablePD(kPDRUNCFG_PD_LPOSC); + /* Configure FFRO clock */ + POWER_DisablePD(kPDRUNCFG_PD_FFRO); + CLOCK_EnableFfroClk(kCLOCK_Ffro48M); + /* Configure SFRO clock */ + POWER_DisablePD(kPDRUNCFG_PD_SFRO); + CLOCK_EnableSfroClk(); + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP + /* + * Call function flexspi_clock_safe_config() to move FlexSPI clock to a stable + * clock source to avoid instruction/data fetch issue when updating PLL and Main + * clock if XIP(execute code on FLEXSPI memory). + */ + flexspi_clock_safe_config(); +#endif + + /* Let CPU run on FFRO for safe switching. */ + CLOCK_AttachClk(kFFRO_to_MAIN_CLK); + + /* Configure SYSOSC clock source */ + POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); + POWER_UpdateOscSettlingTime(CONFIG_SYSOSC_SETTLING_US); + CLOCK_EnableSysOscClk(true, true, CONFIG_SYSOSC_SETTLING_US); + CLOCK_SetXtalFreq(CONFIG_XTAL_SYS_CLK_HZ); + +#ifdef CONFIG_INIT_SYS_PLL + /* Configure SysPLL0 clock source */ + CLOCK_InitSysPll(&g_sysPllConfig); + CLOCK_InitSysPfd(kCLOCK_Pfd0, 19); + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); +#endif + +#ifdef CONFIG_INIT_AUDIO_PLL + /* Configure Audio PLL clock source */ + CLOCK_InitAudioPll(&g_audioPllConfig); + CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); + CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); +#endif + + /* Set SYSCPUAHBCLKDIV divider to value 2 */ + CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); + + /* Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); + + /* Set up dividers */ + /* Set PFC0DIV divider to value 2 */ + CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); + /* Set FRGPLLCLKDIV divider to value 12 */ + CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U); + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay) + CLOCK_AttachClk(kSFRO_to_FLEXCOMM0); +#endif + +#if CONFIG_USB_DC_NXP_LPCIP3511 + usb_device_clock_init(); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2c, okay) + CLOCK_AttachClk(kSFRO_to_FLEXCOMM2); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pmic_i2c), nxp_lpc_i2c, okay) + CLOCK_AttachClk(kFFRO_to_FLEXCOMM15); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_usart, okay) + CLOCK_AttachClk(kSFRO_to_FLEXCOMM4); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_spi, okay) + CLOCK_AttachClk(kFFRO_to_FLEXCOMM5); +#endif + +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay)) + /* attach AUDIO PLL clock to FLEXCOMM1 (I2S1) */ + CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM1); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay)) + /* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */ + CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3); +#endif + +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt0), nxp_lpc_wwdt, okay)) + CLOCK_AttachClk(kLPOSC_to_WDT0_CLK); +#else + /* Allowed to select none if not being used for watchdog to + * reduce power + */ + CLOCK_AttachClk(kNONE_to_WDT0_CLK); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC + /* Make sure USDHC ram buffer has been power up*/ + POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PD_LPOSC); + POWER_ApplyPD(); + + /* usdhc depend on 32K clock also */ + CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK); + CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK); + CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1); + CLOCK_EnableClock(kCLOCK_Sdio0); + RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn); +#endif + + DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP) + DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP) + +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(i3c0), nxp_mcux_i3c, okay)) + CLOCK_AttachClk(kFFRO_to_I3C_CLK); + CLOCK_AttachClk(kLPOSC_to_I3C_TC_CLK); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpadc0), nxp_lpc_lpadc, okay) + SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK; + SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK; + RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); + CLOCK_AttachClk(kSFRO_to_ADC_CLK); + CLOCK_SetClkDiv(kCLOCK_DivAdcClk, DT_PROP(DT_NODELABEL(lpadc0), clk_divider)); +#endif + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP + /* + * Call function flexspi_setup_clock() to set user configured clock source/divider + * for FlexSPI. + */ + flexspi_setup_clock(FLEXSPI, 1U, 9U); +#endif + +#if CONFIG_COUNTER_NXP_MRT + RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn); +#endif + + /* Set SystemCoreClock variable. */ + SystemCoreClock = CLOCK_INIT_CORE_CLOCK; + +#endif /* CONFIG_SOC_MIMXRT685S_CM33 */ +} + +#if (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC) + +void imxrt_usdhc_pinmux(uint16_t nusdhc, bool init, + uint32_t speed, uint32_t strength) +{ + +} + +void imxrt_usdhc_dat3_pull(bool pullup) +{ + +} +#endif + +/** + * + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * + * @return 0 + */ + +static int nxp_rt600_init(void) +{ + /* Initialize clock */ + clock_init(); + +#ifndef CONFIG_IMXRT6XX_CODE_CACHE + CACHE64_DisableCache(CACHE64); +#endif + + return 0; +} + +#ifdef CONFIG_PLATFORM_SPECIFIC_INIT + +void z_arm_platform_init(void) +{ +#ifndef CONFIG_NXP_IMXRT_BOOT_HEADER + /* + * If boot did not proceed using a boot header, we should not assume + * the core is in reset state. Disable the MPU and correctly + * set the stack pointer, since we are about to push to + * the stack when we call SystemInit + */ + /* Clear stack limit registers */ + __set_MSPLIM(0); + __set_PSPLIM(0); + /* Disable MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + /* Set stack pointer */ + __set_MSP((uint32_t)(z_main_stack + CONFIG_MAIN_STACK_SIZE)); +#endif /* !CONFIG_NXP_IMXRT_BOOT_HEADER */ + /* This is provided by the SDK */ + SystemInit(); +} + +#endif + +SYS_INIT(nxp_rt600_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_imx/rt6xx/soc.h b/soc/nxp/imxrt/imxrt6xx/soc.h similarity index 100% rename from soc/arm/nxp_imx/rt6xx/soc.h rename to soc/nxp/imxrt/imxrt6xx/soc.h diff --git a/soc/arm/nxp_imx/rt/mpu_regions.c b/soc/nxp/imxrt/mpu_regions.c similarity index 100% rename from soc/arm/nxp_imx/rt/mpu_regions.c rename to soc/nxp/imxrt/mpu_regions.c diff --git a/soc/nxp/imxrt/soc.yml b/soc/nxp/imxrt/soc.yml new file mode 100644 index 00000000000..319d5b947e2 --- /dev/null +++ b/soc/nxp/imxrt/soc.yml @@ -0,0 +1,34 @@ +family: +- name: nxp_imxrt + series: + - name: imxrt10xx + socs: + - name: mimxrt1011 + - name: mimxrt1015 + - name: mimxrt1021 + - name: mimxrt1024 + - name: mimxrt1042 + - name: mimxrt1051 + - name: mimxrt1052 + - name: mimxrt1061 + - name: mimxrt1062 + - name: mimxrt1064 + - name: imxrt11xx + socs: + - name: mimxrt1166 + cpuclusters: + - name: cm7 + - name: cm4 + - name: mimxrt1176 + cpuclusters: + - name: cm7 + - name: cm4 + - name: imxrt5xx + socs: + - name: mimxrt595s + cpuclusters: + - name: cm33 + - name: f1 + - name: imxrt6xx + socs: + - name: mimxrt685s diff --git a/soc/arm/nxp_imx/rt6xx/usb.ld b/soc/nxp/imxrt/usb.ld similarity index 91% rename from soc/arm/nxp_imx/rt6xx/usb.ld rename to soc/nxp/imxrt/usb.ld index 170e2cefd84..2e10b4b12dc 100644 --- a/soc/arm/nxp_imx/rt6xx/usb.ld +++ b/soc/nxp/imxrt/usb.ld @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 NXP + * Copyright 2021-2022, 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/soc/arm/nxp_kinetis/CMakeLists.txt b/soc/nxp/kinetis/CMakeLists.txt similarity index 100% rename from soc/arm/nxp_kinetis/CMakeLists.txt rename to soc/nxp/kinetis/CMakeLists.txt diff --git a/soc/nxp/kinetis/Kconfig b/soc/nxp/kinetis/Kconfig new file mode 100644 index 00000000000..4476e8f1697 --- /dev/null +++ b/soc/nxp/kinetis/Kconfig @@ -0,0 +1,156 @@ +# Copyright (c) 2016 Intel Corporation +# Copyright (c) 2016, Freescale Semiconductor, Inc. +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_KINETIS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +if SOC_FAMILY_KINETIS + +config HAS_OSC + bool + help + Set if the oscillator (OSC) module is present in the SoC. + +config HAS_MCG + bool + help + Set if the multipurpose clock generator (MCG) module is present in the SoC. + +if HAS_OSC + +choice + prompt "Oscillator Mode Selection" + default OSC_EXTERNAL + +config OSC_EXTERNAL + bool "External reference clock" + help + Set this option to use the oscillator in external reference clock mode. + +config OSC_LOW_POWER + bool "Low power oscillator" + help + Set this option to use the oscillator in low-power mode. + +config OSC_HIGH_GAIN + bool "High gain oscillator" + help + Set this option to use the oscillator in high-gain mode. + +endchoice + +config OSC_XTAL0_FREQ + int "External oscillator frequency" + help + Set the external oscillator frequency in Hz. This should be set by the + board's defconfig. + +endif # HAS_OSC + +if HAS_MCG + +config MCG_PRDIV0 + hex "PLL external reference divider" + range 0 0x18 + default 0 + help + Selects the amount to divide down the external reference clock for the PLL. + The resulting frequency must be in the range of 2 MHz to 4 MHz. + +config MCG_VDIV0 + hex "VCO 0 divider" + range 0 0x1F + default 0 + help + Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits + establish the multiplication factor (M) applied to the reference clock + frequency. + +config MCG_FCRDIV + int "Fast internal reference clock divider" + range 0 7 + default 1 + help + Selects the amount to divide down the fast internal reference clock. The + resulting frequency must be in the range 31.25 kHz to 4 MHz. + +config MCG_FRDIV + int "FLL external reference divider" + range 0 7 + default 0 + help + Selects the amount to divide down the external reference clock for the + FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 + kHz. + +endif # HAS_MCG + +config KINETIS_FLASH_CONFIG + bool "Kinetis flash configuration field" + default y if XIP && !BOOTLOADER_MCUBOOT + help + Include the 16-byte flash configuration field that stores default + protection settings (loaded on reset) and security information that + allows the MCU to restrict access to the FTFx module. + +if KINETIS_FLASH_CONFIG + +config KINETIS_FLASH_CONFIG_OFFSET + hex "Kinetis flash configuration field offset" + default 0x400 + +config KINETIS_FLASH_CONFIG_FSEC + hex "Flash security byte (FSEC)" + range 0 0xff + default 0xfe + help + Configures the reset value of the FSEC register, which includes + backdoor key access, mass erase, factory access, and flash security + options. + +config KINETIS_FLASH_CONFIG_FOPT + hex "Flash nonvolatile option byte (FOPT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FOPT register, which includes boot, + NMI, and EzPort options. + +config KINETIS_FLASH_CONFIG_FEPROT + hex "EEPROM protection byte (FEPROT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FEPROT register for FlexNVM + devices. For program flash only devices, this byte is reserved. + +config KINETIS_FLASH_CONFIG_FDPROT + hex "Data flash protection byte (FDPROT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FDPROT register for FlexNVM + devices. For program flash only devices, this byte is reserved. + +endif # KINETIS_FLASH_CONFIG + +config WDOG_ENABLE_AT_BOOT + bool "Keep watchdog timer enabled at boot" + help + Leave SOC watchdog timer enabled at boot. The specific timeout + and clock configuration of the watchdog at boot is SOC dependent. + Note: if the watchdog timer is enabled at boot, the user will + need to configure the watchdog using z_arm_watchdog_init, as + the SOC requires watchdog configuration before initial expiration + +# Enable watchdog configuration function if watchdog is left enabled at boot +config WDOG_INIT + bool + default WDOG_ENABLE_AT_BOOT + + +rsource "*/Kconfig" + +endif # SOC_FAMILY_KINETIS diff --git a/soc/nxp/kinetis/Kconfig.defconfig b/soc/nxp/kinetis/Kconfig.defconfig new file mode 100644 index 00000000000..33f477c0230 --- /dev/null +++ b/soc/nxp/kinetis/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_KINETIS + +config SERIAL_INIT_PRIORITY + default 55 + depends on SERIAL + +config ADC_INIT_PRIORITY + default 80 if ADC_MCUX_ADC16_ENABLE_EDMA + depends on ADC + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_KINETIS diff --git a/soc/nxp/kinetis/Kconfig.soc b/soc/nxp/kinetis/Kconfig.soc new file mode 100644 index 00000000000..b5fcf5db79a --- /dev/null +++ b/soc/nxp/kinetis/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_KINETIS + bool + +config SOC_FAMILY + default "nxp_kinetis" if SOC_FAMILY_KINETIS + +rsource "*/Kconfig.soc" diff --git a/soc/arm/nxp_kinetis/common/pinctrl_soc.h b/soc/nxp/kinetis/common/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_kinetis/common/pinctrl_soc.h rename to soc/nxp/kinetis/common/pinctrl_soc.h diff --git a/soc/arm/nxp_kinetis/flash_config.ld b/soc/nxp/kinetis/flash_config.ld similarity index 100% rename from soc/arm/nxp_kinetis/flash_config.ld rename to soc/nxp/kinetis/flash_config.ld diff --git a/soc/arm/nxp_kinetis/flash_configuration.c b/soc/nxp/kinetis/flash_configuration.c similarity index 100% rename from soc/arm/nxp_kinetis/flash_configuration.c rename to soc/nxp/kinetis/flash_configuration.c diff --git a/soc/nxp/kinetis/k2x/CMakeLists.txt b/soc/nxp/kinetis/k2x/CMakeLists.txt new file mode 100644 index 00000000000..915f002e0ed --- /dev/null +++ b/soc/nxp/kinetis/k2x/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# Copyright (c) 2018 Prevas A/S +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c + ) + +if(DEFINED CONFIG_ARM_MPU AND DEFINED CONFIG_CPU_HAS_NXP_MPU) + # MK22F12 series MCUs have NXP MPU + zephyr_sources(nxp_mpu_regions.c) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/kinetis/k2x/Kconfig b/soc/nxp/kinetis/k2x/Kconfig new file mode 100644 index 00000000000..29317c2239c --- /dev/null +++ b/soc/nxp/kinetis/k2x/Kconfig @@ -0,0 +1,47 @@ +# Kinetis K2X MCU line + +# Copyright (c) 2018 Prevas A/S +# Copyright (c) 2019 Thomas Burdick +# Copyright 2024 NXP + +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_KINETIS_K2X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CLOCK_CONTROL + select PLATFORM_SPECIFIC_INIT + +config SOC_MK22F51212 + select HAS_MCUX + select HAS_MCUX_SMC + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select CPU_HAS_FPU + select HAS_MCUX_DAC + select HAS_MCUX_RCM + +# Note- the MK22F12 SKU is a legacy SOC, no longer officially supported by +# NXP's MCUX SDK, and not recommended for new designs. +config SOC_MK22F12 + select HAS_MCUX + select HAS_MCUX_SMC + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select CPU_HAS_FPU + select HAS_MCUX_DAC + select HAS_MCUX_RCM + select CPU_HAS_NXP_MPU diff --git a/soc/nxp/kinetis/k2x/Kconfig.defconfig b/soc/nxp/kinetis/k2x/Kconfig.defconfig new file mode 100644 index 00000000000..8095c7a1842 --- /dev/null +++ b/soc/nxp/kinetis/k2x/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Kinetis K2x series configuration options + +# Copyright (c) 2018 Prevas A/S +# Copyright (c) 2019 Thomas Burdick +# Copyright 2024 NXP + +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_KINETIS_K2X + +config GPIO + default y if SOC_MK22F51212 + +config NUM_IRQS + default 74 + +config NUM_IRQS + default 81 if SOC_MK22F12 + default 74 if SOC_MK22F51212 + +config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + default y if SOC_MK22F12 + +endif # SOC_SERIES_KINETIS_K2X diff --git a/soc/nxp/kinetis/k2x/Kconfig.soc b/soc/nxp/kinetis/k2x/Kconfig.soc new file mode 100644 index 00000000000..60979d8a9d8 --- /dev/null +++ b/soc/nxp/kinetis/k2x/Kconfig.soc @@ -0,0 +1,40 @@ +# Kinetis K2X MCU line + +# Copyright (c) 2018 Prevas A/S +# Copyright (c) 2019 Thomas Burdick +# Copyright 2024 NXP + +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_KINETIS_K2X + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "k2x" if SOC_SERIES_KINETIS_K2X + +config SOC_MK22F51212 + bool + select SOC_SERIES_KINETIS_K2X + +# Note- the MK22F12 SKU is a legacy SOC, no longer officially supported by +# NXP's MCUX SDK, and not recommended for new designs. +config SOC_MK22F12 + bool + select SOC_SERIES_KINETIS_K2X + +config SOC + default "mk22f51212" if SOC_MK22F51212 + default "mk22f12" if SOC_MK22F12 + +config SOC_PART_NUMBER_MK22FN512VLH12 + bool + +config SOC_PART_NUMBER_MK22FX512VLQ12 + bool + +config SOC_PART_NUMBER + default "MK22FN512VLH12" if SOC_PART_NUMBER_MK22FN512VLH12 + default "MK22FX512VLQ12" if SOC_PART_NUMBER_MK22FX512VLQ12 diff --git a/soc/arm/nxp_kinetis/k2x/nxp_mpu_regions.c b/soc/nxp/kinetis/k2x/nxp_mpu_regions.c similarity index 100% rename from soc/arm/nxp_kinetis/k2x/nxp_mpu_regions.c rename to soc/nxp/kinetis/k2x/nxp_mpu_regions.c diff --git a/soc/arm/nxp_kinetis/k2x/soc.c b/soc/nxp/kinetis/k2x/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/k2x/soc.c rename to soc/nxp/kinetis/k2x/soc.c diff --git a/soc/arm/nxp_kinetis/k2x/soc.h b/soc/nxp/kinetis/k2x/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/k2x/soc.h rename to soc/nxp/kinetis/k2x/soc.h diff --git a/soc/nxp/kinetis/k6x/CMakeLists.txt b/soc/nxp/kinetis/k6x/CMakeLists.txt new file mode 100644 index 00000000000..ef8279861fd --- /dev/null +++ b/soc/nxp/kinetis/k6x/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) +zephyr_sources_ifdef( + CONFIG_ARM_MPU + nxp_mpu_regions.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/kinetis/k6x/Kconfig b/soc/nxp/kinetis/k6x/Kconfig new file mode 100644 index 00000000000..4f7bd55078d --- /dev/null +++ b/soc/nxp/kinetis/k6x/Kconfig @@ -0,0 +1,59 @@ +# Kinetis K6x series configuration + +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_K6X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_NXP_MPU + select HAS_MCUX_PIT + select CLOCK_CONTROL + select PLATFORM_SPECIFIC_INIT + +config SOC_MK64F12 + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_ENET + select HAS_MCUX_FLEXCAN + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select CPU_HAS_FPU + select HAS_MCUX_RTC + select HAS_MCUX_DAC + select HAS_MCUX_EDMA + select HAS_MCUX_RCM + +config SOC_MK66F18 + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_ENET + select HAS_MCUX_FLEXCAN + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select CPU_HAS_FPU + select HAS_MCUX_RTC + select HAS_MCUX_DAC + select HAS_MCUX_EDMA + select HAS_MCUX_RCM + select HAS_MCUX_LPUART + + +if SOC_MK66F18 + +config K6X_HSRUN + bool "High Speed RUN mode" + default y + help + This options enables support for High Speed RUN mode on K66F SoC. + +endif # SOC_MK66F18 diff --git a/soc/nxp/kinetis/k6x/Kconfig.defconfig b/soc/nxp/kinetis/k6x/Kconfig.defconfig new file mode 100644 index 00000000000..94136541855 --- /dev/null +++ b/soc/nxp/kinetis/k6x/Kconfig.defconfig @@ -0,0 +1,22 @@ +# Kinetis K6x series default configurations + +# Copyright (c) 2014-2016 Wind River Systems, Inc. +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_K6X + +config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + default y + +config NUM_IRQS + default 100 if SOC_MK66F18 + default 86 if SOC_MK64F12 + +config GPIO + default y + +config SPI + default n if SOC_MK64F12 + +endif # SOC_SERIES_KINETIS_K6X diff --git a/soc/nxp/kinetis/k6x/Kconfig.soc b/soc/nxp/kinetis/k6x/Kconfig.soc new file mode 100644 index 00000000000..2e8d8f7b924 --- /dev/null +++ b/soc/nxp/kinetis/k6x/Kconfig.soc @@ -0,0 +1,70 @@ +# Kinetis K6X MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_K6X + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "k6x" if SOC_SERIES_KINETIS_K6X + +config SOC_MK64F12 + bool + select SOC_SERIES_KINETIS_K6X + +config SOC_MK66F18 + bool + select SOC_SERIES_KINETIS_K6X + +config SOC + default "mk64f12" if SOC_MK64F12 + default "mk66f18" if SOC_MK66F18 + +config SOC_PART_NUMBER_MK64FN1M0CAJ12 + bool + +config SOC_PART_NUMBER_MK64FN1M0VDC12 + bool + +config SOC_PART_NUMBER_MK64FN1M0VLL12 + bool + +config SOC_PART_NUMBER_MK64FN1M0VLQ12 + bool + +config SOC_PART_NUMBER_MK64FN1M0VMD12 + bool + +config SOC_PART_NUMBER_MK64FX512VDC12 + bool + +config SOC_PART_NUMBER_MK64FX512VLL12 + bool + +config SOC_PART_NUMBER_MK64FX512VLQ12 + bool + +config SOC_PART_NUMBER_MK64FX512VMD12 + bool + +config SOC_PART_NUMBER_MK66FN2M0VMD18 + bool + +config SOC_PART_NUMBER_MK66FN2M0VLQ18 + bool + +config SOC_PART_NUMBER + default "MK64FN1M0CAJ12" if SOC_PART_NUMBER_MK64FN1M0CAJ12 + default "MK64FN1M0VDC12" if SOC_PART_NUMBER_MK64FN1M0VDC12 + default "MK64FN1M0VLL12" if SOC_PART_NUMBER_MK64FN1M0VLL12 + default "MK64FN1M0VLQ12" if SOC_PART_NUMBER_MK64FN1M0VLQ12 + default "MK64FN1M0VMD12" if SOC_PART_NUMBER_MK64FN1M0VMD12 + default "MK64FX512VDC12" if SOC_PART_NUMBER_MK64FX512VDC12 + default "MK64FX512VLL12" if SOC_PART_NUMBER_MK64FX512VLL12 + default "MK64FX512VLQ12" if SOC_PART_NUMBER_MK64FX512VLQ12 + default "MK64FX512VMD12" if SOC_PART_NUMBER_MK64FX512VMD12 + default "MK66FN2M0VMD18" if SOC_PART_NUMBER_MK66FN2M0VMD18 + default "MK66FN2M0VLQ18" if SOC_PART_NUMBER_MK66FN2M0VLQ18 diff --git a/soc/arm/nxp_kinetis/k6x/README.txt b/soc/nxp/kinetis/k6x/README.txt similarity index 100% rename from soc/arm/nxp_kinetis/k6x/README.txt rename to soc/nxp/kinetis/k6x/README.txt diff --git a/soc/arm/nxp_kinetis/k6x/nxp_mpu_regions.c b/soc/nxp/kinetis/k6x/nxp_mpu_regions.c similarity index 100% rename from soc/arm/nxp_kinetis/k6x/nxp_mpu_regions.c rename to soc/nxp/kinetis/k6x/nxp_mpu_regions.c diff --git a/soc/arm/nxp_kinetis/k6x/soc.c b/soc/nxp/kinetis/k6x/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/k6x/soc.c rename to soc/nxp/kinetis/k6x/soc.c diff --git a/soc/arm/nxp_kinetis/k6x/soc.h b/soc/nxp/kinetis/k6x/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/k6x/soc.h rename to soc/nxp/kinetis/k6x/soc.h diff --git a/soc/nxp/kinetis/k8x/CMakeLists.txt b/soc/nxp/kinetis/k8x/CMakeLists.txt new file mode 100644 index 00000000000..ef8279861fd --- /dev/null +++ b/soc/nxp/kinetis/k8x/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) +zephyr_sources_ifdef( + CONFIG_ARM_MPU + nxp_mpu_regions.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/kinetis/k8x/Kconfig b/soc/nxp/kinetis/k8x/Kconfig new file mode 100644 index 00000000000..ad8c4c85589 --- /dev/null +++ b/soc/nxp/kinetis/k8x/Kconfig @@ -0,0 +1,61 @@ +# Kinetis K8x series MCU + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_K8X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_NXP_MPU + select CPU_HAS_FPU + select CLOCK_CONTROL + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_LPUART + select HAS_MCUX_PIT + select HAS_MCUX_RTC + select HAS_MCUX_SIM + select HAS_MCUX_TRNG + select HAS_OSC + select HAS_MCG + select HAS_MCUX_EDMA + select HAS_MCUX_PIT + select HAS_MCUX_RCM + select HAS_MCUX_CACHE + select PLATFORM_SPECIFIC_INIT + +if SOC_SERIES_KINETIS_K8X + +config K8X_CORE_CLOCK_DIVIDER + int "Freescale K8x core clock divider" + default 1 + help + This option specifies the divide value for the K8x processor core clock + from the system clock. + +config K8X_BUS_CLOCK_DIVIDER + int "Freescale K8x bus clock divider" + default 2 + help + This option specifies the divide value for the K8x bus clock from the + system clock. + +config K8X_FLEXBUS_CLOCK_DIVIDER + int "Freescale K8x FlexBus clock divider" + default 2 + help + This option specifies the divide value for the K8x FlexBus clock from the + system clock. + +config K8X_FLASH_CLOCK_DIVIDER + int "Freescale K8x flash clock divider" + default 5 + help + This option specifies the divide value for the K8x flash clock from the + system clock. + +endif # SOC_SERIES_KINETIS_K8X diff --git a/soc/nxp/kinetis/k8x/Kconfig.defconfig b/soc/nxp/kinetis/k8x/Kconfig.defconfig new file mode 100644 index 00000000000..777c123c5ac --- /dev/null +++ b/soc/nxp/kinetis/k8x/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Kinetis K8x series configuration options + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_K8X + +config NUM_IRQS + # must be >= the highest interrupt number used + default 106 + +config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + default y + +config KINETIS_FLASH_CONFIG_FOPT + default 0x3f + depends on KINETIS_FLASH_CONFIG + +config GPIO + default y + +endif # SOC_SERIES_KINETIS_K8X diff --git a/soc/nxp/kinetis/k8x/Kconfig.soc b/soc/nxp/kinetis/k8x/Kconfig.soc new file mode 100644 index 00000000000..53bf2d656e3 --- /dev/null +++ b/soc/nxp/kinetis/k8x/Kconfig.soc @@ -0,0 +1,42 @@ +# Kinetis K8x series MCU + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_K8X + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "k8x" if SOC_SERIES_KINETIS_K8X + +config SOC_MK80F25615 + bool + select SOC_SERIES_KINETIS_K8X + +config SOC_MK82F25615 + bool + select SOC_SERIES_KINETIS_K8X + +config SOC + default "mk80f25615" if SOC_MK80F25615 + default "mk82f25615" if SOC_MK82F25615 + +config SOC_PART_NUMBER_MK80FN256VDC15 + bool + +config SOC_PART_NUMBER_MK80FN256VLL15 + bool + +config SOC_PART_NUMBER_MK82FN256VDC15 + bool + +config SOC_PART_NUMBER_MK82FN256VLL15 + bool + +config SOC_PART_NUMBER + default "MK80FN256VDC15" if SOC_PART_NUMBER_MK80FN256VDC15 + default "MK80FN256VLL15" if SOC_PART_NUMBER_MK80FN256VLL15 + default "MK82FN256VDC15" if SOC_PART_NUMBER_MK82FN256VDC15 + default "MK82FN256VLL15" if SOC_PART_NUMBER_MK82FN256VLL15 diff --git a/soc/arm/nxp_kinetis/k8x/nxp_mpu_regions.c b/soc/nxp/kinetis/k8x/nxp_mpu_regions.c similarity index 100% rename from soc/arm/nxp_kinetis/k8x/nxp_mpu_regions.c rename to soc/nxp/kinetis/k8x/nxp_mpu_regions.c diff --git a/soc/arm/nxp_kinetis/k8x/soc.c b/soc/nxp/kinetis/k8x/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/k8x/soc.c rename to soc/nxp/kinetis/k8x/soc.c diff --git a/soc/arm/nxp_kinetis/k8x/soc.h b/soc/nxp/kinetis/k8x/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/k8x/soc.h rename to soc/nxp/kinetis/k8x/soc.h diff --git a/soc/nxp/kinetis/ke1xf/CMakeLists.txt b/soc/nxp/kinetis/ke1xf/CMakeLists.txt new file mode 100644 index 00000000000..9a2e98801ac --- /dev/null +++ b/soc/nxp/kinetis/ke1xf/CMakeLists.txt @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) +zephyr_sources_ifdef( + CONFIG_ARM_MPU + nxp_mpu_regions.c + ) +zephyr_sources_ifdef( + CONFIG_PM + power.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") + +zephyr_include_directories(.) diff --git a/soc/nxp/kinetis/ke1xf/Kconfig b/soc/nxp/kinetis/ke1xf/Kconfig new file mode 100644 index 00000000000..df752ab9da3 --- /dev/null +++ b/soc/nxp/kinetis/ke1xf/Kconfig @@ -0,0 +1,68 @@ +# Kinetis KE1xF series MCU + +# Copyright (c) 2019 Vestas Wind Systems A/S +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KE1XF + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_NXP_MPU + select CPU_HAS_FPU + select CLOCK_CONTROL + select HAS_MCUX + select HAS_MCUX_CACHE + select HAS_MCUX_FTFX + select HAS_MCUX_LPI2C + select HAS_MCUX_LPSPI + select HAS_MCUX_LPUART + select HAS_MCUX_PCC + select HAS_MCUX_RTC + select HAS_MCUX_SIM + select HAS_MCUX_ADC12 + select HAS_MCUX_SCG + select HAS_MCUX_WDOG32 + select HAS_MCUX_FTM + select HAS_MCUX_LPTMR + select HAS_MCUX_DAC32 + select HAS_MCUX_EDMA + select HAS_MCUX_ACMP + select HAS_MCUX_PWT + select HAS_MCUX_RCM + select PLATFORM_SPECIFIC_INIT + select HAS_PM + +config SOC_MKE16F16 + select HAS_MCUX + select HAS_MCUX_FLEXCAN + +config SOC_MKE18F16 + select HAS_MCUX + select HAS_MCUX_FLEXCAN + +if SOC_SERIES_KINETIS_KE1XF + +config WDOG_ENABLE_AT_BOOT + bool "Keep watchdog timer enabled at boot" + help + Keep the watchdog timer enabled at boot with the internal + 128kHz LPO clock (and a prescaler of 256) as clock + source. The application can take over control of the + watchdog timer after boot and install a different timeout, + if needed. + +config WDOG_INITIAL_TIMEOUT + int "Initial timeout for the watchdog timer in milliseconds" + depends on WDOG_ENABLE_AT_BOOT && WDOG_INIT + range 2 131070 + default 2048 + help + Initial timeout value for the watchdog timer in + milliseconds. + +config KINETIS_KE1XF_ENABLE_CODE_CACHE + bool "Code cache" + default y + +endif # SOC_SERIES_KINETIS_KE1XF diff --git a/soc/nxp/kinetis/ke1xf/Kconfig.defconfig b/soc/nxp/kinetis/ke1xf/Kconfig.defconfig new file mode 100644 index 00000000000..bf6d1e532ea --- /dev/null +++ b/soc/nxp/kinetis/ke1xf/Kconfig.defconfig @@ -0,0 +1,37 @@ +# Kinetis KE1xF series configuration options + +# Copyright (c) 2019-2021 Vestas Wind Systems A/S +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_KE1XF + +config MCUX_LPTMR_TIMER + default y if PM + +config CORTEX_M_SYSTICK + default n if MCUX_LPTMR_TIMER + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK + default $(dt_node_int_prop_int,/soc/lptmr@40040000,clock-frequency) if MCUX_LPTMR_TIMER + +config NUM_IRQS + # must be >= the highest interrupt number used + default 91 + +config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + default y + +config KINETIS_FLASH_CONFIG_FOPT + default 0x7d + depends on KINETIS_FLASH_CONFIG + +config PWM_MCUX_PWT + default y + depends on PWM_CAPTURE + +config GPIO + default y + +endif # SOC_SERIES_KINETIS_KE1XF diff --git a/soc/nxp/kinetis/ke1xf/Kconfig.soc b/soc/nxp/kinetis/ke1xf/Kconfig.soc new file mode 100644 index 00000000000..97988220428 --- /dev/null +++ b/soc/nxp/kinetis/ke1xf/Kconfig.soc @@ -0,0 +1,79 @@ +# Kinetis KE1xF MCU line + +# Copyright (c) 2019 Vestas Wind Systems A/S +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KE1XF + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "ke1xf" if SOC_SERIES_KINETIS_KE1XF + +config SOC_MKE14F16 + bool + select SOC_SERIES_KINETIS_KE1XF + +config SOC_MKE16F16 + bool + select SOC_SERIES_KINETIS_KE1XF + +config SOC_MKE18F16 + bool + select SOC_SERIES_KINETIS_KE1XF + +config SOC + default "mke14f16" if SOC_MKE14F16 + default "mke16f16" if SOC_MKE16F16 + default "mke18f16" if SOC_MKE18F16 + +config SOC_PART_NUMBER_MKE14F256VLH16 + bool + +config SOC_PART_NUMBER_MKE14F256VLL16 + bool + +config SOC_PART_NUMBER_MKE14F512VLH16 + bool + +config SOC_PART_NUMBER_MKE14F512VLL16 + bool + +config SOC_PART_NUMBER_MKE16F256VLH16 + bool + +config SOC_PART_NUMBER_MKE16F256VLL16 + bool + +config SOC_PART_NUMBER_MKE16F512VLH16 + bool + +config SOC_PART_NUMBER_MKE16F512VLL16 + bool + +config SOC_PART_NUMBER_MKE18F256VLH16 + bool + +config SOC_PART_NUMBER_MKE18F256VLL16 + bool + +config SOC_PART_NUMBER_MKE18F512VLH16 + bool + +config SOC_PART_NUMBER_MKE18F512VLL16 + bool + +config SOC_PART_NUMBER + default "MKE14F256VLH16" if SOC_PART_NUMBER_MKE14F256VLH16 + default "MKE14F256VLL16" if SOC_PART_NUMBER_MKE14F256VLL16 + default "MKE14F512VLH16" if SOC_PART_NUMBER_MKE14F512VLH16 + default "MKE14F512VLL16" if SOC_PART_NUMBER_MKE14F512VLL16 + default "MKE16F256VLH16" if SOC_PART_NUMBER_MKE16F256VLH16 + default "MKE16F256VLL16" if SOC_PART_NUMBER_MKE16F256VLL16 + default "MKE16F512VLH16" if SOC_PART_NUMBER_MKE16F512VLH16 + default "MKE16F512VLL16" if SOC_PART_NUMBER_MKE16F512VLL16 + default "MKE18F256VLH16" if SOC_PART_NUMBER_MKE18F256VLH16 + default "MKE18F256VLL16" if SOC_PART_NUMBER_MKE18F256VLL16 + default "MKE18F512VLH16" if SOC_PART_NUMBER_MKE18F512VLH16 + default "MKE18F512VLL16" if SOC_PART_NUMBER_MKE18F512VLL16 diff --git a/soc/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c b/soc/nxp/kinetis/ke1xf/nxp_mpu_regions.c similarity index 100% rename from soc/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c rename to soc/nxp/kinetis/ke1xf/nxp_mpu_regions.c diff --git a/soc/arm/nxp_kinetis/ke1xf/power.c b/soc/nxp/kinetis/ke1xf/power.c similarity index 100% rename from soc/arm/nxp_kinetis/ke1xf/power.c rename to soc/nxp/kinetis/ke1xf/power.c diff --git a/soc/arm/nxp_kinetis/ke1xf/soc.c b/soc/nxp/kinetis/ke1xf/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/ke1xf/soc.c rename to soc/nxp/kinetis/ke1xf/soc.c diff --git a/soc/arm/nxp_kinetis/ke1xf/soc.h b/soc/nxp/kinetis/ke1xf/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/ke1xf/soc.h rename to soc/nxp/kinetis/ke1xf/soc.h diff --git a/soc/nxp/kinetis/kl2x/CMakeLists.txt b/soc/nxp/kinetis/kl2x/CMakeLists.txt new file mode 100644 index 00000000000..15835842aa8 --- /dev/null +++ b/soc/nxp/kinetis/kl2x/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") + +zephyr_include_directories(.) diff --git a/soc/nxp/kinetis/kl2x/Kconfig b/soc/nxp/kinetis/kl2x/Kconfig new file mode 100644 index 00000000000..6e88ad79fc2 --- /dev/null +++ b/soc/nxp/kinetis/kl2x/Kconfig @@ -0,0 +1,23 @@ +# Kinetis KL2x MCU series + +# Copyright (c) 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KL2X + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CLOCK_CONTROL + select PLATFORM_SPECIFIC_INIT + +config SOC_MKL25Z4 + select CPU_CORTEX_M0PLUS + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_LPSCI + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM diff --git a/soc/nxp/kinetis/kl2x/Kconfig.defconfig b/soc/nxp/kinetis/kl2x/Kconfig.defconfig new file mode 100644 index 00000000000..d51313e9598 --- /dev/null +++ b/soc/nxp/kinetis/kl2x/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Kinetis KL2x series configuration options + +# Copyright 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_KL2X + +config NUM_IRQS + default 32 if SOC_MKL25Z4 + +endif # SOC_SERIES_KINETIS_KL2X diff --git a/soc/nxp/kinetis/kl2x/Kconfig.soc b/soc/nxp/kinetis/kl2x/Kconfig.soc new file mode 100644 index 00000000000..f1525737db6 --- /dev/null +++ b/soc/nxp/kinetis/kl2x/Kconfig.soc @@ -0,0 +1,68 @@ +# Kinetis KL2x MCU series + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KL2X + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "kl2x" if SOC_SERIES_KINETIS_KL2X + +config SOC_MKL25Z4 + bool + select SOC_SERIES_KINETIS_KL2X + +config SOC + default "mkl25z4" if SOC_MKL25Z4 + +config SOC_PART_NUMBER_MKL25Z32VFM4 + bool + +config SOC_PART_NUMBER_MKL25Z64VFM4 + bool + +config SOC_PART_NUMBER_MKL25Z128VFM4 + bool + +config SOC_PART_NUMBER_MKL25Z32VFT4 + bool + +config SOC_PART_NUMBER_MKL25Z64VFT4 + bool + +config SOC_PART_NUMBER_MKL25Z128VFT4 + bool + +config SOC_PART_NUMBER_MKL25Z32VLH4 + bool + +config SOC_PART_NUMBER_MKL25Z64VLH4 + bool + +config SOC_PART_NUMBER_MKL25Z128VLH4 + bool + +config SOC_PART_NUMBER_MKL25Z32VLK4 + bool + +config SOC_PART_NUMBER_MKL25Z64VLK4 + bool + +config SOC_PART_NUMBER_MKL25Z128VLK4 + bool + +config SOC_PART_NUMBER + default "MKL25Z32VFM4" if SOC_PART_NUMBER_MKL25Z32VFM4 + default "MKL25Z64VFM4" if SOC_PART_NUMBER_MKL25Z64VFM4 + default "MKL25Z128VFM4" if SOC_PART_NUMBER_MKL25Z128VFM4 + default "MKL25Z32VFT4" if SOC_PART_NUMBER_MKL25Z32VFT4 + default "MKL25Z64VFT4" if SOC_PART_NUMBER_MKL25Z64VFT4 + default "MKL25Z128VFT4" if SOC_PART_NUMBER_MKL25Z128VFT4 + default "MKL25Z32VLH4" if SOC_PART_NUMBER_MKL25Z32VLH4 + default "MKL25Z64VLH4" if SOC_PART_NUMBER_MKL25Z64VLH4 + default "MKL25Z128VLH4" if SOC_PART_NUMBER_MKL25Z128VLH4 + default "MKL25Z32VLK4" if SOC_PART_NUMBER_MKL25Z32VLK4 + default "MKL25Z64VLK4" if SOC_PART_NUMBER_MKL25Z64VLK4 + default "MKL25Z128VLK4" if SOC_PART_NUMBER_MKL25Z128VLK4 diff --git a/soc/arm/nxp_kinetis/kl2x/soc.c b/soc/nxp/kinetis/kl2x/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/kl2x/soc.c rename to soc/nxp/kinetis/kl2x/soc.c diff --git a/soc/arm/nxp_kinetis/kl2x/soc.h b/soc/nxp/kinetis/kl2x/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/kl2x/soc.h rename to soc/nxp/kinetis/kl2x/soc.h diff --git a/soc/nxp/kinetis/kv5x/CMakeLists.txt b/soc/nxp/kinetis/kv5x/CMakeLists.txt new file mode 100644 index 00000000000..11a75f9d221 --- /dev/null +++ b/soc/nxp/kinetis/kv5x/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") + +zephyr_include_directories(.) diff --git a/soc/nxp/kinetis/kv5x/Kconfig b/soc/nxp/kinetis/kv5x/Kconfig new file mode 100644 index 00000000000..93a48b3caba --- /dev/null +++ b/soc/nxp/kinetis/kv5x/Kconfig @@ -0,0 +1,24 @@ +# Kinetis KV5x series MCU + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KV5X + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select CLOCK_CONTROL + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM + select PLATFORM_SPECIFIC_INIT diff --git a/soc/nxp/kinetis/kv5x/Kconfig.defconfig b/soc/nxp/kinetis/kv5x/Kconfig.defconfig new file mode 100644 index 00000000000..206a2c4de0c --- /dev/null +++ b/soc/nxp/kinetis/kv5x/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Kinetis KV5x series configuration options + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_KV5X + +config NUM_IRQS + # must be >= the highest interrupt number used + default 121 + +config GPIO + default y + +endif # SOC_SERIES_KINETIS_KV5X diff --git a/soc/nxp/kinetis/kv5x/Kconfig.soc b/soc/nxp/kinetis/kv5x/Kconfig.soc new file mode 100644 index 00000000000..ce717b2f371 --- /dev/null +++ b/soc/nxp/kinetis/kv5x/Kconfig.soc @@ -0,0 +1,58 @@ +# Kinetis KV5x series MCU + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KV5X + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "kv5x" if SOC_SERIES_KINETIS_KV5X + +config SOC_MKV56F24 + bool + select SOC_SERIES_KINETIS_KV5X + +config SOC_MKV58F24 + bool + select SOC_SERIES_KINETIS_KV5X + +config SOC + default "mkv56f24" if SOC_MKV56F24 + default "mkv58f24" if SOC_MKV58F24 + +config SOC_PART_NUMBER_MKV56F512VLL24 + bool + +config SOC_PART_NUMBER_MKV56F512VLQ24 + bool + +config SOC_PART_NUMBER_MKV56F1M0VLL24 + bool + +config SOC_PART_NUMBER_MKV56F1M0VLQ24 + bool + +config SOC_PART_NUMBER_MKV58F512VLL24 + bool + +config SOC_PART_NUMBER_MKV58F512VLQ24 + bool + +config SOC_PART_NUMBER_MKV58F1M0VLL24 + bool + +config SOC_PART_NUMBER_MKV58F1M0VLQ24 + bool + +config SOC_PART_NUMBER + default "MKV56F512VLL24" if SOC_PART_NUMBER_MKV56F512VLL24 + default "MKV56F512VLQ24" if SOC_PART_NUMBER_MKV56F512VLQ24 + default "MKV56F1M0VLL24" if SOC_PART_NUMBER_MKV56F1M0VLL24 + default "MKV56F1M0VLQ24" if SOC_PART_NUMBER_MKV56F1M0VLQ24 + default "MKV58F512VLL24" if SOC_PART_NUMBER_MKV58F512VLL24 + default "MKV58F512VLQ24" if SOC_PART_NUMBER_MKV58F512VLQ24 + default "MKV58F1M0VLL24" if SOC_PART_NUMBER_MKV58F1M0VLL24 + default "MKV58F1M0VLQ24" if SOC_PART_NUMBER_MKV58F1M0VLQ24 diff --git a/soc/arm/nxp_kinetis/kv5x/soc.c b/soc/nxp/kinetis/kv5x/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/kv5x/soc.c rename to soc/nxp/kinetis/kv5x/soc.c diff --git a/soc/arm/nxp_kinetis/kv5x/soc.h b/soc/nxp/kinetis/kv5x/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/kv5x/soc.h rename to soc/nxp/kinetis/kv5x/soc.h diff --git a/soc/arm/nxp_kinetis/kv5x/wdog.S b/soc/nxp/kinetis/kv5x/wdog.S similarity index 100% rename from soc/arm/nxp_kinetis/kv5x/wdog.S rename to soc/nxp/kinetis/kv5x/wdog.S diff --git a/soc/nxp/kinetis/kwx/CMakeLists.txt b/soc/nxp/kinetis/kwx/CMakeLists.txt new file mode 100644 index 00000000000..5355c9c96fe --- /dev/null +++ b/soc/nxp/kinetis/kwx/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_SOC_MKW24D5 soc_kw2xd.c) +zephyr_sources_ifdef(CONFIG_SOC_MKW22D5 soc_kw2xd.c) +zephyr_sources_ifdef(CONFIG_SOC_MKW41Z4 soc_kw4xz.c) +zephyr_sources_ifdef(CONFIG_SOC_MKW40Z4 soc_kw4xz.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/kinetis/kwx/Kconfig b/soc/nxp/kinetis/kwx/Kconfig new file mode 100644 index 00000000000..d3e209e3f96 --- /dev/null +++ b/soc/nxp/kinetis/kwx/Kconfig @@ -0,0 +1,62 @@ +# Kinetis KWx MCU series + +# Copyright (c) 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KWX + select ARM + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CLOCK_CONTROL + select PLATFORM_SPECIFIC_INIT + +config SOC_MKW22D5 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM + +config SOC_MKW24D5 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM + +config SOC_MKW40Z4 + select CPU_CORTEX_M0PLUS + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_LPUART + select HAS_MCUX_SIM + select HAS_MCUX_TRNG + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM + +config SOC_MKW41Z4 + select CPU_CORTEX_M0PLUS + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_LPUART + select HAS_MCUX_RTC + select HAS_MCUX_SIM + select HAS_MCUX_TPM + select HAS_MCUX_TRNG + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM diff --git a/soc/nxp/kinetis/kwx/Kconfig.defconfig b/soc/nxp/kinetis/kwx/Kconfig.defconfig new file mode 100644 index 00000000000..d2fb4f0de0d --- /dev/null +++ b/soc/nxp/kinetis/kwx/Kconfig.defconfig @@ -0,0 +1,34 @@ +# Kinetis KWx series configuration options + +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_KWX + +config NUM_IRQS + default 65 if SOC_MKW22D5 || SOC_MKW24D5 + default 32 if SOC_MKW40Z4 || SOC_MKW41Z4 + +config SPI + default y if SOC_MKW22D5 || SOC_MKW24D5 + +config NET_L2_IEEE802154 + default y if !NET_L2_OPENTHREAD && SOC_MKW41Z4 + +if SOC_MKW40Z4 || SOC_MKW41Z4 + +choice CSPRNG_GENERATOR_CHOICE + default CTR_DRBG_CSPRNG_GENERATOR +endchoice + +choice RNG_GENERATOR_CHOICE + default XOSHIRO_RANDOM_GENERATOR +endchoice + +config TINYCRYPT + default y + depends on ENTROPY_GENERATOR && SOC_MKW41Z4 + +endif # SOC_MKW40Z4 || SOC_MKW41Z4 + +endif # SOC_SERIES_KINETIS_KWX diff --git a/soc/nxp/kinetis/kwx/Kconfig.soc b/soc/nxp/kinetis/kwx/Kconfig.soc new file mode 100644 index 00000000000..ad2a4607221 --- /dev/null +++ b/soc/nxp/kinetis/kwx/Kconfig.soc @@ -0,0 +1,55 @@ +# Kinetis KWx MCU series + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KWX + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "kwx" if SOC_SERIES_KINETIS_KWX + +config SOC_MKW22D5 + bool + select SOC_SERIES_KINETIS_KWX + +config SOC_MKW24D5 + bool + select SOC_SERIES_KINETIS_KWX + +config SOC_MKW40Z4 + bool + select SOC_SERIES_KINETIS_KWX + +config SOC_MKW41Z4 + bool + select SOC_SERIES_KINETIS_KWX + +config SOC + default "mkw22d5" if SOC_MKW22D5 + default "mkw24d5" if SOC_MKW24D5 + default "mkw40z4" if SOC_MKW40Z4 + default "mkw41z4" if SOC_MKW41Z4 + +config SOC_PART_NUMBER_MKW22D512VHA5 + bool + +config SOC_PART_NUMBER_MKW24D512VHA5 + bool + +config SOC_PART_NUMBER_MKW40Z160VHT4 + bool + +config SOC_PART_NUMBER_MKW41Z256VHT4 + bool + +config SOC_PART_NUMBER_MKW41Z512VHT4 + bool + +config SOC_PART_NUMBER + default "MKW22D512VHA5" if SOC_PART_NUMBER_MKW22D512VHA5 + default "MKW24D512VHA5" if SOC_PART_NUMBER_MKW24D512VHA5 + default "MKW40Z160VHT4" if SOC_PART_NUMBER_MKW40Z160VHT4 + default "MKW41Z256VHT4" if SOC_PART_NUMBER_MKW41Z256VHT4 + default "MKW41Z512VHT4" if SOC_PART_NUMBER_MKW41Z512VHT4 diff --git a/soc/arm/nxp_kinetis/kwx/soc.h b/soc/nxp/kinetis/kwx/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/kwx/soc.h rename to soc/nxp/kinetis/kwx/soc.h diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c b/soc/nxp/kinetis/kwx/soc_kw2xd.c similarity index 100% rename from soc/arm/nxp_kinetis/kwx/soc_kw2xd.c rename to soc/nxp/kinetis/kwx/soc_kw2xd.c diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw4xz.c b/soc/nxp/kinetis/kwx/soc_kw4xz.c similarity index 100% rename from soc/arm/nxp_kinetis/kwx/soc_kw4xz.c rename to soc/nxp/kinetis/kwx/soc_kw4xz.c diff --git a/soc/nxp/kinetis/soc.yml b/soc/nxp/kinetis/soc.yml new file mode 100644 index 00000000000..c2b27eb9841 --- /dev/null +++ b/soc/nxp/kinetis/soc.yml @@ -0,0 +1,31 @@ +family: +- name: kinetis + series: + - name: kwx + socs: + - name: mkw22d5 + - name: mkw24d5 + - name: mkw40z4 + - name: mkw41z4 + - name: k6x + socs: + - name: mk64f12 + - name: mk66f18 + - name: k2x + socs: + - name: mk22f51212 + - name: mk22f12 + - name: ke1xf + socs: + - name: mke18f16 + - name: k8x + socs: + - name: mk80f25615 + - name: mk82f25615 + - name: kl2x + socs: + - name: mkl25z4 + - name: kv5x + socs: + - name: mkv56f24 + - name: mkv58f24 diff --git a/soc/arm64/nxp_layerscape/CMakeLists.txt b/soc/nxp/layerscape/CMakeLists.txt similarity index 100% rename from soc/arm64/nxp_layerscape/CMakeLists.txt rename to soc/nxp/layerscape/CMakeLists.txt diff --git a/soc/nxp/layerscape/Kconfig b/soc/nxp/layerscape/Kconfig new file mode 100644 index 00000000000..5b5b1c572f8 --- /dev/null +++ b/soc/nxp/layerscape/Kconfig @@ -0,0 +1,11 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +# +if SOC_FAMILY_NXP_LAYERSCAPE + +rsource "*/Kconfig" + +endif # SOC_FAMILY_NXP_LAYERSCAPE diff --git a/soc/nxp/layerscape/Kconfig.defconfig b/soc/nxp/layerscape/Kconfig.defconfig new file mode 100644 index 00000000000..99feef9bf84 --- /dev/null +++ b/soc/nxp/layerscape/Kconfig.defconfig @@ -0,0 +1,11 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_FAMILY_NXP_LAYERSCAPE + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_NXP_LAYERSCAPE diff --git a/soc/nxp/layerscape/Kconfig.soc b/soc/nxp/layerscape/Kconfig.soc new file mode 100644 index 00000000000..0ea005c8175 --- /dev/null +++ b/soc/nxp/layerscape/Kconfig.soc @@ -0,0 +1,13 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_FAMILY_NXP_LAYERSCAPE + bool + +config SOC_FAMILY + default "nxp_layerscape" if SOC_FAMILY_NXP_LAYERSCAPE + +rsource "*/Kconfig.soc" diff --git a/soc/arm64/nxp_layerscape/ls1046a/CMakeLists.txt b/soc/nxp/layerscape/ls1046a/CMakeLists.txt similarity index 100% rename from soc/arm64/nxp_layerscape/ls1046a/CMakeLists.txt rename to soc/nxp/layerscape/ls1046a/CMakeLists.txt diff --git a/soc/nxp/layerscape/ls1046a/Kconfig b/soc/nxp/layerscape/ls1046a/Kconfig new file mode 100644 index 00000000000..bc151b6b665 --- /dev/null +++ b/soc/nxp/layerscape/ls1046a/Kconfig @@ -0,0 +1,10 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_LS1046A + select ARM64 + select CPU_CORTEX_A72 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS diff --git a/soc/nxp/layerscape/ls1046a/Kconfig.defconfig b/soc/nxp/layerscape/ls1046a/Kconfig.defconfig new file mode 100644 index 00000000000..f22b14b4e26 --- /dev/null +++ b/soc/nxp/layerscape/ls1046a/Kconfig.defconfig @@ -0,0 +1,19 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_LS1046A + +config NUM_IRQS + int + default 240 + +config FLASH_SIZE + default 0 + +config FLASH_BASE_ADDRESS + default 0 + +endif diff --git a/soc/nxp/layerscape/ls1046a/Kconfig.soc b/soc/nxp/layerscape/ls1046a/Kconfig.soc new file mode 100644 index 00000000000..cced813a62c --- /dev/null +++ b/soc/nxp/layerscape/ls1046a/Kconfig.soc @@ -0,0 +1,31 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_LS1046A + bool + select SOC_FAMILY_NXP_LAYERSCAPE + +config SOC_LS1046A + bool + select SOC_SERIES_LS1046A + help + NXP Layerscape ls1046a + +config SOC + default "ls1046a" if SOC_LS1046A + +config SOC_SERIES + default "ls1046a" if SOC_SERIES_LS1046A + +config SOC_PART_NUMBER_LS1046A + bool + +config SOC_PART_NUMBER_LS1026A + bool + +config SOC_PART_NUMBER + default "LS1046A" if SOC_PART_NUMBER_LS1046A + default "LS1026A" if SOC_PART_NUMBER_LS1026A diff --git a/soc/arm64/nxp_layerscape/ls1046a/mmu_regions.c b/soc/nxp/layerscape/ls1046a/mmu_regions.c similarity index 100% rename from soc/arm64/nxp_layerscape/ls1046a/mmu_regions.c rename to soc/nxp/layerscape/ls1046a/mmu_regions.c diff --git a/soc/nxp/layerscape/soc.yml b/soc/nxp/layerscape/soc.yml new file mode 100644 index 00000000000..69fae2c6abd --- /dev/null +++ b/soc/nxp/layerscape/soc.yml @@ -0,0 +1,6 @@ +family: +- name: nxp_layerscape + series: + - name: ls1046a + socs: + - name: ls1046a diff --git a/soc/arm/nxp_lpc/CMakeLists.txt b/soc/nxp/lpc/CMakeLists.txt similarity index 100% rename from soc/arm/nxp_lpc/CMakeLists.txt rename to soc/nxp/lpc/CMakeLists.txt diff --git a/soc/nxp/lpc/Kconfig b/soc/nxp/lpc/Kconfig new file mode 100644 index 00000000000..ac4411e6c5f --- /dev/null +++ b/soc/nxp/lpc/Kconfig @@ -0,0 +1,12 @@ +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_LPC + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select CLOCK_CONTROL + select ARM + +if SOC_FAMILY_LPC +rsource "*/Kconfig" + +endif # SOC_FAMILY_LPC diff --git a/soc/nxp/lpc/Kconfig.defconfig b/soc/nxp/lpc/Kconfig.defconfig new file mode 100644 index 00000000000..ca61dec3a84 --- /dev/null +++ b/soc/nxp/lpc/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_LPC + +config SERIAL_INIT_PRIORITY + default 55 if SERIAL + +config BUILD_WITH_TFM + default y if TRUSTED_EXECUTION_NONSECURE + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_LPC diff --git a/soc/nxp/lpc/Kconfig.soc b/soc/nxp/lpc/Kconfig.soc new file mode 100644 index 00000000000..46b6b54c2f1 --- /dev/null +++ b/soc/nxp/lpc/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_LPC + bool + +config SOC_FAMILY + default "lpc" if SOC_FAMILY_LPC + +rsource "*/Kconfig.soc" diff --git a/soc/nxp/lpc/lpc11u6x/CMakeLists.txt b/soc/nxp/lpc/lpc11u6x/CMakeLists.txt new file mode 100644 index 00000000000..628e4ab155d --- /dev/null +++ b/soc/nxp/lpc/lpc11u6x/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/lpc/lpc11u6x/Kconfig b/soc/nxp/lpc/lpc11u6x/Kconfig new file mode 100644 index 00000000000..52ccbdd5ed8 --- /dev/null +++ b/soc/nxp/lpc/lpc11u6x/Kconfig @@ -0,0 +1,14 @@ +# LPC LPC11U6X MCU line +# +# Copyright (c) 2020, Seagate +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_LPC11U6X + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select PINCTRL + select CLOCK_CONTROL diff --git a/soc/nxp/lpc/lpc11u6x/Kconfig.defconfig b/soc/nxp/lpc/lpc11u6x/Kconfig.defconfig new file mode 100644 index 00000000000..7f924a52a7b --- /dev/null +++ b/soc/nxp/lpc/lpc11u6x/Kconfig.defconfig @@ -0,0 +1,15 @@ +# LPC LPC11U6X MCU line +# +# Copyright (c) 2020, Seagate +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_LPC11U6X + +config NUM_IRQS + # must be >= the highest interrupt number used + default 40 + +endif # SOC_SERIES_LPC11U6X diff --git a/soc/nxp/lpc/lpc11u6x/Kconfig.soc b/soc/nxp/lpc/lpc11u6x/Kconfig.soc new file mode 100644 index 00000000000..94a5067b29c --- /dev/null +++ b/soc/nxp/lpc/lpc11u6x/Kconfig.soc @@ -0,0 +1,55 @@ +# NXP LPC11U6x series + +# Copyright 2024 NXP + +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_LPC11U6X + bool + select SOC_FAMILY_LPC + +config SOC_SERIES + default "lpc11u6x" if SOC_SERIES_LPC11U6X + +config SOC_LPC11U68 + bool + select SOC_SERIES_LPC11U6X + +config SOC_LPC11U67 + bool + select SOC_SERIES_LPC11U6X + +config SOC_LPC11U66 + bool + select SOC_SERIES_LPC11U6X + +config SOC + default "lpc11u66" if SOC_LPC11U66 + default "lpc11u67" if SOC_LPC11U67 + default "lpc11u68" if SOC_LPC11U68 + +config SOC_PART_NUMBER_LPC11U66JBD48 + bool +config SOC_PART_NUMBER_LPC11U67JBD48 + bool +config SOC_PART_NUMBER_LPC11U67JBD64 + bool +config SOC_PART_NUMBER_LPC11U67JBD100 + bool +config SOC_PART_NUMBER_LPC11U68JBD48 + bool +config SOC_PART_NUMBER_LPC11U68JBD64 + bool +config SOC_PART_NUMBER_LPC11U68JBD100 + bool + +config SOC_PART_NUMBER + default "LPC11U66JBD48" if SOC_PART_NUMBER_LPC11U66JBD48 + default "LPC11U67JBD48" if SOC_PART_NUMBER_LPC11U67JBD48 + default "LPC11U67JBD64" if SOC_PART_NUMBER_LPC11U67JBD64 + default "LPC11U67JBD100" if SOC_PART_NUMBER_LPC11U67JBD100 + default "LPC11U68JBD48" if SOC_PART_NUMBER_LPC11U68JBD48 + default "LPC11U68JBD64" if SOC_PART_NUMBER_LPC11U68JBD64 + default "LPC11U68JBD100" if SOC_PART_NUMBER_LPC11U68JBD100 diff --git a/soc/arm/nxp_lpc/lpc11u6x/iap.h b/soc/nxp/lpc/lpc11u6x/iap.h similarity index 100% rename from soc/arm/nxp_lpc/lpc11u6x/iap.h rename to soc/nxp/lpc/lpc11u6x/iap.h diff --git a/soc/arm/nxp_lpc/lpc11u6x/pinctrl_soc.h b/soc/nxp/lpc/lpc11u6x/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc11u6x/pinctrl_soc.h rename to soc/nxp/lpc/lpc11u6x/pinctrl_soc.h diff --git a/soc/arm/nxp_lpc/lpc11u6x/soc.h b/soc/nxp/lpc/lpc11u6x/soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc11u6x/soc.h rename to soc/nxp/lpc/lpc11u6x/soc.h diff --git a/soc/nxp/lpc/lpc51u68/CMakeLists.txt b/soc/nxp/lpc/lpc51u68/CMakeLists.txt new file mode 100644 index 00000000000..3bae960a47e --- /dev/null +++ b/soc/nxp/lpc/lpc51u68/CMakeLists.txt @@ -0,0 +1,18 @@ +# +# Copyright (c) 2021 metraTec GmbH +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +zephyr_library() + +zephyr_library_sources(soc.c) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/lpc/lpc51u68/Kconfig b/soc/nxp/lpc/lpc51u68/Kconfig new file mode 100644 index 00000000000..fc920bb89e4 --- /dev/null +++ b/soc/nxp/lpc/lpc51u68/Kconfig @@ -0,0 +1,21 @@ +# LPC51U68 series configuration options +# +# Copyright (c) 2021 metraTec GmbH +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_LPC51U68 + select ARM + select CPU_CORTEX_M0PLUS + select HAS_MCUX + select HAS_MCUX_FLEXCOMM + select HAS_MCUX_SYSCON + select HAS_MCUX_SCTIMER + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT + +config SOC_LPC51U68 + select CLOCK_CONTROL diff --git a/soc/nxp/lpc/lpc51u68/Kconfig.defconfig b/soc/nxp/lpc/lpc51u68/Kconfig.defconfig new file mode 100644 index 00000000000..b62054ea6db --- /dev/null +++ b/soc/nxp/lpc/lpc51u68/Kconfig.defconfig @@ -0,0 +1,17 @@ +# LPC51U68 series configuration options + +# Copyright (c) 2021 metraTec GmbH +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_LPC51U68 + +config NUM_IRQS + # must be >= the highest interrupt number used. + default 32 + +config SOC_FLASH_LPC + default y + depends on FLASH + +endif # SOC_SERIES_LPC51U86 diff --git a/soc/nxp/lpc/lpc51u68/Kconfig.soc b/soc/nxp/lpc/lpc51u68/Kconfig.soc new file mode 100644 index 00000000000..a09015b66f1 --- /dev/null +++ b/soc/nxp/lpc/lpc51u68/Kconfig.soc @@ -0,0 +1,29 @@ +# LPC LPC51U68 MCU line + +# Copyright (c) 2021 metraTec GmbH +# Copyright 2024 NXP +# SPDX-License Identifier: Apache-2.0 + +config SOC_SERIES_LPC51U68 + bool + select SOC_FAMILY_LPC + +config SOC_SERIES + default "lpc51u68" if SOC_SERIES_LPC51U68 + +config SOC_LPC51U68 + bool + select SOC_SERIES_LPC51U68 + +config SOC + default "lpc51u68" if SOC_LPC51U68 + +config SOC_PART_NUMBER_LPC51U68JBD48 + bool + +config SOC_PART_NUMBER_LPC51U68JBD64 + bool + +config SOC_PART_NUMBER + default "LPC51U68JBD48" if SOC_PART_NUMBER_LPC51U68JBD48 + default "LPC51U68JBD64" if SOC_PART_NUMBER_LPC51U68JBD64 diff --git a/soc/arm/nxp_lpc/lpc51u68/linker.ld b/soc/nxp/lpc/lpc51u68/linker.ld similarity index 100% rename from soc/arm/nxp_lpc/lpc51u68/linker.ld rename to soc/nxp/lpc/lpc51u68/linker.ld diff --git a/soc/arm/nxp_lpc/lpc51u68/pinctrl_soc.h b/soc/nxp/lpc/lpc51u68/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc51u68/pinctrl_soc.h rename to soc/nxp/lpc/lpc51u68/pinctrl_soc.h diff --git a/soc/arm/nxp_lpc/lpc51u68/soc.c b/soc/nxp/lpc/lpc51u68/soc.c similarity index 100% rename from soc/arm/nxp_lpc/lpc51u68/soc.c rename to soc/nxp/lpc/lpc51u68/soc.c diff --git a/soc/arm/nxp_lpc/lpc51u68/soc.h b/soc/nxp/lpc/lpc51u68/soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc51u68/soc.h rename to soc/nxp/lpc/lpc51u68/soc.h diff --git a/soc/nxp/lpc/lpc54xxx/CMakeLists.txt b/soc/nxp/lpc/lpc54xxx/CMakeLists.txt new file mode 100644 index 00000000000..d8fab22133d --- /dev/null +++ b/soc/nxp/lpc/lpc54xxx/CMakeLists.txt @@ -0,0 +1,25 @@ +# +# Copyright (c) 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +zephyr_library() + +zephyr_library_sources(soc.c) +zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT gcc/startup_LPC54114_cm4.S) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) + + +# CMSIS SystemInit allows us to skip enabling clock to SRAM2 bank via +# this compiler definition +if(NOT DEFINED CONFIG_LPC54XXX_SRAM2_CLOCK) +zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/lpc/lpc54xxx/Kconfig b/soc/nxp/lpc/lpc54xxx/Kconfig new file mode 100644 index 00000000000..78997d6504b --- /dev/null +++ b/soc/nxp/lpc/lpc54xxx/Kconfig @@ -0,0 +1,69 @@ +# LPC LPC54XXX MCU line + +# Copyright 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_LPC54XXX + select ARM + select HAS_MCUX + select HAS_MCUX_FLEXCOMM + select HAS_MCUX_SYSCON + select CPU_CORTEX_M_HAS_SYSTICK + select PLATFORM_SPECIFIC_INIT + +config SOC_LPC54114_M4 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT + select CLOCK_CONTROL + select HAS_MCUX_IAP_LEGACY + +config SOC_LPC54114_M0 + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_VTOR + select CLOCK_CONTROL + +config MCUX_CORE_SUFFIX + default "_cm4" if SOC_LPC54114_M4 + default "_cm0plus" if SOC_LPC54114_M0 + +if SOC_SERIES_LPC54XXX + +config SECOND_CORE_MCUX + bool "LPC54114 Cortex-M0 second core" + help + Driver for second core startup + +config SECOND_CORE_BOOT_ADDRESS_MCUX + depends on SECOND_CORE_MCUX + hex "Address the second core will boot at" + default 0x20010000 + help + This is the address the second core will boot from. Additionally this + address is where we will copy the SECOND_IMAGE to. We default this to + the base of SRAM1. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition + +# Move the LMA address of second core into flash +config BUILD_OUTPUT_ADJUST_LMA + depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 + default "-0x20010000+\ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))" + +config BUILD_OUTPUT_INFO_HEADER + default y + depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 + +config LPC54XXX_SRAM2_CLOCK + bool "Clock LPC54XXX SRAM2" + default y + help + SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit + will enable the clock to this RAM bank. Disable this Kconfig to leave + this ram bank untouched out of reset. + +endif # SOC_SERIES_LPC54XXX diff --git a/soc/nxp/lpc/lpc54xxx/Kconfig.defconfig b/soc/nxp/lpc/lpc54xxx/Kconfig.defconfig new file mode 100644 index 00000000000..5955a2f8e36 --- /dev/null +++ b/soc/nxp/lpc/lpc54xxx/Kconfig.defconfig @@ -0,0 +1,15 @@ +# NXP LPC54114 M0 platform configuration options + +# Copyright 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_LPC54XXX + +config GPIO + default n if SOC_LPC54114_M0 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 40 + +endif # SOC_SERIES_LPC54XXX diff --git a/soc/nxp/lpc/lpc54xxx/Kconfig.soc b/soc/nxp/lpc/lpc54xxx/Kconfig.soc new file mode 100644 index 00000000000..346facb7129 --- /dev/null +++ b/soc/nxp/lpc/lpc54xxx/Kconfig.soc @@ -0,0 +1,38 @@ +# LPC LPC54XXX MCU line + +# Copyright (c) 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_LPC54XXX + bool + select SOC_FAMILY_LPC + +config SOC_SERIES + default "lpc54xxx" if SOC_SERIES_LPC54XXX + +config SOC_LPC54114 + bool + select SOC_SERIES_LPC54XXX + +config SOC_LPC54114_M4 + bool + select SOC_LPC54114 + +config SOC_LPC54114_M0 + bool + select SOC_LPC54114 + +# The NXP HAL expects the SOC to just be lpc54114 if targeting +# the M4. When targeting M0 it expects lpc54114_m0. +# +# Action to update the NXP HAL to support checking for SOC_LPC54114_M0 +# instead. +config SOC + default "lpc54114" if SOC_LPC54114_M4 + default "lpc54114" if SOC_LPC54114_M0 + +config SOC_PART_NUMBER_LPC54114J256BD64 + bool + +config SOC_PART_NUMBER + default "LPC54114J256BD64" if SOC_PART_NUMBER_LPC54114J256BD64 diff --git a/soc/arm/nxp_lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S b/soc/nxp/lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S similarity index 100% rename from soc/arm/nxp_lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S rename to soc/nxp/lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S diff --git a/soc/arm/nxp_lpc/lpc54xxx/linker.ld b/soc/nxp/lpc/lpc54xxx/linker.ld similarity index 100% rename from soc/arm/nxp_lpc/lpc54xxx/linker.ld rename to soc/nxp/lpc/lpc54xxx/linker.ld diff --git a/soc/arm/nxp_lpc/lpc54xxx/pinctrl_soc.h b/soc/nxp/lpc/lpc54xxx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc54xxx/pinctrl_soc.h rename to soc/nxp/lpc/lpc54xxx/pinctrl_soc.h diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.c b/soc/nxp/lpc/lpc54xxx/soc.c similarity index 100% rename from soc/arm/nxp_lpc/lpc54xxx/soc.c rename to soc/nxp/lpc/lpc54xxx/soc.c diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.h b/soc/nxp/lpc/lpc54xxx/soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc54xxx/soc.h rename to soc/nxp/lpc/lpc54xxx/soc.h diff --git a/soc/nxp/lpc/lpc55xxx/CMakeLists.txt b/soc/nxp/lpc/lpc55xxx/CMakeLists.txt new file mode 100644 index 00000000000..5f66a3eb9d8 --- /dev/null +++ b/soc/nxp/lpc/lpc55xxx/CMakeLists.txt @@ -0,0 +1,29 @@ +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +zephyr_library() + +zephyr_library_sources(soc.c) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) +if(DEFINED CONFIG_LPC55XXX_USB_RAM) +zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER + SECTIONS usb.ld) + +zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) +endif() + +# CMSIS SystemInit allows us to skip enabling clock to SRAM banks via +# this compiler definition +if(NOT DEFINED CONFIG_LPC55XXX_SRAM_CLOCKS) +zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/lpc/lpc55xxx/Kconfig b/soc/nxp/lpc/lpc55xxx/Kconfig new file mode 100644 index 00000000000..2fcc3e4ee66 --- /dev/null +++ b/soc/nxp/lpc/lpc55xxx/Kconfig @@ -0,0 +1,114 @@ +# Copyright 2019,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_LPC55XXX + select HAS_MCUX + select HAS_MCUX_FLEXCOMM + select HAS_MCUX_SYSCON + select HAS_MCUX_WWDT + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_DWT + select PLATFORM_SPECIFIC_INIT + +config SOC_LPC55S06 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE + select HAS_MCUX_RNG + +config SOC_LPC55S16 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE + select HAS_MCUX_MCAN + select HAS_MCUX_RNG + +config SOC_LPC55S28 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select HAS_MCUX_IAP + select HAS_MCUX_LPADC + select HAS_MCUX_LPC_DMA + select HAS_MCUX_RNG + +config SOC_LPC55S36 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select HAS_MCUX_MCAN + select HAS_MCUX_PWM + +config SOC_LPC55S69 + select CPU_CORTEX_M33 + +config SOC_LPC55S69_CPU0 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select HAS_MCUX_IAP + select HAS_MCUX_LPADC + select HAS_MCUX_LPC_DMA + select HAS_MCUX_USB_LPCIP3511 + select HAS_MCUX_CTIMER + select HAS_MCUX_SCTIMER + select HAS_MCUX_RNG + +if SOC_SERIES_LPC55XXX + +config INIT_PLL0 + bool "Initialize PLL0" + +config INIT_PLL1 + bool "Initialize PLL1" + default "y" + depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM) + help + In the LPC55XXX Family, this is currently being used to set the + core clock value at it's highest frequency which clocks at 150MHz. + Note that flash programming operations are limited to 100MHz, and + this PLL should not be used as the core clock in those cases. + +config SECOND_CORE_MCUX + bool "LPC55xxx's second core" + +config SECOND_CORE_BOOT_ADDRESS_MCUX + depends on SECOND_CORE_MCUX + hex "Address the second core will boot at" + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION)) + help + This is the address the second core will boot from. + +config LPC55XXX_SRAM_CLOCKS + bool "CLock LPC SRAM banks" + +config LPC55XXX_USB_RAM + bool + +if SOC_LPC55S69 + +config SOC_FLASH_MCUX + bool + +endif # SOC_LPC55S69 + +config MCUX_CORE_SUFFIX + default "_cm33_core0" if SOC_LPC55S69_CPU0 + default "_cm33_core1" if SOC_LPC55S69_CPU1 + +endif # SOC_SERIES_LPC55XXX diff --git a/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig b/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig new file mode 100644 index 00000000000..ed43f5041ed --- /dev/null +++ b/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig @@ -0,0 +1,114 @@ +# Copyright 2019,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_LPC55XXX + +config NUM_IRQS + # must be >= the highest interrupt number used + default 60 + +# In the LPC55XXX Family, this is currently being used to set the +# core clock value at it's highest frequency which clocks at 150MHz. +# Note that flash programming operations are limited to 100MHz, and +# this PLL should not be used as the core clock in those cases. +config INIT_PLL1 + default "y" + depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 144000000 if INIT_PLL1 + default 96000000 + +# Indicates the second core will be enabled, and the part will run +# in dual core mode. +config SECOND_CORE_MCUX + depends on HAS_MCUX + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition + + +# Move the LMA for the second core image to be in the flash region of primary +# core, so that JLink flash will load it correctly. +config BUILD_OUTPUT_ADJUST_LMA + depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1 + default "0x10000000" + +# SRAM controllers 1,2,3, and 4 are disabled at reset. +# By default, CMSIS SystemInit will enable the clock to these RAM banks. +# Disable this Kconfig to leave the ram banks untouched out of reset. +config LPC55XXX_SRAM_CLOCKS + default y + +# Some SoC's in the LPC5500 Series do have a dedicated USB RAM. +# By default, USB RAM is assumed to be present. +# Disable this Kconfig in case there is no dedicated USB RAM. +config LPC55XXX_USB_RAM + default y + +if SOC_LPC55S06 + +config LPC55XXX_USB_RAM + default n + +endif # SOC_LPC55S06 + +if SOC_LPC55S16 + +config CAN_MCUX_MCAN + default y + depends on CAN + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +endif # SOC_LPC55S16 + +if SOC_LPC55S28 + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +endif # SOC_LPC55S28 + +if SOC_LPC55S36 + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +config LPC55XXX_USB_RAM + default n + +endif # SOC_LPC55S36 + +if SOC_LPC55S69 + +config SOC_FLASH_MCUX + default y + depends on FLASH + depends on !TRUSTED_EXECUTION_NONSECURE + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +config I2S_MCUX_FLEXCOMM + select INIT_PLL0 + +endif # SOC_LPC55S69 + +if SOC_LPC55S69_CPU1 + + +config GPIO + default y + +config SERIAL + default n + +endif # SOC_LPC55S69_CPU1 + +endif # SOC_SERIES_LPC55XXX diff --git a/soc/nxp/lpc/lpc55xxx/Kconfig.soc b/soc/nxp/lpc/lpc55xxx/Kconfig.soc new file mode 100644 index 00000000000..e5b668b54fa --- /dev/null +++ b/soc/nxp/lpc/lpc55xxx/Kconfig.soc @@ -0,0 +1,74 @@ +# Copyright 2019, 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_LPC55XXX + bool + select SOC_FAMILY_LPC + +config SOC_SERIES + default "lpc55xxx" if SOC_SERIES_LPC55XXX + +config SOC_LPC55S06 + bool + select SOC_SERIES_LPC55XXX + +config SOC_LPC55S16 + bool + select SOC_SERIES_LPC55XXX + +config SOC_LPC55S28 + bool + select SOC_SERIES_LPC55XXX + +config SOC_LPC55S36 + bool + select SOC_SERIES_LPC55XXX + +config SOC_LPC55S69 + bool + select SOC_SERIES_LPC55XXX + +config SOC_LPC55S69_CPU0 + bool + select SOC_LPC55S69 + +config SOC_LPC55S69_CPU1 + bool + select SOC_LPC55S69 + +config SOC + default "lpc55s69" if SOC_LPC55S69_CPU0 || SOC_LPC55S69_CPU1 + default "lpc55s06" if SOC_LPC55S06 + default "lpc55s16" if SOC_LPC55S16 + default "lpc55s28" if SOC_LPC55S28 + default "lpc55s36" if SOC_LPC55S36 + +config SOC_PART_NUMBER_LPC55S06JBD64 + bool + +config SOC_PART_NUMBER_LPC55S16JBD64 + bool + +config SOC_PART_NUMBER_LPC55S16JBD100 + bool + +config SOC_PART_NUMBER_LPC55S28JBD100 + bool + +config SOC_PART_NUMBER_LPC55S36JBD100 + bool + +config SOC_PART_NUMBER_LPC55S69JBD100 + bool + +config SOC_PART_NUMBER_LPC55S69JET98 + bool + +config SOC_PART_NUMBER + default "LPC55S06JBD64" if SOC_PART_NUMBER_LPC55S06JBD64 + default "LPC55S16JBD64" if SOC_PART_NUMBER_LPC55S16JBD64 + default "LPC55S16JBD100" if SOC_PART_NUMBER_LPC55S16JBD100 + default "LPC55S28JBD100" if SOC_PART_NUMBER_LPC55S28JBD100 + default "LPC55S36JBD100" if SOC_PART_NUMBER_LPC55S36JBD100 + default "LPC55S69JBD100" if SOC_PART_NUMBER_LPC55S69JBD100 + default "LPC55S69JET98" if SOC_PART_NUMBER_LPC55S69JET98 diff --git a/soc/arm/nxp_lpc/lpc55xxx/linker.ld b/soc/nxp/lpc/lpc55xxx/linker.ld similarity index 100% rename from soc/arm/nxp_lpc/lpc55xxx/linker.ld rename to soc/nxp/lpc/lpc55xxx/linker.ld diff --git a/soc/arm/nxp_lpc/lpc55xxx/pinctrl_soc.h b/soc/nxp/lpc/lpc55xxx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc55xxx/pinctrl_soc.h rename to soc/nxp/lpc/lpc55xxx/pinctrl_soc.h diff --git a/soc/arm/nxp_lpc/lpc55xxx/soc.c b/soc/nxp/lpc/lpc55xxx/soc.c similarity index 100% rename from soc/arm/nxp_lpc/lpc55xxx/soc.c rename to soc/nxp/lpc/lpc55xxx/soc.c diff --git a/soc/arm/nxp_lpc/lpc55xxx/soc.h b/soc/nxp/lpc/lpc55xxx/soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc55xxx/soc.h rename to soc/nxp/lpc/lpc55xxx/soc.h diff --git a/soc/arm/nxp_lpc/lpc55xxx/usb.ld b/soc/nxp/lpc/lpc55xxx/usb.ld similarity index 100% rename from soc/arm/nxp_lpc/lpc55xxx/usb.ld rename to soc/nxp/lpc/lpc55xxx/usb.ld diff --git a/soc/nxp/lpc/soc.yml b/soc/nxp/lpc/soc.yml new file mode 100644 index 00000000000..32b07924fb6 --- /dev/null +++ b/soc/nxp/lpc/soc.yml @@ -0,0 +1,27 @@ +family: +- name: lpc + series: + - name: lpc11u6x + socs: + - name: lpc11u66 + - name: lpc11u67 + - name: lpc11u68 + - name: lpc51u68 + socs: + - name: lpc51u68 + - name: lpc54xxx + socs: + - name: lpc54114 + cpuclusters: + - name: m4 + - name: m0 + - name: lpc55xxx + socs: + - name: lpc55s06 + - name: lpc55s16 + - name: lpc55s28 + - name: lpc55s36 + - name: lpc55s69 + cpuclusters: + - name: cpu0 + - name: cpu1 diff --git a/soc/arm/nxp_s32/CMakeLists.txt b/soc/nxp/s32/CMakeLists.txt similarity index 100% rename from soc/arm/nxp_s32/CMakeLists.txt rename to soc/nxp/s32/CMakeLists.txt diff --git a/soc/nxp/s32/Kconfig b/soc/nxp/s32/Kconfig new file mode 100644 index 00000000000..9b608588e21 --- /dev/null +++ b/soc/nxp/s32/Kconfig @@ -0,0 +1,31 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NXP_S32 + +config NXP_S32_FUNC_RESET_THRESHOLD + int "Functional Reset Escalation threshold" + default 15 + range 0 15 + help + If the value of this option is 0, the Functional reset escalation + function is disabled. Any other value is the number of Functional + resets that causes a Destructive reset, if the FRET register isn't + written to beforehand. + Default to maximum threshold (hardware reset value). + +config NXP_S32_DEST_RESET_THRESHOLD + int "Destructive Reset Escalation threshold" + default 0 + range 0 15 + help + If the value of this field is 0, the Destructive reset escalation + function is disabled. Any other value is the number of Destructive + resets which keeps the chip in the reset state until the next power-on + reset triggers a new reset sequence, if the DRET register isn't + written to beforehand. + Default to disabled (hardware reset value). + +rsource "*/Kconfig" + +endif # SOC_FAMILY_NXP_S32 diff --git a/soc/nxp/s32/Kconfig.defconfig b/soc/nxp/s32/Kconfig.defconfig new file mode 100644 index 00000000000..47d7caffcfb --- /dev/null +++ b/soc/nxp/s32/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NXP_S32 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_NXP_S32 diff --git a/soc/nxp/s32/Kconfig.soc b/soc/nxp/s32/Kconfig.soc new file mode 100644 index 00000000000..875db9b12fe --- /dev/null +++ b/soc/nxp/s32/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_S32 + bool + +config SOC_FAMILY + default "nxp_s32" if SOC_FAMILY_NXP_S32 + +rsource "*/Kconfig.soc" diff --git a/soc/nxp/s32/common/CMakeLists.txt b/soc/nxp/s32/common/CMakeLists.txt new file mode 100644 index 00000000000..7b98b446338 --- /dev/null +++ b/soc/nxp/s32/common/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2022-2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_sources(osif.c) +zephyr_sources_ifdef(CONFIG_SOC_SERIES_S32K3 power_soc.c) diff --git a/soc/arm/nxp_s32/common/cmsis_rtos_v2_adapt.h b/soc/nxp/s32/common/cmsis_rtos_v2_adapt.h similarity index 100% rename from soc/arm/nxp_s32/common/cmsis_rtos_v2_adapt.h rename to soc/nxp/s32/common/cmsis_rtos_v2_adapt.h diff --git a/soc/arm/nxp_s32/common/osif.c b/soc/nxp/s32/common/osif.c similarity index 94% rename from soc/arm/nxp_s32/common/osif.c rename to soc/nxp/s32/common/osif.c index 73b5c6c1d1f..5216f632a11 100644 --- a/soc/arm/nxp_s32/common/osif.c +++ b/soc/nxp/s32/common/osif.c @@ -8,7 +8,7 @@ #include #include -#if defined(CONFIG_SOC_SERIES_S32K1XX) +#if defined(CONFIG_SOC_SERIES_S32K1) /* Aliases needed to build with different SoC-specific HAL versions */ #define CPXNUM CPxNUM #define MSCM_CPXNUM_CPN_MASK MSCM_CPxNUM_CPN_MASK diff --git a/soc/arm/nxp_s32/common/pinctrl_soc.h b/soc/nxp/s32/common/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_s32/common/pinctrl_soc.h rename to soc/nxp/s32/common/pinctrl_soc.h diff --git a/soc/arm/nxp_s32/common/power_soc.c b/soc/nxp/s32/common/power_soc.c similarity index 98% rename from soc/arm/nxp_s32/common/power_soc.c rename to soc/nxp/s32/common/power_soc.c index 3e277155cb8..a2ca0cabfca 100644 --- a/soc/arm/nxp_s32/common/power_soc.c +++ b/soc/nxp/s32/common/power_soc.c @@ -71,7 +71,7 @@ static int nxp_s32_power_init(void) }; const Power_Ip_PMC_ConfigType pmc_cfg = { -#ifdef CONFIG_SOC_SERIES_S32K3XX +#ifdef CONFIG_SOC_SERIES_S32K3 /* PMC Configuration Register (CONFIG) */ .ConfigRegister = PMC_CONFIG_LMEN(IS_ENABLED(CONFIG_NXP_S32_PMC_LMEN)) | PMC_CONFIG_LMBCTLEN(IS_ENABLED(CONFIG_NXP_S32_PMC_LMBCTLEN)), diff --git a/soc/nxp/s32/s32k1/CMakeLists.txt b/soc/nxp/s32/s32k1/CMakeLists.txt new file mode 100644 index 00000000000..cb66e9e1ffc --- /dev/null +++ b/soc/nxp/s32/s32k1/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") + +zephyr_sources(soc.c) +zephyr_sources_ifdef(CONFIG_ARM_MPU nxp_mpu_regions.c) + +zephyr_sources_ifdef(CONFIG_NXP_S32_FLASH_CONFIG flash_configuration.c) +zephyr_linker_sources_ifdef(CONFIG_NXP_S32_FLASH_CONFIG ROM_START SORT_KEY 0x1 flash_config.ld) diff --git a/soc/nxp/s32/s32k1/Kconfig b/soc/nxp/s32/s32k1/Kconfig new file mode 100644 index 00000000000..c1b6de3e3ef --- /dev/null +++ b/soc/nxp/s32/s32k1/Kconfig @@ -0,0 +1,124 @@ +# NXP S32K1XX MCUs series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32K1 + select ARM + select HAS_NXP_S32_HAL + select HAS_MCUX + select CPU_HAS_NXP_MPU + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select MPU_ALLOW_FLASH_WRITE if !XIP + select CLOCK_CONTROL + select HAS_MCUX_LPUART + select HAS_MCUX_LPI2C + select HAS_MCUX_LPSPI + select HAS_MCUX_FTM + select HAS_MCUX_FLEXCAN + select HAS_MCUX_WDOG32 + select HAS_MCUX_RTC + +config SOC_S32K116 + select CPU_CORTEX_M0PLUS + +config SOC_S32K118 + select CPU_CORTEX_M0PLUS + +config SOC_S32K142 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +config SOC_S32K142W + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +config SOC_S32K144 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +config SOC_S32K144W + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +config SOC_S32K146 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +config SOC_S32K148 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +if SOC_SERIES_S32K1 + +config WDOG_INIT + bool + default y + +config NXP_S32_FLASH_CONFIG + bool "NXP S32 flash configuration field" + default y if XIP && !BOOTLOADER_MCUBOOT + help + Include the 16-byte flash configuration field that stores default + protection settings (loaded on reset) and security information that + allows the MCU to restrict access to the FTFx module. + +if NXP_S32_FLASH_CONFIG + +config NXP_S32_FLASH_CONFIG_OFFSET + hex "NXP S32 flash configuration field offset" + default 0x400 + +config NXP_S32_FLASH_CONFIG_FSEC + hex "Flash security byte (FSEC)" + range 0 0xff + default 0xfe + help + Configures the reset value of the FSEC register, which includes + backdoor key access, mass erase, factory access, and flash security + options. + +config NXP_S32_FLASH_CONFIG_FOPT + hex "Flash nonvolatile option byte (FOPT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FOPT register, which includes boot, + NMI, and EzPort options. + +config NXP_S32_FLASH_CONFIG_FEPROT + hex "EEPROM protection byte (FEPROT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FEPROT register for FlexNVM + devices. For program flash only devices, this byte is reserved. + +config NXP_S32_FLASH_CONFIG_FDPROT + hex "Data flash protection byte (FDPROT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FDPROT register for FlexNVM + devices. For program flash only devices, this byte is reserved. + +endif # NXP_S32_FLASH_CONFIG + +config NXP_S32_ENABLE_CODE_CACHE + bool "Code cache" + default y + depends on HAS_MCUX_CACHE + +endif # SOC_SERIES_S32K1 diff --git a/soc/nxp/s32/s32k1/Kconfig.defconfig b/soc/nxp/s32/s32k1/Kconfig.defconfig new file mode 100644 index 00000000000..582ebf0e326 --- /dev/null +++ b/soc/nxp/s32/s32k1/Kconfig.defconfig @@ -0,0 +1,30 @@ +# NXP S32K1XX MCU series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_S32K1 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 80000000 + +config NUM_IRQS + default 239 if CPU_CORTEX_M4 + default 47 if CPU_CORTEX_M0PLUS + +config FPU + default y if CPU_HAS_FPU + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +# The S32K1xx have 8 MPU regions, which is not enough for both HW stack protection +# and userspace. Only enable HW stack protection if userspace is not enabled. +config HW_STACK_PROTECTION + default y if !USERSPACE + +endif # SOC_SERIES_S32K1 diff --git a/soc/nxp/s32/s32k1/Kconfig.soc b/soc/nxp/s32/s32k1/Kconfig.soc new file mode 100644 index 00000000000..26a5210bbb7 --- /dev/null +++ b/soc/nxp/s32/s32k1/Kconfig.soc @@ -0,0 +1,371 @@ +# NXP S32K1XX MCUs series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32K1 + bool + select SOC_FAMILY_NXP_S32 + +config SOC_SERIES + default "s32k1" if SOC_SERIES_S32K1 + +config SOC_S32K116 + bool + select SOC_SERIES_S32K1 + +config SOC_S32K118 + bool + select SOC_SERIES_S32K1 + +config SOC_S32K142 + bool + select SOC_SERIES_S32K1 + +config SOC_S32K142W + bool + select SOC_SERIES_S32K1 + +config SOC_S32K144 + bool + select SOC_SERIES_S32K1 + +config SOC_S32K144W + bool + select SOC_SERIES_S32K1 + +config SOC_S32K146 + bool + select SOC_SERIES_S32K1 + +config SOC_S32K148 + bool + select SOC_SERIES_S32K1 + +config SOC + default "s32k116" if SOC_S32K116 + default "s32k118" if SOC_S32K118 + default "s32k142" if SOC_S32K142 + default "s32k142w" if SOC_S32K142W + default "s32k144" if SOC_S32K144 + default "s32k144w" if SOC_S32K144W + default "s32k146" if SOC_S32K146 + default "s32k148" if SOC_S32K148 + +config SOC_PART_NUMBER_FS32K116LAT0MFMT + bool + +config SOC_PART_NUMBER_FS32K116LAT0MLFR + bool + +config SOC_PART_NUMBER_FS32K116LAT0MLFT + bool + +config SOC_PART_NUMBER_FS32K116LIT0VFMT + bool + +config SOC_PART_NUMBER_FS32K116LIT0VLFT + bool + +config SOC_PART_NUMBER_FS32K118LAT0MLFR + bool + +config SOC_PART_NUMBER_FS32K118LAT0MLFT + bool + +config SOC_PART_NUMBER_FS32K118LAT0MLHR + bool + +config SOC_PART_NUMBER_FS32K118LAT0MLHT + bool + +config SOC_PART_NUMBER_FS32K118LIT0VLFT + bool + +config SOC_PART_NUMBER_FS32K142HAT0MLFT + bool + +config SOC_PART_NUMBER_FS32K142HAT0MLHT + bool + +config SOC_PART_NUMBER_FS32K142HAT0MLLR + bool + +config SOC_PART_NUMBER_FS32K142HAT0MLLT + bool + +config SOC_PART_NUMBER_FS32K142HVT0VLHT + bool + +config SOC_PART_NUMBER_FS32K142UAT0VLFT + bool + +config SOC_PART_NUMBER_FS32K142UAT0VLHR + bool + +config SOC_PART_NUMBER_FS32K142UAT0VLHT + bool + +config SOC_PART_NUMBER_FS32K142UAT0VLLR + bool + +config SOC_PART_NUMBER_FS32K142UAT0VLLT + bool + +config SOC_PART_NUMBER_FS32K142UIT0VLHT + bool + +config SOC_PART_NUMBER_FS32K142WAT0WLFT + bool + +config SOC_PART_NUMBER_FS32K142WAT0WLHT + bool + +config SOC_PART_NUMBER_FS32K144HAT0MLFT + bool + +config SOC_PART_NUMBER_FS32K144HAT0MLHR + bool + +config SOC_PART_NUMBER_FS32K144HAT0MLHT + bool + +config SOC_PART_NUMBER_FS32K144HAT0MLLR + bool + +config SOC_PART_NUMBER_FS32K144HAT0MLLT + bool + +config SOC_PART_NUMBER_FS32K144HAT0MMHR + bool + +config SOC_PART_NUMBER_FS32K144HAT0MMHT + bool + +config SOC_PART_NUMBER_FS32K144HVT0VLHR + bool + +config SOC_PART_NUMBER_FS32K144HVT0VLHT + bool + +config SOC_PART_NUMBER_FS32K144HXT0VLHT + bool + +config SOC_PART_NUMBER_FS32K144HXT0VLLT + bool + +config SOC_PART_NUMBER_FS32K144UAT0VLFT + bool + +config SOC_PART_NUMBER_FS32K144UAT0VLHR + bool + +config SOC_PART_NUMBER_FS32K144UAT0VLHT + bool + +config SOC_PART_NUMBER_FS32K144UAT0VLLT + bool + +config SOC_PART_NUMBER_FS32K144UAT0VMHR + bool + +config SOC_PART_NUMBER_FS32K144UAT0VMHT + bool + +config SOC_PART_NUMBER_FS32K144UIT0VLHT + bool + +config SOC_PART_NUMBER_FS32K144ULT0VLHT + bool + +config SOC_PART_NUMBER_FS32K144ULT0VLLR + bool + +config SOC_PART_NUMBER_FS32K144ULT0VLLT + bool + +config SOC_PART_NUMBER_FS32K144WAT0WLFT + bool + +config SOC_PART_NUMBER_FS32K144WAT0WLHT + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLHR + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLHT + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLLR + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLLT + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLQR + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLQT + bool + +config SOC_PART_NUMBER_FS32K146HAT0MMHR + bool + +config SOC_PART_NUMBER_FS32K146HAT0MMHT + bool + +config SOC_PART_NUMBER_FS32K146HVT0VLHT + bool + +config SOC_PART_NUMBER_FS32K146HXT0VLLT + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLHR + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLHT + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLLR + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLLT + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLQR + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLQT + bool + +config SOC_PART_NUMBER_FS32K146UAT0VMHR + bool + +config SOC_PART_NUMBER_FS32K146UAT0VMHT + bool + +config SOC_PART_NUMBER_FS32K146UIT0VLLT + bool + +config SOC_PART_NUMBER_FS32K146ULT0VLLT + bool + +config SOC_PART_NUMBER_FS32K148HAT0MLLR + bool + +config SOC_PART_NUMBER_FS32K148HAT0MLLT + bool + +config SOC_PART_NUMBER_FS32K148HAT0MLQR + bool + +config SOC_PART_NUMBER_FS32K148HAT0MLQT + bool + +config SOC_PART_NUMBER_FS32K148HAT0MLUT + bool + +config SOC_PART_NUMBER_FS32K148HAT0MMHT + bool + +config SOC_PART_NUMBER_FS32K148UGT0VLQT + bool + +config SOC_PART_NUMBER_FS32K148UIT0VLQT + bool + +config SOC_PART_NUMBER_FS32K148UJT0VLLT + bool + +config SOC_PART_NUMBER_FS32K148UJT0VLQT + bool + +config SOC_PART_NUMBER_FS32K148UJT0VLUT + bool + +config SOC_PART_NUMBER_FS32K148UJT0VMHR + bool + +config SOC_PART_NUMBER_FS32K148UJT0VMHT + bool + +config SOC_PART_NUMBER + default "FS32K116LAT0MFMT" if SOC_PART_NUMBER_FS32K116LAT0MFMT + default "FS32K116LAT0MLFR" if SOC_PART_NUMBER_FS32K116LAT0MLFR + default "FS32K116LAT0MLFT" if SOC_PART_NUMBER_FS32K116LAT0MLFT + default "FS32K116LIT0VFMT" if SOC_PART_NUMBER_FS32K116LIT0VFMT + default "FS32K116LIT0VLFT" if SOC_PART_NUMBER_FS32K116LIT0VLFT + default "FS32K118LAT0MLFR" if SOC_PART_NUMBER_FS32K118LAT0MLFR + default "FS32K118LAT0MLFT" if SOC_PART_NUMBER_FS32K118LAT0MLFT + default "FS32K118LAT0MLHR" if SOC_PART_NUMBER_FS32K118LAT0MLHR + default "FS32K118LAT0MLHT" if SOC_PART_NUMBER_FS32K118LAT0MLHT + default "FS32K118LIT0VLFT" if SOC_PART_NUMBER_FS32K118LIT0VLFT + default "FS32K142HAT0MLFT" if SOC_PART_NUMBER_FS32K142HAT0MLFT + default "FS32K142HAT0MLHT" if SOC_PART_NUMBER_FS32K142HAT0MLHT + default "FS32K142HAT0MLLR" if SOC_PART_NUMBER_FS32K142HAT0MLLR + default "FS32K142HAT0MLLT" if SOC_PART_NUMBER_FS32K142HAT0MLLT + default "FS32K142HVT0VLHT" if SOC_PART_NUMBER_FS32K142HVT0VLHT + default "FS32K142UAT0VLFT" if SOC_PART_NUMBER_FS32K142UAT0VLFT + default "FS32K142UAT0VLHR" if SOC_PART_NUMBER_FS32K142UAT0VLHR + default "FS32K142UAT0VLHT" if SOC_PART_NUMBER_FS32K142UAT0VLHT + default "FS32K142UAT0VLLR" if SOC_PART_NUMBER_FS32K142UAT0VLLR + default "FS32K142UAT0VLLT" if SOC_PART_NUMBER_FS32K142UAT0VLLT + default "FS32K142UIT0VLHT" if SOC_PART_NUMBER_FS32K142UIT0VLHT + default "FS32K142WAT0WLFT" if SOC_PART_NUMBER_FS32K142WAT0WLFT + default "FS32K142WAT0WLHT" if SOC_PART_NUMBER_FS32K142WAT0WLHT + default "FS32K144HAT0MLFT" if SOC_PART_NUMBER_FS32K144HAT0MLFT + default "FS32K144HAT0MLHR" if SOC_PART_NUMBER_FS32K144HAT0MLHR + default "FS32K144HAT0MLHT" if SOC_PART_NUMBER_FS32K144HAT0MLHT + default "FS32K144HAT0MLLR" if SOC_PART_NUMBER_FS32K144HAT0MLLR + default "FS32K144HAT0MLLT" if SOC_PART_NUMBER_FS32K144HAT0MLLT + default "FS32K144HAT0MMHR" if SOC_PART_NUMBER_FS32K144HAT0MMHR + default "FS32K144HAT0MMHT" if SOC_PART_NUMBER_FS32K144HAT0MMHT + default "FS32K144HVT0VLHR" if SOC_PART_NUMBER_FS32K144HVT0VLHR + default "FS32K144HVT0VLHT" if SOC_PART_NUMBER_FS32K144HVT0VLHT + default "FS32K144HXT0VLHT" if SOC_PART_NUMBER_FS32K144HXT0VLHT + default "FS32K144HXT0VLLT" if SOC_PART_NUMBER_FS32K144HXT0VLLT + default "FS32K144UAT0VLFT" if SOC_PART_NUMBER_FS32K144UAT0VLFT + default "FS32K144UAT0VLHR" if SOC_PART_NUMBER_FS32K144UAT0VLHR + default "FS32K144UAT0VLHT" if SOC_PART_NUMBER_FS32K144UAT0VLHT + default "FS32K144UAT0VLLT" if SOC_PART_NUMBER_FS32K144UAT0VLLT + default "FS32K144UAT0VMHR" if SOC_PART_NUMBER_FS32K144UAT0VMHR + default "FS32K144UAT0VMHT" if SOC_PART_NUMBER_FS32K144UAT0VMHT + default "FS32K144UIT0VLHT" if SOC_PART_NUMBER_FS32K144UIT0VLHT + default "FS32K144ULT0VLHT" if SOC_PART_NUMBER_FS32K144ULT0VLHT + default "FS32K144ULT0VLLR" if SOC_PART_NUMBER_FS32K144ULT0VLLR + default "FS32K144ULT0VLLT" if SOC_PART_NUMBER_FS32K144ULT0VLLT + default "FS32K144WAT0WLFT" if SOC_PART_NUMBER_FS32K144WAT0WLFT + default "FS32K144WAT0WLHT" if SOC_PART_NUMBER_FS32K144WAT0WLHT + default "FS32K146HAT0MLHR" if SOC_PART_NUMBER_FS32K146HAT0MLHR + default "FS32K146HAT0MLHT" if SOC_PART_NUMBER_FS32K146HAT0MLHT + default "FS32K146HAT0MLLR" if SOC_PART_NUMBER_FS32K146HAT0MLLR + default "FS32K146HAT0MLLT" if SOC_PART_NUMBER_FS32K146HAT0MLLT + default "FS32K146HAT0MLQR" if SOC_PART_NUMBER_FS32K146HAT0MLQR + default "FS32K146HAT0MLQT" if SOC_PART_NUMBER_FS32K146HAT0MLQT + default "FS32K146HAT0MMHR" if SOC_PART_NUMBER_FS32K146HAT0MMHR + default "FS32K146HAT0MMHT" if SOC_PART_NUMBER_FS32K146HAT0MMHT + default "FS32K146HVT0VLHT" if SOC_PART_NUMBER_FS32K146HVT0VLHT + default "FS32K146HXT0VLLT" if SOC_PART_NUMBER_FS32K146HXT0VLLT + default "FS32K146UAT0VLHR" if SOC_PART_NUMBER_FS32K146UAT0VLHR + default "FS32K146UAT0VLHT" if SOC_PART_NUMBER_FS32K146UAT0VLHT + default "FS32K146UAT0VLLR" if SOC_PART_NUMBER_FS32K146UAT0VLLR + default "FS32K146UAT0VLLT" if SOC_PART_NUMBER_FS32K146UAT0VLLT + default "FS32K146UAT0VLQR" if SOC_PART_NUMBER_FS32K146UAT0VLQR + default "FS32K146UAT0VLQT" if SOC_PART_NUMBER_FS32K146UAT0VLQT + default "FS32K146UAT0VMHR" if SOC_PART_NUMBER_FS32K146UAT0VMHR + default "FS32K146UAT0VMHT" if SOC_PART_NUMBER_FS32K146UAT0VMHT + default "FS32K146UIT0VLLT" if SOC_PART_NUMBER_FS32K146UIT0VLLT + default "FS32K146ULT0VLLT" if SOC_PART_NUMBER_FS32K146ULT0VLLT + default "FS32K148HAT0MLLR" if SOC_PART_NUMBER_FS32K148HAT0MLLR + default "FS32K148HAT0MLLT" if SOC_PART_NUMBER_FS32K148HAT0MLLT + default "FS32K148HAT0MLQR" if SOC_PART_NUMBER_FS32K148HAT0MLQR + default "FS32K148HAT0MLQT" if SOC_PART_NUMBER_FS32K148HAT0MLQT + default "FS32K148HAT0MLUT" if SOC_PART_NUMBER_FS32K148HAT0MLUT + default "FS32K148HAT0MMHT" if SOC_PART_NUMBER_FS32K148HAT0MMHT + default "FS32K148UGT0VLQT" if SOC_PART_NUMBER_FS32K148UGT0VLQT + default "FS32K148UIT0VLQT" if SOC_PART_NUMBER_FS32K148UIT0VLQT + default "FS32K148UJT0VLLT" if SOC_PART_NUMBER_FS32K148UJT0VLLT + default "FS32K148UJT0VLQT" if SOC_PART_NUMBER_FS32K148UJT0VLQT + default "FS32K148UJT0VLUT" if SOC_PART_NUMBER_FS32K148UJT0VLUT + default "FS32K148UJT0VMHR" if SOC_PART_NUMBER_FS32K148UJT0VMHR + default "FS32K148UJT0VMHT" if SOC_PART_NUMBER_FS32K148UJT0VMHT diff --git a/soc/arm/nxp_s32/s32k1/flash_config.ld b/soc/nxp/s32/s32k1/flash_config.ld similarity index 100% rename from soc/arm/nxp_s32/s32k1/flash_config.ld rename to soc/nxp/s32/s32k1/flash_config.ld diff --git a/soc/arm/nxp_s32/s32k1/flash_configuration.c b/soc/nxp/s32/s32k1/flash_configuration.c similarity index 100% rename from soc/arm/nxp_s32/s32k1/flash_configuration.c rename to soc/nxp/s32/s32k1/flash_configuration.c diff --git a/soc/arm/nxp_s32/s32k1/nxp_mpu_regions.c b/soc/nxp/s32/s32k1/nxp_mpu_regions.c similarity index 94% rename from soc/arm/nxp_s32/s32k1/nxp_mpu_regions.c rename to soc/nxp/s32/s32k1/nxp_mpu_regions.c index 5c8ac8de3b9..fb66036dfc7 100644 --- a/soc/arm/nxp_s32/s32k1/nxp_mpu_regions.c +++ b/soc/nxp/s32/s32k1/nxp_mpu_regions.c @@ -1,7 +1,7 @@ /* * Copyright 2023 NXP * - * Based on soc/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c, which is: + * Based on soc/soc_legacy/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c, which is: * Copyright (c) 2017 Linaro Limited. * * SPDX-License-Identifier: Apache-2.0 diff --git a/soc/arm/nxp_s32/s32k1/pinctrl_soc.h b/soc/nxp/s32/s32k1/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_s32/s32k1/pinctrl_soc.h rename to soc/nxp/s32/s32k1/pinctrl_soc.h diff --git a/soc/nxp/s32/s32k1/soc.c b/soc/nxp/s32/s32k1/soc.c new file mode 100644 index 00000000000..20a27eb13c0 --- /dev/null +++ b/soc/nxp/s32/s32k1/soc.c @@ -0,0 +1,78 @@ +/* + * Copyright 2023 NXP + * + * Based on zephyr/soc/soc_legacy/arm/nxp_kinetis/ke1xf/soc.c, which is: + * Copyright (c) 2019-2021 Vestas Wind Systems A/S + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include +#include + +#if defined(CONFIG_HAS_MCUX_CACHE) +#include +#endif + +#if defined(CONFIG_WDOG_INIT) +void z_arm_watchdog_init(void) +{ + /* + * NOTE: DO NOT SINGLE STEP THROUGH THIS SECTION!!! Watchdog + * reconfiguration must take place within 128 bus clocks from + * unlocking. Single stepping through the code will cause the + * watchdog to close the unlock window again. + */ + if ((IP_WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U) { + IP_WDOG->CNT = WDOG_UPDATE_KEY; + } else { + IP_WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU; + IP_WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU; + } + while (!(IP_WDOG->CS & WDOG_CS_ULK_MASK)) { + ; + } + + IP_WDOG->TOVAL = 0xFFFFU; + IP_WDOG->CS = (uint32_t) ((IP_WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; + + /* Wait for new configuration to take effect */ + while (!(IP_WDOG->CS & WDOG_CS_RCS_MASK)) { + ; + } +} +#endif /* CONFIG_WDOG_INIT */ + +static int soc_init(void) +{ +#if !defined(CONFIG_ARM_MPU) + uint32_t tmp; + + /* + * Disable memory protection and clear slave port errors. + * Note that the S32K1xx does not implement the optional Arm MPU but + * instead the Soc includes its own NXP MPU module. + */ + tmp = IP_MPU->CESR; + tmp &= ~MPU_CESR_VLD_MASK; + tmp |= MPU_CESR_SPERR0_MASK | MPU_CESR_SPERR1_MASK + | MPU_CESR_SPERR2_MASK | MPU_CESR_SPERR3_MASK; + IP_MPU->CESR = tmp; +#endif /* !CONFIG_ARM_MPU */ + +#if defined(CONFIG_HAS_MCUX_CACHE) && defined(CONFIG_NXP_S32_ENABLE_CODE_CACHE) + L1CACHE_EnableCodeCache(); + barrier_isync_fence_full(); +#endif + + OsIf_Init(NULL); + + return 0; +} + +SYS_INIT(soc_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_s32/s32k1/soc.h b/soc/nxp/s32/s32k1/soc.h similarity index 100% rename from soc/arm/nxp_s32/s32k1/soc.h rename to soc/nxp/s32/s32k1/soc.h diff --git a/soc/nxp/s32/s32k3/CMakeLists.txt b/soc/nxp/s32/s32k3/CMakeLists.txt new file mode 100644 index 00000000000..4d18223a61c --- /dev/null +++ b/soc/nxp/s32/s32k3/CMakeLists.txt @@ -0,0 +1,13 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_include_directories(.) + +zephyr_library_sources(soc.c) +zephyr_library_sources_ifdef(CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS mpu_regions.c) +zephyr_linker_sources(SECTIONS sections.ld) +zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT s32k3xx_startup.S) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/s32/s32k3/Kconfig b/soc/nxp/s32/s32k3/Kconfig new file mode 100644 index 00000000000..0ca5882062c --- /dev/null +++ b/soc/nxp/s32/s32k3/Kconfig @@ -0,0 +1,60 @@ +# NXP S32K3XX MCU series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32K3 + select ARM + select CPU_CORTEX_M7 + select HAS_NXP_S32_HAL + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select PLATFORM_SPECIFIC_INIT if XIP + select USE_DT_CODE_PARTITION if XIP + select CLOCK_CONTROL + select HAS_MCUX + select HAS_MCUX_LPUART + select HAS_MCUX_FLEXCAN + select HAS_MCUX_LPI2C + select HAS_MCUX_LPSPI + select HAS_MCUX_CACHE + +if SOC_SERIES_S32K3 + +config IVT_HEADER_OFFSET + hex + depends on XIP + default $(dt_node_reg_addr_hex,$(dt_nodelabel_path,ivt_header)) + help + The offset address from flash base address for ivt header + +config IVT_HEADER_SIZE + hex + depends on XIP + default $(dt_node_reg_size_hex,$(dt_nodelabel_path,ivt_header)) + help + Size of ivt header region + +config NXP_S32_PMC_LMEN + bool "Last Mile regulator" + default y if CLOCK_CONTROL + help + Enables the Last Mile regulator, which regulates an external 1.5V + voltage on V15 down to the core and logic supply (V11 power domain), + which is typically 1.1V. + When enabling PLL as system clock, the PMC last mile regulator should + be enabled. + +config NXP_S32_PMC_LMBCTLEN + bool "External BCTL regulator for V15" + depends on NXP_S32_PMC_LMEN + help + This option must be selected if an external BJT between VDD_HV_A and + V15 is used on the PCB. The base of this BJT must be connected to the + VRC_CTRL pin and is controlled by the PMC to regulate a voltage of + 1.5V on V15 pin. + +endif # SOC_SERIES_S32K3 diff --git a/soc/nxp/s32/s32k3/Kconfig.defconfig b/soc/nxp/s32/s32k3/Kconfig.defconfig new file mode 100644 index 00000000000..6c58f348ea6 --- /dev/null +++ b/soc/nxp/s32/s32k3/Kconfig.defconfig @@ -0,0 +1,38 @@ +# NXP S32K3XX MCU series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_S32K3 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 2000000 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 239 + +config FPU + default y + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +if NET_L2_ETHERNET + +config NET_TCP_CHECKSUM + default n + +config NET_UDP_CHECKSUM + default n + +endif # NET_L2_ETHERNET + +config CACHE_MANAGEMENT + default y + +endif # SOC_SERIES_S32K3 diff --git a/soc/nxp/s32/s32k3/Kconfig.soc b/soc/nxp/s32/s32k3/Kconfig.soc new file mode 100644 index 00000000000..164edf56231 --- /dev/null +++ b/soc/nxp/s32/s32k3/Kconfig.soc @@ -0,0 +1,24 @@ +# NXP S32K3XX MCU series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32K3 + bool + select SOC_FAMILY_NXP_S32 + +config SOC_SERIES + default "s32k3" if SOC_SERIES_S32K3 + +config SOC_S32K344 + bool + select SOC_SERIES_S32K3 + +config SOC + default "s32k344" if SOC_S32K344 + +config SOC_PART_NUMBER_PS32K344EHVPBS + bool + +config SOC_PART_NUMBER + default "PS32K344EHVPBS" if SOC_PART_NUMBER_PS32K344EHVPBS diff --git a/soc/arm/nxp_s32/s32k3/linker.ld b/soc/nxp/s32/s32k3/linker.ld similarity index 100% rename from soc/arm/nxp_s32/s32k3/linker.ld rename to soc/nxp/s32/s32k3/linker.ld diff --git a/soc/arm/nxp_s32/s32k3/mpu_regions.c b/soc/nxp/s32/s32k3/mpu_regions.c similarity index 100% rename from soc/arm/nxp_s32/s32k3/mpu_regions.c rename to soc/nxp/s32/s32k3/mpu_regions.c diff --git a/soc/arm/nxp_s32/s32k3/s32k3xx_startup.S b/soc/nxp/s32/s32k3/s32k3xx_startup.S similarity index 100% rename from soc/arm/nxp_s32/s32k3/s32k3xx_startup.S rename to soc/nxp/s32/s32k3/s32k3xx_startup.S diff --git a/soc/arm/nxp_s32/s32k3/sections.ld b/soc/nxp/s32/s32k3/sections.ld similarity index 100% rename from soc/arm/nxp_s32/s32k3/sections.ld rename to soc/nxp/s32/s32k3/sections.ld diff --git a/soc/arm/nxp_s32/s32k3/soc.c b/soc/nxp/s32/s32k3/soc.c similarity index 100% rename from soc/arm/nxp_s32/s32k3/soc.c rename to soc/nxp/s32/s32k3/soc.c diff --git a/soc/arm/nxp_s32/s32k3/soc.h b/soc/nxp/s32/s32k3/soc.h similarity index 100% rename from soc/arm/nxp_s32/s32k3/soc.h rename to soc/nxp/s32/s32k3/soc.h diff --git a/soc/nxp/s32/s32ze/CMakeLists.txt b/soc/nxp/s32/s32ze/CMakeLists.txt new file mode 100644 index 00000000000..b7ce37a2f00 --- /dev/null +++ b/soc/nxp/s32/s32ze/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library_sources( + soc.c +) + +zephyr_library_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/s32/s32ze/Kconfig b/soc/nxp/s32/s32ze/Kconfig new file mode 100644 index 00000000000..5adac36dce4 --- /dev/null +++ b/soc/nxp/s32/s32ze/Kconfig @@ -0,0 +1,30 @@ +# NXP S32ZE MCUs series + +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32ZE + select ARM + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select CPU_CORTEX_R52 + select CPU_HAS_DCLS + select CPU_HAS_ARM_MPU + select GIC_SINGLE_SECURITY_STATE + select VFP_DP_D16 + select PLATFORM_SPECIFIC_INIT + select CLOCK_CONTROL + select HAS_NXP_S32_HAL + select HAS_MCUX + select HAS_MCUX_PIT + +if SOC_SERIES_S32ZE + +config NXP_S32_RTU_INDEX + int + range 0 1 + default 0 if SOC_S32Z270_RTU0 + default 1 if SOC_S32Z270_RTU1 + help + This option indicates the index of the target RTU (Real-Time Unit) subsystem. + +endif # SOC_SERIES_S32ZE diff --git a/soc/nxp/s32/s32ze/Kconfig.defconfig b/soc/nxp/s32/s32ze/Kconfig.defconfig new file mode 100644 index 00000000000..7deb599e3a2 --- /dev/null +++ b/soc/nxp/s32/s32ze/Kconfig.defconfig @@ -0,0 +1,40 @@ +# NXP S32ZE MCUs series + +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_S32ZE + +config NUM_IRQS + # must be >= the highest interrupt number used + default 991 + +config FPU + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 2000000 + +config MAIN_STACK_SIZE + default 1024 + +if !XIP +config FLASH_SIZE + default 0 + +config FLASH_BASE_ADDRESS + default 0 +endif # !XIP + +if NET_L2_ETHERNET + +# NETC drops TCP/UDP packets with invalid checksum +config NET_TCP_CHECKSUM + default n + +config NET_UDP_CHECKSUM + default n + +endif # NET_L2_ETHERNET + +endif # SOC_SERIES_S32ZE diff --git a/soc/nxp/s32/s32ze/Kconfig.soc b/soc/nxp/s32/s32ze/Kconfig.soc new file mode 100644 index 00000000000..8578508ddb1 --- /dev/null +++ b/soc/nxp/s32/s32ze/Kconfig.soc @@ -0,0 +1,32 @@ +# NXP S32ZE MCUs series + +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32ZE + bool + select SOC_FAMILY_NXP_S32 + +config SOC_SERIES + default "s32ze" if SOC_SERIES_S32ZE + +config SOC_S32Z270 + bool + select SOC_SERIES_S32ZE + +config SOC_S32Z270_RTU0 + bool + select SOC_S32Z270 + +config SOC_S32Z270_RTU1 + bool + select SOC_S32Z270 + +config SOC + default "s32z270" if SOC_S32Z270 + +config SOC_PART_NUMBER_P32Z270ADCK0MJFT + bool + +config SOC_PART_NUMBER + default "P32Z270ADCK0MJFT" if SOC_PART_NUMBER_P32Z270ADCK0MJFT diff --git a/soc/arm/nxp_s32/s32ze/mpu_regions.c b/soc/nxp/s32/s32ze/mpu_regions.c similarity index 100% rename from soc/arm/nxp_s32/s32ze/mpu_regions.c rename to soc/nxp/s32/s32ze/mpu_regions.c diff --git a/soc/arm/nxp_s32/s32ze/soc.c b/soc/nxp/s32/s32ze/soc.c similarity index 100% rename from soc/arm/nxp_s32/s32ze/soc.c rename to soc/nxp/s32/s32ze/soc.c diff --git a/soc/nxp/s32/s32ze/soc.h b/soc/nxp/s32/s32ze/soc.h new file mode 100644 index 00000000000..57e8fb0b8b8 --- /dev/null +++ b/soc/nxp/s32/s32ze/soc.h @@ -0,0 +1,74 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _NXP_S32_S32ZE_SOC_H_ +#define _NXP_S32_S32ZE_SOC_H_ + +/* Do not let CMSIS to handle GIC */ +#define __GIC_PRESENT 0 + +#if defined(CONFIG_SOC_S32Z270) +#include +#else +#error "SoC not supported" +#endif + +#if defined(CONFIG_CMSIS_RTOS_V2) +#include +#endif + +/* Aliases for peripheral base addresses */ + +/* SIUL2 */ +#define IP_SIUL2_2_BASE 0U /* instance does not exist on this SoC */ + +/* LINFlexD*/ +#define IP_LINFLEX_12_BASE IP_MSC_0_LIN_BASE + +/* SWT */ +#define IP_SWT_0_BASE IP_CE_SWT_0_BASE +#define IP_SWT_1_BASE IP_CE_SWT_1_BASE +#define IP_SWT_2_BASE IP_RTU0__SWT_0_BASE +#define IP_SWT_3_BASE IP_RTU0__SWT_1_BASE +#define IP_SWT_4_BASE IP_RTU0__SWT_2_BASE +#define IP_SWT_5_BASE IP_RTU0__SWT_3_BASE +#define IP_SWT_6_BASE IP_RTU0__SWT_4_BASE +#define IP_SWT_7_BASE IP_RTU1__SWT_0_BASE +#define IP_SWT_8_BASE IP_RTU1__SWT_1_BASE +#define IP_SWT_9_BASE IP_RTU1__SWT_2_BASE +#define IP_SWT_10_BASE IP_RTU1__SWT_3_BASE +#define IP_SWT_11_BASE IP_RTU1__SWT_4_BASE +#define IP_SWT_12_BASE IP_SMU__SWT_BASE + +/* STM */ +#define IP_STM_0_BASE IP_CE_STM_0_BASE +#define IP_STM_1_BASE IP_CE_STM_1_BASE +#define IP_STM_2_BASE IP_CE_STM_2_BASE +#define IP_STM_3_BASE IP_RTU0__STM_0_BASE +#define IP_STM_4_BASE IP_RTU0__STM_1_BASE +#define IP_STM_5_BASE IP_RTU0__STM_2_BASE +#define IP_STM_6_BASE IP_RTU0__STM_3_BASE +#define IP_STM_7_BASE IP_RTU1__STM_0_BASE +#define IP_STM_8_BASE IP_RTU1__STM_1_BASE +#define IP_STM_9_BASE IP_RTU1__STM_2_BASE +#define IP_STM_10_BASE IP_RTU1__STM_3_BASE +#define IP_STM_11_BASE IP_SMU__STM_0_BASE +#define IP_STM_12_BASE IP_SMU__STM_2_BASE + +/* NETC */ +#define IP_NETC_EMDIO_0_BASE IP_NETC__EMDIO_BASE_BASE + +/* MRU */ +#define IP_MRU_0_BASE IP_RTU0__MRU_0_BASE +#define IP_MRU_1_BASE IP_RTU0__MRU_1_BASE +#define IP_MRU_2_BASE IP_RTU0__MRU_2_BASE +#define IP_MRU_3_BASE IP_RTU0__MRU_3_BASE +#define IP_MRU_4_BASE IP_RTU1__MRU_0_BASE +#define IP_MRU_5_BASE IP_RTU1__MRU_1_BASE +#define IP_MRU_6_BASE IP_RTU1__MRU_2_BASE +#define IP_MRU_7_BASE IP_RTU1__MRU_3_BASE + +#endif /* _NXP_S32_S32ZE_SOC_H_ */ diff --git a/soc/nxp/s32/soc.yml b/soc/nxp/s32/soc.yml new file mode 100644 index 00000000000..8d71e2b53aa --- /dev/null +++ b/soc/nxp/s32/soc.yml @@ -0,0 +1,22 @@ +family: +- name: nxp_s32 + series: + - name: s32k1 + socs: + - name: s32k116 + - name: s32k118 + - name: s32k142 + - name: s32k142w + - name: s32k144 + - name: s32k144w + - name: s32k146 + - name: s32k148 + - name: s32k3 + socs: + - name: s32k344 + - name: s32ze + socs: + - name: s32z270 + cpuclusters: + - name: rtu0 + - name: rtu1 diff --git a/soc/openisa/rv32m1/CMakeLists.txt b/soc/openisa/rv32m1/CMakeLists.txt new file mode 100644 index 00000000000..cd65ea9d628 --- /dev/null +++ b/soc/openisa/rv32m1/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2018 Foundries.io Ltd +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_OPENISA_RV32M1_RI5CY) + if (CONFIG_RISCV_GENERIC_TOOLCHAIN) + zephyr_compile_options(-march=rv32imc_zicsr_zifencei) + else() + zephyr_compile_options(-march=rv32imcxpulpv2) + endif() +elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY) + zephyr_compile_options(-march=rv32imc_zicsr_zifencei) +endif() + +zephyr_sources( + vector.S + soc_irq.S + wdog.S + soc.c +) + +zephyr_include_directories(.) + +zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/openisa/rv32m1/Kconfig b/soc/openisa/rv32m1/Kconfig new file mode 100644 index 00000000000..21fe5d9297d --- /dev/null +++ b/soc/openisa/rv32m1/Kconfig @@ -0,0 +1,22 @@ +# Copyright (c) 2018 Foundries.io Ltd +# SPDX-License-Identifier: Apache-2.0 + +config SOC_OPENISA_RV32M1 + select RISCV + select XIP + select HAS_RV32M1_LPUART + select HAS_RV32M1_LPI2C + select HAS_RV32M1_LPSPI + select HAS_RV32M1_TPM + select ATOMIC_OPERATIONS_C + select VEGA_SDK_HAL + select RISCV_SOC_INTERRUPT_INIT + select CLOCK_CONTROL + select HAS_RV32M1_FTFX + select HAS_FLASH_LOAD_OFFSET + select BUILD_OUTPUT_HEX + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/openisa/rv32m1/Kconfig.defconfig b/soc/openisa/rv32m1/Kconfig.defconfig new file mode 100644 index 00000000000..10d6bca39d5 --- /dev/null +++ b/soc/openisa/rv32m1/Kconfig.defconfig @@ -0,0 +1,122 @@ +# RV32M1 SoC RISC-V core default configuration values + +# Copyright (c) 2018 Foundries.io Ltd +# SPDX-License-Identifier: Apache-2.0 + +if SOC_OPENISA_RV32M1 + +# 32 from event unit + 32 * (1 + max enabled INTMUX channel) +config NUM_IRQS + default 288 if RV32M1_INTMUX_CHANNEL_7 + default 256 if RV32M1_INTMUX_CHANNEL_6 + default 224 if RV32M1_INTMUX_CHANNEL_5 + default 192 if RV32M1_INTMUX_CHANNEL_4 + default 160 if RV32M1_INTMUX_CHANNEL_3 + default 128 if RV32M1_INTMUX_CHANNEL_2 + default 96 if RV32M1_INTMUX_CHANNEL_1 + default 64 if RV32M1_INTMUX_CHANNEL_0 + default 32 + +config RISCV_GENERIC_TOOLCHAIN + default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" + default n + +config RISCV_SOC_CONTEXT_SAVE + default y if SOC_OPENISA_RV32M1_RI5CY + +config RISCV_SOC_OFFSETS + default y + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_MCAUSE_EXCEPTION_MASK + default 0x1F + +# We need to disable the watchdog out of reset, as it's enabled by +# default. Use the WDOG_INIT hook for doing that. +config WDOG_INIT + def_bool y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 8000000 + +if MULTI_LEVEL_INTERRUPTS + +config MAX_IRQ_PER_AGGREGATOR + default 32 + +config 2ND_LEVEL_INTERRUPTS + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 32 + +config NUM_2ND_LEVEL_AGGREGATORS + default 8 if RV32M1_INTMUX_CHANNEL_7 + default 7 if RV32M1_INTMUX_CHANNEL_6 + default 6 if RV32M1_INTMUX_CHANNEL_5 + default 5 if RV32M1_INTMUX_CHANNEL_4 + default 4 if RV32M1_INTMUX_CHANNEL_3 + default 3 if RV32M1_INTMUX_CHANNEL_2 + default 2 if RV32M1_INTMUX_CHANNEL_1 + default 1 # just channel 0 + +config 2ND_LVL_INTR_00_OFFSET + default 24 + +config 2ND_LVL_INTR_01_OFFSET + int + default 25 + +config 2ND_LVL_INTR_02_OFFSET + int + default 26 + +config 2ND_LVL_INTR_03_OFFSET + int + default 27 + +config 2ND_LVL_INTR_04_OFFSET + int + default 28 + +config 2ND_LVL_INTR_05_OFFSET + int + default 29 + +config 2ND_LVL_INTR_06_OFFSET + int + default 30 + +config 2ND_LVL_INTR_07_OFFSET + int + default 31 + +config RV32M1_INTMUX_CHANNEL_0 + default y + +config RV32M1_INTMUX_CHANNEL_1 + default y + +config RV32M1_INTMUX_CHANNEL_2 + default y + +config RV32M1_INTMUX_CHANNEL_3 + default y + +config RV32M1_INTMUX_CHANNEL_4 + default y + +config RV32M1_INTMUX_CHANNEL_5 + default y + +config RV32M1_INTMUX_CHANNEL_6 + default y + +config RV32M1_INTMUX_CHANNEL_7 + default y + +endif # MULTI_LEVEL_INTERRUPTS + +endif # SOC_OPENISA_RV32M1 diff --git a/soc/openisa/rv32m1/Kconfig.soc b/soc/openisa/rv32m1/Kconfig.soc new file mode 100644 index 00000000000..0144d82b011 --- /dev/null +++ b/soc/openisa/rv32m1/Kconfig.soc @@ -0,0 +1,24 @@ +# Copyright (c) 2018 Foundries.io Ltd +# SPDX-License-Identifier: Apache-2.0 + +config SOC_OPENISA_RV32M1 + bool + help + Enable support for OpenISA RV32M1 RISC-V processors. Choose + this option to target the RI5CY or ZERO-RISCY core. This + option should not be used to target either Arm core. + +config SOC_OPENISA_RV32M1_RI5CY + bool + select SOC_OPENISA_RV32M1 + help + OpenISA RV32M1 RI5CY core + +config SOC_OPENISA_RV32M1_ZERO_RISCY + bool + select SOC_OPENISA_RV32M1 + help + OpenISA RV32M1 ZERO-RISCY core + +config SOC + default "openisa_rv32m1" if SOC_OPENISA_RV32M1 diff --git a/soc/riscv/openisa_rv32m1/linker.ld b/soc/openisa/rv32m1/linker.ld similarity index 100% rename from soc/riscv/openisa_rv32m1/linker.ld rename to soc/openisa/rv32m1/linker.ld diff --git a/soc/riscv/openisa_rv32m1/pinctrl_soc.h b/soc/openisa/rv32m1/pinctrl_soc.h similarity index 100% rename from soc/riscv/openisa_rv32m1/pinctrl_soc.h rename to soc/openisa/rv32m1/pinctrl_soc.h diff --git a/soc/riscv/openisa_rv32m1/soc.c b/soc/openisa/rv32m1/soc.c similarity index 100% rename from soc/riscv/openisa_rv32m1/soc.c rename to soc/openisa/rv32m1/soc.c diff --git a/soc/riscv/openisa_rv32m1/soc.h b/soc/openisa/rv32m1/soc.h similarity index 100% rename from soc/riscv/openisa_rv32m1/soc.h rename to soc/openisa/rv32m1/soc.h diff --git a/soc/openisa/rv32m1/soc.yml b/soc/openisa/rv32m1/soc.yml new file mode 100644 index 00000000000..135006f7eb9 --- /dev/null +++ b/soc/openisa/rv32m1/soc.yml @@ -0,0 +1,5 @@ +socs: +- name: openisa_rv32m1 + cpuclusters: + - name: zero_riscy + - name: ri5cy diff --git a/soc/riscv/openisa_rv32m1/soc_context.h b/soc/openisa/rv32m1/soc_context.h similarity index 100% rename from soc/riscv/openisa_rv32m1/soc_context.h rename to soc/openisa/rv32m1/soc_context.h diff --git a/soc/riscv/openisa_rv32m1/soc_irq.S b/soc/openisa/rv32m1/soc_irq.S similarity index 100% rename from soc/riscv/openisa_rv32m1/soc_irq.S rename to soc/openisa/rv32m1/soc_irq.S diff --git a/soc/riscv/openisa_rv32m1/soc_offsets.h b/soc/openisa/rv32m1/soc_offsets.h similarity index 100% rename from soc/riscv/openisa_rv32m1/soc_offsets.h rename to soc/openisa/rv32m1/soc_offsets.h diff --git a/soc/riscv/openisa_rv32m1/soc_ri5cy.h b/soc/openisa/rv32m1/soc_ri5cy.h similarity index 100% rename from soc/riscv/openisa_rv32m1/soc_ri5cy.h rename to soc/openisa/rv32m1/soc_ri5cy.h diff --git a/soc/riscv/openisa_rv32m1/soc_zero_riscy.h b/soc/openisa/rv32m1/soc_zero_riscy.h similarity index 100% rename from soc/riscv/openisa_rv32m1/soc_zero_riscy.h rename to soc/openisa/rv32m1/soc_zero_riscy.h diff --git a/soc/riscv/openisa_rv32m1/vector.S b/soc/openisa/rv32m1/vector.S similarity index 100% rename from soc/riscv/openisa_rv32m1/vector.S rename to soc/openisa/rv32m1/vector.S diff --git a/soc/riscv/openisa_rv32m1/vector_table.ld b/soc/openisa/rv32m1/vector_table.ld similarity index 100% rename from soc/riscv/openisa_rv32m1/vector_table.ld rename to soc/openisa/rv32m1/vector_table.ld diff --git a/soc/riscv/openisa_rv32m1/wdog.S b/soc/openisa/rv32m1/wdog.S similarity index 100% rename from soc/riscv/openisa_rv32m1/wdog.S rename to soc/openisa/rv32m1/wdog.S diff --git a/soc/posix/CMakeLists.txt b/soc/posix/CMakeLists.txt deleted file mode 100644 index b42e9be8863..00000000000 --- a/soc/posix/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) -else() - add_subdirectory(${SOC_NAME}) -endif() - diff --git a/soc/posix/inf_clock/CMakeLists.txt b/soc/posix/inf_clock/CMakeLists.txt deleted file mode 100644 index 5bc6ab3c428..00000000000 --- a/soc/posix/inf_clock/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_compile_definitions(NO_POSIX_CHEATS) - -zephyr_library_sources( - soc.c - native_tasks.c - ) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/posix/include - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/posix/linker.ld CACHE INTERNAL "") diff --git a/soc/posix/inf_clock/Kconfig b/soc/posix/inf_clock/Kconfig deleted file mode 100644 index 27a5d511ec5..00000000000 --- a/soc/posix/inf_clock/Kconfig +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config NATIVE_SIMULATOR_MCU_N - int "CPU Number this image targets" - range 0 15 - default 0 - depends on NATIVE_LIBRARY - help - Which native simulator microcontroller/CPU number is this image targeting. - This option is only applicable for targets which use the - native simulator as their runner. - -config NATIVE_SIMULATOR_NUMBER_MCUS - int "Total number of MCUs this target has" - range 1 16 - default 1 - depends on NATIVE_LIBRARY - help - How many AMP MCUs does this target have in total. - -config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX - int "Which CPU is the primary/preferred" - default 0 - depends on NATIVE_LIBRARY - help - On a multi MCU device, which MCU is the preferred one. - This MCU will for example have its tests command line parameters presented - without any prefix. Note that an MCU being primary does not imply it will be - the first one to boot, or even that it will boot automatically. - -config NATIVE_SIMULATOR_EXTRA_IMAGE_PATHS - string "Other cores images to include" - depends on NATIVE_LIBRARY - help - This option can be used to provide the native simulator with other MCUs/Cores images which have - been produced by either other Zephyr builds or different OS builds. - So you can, for ex., use this application build to produce one core image, and at the same time - have it produce the final link with the native simulator runner and the other MCU images. - -config NATIVE_SIMULATOR_AUTOSTART_MCU - bool "Auto-start this MCU" - depends on NATIVE_LIBRARY - help - Automatically start the MCU this Zephyr image is built for during HW boot, - even if in other circumstances this MCU would not start automatically (for ex. because - another core is meant to release its reset). - If that MCU was, by HW design, going to start at HW boot anyhow, this option does nothing. - This option is meant to facilitate development. diff --git a/soc/posix/inf_clock/Kconfig.defconfig b/soc/posix/inf_clock/Kconfig.defconfig deleted file mode 100644 index fd74815c4a6..00000000000 --- a/soc/posix/inf_clock/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "inf_clock" - depends on SOC_POSIX diff --git a/soc/posix/inf_clock/Kconfig.soc b/soc/posix/inf_clock/Kconfig.soc deleted file mode 100644 index 5c300b6eaff..00000000000 --- a/soc/posix/inf_clock/Kconfig.soc +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_POSIX - bool "Native port" - select ARCH_POSIX - select CPU_HAS_FPU - help - SOC for to the POSIX arch. It emulates a CPU running at an infinitely fast - clock. That means the CPU will always run in zero time until completion after - each wake reason (e.g. interrupts), before going back to idle. Note that an - infinite loop in the code which does not sleep the CPU will cause the process - to appear "hung", as simulated time does not advance while the CPU does not - sleep. Therefore do not use busy waits while waiting for something to happen - (if needed use k_busy_wait()). - Note that the interrupt handling is provided by the board. diff --git a/soc/qemu_malta/CMakeLists.txt b/soc/qemu_malta/CMakeLists.txt new file mode 100644 index 00000000000..fd24f78c41d --- /dev/null +++ b/soc/qemu_malta/CMakeLists.txt @@ -0,0 +1,21 @@ +# Copyright (c) 2020, 2021 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_compile_options( + -mips32 + ${TOOLCHAIN_C_FLAGS} +) + +zephyr_sources( + vector.S +) + +zephyr_ld_options( + -mips32 + ${TOOLCHAIN_LD_FLAGS} +) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/mips/linker.ld CACHE INTERNAL "") diff --git a/soc/qemu_malta/Kconfig b/soc/qemu_malta/Kconfig new file mode 100644 index 00000000000..f113aed6764 --- /dev/null +++ b/soc/qemu_malta/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_MALTA + select MIPS diff --git a/soc/qemu_malta/Kconfig.defconfig b/soc/qemu_malta/Kconfig.defconfig new file mode 100644 index 00000000000..6eb3470689d --- /dev/null +++ b/soc/qemu_malta/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_QEMU_MALTA + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 200000000 + +config NUM_IRQS + default 8 + +endif # SOC_QEMU_MALTA diff --git a/soc/qemu_malta/Kconfig.soc b/soc/qemu_malta/Kconfig.soc new file mode 100644 index 00000000000..2ffbdea589d --- /dev/null +++ b/soc/qemu_malta/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_MALTA + bool + +config SOC + default "qemu_malta" if SOC_QEMU_MALTA diff --git a/soc/mips/qemu_malta/soc.h b/soc/qemu_malta/soc.h similarity index 100% rename from soc/mips/qemu_malta/soc.h rename to soc/qemu_malta/soc.h diff --git a/soc/qemu_malta/soc.yml b/soc/qemu_malta/soc.yml new file mode 100644 index 00000000000..0ba23c27381 --- /dev/null +++ b/soc/qemu_malta/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: qemu_malta diff --git a/soc/mips/qemu_malta/vector.S b/soc/qemu_malta/vector.S similarity index 100% rename from soc/mips/qemu_malta/vector.S rename to soc/qemu_malta/vector.S diff --git a/soc/quicklogic/eos_s3/CMakeLists.txt b/soc/quicklogic/eos_s3/CMakeLists.txt new file mode 100644 index 00000000000..5c821692a4b --- /dev/null +++ b/soc/quicklogic/eos_s3/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2020 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/quicklogic/eos_s3/Kconfig b/soc/quicklogic/eos_s3/Kconfig new file mode 100644 index 00000000000..e294a432778 --- /dev/null +++ b/soc/quicklogic/eos_s3/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2020 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EOS_S3 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select EOS_S3_HAL diff --git a/soc/quicklogic/eos_s3/Kconfig.defconfig b/soc/quicklogic/eos_s3/Kconfig.defconfig new file mode 100644 index 00000000000..2d4f48b45e3 --- /dev/null +++ b/soc/quicklogic/eos_s3/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2020 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_EOS_S3 + +config NUM_IRQS + default 52 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 61440000 + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +endif # SERIAL + +endif # SOC_EOS_S3 diff --git a/soc/quicklogic/eos_s3/Kconfig.soc b/soc/quicklogic/eos_s3/Kconfig.soc new file mode 100644 index 00000000000..0f762d3927e --- /dev/null +++ b/soc/quicklogic/eos_s3/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2020 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EOS_S3 + bool + help + QuickLogic EOS S3 SoC + +config SOC + default "quicklogic_eos_s3" if SOC_EOS_S3 diff --git a/soc/arm/quicklogic_eos_s3/pinctrl_soc.h b/soc/quicklogic/eos_s3/pinctrl_soc.h similarity index 100% rename from soc/arm/quicklogic_eos_s3/pinctrl_soc.h rename to soc/quicklogic/eos_s3/pinctrl_soc.h diff --git a/soc/arm/quicklogic_eos_s3/soc.c b/soc/quicklogic/eos_s3/soc.c similarity index 100% rename from soc/arm/quicklogic_eos_s3/soc.c rename to soc/quicklogic/eos_s3/soc.c diff --git a/soc/arm/quicklogic_eos_s3/soc.h b/soc/quicklogic/eos_s3/soc.h similarity index 100% rename from soc/arm/quicklogic_eos_s3/soc.h rename to soc/quicklogic/eos_s3/soc.h diff --git a/soc/quicklogic/eos_s3/soc.yml b/soc/quicklogic/eos_s3/soc.yml new file mode 100644 index 00000000000..6a217341807 --- /dev/null +++ b/soc/quicklogic/eos_s3/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: quicklogic_eos_s3 diff --git a/soc/arm/quicklogic_eos_s3/soc_pinmap.h b/soc/quicklogic/eos_s3/soc_pinmap.h similarity index 100% rename from soc/arm/quicklogic_eos_s3/soc_pinmap.h rename to soc/quicklogic/eos_s3/soc_pinmap.h diff --git a/soc/arm/bcm_vk/CMakeLists.txt b/soc/raspberrypi/CMakeLists.txt similarity index 100% rename from soc/arm/bcm_vk/CMakeLists.txt rename to soc/raspberrypi/CMakeLists.txt diff --git a/soc/raspberrypi/Kconfig b/soc/raspberrypi/Kconfig new file mode 100644 index 00000000000..2085e72f2b1 --- /dev/null +++ b/soc/raspberrypi/Kconfig @@ -0,0 +1,11 @@ +# Raspberry Pi (RP) MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RPI_PICO + +rsource "*/Kconfig" + +endif # SOC_FAMILY_RPI_PICO diff --git a/soc/raspberrypi/Kconfig.defconfig b/soc/raspberrypi/Kconfig.defconfig new file mode 100644 index 00000000000..6cc52817a8f --- /dev/null +++ b/soc/raspberrypi/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Raspberry Pi (RP) MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RPI_PICO + +rsource "*/Kconfig.defconfig" + +config PINCTRL + default y + +endif # SOC_FAMILY_RPI_PICO diff --git a/soc/raspberrypi/Kconfig.soc b/soc/raspberrypi/Kconfig.soc new file mode 100644 index 00000000000..b0b8b7b761f --- /dev/null +++ b/soc/raspberrypi/Kconfig.soc @@ -0,0 +1,12 @@ +# Raspberry Pi (RP) MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RPI_PICO + bool + +config SOC_FAMILY + default "rpi_pico" if SOC_FAMILY_RPI_PICO + +rsource "*/Kconfig.soc" diff --git a/soc/raspberrypi/rp2xxx/CMakeLists.txt b/soc/raspberrypi/rp2xxx/CMakeLists.txt new file mode 100644 index 00000000000..8f48fc01aba --- /dev/null +++ b/soc/raspberrypi/rp2xxx/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/raspberrypi/rp2xxx/Kconfig b/soc/raspberrypi/rp2xxx/Kconfig new file mode 100644 index 00000000000..1abc32af2ce --- /dev/null +++ b/soc/raspberrypi/rp2xxx/Kconfig @@ -0,0 +1,53 @@ +# Raspberry Pi RP2XXX MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RP2XXX + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + select HAS_RPI_PICO + select XIP + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + help + Enable support for Raspberry Pi RP2 MCU series + +config RP2_REQUIRES_SECOND_STAGE_BOOT + bool + default y if FLASH_LOAD_OFFSET = 0x100 + +# Flash type used by the SoC. The board should select the one used. + +config RP2_FLASH_W25Q080 + bool + help + Configure RP2 to use a W25Q080 flash chip, or similar. Should be selected + by the board definition, not the user. + +config RP2_FLASH_GENERIC_03H + bool + help + Configure RP2 to use a flash chip supporting the standard 03h command. + Should be selected by the board definition, not the user. + +config RP2_FLASH_IS25LP080 + bool + help + Configure RP2 to use a IS25LP080 flash chip, or similar. Should be selected + by the board definition, not the user. + +config RP2_FLASH_W25X10CL + bool + help + Configure RP2 to use a W25X10CL flash chip, or similar. Should be selected + by the board definition, not the user. + +config RP2_FLASH_AT25SF128A + bool + help + Configure RP2 to use a AT25SF128A flash chip, or similar. Should be selected + by the board definition, not the user. diff --git a/soc/raspberrypi/rp2xxx/Kconfig.defconfig b/soc/raspberrypi/rp2xxx/Kconfig.defconfig new file mode 100644 index 00000000000..82256e806d0 --- /dev/null +++ b/soc/raspberrypi/rp2xxx/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Raspberry Pi RP2XXX MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RP2XXX + +rsource "Kconfig.defconfig.rp2*" + +config NUM_IRQS + default 26 + +endif # SOC_SERIES_RP2XXX diff --git a/soc/arm/rpi_pico/rp2/Kconfig.defconfig.rp2040 b/soc/raspberrypi/rp2xxx/Kconfig.defconfig.rp2040 similarity index 84% rename from soc/arm/rpi_pico/rp2/Kconfig.defconfig.rp2040 rename to soc/raspberrypi/rp2xxx/Kconfig.defconfig.rp2040 index 0470f2aaa69..304e2629afd 100644 --- a/soc/arm/rpi_pico/rp2/Kconfig.defconfig.rp2040 +++ b/soc/raspberrypi/rp2xxx/Kconfig.defconfig.rp2040 @@ -3,10 +3,6 @@ # Copyright (c) 2021 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -config SOC - default "rp2040" - depends on SOC_RP2040 - config BUILD_OUTPUT_UF2_USE_FLASH_BASE default y if RP2_REQUIRES_SECOND_STAGE_BOOT diff --git a/soc/raspberrypi/rp2xxx/Kconfig.soc b/soc/raspberrypi/rp2xxx/Kconfig.soc new file mode 100644 index 00000000000..045061697fe --- /dev/null +++ b/soc/raspberrypi/rp2xxx/Kconfig.soc @@ -0,0 +1,19 @@ +# Raspberry Pi RP2XXX MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RP2040 + bool + select SOC_SERIES_RP2XXX + +config SOC_SERIES_RP2XXX + bool + select SOC_FAMILY_RPI_PICO + +config SOC_SERIES + default "rp2xxx" if SOC_SERIES_RP2XXX + +config SOC + default "rp2040" if SOC_RP2040 diff --git a/soc/arm/rpi_pico/rp2/linker.ld b/soc/raspberrypi/rp2xxx/linker.ld similarity index 100% rename from soc/arm/rpi_pico/rp2/linker.ld rename to soc/raspberrypi/rp2xxx/linker.ld diff --git a/soc/arm/rpi_pico/rp2/pinctrl_soc.h b/soc/raspberrypi/rp2xxx/pinctrl_soc.h similarity index 100% rename from soc/arm/rpi_pico/rp2/pinctrl_soc.h rename to soc/raspberrypi/rp2xxx/pinctrl_soc.h diff --git a/soc/arm/rpi_pico/rp2/soc.c b/soc/raspberrypi/rp2xxx/soc.c similarity index 100% rename from soc/arm/rpi_pico/rp2/soc.c rename to soc/raspberrypi/rp2xxx/soc.c diff --git a/soc/arm/rpi_pico/rp2/soc.h b/soc/raspberrypi/rp2xxx/soc.h similarity index 100% rename from soc/arm/rpi_pico/rp2/soc.h rename to soc/raspberrypi/rp2xxx/soc.h diff --git a/soc/raspberrypi/soc.yml b/soc/raspberrypi/soc.yml new file mode 100644 index 00000000000..192d7a947f2 --- /dev/null +++ b/soc/raspberrypi/soc.yml @@ -0,0 +1,6 @@ +family: +- name: rpi_pico + series: + - name: rp2xxx + socs: + - name: rp2040 diff --git a/soc/arm/renesas_ra/CMakeLists.txt b/soc/renesas/ra/CMakeLists.txt similarity index 100% rename from soc/arm/renesas_ra/CMakeLists.txt rename to soc/renesas/ra/CMakeLists.txt diff --git a/soc/renesas/ra/Kconfig b/soc/renesas/ra/Kconfig new file mode 100644 index 00000000000..52a056a7612 --- /dev/null +++ b/soc/renesas/ra/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RA + +config SERIES_SPECIFIC_SOC_INIT + bool "Use series specific initialize" + +rsource "*/Kconfig" + +endif # SOC_FAMILY_RENESAS_RA diff --git a/soc/renesas/ra/Kconfig.defconfig b/soc/renesas/ra/Kconfig.defconfig new file mode 100644 index 00000000000..beb1aa718da --- /dev/null +++ b/soc/renesas/ra/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RA + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_RENESAS_RA diff --git a/soc/renesas/ra/Kconfig.soc b/soc/renesas/ra/Kconfig.soc new file mode 100644 index 00000000000..52449b517a5 --- /dev/null +++ b/soc/renesas/ra/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RENESAS_RA + bool + +config SOC_FAMILY + default "renesas_ra" if SOC_FAMILY_RENESAS_RA + +rsource "*/Kconfig.soc" diff --git a/soc/arm/renesas_ra/common/pinctrl_ra.h b/soc/renesas/ra/common/pinctrl_ra.h similarity index 100% rename from soc/arm/renesas_ra/common/pinctrl_ra.h rename to soc/renesas/ra/common/pinctrl_ra.h diff --git a/soc/arm/renesas_ra/common/ra_common_soc.h b/soc/renesas/ra/common/ra_common_soc.h similarity index 100% rename from soc/arm/renesas_ra/common/ra_common_soc.h rename to soc/renesas/ra/common/ra_common_soc.h diff --git a/soc/renesas/ra/ra4m1/CMakeLists.txt b/soc/renesas/ra/ra4m1/CMakeLists.txt new file mode 100644 index 00000000000..c0d9c7b1baa --- /dev/null +++ b/soc/renesas/ra/ra4m1/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4m1/Kconfig b/soc/renesas/ra/ra4m1/Kconfig new file mode 100644 index 00000000000..56153d0732f --- /dev/null +++ b/soc/renesas/ra/ra4m1/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4M1 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_SYSTICK + select DYNAMIC_INTERRUPTS + select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME + select XIP diff --git a/soc/renesas/ra/ra4m1/Kconfig.defconfig b/soc/renesas/ra/ra4m1/Kconfig.defconfig new file mode 100644 index 00000000000..5913bd7257f --- /dev/null +++ b/soc/renesas/ra/ra4m1/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA4M1 + +config NUM_IRQS + default 32 + +endif # SOC_SERIES_RA4M1 diff --git a/soc/renesas/ra/ra4m1/Kconfig.soc b/soc/renesas/ra/ra4m1/Kconfig.soc new file mode 100644 index 00000000000..e83c7bf3629 --- /dev/null +++ b/soc/renesas/ra/ra4m1/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4M1 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA4M1 + +config SOC_R7FA4M1AB3CFM + bool + select SOC_SERIES_RA4M1 + help + R7FA4M1AB3CFM + +config SOC_SERIES + default "ra4m1" if SOC_SERIES_RA4M1 + +config SOC + default "r7fa4m1ab3cfm" if SOC_R7FA4M1AB3CFM diff --git a/soc/arm/renesas_ra/ra4m1/pinctrl_soc.h b/soc/renesas/ra/ra4m1/pinctrl_soc.h similarity index 100% rename from soc/arm/renesas_ra/ra4m1/pinctrl_soc.h rename to soc/renesas/ra/ra4m1/pinctrl_soc.h diff --git a/soc/arm/renesas_ra/ra4m1/soc.h b/soc/renesas/ra/ra4m1/soc.h similarity index 100% rename from soc/arm/renesas_ra/ra4m1/soc.h rename to soc/renesas/ra/ra4m1/soc.h diff --git a/soc/renesas/ra/soc.yml b/soc/renesas/ra/soc.yml new file mode 100644 index 00000000000..e031d886067 --- /dev/null +++ b/soc/renesas/ra/soc.yml @@ -0,0 +1,6 @@ +family: + - name: renesas_ra + series: + - name: ra4m1 + socs: + - name: r7fa4m1ab3cfm diff --git a/soc/arm/renesas_rcar/CMakeLists.txt b/soc/renesas/rcar/CMakeLists.txt similarity index 100% rename from soc/arm/renesas_rcar/CMakeLists.txt rename to soc/renesas/rcar/CMakeLists.txt diff --git a/soc/renesas/rcar/Kconfig b/soc/renesas/rcar/Kconfig new file mode 100644 index 00000000000..76a07262bf7 --- /dev/null +++ b/soc/renesas/rcar/Kconfig @@ -0,0 +1,9 @@ +# Renesas R-Car SoC line +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RCAR + +rsource "*/Kconfig" + +endif # SOC_FAMILY_RENESAS_RCAR diff --git a/soc/renesas/rcar/Kconfig.defconfig b/soc/renesas/rcar/Kconfig.defconfig new file mode 100644 index 00000000000..9a7fa2d5d73 --- /dev/null +++ b/soc/renesas/rcar/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RCAR + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_RENESAS_RCAR diff --git a/soc/renesas/rcar/Kconfig.soc b/soc/renesas/rcar/Kconfig.soc new file mode 100644 index 00000000000..6869cbd86f5 --- /dev/null +++ b/soc/renesas/rcar/Kconfig.soc @@ -0,0 +1,11 @@ +# Renesas R-Car SoC line +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RENESAS_RCAR + bool + +config SOC_FAMILY + default "renesas_rcar" if SOC_FAMILY_RENESAS_RCAR + +rsource "*/Kconfig.soc" diff --git a/soc/arm/renesas_rcar/common/pinctrl_rcar.h b/soc/renesas/rcar/common/pinctrl_rcar.h similarity index 100% rename from soc/arm/renesas_rcar/common/pinctrl_rcar.h rename to soc/renesas/rcar/common/pinctrl_rcar.h diff --git a/soc/renesas/rcar/rcar_gen3/CMakeLists.txt b/soc/renesas/rcar/rcar_gen3/CMakeLists.txt new file mode 100644 index 00000000000..7f96e60788e --- /dev/null +++ b/soc/renesas/rcar/rcar_gen3/CMakeLists.txt @@ -0,0 +1,18 @@ +# Copyright (c) 2021 IoT.bzh +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_SERIES_RCAR_GEN3_R7) + zephyr_sources(r7/soc.c) + zephyr_include_directories(r7) + zephyr_library_sources_ifdef(CONFIG_SOC_R8A77951_R7 pfc_r8a77951.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_SERIES_RCAR_GEN3_A57) + zephyr_include_directories(a57) + zephyr_library_sources_ifdef(CONFIG_SOC_R8A77951_A57 pfc_r8a77951.c) + zephyr_library_sources_ifdef(CONFIG_SOC_R8A77961 pfc_r8a77961.c) + zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/renesas/rcar/rcar_gen3/Kconfig b/soc/renesas/rcar/rcar_gen3/Kconfig new file mode 100644 index 00000000000..3d4c577e46a --- /dev/null +++ b/soc/renesas/rcar/rcar_gen3/Kconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RCAR_GEN3_R7 + bool + select ARM + select CPU_CORTEX_R7 + select PLATFORM_SPECIFIC_INIT + select CPU_HAS_DCLS + select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL + +config SOC_SERIES_RCAR_GEN3_A57 + bool + select ARM64 + select CPU_CORTEX_A57 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL + +config SOC_R8A77951_R7 + select SOC_SERIES_RCAR_GEN3_R7 + +config SOC_R8A77951_A57 + select SOC_SERIES_RCAR_GEN3_A57 + +config SOC_R8A77961 + select SOC_SERIES_RCAR_GEN3_A57 diff --git a/soc/renesas/rcar/rcar_gen3/Kconfig.defconfig b/soc/renesas/rcar/rcar_gen3/Kconfig.defconfig new file mode 100644 index 00000000000..173efde9137 --- /dev/null +++ b/soc/renesas/rcar/rcar_gen3/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Renesas R-Car Gen3 SoC line + +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RCAR_GEN3 + +config NUM_IRQS + default 512 if SOC_R8A77951_R7 + default 240 if SOC_R8A77961 || SOC_R8A77951_A57 + +config PINCTRL + default y + +endif # SOC_SERIES_RCAR_GEN3 diff --git a/soc/renesas/rcar/rcar_gen3/Kconfig.soc b/soc/renesas/rcar/rcar_gen3/Kconfig.soc new file mode 100644 index 00000000000..d1476c91d4f --- /dev/null +++ b/soc/renesas/rcar/rcar_gen3/Kconfig.soc @@ -0,0 +1,31 @@ +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RCAR_GEN3 + bool + select SOC_FAMILY_RENESAS_RCAR + +config SOC_R8A77951_R7 + bool + select SOC_SERIES_RCAR_GEN3 + help + R8A77951 R7 + +config SOC_R8A77951_A57 + bool + select SOC_SERIES_RCAR_GEN3 + help + R8A77951 A57 + +config SOC_R8A77961 + bool + select SOC_SERIES_RCAR_GEN3 + help + R8A77961 + +config SOC_SERIES + default "rcar_gen3" if SOC_SERIES_RCAR_GEN3 + +config SOC + default "r8a77951" if SOC_R8A77951_R7 || SOC_R8A77951_A57 + default "r8a77961" if SOC_R8A77961 diff --git a/soc/arm64/renesas_rcar/gen3/pinctrl_soc.h b/soc/renesas/rcar/rcar_gen3/a57/pinctrl_soc.h similarity index 100% rename from soc/arm64/renesas_rcar/gen3/pinctrl_soc.h rename to soc/renesas/rcar/rcar_gen3/a57/pinctrl_soc.h diff --git a/soc/arm64/renesas_rcar/gen3/mmu_regions.c b/soc/renesas/rcar/rcar_gen3/mmu_regions.c similarity index 100% rename from soc/arm64/renesas_rcar/gen3/mmu_regions.c rename to soc/renesas/rcar/rcar_gen3/mmu_regions.c diff --git a/soc/arm/renesas_rcar/gen3/pfc_r8a77951.c b/soc/renesas/rcar/rcar_gen3/pfc_r8a77951.c similarity index 100% rename from soc/arm/renesas_rcar/gen3/pfc_r8a77951.c rename to soc/renesas/rcar/rcar_gen3/pfc_r8a77951.c diff --git a/soc/arm64/renesas_rcar/gen3/pfc_r8a77961.c b/soc/renesas/rcar/rcar_gen3/pfc_r8a77961.c similarity index 100% rename from soc/arm64/renesas_rcar/gen3/pfc_r8a77961.c rename to soc/renesas/rcar/rcar_gen3/pfc_r8a77961.c diff --git a/soc/arm/renesas_rcar/gen3/pinctrl_soc.h b/soc/renesas/rcar/rcar_gen3/r7/pinctrl_soc.h similarity index 100% rename from soc/arm/renesas_rcar/gen3/pinctrl_soc.h rename to soc/renesas/rcar/rcar_gen3/r7/pinctrl_soc.h diff --git a/soc/arm/renesas_rcar/gen3/soc.c b/soc/renesas/rcar/rcar_gen3/r7/soc.c similarity index 100% rename from soc/arm/renesas_rcar/gen3/soc.c rename to soc/renesas/rcar/rcar_gen3/r7/soc.c diff --git a/soc/arm/renesas_rcar/gen3/soc.h b/soc/renesas/rcar/rcar_gen3/r7/soc.h similarity index 100% rename from soc/arm/renesas_rcar/gen3/soc.h rename to soc/renesas/rcar/rcar_gen3/r7/soc.h diff --git a/soc/renesas/rcar/rcar_gen4/CMakeLists.txt b/soc/renesas/rcar/rcar_gen4/CMakeLists.txt new file mode 100644 index 00000000000..79be28ffe55 --- /dev/null +++ b/soc/renesas/rcar/rcar_gen4/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2023 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c) +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rcar/rcar_gen4/Kconfig b/soc/renesas/rcar/rcar_gen4/Kconfig new file mode 100644 index 00000000000..a084ac558b8 --- /dev/null +++ b/soc/renesas/rcar/rcar_gen4/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2023 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RCAR_GEN4 + bool + select ARM + select CPU_CORTEX_R52 + select GIC_SINGLE_SECURITY_STATE + select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL + select ARM_ARCH_TIMER diff --git a/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig new file mode 100644 index 00000000000..cdb614fdc62 --- /dev/null +++ b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Renesas R-Car Gen4 SoC line + +# Copyright (c) 2023 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RCAR_GEN4 + +rsource "Kconfig.defconfig.r8a779*" + +endif # SOC_SERIES_RCAR_GEN4 diff --git a/soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779f0 b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0 similarity index 85% rename from soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779f0 rename to soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0 index 6da34845bf9..c3c09787e11 100644 --- a/soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779f0 +++ b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0 @@ -3,9 +3,6 @@ if SOC_R8A779F0 -config SOC - default "r8a779f0" - config NUM_IRQS default 1216 #960 SPI + 256 LPI diff --git a/soc/renesas/rcar/rcar_gen4/Kconfig.soc b/soc/renesas/rcar/rcar_gen4/Kconfig.soc new file mode 100644 index 00000000000..99193973d59 --- /dev/null +++ b/soc/renesas/rcar/rcar_gen4/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2023 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RCAR_GEN4 + bool + select SOC_FAMILY_RENESAS_RCAR + +config SOC_R8A779F0 + bool + select SOC_SERIES_RCAR_GEN4 + help + r8a779f0 + +config SOC_SERIES + default "rcar_gen4" if SOC_SERIES_RCAR_GEN4 + +config SOC + default "r8a779f0" if SOC_R8A779F0 diff --git a/soc/arm/renesas_rcar/gen4/pfc_r8a779f0.c b/soc/renesas/rcar/rcar_gen4/pfc_r8a779f0.c similarity index 100% rename from soc/arm/renesas_rcar/gen4/pfc_r8a779f0.c rename to soc/renesas/rcar/rcar_gen4/pfc_r8a779f0.c diff --git a/soc/arm/renesas_rcar/gen4/pinctrl_soc.h b/soc/renesas/rcar/rcar_gen4/pinctrl_soc.h similarity index 100% rename from soc/arm/renesas_rcar/gen4/pinctrl_soc.h rename to soc/renesas/rcar/rcar_gen4/pinctrl_soc.h diff --git a/soc/arm/renesas_rcar/gen4/soc.h b/soc/renesas/rcar/rcar_gen4/soc.h similarity index 100% rename from soc/arm/renesas_rcar/gen4/soc.h rename to soc/renesas/rcar/rcar_gen4/soc.h diff --git a/soc/renesas/rcar/soc.yml b/soc/renesas/rcar/soc.yml new file mode 100644 index 00000000000..6c936a7b7c9 --- /dev/null +++ b/soc/renesas/rcar/soc.yml @@ -0,0 +1,13 @@ +family: + - name: renesas_rcar + series: + - name: rcar_gen3 + socs: + - name: r8a77951 + cpuclusters: + - name: r7 + - name: a57 + - name: r8a77961 + - name: rcar_gen4 + socs: + - name: r8a779f0 diff --git a/soc/renesas/rzt2m/CMakeLists.txt b/soc/renesas/rzt2m/CMakeLists.txt new file mode 100644 index 00000000000..8cf72713d11 --- /dev/null +++ b/soc/renesas/rzt2m/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rzt2m/Kconfig b/soc/renesas/rzt2m/Kconfig new file mode 100644 index 00000000000..5b26c6bcba7 --- /dev/null +++ b/soc/renesas/rzt2m/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RENESAS_RZT2M + select ARM + select CPU_CORTEX_R52 + select CPU_HAS_ARM_MPU + select GIC_V3 + select GIC_SINGLE_SECURITY_STATE + select ARM_ARCH_TIMER + select SYSCON diff --git a/soc/renesas/rzt2m/Kconfig.defconfig b/soc/renesas/rzt2m/Kconfig.defconfig new file mode 100644 index 00000000000..7eedc53ffc6 --- /dev/null +++ b/soc/renesas/rzt2m/Kconfig.defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_RENESAS_RZT2M + +config NUM_IRQS + default 994 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 20000000 + +config FPU + default y + +config FLASH_SIZE + default 0 + +config FLASH_BASE_ADDRESS + default 0 + +endif # SOC_RENESAS_RZT2M diff --git a/soc/renesas/rzt2m/Kconfig.soc b/soc/renesas/rzt2m/Kconfig.soc new file mode 100644 index 00000000000..9304484d065 --- /dev/null +++ b/soc/renesas/rzt2m/Kconfig.soc @@ -0,0 +1,14 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RENESAS_RZT2M + bool + +config SOC_PART_NUMBER_R9A07G075 + bool + +config SOC + default "renesas_rzt2m" if SOC_RENESAS_RZT2M + +config SOC_PART_NUMBER + default "R9A07G075" if SOC_PART_NUMBER_R9A07G075 diff --git a/soc/arm/renesas_rzt2m/linker.ld b/soc/renesas/rzt2m/linker.ld similarity index 100% rename from soc/arm/renesas_rzt2m/linker.ld rename to soc/renesas/rzt2m/linker.ld diff --git a/soc/arm/renesas_rzt2m/pinctrl_soc.h b/soc/renesas/rzt2m/pinctrl_soc.h similarity index 100% rename from soc/arm/renesas_rzt2m/pinctrl_soc.h rename to soc/renesas/rzt2m/pinctrl_soc.h diff --git a/soc/arm/renesas_rzt2m/soc.c b/soc/renesas/rzt2m/soc.c similarity index 100% rename from soc/arm/renesas_rzt2m/soc.c rename to soc/renesas/rzt2m/soc.c diff --git a/soc/arm/renesas_rzt2m/soc.h b/soc/renesas/rzt2m/soc.h similarity index 100% rename from soc/arm/renesas_rzt2m/soc.h rename to soc/renesas/rzt2m/soc.h diff --git a/soc/renesas/rzt2m/soc.yml b/soc/renesas/rzt2m/soc.yml new file mode 100644 index 00000000000..35c7cc27f77 --- /dev/null +++ b/soc/renesas/rzt2m/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: renesas_rzt2m diff --git a/soc/arm/renesas_smartbond/CMakeLists.txt b/soc/renesas/smartbond/CMakeLists.txt similarity index 100% rename from soc/arm/renesas_smartbond/CMakeLists.txt rename to soc/renesas/smartbond/CMakeLists.txt diff --git a/soc/renesas/smartbond/Kconfig b/soc/renesas/smartbond/Kconfig new file mode 100644 index 00000000000..184f4b77ca2 --- /dev/null +++ b/soc/renesas/smartbond/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_SMARTBOND + +rsource "*/Kconfig" + +endif # SOC_FAMILY_RENESAS_SMARTBOND diff --git a/soc/renesas/smartbond/Kconfig.defconfig b/soc/renesas/smartbond/Kconfig.defconfig new file mode 100644 index 00000000000..0df71b16f2e --- /dev/null +++ b/soc/renesas/smartbond/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_SMARTBOND + +rsource "*/Kconfig.defconfig" + +config PINCTRL + default y + +endif # SOC_FAMILY_RENESAS_SMARTBOND diff --git a/soc/renesas/smartbond/Kconfig.soc b/soc/renesas/smartbond/Kconfig.soc new file mode 100644 index 00000000000..584bb522944 --- /dev/null +++ b/soc/renesas/smartbond/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RENESAS_SMARTBOND + bool + +config SOC_FAMILY + default "renesas_smartbond" if SOC_FAMILY_RENESAS_SMARTBOND + +rsource "*/Kconfig.soc" diff --git a/soc/renesas/smartbond/da1469x/CMakeLists.txt b/soc/renesas/smartbond/da1469x/CMakeLists.txt new file mode 100644 index 00000000000..0c45be52d2d --- /dev/null +++ b/soc/renesas/smartbond/da1469x/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_linker_sources( + RAM_SECTIONS + SORT_KEY 0 + intvect_reserved.ld +) +zephyr_library() +zephyr_library_sources(soc.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/smartbond/da1469x/Kconfig b/soc/renesas/smartbond/da1469x/Kconfig new file mode 100644 index 00000000000..267df2ea79d --- /dev/null +++ b/soc/renesas/smartbond/da1469x/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_DA1469X + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_SYSTICK + select ARMV8_M_DSP + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select CLOCK_CONTROL + select CLOCK_CONTROL_SMARTBOND diff --git a/soc/renesas/smartbond/da1469x/Kconfig.defconfig b/soc/renesas/smartbond/da1469x/Kconfig.defconfig new file mode 100644 index 00000000000..fedbde9f19e --- /dev/null +++ b/soc/renesas/smartbond/da1469x/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_DA1469X + +config NUM_IRQS + default 40 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config SRAM_VECTOR_TABLE + default y + +config USE_DT_CODE_PARTITION + default y if MCUBOOT + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config FLASH_LOAD_OFFSET + default 0x2400 if !USE_DT_CODE_PARTITION + +config PLATFORM_SPECIFIC_INIT + default y + +endif # SOC_SERIES_DA1469X diff --git a/soc/renesas/smartbond/da1469x/Kconfig.soc b/soc/renesas/smartbond/da1469x/Kconfig.soc new file mode 100644 index 00000000000..b52b2905936 --- /dev/null +++ b/soc/renesas/smartbond/da1469x/Kconfig.soc @@ -0,0 +1,27 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_DA1469X + bool + select SOC_FAMILY_RENESAS_SMARTBOND + help + Renesas SmartBond(tm) DA1469x series MCU + +config SOC_DA14695 + bool + select SOC_SERIES_DA1469X + help + DA14695 + +config SOC_DA14699 + bool + select SOC_SERIES_DA1469X + help + DA14699 + +config SOC_SERIES + default "da1469x" if SOC_SERIES_DA1469X + +config SOC + default "da14695" if SOC_DA14695 + default "da14699" if SOC_DA14699 diff --git a/soc/arm/renesas_smartbond/da1469x/intvect_reserved.ld b/soc/renesas/smartbond/da1469x/intvect_reserved.ld similarity index 100% rename from soc/arm/renesas_smartbond/da1469x/intvect_reserved.ld rename to soc/renesas/smartbond/da1469x/intvect_reserved.ld diff --git a/soc/arm/renesas_smartbond/da1469x/pinctrl_soc.h b/soc/renesas/smartbond/da1469x/pinctrl_soc.h similarity index 100% rename from soc/arm/renesas_smartbond/da1469x/pinctrl_soc.h rename to soc/renesas/smartbond/da1469x/pinctrl_soc.h diff --git a/soc/arm/renesas_smartbond/da1469x/soc.c b/soc/renesas/smartbond/da1469x/soc.c similarity index 100% rename from soc/arm/renesas_smartbond/da1469x/soc.c rename to soc/renesas/smartbond/da1469x/soc.c diff --git a/soc/arm/renesas_smartbond/da1469x/soc.h b/soc/renesas/smartbond/da1469x/soc.h similarity index 100% rename from soc/arm/renesas_smartbond/da1469x/soc.h rename to soc/renesas/smartbond/da1469x/soc.h diff --git a/soc/renesas/smartbond/soc.yml b/soc/renesas/smartbond/soc.yml new file mode 100644 index 00000000000..ee32857c5b7 --- /dev/null +++ b/soc/renesas/smartbond/soc.yml @@ -0,0 +1,7 @@ +family: + - name: renesas_smartbond + series: + - name: da1469x + socs: + - name: da14695 + - name: da14699 diff --git a/soc/riscv/renode_virt/CMakeLists.txt b/soc/renode/riscv_virtual/CMakeLists.txt similarity index 100% rename from soc/riscv/renode_virt/CMakeLists.txt rename to soc/renode/riscv_virtual/CMakeLists.txt diff --git a/soc/renode/riscv_virtual/Kconfig b/soc/renode/riscv_virtual/Kconfig new file mode 100644 index 00000000000..37c4578df80 --- /dev/null +++ b/soc/renode/riscv_virtual/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2023 Meta +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RISCV_VIRTUAL_RENODE + select RISCV + select RISCV_PRIVILEGED + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_HAS_PLIC diff --git a/soc/renode/riscv_virtual/Kconfig.defconfig b/soc/renode/riscv_virtual/Kconfig.defconfig new file mode 100644 index 00000000000..8b00c5867ab --- /dev/null +++ b/soc/renode/riscv_virtual/Kconfig.defconfig @@ -0,0 +1,39 @@ +# Copyright (c) 2023 Meta +# SPDX-License-Identifier: Apache-2.0 + +if SOC_RISCV_VIRTUAL_RENODE + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 4000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 1ST_LEVEL_INTERRUPT_BITS + default 4 + +config NUM_2ND_LEVEL_AGGREGATORS + default 2 + +config 2ND_LEVEL_INTERRUPT_BITS + default 11 + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config 2ND_LVL_INTR_01_OFFSET + default 4 + +config MAX_IRQ_PER_AGGREGATOR + default 1023 + +config NUM_IRQS + default 2058 + +endif # SOC_RISCV_VIRTUAL_RENODE diff --git a/soc/renode/riscv_virtual/Kconfig.soc b/soc/renode/riscv_virtual/Kconfig.soc new file mode 100644 index 00000000000..f047830815c --- /dev/null +++ b/soc/renode/riscv_virtual/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Meta +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RISCV_VIRTUAL_RENODE + bool + help + Renode RISCV32 Virtual system implementation + +config SOC + default "riscv_virtual_renode" if SOC_RISCV_VIRTUAL_RENODE diff --git a/soc/renode/riscv_virtual/soc.yml b/soc/renode/riscv_virtual/soc.yml new file mode 100644 index 00000000000..f971b54978d --- /dev/null +++ b/soc/renode/riscv_virtual/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: riscv_virtual_renode diff --git a/soc/riscv/CMakeLists.txt b/soc/riscv/CMakeLists.txt deleted file mode 100644 index 79d115704b2..00000000000 --- a/soc/riscv/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(common) - -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) -else() - add_subdirectory(${SOC_NAME}) -endif() diff --git a/soc/riscv/andes_v5/Kconfig b/soc/riscv/andes_v5/Kconfig deleted file mode 100644 index f3c78ab7f81..00000000000 --- a/soc/riscv/andes_v5/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ANDES_V5 - bool - -if SOC_FAMILY_ANDES_V5 - -config SOC_FAMILY - string - default "andes_v5" - -source "soc/riscv/andes_v5/*/Kconfig.soc" - -endif # SOC_FAMILY_ANDES_V5 diff --git a/soc/riscv/andes_v5/Kconfig.defconfig b/soc/riscv/andes_v5/Kconfig.defconfig deleted file mode 100644 index 6213f28d2cb..00000000000 --- a/soc/riscv/andes_v5/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/andes_v5/*/Kconfig.defconfig.series" diff --git a/soc/riscv/andes_v5/Kconfig.soc b/soc/riscv/andes_v5/Kconfig.soc deleted file mode 100644 index 9efb4781934..00000000000 --- a/soc/riscv/andes_v5/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/andes_v5/*/Kconfig.series" diff --git a/soc/riscv/andes_v5/ae350/Kconfig.defconfig.series b/soc/riscv/andes_v5/ae350/Kconfig.defconfig.series deleted file mode 100644 index 7b9bbc3eadb..00000000000 --- a/soc/riscv/andes_v5/ae350/Kconfig.defconfig.series +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2021 Andes Technology Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ANDES_AE350 - -# Kconfig picks the first default with a satisfied condition. -# SoC defaults should be parsed before SoC Series defaults, because SoCs usually -# overrides SoC Series values. -source "soc/riscv/andes_v5/ae350/Kconfig.defconfig.ae*" - -config SOC_SERIES - default "ae350" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 60000000 - -config KERNEL_ENTRY - default "entry" - -config RISCV_GENERIC_TOOLCHAIN - default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" - default n - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 52 - -config NUM_IRQS - default 64 - -endif # SOC_SERIES_ANDES_AE350 diff --git a/soc/riscv/andes_v5/ae350/Kconfig.series b/soc/riscv/andes_v5/ae350/Kconfig.series deleted file mode 100644 index c2e9b40bfb7..00000000000 --- a/soc/riscv/andes_v5/ae350/Kconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 Andes Technology Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ANDES_AE350 - bool "Andes V5 AE350 SoC Series Implementation" - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - select SOC_FAMILY_ANDES_V5 - help - Enable support for Andes V5 AE350 SoC Series diff --git a/soc/riscv/andes_v5/ae350/Kconfig.soc b/soc/riscv/andes_v5/ae350/Kconfig.soc deleted file mode 100644 index 1731cc08f51..00000000000 --- a/soc/riscv/andes_v5/ae350/Kconfig.soc +++ /dev/null @@ -1,124 +0,0 @@ -# Copyright (c) 2021 Andes Technology Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Andes V5 SoC Selection" -depends on SOC_SERIES_ANDES_AE350 - -config SOC_ANDES_AE350 - bool "Andes AE350 SoC implementation" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select RISCV_PMP - -endchoice - -if SOC_SERIES_ANDES_AE350 - -choice -prompt "Base CPU ISA options" -default RV32I_CPU - -config RV32I_CPU - bool "RISCV32 CPU ISA" - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config RV32E_CPU - bool "RISCV32E CPU ISA" - select RISCV_ISA_RV32E - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config RV64I_CPU - bool "RISCV64 CPU ISA" - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select 64BIT - -endchoice - -choice -prompt "FPU options" -default NO_FPU - -config NO_FPU - bool "No FPU" - -config SINGLE_PRECISION_FPU - bool "Single precision FPU" - select CPU_HAS_FPU - -config DOUBLE_PRECISION_FPU - bool "Double precision FPU" - select CPU_HAS_FPU_DOUBLE_PRECISION - -endchoice - -config SOC_ANDES_V5_HWDSP - bool "AndeStar V5 DSP ISA" - select RISCV_SOC_CONTEXT_SAVE - depends on !RISCV_GENERIC_TOOLCHAIN - help - This option enables the AndeStar v5 hardware DSP, in order to - support using the DSP instructions. - -config SOC_ANDES_V5_PFT - bool "Andes V5 PowerBrake extension" - default y - select RISCV_SOC_CONTEXT_SAVE - help - The PowerBrake extension throttles performance by reducing instruction - executing rate. - -config SOC_ANDES_V5_EXECIT - bool "Andes V5 EXEC.IT extension" - depends on RISCV_ISA_EXT_C - depends on !RISCV_GENERIC_TOOLCHAIN - depends on !LINKER_USE_NO_RELAX - help - The EXEC.IT extension (Execution on Instruction Table) generate - a look-up table and replaces suitable 32-bit instructions with - the 16-bit "exec.it ". - -config SOC_ANDES_V5_PMA - bool "Andes V5 Physical Memory Attribute (PMA)" - select ARCH_HAS_NOCACHE_MEMORY_SUPPORT - help - This option enables the Andes V5 PMA, in order to support SW to - configure physical memory attribute by PMA CSRs. The address - matching of Andes V5 PMA is like RISC-V PMP NAPOT mode - (power-of-two alignment). - -config SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE - int - depends on SOC_ANDES_V5_PMA - default 4096 - help - Minimum size (and alignment) of an PMA region. Use this symbol - to guarantee minimum size and alignment of PMA regions. - -# Workaround for not being able to have commas in macro arguments -DT_ANDESTECH_L2C := andestech,l2c - -config SOC_ANDES_V5_L2C - bool - default $(dt_compat_enabled,$(DT_ANDESTECH_L2C)) - -config SOC_ANDES_V5_IOCP - bool "Andes V5 I/O Coherence Port (IOCP)" - depends on SOC_ANDES_V5_L2C - depends on DCACHE - help - Support Andes V5 I/O Coherence Port to handle cache coherency - between cache and external non-caching master, such as DMA - controller. - -endif # SOC_SERIES_ANDES_AE350 diff --git a/soc/riscv/common/CMakeLists.txt b/soc/riscv/common/CMakeLists.txt deleted file mode 100644 index 91ef5c975b9..00000000000 --- a/soc/riscv/common/CMakeLists.txt +++ /dev/null @@ -1 +0,0 @@ -add_subdirectory_ifdef(CONFIG_RISCV_PRIVILEGED riscv-privileged) diff --git a/soc/riscv/common/Kconfig b/soc/riscv/common/Kconfig deleted file mode 100644 index 91f2c5cf80a..00000000000 --- a/soc/riscv/common/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 -# -source "soc/riscv/common/riscv-privileged/Kconfig" diff --git a/soc/riscv/efinix_sapphire/Kconfig.defconfig b/soc/riscv/efinix_sapphire/Kconfig.defconfig deleted file mode 100644 index 95a33b4ab82..00000000000 --- a/soc/riscv/efinix_sapphire/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2023 Efinix Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_EFINIX_SAPPHIRE - -config SOC - default "efinix_sapphire" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config RISCV_SOC_INTERRUPT_INIT - bool - default y - -config NUM_IRQS - int - default 36 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -endif # SOC_EFINIX_SAPPHIRE diff --git a/soc/riscv/efinix_sapphire/Kconfig.soc b/soc/riscv/efinix_sapphire/Kconfig.soc deleted file mode 100644 index 4bad3b5cb79..00000000000 --- a/soc/riscv/efinix_sapphire/Kconfig.soc +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Efinix Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_EFINIX_SAPPHIRE - bool "Efinix Sapphire VexRiscv system implementation" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC diff --git a/soc/riscv/espressif_esp32/CMakeLists.txt b/soc/riscv/espressif_esp32/CMakeLists.txt deleted file mode 100644 index 31ef76aadee..00000000000 --- a/soc/riscv/espressif_esp32/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) -add_subdirectory(common) diff --git a/soc/riscv/espressif_esp32/Kconfig b/soc/riscv/espressif_esp32/Kconfig deleted file mode 100644 index 0a6d3f90be9..00000000000 --- a/soc/riscv/espressif_esp32/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ESP32 - bool - -if SOC_FAMILY_ESP32 - -config SOC_FAMILY - string - default "espressif_esp32" - -source "soc/riscv/espressif_esp32/common/Kconfig.soc" -source "soc/riscv/espressif_esp32/*/Kconfig.soc" - -endif # SOC_FAMILY_ESP32 diff --git a/soc/riscv/espressif_esp32/Kconfig.defconfig b/soc/riscv/espressif_esp32/Kconfig.defconfig deleted file mode 100644 index ee9d04c4dab..00000000000 --- a/soc/riscv/espressif_esp32/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/espressif_esp32/common/Kconfig.defconfig.series" -source "soc/riscv/espressif_esp32/*/Kconfig.defconfig.series" diff --git a/soc/riscv/espressif_esp32/Kconfig.soc b/soc/riscv/espressif_esp32/Kconfig.soc deleted file mode 100644 index ce15ddcf10e..00000000000 --- a/soc/riscv/espressif_esp32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/espressif_esp32/*/Kconfig.series" diff --git a/soc/riscv/espressif_esp32/common/CMakeLists.txt b/soc/riscv/espressif_esp32/common/CMakeLists.txt deleted file mode 100644 index 9edbe85c821..00000000000 --- a/soc/riscv/espressif_esp32/common/CMakeLists.txt +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 diff --git a/soc/riscv/espressif_esp32/common/Kconfig.defconfig.series b/soc/riscv/espressif_esp32/common/Kconfig.defconfig.series deleted file mode 100644 index a0a4b4f4943..00000000000 --- a/soc/riscv/espressif_esp32/common/Kconfig.defconfig.series +++ /dev/null @@ -1,52 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_ESP32 - -config GEN_ISR_TABLES - default y - -config GEN_SW_ISR_TABLE - default y - -config GEN_IRQ_VECTOR_TABLE - default n - -config DYNAMIC_INTERRUPTS - default y - -config ISR_STACK_SIZE - default 2048 - -config ATOMIC_OPERATIONS_C - default y - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 16000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config CLOCK_CONTROL - default y - -if BOOTLOADER_MCUBOOT - - config HAS_FLASH_LOAD_OFFSET - default y - config MCUBOOT_GENERATE_UNSIGNED_IMAGE - default y - config MCUBOOT_GENERATE_CONFIRMED_IMAGE - default y - config ROM_START_OFFSET - default 0x20 - -endif # BOOTLOADER_MCUBOOT config - -endif # SOC_FAMILY_ESP32 diff --git a/soc/riscv/espressif_esp32/common/Kconfig.soc b/soc/riscv/espressif_esp32/common/Kconfig.soc deleted file mode 100644 index 5eb40f3b340..00000000000 --- a/soc/riscv/espressif_esp32/common/Kconfig.soc +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_ESP32 - -config ESPTOOLPY_FLASHFREQ_80M - bool - -config FLASH_SIZE - int - -config FLASH_BASE_ADDRESS - hex - -endif # SOC_FAMILY_ESP32 diff --git a/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt b/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt deleted file mode 100644 index d6772eacbfc..00000000000 --- a/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt +++ /dev/null @@ -1,101 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - vectors.S - soc_irq.S - soc_irq.c - soc.c - loader.c - ) - -zephyr_library_sources_ifdef(CONFIG_PM power.c) -zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -# get code-partition slot0 address -dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") -dt_reg_addr(img_0_off PATH ${dts_partition_path}) - -# get code-partition boot address -dt_nodelabel(dts_partition_path NODELABEL "boot_partition") -dt_reg_addr(boot_off PATH ${dts_partition_path}) - -# get flash size to use in esptool as string -math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") - -if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") - -endif() - -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py - ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) - endif() - - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - -endif() - -board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") - -board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") - -if(CONFIG_MCUBOOT) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") -else() - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") -endif() diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series b/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series deleted file mode 100644 index 50d52b3f5bf..00000000000 --- a/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32C3 - -config SOC_SERIES - default "esp32c3" - -config NUM_IRQS - default 62 - -config ESPTOOLPY_FLASHFREQ_80M - default y - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) - -endif # SOC_SERIES_ESP32C3 diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.series b/soc/riscv/espressif_esp32/esp32c3/Kconfig.series deleted file mode 100644 index 2b845a3f057..00000000000 --- a/soc/riscv/espressif_esp32/esp32c3/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ESP32C3 - bool "ESP32C3" - select RISCV - select RISCV_GP - select DYNAMIC_INTERRUPTS - select CLOCK_CONTROL - select PINCTRL - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select HAS_ESPRESSIF_HAL - select SOC_FAMILY_ESP32 - select XIP if !MCUBOOT - select HAS_PM - select HAS_POWEROFF - help - Enable support for Espressif ESP32-C3 diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.soc b/soc/riscv/espressif_esp32/esp32c3/Kconfig.soc deleted file mode 100644 index 66a6e918f31..00000000000 --- a/soc/riscv/espressif_esp32/esp32c3/Kconfig.soc +++ /dev/null @@ -1,99 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32C3 - -config IDF_TARGET_ESP32C3 - bool "ESP32C3 as target board" - default y - -choice SOC_PART_NUMBER - prompt "ESP32-C3 SOC Selection" - depends on SOC_SERIES_ESP32C3 - - config SOC_ESP32C3 - bool "ESP32C3" - config SOC_ESP32C3_FX4 - bool "ESP32C3_FX4" - config SOC_ESP32C3_MINI_N4 - bool "ESP32C3_MINI_N4" - config SOC_ESP32C3_WROOM_02_N4 - bool "ESP32C3_WROOM_02_N4" - config SOC_ESP32C3_WROOM_02_N8 - bool "ESP32C3_WROOM_02_N8" - -endchoice # SOC_PART_NUMBER - -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - -choice ESP32C3_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32C3_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - -config ESP32C3_RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - -config ESP32C3_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32C3_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XP pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32C3_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" - -endchoice # ESP32C3_RTC_CLK_SRC - -config ESP32C3_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32C3_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32C3_RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -config ESP32_PHY_MAX_WIFI_TX_POWER - int "Max WiFi TX power (dBm)" - range 10 20 - default 20 - help - Set maximum transmit power for WiFi radio. Actual transmit power for high - data rates may be lower than this setting. - -config ESP32_PHY_MAX_TX_POWER - int - default ESP32_PHY_MAX_WIFI_TX_POWER - -config MAC_BB_PD - bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled" - depends on SOC_SERIES_ESP32C3 && TICKLESS_KERNEL - default n - help - If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered - down when PHY is disabled. Enabling this setting reduces power consumption - by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only), - 2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth). - -endif # SOC_SERIES_ESP32C3 diff --git a/soc/riscv/gd_gd32/Kconfig b/soc/riscv/gd_gd32/Kconfig deleted file mode 100644 index 46f2dd0b1d6..00000000000 --- a/soc/riscv/gd_gd32/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_GD32 - bool - -if SOC_FAMILY_GD32 - -config SOC_FAMILY - string - default "gd_gd32" - -source "soc/riscv/gd_gd32/*/Kconfig.soc" - -endif # SOC_FAMILY_GIGADEVICE_GD32 diff --git a/soc/riscv/gd_gd32/Kconfig.defconfig b/soc/riscv/gd_gd32/Kconfig.defconfig deleted file mode 100644 index 2be284db7ea..00000000000 --- a/soc/riscv/gd_gd32/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/gd_gd32/*/Kconfig.defconfig.series" diff --git a/soc/riscv/gd_gd32/Kconfig.soc b/soc/riscv/gd_gd32/Kconfig.soc deleted file mode 100644 index 09d7d5d627e..00000000000 --- a/soc/riscv/gd_gd32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/gd_gd32/*/Kconfig.series" diff --git a/soc/riscv/gd_gd32/gd32vf103/CMakeLists.txt b/soc/riscv/gd_gd32/gd32vf103/CMakeLists.txt deleted file mode 100644 index 9fa5868a2a6..00000000000 --- a/soc/riscv/gd_gd32/gd32vf103/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Tokita, Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(entry.S) -zephyr_sources(soc.c) - -zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.series b/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.series deleted file mode 100644 index 17ab7a87c39..00000000000 --- a/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 Tokita, Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32VF103 - -source "soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103*" - -config SOC_SERIES - default "gd32vf103" - -endif # SOC_SERIES_GD32VF103 diff --git a/soc/riscv/gd_gd32/gd32vf103/Kconfig.series b/soc/riscv/gd_gd32/gd32vf103/Kconfig.series deleted file mode 100644 index e50567e0798..00000000000 --- a/soc/riscv/gd_gd32/gd32vf103/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# GD32VF103 SOC implementation - -# Copyright (c) 2021 Tokita, Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32VF103 - bool "GigaDevice GD32VF103 series SoC implementation" - select RISCV - select RISCV_PRIVILEGED - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select BUILD_OUTPUT_HEX - select XIP - select GD32_HAS_AFIO_PINMUX - select GD32_HAS_IRC_40K - select HAS_GD32_HAL - select RISCV_HAS_CLIC - select SOC_FAMILY_GD32 - help - Enable support for GigaDevice GD32VF1 series SoC diff --git a/soc/riscv/gd_gd32/gd32vf103/Kconfig.soc b/soc/riscv/gd_gd32/gd32vf103/Kconfig.soc deleted file mode 100644 index a2da5540e41..00000000000 --- a/soc/riscv/gd_gd32/gd32vf103/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# GD32VF103 SOC configuration options - -# Copyright (c) 2021 Tokita, Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32VF103 SOC implementation" - depends on SOC_SERIES_GD32VF103 - -config SOC_GD32VF103 - bool "GD32VF103" - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/gd_gd32/gd32vf103/pinctrl_soc.h b/soc/riscv/gd_gd32/gd32vf103/pinctrl_soc.h deleted file mode 100644 index 7d703caa97a..00000000000 --- a/soc/riscv/gd_gd32/gd32vf103/pinctrl_soc.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2021 Tokita, Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * Gigadevice SoC specific helpers for pinctrl driver - */ - -#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_ -#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_ - -#include - -#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/riscv/intel_niosv/Kconfig b/soc/riscv/intel_niosv/Kconfig deleted file mode 100644 index b841d19c922..00000000000 --- a/soc/riscv/intel_niosv/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_INTEL_NIOSV - bool - -if SOC_FAMILY_INTEL_NIOSV - -config SOC_FAMILY - string - default "intel_niosv" - -source "soc/riscv/intel_niosv/*/Kconfig.soc" - -endif # SOC_FAMILY_INTEL_NIOSV diff --git a/soc/riscv/intel_niosv/Kconfig.defconfig b/soc/riscv/intel_niosv/Kconfig.defconfig deleted file mode 100644 index 2afa0f7e0e6..00000000000 --- a/soc/riscv/intel_niosv/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/intel_niosv/*/Kconfig.defconfig.series" diff --git a/soc/riscv/intel_niosv/Kconfig.soc b/soc/riscv/intel_niosv/Kconfig.soc deleted file mode 100644 index 8567429c61f..00000000000 --- a/soc/riscv/intel_niosv/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/intel_niosv/*/Kconfig.series" diff --git a/soc/riscv/intel_niosv/niosv/Kconfig.defconfig.series b/soc/riscv/intel_niosv/niosv/Kconfig.defconfig.series deleted file mode 100644 index 15e98314c89..00000000000 --- a/soc/riscv/intel_niosv/niosv/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NIOSV - -config SOC_SERIES - default "niosv" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config NUM_IRQS # Platform interrupts IRQs index start from index 16 - default 32 - -config RISCV_GP - default y - -config RISCV_SOC_INTERRUPT_INIT - default y - -endif # SOC_NIOSV diff --git a/soc/riscv/intel_niosv/niosv/Kconfig.series b/soc/riscv/intel_niosv/niosv/Kconfig.series deleted file mode 100644 index 9d7aa492692..00000000000 --- a/soc/riscv/intel_niosv/niosv/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NIOSV - bool "INTEL FPGA NIOSV" - select RISCV - select RISCV_PRIVILEGED - select SOC_FAMILY_INTEL_NIOSV - help - Enable support for the INTEL FPGA NIOSV. diff --git a/soc/riscv/intel_niosv/niosv/Kconfig.soc b/soc/riscv/intel_niosv/niosv/Kconfig.soc deleted file mode 100644 index 67da5ccee38..00000000000 --- a/soc/riscv/intel_niosv/niosv/Kconfig.soc +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "FPGA NIOSV" - depends on SOC_SERIES_NIOSV - -config SOC_NIOSV_M - bool "Intel FPGA NIOSV Microcontroller Core Processor" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config SOC_NIOSV_G - bool "Intel FPGA NIOSV General Purpose Processor" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/ite_ec/Kconfig b/soc/riscv/ite_ec/Kconfig deleted file mode 100644 index 54628029a4e..00000000000 --- a/soc/riscv/ite_ec/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ITE_EC - bool - help - ITE Embedded Controller SoC family - -if SOC_FAMILY_ITE_EC - -config SOC_FAMILY - string - default "ite_ec" - -source "soc/riscv/ite_ec/*/Kconfig.soc" - -endif # SOC_FAMILY_ITE_EC diff --git a/soc/riscv/ite_ec/Kconfig.defconfig b/soc/riscv/ite_ec/Kconfig.defconfig deleted file mode 100644 index 8994f47abd9..00000000000 --- a/soc/riscv/ite_ec/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/ite_ec/*/Kconfig.defconfig.series" diff --git a/soc/riscv/ite_ec/Kconfig.soc b/soc/riscv/ite_ec/Kconfig.soc deleted file mode 100644 index 13f951c0466..00000000000 --- a/soc/riscv/ite_ec/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/ite_ec/*/Kconfig.series" diff --git a/soc/riscv/ite_ec/it8xxx2/CMakeLists.txt b/soc/riscv/ite_ec/it8xxx2/CMakeLists.txt deleted file mode 100644 index df4d9021745..00000000000 --- a/soc/riscv/ite_ec/it8xxx2/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -zephyr_sources( - soc.c -) -zephyr_library_sources_ifndef(CONFIG_RISCV_ISA_EXT_M __arithmetic.S) -zephyr_sources_ifdef(CONFIG_SOC_IT8XXX2_USE_ILM ilm.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld - CACHE INTERNAL "SoC Linker script ${SOC_NAME}" -) diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82302ax b/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82302ax deleted file mode 100644 index 9dd33cc00ec..00000000000 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82302ax +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 ITE Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_IT82302_AX - -config SOC - default "it82302ax" - -endif diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.series b/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.series deleted file mode 100644 index 0ed7358b631..00000000000 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.series +++ /dev/null @@ -1,59 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ITE_IT8XXX2 - -config SOC_SERIES - default "it8xxx2" - -config RISCV_GP - default y - -config ARCH_HAS_CUSTOM_BUSY_WAIT - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 4096 - -config UART_NS16550_WA_ISR_REENABLE_INTERRUPT - default y - depends on UART_NS16550 - -config FLASH_INIT_PRIORITY - default 0 - -config IT8XXX2_PLL_SEQUENCE_PRIORITY - int - default 1 - depends on SOC_IT8XXX2_PLL_FLASH_48M - -config VCMP_IT8XXX2_INIT_PRIORITY - default 91 if VCMP_IT8XXX2_WORKQUEUE - -config PINCTRL - default y - -config NUM_IRQS - default 185 - -config DYNAMIC_INTERRUPTS - default y - -config GEN_ISR_TABLES - default y - -config GEN_IRQ_START_VECTOR - default 0 - -config GEN_SW_ISR_TABLE - default y - -config RISCV_SOC_INTERRUPT_INIT - default y - -source "soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it8*" - -endif # SOC_SERIES_ITE_IT8XXX2 diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.series b/soc/riscv/ite_ec/it8xxx2/Kconfig.series deleted file mode 100644 index 265bf855f12..00000000000 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ITE_IT8XXX2 - bool "ITE IT8XXX2 implementation" - #depends on RISCV - # RV32IAFC is an uncommon configuration which is not supported by - # default in most toolchains, causing link-time errors. - select CPU_HAS_FPU if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M - select SOC_FAMILY_ITE_EC - select HAS_PM - help - Enable support for ITE IT8XXX2 diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.soc b/soc/riscv/ite_ec/it8xxx2/Kconfig.soc deleted file mode 100644 index d918318dfaa..00000000000 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.soc +++ /dev/null @@ -1,173 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "ITE IT8XXX2 system implementation" -depends on SOC_SERIES_ITE_IT8XXX2 - -config SOC_IT8XXX2 - bool "ITE IT8XXX2 system implementation" - select RISCV - select ATOMIC_OPERATIONS_BUILTIN - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - # Workaround mul instruction bug, see: - # https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf - select RISCV_ISA_EXT_M if !(SOC_IT81302_BX || SOC_IT81202_BX) - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select FLASH - select FLASH_HAS_PAGE_LAYOUT - select FLASH_HAS_DRIVER_ENABLED - select HAS_FLASH_LOAD_OFFSET - -endchoice - -config SOC_IT8XXX2_REG_SET_V1 - bool - help - This option is selected by a variable of which soc, and will - determine the register for the IT81xx2 specification. - -config SOC_IT8XXX2_REG_SET_V2 - bool - help - This option is selected by a variable of which soc, and will - determine the register for the IT82xx2 specification. - -if SOC_IT8XXX2 - -choice IT8XXX2_SERIES - prompt "IT8XXX2 Series" - default SOC_IT81302_BX - -config SOC_IT81302_BX - bool "IT81302 BX version" - select SOC_IT8XXX2_REG_SET_V1 - -config SOC_IT81202_BX - bool "IT81202 BX version" - select SOC_IT8XXX2_REG_SET_V1 - -config SOC_IT81302_CX - bool "IT81302 CX version" - select SOC_IT8XXX2_REG_SET_V1 - -config SOC_IT81202_CX - bool "IT81202 CX version" - select SOC_IT8XXX2_REG_SET_V1 - -config SOC_IT82202_AX - bool "IT82202 AX version" - select SOC_IT8XXX2_REG_SET_V2 - select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED - -config SOC_IT82302_AX - bool "IT82302 AX version" - select SOC_IT8XXX2_REG_SET_V2 - select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED - -config SOC_IT82002_AW - bool "IT82002 AW version" - select SOC_IT8XXX2_REG_SET_V2 - select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED - -endchoice - -config SOC_IT8XXX2_PLL_FLASH_48M - bool "Flash frequency is 48MHz" - default y - help - Change frequency of PLL, CPU, and flash to 48MHz during initialization. - - Set n to use the default settings. - (PLL and CPU run at 48MHz, flash frequency is 16MHz) - -config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN - bool "The pins of GPIO group K and L aren't bonding with pad" - default y - help - On IT81202 (128-pins package), the pins of GPIO group K and L aren't - bonding with pad. So we configure these pins as internal pull-down - at default to prevent leakage current due to floating. - -config SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW - bool "The GPIOH7 isn't bonding with pad and is left floating internally" - default y - help - On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left - floating internally. We need to enable internal pull-down for the pin - to prevent leakage current, but IT81202/IT81302 doesn't have the - capability to pull it down. We can only set it as output low, - so we enable output low for it at initialization to prevent leakage. - -config SOC_IT8XXX2_CPU_IDLE_GATING - bool - help - This option determines whether the entering CPU idle mode can be - gated by individual drivers. When this option is disabled, CPU idle - mode is always permitted. - -config SOC_IT8XXX2_EC_BUS_24MHZ - bool "EC bus is 24MHz" - help - Raise EC bus to 24MHz (default is 8MHz). - This reduces read/write EC registers latency by 50%. - NOTE: There is limitation to enabling this config on it81xx2 series. - The clock_frequency of ite,it8xxx2-i2c node (i2c0, i2c1, and i2c2) will - be fixed at 400KHz. - -choice - prompt "Clock source for PLL reference clock" - -config SOC_IT8XXX2_INT_32K - bool "Use the +/-2.3% internal clock generator" - -config SOC_IT8XXX2_EXT_32K - bool "Use external 32.768 kHz clock source" - -endchoice - -config SOC_IT8XXX2_USE_ILM - bool - default y - help - If enabled, Instruction Local Memory (ILM) will be configured to execute - code placed in the .__ram_code section out of RAM. This consumes RAM in - blocks of 4 kilobytes, but performance of code in ILM is much more - predictable than executing from Flash directly, and some code (such as code - that writes to the internal Flash) must execute out of RAM. - -config SOC_IT8XXX2_EXCEPTIONS_IN_RAM - bool "Place exception handling code in RAM" - default y - select SOC_IT8XXX2_USE_ILM - help - Place exception handling (ISR entry/exit and related) code in ILM, which - has more reliable performance characteristics than executing directly from - Flash. This can significantly improve performance when under I-cache - pressure. - -config SOC_IT8XXX2_SHA256_HW_ACCELERATE - bool "HW SHA256 calculation" - help - IT8XXX2 HW support sha256 calculation, and its calculation is faster than FW. - We place SHA256 message, hash and key data (total 512bytes) in RAM. - If we enable this config, because HW limits, the sha256 data must place in - first 4KB of RAM. - -DT_CHOSEN_ZEPHYR_FLASH := zephyr,flash - -config SOC_IT8XXX2_FLASH_SIZE_BYTES - hex - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_ZEPHYR_FLASH)) - help - Total size of writable flash. - -config ILM_MAX_SIZE - int "ILM Size in kB" - default 60 if SOC_IT81202_CX || SOC_IT81302_CX - default SRAM_SIZE - -endif # SOC_IT8XXX2 diff --git a/soc/riscv/litex_vexriscv/CMakeLists.txt b/soc/riscv/litex_vexriscv/CMakeLists.txt deleted file mode 100644 index 98386f6b57a..00000000000 --- a/soc/riscv/litex_vexriscv/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2018 - 2019 Antmicro -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - ../common/riscv-privileged/soc_irq.S - ../common/riscv-privileged/vector.S -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/litex_vexriscv/Kconfig.defconfig b/soc/riscv/litex_vexriscv/Kconfig.defconfig deleted file mode 100644 index 0088420459f..00000000000 --- a/soc/riscv/litex_vexriscv/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2018 - 2019 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_RISCV32_LITEX_VEXRISCV - -config SOC - default "litex_vexriscv" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config NUM_IRQS - default 12 - -endif # SOC_RISCV32_LITEX_VEXRISCV diff --git a/soc/riscv/litex_vexriscv/Kconfig.soc b/soc/riscv/litex_vexriscv/Kconfig.soc deleted file mode 100644 index a7e632e3afd..00000000000 --- a/soc/riscv/litex_vexriscv/Kconfig.soc +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2018 - 2019 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RISCV32_LITEX_VEXRISCV - bool "LiteX VexRiscv system implementation" - select RISCV - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -if SOC_RISCV32_LITEX_VEXRISCV - -config LITEX_CSR_DATA_WIDTH - int "Select Control/Status register width" - default 32 - -endif # SOC_RISCV32_LITEX_VEXRISCV diff --git a/soc/riscv/microchip_miv/CMakeLists.txt b/soc/riscv/microchip_miv/CMakeLists.txt deleted file mode 100644 index 69b2926358e..00000000000 --- a/soc/riscv/microchip_miv/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/riscv/microchip_miv/Kconfig b/soc/riscv/microchip_miv/Kconfig deleted file mode 100644 index 46616636aa1..00000000000 --- a/soc/riscv/microchip_miv/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_MICROCHIP_MIV - bool - -if SOC_FAMILY_MICROCHIP_MIV - -config SOC_FAMILY - string - default "microchip_miv" - -source "soc/riscv/microchip_miv/*/Kconfig.soc" - -endif # SOC_FAMILY_MICROCHIP_MIV diff --git a/soc/riscv/microchip_miv/Kconfig.defconfig b/soc/riscv/microchip_miv/Kconfig.defconfig deleted file mode 100644 index 2fe508bddba..00000000000 --- a/soc/riscv/microchip_miv/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/microchip_miv/*/Kconfig.defconfig.series" diff --git a/soc/riscv/microchip_miv/Kconfig.soc b/soc/riscv/microchip_miv/Kconfig.soc deleted file mode 100644 index 8677f1ba448..00000000000 --- a/soc/riscv/microchip_miv/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/microchip_miv/*/Kconfig.series" diff --git a/soc/riscv/microchip_miv/miv/Kconfig.defconfig.series b/soc/riscv/microchip_miv/miv/Kconfig.defconfig.series deleted file mode 100644 index 35f4365b02b..00000000000 --- a/soc/riscv/microchip_miv/miv/Kconfig.defconfig.series +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MIV - -config SOC_SERIES - default "miv" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 4000000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 30 - -config NUM_IRQS - default 42 - -endif # SOC_SERIES_MIV diff --git a/soc/riscv/microchip_miv/miv/Kconfig.series b/soc/riscv/microchip_miv/miv/Kconfig.series deleted file mode 100644 index 9f348619624..00000000000 --- a/soc/riscv/microchip_miv/miv/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV32_MIV implementation - -# Copyright (c) 2018 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MIV - bool "Microchip Mi-V implementation" - select SOC_FAMILY_MICROCHIP_MIV - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - help - Enable support for Microchip Mi-V diff --git a/soc/riscv/microchip_miv/miv/Kconfig.soc b/soc/riscv/microchip_miv/miv/Kconfig.soc deleted file mode 100644 index 0a48c2e0524..00000000000 --- a/soc/riscv/microchip_miv/miv/Kconfig.soc +++ /dev/null @@ -1,20 +0,0 @@ -# RISCV32_MIV configuration options - -# Copyright (c) 2018 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Microchip Mi-V system implementation" - depends on SOC_SERIES_MIV - -config SOC_MIV - bool "Microchip Mi-V system implementation" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/microchip_miv/polarfire/CMakeLists.txt b/soc/riscv/microchip_miv/polarfire/CMakeLists.txt deleted file mode 100644 index 316f08474ba..00000000000 --- a/soc/riscv/microchip_miv/polarfire/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/microchip_miv/polarfire/Kconfig.defconfig.series b/soc/riscv/microchip_miv/polarfire/Kconfig.defconfig.series deleted file mode 100644 index 53e88f1096e..00000000000 --- a/soc/riscv/microchip_miv/polarfire/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2020-2021 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_POLARFIRE - -config SOC_SERIES - default "polarfire" - -# MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock... - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 13 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 186 - -config NUM_IRQS - default 186 - -endif # SOC_SERIES_POLARFIRE diff --git a/soc/riscv/microchip_miv/polarfire/Kconfig.series b/soc/riscv/microchip_miv/polarfire/Kconfig.series deleted file mode 100644 index 59ec4dbdd7a..00000000000 --- a/soc/riscv/microchip_miv/polarfire/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV64_MIV implementation - -# Copyright (c) 2018 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_POLARFIRE - bool "Microchip RV64 implementation" - select SOC_FAMILY_MICROCHIP_MIV - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - help - Enable support for Microchip RISCV 64bit diff --git a/soc/riscv/microchip_miv/polarfire/Kconfig.soc b/soc/riscv/microchip_miv/polarfire/Kconfig.soc deleted file mode 100644 index 101e8b4d029..00000000000 --- a/soc/riscv/microchip_miv/polarfire/Kconfig.soc +++ /dev/null @@ -1,30 +0,0 @@ -# RISCV64_MIV Microchip Polarfire SOC configuration options - -# Copyright (c) 2020-2021 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Microchip Polarfire SOC implementation" - depends on SOC_SERIES_POLARFIRE - -config SOC_POLARFIRE - bool "Microchip MPFS system implementation" - select ATOMIC_OPERATIONS_BUILTIN - select RISCV_GP - select USE_SWITCH_SUPPORTED - select USE_SWITCH - select CPU_HAS_FPU - select SCHED_IPI_SUPPORTED - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice - -config MPFS_HAL - depends on SOC_POLARFIRE - bool "Microchip Polarfire SOC hardware abstracton layer" - select HAS_MPFS_HAL diff --git a/soc/riscv/neorv32/Kconfig.defconfig b/soc/riscv/neorv32/Kconfig.defconfig deleted file mode 100644 index bc37ea74727..00000000000 --- a/soc/riscv/neorv32/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NEORV32 - -config SOC - default "neorv32" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if RISCV_MACHINE_TIMER - -config NUM_IRQS - default 32 - -config RISCV_GP - default y - -config SYSCON - default y - -config SERIAL_INIT_PRIORITY - default 55 - depends on SERIAL - -config ENTROPY_INIT_PRIORITY - default 55 - depends on ENTROPY_GENERATOR - -endif # SOC_NEORV32 diff --git a/soc/riscv/neorv32/Kconfig.soc b/soc/riscv/neorv32/Kconfig.soc deleted file mode 100644 index 3155d1b7c31..00000000000 --- a/soc/riscv/neorv32/Kconfig.soc +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NEORV32 - bool "NEORV32 Processor" - select RISCV - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_PRIVILEGED - help - Enable support for the NEORV32 Processor (SoC). - - The NEORV32 CPU implementation must have the following RISC-V ISA - extensions enabled in order to support Zephyr: - - M (Integer Multiplication and Division) - - Zicsr (Control and Status Register (CSR) Instructions) - - The following NEORV32 CPU ISA extensions are not currently supported - by Zephyr and can safely be disabled: - - A (Atomic Instructions) - - E (Embedded, only 16 integer registers) - - Zbb (Basic Bit Manipulation) - - Zfinx (Floating Point in Integer Registers) - -if SOC_NEORV32 - -config SOC_NEORV32_V1_8_6 - bool "v1.8.6" - # NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO - select ATOMIC_OPERATIONS_C - -config SOC_NEORV32_VERSION - hex - default 0x01080600 if SOC_NEORV32_V1_8_6 - help - The targeted NEORV32 version as BCD-coded number. The format is - identical to that of the NEORV32 Machine implementation ID (mimpid) - register. - -config SOC_NEORV32_ISA_C - bool "RISC-V ISA Extension \"C\"" - select RISCV_ISA_EXT_C - help - Enable this if the NEORV32 CPU implementation supports the RISC-V ISA - "C" extension (Compressed Instructions). - -endif # SOC_NEORV32 diff --git a/soc/riscv/nordic_nrf/Kconfig b/soc/riscv/nordic_nrf/Kconfig deleted file mode 100644 index a39db4671d5..00000000000 --- a/soc/riscv/nordic_nrf/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_NRF - bool - -if SOC_FAMILY_NRF - -config SOC_FAMILY - string - default "nordic_nrf" - -source "soc/riscv/nordic_nrf/common/Kconfig" - -source "soc/common/nordic_nrf/Kconfig.peripherals" -source "soc/riscv/nordic_nrf/*/Kconfig.soc" - -endif # SOC_FAMILY_NRF diff --git a/soc/riscv/nordic_nrf/Kconfig.defconfig b/soc/riscv/nordic_nrf/Kconfig.defconfig deleted file mode 100644 index cc3ec954985..00000000000 --- a/soc/riscv/nordic_nrf/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_NRF - -source "soc/riscv/nordic_nrf/*/Kconfig.defconfig.series" -source "soc/riscv/nordic_nrf/common/Kconfig.defconfig" - -config BUILD_OUTPUT_HEX - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 if NRF_GRTC_TIMER - default 32768 if NRF_RTC_TIMER - -endif # SOC_FAMILY_NRF diff --git a/soc/riscv/nordic_nrf/Kconfig.soc b/soc/riscv/nordic_nrf/Kconfig.soc deleted file mode 100644 index 593d6f91769..00000000000 --- a/soc/riscv/nordic_nrf/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/nordic_nrf/*/Kconfig.series" diff --git a/soc/riscv/nordic_nrf/common/CMakeLists.txt b/soc/riscv/nordic_nrf/common/CMakeLists.txt deleted file mode 100644 index 806a295ea22..00000000000 --- a/soc/riscv/nordic_nrf/common/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr) diff --git a/soc/riscv/nordic_nrf/common/Kconfig b/soc/riscv/nordic_nrf/common/Kconfig deleted file mode 100644 index 610689ecc6d..00000000000 --- a/soc/riscv/nordic_nrf/common/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/nordic_nrf/common/vpr/Kconfig" diff --git a/soc/riscv/nordic_nrf/common/Kconfig.defconfig b/soc/riscv/nordic_nrf/common/Kconfig.defconfig deleted file mode 100644 index 9beb943edb8..00000000000 --- a/soc/riscv/nordic_nrf/common/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if RISCV_CORE_NORDIC_VPR - -source "soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig" - -endif # RISCV_CORE_NORDIC_VPR diff --git a/soc/riscv/nordic_nrf/common/vpr/CMakeLists.txt b/soc/riscv/nordic_nrf/common/vpr/CMakeLists.txt deleted file mode 100644 index e0331bb8e0b..00000000000 --- a/soc/riscv/nordic_nrf/common/vpr/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) - -zephyr_library() -zephyr_library_sources(soc_irq.S soc_irq.c vector.S) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/nordic_nrf/nrf54h/CMakeLists.txt b/soc/riscv/nordic_nrf/nrf54h/CMakeLists.txt deleted file mode 100644 index 5b37b3a54d8..00000000000 --- a/soc/riscv/nordic_nrf/nrf54h/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes -# for the image correctly -zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld) diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.series b/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.series deleted file mode 100644 index 0f827fbe96b..00000000000 --- a/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF54HX - -rsource "Kconfig.defconfig.nrf54h*" - -config SOC_SERIES - default "nrf54h" - -DT_CHOSEN_Z_SRAM = zephyr,sram -DT_CHOSEN_Z_CODE = zephyr,code-partition - -config BUILD_OUTPUT_ADJUST_LMA - depends on !XIP - default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_Z_CODE)) - \ - $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))" - -endif # SOC_SERIES_NRF54HX diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.series b/soc/riscv/nordic_nrf/nrf54h/Kconfig.series deleted file mode 100644 index acb85b5623a..00000000000 --- a/soc/riscv/nordic_nrf/nrf54h/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF54HX - bool "Nordic Semiconductor nRF54H series MCU" - select SOC_FAMILY_NRF - select HAS_NRFX - select HAS_NORDIC_DRIVERS - help - Enable support for nRF54H MCU series diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc b/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc deleted file mode 100644 index 760e05a0e64..00000000000 --- a/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NRF54H20 - bool "nRF54H20" - depends on SOC_SERIES_NRF54HX - -if SOC_NRF54H20 - -choice - prompt "nRF54Hx MCU Selection" - -config SOC_NRF54H20_ENGA_CPUPPR - bool "nRF54H20 ENGA CPUPPR" - depends on RISCV_CORE_NORDIC_VPR - -endchoice - -endif # SOC_NRF54H20 diff --git a/soc/riscv/nordic_nrf/nrf54h/align.ld b/soc/riscv/nordic_nrf/nrf54h/align.ld deleted file mode 100644 index 0905aa7f7bc..00000000000 --- a/soc/riscv/nordic_nrf/nrf54h/align.ld +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA. - * SPDX-License-Identifier: Apache-2.0 - */ - -SECTION_PROLOGUE(.align16,,) -{ - . = (ALIGN(16) > 0 ? ALIGN(16) : 16) - 1; - BYTE(0); -} GROUP_LINK_IN(ROMABLE_REGION) diff --git a/soc/riscv/openisa_rv32m1/CMakeLists.txt b/soc/riscv/openisa_rv32m1/CMakeLists.txt deleted file mode 100644 index a7a722279c3..00000000000 --- a/soc/riscv/openisa_rv32m1/CMakeLists.txt +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2018 Foundries.io Ltd -# -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_SOC_OPENISA_RV32M1_RI5CY) - if (CONFIG_RISCV_GENERIC_TOOLCHAIN) - zephyr_compile_options(-march=rv32imc_zicsr_zifencei) - else() - zephyr_compile_options(-march=rv32imcxpulpv2) - endif() -elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY) - zephyr_compile_options(-march=rv32imc_zicsr_zifencei) -endif() - -zephyr_sources( - vector.S - soc_irq.S - wdog.S - soc.c -) - -zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/openisa_rv32m1/Kconfig b/soc/riscv/openisa_rv32m1/Kconfig deleted file mode 100644 index b9dc0e55f11..00000000000 --- a/soc/riscv/openisa_rv32m1/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2018 Foundries.io Ltd -# SPDX-License-Identifier: Apache-2.0 - -# The OpenISA RV32M1 SoC directory in riscv supports the RISC-V -# cores on OpenISA RV32M1 SoCs. -# -# The Zephyr "soc" abstraction isn't a great fit here. These SoCs (in -# the strict physical sense of "systems on chip") also contain Arm -# cores, so this type of "soc" doesn't really belong to a single "arch". -# -# However, due to constraints imposed by Zephyr's file hierarchy -# conventions, those "other" cores would need to be supported under a -# different soc subdirectory, e.g. soc/arm instead of soc/riscv. - -choice - prompt "OpenISA RV32M1 RISC-V Core Selection" - depends on SOC_OPENISA_RV32M1_RISCV32 - -config SOC_OPENISA_RV32M1_RI5CY - bool "OpenISA RV32M1 RI5CY core" - -config SOC_OPENISA_RV32M1_ZERO_RISCY - bool "OpenISA RV32M1 ZERO-RISCY core" - -endchoice diff --git a/soc/riscv/openisa_rv32m1/Kconfig.defconfig b/soc/riscv/openisa_rv32m1/Kconfig.defconfig deleted file mode 100644 index 52d652a061e..00000000000 --- a/soc/riscv/openisa_rv32m1/Kconfig.defconfig +++ /dev/null @@ -1,125 +0,0 @@ -# RV32M1 SoC RISC-V core default configuration values - -# Copyright (c) 2018 Foundries.io Ltd -# SPDX-License-Identifier: Apache-2.0 - -if SOC_OPENISA_RV32M1_RISCV32 - -config SOC - default "openisa_rv32m1" - -# 32 from event unit + 32 * (1 + max enabled INTMUX channel) -config NUM_IRQS - default 288 if RV32M1_INTMUX_CHANNEL_7 - default 256 if RV32M1_INTMUX_CHANNEL_6 - default 224 if RV32M1_INTMUX_CHANNEL_5 - default 192 if RV32M1_INTMUX_CHANNEL_4 - default 160 if RV32M1_INTMUX_CHANNEL_3 - default 128 if RV32M1_INTMUX_CHANNEL_2 - default 96 if RV32M1_INTMUX_CHANNEL_1 - default 64 if RV32M1_INTMUX_CHANNEL_0 - default 32 - -config RISCV_GENERIC_TOOLCHAIN - default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" - default n - -config RISCV_SOC_CONTEXT_SAVE - default y if SOC_OPENISA_RV32M1_RI5CY - -config RISCV_SOC_OFFSETS - default y - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_MCAUSE_EXCEPTION_MASK - default 0x1F - -# We need to disable the watchdog out of reset, as it's enabled by -# default. Use the WDOG_INIT hook for doing that. -config WDOG_INIT - def_bool y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 8000000 - -if MULTI_LEVEL_INTERRUPTS - -config MAX_IRQ_PER_AGGREGATOR - default 32 - -config 2ND_LEVEL_INTERRUPTS - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 32 - -config NUM_2ND_LEVEL_AGGREGATORS - default 8 if RV32M1_INTMUX_CHANNEL_7 - default 7 if RV32M1_INTMUX_CHANNEL_6 - default 6 if RV32M1_INTMUX_CHANNEL_5 - default 5 if RV32M1_INTMUX_CHANNEL_4 - default 4 if RV32M1_INTMUX_CHANNEL_3 - default 3 if RV32M1_INTMUX_CHANNEL_2 - default 2 if RV32M1_INTMUX_CHANNEL_1 - default 1 # just channel 0 - -config 2ND_LVL_INTR_00_OFFSET - default 24 - -config 2ND_LVL_INTR_01_OFFSET - int - default 25 - -config 2ND_LVL_INTR_02_OFFSET - int - default 26 - -config 2ND_LVL_INTR_03_OFFSET - int - default 27 - -config 2ND_LVL_INTR_04_OFFSET - int - default 28 - -config 2ND_LVL_INTR_05_OFFSET - int - default 29 - -config 2ND_LVL_INTR_06_OFFSET - int - default 30 - -config 2ND_LVL_INTR_07_OFFSET - int - default 31 - -config RV32M1_INTMUX_CHANNEL_0 - default y - -config RV32M1_INTMUX_CHANNEL_1 - default y - -config RV32M1_INTMUX_CHANNEL_2 - default y - -config RV32M1_INTMUX_CHANNEL_3 - default y - -config RV32M1_INTMUX_CHANNEL_4 - default y - -config RV32M1_INTMUX_CHANNEL_5 - default y - -config RV32M1_INTMUX_CHANNEL_6 - default y - -config RV32M1_INTMUX_CHANNEL_7 - default y - -endif # MULTI_LEVEL_INTERRUPTS - -endif # SOC_OPENISA_RV32M1_RISCV32 diff --git a/soc/riscv/openisa_rv32m1/Kconfig.soc b/soc/riscv/openisa_rv32m1/Kconfig.soc deleted file mode 100644 index c1264e95b46..00000000000 --- a/soc/riscv/openisa_rv32m1/Kconfig.soc +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2018 Foundries.io Ltd -# SPDX-License-Identifier: Apache-2.0 - -config SOC_OPENISA_RV32M1_RISCV32 - bool "OpenISA RV32M1 RISC-V cores" - select RISCV - # The following select is due to limitations in the linker script. - # (We can't make it a 'depends on' without causing a dependency loop). - select XIP - select HAS_RV32M1_LPUART - select HAS_RV32M1_LPI2C - select HAS_RV32M1_LPSPI - select HAS_RV32M1_TPM - select ATOMIC_OPERATIONS_C - select VEGA_SDK_HAL - select RISCV_SOC_INTERRUPT_INIT - select CLOCK_CONTROL - select HAS_RV32M1_FTFX - select HAS_FLASH_LOAD_OFFSET - select BUILD_OUTPUT_HEX - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - help - Enable support for OpenISA RV32M1 RISC-V processors. Choose - this option to target the RI5CY or ZERO-RISCY core. This - option should not be used to target either Arm core. diff --git a/soc/riscv/opentitan/Kconfig.defconfig b/soc/riscv/opentitan/Kconfig.defconfig deleted file mode 100644 index 4b067ef76af..00000000000 --- a/soc/riscv/opentitan/Kconfig.defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright (c) 2023 Rivos Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_OPENTITAN - -config SOC - default "opentitan" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 32 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config NUM_IRQS - default 256 - -endif # SOC_OPENTITAN diff --git a/soc/riscv/opentitan/Kconfig.soc b/soc/riscv/opentitan/Kconfig.soc deleted file mode 100644 index c76cfe013b1..00000000000 --- a/soc/riscv/opentitan/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2023 Rivos Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_OPENTITAN - bool "OpenTitan implementation" - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_ISA_EXT_ZBA - select RISCV_ISA_EXT_ZBB - select RISCV_ISA_EXT_ZBC - select RISCV_ISA_EXT_ZBS - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - # OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode. - select RISCV_VECTORED_MODE - select GEN_IRQ_VECTOR_TABLE diff --git a/soc/riscv/qemu_virt_riscv/CMakeLists.txt b/soc/riscv/qemu_virt_riscv/CMakeLists.txt new file mode 100644 index 00000000000..ce57a74e239 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") +add_subdirectory(common) diff --git a/soc/riscv/qemu_virt_riscv/Kconfig b/soc/riscv/qemu_virt_riscv/Kconfig new file mode 100644 index 00000000000..1c3382371bb --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/Kconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_QEMU_VIRT_RISCV + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + +if SOC_FAMILY_QEMU_VIRT_RISCV + +rsource "*/Kconfig" + +endif # SOC_FAMILY_QEMU_VIRT_RISCV diff --git a/soc/riscv/qemu_virt_riscv/Kconfig.defconfig b/soc/riscv/qemu_virt_riscv/Kconfig.defconfig new file mode 100644 index 00000000000..4eb51b6d889 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/Kconfig.defconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2020 Cobham Gaisler AB +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_QEMU_VIRT_RISCV + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 10000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 52 + +config NUM_IRQS + default 1035 + +config PMP_SLOTS + default 16 + +endif # SOC_FAMILY_QEMU_VIRT_RISCV diff --git a/soc/riscv/qemu_virt_riscv/Kconfig.soc b/soc/riscv/qemu_virt_riscv/Kconfig.soc new file mode 100644 index 00000000000..ba3a1bd5961 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_QEMU_VIRT_RISCV + bool + +config SOC_FAMILY + default "qemu_virt_riscv" if SOC_FAMILY_QEMU_VIRT_RISCV + +rsource "*/Kconfig.soc" diff --git a/soc/riscv/qemu_virt_riscv/common/CMakeLists.txt b/soc/riscv/qemu_virt_riscv/common/CMakeLists.txt new file mode 100644 index 00000000000..77a7ba35d26 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/common/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) diff --git a/soc/riscv/virt/soc.c b/soc/riscv/qemu_virt_riscv/common/soc.c similarity index 100% rename from soc/riscv/virt/soc.c rename to soc/riscv/qemu_virt_riscv/common/soc.c diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig new file mode 100644 index 00000000000..ff49d3fe3ab --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV32 + select CPU_HAS_FPU + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig.soc b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig.soc new file mode 100644 index 00000000000..4b1ee59adc1 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV32 + bool + select SOC_FAMILY_QEMU_VIRT_RISCV + +config SOC + default "qemu_virt_riscv32" if SOC_QEMU_VIRT_RISCV32 diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig new file mode 100644 index 00000000000..9ad39ce22ad --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2020 Cobham Gaisler AB +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV32E + select RISCV_ISA_RV32E + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig.soc b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig.soc new file mode 100644 index 00000000000..38b51ee58ff --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV32E + bool + select SOC_FAMILY_QEMU_VIRT_RISCV + +config SOC + default "qemu_virt_riscv32e" if SOC_QEMU_VIRT_RISCV32E diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig new file mode 100644 index 00000000000..f8560c607f0 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV64 + select 64BIT + select CPU_HAS_FPU_DOUBLE_PRECISION + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig.soc b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig.soc new file mode 100644 index 00000000000..cfcf51103de --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV64 + bool + select SOC_FAMILY_QEMU_VIRT_RISCV + +config SOC + default "qemu_virt_riscv64" if SOC_QEMU_VIRT_RISCV64 diff --git a/soc/riscv/qemu_virt_riscv/soc.yml b/soc/riscv/qemu_virt_riscv/soc.yml new file mode 100644 index 00000000000..746051f76a9 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/soc.yml @@ -0,0 +1,6 @@ +family: +- name: qemu_virt_riscv + socs: + - name: qemu_virt_riscv32 + - name: qemu_virt_riscv32e + - name: qemu_virt_riscv64 diff --git a/soc/riscv/renode_virt/Kconfig.defconfig b/soc/riscv/renode_virt/Kconfig.defconfig deleted file mode 100644 index fab59719595..00000000000 --- a/soc/riscv/renode_virt/Kconfig.defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2023 Meta -# SPDX-License-Identifier: Apache-2.0 - -if SOC_RISCV32_VIRTUAL_RENODE - -config SOC - default "renode_virt" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 4000000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 1ST_LEVEL_INTERRUPT_BITS - default 4 - -config NUM_2ND_LEVEL_AGGREGATORS - default 2 - -config 2ND_LEVEL_INTERRUPT_BITS - default 11 - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config 2ND_LVL_INTR_01_OFFSET - default 4 - -config MAX_IRQ_PER_AGGREGATOR - default 1023 - -config NUM_IRQS - default 2058 - -endif # SOC_RISCV32_VIRTUAL_RENODE diff --git a/soc/riscv/renode_virt/Kconfig.soc b/soc/riscv/renode_virt/Kconfig.soc deleted file mode 100644 index ba42c40c28d..00000000000 --- a/soc/riscv/renode_virt/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2023 Meta -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RISCV32_VIRTUAL_RENODE - bool "Renode RISCV32 Virtual system implementation" - select RISCV - select RISCV_PRIVILEGED - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_HAS_PLIC diff --git a/soc/riscv/sifive_freedom/CMakeLists.txt b/soc/riscv/sifive_freedom/CMakeLists.txt deleted file mode 100644 index 6a5b10545ff..00000000000 --- a/soc/riscv/sifive_freedom/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(common) -add_subdirectory(${SOC_SERIES}) diff --git a/soc/riscv/sifive_freedom/Kconfig b/soc/riscv/sifive_freedom/Kconfig deleted file mode 100644 index 0fed11158af..00000000000 --- a/soc/riscv/sifive_freedom/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_SIFIVE_FREEDOM - bool - -if SOC_FAMILY_SIFIVE_FREEDOM - -config SOC_FAMILY - string - default "sifive_freedom" - -source "soc/riscv/sifive_freedom/*/Kconfig.soc" - -endif # SOC_FAMILY_SIFIVE_FREEDOM diff --git a/soc/riscv/sifive_freedom/Kconfig.defconfig b/soc/riscv/sifive_freedom/Kconfig.defconfig deleted file mode 100644 index 5adf8fc437e..00000000000 --- a/soc/riscv/sifive_freedom/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/sifive_freedom/*/Kconfig.defconfig.series" diff --git a/soc/riscv/sifive_freedom/Kconfig.soc b/soc/riscv/sifive_freedom/Kconfig.soc deleted file mode 100644 index 54274defd91..00000000000 --- a/soc/riscv/sifive_freedom/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/sifive_freedom/*/Kconfig.series" diff --git a/soc/riscv/sifive_freedom/e300/CMakeLists.txt b/soc/riscv/sifive_freedom/e300/CMakeLists.txt deleted file mode 100644 index baf01a6b047..00000000000 --- a/soc/riscv/sifive_freedom/e300/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(clock.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.e340 b/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.e340 deleted file mode 100644 index cb0131f1427..00000000000 --- a/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.e340 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "e340" if SOC_SIFIVE_FREEDOM_E340 diff --git a/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.series b/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.series deleted file mode 100644 index eaa43e68e70..00000000000 --- a/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SIFIVE_FREEDOM_E300 - -config SOC_SERIES - default "e300" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 52 - -config NUM_IRQS - default 64 - -source "soc/riscv/sifive_freedom/e300/Kconfig.defconfig.e*" - -endif # SOC_SERIES_SIFIVE_FREEDOM_E300 diff --git a/soc/riscv/sifive_freedom/e300/Kconfig.series b/soc/riscv/sifive_freedom/e300/Kconfig.series deleted file mode 100644 index 81634da000d..00000000000 --- a/soc/riscv/sifive_freedom/e300/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC implementation - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SIFIVE_FREEDOM_E300 - bool "SiFive Freedom E300 SOC implementation" - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - select SOC_FAMILY_SIFIVE_FREEDOM - help - Enable support for SiFive Freedom FE300 SOC diff --git a/soc/riscv/sifive_freedom/e300/Kconfig.soc b/soc/riscv/sifive_freedom/e300/Kconfig.soc deleted file mode 100644 index e53b84c0890..00000000000 --- a/soc/riscv/sifive_freedom/e300/Kconfig.soc +++ /dev/null @@ -1,20 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC configuration options - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "SiFive Freedom SOC implementation" - depends on SOC_SERIES_SIFIVE_FREEDOM_E300 - -config SOC_SIFIVE_FREEDOM_E340 - bool "SiFive Freedom SOC implementation" - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/sifive_freedom/u500/CMakeLists.txt b/soc/riscv/sifive_freedom/u500/CMakeLists.txt deleted file mode 100644 index baf01a6b047..00000000000 --- a/soc/riscv/sifive_freedom/u500/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(clock.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.series b/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.series deleted file mode 100644 index d306b60252a..00000000000 --- a/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SIFIVE_FREEDOM_U500 - -config SOC_SERIES - default "u500" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 52 - -config NUM_IRQS - default 64 - -source "soc/riscv/sifive_freedom/u500/Kconfig.defconfig.u*" - -endif # SOC_SERIES_SIFIVE_FREEDOM_U500 diff --git a/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.u540 b/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.u540 deleted file mode 100644 index f559f5914b3..00000000000 --- a/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.u540 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "u540" if SOC_SIFIVE_FREEDOM_U540 diff --git a/soc/riscv/sifive_freedom/u500/Kconfig.series b/soc/riscv/sifive_freedom/u500/Kconfig.series deleted file mode 100644 index 7335a1a5293..00000000000 --- a/soc/riscv/sifive_freedom/u500/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC implementation - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SIFIVE_FREEDOM_U500 - bool "SiFive Freedom U500 SOC implementation" - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - select SOC_FAMILY_SIFIVE_FREEDOM - help - Enable support for SiFive Freedom U500 SOC diff --git a/soc/riscv/sifive_freedom/u500/Kconfig.soc b/soc/riscv/sifive_freedom/u500/Kconfig.soc deleted file mode 100644 index 0a88ccf8cc1..00000000000 --- a/soc/riscv/sifive_freedom/u500/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC configuration options - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "SiFive Freedom SOC implementation" - depends on SOC_SERIES_SIFIVE_FREEDOM_U500 - -config SOC_SIFIVE_FREEDOM_U540 - bool "SiFive Freedom U540 SOC implementation" - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select 64BIT - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/sifive_freedom/u700/CMakeLists.txt b/soc/riscv/sifive_freedom/u700/CMakeLists.txt deleted file mode 100644 index baf01a6b047..00000000000 --- a/soc/riscv/sifive_freedom/u700/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(clock.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.series b/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.series deleted file mode 100644 index a0e730d608f..00000000000 --- a/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SIFIVE_FREEDOM_U700 - -config SOC_SERIES - default "u700" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 52 - -config NUM_IRQS - default 64 - -source "soc/riscv/sifive_freedom/u700/Kconfig.defconfig.u*" - -endif # SOC_SERIES_SIFIVE_FREEDOM_U700 diff --git a/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.u740 b/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.u740 deleted file mode 100644 index ca935f772eb..00000000000 --- a/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.u740 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "u740" if SOC_SIFIVE_FREEDOM_U740 diff --git a/soc/riscv/sifive_freedom/u700/Kconfig.series b/soc/riscv/sifive_freedom/u700/Kconfig.series deleted file mode 100644 index 04bdc1fb9b2..00000000000 --- a/soc/riscv/sifive_freedom/u700/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC implementation - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SIFIVE_FREEDOM_U700 - bool "SiFive Freedom SOC U700 implementation" - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - select SOC_FAMILY_SIFIVE_FREEDOM - help - Enable support for SiFive Freedom U700 SOC diff --git a/soc/riscv/sifive_freedom/u700/Kconfig.soc b/soc/riscv/sifive_freedom/u700/Kconfig.soc deleted file mode 100644 index 1eec9b4bb17..00000000000 --- a/soc/riscv/sifive_freedom/u700/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC configuration options - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "SiFive Freedom SOC implementation" - depends on SOC_SERIES_SIFIVE_FREEDOM_U700 - -config SOC_SIFIVE_FREEDOM_U740 - bool "SiFive Freedom U740 SOC implementation" - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select 64BIT - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/starfive_jh71xx/CMakeLists.txt b/soc/riscv/starfive_jh71xx/CMakeLists.txt deleted file mode 100644 index 69b2926358e..00000000000 --- a/soc/riscv/starfive_jh71xx/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/riscv/starfive_jh71xx/Kconfig b/soc/riscv/starfive_jh71xx/Kconfig deleted file mode 100644 index 65694c07eff..00000000000 --- a/soc/riscv/starfive_jh71xx/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_STARFIVE_JH71XX - bool - -if SOC_FAMILY_STARFIVE_JH71XX - -config SOC_FAMILY - string - default "starfive_jh71xx" - -source "soc/riscv/starfive_jh71xx/*/Kconfig.soc" - -endif # SOC_FAMILY_STARFIVE_JH71XX diff --git a/soc/riscv/starfive_jh71xx/Kconfig.defconfig b/soc/riscv/starfive_jh71xx/Kconfig.defconfig deleted file mode 100644 index b399e38b340..00000000000 --- a/soc/riscv/starfive_jh71xx/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/starfive_jh71xx/*/Kconfig.defconfig.series" diff --git a/soc/riscv/starfive_jh71xx/Kconfig.soc b/soc/riscv/starfive_jh71xx/Kconfig.soc deleted file mode 100644 index 1ff54faa970..00000000000 --- a/soc/riscv/starfive_jh71xx/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/starfive_jh71xx/*/Kconfig.series" diff --git a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.jh7100 b/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.jh7100 deleted file mode 100644 index 6f38d61dd4e..00000000000 --- a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.jh7100 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "jh7100" if SOC_JH7100 diff --git a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.series b/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.series deleted file mode 100644 index 0f058cb6c25..00000000000 --- a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.series +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2021 Rajnesh Kanwal -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STARFIVE_JH71XX - -config SOC_SERIES - default "jh71xx" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 6250000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config NUM_IRQS - default 139 - -source "soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.jh71*" - -endif diff --git a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.series b/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.series deleted file mode 100644 index f392a5d1f97..00000000000 --- a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Rajnesh Kanwal -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STARFIVE_JH71XX - bool "Starfive JH71XX series" - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - help - Enable support for Starfive JH71XX SoC Series. diff --git a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.soc b/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.soc deleted file mode 100644 index 8be7ebe5dbe..00000000000 --- a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2021 Rajnesh Kanwal -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Starfive JH7100 SoC" - depends on SOC_SERIES_STARFIVE_JH71XX - -config SOC_JH7100 - bool "Starfive JH7100" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/telink_tlsr/CMakeLists.txt b/soc/riscv/telink_tlsr/CMakeLists.txt deleted file mode 100644 index 69b2926358e..00000000000 --- a/soc/riscv/telink_tlsr/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/riscv/telink_tlsr/Kconfig b/soc/riscv/telink_tlsr/Kconfig deleted file mode 100644 index 144751311ba..00000000000 --- a/soc/riscv/telink_tlsr/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_TELINK_TLSR - bool - -if SOC_FAMILY_TELINK_TLSR - -config SOC_FAMILY - string - default "telink_tlsr" - -source "soc/riscv/telink_tlsr/*/Kconfig.soc" - -endif # SOC_FAMILY_TELINK_TLSR diff --git a/soc/riscv/telink_tlsr/Kconfig.defconfig b/soc/riscv/telink_tlsr/Kconfig.defconfig deleted file mode 100644 index 04a888381fa..00000000000 --- a/soc/riscv/telink_tlsr/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/telink_tlsr/*/Kconfig.defconfig.series" diff --git a/soc/riscv/telink_tlsr/Kconfig.soc b/soc/riscv/telink_tlsr/Kconfig.soc deleted file mode 100644 index db09c69d1f4..00000000000 --- a/soc/riscv/telink_tlsr/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/telink_tlsr/*/Kconfig.series" diff --git a/soc/riscv/telink_tlsr/tlsr951x/CMakeLists.txt b/soc/riscv/telink_tlsr/tlsr951x/CMakeLists.txt deleted file mode 100644 index 8c489ac6dd7..00000000000 --- a/soc/riscv/telink_tlsr/tlsr951x/CMakeLists.txt +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - start.S - soc_irq.S - soc.c -) - -# Force using BFD-LD -zephyr_ld_options(-fuse-ld=bfd) - -# Set compile options -zephyr_compile_options_ifdef(CONFIG_TELINK_B91_HWDSP -mext-dsp) -zephyr_compile_options_ifndef(CONFIG_RISCV_GP -mno-relax) -zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.series b/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.series deleted file mode 100644 index 2b72ad9960c..00000000000 --- a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.series +++ /dev/null @@ -1,53 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_TELINK_TLSR951X - -config SOC_SERIES - string - default "tlsr951x" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 32000 - -config RISCV_SOC_INTERRUPT_INIT - bool - default y - -config RISCV_GP - bool - default y - -config NUM_IRQS - int - default 64 - -config PINCTRL - default y - -config XIP - bool - default n - -config MAIN_STACK_SIZE - int - default 2048 - -config IDLE_STACK_SIZE - int - default 1536 - -config TEST_EXTRA_STACK_SIZE - int - default 1024 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config HAS_FLASH_LOAD_OFFSET - default y if BOOTLOADER_MCUBOOT - -source "soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.tlsr*" - -endif # SOC_SERIES_TELINK_TLSR951X diff --git a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.tlsr9518 b/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.tlsr9518 deleted file mode 100644 index 4ffdebdaf6b..00000000000 --- a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.tlsr9518 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "tlsr9518" if SOC_TELINK_TLSR9518 diff --git a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.series b/soc/riscv/telink_tlsr/tlsr951x/Kconfig.series deleted file mode 100644 index 5d5fc3226e5..00000000000 --- a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_TELINK_TLSR951X - bool "Telink TLSR951X" - select RISCV - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - select HAS_TELINK_DRIVERS - select ATOMIC_OPERATIONS_BUILTIN - select CPU_HAS_FPU - select INCLUDE_RESET_VECTOR - select SOC_FAMILY_TELINK_TLSR - help - Enable support for Telink TLSR951X diff --git a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.soc b/soc/riscv/telink_tlsr/tlsr951x/Kconfig.soc deleted file mode 100644 index 2abc12cc58c..00000000000 --- a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.soc +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_TELINK_TLSR951X - -choice - prompt "Telink TLSR951X SoC implementation" - -config SOC_TELINK_TLSR9518 - bool "Telink TLSR9518" - -endchoice - -config TELINK_B91_HWDSP - bool "Support Hardware DSP" - select RISCV_SOC_CONTEXT_SAVE - -config TELINK_B91_PFT_ARCH - bool "Support performance throttling" - default y - select RISCV_SOC_CONTEXT_SAVE - -endif # SOC_SERIES_TELINK_TLSR951X diff --git a/soc/riscv/virt/CMakeLists.txt b/soc/riscv/virt/CMakeLists.txt deleted file mode 100644 index 6a1826b29f9..00000000000 --- a/soc/riscv/virt/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/virt/Kconfig.defconfig b/soc/riscv/virt/Kconfig.defconfig deleted file mode 100644 index bed5ff8bec7..00000000000 --- a/soc/riscv/virt/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (c) 2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -if SOC_RISCV_VIRT - -config SOC - default "virt" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 10000000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 52 - -config NUM_IRQS - default 1035 - -config PMP_SLOTS - default 16 - -endif diff --git a/soc/riscv/virt/Kconfig.soc b/soc/riscv/virt/Kconfig.soc deleted file mode 100644 index 59e553a9d7b..00000000000 --- a/soc/riscv/virt/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RISCV_VIRT - bool "QEMU RISC-V VirtIO Board" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC diff --git a/soc/rockchip/CMakeLists.txt b/soc/rockchip/CMakeLists.txt new file mode 100644 index 00000000000..5e343b6e266 --- /dev/null +++ b/soc/rockchip/CMakeLists.txt @@ -0,0 +1,7 @@ +# +# Copyright 2021 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/rockchip/Kconfig b/soc/rockchip/Kconfig new file mode 100644 index 00000000000..80f0d67eb4d --- /dev/null +++ b/soc/rockchip/Kconfig @@ -0,0 +1,11 @@ +# +# Copyright 2021 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_FAMILY_ROCKCHIP + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ROCKCHIP diff --git a/soc/rockchip/Kconfig.defconfig b/soc/rockchip/Kconfig.defconfig new file mode 100644 index 00000000000..122e92dc999 --- /dev/null +++ b/soc/rockchip/Kconfig.defconfig @@ -0,0 +1,11 @@ +# +# Copyright 2021 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_FAMILY_ROCKCHIP + +rsource "*/Kconfig.defconfig" + +endif diff --git a/soc/rockchip/Kconfig.soc b/soc/rockchip/Kconfig.soc new file mode 100644 index 00000000000..2e782486499 --- /dev/null +++ b/soc/rockchip/Kconfig.soc @@ -0,0 +1,13 @@ +# +# Copyright 2021 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_FAMILY_ROCKCHIP + bool + +config SOC_FAMILY + default "rockchip" if SOC_FAMILY_ROCKCHIP + +rsource "*/Kconfig.soc" diff --git a/soc/arm64/rockchip/rk3399/CMakeLists.txt b/soc/rockchip/rk3399/CMakeLists.txt similarity index 100% rename from soc/arm64/rockchip/rk3399/CMakeLists.txt rename to soc/rockchip/rk3399/CMakeLists.txt diff --git a/soc/rockchip/rk3399/Kconfig b/soc/rockchip/rk3399/Kconfig new file mode 100644 index 00000000000..d85c98ec4a5 --- /dev/null +++ b/soc/rockchip/rk3399/Kconfig @@ -0,0 +1,13 @@ +# +# Copyright 2022 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_RK3399 + select ARM64 + select CPU_CORTEX_A53 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + +config SOC_PART_NUMBER + default "RK3399" if SOC_SERIES_RK3399 diff --git a/soc/rockchip/rk3399/Kconfig.defconfig b/soc/rockchip/rk3399/Kconfig.defconfig new file mode 100644 index 00000000000..775e37bf0c9 --- /dev/null +++ b/soc/rockchip/rk3399/Kconfig.defconfig @@ -0,0 +1,11 @@ +# +# Copyright 2022 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_RK3399 + +rsource "Kconfig.defconfig.rk3399" + +endif # SOC_SERIES_RK3399 diff --git a/soc/arm64/rockchip/rk3399/Kconfig.defconfig.rk3399 b/soc/rockchip/rk3399/Kconfig.defconfig.rk3399 similarity index 87% rename from soc/arm64/rockchip/rk3399/Kconfig.defconfig.rk3399 rename to soc/rockchip/rk3399/Kconfig.defconfig.rk3399 index 53eb8ae452a..07751909f32 100644 --- a/soc/arm64/rockchip/rk3399/Kconfig.defconfig.rk3399 +++ b/soc/rockchip/rk3399/Kconfig.defconfig.rk3399 @@ -6,9 +6,6 @@ if SOC_RK3399 -config SOC - default "rk3399" - config NUM_IRQS int default 240 diff --git a/soc/rockchip/rk3399/Kconfig.soc b/soc/rockchip/rk3399/Kconfig.soc new file mode 100644 index 00000000000..9d3885591dc --- /dev/null +++ b/soc/rockchip/rk3399/Kconfig.soc @@ -0,0 +1,19 @@ +# +# Copyright 2022 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_RK3399 + bool + select SOC_SERIES_RK3399 + +config SOC_SERIES_RK3399 + bool + select SOC_FAMILY_ROCKCHIP + +config SOC + default "rk3399" if SOC_RK3399 + +config SOC_SERIES + default "rk3399" if SOC_SERIES_RK3399 diff --git a/soc/arm64/rockchip/rk3399/mmu_regions.c b/soc/rockchip/rk3399/mmu_regions.c similarity index 100% rename from soc/arm64/rockchip/rk3399/mmu_regions.c rename to soc/rockchip/rk3399/mmu_regions.c diff --git a/soc/rockchip/rk3568/CMakeLists.txt b/soc/rockchip/rk3568/CMakeLists.txt new file mode 100644 index 00000000000..22fc2aa11be --- /dev/null +++ b/soc/rockchip/rk3568/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/rockchip/rk3568/Kconfig b/soc/rockchip/rk3568/Kconfig new file mode 100644 index 00000000000..8fc53a80fd9 --- /dev/null +++ b/soc/rockchip/rk3568/Kconfig @@ -0,0 +1,12 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RK3568 + select ARM64 + select CPU_CORTEX_A55 + select ARM_ARCH_TIMER + select GIC_V3 + +config SOC_PART_NUMBER + default "RK3568" if SOC_SERIES_RK3568 diff --git a/soc/rockchip/rk3568/Kconfig.defconfig b/soc/rockchip/rk3568/Kconfig.defconfig new file mode 100644 index 00000000000..b7f52249abe --- /dev/null +++ b/soc/rockchip/rk3568/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RK3568 + +rsource "Kconfig.defconfig.rk3568" + +endif # SOC_SERIES_RK3568 diff --git a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568 b/soc/rockchip/rk3568/Kconfig.defconfig.rk3568 similarity index 90% rename from soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568 rename to soc/rockchip/rk3568/Kconfig.defconfig.rk3568 index 13dca55c6e9..58cf932996f 100644 --- a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568 +++ b/soc/rockchip/rk3568/Kconfig.defconfig.rk3568 @@ -4,9 +4,6 @@ if SOC_RK3568 -config SOC - default "rk3568" - config FLASH_SIZE default 0 diff --git a/soc/rockchip/rk3568/Kconfig.soc b/soc/rockchip/rk3568/Kconfig.soc new file mode 100644 index 00000000000..7d965d764cb --- /dev/null +++ b/soc/rockchip/rk3568/Kconfig.soc @@ -0,0 +1,17 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RK3568 + bool + select SOC_FAMILY_ROCKCHIP + +config SOC_RK3568 + bool + select SOC_SERIES_RK3568 + +config SOC + default "rk3568" if SOC_RK3568 + +config SOC_SERIES + default "rk3568" if SOC_RK3568 diff --git a/soc/arm64/rockchip/rk3568/mmu_regions.c b/soc/rockchip/rk3568/mmu_regions.c similarity index 100% rename from soc/arm64/rockchip/rk3568/mmu_regions.c rename to soc/rockchip/rk3568/mmu_regions.c diff --git a/soc/rockchip/soc.yml b/soc/rockchip/soc.yml new file mode 100644 index 00000000000..5568a11aa49 --- /dev/null +++ b/soc/rockchip/soc.yml @@ -0,0 +1,9 @@ +family: + - name: rockchip + series: + - name: rk3399 + socs: + - name: rk3399 + - name: rk3568 + socs: + - name: rk3568 diff --git a/soc/riscv/nordic_nrf/CMakeLists.txt b/soc/sifive/sifive_freedom/CMakeLists.txt similarity index 100% rename from soc/riscv/nordic_nrf/CMakeLists.txt rename to soc/sifive/sifive_freedom/CMakeLists.txt diff --git a/soc/sifive/sifive_freedom/Kconfig b/soc/sifive/sifive_freedom/Kconfig new file mode 100644 index 00000000000..cee97a755b6 --- /dev/null +++ b/soc/sifive/sifive_freedom/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_SIFIVE_FREEDOM + +rsource "*/Kconfig" + +endif # SOC_FAMILY_SIFIVE_FREEDOM diff --git a/soc/sifive/sifive_freedom/Kconfig.defconfig b/soc/sifive/sifive_freedom/Kconfig.defconfig new file mode 100644 index 00000000000..004ef668fcf --- /dev/null +++ b/soc/sifive/sifive_freedom/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_SIFIVE_FREEDOM + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_SIFIVE_FREEDOM diff --git a/soc/sifive/sifive_freedom/Kconfig.soc b/soc/sifive/sifive_freedom/Kconfig.soc new file mode 100644 index 00000000000..e0bf27cb808 --- /dev/null +++ b/soc/sifive/sifive_freedom/Kconfig.soc @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_SIFIVE_FREEDOM + bool + +config SOC_FAMILY + default "sifive_freedom" if SOC_FAMILY_SIFIVE_FREEDOM + +rsource "*/Kconfig.soc" diff --git a/soc/riscv/sifive_freedom/common/CMakeLists.txt b/soc/sifive/sifive_freedom/common/CMakeLists.txt similarity index 100% rename from soc/riscv/sifive_freedom/common/CMakeLists.txt rename to soc/sifive/sifive_freedom/common/CMakeLists.txt diff --git a/soc/riscv/sifive_freedom/common/pinctrl_soc.h b/soc/sifive/sifive_freedom/common/pinctrl_soc.h similarity index 100% rename from soc/riscv/sifive_freedom/common/pinctrl_soc.h rename to soc/sifive/sifive_freedom/common/pinctrl_soc.h diff --git a/soc/sifive/sifive_freedom/fe300/CMakeLists.txt b/soc/sifive/sifive_freedom/fe300/CMakeLists.txt new file mode 100644 index 00000000000..4c3ee8c2ad8 --- /dev/null +++ b/soc/sifive/sifive_freedom/fe300/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(clock.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/sifive/sifive_freedom/fe300/Kconfig b/soc/sifive/sifive_freedom/fe300/Kconfig new file mode 100644 index 00000000000..e5796d7c9dc --- /dev/null +++ b/soc/sifive/sifive_freedom/fe300/Kconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2017 Jean-Paul Etienne +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FE300 + bool + + # RISC-V options + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + + select ATOMIC_OPERATIONS_C + select INCLUDE_RESET_VECTOR diff --git a/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig b/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig new file mode 100644 index 00000000000..c280c62ef43 --- /dev/null +++ b/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2017 Jean-Paul Etienne +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SIFIVE_FREEDOM_FE300 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 52 + +config NUM_IRQS + default 64 + +endif # SOC_SERIES_SIFIVE_FREEDOM_FE300 diff --git a/soc/sifive/sifive_freedom/fe300/Kconfig.soc b/soc/sifive/sifive_freedom/fe300/Kconfig.soc new file mode 100644 index 00000000000..e5229d16710 --- /dev/null +++ b/soc/sifive/sifive_freedom/fe300/Kconfig.soc @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FE300 + bool + select SOC_FAMILY_SIFIVE_FREEDOM + +config SOC_SERIES + default "fe300" if SOC_SERIES_SIFIVE_FREEDOM_FE300 + +config SOC_SIFIVE_FREEDOM_FE310 + bool + select SOC_SERIES_SIFIVE_FREEDOM_FE300 + +config SOC + default "fe310" if SOC_SIFIVE_FREEDOM_FE310 diff --git a/soc/riscv/sifive_freedom/e300/clock.c b/soc/sifive/sifive_freedom/fe300/clock.c similarity index 100% rename from soc/riscv/sifive_freedom/e300/clock.c rename to soc/sifive/sifive_freedom/fe300/clock.c diff --git a/soc/riscv/sifive_freedom/e300/prci.h b/soc/sifive/sifive_freedom/fe300/prci.h similarity index 100% rename from soc/riscv/sifive_freedom/e300/prci.h rename to soc/sifive/sifive_freedom/fe300/prci.h diff --git a/soc/riscv/sifive_freedom/e300/soc.h b/soc/sifive/sifive_freedom/fe300/soc.h similarity index 100% rename from soc/riscv/sifive_freedom/e300/soc.h rename to soc/sifive/sifive_freedom/fe300/soc.h diff --git a/soc/sifive/sifive_freedom/fu500/CMakeLists.txt b/soc/sifive/sifive_freedom/fu500/CMakeLists.txt new file mode 100644 index 00000000000..4c3ee8c2ad8 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu500/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(clock.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/sifive/sifive_freedom/fu500/Kconfig b/soc/sifive/sifive_freedom/fu500/Kconfig new file mode 100644 index 00000000000..dbe9e074ddd --- /dev/null +++ b/soc/sifive/sifive_freedom/fu500/Kconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2017 Jean-Paul Etienne +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FU500 + bool + + # RISC-V options + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + + select 64BIT + select INCLUDE_RESET_VECTOR diff --git a/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig b/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig new file mode 100644 index 00000000000..4db8701beb2 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2017 Jean-Paul Etienne +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SIFIVE_FREEDOM_FU500 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 52 + +config NUM_IRQS + default 64 + +endif # SOC_SERIES_SIFIVE_FREEDOM_FU500 diff --git a/soc/sifive/sifive_freedom/fu500/Kconfig.soc b/soc/sifive/sifive_freedom/fu500/Kconfig.soc new file mode 100644 index 00000000000..87a9e6d6edb --- /dev/null +++ b/soc/sifive/sifive_freedom/fu500/Kconfig.soc @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FU500 + bool + select SOC_FAMILY_SIFIVE_FREEDOM + +config SOC_SERIES + default "fu500" if SOC_SERIES_SIFIVE_FREEDOM_FU500 + +config SOC_SIFIVE_FREEDOM_FU540 + bool + select SOC_SERIES_SIFIVE_FREEDOM_FU500 + +config SOC + default "fu540" if SOC_SIFIVE_FREEDOM_FU540 diff --git a/soc/riscv/sifive_freedom/u500/clock.c b/soc/sifive/sifive_freedom/fu500/clock.c similarity index 100% rename from soc/riscv/sifive_freedom/u500/clock.c rename to soc/sifive/sifive_freedom/fu500/clock.c diff --git a/soc/riscv/sifive_freedom/u500/prci.h b/soc/sifive/sifive_freedom/fu500/prci.h similarity index 100% rename from soc/riscv/sifive_freedom/u500/prci.h rename to soc/sifive/sifive_freedom/fu500/prci.h diff --git a/soc/riscv/sifive_freedom/u500/soc.h b/soc/sifive/sifive_freedom/fu500/soc.h similarity index 100% rename from soc/riscv/sifive_freedom/u500/soc.h rename to soc/sifive/sifive_freedom/fu500/soc.h diff --git a/soc/sifive/sifive_freedom/fu700/CMakeLists.txt b/soc/sifive/sifive_freedom/fu700/CMakeLists.txt new file mode 100644 index 00000000000..4c3ee8c2ad8 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu700/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(clock.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/sifive/sifive_freedom/fu700/Kconfig b/soc/sifive/sifive_freedom/fu700/Kconfig new file mode 100644 index 00000000000..11804e56b92 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu700/Kconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FU700 + bool + + # RISC-V options + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + + select INCLUDE_RESET_VECTOR + select 64BIT diff --git a/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig b/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig new file mode 100644 index 00000000000..56aab7e3df8 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2017 Jean-Paul Etienne +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SIFIVE_FREEDOM_FU700 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 52 + +config NUM_IRQS + default 64 + +endif # SOC_SERIES_SIFIVE_FREEDOM_FU700 diff --git a/soc/sifive/sifive_freedom/fu700/Kconfig.soc b/soc/sifive/sifive_freedom/fu700/Kconfig.soc new file mode 100644 index 00000000000..db58d77a2c3 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu700/Kconfig.soc @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FU700 + bool + select SOC_FAMILY_SIFIVE_FREEDOM + +config SOC_SERIES + default "fu700" if SOC_SERIES_SIFIVE_FREEDOM_FU700 + +config SOC_SIFIVE_FREEDOM_FU740 + bool + select SOC_SERIES_SIFIVE_FREEDOM_FU700 + +config SOC + default "fu740" if SOC_SIFIVE_FREEDOM_FU740 diff --git a/soc/riscv/sifive_freedom/u700/clock.c b/soc/sifive/sifive_freedom/fu700/clock.c similarity index 100% rename from soc/riscv/sifive_freedom/u700/clock.c rename to soc/sifive/sifive_freedom/fu700/clock.c diff --git a/soc/riscv/sifive_freedom/u700/prci.h b/soc/sifive/sifive_freedom/fu700/prci.h similarity index 100% rename from soc/riscv/sifive_freedom/u700/prci.h rename to soc/sifive/sifive_freedom/fu700/prci.h diff --git a/soc/riscv/sifive_freedom/u700/soc.h b/soc/sifive/sifive_freedom/fu700/soc.h similarity index 100% rename from soc/riscv/sifive_freedom/u700/soc.h rename to soc/sifive/sifive_freedom/fu700/soc.h diff --git a/soc/sifive/sifive_freedom/soc.yml b/soc/sifive/sifive_freedom/soc.yml new file mode 100644 index 00000000000..1590d495d15 --- /dev/null +++ b/soc/sifive/sifive_freedom/soc.yml @@ -0,0 +1,12 @@ +family: + - name: sifive_freedom + series: + - name: fe300 + socs: + - name: fe310 + - name: fu500 + socs: + - name: fu540 + - name: fu700 + socs: + - name: fu740 diff --git a/soc/silabs/CMakeLists.txt b/soc/silabs/CMakeLists.txt new file mode 100644 index 00000000000..17eca2d8d6b --- /dev/null +++ b/soc/silabs/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Christian Taedcke + +add_subdirectory(common) +zephyr_include_directories(${SOC_FAMILY}/${SOC_SERIES}) diff --git a/soc/silabs/Kconfig b/soc/silabs/Kconfig new file mode 100644 index 00000000000..4e86a6e2b74 --- /dev/null +++ b/soc/silabs/Kconfig @@ -0,0 +1,325 @@ +# Copyright (c) 2017 Christian Taedcke +# Copyright (c) 2018 Gil Benkoe +# SPDX-License-Identifier: Apache-2.0 + +config SOC_VENDOR_SILABS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select BUILD_OUTPUT_HEX + +if SOC_VENDOR_SILABS + +rsource "*/*/Kconfig" + +config SOC_GECKO_SDID + int + help + Gecko SDK sometime refere to the chipset using the internal ID. This + entry reflects this ID. + +config SOC_GECKO_BURTC + bool + help + Set if the Back-Up Real Time Counter (BURTC) HAL module is used. + +config SOC_GECKO_CORE + bool + default y + help + Set if the Core interrupt handling (CORE) HAL module is used. + +config SOC_GECKO_ADC + bool + help + Set if the Analog to Digital Converter (ADC) HAL module is used. + +config SOC_GECKO_IADC + bool + help + Set if the Incremental Analog to Digital Converter (IADC) HAL module is used. + +config SOC_GECKO_CRYOTIMER + bool + help + Set if the Ultra Low Energy Timer/Counter (CRYOTIMER) HAL module is used. + +config SOC_GECKO_EMU + bool + help + Set if the Energy Management Unit (EMU) HAL module is used. + +config SOC_GECKO_GPIO + bool + help + Set if the General Purpose Input/Output (GPIO) HAL module is used. + +config SOC_GECKO_I2C + bool + help + Set if the Inter-Integrated Circuit Interface (I2C) HAL module is used. + +config SOC_GECKO_LETIMER + bool + help + Set if the Low Energy Timer (LETIMER) HAL module is used. + +config SOC_GECKO_LEUART + bool + help + Set if the Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) + HAL module is used. + +config SOC_GECKO_MSC + bool + help + Set if the Memory System Controller (MSC) HAL module is used. + +config SOC_GECKO_PRS + bool + help + Set if the Peripheral Reflex System (PRS) HAL module is used. + +config SOC_GECKO_RMU + bool + help + Set if the Reset Management Unit (RMU) HAL module is used. + +config SOC_GECKO_RTC + bool + help + Set if the Real Time Counter (RTC) HAL module is used. + +config SOC_GECKO_RTCC + bool + help + Set if the Real Time Counter and Calendar (RTCC) HAL module is used. + +config SOC_GECKO_SE + bool + help + Set if the Secure Element (SE) HAL module is used. + +config SOC_GECKO_TIMER + bool + help + Set if the Timer/Counter (TIMER) HAL module is used. + +config SOC_GECKO_USART + bool + help + Set if the Universal Synchronous Asynchronous Receiver/Transmitter (USART) + HAL module is used. + +config SOC_GECKO_WDOG + bool + help + Set if the Watchdog Timer (WDOG) HAL module is used. + +config SOC_GECKO_TRNG + bool + help + Set if the SoC has a True Random Number Generator (TRNG) module. + +if PM + +config SOC_GECKO_PM_BACKEND_PMGR + bool + depends on SOC_GECKO_DEV_INIT + default y if SOC_FAMILY_SILABS_S2 + help + Implement PM using sl_power_manager service from Gecko SDK + +config SOC_GECKO_PM_BACKEND_EMU + bool + default y if !SOC_GECKO_PM_BACKEND_PMGR + help + Implement PM using direct calls to EMU driver in emlib + +endif + +config SOC_GECKO_EMU_DCDC + bool "SoC DC/DC regulator" + select SOC_GECKO_EMU + help + Enable the on chip DC/DC regulator + +choice SOC_GECKO_EMU_DCDC_MODE + prompt "DC/DC mode" + depends on SOC_GECKO_EMU_DCDC + help + Select power configuration mode of the on chip DC/DC converter. + + config SOC_GECKO_EMU_DCDC_MODE_UNCONFIGURED + bool "Initial / Unconfigured" + + config SOC_GECKO_EMU_DCDC_MODE_ON + bool "DC/DC On" + + config SOC_GECKO_EMU_DCDC_MODE_OFF + bool "DC/DC Off" + + config SOC_GECKO_EMU_DCDC_MODE_BYPASS + bool "Bypass" +endchoice + +config CRYPTO_ACC_GECKO_TRNG + bool + help + Enable Entropy driver based on the CRYPTO_ACC module for Silicon Labs + Gecko chips. + +config SOC_GECKO_DEV_INIT + bool + help + Use the device initialization routines from the device_init service + in Silicon Labs HAL. These routines initialize and tune HFXOs, + configures DPLLs and manages the Energy Management Unit. + + Disabling these services may negatively impact counter and timer + routines in Silabs SoCs. + +config COUNTER_GECKO_STIMER + bool + help + Enable counter driver based on the Sleep Timer driver for Silicon Labs + Gecko chips. + +config SOC_GECKO_CMU + bool + help + Set if the clock management unit (CMU) is present in the SoC. + +if SOC_GECKO_CMU + +config CMU_NEED_LFXO + bool + help + Set if LFXO oscillator should be configured and enabled, potentially + in on-demand mode, after SoC is initialized. + +choice + prompt "High Frequency Clock Selection" + default CMU_HFCLK_HFXO + +config CMU_HFCLK_HFXO + bool "External high frequency crystal oscillator" + help + Set this option to use the external high frequency crystal oscillator + as high frequency clock. + +config CMU_HFCLK_LFXO + bool "External low frequency crystal oscillator" + select CMU_NEED_LFXO + help + Set this option to use the external low frequency crystal oscillator + as high frequency clock. + +config CMU_HFCLK_HFRCO + bool "Internal high frequency RC oscillator" + help + Set this option to use the internal high frequency RC oscillator as high frequency clock. + +endchoice + + +choice + prompt "BURTC Clock Selection" + depends on SOC_GECKO_BURTC + default CMU_BURTCCLK_LFRCO + +config CMU_BURTCCLK_LFXO + bool "LFXO - external low frequency crystal oscillator" + select CMU_NEED_LFXO + help + Set this option to use LFXO - the external low freqency crystal oscillator + as BURTC clock. + Frequency is set by external crystal, typically 32.768 kHz. + +config CMU_BURTCCLK_LFRCO + bool "LFRCO - internal low frequency RC oscillator" + help + Set this option to use LFRCO - the internal low freqency RC oscillator + as BURTC clock. + Frequency is approximately 32.768 kHz. + +config CMU_BURTCCLK_ULFRCO + bool "ULFRCO - internal ultra low frequency RC oscillator" + help + Set this option to use ULFRCO - the external low freqency crystal oscillator + as BURTC clock. + Frequency is approximately 1 kHz. + +endchoice + + +config CMU_HFXO_FREQ + int "External high frequency oscillator frequency" + help + Set the external high frequency oscillator frequency in Hz. This should be set by the + board's defconfig. + +config CMU_LFXO_FREQ + int "External low frequency oscillator frequency" + help + Set the external low frequency oscillator frequency in Hz. This should be set by the + board's defconfig. + +config CMU_HFRCO_FREQ + int "Internal high frequency RC oscillator frequency" + default 0 + depends on SOC_GECKO_HAS_HFRCO_FREQRANGE + help + Set the internal high frequency RC oscillator frequency in Hz. This should be set by the + board's defconfig. Only supported values may be used here. Setting this to 0, skips the + configuration of the high frequency RC oscillator completely. This may be desired, if + the bootloader already configured it properly or the device's default clock source should + be used with it's default configuration. + +endif # SOC_GECKO_CMU + +config SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + bool + help + If enabled, indicates that SoC allows to configure individual pin + locations. This is supported by e.g. efr32fg1p, efr32mg12p series. + If disabled, indicates that pin locations are configured in groups. + This is supported by e.g. efm32hg, efm32wg series. + +config SOC_GECKO_HAS_ERRATA_RTCC_E201 + bool + help + Set if the SoC is affected by errata RTCC_E201: + "When the RTCC is configured with a prescaler, the CCV1 top value enable + feature enabled by setting CCV1TOP in RTCC_CTRL fails to wrap the counter + when RTCC_CNT is equal to RTCC_CC1_CCV, as intended." + +config SOC_GECKO_HAS_HFRCO_FREQRANGE + bool + help + If enabled, indicates that configuration of HFRCO frequency for this SOC is supported + via FREQRANGE field. This is supported for e.g. efr32fg1p, efr32mg12p series. + If disabled, indicates that configuration of HFRCO frequency for corresponding SOC + is not supported via this field. This is the case for e.g. efm32hg, efm32wg series. + +config SOC_GECKO_HAS_RADIO + bool + help + If enabled, indicates that the SoC has a Radio PHY. + +config SOC_GECKO_USE_RAIL + bool "Use RAIL (Radio Abstraction Interface Layer)" + depends on SOC_GECKO_HAS_RADIO + help + RAIL (Radio Abstraction Interface Layer) is a library needed to use the EFR radio + hardware. This option enable the proper set of features to allow to properly compile + with the RAIL blob. + +config SOC_GECKO_CUSTOM_RADIO_PHY + bool "Use RAIL for custom radio phy packet sending and receiving" + depends on SOC_GECKO_HAS_RADIO + select SOC_GECKO_USE_RAIL + help + If enabled, RAIL can be used for user generated custom radio phy + management, sending and receiving packets on radio phy. User has + to provide the radio_config.c and radio_config.h files for the phy. + +endif # SOC_VENDOR_SILABS diff --git a/soc/silabs/Kconfig.defconfig b/soc/silabs/Kconfig.defconfig new file mode 100644 index 00000000000..530325a76a8 --- /dev/null +++ b/soc/silabs/Kconfig.defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Christian Taedcke + +if SOC_VENDOR_SILABS + +rsource "*/*/Kconfig.defconfig" + +config SOC_GECKO_EMU + default y + select SOC_GECKO_CORE + depends on PM + +config CORTEX_M_SYSTICK + default n if GECKO_BURTC_TIMER + +# With sl_power_manager, pm_state_set()'s stack footrpting is noticeably +# large, especially with logs enabled. Since it is called from IDLE task, +# its stack size has to be increased +config IDLE_STACK_SIZE + default 512 if SOC_GECKO_PM_BACKEND_PMGR + +endif diff --git a/soc/silabs/Kconfig.soc b/soc/silabs/Kconfig.soc new file mode 100644 index 00000000000..bea030078b7 --- /dev/null +++ b/soc/silabs/Kconfig.soc @@ -0,0 +1,12 @@ +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_VENDOR_SILABS + bool + +config SOC_FAMILY + default "silabs_s0" if SOC_FAMILY_SILABS_S0 + default "silabs_s1" if SOC_FAMILY_SILABS_S1 + default "silabs_s2" if SOC_FAMILY_SILABS_S2 + +rsource "*/Kconfig.soc" diff --git a/soc/arm/silabs_exx32/common/CMakeLists.txt b/soc/silabs/common/CMakeLists.txt similarity index 100% rename from soc/arm/silabs_exx32/common/CMakeLists.txt rename to soc/silabs/common/CMakeLists.txt diff --git a/soc/silabs/common/pinctrl_soc.h b/soc/silabs/common/pinctrl_soc.h new file mode 100644 index 00000000000..967b7c02455 --- /dev/null +++ b/soc/silabs/common/pinctrl_soc.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2022 Silicon Labs + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * Silabs SoC specific helpers for pinctrl driver + */ + +#ifndef ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ + +#include + +#include +#if CONFIG_SOC_FAMILY_SILABS_S1 +#include +#else +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +/** Type for gecko pin. */ +typedef uint32_t pinctrl_soc_pin_t; + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param prop Property name. + * @param idx Property entry index. + */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) (DT_PROP_BY_IDX(node_id, prop, idx)), + +/** + * @brief Utility macro to initialize state pins contained in a given property. + * + * @param node_id Node identifier. + * @param prop Property name describing state pins. + */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { \ + DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, psels, \ + Z_PINCTRL_STATE_PIN_INIT) \ + } + +/** + * @brief Utility macro to obtain pin function. + * + * @param pincfg Pin configuration bit field. + */ +#define GECKO_GET_FUN(pincfg) (((pincfg) >> GECKO_FUN_POS) & GECKO_FUN_MSK) + +/** + * @brief Utility macro to obtain port configuration. + * + * @param pincfg port configuration bit field. + */ +#define GECKO_GET_PORT(pincfg) (((pincfg) >> GECKO_PORT_POS) & GECKO_PORT_MSK) + +/** + * @brief Utility macro to obtain pin configuration. + * + * @param pincfg pin configuration bit field. + */ +#define GECKO_GET_PIN(pincfg) (((pincfg) >> GECKO_PIN_POS) & GECKO_PIN_MSK) + +/** + * @brief Utility macro to obtain location configuration. + * + * @param pincfg Loc configuration bit field. + */ +#define GECKO_GET_LOC(pincfg) (((pincfg) >> GECKO_LOC_POS) & GECKO_LOC_MSK) + +/** + * @brief Utility macro to obtain speed configuration. + * + * @param pincfg speed configuration bit field. + */ +#define GECKO_GET_SPEED(pincfg) (((pincfg) >> GECKO_SPEED_POS) & GECKO_SPEED_MSK) + +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/arm/silabs_exx32/common/sl_device_init_hfxo_config.h b/soc/silabs/common/sl_device_init_hfxo_config.h similarity index 100% rename from soc/arm/silabs_exx32/common/sl_device_init_hfxo_config.h rename to soc/silabs/common/sl_device_init_hfxo_config.h diff --git a/soc/silabs/common/soc.c b/soc/silabs/common/soc.c new file mode 100644 index 00000000000..1136a1fedfd --- /dev/null +++ b/soc/silabs/common/soc.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2018, Christian Taedcke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Common SoC initialization for the Silabs products + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SOC_GECKO_DEV_INIT +#include +#include +#include +#include +#include + +#ifdef CONFIG_PM +#include +#include +#endif + +#endif + +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#ifdef CONFIG_CMU_HFCLK_HFXO +/** + * @brief Initialization parameters for the external high frequency oscillator + */ +static CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT; +#endif + +#ifdef CONFIG_CMU_NEED_LFXO +/** + * @brief Initialization parameters for the external low frequency oscillator + */ +static CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT; + +static void init_lfxo(void) +{ + /* + * Configuring LFXO disables it, so we can do that only if it's not + * used as a SYSCLK/HFCLK source. + */ +#if defined(_SILICON_LABS_32B_SERIES_2) + if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_LFXO) { + /* + * Check if device has LFXO configuration info in DEVINFO + * See AN0016.2 + */ + if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_LFXOCALVAL) == + DEVINFO_MODULEINFO_LFXOCALVAL_VALID) { + lfxoInit.capTune = + (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK) >> + _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT; + } + CMU_LFXOInit(&lfxoInit); + } +#else + if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO) { + CMU_LFXOInit(&lfxoInit); + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + } +#endif /* _SILICON_LABS_32B_SERIES_2 */ + SystemLFXOClockSet(CONFIG_CMU_LFXO_FREQ); +} + +#endif /* CONFIG_CMU_NEED_LFXO */ + +/** + * @brief Initialize the system clock + */ +static ALWAYS_INLINE void clock_init(void) +{ +#ifdef CONFIG_CMU_HFCLK_HFXO +#if defined(_SILICON_LABS_32B_SERIES_2) + if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_HFXO) { + /* + * Check if device has HFXO configuration info in DEVINFO + * See AN0016.2 + */ + if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_HFXOCALVAL) == + DEVINFO_MODULEINFO_HFXOCALVAL_VALID) { + hfxoInit.ctuneXoAna = + (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK) >> + _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT; + hfxoInit.ctuneXiAna = + (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) >> + _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT; + } + + CMU_HFXOInit(&hfxoInit); + CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFXO); + } + + SystemHFXOClockSet(CONFIG_CMU_HFXO_FREQ); +#else + if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO) { + CMU_HFXOInit(&hfxoInit); + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); + } + SystemHFXOClockSet(CONFIG_CMU_HFXO_FREQ); + CMU_OscillatorEnable(cmuOsc_HFRCO, false, false); +#endif /* _SILICON_LABS_32B_SERIES_2 */ +#elif (defined CONFIG_CMU_HFCLK_LFXO) + /* LFXO should've been already brought up by init_lfxo() */ +#if defined(_SILICON_LABS_32B_SERIES_2) + CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_LFXO); +#else + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_LFXO); + CMU_OscillatorEnable(cmuOsc_HFRCO, false, false); +#endif /* _SILICON_LABS_32B_SERIES_2 */ +#elif (defined CONFIG_CMU_HFCLK_HFRCO) + /* + * This is the default clock, the controller starts with + */ + +#ifdef CONFIG_SOC_GECKO_HAS_HFRCO_FREQRANGE + if (CONFIG_CMU_HFRCO_FREQ) { + /* Setting system HFRCO frequency */ + CMU_HFRCOBandSet(CONFIG_CMU_HFRCO_FREQ); + + /* Using HFRCO as high frequency clock, HFCLK */ + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + } +#endif +#else +#error "Unsupported clock source for HFCLK selected" +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2) + /* Enable the High Frequency Peripheral Clock */ + CMU_ClockEnable(cmuClock_PCLK, true); +#else + /* Enable the High Frequency Peripheral Clock */ + CMU_ClockEnable(cmuClock_HFPER, true); +#endif /* _SILICON_LABS_32B_SERIES_2 */ + +#if defined(CONFIG_GPIO_GECKO) || defined(CONFIG_LOG_BACKEND_SWO) + CMU_ClockEnable(cmuClock_GPIO, true); +#endif +} + +#ifdef CONFIG_SOC_GECKO_EMU_DCDC +static ALWAYS_INLINE void dcdc_init(void) +{ +#if defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_UNCONFIGURED) + /* Nothing to do, leave DC/DC converter in unconfigured, safe state. */ +#elif defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON) || defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_BYPASS) + EMU_DCDCInit_TypeDef init_cfg = EMU_DCDCINIT_DEFAULT; +#if defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_BYPASS) + init_cfg.dcdcMode = emuDcdcMode_Bypass; +#endif + EMU_DCDCInit(&init_cfg); +#elif defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_OFF) + EMU_DCDCPowerOff(); +#else +#error "Unsupported power configuration mode of the on chip DC/DC converter." +#endif +} +#endif + +#ifdef CONFIG_LOG_BACKEND_SWO +static void swo_init(void) +{ + struct soc_gpio_pin pin_swo = PIN_SWO; + +#if defined(_SILICON_LABS_32B_SERIES_2) + GPIO->TRACEROUTEPEN = GPIO_TRACEROUTEPEN_SWVPEN; +#else + /* Select HFCLK as the debug trace clock */ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; + +#if defined(_GPIO_ROUTEPEN_MASK) + /* Enable Serial wire output pin */ + GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN; + /* Set SWO location */ + GPIO->ROUTELOC0 = SWO_LOCATION << _GPIO_ROUTELOC0_SWVLOC_SHIFT; +#else + GPIO->ROUTE = GPIO_ROUTE_SWOPEN | (SWO_LOCATION << 8); +#endif +#endif /* _SILICON_LABS_32B_SERIES_2 */ + + GPIO_PinModeSet(pin_swo.port, pin_swo.pin, pin_swo.mode, pin_swo.out); +} +#endif /* CONFIG_LOG_BACKEND_SWO */ + +/** + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * + * @return 0 + */ +static int silabs_init(void) +{ + /* handle chip errata */ + CHIP_Init(); + +#ifdef CONFIG_CMU_NEED_LFXO + init_lfxo(); +#endif + +#ifdef CONFIG_SOC_GECKO_DEV_INIT + sl_device_init_dcdc(); + sl_device_init_hfxo(); + sl_device_init_dpll(); + sl_device_init_emu(); + +#ifdef CONFIG_PM + sl_power_manager_init(); + sl_hfxo_manager_init(); +#endif + +#else /* !CONFIG_SOC_GECKO_DEV_INIT */ + +#ifdef CONFIG_SOC_GECKO_EMU_DCDC + dcdc_init(); +#endif + + /* Initialize system clock according to CONFIG_CMU settings */ + clock_init(); + +#ifdef CONFIG_LOG_BACKEND_SWO + /* Configure SWO debug output */ + swo_init(); +#endif +#endif /* !CONFIG_SOC_GECKO_DEV_INIT */ + + return 0; +} + +SYS_INIT(silabs_init, PRE_KERNEL_1, 0); diff --git a/soc/silabs/common/soc_gpio.h b/soc/silabs/common/soc_gpio.h new file mode 100644 index 00000000000..3d3faeac8b7 --- /dev/null +++ b/soc/silabs/common/soc_gpio.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017 Christian Taedcke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Silabs MCU family General Purpose Input Output (GPIO) + * module HAL driver. + */ + +#ifndef _SILABS_COMMON_SOC_GPIO_H_ +#define _SILABS_COMMON_SOC_GPIO_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct soc_gpio_pin { + GPIO_Port_TypeDef port; /** GPIO port */ + unsigned int pin; /** GPIO pin on the port */ + GPIO_Mode_TypeDef mode; /** mode of the pin, e.g. gpioModeInput */ + unsigned int out; /** out register value */ +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _SILABS_COMMON_SOC_GPIO_H_ */ diff --git a/soc/arm/silabs_exx32/common/soc_power.c b/soc/silabs/common/soc_power.c similarity index 100% rename from soc/arm/silabs_exx32/common/soc_power.c rename to soc/silabs/common/soc_power.c diff --git a/soc/arm/silabs_exx32/common/soc_power_pmgr.c b/soc/silabs/common/soc_power_pmgr.c similarity index 100% rename from soc/arm/silabs_exx32/common/soc_power_pmgr.c rename to soc/silabs/common/soc_power_pmgr.c diff --git a/soc/silabs/silabs_s0/Kconfig.soc b/soc/silabs/silabs_s0/Kconfig.soc new file mode 100644 index 00000000000..870fecc2a4a --- /dev/null +++ b/soc/silabs/silabs_s0/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_SILABS_S0 + bool + select SOC_VENDOR_SILABS + +rsource "*/Kconfig.soc" diff --git a/soc/silabs/silabs_s0/efm32hg/Kconfig b/soc/silabs/silabs_s0/efm32hg/Kconfig new file mode 100644 index 00000000000..8470c481634 --- /dev/null +++ b/soc/silabs/silabs_s0/efm32hg/Kconfig @@ -0,0 +1,17 @@ +# EFM32HG (Happy Gecko) MCU line + +# Copyright (c) 2018 Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32HG + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select HAS_SILABS_GECKO + select SOC_GECKO_CMU + select SOC_GECKO_GPIO + select HAS_PM + +config SOC_GECKO_SDID + default 77 if SOC_SERIES_EFM32HG diff --git a/soc/silabs/silabs_s0/efm32hg/Kconfig.defconfig b/soc/silabs/silabs_s0/efm32hg/Kconfig.defconfig new file mode 100644 index 00000000000..eaedcb9a996 --- /dev/null +++ b/soc/silabs/silabs_s0/efm32hg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# EFM32HG series configuration options + +# Copyright (c) 2018 Christian Taedcke +# Copyright (c) 2018 Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32HG + +config NUM_IRQS + # must be >= the highest interrupt number used + default 20 + +endif # SOC_SERIES_EFM32HG diff --git a/soc/silabs/silabs_s0/efm32hg/Kconfig.soc b/soc/silabs/silabs_s0/efm32hg/Kconfig.soc new file mode 100644 index 00000000000..c5dbfa03cf5 --- /dev/null +++ b/soc/silabs/silabs_s0/efm32hg/Kconfig.soc @@ -0,0 +1,23 @@ +# EFM32HG (Happy Gecko) MCU line + +# Copyright (c) 2018 Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32HG + bool + select SOC_FAMILY_SILABS_S0 + help + EFM32HG Series MCU + +config SOC_PART_NUMBER_EFM32HG322F64 + bool + select SOC_SERIES_EFM32HG + +config SOC_SERIES + default "efm32hg" if SOC_SERIES_EFM32HG + +config SOC + default "efm32hg322f64" if SOC_PART_NUMBER_EFM32HG322F64 + +config SOC_PART_NUMBER + default "EFM32HG322F64" if SOC_PART_NUMBER_EFM32HG322F64 diff --git a/soc/arm/silabs_exx32/efm32hg/soc.h b/soc/silabs/silabs_s0/efm32hg/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32hg/soc.h rename to soc/silabs/silabs_s0/efm32hg/soc.h diff --git a/soc/arm/silabs_exx32/efm32hg/soc_pinmap.h b/soc/silabs/silabs_s0/efm32hg/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32hg/soc_pinmap.h rename to soc/silabs/silabs_s0/efm32hg/soc_pinmap.h diff --git a/soc/silabs/silabs_s0/efm32wg/Kconfig b/soc/silabs/silabs_s0/efm32wg/Kconfig new file mode 100644 index 00000000000..9afdfa8846e --- /dev/null +++ b/soc/silabs/silabs_s0/efm32wg/Kconfig @@ -0,0 +1,18 @@ +# EFM32WG (Wonder Gecko) MCU line + +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32WG + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_SILABS_GECKO + select SOC_GECKO_CMU + select SOC_GECKO_GPIO + select HAS_PM + +config SOC_GECKO_SDID + default 74 if SOC_SERIES_EFM32WG diff --git a/soc/silabs/silabs_s0/efm32wg/Kconfig.defconfig b/soc/silabs/silabs_s0/efm32wg/Kconfig.defconfig new file mode 100644 index 00000000000..93664abc5f4 --- /dev/null +++ b/soc/silabs/silabs_s0/efm32wg/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFM32WG series configuration options + +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32WG + +config NUM_IRQS + # must be >= the highest interrupt number used + default 39 + +endif # SOC_SERIES_EFM32WG diff --git a/soc/silabs/silabs_s0/efm32wg/Kconfig.soc b/soc/silabs/silabs_s0/efm32wg/Kconfig.soc new file mode 100644 index 00000000000..bdf6bac595a --- /dev/null +++ b/soc/silabs/silabs_s0/efm32wg/Kconfig.soc @@ -0,0 +1,23 @@ +# EFM32WG (Wonder Gecko) MCU line + +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32WG + bool + select SOC_FAMILY_SILABS_S0 + help + EFM32WG Series MCU + +config SOC_PART_NUMBER_EFM32WG990F256 + bool + select SOC_SERIES_EFM32WG + +config SOC_SERIES + default "efm32wg" if SOC_SERIES_EFM32WG + +config SOC + default "efm32wg990f256" if SOC_PART_NUMBER_EFM32WG990F256 + +config SOC_PART_NUMBER + default "EFM32WG990F256" if SOC_PART_NUMBER_EFM32WG990F256 diff --git a/soc/arm/silabs_exx32/efm32wg/soc.h b/soc/silabs/silabs_s0/efm32wg/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32wg/soc.h rename to soc/silabs/silabs_s0/efm32wg/soc.h diff --git a/soc/arm/silabs_exx32/efm32wg/soc_pinmap.h b/soc/silabs/silabs_s0/efm32wg/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32wg/soc_pinmap.h rename to soc/silabs/silabs_s0/efm32wg/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/Kconfig.soc b/soc/silabs/silabs_s1/Kconfig.soc new file mode 100644 index 00000000000..d2771e803ec --- /dev/null +++ b/soc/silabs/silabs_s1/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_SILABS_S1 + bool + select SOC_VENDOR_SILABS + +rsource "*/Kconfig.soc" diff --git a/soc/silabs/silabs_s1/efm32gg11b/Kconfig b/soc/silabs/silabs_s1/efm32gg11b/Kconfig new file mode 100644 index 00000000000..8dcc746fb6e --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg11b/Kconfig @@ -0,0 +1,21 @@ +# EFM32GG11B (Giant Gecko) MCU line +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32GG11B + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_TRNG + +config SOC_GECKO_SDID + default 100 if SOC_SERIES_EFM32GG11B diff --git a/soc/silabs/silabs_s1/efm32gg11b/Kconfig.defconfig b/soc/silabs/silabs_s1/efm32gg11b/Kconfig.defconfig new file mode 100644 index 00000000000..07a92c66b82 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg11b/Kconfig.defconfig @@ -0,0 +1,17 @@ +# EFM32GG11B series configuration options +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32GG11B + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 68 + +config GPIO_GECKO + default y + depends on GPIO || LOG_BACKEND_SWO + +endif # SOC_SERIES_EFM32GG11B diff --git a/soc/silabs/silabs_s1/efm32gg11b/Kconfig.soc b/soc/silabs/silabs_s1/efm32gg11b/Kconfig.soc new file mode 100644 index 00000000000..0d136b520c7 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg11b/Kconfig.soc @@ -0,0 +1,29 @@ +# EFM32GG11B (Giant Gecko) MCU line +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32GG11B + bool + select SOC_FAMILY_SILABS_S1 + help + EFM32GG11B Series MCU + +config SOC_PART_NUMBER_EFM32GG11B820F2048GL192 + bool + select SOC_SERIES_EFM32GG11B + +config SOC_PART_NUMBER_EFM32GG11B820F2048GM64 + bool + select SOC_SERIES_EFM32GG11B + +config SOC_SERIES + default "efm32gg11b" if SOC_SERIES_EFM32GG11B + +config SOC + default "efm32gg11b820f2048gl192" if SOC_PART_NUMBER_EFM32GG11B820F2048GL192 + default "efm32gg11b820f2048gm64" if SOC_PART_NUMBER_EFM32GG11B820F2048GM64 + +config SOC_PART_NUMBER + default "EFM32GG11B820F2048GL192" if SOC_PART_NUMBER_EFM32GG11B820F2048GL192 + default "EFM32GG11B820F2048GM64" if SOC_PART_NUMBER_EFM32GG11B820F2048GM64 diff --git a/soc/arm/silabs_exx32/efm32gg11b/soc.h b/soc/silabs/silabs_s1/efm32gg11b/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32gg11b/soc.h rename to soc/silabs/silabs_s1/efm32gg11b/soc.h diff --git a/soc/arm/silabs_exx32/efm32gg11b/soc_pinmap.h b/soc/silabs/silabs_s1/efm32gg11b/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32gg11b/soc_pinmap.h rename to soc/silabs/silabs_s1/efm32gg11b/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efm32gg12b/Kconfig b/soc/silabs/silabs_s1/efm32gg12b/Kconfig new file mode 100644 index 00000000000..f8be8f8b993 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg12b/Kconfig @@ -0,0 +1,20 @@ +# EFM32GG12B (Giant Gecko) MCU line +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32GG12B + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_TRNG + +config SOC_GECKO_SDID + default 106 if SOC_SERIES_EFM32GG12B diff --git a/soc/silabs/silabs_s1/efm32gg12b/Kconfig.defconfig b/soc/silabs/silabs_s1/efm32gg12b/Kconfig.defconfig new file mode 100644 index 00000000000..7bcb50e8ef7 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg12b/Kconfig.defconfig @@ -0,0 +1,16 @@ +# EFM32GG12B series configuration options +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32GG12B + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 68 + +config GPIO_GECKO + default y + depends on GPIO || LOG_BACKEND_SWO + +endif # SOC_SERIES_EFM32GG12B diff --git a/soc/silabs/silabs_s1/efm32gg12b/Kconfig.soc b/soc/silabs/silabs_s1/efm32gg12b/Kconfig.soc new file mode 100644 index 00000000000..8367ffcd908 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg12b/Kconfig.soc @@ -0,0 +1,22 @@ +# EFM32GG12B (Giant Gecko) MCU line +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32GG12B + bool + select SOC_FAMILY_SILABS_S1 + help + EFM32GG12B Series MCU + +config SOC_PART_NUMBER_EFM32GG12B810F1024GM64 + bool + select SOC_SERIES_EFM32GG12B + +config SOC_SERIES + default "efm32gg12b" if SOC_SERIES_EFM32GG12B + +config SOC + default "efm32gg12b810f1024gm64" if SOC_PART_NUMBER_EFM32GG12B810F1024GM64 + +config SOC_PART_NUMBER + default "EFM32GG12B810F1024GM64" if SOC_PART_NUMBER_EFM32GG12B810F1024GM64 diff --git a/soc/arm/silabs_exx32/efm32gg12b/soc.h b/soc/silabs/silabs_s1/efm32gg12b/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32gg12b/soc.h rename to soc/silabs/silabs_s1/efm32gg12b/soc.h diff --git a/soc/arm/silabs_exx32/efm32gg12b/soc_pinmap.h b/soc/silabs/silabs_s1/efm32gg12b/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32gg12b/soc_pinmap.h rename to soc/silabs/silabs_s1/efm32gg12b/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efm32jg12b/Kconfig b/soc/silabs/silabs_s1/efm32jg12b/Kconfig new file mode 100644 index 00000000000..adb3d67c04c --- /dev/null +++ b/soc/silabs/silabs_s1/efm32jg12b/Kconfig @@ -0,0 +1,21 @@ +# EFM32JG12B (Jade Gecko) MCU line + +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32JG12B + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M3 + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_TRNG + select HAS_PM + +config SOC_GECKO_SDID + default 84 if SOC_SERIES_EFM32JG12B diff --git a/soc/silabs/silabs_s1/efm32jg12b/Kconfig.defconfig b/soc/silabs/silabs_s1/efm32jg12b/Kconfig.defconfig new file mode 100644 index 00000000000..d0d04a59ba3 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32jg12b/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFM32JG12B series configuration options + +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32JG12B + +config NUM_IRQS + # must be >= the highest interrupt number used + default 50 + +endif # SOC_SERIES_EFM32JG12B diff --git a/soc/silabs/silabs_s1/efm32jg12b/Kconfig.soc b/soc/silabs/silabs_s1/efm32jg12b/Kconfig.soc new file mode 100644 index 00000000000..1142c09a25a --- /dev/null +++ b/soc/silabs/silabs_s1/efm32jg12b/Kconfig.soc @@ -0,0 +1,23 @@ +# EFM32JG12B (Jade Gecko) MCU line + +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32JG12B + bool + select SOC_FAMILY_SILABS_S1 + help + EFM32JG12B Series MCU + +config SOC_PART_NUMBER_EFM32JG12B500F1024GL125 + bool + select SOC_SERIES_EFM32JG12B + +config SOC_SERIES + default "efm32jg12b" if SOC_SERIES_EFM32JG12B + +config SOC + default "efm32jg12b500f1024gl125" if SOC_PART_NUMBER_EFM32JG12B500F1024GL125 + +config SOC_PART_NUMBER + default "EFM32JG12B500F1024GL125" if SOC_PART_NUMBER_EFM32JG12B500F1024GL125 diff --git a/soc/arm/silabs_exx32/efm32jg12b/soc.h b/soc/silabs/silabs_s1/efm32jg12b/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32jg12b/soc.h rename to soc/silabs/silabs_s1/efm32jg12b/soc.h diff --git a/soc/arm/silabs_exx32/efm32jg12b/soc_pinmap.h b/soc/silabs/silabs_s1/efm32jg12b/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32jg12b/soc_pinmap.h rename to soc/silabs/silabs_s1/efm32jg12b/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efm32pg12b/Kconfig b/soc/silabs/silabs_s1/efm32pg12b/Kconfig new file mode 100644 index 00000000000..6919ee1e71b --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg12b/Kconfig @@ -0,0 +1,24 @@ +# EFM32PG12B (Pearl Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32PG12B + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_TRNG + select SOC_GECKO_ADC + select HAS_PM + +config SOC_GECKO_SDID + default 84 if SOC_SERIES_EFM32PG12B diff --git a/soc/silabs/silabs_s1/efm32pg12b/Kconfig.defconfig b/soc/silabs/silabs_s1/efm32pg12b/Kconfig.defconfig new file mode 100644 index 00000000000..2fce94f7c2b --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg12b/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFM32PG12B series configuration options + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32PG12B + +config NUM_IRQS + # must be >= the highest interrupt number used + default 50 + +endif # SOC_SERIES_EFM32PG12B diff --git a/soc/silabs/silabs_s1/efm32pg12b/Kconfig.soc b/soc/silabs/silabs_s1/efm32pg12b/Kconfig.soc new file mode 100644 index 00000000000..1a8a7006045 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg12b/Kconfig.soc @@ -0,0 +1,23 @@ +# EFM32PG12B (Pearl Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32PG12B + bool + select SOC_FAMILY_SILABS_S1 + help + EFM32PG12B Series MCU + +config SOC_PART_NUMBER_EFM32PG12B500F1024GL125 + bool + select SOC_SERIES_EFM32PG12B + +config SOC_SERIES + default "efm32pg12b" if SOC_SERIES_EFM32PG12B + +config SOC + default "efm32pg12b500f1024gl125" if SOC_PART_NUMBER_EFM32PG12B500F1024GL125 + +config SOC_PART_NUMBER + default "EFM32PG12B500F1024GL125" if SOC_PART_NUMBER_EFM32PG12B500F1024GL125 diff --git a/soc/arm/silabs_exx32/efm32pg12b/soc.h b/soc/silabs/silabs_s1/efm32pg12b/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32pg12b/soc.h rename to soc/silabs/silabs_s1/efm32pg12b/soc.h diff --git a/soc/arm/silabs_exx32/efm32pg12b/soc_pinmap.h b/soc/silabs/silabs_s1/efm32pg12b/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32pg12b/soc_pinmap.h rename to soc/silabs/silabs_s1/efm32pg12b/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efm32pg1b/Kconfig b/soc/silabs/silabs_s1/efm32pg1b/Kconfig new file mode 100644 index 00000000000..44596bb5d3c --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg1b/Kconfig @@ -0,0 +1,22 @@ +# EFM32PG1B (Pearl Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32PG1B + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select HAS_PM + +config SOC_GECKO_SDID + default 80 if SOC_SERIES_EFM32PG1B diff --git a/soc/silabs/silabs_s1/efm32pg1b/Kconfig.defconfig b/soc/silabs/silabs_s1/efm32pg1b/Kconfig.defconfig new file mode 100644 index 00000000000..7a0549d800e --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg1b/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFM32PG1B series configuration options + +# Copyright (c) 2020 Rafael Dias Menezes +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32PG1B + +config NUM_IRQS + # must be >= the highest interrupt number used + default 34 + +endif # SOC_SERIES_EFM32PG1B diff --git a/soc/silabs/silabs_s1/efm32pg1b/Kconfig.soc b/soc/silabs/silabs_s1/efm32pg1b/Kconfig.soc new file mode 100644 index 00000000000..428c49847bd --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg1b/Kconfig.soc @@ -0,0 +1,23 @@ +# EFM32PG1B (Pearl Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32PG1B + bool + select SOC_FAMILY_SILABS_S1 + help + EFM32PG1B Series MCU + +config SOC_PART_NUMBER_EFM32PG1B200F256GM48 + bool + select SOC_SERIES_EFM32PG1B + +config SOC_SERIES + default "efm32pg1b" if SOC_SERIES_EFM32PG1B + +config SOC + default "efm32pg1b200f256gm48" if SOC_PART_NUMBER_EFM32PG1B200F256GM48 + +config SOC_PART_NUMBER + default "EFM32PG1B200F256GM48" if SOC_PART_NUMBER_EFM32PG1B200F256GM48 diff --git a/soc/arm/silabs_exx32/efm32pg1b/soc.h b/soc/silabs/silabs_s1/efm32pg1b/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32pg1b/soc.h rename to soc/silabs/silabs_s1/efm32pg1b/soc.h diff --git a/soc/arm/silabs_exx32/efm32pg1b/soc_pinmap.h b/soc/silabs/silabs_s1/efm32pg1b/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32pg1b/soc_pinmap.h rename to soc/silabs/silabs_s1/efm32pg1b/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efr32bg13p/Kconfig b/soc/silabs/silabs_s1/efr32bg13p/Kconfig new file mode 100644 index 00000000000..04161566878 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32bg13p/Kconfig @@ -0,0 +1,22 @@ +# Silicon Labs EFR32BG13P (Blue Gecko) MCU series + +# Copyright (c) 2020 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG13P + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_RADIO + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select HAS_PM + +config SOC_GECKO_SDID + default 89 if SOC_SERIES_EFR32BG13P diff --git a/soc/silabs/silabs_s1/efr32bg13p/Kconfig.defconfig b/soc/silabs/silabs_s1/efr32bg13p/Kconfig.defconfig new file mode 100644 index 00000000000..ec5e8cd1f66 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32bg13p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Silicon Labs EFR32BG13P (Blue Gecko) MCU configuration options + +# Copyright (c) 2020 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32BG13P + +config NUM_IRQS + # must be >= the highest interrupt number used + default 47 + +endif # SOC_SERIES_EFR32BG13P diff --git a/soc/silabs/silabs_s1/efr32bg13p/Kconfig.soc b/soc/silabs/silabs_s1/efr32bg13p/Kconfig.soc new file mode 100644 index 00000000000..971e7932b95 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32bg13p/Kconfig.soc @@ -0,0 +1,23 @@ +# Silicon Labs EFR32BG13P (Blue Gecko) MCU series + +# Copyright (c) 2020 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG13P + bool + select SOC_FAMILY_SILABS_S1 + help + EFR32BG13P Series MCU + +config SOC_PART_NUMBER_EFR32BG13P632F512GM48 + bool + select SOC_SERIES_EFR32BG13P + +config SOC_SERIES + default "efr32bg13p" if SOC_SERIES_EFR32BG13P + +config SOC + default "efr32bg13p632f512gm48" if SOC_PART_NUMBER_EFR32BG13P632F512GM48 + +config SOC_PART_NUMBER + default "EFR32BG13P632F512GM48" if SOC_PART_NUMBER_EFR32BG13P632F512GM48 diff --git a/soc/arm/silabs_exx32/efr32bg13p/soc.h b/soc/silabs/silabs_s1/efr32bg13p/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32bg13p/soc.h rename to soc/silabs/silabs_s1/efr32bg13p/soc.h diff --git a/soc/arm/silabs_exx32/efr32bg13p/soc_pinmap.h b/soc/silabs/silabs_s1/efr32bg13p/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efr32bg13p/soc_pinmap.h rename to soc/silabs/silabs_s1/efr32bg13p/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efr32fg13p/Kconfig b/soc/silabs/silabs_s1/efr32fg13p/Kconfig new file mode 100644 index 00000000000..9b68eb58066 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg13p/Kconfig @@ -0,0 +1,23 @@ +# EFR32FG13P (Flex Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32FG13P + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_RADIO + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_GPIO + select SOC_GECKO_HAS_ERRATA_RTCC_E201 + select HAS_PM + +config SOC_GECKO_SDID + default 89 if SOC_SERIES_EFR32FG13P diff --git a/soc/silabs/silabs_s1/efr32fg13p/Kconfig.defconfig b/soc/silabs/silabs_s1/efr32fg13p/Kconfig.defconfig new file mode 100644 index 00000000000..5d3bdc08618 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg13p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFR32FG13P series configuration options + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32FG13P + +config NUM_IRQS + # must be >= the highest interrupt number used + default 45 + +endif # SOC_SERIES_EFR32FG13P diff --git a/soc/silabs/silabs_s1/efr32fg13p/Kconfig.soc b/soc/silabs/silabs_s1/efr32fg13p/Kconfig.soc new file mode 100644 index 00000000000..e65132a49e6 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg13p/Kconfig.soc @@ -0,0 +1,23 @@ +# EFR32FG13P (Flex Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32FG13P + bool + select SOC_FAMILY_SILABS_S1 + help + EFR32FG13P Series MCU + +config SOC_PART_NUMBER_EFR32FG13P233F512GM48 + bool + select SOC_SERIES_EFR32FG13P + +config SOC_SERIES + default "efr32fg13p" if SOC_SERIES_EFR32FG13P + +config SOC + default "efr32fg13p233f512gm48" if SOC_PART_NUMBER_EFR32FG13P233F512GM48 + +config SOC_PART_NUMBER + default "EFR32FG13P233F512GM48" if SOC_PART_NUMBER_EFR32FG13P233F512GM48 diff --git a/soc/arm/silabs_exx32/efr32fg13p/soc.h b/soc/silabs/silabs_s1/efr32fg13p/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32fg13p/soc.h rename to soc/silabs/silabs_s1/efr32fg13p/soc.h diff --git a/soc/arm/silabs_exx32/efr32fg13p/soc_pinmap.h b/soc/silabs/silabs_s1/efr32fg13p/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efr32fg13p/soc_pinmap.h rename to soc/silabs/silabs_s1/efr32fg13p/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efr32fg1p/Kconfig b/soc/silabs/silabs_s1/efr32fg1p/Kconfig new file mode 100644 index 00000000000..19c8ef7af98 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg1p/Kconfig @@ -0,0 +1,23 @@ +# EFR32FG1P (Flex Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32FG1P + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_RADIO + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_GPIO + select SOC_GECKO_HAS_ERRATA_RTCC_E201 + select HAS_PM + +config SOC_GECKO_SDID + default 80 if SOC_SERIES_EFR32FG1P diff --git a/soc/silabs/silabs_s1/efr32fg1p/Kconfig.defconfig b/soc/silabs/silabs_s1/efr32fg1p/Kconfig.defconfig new file mode 100644 index 00000000000..8e6645f22e1 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg1p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFR32FG1P series configuration options + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32FG1P + +config NUM_IRQS + # must be >= the highest interrupt number used + default 33 + +endif # SOC_SERIES_EFR32FG1P diff --git a/soc/silabs/silabs_s1/efr32fg1p/Kconfig.soc b/soc/silabs/silabs_s1/efr32fg1p/Kconfig.soc new file mode 100644 index 00000000000..ed0f05860f7 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg1p/Kconfig.soc @@ -0,0 +1,23 @@ +# EFR32FG1P (Flex Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32FG1P + bool + select SOC_FAMILY_SILABS_S1 + help + EFR32FG1P Series MCU + +config SOC_PART_NUMBER_EFR32FG1P133F256GM48 + bool + select SOC_SERIES_EFR32FG1P + +config SOC_SERIES + default "efr32fg1p" if SOC_SERIES_EFR32FG1P + +config SOC + default "efr32fg1p133f256gm48" if SOC_PART_NUMBER_EFR32FG1P133F256GM48 + +config SOC_PART_NUMBER + default "EFR32FG1P133F256GM48" if SOC_PART_NUMBER_EFR32FG1P133F256GM48 diff --git a/soc/arm/silabs_exx32/efr32fg1p/soc.h b/soc/silabs/silabs_s1/efr32fg1p/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32fg1p/soc.h rename to soc/silabs/silabs_s1/efr32fg1p/soc.h diff --git a/soc/arm/silabs_exx32/efr32fg1p/soc_pinmap.h b/soc/silabs/silabs_s1/efr32fg1p/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efr32fg1p/soc_pinmap.h rename to soc/silabs/silabs_s1/efr32fg1p/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efr32mg12p/Kconfig b/soc/silabs/silabs_s1/efr32mg12p/Kconfig new file mode 100644 index 00000000000..cba1530dbf8 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32mg12p/Kconfig @@ -0,0 +1,24 @@ +# EFR32MG12P (Mighty Gecko) MCU line + +# Copyright (c) 2018 Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG12P + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_RADIO + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_TRNG + select HAS_PM + +config SOC_GECKO_SDID + default 84 if SOC_SERIES_EFR32MG12P diff --git a/soc/silabs/silabs_s1/efr32mg12p/Kconfig.defconfig b/soc/silabs/silabs_s1/efr32mg12p/Kconfig.defconfig new file mode 100644 index 00000000000..bb2b6c314b9 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32mg12p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFM32WG series configuration options + +# Copyright (c) 2018 Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32MG12P + +config NUM_IRQS + # must be >= the highest interrupt number used + default 49 + +endif # SOC_SERIES_EFR32MG12P diff --git a/soc/silabs/silabs_s1/efr32mg12p/Kconfig.soc b/soc/silabs/silabs_s1/efr32mg12p/Kconfig.soc new file mode 100644 index 00000000000..61890df2ccf --- /dev/null +++ b/soc/silabs/silabs_s1/efr32mg12p/Kconfig.soc @@ -0,0 +1,35 @@ +# EFR32MG12P (Mighty Gecko) MCU line + +# Copyright (c) 2018 Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG12P + bool + select SOC_FAMILY_SILABS_S1 + help + EFR32MG12P Series MCU + +config SOC_PART_NUMBER_EFR32MG12P332F1024GL125 + bool + select SOC_SERIES_EFR32MG12P + +config SOC_PART_NUMBER_EFR32MG12P433F1024GM68 + bool + select SOC_SERIES_EFR32MG12P + +config SOC_PART_NUMBER_EFR32MG12P432F1024GL125 + bool + select SOC_SERIES_EFR32MG12P + +config SOC_SERIES + default "efr32mg12p" if SOC_SERIES_EFR32MG12P + +config SOC + default "efr32mg12p332f1024gl125" if SOC_PART_NUMBER_EFR32MG12P332F1024GL125 + default "efr32mg12p432f1024gl125" if SOC_PART_NUMBER_EFR32MG12P432F1024GL125 + default "efr32mg12p433f1024gm68" if SOC_PART_NUMBER_EFR32MG12P433F1024GM68 + +config SOC_PART_NUMBER + default "EFR32MG12P332F1024GL125" if SOC_PART_NUMBER_EFR32MG12P332F1024GL125 + default "EFR32MG12P432F1024GL125" if SOC_PART_NUMBER_EFR32MG12P432F1024GL125 + default "EFR32MG12P433F1024GM68" if SOC_PART_NUMBER_EFR32MG12P433F1024GM68 diff --git a/soc/arm/silabs_exx32/efr32mg12p/soc.h b/soc/silabs/silabs_s1/efr32mg12p/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32mg12p/soc.h rename to soc/silabs/silabs_s1/efr32mg12p/soc.h diff --git a/soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h b/soc/silabs/silabs_s1/efr32mg12p/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h rename to soc/silabs/silabs_s1/efr32mg12p/soc_pinmap.h diff --git a/soc/silabs/silabs_s2/Kconfig.soc b/soc/silabs/silabs_s2/Kconfig.soc new file mode 100644 index 00000000000..c8926b83e6e --- /dev/null +++ b/soc/silabs/silabs_s2/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_SILABS_S2 + bool + select SOC_VENDOR_SILABS + +rsource "*/Kconfig.soc" diff --git a/soc/silabs/silabs_s2/efr32bg22/Kconfig b/soc/silabs/silabs_s2/efr32bg22/Kconfig new file mode 100644 index 00000000000..75747fd76aa --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg22/Kconfig @@ -0,0 +1,25 @@ +# Silicon Labs EFR32BG22 (Blue Gecko) MCU series + +# Copyright (c) 2021 Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG22 + select ARM + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_FPU + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_HAS_RADIO + select SOC_GECKO_GPIO + select SOC_GECKO_CMU + select SOC_GECKO_CORE + select SOC_GECKO_DEV_INIT + select SOC_GECKO_SE + select HAS_PM + +config SOC_GECKO_SDID + default 205 if SOC_SERIES_EFR32BG22 diff --git a/soc/silabs/silabs_s2/efr32bg22/Kconfig.defconfig b/soc/silabs/silabs_s2/efr32bg22/Kconfig.defconfig new file mode 100644 index 00000000000..d0cdff43ea6 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg22/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Silicon Labs EFR32BG22 (Blue Gecko) MCU configuration options + +# Copyright (c) 2021 Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32BG22 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 60 + +config PM + select COUNTER + select UART_INTERRUPT_DRIVEN + +config GPIO_GECKO + default y + +endif # SOC_SERIES_EFR32BG22 diff --git a/soc/silabs/silabs_s2/efr32bg22/Kconfig.soc b/soc/silabs/silabs_s2/efr32bg22/Kconfig.soc new file mode 100644 index 00000000000..5625510eccb --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg22/Kconfig.soc @@ -0,0 +1,23 @@ +# Silicon Labs EFR32BG22 (Blue Gecko) MCU series + +# Copyright (c) 2021 Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG22 + bool + select SOC_FAMILY_SILABS_S2 + help + EFR32BG22P Series MCU + +config SOC_PART_NUMBER_EFR32BG22C224F512IM40 + bool + select SOC_SERIES_EFR32BG22 + +config SOC_SERIES + default "efr32bg22" if SOC_SERIES_EFR32BG22 + +config SOC + default "efr32bg22c224f512im40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 + +config SOC_PART_NUMBER + default "EFR32BG22C224F512IM40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 diff --git a/soc/arm/silabs_exx32/efr32bg22/soc.h b/soc/silabs/silabs_s2/efr32bg22/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32bg22/soc.h rename to soc/silabs/silabs_s2/efr32bg22/soc.h diff --git a/soc/silabs/silabs_s2/efr32bg27/Kconfig b/soc/silabs/silabs_s2/efr32bg27/Kconfig new file mode 100644 index 00000000000..69825f9b539 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg27/Kconfig @@ -0,0 +1,24 @@ +# Silicon Labs EFR32BG27 (Blue Gecko) MCU series + +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG27 + select ARM + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_FPU + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_HAS_RADIO + select SOC_GECKO_CMU + select SOC_GECKO_CORE + select SOC_GECKO_DEV_INIT + select SOC_GECKO_SE + select HAS_PM + +config SOC_GECKO_SDID + default 230 if SOC_SERIES_EFR32BG27 diff --git a/soc/silabs/silabs_s2/efr32bg27/Kconfig.defconfig b/soc/silabs/silabs_s2/efr32bg27/Kconfig.defconfig new file mode 100644 index 00000000000..a997408c74e --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg27/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Silicon Labs EFR32BG27 (Blue Gecko) MCU configuration options + +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32BG27 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 66 + +config PM + select COUNTER + +config GPIO_GECKO + default y + +endif # SOC_SERIES_EFR32BG27 diff --git a/soc/silabs/silabs_s2/efr32bg27/Kconfig.soc b/soc/silabs/silabs_s2/efr32bg27/Kconfig.soc new file mode 100644 index 00000000000..33998241d5a --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg27/Kconfig.soc @@ -0,0 +1,23 @@ +# Silicon Labs EFR32BG27 (Blue Gecko) MCU series + +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG27 + bool + select SOC_FAMILY_SILABS_S2 + help + EFR32BG27 Series MCU + +config SOC_PART_NUMBER_EFR32BG27C140F768IM40 + bool + select SOC_SERIES_EFR32BG27 + +config SOC_SERIES + default "efr32bg27" if SOC_SERIES_EFR32BG27 + +config SOC + default "efr32bg27c140f768im40" if SOC_PART_NUMBER_EFR32BG27C140F768IM40 + +config SOC_PART_NUMBER + default "EFR32BG27C140F768IM40" if SOC_PART_NUMBER_EFR32BG27C140F768IM40 diff --git a/soc/arm/silabs_exx32/efr32bg27/soc.h b/soc/silabs/silabs_s2/efr32bg27/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32bg27/soc.h rename to soc/silabs/silabs_s2/efr32bg27/soc.h diff --git a/soc/silabs/silabs_s2/efr32mg21/Kconfig b/soc/silabs/silabs_s2/efr32mg21/Kconfig new file mode 100644 index 00000000000..e63182b6efa --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg21/Kconfig @@ -0,0 +1,24 @@ +# Silicon Labs EFR32MG21 (Mighty Gecko) MCU line + +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG21 + select ARM + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select ARMV8_M_DSP + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select SOC_GECKO_HAS_RADIO + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_SE + select HAS_PM + +config SOC_GECKO_SDID + default 200 if SOC_SERIES_EFR32MG21 diff --git a/soc/silabs/silabs_s2/efr32mg21/Kconfig.defconfig b/soc/silabs/silabs_s2/efr32mg21/Kconfig.defconfig new file mode 100644 index 00000000000..76555bbaa1c --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg21/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Silicon Labs EFR32MG21 (Might Gecko) series configuration options + +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32MG21 + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 61 + +config GPIO_GECKO + default y + depends on GPIO || LOG_BACKEND_SWO + +endif # SOC_SERIES_EFR32MG21 diff --git a/soc/silabs/silabs_s2/efr32mg21/Kconfig.soc b/soc/silabs/silabs_s2/efr32mg21/Kconfig.soc new file mode 100644 index 00000000000..abdfaf79625 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg21/Kconfig.soc @@ -0,0 +1,23 @@ +# Silicon Labs EFR32MG21 (Mighty Gecko) MCU line + +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG21 + bool + select SOC_FAMILY_SILABS_S2 + help + EFR32MG21 Series MCU + +config SOC_PART_NUMBER_EFR32MG21A020F1024IM32 + bool + select SOC_SERIES_EFR32MG21 + +config SOC_SERIES + default "efr32mg21" if SOC_SERIES_EFR32MG21 + +config SOC + default "efr32mg21a020f1024im32" if SOC_PART_NUMBER_EFR32MG21A020F1024IM32 + +config SOC_PART_NUMBER + default "EFR32MG21A020F1024IM32" if SOC_PART_NUMBER_EFR32MG21A020F1024IM32 diff --git a/soc/silabs/silabs_s2/efr32mg21/soc.h b/soc/silabs/silabs_s2/efr32mg21/soc.h new file mode 100644 index 00000000000..90b93a0acd1 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg21/soc.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros for the EFR32MG21 SoC + * + */ + +#ifndef _SILABS_EFR32MG21_SOC_H +#define _SILABS_EFR32MG21_SOC_H + +#include + +#ifndef _ASMLANGUAGE + +#include + +#include "soc_pinmap.h" +#include "../common/soc_gpio.h" + + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SILABS_EFR32MG21_SOC_H */ diff --git a/soc/silabs/silabs_s2/efr32mg21/soc_pinmap.h b/soc/silabs/silabs_s2/efr32mg21/soc_pinmap.h new file mode 100644 index 00000000000..1f38208d0d3 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg21/soc_pinmap.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Silabs EFR32MG21 MCU pin definitions. + * + * This file contains pin configuration data required by different MCU + * modules to correctly configure GPIO controller. + */ + +#ifndef _SILABS_EFR32MG21_SOC_PINMAP_H_ +#define _SILABS_EFR32MG21_SOC_PINMAP_H_ + +#include + +#ifdef CONFIG_LOG_BACKEND_SWO +#define PIN_SWO { gpioPortA, 3, gpioModePushPull, 1 } +#endif /* CONFIG_LOG_BACKEND_SWO */ + +#endif /* _SILABS_EFR32MG21_SOC_PINMAP_H_ */ diff --git a/soc/silabs/silabs_s2/efr32mg24/Kconfig b/soc/silabs/silabs_s2/efr32mg24/Kconfig new file mode 100644 index 00000000000..eb8c1ea6673 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg24/Kconfig @@ -0,0 +1,26 @@ +# Silicon Labs EFR32MG24 (Mighty Gecko) MCU line + +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG24 + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_CORTEX_M_HAS_DWT + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select SOC_GECKO_HAS_RADIO + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_DEV_INIT + select SOC_GECKO_SE + select HAS_PM + +config SOC_GECKO_SDID + default 215 if SOC_SERIES_EFR32MG24 diff --git a/soc/silabs/silabs_s2/efr32mg24/Kconfig.defconfig b/soc/silabs/silabs_s2/efr32mg24/Kconfig.defconfig new file mode 100644 index 00000000000..34428b46915 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg24/Kconfig.defconfig @@ -0,0 +1,22 @@ +# Silicon Labs EFR32MG24 (Mighty Gecko) MCU configuration options + +# Copyright (c) 2021 Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32MG24 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 75 + +config PM + default n + select COUNTER + select UART_INTERRUPT_DRIVEN if SERIAL_SUPPORT_INTERRUPT + +choice PM_POLICY + default PM_POLICY_DEFAULT + depends on PM +endchoice + +endif # SOC_SERIES_EFR32MG24 diff --git a/soc/silabs/silabs_s2/efr32mg24/Kconfig.soc b/soc/silabs/silabs_s2/efr32mg24/Kconfig.soc new file mode 100644 index 00000000000..ae2cd2f26fb --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg24/Kconfig.soc @@ -0,0 +1,29 @@ +# Silicon Labs EFR32MG24 (Mighty Gecko) MCU line + +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG24 + bool + select SOC_FAMILY_SILABS_S2 + help + EFR32MG24 Series MCU + +config SOC_PART_NUMBER_EFR32MG24B220F1536IM48 + bool + select SOC_SERIES_EFR32MG24 + +config SOC_PART_NUMBER_EFR32MG24B310F1536IM48 + bool + select SOC_SERIES_EFR32MG24 + +config SOC_SERIES + default "efr32mg24" if SOC_SERIES_EFR32MG24 + +config SOC + default "efr32mg24b220f1536im48" if SOC_PART_NUMBER_EFR32MG24B220F1536IM48 + default "efr32mg24b310f1536im48" if SOC_PART_NUMBER_EFR32MG24B310F1536IM48 + +config SOC_PART_NUMBER + default "EFR32MG24B220F1536IM48" if SOC_PART_NUMBER_EFR32MG24B220F1536IM48 + default "EFR32MG24B310F1536IM48" if SOC_PART_NUMBER_EFR32MG24B310F1536IM48 diff --git a/soc/silabs/silabs_s2/efr32mg24/soc.h b/soc/silabs/silabs_s2/efr32mg24/soc.h new file mode 100644 index 00000000000..210526c1109 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg24/soc.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros for the EFR32MG24 SoC + * + */ + +#ifndef _SILABS_EFR32MG24_SOC_H +#define _SILABS_EFR32MG24_SOC_H + +#include + +#ifndef _ASMLANGUAGE + +#include + +#include "soc_pinmap.h" +#include "../common/soc_gpio.h" + +/* Add include for DTS generated information */ +#include + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SILABS_EFR32MG24_SOC_H */ diff --git a/soc/silabs/silabs_s2/efr32mg24/soc_pinmap.h b/soc/silabs/silabs_s2/efr32mg24/soc_pinmap.h new file mode 100644 index 00000000000..37c1924599f --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg24/soc_pinmap.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Silabs EFR32MG24 MCU pin definitions. + * + * This file contains pin configuration data required by different MCU + * modules to correctly configure GPIO controller. + */ + +#ifndef _SILABS_EFR32MG24_SOC_PINMAP_H_ +#define _SILABS_EFR32MG24_SOC_PINMAP_H_ + +#include + +#ifdef CONFIG_LOG_BACKEND_SWO +#define PIN_SWO { gpioPortA, 3, gpioModePushPull, 1 } +#endif /* CONFIG_LOG_BACKEND_SWO */ + +#endif /* _SILABS_EFR32MG24_SOC_PINMAP_H_ */ diff --git a/soc/silabs/soc.yml b/soc/silabs/soc.yml new file mode 100644 index 00000000000..d6b2cc7866a --- /dev/null +++ b/soc/silabs/soc.yml @@ -0,0 +1,56 @@ +family: + - name: silabs_s0 + series: + - name: efm32wg + socs: + - name: efm32wg990f256 + - name: efm32hg + socs: + - name: efm32hg322f64 + - name: silabs_s1 + series: + - name: efm32pg1b + socs: + - name: efm32pg1b200f256gm48 + - name: efr32fg1p + socs: + - name: efr32fg1p133f256gm48 + - name: efm32pg12b + socs: + - name: efm32pg12b500f1024gl125 + - name: efr32bg13p + socs: + - name: efr32bg13p632f512gm48 + - name: efr32fg13p + socs: + - name: efr32fg13p233f512gm48 + - name: efm32jg12b + socs: + - name: efm32jg12b500f1024gl125 + - name: efr32mg12p + socs: + - name: efr32mg12p332f1024gl125 + - name: efr32mg12p432f1024gl125 + - name: efr32mg12p433f1024gm68 + - name: efm32gg11b + socs: + - name: efm32gg11b820f2048gl192 + - name: efm32gg11b820f2048gm64 + - name: efm32gg12b + socs: + - name: efm32gg12b810f1024gm64 + - name: silabs_s2 + series: + - name: efr32mg21 + socs: + - name: efr32mg21a020f1024im32 + - name: efr32bg22 + socs: + - name: efr32bg22c224f512im40 + - name: efr32mg24 + socs: + - name: efr32mg24b220f1536im48 + - name: efr32mg24b310f1536im48 + - name: efr32bg27 + socs: + - name: efr32bg27c140f768im40 diff --git a/soc/sparc/Kconfig b/soc/sparc/Kconfig deleted file mode 100644 index de68a730048..00000000000 --- a/soc/sparc/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -config SPARC_CASA - default y if SPARC - -config SOC_SPARC_LEON - bool diff --git a/soc/sparc/gr716a/CMakeLists.txt b/soc/sparc/gr716a/CMakeLists.txt deleted file mode 100644 index 888e386817e..00000000000 --- a/soc/sparc/gr716a/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(../leon3/idle.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/sparc/gr716a/Kconfig.defconfig b/soc/sparc/gr716a/Kconfig.defconfig deleted file mode 100644 index ef9bf0ca778..00000000000 --- a/soc/sparc/gr716a/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -if SOC_GR716A - -config SOC - default "gr716a" - -config SPARC_NWIN - default 31 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 50000000 - -if FLASH - -config SPI - default y - -config SPI_NOR - default y - -config SPI_GRLIB_SPIMCTRL - default y - -endif - -endif diff --git a/soc/sparc/gr716a/Kconfig.soc b/soc/sparc/gr716a/Kconfig.soc deleted file mode 100644 index d74f04a28eb..00000000000 --- a/soc/sparc/gr716a/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -config SOC_GR716A - bool "GR716A LEON3 fault-tolerant microcontroller" - select SPARC - select SOC_SPARC_LEON - select CPU_HAS_FPU diff --git a/soc/sparc/leon3/CMakeLists.txt b/soc/sparc/leon3/CMakeLists.txt deleted file mode 100644 index 722526c00cf..00000000000 --- a/soc/sparc/leon3/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(idle.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/sparc/leon3/Kconfig.defconfig b/soc/sparc/leon3/Kconfig.defconfig deleted file mode 100644 index 52a71b68275..00000000000 --- a/soc/sparc/leon3/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LEON3 - -config SOC - default "leon3" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 40000000 - -endif diff --git a/soc/sparc/leon3/Kconfig.soc b/soc/sparc/leon3/Kconfig.soc deleted file mode 100644 index f3e01822092..00000000000 --- a/soc/sparc/leon3/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -config SOC_LEON3 - bool "A LEON3 SOC which you can configure" - select SPARC - select SOC_SPARC_LEON diff --git a/soc/st/stm32/CMakeLists.txt b/soc/st/stm32/CMakeLists.txt new file mode 100644 index 00000000000..cda6e428374 --- /dev/null +++ b/soc/st/stm32/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) diff --git a/soc/st/stm32/Kconfig b/soc/st/stm32/Kconfig new file mode 100644 index 00000000000..363f772f74d --- /dev/null +++ b/soc/st/stm32/Kconfig @@ -0,0 +1,84 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_STM32 + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select STM32_ENABLE_DEBUG_SLEEP_STOP if DEBUG || ZTEST + select BUILD_OUTPUT_HEX + +if SOC_FAMILY_STM32 + +rsource "*/Kconfig" + +# STM32 wide symbols definitions + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CCM := zephyr,ccm + +config STM32_CCM + def_bool $(dt_chosen_enabled,$(DT_CHOSEN_Z_CCM)) + +config USE_STM32_ASSERT + depends on ASSERT + bool "STM32Cube HAL and LL drivers asserts" + help + Enable asserts in STM32Cube HAL and LL drivers. + +config STM32_BACKUP_SRAM + bool "STM32 Backup SRAM" + depends on DT_HAS_ST_STM32_BACKUP_SRAM_ENABLED + help + Enable support for STM32 backup SRAM. + +config STM32_ENABLE_DEBUG_SLEEP_STOP + bool "Allow debugger attach in stop/sleep Mode" + help + Some STM32 parts disable the DBGMCU in sleep/stop modes because + of power consumption. As a side-effects this prevents + debuggers from attaching w/o resetting the target. This + effectivly destroys the use-case of `west attach`. Also + SEGGER RTT and similar technologies need this. + +choice POWER_SUPPLY_CHOICE + prompt "STM32 power supply configuration" + default POWER_SUPPLY_LDO + depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32U5X || \ + SOC_STM32WBA55XX + +config POWER_SUPPLY_LDO + bool "LDO supply" + +config POWER_SUPPLY_DIRECT_SMPS + bool "Direct SMPS supply" + +config POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO + bool "SMPS 1.8V supplies LDO (no external supply)" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO + bool "SMPS 2.5V supplies LDO (no external supply)" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO + bool "External SMPS 1.8V supply, supplies LDO" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO + bool "External SMPS 2.5V supply, supplies LDO" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT + bool "External SMPS 1.8V supply and bypass" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT + bool "External SMPS 2.5V supply and bypass" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_EXTERNAL_SOURCE + bool "Bypass" + depends on SOC_SERIES_STM32H7X + +endchoice + +endif # SOC_FAMILY_STM32 diff --git a/soc/st/stm32/Kconfig.defconfig b/soc/st/stm32/Kconfig.defconfig new file mode 100644 index 00000000000..b214f103723 --- /dev/null +++ b/soc/st/stm32/Kconfig.defconfig @@ -0,0 +1,63 @@ +# ST Microelectronics STM32 all MCU lines + +# Copyright (c) 2017, I-SENSE group of ICCS +# SPDX-License-Identifier: Apache-2.0 + +# Default configurations appplied tp the whole STM32 family + +if SOC_FAMILY_STM32 + +rsource "*/Kconfig.defconfig" + +config CORTEX_M_SYSTICK + default n if STM32_LPTIM_TIMER + +DT_STM32_RCC_PATH := $(dt_nodelabel_path,rcc) +DT_STM32_RCC_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_RCC_PATH),clock-frequency) + +DT_ST_PRESCALER := st,prescaler +DT_STM32_LPTIM_PATH := $(dt_nodelabel_path,stm32_lp_tick_source) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" + +config LOG_BACKEND_SWO_REF_FREQ_HZ + default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" + depends on LOG_BACKEND_SWO + +# set the tick per sec as a divider of the LPTIM clock source +# with a minimum value of 4096 for SYS_CLOCK_TICKS_PER_SEC to keep +# SYS_CLOCK_TICKS_PER_SEC not too high compared to the LPTIM counter clock +config SYS_CLOCK_TICKS_PER_SEC + default 4096 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16 + default 2048 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16 + default 1024 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32 + default 512 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64 + default 256 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128 + depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSE + +config SYS_CLOCK_TICKS_PER_SEC + default 4000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16 + default 2000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16 + default 1000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32 + default 500 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64 + default 250 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128 + depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSI + +config CLOCK_CONTROL_STM32_CUBE + default y + depends on CLOCK_CONTROL + +config CLOCK_CONTROL_INIT_PRIORITY + default 1 + depends on CLOCK_CONTROL + +config MEMC_STM32 + default y + depends on MEMC + +# Get flash configuration for NS image from dts flash partition +config USE_DT_CODE_PARTITION + default y if TRUSTED_EXECUTION_NONSECURE + +endif # SOC_FAMILY_STM32 diff --git a/soc/st/stm32/Kconfig.soc b/soc/st/stm32/Kconfig.soc new file mode 100644 index 00000000000..dce2d0d6557 --- /dev/null +++ b/soc/st/stm32/Kconfig.soc @@ -0,0 +1,12 @@ +# ST Microelectronics STM32 MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_STM32 + bool + +config SOC_FAMILY + default "stm32" if SOC_FAMILY_STM32 + +rsource "*/Kconfig.soc" diff --git a/soc/st/stm32/common/CMakeLists.txt b/soc/st/stm32/common/CMakeLists.txt new file mode 100644 index 00000000000..abc9793b2c5 --- /dev/null +++ b/soc/st/stm32/common/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + stm32cube_hal.c + soc_config.c +) + +zephyr_linker_sources_ifdef(CONFIG_STM32_CCM SECTIONS ccm.ld) + +zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c) +zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld) diff --git a/soc/arm/st_stm32/common/ccm.ld b/soc/st/stm32/common/ccm.ld similarity index 100% rename from soc/arm/st_stm32/common/ccm.ld rename to soc/st/stm32/common/ccm.ld diff --git a/soc/arm/st_stm32/common/pinctrl_soc.h b/soc/st/stm32/common/pinctrl_soc.h similarity index 100% rename from soc/arm/st_stm32/common/pinctrl_soc.h rename to soc/st/stm32/common/pinctrl_soc.h diff --git a/soc/arm/st_stm32/common/soc_config.c b/soc/st/stm32/common/soc_config.c similarity index 100% rename from soc/arm/st_stm32/common/soc_config.c rename to soc/st/stm32/common/soc_config.c diff --git a/soc/arm/st_stm32/common/stm32_backup_sram.c b/soc/st/stm32/common/stm32_backup_sram.c similarity index 100% rename from soc/arm/st_stm32/common/stm32_backup_sram.c rename to soc/st/stm32/common/stm32_backup_sram.c diff --git a/soc/arm/st_stm32/common/stm32_backup_sram.ld b/soc/st/stm32/common/stm32_backup_sram.ld similarity index 100% rename from soc/arm/st_stm32/common/stm32_backup_sram.ld rename to soc/st/stm32/common/stm32_backup_sram.ld diff --git a/soc/arm/st_stm32/common/stm32_hsem.h b/soc/st/stm32/common/stm32_hsem.h similarity index 100% rename from soc/arm/st_stm32/common/stm32_hsem.h rename to soc/st/stm32/common/stm32_hsem.h diff --git a/soc/arm/st_stm32/common/stm32cube_hal.c b/soc/st/stm32/common/stm32cube_hal.c similarity index 100% rename from soc/arm/st_stm32/common/stm32cube_hal.c rename to soc/st/stm32/common/stm32cube_hal.c diff --git a/soc/st/stm32/soc.yml b/soc/st/stm32/soc.yml new file mode 100644 index 00000000000..304ab56acfc --- /dev/null +++ b/soc/st/stm32/soc.yml @@ -0,0 +1,192 @@ +family: +- name: stm32 + series: + - name: stm32c0x + socs: + - name: stm32c031xx + - name: stm32f0x + socs: + - name: stm32f030x6 + - name: stm32f030x8 + - name: stm32f030xc + - name: stm32f031x6 + - name: stm32f042x6 + - name: stm32f051x8 + - name: stm32f070xb + - name: stm32f072xb + - name: stm32f091xc + - name: stm32f098xx + - name: stm32f1x + socs: + - name: stm32f100xb + - name: stm32f100xe + - name: stm32f103xb + - name: stm32f103xe + - name: stm32f105xc + - name: stm32f107xc + - name: stm32f2x + socs: + - name: stm32f205xx + - name: stm32f207xx + - name: stm32f3x + socs: + - name: stm32f302x8 + - name: stm32f302xc + - name: stm32f303x8 + - name: stm32f303xb + - name: stm32f303xc + - name: stm32f303xe + - name: stm32f334x8 + - name: stm32f373xc + - name: stm32f4x + socs: + - name: stm32f401xc + - name: stm32f401xe + - name: stm32f405xx + - name: stm32f407xx + - name: stm32f410rx + - name: stm32f411xe + - name: stm32f412cx + - name: stm32f412rx + - name: stm32f412vx + - name: stm32f412zx + - name: stm32f413xx + - name: stm32f415xx + - name: stm32f417xx + - name: stm32f423xx + - name: stm32f427xx + - name: stm32f429xx + - name: stm32f437xx + - name: stm32f446xx + - name: stm32f469xx + - name: stm32f7x + socs: + - name: stm32f722xx + - name: stm32f723xx + - name: stm32f745xx + - name: stm32f746xx + - name: stm32f750xx + - name: stm32f756xx + - name: stm32f765xx + - name: stm32f767xx + - name: stm32f769xx + - name: stm32g0x + socs: + - name: stm32g030xx + - name: stm32g031xx + - name: stm32g041xx + - name: stm32g050xx + - name: stm32g051xx + - name: stm32g061xx + - name: stm32g070xx + - name: stm32g071xx + - name: stm32g081xx + - name: stm32g0b0xx + - name: stm32g0b1xx + - name: stm32g0c1xx + - name: stm32g4x + socs: + - name: stm32g431xx + - name: stm32g441xx + - name: stm32g473xx + - name: stm32g474xx + - name: stm32g483xx + - name: stm32g484xx + - name: stm32g491xx + - name: stm32g4a1xx + - name: stm32h5x + socs: + - name: stm32h503xx + - name: stm32h562xx + - name: stm32h563xx + - name: stm32h573xx + - name: stm32h7x + socs: + - name: stm32h7a3xx + - name: stm32h7b0xx + - name: stm32h7b3xx + - name: stm32h723xx + - name: stm32h725xx + - name: stm32h730xx + - name: stm32h735xx + - name: stm32h743xx + - name: stm32h745xx + cpuclusters: + - name: m7 + - name: m4 + - name: stm32h747xx + cpuclusters: + - name: m7 + - name: m4 + - name: stm32h750xx + - name: stm32h753xx + - name: stm32l0x + socs: + - name: stm32l010x4 + - name: stm32l010x6 + - name: stm32l010x8 + - name: stm32l010xb + - name: stm32l011xx + - name: stm32l031xx + - name: stm32l051xx + - name: stm32l053xx + - name: stm32l071xx + - name: stm32l072xx + - name: stm32l073xx + - name: stm32l081xx + - name: stm32l1x + socs: + - name: stm32l151xb + - name: stm32l151xba + - name: stm32l151xc + - name: stm32l152xc + - name: stm32l152xe + - name: stm32l4x + socs: + - name: stm32l412xx + - name: stm32l422xx + - name: stm32l431xx + - name: stm32l432xx + - name: stm32l433xx + - name: stm32l451xx + - name: stm32l452xx + - name: stm32l462xx + - name: stm32l471xx + - name: stm32l475xx + - name: stm32l476xx + - name: stm32l486xx + - name: stm32l496xx + - name: stm32l4a6xx + - name: stm32l4p5xx + - name: stm32l4q5xx + - name: stm32l4s5xx + - name: stm32l4r5xx + - name: stm32l4r9xx + - name: stm32l5x + socs: + - name: stm32l552xx + - name: stm32l562xx + - name: stm32mp1x + socs: + - name: stm32mp157cxx + - name: stm32u5x + socs: + - name: stm32u5a5xx + - name: stm32u5a9xx + - name: stm32u575xx + - name: stm32u585xx + - name: stm32u595xx + - name: stm32u599xx + - name: stm32wbx + socs: + - name: stm32wb55xx + - name: stm32wbax + socs: + - name: stm32wba52xx + - name: stm32wba55xx + - name: stm32wlx + socs: + - name: stm32wle4xx + - name: stm32wle5xx + - name: stm32wl54xx + - name: stm32wl55xx diff --git a/soc/st/stm32/stm32c0x/CMakeLists.txt b/soc/st/stm32/stm32c0x/CMakeLists.txt new file mode 100644 index 00000000000..eebd281cd96 --- /dev/null +++ b/soc/st/stm32/stm32c0x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32c0x/Kconfig b/soc/st/stm32/stm32c0x/Kconfig new file mode 100644 index 00000000000..8d8c1b89d18 --- /dev/null +++ b/soc/st/stm32/stm32c0x/Kconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32C0 MCU series + +# Copyright (c) 2023 Benjamin Björnsson +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32C0X + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + select HAS_STM32CUBE + select CPU_CORTEX_M_HAS_SYSTICK diff --git a/soc/st/stm32/stm32c0x/Kconfig.defconfig b/soc/st/stm32/stm32c0x/Kconfig.defconfig new file mode 100644 index 00000000000..b960c560bc5 --- /dev/null +++ b/soc/st/stm32/stm32c0x/Kconfig.defconfig @@ -0,0 +1,10 @@ +# STMicroelectronics STM32C0 MCU line + +# Copyright (c) 2023 Benjamin Björnsson +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32C0X + +rsource "Kconfig.defconfig.stm32c0*" + +endif # SOC_SERIES_STM32C0X diff --git a/soc/arm/st_stm32/stm32c0/Kconfig.defconfig.stm32c031xx b/soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c031xx similarity index 86% rename from soc/arm/st_stm32/stm32c0/Kconfig.defconfig.stm32c031xx rename to soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c031xx index 5a84b4ff31a..96f2cc8da2a 100644 --- a/soc/arm/st_stm32/stm32c0/Kconfig.defconfig.stm32c031xx +++ b/soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c031xx @@ -5,9 +5,6 @@ if SOC_STM32C031XX -config SOC - default "stm32c031xx" - config NUM_IRQS default 29 diff --git a/soc/st/stm32/stm32c0x/Kconfig.soc b/soc/st/stm32/stm32c0x/Kconfig.soc new file mode 100644 index 00000000000..c91158abbb1 --- /dev/null +++ b/soc/st/stm32/stm32c0x/Kconfig.soc @@ -0,0 +1,18 @@ +# STMicroelectronics STM32C0 MCU line + +# Copyright (c) 2023 Benjamin Björnsson +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32C0X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32c0x" if SOC_SERIES_STM32C0X + +config SOC_STM32C031XX + bool + select SOC_SERIES_STM32C0X + +config SOC + default "stm32c031xx" if SOC_STM32C031XX diff --git a/soc/arm/st_stm32/stm32c0/soc.c b/soc/st/stm32/stm32c0x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32c0/soc.c rename to soc/st/stm32/stm32c0x/soc.c diff --git a/soc/arm/st_stm32/stm32c0/soc.h b/soc/st/stm32/stm32c0x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32c0/soc.h rename to soc/st/stm32/stm32c0x/soc.h diff --git a/soc/st/stm32/stm32f0x/CMakeLists.txt b/soc/st/stm32/stm32f0x/CMakeLists.txt new file mode 100644 index 00000000000..0ce31c70062 --- /dev/null +++ b/soc/st/stm32/stm32f0x/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# The vector table must be placed at the start of SRAM +zephyr_linker_sources_ifdef(CONFIG_SRAM_VECTOR_TABLE + RAM_SECTIONS + SORT_KEY 0 + sram_vector_table.ld +) +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32f0x/Kconfig b/soc/st/stm32/stm32f0x/Kconfig new file mode 100644 index 00000000000..54eb854963a --- /dev/null +++ b/soc/st/stm32/stm32f0x/Kconfig @@ -0,0 +1,11 @@ +# ST Microelectronics STM32F0 MCU series + +# Copyright (c) 2017 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F0X + select ARM + select CPU_CORTEX_M0 + select CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_STM32CUBE diff --git a/soc/st/stm32/stm32f0x/Kconfig.defconfig b/soc/st/stm32/stm32f0x/Kconfig.defconfig new file mode 100644 index 00000000000..23687080b8f --- /dev/null +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig @@ -0,0 +1,20 @@ +# ST Microelectronics STM32F0 MCU line + +# Copyright (c) 2017 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F0 series + +if SOC_SERIES_STM32F0X + +rsource "Kconfig.defconfig.stm32f0*" + +config SRAM_VECTOR_TABLE + default y + +# adjust the fallback because of the LSI oscillator characteristics +config TASK_WDT_HW_FALLBACK_DELAY + depends on TASK_WDT_HW_FALLBACK + default 100 + +endif # SOC_SERIES_STM32F0X diff --git a/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x4 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x4 new file mode 100644 index 00000000000..3492ea11c99 --- /dev/null +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x4 @@ -0,0 +1,9 @@ +# Copyright (c) 2019 Antony Pavlov +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F030X4 + +config NUM_IRQS + default 28 + +endif # SOC_STM32F030X4 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x6 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x6 similarity index 83% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x6 rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x6 index b65641f1232..f43a019d232 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x6 +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x6 @@ -3,9 +3,6 @@ if SOC_STM32F030X6 -config SOC - default "stm32f030x6" - config NUM_IRQS default 28 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x8 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x8 similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x8 rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x8 index f7263ed17ec..5fe9da0085d 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x8 +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x8 @@ -5,9 +5,6 @@ if SOC_STM32F030X8 -config SOC - default "stm32f030x8" - config NUM_IRQS default 29 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030xc b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030xc similarity index 82% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030xc rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030xc index 6885f82295c..29a31c57bdd 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030xc +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030xc @@ -3,9 +3,6 @@ if SOC_STM32F030XC -config SOC - default "stm32f030xc" - config NUM_IRQS default 31 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f031x6 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f031x6 similarity index 86% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f031x6 rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f031x6 index c7f2d37b3e5..90c240908d4 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f031x6 +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f031x6 @@ -5,9 +5,6 @@ if SOC_STM32F031X6 -config SOC - default "stm32f031x6" - config NUM_IRQS default 28 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f042x6 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f042x6 similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f042x6 rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f042x6 index fe4a08966b5..eacebeedb7a 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f042x6 +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f042x6 @@ -5,9 +5,6 @@ if SOC_STM32F042X6 -config SOC - default "stm32f042x6" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f051x8 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f051x8 similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f051x8 rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f051x8 index 66f76cc9b24..d5af754f15e 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f051x8 +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f051x8 @@ -5,9 +5,6 @@ if SOC_STM32F051X8 -config SOC - default "stm32f051x8" - config NUM_IRQS default 31 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f070xb b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f070xb similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f070xb rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f070xb index 6c6a67a0297..35b7c18a61e 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f070xb +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f070xb @@ -5,9 +5,6 @@ if SOC_STM32F070XB -config SOC - default "stm32f070xb" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f072xx b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f072xx similarity index 86% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f072xx rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f072xx index 8bfed8c7b10..8b8b5a178c2 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f072xx +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f072xx @@ -5,9 +5,6 @@ if SOC_STM32F072X8 || SOC_STM32F072XB -config SOC - default "stm32f072xb" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f091xc b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f091xc similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f091xc rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f091xc index 9d17769f793..ba3a9e80588 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f091xc +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f091xc @@ -5,9 +5,6 @@ if SOC_STM32F091XC -config SOC - default "stm32f091xc" - config NUM_IRQS default 31 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f098xx b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f098xx similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f098xx rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f098xx index 0a877cb26f7..f82775d9ee9 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f098xx +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f098xx @@ -5,9 +5,6 @@ if SOC_STM32F098XX -config SOC - default "stm32f098xx" - config NUM_IRQS default 31 diff --git a/soc/st/stm32/stm32f0x/Kconfig.soc b/soc/st/stm32/stm32f0x/Kconfig.soc new file mode 100644 index 00000000000..d9f4d96a847 --- /dev/null +++ b/soc/st/stm32/stm32f0x/Kconfig.soc @@ -0,0 +1,73 @@ +# ST Microelectronics STM32F0 MCU line + +# Copyright (c) 2017 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F0X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f0x" if SOC_SERIES_STM32F0X + +config SOC_STM32F030X4 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F030X6 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F030X8 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F030XC + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F031X6 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F042X6 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F051X8 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F070XB + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F072X8 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F072XB + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F091XC + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F098XX + bool + select SOC_SERIES_STM32F0X + +# STM32F0 Cube package advises to use 'stm32f030x6' code +# for both STM32F030x4 and STM32F030x6 +config SOC + default "stm32f030x6" if SOC_STM32F030X4 || SOC_STM32F030X6 + default "stm32f030x8" if SOC_STM32F030X8 + default "stm32f030xc" if SOC_STM32F030XC + default "stm32f031x6" if SOC_STM32F031X6 + default "stm32f042x6" if SOC_STM32F042X6 + default "stm32f051x8" if SOC_STM32F051X8 + default "stm32f070xb" if SOC_STM32F070XB + default "stm32f072xb" if SOC_STM32F072X8 || SOC_STM32F072XB + default "stm32f091xc" if SOC_STM32F091XC + default "stm32f098xx" if SOC_STM32F098XX diff --git a/soc/arm/st_stm32/stm32f0/soc.c b/soc/st/stm32/stm32f0x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f0/soc.c rename to soc/st/stm32/stm32f0x/soc.c diff --git a/soc/arm/st_stm32/stm32f0/soc.h b/soc/st/stm32/stm32f0x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f0/soc.h rename to soc/st/stm32/stm32f0x/soc.h diff --git a/soc/arm/st_stm32/stm32f0/sram_vector_table.ld b/soc/st/stm32/stm32f0x/sram_vector_table.ld similarity index 100% rename from soc/arm/st_stm32/stm32f0/sram_vector_table.ld rename to soc/st/stm32/stm32f0x/sram_vector_table.ld diff --git a/soc/st/stm32/stm32f1x/CMakeLists.txt b/soc/st/stm32/stm32f1x/CMakeLists.txt new file mode 100644 index 00000000000..eebd281cd96 --- /dev/null +++ b/soc/st/stm32/stm32f1x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32f1x/Kconfig b/soc/st/stm32/stm32f1x/Kconfig new file mode 100644 index 00000000000..13680c516c1 --- /dev/null +++ b/soc/st/stm32/stm32f1x/Kconfig @@ -0,0 +1,11 @@ +# ST Microelectronics STM32F1 MCU series + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F1X + select ARM + select CPU_CORTEX_M3 + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_SWO diff --git a/soc/st/stm32/stm32f1x/Kconfig.defconfig b/soc/st/stm32/stm32f1x/Kconfig.defconfig new file mode 100644 index 00000000000..0ca499ef81f --- /dev/null +++ b/soc/st/stm32/stm32f1x/Kconfig.defconfig @@ -0,0 +1,17 @@ +# ST Microelectronics STM32F1 MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F1 series + +if SOC_SERIES_STM32F1X + +rsource "Kconfig.defconfig.stm32f1*" + +# adjust the fallback because of the LSI oscaillator characteristics +config TASK_WDT_HW_FALLBACK_DELAY + depends on TASK_WDT_HW_FALLBACK + default 200 + +endif # SOC_SERIES_STM32F1X diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f100xx b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f100xx similarity index 100% rename from soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f100xx rename to soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f100xx diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xx b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f103xx similarity index 81% rename from soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xx rename to soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f103xx index 10a141e0d98..d4d30f8a25a 100644 --- a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xx +++ b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f103xx @@ -5,9 +5,6 @@ if SOC_STM32F103XB || SOC_STM32F103X8 -config SOC - default "stm32f103xb" - config NUM_IRQS default 43 @@ -15,9 +12,6 @@ endif # SOC_STM32F103XB || SOC_STM32F103X8 if SOC_STM32F103XE -config SOC - default "stm32f103xe" - config NUM_IRQS default 60 diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f105xx b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f105xx similarity index 84% rename from soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f105xx rename to soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f105xx index b7963eacb6a..ac031d653d1 100644 --- a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f105xx +++ b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f105xx @@ -5,10 +5,6 @@ if SOC_STM32F105XC || SOC_STM32F105XB -config SOC - string - default "stm32f105xc" - config NUM_IRQS int default 68 diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f107xc b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f107xc similarity index 84% rename from soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f107xc rename to soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f107xc index 5ce4d9f6f1d..944cd2df2ae 100644 --- a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f107xc +++ b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f107xc @@ -5,9 +5,6 @@ if SOC_STM32F107XC -config SOC - default "stm32f107xc" - config NUM_IRQS default 68 diff --git a/soc/st/stm32/stm32f1x/Kconfig.soc b/soc/st/stm32/stm32f1x/Kconfig.soc new file mode 100644 index 00000000000..38258ce187e --- /dev/null +++ b/soc/st/stm32/stm32f1x/Kconfig.soc @@ -0,0 +1,76 @@ +# ST Microelectronics STM32F1 MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F1X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f1x" if SOC_SERIES_STM32F1X + +config SOC_STM32F100XB + bool + select SOC_SERIES_STM32F1X + +config SOC_STM32F100XE + bool + select SOC_SERIES_STM32F1X + +config SOC_STM32F103XE + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_DENSITY_DEVICE + +config SOC_STM32F103XB + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_DENSITY_DEVICE + +config SOC_STM32F103X8 + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_DENSITY_DEVICE + +config SOC_STM32F105XB + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + +config SOC_STM32F105XC + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + +config SOC_STM32F107XC + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + +config SOC_STM32F10X_DENSITY_DEVICE + bool + help + STM32F101xx, STM32F102xx, STM32F103xx: + * Low density Value line devices + * Medium density Value line devices + * High density Value line devices + * XL-density devices Value line devices + +config SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + bool + help + Connectivity line devices are STM32F105xx and STM32F107xx + microcontrollers. They are intended for applications where + connectivity and real-time performances are required such as + industrial control, control panels for security applications, UPS or + home audio. For STM32F107xx also the Ethernet MAC is available. + +config SOC + default "stm32f100xb" if SOC_STM32F100XB + default "stm32f100xe" if SOC_STM32F100XE + default "stm32f103xb" if SOC_STM32F103XB || SOC_STM32F103X8 + default "stm32f103xe" if SOC_STM32F103XE + default "stm32f105xc" if SOC_STM32F105XC || SOC_STM32F105XB + default "stm32f107xc" if SOC_STM32F107XC diff --git a/soc/arm/st_stm32/stm32f1/soc.c b/soc/st/stm32/stm32f1x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f1/soc.c rename to soc/st/stm32/stm32f1x/soc.c diff --git a/soc/arm/st_stm32/stm32f1/soc.h b/soc/st/stm32/stm32f1x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f1/soc.h rename to soc/st/stm32/stm32f1x/soc.h diff --git a/soc/st/stm32/stm32f2x/CMakeLists.txt b/soc/st/stm32/stm32f2x/CMakeLists.txt new file mode 100644 index 00000000000..eebd281cd96 --- /dev/null +++ b/soc/st/stm32/stm32f2x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32f2x/Kconfig b/soc/st/stm32/stm32f2x/Kconfig new file mode 100644 index 00000000000..4821425c09c --- /dev/null +++ b/soc/st/stm32/stm32f2x/Kconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32F2X MCU series + +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F2X + select ARM + select CPU_CORTEX_M3 + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_SWO + select CPU_HAS_ARM_MPU diff --git a/soc/st/stm32/stm32f2x/Kconfig.defconfig b/soc/st/stm32/stm32f2x/Kconfig.defconfig new file mode 100644 index 00000000000..eff10490e63 --- /dev/null +++ b/soc/st/stm32/stm32f2x/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32F2 MCU line + +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F2 series + +if SOC_SERIES_STM32F2X + +rsource "Kconfig.defconfig.stm32f2*" + +endif # SOC_SERIES_STM32F2X diff --git a/soc/st/stm32/stm32f2x/Kconfig.defconfig.stm32f205xx b/soc/st/stm32/stm32f2x/Kconfig.defconfig.stm32f205xx new file mode 100644 index 00000000000..d045e6d4560 --- /dev/null +++ b/soc/st/stm32/stm32f2x/Kconfig.defconfig.stm32f205xx @@ -0,0 +1,11 @@ +# STMicroelectronics stm32f205 MCU + +# Copyright (c) 2021 Manuel Forcen +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F207XX + +config NUM_IRQS + default 81 + +endif diff --git a/soc/st/stm32/stm32f2x/Kconfig.soc b/soc/st/stm32/stm32f2x/Kconfig.soc new file mode 100644 index 00000000000..f37690b0fa0 --- /dev/null +++ b/soc/st/stm32/stm32f2x/Kconfig.soc @@ -0,0 +1,23 @@ +# STMicroelectronics stm32f2 MCU line + +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F2X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f2x" if SOC_SERIES_STM32F2X + +config SOC_STM32F205XX + bool + select SOC_SERIES_STM32F2X + +config SOC_STM32F207XX + bool + select SOC_SERIES_STM32F2X + +config SOC + default "stm32f205xx" if SOC_STM32F205XX + default "stm32f207xx" if SOC_STM32F207XX diff --git a/soc/arm/st_stm32/stm32f2/soc.c b/soc/st/stm32/stm32f2x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f2/soc.c rename to soc/st/stm32/stm32f2x/soc.c diff --git a/soc/arm/st_stm32/stm32f2/soc.h b/soc/st/stm32/stm32f2x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f2/soc.h rename to soc/st/stm32/stm32f2x/soc.h diff --git a/soc/st/stm32/stm32f3x/CMakeLists.txt b/soc/st/stm32/stm32f3x/CMakeLists.txt new file mode 100644 index 00000000000..eebd281cd96 --- /dev/null +++ b/soc/st/stm32/stm32f3x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32f3x/Kconfig b/soc/st/stm32/stm32f3x/Kconfig new file mode 100644 index 00000000000..50b83a2a4b6 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32F3 MCU series + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F3X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select HAS_SWO diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig b/soc/st/stm32/stm32f3x/Kconfig.defconfig new file mode 100644 index 00000000000..e1e87a8e5e5 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32F3 MCU line + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F3 series + +if SOC_SERIES_STM32F3X + +rsource "Kconfig.defconfig.stm32f3*" + +endif # SOC_SERIES_STM32F3X diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302x8 b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302x8 new file mode 100644 index 00000000000..ca69c9eec62 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302x8 @@ -0,0 +1,11 @@ +# STMicroelectronics STM32F302X8 MCU + +# Copyright (c) 2018 Seitz & Associates +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F302X8 + +config NUM_IRQS + default 82 + +endif # SOC_STM32F302X8 diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302xc b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302xc new file mode 100644 index 00000000000..9a5268d563e --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302xc @@ -0,0 +1,14 @@ +# STMicroelectronics STM32F302XC MCU + +# Copyright (c) 2022, SECO Spa +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F302XC + +config NUM_IRQS + default 82 + +config CPU_HAS_ARM_MPU + default y + +endif # SOC_STM32F302XC diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x(b-c) b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x(b-c) similarity index 80% rename from soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x(b-c) rename to soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x(b-c) index 752bef89690..5971b6f4c24 100644 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x(b-c) +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x(b-c) @@ -1,4 +1,4 @@ -# ST Microelectronics STM32F303XC MCU +# STMicroelectronics STM32F303XC MCU # Copyright (c) 2016 RnDity Sp. z o.o. # SPDX-License-Identifier: Apache-2.0 @@ -7,10 +7,10 @@ # size differ). if SOC_STM32F303XB || SOC_STM32F303XC -config SOC - default "stm32f303xc" - config NUM_IRQS default 82 +config CPU_HAS_ARM_MPU + default y + endif # SOC_STM32F303XB || SOC_STM32F303XC diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x8 b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x8 similarity index 78% rename from soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x8 rename to soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x8 index e585815feb8..827744b868b 100644 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x8 +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x8 @@ -1,4 +1,4 @@ -# ST Microelectronics STM32F303x8 MCU +# STMicroelectronics STM32F303x8 MCU # Copyright (c) 2020 Sebastian Schwabe # Fabian Paschke @@ -6,9 +6,6 @@ if SOC_STM32F303X8 -config SOC - default "stm32f303x8" - config NUM_IRQS default 82 diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303xe b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303xe new file mode 100644 index 00000000000..839c30d4d1a --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303xe @@ -0,0 +1,14 @@ +# STMicroelectronics STM32F303XC MCU + +# Copyright (c) 2020 Paul M. Bendixen +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F303XE + +config NUM_IRQS + default 85 + +config CPU_HAS_ARM_MPU + default y + +endif # SOC_STM32F303XE diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f334x8 b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f334x8 new file mode 100644 index 00000000000..b115e9d07e4 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f334x8 @@ -0,0 +1,11 @@ +# STMicroelectronics STM32F334X8 MCU + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F334X8 + +config NUM_IRQS + default 82 + +endif # SOC_STM32F334X8 diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f373xc b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f373xc new file mode 100644 index 00000000000..b3f0dd03d91 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f373xc @@ -0,0 +1,14 @@ +# STMicroelectronics STM32F373XC MCU + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F373XC + +config NUM_IRQS + default 82 + +config CPU_HAS_ARM_MPU + default y + +endif # SOC_STM32F373XC diff --git a/soc/st/stm32/stm32f3x/Kconfig.soc b/soc/st/stm32/stm32f3x/Kconfig.soc new file mode 100644 index 00000000000..cb26880f98d --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.soc @@ -0,0 +1,53 @@ +# STMicroelectronics STM32F3 MCU line + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F3X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f3x" if SOC_SERIES_STM32F3X + +config SOC_STM32F302X8 + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F302XC + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F303X8 + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F303XB + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F303XC + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F303XE + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F334X8 + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F373XC + bool + select SOC_SERIES_STM32F3X + +config SOC + default "stm32f302x8" if SOC_STM32F302X8 + default "stm32f302xc" if SOC_STM32F302XC + default "stm32f303x8" if SOC_STM32F303X8 + default "stm32f303xb" if SOC_STM32F303XB + default "stm32f303xc" if SOC_STM32F303XC + default "stm32f303xe" if SOC_STM32F303XE + default "stm32f334x8" if SOC_STM32F334X8 + default "stm32f373xc" if SOC_STM32F373XC diff --git a/soc/arm/st_stm32/stm32f3/soc.c b/soc/st/stm32/stm32f3x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f3/soc.c rename to soc/st/stm32/stm32f3x/soc.c diff --git a/soc/arm/st_stm32/stm32f3/soc.h b/soc/st/stm32/stm32f3x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f3/soc.h rename to soc/st/stm32/stm32f3x/soc.h diff --git a/soc/st/stm32/stm32f4x/CMakeLists.txt b/soc/st/stm32/stm32f4x/CMakeLists.txt new file mode 100644 index 00000000000..ea800d26565 --- /dev/null +++ b/soc/st/stm32/stm32f4x/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) diff --git a/soc/st/stm32/stm32f4x/Kconfig b/soc/st/stm32/stm32f4x/Kconfig new file mode 100644 index 00000000000..92bba334775 --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig @@ -0,0 +1,14 @@ +# STMicroelectronics STM32F4 MCU series + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F4X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select HAS_SWO + select HAS_PM diff --git a/soc/st/stm32/stm32f4x/Kconfig.defconfig b/soc/st/stm32/stm32f4x/Kconfig.defconfig new file mode 100644 index 00000000000..26fc770096c --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig @@ -0,0 +1,30 @@ +# STMicroelectronics STM32F4 MCU line + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F4 series + +if SOC_SERIES_STM32F4X + +rsource "Kconfig.defconfig.stm32f4*" + +# adjust the fallback because of the LSI oscaillator characteristics +config TASK_WDT_HW_FALLBACK_DELAY + depends on TASK_WDT_HW_FALLBACK + default 200 + +if PM + +config COUNTER + default y + +config COUNTER_RTC_STM32_SUBSECONDS + default y if DT_HAS_ST_STM32_RTC_ENABLED + +config IDLE_STACK_SIZE + default 512 + +endif # PM + +endif # SOC_SERIES_STM32F4X diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xc b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xc similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xc rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xc index 21549f883fa..2149fac901e 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xc +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xc @@ -5,9 +5,6 @@ if SOC_STM32F401XC -config SOC - default "stm32f401xc" - config NUM_IRQS default 85 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xe b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xe similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xe rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xe index 643d071c5e9..60e85df4d93 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xe +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xe @@ -5,9 +5,6 @@ if SOC_STM32F401XE -config SOC - default "stm32f401xe" - config NUM_IRQS default 85 diff --git a/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f405xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f405xx new file mode 100644 index 00000000000..646517bfbed --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f405xx @@ -0,0 +1,11 @@ +# ST STM32F405XX MCU configuration options + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F405XX + +config NUM_IRQS + default 82 + +endif # SOC_STM32F405XX diff --git a/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f407xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f407xx new file mode 100644 index 00000000000..ee8c67085aa --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f407xx @@ -0,0 +1,11 @@ +# ST STM32F407XX MCU configuration options + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F407XE || SOC_STM32F407XG + +config NUM_IRQS + default 82 + +endif diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f410xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f410xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f410xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f410xx index dde123f6173..ecd4452303c 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f410xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f410xx @@ -5,9 +5,6 @@ if SOC_STM32F410RX -config SOC - default "stm32f410rx" - config NUM_IRQS default 97 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f411xe b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f411xe similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f411xe rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f411xe index e83c7bbcbab..f403532b493 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f411xe +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f411xe @@ -5,9 +5,6 @@ if SOC_STM32F411XE -config SOC - default "stm32f411xe" - config NUM_IRQS default 86 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412rx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412rx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412rx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412rx index 94d4a1bc0a8..32df074def1 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412rx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412rx @@ -5,9 +5,6 @@ if SOC_STM32F412RX -config SOC - default "stm32f412rx" - config NUM_IRQS default 97 diff --git a/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412xx new file mode 100644 index 00000000000..e86d8c1f0b4 --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412xx @@ -0,0 +1,11 @@ +# ST STM32F412XX MCU configuration options + +# Copyright (c) 2024 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F412CX || SOC_STM32F412VX || SOC_STM32F412ZX + +config NUM_IRQS + default 97 + +endif diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f413xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f413xx similarity index 85% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f413xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f413xx index 568afdddf84..ef74ff5ff77 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f413xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f413xx @@ -5,9 +5,6 @@ if SOC_STM32F413XX -config SOC - default "stm32f413xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f415xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f415xx similarity index 85% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f415xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f415xx index 8b9be0ce0d6..b79b20746a1 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f415xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f415xx @@ -5,9 +5,6 @@ if SOC_STM32F415XX -config SOC - default "stm32f415xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f417xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f417xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f417xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f417xx index beb1c1b1db2..6bc928003ca 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f417xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f417xx @@ -5,9 +5,6 @@ if SOC_STM32F417XX -config SOC - default "stm32f417xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f423xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f423xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f423xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f423xx index c7f6d30aeb1..36b4d0987d7 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f423xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f423xx @@ -5,9 +5,6 @@ if SOC_STM32F423XX -config SOC - default "stm32f423xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f427xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f427xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f427xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f427xx index 46415d356d4..66a1ae8963b 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f427xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f427xx @@ -5,9 +5,6 @@ if SOC_STM32F427XX -config SOC - default "stm32f427xx" - config NUM_IRQS default 91 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f429xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f429xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f429xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f429xx index f68bf7bedd0..681dd9b0a8f 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f429xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f429xx @@ -5,9 +5,6 @@ if SOC_STM32F429XX -config SOC - default "stm32f429xx" - config NUM_IRQS default 91 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f437xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f437xx similarity index 86% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f437xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f437xx index bb20242284e..60aeb2807d4 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f437xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f437xx @@ -5,9 +5,6 @@ if SOC_STM32F437XX -config SOC - default "stm32f437xx" - config NUM_IRQS default 91 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f446xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f446xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f446xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f446xx index 6c3f98140a8..bafecebf0f5 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f446xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f446xx @@ -5,9 +5,6 @@ if SOC_STM32F446XX -config SOC - default "stm32f446xx" - config NUM_IRQS default 97 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f469xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f469xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f469xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f469xx index e9b17f18886..b8e768c86cd 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f469xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f469xx @@ -5,9 +5,6 @@ if SOC_STM32F469XX -config SOC - default "stm32f469xx" - config NUM_IRQS default 93 diff --git a/soc/st/stm32/stm32f4x/Kconfig.soc b/soc/st/stm32/stm32f4x/Kconfig.soc new file mode 100644 index 00000000000..0f830e8a365 --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig.soc @@ -0,0 +1,113 @@ +# STMicroelectronics STM32F4 MCU line + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F4X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f4x" if SOC_SERIES_STM32F4X + +config SOC_STM32F401XC + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F401XE + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F405XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F407XE + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F407XG + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F410RX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F411XE + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F412CX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F412RX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F412VX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F412ZX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F413XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F415XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F417XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F423XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F427XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F429XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F437XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F446XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F469XX + bool + select SOC_SERIES_STM32F4X + +config SOC + default "stm32f401xc" if SOC_STM32F401XC + default "stm32f401xe" if SOC_STM32F401XE + default "stm32f405xx" if SOC_STM32F405XX + default "stm32f407xx" if SOC_STM32F407XE + default "stm32f407xx" if SOC_STM32F407XG + default "stm32f410rx" if SOC_STM32F410RX + default "stm32f411xe" if SOC_STM32F411XE + default "stm32f412cx" if SOC_STM32F412CX + default "stm32f412rx" if SOC_STM32F412RX + default "stm32f412vx" if SOC_STM32F412VX + default "stm32f412zx" if SOC_STM32F412ZX + default "stm32f413xx" if SOC_STM32F413XX + default "stm32f415xx" if SOC_STM32F415XX + default "stm32f417xx" if SOC_STM32F417XX + default "stm32f423xx" if SOC_STM32F423XX + default "stm32f427xx" if SOC_STM32F427XX + default "stm32f429xx" if SOC_STM32F429XX + default "stm32f437xx" if SOC_STM32F437XX + default "stm32f446xx" if SOC_STM32F446XX + default "stm32f469xx" if SOC_STM32F469XX diff --git a/soc/arm/st_stm32/stm32f4/power.c b/soc/st/stm32/stm32f4x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32f4/power.c rename to soc/st/stm32/stm32f4x/power.c diff --git a/soc/arm/st_stm32/stm32f4/soc.c b/soc/st/stm32/stm32f4x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f4/soc.c rename to soc/st/stm32/stm32f4x/soc.c diff --git a/soc/arm/st_stm32/stm32f4/soc.h b/soc/st/stm32/stm32f4x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f4/soc.h rename to soc/st/stm32/stm32f4x/soc.h diff --git a/soc/st/stm32/stm32f7x/CMakeLists.txt b/soc/st/stm32/stm32f7x/CMakeLists.txt new file mode 100644 index 00000000000..eebd281cd96 --- /dev/null +++ b/soc/st/stm32/stm32f7x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32f7x/Kconfig b/soc/st/stm32/stm32f7x/Kconfig new file mode 100644 index 00000000000..1af203c4680 --- /dev/null +++ b/soc/st/stm32/stm32f7x/Kconfig @@ -0,0 +1,15 @@ +# ST Microelectronics STM32F7 MCU series + +# Copyright (c) 2018 Yurii Hamann +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F7X + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select HAS_SWO diff --git a/soc/st/stm32/stm32f7x/Kconfig.defconfig b/soc/st/stm32/stm32f7x/Kconfig.defconfig new file mode 100644 index 00000000000..ef1d4ba5283 --- /dev/null +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ST Microelectronics STM32F7 MCU line + +# Copyright (c) 2018 Yurii Hamann +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F7 series + +if SOC_SERIES_STM32F7X + +rsource "Kconfig.defconfig.stm32f7*" + +endif # SOC_SERIES_STM32F7X diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f722xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f722xx similarity index 84% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f722xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f722xx index 5b85551f939..1ab0276fd91 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f722xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f722xx @@ -6,9 +6,6 @@ if SOC_STM32F722XX -config SOC - default "stm32f722xx" - config NUM_IRQS default 104 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f723xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f723xx similarity index 84% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f723xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f723xx index ff7db64ebec..e5195cf396e 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f723xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f723xx @@ -5,9 +5,6 @@ if SOC_STM32F723XX -config SOC - default "stm32f723xx" - config NUM_IRQS default 104 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f745xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f745xx similarity index 85% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f745xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f745xx index ec2b00093fc..83344e1fae4 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f745xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f745xx @@ -5,9 +5,6 @@ if SOC_STM32F745XX -config SOC - default "stm32f745xx" - config NUM_IRQS default 98 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f746xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f746xx similarity index 84% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f746xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f746xx index 11c00936039..a3024dbe00e 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f746xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f746xx @@ -5,9 +5,6 @@ if SOC_STM32F746XX -config SOC - default "stm32f746xx" - config NUM_IRQS default 98 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f750xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f750xx similarity index 84% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f750xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f750xx index d73314e11a4..1b228f95f57 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f750xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f750xx @@ -5,9 +5,6 @@ if SOC_STM32F750XX -config SOC - default "stm32f750xx" - config NUM_IRQS default 98 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f756xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f756xx similarity index 84% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f756xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f756xx index ff59bd3b9b5..e9f64abf7bb 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f756xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f756xx @@ -5,9 +5,6 @@ if SOC_STM32F756XX -config SOC - default "stm32f756xx" - config NUM_IRQS default 98 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f765xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f765xx similarity index 75% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f765xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f765xx index 37b8d537939..5f0ef8314d7 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f765xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f765xx @@ -5,10 +5,10 @@ if SOC_STM32F765XX -config SOC - default "stm32f765xx" - config NUM_IRQS - default 110 + default 100 + +config CPU_HAS_FPU_DOUBLE_PRECISION + default y endif # SOC_STM32F765XX diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f767xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f767xx similarity index 80% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f767xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f767xx index e816a061933..f906cd30831 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f767xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f767xx @@ -5,10 +5,10 @@ if SOC_STM32F767XX -config SOC - default "stm32f767xx" - config NUM_IRQS default 110 +config CPU_HAS_FPU_DOUBLE_PRECISION + default y + endif # SOC_STM32F767XX diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f769xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f769xx similarity index 80% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f769xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f769xx index 4b90ad5a659..9a709388c67 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f769xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f769xx @@ -5,10 +5,10 @@ if SOC_STM32F769XX -config SOC - default "stm32f769xx" - config NUM_IRQS default 110 +config CPU_HAS_FPU_DOUBLE_PRECISION + default y + endif # SOC_STM32F769XX diff --git a/soc/st/stm32/stm32f7x/Kconfig.soc b/soc/st/stm32/stm32f7x/Kconfig.soc new file mode 100644 index 00000000000..4ade7ca8fbf --- /dev/null +++ b/soc/st/stm32/stm32f7x/Kconfig.soc @@ -0,0 +1,61 @@ +# ST Microelectronics STM32F7 MCU line + +# Copyright (c) 2018 Yurii Hamann +# Copyright (c) 2022, Rtone. +# Copyright (c) 2023, Rahul Arasikere. +# Copyright (c) 2023 Evan Perry Grove +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F7X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f7x" if SOC_SERIES_STM32F7X + +config SOC_STM32F722XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F723XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F745XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F746XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F756XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F750XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F765XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F767XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F769XX + bool + select SOC_SERIES_STM32F7X + +config SOC + default "stm32f722xx" if SOC_STM32F722XX + default "stm32f723xx" if SOC_STM32F723XX + default "stm32f745xx" if SOC_STM32F745XX + default "stm32f746xx" if SOC_STM32F746XX + default "stm32f750xx" if SOC_STM32F750XX + default "stm32f756xx" if SOC_STM32F756XX + default "stm32f765xx" if SOC_STM32F765XX + default "stm32f767xx" if SOC_STM32F767XX + default "stm32f769xx" if SOC_STM32F769XX diff --git a/soc/arm/st_stm32/stm32f7/soc.c b/soc/st/stm32/stm32f7x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f7/soc.c rename to soc/st/stm32/stm32f7x/soc.c diff --git a/soc/arm/st_stm32/stm32f7/soc.h b/soc/st/stm32/stm32f7x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f7/soc.h rename to soc/st/stm32/stm32f7x/soc.h diff --git a/soc/st/stm32/stm32g0x/CMakeLists.txt b/soc/st/stm32/stm32g0x/CMakeLists.txt new file mode 100644 index 00000000000..65706e73bfa --- /dev/null +++ b/soc/st/stm32/stm32g0x/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2021 G-Technologies Sdn. Bhd. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32g0x/Kconfig b/soc/st/stm32/stm32g0x/Kconfig new file mode 100644 index 00000000000..8fac199d153 --- /dev/null +++ b/soc/st/stm32/stm32g0x/Kconfig @@ -0,0 +1,14 @@ +# STMicroelectronics STM32G0 MCU series + +# Copyright (c) 2019 Philippe Retornaz +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32G0X + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + select HAS_STM32CUBE + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_PM diff --git a/soc/st/stm32/stm32g0x/Kconfig.defconfig b/soc/st/stm32/stm32g0x/Kconfig.defconfig new file mode 100644 index 00000000000..e4978d0cfe4 --- /dev/null +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32G0 MCU line + +# Copyright (c) 2019 Philippe Retornaz +# Copyright (c) 2019 STMicroelectronics +# Copyright (c) 2021 G-Technologies Sdn. Bhd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32G0X + +rsource "Kconfig.defconfig.stm32g0*" + +endif # SOC_SERIES_STM32G0X diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g030xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g030xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g030xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g030xx index c72bb705866..4800b2584f5 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g030xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g030xx @@ -5,9 +5,6 @@ if SOC_STM32G030XX -config SOC - default "stm32g030xx" - config NUM_IRQS default 29 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g031xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g031xx similarity index 83% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g031xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g031xx index 9b7236b9853..d6890a5b372 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g031xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g031xx @@ -5,9 +5,6 @@ if SOC_STM32G031XX -config SOC - default "stm32g031xx" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g041xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g041xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g041xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g041xx index dc63f9e2520..327f7a42261 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g041xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g041xx @@ -5,9 +5,6 @@ if SOC_STM32G041XX -config SOC - default "stm32g041xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g050xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g050xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g050xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g050xx index f2e15925046..efaab9634cc 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g050xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g050xx @@ -5,9 +5,6 @@ if SOC_STM32G050XX -config SOC - default "stm32g050xx" - config NUM_IRQS default 29 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g051xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g051xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g051xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g051xx index 67a06d1c139..88177fb506f 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g051xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g051xx @@ -5,9 +5,6 @@ if SOC_STM32G051XX -config SOC - default "stm32g051xx" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g061xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g061xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g061xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g061xx index 4d052632eb6..b81c12efefa 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g061xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g061xx @@ -5,9 +5,6 @@ if SOC_STM32G061XX -config SOC - default "stm32g061xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g070xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g070xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g070xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g070xx index d7eb915534f..502dfe952fb 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g070xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g070xx @@ -5,9 +5,6 @@ if SOC_STM32G070XX -config SOC - default "stm32g070xx" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g071xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g071xx similarity index 87% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g071xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g071xx index a1814043d4d..3c953d99823 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g071xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g071xx @@ -6,9 +6,6 @@ if SOC_STM32G071XX -config SOC - default "stm32g071xx" - config NUM_IRQS default 31 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g081xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g081xx similarity index 86% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g081xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g081xx index ab46bc38c9d..f308c47e668 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g081xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g081xx @@ -6,9 +6,6 @@ if SOC_STM32G081XX -config SOC - default "stm32g081xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b0xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b0xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b0xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b0xx index 3be972e356a..02829267715 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b0xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b0xx @@ -5,9 +5,6 @@ if SOC_STM32G0B0XX -config SOC - default "stm32g0b0xx" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b1xx similarity index 90% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b1xx index 767cea2556c..9a226fc0ad7 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b1xx @@ -5,9 +5,6 @@ if SOC_STM32G0B1XX -config SOC - default "stm32g0b1xx" - config NUM_IRQS default 31 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0c1xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0c1xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0c1xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0c1xx index fed2a1f0932..0e1e696b72a 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0c1xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0c1xx @@ -5,9 +5,6 @@ if SOC_STM32G0C1XX -config SOC - default "stm32g0c1xx" - config NUM_IRQS default 32 diff --git a/soc/st/stm32/stm32g0x/Kconfig.soc b/soc/st/stm32/stm32g0x/Kconfig.soc new file mode 100644 index 00000000000..cc1b5e58a6c --- /dev/null +++ b/soc/st/stm32/stm32g0x/Kconfig.soc @@ -0,0 +1,75 @@ +# STMicroelectronics STM32G0 MCU line + +# Copyright (c) 2019 Philippe Retornaz +# Copyright (c) 2019 STMicroelectronics +# Copyright (c) 2020 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32G0X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32g0x" if SOC_SERIES_STM32G0X + +config SOC_STM32G030XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G031XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G041XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G050XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G051XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G061XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G070XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G071XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G081XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G0B0XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G0B1XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G0C1XX + bool + select SOC_SERIES_STM32G0X + +config SOC + default "stm32g030xx" if SOC_STM32G030XX + default "stm32g031xx" if SOC_STM32G031XX + default "stm32g041xx" if SOC_STM32G041XX + default "stm32g050xx" if SOC_STM32G050XX + default "stm32g051xx" if SOC_STM32G051XX + default "stm32g061xx" if SOC_STM32G061XX + default "stm32g070xx" if SOC_STM32G070XX + default "stm32g071xx" if SOC_STM32G071XX + default "stm32g081xx" if SOC_STM32G081XX + default "stm32g0b0xx" if SOC_STM32G0B0XX + default "stm32g0b1xx" if SOC_STM32G0B1XX + default "stm32g0c1xx" if SOC_STM32G0C1XX diff --git a/soc/arm/st_stm32/stm32g0/power.c b/soc/st/stm32/stm32g0x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32g0/power.c rename to soc/st/stm32/stm32g0x/power.c diff --git a/soc/arm/st_stm32/stm32g0/soc.c b/soc/st/stm32/stm32g0x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32g0/soc.c rename to soc/st/stm32/stm32g0x/soc.c diff --git a/soc/arm/st_stm32/stm32g0/soc.h b/soc/st/stm32/stm32g0x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32g0/soc.h rename to soc/st/stm32/stm32g0x/soc.h diff --git a/soc/st/stm32/stm32g4x/CMakeLists.txt b/soc/st/stm32/stm32g4x/CMakeLists.txt new file mode 100644 index 00000000000..cfbedf4ff85 --- /dev/null +++ b/soc/st/stm32/stm32g4x/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32g4x/Kconfig b/soc/st/stm32/stm32g4x/Kconfig new file mode 100644 index 00000000000..50aecbbca3c --- /dev/null +++ b/soc/st/stm32/stm32g4x/Kconfig @@ -0,0 +1,15 @@ +# STMicroelectronics STM32G4 MCU series + +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32G4X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL + select HAS_PM + select HAS_SWO diff --git a/soc/st/stm32/stm32g4x/Kconfig.defconfig b/soc/st/stm32/stm32g4x/Kconfig.defconfig new file mode 100644 index 00000000000..0a9488d7e4c --- /dev/null +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig @@ -0,0 +1,18 @@ +# STMicroelectronics STM32G4 MCU line + +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32G4X + +rsource "Kconfig.defconfig.stm32g4*" + +if PM +config PM_DEVICE + default y + +config STM32_LPTIM_TIMER + default y +endif # PM + +endif # SOC_SERIES_STM32G4X diff --git a/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g431xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g431xx new file mode 100644 index 00000000000..73d1c70368e --- /dev/null +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g431xx @@ -0,0 +1,11 @@ +# STMicroelectronics STM32G431XX MCU + +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32G431XX + +config NUM_IRQS + default 102 + +endif # SOC_STM32G431XX diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g441xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g441xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g441xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g441xx index 3630ac865d2..ec5a0092cd0 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g441xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g441xx @@ -5,9 +5,6 @@ if SOC_STM32G441XX -config SOC - default "stm32g441xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g473xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g473xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g473xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g473xx index 108ca2aecf1..46caf1f4bc0 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g473xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g473xx @@ -5,9 +5,6 @@ if SOC_STM32G473XX -config SOC - default "stm32g473xx" - config NUM_IRQS default 102 diff --git a/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g474xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g474xx new file mode 100644 index 00000000000..dac9df141e1 --- /dev/null +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g474xx @@ -0,0 +1,11 @@ +# STMicroelectronics STM32G474XX MCU + +# Copyright (c) 2019 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32G474XX + +config NUM_IRQS + default 102 + +endif # SOC_STM32G474XX diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g483xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g483xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g483xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g483xx index 5564372b3bb..b0cd7a2b55d 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g483xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g483xx @@ -5,9 +5,6 @@ if SOC_STM32G483XX -config SOC - default "stm32g483xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g484xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g484xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g484xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g484xx index 2c5b500833c..ed1165bef1f 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g484xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g484xx @@ -5,9 +5,6 @@ if SOC_STM32G484XX -config SOC - default "stm32g484xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g491xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g491xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g491xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g491xx index a8cbbe859f0..33a14e1c58e 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g491xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g491xx @@ -5,9 +5,6 @@ if SOC_STM32G491XX -config SOC - default "stm32g491xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g4a1xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g4a1xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g4a1xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g4a1xx index 280eb0790a2..f472e8323e6 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g4a1xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g4a1xx @@ -5,9 +5,6 @@ if SOC_STM32G4A1XX -config SOC - default "stm32g4a1xx" - config NUM_IRQS default 102 diff --git a/soc/st/stm32/stm32g4x/Kconfig.soc b/soc/st/stm32/stm32g4x/Kconfig.soc new file mode 100644 index 00000000000..110fe503fab --- /dev/null +++ b/soc/st/stm32/stm32g4x/Kconfig.soc @@ -0,0 +1,53 @@ +# STMicroelectronics STM32G4 MCU line + +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32G4X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32g4x" if SOC_SERIES_STM32G4X + +config SOC_STM32G431XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G441XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G473XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G474XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G483XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G484XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G491XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G4A1XX + bool + select SOC_SERIES_STM32G4X + +config SOC + default "stm32g431xx" if SOC_STM32G431XX + default "stm32g441xx" if SOC_STM32G441XX + default "stm32g473xx" if SOC_STM32G473XX + default "stm32g474xx" if SOC_STM32G474XX + default "stm32g483xx" if SOC_STM32G483XX + default "stm32g484xx" if SOC_STM32G484XX + default "stm32g491xx" if SOC_STM32G491XX + default "stm32g4a1xx" if SOC_STM32G4A1XX diff --git a/soc/arm/st_stm32/stm32g4/power.c b/soc/st/stm32/stm32g4x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32g4/power.c rename to soc/st/stm32/stm32g4x/power.c diff --git a/soc/st/stm32/stm32g4x/soc.c b/soc/st/stm32/stm32g4x/soc.c new file mode 100644 index 00000000000..c8d41f474f9 --- /dev/null +++ b/soc/st/stm32/stm32g4x/soc.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2019 Richard Osterloh + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for STM32G4 processor + */ + +#include +#include +#include +#include + +#include +#if defined(PWR_CR3_UCPD_DBDIS) +#include +#include +#endif /* PWR_CR3_UCPD_DBDIS */ + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int stm32g4_init(void) +{ + /* Update CMSIS SystemCoreClock variable (HCLK) */ + /* At reset, system core clock is set to 16 MHz from HSI */ + SystemCoreClock = 16000000; + + /* allow reflashing board */ + LL_DBGMCU_EnableDBGSleepMode(); + +#if defined(PWR_CR3_UCPD_DBDIS) + /* Disable USB Type-C dead battery pull-down behavior */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); + LL_PWR_DisableUCPDDeadBattery(); +#endif /* PWR_CR3_UCPD_DBDIS */ + return 0; +} + +SYS_INIT(stm32g4_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/st_stm32/stm32g4/soc.h b/soc/st/stm32/stm32g4x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32g4/soc.h rename to soc/st/stm32/stm32g4x/soc.h diff --git a/soc/st/stm32/stm32h5x/CMakeLists.txt b/soc/st/stm32/stm32h5x/CMakeLists.txt new file mode 100644 index 00000000000..eebd281cd96 --- /dev/null +++ b/soc/st/stm32/stm32h5x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32h5x/Kconfig b/soc/st/stm32/stm32h5x/Kconfig new file mode 100644 index 00000000000..9ff02424ebd --- /dev/null +++ b/soc/st/stm32/stm32h5x/Kconfig @@ -0,0 +1,16 @@ +# ST Microelectronics STM32H5 MCU series + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32H5X + select ARM + select CPU_CORTEX_M33 + select ARM_TRUSTZONE_M if !SOC_STM32H503XX + select CPU_HAS_ARM_SAU if !SOC_STM32H503XX + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_SWO diff --git a/soc/st/stm32/stm32h5x/Kconfig.defconfig b/soc/st/stm32/stm32h5x/Kconfig.defconfig new file mode 100644 index 00000000000..f8167440f33 --- /dev/null +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig @@ -0,0 +1,13 @@ +# ST Microelectronics STM32H5 MCU line + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32H5X + +rsource "Kconfig.defconfig.stm32h5*" + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_STM32H5X diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h503xx b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h503xx similarity index 84% rename from soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h503xx rename to soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h503xx index e7d7b508baa..fb6e125f87f 100644 --- a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h503xx +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h503xx @@ -5,9 +5,6 @@ if SOC_STM32H503XX -config SOC - default "stm32h503xx" - config NUM_IRQS default 134 diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h562xx b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h562xx similarity index 84% rename from soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h562xx rename to soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h562xx index eb76a2d7989..f7dc9451df0 100644 --- a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h562xx +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h562xx @@ -5,9 +5,6 @@ if SOC_STM32H562XX -config SOC - default "stm32h562xx" - config NUM_IRQS default 131 diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h563xx b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h563xx similarity index 84% rename from soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h563xx rename to soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h563xx index 94994a7d060..1a36a617e53 100644 --- a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h563xx +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h563xx @@ -5,9 +5,6 @@ if SOC_STM32H563XX -config SOC - default "stm32h563xx" - config NUM_IRQS default 131 diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h573xx b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h573xx similarity index 84% rename from soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h573xx rename to soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h573xx index d6641c126ec..af698c3e81c 100644 --- a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h573xx +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h573xx @@ -5,9 +5,6 @@ if SOC_STM32H573XX -config SOC - default "stm32h573xx" - config NUM_IRQS default 131 diff --git a/soc/st/stm32/stm32h5x/Kconfig.soc b/soc/st/stm32/stm32h5x/Kconfig.soc new file mode 100644 index 00000000000..f218ad10064 --- /dev/null +++ b/soc/st/stm32/stm32h5x/Kconfig.soc @@ -0,0 +1,33 @@ +# ST Microelectronics STM32H5 MCU line + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32H5X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32h5x" if SOC_SERIES_STM32H5X + +config SOC_STM32H503XX + bool + select SOC_SERIES_STM32H5X + +config SOC_STM32H562XX + bool + select SOC_SERIES_STM32H5X + +config SOC_STM32H563XX + bool + select SOC_SERIES_STM32H5X + +config SOC_STM32H573XX + bool + select SOC_SERIES_STM32H5X + +config SOC + default "stm32h503xx" if SOC_STM32H503XX + default "stm32h562xx" if SOC_STM32H562XX + default "stm32h563xx" if SOC_STM32H563XX + default "stm32h573xx" if SOC_STM32H573XX diff --git a/soc/arm/st_stm32/stm32h5/soc.c b/soc/st/stm32/stm32h5x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32h5/soc.c rename to soc/st/stm32/stm32h5x/soc.c diff --git a/soc/arm/st_stm32/stm32h5/soc.h b/soc/st/stm32/stm32h5x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32h5/soc.h rename to soc/st/stm32/stm32h5x/soc.h diff --git a/soc/st/stm32/stm32h7x/CMakeLists.txt b/soc/st/stm32/stm32h7x/CMakeLists.txt new file mode 100644 index 00000000000..b4ea68f3c47 --- /dev/null +++ b/soc/st/stm32/stm32h7x/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c) +zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M4 soc_m4.c) + +zephyr_sources(mpu_regions.c) +zephyr_linker_sources(SECTIONS sections.ld) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32h7x/Kconfig b/soc/st/stm32/stm32h7x/Kconfig new file mode 100644 index 00000000000..f72707ae006 --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig @@ -0,0 +1,82 @@ +# ST Microelectronics STM32H7 MCU series + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32H7X + select ARM + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select HAS_SWO + select USE_STM32_HAL_CORTEX + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7 + select CPU_HAS_ICACHE if CPU_CORTEX_M7 + select CPU_HAS_DCACHE if CPU_CORTEX_M7 + +config SOC_STM32H723XX + select CPU_CORTEX_M7 + +config SOC_STM32H725XX + select CPU_CORTEX_M7 + +config SOC_STM32H730XX + select CPU_CORTEX_M7 + +config SOC_STM32H730XXQ + select CPU_CORTEX_M7 + +config SOC_STM32H735XX + select CPU_CORTEX_M7 + +config SOC_STM32H743XX + select CPU_CORTEX_M7 + +config SOC_STM32H745XX_M7 + select CPU_CORTEX_M7 + +config SOC_STM32H745XX_M4 + select CPU_CORTEX_M4 + +config SOC_STM32H747XX_M7 + select CPU_CORTEX_M7 + +config SOC_STM32H747XX_M4 + select CPU_CORTEX_M4 + +config SOC_STM32H750XX + select CPU_CORTEX_M7 + +config SOC_STM32H753XX + select CPU_CORTEX_M7 + +config SOC_STM32H7A3XX + select CPU_CORTEX_M7 + +config SOC_STM32H7A3XXQ + select CPU_CORTEX_M7 + +config SOC_STM32H7B0XX + select CPU_CORTEX_M7 + +config SOC_STM32H7B0XXQ + select CPU_CORTEX_M7 + +config SOC_STM32H7B3XX + select CPU_CORTEX_M7 + +config SOC_STM32H7B3XXQ + select CPU_CORTEX_M7 + +if SOC_SERIES_STM32H7X + +config STM32H7_DUAL_CORE + bool "Dual Core" + +config STM32H7_BOOT_M4_AT_INIT + bool "Boot M4 core during M7 init independent of option byte BCM4." + default y + +endif # SOC_SERIES_STM32H7X diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig b/soc/st/stm32/stm32h7x/Kconfig.defconfig new file mode 100644 index 00000000000..790b1659c05 --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig @@ -0,0 +1,17 @@ +# ST Microelectronics STM32H7 MCU line + +# Copyright (c) 2019 Linaro Limited +# Copyright (c) 2022 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32H7 series + +if SOC_SERIES_STM32H7X + +rsource "Kconfig.defconfig.stm32h7*" + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + default 0x0 if !BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_STM32H7X diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h723xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h723xx similarity index 86% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h723xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h723xx index b640a00eeef..53acf7448b9 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h723xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h723xx @@ -5,9 +5,6 @@ if SOC_STM32H723XX -config SOC - default "stm32h723xx" - config NUM_IRQS default 163 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h725xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h725xx similarity index 84% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h725xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h725xx index b5e50ed4fa1..061ea62a2a3 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h725xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h725xx @@ -5,9 +5,6 @@ if SOC_STM32H725XX -config SOC - default "stm32h725xx" - config NUM_IRQS default 163 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h730xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h730xx similarity index 75% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h730xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h730xx index 51b110dbc9f..93befd25a9c 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h730xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h730xx @@ -6,10 +6,6 @@ if SOC_STM32H730XX || SOC_STM32H730XXQ -config SOC - default "stm32h730xxQ" if SOC_STM32H730XXQ - default "stm32h730xx" if SOC_STM32H730XX - config NUM_IRQS default 163 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h735xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h735xx similarity index 85% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h735xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h735xx index fec1b04d46e..33d0a741f89 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h735xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h735xx @@ -5,9 +5,6 @@ if SOC_STM32H735XX -config SOC - default "stm32h735xx" - config NUM_IRQS default 163 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h743xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h743xx similarity index 85% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h743xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h743xx index 3774f4f8a93..d54e5b0d6d5 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h743xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h743xx @@ -5,9 +5,6 @@ if SOC_STM32H743XX -config SOC - default "stm32h743xx" - config NUM_IRQS default 150 diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h745xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h745xx new file mode 100644 index 00000000000..feeba8cff1e --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h745xx @@ -0,0 +1,14 @@ +# ST STM32H745X MCU configuration options + +# Copyright (c) 2020 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H745XX_M7 || SOC_STM32H745XX_M4 + +config STM32H7_DUAL_CORE + default y + +config NUM_IRQS + default 150 + +endif # SOC_STM32H745XX_M7 || SOC_STM32H745XX_M4 diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h747xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h747xx new file mode 100644 index 00000000000..32496e0711e --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h747xx @@ -0,0 +1,14 @@ +# ST STM32H747X MCU configuration options + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H747XX_M7 || SOC_STM32H747XX_M4 + +config STM32H7_DUAL_CORE + default y + +config NUM_IRQS + default 150 + +endif # SOC_STM32H747XX_M7 || SOC_STM32H747XX_M7 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h750xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h750xx similarity index 85% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h750xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h750xx index 13d859aa53e..1d00fdc403b 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h750xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h750xx @@ -5,9 +5,6 @@ if SOC_STM32H750XX -config SOC - default "stm32h750xx" - config NUM_IRQS default 150 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h753xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h753xx similarity index 85% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h753xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h753xx index 20253b33784..06b08dfcdc2 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h753xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h753xx @@ -5,9 +5,6 @@ if SOC_STM32H753XX -config SOC - default "stm32h753xx" - config NUM_IRQS default 150 diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7a3xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7a3xx new file mode 100644 index 00000000000..ab1ff87833b --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7a3xx @@ -0,0 +1,11 @@ +# ST STM32H7A3X MCU configuration options + +# Copyright (c) 2021 Electrolance Solutions +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H7A3XX || SOC_STM32H7A3XXQ + +config NUM_IRQS + default 155 + +endif # SOC_STM32H7A3XX || SOC_STM32H7A3XXQ diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b0xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b0xx new file mode 100644 index 00000000000..0cb129871b6 --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b0xx @@ -0,0 +1,11 @@ +# ST STM32H7B0XX MCU configuration options + +# Copyright (c) 2023 Charles Dias +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H7B0XX || SOC_STM32H7B0XXQ + +config NUM_IRQS + default 155 + +endif # SOC_STM32H7B0XX || SOC_STM32H7B0XXQ diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b3xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b3xx new file mode 100644 index 00000000000..92de5028545 --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b3xx @@ -0,0 +1,11 @@ +# ST STM32H7B3X MCU configuration options + +# Copyright (c) 2022 Byte-Lab d.o.o +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H7B3XX || SOC_STM32H7B3XXQ + +config NUM_IRQS + default 155 + +endif # SOC_STM32H7B3XX || SOC_STM32H7B3XXQ diff --git a/soc/st/stm32/stm32h7x/Kconfig.soc b/soc/st/stm32/stm32h7x/Kconfig.soc new file mode 100644 index 00000000000..18841c0262c --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.soc @@ -0,0 +1,103 @@ +# ST Microelectronics STM32H7 MCU line + +# Copyright (c) 2019 Linaro Limited +# Copyright (c) 2020 Teslabs Engineering S.L. +# Copyright (c) 2021 Electrolance Solutions +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32H7X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32h7x" if SOC_SERIES_STM32H7X + +config SOC_STM32H723XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H725XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H730XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H730XXQ + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H735XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H743XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H745XX_M7 + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H745XX_M4 + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H747XX_M7 + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H747XX_M4 + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H750XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H753XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7A3XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7A3XXQ + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7B0XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7B0XXQ + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7B3XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7B3XXQ + bool + select SOC_SERIES_STM32H7X + +config SOC + default "stm32h7a3xx" if SOC_STM32H7A3XX + default "stm32h7a3xxq" if SOC_STM32H7A3XXQ + default "stm32h7b0xx" if SOC_STM32H7B0XX + default "stm32h7b0xxq" if SOC_STM32H7B0XXQ + default "stm32h7b3xx" if SOC_STM32H7B3XX + default "stm32h7b3xxq"if SOC_STM32H7B3XXQ + default "stm32h723xx" if SOC_STM32H723XX + default "stm32h725xx" if SOC_STM32H725XX + default "stm32h730xx" if SOC_STM32H730XX + default "stm32h730xxq" if SOC_STM32H730XXQ + default "stm32h735xx" if SOC_STM32H735XX + default "stm32h743xx" if SOC_STM32H743XX + default "stm32h745xx" if SOC_STM32H745XX_M7 || SOC_STM32H745XX_M4 + default "stm32h747xx" if SOC_STM32H747XX_M7 || SOC_STM32H747XX_M4 + default "stm32h750xx" if SOC_STM32H750XX + default "stm32h753xx" if SOC_STM32H753XX diff --git a/soc/arm/st_stm32/stm32h7/mpu_regions.c b/soc/st/stm32/stm32h7x/mpu_regions.c similarity index 100% rename from soc/arm/st_stm32/stm32h7/mpu_regions.c rename to soc/st/stm32/stm32h7x/mpu_regions.c diff --git a/soc/arm/st_stm32/stm32h7/sections.ld b/soc/st/stm32/stm32h7x/sections.ld similarity index 100% rename from soc/arm/st_stm32/stm32h7/sections.ld rename to soc/st/stm32/stm32h7x/sections.ld diff --git a/soc/arm/st_stm32/stm32h7/soc.h b/soc/st/stm32/stm32h7x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32h7/soc.h rename to soc/st/stm32/stm32h7x/soc.h diff --git a/soc/arm/st_stm32/stm32h7/soc_m4.c b/soc/st/stm32/stm32h7x/soc_m4.c similarity index 100% rename from soc/arm/st_stm32/stm32h7/soc_m4.c rename to soc/st/stm32/stm32h7x/soc_m4.c diff --git a/soc/arm/st_stm32/stm32h7/soc_m7.c b/soc/st/stm32/stm32h7x/soc_m7.c similarity index 100% rename from soc/arm/st_stm32/stm32h7/soc_m7.c rename to soc/st/stm32/stm32h7x/soc_m7.c diff --git a/soc/st/stm32/stm32l0x/CMakeLists.txt b/soc/st/stm32/stm32l0x/CMakeLists.txt new file mode 100644 index 00000000000..bc9a65c0049 --- /dev/null +++ b/soc/st/stm32/stm32l0x/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32l0x/Kconfig b/soc/st/stm32/stm32l0x/Kconfig new file mode 100644 index 00000000000..80479edffec --- /dev/null +++ b/soc/st/stm32/stm32l0x/Kconfig @@ -0,0 +1,30 @@ +# ST Microelectronics STM32L0 MCU series + +# Copyright (c) 2018 Endre Karlson +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L0X + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_VTOR + select HAS_STM32CUBE + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_PM + +config SOC_STM32L051XX + select CPU_HAS_ARM_MPU + +config SOC_STM32L053XX + select CPU_HAS_ARM_MPU + +config SOC_STM32L071XX + select CPU_HAS_ARM_MPU + +config SOC_STM32L072XX + select CPU_HAS_ARM_MPU + +config SOC_STM32L073XX + select CPU_HAS_ARM_MPU + +config SOC_STM32L081XX + select CPU_HAS_ARM_MPU diff --git a/soc/st/stm32/stm32l0x/Kconfig.defconfig b/soc/st/stm32/stm32l0x/Kconfig.defconfig new file mode 100644 index 00000000000..098889979b5 --- /dev/null +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig @@ -0,0 +1,17 @@ +# ST Microelectronics STM32L0 MCU line + +# Copyright (c) 2018 Endre Karlson +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32L0 series + +if SOC_SERIES_STM32L0X + +rsource "Kconfig.defconfig.stm32l0*" + +# adjust the fallback because of the LSI oscillator characteristics +config TASK_WDT_HW_FALLBACK_DELAY + depends on TASK_WDT_HW_FALLBACK + default 200 + +endif # SOC_SERIES_STM32L0X diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x4 b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x4 similarity index 84% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x4 rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x4 index 779d2624508..f47057ce5d4 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x4 +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x4 @@ -5,9 +5,6 @@ if SOC_STM32L010X4 -config SOC - default "stm32l010x4" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x6 b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x6 similarity index 84% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x6 rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x6 index dd86c005ad8..555ac98a02c 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x6 +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x6 @@ -5,9 +5,6 @@ if SOC_STM32L010X6 -config SOC - default "stm32l010x6" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x8 b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x8 similarity index 84% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x8 rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x8 index 20dd0b0c09a..39dbb520c70 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x8 +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x8 @@ -5,9 +5,6 @@ if SOC_STM32L010X8 -config SOC - default "stm32l010x8" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010xb b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010xb similarity index 86% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010xb rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010xb index 89e20292fc1..a3aa500c32f 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010xb +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010xb @@ -5,9 +5,6 @@ if SOC_STM32L010XB -config SOC - default "stm32l010xb" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l011xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l011xx similarity index 84% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l011xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l011xx index fe4c3045d63..2d31620a420 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l011xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l011xx @@ -5,9 +5,6 @@ if SOC_STM32L011XX -config SOC - default "stm32l011xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l031xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l031xx similarity index 85% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l031xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l031xx index 554fe3ed1ac..098e7f2fd77 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l031xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l031xx @@ -5,9 +5,6 @@ if SOC_STM32L031XX -config SOC - default "stm32l031xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l051xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l051xx similarity index 83% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l051xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l051xx index 3b5ff4ffd64..23f96935824 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l051xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l051xx @@ -5,9 +5,6 @@ if SOC_STM32L051XX -config SOC - default "stm32l051xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l053xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l053xx similarity index 85% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l053xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l053xx index 2d2e37e38c8..3ea376859cf 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l053xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l053xx @@ -5,9 +5,6 @@ if SOC_STM32L053XX -config SOC - default "stm32l053xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l071xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l071xx similarity index 85% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l071xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l071xx index dcc6b685281..41a40c94662 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l071xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l071xx @@ -5,9 +5,6 @@ if SOC_STM32L071XX -config SOC - default "stm32l071xx" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l072xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l072xx similarity index 85% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l072xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l072xx index a03a7696e27..33089c6253b 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l072xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l072xx @@ -5,9 +5,6 @@ if SOC_STM32L072XX -config SOC - default "stm32l072xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l073xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l073xx similarity index 85% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l073xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l073xx index d0a7acfd8e5..4cf34179d1b 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l073xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l073xx @@ -5,9 +5,6 @@ if SOC_STM32L073XX -config SOC - default "stm32l073xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l081xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l081xx similarity index 86% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l081xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l081xx index f3cc93c38c8..87f248e400d 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l081xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l081xx @@ -5,9 +5,6 @@ if SOC_STM32L081XX -config SOC - default "stm32l081xx" - config NUM_IRQS default 32 diff --git a/soc/st/stm32/stm32l0x/Kconfig.soc b/soc/st/stm32/stm32l0x/Kconfig.soc new file mode 100644 index 00000000000..c3ef0032e2e --- /dev/null +++ b/soc/st/stm32/stm32l0x/Kconfig.soc @@ -0,0 +1,76 @@ +# ST Microelectronics STM32L0 MCU line + +# Copyright (c) 2018 Endre Karlson +# Copyright (c) 2021 Nomono AS +# Copyright (c) 2023 OS Systems +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L0X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32l0x" if SOC_SERIES_STM32L0X + +config SOC_STM32L010X4 + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L010X6 + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L010X8 + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L010XB + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L011XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L031XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L051XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L053XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L071XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L072XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L073XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L081XX + bool + select SOC_SERIES_STM32L0X + +config SOC + default "stm32l010x4" if SOC_STM32L010X4 + default "stm32l010x6" if SOC_STM32L010X6 + default "stm32l010x8" if SOC_STM32L010X8 + default "stm32l010xb" if SOC_STM32L010XB + default "stm32l011xx" if SOC_STM32L011XX + default "stm32l031xx" if SOC_STM32L031XX + default "stm32l051xx" if SOC_STM32L051XX + default "stm32l053xx" if SOC_STM32L053XX + default "stm32l071xx" if SOC_STM32L071XX + default "stm32l072xx" if SOC_STM32L072XX + default "stm32l073xx" if SOC_STM32L073XX + default "stm32l081xx" if SOC_STM32L081XX diff --git a/soc/arm/st_stm32/stm32l0/power.c b/soc/st/stm32/stm32l0x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32l0/power.c rename to soc/st/stm32/stm32l0x/power.c diff --git a/soc/arm/st_stm32/stm32l0/soc.c b/soc/st/stm32/stm32l0x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32l0/soc.c rename to soc/st/stm32/stm32l0x/soc.c diff --git a/soc/arm/st_stm32/stm32l0/soc.h b/soc/st/stm32/stm32l0x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32l0/soc.h rename to soc/st/stm32/stm32l0x/soc.h diff --git a/soc/st/stm32/stm32l1x/CMakeLists.txt b/soc/st/stm32/stm32l1x/CMakeLists.txt new file mode 100644 index 00000000000..3e033529043 --- /dev/null +++ b/soc/st/stm32/stm32l1x/CMakeLists.txt @@ -0,0 +1,8 @@ +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32l1x/Kconfig b/soc/st/stm32/stm32l1x/Kconfig new file mode 100644 index 00000000000..db21b1d0bde --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32L1 MCU series + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L1X + select ARM + select CPU_CORTEX_M3 + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_SWO + select CPU_HAS_ARM_MPU diff --git a/soc/st/stm32/stm32l1x/Kconfig.defconfig b/soc/st/stm32/stm32l1x/Kconfig.defconfig new file mode 100644 index 00000000000..e04f33b22dd --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STMicroelectronics STM32L1 MCU line + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32L1X + +rsource "Kconfig.defconfig.stm32l1*" + +# adjust the fallback because of the LSI oscaillator characteristics +config TASK_WDT_HW_FALLBACK_DELAY + depends on TASK_WDT_HW_FALLBACK + default 200 + +endif # SOC_SERIES_STM32L1X diff --git a/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xb b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xb new file mode 100644 index 00000000000..dc9c04cda24 --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xb @@ -0,0 +1,11 @@ +# STMicroelectronics STM32L151XB MCU + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32L151XB + +config NUM_IRQS + default 45 + +endif # SOC_STM32L151XB diff --git a/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xba b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xba new file mode 100644 index 00000000000..f28ad427628 --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xba @@ -0,0 +1,11 @@ +# STMicroelectronics STM32L151XB-A MCU + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32L151XBA + +config NUM_IRQS + default 45 + +endif # SOC_STM32L151XBA diff --git a/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xc b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xc new file mode 100644 index 00000000000..ba82596f38f --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xc @@ -0,0 +1,12 @@ +# STMicroelectronics STM32L151XC MCU + +# Copyright (c) 2020 Abel Sensors +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32L151XC + +# Based on stm32cube number of interrupts+1, not datasheet +config NUM_IRQS + default 57 + +endif # SOC_STM32L151XC diff --git a/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xc b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xc new file mode 100644 index 00000000000..661ce869a45 --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xc @@ -0,0 +1,12 @@ +# STMicroelectronics STM32L152XC MCU + +# Copyright (c) 2020 Abel Sensors +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32L152XC + +config NUM_IRQS + int + default 57 + +endif # SOC_STM32L152XC diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xe b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xe similarity index 83% rename from soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xe rename to soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xe index 9a979aa8094..604cad7aaf5 100644 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xe +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xe @@ -5,10 +5,6 @@ if SOC_STM32L152XE -config SOC - string - default "stm32l152xe" - config NUM_IRQS int default 57 diff --git a/soc/st/stm32/stm32l1x/Kconfig.soc b/soc/st/stm32/stm32l1x/Kconfig.soc new file mode 100644 index 00000000000..b0165c76991 --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.soc @@ -0,0 +1,38 @@ +# STMicroelectronics STM32L1 MCU line + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L1X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32l1x" if SOC_SERIES_STM32L1X + +config SOC_STM32L151XB + bool + select SOC_SERIES_STM32L1X + +config SOC_STM32L151XBA + bool + select SOC_SERIES_STM32L1X + +config SOC_STM32L151XC + bool + select SOC_SERIES_STM32L1X + +config SOC_STM32L152XC + bool + select SOC_SERIES_STM32L1X + +config SOC_STM32L152XE + bool + select SOC_SERIES_STM32L1X + +config SOC + default "stm32l151xb" if SOC_STM32L151XB + default "stm32l151xba" if SOC_STM32L151XBA + default "stm32l151xc" if SOC_STM32L151XC + default "stm32l152xc" if SOC_STM32L152XC + default "stm32l152xe" if SOC_STM32L152XE diff --git a/soc/arm/st_stm32/stm32l1/soc.c b/soc/st/stm32/stm32l1x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32l1/soc.c rename to soc/st/stm32/stm32l1x/soc.c diff --git a/soc/arm/st_stm32/stm32l1/soc.h b/soc/st/stm32/stm32l1x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32l1/soc.h rename to soc/st/stm32/stm32l1x/soc.h diff --git a/soc/st/stm32/stm32l4x/CMakeLists.txt b/soc/st/stm32/stm32l4x/CMakeLists.txt new file mode 100644 index 00000000000..2a910ba7512 --- /dev/null +++ b/soc/st/stm32/stm32l4x/CMakeLists.txt @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32l4x/Kconfig b/soc/st/stm32/stm32l4x/Kconfig new file mode 100644 index 00000000000..80bc62075c3 --- /dev/null +++ b/soc/st/stm32/stm32l4x/Kconfig @@ -0,0 +1,16 @@ +# ST Microelectronics STM32L4 MCU series + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L4X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select HAS_SWO + select HAS_PM + select HAS_POWEROFF diff --git a/soc/st/stm32/stm32l4x/Kconfig.defconfig b/soc/st/stm32/stm32l4x/Kconfig.defconfig new file mode 100644 index 00000000000..3e4402b556e --- /dev/null +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig @@ -0,0 +1,13 @@ +# ST Microelectronics STM32L4 MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32L4 series + +if SOC_SERIES_STM32L4X + +rsource "Kconfig.defconfig.stm32l4*" + +endif # SOC_SERIES_STM32L4X diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l412xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l412xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l412xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l412xx index 2918e3d3dd2..eb73f26dc4d 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l412xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l412xx @@ -5,9 +5,6 @@ if SOC_STM32L412XX -config SOC - default "stm32l412xx" - config NUM_IRQS default 83 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l422xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l422xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l422xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l422xx index f6be07396ba..24143f8ede9 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l422xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l422xx @@ -5,9 +5,6 @@ if SOC_STM32L422XX -config SOC - default "stm32l422xx" - config NUM_IRQS default 83 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l431xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l431xx similarity index 83% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l431xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l431xx index d21a2bd58f9..65b11365368 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l431xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l431xx @@ -5,9 +5,6 @@ if SOC_STM32L431XX -config SOC - default "stm32l431xx" - config NUM_IRQS default 83 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l432xx similarity index 86% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l432xx index d6ed27b7b44..b16bdfd5090 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l432xx @@ -6,9 +6,6 @@ if SOC_STM32L432XX -config SOC - default "stm32l432xx" - config NUM_IRQS default 83 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l433xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l433xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l433xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l433xx index d10133eb1a8..2cb0b3162a0 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l433xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l433xx @@ -5,9 +5,6 @@ if SOC_STM32L433XX -config SOC - default "stm32l433xx" - config NUM_IRQS default 83 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l451xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l451xx similarity index 85% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l451xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l451xx index d3f5867a8dc..36350d41b5e 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l451xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l451xx @@ -5,9 +5,6 @@ if SOC_STM32L451XX -config SOC - default "stm32l451xx" - config NUM_IRQS default 85 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l452xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l452xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l452xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l452xx index 0c6cc32f1f8..c1564d0513d 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l452xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l452xx @@ -5,9 +5,6 @@ if SOC_STM32L452XX -config SOC - default "stm32l452xx" - config NUM_IRQS default 85 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l462xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l462xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l462xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l462xx index 1c3575884b2..57d136e67c5 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l462xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l462xx @@ -5,9 +5,6 @@ if SOC_STM32L462XX -config SOC - default "stm32l462xx" - config NUM_IRQS default 85 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l471xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l471xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l471xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l471xx index afb35990bee..22e8dd61d44 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l471xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l471xx @@ -5,9 +5,6 @@ if SOC_STM32L471XX -config SOC - default "stm32l471xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l475xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l475xx index 25e11c3bcec..0e3e1d231e6 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l475xx @@ -5,9 +5,6 @@ if SOC_STM32L475XX -config SOC - default "stm32l475xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l476xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l476xx similarity index 86% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l476xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l476xx index d2f70cd6c66..bd53c4066cc 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l476xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l476xx @@ -6,9 +6,6 @@ if SOC_STM32L476XX -config SOC - default "stm32l476xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l486xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l486xx similarity index 88% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l486xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l486xx index 600948c5ffa..4e5cbd8b581 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l486xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l486xx @@ -7,9 +7,6 @@ if SOC_STM32L486XX -config SOC - default "stm32l486xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l496xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l496xx similarity index 88% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l496xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l496xx index 6d5dcb62bad..d7100e5c9ca 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l496xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l496xx @@ -7,9 +7,6 @@ if SOC_STM32L496XX -config SOC - default "stm32l496xx" - config NUM_IRQS default 91 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4a6xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4a6xx similarity index 89% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4a6xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4a6xx index 12a88ee608f..7cfcecfe204 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4a6xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4a6xx @@ -8,9 +8,6 @@ if SOC_STM32L4A6XX -config SOC - default "stm32l4a6xx" - config NUM_IRQS default 91 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4p5xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4p5xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4p5xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4p5xx index 605264f36a0..2c55c2d0113 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4p5xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4p5xx @@ -5,9 +5,6 @@ if SOC_STM32L4P5XX -config SOC - default "stm32l4p5xx" - config NUM_IRQS default 95 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4q5xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4q5xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4q5xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4q5xx index 964cd4ad9ad..779d194eb4c 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4q5xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4q5xx @@ -5,9 +5,6 @@ if SOC_STM32L4Q5XX -config SOC - default "stm32l4q5xx" - config NUM_IRQS default 95 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r5xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r5xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r5xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r5xx index 3a221310774..301004d3a84 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r5xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r5xx @@ -5,9 +5,6 @@ if SOC_STM32L4R5XX -config SOC - default "stm32l4r5xx" - config NUM_IRQS default 95 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r9xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r9xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r9xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r9xx index fd39575c550..150a22332b7 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r9xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r9xx @@ -5,9 +5,6 @@ if SOC_STM32L4R9XX -config SOC - default "stm32l4r9xx" - config NUM_IRQS default 95 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4s5xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4s5xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4s5xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4s5xx index 79d97dbe083..85ab309e848 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4s5xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4s5xx @@ -5,9 +5,6 @@ if SOC_STM32L4S5XX -config SOC - default "stm32l4s5xx" - config NUM_IRQS default 95 diff --git a/soc/st/stm32/stm32l4x/Kconfig.soc b/soc/st/stm32/stm32l4x/Kconfig.soc new file mode 100644 index 00000000000..e48579d93b7 --- /dev/null +++ b/soc/st/stm32/stm32l4x/Kconfig.soc @@ -0,0 +1,111 @@ +# ST Microelectronics STM32L4 MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# Copyright (c) 2019 Centaur Analytics, Inc +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L4X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32l4x" if SOC_SERIES_STM32L4X + +config SOC_STM32L412XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L422XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L431XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L432XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L433XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L451XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L452XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L462XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L471XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L475XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L476XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L486XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L496XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4A6XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4P5XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4Q5XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4S5XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4R5XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4R9XX + bool + select SOC_SERIES_STM32L4X + +config SOC + default "stm32l412xx" if SOC_STM32L412XX + default "stm32l422xx" if SOC_STM32L422XX + default "stm32l431xx" if SOC_STM32L431XX + default "stm32l432xx" if SOC_STM32L432XX + default "stm32l433xx" if SOC_STM32L433XX + default "stm32l451xx" if SOC_STM32L451XX + default "stm32l452xx" if SOC_STM32L452XX + default "stm32l462xx" if SOC_STM32L462XX + default "stm32l471xx" if SOC_STM32L471XX + default "stm32l475xx" if SOC_STM32L475XX + default "stm32l476xx" if SOC_STM32L476XX + default "stm32l486xx" if SOC_STM32L486XX + default "stm32l496xx" if SOC_STM32L496XX + default "stm32l4a6xx" if SOC_STM32L4A6XX + default "stm32l4p5xx" if SOC_STM32L4P5XX + default "stm32l4q5xx" if SOC_STM32L4Q5XX + default "stm32l4s5xx" if SOC_STM32L4S5XX + default "stm32l4r5xx" if SOC_STM32L4R5XX + default "stm32l4r9xx" if SOC_STM32L4R9XX diff --git a/soc/arm/st_stm32/stm32l4/power.c b/soc/st/stm32/stm32l4x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32l4/power.c rename to soc/st/stm32/stm32l4x/power.c diff --git a/soc/arm/st_stm32/stm32l4/poweroff.c b/soc/st/stm32/stm32l4x/poweroff.c similarity index 100% rename from soc/arm/st_stm32/stm32l4/poweroff.c rename to soc/st/stm32/stm32l4x/poweroff.c diff --git a/soc/arm/st_stm32/stm32l4/soc.c b/soc/st/stm32/stm32l4x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32l4/soc.c rename to soc/st/stm32/stm32l4x/soc.c diff --git a/soc/arm/st_stm32/stm32l4/soc.h b/soc/st/stm32/stm32l4x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32l4/soc.h rename to soc/st/stm32/stm32l4x/soc.h diff --git a/soc/st/stm32/stm32l5x/CMakeLists.txt b/soc/st/stm32/stm32l5x/CMakeLists.txt new file mode 100644 index 00000000000..bc9a65c0049 --- /dev/null +++ b/soc/st/stm32/stm32l5x/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32l5x/Kconfig b/soc/st/stm32/stm32l5x/Kconfig new file mode 100644 index 00000000000..ac7de0dfd7d --- /dev/null +++ b/soc/st/stm32/stm32l5x/Kconfig @@ -0,0 +1,16 @@ +# ST Microelectronics STM32L5 MCU series + +# Copyright (c) 2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L5X + select ARM + select CPU_CORTEX_M33 + select ARM_TRUSTZONE_M + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_PM diff --git a/soc/st/stm32/stm32l5x/Kconfig.defconfig b/soc/st/stm32/stm32l5x/Kconfig.defconfig new file mode 100644 index 00000000000..2c8607c9b79 --- /dev/null +++ b/soc/st/stm32/stm32l5x/Kconfig.defconfig @@ -0,0 +1,13 @@ +# ST Microelectronics STM32L5 MCU line + +# Copyright (c) 2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32L5X + +rsource "Kconfig.defconfig.stm32l5*" + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_STM32L5X diff --git a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l552xx b/soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l552xx similarity index 84% rename from soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l552xx rename to soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l552xx index 7692fbd7451..29d2e2d8147 100644 --- a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l552xx +++ b/soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l552xx @@ -5,9 +5,6 @@ if SOC_STM32L552XX -config SOC - default "stm32l552xx" - config NUM_IRQS default 108 diff --git a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l562xx b/soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l562xx similarity index 84% rename from soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l562xx rename to soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l562xx index 484880dc910..5b1490c11c9 100644 --- a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l562xx +++ b/soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l562xx @@ -5,9 +5,6 @@ if SOC_STM32L562XX -config SOC - default "stm32l562xx" - config NUM_IRQS default 109 diff --git a/soc/st/stm32/stm32l5x/Kconfig.soc b/soc/st/stm32/stm32l5x/Kconfig.soc new file mode 100644 index 00000000000..a2752f86bc1 --- /dev/null +++ b/soc/st/stm32/stm32l5x/Kconfig.soc @@ -0,0 +1,23 @@ +# ST Microelectronics STM32L5 MCU line + +# Copyright (c) 2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L5X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32l5x" if SOC_SERIES_STM32L5X + +config SOC_STM32L552XX + bool + select SOC_SERIES_STM32L5X + +config SOC_STM32L562XX + bool + select SOC_SERIES_STM32L5X + +config SOC + default "stm32l552xx" if SOC_STM32L552XX + default "stm32l562xx" if SOC_STM32L562XX diff --git a/soc/arm/st_stm32/stm32l5/power.c b/soc/st/stm32/stm32l5x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32l5/power.c rename to soc/st/stm32/stm32l5x/power.c diff --git a/soc/arm/st_stm32/stm32l5/soc.c b/soc/st/stm32/stm32l5x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32l5/soc.c rename to soc/st/stm32/stm32l5x/soc.c diff --git a/soc/arm/st_stm32/stm32l5/soc.h b/soc/st/stm32/stm32l5x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32l5/soc.h rename to soc/st/stm32/stm32l5x/soc.h diff --git a/soc/st/stm32/stm32mp1x/CMakeLists.txt b/soc/st/stm32/stm32mp1x/CMakeLists.txt new file mode 100644 index 00000000000..65004cceca8 --- /dev/null +++ b/soc/st/stm32/stm32mp1x/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2019 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32mp1x/Kconfig b/soc/st/stm32/stm32mp1x/Kconfig new file mode 100644 index 00000000000..76e50a92e4a --- /dev/null +++ b/soc/st/stm32/stm32mp1x/Kconfig @@ -0,0 +1,13 @@ +# STMicroelectronics STM32MP1 MPU series + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32MP1X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select OPENAMP_RSC_TABLE if RAM_CONSOLE diff --git a/soc/st/stm32/stm32mp1x/Kconfig.defconfig b/soc/st/stm32/stm32mp1x/Kconfig.defconfig new file mode 100644 index 00000000000..3a27f9118d9 --- /dev/null +++ b/soc/st/stm32/stm32mp1x/Kconfig.defconfig @@ -0,0 +1,10 @@ +# STMicroelectronics STM32MP1 MCU/MPU line + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32MP1X + +rsource "Kconfig.defconfig.stm32mp15_m4" + +endif # SOC_SERIES_STM32MP1X diff --git a/soc/st/stm32/stm32mp1x/Kconfig.defconfig.stm32mp15_m4 b/soc/st/stm32/stm32mp1x/Kconfig.defconfig.stm32mp15_m4 new file mode 100644 index 00000000000..08a4e1bf0ac --- /dev/null +++ b/soc/st/stm32/stm32mp1x/Kconfig.defconfig.stm32mp15_m4 @@ -0,0 +1,11 @@ +# STMicroelectronics STM32MP157C_M4 MCU + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32MP15_M4 + +config NUM_IRQS + default 150 + +endif # SOC_STM32MP15_M4 diff --git a/soc/st/stm32/stm32mp1x/Kconfig.soc b/soc/st/stm32/stm32mp1x/Kconfig.soc new file mode 100644 index 00000000000..b67930b89dc --- /dev/null +++ b/soc/st/stm32/stm32mp1x/Kconfig.soc @@ -0,0 +1,18 @@ +# STMicroelectronics STM32MP1 MPU line + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32MP1X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32mp1x" if SOC_SERIES_STM32MP1X + +config SOC_STM32MP15_M4 + bool + select SOC_SERIES_STM32MP1X + +config SOC + default "stm32mp157cxx" if SOC_STM32MP15_M4 diff --git a/soc/arm/st_stm32/stm32mp1/linker.ld b/soc/st/stm32/stm32mp1x/linker.ld similarity index 100% rename from soc/arm/st_stm32/stm32mp1/linker.ld rename to soc/st/stm32/stm32mp1x/linker.ld diff --git a/soc/arm/st_stm32/stm32mp1/soc.c b/soc/st/stm32/stm32mp1x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32mp1/soc.c rename to soc/st/stm32/stm32mp1x/soc.c diff --git a/soc/arm/st_stm32/stm32mp1/soc.h b/soc/st/stm32/stm32mp1x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32mp1/soc.h rename to soc/st/stm32/stm32mp1x/soc.h diff --git a/soc/st/stm32/stm32u5x/CMakeLists.txt b/soc/st/stm32/stm32u5x/CMakeLists.txt new file mode 100644 index 00000000000..f737c62ce24 --- /dev/null +++ b/soc/st/stm32/stm32u5x/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM power.c) +zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32u5x/Kconfig b/soc/st/stm32/stm32u5x/Kconfig new file mode 100644 index 00000000000..a2e4145abc3 --- /dev/null +++ b/soc/st/stm32/stm32u5x/Kconfig @@ -0,0 +1,17 @@ +# ST Microelectronics STM32U5 MCU series + +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32U5X + select ARM + select CPU_CORTEX_M33 + select ARM_TRUSTZONE_M + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_PM + select HAS_POWEROFF diff --git a/soc/st/stm32/stm32u5x/Kconfig.defconfig b/soc/st/stm32/stm32u5x/Kconfig.defconfig new file mode 100644 index 00000000000..354cc6cd0ab --- /dev/null +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig @@ -0,0 +1,13 @@ +# ST Microelectronics STM32U5 MCU line + +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32U5X + +rsource "Kconfig.defconfig.stm32u5*" + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_STM32U5X diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u575xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u575xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u575xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u575xx index 47c61114b7a..7c2ed2282c2 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u575xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u575xx @@ -5,9 +5,6 @@ if SOC_STM32U575XX -config SOC - default "stm32u575xx" - config NUM_IRQS default 125 diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u585xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u585xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u585xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u585xx index d1ac8788b7a..117dc3fe481 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u585xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u585xx @@ -5,9 +5,6 @@ if SOC_STM32U585XX -config SOC - default "stm32u585xx" - config NUM_IRQS default 125 diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u595xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u595xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u595xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u595xx index d0bd4f99450..05f932ea7b7 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u595xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u595xx @@ -5,9 +5,6 @@ if SOC_STM32U595XX -config SOC - default "stm32u595xx" - config NUM_IRQS default 132 diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u599xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u599xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u599xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u599xx index df30e49fd02..01aa1f4663a 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u599xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u599xx @@ -5,9 +5,6 @@ if SOC_STM32U599XX -config SOC - default "stm32u599xx" - config NUM_IRQS default 139 diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a5xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a5xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a5xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a5xx index 1759406a580..f8812b1fa40 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a5xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a5xx @@ -5,9 +5,6 @@ if SOC_STM32U5A5XX -config SOC - default "stm32u5a5xx" - config NUM_IRQS default 139 diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a9xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a9xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a9xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a9xx index 0553382acb1..5e77b7b8c04 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a9xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a9xx @@ -5,9 +5,6 @@ if SOC_STM32U5A9XX -config SOC - default "stm32u5a9xx" - config NUM_IRQS default 139 diff --git a/soc/st/stm32/stm32u5x/Kconfig.soc b/soc/st/stm32/stm32u5x/Kconfig.soc new file mode 100644 index 00000000000..59324d56193 --- /dev/null +++ b/soc/st/stm32/stm32u5x/Kconfig.soc @@ -0,0 +1,45 @@ +# ST Microelectronics STM32U5 MCU line + +# Copyright (c) 2021 Linaro Limited +# Copyright (c) 2023 PSICONTROL nv +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32U5X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32u5x" if SOC_SERIES_STM32U5X + +config SOC_STM32U575XX + bool + select SOC_SERIES_STM32U5X + +config SOC_STM32U585XX + bool + select SOC_SERIES_STM32U5X + +config SOC_STM32U595XX + bool + select SOC_SERIES_STM32U5X + +config SOC_STM32U599XX + bool + select SOC_SERIES_STM32U5X + +config SOC_STM32U5A5XX + bool + select SOC_SERIES_STM32U5X + +config SOC_STM32U5A9XX + bool + select SOC_SERIES_STM32U5X + +config SOC + default "stm32u5a5xx" if SOC_STM32U5A5XX + default "stm32u5a9xx" if SOC_STM32U5A9XX + default "stm32u575xx" if SOC_STM32U575XX + default "stm32u585xx" if SOC_STM32U585XX + default "stm32u595xx" if SOC_STM32U595XX + default "stm32u599xx" if SOC_STM32U599XX diff --git a/soc/arm/st_stm32/stm32u5/power.c b/soc/st/stm32/stm32u5x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32u5/power.c rename to soc/st/stm32/stm32u5x/power.c diff --git a/soc/arm/st_stm32/stm32u5/poweroff.c b/soc/st/stm32/stm32u5x/poweroff.c similarity index 100% rename from soc/arm/st_stm32/stm32u5/poweroff.c rename to soc/st/stm32/stm32u5x/poweroff.c diff --git a/soc/arm/st_stm32/stm32u5/soc.c b/soc/st/stm32/stm32u5x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32u5/soc.c rename to soc/st/stm32/stm32u5x/soc.c diff --git a/soc/arm/st_stm32/stm32u5/soc.h b/soc/st/stm32/stm32u5x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32u5/soc.h rename to soc/st/stm32/stm32u5x/soc.h diff --git a/soc/st/stm32/stm32wbax/CMakeLists.txt b/soc/st/stm32/stm32wbax/CMakeLists.txt new file mode 100644 index 00000000000..0c970756442 --- /dev/null +++ b/soc/st/stm32/stm32wbax/CMakeLists.txt @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +if(CONFIG_BT_STM32WBA) + zephyr_include_directories(hci_if) + + zephyr_sources(hci_if/linklayer_plat.c) + zephyr_sources(hci_if/bleplat.c) + zephyr_sources(hci_if/host_stack_if.c) + zephyr_sources(hci_if/ll_sys_if.c) + zephyr_sources(hci_if/stm32_timer.c) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32wbax/Kconfig b/soc/st/stm32/stm32wbax/Kconfig new file mode 100644 index 00000000000..2f737ebb4b9 --- /dev/null +++ b/soc/st/stm32/stm32wbax/Kconfig @@ -0,0 +1,17 @@ +# ST Microelectronics STM32WBA MCU series + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WBAX + select ARM + select CPU_CORTEX_M33 + select ARM_TRUSTZONE_M + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select USE_STM32_HAL_PWR_EX + select HAS_PM diff --git a/soc/st/stm32/stm32wbax/Kconfig.defconfig b/soc/st/stm32/stm32wbax/Kconfig.defconfig new file mode 100644 index 00000000000..8a7e2c0ab04 --- /dev/null +++ b/soc/st/stm32/stm32wbax/Kconfig.defconfig @@ -0,0 +1,61 @@ +# ST Microelectronics STM32WBA MCU line + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32WBAX + +rsource "Kconfig.defconfig.stm32wba*" + +config STM32_LPTIM_TIMER + default y if PM + +choice BT_HCI_BUS_TYPE + default BT_STM32WBA + depends on BT +endchoice + +config BT_STM32WBA + select DYNAMIC_INTERRUPTS + select DYNAMIC_DIRECT_INTERRUPTS + select ENTROPY_GENERATOR + select USE_STM32_HAL_RAMCFG + +if BT_STM32WBA + +choice LIBC_IMPLEMENTATION + default NEWLIB_LIBC +endchoice + +choice LINKER_ORPHAN_CONFIGURATION + default LINKER_ORPHAN_SECTION_PLACE +endchoice + +config ENTROPY_STM32_CLK_CHECK + default n + +endif + +if PM_S2RAM + +config COUNTER + default y + +config COUNTER_RTC_STM32_SUBSECONDS + default y + +config STM32_LPTIM_STDBY_TIMER + default y + +config TICKLESS_KERNEL + default y + +config COUNTER_RTC_STM32_SAVE_VALUE_BETWEEN_RESETS + default y + +config IDLE_STACK_SIZE + default 512 + +endif + +endif # SOC_SERIES_STM32WBAX diff --git a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba52xx b/soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba52xx similarity index 84% rename from soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba52xx rename to soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba52xx index b9d54cdfc72..d48a67710b8 100644 --- a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba52xx +++ b/soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba52xx @@ -5,9 +5,6 @@ if SOC_STM32WBA52XX -config SOC - default "stm32wba52xx" - config NUM_IRQS default 70 diff --git a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba55xx b/soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba55xx similarity index 84% rename from soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba55xx rename to soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba55xx index ca745f87471..ce80f32291b 100644 --- a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba55xx +++ b/soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba55xx @@ -5,9 +5,6 @@ if SOC_STM32WBA55XX -config SOC - default "stm32wba55xx" - config NUM_IRQS default 70 diff --git a/soc/st/stm32/stm32wbax/Kconfig.soc b/soc/st/stm32/stm32wbax/Kconfig.soc new file mode 100644 index 00000000000..104a3923989 --- /dev/null +++ b/soc/st/stm32/stm32wbax/Kconfig.soc @@ -0,0 +1,23 @@ +# ST Microelectronics STM32WBA MCU line + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WBAX + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32wbax" if SOC_SERIES_STM32WBAX + +config SOC_STM32WBA52XX + bool + select SOC_SERIES_STM32WBAX + +config SOC_STM32WBA55XX + bool + select SOC_SERIES_STM32WBAX + +config SOC + default "stm32wba52xx" if SOC_STM32WBA52XX + default "stm32wba55xx" if SOC_STM32WBA55XX diff --git a/soc/arm/st_stm32/stm32wba/hci_if/bleplat.c b/soc/st/stm32/stm32wbax/hci_if/bleplat.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/bleplat.c rename to soc/st/stm32/stm32wbax/hci_if/bleplat.c diff --git a/soc/arm/st_stm32/stm32wba/hci_if/host_stack_if.c b/soc/st/stm32/stm32wbax/hci_if/host_stack_if.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/host_stack_if.c rename to soc/st/stm32/stm32wbax/hci_if/host_stack_if.c diff --git a/soc/arm/st_stm32/stm32wba/hci_if/linklayer_plat.c b/soc/st/stm32/stm32wbax/hci_if/linklayer_plat.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/linklayer_plat.c rename to soc/st/stm32/stm32wbax/hci_if/linklayer_plat.c diff --git a/soc/arm/st_stm32/stm32wba/hci_if/linklayer_plat_local.h b/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_local.h similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/linklayer_plat_local.h rename to soc/st/stm32/stm32wbax/hci_if/linklayer_plat_local.h diff --git a/soc/arm/st_stm32/stm32wba/hci_if/ll_sys_if.c b/soc/st/stm32/stm32wbax/hci_if/ll_sys_if.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/ll_sys_if.c rename to soc/st/stm32/stm32wbax/hci_if/ll_sys_if.c diff --git a/soc/arm/st_stm32/stm32wba/hci_if/stm32_timer.c b/soc/st/stm32/stm32wbax/hci_if/stm32_timer.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/stm32_timer.c rename to soc/st/stm32/stm32wbax/hci_if/stm32_timer.c diff --git a/soc/arm/st_stm32/stm32wba/power.c b/soc/st/stm32/stm32wbax/power.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/power.c rename to soc/st/stm32/stm32wbax/power.c diff --git a/soc/arm/st_stm32/stm32wba/soc.c b/soc/st/stm32/stm32wbax/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/soc.c rename to soc/st/stm32/stm32wbax/soc.c diff --git a/soc/arm/st_stm32/stm32wba/soc.h b/soc/st/stm32/stm32wbax/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32wba/soc.h rename to soc/st/stm32/stm32wbax/soc.h diff --git a/soc/st/stm32/stm32wbx/CMakeLists.txt b/soc/st/stm32/stm32wbx/CMakeLists.txt new file mode 100644 index 00000000000..6806b1fa772 --- /dev/null +++ b/soc/st/stm32/stm32wbx/CMakeLists.txt @@ -0,0 +1,19 @@ +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_linker_sources_ifdef(CONFIG_BT_STM32_IPM + SECTIONS + ipm.ld + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32wbx/Kconfig b/soc/st/stm32/stm32wbx/Kconfig new file mode 100644 index 00000000000..65aadce2808 --- /dev/null +++ b/soc/st/stm32/stm32wbx/Kconfig @@ -0,0 +1,15 @@ +# ST Microelectronics STM32WB MCU series + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WBX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select HAS_SWO + select HAS_PM + select HAS_POWEROFF diff --git a/soc/st/stm32/stm32wbx/Kconfig.defconfig b/soc/st/stm32/stm32wbx/Kconfig.defconfig new file mode 100644 index 00000000000..948e9cc0f2c --- /dev/null +++ b/soc/st/stm32/stm32wbx/Kconfig.defconfig @@ -0,0 +1,13 @@ +# ST Microelectronics STM32WB MCU line + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32WBX + +rsource "Kconfig.defconfig.stm32wb*" + +config BT_USER_PHY_UPDATE + default y if BT + +endif # SOC_SERIES_STM32WBX diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb55xx b/soc/st/stm32/stm32wbx/Kconfig.defconfig.stm32wb55xx similarity index 84% rename from soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb55xx rename to soc/st/stm32/stm32wbx/Kconfig.defconfig.stm32wb55xx index 175518e3ff1..c7659b460ff 100644 --- a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb55xx +++ b/soc/st/stm32/stm32wbx/Kconfig.defconfig.stm32wb55xx @@ -5,9 +5,6 @@ if SOC_STM32WB55XX -config SOC - default "stm32wb55xx" - config NUM_IRQS default 63 diff --git a/soc/st/stm32/stm32wbx/Kconfig.soc b/soc/st/stm32/stm32wbx/Kconfig.soc new file mode 100644 index 00000000000..0ba89943c8d --- /dev/null +++ b/soc/st/stm32/stm32wbx/Kconfig.soc @@ -0,0 +1,18 @@ +# ST Microelectronics STM32WB MCU line + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WBX + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32wbx" if SOC_SERIES_STM32WBX + +config SOC_STM32WB55XX + bool + select SOC_SERIES_STM32WBX + +config SOC + default "stm32wb55xx" if SOC_STM32WB55XX diff --git a/soc/arm/st_stm32/stm32wb/ipm.ld b/soc/st/stm32/stm32wbx/ipm.ld similarity index 100% rename from soc/arm/st_stm32/stm32wb/ipm.ld rename to soc/st/stm32/stm32wbx/ipm.ld diff --git a/soc/arm/st_stm32/stm32wb/power.c b/soc/st/stm32/stm32wbx/power.c similarity index 100% rename from soc/arm/st_stm32/stm32wb/power.c rename to soc/st/stm32/stm32wbx/power.c diff --git a/soc/arm/st_stm32/stm32wb/poweroff.c b/soc/st/stm32/stm32wbx/poweroff.c similarity index 100% rename from soc/arm/st_stm32/stm32wb/poweroff.c rename to soc/st/stm32/stm32wbx/poweroff.c diff --git a/soc/arm/st_stm32/stm32wb/soc.c b/soc/st/stm32/stm32wbx/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32wb/soc.c rename to soc/st/stm32/stm32wbx/soc.c diff --git a/soc/arm/st_stm32/stm32wb/soc.h b/soc/st/stm32/stm32wbx/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32wb/soc.h rename to soc/st/stm32/stm32wbx/soc.h diff --git a/soc/st/stm32/stm32wlx/CMakeLists.txt b/soc/st/stm32/stm32wlx/CMakeLists.txt new file mode 100644 index 00000000000..54069f6b599 --- /dev/null +++ b/soc/st/stm32/stm32wlx/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources(soc.c) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32wlx/Kconfig b/soc/st/stm32/stm32wlx/Kconfig new file mode 100644 index 00000000000..a4983fdad0a --- /dev/null +++ b/soc/st/stm32/stm32wlx/Kconfig @@ -0,0 +1,14 @@ +# STMicroelectronics STM32WL MCU series + +# Copyright (c) 2020 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WLX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL + select HAS_PM + select HAS_POWEROFF diff --git a/soc/st/stm32/stm32wlx/Kconfig.defconfig b/soc/st/stm32/stm32wlx/Kconfig.defconfig new file mode 100644 index 00000000000..277a9046c73 --- /dev/null +++ b/soc/st/stm32/stm32wlx/Kconfig.defconfig @@ -0,0 +1,10 @@ +# STMicroelectronics STM32WL MCU line + +# Copyright (c) 2020 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32WLX + +rsource "Kconfig.defconfig.stm32wl*" + +endif # SOC_SERIES_STM32WLX diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl54xx b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl54xx similarity index 84% rename from soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl54xx rename to soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl54xx index d692e02e28c..876c15437b5 100644 --- a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl54xx +++ b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl54xx @@ -5,9 +5,6 @@ if SOC_STM32WL54XX -config SOC - default "stm32wl54xx" - config NUM_IRQS default 62 diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl55xx b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl55xx similarity index 84% rename from soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl55xx rename to soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl55xx index 1358c9d0487..247c174e020 100644 --- a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl55xx +++ b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl55xx @@ -5,9 +5,6 @@ if SOC_STM32WL55XX -config SOC - default "stm32wl55xx" - config NUM_IRQS default 62 diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle4xx b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle4xx similarity index 84% rename from soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle4xx rename to soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle4xx index cbdfe62f9a3..0ebb75b9155 100644 --- a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle4xx +++ b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle4xx @@ -5,9 +5,6 @@ if SOC_STM32WLE4XX -config SOC - default "stm32wle4xx" - config NUM_IRQS default 62 diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle5xx b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle5xx similarity index 84% rename from soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle5xx rename to soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle5xx index 14f16697216..97682fdc65c 100644 --- a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle5xx +++ b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle5xx @@ -5,9 +5,6 @@ if SOC_STM32WLE5XX -config SOC - default "stm32wle5xx" - config NUM_IRQS default 62 diff --git a/soc/st/stm32/stm32wlx/Kconfig.soc b/soc/st/stm32/stm32wlx/Kconfig.soc new file mode 100644 index 00000000000..4b130d029be --- /dev/null +++ b/soc/st/stm32/stm32wlx/Kconfig.soc @@ -0,0 +1,33 @@ +# STMicroelectronics STM32WL MCU line + +# Copyright (c) 2020 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WLX + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32wlx" if SOC_SERIES_STM32WLX + +config SOC_STM32WLE4XX + bool + select SOC_SERIES_STM32WLX + +config SOC_STM32WLE5XX + bool + select SOC_SERIES_STM32WLX + +config SOC_STM32WL54XX + bool + select SOC_SERIES_STM32WLX + +config SOC_STM32WL55XX + bool + select SOC_SERIES_STM32WLX + +config SOC + default "stm32wle4xx" if SOC_STM32WLE4XX + default "stm32wle5xx" if SOC_STM32WLE5XX + default "stm32wl54xx" if SOC_STM32WL54XX + default "stm32wl55xx" if SOC_STM32WL55XX diff --git a/soc/arm/st_stm32/stm32wl/power.c b/soc/st/stm32/stm32wlx/power.c similarity index 100% rename from soc/arm/st_stm32/stm32wl/power.c rename to soc/st/stm32/stm32wlx/power.c diff --git a/soc/arm/st_stm32/stm32wl/poweroff.c b/soc/st/stm32/stm32wlx/poweroff.c similarity index 100% rename from soc/arm/st_stm32/stm32wl/poweroff.c rename to soc/st/stm32/stm32wlx/poweroff.c diff --git a/soc/arm/st_stm32/stm32wl/soc.c b/soc/st/stm32/stm32wlx/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32wl/soc.c rename to soc/st/stm32/stm32wlx/soc.c diff --git a/soc/arm/st_stm32/stm32wl/soc.h b/soc/st/stm32/stm32wlx/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32wl/soc.h rename to soc/st/stm32/stm32wlx/soc.h diff --git a/soc/riscv/starfive_jh71xx/jh71xx/CMakeLists.txt b/soc/starfive/jh71xx/CMakeLists.txt similarity index 100% rename from soc/riscv/starfive_jh71xx/jh71xx/CMakeLists.txt rename to soc/starfive/jh71xx/CMakeLists.txt diff --git a/soc/starfive/jh71xx/Kconfig b/soc/starfive/jh71xx/Kconfig new file mode 100644 index 00000000000..91ef208f9c1 --- /dev/null +++ b/soc/starfive/jh71xx/Kconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2021 Rajnesh Kanwal +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STARFIVE_JH71XX + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + +config SOC_JH7100 + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/starfive/jh71xx/Kconfig.defconfig b/soc/starfive/jh71xx/Kconfig.defconfig new file mode 100644 index 00000000000..c20bde5ee58 --- /dev/null +++ b/soc/starfive/jh71xx/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2021 Rajnesh Kanwal +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STARFIVE_JH71XX + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 6250000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config NUM_IRQS + default 139 + +endif diff --git a/soc/starfive/jh71xx/Kconfig.soc b/soc/starfive/jh71xx/Kconfig.soc new file mode 100644 index 00000000000..48d6d506cc9 --- /dev/null +++ b/soc/starfive/jh71xx/Kconfig.soc @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STARFIVE_JH71XX + bool + help + Starfive JH71XX series + +config SOC_JH7100 + bool + select SOC_SERIES_STARFIVE_JH71XX + help + Starfive JH7100 + +config SOC_SERIES + default "starfive_jh71xx" if SOC_SERIES_STARFIVE_JH71XX + +config SOC + default "jh7100" if SOC_JH7100 diff --git a/soc/starfive/jh71xx/soc.yml b/soc/starfive/jh71xx/soc.yml new file mode 100644 index 00000000000..1d424c2f540 --- /dev/null +++ b/soc/starfive/jh71xx/soc.yml @@ -0,0 +1,4 @@ +series: +- name: starfive_jh71xx + socs: + - name: jh7100 diff --git a/soc/arc/snps_arc_iot/CMakeLists.txt b/soc/synopsys/arc_iot/CMakeLists.txt similarity index 100% rename from soc/arc/snps_arc_iot/CMakeLists.txt rename to soc/synopsys/arc_iot/CMakeLists.txt diff --git a/soc/synopsys/arc_iot/Kconfig b/soc/synopsys/arc_iot/Kconfig new file mode 100644 index 00000000000..362d2d1ae71 --- /dev/null +++ b/soc/synopsys/arc_iot/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_IOT + select ARC + select CPU_HAS_MPU + select CPU_HAS_FPU diff --git a/soc/synopsys/arc_iot/Kconfig.defconfig b/soc/synopsys/arc_iot/Kconfig.defconfig new file mode 100644 index 00000000000..9c64732bf1f --- /dev/null +++ b/soc/synopsys/arc_iot/Kconfig.defconfig @@ -0,0 +1,34 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ARC_IOT + +config CPU_EM4_FPUS + default y + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 4 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). + default 4 + +config ARC_MPU_VER + default 2 + +config NUM_IRQS + # must be > the highest interrupt number used + default 95 + +config RGF_NUM_BANKS + default 2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 144000000 + +config HARVARD + default y + +config ARC_FIRQ + default y + +endif # ARC_IOT diff --git a/soc/synopsys/arc_iot/Kconfig.soc b/soc/synopsys/arc_iot/Kconfig.soc new file mode 100644 index 00000000000..d7e5a54079f --- /dev/null +++ b/soc/synopsys/arc_iot/Kconfig.soc @@ -0,0 +1,11 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_IOT + bool + help + Synopsys ARC IoT SoC + +config SOC + default "arc_iot" if SOC_ARC_IOT diff --git a/soc/arc/snps_arc_iot/linker.ld b/soc/synopsys/arc_iot/linker.ld similarity index 100% rename from soc/arc/snps_arc_iot/linker.ld rename to soc/synopsys/arc_iot/linker.ld diff --git a/soc/arc/snps_arc_iot/soc.c b/soc/synopsys/arc_iot/soc.c similarity index 100% rename from soc/arc/snps_arc_iot/soc.c rename to soc/synopsys/arc_iot/soc.c diff --git a/soc/synopsys/arc_iot/soc.yml b/soc/synopsys/arc_iot/soc.yml new file mode 100644 index 00000000000..9ee993439e6 --- /dev/null +++ b/soc/synopsys/arc_iot/soc.yml @@ -0,0 +1,4 @@ +series: +- name: arc_iot + socs: + - name: arc_iot diff --git a/soc/arc/snps_arc_iot/sysconf.c b/soc/synopsys/arc_iot/sysconf.c similarity index 100% rename from soc/arc/snps_arc_iot/sysconf.c rename to soc/synopsys/arc_iot/sysconf.c diff --git a/soc/arc/snps_arc_iot/sysconf.h b/soc/synopsys/arc_iot/sysconf.h similarity index 100% rename from soc/arc/snps_arc_iot/sysconf.h rename to soc/synopsys/arc_iot/sysconf.h diff --git a/soc/synopsys/emsdp/CMakeLists.txt b/soc/synopsys/emsdp/CMakeLists.txt new file mode 100644 index 00000000000..ce71339f637 --- /dev/null +++ b/soc/synopsys/emsdp/CMakeLists.txt @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 +zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata) + +if(CONFIG_SOC_EMSDP_EM4) + zephyr_compile_options(-mmpy-option=3 -mno-div-rem) +elseif(CONFIG_SOC_EMSDP_EM6) + zephyr_compile_options(-mmpy-option=3 -mno-div-rem) +elseif(CONFIG_SOC_EMSDP_EM5D) + zephyr_compile_options(-mmpy-option=6) +elseif(CONFIG_SOC_EMSDP_EM7D) + zephyr_compile_options(-mmpy-option=6) +elseif(CONFIG_SOC_EMSDP_EM7D_ESP) + zephyr_compile_options(-mmpy-option=6) +elseif(CONFIG_SOC_EMSDP_EM9D) + zephyr_compile_options(-mmpy-option=6) + zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpus_all) +elseif(CONFIG_SOC_EMSDP_EM11D) + zephyr_compile_options(-mmpy-option=6) + zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/synopsys/emsdp/Kconfig b/soc/synopsys/emsdp/Kconfig new file mode 100644 index 00000000000..424620ed6fc --- /dev/null +++ b/soc/synopsys/emsdp/Kconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_EMSDP + select ARC + +config SOC_EMSDP_EM4 + select CPU_HAS_MPU + +config SOC_EMSDP_EM5D + select CPU_HAS_MPU + select CPU_HAS_FPU + +config SOC_EMSDP_EM6 + select CPU_HAS_MPU + +config SOC_EMSDP_EM7D + select CPU_HAS_MPU + select CPU_HAS_FPU + +config SOC_EMSDP_EM7D_ESP + select CPU_HAS_MPU + select CPU_HAS_FPU + select ARC_HAS_SECURE + +config SOC_EMSDP_EM9D + select CPU_HAS_MPU + select CPU_HAS_FPU + +config SOC_EMSDP_EM11D + select CPU_HAS_MPU + select CPU_HAS_FPU diff --git a/soc/synopsys/emsdp/Kconfig.defconfig b/soc/synopsys/emsdp/Kconfig.defconfig new file mode 100644 index 00000000000..7807c53c931 --- /dev/null +++ b/soc/synopsys/emsdp/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ARC_EMSDP + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 4 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). + default 4 + +rsource "Kconfig.defconfig.*" + +endif # SOC_ARC_EMSDP diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em11d b/soc/synopsys/emsdp/Kconfig.defconfig.em11d similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em11d rename to soc/synopsys/emsdp/Kconfig.defconfig.em11d diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em4 b/soc/synopsys/emsdp/Kconfig.defconfig.em4 similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em4 rename to soc/synopsys/emsdp/Kconfig.defconfig.em4 diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em5d b/soc/synopsys/emsdp/Kconfig.defconfig.em5d similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em5d rename to soc/synopsys/emsdp/Kconfig.defconfig.em5d diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em6 b/soc/synopsys/emsdp/Kconfig.defconfig.em6 similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em6 rename to soc/synopsys/emsdp/Kconfig.defconfig.em6 diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em7d b/soc/synopsys/emsdp/Kconfig.defconfig.em7d similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em7d rename to soc/synopsys/emsdp/Kconfig.defconfig.em7d diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em7d_esp b/soc/synopsys/emsdp/Kconfig.defconfig.em7d_esp similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em7d_esp rename to soc/synopsys/emsdp/Kconfig.defconfig.em7d_esp diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em9d b/soc/synopsys/emsdp/Kconfig.defconfig.em9d similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em9d rename to soc/synopsys/emsdp/Kconfig.defconfig.em9d diff --git a/soc/synopsys/emsdp/Kconfig.soc b/soc/synopsys/emsdp/Kconfig.soc new file mode 100644 index 00000000000..faa62ee05e7 --- /dev/null +++ b/soc/synopsys/emsdp/Kconfig.soc @@ -0,0 +1,59 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_EMSDP + bool + +config SOC_EMSDP_EM4 + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM4 of EMSDP + +config SOC_EMSDP_EM5D + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM5D of EMSDP + +config SOC_EMSDP_EM6 + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM6 of EMSDP + +config SOC_EMSDP_EM7D + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM7D of EMSDP + +config SOC_EMSDP_EM7D_ESP + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM7D+ESP of EMSDP + +config SOC_EMSDP_EM9D + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM9D of EMSDP + +config SOC_EMSDP_EM11D + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM11D of EMSDP + +config SOC_SERIES + default "emsdp" if SOC_ARC_EMSDP + +config SOC + default "emsdp_em4" if SOC_EMSDP_EM4 + default "emsdp_em5d" if SOC_EMSDP_EM5D + default "emsdp_em6" if SOC_EMSDP_EM6 + default "emsdp_em7d" if SOC_EMSDP_EM7D + default "emsdp_em7d_esp" if SOC_EMSDP_EM7D_ESP + default "emsdp_em9d" if SOC_EMSDP_EM9D + default "emsdp_em11d" if SOC_EMSDP_EM11D diff --git a/soc/arc/snps_emsdp/linker.ld b/soc/synopsys/emsdp/linker.ld similarity index 100% rename from soc/arc/snps_emsdp/linker.ld rename to soc/synopsys/emsdp/linker.ld diff --git a/soc/arc/snps_emsdp/pinctrl_soc.h b/soc/synopsys/emsdp/pinctrl_soc.h similarity index 100% rename from soc/arc/snps_emsdp/pinctrl_soc.h rename to soc/synopsys/emsdp/pinctrl_soc.h diff --git a/soc/synopsys/emsdp/soc.yml b/soc/synopsys/emsdp/soc.yml new file mode 100644 index 00000000000..c308d85d0f0 --- /dev/null +++ b/soc/synopsys/emsdp/soc.yml @@ -0,0 +1,10 @@ +series: +- name: emsdp + socs: + - name: emsdp_em4 + - name: emsdp_em5d + - name: emsdp_em6 + - name: emsdp_em7d + - name: emsdp_em7d_esp + - name: emsdp_em9d + - name: emsdp_em11d diff --git a/soc/synopsys/emsk/CMakeLists.txt b/soc/synopsys/emsk/CMakeLists.txt new file mode 100644 index 00000000000..ea14ab053c8 --- /dev/null +++ b/soc/synopsys/emsk/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata -mmpy-option=6) + +if(CONFIG_SOC_EMSK_EM9D) + zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpus_all) +elseif(CONFIG_SOC_EMSK_EM11D) + zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all) +endif() + +zephyr_sources(soc_config.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/synopsys/emsk/Kconfig b/soc/synopsys/emsk/Kconfig new file mode 100644 index 00000000000..88cdfe70671 --- /dev/null +++ b/soc/synopsys/emsk/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EMSK + select ARC + +config SOC_EMSK_EM7D + select CPU_HAS_MPU + +config SOC_EMSK_EM9D + select CPU_HAS_FPU + +config SOC_EMSK_EM11D + select CPU_HAS_FPU diff --git a/soc/synopsys/emsk/Kconfig.defconfig b/soc/synopsys/emsk/Kconfig.defconfig new file mode 100644 index 00000000000..e7f231ebcf2 --- /dev/null +++ b/soc/synopsys/emsk/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_EMSK + +rsource "Kconfig.defconfig.*" + +endif # SOC_EMSK diff --git a/soc/arc/snps_emsk/Kconfig.defconfig.em11d b/soc/synopsys/emsk/Kconfig.defconfig.em11d similarity index 87% rename from soc/arc/snps_emsk/Kconfig.defconfig.em11d rename to soc/synopsys/emsk/Kconfig.defconfig.em11d index ad965710b51..4c0854682fd 100644 --- a/soc/arc/snps_emsk/Kconfig.defconfig.em11d +++ b/soc/synopsys/emsk/Kconfig.defconfig.em11d @@ -14,8 +14,8 @@ config NUM_IRQ_PRIO_LEVELS config NUM_IRQS # must be > the highest interrupt number used - default 38 if BOARD_EM_STARTERKIT_R23 - default 36 if BOARD_EM_STARTERKIT_R22 + default 38 if "$(BOARD_REVISION)" = "2.3" + default 36 if "$(BOARD_REVISION)" = "2.2" config RGF_NUM_BANKS default 2 diff --git a/soc/synopsys/emsk/Kconfig.defconfig.em7d b/soc/synopsys/emsk/Kconfig.defconfig.em7d new file mode 100644 index 00000000000..3decdef43cb --- /dev/null +++ b/soc/synopsys/emsk/Kconfig.defconfig.em7d @@ -0,0 +1,55 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_EMSK_EM7D + +config CPU_EM4_DMIPS + default y + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 4 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). + default 4 + +config NUM_IRQS + # must be > the highest interrupt number used + default 38 if "$(BOARD_REVISION)" = "2.3" + default 36 if "$(BOARD_REVISION)" = "2.2" + +config ARC_MPU_VER + default 4 if "$(BOARD_REVISION)" = "2.3" + default 2 if "$(BOARD_REVISION)" = "2.2" + +config RGF_NUM_BANKS + default 1 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 if "$(BOARD_REVISION)" = "2.3" + default 30000000 if "$(BOARD_REVISION)" = "2.2" + +config HARVARD + default y + +config ARC_FIRQ + default n if "$(BOARD_REVISION)" = "2.3" + default y if "$(BOARD_REVISION)" = "2.2" + +config CACHE_MANAGEMENT + default y + +if (ARC_MPU_VER = 2) + +config MAIN_STACK_SIZE + default 2048 + +config IDLE_STACK_SIZE + default 2048 + +config ZTEST_STACK_SIZE + default 2048 + depends on ZTEST + +endif # ARC_MPU_VER + +endif # SOC_EMSK_EM7D diff --git a/soc/arc/snps_emsk/Kconfig.defconfig.em9d b/soc/synopsys/emsk/Kconfig.defconfig.em9d similarity index 86% rename from soc/arc/snps_emsk/Kconfig.defconfig.em9d rename to soc/synopsys/emsk/Kconfig.defconfig.em9d index 00114baac3e..cebfde7d74d 100644 --- a/soc/arc/snps_emsk/Kconfig.defconfig.em9d +++ b/soc/synopsys/emsk/Kconfig.defconfig.em9d @@ -14,8 +14,8 @@ config NUM_IRQ_PRIO_LEVELS config NUM_IRQS # must be > the highest interrupt number used - default 38 if BOARD_EM_STARTERKIT_R23 - default 36 if BOARD_EM_STARTERKIT_R22 + default 38 if "$(BOARD_REVISION)" = "2.3" + default 36 if "$(BOARD_REVISION)" = "2.2" config RGF_NUM_BANKS default 2 diff --git a/soc/synopsys/emsk/Kconfig.soc b/soc/synopsys/emsk/Kconfig.soc new file mode 100644 index 00000000000..d74e73ddc89 --- /dev/null +++ b/soc/synopsys/emsk/Kconfig.soc @@ -0,0 +1,34 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EMSK + bool + help + Synopsys ARC EM Starter Kit SoC + +config SOC_EMSK_EM7D + bool + select SOC_EMSK + help + Synopsys ARC EM7D of EMSK + +config SOC_EMSK_EM9D + bool + select SOC_EMSK + help + Synopsys ARC EM9D of EMSK + +config SOC_EMSK_EM11D + bool + select SOC_EMSK + help + Synopsys ARC EM11D of EMSK + +config SOC_SERIES + default "emsk" if SOC_EMSK + +config SOC + default "emsk_em7d" if SOC_EMSK_EM7D + default "emsk_em9d" if SOC_EMSK_EM9D + default "emsk_em11d" if SOC_EMSK_EM11D diff --git a/soc/arc/snps_emsk/linker.ld b/soc/synopsys/emsk/linker.ld similarity index 100% rename from soc/arc/snps_emsk/linker.ld rename to soc/synopsys/emsk/linker.ld diff --git a/soc/synopsys/emsk/soc.yml b/soc/synopsys/emsk/soc.yml new file mode 100644 index 00000000000..43623616a49 --- /dev/null +++ b/soc/synopsys/emsk/soc.yml @@ -0,0 +1,6 @@ +series: +- name: emsk + socs: + - name: emsk_em7d + - name: emsk_em9d + - name: emsk_em11d diff --git a/soc/arc/snps_emsk/soc_config.c b/soc/synopsys/emsk/soc_config.c similarity index 100% rename from soc/arc/snps_emsk/soc_config.c rename to soc/synopsys/emsk/soc_config.c diff --git a/soc/arc/snps_arc_hsdk/CMakeLists.txt b/soc/synopsys/hsdk/CMakeLists.txt similarity index 100% rename from soc/arc/snps_arc_hsdk/CMakeLists.txt rename to soc/synopsys/hsdk/CMakeLists.txt diff --git a/soc/synopsys/hsdk/Kconfig b/soc/synopsys/hsdk/Kconfig new file mode 100644 index 00000000000..1c92ff4bb53 --- /dev/null +++ b/soc/synopsys/hsdk/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_HSDK + select ARC + select CPU_HAS_FPU diff --git a/soc/synopsys/hsdk/Kconfig.defconfig b/soc/synopsys/hsdk/Kconfig.defconfig new file mode 100644 index 00000000000..c86f4e25c67 --- /dev/null +++ b/soc/synopsys/hsdk/Kconfig.defconfig @@ -0,0 +1,46 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ARC_HSDK + +config CPU_HS3X + default y + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 2 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs). + default 2 + +config NUM_IRQS + # must be > the highest interrupt number used + default 88 + +config RGF_NUM_BANKS + default 2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 500000000 + +config ARC_FIRQ + default y + +config CODE_DENSITY + default y + +config ARCV2_TIMER_IRQ_PRIORITY + default 1 + +config ARC_CONNECT + default y + +config MP_MAX_NUM_CPUS + default 4 + +config UART_NS16550_ACCESS_WORD_ONLY + default y + depends on UART_NS16550 + +config ARC_HAS_ACCL_REGS + default y + +endif # ARC_HSDK diff --git a/soc/synopsys/hsdk/Kconfig.soc b/soc/synopsys/hsdk/Kconfig.soc new file mode 100644 index 00000000000..51375c0861b --- /dev/null +++ b/soc/synopsys/hsdk/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_HSDK + bool + +config SOC + default "arc_hsdk" if SOC_ARC_HSDK diff --git a/soc/arc/snps_arc_hsdk/linker.ld b/soc/synopsys/hsdk/linker.ld similarity index 100% rename from soc/arc/snps_arc_hsdk/linker.ld rename to soc/synopsys/hsdk/linker.ld diff --git a/soc/synopsys/hsdk/soc.yml b/soc/synopsys/hsdk/soc.yml new file mode 100644 index 00000000000..b66e8720228 --- /dev/null +++ b/soc/synopsys/hsdk/soc.yml @@ -0,0 +1,4 @@ +series: +- name: arc_hsdk + socs: + - name: arc_hsdk diff --git a/soc/synopsys/hsdk4xd/CMakeLists.txt b/soc/synopsys/hsdk4xd/CMakeLists.txt new file mode 100644 index 00000000000..e1765fe1136 --- /dev/null +++ b/soc/synopsys/hsdk4xd/CMakeLists.txt @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(COMPILER STREQUAL gcc) + # GNU compiler options + zephyr_compile_options(-mno-sdata) + zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpud_all) +else() + # MWDT compiler options + zephyr_compile_options(-arcv2hs -core4 -Xdual_issue -Xcode_density -Hrgf_banked_regs=32 -HL + -Xatomic -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist + -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc -Hld_cycles=2) + + zephyr_compile_options_ifdef(CONFIG_FPU -Xfpu_mac -Xfpud_div) + + zephyr_ld_options(-Hlib=hs48_slc_full) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/synopsys/hsdk4xd/Kconfig b/soc/synopsys/hsdk4xd/Kconfig new file mode 100644 index 00000000000..27abcacf83f --- /dev/null +++ b/soc/synopsys/hsdk4xd/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_HSDK4XD + select ARC + select CPU_HAS_FPU + select CPU_HAS_DSP diff --git a/soc/synopsys/hsdk4xd/Kconfig.defconfig b/soc/synopsys/hsdk4xd/Kconfig.defconfig new file mode 100644 index 00000000000..a47f25d09d0 --- /dev/null +++ b/soc/synopsys/hsdk4xd/Kconfig.defconfig @@ -0,0 +1,53 @@ +# Copyright (c) 2023 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ARC_HSDK4XD + +config CPU_HS4X + default y + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 2 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs). + default 2 + +config NUM_IRQS + # must be > the highest interrupt number used + default 88 + +config RGF_NUM_BANKS + # Actually cpu has 4 banks but zephys currently supports up to 2 + default 2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 500000000 + +config ARC_FIRQ + default y + +config CODE_DENSITY + default y + +config ARCV2_TIMER_IRQ_PRIORITY + default 1 + +config ARC_CONNECT + default y + +config MP_MAX_NUM_CPUS + default 4 + +config UART_NS16550_ACCESS_WORD_ONLY + default y + depends on UART_NS16550 + +config ARC_HAS_ACCL_REGS + default y + +config ARC_EARLY_SOC_INIT + default y + +config ARC_HAS_STACK_CHECKING + default n + +endif # SOC_ARC_HS4XD diff --git a/soc/synopsys/hsdk4xd/Kconfig.soc b/soc/synopsys/hsdk4xd/Kconfig.soc new file mode 100644 index 00000000000..878a800b6bf --- /dev/null +++ b/soc/synopsys/hsdk4xd/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_HSDK4XD + bool + help + Synopsys ARC HSDK4XD SoC + +config SOC + default "arc_hsdk4xd" if SOC_ARC_HSDK4XD diff --git a/soc/arc/snps_arc_hsdk4xd/linker.ld b/soc/synopsys/hsdk4xd/linker.ld similarity index 100% rename from soc/arc/snps_arc_hsdk4xd/linker.ld rename to soc/synopsys/hsdk4xd/linker.ld diff --git a/soc/synopsys/hsdk4xd/soc.yml b/soc/synopsys/hsdk4xd/soc.yml new file mode 100644 index 00000000000..2200428bde5 --- /dev/null +++ b/soc/synopsys/hsdk4xd/soc.yml @@ -0,0 +1,4 @@ +series: +- name: arc_hsdk4xd + socs: + - name: arc_hsdk4xd diff --git a/soc/arc/snps_arc_hsdk4xd/soc_ctrl.h b/soc/synopsys/hsdk4xd/soc_ctrl.h similarity index 99% rename from soc/arc/snps_arc_hsdk4xd/soc_ctrl.h rename to soc/synopsys/hsdk4xd/soc_ctrl.h index bde8f04f6ed..93d50d3eb20 100644 --- a/soc/arc/snps_arc_hsdk4xd/soc_ctrl.h +++ b/soc/synopsys/hsdk4xd/soc_ctrl.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #ifndef _ARC_HSDK4XD_SOC_CTRL_H_ #define _ARC_HSDK4XD_SOC_CTRL_H_ diff --git a/soc/arc/snps_arc_hsdk4xd/tune_build_ops.cmake b/soc/synopsys/hsdk4xd/tune_build_ops.cmake similarity index 100% rename from soc/arc/snps_arc_hsdk4xd/tune_build_ops.cmake rename to soc/synopsys/hsdk4xd/tune_build_ops.cmake diff --git a/soc/arc/snps_nsim/CMakeLists.txt b/soc/synopsys/nsim/CMakeLists.txt similarity index 100% rename from soc/arc/snps_nsim/CMakeLists.txt rename to soc/synopsys/nsim/CMakeLists.txt diff --git a/soc/synopsys/nsim/Kconfig b/soc/synopsys/nsim/Kconfig new file mode 100644 index 00000000000..c3077115265 --- /dev/null +++ b/soc/synopsys/nsim/Kconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NSIM + select ARC + +config SOC_NSIM_EM + select CPU_HAS_MPU + +config SOC_NSIM_EM7D_V22 + select CPU_HAS_MPU + select CPU_HAS_FPU + +config SOC_NSIM_EM11D + select CPU_HAS_MPU + select CPU_HAS_DSP + +config SOC_NSIM_SEM + select CPU_HAS_MPU + select CPU_HAS_FPU + select ARC_HAS_SECURE + +config SOC_NSIM_HS + select CPU_HAS_FPU + select CPU_HAS_MPU + +config SOC_NSIM_HS_SMP + select CPU_HAS_FPU + +config SOC_NSIM_HS_MPUV6 + select CPU_HAS_MPU + select CPU_HAS_FPU diff --git a/soc/synopsys/nsim/Kconfig.defconfig b/soc/synopsys/nsim/Kconfig.defconfig new file mode 100644 index 00000000000..31219661142 --- /dev/null +++ b/soc/synopsys/nsim/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NSIM + +config XIP + default n + +rsource "Kconfig.defconfig.*" + +endif # SOC_NSIM diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.em b/soc/synopsys/nsim/Kconfig.defconfig.em similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.em rename to soc/synopsys/nsim/Kconfig.defconfig.em diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.em11d b/soc/synopsys/nsim/Kconfig.defconfig.em11d similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.em11d rename to soc/synopsys/nsim/Kconfig.defconfig.em11d diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.em7d_v22 b/soc/synopsys/nsim/Kconfig.defconfig.em7d_v22 similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.em7d_v22 rename to soc/synopsys/nsim/Kconfig.defconfig.em7d_v22 diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs b/soc/synopsys/nsim/Kconfig.defconfig.hs similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs rename to soc/synopsys/nsim/Kconfig.defconfig.hs diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs5x b/soc/synopsys/nsim/Kconfig.defconfig.hs5x similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs5x rename to soc/synopsys/nsim/Kconfig.defconfig.hs5x diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs5x_smp b/soc/synopsys/nsim/Kconfig.defconfig.hs5x_smp similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs5x_smp rename to soc/synopsys/nsim/Kconfig.defconfig.hs5x_smp diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs6x b/soc/synopsys/nsim/Kconfig.defconfig.hs6x similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs6x rename to soc/synopsys/nsim/Kconfig.defconfig.hs6x diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp b/soc/synopsys/nsim/Kconfig.defconfig.hs6x_smp similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp rename to soc/synopsys/nsim/Kconfig.defconfig.hs6x_smp diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs_mpuv6 b/soc/synopsys/nsim/Kconfig.defconfig.hs_mpuv6 similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs_mpuv6 rename to soc/synopsys/nsim/Kconfig.defconfig.hs_mpuv6 diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs_smp b/soc/synopsys/nsim/Kconfig.defconfig.hs_smp similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs_smp rename to soc/synopsys/nsim/Kconfig.defconfig.hs_smp diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.sem b/soc/synopsys/nsim/Kconfig.defconfig.sem similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.sem rename to soc/synopsys/nsim/Kconfig.defconfig.sem diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.vpx5 b/soc/synopsys/nsim/Kconfig.defconfig.vpx5 similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.vpx5 rename to soc/synopsys/nsim/Kconfig.defconfig.vpx5 diff --git a/soc/synopsys/nsim/Kconfig.soc b/soc/synopsys/nsim/Kconfig.soc new file mode 100644 index 00000000000..f12b143a871 --- /dev/null +++ b/soc/synopsys/nsim/Kconfig.soc @@ -0,0 +1,94 @@ +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NSIM + bool + +config SOC_NSIM_EM + bool + select SOC_NSIM + help + Synopsys ARC EM4 in nSIM + +config SOC_NSIM_EM7D_V22 + bool + select SOC_NSIM + help + Synopsys ARC EM7D_V22 in nSIM + +config SOC_NSIM_EM11D + bool + select SOC_NSIM + help + Synopsys ARC EM11D in nSIM + +config SOC_NSIM_SEM + bool + select SOC_NSIM + help + Synopsys ARC SEM in nSIM + +config SOC_NSIM_HS + bool + select SOC_NSIM + help + Synopsys ARC HS3X in nSIM + +config SOC_NSIM_HS_SMP + bool + select SOC_NSIM + help + Multi-core Synopsys ARC HS3X in nSIM + +config SOC_NSIM_HS_MPUV6 + bool + select SOC_NSIM + help + Synopsys ARC HS3X with MPU v6 in nSIM + +config SOC_NSIM_VPX5 + bool + select SOC_NSIM + help + Synopsys ARC VPX5 in nSIM + +config SOC_NSIM_HS5X + bool + select SOC_NSIM + help + Synopsys ARC HS5x in nSIM + +config SOC_NSIM_HS5X_SMP + bool + select SOC_NSIM + help + Multi-core Synopsys ARC HS5x in nSIM + +config SOC_NSIM_HS6X + bool + select SOC_NSIM + help + Synopsys ARC HS6x in nSIM + +config SOC_NSIM_HS6X_SMP + bool + select SOC_NSIM + help + Multi-core Synopsys ARC HS6x in nSIM + +config SOC + default "nsim_em" if SOC_NSIM_EM + default "nsim_em7d_v22" if SOC_NSIM_EM7D_V22 + default "nsim_em11d" if SOC_NSIM_EM11D + default "nsim_sem" if SOC_NSIM_SEM + default "nsim_hs" if SOC_NSIM_HS + default "nsim_hs_smp" if SOC_NSIM_HS_SMP + default "nsim_hs_mpuv6" if SOC_NSIM_HS_MPUV6 + default "nsim_vpx5" if SOC_NSIM_VPX5 + default "nsim_hs5x" if SOC_NSIM_HS5X + default "nsim_hs5x_smp" if SOC_NSIM_HS5X_SMP + default "nsim_hs6x" if SOC_NSIM_HS6X + default "nsim_hs6x_smp" if SOC_NSIM_HS6X_SMP + +config SOC_SERIES + default "nsim" if SOC_NSIM diff --git a/soc/arc/snps_nsim/linker.ld b/soc/synopsys/nsim/linker.ld similarity index 100% rename from soc/arc/snps_nsim/linker.ld rename to soc/synopsys/nsim/linker.ld diff --git a/soc/synopsys/nsim/soc.yml b/soc/synopsys/nsim/soc.yml new file mode 100644 index 00000000000..a3a427ca006 --- /dev/null +++ b/soc/synopsys/nsim/soc.yml @@ -0,0 +1,15 @@ +series: +- name: nsim + socs: + - name: nsim_em + - name: nsim_em7d_v22 + - name: nsim_em11d + - name: nsim_hs + - name: nsim_hs_smp + - name: nsim_hs_mpuv6 + - name: nsim_hs5x + - name: nsim_hs5x_smp + - name: nsim_hs6x + - name: nsim_hs6x_smp + - name: nsim_vpx5 + - name: nsim_sem diff --git a/soc/synopsys/qemu_arc/CMakeLists.txt b/soc/synopsys/qemu_arc/CMakeLists.txt new file mode 100644 index 00000000000..f2925afa745 --- /dev/null +++ b/soc/synopsys/qemu_arc/CMakeLists.txt @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(COMPILER STREQUAL gcc) + zephyr_compile_options(-mcpu=${GCC_M_CPU}) + + zephyr_compile_options_ifdef(CONFIG_ISA_ARCV2 -mno-sdata) +else() + zephyr_compile_options_ifdef(CONFIG_SOC_QEMU_ARC_HS -arcv2hs -core2 -Xatomic + -Xunaligned -Xcode_density -Xswap -Xbitscan + -Xmpy_option=qmpyh -Xshift_assist -Xbarrel_shifter + -Xtimer0 -Xtimer1) + + zephyr_ld_option_ifdef(CONFIG_SOC_QEMU_ARC_HS -Hlib=hs38_full) + + if(NOT CONFIG_SOC_QEMU_ARC_HS) + message(WARNING "QEMU ARC platforms other than HS3X are not supported yet with MW toolchain") + endif() +endif() + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/synopsys/qemu_arc/Kconfig b/soc/synopsys/qemu_arc/Kconfig new file mode 100644 index 00000000000..ef3cfb984d3 --- /dev/null +++ b/soc/synopsys/qemu_arc/Kconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2020 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_ARC + select ARC + select CPU_HAS_MPU + +config SOC_QEMU_ARC_EM + select CPU_EM4 + +config SOC_QEMU_ARC_HS + select CPU_HS3X + +config SOC_QEMU_ARC_HS5X + select CPU_HS5X + +config SOC_QEMU_ARC_HS6X + select CPU_HS6X diff --git a/soc/synopsys/qemu_arc/Kconfig.defconfig b/soc/synopsys/qemu_arc/Kconfig.defconfig new file mode 100644 index 00000000000..a8a7550ef53 --- /dev/null +++ b/soc/synopsys/qemu_arc/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2020 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_QEMU_ARC + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 10000000 + +config RGF_NUM_BANKS + default 1 + +config ARC_FIRQ + default n + +config NUM_IRQ_PRIO_LEVELS + default 15 + +config NUM_IRQS + default 26 + +# Technically ARC HS supports MPUv3, but not v2. But given MPUv3 +# is the same as v2 but with minimal region size of 32 bytes, we +# may assume MPUv3 is just a subset of MPUv2. + +config ARC_MPU_VER + default 2 + +endif diff --git a/soc/synopsys/qemu_arc/Kconfig.soc b/soc/synopsys/qemu_arc/Kconfig.soc new file mode 100644 index 00000000000..9644bd9a534 --- /dev/null +++ b/soc/synopsys/qemu_arc/Kconfig.soc @@ -0,0 +1,30 @@ +# Copyright (c) 2020 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_ARC + bool + +config SOC_QEMU_ARC_EM + bool + select SOC_QEMU_ARC + +config SOC_QEMU_ARC_HS + bool + select SOC_QEMU_ARC + +config SOC_QEMU_ARC_HS5X + bool + select SOC_QEMU_ARC + +config SOC_QEMU_ARC_HS6X + bool + select SOC_QEMU_ARC + +config SOC_SERIES + default "qemu_arc" if SOC_QEMU_ARC + +config SOC + default "qemu_arc_em" if SOC_QEMU_ARC_EM + default "qemu_arc_hs" if SOC_QEMU_ARC_HS + default "qemu_arc_hs5x" if SOC_QEMU_ARC_HS5X + default "qemu_arc_hs6x" if SOC_QEMU_ARC_HS6X diff --git a/soc/arc/snps_qemu/linker.ld b/soc/synopsys/qemu_arc/linker.ld similarity index 100% rename from soc/arc/snps_qemu/linker.ld rename to soc/synopsys/qemu_arc/linker.ld diff --git a/soc/synopsys/qemu_arc/soc.yml b/soc/synopsys/qemu_arc/soc.yml new file mode 100644 index 00000000000..06caef5f3d9 --- /dev/null +++ b/soc/synopsys/qemu_arc/soc.yml @@ -0,0 +1,7 @@ +series: +- name: qemu_arc + socs: + - name: qemu_arc_em + - name: qemu_arc_hs + - name: qemu_arc_hs5x + - name: qemu_arc_hs6x diff --git a/soc/riscv/intel_niosv/CMakeLists.txt b/soc/telink/tlsr/CMakeLists.txt similarity index 100% rename from soc/riscv/intel_niosv/CMakeLists.txt rename to soc/telink/tlsr/CMakeLists.txt diff --git a/soc/telink/tlsr/Kconfig b/soc/telink/tlsr/Kconfig new file mode 100644 index 00000000000..ffc4a398905 --- /dev/null +++ b/soc/telink/tlsr/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_TELINK_TLSR + +rsource "*/Kconfig" + +endif # SOC_FAMILY_TELINK_TLSR diff --git a/soc/telink/tlsr/Kconfig.defconfig b/soc/telink/tlsr/Kconfig.defconfig new file mode 100644 index 00000000000..58492dd1ac9 --- /dev/null +++ b/soc/telink/tlsr/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_TELINK_TLSR + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_TELINK_TLSR diff --git a/soc/telink/tlsr/Kconfig.soc b/soc/telink/tlsr/Kconfig.soc new file mode 100644 index 00000000000..98f5cbf1b83 --- /dev/null +++ b/soc/telink/tlsr/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_TELINK_TLSR + bool + +config SOC_FAMILY + default "telink_tlsr" if SOC_FAMILY_TELINK_TLSR + +rsource "*/Kconfig.soc" diff --git a/soc/telink/tlsr/soc.yml b/soc/telink/tlsr/soc.yml new file mode 100644 index 00000000000..e982d5e69dc --- /dev/null +++ b/soc/telink/tlsr/soc.yml @@ -0,0 +1,6 @@ +family: + - name: telink_tlsr + series: + - name: tlsr951x + socs: + - name: tlsr9518 diff --git a/soc/telink/tlsr/tlsr951x/CMakeLists.txt b/soc/telink/tlsr/tlsr951x/CMakeLists.txt new file mode 100644 index 00000000000..9e1dff40e4b --- /dev/null +++ b/soc/telink/tlsr/tlsr951x/CMakeLists.txt @@ -0,0 +1,20 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + start.S + soc_irq.S + soc.c +) + +zephyr_include_directories(.) + +# Force using BFD-LD +zephyr_ld_options(-fuse-ld=bfd) + +# Set compile options +zephyr_compile_options_ifdef(CONFIG_TELINK_B91_HWDSP -mext-dsp) +zephyr_compile_options_ifndef(CONFIG_RISCV_GP -mno-relax) +zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/telink/tlsr/tlsr951x/Kconfig b/soc/telink/tlsr/tlsr951x/Kconfig new file mode 100644 index 00000000000..80fa44e6658 --- /dev/null +++ b/soc/telink/tlsr/tlsr951x/Kconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_TLSR951X + bool + select RISCV + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + select HAS_TELINK_DRIVERS + select ATOMIC_OPERATIONS_BUILTIN + select CPU_HAS_FPU + select INCLUDE_RESET_VECTOR + +if SOC_SERIES_TLSR951X + +config TELINK_B91_HWDSP + bool "Support Hardware DSP" + select RISCV_SOC_CONTEXT_SAVE + +config TELINK_B91_PFT_ARCH + bool "Support performance throttling" + default y + select RISCV_SOC_CONTEXT_SAVE + +endif # SOC_SERIES_TLSR951X diff --git a/soc/telink/tlsr/tlsr951x/Kconfig.defconfig b/soc/telink/tlsr/tlsr951x/Kconfig.defconfig new file mode 100644 index 00000000000..7ad94f13430 --- /dev/null +++ b/soc/telink/tlsr/tlsr951x/Kconfig.defconfig @@ -0,0 +1,47 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_TLSR951X + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 32000 + +config RISCV_SOC_INTERRUPT_INIT + bool + default y + +config RISCV_GP + bool + default y + +config NUM_IRQS + int + default 64 + +config PINCTRL + default y + +config XIP + bool + default n + +config MAIN_STACK_SIZE + int + default 2048 + +config IDLE_STACK_SIZE + int + default 1536 + +config TEST_EXTRA_STACK_SIZE + int + default 1024 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config HAS_FLASH_LOAD_OFFSET + default y if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_TLSR951X diff --git a/soc/telink/tlsr/tlsr951x/Kconfig.soc b/soc/telink/tlsr/tlsr951x/Kconfig.soc new file mode 100644 index 00000000000..102ef4390a6 --- /dev/null +++ b/soc/telink/tlsr/tlsr951x/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_TLSR951X + bool + select SOC_FAMILY_TELINK_TLSR + help + Telink TLSR951X + +config SOC_TLSR9518 + bool + select SOC_SERIES_TLSR951X + help + Telink TLSR9518 + +config SOC_SERIES + default "tlsr951x" if SOC_SERIES_TLSR951X + +config SOC + default "tlsr9518" if SOC_TLSR9518 diff --git a/soc/riscv/telink_tlsr/tlsr951x/init.ld b/soc/telink/tlsr/tlsr951x/init.ld similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/init.ld rename to soc/telink/tlsr/tlsr951x/init.ld diff --git a/soc/riscv/telink_tlsr/tlsr951x/linker.ld b/soc/telink/tlsr/tlsr951x/linker.ld similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/linker.ld rename to soc/telink/tlsr/tlsr951x/linker.ld diff --git a/soc/riscv/telink_tlsr/tlsr951x/pinctrl_soc.h b/soc/telink/tlsr/tlsr951x/pinctrl_soc.h similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/pinctrl_soc.h rename to soc/telink/tlsr/tlsr951x/pinctrl_soc.h diff --git a/soc/riscv/telink_tlsr/tlsr951x/soc.c b/soc/telink/tlsr/tlsr951x/soc.c similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/soc.c rename to soc/telink/tlsr/tlsr951x/soc.c diff --git a/soc/riscv/telink_tlsr/tlsr951x/soc.h b/soc/telink/tlsr/tlsr951x/soc.h similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/soc.h rename to soc/telink/tlsr/tlsr951x/soc.h diff --git a/soc/riscv/telink_tlsr/tlsr951x/soc_context.h b/soc/telink/tlsr/tlsr951x/soc_context.h similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/soc_context.h rename to soc/telink/tlsr/tlsr951x/soc_context.h diff --git a/soc/riscv/telink_tlsr/tlsr951x/soc_irq.S b/soc/telink/tlsr/tlsr951x/soc_irq.S similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/soc_irq.S rename to soc/telink/tlsr/tlsr951x/soc_irq.S diff --git a/soc/riscv/telink_tlsr/tlsr951x/soc_offsets.h b/soc/telink/tlsr/tlsr951x/soc_offsets.h similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/soc_offsets.h rename to soc/telink/tlsr/tlsr951x/soc_offsets.h diff --git a/soc/riscv/telink_tlsr/tlsr951x/start.S b/soc/telink/tlsr/tlsr951x/start.S similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/start.S rename to soc/telink/tlsr/tlsr951x/start.S diff --git a/soc/ti/k3/CMakeLists.txt b/soc/ti/k3/CMakeLists.txt new file mode 100644 index 00000000000..9d3cdd0d7af --- /dev/null +++ b/soc/ti/k3/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/ti/k3/Kconfig b/soc/ti/k3/Kconfig new file mode 100644 index 00000000000..4bc3bc6b2a9 --- /dev/null +++ b/soc/ti/k3/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_TI_K3 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_TI_K3 diff --git a/soc/ti/k3/Kconfig.defconfig b/soc/ti/k3/Kconfig.defconfig new file mode 100644 index 00000000000..2889e544ad0 --- /dev/null +++ b/soc/ti/k3/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_TI_K3 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_TI_K3 diff --git a/soc/ti/k3/Kconfig.soc b/soc/ti/k3/Kconfig.soc new file mode 100644 index 00000000000..d49a35ebfe8 --- /dev/null +++ b/soc/ti/k3/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_TI_K3 + bool + +config SOC_FAMILY + default "ti_k3" if SOC_FAMILY_TI_K3 + +rsource "*/Kconfig.soc" diff --git a/soc/ti/k3/am6x/CMakeLists.txt b/soc/ti/k3/am6x/CMakeLists.txt new file mode 100644 index 00000000000..9f0cb3dd2f5 --- /dev/null +++ b/soc/ti/k3/am6x/CMakeLists.txt @@ -0,0 +1,21 @@ +# Copyright (c) 2023 Enphase Energy +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +if(CONFIG_SOC_AM6234_A53) + zephyr_sources_ifdef(CONFIG_ARM_MMU a53/mmu_regions.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_AM6234_M4) + zephyr_sources(m4/soc.c) + + zephyr_include_directories(m4) + + if(CONFIG_OPENAMP_RSC_TABLE) + zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) + zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") + endif() + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/m4/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/ti/k3/am6x/Kconfig b/soc/ti/k3/am6x/Kconfig new file mode 100644 index 00000000000..8eb993db66f --- /dev/null +++ b/soc/ti/k3/am6x/Kconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2023 Enphase Energy +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AM6X_A53 + select ARM64 + select CPU_CORTEX_A53 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + +config SOC_SERIES_AM6X_M4 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_SYSTICK + select DYNAMIC_INTERRUPTS + select CPU_CORTEX_M_HAS_DWT + select OPENAMP_RSC_TABLE + select UART_NS16550_ACCESS_WORD_ONLY + select EXTERNAL_ADDRESS_TRANSLATION + select MM_DRV + select MM_TI_RAT + +config SOC_PART_NUMBER + default "AM6234" if SOC_AM6234_A53 + default "AM6234" if SOC_AM6234_M4 diff --git a/soc/ti/k3/am6x/Kconfig.defconfig b/soc/ti/k3/am6x/Kconfig.defconfig new file mode 100644 index 00000000000..f8a999baf50 --- /dev/null +++ b/soc/ti/k3/am6x/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Copyright (c) 2023 Enphase Energy +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_AM6X + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + int + default 64 if SOC_SERIES_AM6X_M4 + default 280 if SOC_SERIES_AM6X_A53 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 400000000 if SOC_SERIES_AM6X_M4 + default 200000000 if SOC_SERIES_AM6X_A53 + +config PINCTRL + default y + +if SERIAL + +config UART_NS16550 + default y + +config UART_NS16550_TI_K3 + default y if SOC_SERIES_AM6X_M4 + +choice UART_NS16550_VARIANT + default UART_NS16550_VARIANT_NS16750 +endchoice + +endif # SERIAL + +config BUILD_OUTPUT_BIN + default n if SOC_SERIES_AM6X_M4 + +endif # SOC_SERIES_AM6X diff --git a/soc/ti/k3/am6x/Kconfig.soc b/soc/ti/k3/am6x/Kconfig.soc new file mode 100644 index 00000000000..fa9c8e20f7e --- /dev/null +++ b/soc/ti/k3/am6x/Kconfig.soc @@ -0,0 +1,32 @@ +# Copyright (c) 2023 Enphase Energy +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AM6X + bool + select SOC_FAMILY_TI_K3 + +config SOC_SERIES_AM6X_A53 + bool + select SOC_SERIES_AM6X + help + Enable support for AM6X A53 Series. + +config SOC_SERIES_AM6X_M4 + bool + select SOC_SERIES_AM6X + help + Enable support for AM62X M4 Series. + +config SOC_AM6234_A53 + bool + select SOC_SERIES_AM6X_A53 + +config SOC_AM6234_M4 + bool + select SOC_SERIES_AM6X_M4 + +config SOC_SERIES + default "am6x" if SOC_SERIES_AM6X + +config SOC + default "am6234" if SOC_AM6234_M4 || SOC_AM6234_A53 diff --git a/soc/arm64/ti_k3/am6x/mmu_regions.c b/soc/ti/k3/am6x/a53/mmu_regions.c similarity index 100% rename from soc/arm64/ti_k3/am6x/mmu_regions.c rename to soc/ti/k3/am6x/a53/mmu_regions.c diff --git a/soc/arm/ti_k3/am62x_m4/linker.ld b/soc/ti/k3/am6x/m4/linker.ld similarity index 100% rename from soc/arm/ti_k3/am62x_m4/linker.ld rename to soc/ti/k3/am6x/m4/linker.ld diff --git a/soc/arm/ti_k3/am62x_m4/soc.c b/soc/ti/k3/am6x/m4/soc.c similarity index 100% rename from soc/arm/ti_k3/am62x_m4/soc.c rename to soc/ti/k3/am6x/m4/soc.c diff --git a/soc/arm/ti_k3/am62x_m4/soc.h b/soc/ti/k3/am6x/m4/soc.h similarity index 100% rename from soc/arm/ti_k3/am62x_m4/soc.h rename to soc/ti/k3/am6x/m4/soc.h diff --git a/soc/arm64/ti_k3/pinctrl_soc.h b/soc/ti/k3/am6x/pinctrl_soc.h similarity index 100% rename from soc/arm64/ti_k3/pinctrl_soc.h rename to soc/ti/k3/am6x/pinctrl_soc.h diff --git a/soc/ti/k3/soc.yml b/soc/ti/k3/soc.yml new file mode 100644 index 00000000000..92ae28d5a0a --- /dev/null +++ b/soc/ti/k3/soc.yml @@ -0,0 +1,9 @@ +family: +- name: ti_k3 + series: + - name: am6x + socs: + - name: am6234 + cpuclusters: + - name: m4 + - name: a53 diff --git a/soc/ti/lm3s6965/CMakeLists.txt b/soc/ti/lm3s6965/CMakeLists.txt new file mode 100644 index 00000000000..b490726e507 --- /dev/null +++ b/soc/ti/lm3s6965/CMakeLists.txt @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources( + soc_config.c + reboot.S + sys_arch_reboot.c + ) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/arm/include + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/lm3s6965/Kconfig b/soc/ti/lm3s6965/Kconfig new file mode 100644 index 00000000000..16a9c5c083f --- /dev/null +++ b/soc/ti/lm3s6965/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_TI_LM3S6965 + select ARM + select CPU_CORTEX_M3 + select CPU_CORTEX_M_HAS_DWT diff --git a/soc/ti/lm3s6965/Kconfig.defconfig b/soc/ti/lm3s6965/Kconfig.defconfig new file mode 100644 index 00000000000..097a4969c37 --- /dev/null +++ b/soc/ti/lm3s6965/Kconfig.defconfig @@ -0,0 +1,29 @@ +# TI LM3S6965 platform configuration options + +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_TI_LM3S6965 + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts and ethernet interrupts + default 43 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 12000000 + +if UART_STELLARIS + +config UART_STELLARIS_PORT_0 + default y + +config UART_STELLARIS_PORT_1 + default y + +config UART_STELLARIS_PORT_2 + default y + +endif # UART_STELLARIS + +endif diff --git a/soc/ti/lm3s6965/Kconfig.soc b/soc/ti/lm3s6965/Kconfig.soc new file mode 100644 index 00000000000..dc1da3fa35b --- /dev/null +++ b/soc/ti/lm3s6965/Kconfig.soc @@ -0,0 +1,16 @@ +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_TI_LM3S6965 + bool + help + TI LM3S6965 + +config SOC_TI_LM3S6965_QEMU + def_bool y + depends on SOC_TI_LM3S6965 + # Platform has only been tested on QEMU, not on real hardware, so always + # assume it is used for a QEMU target. + +config SOC + default "ti_lm3s6965" if SOC_TI_LM3S6965 diff --git a/soc/arm/ti_lm3s6965/reboot.S b/soc/ti/lm3s6965/reboot.S similarity index 100% rename from soc/arm/ti_lm3s6965/reboot.S rename to soc/ti/lm3s6965/reboot.S diff --git a/soc/arm/ti_lm3s6965/soc.h b/soc/ti/lm3s6965/soc.h similarity index 100% rename from soc/arm/ti_lm3s6965/soc.h rename to soc/ti/lm3s6965/soc.h diff --git a/soc/ti/lm3s6965/soc.yml b/soc/ti/lm3s6965/soc.yml new file mode 100644 index 00000000000..6f80cd356af --- /dev/null +++ b/soc/ti/lm3s6965/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: ti_lm3s6965 diff --git a/soc/arm/ti_lm3s6965/soc_config.c b/soc/ti/lm3s6965/soc_config.c similarity index 100% rename from soc/arm/ti_lm3s6965/soc_config.c rename to soc/ti/lm3s6965/soc_config.c diff --git a/soc/arm/ti_lm3s6965/sys_arch_reboot.c b/soc/ti/lm3s6965/sys_arch_reboot.c similarity index 100% rename from soc/arm/ti_lm3s6965/sys_arch_reboot.c rename to soc/ti/lm3s6965/sys_arch_reboot.c diff --git a/soc/ti/simplelink/CMakeLists.txt b/soc/ti/simplelink/CMakeLists.txt new file mode 100644 index 00000000000..c9df1f11486 --- /dev/null +++ b/soc/ti/simplelink/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Zephyr Contributors + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/ti/simplelink/Kconfig b/soc/ti/simplelink/Kconfig new file mode 100644 index 00000000000..af4cd5f7433 --- /dev/null +++ b/soc/ti/simplelink/Kconfig @@ -0,0 +1,15 @@ +# Texas Instruments SimpleLink Family +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Zephyr Contributors + +if SOC_FAMILY_TI_SIMPLELINK + +rsource "*/Kconfig" + +config HAS_TI_CCFG + bool + help + Selected when CCFG (Customer Configuration) registers + appear at the end of flash + +endif # SOC_FAMILY_TI_SIMPLELINK diff --git a/soc/ti/simplelink/Kconfig.defconfig b/soc/ti/simplelink/Kconfig.defconfig new file mode 100644 index 00000000000..0051bdd7801 --- /dev/null +++ b/soc/ti/simplelink/Kconfig.defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Zephyr Contributors + +if SOC_FAMILY_TI_SIMPLELINK + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_TI_SIMPLELINK diff --git a/soc/ti/simplelink/Kconfig.soc b/soc/ti/simplelink/Kconfig.soc new file mode 100644 index 00000000000..d1f3a505e21 --- /dev/null +++ b/soc/ti/simplelink/Kconfig.soc @@ -0,0 +1,11 @@ +# Texas Instruments SimpleLink Family +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Zephyr Contributors + +config SOC_FAMILY_TI_SIMPLELINK + bool + +config SOC_FAMILY + default "ti_simplelink" if SOC_FAMILY_TI_SIMPLELINK + +rsource "*/Kconfig.soc" diff --git a/soc/ti/simplelink/cc13x2_cc26x2/CMakeLists.txt b/soc/ti/simplelink/cc13x2_cc26x2/CMakeLists.txt new file mode 100644 index 00000000000..5da2629b5c0 --- /dev/null +++ b/soc/ti/simplelink/cc13x2_cc26x2/CMakeLists.txt @@ -0,0 +1,16 @@ +# Copyright (c) 2019 Brett Witherspoon +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) +zephyr_sources(ccfg.c) +zephyr_include_directories(.) + +if(CONFIG_PM OR CONFIG_PM_DEVICE OR CONFIG_POWEROFF) + zephyr_library_sources(power.c) +endif() +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_linker_sources_ifdef(CONFIG_HAS_TI_CCFG SECTIONS ccfg.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/simplelink/cc13x2_cc26x2/Kconfig b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig new file mode 100644 index 00000000000..056e6162523 --- /dev/null +++ b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig @@ -0,0 +1,62 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 +# Copyright (c) 2019 Brett Witherspoon +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CC13X2_CC26X2 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select DYNAMIC_INTERRUPTS + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_CC13X2_CC26X2_SDK + select HAS_TI_CCFG if !BOOTLOADER_MCUBOOT + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_PM + select HAS_POWEROFF + +menu "Customer Configuration (CCFG)" +depends on SOC_SERIES_CC13X2_CC26X2 + +config CC13X2_CC26X2_BOOST_MODE + bool "Radio boost mode (VDDR_HH)" + help + Enable the radio boost mode +14dBm (sets CCFG_FORCE_VDDR_HH to 1). + +config CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS + bool "Board defines custom RFCC26XX hwAttrs structure" + help + The board defines its own RFCC26XX_hwAttrs structure (e.g., for + custom antenna switching callback). + +config CC13X2_CC26X2_BOOTLOADER_ENABLE + bool "ROM bootloader" + help + Enable the serial bootloader which resides in ROM on CC13xx / CC26xx + devices. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + bool "ROM bootloader backdoor" + depends on CC13X2_CC26X2_BOOTLOADER_ENABLE + help + Enable the ROM bootloader backdoor which starts the bootloader if the + associated pin is at the correct logic level on reset. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN + int "ROM bootloader backdoor pin" + depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + range 0 255 + default 255 + help + Set the pin that is level checked if the bootloader backdoor is + enabled. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_LEVEL + int "ROM bootloader backdoor level" + depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + range 0 1 + default 0 + help + Set the active level of the pin selected for the bootloader backdoor. + +endmenu diff --git a/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.defconfig b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.defconfig new file mode 100644 index 00000000000..fa1d5d9b6dc --- /dev/null +++ b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.defconfig @@ -0,0 +1,41 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 +# Copyright (c) 2019 Brett Witherspoon +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CC13X2_CC26X2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +# Note that when using the RTC as system clock, this needs to be 32768 +# to reduce truncation errors from accumulating due to conversion to/from +# time, ticks, and HW cycles +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +config NUM_IRQS + default 38 + +if IEEE802154 + +config IEEE802154_CC13XX_CC26XX + # required for linking with PowerCC26X2_config in + # soc/soc_legacy/arm/ti_simplelink/cc13x2_cc26x2/power.c + select PM + +config IEEE802154_CC13XX_CC26XX_SUB_GHZ + # required for linking with PowerCC26X2_config in + # soc/soc_legacy/arm/ti_simplelink/cc13x2_cc26x2/power.c + select PM + +endif # IEEE802154 + +if BT + +config BLE_CC13XX_CC26XX + bool + default y + +endif # BT + +endif # SOC_SERIES_CC13X2_CC26X2 diff --git a/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.soc b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.soc new file mode 100644 index 00000000000..0642c518ec7 --- /dev/null +++ b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.soc @@ -0,0 +1,43 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 + +# Copyright (c) 2019 Brett Witherspoon +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CC13X2_CC26X2 + bool + select SOC_FAMILY_TI_SIMPLELINK + help + Enable support for TI SimpleLink CC13x2 / CC26x2 SoCs + +config SOC_CC1352P + bool + select SOC_SERIES_CC13X2_CC26X2 + help + CC1352P + +config SOC_CC1352R + bool + select SOC_SERIES_CC13X2_CC26X2 + help + CC1352R + +config SOC_CC2652P + bool + select SOC_SERIES_CC13X2_CC26X2 + help + CC2652P + +config SOC_CC2652R + bool + select SOC_SERIES_CC13X2_CC26X2 + help + CC2652R + +config SOC_SERIES + default "cc13x2_cc26x2" if SOC_SERIES_CC13X2_CC26X2 + +config SOC + default "cc1352p" if SOC_CC1352P + default "cc1352r" if SOC_CC1352R + default "cc2652p" if SOC_CC2652P + default "cc2652r" if SOC_CC2652R diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.c b/soc/ti/simplelink/cc13x2_cc26x2/ccfg.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.c rename to soc/ti/simplelink/cc13x2_cc26x2/ccfg.c diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.ld b/soc/ti/simplelink/cc13x2_cc26x2/ccfg.ld similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.ld rename to soc/ti/simplelink/cc13x2_cc26x2/ccfg.ld diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/pinctrl_soc.h b/soc/ti/simplelink/cc13x2_cc26x2/pinctrl_soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/pinctrl_soc.h rename to soc/ti/simplelink/cc13x2_cc26x2/pinctrl_soc.h diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/power.c b/soc/ti/simplelink/cc13x2_cc26x2/power.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/power.c rename to soc/ti/simplelink/cc13x2_cc26x2/power.c diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/poweroff.c b/soc/ti/simplelink/cc13x2_cc26x2/poweroff.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/poweroff.c rename to soc/ti/simplelink/cc13x2_cc26x2/poweroff.c diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/soc.c b/soc/ti/simplelink/cc13x2_cc26x2/soc.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/soc.c rename to soc/ti/simplelink/cc13x2_cc26x2/soc.c diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/soc.h b/soc/ti/simplelink/cc13x2_cc26x2/soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/soc.h rename to soc/ti/simplelink/cc13x2_cc26x2/soc.h diff --git a/soc/ti/simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt b/soc/ti/simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt new file mode 100644 index 00000000000..634e6995f53 --- /dev/null +++ b/soc/ti/simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2022 Vaishnav Achath +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) +zephyr_sources(ccfg.c) + +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_PM power.c) +zephyr_library_sources_ifdef(CONFIG_PM_DEVICE power.c) + +zephyr_linker_sources_ifdef(CONFIG_HAS_TI_CCFG SECTIONS ccfg.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig new file mode 100644 index 00000000000..42789af2526 --- /dev/null +++ b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig @@ -0,0 +1,69 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 +# Copyright (c) 2022 Vaishnav Achath +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CC13X2X7_CC26X2X7 + bool + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select DYNAMIC_INTERRUPTS + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_CC13X2X7_CC26X2X7_SDK + select HAS_TI_CCFG if !BOOTLOADER_MCUBOOT + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_PM + +menu "Customer Configuration (CCFG)" +depends on SOC_SERIES_CC13X2X7_CC26X2X7 + +config CC13X2_CC26X2_BOOST_MODE + bool "Radio boost mode (VDDR_HH)" + help + Enable the radio boost mode +14dBm (sets CCFG_FORCE_VDDR_HH to 1). + +config CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS + bool "Board defines custom RFCC26XX hwAttrs structure" + help + The board defines its own RFCC26XX_hwAttrs structure (e.g., for + custom antenna switching callback). + +config CC13X2_CC26X2_BOOTLOADER_ENABLE + bool "ROM bootloader" + help + Enable the serial bootloader which resides in ROM on CC13xx / CC26xx + devices. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + bool "ROM bootloader backdoor" + depends on CC13X2_CC26X2_BOOTLOADER_ENABLE + help + Enable the ROM bootloader backdoor which starts the bootloader if the + associated pin is at the correct logic level on reset. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN + int "ROM bootloader backdoor pin" + depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + range 0 255 + default 255 + help + Set the pin that is level checked if the bootloader backdoor is + enabled. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_LEVEL + int "ROM bootloader backdoor level" + depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + range 0 1 + default 0 + help + Set the active level of the pin selected for the bootloader backdoor. + +config CC13X2_CC26X2_XOSC_CAPARRAY_DELTA + hex "Cap array tuning delta" + range 0 0xFF + default 0xD5 + help + Enable a specific cap array tunning delta. + +endmenu diff --git a/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig new file mode 100644 index 00000000000..c453227ad4c --- /dev/null +++ b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig @@ -0,0 +1,41 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 +# Copyright (c) 2022 Vaishnav Achath +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CC13X2X7_CC26X2X7 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +# Note that when using the RTC as system clock, this needs to be 32768 +# to reduce truncation errors from accumulating due to conversion to/from +# time, ticks, and HW cycles +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +config NUM_IRQS + default 38 + +if IEEE802154 + +config IEEE802154_CC13XX_CC26XX + # required for linking with PowerCC26X2_config in + # soc/soc_legacy/arm/ti_simplelink/cc13x2_cc26x2/power.c + select PM + +config IEEE802154_CC13XX_CC26XX_SUB_GHZ + # required for linking with PowerCC26X2_config in + # soc/soc_legacy/arm/ti_simplelink/cc13x2_cc26x2/power.c + select PM + +endif # IEEE802154 + +if BT + +config BLE_CC13XX_CC26XX + bool + default y + +endif # BT + +endif # SOC_SERIES_CC13X2X7_CC26X2X7 diff --git a/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.soc b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.soc new file mode 100644 index 00000000000..8ab5dc1ea6e --- /dev/null +++ b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.soc @@ -0,0 +1,42 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 +# Copyright (c) 2022 Vaishnav Achath +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CC13X2X7_CC26X2X7 + bool + select SOC_FAMILY_TI_SIMPLELINK + help + Enable support for TI SimpleLink CC13x2x7 / CC26x2x7 SoCs + +config SOC_CC1352P7 + bool + select SOC_SERIES_CC13X2X7_CC26X2X7 + help + CC1352P7 + +config SOC_CC1352R7 + bool + select SOC_SERIES_CC13X2X7_CC26X2X7 + help + CC1352R7 + +config SOC_CC2652P7 + bool + select SOC_SERIES_CC13X2X7_CC26X2X7 + help + CC2652P7 + +config SOC_CC2652R7 + bool + select SOC_SERIES_CC13X2X7_CC26X2X7 + help + CC2652R7 + +config SOC_SERIES + default "cc13x2x7_cc26x2x7" if SOC_SERIES_CC13X2X7_CC26X2X7 + +config SOC + default "cc1352p7" if SOC_CC1352P7 + default "cc1352r7" if SOC_CC1352R7 + default "cc2652p7" if SOC_CC2652P7 + default "cc2652r7" if SOC_CC2652R7 diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.c b/soc/ti/simplelink/cc13x2x7_cc26x2x7/ccfg.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.c rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/ccfg.c diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.ld b/soc/ti/simplelink/cc13x2x7_cc26x2x7/ccfg.ld similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.ld rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/ccfg.ld diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h b/soc/ti/simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/power.c b/soc/ti/simplelink/cc13x2x7_cc26x2x7/power.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/power.c rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/power.c diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.c b/soc/ti/simplelink/cc13x2x7_cc26x2x7/soc.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.c rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/soc.c diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.h b/soc/ti/simplelink/cc13x2x7_cc26x2x7/soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.h rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/soc.h diff --git a/soc/ti/simplelink/cc32xx/CMakeLists.txt b/soc/ti/simplelink/cc32xx/CMakeLists.txt new file mode 100644 index 00000000000..4142f958e05 --- /dev/null +++ b/soc/ti/simplelink/cc32xx/CMakeLists.txt @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2016-2017, Texas Instruments Incorporated + +zephyr_sources(soc.c) +zephyr_include_directories(.) + +if(DEFINED CONFIG_CC3220SF_DEBUG OR DEFINED CONFIG_CC3235SF_DEBUG) + zephyr_linker_sources(ROM_START SORT_KEY 0 cc32xx_debug.ld) +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/simplelink/cc32xx/Kconfig b/soc/ti/simplelink/cc32xx/Kconfig new file mode 100644 index 00000000000..d8ec2f20715 --- /dev/null +++ b/soc/ti/simplelink/cc32xx/Kconfig @@ -0,0 +1,25 @@ +# Texas Instruments CC32XX +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2016-2017, Texas Instruments Incorporated + +config SOC_SERIES_CC32XX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select DYNAMIC_INTERRUPTS + +config SOC_CC3220SF + select HAS_CC3220SDK + +config SOC_CC3235SF + select HAS_CC3220SDK + +config CC3220SF_DEBUG + bool "Prepend debug header, disabling flash verification" if XIP + default XIP + depends on SOC_CC3220SF + +config CC3235SF_DEBUG + bool "Prepend debug header, disabling flash verification" if XIP + default XIP + depends on SOC_CC3235SF diff --git a/soc/ti/simplelink/cc32xx/Kconfig.defconfig b/soc/ti/simplelink/cc32xx/Kconfig.defconfig new file mode 100644 index 00000000000..f782322c9cc --- /dev/null +++ b/soc/ti/simplelink/cc32xx/Kconfig.defconfig @@ -0,0 +1,9 @@ +# TI SimpleLink Family +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2016-2017, Texas Instruments Incorporated + +if SOC_SERIES_CC32XX + +rsource "Kconfig.defconfig.cc32*" + +endif # SOC_SERIES_CC32XX diff --git a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf b/soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3220sf similarity index 88% rename from soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf rename to soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3220sf index 461802f2155..ac26dbe66f7 100644 --- a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf +++ b/soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3220sf @@ -1,12 +1,9 @@ # TI SimpleLink CC3220SF SoC - # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2016-2017, Texas Instruments Incorporated if SOC_CC3220SF -config SOC - default "cc3220sf" - config NUM_IRQS # must be >= the highest interrupt number used # This includes the NWP interrupt @@ -20,10 +17,12 @@ config ROM_START_OFFSET default 0x0 if !XIP if !XIP + config FLASH_SIZE default 0 config FLASH_BASE_ADDRESS default 0 + endif endif # SOC_CC3220SF diff --git a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3235sf b/soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3235sf similarity index 93% rename from soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3235sf rename to soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3235sf index 37852a154a0..9da363f006c 100644 --- a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3235sf +++ b/soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3235sf @@ -1,13 +1,9 @@ # TI SimpleLink CC3235SF SoC - # Copyright (c) 2019, Texas Instruments Incorporated # SPDX-License-Identifier: Apache-2.0 if SOC_CC3235SF -config SOC - default "cc3235sf" - config NUM_IRQS # must be >= the highest interrupt number used # This includes the NWP interrupt @@ -21,10 +17,12 @@ config ROM_START_OFFSET default 0x0 if !XIP if !XIP + config FLASH_SIZE default 0 config FLASH_BASE_ADDRESS default 0 + endif endif # SOC_CC3235SF diff --git a/soc/ti/simplelink/cc32xx/Kconfig.soc b/soc/ti/simplelink/cc32xx/Kconfig.soc new file mode 100644 index 00000000000..44cd0123b94 --- /dev/null +++ b/soc/ti/simplelink/cc32xx/Kconfig.soc @@ -0,0 +1,28 @@ +# TI SimpleLink CC32xx +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2016-2017, Texas Instruments Incorporated + +config SOC_SERIES_CC32XX + bool + select SOC_FAMILY_TI_SIMPLELINK + help + Enable support for TI SimpleLink CC32xx + +config SOC_CC3220SF + bool + select SOC_SERIES_CC32XX + help + CC3220SF + +config SOC_CC3235SF + bool + select SOC_SERIES_CC32XX + help + CC3235SF + +config SOC_SERIES + default "cc32xx" if SOC_SERIES_CC32XX + +config SOC + default "cc3220sf" if SOC_CC3220SF + default "cc3235sf" if SOC_CC3235SF diff --git a/soc/arm/ti_simplelink/cc32xx/README b/soc/ti/simplelink/cc32xx/README similarity index 100% rename from soc/arm/ti_simplelink/cc32xx/README rename to soc/ti/simplelink/cc32xx/README diff --git a/soc/arm/ti_simplelink/cc32xx/cc32xx_debug.ld b/soc/ti/simplelink/cc32xx/cc32xx_debug.ld similarity index 100% rename from soc/arm/ti_simplelink/cc32xx/cc32xx_debug.ld rename to soc/ti/simplelink/cc32xx/cc32xx_debug.ld diff --git a/soc/arm/ti_simplelink/cc32xx/pinctrl_soc.h b/soc/ti/simplelink/cc32xx/pinctrl_soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc32xx/pinctrl_soc.h rename to soc/ti/simplelink/cc32xx/pinctrl_soc.h diff --git a/soc/arm/ti_simplelink/cc32xx/soc.c b/soc/ti/simplelink/cc32xx/soc.c similarity index 100% rename from soc/arm/ti_simplelink/cc32xx/soc.c rename to soc/ti/simplelink/cc32xx/soc.c diff --git a/soc/arm/ti_simplelink/cc32xx/soc.h b/soc/ti/simplelink/cc32xx/soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc32xx/soc.h rename to soc/ti/simplelink/cc32xx/soc.h diff --git a/soc/ti/simplelink/msp432p4xx/CMakeLists.txt b/soc/ti/simplelink/msp432p4xx/CMakeLists.txt new file mode 100644 index 00000000000..537a7cb4287 --- /dev/null +++ b/soc/ti/simplelink/msp432p4xx/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_compile_definitions(-D__MSP432P401R__) +zephyr_sources(soc.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/simplelink/msp432p4xx/Kconfig b/soc/ti/simplelink/msp432p4xx/Kconfig new file mode 100644 index 00000000000..9b44c5f34ab --- /dev/null +++ b/soc/ti/simplelink/msp432p4xx/Kconfig @@ -0,0 +1,14 @@ +# Texas Instruments MSP432P401R +# Copyright (c) 2017, Linaro Ltd +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MSP432P4XX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select DYNAMIC_INTERRUPTS + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + +config SOC_MSP432P401R + select HAS_MSP432P4XXSDK diff --git a/soc/ti/simplelink/msp432p4xx/Kconfig.defconfig b/soc/ti/simplelink/msp432p4xx/Kconfig.defconfig new file mode 100644 index 00000000000..449e9fd020b --- /dev/null +++ b/soc/ti/simplelink/msp432p4xx/Kconfig.defconfig @@ -0,0 +1,9 @@ +# TI SimpleLink MSP432P4XX +# Copyright (c) 2017, Linaro Ltd +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MSP432P4XX + +rsource "Kconfig.defconfig.msp432p4*" + +endif # SOC_SERIES_MSP432P4XX diff --git a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r b/soc/ti/simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r similarity index 86% rename from soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r rename to soc/ti/simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r index af491c6b8ad..3c984147a6d 100644 --- a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r +++ b/soc/ti/simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r @@ -1,13 +1,9 @@ # TI SimpleLink MSP432P401R SoC - # Copyright (c) 2017, Linaro Ltd # SPDX-License-Identifier: Apache-2.0 if SOC_MSP432P401R -config SOC - default "msp432p401r" - config SYS_CLOCK_HW_CYCLES_PER_SEC default 48000000 diff --git a/soc/ti/simplelink/msp432p4xx/Kconfig.soc b/soc/ti/simplelink/msp432p4xx/Kconfig.soc new file mode 100644 index 00000000000..aca5e6b425a --- /dev/null +++ b/soc/ti/simplelink/msp432p4xx/Kconfig.soc @@ -0,0 +1,21 @@ +# Texas Instruments MSP432P401R +# Copyright (c) 2017, Linaro Ltd +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MSP432P4XX + bool + select SOC_FAMILY_TI_SIMPLELINK + help + Enable support for TI SimpleLink MSP432P4XX. + +config SOC_MSP432P401R + bool + select SOC_SERIES_MSP432P4XX + help + MSP432P401R + +config SOC_SERIES + default "msp432p4xx" if SOC_SERIES_MSP432P4XX + +config SOC + default "msp432p401r" if SOC_MSP432P401R diff --git a/soc/arm/ti_simplelink/msp432p4xx/soc.c b/soc/ti/simplelink/msp432p4xx/soc.c similarity index 100% rename from soc/arm/ti_simplelink/msp432p4xx/soc.c rename to soc/ti/simplelink/msp432p4xx/soc.c diff --git a/soc/arm/ti_simplelink/msp432p4xx/soc.h b/soc/ti/simplelink/msp432p4xx/soc.h similarity index 100% rename from soc/arm/ti_simplelink/msp432p4xx/soc.h rename to soc/ti/simplelink/msp432p4xx/soc.h diff --git a/soc/ti/simplelink/soc.yml b/soc/ti/simplelink/soc.yml new file mode 100644 index 00000000000..2dbf91f315e --- /dev/null +++ b/soc/ti/simplelink/soc.yml @@ -0,0 +1,22 @@ +family: +- name: ti_simplelink + series: + - name: cc13x2_cc26x2 + socs: + - name: cc1352p + - name: cc1352r + - name: cc2652p + - name: cc2652r + - name: cc13x2x7_cc26x2x7 + socs: + - name: cc1352p7 + - name: cc1352r7 + - name: cc2652p7 + - name: cc2652r7 + - name: cc32xx + socs: + - name: cc3220sf + - name: cc3235sf + - name: msp432p4xx + socs: + - name: msp432p401r diff --git a/soc/x86/alder_lake/CMakeLists.txt b/soc/x86/alder_lake/CMakeLists.txt deleted file mode 100644 index 47325b7a809..00000000000 --- a/soc/x86/alder_lake/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_cc_option(-march=goldmont) - -zephyr_library_sources(cpu.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/alder_lake/Kconfig.defconfig b/soc/x86/alder_lake/Kconfig.defconfig deleted file mode 100644 index c2cd55fc85a..00000000000 --- a/soc/x86/alder_lake/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Alder Lake SoC configuration options - -# Copyright (c) 2018-2023 Intel Corporation -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ALDER_LAKE - -config SOC - default "alder_lake" - -config PCIE_MMIO_CFG - default y - -config X86_DYNAMIC_IRQ_STUBS - default 16 - depends on DYNAMIC_INTERRUPTS - -endif # SOC_ALDER_LAKE diff --git a/soc/x86/alder_lake/Kconfig.soc b/soc/x86/alder_lake/Kconfig.soc deleted file mode 100644 index 1f046e0b92d..00000000000 --- a/soc/x86/alder_lake/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2018-2023 Intel Corporation Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ALDER_LAKE - bool "Intel Alder Lake SOC" - select X86 - select CPU_ATOM - select PCIE - select PCIE_MSI - select DYNAMIC_INTERRUPTS - select X86_MMU diff --git a/soc/x86/apollo_lake/CMakeLists.txt b/soc/x86/apollo_lake/CMakeLists.txt deleted file mode 100644 index 47325b7a809..00000000000 --- a/soc/x86/apollo_lake/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_cc_option(-march=goldmont) - -zephyr_library_sources(cpu.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/apollo_lake/Kconfig.defconfig b/soc/x86/apollo_lake/Kconfig.defconfig deleted file mode 100644 index a865865b1dd..00000000000 --- a/soc/x86/apollo_lake/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# Apollo Lake SoC configuration options - -# Copyright (c) 2018-2019 Intel Corporation -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_APOLLO_LAKE - -config SOC - default "apollo_lake" - -config PCIE_MMIO_CFG - default y - -if APIC_TIMER - -config APIC_TIMER_IRQ - default 24 - -config APIC_TIMER_TSC - default y - -endif # APIC_TIMER - -config X86_DYNAMIC_IRQ_STUBS - default 16 - depends on DYNAMIC_INTERRUPTS - -endif # SOC_APOLLO_LAKE diff --git a/soc/x86/apollo_lake/Kconfig.soc b/soc/x86/apollo_lake/Kconfig.soc deleted file mode 100644 index 6eae75b8c5e..00000000000 --- a/soc/x86/apollo_lake/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2018 Intel Corporation Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_APOLLO_LAKE - bool "Intel Apollo Lake Soc" - select X86 - select CPU_APOLLO_LAKE - select PCIE - select PCIE_MSI - select DYNAMIC_INTERRUPTS - select X86_MMU - select ARCH_HAS_RESERVED_PAGE_FRAMES diff --git a/soc/x86/atom/CMakeLists.txt b/soc/x86/atom/CMakeLists.txt deleted file mode 100644 index 66d55c6ba96..00000000000 --- a/soc/x86/atom/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/atom/Kconfig.defconfig b/soc/x86/atom/Kconfig.defconfig deleted file mode 100644 index 743b43465f4..00000000000 --- a/soc/x86/atom/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# ATOM SoC configuration options - -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ATOM - -config SOC - default "atom" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 25000000 if HPET_TIMER - -endif diff --git a/soc/x86/atom/Kconfig.soc b/soc/x86/atom/Kconfig.soc deleted file mode 100644 index ac396eec880..00000000000 --- a/soc/x86/atom/Kconfig.soc +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ATOM - bool "Intel ATOM SoC" - select X86 - select CPU_ATOM - select X86_MMU - select ARCH_HAS_USERSPACE - select ARCH_HAS_RESERVED_PAGE_FRAMES diff --git a/soc/x86/atom/soc.h b/soc/x86/atom/soc.h deleted file mode 100644 index 199820fa7bd..00000000000 --- a/soc/x86/atom/soc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2010-2015, Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Board configuration macros for the ia32 platform - * - * This header file is used to specify and describe board-level aspects for - * the 'ia32' platform. - */ - -#ifndef __SOC_H_ -#define __SOC_H_ - -#include - -#ifndef _ASMLANGUAGE -#include -#include -#endif - -/* PCI definitions */ -/* FIXME: The values below copied from generic ia32 soc, we need to get the - * correct numbers for Atom and the minnowboard - * - * This is added now to get basic enumeration of devices and verify that PCI - * driver is functional. - */ -#define PCI_BUS_NUMBERS 1 - -#define PCI_CTRL_ADDR_REG 0xCF8 -#define PCI_CTRL_DATA_REG 0xCFC - -#define PCI_INTA 1 -#define PCI_INTB 2 -#define PCI_INTC 3 -#define PCI_INTD 4 - -/** - * - * @brief Convert PCI interrupt PIN to IRQ - * - * @return IRQ number, -1 if the result is incorrect - * - */ - -static inline int pci_pin2irq(int bus, int dev, int pin) -{ - ARG_UNUSED(bus); - - if ((pin < PCI_INTA) || (pin > PCI_INTD)) { - return -1; - } - return 10 + (((pin + dev - 1) >> 1) & 1); -} - -#endif /* __SOC_H_ */ diff --git a/soc/x86/elkhart_lake/CMakeLists.txt b/soc/x86/elkhart_lake/CMakeLists.txt deleted file mode 100644 index 47325b7a809..00000000000 --- a/soc/x86/elkhart_lake/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_cc_option(-march=goldmont) - -zephyr_library_sources(cpu.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/elkhart_lake/Kconfig.defconfig b/soc/x86/elkhart_lake/Kconfig.defconfig deleted file mode 100644 index ba983ea7eb7..00000000000 --- a/soc/x86/elkhart_lake/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Elkhart Lake SoC configuration options - -# Copyright (c) 2018-2020 Intel Corporation -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ELKHART_LAKE - -config SOC - default "elkhart_lake" - -config PCIE_MMIO_CFG - default y - -config X86_DYNAMIC_IRQ_STUBS - default 16 - depends on DYNAMIC_INTERRUPTS - -endif # SOC_ELKHART_LAKE diff --git a/soc/x86/elkhart_lake/Kconfig.soc b/soc/x86/elkhart_lake/Kconfig.soc deleted file mode 100644 index 26c11392388..00000000000 --- a/soc/x86/elkhart_lake/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2018-2020 Intel Corporation Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ELKHART_LAKE - bool "Intel Elkhart Lake Soc" - select X86 - select CPU_ATOM - select PCIE - select PCIE_MSI - select DYNAMIC_INTERRUPTS - select X86_MMU diff --git a/soc/x86/ia32/CMakeLists.txt b/soc/x86/ia32/CMakeLists.txt deleted file mode 100644 index 66d55c6ba96..00000000000 --- a/soc/x86/ia32/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/ia32/Kconfig.defconfig b/soc/x86/ia32/Kconfig.defconfig deleted file mode 100644 index 87600183a20..00000000000 --- a/soc/x86/ia32/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Generic PC platform configuration options - -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_IA32 - -config SOC - default "ia32" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 25000000 if HPET_TIMER - -endif diff --git a/soc/x86/ia32/Kconfig.soc b/soc/x86/ia32/Kconfig.soc deleted file mode 100644 index d2731afdba3..00000000000 --- a/soc/x86/ia32/Kconfig.soc +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_IA32 - bool "Generic IA32 SoC" - select X86 - select CPU_ATOM - select X86_CPU_HAS_MMX - select X86_CPU_HAS_SSE - select ARCH_HAS_RESERVED_PAGE_FRAMES if SRAM_BASE_ADDRESS = 0 diff --git a/soc/x86/ia32/soc.h b/soc/x86/ia32/soc.h deleted file mode 100644 index 51da1d1cdf4..00000000000 --- a/soc/x86/ia32/soc.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2010-2015, Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Board configuration macros for the ia32 platform - * - * This header file is used to specify and describe board-level aspects for - * the 'ia32' platform. - */ - -#ifndef __SOC_H_ -#define __SOC_H_ - -#include - -#ifndef _ASMLANGUAGE -#include -#include -#endif - -/* PCI definitions */ -#define PCI_BUS_NUMBERS 1 - -#define PCI_CTRL_ADDR_REG 0xCF8 -#define PCI_CTRL_DATA_REG 0xCFC - -#define PCI_INTA 1 -#define PCI_INTB 2 -#define PCI_INTC 3 -#define PCI_INTD 4 - -/** - * - * @brief Convert PCI interrupt PIN to IRQ - * - * This file is only used by QEMU, which emulates the i440fx chipset. - * INTx are mapped to IRQs 10 and 11 after being swizzled. - * - * @return IRQ number, -1 if the result is incorrect - * - */ - -static inline int pci_pin2irq(int bus, int dev, int pin) -{ - ARG_UNUSED(bus); - - if ((pin < PCI_INTA) || (pin > PCI_INTD)) { - return -1; - } - - return 10 + (((pin + dev - 1) >> 1) & 1); -} - -#endif /* __SOC_H_ */ diff --git a/soc/x86/intel_ish/Kconfig b/soc/x86/intel_ish/Kconfig deleted file mode 100644 index b3865915a2a..00000000000 --- a/soc/x86/intel_ish/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Intel ISH family configuration options -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_INTEL_ISH - bool "Intel ISH SoC family" - select X86 - select X86_NO_SPECULATIVE_VULNERABILITIES - select IOAPIC - select LOAPIC - select CPU_HAS_FPU - select INTEL_HAL - select HAS_PM - select HAS_COVERAGE_SUPPORT diff --git a/soc/x86/intel_ish/Kconfig.defconfig b/soc/x86/intel_ish/Kconfig.defconfig deleted file mode 100644 index adcca64b9a8..00000000000 --- a/soc/x86/intel_ish/Kconfig.defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Intel ISH family default configuration options -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_INTEL_ISH - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 if HPET_TIMER - -config SOC_FAMILY - string - default "intel_ish" - -config X86_VERY_EARLY_CONSOLE - default n - -config SRAM_OFFSET - hex - default 0x0 - -# Target platforms are not PC-compatible -# (e.g. without BIOS, ACPI, CMOS, etc.). -config X86_PC_COMPATIBLE - default n - -endif # SOC_FAMILY_INTEL_ISH - -rsource "*/Kconfig.defconfig.series" diff --git a/soc/x86/intel_ish/Kconfig.soc b/soc/x86/intel_ish/Kconfig.soc deleted file mode 100644 index b4b1e1456b9..00000000000 --- a/soc/x86/intel_ish/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Intel ISH family selection -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -rsource "*/Kconfig.series" -rsource "*/Kconfig.soc" diff --git a/soc/x86/intel_ish/intel_ish5/CMakeLists.txt b/soc/x86/intel_ish/intel_ish5/CMakeLists.txt deleted file mode 100644 index 3c253ac2648..00000000000 --- a/soc/x86/intel_ish/intel_ish5/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_cc_option(-march=pentium -mtune=i486) - -zephyr_sources(soc.c) -add_subdirectory_ifdef(CONFIG_PM pm) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") - -include(../utils/build_ish_firmware.cmake) diff --git a/soc/x86/intel_ish/intel_ish5/Kconfig.defconfig.series b/soc/x86/intel_ish/intel_ish5/Kconfig.defconfig.series deleted file mode 100644 index fecc6d2428f..00000000000 --- a/soc/x86/intel_ish/intel_ish5/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_INTEL_ISH5 - -config SOC_SERIES - string - default "intel_ish5" - -config SOC - string - default "intel_ish_5_4_1" if SOC_INTEL_ISH_5_4_1 - default "intel_ish_5_6_0" if SOC_INTEL_ISH_5_6_0 - default "intel_ish_5_8_0" if SOC_INTEL_ISH_5_8_0 - -endif # SOC_SERIES_INTEL_ISH5 - -rsource "pm/Kconfig.pm" diff --git a/soc/x86/intel_ish/intel_ish5/Kconfig.series b/soc/x86/intel_ish/intel_ish5/Kconfig.series deleted file mode 100644 index ef39ee29c20..00000000000 --- a/soc/x86/intel_ish/intel_ish5/Kconfig.series +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_INTEL_ISH5 - bool "Intel ISH5 SoC" - select SOC_FAMILY_INTEL_ISH diff --git a/soc/x86/intel_ish/intel_ish5/Kconfig.soc b/soc/x86/intel_ish/intel_ish5/Kconfig.soc deleted file mode 100644 index bbc4a76fdae..00000000000 --- a/soc/x86/intel_ish/intel_ish5/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -choice - prompt "Intel ISH5 SoCs" - depends on SOC_SERIES_INTEL_ISH5 - -config SOC_INTEL_ISH_5_4_1 - bool "Intel ISH 5.4.1 SoC" - -config SOC_INTEL_ISH_5_6_0 - bool "Intel ISH 5.6.0 SoC" - -config SOC_INTEL_ISH_5_8_0 - bool "Intel ISH 5.8.0 SoC" - -endchoice diff --git a/soc/x86/lakemont/CMakeLists.txt b/soc/x86/lakemont/CMakeLists.txt deleted file mode 100644 index 4527b084519..00000000000 --- a/soc/x86/lakemont/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_cc_option(-march=pentium) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/lakemont/Kconfig.defconfig b/soc/x86/lakemont/Kconfig.defconfig deleted file mode 100644 index 3e21fbe3e00..00000000000 --- a/soc/x86/lakemont/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LAKEMONT - -config SOC - default "lakemont" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -# Can be enabled once UART is defined in board -# configuration. -config X86_VERY_EARLY_CONSOLE - default n - -# Target platforms are usually not PC-compatible -# (e.g. without BIOS, ACPI, etc.). -config X86_PC_COMPATIBLE - default n - -endif diff --git a/soc/x86/lakemont/Kconfig.soc b/soc/x86/lakemont/Kconfig.soc deleted file mode 100644 index 9a62a2d1e44..00000000000 --- a/soc/x86/lakemont/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_LAKEMONT - bool "Intel Lakemont SoC" - select X86 - select CPU_LAKEMONT - select X86_MMU if FPU - select X86_SSE if FPU - select X86_SSE2 if FPU - select X86_SSE3 if FPU - select X86_SSSE3 if FPU - select ARCH_HAS_USERSPACE diff --git a/soc/x86/lakemont/linker.ld b/soc/x86/lakemont/linker.ld deleted file mode 100644 index d77f13846dd..00000000000 --- a/soc/x86/lakemont/linker.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2011-2014, Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include diff --git a/soc/x86/raptor_lake/CMakeLists.txt b/soc/x86/raptor_lake/CMakeLists.txt deleted file mode 100644 index 06c46752f81..00000000000 --- a/soc/x86/raptor_lake/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_cc_option(-march=goldmont) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/raptor_lake/Kconfig.defconfig b/soc/x86/raptor_lake/Kconfig.defconfig deleted file mode 100644 index f9b14da95d0..00000000000 --- a/soc/x86/raptor_lake/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Raptor Lake SoC configuration options - -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_RAPTOR_LAKE - -config SOC - default "raptor_lake" - -config PCIE_MMIO_CFG - default y - -config X86_DYNAMIC_IRQ_STUBS - default 16 - depends on DYNAMIC_INTERRUPTS - -endif # SOC_RAPTOR_LAKE diff --git a/soc/x86/raptor_lake/Kconfig.soc b/soc/x86/raptor_lake/Kconfig.soc deleted file mode 100644 index b172bc44869..00000000000 --- a/soc/x86/raptor_lake/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 Intel Corporation Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RAPTOR_LAKE - bool "Intel Raptor Lake Soc" - select X86 - select CPU_ATOM - select PCIE - select PCIE_MSI - select DYNAMIC_INTERRUPTS - select X86_MMU diff --git a/soc/arm64/xenvm/CMakeLists.txt b/soc/xen/CMakeLists.txt similarity index 100% rename from soc/arm64/xenvm/CMakeLists.txt rename to soc/xen/CMakeLists.txt diff --git a/soc/xen/Kconfig b/soc/xen/Kconfig new file mode 100644 index 00000000000..966c5fc6ba0 --- /dev/null +++ b/soc/xen/Kconfig @@ -0,0 +1,7 @@ +# Copyright 2020 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XENVM + select ARM64 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select CPU_CORTEX_A72 diff --git a/soc/xen/Kconfig.defconfig b/soc/xen/Kconfig.defconfig new file mode 100644 index 00000000000..eeb2cf9aa0e --- /dev/null +++ b/soc/xen/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright 2020 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if SOC_XENVM + +config NUM_IRQS + int + default 500 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 8320000 + +# We need at least 16M of virtual address space to map memory of Xen node +# 32M should be enough for basic use-cases +config KERNEL_VM_SIZE + default 0x2000000 + +endif diff --git a/soc/xen/Kconfig.soc b/soc/xen/Kconfig.soc new file mode 100644 index 00000000000..65452526749 --- /dev/null +++ b/soc/xen/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright 2020 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XENVM + bool + +config SOC + default "xenvm" if SOC_XENVM diff --git a/soc/arm64/xenvm/mmu_regions.c b/soc/xen/mmu_regions.c similarity index 100% rename from soc/arm64/xenvm/mmu_regions.c rename to soc/xen/mmu_regions.c diff --git a/soc/xen/soc.yml b/soc/xen/soc.yml new file mode 100644 index 00000000000..c559004e7c6 --- /dev/null +++ b/soc/xen/soc.yml @@ -0,0 +1,4 @@ +series: +- name: xenvm + socs: + - name: xenvm diff --git a/soc/arm/xilinx_zynq7000/CMakeLists.txt b/soc/xlnx/zynq7000/CMakeLists.txt similarity index 100% rename from soc/arm/xilinx_zynq7000/CMakeLists.txt rename to soc/xlnx/zynq7000/CMakeLists.txt diff --git a/soc/xlnx/zynq7000/Kconfig b/soc/xlnx/zynq7000/Kconfig new file mode 100644 index 00000000000..478c5bb4010 --- /dev/null +++ b/soc/xlnx/zynq7000/Kconfig @@ -0,0 +1,10 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_FAMILY_XILINX_ZYNQ7000 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_XILINX_ZYNQ7000 diff --git a/soc/xlnx/zynq7000/Kconfig.defconfig b/soc/xlnx/zynq7000/Kconfig.defconfig new file mode 100644 index 00000000000..8976925507f --- /dev/null +++ b/soc/xlnx/zynq7000/Kconfig.defconfig @@ -0,0 +1,27 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_FAMILY_XILINX_ZYNQ7000 + +rsource "*/Kconfig.defconfig" + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 96 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config PLATFORM_SPECIFIC_INIT + default y + +endif # SOC_FAMILY_XILINX_ZYNQ7000 diff --git a/soc/xlnx/zynq7000/Kconfig.soc b/soc/xlnx/zynq7000/Kconfig.soc new file mode 100644 index 00000000000..c925637d783 --- /dev/null +++ b/soc/xlnx/zynq7000/Kconfig.soc @@ -0,0 +1,12 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_FAMILY_XILINX_ZYNQ7000 + bool + +config SOC_FAMILY + default "xilinx_zynq7000" if SOC_FAMILY_XILINX_ZYNQ7000 + +rsource "*/Kconfig.soc" diff --git a/soc/arm/xilinx_zynq7000/common/pinctrl_soc.h b/soc/xlnx/zynq7000/common/pinctrl_soc.h similarity index 100% rename from soc/arm/xilinx_zynq7000/common/pinctrl_soc.h rename to soc/xlnx/zynq7000/common/pinctrl_soc.h diff --git a/soc/xlnx/zynq7000/soc.yml b/soc/xlnx/zynq7000/soc.yml new file mode 100644 index 00000000000..25c5d0f227f --- /dev/null +++ b/soc/xlnx/zynq7000/soc.yml @@ -0,0 +1,18 @@ +family: +- name: xilinx_zynq7000 + series: + - name: xc7zxxx + socs: + - name: xc7z010 + - name: xc7z010 + - name: xc7z015 + - name: xc7z020 + - name: xc7z030 + - name: xc7z035 + - name: xc7z045 + - name: xc7z100 + - name: xc7zxxxs + socs: + - name: xc7z007s + - name: xc7z012s + - name: xc7z014s diff --git a/soc/xlnx/zynq7000/xc7zxxx/CMakeLists.txt b/soc/xlnx/zynq7000/xc7zxxx/CMakeLists.txt new file mode 100644 index 00000000000..dcdc25a830a --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxx/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/xlnx/zynq7000/xc7zxxx/Kconfig b/soc/xlnx/zynq7000/xc7zxxx/Kconfig new file mode 100644 index 00000000000..7a94994fd8d --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxx/Kconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# +# Device data: comp. +# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable +# + +config SOC_SERIES_XC7ZXXX + select ARM + select CPU_CORTEX_A9 + select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER diff --git a/soc/xlnx/zynq7000/xc7zxxx/Kconfig.defconfig b/soc/xlnx/zynq7000/xc7zxxx/Kconfig.defconfig new file mode 100644 index 00000000000..b7e4f98dfbe --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxx/Kconfig.defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_XC7ZXXX + +# Zephyr does not support SMP on aarch32 yet, so we default to 1 CPU core +config MP_MAX_NUM_CPUS + default 1 + +endif # SOC_SERIES_XC7ZXXX diff --git a/soc/xlnx/zynq7000/xc7zxxx/Kconfig.soc b/soc/xlnx/zynq7000/xc7zxxx/Kconfig.soc new file mode 100644 index 00000000000..6405dc488af --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxx/Kconfig.soc @@ -0,0 +1,80 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# +# Device data: comp. +# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable +# + +config SOC_SERIES_XC7ZXXX + bool + select SOC_FAMILY_XILINX_ZYNQ7000 + help + Enable support for the Xilinx Zynq-7000 (XC7Zxxx) + SoC series (dual core ARM Cortex-A9). + +config SOC_XILINX_XC7Z010 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, + 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins. + +config SOC_XILINX_XC7Z015 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, + 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins, + up to 4 transceivers. + +config SOC_XILINX_XC7Z020 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, + 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins. + +config SOC_XILINX_XC7Z030 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, + 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins, + up to 4 transceivers. + +config SOC_XILINX_XC7Z035 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, + 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins, + up to 16 transceivers. + +config SOC_XILINX_XC7Z045 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, + 350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins, + up to 16 transceivers. + +config SOC_XILINX_XC7Z100 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, + 444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins, + up to 16 transceivers. + +config SOC_SERIES + default "xc7zxxx" if SOC_SERIES_XC7ZXXX + +config SOC + default "xc7z010" if SOC_XILINX_XC7Z010 + default "xc7z015" if SOC_XILINX_XC7Z015 + default "xc7z020" if SOC_XILINX_XC7Z020 + default "xc7z030" if SOC_XILINX_XC7Z030 + default "xc7z035" if SOC_XILINX_XC7Z035 + default "xc7z045" if SOC_XILINX_XC7Z045 + default "xc7z100" if SOC_XILINX_XC7Z100 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c b/soc/xlnx/zynq7000/xc7zxxx/soc.c similarity index 100% rename from soc/arm/xilinx_zynq7000/xc7zxxx/soc.c rename to soc/xlnx/zynq7000/xc7zxxx/soc.c diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.h b/soc/xlnx/zynq7000/xc7zxxx/soc.h similarity index 100% rename from soc/arm/xilinx_zynq7000/xc7zxxx/soc.h rename to soc/xlnx/zynq7000/xc7zxxx/soc.h diff --git a/soc/xlnx/zynq7000/xc7zxxxs/CMakeLists.txt b/soc/xlnx/zynq7000/xc7zxxxs/CMakeLists.txt new file mode 100644 index 00000000000..dcdc25a830a --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxxs/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/xlnx/zynq7000/xc7zxxxs/Kconfig b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig new file mode 100644 index 00000000000..ecac57425fe --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# +# Device data: comp. +# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable +# + +config SOC_SERIES_XC7ZXXXS + select ARM + select CPU_CORTEX_A9 + select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER diff --git a/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.defconfig b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.defconfig new file mode 100644 index 00000000000..6b4c6558c9a --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.defconfig @@ -0,0 +1,11 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_XC7ZXXXS + +config MP_MAX_NUM_CPUS + default 1 + +endif # SOC_SERIES_XC7ZXXXS diff --git a/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.soc b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.soc new file mode 100644 index 00000000000..71a0bf01991 --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.soc @@ -0,0 +1,44 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# +# Device data: comp. +# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable +# + +config SOC_SERIES_XC7ZXXXS + bool + select SOC_FAMILY_XILINX_ZYNQ7000 + help + Enable support for the Xilinx Zynq-7000S (XC7ZxxxS) + SoC series (single core ARM Cortex-A9). + +config SOC_XILINX_XC7Z007S + bool + select SOC_SERIES_XC7ZXXXS + help + 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, + 23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins. + +config SOC_XILINX_XC7Z012S + bool + select SOC_SERIES_XC7ZXXXS + help + 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, + 55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins, + up to 4 transceivers. + +config SOC_XILINX_XC7Z014S + bool + select SOC_SERIES_XC7ZXXXS + help + 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, + 65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins. + +config SOC_SERIES + default "xc7zxxxs" if SOC_SERIES_XC7ZXXXS + +config SOC + default "xc7z007s" if SOC_XILINX_XC7Z007S + default "xc7z012s" if SOC_XILINX_XC7Z012S + default "xc7z014s" if SOC_XILINX_XC7Z014S diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c b/soc/xlnx/zynq7000/xc7zxxxs/soc.c similarity index 100% rename from soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c rename to soc/xlnx/zynq7000/xc7zxxxs/soc.c diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.h b/soc/xlnx/zynq7000/xc7zxxxs/soc.h similarity index 100% rename from soc/arm/xilinx_zynq7000/xc7zxxxs/soc.h rename to soc/xlnx/zynq7000/xc7zxxxs/soc.h diff --git a/soc/xlnx/zynqmp/CMakeLists.txt b/soc/xlnx/zynqmp/CMakeLists.txt new file mode 100644 index 00000000000..70885608559 --- /dev/null +++ b/soc/xlnx/zynqmp/CMakeLists.txt @@ -0,0 +1,17 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c +) +zephyr_sources_ifdef( + CONFIG_ARM_MPU + arm_mpu_regions.c +) + +zephyr_include_directories(.) + +if(CONFIG_SOC_XILINX_ZYNQMP_RPU) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/xlnx/zynqmp/Kconfig b/soc/xlnx/zynqmp/Kconfig new file mode 100644 index 00000000000..f28454573c6 --- /dev/null +++ b/soc/xlnx/zynqmp/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# Copyright (c) 2019 Stephanos Ioannidis +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XILINX_ZYNQMP_RPU + select ARM + select CPU_CORTEX_R5 + select PLATFORM_SPECIFIC_INIT + select CPU_HAS_ARM_MPU + select VFP_DP_D16 diff --git a/soc/xlnx/zynqmp/Kconfig.defconfig b/soc/xlnx/zynqmp/Kconfig.defconfig new file mode 100644 index 00000000000..869f4403d32 --- /dev/null +++ b/soc/xlnx/zynqmp/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# Copyright (c) 2019 Stephanos Ioannidis +# SPDX-License-Identifier: Apache-2.0 + +if SOC_XILINX_ZYNQMP + +if SOC_XILINX_ZYNQMP_RPU + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + default 220 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 5000000 + +endif # SOC_XILINX_ZYNQMP_RPU + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +endif # SOC_XILINX_ZYNQMP diff --git a/soc/xlnx/zynqmp/Kconfig.soc b/soc/xlnx/zynqmp/Kconfig.soc new file mode 100644 index 00000000000..136e1d1f1a0 --- /dev/null +++ b/soc/xlnx/zynqmp/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# Copyright (c) 2019 Stephanos Ioannidis +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XILINX_ZYNQMP + bool + +config SOC_XILINX_ZYNQMP_RPU + bool + select SOC_XILINX_ZYNQMP + help + Xilinx ZynqMP RPU + +config SOC_FAMILY + default "xilinx_zynqmp" if SOC_XILINX_ZYNQMP + +config SOC + default "zynqmp_rpu" if SOC_XILINX_ZYNQMP_RPU diff --git a/soc/arm/xilinx_zynqmp/arm_mpu_regions.c b/soc/xlnx/zynqmp/arm_mpu_regions.c similarity index 100% rename from soc/arm/xilinx_zynqmp/arm_mpu_regions.c rename to soc/xlnx/zynqmp/arm_mpu_regions.c diff --git a/soc/arm/xilinx_zynqmp/pinctrl_soc.h b/soc/xlnx/zynqmp/pinctrl_soc.h similarity index 100% rename from soc/arm/xilinx_zynqmp/pinctrl_soc.h rename to soc/xlnx/zynqmp/pinctrl_soc.h diff --git a/soc/arm/xilinx_zynqmp/soc.c b/soc/xlnx/zynqmp/soc.c similarity index 100% rename from soc/arm/xilinx_zynqmp/soc.c rename to soc/xlnx/zynqmp/soc.c diff --git a/soc/arm/xilinx_zynqmp/soc.h b/soc/xlnx/zynqmp/soc.h similarity index 100% rename from soc/arm/xilinx_zynqmp/soc.h rename to soc/xlnx/zynqmp/soc.h diff --git a/soc/xlnx/zynqmp/soc.yml b/soc/xlnx/zynqmp/soc.yml new file mode 100644 index 00000000000..e1a20c4a5ef --- /dev/null +++ b/soc/xlnx/zynqmp/soc.yml @@ -0,0 +1,4 @@ +family: +- name: xilinx_zynqmp + socs: + - name: zynqmp_rpu diff --git a/soc/xtensa/CMakeLists.txt b/soc/xtensa/CMakeLists.txt deleted file mode 100644 index b826da926ca..00000000000 --- a/soc/xtensa/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) -else() - add_subdirectory(${SOC_NAME}) -endif() diff --git a/soc/xtensa/dc233c/Kconfig.defconfig b/soc/xtensa/dc233c/Kconfig.defconfig deleted file mode 100644 index dc5be860b4a..00000000000 --- a/soc/xtensa/dc233c/Kconfig.defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_XTENSA_DC233C - -config SOC - default "dc233c" - -config SOC_TOOLCHAIN_NAME - string - default "dc233c" - -config XTENSA_MMU_NUM_L2_TABLES - int - default 48 if XTENSA_MMU - -# Both SRAM_OFFSET and KERNEL_VM_OFFSET are set at 1MB. -# This is to allow VECBASE to be mapped permanently -# via TLB way 4 (which covers 1MB). -config SRAM_OFFSET - hex - default 0x100000 if XTENSA_MMU - default 0x2400 - -config KERNEL_VM_OFFSET - hex - default 0x100000 - -endif diff --git a/soc/xtensa/dc233c/Kconfig.soc b/soc/xtensa/dc233c/Kconfig.soc deleted file mode 100644 index ecbe77a9feb..00000000000 --- a/soc/xtensa/dc233c/Kconfig.soc +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2017, 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XTENSA_DC233C - bool "Xtensa dc233c core" - select XTENSA - select XTENSA_HAL - select ARCH_HAS_THREAD_LOCAL_STORAGE - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CPU_HAS_MMU - select ARCH_HAS_RESERVED_PAGE_FRAMES if XTENSA_MMU - select ARCH_HAS_USERSPACE if XTENSA_MMU - select XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP if XTENSA_MMU diff --git a/soc/xtensa/espressif_esp32/CMakeLists.txt b/soc/xtensa/espressif_esp32/CMakeLists.txt deleted file mode 100644 index 31ef76aadee..00000000000 --- a/soc/xtensa/espressif_esp32/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) -add_subdirectory(common) diff --git a/soc/xtensa/espressif_esp32/Kconfig b/soc/xtensa/espressif_esp32/Kconfig deleted file mode 100644 index 31e176291ab..00000000000 --- a/soc/xtensa/espressif_esp32/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ESP32 - bool - -if SOC_FAMILY_ESP32 - -config SOC_FAMILY - string - default "espressif_esp32" - -source "soc/xtensa/espressif_esp32/common/Kconfig.soc" -source "soc/xtensa/espressif_esp32/*/Kconfig.soc" - -endif # SOC_FAMILY_ESP32 diff --git a/soc/xtensa/espressif_esp32/Kconfig.defconfig b/soc/xtensa/espressif_esp32/Kconfig.defconfig deleted file mode 100644 index fedabb82b8c..00000000000 --- a/soc/xtensa/espressif_esp32/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series" -source "soc/xtensa/espressif_esp32/*/Kconfig.defconfig.series" diff --git a/soc/xtensa/espressif_esp32/Kconfig.soc b/soc/xtensa/espressif_esp32/Kconfig.soc deleted file mode 100644 index 6b28e800868..00000000000 --- a/soc/xtensa/espressif_esp32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/xtensa/espressif_esp32/*/Kconfig.series" diff --git a/soc/xtensa/espressif_esp32/common/CMakeLists.txt b/soc/xtensa/espressif_esp32/common/CMakeLists.txt deleted file mode 100644 index e097e8ce4ee..00000000000 --- a/soc/xtensa/espressif_esp32/common/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(include) diff --git a/soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series b/soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series deleted file mode 100644 index 771976bc66d..00000000000 --- a/soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series +++ /dev/null @@ -1,44 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_ESP32 - -# Xtensa default options for ESP32 family -config XTENSA_RESET_VECTOR - default n - -config XTENSA_USE_CORE_CRT1 - default n - -config GEN_ISR_TABLES - default y - -config GEN_IRQ_VECTOR_TABLE - default n - -config CLOCK_CONTROL - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -if BOOTLOADER_MCUBOOT - - config HAS_FLASH_LOAD_OFFSET - default y - config MCUBOOT_GENERATE_UNSIGNED_IMAGE - default y - config MCUBOOT_GENERATE_CONFIRMED_IMAGE - default y - config ROM_START_OFFSET - default 0x20 - -endif # BOOTLOADER_MCUBOOT - -endif # SOC_FAMILY_ESP32 diff --git a/soc/xtensa/espressif_esp32/common/Kconfig.soc b/soc/xtensa/espressif_esp32/common/Kconfig.soc deleted file mode 100644 index c8eaad62d5b..00000000000 --- a/soc/xtensa/espressif_esp32/common/Kconfig.soc +++ /dev/null @@ -1,215 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_ESP32 - -config ESPTOOLPY_FLASHFREQ_80M - bool - -config FLASH_SIZE - int - -config FLASH_BASE_ADDRESS - hex - -config ESP_SPIRAM - bool "Support for external, SPI-connected RAM" - help - This enables support for an external SPI RAM chip, connected in - parallel with the main SPI flash chip. - -config ESP_HEAP_MIN_EXTRAM_THRESHOLD - int "Minimum threshold for external RAM allocation" - default 8192 - range 1024 131072 - depends on ESP_SPIRAM - help - Threshold to decide if memory will be allocated from DRAM - or SPIRAM. If value of allocation size is less than this value, - memory will be allocated from internal RAM. - -config ESP_HEAP_SEARCH_ALL_REGIONS - bool "Search for all available heap regions" - depends on ESP_SPIRAM - default y - help - This configuration enables searching all available heap - regions. If the region of desired capability is exhausted, - memory will be allocated from other available region. - -config ESP_SPIRAM_HEAP_SIZE - int "Size of SPIRAM heap" - default 262134 if SYS_HEAP_SMALL_ONLY - default 1048576 if !SYS_HEAP_SMALL_ONLY - depends on ESP_SPIRAM - help - Specify size of SPIRAM heap. - -menu "SPI RAM config" - depends on ESP_SPIRAM - -choice SPIRAM_MODE - prompt "Mode (QUAD/OCT) of SPI RAM chip in use" - default SPIRAM_MODE_QUAD - -config SPIRAM_MODE_QUAD - bool "Quad Mode PSRAM" - -endchoice # SPIRAM_MODE - -choice SPIRAM_TYPE - prompt "Type of SPI RAM chip in use" - depends on ESP_SPIRAM - default SPIRAM_TYPE_ESPPSRAM16 - -config SPIRAM_TYPE_ESPPSRAM16 - bool "ESP-PSRAM16 or APS1604" - -config SPIRAM_TYPE_ESPPSRAM32 - bool "ESP-PSRAM32 or IS25WP032" - -config SPIRAM_TYPE_ESPPSRAM64 - bool "ESP-PSRAM64 or LY68L6400" - -endchoice # SPIRAM_TYPE - -config ESP_SPIRAM_SIZE - int "Size of SPIRAM part" - default 2097152 if SPIRAM_TYPE_ESPPSRAM16 - default 4194304 if SPIRAM_TYPE_ESPPSRAM32 - default 8388608 if SPIRAM_TYPE_ESPPSRAM64 - help - Specify size of SPIRAM part. - NOTE: If SPIRAM size is greater than 4MB, only - lower 4MB can be allocated using k_malloc(). - -choice SPIRAM_SPEED - prompt "Set RAM clock speed" - default SPIRAM_SPEED_40M - help - Select the speed for the SPI RAM chip. - If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: - - 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz - 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz - 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz - - Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host - will be occupied by the system. Which SPI host to use can be selected by the config item - SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The - option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. - (ESPTOOLPY_FLASHFREQ_79M is true) - -config SPIRAM_SPEED_26M - bool "26MHz clock speed" - depends on SOC_SERIES_ESP32S2 - -config SPIRAM_SPEED_20M - bool "20MHz clock speed" - depends on SOC_SERIES_ESP32S2 - -config SPIRAM_SPEED_40M - bool "40MHz clock speed" - -config SPIRAM_SPEED_80M - depends on ESPTOOLPY_FLASHFREQ_80M - bool "80MHz clock speed" - -config SPIRAM_SPEED_120M - depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3 - bool "120MHz clock speed" - -endchoice # SPIRAM_SPEED - -menu "PSRAM clock and cs IO for ESP32-DOWD" - -config D0WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 17 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D0WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 16 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-DOWD - -menu "PSRAM clock and cs IO for ESP32-D2WD" - -config D2WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 9 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D2WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-D2WD - -menu "PSRAM clock and cs IO for ESP32-PICO" - -config PICO_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. - - For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock - IO. - For the reference hardware design, please refer to - https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf - -endmenu # PSRAM clock and cs IO for ESP32-PICO - -config SPIRAM_CUSTOM_SPIWP_SD3_PIN - bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" - default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5 - default n - help - This setting is only used if the SPI flash pins have been overridden by setting the eFuses - SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. - - When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka - ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI - mode, so a WP pin setting is necessary. - - If this config item is set to N (default), the correct WP pin will be automatically used for any - Espressif chip or module with integrated flash. If a custom setting is needed, set this config item - to Y and specify the GPIO number connected to the WP pin. - - When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin - configured in the bootloader. - -config SPIRAM_SPIWP_SD3_PIN - int "Custom SPI PSRAM WP(SD3) Pin" - range 0 33 - default 7 - help - The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored - - If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this - value to the GPIO number of the SPIRAM WP pin. - -config SPIRAM - bool - default y - -endmenu # SPI RAM config - -endif # SOC_FAMILY_ESP32 diff --git a/soc/xtensa/espressif_esp32/esp32/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32/CMakeLists.txt deleted file mode 100644 index c71c016a706..00000000000 --- a/soc/xtensa/espressif_esp32/esp32/CMakeLists.txt +++ /dev/null @@ -1,123 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if (CONFIG_SOC_ESP32_APPCPU) - zephyr_sources(soc_appcpu.c) -else() - zephyr_sources( - soc.c - loader.c - esp32-mp.c - ) -endif() - -zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) - -zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c) - -zephyr_library_sources_ifdef(CONFIG_PM power.c) -zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -# get flash size to use in esptool as string -math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") - -if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") - -endif() - -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py - ARGS --chip esp32 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) - endif() - - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - -endif() - -## When building for APPCPU -if (CONFIG_SOC_ESP32_APPCPU) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py - ARGS -i ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c - -a "esp32_appcpu_fw_array") - endif() - -else() - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - # get code-partition slot0 address - dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") - dt_reg_addr(img_0_off PATH ${dts_partition_path}) - - # get code-partition boot address - dt_nodelabel(dts_partition_path NODELABEL "boot_partition") - dt_reg_addr(boot_off PATH ${dts_partition_path}) - - board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") - board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") -endif() - -if(CONFIG_MCUBOOT) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") -elseif(CONFIG_SOC_ESP32_APPCPU) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "") -else() - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") -endif() diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series deleted file mode 100644 index 50a7e9e8124..00000000000 --- a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32 - -config SOC_SERIES - default "esp32" - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config ESPTOOLPY_FLASHFREQ_80M - default y - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/flash-controller@3ff42000/flash@0,0) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/flash-controller@3ff42000/flash@0) - -if SMP - -config SCHED_IPI_SUPPORTED - default y - -config SCHED_CPU_MASK - default y - -config MP_MAX_NUM_CPUS - default 2 - -endif # SMP config - -if GDBSTUB - -# ESP32 GDB expects 420 bytes G-packet. -# So double for hexadecimal digits. -config GDBSTUB_BUF_SZ - default 840 if GDBSTUB - -endif # GDBSTUB config - -endif # SOC_SERIES_ESP32 config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.series b/soc/xtensa/espressif_esp32/esp32/Kconfig.series deleted file mode 100644 index 858386e4fd0..00000000000 --- a/soc/xtensa/espressif_esp32/esp32/Kconfig.series +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ESP32 - bool "ESP32 Series" - select XTENSA - select SOC_FAMILY_ESP32 - select CLOCK_CONTROL - select DYNAMIC_INTERRUPTS - select ARCH_HAS_GDBSTUB - select ARCH_SUPPORTS_COREDUMP - select PINCTRL - select XIP if !MCUBOOT - select HAS_ESPRESSIF_HAL - select CPU_HAS_FPU - select HAS_PM - select HAS_POWEROFF - help - Enable support for Espressif ESP32 - -config SOC_ESP32_PROCPU - bool "Application runs in ESP32 PROCPU (core 0)" - depends on SOC_SERIES_ESP32 - help - When this SOC is enabled, it will run application on PROCPU (core 0). It will automatically - enable AMP support by building, flashing and loading APPCPU (core 1) image if exists. - -config SOC_ESP32_APPCPU - bool "Application runs in ESP32 APPCPU (core 1)" - depends on SOC_SERIES_ESP32 - help - When this SOC is enabled, it will run application on APPCPU (core 1). It is expected that - there is another image running on PROCPU (core 0) to trigger the AMP support. diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32/Kconfig.soc deleted file mode 100644 index 6b530767703..00000000000 --- a/soc/xtensa/espressif_esp32/esp32/Kconfig.soc +++ /dev/null @@ -1,281 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32 - -config IDF_TARGET_ESP32 - bool "ESP32 as target board" - default y - -config SOC_TOOLCHAIN_NAME - string - default "espressif_esp32" - -choice SOC_PART_NUMBER - prompt "ESP32 SOC/SIP Selection" - - # SoC with/without embedded flash - config SOC_ESP32_D0WD_V3 - bool "ESP32_D0WD_V3" - config SOC_ESP32_D0WDR2_V3 - bool "ESP32_D0WDR2_V3" - config SOC_ESP32_U4WDH - bool "ESP32_U4WDH" - config SOC_ESP32_PICO_V3 - bool "ESP32_PICO_V3" - config SOC_ESP32_PICO_V3_02 - bool "ESP32_PICO_V3_02" - config SOC_ESP32_PICO_D4 - bool "ESP32_PICO_D4" - # SiP with external flash / psram - config SOC_ESP32_WROOM_DA_N4 - bool "ESP32_WROOM_DA_N4" - config SOC_ESP32_WROOM_DA_N8 - bool "ESP32_WROOM_DA_N8" - config SOC_ESP32_WROOM_DA_N16 - bool "ESP32_WROOM_DA_N16" - config SOC_ESP32_WROOM_32UE_N4 - bool "ESP32_WROOM_32UE_N4" - config SOC_ESP32_WROOM_32UE_N8 - bool "ESP32_WROOM_32UE_N8" - config SOC_ESP32_WROOM_32UE_N16 - bool "ESP32_WROOM_32UE_N16" - config SOC_ESP32_WROVER_E_N4R2 - bool "ESP32_WROVER_E_N4R2" - config SOC_ESP32_WROVER_E_N8R2 - bool "ESP32_WROVER_E_N8R2" - config SOC_ESP32_WROVER_E_N16R2 - bool "ESP32_WROVER_E_N16R2" - config SOC_ESP32_WROVER_E_N4R8 - bool "ESP32_WROVER_E_N4R8" - config SOC_ESP32_WROVER_E_N8R8 - bool "ESP32_WROVER_E_N8R8" - config SOC_ESP32_WROVER_E_N16R8 - bool "ESP32_WROVER_E_N16R8" - -endchoice # SOC_PART_NUMBER - -config ESP32_APPCPU_IRAM - hex "ESP32 APPCPU IRAM size" - depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU - default 0x20000 - help - Defines APPCPU IRAM area in bytes. - -config ESP32_APPCPU_DRAM - hex "ESP32 APPCPU DRAM size" - depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU - default 0x10000 - help - Defines APPCPU DRAM area in bytes. - -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - -config ESP32_BT_RESERVE_DRAM - hex "Bluetooth controller reserved RAM region" - default 0xdb5c if BT - default 0 - -config ESP_HEAP_MEM_POOL_REGION_1_SIZE - int "Internal DRAM region 1 mempool size" - default 0 if MCUBOOT - default 1024 if SOC_ESP32_PROCPU - default 49152 - help - ESP32 has two banks of size 192K and 128K which can be used - as DRAM, system heap allocates area from region 0. - This configuration can be used to add memory from region 1 - to heap and can be allocated using k_malloc. - -choice ESP32_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - - "Internal 150kHz oscillator" option provides lowest deep sleep current - consumption, and does not require extra external components. However - frequency stability with respect to temperature is poor, so time may - drift in deep/light sleep modes. - - "External 32kHz crystal" provides better frequency stability, at the - expense of slightly higher (1uA) deep sleep current consumption. - - "External 32kHz oscillator" allows using 32kHz clock generated by an - external circuit. In this case, external clock signal must be connected - to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, - and <1V in case of square wave signal. Common mode voltage should be - 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. - Additionally, 1nF capacitor must be connected between 32K_XP pin and - ground. 32K_XP pin can not be used as a GPIO in this case. - - "Internal 8.5MHz oscillator divided by 256" option results in higher - deep sleep current (by 5uA) but has better frequency stability than - the internal 150kHz oscillator. It does not require external components. - -config ESP32_RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - -config ESP32_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XN pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" - -endchoice # ESP32_RTC_CLK_SRC - -config ESP32_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -config ESP32_RTC_XTAL_CAL_RETRY - int "Number of attempts to repeat 32k XTAL calibration" - default 1 - depends on ESP32_RTC_CLK_SRC_EXT_CRYS - help - Number of attempts to repeat 32k XTAL calibration - before giving up and switching to the internal RC. - Increase this option if the 32k crystal oscillator - does not start and switches to internal RC. - -config ESP32_DEEP_SLEEP_WAKEUP_DELAY - int "Extra delay in deep sleep wake stub (in us)" - default 2000 - range 0 5000 - help - When ESP32 exits deep sleep, the CPU and the flash chip are powered on - at the same time. CPU will run deep sleep stub first, and then - proceed to load code from flash. Some flash chips need sufficient - time to pass between power on and first read operation. By default, - without any extra delay, this time is approximately 900us, although - some flash chip types need more than that. - - By default extra delay is set to 2000us. When optimizing startup time - for applications which require it, this value may be reduced. - - If you are seeing "flash read err, 1000" message printed to the - console after deep sleep reset, try increasing this value. - -choice ESP32_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is four, - all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally - administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) - to the final octet of the base MAC address. If the number of universal MAC addresses is two, - only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. - These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. - The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. - These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 2 or 4 per device.) - -config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_BT - -config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - bool "Four" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - select ESP_MAC_ADDR_UNIVERSE_BT - select ESP_MAC_ADDR_UNIVERSE_ETH - -endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP_MAC_ADDR_UNIVERSE_BT - bool - -config ESP_MAC_ADDR_UNIVERSE_ETH - bool - -config ESP32_UNIVERSAL_MAC_ADDRESSES - int - default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - -config ESP32_PHY_MAX_WIFI_TX_POWER - int "Max WiFi/BLE TX power (dBm)" - range 10 20 - default 20 - help - Set maximum transmit power for WiFi radio. Actual transmit power for high - data rates may be lower than this setting. - -config ESP32_PHY_MAX_TX_POWER - int - default ESP32_PHY_MAX_WIFI_TX_POWER - -config ESP32_EMAC - bool - default y if ETH_ESP32 - default y if MDIO_ESP32 - default n - help - Hidden option to enable the ESP32 Ethernet MAC driver. - Both Ethernet and MDIO depend on this driver. - This option allows enabling MDIO independently of Ethernet. - -if ESP32_EMAC - -config ETH_DMA_BUFFER_SIZE - int "Ethernet DMA buffer size (Byte)" - range 256 1600 - default 512 - help - Set the size of each buffer used by Ethernet MAC DMA. - -config ETH_DMA_RX_BUFFER_NUM - int "Amount of Ethernet DMA Rx buffers" - range 3 30 - default 10 - help - Number of DMA receive buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE. - Larger number of buffers could increase throughput somehow. - -config ETH_DMA_TX_BUFFER_NUM - int "Amount of Ethernet DMA Tx buffers" - range 3 30 - default 10 - help - Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE. - Larger number of buffers could increase throughput somehow. - -endif # ESP32_EMAC config - -endif # SOC_SERIES_ESP32 config diff --git a/soc/xtensa/espressif_esp32/esp32/default.ld b/soc/xtensa/espressif_esp32/esp32/default.ld deleted file mode 100644 index d0eb9b46f4a..00000000000 --- a/soc/xtensa/espressif_esp32/esp32/default.ld +++ /dev/null @@ -1,583 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * Copyright (c) 2017 Intel Corporation - * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#include -#include -#include -#include - -#define RAMABLE_REGION dram0_0_seg -#ifndef CONFIG_SOC_ESP32_PROCPU -#define RAMABLE_REGION_1 dram0_1_seg -#else -#define RAMABLE_REGION_1 dram0_0_seg -#endif -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define FLASH_CODE_REGION irom0_0_seg - -#define ROMABLE_REGION ROM - -#ifdef CONFIG_FLASH_SIZE -#define FLASH_SIZE CONFIG_FLASH_SIZE -#else -#define FLASH_SIZE 0x400000 -#endif - -#ifdef CONFIG_BOOTLOADER_ESP_IDF -#define IROM_SEG_ORG 0x400D0020 -#define IROM_SEG_LEN FLASH_SIZE-0x20 -#define IROM_SEG_ALIGN 0x4 -#else -#define IROM_SEG_ORG 0x400D0000 -#define IROM_SEG_LEN FLASH_SIZE -#define IROM_SEG_ALIGN 0x10000 -#endif -#define IRAM_SEG_LEN 0x20000 - -/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. - * Executing directly from LMA is not possible. */ -#undef GROUP_ROM_LINK_IN -#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion - -MEMORY -{ - mcuboot_hdr (RX): org = 0x0, len = 0x20 - metadata (RX): org = 0x20, len = 0x20 - ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 - - #ifdef CONFIG_SOC_ESP32_PROCPU - iram0_0_seg(RX): org = 0x40080000, len = 0x08000 - #else - iram0_0_seg(RX): org = 0x40080000, len = IRAM_SEG_LEN - #endif - - irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - /* - * Following is DRAM memory split with reserved address ranges in ESP32: - * - * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions) - * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage) - * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU) - * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU) - * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage) - * - * FIXME: - * - Utilize available memory regions to full capacity - */ - dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM - - #ifdef CONFIG_SOC_ESP32_PROCPU - dram0_shm0_seg(RW): org = 0x3FFE5230, len = 2K /* shared RAM reserved for IPM */ - dram0_sem0_seg(RW): org = 0x3FFE5A30, len = 8 /* shared data reserved for IPM data header */ - dram0_1_seg(RW): org = 0x3FFE5A38, len = 0K /* for AMP builds dram0_1 is reserved for network core */ - #else - dram0_1_seg(RW): org = 0x3FFE5230, len = 0x1BCB0 - 0xEE0 /* skip data for APP CPU initialization usage */ - #endif - - /* DROM is the first segment placed in generated binary. - * MCUboot binary for ESP32 has image header of 0x20 bytes. - * Additional load header of 0x20 bytes are appended to the image. - * Hence, an offset of 0x40 is added to DROM segment origin. - */ - drom0_0_seg(R): org = 0x3F400040, len = 0x400000 - 0x40 - rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000 - rtc_slow_seg(RW): org = 0x50000000, len = 0x1000 -#if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE -#endif -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 -#endif -} - -/* Default entry point: */ -PROVIDE ( _ResetVector = 0x40000400 ); -ENTRY(CONFIG_KERNEL_ENTRY) - -_rom_store_table = 0; - -PROVIDE(_memmap_vecbase_reset = 0x40000450); -PROVIDE(_memmap_reset_vector = 0x40000400); - -SECTIONS -{ - /* Reserve space for MCUboot header in the binary */ - .mcuboot_header : - { - QUAD(0x0) - QUAD(0x0) - QUAD(0x0) - QUAD(0x0) - } > mcuboot_hdr - .metadata : - { - /* Magic byte for load header */ - LONG(0xace637d3) - - /* Application entry point address */ - KEEP(*(.entry_addr)) - - /* IRAM metadata: - * - Destination address (VMA) for IRAM region - * - Flash offset (LMA) for start of IRAM region - * - Size of IRAM region - */ - - LONG(ADDR(.iram0.vectors)) - LONG(LOADADDR(.iram0.vectors)) - LONG(LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - LOADADDR(.iram0.vectors)) - - /* DRAM metadata: - * - Destination address (VMA) for DRAM region - * - Flash offset (LMA) for start of DRAM region - * - Size of DRAM region - */ - - LONG(ADDR(.dram0.data)) - LONG(LOADADDR(.dram0.data)) - LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) - } > metadata - -#include - - _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); - _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; - _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); - - /* NOTE: .rodata section should be the first section in the linker script and no - * other section should appear before .rodata section. This is the requirement - * to align ROM section to 64K page offset. - * Adding .rodata as first section helps to reduce size of generated binary by - * few kBs. - */ - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) - { - __rodata_region_start = ABSOLUTE(.); - - . = ALIGN(4); - #include - - . = ALIGN(4); - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata) - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*) - - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; - - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); - __rodata_region_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - *(.rodata_wlog) - *(.rodata_wlog*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - #include - #include - #include - #include - - /* Create an explicit section at the end of all the data that shall be mapped into drom. - * This is used to calculate the size of the _image_drom_size variable */ - SECTION_PROLOGUE(_RODATA_SECTION_END,,) - { - . = ALIGN(4); - _image_rodata_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - - _image_dram_start = LOADADDR(.dram0.data); - _image_dram_size = LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - _image_dram_start; - _image_dram_vaddr = ADDR(.dram0.data); - - .dram0.data : - { - __data_start = ABSOLUTE(.); - - _btdm_data_start = ABSOLUTE(.); - *libbtdm_app.a:(.data .data.*) - . = ALIGN (4); - _btdm_data_end = ABSOLUTE(.); - - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - /* rodata for panic handler(libarch__xtensa__core.a) and all - * dependent functions should be placed in DRAM to avoid issue - * when flash cache is disabled */ - *libarch__xtensa__core.a:(.rodata .rodata.*) - *libkernel.a:fatal.*(.rodata .rodata.*) - *libkernel.a:init.*(.rodata .rodata.*) - *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) - *libzephyr.a:log_core.*(.rodata .rodata.*) - *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) - *libzephyr.a:log_output.*(.rodata .rodata.*) - *libzephyr.a:loader.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) - *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) - *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) - - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - - /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ - #pragma push_macro("GROUP_ROM_LINK_IN") - #undef GROUP_ROM_LINK_IN - #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN - #include - #pragma pop_macro("GROUP_ROM_LINK_IN") - - .dram0.end : - { - . = ALIGN(4); - #include - . = ALIGN(4); - _end = ABSOLUTE(.); - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - _image_iram_start = LOADADDR(.iram0.vectors); - _image_iram_size = LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - _image_iram_start; - _image_iram_vaddr = ADDR(.iram0.vectors); - - /* Send .iram0 code to iram */ - .iram0.vectors : ALIGN(4) - { - /* Vectors go to IRAM */ - _init_start = ABSOLUTE(.); - /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ - . = 0x0; - KEEP(*(.WindowVectors.text)); - . = 0x180; - KEEP(*(.Level2InterruptVector.text)); - . = 0x1c0; - KEEP(*(.Level3InterruptVector.text)); - . = 0x200; - KEEP(*(.Level4InterruptVector.text)); - . = 0x240; - KEEP(*(.Level5InterruptVector.text)); - . = 0x280; - KEEP(*(.DebugExceptionVector.text)); - . = 0x2c0; - KEEP(*(.NMIExceptionVector.text)); - . = 0x300; - KEEP(*(.KernelExceptionVector.text)); - . = 0x340; - KEEP(*(.UserExceptionVector.text)); - . = 0x3C0; - KEEP(*(.DoubleExceptionVector.text)); - . = 0x400; - *(.*Vector.literal) - - *(.UserEnter.literal); - *(.UserEnter.text); - . = ALIGN (16); - *(.entry.text) - *(.init.literal) - *(.init) - _init_end = ABSOLUTE(.); - - /* This goes here, not at top of linker script, so addr2line finds it last, - and uses it in preference to the first symbol in IRAM */ - _iram_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) - { - /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); - *(.iram1 .iram1.*) - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - *libesp32.a:panic.*(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) - *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) - *libkernel.a:(.literal .text .literal.* .text.*) - *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) - *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) - *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) - *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) - *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) - *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) - *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) - *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) - *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) - *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) - *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) - *libzephyr.a:loader.*(.literal .text .literal.* .text.*) - *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) - *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) - *libc.a:*(.literal .text .literal.* .text.*) - *libphy.a:( .phyiram .phyiram.*) - *libgcov.a:(.literal .text .literal.* .text.*) - -#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) -#endif - -#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) - *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) - *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif - - _iram_text_end = ABSOLUTE(.); - . = ALIGN(4); - _iram_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - /* RTC fast memory holds RTC wake stub code, - including from any source file named rtc_wake_stub*.c - */ - .rtc.text : - { - . = ALIGN(4); - *(.rtc.literal .rtc.text) - *rtc_wake_stub*.o(.literal .text .literal.* .text.*) - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - - /* RTC slow memory holds RTC wake stub - data/rodata, including from any source file - named rtc_wake_stub*.c - */ - .rtc.data : - { - _rtc_data_start = ABSOLUTE(.); - *(.rtc.data) - *(.rtc.rodata) - *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) - _rtc_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.o(.bss .bss.*) - *rtc_wake_stub*.o(COMMON) - _rtc_bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(rtc_slow_seg) - - /* This section located in RTC SLOW Memory area. - It holds data marked with RTC_SLOW_ATTR attribute. - See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : - { - . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } > rtc_slow_seg - - /* Get size of rtc slow data */ - _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); - -#if defined(CONFIG_ESP_SPIRAM) - .ext_ram.bss (NOLOAD): - { - _ext_ram_data_start = ABSOLUTE(.); - -#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) - *libdrivers__wifi.a:(.noinit .noinit.*) - *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) - *libsubsys__net__lib__config.a:(.noinit .noinit.*) - *libsubsys__net__ip.a:(.noinit .noinit.*) - *libsubsys__net.a:(.noinit .noinit.*) -#endif - _spiram_heap_start = ABSOLUTE(.); - . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; - - *(.ext_ram.bss*) - - _ext_ram_data_end = ABSOLUTE(.); - } GROUP_LINK_IN(ext_ram_seg) -#endif - - /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); /* required by bluetooth library */ - __bss_start = ABSOLUTE(.); - - _btdm_bss_start = ABSOLUTE(.); - *libbtdm_app.a:(.bss .bss.* COMMON) - . = ALIGN (4); - _btdm_bss_end = ABSOLUTE(.); - - /* Buffer for system heap should be placed in dram0_0_seg */ - *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap) - - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - __bss_end = ABSOLUTE(.); - _end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) - - ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), - "DRAM segment data does not fit.") - - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN (8); - *(.noinit) - *(.noinit.*) - . = ALIGN (8); - } GROUP_LINK_IN(RAMABLE_REGION_1) - - _image_irom_start = LOADADDR(.flash.text); - _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; - _image_irom_vaddr = ADDR(.flash.text); - - .flash.text : ALIGN(IROM_SEG_ALIGN) - { - _stext = .; - _text_start = ABSOLUTE(.); - -#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) -#endif - -#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) - *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) - *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif - - *(.literal .text .literal.* .text.*) - . = ALIGN(4); - _text_end = ABSOLUTE(.); - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - resolved by addr2line in preference to the first symbol in - the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - -_heap_sentry = 0x3ffe3f20; - -#include - - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } - -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif - -} - -ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), - "IRAM0 segment data does not fit.") - -#if defined(CONFIG_ESP_SPIRAM) -ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), - "External SPIRAM overflowed.") -#endif /* CONFIG_ESP_SPIRAM */ diff --git a/soc/xtensa/espressif_esp32/esp32/soc.c b/soc/xtensa/espressif_esp32/esp32/soc.c deleted file mode 100644 index 16df3aca645..00000000000 --- a/soc/xtensa/espressif_esp32/esp32/soc.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (c) 2017 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Include esp-idf headers first to avoid redefining BIT() macro */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "esp_private/system_internal.h" -#include "esp32/rom/cache.h" -#include "hal/soc_ll.h" -#include "soc/cpu.h" -#include "soc/gpio_periph.h" -#include "esp_spi_flash.h" -#include "esp_err.h" -#include "esp_timer.h" -#include "esp32/spiram.h" -#include "esp_app_format.h" -#include "hal/wdt_hal.h" - -#ifndef CONFIG_SOC_ESP32_PROCPU -#include "esp_clk_internal.h" -#endif /* CONFIG_SOC_ESP32_PROCPU */ - -#ifdef CONFIG_MCUBOOT -#include "bootloader_init.h" -#endif /* CONFIG_MCUBOOT */ -#include - -extern void z_cstart(void); -extern void esp_reset_reason_init(void); - -#ifdef CONFIG_SOC_ESP32_PROCPU -extern const unsigned char esp32_appcpu_fw_array[]; - -void IRAM_ATTR esp_start_appcpu(void) -{ - esp_image_header_t *header = (esp_image_header_t *)&esp32_appcpu_fw_array[0]; - esp_image_segment_header_t *segment = - (esp_image_segment_header_t *)&esp32_appcpu_fw_array[sizeof(esp_image_header_t)]; - uint8_t *segment_payload; - uint32_t entry_addr = header->entry_addr; - uint32_t idx = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t); - - for (int i = 0; i < header->segment_count; i++) { - segment_payload = (uint8_t *)&esp32_appcpu_fw_array[idx]; - - if (segment->load_addr >= SOC_IRAM_LOW && segment->load_addr < SOC_IRAM_HIGH) { - /* IRAM segment only accepts 4 byte access, avoid memcpy usage here */ - volatile uint32_t *src = (volatile uint32_t *)segment_payload; - volatile uint32_t *dst = (volatile uint32_t *)segment->load_addr; - - for (int j = 0; j < segment->data_len / 4; j++) { - dst[j] = src[j]; - } - } else if (segment->load_addr >= SOC_DRAM_LOW && - segment->load_addr < SOC_DRAM_HIGH) { - - memcpy((void *)segment->load_addr, (const void *)segment_payload, - segment->data_len); - } - - idx += segment->data_len; - segment = (esp_image_segment_header_t *)&esp32_appcpu_fw_array[idx]; - idx += sizeof(esp_image_segment_header_t); - } - - esp_appcpu_start((void *)entry_addr); -} -#endif /* CONFIG_SOC_ESP32_PROCPU */ - -/* - * This is written in C rather than assembly since, during the port bring up, - * Zephyr is being booted by the Espressif bootloader. With it, the C stack - * is already set up. - */ -void __attribute__((section(".iram1"))) __esp_platform_start(void) -{ - extern uint32_t _init_start; - - /* Move the exception vector table to IRAM. */ - __asm__ __volatile__ ( - "wsr %0, vecbase" - : - : "r"(&_init_start)); - - z_bss_zero(); - - __asm__ __volatile__ ( - "" - : - : "g"(&__bss_start) - : "memory"); - - /* Disable normal interrupts. */ - __asm__ __volatile__ ( - "wsr %0, PS" - : - : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); - - /* Initialize the architecture CPU pointer. Some of the - * initialization code wants a valid _current before - * arch_kernel_init() is invoked. - */ - __asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); - - esp_reset_reason_init(); - -#ifdef CONFIG_MCUBOOT - /* MCUboot early initialisation. */ - if (bootloader_init()) { - abort(); - } -#else - /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check - * on startup sequence related issues in application. Hence disable that - * as we are about to start Zephyr environment. - */ - wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; - - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_disable(&rtc_wdt_ctx); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); - -#ifndef CONFIG_SOC_ESP32_PROCPU - /* Configures the CPU clock, RTC slow and fast clocks, and performs - * RTC slow clock calibration. - */ - esp_clk_init(); -#endif - - esp_timer_early_init(); - -#if CONFIG_SOC_ESP32_PROCPU - /* start the ESP32 APP CPU */ - esp_start_appcpu(); -#endif - -#if CONFIG_ESP_SPIRAM - esp_err_t err = esp_spiram_init(); - - if (err != ESP_OK) { - printk("Failed to Initialize SPIRAM, aborting.\n"); - abort(); - } - esp_spiram_init_cache(); - if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { - printk("SPIRAM size is less than configured size, aborting.\n"); - abort(); - } -#endif - -/* Scheduler is not started at this point. Hence, guard functions - * must be initialized after esp_spiram_init_cache which internally - * uses guard functions. Setting guard functions before SPIRAM - * cache initialization will result in a crash. - */ -#if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM - spi_flash_guard_set(&g_flash_guard_default_ops); -#endif - -#endif /* CONFIG_MCUBOOT */ - - esp_intr_initialize(); - - /* Start Zephyr */ - z_cstart(); - - CODE_UNREACHABLE; -} - -/* Boot-time static default printk handler, possibly to be overridden later. */ -int IRAM_ATTR arch_printk_char_out(int c) -{ - if (c == '\n') { - esp_rom_uart_tx_one_char('\r'); - } - esp_rom_uart_tx_one_char(c); - return 0; -} - -void sys_arch_reboot(int type) -{ - esp_restart_noos(); -} - -void IRAM_ATTR esp_restart_noos(void) -{ - /* Disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - const uint32_t core_id = cpu_hal_get_core_id(); - const uint32_t other_core_id = (core_id == 0) ? 1 : 0; - - soc_ll_reset_core(other_core_id); - soc_ll_stall_core(other_core_id); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Read_Disable(0); - Cache_Read_Disable(1); - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, - DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | - DPORT_BT_RST | DPORT_BTMAC_RST | - DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | - DPORT_EMAC_RST | DPORT_MACPWR_RST | - DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); - DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - DPORT_SET_PERI_REG_MASK( - DPORT_PERIP_RST_EN_REG, - /* UART TX FIFO cannot be reset correctly on ESP32, */ - /* so reset the UART memory by DPORT here. */ - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | - DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); - DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); - - /* Clear entry point for APP CPU */ - DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0); - - /* Reset CPUs */ - if (core_id == 0) { - /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ - soc_ll_reset_core(1); - soc_ll_reset_core(0); - } else { - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - } - - while (true) { - ; - } -} diff --git a/soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt deleted file mode 100644 index b9f361d1d5c..00000000000 --- a/soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt +++ /dev/null @@ -1,101 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - soc_cache.c - loader.c - ) - -zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) - -zephyr_library_sources_ifdef(CONFIG_PM power.c) -zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -# get code-partition slot0 address -dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") -dt_reg_addr(img_0_off PATH ${dts_partition_path}) - -# get code-partition boot address -dt_nodelabel(dts_partition_path NODELABEL "boot_partition") -dt_reg_addr(boot_off PATH ${dts_partition_path}) - -# get flash size to use in esptool as string -math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") - -if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") - -endif() - -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py - ARGS --chip esp32s2 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) - endif() - - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - -endif() - -board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") - -board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") - -if(CONFIG_MCUBOOT) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") -else() - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") -endif() diff --git a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig.series b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig.series deleted file mode 100644 index 177c5184e98..00000000000 --- a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig.series +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S2 - -config SOC_SERIES - default "esp32s2" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config MP_MAX_NUM_CPUS - default 1 - -config ISR_STACK_SIZE - default 2048 - -config ESPTOOLPY_FLASHFREQ_80M - default y - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) - -endif # SOC_SERIES_ESP32S2 diff --git a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.series b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.series deleted file mode 100644 index 63a5d3218db..00000000000 --- a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ESP32S2 - bool "ESP32-S2 Series" - select XTENSA - select SOC_FAMILY_ESP32 - select ATOMIC_OPERATIONS_C - select DYNAMIC_INTERRUPTS - select CLOCK_CONTROL - select PINCTRL - select XIP if !MCUBOOT - select HAS_ESPRESSIF_HAL - select ARCH_SUPPORTS_COREDUMP - select HAS_PM - select HAS_POWEROFF - help - Enable support for Espressif ESP32-S2 diff --git a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc deleted file mode 100644 index 85d190d6472..00000000000 --- a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc +++ /dev/null @@ -1,259 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S2 - -config IDF_TARGET_ESP32S2 - bool "ESP32S2 as target SOC" - default y - -config SOC_TOOLCHAIN_NAME - string - default "espressif_esp32s2" - -choice SOC_PART_NUMBER - prompt "ESP32-S2 SOC Selection" - depends on SOC_SERIES_ESP32S2 - - # SoC with/without embedded flash - config SOC_ESP32S2 - bool "ESP32S2" - config SOC_ESP32S2_R2 - bool "ESP32S2_R2" - config SOC_ESP32S2_FH2 - bool "ESP32S2_FH2" - config SOC_ESP32S2_FH4 - bool "ESP32S2_FH4" - config SOC_ESP32S2_FN4R2 - bool "ESP32S2_FN4R2" - # SiP with external flash / psram - config SOC_ESP32S2_SOLO_N4 - bool "ESP32S2_SOLO_N4" - config SOC_ESP32S2_SOLO_N8 - bool "ESP32S2_SOLO_N8" - config SOC_ESP32S2_SOLO_N16 - bool "ESP32S2_SOLO_N16" - config SOC_ESP32S2_SOLO_N4R2 - bool "ESP32S2_SOLO_N4R2" - config SOC_ESP32S2_MINI_N4 - bool "ESP32S2_MINI_N4" - config SOC_ESP32S2_MINI_N4R2 - bool "ESP32S2_MINI_N4R2" - config SOC_ESP32S2_WROOM - bool "ESP32S2_WROOM" - config SOC_ESP32S2_WROVER_N4R2 - bool "ESP32S2_WROVER_N4R2" - config SOC_ESP32S2_WROVER_N8R2 - bool "ESP32S2_WROVER_N8R2" - config SOC_ESP32S2_WROVER_N16R2 - bool "ESP32S2_WROVER_N16R2" - -endchoice # SOC_PART_NUMBER - -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - -choice ESP32S2_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32S2_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - - "Internal 90kHz oscillator" option provides lowest deep sleep current - consumption, and does not require extra external components. However - frequency stability with respect to temperature is poor, so time may - drift in deep/light sleep modes. - - "External 32kHz crystal" provides better frequency stability, at the - expense of slightly higher (1uA) deep sleep current consumption. - - "External 32kHz oscillator" allows using 32kHz clock generated by an - external circuit. In this case, external clock signal must be connected - to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, - and <1V in case of square wave signal. Common mode voltage should be - 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. - Additionally, 1nF capacitor must be connected between 32K_XP pin and - ground. 32K_XP pin can not be used as a GPIO in this case. - - "Internal 8MHz oscillator divided by 256" option results in higher - deep sleep current (by 5uA) but has better frequency stability than - the internal 90kHz oscillator. It does not require external components. - -config ESP32S2_RTC_CLK_SRC_INT_RC - bool "Internal 90kHz RC oscillator" - -config ESP32S2_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32S2_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XN pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32S2_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" - -endchoice - -config ESP32S2_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS || ESP32S2_RTC_CLK_SRC_EXT_OSC || ESP32S2_RTC_CLK_SRC_INT_8MD256 - default 576 if ESP32S2_RTC_CLK_SRC_INT_RC - range 0 125000 - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -menu "Cache config" - -choice - prompt "Instruction cache line size" - default ESP32S2_INSTRUCTION_CACHE_LINE_32B - - config ESP32S2_INSTRUCTION_CACHE_LINE_16B - bool "16 Bytes" - - config ESP32S2_INSTRUCTION_CACHE_LINE_32B - bool "32 Bytes" - -endchoice - -choice - prompt "Instruction cache size" - default ESP32S2_INSTRUCTION_CACHE_8KB - - config ESP32S2_INSTRUCTION_CACHE_8KB - bool "8KB instruction cache size" - - config ESP32S2_INSTRUCTION_CACHE_16KB - bool "16KB instruction cache size" - -endchoice - -choice - prompt "Data cache size" - default ESP32S2_DATA_CACHE_0KB if !ESP_SPIRAM - default ESP32S2_DATA_CACHE_8KB if ESP_SPIRAM - - config ESP32S2_DATA_CACHE_0KB - bool "0KB data cache size" - - config ESP32S2_DATA_CACHE_8KB - bool "8KB data cache size" - - config ESP32S2_DATA_CACHE_16KB - bool "16KB data cache size" - -endchoice - -choice - prompt "Data cache line size" - default ESP32S2_DATA_CACHE_LINE_32B - - config ESP32S2_DATA_CACHE_LINE_16B - bool "16 Bytes" - - config ESP32S2_DATA_CACHE_LINE_32B - bool "32 Bytes" - -endchoice - -config ESP32S2_INSTRUCTION_CACHE_SIZE - hex - default 0x4000 if ESP32S2_INSTRUCTION_CACHE_16KB - default 0x2000 - -config ESP32S2_DATA_CACHE_SIZE - hex - default 0x2000 if ESP32S2_DATA_CACHE_8KB - default 0x4000 if ESP32S2_DATA_CACHE_16KB - default 0x0000 - -endmenu # Cache config - -menu "PSRAM clock and cs IO for ESP32-S2" - depends on ESP_SPIRAM - -config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config - it based on hardware design. - -config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, user can config it - based on hardware design. - -endmenu # PSRAM clock and cs IO for ESP32S2 - -choice ESP32S2_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is two, - all interfaces (WiFi station, WiFi softap) receive a universally administered MAC - address. - They are generated sequentially by adding 0, and 1 (respectively) to the final octet of - the base MAC address. If the number of universal MAC addresses is one, only WiFi station - receives a universally administered MAC address. - The WiFi softap receives local MAC addresses. It's derived from the universal WiFi - station MAC addresses. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 1 or 2 per device). - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE - bool "One" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - -endchoice # ESP32S2_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES - int - default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE - default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - -config ESP32_PHY_MAX_WIFI_TX_POWER - int "Max WiFi TX power (dBm)" - range 10 20 - default 20 - help - Set maximum transmit power for WiFi radio. Actual transmit power for high - data rates may be lower than this setting. - -config ESP32_PHY_MAX_TX_POWER - int - default ESP32_PHY_MAX_WIFI_TX_POWER - -endif # SOC_SERIES_ESP32S2 diff --git a/soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt deleted file mode 100644 index cb5291614bc..00000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt +++ /dev/null @@ -1,122 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if (CONFIG_SOC_ESP32S3_APPCPU) - zephyr_sources(soc_appcpu.c) -else() - zephyr_sources( - soc.c - soc_cache.c - loader.c - esp32s3-mp.c - ) -endif() - -zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) - -# get flash size to use in esptool as string -math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") - -if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") - -endif() - -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py - ARGS --chip esp32s3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) - endif() - - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - -endif() - -## When building for APPCPU -if (CONFIG_SOC_ESP32S3_APPCPU) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py - ARGS -i ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c - -a "esp32s3_appcpu_fw_array") - endif() - -else() - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - # get code-partition slot0 address - dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") - dt_reg_addr(img_0_off PATH ${dts_partition_path}) - - # get code-partition boot address - dt_nodelabel(dts_partition_path NODELABEL "boot_partition") - dt_reg_addr(boot_off PATH ${dts_partition_path}) - - board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") - - board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") - -endif() - -if(CONFIG_MCUBOOT) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") -elseif(CONFIG_SOC_ESP32S3_APPCPU) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "") -else() - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") -endif() diff --git a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig.series b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig.series deleted file mode 100644 index 30d0480cad2..00000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S3 - -config SOC_SERIES - default "esp32s3" - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config ESPTOOLPY_FLASHFREQ_80M - default y - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) - -endif # SOC_SERIES_ESP32S3 diff --git a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.series b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.series deleted file mode 100644 index 6f5fcf88c17..00000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.series +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ESP32S3 - bool "ESP32-S3 Series" - select XTENSA - select SOC_FAMILY_ESP32 - select DYNAMIC_INTERRUPTS - select ARCH_SUPPORTS_COREDUMP - select CLOCK_CONTROL - select PINCTRL - select XIP if !MCUBOOT - select HAS_ESPRESSIF_HAL - select CPU_HAS_FPU - -config SOC_ESP32S3_PROCPU - bool "Application runs in ESP32S3 PROCPU (core 0)" - depends on SOC_SERIES_ESP32S3 - help - When this SOC is enabled, it will run application on PROCPU (core 0). It will automatically - enable AMP support by building, flashing and loading APPCPU (core 1) image if exists. - -config SOC_ESP32S3_APPCPU - bool "Application runs in ESP32S3 APPCPU (core 1)" - depends on SOC_SERIES_ESP32S3 - help - When this SOC is enabled, it will run application on APPCPU (core 1). It is expected that - there is another image running on PROCPU (core 0) to trigger the AMP support. diff --git a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc deleted file mode 100644 index ad8b4b4234b..00000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc +++ /dev/null @@ -1,332 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S3 - -config IDF_TARGET_ESP32S3 - bool "ESP32S3 as target SOC" - default y - -config SOC_TOOLCHAIN_NAME - string - default "espressif_esp32s3" - -choice SOC_PART_NUMBER - prompt "ESP32-S3 SOC Selection" - - # SoC with/without embedded flash - config SOC_ESP32S3_R2 - bool "ESP32S3_R2" - config SOC_ESP32S3_R8 - bool "ESP32S3_R8" - config SOC_ESP32S3_R8V - bool "ESP32S3_R8V" - config SOC_ESP32S3_FN8 - bool "ESP32S3_FN8" - config SOC_ESP32S3_PICO_N8R2 - bool "ESP32S3_PICO_N8R2" - config SOC_ESP32S3_PICO_N8R8 - bool "ESP32S3_PICO_N8R8" - # SiP with flash and/or psram - config SOC_ESP32S3_MINI_N8 - bool "ESP32S3_MINI_N8" - config SOC_ESP32S3_MINI_N4R2 - bool "ESP32S3_MINI_N4R2" - config SOC_ESP32S3_WROOM_N4 - bool "ESP32S3_WROOM_N4" - config SOC_ESP32S3_WROOM_N8 - bool "ESP32S3_WROOM_N8" - config SOC_ESP32S3_WROOM_N16 - bool "ESP32S3_WROOM_N16" - config SOC_ESP32S3_WROOM_N4R8 - bool "ESP32S3_WROOM_N4R8" - config SOC_ESP32S3_WROOM_N8R8 - bool "ESP32S3_WROOM_N8R8" - config SOC_ESP32S3_WROOM_N16R8 - bool "ESP32S3_WROOM_N16R8" - config SOC_ESP32S3_WROOM_N4R2 - bool "ESP32S3_WROOM_N4R2" - config SOC_ESP32S3_WROOM_N8R2 - bool "ESP32S3_WROOM_N8R2" - config SOC_ESP32S3_WROOM_N16R2 - bool "ESP32S3_WROOM_N16R2" - -endchoice # SOC_PART_NUMBER - -config ESP32S3_APPCPU_IRAM - hex "ESP32S3 APPCPU IRAM size" - depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU - default 0x20000 - help - Defines APPCPU IRAM area in bytes. - -config ESP32S3_APPCPU_DRAM - hex "ESP32S3 APPCPU DRAM size" - depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU - default 0x10000 - help - Defines APPCPU DRAM area in bytes. - -choice ESP32S3_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32S3_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - config ESP32S3_RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - config ESP32S3_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - config ESP32S3_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XP pin" - select ESP_SYSTEM_RTC_EXT_OSC - config ESP32S3_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" -endchoice - -config ESP32S3_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32S3_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32S3_RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -choice ESP32_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is four, - all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally - administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) - to the final octet of the base MAC address. If the number of universal MAC addresses is two, - only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. - These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. - The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. - These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 2 or 4 per device.) - -config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_BT - -config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - bool "Four" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - select ESP_MAC_ADDR_UNIVERSE_BT - select ESP_MAC_ADDR_UNIVERSE_ETH - -endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP_MAC_ADDR_UNIVERSE_BT - bool - -config ESP_MAC_ADDR_UNIVERSE_ETH - bool - -config ESP32_UNIVERSAL_MAC_ADDRESSES - int - default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - -config ESP32_PHY_MAX_WIFI_TX_POWER - int "Max WiFi/BLE TX power (dBm)" - range 10 20 - default 20 - help - Set maximum transmit power for WiFi radio. Actual transmit power for high - data rates may be lower than this setting. - -config ESP32_PHY_MAX_TX_POWER - int - default ESP32_PHY_MAX_WIFI_TX_POWER - -menu "Cache config" - -choice ESP32S3_INSTRUCTION_CACHE_SIZE - prompt "Instruction cache size" - default ESP32S3_INSTRUCTION_CACHE_16KB - help - Instruction cache size to be set on application startup. - If you use 16KB instruction cache rather than 32KB instruction cache, - then the other 16KB will be managed by heap allocator. - - config ESP32S3_INSTRUCTION_CACHE_16KB - bool "16KB" - config ESP32S3_INSTRUCTION_CACHE_32KB - bool "32KB" -endchoice - -config ESP32S3_INSTRUCTION_CACHE_SIZE - hex - default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB - default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB - -choice ESP32S3_ICACHE_ASSOCIATED_WAYS - prompt "Instruction cache associated ways" - default ESP32S3_INSTRUCTION_CACHE_8WAYS - help - Instruction cache associated ways to be set on application startup. - - config ESP32S3_INSTRUCTION_CACHE_4WAYS - bool "4 ways" - config ESP32S3_INSTRUCTION_CACHE_8WAYS - bool "8 ways" -endchoice - -config ESP32S3_ICACHE_ASSOCIATED_WAYS - int - default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS - default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS - -choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE - prompt "Instruction cache line size" - default ESP32S3_INSTRUCTION_CACHE_LINE_32B - help - Instruction cache line size to be set on application startup. - - config ESP32S3_INSTRUCTION_CACHE_LINE_16B - bool "16 Bytes" - depends on ESP32S3_INSTRUCTION_CACHE_16KB - config ESP32S3_INSTRUCTION_CACHE_LINE_32B - bool "32 Bytes" -endchoice - -config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE - int - default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B - default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B - -config ESP32S3_INSTRUCTION_CACHE_WRAP - bool "Define instruction cache wrap mode" - help - If enabled, instruction cache will use wrap mode to read spi flash or spi ram. - The wrap length equals to ESP32S3_INSTRUCTION_CACHE_LINE_SIZE. - However, it depends on complex conditions. - -choice ESP32S3_DATA_CACHE_SIZE - prompt "Data cache size" - default ESP32S3_DATA_CACHE_32KB - help - Data cache size to be set on application startup. - If you use 32KB data cache rather than 64KB data cache, - the other 32KB will be added to the heap. - - config ESP32S3_DATA_CACHE_16KB - bool "16KB" - config ESP32S3_DATA_CACHE_32KB - bool "32KB" - config ESP32S3_DATA_CACHE_64KB - bool "64KB" -endchoice - -config ESP32S3_DATA_CACHE_SIZE - hex - # For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup - default 0x8000 if ESP32S3_DATA_CACHE_16KB - default 0x8000 if ESP32S3_DATA_CACHE_32KB - default 0x10000 if ESP32S3_DATA_CACHE_64KB - -choice ESP32S3_DCACHE_ASSOCIATED_WAYS - prompt "Data cache associated ways" - default ESP32S3_DATA_CACHE_8WAYS - help - Data cache associated ways to be set on application startup. - - config ESP32S3_DATA_CACHE_4WAYS - bool "4 ways" - config ESP32S3_DATA_CACHE_8WAYS - bool "8 ways" -endchoice - -config ESP32S3_DCACHE_ASSOCIATED_WAYS - int - default 4 if ESP32S3_DATA_CACHE_4WAYS - default 8 if ESP32S3_DATA_CACHE_8WAYS - -choice ESP32S3_DATA_CACHE_LINE_SIZE - prompt "Data cache line size" - default ESP32S3_DATA_CACHE_LINE_32B - help - Data cache line size to be set on application startup. - - config ESP32S3_DATA_CACHE_LINE_16B - bool "16 Bytes" - depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB - config ESP32S3_DATA_CACHE_LINE_32B - bool "32 Bytes" - config ESP32S3_DATA_CACHE_LINE_64B - bool "64 Bytes" -endchoice - -config ESP32S3_DATA_CACHE_LINE_SIZE - int - default 16 if ESP32S3_DATA_CACHE_LINE_16B - default 32 if ESP32S3_DATA_CACHE_LINE_32B - default 64 if ESP32S3_DATA_CACHE_LINE_64B - -config ESP32S3_DATA_CACHE_WRAP - bool "Define data cache wrap mode" - help - If enabled, data cache will use wrap mode to read spi flash or spi ram. - The wrap length equals to ESP32S3_DATA_CACHE_LINE_SIZE. - However, it depends on complex conditions. - -config MAC_BB_PD - bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled" - depends on SOC_SERIES_ESP32S3 && TICKLESS_KERNEL - default n - help - If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered - down when PHY is disabled. Enabling this setting reduces power consumption - by a small amount but increases RAM use by approximat - -endmenu # Cache config - -menu "PSRAM Clock and CS IO for ESP32S3" - depends on ESP_SPIRAM - -config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design. - -config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, please refer to your hardware design. - -endmenu # PSRAM clock and cs IO for ESP32S3 - -endif # SOC_SERIES_ESP32S3 diff --git a/soc/xtensa/espressif_esp32/esp32s3/default.ld b/soc/xtensa/espressif_esp32/esp32s3/default.ld deleted file mode 100644 index 4076ea7c1af..00000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/default.ld +++ /dev/null @@ -1,693 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the ESP32S3 platform. - */ - -#include -#include -#include -#include - -#define SRAM_IRAM_START 0x40370000 -#define SRAM_DIRAM_I_START 0x40378000 -/* SRAM_IRAM_END is equivalent 2nd stage bootloader iram_loader_seg - start address (that should not be overlapped) */ -#define SRAM_IRAM_END 0x403BA000 -#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START) - -#define SRAM_DRAM_START 0x3FC88000 -#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET) -#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START) - -#define ICACHE_SIZE 0x8000 -#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) -#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) - -#define DCACHE_SIZE 0x10000 -#define SRAM_DRAM_ORG (SRAM_DRAM_START) - -#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE - -#define FLASH_CODE_REGION irom0_0_seg -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define RAMABLE_REGION dram0_0_seg -#define ROMABLE_REGION ROM - -#define EXT_RAM_ORG (0x3E000000 - CONFIG_ESP_SPIRAM_SIZE) - -#ifdef CONFIG_FLASH_SIZE -#define FLASH_SIZE CONFIG_FLASH_SIZE -#else -#define FLASH_SIZE 0x800000 -#endif - -#ifdef CONFIG_BOOTLOADER_ESP_IDF -#define IROM_SEG_ORG 0x42000020 -#define IROM_SEG_LEN FLASH_SIZE-0x20 -#else -#define IROM_SEG_ORG 0x42000000 -#define IROM_SEG_LEN FLASH_SIZE -#endif - -#ifdef CONFIG_SOC_ESP32S3_PROCPU -#define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM -#define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM -#else -#define APPCPU_IRAM_SIZE 0x0 -#define APPCPU_DRAM_SIZE 0x0 -#endif - -#define IROM_SEG_ALIGN 0x10000 - -/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. - * Executing directly from LMA is not possible. */ -#undef GROUP_ROM_LINK_IN -#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion - -MEMORY -{ - mcuboot_hdr (RX): org = 0x0, len = 0x20 - metadata (RX): org = 0x20, len = 0x20 - ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 - iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE - APPCPU_IRAM_SIZE - dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN - APPCPU_DRAM_SIZE - - irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - - /* DROM is the first segment placed in generated binary. - * MCUboot binary for ESP32 has image header of 0x20 bytes. - * Additional load header of 0x20 bytes are appended to the image. - * Hence, an offset of 0x40 is added to DROM segment origin. - */ - drom0_0_seg(R): org = 0x3C000040, len = FLASH_SIZE - 0x40 - /** - * `extern_ram_seg` and `drom0_0_seg` share the same bus and the address region. - * so we allocate `extern_ram_seg` at the end of the address region. - */ -#if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RWX): org = EXT_RAM_ORG, len = CONFIG_ESP_SPIRAM_SIZE -#endif - - /* RTC fast memory (executable). Persists over deep sleep. - */ - rtc_iram_seg(RWX): org = 0x600fe000, len = 0x2000 - - /* RTC fast memory (same block as above), viewed from data bus - */ - rtc_data_seg(RW): org = 0x600fe000, len = 0x2000 - - /* RTC slow memory (data accessible). Persists over deep sleep. - */ - rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 - -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 -#endif -} - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -SECTIONS -{ - /* Reserve space for MCUboot header in the binary */ - .mcuboot_header : - { - QUAD(0x0) - QUAD(0x0) - QUAD(0x0) - QUAD(0x0) - } > mcuboot_hdr - .metadata : - { - /* Magic byte for load header */ - LONG(0xace637d3) - - /* Application entry point address */ - KEEP(*(.entry_addr)) - - /* IRAM metadata: - * - Destination address (VMA) for IRAM region - * - Flash offset (LMA) for start of IRAM region - * - Size of IRAM region - */ - LONG(ADDR(.iram0.vectors)) - LONG(LOADADDR(.iram0.vectors)) - LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors)) - - /* DRAM metadata: - * - Destination address (VMA) for DRAM region - * - Flash offset (LMA) for start of DRAM region - * - Size of DRAM region - */ - LONG(ADDR(.dram0.data)) - LONG(LOADADDR(.dram0.data)) - LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) - } > metadata - - #include - - _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); - _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; - _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); - - /* NOTE: .rodata section should be the first section in the linker script and no - * other section should appear before .rodata section. This is the requirement - * to align ROM section to 64K page offset. - * Adding .rodata as first section helps to reduce size of generated binary by - * few kBs. - */ - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(0x10)) - { - _rodata_reserved_start = ABSOLUTE(.); - _rodata_start = ABSOLUTE(.); - - *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - - __rodata_region_start = ABSOLUTE(.); - . = ALIGN(4); - #include - - . = ALIGN(4); - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata) - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata.*) - - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; - - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); - __rodata_region_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - *(.rodata_wlog) - *(.rodata_wlog*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - #include - #include - #include - #include - - /* Create an explicit section at the end of all the data that shall be mapped into drom. - * This is used to calculate the size of the _image_drom_size variable */ - SECTION_PROLOGUE(_RODATA_SECTION_END,,ALIGN(0x10)) - { - _rodata_reserved_end = ABSOLUTE(.); - . = ALIGN(16); - _image_rodata_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - -#if defined(CONFIG_ESP_SPIRAM) - /* This section holds .ext_ram.bss data, and will be put in PSRAM */ - .ext_ram.bss (NOLOAD) : - { - _ext_ram_data_start = ABSOLUTE(.); - _ext_ram_bss_start = ABSOLUTE(.); - *(.ext_ram.bss*) - . = ALIGN(4); - _ext_ram_bss_end = ABSOLUTE(.); - } > ext_ram_seg - - .ext_ram_noinit (NOLOAD) : - { -#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) - *libdrivers__wifi.a:(.noinit .noinit.*) - *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) - *libsubsys__net__lib__config.a:(.noinit .noinit.*) - *libsubsys__net__ip.a:(.noinit .noinit.*) - *libsubsys__net.a:(.noinit .noinit.*) -#endif - _spiram_heap_start = ABSOLUTE(.); - . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; - - _ext_ram_data_end = ABSOLUTE(.); - } > ext_ram_seg -#endif - - /* Send .iram0 code to iram */ - .iram0.vectors : ALIGN(4) - { - _iram_start = ABSOLUTE(.); - /* Vectors go to IRAM */ - _init_start = ABSOLUTE(.); - /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ - . = 0x0; - KEEP(*(.WindowVectors.text)); - . = 0x180; - KEEP(*(.Level2InterruptVector.text)); - . = 0x1c0; - KEEP(*(.Level3InterruptVector.text)); - . = 0x200; - KEEP(*(.Level4InterruptVector.text)); - . = 0x240; - KEEP(*(.Level5InterruptVector.text)); - . = 0x280; - KEEP(*(.DebugExceptionVector.text)); - . = 0x2c0; - KEEP(*(.NMIExceptionVector.text)); - . = 0x300; - KEEP(*(.KernelExceptionVector.text)); - . = 0x340; - KEEP(*(.UserExceptionVector.text)); - . = 0x3C0; - KEEP(*(.DoubleExceptionVector.text)); - . = 0x400; - _invalid_pc_placeholder = ABSOLUTE(.); - *(.*Vector.literal) - - *(.UserEnter.literal); - *(.UserEnter.text); - . = ALIGN (16); - *(.entry.text) - *(.init.literal) - *(.init) - _init_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram0.text : ALIGN(4) - { - /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); - *(.iram1 .iram1.*) - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - *libesp32.a:panic.*(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) - *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) - *libkernel.a:(.literal .text .literal.* .text.*) - *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) - *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) - *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) - *libzephyr.a:spiram*.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_timing*.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_flash*.*(.literal .text .literal.* .text.*) - *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) - *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) - *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) - *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) - *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) - *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) - *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) - *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) - *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) - *libzephyr.a:loader.*(.literal .text .literal.* .text.*) - *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) - *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) - *libc.a:*(.literal .text .literal.* .text.*) - *libphy.a:(.phyiram .phyiram.*) - *libgcov.a:(.literal .text .literal.* .text.*) - -#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) -#endif - -#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) - *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) - *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif - - . = ALIGN(4) + 16; - - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - /* Marks the end of IRAM code segment */ - .iram0.text_end (NOLOAD) : - { - /* ESP32-S3 memprot requires 16B padding for possible CPU - * prefetch and 256B alignment for PMS split lines */ - . = ALIGN(16); - _iram_text_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - .iram0.data : - { - . = ALIGN(16); - *(.iram.data) - *(.iram.data*) - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram0.bss (NOLOAD) : - { - . = ALIGN(16); - *(.iram.bss) - *(.iram.bss*) - - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - - /* This section is required to skip .iram0.text area because iram0_0_seg and - * dram0_0_seg reflect the same address space on different buses. - */ - .dram0.dummy (NOLOAD): - { - . = ALIGN (8); - . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM_DIRAM_I_START) - SRAM_DIRAM_I_START; - } GROUP_LINK_IN(RAMABLE_REGION) - - /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); /* required by bluetooth library */ - __bss_start = ABSOLUTE(.); - - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - __bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) - - ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") - - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN(8); - *(.noinit) - *(.noinit.*) - . = ALIGN(8) ; - } GROUP_LINK_IN(RAMABLE_REGION) - - .dram0.data : - { - . = ALIGN (8); - __data_start = ABSOLUTE(.); - - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - /* rodata for panic handler(libarch__xtensa__core.a) and all - * dependent functions should be placed in DRAM to avoid issue - * when flash cache is disabled */ - *libarch__xtensa__core.a:(.rodata .rodata.*) - *libkernel.a:fatal.*(.rodata .rodata.*) - *libkernel.a:init.*(.rodata .rodata.*) - *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) - *libzephyr.a:systimer_hal.*(.rodata .rodata.*) - *libzephyr.a:log_core.*(.rodata .rodata.*) - *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) - *libzephyr.a:log_output.*(.rodata .rodata.*) - *libzephyr.a:loader.*(.rodata .rodata.*) - *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) - - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - - /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ - #pragma push_macro("GROUP_ROM_LINK_IN") - #undef GROUP_ROM_LINK_IN - #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN - #include - #pragma pop_macro("GROUP_ROM_LINK_IN") - - .dram0.end : - { - . = ALIGN(4); - - #include - - . = ALIGN(4); - _end = ABSOLUTE(.); - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - _image_irom_start = LOADADDR(.flash.text); - _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; - _image_irom_vaddr = ADDR(.flash.text); - - .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN) - { - . = SIZEOF(_RODATA_SECTION_NAME); - . = ALIGN(IROM_SEG_ALIGN) + 0x20; - } GROUP_LINK_IN(FLASH_CODE_REGION) - - .flash.text : ALIGN(IROM_SEG_ALIGN) - { - _stext = .; - _text_start = ABSOLUTE(.); - -#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) -#endif - -#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) - *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) - *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif - - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - *(.literal .text .literal.* .text.*) - - /* CPU will try to prefetch up to 16 bytes of - * of instructions. This means that any configuration (e.g. MMU, PMS) must allow - * safe access to up to 16 bytes after the last real instruction, add - * dummy bytes to ensure this - */ - . += 16; - - _text_end = ABSOLUTE(.); - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - - /* RTC fast memory holds RTC wake stub code, - * including from any source file named rtc_wake_stub*.c - */ - .rtc.text : - { - . = ALIGN(4); - _rtc_text_start = ABSOLUTE(.); - *(.rtc.literal .rtc.text) - *(.rtc.entry.text) - *rtc_wake_stub*.*(.literal .text .literal.* .text.*) - _rtc_text_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - - /* This section is required to skip rtc.text area because rtc_iram_seg and - * rtc_data_seg are reflect the same address space on different buses. - */ - .rtc.dummy : - { - _rtc_dummy_start = ABSOLUTE(.); - _rtc_fast_start = ABSOLUTE(.); - . = SIZEOF(.rtc.text); - _rtc_dummy_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) - - /* This section located in RTC FAST Memory area. - * It holds data marked with RTC_FAST_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_fast : - { - . = ALIGN(4); - _rtc_force_fast_start = ABSOLUTE(.); - - *(.rtc.force_fast .rtc.force_fast.*) - . = ALIGN(4) ; - _rtc_force_fast_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) - - /* RTC data section holds RTC wake stub - * data/rodata, including from any source file - * named rtc_wake_stub*.c and the data marked with - * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. - */ - .rtc.data : - { - _rtc_data_start = ABSOLUTE(.); - *(.rtc.data) - *(.rtc.rodata) - *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) - _rtc_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.*(.bss .bss.*) - *rtc_wake_stub*.*(COMMON) - - *(.rtc.data) - *(.rtc.rodata) - - _rtc_bss_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.*(.bss .bss.*) - *rtc_wake_stub*.*(COMMON) - - _rtc_bss_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* This section holds data that should not be initialized at power up - * and will be retained during deep sleep. - * User data marked with RTC_NOINIT_ATTR will be placed - * into this section. See the file "esp_attr.h" for more information. - */ - .rtc_noinit (NOLOAD): - { - . = ALIGN(4); - _rtc_noinit_start = ABSOLUTE(.); - *(.rtc_noinit .rtc_noinit.*) - . = ALIGN(4) ; - _rtc_noinit_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* This section located in RTC SLOW Memory area. - * It holds data marked with RTC_SLOW_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : - { - . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* Get size of rtc slow data based on rtc_data_location alias */ - _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); - _rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start); - - ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") - ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") - -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif - -_heap_sentry = 0x3fceb910; - -#include - - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } - -} - -ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), - "IRAM0 segment data does not fit.") - -#if defined(CONFIG_ESP_SPIRAM) -ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), - "External SPIRAM overflowed.") -#endif /* CONFIG_ESP_SPIRAM */ diff --git a/soc/xtensa/espressif_esp32/esp32s3/soc.c b/soc/xtensa/espressif_esp32/esp32s3/soc.c deleted file mode 100644 index d250657c49e..00000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/soc.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2017 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Include esp-idf headers first to avoid redefining BIT() macro */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "esp_private/system_internal.h" -#include "esp32s3/rom/cache.h" -#include "esp32s3/rom/rtc.h" -#include "soc/syscon_reg.h" -#include "hal/soc_ll.h" -#include "hal/wdt_hal.h" -#include "soc/cpu.h" -#include "soc/gpio_periph.h" -#include "esp_spi_flash.h" -#include "esp_err.h" -#include "esp_timer.h" -#include "esp_app_format.h" -#include "esp_clk_internal.h" - -#include "esp32s3/spiram.h" - -#ifdef CONFIG_MCUBOOT -#include "bootloader_init.h" -#endif /* CONFIG_MCUBOOT */ -#include - -#if CONFIG_ESP_SPIRAM -extern int _ext_ram_bss_start; -extern int _ext_ram_bss_end; -#endif - -extern void z_cstart(void); -extern void esp_reset_reason_init(void); - -#ifdef CONFIG_SOC_ESP32S3_PROCPU -extern const unsigned char esp32s3_appcpu_fw_array[]; - -void IRAM_ATTR esp_start_appcpu(void) -{ - esp_image_header_t *header = (esp_image_header_t *)&esp32s3_appcpu_fw_array[0]; - esp_image_segment_header_t *segment = - (esp_image_segment_header_t *)&esp32s3_appcpu_fw_array[sizeof(esp_image_header_t)]; - uint8_t *segment_payload; - uint32_t entry_addr = header->entry_addr; - uint32_t idx = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t); - - for (int i = 0; i < header->segment_count; i++) { - segment_payload = (uint8_t *)&esp32s3_appcpu_fw_array[idx]; - - if (segment->load_addr >= SOC_IRAM_LOW && segment->load_addr < SOC_IRAM_HIGH) { - /* IRAM segment only accepts 4 byte access, avoid memcpy usage here */ - volatile uint32_t *src = (volatile uint32_t *)segment_payload; - volatile uint32_t *dst = (volatile uint32_t *)segment->load_addr; - - for (int i = 0; i < segment->data_len / 4; i++) { - dst[i] = src[i]; - } - - } else if (segment->load_addr >= SOC_DRAM_LOW && - segment->load_addr < SOC_DRAM_HIGH) { - memcpy((void *)segment->load_addr, (const void *)segment_payload, - segment->data_len); - } - - idx += segment->data_len; - segment = (esp_image_segment_header_t *)&esp32s3_appcpu_fw_array[idx]; - idx += sizeof(esp_image_segment_header_t); - } - - esp_appcpu_start((void *)entry_addr); -} -#endif /* CONFIG_SOC_ESP32S3_PROCPU*/ - -#ifndef CONFIG_MCUBOOT -/* - * This function is a container for SoC patches - * that needs to be applied during the startup. - */ -static void IRAM_ATTR esp_errata(void) -{ - /* Handle the clock gating fix */ - REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); - /* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING - * signals to ensure that the App core stops running in single-core mode. - */ - REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL); - REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); - - /* Handle the Dcache case following the IDF startup code */ -#if CONFIG_ESP32S3_DATA_CACHE_16KB - Cache_Invalidate_DCache_All(); - Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000); -#endif -} -#endif /* CONFIG_MCUBOOT */ - -/* - * This is written in C rather than assembly since, during the port bring up, - * Zephyr is being booted by the Espressif bootloader. With it, the C stack - * is already set up. - */ -void IRAM_ATTR __esp_platform_start(void) -{ - extern uint32_t _init_start; - - /* Move the exception vector table to IRAM. */ - __asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start)); - - z_bss_zero(); - - /* Disable normal interrupts. */ - __asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); - - /* Initialize the architecture CPU pointer. Some of the - * initialization code wants a valid _current before - * arch_kernel_init() is invoked. - */ - __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); - -#ifdef CONFIG_MCUBOOT - /* MCUboot early initialisation. */ - if (bootloader_init()) { - abort(); - } -#else - /* Configure the mode of instruction cache : cache size, cache line size. */ - esp_config_instruction_cache_mode(); - - /* If we need use SPIRAM, we should use data cache. - * Configure the mode of data : cache size, cache line size. - */ - esp_config_data_cache_mode(); - - /* Apply SoC patches */ - esp_errata(); - -#if CONFIG_ESP_SPIRAM - esp_err_t err = esp_spiram_init(); - - if (err != ESP_OK) { - printk("Failed to Initialize external RAM, aborting.\n"); - abort(); - } - - esp_spiram_init_cache(); - if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { - printk("External RAM size is less than configured, aborting.\n"); - abort(); - } - - if (!esp_spiram_test()) { - printk("External RAM failed memory test!\n"); - abort(); - } - - memset(&_ext_ram_bss_start, 0, - (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); - -#endif /* CONFIG_ESP_SPIRAM */ - - /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence - * related issues in application. Hence disable that as we are about to start - * Zephyr environment. - */ - wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; - - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_disable(&rtc_wdt_ctx); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); - - esp_reset_reason_init(); - - esp_clk_init(); - - esp_timer_early_init(); - -#if CONFIG_SOC_ESP32S3_PROCPU - /* start the ESP32S3 APP CPU */ - esp_start_appcpu(); -#endif - -#if CONFIG_SOC_FLASH_ESP32 - spi_flash_guard_set(&g_flash_guard_default_ops); -#endif -#endif /* CONFIG_MCUBOOT */ - - esp_intr_initialize(); - - /* Start Zephyr */ - z_cstart(); - - CODE_UNREACHABLE; -} - -/* Boot-time static default printk handler, possibly to be overridden later. */ -int IRAM_ATTR arch_printk_char_out(int c) -{ - if (c == '\n') { - esp_rom_uart_tx_one_char('\r'); - } - esp_rom_uart_tx_one_char(c); - return 0; -} - -void sys_arch_reboot(int type) -{ - esp_restart_noos(); -} - -void IRAM_ATTR esp_restart_noos(void) -{ - /* disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - /* enable RTC watchdog for 1 second */ - wdt_hal_context_t wdt_ctx; - uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); - - wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false); - wdt_hal_write_protect_disable(&wdt_ctx); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - - /* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */ - wdt_hal_set_flashboot_en(&wdt_ctx, true); - wdt_hal_write_protect_enable(&wdt_ctx); - - /* disable TG0/TG1 watchdogs */ - wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; - - wdt_hal_write_protect_disable(&wdt0_context); - wdt_hal_disable(&wdt0_context); - wdt_hal_write_protect_enable(&wdt0_context); - - wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; - - wdt_hal_write_protect_disable(&wdt1_context); - wdt_hal_disable(&wdt1_context); - wdt_hal_write_protect_enable(&wdt1_context); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Disable_ICache(); - Cache_Disable_DCache(); - - const uint32_t core_id = cpu_hal_get_core_id(); -#if CONFIG_SMP - const uint32_t other_core_id = (core_id == 0) ? 1 : 0; - - soc_ll_reset_core(other_core_id); - soc_ll_stall_core(other_core_id); -#endif - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, - SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST | - SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_SDIO_HOST_RST | - SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | - SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST); - REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | - SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - - /* Reset DMA */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - - SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - - rtc_clk_cpu_freq_set_xtal(); - - /* Reset CPUs */ - if (core_id == 0) { - /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ - soc_ll_reset_core(1); - soc_ll_reset_core(0); - } else { - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - } - - while (true) { - ; - } -} diff --git a/soc/xtensa/intel_adsp/CMakeLists.txt b/soc/xtensa/intel_adsp/CMakeLists.txt deleted file mode 100644 index 2cee15bbcf6..00000000000 --- a/soc/xtensa/intel_adsp/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Intel ADSP SoCs family CMake file -# -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(common) -if(CONFIG_SOC_SERIES_INTEL_ACE) - add_subdirectory(ace) -endif() -if(CONFIG_INTEL_ADSP_CAVS) - add_subdirectory(cavs) -endif() -zephyr_include_directories(common/include) diff --git a/soc/xtensa/intel_adsp/Kconfig b/soc/xtensa/intel_adsp/Kconfig deleted file mode 100644 index 32dae7612f5..00000000000 --- a/soc/xtensa/intel_adsp/Kconfig +++ /dev/null @@ -1,138 +0,0 @@ -# Intel CAVS SoC family configuration options -# -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_INTEL_ADSP - select WINSTREAM - select ARCH_SUPPORTS_COREDUMP - select CPU_HAS_DCACHE - select ARCH_HAS_USERSPACE if XTENSA_MMU - select CPU_CACHE_INCOHERENT - bool - -if SOC_FAMILY_INTEL_ADSP - -config SOC_FAMILY - string - default "intel_adsp" - -# Select SoC Part No. and configuration options -source "soc/xtensa/intel_adsp/*/Kconfig.soc" - -DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc -DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc - -config INTEL_ADSP_IPC - bool "Driver for the host IPC interrupt delivery" - default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HOST_IPC)) if !SOF - default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_IDC)) if !SOF - help - Driver for the host IPC interrupt delivery mechanism. - Currently SOF has its own driver for this hardware. - -config MEMORY_WIN_0_SIZE - int "Size of memory window 0" - default 8192 - help - Size of memory window 0. - - This window is used for firmware status & outbox/uplink mbox. - -config MEMORY_WIN_1_SIZE - int "Size of memory window 1" - default 8192 - help - Size of memory window 1. - - This window is used for inbox/downlink mbox. - -config MEMORY_WIN_2_SIZE - int "Size of memory window 2" - default 8192 - help - Size of memory window 2. - - This window is used for debug. - -config MEMORY_WIN_3_SIZE - int "Size of memory window 3" - default 8192 - help - Size of memory window 3. - - This window is used for trace. - -config ADSP_CLOCK - bool - help - Driver for the CAVS clocks. Allow type of clock (and - thus frequency) to be chosen. - -config HP_SRAM_RESERVE - int "Bytes to reserve at start of HP-SRAM" - default 65536 - help - Bytes to reserve at the start of HP-SRAM. Zephyr will not - place any symbols here, though the host windows have - addresses here. The SOF application also makes direct use - of this region, so be very careful changing this value. - -config ADSP_TRACE_SIMCALL - bool "Emit SIMCALL output in addition to window tracing" - help - When true, the trace_out layer will also use a SIMCALL - instruction to emit the passed data to the standard output - of an enclosing simulator process. All window contents will - remain identical. - -config ADSP_NEED_POWER_ON_CACHE - bool - help - Need to power cache SRAM banks on. - -config ADSP_INIT_HPSRAM - bool - default y - help - Need to init HP SRAM. - -config ADSP_POWER_DOWN_HPSRAM - bool - default n if ZTEST - default y - help - Switch off HP SRAM during power down. - -config ADSP_DISABLE_L2CACHE_AT_BOOT - bool - -config ADSP_IMR_CONTEXT_SAVE - bool "Saves FW context into IMR before core is shut down" - default n - help - When true, FW will store its entire context into IMR before - entering D3 state. Later this context can be used to FW restore - when Host power up DSP again. - -config XTENSA_CPU_IDLE_SPIN - bool "Use busy loop for k_cpu_idle" - help - Use a spin loop instead of WAITI for the CPU idle state. - -config XTENSA_WAITI_BUG - bool "Workaround sequence for WAITI bug on LX6" - help - SOF traditionally contains this workaround on its ADSP - platforms which prefixes a WAITI entry with 128 NOP - instructions followed by an ISYNC and EXTW. - -config ADSP_IDLE_CLOCK_GATING - bool "DSP clock gating in Idle" - help - When true, FW will run with enabled clock gating. This options change - HW configuration of a DSP. Evry time core goes to the WAITI state - (wait for interrupt) during idle, the clock can be gated (however, this - does not mean that this will happen). - -endif # SOC_FAMILY_INTEL_ADSP diff --git a/soc/xtensa/intel_adsp/Kconfig.defconfig b/soc/xtensa/intel_adsp/Kconfig.defconfig deleted file mode 100644 index 1f48b33ee68..00000000000 --- a/soc/xtensa/intel_adsp/Kconfig.defconfig +++ /dev/null @@ -1,44 +0,0 @@ -# Intel CAVS SoC family default configuration options -# -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_INTEL_ADSP -source "soc/xtensa/intel_adsp/*/Kconfig.defconfig.series" - - -config XTENSA_RPO_CACHE - def_bool y - -# console can't handle the amount of data coming from many tests, so introduce -# a delay beween testcases. -if ZTEST -config ZTEST_TEST_DELAY_MS - default 100 -endif - -if XTENSA_RPO_CACHE -config XTENSA_CACHED_REGION - default 5 - -config XTENSA_UNCACHED_REGION - default 4 - -endif # XTENSA_RPO_CACHE - -config CONSOLE - def_bool y - -if CONSOLE -config WINSTREAM_CONSOLE - def_bool y -endif - -config CACHE_MANAGEMENT - def_bool y - -choice CACHE_TYPE - default ARCH_CACHE -endchoice - -endif # SOC_FAMILY_INTEL_ADSP diff --git a/soc/xtensa/intel_adsp/Kconfig.soc b/soc/xtensa/intel_adsp/Kconfig.soc deleted file mode 100644 index 448b1645079..00000000000 --- a/soc/xtensa/intel_adsp/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Intel CAVS SoC series selection -# -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/xtensa/intel_adsp/*/Kconfig.series" diff --git a/soc/xtensa/intel_adsp/ace/CMakeLists.txt b/soc/xtensa/intel_adsp/ace/CMakeLists.txt deleted file mode 100644 index 28626787c5e..00000000000 --- a/soc/xtensa/intel_adsp/ace/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# Intel ACE SoC family CMake file -# -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - - -zephyr_library_sources( - sram.c - multiprocessing.c - irq.c - power_down.S - power.c - boot.c - timestamp.c - ) - -zephyr_include_directories(include) -zephyr_include_directories(include/${SOC_NAME}) -zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget.c) -zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget_messages.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm b/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm deleted file mode 100644 index 937b3e2b3c5..00000000000 --- a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - - -if SOC_INTEL_ACE15_MTPM - -config SOC - string - default "intel_ace15_mtpm" - -config MP_MAX_NUM_CPUS - default 3 - -endif diff --git a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace20_lnl b/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace20_lnl deleted file mode 100644 index 2dc9365ffb5..00000000000 --- a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace20_lnl +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - - -if SOC_INTEL_ACE20_LNL - -config SOC - string - default "intel_ace20_lnl" - -config MP_MAX_NUM_CPUS - default 5 - -endif diff --git a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.series deleted file mode 100644 index 5057e5cb16a..00000000000 --- a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.series +++ /dev/null @@ -1,73 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_INTEL_ACE - -config SOC_SERIES - string - default "ace" - -config SOC_TOOLCHAIN_NAME - string - default "intel_ace15_mtpm" - -config SMP - default y - -config POWER_DOMAIN - default y - -# MTL leaves the upper mapping in the same spot as cAVS, but moves the -# lower one inexplicably. -config XTENSA_UNCACHED_REGION - default 2 - -# Parameters for gen_isr_tables.py: - -config 2ND_LVL_INTR_00_OFFSET - default 4 - -config MULTI_LEVEL_INTERRUPTS - default y - -config MAX_IRQ_PER_AGGREGATOR - default 29 - -config NUM_2ND_LEVEL_AGGREGATORS - default 1 - -config 2ND_LVL_ISR_TBL_OFFSET - default 9 - -config 2ND_LEVEL_INTERRUPTS - default y - -config XTENSA_TIMER - default n - -config XTENSA_TIMER_ID - default 0 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 393216000 if XTENSA_TIMER - default 38400000 if INTEL_ADSP_TIMER - -config SYS_CLOCK_TICKS_PER_SEC - default 12000 - -config XTENSA_CCOUNT_HZ - default 393216000 - -config DYNAMIC_INTERRUPTS - default y - -if LOG - -config LOG_BACKEND_ADSP - default y - -endif # LOG - -source "soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace*" - -endif # SOC_SERIES_INTEL_ACE diff --git a/soc/xtensa/intel_adsp/ace/Kconfig.series b/soc/xtensa/intel_adsp/ace/Kconfig.series deleted file mode 100644 index 963c33bdf61..00000000000 --- a/soc/xtensa/intel_adsp/ace/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_INTEL_ACE - bool "Intel ACE" - select SOC_FAMILY_INTEL_ADSP - select XTENSA - select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")) - select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" - select ARCH_HAS_COHERENCE - select SCHED_IPI_SUPPORTED - select DW_ICTL_ACE - select SOC_HAS_RUNTIME_NUM_CPUS - select HAS_PM - help - Intel ADSP ACE diff --git a/soc/xtensa/intel_adsp/ace/Kconfig.soc b/soc/xtensa/intel_adsp/ace/Kconfig.soc deleted file mode 100644 index 69f8ebd887a..00000000000 --- a/soc/xtensa/intel_adsp/ace/Kconfig.soc +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Intel ADSP SoC Selection" - - config SOC_INTEL_ACE15_MTPM - bool "ACE 1.5 Meteor PCH M" - depends on SOC_SERIES_INTEL_ACE - - config SOC_INTEL_ACE20_LNL - bool "ACE 2.0 Lunar Lake PCH" - depends on SOC_SERIES_INTEL_ACE - -endchoice - -config SOC_INTEL_COMM_WIDGET - bool "Intel Communication Widget driver" - default y - depends on DT_HAS_INTEL_ADSP_COMMUNICATION_WIDGET_ENABLED - help - Select this to enable Intel Communication Widget driver. - DSP Communication Widget is a device for generic sideband message transmit/receive. diff --git a/soc/xtensa/intel_adsp/cavs/CMakeLists.txt b/soc/xtensa/intel_adsp/cavs/CMakeLists.txt deleted file mode 100644 index 5226f1b0535..00000000000 --- a/soc/xtensa/intel_adsp/cavs/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# Intel ADSP SoCs family CMake file -# -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(include) -zephyr_include_directories(include/${SOC_NAME}) -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_library_sources( - sram.c - power.c - power_down_cavs.S - ) - -if(CONFIG_SMP OR CONFIG_MP_MAX_NUM_CPUS GREATER 1) - zephyr_library_sources(multiprocessing.c) -endif() - -zephyr_library_sources_ifdef(CONFIG_CAVS_ICTL irq.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/include/xtensa-cavs-linker.ld CACHE INTERNAL "") diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series deleted file mode 100644 index d29c01a7988..00000000000 --- a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_INTEL_ADSP_CAVS - -config SOC_SERIES - string - default "cavs" - -config INTEL_ADSP_CAVS - def_bool y - -source "soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs*" - -config DMA_INTEL_ADSP_GPDMA - default y - depends on DMA - -config XTENSA_CCOUNT_HZ - default 400000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 50000 - -config SMP - default y - -config XTENSA_TIMER - default n - -config KERNEL_ENTRY - default "_MainEntry" - -config MULTI_LEVEL_INTERRUPTS - default y - -config 2ND_LEVEL_INTERRUPTS - default y - -config DYNAMIC_INTERRUPTS - default y - -if LOG - -config LOG_BACKEND_ADSP - default y - -endif # LOG - -endif # SOC_SERIES_INTEL_ADSP_CAVS diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.series b/soc/xtensa/intel_adsp/cavs/Kconfig.series deleted file mode 100644 index a88bec1ec2e..00000000000 --- a/soc/xtensa/intel_adsp/cavs/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2017,2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_INTEL_ADSP_CAVS - bool "Intel CAVS" - select SOC_FAMILY_INTEL_ADSP - select XTENSA - select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")) - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" - select ATOMIC_OPERATIONS_ARCH if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xcc" - select ARCH_HAS_COHERENCE - select HAS_PM - help - Intel ADSP CAVS diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.soc b/soc/xtensa/intel_adsp/cavs/Kconfig.soc deleted file mode 100644 index 0d054e0ee2a..00000000000 --- a/soc/xtensa/intel_adsp/cavs/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Intel CAVS SoC Selection" - depends on SOC_SERIES_INTEL_ADSP_CAVS - -config SOC_INTEL_CAVS_V25 - bool "Intel Tiger Lake" - select XTENSA_WAITI_BUG - select SCHED_IPI_SUPPORTED - -endchoice diff --git a/soc/xtensa/intel_adsp/common/CMakeLists.txt b/soc/xtensa/intel_adsp/common/CMakeLists.txt deleted file mode 100644 index c463e4453fc..00000000000 --- a/soc/xtensa/intel_adsp/common/CMakeLists.txt +++ /dev/null @@ -1,149 +0,0 @@ -# Intel CAVS SoC family CMake file -# -# Copyright (c) 2020-2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -zephyr_interface_library_named(INTEL_ADSP_COMMON) - -zephyr_library_named(intel_adsp_common) -zephyr_include_directories(include) -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_library_sources_ifdef(CONFIG_INTEL_ADSP_IPC ipc.c) - -zephyr_library_sources( - rimage_modules.c - boot.c - soc.c - mem_window.c - boot_complete.c - ) - -zephyr_library_sources_ifdef(CONFIG_ADSP_CLOCK clk.c) - -if(CONFIG_SMP OR CONFIG_MP_MAX_NUM_CPUS GREATER 1) - zephyr_library_sources(multiprocessing.c) -endif() - -zephyr_library_link_libraries(INTEL_ADSP_COMMON) - -target_include_directories(INTEL_ADSP_COMMON INTERFACE include) -target_link_libraries(INTEL_ADSP_COMMON INTERFACE intel_adsp_common) - -set(KERNEL_REMAPPED ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}-remapped.elf) -set(EXTMAN ${CMAKE_BINARY_DIR}/zephyr/extman.bin) - -if(${CMAKE_HOST_WIN32}) - set(NULL_FILE nul) -elseif(${CMAKE_HOST_UNIX}) - set(NULL_FILE /dev/null) -endif() - -# Generate rimage modules from the base kernel ELF file. Note the -# warning squashing on the objcopy steps. Binutils has a misfeature -# where if the copy removes all the sections from an input ELF program -# header (our link generates lots of phdrs because of the disjoint -# cacheability addresses), it will warn about an "empty" segment even -# though it was TOLD to drop the contents! -# -# Also note that rimage is picky with section flags: it will try to -# include a section in the output data (even its own metadata in -# .module!) if it has any of ALLOC, WRITABLE or EXEC flags in the ELF -# file. The GNU linker will set these automatically based on the -# flags of the sections coming out of C code, so this is fragile and -# breaks easily. Set noload flags explicitly here. -add_custom_target( - gen_modules ALL - DEPENDS ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod -) - -add_custom_command( - OUTPUT ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod - COMMENT "Extracting .mod(ule) files for rimage" - DEPENDS ${ZEPHYR_FINAL_EXECUTABLE} ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} - - # The .fw_metadata section may not be present (xcc's older linker - # will remove it if empty). Extract it here (which will create an - # empty file if not present) and add it back when we generate the - # main.mod file below. - COMMAND ${CMAKE_OBJCOPY} -O binary --only-section=.fw_metadata - ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}.elf ${EXTMAN} - - # Remap uncached section addresses so they appear contiguous - COMMAND ${CMAKE_COMMAND} -E - copy ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}.elf ${KERNEL_REMAPPED} - - # Extract modules for rimage - COMMAND ${CMAKE_OBJCOPY} - --only-section .imr - --only-section .imrdata - --only-section .module.boot - --set-section-flags .module.boot=noload,readonly - --rename-section .module.boot=.module - ${KERNEL_REMAPPED} ${CMAKE_BINARY_DIR}/zephyr/boot.mod 2>${NULL_FILE} - - # Remove .fw_metadata here... - COMMAND ${CMAKE_OBJCOPY} - --remove-section .imr - --remove-section .imrdata - --remove-section .module.boot - --remove-section .fw_metadata - --set-section-flags .module.main=noload,readonly - --set-section-flags .static_uuid_entries=noload,readonly - --set-section-flags .static_log_entries=noload,readonly - --rename-section .module.main=.module - ${KERNEL_REMAPPED} ${CMAKE_BINARY_DIR}/zephyr/main.mod 2>${NULL_FILE} - - # ...and copy it back in - COMMAND ${CMAKE_OBJCOPY} - --add-section .fw_metadata=${EXTMAN} - --set-section-flags .fw_metadata=noload,readonly - ${CMAKE_BINARY_DIR}/zephyr/main.mod - ${CMAKE_BINARY_DIR}/zephyr/main.mod 2>${NULL_FILE} -) - -if(CONFIG_BUILD_OUTPUT_STRIPPED) -add_custom_command( - COMMENT "strip main.mod" - APPEND OUTPUT ${CMAKE_BINARY_DIR}/zephyr/main.mod - COMMAND $ - $ - $ - $${CMAKE_BINARY_DIR}/zephyr/main.mod - $${CMAKE_BINARY_DIR}/zephyr/main-stripped.mod - $ -) -endif() - - -# west sign -add_custom_target(zephyr.ri ALL - DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri -) - -# If some of your board(s) need to override default rimage parameters -# then you can define WEST_SIGN_OPTS in boards/my/board/board.cmake. -# Example: -# -# set(WEST_SIGN_OPTS -- -c "/home/sweet home/rimage/config/abc.toml" -i 4) - -# Parameters after the double dash -- are passed through to rimage. For -# other ways to override default rimage parameters check -# boards/xtensa/intel_adsp_cavs25/doc/intel_adsp_generic.rst - -# Warning: because `west sign` can also be used interactively, using -# ${WEST_SIGN_OPTS} like this has _higher_ precedence than `west config -# rimage.extra-args`! Avoid overriding default rimage parameters in -# multiple places to avoid unexpected precedence rules. -add_custom_command( - OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri - COMMENT "west sign --if-tool-available --tool rimage ..." - # Use --if-tool-available so we don't force every CI to install - # rimage. We don't want to break build-only and other tests that don't - # require signing. When rimage is missing, `west flash` fails with a - # clear "zephyr.ri missing" error with an "rimage not found" warning - # from west sign immediately before it. - COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} - DEPENDS gen_modules - ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod -) diff --git a/soc/xtensa/nxp_adsp/CMakeLists.txt b/soc/xtensa/nxp_adsp/CMakeLists.txt deleted file mode 100644 index a0ab21fb6a8..00000000000 --- a/soc/xtensa/nxp_adsp/CMakeLists.txt +++ /dev/null @@ -1,27 +0,0 @@ -# NXP i.MX8/RT SoC family CMake file -# -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_SOC_NXP_RT595) - zephyr_compile_definitions(CPU_MIMXRT595SFFOC_dsp) -endif() - -add_subdirectory(common) -zephyr_include_directories(${SOC_SERIES}/include) - -# west sign - -# See detailed comments in soc/xtensa/intel_adsp/common/CMakeLists.txt -add_custom_target(zephyr.ri ALL - DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri -) - -add_custom_command( - OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri - COMMENT "west sign --if-tool-available --tool rimage ..." - COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} - DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} -) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/${SOC_SERIES}/linker.ld CACHE INTERNAL "") diff --git a/soc/xtensa/nxp_adsp/Kconfig b/soc/xtensa/nxp_adsp/Kconfig deleted file mode 100644 index 486cb7bad54..00000000000 --- a/soc/xtensa/nxp_adsp/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -# NXP i.MX8 SoC family configuration options -# -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_NXP_ADSP - bool - select ARCH_HAS_COHERENCE - select CPU_HAS_DCACHE - -if SOC_FAMILY_NXP_ADSP - -config SOC_FAMILY - string - default "nxp_adsp" - -# Select SoC Part No. and configuration options -source "soc/xtensa/nxp_adsp/*/Kconfig.soc" - -endif # SOC_FAMILY_NXP_ADSP diff --git a/soc/xtensa/nxp_adsp/Kconfig.defconfig b/soc/xtensa/nxp_adsp/Kconfig.defconfig deleted file mode 100644 index cdee20c75f5..00000000000 --- a/soc/xtensa/nxp_adsp/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# NXP i.MX8/RT SoC family default configuration options -# -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_NXP_ADSP - -source "soc/xtensa/nxp_adsp/*/Kconfig.defconfig.series" - -config CACHE_MANAGEMENT - default y - -config SMP - default n - -config XTENSA_TIMER - default y - -config KERNEL_ENTRY - default "__start" - -config MULTI_LEVEL_INTERRUPTS - default n - -config 2ND_LEVEL_INTERRUPTS - default n - -# To prevent test uses TEST_LOGGING_MINIMAL -config TEST_LOGGING_DEFAULTS - default n - depends on TEST - -endif diff --git a/soc/xtensa/nxp_adsp/Kconfig.soc b/soc/xtensa/nxp_adsp/Kconfig.soc deleted file mode 100644 index c56da8e7551..00000000000 --- a/soc/xtensa/nxp_adsp/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# NXP i.MX8 SoC series selection -# -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/xtensa/nxp_adsp/*/Kconfig.series" diff --git a/soc/xtensa/nxp_adsp/common/CMakeLists.txt b/soc/xtensa/nxp_adsp/common/CMakeLists.txt deleted file mode 100644 index 5c53c771f08..00000000000 --- a/soc/xtensa/nxp_adsp/common/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# NXP SoC family CMake file -# -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(include) diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qm b/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qm deleted file mode 100644 index e678be83592..00000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qm +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8QM_ADSP - -config SOC - default "mimx8qm6" - -endif # SOC_MIMX8QM_ADSP diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qxp b/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qxp deleted file mode 100644 index e4fcdd92fd0..00000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qxp +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8QXP_ADSP - -config SOC - default "mimx8qx6" - -endif # SOC_MIMX8QXP_ADSP diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.series b/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.series deleted file mode 100644 index a5f4597f069..00000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.series +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NXP_IMX8 - -config SOC_SERIES - string - default "imx8" - -config SOC_TOOLCHAIN_NAME - string - default "nxp_imx_adsp" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 666000000 if XTENSA_TIMER - -config SYS_CLOCK_TICKS_PER_SEC - default 50000 - -config DCACHE_LINE_SIZE - default 128 - -config GEN_IRQ_VECTOR_TABLE - default n - -source "soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8q*" - -endif # SOC_SERIES_NXP_IMX8 diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.series b/soc/xtensa/nxp_adsp/imx8/Kconfig.series deleted file mode 100644 index 003784e842b..00000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NXP_IMX8 - bool "NXP i.MX8" - select SOC_FAMILY_NXP_ADSP - select XTENSA - select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - select ATOMIC_OPERATIONS_BUILTIN - select GEN_ISR_TABLES - select XTENSA_SMALL_VECTOR_TABLE_ENTRY - help - NXP i.MX8 diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc b/soc/xtensa/nxp_adsp/imx8/Kconfig.soc deleted file mode 100644 index 33794a85c2b..00000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP i.MX SoC Selection" - depends on SOC_SERIES_NXP_IMX8 - - config SOC_MIMX8QM_ADSP - bool "NXP i.MX8QM Audio DSP" - depends on SOC_SERIES_NXP_IMX8 - select HAS_MCUX - - config SOC_MIMX8QXP_ADSP - bool "NXP i.MX8QXP Audio DSP" - depends on SOC_SERIES_NXP_IMX8 - select HAS_MCUX -endchoice - -if SOC_SERIES_NXP_IMX8 - -config SOC_PART_NUMBER - string - default SOC_PART_NUMBER_MIMX8QM_DSP if SOC_MIMX8QM_ADSP - default SOC_PART_NUMBER_MIMX8QXP_DSP if SOC_MIMX8QXP_ADSP - -source "soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8q*" - -endif # SOC_SERIES_NXP_IMX8 diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qm b/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qm deleted file mode 100644 index fd5334cfee5..00000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qm +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8QM_ADSP - -config SOC_PART_NUMBER_MIMX8QM6AVUFF - bool - -config SOC_PART_NUMBER_MIMX8QM_DSP - string - default "MIMX8QM6AVUFF_dsp" if SOC_PART_NUMBER_MIMX8QM6AVUFF - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -endif # SOC_MIMX8QM_ADSP diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qxp b/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qxp deleted file mode 100644 index 20f0a13e117..00000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qxp +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8QXP_ADSP - -config SOC_PART_NUMBER_MIMX8QX6AVLFZ - bool - -config SOC_PART_NUMBER_MIMX8QX6CVLDZ - bool - -config SOC_PART_NUMBER_MIMX8QXP_DSP - string - default "MIMX8QX6AVLFZ_dsp" if SOC_PART_NUMBER_MIMX8QX6AVLFZ - default "MIMX8QX6CVLDZ_dsp" if SOC_PART_NUMBER_MIMX8QX6CVLDZ - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -endif # SOC_MIMX8QXP_ADSP diff --git a/soc/xtensa/nxp_adsp/imx8m/Kconfig.defconfig.series b/soc/xtensa/nxp_adsp/imx8m/Kconfig.defconfig.series deleted file mode 100644 index 2d00a5e93d9..00000000000 --- a/soc/xtensa/nxp_adsp/imx8m/Kconfig.defconfig.series +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NXP_IMX8M - -config SOC_SERIES - string - default "imx8m" - -config SOC_TOOLCHAIN_NAME - string - default "nxp_imx8m_adsp" - -if SOC_MIMX8M_ADSP - -config SOC - string - default "mimx8ml8" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 800000000 if XTENSA_TIMER - -config SYS_CLOCK_TICKS_PER_SEC - default 50000 - -config DCACHE_LINE_SIZE - default 128 - -config DYNAMIC_INTERRUPTS - default y - -config GEN_IRQ_VECTOR_TABLE - default n - -endif # SOC_MIMX8M_ADSP - -endif # SOC_SERIES_NXP_IMX8M diff --git a/soc/xtensa/nxp_adsp/imx8m/Kconfig.series b/soc/xtensa/nxp_adsp/imx8m/Kconfig.series deleted file mode 100644 index 3847f52d2da..00000000000 --- a/soc/xtensa/nxp_adsp/imx8m/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NXP_IMX8M - bool "NXP i.MX8M Audio DSP Series" - select SOC_FAMILY_NXP_ADSP - select XTENSA - select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - select ATOMIC_OPERATIONS_BUILTIN - select GEN_ISR_TABLES - select XTENSA_SMALL_VECTOR_TABLE_ENTRY - help - Enable support for NXP i.MX8M Audio DSP diff --git a/soc/xtensa/nxp_adsp/imx8m/Kconfig.soc b/soc/xtensa/nxp_adsp/imx8m/Kconfig.soc deleted file mode 100644 index 5ad3c1b9b1e..00000000000 --- a/soc/xtensa/nxp_adsp/imx8m/Kconfig.soc +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP i.MX8M Audio DSP Selection" - depends on SOC_SERIES_NXP_IMX8M - - config SOC_MIMX8M_ADSP - bool "NXP i.MX8MP Audio DSP" - select HAS_MCUX if CLOCK_CONTROL - select HAS_MCUX_CCM if CLOCK_CONTROL - select HAS_MCUX_IOMUXC if PINCTRL - select PINCTRL_IMX if HAS_MCUX_IOMUXC - -endchoice - -if SOC_SERIES_NXP_IMX8M - -config SOC_PART_NUMBER_MIMX8ML8DVNLZ - bool - -config SOC_PART_NUMBER_MIMX8ML8CVNKZ - bool - -config SOC_PART_NUMBER_MIMX8MP_DSP - string - default "MIMX8ML8DVNLZ_dsp" if SOC_PART_NUMBER_MIMX8ML8DVNLZ - default "MIMX8ML8CVNKZ_dsp" if SOC_PART_NUMBER_MIMX8ML8CVNKZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_PART_NUMBER - string - default SOC_PART_NUMBER_MIMX8MP_DSP if SOC_MIMX8M_ADSP - -endif # SOC_SERIES_NXP_IMX8M diff --git a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.defconfig.series b/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.defconfig.series deleted file mode 100644 index ebd9377660b..00000000000 --- a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.defconfig.series +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NXP_IMX8ULP - -config SOC_SERIES - string - default "imx8ulp" - -config SOC_TOOLCHAIN_NAME - string - default "nxp_imx8ulp_adsp" - -config SOC - string - default "nxp_imx8ulp" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 528000000 if XTENSA_TIMER - -config SYS_CLOCK_TICKS_PER_SEC - default 50000 - -config DCACHE_LINE_SIZE - default 128 - -config GEN_IRQ_VECTOR_TABLE - default n - -endif # SOC_SERIES_NXP_IMX8ULP diff --git a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.series b/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.series deleted file mode 100644 index 34e9b3a1a1d..00000000000 --- a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NXP_IMX8ULP - bool "NXP i.MX8ULP Audio DSP Series" - select SOC_FAMILY_NXP_ADSP - select XTENSA - select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - select ATOMIC_OPERATIONS_BUILTIN - select GEN_ISR_TABLES - select XTENSA_SMALL_VECTOR_TABLE_ENTRY - help - Enable support for NXP i.MX8ULP Audio DSP diff --git a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.soc b/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.soc deleted file mode 100644 index b90fada22d4..00000000000 --- a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP i.MX8ULP Audio DSP Selection" - depends on SOC_SERIES_NXP_IMX8ULP - - config SOC_NXP_IMX8ULP - bool "NXP i.MX8ULP Audio DSP" - -endchoice diff --git a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.defconfig.series b/soc/xtensa/nxp_adsp/rt5xx/Kconfig.defconfig.series deleted file mode 100644 index b5a56658c7d..00000000000 --- a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.defconfig.series +++ /dev/null @@ -1,46 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NXP_RT5XX - -config SOC_SERIES - string - default "rt5xx" - -config SOC_TOOLCHAIN_NAME - string - default "nxp_rt500_adsp" - -config SOC - string - default "nxp_rt5xx" - -config SOC_PART_NUMBER - string - default "MIMXRT595SFFOC_dsp" if SOC_NXP_RT595 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 198000000 - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config DYNAMIC_INTERRUPTS - default n - -config CACHE - default n - -config DCACHE - default n - -config CACHE_MANAGEMENT - default n - -config LOG - default n - -endif # SOC_SERIES_NXP_RT5XX diff --git a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.series b/soc/xtensa/nxp_adsp/rt5xx/Kconfig.series deleted file mode 100644 index 5135b881638..00000000000 --- a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NXP_RT5XX - bool "NXP RT5xx Series" - select SOC_FAMILY_NXP_ADSP - select XTENSA - select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - help - NXP RT5xx ADSP Series diff --git a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.soc b/soc/xtensa/nxp_adsp/rt5xx/Kconfig.soc deleted file mode 100644 index e5b598c4f57..00000000000 --- a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP RT5xx ADSP SoC Selection" - - config SOC_NXP_RT595 - bool "NXP RT595" - depends on SOC_SERIES_NXP_RT5XX -endchoice diff --git a/soc/xtensa/sample_controller/Kconfig.defconfig b/soc/xtensa/sample_controller/Kconfig.defconfig deleted file mode 100644 index cc2040a5e93..00000000000 --- a/soc/xtensa/sample_controller/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# XTENSA board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_XTENSA_SAMPLE_CONTROLLER - -config SOC - default "sample_controller" - -config SOC_TOOLCHAIN_NAME - string - default "sample_controller" - -endif diff --git a/soc/xtensa/sample_controller/Kconfig.soc b/soc/xtensa/sample_controller/Kconfig.soc deleted file mode 100644 index 0fbdce896c7..00000000000 --- a/soc/xtensa/sample_controller/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XTENSA_SAMPLE_CONTROLLER - bool "Xtensa sample_controller core" - select XTENSA - select XTENSA_HAL - select ARCH_SUPPORTS_COREDUMP diff --git a/submanifests/optional.yaml b/submanifests/optional.yaml index 02eb081df6a..39faa5f3887 100644 --- a/submanifests/optional.yaml +++ b/submanifests/optional.yaml @@ -34,7 +34,7 @@ manifest: groups: - optional - name: sof - revision: 0606152d4aafc1f7ed43df1b1813252bfc74e154 + revision: 3e70d036a2df94b854add51742681b64ea0df729 path: modules/audio/sof remote: upstream groups: @@ -60,7 +60,7 @@ manifest: - optional - name: zscilib path: modules/lib/zscilib - revision: a4bb6cfd6800e14373261904825f7f34a3a7f2e5 + revision: ee1b287d9dd07208d2cc52284240ac25bb66eae3 remote: upstream groups: - optional diff --git a/subsys/bluetooth/controller/CMakeLists.txt b/subsys/bluetooth/controller/CMakeLists.txt index fa5c22f2e28..36d093c8037 100644 --- a/subsys/bluetooth/controller/CMakeLists.txt +++ b/subsys/bluetooth/controller/CMakeLists.txt @@ -188,7 +188,7 @@ zephyr_library_include_directories_ifdef( ) zephyr_library_include_directories_ifdef( - CONFIG_SOC_OPENISA_RV32M1_RISCV32 + CONFIG_SOC_OPENISA_RV32M1 ll_sw/openisa hci/openisa ) @@ -204,7 +204,7 @@ add_subdirectory_ifdef( ) add_subdirectory_ifdef( - CONFIG_SOC_OPENISA_RV32M1_RISCV32 + CONFIG_SOC_OPENISA_RV32M1 ll_sw/openisa ) diff --git a/subsys/bluetooth/controller/Kconfig b/subsys/bluetooth/controller/Kconfig index 2f154ad7d5a..bbd045b093c 100644 --- a/subsys/bluetooth/controller/Kconfig +++ b/subsys/bluetooth/controller/Kconfig @@ -557,8 +557,8 @@ config BT_CTLR_FAL_SIZE int "LE Controller-based Privacy White List size" depends on BT_CTLR_FILTER_ACCEPT_LIST default 8 - range 1 8 if (SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1_RISCV32) - range 1 16 if !(SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1_RISCV32) + range 1 8 if (SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1) + range 1 16 if !(SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1) help Set the size of the Filter Accept List for LE Controller-based Privacy. On nRF5x-based controllers, the hardware imposes a limit of 8 devices. @@ -569,7 +569,7 @@ config BT_CTLR_RL_SIZE depends on BT_CTLR_PRIVACY default 8 range 1 8 if SOC_COMPATIBLE_NRF - range 1 8 if SOC_OPENISA_RV32M1_RISCV32 + range 1 8 if SOC_OPENISA_RV32M1 help Set the size of the Resolving List for LE Controller-based Privacy. On nRF5x-based controllers, the hardware imposes a limit of 8 devices. diff --git a/subsys/bluetooth/controller/Kconfig.ll_sw_split b/subsys/bluetooth/controller/Kconfig.ll_sw_split index b3cd1e9f8f8..97f7161bf07 100644 --- a/subsys/bluetooth/controller/Kconfig.ll_sw_split +++ b/subsys/bluetooth/controller/Kconfig.ll_sw_split @@ -63,7 +63,7 @@ config BT_LLL_VENDOR_NORDIC config BT_LLL_VENDOR_OPENISA bool "Use OpenISA LLL" - depends on SOC_OPENISA_RV32M1_RISCV32 + depends on SOC_OPENISA_RV32M1 select BT_CTLR_PHY_UPDATE_SUPPORT select BT_CTLR_EXT_REJ_IND_SUPPORT select BT_HAS_HCI_VS @@ -1209,7 +1209,7 @@ config BT_CTLR_PROFILE_ISR config BT_CTLR_DEBUG_PINS bool "Bluetooth Controller Debug Pins" - depends on BOARD_NRF51DK_NRF51422 || BOARD_NRF52DK_NRF52832 || BOARD_NRF52DK_NRF52810 || BOARD_NRF52840DK_NRF52840 || BOARD_NRF52833DK_NRF52833 || BOARD_NRF5340DK_NRF5340_CPUNET || BOARD_RV32M1_VEGA + depends on BOARD_NRF51DK_NRF51822 || BOARD_NRF52DK_NRF52832 || BOARD_NRF52DK_NRF52810 || BOARD_NRF52840DK_NRF52840 || BOARD_NRF52833DK_NRF52833 || BOARD_NRF5340DK_NRF5340_CPUNET || BOARD_RV32M1_VEGA help Turn on debug GPIO toggling for the BLE Controller. This is useful when debugging with a logic analyzer or profiling certain sections of diff --git a/subsys/bluetooth/controller/hci/hci_driver.c b/subsys/bluetooth/controller/hci/hci_driver.c index 8be4255cb4a..fa3966c945f 100644 --- a/subsys/bluetooth/controller/hci/hci_driver.c +++ b/subsys/bluetooth/controller/hci/hci_driver.c @@ -35,9 +35,9 @@ #include "hal/ccm.h" -#if defined(CONFIG_SOC_FAMILY_NRF) +#if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) #include "hal/radio.h" -#endif /* CONFIG_SOC_FAMILY_NRF */ +#endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */ #include "ll_sw/pdu_df.h" #include "lll/pdu_vendor.h" diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h index 93229080688..dca94d2a811 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h @@ -74,7 +74,7 @@ #define DEBUG_PIN7 BIT(18) #define DEBUG_PIN8 BIT(19) #define DEBUG_PIN9 BIT(20) -#elif defined(CONFIG_BOARD_NRF51DK_NRF51422) +#elif defined(CONFIG_BOARD_NRF51DK_NRF51822) #define DEBUG_PORT NRF_GPIO #define DEBUG_PIN0 BIT(12) #define DEBUG_PIN1 BIT(13) diff --git a/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_conn.c b/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_conn.c index ccf18702dce..e34dd883d4e 100644 --- a/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_conn.c +++ b/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_conn.c @@ -542,11 +542,11 @@ void lll_conn_pdu_tx_prep(struct lll_conn *lll, struct pdu_data **pdu_data_tx) p->rfu = 0U; -#if !defined(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +#if !defined(CONFIG_SOC_OPENISA_RV32M1) #if !defined(CONFIG_BT_CTLR_DATA_LENGTH_CLEAR) p->resv = 0U; #endif /* !CONFIG_BT_CTLR_DATA_LENGTH_CLEAR */ -#endif /* !CONFIG_SOC_OPENISA_RV32M1_RISCV32 */ +#endif /* !CONFIG_SOC_OPENISA_RV32M1 */ *pdu_data_tx = p; } diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c index 0c6a96e2aec..8406feef897 100644 --- a/subsys/bluetooth/host/hci_core.c +++ b/subsys/bluetooth/host/hci_core.c @@ -18,7 +18,6 @@ #include #include #include -#include #include diff --git a/subsys/testsuite/Kconfig b/subsys/testsuite/Kconfig index 5fa2a240f4d..266b8533025 100644 --- a/subsys/testsuite/Kconfig +++ b/subsys/testsuite/Kconfig @@ -131,8 +131,8 @@ config TEST_ENABLE_USERSPACE bool depends on TEST_USERSPACE depends on ARCH_HAS_USERSPACE - select USERSPACE - select DYNAMIC_OBJECTS + imply USERSPACE + imply DYNAMIC_OBJECTS default y help This hidden option implements the TEST_USERSPACE logic. It turns on @@ -143,7 +143,7 @@ config TEST_ENABLE_USERSPACE config TEST_USERSPACE_WITHOUT_HW_STACK_PROTECTION bool "Run User Mode tests without additionally enabling stack protection" depends on TEST_ENABLE_USERSPACE - default y if SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K1XX + default y if SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K1 help A HW platform might not have sufficient MPU/MMU capabilities to support running all test cases with User Mode and HW Stack Protection features diff --git a/subsys/testsuite/arch/Kconfig.v1 b/subsys/testsuite/arch/Kconfig.v1 new file mode 100644 index 00000000000..28d4b43df0b --- /dev/null +++ b/subsys/testsuite/arch/Kconfig.v1 @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +rsource "unit_testing/Kconfig" diff --git a/subsys/testsuite/boards/unit_testing/unit_testing/Kconfig.board b/subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/Kconfig.board similarity index 100% rename from subsys/testsuite/boards/unit_testing/unit_testing/Kconfig.board rename to subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/Kconfig.board diff --git a/subsys/testsuite/boards/unit_testing/unit_testing/Kconfig.defconfig b/subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/Kconfig.defconfig similarity index 100% rename from subsys/testsuite/boards/unit_testing/unit_testing/Kconfig.defconfig rename to subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/Kconfig.defconfig diff --git a/subsys/testsuite/boards/unit_testing/unit_testing/unit_testing_defconfig b/subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/unit_testing_defconfig similarity index 100% rename from subsys/testsuite/boards/unit_testing/unit_testing/unit_testing_defconfig rename to subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/unit_testing_defconfig diff --git a/subsys/testsuite/soc/unit_testing/unit_testing/Kconfig.soc b/subsys/testsuite/soc/soc_legacy/unit_testing/unit_testing/Kconfig.soc similarity index 100% rename from subsys/testsuite/soc/unit_testing/unit_testing/Kconfig.soc rename to subsys/testsuite/soc/soc_legacy/unit_testing/unit_testing/Kconfig.soc diff --git a/tests/application_development/code_relocation/testcase.yaml b/tests/application_development/code_relocation/testcase.yaml index e67885390d8..2fcf97b6aa6 100644 --- a/tests/application_development/code_relocation/testcase.yaml +++ b/tests/application_development/code_relocation/testcase.yaml @@ -26,8 +26,8 @@ tests: - _CUSTOM_SECTION_NAME2 platform_allow: - qemu_cortex_m3 - - mps2_an385 - - sam_e70_xplained + - mps2/an385 + - sam_e70_xplained/same70q21 integration_platforms: - qemu_cortex_m3 application_development.code_relocation.riscv: diff --git a/tests/arch/arc/arc_dsp_sharing/testcase.yaml b/tests/arch/arc/arc_dsp_sharing/testcase.yaml index c2149b0570e..67ade8fbbcd 100644 --- a/tests/arch/arc/arc_dsp_sharing/testcase.yaml +++ b/tests/arch/arc/arc_dsp_sharing/testcase.yaml @@ -1,8 +1,8 @@ tests: arch.arc.dsp_sharing.test_load_store: filter: CONFIG_ISA_ARCV2 and CONFIG_CPU_HAS_DSP - platform_allow: nsim_em11d + platform_allow: nsim/nsim_em11d arch.arc.dsp_sharing.test_calculation: filter: CONFIG_ISA_ARCV2 and CONFIG_CPU_HAS_DSP toolchain_allow: arcmwdt - platform_allow: nsim_em11d + platform_allow: nsim/nsim_em11d diff --git a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c index 61679107103..eaf9ddd2a6d 100644 --- a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c +++ b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c @@ -16,7 +16,7 @@ */ #define _ISR_OFFSET 0 -#if defined(CONFIG_SOC_FAMILY_NRF) +#if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) #undef _ISR_OFFSET #if defined(CONFIG_BOARD_QEMU_CORTEX_M0) /* For the nRF51-based QEMU Cortex-M0 platform, the first set of consecutive @@ -34,7 +34,7 @@ /* For other nRF targets, use TIMER0-2 interrupt lines. */ #define _ISR_OFFSET TIMER0_IRQn #endif -#endif /* CONFIG_SOC_FAMILY_NRF */ +#endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */ struct k_sem sem[3]; @@ -130,7 +130,7 @@ ZTEST(vector_table, test_arm_irq_vector_table) typedef void (*vth)(void); /* Vector Table Handler */ -#if defined(CONFIG_SOC_FAMILY_NRF) +#if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) /* nRF5X- and nRF91X-based platforms employ a Hardware RTC peripheral * to implement the Kernel system timer, instead of the ARM Cortex-M * SysTick. Therefore, a pointer to the timer ISR needs to be added in @@ -184,7 +184,7 @@ vth __irq_vector_table _irq_vector_table[] = { isr0, isr1, isr2, 0, rtc_isr }; -#elif defined(CONFIG_SOC_SERIES_IMX_RT6XX) || defined(CONFIG_SOC_SERIES_IMX_RT5XX) && \ +#elif defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) && \ defined(CONFIG_MCUX_OS_TIMER) /* MXRT685 employs a OS Event timer to implement the Kernel system * timer, instead of the ARM Cortex-M SysTick. Therefore, a pointer to @@ -197,7 +197,8 @@ vth __irq_vector_table _irq_vector_table[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, mcux_lpc_ostick_isr }; -#elif defined(CONFIG_SOC_SERIES_IMX_RT) && defined(CONFIG_MCUX_GPT_TIMER) +#elif (defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)) && \ + defined(CONFIG_MCUX_GPT_TIMER) /** MXRT parts employ a GPT timer peripheral to implement the Kernel system * timer, instead of the ARM Cortex-M Systick. Thereforce, a pointer to the * timer ISR need to be added in the custom vector table to handle @@ -210,7 +211,7 @@ vth __irq_vector_table _irq_vector_table[] = { isr0, isr1, isr2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, mcux_imx_gpt_isr }; -#elif defined(CONFIG_SOC_SERIES_IMX_RT10XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT10XX) /* RT10xx GPT timer interrupt is at offset 100 */ vth __irq_vector_table _irq_vector_table[] = { isr0, isr1, isr2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -219,7 +220,7 @@ vth __irq_vector_table _irq_vector_table[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, mcux_imx_gpt_isr }; -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) /* RT11xx GPT timer interrupt is at offset 119 */ vth __irq_vector_table _irq_vector_table[] = { isr0, isr1, isr2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -236,7 +237,7 @@ vth __irq_vector_table _irq_vector_table[] = { vth __irq_vector_table _irq_vector_table[] = { isr0, isr1, isr2 }; -#endif /* CONFIG_SOC_FAMILY_NRF */ +#endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */ /** * @} diff --git a/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml b/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml index b2cd459d1d3..638e54f59d7 100644 --- a/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml +++ b/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml @@ -1,6 +1,6 @@ common: filter: (CONFIG_ARMV6_M_ARMV8_M_BASELINE or CONFIG_ARMV7_M_ARMV8_M_MAINLINE) and - not CONFIG_SOC_FAMILY_NRF + not CONFIG_SOC_FAMILY_NORDIC_NRF tags: - arm - interrupt @@ -9,8 +9,8 @@ tests: arch.arm.irq_zero_latency_levels: filter: not CONFIG_TRUSTED_EXECUTION_NONSECURE integration_platforms: - - mps2_an521_remote + - mps2/an521/cpu1 arch.arm.irq_zero_latency_levels.secure_fw: filter: CONFIG_TRUSTED_EXECUTION_SECURE integration_platforms: - - mps2_an521 + - mps2/an521/cpu0 diff --git a/tests/arch/arm/arm_no_multithreading/testcase.yaml b/tests/arch/arm/arm_no_multithreading/testcase.yaml index 43ab80279f0..855a94ca97e 100644 --- a/tests/arch/arm/arm_no_multithreading/testcase.yaml +++ b/tests/arch/arm/arm_no_multithreading/testcase.yaml @@ -8,11 +8,11 @@ tests: platform_allow: - qemu_cortex_m0 - qemu_cortex_m3 - - mps2_an385 - - mps2_an521 - - mps3_an547 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf51dk_nrf51422 + - mps2/an385 + - mps2/an521/cpu0 + - mps3/an547 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf51dk/nrf51822 integration_platforms: - qemu_cortex_m0 diff --git a/tests/arch/arm/arm_sw_vector_relay/testcase.yaml b/tests/arch/arm/arm_sw_vector_relay/testcase.yaml index 37433433d91..7c5dfc14903 100644 --- a/tests/arch/arm/arm_sw_vector_relay/testcase.yaml +++ b/tests/arch/arm/arm_sw_vector_relay/testcase.yaml @@ -5,4 +5,4 @@ tests: - vector_relay arch_allow: arm integration_platforms: - - mps2_an385 + - mps2/an385 diff --git a/tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_ns.overlay b/tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay similarity index 100% rename from tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_ns.overlay rename to tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay diff --git a/tests/arch/arm/arm_thread_swap_tz/testcase.yaml b/tests/arch/arm/arm_thread_swap_tz/testcase.yaml index f8bbbc8dd93..808aa5250d2 100644 --- a/tests/arch/arm/arm_thread_swap_tz/testcase.yaml +++ b/tests/arch/arm/arm_thread_swap_tz/testcase.yaml @@ -9,16 +9,16 @@ tests: arch.arm.swap.tz: # NOTE: this platform disables FPU access in TFM. platform_exclude: - - mps3_an547_ns - - nucleo_l552ze_q_ns + - mps3/an547/ns + - nucleo_l552ze_q/stm32l552xx/ns integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns arch.arm.swap.tz_off: extra_configs: - CONFIG_ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS=n # NOTE: this platform disables FPU access in TFM. platform_exclude: - - mps3_an547_ns - - nucleo_l552ze_q_ns + - mps3/an547/ns + - nucleo_l552ze_q/stm32l552xx/ns integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns diff --git a/tests/arch/arm/arm_tz_wrap_func/testcase.yaml b/tests/arch/arm/arm_tz_wrap_func/testcase.yaml index ef0e1eda7db..43826147ad8 100644 --- a/tests/arch/arm/arm_tz_wrap_func/testcase.yaml +++ b/tests/arch/arm/arm_tz_wrap_func/testcase.yaml @@ -7,4 +7,4 @@ tests: - tz_wrap_func filter: CONFIG_CPU_CORTEX_M integration_platforms: - - mps2_an385 + - mps2/an385 diff --git a/tests/arch/arm64/arm64_smc_call/testcase.yaml b/tests/arch/arm64/arm64_smc_call/testcase.yaml index d6254cfa67d..763192878e6 100644 --- a/tests/arch/arm64/arm64_smc_call/testcase.yaml +++ b/tests/arch/arm64/arm64_smc_call/testcase.yaml @@ -1,6 +1,6 @@ tests: arch.arm64.smc_call.smc: - platform_allow: fvp_base_revc_2xaemv8a_smp_ns + platform_allow: fvp_base_revc_2xaemv8a//smp/ns tags: - arm - smc diff --git a/tests/arch/common/ramfunc/boards/arty_a7_arm_designstart_m1.overlay b/tests/arch/common/ramfunc/boards/arty_a7_designstart_fpga_cortex_m1.overlay similarity index 100% rename from tests/arch/common/ramfunc/boards/arty_a7_arm_designstart_m1.overlay rename to tests/arch/common/ramfunc/boards/arty_a7_designstart_fpga_cortex_m1.overlay diff --git a/tests/benchmarks/app_kernel/testcase.yaml b/tests/benchmarks/app_kernel/testcase.yaml index 2b07dedad66..32790a43e4e 100644 --- a/tests/benchmarks/app_kernel/testcase.yaml +++ b/tests/benchmarks/app_kernel/testcase.yaml @@ -8,11 +8,11 @@ common: tests: benchmark.kernel.application: integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 benchmark.kernel.application.objcore.stats: integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 extra_configs: - CONFIG_OBJ_CORE=y @@ -34,7 +34,7 @@ tests: - CONFIG_OBJ_CORE_STATS=y benchmark.kernel.application.timeslicing: integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 extra_configs: - CONFIG_TIMESLICING=y @@ -42,7 +42,7 @@ tests: extra_args: CONF_FILE=prj_user.conf filter: CONFIG_ARCH_HAS_USERSPACE integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 extra_configs: - CONFIG_TIMESLICING=y diff --git a/tests/benchmarks/cmsis_dsp/basicmath/testcase.yaml b/tests/benchmarks/cmsis_dsp/basicmath/testcase.yaml index c2527111322..d63b4f0aa83 100644 --- a/tests/benchmarks/cmsis_dsp/basicmath/testcase.yaml +++ b/tests/benchmarks/cmsis_dsp/basicmath/testcase.yaml @@ -11,13 +11,13 @@ tests: benchmark.cmsis_dsp.basicmath: integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 benchmark.cmsis_dsp.basicmath.fpu: filter: CONFIG_CPU_HAS_FPU integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - fpu extra_configs: diff --git a/tests/benchmarks/footprints/testcase.yaml b/tests/benchmarks/footprints/testcase.yaml index 926b582ddcb..2e9165e8b8b 100644 --- a/tests/benchmarks/footprints/testcase.yaml +++ b/tests/benchmarks/footprints/testcase.yaml @@ -6,14 +6,14 @@ tests: benchmark.kernel.footprints.default: build_only: true integration_platforms: - - mps2_an385 + - mps2/an385 benchmark.kernel.footprints.pm: tags: - pm build_only: true extra_args: CONF_FILE=prj_pm.conf integration_platforms: - - mps2_an385 + - mps2/an385 benchmark.kernel.footprints.userspace: filter: CONFIG_ARCH_HAS_USERSPACE extra_args: CONF_FILE=prj_userspace.conf @@ -25,4 +25,4 @@ tests: - userspace build_only: true integration_platforms: - - mps2_an385 + - mps2/an385 diff --git a/tests/benchmarks/latency_measure/boards/atsame54_xpro.conf b/tests/benchmarks/latency_measure/boards/same54_xpro.conf similarity index 100% rename from tests/benchmarks/latency_measure/boards/atsame54_xpro.conf rename to tests/benchmarks/latency_measure/boards/same54_xpro.conf diff --git a/tests/benchmarks/latency_measure/testcase.yaml b/tests/benchmarks/latency_measure/testcase.yaml index e6af80305c7..76ed840c7cf 100644 --- a/tests/benchmarks/latency_measure/testcase.yaml +++ b/tests/benchmarks/latency_measure/testcase.yaml @@ -12,7 +12,7 @@ tests: harness: console integration_platforms: - qemu_x86 - - qemu_arc_em + - qemu_arc/qemu_arc_em harness_config: type: one_line record: @@ -30,7 +30,7 @@ tests: harness: console integration_platforms: - qemu_x86 - - qemu_arc_em + - qemu_arc/qemu_arc_em extra_configs: - CONFIG_OBJ_CORE=y - CONFIG_OBJ_CORE_STATS=y @@ -107,7 +107,7 @@ tests: harness: console integration_platforms: - qemu_x86 - - qemu_arc_em + - qemu_arc/qemu_arc_em extra_configs: - CONFIG_TIMESLICING=y harness_config: diff --git a/tests/benchmarks/sched/testcase.yaml b/tests/benchmarks/sched/testcase.yaml index 6ec2987d335..9ae091c3d62 100644 --- a/tests/benchmarks/sched/testcase.yaml +++ b/tests/benchmarks/sched/testcase.yaml @@ -4,7 +4,7 @@ tests: - benchmark - kernel integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 slow: true harness: console diff --git a/tests/bluetooth/adv/testcase.yaml b/tests/bluetooth/adv/testcase.yaml index 12a927be910..d20f6436d1e 100644 --- a/tests/bluetooth/adv/testcase.yaml +++ b/tests/bluetooth/adv/testcase.yaml @@ -2,10 +2,10 @@ tests: bluetooth.adv: platform_allow: - nrf52_bsim - - nrf51dk_nrf51422 - - nrf52840dk_nrf52840 + - nrf51dk/nrf51822 + - nrf52840dk/nrf52840 tags: bluetooth slow: true timeout: 360 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 diff --git a/tests/bluetooth/ctrl_user_ext/CMakeLists.txt b/tests/bluetooth/ctrl_user_ext/CMakeLists.txt index 087435e8884..9a6673eb324 100644 --- a/tests/bluetooth/ctrl_user_ext/CMakeLists.txt +++ b/tests/bluetooth/ctrl_user_ext/CMakeLists.txt @@ -13,7 +13,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF) ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic ) -elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +elseif(CONFIG_SOC_OPENISA_RV32M1) zephyr_library_include_directories( ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa ${ZEPHYR_BASE}/bluetooth/hci/openisa diff --git a/tests/bluetooth/df/connection_cte_req/CMakeLists.txt b/tests/bluetooth/df/connection_cte_req/CMakeLists.txt index 9b6dc638090..f2828b825aa 100644 --- a/tests/bluetooth/df/connection_cte_req/CMakeLists.txt +++ b/tests/bluetooth/df/connection_cte_req/CMakeLists.txt @@ -27,7 +27,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF) ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic ) -elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +elseif(CONFIG_SOC_OPENISA_RV32M1) zephyr_library_include_directories( ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa ${ZEPHYR_BASE}/bluetooth/hci/openisa diff --git a/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt b/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt index a2ae350c4f0..d03e6e15ba2 100644 --- a/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt +++ b/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt @@ -28,7 +28,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF) ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic ) -elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +elseif(CONFIG_SOC_OPENISA_RV32M1) zephyr_library_include_directories( ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa ${ZEPHYR_BASE}/bluetooth/hci/openisa diff --git a/tests/bluetooth/df/connectionless_cte_rx/CMakeLists.txt b/tests/bluetooth/df/connectionless_cte_rx/CMakeLists.txt index 4af6a0694ca..cac22fa3401 100644 --- a/tests/bluetooth/df/connectionless_cte_rx/CMakeLists.txt +++ b/tests/bluetooth/df/connectionless_cte_rx/CMakeLists.txt @@ -26,7 +26,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF) ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic ) -elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +elseif(CONFIG_SOC_OPENISA_RV32M1) zephyr_library_include_directories( ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa ${ZEPHYR_BASE}/bluetooth/hci/openisa diff --git a/tests/bluetooth/df/connectionless_cte_tx/CMakeLists.txt b/tests/bluetooth/df/connectionless_cte_tx/CMakeLists.txt index 4af6a0694ca..cac22fa3401 100644 --- a/tests/bluetooth/df/connectionless_cte_tx/CMakeLists.txt +++ b/tests/bluetooth/df/connectionless_cte_tx/CMakeLists.txt @@ -26,7 +26,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF) ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic ) -elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +elseif(CONFIG_SOC_OPENISA_RV32M1) zephyr_library_include_directories( ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa ${ZEPHYR_BASE}/bluetooth/hci/openisa diff --git a/tests/bluetooth/init/testcase.yaml b/tests/bluetooth/init/testcase.yaml index 060c51a3f81..63267a96c8e 100644 --- a/tests/bluetooth/init/testcase.yaml +++ b/tests/bluetooth/init/testcase.yaml @@ -76,255 +76,255 @@ tests: bluetooth.init.test_ctlr: extra_args: CONF_FILE=prj_ctlr.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy integration_platforms: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_4_0: extra_args: CONF_FILE=prj_ctlr_4_0.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_4_0_dbg: extra_args: CONF_FILE=prj_ctlr_4_0_dbg.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_tiny: extra_args: CONF_FILE=prj_ctlr_tiny.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_dbg: extra_args: - CONF_FILE=prj_ctlr_dbg.conf - DTC_OVERLAY_FILE=pa_lna.overlay platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 bluetooth.init.test_ctlr_5_x_dbg: extra_args: - CONF_FILE=prj_ctlr_5_x_dbg.conf - DTC_OVERLAY_FILE=pa_lna.overlay platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 bluetooth.init.test_ctlr_sw_switch_single_timer: extra_args: - CONF_FILE=prj_ctlr.conf - CONFIG_BT_CTLR_ADVANCED_FEATURES=y - CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER=y platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf5340dk/nrf5340/cpunet + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf5340dk_nrf5340_cpunet - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf5340dk/nrf5340/cpunet + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 bluetooth.init.test_ctlr_ticker: extra_args: - CONF_FILE=prj_ctlr_ticker.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 bluetooth.init.test_ctlr_broadcaster: extra_args: CONF_FILE=prj_ctlr_broadcaster.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_peripheral: extra_args: CONF_FILE=prj_ctlr_peripheral.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_peripheral_priv: extra_args: CONF_FILE=prj_ctlr_peripheral_priv.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_observer: extra_args: CONF_FILE=prj_ctlr_observer.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_central: extra_args: CONF_FILE=prj_ctlr_central.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_central_priv: extra_args: CONF_FILE=prj_ctlr_central_priv.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_broadcaster_ext: extra_args: CONF_FILE=prj_ctlr_broadcaster_ext.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_peripheral_ext: extra_args: CONF_FILE=prj_ctlr_peripheral_ext.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_peripheral_ext_priv: extra_args: CONF_FILE=prj_ctlr_peripheral_ext_priv.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_oberver_ext: extra_args: CONF_FILE=prj_ctlr_observer_ext.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_central_ext: extra_args: CONF_FILE=prj_ctlr_central_ext.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_central_ext_priv: extra_args: CONF_FILE=prj_ctlr_central_ext_priv.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_per_adv: extra_args: CONF_FILE=prj_ctlr_per_adv.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_per_adv_no_adi: extra_args: CONF_FILE=prj_ctlr_per_adv_no_adi.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_per_sync: extra_args: CONF_FILE=prj_ctlr_per_sync.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_per_sync_no_adi: extra_args: CONF_FILE=prj_ctlr_per_sync_no_adi.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_per_sync_no_filter: extra_args: CONF_FILE=prj_ctlr_per_sync_no_filter.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_peripheral_iso: extra_args: CONF_FILE=prj_ctlr_peripheral_iso.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_central_iso: extra_args: CONF_FILE=prj_ctlr_central_iso.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_h5: extra_args: CONF_FILE=prj_h5.conf platform_allow: qemu_cortex_m3 @@ -334,16 +334,16 @@ tests: bluetooth.init.test_llcp: extra_args: CONF_FILE=prj_llcp.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - rv32m1_vega/openisa_rv32m1/ri5cy integration_platforms: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_config_bt_recv_workq_bt: extra_args: - CONF_FILE=prj_ctlr.conf - CONFIG_BT_RECV_WORKQ_BT=y platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/tests/bluetooth/mesh/basic/testcase.yaml b/tests/bluetooth/mesh/basic/testcase.yaml index 1e417baa343..b299442f8ac 100644 --- a/tests/bluetooth/mesh/basic/testcase.yaml +++ b/tests/bluetooth/mesh/basic/testcase.yaml @@ -3,7 +3,7 @@ tests: build_only: true platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -14,7 +14,7 @@ tests: extra_args: CONF_FILE=dbg.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -25,7 +25,7 @@ tests: extra_args: CONF_FILE=friend.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -36,7 +36,7 @@ tests: extra_args: CONF_FILE=gatt.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -47,7 +47,7 @@ tests: extra_args: CONF_FILE=lpn.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -58,7 +58,7 @@ tests: extra_args: CONF_FILE=pb_gatt.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -69,7 +69,7 @@ tests: extra_args: CONF_FILE=proxy.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -80,7 +80,7 @@ tests: extra_args: CONF_FILE=ext_adv.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -91,7 +91,7 @@ tests: extra_args: CONF_FILE=multi_ext_adv.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: diff --git a/tests/bluetooth/mesh_shell/testcase.yaml b/tests/bluetooth/mesh_shell/testcase.yaml index 5d08287a43c..7e565b493a2 100644 --- a/tests/bluetooth/mesh_shell/testcase.yaml +++ b/tests/bluetooth/mesh_shell/testcase.yaml @@ -5,7 +5,7 @@ tests: bluetooth.mesh.mesh_shell: platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 diff --git a/tests/bluetooth/shell/testcase.yaml b/tests/bluetooth/shell/testcase.yaml index c47b845a5dc..b561844db6e 100644 --- a/tests/bluetooth/shell/testcase.yaml +++ b/tests/bluetooth/shell/testcase.yaml @@ -15,10 +15,10 @@ tests: - native_posix_64 - native_sim - native_sim_64 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 tags: bluetooth harness: keyboard min_flash: 145 @@ -39,10 +39,10 @@ tests: - native_posix_64 - native_sim - native_sim_64 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - native_sim - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 tags: bluetooth harness: keyboard min_flash: 350 @@ -59,7 +59,7 @@ tests: - native_sim_64 integration_platforms: - native_sim - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 tags: bluetooth harness: keyboard bluetooth.shell.no_privacy: diff --git a/tests/bluetooth/tester/testcase.yaml b/tests/bluetooth/tester/testcase.yaml index 37c7ab3193d..7721cabf153 100644 --- a/tests/bluetooth/tester/testcase.yaml +++ b/tests/bluetooth/tester/testcase.yaml @@ -5,7 +5,7 @@ tests: - qemu_x86 - native_posix - native_sim - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth harness: bluetooth bluetooth.general.tester_le_audio: @@ -14,7 +14,7 @@ tests: - qemu_x86 - native_posix - native_sim - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp extra_args: OVERLAY_CONFIG="overlay-le-audio.conf" tags: bluetooth harness: bluetooth @@ -24,7 +24,7 @@ tests: - qemu_x86 - native_posix - native_sim - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_args: OVERLAY_CONFIG="overlay-mesh.conf" tags: bluetooth harness: bluetooth diff --git a/tests/boards/espressif_esp32/cache_coex/testcase.yaml b/tests/boards/espressif_esp32/cache_coex/testcase.yaml index 063d4e9fb3b..a7205b75cd2 100644 --- a/tests/boards/espressif_esp32/cache_coex/testcase.yaml +++ b/tests/boards/espressif_esp32/cache_coex/testcase.yaml @@ -1,9 +1,9 @@ tests: boards.esp32.cache_coex: platform_allow: - - esp32_devkitc_wrover + - esp32_devkitc_wrover/esp32/procpu - esp32s2_saola - - esp32s3_devkitm + - esp32s3_devkitm/esp32s3/procpu tags: - spiram - spiflash diff --git a/tests/boards/intel_adsp/cache/testcase.yaml b/tests/boards/intel_adsp/cache/testcase.yaml index 93aaae71841..7c2b30614fa 100644 --- a/tests/boards/intel_adsp/cache/testcase.yaml +++ b/tests/boards/intel_adsp/cache/testcase.yaml @@ -2,6 +2,6 @@ common: tags: boards tests: boards.intel_adsp.cache: - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 diff --git a/tests/boards/intel_adsp/hda/testcase.yaml b/tests/boards/intel_adsp/hda/testcase.yaml index 7e801157de5..fd657b95b25 100644 --- a/tests/boards/intel_adsp/hda/testcase.yaml +++ b/tests/boards/intel_adsp/hda/testcase.yaml @@ -1,7 +1,7 @@ common: - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 tests: boards.intel_adsp.hda: tags: diff --git a/tests/boards/intel_adsp/mm/testcase.yaml b/tests/boards/intel_adsp/mm/testcase.yaml index f7a80b8139f..c714f41fe00 100644 --- a/tests/boards/intel_adsp/mm/testcase.yaml +++ b/tests/boards/intel_adsp/mm/testcase.yaml @@ -2,4 +2,4 @@ common: tags: boards tests: boards.intel_adsp.mm: - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 diff --git a/tests/boards/intel_adsp/smoke/testcase.yaml b/tests/boards/intel_adsp/smoke/testcase.yaml index 4339486839f..9561d1c2d57 100644 --- a/tests/boards/intel_adsp/smoke/testcase.yaml +++ b/tests/boards/intel_adsp/smoke/testcase.yaml @@ -1,5 +1,5 @@ tests: boards.intel_adsp.smoke: - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 diff --git a/tests/boards/intel_adsp/ssp/testcase.yaml b/tests/boards/intel_adsp/ssp/testcase.yaml index d196a487aff..e524a87784f 100644 --- a/tests/boards/intel_adsp/ssp/testcase.yaml +++ b/tests/boards/intel_adsp/ssp/testcase.yaml @@ -7,6 +7,6 @@ tests: depends_on: - dai - dma - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 diff --git a/tests/boards/nrf52_bsim/egu/testcase.yaml b/tests/boards/nrf52_bsim/egu/testcase.yaml index 952a83781d5..2f3f28f734e 100644 --- a/tests/boards/nrf52_bsim/egu/testcase.yaml +++ b/tests/boards/nrf52_bsim/egu/testcase.yaml @@ -1,5 +1,5 @@ tests: boards.nrf52_bsim.egu: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nrf52_bsim diff --git a/tests/boot/mcuboot_data_sharing/testcase.yaml b/tests/boot/mcuboot_data_sharing/testcase.yaml index b12fb012f4b..cc1ca4a4140 100644 --- a/tests/boot/mcuboot_data_sharing/testcase.yaml +++ b/tests/boot/mcuboot_data_sharing/testcase.yaml @@ -7,7 +7,7 @@ common: sysbuild: true tests: bootloader.mcuboot.data.sharing: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: - mcuboot - sysbuild diff --git a/tests/boot/mcuboot_recovery_retention/testcase.yaml b/tests/boot/mcuboot_recovery_retention/testcase.yaml index 084aedcba58..8ec7fa47496 100644 --- a/tests/boot/mcuboot_recovery_retention/testcase.yaml +++ b/tests/boot/mcuboot_recovery_retention/testcase.yaml @@ -22,13 +22,13 @@ common: - "Boot source: none" tests: bootloader.mcuboot.recovery.retention: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: - mcuboot - sysbuild - recovery bootloader.mcuboot.recovery.retention.mem: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG="boards/nrf52840dk_nrf52840_mem.conf" - DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840_mem.overlay" diff --git a/tests/boot/test_mcuboot/testcase.yaml b/tests/boot/test_mcuboot/testcase.yaml index b4b7735c1c8..6669dc5efdb 100644 --- a/tests/boot/test_mcuboot/testcase.yaml +++ b/tests/boot/test_mcuboot/testcase.yaml @@ -20,7 +20,7 @@ tests: - lpcxpresso55s16 - lpcxpresso55s28 - lpcxpresso55s36 - - lpcxpresso55s69_cpu0 + - lpcxpresso55s69/lpc55s69/cpu0 - mimxrt1010_evk - mimxrt1015_evk - mimxrt1020_evk @@ -29,14 +29,14 @@ tests: - mimxrt1050_evk - mimxrt1060_evk - mimxrt1064_evk - - mimxrt1160_evk_cm7 - - mimxrt1170_evk_cm7 - - mimxrt595_evk_cm33 - - mimxrt685_evk_cm33 - - nrf52840dk_nrf52840 + - mimxrt1160_evk/mimxrt1166/cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt595_evk/mimxrt595s/cm33 + - mimxrt685_evk + - nrf52840dk/nrf52840 integration_platforms: - frdm_k64f - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 bootloader.mcuboot.assert: tags: mcuboot platform_allow: diff --git a/tests/boot/with_mcumgr/README.rst b/tests/boot/with_mcumgr/README.rst index f3281f57c5c..e937d08163c 100644 --- a/tests/boot/with_mcumgr/README.rst +++ b/tests/boot/with_mcumgr/README.rst @@ -10,13 +10,13 @@ using **sysbuild**. Tests are automated with pytest, a new harness of Twister in the system PATH. More information about MCUmgr can be found here :ref:`mcu_mgr`. -To run tests with Twister on ``nrf52840dk_nrf52840`` platform, +To run tests with Twister on ``nrf52840dk/nrf52840`` platform, use following command: .. code-block:: console ./zephyr/scripts/twister -vv --west-flash --enable-slow -T zephyr/tests/boot/with_mcumgr \ - -p nrf52840dk_nrf52840 --device-testing --device-serial /dev/ttyACM0 + -p nrf52840dk/nrf52840 --device-testing --device-serial /dev/ttyACM0 .. note:: Twister requires ``--west-flash`` flag enabled (without additional parameters diff --git a/tests/boot/with_mcumgr/testcase.yaml b/tests/boot/with_mcumgr/testcase.yaml index 08904c177bd..3926819e6f2 100644 --- a/tests/boot/with_mcumgr/testcase.yaml +++ b/tests/boot/with_mcumgr/testcase.yaml @@ -1,11 +1,11 @@ common: sysbuild: true platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf9160dk_nrf9160 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf9160dk/nrf9160 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 timeout: 600 slow: true tests: diff --git a/tests/crypto/rand32/testcase.yaml b/tests/crypto/rand32/testcase.yaml index 5db81483366..5561511b2c6 100644 --- a/tests/crypto/rand32/testcase.yaml +++ b/tests/crypto/rand32/testcase.yaml @@ -33,4 +33,4 @@ tests: tags: - psa-crypto integration_platforms: - - nrf5340dk_nrf5340_cpuapp_ns + - nrf5340dk/nrf5340/cpuapp/ns diff --git a/tests/crypto/tinycrypt/testcase.yaml b/tests/crypto/tinycrypt/testcase.yaml index ac08d94fd95..74c4853a9cc 100644 --- a/tests/crypto/tinycrypt/testcase.yaml +++ b/tests/crypto/tinycrypt/testcase.yaml @@ -6,8 +6,8 @@ tests: - aes - ccm platform_exclude: - - qemu_arc_em - - qemu_arc_hs + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs - m2gl025_miv timeout: 500 integration_platforms: diff --git a/tests/drivers/adc/adc_api/boards/arduino_nano_33_ble_sense.overlay b/tests/drivers/adc/adc_api/boards/arduino_nano_33_ble_nrf52840_sense.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/arduino_nano_33_ble_sense.overlay rename to tests/drivers/adc/adc_api/boards/arduino_nano_33_ble_nrf52840_sense.overlay diff --git a/tests/drivers/adc/adc_api/boards/hexiwear_k64.overlay b/tests/drivers/adc/adc_api/boards/hexiwear_mk64f12.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/hexiwear_k64.overlay rename to tests/drivers/adc/adc_api/boards/hexiwear_mk64f12.overlay diff --git a/tests/drivers/adc/adc_api/boards/hexiwear_kw40z.overlay b/tests/drivers/adc/adc_api/boards/hexiwear_mkw40z4.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/hexiwear_kw40z.overlay rename to tests/drivers/adc/adc_api/boards/hexiwear_mkw40z4.overlay diff --git a/tests/drivers/adc/adc_api/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/tests/drivers/adc/adc_api/boards/mimxrt1170_evkb_cm7.overlay b/tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/mimxrt1170_evkb_cm7.overlay rename to tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/tests/drivers/adc/adc_api/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/adc/adc_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/adc/adc_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/adc/adc_api/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/adc/adc_api/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/adc/adc_api/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/adc/adc_api/boards/nrf51dk_nrf51422.conf b/tests/drivers/adc/adc_api/boards/nrf51dk_nrf51822.conf similarity index 100% rename from tests/drivers/adc/adc_api/boards/nrf51dk_nrf51422.conf rename to tests/drivers/adc/adc_api/boards/nrf51dk_nrf51822.conf diff --git a/tests/drivers/adc/adc_api/boards/nrf51dk_nrf51422.overlay b/tests/drivers/adc/adc_api/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/nrf51dk_nrf51422.overlay rename to tests/drivers/adc/adc_api/boards/nrf51dk_nrf51822.overlay diff --git a/tests/drivers/adc/adc_api/boards/rpi_pico_w.overlay b/tests/drivers/adc/adc_api/boards/rpi_pico_rp2040_w.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/rpi_pico_w.overlay rename to tests/drivers/adc/adc_api/boards/rpi_pico_rp2040_w.overlay diff --git a/tests/drivers/adc/adc_api/boards/sam4e_xpro.overlay b/tests/drivers/adc/adc_api/boards/sam4e_xpro.overlay new file mode 100644 index 00000000000..3486ce077fc --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/sam4e_xpro.overlay @@ -0,0 +1,25 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Gerson Fernando Budke + */ + +/ { + zephyr,user { + io-channels = <&afec0 0>; + }; +}; + +&afec0 { + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_EXTERNAL0"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,input-positive = <15>; + }; +}; diff --git a/tests/drivers/adc/adc_api/boards/sam_e70_xplained.overlay b/tests/drivers/adc/adc_api/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/sam_e70_xplained.overlay rename to tests/drivers/adc/adc_api/boards/sam_e70_xplained_same70q21.overlay diff --git a/tests/drivers/adc/adc_api/boards/sam_e70b_xplained.overlay b/tests/drivers/adc/adc_api/boards/sam_e70_xplained_same70q21b.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/sam_e70b_xplained.overlay rename to tests/drivers/adc/adc_api/boards/sam_e70_xplained_same70q21b.overlay diff --git a/tests/drivers/adc/adc_api/boards/sam_v71_xult.overlay b/tests/drivers/adc/adc_api/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/sam_v71_xult.overlay rename to tests/drivers/adc/adc_api/boards/sam_v71_xult_samv71q21.overlay diff --git a/tests/drivers/adc/adc_api/boards/sam_v71b_xult.overlay b/tests/drivers/adc/adc_api/boards/sam_v71_xult_samv71q21b.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/sam_v71b_xult.overlay rename to tests/drivers/adc/adc_api/boards/sam_v71_xult_samv71q21b.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsamc21n_xpro.overlay b/tests/drivers/adc/adc_api/boards/samc21n_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsamc21n_xpro.overlay rename to tests/drivers/adc/adc_api/boards/samc21n_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsamd20_xpro.overlay b/tests/drivers/adc/adc_api/boards/samd20_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsamd20_xpro.overlay rename to tests/drivers/adc/adc_api/boards/samd20_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsamd21_xpro.overlay b/tests/drivers/adc/adc_api/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsamd21_xpro.overlay rename to tests/drivers/adc/adc_api/boards/samd21_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsame54_xpro.overlay b/tests/drivers/adc/adc_api/boards/same54_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsame54_xpro.overlay rename to tests/drivers/adc/adc_api/boards/same54_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsaml21_xpro.overlay b/tests/drivers/adc/adc_api/boards/saml21_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsaml21_xpro.overlay rename to tests/drivers/adc/adc_api/boards/saml21_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsamr21_xpro.overlay b/tests/drivers/adc/adc_api/boards/samr21_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsamr21_xpro.overlay rename to tests/drivers/adc/adc_api/boards/samr21_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsamr34_xpro.overlay b/tests/drivers/adc/adc_api/boards/samr34_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsamr34_xpro.overlay rename to tests/drivers/adc/adc_api/boards/samr34_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/xiao_ble_sense.overlay b/tests/drivers/adc/adc_api/boards/xiao_ble_nrf52840_sense.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/xiao_ble_sense.overlay rename to tests/drivers/adc/adc_api/boards/xiao_ble_nrf52840_sense.overlay diff --git a/tests/drivers/audio/dmic_api/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/audio/dmic_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/audio/dmic_api/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/audio/dmic_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/audio/dmic_api/testcase.yaml b/tests/drivers/audio/dmic_api/testcase.yaml index 960aad3323a..28f9643f6ca 100644 --- a/tests/drivers/audio/dmic_api/testcase.yaml +++ b/tests/drivers/audio/dmic_api/testcase.yaml @@ -5,4 +5,4 @@ tests: harness: ztest filter: dt_alias_exists("dmic-dev") integration_platforms: - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 diff --git a/tests/drivers/build_all/adc/testcase.yaml b/tests/drivers/build_all/adc/testcase.yaml index 0d2df1769ea..9c4afb9cc0d 100644 --- a/tests/drivers/build_all/adc/testcase.yaml +++ b/tests/drivers/build_all/adc/testcase.yaml @@ -26,13 +26,13 @@ tests: drivers.adc.npcx.build: platform_allow: npcx7m6fb_evb drivers.adc.nrf.build: - platform_allow: nrf51dk_nrf51422 + platform_allow: nrf51dk/nrf51822 drivers.adc.nrf.saadc.build: - platform_allow: nrf21540dk_nrf52840 + platform_allow: nrf21540dk/nrf52840 drivers.adc.sam0.build: - platform_allow: atsame54_xpro + platform_allow: same54_xpro drivers.adc.sam.afec.build: - platform_allow: sam_e70_xplained + platform_allow: sam_e70_xplained/same70q21 drivers.adc.stm32.build: platform_allow: disco_l475_iot1 drivers.adc.xec.build: diff --git a/tests/drivers/build_all/counter/boards/arty_a7_arm_designstart_m1.overlay b/tests/drivers/build_all/counter/boards/arty_a7_designstart_fpga_cortex_m1.overlay similarity index 100% rename from tests/drivers/build_all/counter/boards/arty_a7_arm_designstart_m1.overlay rename to tests/drivers/build_all/counter/boards/arty_a7_designstart_fpga_cortex_m1.overlay diff --git a/tests/drivers/build_all/counter/testcase.yaml b/tests/drivers/build_all/counter/testcase.yaml index ff50c81289c..d5861c45eae 100644 --- a/tests/drivers/build_all/counter/testcase.yaml +++ b/tests/drivers/build_all/counter/testcase.yaml @@ -5,6 +5,6 @@ common: - counter tests: drivers.counter.build.xlnx: - platform_allow: arty_a7_arm_designstart_m1 + platform_allow: arty_a7/designstart_fpga_cortex_m1 extra_configs: - CONFIG_COUNTER_XLNX_AXI_TIMER=y diff --git a/tests/drivers/build_all/dac/boards/atsamd21_xpro.overlay b/tests/drivers/build_all/dac/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/build_all/dac/boards/atsamd21_xpro.overlay rename to tests/drivers/build_all/dac/boards/samd21_xpro.overlay diff --git a/tests/drivers/build_all/dac/testcase.yaml b/tests/drivers/build_all/dac/testcase.yaml index a298ded77b4..4192c6ca085 100644 --- a/tests/drivers/build_all/dac/testcase.yaml +++ b/tests/drivers/build_all/dac/testcase.yaml @@ -15,6 +15,6 @@ tests: drivers.dac.mcux32.build: platform_allow: twr_ke18f drivers.dac.sam0.build: - platform_allow: atsamd21_xpro + platform_allow: samd21_xpro drivers.dac.stm32.build: platform_allow: nucleo_f091rc diff --git a/tests/drivers/build_all/gpio/testcase.yaml b/tests/drivers/build_all/gpio/testcase.yaml index 88d62c5b770..b3f76141396 100644 --- a/tests/drivers/build_all/gpio/testcase.yaml +++ b/tests/drivers/build_all/gpio/testcase.yaml @@ -26,7 +26,7 @@ tests: drivers.gpio.build.adc_ads1145s0x_gpio: min_ram: 32 - platform_allow: m5stack_core2 nrf52840dk_nrf52840 + platform_allow: m5stack_core2/esp32/procpu nrf52840dk/nrf52840 depends_on: - gpio - adc diff --git a/tests/drivers/build_all/ieee802154/testcase.yaml b/tests/drivers/build_all/ieee802154/testcase.yaml index 1d9ab3617f9..176cd1acff1 100644 --- a/tests/drivers/build_all/ieee802154/testcase.yaml +++ b/tests/drivers/build_all/ieee802154/testcase.yaml @@ -15,7 +15,7 @@ tests: drivers.ieee802154.build.mcr20a: platform_allow: usb_kw24d512 drivers.ieee802154.build.nrf5: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 drivers.ieee802154.build.telink_b91: platform_allow: tlsr9518adk80d drivers.ieee802154.build.upipe: diff --git a/tests/drivers/build_all/pwm/boards/arty_a7_arm_designstart_m1.overlay b/tests/drivers/build_all/pwm/boards/arty_a7_designstart_fpga_cortex_m1.overlay similarity index 100% rename from tests/drivers/build_all/pwm/boards/arty_a7_arm_designstart_m1.overlay rename to tests/drivers/build_all/pwm/boards/arty_a7_designstart_fpga_cortex_m1.overlay diff --git a/tests/drivers/build_all/pwm/testcase.yaml b/tests/drivers/build_all/pwm/testcase.yaml index 61d93f789d0..3bcb57b6100 100644 --- a/tests/drivers/build_all/pwm/testcase.yaml +++ b/tests/drivers/build_all/pwm/testcase.yaml @@ -7,9 +7,9 @@ tests: drivers.pwm.cc13xx_cc26xx_timer.build: platform_allow: cc1352p1_launchxl drivers.pwm.gecko.build: - platform_allow: efr32_radio_brd4250b + platform_allow: efr32_radio/efr32fg1p133f256gm48 drivers.pwm.imx.build: - platform_allow: colibri_imx7d_m4 + platform_allow: colibri_imx7d/mcimx7d/m4 drivers.pwm.litex.build: platform_allow: litex_vexriscv drivers.pwm.mcux.ftm.build: @@ -23,32 +23,32 @@ tests: drivers.pwm.mcux.build: platform_allow: mimxrt1064_evk drivers.pwm.mcux.sctimer.build: - platform_allow: mimxrt685_evk_cm33 + platform_allow: mimxrt685_evk drivers.pwm.rv32m1.tpm.build: - platform_allow: rv32m1_vega_ri5cy + platform_allow: rv32m1_vega/openisa_rv32m1/ri5cy drivers.pwm.sifive.build: - platform_allow: hifive1_revb + platform_allow: hifive1@B drivers.pwm.npcx.build: platform_allow: npcx7m6fb_evb drivers.pwm.nrf.sw.build: - platform_allow: nrf51dk_nrf51422 + platform_allow: nrf51dk/nrf51822 drivers.pwm.nrf.build: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 drivers.pwm.pca9685.build: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=adafruit_pca9685 drivers.pwm.sam0.tcc.build: - platform_allow: atsame54_xpro + platform_allow: same54_xpro drivers.pwm.build.sam: platform_allow: - - sam_e70_xplained - - sam_v71b_xult + - sam_e70_xplained/same70q21 + - sam_v71_xult/samv71q21b drivers.pwm.stm32.build: platform_allow: disco_l475_iot1 drivers.pwm.xec.build: platform_allow: mec15xxevb_assy6853 drivers.pwm.build.xlnx: - platform_allow: arty_a7_arm_designstart_m1 + platform_allow: arty_a7/designstart_fpga_cortex_m1 drivers.pwm.build.test: platform_allow: qemu_cortex_m3 drivers.pwm.max31790.build: diff --git a/tests/drivers/can/api/testcase.yaml b/tests/drivers/can/api/testcase.yaml index 9ee9777fcef..75bb509f827 100644 --- a/tests/drivers/can/api/testcase.yaml +++ b/tests/drivers/can/api/testcase.yaml @@ -16,12 +16,12 @@ tests: extra_args: DTC_OVERLAY_FILE=twai-enable.overlay filter: dt_compat_enabled("espressif,esp32-twai") platform_allow: - - esp32_devkitc_wroom - - esp32_devkitc_wrover + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu - esp32c3_devkitm - esp32s2_saola - - esp32s3_devkitm - - xiao_esp32s3 + - esp32s3_devkitm/esp32s3/procpu + - xiao_esp32s3/esp32s3/procpu drivers.can.api.nxp_s32_canxl.non_rx_fifo: extra_configs: - CONFIG_CAN_NXP_S32_RX_FIFO=n diff --git a/tests/drivers/charger/sbs_charger/testcase.yaml b/tests/drivers/charger/sbs_charger/testcase.yaml index 7256c6530e9..75c9994b8f5 100644 --- a/tests/drivers/charger/sbs_charger/testcase.yaml +++ b/tests/drivers/charger/sbs_charger/testcase.yaml @@ -12,13 +12,13 @@ tests: DTC_OVERLAY_FILE="boards/emulated_board.overlay" platform_exclude: - qemu_cortex_a53 - - qemu_cortex_a53_smp + - qemu_cortex_a53/qemu_cortex_a53/smp - qemu_kvm_arm64 - xenvm - - xenvm_gicv3 + - xenvm/xenvm/gicv3 - hifive_unmatched - - rcar_h3ulcb_ca57 - - rcar_salvator_xs_m3 + - rcar_h3ulcb/r8a77951/a57 + - rcar_salvator_xs - numaker_pfm_m467 drivers.charger.sbs.emulated_64_bit_i2c_addr: tags: @@ -29,10 +29,10 @@ tests: (CONFIG_QEMU_TARGET or CONFIG_ARCH_POSIX) platform_allow: - qemu_cortex_a53 - - qemu_cortex_a53_smp + - qemu_cortex_a53/qemu_cortex_a53/smp - qemu_kvm_arm64 - xenvm - - xenvm_gicv3 + - xenvm/xenvm/gicv3 extra_args: CONF_FILE="prj.conf;boards/qemu_cortex_a53.conf" DTC_OVERLAY_FILE="boards/qemu_cortex_a53.overlay" diff --git a/tests/drivers/clock_control/adsp_clock/testcase.yaml b/tests/drivers/clock_control/adsp_clock/testcase.yaml index 48df05a8462..04de6e55838 100644 --- a/tests/drivers/clock_control/adsp_clock/testcase.yaml +++ b/tests/drivers/clock_control/adsp_clock/testcase.yaml @@ -3,6 +3,6 @@ tests: tags: - drivers - clock_control - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 diff --git a/tests/drivers/clock_control/clock_control_api/testcase.yaml b/tests/drivers/clock_control/clock_control_api/testcase.yaml index be789c8382a..7a3552fd4e7 100644 --- a/tests/drivers/clock_control/clock_control_api/testcase.yaml +++ b/tests/drivers/clock_control/clock_control_api/testcase.yaml @@ -4,20 +4,20 @@ tests: - drivers - clock_control platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 drivers.clock.clock_control_nrf5_lfclk_rc: tags: - drivers - clock_control platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_args: CONF_FILE="nrf_lfclk_rc.conf" diff --git a/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml b/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml index 092471d30e4..2e2934b33ea 100644 --- a/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml +++ b/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml @@ -4,8 +4,8 @@ tests: - drivers - clock_control platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 diff --git a/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml b/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml index f4940d79896..a5716326ab9 100644 --- a/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml +++ b/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml @@ -3,124 +3,124 @@ common: - drivers - clock_control integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 tests: drivers.clock.nrf_lf_clock_start_xtal_stable: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_STABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 drivers.clock.nrf_lf_clock_start_xtal_available: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 drivers.clock.nrf_lf_clock_start_xtal_no_wait: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_NO_WAIT=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y drivers.clock.nrf_lf_clock_start_rc_stable: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_STABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y drivers.clock.nrf_lf_clock_start_rc_available: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y drivers.clock.nrf_lf_clock_start_rc_no_wait: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_NO_WAIT=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y drivers.clock.nrf_lf_clock_start_synth_stable: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_STABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=y drivers.clock.nrf_lf_clock_start_synth_available: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=y drivers.clock.nrf_lf_clock_start_synth_no_wait: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_NO_WAIT=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=y diff --git a/tests/drivers/clock_control/nrf_onoff_and_bt/testcase.yaml b/tests/drivers/clock_control/nrf_onoff_and_bt/testcase.yaml index 19c77496933..4f5eff4456b 100644 --- a/tests/drivers/clock_control/nrf_onoff_and_bt/testcase.yaml +++ b/tests/drivers/clock_control/nrf_onoff_and_bt/testcase.yaml @@ -4,8 +4,8 @@ tests: - drivers - clock_control platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 diff --git a/tests/drivers/clock_control/onoff/testcase.yaml b/tests/drivers/clock_control/onoff/testcase.yaml index a6e03d9a0ec..91239e3b538 100644 --- a/tests/drivers/clock_control/onoff/testcase.yaml +++ b/tests/drivers/clock_control/onoff/testcase.yaml @@ -4,9 +4,9 @@ tests: - drivers - clock_control platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt685_evk_cm33_rtc_1khz.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt685_evk_rtc_1khz.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/mimxrt685_evk_cm33_rtc_1khz.overlay rename to tests/drivers/counter/counter_basic_api/boards/mimxrt685_evk_rtc_1khz.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/nrf51dk_nrf51422.overlay b/tests/drivers/counter/counter_basic_api/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/nrf51dk_nrf51422.overlay rename to tests/drivers/counter/counter_basic_api/boards/nrf51dk_nrf51822.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/stm32h747i_disco_m7.overlay b/tests/drivers/counter/counter_basic_api/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/stm32h747i_disco_m7.overlay rename to tests/drivers/counter/counter_basic_api/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/tests/drivers/counter/counter_basic_api/testcase.yaml b/tests/drivers/counter/counter_basic_api/testcase.yaml index f6210c0bc74..f4f1120fdf9 100644 --- a/tests/drivers/counter/counter_basic_api/testcase.yaml +++ b/tests/drivers/counter/counter_basic_api/testcase.yaml @@ -12,7 +12,7 @@ tests: - drivers - counter depends_on: counter - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 timeout: 400 extra_configs: - CONFIG_ZERO_LATENCY_IRQS=y @@ -32,7 +32,7 @@ tests: - drivers - counter depends_on: counter - platform_allow: mimxrt685_evk_cm33 + platform_allow: mimxrt685_evk timeout: 400 extra_args: - DTC_OVERLAY_FILE="boards/mimxrt685_evk_cm33_rtc_1khz.overlay" + DTC_OVERLAY_FILE="boards/mimxrt685_evk_rtc_1khz.overlay" diff --git a/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml b/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml index 5c46deb6e61..af42d7b327c 100644 --- a/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml +++ b/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml @@ -4,4 +4,4 @@ tests: - drivers - counter depends_on: counter - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 diff --git a/tests/drivers/counter/maxim_ds3231_api/boards/nrf51dk_nrf51422.overlay b/tests/drivers/counter/maxim_ds3231_api/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from tests/drivers/counter/maxim_ds3231_api/boards/nrf51dk_nrf51422.overlay rename to tests/drivers/counter/maxim_ds3231_api/boards/nrf51dk_nrf51822.overlay diff --git a/tests/drivers/dac/dac_api/src/test_dac.c b/tests/drivers/dac/dac_api/src/test_dac.c index 53ffb2ac0e9..612aa824ec0 100644 --- a/tests/drivers/dac/dac_api/src/test_dac.c +++ b/tests/drivers/dac/dac_api/src/test_dac.c @@ -57,7 +57,7 @@ #elif defined(CONFIG_BOARD_BL652_DVK) || \ defined(CONFIG_BOARD_BL653_DVK) || \ defined(CONFIG_BOARD_BL654_DVK) || \ - defined(CONFIG_BOARD_BL5340_DVK_CPUAPP) + defined(CONFIG_BOARD_BL5340_DVK) /* Note external DAC MCP4725 is not populated on BL652_DVK, BL653_DVK and * BL654_DVK at factory */ diff --git a/tests/drivers/dac/dac_loopback/src/test_dac.c b/tests/drivers/dac/dac_loopback/src/test_dac.c index 9b571bf384c..38d71c4b8a1 100644 --- a/tests/drivers/dac/dac_loopback/src/test_dac.c +++ b/tests/drivers/dac/dac_loopback/src/test_dac.c @@ -144,7 +144,7 @@ #elif defined(CONFIG_BOARD_BL652_DVK) || \ defined(CONFIG_BOARD_BL653_DVK) || \ defined(CONFIG_BOARD_BL654_DVK) || \ - defined(CONFIG_BOARD_BL5340_DVK_CPUAPP) + defined(CONFIG_BOARD_BL5340_DVK) #include /* DAC output from MCP4725 pin 1 * On BL65x ADC_1 input is read from pin SIO_3 @@ -184,7 +184,7 @@ static const struct adc_channel_cfg adc_ch_cfg = { #if defined(CONFIG_BOARD_BL652_DVK) || \ defined(CONFIG_BOARD_BL653_DVK) || \ defined(CONFIG_BOARD_BL654_DVK) || \ - defined(CONFIG_BOARD_BL5340_DVK_CPUAPP) || \ + defined(CONFIG_BOARD_BL5340_DVK) || \ defined(CONFIG_BOARD_LPCXPRESSO55S36) .input_positive = ADC_1ST_CHANNEL_INPUT, #endif diff --git a/tests/drivers/dac/dac_loopback/testcase.yaml b/tests/drivers/dac/dac_loopback/testcase.yaml index f1a682f2f5b..1a2c06758b6 100644 --- a/tests/drivers/dac/dac_loopback/testcase.yaml +++ b/tests/drivers/dac/dac_loopback/testcase.yaml @@ -20,7 +20,7 @@ tests: - bl652_dvk - bl653_dvk - bl654_dvk - - bl5340_dvk_cpuapp + - bl5340_dvk/nrf5340/cpuapp - stm32f3_disco - stm32l562e_dk - nucleo_l552ze_q diff --git a/tests/drivers/disk/disk_performance/testcase.yaml b/tests/drivers/disk/disk_performance/testcase.yaml index af008bf56e0..5f39653838a 100644 --- a/tests/drivers/disk/disk_performance/testcase.yaml +++ b/tests/drivers/disk/disk_performance/testcase.yaml @@ -10,7 +10,7 @@ tests: tags: sdhc integration_platforms: - mimxrt1064_evk - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 drivers.disk.disk_performance.disk.nvme: extra_configs: - CONFIG_NVME=y diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000..cdc6eb7c7f1 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000..5e8bafa1d9b --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm7.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.conf similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm7.conf rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.conf diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000..f3ceb4ecbb8 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_NOCACHE_MEMORY=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000..5e8bafa1d9b --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000..cdc6eb7c7f1 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000..5e8bafa1d9b --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000..433a67585be --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="DTCM" diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000..82f0bbe94e8 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&dtcm { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_cm33.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_cm33.conf rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/atsamc21n_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/samc21n_xpro.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/atsamc21n_xpro.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/samc21n_xpro.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/atsamd21_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/atsamd21_xpro.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/samd21_xpro.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/atsaml21_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/saml21_xpro.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/atsaml21_xpro.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/saml21_xpro.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/atsamr34_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/samr34_xpro.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/atsamr34_xpro.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/samr34_xpro.overlay diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000..9d2f44e7231 --- /dev/null +++ b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Kumar Gala + * + * SPDX-License-Identifier: Apache-2.0 + */ + +dma0: &edma0 { }; diff --git a/tests/drivers/dma/chan_link_transfer/testcase.yaml b/tests/drivers/dma/chan_link_transfer/testcase.yaml index 930ab1067eb..23bb9c6bc8a 100644 --- a/tests/drivers/dma/chan_link_transfer/testcase.yaml +++ b/tests/drivers/dma/chan_link_transfer/testcase.yaml @@ -7,14 +7,14 @@ tests: - dma platform_allow: - frdm_k64f - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 - mimxrt1050_evk - mimxrt1060_evk - mimxrt1064_evk - - mimxrt1160_evk_cm7 - - mimxrt1170_evk_cm7 + - mimxrt1160_evk/mimxrt1166/cm7 + - mimxrt1170_evk/mimxrt1176/cm7 - mimxrt1024_evk - - lpcxpresso55s69_cpu0 + - lpcxpresso55s69/lpc55s69/cpu0 - lpcxpresso55s36 - native_posix - native_posix_64 diff --git a/tests/drivers/dma/loop_transfer/boards/longan_nano_lite.overlay b/tests/drivers/dma/loop_transfer/boards/longan_nano_gd32vf103_lite.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/longan_nano_lite.overlay rename to tests/drivers/dma/loop_transfer/boards/longan_nano_gd32vf103_lite.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000..cdc6eb7c7f1 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000..5e8bafa1d9b --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm7.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.conf similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm7.conf rename to tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.conf diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000..cdc6eb7c7f1 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000..5e8bafa1d9b --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000..cdc6eb7c7f1 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000..5e8bafa1d9b --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000..8aa11602c69 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="ITCM" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000..43b7fc37826 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&itcm { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000..8aa11602c69 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="ITCM" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evkb_cm7.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt1170_evkb_cm7.overlay rename to tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_cm33.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_cm33.conf rename to tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/dma/loop_transfer/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/atsamc21n_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/samc21n_xpro.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/atsamc21n_xpro.overlay rename to tests/drivers/dma/loop_transfer/boards/samc21n_xpro.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/atsamd21_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/atsamd21_xpro.overlay rename to tests/drivers/dma/loop_transfer/boards/samd21_xpro.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/atsaml21_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/saml21_xpro.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/atsaml21_xpro.overlay rename to tests/drivers/dma/loop_transfer/boards/saml21_xpro.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/atsamr34_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/samr34_xpro.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/atsamr34_xpro.overlay rename to tests/drivers/dma/loop_transfer/boards/samr34_xpro.overlay diff --git a/tests/drivers/dma/scatter_gather/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/dma/scatter_gather/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/dma/scatter_gather/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/dma/scatter_gather/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/dma/scatter_gather/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/dma/scatter_gather/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/dma/scatter_gather/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/dma/scatter_gather/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/dma/scatter_gather/testcase.yaml b/tests/drivers/dma/scatter_gather/testcase.yaml index 6b05448a96c..78b5e0f115e 100644 --- a/tests/drivers/dma/scatter_gather/testcase.yaml +++ b/tests/drivers/dma/scatter_gather/testcase.yaml @@ -5,7 +5,7 @@ tests: - drivers - dma platform_allow: - - intel_adsp_cavs25 + - intel_adsp/cavs25 - frdm_k64f - mimxrt1060_evk - lpcxpresso55s36 @@ -13,6 +13,6 @@ tests: - native_posix_64 filter: dt_alias_exists("dma0") integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 - native_posix - native_posix_64 diff --git a/tests/drivers/flash/common/boards/b_u585i_iot02a_ns.overlay b/tests/drivers/flash/common/boards/b_u585i_iot02a_stm32u585xx_ns.overlay similarity index 100% rename from tests/drivers/flash/common/boards/b_u585i_iot02a_ns.overlay rename to tests/drivers/flash/common/boards/b_u585i_iot02a_stm32u585xx_ns.overlay diff --git a/tests/drivers/flash/common/boards/mimxrt595_evk_cm33.conf b/tests/drivers/flash/common/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from tests/drivers/flash/common/boards/mimxrt595_evk_cm33.conf rename to tests/drivers/flash/common/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/tests/drivers/flash/common/boards/nrf52840_flash_qspi.conf b/tests/drivers/flash/common/boards/nrf52840_flash_qspi.conf index 60f91e378f9..f995a2d2993 100644 --- a/tests/drivers/flash/common/boards/nrf52840_flash_qspi.conf +++ b/tests/drivers/flash/common/boards/nrf52840_flash_qspi.conf @@ -1,4 +1,4 @@ # Minimal configuration for testing flash driver -# on nrf52840dk_nrf52840 board +# on nrf52840dk/nrf52840 board CONFIG_NORDIC_QSPI_NOR=y diff --git a/tests/drivers/flash/common/boards/nrf52840_flash_soc.conf b/tests/drivers/flash/common/boards/nrf52840_flash_soc.conf index 3e24ed6e555..f28de713011 100644 --- a/tests/drivers/flash/common/boards/nrf52840_flash_soc.conf +++ b/tests/drivers/flash/common/boards/nrf52840_flash_soc.conf @@ -1,4 +1,4 @@ # Minimal configuration for testing flash driver -# on nrf52840dk_nrf52840 board +# on nrf52840dk/nrf52840 board CONFIG_MPU_ALLOW_FLASH_WRITE=y diff --git a/tests/drivers/flash/common/testcase.yaml b/tests/drivers/flash/common/testcase.yaml index c7a60cbff5c..7b7827db069 100644 --- a/tests/drivers/flash/common/testcase.yaml +++ b/tests/drivers/flash/common/testcase.yaml @@ -4,31 +4,31 @@ common: - flash tests: drivers.flash.common.nrf_qspi_nor: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: OVERLAY_CONFIG=boards/nrf52840_flash_qspi.conf integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 drivers.flash.common.nrf_qspi_nor.size_in_bytes: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840_flash_qspi.conf - DTC_OVERLAY_FILE=boards/nrf52840_size_in_bytes.overlay integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 drivers.flash.common.nrf_qspi_nor_4B_addr: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840_flash_qspi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_mx25l51245g.overlay harness_config: fixture: external_flash_mx25l51245g integration_platforms: - - nrf52840dk_nrf52840 - drivers.flash.common.soc_flash_nrf: - platform_allow: nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 + drivers.flash.common.soc_flash/nrf: + platform_allow: nrf52840dk/nrf52840 extra_args: OVERLAY_CONFIG=boards/nrf52840_flash_soc.conf integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 drivers.flash.common.default: filter: ((CONFIG_FLASH_HAS_DRIVER_ENABLED and not CONFIG_TRUSTED_EXECUTION_NONSECURE) and dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions")) @@ -40,7 +40,7 @@ tests: filter: (CONFIG_FLASH_HAS_DRIVER_ENABLED and CONFIG_TRUSTED_EXECUTION_NONSECURE and dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions")) integration_platforms: - - nrf9161dk_nrf9161_ns + - nrf9161dk/nrf9161/ns drivers.flash.common.stm32: platform_allow: - nucleo_f103rb @@ -57,32 +57,32 @@ tests: - nucleo_wb55rg - nucleo_wl55jc - stm32l562e_dk - - stm32l562e_dk_ns + - stm32l562e_dk/stm32l562xx/ns integration_platforms: - nucleo_f103rb filter: (dt_compat_enabled("st,stm32-flash-controller") or dt_compat_enabled("st,stm32h7-flash-controller")) and dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions") drivers.flash.common.mx25r_high_perf: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_flash_spi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_mx25r_high_perf.overlay integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 drivers.flash.common.mr_canhubk3_sfdp_runtime: platform_allow: mr_canhubk3 extra_configs: - CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME=y drivers.flash.common.spi_nor: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_flash_spi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_spi_nor.overlay harness_config: fixture: external_flash_mx25v1635f drivers.flash.common.spi_nor_wp_hold: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_flash_spi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_spi_nor_wp_hold.overlay @@ -90,9 +90,9 @@ tests: fixture: external_flash_mx25v1635f drivers.flash.common.sam0: platform_allow: - - atsamd20_xpro - - atsamr21_xpro - - atsame54_xpro + - samd20_xpro + - samr21_xpro + - same54_xpro drivers.flash.common.gd32: platform_allow: - gd32vf103v_eval diff --git a/tests/drivers/flash/erase_blocks/testcase.yaml b/tests/drivers/flash/erase_blocks/testcase.yaml index 2382563bd4e..5be1ff92c1f 100644 --- a/tests/drivers/flash/erase_blocks/testcase.yaml +++ b/tests/drivers/flash/erase_blocks/testcase.yaml @@ -11,7 +11,7 @@ tests: harness: ztest build_only: true platform_allow: - - sam_v71_xult + - sam_v71_xult/samv71q21 - b_u585i_iot02a - - nrf9160dk_nrf9160 - - nrf5340dk_nrf5340_cpuapp + - nrf9160dk/nrf9160 + - nrf5340dk/nrf5340/cpuapp diff --git a/tests/drivers/flash/stm32/testcase.yaml b/tests/drivers/flash/stm32/testcase.yaml index f3346c96052..fe13b3444fd 100644 --- a/tests/drivers/flash/stm32/testcase.yaml +++ b/tests/drivers/flash/stm32/testcase.yaml @@ -14,7 +14,7 @@ tests: dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions") drivers.flash.stm32.l4: platform_allow: - - nucleo_l452re_p + - nucleo_l452re/stm32l452xx/p - disco_l475_iot1 extra_configs: - CONFIG_FLASH_STM32_READOUT_PROTECTION=y diff --git a/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml b/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml index 97d25b26a05..bcdcd84127b 100644 --- a/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml +++ b/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml @@ -12,12 +12,12 @@ tests: platform_exclude: - hifive_unmatched - qemu_cortex_a53 - - qemu_cortex_a53_smp + - qemu_cortex_a53/qemu_cortex_a53/smp - qemu_kvm_arm64 - xenvm - - xenvm_gicv3 - - rcar_h3ulcb_ca57 - - rcar_salvator_xs_m3 + - xenvm/xenvm/gicv3 + - rcar_h3ulcb/r8a77951/a57 + - rcar_salvator_xs integration_platforms: - qemu_x86 drivers.fuel_gauge.sbs_gauge_new_api.emulated_64_bit_i2c_addr: @@ -30,10 +30,10 @@ tests: platform_allow: - hifive_unmatched - qemu_cortex_a53 - - qemu_cortex_a53_smp + - qemu_cortex_a53/qemu_cortex_a53/smp - qemu_kvm_arm64 - xenvm - - xenvm_gicv3 + - xenvm/xenvm/gicv3 integration_platforms: - qemu_cortex_a53 extra_args: diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/gpio/gpio_api_1pin/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/gpio/gpio_api_1pin/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/gpio/gpio_api_1pin/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/gpio/gpio_api_1pin/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/gpio/gpio_api_1pin/testcase.yaml b/tests/drivers/gpio/gpio_api_1pin/testcase.yaml index 18b8bc1bd69..66f36a4a14f 100644 --- a/tests/drivers/gpio/gpio_api_1pin/testcase.yaml +++ b/tests/drivers/gpio/gpio_api_1pin/testcase.yaml @@ -7,7 +7,8 @@ tests: min_flash: 48 # Fix exclude when we can exclude just sim run platform_exclude: - - mps2_an385 - - mps2_an521 + - mps2/an385 + - mps2/an521/cpu0 - neorv32 + - hifive1 # see #69350 filter: dt_enabled_alias_with_parent_compat("led0", "gpio-leds") diff --git a/tests/drivers/gpio/gpio_basic_api/boards/bl5340_dvk_cpuapp.overlay b/tests/drivers/gpio/gpio_basic_api/boards/bl5340_dvk_nrf5340_cpuapp.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/bl5340_dvk_cpuapp.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/bl5340_dvk_nrf5340_cpuapp.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/hifive1_revb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/hifive1_fe310_B.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/hifive1_revb.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/hifive1_fe310_B.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso54114_m4.overlay b/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso54114_lpc54114_m4.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso54114_m4.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso54114_lpc54114_m4.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rv32m1_vega_ri5cy.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/rv32m1_vega_ri5cy.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/gpio/gpio_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/gpio/gpio_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/sam_e70_xplained.overlay b/tests/drivers/gpio/gpio_basic_api/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/sam_e70_xplained.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/sam_e70_xplained_same70q21.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/atsamd21_xpro.overlay b/tests/drivers/gpio/gpio_basic_api/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/atsamd21_xpro.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/samd21_xpro.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/stm32h747i_disco_m7.overlay b/tests/drivers/gpio/gpio_basic_api/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/stm32h747i_disco_m7.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.overlay b/tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_mcimx6x_m4.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_mcimx6x_m4.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/src/main.c b/tests/drivers/gpio/gpio_basic_api/src/main.c index 143be7d314d..67326505e98 100644 --- a/tests/drivers/gpio/gpio_basic_api/src/main.c +++ b/tests/drivers/gpio/gpio_basic_api/src/main.c @@ -10,7 +10,7 @@ /* Grotesque hack for pinmux boards */ #if defined(CONFIG_BOARD_RV32M1_VEGA) #include -#elif defined(CONFIG_BOARD_UDOO_NEO_FULL_M4) +#elif defined(CONFIG_BOARD_UDOO_NEO_FULL_MCIMX6X_M4) #include "device_imx.h" #elif defined(CONFIG_BOARD_MIMXRT1050_EVK) #include @@ -32,7 +32,7 @@ static void board_setup(void) } #endif -#if defined(CONFIG_BOARD_UDOO_NEO_FULL_M4) +#if defined(CONFIG_BOARD_UDOO_NEO_FULL_MCIMX6X_M4) /* * Configure pin mux. * The following code needs to configure the same GPIOs which were diff --git a/tests/drivers/gpio/gpio_basic_api/testcase.yaml b/tests/drivers/gpio/gpio_basic_api/testcase.yaml index cc572e82ef0..e431230f5aa 100644 --- a/tests/drivers/gpio/gpio_basic_api/testcase.yaml +++ b/tests/drivers/gpio/gpio_basic_api/testcase.yaml @@ -13,7 +13,7 @@ tests: filter: dt_compat_enabled("test-gpio-basic-api") drivers.gpio.nrf_sense_edge: - platform_allow: nrf52840dk_nrf52840 nrf52_bsim + platform_allow: nrf52840dk/nrf52840 nrf52_bsim extra_args: "DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840.overlay;\ boards/nrf52840dk_nrf52840_sense_edge.overlay" diff --git a/tests/drivers/gpio/gpio_get_direction/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/gpio/gpio_get_direction/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/gpio/gpio_get_direction/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/gpio/gpio_get_direction/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/gpio/gpio_get_direction/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/gpio/gpio_get_direction/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/gpio/gpio_get_direction/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/gpio/gpio_get_direction/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/gpio/gpio_get_direction/testcase.yaml b/tests/drivers/gpio/gpio_get_direction/testcase.yaml index a957a3cb1b8..b66145fc9af 100644 --- a/tests/drivers/gpio/gpio_get_direction/testcase.yaml +++ b/tests/drivers/gpio/gpio_get_direction/testcase.yaml @@ -7,7 +7,7 @@ tests: min_flash: 48 # Fix exclude when we can exclude just sim run platform_exclude: - - mps2_an385 - - mps2_an521 + - mps2/an385 + - mps2/an521/cpu0 - neorv32 filter: dt_enabled_alias_with_parent_compat("led0", "gpio-leds") diff --git a/tests/drivers/gpio/gpio_hogs/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/gpio/gpio_hogs/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/gpio/gpio_hogs/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/gpio/gpio_hogs/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/gpio/gpio_hogs/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/gpio/gpio_hogs/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/gpio/gpio_hogs/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/gpio/gpio_hogs/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/gpio/gpio_hogs/testcase.yaml b/tests/drivers/gpio/gpio_hogs/testcase.yaml index 98e279b789c..357ed4388c3 100644 --- a/tests/drivers/gpio/gpio_hogs/testcase.yaml +++ b/tests/drivers/gpio/gpio_hogs/testcase.yaml @@ -8,12 +8,14 @@ tests: - native_sim - native_sim_64 - frdm_k64f - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nucleo_g474re - nrf52_bsim - mr_canhubk3 - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 integration_platforms: - native_sim - native_sim_64 diff --git a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/CMakeLists.txt b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/CMakeLists.txt index 1079605a2b4..39ef8a7b979 100644 --- a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/CMakeLists.txt +++ b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/CMakeLists.txt @@ -13,8 +13,8 @@ target_include_directories(app PRIVATE zephyr_include_directories( include - ${ZEPHYR_BASE}/soc/riscv/ite_ec/common - ${ZEPHYR_BASE}/soc/riscv/ite_ec/it8xxx2 + ${ZEPHYR_BASE}/soc/ite/ec/common + ${ZEPHYR_BASE}/soc/ite/ec/it8xxx2 ) target_sources(app diff --git a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h index d3c1f7c827e..67c86ccdc40 100644 --- a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h +++ b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include <../soc/riscv/ite_ec/common/chip_chipregs.h> +#include <../soc/ite/ec/common/chip_chipregs.h> /* * Macros for emulated hardware registers access. diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evkb_cm7.overlay b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay similarity index 100% rename from tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evkb_cm7.overlay rename to tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay new file mode 100644 index 00000000000..4e17adc5dce --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -0,0 +1,25 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* To test this sample, connect J26.12 <-> J10.20 and J26.10 <-> J10.18 */ + +&lpi2c1 { + status = "okay"; + eeprom0: eeprom@54 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x54>; + size = <1024>; + }; +}; + +&lpi2c5 { + status = "okay"; + eeprom1: eeprom@56 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x56>; + size = <1024>; + }; +}; diff --git a/tests/drivers/i2c/i2c_tca954x/testcase.yaml b/tests/drivers/i2c/i2c_tca954x/testcase.yaml index 0f6d12b77c5..2304bc62c56 100644 --- a/tests/drivers/i2c/i2c_tca954x/testcase.yaml +++ b/tests/drivers/i2c/i2c_tca954x/testcase.yaml @@ -6,4 +6,4 @@ tests: - drivers depends_on: i2c filter: dt_compat_enabled("ti,tca9546a") - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 diff --git a/tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/tests/drivers/i2s/i2s_api/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/i2s/i2s_api/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/i2s/i2s_api/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/i2s/i2s_api/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/i2s/i2s_api/boards/sam_e70_xplained.overlay b/tests/drivers/i2s/i2s_api/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from tests/drivers/i2s/i2s_api/boards/sam_e70_xplained.overlay rename to tests/drivers/i2s/i2s_api/boards/sam_e70_xplained_same70q21.overlay diff --git a/tests/drivers/i2s/i2s_api/boards/sam_v71_xult.overlay b/tests/drivers/i2s/i2s_api/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from tests/drivers/i2s/i2s_api/boards/sam_v71_xult.overlay rename to tests/drivers/i2s/i2s_api/boards/sam_v71_xult_samv71q21.overlay diff --git a/tests/drivers/i2s/i2s_api/testcase.yaml b/tests/drivers/i2s/i2s_api/testcase.yaml index 5d8b66e29ac..84a1d2bede9 100644 --- a/tests/drivers/i2s/i2s_api/testcase.yaml +++ b/tests/drivers/i2s/i2s_api/testcase.yaml @@ -6,8 +6,8 @@ tests: - userspace filter: not CONFIG_I2S_TEST_USE_GPIO_LOOPBACK platform_exclude: - - mimxrt595_evk_cm33 - - mimxrt685_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 + - mimxrt685_evk drivers.i2s.gpio_loopback: depends_on: - i2s @@ -18,7 +18,7 @@ tests: filter: CONFIG_I2S_TEST_USE_GPIO_LOOPBACK harness: ztest platform_exclude: - - mimxrt595_evk_cm33 - - mimxrt685_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 + - mimxrt685_evk harness_config: fixture: gpio_loopback diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_cm7.conf b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_cm7.conf rename to tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_rt1176_cm7.conf b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_rt1176_cm7.conf new file mode 100644 index 00000000000..9473f58b112 --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_rt1176_cm7.conf @@ -0,0 +1,25 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +# SAI peripheral does not have loopback mode. Use 2 SAI peripherals connected +# together externally. +CONFIG_I2S_TEST_SEPARATE_DEVICES=y + +# CONFIG_DMA_TCD_QUEUE_SIZE sets size of queue used to chain DMA blocks (TCDs) +# together, and should be sized as needed by the application. If not large +# enough, the DMA may starve. Symptoms of this issue include transmit blocks +# repeated, or RX blocks skipped. For I2S driver, queue size must be at least 3. +CONFIG_DMA_TCD_QUEUE_SIZE=4 + +# Repeat test continually to help find intermittent issues +CONFIG_ZTEST_RETEST_IF_PASSED=y + +# I2S and DMA logging can occur in interrupt context, and interfere with I2S +# stream timing. If using either logging, set logging to deferred +# CONFIG_LOG_MODE_DEFERRED=y + +CONFIG_DMA_LOG_LEVEL_OFF=y +CONFIG_I2S_LOG_LEVEL_OFF=y diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_cm33.conf b/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_cm33.conf rename to tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/mbox/mbox_data/CMakeLists.txt b/tests/drivers/mbox/mbox_data/CMakeLists.txt index a410ac3d214..fa444f592df 100644 --- a/tests/drivers/mbox/mbox_data/CMakeLists.txt +++ b/tests/drivers/mbox/mbox_data/CMakeLists.txt @@ -9,10 +9,10 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr) -if(("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm7") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu0")) +if(("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69")) message(STATUS "${BOARD} compile as Main in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/tests/drivers/mbox/mbox_data/Kconfig.sysbuild b/tests/drivers/mbox/mbox_data/Kconfig.sysbuild index 2ddab228177..66a4e929ae2 100644 --- a/tests/drivers/mbox/mbox_data/Kconfig.sysbuild +++ b/tests/drivers/mbox/mbox_data/Kconfig.sysbuild @@ -6,7 +6,7 @@ source "share/sysbuild/Kconfig" config REMOTE_BOARD string - default "mimxrt1170_evkb_cm4" if $(BOARD) = "mimxrt1170_evkb_cm7" - default "mimxrt1170_evk_cm4" if $(BOARD) = "mimxrt1170_evk_cm7" - default "mimxrt1160_evk_cm4" if $(BOARD) = "mimxrt1160_evk_cm7" - default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" + default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb" + default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" + default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" + default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" diff --git a/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_cpu0.conf b/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_cpu0.conf rename to tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_cpu0.overlay b/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_cpu0.overlay rename to tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf new file mode 100644 index 00000000000..583b4950360 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evkb_cm7.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from tests/drivers/mbox/mbox_data/boards/mimxrt1170_evkb_cm7.overlay rename to tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000..583b4950360 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000..870b9928faf --- /dev/null +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,29 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c48000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c48000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c48000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000..0dfb100ed70 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_SECOND_CORE_MCUX=y +CONFIG_INCLUDE_REMOTE_DIR=y diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay new file mode 100644 index 00000000000..870b9928faf --- /dev/null +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -0,0 +1,29 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c48000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c48000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c48000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; diff --git a/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt b/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt index 47e1cae8628..234d58a2164 100644 --- a/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt +++ b/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt @@ -7,10 +7,10 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(("${BOARD}" STREQUAL "mimxrt1170_evkb_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm4") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu1")) +if(("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69")) message(STATUS "${BOARD} compile as remote in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_cpu1.conf b/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf similarity index 100% rename from tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_cpu1.conf rename to tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf diff --git a/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_cpu1.overlay b/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay similarity index 100% rename from tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_cpu1.overlay rename to tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000..0d36a72aec6 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000..3f6115b9c58 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,54 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000..0d36a72aec6 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000..3f6115b9c58 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,54 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000..0d36a72aec6 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000..e3576826702 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,55 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; + +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/tests/drivers/mbox/mbox_data/sysbuild.cmake b/tests/drivers/mbox/mbox_data/sysbuild.cmake index 5c536a6229a..91ee9bf4b6b 100644 --- a/tests/drivers/mbox/mbox_data/sysbuild.cmake +++ b/tests/drivers/mbox/mbox_data/sysbuild.cmake @@ -16,9 +16,9 @@ ExternalZephyrProject_Add( BOARD ${SB_CONFIG_REMOTE_BOARD} ) -if ("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7" OR - "${BOARD}" STREQUAL "mimxrt1170_evk_cm7" OR - "${BOARD}" STREQUAL "mimxrt1160_evk_cm7" +if ("${BOARD}" STREQUAL "mimxrt1170_evkb" OR + "${BOARD}" STREQUAL "mimxrt1170_evk" OR + "${BOARD}" STREQUAL "mimxrt1160_evk" ) # For these NXP boards the main core application is dependent on # 'zephyr_image_info.h' generated by remote application. diff --git a/tests/drivers/mbox/mbox_data/testcase.yaml b/tests/drivers/mbox/mbox_data/testcase.yaml index 72aff63ac3a..0044581cdb8 100644 --- a/tests/drivers/mbox/mbox_data/testcase.yaml +++ b/tests/drivers/mbox/mbox_data/testcase.yaml @@ -5,10 +5,10 @@ tests: - mbox sysbuild: true platform_allow: - - mimxrt1170_evkb_cm7 - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 - - lpcxpresso55s69_cpu0 + - mimxrt1170_evk@B/mimxrt1176/cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 integration_platforms: - - mimxrt1170_evkb_cm7 - - lpcxpresso55s69_cpu0 + - mimxrt1170_evk@B/mimxrt1176/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 diff --git a/tests/drivers/mm/sys_mm_drv_api/testcase.yaml b/tests/drivers/mm/sys_mm_drv_api/testcase.yaml index e25212a3e0a..10c9480cc1e 100644 --- a/tests/drivers/mm/sys_mm_drv_api/testcase.yaml +++ b/tests/drivers/mm/sys_mm_drv_api/testcase.yaml @@ -5,4 +5,4 @@ tests: - mm filter: dt_compat_enabled("intel,adsp-mtl-tlb") or dt_compat_enabled("intel,adsp-tlb") integration_platforms: - - intel_adsp_ace15_mtpm + - intel_adsp/ace15_mtpm diff --git a/tests/drivers/mm/sys_mm_drv_bank/testcase.yaml b/tests/drivers/mm/sys_mm_drv_bank/testcase.yaml index 73ce465b0e6..3bdd847797d 100644 --- a/tests/drivers/mm/sys_mm_drv_bank/testcase.yaml +++ b/tests/drivers/mm/sys_mm_drv_bank/testcase.yaml @@ -5,4 +5,4 @@ tests: - mm filter: dt_compat_enabled("intel,adsp-mtl-tlb") or dt_compat_enabled("intel,adsp-tlb") integration_platforms: - - intel_adsp_ace15_mtpm + - intel_adsp/ace15_mtpm diff --git a/tests/drivers/pwm/pwm_api/boards/rcar_h3ulcb_cr7.overlay b/tests/drivers/pwm/pwm_api/boards/rcar_h3ulcb_r8a77951_r7.overlay similarity index 100% rename from tests/drivers/pwm/pwm_api/boards/rcar_h3ulcb_cr7.overlay rename to tests/drivers/pwm/pwm_api/boards/rcar_h3ulcb_r8a77951_r7.overlay diff --git a/tests/drivers/pwm/pwm_api/src/test_pwm.c b/tests/drivers/pwm/pwm_api/src/test_pwm.c index 867025d99b1..c04bca4568a 100644 --- a/tests/drivers/pwm/pwm_api/src/test_pwm.c +++ b/tests/drivers/pwm/pwm_api/src/test_pwm.c @@ -54,7 +54,7 @@ #error "Define a PWM device" #endif -#if defined(CONFIG_BOARD_COLIBRI_IMX7D_M4) || defined(CONFIG_SOC_MK64F12) || \ +#if defined(CONFIG_BOARD_COLIBRI_IMX7D_MCIMX7D_M4) || defined(CONFIG_SOC_MK64F12) || \ defined(CONFIG_SOC_MKW41Z4) || defined(CONFIG_SOC_SERIES_ESP32S2) || \ defined(CONFIG_SOC_SERIES_ESP32S3) || defined(CONFIG_SOC_SERIES_ESP32C3) #define DEFAULT_PERIOD_CYCLE 1024 @@ -81,7 +81,7 @@ #define DEFAULT_PWM_PORT 2 /* TCC1/WO[2] on PA18 (D7) */ #elif defined CONFIG_BOARD_MIMXRT685_EVK #define DEFAULT_PWM_PORT 7 /* D3 on Arduino connector J27 */ -#elif defined CONFIG_BOARD_LPCXPRESSO55S69_CPU0 +#elif defined CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 #define DEFAULT_PWM_PORT 2 /* D2 on Arduino connector P18 */ #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_pwm) /* Default port should be adapted per board to fit the channel diff --git a/tests/drivers/regulator/fixed/testcase.yaml b/tests/drivers/regulator/fixed/testcase.yaml index 35a80a37669..28f61b36ff4 100644 --- a/tests/drivers/regulator/fixed/testcase.yaml +++ b/tests/drivers/regulator/fixed/testcase.yaml @@ -8,10 +8,10 @@ tests: fixture: gpio_loopback depends_on: gpio platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf9160dk_nrf9160 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf9160dk/nrf9160 integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf9160dk_nrf9160 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf9160dk/nrf9160 diff --git a/tests/drivers/regulator/voltage/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/regulator/voltage/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/regulator/voltage/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/regulator/voltage/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/regulator/voltage/testcase.yaml b/tests/drivers/regulator/voltage/testcase.yaml index 04b83333079..19dac317421 100644 --- a/tests/drivers/regulator/voltage/testcase.yaml +++ b/tests/drivers/regulator/voltage/testcase.yaml @@ -9,7 +9,7 @@ common: tests: drivers.regulator.voltage.nrf52840dk_nrf52840_npm6001: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_npm6001.overlay - SHIELD=npm6001_ek @@ -17,7 +17,7 @@ tests: fixture: npm6001_ek_to_adc drivers.regulator.voltage.nxp: platform_allow: - - mimxrt685_evk_cm33 + - mimxrt685_evk - lpcxpresso55s36 harness_config: fixture: gpio_loopback diff --git a/tests/drivers/retained_mem/api/testcase.yaml b/tests/drivers/retained_mem/api/testcase.yaml index 3ec6a2cf5d4..d5571608333 100644 --- a/tests/drivers/retained_mem/api/testcase.yaml +++ b/tests/drivers/retained_mem/api/testcase.yaml @@ -1,6 +1,6 @@ tests: drivers.retained_mem.api.gpregret: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: - drivers - retained_mem @@ -10,7 +10,7 @@ tests: - drivers - retained_mem drivers.retained_mem.api.ram.nrf52840dk_nrf52840: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840_ram.overlay" - OVERLAY_CONFIG="boards/nrf52840dk_nrf52840_ram.conf" diff --git a/tests/drivers/sensor/generic/testcase.yaml b/tests/drivers/sensor/generic/testcase.yaml index a742d6129ed..80735430c80 100644 --- a/tests/drivers/sensor/generic/testcase.yaml +++ b/tests/drivers/sensor/generic/testcase.yaml @@ -1,7 +1,7 @@ common: integration_platforms: - qemu_x86 - - mps2_an385 + - mps2/an385 tests: drivers.sensor.generic: tags: diff --git a/tests/drivers/sensor/sbs_gauge/boards/qemu_arc_hs.overlay b/tests/drivers/sensor/sbs_gauge/boards/qemu_arc_qemu_arc_hs.overlay similarity index 100% rename from tests/drivers/sensor/sbs_gauge/boards/qemu_arc_hs.overlay rename to tests/drivers/sensor/sbs_gauge/boards/qemu_arc_qemu_arc_hs.overlay diff --git a/tests/drivers/sensor/sbs_gauge/testcase.yaml b/tests/drivers/sensor/sbs_gauge/testcase.yaml index e585ed6f807..eb5170ed155 100644 --- a/tests/drivers/sensor/sbs_gauge/testcase.yaml +++ b/tests/drivers/sensor/sbs_gauge/testcase.yaml @@ -17,7 +17,7 @@ tests: platform_allow: - native_sim - qemu_cortex_a9 - - qemu_arc_hs + - qemu_arc/qemu_arc_hs integration_platforms: - native_sim extra_configs: diff --git a/tests/drivers/spi/spi_loopback/boards/96b_carbon.conf b/tests/drivers/spi/spi_loopback/boards/96b_carbon_stm32f401xe.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/96b_carbon.conf rename to tests/drivers/spi/spi_loopback/boards/96b_carbon_stm32f401xe.conf diff --git a/tests/drivers/spi/spi_loopback/boards/96b_carbon.overlay b/tests/drivers/spi/spi_loopback/boards/96b_carbon_stm32f401xe.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/96b_carbon.overlay rename to tests/drivers/spi/spi_loopback/boards/96b_carbon_stm32f401xe.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/arty_a7_arm_designstart_m1.conf b/tests/drivers/spi/spi_loopback/boards/arty_a7_designstart_fpga_cortex_m1.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/arty_a7_arm_designstart_m1.conf rename to tests/drivers/spi/spi_loopback/boards/arty_a7_designstart_fpga_cortex_m1.conf diff --git a/tests/drivers/spi/spi_loopback/boards/arty_a7_arm_designstart_m1.overlay b/tests/drivers/spi/spi_loopback/boards/arty_a7_designstart_fpga_cortex_m1.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/arty_a7_arm_designstart_m1.overlay rename to tests/drivers/spi/spi_loopback/boards/arty_a7_designstart_fpga_cortex_m1.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/longan_nano_lite.overlay b/tests/drivers/spi/spi_loopback/boards/longan_nano_gd32vf103_lite.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/longan_nano_lite.overlay rename to tests/drivers/spi/spi_loopback/boards/longan_nano_gd32vf103_lite.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/lpcxpresso54114_m4.overlay b/tests/drivers/spi/spi_loopback/boards/lpcxpresso54114_lpc54114_m4.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/lpcxpresso54114_m4.overlay rename to tests/drivers/spi/spi_loopback/boards/lpcxpresso54114_lpc54114_m4.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evkb_cm4.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt1170_evkb_cm4.overlay rename to tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_cm7.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_cm7.conf rename to tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evkb_cm7.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt1170_evkb_cm7.overlay rename to tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_cm33.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_cm33.conf rename to tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/spi/spi_loopback/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/nrf51dk_nrf51422.overlay b/tests/drivers/spi/spi_loopback/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/nrf51dk_nrf51422.overlay rename to tests/drivers/spi/spi_loopback/boards/nrf51dk_nrf51822.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/tdk_robokit1.conf b/tests/drivers/spi/spi_loopback/boards/robokit1.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/tdk_robokit1.conf rename to tests/drivers/spi/spi_loopback/boards/robokit1.conf diff --git a/tests/drivers/spi/spi_loopback/boards/tdk_robokit1.overlay b/tests/drivers/spi/spi_loopback/boards/robokit1.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/tdk_robokit1.overlay rename to tests/drivers/spi/spi_loopback/boards/robokit1.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/rv32m1_vega_ri5cy.overlay b/tests/drivers/spi/spi_loopback/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/rv32m1_vega_ri5cy.overlay rename to tests/drivers/spi/spi_loopback/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/spi/spi_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/spi/spi_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/spi/spi_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/spi/spi_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/sam_e70_xplained.overlay b/tests/drivers/spi/spi_loopback/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/sam_e70_xplained.overlay rename to tests/drivers/spi/spi_loopback/boards/sam_e70_xplained_same70q21.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/sam_v71_xult.overlay b/tests/drivers/spi/spi_loopback/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/sam_v71_xult.overlay rename to tests/drivers/spi/spi_loopback/boards/sam_v71_xult_samv71q21.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/atsamd21_xpro.conf b/tests/drivers/spi/spi_loopback/boards/samd21_xpro.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/atsamd21_xpro.conf rename to tests/drivers/spi/spi_loopback/boards/samd21_xpro.conf diff --git a/tests/drivers/spi/spi_loopback/boards/atsamd21_xpro.overlay b/tests/drivers/spi/spi_loopback/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/atsamd21_xpro.overlay rename to tests/drivers/spi/spi_loopback/boards/samd21_xpro.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/atsame54_xpro.overlay b/tests/drivers/spi/spi_loopback/boards/same54_xpro.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/atsame54_xpro.overlay rename to tests/drivers/spi/spi_loopback/boards/same54_xpro.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/atsamr21_xpro.conf b/tests/drivers/spi/spi_loopback/boards/samr21_xpro.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/atsamr21_xpro.conf rename to tests/drivers/spi/spi_loopback/boards/samr21_xpro.conf diff --git a/tests/drivers/spi/spi_loopback/boards/atsamr21_xpro.overlay b/tests/drivers/spi/spi_loopback/boards/samr21_xpro.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/atsamr21_xpro.overlay rename to tests/drivers/spi/spi_loopback/boards/samr21_xpro.overlay diff --git a/tests/drivers/spi/spi_loopback/testcase.yaml b/tests/drivers/spi/spi_loopback/testcase.yaml index fef5e5b361d..bb2e69961f6 100644 --- a/tests/drivers/spi/spi_loopback/testcase.yaml +++ b/tests/drivers/spi/spi_loopback/testcase.yaml @@ -31,9 +31,9 @@ tests: extra_configs: - CONFIG_SPI_RTIO=y platform_allow: - - tdk_robokit1 - - mimxrt1170_evk_cm7 - - vmu_rt1170 + - robokit1 + - mimxrt1170_evk/mimxrt1176/cm7 + - vmu_rt1170/mimxrt1176/cm7 drivers.spi.mcux_dspi_dma.loopback: extra_args: - OVERLAY_CONFIG="overlay-mcux-dspi-dma.conf" @@ -44,11 +44,11 @@ tests: - OVERLAY_CONFIG="overlay-sam-spi-dma.conf" - DTC_OVERLAY_FILE="overlay-sam-spi-dma.overlay" platform_allow: - - sam_e70_xplained - - sam_v71_xult - - tdk_robokit1 + - sam_e70_xplained/same70q21 + - sam_v71_xult/samv71q21 + - robokit1 integration_platforms: - - sam_e70_xplained + - sam_e70_xplained/same70q21 drivers.spi.stm32_spi_16bits_frames.loopback: extra_args: - OVERLAY_CONFIG="overlay-stm32-spi-16bits.conf" @@ -113,7 +113,7 @@ tests: - gd32vf103c_starter - gd32vf103v_eval - longan_nano - - longan_nano_lite + - longan_nano/gd32vf103/lite drivers.spi.gd32_spi_dma.loopback: extra_args: OVERLAY_CONFIG="overlay-gd32-spi-dma.conf" platform_allow: @@ -126,7 +126,7 @@ tests: - gd32vf103c_starter - gd32vf103v_eval - longan_nano - - longan_nano_lite + - longan_nano/gd32vf103/lite drivers.spi.pl022_spi_interrupt.loopback: extra_configs: - CONFIG_SPI_PL022_INTERRUPT=y diff --git a/tests/drivers/timer/nrf_rtc_timer/testcase.yaml b/tests/drivers/timer/nrf_rtc_timer/testcase.yaml index 9c3f9a94413..d946e37062d 100644 --- a/tests/drivers/timer/nrf_rtc_timer/testcase.yaml +++ b/tests/drivers/timer/nrf_rtc_timer/testcase.yaml @@ -4,10 +4,10 @@ tests: - drivers - timer platform_allow: - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 extra_configs: - CONFIG_ZERO_LATENCY_IRQS=y @@ -16,10 +16,10 @@ tests: - drivers - timer platform_allow: - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 - nrf52_bsim - nrf5340bsim_nrf5340_cpuapp - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000..4f031193d15 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +dut: &lpuart2 { + status = "okay"; + current-speed = <115200>; + nxp,loopback; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000..4f031193d15 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +dut: &lpuart2 { + status = "okay"; + current-speed = <115200>; + nxp,loopback; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000..37f2577dc2a --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +/ { + chosen { + zephyr,sram = &dtcm; + }; +}; + +dut: &lpuart2 { + status = "okay"; + current-speed = <115200>; + nxp,loopback; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/uart/uart_async_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/uart/uart_async_api/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_ns.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_ns.overlay rename to tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsamc21n_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/samc21n_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsamc21n_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/samc21n_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsamd21_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsamd21_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/samd21_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsame54_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/same54_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsame54_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/same54_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsaml21_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/saml21_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsaml21_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/saml21_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsamr21_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/samr21_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsamr21_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/samr21_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsamr34_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/samr34_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsamr34_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/samr34_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_ns.overlay b/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_stm32l562xx_ns.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_ns.overlay rename to tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_stm32l562xx_ns.overlay diff --git a/tests/drivers/uart/uart_async_api/testcase.yaml b/tests/drivers/uart/uart_async_api/testcase.yaml index 8d53d935412..84bbd9c439b 100644 --- a/tests/drivers/uart/uart_async_api/testcase.yaml +++ b/tests/drivers/uart/uart_async_api/testcase.yaml @@ -26,7 +26,7 @@ tests: integration_platforms: - nucleo_h743zi drivers.uart.async_api.nrf_uarte_new: - platform_allow: nrf52840dk_nrf52840 nrf52_bsim + platform_allow: nrf52840dk/nrf52840 nrf52_bsim filter: CONFIG_SERIAL_SUPPORT_ASYNC harness: ztest harness_config: @@ -38,13 +38,13 @@ tests: drivers.uart.async_api.nrf_uart: filter: CONFIG_SERIAL_SUPPORT_ASYNC harness: ztest - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 harness_config: fixture: gpio_loopback depends_on: gpio extra_args: DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840.overlay;boards/nrf_uart.overlay" integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 drivers.uart.async_api.rtt: filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_HAS_SEGGER_RTT and not CONFIG_UART_MCUX_LPUART and not CONFIG_UART_MCUX_FLEXCOMM @@ -63,14 +63,14 @@ tests: harness: ztest depends_on: dma drivers.uart.async_api.sam0: - filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_SOC_FAMILY_SAM0 + filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_SOC_FAMILY_ATMEL_SAM0 platform_allow: - - atsamc21n_xpro - - atsamd21_xpro - - atsaml21_xpro - - atsamr21_xpro - - atsamr34_xpro - - atsame54_xpro + - samc21n_xpro + - samd21_xpro + - saml21_xpro + - samr21_xpro + - samr34_xpro + - same54_xpro extra_configs: - CONFIG_UART_SAM0_ASYNC=y - CONFIG_DMA=y diff --git a/tests/drivers/uart/uart_basic_api/testcase.yaml b/tests/drivers/uart/uart_basic_api/testcase.yaml index ee4fd934660..6d227a2e613 100644 --- a/tests/drivers/uart/uart_basic_api/testcase.yaml +++ b/tests/drivers/uart/uart_basic_api/testcase.yaml @@ -6,7 +6,7 @@ tests: filter: CONFIG_UART_CONSOLE harness: keyboard integration_platforms: - - mps2_an385 + - mps2/an385 drivers.uart.basic_api.wide: extra_configs: - CONFIG_UART_WIDE_DATA=y @@ -26,7 +26,7 @@ tests: filter: CONFIG_UART_CONSOLE harness: keyboard integration_platforms: - - mps2_an385 + - mps2/an385 drivers.uart.basic_api.shell: extra_args: CONF_FILE=prj_shell.conf min_flash: 64 @@ -36,7 +36,7 @@ tests: filter: CONFIG_UART_CONSOLE harness: keyboard integration_platforms: - - mps2_an385 + - mps2/an385 drivers.uart.basic_api.cdc_acm: extra_args: - OVERLAY_CONFIG="overlay-usb.conf" diff --git a/tests/drivers/uart/uart_mix_fifo_poll/src/main.c b/tests/drivers/uart/uart_mix_fifo_poll/src/main.c index aaf97ea8488..2f38354d21e 100644 --- a/tests/drivers/uart/uart_mix_fifo_poll/src/main.c +++ b/tests/drivers/uart/uart_mix_fifo_poll/src/main.c @@ -19,11 +19,11 @@ #if DT_NODE_EXISTS(DT_NODELABEL(dut)) #define UART_NODE DT_NODELABEL(dut) -#elif defined(CONFIG_BOARD_ATSAMD21_XPRO) +#elif defined(CONFIG_BOARD_SAMD21_XPRO) #define UART_NODE DT_NODELABEL(sercom1) -#elif defined(CONFIG_BOARD_ATSAMR21_XPRO) +#elif defined(CONFIG_BOARD_SAMR21_XPRO) #define UART_NODE DT_NODELABEL(sercom3) -#elif defined(CONFIG_BOARD_ATSAME54_XPRO) +#elif defined(CONFIG_BOARD_SAME54_XPRO) #define UART_NODE DT_NODELABEL(sercom1) #else #define UART_NODE DT_CHOSEN(zephyr_console) diff --git a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml index ccfdd1aa717..4cb6c5d1308 100644 --- a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml +++ b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml @@ -5,12 +5,12 @@ common: depends_on: gpio harness: ztest platform_allow: - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf5340dk/nrf5340/cpuapp - nrf52_bsim integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 harness_config: fixture: gpio_loopback tests: diff --git a/tests/drivers/uart/uart_pm/testcase.yaml b/tests/drivers/uart/uart_pm/testcase.yaml index 5417be597e0..f90eed73949 100644 --- a/tests/drivers/uart/uart_pm/testcase.yaml +++ b/tests/drivers/uart/uart_pm/testcase.yaml @@ -4,7 +4,7 @@ common: - uart harness: ztest platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nrf52_bsim harness_config: fixture: gpio_loopback diff --git a/tests/drivers/udc/testcase.yaml b/tests/drivers/udc/testcase.yaml index e15fdd6761c..e43a7a11c16 100644 --- a/tests/drivers/udc/testcase.yaml +++ b/tests/drivers/udc/testcase.yaml @@ -4,5 +4,5 @@ tests: - usb - drivers platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_sim_64 diff --git a/tests/drivers/w1/w1_api/testcase.yaml b/tests/drivers/w1/w1_api/testcase.yaml index 19c283863f2..f35b156ed5c 100644 --- a/tests/drivers/w1/w1_api/testcase.yaml +++ b/tests/drivers/w1/w1_api/testcase.yaml @@ -6,9 +6,9 @@ common: harness: ztest platform_allow: - nucleo_g0b1re - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tests: drivers.w1.w1-serial: diff --git a/tests/drivers/watchdog/wdt_basic_api/testcase.yaml b/tests/drivers/watchdog/wdt_basic_api/testcase.yaml index a2f8ea97f1f..8736f0c20eb 100644 --- a/tests/drivers/watchdog/wdt_basic_api/testcase.yaml +++ b/tests/drivers/watchdog/wdt_basic_api/testcase.yaml @@ -8,14 +8,14 @@ tests: filter: > not (CONFIG_WDT_SAM or dt_compat_enabled("st,stm32-window-watchdog") or dt_compat_enabled("st,stm32-watchdog") or CONFIG_SOC_FAMILY_LPC or - CONFIG_SOC_SERIES_IMX_RT6XX or CONFIG_SOC_SERIES_IMX_RT5XX or - CONFIG_SOC_FAMILY_GD32 or SOC_SERIES_GD32VF103) + CONFIG_SOC_SERIES_IMXRT6XX or CONFIG_SOC_SERIES_IMXRT5XX or + CONFIG_SOC_FAMILY_GD_GD32 or SOC_SERIES_GD32VF103) platform_exclude: - mec15xxevb_assy6853 - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 - - s32z270dc2_rtu0_r52@D - - s32z270dc2_rtu1_r52@D + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 drivers.watchdog.stm32wwdg: filter: dt_compat_enabled("st,stm32-window-watchdog") or dt_compat_enabled("st,stm32-watchdog") extra_args: DTC_OVERLAY_FILE="boards/stm32_wwdg.overlay" @@ -78,7 +78,7 @@ tests: build_only: true platform_allow: mec15xxevb_assy6853 drivers.watchdog.counter_watchdog: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG="boards/nrf52840dk_nrf52840_counter.conf" - DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840_counter.overlay" @@ -117,10 +117,10 @@ tests: drivers.watchdog.nxp_s32: build_only: true platform_allow: - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 - - s32z270dc2_rtu0_r52@D - - s32z270dc2_rtu1_r52@D + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 - mr_canhubk3 drivers.watchdog.mimxrt1050_evk_ti_tps382x: filter: dt_compat_enabled("ti,tps382x") diff --git a/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml b/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml index 0290edbafc1..ea75ad5c6e1 100644 --- a/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml +++ b/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml @@ -4,10 +4,10 @@ tests: drivers.watchdog.reset_none: platform_allow: - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 - - s32z270dc2_rtu0_r52@D - - s32z270dc2_rtu1_r52@D + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 tags: - drivers - watchdog diff --git a/tests/kernel/cache/testcase.yaml b/tests/kernel/cache/testcase.yaml index 37e277c4be2..2c089e26eaf 100644 --- a/tests/kernel/cache/testcase.yaml +++ b/tests/kernel/cache/testcase.yaml @@ -5,13 +5,13 @@ tests: - cache filter: CONFIG_CACHE_MANAGEMENT platform_exclude: - - adp_xc7k_ae350 - - bcm958402m2_m7 + - adp_xc7k/ae350 + - bcm958402m2/bcm58402/m7 - bcm958401m2 integration_platforms: - qemu_xtensa - qemu_cortex_a53 - - nsim_em + - nsim/nsim_em - qemu_x86 - qemu_x86_64 kernel.cache.api.minimallibc: @@ -21,13 +21,13 @@ tests: - libc filter: CONFIG_CACHE_MANAGEMENT and CONFIG_MINIMAL_LIBC_SUPPORTED platform_exclude: - - adp_xc7k_ae350 - - bcm958402m2_m7 + - adp_xc7k/ae350 + - bcm958402m2/bcm58402/m7 - bcm958401m2 integration_platforms: - qemu_xtensa - qemu_cortex_a53 - - nsim_em + - nsim/nsim_em - qemu_x86 - qemu_x86_64 extra_configs: diff --git a/tests/kernel/fatal/exception/testcase.yaml b/tests/kernel/fatal/exception/testcase.yaml index 4304040e6ee..6a471ab59a3 100644 --- a/tests/kernel/fatal/exception/testcase.yaml +++ b/tests/kernel/fatal/exception/testcase.yaml @@ -31,7 +31,7 @@ tests: - kernel - userspace integration_platforms: - - mps2_an385 + - mps2/an385 kernel.common.stack_protection_armv8m_mpu_stack_guard: extra_args: CONF_FILE=prj_armv8m_mpu_stack_guard.conf filter: CONFIG_ARM_MPU and CONFIG_ARMV8_M_MAINLINE @@ -40,7 +40,7 @@ tests: - kernel - userspace integration_platforms: - - mps2_an385 + - mps2/an385 kernel.common.stack_sentinel: extra_args: CONF_FILE=sentinel.conf platform_exclude: diff --git a/tests/kernel/fatal/no-multithreading/testcase.yaml b/tests/kernel/fatal/no-multithreading/testcase.yaml index 973b78aef88..ef0b24a79f5 100644 --- a/tests/kernel/fatal/no-multithreading/testcase.yaml +++ b/tests/kernel/fatal/no-multithreading/testcase.yaml @@ -1,21 +1,21 @@ common: platform_allow: - qemu_cortex_m3 - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs6x - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 - - nsim_em - - nsim_em7d_v22 - - nsim_hs - - nsim_hs_mpuv6 - - nsim_hs5x - - nsim_hs6x + - nsim/nsim_em + - nsim/nsim_em7d_v22 + - nsim/nsim_hs + - nsim/nsim_hs/mpuv6 + - nsim/nsim_hs5x + - nsim/nsim_hs6x integration_platforms: - qemu_cortex_m3 - - nsim_em + - nsim/nsim_em tags: - kernel - scheduler diff --git a/tests/kernel/gen_isr_table/boards/lpcxpresso54114_m4.conf b/tests/kernel/gen_isr_table/boards/lpcxpresso54114_lpc54114_m4.conf similarity index 100% rename from tests/kernel/gen_isr_table/boards/lpcxpresso54114_m4.conf rename to tests/kernel/gen_isr_table/boards/lpcxpresso54114_lpc54114_m4.conf diff --git a/tests/kernel/gen_isr_table/testcase.yaml b/tests/kernel/gen_isr_table/testcase.yaml index a255e0e4caf..1b06037c780 100644 --- a/tests/kernel/gen_isr_table/testcase.yaml +++ b/tests/kernel/gen_isr_table/testcase.yaml @@ -23,8 +23,8 @@ tests: - stmf103_mini - nucleo_f103rb - olimexino_stm32 - - stm32_min_dev_black - - stm32_min_dev_blue + - stm32_min_dev@black + - stm32_min_dev@blue - usb_kw24d512 - v2m_beetle - cc1352r1_launchxl @@ -71,7 +71,7 @@ tests: arch_allow: riscv platform_exclude: - m2gl025_miv - - adp_xc7k_ae350 + - adp_xc7k/ae350 filter: CONFIG_RISCV_PRIVILEGED extra_configs: - CONFIG_GEN_IRQ_VECTOR_TABLE=y diff --git a/tests/kernel/mbox/mbox_api/boards/qemu_x86_tiny_768.conf b/tests/kernel/mbox/mbox_api/boards/qemu_x86_tiny_768.conf deleted file mode 100644 index c10fad4375b..00000000000 --- a/tests/kernel/mbox/mbox_api/boards/qemu_x86_tiny_768.conf +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Need quite some space for coverage. -CONFIG_TEST_EXTRA_STACK_SIZE=1024 diff --git a/tests/kernel/mem_protect/mem_map/boards/qemu_cortex_a53_smp.conf b/tests/kernel/mem_protect/mem_map/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf similarity index 100% rename from tests/kernel/mem_protect/mem_map/boards/qemu_cortex_a53_smp.conf rename to tests/kernel/mem_protect/mem_map/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf diff --git a/tests/kernel/mem_protect/mem_map/boards/qemu_x86_tiny_768.overlay b/tests/kernel/mem_protect/mem_map/boards/qemu_x86_tiny_768.overlay deleted file mode 100644 index dffdf462738..00000000000 --- a/tests/kernel/mem_protect/mem_map/boards/qemu_x86_tiny_768.overlay +++ /dev/null @@ -1,3 +0,0 @@ -&dram0 { - reg = < 0x100000 0x100000 >; -}; diff --git a/tests/kernel/mem_protect/mem_protect/boards/qemu_cortex_a53_smp.conf b/tests/kernel/mem_protect/mem_protect/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf similarity index 100% rename from tests/kernel/mem_protect/mem_protect/boards/qemu_cortex_a53_smp.conf rename to tests/kernel/mem_protect/mem_protect/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf diff --git a/tests/kernel/mem_protect/mem_protect/testcase.yaml b/tests/kernel/mem_protect/mem_protect/testcase.yaml index 39551533e95..efc1553dec5 100644 --- a/tests/kernel/mem_protect/mem_protect/testcase.yaml +++ b/tests/kernel/mem_protect/mem_protect/testcase.yaml @@ -23,9 +23,9 @@ tests: filter: CONFIG_ARCH_HAS_USERSPACE and CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS arch_allow: arm platform_allow: - - efr32_radio_brd4180a - - mps3_an547 - - nrf9160dk_nrf9160 + - efr32_radio/efr32mg21a020f1024im32 + - mps3/an547 + - nrf9160dk/nrf9160 integration_platforms: - - mps3_an547 + - mps3/an547 extra_args: CONFIG_MPU_GAP_FILLING=y diff --git a/tests/kernel/mem_protect/stackprot/boards/qemu_x86_tiny_768.conf b/tests/kernel/mem_protect/stackprot/boards/qemu_x86_tiny_768.conf deleted file mode 100644 index b266485dc1b..00000000000 --- a/tests/kernel/mem_protect/stackprot/boards/qemu_x86_tiny_768.conf +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -# This is needed for coverage. -CONFIG_MAIN_STACK_SIZE=4096 diff --git a/tests/kernel/mem_protect/syscalls/testcase.yaml b/tests/kernel/mem_protect/syscalls/testcase.yaml index 0f2587f3859..1f5210ebc89 100644 --- a/tests/kernel/mem_protect/syscalls/testcase.yaml +++ b/tests/kernel/mem_protect/syscalls/testcase.yaml @@ -1,6 +1,6 @@ tests: kernel.memory_protection.syscalls: - platform_exclude: qemu_arc_em + platform_exclude: qemu_arc/qemu_arc_em filter: CONFIG_ARCH_HAS_USERSPACE arch_exclude: - posix diff --git a/tests/kernel/mem_protect/userspace/boards/mimxrt595_evk_cm33.overlay b/tests/kernel/mem_protect/userspace/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/kernel/mem_protect/userspace/boards/mimxrt595_evk_cm33.overlay rename to tests/kernel/mem_protect/userspace/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/kernel/mem_protect/userspace/boards/mimxrt685_evk_cm33.overlay b/tests/kernel/mem_protect/userspace/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/kernel/mem_protect/userspace/boards/mimxrt685_evk_cm33.overlay rename to tests/kernel/mem_protect/userspace/boards/mimxrt685_evk.overlay diff --git a/tests/kernel/mem_protect/userspace/testcase.yaml b/tests/kernel/mem_protect/userspace/testcase.yaml index 858b341875a..5306d5a7638 100644 --- a/tests/kernel/mem_protect/userspace/testcase.yaml +++ b/tests/kernel/mem_protect/userspace/testcase.yaml @@ -22,9 +22,9 @@ tests: filter: CONFIG_ARCH_HAS_USERSPACE and CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS arch_allow: arm platform_allow: - - efr32_radio_brd4180a - - mps3_an547 - - nrf9160dk_nrf9160 + - efr32_radio/efr32mg21a020f1024im32 + - mps3/an547 + - nrf9160dk/nrf9160 integration_platforms: - - mps3_an547 + - mps3/an547 extra_args: CONFIG_MPU_GAP_FILLING=y diff --git a/tests/kernel/mem_slab/mslab_api/testcase.yaml b/tests/kernel/mem_slab/mslab_api/testcase.yaml index 3f067a1529f..40021091d01 100644 --- a/tests/kernel/mem_slab/mslab_api/testcase.yaml +++ b/tests/kernel/mem_slab/mslab_api/testcase.yaml @@ -10,21 +10,21 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_cortex_m0 - - nsim_em - - nsim_em7d_v22 - - nsim_hs - - nsim_hs_mpuv6 - - nsim_hs5x - - nsim_hs6x - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs6x + - nsim/nsim_em + - nsim/nsim_em7d_v22 + - nsim/nsim_hs + - nsim/nsim_hs/mpuv6 + - nsim/nsim_hs5x + - nsim/nsim_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs6x - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 - qemu_leon3 integration_platforms: - qemu_cortex_m3 - - qemu_arc_hs + - qemu_arc/qemu_arc_hs extra_configs: - CONFIG_MULTITHREADING=n diff --git a/tests/kernel/obj_core/obj_core/testcase.yaml b/tests/kernel/obj_core/obj_core/testcase.yaml index e6bcafafc56..6751c0bcb10 100644 --- a/tests/kernel/obj_core/obj_core/testcase.yaml +++ b/tests/kernel/obj_core/obj_core/testcase.yaml @@ -6,4 +6,4 @@ tests: - qemu_x86 platform_exclude: - qemu_x86_tiny - - qemu_x86_tiny@768 + - qemu_x86_tiny/ia32/768 diff --git a/tests/kernel/obj_core/obj_core_stats/testcase.yaml b/tests/kernel/obj_core/obj_core_stats/testcase.yaml index 28bbaf1ec71..1027cac8fec 100644 --- a/tests/kernel/obj_core/obj_core_stats/testcase.yaml +++ b/tests/kernel/obj_core/obj_core_stats/testcase.yaml @@ -6,4 +6,4 @@ tests: - qemu_x86 platform_exclude: - qemu_x86_tiny - - qemu_x86_tiny@768 + - qemu_x86_tiny/ia32/768 diff --git a/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml b/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml index c17ff99e213..2c4ecb5bc21 100644 --- a/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml +++ b/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml @@ -6,4 +6,4 @@ tests: - qemu_x86 platform_exclude: - qemu_x86_tiny - - qemu_x86_tiny@768 + - qemu_x86_tiny/ia32/768 diff --git a/tests/kernel/poll/testcase.yaml b/tests/kernel/poll/testcase.yaml index 5eb5fc9a626..fdf503e3615 100644 --- a/tests/kernel/poll/testcase.yaml +++ b/tests/kernel/poll/testcase.yaml @@ -4,10 +4,10 @@ tests: tags: - kernel - userspace - # FIXME: qemu_arc_hs6x is excluded due to a run-time failure, see #49492 + # FIXME: qemu_arc/qemu_arc_hs6x is excluded due to a run-time failure, see #49492 platform_exclude: - - nrf52dk_nrf52810 - - qemu_arc_hs6x + - nrf52dk/nrf52810 + - qemu_arc/qemu_arc_hs6x kernel.poll.minimallibc: filter: CONFIG_MINIMAL_LIBC_SUPPORTED ignore_faults: true @@ -15,9 +15,9 @@ tests: - kernel - userspace - libc - # FIXME: qemu_arc_hs6x is excluded due to a run-time failure, see #49492 + # FIXME: qemu_arc/qemu_arc_hs6x is excluded due to a run-time failure, see #49492 platform_exclude: - - nrf52dk_nrf52810 - - qemu_arc_hs6x + - nrf52dk/nrf52810 + - qemu_arc/qemu_arc_hs6x extra_configs: - CONFIG_MINIMAL_LIBC=y diff --git a/tests/kernel/profiling/profiling_api/testcase.yaml b/tests/kernel/profiling/profiling_api/testcase.yaml index aeec61bad8a..d4dad4abd08 100644 --- a/tests/kernel/profiling/profiling_api/testcase.yaml +++ b/tests/kernel/profiling/profiling_api/testcase.yaml @@ -2,11 +2,13 @@ tests: kernel.common.profiling: arch_exclude: nios2 platform_exclude: - - em_starterkit + - em_starterkit/emsk_em7d + - em_starterkit/emsk_em9d + - em_starterkit/emsk_em11d - litex_vexriscv - - rv32m1_vega_zero_riscy - - rv32m1_vega_ri5cy - - nrf5340dk_nrf5340_cpunet + - rv32m1_vega/openisa_rv32m1/zero_riscy + - rv32m1_vega/openisa_rv32m1/ri5cy + - nrf5340dk/nrf5340/cpunet tags: - kernel - pm diff --git a/tests/kernel/sched/metairq/testcase.yaml b/tests/kernel/sched/metairq/testcase.yaml index 041d7d0b696..53b0a8a0b53 100644 --- a/tests/kernel/sched/metairq/testcase.yaml +++ b/tests/kernel/sched/metairq/testcase.yaml @@ -1,4 +1,4 @@ tests: kernel.scheduler.metairq: tags: kernel - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 diff --git a/tests/kernel/sched/preempt/testcase.yaml b/tests/kernel/sched/preempt/testcase.yaml index 5aa32450d8e..affc1ce1944 100644 --- a/tests/kernel/sched/preempt/testcase.yaml +++ b/tests/kernel/sched/preempt/testcase.yaml @@ -1,4 +1,4 @@ tests: kernel.scheduler.preempt: tags: kernel - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 diff --git a/tests/kernel/smp/boards/qemu_cortex_a53_smp.conf b/tests/kernel/smp/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf similarity index 100% rename from tests/kernel/smp/boards/qemu_cortex_a53_smp.conf rename to tests/kernel/smp/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf diff --git a/tests/kernel/smp/boards/qemu_cortex_a53_smp.overlay b/tests/kernel/smp/boards/qemu_cortex_a53_qemu_cortex_a53_smp.overlay similarity index 100% rename from tests/kernel/smp/boards/qemu_cortex_a53_smp.overlay rename to tests/kernel/smp/boards/qemu_cortex_a53_qemu_cortex_a53_smp.overlay diff --git a/tests/kernel/smp_boot_delay/testcase.yaml b/tests/kernel/smp_boot_delay/testcase.yaml index 3aef08bc67e..ea84c6d2cf0 100644 --- a/tests/kernel/smp_boot_delay/testcase.yaml +++ b/tests/kernel/smp_boot_delay/testcase.yaml @@ -3,7 +3,7 @@ tests: tags: - kernel - smp - platform_allow: intel_adsp_cavs25 qemu_x86_64 + platform_allow: intel_adsp/cavs25 qemu_x86_64 integration_platforms: - qemu_x86_64 kernel.multiprocessing.smp_boot_delay.minimallibc: @@ -12,7 +12,7 @@ tests: - kernel - smp - libc - platform_allow: intel_adsp_cavs25 qemu_x86_64 + platform_allow: intel_adsp/cavs25 qemu_x86_64 integration_platforms: - qemu_x86_64 extra_configs: diff --git a/tests/kernel/threads/dynamic_thread_stack/testcase.yaml b/tests/kernel/threads/dynamic_thread_stack/testcase.yaml index 69f5651406f..27bfe6602fb 100644 --- a/tests/kernel/threads/dynamic_thread_stack/testcase.yaml +++ b/tests/kernel/threads/dynamic_thread_stack/testcase.yaml @@ -3,15 +3,15 @@ common: min_ram: 32 integration_platforms: - qemu_x86 - - qemu_x86_nommu + - qemu_x86/atom/nommu - qemu_x86_64 - qemu_cortex_a53 - - qemu_cortex_a53_smp + - qemu_cortex_a53/qemu_cortex_a53/smp - qemu_cortex_m3 - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 - - qemu_riscv64_smp + - qemu_riscv64/qemu_virt_riscv64/smp # Permutations of (pool | alloc | user) tests: diff --git a/tests/kernel/threads/no-multithreading/testcase.yaml b/tests/kernel/threads/no-multithreading/testcase.yaml index d29165f683c..ae0556c54c6 100644 --- a/tests/kernel/threads/no-multithreading/testcase.yaml +++ b/tests/kernel/threads/no-multithreading/testcase.yaml @@ -5,20 +5,20 @@ tests: platform_allow: - qemu_cortex_m0 - qemu_cortex_m3 - - mps2_an385 - - mps2_an521 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf51dk_nrf51422 - - nsim_em - - nsim_em7d_v22 - - nsim_hs - - nsim_hs_mpuv6 - - nsim_hs5x - - nsim_hs6x - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs6x + - mps2/an385 + - mps2/an521/cpu0 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf51dk/nrf51822 + - nsim/nsim_em + - nsim/nsim_em7d_v22 + - nsim/nsim_hs + - nsim/nsim_hs/mpuv6 + - nsim/nsim_hs5x + - nsim/nsim_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs6x - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 diff --git a/tests/kernel/threads/thread_stack/testcase.yaml b/tests/kernel/threads/thread_stack/testcase.yaml index 5303a8ee698..ed47161b97d 100644 --- a/tests/kernel/threads/thread_stack/testcase.yaml +++ b/tests/kernel/threads/thread_stack/testcase.yaml @@ -7,7 +7,7 @@ tests: ignore_faults: true min_ram: 16 integration_platforms: - - mps2_an521 + - mps2/an521/cpu0 - qemu_x86 kernel.threads.armv8m_mpu_stack_guard: min_ram: 16 @@ -20,4 +20,4 @@ tests: - userspace ignore_faults: true integration_platforms: - - mps2_an521 + - mps2/an521/cpu0 diff --git a/tests/kernel/tickless/tickless_concept/testcase.yaml b/tests/kernel/tickless/tickless_concept/testcase.yaml index f4c1f95da98..186f76d539d 100644 --- a/tests/kernel/tickless/tickless_concept/testcase.yaml +++ b/tests/kernel/tickless/tickless_concept/testcase.yaml @@ -5,9 +5,9 @@ tests: # consistently when coverage is enabled. Disable until 14173 is fixed. platform_exclude: - litex_vexriscv - - rv32m1_vega_zero_riscy - - rv32m1_vega_ri5cy - - nrf5340dk_nrf5340_cpunet + - rv32m1_vega/openisa_rv32m1/zero_riscy + - rv32m1_vega/openisa_rv32m1/ri5cy + - nrf5340dk/nrf5340/cpunet - nucleo_l073rz tags: - kernel diff --git a/tests/kernel/timer/timer_api/testcase.yaml b/tests/kernel/timer/timer_api/testcase.yaml index 82919939e43..9337459bf51 100644 --- a/tests/kernel/timer/timer_api/testcase.yaml +++ b/tests/kernel/timer/timer_api/testcase.yaml @@ -11,9 +11,9 @@ tests: - posix platform_exclude: - litex_vexriscv - - rv32m1_vega_zero_riscy - - rv32m1_vega_ri5cy - - nrf5340dk_nrf5340_cpunet + - rv32m1_vega/openisa_rv32m1/zero_riscy + - rv32m1_vega/openisa_rv32m1/ri5cy + - nrf5340dk/nrf5340/cpunet tags: - kernel - timer @@ -25,19 +25,19 @@ tests: - timer platform_allow: - qemu_cortex_m3 - - nsim_em - - nsim_em7d_v22 - - nsim_hs - - nsim_hs_mpuv6 - - nsim_hs5x - - nsim_hs6x - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs6x + - nsim/nsim_em + - nsim/nsim_em7d_v22 + - nsim/nsim_hs + - nsim/nsim_hs/mpuv6 + - nsim/nsim_hs5x + - nsim/nsim_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs6x - qemu_leon3 integration_platforms: - qemu_cortex_m3 - - nsim_em + - nsim/nsim_em extra_configs: - CONFIG_MULTITHREADING=n - CONFIG_TEST_USERSPACE=n diff --git a/tests/kernel/timer/timer_monotonic/testcase.yaml b/tests/kernel/timer/timer_monotonic/testcase.yaml index 9c38d456986..075f3009e8f 100644 --- a/tests/kernel/timer/timer_monotonic/testcase.yaml +++ b/tests/kernel/timer/timer_monotonic/testcase.yaml @@ -3,9 +3,9 @@ tests: tags: - kernel - timer - # FIXME: This test may fail for qemu_arc_hs on certain host systems. + # FIXME: This test may fail for qemu_arc/qemu_arc_hs on certain host systems. # See foss-for-synopsys-dwc-arc-processors/qemu#67. - platform_exclude: qemu_arc_hs + platform_exclude: qemu_arc/qemu_arc_hs kernel.timer.monotonic.apic.tsc: tags: - kernel @@ -20,6 +20,6 @@ tests: tags: - kernel - timer - platform_allow: mps2_an385 + platform_allow: mps2/an385 extra_configs: - CONFIG_QEMU_ICOUNT=n diff --git a/tests/kernel/usage/thread_runtime_stats/testcase.yaml b/tests/kernel/usage/thread_runtime_stats/testcase.yaml index 05fabf3ba57..671a01b8a19 100644 --- a/tests/kernel/usage/thread_runtime_stats/testcase.yaml +++ b/tests/kernel/usage/thread_runtime_stats/testcase.yaml @@ -15,6 +15,6 @@ tests: filter: not CONFIG_SMP integration_platforms: - qemu_x86 - - mps2_an385 + - mps2/an385 platform_exclude: - mr_canhubk3 diff --git a/tests/kernel/workq/critical/testcase.yaml b/tests/kernel/workq/critical/testcase.yaml index 822e6d2af99..7ba31c3661c 100644 --- a/tests/kernel/workq/critical/testcase.yaml +++ b/tests/kernel/workq/critical/testcase.yaml @@ -4,7 +4,7 @@ common: - workqueue tests: kernel.workqueue.critical: - platform_exclude: nsim_sem_mpu_stack_guard + platform_exclude: nsim/nsim_sem/mpu_stack_guard filter: not CONFIG_WDT_SAM integration_platforms: - qemu_x86 @@ -13,8 +13,8 @@ tests: extra_configs: - CONFIG_WDT_DISABLE_AT_BOOT=y integration_platforms: - - sam_e70_xplained + - sam_e70_xplained/same70q21 kernel.workqueue.critical.nsim: - platform_allow: nsim_sem_mpu_stack_guard + platform_allow: nsim/nsim_sem/mpu_stack_guard extra_configs: - CONFIG_TEST_HW_STACK_PROTECTION=n diff --git a/tests/kernel/xip/testcase.yaml b/tests/kernel/xip/testcase.yaml index 0992d219064..44360ec5bee 100644 --- a/tests/kernel/xip/testcase.yaml +++ b/tests/kernel/xip/testcase.yaml @@ -5,15 +5,15 @@ tests: - kernel - xip integration_platforms: - - qemu_arc_em - - qemu_x86_xip + - qemu_arc/qemu_arc_em + - qemu_x86/atom/xip arch.common.xip.minimallibc: filter: CONFIG_XIP and CONFIG_MINIMAL_LIBC_SUPPORTED tags: - kernel - xip integration_platforms: - - qemu_arc_em - - qemu_x86_xip + - qemu_arc/qemu_arc_em + - qemu_x86/atom/xip extra_configs: - CONFIG_MINIMAL_LIBC=y diff --git a/tests/lib/c_lib/common/testcase.yaml b/tests/lib/c_lib/common/testcase.yaml index 28a7d54194c..4d184b9536f 100644 --- a/tests/lib/c_lib/common/testcase.yaml +++ b/tests/lib/c_lib/common/testcase.yaml @@ -3,7 +3,7 @@ common: - clib ignore_faults: true integration_platforms: - - mps2_an385 + - mps2/an385 tests: libraries.libc.common: {} libraries.libc.common.minimal: diff --git a/tests/lib/cmsis_dsp/bayes/testcase.yaml b/tests/lib/cmsis_dsp/bayes/testcase.yaml index 3e0ae0018b9..abdc24b7335 100644 --- a/tests/lib/cmsis_dsp/bayes/testcase.yaml +++ b/tests/lib/cmsis_dsp/bayes/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: - cmsis-dsp @@ -15,8 +15,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/complexmath/testcase.yaml b/tests/lib/cmsis_dsp/complexmath/testcase.yaml index 58eae41629a..5dda156a111 100644 --- a/tests/lib/cmsis_dsp/complexmath/testcase.yaml +++ b/tests/lib/cmsis_dsp/complexmath/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim - native_posix tags: cmsis-dsp @@ -15,8 +15,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/distance/testcase.yaml b/tests/lib/cmsis_dsp/distance/testcase.yaml index 6c2bc20659e..b44b53af16e 100644 --- a/tests/lib/cmsis_dsp/distance/testcase.yaml +++ b/tests/lib/cmsis_dsp/distance/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis_dsp min_flash: 64 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/fastmath/testcase.yaml b/tests/lib/cmsis_dsp/fastmath/testcase.yaml index 8524cb01a60..27665a80250 100644 --- a/tests/lib/cmsis_dsp/fastmath/testcase.yaml +++ b/tests/lib/cmsis_dsp/fastmath/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis_dsp min_flash: 128 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/filtering/testcase.yaml b/tests/lib/cmsis_dsp/filtering/testcase.yaml index eb620938560..ef45599a827 100644 --- a/tests/lib/cmsis_dsp/filtering/testcase.yaml +++ b/tests/lib/cmsis_dsp/filtering/testcase.yaml @@ -12,8 +12,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis_dsp min_flash: 128 @@ -25,8 +25,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -41,8 +41,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -54,8 +54,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -70,8 +70,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -83,8 +83,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -99,8 +99,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 256 @@ -112,9 +112,9 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote + - mps2/an521/cpu1 platform_exclude: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/interpolation/testcase.yaml b/tests/lib/cmsis_dsp/interpolation/testcase.yaml index 2631b5ef19f..7c5b5163715 100644 --- a/tests/lib/cmsis_dsp/interpolation/testcase.yaml +++ b/tests/lib/cmsis_dsp/interpolation/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/matrix/testcase.yaml b/tests/lib/cmsis_dsp/matrix/testcase.yaml index 10a2c60ab3b..36aea53d84b 100644 --- a/tests/lib/cmsis_dsp/matrix/testcase.yaml +++ b/tests/lib/cmsis_dsp/matrix/testcase.yaml @@ -9,8 +9,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -22,8 +22,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -38,8 +38,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -51,8 +51,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -67,8 +67,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -80,8 +80,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -96,8 +96,8 @@ tests: and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 tags: cmsis-dsp min_flash: 128 min_ram: 64 @@ -108,8 +108,8 @@ tests: filter: (CONFIG_CMSIS_DSP_FLOAT16 and (CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -124,8 +124,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -137,8 +137,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -153,8 +153,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -166,8 +166,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -182,8 +182,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp platform_exclude: frdm_kw41z @@ -196,8 +196,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -213,8 +213,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp platform_exclude: frdm_kw41z @@ -227,8 +227,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -244,8 +244,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp platform_exclude: frdm_kw41z @@ -258,8 +258,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -275,8 +275,8 @@ tests: and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 tags: cmsis-dsp min_flash: 128 min_ram: 144 @@ -287,8 +287,8 @@ tests: filter: (CONFIG_CMSIS_DSP_FLOAT16 and (CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -303,8 +303,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp platform_exclude: frdm_kw41z @@ -317,8 +317,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -334,8 +334,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp platform_exclude: frdm_kw41z @@ -348,8 +348,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/quaternionmath/testcase.yaml b/tests/lib/cmsis_dsp/quaternionmath/testcase.yaml index f8c45b290eb..e6d59cd451a 100644 --- a/tests/lib/cmsis_dsp/quaternionmath/testcase.yaml +++ b/tests/lib/cmsis_dsp/quaternionmath/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/statistics/testcase.yaml b/tests/lib/cmsis_dsp/statistics/testcase.yaml index 1c142870ff3..a6ec436ee11 100644 --- a/tests/lib/cmsis_dsp/statistics/testcase.yaml +++ b/tests/lib/cmsis_dsp/statistics/testcase.yaml @@ -4,8 +4,8 @@ tests: and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -15,8 +15,8 @@ tests: and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/support/testcase.yaml b/tests/lib/cmsis_dsp/support/testcase.yaml index c9ac7fd6dc7..254684346f3 100644 --- a/tests/lib/cmsis_dsp/support/testcase.yaml +++ b/tests/lib/cmsis_dsp/support/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/svm/testcase.yaml b/tests/lib/cmsis_dsp/svm/testcase.yaml index a187e2e2648..895a32bd181 100644 --- a/tests/lib/cmsis_dsp/svm/testcase.yaml +++ b/tests/lib/cmsis_dsp/svm/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/transform/testcase.yaml b/tests/lib/cmsis_dsp/transform/testcase.yaml index d4e1ecb980e..3e4fb163cb0 100644 --- a/tests/lib/cmsis_dsp/transform/testcase.yaml +++ b/tests/lib/cmsis_dsp/transform/testcase.yaml @@ -9,8 +9,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 512 @@ -22,7 +22,7 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -37,8 +37,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 512 @@ -50,7 +50,7 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -65,8 +65,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 1024 @@ -91,8 +91,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 1024 @@ -117,8 +117,8 @@ tests: and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 tags: cmsis-dsp min_flash: 512 min_ram: 64 @@ -129,7 +129,7 @@ tests: filter: (CMSIS_DSP_FLOAT16 and (CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -144,8 +144,8 @@ tests: and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 tags: cmsis-dsp min_flash: 512 min_ram: 64 @@ -156,7 +156,7 @@ tests: filter: (CMSIS_DSP_FLOAT16 and (CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -171,8 +171,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 1024 @@ -197,8 +197,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 512 @@ -210,7 +210,7 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -225,8 +225,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 1024 @@ -251,8 +251,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 1024 diff --git a/tests/lib/cmsis_nn/testcase.yaml b/tests/lib/cmsis_nn/testcase.yaml index 438c267ef5c..3952266880e 100644 --- a/tests/lib/cmsis_nn/testcase.yaml +++ b/tests/lib/cmsis_nn/testcase.yaml @@ -3,8 +3,8 @@ tests: filter: CONFIG_CPU_CORTEX_M and CONFIG_FULL_LIBC_SUPPORTED integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 tags: cmsis_nn min_flash: 64 min_ram: 32 diff --git a/tests/lib/cpp/cxx/testcase.yaml b/tests/lib/cpp/cxx/testcase.yaml index f06b451742b..5d130869605 100644 --- a/tests/lib/cpp/cxx/testcase.yaml +++ b/tests/lib/cpp/cxx/testcase.yaml @@ -2,7 +2,7 @@ common: tags: cpp toolchain_exclude: xcc integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_cortex_a53 tests: @@ -36,9 +36,9 @@ tests: arch_exclude: posix # Exclude nRF54L15 and nRF54H20 as Nordic HAL is not compatible with C++98. platform_exclude: - - nrf54l15pdk_nrf54l15_cpuapp - - nrf54h20pdk_nrf54h20_cpuapp - - nrf54h20pdk_nrf54h20_cpurad + - nrf54l15pdk/nrf54l15/cpuapp + - nrf54h20pdk/nrf54h20/cpuapp + - nrf54h20pdk/nrf54h20/cpurad build_only: true extra_configs: - CONFIG_STD_CPP98=y diff --git a/tests/lib/cpp/libcxx/testcase.yaml b/tests/lib/cpp/libcxx/testcase.yaml index a75430644c8..fdf0318ebd2 100644 --- a/tests/lib/cpp/libcxx/testcase.yaml +++ b/tests/lib/cpp/libcxx/testcase.yaml @@ -10,7 +10,7 @@ tests: - CONFIG_GLIBCXX_LIBCPP=y - CONFIG_CPP_EXCEPTIONS=y integration_platforms: - - mps2_an385 + - mps2/an385 cpp.libcxx.glibcxx.newlib_nano: filter: TOOLCHAIN_HAS_NEWLIB == 1 toolchain_exclude: xcc @@ -22,7 +22,7 @@ tests: - CONFIG_NEWLIB_LIBC_NANO=y - CONFIG_GLIBCXX_LIBCPP=y integration_platforms: - - mps2_an385 + - mps2/an385 cpp.libcxx.glibcxx.picolibc: filter: TOOLCHAIN_HAS_PICOLIBC == 1 toolchain_exclude: xcc @@ -33,7 +33,7 @@ tests: - CONFIG_GLIBCXX_LIBCPP=y - CONFIG_CPP_EXCEPTIONS=y integration_platforms: - - mps2_an385 + - mps2/an385 cpp.libcxx.arcmwdtlib: toolchain_allow: arcmwdt min_flash: 54 diff --git a/tests/lib/heap/src/main.c b/tests/lib/heap/src/main.c index 7db993dc035..a87cc91c480 100644 --- a/tests/lib/heap/src/main.c +++ b/tests/lib/heap/src/main.c @@ -14,7 +14,7 @@ */ #if defined(CONFIG_SOC_MPS2_AN521) && defined(CONFIG_QEMU_TARGET) -/* mps2_an521 blows up if allowed to link into large area, even though +/* mps2/an521 blows up if allowed to link into large area, even though * the link is successful and it claims the memory is there. We get * hard faults on boot in qemu before entry to cstart() once MEMSZ is * allowed to get near 256kb. diff --git a/tests/lib/heap/testcase.yaml b/tests/lib/heap/testcase.yaml index 4427788fb07..8ed06a7431e 100644 --- a/tests/lib/heap/testcase.yaml +++ b/tests/lib/heap/testcase.yaml @@ -13,7 +13,6 @@ tests: - qemu_xtensa - esp32s2_saola - esp32s2_lolin_mini - - esp32s3_devkitm filter: not CONFIG_SOC_NSIM timeout: 480 integration_platforms: diff --git a/tests/lib/heap_align/testcase.yaml b/tests/lib/heap_align/testcase.yaml index 3dba0fad765..f9b499b6d5f 100644 --- a/tests/lib/heap_align/testcase.yaml +++ b/tests/lib/heap_align/testcase.yaml @@ -5,4 +5,4 @@ tests: - heap_align integration_platforms: - native_sim - - mps2_an521 + - mps2/an521/cpu0 diff --git a/tests/lib/mpsc_pbuf/testcase.yaml b/tests/lib/mpsc_pbuf/testcase.yaml index 61341277ec1..f2665aa93f5 100644 --- a/tests/lib/mpsc_pbuf/testcase.yaml +++ b/tests/lib/mpsc_pbuf/testcase.yaml @@ -2,8 +2,8 @@ tests: libraries.mpsc_pbuf: tags: mpsc_pbuf platform_allow: - - qemu_arc_em - - qemu_arc_hs + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs - qemu_cortex_a53 - qemu_cortex_m0 - qemu_cortex_m3 diff --git a/tests/lib/multi_heap/testcase.yaml b/tests/lib/multi_heap/testcase.yaml index 7780e09193a..f327881614f 100644 --- a/tests/lib/multi_heap/testcase.yaml +++ b/tests/lib/multi_heap/testcase.yaml @@ -10,15 +10,15 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_cortex_m0 - - nsim_em - - nsim_em7d_v22 - - nsim_hs - - nsim_hs_mpuv6 - - nsim_hs5x - - nsim_hs6x - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs6x + - nsim/nsim_em + - nsim/nsim_em7d_v22 + - nsim/nsim_hs + - nsim/nsim_hs/mpuv6 + - nsim/nsim_hs5x + - nsim/nsim_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs6x - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 diff --git a/tests/lib/newlib/heap_listener/testcase.yaml b/tests/lib/newlib/heap_listener/testcase.yaml index a4620e464cc..6c8d5b8ef1f 100644 --- a/tests/lib/newlib/heap_listener/testcase.yaml +++ b/tests/lib/newlib/heap_listener/testcase.yaml @@ -6,5 +6,5 @@ tests: filter: TOOLCHAIN_HAS_NEWLIB == 1 arch_exclude: posix integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 diff --git a/tests/lib/newlib/thread_safety/testcase.yaml b/tests/lib/newlib/thread_safety/testcase.yaml index 91b5d650083..9071f59a5e4 100644 --- a/tests/lib/newlib/thread_safety/testcase.yaml +++ b/tests/lib/newlib/thread_safety/testcase.yaml @@ -5,7 +5,7 @@ common: - clib - newlib integration_platforms: - - mps2_an521 + - mps2/an521/cpu0 - qemu_x86 tests: libraries.libc.newlib.thread_safety: diff --git a/tests/lib/shared_multi_heap/testcase.yaml b/tests/lib/shared_multi_heap/testcase.yaml index 5580716785d..c821457bb9c 100644 --- a/tests/lib/shared_multi_heap/testcase.yaml +++ b/tests/lib/shared_multi_heap/testcase.yaml @@ -5,7 +5,7 @@ tests: libraries.shared_multi_heap: platform_allow: - qemu_cortex_a53 - - mps2_an521 + - mps2/an521/cpu0 integration_platforms: - qemu_cortex_a53 tags: diff --git a/tests/lib/sprintf/testcase.yaml b/tests/lib/sprintf/testcase.yaml index 2fb0850fb03..860b4318874 100644 --- a/tests/lib/sprintf/testcase.yaml +++ b/tests/lib/sprintf/testcase.yaml @@ -4,7 +4,7 @@ common: tests: libraries.libc.sprintf: extra_args: CONF_FILE=prj.conf - filter: not CONFIG_SOC_MCIMX7_M4 and CONFIG_STDOUT_CONSOLE + filter: not CONFIG_SOC_MCIMX7D_M4 and CONFIG_STDOUT_CONSOLE integration_platforms: - qemu_x86 arch_exclude: posix diff --git a/tests/lib/time/testcase.yaml b/tests/lib/time/testcase.yaml index f4e8d91ec1b..9b002ace2d9 100644 --- a/tests/lib/time/testcase.yaml +++ b/tests/lib/time/testcase.yaml @@ -3,7 +3,7 @@ tests: tags: libc timeout: 180 integration_platforms: - - mps2_an385 + - mps2/an385 platform_exclude: - native_posix - native_posix_64 diff --git a/tests/misc/test_build/testcase.yaml b/tests/misc/test_build/testcase.yaml index 42732457c42..e7217a3c054 100644 --- a/tests/misc/test_build/testcase.yaml +++ b/tests/misc/test_build/testcase.yaml @@ -1,9 +1,9 @@ tests: buildsystem.debug.build: platform_exclude: - - lpcxpresso55s69_ns - - nrf9160dk_nrf9160_ns - - nrf5340dk_nrf5340_cpuapp_ns + - lpcxpresso55s69/lpc55s69/cpu0/ns + - nrf9160dk/nrf9160/ns + - nrf5340dk/nrf5340/cpuapp/ns build_only: true extra_args: CONF_FILE=debug.conf tags: debug @@ -14,13 +14,13 @@ tests: tags: mcuboot build_only: true platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 extra_configs: - CONFIG_BOOTLOADER_MCUBOOT=y integration_platforms: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 buildsystem.kconfig.utf8_in_values: build_only: true tags: kconfig diff --git a/tests/modules/thrift/ThriftTest/testcase.yaml b/tests/modules/thrift/ThriftTest/testcase.yaml index cc92bef771e..760b2a6fae6 100644 --- a/tests/modules/thrift/ThriftTest/testcase.yaml +++ b/tests/modules/thrift/ThriftTest/testcase.yaml @@ -8,7 +8,7 @@ common: # qemu_x86 exluded due to missing long double functions in SDK # See https://github.com/zephyrproject-rtos/sdk-ng/issues/603 platform_allow: - - mps2_an385 + - mps2/an385 - qemu_cortex_a53 - qemu_riscv32 - qemu_riscv64 diff --git a/tests/net/lib/dns_sd/prj-no-ipv6.conf b/tests/net/lib/dns_sd/prj-no-ipv6.conf index d973914fa47..f06b5ca10bc 100644 --- a/tests/net/lib/dns_sd/prj-no-ipv6.conf +++ b/tests/net/lib/dns_sd/prj-no-ipv6.conf @@ -24,5 +24,5 @@ CONFIG_DNS_SD_LOG_LEVEL_DBG=y CONFIG_ZTEST=y CONFIG_ZTEST_STACK_SIZE=2048 -# Maybe avoid stack overflow on mps2_an385? +# Maybe avoid stack overflow on mps2/an385? CONFIG_MAIN_STACK_SIZE=2048 diff --git a/tests/net/lib/dns_sd/prj.conf b/tests/net/lib/dns_sd/prj.conf index f53083ff72d..6655eb94323 100644 --- a/tests/net/lib/dns_sd/prj.conf +++ b/tests/net/lib/dns_sd/prj.conf @@ -17,7 +17,7 @@ CONFIG_DNS_SD_LOG_LEVEL_DBG=y CONFIG_ZTEST=y CONFIG_ZTEST_STACK_SIZE=2048 -# Maybe avoid stack overflow on mps2_an385? +# Maybe avoid stack overflow on mps2/an385? CONFIG_MAIN_STACK_SIZE=2048 CONFIG_NET_MAX_CONTEXTS=8 diff --git a/tests/net/ptp/clock/testcase.yaml b/tests/net/ptp/clock/testcase.yaml index 1d724695337..6d5134dcf6f 100644 --- a/tests/net/ptp/clock/testcase.yaml +++ b/tests/net/ptp/clock/testcase.yaml @@ -3,7 +3,7 @@ common: # We can only run this in platforms that support PTP clock platform_allow: - frdm_k64f - - sam_e70_xplained + - sam_e70_xplained/same70q21 - native_posix - native_sim integration_platforms: diff --git a/tests/net/socket/poll/testcase.yaml b/tests/net/socket/poll/testcase.yaml index 54da5b83b7d..56ac475d13e 100644 --- a/tests/net/socket/poll/testcase.yaml +++ b/tests/net/socket/poll/testcase.yaml @@ -1,9 +1,9 @@ common: depends_on: netif - # FIXME: This test fails very frequently on mps2_an385 due to the system + # FIXME: This test fails very frequently on mps2/an385 due to the system # timer stability issues, so keep it disabled until the root cause # is fixed (GitHub issue zephyrproject-rtos/zephyr#48608). - platform_exclude: mps2_an385 + platform_exclude: mps2/an385 tests: net.socket.poll: min_ram: 21 diff --git a/tests/net/socket/reuseaddr_reuseport/testcase.yaml b/tests/net/socket/reuseaddr_reuseport/testcase.yaml index c1a4808d1d3..fcfce0b1e49 100644 --- a/tests/net/socket/reuseaddr_reuseport/testcase.yaml +++ b/tests/net/socket/reuseaddr_reuseport/testcase.yaml @@ -5,10 +5,10 @@ common: tags: - net - socket - # FIXME: This test fails very frequently on mps2_an385 due to the system + # FIXME: This test fails very frequently on mps2/an385 due to the system # timer stability issues, so keep it disabled until the root cause # is fixed (GitHub issue zephyrproject-rtos/zephyr#48608). - platform_exclude: mps2_an385 + platform_exclude: mps2/an385 tests: net.socket.reuseaddr_reuseport: extra_configs: diff --git a/tests/net/socket/select/testcase.yaml b/tests/net/socket/select/testcase.yaml index eaae57ab9ef..320cfbaa3ec 100644 --- a/tests/net/socket/select/testcase.yaml +++ b/tests/net/socket/select/testcase.yaml @@ -6,10 +6,10 @@ common: - socket - userspace filter: CONFIG_FULL_LIBC_SUPPORTED - # FIXME: This test fails very frequently on mps2_an385 due to the system + # FIXME: This test fails very frequently on mps2/an385 due to the system # timer stability issues, so keep it disabled until the root cause # is fixed (GitHub issue zephyrproject-rtos/zephyr#48608). - platform_exclude: mps2_an385 + platform_exclude: mps2/an385 tests: net.socket.select: extra_configs: diff --git a/tests/net/socket/service/testcase.yaml b/tests/net/socket/service/testcase.yaml index 74046d08274..a2ea34cfe88 100644 --- a/tests/net/socket/service/testcase.yaml +++ b/tests/net/socket/service/testcase.yaml @@ -1,11 +1,11 @@ common: depends_on: netif - # FIXME: This test fails very frequently on mps2_an385 due to the system + # FIXME: This test fails very frequently on mps2/an385 due to the system # timer stability issues, so keep it disabled until the root cause # is fixed (GitHub issue zephyrproject-rtos/zephyr#48608). # eventfd API does not work with native_posix so exclude it here platform_exclude: - - mps2_an385 + - mps2/an385 - native_posix - native_posix_64 tests: diff --git a/tests/net/socket/socketpair/testcase.yaml b/tests/net/socket/socketpair/testcase.yaml index 5410f938376..bb906c29d0c 100644 --- a/tests/net/socket/socketpair/testcase.yaml +++ b/tests/net/socket/socketpair/testcase.yaml @@ -7,17 +7,17 @@ common: min_ram: 21 tests: net.socket.socketpair: - platform_exclude: vmu_rt1170 mimxrt1160_evk_cm7 # See #61246 + platform_exclude: vmu_rt1170/mimxrt1176/cm7 mimxrt1160_evk/mimxrt1166/cm7 # See #61246 net.socket.socketpair.newlib: filter: CONFIG_FULL_LIBC_SUPPORTED extra_configs: - CONFIG_REQUIRES_FULL_LIBC=y - platform_exclude: vmu_rt1170 mimxrt1160_evk_cm7 # See #61246 + platform_exclude: vmu_rt1170/mimxrt1176/cm7 mimxrt1160_evk/mimxrt1166/cm7 # See #61246 net.socket.socketpair.picolibc: filter: CONFIG_PICOLIBC_SUPPORTED extra_configs: - CONFIG_PICOLIBC=y - platform_exclude: vmu_rt1170 mimxrt1160_evk_cm7 # See #61246 + platform_exclude: vmu_rt1170/mimxrt1176/cm7 mimxrt1160_evk/mimxrt1166/cm7 # See #61246 net.socket.socketpair.high_mem: min_ram: 64 extra_configs: @@ -25,4 +25,4 @@ tests: # fail due to insufficient memory. So, use high buffer sizes. - CONFIG_NET_SOCKETPAIR_BUFFER_SIZE=4096 - CONFIG_HEAP_MEM_POOL_SIZE=32768 - platform_exclude: vmu_rt1170 mimxrt1160_evk_cm7 # See #61246 + platform_exclude: vmu_rt1170/mimxrt1176/cm7 mimxrt1160_evk/mimxrt1166/cm7 # See #61246 diff --git a/tests/net/socket/tcp/testcase.yaml b/tests/net/socket/tcp/testcase.yaml index cff7591d938..cd5f7533226 100644 --- a/tests/net/socket/tcp/testcase.yaml +++ b/tests/net/socket/tcp/testcase.yaml @@ -7,10 +7,10 @@ common: - userspace filter: CONFIG_FULL_LIBC_SUPPORTED timeout: 180 - # FIXME: This test fails very frequently on mps2_an385 due to the system + # FIXME: This test fails very frequently on mps2/an385 due to the system # timer stability issues, so keep it disabled until the root cause # is fixed (GitHub issue zephyrproject-rtos/zephyr#48608). - platform_exclude: mps2_an385 + platform_exclude: mps2/an385 tests: net.socket.tcp: extra_configs: diff --git a/tests/net/socket/tls/testcase.yaml b/tests/net/socket/tls/testcase.yaml index e10c883312f..00a126769c7 100644 --- a/tests/net/socket/tls/testcase.yaml +++ b/tests/net/socket/tls/testcase.yaml @@ -9,7 +9,7 @@ common: filter: CONFIG_FULL_LIBC_SUPPORTED integration_platforms: - qemu_x86 - platform_exclude: vmu_rt1170 # See #61129 + platform_exclude: vmu_rt1170/mimxrt1176/cm7 # See #61129 tests: net.socket.tls: extra_configs: @@ -17,4 +17,4 @@ tests: net.socket.tls.preempt: extra_configs: - CONFIG_NET_TC_THREAD_PREEMPTIVE=y - platform_exclude: mps2_an385 + platform_exclude: mps2/an385 diff --git a/tests/posix/common/testcase.yaml b/tests/posix/common/testcase.yaml index 9617cd8e08f..1562b00320b 100644 --- a/tests/posix/common/testcase.yaml +++ b/tests/posix/common/testcase.yaml @@ -9,7 +9,7 @@ common: tests: portability.posix.common: platform_exclude: - - nsim_sem_mpu_stack_guard + - nsim/nsim_sem/mpu_stack_guard - intel_ehl_crb extra_configs: - CONFIG_NEWLIB_LIBC=n @@ -17,7 +17,7 @@ tests: - qemu_x86 portability.posix.common.newlib: platform_exclude: - - nsim_sem_mpu_stack_guard + - nsim/nsim_sem/mpu_stack_guard - intel_ehl_crb - lpcxpresso55s06 filter: TOOLCHAIN_HAS_NEWLIB == 1 @@ -37,7 +37,7 @@ tests: - CONFIG_ARCMWDT_LIBC=y portability.posix.common.tls: platform_exclude: - - nsim_sem_mpu_stack_guard + - nsim/nsim_sem/mpu_stack_guard - intel_ehl_crb filter: CONFIG_ARCH_HAS_THREAD_LOCAL_STORAGE and CONFIG_TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE extra_configs: @@ -47,7 +47,7 @@ tests: - qemu_x86 portability.posix.common.tls.newlib: platform_exclude: - - nsim_sem_mpu_stack_guard + - nsim/nsim_sem/mpu_stack_guard - intel_ehl_crb - lpcxpresso55s06 filter: TOOLCHAIN_HAS_NEWLIB == 1 and CONFIG_ARCH_HAS_THREAD_LOCAL_STORAGE and @@ -60,12 +60,12 @@ tests: - CONFIG_NEWLIB_LIBC=y - CONFIG_THREAD_LOCAL_STORAGE=y portability.posix.common.nsim: - platform_allow: nsim_sem_mpu_stack_guard + platform_allow: nsim/nsim_sem/mpu_stack_guard extra_configs: - CONFIG_NEWLIB_LIBC=n - CONFIG_TEST_HW_STACK_PROTECTION=n portability.posix.common.newlib.nsim: - platform_allow: nsim_sem_mpu_stack_guard + platform_allow: nsim/nsim_sem/mpu_stack_guard filter: TOOLCHAIN_HAS_NEWLIB == 1 extra_configs: - CONFIG_NEWLIB_LIBC=y @@ -81,7 +81,7 @@ tests: extra_configs: - CONFIG_SPIN_VALIDATE=n integration_platforms: - - mps2_an385 + - mps2/an385 portability.posix.common.signal.strsignal_no_desc: extra_configs: - CONFIG_POSIX_SIGNAL_STRING_DESC=n diff --git a/tests/posix/pthread_pressure/testcase.yaml b/tests/posix/pthread_pressure/testcase.yaml index 73a8fa34e23..83492a4c9db 100644 --- a/tests/posix/pthread_pressure/testcase.yaml +++ b/tests/posix/pthread_pressure/testcase.yaml @@ -4,7 +4,7 @@ common: arch_exclude: - posix integration_platforms: - - qemu_riscv64_smp + - qemu_riscv64/qemu_virt_riscv64/smp tests: portability.posix.pthread_pressure: extra_configs: diff --git a/tests/subsys/bindesc/definition/testcase.yaml b/tests/subsys/bindesc/definition/testcase.yaml index 0f447941374..6e1884ee0b0 100644 --- a/tests/subsys/bindesc/definition/testcase.yaml +++ b/tests/subsys/bindesc/definition/testcase.yaml @@ -14,10 +14,10 @@ tests: - qemu_cortex_m0 - qemu_cortex_m3 - qemu_cortex_r5 - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs5x - - qemu_arc_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs5x + - qemu_arc/qemu_arc_hs6x - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 diff --git a/tests/subsys/debug/coredump/src/main.c b/tests/subsys/debug/coredump/src/main.c index d5e11f2148d..3f18ef9e2d6 100644 --- a/tests/subsys/debug/coredump/src/main.c +++ b/tests/subsys/debug/coredump/src/main.c @@ -30,7 +30,6 @@ void func_3(uint32_t *addr) #if defined(CONFIG_BOARD_M2GL025_MIV) || \ defined(CONFIG_BOARD_HIFIVE1) || \ defined(CONFIG_BOARD_LONGAN_NANO) || \ - defined(CONFIG_BOARD_LONGAN_NANO_LITE) || \ defined(CONFIG_BOARD_QEMU_XTENSA) || \ defined(CONFIG_SOC_FAMILY_INTEL_ADSP) ARG_UNUSED(addr); diff --git a/tests/subsys/debug/coredump_backends/testcase.yaml b/tests/subsys/debug/coredump_backends/testcase.yaml index d7b5f722f37..ff4109f9d50 100644 --- a/tests/subsys/debug/coredump_backends/testcase.yaml +++ b/tests/subsys/debug/coredump_backends/testcase.yaml @@ -19,10 +19,10 @@ tests: - CONFIG_TEST_STORED_COREDUMP=y platform_allow: - qemu_x86 - - esp32_devkitc_wroom - - esp32_devkitc_wrover + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu - esp32s2_saola - - esp32s3_devkitm + - esp32s3_devkitm/esp32s3/procpu - esp32c3_devkitm debug.coredump.backends.other: filter: CONFIG_ARCH_SUPPORTS_COREDUMP diff --git a/tests/subsys/dfu/img_util/testcase.yaml b/tests/subsys/dfu/img_util/testcase.yaml index e90fb0842b1..58cc48f98a6 100644 --- a/tests/subsys/dfu/img_util/testcase.yaml +++ b/tests/subsys/dfu/img_util/testcase.yaml @@ -1,12 +1,12 @@ common: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_posix - native_posix_64 - native_sim - native_sim_64 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tests: dfu.image_util: tags: dfu_image_util diff --git a/tests/subsys/dfu/mcuboot/testcase.yaml b/tests/subsys/dfu/mcuboot/testcase.yaml index 6b630c71865..3b1ddc39a3c 100644 --- a/tests/subsys/dfu/mcuboot/testcase.yaml +++ b/tests/subsys/dfu/mcuboot/testcase.yaml @@ -1,11 +1,11 @@ tests: dfu.mcuboot: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_posix - native_posix_64 - native_sim - native_sim_64 tags: dfu_mcuboot integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/tests/subsys/dfu/mcuboot_multi/testcase.yaml b/tests/subsys/dfu/mcuboot_multi/testcase.yaml index 742bbe38ce6..9f641191803 100644 --- a/tests/subsys/dfu/mcuboot_multi/testcase.yaml +++ b/tests/subsys/dfu/mcuboot_multi/testcase.yaml @@ -1,9 +1,9 @@ tests: dfu.mcuboot.multiimage: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_sim - native_sim_64 tags: dfu_mcuboot integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/tests/subsys/dsp/basicmath/testcase.yaml b/tests/subsys/dsp/basicmath/testcase.yaml index cb8dd1a2765..7311f8cb906 100644 --- a/tests/subsys/dsp/basicmath/testcase.yaml +++ b/tests/subsys/dsp/basicmath/testcase.yaml @@ -3,8 +3,8 @@ tests: filter: CONFIG_FULL_LIBC_SUPPORTED or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: zdsp min_flash: 128 @@ -12,8 +12,8 @@ tests: zdsp.basicmath.fpu: filter: (CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - zdsp - fpu @@ -24,5 +24,5 @@ tests: zdsp.basicmath.arcmwdt: filter: CONFIG_ISA_ARCV2 toolchain_allow: arcmwdt - platform_allow: nsim_em11d + platform_allow: nsim/nsim_em11d extra_args: CONF_FILE=prj_arc.conf diff --git a/tests/subsys/fs/ext2/testcase.yaml b/tests/subsys/fs/ext2/testcase.yaml index bb4402c9b0e..76ec97de3c8 100644 --- a/tests/subsys/fs/ext2/testcase.yaml +++ b/tests/subsys/fs/ext2/testcase.yaml @@ -6,7 +6,7 @@ tests: - native_sim - native_sim_64 - hifive_unmatched - - bl5340_dvk_cpuapp + - bl5340_dvk/nrf5340/cpuapp extra_args: - EXTRA_DTC_OVERLAY_FILE="ramdisk_small.overlay" @@ -23,7 +23,7 @@ tests: - renode platform_allow: - hifive_unmatched - - bl5340_dvk_cpuapp + - bl5340_dvk/nrf5340/cpuapp extra_args: CONF_FILE=prj_sdcard.conf filesystem.ext2.flash: diff --git a/tests/subsys/fs/fcb/boards/nrf51dk_nrf51422.conf b/tests/subsys/fs/fcb/boards/nrf51dk_nrf51822.conf similarity index 100% rename from tests/subsys/fs/fcb/boards/nrf51dk_nrf51422.conf rename to tests/subsys/fs/fcb/boards/nrf51dk_nrf51822.conf diff --git a/tests/subsys/fs/fcb/testcase.yaml b/tests/subsys/fs/fcb/testcase.yaml index 3945049a534..9070bbaf7bb 100644 --- a/tests/subsys/fs/fcb/testcase.yaml +++ b/tests/subsys/fs/fcb/testcase.yaml @@ -1,9 +1,9 @@ tests: filesystem.fcb: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 - native_posix - native_posix_64 - native_sim @@ -11,7 +11,7 @@ tests: - mr_canhubk3 tags: flash_circural_buffer integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 filesystem.fcb.native_sim.fcb_0x00: extra_args: DTC_OVERLAY_FILE=boards/native_sim_ev_0x00.overlay platform_allow: native_sim diff --git a/tests/subsys/fs/littlefs/testcase.yaml b/tests/subsys/fs/littlefs/testcase.yaml index 211137180f8..1a125021bf7 100644 --- a/tests/subsys/fs/littlefs/testcase.yaml +++ b/tests/subsys/fs/littlefs/testcase.yaml @@ -3,13 +3,13 @@ common: - filesystem - littlefs platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_sim - native_sim_64 - mimxrt1060_evk - mr_canhubk3 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 modules: - littlefs tests: diff --git a/tests/subsys/llext/hello_world/testcase.yaml b/tests/subsys/llext/hello_world/testcase.yaml index c977dc5f94f..391e2f81c92 100644 --- a/tests/subsys/llext/hello_world/testcase.yaml +++ b/tests/subsys/llext/hello_world/testcase.yaml @@ -4,11 +4,11 @@ common: - arm - xtensa platform_exclude: - - nuvoton_pfm_m487 # See #63167 + - numaker_pfm_m487 # See #63167 tests: llext.simple.readonly: arch_exclude: xtensa # for now - filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE_R52 + filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE extra_configs: - arch:arm:CONFIG_ARM_MPU=n - CONFIG_LLEXT_STORAGE_WRITABLE=n @@ -19,7 +19,7 @@ tests: - CONFIG_USERSPACE=y - CONFIG_LLEXT_STORAGE_WRITABLE=n llext.simple.writable: - filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE_R52 + filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE extra_configs: - arch:arm:CONFIG_ARM_MPU=n - CONFIG_LLEXT_STORAGE_WRITABLE=y diff --git a/tests/subsys/logging/log_backend_fs/testcase.yaml b/tests/subsys/logging/log_backend_fs/testcase.yaml index c8caccc8c8f..60ad3a0a295 100644 --- a/tests/subsys/logging/log_backend_fs/testcase.yaml +++ b/tests/subsys/logging/log_backend_fs/testcase.yaml @@ -10,7 +10,7 @@ common: platform_allow: - native_sim - native_sim_64 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - mr_canhubk3 integration_platforms: - native_sim diff --git a/tests/subsys/logging/log_switch_format/testcase.yaml b/tests/subsys/logging/log_switch_format/testcase.yaml index 911c8e2c178..bc1f1e933b7 100644 --- a/tests/subsys/logging/log_switch_format/testcase.yaml +++ b/tests/subsys/logging/log_switch_format/testcase.yaml @@ -13,7 +13,7 @@ common: tests: logging.format.switch.deferred: integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 extra_args: OVERLAY_CONFIG=overlay_deferred.conf # "CONFIG_FULL_LIBC_SUPPORTED" filter was applied @@ -28,7 +28,7 @@ tests: logging.format.switch.immediate: extra_args: OVERLAY_CONFIG=overlay_immediate.conf integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 filter: CONFIG_FULL_LIBC_SUPPORTED extra_configs: @@ -36,7 +36,7 @@ tests: logging.format.switch.custom_output: extra_args: OVERLAY_CONFIG=overlay_custom_output.conf integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 filter: CONFIG_FULL_LIBC_SUPPORTED extra_configs: diff --git a/tests/subsys/logging/log_syst/testcase.yaml b/tests/subsys/logging/log_syst/testcase.yaml index db2160b60f0..d77a94d1d09 100644 --- a/tests/subsys/logging/log_syst/testcase.yaml +++ b/tests/subsys/logging/log_syst/testcase.yaml @@ -18,9 +18,9 @@ tests: # Not all compilers announced in Zephyr support full libc filter: CONFIG_FULL_LIBC_SUPPORTED integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 - - sam_e70_xplained + - sam_e70_xplained/same70q21 extra_configs: - CONFIG_LOG_MIPI_SYST_ENABLE=y - CONFIG_LOG_BACKEND_MOCK_OUTPUT_SYST=y diff --git a/tests/subsys/mgmt/mcumgr/all_options/testcase.yaml b/tests/subsys/mgmt/mcumgr/all_options/testcase.yaml index 471a96a935f..f21fad9510f 100644 --- a/tests/subsys/mgmt/mcumgr/all_options/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/all_options/testcase.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # common: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: - mgmt - mcumgr diff --git a/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml b/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml index a2514c4dac8..7243c980375 100644 --- a/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml @@ -11,7 +11,7 @@ tests: - native_posix_64 - native_sim - native_sim_64 - - qemu_riscv32_smp + - qemu_riscv32/qemu_virt_riscv32/smp - qemu_riscv64 tags: - cb_notifications diff --git a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml index 5d8994f8541..4f07ecf0211 100644 --- a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml @@ -15,26 +15,26 @@ tests: extra_args: > OVERLAY_CONFIG="configuration/crc32.conf" platform_exclude: - - arduino_giga_r1_m4 - - arduino_portenta_h7_m4 + - arduino_giga_r1/stm32h747xx/m4 + - arduino_portenta_h7/stm32h747xx/m4 - lpcxpresso51u68 - - nucleo_h745zi_q_m4 - - stm32h747i_disco_m4 + - nucleo_h745zi_q/stm32h745xx/m4 + - stm32h747i_disco/stm32h747xx/m4 mgmt.mcumgr.fs.mgmt.hash.supported.sha256: extra_args: > OVERLAY_CONFIG="configuration/sha256.conf" platform_exclude: - - arduino_giga_r1_m4 - - arduino_portenta_h7_m4 + - arduino_giga_r1/stm32h747xx/m4 + - arduino_portenta_h7/stm32h747xx/m4 - lpcxpresso51u68 - - nucleo_h745zi_q_m4 - - stm32h747i_disco_m4 + - nucleo_h745zi_q/stm32h745xx/m4 + - stm32h747i_disco/stm32h747xx/m4 mgmt.mcumgr.fs.mgmt.hash.supported.all: extra_args: > OVERLAY_CONFIG="configuration/all.conf" platform_exclude: - - arduino_giga_r1_m4 - - arduino_portenta_h7_m4 + - arduino_giga_r1/stm32h747xx/m4 + - arduino_portenta_h7/stm32h747xx/m4 - lpcxpresso51u68 - - nucleo_h745zi_q_m4 - - stm32h747i_disco_m4 + - nucleo_h745zi_q/stm32h745xx/m4 + - stm32h747i_disco/stm32h747xx/m4 diff --git a/tests/subsys/mgmt/mcumgr/handler_demo/testcase.yaml b/tests/subsys/mgmt/mcumgr/handler_demo/testcase.yaml index 88e6eae4b5e..dbd18f8d1c5 100644 --- a/tests/subsys/mgmt/mcumgr/handler_demo/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/handler_demo/testcase.yaml @@ -12,15 +12,15 @@ common: tests: mgmt.mcumgr.handler.demo: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 build_only: true mgmt.mcumgr.handler.demo.module: extra_args: - OVERLAY_CONFIG="module.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 build_only: true diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_arc_hs6x.overlay b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_arc_qemu_arc_hs6x.overlay similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_arc_hs6x.overlay rename to tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_arc_qemu_arc_hs6x.overlay diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_smp.overlay b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.overlay similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_smp.overlay rename to tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.overlay diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml index 82d0021d325..9da5603fe74 100644 --- a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml @@ -12,9 +12,9 @@ common: - native_sim - qemu_cortex_m0 - qemu_riscv64 - - qemu_riscv64_smp + - qemu_riscv64/qemu_virt_riscv64/smp - qemu_malta - - qemu_arc_hs6x + - qemu_arc/qemu_arc_hs6x - qemu_leon3 tests: mgmt.mcumgr.os.datetime: {} diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml b/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml index 930ae58cd3d..7c5eeff1919 100644 --- a/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml @@ -33,13 +33,13 @@ tests: platform_exclude: - qemu_cortex_a9 - qemu_x86 - - qemu_riscv64_smp + - qemu_riscv64/qemu_virt_riscv64/smp - qemu_riscv64 - qemu_riscv32e - qemu_riscv32 - - qemu_riscv32_smp + - qemu_riscv32/qemu_virt_riscv32/smp - qemu_cortex_m3 - - mps2_an385 + - mps2/an385 extra_configs: - CONFIG_NETWORKING=y - CONFIG_NET_HOSTNAME_ENABLE=y diff --git a/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml b/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml index 2e8a68cca64..07bf722bbf9 100644 --- a/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml @@ -10,7 +10,7 @@ tests: - native_posix_64 - native_sim - native_sim_64 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - settings_mgmt - mcumgr diff --git a/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/modem/backends/uart/testcase.yaml b/tests/subsys/modem/backends/uart/testcase.yaml index 54d8a6b9470..be53728c724 100644 --- a/tests/subsys/modem/backends/uart/testcase.yaml +++ b/tests/subsys/modem/backends/uart/testcase.yaml @@ -7,7 +7,7 @@ common: fixture: gpio_loopback platform_allow: - b_u585i_iot02a - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tests: modem.backends.uart.async: diff --git a/tests/subsys/pm/power_mgmt_soc/testcase.yaml b/tests/subsys/pm/power_mgmt_soc/testcase.yaml index 8fe974f0bfa..021a3416b9b 100644 --- a/tests/subsys/pm/power_mgmt_soc/testcase.yaml +++ b/tests/subsys/pm/power_mgmt_soc/testcase.yaml @@ -9,7 +9,7 @@ tests: - nucleo_wb55rg - nucleo_l476rg - twr_ke18f - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 tags: pm integration_platforms: - mec15xxevb_assy6853 diff --git a/tests/subsys/sd/mmc/testcase.yaml b/tests/subsys/sd/mmc/testcase.yaml index ac45914242e..3c201d0f1e4 100644 --- a/tests/subsys/sd/mmc/testcase.yaml +++ b/tests/subsys/sd/mmc/testcase.yaml @@ -10,4 +10,4 @@ tests: tags: sdhc min_ram: 32 integration_platforms: - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 diff --git a/tests/subsys/settings/fcb/testcase.yaml b/tests/subsys/settings/fcb/testcase.yaml index 0382c74ff00..01dc9f5bf0f 100644 --- a/tests/subsys/settings/fcb/testcase.yaml +++ b/tests/subsys/settings/fcb/testcase.yaml @@ -1,13 +1,13 @@ tests: settings.fcb.raw: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 - native_sim - native_sim_64 - mr_canhubk3 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_sim tags: - settings diff --git a/tests/subsys/settings/fcb_init/testcase.yaml b/tests/subsys/settings/fcb_init/testcase.yaml index fd0d0209c71..8c26410c613 100644 --- a/tests/subsys/settings/fcb_init/testcase.yaml +++ b/tests/subsys/settings/fcb_init/testcase.yaml @@ -1,10 +1,10 @@ tests: settings.fcb: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - settings - fcb diff --git a/tests/subsys/settings/file/testcase.yaml b/tests/subsys/settings/file/testcase.yaml index 9491f9b2046..c98239ca2ad 100644 --- a/tests/subsys/settings/file/testcase.yaml +++ b/tests/subsys/settings/file/testcase.yaml @@ -4,7 +4,7 @@ tests: settings.file.raw: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_sim - native_sim_64 - mr_canhubk3 diff --git a/tests/subsys/settings/functional/fcb/testcase.yaml b/tests/subsys/settings/functional/fcb/testcase.yaml index d9d63adc66c..eaad89b64e6 100644 --- a/tests/subsys/settings/functional/fcb/testcase.yaml +++ b/tests/subsys/settings/functional/fcb/testcase.yaml @@ -1,15 +1,15 @@ tests: settings.functional.fcb: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 - native_posix - native_posix_64 - native_sim - native_sim_64 - mr_canhubk3 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - settings - fcb diff --git a/tests/subsys/settings/functional/file/testcase.yaml b/tests/subsys/settings/functional/file/testcase.yaml index 6f876e93f3f..bb4b9036f4b 100644 --- a/tests/subsys/settings/functional/file/testcase.yaml +++ b/tests/subsys/settings/functional/file/testcase.yaml @@ -1,8 +1,8 @@ tests: settings.file: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 - native_sim - native_sim_64 - mr_canhubk3 diff --git a/tests/subsys/settings/functional/nvs/testcase.yaml b/tests/subsys/settings/functional/nvs/testcase.yaml index def7aa02a52..3f0cf37b796 100644 --- a/tests/subsys/settings/functional/nvs/testcase.yaml +++ b/tests/subsys/settings/functional/nvs/testcase.yaml @@ -22,10 +22,10 @@ tests: settings.functional.nvs.dk: extra_args: OVERLAY_CONFIG=mpu.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - settings - nvs diff --git a/tests/subsys/storage/flash_map/testcase.yaml b/tests/subsys/storage/flash_map/testcase.yaml index 1d03fc2ed2f..027b3865fdd 100644 --- a/tests/subsys/storage/flash_map/testcase.yaml +++ b/tests/subsys/storage/flash_map/testcase.yaml @@ -1,7 +1,7 @@ tests: storage.flash_map: platform_allow: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 - qemu_x86 - native_posix - native_posix_64 @@ -14,18 +14,18 @@ tests: storage.flash_map.mpu: extra_args: OVERLAY_CONFIG=overlay-mpu.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 - frdm_k64f - - hexiwear_k64 + - hexiwear/mk64f12 - twr_ke18f integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: flash_map storage.flash_map.mbedtls: extra_args: OVERLAY_CONFIG=overlay-mbedtls.conf platform_allow: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 - qemu_x86 - native_posix - native_posix_64 diff --git a/tests/subsys/storage/stream/stream_flash/testcase.yaml b/tests/subsys/storage/stream/stream_flash/testcase.yaml index 9f4b8c16383..e61557feadc 100644 --- a/tests/subsys/storage/stream/stream_flash/testcase.yaml +++ b/tests/subsys/storage/stream/stream_flash/testcase.yaml @@ -18,7 +18,7 @@ tests: storage.stream_flash.mpu_allow_flash_write: extra_args: OVERLAY_CONFIG=mpu_allow_flash_write.overlay platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: stream_flash diff --git a/tests/subsys/zbus/dyn_channel/testcase.yaml b/tests/subsys/zbus/dyn_channel/testcase.yaml index 8bdee772571..96bd746beaa 100644 --- a/tests/subsys/zbus/dyn_channel/testcase.yaml +++ b/tests/subsys/zbus/dyn_channel/testcase.yaml @@ -1,6 +1,6 @@ tests: message_bus.zbus.dyn_channel.static_and_dynamic_channels: - platform_exclude: fvp_base_revc_2xaemv8a_smp_ns + platform_exclude: fvp_base_revc_2xaemv8a//smp/ns tags: zbus integration_platforms: - native_sim diff --git a/tests/subsys/zbus/hlp_priority_boost/testcase.yaml b/tests/subsys/zbus/hlp_priority_boost/testcase.yaml index f83e54f59e9..54fdf3021fb 100644 --- a/tests/subsys/zbus/hlp_priority_boost/testcase.yaml +++ b/tests/subsys/zbus/hlp_priority_boost/testcase.yaml @@ -1,6 +1,6 @@ tests: message_bus.zbus.hlp_priority_boost: - platform_exclude: fvp_base_revc_2xaemv8a_smp_ns + platform_exclude: fvp_base_revc_2xaemv8a//smp/ns tags: zbus integration_platforms: - native_sim diff --git a/tests/subsys/zbus/integration/testcase.yaml b/tests/subsys/zbus/integration/testcase.yaml index 410280b1b0d..ec123e9477e 100644 --- a/tests/subsys/zbus/integration/testcase.yaml +++ b/tests/subsys/zbus/integration/testcase.yaml @@ -3,7 +3,7 @@ tests: platform_exclude: - qemu_cortex_a9 - hifive_unleashed - - fvp_base_revc_2xaemv8a_smp_ns + - fvp_base_revc_2xaemv8a//smp/ns - fvp_baser_aemv8r_aarch32_smp tags: zbus integration_platforms: diff --git a/tests/subsys/zbus/unittests/testcase.yaml b/tests/subsys/zbus/unittests/testcase.yaml index 6b7076cb680..8c9d10c7574 100644 --- a/tests/subsys/zbus/unittests/testcase.yaml +++ b/tests/subsys/zbus/unittests/testcase.yaml @@ -1,11 +1,11 @@ tests: message_bus.zbus.general_unittests: - platform_exclude: fvp_base_revc_2xaemv8a_smp_ns + platform_exclude: fvp_base_revc_2xaemv8a//smp/ns tags: zbus integration_platforms: - native_sim message_bus.zbus.general_unittests_without_priority_boost: - platform_exclude: fvp_base_revc_2xaemv8a_smp_ns + platform_exclude: fvp_base_revc_2xaemv8a//smp/ns tags: zbus integration_platforms: - native_sim diff --git a/tests/subsys/zbus/user_data/testcase.yaml b/tests/subsys/zbus/user_data/testcase.yaml index 4f21a9c35c8..e8f6e936b9b 100644 --- a/tests/subsys/zbus/user_data/testcase.yaml +++ b/tests/subsys/zbus/user_data/testcase.yaml @@ -1,6 +1,6 @@ tests: message_bus.zbus.user_data.channel_user_data: - platform_exclude: fvp_base_revc_2xaemv8a_smp_ns + platform_exclude: fvp_base_revc_2xaemv8a//smp/ns tags: zbus integration_platforms: - native_sim diff --git a/tests/ztest/busy_sim/testcase.yaml b/tests/ztest/busy_sim/testcase.yaml index 931871c830a..271b2aa8542 100644 --- a/tests/ztest/busy_sim/testcase.yaml +++ b/tests/ztest/busy_sim/testcase.yaml @@ -4,7 +4,7 @@ common: depends_on: counter tests: testing.ztest.busy_sim: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 testing.ztest.busy_sim_nrf52840dk_pin: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_pin.overlay diff --git a/west.yml b/west.yml index 3e8b2f0fa48..087e2563203 100644 --- a/west.yml +++ b/west.yml @@ -147,7 +147,7 @@ manifest: groups: - hal - name: hal_atmel - revision: aad79bf530b69b72712d18873df4120ad052d921 + revision: d6221e73d76a4a31d802e0657342fcbda77e21ae path: modules/hal/atmel groups: - hal @@ -168,7 +168,7 @@ manifest: groups: - hal - name: hal_infineon - revision: 69c883d3bd9fac8a18dd8384624b8c472a68d06f + revision: b1a47231e8671c882c5f055f9f10c32b18133d08 path: modules/hal/infineon groups: - hal @@ -178,7 +178,7 @@ manifest: groups: - hal - name: hal_microchip - revision: 5d079f1683a00b801373bbbbf5d181d4e33b30d5 + revision: 68575aa28cd33c68b3b8d66f510d15746c57fdb5 path: modules/hal/microchip groups: - hal @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: d45b14c198d778658b7853b48378d2e132a6c4be + revision: f436a4529f284067af29ad72af5bd0ad51b09f3e path: modules/hal/nxp groups: - hal @@ -210,7 +210,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 0b1f2fdb99d6386f125a8dba72083e3c56aecc2b + revision: 991e060b6825f0f6830f4dbccbed8252598f2a6d groups: - hal - name: hal_rpi_pico @@ -219,7 +219,7 @@ manifest: groups: - hal - name: hal_silabs - revision: b11b29167f3f9a0fd0c34a8eeeb36b0c1d218917 + revision: 59c6c6e2e8862f0ff5c6087ef055793bed125778 path: modules/hal/silabs groups: - hal @@ -249,7 +249,7 @@ manifest: groups: - hal - name: hal_xtensa - revision: 08325d6fb7190a105f5382d35e64ed2812c57cf4 + revision: a2d658525b16c57bea8dd565f5bd5167e4b9f1ee path: modules/hal/xtensa groups: - hal @@ -282,7 +282,7 @@ manifest: groups: - crypto - name: mcuboot - revision: a4eda30f5b0cfd0cf15512be9dcd559239dbfc91 + revision: fefe701a5de7ffcec001938c978ef57ff7d0592d path: bootloader/mcuboot - name: mipi-sys-t path: modules/debug/mipi-sys-t @@ -335,7 +335,7 @@ manifest: revision: 150f4eb2955eaf36ac0f9519d4f4f58d5ade5740 path: modules/lib/uoscore-uedhoc - name: zcbor - revision: d3093b5684f62268c7f27f8a5079f166772619de + revision: 75d088037eb237b18e7ec1f47c9ce494b9b95aab path: modules/lib/zcbor self: From 083036fffcbd5c9f1a99eea8445c3f0a41ce3e3f Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Thu, 22 Feb 2024 19:24:36 +0100 Subject: [PATCH 0031/2402] cmake: modules: boards: Fix board deprecation for HWMv2 (again) If board `plank` was deprecated, then building with `-DBOARD=plank/foo` would fail, so as to discourage identifier misuse. However, `plank/foo` could actually be a valid target in HWMv2, so this was a bad idea. Replace the offending error with more open-ended identifier handling, originally suggested in #68940 (anchor: #discussion_r1492103361). Signed-off-by: Grzegorz Swiderski --- cmake/modules/boards.cmake | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index 0854653445d..1cc649326ff 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -77,14 +77,20 @@ function(parse_board_components board_in name_out revision_out identifier_out) set(${identifier_out} ${CMAKE_MATCH_3} PARENT_SCOPE) endfunction() -parse_board_components(BOARD BOARD BOARD_REVISION BOARD_IDENTIFIER) +parse_board_components( + BOARD + BOARD BOARD_REVISION BOARD_IDENTIFIER +) zephyr_get(ZEPHYR_BOARD_ALIASES) if(DEFINED ZEPHYR_BOARD_ALIASES) include(${ZEPHYR_BOARD_ALIASES}) if(${BOARD}_BOARD_ALIAS) set(BOARD_ALIAS ${BOARD} CACHE STRING "Board alias, provided by user") - parse_board_components(${BOARD}_BOARD_ALIAS BOARD BOARD_ALIAS_REVISION BOARD_ALIAS_IDENTIFIER) + parse_board_components( + ${BOARD}_BOARD_ALIAS + BOARD BOARD_ALIAS_REVISION BOARD_ALIAS_IDENTIFIER + ) message(STATUS "Aliased BOARD=${BOARD_ALIAS} changed to ${BOARD}") if(NOT DEFINED BOARD_REVISION) set(BOARD_REVISION ${BOARD_ALIAS_REVISION}) @@ -94,10 +100,16 @@ if(DEFINED ZEPHYR_BOARD_ALIASES) endif() include(${ZEPHYR_BASE}/boards/deprecated.cmake) -if(${BOARD}_DEPRECATED) - set(BOARD_DEPRECATED ${BOARD} CACHE STRING "Deprecated board name, provided by user") - parse_board_components(${BOARD}_DEPRECATED BOARD BOARD_DEPRECATED_REVISION BOARD_DEPRECATED_IDENTIFIER) - message(WARNING "Deprecated BOARD=${BOARD_DEPRECATED} name specified, board automatically changed to: ${BOARD}.") +if(${BOARD}${BOARD_IDENTIFIER}_DEPRECATED) + set(BOARD_DEPRECATED ${BOARD}${BOARD_IDENTIFIER} CACHE STRING "Deprecated BOARD, provided by user") + message(WARNING + "Deprecated BOARD=${BOARD_DEPRECATED} specified, " + "board automatically changed to: ${${BOARD}${BOARD_IDENTIFIER}_DEPRECATED}." + ) + parse_board_components( + ${BOARD}${BOARD_IDENTIFIER}_DEPRECATED + BOARD BOARD_DEPRECATED_REVISION BOARD_IDENTIFIER + ) if(DEFINED BOARD_DEPRECATED_REVISION) if(DEFINED BOARD_REVISION) message(FATAL_ERROR @@ -109,13 +121,6 @@ if(${BOARD}_DEPRECATED) endif() set(BOARD_REVISION ${BOARD_DEPRECATED_REVISION}) endif() - if(DEFINED BOARD_IDENTIFIER) - message(FATAL_ERROR - "Deprecated boards cannot have board identifiers: ${BOARD_DEPRECATED}${BOARD_IDENTIFIER}.\n" - "Please consult the documentation for '${BOARD}' to see how to build for the new board." - ) - endif() - set(BOARD_IDENTIFIER ${BOARD_DEPRECATED_IDENTIFIER}) endif() zephyr_boilerplate_watch(BOARD) From 792be769a23487fa0ed2469f6928b8c7ce73525f Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Thu, 22 Feb 2024 17:49:27 +0100 Subject: [PATCH 0032/2402] boards: Deprecate HWMv1 board names Generate `boards/deprecated.cmake` entries to map all legacy boards to their HWMv2 incarnations. Single-SoC, single-CPU boards, whose names haven't changed, don't need to be listed here. In those cases, `BOARD=` counts as a shortened form of `BOARD=/`. Signed-off-by: Grzegorz Swiderski --- boards/deprecated.cmake | 859 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 858 insertions(+), 1 deletion(-) diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 270d5f5e1a9..43334da2a33 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -8,4 +8,861 @@ # To add a board rename, add a line in following format: # set(_DEPRECATED ) -set(esp32_DEPRECATED esp32_devkitc_wrover) +set(96b_carbon_DEPRECATED + 96b_carbon/stm32f401xe +) +set(96b_carbon_nrf51_DEPRECATED + 96b_carbon/nrf51822 +) +set(96b_meerkat96_DEPRECATED + 96b_meerkat96/mcimx7d/m4 +) +set(actinius_icarus_bee_ns_DEPRECATED + actinius_icarus_bee/nrf9160/ns +) +set(actinius_icarus_ns_DEPRECATED + actinius_icarus/nrf9160/ns +) +set(actinius_icarus_som_dk_ns_DEPRECATED + actinius_icarus_som_dk/nrf9160/ns +) +set(actinius_icarus_som_ns_DEPRECATED + actinius_icarus_som/nrf9160/ns +) +set(adafruit_feather_nrf52840_DEPRECATED + adafruit_feather +) +set(adafruit_itsybitsy_nrf52840_DEPRECATED + adafruit_itsybitsy +) +set(adp_xc7k_ae350_DEPRECATED + adp_xc7k +) +set(am62x_m4_phyboard_lyra_DEPRECATED + phyboard_lyra_am62x/am6234/m4 +) +set(am62x_m4_sk_DEPRECATED + sk_am62/am6234/m4 +) +set(arduino_giga_r1_m4_DEPRECATED + arduino_giga_r1/stm32h747xx/m4 +) +set(arduino_giga_r1_m7_DEPRECATED + arduino_giga_r1/stm32h747xx/m7 +) +set(arduino_nano_33_ble_sense_DEPRECATED + arduino_nano_33_ble/nrf52840/sense +) +set(arduino_opta_m4_DEPRECATED + arduino_opta/stm32h747xx/m4 +) +set(arduino_portenta_h7_m4_DEPRECATED + arduino_portenta_h7/stm32h747xx/m4 +) +set(arduino_portenta_h7_m7_DEPRECATED + arduino_portenta_h7/stm32h747xx/m7 +) +set(arty_a7_arm_designstart_m1_DEPRECATED + arty_a7/designstart_fpga_cortex_m1 +) +set(arty_a7_arm_designstart_m3_DEPRECATED + arty_a7/designstart_fpga_cortex_m3 +) +set(atsamc21n_xpro_DEPRECATED + samc21n_xpro +) +set(atsamd20_xpro_DEPRECATED + samd20_xpro +) +set(atsamd21_xpro_DEPRECATED + samd21_xpro +) +set(atsame54_xpro_DEPRECATED + same54_xpro +) +set(atsaml21_xpro_DEPRECATED + saml21_xpro +) +set(atsamr21_xpro_DEPRECATED + samr21_xpro +) +set(atsamr34_xpro_DEPRECATED + samr34_xpro +) +set(b_u585i_iot02a_ns_DEPRECATED + b_u585i_iot02a/stm32u585xx/ns +) +set(bcm958402m2_a72_DEPRECATED + bcm958402m2/bcm58402/a72 +) +set(bcm958402m2_m7_DEPRECATED + bcm958402m2/bcm58402/m7 +) +set(bl5340_dvk_cpuapp_DEPRECATED + bl5340_dvk/nrf5340/cpuapp +) +set(bl5340_dvk_cpuapp_ns_DEPRECATED + bl5340_dvk/nrf5340/cpuapp/ns +) +set(bl5340_dvk_cpunet_DEPRECATED + bl5340_dvk/nrf5340/cpunet +) +set(blueclover_plt_demo_v2_nrf52832_DEPRECATED + blueclover_plt_demo_v2 +) +set(circuitdojo_feather_nrf9160_DEPRECATED + circuitdojo_feather +) +set(circuitdojo_feather_nrf9160_ns_DEPRECATED + circuitdojo_feather/nrf9160/ns +) +set(colibri_imx7d_m4_DEPRECATED + colibri_imx7d/mcimx7d/m4 +) +set(cy8ckit_062_ble_m0_DEPRECATED + cy8ckit_062_ble/cy8c6347/m0 +) +set(cy8ckit_062_ble_m4_DEPRECATED + cy8ckit_062_ble/cy8c6347/m4 +) +set(cy8ckit_062_wifi_bt_m0_DEPRECATED + cy8ckit_062_wifi_bt/cy8c6247/m0 +) +set(cy8ckit_062_wifi_bt_m4_DEPRECATED + cy8ckit_062_wifi_bt/cy8c6247/m4 +) +set(cy8ckit_062s4_m4_DEPRECATED + cy8ckit_062s4 +) +set(ebyte_e73_tbb_nrf52832_DEPRECATED + ebyte_e73_tbb +) +set(efm32pg_stk3402a_DEPRECATED + efm32pg_stk3402a/efm32pg12b500f1024gl125 +) +set(efm32pg_stk3402a_jg_DEPRECATED + efm32pg_stk3402a/efm32jg12b500f1024gl125 +) +set(efr32_radio_brd4104a_DEPRECATED + efr32_radio/efr32bg13p632f512gm48 +) +set(efr32_radio_brd4161a_DEPRECATED + efr32_radio/efr32mg12p432f1024gl125 +) +set(efr32_radio_brd4170a_DEPRECATED + efr32_radio/efr32mg12p433f1024gm68 +) +set(efr32_radio_brd4180a_DEPRECATED + efr32_radio/efr32mg21a020f1024im32 +) +set(efr32_radio_brd4187c_DEPRECATED + efr32_radio/efr32mg24b220f1536im48 +) +set(efr32_radio_brd4250b_DEPRECATED + efr32_radio/efr32fg1p133f256gm48 +) +set(efr32_radio_brd4255a_DEPRECATED + efr32_radio/efr32fg13p233f512gm48 +) +set(em_starterkit_DEPRECATED + em_starterkit/emsk_em9d +) +set(em_starterkit_em11d_DEPRECATED + em_starterkit@2.3/emsk_em11d +) +set(em_starterkit_em7d_DEPRECATED + em_starterkit@2.3/emsk_em7d +) +set(em_starterkit_em7d_v22_DEPRECATED + em_starterkit@2.2/emsk_em7d +) +set(emsdp_DEPRECATED + emsdp/emsdp_em11d +) +set(emsdp_em4_DEPRECATED + emsdp/emsdp_em4 +) +set(emsdp_em5d_DEPRECATED + emsdp/emsdp_em5d +) +set(emsdp_em6_DEPRECATED + emsdp/emsdp_em6 +) +set(emsdp_em7d_DEPRECATED + emsdp/emsdp_em7d +) +set(emsdp_em7d_esp_DEPRECATED + emsdp/emsdp_em7d_esp +) +set(emsdp_em9d_DEPRECATED + emsdp/emsdp_em9d +) +set(esp32_DEPRECATED + esp32_devkitc_wrover/esp32/procpu +) +set(esp32_devkitc_wroom_DEPRECATED + esp32_devkitc_wroom/esp32/procpu +) +set(esp32_devkitc_wroom_appcpu_DEPRECATED + esp32_devkitc_wroom/esp32/appcpu +) +set(esp32_devkitc_wrover_DEPRECATED + esp32_devkitc_wrover/esp32/procpu +) +set(esp32_devkitc_wrover_appcpu_DEPRECATED + esp32_devkitc_wrover/esp32/appcpu +) +set(esp32_ethernet_kit_DEPRECATED + esp32_ethernet_kit/esp32/procpu +) +set(esp32c3_luatos_core_usb_DEPRECATED + esp32c3_luatos_core/esp32c3/usb +) +set(esp32s3_devkitm_DEPRECATED + esp32s3_devkitm/esp32s3/procpu +) +set(esp32s3_devkitm_appcpu_DEPRECATED + esp32s3_devkitm/esp32s3/appcpu +) +set(esp32s3_luatos_core_DEPRECATED + esp32s3_luatos_core/esp32s3/procpu +) +set(esp32s3_luatos_core_usb_DEPRECATED + esp32s3_luatos_core/esp32s3/procpu/usb +) +set(esp_wrover_kit_DEPRECATED + esp_wrover_kit/esp32/procpu +) +set(fvp_base_revc_2xaemv8a_smp_ns_DEPRECATED + fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns +) +set(fvp_baser_aemv8r_DEPRECATED + fvp_baser_aemv8r/fvp_aemv8r_aarch64 +) +set(fvp_baser_aemv8r_aarch32_DEPRECATED + fvp_baser_aemv8r/fvp_aemv8r_aarch32 +) +set(fvp_baser_aemv8r_aarch32_smp_DEPRECATED + fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp +) +set(fvp_baser_aemv8r_smp_DEPRECATED + fvp_baser_aemv8r/fvp_aemv8r_aarch64/smp +) +set(heltec_wifi_lora32_v2_DEPRECATED + heltec_wifi_lora32_v2/esp32/procpu +) +set(heltec_wireless_stick_lite_v3_DEPRECATED + heltec_wireless_stick_lite_v3/esp32s3/procpu +) +set(hexiwear_k64_DEPRECATED + hexiwear/mk64f12 +) +set(hexiwear_kw40z_DEPRECATED + hexiwear/mkw40z4 +) +set(hifive1_revb_DEPRECATED + hifive1@B +) +set(hsdk_2cores_DEPRECATED + hsdk/arc_hsdk/2cores +) +set(intel_adsp_ace15_mtpm_DEPRECATED + intel_adsp/ace15_mtpm +) +set(intel_adsp_ace20_lnl_DEPRECATED + intel_adsp/ace20_lnl +) +set(intel_adsp_cavs25_DEPRECATED + intel_adsp/cavs25 +) +set(intel_adsp_cavs25_tgph_DEPRECATED + intel_adsp/cavs25/tgph +) +set(intel_ehl_crb_sbl_DEPRECATED + intel_ehl_crb/elkhart_lake/sbl +) +set(kincony_kc868_a32_DEPRECATED + kincony_kc868_a32/esp32/procpu +) +set(longan_nano_lite_DEPRECATED + longan_nano/gd32vf103/lite +) +set(lpcxpresso54114_m0_DEPRECATED + lpcxpresso54114/lpc54114/m0 +) +set(lpcxpresso54114_m4_DEPRECATED + lpcxpresso54114/lpc54114/m4 +) +set(lpcxpresso55s69_cpu0_DEPRECATED + lpcxpresso55s69/lpc55s69/cpu0 +) +set(lpcxpresso55s69_cpu1_DEPRECATED + lpcxpresso55s69/lpc55s69/cpu1 +) +set(lpcxpresso55s69_ns_DEPRECATED + lpcxpresso55s69/lpc55s69/cpu0/ns +) +set(m5stack_atoms3_DEPRECATED + m5stack_atoms3/esp32s3/procpu +) +set(m5stack_atoms3_lite_DEPRECATED + m5stack_atoms3_lite/esp32s3/procpu +) +set(m5stack_core2_DEPRECATED + m5stack_core2/esp32/procpu +) +set(m5stack_stamps3_DEPRECATED + m5stack_stamps3/esp32s3/procpu +) +set(m5stickc_plus_DEPRECATED + m5stickc_plus/esp32/procpu +) +set(mimx8mm_evk_DEPRECATED + imx8mm_evk/mimx8mm6/m4 +) +set(mimx8mm_evk_a53_DEPRECATED + imx8mm_evk/mimx8mm6/a53 +) +set(mimx8mm_evk_a53_smp_DEPRECATED + imx8mm_evk/mimx8mm6/a53/smp +) +set(mimx8mm_phyboard_polis_DEPRECATED + mimx8mm_phyboard_polis/mimx8mm6/m4 +) +set(mimx8mn_evk_a53_DEPRECATED + imx8mn_evk/mimx8mn6/a53 +) +set(mimx8mn_evk_a53_smp_DEPRECATED + imx8mn_evk/mimx8mn6/a53/smp +) +set(mimx8mp_evk_a53_DEPRECATED + imx8mp_evk/mimx8ml8/a53 +) +set(mimx8mp_evk_a53_smp_DEPRECATED + imx8mp_evk/mimx8ml8/a53/smp +) +set(mimx8mp_evk_ddr_DEPRECATED + imx8mp_evk/mimx8ml8/m7/ddr +) +set(mimx8mp_evk_itcm_DEPRECATED + imx8mp_evk/mimx8ml8/m7 +) +set(mimx8mp_phyboard_pollux_DEPRECATED + mimx8mp_phyboard_pollux/mimx8ml8/m7 +) +set(mimx8mq_evk_cm4_DEPRECATED + imx8mq_evk/mimx8mq6/m4 +) +set(mimx93_evk_a55_DEPRECATED + imx93_evk/mimx9352/a55 +) +set(mimxrt1050_evk_qspi_DEPRECATED + mimxrt1050_evk@qspi +) +set(mimxrt1060_evk_hyperflash_DEPRECATED + mimxrt1060_evk@hyperflash +) +set(mimxrt1160_evk_cm4_DEPRECATED + mimxrt1160_evk/mimxrt1166/cm4 +) +set(mimxrt1160_evk_cm7_DEPRECATED + mimxrt1160_evk/mimxrt1166/cm7 +) +set(mimxrt1170_evk_cm4_DEPRECATED + mimxrt1170_evk@A/mimxrt1176/cm4 +) +set(mimxrt1170_evk_cm7_DEPRECATED + mimxrt1170_evk@A/mimxrt1176/cm7 +) +set(mimxrt1170_evkb_cm4_DEPRECATED + mimxrt1170_evk@B/mimxrt1176/cm4 +) +set(mimxrt1170_evkb_cm7_DEPRECATED + mimxrt1170_evk@B/mimxrt1176/cm7 +) +set(mimxrt595_evk_cm33_DEPRECATED + mimxrt595_evk/mimxrt595s/cm33 +) +set(mimxrt685_evk_cm33_DEPRECATED + mimxrt685_evk +) +set(mps2_an385_DEPRECATED + mps2/an385 +) +set(mps2_an521_DEPRECATED + mps2/an521/cpu0 +) +set(mps2_an521_ns_DEPRECATED + mps2/an521/cpu0/ns +) +set(mps2_an521_remote_DEPRECATED + mps2/an521/cpu1 +) +set(mps3_an547_DEPRECATED + mps3 +) +set(mps3_an547_ns_DEPRECATED + mps3/an547/ns +) +set(nrf21540dk_nrf52840_DEPRECATED + nrf21540dk +) +set(nrf51dk_nrf51422_DEPRECATED + nrf51dk +) +set(nrf51dongle_nrf51422_DEPRECATED + nrf51dongle +) +set(nrf52833dk_nrf52820_DEPRECATED + nrf52833dk/nrf52820 +) +set(nrf52833dk_nrf52833_DEPRECATED + nrf52833dk/nrf52833 +) +set(nrf52840dk_nrf52811_DEPRECATED + nrf52840dk/nrf52811 +) +set(nrf52840dk_nrf52840_DEPRECATED + nrf52840dk/nrf52840 +) +set(nrf52840dongle_nrf52840_DEPRECATED + nrf52840dongle +) +set(nrf52dk_nrf52805_DEPRECATED + nrf52dk/nrf52805 +) +set(nrf52dk_nrf52810_DEPRECATED + nrf52dk/nrf52810 +) +set(nrf52dk_nrf52832_DEPRECATED + nrf52dk/nrf52832 +) +set(nrf5340_audio_dk_nrf5340_cpuapp_DEPRECATED + nrf5340_audio_dk/nrf5340/cpuapp +) +set(nrf5340_audio_dk_nrf5340_cpuapp_ns_DEPRECATED + nrf5340_audio_dk/nrf5340/cpuapp/ns +) +set(nrf5340_audio_dk_nrf5340_cpunet_DEPRECATED + nrf5340_audio_dk/nrf5340/cpunet +) +set(nrf5340dk_nrf5340_cpuapp_DEPRECATED + nrf5340dk/nrf5340/cpuapp +) +set(nrf5340dk_nrf5340_cpuapp_ns_DEPRECATED + nrf5340dk/nrf5340/cpuapp/ns +) +set(nrf5340dk_nrf5340_cpunet_DEPRECATED + nrf5340dk/nrf5340/cpunet +) +set(nrf54h20pdk_nrf54h20_cpuapp_DEPRECATED + nrf54h20pdk/nrf54h20/cpuapp +) +set(nrf54h20pdk_nrf54h20_cpuppr_DEPRECATED + nrf54h20pdk/nrf54h20/cpuppr +) +set(nrf54h20pdk_nrf54h20_cpurad_DEPRECATED + nrf54h20pdk/nrf54h20/cpurad +) +set(nrf54l15pdk_nrf54l15_cpuapp_DEPRECATED + nrf54l15pdk/nrf54l15/cpuapp +) +set(nrf9131ek_nrf9131_DEPRECATED + nrf9131ek +) +set(nrf9131ek_nrf9131_ns_DEPRECATED + nrf9131ek/nrf9131/ns +) +set(nrf9151dk_nrf9151_DEPRECATED + nrf9151dk +) +set(nrf9151dk_nrf9151_ns_DEPRECATED + nrf9151dk/nrf9151/ns +) +set(nrf9160_innblue21_DEPRECATED + innblue21 +) +set(nrf9160_innblue21_ns_DEPRECATED + innblue21/nrf9160/ns +) +set(nrf9160_innblue22_DEPRECATED + innblue22 +) +set(nrf9160_innblue22_ns_DEPRECATED + innblue22/nrf9160/ns +) +set(nrf9160dk_nrf52840_DEPRECATED + nrf9160dk/nrf52840 +) +set(nrf9160dk_nrf9160_DEPRECATED + nrf9160dk/nrf9160 +) +set(nrf9160dk_nrf9160_ns_DEPRECATED + nrf9160dk/nrf9160/ns +) +set(nrf9161dk_nrf9161_DEPRECATED + nrf9161dk +) +set(nrf9161dk_nrf9161_ns_DEPRECATED + nrf9161dk/nrf9161/ns +) +set(nsim_em_DEPRECATED + nsim/nsim_em +) +set(nsim_em11d_DEPRECATED + nsim/nsim_em11d +) +set(nsim_em7d_v22_DEPRECATED + nsim/nsim_em7d_v22 +) +set(nsim_hs_DEPRECATED + nsim/nsim_hs +) +set(nsim_hs3x_hostlink_DEPRECATED + nsim/nsim_hs/hostlink +) +set(nsim_hs5x_DEPRECATED + nsim/nsim_hs5x +) +set(nsim_hs5x_smp_DEPRECATED + nsim/nsim_hs5x/smp +) +set(nsim_hs5x_smp_12cores_DEPRECATED + nsim/nsim_hs5x/smp/12cores +) +set(nsim_hs6x_DEPRECATED + nsim/nsim_hs6x +) +set(nsim_hs6x_smp_DEPRECATED + nsim/nsim_hs6x/smp +) +set(nsim_hs6x_smp_12cores_DEPRECATED + nsim/nsim_hs6x/smp/12cores +) +set(nsim_hs_flash_xip_DEPRECATED + nsim/nsim_hs/flash_xip +) +set(nsim_hs_mpuv6_DEPRECATED + nsim/nsim_hs/mpuv6 +) +set(nsim_hs_smp_DEPRECATED + nsim/nsim_hs/smp +) +set(nsim_hs_sram_DEPRECATED + nsim/nsim_hs/sram +) +set(nsim_sem_DEPRECATED + nsim/nsim_sem +) +set(nsim_sem_mpu_stack_guard_DEPRECATED + nsim/nsim_sem/mpu_stack_guard +) +set(nsim_vpx5_DEPRECATED + nsim/nsim_vpx5 +) +set(nucleo_h745zi_q_m4_DEPRECATED + nucleo_h745zi_q/stm32h745xx/m4 +) +set(nucleo_h745zi_q_m7_DEPRECATED + nucleo_h745zi_q/stm32h745xx/m7 +) +set(nucleo_l452re_p_DEPRECATED + nucleo_l452re/stm32l452xx/p +) +set(nucleo_l552ze_q_ns_DEPRECATED + nucleo_l552ze_q/stm32l552xx/ns +) +set(nuvoton_pfm_m487_DEPRECATED + numaker_pfm_m487 +) +set(nxp_adsp_imx8_DEPRECATED + imx8qm_mek/mimx8qm6/adsp +) +set(nxp_adsp_imx8m_DEPRECATED + imx8mp_evk/mimx8ml8/adsp +) +set(nxp_adsp_imx8ulp_DEPRECATED + imx8ulp_evk/imx8ulp/adsp +) +set(nxp_adsp_imx8x_DEPRECATED + imx8qxp_mek/mimx8qx6/adsp +) +set(nxp_adsp_rt595_DEPRECATED + mimxrt595_evk/mimxrt595s/f1 +) +set(nxp_ls1046ardb_DEPRECATED + ls1046ardb +) +set(nxp_ls1046ardb_smp_2cores_DEPRECATED + ls1046ardb/ls1046a/smp +) +set(nxp_ls1046ardb_smp_4cores_DEPRECATED + ls1046ardb/ls1046a/smp/4cores +) +set(odroid_go_DEPRECATED + odroid_go/esp32/procpu +) +set(olimex_esp32_evb_DEPRECATED + olimex_esp32_evb/esp32/procpu +) +set(pan1783_evb_cpuapp_DEPRECATED + pan1783_evb/nrf5340/cpuapp +) +set(pan1783_evb_cpunet_DEPRECATED + pan1783_evb/nrf5340/cpunet +) +set(pan1783a_evb_cpuapp_DEPRECATED + pan1783a_evb/nrf5340/cpuapp +) +set(pan1783a_evb_cpunet_DEPRECATED + pan1783a_evb/nrf5340/cpunet +) +set(pan1783a_pa_evb_cpuapp_DEPRECATED + pan1783a_pa_evb/nrf5340/cpuapp +) +set(pan1783a_pa_evb_cpunet_DEPRECATED + pan1783a_pa_evb/nrf5340/cpunet +) +set(phycore_am62x_a53_DEPRECATED + phycore_am62x/am6234/a53 +) +set(pico_pi_m4_DEPRECATED + pico_pi/mcimx7d/m4 +) +set(qemu_arc_em_DEPRECATED + qemu_arc/qemu_arc_em +) +set(qemu_arc_hs_DEPRECATED + qemu_arc/qemu_arc_hs +) +set(qemu_arc_hs5x_DEPRECATED + qemu_arc/qemu_arc_hs5x +) +set(qemu_arc_hs6x_DEPRECATED + qemu_arc/qemu_arc_hs6x +) +set(qemu_arc_hs_xip_DEPRECATED + qemu_arc/qemu_arc_hs/xip +) +set(qemu_cortex_a53_smp_DEPRECATED + qemu_cortex_a53/qemu_cortex_a53/smp +) +set(qemu_cortex_a53_xip_DEPRECATED + qemu_cortex_a53/qemu_cortex_a53/xip +) +set(qemu_malta_be_DEPRECATED + qemu_malta/qemu_malta/be +) +set(qemu_riscv32_smp_DEPRECATED + qemu_riscv32/qemu_virt_riscv32/smp +) +set(qemu_riscv64_smp_DEPRECATED + qemu_riscv64/qemu_virt_riscv64/smp +) +set(qemu_x86_64_nokpti_DEPRECATED + qemu_x86_64/atom/nokpti +) +set(qemu_x86_nokpti_DEPRECATED + qemu_x86/atom/nokpti +) +set(qemu_x86_nommu_DEPRECATED + qemu_x86/atom/nommu +) +set(qemu_x86_nopae_DEPRECATED + qemu_x86/atom/nopae +) +set(qemu_x86_virt_DEPRECATED + qemu_x86/atom/virt +) +set(qemu_x86_xip_DEPRECATED + qemu_x86/atom/xip +) +set(qemu_xtensa_mmu_DEPRECATED + qemu_xtensa/dc233c/mmu +) +set(rak4631_nrf52840_DEPRECATED + rak4631 +) +set(rak5010_nrf52840_DEPRECATED + rak5010 +) +set(raytac_mdbt50q_db_33_nrf52833_DEPRECATED + raytac_mdbt50q_db_33 +) +set(raytac_mdbt50q_db_40_nrf52840_DEPRECATED + raytac_mdbt50q_db_40 +) +set(raytac_mdbt53_db_40_nrf5340_cpuapp_DEPRECATED + raytac_mdbt53_db_40/nrf5340/cpuapp +) +set(raytac_mdbt53_db_40_nrf5340_cpuapp_ns_DEPRECATED + raytac_mdbt53_db_40/nrf5340/cpuapp/ns +) +set(raytac_mdbt53_db_40_nrf5340_cpunet_DEPRECATED + raytac_mdbt53_db_40/nrf5340/cpunet +) +set(raytac_mdbt53v_db_40_nrf5340_cpuapp_DEPRECATED + raytac_mdbt53v_db_40/nrf5340/cpuapp +) +set(raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_DEPRECATED + raytac_mdbt53v_db_40/nrf5340/cpuapp/ns +) +set(raytac_mdbt53v_db_40_nrf5340_cpunet_DEPRECATED + raytac_mdbt53v_db_40/nrf5340/cpunet +) +set(rcar_h3_salvatorx_cr7_DEPRECATED + rcar_salvator_x/r8a77951/r7 +) +set(rcar_h3ulcb_ca57_DEPRECATED + rcar_h3ulcb/r8a77951/a57 +) +set(rcar_h3ulcb_cr7_DEPRECATED + rcar_h3ulcb/r8a77951/r7 +) +set(rcar_salvator_xs_m3_DEPRECATED + rcar_salvator_xs +) +set(rcar_spider_cr52_DEPRECATED + rcar_spider_s4 +) +set(reel_board_v2_DEPRECATED + reel_board@2 +) +set(roc_rk3568_pc_smp_DEPRECATED + roc_rk3568_pc/rk3568/smp +) +set(rpi_pico_w_DEPRECATED + rpi_pico/rp2040/w +) +set(rv32m1_vega_ri5cy_DEPRECATED + rv32m1_vega/openisa_rv32m1/ri5cy +) +set(rv32m1_vega_zero_riscy_DEPRECATED + rv32m1_vega/openisa_rv32m1/zero_riscy +) +set(s32z270dc2_rtu0_r52_DEPRECATED + s32z2xxdc2/s32z270/rtu0 +) +set(s32z270dc2_rtu1_r52_DEPRECATED + s32z2xxdc2/s32z270/rtu1 +) +set(sam_e70_xplained_DEPRECATED + sam_e70_xplained/same70q21 +) +set(sam_e70b_xplained_DEPRECATED + sam_e70_xplained/same70q21b +) +set(sam_v71_xult_DEPRECATED + sam_v71_xult/samv71q21 +) +set(sam_v71b_xult_DEPRECATED + sam_v71_xult/samv71q21b +) +set(sparkfun_thing_plus_nrf9160_DEPRECATED + sparkfun_thing_plus +) +set(sparkfun_thing_plus_nrf9160_ns_DEPRECATED + sparkfun_thing_plus/nrf9160/ns +) +set(stm32_min_dev_black_DEPRECATED + stm32_min_dev@black +) +set(stm32_min_dev_blue_DEPRECATED + stm32_min_dev@blue +) +set(stm32h747i_disco_m4_DEPRECATED + stm32h747i_disco/stm32h747xx/m4 +) +set(stm32h747i_disco_m7_DEPRECATED + stm32h747i_disco/stm32h747xx/m7 +) +set(stm32l562e_dk_ns_DEPRECATED + stm32l562e_dk/stm32l562xx/ns +) +set(tdk_robokit1_DEPRECATED + robokit1 +) +set(thingy52_nrf52832_DEPRECATED + thingy52 +) +set(thingy53_nrf5340_cpuapp_DEPRECATED + thingy53/nrf5340/cpuapp +) +set(thingy53_nrf5340_cpuapp_ns_DEPRECATED + thingy53/nrf5340/cpuapp/ns +) +set(thingy53_nrf5340_cpunet_DEPRECATED + thingy53/nrf5340/cpunet +) +set(ubx_bmd300eval_nrf52832_DEPRECATED + ubx_bmd300eval +) +set(ubx_bmd330eval_nrf52810_DEPRECATED + ubx_bmd330eval +) +set(ubx_bmd340eval_nrf52840_DEPRECATED + ubx_bmd340eval +) +set(ubx_bmd345eval_nrf52840_DEPRECATED + ubx_bmd345eval +) +set(ubx_bmd360eval_nrf52811_DEPRECATED + ubx_bmd360eval +) +set(ubx_bmd380eval_nrf52840_DEPRECATED + ubx_bmd380eval +) +set(ubx_evkannab1_nrf52832_DEPRECATED + ubx_evkannab1 +) +set(ubx_evkninab1_nrf52832_DEPRECATED + ubx_evkninab1 +) +set(ubx_evkninab3_nrf52840_DEPRECATED + ubx_evkninab3 +) +set(ubx_evkninab4_nrf52833_DEPRECATED + ubx_evkninab4 +) +set(udoo_neo_full_m4_DEPRECATED + udoo_neo_full/mcimx6x/m4 +) +set(v2m_musca_b1_ns_DEPRECATED + v2m_musca_b1/musca_b1/ns +) +set(v2m_musca_s1_ns_DEPRECATED + v2m_musca_s1/musca_s1/ns +) +set(verdin_imx8mp_m7_ddr_DEPRECATED + verdin_imx8mp/mimx8ml8/m7/ddr +) +set(verdin_imx8mp_m7_itcm_DEPRECATED + verdin_imx8mp/mimx8ml8/m7 +) +set(vmu_rt1170_DEPRECATED + vmu_rt1170/mimxrt1176/cm7 +) +set(warp7_m4_DEPRECATED + warp7/mcimx7d/m4 +) +set(we_ophelia1ev_nrf52805_DEPRECATED + we_ophelia1ev +) +set(we_proteus2ev_nrf52832_DEPRECATED + we_proteus2ev +) +set(we_proteus3ev_nrf52840_DEPRECATED + we_proteus3ev +) +set(xenvm_gicv3_DEPRECATED + xenvm/xenvm/gicv3 +) +set(xiao_ble_sense_DEPRECATED + xiao_ble/nrf52840/sense +) +set(xiao_esp32s3_DEPRECATED + xiao_esp32s3/esp32s3/procpu +) +set(yd_esp32_DEPRECATED + yd_esp32/esp32/procpu +) From 6fa439738e3400068d93d3f2a79337c000bb9742 Mon Sep 17 00:00:00 2001 From: Carles Cufi Date: Sat, 2 Mar 2024 18:41:14 +0100 Subject: [PATCH 0033/2402] doc: relnotes: Add notes for Hardware Model v2 Include notes in the release notes and migration guide for Hardware Model v2. Signed-off-by: Carles Cufi --- doc/releases/migration-guide-3.7.rst | 6 ++++++ doc/releases/release-notes-3.7.rst | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index 64763e03d7c..3398e1e9df6 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -18,6 +18,12 @@ the :ref:`release notes`. Build System ************ +* Completely overhauled the way SoCs and boards are defined. This requires all + out-of-tree SoCs and boards to be ported to the new model. See the + :ref:`board_porting_guide` for more detailed information. + * Pull Request: https://github.com/zephyrproject-rtos/zephyr/pull/69607 + * Issue: https://github.com/zephyrproject-rtos/zephyr/issues/51831 + Kernel ****** diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index d97f69bf628..6ad59d5988f 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -9,6 +9,10 @@ We are pleased to announce the release of Zephyr version 3.7.0. Major enhancements with this release include: +* A new, completely overhauled hardware model has been introduced. This changes + the way both SoCs and boards are named, defined and constructed in Zephyr. + Additional information can be found in the :ref:`board_porting_guide`. + An overview of the changes required or recommended when migrating your application from Zephyr v3.6.0 to Zephyr v3.7.0 can be found in the separate :ref:`migration guide`. From cf4f90a712aca934a3adafcab3664a148feb2550 Mon Sep 17 00:00:00 2001 From: Kelly Lord Date: Sat, 7 Oct 2023 18:25:23 -0400 Subject: [PATCH 0034/2402] samples: usb: mass Raspberry Pi Pico Support Added a flash partition for the mass storage example. Signed-off-by: Kelly Lord --- .../subsys/usb/mass/boards/rpi_pico.overlay | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 samples/subsys/usb/mass/boards/rpi_pico.overlay diff --git a/samples/subsys/usb/mass/boards/rpi_pico.overlay b/samples/subsys/usb/mass/boards/rpi_pico.overlay new file mode 100644 index 00000000000..bdafdd3c259 --- /dev/null +++ b/samples/subsys/usb/mass/boards/rpi_pico.overlay @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2024 Kelly Lord + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/delete-node/ &code_partition; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 1MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code"; + reg = <0x100 (DT_SIZE_M(1) - 0x100)>; + read-only; + }; + + storage_partition: partition@100000 { + label = "storage"; + reg = <0x100000 DT_SIZE_M(1)>; + }; + }; +}; + +/ { + msc_disk0 { + compatible = "zephyr,flash-disk"; + partition = <&storage_partition>; + disk-name = "NAND"; + cache-size = <4096>; + }; +}; From 2e2cfb063d5b7f9ef7baf7fcc2fdf4bf33eeb709 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Sat, 2 Mar 2024 16:57:00 -0500 Subject: [PATCH 0035/2402] tests: drivers/flash: fix suite identifier Fix name of scenario, we do not support / in scenario names. Signed-off-by: Anas Nashif --- tests/drivers/flash/common/testcase.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/drivers/flash/common/testcase.yaml b/tests/drivers/flash/common/testcase.yaml index 7b7827db069..0e0b1ce546d 100644 --- a/tests/drivers/flash/common/testcase.yaml +++ b/tests/drivers/flash/common/testcase.yaml @@ -24,7 +24,7 @@ tests: fixture: external_flash_mx25l51245g integration_platforms: - nrf52840dk/nrf52840 - drivers.flash.common.soc_flash/nrf: + drivers.flash.common.soc_flash_nrf: platform_allow: nrf52840dk/nrf52840 extra_args: OVERLAY_CONFIG=boards/nrf52840_flash_soc.conf integration_platforms: From 1b0f9e865e35a6b3e1ca8aad7a67f7cfbfc2e666 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 31 Jan 2024 17:39:44 +0200 Subject: [PATCH 0036/2402] net: ipv4: Make netmask IPv4 address specific The netmask should be tied to the IPv4 address instead of being global for the network interface. If there is only one IPv4 address specified to the network interface, nothing changes from user point of view. But if there are more than one IPv4 address / network interface, the netmask must be specified to each address separately. This means that net_if_ipv4_get_netmask() and net_if_ipv4_set_netmask() functions should not be used as they only work reliably if there is only one IPv4 address in the network interface. The new net_if_ipv4_get_netmask_by_addr() and net_if_ipv4_set_netmask_by_addr() functions should be used as they make sure that the netmask is tied to correct IPv4 address in the network interface. Signed-off-by: Jukka Rissanen --- include/zephyr/net/net_if.h | 55 +++++- subsys/net/ip/ipv4_autoconf.c | 4 +- subsys/net/ip/net_if.c | 241 +++++++++++++++++++++----- subsys/net/l2/ethernet/arp.c | 10 +- subsys/net/lib/capture/capture.c | 4 +- subsys/net/lib/config/init.c | 10 +- subsys/net/lib/dhcpv4/dhcpv4.c | 4 +- subsys/net/lib/dhcpv4/dhcpv4_server.c | 2 +- subsys/net/lib/shell/iface.c | 8 +- subsys/net/lib/shell/ipv4.c | 17 +- subsys/net/lib/shell/tcp.c | 2 +- 11 files changed, 286 insertions(+), 71 deletions(-) diff --git a/include/zephyr/net/net_if.h b/include/zephyr/net/net_if.h index b0478eee9ae..387e742d0b9 100644 --- a/include/zephyr/net/net_if.h +++ b/include/zephyr/net/net_if.h @@ -368,9 +368,21 @@ struct net_if_dhcpv6 { #endif /** @endcond */ +/** + * @brief Network Interface unicast IPv4 address and netmask + * + * Stores the unicast IPv4 address and related netmask. + */ +struct net_if_addr_ipv4 { + /** IPv4 address */ + struct net_if_addr ipv4; + /** Netmask */ + struct in_addr netmask; +}; + struct net_if_ipv4 { /** Unicast IP addresses */ - struct net_if_addr unicast[NET_IF_MAX_IPV4_ADDR]; + struct net_if_addr_ipv4 unicast[NET_IF_MAX_IPV4_ADDR]; /** Multicast IP addresses */ struct net_if_mcast_addr mcast[NET_IF_MAX_IPV4_MADDR]; @@ -378,9 +390,6 @@ struct net_if_ipv4 { /** Gateway */ struct in_addr gw; - /** Netmask */ - struct in_addr netmask; - /** IPv4 time-to-live */ uint8_t ttl; @@ -2341,6 +2350,18 @@ struct in_addr *net_if_ipv4_get_ll(struct net_if *iface, struct in_addr *net_if_ipv4_get_global_addr(struct net_if *iface, enum net_addr_state addr_state); +/** + * @brief Get IPv4 netmask related to an address of an interface. + * + * @param iface Interface to use. + * @param addr IPv4 address to check. + * + * @return The netmask set on the interface related to the give address, + * unspecified address if not found. + */ +struct in_addr net_if_ipv4_get_netmask_by_addr(struct net_if *iface, + const struct in_addr *addr); + /** * @brief Get IPv4 netmask of an interface. * @@ -2370,6 +2391,32 @@ void net_if_ipv4_set_netmask(struct net_if *iface, __syscall bool net_if_ipv4_set_netmask_by_index(int index, const struct in_addr *netmask); +/** + * @brief Set IPv4 netmask for an interface index for a given address. + * + * @param index Network interface index + * @param addr IPv4 address related to this netmask + * @param netmask IPv4 netmask + * + * @return True if netmask was added, false otherwise. + */ +__syscall bool net_if_ipv4_set_netmask_by_addr_by_index(int index, + const struct in_addr *addr, + const struct in_addr *netmask); + +/** + * @brief Set IPv4 netmask for an interface index for a given address. + * + * @param iface Network interface + * @param addr IPv4 address related to this netmask + * @param netmask IPv4 netmask + * + * @return True if netmask was added, false otherwise. + */ +bool net_if_ipv4_set_netmask_by_addr(struct net_if *iface, + const struct in_addr *addr, + const struct in_addr *netmask); + /** * @brief Set IPv4 gateway for an interface. * diff --git a/subsys/net/ip/ipv4_autoconf.c b/subsys/net/ip/ipv4_autoconf.c index aa18a27ef63..e34b51523c3 100644 --- a/subsys/net/ip/ipv4_autoconf.c +++ b/subsys/net/ip/ipv4_autoconf.c @@ -182,7 +182,9 @@ static inline void ipv4_autoconf_addr_set(struct net_if_ipv4_autoconf *ipv4auto) return; } - net_if_ipv4_set_netmask(ipv4auto->iface, &netmask); + net_if_ipv4_set_netmask_by_addr(ipv4auto->iface, + &ipv4auto->requested_ip, + &netmask); ipv4auto->state = NET_IPV4_AUTOCONF_ASSIGNED; } diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 5bb862896ed..7a6cfc34821 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -3361,16 +3361,17 @@ bool net_if_ipv4_addr_mask_cmp(struct net_if *iface, goto out; } - subnet = UNALIGNED_GET(&addr->s_addr) & ipv4->netmask.s_addr; - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (!ipv4->unicast[i].is_used || - ipv4->unicast[i].address.family != AF_INET) { + if (!ipv4->unicast[i].ipv4.is_used || + ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; } - if ((ipv4->unicast[i].address.in_addr.s_addr & - ipv4->netmask.s_addr) == subnet) { + subnet = UNALIGNED_GET(&addr->s_addr) & + ipv4->unicast[i].netmask.s_addr; + + if ((ipv4->unicast[i].ipv4.address.in_addr.s_addr & + ipv4->unicast[i].netmask.s_addr) == subnet) { ret = true; goto out; } @@ -3387,6 +3388,7 @@ static bool ipv4_is_broadcast_address(struct net_if *iface, { struct net_if_ipv4 *ipv4; bool ret = false; + struct in_addr bcast; net_if_lock(iface); @@ -3396,15 +3398,19 @@ static bool ipv4_is_broadcast_address(struct net_if *iface, goto out; } - if (!net_if_ipv4_addr_mask_cmp(iface, addr)) { - ret = false; - goto out; - } + for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + if (!ipv4->unicast[i].ipv4.is_used || + ipv4->unicast[i].ipv4.address.family != AF_INET) { + continue; + } - if ((UNALIGNED_GET(&addr->s_addr) & ~ipv4->netmask.s_addr) == - ~ipv4->netmask.s_addr) { - ret = true; - goto out; + bcast.s_addr = ipv4->unicast[i].ipv4.address.in_addr.s_addr | + ~ipv4->unicast[i].netmask.s_addr; + + if (bcast.s_addr == addr->s_addr) { + ret = true; + goto out; + } } out: @@ -3489,14 +3495,14 @@ static struct in_addr *net_if_ipv4_get_best_match(struct net_if *iface, } for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (!is_proper_ipv4_address(&ipv4->unicast[i])) { + if (!is_proper_ipv4_address(&ipv4->unicast[i].ipv4)) { continue; } - len = get_diff_ipv4(dst, &ipv4->unicast[i].address.in_addr); + len = get_diff_ipv4(dst, &ipv4->unicast[i].ipv4.address.in_addr); if (len >= *best_so_far) { *best_so_far = len; - src = &ipv4->unicast[i].address.in_addr; + src = &ipv4->unicast[i].ipv4.address.in_addr; } } @@ -3525,14 +3531,14 @@ static struct in_addr *if_ipv4_get_addr(struct net_if *iface, } for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (!ipv4->unicast[i].is_used || + if (!ipv4->unicast[i].ipv4.is_used || (addr_state != NET_ADDR_ANY_STATE && - ipv4->unicast[i].addr_state != addr_state) || - ipv4->unicast[i].address.family != AF_INET) { + ipv4->unicast[i].ipv4.addr_state != addr_state) || + ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; } - if (net_ipv4_is_ll_addr(&ipv4->unicast[i].address.in_addr)) { + if (net_ipv4_is_ll_addr(&ipv4->unicast[i].ipv4.address.in_addr)) { if (!ll) { continue; } @@ -3542,7 +3548,7 @@ static struct in_addr *if_ipv4_get_addr(struct net_if *iface, } } - addr = &ipv4->unicast[i].address.in_addr; + addr = &ipv4->unicast[i].ipv4.address.in_addr; goto out; } @@ -3651,19 +3657,19 @@ struct net_if_addr *net_if_ipv4_addr_lookup(const struct in_addr *addr, } for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (!ipv4->unicast[i].is_used || - ipv4->unicast[i].address.family != AF_INET) { + if (!ipv4->unicast[i].ipv4.is_used || + ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; } if (UNALIGNED_GET(&addr->s4_addr32[0]) == - ipv4->unicast[i].address.in_addr.s_addr) { + ipv4->unicast[i].ipv4.address.in_addr.s_addr) { if (ret) { *ret = iface; } - ifaddr = &ipv4->unicast[i]; + ifaddr = &ipv4->unicast[i].ipv4; net_if_unlock(iface); goto out; } @@ -3702,9 +3708,97 @@ static inline int z_vrfy_net_if_ipv4_addr_lookup_by_index( #include #endif +struct in_addr net_if_ipv4_get_netmask_by_addr(struct net_if *iface, + const struct in_addr *addr) +{ + struct in_addr netmask = { 0 }; + struct net_if_ipv4 *ipv4; + uint32_t subnet; + + net_if_lock(iface); + + if (net_if_config_ipv4_get(iface, NULL) < 0) { + goto out; + } + + ipv4 = iface->config.ip.ipv4; + if (ipv4 == NULL) { + goto out; + } + + for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + if (!ipv4->unicast[i].ipv4.is_used || + ipv4->unicast[i].ipv4.address.family != AF_INET) { + continue; + } + + subnet = UNALIGNED_GET(&addr->s_addr) & + ipv4->unicast[i].netmask.s_addr; + + if ((ipv4->unicast[i].ipv4.address.in_addr.s_addr & + ipv4->unicast[i].netmask.s_addr) == subnet) { + netmask = ipv4->unicast[i].netmask; + goto out; + } + } + +out: + net_if_unlock(iface); + + return netmask; +} + +bool net_if_ipv4_set_netmask_by_addr(struct net_if *iface, + const struct in_addr *addr, + const struct in_addr *netmask) +{ + struct net_if_ipv4 *ipv4; + uint32_t subnet; + bool ret = false; + + net_if_lock(iface); + + if (net_if_config_ipv4_get(iface, NULL) < 0) { + goto out; + } + + ipv4 = iface->config.ip.ipv4; + if (ipv4 == NULL) { + goto out; + } + + for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + if (!ipv4->unicast[i].ipv4.is_used || + ipv4->unicast[i].ipv4.address.family != AF_INET) { + continue; + } + + subnet = UNALIGNED_GET(&addr->s_addr) & + ipv4->unicast[i].netmask.s_addr; + + if ((ipv4->unicast[i].ipv4.address.in_addr.s_addr & + ipv4->unicast[i].netmask.s_addr) == subnet) { + ipv4->unicast[i].netmask = *netmask; + ret = true; + goto out; + } + } + +out: + net_if_unlock(iface); + + return ret; +} + +/* Using this function is problematic as if we have multiple + * addresses configured, which one to return. Use heuristic + * in this case and return the first one found. Please use + * net_if_ipv4_get_netmask_by_addr() instead. + */ struct in_addr net_if_ipv4_get_netmask(struct net_if *iface) { struct in_addr netmask = { 0 }; + struct net_if_ipv4 *ipv4; net_if_lock(iface); @@ -3712,31 +3806,58 @@ struct in_addr net_if_ipv4_get_netmask(struct net_if *iface) goto out; } - if (!iface->config.ip.ipv4) { + ipv4 = iface->config.ip.ipv4; + if (ipv4 == NULL) { goto out; } - netmask = iface->config.ip.ipv4->netmask; + for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + if (!ipv4->unicast[i].ipv4.is_used || + ipv4->unicast[i].ipv4.address.family != AF_INET) { + continue; + } + + netmask = iface->config.ip.ipv4->unicast[i].netmask; + break; + } + out: net_if_unlock(iface); return netmask; } +/* Using this function is problematic as if we have multiple + * addresses configured, which one to set. Use heuristic + * in this case and set the first one found. Please use + * net_if_ipv4_set_netmask_by_addr() instead. + */ void net_if_ipv4_set_netmask(struct net_if *iface, const struct in_addr *netmask) { + struct net_if_ipv4 *ipv4; + net_if_lock(iface); if (net_if_config_ipv4_get(iface, NULL) < 0) { goto out; } - if (!iface->config.ip.ipv4) { + ipv4 = iface->config.ip.ipv4; + if (ipv4 == NULL) { goto out; } - net_ipaddr_copy(&iface->config.ip.ipv4->netmask, netmask); + for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + if (!ipv4->unicast[i].ipv4.is_used || + ipv4->unicast[i].ipv4.address.family != AF_INET) { + continue; + } + + net_ipaddr_copy(&ipv4->unicast[i].netmask, netmask); + break; + } + out: net_if_unlock(iface); } @@ -3756,6 +3877,22 @@ bool z_impl_net_if_ipv4_set_netmask_by_index(int index, return true; } +bool z_impl_net_if_ipv4_set_netmask_by_addr_by_index(int index, + const struct in_addr *addr, + const struct in_addr *netmask) +{ + struct net_if *iface; + + iface = net_if_get_by_index(index); + if (!iface) { + return false; + } + + net_if_ipv4_set_netmask_by_addr(iface, addr, netmask); + + return true; +} + #ifdef CONFIG_USERSPACE bool z_vrfy_net_if_ipv4_set_netmask_by_index(int index, const struct in_addr *netmask) @@ -3775,6 +3912,30 @@ bool z_vrfy_net_if_ipv4_set_netmask_by_index(int index, } #include + +bool z_vrfy_net_if_ipv4_set_netmask_by_addr_by_index(int index, + const struct in_addr *addr, + const struct in_addr *netmask) +{ + struct in_addr ipv4_addr, netmask_addr; + struct net_if *iface; + + iface = z_vrfy_net_if_get_by_index(index); + if (!iface) { + return false; + } + + K_OOPS(k_usermode_from_copy(&ipv4_addr, (void *)addr, + sizeof(ipv4_addr))); + K_OOPS(k_usermode_from_copy(&netmask_addr, (void *)netmask, + sizeof(netmask_addr))); + + return z_impl_net_if_ipv4_set_netmask_by_addr_by_index(index, + &ipv4_addr, + &netmask_addr); +} + +#include #endif /* CONFIG_USERSPACE */ void net_if_ipv4_set_gw(struct net_if *iface, const struct in_addr *gw) @@ -3836,13 +3997,13 @@ static struct net_if_addr *ipv4_addr_find(struct net_if *iface, int i; for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (!ipv4->unicast[i].is_used) { + if (!ipv4->unicast[i].ipv4.is_used) { continue; } if (net_ipv4_addr_cmp(addr, - &ipv4->unicast[i].address.in_addr)) { - return &ipv4->unicast[i]; + &ipv4->unicast[i].ipv4.address.in_addr)) { + return &ipv4->unicast[i].ipv4; } } @@ -3871,7 +4032,7 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface, } for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - struct net_if_addr *cur = &ipv4->unicast[i]; + struct net_if_addr *cur = &ipv4->unicast[i].ipv4; if (addr_type == NET_ADDR_DHCP && cur->addr_type == NET_ADDR_OVERRIDABLE) { @@ -3879,7 +4040,7 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface, break; } - if (!ipv4->unicast[i].is_used) { + if (!ipv4->unicast[i].ipv4.is_used) { ifaddr = cur; break; } @@ -3935,23 +4096,23 @@ bool net_if_ipv4_addr_rm(struct net_if *iface, const struct in_addr *addr) } for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (!ipv4->unicast[i].is_used) { + if (!ipv4->unicast[i].ipv4.is_used) { continue; } - if (!net_ipv4_addr_cmp(&ipv4->unicast[i].address.in_addr, + if (!net_ipv4_addr_cmp(&ipv4->unicast[i].ipv4.address.in_addr, addr)) { continue; } - ipv4->unicast[i].is_used = false; + ipv4->unicast[i].ipv4.is_used = false; NET_DBG("[%d] interface %p address %s removed", i, iface, net_sprint_ipv4_addr(addr)); net_mgmt_event_notify_with_info( NET_EVENT_IPV4_ADDR_DEL, iface, - &ipv4->unicast[i].address.in_addr, + &ipv4->unicast[i].ipv4.address.in_addr, sizeof(struct in_addr)); ret = true; @@ -4056,7 +4217,7 @@ void net_if_ipv4_addr_foreach(struct net_if *iface, net_if_ip_addr_cb_t cb, } for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - struct net_if_addr *if_addr = &ipv4->unicast[i]; + struct net_if_addr *if_addr = &ipv4->unicast[i].ipv4; if (!if_addr->is_used) { continue; diff --git a/subsys/net/l2/ethernet/arp.c b/subsys/net/l2/ethernet/arp.c index 27fb70a6aaf..93b63f246ad 100644 --- a/subsys/net/l2/ethernet/arp.c +++ b/subsys/net/l2/ethernet/arp.c @@ -227,13 +227,13 @@ static inline struct in_addr *if_get_addr(struct net_if *iface, } for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (ipv4->unicast[i].is_used && - ipv4->unicast[i].address.family == AF_INET && - ipv4->unicast[i].addr_state == NET_ADDR_PREFERRED && + if (ipv4->unicast[i].ipv4.is_used && + ipv4->unicast[i].ipv4.address.family == AF_INET && + ipv4->unicast[i].ipv4.addr_state == NET_ADDR_PREFERRED && (!addr || net_ipv4_addr_cmp(addr, - &ipv4->unicast[i].address.in_addr))) { - return &ipv4->unicast[i].address.in_addr; + &ipv4->unicast[i].ipv4.address.in_addr))) { + return &ipv4->unicast[i].ipv4.address.in_addr; } } diff --git a/subsys/net/lib/capture/capture.c b/subsys/net/lib/capture/capture.c index 91ed775ad45..27114ca7e67 100644 --- a/subsys/net/lib/capture/capture.c +++ b/subsys/net/lib/capture/capture.c @@ -230,7 +230,9 @@ static int setup_iface(struct net_if *iface, const char *ipaddr, /* Set the netmask so that we do not get IPv4 traffic routed * into this interface. */ - net_if_ipv4_set_netmask(iface, &netmask); + net_if_ipv4_set_netmask_by_addr(iface, + &net_sin(addr)->sin_addr, + &netmask); *addr_len = sizeof(struct sockaddr_in); } else { diff --git a/subsys/net/lib/config/init.c b/subsys/net/lib/config/init.c index fcd379c1559..a54fc0ed5c9 100644 --- a/subsys/net/lib/config/init.c +++ b/subsys/net/lib/config/init.c @@ -70,7 +70,7 @@ static void ipv4_addr_add_handler(struct net_mgmt_event_callback *cb, for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { struct net_if_addr *if_addr = - &iface->config.ip.ipv4->unicast[i]; + &iface->config.ip.ipv4->unicast[i].ipv4; if (if_addr->addr_type != NET_ADDR_DHCP || !if_addr->is_used) { continue; @@ -85,7 +85,7 @@ static void ipv4_addr_add_handler(struct net_mgmt_event_callback *cb, iface->config.dhcpv4.lease_time); NET_INFO("Subnet: %s", net_addr_ntop(AF_INET, - &iface->config.ip.ipv4->netmask, + &iface->config.ip.ipv4->unicast[i].netmask, hr_addr, sizeof(hr_addr))); NET_INFO("Router: %s", net_addr_ntop(AF_INET, @@ -141,7 +141,7 @@ static void setup_ipv4(struct net_if *iface) #if CONFIG_NET_CONFIG_LOG_LEVEL >= LOG_LEVEL_INF char hr_addr[NET_IPV4_ADDR_LEN]; #endif - struct in_addr addr; + struct in_addr addr, netmask; if (sizeof(CONFIG_NET_CONFIG_MY_IPV4_ADDR) == 1) { /* Empty address, skip setting ANY address in this case */ @@ -177,11 +177,11 @@ static void setup_ipv4(struct net_if *iface) if (sizeof(CONFIG_NET_CONFIG_MY_IPV4_NETMASK) > 1) { /* If not empty */ if (net_addr_pton(AF_INET, CONFIG_NET_CONFIG_MY_IPV4_NETMASK, - &addr)) { + &netmask)) { NET_ERR("Invalid netmask: %s", CONFIG_NET_CONFIG_MY_IPV4_NETMASK); } else { - net_if_ipv4_set_netmask(iface, &addr); + net_if_ipv4_set_netmask_by_addr(iface, &addr, &netmask); } } diff --git a/subsys/net/lib/dhcpv4/dhcpv4.c b/subsys/net/lib/dhcpv4/dhcpv4.c index e916d3f86c6..bfcd7c5f4ce 100644 --- a/subsys/net/lib/dhcpv4/dhcpv4.c +++ b/subsys/net/lib/dhcpv4/dhcpv4.c @@ -823,7 +823,9 @@ static bool dhcpv4_parse_options(struct net_pkt *pkt, return false; } - net_if_ipv4_set_netmask(iface, &netmask); + net_if_ipv4_set_netmask_by_addr(iface, + &iface->config.dhcpv4.requested_ip, + &netmask); NET_DBG("options_subnet_mask %s", net_sprint_ipv4_addr(&netmask)); break; diff --git a/subsys/net/lib/dhcpv4/dhcpv4_server.c b/subsys/net/lib/dhcpv4/dhcpv4_server.c index 4b232323a78..49ffe012834 100644 --- a/subsys/net/lib/dhcpv4/dhcpv4_server.c +++ b/subsys/net/lib/dhcpv4/dhcpv4_server.c @@ -1466,7 +1466,7 @@ int net_dhcpv4_server_start(struct net_if *iface, struct in_addr *base_addr) return -EINVAL; } - netmask = net_if_ipv4_get_netmask(iface); + netmask = net_if_ipv4_get_netmask_by_addr(iface, server_addr); if (net_ipv4_is_addr_unspecified(&netmask)) { LOG_ERR("Failed to obtain subnet mask."); return -EINVAL; diff --git a/subsys/net/lib/shell/iface.c b/subsys/net/lib/shell/iface.c index fb0ed4e00fd..b238846ba19 100644 --- a/subsys/net/lib/shell/iface.c +++ b/subsys/net/lib/shell/iface.c @@ -437,14 +437,16 @@ static void iface_cb(struct net_if *iface, void *user_data) PR("IPv4 unicast addresses (max %d):\n", NET_IF_MAX_IPV4_ADDR); for (i = 0; ipv4 && i < NET_IF_MAX_IPV4_ADDR; i++) { - unicast = &ipv4->unicast[i]; + unicast = &ipv4->unicast[i].ipv4; if (!unicast->is_used) { continue; } - PR("\t%s %s %s%s\n", + PR("\t%s/%s %s %s%s\n", net_sprint_ipv4_addr(&unicast->address.in_addr), + net_sprint_ipv4_addr(&ipv4->unicast[i].netmask), + addrtype2str(unicast->addr_type), addrstate2str(unicast->addr_state), unicast->is_infinite ? " infinite" : ""); @@ -480,8 +482,6 @@ static void iface_cb(struct net_if *iface, void *user_data) if (ipv4) { PR("IPv4 gateway : %s\n", net_sprint_ipv4_addr(&ipv4->gw)); - PR("IPv4 netmask : %s\n", - net_sprint_ipv4_addr(&ipv4->netmask)); } #endif /* CONFIG_NET_IPV4 */ diff --git a/subsys/net/lib/shell/ipv4.c b/subsys/net/lib/shell/ipv4.c index b23b691ed69..f5c6ea71734 100644 --- a/subsys/net/lib/shell/ipv4.c +++ b/subsys/net/lib/shell/ipv4.c @@ -36,18 +36,18 @@ static void ip_address_lifetime_cb(struct net_if *iface, void *user_data) PR("Type \tState \tLifetime (sec)\tAddress\n"); for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (!ipv4->unicast[i].is_used || - ipv4->unicast[i].address.family != AF_INET) { + if (!ipv4->unicast[i].ipv4.is_used || + ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; } PR("%s \t%s \t%12s/%12s\n", - addrtype2str(ipv4->unicast[i].addr_type), - addrstate2str(ipv4->unicast[i].addr_state), + addrtype2str(ipv4->unicast[i].ipv4.addr_type), + addrstate2str(ipv4->unicast[i].ipv4.addr_state), net_sprint_ipv4_addr( - &ipv4->unicast[i].address.in_addr), + &ipv4->unicast[i].ipv4.address.in_addr), net_sprint_ipv4_addr( - &ipv4->netmask)); + &ipv4->unicast[i].netmask)); } } #endif /* CONFIG_NET_NATIVE_IPV4 */ @@ -126,6 +126,7 @@ static int cmd_net_ip_add(const struct shell *sh, size_t argc, char *argv[]) } } else { struct net_if_addr *ifaddr; + struct in_addr netmask; if (argc < 4) { PR_ERROR("Netmask is missing.\n"); @@ -139,12 +140,12 @@ static int cmd_net_ip_add(const struct shell *sh, size_t argc, char *argv[]) return -ENOMEM; } - if (net_addr_pton(AF_INET, argv[3], &addr)) { + if (net_addr_pton(AF_INET, argv[3], &netmask)) { PR_ERROR("Invalid netmask: %s", argv[3]); return -EINVAL; } - net_if_ipv4_set_netmask(iface, &addr); + net_if_ipv4_set_netmask_by_addr(iface, &addr, &netmask); } #else /* CONFIG_NET_NATIVE_IPV4 */ diff --git a/subsys/net/lib/shell/tcp.c b/subsys/net/lib/shell/tcp.c index e2839af36ba..300f0f3fa52 100644 --- a/subsys/net/lib/shell/tcp.c +++ b/subsys/net/lib/shell/tcp.c @@ -51,7 +51,7 @@ static void get_my_ipv4_addr(struct net_if *iface, #if defined(CONFIG_NET_NATIVE_IPV4) /* Just take the first IPv4 address of an interface. */ memcpy(&net_sin(myaddr)->sin_addr, - &iface->config.ip.ipv4->unicast[0].address.in_addr, + &iface->config.ip.ipv4->unicast[0].ipv4.address.in_addr, sizeof(struct in_addr)); net_sin(myaddr)->sin_port = 0U; /* let the IP stack to select */ From 1e85823fa6aec4eb6757fe62c85e1f005d114f64 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 1 Feb 2024 15:38:34 +0200 Subject: [PATCH 0037/2402] tests: net: ipv4: Fix tests to support new netmask handling Make sure that the tests work properly when each IPv4 address in the network interface gets its own netmask. Signed-off-by: Jukka Rissanen --- tests/net/arp/src/main.c | 11 ++++++----- tests/net/checksum_offload/src/main.c | 4 ++-- tests/net/dhcpv4/server/src/main.c | 2 +- tests/net/iface/src/main.c | 4 ++-- tests/net/ip-addr/src/main.c | 11 +++++++---- tests/net/shell/src/main.c | 8 ++++---- tests/net/udp/src/main.c | 8 ++++---- tests/net/virtual/src/main.c | 12 ++++++++---- 8 files changed, 34 insertions(+), 26 deletions(-) diff --git a/tests/net/arp/src/main.c b/tests/net/arp/src/main.c index a196599214f..9a94c488215 100644 --- a/tests/net/arp/src/main.c +++ b/tests/net/arp/src/main.c @@ -154,13 +154,13 @@ static inline struct in_addr *if_get_addr(struct net_if *iface) int i; for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (iface->config.ip.ipv4->unicast[i].is_used && - iface->config.ip.ipv4->unicast[i].address.family == + if (iface->config.ip.ipv4->unicast[i].ipv4.is_used && + iface->config.ip.ipv4->unicast[i].ipv4.address.family == AF_INET && - iface->config.ip.ipv4->unicast[i].addr_state == + iface->config.ip.ipv4->unicast[i].ipv4.addr_state == NET_ADDR_PREFERRED) { return - &iface->config.ip.ipv4->unicast[i].address.in_addr; + &iface->config.ip.ipv4->unicast[i].ipv4.address.in_addr; } } @@ -347,7 +347,6 @@ ZTEST(arp_fn_tests, test_arp) iface = net_if_lookup_by_dev(DEVICE_GET(net_arp_test)); net_if_ipv4_set_gw(iface, &gw); - net_if_ipv4_set_netmask(iface, &netmask); /* Unicast test */ ifaddr = net_if_ipv4_addr_add(iface, @@ -357,6 +356,8 @@ ZTEST(arp_fn_tests, test_arp) zassert_not_null(ifaddr, "Cannot add address"); ifaddr->addr_state = NET_ADDR_PREFERRED; + net_if_ipv4_set_netmask_by_addr(iface, &src, &netmask); + len = strlen(app_data); /* Application data for testing */ diff --git a/tests/net/checksum_offload/src/main.c b/tests/net/checksum_offload/src/main.c index e9c59695602..da65d69f4f9 100644 --- a/tests/net/checksum_offload/src/main.c +++ b/tests/net/checksum_offload/src/main.c @@ -578,7 +578,7 @@ static void test_address_setup(void) NET_ADDR_MANUAL, 0); zassert_not_null(ifaddr, "Cannot add IPv4 address"); - net_if_ipv4_set_netmask(iface1, &netmask); + net_if_ipv4_set_netmask_by_addr(iface1, &in4addr_my, &netmask); ifaddr = net_if_ipv6_addr_add(iface2, &my_addr2, NET_ADDR_MANUAL, 0); @@ -594,7 +594,7 @@ static void test_address_setup(void) NET_ADDR_MANUAL, 0); zassert_not_null(ifaddr, "Cannot add IPv4 address"); - net_if_ipv4_set_netmask(iface2, &netmask); + net_if_ipv4_set_netmask_by_addr(iface2, &in4addr_my2, &netmask); net_if_up(iface1); net_if_up(iface2); diff --git a/tests/net/dhcpv4/server/src/main.c b/tests/net/dhcpv4/server/src/main.c index 0baff8c2738..9d1eb962f41 100644 --- a/tests/net/dhcpv4/server/src/main.c +++ b/tests/net/dhcpv4/server/src/main.c @@ -67,7 +67,7 @@ static void server_iface_init(struct net_if *iface) test_ctx.iface = iface; (void)net_if_ipv4_addr_add(iface, &server_addr, NET_ADDR_MANUAL, 0); - (void)net_if_ipv4_set_netmask(iface, &netmask); + (void)net_if_ipv4_set_netmask_by_addr(iface, &server_addr, &netmask); } static void send_icmp_echo_reply(struct net_pkt *pkt, diff --git a/tests/net/iface/src/main.c b/tests/net/iface/src/main.c index 95f9d00a8d4..d5cada6fc46 100644 --- a/tests/net/iface/src/main.c +++ b/tests/net/iface/src/main.c @@ -41,7 +41,7 @@ LOG_MODULE_REGISTER(net_test, NET_LOG_LEVEL); /* Interface 1 addresses */ static struct in6_addr my_addr1 = { { { 0x20, 0x01, 0x0d, 0xb8, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x1 } } }; -static struct in_addr my_ipv4_addr1 = { { { 192, 0, 2, 1 } } }; +static ZTEST_BMEM struct in_addr my_ipv4_addr1 = { { { 192, 0, 2, 1 } } }; /* Interface 2 addresses */ static struct in6_addr my_addr2 = { { { 0x20, 0x01, 0x0d, 0xb8, 2, 0, 0, 0, @@ -1076,7 +1076,7 @@ static void netmask_addr_add(void *p1, void *p2, void *p3) struct in_addr my_netmask = { { { 255, 255, 255, 0 } } }; bool ret; - ret = net_if_ipv4_set_netmask_by_index(1, &my_netmask); + ret = net_if_ipv4_set_netmask_by_addr_by_index(1, &my_ipv4_addr1, &my_netmask); zassert_true(ret, "Cannot add IPv4 netmask"); } diff --git a/tests/net/ip-addr/src/main.c b/tests/net/ip-addr/src/main.c index 81f8f2ba8fb..30ef20cd6c2 100644 --- a/tests/net/ip-addr/src/main.c +++ b/tests/net/ip-addr/src/main.c @@ -404,12 +404,16 @@ ZTEST(ip_addr_fn, test_ipv4_addresses) zassert_true(net_ipv4_is_my_addr(&addr4), "My IPv4 address check failed"); + net_if_ipv4_set_netmask_by_addr(default_iface, &addr4, &netmask); + ifaddr1 = net_if_ipv4_addr_add(default_iface, &lladdr4, NET_ADDR_MANUAL, 0); zassert_not_null(ifaddr1, "IPv4 interface address add failed"); + net_if_ipv4_set_netmask_by_addr(default_iface, &lladdr4, &netmask2); + zassert_true(net_ipv4_is_my_addr(&lladdr4), "My IPv4 address check failed"); @@ -471,10 +475,9 @@ ZTEST(ip_addr_fn, test_ipv4_addresses) iface = default_iface; net_if_ipv4_set_gw(iface, &gw); - net_if_ipv4_set_netmask(iface, &netmask); zassert_false(net_ipv4_addr_mask_cmp(iface, &fail_addr), - "IPv4 wrong match failed"); + "IPv4 wrong match failed"); zassert_true(net_ipv4_addr_mask_cmp(iface, &match_addr), "IPv4 match failed"); @@ -541,11 +544,11 @@ ZTEST(ip_addr_fn, test_ipv4_addresses) ret = net_ipv4_is_addr_bcast(iface, &bcast_addr5); zassert_true(ret, "IPv4 address 5 is not broadcast address"); - net_if_ipv4_set_netmask(iface, &netmask2); - ret = net_ipv4_is_addr_bcast(iface, &bcast_addr2); zassert_false(ret, "IPv4 address 2 is broadcast address"); + net_if_ipv4_set_netmask_by_addr(iface, &addr4, &netmask2); + ret = net_ipv4_is_addr_bcast(iface, &bcast_addr3); zassert_true(ret, "IPv4 address 3 is not broadcast address"); } diff --git a/tests/net/shell/src/main.c b/tests/net/shell/src/main.c index 528958698f8..af61dfd750f 100644 --- a/tests/net/shell/src/main.c +++ b/tests/net/shell/src/main.c @@ -112,13 +112,13 @@ static inline struct in_addr *if_get_addr(struct net_if *iface) int i; for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (iface->config.ip.ipv4->unicast[i].is_used && - iface->config.ip.ipv4->unicast[i].address.family == + if (iface->config.ip.ipv4->unicast[i].ipv4.is_used && + iface->config.ip.ipv4->unicast[i].ipv4.address.family == AF_INET && - iface->config.ip.ipv4->unicast[i].addr_state == + iface->config.ip.ipv4->unicast[i].ipv4.addr_state == NET_ADDR_PREFERRED) { return - &iface->config.ip.ipv4->unicast[i].address.in_addr; + &iface->config.ip.ipv4->unicast[i].ipv4.address.in_addr; } } diff --git a/tests/net/udp/src/main.c b/tests/net/udp/src/main.c index 0de851fffff..452db57ebb0 100644 --- a/tests/net/udp/src/main.c +++ b/tests/net/udp/src/main.c @@ -114,13 +114,13 @@ static inline struct in_addr *if_get_addr(struct net_if *iface) int i; for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (iface->config.ip.ipv4->unicast[i].is_used && - iface->config.ip.ipv4->unicast[i].address.family == + if (iface->config.ip.ipv4->unicast[i].ipv4.is_used && + iface->config.ip.ipv4->unicast[i].ipv4.address.family == AF_INET && - iface->config.ip.ipv4->unicast[i].addr_state == + iface->config.ip.ipv4->unicast[i].ipv4.addr_state == NET_ADDR_PREFERRED) { return - &iface->config.ip.ipv4->unicast[i].address.in_addr; + &iface->config.ip.ipv4->unicast[i].ipv4.address.in_addr; } } diff --git a/tests/net/virtual/src/main.c b/tests/net/virtual/src/main.c index b124f14a5ba..003bebd33e0 100644 --- a/tests/net/virtual/src/main.c +++ b/tests/net/virtual/src/main.c @@ -379,6 +379,7 @@ static void test_virtual_setup(void) static void test_address_setup(void) { + struct in_addr netmask = {{{ 255, 255, 255, 0 }}}; struct net_if_addr *ifaddr; struct net_if *eth, *virt, *dummy1, *dummy2; int ret; @@ -412,6 +413,8 @@ static void test_address_setup(void) ifaddr->addr_state = NET_ADDR_PREFERRED; + net_if_ipv4_set_netmask_by_addr(eth, &my_addr, &netmask); + ifaddr = net_if_ipv6_addr_add(eth, &ll_addr, NET_ADDR_MANUAL, 0); if (!ifaddr) { DBG("Cannot add IPv6 address %s\n", @@ -460,6 +463,11 @@ static void test_address_setup(void) } net_sin(&virtual_addr)->sin_port = htons(4242); + + net_if_ipv4_set_netmask_by_addr(virt, + &net_sin(&virtual_addr)->sin_addr, + &netmask); + } else if (virtual_addr.sa_family == AF_INET6) { ifaddr = net_if_ipv6_addr_add(virt, &net_sin6(&virtual_addr)->sin6_addr, @@ -790,7 +798,6 @@ ZTEST(net_virtual, test_virtual_08_send_data_to_tunnel) struct net_if *iface = virtual_interfaces[0]; struct net_if *attached; struct sockaddr dst_addr, src_addr; - struct in_addr netmask = {{{ 255, 255, 255, 0 }}}; void *addr; int addrlen; int ret; @@ -818,9 +825,6 @@ ZTEST(net_virtual, test_virtual_08_send_data_to_tunnel) zassert_true(false, "Invalid family (%d)", params.family); } - net_if_ipv4_set_netmask(iface, &netmask); - net_if_ipv4_set_netmask(eth_interfaces[0], &netmask); - ret = net_mgmt(NET_REQUEST_VIRTUAL_INTERFACE_SET_PEER_ADDRESS, iface, ¶ms, sizeof(params)); zassert_equal(ret, 0, "Cannot set interface %d peer to %s (%d)", From 58b2a3dfd4464f9d924e9fe445db4f42828077e1 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 1 Feb 2024 15:44:23 +0200 Subject: [PATCH 0038/2402] net: ipv4: Deprecate the old netmask set/get routines This commit deprecates these legacy netmask get/set routines net_if_ipv4_set_netmask() net_if_ipv4_set_netmask_by_index() net_if_ipv4_get_netmask() as they do not work well if there are multiple IPv4 address assigned to the network interface. User should use these functions instead net_if_ipv4_set_netmask_by_addr() net_if_ipv4_set_netmask_by_addr_by_index() net_if_ipv4_get_netmask_by_addr() as they make sure the netmask it bound to correct IPv4 address. Signed-off-by: Jukka Rissanen --- include/zephyr/net/net_if.h | 16 +++++++++++----- subsys/net/ip/net_if.c | 12 +++++++++--- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/include/zephyr/net/net_if.h b/include/zephyr/net/net_if.h index 387e742d0b9..fabd2cc5f89 100644 --- a/include/zephyr/net/net_if.h +++ b/include/zephyr/net/net_if.h @@ -2365,31 +2365,37 @@ struct in_addr net_if_ipv4_get_netmask_by_addr(struct net_if *iface, /** * @brief Get IPv4 netmask of an interface. * + * @deprecated Use net_if_ipv4_get_netmask_by_addr() instead. + * * @param iface Interface to use. * * @return The netmask set on the interface, unspecified address if not found. */ -struct in_addr net_if_ipv4_get_netmask(struct net_if *iface); +__deprecated struct in_addr net_if_ipv4_get_netmask(struct net_if *iface); /** * @brief Set IPv4 netmask for an interface. * + * @deprecated Use net_if_ipv4_set_netmask_by_addr() instead. + * * @param iface Interface to use. * @param netmask IPv4 netmask */ -void net_if_ipv4_set_netmask(struct net_if *iface, - const struct in_addr *netmask); +__deprecated void net_if_ipv4_set_netmask(struct net_if *iface, + const struct in_addr *netmask); /** * @brief Set IPv4 netmask for an interface index. * + * @deprecated Use net_if_ipv4_set_netmask_by_addr() instead. + * * @param index Network interface index * @param netmask IPv4 netmask * * @return True if netmask was added, false otherwise. */ -__syscall bool net_if_ipv4_set_netmask_by_index(int index, - const struct in_addr *netmask); +__deprecated __syscall bool net_if_ipv4_set_netmask_by_index(int index, + const struct in_addr *netmask); /** * @brief Set IPv4 netmask for an interface index for a given address. diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 7a6cfc34821..8248296c991 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -3832,8 +3832,8 @@ struct in_addr net_if_ipv4_get_netmask(struct net_if *iface) * in this case and set the first one found. Please use * net_if_ipv4_set_netmask_by_addr() instead. */ -void net_if_ipv4_set_netmask(struct net_if *iface, - const struct in_addr *netmask) +static void net_if_ipv4_set_netmask_deprecated(struct net_if *iface, + const struct in_addr *netmask) { struct net_if_ipv4 *ipv4; @@ -3862,6 +3862,12 @@ void net_if_ipv4_set_netmask(struct net_if *iface, net_if_unlock(iface); } +void net_if_ipv4_set_netmask(struct net_if *iface, + const struct in_addr *netmask) +{ + net_if_ipv4_set_netmask_deprecated(iface, netmask); +} + bool z_impl_net_if_ipv4_set_netmask_by_index(int index, const struct in_addr *netmask) { @@ -3872,7 +3878,7 @@ bool z_impl_net_if_ipv4_set_netmask_by_index(int index, return false; } - net_if_ipv4_set_netmask(iface, netmask); + net_if_ipv4_set_netmask_deprecated(iface, netmask); return true; } From 8860a81cfeeae9db20e518a1960123ac51938f8f Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 2 Feb 2024 10:04:42 +0200 Subject: [PATCH 0039/2402] drivers: Change drivers to support new IPv4 netmask setting API Make sure that the drivers use the new IPv4 netmask setting API. Signed-off-by: Jukka Rissanen --- drivers/modem/hl7800.c | 4 +++- drivers/net/loopback.c | 2 +- drivers/wifi/esp_at/esp.c | 4 ++-- drivers/wifi/eswifi/eswifi_core.c | 4 ++-- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/modem/hl7800.c b/drivers/modem/hl7800.c index a08e02104d8..47c11f865f0 100644 --- a/drivers/modem/hl7800.c +++ b/drivers/modem/hl7800.c @@ -2173,7 +2173,9 @@ static bool on_cmd_atcmdinfo_ipaddr(struct net_buf **buf, uint16_t len) LOG_ERR("Cannot set iface IPv4 addr"); } - net_if_ipv4_set_netmask(iface_ctx.iface, &iface_ctx.subnet); + net_if_ipv4_set_netmask_by_addr(iface_ctx.iface, + &new_ipv4_addr, + &iface_ctx.subnet); net_if_ipv4_set_gw(iface_ctx.iface, &iface_ctx.gateway); #endif /* store the new IP addr */ diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index 2695875ae27..0f07b0af65e 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -50,7 +50,7 @@ static void loopback_init(struct net_if *iface) LOG_ERR("Failed to register IPv4 loopback address"); } - net_if_ipv4_set_netmask(iface, &netmask); + net_if_ipv4_set_netmask_by_addr(iface, &ipv4_loopback, &netmask); } if (IS_ENABLED(CONFIG_NET_IPV6)) { diff --git a/drivers/wifi/esp_at/esp.c b/drivers/wifi/esp_at/esp.c index e0b44200061..e2c84e4eb71 100644 --- a/drivers/wifi/esp_at/esp.c +++ b/drivers/wifi/esp_at/esp.c @@ -640,13 +640,13 @@ static void esp_ip_addr_work(struct k_work *work) #if defined(CONFIG_NET_NATIVE_IPV4) /* update interface addresses */ - net_if_ipv4_set_gw(dev->net_iface, &dev->gw); - net_if_ipv4_set_netmask(dev->net_iface, &dev->nm); #if defined(CONFIG_WIFI_ESP_AT_IP_STATIC) net_if_ipv4_addr_add(dev->net_iface, &dev->ip, NET_ADDR_MANUAL, 0); #else net_if_ipv4_addr_add(dev->net_iface, &dev->ip, NET_ADDR_DHCP, 0); #endif + net_if_ipv4_set_gw(dev->net_iface, &dev->gw); + net_if_ipv4_set_netmask_by_addr(dev->net_iface, &dev->ip, &dev->nm); #endif if (IS_ENABLED(CONFIG_WIFI_ESP_AT_DNS_USE)) { diff --git a/drivers/wifi/eswifi/eswifi_core.c b/drivers/wifi/eswifi/eswifi_core.c index 82f24982d1a..2ee8b597d1b 100644 --- a/drivers/wifi/eswifi/eswifi_core.c +++ b/drivers/wifi/eswifi/eswifi_core.c @@ -677,8 +677,8 @@ static int eswifi_mgmt_ap_enable(const struct device *dev, /* Set IP Address */ for (i = 0; ipv4 && i < NET_IF_MAX_IPV4_ADDR; i++) { - if (ipv4->unicast[i].is_used) { - unicast = &ipv4->unicast[i]; + if (ipv4->unicast[i].ipv4.is_used) { + unicast = &ipv4->unicast[i].ipv4; break; } } From 3c0fe6b04b9d67c6a90640d9e4292135cc3704c2 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 2 Feb 2024 10:13:19 +0200 Subject: [PATCH 0040/2402] samples: net: Change samples to support new IPv4 netmask setting API Make sure that the samples use the new IPv4 netmask setting API. Signed-off-by: Jukka Rissanen --- samples/boards/nxp_s32/netc/src/main.c | 6 ++++-- samples/net/dhcpv4_client/src/main.c | 6 +++--- samples/net/dns_resolve/src/main.c | 8 +++++--- samples/net/ipv4_autoconf/src/main.c | 8 ++++++-- samples/net/mdns_responder/src/vlan.c | 6 ++++-- samples/net/sockets/echo_server/src/vlan.c | 6 ++++-- samples/net/virtual/src/main.c | 6 ++++-- samples/subsys/mgmt/hawkbit/src/dhcp.c | 2 +- 8 files changed, 31 insertions(+), 17 deletions(-) diff --git a/samples/boards/nxp_s32/netc/src/main.c b/samples/boards/nxp_s32/netc/src/main.c index 3b3848a1ef1..8399a7dd9b5 100644 --- a/samples/boards/nxp_s32/netc/src/main.c +++ b/samples/boards/nxp_s32/netc/src/main.c @@ -54,12 +54,14 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, LOG_INF("IPv4 address: %s", ipv4_addr); if (netmask && netmask[0]) { - if (net_addr_pton(AF_INET, netmask, &addr4)) { + struct in_addr nm; + + if (net_addr_pton(AF_INET, netmask, &nm)) { LOG_ERR("Invalid netmask: %s", netmask); return -EINVAL; } - net_if_ipv4_set_netmask(iface, &addr4); + net_if_ipv4_set_netmask_by_addr(iface, &addr4, &nm); } } diff --git a/samples/net/dhcpv4_client/src/main.c b/samples/net/dhcpv4_client/src/main.c index 68d6abc2b91..00d48949d73 100644 --- a/samples/net/dhcpv4_client/src/main.c +++ b/samples/net/dhcpv4_client/src/main.c @@ -50,18 +50,18 @@ static void handler(struct net_mgmt_event_callback *cb, for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { char buf[NET_IPV4_ADDR_LEN]; - if (iface->config.ip.ipv4->unicast[i].addr_type != + if (iface->config.ip.ipv4->unicast[i].ipv4.addr_type != NET_ADDR_DHCP) { continue; } LOG_INF(" Address[%d]: %s", net_if_get_by_iface(iface), net_addr_ntop(AF_INET, - &iface->config.ip.ipv4->unicast[i].address.in_addr, + &iface->config.ip.ipv4->unicast[i].ipv4.address.in_addr, buf, sizeof(buf))); LOG_INF(" Subnet[%d]: %s", net_if_get_by_iface(iface), net_addr_ntop(AF_INET, - &iface->config.ip.ipv4->netmask, + &iface->config.ip.ipv4->unicast[i].netmask, buf, sizeof(buf))); LOG_INF(" Router[%d]: %s", net_if_get_by_iface(iface), net_addr_ntop(AF_INET, diff --git a/samples/net/dns_resolve/src/main.c b/samples/net/dns_resolve/src/main.c index 0aa5f2a9886..5eec113ead3 100644 --- a/samples/net/dns_resolve/src/main.c +++ b/samples/net/dns_resolve/src/main.c @@ -168,6 +168,7 @@ static void print_dhcpv4_addr(struct net_if *iface, struct net_if_addr *if_addr, { bool *found = (bool *)user_data; char hr_addr[NET_IPV4_ADDR_LEN]; + struct in_addr netmask; if (*found) { return; @@ -181,10 +182,11 @@ static void print_dhcpv4_addr(struct net_if *iface, struct net_if_addr *if_addr, net_addr_ntop(AF_INET, &if_addr->address.in_addr, hr_addr, NET_IPV4_ADDR_LEN)); LOG_INF("Lease time: %u seconds", iface->config.dhcpv4.lease_time); + + netmask = net_if_ipv4_get_netmask_by_addr(iface, + &if_addr->address.in_addr); LOG_INF("Subnet: %s", - net_addr_ntop(AF_INET, - &iface->config.ip.ipv4->netmask, - hr_addr, NET_IPV4_ADDR_LEN)); + net_addr_ntop(AF_INET, &netmask, hr_addr, NET_IPV4_ADDR_LEN)); LOG_INF("Router: %s", net_addr_ntop(AF_INET, &iface->config.ip.ipv4->gw, diff --git a/samples/net/ipv4_autoconf/src/main.c b/samples/net/ipv4_autoconf/src/main.c index 865c91659dd..b9f9c00379d 100644 --- a/samples/net/ipv4_autoconf/src/main.c +++ b/samples/net/ipv4_autoconf/src/main.c @@ -41,13 +41,17 @@ static void handler(struct net_mgmt_event_callback *cb, for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { char buf[NET_IPV4_ADDR_LEN]; - if (cfg->ip.ipv4->unicast[i].addr_type != NET_ADDR_AUTOCONF) { + if (cfg->ip.ipv4->unicast[i].ipv4.addr_type != NET_ADDR_AUTOCONF) { continue; } LOG_INF("Your address: %s", net_addr_ntop(AF_INET, - &cfg->ip.ipv4->unicast[i].address.in_addr, + &cfg->ip.ipv4->unicast[i].ipv4.address.in_addr, + buf, sizeof(buf))); + LOG_INF("Your netmask: %s", + net_addr_ntop(AF_INET, + &cfg->ip.ipv4->unicast[i].netmask, buf, sizeof(buf))); } } diff --git a/samples/net/mdns_responder/src/vlan.c b/samples/net/mdns_responder/src/vlan.c index 534662c3c64..7458343eaee 100644 --- a/samples/net/mdns_responder/src/vlan.c +++ b/samples/net/mdns_responder/src/vlan.c @@ -86,12 +86,14 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, } if (netmask && netmask[0]) { - if (net_addr_pton(AF_INET, netmask, &addr4)) { + struct in_addr nm; + + if (net_addr_pton(AF_INET, netmask, &nm)) { LOG_ERR("Invalid netmask: %s", ipv4_addr); return -EINVAL; } - net_if_ipv4_set_netmask(iface, &addr4); + net_if_ipv4_set_netmask_by_addr(iface, &addr4, &nm); } } diff --git a/samples/net/sockets/echo_server/src/vlan.c b/samples/net/sockets/echo_server/src/vlan.c index 4f2a52034e2..2115a5f3ae5 100644 --- a/samples/net/sockets/echo_server/src/vlan.c +++ b/samples/net/sockets/echo_server/src/vlan.c @@ -86,12 +86,14 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, } if (netmask && netmask[0]) { - if (net_addr_pton(AF_INET, netmask, &addr4)) { + struct in_addr nm; + + if (net_addr_pton(AF_INET, netmask, &nm)) { LOG_ERR("Invalid netmask: %s", ipv4_addr); return -EINVAL; } - net_if_ipv4_set_netmask(iface, &addr4); + net_if_ipv4_set_netmask_by_addr(iface, &addr4, &nm); } } diff --git a/samples/net/virtual/src/main.c b/samples/net/virtual/src/main.c index 0c086e0726c..bbc803cd4a3 100644 --- a/samples/net/virtual/src/main.c +++ b/samples/net/virtual/src/main.c @@ -302,12 +302,14 @@ static int setup_iface(struct net_if *iface, } if (netmask) { - if (net_addr_pton(AF_INET, netmask, &addr4)) { + struct in_addr nm; + + if (net_addr_pton(AF_INET, netmask, &nm)) { LOG_ERR("Invalid netmask: %s", netmask); return -EINVAL; } - net_if_ipv4_set_netmask(iface, &addr4); + net_if_ipv4_set_netmask_by_addr(iface, &addr4, &nm); } if (!peer4addr || *peer4addr == '\0') { diff --git a/samples/subsys/mgmt/hawkbit/src/dhcp.c b/samples/subsys/mgmt/hawkbit/src/dhcp.c index 3f72a03f3f3..ec433dae7e1 100644 --- a/samples/subsys/mgmt/hawkbit/src/dhcp.c +++ b/samples/subsys/mgmt/hawkbit/src/dhcp.c @@ -30,7 +30,7 @@ static void handler(struct net_mgmt_event_callback *cb, } for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (iface->config.ip.ipv4->unicast[i].addr_type != + if (iface->config.ip.ipv4->unicast[i].ipv4.addr_type != NET_ADDR_DHCP) { continue; } From 6e7d97dc382d3f387d10fc9751b95cb69ee76e17 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 2 Feb 2024 15:26:20 +0200 Subject: [PATCH 0041/2402] net: if: Convert array loops to use ARRAY_FOR_EACH macro Convert various array loops in the net_if.c to use the ARRAY_FOR_EACH() macro. This makes the code more robust as we do not need to keep track of the separate define that tells the array size. Signed-off-by: Jukka Rissanen --- subsys/net/ip/net_if.c | 126 ++++++++++++++++------------------------- 1 file changed, 49 insertions(+), 77 deletions(-) diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 8248296c991..70b21d6b866 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -1274,7 +1274,7 @@ void net_if_start_dad(struct net_if *iface) struct net_if_addr *ifaddr; struct net_if_ipv6 *ipv6; struct in6_addr addr = { }; - int ret, i; + int ret; net_if_lock(iface); @@ -1304,7 +1304,7 @@ void net_if_start_dad(struct net_if *iface) /* Start DAD for all the addresses that were added earlier when * the interface was down. */ - for (i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { if (!ipv6->unicast[i].is_used || ipv6->unicast[i].address.family != AF_INET6 || &ipv6->unicast[i] == ifaddr || @@ -1522,7 +1522,6 @@ struct net_if_addr *net_if_ipv6_addr_lookup(const struct in6_addr *addr, STRUCT_SECTION_FOREACH(net_if, iface) { struct net_if_ipv6 *ipv6; - int i; net_if_lock(iface); @@ -1532,7 +1531,7 @@ struct net_if_addr *net_if_ipv6_addr_lookup(const struct in6_addr *addr, continue; } - for (i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { if (!ipv6->unicast[i].is_used || ipv6->unicast[i].address.family != AF_INET6) { continue; @@ -1565,7 +1564,6 @@ struct net_if_addr *net_if_ipv6_addr_lookup_by_iface(struct net_if *iface, { struct net_if_addr *ifaddr = NULL; struct net_if_ipv6 *ipv6; - int i; net_if_lock(iface); @@ -1574,7 +1572,7 @@ struct net_if_addr *net_if_ipv6_addr_lookup_by_iface(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { if (!ipv6->unicast[i].is_used || ipv6->unicast[i].address.family != AF_INET6) { continue; @@ -1709,9 +1707,8 @@ static struct net_if_addr *ipv6_addr_find(struct net_if *iface, struct in6_addr *addr) { struct net_if_ipv6 *ipv6 = iface->config.ip.ipv6; - int i; - for (i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { if (!ipv6->unicast[i].is_used) { continue; } @@ -1758,7 +1755,6 @@ struct net_if_addr *net_if_ipv6_addr_add(struct net_if *iface, { struct net_if_addr *ifaddr = NULL; struct net_if_ipv6 *ipv6; - int i; net_if_lock(iface); @@ -1771,7 +1767,7 @@ struct net_if_addr *net_if_ipv6_addr_add(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { if (ipv6->unicast[i].is_used) { continue; } @@ -1779,7 +1775,7 @@ struct net_if_addr *net_if_ipv6_addr_add(struct net_if *iface, net_if_addr_init(&ipv6->unicast[i], addr, addr_type, vlifetime); - NET_DBG("[%d] interface %p address %s type %s added", i, + NET_DBG("[%zu] interface %p address %s type %s added", i, iface, net_sprint_ipv6_addr(addr), net_addr_type2str(addr_type)); @@ -1841,7 +1837,7 @@ bool net_if_ipv6_addr_rm(struct net_if *iface, const struct in6_addr *addr) net_ipv6_addr_create_solicited_node(addr, &maddr); - for (int i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { struct in6_addr unicast_maddr; if (!ipv6->unicast[i].is_used) { @@ -2014,7 +2010,7 @@ void net_if_ipv6_addr_foreach(struct net_if *iface, net_if_ip_addr_cb_t cb, goto out; } - for (int i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { struct net_if_addr *if_addr = &ipv6->unicast[i]; if (!if_addr->is_used) { @@ -2033,7 +2029,6 @@ struct net_if_mcast_addr *net_if_ipv6_maddr_add(struct net_if *iface, { struct net_if_mcast_addr *ifmaddr = NULL; struct net_if_ipv6 *ipv6; - int i; net_if_lock(iface); @@ -2053,7 +2048,7 @@ struct net_if_mcast_addr *net_if_ipv6_maddr_add(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV6_MADDR; i++) { + ARRAY_FOR_EACH(ipv6->mcast, i) { if (ipv6->mcast[i].is_used) { continue; } @@ -2062,7 +2057,7 @@ struct net_if_mcast_addr *net_if_ipv6_maddr_add(struct net_if *iface, ipv6->mcast[i].address.family = AF_INET6; memcpy(&ipv6->mcast[i].address.in6_addr, addr, 16); - NET_DBG("[%d] interface %p address %s added", i, iface, + NET_DBG("[%zu] interface %p address %s added", i, iface, net_sprint_ipv6_addr(addr)); net_mgmt_event_notify_with_info( @@ -2084,7 +2079,6 @@ bool net_if_ipv6_maddr_rm(struct net_if *iface, const struct in6_addr *addr) { bool ret = false; struct net_if_ipv6 *ipv6; - int i; net_if_lock(iface); @@ -2093,7 +2087,7 @@ bool net_if_ipv6_maddr_rm(struct net_if *iface, const struct in6_addr *addr) goto out; } - for (i = 0; i < NET_IF_MAX_IPV6_MADDR; i++) { + ARRAY_FOR_EACH(ipv6->mcast, i) { if (!ipv6->mcast[i].is_used) { continue; } @@ -2105,7 +2099,7 @@ bool net_if_ipv6_maddr_rm(struct net_if *iface, const struct in6_addr *addr) ipv6->mcast[i].is_used = false; - NET_DBG("[%d] interface %p address %s removed", + NET_DBG("[%zu] interface %p address %s removed", i, iface, net_sprint_ipv6_addr(addr)); net_mgmt_event_notify_with_info( @@ -2157,7 +2151,6 @@ struct net_if_mcast_addr *net_if_ipv6_maddr_lookup(const struct in6_addr *maddr, STRUCT_SECTION_FOREACH(net_if, iface) { struct net_if_ipv6 *ipv6; - int i; if (ret && *ret && iface != *ret) { continue; @@ -2171,7 +2164,7 @@ struct net_if_mcast_addr *net_if_ipv6_maddr_lookup(const struct in6_addr *maddr, continue; } - for (i = 0; i < NET_IF_MAX_IPV6_MADDR; i++) { + ARRAY_FOR_EACH(ipv6->mcast, i) { if (!ipv6->mcast[i].is_used || ipv6->mcast[i].address.family != AF_INET6) { continue; @@ -2223,9 +2216,7 @@ static void remove_prefix_addresses(struct net_if *iface, struct in6_addr *addr, uint8_t len) { - int i; - - for (i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { if (!ipv6->unicast[i].is_used || ipv6->unicast[i].address.family != AF_INET6 || ipv6->unicast[i].addr_type != NET_ADDR_AUTOCONF) { @@ -2366,13 +2357,12 @@ static struct net_if_ipv6_prefix *ipv6_prefix_find(struct net_if *iface, uint8_t prefix_len) { struct net_if_ipv6 *ipv6 = iface->config.ip.ipv6; - int i; if (!ipv6) { return NULL; } - for (i = 0; i < NET_IF_MAX_IPV6_PREFIX; i++) { + ARRAY_FOR_EACH(ipv6->prefix, i) { if (!ipv6->prefix[i].is_used) { continue; } @@ -2410,7 +2400,6 @@ struct net_if_ipv6_prefix *net_if_ipv6_prefix_add(struct net_if *iface, { struct net_if_ipv6_prefix *ifprefix = NULL; struct net_if_ipv6 *ipv6; - int i; net_if_lock(iface); @@ -2427,7 +2416,7 @@ struct net_if_ipv6_prefix *net_if_ipv6_prefix_add(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV6_PREFIX; i++) { + ARRAY_FOR_EACH(ipv6->prefix, i) { if (ipv6->prefix[i].is_used) { continue; } @@ -2435,7 +2424,7 @@ struct net_if_ipv6_prefix *net_if_ipv6_prefix_add(struct net_if *iface, net_if_ipv6_prefix_init(iface, &ipv6->prefix[i], prefix, len, lifetime); - NET_DBG("[%d] interface %p prefix %s/%d added", i, iface, + NET_DBG("[%zu] interface %p prefix %s/%d added", i, iface, net_sprint_ipv6_addr(prefix), len); if (IS_ENABLED(CONFIG_NET_MGMT_EVENT_INFO)) { @@ -2467,7 +2456,6 @@ bool net_if_ipv6_prefix_rm(struct net_if *iface, struct in6_addr *addr, { bool ret = false; struct net_if_ipv6 *ipv6; - int i; net_if_lock(iface); @@ -2476,7 +2464,7 @@ bool net_if_ipv6_prefix_rm(struct net_if *iface, struct in6_addr *addr, goto out; } - for (i = 0; i < NET_IF_MAX_IPV6_PREFIX; i++) { + ARRAY_FOR_EACH(ipv6->prefix, i) { if (!ipv6->prefix[i].is_used) { continue; } @@ -2524,7 +2512,6 @@ struct net_if_ipv6_prefix *net_if_ipv6_prefix_get(struct net_if *iface, { struct net_if_ipv6_prefix *prefix = NULL; struct net_if_ipv6 *ipv6; - int i; if (!iface) { iface = net_if_get_default(); @@ -2537,7 +2524,7 @@ struct net_if_ipv6_prefix *net_if_ipv6_prefix_get(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV6_PREFIX; i++) { + ARRAY_FOR_EACH(ipv6->prefix, i) { if (!ipv6->prefix[i].is_used) { continue; } @@ -2563,7 +2550,6 @@ struct net_if_ipv6_prefix *net_if_ipv6_prefix_lookup(struct net_if *iface, { struct net_if_ipv6_prefix *prefix = NULL; struct net_if_ipv6 *ipv6; - int i; net_if_lock(iface); @@ -2572,7 +2558,7 @@ struct net_if_ipv6_prefix *net_if_ipv6_prefix_lookup(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV6_PREFIX; i++) { + ARRAY_FOR_EACH(ipv6->prefix, i) { if (!ipv6->prefix[i].is_used) { continue; } @@ -2596,7 +2582,6 @@ bool net_if_ipv6_addr_onlink(struct net_if **iface, struct in6_addr *addr) STRUCT_SECTION_FOREACH(net_if, tmp) { struct net_if_ipv6 *ipv6; - int i; if (iface && *iface && *iface != tmp) { continue; @@ -2610,7 +2595,7 @@ bool net_if_ipv6_addr_onlink(struct net_if **iface, struct in6_addr *addr) continue; } - for (i = 0; i < NET_IF_MAX_IPV6_PREFIX; i++) { + ARRAY_FOR_EACH(ipv6->prefix, i) { if (ipv6->prefix[i].is_used && net_ipv6_is_prefix(ipv6->prefix[i].prefix.s6_addr, addr->s6_addr, @@ -2794,7 +2779,6 @@ struct in6_addr *net_if_ipv6_get_ll(struct net_if *iface, { struct in6_addr *addr = NULL; struct net_if_ipv6 *ipv6; - int i; net_if_lock(iface); @@ -2803,7 +2787,7 @@ struct in6_addr *net_if_ipv6_get_ll(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { if (!ipv6->unicast[i].is_used || (addr_state != NET_ADDR_ANY_STATE && ipv6->unicast[i].addr_state != addr_state) || @@ -2852,13 +2836,12 @@ static inline struct in6_addr *check_global_addr(struct net_if *iface, enum net_addr_state state) { struct net_if_ipv6 *ipv6 = iface->config.ip.ipv6; - int i; if (!ipv6) { return NULL; } - for (i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { if (!ipv6->unicast[i].is_used || (ipv6->unicast[i].addr_state != state) || ipv6->unicast[i].address.family != AF_INET6) { @@ -2926,7 +2909,6 @@ static struct in6_addr *net_if_ipv6_get_best_match(struct net_if *iface, struct net_if_ipv6 *ipv6; struct in6_addr *src = NULL; uint8_t len; - int i; net_if_lock(iface); @@ -2935,7 +2917,7 @@ static struct in6_addr *net_if_ipv6_get_best_match(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { if (!is_proper_ipv6_address(&ipv6->unicast[i])) { continue; } @@ -3073,8 +3055,6 @@ static void iface_ipv6_start(struct net_if *iface) static void iface_ipv6_init(int if_count) { - int i; - iface_ipv6_dad_init(); iface_ipv6_nd_init(); @@ -3090,7 +3070,7 @@ static void iface_ipv6_init(int if_count) "value."); } - for (i = 0; i < ARRAY_SIZE(ipv6_addresses); i++) { + ARRAY_FOR_EACH(ipv6_addresses, i) { ipv6_addresses[i].ipv6.hop_limit = CONFIG_NET_INITIAL_HOP_LIMIT; ipv6_addresses[i].ipv6.mcast_hop_limit = CONFIG_NET_INITIAL_MCAST_HOP_LIMIT; ipv6_addresses[i].ipv6.base_reachable_time = REACHABLE_TIME; @@ -3139,7 +3119,6 @@ struct in6_addr *net_if_ipv6_get_global_addr(enum net_addr_state state, int net_if_config_ipv4_get(struct net_if *iface, struct net_if_ipv4 **ipv4) { int ret = 0; - int i; net_if_lock(iface); @@ -3158,7 +3137,7 @@ int net_if_config_ipv4_get(struct net_if *iface, struct net_if_ipv4 **ipv4) k_mutex_lock(&lock, K_FOREVER); - for (i = 0; i < ARRAY_SIZE(ipv4_addresses); i++) { + ARRAY_FOR_EACH(ipv4_addresses, i) { if (ipv4_addresses[i].iface) { continue; } @@ -3186,7 +3165,6 @@ int net_if_config_ipv4_get(struct net_if *iface, struct net_if_ipv4 **ipv4) int net_if_config_ipv4_put(struct net_if *iface) { int ret = 0; - int i; net_if_lock(iface); @@ -3202,7 +3180,7 @@ int net_if_config_ipv4_put(struct net_if *iface) k_mutex_lock(&lock, K_FOREVER); - for (i = 0; i < ARRAY_SIZE(ipv4_addresses); i++) { + ARRAY_FOR_EACH(ipv4_addresses, i) { if (ipv4_addresses[i].iface != iface) { continue; } @@ -3352,7 +3330,6 @@ bool net_if_ipv4_addr_mask_cmp(struct net_if *iface, bool ret = false; struct net_if_ipv4 *ipv4; uint32_t subnet; - int i; net_if_lock(iface); @@ -3361,7 +3338,7 @@ bool net_if_ipv4_addr_mask_cmp(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!ipv4->unicast[i].ipv4.is_used || ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; @@ -3398,7 +3375,7 @@ static bool ipv4_is_broadcast_address(struct net_if *iface, goto out; } - for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!ipv4->unicast[i].ipv4.is_used || ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; @@ -3485,7 +3462,6 @@ static struct in_addr *net_if_ipv4_get_best_match(struct net_if *iface, struct net_if_ipv4 *ipv4; struct in_addr *src = NULL; uint8_t len; - int i; net_if_lock(iface); @@ -3494,7 +3470,7 @@ static struct in_addr *net_if_ipv4_get_best_match(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!is_proper_ipv4_address(&ipv4->unicast[i].ipv4)) { continue; } @@ -3517,7 +3493,6 @@ static struct in_addr *if_ipv4_get_addr(struct net_if *iface, { struct in_addr *addr = NULL; struct net_if_ipv4 *ipv4; - int i; if (!iface) { return NULL; @@ -3530,7 +3505,7 @@ static struct in_addr *if_ipv4_get_addr(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!ipv4->unicast[i].ipv4.is_used || (addr_state != NET_ADDR_ANY_STATE && ipv4->unicast[i].ipv4.addr_state != addr_state) || @@ -3646,7 +3621,6 @@ struct net_if_addr *net_if_ipv4_addr_lookup(const struct in_addr *addr, STRUCT_SECTION_FOREACH(net_if, iface) { struct net_if_ipv4 *ipv4; - int i; net_if_lock(iface); @@ -3656,7 +3630,7 @@ struct net_if_addr *net_if_ipv4_addr_lookup(const struct in_addr *addr, continue; } - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!ipv4->unicast[i].ipv4.is_used || ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; @@ -3726,7 +3700,7 @@ struct in_addr net_if_ipv4_get_netmask_by_addr(struct net_if *iface, goto out; } - for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!ipv4->unicast[i].ipv4.is_used || ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; @@ -3767,7 +3741,7 @@ bool net_if_ipv4_set_netmask_by_addr(struct net_if *iface, goto out; } - for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!ipv4->unicast[i].ipv4.is_used || ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; @@ -3811,7 +3785,7 @@ struct in_addr net_if_ipv4_get_netmask(struct net_if *iface) goto out; } - for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!ipv4->unicast[i].ipv4.is_used || ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; @@ -3848,7 +3822,7 @@ static void net_if_ipv4_set_netmask_deprecated(struct net_if *iface, goto out; } - for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!ipv4->unicast[i].ipv4.is_used || ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; @@ -4000,9 +3974,8 @@ static struct net_if_addr *ipv4_addr_find(struct net_if *iface, struct in_addr *addr) { struct net_if_ipv4 *ipv4 = iface->config.ip.ipv4; - int i; - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!ipv4->unicast[i].ipv4.is_used) { continue; } @@ -4023,7 +3996,7 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface, { struct net_if_addr *ifaddr = NULL; struct net_if_ipv4 *ipv4; - int i; + int idx; net_if_lock(iface); @@ -4037,17 +4010,19 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface, goto out; } - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { struct net_if_addr *cur = &ipv4->unicast[i].ipv4; if (addr_type == NET_ADDR_DHCP && cur->addr_type == NET_ADDR_OVERRIDABLE) { ifaddr = cur; + idx = i; break; } if (!ipv4->unicast[i].ipv4.is_used) { ifaddr = cur; + idx = i; break; } } @@ -4072,8 +4047,8 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface, */ ifaddr->addr_state = NET_ADDR_PREFERRED; - NET_DBG("[%d] interface %p address %s type %s added", i, iface, - net_sprint_ipv4_addr(addr), + NET_DBG("[%d] interface %p address %s type %s added", + idx, iface, net_sprint_ipv4_addr(addr), net_addr_type2str(addr_type)); net_mgmt_event_notify_with_info(NET_EVENT_IPV4_ADDR_ADD, iface, @@ -4092,7 +4067,6 @@ bool net_if_ipv4_addr_rm(struct net_if *iface, const struct in_addr *addr) { struct net_if_ipv4 *ipv4; bool ret = false; - int i; net_if_lock(iface); @@ -4101,7 +4075,7 @@ bool net_if_ipv4_addr_rm(struct net_if *iface, const struct in_addr *addr) goto out; } - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!ipv4->unicast[i].ipv4.is_used) { continue; } @@ -4113,7 +4087,7 @@ bool net_if_ipv4_addr_rm(struct net_if *iface, const struct in_addr *addr) ipv4->unicast[i].ipv4.is_used = false; - NET_DBG("[%d] interface %p address %s removed", + NET_DBG("[%zu] interface %p address %s removed", i, iface, net_sprint_ipv4_addr(addr)); net_mgmt_event_notify_with_info( @@ -4222,7 +4196,7 @@ void net_if_ipv4_addr_foreach(struct net_if *iface, net_if_ip_addr_cb_t cb, goto out; } - for (int i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { struct net_if_addr *if_addr = &ipv4->unicast[i].ipv4; if (!if_addr->is_used) { @@ -4241,13 +4215,12 @@ static struct net_if_mcast_addr *ipv4_maddr_find(struct net_if *iface, const struct in_addr *addr) { struct net_if_ipv4 *ipv4 = iface->config.ip.ipv4; - int i; if (!ipv4) { return NULL; } - for (i = 0; i < NET_IF_MAX_IPV4_MADDR; i++) { + ARRAY_FOR_EACH(ipv4->mcast, i) { if ((is_used && !ipv4->mcast[i].is_used) || (!is_used && ipv4->mcast[i].is_used)) { continue; @@ -4427,13 +4400,12 @@ static void iface_ipv4_init(int if_count) static void leave_ipv4_mcast_all(struct net_if *iface) { struct net_if_ipv4 *ipv4 = iface->config.ip.ipv4; - int i; if (!ipv4) { return; } - for (i = 0; i < NET_IF_MAX_IPV4_MADDR; i++) { + ARRAY_FOR_EACH(ipv4->mcast, i) { if (!ipv4->mcast[i].is_used || !ipv4->mcast[i].is_joined) { continue; From 5bfcec503b6ca7809f3a3830f93985bdd825b45b Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 2 Feb 2024 16:18:26 +0200 Subject: [PATCH 0042/2402] samples: mgmt: hawkbit: Simplify DHCPv4 address detection No need to loop through network interface addresses, just listen DHCPv4 bound event and use that as a condition to continue. Signed-off-by: Jukka Rissanen --- samples/subsys/mgmt/hawkbit/src/dhcp.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/samples/subsys/mgmt/hawkbit/src/dhcp.c b/samples/subsys/mgmt/hawkbit/src/dhcp.c index ec433dae7e1..b8dae6357a3 100644 --- a/samples/subsys/mgmt/hawkbit/src/dhcp.c +++ b/samples/subsys/mgmt/hawkbit/src/dhcp.c @@ -22,24 +22,15 @@ static void handler(struct net_mgmt_event_callback *cb, uint32_t mgmt_event, struct net_if *iface) { - int i; bool notified = false; - if (mgmt_event != NET_EVENT_IPV4_ADDR_ADD) { + if (mgmt_event != NET_EVENT_IPV4_DHCP_BOUND) { return; } - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (iface->config.ip.ipv4->unicast[i].ipv4.addr_type != - NET_ADDR_DHCP) { - continue; - } - - if (!notified) { - k_sem_give(&got_address); - notified = true; - } - break; + if (!notified) { + k_sem_give(&got_address); + notified = true; } } @@ -51,7 +42,7 @@ void app_dhcpv4_startup(void) struct net_if *iface; net_mgmt_init_event_callback(&mgmt_cb, handler, - NET_EVENT_IPV4_ADDR_ADD); + NET_EVENT_IPV4_DHCP_BOUND); net_mgmt_add_event_callback(&mgmt_cb); iface = net_if_get_default(); From a943d7fd5338898487bc1a96806a48ac9aa87790 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 2 Feb 2024 17:30:16 +0200 Subject: [PATCH 0043/2402] net: Convert various address loops to use ARRAY_FOR_EACH macro Convert various networking subsystem files to use ARRAY_FOR_EACH macro to make the looping more robust. Signed-off-by: Jukka Rissanen --- subsys/net/l2/ethernet/arp.c | 3 +-- subsys/net/lib/config/init.c | 3 +-- subsys/net/lib/shell/iface.c | 29 +++++++++++++---------------- subsys/net/lib/shell/ipv4.c | 3 +-- subsys/net/lib/shell/ipv6.c | 3 +-- 5 files changed, 17 insertions(+), 24 deletions(-) diff --git a/subsys/net/l2/ethernet/arp.c b/subsys/net/l2/ethernet/arp.c index 93b63f246ad..5619c1b28d0 100644 --- a/subsys/net/l2/ethernet/arp.c +++ b/subsys/net/l2/ethernet/arp.c @@ -220,13 +220,12 @@ static inline struct in_addr *if_get_addr(struct net_if *iface, struct in_addr *addr) { struct net_if_ipv4 *ipv4 = iface->config.ip.ipv4; - int i; if (!ipv4) { return NULL; } - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (ipv4->unicast[i].ipv4.is_used && ipv4->unicast[i].ipv4.address.family == AF_INET && ipv4->unicast[i].ipv4.addr_state == NET_ADDR_PREFERRED && diff --git a/subsys/net/lib/config/init.c b/subsys/net/lib/config/init.c index a54fc0ed5c9..2cc7236dfcc 100644 --- a/subsys/net/lib/config/init.c +++ b/subsys/net/lib/config/init.c @@ -62,13 +62,12 @@ static void ipv4_addr_add_handler(struct net_mgmt_event_callback *cb, #if CONFIG_NET_CONFIG_LOG_LEVEL >= LOG_LEVEL_INF char hr_addr[NET_IPV4_ADDR_LEN]; #endif - int i; if (mgmt_event != NET_EVENT_IPV4_ADDR_ADD) { return; } - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(iface->config.ip.ipv4->unicast, i) { struct net_if_addr *if_addr = &iface->config.ip.ipv4->unicast[i].ipv4; diff --git a/subsys/net/lib/shell/iface.c b/subsys/net/lib/shell/iface.c index b238846ba19..5a31c6e8d59 100644 --- a/subsys/net/lib/shell/iface.c +++ b/subsys/net/lib/shell/iface.c @@ -54,9 +54,8 @@ static void print_supported_ethernet_capabilities( const struct shell *sh, struct net_if *iface) { enum ethernet_hw_caps caps = net_eth_get_hw_capabilities(iface); - int i; - for (i = 0; i < ARRAY_SIZE(eth_hw_caps); i++) { + ARRAY_FOR_EACH(eth_hw_caps, i) { if (caps & eth_hw_caps[i].capability) { PR("\t%s\n", eth_hw_caps[i].description); } @@ -150,7 +149,7 @@ static void iface_cb(struct net_if *iface, void *user_data) #endif const char *extra; #if defined(CONFIG_NET_IP) - int i, count; + int count; #endif if (data->user_data && data->user_data != iface) { @@ -257,7 +256,7 @@ static void iface_cb(struct net_if *iface, void *user_data) if (!ret && params.priority_queues_num) { count = params.priority_queues_num; PR("Priority queues:\n"); - for (i = 0; i < count; ++i) { + for (int i = 0; i < count; ++i) { params.qav_param.queue_id = i; params.qav_param.type = ETHERNET_QAV_PARAM_TYPE_STATUS; @@ -290,7 +289,7 @@ static void iface_cb(struct net_if *iface, void *user_data) eth_ctx = net_if_l2_data(iface); if (eth_ctx->vlan_enabled) { - for (i = 0; i < CONFIG_NET_VLAN_COUNT; i++) { + for (int i = 0; i < CONFIG_NET_VLAN_COUNT; i++) { if (eth_ctx->vlan[i].iface != iface || eth_ctx->vlan[i].tag == NET_VLAN_TAG_UNSPEC) { @@ -316,17 +315,16 @@ static void iface_cb(struct net_if *iface, void *user_data) #if defined(CONFIG_NET_IPV6) count = 0; + ipv6 = iface->config.ip.ipv6; - if (!net_if_flag_is_set(iface, NET_IF_IPV6)) { + if (!net_if_flag_is_set(iface, NET_IF_IPV6) || ipv6 == NULL) { PR("%s not %s for this interface.\n", "IPv6", "enabled"); ipv6 = NULL; goto skip_ipv6; } - ipv6 = iface->config.ip.ipv6; - PR("IPv6 unicast addresses (max %d):\n", NET_IF_MAX_IPV6_ADDR); - for (i = 0; ipv6 && i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { unicast = &ipv6->unicast[i]; if (!unicast->is_used) { @@ -349,7 +347,7 @@ static void iface_cb(struct net_if *iface, void *user_data) count = 0; PR("IPv6 multicast addresses (max %d):\n", NET_IF_MAX_IPV6_MADDR); - for (i = 0; ipv6 && i < NET_IF_MAX_IPV6_MADDR; i++) { + ARRAY_FOR_EACH(ipv6->mcast, i) { mcast = &ipv6->mcast[i]; if (!mcast->is_used) { @@ -368,7 +366,7 @@ static void iface_cb(struct net_if *iface, void *user_data) count = 0; PR("IPv6 prefixes (max %d):\n", NET_IF_MAX_IPV6_PREFIX); - for (i = 0; ipv6 && i < NET_IF_MAX_IPV6_PREFIX; i++) { + ARRAY_FOR_EACH(ipv6->prefix, i) { prefix = &ipv6->prefix[i]; if (!prefix->is_used) { @@ -426,17 +424,16 @@ static void iface_cb(struct net_if *iface, void *user_data) } count = 0; + ipv4 = iface->config.ip.ipv4; - if (!net_if_flag_is_set(iface, NET_IF_IPV4)) { + if (!net_if_flag_is_set(iface, NET_IF_IPV4) || ipv4 == NULL) { PR("%s not %s for this interface.\n", "IPv4", "enabled"); ipv4 = NULL; goto skip_ipv4; } - ipv4 = iface->config.ip.ipv4; - PR("IPv4 unicast addresses (max %d):\n", NET_IF_MAX_IPV4_ADDR); - for (i = 0; ipv4 && i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { unicast = &ipv4->unicast[i].ipv4; if (!unicast->is_used) { @@ -461,7 +458,7 @@ static void iface_cb(struct net_if *iface, void *user_data) count = 0; PR("IPv4 multicast addresses (max %d):\n", NET_IF_MAX_IPV4_MADDR); - for (i = 0; ipv4 && i < NET_IF_MAX_IPV4_MADDR; i++) { + ARRAY_FOR_EACH(ipv4->mcast, i) { mcast = &ipv4->mcast[i]; if (!mcast->is_used) { diff --git a/subsys/net/lib/shell/ipv4.c b/subsys/net/lib/shell/ipv4.c index f5c6ea71734..cc2e7e30d70 100644 --- a/subsys/net/lib/shell/ipv4.c +++ b/subsys/net/lib/shell/ipv4.c @@ -20,7 +20,6 @@ static void ip_address_lifetime_cb(struct net_if *iface, void *user_data) const struct shell *sh = data->sh; struct net_if_ipv4 *ipv4 = iface->config.ip.ipv4; const char *extra; - int i; ARG_UNUSED(user_data); @@ -35,7 +34,7 @@ static void ip_address_lifetime_cb(struct net_if *iface, void *user_data) PR("Type \tState \tLifetime (sec)\tAddress\n"); - for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { + ARRAY_FOR_EACH(ipv4->unicast, i) { if (!ipv4->unicast[i].ipv4.is_used || ipv4->unicast[i].ipv4.address.family != AF_INET) { continue; diff --git a/subsys/net/lib/shell/ipv6.c b/subsys/net/lib/shell/ipv6.c index e9052750761..12f4ce66565 100644 --- a/subsys/net/lib/shell/ipv6.c +++ b/subsys/net/lib/shell/ipv6.c @@ -62,7 +62,6 @@ static void address_lifetime_cb(struct net_if *iface, void *user_data) const struct shell *sh = data->sh; struct net_if_ipv6 *ipv6 = iface->config.ip.ipv6; const char *extra; - int i; ARG_UNUSED(user_data); @@ -77,7 +76,7 @@ static void address_lifetime_cb(struct net_if *iface, void *user_data) PR("Type \tState \tLifetime (sec)\tAddress\n"); - for (i = 0; i < NET_IF_MAX_IPV6_ADDR; i++) { + ARRAY_FOR_EACH(ipv6->unicast, i) { struct net_if_ipv6_prefix *prefix; char remaining_str[sizeof("01234567890")]; uint64_t remaining; From 7cb3f47ae9b50fd3ca1e6c6e399f03106831830a Mon Sep 17 00:00:00 2001 From: cyliang tw Date: Thu, 25 Jan 2024 13:47:34 +0800 Subject: [PATCH 0044/2402] drivers: watchdog: support Nuvoton numaker WWDT Add Nuvoton numaker series window watchdog feature. Signed-off-by: cyliang tw --- drivers/watchdog/CMakeLists.txt | 1 + drivers/watchdog/Kconfig | 2 + drivers/watchdog/Kconfig.numaker | 13 + drivers/watchdog/wdt_wwdt_numaker.c | 301 ++++++++++++++++++ dts/arm/nuvoton/m46x.dtsi | 8 + .../watchdog/nuvoton,numaker-wwdt.yaml | 18 ++ 6 files changed, 343 insertions(+) create mode 100644 drivers/watchdog/Kconfig.numaker create mode 100644 drivers/watchdog/wdt_wwdt_numaker.c create mode 100644 dts/bindings/watchdog/nuvoton,numaker-wwdt.yaml diff --git a/drivers/watchdog/CMakeLists.txt b/drivers/watchdog/CMakeLists.txt index 7f58a5461a9..9414b865b55 100644 --- a/drivers/watchdog/CMakeLists.txt +++ b/drivers/watchdog/CMakeLists.txt @@ -40,6 +40,7 @@ zephyr_library_sources_ifdef(CONFIG_WDT_INFINEON_CAT1 wdt_ifx_cat1.c) zephyr_library_sources_ifdef(CONFIG_WDT_OPENTITAN wdt_opentitan.c) zephyr_library_sources_ifdef(CONFIG_WDT_AMBIQ wdt_ambiq.c) zephyr_library_sources_ifdef(CONFIG_WDT_XMC4XXX wdt_xmc4xxx.c) +zephyr_library_sources_ifdef(CONFIG_WWDT_NUMAKER wdt_wwdt_numaker.c) zephyr_library_sources_ifdef(CONFIG_WDT_DW wdt_dw.c wdt_dw_common.c) zephyr_library_sources_ifdef(CONFIG_WDT_INTEL_ADSP wdt_intel_adsp.c wdt_dw_common.c) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 2ee5545f39e..f10dc5582e8 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -122,4 +122,6 @@ source "drivers/watchdog/Kconfig.shell" source "drivers/watchdog/Kconfig.xmc4xxx" +source "drivers/watchdog/Kconfig.numaker" + endif # WATCHDOG diff --git a/drivers/watchdog/Kconfig.numaker b/drivers/watchdog/Kconfig.numaker new file mode 100644 index 00000000000..bc0ac984c7a --- /dev/null +++ b/drivers/watchdog/Kconfig.numaker @@ -0,0 +1,13 @@ +# NUMAKER Watchdog Driver configuration options + +# Copyright (c) 2024 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config WWDT_NUMAKER + bool "Nuvoton NUMAKER MCU Window Watchdog driver" + default y + depends on DT_HAS_NUVOTON_NUMAKER_WWDT_ENABLED + help + This option enables the Watchdog driver for Nuvoton NuMaker family of + processors. + Say y if you wish to enable NuMaker WWDT. diff --git a/drivers/watchdog/wdt_wwdt_numaker.c b/drivers/watchdog/wdt_wwdt_numaker.c new file mode 100644 index 00000000000..3004635031b --- /dev/null +++ b/drivers/watchdog/wdt_wwdt_numaker.c @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nuvoton_numaker_wwdt + +#include +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(wwdt_numaker, CONFIG_WDT_LOG_LEVEL); + +#define NUMAKER_PRESCALER_MAX 15U +#define NUMAKER_COUNTER_MAX 0x3eU +#define NUMAKER_COUNTER_MIN 0x01U + +/* Device config */ +struct wwdt_numaker_config { + /* wdt base address */ + WWDT_T *wwdt_base; + uint32_t clk_modidx; + uint32_t clk_src; + uint32_t clk_div; + const struct device *clk_dev; +}; + +struct wwdt_numaker_data { + wdt_callback_t cb; + bool timeout_valid; + /* watchdog timeout in milliseconds */ + uint32_t timeout; + uint32_t prescaler; + uint32_t counter; +}; + +static int m_wwdt_numaker_clk_get_rate(const struct wwdt_numaker_config *cfg, uint32_t *rate) +{ + + if (cfg->clk_src == CLK_CLKSEL1_WWDTSEL_LIRC) { + *rate = __LIRC / (cfg->clk_div + 1); + } else { + /* clock source is from HCLK, CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 */ + SystemCoreClockUpdate(); + *rate = CLK_GetHCLKFreq() / 2048 / (cfg->clk_div + 1); + } + + return 0; +} + + +/* Convert watchdog clock to nearest ms (rounded up) */ +static uint32_t m_wwdt_numaker_calc_ms(const struct device *dev, uint32_t pow2) +{ + const struct wwdt_numaker_config *cfg = dev->config; + uint32_t clk_freq; + uint32_t prescale_clks; + uint32_t period_ms; + + m_wwdt_numaker_clk_get_rate(cfg, &clk_freq); + prescale_clks = (1 << pow2) * 64; + period_ms = DIV_ROUND_UP(prescale_clks * MSEC_PER_SEC, clk_freq); + + return period_ms; +} + +static int m_wwdt_numaker_calc_window(const struct device *dev, + const struct wdt_window *win, + uint32_t *timeout, + uint32_t *prescaler, + uint32_t *counter) +{ + uint32_t pow2; + uint32_t gap; + + /* Find nearest period value (rounded up) */ + for (pow2 = 0U; pow2 <= NUMAKER_PRESCALER_MAX; pow2++) { + *timeout = m_wwdt_numaker_calc_ms(dev, pow2); + + if (*timeout >= win->max) { + *prescaler = pow2 << WWDT_CTL_PSCSEL_Pos; + if (win->min == 0U) { + *counter = NUMAKER_COUNTER_MAX; + } else { + gap = DIV_ROUND_UP(win->min + * NUMAKER_COUNTER_MAX, + *timeout); + *counter = NUMAKER_COUNTER_MAX - gap; + if (*counter < NUMAKER_COUNTER_MIN) { + *counter = NUMAKER_COUNTER_MIN; + } + } + + return 0; + } + } + + return -EINVAL; +} + +static int wwdt_numaker_install_timeout(const struct device *dev, + const struct wdt_timeout_cfg *cfg) +{ + struct wwdt_numaker_data *data = dev->data; + const struct wwdt_numaker_config *config = dev->config; + uint32_t timeout; + uint32_t prescaler; + uint32_t counter; + + LOG_DBG(""); + /* Validate watchdog already running */ + if (config->wwdt_base->CTL & WWDT_CTL_WWDTEN_Msk) { + LOG_ERR("watchdog is busy"); + return -EBUSY; + } + + if (cfg->window.max == 0U) { + LOG_ERR("window.max should be non-zero"); + return -EINVAL; + } + + if (m_wwdt_numaker_calc_window(dev, &cfg->window, &timeout, &prescaler, &counter) != 0) { + LOG_ERR("window.max is out of range"); + return -EINVAL; + } + + LOG_DBG("counter=%d", counter); + data->timeout = timeout; + data->prescaler = prescaler; + data->counter = counter; + data->cb = cfg->callback; + data->timeout_valid = true; + + return 0; +} + +static int wwdt_numaker_disable(const struct device *dev) +{ + struct wwdt_numaker_data *data = dev->data; + const struct wwdt_numaker_config *cfg = dev->config; + WWDT_T *wwdt_base = cfg->wwdt_base; + + LOG_DBG(""); + /* stop counting */ + wwdt_base->CTL &= ~WWDT_CTL_WWDTEN_Msk; + + /* disable interrupt enable bit */ + wwdt_base->CTL &= ~WWDT_CTL_INTEN_Msk; + + /* disable interrupt */ + irq_disable(DT_INST_IRQN(0)); + + data->timeout_valid = false; + + return 0; +} + +static int wwdt_numaker_setup(const struct device *dev, uint8_t options) +{ + struct wwdt_numaker_data *data = dev->data; + const struct wwdt_numaker_config *cfg = dev->config; + WWDT_T *wwdt_base = cfg->wwdt_base; + uint32_t dbg_mask = 0U; + + LOG_DBG(""); + irq_disable(DT_INST_IRQN(0)); + + /* Validate watchdog already running */ + if (wwdt_base->CTL & WWDT_CTL_WWDTEN_Msk) { + LOG_ERR("watchdog is busy"); + return -EBUSY; + } + + if (!data->timeout_valid) { + LOG_ERR("No valid timeout installed"); + return -EINVAL; + } + + if (options & WDT_OPT_PAUSE_IN_SLEEP) { + LOG_ERR("WDT_OPT_PAUSE_IN_SLEEP is not supported"); + return -ENOTSUP; + } + + if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) { + dbg_mask = WWDT_CTL_ICEDEBUG_Msk; + } + + /* Clear WWDT Reset & Compared Match Interrupt System Flag */ + wwdt_base->STATUS = WWDT_STATUS_WWDTRF_Msk | + WWDT_STATUS_WWDTIF_Msk; + + /* Open WWDT and start counting */ + wwdt_base->CTL = data->prescaler | + (data->counter << WWDT_CTL_CMPDAT_Pos) | + WWDT_CTL_INTEN_Msk | + WWDT_CTL_WWDTEN_Msk | + dbg_mask; + + irq_enable(DT_INST_IRQN(0)); + + return 0; +} + +static int wwdt_numaker_feed(const struct device *dev, int channel_id) +{ + const struct wwdt_numaker_config *cfg = dev->config; + WWDT_T *wwdt_base = cfg->wwdt_base; + + LOG_DBG("CNT=%d, CTL=0x%x", wwdt_base->CNT, wwdt_base->CTL); + ARG_UNUSED(channel_id); + + /* Reload WWDT Counter */ + wwdt_base->RLDCNT = WWDT_RELOAD_WORD; + + return 0; +} + +static void wwdt_numaker_isr(const struct device *dev) +{ + struct wwdt_numaker_data *data = dev->data; + const struct wwdt_numaker_config *cfg = dev->config; + WWDT_T *wwdt_base = cfg->wwdt_base; + + LOG_DBG("CNT=%d", wwdt_base->CNT); + if (wwdt_base->STATUS & WWDT_STATUS_WWDTIF_Msk) { + /* Clear WWDT Compared Match Interrupt Flag */ + wwdt_base->STATUS = WWDT_STATUS_WWDTIF_Msk; + + if (data->cb != NULL) { + data->cb(dev, 0); + } + } +} + +static const struct wdt_driver_api wwdt_numaker_api = { + .setup = wwdt_numaker_setup, + .disable = wwdt_numaker_disable, + .install_timeout = wwdt_numaker_install_timeout, + .feed = wwdt_numaker_feed, +}; + +static int wwdt_numaker_init(const struct device *dev) +{ + const struct wwdt_numaker_config *cfg = dev->config; + struct numaker_scc_subsys scc_subsys; + int err; + + SYS_UnlockReg(); + + irq_disable(DT_INST_IRQN(0)); + /* CLK controller */ + memset(&scc_subsys, 0x00, sizeof(scc_subsys)); + scc_subsys.subsys_id = NUMAKER_SCC_SUBSYS_ID_PCC; + scc_subsys.pcc.clk_modidx = cfg->clk_modidx; + scc_subsys.pcc.clk_src = cfg->clk_src; + scc_subsys.pcc.clk_div = cfg->clk_div; + + /* Equivalent to CLK_EnableModuleClock() */ + err = clock_control_on(cfg->clk_dev, (clock_control_subsys_t)&scc_subsys); + if (err != 0) { + goto done; + } + + /* Equivalent to CLK_SetModuleClock() */ + err = clock_control_configure(cfg->clk_dev, (clock_control_subsys_t)&scc_subsys, NULL); + if (err != 0) { + goto done; + } + + /* Enable NVIC */ + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), + wwdt_numaker_isr, DEVICE_DT_INST_GET(0), 0); + irq_enable(DT_INST_IRQN(0)); + +done: + SYS_LockReg(); + return err; + +} + +/* Set config based on DTS */ +static struct wwdt_numaker_config wwdt_numaker_cfg_inst = { + .wwdt_base = (WWDT_T *)DT_INST_REG_ADDR(0), + .clk_modidx = DT_INST_CLOCKS_CELL(0, clock_module_index), + .clk_src = DT_INST_CLOCKS_CELL(0, clock_source), + .clk_div = DT_INST_CLOCKS_CELL(0, clock_divider), + .clk_dev = DEVICE_DT_GET(DT_PARENT(DT_INST_CLOCKS_CTLR(0))), +}; + +static struct wwdt_numaker_data wwdt_numaker_data_inst; + +DEVICE_DT_INST_DEFINE(0, wwdt_numaker_init, NULL, + &wwdt_numaker_data_inst, &wwdt_numaker_cfg_inst, + POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, + &wwdt_numaker_api); diff --git a/dts/arm/nuvoton/m46x.dtsi b/dts/arm/nuvoton/m46x.dtsi index 9e0014f2597..020c5848809 100644 --- a/dts/arm/nuvoton/m46x.dtsi +++ b/dts/arm/nuvoton/m46x.dtsi @@ -616,6 +616,14 @@ num-bidir-endpoints = <25>; disallow-iso-in-out-same-number; }; + + wwdt: watchdog@40040100 { + compatible = "nuvoton,numaker-wwdt"; + reg = <0x40040100 0x10>; + interrupts = <9 0>; + clocks = <&pcc NUMAKER_WWDT_MODULE NUMAKER_CLK_CLKSEL1_WWDTSEL_LIRC 0>; + status = "disabled"; + }; }; }; diff --git a/dts/bindings/watchdog/nuvoton,numaker-wwdt.yaml b/dts/bindings/watchdog/nuvoton,numaker-wwdt.yaml new file mode 100644 index 00000000000..058e45100d7 --- /dev/null +++ b/dts/bindings/watchdog/nuvoton,numaker-wwdt.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +description: Nuvoton, NuMaker window watchdog timer + +compatible: "nuvoton,numaker-wwdt" + +include: base.yaml + +properties: + reg: + required: true + + interrupts: + required: true + + clocks: + required: true From c4b5b28103b24b94ef18fafcce1f5189b67bed33 Mon Sep 17 00:00:00 2001 From: cyliang tw Date: Mon, 29 Jan 2024 09:42:10 +0800 Subject: [PATCH 0045/2402] tests: drivers: watchdog: wdt_basic_api: support numaker_pfm_m467 Add support for Nuvoton numaker board numaker_pfm_m467. Signed-off-by: cyliang tw --- .../watchdog/wdt_basic_api/boards/numaker_pfm_m467.overlay | 5 +++++ tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c | 3 +++ 2 files changed, 8 insertions(+) create mode 100644 tests/drivers/watchdog/wdt_basic_api/boards/numaker_pfm_m467.overlay diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/numaker_pfm_m467.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/numaker_pfm_m467.overlay new file mode 100644 index 00000000000..78f321a84ad --- /dev/null +++ b/tests/drivers/watchdog/wdt_basic_api/boards/numaker_pfm_m467.overlay @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +&wwdt { + status = "okay"; +}; diff --git a/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c b/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c index 76199a27d63..9415149c89f 100644 --- a/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c +++ b/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c @@ -98,6 +98,9 @@ #define WDT_NODE DT_INST(0, gd_gd32_fwdgt) #elif DT_HAS_COMPAT_STATUS_OKAY(zephyr_counter_watchdog) #define WDT_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(zephyr_counter_watchdog) +#elif DT_HAS_COMPAT_STATUS_OKAY(nuvoton_numaker_wwdt) +#define WDT_NODE DT_INST(0, nuvoton_numaker_wwdt) +#define TIMEOUTS 1 #elif DT_HAS_COMPAT_STATUS_OKAY(andestech_atcwdt200) #define WDT_NODE DT_INST(0, andestech_atcwdt200) #define TIMEOUTS 0 From 270ec8cdb3fa4ddc01adcd90e197c3760c2a67dd Mon Sep 17 00:00:00 2001 From: Manimaran A Date: Wed, 27 Sep 2023 10:48:43 +0530 Subject: [PATCH 0046/2402] drivers: pwm: bbled: Update bbled-pwm, to be compatible with PWM-LED Zephyr has a PWM-LED driver which makes calls to a PWM driver to control the pin. The previous MCHP PWM-BBLED driver do not report its actual PWM cycles, instead it reported the clock source it used: 32KHz or 48MHz. This bug caused the LED-PWM driver set brightness to compute incorrect parameters passed to the PWM-BBLED driver. The BBLED hardware has a built-in divider of 256 therefore its maximum cycles are 128 and 48M/256 respectively. This change also simplified the calculations. A DT overlay for the MEC172x EVB was added to the PWM-LED sample to demonstrate driver operation. We found specifying >= 50 ms for the PWM period in the device tree nodes provided a good operating range for the LED-PWM driver parameter calculations. Note: BBLED hardware implements an 8-bit PWM with a fixed divider of 256 and a 12-bit frequency pre-scaler. Duty cycle is represented by an 8-bit value. Signed-off-by: Manimaran A --- drivers/pwm/pwm_mchp_xec_bbled.c | 221 +++++++++++-------------------- 1 file changed, 80 insertions(+), 141 deletions(-) diff --git a/drivers/pwm/pwm_mchp_xec_bbled.c b/drivers/pwm/pwm_mchp_xec_bbled.c index 63b673ca02e..52177ee3ee2 100644 --- a/drivers/pwm/pwm_mchp_xec_bbled.c +++ b/drivers/pwm/pwm_mchp_xec_bbled.c @@ -24,20 +24,23 @@ LOG_MODULE_REGISTER(pwmbbled_mchp_xec, CONFIG_PWM_LOG_LEVEL); +#define XEC_PWM_BBLED_MAX_FREQ_DIV 256U + /* We will choose frequency from Device Tree */ #define XEC_PWM_BBLED_INPUT_FREQ_HI 48000000 #define XEC_PWM_BBLED_INPUT_FREQ_LO 32768 -#define XEC_PWM_BBLED_MAX_FREQ_DIV 256U -#define XEC_PWM_BBLED_MIN_FREQ_DIV (256U * 4066U) - -/* Maximum frequency BBLED-PWM can generate is scaled by - * 256 * (LD+1) where LD is in [0, 4065]. +/* Hardware blink mode equation is Fpwm = Fin / (256 * (LD + 1)) + * The maximum Fpwm is actually Fin / 256 + * LD in [0, 4095] */ -#define XEC_PWM_BBLED_MAX_PWM_FREQ_AHB_CLK \ - (XEC_PWM_BBLED_INPUT_FREQ_HI / XEC_PWM_BBLED_MAX_FREQ_DIV) -#define XEC_PWM_BBLED_MAX_PWM_FREQ_32K_CLK \ - (XEC_PWM_BBLED_INPUT_FREQ_LO / XEC_PWM_BBLED_MAX_FREQ_DIV) +#define XEC_PWM_BBLED_MAX_PWM_FREQ_HI (XEC_PWM_BBLED_INPUT_FREQ_HI / \ + XEC_PWM_BBLED_MAX_FREQ_DIV) +#define XEC_PWM_BBLED_MAX_PWM_FREQ_LO (XEC_PWM_BBLED_INPUT_FREQ_LO / \ + XEC_PWM_BBLED_MAX_FREQ_DIV) +#define XEC_PWM_BBLED_LD_MAX 4095 +#define XEC_PWM_BBLED_DC_MIN 1u /* 0 full off */ +#define XEC_PWM_BBLED_DC_MAX 254u /* 255 is full on */ /* BBLED PWM mode uses the duty cycle to set the PWM frequency: * Fpwm = Fclock / (256 * (LD + 1)) OR @@ -98,12 +101,10 @@ LOG_MODULE_REGISTER(pwmbbled_mchp_xec, CONFIG_PWM_LOG_LEVEL); /* DT enum values */ #define XEC_PWM_BBLED_CLKSEL_32K 0 -#define XEC_PWM_BBLED_CLKSEL_PCR_SLOW 1 -#define XEC_PWM_BBLED_CLKSEL_AHB_48M 2 +#define XEC_PWM_BBLED_CLKSEL_AHB_48M 1 #define XEC_PWM_BBLED_CLKSEL_0 XEC_PWM_BBLED_CLKSEL_32K -#define XEC_PWM_BBLED_CLKSEL_1 XEC_PWM_BBLED_CLKSEL_PCR_SLOW -#define XEC_PWM_BBLED_CLKSEL_2 XEC_PWM_BBLED_CLKSEL_AHB_48M +#define XEC_PWM_BBLED_CLKSEL_1 XEC_PWM_BBLED_CLKSEL_AHB_48M struct bbled_regs { @@ -133,52 +134,6 @@ struct bbled_xec_data { uint32_t config; }; -/* Compute BBLED PWM delay factor to produce requested frequency. - * Fpwm = Fclk / (256 * (LD+1)) where Fclk is 48MHz or 32KHz and - * LD is a 12-bit value in [0, 4096]. - * We expect 256 <= pulse_cycles <= (256 * 4096) - * period_cycles = (period * cycles_per_sec) / NSEC_PER_SEC; - * period_cycles = (Tpwm * Fclk) = Fclk / Fpwm - * period_cycles = Fclk * (256 * (LD+1)) / Fclk = (256 * (LD+1)) - * (LD+1) = period_cycles / 256 - */ -static uint32_t xec_pwmbb_compute_ld(const struct device *dev, uint32_t period_cycles) -{ - uint32_t ld = 0; - - ld = period_cycles / 256U; - if (ld > 0) { - if (ld > 4096U) { - ld = 4096U; - } - ld--; - } - - return ld; -} - -/* BBLED-PWM duty cycle set in 8-bit MINIMUM field of BBLED LIMITS register. - * Limits.Minimum == 0 (alwyas off, output driven low) - * == 255 (always on, output driven high) - * 1 <= Limits.Minimum <= 254 duty cycle - */ -static uint32_t xec_pwmbb_compute_dc(uint32_t period_cycles, uint32_t pulse_cycles) -{ - uint32_t dc; - - if (pulse_cycles >= period_cycles) { - return 255U; /* always on */ - } - - if (period_cycles < 256U) { - return 0; /* always off */ - } - - dc = (256U * pulse_cycles) / period_cycles; - - return dc; -} - /* Issue: two separate registers must be updated. * LIMITS.MIN = duty cycle = [1, 254] * LIMITS register update takes effect immediately. @@ -193,14 +148,14 @@ static void xec_pwmbb_progam_pwm(const struct device *dev, uint32_t ld, uint32_t struct bbled_regs * const regs = cfg->regs; uint32_t val; - val = regs->delay & ~(XEC_PWM_BBLED_DLY_LO_MSK); - val |= ((ld << XEC_PWM_BBLED_DLY_LO_POS) & XEC_PWM_BBLED_DLY_LO_MSK); - regs->delay = val; - val = regs->limits & ~(XEC_PWM_BBLED_LIM_MIN_MSK); val |= ((dc << XEC_PWM_BBLED_LIM_MIN_POS) & XEC_PWM_BBLED_LIM_MIN_MSK); regs->limits = val; + val = regs->delay & ~(XEC_PWM_BBLED_DLY_LO_MSK); + val |= ((ld << XEC_PWM_BBLED_DLY_LO_POS) & XEC_PWM_BBLED_DLY_LO_MSK); + regs->delay = val; + /* transfer new delay value from holding register */ regs->config |= BIT(XEC_PWM_BBLED_CFG_EN_UPDATE_POS); @@ -209,54 +164,51 @@ static void xec_pwmbb_progam_pwm(const struct device *dev, uint32_t ld, uint32_t regs->config = val; } -/* API implementation: Set the period and pulse width for a single PWM. - * channel must be 0 as each PWM instance implements one output. - * period in clock cycles of currently configured clock. - * pulse width in clock cycles of currently configured clock. - * flags b[7:0] defined by zephyr. b[15:8] can be SoC specific. - * Bit[0] = 1 inverted, bits[7:1] specify capture features not implemented in XEC PWM. - * Note: macro PWM_MSEC() and others convert from other units to nanoseconds. - * BBLED output state is Active High. If Active low is required the GPIO pin invert - * bit must be set. The XEC PWM block also defaults to Active High but it has a bit - * to select Active Low. - * PWM API exposes this function as pwm_set_cycles and has wrapper API defined in - * pwm.h, named pwm_set which: - * Calls pwm_get_cycles_per_second to get current maximum HW frequency as cycles_per_sec - * Computes period_cycles = (period * cycles_per_sec) / NSEC_PER_SEC - * pulse_cycles = (pulse * cycles_per_sec) / NSEC_PER_SEC - * Call pwm_set_cycles passing period_cycles and pulse_cycles. - * - * BBLED PWM input frequency is 32KHz (POR default) or 48MHz selected by device tree - * at application build time. - * BBLED Fpwm = Fin / (256 * (LD + 1)) where LD = [0, 4095] - * This equation tells use the maximum number of cycles of Fin the hardware can - * generate is 256 whereas the mininum number of cycles is 256 * 4096. - * - * Fin = 32KHz - * Fpwm-min = 32768 / (256 * 4096) = 31.25 mHz = 31250000 nHz = 0x01DC_D650 nHz - * Fpwm-max = 32768 / 256 = 128 Hz = 128e9 nHz = 0x1D_CD65_0000 nHz - * Tpwm-min = 32e9 ns = 0x0007_7359_4000 ns - * Tpmw-max = 7812500 ns = 0x0077_3594 ns - * - * Fin = 48MHz - * Fpwm-min = 48e6 / (256 * 4096) = 45.7763 Hz = 45776367188 nHz = 0x000A_A87B_EE53 nHz - * Fpwm-max = 48e6 / 256 = 187500 = 1.875e14 = 0xAA87_BEE5_3800 nHz - * Tpwm-min = 5334 ns = 0x14D6 ns - * Tpwm-max = 21845333 ns = 0x014D_5555 ns +/* API implementation: Get the clock rate (cycles per second) for a single PWM output. + * BBLED in PWM mode (same as blink mode) PWM frequency = Source Frequency / (256 * (LP + 1)) + * where Source Frequency is either 48 MHz or 32768 Hz and LP is the 12-bit low delay + * field of the DELAY register. We return the maximum PWM frequency which is configured + * hardware input frequency (32K or 48M) divided by 256. */ -static int pwm_bbled_xec_check_cycles(uint32_t period_cycles, uint32_t pulse_cycles) +static int pwm_bbled_xec_get_cycles_per_sec(const struct device *dev, + uint32_t channel, uint64_t *cycles) { - if ((period_cycles < 256U) || (period_cycles > (4096U * 256U))) { - return -EINVAL; + const struct pwm_bbled_xec_config * const cfg = dev->config; + struct bbled_regs * const regs = cfg->regs; + + if (channel > 0) { + return -EIO; } - if ((pulse_cycles < 256U) || (pulse_cycles > (4096U * 256U))) { - return -EINVAL; + if (cycles) { + if (regs->config & BIT(XEC_PWM_BBLED_CFG_CLK_SRC_48M_POS)) { + *cycles = XEC_PWM_BBLED_MAX_PWM_FREQ_HI; /* 187,500 Hz */ + } else { + *cycles = XEC_PWM_BBLED_MAX_PWM_FREQ_LO; /* 128 Hz */ + } } return 0; } +/* API PWM set cycles: + * pulse == 0 -> pin should be constant inactive level + * pulse >= period -> pin should be constant active level + * hardware PWM (blink) mode: Fpwm = Fin_actual / (LD + 1) + * Fin_actual = XEC_PWM_BBLED_MAX_PWM_FREQ_HI or XEC_PWM_BBLED_MAX_PWM_FREQ_LO. + * period cycles and pulse cycles both zero is OFF + * pulse cycles == 0 is OFF + * pulse cycles > 0 and period cycles == 0 is OFF + * otherwise + * compute duty cycle = 256 * (pulse_cycles / period_cycles). + * compute (LD + 1) = Fin_actual / Fpwm + * program LD into bits[11:0] of Delay register + * program duty cycle info bits[7:0] of Limits register + * NOTE: flags parameter is currently used for pin invert and PWM capture. + * The BBLED HW does not support pin invert or PWM capture. + * NOTE 2: Pin invert is possible by using the MCHP function invert feature + * of the GPIO pin. This property can be set using PINCTRL at build time. + */ static int pwm_bbled_xec_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles, uint32_t pulse_cycles, pwm_flags_t flags) @@ -264,62 +216,49 @@ static int pwm_bbled_xec_set_cycles(const struct device *dev, uint32_t channel, const struct pwm_bbled_xec_config * const cfg = dev->config; struct bbled_regs * const regs = cfg->regs; uint32_t dc, ld; - int ret; if (channel > 0) { + LOG_ERR("Invalid channel: %u", channel); return -EIO; } if (flags) { - /* PWM polarity not supported (yet?) */ return -ENOTSUP; } - if ((pulse_cycles == 0U) && (period_cycles == 0U)) { /* Controller off, clocks gated */ + LOG_DBG("period_cycles = %u pulse_cycles = %u", period_cycles, pulse_cycles); + + if (pulse_cycles == 0u) { + /* drive pin to inactive state */ regs->config = (regs->config & ~XEC_PWM_BBLED_CFG_MODE_MSK) | XEC_PWM_BBLED_CFG_MODE_OFF; - } else if ((pulse_cycles == 0U) && (period_cycles > 0U)) { - /* PWM mode: Limits minimum duty cycle == 0 -> LED output is fully OFF */ regs->limits &= ~XEC_PWM_BBLED_LIM_MIN_MSK; - } else if ((pulse_cycles > 0U) && (period_cycles == 0U)) { - /* PWM mode: Limits minimum duty cycle == full value -> LED output is fully ON */ - regs->limits |= XEC_PWM_BBLED_LIM_MIN_MSK; + regs->delay &= ~(XEC_PWM_BBLED_DLY_LO_MSK); + } else if (pulse_cycles >= period_cycles) { + /* drive pin to active state */ + regs->config = (regs->config & ~XEC_PWM_BBLED_CFG_MODE_MSK) + | XEC_PWM_BBLED_CFG_MODE_ALWAYS_ON; + regs->limits &= ~XEC_PWM_BBLED_LIM_MIN_MSK; + regs->delay &= ~(XEC_PWM_BBLED_DLY_LO_MSK); } else { - ret = pwm_bbled_xec_check_cycles(period_cycles, pulse_cycles); - if (ret) { - LOG_DBG("Target frequency out of range"); - return ret; + ld = period_cycles; + if (ld) { + ld--; + if (ld > XEC_PWM_BBLED_LD_MAX) { + ld = XEC_PWM_BBLED_LD_MAX; + } } - ld = xec_pwmbb_compute_ld(dev, period_cycles); - dc = xec_pwmbb_compute_dc(period_cycles, pulse_cycles); - xec_pwmbb_progam_pwm(dev, ld, dc); - } - - return 0; -} - -/* API implementation: Get the clock rate (cycles per second) for a single PWM output. - * BBLED in PWM mode (same as blink mode) PWM frequency = Source Frequency / (256 * (LP + 1)) - * where Source Frequency is either 48 MHz or 32768 Hz and LP is the 12-bit low delay - * field of the DELAY register. - */ -static int pwm_bbled_xec_get_cycles_per_sec(const struct device *dev, - uint32_t channel, uint64_t *cycles) -{ - const struct pwm_bbled_xec_config * const cfg = dev->config; - struct bbled_regs * const regs = cfg->regs; + dc = ((XEC_PWM_BBLED_DC_MAX + 1) * pulse_cycles / period_cycles); + if (dc < XEC_PWM_BBLED_DC_MIN) { + dc = XEC_PWM_BBLED_DC_MIN; + } else if (dc > XEC_PWM_BBLED_DC_MAX) { + dc = XEC_PWM_BBLED_DC_MAX; + } - if (channel > 0) { - return -EIO; - } + LOG_DBG("Program: ld = 0x%0x dc = 0x%0x", ld, dc); - if (cycles) { - if (regs->config & BIT(XEC_PWM_BBLED_CFG_CLK_SRC_48M_POS)) { - *cycles = XEC_PWM_BBLED_INPUT_FREQ_HI; - } else { - *cycles = XEC_PWM_BBLED_INPUT_FREQ_LO; - } + xec_pwmbb_progam_pwm(dev, ld, dc); } return 0; From 28475a34968bee0951816926e6450001ef941706 Mon Sep 17 00:00:00 2001 From: Manimaran A Date: Wed, 27 Sep 2023 10:58:24 +0530 Subject: [PATCH 0047/2402] drivers: pwm: bbled: Update bbled-pwm dts files Updated Overlay, dtsi and yaml files. Signed-off-by: Manimaran A --- .../microchip/mec152x/mec152xhsz-pinctrl.dtsi | 15 +++ .../microchip/mec172x/mec172xnsz-pinctrl.dtsi | 22 ++++ dts/bindings/pwm/microchip,xec-pwmbbled.yaml | 7 +- .../boards/mec15xxevb_assy6853.overlay | 81 ++++++++++++++ .../boards/mec172xevb_assy6906.overlay | 100 ++++++++++++++++++ 5 files changed, 221 insertions(+), 4 deletions(-) create mode 100644 samples/drivers/led_pwm/boards/mec15xxevb_assy6853.overlay create mode 100644 samples/drivers/led_pwm/boards/mec172xevb_assy6906.overlay diff --git a/dts/arm/microchip/mec152x/mec152xhsz-pinctrl.dtsi b/dts/arm/microchip/mec152x/mec152xhsz-pinctrl.dtsi index 952401b8cf7..bb276d8603d 100644 --- a/dts/arm/microchip/mec152x/mec152xhsz-pinctrl.dtsi +++ b/dts/arm/microchip/mec152x/mec152xhsz-pinctrl.dtsi @@ -1349,4 +1349,19 @@ low-power-enable; }; + /* BBLED */ + led0_gpio156_sleep: led0_gpio156_sleep { + pinmux = < MCHP_XEC_PINMUX(0156, MCHP_AF1) >; + low-power-enable; + }; + + led1_gpio157_sleep: led1_gpio157_sleep { + pinmux = < MCHP_XEC_PINMUX(0157, MCHP_AF1) >; + low-power-enable; + }; + + led2_gpio153_sleep: led2_gpio153_sleep { + pinmux = < MCHP_XEC_PINMUX(0153, MCHP_AF1) >; + low-power-enable; + }; }; diff --git a/dts/arm/microchip/mec172x/mec172xnsz-pinctrl.dtsi b/dts/arm/microchip/mec172x/mec172xnsz-pinctrl.dtsi index fc79cf357fa..c68f634707a 100644 --- a/dts/arm/microchip/mec172x/mec172xnsz-pinctrl.dtsi +++ b/dts/arm/microchip/mec172x/mec172xnsz-pinctrl.dtsi @@ -1344,4 +1344,26 @@ pinmux = < MCHP_XEC_PINMUX(0140, MCHP_AF3) >; low-power-enable; }; + + /* BBLED */ + led0_gpio156_sleep: led0_gpio156_sleep { + pinmux = < MCHP_XEC_PINMUX(0156, MCHP_AF1) >; + low-power-enable; + }; + + led1_gpio157_sleep: led1_gpio157_sleep { + pinmux = < MCHP_XEC_PINMUX(0157, MCHP_AF1) >; + low-power-enable; + }; + + led2_gpio153_sleep: led2_gpio153_sleep { + pinmux = < MCHP_XEC_PINMUX(0153, MCHP_AF1) >; + low-power-enable; + }; + + led3_gpio035_sleep: led3_gpio035_sleep { + pinmux = < MCHP_XEC_PINMUX(035, MCHP_AF4) >; + low-power-enable; + }; + }; diff --git a/dts/bindings/pwm/microchip,xec-pwmbbled.yaml b/dts/bindings/pwm/microchip,xec-pwmbbled.yaml index 6ee66fafcd9..e672df583f6 100644 --- a/dts/bindings/pwm/microchip,xec-pwmbbled.yaml +++ b/dts/bindings/pwm/microchip,xec-pwmbbled.yaml @@ -30,11 +30,9 @@ properties: description: | Clock source selection: 32 KHz is available in deep sleep. - PWM_BBLED_CLK_AHB: Clock source is the PLL based AHB clock - - PWM_BBLED_CLK_SLOW: Clock source is the PLL based PCR slow clock - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain enum: - "PWM_BBLED_CLK_32K" - - "PWM_BBLED_CLK_SLOW" - "PWM_BBLED_CLK_48M" pinctrl-0: @@ -44,7 +42,7 @@ properties: required: true "#pwm-cells": - const: 2 + const: 3 enable-low-power-32k: type: boolean @@ -55,9 +53,10 @@ properties: When BBLED enter into Suspend state, 48MHz clock will be switched off by PCR(Power, Clock and Reset) block. But 32KHz Core clock will be available to BBLED. There may be a product requirement, either to blink (or) not blink LED in Suspend state. - Flag "enable-low-power-32k" shall be used along with 32KHz clock to blink (or) not blink + Property "enable-low-power-32k" shall be used along with 32KHz clock to blink (or) not blink the LED in Suspend state. pwm-cells: - channel - period + - flags diff --git a/samples/drivers/led_pwm/boards/mec15xxevb_assy6853.overlay b/samples/drivers/led_pwm/boards/mec15xxevb_assy6853.overlay new file mode 100644 index 00000000000..55586ffc3c9 --- /dev/null +++ b/samples/drivers/led_pwm/boards/mec15xxevb_assy6853.overlay @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2023 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* MEC152x EVB + * BBLED controller 0 uses GPIO156/LED0 connected to JP31-13 + * BBLED controller 1 uses GPIO157/LED1 connected to JP31-15 + * BBLED controller 2 uses GPIO153/LED2 connected to JP31-17 + * + * BBLED hardware divides input clock (32KHz or 48MHz) by (256 * (prescalar+1) + * and implements duty cycle for blink mode as an 8-bit value where 0 is off and + * 255 full on. BBLED PWM is 8-bit. + * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256. + * Due to all the above we use 50 ms for DT PWM period. + */ + +/* PWM_SEC(1) PWM_USEC(7812) */ +/ { + pwmleds { + compatible = "pwm-leds"; + /* struct pwm_dt_spec: phandle channel period(ns) flags */ + bbled_pwm0: bbled_pwm0 { + pwms = <&bbled0 0 PWM_MSEC(50) PWM_POLARITY_NORMAL>; + }; + bbled_pwm1: bbled_pwm1 { + pwms = <&bbled1 0 PWM_MSEC(50) PWM_POLARITY_NORMAL>; + }; + bbled_pwm2: bbled_pwm2 { + pwms = <&bbled2 0 PWM_MSEC(50) PWM_POLARITY_NORMAL>; + }; + }; +}; + +&pinctrl { + led0_gpio156_invert: led0_gpio156_invert { + pinmux = ; + microchip,output-func-invert; + }; + led1_gpio157_invert: led1_gpio157_invert { + pinmux = ; + microchip,output-func-invert; + }; + led2_gpio153_invert: led2_gpio153_invert { + pinmux = ; + microchip,output-func-invert; + }; +}; + +&bbled0 { + compatible = "microchip,xec-pwmbbled"; + clock-select = "PWM_BBLED_CLK_32K"; + pinctrl-0 = <&led0_gpio156>; + pinctrl-1 = <&led0_gpio156_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + #pwm-cells = <3>; +}; + +&bbled1 { + compatible = "microchip,xec-pwmbbled"; + clock-select = "PWM_BBLED_CLK_32K"; + pinctrl-0 = <&led1_gpio157>; + pinctrl-1 = <&led1_gpio157_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + #pwm-cells = <3>; +}; + +&bbled2 { + compatible = "microchip,xec-pwmbbled"; + clock-select = "PWM_BBLED_CLK_32K"; + pinctrl-0 = <&led2_gpio153>; + pinctrl-1 = <&led2_gpio153_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + #pwm-cells = <3>; +}; diff --git a/samples/drivers/led_pwm/boards/mec172xevb_assy6906.overlay b/samples/drivers/led_pwm/boards/mec172xevb_assy6906.overlay new file mode 100644 index 00000000000..9b1b7fd8862 --- /dev/null +++ b/samples/drivers/led_pwm/boards/mec172xevb_assy6906.overlay @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2023 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* MEC172x EVB + * BBLED controller 0 uses GPIO156/LED1 connected to JP71-11 + * BBLED controller 1 uses GPIO157/LED2 connected to JP71-13 + * BBLED controller 2 uses GPIO153/LED3 connected to JP71-5 + * BBLED controller 3 uses GPIO035/PWM8 connected to JP67-19 + * NOTE: Data sheet indicates BBLED3 uses GPIO035. + * Schematic Rev A1p0 shows LED3 on GPIO226 (incorrect). + * BBLED hardware divides input clock (32KHz or 48MHz) by (256 * (prescalar+1) + * and implements duty cycle for blink mode as an 8-bit value where 0 is off and + * 255 full on. BBLED PWM is 8-bit. + * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256. + * Due to all the above we use 50 ms for DT PWM period. + */ + +/* PWM_SEC(1) PWM_USEC(7812) */ +/ { + pwmleds { + compatible = "pwm-leds"; + /* struct pwm_dt_spec: phandle channel period(ns) flags */ + bbled_pwm0: bbled_pwm0 { + pwms = <&bbled0 0 PWM_MSEC(50) PWM_POLARITY_NORMAL>; + }; + bbled_pwm1: bbled_pwm1 { + pwms = <&bbled1 0 PWM_MSEC(50) PWM_POLARITY_NORMAL>; + }; + bbled_pwm2: bbled_pwm2 { + pwms = <&bbled2 0 PWM_MSEC(50) PWM_POLARITY_NORMAL>; + }; + bbled_pwm3: bbled_pwm3 { + pwms = <&bbled3 0 PWM_MSEC(50) PWM_POLARITY_NORMAL>; + }; + }; +}; + +&pinctrl { + led0_gpio156_invert: led0_gpio156_invert { + pinmux = ; + microchip,output-func-invert; + }; + led1_gpio157_invert: led1_gpio157_invert { + pinmux = ; + microchip,output-func-invert; + }; + led2_gpio153_invert: led2_gpio153_invert { + pinmux = ; + microchip,output-func-invert; + }; + led3_gpio035_invert: led3_gpio035_invert { + pinmux = ; + microchip,output-func-invert; + }; +}; + +&bbled0 { + compatible = "microchip,xec-pwmbbled"; + clock-select = "PWM_BBLED_CLK_32K"; + pinctrl-0 = <&led0_gpio156>; + pinctrl-1 = <&led0_gpio156_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + #pwm-cells = <3>; +}; + +&bbled1 { + compatible = "microchip,xec-pwmbbled"; + clock-select = "PWM_BBLED_CLK_32K"; + pinctrl-0 = <&led1_gpio157>; + pinctrl-1 = <&led1_gpio157_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + #pwm-cells = <3>; +}; + +&bbled2 { + compatible = "microchip,xec-pwmbbled"; + clock-select = "PWM_BBLED_CLK_32K"; + pinctrl-0 = <&led2_gpio153>; + pinctrl-1 = <&led2_gpio153_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + #pwm-cells = <3>; +}; + +&bbled3 { + compatible = "microchip,xec-pwmbbled"; + clock-select = "PWM_BBLED_CLK_32K"; + pinctrl-0 = <&led3_gpio035>; + pinctrl-1 = <&led3_gpio035_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + #pwm-cells = <3>; +}; From 0f5b3269dff642f11d8dcdf114b9e88fce9fe1eb Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Wed, 14 Feb 2024 07:24:26 +0200 Subject: [PATCH 0048/2402] drivers: modem_cellular: allow variable length chat delimiter and filter To allow for differences between modems. Signed-off-by: Tomi Fontanilles --- drivers/modem/modem_cellular.c | 46 +++++++++++++++++----------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index f5e099cd08c..35b05602a74 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -96,8 +96,8 @@ struct modem_cellular_data { /* Modem chat */ struct modem_chat chat; uint8_t chat_receive_buf[128]; - uint8_t chat_delimiter[1]; - uint8_t chat_filter[1]; + uint8_t *chat_delimiter; + uint8_t *chat_filter; uint8_t *chat_argv[32]; /* Status */ @@ -424,9 +424,9 @@ MODEM_CHAT_MATCH_DEFINE(imei_match, "", "", modem_cellular_chat_on_imei); MODEM_CHAT_MATCH_DEFINE(cgmm_match, "", "", modem_cellular_chat_on_cgmm); MODEM_CHAT_MATCH_DEFINE(csq_match, "+CSQ: ", ",", modem_cellular_chat_on_csq); MODEM_CHAT_MATCH_DEFINE(cesq_match, "+CESQ: ", ",", modem_cellular_chat_on_cesq); -MODEM_CHAT_MATCH_DEFINE(cimi_match, "", "", modem_cellular_chat_on_imsi); -MODEM_CHAT_MATCH_DEFINE(cgmi_match, "", "", modem_cellular_chat_on_cgmi); -MODEM_CHAT_MATCH_DEFINE(cgmr_match, "", "", modem_cellular_chat_on_cgmr); +MODEM_CHAT_MATCH_DEFINE(cimi_match __maybe_unused, "", "", modem_cellular_chat_on_imsi); +MODEM_CHAT_MATCH_DEFINE(cgmi_match __maybe_unused, "", "", modem_cellular_chat_on_cgmi); +MODEM_CHAT_MATCH_DEFINE(cgmr_match __maybe_unused, "", "", modem_cellular_chat_on_cgmr); MODEM_CHAT_MATCHES_DEFINE(unsol_matches, MODEM_CHAT_MATCH("+CREG: ", ",", modem_cellular_chat_on_cxreg), @@ -1513,9 +1513,9 @@ static int modem_cellular_init(const struct device *dev) .receive_buf = data->chat_receive_buf, .receive_buf_size = ARRAY_SIZE(data->chat_receive_buf), .delimiter = data->chat_delimiter, - .delimiter_size = ARRAY_SIZE(data->chat_delimiter), + .delimiter_size = strlen(data->chat_delimiter), .filter = data->chat_filter, - .filter_size = ARRAY_SIZE(data->chat_filter), + .filter_size = strlen(data->chat_filter), .argv = data->chat_argv, .argv_size = ARRAY_SIZE(data->chat_argv), .unsol_matches = unsol_matches, @@ -1939,8 +1939,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = {'\r'}, \ - .chat_filter = {'\n'}, \ + .chat_delimiter = "\r", \ + .chat_filter = "\n", \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -1968,8 +1968,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = {'\r'}, \ - .chat_filter = {'\n'}, \ + .chat_delimiter = "\r", \ + .chat_filter = "\n", \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -1997,8 +1997,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = {'\r'}, \ - .chat_filter = {'\n'}, \ + .chat_delimiter = "\r", \ + .chat_filter = "\n", \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -2026,8 +2026,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = {'\r'}, \ - .chat_filter = {'\n'}, \ + .chat_delimiter = "\r", \ + .chat_filter = "\n", \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -2055,8 +2055,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = {'\r'}, \ - .chat_filter = {'\n'}, \ + .chat_delimiter = "\r", \ + .chat_filter = "\n", \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -2084,8 +2084,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = {'\r'}, \ - .chat_filter = {'\n'}, \ + .chat_delimiter = "\r", \ + .chat_filter = "\n", \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -2114,8 +2114,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = {'\r'}, \ - .chat_filter = {'\n'}, \ + .chat_delimiter = "\r", \ + .chat_filter = "\n", \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -2143,8 +2143,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = {'\r'}, \ - .chat_filter = {'\n'}, \ + .chat_delimiter = "\r", \ + .chat_filter = "\n", \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ From c6176b523afa78767e37c45cfcde81fc03436681 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Wed, 14 Feb 2024 08:12:34 +0200 Subject: [PATCH 0049/2402] drivers: modem_cellular: make the buffer sizes configurable To allow fine tuning and accommodate modem differences. Signed-off-by: Tomi Fontanilles --- drivers/modem/Kconfig.cellular | 14 ++++++++++++++ drivers/modem/modem_cellular.c | 15 ++++++++------- 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/drivers/modem/Kconfig.cellular b/drivers/modem/Kconfig.cellular index 0460cda8d96..599a8a61138 100644 --- a/drivers/modem/Kconfig.cellular +++ b/drivers/modem/Kconfig.cellular @@ -36,4 +36,18 @@ config MODEM_CELLULAR_PERIODIC_SCRIPT_MS int "Periodic script interval in milliseconds" default 2000 +config MODEM_CELLULAR_UART_BUFFER_SIZES + int "The UART receive and transmit buffer sizes in bytes." + default 512 + +config MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE + int "The maximum CMUX frame size in bytes." + default 128 + help + This value affects the size of buffers used to receive and transmit CMUX frames. + +config MODEM_CELLULAR_CHAT_BUFFER_SIZES + int "The size of the buffers used for the chat scripts in bytes." + default 128 + endif diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 35b05602a74..63430d45c1a 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -79,23 +79,24 @@ struct modem_cellular_data { /* UART backend */ struct modem_pipe *uart_pipe; struct modem_backend_uart uart_backend; - uint8_t uart_backend_receive_buf[512]; - uint8_t uart_backend_transmit_buf[512]; + uint8_t uart_backend_receive_buf[CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES]; + uint8_t uart_backend_transmit_buf[CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES]; /* CMUX */ struct modem_cmux cmux; - uint8_t cmux_receive_buf[128]; - uint8_t cmux_transmit_buf[256]; + uint8_t cmux_receive_buf[CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE]; + uint8_t cmux_transmit_buf[2 * CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE]; struct modem_cmux_dlci dlci1; struct modem_cmux_dlci dlci2; struct modem_pipe *dlci1_pipe; struct modem_pipe *dlci2_pipe; - uint8_t dlci1_receive_buf[128]; - uint8_t dlci2_receive_buf[256]; + uint8_t dlci1_receive_buf[CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE]; + /* DLCI 2 is only used for chat scripts. */ + uint8_t dlci2_receive_buf[CONFIG_MODEM_CELLULAR_CHAT_BUFFER_SIZES]; /* Modem chat */ struct modem_chat chat; - uint8_t chat_receive_buf[128]; + uint8_t chat_receive_buf[CONFIG_MODEM_CELLULAR_CHAT_BUFFER_SIZES]; uint8_t *chat_delimiter; uint8_t *chat_filter; uint8_t *chat_argv[32]; From c7be3bcd4f4e778300ae6517fc0ced940c000e61 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Wed, 14 Feb 2024 08:43:10 +0200 Subject: [PATCH 0050/2402] samples: net: cellular_modem: small improvements - It now uses the first PPP network interface instead of the default network interface. - Logs are added/improved. - Potentially unused modem_chat matches are declared as such to suppress compiler warnings. Signed-off-by: Tomi Fontanilles --- samples/net/cellular_modem/README.rst | 2 +- samples/net/cellular_modem/src/main.c | 63 ++++++++++++++++----------- 2 files changed, 39 insertions(+), 26 deletions(-) diff --git a/samples/net/cellular_modem/README.rst b/samples/net/cellular_modem/README.rst index 384d8b3bef5..b845b2e37d8 100644 --- a/samples/net/cellular_modem/README.rst +++ b/samples/net/cellular_modem/README.rst @@ -18,7 +18,7 @@ Notes This sample uses the devicetree alias modem to identify the modem instance to use. The sample also presumes that -the modem driver creates the only network interface. +the modem driver creates the only PPP network interface. Setup ***** diff --git a/samples/net/cellular_modem/src/main.c b/samples/net/cellular_modem/src/main.c index 35a97d3e831..6ab5ddc297d 100644 --- a/samples/net/cellular_modem/src/main.c +++ b/samples/net/cellular_modem/src/main.c @@ -127,7 +127,7 @@ static int sample_dns_request(void) return 0; } -int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen) +int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t *port) { int ret; int socket_fd; @@ -140,22 +140,16 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen) socket_fd = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); if (socket_fd < 0) { - printk("Failed to open socket\n"); + printk("Failed to open socket (%d)\n", errno); return -1; } printk("Socket opened\n"); - if (ai_addr->sa_family == AF_INET) { - net_sin(ai_addr)->sin_port = htons(SAMPLE_TEST_ENDPOINT_UDP_ECHO_PORT); - } else if (ai_addr->sa_family == AF_INET6) { - net_sin6(ai_addr)->sin6_port = htons(SAMPLE_TEST_ENDPOINT_UDP_ECHO_PORT); - } else { - printk("Unsupported address family\n"); - return -1; - } + *port = htons(SAMPLE_TEST_ENDPOINT_UDP_ECHO_PORT); for (uint32_t i = 0; i < SAMPLE_TEST_ECHO_PACKETS; i++) { + printk("Sending echo packet\n"); send_start_ms = k_uptime_get_32(); ret = zsock_sendto(socket_fd, sample_test_packet, sizeof(sample_test_packet), 0, @@ -166,6 +160,7 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen) continue; } + printk("Receiving echoed packet"); ret = zsock_recv(socket_fd, sample_recv_buffer, sizeof(sample_recv_buffer), 0); if (ret != sizeof(sample_test_packet)) { printk("Echoed sample test packet has incorrect size\n"); @@ -204,7 +199,7 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen) } -int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen) +int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t *port) { int ret; int socket_fd; @@ -224,14 +219,7 @@ int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen) printk("Socket opened\n"); - if (ai_addr->sa_family == AF_INET) { - net_sin(ai_addr)->sin_port = htons(SAMPLE_TEST_ENDPOINT_UDP_RECEIVE_PORT); - } else if (ai_addr->sa_family == AF_INET6) { - net_sin6(ai_addr)->sin6_port = htons(SAMPLE_TEST_ENDPOINT_UDP_RECEIVE_PORT); - } else { - printk("Unsupported address family\n"); - return -1; - } + *port = htons(SAMPLE_TEST_ENDPOINT_UDP_RECEIVE_PORT); printk("Sending %u packets\n", SAMPLE_TEST_TRANSMIT_PACKETS); send_start_ms = k_uptime_get_32(); @@ -276,7 +264,9 @@ int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen) int main(void) { + struct net_if *const iface = net_if_get_first_by_type(&NET_L2_GET_NAME(PPP)); uint32_t raised_event; + uint16_t *port; const void *info; size_t info_len; int ret; @@ -287,14 +277,14 @@ int main(void) pm_device_action_run(modem, PM_DEVICE_ACTION_RESUME); printk("Bring up network interface\n"); - ret = net_if_up(net_if_get_default()); + ret = net_if_up(iface); if (ret < 0) { printk("Failed to bring up network interface\n"); return -1; } printk("Waiting for L4 connected\n"); - ret = net_mgmt_event_wait_on_iface(net_if_get_default(), + ret = net_mgmt_event_wait_on_iface(iface, NET_EVENT_L4_CONNECTED, &raised_event, &info, &info_len, K_SECONDS(120)); @@ -304,7 +294,7 @@ int main(void) } printk("Waiting for DNS server added\n"); - ret = net_mgmt_event_wait_on_iface(net_if_get_default(), + ret = net_mgmt_event_wait_on_iface(iface, NET_EVENT_DNS_SERVER_ADD, &raised_event, &info, &info_len, K_SECONDS(10)); @@ -318,8 +308,29 @@ int main(void) return -1; } + { + char ip_str[INET6_ADDRSTRLEN]; + const void *src; + + switch (sample_test_dns_addrinfo.ai_addr.sa_family) { + case AF_INET: + src = &net_sin(&sample_test_dns_addrinfo.ai_addr)->sin_addr; + port = &net_sin(&sample_test_dns_addrinfo.ai_addr)->sin_port; + break; + case AF_INET6: + src = &net_sin6(&sample_test_dns_addrinfo.ai_addr)->sin6_addr; + port = &net_sin6(&sample_test_dns_addrinfo.ai_addr)->sin6_port; + break; + default: + printk("Unsupported address family\n"); + return -1; + } + inet_ntop(sample_test_dns_addrinfo.ai_addr.sa_family, src, ip_str, sizeof(ip_str)); + printk("Resolved to %s\n", ip_str); + } + ret = sample_echo_packet(&sample_test_dns_addrinfo.ai_addr, - sample_test_dns_addrinfo.ai_addrlen); + sample_test_dns_addrinfo.ai_addrlen, port); if (ret < 0) { printk("Failed to send echo\n"); @@ -327,7 +338,7 @@ int main(void) } ret = sample_transmit_packets(&sample_test_dns_addrinfo.ai_addr, - sample_test_dns_addrinfo.ai_addrlen); + sample_test_dns_addrinfo.ai_addrlen, port); if (ret < 0) { printk("Failed to send packets\n"); @@ -342,6 +353,8 @@ int main(void) } pm_device_action_run(modem, PM_DEVICE_ACTION_RESUME); + + printk("Waiting for L4 connected\n"); ret = net_mgmt_event_wait_on_iface(net_if_get_default(), NET_EVENT_L4_CONNECTED, &raised_event, &info, &info_len, K_SECONDS(60)); @@ -352,7 +365,7 @@ int main(void) } ret = sample_echo_packet(&sample_test_dns_addrinfo.ai_addr, - sample_test_dns_addrinfo.ai_addrlen); + sample_test_dns_addrinfo.ai_addrlen, port); if (ret < 0) { printk("Failed to send echo after restart\n"); From 9a3dbaf99357a688177506769a212deaa3044d6c Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Wed, 14 Feb 2024 10:27:55 +0200 Subject: [PATCH 0051/2402] drivers: modem_cellular: add nRF91 series (w/ SLM) The nRF91 series devices, when running the Serial LTE Modem (SLM) application starting with nRF Connect SDK 2.6.0, can now be used as standalone modems via the generic modem_cellular driver. A configuration to run the cellular_modem sample on the nRF9160 DK (plugged in to another nRF91 series device running SLM) is provided. Signed-off-by: Tomi Fontanilles --- drivers/modem/Kconfig.cellular | 3 +- drivers/modem/modem_cellular.c | 67 +++++++++++++++++++ dts/bindings/modem/nordic,nrf91-slm.yaml | 9 +++ .../boards/nrf9160dk_nrf9160_ns.conf | 16 +++++ .../boards/nrf9160dk_nrf9160_ns.overlay | 34 ++++++++++ tests/drivers/build_all/modem/uart.dtsi | 6 ++ 6 files changed, 134 insertions(+), 1 deletion(-) create mode 100644 dts/bindings/modem/nordic,nrf91-slm.yaml create mode 100644 samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf create mode 100644 samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.overlay diff --git a/drivers/modem/Kconfig.cellular b/drivers/modem/Kconfig.cellular index 599a8a61138..aacf4449d28 100644 --- a/drivers/modem/Kconfig.cellular +++ b/drivers/modem/Kconfig.cellular @@ -15,7 +15,8 @@ config MODEM_CELLULAR depends on (DT_HAS_QUECTEL_BG95_ENABLED || DT_HAS_ZEPHYR_GSM_PPP_ENABLED || \ DT_HAS_SIMCOM_SIM7080_ENABLED || DT_HAS_U_BLOX_SARA_R4_ENABLED || \ DT_HAS_U_BLOX_SARA_R5_ENABLED || DT_HAS_SWIR_HL7800_ENABLED || \ - DT_HAS_TELIT_ME910G1_ENABLED || DT_HAS_QUECTEL_EG25_G_ENABLED) + DT_HAS_TELIT_ME910G1_ENABLED || DT_HAS_QUECTEL_EG25_G_ENABLED || \ + DT_HAS_NORDIC_NRF91_SLM_ENABLED) help This driver uses the generic 3gpp AT commands, along with the standard protocols CMUX and PPP, to configure diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 63430d45c1a..ed4e998fec3 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -1933,6 +1933,41 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, modem_cellular_chat_callback_handler, 4); #endif +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf91_slm) +MODEM_CHAT_SCRIPT_CMDS_DEFINE(nordic_nrf91_slm_init_chat_script_cmds, + MODEM_CHAT_SCRIPT_CMD_RESP_MULT("AT", allow_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CMEE=1", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CEREG=1", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CEREG?", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGSN", imei_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMM", cgmm_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMI", cgmi_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMR", cgmr_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT#XCMUX=1", ok_match)); + +MODEM_CHAT_SCRIPT_DEFINE(nordic_nrf91_slm_init_chat_script, nordic_nrf91_slm_init_chat_script_cmds, + abort_matches, modem_cellular_chat_callback_handler, 10); + +MODEM_CHAT_SCRIPT_CMDS_DEFINE(nordic_nrf91_slm_dial_chat_script_cmds, + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CFUN=4", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CFUN=1", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT#XCMUX=2", ok_match)); + +MODEM_CHAT_SCRIPT_DEFINE(nordic_nrf91_slm_dial_chat_script, nordic_nrf91_slm_dial_chat_script_cmds, + dial_abort_matches, modem_cellular_chat_callback_handler, 10); + +MODEM_CHAT_SCRIPT_CMDS_DEFINE(nordic_nrf91_slm_periodic_chat_script_cmds, + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CEREG?", ok_match)); + +MODEM_CHAT_SCRIPT_DEFINE(nordic_nrf91_slm_periodic_chat_script, + nordic_nrf91_slm_periodic_chat_script_cmds, abort_matches, + modem_cellular_chat_callback_handler, 4); +#endif + #define MODEM_CELLULAR_INST_NAME(name, inst) \ _CONCAT(_CONCAT(_CONCAT(name, _), DT_DRV_COMPAT), inst) @@ -2169,6 +2204,34 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \ &modem_cellular_api); +#define MODEM_CELLULAR_DEVICE_NORDIC_NRF91_SLM(inst) \ + MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 1500); \ + \ + static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ + .chat_delimiter = "\r\n", \ + .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ + }; \ + \ + static struct modem_cellular_config MODEM_CELLULAR_INST_NAME(config, inst) = { \ + .uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \ + .power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}), \ + .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}), \ + .power_pulse_duration_ms = 100, \ + .reset_pulse_duration_ms = 100, \ + .startup_time_ms = 2000, \ + .shutdown_time_ms = 3000, \ + .init_chat_script = &nordic_nrf91_slm_init_chat_script, \ + .dial_chat_script = &nordic_nrf91_slm_dial_chat_script, \ + .periodic_chat_script = &nordic_nrf91_slm_periodic_chat_script, \ + }; \ + \ + PM_DEVICE_DT_INST_DEFINE(inst, modem_cellular_pm_action); \ + \ + DEVICE_DT_INST_DEFINE(inst, modem_cellular_init, PM_DEVICE_DT_INST_GET(inst), \ + &MODEM_CELLULAR_INST_NAME(data, inst), \ + &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \ + &modem_cellular_api); + #define DT_DRV_COMPAT quectel_bg95 DT_INST_FOREACH_STATUS_OKAY(MODEM_CELLULAR_DEVICE_QUECTEL_BG95) #undef DT_DRV_COMPAT @@ -2200,3 +2263,7 @@ DT_INST_FOREACH_STATUS_OKAY(MODEM_CELLULAR_DEVICE_SWIR_HL7800) #define DT_DRV_COMPAT telit_me910g1 DT_INST_FOREACH_STATUS_OKAY(MODEM_CELLULAR_DEVICE_TELIT_ME910G1) #undef DT_DRV_COMPAT + +#define DT_DRV_COMPAT nordic_nrf91_slm +DT_INST_FOREACH_STATUS_OKAY(MODEM_CELLULAR_DEVICE_NORDIC_NRF91_SLM) +#undef DT_DRV_COMPAT diff --git a/dts/bindings/modem/nordic,nrf91-slm.yaml b/dts/bindings/modem/nordic,nrf91-slm.yaml new file mode 100644 index 00000000000..3f06696197d --- /dev/null +++ b/dts/bindings/modem/nordic,nrf91-slm.yaml @@ -0,0 +1,9 @@ +description: Nordic nRF91 series running the Serial LTE Modem application + +compatible: "nordic,nrf91-slm" + +include: uart-device.yaml + +properties: + mdm-power-gpios: + type: phandle-array diff --git a/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf b/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf new file mode 100644 index 00000000000..441a5395ca1 --- /dev/null +++ b/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf @@ -0,0 +1,16 @@ +CONFIG_UART_ASYNC_API=y + +# Align with the Serial LTE Modem (SLM) application. +CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE=1500 +CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES=1500 + +# Allow large UART TXs to go through @115200. +CONFIG_MODEM_BACKEND_UART_ASYNC_TRANSMIT_TIMEOUT_MS=200 + +# Prevent sockets getting offloaded to the modem. +CONFIG_NET_SOCKETS_OFFLOAD=n + +# Print logs and printk() output on uart0. +CONFIG_LOG=y +CONFIG_LOG_BACKEND_UART=y +CONFIG_MODEM_LOG_LEVEL_DBG=y diff --git a/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.overlay b/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.overlay new file mode 100644 index 00000000000..44ce80601a1 --- /dev/null +++ b/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.overlay @@ -0,0 +1,34 @@ +/ { + aliases { + modem = &modem; + }; +}; + +&uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + hw-flow-control; + status = "okay"; + + pinctrl-0 = <&uart1_default_alt>; + + modem: modem { + compatible = "nordic,nrf91-slm"; + status = "okay"; + mdm-power-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + uart1_default_alt: uart1_default_alt { + group1 { + psels = ; + bias-pull-up; + }; + group2 { + psels = , + , + ; + }; + }; +}; diff --git a/tests/drivers/build_all/modem/uart.dtsi b/tests/drivers/build_all/modem/uart.dtsi index 3d649a2ff60..08da2c325d3 100644 --- a/tests/drivers/build_all/modem/uart.dtsi +++ b/tests/drivers/build_all/modem/uart.dtsi @@ -70,3 +70,9 @@ test_telit_me910g1: telit_me910g1 { test_esp_at: esp_at { compatible = "espressif,esp-at"; }; + +test_nordic_nrf91_slm: nordic_nrf91_slm { + compatible = "nordic,nrf91-slm"; + + mdm-power-gpios = <&test_gpio 0 0>; +}; From 4666d6049575d6bc82683d1ae90a41fded2da35e Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Sat, 11 Nov 2023 16:01:37 +0100 Subject: [PATCH 0052/2402] samples: http_get: move 'not CONFIG_NATIVE_LIBC' filter to POSIX build 'not CONFIG_NATIVE_LIBC' filter is just to prevent building for 'native_posix' platform with additional options selected by 'sample.net.sockets.http_get.posix' testcase. Signed-off-by: Marcin Niestroj --- samples/net/sockets/http_get/sample.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/samples/net/sockets/http_get/sample.yaml b/samples/net/sockets/http_get/sample.yaml index 999c7ba97d6..2de78ce0bee 100644 --- a/samples/net/sockets/http_get/sample.yaml +++ b/samples/net/sockets/http_get/sample.yaml @@ -2,7 +2,7 @@ sample: description: BSD Sockets API HTTP GET example name: socket_http_get common: - filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC + filter: CONFIG_FULL_LIBC_SUPPORTED harness: net min_ram: 32 min_flash: 80 @@ -16,7 +16,7 @@ tests: # Forcibly defines CONFIG_POSIX_API, which is incompatible with # CONFIG_NET_SOCKETS_POSIX_NAMES. sample.net.sockets.http_get.posix: - filter: not CONFIG_NET_SOCKETS_OFFLOAD + filter: not CONFIG_NET_SOCKETS_OFFLOAD and not CONFIG_NATIVE_LIBC platform_exclude: - cc3220sf_launchxl - cc3235sf_launchxl From ab48eae508c9e865fde3381807d1c7e5dd259dd0 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 29 Feb 2024 14:14:24 -0600 Subject: [PATCH 0053/2402] MAINTAINERS: Add decsny to ADC collaborator Add myself as ADC collaborator to facilitate the PRs Signed-off-by: Declan Snyder --- MAINTAINERS.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 2d59af46304..f36e18a5528 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -901,6 +901,8 @@ Release Notes: status: maintained maintainers: - anangl + collaborators: + - decsny files: - drivers/adc/ - include/zephyr/drivers/adc.h From 95084e53e05ef4434480ebcf5ff8126204ce4af2 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 27 Feb 2024 09:23:38 +0100 Subject: [PATCH 0054/2402] samples: drivers: watchdog testing on stm32c031 nucleo board Add the nucleo_c031c6 target to run the samples/drivers/watchdog for iwdg and wwdg on the stm32c0 serie. Signed-off-by: Francois Ramu --- samples/drivers/watchdog/sample.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/samples/drivers/watchdog/sample.yaml b/samples/drivers/watchdog/sample.yaml index 4297f28d77a..1d887396c3c 100644 --- a/samples/drivers/watchdog/sample.yaml +++ b/samples/drivers/watchdog/sample.yaml @@ -27,6 +27,7 @@ tests: filter: dt_compat_enabled("st,stm32-window-watchdog") platform_allow: - b_u585i_iot02a + - nucleo_c031c6 - nucleo_f091rc - nucleo_f103rb - nucleo_f207zg @@ -53,6 +54,7 @@ tests: filter: dt_compat_enabled("st,stm32-watchdog") platform_allow: - b_u585i_iot02a + - nucleo_c031c6 - nucleo_f091rc - nucleo_f103rb - nucleo_f207zg From 72a17b6d887ef20b3cc08a25d8ea1d622792d57a Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Fri, 1 Mar 2024 06:58:48 -0500 Subject: [PATCH 0055/2402] ci: fix doc workflow on schedule Build phase was skipped, we were checking for file changes which will not have any results on a scheduled event. Signed-off-by: Anas Nashif --- .github/workflows/doc-build.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index 8dcf6e7ef95..c67cac82bab 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -54,7 +54,9 @@ jobs: doc-build-html: name: "Documentation Build (HTML)" needs: [doc-file-check] - if: github.repository_owner == 'zephyrproject-rtos' && needs.doc-file-check.outputs.file_check == 'true' + if: > + github.repository_owner == 'zephyrproject-rtos' && + ( needs.doc-file-check.outputs.file_check == 'true' || github.event_name != 'pull_request' ) runs-on: zephyr-runner-linux-x64-4xlarge timeout-minutes: 45 concurrency: @@ -169,6 +171,7 @@ jobs: doc-build-pdf: name: "Documentation Build (PDF)" + needs: [doc-file-check] if: | github.event_name != 'pull_request' && github.repository_owner == 'zephyrproject-rtos' From c53c4e3b4388487d6755edd35b081472b4f67624 Mon Sep 17 00:00:00 2001 From: David Leach Date: Sun, 3 Mar 2024 22:18:37 -0600 Subject: [PATCH 0056/2402] soc: nxp: fix duplicate SOC_MIMX8MP definition SOC_MIMX8MP defined twice in file Signed-off-by: David Leach --- soc/nxp/imx/imx8m/Kconfig.soc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/soc/nxp/imx/imx8m/Kconfig.soc b/soc/nxp/imx/imx8m/Kconfig.soc index 79471279a75..ca93c3fcdeb 100644 --- a/soc/nxp/imx/imx8m/Kconfig.soc +++ b/soc/nxp/imx/imx8m/Kconfig.soc @@ -8,10 +8,6 @@ config SOC_SERIES_IMX8M config SOC_SERIES default "imx8m" if SOC_SERIES_IMX8M -config SOC_MIMX8MP - bool - select SOC_SERIES_IMX8M - config SOC_MIMX8MM6 bool select SOC_SERIES_IMX8M From ca769441d088cf7d48cfe7c0ee774c5fa6a19b1f Mon Sep 17 00:00:00 2001 From: Carles Cufi Date: Sun, 3 Mar 2024 19:55:45 +0100 Subject: [PATCH 0057/2402] doc: porting: Add a section on the new hardware model The current board porting guide explains the new hardware model without making any references to the previous one. Add a new section that explains the rationale behind the transition as well as adding important bits of information for users that need to convert their boards. Signed-off-by: Carles Cufi --- doc/hardware/porting/board_porting.rst | 57 ++++++++++++++++++++++++++ doc/releases/migration-guide-3.7.rst | 4 +- 2 files changed, 58 insertions(+), 3 deletions(-) diff --git a/doc/hardware/porting/board_porting.rst b/doc/hardware/porting/board_porting.rst index c45b2a7bb54..107a284563b 100644 --- a/doc/hardware/porting/board_porting.rst +++ b/doc/hardware/porting/board_porting.rst @@ -8,6 +8,63 @@ directory* with various files in it. Files in the board directory inherit support for at least one SoC and all of its features. Therefore, Zephyr must support your :term:`SoC` as well. +.. _hw_model_v2: + +Transition to the current hardware model +**************************************** + +Shortly after Zephyr 3.6.0 was released, a new hardware model was introduced to +Zephyr. This new model overhauls the way both SoCs and boards are named and +defined, and adds support for features that had been identified as important +over the years. Among them: + +- Support for multi-core, multi-arch AMP (Asymmetrical Multi Processing) SoCs +- Support for multi-SoC boards +- Support for reusing the SoC and board Kconfig trees outside of the Zephyr + build system +- Support for advanced use cases with :ref:`sysbuild` +- Removal of all existing arbitrary and inconsistent uses of Kconfig and folder + names + +All the documentation in this page refers to the current hardware model. Please +refer to the documentation in Zephyr v3.6.0 (or earlier) for information on the +previous, now obsolete, hardware model. + +More information about the rationale, development and concepts behind the new +model can be found in the :github:`original issue <51381>`, the +:github:`original Pull Request <50305>` and, for a complete set of changes +introduced, the `hardware model v2 commit`_. + +Some non-critical features, enhancements and improvements of the new hardware +model are still in development. Check the +:github:`hardware model v2 enhancements issue <69546>` for a complete list. + +The transition from the previous hardware model to the current one (commonly +referred to as "hardware model v2") requires modifications to all existing board +and SoC definitions. A decision was made not to provide direct backwards +compatibility for the previous model, which leaves users transitioning from a +previous version of Zephyr to one including the new model (v3.7.0 and onwards) +with two options if they have an out-of-tree board (or SoC): + +#. Convert the out-of-tree board to the current hardware model (recommended) +#. Take the SoC definition from Zephyr v3.6.0 and copy it to your downstream + repository (ensuring that the build system can find it via a + :ref:`zephyr module ` or ``SOC_ROOT``). This will allow your board, + defined in the previous hardware model, to continue to work + +When converting your board from the previous to the current hardware model, we +recommend first reading through this page to understand the model in detail. You +can then use the `example-application conversion Pull Request`_ as an example on +how to port a simple board. Additionally, a `conversion script`_ is available +and works reliably in many cases (though multi-core SoCs may not be handled +entirely). Finally, the `hardware model v2 commit`_ contains the full conversion +of all existing boards from the old to the current model, so you can use it as a +complete conversion reference. + +.. _hardware model v2 commit: https://github.com/zephyrproject-rtos/zephyr/commit/8dc3f856229ce083c956aa301c31a23e65bd8cd8 +.. _example-application conversion Pull Request: https://github.com/zephyrproject-rtos/example-application/pull/58 +.. _conversion script: https://github.com/zephyrproject-rtos/zephyr/blob/main/scripts/utils/board_v1_to_v2.py + .. _board_and_identifiers: Board and board identifiers diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index 3398e1e9df6..c73d06bfdb7 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -20,9 +20,7 @@ Build System * Completely overhauled the way SoCs and boards are defined. This requires all out-of-tree SoCs and boards to be ported to the new model. See the - :ref:`board_porting_guide` for more detailed information. - * Pull Request: https://github.com/zephyrproject-rtos/zephyr/pull/69607 - * Issue: https://github.com/zephyrproject-rtos/zephyr/issues/51831 + :ref:`hw_model_v2` for more detailed information. Kernel ****** From a24238e9f948d43265b5bce00e622faf203174ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20B=C3=B8e?= Date: Thu, 22 Feb 2024 10:21:23 +0100 Subject: [PATCH 0058/2402] boards: nrf54l15pdk_nrf54l15 support west attach MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add CMake code that fixes west attach on nrf54l15pdk_nrf54l15. I don't know why this fixes west attach as this is cargo cult code. Signed-off-by: Sebastian Bøe --- boards/nordic/nrf54l15pdk/board.cmake | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/boards/nordic/nrf54l15pdk/board.cmake b/boards/nordic/nrf54l15pdk/board.cmake index 378b7bcdb57..2107fb5d71e 100644 --- a/boards/nordic/nrf54l15pdk/board.cmake +++ b/boards/nordic/nrf54l15pdk/board.cmake @@ -1,4 +1,8 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +board_runner_args(jlink "--device=cortex-m33" "--speed=4000") + include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) From 12d89c65bed79936a7b04d7bae60ab3111ced298 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Sun, 3 Mar 2024 16:32:46 +0000 Subject: [PATCH 0059/2402] Bluetooth: Controller: re-add missing hci_vendor.c reference Move the nordic and openisa vendor file under ll_sw and add them back to the list when building for nRF platforms, this was inadvertently removed in 7bd2804c24 Bluetooth: Controller: Build vendor LLL as library and is currently causing a: bt_id: No static addresses stored in controller and random address on nRF devices. Signed-off-by: Fabio Baltieri Signed-off-by: Vinayak Kariappa Chettimada --- subsys/bluetooth/controller/CMakeLists.txt | 4 ++-- subsys/bluetooth/controller/ll_sw/nordic/CMakeLists.txt | 5 +++++ .../controller/{hci/nordic => ll_sw/nordic/hci}/hci_vendor.c | 0 .../controller/{hci/nordic => ll_sw/nordic/hci}/hci_vendor.h | 0 .../{hci/openisa => ll_sw/openisa/hci}/hci_vendor.h | 0 5 files changed, 7 insertions(+), 2 deletions(-) rename subsys/bluetooth/controller/{hci/nordic => ll_sw/nordic/hci}/hci_vendor.c (100%) rename subsys/bluetooth/controller/{hci/nordic => ll_sw/nordic/hci}/hci_vendor.h (100%) rename subsys/bluetooth/controller/{hci/openisa => ll_sw/openisa/hci}/hci_vendor.h (100%) diff --git a/subsys/bluetooth/controller/CMakeLists.txt b/subsys/bluetooth/controller/CMakeLists.txt index 36d093c8037..42008750d6d 100644 --- a/subsys/bluetooth/controller/CMakeLists.txt +++ b/subsys/bluetooth/controller/CMakeLists.txt @@ -184,13 +184,13 @@ zephyr_library_include_directories_ifdef( zephyr_library_include_directories_ifdef( CONFIG_SOC_COMPATIBLE_NRF ll_sw/nordic - hci/nordic + ll_sw/nordic/hci ) zephyr_library_include_directories_ifdef( CONFIG_SOC_OPENISA_RV32M1 ll_sw/openisa - hci/openisa + ll_sw/openisa/hci ) add_subdirectory_ifdef( diff --git a/subsys/bluetooth/controller/ll_sw/nordic/CMakeLists.txt b/subsys/bluetooth/controller/ll_sw/nordic/CMakeLists.txt index ce73e2f386b..ed2628827b8 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/CMakeLists.txt +++ b/subsys/bluetooth/controller/ll_sw/nordic/CMakeLists.txt @@ -85,6 +85,11 @@ zephyr_library_sources_ifdef( ull/ull_iso_vendor.c ) +zephyr_library_sources_ifdef( + CONFIG_SOC_FAMILY_NORDIC_NRF + hci/hci_vendor.c + ) + zephyr_library_sources( hal/nrf5/cntr.c hal/nrf5/ecb.c diff --git a/subsys/bluetooth/controller/hci/nordic/hci_vendor.c b/subsys/bluetooth/controller/ll_sw/nordic/hci/hci_vendor.c similarity index 100% rename from subsys/bluetooth/controller/hci/nordic/hci_vendor.c rename to subsys/bluetooth/controller/ll_sw/nordic/hci/hci_vendor.c diff --git a/subsys/bluetooth/controller/hci/nordic/hci_vendor.h b/subsys/bluetooth/controller/ll_sw/nordic/hci/hci_vendor.h similarity index 100% rename from subsys/bluetooth/controller/hci/nordic/hci_vendor.h rename to subsys/bluetooth/controller/ll_sw/nordic/hci/hci_vendor.h diff --git a/subsys/bluetooth/controller/hci/openisa/hci_vendor.h b/subsys/bluetooth/controller/ll_sw/openisa/hci/hci_vendor.h similarity index 100% rename from subsys/bluetooth/controller/hci/openisa/hci_vendor.h rename to subsys/bluetooth/controller/ll_sw/openisa/hci/hci_vendor.h From 9aec7af1c52077bc25df60fb353fac007adf77cf Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 4 Mar 2024 11:09:06 +0100 Subject: [PATCH 0060/2402] Bluetooth: Controller: Build hci_vendor.c also for simulation The FICR is also modelled in simulation, but changing this conditional compile was forgotten, so it was only being built for real HW. A test had provided its own version of this function so it would avoid a runtime warning due to the lack of static address. But this needs to be removed as it conflicts with the function provided now always by the nordic controller SW. Signed-off-by: Alberto Escolar Piedras --- .../controller/ll_sw/nordic/CMakeLists.txt | 3 +-- .../bluetooth/df/common/src/hci_vendor_stub.c | 25 ------------------- .../connection_cte_tx_params/CMakeLists.txt | 1 - 3 files changed, 1 insertion(+), 28 deletions(-) delete mode 100644 tests/bluetooth/df/common/src/hci_vendor_stub.c diff --git a/subsys/bluetooth/controller/ll_sw/nordic/CMakeLists.txt b/subsys/bluetooth/controller/ll_sw/nordic/CMakeLists.txt index ed2628827b8..06904eb0094 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/CMakeLists.txt +++ b/subsys/bluetooth/controller/ll_sw/nordic/CMakeLists.txt @@ -85,8 +85,7 @@ zephyr_library_sources_ifdef( ull/ull_iso_vendor.c ) -zephyr_library_sources_ifdef( - CONFIG_SOC_FAMILY_NORDIC_NRF +zephyr_library_sources( hci/hci_vendor.c ) diff --git a/tests/bluetooth/df/common/src/hci_vendor_stub.c b/tests/bluetooth/df/common/src/hci_vendor_stub.c deleted file mode 100644 index d1f7f5f4f48..00000000000 --- a/tests/bluetooth/df/common/src/hci_vendor_stub.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2021 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -/** - * @brief This is a stub of a function that provides static address. - * - * This function is defined to silent warning printed by Host during BT stack initialization due - * to lack of static address stored in controller. - */ -uint8_t hci_vendor_read_static_addr(struct bt_hci_vs_static_addr addrs[], uint8_t size) -{ - /* only one supported */ - ARG_UNUSED(size); - - /* Use some fake address, because it does not matter for test purposes */ - (void)memset(addrs[0].ir, 0x01, sizeof(addrs[0].ir)); - - return 1; -} diff --git a/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt b/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt index d03e6e15ba2..e21effd2a8b 100644 --- a/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt +++ b/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt @@ -10,7 +10,6 @@ project(bluetooth_df_connection_cte_tx_params) FILE(GLOB app_sources src/*.c) SET(common_sources ${CMAKE_CURRENT_SOURCE_DIR}/../common/src/bt_common.c ${CMAKE_CURRENT_SOURCE_DIR}/../common/src/bt_conn_common.c - ${CMAKE_CURRENT_SOURCE_DIR}/../common/src/hci_vendor_stub.c ${CMAKE_CURRENT_SOURCE_DIR}/../common/src/radio_df_stub.c) target_sources(app PRIVATE ${common_sources} ${app_sources}) From 44e0a64a907b5aa1835cdb2376b5c842a45710fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Thu, 29 Feb 2024 10:55:32 +0100 Subject: [PATCH 0061/2402] logging: Fix support for CONFIG_LOG_MSG_APPEND_RO_STRING_LOC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is an Kconfig option which results in RO string locations being appended to the cbprintf package of a log message. Option was not correctly handled, especially optimized API which was recently added did not support that. Restoring support. Signed-off-by: Krzysztof Chruściński --- subsys/logging/log_msg.c | 91 ++++++++++++++++++++++++++++------------ 1 file changed, 64 insertions(+), 27 deletions(-) diff --git a/subsys/logging/log_msg.c b/subsys/logging/log_msg.c index f69c96dd7b0..ef9b777eb69 100644 --- a/subsys/logging/log_msg.c +++ b/subsys/logging/log_msg.c @@ -93,11 +93,13 @@ static void z_log_msg_simple_create(const void *source, uint32_t level, uint32_t /* Package length (in words) is increased by the header. */ size_t plen32 = len + CBPRINTF_DESC_SIZE32; /* Package length in bytes. */ - size_t plen8 = sizeof(uint32_t) * plen32; + size_t plen8 = sizeof(uint32_t) * plen32 + + (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) ? 1 : 0); struct log_msg *msg = z_log_msg_alloc(Z_LOG_MSG_ALIGNED_WLEN(plen8, 0)); union cbprintf_package_hdr package_hdr = { .desc = { - .len = plen32 + .len = plen32, + .ro_str_cnt = IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) ? 1 : 0 } }; @@ -108,6 +110,10 @@ static void z_log_msg_simple_create(const void *source, uint32_t level, uint32_t for (size_t i = 0; i < len; i++) { *package++ = data[i]; } + if (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC)) { + /* fmt string located at index 1 */ + *(uint8_t *)package = 1; + } } struct log_msg_desc desc = { @@ -117,7 +123,6 @@ static void z_log_msg_simple_create(const void *source, uint32_t level, uint32_t }; z_log_msg_finalize(msg, source, desc, NULL); - } void z_impl_z_log_msg_simple_create_0(const void *source, uint32_t level, const char *fmt) @@ -133,20 +138,30 @@ void z_impl_z_log_msg_simple_create_0(const void *source, uint32_t level, const uint32_t plen32 = CBPRINTF_DESC_SIZE32 + 1; union cbprintf_package_hdr hdr = { .desc = { - .len = plen32 + .len = plen32, + .ro_str_cnt = + IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) ? 1 : 0 } }; - uint32_t package[] = { - (uint32_t)(uintptr_t)hdr.raw, - (uint32_t)(uintptr_t)fmt, - }; + uint8_t package[sizeof(uint32_t) * (CBPRINTF_DESC_SIZE32 + 1) + + (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) ? 1 : 0)] + __aligned(sizeof(uint32_t)); + uint32_t *p32 = (uint32_t *)package; + + *p32++ = (uint32_t)(uintptr_t)hdr.raw; + *p32++ = (uint32_t)(uintptr_t)fmt; + if (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC)) { + /* fmt string located at index 1 */ + *(uint8_t *)p32 = 1; + } + struct log_msg_desc desc = { .level = level, - .package_len = plen32 * sizeof(uint32_t), + .package_len = sizeof(package), .data_len = 0, }; - log_frontend_msg(source, desc, (uint8_t *)package, NULL); + log_frontend_msg(source, desc, package, NULL); } } @@ -172,21 +187,31 @@ void z_impl_z_log_msg_simple_create_1(const void *source, uint32_t level, uint32_t plen32 = CBPRINTF_DESC_SIZE32 + 2; union cbprintf_package_hdr hdr = { .desc = { - .len = plen32 + .len = plen32, + .ro_str_cnt = + IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) ? 1 : 0 } }; - uint32_t package[] = { - (uint32_t)(uintptr_t)hdr.raw, - (uint32_t)(uintptr_t)fmt, - arg - }; + uint8_t package[sizeof(uint32_t) * (CBPRINTF_DESC_SIZE32 + 2) + + (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) ? 1 : 0)] + __aligned(sizeof(uint32_t)); + uint32_t *p32 = (uint32_t *)package; + + *p32++ = (uint32_t)(uintptr_t)hdr.raw; + *p32++ = (uint32_t)(uintptr_t)fmt; + *p32++ = arg; + if (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC)) { + /* fmt string located at index 1 */ + *(uint8_t *)p32 = 1; + } + struct log_msg_desc desc = { .level = level, - .package_len = plen32 * sizeof(uint32_t), + .package_len = sizeof(package), .data_len = 0, }; - log_frontend_msg(source, desc, (uint8_t *)package, NULL); + log_frontend_msg(source, desc, package, NULL); } } @@ -212,22 +237,32 @@ void z_impl_z_log_msg_simple_create_2(const void *source, uint32_t level, uint32_t plen32 = CBPRINTF_DESC_SIZE32 + 3; union cbprintf_package_hdr hdr = { .desc = { - .len = plen32 + .len = plen32, + .ro_str_cnt = + IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) ? 1 : 0 } }; - uint32_t package[] = { - [0](uint32_t)(uintptr_t)hdr.raw, - (uint32_t)(uintptr_t)fmt, - arg0, - arg1 - }; + uint8_t package[sizeof(uint32_t) * (CBPRINTF_DESC_SIZE32 + 3) + + (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) ? 1 : 0)] + __aligned(sizeof(uint32_t)); + uint32_t *p32 = (uint32_t *)package; + + *p32++ = (uint32_t)(uintptr_t)hdr.raw; + *p32++ = (uint32_t)(uintptr_t)fmt; + *p32++ = arg0; + *p32++ = arg1; + if (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC)) { + /* fmt string located at index 1 */ + *(uint8_t *)p32 = 1; + } + struct log_msg_desc desc = { .level = level, - .package_len = plen32 * sizeof(uint32_t), + .package_len = sizeof(package), .data_len = 0, }; - log_frontend_msg(source, desc, (uint8_t *)package, NULL); + log_frontend_msg(source, desc, package, NULL); } } @@ -258,6 +293,8 @@ void z_impl_z_log_msg_static_create(const void *source, if (inlen > 0) { uint32_t flags = CBPRINTF_PACKAGE_CONVERT_RW_STR | + (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) ? + CBPRINTF_PACKAGE_CONVERT_KEEP_RO_STR : 0) | (IS_ENABLED(CONFIG_LOG_FMT_SECTION_STRIP) ? 0 : CBPRINTF_PACKAGE_CONVERT_PTR_CHECK); uint16_t strl[4]; From 4d6bce34f74b09efef36335bc33dd4b358d67c4d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Thu, 29 Feb 2024 10:56:53 +0100 Subject: [PATCH 0062/2402] tests: logging: log_api: Validate CONFIG_LOG_MSG_APPEND_RO_STRING_LOC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extended test to validate that RO string locations are appended to the cbprintf package for a log message if Kconfig option is enabled. Signed-off-by: Krzysztof Chruściński --- tests/subsys/logging/log_api/Kconfig | 4 ++++ tests/subsys/logging/log_api/src/main.c | 10 ++++++++-- tests/subsys/logging/log_api/src/mock_backend.c | 11 +++++++++++ tests/subsys/logging/log_api/src/mock_frontend.c | 8 ++++++++ tests/subsys/logging/log_api/testcase.yaml | 2 ++ 5 files changed, 33 insertions(+), 2 deletions(-) diff --git a/tests/subsys/logging/log_api/Kconfig b/tests/subsys/logging/log_api/Kconfig index 89a0fefa76f..a09d5854981 100644 --- a/tests/subsys/logging/log_api/Kconfig +++ b/tests/subsys/logging/log_api/Kconfig @@ -5,4 +5,8 @@ module = SAMPLE_MODULE module-str = Test logging API source "subsys/logging/Kconfig.template.log_config" +config TEST_LOG_MSG_APPEND_RO_STRING_LOC + bool "Append read-only string locations to the package" + select LOG_MSG_APPEND_RO_STRING_LOC + source "Kconfig.zephyr" diff --git a/tests/subsys/logging/log_api/src/main.c b/tests/subsys/logging/log_api/src/main.c index 7771dd8b766..1de5180f239 100644 --- a/tests/subsys/logging/log_api/src/main.c +++ b/tests/subsys/logging/log_api/src/main.c @@ -27,11 +27,14 @@ LOG_MODULE_REGISTER(test, CONFIG_SAMPLE_MODULE_LOG_LEVEL); #define LOG_SIMPLE_MSG_LEN \ ROUND_UP(sizeof(struct log_msg) + \ sizeof(struct cbprintf_package_hdr_ext) + \ - sizeof(int), CBPRINTF_PACKAGE_ALIGNMENT) + sizeof(int) + (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) ? 1 : 0), \ + CBPRINTF_PACKAGE_ALIGNMENT) #else #define LOG_SIMPLE_MSG_LEN \ ROUND_UP(sizeof(struct log_msg) + \ - sizeof(struct cbprintf_package_hdr_ext), CBPRINTF_PACKAGE_ALIGNMENT) + sizeof(struct cbprintf_package_hdr_ext) + \ + (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) ? 1 : 0), \ + CBPRINTF_PACKAGE_ALIGNMENT) #endif #ifdef CONFIG_LOG_TIMESTAMP_64BIT @@ -366,6 +369,9 @@ static size_t get_long_hexdump(void) */ extra_hexdump_sz = sizeof(int); } + if (IS_ENABLED(CONFIG_TEST_LOG_MSG_APPEND_RO_STRING_LOC)) { + extra_msg_sz += sizeof(uint8_t); /* Location of format string. */ + } return CONFIG_LOG_BUFFER_SIZE - /* First message */ diff --git a/tests/subsys/logging/log_api/src/mock_backend.c b/tests/subsys/logging/log_api/src/mock_backend.c index 2da4907dfde..e9cd66978ac 100644 --- a/tests/subsys/logging/log_api/src/mock_backend.c +++ b/tests/subsys/logging/log_api/src/mock_backend.c @@ -167,8 +167,10 @@ static void process(const struct log_backend *const backend, size_t len; uint8_t *data; + struct cbprintf_package_desc *package_desc; data = log_msg_get_data(&msg->log, &len); + zassert_equal(exp->data_len, len); if (exp->data_len <= sizeof(exp->data)) { zassert_equal(memcmp(data, exp->data, len), 0); @@ -178,6 +180,15 @@ static void process(const struct log_backend *const backend, struct test_str s = { .str = str }; data = log_msg_get_package(&msg->log, &len); + package_desc = (struct cbprintf_package_desc *)data; + + if (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC)) { + /* If RO string locations are appended there is always at least 1: format string. */ + zassert_true(package_desc->ro_str_cnt > 0); + } else { + zassert_equal(package_desc->ro_str_cnt, 0); + } + len = cbpprintf(out, &s, data); if (len > 0) { str[len] = '\0'; diff --git a/tests/subsys/logging/log_api/src/mock_frontend.c b/tests/subsys/logging/log_api/src/mock_frontend.c index 171b8907367..f74a441f294 100644 --- a/tests/subsys/logging/log_api/src/mock_frontend.c +++ b/tests/subsys/logging/log_api/src/mock_frontend.c @@ -88,6 +88,7 @@ void log_frontend_msg(const void *source, uint8_t *package, const void *data) { struct mock_log_backend_msg *exp_msg = &mock.exp_msgs[mock.msg_proc_idx]; + struct cbprintf_package_desc *package_desc = (struct cbprintf_package_desc *)package; if (mock.do_check == false) { return; @@ -99,6 +100,13 @@ void log_frontend_msg(const void *source, return; } + if (IS_ENABLED(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC)) { + /* If RO string locations are appended there is always at least 1: format string. */ + zassert_true(package_desc->ro_str_cnt > 0); + } else { + zassert_equal(package_desc->ro_str_cnt, 0); + } + zassert_equal(desc.level, exp_msg->level); zassert_equal(desc.domain, exp_msg->domain_id); diff --git a/tests/subsys/logging/log_api/testcase.yaml b/tests/subsys/logging/log_api/testcase.yaml index b30b61163fd..05dbd311a66 100644 --- a/tests/subsys/logging/log_api/testcase.yaml +++ b/tests/subsys/logging/log_api/testcase.yaml @@ -32,6 +32,7 @@ tests: extra_configs: - CONFIG_LOG_MODE_DEFERRED=y - CONFIG_SAMPLE_MODULE_LOG_LEVEL_DBG=y + - CONFIG_TEST_LOG_MSG_APPEND_RO_STRING_LOC=y logging.deferred.api.printk: extra_configs: @@ -105,6 +106,7 @@ tests: extra_configs: - CONFIG_LOG_FRONTEND=y - CONFIG_LOG_MODE_DEFERRED=y + - CONFIG_TEST_LOG_MSG_APPEND_RO_STRING_LOC=y logging.frontend.rt_filtering: extra_configs: From 23049346e0dfbbcd7238d80c83eb244ddc3b01a3 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Thu, 29 Feb 2024 09:38:55 +0100 Subject: [PATCH 0063/2402] Bluetooth: Mesh: Fix dev key selection in SAR Cfg Client For dev key encrypiton, BT_MESH_KEY_DEV_REMOTE should be used instead of BT_MESH_KEY_DEV regardless of whether the destination is a local element or remote. BT_MESH_MSG_CTX_INIT_DEV macro selects correct key. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/sar_cfg_cli.c | 28 ++++------------------------ 1 file changed, 4 insertions(+), 24 deletions(-) diff --git a/subsys/bluetooth/mesh/sar_cfg_cli.c b/subsys/bluetooth/mesh/sar_cfg_cli.c index 52239c95be4..9a243f722c9 100644 --- a/subsys/bluetooth/mesh/sar_cfg_cli.c +++ b/subsys/bluetooth/mesh/sar_cfg_cli.c @@ -129,12 +129,7 @@ int bt_mesh_sar_cfg_cli_transmitter_get(uint16_t net_idx, uint16_t addr, struct bt_mesh_sar_tx *rsp) { BT_MESH_MODEL_BUF_DEFINE(msg, OP_SAR_CFG_TX_GET, 0); - struct bt_mesh_msg_ctx ctx = { - .net_idx = net_idx, - .app_idx = BT_MESH_KEY_DEV, - .addr = addr, - .send_ttl = BT_MESH_TTL_DEFAULT, - }; + struct bt_mesh_msg_ctx ctx = BT_MESH_MSG_CTX_INIT_DEV(net_idx, addr); int err; err = bt_mesh_msg_ack_ctx_prepare(&cli->ack_ctx, OP_SAR_CFG_TX_STATUS, addr, rsp); @@ -159,12 +154,7 @@ int bt_mesh_sar_cfg_cli_transmitter_set(uint16_t net_idx, uint16_t addr, struct bt_mesh_sar_tx *rsp) { BT_MESH_MODEL_BUF_DEFINE(msg, OP_SAR_CFG_TX_SET, BT_MESH_SAR_TX_LEN); - struct bt_mesh_msg_ctx ctx = { - .net_idx = net_idx, - .app_idx = BT_MESH_KEY_DEV, - .addr = addr, - .send_ttl = BT_MESH_TTL_DEFAULT, - }; + struct bt_mesh_msg_ctx ctx = BT_MESH_MSG_CTX_INIT_DEV(net_idx, addr); int err; err = bt_mesh_msg_ack_ctx_prepare(&cli->ack_ctx, OP_SAR_CFG_TX_STATUS, addr, rsp); @@ -189,12 +179,7 @@ int bt_mesh_sar_cfg_cli_receiver_get(uint16_t net_idx, uint16_t addr, struct bt_mesh_sar_rx *rsp) { BT_MESH_MODEL_BUF_DEFINE(msg, OP_SAR_CFG_RX_GET, 0); - struct bt_mesh_msg_ctx ctx = { - .net_idx = net_idx, - .app_idx = BT_MESH_KEY_DEV, - .addr = addr, - .send_ttl = BT_MESH_TTL_DEFAULT, - }; + struct bt_mesh_msg_ctx ctx = BT_MESH_MSG_CTX_INIT_DEV(net_idx, addr); int err; err = bt_mesh_msg_ack_ctx_prepare(&cli->ack_ctx, OP_SAR_CFG_RX_STATUS, addr, rsp); @@ -219,12 +204,7 @@ int bt_mesh_sar_cfg_cli_receiver_set(uint16_t net_idx, uint16_t addr, struct bt_mesh_sar_rx *rsp) { BT_MESH_MODEL_BUF_DEFINE(msg, OP_SAR_CFG_RX_SET, BT_MESH_SAR_RX_LEN); - struct bt_mesh_msg_ctx ctx = { - .net_idx = net_idx, - .app_idx = BT_MESH_KEY_DEV, - .addr = addr, - .send_ttl = BT_MESH_TTL_DEFAULT, - }; + struct bt_mesh_msg_ctx ctx = BT_MESH_MSG_CTX_INIT_DEV(net_idx, addr); int err; err = bt_mesh_msg_ack_ctx_prepare(&cli->ack_ctx, OP_SAR_CFG_RX_STATUS, addr, rsp); From 6976ad82ea26b023965a745a105291890f7eb462 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Mon, 26 Feb 2024 21:50:05 +0100 Subject: [PATCH 0064/2402] Bluetooth: BAP: Add can_recv to bt_bap_ep_info Similar to the can_send, the can_recv field indicates whether or not this endpoint can receive data. This commit also slightly refactors and optimized how the can_send field is set. Signed-off-by: Emil Gydesen --- include/zephyr/bluetooth/audio/bap.h | 3 +++ subsys/bluetooth/audio/bap_stream.c | 30 ++++++++++++++-------------- 2 files changed, 18 insertions(+), 15 deletions(-) diff --git a/include/zephyr/bluetooth/audio/bap.h b/include/zephyr/bluetooth/audio/bap.h index f61accde211..9584a459c87 100644 --- a/include/zephyr/bluetooth/audio/bap.h +++ b/include/zephyr/bluetooth/audio/bap.h @@ -400,6 +400,9 @@ struct bt_bap_ep_info { /** @brief True if the stream associated with the endpoint is able to send data */ bool can_send; + /** @brief True if the stream associated with the endpoint is able to receive data */ + bool can_recv; + /** Pointer to paired endpoint if the endpoint is part of a bidirectional CIS, * otherwise NULL */ diff --git a/subsys/bluetooth/audio/bap_stream.c b/subsys/bluetooth/audio/bap_stream.c index 1e132c57f00..b10d32303fd 100644 --- a/subsys/bluetooth/audio/bap_stream.c +++ b/subsys/bluetooth/audio/bap_stream.c @@ -112,25 +112,25 @@ int bt_bap_ep_get_info(const struct bt_bap_ep *ep, struct bt_bap_ep_info *info) } info->can_send = false; + info->can_recv = false; if (IS_ENABLED(CONFIG_BT_AUDIO_TX) && ep->stream != NULL) { if (IS_ENABLED(CONFIG_BT_BAP_BROADCAST_SOURCE) && bt_bap_ep_is_broadcast_src(ep)) { info->can_send = true; - } else if (IS_ENABLED(CONFIG_BT_CONN) && ep->stream->conn != NULL) { - struct bt_conn_info conn_info; - uint8_t role; - int err; - - err = bt_conn_get_info(ep->stream->conn, &conn_info); - if (err != 0) { - LOG_DBG("Could not get conn info: %d", err); - - return err; + } else if (IS_ENABLED(CONFIG_BT_BAP_BROADCAST_SINK) && + bt_bap_ep_is_broadcast_snk(ep)) { + info->can_recv = true; + } else if (IS_ENABLED(CONFIG_BT_BAP_UNICAST_CLIENT) && + bt_bap_ep_is_unicast_client(ep)) { + /* dir is not initialized before the connection is set */ + if (ep->stream->conn != NULL) { + info->can_send = dir == BT_AUDIO_DIR_SINK; + info->can_recv = dir == BT_AUDIO_DIR_SOURCE; } - - role = conn_info.role; - if ((role == BT_CONN_ROLE_CENTRAL && dir == BT_AUDIO_DIR_SINK) || - (role == BT_CONN_ROLE_PERIPHERAL && dir == BT_AUDIO_DIR_SOURCE)) { - info->can_send = true; + } else if (IS_ENABLED(CONFIG_BT_BAP_UNICAST_SERVER)) { + /* dir is not initialized before the connection is set */ + if (ep->stream->conn != NULL) { + info->can_send = dir == BT_AUDIO_DIR_SOURCE; + info->can_recv = dir == BT_AUDIO_DIR_SINK; } } } From 55bd06b03e913eed4377d02ee05da412e3ac233a Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 27 Feb 2024 09:57:17 +0100 Subject: [PATCH 0065/2402] tests: bsim: Bluetooth: Add bcast validation of bt_bap_ep_get_info The broadcast sink and broadcast source will now use and verify the info returned by bt_bap_ep_get_info. Signed-off-by: Emil Gydesen --- .../audio/src/bap_broadcast_sink_test.c | 34 +++++++++++++++++++ .../audio/src/bap_broadcast_source_test.c | 34 +++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c index 9dd143f59a5..03c2073746b 100644 --- a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c +++ b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c @@ -498,6 +498,40 @@ static void validate_stream_codec_cfg(const struct bt_bap_stream *stream) static void started_cb(struct bt_bap_stream *stream) { + struct bt_bap_ep_info info; + int err; + + err = bt_bap_ep_get_info(stream->ep, &info); + if (err != 0) { + FAIL("Failed to get EP info: %d\n", err); + return; + } + + if (info.state != BT_BAP_EP_STATE_STREAMING) { + FAIL("Unexpected EP state: %d\n", info.state); + return; + } + + if (info.dir != BT_AUDIO_DIR_SINK) { + FAIL("Unexpected info.dir: %d\n", info.dir); + return; + } + + if (info.can_send) { + FAIL("info.can_send is true\n"); + return; + } + + if (!info.can_recv) { + FAIL("info.can_recv is false\n"); + return; + } + + if (info.paired_ep != NULL) { + FAIL("Unexpected info.paired_ep: %p\n", info.paired_ep); + return; + } + printk("Stream %p started\n", stream); k_sem_give(&sem_started); diff --git a/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c b/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c index ccd26af4e9c..7548147241b 100644 --- a/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c +++ b/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c @@ -39,6 +39,40 @@ static K_SEM_DEFINE(sem_stopped, 0U, ARRAY_SIZE(broadcast_source_streams)); static void started_cb(struct bt_bap_stream *stream) { + struct bt_bap_ep_info info; + int err; + + err = bt_bap_ep_get_info(stream->ep, &info); + if (err != 0) { + FAIL("Failed to get EP info: %d\n", err); + return; + } + + if (info.state != BT_BAP_EP_STATE_STREAMING) { + FAIL("Unexpected EP state: %d\n", info.state); + return; + } + + if (info.dir != BT_AUDIO_DIR_SOURCE) { + FAIL("Unexpected info.dir: %d\n", info.dir); + return; + } + + if (!info.can_send) { + FAIL("info.can_send is false\n"); + return; + } + + if (info.can_recv) { + FAIL("info.can_recv is true\n"); + return; + } + + if (info.paired_ep != NULL) { + FAIL("Unexpected info.paired_ep: %p\n", info.paired_ep); + return; + } + printk("Stream %p started\n", stream); k_sem_give(&sem_started); } From 9ae0dbc2753ffa85ac2b5706877540cd968ac555 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Mon, 12 Feb 2024 22:05:21 +0530 Subject: [PATCH 0066/2402] boards: arm: rak5010_nrf52840: fix qspi settings fix QSPI NOR flash is25wp064a input page programming to 32h as 38h isn't functional. Also adjust the frequency to max possible value from nRF52 as 32MHz as the flash supports upto 133MHz. Signed-off-by: Parthiban Nallathambi --- boards/rak/rak5010/rak5010_nrf52840.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/rak/rak5010/rak5010_nrf52840.dts b/boards/rak/rak5010/rak5010_nrf52840.dts index 9d6f5df44a3..eeba2a5e20b 100644 --- a/boards/rak/rak5010/rak5010_nrf52840.dts +++ b/boards/rak/rak5010/rak5010_nrf52840.dts @@ -114,9 +114,9 @@ is25wp064a: is25wp064a@0 { compatible = "nordic,qspi-nor"; reg = <0>; - writeoc = "pp4io"; + writeoc = "pp4o"; readoc = "read4io"; - sck-frequency = <16000000>; + sck-frequency = <32000000>; jedec-id = [9d 70 17]; size = <67108864>; has-dpd; From f764763f005c20a534a7f52663c48c6b7cc5cd3c Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Mon, 12 Feb 2024 22:10:01 +0530 Subject: [PATCH 0067/2402] samples: littlefs: add qspi nodes for rak5010_nrf52840 add qspi nodes with size of 64MB to LFS with automount. Signed-off-by: Parthiban Nallathambi --- .../fs/littlefs/boards/rak5010_nrf52840.conf | 10 +++++ .../littlefs/boards/rak5010_nrf52840.overlay | 37 +++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 samples/subsys/fs/littlefs/boards/rak5010_nrf52840.conf create mode 100644 samples/subsys/fs/littlefs/boards/rak5010_nrf52840.overlay diff --git a/samples/subsys/fs/littlefs/boards/rak5010_nrf52840.conf b/samples/subsys/fs/littlefs/boards/rak5010_nrf52840.conf new file mode 100644 index 00000000000..5ad368d450d --- /dev/null +++ b/samples/subsys/fs/littlefs/boards/rak5010_nrf52840.conf @@ -0,0 +1,10 @@ +# +# Copyright (c) 2024 Linumiz +# SPDX-License-Identifier: Apache-2.0 +# + +# Need this when storage is on flash +CONFIG_MPU_ALLOW_FLASH_WRITE=y + +CONFIG_NORDIC_QSPI_NOR=y +CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096 diff --git a/samples/subsys/fs/littlefs/boards/rak5010_nrf52840.overlay b/samples/subsys/fs/littlefs/boards/rak5010_nrf52840.overlay new file mode 100644 index 00000000000..c82338c518e --- /dev/null +++ b/samples/subsys/fs/littlefs/boards/rak5010_nrf52840.overlay @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024 Linumiz + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/delete-node/ &storage_partition; + +/ { + fstab { + compatible = "zephyr,fstab"; + lfs1: lfs1 { + compatible = "zephyr,fstab,littlefs"; + mount-point = "/lfs1"; + partition = <&lfs1_part>; + automount; + read-size = <16>; + prog-size = <16>; + cache-size = <64>; + lookahead-size = <32>; + block-cycles = <512>; + }; + }; +}; + +&is25wp064a { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + lfs1_part: partition@0 { + label = "storage"; + reg = <0x00000000 DT_SIZE_M(8)>; + }; + }; +}; From 63d28e56f90e06968554638c93f934af6739780f Mon Sep 17 00:00:00 2001 From: Mykyta Poturai Date: Wed, 28 Feb 2024 16:14:00 +0200 Subject: [PATCH 0068/2402] fs: explicitly initialize fs_file_t and fs_dir_t C++ compilers forbid usage of compound literals with -Wpedantic enabled. They also forbid the usage of designated initializers for standards lower than c++20. So switch to explicit initialization, that would not make compilers angry at us. Signed-off-by: Mykyta Poturai --- include/zephyr/fs/fs.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/zephyr/fs/fs.h b/include/zephyr/fs/fs.h index bb051804b6c..73782134c8a 100644 --- a/include/zephyr/fs/fs.h +++ b/include/zephyr/fs/fs.h @@ -231,7 +231,9 @@ struct fs_statvfs { */ static inline void fs_file_t_init(struct fs_file_t *zfp) { - *zfp = (struct fs_file_t){ 0 }; + zfp->filep = NULL; + zfp->mp = NULL; + zfp->flags = 0; } /** @@ -245,7 +247,8 @@ static inline void fs_file_t_init(struct fs_file_t *zfp) */ static inline void fs_dir_t_init(struct fs_dir_t *zdp) { - *zdp = (struct fs_dir_t){ 0 }; + zdp->dirp = NULL; + zdp->mp = NULL; } /** From 5bd03fd41b576fc936616f6cbae9120661e32395 Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Thu, 29 Feb 2024 11:12:08 +0800 Subject: [PATCH 0069/2402] Bluetooth: HFP: Fix session pointer invalid issue The dlc->session is invalid in the callback hfp_hf_disconnected. The behavior of obtaining an ACL connection handle through an invalid pointer is unknown. Add a field "struct bt_conn *acl" to "struct bt_hfp_hf". Save acl connect handle to "struct bt_hfp_hf::acl" in function bt_hfp_hf_accept. Signed-off-by: Lyle Zhu --- subsys/bluetooth/host/hfp_hf.c | 14 ++++++++------ subsys/bluetooth/host/hfp_internal.h | 2 ++ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/subsys/bluetooth/host/hfp_hf.c b/subsys/bluetooth/host/hfp_hf.c index 0bb2398e537..4b0e82ee3c7 100644 --- a/subsys/bluetooth/host/hfp_hf.c +++ b/subsys/bluetooth/host/hfp_hf.c @@ -228,7 +228,7 @@ void ag_indicator_handle_values(struct at_client *hf_at, uint32_t index, uint32_t value) { struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at); - struct bt_conn *conn = hf->rfcomm_dlc.session->br_chan.chan.conn; + struct bt_conn *conn = hf->acl; LOG_DBG("Index :%u, Value :%u", index, value); @@ -351,7 +351,7 @@ int ciev_handle(struct at_client *hf_at) int ring_handle(struct at_client *hf_at) { struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at); - struct bt_conn *conn = hf->rfcomm_dlc.session->br_chan.chan.conn; + struct bt_conn *conn = hf->acl; if (bt_hf->ring_indication) { bt_hf->ring_indication(conn); @@ -405,7 +405,7 @@ int cmd_complete(struct at_client *hf_at, enum at_result result, enum at_cme cme_err) { struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at); - struct bt_conn *conn = hf->rfcomm_dlc.session->br_chan.chan.conn; + struct bt_conn *conn = hf->acl; struct bt_hfp_hf_cmd_complete cmd = { 0 }; LOG_DBG(""); @@ -448,7 +448,7 @@ int cmee_finish(struct at_client *hf_at, enum at_result result, static void slc_completed(struct at_client *hf_at) { struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at); - struct bt_conn *conn = hf->rfcomm_dlc.session->br_chan.chan.conn; + struct bt_conn *conn = hf->acl; if (bt_hf->connected) { bt_hf->connected(conn); @@ -561,7 +561,7 @@ static struct bt_hfp_hf *bt_hfp_hf_lookup_bt_conn(struct bt_conn *conn) for (i = 0; i < ARRAY_SIZE(bt_hfp_hf_pool); i++) { struct bt_hfp_hf *hf = &bt_hfp_hf_pool[i]; - if (hf->rfcomm_dlc.session->br_chan.chan.conn == conn) { + if (hf->acl == conn) { return hf; } } @@ -622,7 +622,8 @@ static void hfp_hf_connected(struct bt_rfcomm_dlc *dlc) static void hfp_hf_disconnected(struct bt_rfcomm_dlc *dlc) { - struct bt_conn *conn = dlc->session->br_chan.chan.conn; + struct bt_hfp_hf *hf = CONTAINER_OF(dlc, struct bt_hfp_hf, rfcomm_dlc); + struct bt_conn *conn = hf->acl; LOG_DBG("hf disconnected!"); if (bt_hf->disconnected) { @@ -658,6 +659,7 @@ static int bt_hfp_hf_accept(struct bt_conn *conn, struct bt_rfcomm_dlc **dlc) continue; } + hf->acl = conn; hf->at.buf = hf->hf_buffer; hf->at.buf_max_len = HF_MAX_BUF_LEN; diff --git a/subsys/bluetooth/host/hfp_internal.h b/subsys/bluetooth/host/hfp_internal.h index 100e82de424..933e2578d26 100644 --- a/subsys/bluetooth/host/hfp_internal.h +++ b/subsys/bluetooth/host/hfp_internal.h @@ -46,6 +46,8 @@ struct bt_hfp_hf { struct bt_rfcomm_dlc rfcomm_dlc; + /* ACL connection handle */ + struct bt_conn *acl; char hf_buffer[HF_MAX_BUF_LEN]; struct at_client at; uint32_t hf_features; From 1261745b2c19db453f9972018d031ab66a7827c8 Mon Sep 17 00:00:00 2001 From: Jakub Rzeszutko Date: Thu, 29 Feb 2024 03:11:04 +0100 Subject: [PATCH 0070/2402] shell: fix shell_stop command Added missing condition to check if log backend is configured before calling the function: z_shell_log_backend_disable. Without this, in some configurations, a compilation error appeared due to calling a non-existent function. Fixes: #69555 Signed-off-by: Jakub Rzeszutko --- subsys/shell/shell.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/subsys/shell/shell.c b/subsys/shell/shell.c index acbe9ea11a9..9cbd8a7158a 100644 --- a/subsys/shell/shell.c +++ b/subsys/shell/shell.c @@ -1465,7 +1465,9 @@ int shell_stop(const struct shell *sh) state_set(sh, SHELL_STATE_INITIALIZED); - z_shell_log_backend_disable(sh->log_backend); + if (IS_ENABLED(CONFIG_SHELL_LOG_BACKEND)) { + z_shell_log_backend_disable(sh->log_backend); + } return 0; } From ad9f2c599ba6bb00eddc9794f41929e774eb61a0 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Fri, 5 Jan 2024 15:00:02 +0000 Subject: [PATCH 0071/2402] input: kbd_matrix: skip column with empty mask The active key mask can be used for supporting multiple keyboard layouts with a single firmware. A possible use case is to support keyboard with or without a numpad, in which case an entire set of columns may be missing. Add a check to detect this condition and skip scanning that column entirely if no keys are defined in it. Signed-off-by: Fabio Baltieri --- drivers/input/input_kbd_matrix.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/input/input_kbd_matrix.c b/drivers/input/input_kbd_matrix.c index 095a9bb0cfd..47d8cfc07e1 100644 --- a/drivers/input/input_kbd_matrix.c +++ b/drivers/input/input_kbd_matrix.c @@ -88,6 +88,11 @@ static bool input_kbd_matrix_scan(const struct device *dev) kbd_row_t key_event = 0U; for (int col = 0; col < cfg->col_size; col++) { + if (cfg->actual_key_mask != NULL && + cfg->actual_key_mask[col] == 0) { + continue; + } + input_kbd_matrix_drive_column(dev, col); /* Allow the matrix to stabilize before reading it */ From 5046229bb94cd2683ec1022848991d387152a0d2 Mon Sep 17 00:00:00 2001 From: Christopher Radzik Date: Tue, 27 Feb 2024 15:09:43 -0600 Subject: [PATCH 0072/2402] drivers: clock_control: Fix STM32H5 MCO2 support Add STM32H5 to the list of dependencies for CLOCK_STM32_MCO2_DIV. Signed-off-by: Christopher Radzik --- drivers/clock_control/Kconfig.stm32 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32 index cccbe5e2e74..c5f4f273646 100644 --- a/drivers/clock_control/Kconfig.stm32 +++ b/drivers/clock_control/Kconfig.stm32 @@ -253,6 +253,7 @@ config CLOCK_STM32_MCO2_DIV depends on !CLOCK_STM32_MCO2_SRC_NOCLOCK && (\ SOC_SERIES_STM32F4X || \ SOC_SERIES_STM32F7X || \ + SOC_SERIES_STM32H5X || \ SOC_SERIES_STM32H7X \ ) default 1 From 1d4121d97b9001d43f028d908f6616ee79bd7059 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Mon, 4 Mar 2024 15:26:41 +0200 Subject: [PATCH 0073/2402] doc: porting: HW model: fix an issue link It pointed to the wrong issue. Signed-off-by: Tomi Fontanilles --- doc/hardware/porting/board_porting.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/hardware/porting/board_porting.rst b/doc/hardware/porting/board_porting.rst index 107a284563b..04ccc33bb1c 100644 --- a/doc/hardware/porting/board_porting.rst +++ b/doc/hardware/porting/board_porting.rst @@ -31,7 +31,7 @@ refer to the documentation in Zephyr v3.6.0 (or earlier) for information on the previous, now obsolete, hardware model. More information about the rationale, development and concepts behind the new -model can be found in the :github:`original issue <51381>`, the +model can be found in the :github:`original issue <51831>`, the :github:`original Pull Request <50305>` and, for a complete set of changes introduced, the `hardware model v2 commit`_. From e2ff2a88ba76b1c4bd855c3f7035b810a0cb48f5 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Fri, 3 Nov 2023 13:47:54 +0100 Subject: [PATCH 0074/2402] sysbuild: include HWMv2 Kconfig in sysbuild Including HWMv2 Kconfig in sysbuild allows sysbuild to introduce configuration options or defaults based on selected board and SoC. Signed-off-by: Torsten Rasmussen --- share/sysbuild/CMakeLists.txt | 4 ++-- share/sysbuild/Kconfig | 2 ++ share/sysbuild/Kconfig.v1 | 5 +++++ share/sysbuild/Kconfig.v2 | 32 ++++++++++++++++++++++++++++++++ 4 files changed, 41 insertions(+), 2 deletions(-) create mode 100644 share/sysbuild/Kconfig.v1 create mode 100644 share/sysbuild/Kconfig.v2 diff --git a/share/sysbuild/CMakeLists.txt b/share/sysbuild/CMakeLists.txt index 9133fe874ef..4a6fde214d5 100644 --- a/share/sysbuild/CMakeLists.txt +++ b/share/sysbuild/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2023 Nordic Semiconductor +# Copyright (c) 2021-2023 Nordic Semiconductor # # SPDX-License-Identifier: Apache-2.0 @@ -19,7 +19,7 @@ list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/cmake/modules) # List of Zephyr and sysbuild CMake modules we need for sysbuild. # Note: sysbuild_kconfig will internally load kconfig CMake module. set(zephyr_modules extensions - sysbuild_extensions python west root zephyr_module boards shields + sysbuild_extensions python west root zephyr_module boards shields hwm_v2 sysbuild_kconfig native_simulator_sb_extensions ) diff --git a/share/sysbuild/Kconfig b/share/sysbuild/Kconfig index b08db20e5df..9f1a1cf30af 100644 --- a/share/sysbuild/Kconfig +++ b/share/sysbuild/Kconfig @@ -2,6 +2,8 @@ # # SPDX-License-Identifier: Apache-2.0 +rsource "Kconfig.$(HWM_SCHEME)" + comment "Sysbuild image configuration" osource "$(BOARD_DIR)/Kconfig.sysbuild" diff --git a/share/sysbuild/Kconfig.v1 b/share/sysbuild/Kconfig.v1 new file mode 100644 index 00000000000..58191354bb7 --- /dev/null +++ b/share/sysbuild/Kconfig.v1 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +# Intentionally left empty as sysbuild Kconfig doesn't support hw model v1. diff --git a/share/sysbuild/Kconfig.v2 b/share/sysbuild/Kconfig.v2 new file mode 100644 index 00000000000..aa3a656e13f --- /dev/null +++ b/share/sysbuild/Kconfig.v2 @@ -0,0 +1,32 @@ +# Copyright (c) 2023 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + string + default "$(BOARD)" + help + This option holds the name of the board and is used to locate the files + related to the board in the source tree (under boards/). + The Board is the first location where we search for a linker.ld file, + if not found we look for the linker file in + soc/// + +config BOARD_REVISION + def_string "$BOARD_REVISION" + help + If the BOARD has a revision field set, this is the revision. + Otherwise, it is the empty string. For example, if BOARD is + "plank@foo", this option will be "foo". If BOARD is "plank", + this option will be the empty string. + +config BOARD_DEPRECATED_RELEASE + string + help + This hidden option is set in the board configuration and indicates + the Zephyr release that the board configuration will be removed. + When set, any build for that board will generate a clearly visible + deprecation warning. + +source "boards/Kconfig.$(HWM_SCHEME)" +source "soc/Kconfig.$(HWM_SCHEME)" From 148e6f09357e3f2ca5e96c8306f6f38dbc74107b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 4 Mar 2024 10:47:17 +0100 Subject: [PATCH 0075/2402] snippets: nordic-ppr-ram: fix board identifier Missed conversion to HWMv2. Signed-off-by: Gerard Marull-Paretas --- snippets/nordic-ppr-ram/snippet.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/snippets/nordic-ppr-ram/snippet.yml b/snippets/nordic-ppr-ram/snippet.yml index 0d6039af2e5..2b5b987d3e6 100644 --- a/snippets/nordic-ppr-ram/snippet.yml +++ b/snippets/nordic-ppr-ram/snippet.yml @@ -3,6 +3,6 @@ append: EXTRA_DTC_OVERLAY_FILE: nordic-ppr-ram.overlay boards: - nrf54h20pdk_nrf54h20_cpuapp: + nrf54h20pdk/nrf54h20/cpuapp: append: EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20pdk_nrf54h20_cpuapp.overlay From 64f18bd55429b424bbbbe4921a2d9d8fea0bed35 Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Sat, 2 Mar 2024 02:06:16 +0800 Subject: [PATCH 0076/2402] MAINTAINERS: add myself as riscv collaborator specifically for the intc_plic. Signed-off-by: Yong Cong Sin --- MAINTAINERS.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index f36e18a5528..b242d9028e1 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2859,6 +2859,7 @@ RISCV arch: - edersondisouza - carlocaione - npitre + - ycsin files: - arch/riscv/ - boards/qemu/riscv*/ From 4c8fafdf357cb2cf2747874f9fe8813ab8790151 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 1 Mar 2024 17:33:33 +0200 Subject: [PATCH 0077/2402] MAINTAINERS: Add pdgendt as networking collaborator Adding Pieter De Gendt (pdgendt) as a collaborator to the networking subsystem. Signed-off-by: Jukka Rissanen --- MAINTAINERS.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index b242d9028e1..470f7c9f422 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2536,6 +2536,7 @@ Networking: - rlubos - jukkar collaborators: + - pdgendt - tbursztyka - ssharks files: From cbbd79a8c968ce85b6bc22a268f3be0c10144eaa Mon Sep 17 00:00:00 2001 From: Kevin Townsend Date: Fri, 1 Mar 2024 12:27:02 +0100 Subject: [PATCH 0078/2402] maintainers: Update Arm maintainer and collabs Updates the maintainer for Arm and cleans up the collab list. Signed-off-by: Kevin Townsend --- MAINTAINERS.yml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 470f7c9f422..3f7911e0593 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -150,16 +150,14 @@ ARC arch: ARM arch: status: maintained maintainers: - - microbuilder + - ithinuel collaborators: + - microbuilder - carlocaione - galak - MaureenHelm - stephanosio - bbolen - - povergoing - - ithinuel - - sgrrzhf files: - arch/arm/ - arch/arm/core/offsets/ From 6f6480c90aef91f532dfce2bb58df7fc8217cfb6 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Mon, 4 Mar 2024 09:21:30 +0000 Subject: [PATCH 0079/2402] maintainers: Update Kconfig paths Updates the Kconfig path to include 2 missed files Signed-off-by: Jamie McCrae --- MAINTAINERS.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 3f7911e0593..e2e40904416 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -522,7 +522,7 @@ Board/SoC configuration: - "57300" files: - soc/Kconfig* - - boards/Kconfig + - boards/Kconfig* labels: - "area: Board/SoC configuration" From eb1f5fec0c0eaf89d0a8f46a0f0b10b6ca24abb7 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Mon, 4 Mar 2024 11:35:42 -0600 Subject: [PATCH 0080/2402] soc: nxp: Fix issues caught in CI from HWMv2 port During HWMv2 porting there was some build fails missed from typos in the RT1064 and RT11XX series, fix these. Signed-off-by: Declan Snyder --- soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c | 2 ++ soc/nxp/imxrt/imxrt11xx/power.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c b/soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c index 42d1110b3ca..9020b9bf809 100644 --- a/soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c +++ b/soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c @@ -214,6 +214,7 @@ void clock_full_power(void) #if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash))) clock_set_div(kCLOCK_FlexspiDiv, flexspi_div); clock_set_mux(kCLOCK_FlexspiMux, 3); +#endif #if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash))) clock_set_div(kCLOCK_Flexspi2Div, flexspi_div); clock_set_mux(kCLOCK_Flexspi2Mux, 1); @@ -261,6 +262,7 @@ void clock_low_power(void) clock_set_div(kCLOCK_FlexspiDiv, 0); /* FLEXSPI1 mux to PLL3 PFD0 BYPASS */ clock_set_mux(kCLOCK_FlexspiMux, 3); +#endif #if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash))) clock_set_div(kCLOCK_Flexspi2Div, 0); /* FLEXSPI2 mux to PLL3 PFD0 BYPASS */ diff --git a/soc/nxp/imxrt/imxrt11xx/power.c b/soc/nxp/imxrt/imxrt11xx/power.c index 871a7d809a3..af7ee9d0f18 100644 --- a/soc/nxp/imxrt/imxrt11xx/power.c +++ b/soc/nxp/imxrt/imxrt11xx/power.c @@ -9,7 +9,7 @@ #include #include #include -#include "power_rt11xx.h" +#include "power.h" #include LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); From f1f6b72c76d6407164172335b06effa26a33c5c9 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 4 Mar 2024 12:39:37 -0500 Subject: [PATCH 0081/2402] ci: run twister/west tests on collab/release branches Make sure we run twister and west unit tests on branches, to avoid breakage when introducing changes to those branches. Signed-off-by: Anas Nashif --- .github/workflows/twister_tests.yml | 1 + .github/workflows/twister_tests_blackbox.yml | 2 ++ .github/workflows/west_cmds.yml | 2 ++ 3 files changed, 5 insertions(+) diff --git a/.github/workflows/twister_tests.yml b/.github/workflows/twister_tests.yml index 92de15b81b0..70db179a98c 100644 --- a/.github/workflows/twister_tests.yml +++ b/.github/workflows/twister_tests.yml @@ -8,6 +8,7 @@ on: branches: - main - v*-branch + - collab-* paths: - 'scripts/pylib/**' - 'scripts/twister' diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index cdb11d95286..14413ced5b8 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -7,6 +7,8 @@ on: pull_request: branches: - main + - collab-* + - v*-branch paths: - 'scripts/pylib/twister/**' - 'scripts/twister' diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml index 25a5fc88fd6..96eda2089f7 100644 --- a/.github/workflows/west_cmds.yml +++ b/.github/workflows/west_cmds.yml @@ -8,6 +8,7 @@ on: branches: - main - v*-branch + - collab-* paths: - 'scripts/west-commands.yml' - 'scripts/west_commands/**' @@ -16,6 +17,7 @@ on: branches: - main - v*-branch + - collab-* paths: - 'scripts/west-commands.yml' - 'scripts/west_commands/**' From 668f6d87ec49b6ad204224868fb83254921fecae Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 4 Mar 2024 11:04:00 -0500 Subject: [PATCH 0082/2402] twister: tests: fix tests by mocking platform attributes We were missing mocking for normalized_name and board detection was not working correctly after moving to hwmv2. Signed-off-by: Anas Nashif --- scripts/pylib/twister/twisterlib/platform.py | 1 + .../boards/1_level/2_level/board.yml | 14 +++++ .../1_level/2_level/board_config_1.yaml | 0 .../1_level/2_level/board_config_2.yaml | 0 .../1_level/2_level/board_config_3.yaml | 0 scripts/tests/twister/test_harness.py | 9 ++++ scripts/tests/twister/test_testinstance.py | 1 + scripts/tests/twister/test_testplan.py | 54 +++++++++++++++++++ 8 files changed, 79 insertions(+) create mode 100644 scripts/tests/twister/test_data/boards/1_level/2_level/board.yml rename scripts/tests/twister/test_data/{board_config => boards}/1_level/2_level/board_config_1.yaml (100%) rename scripts/tests/twister/test_data/{board_config => boards}/1_level/2_level/board_config_2.yaml (100%) rename scripts/tests/twister/test_data/{board_config => boards}/1_level/2_level/board_config_3.yaml (100%) diff --git a/scripts/pylib/twister/twisterlib/platform.py b/scripts/pylib/twister/twisterlib/platform.py index 91c1df83428..769876cf05a 100644 --- a/scripts/pylib/twister/twisterlib/platform.py +++ b/scripts/pylib/twister/twisterlib/platform.py @@ -23,6 +23,7 @@ def __init__(self): """ self.name = "" + self.normalized_name = "" self.twister = True # if no RAM size is specified by the board, take a default of 128K self.ram = 128 diff --git a/scripts/tests/twister/test_data/boards/1_level/2_level/board.yml b/scripts/tests/twister/test_data/boards/1_level/2_level/board.yml new file mode 100644 index 00000000000..863e42047b6 --- /dev/null +++ b/scripts/tests/twister/test_data/boards/1_level/2_level/board.yml @@ -0,0 +1,14 @@ +boards: + + - name: demo_board_1 + vendor: zephyr + socs: + - name: unit_testing + - name: demo_board_2 + vendor: zephyr + socs: + - name: unit_testing + - name: demo_board_3 + vendor: zephyr + socs: + - name: unit_testing diff --git a/scripts/tests/twister/test_data/board_config/1_level/2_level/board_config_1.yaml b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_1.yaml similarity index 100% rename from scripts/tests/twister/test_data/board_config/1_level/2_level/board_config_1.yaml rename to scripts/tests/twister/test_data/boards/1_level/2_level/board_config_1.yaml diff --git a/scripts/tests/twister/test_data/board_config/1_level/2_level/board_config_2.yaml b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_2.yaml similarity index 100% rename from scripts/tests/twister/test_data/board_config/1_level/2_level/board_config_2.yaml rename to scripts/tests/twister/test_data/boards/1_level/2_level/board_config_2.yaml diff --git a/scripts/tests/twister/test_data/board_config/1_level/2_level/board_config_3.yaml b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_3.yaml similarity index 100% rename from scripts/tests/twister/test_data/board_config/1_level/2_level/board_config_3.yaml rename to scripts/tests/twister/test_data/boards/1_level/2_level/board_config_3.yaml diff --git a/scripts/tests/twister/test_harness.py b/scripts/tests/twister/test_harness.py index 10a6e295d6f..f117a77e3f5 100644 --- a/scripts/tests/twister/test_harness.py +++ b/scripts/tests/twister/test_harness.py @@ -77,6 +77,7 @@ def test_robot_configure(): #Arrange mock_platform = mock.Mock() mock_platform.name = "mock_platform" + mock_platform.normalized_name = "mock_platform" mock_testsuite = mock.Mock(id = 'id', testcases = []) mock_testsuite.name = "mock_testsuite" @@ -100,6 +101,7 @@ def test_robot_handle(): #Arrange mock_platform = mock.Mock() mock_platform.name = "mock_platform" + mock_platform.normalized_name = "mock_platform" mock_testsuite = mock.Mock(id = 'id', testcases = []) mock_testsuite.name = "mock_testsuite" @@ -140,6 +142,7 @@ def test_robot_run_robot_test(caplog, exp_out, returncode, expected_status): mock_platform = mock.Mock() mock_platform.name = "mock_platform" + mock_platform.normalized_name = "mock_platform" mock_testsuite = mock.Mock(id = 'id', testcases = [mock.Mock()]) mock_testsuite.name = "mock_testsuite" @@ -184,6 +187,7 @@ def test_console_configure(type, num_patterns): #Arrange mock_platform = mock.Mock() mock_platform.name = "mock_platform" + mock_platform.normalized_name = "mock_platform" mock_testsuite = mock.Mock(id = 'id', testcases = []) mock_testsuite.name = "mock_testsuite" @@ -222,6 +226,7 @@ def test_console_configure(type, num_patterns): def test_console_handle(line_type, ordered_val, exp_state, line, exp_fault, exp_capture): mock_platform = mock.Mock() mock_platform.name = "mock_platform" + mock_platform.normalized_name = "mock_platform" mock_testsuite = mock.Mock(id = 'id', testcases = []) mock_testsuite.name = "mock_testsuite" @@ -277,6 +282,7 @@ def test_pytest__generate_parameters_for_hardware(pty_value, hardware_value): #Arrange mock_platform = mock.Mock() mock_platform.name = "mock_platform" + mock_platform.normalized_name = "mock_platform" mock_testsuite = mock.Mock(id = 'id', testcases = []) mock_testsuite.name = "mock_testsuite" @@ -359,6 +365,7 @@ def test_pytest_run(caplog): mock_platform = mock.Mock() mock_platform.name = "mock_platform" + mock_platform.normalized_name = "mock_platform" mock_testsuite = mock.Mock(id = 'id', testcases = [], source_dir = 'source_dir', harness_config = {}) mock_testsuite.name = "mock_testsuite" @@ -416,6 +423,7 @@ def test_test_handle(caplog, exp_out, line, exp_suite_name, exp_status, ztest, s line = line mock_platform = mock.Mock() mock_platform.name = "mock_platform" + mock_platform.normalized_name = "mock_platform" mock_testsuite = mock.Mock(id = 'id', testcases = []) mock_testsuite.name = "mock_testsuite" @@ -445,6 +453,7 @@ def test_test_handle(caplog, exp_out, line, exp_suite_name, exp_status, ztest, s def gtest(tmp_path): mock_platform = mock.Mock() mock_platform.name = "mock_platform" + mock_platform.normalized_name = "mock_platform" mock_testsuite = mock.Mock() mock_testsuite.name = "mock_testsuite" mock_testsuite.detailed_test_id = True diff --git a/scripts/tests/twister/test_testinstance.py b/scripts/tests/twister/test_testinstance.py index 52c51b2b278..849421bddf0 100644 --- a/scripts/tests/twister/test_testinstance.py +++ b/scripts/tests/twister/test_testinstance.py @@ -207,6 +207,7 @@ def test_testinstance_init(all_testsuites_dict, class_testplan, platforms_list, testsuite = class_testplan.testsuites.get(testsuite_path) testsuite.detailed_test_id = detailed_test_id class_testplan.platforms = platforms_list + print(class_testplan.platforms) platform = class_testplan.get_platform("demo_board_2") testinstance = TestInstance(testsuite, platform, class_testplan.env.outdir) diff --git a/scripts/tests/twister/test_testplan.py b/scripts/tests/twister/test_testplan.py index 488c39ddf73..1f765c475c1 100644 --- a/scripts/tests/twister/test_testplan.py +++ b/scripts/tests/twister/test_testplan.py @@ -728,6 +728,18 @@ def test_testplan_load( testplan.platforms[9].name = 'lt-p2' testplan.platforms[10].name = 'lt-p3' testplan.platforms[11].name = 'lt-p4' + testplan.platforms[0].normalized_name = 't-p1' + testplan.platforms[1].normalized_name = 't-p2' + testplan.platforms[2].normalized_name = 't-p3' + testplan.platforms[3].normalized_name = 't-p4' + testplan.platforms[4].normalized_name = 'ts-p1' + testplan.platforms[5].normalized_name = 'ts-p2' + testplan.platforms[6].normalized_name = 'ts-p3' + testplan.platforms[7].normalized_name = 'ts-p4' + testplan.platforms[8].normalized_name = 'lt-p1' + testplan.platforms[9].normalized_name = 'lt-p2' + testplan.platforms[10].normalized_name = 'lt-p3' + testplan.platforms[11].normalized_name = 'lt-p4' testplan.generate_subset = mock.Mock() testplan.apply_filters = mock.Mock() @@ -1098,6 +1110,21 @@ def test_testplan_add_configurations( tmp_p1_dir = tmp_arch1_dir / 'p1' tmp_p1_dir.mkdir() + p1e1_bs_yaml = """\ +boards: + + - name: ple1 + vendor: zephyr + socs: + - name: unit_testing + - name: ple2 + vendor: zephyr + socs: + - name: unit_testing +""" + p1e1_yamlfile = tmp_p1_dir / 'board.yml' + p1e1_yamlfile.write_text(p1e1_bs_yaml) + p1e1_yaml = """\ identifier: p1e1 name: Platform 1 Edition 1 @@ -1126,6 +1153,21 @@ def test_testplan_add_configurations( tmp_p2_dir = tmp_arch1_dir / 'p2' tmp_p2_dir.mkdir() + p2_bs_yaml = """\ +boards: + + - name: p2 + vendor: zephyr + socs: + - name: unit_testing + - name: p2_2 + vendor: zephyr + socs: + - name: unit_testing +""" + p2_yamlfile = tmp_p2_dir / 'board.yml' + p2_yamlfile.write_text(p2_bs_yaml) + p2_yaml = """\ identifier: p2 name: Platform 2 @@ -1164,6 +1206,17 @@ def test_testplan_add_configurations( tmp_p3_dir = tmp_arch2_dir / 'p3' tmp_p3_dir.mkdir() + p3_bs_yaml = """\ +boards: + + - name: p3 + vendor: zephyr + socs: + - name: unit_testing +""" + p3_yamlfile = tmp_p3_dir / 'board.yml' + p3_yamlfile.write_text(p3_bs_yaml) + p3_yaml = """\ identifier: p3 name: Platform 3 @@ -1375,6 +1428,7 @@ def test_testplan_load_from_file(caplog, device_testing, expected_tfilter): def get_platform(name): p = mock.Mock() p.name = name + p.normalized_name = name return p ts1tc1 = mock.Mock() From e2f3912c5a633569d2de45dcf7ce66df16b77632 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 4 Mar 2024 03:15:20 +0000 Subject: [PATCH 0083/2402] x86: revert removing soc.h from atom soc This was part of the mega hwmv2 commit. Looks like hpet drivers heavily relies on soc.h. Reverting this for now while we look for a proper fix and remove reliance on soc.h for drivers. Signed-off-by: Anas Nashif --- arch/x86/core/early_serial.c | 1 + drivers/counter/counter_cmos.c | 7 ++-- drivers/disk/nvme/nvme_controller.c | 1 + drivers/timer/hpet.c | 2 + soc/intel/atom/soc.h | 60 +++++++++++++++++++++++++++++ subsys/bluetooth/host/hci_core.c | 1 + 6 files changed, 68 insertions(+), 4 deletions(-) create mode 100644 soc/intel/atom/soc.h diff --git a/arch/x86/core/early_serial.c b/arch/x86/core/early_serial.c index a2abafbf05e..3a0bc7465e1 100644 --- a/arch/x86/core/early_serial.c +++ b/arch/x86/core/early_serial.c @@ -8,6 +8,7 @@ #include #include #include +#include #if DT_PROP_OR(DT_CHOSEN(zephyr_console), io_mapped, 0) != 0 diff --git a/drivers/counter/counter_cmos.c b/drivers/counter/counter_cmos.c index 00645bc71b0..3edd718b9fe 100644 --- a/drivers/counter/counter_cmos.c +++ b/drivers/counter/counter_cmos.c @@ -11,12 +11,11 @@ * crossing clock domains (no pun intended). Use accordingly. */ -#include +#define DT_DRV_COMPAT motorola_mc146818 + #include #include -#include - -#define DT_DRV_COMPAT motorola_mc146818 +#include /* The "CMOS" device is accessed via an address latch and data port. */ diff --git a/drivers/disk/nvme/nvme_controller.c b/drivers/disk/nvme/nvme_controller.c index e58a1baa734..699df325add 100644 --- a/drivers/disk/nvme/nvme_controller.c +++ b/drivers/disk/nvme/nvme_controller.c @@ -13,6 +13,7 @@ LOG_MODULE_REGISTER(nvme, CONFIG_NVME_LOG_LEVEL); #include +#include #include #include diff --git a/drivers/timer/hpet.c b/drivers/timer/hpet.c index de2abf757f8..8a7134a762e 100644 --- a/drivers/timer/hpet.c +++ b/drivers/timer/hpet.c @@ -14,6 +14,8 @@ #include +#include + /** * @file * @brief HPET (High Precision Event Timers) driver diff --git a/soc/intel/atom/soc.h b/soc/intel/atom/soc.h new file mode 100644 index 00000000000..199820fa7bd --- /dev/null +++ b/soc/intel/atom/soc.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2010-2015, Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros for the ia32 platform + * + * This header file is used to specify and describe board-level aspects for + * the 'ia32' platform. + */ + +#ifndef __SOC_H_ +#define __SOC_H_ + +#include + +#ifndef _ASMLANGUAGE +#include +#include +#endif + +/* PCI definitions */ +/* FIXME: The values below copied from generic ia32 soc, we need to get the + * correct numbers for Atom and the minnowboard + * + * This is added now to get basic enumeration of devices and verify that PCI + * driver is functional. + */ +#define PCI_BUS_NUMBERS 1 + +#define PCI_CTRL_ADDR_REG 0xCF8 +#define PCI_CTRL_DATA_REG 0xCFC + +#define PCI_INTA 1 +#define PCI_INTB 2 +#define PCI_INTC 3 +#define PCI_INTD 4 + +/** + * + * @brief Convert PCI interrupt PIN to IRQ + * + * @return IRQ number, -1 if the result is incorrect + * + */ + +static inline int pci_pin2irq(int bus, int dev, int pin) +{ + ARG_UNUSED(bus); + + if ((pin < PCI_INTA) || (pin > PCI_INTD)) { + return -1; + } + return 10 + (((pin + dev - 1) >> 1) & 1); +} + +#endif /* __SOC_H_ */ diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c index 8406feef897..0c6a96e2aec 100644 --- a/subsys/bluetooth/host/hci_core.c +++ b/subsys/bluetooth/host/hci_core.c @@ -18,6 +18,7 @@ #include #include #include +#include #include From a14ba6a253892903d3e72d10c283adcd2087840c Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 4 Mar 2024 12:53:27 +0000 Subject: [PATCH 0084/2402] intel_adsp: do not use SOC_TOOLCHAIN_NAME for include path SOC_TOOLCHAIN_NAME was used instead of the SoC name for setting include path, so all SoCs were using the same path. Originally this was relying on SoC (before hwmv2), so reverting back to using the SoC name instead and renaming directories as well. Signed-off-by: Anas Nashif --- soc/intel/intel_adsp/ace/CMakeLists.txt | 2 +- .../ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_boot.h | 0 .../{intel_ace15_mtpm => ace15_mtpm}/adsp_comm_widget.h | 0 .../include/{intel_ace15_mtpm => ace15_mtpm}/adsp_interrupt.h | 0 .../include/{intel_ace15_mtpm => ace15_mtpm}/adsp_ipc_regs.h | 0 .../include/{intel_ace15_mtpm => ace15_mtpm}/adsp_memory.h | 0 .../{intel_ace15_mtpm => ace15_mtpm}/adsp_memory_regions.h | 0 .../ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_power.h | 0 .../ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_shim.h | 0 .../include/{intel_ace15_mtpm => ace15_mtpm}/adsp_watchdog.h | 0 .../{intel_ace15_mtpm => ace15_mtpm}/dmic_regs_ace1x.h | 0 .../ace/include/{intel_ace20_lnl => ace20_lnl}/adsp_boot.h | 0 .../include/{intel_ace20_lnl => ace20_lnl}/adsp_interrupt.h | 0 .../include/{intel_ace20_lnl => ace20_lnl}/adsp_ipc_regs.h | 0 .../ace/include/{intel_ace20_lnl => ace20_lnl}/adsp_memory.h | 0 .../{intel_ace20_lnl => ace20_lnl}/adsp_memory_regions.h | 0 .../ace/include/{intel_ace20_lnl => ace20_lnl}/adsp_power.h | 0 .../ace/include/{intel_ace20_lnl => ace20_lnl}/adsp_shim.h | 0 .../include/{intel_ace20_lnl => ace20_lnl}/dmic_regs_ace2x.h | 0 soc/intel/intel_adsp/ace/include/dmic_regs.h | 4 ++-- soc/intel/intel_adsp/cavs/CMakeLists.txt | 2 +- .../cavs/include/{intel_tgl_adsp => cavs25}/adsp_imr_layout.h | 0 .../cavs/include/{intel_tgl_adsp => cavs25}/adsp_ipc_regs.h | 0 .../cavs/include/{intel_tgl_adsp => cavs25}/adsp_memory.h | 0 .../cavs/include/{intel_tgl_adsp => cavs25}/adsp_shim.h | 0 .../cavs/include/{intel_tgl_adsp => cavs25}/dmic_regs.h | 0 26 files changed, 4 insertions(+), 4 deletions(-) rename soc/intel/intel_adsp/ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_boot.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_comm_widget.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_interrupt.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_ipc_regs.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_memory.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_memory_regions.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_power.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_shim.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace15_mtpm => ace15_mtpm}/adsp_watchdog.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace15_mtpm => ace15_mtpm}/dmic_regs_ace1x.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace20_lnl => ace20_lnl}/adsp_boot.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace20_lnl => ace20_lnl}/adsp_interrupt.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace20_lnl => ace20_lnl}/adsp_ipc_regs.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace20_lnl => ace20_lnl}/adsp_memory.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace20_lnl => ace20_lnl}/adsp_memory_regions.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace20_lnl => ace20_lnl}/adsp_power.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace20_lnl => ace20_lnl}/adsp_shim.h (100%) rename soc/intel/intel_adsp/ace/include/{intel_ace20_lnl => ace20_lnl}/dmic_regs_ace2x.h (100%) rename soc/intel/intel_adsp/cavs/include/{intel_tgl_adsp => cavs25}/adsp_imr_layout.h (100%) rename soc/intel/intel_adsp/cavs/include/{intel_tgl_adsp => cavs25}/adsp_ipc_regs.h (100%) rename soc/intel/intel_adsp/cavs/include/{intel_tgl_adsp => cavs25}/adsp_memory.h (100%) rename soc/intel/intel_adsp/cavs/include/{intel_tgl_adsp => cavs25}/adsp_shim.h (100%) rename soc/intel/intel_adsp/cavs/include/{intel_tgl_adsp => cavs25}/dmic_regs.h (100%) diff --git a/soc/intel/intel_adsp/ace/CMakeLists.txt b/soc/intel/intel_adsp/ace/CMakeLists.txt index 78d3d5b9d1e..919e7993427 100644 --- a/soc/intel/intel_adsp/ace/CMakeLists.txt +++ b/soc/intel/intel_adsp/ace/CMakeLists.txt @@ -15,7 +15,7 @@ zephyr_library_sources( ) zephyr_include_directories(include) -zephyr_include_directories(include/${SOC_TOOLCHAIN_NAME}) +zephyr_include_directories(include/${CONFIG_SOC}) zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget.c) zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget_messages.c) diff --git a/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h b/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_boot.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h rename to soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_boot.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_comm_widget.h b/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_comm_widget.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_comm_widget.h rename to soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_comm_widget.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_interrupt.h b/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_interrupt.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_interrupt.h rename to soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_interrupt.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_ipc_regs.h b/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_ipc_regs.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_ipc_regs.h rename to soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_ipc_regs.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h b/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_memory.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h rename to soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_memory.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h b/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_memory_regions.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h rename to soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_memory_regions.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h b/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_power.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h rename to soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_power.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h b/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_shim.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h rename to soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_shim.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_watchdog.h b/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_watchdog.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_watchdog.h rename to soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_watchdog.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/dmic_regs_ace1x.h b/soc/intel/intel_adsp/ace/include/ace15_mtpm/dmic_regs_ace1x.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/dmic_regs_ace1x.h rename to soc/intel/intel_adsp/ace/include/ace15_mtpm/dmic_regs_ace1x.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_boot.h b/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_boot.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_boot.h rename to soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_boot.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_interrupt.h b/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_interrupt.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_interrupt.h rename to soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_interrupt.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_ipc_regs.h b/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_ipc_regs.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_ipc_regs.h rename to soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_ipc_regs.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h b/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_memory.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h rename to soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_memory.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory_regions.h b/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_memory_regions.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory_regions.h rename to soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_memory_regions.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h b/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_power.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h rename to soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_power.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_shim.h b/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_shim.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_shim.h rename to soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_shim.h diff --git a/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/dmic_regs_ace2x.h b/soc/intel/intel_adsp/ace/include/ace20_lnl/dmic_regs_ace2x.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/intel_ace20_lnl/dmic_regs_ace2x.h rename to soc/intel/intel_adsp/ace/include/ace20_lnl/dmic_regs_ace2x.h diff --git a/soc/intel/intel_adsp/ace/include/dmic_regs.h b/soc/intel/intel_adsp/ace/include/dmic_regs.h index 56a1c090209..201c3b2d6df 100644 --- a/soc/intel/intel_adsp/ace/include/dmic_regs.h +++ b/soc/intel/intel_adsp/ace/include/dmic_regs.h @@ -348,9 +348,9 @@ /* Digital Mic Shim Registers */ #ifdef CONFIG_SOC_INTEL_ACE20_LNL -#include +#include #elif CONFIG_SOC_INTEL_ACE15_MTPM -#include "intel_ace15_mtpm/dmic_regs_ace1x.h" +#include #else #error "Unknown SoC" #endif diff --git a/soc/intel/intel_adsp/cavs/CMakeLists.txt b/soc/intel/intel_adsp/cavs/CMakeLists.txt index 5c253147aee..fdf8200fa6e 100644 --- a/soc/intel/intel_adsp/cavs/CMakeLists.txt +++ b/soc/intel/intel_adsp/cavs/CMakeLists.txt @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(include) -zephyr_include_directories(include/${SOC_TOOLCHAIN_NAME}) +zephyr_include_directories(include/${CONFIG_SOC}) zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) zephyr_library_sources( diff --git a/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_imr_layout.h b/soc/intel/intel_adsp/cavs/include/cavs25/adsp_imr_layout.h similarity index 100% rename from soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_imr_layout.h rename to soc/intel/intel_adsp/cavs/include/cavs25/adsp_imr_layout.h diff --git a/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_ipc_regs.h b/soc/intel/intel_adsp/cavs/include/cavs25/adsp_ipc_regs.h similarity index 100% rename from soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_ipc_regs.h rename to soc/intel/intel_adsp/cavs/include/cavs25/adsp_ipc_regs.h diff --git a/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h b/soc/intel/intel_adsp/cavs/include/cavs25/adsp_memory.h similarity index 100% rename from soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h rename to soc/intel/intel_adsp/cavs/include/cavs25/adsp_memory.h diff --git a/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h b/soc/intel/intel_adsp/cavs/include/cavs25/adsp_shim.h similarity index 100% rename from soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h rename to soc/intel/intel_adsp/cavs/include/cavs25/adsp_shim.h diff --git a/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h b/soc/intel/intel_adsp/cavs/include/cavs25/dmic_regs.h similarity index 100% rename from soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h rename to soc/intel/intel_adsp/cavs/include/cavs25/dmic_regs.h From 7d676c23319460e1e56b2a88614014f0d956108a Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Sat, 10 Feb 2024 10:47:18 +0000 Subject: [PATCH 0085/2402] input: pat912x: add a bunch of settings Add devicetree based settings for resolution, axis inversion and sleep mode enable. Keep the resolution setting in its own function so it can be called by the application again in runtime if needed. Signed-off-by: Fabio Baltieri --- drivers/input/input_pat912x.c | 90 +++++++++++++++++++++++ dts/bindings/input/pixart,pat912x.yaml | 32 ++++++++ include/zephyr/input/input_pat912x.h | 22 ++++++ tests/drivers/build_all/input/app.overlay | 6 ++ 4 files changed, 150 insertions(+) create mode 100644 include/zephyr/input/input_pat912x.h diff --git a/drivers/input/input_pat912x.c b/drivers/input/input_pat912x.c index 616984ddac5..be47d1d8dd2 100644 --- a/drivers/input/input_pat912x.c +++ b/drivers/input/input_pat912x.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -47,6 +48,10 @@ LOG_MODULE_REGISTER(input_pat912x, CONFIG_INPUT_LOG_LEVEL); #define WRITE_PROTECT_ENABLE 0x00 #define WRITE_PROTECT_DISABLE 0x5a #define MOTION_STATUS_MOTION BIT(7) +#define RES_SCALING_FACTOR 5 +#define RES_MAX (UINT8_MAX * RES_SCALING_FACTOR) +#define OPERATION_MODE_SLEEP_1_EN BIT(4) +#define OPERATION_MODE_SLEEP_12_EN (BIT(4) | BIT(3)) #define PAT912X_DATA_SIZE_BITS 12 @@ -57,6 +62,12 @@ struct pat912x_config { struct gpio_dt_spec motion_gpio; int32_t axis_x; int32_t axis_y; + int16_t res_x_cpi; + int16_t res_y_cpi; + bool invert_x; + bool invert_y; + bool sleep1_enable; + bool sleep2_enable; }; struct pat912x_data { @@ -102,6 +113,13 @@ static void pat912x_motion_work_handler(struct k_work *work) x = sign_extend(x, PAT912X_DATA_SIZE_BITS - 1); y = sign_extend(y, PAT912X_DATA_SIZE_BITS - 1); + if (cfg->invert_x) { + x *= -1; + } + if (cfg->invert_y) { + y *= -1; + } + LOG_DBG("x=%4d y=%4d", x, y); if (cfg->axis_x >= 0) { @@ -128,6 +146,41 @@ static void pat912x_motion_handler(const struct device *gpio_dev, k_work_submit(&data->motion_work); } +int pat912x_set_resolution(const struct device *dev, + int16_t res_x_cpi, int16_t res_y_cpi) +{ + const struct pat912x_config *cfg = dev->config; + int ret; + + if (res_x_cpi >= 0) { + if (!IN_RANGE(res_x_cpi, 0, RES_MAX)) { + LOG_ERR("res_x_cpi out of range: %d", res_x_cpi); + return -EINVAL; + } + + ret = i2c_reg_write_byte_dt(&cfg->i2c, PAT912X_RES_X, + res_x_cpi / RES_SCALING_FACTOR); + if (ret < 0) { + return ret; + } + } + + if (res_y_cpi >= 0) { + if (!IN_RANGE(res_y_cpi, 0, RES_MAX)) { + LOG_ERR("res_y_cpi out of range: %d", res_y_cpi); + return -EINVAL; + } + + ret = i2c_reg_write_byte_dt(&cfg->i2c, PAT912X_RES_Y, + res_y_cpi / RES_SCALING_FACTOR); + if (ret < 0) { + return ret; + } + } + + return 0; +} + static int pat912x_configure(const struct device *dev) { const struct pat912x_config *cfg = dev->config; @@ -156,6 +209,29 @@ static int pat912x_configure(const struct device *dev) return ret; } + ret = pat912x_set_resolution(dev, cfg->res_x_cpi, cfg->res_y_cpi); + if (ret < 0) { + return ret; + } + + if (cfg->sleep1_enable && cfg->sleep2_enable) { + ret = i2c_reg_update_byte_dt(&cfg->i2c, + PAT912X_OPERATION_MODE, + OPERATION_MODE_SLEEP_12_EN, + OPERATION_MODE_SLEEP_12_EN); + if (ret < 0) { + return ret; + } + } else if (cfg->sleep1_enable) { + ret = i2c_reg_update_byte_dt(&cfg->i2c, + PAT912X_OPERATION_MODE, + OPERATION_MODE_SLEEP_12_EN, + OPERATION_MODE_SLEEP_1_EN); + if (ret < 0) { + return ret; + } + } + return 0; } @@ -249,11 +325,25 @@ static int pat912x_pm_action(const struct device *dev, #endif #define PAT912X_INIT(n) \ + BUILD_ASSERT(IN_RANGE(DT_INST_PROP(n, res_x_cpi), 0, RES_MAX), \ + "invalid res-x-cpy"); \ + BUILD_ASSERT(IN_RANGE(DT_INST_PROP(n, res_y_cpi), 0, RES_MAX), \ + "invalid res-y-cpy"); \ + BUILD_ASSERT(DT_INST_PROP(n, sleep1_enable) || \ + !DT_INST_PROP(n, sleep2_enable), \ + "invalid sleep configuration"); \ + \ static const struct pat912x_config pat912x_cfg_##n = { \ .i2c = I2C_DT_SPEC_INST_GET(n), \ .motion_gpio = GPIO_DT_SPEC_INST_GET(n, motion_gpios), \ .axis_x = DT_INST_PROP_OR(n, zephyr_axis_x, -1), \ .axis_y = DT_INST_PROP_OR(n, zephyr_axis_y, -1), \ + .res_x_cpi = DT_INST_PROP_OR(n, res_x_cpi, -1), \ + .res_y_cpi = DT_INST_PROP_OR(n, res_y_cpi, -1), \ + .invert_x = DT_INST_PROP(n, invert_x), \ + .invert_y = DT_INST_PROP(n, invert_y), \ + .sleep1_enable = DT_INST_PROP(n, sleep1_enable), \ + .sleep2_enable = DT_INST_PROP(n, sleep2_enable), \ }; \ \ static struct pat912x_data pat912x_data_##n; \ diff --git a/dts/bindings/input/pixart,pat912x.yaml b/dts/bindings/input/pixart,pat912x.yaml index 0a50161032c..354e265c021 100644 --- a/dts/bindings/input/pixart,pat912x.yaml +++ b/dts/bindings/input/pixart,pat912x.yaml @@ -25,3 +25,35 @@ properties: description: | The input code for the Y axis to report for the device, typically any of INPUT_REL_*. No report produced for the device Y axis if unspecified. + + res-x-cpi: + type: int + description: | + CPI resolution for the X axis, range 0 to 1275, rounded down to the + closest supported value in increments of 5. + + res-y-cpi: + type: int + description: | + CPI resolution for the Y axis, range 0 to 1275, rounded down to the + closest supported value in increments of 5. + + invert-x: + type: boolean + description: | + Invert X axis values. + + invert-y: + type: boolean + description: | + Invert Y axis values. + + sleep1-enable: + type: boolean + description: | + Enable sleep1 mode. + + sleep2-enable: + type: boolean + description: | + Enable sleep2 mode, only valid if sleep1 is also enabled. diff --git a/include/zephyr/input/input_pat912x.h b/include/zephyr/input/input_pat912x.h new file mode 100644 index 00000000000..8cbb738d118 --- /dev/null +++ b/include/zephyr/input/input_pat912x.h @@ -0,0 +1,22 @@ +/* + * Copyright 2024 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_INPUT_PAT912X_H_ +#define ZEPHYR_INCLUDE_INPUT_PAT912X_H_ + +/** + * @brief Set resolution on a pat912x device + * + * @param dev pat912x device. + * @param res_x_cpi CPI resolution for the X axis, 0 to 1275, -1 to keep the + * current value. + * @param res_y_cpi CPI resolution for the Y axis, 0 to 1275, -1 to keep the + * current value. + */ +int pat912x_set_resolution(const struct device *dev, + int16_t res_x_cpi, int16_t res_y_cpi); + +#endif /* ZEPHYR_INCLUDE_INPUT_PAT912X_H_ */ diff --git a/tests/drivers/build_all/input/app.overlay b/tests/drivers/build_all/input/app.overlay index dc1d2375397..6cfaae7066b 100644 --- a/tests/drivers/build_all/input/app.overlay +++ b/tests/drivers/build_all/input/app.overlay @@ -204,6 +204,12 @@ motion-gpios = <&test_gpio 0 0>; zephyr,axis-x = <0>; zephyr,axis-y = <1>; + res-x-cpi = <0>; + res-y-cpi = <0>; + invert-x; + invert-y; + sleep1-enable; + sleep2-enable; }; }; From 9fc9eb5ddb905cb654a7cd9d9c247192a92d62c6 Mon Sep 17 00:00:00 2001 From: Jonathon Penix Date: Tue, 27 Feb 2024 15:41:05 -0800 Subject: [PATCH 0086/2402] cmake: Set memusage property for lld lld gained support for the --print-memory-usage flag somewhat recently (May 2023). Associate this flag with the memusage property when building with lld, similar to what is done for GNU ld. Signed-off-by: Jonathon Penix --- cmake/linker/lld/linker_flags.cmake | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cmake/linker/lld/linker_flags.cmake b/cmake/linker/lld/linker_flags.cmake index 61e72093c0f..8ed5f7a65b9 100644 --- a/cmake/linker/lld/linker_flags.cmake +++ b/cmake/linker/lld/linker_flags.cmake @@ -4,6 +4,8 @@ # Since lld is a drop in replacement for ld, we can just use ld's flags include(${ZEPHYR_BASE}/cmake/linker/ld/${COMPILER}/linker_flags.cmake OPTIONAL) +check_set_linker_property(TARGET linker PROPERTY memusage "${LINKERFLAGPREFIX},--print-memory-usage") + set_property(TARGET linker PROPERTY no_position_independent "${LINKERFLAGPREFIX},--no-pie") set_property(TARGET linker PROPERTY partial_linking "-r") From fce35569b87835c7a9161b6d2fb10595d5619a78 Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Wed, 20 Dec 2023 15:32:39 +0200 Subject: [PATCH 0087/2402] modules: lvgl: Add support for frame rounder callback Add support for LVGL rounder callback function. Sometimes, either the underlying display controller and/or the LCD host controller might impose restrictions on frame resolution. For instance, the E1394AA65A display model should impose that either axis of a frame be multiple of 2 pixels or the Renesas LCD controller of the DA1469x SoC, should impose that the stride value, number of bytes between consecutive frame lines, be multiple of 4 bytes. Signed-off-by: Ioannis Karachalios --- modules/lvgl/Kconfig | 20 ++++++++++++++++++++ modules/lvgl/include/lvgl_display.h | 4 ++++ modules/lvgl/lvgl_display.c | 26 +++++++++++++++++++++++--- 3 files changed, 47 insertions(+), 3 deletions(-) diff --git a/modules/lvgl/Kconfig b/modules/lvgl/Kconfig index 4bd00b1bc55..dba26b76d89 100644 --- a/modules/lvgl/Kconfig +++ b/modules/lvgl/Kconfig @@ -52,6 +52,10 @@ config LV_Z_LOG_LEVEL default 3 if LV_LOG_LEVEL_USER default 4 if LV_LOG_LEVEL_TRACE +config LV_Z_USE_ROUNDER_CB + bool + default y if LV_Z_AREA_X_ALIGNMENT_WIDTH != 1 || LV_Z_AREA_Y_ALIGNMENT_WIDTH != 1 + config APP_LINK_WITH_LVGL bool "Link 'app' with LVGL" default y @@ -107,6 +111,22 @@ config LV_Z_FLUSH_THREAD_PRIO endif # LV_Z_FLUSH_THREAD +config LV_Z_AREA_X_ALIGNMENT_WIDTH + int "Frame X alignment size" + default 1 + help + Number of pixels, X axis should be rounded to. Should be used to override + the current frame dimensions to meet display and/or LCD host + controller requirements. The value must be power of 2. + +config LV_Z_AREA_Y_ALIGNMENT_WIDTH + int "Frame Y alignment size" + default 1 + help + Number of pixels, Y axis should be rounded to. Should be used to override + the current frame dimensions to meet display and/or LCD host + controller requirements. The value must be power of 2. + rsource "Kconfig.memory" rsource "Kconfig.input" rsource "Kconfig.shell" diff --git a/modules/lvgl/include/lvgl_display.h b/modules/lvgl/include/lvgl_display.h index b031958c736..9a0c14c6831 100644 --- a/modules/lvgl/include/lvgl_display.h +++ b/modules/lvgl/include/lvgl_display.h @@ -49,6 +49,10 @@ int set_lvgl_rendering_cb(lv_disp_drv_t *disp_drv); void lvgl_flush_display(struct lvgl_display_flush *request); +#ifdef CONFIG_LV_Z_USE_ROUNDER_CB +void lvgl_rounder_cb(lv_disp_drv_t *disp_drv, lv_area_t *area); +#endif + #ifdef __cplusplus } #endif diff --git a/modules/lvgl/lvgl_display.c b/modules/lvgl/lvgl_display.c index 8ac4fc97a6a..604cd0078d8 100644 --- a/modules/lvgl/lvgl_display.c +++ b/modules/lvgl/lvgl_display.c @@ -45,6 +45,26 @@ void lvgl_wait_cb(lv_disp_drv_t *disp_drv) #endif /* CONFIG_LV_Z_FLUSH_THREAD */ +#ifdef CONFIG_LV_Z_USE_ROUNDER_CB +void lvgl_rounder_cb(lv_disp_drv_t *disp_drv, lv_area_t *area) +{ +#if CONFIG_LV_Z_AREA_X_ALIGNMENT_WIDTH != 1 + __ASSERT(POPCOUNT(CONFIG_LV_Z_AREA_X_ALIGNMENT_WIDTH) == 1, "Invalid X alignment width"); + + area->x1 &= ~(CONFIG_LV_Z_AREA_X_ALIGNMENT_WIDTH - 1); + area->x2 |= (CONFIG_LV_Z_AREA_X_ALIGNMENT_WIDTH - 1); +#endif +#if CONFIG_LV_Z_AREA_Y_ALIGNMENT_WIDTH != 1 + __ASSERT(POPCOUNT(CONFIG_LV_Z_AREA_Y_ALIGNMENT_WIDTH) == 1, "Invalid Y alignment width"); + + area->y1 &= ~(CONFIG_LV_Z_AREA_Y_ALIGNMENT_WIDTH - 1); + area->y2 |= (CONFIG_LV_Z_AREA_Y_ALIGNMENT_WIDTH - 1); +#endif +} +#else +#define lvgl_rounder_cb NULL +#endif + int set_lvgl_rendering_cb(lv_disp_drv_t *disp_drv) { int err = 0; @@ -57,7 +77,7 @@ int set_lvgl_rendering_cb(lv_disp_drv_t *disp_drv) switch (data->cap.current_pixel_format) { case PIXEL_FORMAT_ARGB_8888: disp_drv->flush_cb = lvgl_flush_cb_32bit; - disp_drv->rounder_cb = NULL; + disp_drv->rounder_cb = lvgl_rounder_cb; #ifdef CONFIG_LV_COLOR_DEPTH_32 disp_drv->set_px_cb = NULL; #else @@ -66,13 +86,13 @@ int set_lvgl_rendering_cb(lv_disp_drv_t *disp_drv) break; case PIXEL_FORMAT_RGB_888: disp_drv->flush_cb = lvgl_flush_cb_24bit; - disp_drv->rounder_cb = NULL; + disp_drv->rounder_cb = lvgl_rounder_cb; disp_drv->set_px_cb = lvgl_set_px_cb_24bit; break; case PIXEL_FORMAT_RGB_565: case PIXEL_FORMAT_BGR_565: disp_drv->flush_cb = lvgl_flush_cb_16bit; - disp_drv->rounder_cb = NULL; + disp_drv->rounder_cb = lvgl_rounder_cb; #ifdef CONFIG_LV_COLOR_DEPTH_16 disp_drv->set_px_cb = NULL; #else From abc07d82e5492288250e42432c3aaf5a456fcc32 Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Wed, 14 Feb 2024 16:17:35 +0200 Subject: [PATCH 0088/2402] boards: da1469x_dk_pro: Update board's default Kconfig Add default LVGL Kconfig for rounder cb. Signed-off-by: Ioannis Karachalios --- boards/renesas/da1469x_dk_pro/Kconfig.defconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 boards/renesas/da1469x_dk_pro/Kconfig.defconfig diff --git a/boards/renesas/da1469x_dk_pro/Kconfig.defconfig b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig new file mode 100644 index 00000000000..ca6a91cea95 --- /dev/null +++ b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig @@ -0,0 +1,12 @@ +# DA1469x series Development Kit Pro board configuration + +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_DA1469X_DK_PRO + +config LV_Z_AREA_X_ALIGNMENT_WIDTH + default 2 + depends on LVGL + +endif # BOARD_DA1469X_DK_PRO From 3813faa302914f2f4ad0b9a6a56aaa6f2bc11df0 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Wed, 21 Feb 2024 13:21:30 +0200 Subject: [PATCH 0089/2402] modem: backends: uart_async: log the number of bytes dropped When a receive buffer overrun happens. Signed-off-by: Tomi Fontanilles --- subsys/modem/backends/modem_backend_uart_async.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/subsys/modem/backends/modem_backend_uart_async.c b/subsys/modem/backends/modem_backend_uart_async.c index 29107198c2f..0fa3684780e 100644 --- a/subsys/modem/backends/modem_backend_uart_async.c +++ b/subsys/modem/backends/modem_backend_uart_async.c @@ -114,7 +114,8 @@ static void modem_backend_uart_async_event_handler(const struct device *dev, if (received < evt->data.rx.len) { ring_buf_reset(&backend->async.receive_rb); k_spin_unlock(&backend->async.receive_rb_lock, key); - LOG_WRN("Receive buffer overrun"); + LOG_WRN("Receive buffer overrun (%u/%u dropped)", + evt->data.rx.len - received, evt->data.rx.len); break; } From 62d84fb3224dd724f1aa95ab239736a4231e48ec Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Wed, 21 Feb 2024 13:27:31 +0200 Subject: [PATCH 0090/2402] drivers: modem_cellular: fine tune nRF91's shutdown_time A shutdown lasting more than 5 seconds was experienced. Signed-off-by: Tomi Fontanilles --- drivers/modem/modem_cellular.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index ed4e998fec3..276c9d38f7b 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -2219,7 +2219,7 @@ MODEM_CHAT_SCRIPT_DEFINE(nordic_nrf91_slm_periodic_chat_script, .power_pulse_duration_ms = 100, \ .reset_pulse_duration_ms = 100, \ .startup_time_ms = 2000, \ - .shutdown_time_ms = 3000, \ + .shutdown_time_ms = 10000, \ .init_chat_script = &nordic_nrf91_slm_init_chat_script, \ .dial_chat_script = &nordic_nrf91_slm_dial_chat_script, \ .periodic_chat_script = &nordic_nrf91_slm_periodic_chat_script, \ From 8473c540359572672a19b94d060fe658271bd081 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Wed, 21 Feb 2024 13:36:22 +0200 Subject: [PATCH 0091/2402] samples: net: cellular_modem: small fixes/improvements - A small delay is added after the post-restart L4_CONNECTED event is received to prevent trying to send packets too quickly. Otherwise the first packet would not get sent and the sample would hang on recv(). - Some logs and function parameters are fixed. Signed-off-by: Tomi Fontanilles --- samples/net/cellular_modem/README.rst | 2 +- samples/net/cellular_modem/prj.conf | 4 +++ samples/net/cellular_modem/src/main.c | 39 ++++++++++++++------------- 3 files changed, 25 insertions(+), 20 deletions(-) diff --git a/samples/net/cellular_modem/README.rst b/samples/net/cellular_modem/README.rst index b845b2e37d8..d46f61f958d 100644 --- a/samples/net/cellular_modem/README.rst +++ b/samples/net/cellular_modem/README.rst @@ -16,7 +16,7 @@ up the IP of test-endpoint.com. Notes ***** -This sample uses the devicetree alias modem to identify +This sample uses the devicetree alias ``modem`` to identify the modem instance to use. The sample also presumes that the modem driver creates the only PPP network interface. diff --git a/samples/net/cellular_modem/prj.conf b/samples/net/cellular_modem/prj.conf index 52d0ca26bde..ab44ca9528e 100644 --- a/samples/net/cellular_modem/prj.conf +++ b/samples/net/cellular_modem/prj.conf @@ -22,3 +22,7 @@ CONFIG_NET_CONNECTION_MANAGER=y CONFIG_MODEM=y CONFIG_PM_DEVICE=y CONFIG_MODEM_CELLULAR=y + +# Logging +CONFIG_MODEM_MODULES_LOG_LEVEL_DBG=y +#CONFIG_MODEM_CMUX_LOG_LEVEL_DBG=y diff --git a/samples/net/cellular_modem/src/main.c b/samples/net/cellular_modem/src/main.c index 6ab5ddc297d..b7e738d13e5 100644 --- a/samples/net/cellular_modem/src/main.c +++ b/samples/net/cellular_modem/src/main.c @@ -160,7 +160,7 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t continue; } - printk("Receiving echoed packet"); + printk("Receiving echoed packet\n"); ret = zsock_recv(socket_fd, sample_recv_buffer, sizeof(sample_recv_buffer), 0); if (ret != sizeof(sample_test_packet)) { printk("Echoed sample test packet has incorrect size\n"); @@ -181,10 +181,10 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t printk("Echo transmit time %ums\n", echo_received_ms - send_start_ms); } - printk("Successfully sent %u packets of %u packets\n", packets_sent, + printk("Successfully sent and received %u of %u packets\n", packets_sent, SAMPLE_TEST_ECHO_PACKETS); - printk("Average time per echo: %u ms\n", + printk("Average time per successful echo: %u ms\n", accumulated_ms / packets_sent); printk("Close UDP socket\n"); @@ -265,10 +265,7 @@ int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint int main(void) { struct net_if *const iface = net_if_get_first_by_type(&NET_L2_GET_NAME(PPP)); - uint32_t raised_event; uint16_t *port; - const void *info; - size_t info_len; int ret; init_sample_test_packet(); @@ -284,9 +281,8 @@ int main(void) } printk("Waiting for L4 connected\n"); - ret = net_mgmt_event_wait_on_iface(iface, - NET_EVENT_L4_CONNECTED, &raised_event, &info, - &info_len, K_SECONDS(120)); + ret = net_mgmt_event_wait_on_iface(iface, NET_EVENT_L4_CONNECTED, NULL, NULL, NULL, + K_SECONDS(120)); if (ret != 0) { printk("L4 was not connected in time\n"); @@ -294,9 +290,12 @@ int main(void) } printk("Waiting for DNS server added\n"); - ret = net_mgmt_event_wait_on_iface(iface, - NET_EVENT_DNS_SERVER_ADD, &raised_event, &info, - &info_len, K_SECONDS(10)); + ret = net_mgmt_event_wait_on_iface(iface, NET_EVENT_DNS_SERVER_ADD, NULL, NULL, NULL, + K_SECONDS(10)); + if (ret) { + printk("DNS server was not added in time\n"); + return -1; + } printk("Retrieving cellular info\n"); print_cellular_info(); @@ -333,7 +332,7 @@ int main(void) sample_test_dns_addrinfo.ai_addrlen, port); if (ret < 0) { - printk("Failed to send echo\n"); + printk("Failed to send echos\n"); return -1; } @@ -355,24 +354,26 @@ int main(void) pm_device_action_run(modem, PM_DEVICE_ACTION_RESUME); printk("Waiting for L4 connected\n"); - ret = net_mgmt_event_wait_on_iface(net_if_get_default(), - NET_EVENT_L4_CONNECTED, &raised_event, &info, - &info_len, K_SECONDS(60)); - + ret = net_mgmt_event_wait_on_iface(iface, NET_EVENT_L4_CONNECTED, NULL, NULL, NULL, + K_SECONDS(60)); if (ret != 0) { printk("L4 was not connected in time\n"); return -1; } + printk("L4 connected\n"); + + /* Wait a bit to avoid (unsuccessfully) trying to send the first echo packet too quickly. */ + k_sleep(K_SECONDS(1)); ret = sample_echo_packet(&sample_test_dns_addrinfo.ai_addr, sample_test_dns_addrinfo.ai_addrlen, port); if (ret < 0) { - printk("Failed to send echo after restart\n"); + printk("Failed to send echos after restart\n"); return -1; } - ret = net_if_down(net_if_get_default()); + ret = net_if_down(iface); if (ret < 0) { printk("Failed to bring down network interface\n"); return -1; From 7f9ed8695c25c3afefe19b27d6bb1344bbb88efb Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Thu, 22 Feb 2024 14:54:45 +0200 Subject: [PATCH 0092/2402] samples: net: cellular_modem: add nRF9160 DK's nRF52840 The added configuration files allow the sample to be run on the nRF52840 present on the nRF9160 DK with the nRF9160 (running SLM) being the modem and communication happening through pins that are routed internally between the two. Signed-off-by: Tomi Fontanilles --- .../boards/nrf9160dk_nrf52840.conf | 13 +++++++++++++ .../boards/nrf9160dk_nrf52840.overlay | 18 ++++++++++++++++++ .../modem/backends/modem_backend_uart_async.c | 2 +- 3 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf create mode 100644 samples/net/cellular_modem/boards/nrf9160dk_nrf52840.overlay diff --git a/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf b/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf new file mode 100644 index 00000000000..2af3b6d2a41 --- /dev/null +++ b/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf @@ -0,0 +1,13 @@ +CONFIG_UART_ASYNC_API=y + +# Align with the Serial LTE Modem (SLM) application. +CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE=1500 +CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES=1500 + +# Allow large UART TXs to go through @115200. +CONFIG_MODEM_BACKEND_UART_ASYNC_TRANSMIT_TIMEOUT_MS=200 + +# Print logs and printk() output on uart0. +CONFIG_LOG=y +CONFIG_LOG_BACKEND_UART=y +CONFIG_MODEM_LOG_LEVEL_DBG=y diff --git a/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.overlay b/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.overlay new file mode 100644 index 00000000000..c639ec8b305 --- /dev/null +++ b/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.overlay @@ -0,0 +1,18 @@ +#include + +/ { + aliases { + modem = &modem; + }; +}; + +&uart1 { + current-speed = <115200>; + hw-flow-control; + + modem: modem { + compatible = "nordic,nrf91-slm"; + status = "okay"; + mdm-power-gpios = <&interface_to_nrf9160 4 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/subsys/modem/backends/modem_backend_uart_async.c b/subsys/modem/backends/modem_backend_uart_async.c index 0fa3684780e..9c06885aec1 100644 --- a/subsys/modem/backends/modem_backend_uart_async.c +++ b/subsys/modem/backends/modem_backend_uart_async.c @@ -114,7 +114,7 @@ static void modem_backend_uart_async_event_handler(const struct device *dev, if (received < evt->data.rx.len) { ring_buf_reset(&backend->async.receive_rb); k_spin_unlock(&backend->async.receive_rb_lock, key); - LOG_WRN("Receive buffer overrun (%u/%u dropped)", + LOG_WRN("Receive buffer overrun (%zu/%zu dropped)", evt->data.rx.len - received, evt->data.rx.len); break; } From ec2e8aaddf3f5623bd7ddcc3b025c10622e27cc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ayt=C3=BCrk=20D=C3=BCzen?= Date: Wed, 21 Feb 2024 11:49:25 +0100 Subject: [PATCH 0093/2402] tests: bluetooth: tester: add nrf54l15 configs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Added: nrf545pdk_nrf5415_cpuapp.overlay: Choose uart20 hwfc 115200 nrf54l15pdk_nrf54l15_cpuapp.conf Signed-off-by: Aytürk Düzen --- .../boards/nrf54l15pdk_nrf54l15_cpuapp.conf | 23 +++++++++++++++++++ .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 14 +++++++++++ 2 files changed, 37 insertions(+) create mode 100644 tests/bluetooth/tester/boards/nrf54l15pdk_nrf54l15_cpuapp.conf create mode 100644 tests/bluetooth/tester/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay diff --git a/tests/bluetooth/tester/boards/nrf54l15pdk_nrf54l15_cpuapp.conf b/tests/bluetooth/tester/boards/nrf54l15pdk_nrf54l15_cpuapp.conf new file mode 100644 index 00000000000..29139393b46 --- /dev/null +++ b/tests/bluetooth/tester/boards/nrf54l15pdk_nrf54l15_cpuapp.conf @@ -0,0 +1,23 @@ +# CONFIG_TEST enforces minimal logging, which we don't want +CONFIG_TEST=n + +CONFIG_ASSERT=y +# Enable the option below to measure stack usage +#CONFIG_INIT_STACKS=y +CONFIG_THREAD_NAME=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_LOG=y +CONFIG_LOG_BUFFER_SIZE=4096 +CONFIG_RTT_CONSOLE=y +CONFIG_LOG_BACKEND_RTT=y +CONFIG_LOG_BACKEND_RTT_MODE_DROP=y +CONFIG_USE_SEGGER_RTT=y +CONFIG_SEGGER_RTT_BUFFER_SIZE_UP=4096 +CONFIG_LOG_BACKEND_SHOW_COLOR=n +CONFIG_LOG_PROCESS_THREAD_STACK_SIZE=1024 + +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_BTTESTER_LOG_LEVEL_DBG=y + +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/tests/bluetooth/tester/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/bluetooth/tester/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay new file mode 100644 index 00000000000..979fa6cc5df --- /dev/null +++ b/tests/bluetooth/tester/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +/ { + chosen { + zephyr,uart-pipe = &uart20; + }; +}; + +&uart20 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + hw-flow-control; +}; From f1bfbb06277cca9d8576f6aac99e7777f7c0ab22 Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Wed, 21 Feb 2024 10:20:54 +0100 Subject: [PATCH 0094/2402] dts: arm: st: wba: do not enable standby pm mode Do not enable Standby low-power mode by default since the associated Kconfig PM_S2RAM is disabled by default. Otherwise we could enter an unsupported low-power state. Signed-off-by: Guillaume Gautier --- dts/arm/st/wba/stm32wba.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/dts/arm/st/wba/stm32wba.dtsi b/dts/arm/st/wba/stm32wba.dtsi index 4ae45491f7f..0039b1500a1 100644 --- a/dts/arm/st/wba/stm32wba.dtsi +++ b/dts/arm/st/wba/stm32wba.dtsi @@ -33,7 +33,8 @@ device_type = "cpu"; compatible = "arm,cortex-m33"; reg = <0>; - cpu-power-states = <&stop0 &stop1 &standby>; + /* Do not add &standby here since CONFIG_PM_S2RAM is disabled by default */ + cpu-power-states = <&stop0 &stop1>; #address-cells = <1>; #size-cells = <1>; From cfa7e38378a9023cd6b4e1bc093de8f82e4b413b Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Wed, 21 Feb 2024 10:21:51 +0100 Subject: [PATCH 0095/2402] samples: boards: stm32: pm: s2ram: enable standby mode Add Standby mode to the overlay since here we want to test Suspend to RAM. Signed-off-by: Guillaume Gautier --- .../power_mgmt/suspend_to_ram/boards/nucleo_wba55cg.overlay | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/samples/boards/stm32/power_mgmt/suspend_to_ram/boards/nucleo_wba55cg.overlay b/samples/boards/stm32/power_mgmt/suspend_to_ram/boards/nucleo_wba55cg.overlay index 3ed3dab7a88..a3d46e95fb7 100644 --- a/samples/boards/stm32/power_mgmt/suspend_to_ram/boards/nucleo_wba55cg.overlay +++ b/samples/boards/stm32/power_mgmt/suspend_to_ram/boards/nucleo_wba55cg.overlay @@ -7,6 +7,10 @@ / { /* Change min residency time to ease power consumption measurement */ cpus { + cpu0: cpu@0 { + cpu-power-states = <&stop0 &stop1 &standby>; + }; + power-states { stop0: state0 { min-residency-us = <500000>; From 112bcb229cd28b385b322f9b048eb9182052fb07 Mon Sep 17 00:00:00 2001 From: Jan Bylicki Date: Wed, 13 Dec 2023 13:53:17 +0100 Subject: [PATCH 0096/2402] soc/arm/renesas_rzt2m: set default System Clock Control register values Introduced changes to set the default values for clock control registers Signed-off-by: Jan Bylicki --- dts/arm/renesas/rz/rzt2m.dtsi | 14 +++++++++++ soc/renesas/rzt2m/soc.c | 45 +++++++++++++++++++++++++++++++++++ soc/renesas/rzt2m/soc.h | 29 ++++++++++++++++++++++ 3 files changed, 88 insertions(+) diff --git a/dts/arm/renesas/rz/rzt2m.dtsi b/dts/arm/renesas/rz/rzt2m.dtsi index 9c6c1688d63..d4138994372 100644 --- a/dts/arm/renesas/rz/rzt2m.dtsi +++ b/dts/arm/renesas/rz/rzt2m.dtsi @@ -89,6 +89,20 @@ reg-io-width = <4>; }; + sckcr: sckcr@81280004 { + /* System Clock Control Register*/ + compatible = "syscon"; + reg = <0x80280000 0x20>; + reg-io-width = <4>; + }; + + sckcr2: sckcr2@81280004 { + /* System Clock Control Register 2 */ + compatible = "syscon"; + reg = <0x81280004 0x1a>; + reg-io-width = <4>; + }; + uart0: serial@80001000 { compatible = "renesas,rzt2m-uart"; reg = <0x80001000 0x1000>; diff --git a/soc/renesas/rzt2m/soc.c b/soc/renesas/rzt2m/soc.c index 5a854090229..673994e254d 100644 --- a/soc/renesas/rzt2m/soc.c +++ b/soc/renesas/rzt2m/soc.c @@ -12,6 +12,8 @@ static const struct device *const prcrn_dev = DEVICE_DT_GET(DT_NODELABEL(prcrn)); static const struct device *const prcrs_dev = DEVICE_DT_GET(DT_NODELABEL(prcrs)); +static const struct device *const sckcr_dev = DEVICE_DT_GET(DT_NODELABEL(sckcr)); +static const struct device *const sckcr2_dev = DEVICE_DT_GET(DT_NODELABEL(sckcr2)); void rzt2m_unlock_prcrn(uint32_t mask) { @@ -55,6 +57,32 @@ void rzt2m_lock_prcrs(uint32_t mask) syscon_write_reg(prcrs_dev, 0, prcrs); } +void rzt2m_set_sckcr2(uint32_t mask) +{ + syscon_write_reg(sckcr2_dev, 0, mask); +} + +uint32_t rzt2m_get_sckcr2(void) +{ + uint32_t reg; + + syscon_read_reg(sckcr2_dev, 0, ®); + return reg; +} + +void rzt2m_set_sckcr(uint32_t mask) +{ + syscon_write_reg(sckcr_dev, 0, mask); +} + +uint32_t rzt2m_get_sckcr(void) +{ + uint32_t reg; + + syscon_read_reg(sckcr_dev, 0, ®); + return reg; +} + void rzt2m_enable_counters(void) { const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(gsc)); @@ -68,6 +96,23 @@ static int rzt2m_init(void) * so that device drivers can access configuration registers of peripherals. */ /* After the device drivers are done, lock the Protect Registers. */ + rzt2m_unlock_prcrs(PRCRS_GPIO | PRCRS_CLK); + rzt2m_unlock_prcrn(PRCRN_PRC1 | PRCRN_PRC2 | PRCRN_PRC0); + + /* Reset the System Clock Control Registers to default values */ + rzt2m_set_sckcr( + CLMASEL | + PHYSEL | + FSELCANFD | + FSELXSPI0_DEFAULT | + FSELXSPI1_DEFAULT | + CKIO_DEFAULT + ); + + rzt2m_set_sckcr2(FSELCPU0_DEFAULT | FSELCPU1_DEFAULT); + + rzt2m_lock_prcrs(PRCRS_GPIO | PRCRS_CLK); + rzt2m_lock_prcrn(PRCRN_PRC1 | PRCRN_PRC2 | PRCRN_PRC0); rzt2m_enable_counters(); return 0; diff --git a/soc/renesas/rzt2m/soc.h b/soc/renesas/rzt2m/soc.h index 02bd03b69a1..64ccdc0e0b5 100644 --- a/soc/renesas/rzt2m/soc.h +++ b/soc/renesas/rzt2m/soc.h @@ -27,6 +27,30 @@ #define PRCRN_PRC1 BIT(1) #define PRCRN_PRC2 BIT(2) +#define SCI4ASYNCSEL BIT(31) +#define SCI3ASYNCSEL BIT(30) +#define SCI2ASYNCSEL BIT(29) +#define SCI1ASYNCSEL BIT(28) +#define SCI0ASYNCSEL BIT(27) +#define SPI2ASYNCSEL BIT(26) +#define SPI1ASYNCSEL BIT(25) +#define SPI0ASYNCSEL BIT(24) +#define CLMASEL BIT(22) +#define PHYSEL BIT(21) +#define FSELCANFD BIT(20) +#define DIVSELXSPI1 BIT(14) +#define DIVSELXSPI0 BIT(6) + +#define CKIO_DEFAULT BIT(17) +#define FSELXSPI1_DEFAULT GENMASK(10, 9) +#define FSELXSPI0_DEFAULT GENMASK(2, 1) + +#define SCI5ASYNCSEL BIT(25) +#define SPI3ASYNCSEL BIT(24) +#define DIVSELSUB BIT(5) +#define FSELCPU1_DEFAULT 0b10 << 2 +#define FSELCPU0_DEFAULT 0b10 << 0 + /* PRC Key Code - this value is required to allow any write operation * to the PRCRS / PRCRN registers. * See section 10.2 of the RZ/T2M User's Manual: Hardware. @@ -38,4 +62,9 @@ void rzt2m_lock_prcrn(uint32_t mask); void rzt2m_unlock_prcrs(uint32_t mask); void rzt2m_lock_prcrs(uint32_t mask); +void rzt2m_set_sckcr2(uint32_t mask); +uint32_t rzt2m_get_sckcr2(void); +void rzt2m_set_sckcr(uint32_t mask); +uint32_t rzt2m_get_sckcr(void); + #endif /* _SOC__H_ */ From 0569809c807f80028463eb3c7b564fb76a54bb6b Mon Sep 17 00:00:00 2001 From: Glenn Andrews Date: Thu, 21 Dec 2023 08:12:10 -0800 Subject: [PATCH 0097/2402] Lib: SMF: Add initial transition and smf_set_handled() Brings SMF framework closer into alignment with accepted Hierarchical State Machine operation by: 1. Allowing 'programming by difference' by having some child states handle events and prevent propagation up to the parent run actions while others propagate events up to a common handler in a parent state. 2. Optionally allow initial transitions within a parent state to determine the most nested child state to transition to. 3. Adding a test case for `CONFIG_SMF_INITIAL_TRANSITION` and `smf_set_handled()` 4. Updating documentation for the new API (and fixing some references) There was discussion in https://github.com/zephyrproject-rtos/zephyr/issues/55344 about not making the initial transition a Kconfig option, but I'm not sure of any way else of doing it without permanently adding a pointer to each `smf_state` entry, which is a problem for resource-constrained devices. This does not fix https://github.com/zephyrproject-rtos/zephyr/issues/66341 but documentation has been updated to warn users of the issue. Signed-off-by: Glenn Andrews --- doc/services/smf/index.rst | 116 +++- include/zephyr/smf.h | 36 ++ lib/smf/Kconfig | 6 + lib/smf/smf.c | 40 ++ tests/lib/smf/CMakeLists.txt | 4 +- .../src/test_lib_initial_transitions_smf.c | 501 ++++++++++++++++++ tests/lib/smf/src/test_lib_smf.h | 1 + tests/lib/smf/testcase.yaml | 4 + 8 files changed, 687 insertions(+), 21 deletions(-) create mode 100644 tests/lib/smf/src/test_lib_initial_transitions_smf.c diff --git a/doc/services/smf/index.rst b/doc/services/smf/index.rst index d5f1f918471..bc745c0acee 100644 --- a/doc/services/smf/index.rst +++ b/doc/services/smf/index.rst @@ -20,7 +20,7 @@ A state is represented by three functions, where one function implements the Entry actions, another function implements the Run actions, and the last function implements the Exit actions. The prototype for these functions is as follows: ``void funct(void *obj)``, where the ``obj`` parameter is a user -defined structure that has the state machine context, ``struct smf_ctx``, as +defined structure that has the state machine context, :c:struct:`smf_ctx`, as its first member. For example:: struct user_object { @@ -28,9 +28,9 @@ its first member. For example:: /* All User Defined Data Follows */ }; -The ``struct smf_ctx`` member must be first because the state machine -framework's functions casts the user defined object to the ``struct smf_ctx`` -type with the following macro: ``SMF_CTX(o)`` +The :c:struct:`smf_ctx` member must be first because the state machine +framework's functions casts the user defined object to the :c:struct:`smf_ctx` +type with the :c:macro:`SMF_CTX` macro. For example instead of doing this ``(struct smf_ctx *)&user_obj``, you could use ``SMF_CTX(&user_obj)``. @@ -39,12 +39,19 @@ By default, a state can have no ancestor states, resulting in a flat state machine. But to enable the creation of a hierarchical state machine, the :kconfig:option:`CONFIG_SMF_ANCESTOR_SUPPORT` option must be enabled. +By default, the hierarchical state machine does not support initial transitions +to child states on entering a superstate. To enable them the +:kconfig:option:`CONFIG_SMF_INITIAL_TRANSITION` option must be enabled. + The following macro can be used for easy state creation: * :c:macro:`SMF_CREATE_STATE` Create a state -**NOTE:** The :c:macro:`SMF_CREATE_STATE` macro takes an additional parameter -when :kconfig:option:`CONFIG_SMF_ANCESTOR_SUPPORT` is enabled. +.. note:: The :c:macro:`SMF_CREATE_STATE` macro takes an additional parameter + for the parent state when :kconfig:option:`CONFIG_SMF_ANCESTOR_SUPPORT` is + enabled . The :c:macro:`SMF_CREATE_STATE` macro takes two additional + parameters for the parent state and initial transition when the + :kconfig:option:`CONFIG_SMF_INITIAL_TRANSITION` option is enabled. State Machine Creation ====================== @@ -71,33 +78,61 @@ And this example creates three hierarchical states:: }; -To set the initial state, the ``smf_set_initial`` function should be +This example creates three hierarchical states with an initial transition +from parent state S0 to child state S2:: + + enum demo_state { S0, S1, S2 }; + + /* Forward declaration of state table */ + const struct smf_state demo_states[]; + + const struct smf_state demo_states[] = { + [S0] = SMF_CREATE_STATE(s0_entry, s0_run, s0_exit, NULL, demo_states[S2]), + [S1] = SMF_CREATE_STATE(s1_entry, s1_run, s1_exit, demo_states[S0], NULL), + [S2] = SMF_CREATE_STATE(s2_entry, s2_run, s2_exit, demo_states[S0], NULL) + }; + +To set the initial state, the :c:func:`smf_set_initial` function should be called. It has the following prototype: ``void smf_set_initial(smf_ctx *ctx, smf_state *state)`` -To transition from one state to another, the ``smf_set_state`` function is -used and it has the following prototype: +To transition from one state to another, the :c:func:`smf_set_state` +function is used and it has the following prototype: ``void smf_set_state(smf_ctx *ctx, smf_state *state)`` -**NOTE:** While the state machine is running, smf_set_state should only be -called from the Entry and Run functions. Calling smf_set_state from the Exit -functions doesn't make sense and will generate a warning. +.. note:: If :kconfig:option:`CONFIG_SMF_INITIAL_TRANSITION` is not set, + :c:func:`smf_set_initial` and :c:func:`smf_set_state` function should + not be passed a parent state as they will not know which child state + to transition to. Transitioning to a parent state is OK if an initial + transition to a child state is defined. A well-formed HSM will have + initial transitions defined for all parent states. + +.. note:: While the state machine is running, smf_set_state should only be + called from the Entry and Run functions. Calling smf_set_state from the + Exit functions doesn't make sense and will generate a warning. State Machine Execution ======================= -To run the state machine, the ``smf_run_state`` function should be called in -some application dependent way. An application should cease calling +To run the state machine, the :c:func:`smf_run_state` function should be +called in some application dependent way. An application should cease calling smf_run_state if it returns a non-zero value. The function has the following prototype: ``int32_t smf_run_state(smf_ctx *ctx)`` +Preventing Parent Run Actions +============================= + +Calling :c:func:`smf_set_handled` prevents calling the run action of parent +states. It is not required to call :c:func:`smf_set_handled` if the state +calls :c:func:`smf_set_state`. + State Machine Termination ========================= -To terminate the state machine, the ``smf_terminate`` function should be -called. It can be called from the entry, run, or exit action. The function -takes a non-zero user defined value that's returned by the ``smf_run_state`` -function. The function has the following prototype: +To terminate the state machine, the :c:func:`smf_terminate` function should +be called. It can be called from the entry, run, or exit action. The +function takes a non-zero user defined value that's returned by the +:c:func:`smf_run_state` function. The function has the following prototype: ``void smf_terminate(smf_ctx *ctx, int32_t val)`` Flat State Machine Example @@ -316,8 +351,11 @@ When designing hierarchical state machines, the following should be considered: - Ancestor exit actions are executed after the sibling exit actions. For example, the s1_exit function is called before the parent_exit function is called. - - The parent_run function only executes if the child_run function returns - without transitioning to another state, ie. calling smf_set_state. + - The parent_run function only executes if the child_run function does not + call either :c:func:`smf_set_state` or :c:func:`smf_set_handled`. + - When a parent state intitiates a transition to self, the parents's exit + action is not called, e.g. instead of child_exit, parent_exit, parent_entry + it performs child_exit, parent_entry Event Driven State Machine Example ================================== @@ -466,3 +504,41 @@ Code:: } } } + +Hierarchical State Machine Example With Initial Transitions +=========================================================== + +:zephyr_file:`tests/lib/smf/src/test_lib_initial_transitions_smf.c` defines +a state machine for testing initial transitions and :c:func:`smf_set_handled`. +The statechart for this test is below. + +.. graphviz:: + :caption: Test state machine for initial trnasitions and ``smf_set_handled`` + + digraph smf_hierarchical_initial { + compound=true; + node [style = rounded]; + smf_set_initial [shape=plaintext]; + ab_init_state [shape = point]; + STATE_A [shape = box]; + STATE_B [shape = box]; + STATE_C [shape = box]; + STATE_D [shape = box]; + + subgraph cluster_ab { + label = "PARENT_AB"; + style = rounded; + ab_init_state -> STATE_A; + STATE_A -> STATE_B; + } + + subgraph cluster_c { + label = "PARENT_C"; + style = rounded; + STATE_C -> STATE_C + } + + smf_set_initial -> STATE_A [lhead=cluster_ab] + STATE_B -> STATE_C + STATE_C -> STATE_D + } diff --git a/include/zephyr/smf.h b/include/zephyr/smf.h index 2fdcbbdced6..b4aee26fa74 100644 --- a/include/zephyr/smf.h +++ b/include/zephyr/smf.h @@ -18,6 +18,7 @@ * @param _exit State exit function * @param _parent State parent object or NULL */ +#ifndef CONFIG_SMF_INITIAL_TRANSITION #define SMF_CREATE_STATE(_entry, _run, _exit, _parent) \ { \ .entry = _entry, \ @@ -25,6 +26,25 @@ .exit = _exit, \ .parent = _parent \ } +#else +/** + * @brief Macro to create a hierarchical state. + * + * @param _entry State entry function + * @param _run State run function + * @param _exit State exit function + * @param _parent State parent object or NULL + * @param _initial State initial transition object or NULL + */ +#define SMF_CREATE_STATE(_entry, _run, _exit, _parent, _initial) \ +{ \ + .entry = _entry, \ + .run = _run, \ + .exit = _exit, \ + .parent = _parent, \ + .initial = _initial \ +} +#endif /* CONFIG_SMF_INITIAL_TRANSITION */ #else @@ -87,6 +107,13 @@ struct smf_state { * that parent's exit and entry functions do not execute. */ const struct smf_state *parent; + +#ifdef CONFIG_SMF_INITIAL_TRANSITION + /** + * Optional initial transition state. NULL for leaf states. + */ + const struct smf_state *initial; +#endif }; /** Defines the current context of the state machine. */ @@ -136,6 +163,15 @@ void smf_set_state(struct smf_ctx *ctx, const struct smf_state *new_state); */ void smf_set_terminate(struct smf_ctx *ctx, int32_t val); +/** + * @brief Tell the SMF to stop propagating the event to ancestors. This allows + * HSMs to implement 'programming by difference' where substates can + * handle events on their own or propagate up to a common handler. + * + * @param ctx State machine context + */ +void smf_set_handled(struct smf_ctx *ctx); + /** * @brief Runs one iteration of a state machine (including any parent states) * diff --git a/lib/smf/Kconfig b/lib/smf/Kconfig index 4204e9c8ed4..19cd165637d 100644 --- a/lib/smf/Kconfig +++ b/lib/smf/Kconfig @@ -13,4 +13,10 @@ config SMF_ANCESTOR_SUPPORT help If y, then the state machine framework includes ancestor state support +config SMF_INITIAL_TRANSITION + depends on SMF_ANCESTOR_SUPPORT + bool "Support initial transitions for ancestor states" + help + If y, then each state can have an initial transition to a sub-state + endif # SMF diff --git a/lib/smf/smf.c b/lib/smf/smf.c index 01fb42e6cfc..d869de47c6e 100644 --- a/lib/smf/smf.c +++ b/lib/smf/smf.c @@ -18,6 +18,7 @@ struct internal_ctx { bool new_state : 1; bool terminate : 1; bool exit : 1; + bool handled : 1; }; static bool share_paren(const struct smf_state *test_state, @@ -118,6 +119,12 @@ __unused static bool smf_execute_ancestor_run_actions(struct smf_ctx *ctx) return true; } + if (internal->handled) { + /* Event was handled by this state. Stop propagating */ + internal->handled = false; + return false; + } + /* Try to run parent run actions */ for (const struct smf_state *tmp_state = ctx->current->parent; tmp_state != NULL; @@ -133,6 +140,12 @@ __unused static bool smf_execute_ancestor_run_actions(struct smf_ctx *ctx) if (internal->new_state) { break; } + + if (internal->handled) { + /* Event was handled by this state. Stop propagating */ + internal->handled = false; + break; + } } } @@ -175,6 +188,16 @@ void smf_set_initial(struct smf_ctx *ctx, const struct smf_state *init_state) { struct internal_ctx * const internal = (void *) &ctx->internal; + +#ifdef CONFIG_SMF_INITIAL_TRANSITION + /* + * The final target will be the deepest leaf state that + * the target contains. Set that as the real target. + */ + while (init_state->initial) { + init_state = init_state->initial; + } +#endif internal->exit = false; internal->terminate = false; ctx->current = init_state; @@ -234,6 +257,16 @@ void smf_set_state(struct smf_ctx *const ctx, const struct smf_state *target) internal->exit = false; +#ifdef CONFIG_SMF_INITIAL_TRANSITION + /* + * The final target will be the deepest leaf state that + * the target contains. Set that as the real target. + */ + while (target->initial) { + target = target->initial; + } +#endif + /* update the state variables */ ctx->previous = ctx->current; ctx->current = target; @@ -262,6 +295,13 @@ void smf_set_terminate(struct smf_ctx *ctx, int32_t val) ctx->terminate_val = val; } +void smf_set_handled(struct smf_ctx *ctx) +{ + struct internal_ctx *const internal = (void *)&ctx->internal; + + internal->handled = true; +} + int32_t smf_run_state(struct smf_ctx *const ctx) { struct internal_ctx * const internal = (void *) &ctx->internal; diff --git a/tests/lib/smf/CMakeLists.txt b/tests/lib/smf/CMakeLists.txt index 147223b0288..08844e75aa6 100644 --- a/tests/lib/smf/CMakeLists.txt +++ b/tests/lib/smf/CMakeLists.txt @@ -6,7 +6,9 @@ project(smf) target_sources(app PRIVATE src/main.c) -if(CONFIG_SMF_ANCESTOR_SUPPORT) +if(CONFIG_SMF_INITIAL_TRANSITION) + target_sources(app PRIVATE src/test_lib_initial_transitions_smf.c) +elseif(CONFIG_SMF_ANCESTOR_SUPPORT) target_sources(app PRIVATE src/test_lib_hierarchical_smf.c src/test_lib_hierarchical_5_ancestor_smf.c) else() diff --git a/tests/lib/smf/src/test_lib_initial_transitions_smf.c b/tests/lib/smf/src/test_lib_initial_transitions_smf.c new file mode 100644 index 00000000000..2e00dc2d553 --- /dev/null +++ b/tests/lib/smf/src/test_lib_initial_transitions_smf.c @@ -0,0 +1,501 @@ +/* + * Copyright 2024 Glenn Andrews + * based on test_lib_hierarchical_smf.c + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* + * Hierarchical Test Transition: + * + * PARENT_AB_ENTRY --> A_ENTRY --> A_RUN --> PARENT_AB_RUN ---| + * | + * |----------------------------------------------------------| + * | + * |--> A_EXIT --> B_ENTRY --> B_RUN --> B_EXIT --------------| + * | + * |----------------------------------------------------------| + * | + * |--> PARENT_AB_EXIT --> PARENT_C_ENTRY --> C_ENTRY --------| + * | + * |----------------------------------------------------------| + * | + * |--> C_RUN(#1) --> C_RUN(#2) --> C_EXIT --> PARENT_C_RUN --| + * | + * |----------------------------------------------------------| + * | + * |--> PARENT_C_EXIT + */ + +#define TEST_OBJECT(o) ((struct test_object *)o) + +#define SMF_RUN 4 + +/* Initial Setup */ +#define PARENT_AB_ENTRY_BIT (1 << 0) +#define STATE_A_ENTRY_BIT (1 << 1) + +/* Run 0 */ +#define STATE_A_RUN_BIT (1 << 2) +#define PARENT_AB_RUN_BIT (1 << 3) +#define STATE_A_EXIT_BIT (1 << 4) +#define STATE_B_ENTRY_BIT (1 << 5) + +/* Run 1 */ +#define STATE_B_RUN_BIT (1 << 6) +#define STATE_B_EXIT_BIT (1 << 7) +#define PARENT_AB_EXIT_BIT (1 << 8) +#define PARENT_C_ENTRY_BIT (1 << 9) +#define STATE_C_ENTRY_BIT (1 << 10) + +/* Run 2 */ +#define STATE_C_1ST_RUN_BIT (1 << 11) + +/* Run 3 */ +#define STATE_C_2ND_RUN_BIT (1 << 12) +#define PARENT_C_RUN_BIT (1 << 13) +#define STATE_C_EXIT_BIT (1 << 14) +#define PARENT_C_EXIT_BIT (1 << 15) + +#define TEST_PARENT_ENTRY_VALUE_NUM 0 +#define TEST_PARENT_RUN_VALUE_NUM 3 +#define TEST_PARENT_EXIT_VALUE_NUM 8 +#define TEST_ENTRY_VALUE_NUM 1 +#define TEST_RUN_VALUE_NUM 6 +#define TEST_EXIT_VALUE_NUM 14 +#define TEST_VALUE_NUM 16 +static uint32_t test_value[] = { + 0x00, /* PARENT_AB_ENTRY */ + 0x01, /* STATE_A_ENTRY */ + 0x03, /* STATE_A_RUN */ + 0x07, /* PARENT_AB_RUN */ + 0x0f, /* STATE_A_EXIT */ + 0x1f, /* STATE_B_ENTRY */ + 0x3f, /* STATE_B_RUN */ + 0x7f, /* STATE_B_EXIT */ + 0xff, /* PARENT_AB_EXIT */ + 0x1ff, /* PARENT_C_ENTRY */ + 0x3ff, /* STATE_C_ENTRY */ + 0x7ff, /* STATE_C_1ST_RUN */ + 0xfff, /* STATE_C_2ND_RUN */ + 0x1fff, /* STATE_C_EXIT */ + 0x3fff, /* PARENT_C_RUN */ + 0x7fff, /* PARENT_C_EXIT */ + 0xffff, /* FINAL VALUE */ +}; + +/* Forward declaration of test_states */ +static const struct smf_state test_states[]; + +/* List of all TypeC-level states */ +enum test_state { + PARENT_AB, + PARENT_C, + STATE_A, + STATE_B, + STATE_C, + STATE_D +}; + +enum terminate_action { + NONE, + PARENT_ENTRY, + PARENT_RUN, + PARENT_EXIT, + ENTRY, + RUN, + EXIT +}; + +static struct test_object { + struct smf_ctx ctx; + uint32_t transition_bits; + uint32_t tv_idx; + enum terminate_action terminate; + uint32_t first_time; +} test_obj; + +static void parent_ab_entry(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx = 0; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test Parent AB entry failed"); + + if (o->terminate == PARENT_ENTRY) { + smf_set_terminate(obj, -1); + return; + } + + o->transition_bits |= PARENT_AB_ENTRY_BIT; +} + +static void parent_ab_run(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test Parent AB run failed"); + + if (o->terminate == PARENT_RUN) { + smf_set_terminate(obj, -1); + return; + } + + o->transition_bits |= PARENT_AB_RUN_BIT; + + smf_set_state(SMF_CTX(obj), &test_states[STATE_B]); +} + +static void parent_ab_exit(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test Parent AB exit failed"); + + if (o->terminate == PARENT_EXIT) { + smf_set_terminate(obj, -1); + return; + } + + o->transition_bits |= PARENT_AB_EXIT_BIT; +} + +static void parent_c_entry(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test Parent C entry failed"); + o->transition_bits |= PARENT_C_ENTRY_BIT; +} + +static void parent_c_run(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + if (o->first_time) { + /* This state should not be reached */ + zassert_true(0, "Test Parent C run failed"); + } else { + o->transition_bits |= PARENT_C_RUN_BIT; + + smf_set_state(SMF_CTX(obj), &test_states[STATE_D]); + } +} + +static void parent_c_exit(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test Parent C exit failed"); + o->transition_bits |= PARENT_C_EXIT_BIT; +} + +static void state_a_entry(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test State A entry failed"); + + if (o->terminate == ENTRY) { + smf_set_terminate(obj, -1); + return; + } + + o->transition_bits |= STATE_A_ENTRY_BIT; +} + +static void state_a_run(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test State A run failed"); + + o->transition_bits |= STATE_A_RUN_BIT; + + /* Return to parent run state */ +} + +static void state_a_exit(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test State A exit failed"); + o->transition_bits |= STATE_A_EXIT_BIT; +} + +static void state_b_entry(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test State B entry failed"); + o->transition_bits |= STATE_B_ENTRY_BIT; +} + +static void state_b_run(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test State B run failed"); + + if (o->terminate == RUN) { + smf_set_terminate(obj, -1); + return; + } + + o->transition_bits |= STATE_B_RUN_BIT; + + smf_set_state(SMF_CTX(obj), &test_states[STATE_C]); +} + +static void state_b_exit(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test State B exit failed"); + o->transition_bits |= STATE_B_EXIT_BIT; +} + +static void state_c_entry(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test State C entry failed"); + o->transition_bits |= STATE_C_ENTRY_BIT; +} + +static void state_c_run(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test State C run failed"); + + if (o->first_time) { + o->first_time = false; + o->transition_bits |= STATE_C_1ST_RUN_BIT; + smf_set_handled(SMF_CTX(obj)); + } else { + /* Do nothing, Let parent handle it */ + o->transition_bits |= STATE_C_2ND_RUN_BIT; + } +} + +static void state_c_exit(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; + + zassert_equal(o->transition_bits, test_value[o->tv_idx], + "Test State C exit failed"); + + if (o->terminate == EXIT) { + smf_set_terminate(obj, -1); + return; + } + + o->transition_bits |= STATE_C_EXIT_BIT; +} + +static void state_d_entry(void *obj) +{ + struct test_object *o = TEST_OBJECT(obj); + + o->tv_idx++; +} + +static void state_d_run(void *obj) +{ + /* Do nothing */ +} + +static void state_d_exit(void *obj) +{ + /* Do nothing */ +} + +static const struct smf_state test_states[] = { + [PARENT_AB] = SMF_CREATE_STATE(parent_ab_entry, parent_ab_run, + parent_ab_exit, NULL, &test_states[STATE_A]), + [PARENT_C] = SMF_CREATE_STATE(parent_c_entry, parent_c_run, + parent_c_exit, NULL, &test_states[STATE_C]), + [STATE_A] = SMF_CREATE_STATE(state_a_entry, state_a_run, state_a_exit, + &test_states[PARENT_AB], NULL), + [STATE_B] = SMF_CREATE_STATE(state_b_entry, state_b_run, state_b_exit, + &test_states[PARENT_AB], NULL), + [STATE_C] = SMF_CREATE_STATE(state_c_entry, state_c_run, state_c_exit, + &test_states[PARENT_C], NULL), + [STATE_D] = SMF_CREATE_STATE(state_d_entry, state_d_run, state_d_exit, + NULL, NULL), +}; + +ZTEST(smf_tests, test_smf_initial_transitions) +{ + /* A) Test state transitions */ + + test_obj.transition_bits = 0; + test_obj.first_time = 1; + test_obj.terminate = NONE; + smf_set_initial((struct smf_ctx *)&test_obj, &test_states[PARENT_AB]); + + for (int i = 0; i < SMF_RUN; i++) { + if (smf_run_state((struct smf_ctx *)&test_obj) < 0) { + break; + } + } + + zassert_equal(TEST_VALUE_NUM, test_obj.tv_idx, + "Incorrect test value index"); + zassert_equal(test_obj.transition_bits, test_value[test_obj.tv_idx], + "Final state not reached"); + + /* B) Test termination in parent entry action */ + + test_obj.transition_bits = 0; + test_obj.first_time = 1; + test_obj.terminate = PARENT_ENTRY; + smf_set_initial((struct smf_ctx *)&test_obj, &test_states[PARENT_AB]); + + for (int i = 0; i < SMF_RUN; i++) { + if (smf_run_state((struct smf_ctx *)&test_obj) < 0) { + break; + } + } + + zassert_equal(TEST_PARENT_ENTRY_VALUE_NUM, test_obj.tv_idx, + "Incorrect test value index for parent entry termination"); + zassert_equal(test_obj.transition_bits, test_value[test_obj.tv_idx], + "Final parent entry termination state not reached"); + + /* C) Test termination in parent run action */ + + test_obj.transition_bits = 0; + test_obj.first_time = 1; + test_obj.terminate = PARENT_RUN; + smf_set_initial((struct smf_ctx *)&test_obj, &test_states[PARENT_AB]); + + for (int i = 0; i < SMF_RUN; i++) { + if (smf_run_state((struct smf_ctx *)&test_obj) < 0) { + break; + } + } + + zassert_equal(TEST_PARENT_RUN_VALUE_NUM, test_obj.tv_idx, + "Incorrect test value index for parent run termination"); + zassert_equal(test_obj.transition_bits, test_value[test_obj.tv_idx], + "Final parent run termination state not reached"); + + /* D) Test termination in parent exit action */ + + test_obj.transition_bits = 0; + test_obj.first_time = 1; + test_obj.terminate = PARENT_EXIT; + smf_set_initial((struct smf_ctx *)&test_obj, &test_states[PARENT_AB]); + + for (int i = 0; i < SMF_RUN; i++) { + if (smf_run_state((struct smf_ctx *)&test_obj) < 0) { + break; + } + } + + zassert_equal(TEST_PARENT_EXIT_VALUE_NUM, test_obj.tv_idx, + "Incorrect test value index for parent exit termination"); + zassert_equal(test_obj.transition_bits, test_value[test_obj.tv_idx], + "Final parent exit termination state not reached"); + + /* E) Test termination in child entry action */ + + test_obj.transition_bits = 0; + test_obj.first_time = 1; + test_obj.terminate = ENTRY; + smf_set_initial((struct smf_ctx *)&test_obj, &test_states[PARENT_AB]); + + for (int i = 0; i < SMF_RUN; i++) { + if (smf_run_state((struct smf_ctx *)&test_obj) < 0) { + break; + } + } + + zassert_equal(TEST_ENTRY_VALUE_NUM, test_obj.tv_idx, + "Incorrect test value index for entry termination"); + zassert_equal(test_obj.transition_bits, test_value[test_obj.tv_idx], + "Final entry termination state not reached"); + + /* F) Test termination in child run action */ + + test_obj.transition_bits = 0; + test_obj.first_time = 1; + test_obj.terminate = RUN; + smf_set_initial((struct smf_ctx *)&test_obj, &test_states[PARENT_AB]); + + for (int i = 0; i < SMF_RUN; i++) { + if (smf_run_state((struct smf_ctx *)&test_obj) < 0) { + break; + } + } + + zassert_equal(TEST_RUN_VALUE_NUM, test_obj.tv_idx, + "Incorrect test value index for run termination"); + zassert_equal(test_obj.transition_bits, test_value[test_obj.tv_idx], + "Final run termination state not reached"); + + /* G) Test termination in child exit action */ + + test_obj.transition_bits = 0; + test_obj.first_time = 1; + test_obj.terminate = EXIT; + smf_set_initial((struct smf_ctx *)&test_obj, &test_states[PARENT_AB]); + + for (int i = 0; i < SMF_RUN; i++) { + if (smf_run_state((struct smf_ctx *)&test_obj) < 0) { + break; + } + } + + zassert_equal(TEST_EXIT_VALUE_NUM, test_obj.tv_idx, + "Incorrect test value index for exit termination"); + zassert_equal(test_obj.transition_bits, test_value[test_obj.tv_idx], + "Final exit termination state not reached"); +} diff --git a/tests/lib/smf/src/test_lib_smf.h b/tests/lib/smf/src/test_lib_smf.h index 998e3321ad1..6296352fb73 100644 --- a/tests/lib/smf/src/test_lib_smf.h +++ b/tests/lib/smf/src/test_lib_smf.h @@ -10,5 +10,6 @@ void test_smf_flat(void); void test_smf_hierarchical(void); void test_smf_hierarchical_5_ancestors(void); +void test_smf_initial_transitions(void); #endif /* ZEPHYR_TEST_LIB_SMF_H_ */ diff --git a/tests/lib/smf/testcase.yaml b/tests/lib/smf/testcase.yaml index 761f86e8fff..fff0bf0e974 100644 --- a/tests/lib/smf/testcase.yaml +++ b/tests/lib/smf/testcase.yaml @@ -8,3 +8,7 @@ tests: libraries.smf.hierarchical: extra_configs: - CONFIG_SMF_ANCESTOR_SUPPORT=y + libraries.smf.initial_transition: + extra_configs: + - CONFIG_SMF_ANCESTOR_SUPPORT=y + - CONFIG_SMF_INITIAL_TRANSITION=y From 52b02469645f1030c409370b1231532934d0e44d Mon Sep 17 00:00:00 2001 From: Glenn Andrews Date: Tue, 13 Feb 2024 20:37:18 -0800 Subject: [PATCH 0098/2402] Lib: SMF: Fix `smf_set_terminate` function typo. Fixed where `smf_set_terminate` was written `smf_terminate` Signed-off-by: Glenn Andrews --- doc/services/smf/index.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/services/smf/index.rst b/doc/services/smf/index.rst index bc745c0acee..126c47e63b3 100644 --- a/doc/services/smf/index.rst +++ b/doc/services/smf/index.rst @@ -129,11 +129,11 @@ calls :c:func:`smf_set_state`. State Machine Termination ========================= -To terminate the state machine, the :c:func:`smf_terminate` function should -be called. It can be called from the entry, run, or exit action. The +To terminate the state machine, the :c:func:`smf_set_terminate` function +should be called. It can be called from the entry, run, or exit action. The function takes a non-zero user defined value that's returned by the :c:func:`smf_run_state` function. The function has the following prototype: -``void smf_terminate(smf_ctx *ctx, int32_t val)`` +``void smf_set_terminate(smf_ctx *ctx, int32_t val)`` Flat State Machine Example ========================== From 52453116b5b88a2af8cb256c2bab84594042d2ee Mon Sep 17 00:00:00 2001 From: Glenn Andrews Date: Tue, 13 Feb 2024 20:44:10 -0800 Subject: [PATCH 0099/2402] Lib: SMF: Add Doxygen commands. Added Doxygen markup. Signed-off-by: Glenn Andrews --- doc/services/smf/index.rst | 7 +++++++ include/zephyr/smf.h | 17 ++++++++++++++++- 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/doc/services/smf/index.rst b/doc/services/smf/index.rst index 126c47e63b3..eda2019f6eb 100644 --- a/doc/services/smf/index.rst +++ b/doc/services/smf/index.rst @@ -542,3 +542,10 @@ The statechart for this test is below. STATE_B -> STATE_C STATE_C -> STATE_D } + + + +API Reference +************* + +.. doxygengroup:: smf diff --git a/include/zephyr/smf.h b/include/zephyr/smf.h index b4aee26fa74..c7a2c4fbff4 100644 --- a/include/zephyr/smf.h +++ b/include/zephyr/smf.h @@ -4,11 +4,22 @@ * SPDX-License-Identifier: Apache-2.0 */ -/* State Machine Framework */ +/** + * @file + * + * @brief State Machine Framework header file + */ #ifndef ZEPHYR_INCLUDE_SMF_H_ #define ZEPHYR_INCLUDE_SMF_H_ +/** + * @brief State Machine Framework API + * @defgroup smf State Machine Framework API + * @ingroup os_services + * @{ + */ + #ifdef CONFIG_SMF_ANCESTOR_SUPPORT /** * @brief Macro to create a hierarchical state. @@ -187,4 +198,8 @@ int32_t smf_run_state(struct smf_ctx *ctx); } #endif +/** + * @} + */ + #endif /* ZEPHYR_INCLUDE_SMF_H_ */ From 3203bd660c6c8968e3047fb16b5721645f7ca696 Mon Sep 17 00:00:00 2001 From: Glenn Andrews Date: Sun, 3 Mar 2024 09:13:15 -0800 Subject: [PATCH 0100/2402] Lib: SMF: Update index.rst Incorporated changes requested by @keith-zephyr: 1. Grammar fix 2. Make explicit that transition to self in super-states is not supported Signed-off-by: Glenn Andrews --- doc/services/smf/index.rst | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/doc/services/smf/index.rst b/doc/services/smf/index.rst index eda2019f6eb..38e68cfcf51 100644 --- a/doc/services/smf/index.rst +++ b/doc/services/smf/index.rst @@ -102,10 +102,10 @@ function is used and it has the following prototype: .. note:: If :kconfig:option:`CONFIG_SMF_INITIAL_TRANSITION` is not set, :c:func:`smf_set_initial` and :c:func:`smf_set_state` function should - not be passed a parent state as they will not know which child state - to transition to. Transitioning to a parent state is OK if an initial - transition to a child state is defined. A well-formed HSM will have - initial transitions defined for all parent states. + not be passed a parent state as the parent state does not know which + child state to transition to. Transitioning to a parent state is OK + if an initial transition to a child state is defined. A well-formed + HSM will have initial transitions defined for all parent states. .. note:: While the state machine is running, smf_set_state should only be called from the Entry and Run functions. Calling smf_set_state from the @@ -353,9 +353,9 @@ When designing hierarchical state machines, the following should be considered: is called. - The parent_run function only executes if the child_run function does not call either :c:func:`smf_set_state` or :c:func:`smf_set_handled`. - - When a parent state intitiates a transition to self, the parents's exit - action is not called, e.g. instead of child_exit, parent_exit, parent_entry - it performs child_exit, parent_entry + - Transitions to self in super-states containing sub-states are not supported. + Transitions to self from the most-nested child state are supported and will + call the exit and entry function of the child state correctly. Event Driven State Machine Example ================================== From 46d6e2e09997b4c58fa8ffd3f63d4e19fa57f9bc Mon Sep 17 00:00:00 2001 From: Cong Nguyen Huu Date: Fri, 1 Mar 2024 14:43:49 +0700 Subject: [PATCH 0101/2402] nxp_s32_canxl: use RTD API instead the current can_nxp_s32_abort_msg() API On HAL RTD version 1.0.0, there is available Canexcel_Ip_DeactivateMD() API that have similar capabilities as can_nxp_s32_abort_msg() API, can use to instead. Remove the reg grp_ctrl and reg base_dsc_ctrl that unused after implementation this. Signed-off-by: Cong Nguyen Huu --- drivers/can/can_nxp_s32_canxl.c | 41 +++----------------------------- dts/arm/nxp/nxp_s32z27x_r52.dtsi | 8 ++----- 2 files changed, 5 insertions(+), 44 deletions(-) diff --git a/drivers/can/can_nxp_s32_canxl.c b/drivers/can/can_nxp_s32_canxl.c index 217d78981ca..75df1c65858 100644 --- a/drivers/can/can_nxp_s32_canxl.c +++ b/drivers/can/can_nxp_s32_canxl.c @@ -59,8 +59,6 @@ LOG_MODULE_REGISTER(nxp_s32_canxl, CONFIG_CAN_LOG_LEVEL); struct can_nxp_s32_config { const struct can_driver_config common; CANXL_SIC_Type *base_sic; - CANXL_GRP_CONTROL_Type *base_grp_ctrl; - CANXL_DSC_CONTROL_Type *base_dsc_ctrl; #ifdef CONFIG_CAN_NXP_S32_RX_FIFO CANXL_RXFIFO_Type * base_rx_fifo; CANXL_RXFIFO_CONTROL_Type *base_rx_fifo_ctrl; @@ -201,35 +199,6 @@ static int can_nxp_s32_start(const struct device *dev) return 0; } -static int can_nxp_s32_abort_msg(const struct can_nxp_s32_config *config, int mb_idx) -{ - uint32_t time_start = 0; - int ret = 0; - - Canexcel_Ip_EnterFreezeMode(config->instance); - - CanXL_ClearMsgBuffIntCmd(config->base_grp_ctrl, mb_idx); - CanXL_ClearMsgDescIntStatusFlag(config->base_grp_ctrl, mb_idx); - - time_start = k_uptime_get(); - /* Set system lock Status */ - (void)config->base_dsc_ctrl->DSCMBCTRLAR[mb_idx].SYSLOCK.DCSYSLOCK; - while (CanXL_GetDescControlStatus(config->base_dsc_ctrl, mb_idx) - == CANEXCEL_DESCNTSTATUS_LOCKED_HW) { - if (k_uptime_get() - time_start >= CAN_NXP_S32_TIMEOUT_MS) { - ret = CANEXCEL_STATUS_TIMEOUT; - break; - } - } - - /* Inactive descriptor */ - config->base_dsc_ctrl->DSCMBCTRLAR[mb_idx].ACT.DCACT = 0; - - Canexcel_Ip_ExitFreezeMode(config->instance); - - return ret; -} - static int can_nxp_s32_stop(const struct device *dev) { const struct can_nxp_s32_config *config = dev->config; @@ -251,7 +220,7 @@ static int can_nxp_s32_stop(const struct device *dev) arg = data->tx_cbs[alloc].arg; if (atomic_test_and_clear_bit(data->tx_allocs, alloc)) { - if (can_nxp_s32_abort_msg(config, + if (Canexcel_Ip_DeactivateMD(config->instance, ALLOC_IDX_TO_TXMB_IDX(alloc))) { LOG_ERR("Can't abort message !"); }; @@ -469,7 +438,7 @@ static void can_nxp_s32_remove_rx_filter(const struct device *dev, int filter_id Canexcel_Ip_ExitFreezeMode(config->instance); #else - if (can_nxp_s32_abort_msg(config, mb_indx)) { + if (Canexcel_Ip_DeactivateMD(config->instance, mb_indx)) { LOG_ERR("Can't abort message !"); }; #endif @@ -798,7 +767,7 @@ static void can_nxp_s32_err_callback(const struct device *dev, arg = data->tx_cbs[alloc].arg; if (atomic_test_and_clear_bit(data->tx_allocs, alloc)) { - if (can_nxp_s32_abort_msg(config, + if (Canexcel_Ip_DeactivateMD(config->instance, ALLOC_IDX_TO_TXMB_IDX(alloc))) { LOG_ERR("Can't abort message !"); }; @@ -1184,10 +1153,6 @@ static const struct can_driver_api can_nxp_s32_driver_api = { static struct can_nxp_s32_config can_nxp_s32_config_##n = { \ .common = CAN_DT_DRIVER_CONFIG_INST_GET(n, CAN_NXP_S32_MAX_BITRATE), \ .base_sic = (CANXL_SIC_Type *)DT_INST_REG_ADDR_BY_NAME(n, sic), \ - .base_grp_ctrl = (CANXL_GRP_CONTROL_Type *) \ - DT_INST_REG_ADDR_BY_NAME(n, grp_ctrl), \ - .base_dsc_ctrl = (CANXL_DSC_CONTROL_Type *) \ - DT_INST_REG_ADDR_BY_NAME(n, dsc_ctrl), \ IF_ENABLED(CONFIG_CAN_NXP_S32_RX_FIFO, \ (.base_rx_fifo = (CANXL_RXFIFO_Type *) \ DT_INST_REG_ADDR_BY_NAME(n, rx_fifo), \ diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi index 920f519da0f..c212400a691 100644 --- a/dts/arm/nxp/nxp_s32z27x_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi @@ -694,11 +694,9 @@ can0: can@4741b000 { compatible = "nxp,s32-canxl"; reg = <0x4741b000 0x1000>, - <0x47426000 0x1000>, - <0x47424000 0x1000>, <0x47423000 0x1000>, <0x47425000 0x1000>; - reg-names = "sic", "grp_ctrl", "dsc_ctrl", "rx_fifo", "rx_fifo_ctrl"; + reg-names = "sic", "rx_fifo", "rx_fifo_ctrl"; status = "disabled"; interrupts = , ; @@ -709,11 +707,9 @@ can1: can@4751b000 { compatible = "nxp,s32-canxl"; reg = <0x4751b000 0x1000>, - <0x47526000 0x1000>, - <0x47524000 0x1000>, <0x47523000 0x1000>, <0x47525000 0x1000>; - reg-names = "sic", "grp_ctrl", "dsc_ctrl", "rx_fifo", "rx_fifo_ctrl"; + reg-names = "sic", "rx_fifo", "rx_fifo_ctrl"; status = "disabled"; interrupts = , ; From 894503c758819f4badcfd90d09d91de315bb0734 Mon Sep 17 00:00:00 2001 From: "Mike J. Chen" Date: Wed, 28 Feb 2024 14:25:31 -0800 Subject: [PATCH 0102/2402] nvs: improve nvs_flash_cmp_const() Replace the use of a memcmp of a temp buffer filled with the comparison value with a direct comparison of the read buffer contents. Improves speed of the function (no more memset() call) and reduces stack usage. Signed-off-by: Mike J. Chen --- subsys/fs/nvs/nvs.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/subsys/fs/nvs/nvs.c b/subsys/fs/nvs/nvs.c index 8c4575700a8..ef35e677710 100644 --- a/subsys/fs/nvs/nvs.c +++ b/subsys/fs/nvs/nvs.c @@ -237,18 +237,24 @@ static int nvs_flash_cmp_const(struct nvs_fs *fs, uint32_t addr, uint8_t value, { int rc; size_t bytes_to_cmp, block_size; - uint8_t cmp[NVS_BLOCK_SIZE]; + uint8_t buf[NVS_BLOCK_SIZE]; block_size = NVS_BLOCK_SIZE & ~(fs->flash_parameters->write_block_size - 1U); - (void)memset(cmp, value, block_size); while (len) { bytes_to_cmp = MIN(block_size, len); - rc = nvs_flash_block_cmp(fs, addr, cmp, bytes_to_cmp); + rc = nvs_flash_rd(fs, addr, buf, bytes_to_cmp); if (rc) { return rc; } + + for (size_t i = 0; i < bytes_to_cmp; i++) { + if (buf[i] != value) { + return 1; + } + } + len -= bytes_to_cmp; addr += bytes_to_cmp; } From 705d579685408ddb3c14481d441e443f0e40df12 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Thu, 8 Feb 2024 17:26:06 +0200 Subject: [PATCH 0103/2402] drivers: dma: dma_nxp_edma: allow channel re-configuration Currently, the state transition function doesn't allow the re-configuration of an already configured channel (i.e: CHAN_CONFIGURED -> CHAN_CONFIGURED transition). This causes problems when using `pulseaudio` and `SOF` because the same channel ends up being configured multiple times in the beginning due to how pulse seems to work. Logically speaking, re-configuring an already configured channel is not wrong so this commit solves the issue by allowing the CHAN_CONFIGURED -> CHAN_CONFIGURED transition. Signed-off-by: Laurentiu Mihalcea --- drivers/dma/dma_nxp_edma.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dma_nxp_edma.h b/drivers/dma/dma_nxp_edma.h index 797e9b971d0..6f4ac669483 100644 --- a/drivers/dma/dma_nxp_edma.h +++ b/drivers/dma/dma_nxp_edma.h @@ -241,7 +241,8 @@ static inline int channel_change_state(struct edma_channel *chan, } break; case CHAN_STATE_CONFIGURED: - if (next != CHAN_STATE_STARTED) { + if (next != CHAN_STATE_STARTED && + next != CHAN_STATE_CONFIGURED) { return -EPERM; } break; From a969b36fe053454008ab0b225c864b059c087d13 Mon Sep 17 00:00:00 2001 From: Peter Mitsis Date: Thu, 18 Jan 2024 14:50:06 -0500 Subject: [PATCH 0104/2402] arch: xtensa: Add HiFi Kconfig options Adds HiFi Kconfig options to xtensa Signed-off-by: Peter Mitsis --- arch/xtensa/Kconfig | 47 ++++++++++++++++++++++++++++++++ soc/intel/intel_adsp/ace/Kconfig | 2 ++ 2 files changed, 49 insertions(+) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index aa888e8331a..27153bad4cf 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -93,6 +93,53 @@ config XTENSA_NUM_SPIN_RELAX_NOPS Specify the number of NOPs in Xtensa specific arch_spin_relax(). +menu "Xtensa HiFi Options" + +config XTENSA_CPU_HAS_HIFI + bool + +config XTENSA_CPU_HAS_HIFI3 + select XTENSA_CPU_HAS_HIFI + bool + +config XTENSA_CPU_HAS_HIFI4 + select XTENSA_CPU_HAS_HIFI + bool + +# Selected when at least one XTENSA_HIFIn version has been configured +config XTENSA_HIFI + bool + +if XTENSA_CPU_HAS_HIFI + +config XTENSA_HIFI3 + bool "HiFi3 AudioEngine instructions" + depends on XTENSA_CPU_HAS_HIFI3 + default y + select XTENSA_HIFI + help + This option enables HiFi 3 instruction support. + +config XTENSA_HIFI4 + bool "HiFi4 AudioEngine instructions" + depends on XTENSA_CPU_HAS_HIFI4 + default y + select XTENSA_HIFI + help + This option enables HiFi 4 instruction support. + +config XTENSA_HIFI_SHARING + bool "HiFi register sharing" + depends on XTENSA_HIFI + help + This option enables preservation of the hardware HiFi registers + across context switches to allow multiple threads to perform + concurrent HiFi operations. + +endif # XTENSA_CPU_HAS_HIFI + +endmenu # Xtensa HiFi Options + if CPU_HAS_MMU config XTENSA_MMU diff --git a/soc/intel/intel_adsp/ace/Kconfig b/soc/intel/intel_adsp/ace/Kconfig index 162d34daa34..17de11a36ff 100644 --- a/soc/intel/intel_adsp/ace/Kconfig +++ b/soc/intel/intel_adsp/ace/Kconfig @@ -11,6 +11,8 @@ config SOC_SERIES_INTEL_ADSP_ACE select DW_ICTL_ACE select SOC_HAS_RUNTIME_NUM_CPUS select HAS_PM + select XTENSA_CPU_HAS_HIFI3 + select XTENSA_CPU_HAS_HIFI4 config SOC_INTEL_COMM_WIDGET bool "Intel Communication Widget driver" From 520c8c22834ac9f5266ca364336c85fb97257f40 Mon Sep 17 00:00:00 2001 From: Peter Mitsis Date: Wed, 10 Jan 2024 11:44:43 -0500 Subject: [PATCH 0105/2402] arch: xtensa: Add space for HiFi registers Updates the xtensa_irq_base_save_area structure to include space for saving/restoring the HiFi AudioEngine registers used by CP1. The starting address of these HiFi AE registers also needs to be referenced from assembly, so it is added to the set of symbols symbols for which we need an offset to be auto-generated. Signed-off-by: Peter Mitsis --- arch/xtensa/core/offsets/offsets.c | 4 ++++ arch/xtensa/include/xtensa_asm2_context.h | 13 +++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/xtensa/core/offsets/offsets.c b/arch/xtensa/core/offsets/offsets.c index 8fca6962d3d..df3c4f8cae6 100644 --- a/arch/xtensa/core/offsets/offsets.c +++ b/arch/xtensa/core/offsets/offsets.c @@ -61,6 +61,10 @@ GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu14); GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu15); #endif +#if defined(CONFIG_XTENSA_HIFI_SHARING) +GEN_OFFSET_SYM(_xtensa_irq_bsa_t, hifi); +#endif + #ifdef CONFIG_USERSPACE GEN_OFFSET_SYM(_thread_arch_t, psp); GEN_OFFSET_SYM(_thread_arch_t, ptables); diff --git a/arch/xtensa/include/xtensa_asm2_context.h b/arch/xtensa/include/xtensa_asm2_context.h index 366bea47bab..f06dff077d4 100644 --- a/arch/xtensa/include/xtensa_asm2_context.h +++ b/arch/xtensa/include/xtensa_asm2_context.h @@ -8,6 +8,7 @@ #include #include +#include /* * Stack frame layout for a saved processor context, in memory order, @@ -106,6 +107,18 @@ struct xtensa_irq_base_save_area { uintptr_t fpu15; #endif +#if defined(CONFIG_XTENSA_HIFI_SHARING) + + /* + * Carve space for the registers used by the HiFi audio engine + * coprocessor (which is always CP1). Carve additional space to + * manage alignment at run-time as we can not yet guarantee the + * alignment of the BSA. + */ + + uint8_t hifi[XCHAL_CP1_SA_SIZE + XCHAL_CP1_SA_ALIGN]; +#endif + #if XCHAL_HAVE_THREADPTR uintptr_t threadptr; #endif From b0e527340e109c04434ce21c27d9e4a12602f136 Mon Sep 17 00:00:00 2001 From: Peter Mitsis Date: Wed, 10 Jan 2024 15:58:32 -0500 Subject: [PATCH 0106/2402] arch: xtensa: save/restore HiFi AudioEngine regs Adds the necessary code required to unconditionally save/restore the HiFi AE registers. The macros xchal_cp1_load and xchal_cp1_store are defined in the Xtensa HAL. Signed-off-by: Peter Mitsis --- arch/xtensa/core/CMakeLists.txt | 1 + arch/xtensa/core/userspace.S | 4 +++ arch/xtensa/core/xtensa_asm2_util.S | 9 +++++ arch/xtensa/core/xtensa_hifi.S | 53 +++++++++++++++++++++++++++++ arch/xtensa/include/xtensa_asm2_s.h | 10 ++++++ 5 files changed, 77 insertions(+) create mode 100644 arch/xtensa/core/xtensa_hifi.S diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index e9271d4982f..7119c1046c7 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -27,6 +27,7 @@ zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S) zephyr_library_sources_ifdef(CONFIG_XTENSA_SYSCALL_USE_HELPER syscall_helper.c) zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) zephyr_library_sources_ifdef(CONFIG_SMP smp.c) +zephyr_library_sources_ifdef(CONFIG_XTENSA_HIFI_SHARING xtensa_hifi.S) zephyr_library_sources_ifdef( CONFIG_KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK diff --git a/arch/xtensa/core/userspace.S b/arch/xtensa/core/userspace.S index 22c005f8b41..c798e129762 100644 --- a/arch/xtensa/core/userspace.S +++ b/arch/xtensa/core/userspace.S @@ -87,6 +87,10 @@ end_loop: s32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET ODD_REG_SAVE +#if defined(CONFIG_XTENSA_HIFI_SHARING) + call0 _xtensa_hifi_save +#endif + call0 xtensa_save_high_regs l32i a2, a1, 0 diff --git a/arch/xtensa/core/xtensa_asm2_util.S b/arch/xtensa/core/xtensa_asm2_util.S index bdce3449c75..94e6aa1381d 100644 --- a/arch/xtensa/core/xtensa_asm2_util.S +++ b/arch/xtensa/core/xtensa_asm2_util.S @@ -160,6 +160,11 @@ _restore_context: FPU_REG_RESTORE #endif +#if defined(CONFIG_XTENSA_HIFI_SHARING) +.extern _xtensa_hifi_load + call0 _xtensa_hifi_load +#endif + l32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET wsr a0, SAR #if XCHAL_HAVE_LOOPS @@ -248,6 +253,10 @@ xtensa_switch: movi a0, _switch_restore_pc s32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET +#if defined(CONFIG_XTENSA_HIFI_SHARING) + call0 _xtensa_hifi_save +#endif + /* Now the high registers */ call0 xtensa_save_high_regs diff --git a/arch/xtensa/core/xtensa_hifi.S b/arch/xtensa/core/xtensa_hifi.S new file mode 100644 index 00000000000..3c311acab0f --- /dev/null +++ b/arch/xtensa/core/xtensa_hifi.S @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include + +/* + * Load the HiFi registers from the hifi buffer in the BSA. Round the address + * of this buffer up to XCHAL_CP1_SA_ALIGN bytes to guarantee the necessary + * alignment. + * + * Upon entry ... + * A0 - return address (do not modify) + * A1 - address of BSA (do not modify) + * A2 - available for use + * A3 - available for use + */ +.global _xtensa_hifi_load +.align 4 +_xtensa_hifi_load: + addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1) + movi a3, ~(XCHAL_CP1_SA_ALIGN - 1) + and a2, a2, a3 + + xchal_cp1_load a2 a3 a3 a3 a3 /* Only A2 and A3 are used by macro */ + + ret + +/* + * Save the HiFi registers into the hifi buffer in the BSA. Round the address + * of this buffer up to XCHAL_CP1_SA_ALIGN bytes to guarantee the necessary + * alignment. + * + * A0 - return address (do not modify) + * A1 - address of BSA (do not modify) + * A2 - available for use + * A3 - available for use + */ +.global _xtensa_hifi_save +.align 4 +_xtensa_hifi_save: + addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1) + movi a3, ~(XCHAL_CP1_SA_ALIGN - 1) + and a2, a2, a3 + + xchal_cp1_store a2 a3 a3 a3 a3 /* Only A2 and A3 are used by macro */ + + ret diff --git a/arch/xtensa/include/xtensa_asm2_s.h b/arch/xtensa/include/xtensa_asm2_s.h index c087672957e..98bba884f12 100644 --- a/arch/xtensa/include/xtensa_asm2_s.h +++ b/arch/xtensa/include/xtensa_asm2_s.h @@ -16,6 +16,10 @@ * only by the assembler. */ +#if defined(CONFIG_XTENSA_HIFI_SHARING) +.extern _xtensa_hifi_save +#endif + /* * SPILL_ALL_WINDOWS * @@ -184,6 +188,7 @@ #if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING) FPU_REG_SAVE #endif + .endm #ifdef CONFIG_XTENSA_MMU @@ -405,6 +410,11 @@ _xstack_returned_\@: s32i a2, a1, ___xtensa_irq_bsa_t_scratch_OFFSET ODD_REG_SAVE + +#if defined(CONFIG_XTENSA_HIFI_SHARING) + call0 _xtensa_hifi_save /* Save HiFi registers */ +#endif + call0 xtensa_save_high_regs l32i a2, a1, 0 From a07e7c65dab2a21f10831b837fe60a36fe145af5 Mon Sep 17 00:00:00 2001 From: Peter Mitsis Date: Wed, 17 Jan 2024 09:58:58 -0500 Subject: [PATCH 0107/2402] tests: Add test to verify HiFi save/restore Adds a test to verify the saving and restoration of the HiFi AudioEngine registers. Twice as many threads as there are CPUs are created and each thread sets its HiFi registers with a unique set of values. If after a context switch, the HiFi AE registers contain any unexpected data, we then know that the registers were either not saved or restored properly. Signed-off-by: Peter Mitsis --- .../xtensa/save_restore_hifi/CMakeLists.txt | 10 +++ tests/arch/xtensa/save_restore_hifi/prj.conf | 2 + .../arch/xtensa/save_restore_hifi/src/hifi.S | 65 ++++++++++++++++ .../arch/xtensa/save_restore_hifi/src/main.c | 77 +++++++++++++++++++ .../xtensa/save_restore_hifi/testcase.yaml | 6 ++ 5 files changed, 160 insertions(+) create mode 100644 tests/arch/xtensa/save_restore_hifi/CMakeLists.txt create mode 100644 tests/arch/xtensa/save_restore_hifi/prj.conf create mode 100644 tests/arch/xtensa/save_restore_hifi/src/hifi.S create mode 100644 tests/arch/xtensa/save_restore_hifi/src/main.c create mode 100644 tests/arch/xtensa/save_restore_hifi/testcase.yaml diff --git a/tests/arch/xtensa/save_restore_hifi/CMakeLists.txt b/tests/arch/xtensa/save_restore_hifi/CMakeLists.txt new file mode 100644 index 00000000000..cf5f827c5c1 --- /dev/null +++ b/tests/arch/xtensa/save_restore_hifi/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(save_restore_hifi) + +enable_language(C ASM) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources} src/hifi.S) diff --git a/tests/arch/xtensa/save_restore_hifi/prj.conf b/tests/arch/xtensa/save_restore_hifi/prj.conf new file mode 100644 index 00000000000..4ca3b23a59f --- /dev/null +++ b/tests/arch/xtensa/save_restore_hifi/prj.conf @@ -0,0 +1,2 @@ +CONFIG_ZTEST=y +CONFIG_XTENSA_HIFI_SHARING=y diff --git a/tests/arch/xtensa/save_restore_hifi/src/hifi.S b/tests/arch/xtensa/save_restore_hifi/src/hifi.S new file mode 100644 index 00000000000..79f7db73b18 --- /dev/null +++ b/tests/arch/xtensa/save_restore_hifi/src/hifi.S @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024, Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * hifi_get - Retrieve the HiFi aedX registers + */ +.global hifi_get +.align 4 +hifi_get: + entry a1, 32 + + ae_s64.i aed0, a2, 0 + ae_s64.i aed1, a2, 8 + ae_s64.i aed2, a2, 16 + ae_s64.i aed3, a2, 24 + ae_s64.i aed4, a2, 32 + ae_s64.i aed5, a2, 40 + ae_s64.i aed6, a2, 48 + ae_s64.i aed7, a2, 56 + + addi a2, a2, 64 + + ae_s64.i aed8, a2, 0 + ae_s64.i aed9, a2, 8 + ae_s64.i aed10, a2, 16 + ae_s64.i aed11, a2, 24 + ae_s64.i aed12, a2, 32 + ae_s64.i aed13, a2, 40 + ae_s64.i aed14, a2, 48 + ae_s64.i aed15, a2, 56 + + retw.n + +/* + * hifi_set - Set the HiFi aedX registers + */ +.global hifi_set +.align 4 +hifi_set: + entry a1, 32 + + ae_l64.i aed0, a2, 0 + ae_l64.i aed1, a2, 8 + ae_l64.i aed2, a2, 16 + ae_l64.i aed3, a2, 24 + ae_l64.i aed4, a2, 32 + ae_l64.i aed5, a2, 40 + ae_l64.i aed6, a2, 48 + ae_l64.i aed7, a2, 56 + + addi a2, a2, 64 + + ae_l64.i aed8, a2, 0 + ae_l64.i aed9, a2, 8 + ae_l64.i aed10, a2, 16 + ae_l64.i aed11, a2, 24 + ae_l64.i aed12, a2, 32 + ae_l64.i aed13, a2, 40 + ae_l64.i aed14, a2, 48 + ae_l64.i aed15, a2, 56 + + retw.n diff --git a/tests/arch/xtensa/save_restore_hifi/src/main.c b/tests/arch/xtensa/save_restore_hifi/src/main.c new file mode 100644 index 00000000000..97a331ba768 --- /dev/null +++ b/tests/arch/xtensa/save_restore_hifi/src/main.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2024, Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#define STACK_SIZE 1024 +#define NUM_THREADS (CONFIG_MP_MAX_NUM_CPUS * 2) + +K_THREAD_STACK_ARRAY_DEFINE(thread_stack, NUM_THREADS, STACK_SIZE); + +struct k_thread thread[NUM_THREADS]; + +static void thread_entry(void *p1, void *p2, void *p3) +{ + uint32_t i; + uint32_t j; + uint32_t index = (uint32_t)(uintptr_t)p1; + uint8_t init_regs[8 * 16] __aligned(16) = {0}; + uint8_t value_regs[8 * 16] __aligned(16) = {0}; + + if (index < (NUM_THREADS - 1)) { + k_thread_start(&thread[index + 1]); + } + + /* Initialize the AE regs with known values */ + + for (i = 0; i < sizeof(init_regs); i++) { + init_regs[i] = (index & 0xff); + } + + extern void hifi_set(uint8_t *aed_buffer); + extern void hifi_get(uint8_t *aed_buffer); + + hifi_set(init_regs); + + for (i = 0; i < 10; i++) { + k_yield(); /* Switch to a new thread */ + + /* + * Verify that the HiFi AE regs have not been corrupted + * by another thread. + */ + + hifi_get(value_regs); + + for (j = 0; j < sizeof(value_regs); j++) { + zassert_equal(value_regs[j], init_regs[j], + "Expected %u, got %u\n", + init_regs[j], value_regs[j]); + } + } +} + +ZTEST(hifi, test_register_sanity) +{ + int priority; + uint32_t i; + + priority = k_thread_priority_get(k_current_get()); + + /* Create twice as many threads as there are CPUs */ + + for (i = 0; i < NUM_THREADS; i++) { + k_thread_create(&thread[i], thread_stack[i], STACK_SIZE, + thread_entry, (void *)(uintptr_t)i, NULL, NULL, + priority - 1, 0, K_FOREVER); + + + } + + k_thread_start(&thread[0]); +} + +ZTEST_SUITE(hifi, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/arch/xtensa/save_restore_hifi/testcase.yaml b/tests/arch/xtensa/save_restore_hifi/testcase.yaml new file mode 100644 index 00000000000..1e84e5649b7 --- /dev/null +++ b/tests/arch/xtensa/save_restore_hifi/testcase.yaml @@ -0,0 +1,6 @@ +tests: + xtensa.save_restore_hifi.mtl: + platform_allow: intel_adsp/ace15_mtpm + tags: + - kernel + ignore_faults: true From fa3f2ee485309fee44fa7d78f7a53946983d53fa Mon Sep 17 00:00:00 2001 From: Andrzej Kuros Date: Tue, 6 Feb 2024 09:29:33 +0100 Subject: [PATCH 0108/2402] manifest: update hal_nordic revision MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit updates revision of hal_nordic repo. Signed-off-by: Andrzej Kuroś --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 087e2563203..22a127d08cf 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: dce8519f7da37b0a745237679fd3f88250b495ff + revision: daf875285120be6b2825969b7a0abc3f415b248d path: modules/hal/nordic groups: - hal From ed55e4abd6a092e22f41c22ee7bdc2bed9de511f Mon Sep 17 00:00:00 2001 From: Andrzej Kuros Date: Thu, 1 Feb 2024 14:42:56 +0100 Subject: [PATCH 0109/2402] modules: hal_nordic: nrfx_glue add missing code for nrf_802154 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For use nRF 802.15.4 Radio Driver on nRF54L series there is necessary update for nrfx_glue.h file. It follows the pattern used for other nRF family members. Signed-off-by: Andrzej Kuroś --- modules/hal_nordic/nrfx/nrfx_glue.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/modules/hal_nordic/nrfx/nrfx_glue.h b/modules/hal_nordic/nrfx/nrfx_glue.h index 0edda440112..748c5eafd47 100644 --- a/modules/hal_nordic/nrfx/nrfx_glue.h +++ b/modules/hal_nordic/nrfx/nrfx_glue.h @@ -364,6 +364,10 @@ void nrfx_busy_wait(uint32_t usec_to_wait); #include <../src/nrf_802154_peripherals_nrf53.h> #define NRFX_PPI_CHANNELS_USED_BY_802154_DRV NRF_802154_DPPI_CHANNELS_USED_MASK #define NRFX_PPI_GROUPS_USED_BY_802154_DRV NRF_802154_DPPI_GROUPS_USED_MASK +#elif defined(NRF54L_SERIES) +#include <../src/nrf_802154_peripherals_nrf54l.h> +#define NRFX_PPI_CHANNELS_USED_BY_802154_DRV NRF_802154_DPPI_CHANNELS_USED_MASK +#define NRFX_PPI_GROUPS_USED_BY_802154_DRV NRF_802154_DPPI_GROUPS_USED_MASK #else #error Unsupported chip family #endif From 8e8d4af6c1b3edeb45cc4297a84264a99527b29e Mon Sep 17 00:00:00 2001 From: Andrzej Kuros Date: Mon, 5 Feb 2024 12:13:10 +0100 Subject: [PATCH 0110/2402] drivers: ieee802154_nrf5: Use Radio IRQ number from DT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Used RADIO_IRQ number is based on information provided by DT rather than direct use of RADIO_IRQn. Signed-off-by: Andrzej Kuroś --- drivers/ieee802154/ieee802154_nrf5.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/ieee802154/ieee802154_nrf5.c b/drivers/ieee802154/ieee802154_nrf5.c index 39891c635c9..d5bb4b33058 100644 --- a/drivers/ieee802154/ieee802154_nrf5.c +++ b/drivers/ieee802154/ieee802154_nrf5.c @@ -727,9 +727,8 @@ static void nrf5_irq_config(const struct device *dev) ARG_UNUSED(dev); #if !IS_ENABLED(CONFIG_IEEE802154_NRF5_EXT_IRQ_MGMT) - IRQ_CONNECT(RADIO_IRQn, NRF_802154_IRQ_PRIORITY, - nrf5_radio_irq, NULL, 0); - irq_enable(RADIO_IRQn); + IRQ_CONNECT(DT_IRQN(DT_NODELABEL(radio)), NRF_802154_IRQ_PRIORITY, nrf5_radio_irq, NULL, 0); + irq_enable(DT_IRQN(DT_NODELABEL(radio))); #endif } From 32da903ef8f079185b849c7c7c4f434f21453f53 Mon Sep 17 00:00:00 2001 From: Andrzej Kuros Date: Thu, 1 Feb 2024 14:42:27 +0100 Subject: [PATCH 0111/2402] boards: nrf54l15pdk_nrf54l15_cpuapp: add ieee802154 status okay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set status = "okay" for ieee802154 device tree node to allow use of ieee802154 on the nrf54l15pdk_nrf54l15_cpuapp board. Signed-off-by: Andrzej Kuroś --- boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts index 1e0245f6cc3..45d69531953 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -128,6 +128,10 @@ status = "okay"; }; +&ieee802154 { + status = "okay"; +}; + &rram0 { partitions { compatible = "fixed-partitions"; From 306d6c2290f5f86bf176e1dbe7036c0b19f27dd3 Mon Sep 17 00:00:00 2001 From: Andrzej Kuros Date: Tue, 6 Feb 2024 14:41:35 +0100 Subject: [PATCH 0112/2402] boards: nrf54l15pdk_nrf54l15_cpuapp: add temp status okay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set status = "okay" for temp device tree node to allow use of nRF 802.15.4 Radio Driver on the nrf54l15pdk_nrf54l15_cpuapp board. Signed-off-by: Andrzej Kuroś --- boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts index 45d69531953..e8b13920a19 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -132,6 +132,10 @@ status = "okay"; }; +&temp { + status = "okay"; +}; + &rram0 { partitions { compatible = "fixed-partitions"; From 87c427609e163e7f88fd9a2dc063ebd3b426ba2c Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Tue, 16 Jan 2024 14:09:59 +0000 Subject: [PATCH 0113/2402] doc: develop: test: Blackbox explanation Documentation file for blackbox tests added. Signed-off-by: Lukasz Mrugala --- doc/develop/test/index.rst | 1 + .../test/twister/sample_blackbox_test.py | 93 +++++++++++++ doc/develop/test/twister/twister_blackbox.rst | 127 ++++++++++++++++++ 3 files changed, 221 insertions(+) create mode 100644 doc/develop/test/twister/sample_blackbox_test.py create mode 100644 doc/develop/test/twister/twister_blackbox.rst diff --git a/doc/develop/test/index.rst b/doc/develop/test/index.rst index c8c67d20ef6..9f43f86f8bc 100644 --- a/doc/develop/test/index.rst +++ b/doc/develop/test/index.rst @@ -8,6 +8,7 @@ Testing ztest twister + twister/twister_blackbox pytest coverage BabbleSim diff --git a/doc/develop/test/twister/sample_blackbox_test.py b/doc/develop/test/twister/sample_blackbox_test.py new file mode 100644 index 00000000000..c638af13dd8 --- /dev/null +++ b/doc/develop/test/twister/sample_blackbox_test.py @@ -0,0 +1,93 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +import importlib +import mock +import os +import pytest +import sys +import json + +from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +class TestDummy: + TESTDATA_X = [ + ("smoke", 5), + ("acceptance", 6), + ] + + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, "scripts", "twister") + cls.loader = importlib.machinery.SourceFileLoader("__main__", apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @pytest.mark.parametrize( + "level, expected_tests", TESTDATA_X, ids=["smoke", "acceptance"] + ) + @mock.patch.object(TestPlan, "TESTSUITE_FILENAME", testsuite_filename_mock) + def test_level(self, capfd, out_path, level, expected_tests): + # Select platforms used for the tests + test_platforms = ["qemu_x86", "frdm_k64f"] + # Select test root + path = os.path.join(TEST_DATA, "tests") + config_path = os.path.join(TEST_DATA, "test_config.yaml") + + # Set flags for our Twister command as a list of strs + args = ( + # Flags related to the generic test setup: + # * Control the level of detail in stdout/err + # * Establish the output directory + # * Select Zephyr tests to use + # * Control whether to only build or build and run aforementioned tests + ["-i", "--outdir", out_path, "-T", path, "-y"] + # Flags under test + + ["--level", level] + # Flags required for the test + + ["--test-config", config_path] + # Flags related to platform selection + + [ + val + for pair in zip(["-p"] * len(test_platforms), test_platforms) + for val in pair + ] + ) + + # First, provide the args variable as our Twister command line arguments. + # Then, catch the exit code in the sys_exit variable. + with mock.patch.object(sys, "argv", [sys.argv[0]] + args), pytest.raises( + SystemExit + ) as sys_exit: + # Execute the Twister call itself. + self.loader.exec_module(self.twister_module) + + # Check whether the Twister call succeeded + assert str(sys_exit.value) == "0" + + # Access to the test file output + with open(os.path.join(out_path, "testplan.json")) as f: + j = json.load(f) + filtered_j = [ + (ts["platform"], ts["name"], tc["identifier"]) + for ts in j["testsuites"] + for tc in ts["testcases"] + if "reason" not in tc + ] + + # Read stdout and stderr to out and err variables respectively + out, err = capfd.readouterr() + # Rewrite the captured buffers to stdout and stderr so the user can still read them + sys.stdout.write(out) + sys.stderr.write(err) + + # Test-relevant checks + assert expected_tests == len(filtered_j) diff --git a/doc/develop/test/twister/twister_blackbox.rst b/doc/develop/test/twister/twister_blackbox.rst new file mode 100644 index 00000000000..fc6231fb90d --- /dev/null +++ b/doc/develop/test/twister/twister_blackbox.rst @@ -0,0 +1,127 @@ +.. _twister_blackbox: + +Twister blackbox tests +###################### + +This guide aims to explain the structure of a test file so the reader will be able +to understand existing files and create their own. All developers should fix any tests +they break and create new ones when introducing new features, so this knowledge is +important for any Twister developer. + +Basics +****** + +Twister blackbox tests are written in python, using the ``pytest`` library. +Read up on it :ref:`here ` . +Auxiliary test data follows whichever format it was in originally. +Tests and data are wholly contained in the :zephyr_file:`scripts/tests/twister_blackbox` +directory and prepended with ``test_``. + +Blackbox tests should not be aware of the internal twister code. Instead, they should +call twister as user would and check the results. + +Sample test file +**************** + +.. literalinclude:: ./sample_blackbox_test.py + :language: python + :linenos: + +Comparison with CLI +******************* + +Test above runs the command + +.. code-block:: console + + twister -i --outdir $OUTDIR -T $TEST_DATA/tests -y --level $LEVEL + --test-config $TEST_DATA/test_config.yaml -p qemu_x86 -p frdm_k64f + +It presumes a CLI with the ``zephyr-env.sh`` or ``zephyr-env.cmd`` already run. + +Such a test provides us with all the outputs we typically expect of a Twister run thanks to +``importlib`` 's ``exec_module()`` [#f1]_ . +We can easily set up all flags that we expect from a Twister call via ``args`` variable [#f2]_ . +We can check the standard output or stderr in ``out`` and ``err`` variables. + +Beside the standard outputs, we can also investigate the file outputs, normally placed in +``twister-out`` directories. Most of the time, we will use the ``out_path`` fixture in conjunction +with ``--outdir`` flag (L52) to keep test-generated files in temporary directories. +Typical files read in blackbox tests are ``testplan.json`` , ``twister.xml`` and ``twister.log`` . + +Other functionalities +********************* + +Decorators +========== + +* ``@pytest.mark.usefixtures('clear_log')`` + - allows us to use ``clear_log`` fixture from ``conftest.py`` . + The fixture is to become ``autouse`` in the future. + After that, this decorator can be removed. +* ``@pytest.mark.parametrize('level, expected_tests', TESTDATA_X, ids=['smoke', 'acceptance'])`` + - this is an example of ``pytest`` 's test parametrization. + Read up on it `here `__. + TESTDATAs are most often declared as class fields. +* ``@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock)`` + - this decorator allows us to use only tests defined in the ``test_data`` and + ignore the Zephyr testcases in the ``tests`` directory. **Note that all ``test_data`` + tests use** ``test_data.yaml`` **as a filename, not** ``testcase.yaml`` **!** + Read up on the ``mock`` library + `here `__. + +Fixtures +======== + +Blackbox tests use ``pytest`` 's fixtures, further reading on which is available +`here `__. + +If you would like to add your own fixtures, +consider whether they will be used in just one test file, or in many. + +* If in many, create such a fixture in the + :zephyr_file:`scripts/tests/twister_blackbox/conftest.py` file. + + - :zephyr_file:`scripts/tests/twister_blackbox/conftest.py` already contains some fixtures - + take a look there for an example. +* If in just one, declare it in that file. + + - Consider using class fields instead - look at TESTDATAs for an example. + +How do I... +*********** + +Call Twister multiple times in one test? +======================================== + +Sometimes we want to test something that requires prior Twister use. ``--test-only`` +flag would be a typical example, as it is to be coupled with previous ``--build-only`` +Twister call. How should we approach that? + +If we just call the ``importlib`` 's ``exec_module`` two times, we will experience log +duplication. ``twister.log`` will duplicate every line (triplicate if we call it three times, etc.) +instead of overwriting the log or appending to the end of it. + +It is caused by the use of logger module variables in the Twister files. +Thus us executing the module again causes the loggers to have multiple handles. + +To overcome this, between the calls you ought to use + +.. code:: python + + capfd.readouterr() # To remove output from the buffer + # Note that if you want output from all runs after each other, + # skip this line. + clear_log_in_test() # To remove log duplication + + +------ + +.. rubric:: Footnotes + +.. [#f1] Take note of the ``setup_class()`` class function, which allows us to run + ``twister`` python file as if it were called directly + (bypassing the ``__name__ == '__main__'`` check). + +.. [#f2] We advise you to keep the first section of ``args`` definition intact in almost all + of your tests, as it is used for the common test setup. From b583f3ad4bb054978f25d5f2b18ec18c39220490 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Mon, 15 Jan 2024 15:09:13 +0000 Subject: [PATCH 0114/2402] scripts: tests: Blackbox test expansion - shuffle Adds tests related to the shuffling of the tests: * -B, --subset * --shuffle-tests * --shuffle-tests-seed Signed-off-by: Lukasz Mrugala --- .../tests/twister_blackbox/test_shuffle.py | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_shuffle.py diff --git a/scripts/tests/twister_blackbox/test_shuffle.py b/scripts/tests/twister_blackbox/test_shuffle.py new file mode 100644 index 00000000000..afa10e106b2 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_shuffle.py @@ -0,0 +1,79 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions related to the shuffling of the test order. +""" + +import importlib +import mock +import os +import pytest +import re +import sys +import json + +from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +class TestShuffle: + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @pytest.mark.parametrize( + 'seed, ratio, expected_order', + [ + ('123', '1/2', ['dummy.agnostic.group1.subgroup1', 'dummy.agnostic.group1.subgroup2']), + ('123', '2/2', ['dummy.agnostic.group2', 'dummy.device.group']), + ('321', '1/2', ['dummy.agnostic.group1.subgroup1', 'dummy.agnostic.group2']), + ('321', '2/2', ['dummy.device.group', 'dummy.agnostic.group1.subgroup2']), + ('123', '1/3', ['dummy.agnostic.group1.subgroup1', 'dummy.agnostic.group1.subgroup2']), + ('123', '2/3', ['dummy.agnostic.group2']), + ('123', '3/3', ['dummy.device.group']), + ('321', '1/3', ['dummy.agnostic.group1.subgroup1', 'dummy.agnostic.group2']), + ('321', '2/3', ['dummy.device.group']), + ('321', '3/3', ['dummy.agnostic.group1.subgroup2']) + ], + ids=['first half, 123', 'second half, 123', 'first half, 321', 'second half, 321', + 'first third, 123', 'middle third, 123', 'last third, 123', + 'first third, 321', 'middle third, 321', 'last third, 321'] + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_shuffle_tests(self, out_path, seed, ratio, expected_order): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + ['--shuffle-tests', '--shuffle-tests-seed', seed] + \ + ['--subset', ratio] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + testcases = [re.sub(r'\.assert[^\.]*?$', '', j[2]) for j in filtered_j] + testsuites = list(dict.fromkeys(testcases)) + + assert testsuites == expected_order + + assert str(sys_exit.value) == '0' From a815f70177cccdabef1a047ba7f9ebab6dbd28c1 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Mon, 5 Feb 2024 14:45:28 +0000 Subject: [PATCH 0115/2402] scripts: tests: Blackbox test expansion - config Adds tests related to the flags concerned with config files: * --alt-config-root Signed-off-by: Lukasz Mrugala --- scripts/tests/twister_blackbox/test_config.py | 58 +++++++++++++++++++ .../dummy/agnostic/group2/test_data.yaml | 12 ++++ 2 files changed, 70 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_config.py create mode 100644 scripts/tests/twister_blackbox/test_data/alt-test-configs/dummy/agnostic/group2/test_data.yaml diff --git a/scripts/tests/twister_blackbox/test_config.py b/scripts/tests/twister_blackbox/test_config.py new file mode 100644 index 00000000000..369fa4f1dc5 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_config.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions related to test configuration files. +""" + +import importlib +import mock +import os +import pytest +import sys +import json + +from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +class TestConfig: + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_alt_config_root(self, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + alt_config_root = os.path.join(TEST_DATA, 'alt-test-configs', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + ['--alt-config-root', alt_config_root] + \ + ['--tag', 'alternate-config-root'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert str(sys_exit.value) == '0' + + assert len(filtered_j) == 3 diff --git a/scripts/tests/twister_blackbox/test_data/alt-test-configs/dummy/agnostic/group2/test_data.yaml b/scripts/tests/twister_blackbox/test_data/alt-test-configs/dummy/agnostic/group2/test_data.yaml new file mode 100644 index 00000000000..cf3d78222e2 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/alt-test-configs/dummy/agnostic/group2/test_data.yaml @@ -0,0 +1,12 @@ +tests: + dummy.agnostic.group2.alt: + platform_allow: + - native_sim + - qemu_x86 + - qemu_x86_64 + integration_platforms: + - native_sim + slow: true + tags: + - agnostic + - alternate-config-root From 9d8600136d444101124fd2480d173441f9ae7a02 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Mon, 5 Feb 2024 14:58:52 +0000 Subject: [PATCH 0116/2402] scripts: tests: Move blackbox config tests to test_config.py Moved tests related to the test_config.yaml files to test_config.py. * test_level Signed-off-by: Lukasz Mrugala --- scripts/tests/twister_blackbox/test_config.py | 35 ++++++++++++++ .../tests/twister_blackbox/test_testplan.py | 46 ++----------------- 2 files changed, 40 insertions(+), 41 deletions(-) diff --git a/scripts/tests/twister_blackbox/test_config.py b/scripts/tests/twister_blackbox/test_config.py index 369fa4f1dc5..eb55962e3c4 100644 --- a/scripts/tests/twister_blackbox/test_config.py +++ b/scripts/tests/twister_blackbox/test_config.py @@ -56,3 +56,38 @@ def test_alt_config_root(self, out_path): assert str(sys_exit.value) == '0' assert len(filtered_j) == 3 + + @pytest.mark.parametrize( + 'level, expected_tests', + [ + ('smoke', 5), + ('acceptance', 6), + ], + ids=['smoke', 'acceptance'] + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_level(self, out_path, level, expected_tests): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + config_path = os.path.join(TEST_DATA, 'test_config.yaml') + args = ['-i','--outdir', out_path, '-T', path, '--level', level, '-y', + '--test-config', config_path] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert str(sys_exit.value) == '0' + + assert expected_tests == len(filtered_j) diff --git a/scripts/tests/twister_blackbox/test_testplan.py b/scripts/tests/twister_blackbox/test_testplan.py index 7316209b1af..30aecbf1c3d 100644 --- a/scripts/tests/twister_blackbox/test_testplan.py +++ b/scripts/tests/twister_blackbox/test_testplan.py @@ -20,10 +20,6 @@ class TestTestPlan: TESTDATA_1 = [ - ('smoke', 5), - ('acceptance', 6), - ] - TESTDATA_2 = [ ('dummy.agnostic.group2.assert1', SystemExit, 3), ( os.path.join('scripts', 'tests', 'twister_blackbox', 'test_data', 'tests', @@ -33,11 +29,11 @@ class TestTestPlan: None ), ] - TESTDATA_3 = [ + TESTDATA_2 = [ ('buildable', 6), ('runnable', 5), ] - TESTDATA_4 = [ + TESTDATA_3 = [ (True, 1), (False, 6), ] @@ -53,41 +49,9 @@ def setup_class(cls): def teardown_class(cls): pass - @pytest.mark.parametrize( - 'level, expected_tests', - TESTDATA_1, - ids=['smoke', 'acceptance'] - ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) - def test_level(self, out_path, level, expected_tests): - test_platforms = ['qemu_x86', 'frdm_k64f'] - path = os.path.join(TEST_DATA, 'tests', 'dummy') - config_path = os.path.join(TEST_DATA, 'test_config.yaml') - args = ['-i','--outdir', out_path, '-T', path, '--level', level, '-y', - '--test-config', config_path] + \ - [val for pair in zip( - ['-p'] * len(test_platforms), test_platforms - ) for val in pair] - - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) - - with open(os.path.join(out_path, 'testplan.json')) as f: - j = json.load(f) - filtered_j = [ - (ts['platform'], ts['name'], tc['identifier']) \ - for ts in j['testsuites'] \ - for tc in ts['testcases'] if 'reason' not in tc - ] - - assert str(sys_exit.value) == '0' - - assert expected_tests == len(filtered_j) - @pytest.mark.parametrize( 'test, expected_exception, expected_subtest_count', - TESTDATA_2, + TESTDATA_1, ids=['valid', 'invalid'] ) @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) @@ -120,7 +84,7 @@ def test_subtest(self, out_path, test, expected_exception, expected_subtest_coun @pytest.mark.parametrize( 'filter, expected_count', - TESTDATA_3, + TESTDATA_2, ids=['buildable', 'runnable'] ) @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) @@ -150,7 +114,7 @@ def test_filter(self, out_path, filter, expected_count): @pytest.mark.parametrize( 'integration, expected_count', - TESTDATA_4, + TESTDATA_3, ids=['integration', 'no integration'] ) @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) From 0db5d5194aded27064aaa4d7bf74969d8d78d5e4 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Fri, 16 Feb 2024 13:42:37 +0000 Subject: [PATCH 0117/2402] scripts: tests: Blackbox test expansion - footprint Adds tests related to report flags: * --compare-report * -m, --last-metrics * -D, --all-deltas * --footprint-threshold * --show-footprint * --footprint-from-buildlog Signed-off-by: Lukasz Mrugala --- .../tests/twister_blackbox/test_footprint.py | 472 ++++++++++++++++++ 1 file changed, 472 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_footprint.py diff --git a/scripts/tests/twister_blackbox/test_footprint.py b/scripts/tests/twister_blackbox/test_footprint.py new file mode 100644 index 00000000000..67aee1ea448 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_footprint.py @@ -0,0 +1,472 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions related to memory footprints. +""" + +import importlib +import json +import mock +import os +import pytest +import sys + +from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock, clear_log_in_test +from twisterlib.testplan import TestPlan + + +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +class TestFootprint: + # Log printed when entering delta calculations + FOOTPRINT_LOG = 'running footprint_reports' + + # These warnings notify us that deltas were shown in log. + # Coupled with the code under test. + DELTA_WARNING_RELEASE = 'Deltas based on metrics from last release' + DELTA_WARNING_RUN = 'Deltas based on metrics from last run' + + # Size report key we modify to control for deltas + RAM_KEY = 'used_ram' + + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @pytest.mark.parametrize( + 'old_ram_multiplier, expect_delta_log', + [ + (0.75, True), + (1.25, False), + ], + ids=['footprint increased', 'footprint reduced'] + ) + def test_compare_report(self, caplog, out_path, old_ram_multiplier, expect_delta_log): + # First run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'device', 'group') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--enable-size-report'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + # Modify the older report so we can control the difference. + # Note: if footprint tests take too long, replace first run with a prepared twister.json + # That will increase test-to-code_under_test coupling, however. + with open(os.path.join(out_path, 'twister.json')) as f: + j = json.load(f) + for ts in j['testsuites']: + if 'reason' not in ts: + # We assume positive RAM usage. + ts[self.RAM_KEY] *= old_ram_multiplier + with open(os.path.join(out_path, 'twister.json'), 'w') as f: + f.write(json.dumps(j, indent=4)) + + report_path = os.path.join( + os.path.dirname(out_path), + f'{os.path.basename(out_path)}.1', + 'twister.json' + ) + + # Second run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--compare-report', report_path] + \ + ['--show-footprint'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + assert self.FOOTPRINT_LOG in caplog.text + + if expect_delta_log: + assert self.RAM_KEY in caplog.text + assert self.DELTA_WARNING_RELEASE in caplog.text, \ + 'Expected footprint deltas not logged.' + else: + assert self.RAM_KEY not in caplog.text + assert self.DELTA_WARNING_RELEASE not in caplog.text, \ + 'Unexpected footprint deltas logged.' + + def test_footprint_from_buildlog(self, out_path): + # First run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'device', 'group') + args = ['-i', '--outdir', out_path, '-T', path] + \ + [] + \ + ['--show-footprint'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + # Get values + old_values = [] + with open(os.path.join(out_path, 'twister.json')) as f: + j = json.load(f) + for ts in j['testsuites']: + if 'reason' not in ts: + assert self.RAM_KEY in ts + old_values += [ts[self.RAM_KEY]] + + # Second run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'device', 'group') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--footprint-from-buildlog'] + \ + ['--show-footprint'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + # Get values + new_values = [] + with open(os.path.join(out_path, 'twister.json')) as f: + j = json.load(f) + for ts in j['testsuites']: + if 'reason' not in ts: + assert self.RAM_KEY in ts + new_values += [ts[self.RAM_KEY]] + + # There can be false positives if our calculations become too accurate. + # Turn this test into a dummy (check only exit value) in such case. + assert sorted(old_values) != sorted(new_values), \ + 'Same values whether calculating size or using buildlog.' + + @pytest.mark.parametrize( + 'old_ram_multiplier, threshold, expect_delta_log', + [ + (0.75, 95, False), + (0.75, 25, True), + ], + ids=['footprint threshold not met', 'footprint threshold met'] + ) + def test_footprint_threshold(self, caplog, out_path, old_ram_multiplier, + threshold, expect_delta_log): + # First run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'device', 'group') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--enable-size-report'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + # Modify the older report so we can control the difference. + # Note: if footprint tests take too long, replace first run with a prepared twister.json + # That will increase test-to-code_under_test coupling, however. + with open(os.path.join(out_path, 'twister.json')) as f: + j = json.load(f) + for ts in j['testsuites']: + if 'reason' not in ts: + # We assume positive RAM usage. + ts[self.RAM_KEY] *= old_ram_multiplier + with open(os.path.join(out_path, 'twister.json'), 'w') as f: + f.write(json.dumps(j, indent=4)) + + report_path = os.path.join( + os.path.dirname(out_path), + f'{os.path.basename(out_path)}.1', + 'twister.json' + ) + + # Second run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path] + \ + [f'--footprint-threshold={threshold}'] + \ + ['--compare-report', report_path, '--show-footprint'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + assert self.FOOTPRINT_LOG in caplog.text + + if expect_delta_log: + assert self.RAM_KEY in caplog.text + assert self.DELTA_WARNING_RELEASE in caplog.text, \ + 'Expected footprint deltas not logged.' + else: + assert self.RAM_KEY not in caplog.text + assert self.DELTA_WARNING_RELEASE not in caplog.text, \ + 'Unexpected footprint deltas logged.' + + @pytest.mark.parametrize( + 'flags, old_ram_multiplier, expect_delta_log', + [ + ([], 0.75, False), + (['--show-footprint'], 0.75, True), + ], + ids=['footprint reduced, no show', 'footprint reduced, show'] + ) + def test_show_footprint(self, caplog, out_path, flags, old_ram_multiplier, expect_delta_log): + # First run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'device', 'group') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--enable-size-report'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + # Modify the older report so we can control the difference. + # Note: if footprint tests take too long, replace first run with a prepared twister.json + # That will increase test-to-code_under_test coupling, however. + with open(os.path.join(out_path, 'twister.json')) as f: + j = json.load(f) + for ts in j['testsuites']: + if 'reason' not in ts: + # We assume positive RAM usage. + ts[self.RAM_KEY] *= old_ram_multiplier + with open(os.path.join(out_path, 'twister.json'), 'w') as f: + f.write(json.dumps(j, indent=4)) + + report_path = os.path.join( + os.path.dirname(out_path), + f'{os.path.basename(out_path)}.1', + 'twister.json' + ) + + # Second run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path] + \ + flags + \ + ['--compare-report', report_path] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + print(args) + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + assert self.FOOTPRINT_LOG in caplog.text + + if expect_delta_log: + assert self.RAM_KEY in caplog.text + assert self.DELTA_WARNING_RELEASE in caplog.text, \ + 'Expected footprint deltas not logged.' + else: + assert self.RAM_KEY not in caplog.text + assert self.DELTA_WARNING_RELEASE not in caplog.text, \ + 'Unexpected footprint deltas logged.' + + @pytest.mark.parametrize( + 'old_ram_multiplier, expect_delta_log', + [ + (0.75, True), + (1.25, False), + ], + ids=['footprint increased', 'footprint reduced'] + ) + def test_last_metrics(self, caplog, out_path, old_ram_multiplier, expect_delta_log): + # First run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'device', 'group') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--enable-size-report'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + # Modify the older report so we can control the difference. + # Note: if footprint tests take too long, replace first run with a prepared twister.json + # That will increase test-to-code_under_test coupling, however. + with open(os.path.join(out_path, 'twister.json')) as f: + j = json.load(f) + for ts in j['testsuites']: + if 'reason' not in ts: + # We assume positive RAM usage. + ts[self.RAM_KEY] *= old_ram_multiplier + with open(os.path.join(out_path, 'twister.json'), 'w') as f: + f.write(json.dumps(j, indent=4)) + + report_path = os.path.join( + os.path.dirname(out_path), + f'{os.path.basename(out_path)}.1', + 'twister.json' + ) + + # Second run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--last-metrics'] + \ + ['--show-footprint'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + assert self.FOOTPRINT_LOG in caplog.text + + if expect_delta_log: + assert self.RAM_KEY in caplog.text + assert self.DELTA_WARNING_RUN in caplog.text, \ + 'Expected footprint deltas not logged.' + else: + assert self.RAM_KEY not in caplog.text + assert self.DELTA_WARNING_RUN not in caplog.text, \ + 'Unexpected footprint deltas logged.' + + second_logs = caplog.records + caplog.clear() + clear_log_in_test() + + # Third run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--compare-report', report_path] + \ + ['--show-footprint'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + # Since second run should use the same source as the third, we should compare them. + delta_logs = [ + record.getMessage() for record in second_logs \ + if self.RAM_KEY in record.getMessage() + ] + assert all([log in caplog.text for log in delta_logs]) + + @pytest.mark.parametrize( + 'old_ram_multiplier, expect_delta_log', + [ + (0.75, True), + (1.00, False), + (1.25, True), + ], + ids=['footprint increased', 'footprint constant', 'footprint reduced'] + ) + def test_all_deltas(self, caplog, out_path, old_ram_multiplier, expect_delta_log): + # First run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'device', 'group') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--enable-size-report'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + # Modify the older report so we can control the difference. + # Note: if footprint tests take too long, replace first run with a prepared twister.json + # That will increase test-to-code_under_test coupling, however. + with open(os.path.join(out_path, 'twister.json')) as f: + j = json.load(f) + for ts in j['testsuites']: + if 'reason' not in ts: + # We assume positive RAM usage. + ts[self.RAM_KEY] *= old_ram_multiplier + with open(os.path.join(out_path, 'twister.json'), 'w') as f: + f.write(json.dumps(j, indent=4)) + + report_path = os.path.join( + os.path.dirname(out_path), + f'{os.path.basename(out_path)}.1', + 'twister.json' + ) + + # Second run + test_platforms = ['frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--all-deltas'] + \ + ['--compare-report', report_path, '--show-footprint'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + assert self.FOOTPRINT_LOG in caplog.text + + if expect_delta_log: + assert self.RAM_KEY in caplog.text + assert self.DELTA_WARNING_RELEASE in caplog.text, \ + 'Expected footprint deltas not logged.' + else: + assert self.RAM_KEY not in caplog.text + assert self.DELTA_WARNING_RELEASE not in caplog.text, \ + 'Unexpected footprint deltas logged.' From d079701885c104cadf1667dfd1e940ed4f7e8fbb Mon Sep 17 00:00:00 2001 From: Wojciech Slenska Date: Mon, 4 Mar 2024 12:21:52 +0100 Subject: [PATCH 0118/2402] tracing: segger-sysview: fix compilation error SEGGER_SYSVIEW_RecordU32 function takes only two parameters, SEGGER_SYSVIEW_RecordU32x2 should be used instead. Signed-off-by: Wojciech Slenska --- subsys/tracing/sysview/tracing_sysview.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/tracing/sysview/tracing_sysview.h b/subsys/tracing/sysview/tracing_sysview.h index 8d6e90666f5..a7cb25c2748 100644 --- a/subsys/tracing/sysview/tracing_sysview.h +++ b/subsys/tracing/sysview/tracing_sysview.h @@ -641,7 +641,7 @@ void sys_trace_k_thread_info(struct k_thread *thread); SEGGER_SYSVIEW_RecordEndCallU32(TID_PM_DEVICE_RUNTIME_PUT, \ (uint32_t)ret) #define sys_port_trace_pm_device_runtime_put_async_enter(dev, delay) \ - SEGGER_SYSVIEW_RecordU32(TID_PM_DEVICE_RUNTIME_PUT_ASYNC, \ + SEGGER_SYSVIEW_RecordU32x2(TID_PM_DEVICE_RUNTIME_PUT_ASYNC, \ (uint32_t)(uintptr_t)dev, (uint32_t)delay.ticks) #define sys_port_trace_pm_device_runtime_put_async_exit(dev, delay, ret) \ SEGGER_SYSVIEW_RecordEndCallU32(TID_PM_DEVICE_RUNTIME_PUT_ASYNC, \ From 0e2a25b066776a98a95b755913960a53ee10b5b8 Mon Sep 17 00:00:00 2001 From: Arkadiusz Cholewinski Date: Tue, 6 Feb 2024 13:51:43 +0100 Subject: [PATCH 0119/2402] ci: coverage: add coverage analysis reports Extend codecov workflow to include coverage analysis. Signed-off-by: Arkadiusz Cholewinski Signed-off-by: Anas Nashif --- .github/workflows/codecov.yaml | 39 +- scripts/ci/coverage/coverage_analysis.py | 509 +++++++++++++++++++++++ 2 files changed, 543 insertions(+), 5 deletions(-) create mode 100644 scripts/ci/coverage/coverage_analysis.py diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 0b3755c7d9e..87ed7b963e0 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -90,6 +90,7 @@ jobs: export ZEPHYR_TOOLCHAIN_VARIANT=zephyr mkdir -p coverage/reports pip3 install gcovr==6.0 + ./scripts/twister -E ${{ matrix.platform }}-testplan.json ./scripts/twister -i --force-color -N -v --filter runnable -p ${{ matrix.platform }} --coverage -T tests --coverage-tool gcovr -xCONFIG_TEST_EXTRA_STACK_SIZE=4096 -e nano - name: ccache stats post @@ -107,7 +108,9 @@ jobs: uses: actions/upload-artifact@v4 with: name: Coverage Data (Subset ${{ matrix.platform }}) - path: coverage/reports/${{ matrix.platform }}.json + path: | + coverage/reports/${{ matrix.platform }}.json + ${{ matrix.platform }}-testplan.json codecov-results: name: "Publish Coverage Results" @@ -121,6 +124,7 @@ jobs: uses: actions/checkout@v4 with: fetch-depth: 0 + - name: Download Artifacts uses: actions/download-artifact@v4 with: @@ -128,7 +132,9 @@ jobs: - name: Move coverage files run: | - mv ./coverage/reports/*/*.json ./coverage/reports + ls -lRt ./coverage/reports + mv ./coverage/reports/*/*testplan.json . + mv ./coverage/reports/*/coverage/reports/*.json ./coverage/reports ls -la ./coverage/reports - name: Generate list of coverage files @@ -159,19 +165,42 @@ jobs: - name: Merge coverage files run: | - cd ./coverage/reports + pushd ./coverage/reports pip3 install gcovr==6.0 gcovr ${{ steps.get-coverage-files.outputs.mergefiles }} --merge-mode-functions=separate --json merged.json gcovr ${{ steps.get-coverage-files.outputs.mergefiles }} --merge-mode-functions=separate --cobertura merged.xml + popd + + - name: Get current date + id: run_date + run: | + echo "run_date=$(date --iso-8601=minutes)" >> "$GITHUB_OUTPUT" + echo "run_date_short=$(date +'%Y-%m-%d')" >> "$GITHUB_OUTPUT" + echo "run_date_year=$(date +'%Y')" >> "$GITHUB_OUTPUT" + echo "run_date_month=$(date +'%m')" >> "$GITHUB_OUTPUT" - - name: Upload Merged Coverage Results + - name: Generate Coverage Report + if: always() + run: | + pip install xlsxwriter ijson + python3 ./scripts/ci/coverage/coverage_analysis.py \ + -t native_sim-testplan.json \ + -m MAINTAINERS.yml \ + -c coverage/reports/merged.json \ + -o coverage-report-${{ steps.run_date.outputs.run_date_short }} \ + -f all + cp coverage-report-* coverage/reports/ + + - name: Upload Merged Coverage Results and Report if: always() uses: actions/upload-artifact@v4 with: - name: Merged Coverage Data + name: Coverage Data and report path: | coverage/reports/merged.json coverage/reports/merged.xml + coverage/reports/coverage-report-${{ steps.run_date.outputs.run_date_short }}.json + coverage/reports/coverage-report-${{ steps.run_date.outputs.run_date_short }}.xlsx - name: Upload coverage to Codecov if: always() diff --git a/scripts/ci/coverage/coverage_analysis.py b/scripts/ci/coverage/coverage_analysis.py new file mode 100644 index 00000000000..be6a7b22f1d --- /dev/null +++ b/scripts/ci/coverage/coverage_analysis.py @@ -0,0 +1,509 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 Intel Corporation + +import yaml +import ijson +import json +import re +import argparse +import xlsxwriter +class Json_report: + + json_object = { + "components":[] + } + + report_json = {} + + def __init__(self): + args = parse_args() + self.parse_testplan(args.testplan) + self.maintainers_file = self.get_maintainers_file( args.maintainers) + self.report_json = self.generate_json_report( args.coverage) + + if args.format == "json": + self.save_json_report( args.output, self.report_json) + elif args.format == "xlsx": + self.generate_xlsx_report(self.report_json, args.output) + elif args.format == "all": + self.save_json_report( args.output, self.report_json) + self.generate_xlsx_report(self.report_json, args.output) + else: + print("Format incorrect") + + def get_maintainers_file(self, maintainers): + maintainers_file = "" + with open(maintainers, 'r') as file: + maintainers_file = yaml.safe_load(file) + file.close() + return maintainers_file + + + def parse_testplan(self, testplan_path): + with open(testplan_path, 'r') as file: + parser = ijson.items(file, 'testsuites') + for element in parser: + for testsuite in element: + for testcase in testsuite['testcases']: + if testcase['status'] is None: + testcase_name = testcase['identifier'] + component_name = testcase_name[:testcase_name.find('.')] + component = { + "name": component_name, + "sub_components":[], + "files":[] + } + features = self.json_object['components'] + known_component_flag = False + for item in features: + if component_name == item['name']: + component = item + known_component_flag = True + break + sub_component_name = testcase_name[testcase_name.find('.'):] + sub_component_name = sub_component_name[1:] + sub_component_name = sub_component_name[:sub_component_name.find(".")] + if known_component_flag is False: + + sub_component = { + "name":sub_component_name, + "test_suites":[] + } + test_suite = { + "name":testsuite['name'], + "path":testsuite['path'], + "platforms":[], + "runnable": testsuite['runnable'], + "status":"", + "test_cases":[] + } + test_case = { + "name":testcase_name + } + if 'qemu' in testsuite['platform'] or 'native' in testsuite['platform']: + if test_suite['status'] == "": + test_suite['status'] = 'sim_only' + + if test_suite['status'] == 'hw_only': + test_suite['status'] = 'mixed' + else: + if test_suite['status'] == "": + test_suite['status'] = 'hw_only' + + if test_suite['status'] == 'sim_only': + test_suite['status'] = 'mixed' + test_suite['test_cases'].append(test_case) + test_suite['platforms'].append(testsuite['platform']) + sub_component["test_suites"].append(test_suite) + component['sub_components'].append(sub_component) + self.json_object['components'].append(component) + else: + sub_component = {} + sub_components = component['sub_components'] + known_sub_component_flag = False + for i_sub_component in sub_components: + if sub_component_name == i_sub_component['name']: + sub_component = i_sub_component + known_sub_component_flag = True + break + if known_sub_component_flag is False: + sub_component = { + "name":sub_component_name, + "test_suites":[] + } + test_suite = { + "name":testsuite['name'], + "path":testsuite['path'], + "platforms":[], + "runnable": testsuite['runnable'], + "status":"", + "test_cases":[] + } + test_case = { + "name": testcase_name + } + if 'qemu' in testsuite['platform'] or 'native' in testsuite['platform']: + if test_suite['status'] == "": + test_suite['status'] = 'sim_only' + + if test_suite['status'] == 'hw_only': + test_suite['status'] = 'mixed' + else: + if test_suite['status'] == "": + test_suite['status'] = 'hw_only' + + if test_suite['status'] == 'sim_only': + test_suite['status'] = 'mixed' + test_suite['test_cases'].append(test_case) + test_suite['platforms'].append(testsuite['platform']) + sub_component["test_suites"].append(test_suite) + component['sub_components'].append(sub_component) + else: + test_suite = {} + test_suites = sub_component['test_suites'] + known_testsuite_flag = False + for i_testsuite in test_suites: + if testsuite['name'] == i_testsuite['name']: + test_suite = i_testsuite + known_testsuite_flag = True + break + if known_testsuite_flag is False: + test_suite = { + "name":testsuite['name'], + "path":testsuite['path'], + "platforms":[], + "runnable": testsuite['runnable'], + "status":"", + "test_cases":[] + } + test_case = { + "name": testcase_name + } + if 'qemu' in testsuite['platform'] or 'native' in testsuite['platform']: + if test_suite['status'] == "": + test_suite['status'] = 'sim_only' + + if test_suite['status'] == 'hw_only': + test_suite['status'] = 'mixed' + else: + if test_suite['status'] == "": + test_suite['status'] = 'hw_only' + + if test_suite['status'] == 'sim_only': + test_suite['status'] = 'mixed' + test_suite['test_cases'].append(test_case) + test_suite['platforms'].append(testsuite['platform']) + sub_component["test_suites"].append(test_suite) + else: + test_case = {} + test_cases = test_suite['test_cases'] + known_testcase_flag = False + for i_testcase in test_cases: + if testcase_name == i_testcase['name']: + test_case = i_testcase + known_testcase_flag = True + break + if known_testcase_flag is False: + test_case = { + "name":testcase_name + } + test_suite['test_cases'].append(test_case) + file.close() + + def get_files_from_maintainers_file(self, component_name): + files_path = [] + for item in self.maintainers_file: + _found_flag = False + try: + tests = self.maintainers_file[item].get('tests', []) + for i_test in tests: + if component_name in i_test: + _found_flag = True + + if _found_flag is True: + for path in self.maintainers_file[item]['files']: + path = path.replace('*','.*') + files_path.append(path) + except TypeError: + print("ERROR: Fail while parsing MAINTAINERS file at %s", component_name) + return files_path + + def generate_json_report(self, coverage): + output_json = { + "components":[] + } + + with open(coverage, 'r') as file: + parser = ijson.items(file, 'files') + for element in parser: + + for i_json_component in self.json_object['components']: + json_component = {} + json_component["name"]=i_json_component["name"] + json_component["sub_components"] = i_json_component["sub_components"] + json_component["Comment"] = "" + files_path = [] + files_path = self.get_files_from_maintainers_file(i_json_component["name"]) + json_files = [] + if len(files_path) != 0: + for i_file in files_path: + for i_covered_file in element: + x = re.search(('.*'+i_file+'.*'), i_covered_file['file']) + if x: + file_name = i_covered_file['file'][i_covered_file['file'].rfind('/')+1:] + file_path = i_covered_file['file'] + file_coverage, file_lines, file_hit = self._calculate_coverage_of_file(i_covered_file) + json_file = { + "Name":file_name, + "Path":file_path, + "Lines": file_lines, + "Hit":file_hit, + "Coverage": file_coverage, + "Covered_Functions": [], + "Uncovered_Functions": [] + } + for i_fun in i_covered_file['functions']: + if i_fun['execution_count'] != 0: + json_covered_funciton ={ + "Name":i_fun['name'] + } + json_file['Covered_Functions'].append(json_covered_funciton) + for i_fun in i_covered_file['functions']: + if i_fun['execution_count'] == 0: + json_uncovered_funciton ={ + "Name":i_fun['name'] + } + json_file['Uncovered_Functions'].append(json_uncovered_funciton) + json_files.append(json_file) + json_component['files']=json_files + output_json['components'].append(json_component) + else: + json_component["files"] = [] + json_component["Comment"] = "Missed in maintainers.yml file." + output_json['components'].append(json_component) + + return output_json + + def _calculate_coverage_of_file(self, file): + tracked_lines = len(file['lines']) + covered_lines = 0 + for line in file['lines']: + if line['count'] != 0: + covered_lines += 1 + return ((covered_lines/tracked_lines)*100), tracked_lines, covered_lines + + def save_json_report(self, output_path, json_object): + json_object = json.dumps(json_object, indent=4) + with open(output_path+'.json', "w") as outfile: + outfile.write(json_object) + + def _find_char(self, path, str, n): + sep = path.split(str, n) + if len(sep) <= n: + return -1 + return len(path) - len(sep[-1]) - len(str) + + def _component_calculate_stats(self, json_component): + testsuites_count = 0 + runnable_count = 0 + build_only_count = 0 + sim_only_count = 0 + hw_only_count = 0 + mixed_count = 0 + for i_sub_component in json_component['sub_components']: + for i_testsuit in i_sub_component['test_suites']: + testsuites_count += 1 + if i_testsuit['runnable'] is True: + runnable_count += 1 + else: + build_only_count += 1 + + if i_testsuit['status'] == "hw_only": + hw_only_count += 1 + elif i_testsuit['status'] == "sim_only": + sim_only_count += 1 + else: + mixed_count += 1 + return testsuites_count, runnable_count, build_only_count, sim_only_count, hw_only_count, mixed_count + + def _xlsx_generate_summary_page(self, workbook, json_report): + # formats + header_format = workbook.add_format( + { + "bold": True, + "fg_color": "#538DD5", + "color":"white" + } + ) + cell_format = workbook.add_format( + { + 'valign': 'vcenter' + } + ) + + #generate summary page + worksheet = workbook.add_worksheet('Summary') + row = 0 + col = 0 + worksheet.write(row,col,"Components",header_format) + worksheet.write(row,col+1,"TestSuites",header_format) + worksheet.write(row,col+2,"Runnable",header_format) + worksheet.write(row,col+3,"Build only",header_format) + worksheet.write(row,col+4,"Simulators only",header_format) + worksheet.write(row,col+5,"Hardware only",header_format) + worksheet.write(row,col+6,"Mixed",header_format) + worksheet.write(row,col+7,"Coverage [%]",header_format) + worksheet.write(row,col+8,"Total Functions",header_format) + worksheet.write(row,col+9,"Uncovered Functions",header_format) + worksheet.write(row,col+10,"Comment",header_format) + row = 1 + col = 0 + for item in json_report['components']: + worksheet.write(row, col, item['name'],cell_format) + testsuites,runnable,build_only,sim_only,hw_only, mixed= self._component_calculate_stats(item) + worksheet.write(row,col+1,testsuites,cell_format) + worksheet.write(row,col+2,runnable,cell_format) + worksheet.write(row,col+3,build_only,cell_format) + worksheet.write(row,col+4,sim_only,cell_format) + worksheet.write(row,col+5,hw_only,cell_format) + worksheet.write(row,col+6,mixed,cell_format) + lines = 0 + hit = 0 + coverage = 0.0 + total_funs = 0 + uncovered_funs = 0 + for i_file in item['files']: + lines += i_file['Lines'] + hit += i_file['Hit'] + total_funs += (len(i_file['Covered_Functions'])+len(i_file['Uncovered_Functions'])) + uncovered_funs += len(i_file['Uncovered_Functions']) + + if lines != 0: + coverage = (hit/lines)*100 + + worksheet.write_number(row,col+7,coverage,workbook.add_format({'num_format':'#,##0.00'})) + worksheet.write_number(row,col+8,total_funs) + worksheet.write_number(row,col+9,uncovered_funs) + worksheet.write(row,col+10,item["Comment"],cell_format) + row += 1 + col = 0 + worksheet.conditional_format(1,col+7,row,col+7, {'type': 'data_bar', + 'min_value': 0, + 'max_value': 100, + 'bar_color': '#3fd927', + 'bar_solid': True, + }) + worksheet.autofit() + worksheet.set_default_row(15) + + def generate_xlsx_report(self, json_report, output): + self.report_book = xlsxwriter.Workbook(output+".xlsx") + header_format = self.report_book.add_format( + { + "bold": True, + "fg_color": "#538DD5", + "color":"white" + } + ) + + # Create a format to use in the merged range. + merge_format = self.report_book.add_format( + { + "bold": 1, + "align": "center", + "valign": "vcenter", + "fg_color": "#538DD5", + "color":"white" + } + ) + cell_format = self.report_book.add_format( + { + 'valign': 'vcenter' + } + ) + + self._xlsx_generate_summary_page(self.report_book, self.report_json) + row = 0 + col = 0 + for item in json_report['components']: + worksheet = self.report_book.add_worksheet(item['name']) + row = 0 + col = 0 + worksheet.write(row,col,"File Name",header_format) + worksheet.write(row,col+1,"File Path",header_format) + worksheet.write(row,col+2,"Coverage [%]",header_format) + worksheet.write(row,col+3,"Lines",header_format) + worksheet.write(row,col+4,"Hits",header_format) + worksheet.write(row,col+5,"Diff",header_format) + row += 1 + col = 0 + for i_file in item['files']: + worksheet.write(row,col,i_file['Path'][i_file['Path'].rfind('/')+1:],cell_format) + worksheet.write(row,col+1,i_file["Path"][(self._find_char(i_file["Path"],'/',3)+1):],cell_format) + worksheet.write_number(row,col+2,i_file["Coverage"],self.report_book.add_format({'num_format':'#,##0.00'})) + worksheet.write(row,col+3,i_file["Lines"],cell_format) + worksheet.write(row,col+4,i_file["Hit"],cell_format) + worksheet.write(row,col+5,i_file["Lines"]-i_file["Hit"],cell_format) + row += 1 + col = 0 + row += 1 + col = 0 + worksheet.conditional_format(1,col+2,row,col+2, {'type': 'data_bar', + 'min_value': 0, + 'max_value': 100, + 'bar_color': '#3fd927', + 'bar_solid': True, + }) + worksheet.merge_range(row,col,row,col+2, "Uncovered Functions", merge_format) + row += 1 + worksheet.write(row,col,'Function Name',header_format) + worksheet.write(row,col+1,'Implementation File',header_format) + worksheet.write(row,col+2,'Comment',header_format) + row += 1 + col = 0 + for i_file in item['files']: + for i_uncov_fun in i_file['Uncovered_Functions']: + worksheet.write(row,col,i_uncov_fun["Name"],cell_format) + worksheet.write(row,col+1,i_file["Path"][self._find_char(i_file["Path"],'/',3)+1:],cell_format) + row += 1 + col = 0 + row += 1 + col = 0 + worksheet.write(row,col,"Components",header_format) + worksheet.write(row,col+1,"Sub-Components",header_format) + worksheet.write(row,col+2,"TestSuites",header_format) + worksheet.write(row,col+3,"Runnable",header_format) + worksheet.write(row,col+4,"Build only",header_format) + worksheet.write(row,col+5,"Simulation only",header_format) + worksheet.write(row,col+6,"Hardware only",header_format) + worksheet.write(row,col+7,"Mixed",header_format) + row += 1 + col = 0 + worksheet.write(row,col,item['name'],cell_format) + for i_sub_component in item['sub_components']: + testsuites_count = 0 + runnable_count = 0 + build_only_count = 0 + sim_only_count = 0 + hw_only_count = 0 + mixed_count = 0 + worksheet.write(row,col+1,i_sub_component['name'],cell_format) + for i_testsuit in i_sub_component['test_suites']: + testsuites_count += 1 + if i_testsuit['runnable'] is True: + runnable_count += 1 + else: + build_only_count += 1 + + if i_testsuit['status'] == "hw_only": + hw_only_count += 1 + elif i_testsuit['status'] == "sim_only": + sim_only_count += 1 + else: + mixed_count += 1 + worksheet.write(row,col+2,testsuites_count,cell_format) + worksheet.write(row,col+3,runnable_count,cell_format) + worksheet.write(row,col+4,build_only_count,cell_format) + worksheet.write(row,col+5,sim_only_count,cell_format) + worksheet.write(row,col+6,hw_only_count,cell_format) + worksheet.write(row,col+7,mixed_count,cell_format) + row += 1 + col = 0 + + worksheet.autofit() + worksheet.set_default_row(15) + self.report_book.close() + +def parse_args(): + parser = argparse.ArgumentParser(allow_abbrev=False) + parser.add_argument('-m','--maintainers', help='Path to maintainers.yml [Required]', required=True) + parser.add_argument('-t','--testplan', help='Path to testplan [Required]', required=True) + parser.add_argument('-c','--coverage', help='Path to components file [Required]', required=True) + parser.add_argument('-o','--output', help='Report name [Required]', required=True) + parser.add_argument('-f','--format', help='Output format (json, xlsx, all) [Required]', required=True) + + args = parser.parse_args() + return args + +if __name__ == '__main__': + Json_report() From 3bf61528cce69deec3ea190cf9b37e3b550d6be5 Mon Sep 17 00:00:00 2001 From: Michal Smola Date: Thu, 4 Jan 2024 09:53:51 +0100 Subject: [PATCH 0120/2402] twister: qemu: add QEMU support on Windows in twister Twister does not support running tests on QEMU on Windows. Add a new twister handler called QEMUWinHandler which supports running tests on Windows. Enable running tests in testinstance, only if QEMU_BIN_PATH environment variable exists on Windows. Modify pytest test for testinstance to reflect the change in runnability of QEMU on Windows. Tested by running several Ztest and console harness tests. Signed-off-by: Michal Smola --- scripts/pylib/twister/twisterlib/handlers.py | 269 ++++++++++++++++++ .../pylib/twister/twisterlib/testinstance.py | 22 +- scripts/tests/twister/test_testinstance.py | 8 + 3 files changed, 293 insertions(+), 6 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py index 3a13b819649..525d8f30ec0 100755 --- a/scripts/pylib/twister/twisterlib/handlers.py +++ b/scripts/pylib/twister/twisterlib/handlers.py @@ -19,6 +19,7 @@ import threading import time +from queue import Queue, Empty from twisterlib.environment import ZEPHYR_BASE from twisterlib.error import TwisterException sys.path.insert(0, os.path.join(ZEPHYR_BASE, "scripts/pylib/build_helpers")) @@ -1040,3 +1041,271 @@ def handle(self, harness): def get_fifo(self): return self.fifo_fn + + +class QEMUWinHandler(Handler): + """Spawns a thread to monitor QEMU output on Windows OS + + We redirect subprocess output to pipe and monitor the pipes for output. + We need to do this as once qemu starts, it runs forever until killed. + Test cases emit special messages to the console as they run, we check + for these to collect whether the test passed or failed. + The pipe includes also messages from ninja command which is used for + running QEMU. + """ + + def __init__(self, instance, type_str): + """Constructor + + @param instance Test instance + """ + + super().__init__(instance, type_str) + self.pid_fn = os.path.join(instance.build_dir, "qemu.pid") + self.pid = 0 + self.thread = None + self.stop_thread = False + self.results = {} + + if instance.testsuite.ignore_qemu_crash: + self.ignore_qemu_crash = True + self.ignore_unexpected_eof = True + else: + self.ignore_qemu_crash = False + self.ignore_unexpected_eof = False + + @staticmethod + def _get_cpu_time(pid): + """get process CPU time. + + The guest virtual time in QEMU icount mode isn't host time and + it's maintained by counting guest instructions, so we use QEMU + process execution time to mostly simulate the time of guest OS. + """ + proc = psutil.Process(pid) + cpu_time = proc.cpu_times() + return cpu_time.user + cpu_time.system + + @staticmethod + def _open_log_file(logfile): + return open(logfile, "wt") + + @staticmethod + def _close_log_file(log_file): + log_file.close() + + @staticmethod + def _stop_qemu_process(pid): + if pid: + try: + if pid: + os.kill(pid, signal.SIGTERM) + except (ProcessLookupError, psutil.NoSuchProcess): + # Oh well, as long as it's dead! User probably sent Ctrl-C + pass + + @staticmethod + def _monitor_update_instance_info(handler, handler_time, out_state): + handler.instance.execution_time = handler_time + if out_state == "timeout": + handler.instance.status = "failed" + handler.instance.reason = "Timeout" + elif out_state == "failed": + handler.instance.status = "failed" + handler.instance.reason = "Failed" + elif out_state in ['unexpected eof', 'unexpected byte']: + handler.instance.status = "failed" + handler.instance.reason = out_state + else: + handler.instance.status = out_state + handler.instance.reason = "Unknown" + + def _get_sysbuild_build_dir(self): + if self.instance.testsuite.sysbuild: + # Load domain yaml to get default domain build directory + # Note: for targets using QEMU, we assume that the target will + # have added any additional images to the run target manually + domain_path = os.path.join(self.build_dir, "domains.yaml") + domains = Domains.from_file(domain_path) + logger.debug("Loaded sysbuild domain data from %s" % domain_path) + build_dir = domains.get_default_domain().build_dir + else: + build_dir = self.build_dir + + return build_dir + + def _set_qemu_filenames(self, sysbuild_build_dir): + # PID file will be created in the main sysbuild app's build dir + self.pid_fn = os.path.join(sysbuild_build_dir, "qemu.pid") + + if os.path.exists(self.pid_fn): + os.unlink(self.pid_fn) + + self.log_fn = self.log + + def _create_command(self, sysbuild_build_dir): + command = [self.generator_cmd] + command += ["-C", sysbuild_build_dir, "run"] + + return command + + def _update_instance_info(self, harness_state, is_timeout): + if (self.returncode != 0 and not self.ignore_qemu_crash) or not harness_state: + self.instance.status = "failed" + if is_timeout: + self.instance.reason = "Timeout" + else: + if not self.instance.reason: + self.instance.reason = "Exited with {}".format(self.returncode) + self.instance.add_missing_case_status("blocked") + + def _enqueue_char(self, stdout, queue): + while not self.stop_thread: + try: + c = stdout.read(1) + except ValueError: + # Reading on closed file exception can occur when subprocess is killed. + # Can be ignored. + pass + else: + queue.put(c) + + def _monitor_output(self, queue, timeout, logfile, pid_fn, harness, ignore_unexpected_eof=False): + start_time = time.time() + timeout_time = start_time + timeout + out_state = None + line = "" + timeout_extended = False + self.pid = 0 + + log_out_fp = self._open_log_file(logfile) + + while True: + this_timeout = int((timeout_time - time.time()) * 1000) + if this_timeout < 0: + try: + if self.pid and this_timeout > 0: + # there's possibility we polled nothing because + # of not enough CPU time scheduled by host for + # QEMU process during p.poll(this_timeout) + cpu_time = self._get_cpu_time(self.pid) + if cpu_time < timeout and not out_state: + timeout_time = time.time() + (timeout - cpu_time) + continue + except psutil.NoSuchProcess: + pass + except ProcessLookupError: + out_state = "failed" + break + + if not out_state: + out_state = "timeout" + break + + if self.pid == 0 and os.path.exists(pid_fn): + try: + self.pid = int(open(pid_fn).read()) + except ValueError: + # pid file probably not contains pid yet, continue + pass + + try: + c = queue.get_nowait() + except Empty: + continue + try: + c = c.decode("utf-8") + except UnicodeDecodeError: + # Test is writing something weird, fail + out_state = "unexpected byte" + break + + if c == "": + # EOF, this shouldn't happen unless QEMU crashes + if not ignore_unexpected_eof: + out_state = "unexpected eof" + break + line = line + c + if c != "\n": + continue + + # line contains a full line of data output from QEMU + log_out_fp.write(line) + log_out_fp.flush() + line = line.rstrip() + logger.debug(f"QEMU ({self.pid}): {line}") + + harness.handle(line) + if harness.state: + # if we have registered a fail make sure the state is not + # overridden by a false success message coming from the + # testsuite + if out_state not in ['failed', 'unexpected eof', 'unexpected byte']: + out_state = harness.state + + # if we get some state, that means test is doing well, we reset + # the timeout and wait for 2 more seconds to catch anything + # printed late. We wait much longer if code + # coverage is enabled since dumping this information can + # take some time. + if not timeout_extended or harness.capture_coverage: + timeout_extended = True + if harness.capture_coverage: + timeout_time = time.time() + 30 + else: + timeout_time = time.time() + 2 + line = "" + + self.stop_thread = True + + handler_time = time.time() - start_time + logger.debug(f"QEMU ({self.pid}) complete ({out_state}) after {handler_time} seconds") + self._monitor_update_instance_info(self, handler_time, out_state) + self._close_log_file(log_out_fp) + self._stop_qemu_process(self.pid) + + def handle(self, harness): + self.results = {} + self.run = True + + sysbuild_build_dir = self._get_sysbuild_build_dir() + command = self._create_command(sysbuild_build_dir) + self._set_qemu_filenames(sysbuild_build_dir) + + logger.debug("Running %s (%s)" % (self.name, self.type_str)) + is_timeout = False + self.stop_thread = False + queue = Queue() + + with subprocess.Popen(command, stdout=subprocess.PIPE, stderr=subprocess.PIPE, cwd=self.build_dir) as proc: + logger.debug("Spawning QEMUHandler Thread for %s" % self.name) + + self.thread = threading.Thread(target=self._enqueue_char, args=(proc.stdout, queue)) + self.thread.daemon = True + self.thread.start() + + thread_max_time = time.time() + self.get_test_timeout() + + self._monitor_output(queue, self.get_test_timeout(), self.log_fn, self.pid_fn, harness, + self.ignore_unexpected_eof) + + if (thread_max_time - time.time()) < 0: + logger.debug("Timed out while monitoring QEMU output") + proc.terminate() + # sleep for a while before attempting to kill + time.sleep(0.5) + proc.kill() + + if harness.state == "passed": + self.returncode = 0 + else: + self.returncode = proc.returncode + + if os.path.exists(self.pid_fn): + os.unlink(self.pid_fn) + + logger.debug(f"return code from QEMU ({self.pid}): {self.returncode}") + + self._update_instance_info(harness.state, is_timeout) + + self._final_handle_actions(harness, 0) diff --git a/scripts/pylib/twister/twisterlib/testinstance.py b/scripts/pylib/twister/twisterlib/testinstance.py index e11f8eddfdb..850da363278 100644 --- a/scripts/pylib/twister/twisterlib/testinstance.py +++ b/scripts/pylib/twister/twisterlib/testinstance.py @@ -20,6 +20,7 @@ SimulationHandler, BinaryHandler, QEMUHandler, + QEMUWinHandler, DeviceHandler, SUPPORTED_SIMS, SUPPORTED_SIMS_IN_PYTEST, @@ -178,9 +179,13 @@ def setup_handler(self, env): handler.ready = True elif self.platform.simulation != "na": if self.platform.simulation == "qemu": - handler = QEMUHandler(self, "qemu") - handler.args.append(f"QEMU_PIPE={handler.get_fifo()}") - handler.ready = True + if os.name != "nt": + handler = QEMUHandler(self, "qemu") + handler.args.append(f"QEMU_PIPE={handler.get_fifo()}") + handler.ready = True + else: + handler = QEMUWinHandler(self, "qemu") + handler.ready = True else: handler = SimulationHandler(self, self.platform.simulation) @@ -204,9 +209,14 @@ def setup_handler(self, env): # Global testsuite parameters def check_runnable(self, enable_slow=False, filter='buildable', fixtures=[], hardware_map=None): - # running on simulators is currently not supported on Windows - if os.name == 'nt' and self.platform.simulation != 'na': - return False + if os.name == 'nt': + # running on simulators is currently supported only for QEMU on Windows + if self.platform.simulation not in ('na', 'qemu'): + return False + + # check presence of QEMU on Windows + if 'QEMU_BIN_PATH' not in os.environ: + return False # we asked for build-only on the command line if self.testsuite.build_only: diff --git a/scripts/tests/twister/test_testinstance.py b/scripts/tests/twister/test_testinstance.py index 849421bddf0..bf3b1ff1ded 100644 --- a/scripts/tests/twister/test_testinstance.py +++ b/scripts/tests/twister/test_testinstance.py @@ -72,9 +72,17 @@ def test_check_build_or_run( assert run == r with mock.patch('os.name', 'nt'): + # path to QEMU binary is not in QEMU_BIN_PATH environment variable run = testinstance.check_runnable() assert not run + # mock path to QEMU binary in QEMU_BIN_PATH environment variable + with mock.patch('os.environ', {'QEMU_BIN_PATH': ''}): + run = testinstance.check_runnable() + _, r = expected + assert run == r + + TESTDATA_PART_2 = [ (True, True, True, ["demo_board_2"], "native", None, '\nCONFIG_COVERAGE=y\nCONFIG_COVERAGE_DUMP=y\nCONFIG_ASAN=y\nCONFIG_UBSAN=y'), From a1188a96ff3896ea1d6b9f78020868e46b796d29 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Thu, 22 Feb 2024 15:45:08 +0200 Subject: [PATCH 0121/2402] drivers: dai: sai: use TDR/RDR for fifo base address computation Using the address of RDR/TDR for fifo base address computation has the same effect as using the FSL_FEATURE_SAI_{TX/RX}_FIFO_BASEn macro from NXP HAL. The only difference between the two is that the macro is not defined for all SoCs so whenever we introduce a new SoC that uses the SAI module we have to also introduce the macro for said SoC. Using TDR/RDR has the advantage that it doesn't require any additional changes to the NXP HAL. Since we only support one data line per direction, it's fine to just use RDR[0] and TDR[0] for the address computation. Signed-off-by: Laurentiu Mihalcea --- drivers/dai/nxp/sai/sai.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/dai/nxp/sai/sai.h b/drivers/dai/nxp/sai/sai.h index f3f4441a6cb..c93a1803d41 100644 --- a/drivers/dai/nxp/sai/sai.h +++ b/drivers/dai/nxp/sai/sai.h @@ -101,13 +101,13 @@ LOG_MODULE_REGISTER(nxp_dai_sai); DT_INST_PROP_OR(inst, rx_fifo_watermark,\ FSL_FEATURE_SAI_FIFO_COUNTn(UINT_TO_I2S(DT_INST_REG_ADDR(inst))) / 2) -/* used to retrieve TFR0's address based on SAI's physical address */ +/* used to retrieve TDR0's address based on SAI's physical address */ #define SAI_TX_FIFO_BASE(inst)\ - FSL_FEATURE_SAI_TX_FIFO_BASEn(UINT_TO_I2S(DT_INST_REG_ADDR(inst)), 0) + POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->TDR[0])) -/* used to retrieve RFR0's address based on SAI's physical address */ +/* used to retrieve RDR0's address based on SAI's physical address */ #define SAI_RX_FIFO_BASE(inst)\ - FSL_FEATURE_SAI_RX_FIFO_BASEn(UINT_TO_I2S(DT_INST_REG_ADDR(inst)), 0) + POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->RDR[0])) /* internal macro used to retrieve the default TX/RX FIFO's size (in FIFO words) */ #define _SAI_FIFO_DEPTH(inst)\ From 808f79d863f1d4654d44098940c7dc33a468d23d Mon Sep 17 00:00:00 2001 From: Sibert Declercq Date: Thu, 29 Feb 2024 21:31:35 +0100 Subject: [PATCH 0122/2402] net: coap: CoAP observe age now correctly wraps around Fixes two bugs: * When a notify is executed before any observers are added, the age is incremented from 0 to 1. When an observer is registered, the age is not 0 as expected, causing the age to be 1 instead of the expected 2 * The check if a message is newer than the last received one is described in RFC7641, section 3.4. Simply incrementing age will not comply to what the RFC describes once the value wraps around. This is now fixed Signed-off-by: Sibert Declercq --- include/zephyr/net/coap.h | 2 ++ subsys/net/lib/coap/coap.c | 23 +++++++++++++++++++---- 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/include/zephyr/net/coap.h b/include/zephyr/net/coap.h index cd57c560bee..da241a7734a 100644 --- a/include/zephyr/net/coap.h +++ b/include/zephyr/net/coap.h @@ -84,6 +84,8 @@ enum coap_method { #define COAP_VERSION_1 1U +#define COAP_OBSERVE_MAX_AGE 0xFFFFFF + /** * @brief CoAP packets may be of one of these types. */ diff --git a/subsys/net/lib/coap/coap.c b/subsys/net/lib/coap/coap.c index 929b995f9b1..ac434680740 100644 --- a/subsys/net/lib/coap/coap.c +++ b/subsys/net/lib/coap/coap.c @@ -51,6 +51,8 @@ LOG_MODULE_REGISTER(net_coap, CONFIG_COAP_LOG_LEVEL); #define BASIC_HEADER_SIZE 4 +#define COAP_OBSERVE_FIRST_OFFSET 2 + /* The CoAP message ID that is incremented each time coap_next_id() is called. */ static uint16_t message_id; @@ -1749,12 +1751,21 @@ size_t coap_pendings_count(struct coap_pending *pendings, size_t len) } /* Reordering according to RFC7641 section 3.4 but without timestamp comparison */ -static inline bool is_newer(int v1, int v2) +IF_DISABLED(CONFIG_ZTEST, (static inline)) +bool coap_age_is_newer(int v1, int v2) { return (v1 < v2 && v2 - v1 < (1 << 23)) || (v1 > v2 && v1 - v2 > (1 << 23)); } +static inline void coap_observer_increment_age(struct coap_resource *resource) +{ + resource->age++; + if (resource->age > COAP_OBSERVE_MAX_AGE) { + resource->age = COAP_OBSERVE_FIRST_OFFSET; + } +} + struct coap_reply *coap_response_received( const struct coap_packet *response, const struct sockaddr *from, @@ -1792,7 +1803,7 @@ struct coap_reply *coap_response_received( age = coap_get_option_int(response, COAP_OPTION_OBSERVE); /* handle observed requests only if received in order */ - if (age == -ENOENT || is_newer(r->age, age)) { + if (age == -ENOENT || coap_age_is_newer(r->age, age)) { r->age = age; if (coap_header_get_code(response) != COAP_RESPONSE_CODE_CONTINUE) { r->reply(response, r, from); @@ -1847,7 +1858,11 @@ int coap_resource_notify(struct coap_resource *resource) return -ENOENT; } - resource->age++; + if (sys_slist_is_empty(&resource->observers)) { + return 0; + } + + coap_observer_increment_age(resource); SYS_SLIST_FOR_EACH_CONTAINER(&resource->observers, o, list) { resource->notify(resource, o); @@ -1898,7 +1913,7 @@ bool coap_register_observer(struct coap_resource *resource, first = resource->age == 0; if (first) { - resource->age = 2; + resource->age = COAP_OBSERVE_FIRST_OFFSET; } coap_observer_raise_event(resource, observer, NET_EVENT_COAP_OBSERVER_ADDED); From 8fc88a0ce7629f506bdc62847ec0e46932c9374d Mon Sep 17 00:00:00 2001 From: Sibert Declercq Date: Thu, 29 Feb 2024 21:32:25 +0100 Subject: [PATCH 0123/2402] tests: net: coap: add test for age wrap around - Added a test to the CoAP testsuite for age wrap around - Added test for `coap_age_is_newer` Signed-off-by: Sibert Declercq --- tests/net/lib/coap/src/main.c | 92 ++++++++++++++++++++++++++++++++--- 1 file changed, 85 insertions(+), 7 deletions(-) diff --git a/tests/net/lib/coap/src/main.c b/tests/net/lib/coap/src/main.c index d1903dea10c..18012cc7873 100644 --- a/tests/net/lib/coap/src/main.c +++ b/tests/net/lib/coap/src/main.c @@ -39,18 +39,25 @@ bool _coap_match_path_uri(const char * const *path, const char *uri, uint16_t len); /* Some forward declarations */ -static void server_notify_callback(struct coap_resource *resource, - struct coap_observer *observer); +static void server_resource_1_callback(struct coap_resource *resource, + struct coap_observer *observer); + +static void server_resource_2_callback(struct coap_resource *resource, + struct coap_observer *observer); static int server_resource_1_get(struct coap_resource *resource, struct coap_packet *request, struct sockaddr *addr, socklen_t addr_len); static const char * const server_resource_1_path[] = { "s", "1", NULL }; -static struct coap_resource server_resources[] = { +static const char *const server_resource_2_path[] = { "s", "2", NULL }; +static struct coap_resource server_resources[] = { { .path = server_resource_1_path, .get = server_resource_1_get, - .notify = server_notify_callback }, + .notify = server_resource_1_callback }, + { .path = server_resource_2_path, + .get = server_resource_1_get, /* Get can be shared with the first resource */ + .notify = server_resource_2_callback }, { }, }; @@ -63,6 +70,12 @@ static struct sockaddr_in6 dummy_addr = { static uint8_t data_buf[2][COAP_BUF_SIZE]; +#define COAP_ROLLOVER_AGE (1 << 23) +#define COAP_MAX_AGE 0xffffff +#define COAP_FIRST_AGE 2 + +extern bool coap_age_is_newer(int v1, int v2); + ZTEST(coap, test_build_empty_pdu) { uint8_t result_pdu[] = { 0x40, 0x01, 0x0, 0x0 }; @@ -822,8 +835,8 @@ static bool ipaddr_cmp(const struct sockaddr *a, const struct sockaddr *b) return false; } -static void server_notify_callback(struct coap_resource *resource, - struct coap_observer *observer) +static void server_resource_1_callback(struct coap_resource *resource, + struct coap_observer *observer) { bool r; @@ -832,6 +845,14 @@ static void server_notify_callback(struct coap_resource *resource, coap_remove_observer(resource, observer); } +static void server_resource_2_callback(struct coap_resource *resource, + struct coap_observer *observer) +{ + bool r; + + r = ipaddr_cmp(&observer->addr, (const struct sockaddr *)&dummy_addr); + zassert_true(r, "The address of the observer doesn't match"); +} static int server_resource_1_get(struct coap_resource *resource, struct coap_packet *request, @@ -891,7 +912,7 @@ ZTEST(coap, test_observer_server) 0x45, 0x01, 0x12, 0x34, 't', 'o', 'k', 'e', 'n', 0x60, /* enable observe option */ - 0x51, 's', 0x01, '2', /* path */ + 0x51, 's', 0x01, '3', /* path */ }; struct coap_packet req; struct coap_option options[4] = {}; @@ -1771,4 +1792,61 @@ ZTEST(coap, test_transmission_parameters) zassert_equal(pending->params.max_retransmission, 2, "Wrong max retransmission value"); } +ZTEST(coap, test_notify_age) +{ + uint8_t valid_request_pdu[] = { + 0x45, 0x01, 0x12, 0x34, 't', 'o', 'k', 'e', 'n', 0x60, /* enable observe option */ + 0x51, 's', 0x01, '2', /* path */ + }; + + struct coap_packet req; + struct coap_option options[4] = {}; + uint8_t *data = data_buf[0]; + uint8_t opt_num = ARRAY_SIZE(options) - 1; + struct coap_resource *resource = &server_resources[1]; + int r; + struct coap_observer *observer; + int last_age; + + memcpy(data, valid_request_pdu, sizeof(valid_request_pdu)); + + r = coap_packet_parse(&req, data, sizeof(valid_request_pdu), options, opt_num); + zassert_equal(r, 0, "Could not initialize packet"); + + r = coap_handle_request(&req, server_resources, options, opt_num, + (struct sockaddr *)&dummy_addr, sizeof(dummy_addr)); + zassert_equal(r, 0, "Could not handle packet"); + + /* Forward time a bit, as not to run this 8 million time */ + resource->age = COAP_OBSERVE_MAX_AGE - 10; + + last_age = resource->age; + + for (int i = 0; i < 15; i++) { + r = coap_resource_notify(resource); + zassert_true(coap_age_is_newer(last_age, resource->age), + "Resource age expected to be newer"); + last_age = resource->age; + } + + observer = + CONTAINER_OF(sys_slist_peek_head(&resource->observers), struct coap_observer, list); + coap_remove_observer(resource, observer); +} + +ZTEST(coap, test_age_is_newer) +{ + for (int i = COAP_FIRST_AGE; i < COAP_MAX_AGE; ++i) { + zassert_true(coap_age_is_newer(i, i + 1), + "Resource age expected to be marked as newer"); + } + + zassert_true(coap_age_is_newer(COAP_MAX_AGE, COAP_FIRST_AGE), + "First age should be marked as newer"); + zassert_true(coap_age_is_newer(COAP_FIRST_AGE, COAP_ROLLOVER_AGE), + "Rollover age should be marked as newer"); + zassert_true(coap_age_is_newer(COAP_ROLLOVER_AGE, COAP_MAX_AGE), + "Max age should be marked as newer"); +} + ZTEST_SUITE(coap, NULL, NULL, NULL, NULL, NULL); From 686a13209264f2387427c3b38ccc24aed42cfec1 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Mon, 4 Mar 2024 20:33:04 -0600 Subject: [PATCH 0124/2402] MAINTAINERS: Fix username typo on NXP MPU dleach -> dleach02 Signed-off-by: Declan Snyder --- MAINTAINERS.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index e2e40904416..82b8a2f9344 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3346,7 +3346,7 @@ NXP Platforms (S32): NXP Platforms (MPU): status: maintained maintainers: - - dleach + - dleach02 collaborators: - JiafeiPan - dbaluta From 977fc0c2ad21c30665d48acf88dbc9fa5ce4b78a Mon Sep 17 00:00:00 2001 From: Andy Sinclair Date: Wed, 21 Feb 2024 11:21:43 +0000 Subject: [PATCH 0125/2402] drivers: regulator: common: Added regulator-boot-off Added regulator-boot-off option to common regulator driver. Signed-off-by: Andy Sinclair --- drivers/regulator/regulator_common.c | 3 +++ dts/bindings/regulator/regulator.yaml | 5 +++++ include/zephyr/drivers/regulator.h | 7 ++++++- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/regulator_common.c b/drivers/regulator/regulator_common.c index f2d9f6275e6..c539e1169ee 100644 --- a/drivers/regulator/regulator_common.c +++ b/drivers/regulator/regulator_common.c @@ -90,6 +90,9 @@ int regulator_common_init(const struct device *dev, bool is_enabled) if (is_enabled) { data->refcnt++; + if ((config->flags & REGULATOR_BOOT_OFF) != 0U) { + return regulator_disable(dev); + } } else if ((config->flags & REGULATOR_INIT_ENABLED) != 0U) { ret = api->enable(dev); if (ret < 0) { diff --git a/dts/bindings/regulator/regulator.yaml b/dts/bindings/regulator/regulator.yaml index 635bfa49596..b072ce8c920 100644 --- a/dts/bindings/regulator/regulator.yaml +++ b/dts/bindings/regulator/regulator.yaml @@ -61,6 +61,11 @@ properties: This property is intended to only be used for regulators where software cannot read the state of the regulator. + regulator-boot-off: + type: boolean + description: | + Regulator should be disabled on boot. + regulator-allow-bypass: type: boolean description: allow the regulator to go into bypass mode diff --git a/include/zephyr/drivers/regulator.h b/include/zephyr/drivers/regulator.h index 77e441d0dae..46a085d9239 100644 --- a/include/zephyr/drivers/regulator.h +++ b/include/zephyr/drivers/regulator.h @@ -141,6 +141,8 @@ __subsystem struct regulator_driver_api { /** Regulator active discharge get bits */ #define REGULATOR_ACTIVE_DISCHARGE_GET_BITS(x) \ (((x) & REGULATOR_ACTIVE_DISCHARGE_MASK) >> REGULATOR_ACTIVE_DISCHARGE_POS) +/** Indicates regulator must be initialized OFF */ +#define REGULATOR_BOOT_OFF BIT(4) /** @} */ @@ -212,7 +214,9 @@ struct regulator_common_config { REGULATOR_BOOT_ON) | \ (REGULATOR_ACTIVE_DISCHARGE_SET_BITS( \ DT_PROP_OR(node_id, regulator_active_discharge, \ - REGULATOR_ACTIVE_DISCHARGE_DEFAULT)))), \ + REGULATOR_ACTIVE_DISCHARGE_DEFAULT))) | \ + (DT_PROP_OR(node_id, regulator_boot_off, 0U) * \ + REGULATOR_BOOT_OFF)), \ } /** @@ -254,6 +258,7 @@ void regulator_common_data_init(const struct device *dev); * * - Automatically enable the regulator if it is set to `regulator-boot-on` * or `regulator-always-on` and increase its usage count. + * - Automatically disable the regulator if it is set to `regulator-boot-off`. * - Configure the regulator mode if `regulator-initial-mode` is set. * - Ensure regulator voltage is set to a valid range. * From b46e2f3d8acdc96dae37cae962648b8bf2ee302a Mon Sep 17 00:00:00 2001 From: Andy Sinclair Date: Tue, 20 Feb 2024 22:18:45 +0000 Subject: [PATCH 0126/2402] drivers: regulator: fake: Added is_enabled property Added is_enabled devicetree property to fake regulator. Allows testing of init behaviour when regulator is enabled in hardware. Signed-off-by: Andy Sinclair --- drivers/regulator/regulator_fake.c | 6 +++++- dts/bindings/regulator/zephyr,fake-regulator.yaml | 7 +++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/regulator_fake.c b/drivers/regulator/regulator_fake.c index 129ef2f215e..c2c71593c61 100644 --- a/drivers/regulator/regulator_fake.c +++ b/drivers/regulator/regulator_fake.c @@ -15,6 +15,7 @@ struct regulator_fake_config { struct regulator_common_config common; + bool is_enabled; }; struct regulator_fake_data { @@ -64,9 +65,11 @@ static struct regulator_driver_api api = { static int regulator_fake_init(const struct device *dev) { + const struct regulator_fake_config *config = dev->config; + regulator_common_data_init(dev); - return regulator_common_init(dev, false); + return regulator_common_init(dev, config->is_enabled); } /* parent regulator */ @@ -90,6 +93,7 @@ static struct regulator_parent_driver_api parent_api = { \ static const struct regulator_fake_config FAKE_CONF_NAME(node_id) = { \ .common = REGULATOR_DT_COMMON_CONFIG_INIT(node_id), \ + .is_enabled = DT_PROP(node_id, fake_is_enabled_in_hardware), \ }; \ \ DEVICE_DT_DEFINE(node_id, regulator_fake_init, NULL, \ diff --git a/dts/bindings/regulator/zephyr,fake-regulator.yaml b/dts/bindings/regulator/zephyr,fake-regulator.yaml index 7a6894948b2..833dc8ca115 100644 --- a/dts/bindings/regulator/zephyr,fake-regulator.yaml +++ b/dts/bindings/regulator/zephyr,fake-regulator.yaml @@ -10,3 +10,10 @@ compatible: "zephyr,fake-regulator" child-binding: include: regulator.yaml + + properties: + fake-is-enabled-in-hardware: + type: boolean + description: | + Sets the is_enabled flag passed to regulator_common_init. + Allows test cases where the regulator is enabled in hardware. From 16fdc4bc9f3fd870c5358a477cf4c079e1e5615b Mon Sep 17 00:00:00 2001 From: Andy Sinclair Date: Tue, 20 Feb 2024 22:35:49 +0000 Subject: [PATCH 0127/2402] tests: drivers: regulator: added regulator-boot-off tests Added tests for new regulator-boot-off property. Signed-off-by: Andy Sinclair --- tests/drivers/regulator/api/app.overlay | 9 ++++++++ tests/drivers/regulator/api/src/main.c | 29 +++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/tests/drivers/regulator/api/app.overlay b/tests/drivers/regulator/api/app.overlay index 25d1d8bb795..6dfeefed18f 100644 --- a/tests/drivers/regulator/api/app.overlay +++ b/tests/drivers/regulator/api/app.overlay @@ -26,5 +26,14 @@ regulator-initial-mode = <1>; regulator-active-discharge = <1>; }; + + reg4: REG4 { + regulator-boot-off; + }; + + reg5: REG5 { + regulator-boot-off; + fake-is-enabled-in-hardware; + }; }; }; diff --git a/tests/drivers/regulator/api/src/main.c b/tests/drivers/regulator/api/src/main.c index 648d761a8b4..93fa7863085 100644 --- a/tests/drivers/regulator/api/src/main.c +++ b/tests/drivers/regulator/api/src/main.c @@ -19,6 +19,10 @@ static const struct device *const reg1 = DEVICE_DT_GET(DT_NODELABEL(reg1)); static const struct device *const reg2 = DEVICE_DT_GET(DT_NODELABEL(reg2)); /* REG3: regulator-max/min-microvolt/microamp, regulator-allowed-modes */ static const struct device *const reg3 = DEVICE_DT_GET(DT_NODELABEL(reg3)); +/* REG4: regulator-boot-off */ +static const struct device *const reg4 = DEVICE_DT_GET(DT_NODELABEL(reg4)); +/* REG5: regulator-boot-off and is_enabled */ +static const struct device *const reg5 = DEVICE_DT_GET(DT_NODELABEL(reg5)); ZTEST(regulator_api, test_parent_dvs_state_set_not_implemented) { @@ -129,6 +133,10 @@ ZTEST(regulator_api, test_common_config) zassert_equal(config->allowed_modes[1], 10U); zassert_equal(config->allowed_modes_cnt, 2U); zassert_equal(REGULATOR_ACTIVE_DISCHARGE_GET_BITS(config->flags), 1U); + + /* reg4: regulator-boot-off */ + config = reg4->config; + zassert_equal(config->flags & REGULATOR_BOOT_OFF, REGULATOR_BOOT_OFF); } ZTEST(regulator_api, test_common_is_init_enabled) @@ -137,6 +145,8 @@ ZTEST(regulator_api, test_common_is_init_enabled) zassert_true(regulator_common_is_init_enabled(reg1)); zassert_true(regulator_common_is_init_enabled(reg2)); zassert_false(regulator_common_is_init_enabled(reg3)); + zassert_false(regulator_common_is_init_enabled(reg4)); + zassert_false(regulator_common_is_init_enabled(reg5)); } ZTEST(regulator_api, test_enable_disable) @@ -171,6 +181,16 @@ ZTEST(regulator_api, test_enable_disable) zassert_equal(regulator_disable(reg0), 0); zassert_equal(regulator_fake_disable_fake.arg0_val, reg0); zassert_equal(regulator_fake_disable_fake.call_count, 2U); + + /* REG5: disabled at boot, can be enabled again */ + zassert_equal(regulator_enable(reg5), 0); + zassert_equal(regulator_fake_enable_fake.call_count, 3U); + + /* REG5: disable */ + zassert_equal(regulator_disable(reg5), 0); + zassert_equal(regulator_fake_disable_fake.call_count, 3U); + + } ZTEST(regulator_api, test_count_voltages_not_implemented) @@ -776,6 +796,8 @@ void *setup(void) zassert_true(device_is_ready(reg1)); zassert_true(device_is_ready(reg2)); zassert_true(device_is_ready(reg3)); + zassert_true(device_is_ready(reg4)); + zassert_true(device_is_ready(reg5)); /* REG1, REG2 initialized at init time (always-on/boot-on) */ zassert_equal(regulator_fake_enable_fake.call_count, 2U); @@ -785,6 +807,13 @@ void *setup(void) /* REG3 mode set at init time (initial-mode) */ zassert_equal(regulator_fake_set_mode_fake.call_count, 1U); + /* REG4 already disabled at init time (boot-off) */ + zassert_false(regulator_is_enabled(reg4)); + + /* REG5 explicitly disabled at init time (boot-off) */ + zassert_equal(regulator_fake_disable_fake.call_count, 1U); + zassert_false(regulator_is_enabled(reg5)); + return NULL; } From a14abeb2e6c0fc0884490a1aa3250405d0ffa9fa Mon Sep 17 00:00:00 2001 From: Andy Sinclair Date: Fri, 23 Feb 2024 11:36:39 +0000 Subject: [PATCH 0128/2402] dts: bindings: regulator: Added regulator-boot-off to allowlists Added regulator-boot-off to property-allowlist for adp5360, npm1300, npm6001 and axp192. Signed-off-by: Andy Sinclair --- dts/bindings/regulator/adi,adp5360-regulator.yaml | 1 + dts/bindings/regulator/nordic,npm1300-regulator.yaml | 1 + dts/bindings/regulator/nordic,npm6001-regulator.yaml | 1 + dts/bindings/regulator/x-powers,axp192-regulator.yaml | 1 + 4 files changed, 4 insertions(+) diff --git a/dts/bindings/regulator/adi,adp5360-regulator.yaml b/dts/bindings/regulator/adi,adp5360-regulator.yaml index d683bd694ef..e54a305e80f 100644 --- a/dts/bindings/regulator/adi,adp5360-regulator.yaml +++ b/dts/bindings/regulator/adi,adp5360-regulator.yaml @@ -34,6 +34,7 @@ child-binding: property-allowlist: - regulator-always-on - regulator-boot-on + - regulator-boot-off - regulator-init-microvolt - regulator-min-microvolt - regulator-max-microvolt diff --git a/dts/bindings/regulator/nordic,npm1300-regulator.yaml b/dts/bindings/regulator/nordic,npm1300-regulator.yaml index c5364a49fe0..e0fc28ff8be 100644 --- a/dts/bindings/regulator/nordic,npm1300-regulator.yaml +++ b/dts/bindings/regulator/nordic,npm1300-regulator.yaml @@ -53,6 +53,7 @@ child-binding: property-allowlist: - regulator-always-on - regulator-boot-on + - regulator-boot-off - regulator-min-microvolt - regulator-max-microvolt - regulator-init-microvolt diff --git a/dts/bindings/regulator/nordic,npm6001-regulator.yaml b/dts/bindings/regulator/nordic,npm6001-regulator.yaml index 34c90c78640..378f6c0a8ec 100644 --- a/dts/bindings/regulator/nordic,npm6001-regulator.yaml +++ b/dts/bindings/regulator/nordic,npm6001-regulator.yaml @@ -45,6 +45,7 @@ child-binding: property-allowlist: - regulator-always-on - regulator-boot-on + - regulator-boot-off - regulator-max-microamp - regulator-min-microvolt - regulator-max-microvolt diff --git a/dts/bindings/regulator/x-powers,axp192-regulator.yaml b/dts/bindings/regulator/x-powers,axp192-regulator.yaml index 98599731c3b..9072e80727b 100644 --- a/dts/bindings/regulator/x-powers,axp192-regulator.yaml +++ b/dts/bindings/regulator/x-powers,axp192-regulator.yaml @@ -51,6 +51,7 @@ child-binding: - regulator-max-microvolt - regulator-always-on - regulator-boot-on + - regulator-boot-off - regulator-initial-mode - regulator-allowed-modes From c3a0ea02a7ad32ff211b6704adc57cef9655917e Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Fri, 19 Jan 2024 10:33:42 -0600 Subject: [PATCH 0129/2402] i2c: Add a new API test using (f/s/nv)ram RAM allows for very fast reads and writes and lets us explore most of the I2C controller APIs including RTIO. Theoretically supports any form of i2c connected RAM but requires some tweaking to work with specific parts potentially. Tested with Fujitsu's MB85 FeRAM part using an arduino breakout. Signed-off-by: Tom Burdick --- drivers/i2c/Kconfig | 1 + include/zephyr/drivers/i2c.h | 17 + tests/drivers/i2c/i2c_ram/CMakeLists.txt | 8 + tests/drivers/i2c/i2c_ram/README.rst | 6 + .../i2c/i2c_ram/boards/mimxrt1010_evk.overlay | 10 + tests/drivers/i2c/i2c_ram/prj.conf | 3 + tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c | 297 ++++++++++++++++++ tests/drivers/i2c/i2c_ram/testcase.yaml | 15 + 8 files changed, 357 insertions(+) create mode 100644 tests/drivers/i2c/i2c_ram/CMakeLists.txt create mode 100644 tests/drivers/i2c/i2c_ram/README.rst create mode 100644 tests/drivers/i2c/i2c_ram/boards/mimxrt1010_evk.overlay create mode 100644 tests/drivers/i2c/i2c_ram/prj.conf create mode 100644 tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c create mode 100644 tests/drivers/i2c/i2c_ram/testcase.yaml diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 86e9cd87934..116fffdb844 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -56,6 +56,7 @@ config I2C_CALLBACK config I2C_RTIO bool "I2C RTIO API" + depends on RTIO help API and implementations of I2C for RTIO diff --git a/include/zephyr/drivers/i2c.h b/include/zephyr/drivers/i2c.h index 074e42527f9..8f8b91aa67f 100644 --- a/include/zephyr/drivers/i2c.h +++ b/include/zephyr/drivers/i2c.h @@ -1011,6 +1011,23 @@ extern const struct rtio_iodev_api i2c_iodev_api; I2C_DT_SPEC_GET(node_id); \ RTIO_IODEV_DEFINE(name, &i2c_iodev_api, (void *)&_i2c_dt_spec_##name) +/** + * @brief Define an iodev for a given i2c device on a bus + * + * These do not need to be shared globally but doing so + * will save a small amount of memory. + * + * @param name Symbolic name of the iodev to define + * @param _bus Node ID for I2C bus + * @param _addr I2C target address + */ +#define I2C_IODEV_DEFINE(name, _bus, _addr) \ + const struct i2c_dt_spec _i2c_dt_spec_##name = { \ + .bus = DEVICE_DT_GET(_bus), \ + .addr = _addr, \ + }; \ + RTIO_IODEV_DEFINE(name, &i2c_iodev_api, (void *)&_i2c_dt_spec_##name) + /** * @brief Copy the i2c_msgs into a set of RTIO requests * diff --git a/tests/drivers/i2c/i2c_ram/CMakeLists.txt b/tests/drivers/i2c/i2c_ram/CMakeLists.txt new file mode 100644 index 00000000000..7aca5726cf5 --- /dev/null +++ b/tests/drivers/i2c/i2c_ram/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(i2c_ram) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/i2c/i2c_ram/README.rst b/tests/drivers/i2c/i2c_ram/README.rst new file mode 100644 index 00000000000..c4863151471 --- /dev/null +++ b/tests/drivers/i2c/i2c_ram/README.rst @@ -0,0 +1,6 @@ +i2c ram test +############ + +Tests an i2c controller driver against a (s/f/nv)ram module doing a simple write and readback. + +Excercises most of the i2c controller APIs in the process. diff --git a/tests/drivers/i2c/i2c_ram/boards/mimxrt1010_evk.overlay b/tests/drivers/i2c/i2c_ram/boards/mimxrt1010_evk.overlay new file mode 100644 index 00000000000..d2b49977fdc --- /dev/null +++ b/tests/drivers/i2c/i2c_ram/boards/mimxrt1010_evk.overlay @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2023 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2c-ram = &arduino_i2c; + }; +}; diff --git a/tests/drivers/i2c/i2c_ram/prj.conf b/tests/drivers/i2c/i2c_ram/prj.conf new file mode 100644 index 00000000000..b2a9b8b5db6 --- /dev/null +++ b/tests/drivers/i2c/i2c_ram/prj.conf @@ -0,0 +1,3 @@ +CONFIG_LOG=y +CONFIG_I2C=y +CONFIG_ZTEST=y diff --git a/tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c b/tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c new file mode 100644 index 00000000000..5b9dbb77ce3 --- /dev/null +++ b/tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * @addtogroup t_i2c_basic + * @{ + * @defgroup t_i2c_read_write test_i2c_read_write + * @brief TestPurpose: verify I2C master can read and write + * @} + */ + +#include +#include +#include +#include + +#define RAM_ADDR (0b10100010 >> 1) + +#if DT_NODE_HAS_STATUS(DT_ALIAS(i2c_ram), okay) +#define I2C_DEV_NODE DT_ALIAS(i2c_ram) +#define TX_DATA_OFFSET 2 +static uint8_t tx_data[9] = {0x00, 0x00, 'Z', 'e', 'p', 'h', 'y', 'r', '\n'}; +static uint8_t rx_cmd[2] = {0x00, 0x00}; +#else +#error "Please set the correct I2C device and alias for i2c_ram to be status okay" +#endif + +uint32_t i2c_cfg = I2C_SPEED_SET(I2C_SPEED_STANDARD) | I2C_MODE_CONTROLLER; +struct i2c_msg msgs[2]; +uint8_t rx_data[7]; + +const struct device *i2c_dev = DEVICE_DT_GET(I2C_DEV_NODE); + +/* Address from datasheet is 0b1010xxxr where x bits are additional + * memory address bits and r is the r/w i2c bit. + * + * However... the address needs to be shifted into the lower 7 bits as + * Zephyr expects a 7bit device address and shifts this left to set the + * i2c r/w bit. + */ + +static void *i2c_ram_setup(void) +{ + int ret; + uint32_t i2c_cfg_tmp; + + zassert_true(device_is_ready(i2c_dev), "I2C device is not read"); + + /* 1. Verify i2c_configure() */ + zassert_ok(i2c_configure(i2c_dev, i2c_cfg), "I2C config failed"); + + /* 2. Verify i2c_get_config(), optional API */ + ret = i2c_get_config(i2c_dev, &i2c_cfg_tmp); + if (ret != -ENOSYS) { + zassert_equal(i2c_cfg, i2c_cfg_tmp, + "I2C get_config returned invalid config"); + } + + return NULL; +} + + +static uint16_t addr; + +static void i2c_ram_before(void *f) +{ + tx_data[0] = (addr >> 8) & 0xFF; + tx_data[1] = (addr) & 0xFF; + rx_cmd[0] = (addr >> 8) & 0xFF; + rx_cmd[1] = (addr) & 0xFF; + addr += ARRAY_SIZE(tx_data) - TX_DATA_OFFSET; + memset(rx_data, 0, ARRAY_SIZE(rx_data)); +} + +ZTEST(i2c_ram, test_ram_transfer) +{ + TC_PRINT("ram using i2c_transfer from thread %p addr %x\n", k_current_get(), addr); + + msgs[0].buf = tx_data; + msgs[0].len = ARRAY_SIZE(tx_data); + msgs[0].flags = I2C_MSG_WRITE | I2C_MSG_STOP; + + zassert_ok(i2c_transfer(i2c_dev, msgs, 1, RAM_ADDR), + "I2C write to fram failed"); + + /* Write the address and read the data back */ + msgs[0].buf = rx_cmd; + msgs[0].len = ARRAY_SIZE(rx_cmd); + msgs[0].flags = I2C_MSG_WRITE; + msgs[1].buf = rx_data; + msgs[1].len = 7; + msgs[1].flags = I2C_MSG_RESTART | I2C_MSG_READ | I2C_MSG_STOP; + + zassert_ok(i2c_transfer(i2c_dev, msgs, 2, RAM_ADDR), + "I2C read from fram failed"); + + zassert_equal(memcmp(&tx_data[TX_DATA_OFFSET], &rx_data[0], ARRAY_SIZE(rx_data)), 0, + "Written and Read data should match"); +} + +ZTEST(i2c_ram, test_ram_write_read) +{ + TC_PRINT("ram using i2c_write and i2c_write_read from thread %p addr %x\n", + k_current_get(), addr); + + zassert_ok(i2c_write(i2c_dev, tx_data, ARRAY_SIZE(tx_data), RAM_ADDR), + "I2C write to fram failed"); + + zassert_ok(i2c_write_read(i2c_dev, RAM_ADDR, rx_cmd, ARRAY_SIZE(rx_cmd), + rx_data, ARRAY_SIZE(rx_data)), + "I2C read from fram failed"); + + zassert_equal(memcmp(&tx_data[TX_DATA_OFFSET], &rx_data[0], ARRAY_SIZE(rx_data)), 0, + "Written and Read data should match"); +} + + +#ifdef CONFIG_I2C_CALLBACK +K_SEM_DEFINE(transfer_sem, 0, 1); + +static void i2c_ram_transfer_cb(const struct device *dev, int result, void *data) +{ + struct k_sem *s = data; + + k_sem_give(s); +} + +ZTEST(i2c_ram, test_ram_transfer_cb) +{ + msgs[0].buf = tx_data; + msgs[0].len = ARRAY_SIZE(tx_data); + msgs[0].flags = I2C_MSG_WRITE | I2C_MSG_STOP; + + zassert_ok(i2c_transfer_cb(i2c_dev, msgs, 1, RAM_ADDR, + i2c_ram_transfer_cb, + &transfer_sem), "I2C write to fram failed"); + + k_sem_take(&transfer_sem, K_FOREVER); + + /* Write the address and read the data back */ + msgs[0].buf = rx_cmd; + msgs[0].len = ARRAY_SIZE(rx_cmd); + msgs[0].flags = I2C_MSG_WRITE; + msgs[1].buf = rx_data; + msgs[1].len = ARRAY_SIZE(rx_data); + msgs[1].flags = I2C_MSG_RESTART | I2C_MSG_READ | I2C_MSG_STOP; + + zassert_ok(i2c_transfer_cb(i2c_dev, msgs, 2, RAM_ADDR, + i2c_ram_transfer_cb, &transfer_sem), + "I2C read from fram failed"); + + k_sem_take(&transfer_sem, K_FOREVER); + + zassert_equal(memcmp(&tx_data[TX_DATA_OFFSET], &rx_data[0], ARRAY_SIZE(rx_data)), 0, + "Written and Read data should match"); + +} +#endif /* CONFIG_I2C_CALLBACK */ + +#ifdef CONFIG_I2C_RTIO +#include + +I2C_IODEV_DEFINE(i2c_iodev, I2C_DEV_NODE, RAM_ADDR); +RTIO_DEFINE(i2c_rtio, 2, 2); + +ZTEST(i2c_ram, test_ram_rtio) +{ + struct rtio_sqe *wr_sqe, *rd_sqe; + struct rtio_cqe *wr_cqe, *rd_cqe; + + TC_PRINT("submitting write from thread %p addr %x\n", k_current_get(), addr); + wr_sqe = rtio_sqe_acquire(&i2c_rtio); + wr_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP; + rtio_sqe_prep_write(wr_sqe, &i2c_iodev, 0, tx_data, ARRAY_SIZE(tx_data), tx_data); + zassert_ok(rtio_submit(&i2c_rtio, 1), "submit should succeed"); + + wr_cqe = rtio_cqe_consume(&i2c_rtio); + zassert_ok(wr_cqe->result, "i2c write should succeed"); + rtio_cqe_release(&i2c_rtio, wr_cqe); + + /* Write the address and read the data back */ + msgs[0].len = ARRAY_SIZE(rx_cmd); + msgs[0].flags = I2C_MSG_WRITE; + msgs[1].buf = rx_data; + msgs[1].len = ARRAY_SIZE(rx_data); + msgs[1].flags = I2C_MSG_RESTART | I2C_MSG_READ | I2C_MSG_STOP; + + wr_sqe = rtio_sqe_acquire(&i2c_rtio); + wr_sqe->flags |= RTIO_SQE_TRANSACTION; + rd_sqe = rtio_sqe_acquire(&i2c_rtio); + rd_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART; + rtio_sqe_prep_write(wr_sqe, &i2c_iodev, 0, rx_cmd, ARRAY_SIZE(rx_cmd), rx_cmd); + rtio_sqe_prep_read(rd_sqe, &i2c_iodev, 0, rx_data, ARRAY_SIZE(rx_data), rx_data); + zassert_ok(rtio_submit(&i2c_rtio, 2), "submit should succeed"); + + wr_cqe = rtio_cqe_consume(&i2c_rtio); + rd_cqe = rtio_cqe_consume(&i2c_rtio); + zassert_ok(wr_cqe->result, "i2c write should succeed"); + zassert_ok(rd_cqe->result, "i2c read should succeed"); + rtio_cqe_release(&i2c_rtio, wr_cqe); + rtio_cqe_release(&i2c_rtio, rd_cqe); + + zassert_equal(memcmp(&tx_data[TX_DATA_OFFSET], &rx_data[0], ARRAY_SIZE(rx_data)), 0, + "Written and Read data should match"); +} + +static enum isr_rtio_state { + INIT, + WRITE_WAIT, + READ_CMD_WAIT, + READ_DATA_WAIT, + DONE +} isr_state = INIT; + +K_SEM_DEFINE(ram_rtio_isr_sem, 0, 1); + +void ram_rtio_isr(struct k_timer *tid) +{ + struct rtio_sqe *wr_sqe, *rd_sqe; + struct rtio_cqe *wr_cqe, *rd_cqe; + + switch (isr_state) { + case INIT: + TC_PRINT("timer submitting write, addr %x\n", addr); + wr_sqe = rtio_sqe_acquire(&i2c_rtio); + wr_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP; + rtio_sqe_prep_write(wr_sqe, &i2c_iodev, 0, tx_data, ARRAY_SIZE(tx_data), tx_data); + zassert_ok(rtio_submit(&i2c_rtio, 0), "submit should succeed"); + isr_state += 1; + break; + case WRITE_WAIT: + wr_cqe = rtio_cqe_consume(&i2c_rtio); + if (wr_cqe) { + TC_PRINT("timer checking write result, submitting read\n"); + zassert_ok(wr_cqe->result, "i2c write should succeed"); + rtio_cqe_release(&i2c_rtio, wr_cqe); + + /* Write the address and read the data back */ + msgs[0].len = ARRAY_SIZE(rx_cmd); + msgs[0].flags = I2C_MSG_WRITE; + msgs[1].buf = rx_data; + msgs[1].len = ARRAY_SIZE(rx_data); + msgs[1].flags = I2C_MSG_RESTART | I2C_MSG_READ | I2C_MSG_STOP; + + wr_sqe = rtio_sqe_acquire(&i2c_rtio); + wr_sqe->flags |= RTIO_SQE_TRANSACTION; + rd_sqe = rtio_sqe_acquire(&i2c_rtio); + rd_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART; + rtio_sqe_prep_write(wr_sqe, &i2c_iodev, 0, rx_cmd, + ARRAY_SIZE(rx_cmd), rx_cmd); + rtio_sqe_prep_read(rd_sqe, &i2c_iodev, 0, rx_data, + ARRAY_SIZE(rx_data), rx_data); + zassert_ok(rtio_submit(&i2c_rtio, 0), "submit should succeed"); + isr_state += 1; + } + break; + case READ_CMD_WAIT: + wr_cqe = rtio_cqe_consume(&i2c_rtio); + if (wr_cqe) { + TC_PRINT("read command complete\n"); + zassert_ok(wr_cqe->result, "i2c read command should succeed"); + rtio_cqe_release(&i2c_rtio, wr_cqe); + isr_state += 1; + } + break; + case READ_DATA_WAIT: + rd_cqe = rtio_cqe_consume(&i2c_rtio); + if (rd_cqe) { + TC_PRINT("read data complete\n"); + zassert_ok(rd_cqe->result, "i2c read data should succeed"); + rtio_cqe_release(&i2c_rtio, rd_cqe); + isr_state += 1; + k_sem_give(&ram_rtio_isr_sem); + k_timer_stop(tid); + } + break; + default: + + zassert_ok(-1, "Should not get here"); + } +} + +K_TIMER_DEFINE(ram_rtio_isr_timer, ram_rtio_isr, NULL); + + +ZTEST(i2c_ram, test_ram_rtio_isr) +{ + k_timer_start(&ram_rtio_isr_timer, K_MSEC(1), K_MSEC(1)); + k_sem_take(&ram_rtio_isr_sem, K_FOREVER); +} + +#endif /* CONFIG_I2C_RTIO */ + +ZTEST_SUITE(i2c_ram, NULL, i2c_ram_setup, i2c_ram_before, NULL, NULL); diff --git a/tests/drivers/i2c/i2c_ram/testcase.yaml b/tests/drivers/i2c/i2c_ram/testcase.yaml new file mode 100644 index 00000000000..3bed6b96a87 --- /dev/null +++ b/tests/drivers/i2c/i2c_ram/testcase.yaml @@ -0,0 +1,15 @@ +common: + depends_on: i2c + tags: + - drivers + - i2c + filter: dt_alias_exists("i2c_ram") +tests: + drivers.i2c.ram: + depends_on: i2c + tags: + - drivers + - i2c + drivers.i2c.ram.rtio: + extra_configs: + - CONFIG_I2C_RTIO=y From 1fd7de6aded6d96bee9ee2296a5cd622de1d13dd Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Mon, 5 Feb 2024 08:33:01 -0600 Subject: [PATCH 0130/2402] rtio: Add support for i2c recovery command Adds support for the i2c recovery operation as an opcode in RTIO Signed-off-by: Tom Burdick --- include/zephyr/rtio/rtio.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/zephyr/rtio/rtio.h b/include/zephyr/rtio/rtio.h index 79ab78dc58c..a4b6f6b9aa0 100644 --- a/include/zephyr/rtio/rtio.h +++ b/include/zephyr/rtio/rtio.h @@ -470,6 +470,9 @@ struct rtio_iodev { /** An operation that transceives (reads and writes simultaneously) */ #define RTIO_OP_TXRX (RTIO_OP_CALLBACK+1) +/** An operation to recover I2C buses */ +#define RTIO_OP_I2C_RECOVER (RTIO_OP_TXRX+1) + /** * @brief Prepare a nop (no op) submission From 4c8b1e2d1e6146592a6760fb2a1722ebd589d2d2 Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Mon, 12 Feb 2024 12:35:30 -0600 Subject: [PATCH 0131/2402] rtio: Add I2C configure operation In order to serialize all of the i2c functionality an added op code for configuring the i2c controller was needed. Thankfully very simple. Signed-off-by: Tom Burdick --- drivers/i2c/i2c_rtio.c | 169 +++++++++++++++++++++++++++++++++++++ include/zephyr/rtio/rtio.h | 4 + 2 files changed, 173 insertions(+) diff --git a/drivers/i2c/i2c_rtio.c b/drivers/i2c/i2c_rtio.c index 6c02837065d..002c74c3a37 100644 --- a/drivers/i2c/i2c_rtio.c +++ b/drivers/i2c/i2c_rtio.c @@ -47,3 +47,172 @@ struct rtio_sqe *i2c_rtio_copy(struct rtio *r, return sqe; } + +void i2c_rtio_init(struct i2c_rtio *ctx, const struct device *dev) +{ + k_sem_init(&ctx->lock, 1, 1); + rtio_mpsc_init(&ctx->io_q); + ctx->txn_curr = NULL; + ctx->txn_head = NULL; + ctx->dt_spec.bus = dev; + ctx->iodev.data = &ctx->dt_spec; + ctx->iodev.api = &i2c_iodev_api; + /* TODO drop the builtin submission queue? */ + rtio_mpsc_init(&ctx->iodev.iodev_sq); +} + +/** + * @private + * @brief Setup the next transaction (could be a single op) if needed + * + * @retval true New transaction to start with the hardware is setup + * @retval false No new transaction to start + */ +static bool i2c_rtio_next(struct i2c_rtio *ctx, bool completion) +{ + k_spinlock_key_t key = k_spin_lock(&ctx->slock); + + /* Already working on something, bail early */ + if (!completion && ctx->txn_head != NULL) { + k_spin_unlock(&ctx->slock, key); + return false; + } + + struct rtio_mpsc_node *next = rtio_mpsc_pop(&ctx->io_q); + + /* Nothing left to do */ + if (next == NULL) { + ctx->txn_head = NULL; + ctx->txn_curr = NULL; + k_spin_unlock(&ctx->slock, key); + return false; + } + + ctx->txn_head = CONTAINER_OF(next, struct rtio_iodev_sqe, q); + ctx->txn_curr = ctx->txn_head; + + k_spin_unlock(&ctx->slock, key); + + return true; +} + +bool i2c_rtio_complete(struct i2c_rtio *ctx, int status) +{ + /* On error bail */ + if (status < 0) { + rtio_iodev_sqe_err(ctx->txn_head, status); + return i2c_rtio_next(ctx, true); + } + + /* Try for next submission in the transaction */ + ctx->txn_curr = rtio_txn_next(ctx->txn_curr); + if (ctx->txn_curr) { + return true; + } + + rtio_iodev_sqe_ok(ctx->txn_head, status); + return i2c_rtio_next(ctx, true); +} +bool i2c_rtio_submit(struct i2c_rtio *ctx, struct rtio_iodev_sqe *iodev_sqe) +{ + rtio_mpsc_push(&ctx->iodev.iodev_sq, &iodev_sqe->q); + return i2c_rtio_next(ctx, false); +} + +int i2c_rtio_transfer(struct i2c_rtio *ctx, struct i2c_msg *msgs, uint8_t num_msgs, uint16_t addr) +{ + struct rtio_iodev *iodev = &ctx->iodev; + struct rtio *const r = ctx->r; + struct rtio_sqe *sqe = NULL; + struct rtio_cqe *cqe = NULL; + int res = 0; + + k_sem_take(&ctx->lock, K_FOREVER); + + ctx->dt_spec.addr = addr; + + sqe = i2c_rtio_copy(r, iodev, msgs, num_msgs); + if (sqe == NULL) { + LOG_ERR("Not enough submission queue entries"); + res = -ENOMEM; + goto out; + } + + sqe->flags &= ~RTIO_SQE_TRANSACTION; + + rtio_submit(r, 1); + + cqe = rtio_cqe_consume(r); + while (cqe != NULL) { + res = cqe->result; + rtio_cqe_release(r, cqe); + cqe = rtio_cqe_consume(r); + } + +out: + k_sem_give(&ctx->lock); + return res; +} + +int i2c_rtio_configure(struct i2c_rtio *ctx, uint32_t i2c_config) +{ + struct rtio_iodev *iodev = &ctx->iodev; + struct rtio *const r = ctx->r; + struct rtio_sqe *sqe = NULL; + struct rtio_cqe *cqe = NULL; + int res = 0; + + k_sem_take(&ctx->lock, K_FOREVER); + + sqe = rtio_sqe_acquire(r); + if (sqe == NULL) { + LOG_ERR("Not enough submission queue entries"); + res = -ENOMEM; + goto out; + } + + sqe->op = RTIO_OP_I2C_CONFIGURE; + sqe->iodev = iodev; + sqe->i2c_config = i2c_config; + + rtio_submit(r, 1); + + cqe = rtio_cqe_consume(r); + res = cqe->result; + rtio_cqe_release(r, cqe); + +out: + k_sem_give(&ctx->lock); + return res; +} + +int i2c_rtio_recover(struct i2c_rtio *ctx) +{ + struct rtio_iodev *iodev = &ctx->iodev; + struct rtio *const r = ctx->r; + struct rtio_sqe *sqe = NULL; + struct rtio_cqe *cqe = NULL; + int res = 0; + + k_sem_take(&ctx->lock, K_FOREVER); + + sqe = rtio_sqe_acquire(r); + if (sqe == NULL) { + LOG_ERR("Not enough submission queue entries"); + res = -ENOMEM; + goto out; + } + + sqe->op = RTIO_OP_I2C_RECOVER; + sqe->iodev = iodev; + + rtio_submit(r, 1); + + cqe = rtio_cqe_consume(r); + res = cqe->result; + rtio_cqe_release(r, cqe); + +out: + k_sem_give(&ctx->lock); + return res; +} diff --git a/include/zephyr/rtio/rtio.h b/include/zephyr/rtio/rtio.h index a4b6f6b9aa0..17fc3a2549e 100644 --- a/include/zephyr/rtio/rtio.h +++ b/include/zephyr/rtio/rtio.h @@ -276,6 +276,8 @@ struct rtio_sqe { uint8_t *rx_buf; }; + /** OP_I2C_CONFIGURE */ + uint32_t i2c_config; }; }; @@ -473,6 +475,8 @@ struct rtio_iodev { /** An operation to recover I2C buses */ #define RTIO_OP_I2C_RECOVER (RTIO_OP_TXRX+1) +/** An operation to configure I2C buses */ +#define RTIO_OP_I2C_CONFIGURE (RTIO_OP_I2C_RECOVER+1) /** * @brief Prepare a nop (no op) submission From 1fb449c9bcc79a626afd886fadee4f62c57d577d Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Mon, 12 Feb 2024 13:09:40 -0600 Subject: [PATCH 0132/2402] rtio: Align i2c flags with i2c.h flags Aligns the flags in rtio.h for i2c with those in i2c.h Signed-off-by: Tom Burdick --- include/zephyr/rtio/rtio.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/zephyr/rtio/rtio.h b/include/zephyr/rtio/rtio.h index 17fc3a2549e..b38644c6efb 100644 --- a/include/zephyr/rtio/rtio.h +++ b/include/zephyr/rtio/rtio.h @@ -193,17 +193,17 @@ extern "C" { /** * @brief Equivalent to the I2C_MSG_STOP flag */ -#define RTIO_IODEV_I2C_STOP BIT(0) +#define RTIO_IODEV_I2C_STOP BIT(1) /** * @brief Equivalent to the I2C_MSG_RESTART flag */ -#define RTIO_IODEV_I2C_RESTART BIT(1) +#define RTIO_IODEV_I2C_RESTART BIT(2) /** * @brief Equivalent to the I2C_MSG_ADDR_10_BITS */ -#define RTIO_IODEV_I2C_10_BITS BIT(2) +#define RTIO_IODEV_I2C_10_BITS BIT(3) /** @cond ignore */ struct rtio; From ab590fdb2888c7ef44b033f1ef8c688efe2660fe Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Thu, 8 Feb 2024 13:43:33 -0600 Subject: [PATCH 0133/2402] rtio: Drop include for toolchain.h It's not needed and was likely accidently automatically included by clangd lsp at some point. Signed-off-by: Tom Burdick --- include/zephyr/rtio/rtio_mpsc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/zephyr/rtio/rtio_mpsc.h b/include/zephyr/rtio/rtio_mpsc.h index f129f5712aa..9551d1c5cc4 100644 --- a/include/zephyr/rtio/rtio_mpsc.h +++ b/include/zephyr/rtio/rtio_mpsc.h @@ -10,7 +10,6 @@ #include #include -#include #include #include From e8b528321ae17ee5862fc2fb86bf0b7d5ebd0572 Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Mon, 12 Feb 2024 13:11:14 -0600 Subject: [PATCH 0134/2402] i2c: Select rtio when I2C_RTIO is selected Rather than a depends on, which leaves it up to every single usage of I2C_RTIO to then go and select RTIO, by selecting I2C_RTIO Kconfig inherently selects RTIO now. Signed-off-by: Tom Burdick --- drivers/i2c/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 116fffdb844..f92658f1b32 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -56,7 +56,7 @@ config I2C_CALLBACK config I2C_RTIO bool "I2C RTIO API" - depends on RTIO + select RTIO help API and implementations of I2C for RTIO From bbe8833f25fc2b048f320fbf976b7b8f1e8cae33 Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Mon, 12 Feb 2024 12:36:31 -0600 Subject: [PATCH 0135/2402] i2c: Add submissions queue/completion queue bind To enable per peripheral queue pool sizing options add some bindings to the i2c controller to setup sq/cq pool sizing. Its possible this could go away with a shared application pair of pools. The shared pool would require some added function pointers though to deal with the variants as the shared pools would need a lock. Signed-off-by: Tom Burdick --- dts/bindings/i2c/i2c-controller.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/dts/bindings/i2c/i2c-controller.yaml b/dts/bindings/i2c/i2c-controller.yaml index f8b3a30dcf6..acf1c200bd3 100644 --- a/dts/bindings/i2c/i2c-controller.yaml +++ b/dts/bindings/i2c/i2c-controller.yaml @@ -17,3 +17,11 @@ properties: clock-frequency: type: int description: Initial clock frequency in Hz + sq-size: + type: int + default: 4 + description: Size of the submission queue for blocking requests + cq-size: + type: int + default: 4 + description: Size of the completion queue for blocking requests From bafac2c6895111870e9c52705920391c631f37e2 Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Tue, 6 Feb 2024 20:42:40 -0600 Subject: [PATCH 0136/2402] i2c: Add helpers and context for i2c rtio drivers Implementing RTIO drivers, in theory, should be as simple as the normal i2c drivers and generally be more consistent across implementations. To do that some common code that calls driver specific code is needed much like the venerable spi_context and its helpers. This adds struct i2c_rtio as well as helpers to perform blocking i2c transfers, i2c bus recovery, and similar such tasks. Signed-off-by: Tom Burdick --- drivers/i2c/Kconfig | 24 +++++++ drivers/i2c/i2c_rtio.c | 26 ++++--- include/zephyr/drivers/i2c/rtio.h | 115 ++++++++++++++++++++++++++++++ 3 files changed, 154 insertions(+), 11 deletions(-) create mode 100644 include/zephyr/drivers/i2c/rtio.h diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index f92658f1b32..bba632dfe95 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -60,6 +60,30 @@ config I2C_RTIO help API and implementations of I2C for RTIO +if I2C_RTIO +config I2C_RTIO_SQ_SIZE + int "Submission queue size for blocking calls" + default 4 + help + Blocking i2c calls when I2C_RTIO is enabled are copied into a per driver + submission queue. The queue depth determines the number of possible i2c_msg + structs that may be in the array given to i2c_transfer. A sensible default + is going to be 4 given the device address, register address, and a value + to be read or written. + +config I2C_RTIO_CQ_SIZE + int "Completion queue size for blocking calls" + default 4 + help + Blocking i2c calls when I2C_RTIO is enabled are copied into a per driver + submission queue. The queue depth determines the number of possible i2c_msg + structs that may be in the array given to i2c_transfer. A sensible default + is going to be 4 given the device address, register address, and a value + to be read or written. + +endif # I2C_RTIO + + # Include these first so that any properties (e.g. defaults) below can be # overridden (by defining symbols in multiple locations) source "drivers/i2c/Kconfig.b91" diff --git a/drivers/i2c/i2c_rtio.c b/drivers/i2c/i2c_rtio.c index 002c74c3a37..0a43acc4f62 100644 --- a/drivers/i2c/i2c_rtio.c +++ b/drivers/i2c/i2c_rtio.c @@ -4,18 +4,21 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include #include -#include +#include +#include +#include #include +#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL +#include +LOG_MODULE_REGISTER(i2c_rtio); + const struct rtio_iodev_api i2c_iodev_api = { .submit = i2c_iodev_submit, }; -struct rtio_sqe *i2c_rtio_copy(struct rtio *r, - struct rtio_iodev *iodev, - const struct i2c_msg *msgs, +struct rtio_sqe *i2c_rtio_copy(struct rtio *r, struct rtio_iodev *iodev, const struct i2c_msg *msgs, uint8_t num_msgs) { __ASSERT(num_msgs > 0, "Expecting at least one message to copy"); @@ -31,14 +34,15 @@ struct rtio_sqe *i2c_rtio_copy(struct rtio *r, } if (msgs[i].flags & I2C_MSG_READ) { - rtio_sqe_prep_read(sqe, iodev, RTIO_PRIO_NORM, - msgs[i].buf, msgs[i].len, NULL); + rtio_sqe_prep_read(sqe, iodev, RTIO_PRIO_NORM, msgs[i].buf, msgs[i].len, + NULL); } else { - rtio_sqe_prep_write(sqe, iodev, RTIO_PRIO_NORM, - msgs[i].buf, msgs[i].len, NULL); + rtio_sqe_prep_write(sqe, iodev, RTIO_PRIO_NORM, msgs[i].buf, msgs[i].len, + NULL); } sqe->flags |= RTIO_SQE_TRANSACTION; - sqe->iodev_flags = ((msgs[i].flags & I2C_MSG_STOP) ? RTIO_IODEV_I2C_STOP : 0) | + sqe->iodev_flags = + ((msgs[i].flags & I2C_MSG_STOP) ? RTIO_IODEV_I2C_STOP : 0) | ((msgs[i].flags & I2C_MSG_RESTART) ? RTIO_IODEV_I2C_RESTART : 0) | ((msgs[i].flags & I2C_MSG_ADDR_10_BITS) ? RTIO_IODEV_I2C_10_BITS : 0); } @@ -115,7 +119,7 @@ bool i2c_rtio_complete(struct i2c_rtio *ctx, int status) } bool i2c_rtio_submit(struct i2c_rtio *ctx, struct rtio_iodev_sqe *iodev_sqe) { - rtio_mpsc_push(&ctx->iodev.iodev_sq, &iodev_sqe->q); + rtio_mpsc_push(&ctx->io_q, &iodev_sqe->q); return i2c_rtio_next(ctx, false); } diff --git a/include/zephyr/drivers/i2c/rtio.h b/include/zephyr/drivers/i2c/rtio.h new file mode 100644 index 00000000000..c98aec4586f --- /dev/null +++ b/include/zephyr/drivers/i2c/rtio.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_I2C_RTIO_H_ +#define ZEPHYR_DRIVERS_I2C_RTIO_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Driver context for implementing i2c with rtio + */ +struct i2c_rtio { + struct k_sem lock; + struct k_spinlock slock; + struct rtio *r; + struct rtio_mpsc io_q; + struct rtio_iodev iodev; + struct rtio_iodev_sqe *txn_head; + struct rtio_iodev_sqe *txn_curr; + struct i2c_dt_spec dt_spec; +}; + +/** + * @brief Statically define an i2c_rtio context + * + * @param _name Symbolic name of the context + * @param _sq_sz Submission queue entry pool size + * @param _cq_sz Completeion queue entry pool size + */ +#define I2C_RTIO_DEFINE(_name, _sq_sz, _cq_sz) \ + RTIO_DEFINE(_name##_r, _sq_sz, _cq_sz); \ + static struct i2c_rtio _name = { \ + .r = &_name##_r, \ + }; + +/** + * @brief Copy an an array of i2c_msgs to rtio submissions and a transaction + * + * @retval sqe Last sqe setup in the copy + * @retval NULL Not enough memory to copy the transaction + */ +struct rtio_sqe *i2c_rtio_copy(struct rtio *r, struct rtio_iodev *iodev, const struct i2c_msg *msgs, + uint8_t num_msgs); + +/** + * @brief Initialize an i2c rtio context + * + * @param ctx I2C RTIO driver context + * @param dev I2C bus + */ +void i2c_rtio_init(struct i2c_rtio *ctx, const struct device *dev); + +/** + * @brief Signal that the current (ctx->txn_curr) submission has been completed + * + * @param ctx I2C RTIO driver context + * @param status Completion status, negative values are errors + * + * @retval true Next submission is ready to start + * @retval false No more submissions to work on + */ +bool i2c_rtio_complete(struct i2c_rtio *ctx, int status); + +/** + * @brief Submit, atomically, a submission to work on at some point + * + * @retval true Next submission is ready to start + * @retval false No new submission to start or submissions are in progress already + */ +bool i2c_rtio_submit(struct i2c_rtio *ctx, struct rtio_iodev_sqe *iodev_sqe); + +/** + * @brief Configure the I2C bus controller + * + * Provides a compatible API for the existing i2c_configure API, and blocks the + * caller until the transfer completes. + * + * See i2c_configure(). + */ +int i2c_rtio_configure(struct i2c_rtio *ctx, uint32_t i2c_config); + +/** + * @brief Transfer i2c messages in a blocking call + * + * Provides a compatible API for the existing i2c_transfer API, and blocks the caller + * until the transfer completes. + * + * See i2c_transfer(). + */ +int i2c_rtio_transfer(struct i2c_rtio *ctx, struct i2c_msg *msgs, uint8_t num_msgs, uint16_t addr); + +/** + * @brief Perform an I2C bus recovery in a blocking call + * + * Provides a compatible API for the existing i2c_recover API, and blocks the caller + * until the process completes. + * + * See i2c_recover(). + */ +int i2c_rtio_recover(struct i2c_rtio *ctx); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_DRVIERS_I2C_RTIO_H_ */ From 0dbc3d712ce286d60264232073755898d9a73ca1 Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Wed, 7 Feb 2024 15:17:28 -0600 Subject: [PATCH 0137/2402] i2c: Use i2c_rtio context in sam twihs driver Updates the sam twihs rtio driver to use a common i2c_rtio context object and fixes a few logic issues currently in the driver in the process. Signed-off-by: Tom Burdick --- drivers/i2c/Kconfig.sam_twihs | 28 +------- drivers/i2c/i2c_sam_twihs_rtio.c | 117 ++++++------------------------- 2 files changed, 21 insertions(+), 124 deletions(-) diff --git a/drivers/i2c/Kconfig.sam_twihs b/drivers/i2c/Kconfig.sam_twihs index c84eba29b8c..5f1daa6f4c4 100644 --- a/drivers/i2c/Kconfig.sam_twihs +++ b/drivers/i2c/Kconfig.sam_twihs @@ -3,35 +3,9 @@ # Copyright (c) 2023 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -menuconfig I2C_SAM_TWIHS +config I2C_SAM_TWIHS bool "Atmel SAM (TWIHS) I2C driver" default y depends on DT_HAS_ATMEL_SAM_I2C_TWIHS_ENABLED help Enable Atmel SAM MCU Family (TWIHS) I2C bus driver. - -if I2C_SAM_TWIHS -if I2C_RTIO - -config I2C_SAM_TWIHS_SQ_SIZE - int "Submission queue size for blocking calls" - default 4 - help - Blocking i2c calls when I2C_RTIO is enabled are copied into a per driver - submission queue. The queue depth determines the number of possible i2c_msg - structs that may be in the array given to i2c_transfer. A sensible default - is going to be 4 given the device address, register address, and a value - to be read or written. - -config I2C_SAM_TWIHS_CQ_SIZE - int "Completion queue size for blocking calls" - default 4 - help - Blocking i2c calls when I2C_RTIO is enabled are copied into a per driver - submission queue. The queue depth determines the number of possible i2c_msg - structs that may be in the array given to i2c_transfer. A sensible default - is going to be 4 given the device address, register address, and a value - to be read or written. - -endif # I2C_RTIO -endif # I2C_SAM_TWIHS diff --git a/drivers/i2c/i2c_sam_twihs_rtio.c b/drivers/i2c/i2c_sam_twihs_rtio.c index 40abfd0c263..db8d02e6034 100644 --- a/drivers/i2c/i2c_sam_twihs_rtio.c +++ b/drivers/i2c/i2c_sam_twihs_rtio.c @@ -6,7 +6,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include #define DT_DRV_COMPAT atmel_sam_i2c_twihs /** @file @@ -15,7 +14,6 @@ * Only I2C Controller Mode with 7 bit addressing is currently supported. */ - #include #include #include @@ -23,9 +21,9 @@ #include #include #include +#include #include #include -#include #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL #include @@ -55,14 +53,7 @@ struct i2c_sam_twihs_dev_cfg { /* Device run time data */ struct i2c_sam_twihs_dev_data { - struct k_spinlock lock; - struct k_sem block_lock; - struct i2c_dt_spec dt_spec; - struct rtio_iodev iodev; - struct rtio *r; - struct rtio_mpsc io_q; - struct rtio_iodev_sqe *iodev_sqe; - const struct rtio_sqe *sqe; + struct i2c_rtio *ctx; uint32_t buf_idx; }; @@ -184,7 +175,7 @@ static void i2c_sam_twihs_start(const struct device *dev) struct i2c_sam_twihs_dev_data *const dev_data = dev->data; const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config; Twihs *const twihs = dev_cfg->regs; - const struct rtio_sqe *const sqe = dev_data->sqe; + struct rtio_sqe *sqe = &dev_data->ctx->txn_curr->sqe; struct i2c_dt_spec *dt_spec = sqe->iodev->data; /* Clear pending interrupts, such as NACK. */ @@ -210,64 +201,29 @@ static void i2c_sam_twihs_start(const struct device *dev) } } -static void i2c_sam_twihs_next(const struct device *dev, bool completion) -{ - struct i2c_sam_twihs_dev_data *data = dev->data; - - k_spinlock_key_t key = k_spin_lock(&data->lock); - - if (!completion && data->iodev_sqe != NULL) { - k_spin_unlock(&data->lock, key); - return; - } - - struct rtio_mpsc_node *next = rtio_mpsc_pop(&data->io_q); - - if (next == NULL) { - data->iodev_sqe = NULL; - data->sqe = NULL; - k_spin_unlock(&data->lock, key); - return; - } - - data->iodev_sqe = CONTAINER_OF(next, struct rtio_iodev_sqe, q); - data->sqe = data->iodev_sqe->sqe; - k_spin_unlock(&data->lock, key); - - i2c_sam_twihs_start(dev); -} - static void i2c_sam_twihs_complete(const struct device *dev, int status) { const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config; - struct i2c_sam_twihs_dev_data *const dev_data = dev->data; Twihs *const twihs = dev_cfg->regs; - struct rtio_iodev_sqe *iodev_sqe = dev_data->iodev_sqe; + struct i2c_rtio *const ctx = ((struct i2c_sam_twihs_dev_data *) + dev->data)->ctx; /* Disable all enabled interrupts */ twihs->TWIHS_IDR = twihs->TWIHS_IMR; - if (status < 0) { - rtio_iodev_sqe_err(iodev_sqe, status); - i2c_sam_twihs_next(dev, true); - return; - } - - if (dev_data->sqe->flags & RTIO_SQE_TRANSACTION) { - dev_data->sqe = rtio_spsc_next(iodev_sqe->r->sq, dev_data->sqe); + if (i2c_rtio_complete(ctx, status)) { i2c_sam_twihs_start(dev); - } else { - rtio_iodev_sqe_ok(iodev_sqe, status); - i2c_sam_twihs_next(dev, true); } } static void i2c_sam_twihs_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe) { - struct i2c_sam_twihs_dev_data *const dev_data = dev->data; + struct i2c_rtio *const ctx = ((struct i2c_sam_twihs_dev_data *) + dev->data)->ctx; - rtio_mpsc_push(&dev_data->io_q, &iodev_sqe->q); - i2c_sam_twihs_next(dev, false); + if (i2c_rtio_submit(ctx, iodev_sqe)) { + i2c_sam_twihs_start(dev); + } } static void i2c_sam_twihs_isr(const struct device *dev) @@ -275,7 +231,7 @@ static void i2c_sam_twihs_isr(const struct device *dev) const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config; struct i2c_sam_twihs_dev_data *const dev_data = dev->data; Twihs *const twihs = dev_cfg->regs; - const struct rtio_sqe *const sqe = dev_data->sqe; + struct rtio_sqe *sqe = &dev_data->ctx->txn_curr->sqe; uint32_t isr_status; /* Retrieve interrupt status */ @@ -325,39 +281,10 @@ static void i2c_sam_twihs_isr(const struct device *dev) static int i2c_sam_twihs_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs, uint16_t addr) { - struct i2c_sam_twihs_dev_data *const dev_data = dev->data; - struct rtio_iodev *iodev = &dev_data->iodev; - struct rtio *const r = dev_data->r; - struct rtio_sqe *sqe = NULL; - struct rtio_cqe *cqe = NULL; - int res = 0; - - k_sem_take(&dev_data->block_lock, K_FOREVER); - - dev_data->dt_spec.addr = addr; - - sqe = i2c_rtio_copy(r, iodev, msgs, num_msgs); - if (sqe == NULL) { - LOG_ERR("Not enough submission queue entries"); - res = -ENOMEM; - goto out; - } - - sqe->flags &= ~RTIO_SQE_TRANSACTION; - - rtio_submit(r, 1); - - cqe = rtio_cqe_consume(r); - __ASSERT(cqe != NULL, "Expected valid completion"); - while (cqe != NULL) { - res = cqe->result; - cqe = rtio_cqe_consume(r); - } - rtio_cqe_release_all(r); + struct i2c_rtio *const ctx = ((struct i2c_sam_twihs_dev_data *) + dev->data)->ctx; -out: - k_sem_give(&dev_data->block_lock); - return res; + return i2c_rtio_transfer(ctx, msgs, num_msgs, addr); } static int i2c_sam_twihs_initialize(const struct device *dev) @@ -392,11 +319,7 @@ static int i2c_sam_twihs_initialize(const struct device *dev) return ret; } - k_sem_init(&dev_data->block_lock, 1, 1); - dev_data->dt_spec.bus = dev; - dev_data->iodev.api = &i2c_iodev_api; - dev_data->iodev.data = &dev_data->dt_spec; - rtio_mpsc_init(&dev_data->io_q); + i2c_rtio_init(dev_data->ctx, dev); /* Enable module's IRQ */ irq_enable(dev_cfg->irq_id); @@ -421,9 +344,9 @@ static const struct i2c_driver_api i2c_sam_twihs_driver_api = { DEVICE_DT_INST_GET(n), 0); \ } \ \ - RTIO_DEFINE(_i2c##n##_sam_rtio, \ - CONFIG_I2C_SAM_TWIHS_SQ_SIZE, \ - CONFIG_I2C_SAM_TWIHS_CQ_SIZE); \ + I2C_RTIO_DEFINE(_i2c##n##_sam_rtio, \ + DT_INST_PROP_OR(n, sq_size, CONFIG_I2C_RTIO_SQ_SIZE), \ + DT_INST_PROP_OR(n, cq_size, CONFIG_I2C_RTIO_CQ_SIZE)); \ \ static const struct i2c_sam_twihs_dev_cfg i2c##n##_sam_config = { \ .regs = (Twihs *)DT_INST_REG_ADDR(n), \ @@ -435,7 +358,7 @@ static const struct i2c_driver_api i2c_sam_twihs_driver_api = { }; \ \ static struct i2c_sam_twihs_dev_data i2c##n##_sam_data = { \ - .r = &_i2c##n##_sam_rtio, \ + .ctx = &_i2c##n##_sam_rtio, \ }; \ \ I2C_DEVICE_DT_INST_DEFINE(n, i2c_sam_twihs_initialize, \ From 0b980e1baee9e8f020bc69497f0242fba3511535 Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Mon, 5 Feb 2024 08:32:45 -0600 Subject: [PATCH 0138/2402] i2c: Add rtio support to mcux lpi2c driver A seperate driver for NXP's LPI2C using RTIO and the I2C RTIO context rather than semaphores, allowing for work to be done from any call context at any time. Signed-off-by: Tom Burdick --- drivers/i2c/CMakeLists.txt | 12 +- drivers/i2c/i2c_mcux_lpi2c_rtio.c | 391 ++++++++++++++++++++++++++++++ 2 files changed, 401 insertions(+), 2 deletions(-) create mode 100644 drivers/i2c/i2c_mcux_lpi2c_rtio.c diff --git a/drivers/i2c/CMakeLists.txt b/drivers/i2c/CMakeLists.txt index fe96c112202..53d924850f2 100644 --- a/drivers/i2c/CMakeLists.txt +++ b/drivers/i2c/CMakeLists.txt @@ -21,16 +21,24 @@ zephyr_library_sources_ifdef(CONFIG_I2C_LPC11U6X i2c_lpc11u6x.c) zephyr_library_sources_ifdef(CONFIG_I2C_XEC i2c_mchp_xec.c) zephyr_library_sources_ifdef(CONFIG_I2C_MCUX i2c_mcux.c) zephyr_library_sources_ifdef(CONFIG_I2C_MCUX_FLEXCOMM i2c_mcux_flexcomm.c) -zephyr_library_sources_ifdef(CONFIG_I2C_MCUX_LPI2C i2c_mcux_lpi2c.c) + +if(CONFIG_I2C_RTIO) + zephyr_library_sources_ifdef(CONFIG_I2C_MCUX_LPI2C i2c_mcux_lpi2c_rtio.c) +else() + zephyr_library_sources_ifdef(CONFIG_I2C_MCUX_LPI2C i2c_mcux_lpi2c.c) +endif() + zephyr_library_sources_ifdef(CONFIG_I2C_EMUL i2c_emul.c) zephyr_library_sources_ifdef(CONFIG_I2C_NRFX_TWI i2c_nrfx_twi.c) zephyr_library_sources_ifdef(CONFIG_I2C_NRFX_TWIM i2c_nrfx_twim.c) zephyr_library_sources_ifdef(CONFIG_I2C_SAM_TWI i2c_sam_twi.c) -if(CONFIG_RTIO) + +if(CONFIG_I2C_RTIO) zephyr_library_sources_ifdef(CONFIG_I2C_SAM_TWIHS i2c_sam_twihs_rtio.c) else() zephyr_library_sources_ifdef(CONFIG_I2C_SAM_TWIHS i2c_sam_twihs.c) endif() + zephyr_library_sources_ifdef(CONFIG_I2C_SAM_TWIM i2c_sam4l_twim.c) zephyr_library_sources_ifdef(CONFIG_I2C_SBCON i2c_sbcon.c) zephyr_library_sources_ifdef(CONFIG_I2C_SIFIVE i2c_sifive.c) diff --git a/drivers/i2c/i2c_mcux_lpi2c_rtio.c b/drivers/i2c/i2c_mcux_lpi2c_rtio.c new file mode 100644 index 00000000000..bd966d3017a --- /dev/null +++ b/drivers/i2c/i2c_mcux_lpi2c_rtio.c @@ -0,0 +1,391 @@ +/* + * Copyright (c) 2016 Freescale Semiconductor, Inc. + * Copyright 2019-2023, NXP + * Copyright (c) 2022 Vestas Wind Systems A/S + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_imx_lpi2c + +#include +#include +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY +#include "i2c_bitbang.h" +#include +#endif /* CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY */ + +#include +LOG_MODULE_REGISTER(mcux_lpi2c); + +#include "i2c-priv.h" +/* Wait for the duration of 12 bits to detect a NAK after a bus + * address scan. (10 appears sufficient, 20% safety factor.) + */ +#define SCAN_DELAY_US(baudrate) (12 * USEC_PER_SEC / baudrate) + +/* Required by DEVICE_MMIO_NAMED_* macros */ +#define DEV_CFG(_dev) \ + ((const struct mcux_lpi2c_config *)(_dev)->config) +#define DEV_DATA(_dev) ((struct mcux_lpi2c_data *)(_dev)->data) + +struct mcux_lpi2c_config { + DEVICE_MMIO_NAMED_ROM(reg_base); + const struct device *clock_dev; + clock_control_subsys_t clock_subsys; + void (*irq_config_func)(const struct device *dev); + uint32_t bitrate; + uint32_t bus_idle_timeout_ns; + const struct pinctrl_dev_config *pincfg; +#ifdef CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY + struct gpio_dt_spec scl; + struct gpio_dt_spec sda; +#endif /* CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY */ +}; + +struct mcux_lpi2c_data { + DEVICE_MMIO_NAMED_RAM(reg_base); + lpi2c_master_handle_t handle; + struct i2c_rtio *ctx; + lpi2c_master_transfer_t transfer; +#ifdef CONFIG_I2C_TARGET + lpi2c_slave_handle_t target_handle; + struct i2c_target_config *target_cfg; + bool target_attached; + bool first_tx; + bool read_active; + bool send_ack; +#endif +}; + +static int mcux_lpi2c_configure(const struct device *dev, + uint32_t dev_config_raw) +{ + struct i2c_rtio *const ctx = ((struct mcux_lpi2c_data *) + dev->data)->ctx; + + return i2c_rtio_configure(ctx, dev_config_raw); +} + + +static int mcux_lpi2c_do_configure(const struct device *dev, uint32_t dev_config_raw) +{ + const struct mcux_lpi2c_config *config = dev->config; + LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); + uint32_t clock_freq; + uint32_t baudrate; + + if (!(I2C_MODE_CONTROLLER & dev_config_raw)) { + return -EINVAL; + } + + if (I2C_ADDR_10_BITS & dev_config_raw) { + return -EINVAL; + } + + switch (I2C_SPEED_GET(dev_config_raw)) { + case I2C_SPEED_STANDARD: + baudrate = KHZ(100); + break; + case I2C_SPEED_FAST: + baudrate = KHZ(400); + break; + case I2C_SPEED_FAST_PLUS: + baudrate = MHZ(1); + break; + default: + return -EINVAL; + } + + if (clock_control_get_rate(config->clock_dev, config->clock_subsys, + &clock_freq)) { + return -EINVAL; + } + + LPI2C_MasterSetBaudRate(base, clock_freq, baudrate); + + return 0; +} + + +static uint32_t mcux_lpi2c_convert_flags(int msg_flags) +{ + uint32_t flags = 0U; + + if (!(msg_flags & I2C_MSG_STOP)) { + flags |= kLPI2C_TransferNoStopFlag; + } + + if (msg_flags & I2C_MSG_RESTART) { + flags |= kLPI2C_TransferRepeatedStartFlag; + } + + return flags; +} + +static bool mcux_lpi2c_msg_start(const struct device *dev, uint8_t flags, + uint8_t *buf, size_t buf_len, uint16_t i2c_addr) +{ + struct mcux_lpi2c_data *data = dev->data; + struct i2c_rtio *ctx = data->ctx; + LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); + lpi2c_master_transfer_t *transfer = &data->transfer; + status_t status; + + if (I2C_MSG_ADDR_10_BITS & flags) { + return i2c_rtio_complete(ctx, -ENOTSUP); + } + + /* Initialize the transfer descriptor */ + transfer->flags = mcux_lpi2c_convert_flags(flags); + + /* Prevent the controller to send a start condition between + * messages, except if explicitly requested. + */ + if (ctx->txn_curr != ctx->txn_head && !(flags & I2C_MSG_RESTART)) { + transfer->flags |= kLPI2C_TransferNoStartFlag; + } + + transfer->slaveAddress = i2c_addr; + transfer->direction = (flags & I2C_MSG_READ) + ? kLPI2C_Read : kLPI2C_Write; + transfer->subaddress = 0; + transfer->subaddressSize = 0; + transfer->data = buf; + transfer->dataSize = buf_len; + + /* Start the transfer */ + status = LPI2C_MasterTransferNonBlocking(base, + &data->handle, transfer); + + /* Return an error if the transfer didn't start successfully + * e.g., if the bus was busy + */ + if (status != kStatus_Success) { + LPI2C_MasterTransferAbort(base, &data->handle); + return i2c_rtio_complete(ctx, -EIO); + } + + return false; +} + +static void mcux_lpi2c_complete(const struct device *dev, int status); + +static bool mcux_lpi2c_start(const struct device *dev) +{ + struct mcux_lpi2c_data *data = dev->data; + struct i2c_rtio *ctx = data->ctx; + struct rtio_sqe *sqe = &ctx->txn_curr->sqe; + struct i2c_dt_spec *dt_spec = sqe->iodev->data; + + int res = 0; + + switch (sqe->op) { + case RTIO_OP_RX: + return mcux_lpi2c_msg_start(dev, I2C_MSG_READ | sqe->iodev_flags, + sqe->buf, sqe->buf_len, dt_spec->addr); + case RTIO_OP_TINY_TX: + return mcux_lpi2c_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags, + sqe->tiny_buf, sqe->tiny_buf_len, dt_spec->addr); + case RTIO_OP_TX: + return mcux_lpi2c_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags, + sqe->buf, sqe->buf_len, dt_spec->addr); + case RTIO_OP_I2C_CONFIGURE: + res = mcux_lpi2c_do_configure(dev, sqe->i2c_config); + return i2c_rtio_complete(data->ctx, res); + default: + LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe); + return i2c_rtio_complete(data->ctx, -EINVAL); + } +} + +static void mcux_lpi2c_complete(const struct device *dev, status_t status) +{ + const struct mcux_lpi2c_config *config = dev->config; + struct mcux_lpi2c_data *data = dev->data; + LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); + struct i2c_rtio *const ctx = data->ctx; + + int ret = 0; + + /* Return an error if the transfer didn't complete + * successfully. e.g., nak, timeout, lost arbitration + */ + if (status != kStatus_Success) { + LPI2C_MasterTransferAbort(base, &data->handle); + ret = -EIO; + goto out; + } + + if (data->transfer.dataSize == 0) { + k_busy_wait(SCAN_DELAY_US(config->bitrate)); + if (0 != (base->MSR & LPI2C_MSR_NDF_MASK)) { + LPI2C_MasterTransferAbort(base, &data->handle); + ret = -EIO; + goto out; + } + } + +out: + if (i2c_rtio_complete(ctx, ret)) { + mcux_lpi2c_start(dev); + } +} + +static void mcux_lpi2c_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe) +{ + struct mcux_lpi2c_data *data = dev->data; + struct i2c_rtio *const ctx = data->ctx; + + if (i2c_rtio_submit(ctx, iodev_sqe)) { + mcux_lpi2c_start(dev); + } +} + + +static void mcux_lpi2c_master_transfer_callback(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + status_t status, void *userData) +{ + ARG_UNUSED(handle); + ARG_UNUSED(base); + + const struct device *dev = userData; + + mcux_lpi2c_complete(dev, status); +} + +static int mcux_lpi2c_transfer(const struct device *dev, struct i2c_msg *msgs, + uint8_t num_msgs, uint16_t addr) +{ + struct i2c_rtio *const ctx = ((struct mcux_lpi2c_data *) + dev->data)->ctx; + + return i2c_rtio_transfer(ctx, msgs, num_msgs, addr); +} + +static void mcux_lpi2c_isr(const struct device *dev) +{ + struct mcux_lpi2c_data *data = dev->data; + LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); + + LPI2C_MasterTransferHandleIRQ(base, &data->handle); +} + +static int mcux_lpi2c_init(const struct device *dev) +{ + const struct mcux_lpi2c_config *config = dev->config; + struct mcux_lpi2c_data *data = dev->data; + LPI2C_Type *base; + uint32_t clock_freq, bitrate_cfg; + lpi2c_master_config_t master_config; + int error; + + DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); + + base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); + + if (!device_is_ready(config->clock_dev)) { + LOG_ERR("clock control device not ready"); + return -ENODEV; + } + + error = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); + if (error) { + return error; + } + + if (clock_control_get_rate(config->clock_dev, config->clock_subsys, + &clock_freq)) { + return -EINVAL; + } + + LPI2C_MasterGetDefaultConfig(&master_config); + master_config.busIdleTimeout_ns = config->bus_idle_timeout_ns; + LPI2C_MasterInit(base, &master_config, clock_freq); + LPI2C_MasterTransferCreateHandle(base, &data->handle, + mcux_lpi2c_master_transfer_callback, + (void *)dev); + + bitrate_cfg = i2c_map_dt_bitrate(config->bitrate); + + error = mcux_lpi2c_do_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg); + if (error) { + return error; + } + + config->irq_config_func(dev); + + i2c_rtio_init(data->ctx, dev); + + return 0; +} + +static const struct i2c_driver_api mcux_lpi2c_driver_api = { + .configure = mcux_lpi2c_configure, + .transfer = mcux_lpi2c_transfer, + .iodev_submit = mcux_lpi2c_submit, +}; + +#if CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY +#define I2C_MCUX_LPI2C_SCL_INIT(n) .scl = GPIO_DT_SPEC_INST_GET_OR(n, scl_gpios, {0}), +#define I2C_MCUX_LPI2C_SDA_INIT(n) .sda = GPIO_DT_SPEC_INST_GET_OR(n, sda_gpios, {0}), +#else +#define I2C_MCUX_LPI2C_SCL_INIT(n) +#define I2C_MCUX_LPI2C_SDA_INIT(n) +#endif /* CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY */ + +#define I2C_MCUX_LPI2C_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + \ + static void mcux_lpi2c_config_func_##n(const struct device *dev); \ + \ + static const struct mcux_lpi2c_config mcux_lpi2c_config_##n = { \ + DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \ + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clock_subsys = \ + (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\ + .irq_config_func = mcux_lpi2c_config_func_##n, \ + .bitrate = DT_INST_PROP(n, clock_frequency), \ + .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + I2C_MCUX_LPI2C_SCL_INIT(n) \ + I2C_MCUX_LPI2C_SDA_INIT(n) \ + .bus_idle_timeout_ns = \ + UTIL_AND(DT_INST_NODE_HAS_PROP(n, bus_idle_timeout),\ + DT_INST_PROP(n, bus_idle_timeout)), \ + }; \ + \ + I2C_RTIO_DEFINE(_i2c##n##_lpi2c_rtio, \ + DT_INST_PROP_OR(n, sq_size, CONFIG_I2C_RTIO_SQ_SIZE), \ + DT_INST_PROP_OR(n, cq_size, CONFIG_I2C_RTIO_CQ_SIZE)); \ + \ + static struct mcux_lpi2c_data mcux_lpi2c_data_##n = { \ + .ctx = &CONCAT(_i2c, n, _lpi2c_rtio), \ + }; \ + \ + I2C_DEVICE_DT_INST_DEFINE(n, mcux_lpi2c_init, NULL, \ + &mcux_lpi2c_data_##n, \ + &mcux_lpi2c_config_##n, POST_KERNEL, \ + CONFIG_I2C_INIT_PRIORITY, \ + &mcux_lpi2c_driver_api); \ + \ + static void mcux_lpi2c_config_func_##n(const struct device *dev)\ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), \ + DT_INST_IRQ(n, priority), \ + mcux_lpi2c_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + \ + irq_enable(DT_INST_IRQN(n)); \ + } + +DT_INST_FOREACH_STATUS_OKAY(I2C_MCUX_LPI2C_INIT) From ca520f8493408dd9a7b2602174ce9cca2f3d9f00 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Sun, 19 Nov 2023 21:02:12 +0900 Subject: [PATCH 0139/2402] drivers: display: Add LED-Strip matrix display driver Adds a driver for a display of LED strips arranged in a grid. Signed-off-by: TOKITA Hiroshi --- drivers/display/CMakeLists.txt | 1 + drivers/display/Kconfig | 1 + drivers/display/Kconfig.led_strip_matrix | 11 + drivers/display/display_led_strip_matrix.c | 283 ++++++++++++++++++++ dts/bindings/display/led-strip-matrix.yaml | 182 +++++++++++++ tests/drivers/build_all/display/app.overlay | 31 +++ 6 files changed, 509 insertions(+) create mode 100644 drivers/display/Kconfig.led_strip_matrix create mode 100644 drivers/display/display_led_strip_matrix.c create mode 100644 dts/bindings/display/led-strip-matrix.yaml diff --git a/drivers/display/CMakeLists.txt b/drivers/display/CMakeLists.txt index 3b166e73892..0350efdd44b 100644 --- a/drivers/display/CMakeLists.txt +++ b/drivers/display/CMakeLists.txt @@ -24,6 +24,7 @@ zephyr_library_sources_ifdef(CONFIG_RM68200 display_rm68200.c) zephyr_library_sources_ifdef(CONFIG_RM67162 display_rm67162.c) zephyr_library_sources_ifdef(CONFIG_HX8394 display_hx8394.c) zephyr_library_sources_ifdef(CONFIG_GC9X01X display_gc9x01x.c) +zephyr_library_sources_ifdef(CONFIG_LED_STRIP_MATRIX display_led_strip_matrix.c) zephyr_library_sources_ifdef(CONFIG_MICROBIT_DISPLAY mb_display.c diff --git a/drivers/display/Kconfig b/drivers/display/Kconfig index 53b1a6f3917..cb811c7965f 100644 --- a/drivers/display/Kconfig +++ b/drivers/display/Kconfig @@ -41,5 +41,6 @@ source "drivers/display/Kconfig.mcux_dcnano_lcdif" source "drivers/display/Kconfig.otm8009a" source "drivers/display/Kconfig.hx8394" source "drivers/display/Kconfig.gc9x01x" +source "drivers/display/Kconfig.led_strip_matrix" endif # DISPLAY diff --git a/drivers/display/Kconfig.led_strip_matrix b/drivers/display/Kconfig.led_strip_matrix new file mode 100644 index 00000000000..1230a83ce67 --- /dev/null +++ b/drivers/display/Kconfig.led_strip_matrix @@ -0,0 +1,11 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config LED_STRIP_MATRIX + bool "LED strip matrix display driver" + default y + depends on DT_HAS_LED_STRIP_MATRIX_ENABLED + depends on LED_STRIP + help + Enable LED strip matrix display (LED strip arranged in + a grid pattern) driver. diff --git a/drivers/display/display_led_strip_matrix.c b/drivers/display/display_led_strip_matrix.c new file mode 100644 index 00000000000..0f562eeb66c --- /dev/null +++ b/drivers/display/display_led_strip_matrix.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT led_strip_matrix + +#include +#include +#include + +#include +LOG_MODULE_REGISTER(led_strip_matrix, CONFIG_DISPLAY_LOG_LEVEL); + +struct led_strip_buffer { + const struct device *const dev; + const size_t chain_length; + struct led_rgb *pixels; +}; + +struct led_strip_matrix_config { + size_t num_of_strips; + const struct led_strip_buffer *strips; + uint16_t height; + uint16_t width; + uint16_t module_width; + uint16_t module_height; + bool circulative; + bool start_from_right; + bool start_from_bottom; + bool modules_circulative; + bool modules_start_from_right; + bool modules_start_from_bottom; + enum display_pixel_format pixel_format; +}; + +static size_t pixel_index(const struct led_strip_matrix_config *config, uint16_t x, uint16_t y) +{ + const size_t mods_per_row = config->width / config->module_width; + const size_t mod_w = config->module_width; + const size_t mod_h = config->module_height; + const size_t mod_pixels = mod_w * mod_h; + const size_t mod_row = + config->modules_start_from_bottom ? (mod_h - 1) - (y / mod_h) : y / mod_h; + const size_t y_in_mod = config->start_from_bottom ? (mod_h - 1) - (y % mod_h) : y % mod_h; + size_t mod_col = x / mod_w; + size_t x_in_mod = x % mod_w; + + if (config->modules_circulative) { + if (config->modules_start_from_right) { + mod_col = mods_per_row - 1 - mod_col; + } + } else { + if ((mod_row % 2) == !config->modules_start_from_right) { + mod_col = mods_per_row - 1 - mod_col; + } + } + + if (config->circulative) { + if (config->start_from_right) { + x_in_mod = (mod_w - 1) - (x % mod_w); + } + } else { + if ((y_in_mod % 2) == !config->start_from_right) { + x_in_mod = (mod_w - 1) - (x % mod_w); + } + } + + return (mods_per_row * mod_row + mod_col) * mod_pixels + y_in_mod * mod_w + x_in_mod; +} + +static struct led_rgb *pixel_address(const struct led_strip_matrix_config *config, uint16_t x, + uint16_t y) +{ + size_t idx = pixel_index(config, x, y); + + for (size_t i = 0; i < config->num_of_strips; i++) { + if (idx < config->strips[i].chain_length) { + return &config->strips[i].pixels[idx]; + } + idx -= config->strips[i].chain_length; + } + + return NULL; +} + +static inline int check_descriptor(const struct led_strip_matrix_config *config, const uint16_t x, + const uint16_t y, const struct display_buffer_descriptor *desc) +{ + __ASSERT(desc->width <= desc->pitch, "Pitch is smaller then width"); + __ASSERT(desc->pitch <= config->width, "Pitch in descriptor is larger than screen size"); + __ASSERT(desc->height <= config->height, "Height in descriptor is larger than screen size"); + __ASSERT(x + desc->pitch <= config->width, + "Writing outside screen boundaries in horizontal direction"); + __ASSERT(y + desc->height <= config->height, + "Writing outside screen boundaries in vertical direction"); + + if (desc->width > desc->pitch || x + desc->pitch > config->width || + y + desc->height > config->height) { + return -EINVAL; + } + + return 0; +} + +static int led_strip_matrix_write(const struct device *dev, const uint16_t x, const uint16_t y, + const struct display_buffer_descriptor *desc, const void *buf) +{ + const struct led_strip_matrix_config *config = dev->config; + const uint8_t *buf_ptr = buf; + int rc; + + rc = check_descriptor(config, x, y, desc); + if (rc) { + LOG_ERR("Invalid descriptor: %d", rc); + return rc; + } + + for (size_t ypos = y; ypos < (y + desc->height); ypos++) { + for (size_t xpos = x; xpos < (x + desc->width); xpos++) { + struct led_rgb *pix = pixel_address(config, xpos, ypos); + + if (config->pixel_format == PIXEL_FORMAT_ARGB_8888) { + uint32_t color = *((uint32_t *)buf_ptr); + + pix->r = (color >> 16) & 0xFF; + pix->g = (color >> 8) & 0xFF; + pix->b = (color) & 0xFF; + + buf_ptr += 4; + } else { + pix->r = *buf_ptr; + buf_ptr++; + pix->g = *buf_ptr; + buf_ptr++; + pix->b = *buf_ptr; + buf_ptr++; + } + } + buf_ptr += (desc->pitch - desc->width) * + (config->pixel_format == PIXEL_FORMAT_ARGB_8888 ? 4 : 3); + } + + for (size_t i = 0; i < config->num_of_strips; i++) { + rc = led_strip_update_rgb(config->strips[i].dev, config->strips[i].pixels, + config->width * config->height); + if (rc) { + LOG_ERR("couldn't update strip: %d", rc); + } + } + + return rc; +} + +static int led_strip_matrix_read(const struct device *dev, const uint16_t x, const uint16_t y, + const struct display_buffer_descriptor *desc, void *buf) +{ + const struct led_strip_matrix_config *config = dev->config; + uint8_t *buf_ptr = buf; + int rc; + + rc = check_descriptor(config, x, y, desc); + if (rc) { + LOG_ERR("Invalid descriptor: %d", rc); + return rc; + } + + for (size_t ypos = y; ypos < (y + desc->height); ypos++) { + for (size_t xpos = x; xpos < (x + desc->width); xpos++) { + struct led_rgb *pix = pixel_address(config, xpos, ypos); + + if (config->pixel_format == PIXEL_FORMAT_ARGB_8888) { + uint32_t *pix_ptr = (uint32_t *)buf_ptr; + + *pix_ptr = 0xFF000000 | pix->r << 16 | pix->g << 8 | pix->b; + } else { + *buf_ptr = pix->r; + buf_ptr++; + *buf_ptr = pix->g; + buf_ptr++; + *buf_ptr = pix->b; + buf_ptr++; + } + } + buf_ptr += (desc->pitch - desc->width) * + (config->pixel_format == PIXEL_FORMAT_ARGB_8888 ? 4 : 3); + } + + return 0; +} + +static void led_strip_matrix_get_capabilities(const struct device *dev, + struct display_capabilities *caps) +{ + const struct led_strip_matrix_config *config = dev->config; + + memset(caps, 0, sizeof(struct display_capabilities)); + caps->x_resolution = config->width; + caps->y_resolution = config->height; + caps->supported_pixel_formats = PIXEL_FORMAT_ARGB_8888 | PIXEL_FORMAT_RGB_888; + caps->current_pixel_format = config->pixel_format; + caps->screen_info = 0; +} + +static const struct display_driver_api led_strip_matrix_api = { + .write = led_strip_matrix_write, + .read = led_strip_matrix_read, + .get_capabilities = led_strip_matrix_get_capabilities, +}; + +static int led_strip_matrix_init(const struct device *dev) +{ + const struct led_strip_matrix_config *config = dev->config; + + for (size_t i = 0; i < config->num_of_strips; i++) { + if (!device_is_ready(config->strips[i].dev)) { + LOG_ERR("LED strip device %s is not ready", config->strips[i].dev->name); + return -EINVAL; + } + } + + return 0; +} + +#define CHAIN_LENGTH(idx, inst) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, chain_lengths), \ + (DT_INST_PROP_BY_IDX(inst, chain_lengths, idx)), \ + (DT_INST_PROP_BY_PHANDLE_IDX(inst, led_strips, idx, chain_length))) + +#define STRIP_BUFFER_INITIALIZER(idx, inst) \ + { \ + .dev = DEVICE_DT_GET(DT_INST_PROP_BY_IDX(inst, led_strips, idx)), \ + .chain_length = CHAIN_LENGTH(idx, inst), \ + .pixels = pixels##inst##_##idx, \ + } + +#define DECLARE_PIXELS(idx, inst) \ + static struct led_rgb pixels##inst##_##idx[CHAIN_LENGTH(idx, inst)]; + +#define AMOUNT_OF_LEDS(inst) LISTIFY(DT_INST_PROP_LEN(inst, led_strips), CHAIN_LENGTH, (+), inst) + +#define VALIDATE_CHAIN_LENGTH(idx, inst) \ + BUILD_ASSERT( \ + CHAIN_LENGTH(idx, inst) % \ + (DT_INST_PROP(inst, width) / DT_INST_PROP(inst, horizontal_modules) * \ + (DT_INST_PROP(inst, height) / DT_INST_PROP(inst, vertical_modules))) == \ + 0); + +#define LED_STRIP_MATRIX_DEFINE(inst) \ + LISTIFY(DT_INST_PROP_LEN(inst, led_strips), DECLARE_PIXELS, (;), inst); \ + static const struct led_strip_buffer strip_buffer##inst[] = { \ + LISTIFY(DT_INST_PROP_LEN(inst, led_strips), STRIP_BUFFER_INITIALIZER, (,), inst), \ + }; \ + static const struct led_strip_matrix_config dd_config_##inst = { \ + .num_of_strips = DT_INST_PROP_LEN(inst, led_strips), \ + .strips = strip_buffer##inst, \ + .width = DT_INST_PROP(inst, width), \ + .height = DT_INST_PROP(inst, height), \ + .module_width = \ + DT_INST_PROP(inst, width) / DT_INST_PROP(inst, horizontal_modules), \ + .module_height = \ + DT_INST_PROP(inst, height) / DT_INST_PROP(inst, vertical_modules), \ + .circulative = DT_INST_PROP(inst, circulative), \ + .start_from_right = DT_INST_PROP(inst, start_from_right), \ + .modules_circulative = DT_INST_PROP(inst, modules_circulative), \ + .modules_start_from_right = DT_INST_PROP(inst, modules_start_from_right), \ + .pixel_format = DT_INST_PROP(inst, pixel_format), \ + }; \ + \ + BUILD_ASSERT((DT_INST_PROP(inst, pixel_format) == PIXEL_FORMAT_RGB_888) || \ + (DT_INST_PROP(inst, pixel_format) == PIXEL_FORMAT_ARGB_8888)); \ + BUILD_ASSERT((DT_INST_PROP(inst, width) * DT_INST_PROP(inst, height)) == \ + AMOUNT_OF_LEDS(inst)); \ + BUILD_ASSERT((DT_INST_PROP(inst, width) % DT_INST_PROP(inst, horizontal_modules)) == 0); \ + BUILD_ASSERT((DT_INST_PROP(inst, height) % DT_INST_PROP(inst, vertical_modules)) == 0); \ + LISTIFY(DT_INST_PROP_LEN(inst, led_strips), VALIDATE_CHAIN_LENGTH, (;), inst); \ + \ + DEVICE_DT_INST_DEFINE(inst, led_strip_matrix_init, NULL, NULL, &dd_config_##inst, \ + POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, \ + &led_strip_matrix_api); + +DT_INST_FOREACH_STATUS_OKAY(LED_STRIP_MATRIX_DEFINE) diff --git a/dts/bindings/display/led-strip-matrix.yaml b/dts/bindings/display/led-strip-matrix.yaml new file mode 100644 index 00000000000..f46cee2f0c4 --- /dev/null +++ b/dts/bindings/display/led-strip-matrix.yaml @@ -0,0 +1,182 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +description: | + Generic LED strip matrix (LED strip arranged in a grid pattern) + +compatible: "led-strip-matrix" + +include: display-controller.yaml + +properties: + circulative: + type: boolean + description: | + Use a circulative layout that returns to the left edge of the next row + after reaching the right edge. + If not set, turn around and go left in a serpentine layout when it reaches + the right edge. + + * circulative layout + [ 0][ 1][ 2][ 3] + [ 4][ 5][ 6][ 7] + [ 8][ 9][10][11] + [12][13][14][15] + + * serpentine layout + [ 0][ 1][ 2][ 3] + [ 7][ 6][ 5][ 4] + [ 8][ 9][10][11] + [15][14][13][12] + + start-from-right: + type: boolean + description: | + Specify if the first LED is at the right. + + * Start from the right with a serpentine layout + [ 3][ 2][ 1][ 0] + [ 4][ 5][ 6][ 7] + [11][10][ 9][ 8] + [12][13][14][15] + + * Start from the right with a circulative layout + [ 3][ 2][ 1][ 0] + [ 7][ 6][ 5][ 4] + [11][10][ 9][ 8] + [15][14][13][12] + + start-from-bottom: + type: boolean + description: | + Specify if the first LED is at the bottom. + + * Start from the bottom with a circulative layout + [12][13][14][15] + [ 8][ 9][10][11] + [ 4][ 5][ 6][ 7] + [ 0][ 1][ 2][ 3] + + * Start from the bottom with a serpentine layout + [15][14][13][12] + [ 8][ 9][10][11] + [ 7][ 6][ 5][ 4] + [ 0][ 1][ 2][ 3] + + width: + description: | + Specifies the overall width of the matrix. + If the matrix consists of multiple modules, it is the sum of their widths. + + height: + description: | + Specifies the overall height of the matrix. + If the matrix consists of multiple modules, it is the sum of their heights. + + horizontal-modules: + type: int + default: 1 + description: | + If the display forms with multiple modules, + specify the horizontal number of modules. + The number must be able to divide the width value. + If not set, it controls a single matrix. + + * 8x4 display with 2 serpentine layout modules + [ 0][ 1][ 2][ 3] [16][17][18][19] + [ 7][ 6][ 5][ 4] [23][22][21][20] + [ 8][ 9][10][11] [24][25][26][27] + [15][14][13][12] [31][30][29][28] + + vertical-modules: + type: int + default: 1 + description: | + If the display forms with multiple modules, + specify the vertical number of modules. + The number must be able to divide the height value. + If not set, it controls a single matrix. + + * 4x8 display with 2 serpentine layout modules + [ 0][ 1][ 2][ 3] + [ 7][ 6][ 5][ 4] + [ 8][ 9][10][11] + [15][14][13][12] + + [16][17][18][19] + [23][22][21][20] + [24][25][26][27] + [31][30][29][28] + + modules-circulative: + type: boolean + description: | + Specifies that the order of the modules that make up the matrix is circulative. + + * circulative module layout + [M0][M1][M2] + [M3][M4][M5] + [M6][M7][M8] + + * serpentine module layout + [M0][M1][M2] + [M5][M4][M3] + [M6][M7][M8] + + modules-start-from-right: + type: boolean + description: | + Specifies that modules are ordered from right to left. + + * Start from the right with a module serpentine layout + [M2][M1][M0] + [M3][M4][M5] + [M8][M7][M6] + + * Start from the right with a module circulative layout + [M2][M1][M0] + [M5][M4][M3] + [M8][M7][M6] + + modules-start-from-bottom: + type: boolean + description: | + Specifies that modules are ordered from bottom to top. + + * Start from the right with a module serpentine layout + [M6][M7][M8] + [M5][M4][M3] + [M0][M1][M2] + + * Start from the right with a module circulative layout + [M6][M7][M8] + [M3][M4][M5] + [M0][M1][M2] + + led-strips: + type: phandles + required: true + description: | + Specify the LED strip that is the substance of the matrix. + If multiple strips are specified, they are "flattened" and sequentialized. + For example, if `strip0` and `strip1` with 128 LEDs are specified, + the first LED of `strip1` will be treated as the 129th LED. + These LEDs are mapped to coordinates according to the layout rule in order. + The amount of LEDs must equal the [width * height] value. + + chain-lengths: + type: array + description: | + Specify the number of LEDs for each strip. + It can omit the value if all strip nodes have a `chain-length` property. + Each value must be a multiple of the number of LEDs per module + [(width / horizontal-modules) * (height / vertical-modules)]. + + pixel-format: + type: int + default: 1 + description: | + Initial Pixel format. + See dt-bindings/display/panel.h for a list. + This property only accepts PANEL_PIXEL_FORMAT_RGB_888 and PANEL_PIXEL_FORMAT_RRGB_8888. + If this property is not set, use PANEL_PIXEL_FORMAT_RGB_888 as a default. diff --git a/tests/drivers/build_all/display/app.overlay b/tests/drivers/build_all/display/app.overlay index 61a821dd1ad..f287255274e 100644 --- a/tests/drivers/build_all/display/app.overlay +++ b/tests/drivers/build_all/display/app.overlay @@ -65,6 +65,37 @@ width = <240>; height = <240>; }; + + test_led_strip_0: lpd8806@2 { + compatible = "greeled,lpd8806"; + reg = <2>; + spi-max-frequency = <2000000>; + }; + + test_led_strip_1: ws2812_spi@3 { + compatible = "worldsemi,ws2812-spi"; + reg = <3>; + spi-max-frequency = <2000000>; + spi-one-frame = <1>; + spi-zero-frame = <1>; + chain-length = <256>; + color-mapping = <0 1 2>; + reset-delay = <280>; + }; + }; + + test_led_strip_matrix { + compatible = "led-strip-matrix"; + status = "okay"; + + led-strips = <&test_led_strip_0>, <&test_led_strip_1>; + chain-lengths = <256>, <256>; + width = <32>; + height = <16>; + horizontal-modules = <2>; + vertical-modules = <1>; + circulative; + start-from-right; }; }; }; From 32f4c173741a56ad7fe8a6ec43f54a25e6921025 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Tue, 6 Feb 2024 14:18:56 +0000 Subject: [PATCH 0140/2402] scripts: tests: Blackbox test expansion - output Adds tests related to the flags that change the console outputs: * --detailed-test-ids * --no-detailed-test-ids * -i, --inline-logs Signed-off-by: Lukasz Mrugala --- scripts/tests/twister_blackbox/test_output.py | 125 ++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_output.py diff --git a/scripts/tests/twister_blackbox/test_output.py b/scripts/tests/twister_blackbox/test_output.py new file mode 100644 index 00000000000..e01e69ce06c --- /dev/null +++ b/scripts/tests/twister_blackbox/test_output.py @@ -0,0 +1,125 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions changing test output. +""" + +import importlib +import re +import mock +import os +import pytest +import sys +import json + +from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock, clear_log_in_test +from twisterlib.testplan import TestPlan + + +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +class TestOutput: + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @pytest.mark.parametrize( + 'flag, expect_paths', + [ + ('--no-detailed-test-id', False), + ('--detailed-test-id', True) + ], + ids=['no-detailed-test-id', 'detailed-test-id'] + ) + def test_detailed_test_id(self, out_path, flag, expect_paths): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + [flag] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert len(filtered_j) > 0, "No dummy tests found." + + expected_start = os.path.relpath(TEST_DATA, ZEPHYR_BASE) if expect_paths else 'dummy.' + assert all([testsuite.startswith(expected_start)for _, testsuite, _ in filtered_j]) + + def test_inline_logs(self, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'always_build_error', 'dummy') + args = ['--outdir', out_path, '-T', path] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '1' + + rel_path = os.path.relpath(path, ZEPHYR_BASE) + build_path = os.path.join(out_path, 'qemu_x86', rel_path, 'always_fail.dummy', 'build.log') + with open(build_path) as f: + build_log = f.read() + + clear_log_in_test() + + args = ['--outdir', out_path, '-T', path] + \ + ['--inline-logs'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '1' + + with open(os.path.join(out_path, 'twister.log')) as f: + inline_twister_log = f.read() + + # Remove information that differs between the runs + removal_patterns = [ + # Remove tmp filepaths, as they will differ + r'(/|\\)tmp(/|\\)\S+', + # Remove object creation order, as it can change + r'^\[[0-9]+/[0-9]+\] ', + # Remove variable CMake flag + r'-DTC_RUNID=[0-9a-zA-Z]+', + # Remove variable order CMake flags + r'-I[0-9a-zA-Z/\\]+', + # Cache location may vary between CI runs + r'^.*-- Cache files will be written to:.*$' + ] + for pattern in removal_patterns: + inline_twister_log = re.sub(pattern, '', inline_twister_log, flags=re.MULTILINE) + build_log = re.sub(pattern, '', build_log, flags=re.MULTILINE) + + split_build_log = build_log.split('\n') + for r in split_build_log: + assert r in inline_twister_log From 600c4d8a451d3087cbae1e355e9215a075726b56 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Tue, 6 Feb 2024 15:10:45 +0000 Subject: [PATCH 0141/2402] scripts: tests: Blackbox test expansion - filter Adds tests related to the flags that filter the tests: * -e, --exclude-tag * -S, --enable-slow * --enable-slow-only Signed-off-by: Lukasz Mrugala --- scripts/tests/twister_blackbox/test_filter.py | 124 ++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_filter.py diff --git a/scripts/tests/twister_blackbox/test_filter.py b/scripts/tests/twister_blackbox/test_filter.py new file mode 100644 index 00000000000..d393a035664 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_filter.py @@ -0,0 +1,124 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions related to test filtering. +""" + +import importlib +import mock +import os +import pytest +import sys +import json + +from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +class TestFilter: + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @pytest.mark.parametrize( + 'tag, expected_test_count', + [ + ('device', 5), # dummy.agnostic.group1.subgroup1.assert + # dummy.agnostic.group1.subgroup2.assert + # dummy.agnostic.group2.assert1 + # dummy.agnostic.group2.assert2 + # dummy.agnostic.group2.assert3 + ('agnostic', 1) # dummy.device.group.assert + ], + ids=['no device', 'no agnostic'] + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_exclude_tag(self, out_path, tag, expected_test_count): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + ['--exclude-tag', tag] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert len(filtered_j) == expected_test_count + + assert str(sys_exit.value) == '0' + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_enable_slow(self, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic') + alt_config_root = os.path.join(TEST_DATA, 'alt-test-configs', 'dummy', 'agnostic') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--enable-slow'] + \ + ['--alt-config-root', alt_config_root] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert str(sys_exit.value) == '0' + + assert len(filtered_j) == 5 + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_enable_slow_only(self, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic') + alt_config_root = os.path.join(TEST_DATA, 'alt-test-configs', 'dummy', 'agnostic') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--enable-slow-only'] + \ + ['--alt-config-root', alt_config_root] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert str(sys_exit.value) == '0' + + assert len(filtered_j) == 3 From 93a377e67492ee0c41a7039e13f771c0f5db518e Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Tue, 6 Feb 2024 14:44:26 +0000 Subject: [PATCH 0142/2402] scripts: tests: Blackbox test expansion - outfile Adds tests related to the changing of the output files: * -c, --clobber-output * -n, --no-clean * -M, --runtime-artifact-cleanup * --short-build-path * --prep-artifacts-for-testing Signed-off-by: Lukasz Mrugala --- scripts/tests/twister_blackbox/conftest.py | 1 + .../samples/hello_world/CMakeLists.txt | 8 + .../test_data/samples/hello_world/prj.conf | 1 + .../test_data/samples/hello_world/src/main.c | 13 ++ .../samples/hello_world/test_sample.yaml | 16 ++ .../tests/twister_blackbox/test_outfile.py | 201 ++++++++++++++++++ 6 files changed, 240 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_data/samples/hello_world/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/samples/hello_world/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/samples/hello_world/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/samples/hello_world/test_sample.yaml create mode 100644 scripts/tests/twister_blackbox/test_outfile.py diff --git a/scripts/tests/twister_blackbox/conftest.py b/scripts/tests/twister_blackbox/conftest.py index 517af1a79b7..b0b41219f8a 100644 --- a/scripts/tests/twister_blackbox/conftest.py +++ b/scripts/tests/twister_blackbox/conftest.py @@ -22,6 +22,7 @@ testsuite_filename_mock = mock.PropertyMock(return_value='test_data.yaml') +sample_filename_mock = mock.PropertyMock(return_value='test_sample.yaml') def pytest_configure(config): config.addinivalue_line("markers", "noclearlog: disable the clear_log autouse fixture") diff --git a/scripts/tests/twister_blackbox/test_data/samples/hello_world/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/samples/hello_world/CMakeLists.txt new file mode 100644 index 00000000000..ecb7d24bb8f --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/samples/hello_world/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(hello_world) + +target_sources(app PRIVATE src/main.c) diff --git a/scripts/tests/twister_blackbox/test_data/samples/hello_world/prj.conf b/scripts/tests/twister_blackbox/test_data/samples/hello_world/prj.conf new file mode 100644 index 00000000000..b2a4ba59104 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/samples/hello_world/prj.conf @@ -0,0 +1 @@ +# nothing here diff --git a/scripts/tests/twister_blackbox/test_data/samples/hello_world/src/main.c b/scripts/tests/twister_blackbox/test_data/samples/hello_world/src/main.c new file mode 100644 index 00000000000..2758d75d3fc --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/samples/hello_world/src/main.c @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2012-2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +int main(void) +{ + printf("Hello World! %s\n", CONFIG_BOARD); + return 0; +} diff --git a/scripts/tests/twister_blackbox/test_data/samples/hello_world/test_sample.yaml b/scripts/tests/twister_blackbox/test_data/samples/hello_world/test_sample.yaml new file mode 100644 index 00000000000..1bcb7db62f2 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/samples/hello_world/test_sample.yaml @@ -0,0 +1,16 @@ +sample: + description: Hello World sample, the simplest Zephyr + application + name: hello world +common: + tags: introduction + integration_platforms: + - native_sim + harness: console + harness_config: + type: one_line + regex: + - "Hello World! (.*)" +tests: + sample.basic.helloworld: + tags: introduction diff --git a/scripts/tests/twister_blackbox/test_outfile.py b/scripts/tests/twister_blackbox/test_outfile.py new file mode 100644 index 00000000000..5e019d672fc --- /dev/null +++ b/scripts/tests/twister_blackbox/test_outfile.py @@ -0,0 +1,201 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions changing the output files. +""" + +import importlib +import re +import mock +import os +import shutil +import pytest +import sys + +from conftest import ZEPHYR_BASE, TEST_DATA, sample_filename_mock, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +@mock.patch.object(TestPlan, 'SAMPLE_FILENAME', sample_filename_mock) +class TestOutfile: + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @pytest.mark.parametrize( + 'flag_section, clobber, expect_straggler', + [ + ([], True, False), + (['--clobber-output'], False, False), + (['--no-clean'], False, True), + (['--clobber-output', '--no-clean'], False, True), + ], + ids=['clobber', 'do not clobber', 'do not clean', 'do not clobber, do not clean'] + ) + def test_clobber_output(self, out_path, flag_section, clobber, expect_straggler): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + flag_section + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + # We create an empty 'blackbox-out' to trigger the clobbering + os.mkdir(os.path.join(out_path)) + # We want to have a single straggler to check for + straggler_name = 'atavi.sm' + straggler_path = os.path.join(out_path, straggler_name) + open(straggler_path, 'a').close() + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + expected_dirs = ['blackbox-out'] + if clobber: + expected_dirs += ['blackbox-out.1'] + current_dirs = os.listdir(os.path.normpath(os.path.join(out_path, '..'))) + print(current_dirs) + assert sorted(current_dirs) == sorted(expected_dirs) + + out_contents = os.listdir(os.path.join(out_path)) + print(out_contents) + if expect_straggler: + assert straggler_name in out_contents + else: + assert straggler_name not in out_contents + + def test_runtime_artifact_cleanup(self, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'samples', 'hello_world') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--runtime-artifact-cleanup'] + \ + [] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + relpath = os.path.relpath(path, ZEPHYR_BASE) + sample_path = os.path.join(out_path, 'qemu_x86', relpath, 'sample.basic.helloworld') + listdir = os.listdir(sample_path) + zephyr_listdir = os.listdir(os.path.join(sample_path, 'zephyr')) + + expected_contents = ['CMakeFiles', 'handler.log', 'build.ninja', 'CMakeCache.txt', + 'zephyr', 'build.log'] + expected_zephyr_contents = ['.config'] + + assert all([content in expected_zephyr_contents for content in zephyr_listdir]), \ + 'Cleaned zephyr directory has unexpected files.' + assert all([content in expected_contents for content in listdir]), \ + 'Cleaned directory has unexpected files.' + + def test_short_build_path(self, out_path): + test_platforms = ['qemu_x86'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2') + # twister_links dir does not exist in a dry run. + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--short-build-path'] + \ + ['--ninja'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + relative_test_path = os.path.relpath(path, ZEPHYR_BASE) + test_result_path = os.path.join(out_path, 'qemu_x86', + relative_test_path, 'dummy.agnostic.group2') + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + with open(os.path.join(out_path, 'twister.log')) as f: + twister_log = f.read() + + pattern_running = r'Running\s+cmake\s+on\s+(?P[\\\/].*)\s+for\s+qemu_x86\s*\n' + res_running = re.search(pattern_running, twister_log) + assert res_running + + # Spaces, forward slashes, etc. in the path as well as CMake peculiarities + # require us to forgo simple RegExes. + pattern_calling_line = r'Calling cmake: [^\n]+$' + res_calling = re.search(pattern_calling_line, twister_log[res_running.end():], re.MULTILINE) + calling_line = res_calling.group() + + # HIGHLY DANGEROUS pattern! + # If the checked text is not CMake flags only, it is exponential! + # Where N is the length of non-flag space-delimited text section. + flag_pattern = r'(?:\S+(?: \\)?)+- ' + cmake_path = shutil.which('cmake') + if not cmake_path: + assert False, 'Cmake not found.' + + cmake_call_section = r'^Calling cmake: ' + re.escape(cmake_path) + calling_line = re.sub(cmake_call_section, '', calling_line) + calling_line = calling_line[::-1] + flag_iterable = re.finditer(flag_pattern, calling_line) + + for match in flag_iterable: + reversed_flag = match.group() + flag = reversed_flag[::-1] + + # Build flag + if flag.startswith(' -B'): + flag_value = flag[3:] + build_filename = os.path.basename(os.path.normpath(flag_value)) + unshortened_build_path = os.path.join(test_result_path, build_filename) + assert flag_value != unshortened_build_path, 'Build path unchanged.' + assert len(flag_value) < len(unshortened_build_path), 'Build path not shortened.' + + # Pipe flag + if flag.startswith(' -DQEMU_PIPE='): + flag_value = flag[13:] + pipe_filename = os.path.basename(os.path.normpath(flag_value)) + unshortened_pipe_path = os.path.join(test_result_path, pipe_filename) + assert flag_value != unshortened_pipe_path, 'Pipe path unchanged.' + assert len(flag_value) < len(unshortened_pipe_path), 'Pipe path not shortened.' + + def test_prep_artifacts_for_testing(self, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'samples', 'hello_world') + relative_test_path = os.path.relpath(path, ZEPHYR_BASE) + zephyr_out_path = os.path.join(out_path, 'qemu_x86', relative_test_path, + 'sample.basic.helloworld', 'zephyr') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--prep-artifacts-for-testing'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + zephyr_artifact_list = os.listdir(zephyr_out_path) + + # --build-only and normal run leave more files than --prep-artifacts-for-testing + # However, the cost of testing that this leaves less seems to outweigh the benefits. + # So we'll only check for the most important artifact. + assert 'zephyr.elf' in zephyr_artifact_list From c0d6e9f29b9c0eee485561faf3a45c5348c3037c Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Tue, 6 Feb 2024 12:16:30 +0000 Subject: [PATCH 0143/2402] scripts: tests: Blackbox test expansion - printouts Adds tests related to the flags creating alternate printouts instead of running Twister tests: * -z, --size Signed-off-by: Lukasz Mrugala --- .../tests/twister_blackbox/test_printouts.py | 51 ++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/scripts/tests/twister_blackbox/test_printouts.py b/scripts/tests/twister_blackbox/test_printouts.py index a548137595b..67e97e84f72 100644 --- a/scripts/tests/twister_blackbox/test_printouts.py +++ b/scripts/tests/twister_blackbox/test_printouts.py @@ -13,7 +13,13 @@ import sys import re -from conftest import TEST_DATA, ZEPHYR_BASE, testsuite_filename_mock +from conftest import ( + TEST_DATA, + ZEPHYR_BASE, + clear_log_in_test, + sample_filename_mock, + testsuite_filename_mock +) from twisterlib.testplan import TestPlan @@ -262,3 +268,46 @@ def test_force_color(self, capfd, out_path, test_path, test_platforms): sys.stderr.write(err) assert str(sys_exit.value) == '0' + + @mock.patch.object(TestPlan, 'SAMPLE_FILENAME', sample_filename_mock) + def test_size(self, capfd, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'samples', 'hello_world') + args = ['-i', '--outdir', out_path, '-T', path] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + clear_log_in_test() + capfd.readouterr() + + p = os.path.relpath(path, ZEPHYR_BASE) + prev_path = os.path.join(out_path, 'qemu_x86', p, + 'sample.basic.helloworld', 'zephyr', 'zephyr.elf') + args = ['--size', prev_path] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + # Header and footer should be the most constant out of the report format. + header_pattern = r'SECTION NAME\s+VMA\s+LMA\s+SIZE\s+HEX SZ\s+TYPE\s*\n' + res = re.search(header_pattern, out) + assert res, 'No stdout size report header found.' + + footer_pattern = r'Totals:\s+(?P[0-9]+)\s+bytes\s+\(ROM\),\s+' \ + r'(?P[0-9]+)\s+bytes\s+\(RAM\)\s*\n' + res = re.search(footer_pattern, out) + assert res, 'No stdout size report footer found.' From 6ae873d4c245d91baaab68ebc92798dc6eb73067 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Mon, 5 Feb 2024 15:16:39 +0000 Subject: [PATCH 0144/2402] scripts: tests: Blackbox test expansion - quarantine Adds tests related to the quarantine flags: * --quarantine-verify Signed-off-by: Lukasz Mrugala --- .../tests/twister_blackbox/test_quarantine.py | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_quarantine.py diff --git a/scripts/tests/twister_blackbox/test_quarantine.py b/scripts/tests/twister_blackbox/test_quarantine.py new file mode 100644 index 00000000000..e6380f287d1 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_quarantine.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions related to the quarantine. +""" + +import importlib +import mock +import os +import pytest +import sys +import json + +from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +class TestQuarantine: + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_quarantine_verify(self, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + quarantine_path = os.path.join(TEST_DATA, 'twister-quarantine-list.yml') + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + ['--quarantine-verify'] + \ + ['--quarantine-list', quarantine_path] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert str(sys_exit.value) == '0' + + assert len(filtered_j) == 2 From 8b1ef285cb54fe969c353c971068e2386e8490f7 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Mon, 5 Feb 2024 15:32:52 +0000 Subject: [PATCH 0145/2402] scripts: tests: Move --quarantine-list test to test_quarantine.py Brings the previously-created --quarantine-list test to its test section file. Signed-off-by: Lukasz Mrugala --- .../tests/twister_blackbox/test_quarantine.py | 63 ++++++++++++++++ scripts/tests/twister_blackbox/test_runner.py | 71 ++----------------- 2 files changed, 68 insertions(+), 66 deletions(-) diff --git a/scripts/tests/twister_blackbox/test_quarantine.py b/scripts/tests/twister_blackbox/test_quarantine.py index e6380f287d1..6d25451c72c 100644 --- a/scripts/tests/twister_blackbox/test_quarantine.py +++ b/scripts/tests/twister_blackbox/test_quarantine.py @@ -10,6 +10,7 @@ import mock import os import pytest +import re import sys import json @@ -56,3 +57,65 @@ def test_quarantine_verify(self, out_path): assert str(sys_exit.value) == '0' assert len(filtered_j) == 2 + + @pytest.mark.parametrize( + 'test_path, test_platforms, quarantine_directory', + [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), + ['qemu_x86', 'qemu_x86_64', 'frdm_k64f'], + os.path.join(TEST_DATA, 'twister-quarantine-list.yml'), + ), + ], + ids=[ + 'quarantine', + ], + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_quarantine_list(self, capfd, out_path, test_path, test_platforms, quarantine_directory): + args = ['--outdir', out_path, '-T', test_path] +\ + ['--quarantine-list', quarantine_directory] + \ + ['-vv'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + frdm_match = re.search('agnostic/group2/dummy.agnostic.group2 SKIPPED: Quarantine: test ' + 'frdm_k64f', err) + frdm_match2 = re.search( + 'agnostic/group1/subgroup2/dummy.agnostic.group1.subgroup2 SKIPPED: Quarantine: test ' + 'frdm_k64f', + err) + qemu_64_match = re.search( + 'agnostic/group1/subgroup2/dummy.agnostic.group1.subgroup2 SKIPPED: Quarantine: test ' + 'qemu_x86_64', + err) + all_platforms_match = re.search( + 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantine: test ' + 'all platforms', + err) + all_platforms_match2 = re.search( + 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantine: test ' + 'all platforms', + err) + all_platforms_match3 = re.search( + 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantine: test ' + 'all platforms', + err) + + assert frdm_match and frdm_match2, 'platform quarantine not work properly' + assert qemu_64_match, 'platform quarantine on scenario not work properly' + assert all_platforms_match and all_platforms_match2 and all_platforms_match3, 'scenario ' \ + 'quarantine' \ + ' not work ' \ + 'properly' + + assert str(sys_exit.value) == '0' diff --git a/scripts/tests/twister_blackbox/test_runner.py b/scripts/tests/twister_blackbox/test_runner.py index eea5e706394..acfaf540b8f 100644 --- a/scripts/tests/twister_blackbox/test_runner.py +++ b/scripts/tests/twister_blackbox/test_runner.py @@ -173,13 +173,6 @@ class TestRunner: ), ] TESTDATA_11 = [ - ( - os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64', 'frdm_k64f'], - os.path.join(TEST_DATA, 'twister-quarantine-list.yml'), - ), - ] - TESTDATA_12 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy'), ['qemu_x86'], @@ -205,7 +198,7 @@ class TestRunner: [r'3 of 4 test configurations passed \(100.00%\), 0 failed, 0 errored, 1 skipped'] ), ] - TESTDATA_13 = [ + TESTDATA_12 = [ ( os.path.join(TEST_DATA, 'tests', 'one_fail_one_pass'), ['qemu_x86'], @@ -218,8 +211,7 @@ class TestRunner: } ) ] - - TESTDATA_14 = [ + TESTDATA_13 = [ ( os.path.join(TEST_DATA, 'tests', 'always_build_error'), ['qemu_x86_64'], @@ -803,62 +795,9 @@ def test_timeout_multiplier(self, capfd, out_path, test_path, test_platforms, ti assert str(sys_exit.value) == '1' - @pytest.mark.parametrize( - 'test_path, test_platforms, quarantine_directory', - TESTDATA_11, - ids=[ - 'quarantine', - ], - ) - def test_quarantine_list(self, capfd, out_path, test_path, test_platforms, quarantine_directory): - args = ['--outdir', out_path, '-T', test_path, '--quarantine-list', quarantine_directory, '-vv'] + \ - [val for pair in zip( - ['-p'] * len(test_platforms), test_platforms - ) for val in pair] - - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) - - out, err = capfd.readouterr() - sys.stdout.write(out) - sys.stderr.write(err) - - frdm_match = re.search('agnostic/group2/dummy.agnostic.group2 SKIPPED: Quarantine: test ' - 'frdm_k64f', err) - frdm_match2 = re.search( - 'agnostic/group1/subgroup2/dummy.agnostic.group1.subgroup2 SKIPPED: Quarantine: test ' - 'frdm_k64f', - err) - qemu_64_match = re.search( - 'agnostic/group1/subgroup2/dummy.agnostic.group1.subgroup2 SKIPPED: Quarantine: test ' - 'qemu_x86_64', - err) - all_platforms_match = re.search( - 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantine: test ' - 'all platforms', - err) - all_platforms_match2 = re.search( - 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantine: test ' - 'all platforms', - err) - all_platforms_match3 = re.search( - 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantine: test ' - 'all platforms', - err) - - assert frdm_match and frdm_match2, 'platform quarantine not work properly' - assert qemu_64_match, 'platform quarantine on scenario not work properly' - assert all_platforms_match and all_platforms_match2 and all_platforms_match3, 'scenario ' \ - 'quarantine' \ - ' not work ' \ - 'properly' - - assert str(sys_exit.value) == '0' - @pytest.mark.parametrize( 'test_path, test_platforms, tags, expected', - TESTDATA_12, + TESTDATA_11, ids=[ 'tags device', 'tags subgruped', @@ -890,7 +829,7 @@ def test_tag(self, capfd, out_path, test_path, test_platforms, tags, expected): @pytest.mark.parametrize( 'test_path, test_platforms, expected', - TESTDATA_13, + TESTDATA_12, ids=[ 'only_failed' ], @@ -953,7 +892,7 @@ def test_only_failed(self, capfd, out_path, test_path, test_platforms, expected) @pytest.mark.parametrize( 'test_path, test_platforms, iterations', - TESTDATA_14, + TESTDATA_13, ids=[ 'retry 2', 'retry 3' From dc68b11432def8d48ca3a61b81efb3bfa710d9e8 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Fri, 19 Jan 2024 13:59:19 +0000 Subject: [PATCH 0146/2402] scripts: tests: Blackbox test expansion - testlist Adds tests related to the flags creating testlists: * -E, --save-tests * -F, --load-tests Signed-off-by: Lukasz Mrugala --- .../tests/twister_blackbox/test_testlist.py | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_testlist.py diff --git a/scripts/tests/twister_blackbox/test_testlist.py b/scripts/tests/twister_blackbox/test_testlist.py new file mode 100644 index 00000000000..abbf1012781 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_testlist.py @@ -0,0 +1,74 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions related to saving and loading a testlist. +""" + +import importlib +import mock +import os +import pytest +import sys +import json + +from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock, clear_log_in_test +from twisterlib.testplan import TestPlan + + +class TestTestlist: + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_save_tests(self, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic') + saved_tests_file_path = os.path.realpath(os.path.join(out_path, '..', 'saved-tests.json')) + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + ['--save-tests', saved_tests_file_path] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + # Save agnostics tests + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + clear_log_in_test() + + # Load all + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + ['--load-tests', saved_tests_file_path] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert len(filtered_j) == 5 From 621b6210074ffe4d73a2cec98a5dcfbc137a69b8 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Wed, 14 Feb 2024 12:57:02 +0000 Subject: [PATCH 0147/2402] script: tests: Blackbox test expansion - report Adds tests related to report flags: * --enable-size-report * --detailed-skipped-report Signed-off-by: Lukasz Mrugala --- scripts/tests/twister_blackbox/test_report.py | 74 ++++++++++++++++++- 1 file changed, 70 insertions(+), 4 deletions(-) diff --git a/scripts/tests/twister_blackbox/test_report.py b/scripts/tests/twister_blackbox/test_report.py index 5d120be727e..259579afc5c 100644 --- a/scripts/tests/twister_blackbox/test_report.py +++ b/scripts/tests/twister_blackbox/test_report.py @@ -7,15 +7,15 @@ """ import importlib -import re - +import json import mock import os -import shutil import pytest +import re +import shutil import sys + from lxml import etree -import json from conftest import TEST_DATA, ZEPHYR_BASE, testsuite_filename_mock from twisterlib.testplan import TestPlan @@ -405,3 +405,69 @@ def test_enable_coverage(self, capfd, test_path, test_platforms, out_path, expec assert match, f'line not found: {line}' assert str(sys_exit.value) == '0' + + @pytest.mark.parametrize( + 'test_path, expected_testcase_count', + [(os.path.join(TEST_DATA, 'tests', 'dummy'), 6),], + ids=['dummy tests'] + ) + def test_detailed_skipped_report(self, out_path, test_path, expected_testcase_count): + test_platforms = ['qemu_x86', 'frdm_k64f'] + args = ['-i', '--outdir', out_path, '-T', test_path] + \ + ['--detailed-skipped-report'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + testsuite_counter = 0 + xml_data = etree.parse(os.path.join(out_path, 'twister_report.xml')).getroot() + for ts in xml_data.iter('testsuite'): + testsuite_counter += 1 + # Without the tested flag, filtered testcases would be missing from the report + assert len(list(ts.iter('testcase'))) == expected_testcase_count, \ + 'Not all expected testcases appear in the report.' + + assert testsuite_counter == len(test_platforms), \ + 'Some platforms are missing from the XML report.' + + def test_enable_size_report(self, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'device', 'group') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--enable-size-report'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + with open(os.path.join(out_path, 'twister.json')) as f: + j = json.load(f) + + expected_rel_path = os.path.relpath(os.path.join(path, 'dummy.device.group'), ZEPHYR_BASE) + + # twister.json will contain [used/available]_[ram/rom] keys if the flag works + # except for those keys that would have values of 0. + # In this testcase, availables are equal to 0, so they are missing. + assert all( + [ + 'used_ram' in ts for ts in j['testsuites'] \ + if ts['name'] == expected_rel_path and not 'reason' in ts + ] + ) + assert all( + [ + 'used_rom' in ts for ts in j['testsuites'] \ + if ts['name'] == expected_rel_path and not 'reason' in ts + ] + ) From e8b843b913d8f618ba546d2c3d1effa7e437f14d Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Fri, 1 Mar 2024 16:07:02 +0100 Subject: [PATCH 0148/2402] net: shell: keep event_mon_handler compatible to k_thread_entry_t Nearly all other code places for k_thread_entry_t also keep unused params in place to stay compatible with k_thread_entry_t. Signed-off-by: Florian La Roche --- subsys/net/lib/shell/events.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/subsys/net/lib/shell/events.c b/subsys/net/lib/shell/events.c index 88b3644e029..32edca8b24b 100644 --- a/subsys/net/lib/shell/events.c +++ b/subsys/net/lib/shell/events.c @@ -272,11 +272,13 @@ static const char *get_l4_desc(uint32_t event) /* We use a separate thread in order not to do any shell printing from * event handler callback (to avoid stack size issues). */ -static void event_mon_handler(const struct shell *sh) +static void event_mon_handler(const struct shell *sh, void *p2, void *p3) { char extra_info[NET_IPV6_ADDR_LEN]; struct event_msg msg; + ARG_UNUSED(p2); + ARG_UNUSED(p3); net_mgmt_init_event_callback(&l2_cb, event_handler, MONITOR_L2_MASK); net_mgmt_add_event_callback(&l2_cb); From 4dae6623bc1b1d166968667cb719c245445af4fa Mon Sep 17 00:00:00 2001 From: Thomas PUJOLLE Date: Mon, 19 Feb 2024 16:15:58 +0100 Subject: [PATCH 0149/2402] Bluetooth: BT_HCI_RESERVE set to 1 if BT_SILABS_HCI Was previously causing execution errors due to default value 0 Signed-off-by: Thomas PUJOLLE --- subsys/bluetooth/host/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/subsys/bluetooth/host/Kconfig b/subsys/bluetooth/host/Kconfig index eb9db567469..aae4a5151f9 100644 --- a/subsys/bluetooth/host/Kconfig +++ b/subsys/bluetooth/host/Kconfig @@ -84,6 +84,7 @@ config BT_HCI_RESERVE default 1 if BT_ESP32 default 0 if BT_B91 default 1 if BT_AMBIQ_HCI + default 1 if BT_SILABS_HCI # Even if no driver is selected the following default is still # needed e.g. for unit tests. default 0 From c148dc15fd3a13eaa657ebb513d54534c3b4c5a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Fri, 2 Feb 2024 20:57:55 +0100 Subject: [PATCH 0150/2402] net: dhcpv4: add vendor specific option callback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In certain scenarios, it may be necessary to get values of additional options from the application layer. With this patch, this can be accomplished by registering a callback with the DHCP client. This change has been tested using the posix build in qemu. Signed-off-by: Fin Maaß --- include/zephyr/net/dhcpv4.h | 42 ++++++++ subsys/net/lib/dhcpv4/Kconfig | 8 ++ subsys/net/lib/dhcpv4/dhcpv4.c | 122 ++++++++++++++++++++++++ subsys/net/lib/dhcpv4/dhcpv4_internal.h | 1 + 4 files changed, 173 insertions(+) diff --git a/include/zephyr/net/dhcpv4.h b/include/zephyr/net/dhcpv4.h index 0117e62f9d3..884c4dea5ce 100644 --- a/include/zephyr/net/dhcpv4.h +++ b/include/zephyr/net/dhcpv4.h @@ -163,6 +163,48 @@ int net_dhcpv4_remove_option_callback(struct net_dhcpv4_option_callback *cb); #endif /* CONFIG_NET_DHCPV4_OPTION_CALLBACKS */ +#ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC + +/** + * @brief Helper to initialize a struct net_dhcpv4_option_callback for encapsulated vendor-specific + * options properly + * @param callback A valid Application's callback structure pointer. + * @param handler A valid handler function pointer. + * @param option The DHCP encapsulated vendor-specific option the callback responds to. + * @param data A pointer to a buffer for max_length bytes. + * @param max_length The maximum length of the data returned. + */ +static inline void +net_dhcpv4_init_option_vendor_callback(struct net_dhcpv4_option_callback *callback, + net_dhcpv4_option_callback_handler_t handler, uint8_t option, + void *data, size_t max_length) +{ + __ASSERT(callback, "Callback pointer should not be NULL"); + __ASSERT(handler, "Callback handler pointer should not be NULL"); + __ASSERT(data, "Data pointer should not be NULL"); + + callback->handler = handler; + callback->option = option; + callback->data = data; + callback->max_length = max_length; +} + +/** + * @brief Add an application callback for encapsulated vendor-specific options. + * @param cb A valid application's callback structure pointer. + * @return 0 if successful, negative errno code on failure. + */ +int net_dhcpv4_add_option_vendor_callback(struct net_dhcpv4_option_callback *cb); + +/** + * @brief Remove an application callback for encapsulated vendor-specific options. + * @param cb A valid application's callback structure pointer. + * @return 0 if successful, negative errno code on failure. + */ +int net_dhcpv4_remove_option_vendor_callback(struct net_dhcpv4_option_callback *cb); + +#endif /* CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC */ + /** * @brief Start DHCPv4 client on an iface * diff --git a/subsys/net/lib/dhcpv4/Kconfig b/subsys/net/lib/dhcpv4/Kconfig index 5a0f1aae315..1d23f748e39 100644 --- a/subsys/net/lib/dhcpv4/Kconfig +++ b/subsys/net/lib/dhcpv4/Kconfig @@ -46,6 +46,14 @@ config NET_DHCPV4_MAX_REQUESTED_OPTIONS DHCPv4 request message. The options are added using the net_dhcpv4_add_option_callback() API. +config NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC + bool "Encapsulated vendor specific option callbacks" + depends on NET_DHCPV4 + select NET_DHCPV4_OPTION_CALLBACKS + help + If set, custom callbacks for encapsulated vendor-specific + information in DHCP option 43 can be added. + config NET_DHCPV4_ACCEPT_UNICAST bool "Accept unicast DHCPv4 traffic" depends on NET_DHCPV4 diff --git a/subsys/net/lib/dhcpv4/dhcpv4.c b/subsys/net/lib/dhcpv4/dhcpv4.c index bfcd7c5f4ce..0cf133e6d74 100644 --- a/subsys/net/lib/dhcpv4/dhcpv4.c +++ b/subsys/net/lib/dhcpv4/dhcpv4.c @@ -49,11 +49,18 @@ static sys_slist_t option_callbacks = SYS_SLIST_STATIC_INIT(&option_callbacks); static int unique_types_in_callbacks; #endif +#if defined(CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC) +static sys_slist_t option_vendor_callbacks = SYS_SLIST_STATIC_INIT(&option_vendor_callbacks); +#endif + static const uint8_t min_req_options[] = { DHCPV4_OPTIONS_SUBNET_MASK, DHCPV4_OPTIONS_ROUTER, #ifdef CONFIG_NET_DHCPV4_OPTION_NTP_SERVER DHCPV4_OPTIONS_NTP_SERVER, +#endif +#ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC + DHCPV4_OPTIONS_VENDOR_SPECIFIC, #endif DHCPV4_OPTIONS_DNS_SERVER }; @@ -752,6 +759,71 @@ static void dhcpv4_timeout(struct k_work *work) } } +#if defined(CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC) + +static int dhcpv4_parse_option_vendor(struct net_pkt *pkt, struct net_if *iface, + enum net_dhcpv4_msg_type *msg_type, int length) +{ + struct net_dhcpv4_option_callback *cb, *tmp; + struct net_pkt_cursor backup; + uint8_t len; + uint8_t type; + + if (length < 3) { + NET_ERR("Vendor-specific option parsing, length too short"); + net_pkt_skip(pkt, length); + return -EBADMSG; + } + + while (!net_pkt_read_u8(pkt, &type)) { + if (type == DHCPV4_OPTIONS_END) { + NET_DBG("Vendor-specific options_end"); + return 0; + } + length--; + + if (length <= 0) { + NET_ERR("Vendor-specific option parsing, malformed option"); + return -EBADMSG; + } + + if (net_pkt_read_u8(pkt, &len)) { + NET_ERR("Vendor-specific option parsing, bad length"); + return -ENOBUFS; + } + length--; + if (length < len) { + NET_ERR("Vendor-specific option parsing, length too long"); + net_pkt_skip(pkt, length); + return -EBADMSG; + } + net_pkt_cursor_backup(pkt, &backup); + + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&option_vendor_callbacks, cb, tmp, node) { + if (cb->option == type) { + NET_ASSERT(cb->handler, "No callback handler!"); + + if (net_pkt_read(pkt, cb->data, MIN(cb->max_length, len))) { + NET_DBG("option vendor callback, read err"); + return -ENOBUFS; + } + + cb->handler(cb, len, *msg_type, iface); + net_pkt_cursor_restore(pkt, &backup); + } + } + net_pkt_skip(pkt, len); + length = length - len; + if (length <= 0) { + NET_DBG("Vendor-specific options_end (no code 255)"); + return 0; + } + } + return -ENOBUFS; +} + +#endif /* CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC */ + /* Parse DHCPv4 options and retrieve relevant information * as per RFC 2132. */ @@ -923,6 +995,24 @@ static bool dhcpv4_parse_options(struct net_pkt *pkt, break; } #endif /* CONFIG_NET_DHCPV4_OPTION_NTP_SERVER */ +#if defined(CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC) + case DHCPV4_OPTIONS_VENDOR_SPECIFIC: { + if (!sys_slist_is_empty(&option_vendor_callbacks)) { + NET_DBG("options_vendor_specific"); + if (dhcpv4_parse_option_vendor(pkt, iface, msg_type, length) == + -ENOBUFS) { + return false; + } + } else { + NET_DBG("options_vendor_specific, no callbacks"); + if (net_pkt_skip(pkt, length)) { + NET_DBG("options_vendor_specific, skip err"); + return false; + } + } + break; + } +#endif case DHCPV4_OPTIONS_LEASE_TIME: if (length != 4U) { NET_ERR("options_lease_time, bad length"); @@ -1424,6 +1514,38 @@ int net_dhcpv4_remove_option_callback(struct net_dhcpv4_option_callback *cb) #endif /* CONFIG_NET_DHCPV4_OPTION_CALLBACKS */ +#if defined(CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC) + +int net_dhcpv4_add_option_vendor_callback(struct net_dhcpv4_option_callback *cb) +{ + if (cb == NULL || cb->handler == NULL) { + return -EINVAL; + } + + k_mutex_lock(&lock, K_FOREVER); + sys_slist_prepend(&option_vendor_callbacks, &cb->node); + k_mutex_unlock(&lock); + return 0; +} + +int net_dhcpv4_remove_option_vendor_callback(struct net_dhcpv4_option_callback *cb) +{ + int ret = 0; + + if (cb == NULL || cb->handler == NULL) { + return -EINVAL; + } + + k_mutex_lock(&lock, K_FOREVER); + if (!sys_slist_find_and_remove(&option_vendor_callbacks, &cb->node)) { + ret = -EINVAL; + } + k_mutex_unlock(&lock); + return ret; +} + +#endif /* CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC */ + void net_dhcpv4_start(struct net_if *iface) { return dhcpv4_start_internal(iface, true); diff --git a/subsys/net/lib/dhcpv4/dhcpv4_internal.h b/subsys/net/lib/dhcpv4/dhcpv4_internal.h index 677ccf99ac9..69b31ed7c07 100644 --- a/subsys/net/lib/dhcpv4/dhcpv4_internal.h +++ b/subsys/net/lib/dhcpv4/dhcpv4_internal.h @@ -56,6 +56,7 @@ struct dhcp_msg { #define DHCPV4_OPTIONS_DNS_SERVER 6 #define DHCPV4_OPTIONS_HOST_NAME 12 #define DHCPV4_OPTIONS_NTP_SERVER 42 +#define DHCPV4_OPTIONS_VENDOR_SPECIFIC 43 #define DHCPV4_OPTIONS_REQ_IPADDR 50 #define DHCPV4_OPTIONS_LEASE_TIME 51 #define DHCPV4_OPTIONS_MSG_TYPE 53 From 2f84e7be83f3eeaefd28b72cc3f2b0dc7680ee9c Mon Sep 17 00:00:00 2001 From: Matthias Breithaupt Date: Tue, 13 Feb 2024 10:01:00 +0100 Subject: [PATCH 0151/2402] tests: net: dhcpv4: tests for encapsulated vendor specific option callbacks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add tests for the encapsulated vendor specific option callback API. These test cases are focused on correct parsing of encapsulated vendor specific options. The sample DHCP messages have been extended accordingly. Signed-off-by: Matthias Breithaupt Signed-off-by: Fin Maaß Co-authored-by: Fin Maaß --- tests/net/dhcpv4/client/src/main.c | 226 +++++++++++++++++++++++--- tests/net/dhcpv4/client/testcase.yaml | 4 + 2 files changed, 208 insertions(+), 22 deletions(-) diff --git a/tests/net/dhcpv4/client/src/main.c b/tests/net/dhcpv4/client/src/main.c index 17520ad445a..91f8f06d1bf 100644 --- a/tests/net/dhcpv4/client/src/main.c +++ b/tests/net/dhcpv4/client/src/main.c @@ -36,8 +36,8 @@ LOG_MODULE_REGISTER(net_test, CONFIG_NET_DHCPV4_LOG_LEVEL); #define NET_LOG_ENABLED 1 #include "net_private.h" -/* Sample DHCP offer (382 bytes) */ -static const unsigned char offer[382] = { +/* Sample DHCP offer (420 bytes) */ +static const unsigned char offer[420] = { 0x02, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xed, 0x48, 0x9e, 0x0a, 0xb8, @@ -84,12 +84,35 @@ static const unsigned char offer[382] = { 0x6d, 0x00, 0x04, 0x63, 0x6f, 0x72, 0x70, 0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, 0x63, 0x6f, 0x6d, 0x00, 0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, -0x03, 0x63, 0x6f, 0x6d, 0x00, 0x2c, 0x08, 0xa3, -0x21, 0x07, 0x56, 0x8f, 0xb6, 0xfa, 0x69, 0xff +0x03, 0x63, 0x6f, 0x6d, 0x00, +/* [44] NetBIOS Name Servers: 163.33.7.86, 143.182.250.105 */ +0x2c, 0x08, 0xa3, 0x21, 0x07, 0x56, 0x8f, 0xb6, 0xfa, 0x69, +/* [43] Encapsulated vendor specific information */ +0x2b, 0x0a, + /* [1]: "string" */ + 0x01, 0x07, 0x73, 0x74, 0x72, 0x69, 0x6e, 0x67, 0x00, + /* End marker */ + 0xff, +/* [43] Encapsulated vendor specific information */ +0x2b, 0x0f, + /* [2]: single byte of value 1 */ + 0x02, 0x01, 0x01, + /* [3]: zero-length option */ + 0x03, 0x00, + /* [254]: invalid option (size longer than remainder of opt 43 size) */ + 0xfe, 0x10, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, +/* [43] Too short encapsulated vendor option (only single byte) */ +0x2b, 0x01, + /* [254]: invalid option (no length in opt 43) */ + 0xfe, +/* [70] POP3 Server: 198.51.100.16 */ +0x46, 0x04, 0xc6, 0x33, 0x64, 0x10, +/* End marker */ +0xff }; /* Sample DHCPv4 ACK */ -static const unsigned char ack[382] = { +static const unsigned char ack[420] = { 0x02, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0xed, 0x48, 0x9e, 0x00, 0x00, 0x00, 0x00, @@ -136,19 +159,47 @@ static const unsigned char ack[382] = { 0x04, 0x63, 0x6f, 0x72, 0x70, 0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, 0x63, 0x6f, 0x6d, 0x00, 0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, 0x63, -0x6f, 0x6d, 0x00, 0x2c, 0x08, 0xa3, 0x21, 0x07, -0x56, 0x8f, 0xb6, 0xfa, 0x69, 0xff +0x6f, 0x6d, 0x00, +/* [44] NetBIOS Name Servers: 163.33.7.86, 143.182.250.105 */ +0x2c, 0x08, 0xa3, 0x21, 0x07, 0x56, 0x8f, 0xb6, 0xfa, 0x69, +/* [43] Encapsulated vendor specific information */ +0x2b, 0x0a, + /* [1]: "string" */ + 0x01, 0x07, 0x73, 0x74, 0x72, 0x69, 0x6e, 0x67, 0x00, + /* End marker */ + 0xff, +/* [43] Encapsulated vendor specific information */ +0x2b, 0x0f, + /* [2]: single byte of value 1 */ + 0x02, 0x01, 0x01, + /* [3]: zero-length option */ + 0x03, 0x00, + /* [254]: invalid option (size longer than remainder of opt 43 size) */ + 0xfe, 0x10, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, +/* [43] Too short encapsulated vendor option (only single byte) */ +0x2b, 0x01, + /* [254]: invalid option (no length in opt 43) */ + 0xfe, +/* [70] POP3 Server: 198.51.100.16 */ +0x46, 0x04, 0xc6, 0x33, 0x64, 0x10, +/* End marker */ +0xff }; static const struct in_addr server_addr = { { { 192, 0, 2, 1 } } }; static const struct in_addr client_addr = { { { 255, 255, 255, 255 } } }; -#define SERVER_PORT 67 -#define CLIENT_PORT 68 -#define MSG_TYPE 53 -#define DISCOVER 1 -#define REQUEST 3 -#define OPTION_DOMAIN 15 +#define SERVER_PORT 67 +#define CLIENT_PORT 68 +#define MSG_TYPE 53 +#define DISCOVER 1 +#define REQUEST 3 +#define OPTION_DOMAIN 15 +#define OPTION_POP3 70 +#define OPTION_VENDOR_STRING 1 +#define OPTION_VENDOR_BYTE 2 +#define OPTION_VENDOR_EMPTY 3 +#define OPTION_INVALID 254 struct dhcp_msg { uint32_t xid; @@ -391,9 +442,17 @@ static struct net_mgmt_event_callback rx_cb; static struct net_mgmt_event_callback dns_cb; static struct net_mgmt_event_callback dhcp_cb; #ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS -static struct net_dhcpv4_option_callback opt_cb; +static struct net_dhcpv4_option_callback opt_domain_cb; +static struct net_dhcpv4_option_callback opt_pop3_cb; +static struct net_dhcpv4_option_callback opt_invalid_cb; static uint8_t buffer[15]; #endif +#ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC +static struct net_dhcpv4_option_callback opt_vs_string_cb; +static struct net_dhcpv4_option_callback opt_vs_byte_cb; +static struct net_dhcpv4_option_callback opt_vs_empty_cb; +static struct net_dhcpv4_option_callback opt_vs_invalid_cb; +#endif static int event_count; static void receiver_cb(struct net_mgmt_event_callback *cb, @@ -415,10 +474,10 @@ static void receiver_cb(struct net_mgmt_event_callback *cb, #ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS -static void option_cb(struct net_dhcpv4_option_callback *cb, - size_t length, - enum net_dhcpv4_msg_type msg_type, - struct net_if *iface) +static void option_domain_cb(struct net_dhcpv4_option_callback *cb, + size_t length, + enum net_dhcpv4_msg_type msg_type, + struct net_if *iface) { char expectation[] = "fi.intel.com"; @@ -432,6 +491,87 @@ static void option_cb(struct net_dhcpv4_option_callback *cb, k_sem_give(&test_lock); } +static void option_pop3_cb(struct net_dhcpv4_option_callback *cb, + size_t length, + enum net_dhcpv4_msg_type msg_type, + struct net_if *iface) +{ + uint8_t expectation[4]; + + expectation[0] = 198; + expectation[1] = 51; + expectation[2] = 100; + expectation[3] = 16; + + zassert_equal(cb->option, OPTION_POP3, "Unexpected option value"); + zassert_equal(length, sizeof(expectation), "Incorrect data length"); + zassert_mem_equal(buffer, expectation, sizeof(expectation), + "Incorrect buffer contents"); + + event_count++; + + k_sem_give(&test_lock); +} + +static void option_invalid_cb(struct net_dhcpv4_option_callback *cb, + size_t length, + enum net_dhcpv4_msg_type msg_type, + struct net_if *iface) +{ + /* This function should never be called. If it is, the parser took a wrong turn. */ + zassert_true(false, "Unexpected callback - incorrect parsing of vendor sepcific options"); +} + +#ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC + +static void vendor_specific_string_cb(struct net_dhcpv4_option_callback *cb, + size_t length, + enum net_dhcpv4_msg_type msg_type, + struct net_if *iface) +{ + char expectation[] = "string"; + + zassert_equal(cb->option, OPTION_VENDOR_STRING, + "Unexpected vendor specific option value"); + zassert_equal(length, sizeof(expectation), "Incorrect data length"); + zassert_mem_equal(buffer, expectation, sizeof(expectation), "Incorrect buffer contents"); + + event_count++; + + k_sem_give(&test_lock); +} + +static void vendor_specific_byte_cb(struct net_dhcpv4_option_callback *cb, + size_t length, + enum net_dhcpv4_msg_type msg_type, + struct net_if *iface) +{ + zassert_equal(cb->option, OPTION_VENDOR_BYTE, + "Unexpected vendor specific option value"); + zassert_equal(length, 1, "Incorrect data length"); + zassert_equal(buffer[0], 1, "Incorrect buffer contents"); + + event_count++; + + k_sem_give(&test_lock); +} + +static void vendor_specific_empty_cb(struct net_dhcpv4_option_callback *cb, + size_t length, + enum net_dhcpv4_msg_type msg_type, + struct net_if *iface) +{ + zassert_equal(cb->option, OPTION_VENDOR_EMPTY, + "Unexpected vendor specific option value"); + zassert_equal(length, 0, "Incorrect data length"); + + event_count++; + + k_sem_give(&test_lock); +} + +#endif /* CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC */ + #endif /* CONFIG_NET_DHCPV4_OPTION_CALLBACKS */ ZTEST(dhcpv4_tests, test_dhcp) @@ -458,13 +598,53 @@ ZTEST(dhcpv4_tests, test_dhcp) net_mgmt_add_event_callback(&dhcp_cb); #ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS - net_dhcpv4_init_option_callback(&opt_cb, option_cb, + net_dhcpv4_init_option_callback(&opt_domain_cb, option_domain_cb, OPTION_DOMAIN, buffer, sizeof(buffer)); - net_dhcpv4_add_option_callback(&opt_cb); + net_dhcpv4_add_option_callback(&opt_domain_cb); + + net_dhcpv4_init_option_callback(&opt_pop3_cb, option_pop3_cb, + OPTION_POP3, buffer, + sizeof(buffer)); + + net_dhcpv4_add_option_callback(&opt_pop3_cb); + + net_dhcpv4_init_option_callback(&opt_invalid_cb, option_invalid_cb, + OPTION_INVALID, buffer, + sizeof(buffer)); + + net_dhcpv4_add_option_callback(&opt_invalid_cb); #endif /* CONFIG_NET_DHCPV4_OPTION_CALLBACKS */ +#ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC + net_dhcpv4_init_option_vendor_callback(&opt_vs_string_cb, vendor_specific_string_cb, + OPTION_VENDOR_STRING, buffer, + sizeof(buffer)); + + net_dhcpv4_add_option_vendor_callback(&opt_vs_string_cb); + + net_dhcpv4_init_option_vendor_callback(&opt_vs_byte_cb, vendor_specific_byte_cb, + OPTION_VENDOR_BYTE, buffer, + sizeof(buffer)); + + net_dhcpv4_add_option_vendor_callback(&opt_vs_byte_cb); + + net_dhcpv4_init_option_vendor_callback(&opt_vs_empty_cb, vendor_specific_empty_cb, + OPTION_VENDOR_EMPTY, buffer, + sizeof(buffer)); + + net_dhcpv4_add_option_vendor_callback(&opt_vs_empty_cb); + + net_dhcpv4_init_option_vendor_callback(&opt_vs_invalid_cb, option_invalid_cb, + OPTION_INVALID, buffer, + sizeof(buffer)); + + net_dhcpv4_add_option_vendor_callback(&opt_vs_invalid_cb); + + +#endif /* CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC */ + iface = net_if_get_first_by_type(&NET_L2_GET_NAME(DUMMY)); if (!iface) { zassert_true(false, "Interface not available"); @@ -472,8 +652,10 @@ ZTEST(dhcpv4_tests, test_dhcp) net_dhcpv4_start(iface); -#ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS - while (event_count < 6) { +#ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC + while (event_count < 16) { +#elif defined(CONFIG_NET_DHCPV4_OPTION_CALLBACKS) + while (event_count < 10) { #else while (event_count < 5) { #endif diff --git a/tests/net/dhcpv4/client/testcase.yaml b/tests/net/dhcpv4/client/testcase.yaml index f0a476cfcf5..512d4dc159b 100644 --- a/tests/net/dhcpv4/client/testcase.yaml +++ b/tests/net/dhcpv4/client/testcase.yaml @@ -13,3 +13,7 @@ tests: net.dhcpv4_client.optioncbs: extra_configs: - CONFIG_NET_DHCPV4_OPTION_CALLBACKS=y + net.dhcpv4_client.optioncbs_vendor_specific: + extra_configs: + - CONFIG_NET_DHCPV4_OPTION_CALLBACKS=y + - CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC=y From 1b76f828c9540cb5813a19185ee4655b2119035b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 15 Feb 2024 09:43:53 +0100 Subject: [PATCH 0152/2402] tests: net: dhcpv4: add comments to sample packets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To make the content of the sample packets more more understandable, comments describing it are added. Signed-off-by: Fin Maaß --- tests/net/dhcpv4/client/src/main.c | 94 +++++++++++++++++++----------- 1 file changed, 59 insertions(+), 35 deletions(-) diff --git a/tests/net/dhcpv4/client/src/main.c b/tests/net/dhcpv4/client/src/main.c index 91f8f06d1bf..ceddbbe9e69 100644 --- a/tests/net/dhcpv4/client/src/main.c +++ b/tests/net/dhcpv4/client/src/main.c @@ -67,24 +67,36 @@ static const unsigned char offer[420] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x82, -0x53, 0x63, 0x35, 0x01, 0x02, 0x01, 0x04, 0xff, -0xff, 0xff, 0x00, 0x3a, 0x04, 0x00, 0x00, 0x54, -0x60, 0x3b, 0x04, 0x00, 0x00, 0x93, 0xa8, 0x33, -0x04, 0x00, 0x00, 0xa8, 0xc0, 0x36, 0x04, 0x0a, -0xb8, 0x09, 0x01, 0x03, 0x04, 0x0a, 0xed, 0x48, -0x01, 0x0f, 0x0d, 0x66, 0x69, 0x2e, 0x69, 0x6e, -0x74, 0x65, 0x6c, 0x2e, 0x63, 0x6f, 0x6d, 0x00, -0x06, 0x0c, 0x0a, 0xf8, 0x02, 0x01, 0xa3, 0x21, -0xfd, 0x44, 0x0a, 0xb8, 0x09, 0x01, 0x77, 0x3d, -0x02, 0x66, 0x69, 0x05, 0x69, 0x6e, 0x74, 0x65, -0x6c, 0x03, 0x63, 0x6f, 0x6d, 0x00, 0x03, 0x67, -0x65, 0x72, 0x04, 0x63, 0x6f, 0x72, 0x70, 0x05, -0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, 0x63, 0x6f, -0x6d, 0x00, 0x04, 0x63, 0x6f, 0x72, 0x70, 0x05, -0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, 0x63, 0x6f, -0x6d, 0x00, 0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, -0x03, 0x63, 0x6f, 0x6d, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Magic cookie: DHCP */ +0x63, 0x82, 0x53, 0x63, +/* [53] DHCP Message Type: OFFER */ +0x35, 0x01, 0x02, +/* [1] Subnet Mask: 255.255.255.0 */ +0x01, 0x04, 0xff, 0xff, 0xff, 0x00, +/* [58] Renewal Time Value: (21600s) 6 hours */ +0x3a, 0x04, 0x00, 0x00, 0x54, 0x60, +/* [59] Rebinding Time Value: (37800s) 1 hour 30 min */ +0x3b, 0x04, 0x00, 0x00, 0x93, 0xa8, +/* [51] IP Address Lease Time: (43200s) 12 hours */ +0x33, 0x04, 0x00, 0x00, 0xa8, 0xc0, +/* [54] DHCP Server Identifier: 10.184.9.1 */ +0x36, 0x04, 0x0a, 0xb8, 0x09, 0x01, +/* [3] Router: 10.237.72.1 */ +0x03, 0x04, 0x0a, 0xed, 0x48, 0x01, +/* [15] Domain Name: fi.intel.com */ +0x0f, 0x0d, 0x66, 0x69, 0x2e, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x2e, 0x63, 0x6f, 0x6d, 0x00, +/* [6] Domain Name Server: 10.248.2.1 163.33.253.68 10.184.9.1 */ +0x06, 0x0c, 0x0a, 0xf8, 0x02, 0x01, 0xa3, 0x21, 0xfd, 0x44, 0x0a, 0xb8, 0x09, 0x01, +/* [119] Domain Search Option: fi.intel.com ger.corp.intel.com corp.intel.com intel.com */ +0x77, 0x3d, 0x02, 0x66, 0x69, 0x05, 0x69, 0x6e, +0x74, 0x65, 0x6c, 0x03, 0x63, 0x6f, 0x6d, 0x00, +0x03, 0x67, 0x65, 0x72, 0x04, 0x63, 0x6f, 0x72, +0x70, 0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, +0x63, 0x6f, 0x6d, 0x00, 0x04, 0x63, 0x6f, 0x72, +0x70, 0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, +0x63, 0x6f, 0x6d, 0x00, 0x05, 0x69, 0x6e, 0x74, +0x65, 0x6c, 0x03, 0x63, 0x6f, 0x6d, 0x00, /* [44] NetBIOS Name Servers: 163.33.7.86, 143.182.250.105 */ 0x2c, 0x08, 0xa3, 0x21, 0x07, 0x56, 0x8f, 0xb6, 0xfa, 0x69, /* [43] Encapsulated vendor specific information */ @@ -142,24 +154,36 @@ static const unsigned char ack[420] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x63, 0x82, 0x53, 0x63, -0x35, 0x01, 0x05, 0x3a, 0x04, 0x00, 0x00, 0x54, -0x60, 0x3b, 0x04, 0x00, 0x00, 0x93, 0xa8, 0x33, -0x04, 0x00, 0x00, 0xa8, 0xc0, 0x36, 0x04, 0x0a, -0xb8, 0x09, 0x01, 0x01, 0x04, 0xff, 0xff, 0xff, -0x00, 0x03, 0x04, 0x0a, 0xed, 0x48, 0x01, 0x0f, -0x0d, 0x66, 0x69, 0x2e, 0x69, 0x6e, 0x74, 0x65, -0x6c, 0x2e, 0x63, 0x6f, 0x6d, 0x00, 0x06, 0x0c, -0x0a, 0xf8, 0x02, 0x01, 0xa3, 0x21, 0xfd, 0x44, -0x0a, 0xb8, 0x09, 0x01, 0x77, 0x3d, 0x02, 0x66, -0x69, 0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, -0x63, 0x6f, 0x6d, 0x00, 0x03, 0x67, 0x65, 0x72, -0x04, 0x63, 0x6f, 0x72, 0x70, 0x05, 0x69, 0x6e, -0x74, 0x65, 0x6c, 0x03, 0x63, 0x6f, 0x6d, 0x00, -0x04, 0x63, 0x6f, 0x72, 0x70, 0x05, 0x69, 0x6e, +0x00, 0x00, 0x00, 0x00, +/* Magic cookie: DHCP */ +0x63, 0x82, 0x53, 0x63, +/* [53] DHCP Message Type: ACK */ +0x35, 0x01, 0x05, +/* [58] Renewal Time Value: (21600s) 6 hours */ +0x3a, 0x04, 0x00, 0x00, 0x54, 0x60, +/* [59] Rebinding Time Value: (37800s) 1 hour 30 min */ +0x3b, 0x04, 0x00, 0x00, 0x93, 0xa8, +/* [51] IP Address Lease Time: (43200s) 12 hours */ +0x33, 0x04, 0x00, 0x00, 0xa8, 0xc0, +/* [54] DHCP Server Identifier: 10.184.9.1 */ +0x36, 0x04, 0x0a, 0xb8, 0x09, 0x01, +/* [1] Subnet Mask: 255.255.255.0 */ +0x01, 0x04, 0xff, 0xff, 0xff, 0x00, +/* [3] Router: 10.237.72.1 */ +0x03, 0x04, 0x0a, 0xed, 0x48, 0x01, +/* [15] Domain Name: fi.intel.com */ +0x0f, 0x0d, 0x66, 0x69, 0x2e, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x2e, 0x63, 0x6f, 0x6d, 0x00, +/* [6] Domain Name Server: 10.248.2.1 163.33.253.68 10.184.9.1 */ +0x06, 0x0c, 0x0a, 0xf8, 0x02, 0x01, 0xa3, 0x21, 0xfd, 0x44, 0x0a, 0xb8, 0x09, 0x01, +/* [119] Domain Search Option: fi.intel.com ger.corp.intel.com corp.intel.com intel.com */ +0x77, 0x3d, 0x02, 0x66, 0x69, 0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, 0x63, 0x6f, 0x6d, 0x00, -0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, 0x63, -0x6f, 0x6d, 0x00, +0x03, 0x67, 0x65, 0x72, 0x04, 0x63, 0x6f, 0x72, +0x70, 0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, +0x63, 0x6f, 0x6d, 0x00, 0x04, 0x63, 0x6f, 0x72, +0x70, 0x05, 0x69, 0x6e, 0x74, 0x65, 0x6c, 0x03, +0x63, 0x6f, 0x6d, 0x00, 0x05, 0x69, 0x6e, 0x74, +0x65, 0x6c, 0x03, 0x63, 0x6f, 0x6d, 0x00, /* [44] NetBIOS Name Servers: 163.33.7.86, 143.182.250.105 */ 0x2c, 0x08, 0xa3, 0x21, 0x07, 0x56, 0x8f, 0xb6, 0xfa, 0x69, /* [43] Encapsulated vendor specific information */ From fe4b5594214b7fb396de7d13d5a67603b6888074 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Thu, 8 Feb 2024 12:05:11 +0200 Subject: [PATCH 0153/2402] dts: bindings: nxp,edma: force dma-cells number to 2 To allow EDMA configuration with the help of the DT_INST_DMAS_* and DT_DMAS_* macros, all that a consumer node needs to know is which channel to configure and what MUX value needs to be used. As such, this commit allows doing this by forcing the dma-cells property to 2, each cell representing one of the aforementioned properties. Signed-off-by: Laurentiu Mihalcea --- dts/bindings/dma/nxp,edma.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/dts/bindings/dma/nxp,edma.yaml b/dts/bindings/dma/nxp,edma.yaml index 5c3305cb7dd..37a5bcc3cac 100644 --- a/dts/bindings/dma/nxp,edma.yaml +++ b/dts/bindings/dma/nxp,edma.yaml @@ -39,3 +39,13 @@ properties: configurations available, the user will have to specify which configuration to use through this property. If missing, the configuration found at index 0 will be used. + "#dma-cells": + const: 2 + +# IMPORTANT: if your EDMA version doesn't support channel MUX-ing please +# leave the MUX cell as 0. This is not mandatory for the driver as the +# MUX value will be ignored in this case but all entities using EDMA should +# be consistent in this regard. +dma-cells: + - channel + - mux From 3799e0f498f73ce22a1fbb371134fdbd53fec2d1 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Fri, 9 Feb 2024 00:51:00 +0200 Subject: [PATCH 0154/2402] devicetree.h: switch to DT_IRQ_INTC_BY_IDX for L2 and L3 INTID encodings Using `DT_IRQ_INTC()` to fetch the interrupt controller associated with a node works well for nodes which consume interrupts from a single aggregator. However, when specifying multiple (and different) interrupt aggregators via the `interrupts-extended` property, the L2 and L3 interrupts will no longer be encoded properly. This is because `DT_IRQ_INTC(node_id)` uses `DT_IRQ_INTC_BY_IDX(node_id, 0)` so all the interrupts will use the first aggregator as their parent. To fix this, switch from using `DT_IRQ_INTC()` to `DT_IRQ_INTC_BY_IDX()`. Signed-off-by: Laurentiu Mihalcea --- include/zephyr/devicetree.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/include/zephyr/devicetree.h b/include/zephyr/devicetree.h index 7a71cf2fb42..53eccff85a8 100644 --- a/include/zephyr/devicetree.h +++ b/include/zephyr/devicetree.h @@ -2549,12 +2549,13 @@ #define DT_IRQN_L1_INTERNAL(node_id, idx) DT_IRQ_BY_IDX(node_id, idx, irq) /* DT helper macro to encode a node's IRQN to level 2 according to the multi-level scheme */ #define DT_IRQN_L2_INTERNAL(node_id, idx) \ - (IRQ_TO_L2(DT_IRQN_L1_INTERNAL(node_id, idx)) | DT_IRQ(DT_IRQ_INTC(node_id), irq)) + (IRQ_TO_L2(DT_IRQN_L1_INTERNAL(node_id, idx)) | \ + DT_IRQ(DT_IRQ_INTC_BY_IDX(node_id, idx), irq)) /* DT helper macro to encode a node's IRQN to level 3 according to the multi-level scheme */ #define DT_IRQN_L3_INTERNAL(node_id, idx) \ (IRQ_TO_L3(DT_IRQN_L1_INTERNAL(node_id, idx)) | \ - IRQ_TO_L2(DT_IRQ(DT_IRQ_INTC(node_id), irq)) | \ - DT_IRQ(DT_IRQ_INTC(DT_IRQ_INTC(node_id)), irq)) + IRQ_TO_L2(DT_IRQ(DT_IRQ_INTC_BY_IDX(node_id, idx), irq)) | \ + DT_IRQ(DT_IRQ_INTC(DT_IRQ_INTC_BY_IDX(node_id, idx)), irq)) /* DT helper macro for the macros above */ #define DT_IRQN_LVL_INTERNAL(node_id, idx, level) DT_CAT3(DT_IRQN_L, level, _INTERNAL)(node_id, idx) From 8fec5f361ca73d9877300d3e81f13353c0a7deff Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Sat, 2 Mar 2024 14:41:53 +0200 Subject: [PATCH 0155/2402] tests: devicetree: check L2 interrupt encoding Add some assert statements meant to check if L2 interrupts are encoded right when dealing with nodes that consume interrupts from multiple aggregators. For this to work, also add another interrupt controller node which extends a different L1 interrupt from `test_intc`. Signed-off-by: Laurentiu Mihalcea --- tests/lib/devicetree/api/app.overlay | 18 ++++++++++++++++-- tests/lib/devicetree/api/src/main.c | 14 ++++++++++++++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/tests/lib/devicetree/api/app.overlay b/tests/lib/devicetree/api/app.overlay index a870eea2b55..643bb0977cb 100644 --- a/tests/lib/devicetree/api/app.overlay +++ b/tests/lib/devicetree/api/app.overlay @@ -430,6 +430,19 @@ interrupt-parent = <&test_cpu_intc>; }; + /* same as `test_intc` but extends a different L1 interrupt. + * Required for testing if interrupts are encoded properly for + * nodes consuming interrupts from different aggregators. + */ + test_intc2: interrupt-controller@bbbbdccc { + compatible = "vnd,intc"; + reg = <0xbbbbdccc 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <12 0>; + interrupt-parent = <&test_cpu_intc>; + }; + /* there should only be one of these */ test_irq: interrupt-holder { compatible = "vnd,interrupt-holder"; @@ -444,8 +457,9 @@ compatible = "vnd,interrupt-holder-extended"; status = "okay"; interrupts-extended = <&test_intc 70 7>, - <&test_gpio_4 30 3>; - interrupt-names = "int1", "int2"; + <&test_gpio_4 30 3>, + <&test_intc2 42 7>; + interrupt-names = "int1", "int2", "int3"; }; test_fixed_clk: test-fixed-clock { diff --git a/tests/lib/devicetree/api/src/main.c b/tests/lib/devicetree/api/src/main.c index c9a1d668279..250c340a20c 100644 --- a/tests/lib/devicetree/api/src/main.c +++ b/tests/lib/devicetree/api/src/main.c @@ -750,6 +750,20 @@ ZTEST(devicetree_api, test_irq) zassert_true(DT_INST_IRQ_HAS_NAME(0, stat), ""); zassert_true(DT_INST_IRQ_HAS_NAME(0, done), ""); zassert_false(DT_INST_IRQ_HAS_NAME(0, alpha), ""); + +#ifdef CONFIG_MULTI_LEVEL_INTERRUPTS + /* the following asserts check if interrupt IDs are encoded + * properly when dealing with a node that consumes interrupts + * from L2 aggregators extending different L1 interrupts. + */ + zassert_equal(DT_IRQN_BY_IDX(TEST_IRQ_EXT, 0), + ((70 + 1) << CONFIG_1ST_LEVEL_INTERRUPT_BITS) | 11, ""); + zassert_equal(DT_IRQN_BY_IDX(TEST_IRQ_EXT, 2), + ((42 + 1) << CONFIG_1ST_LEVEL_INTERRUPT_BITS) | 12, ""); +#else + zassert_equal(DT_IRQN_BY_IDX(TEST_IRQ_EXT, 0), 70, ""); + zassert_equal(DT_IRQN_BY_IDX(TEST_IRQ_EXT, 2), 42, ""); +#endif /* CONFIG_MULTI_LEVEL_INTERRUPTS */ } ZTEST(devicetree_api, test_irq_level) From d84e806c34e1ef5c3445c52abb2e662bae80e78f Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 21 Feb 2024 16:12:50 +0100 Subject: [PATCH 0156/2402] dts: bindings: mbox: add nordic,nrf-vevif-local|remote Add a new binding for Nordic VEVIF (VPR Event Interface) (local and remote modes). Signed-off-by: Gerard Marull-Paretas --- .../mbox/nordic,nrf-vevif-common.yaml | 18 +++++++++++ dts/bindings/mbox/nordic,nrf-vevif-local.yaml | 32 +++++++++++++++++++ .../mbox/nordic,nrf-vevif-remote.yaml | 29 +++++++++++++++++ 3 files changed, 79 insertions(+) create mode 100644 dts/bindings/mbox/nordic,nrf-vevif-common.yaml create mode 100644 dts/bindings/mbox/nordic,nrf-vevif-local.yaml create mode 100644 dts/bindings/mbox/nordic,nrf-vevif-remote.yaml diff --git a/dts/bindings/mbox/nordic,nrf-vevif-common.yaml b/dts/bindings/mbox/nordic,nrf-vevif-common.yaml new file mode 100644 index 00000000000..b7cb15457f6 --- /dev/null +++ b/dts/bindings/mbox/nordic,nrf-vevif-common.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +include: mailbox-controller.yaml + +properties: + nordic,tasks: + type: int + required: true + description: Number of tasks supported by the VEVIF instance. + + nordic,tasks-mask: + type: int + required: true + description: Mask of tasks supported by the VEVIF instance. + +mbox-cells: + - channel diff --git a/dts/bindings/mbox/nordic,nrf-vevif-local.yaml b/dts/bindings/mbox/nordic,nrf-vevif-local.yaml new file mode 100644 index 00000000000..5d23cfdcf1e --- /dev/null +++ b/dts/bindings/mbox/nordic,nrf-vevif-local.yaml @@ -0,0 +1,32 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: | + Nordic VEVIF (VPR Event Interface) - Local + + VEVIF is an event interface for VPR, allowing connection to the domain's DPPI + system. VEVIF can also generate IRQs to other CPUs. + + Example definition: + + cpuppr: cpu@d { + ... + cpuppr_vevif_local: mailbox { + compatible = "nordic,nrf-vevif-local"; + interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, + <1 NRF_DEFAULT_IRQ_PRIORITY>, + ... + ; + #mbox-cells = <1>; + nordic,tasks = <16>; + nordic,tasks-mask: <0xfffffff0>; + }; + }; + +compatible: "nordic,nrf-vevif-local" + +include: [base.yaml, "nordic,nrf-vevif-common.yaml"] + +properties: + interrupts: + required: true diff --git a/dts/bindings/mbox/nordic,nrf-vevif-remote.yaml b/dts/bindings/mbox/nordic,nrf-vevif-remote.yaml new file mode 100644 index 00000000000..07522fed99d --- /dev/null +++ b/dts/bindings/mbox/nordic,nrf-vevif-remote.yaml @@ -0,0 +1,29 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: | + Nordic VEVIF (VPR Event Interface) - Remote + + VEVIF is an event interface for VPR, allowing connection to the domain's DPPI + system. VEVIF can also generate IRQs to other CPUs. + + Example definition: + + cpuppr_vpr: vpr@deadbeef{ + ... + cpuppr_vevif_remote: mailbox@0 { + compatible = "nordic,nrf-vevif-remote"; + reg = <0x0 0x1000>; + #mbox-cells = <1>; + nordic,tasks = <16>; + nordic,tasks-mask: <0xfffffff0>; + }; + }; + +compatible: "nordic,nrf-vevif-remote" + +include: [base.yaml, "nordic,nrf-vevif-common.yaml"] + +properties: + reg: + required: true From b823bacecb3583a3ec1b6127fa655fbe4ee812a1 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 21 Feb 2024 16:13:59 +0100 Subject: [PATCH 0157/2402] dts: nordic: nrf54h20_enga: add PPR VEVIF nodes Add a new nodes for PPR's VEVIF. In app cores, VEVIF registers are part of the VPR peripheral, so it is exposed as a child node (since it requires its own properties, eg #mbox-cells). In VPR, it's a CPU child since it's not a memory-mapped peripheral, but used with CSRs. Signed-off-by: Gerard Marull-Paretas --- dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi | 1 + dts/arm/nordic/nrf54h20_enga_cpurad.dtsi | 1 + dts/common/nordic/nrf54h20_enga.dtsi | 34 ++++++++++++++++++++++ dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi | 1 + 4 files changed, 37 insertions(+) diff --git a/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi b/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi index f51528d5733..c7a52a00296 100644 --- a/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi +++ b/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi @@ -9,6 +9,7 @@ cpu: &cpuapp {}; systick: &cpuapp_systick {}; nvic: &cpuapp_nvic {}; +cpuppr_vevif: &cpuppr_vevif_remote {}; /delete-node/ &cpuppr; /delete-node/ &cpurad; diff --git a/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi b/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi index cb2767381da..952f3c00ced 100644 --- a/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi +++ b/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi @@ -9,6 +9,7 @@ cpu: &cpurad {}; systick: &cpurad_systick {}; nvic: &cpurad_nvic {}; +cpuppr_vevif: &cpuppr_vevif_remote {}; /delete-node/ &cpuapp; /delete-node/ &cpuapp_peripherals; diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi index 5a9af57801c..b9ac3d7d0bf 100644 --- a/dts/common/nordic/nrf54h20_enga.dtsi +++ b/dts/common/nordic/nrf54h20_enga.dtsi @@ -40,6 +40,31 @@ clock-frequency = ; riscv,isa = "rv32emc"; nordic,bus-width = <32>; + + cpuppr_vevif_local: mailbox { + compatible = "nordic,nrf-vevif-local"; + status = "disabled"; + interrupt-parent = <&cpuppr_clic>; + interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, + <1 NRF_DEFAULT_IRQ_PRIORITY>, + <2 NRF_DEFAULT_IRQ_PRIORITY>, + <3 NRF_DEFAULT_IRQ_PRIORITY>, + <4 NRF_DEFAULT_IRQ_PRIORITY>, + <5 NRF_DEFAULT_IRQ_PRIORITY>, + <6 NRF_DEFAULT_IRQ_PRIORITY>, + <7 NRF_DEFAULT_IRQ_PRIORITY>, + <8 NRF_DEFAULT_IRQ_PRIORITY>, + <9 NRF_DEFAULT_IRQ_PRIORITY>, + <10 NRF_DEFAULT_IRQ_PRIORITY>, + <11 NRF_DEFAULT_IRQ_PRIORITY>, + <12 NRF_DEFAULT_IRQ_PRIORITY>, + <13 NRF_DEFAULT_IRQ_PRIORITY>, + <14 NRF_DEFAULT_IRQ_PRIORITY>, + <15 NRF_DEFAULT_IRQ_PRIORITY>; + #mbox-cells = <1>; + nordic,tasks = <16>; + nordic,tasks-mask = <0xfffffff0>; + }; }; }; @@ -281,6 +306,15 @@ #size-cells = <1>; ranges = <0x0 0x908000 0x4000>; + cpuppr_vevif_remote: mailbox@0 { + compatible = "nordic,nrf-vevif-remote"; + reg = <0x0 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + nordic,tasks = <16>; + nordic,tasks-mask = <0xfffffff0>; + }; + cpuppr_clic: interrupt-controller@1000 { compatible = "nordic,nrf-clic"; reg = <0x1000 0x3000>; diff --git a/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi b/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi index d42a815a4b2..d96956b7b73 100644 --- a/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi +++ b/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi @@ -8,6 +8,7 @@ cpu: &cpuppr {}; clic: &cpuppr_clic {}; +cpuppr_vevif: &cpuppr_vevif_local {}; /delete-node/ &cpuapp; /delete-node/ &cpuapp_peripherals; From be5403fe65a0a188aacc43a6ac11411c6411b4f5 Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Mon, 26 Feb 2024 14:50:21 +0100 Subject: [PATCH 0158/2402] boards: nrf54h20pdk_nrf54h20: Update memory map Add IPC shared memory regions in the global RAM, as well as an enlarged SRAM region for Application core. Signed-off-by: Grzegorz Swiderski --- .../nrf54h20pdk_nrf54h20-memory_map.dtsi | 100 +++++++++++++++++- .../nrf54h20pdk_nrf54h20_cpuapp.dts | 8 +- .../nrf54h20pdk_nrf54h20_cpurad.dts | 2 +- 3 files changed, 106 insertions(+), 4 deletions(-) diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi index cb5a4fe0b0c..560700b1756 100644 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi @@ -6,6 +6,96 @@ / { reserved-memory { + cpuapp_ram0x_region: memory@2f000000 { + compatible = "nordic,owned-memory"; + reg = <0x2f000000 DT_SIZE_K(260)>; + status = "disabled"; + perm-read; + perm-write; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f000000 0x41000>; + + cpusec_cpuapp_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpuapp_cpusec_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + + cpuapp_data: memory@1000 { + reg = <0x1000 DT_SIZE_K(256)>; + }; + }; + + cpurad_ram0x_region: memory@2f041000 { + compatible = "nordic,owned-memory"; + reg = <0x2f041000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f041000 0x1000>; + + cpusec_cpurad_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpurad_cpusec_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + }; + + cpuapp_cpurad_ram0x_region: memory@2f0bf000 { + compatible = "nordic,owned-memory"; + reg = <0x2f0bf000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f0bf000 0x1000>; + + cpuapp_cpurad_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpurad_cpuapp_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + }; + + shared_ram20_region: memory@2f88f000 { + compatible = "nordic,owned-memory"; + reg = <0x2f88f000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f88f000 0x1000>; + + cpuapp_cpusys_ipc_shm: memory@ce0 { + reg = <0xce0 0x80>; + }; + + cpusys_cpuapp_ipc_shm: memory@d60 { + reg = <0xd60 0x80>; + }; + + cpurad_cpusys_ipc_shm: memory@e00 { + reg = <0xe00 0x80>; + }; + + cpusys_cpurad_ipc_shm: memory@e80 { + reg = <0xe80 0x80>; + }; + }; + cpuppr_ram3x_region: memory@2fc00000 { compatible = "nordic,owned-memory"; reg = <0x2fc00000 DT_SIZE_K(28)>; @@ -15,7 +105,7 @@ perm-execute; }; - ram3x_dma_region: memory@2fc07000 { + shared_ram3x_region: memory@2fc07000 { compatible = "nordic,owned-memory"; reg = <0x2fc07000 DT_SIZE_K(4)>; status = "disabled"; @@ -25,6 +115,14 @@ #size-cells = <1>; ranges = <0x0 0x2fc07000 0x1000>; + cpuapp_cpuppr_ipc_shm: memory@0 { + reg = <0x0 0x340>; + }; + + cpuppr_cpuapp_ipc_shm: memory@340 { + reg = <0x340 0x340>; + }; + cpuapp_dma_region: memory@680 { compatible = "zephyr,memory-region"; reg = <0x680 DT_SIZE_K(2)>; diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts index 8500d22a924..0251fbded25 100644 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts @@ -18,7 +18,7 @@ zephyr,console = &uart136; zephyr,code-partition = &cpuapp_slot0_partition; zephyr,flash = &mram1x; - zephyr,sram = &cpuapp_ram0; + zephyr,sram = &cpuapp_data; }; aliases { @@ -85,7 +85,11 @@ }; }; -&ram3x_dma_region { +&cpuapp_ram0x_region { + status = "okay"; +}; + +&shared_ram3x_region { status = "okay"; }; diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts index a7d142b06c4..d639847e197 100644 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts @@ -22,7 +22,7 @@ }; }; -&ram3x_dma_region { +&shared_ram3x_region { status = "okay"; }; From ae21f7bab3214817f0a612e5b7c7e4f9a93d087a Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Thu, 29 Feb 2024 11:49:37 +0100 Subject: [PATCH 0159/2402] boards: nrf54h20pdk: Add default IPC configuration Add `zephyr,ipc-icmsg*` nodes, with mboxes specified in a common file. Signed-off-by: Grzegorz Swiderski Signed-off-by: Gerard Marull-Partetas --- .../nrf54h20pdk_nrf54h20-ipc_conf.dtsi | 36 +++++++++++++++++++ .../nrf54h20pdk_nrf54h20_cpuapp.dts | 29 +++++++++++++++ .../nrf54h20pdk_nrf54h20_cpuppr.dts | 11 ++++++ .../nrf54h20pdk_nrf54h20_cpurad.dts | 24 +++++++++++++ 4 files changed, 100 insertions(+) create mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-ipc_conf.dtsi diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-ipc_conf.dtsi b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-ipc_conf.dtsi new file mode 100644 index 00000000000..9c3d971b9bc --- /dev/null +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-ipc_conf.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + ipc { + cpusec_cpuapp_ipc: ipc-1-2 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpusec_bellboard 12>, + <&cpuapp_bellboard 0>; + }; + + cpusec_cpurad_ipc: ipc-1-3 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpusec_bellboard 18>, + <&cpurad_bellboard 0>; + }; + + cpuapp_cpurad_ipc: ipc-2-3 { + status = "disabled"; + mboxes = <&cpuapp_bellboard 18>, + <&cpurad_bellboard 12>; + }; + + cpuapp_cpuppr_ipc: ipc-2-13 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpuapp_bellboard 13>, + <&cpuppr_vevif 12>; + }; + }; +}; diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts index 0251fbded25..b2db9e4b9b1 100644 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts @@ -8,8 +8,11 @@ #include #include "nrf54h20pdk_nrf54h20-memory_map.dtsi" +#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" #include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" +/delete-node/ &cpusec_cpurad_ipc; + / { compatible = "nordic,nrf54h20pdk_nrf54h20-cpuapp"; model = "Nordic nRF54H20 PDK nRF54H20 Application MCU"; @@ -93,6 +96,32 @@ status = "okay"; }; +&cpuapp_bellboard { + interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0"; + /* irq0: 0: cpuapp-cpusec, 13: cpuapp-cpuppr, 18: cpuapp-cpurad */ + nordic,interrupt-mapping = <0x00042001 0>; +}; + +&cpusec_cpuapp_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuapp_cpusec_ipc_shm>; + rx-region = <&cpusec_cpuapp_ipc_shm>; +}; + +&cpuapp_cpurad_ipc { + compatible = "zephyr,ipc-icmsg-me-initiator"; + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpurad_ipc_shm>; + rx-region = <&cpurad_cpuapp_ipc_shm>; +}; + +&cpuapp_cpuppr_ipc { + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpuppr_ipc_shm>; + rx-region = <&cpuppr_cpuapp_ipc_shm>; +}; + &cpuapp_dma_region { status = "okay"; }; diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts index 3c74e7c88d4..f98abb9e44b 100644 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts @@ -8,8 +8,13 @@ #include #include "nrf54h20pdk_nrf54h20-memory_map.dtsi" +#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" #include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" +/delete-node/ &cpuapp_cpurad_ipc; +/delete-node/ &cpusec_cpuapp_ipc; +/delete-node/ &cpusec_cpurad_ipc; + / { compatible = "nordic,nrf54h20pdk_nrf54h20-cpuppr"; model = "Nordic nRF54H20 PDK nRF54H20 Peripheral Processor MCU"; @@ -24,6 +29,12 @@ }; }; +&cpuapp_cpuppr_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuppr_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpuppr_ipc_shm>; +}; + &grtc { status = "okay"; owned-channels = <5>; diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts index d639847e197..8d2629df62e 100644 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts @@ -8,8 +8,12 @@ #include #include "nrf54h20pdk_nrf54h20-memory_map.dtsi" +#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" #include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" +/delete-node/ &cpuapp_cpuppr_ipc; +/delete-node/ &cpusec_cpuapp_ipc; + / { compatible = "nordic,nrf54h20pdk_nrf54h20-cpurad"; model = "Nordic nRF54H20 PDK nRF54H20 Radio MCU"; @@ -26,6 +30,26 @@ status = "okay"; }; +&cpurad_bellboard { + interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0"; + /* irq0: 0: cpurad-cpusec, 12: cpurad-cpuapp */ + nordic,interrupt-mapping = <0x00001001 0>; +}; + +&cpusec_cpurad_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpurad_cpusec_ipc_shm>; + rx-region = <&cpusec_cpurad_ipc_shm>; +}; + +&cpuapp_cpurad_ipc { + compatible = "zephyr,ipc-icmsg-me-follower"; + mbox-names = "tx", "rx"; + tx-region = <&cpurad_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpurad_ipc_shm>; +}; + &cpurad_dma_region { status = "okay"; }; From d23ea62be9e9763782c62bf99b1246cce19d843a Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 21 Feb 2024 17:33:24 +0100 Subject: [PATCH 0160/2402] drivers: misc: nordic_vpr_launcher: initialize earlier Set driver to initialize at early POST_KERNEL, so that we make sure other future dependencies priorities (eg VEVIF) do not conflict. Signed-off-by: Gerard Marull-Paretas --- drivers/misc/nordic_vpr_launcher/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/nordic_vpr_launcher/Kconfig b/drivers/misc/nordic_vpr_launcher/Kconfig index 57605e505f2..6aeabcd251c 100644 --- a/drivers/misc/nordic_vpr_launcher/Kconfig +++ b/drivers/misc/nordic_vpr_launcher/Kconfig @@ -17,7 +17,7 @@ source "subsys/logging/Kconfig.template.log_config" config NORDIC_VPR_LAUNCHER_INIT_PRIORITY int "Nordic VPR coprocessor launcher init priority" - default KERNEL_INIT_PRIORITY_DEVICE + default 0 help The init priority of the VPR coprocessor launcher. From 78c40fe31bf2a7f702fa575d1927e8bff7c4a4e1 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 21 Feb 2024 16:16:58 +0100 Subject: [PATCH 0161/2402] drivers: mbox: add initial driver for nRF VEVIF Add a mailbox driver for VEVIF. The driver can be built in either 'local' or 'remote' configuration. This depends on the existence of the 'interrupts' property, which signals that the instance is managed locally. VEVIF is, as expected, always managed by a VPR core. Signed-off-by: Gerard Marull-Paretas --- drivers/mbox/CMakeLists.txt | 2 + drivers/mbox/Kconfig | 1 + drivers/mbox/Kconfig.nrf_vevif | 16 ++++ drivers/mbox/mbox_nrf_vevif_local.c | 123 +++++++++++++++++++++++++++ drivers/mbox/mbox_nrf_vevif_remote.c | 76 +++++++++++++++++ 5 files changed, 218 insertions(+) create mode 100644 drivers/mbox/Kconfig.nrf_vevif create mode 100644 drivers/mbox/mbox_nrf_vevif_local.c create mode 100644 drivers/mbox/mbox_nrf_vevif_remote.c diff --git a/drivers/mbox/CMakeLists.txt b/drivers/mbox/CMakeLists.txt index 89e5d58e65c..b8e28afe6b4 100644 --- a/drivers/mbox/CMakeLists.txt +++ b/drivers/mbox/CMakeLists.txt @@ -10,3 +10,5 @@ zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_S32_MRU mbox_nxp_s32_mru.c) zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_IMX_MU mbox_nxp_imx_mu.c) zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_MAILBOX mbox_nxp_mailbox.c) zephyr_library_sources_ifdef(CONFIG_MBOX_ANDES_PLIC_SW mbox_andes_plic_sw.c) +zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_VEVIF_LOCAL mbox_nrf_vevif_local.c) +zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_VEVIF_REMOTE mbox_nrf_vevif_remote.c) diff --git a/drivers/mbox/Kconfig b/drivers/mbox/Kconfig index 67041e91f59..c6fe36832c9 100644 --- a/drivers/mbox/Kconfig +++ b/drivers/mbox/Kconfig @@ -17,6 +17,7 @@ source "drivers/mbox/Kconfig.nxp_s32" source "drivers/mbox/Kconfig.nxp_imx" source "drivers/mbox/Kconfig.nxp_mailbox" source "drivers/mbox/Kconfig.andes" +source "drivers/mbox/Kconfig.nrf_vevif" config MBOX_INIT_PRIORITY int "MBOX init priority" diff --git a/drivers/mbox/Kconfig.nrf_vevif b/drivers/mbox/Kconfig.nrf_vevif new file mode 100644 index 00000000000..4abb0ef8241 --- /dev/null +++ b/drivers/mbox/Kconfig.nrf_vevif @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config MBOX_NRF_VEVIF_LOCAL + bool "nRF VEVIF local driver" + depends on DT_HAS_NORDIC_NRF_VEVIF_LOCAL_ENABLED + default y + help + Mailbox driver for local Nordic nRF VEVIF (VPR Event Interface) + +config MBOX_NRF_VEVIF_REMOTE + bool "nRF VEVIF remote driver" + depends on DT_HAS_NORDIC_NRF_VEVIF_REMOTE_ENABLED + default y + help + Mailbox driver for remote Nordic nRF VEVIF (VPR Event Interface) diff --git a/drivers/mbox/mbox_nrf_vevif_local.c b/drivers/mbox/mbox_nrf_vevif_local.c new file mode 100644 index 00000000000..31b89e1e6fb --- /dev/null +++ b/drivers/mbox/mbox_nrf_vevif_local.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nordic_nrf_vevif_local + +#include +#include + +#include +#include +#include + +#define VEVIF_TASKS_NUM DT_INST_PROP(0, nordic_tasks) +#define VEVIF_TASKS_MASK DT_INST_PROP(0, nordic_tasks_mask) + +BUILD_ASSERT(VEVIF_TASKS_NUM <= VPR_TASKS_TRIGGER_MaxCount, "Number of tasks exceeds maximum"); +BUILD_ASSERT(VEVIF_TASKS_NUM == DT_NUM_IRQS(DT_DRV_INST(0)), "# IRQs != # tasks"); + +/* callbacks */ +struct mbox_vevif_local_cbs { + mbox_callback_t cb[VEVIF_TASKS_NUM]; + void *user_data[VEVIF_TASKS_NUM]; + uint32_t enabled_mask; +}; + +static struct mbox_vevif_local_cbs cbs; + +/* IRQ list */ +#define VEVIF_IRQN(idx, _) DT_INST_IRQ_BY_IDX(0, idx, irq) + +static const uint8_t vevif_irqs[VEVIF_TASKS_NUM] = { + LISTIFY(DT_NUM_IRQS(DT_DRV_INST(0)), VEVIF_IRQN, (,)) +}; + +static void vevif_local_isr(const void *parameter) +{ + uint8_t id = *(uint8_t *)parameter; + + nrf_vpr_csr_vevif_tasks_clear(BIT(id)); + + if (cbs.cb[id] != NULL) { + cbs.cb[id](DEVICE_DT_INST_GET(0), id, cbs.user_data[id], NULL); + } +} + +static inline bool vevif_local_is_task_valid(uint32_t id) +{ + return (id < VEVIF_TASKS_NUM) && ((VEVIF_TASKS_MASK & BIT(id)) != 0U); +} + +static uint32_t vevif_local_max_channels_get(const struct device *dev) +{ + ARG_UNUSED(dev); + + return VEVIF_TASKS_NUM; +} + +static int vevif_local_register_callback(const struct device *dev, uint32_t id, mbox_callback_t cb, + void *user_data) +{ + ARG_UNUSED(dev); + + if (!vevif_local_is_task_valid(id)) { + return -EINVAL; + } + + cbs.cb[id] = cb; + cbs.user_data[id] = user_data; + + return 0; +} + +static int vevif_local_set_enabled(const struct device *dev, uint32_t id, bool enable) +{ + ARG_UNUSED(dev); + + if (!vevif_local_is_task_valid(id)) { + return -EINVAL; + } + + if (enable) { + if ((cbs.enabled_mask & BIT(id)) != 0U) { + return -EALREADY; + } + + cbs.enabled_mask |= BIT(id); + irq_enable(vevif_irqs[id]); + } else { + if ((cbs.enabled_mask & BIT(id)) == 0U) { + return -EALREADY; + } + + cbs.enabled_mask &= ~BIT(id); + irq_disable(vevif_irqs[id]); + } + + return 0; +} + +static const struct mbox_driver_api vevif_local_driver_api = { + .max_channels_get = vevif_local_max_channels_get, + .register_callback = vevif_local_register_callback, + .set_enabled = vevif_local_set_enabled, +}; + +#define VEVIF_IRQ_CONNECT(idx, _) \ + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, idx, irq), DT_INST_IRQ_BY_IDX(0, idx, priority), \ + vevif_local_isr, &vevif_irqs[idx], 0) + +static int vevif_local_init(const struct device *dev) +{ + nrf_vpr_csr_rtperiph_enable_set(true); + nrf_vpr_csr_vevif_tasks_clear(NRF_VPR_TASK_TRIGGER_ALL_MASK); + + LISTIFY(DT_NUM_IRQS(DT_DRV_INST(0)), VEVIF_IRQ_CONNECT, (;)); + + return 0; +} + +DEVICE_DT_INST_DEFINE(0, vevif_local_init, NULL, NULL, NULL, POST_KERNEL, CONFIG_MBOX_INIT_PRIORITY, + &vevif_local_driver_api); diff --git a/drivers/mbox/mbox_nrf_vevif_remote.c b/drivers/mbox/mbox_nrf_vevif_remote.c new file mode 100644 index 00000000000..cb5d7c507c5 --- /dev/null +++ b/drivers/mbox/mbox_nrf_vevif_remote.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nordic_nrf_vevif_remote + +#include +#include + +#include + +struct mbox_vevif_remote_conf { + NRF_VPR_Type *vpr; + uint32_t tasks_mask; + uint8_t tasks; +}; + +static inline bool vevif_remote_is_task_valid(const struct device *dev, uint32_t id) +{ + const struct mbox_vevif_remote_conf *config = dev->config; + + return (id < config->tasks) && ((config->tasks_mask & BIT(id)) != 0U); +} + +static int vevif_remote_send(const struct device *dev, uint32_t id, const struct mbox_msg *msg) +{ + const struct mbox_vevif_remote_conf *config = dev->config; + + if (!vevif_remote_is_task_valid(dev, id)) { + return -EINVAL; + } + + if (msg != NULL) { + return -ENOTSUP; + } + + nrfy_vpr_task_trigger(config->vpr, nrfy_vpr_trigger_task_get(id)); + + return 0; +} + +static int vevif_remote_mtu_get(const struct device *dev) +{ + ARG_UNUSED(dev); + + return 0; +} + +static uint32_t vevif_remote_max_channels_get(const struct device *dev) +{ + const struct mbox_vevif_remote_conf *config = dev->config; + + return config->tasks; +} + +static const struct mbox_driver_api vevif_remote_driver_api = { + .send = vevif_remote_send, + .mtu_get = vevif_remote_mtu_get, + .max_channels_get = vevif_remote_max_channels_get, +}; + +#define VEVIF_REMOTE_DEFINE(inst) \ + BUILD_ASSERT(DT_INST_PROP(inst, nordic_tasks) <= VPR_TASKS_TRIGGER_MaxCount, \ + "Number of tasks exceeds maximum"); \ + \ + static const struct mbox_vevif_remote_conf conf##inst = { \ + .vpr = (NRF_VPR_Type *)DT_INST_REG_ADDR(inst), \ + .tasks = DT_INST_PROP(inst, nordic_tasks), \ + .tasks_mask = DT_INST_PROP(inst, nordic_tasks_mask), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(inst, NULL, NULL, NULL, &conf##inst, POST_KERNEL, \ + CONFIG_MBOX_INIT_PRIORITY, &vevif_remote_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(VEVIF_REMOTE_DEFINE) From b7378bbd14534e48b38cb9b31bfb5aa08f76a15c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 21 Feb 2024 17:42:14 +0100 Subject: [PATCH 0162/2402] samples: drivers: mbox: allow to configure RX/TX channels By adding Kconfig options for both samples. Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/Kconfig | 13 +++++++++++++ samples/drivers/mbox/remote/Kconfig | 17 +++++++++++++++++ samples/drivers/mbox/remote/src/main.c | 7 ++----- samples/drivers/mbox/src/main.c | 7 ++----- 4 files changed, 34 insertions(+), 10 deletions(-) create mode 100644 samples/drivers/mbox/remote/Kconfig diff --git a/samples/drivers/mbox/Kconfig b/samples/drivers/mbox/Kconfig index 3837c49b6e9..79dd2d09689 100644 --- a/samples/drivers/mbox/Kconfig +++ b/samples/drivers/mbox/Kconfig @@ -9,3 +9,16 @@ config INCLUDE_REMOTE_DIR help Include remote build header files. Can be used if primary image needs to be aware of size or base address of secondary image + +config TX_CHANNEL_ID + int "Channel ID for TX" + default 1 + help + Channel ID for TX + + +config RX_CHANNEL_ID + int "Channel ID for RX" + default 0 + help + Channel ID for RX diff --git a/samples/drivers/mbox/remote/Kconfig b/samples/drivers/mbox/remote/Kconfig new file mode 100644 index 00000000000..a8897e4aab0 --- /dev/null +++ b/samples/drivers/mbox/remote/Kconfig @@ -0,0 +1,17 @@ +# Copyright 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +source "Kconfig.zephyr" + +config TX_CHANNEL_ID + int "Channel ID for TX" + default 0 + help + Channel ID for TX + + +config RX_CHANNEL_ID + int "Channel ID for RX" + default 1 + help + Channel ID for RX diff --git a/samples/drivers/mbox/remote/src/main.c b/samples/drivers/mbox/remote/src/main.c index 89039e3b277..a256ed21daa 100644 --- a/samples/drivers/mbox/remote/src/main.c +++ b/samples/drivers/mbox/remote/src/main.c @@ -9,9 +9,6 @@ #include #include -#define TX_ID (0) -#define RX_ID (1) - static void callback(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data) { @@ -28,8 +25,8 @@ int main(void) dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); - mbox_init_channel(&tx_channel, dev, TX_ID); - mbox_init_channel(&rx_channel, dev, RX_ID); + mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); + mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); if (mbox_register_callback(&rx_channel, callback, NULL)) { printk("mbox_register_callback() error\n"); diff --git a/samples/drivers/mbox/src/main.c b/samples/drivers/mbox/src/main.c index d6c79729b4f..bfe28443f95 100644 --- a/samples/drivers/mbox/src/main.c +++ b/samples/drivers/mbox/src/main.c @@ -9,9 +9,6 @@ #include #include -#define TX_ID (1) -#define RX_ID (0) - static void callback(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data) { @@ -28,8 +25,8 @@ int main(void) dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); - mbox_init_channel(&tx_channel, dev, TX_ID); - mbox_init_channel(&rx_channel, dev, RX_ID); + mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); + mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); if (mbox_register_callback(&rx_channel, callback, NULL)) { printk("mbox_register_callback() error\n"); From d3624a2d4ad38cd6c7a5246314a8d01a43646efb Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 21 Feb 2024 17:48:59 +0100 Subject: [PATCH 0163/2402] samples: drivers: mbox: allow to enable RX/TX This can be useful to provide multiple setups, eg unidirectional ping-pong. Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/Kconfig | 13 +++++++++++++ samples/drivers/mbox/remote/Kconfig | 13 +++++++++++++ samples/drivers/mbox/remote/src/main.c | 20 +++++++++++++++++--- samples/drivers/mbox/src/main.c | 15 ++++++++++++--- 4 files changed, 55 insertions(+), 6 deletions(-) diff --git a/samples/drivers/mbox/Kconfig b/samples/drivers/mbox/Kconfig index 79dd2d09689..3af6e740bfc 100644 --- a/samples/drivers/mbox/Kconfig +++ b/samples/drivers/mbox/Kconfig @@ -10,15 +10,28 @@ config INCLUDE_REMOTE_DIR Include remote build header files. Can be used if primary image needs to be aware of size or base address of secondary image +config TX_ENABLED + bool "TX enabled" + default y + help + Enable TX + config TX_CHANNEL_ID int "Channel ID for TX" default 1 + depends on TX_ENABLED help Channel ID for TX +config RX_ENABLED + bool "RX enabled" + default y + help + Enable RX config RX_CHANNEL_ID int "Channel ID for RX" + depends on RX_ENABLED default 0 help Channel ID for RX diff --git a/samples/drivers/mbox/remote/Kconfig b/samples/drivers/mbox/remote/Kconfig index a8897e4aab0..7edb8574359 100644 --- a/samples/drivers/mbox/remote/Kconfig +++ b/samples/drivers/mbox/remote/Kconfig @@ -3,15 +3,28 @@ source "Kconfig.zephyr" +config TX_ENABLED + bool "TX enabled" + default y + help + Enable TX + config TX_CHANNEL_ID int "Channel ID for TX" default 0 + depends on TX_ENABLED help Channel ID for TX +config RX_ENABLED + bool "RX enabled" + default y + help + Enable RX config RX_CHANNEL_ID int "Channel ID for RX" + depends on RX_ENABLED default 1 help Channel ID for RX diff --git a/samples/drivers/mbox/remote/src/main.c b/samples/drivers/mbox/remote/src/main.c index a256ed21daa..31665951172 100644 --- a/samples/drivers/mbox/remote/src/main.c +++ b/samples/drivers/mbox/remote/src/main.c @@ -9,23 +9,29 @@ #include #include +#if !defined(CONFIG_RX_ENABLED) && !defined(CONFIG_TX_ENABLED) +#error "At least one of CONFIG_RX_ENABLED or CONFIG_TX_ENABLED must be set" +#endif + +#ifdef CONFIG_RX_ENABLED static void callback(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data) { printk("Pong (on channel %d)\n", channel); } +#endif /* CONFIG_RX_ENABLED */ int main(void) { - struct mbox_channel tx_channel; - struct mbox_channel rx_channel; const struct device *dev; printk("Hello from NET\n"); dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); - mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); +#ifdef CONFIG_RX_ENABLED + struct mbox_channel rx_channel; + mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); if (mbox_register_callback(&rx_channel, callback, NULL)) { @@ -37,6 +43,12 @@ int main(void) printk("mbox_set_enable() error\n"); return 0; } +#endif /* CONFIG_RX_ENABLED */ + +#ifdef CONFIG_TX_ENABLED + struct mbox_channel tx_channel; + + mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); while (1) { @@ -49,5 +61,7 @@ int main(void) k_sleep(K_MSEC(3000)); } +#endif /* CONFIG_TX_ENABLED */ + return 0; } diff --git a/samples/drivers/mbox/src/main.c b/samples/drivers/mbox/src/main.c index bfe28443f95..cea34afb29a 100644 --- a/samples/drivers/mbox/src/main.c +++ b/samples/drivers/mbox/src/main.c @@ -9,23 +9,25 @@ #include #include +#ifdef CONFIG_RX_ENABLED static void callback(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data) { printk("Pong (on channel %d)\n", channel); } +#endif int main(void) { - struct mbox_channel tx_channel; - struct mbox_channel rx_channel; const struct device *dev; printk("Hello from APP\n"); dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); - mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); +#ifdef CONFIG_RX_ENABLED + struct mbox_channel rx_channel; + mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); if (mbox_register_callback(&rx_channel, callback, NULL)) { @@ -37,6 +39,12 @@ int main(void) printk("mbox_set_enable() error\n"); return 0; } +#endif /* CONFIG_RX_ENABLED */ + +#ifdef CONFIG_TX_ENABLED + struct mbox_channel tx_channel; + + mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); while (1) { k_sleep(K_MSEC(2000)); @@ -48,5 +56,6 @@ int main(void) return 0; } } +#endif /* CONFIG_TX_ENABLED */ return 0; } From caeedb4663949ecb95c2453b4aada0e9f93332e7 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 21 Feb 2024 17:59:22 +0100 Subject: [PATCH 0164/2402] samples: drivers: mbox: misc cleanups/enhancements - Include cleanup - s/NET/REMOTE (remote core may have nothing to do with NET) - Improved error reporting Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/remote/src/main.c | 26 +++++++++++++------------- samples/drivers/mbox/src/main.c | 23 ++++++++++++----------- 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/samples/drivers/mbox/remote/src/main.c b/samples/drivers/mbox/remote/src/main.c index 31665951172..1ca832a697c 100644 --- a/samples/drivers/mbox/remote/src/main.c +++ b/samples/drivers/mbox/remote/src/main.c @@ -4,10 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include -#include #include #include +#include #if !defined(CONFIG_RX_ENABLED) && !defined(CONFIG_TX_ENABLED) #error "At least one of CONFIG_RX_ENABLED or CONFIG_TX_ENABLED must be set" @@ -23,24 +22,25 @@ static void callback(const struct device *dev, uint32_t channel, int main(void) { - const struct device *dev; + int ret; + const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); - printk("Hello from NET\n"); - - dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); + printk("Hello from REMOTE\n"); #ifdef CONFIG_RX_ENABLED struct mbox_channel rx_channel; mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); - if (mbox_register_callback(&rx_channel, callback, NULL)) { - printk("mbox_register_callback() error\n"); + ret = mbox_register_callback(&rx_channel, callback, NULL); + if (ret < 0) { + printk("Could not register callback (%d)\n", ret); return 0; } - if (mbox_set_enabled(&rx_channel, 1)) { - printk("mbox_set_enable() error\n"); + ret = mbox_set_enabled(&rx_channel, true); + if (ret < 0) { + printk("Could not enable RX channel %d (%d)\n", rx_channel.id, ret); return 0; } #endif /* CONFIG_RX_ENABLED */ @@ -51,11 +51,11 @@ int main(void) mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); while (1) { - printk("Ping (on channel %d)\n", tx_channel.id); - if (mbox_send(&tx_channel, NULL) < 0) { - printk("mbox_send() error\n"); + ret = mbox_send(&tx_channel, NULL); + if (ret < 0) { + printk("Could not send (%d)\n", ret); return 0; } diff --git a/samples/drivers/mbox/src/main.c b/samples/drivers/mbox/src/main.c index cea34afb29a..d4dd21d342f 100644 --- a/samples/drivers/mbox/src/main.c +++ b/samples/drivers/mbox/src/main.c @@ -4,10 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include -#include #include #include +#include #ifdef CONFIG_RX_ENABLED static void callback(const struct device *dev, uint32_t channel, @@ -19,24 +18,25 @@ static void callback(const struct device *dev, uint32_t channel, int main(void) { - const struct device *dev; + int ret; + const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); printk("Hello from APP\n"); - dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); - #ifdef CONFIG_RX_ENABLED struct mbox_channel rx_channel; mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); - if (mbox_register_callback(&rx_channel, callback, NULL)) { - printk("mbox_register_callback() error\n"); + ret = mbox_register_callback(&rx_channel, callback, NULL); + if (ret < 0) { + printk("Could not register callback (%d)\n", ret); return 0; } - if (mbox_set_enabled(&rx_channel, 1)) { - printk("mbox_set_enable() error\n"); + ret = mbox_set_enabled(&rx_channel, true); + if (ret < 0) { + printk("Could not enable RX channel %d (%d)\n", rx_channel.id, ret); return 0; } #endif /* CONFIG_RX_ENABLED */ @@ -51,8 +51,9 @@ int main(void) printk("Ping (on channel %d)\n", tx_channel.id); - if (mbox_send(&tx_channel, NULL) < 0) { - printk("mbox_send() error\n"); + ret = mbox_send(&tx_channel, NULL); + if (ret < 0) { + printk("Could not send (%d)\n", ret); return 0; } } From 5715691562e0a6bd78d30d7d10f91b9267bdf8b3 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 21 Feb 2024 17:36:43 +0100 Subject: [PATCH 0165/2402] samples: drivers: mbox: add support for nRF VEVIF Add support for nRF VEVIF. Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/CMakeLists.txt | 3 ++- samples/drivers/mbox/Kconfig.sysbuild | 1 + .../nrf54h20pdk_nrf54h20_cpuapp_vevif.conf | 2 ++ .../nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay | 8 +++++++ samples/drivers/mbox/remote/CMakeLists.txt | 3 ++- .../nrf54h20pdk_nrf54h20_cpuppr_vevif.conf | 2 ++ .../nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay | 8 +++++++ samples/drivers/mbox/sample.yaml | 21 +++++++++++++++++++ 8 files changed, 46 insertions(+), 2 deletions(-) create mode 100644 samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf create mode 100644 samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay create mode 100644 samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf create mode 100644 samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay diff --git a/samples/drivers/mbox/CMakeLists.txt b/samples/drivers/mbox/CMakeLists.txt index 382aefad0dd..6b54d013431 100644 --- a/samples/drivers/mbox/CMakeLists.txt +++ b/samples/drivers/mbox/CMakeLists.txt @@ -17,7 +17,8 @@ if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "mimxrt1170_evkb") OR ("${BOARD}" STREQUAL "mimxrt1170_evk") OR ("${BOARD}" STREQUAL "mimxrt1160_evk") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69")) + ("${BOARD}" STREQUAL "lpcxpresso55s69") OR + ("${BOARD}" STREQUAL "nrf54h20pdk")) message(STATUS "${BOARD} compile as Main in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/Kconfig.sysbuild b/samples/drivers/mbox/Kconfig.sysbuild index 53f83ddeb9e..9dfa36077ee 100644 --- a/samples/drivers/mbox/Kconfig.sysbuild +++ b/samples/drivers/mbox/Kconfig.sysbuild @@ -14,3 +14,4 @@ string default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" + default "nrf54h20pdk/nrf54h20/cpuppr" if $(BOARD) = "nrf54h20pdk" diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf new file mode 100644 index 00000000000..d8d66e9812d --- /dev/null +++ b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf @@ -0,0 +1,2 @@ +CONFIG_RX_ENABLED=n +CONFIG_TX_CHANNEL_ID=4 diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay new file mode 100644 index 00000000000..ed631f04cc3 --- /dev/null +++ b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay @@ -0,0 +1,8 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +mbox: &cpuppr_vevif { + status = "okay"; +}; diff --git a/samples/drivers/mbox/remote/CMakeLists.txt b/samples/drivers/mbox/remote/CMakeLists.txt index 5fbec71ce41..d0ba1a94e57 100644 --- a/samples/drivers/mbox/remote/CMakeLists.txt +++ b/samples/drivers/mbox/remote/CMakeLists.txt @@ -15,7 +15,8 @@ if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "mimxrt1170_evk") OR ("${BOARD}" STREQUAL "mimxrt1160_evk") OR ("${BOARD}" STREQUAL "lpcxpresso55s69") OR - ("${BOARD}" STREQUAL "adp_xc7k")) + ("${BOARD}" STREQUAL "adp_xc7k") OR + ("${BOARD}" STREQUAL "nrf54h20pdk")) message(STATUS "${BOARD} compile as remote in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf new file mode 100644 index 00000000000..19e03b75c63 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf @@ -0,0 +1,2 @@ +CONFIG_TX_ENABLED=n +CONFIG_RX_CHANNEL_ID=4 diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay new file mode 100644 index 00000000000..ed631f04cc3 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay @@ -0,0 +1,8 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +mbox: &cpuppr_vevif { + status = "okay"; +}; diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml index 1e0feb4e3f0..b2aaa8d36fa 100644 --- a/samples/drivers/mbox/sample.yaml +++ b/samples/drivers/mbox/sample.yaml @@ -23,6 +23,27 @@ tests: - "Pong \\(on channel 0\\)" - "Ping \\(on channel 1\\)" - "Pong \\(on channel 1\\)" + + sample.drivers.mbox.nrf54h20_vevif: + platform_allow: + - nrf54h20pdk/nrf54h20/cpuapp + integration_platforms: + - nrf54h20pdk/nrf54h20/cpuapp + extra_args: + mbox_SNIPPET=nordic-ppr + mbox_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf + mbox_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay + remote_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf + remote_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay + sysbuild: true + harness: console + harness_config: + type: multi_line + ordered: false + regex: + - "Ping \\(on channel 4\\)" + - "Pong \\(on channel 4\\)" + sample.drivers.mbox.simu: platform_allow: - nrf5340bsim_nrf5340_cpuapp From ffaa9077eb4161769eba80e49c155f3aff0ea810 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Thu, 22 Feb 2024 16:23:08 +0100 Subject: [PATCH 0166/2402] dts: bindings: mbox: add nordic,nrf-bellboard-local|remote Add new bindings to describe the BELLBOARD peripheral in its two _programming modes_ local or remote. Signed-off-by: Gerard Marull-Paretas --- .../mbox/nordic,nrf-bellboard-common.yaml | 11 +++++ .../mbox/nordic,nrf-bellboard-local.yaml | 43 +++++++++++++++++++ .../mbox/nordic,nrf-bellboard-remote.yaml | 22 ++++++++++ 3 files changed, 76 insertions(+) create mode 100644 dts/bindings/mbox/nordic,nrf-bellboard-common.yaml create mode 100644 dts/bindings/mbox/nordic,nrf-bellboard-local.yaml create mode 100644 dts/bindings/mbox/nordic,nrf-bellboard-remote.yaml diff --git a/dts/bindings/mbox/nordic,nrf-bellboard-common.yaml b/dts/bindings/mbox/nordic,nrf-bellboard-common.yaml new file mode 100644 index 00000000000..0d1d0bc26e2 --- /dev/null +++ b/dts/bindings/mbox/nordic,nrf-bellboard-common.yaml @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +include: [base.yaml, "mailbox-controller.yaml"] + +properties: + reg: + required: true + +mbox-cells: + - channel diff --git a/dts/bindings/mbox/nordic,nrf-bellboard-local.yaml b/dts/bindings/mbox/nordic,nrf-bellboard-local.yaml new file mode 100644 index 00000000000..5c1709987cc --- /dev/null +++ b/dts/bindings/mbox/nordic,nrf-bellboard-local.yaml @@ -0,0 +1,43 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: | + Nordic BELLBOARD + + BELLBOARD provides support for inter-domain software signaling. It implements + a set of tasks and events intended for signaling within an interprocessor + communication (IPC) framework. When used in local mode, the BELLBOARD + instance is used to receive events triggered by other remote cores. + + Example definition: + + bellboard: mailbox@deadbeef { + compatible = "nordic,nrf-bellboard-local"; + reg = <0xdeadbeef 0x1000>; + interrupts = <98 NRF_DEFAULT_IRQ_PRIORITY>, + <99 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq2", "irq3"; + nordic,interrupt-mapping = <0x0000000f 2>, <0x000000f0 3>; + #mbox-cells = <1>; + }; + +compatible: "nordic,nrf-bellboard-local" + +include: "nordic,nrf-bellboard-common.yaml" + +properties: + interrupts: + required: true + + interrupt-names: + required: true + + nordic,interrupt-mapping: + type: array + required: true + description: | + Set of interrupt mapping pairs. Each pair consists of a bitmask and an + interrupt identifier. The bitmask is used to indicate which of the 32 + possible events are mapped to the given interrupt. For example, given + <0x0000000f 2>, the first four events are mapped to interrupt 2 + (irq2). diff --git a/dts/bindings/mbox/nordic,nrf-bellboard-remote.yaml b/dts/bindings/mbox/nordic,nrf-bellboard-remote.yaml new file mode 100644 index 00000000000..ae17fc916a1 --- /dev/null +++ b/dts/bindings/mbox/nordic,nrf-bellboard-remote.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: | + Nordic BELLBOARD + + BELLBOARD provides support for inter-domain software signaling. It implements + a set of tasks and events intended for signaling within an interprocessor + communication (IPC) framework. When used in remote mode, the BELLBOARD + instance is used to trigger events to another core. + + Example definition: + + bellboard: mailbox@deadbeef { + compatible = "nordic,nrf-bellboard-remote"; + reg = <0xdeadbeef 0x1000>; + #mbox-cells = <1>; + }; + +compatible: "nordic,nrf-bellboard-remote" + +include: "nordic,nrf-bellboard-common.yaml" From dec5ab382f484c042e02513550d9afa48fa34fa3 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Thu, 22 Feb 2024 16:24:14 +0100 Subject: [PATCH 0167/2402] dts: nordic: nrf54h20_enga: add BELLBOARD nodes Add nodes for APP/RAD BELLBOARD peripherals. Signed-off-by: Gerard Marull-Paretas --- dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi | 12 ++++++++++++ dts/arm/nordic/nrf54h20_enga_cpurad.dtsi | 12 ++++++++++++ dts/common/nordic/nrf54h20_enga.dtsi | 18 ++++++++++++++++++ dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi | 12 ++++++++++++ 4 files changed, 54 insertions(+) diff --git a/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi b/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi index c7a52a00296..7252b3d5a04 100644 --- a/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi +++ b/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi @@ -30,6 +30,18 @@ cpuppr_vevif: &cpuppr_vevif_remote {}; ranges; }; +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-local"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + &gpiote130 { interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; }; diff --git a/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi b/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi index 952f3c00ced..d2aaa790349 100644 --- a/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi +++ b/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi @@ -30,6 +30,18 @@ cpuppr_vevif: &cpuppr_vevif_remote {}; ranges; }; +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-local"; +}; + &gpiote130 { interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; }; diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi index b9ac3d7d0bf..610fbd81587 100644 --- a/dts/common/nordic/nrf54h20_enga.dtsi +++ b/dts/common/nordic/nrf54h20_enga.dtsi @@ -248,6 +248,24 @@ #size-cells = <1>; ranges = <0x0 0x5f000000 0x1000000>; + cpusec_bellboard: mailbox@99000 { + reg = <0x99000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + cpuapp_bellboard: mailbox@9a000 { + reg = <0x9a000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + cpurad_bellboard: mailbox@9b000 { + reg = <0x9b000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + timer120: timer@8e2000 { compatible = "nordic,nrf-timer"; reg = <0x8e2000 0x1000>; diff --git a/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi b/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi index d96956b7b73..0af6618688f 100644 --- a/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi +++ b/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi @@ -27,6 +27,18 @@ cpuppr_vevif: &cpuppr_vevif_local {}; }; }; +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + &gpiote130 { interrupts = <104 NRF_DEFAULT_IRQ_PRIORITY>; }; From 0b38425f6d2ace1781205507a0a30e786472c995 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Thu, 22 Feb 2024 16:26:00 +0100 Subject: [PATCH 0168/2402] drivers: mbox: nrf_bellboard: add initial driver Add a new driver for nRF BELLBOARD peripheral, in both local and remote modes. Signed-off-by: Gerard Marull-Paretas --- drivers/mbox/CMakeLists.txt | 2 + drivers/mbox/Kconfig | 1 + drivers/mbox/Kconfig.nrf_bellboard | 16 +++ drivers/mbox/mbox_nrf_bellboard_local.c | 169 +++++++++++++++++++++++ drivers/mbox/mbox_nrf_bellboard_remote.c | 62 +++++++++ 5 files changed, 250 insertions(+) create mode 100644 drivers/mbox/Kconfig.nrf_bellboard create mode 100644 drivers/mbox/mbox_nrf_bellboard_local.c create mode 100644 drivers/mbox/mbox_nrf_bellboard_remote.c diff --git a/drivers/mbox/CMakeLists.txt b/drivers/mbox/CMakeLists.txt index b8e28afe6b4..1d5c65cded7 100644 --- a/drivers/mbox/CMakeLists.txt +++ b/drivers/mbox/CMakeLists.txt @@ -12,3 +12,5 @@ zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_MAILBOX mbox_nxp_mailbox.c) zephyr_library_sources_ifdef(CONFIG_MBOX_ANDES_PLIC_SW mbox_andes_plic_sw.c) zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_VEVIF_LOCAL mbox_nrf_vevif_local.c) zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_VEVIF_REMOTE mbox_nrf_vevif_remote.c) +zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_BELLBOARD_LOCAL mbox_nrf_bellboard_local.c) +zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_BELLBOARD_REMOTE mbox_nrf_bellboard_remote.c) diff --git a/drivers/mbox/Kconfig b/drivers/mbox/Kconfig index c6fe36832c9..7f00324ba47 100644 --- a/drivers/mbox/Kconfig +++ b/drivers/mbox/Kconfig @@ -18,6 +18,7 @@ source "drivers/mbox/Kconfig.nxp_imx" source "drivers/mbox/Kconfig.nxp_mailbox" source "drivers/mbox/Kconfig.andes" source "drivers/mbox/Kconfig.nrf_vevif" +source "drivers/mbox/Kconfig.nrf_bellboard" config MBOX_INIT_PRIORITY int "MBOX init priority" diff --git a/drivers/mbox/Kconfig.nrf_bellboard b/drivers/mbox/Kconfig.nrf_bellboard new file mode 100644 index 00000000000..45233122bd5 --- /dev/null +++ b/drivers/mbox/Kconfig.nrf_bellboard @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config MBOX_NRF_BELLBOARD_LOCAL + bool "nRF BELLBOARD local driver" + depends on DT_HAS_NORDIC_NRF_BELLBOARD_LOCAL_ENABLED + default y + help + Mailbox driver for local Nordic nRF BELLBOARD + +config MBOX_NRF_BELLBOARD_REMOTE + bool "nRF BELLBOARD remote driver" + depends on DT_HAS_NORDIC_NRF_BELLBOARD_REMOTE_ENABLED + default y + help + Mailbox driver for remote Nordic nRF BELLBOARD diff --git a/drivers/mbox/mbox_nrf_bellboard_local.c b/drivers/mbox/mbox_nrf_bellboard_local.c new file mode 100644 index 00000000000..99d05351aaa --- /dev/null +++ b/drivers/mbox/mbox_nrf_bellboard_local.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nordic_nrf_bellboard_local + +#include +#include +#include + +#include + +#define BELLBOARD_NUM_IRQS 4U + +BUILD_ASSERT(DT_NUM_IRQS(DT_DRV_INST(0)) <= BELLBOARD_NUM_IRQS, "# interrupt exceeds maximum"); + +BUILD_ASSERT((DT_INST_PROP_LEN(0, nordic_interrupt_mapping) % 2) == 0, + "# interrupt mappings not specified in pairs"); + +/* BELLBOARD event mappings */ +#define EVT_MAPPING_ITEM(idx) DT_INST_PROP_BY_IDX(0, nordic_interrupt_mapping, idx) +#define BELLBOARD_GET_EVT_MAPPING(idx, _) \ + COND_CODE_1( \ + DT_INST_PROP_HAS_IDX(0, nordic_interrupt_mapping, UTIL_INC(UTIL_X2(idx))), \ + ([EVT_MAPPING_ITEM(UTIL_INC(UTIL_X2(idx)))] = EVT_MAPPING_ITEM(UTIL_X2(idx)),), \ + ()) + +static const uint32_t evt_mappings[BELLBOARD_NUM_IRQS] = { + LISTIFY(DT_NUM_IRQS(DT_DRV_INST(0)), BELLBOARD_GET_EVT_MAPPING, ())}; + +/* BELLBOARD instance */ +static NRF_BELLBOARD_Type *bellboard = (NRF_BELLBOARD_Type *)DT_INST_REG_ADDR(0); + +/* BELLBOARD runtime resources */ +static mbox_callback_t cbs[NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT]; +static void *cbs_ctx[NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT]; +static uint32_t evt_enabled_masks[BELLBOARD_NUM_IRQS]; + +static void bellboard_local_isr(const void *parameter) +{ + uint8_t irq_idx = (uint8_t)(uintptr_t)parameter; + uint32_t int_pend; + + int_pend = nrf_bellboard_int_pending_get(bellboard, irq_idx); + + for (uint8_t i = 0U; i < NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT; i++) { + nrf_bellboard_event_t event = nrf_bellboard_triggered_event_get(i); + + if (nrf_bellboard_event_check(bellboard, event)) { + nrf_bellboard_event_clear(bellboard, event); + } + + if ((int_pend & BIT(i)) != 0U) { + if (cbs[i] != NULL) { + cbs[i](DEVICE_DT_INST_GET(0), i, cbs_ctx[i], NULL); + } + } + } +} + +static uint32_t bellboard_local_max_channels_get(const struct device *dev) +{ + ARG_UNUSED(dev); + + return NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT; +} + +static int bellboard_local_register_callback(const struct device *dev, uint32_t id, + mbox_callback_t cb, void *user_data) +{ + ARG_UNUSED(dev); + + if (id >= NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT) { + return -EINVAL; + } + + cbs[id] = cb; + cbs_ctx[id] = user_data; + + return 0; +} + +static int bellboard_local_set_enabled(const struct device *dev, uint32_t id, bool enable) +{ + bool valid_found = false; + + ARG_UNUSED(dev); + + if (id >= NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT) { + return -EINVAL; + } + + for (uint8_t i = 0U; i < BELLBOARD_NUM_IRQS; i++) { + uint32_t *evt_enabled_mask; + + if ((evt_mappings[i] == 0U) || ((evt_mappings[i] & BIT(id)) == 0U)) { + continue; + } + + valid_found = true; + evt_enabled_mask = &evt_enabled_masks[i]; + + if (enable) { + if ((*evt_enabled_mask & BIT(id)) != 0U) { + return -EALREADY; + } + + *evt_enabled_mask |= BIT(id); + nrf_bellboard_int_enable(bellboard, i, BIT(id)); + } else { + if ((*evt_enabled_mask & BIT(id)) == 0U) { + return -EALREADY; + } + + *evt_enabled_mask &= ~BIT(id); + nrf_bellboard_int_disable(bellboard, i, BIT(id)); + } + } + + if (!valid_found) { + return -EINVAL; + } + + return 0; +} + +static const struct mbox_driver_api bellboard_local_driver_api = { + .max_channels_get = bellboard_local_max_channels_get, + .register_callback = bellboard_local_register_callback, + .set_enabled = bellboard_local_set_enabled, +}; + +#define BELLBOARD_IRQ_CONFIGURE(name, idx) \ + COND_CODE_1(DT_INST_IRQ_HAS_NAME(0, name), \ + (IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, name, irq), \ + DT_INST_IRQ_BY_NAME(0, name, priority), bellboard_local_isr, \ + (const void *)idx, 0); \ + irq_enable(DT_INST_IRQ_BY_NAME(0, name, irq));), \ + ()) + +static int bellboard_local_init(const struct device *dev) +{ + uint32_t evt_all_mappings = + evt_mappings[0] | evt_mappings[1] | evt_mappings[2] | evt_mappings[3]; + + ARG_UNUSED(dev); + + nrf_bellboard_int_disable(bellboard, 0, evt_mappings[0]); + nrf_bellboard_int_disable(bellboard, 1, evt_mappings[1]); + nrf_bellboard_int_disable(bellboard, 2, evt_mappings[2]); + nrf_bellboard_int_disable(bellboard, 3, evt_mappings[3]); + + for (uint8_t i = 0U; i < NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT; i++) { + if ((evt_all_mappings & BIT(i)) != 0U) { + nrf_bellboard_event_clear(bellboard, nrf_bellboard_triggered_event_get(i)); + } + } + + BELLBOARD_IRQ_CONFIGURE(irq0, 0); + BELLBOARD_IRQ_CONFIGURE(irq1, 1); + BELLBOARD_IRQ_CONFIGURE(irq2, 2); + BELLBOARD_IRQ_CONFIGURE(irq3, 3); + + return 0; +} + +DEVICE_DT_INST_DEFINE(0, bellboard_local_init, NULL, NULL, NULL, POST_KERNEL, + CONFIG_MBOX_INIT_PRIORITY, &bellboard_local_driver_api); diff --git a/drivers/mbox/mbox_nrf_bellboard_remote.c b/drivers/mbox/mbox_nrf_bellboard_remote.c new file mode 100644 index 00000000000..c362522c0bf --- /dev/null +++ b/drivers/mbox/mbox_nrf_bellboard_remote.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nordic_nrf_bellboard_remote + +#include +#include + +#include + +struct mbox_bellboard_remote_conf { + NRF_BELLBOARD_Type *bellboard; +}; + +static int bellboard_remote_send(const struct device *dev, uint32_t id, const struct mbox_msg *msg) +{ + const struct mbox_bellboard_remote_conf *config = dev->config; + + if (id >= BELLBOARD_TASKS_TRIGGER_MaxCount) { + return -EINVAL; + } + + if (msg != NULL) { + return -ENOTSUP; + } + + nrfy_bellboard_task_trigger(config->bellboard, nrf_bellboard_trigger_task_get(id)); + + return 0; +} + +static int bellboard_remote_mtu_get(const struct device *dev) +{ + ARG_UNUSED(dev); + + return 0; +} + +static uint32_t bellboard_remote_max_channels_get(const struct device *dev) +{ + ARG_UNUSED(dev); + + return BELLBOARD_TASKS_TRIGGER_MaxCount; +} + +static const struct mbox_driver_api bellboard_remote_driver_api = { + .send = bellboard_remote_send, + .mtu_get = bellboard_remote_mtu_get, + .max_channels_get = bellboard_remote_max_channels_get, +}; + +#define BELLBOARD_REMOTE_DEFINE(inst) \ + static const struct mbox_bellboard_remote_conf conf##inst = { \ + .bellboard = (NRF_BELLBOARD_Type *)DT_INST_REG_ADDR(inst), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(inst, NULL, NULL, NULL, &conf##inst, POST_KERNEL, \ + CONFIG_MBOX_INIT_PRIORITY, &bellboard_remote_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(BELLBOARD_REMOTE_DEFINE) From ceb1e70bb57cee736a0137eccf702ab73dc4bf90 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Thu, 22 Feb 2024 16:22:21 +0100 Subject: [PATCH 0169/2402] samples: drivers: mbox: add support for nRF BELLBOARD Add support for testing BELLBOARD between cpuapp (local) and cpuppr (remote). Signed-off-by: Gerard Marull-Paretas --- ...nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf | 1 + ...54h20pdk_nrf54h20_cpuapp_bellboard.overlay | 8 ++++++++ ...nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf | 1 + ...54h20pdk_nrf54h20_cpuppr_bellboard.overlay | 8 ++++++++ samples/drivers/mbox/sample.yaml | 20 +++++++++++++++++++ 5 files changed, 38 insertions(+) create mode 100644 samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf create mode 100644 samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay create mode 100644 samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf create mode 100644 samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf new file mode 100644 index 00000000000..0b6bc73d6bc --- /dev/null +++ b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf @@ -0,0 +1 @@ +CONFIG_TX_ENABLED=n diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay new file mode 100644 index 00000000000..5f0cfe2261d --- /dev/null +++ b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay @@ -0,0 +1,8 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +mbox: &cpuapp_bellboard { + status = "okay"; +}; diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf new file mode 100644 index 00000000000..4596bc3a757 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf @@ -0,0 +1 @@ +CONFIG_RX_ENABLED=n diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay new file mode 100644 index 00000000000..5f0cfe2261d --- /dev/null +++ b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay @@ -0,0 +1,8 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +mbox: &cpuapp_bellboard { + status = "okay"; +}; diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml index b2aaa8d36fa..75a39dc4939 100644 --- a/samples/drivers/mbox/sample.yaml +++ b/samples/drivers/mbox/sample.yaml @@ -44,6 +44,26 @@ tests: - "Ping \\(on channel 4\\)" - "Pong \\(on channel 4\\)" + sample.drivers.mbox.nrf54h20_bellboard: + platform_allow: + - nrf54h20pdk/nrf54h20/cpuapp + integration_platforms: + - nrf54h20pdk/nrf54h20/cpuapp + extra_args: + mbox_SNIPPET=nordic-ppr + mbox_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf + mbox_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay + remote_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf + remote_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay + sysbuild: true + harness: console + harness_config: + type: multi_line + ordered: false + regex: + - "Ping \\(on channel 0\\)" + - "Pong \\(on channel 0\\)" + sample.drivers.mbox.simu: platform_allow: - nrf5340bsim_nrf5340_cpuapp From 9911d6bba0761e36248cad078e31586b6c85205a Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 4 Mar 2024 09:52:25 +0100 Subject: [PATCH 0170/2402] samples: drivers: mbox: fix hwmv2 issues Some board names were not ported to HWMv2 scheme. Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/sysbuild.cmake | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/samples/drivers/mbox/sysbuild.cmake b/samples/drivers/mbox/sysbuild.cmake index 2e7d69d9da5..f39e7b74316 100644 --- a/samples/drivers/mbox/sysbuild.cmake +++ b/samples/drivers/mbox/sysbuild.cmake @@ -20,9 +20,8 @@ native_simulator_set_child_images(${DEFAULT_IMAGE} ${REMOTE_APP}) native_simulator_set_final_executable(${DEFAULT_IMAGE}) -if ("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7" OR - "${BOARD}" STREQUAL "mimxrt1170_evk_cm7" OR - "${BOARD}" STREQUAL "mimxrt1160_evk_cm7" OR +if ("${BOARD}" STREQUAL "mimxrt1170_evk" OR + "${BOARD}" STREQUAL "mimxrt1160_evk" OR "${BOARD}" STREQUAL "lpcxpresso55s69" ) # For these NXP boards the main core application is dependent on From 590e4f3a82dfad5b0b935545020158868b3999ad Mon Sep 17 00:00:00 2001 From: Peter Mitsis Date: Wed, 24 Jan 2024 15:12:03 -0500 Subject: [PATCH 0171/2402] tests: latency_measure: Add k_stack object support Updates the latency_measure test to add support for benchmarking k_stack_push() and k_stack_pop(). Signed-off-by: Peter Mitsis --- tests/benchmarks/latency_measure/README.rst | 17 ++ tests/benchmarks/latency_measure/src/main.c | 15 ++ tests/benchmarks/latency_measure/src/stack.c | 223 +++++++++++++++++++ 3 files changed, 255 insertions(+) create mode 100644 tests/benchmarks/latency_measure/src/stack.c diff --git a/tests/benchmarks/latency_measure/README.rst b/tests/benchmarks/latency_measure/README.rst index a4119c636c2..1cd75544b8f 100644 --- a/tests/benchmarks/latency_measure/README.rst +++ b/tests/benchmarks/latency_measure/README.rst @@ -23,6 +23,7 @@ including: * Time it takes to send and receive events * Time it takes to wait for events (and context switch) * Time it takes to wake and switch to a thread waiting for events +* Time it takes to push and pop to/from a k_stack * Measure average time to alloc memory from heap then free that memory When userspace is enabled using the prj_user.conf configuration file, this benchmark will @@ -76,6 +77,10 @@ Sample output of the benchmark (without userspace enabled):: semaphore.give.wake+ctx.k_to_k - Give a semaphore (context switch) : 599 cycles , 4992 ns : condvar.wait.blocking.k_to_k - Wait for a condvar (context switch) : 692 cycles , 5767 ns : condvar.signal.wake+ctx.k_to_k - Signal a condvar (context switch) : 715 cycles , 5958 ns : + stack.push.immediate.kernel - Add data to k_stack (no ctx switch) : 166 cycles , 1391 ns : + stack.pop.immediate.kernel - Get data from k_stack (no ctx switch) : 82 cycles , 691 ns : + stack.pop.blocking.k_to_k - Get data from k_stack (w/ ctx switch) : 499 cycles , 4166 ns : + stack.push.wake+ctx.k_to_k - Add data to k_stack (w/ ctx switch) : 645 cycles , 5375 ns : mutex.lock.immediate.recursive.kernel - Lock a mutex : 100 cycles , 833 ns : mutex.unlock.immediate.recursive.kernel - Unlock a mutex : 40 cycles , 333 ns : heap.malloc.immediate - Average time for heap malloc : 627 cycles , 5225 ns : @@ -193,6 +198,18 @@ Sample output of the benchmark (with userspace enabled):: condvar.signal.wake+ctx.k_to_u - Signal a condvar (context switch) : 1715 cycles , 14298 ns : condvar.wait.blocking.u_to_u - Wait for a condvar (context switch) : 2313 cycles , 19279 ns : condvar.signal.wake+ctx.u_to_u - Signal a condvar (context switch) : 2225 cycles , 18541 ns : + stack.push.immediate.kernel - Add data to k_stack (no ctx switch) : 244 cycles , 2041 ns : + stack.pop.immediate.kernel - Get data from k_stack (no ctx switch) : 195 cycles , 1630 ns : + stack.push.immediate.user - Add data to k_stack (no ctx switch) : 714 cycles , 5956 ns : + stack.pop.immediate.user - Get data from k_stack (no ctx switch) : 1009 cycles , 8414 ns : + stack.pop.blocking.k_to_k - Get data from k_stack (w/ ctx switch) : 1234 cycles , 10291 ns : + stack.push.wake+ctx.k_to_k - Add data to k_stack (w/ ctx switch) : 1360 cycles , 11333 ns : + stack.pop.blocking.u_to_k - Get data from k_stack (w/ ctx switch) : 2084 cycles , 17374 ns : + stack.push.wake+ctx.k_to_u - Add data to k_stack (w/ ctx switch) : 1665 cycles , 13875 ns : + stack.pop.blocking.k_to_u - Get data from k_stack (w/ ctx switch) : 1544 cycles , 12874 ns : + stack.push.wake+ctx.u_to_k - Add data to k_stack (w/ ctx switch) : 1850 cycles , 15422 ns : + stack.pop.blocking.u_to_u - Get data from k_stack (w/ ctx switch) : 2394 cycles , 19958 ns : + stack.push.wake+ctx.u_to_u - Add data to k_stack (w/ ctx switch) : 2155 cycles , 17958 ns : mutex.lock.immediate.recursive.kernel - Lock a mutex : 155 cycles , 1291 ns : mutex.unlock.immediate.recursive.kernel - Unlock a mutex : 57 cycles , 475 ns : mutex.lock.immediate.recursive.user - Lock a mutex : 665 cycles , 5541 ns : diff --git a/tests/benchmarks/latency_measure/src/main.c b/tests/benchmarks/latency_measure/src/main.c index b21c0c6b3ea..ba709d54512 100644 --- a/tests/benchmarks/latency_measure/src/main.c +++ b/tests/benchmarks/latency_measure/src/main.c @@ -55,6 +55,9 @@ extern int event_blocking_ops(uint32_t num_iterations, uint32_t start_options, uint32_t alt_options); extern int condvar_blocking_ops(uint32_t num_iterations, uint32_t start_options, uint32_t alt_options); +extern int stack_ops(uint32_t num_iterations, uint32_t options); +extern int stack_blocking_ops(uint32_t num_iterations, uint32_t start_options, + uint32_t alt_options); extern void heap_malloc_free(void); static void test_thread(void *arg1, void *arg2, void *arg3) @@ -154,6 +157,18 @@ static void test_thread(void *arg1, void *arg2, void *arg3) condvar_blocking_ops(CONFIG_BENCHMARK_NUM_ITERATIONS, K_USER, K_USER); #endif + stack_ops(CONFIG_BENCHMARK_NUM_ITERATIONS, 0); +#ifdef CONFIG_USERSPACE + stack_ops(CONFIG_BENCHMARK_NUM_ITERATIONS, K_USER); +#endif + + stack_blocking_ops(CONFIG_BENCHMARK_NUM_ITERATIONS, 0, 0); +#ifdef CONFIG_USERSPACE + stack_blocking_ops(CONFIG_BENCHMARK_NUM_ITERATIONS, 0, K_USER); + stack_blocking_ops(CONFIG_BENCHMARK_NUM_ITERATIONS, K_USER, 0); + stack_blocking_ops(CONFIG_BENCHMARK_NUM_ITERATIONS, K_USER, K_USER); +#endif + mutex_lock_unlock(CONFIG_BENCHMARK_NUM_ITERATIONS, 0); #ifdef CONFIG_USERSPACE mutex_lock_unlock(CONFIG_BENCHMARK_NUM_ITERATIONS, K_USER); diff --git a/tests/benchmarks/latency_measure/src/stack.c b/tests/benchmarks/latency_measure/src/stack.c new file mode 100644 index 00000000000..75962d84fc7 --- /dev/null +++ b/tests/benchmarks/latency_measure/src/stack.c @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * @file measure time for various k_stack operations + * + * This file contains the tests that measures the times for the following + * k_stack operations from both kernel threads and user threads: + * 1. Immediately adding a data item to a k_stack + * 2. Immediately removing a data item from a k_stack + * 3. Blocking on removing a data item from a k_stack + * 4. Waking (and context switching to) a thread blocked on a k_stack + */ + +#include +#include +#include "utils.h" +#include "timing_sc.h" + +#define MAX_ITEMS 16 + +static BENCH_BMEM stack_data_t stack_array[MAX_ITEMS]; + +static struct k_stack stack; + +static void stack_push_pop_thread_entry(void *p1, void *p2, void *p3) +{ + uint32_t num_iterations = (uint32_t)(uintptr_t)p1; + timing_t start; + timing_t mid; + timing_t finish; + uint64_t put_sum = 0ULL; + uint64_t get_sum = 0ULL; + stack_data_t data; + + for (uint32_t i = 0; i < num_iterations; i++) { + start = timing_timestamp_get(); + + (void) k_stack_push(&stack, 1234); + + mid = timing_timestamp_get(); + + (void) k_stack_pop(&stack, &data, K_NO_WAIT); + + finish = timing_timestamp_get(); + + put_sum += timing_cycles_get(&start, &mid); + get_sum += timing_cycles_get(&mid, &finish); + } + + timestamp.cycles = put_sum; + k_sem_take(&pause_sem, K_FOREVER); + + timestamp.cycles = get_sum; +} + +int stack_ops(uint32_t num_iterations, uint32_t options) +{ + int priority; + uint64_t cycles; + char tag[50]; + char description[120]; + + priority = k_thread_priority_get(k_current_get()); + + timing_start(); + + k_stack_init(&stack, stack_array, MAX_ITEMS); + + k_thread_create(&start_thread, start_stack, + K_THREAD_STACK_SIZEOF(start_stack), + stack_push_pop_thread_entry, + (void *)(uintptr_t)num_iterations, + NULL, NULL, + priority - 1, options, K_FOREVER); + + k_thread_access_grant(&start_thread, &pause_sem, &stack); + + k_thread_start(&start_thread); + + snprintf(tag, sizeof(tag), + "stack.push.immediate.%s", + options & K_USER ? "user" : "kernel"); + snprintf(description, sizeof(description), + "%-40s - Add data to k_stack (no ctx switch)", tag); + + cycles = timestamp.cycles; + cycles -= timestamp_overhead_adjustment(options, options); + PRINT_STATS_AVG(description, (uint32_t)cycles, + num_iterations, false, ""); + k_sem_give(&pause_sem); + + snprintf(tag, sizeof(tag), + "stack.pop.immediate.%s", + options & K_USER ? "user" : "kernel"); + snprintf(description, sizeof(description), + "%-40s - Get data from k_stack (no ctx switch)", tag); + cycles = timestamp.cycles; + cycles -= timestamp_overhead_adjustment(options, options); + PRINT_STATS_AVG(description, (uint32_t)cycles, + num_iterations, false, ""); + + k_thread_join(&start_thread, K_FOREVER); + + timing_stop(); + + return 0; +} + +static void alt_thread_entry(void *p1, void *p2, void *p3) +{ + uint32_t num_iterations = (uint32_t)(uintptr_t)p1; + timing_t start; + timing_t mid; + timing_t finish; + uint64_t sum[2] = {0ULL, 0ULL}; + uint32_t i; + stack_data_t data; + + for (i = 0; i < num_iterations; i++) { + + /* 1. Block waiting for data on k_stack */ + + start = timing_timestamp_get(); + + k_stack_pop(&stack, &data, K_FOREVER); + + /* 3. Data obtained. */ + + finish = timing_timestamp_get(); + + mid = timestamp.sample; + + sum[0] += timing_cycles_get(&start, &mid); + sum[1] += timing_cycles_get(&mid, &finish); + } + + timestamp.cycles = sum[0]; + k_sem_take(&pause_sem, K_FOREVER); + timestamp.cycles = sum[1]; +} + +static void start_thread_entry(void *p1, void *p2, void *p3) +{ + uint32_t num_iterations = (uint32_t)(uintptr_t)p1; + uint32_t i; + + k_thread_start(&alt_thread); + + for (i = 0; i < num_iterations; i++) { + + /* 2. Add data thereby waking alt thread */ + + timestamp.sample = timing_timestamp_get(); + + k_stack_push(&stack, (stack_data_t)123); + } + + k_thread_join(&alt_thread, K_FOREVER); +} + +int stack_blocking_ops(uint32_t num_iterations, uint32_t start_options, + uint32_t alt_options) +{ + int priority; + uint64_t cycles; + char tag[50]; + char description[120]; + + priority = k_thread_priority_get(k_current_get()); + + timing_start(); + + k_thread_create(&start_thread, start_stack, + K_THREAD_STACK_SIZEOF(start_stack), + start_thread_entry, + (void *)(uintptr_t)num_iterations, + NULL, NULL, + priority - 1, start_options, K_FOREVER); + + k_thread_create(&alt_thread, alt_stack, + K_THREAD_STACK_SIZEOF(alt_stack), + alt_thread_entry, + (void *)(uintptr_t)num_iterations, + NULL, NULL, + priority - 2, alt_options, K_FOREVER); + + k_thread_access_grant(&start_thread, &alt_thread, &pause_sem, &stack); + k_thread_access_grant(&alt_thread, &pause_sem, &stack); + + k_thread_start(&start_thread); + + snprintf(tag, sizeof(tag), + "stack.pop.blocking.%s_to_%s", + alt_options & K_USER ? "u" : "k", + start_options & K_USER ? "u" : "k"); + snprintf(description, sizeof(description), + "%-40s - Get data from k_stack (w/ ctx switch)", tag); + + cycles = timestamp.cycles; + PRINT_STATS_AVG(description, (uint32_t)cycles, + num_iterations, false, ""); + k_sem_give(&pause_sem); + + snprintf(tag, sizeof(tag), + "stack.push.wake+ctx.%s_to_%s", + start_options & K_USER ? "u" : "k", + alt_options & K_USER ? "u" : "k"); + snprintf(description, sizeof(description), + "%-40s - Add data to k_stack (w/ ctx switch)", tag); + cycles = timestamp.cycles; + PRINT_STATS_AVG(description, (uint32_t)cycles, + num_iterations, false, ""); + + k_thread_join(&start_thread, K_FOREVER); + + timing_stop(); + + return 0; +} From 16a60630830d19c0be6c3118c9dd3f33d03d0ac7 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 5 Mar 2024 13:32:42 +0100 Subject: [PATCH 0172/2402] manifest: remove .git suffixes from repo-paths Some entries had the .git suffix in the repo-path property. While it does not affect e.g. clones, it makes the project URL (built using base url and repo-path) unusable to build other URLs (e.g. to point to a commit, release tag, etc.). Signed-off-by: Gerard Marull-Paretas --- west.yml | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/west.yml b/west.yml index 22a127d08cf..d63685e9dc8 100644 --- a/west.yml +++ b/west.yml @@ -40,77 +40,77 @@ manifest: - babblesim - name: babblesim_base remote: babblesim - repo-path: base.git + repo-path: base path: tools/bsim/components revision: 19d62424c0802c6c9fc15528febe666e40f372a1 groups: - babblesim - name: babblesim_ext_2G4_libPhyComv1 remote: babblesim - repo-path: ext_2G4_libPhyComv1.git + repo-path: ext_2G4_libPhyComv1 path: tools/bsim/components/ext_2G4_libPhyComv1 revision: 9018113a362fa6c9e8f4b9cab9e5a8f12cc46b94 groups: - babblesim - name: babblesim_ext_2G4_phy_v1 remote: babblesim - repo-path: ext_2G4_phy_v1.git + repo-path: ext_2G4_phy_v1 path: tools/bsim/components/ext_2G4_phy_v1 revision: d47c6dd90035b41b14f6921785ccb7b8484868e2 groups: - babblesim - name: babblesim_ext_2G4_channel_NtNcable remote: babblesim - repo-path: ext_2G4_channel_NtNcable.git + repo-path: ext_2G4_channel_NtNcable path: tools/bsim/components/ext_2G4_channel_NtNcable revision: 20a38c997f507b0aa53817aab3d73a462fff7af1 groups: - babblesim - name: babblesim_ext_2G4_channel_multiatt remote: babblesim - repo-path: ext_2G4_channel_multiatt.git + repo-path: ext_2G4_channel_multiatt path: tools/bsim/components/ext_2G4_channel_multiatt revision: bde72a57384dde7a4310bcf3843469401be93074 groups: - babblesim - name: babblesim_ext_2G4_modem_magic remote: babblesim - repo-path: ext_2G4_modem_magic.git + repo-path: ext_2G4_modem_magic path: tools/bsim/components/ext_2G4_modem_magic revision: cb70771794f0bf6f262aa474848611c68ae8f1ed groups: - babblesim - name: babblesim_ext_2G4_modem_BLE_simple remote: babblesim - repo-path: ext_2G4_modem_BLE_simple.git + repo-path: ext_2G4_modem_BLE_simple path: tools/bsim/components/ext_2G4_modem_BLE_simple revision: 809ab073159c9ab6686c2fea5749b0702e0909f7 groups: - babblesim - name: babblesim_ext_2G4_device_burst_interferer remote: babblesim - repo-path: ext_2G4_device_burst_interferer.git + repo-path: ext_2G4_device_burst_interferer path: tools/bsim/components/ext_2G4_device_burst_interferer revision: 5b5339351d6e6a2368c686c734dc8b2fc65698fc groups: - babblesim - name: babblesim_ext_2G4_device_WLAN_actmod remote: babblesim - repo-path: ext_2G4_device_WLAN_actmod.git + repo-path: ext_2G4_device_WLAN_actmod path: tools/bsim/components/ext_2G4_device_WLAN_actmod revision: 9cb6d8e72695f6b785e57443f0629a18069d6ce4 groups: - babblesim - name: babblesim_ext_2G4_device_playback remote: babblesim - repo-path: ext_2G4_device_playback.git + repo-path: ext_2G4_device_playback path: tools/bsim/components/ext_2G4_device_playback revision: 85c645929cf1ce995d8537107d9dcbd12ed64036 groups: - babblesim - name: babblesim_ext_libCryptov1 remote: babblesim - repo-path: ext_libCryptov1.git + repo-path: ext_libCryptov1 path: tools/bsim/components/ext_libCryptov1 revision: eed6d7038e839153e340bd333bc43541cb90ba64 groups: From 5e7286fac5fb8ae166ccc2be978f6a6810d5f63a Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 5 Mar 2024 08:09:56 -0500 Subject: [PATCH 0173/2402] ci: codecov: fix platform names for hwmv2 Replace / with _ in platform names when generating files. Signed-off-by: Anas Nashif --- .github/workflows/codecov.yaml | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 87ed7b963e0..7a9f6fae6c4 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -21,6 +21,15 @@ jobs: fail-fast: false matrix: platform: ["mps2/an385", "native_sim", "qemu_x86", "unit_testing"] + include: + - platform: 'mps2/an385' + normalized: 'mps2_an385' + - platform: 'native_sim' + normalized: 'native_sim' + - platform: 'qemu_x86' + normalized: 'qemu_x86' + - platform: 'unit_testing' + normalized: 'unit_testing' steps: - name: Apply container owner mismatch workaround run: | @@ -90,7 +99,8 @@ jobs: export ZEPHYR_TOOLCHAIN_VARIANT=zephyr mkdir -p coverage/reports pip3 install gcovr==6.0 - ./scripts/twister -E ${{ matrix.platform }}-testplan.json + ./scripts/twister -E ${{matrix.normalized}}-testplan.json + ls -la ./scripts/twister -i --force-color -N -v --filter runnable -p ${{ matrix.platform }} --coverage -T tests --coverage-tool gcovr -xCONFIG_TEST_EXTRA_STACK_SIZE=4096 -e nano - name: ccache stats post @@ -101,16 +111,16 @@ jobs: - name: Rename coverage files if: always() run: | - cp twister-out/coverage.json coverage/reports/${{ matrix.platform }}.json + mv twister-out/coverage.json coverage/reports/${{matrix.normalized}}.json - name: Upload Coverage Results if: always() uses: actions/upload-artifact@v4 with: - name: Coverage Data (Subset ${{ matrix.platform }}) + name: Coverage Data (Subset ${{ matrix.normalized }}) path: | - coverage/reports/${{ matrix.platform }}.json - ${{ matrix.platform }}-testplan.json + coverage/reports/${{ matrix.normalized }}.json + ${{ matrix.normalized }}-testplan.json codecov-results: name: "Publish Coverage Results" From fe381858b7501e302f1caeb3f634693edf1e0cab Mon Sep 17 00:00:00 2001 From: Michal Smola Date: Tue, 5 Mar 2024 10:57:16 +0100 Subject: [PATCH 0174/2402] boards: mps2: Disable qemu host pty on Windows pty is not available on Windows hosts. Running a sample in Qemu on Windows shows an error. Fix it by enabling pty on Unix hosts only. Signed-off-by: Michal Smola --- boards/arm/mps2/board.cmake | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/boards/arm/mps2/board.cmake b/boards/arm/mps2/board.cmake index 21d98c39bfa..6f38d01281b 100644 --- a/boards/arm/mps2/board.cmake +++ b/boards/arm/mps2/board.cmake @@ -26,7 +26,10 @@ board_set_debugger_ifnset(qemu) if(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOARD_MPS2_AN521_CPU1) # To enable a host tty switch between serial and pty # -chardev serial,path=/dev/ttyS0,id=hostS0 - list(APPEND QEMU_EXTRA_FLAGS -chardev pty,id=hostS0 -serial chardev:hostS0) + # pty is not available on Windows. + if(CMAKE_HOST_UNIX) + list(APPEND QEMU_EXTRA_FLAGS -chardev pty,id=hostS0 -serial chardev:hostS0) + endif() if(CONFIG_BUILD_WITH_TFM) # Override the binary used by qemu, to use the combined From d8ebe7b6c966fe6490534a897bbc00d27eb75847 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Thu, 1 Feb 2024 10:13:07 +0100 Subject: [PATCH 0175/2402] drivers: charger: charger_max20335: rename status get function Current driver handles charger status only but the charger chip provides plenty of different statuses. Change name of max20335_get_status() function to max20335_get_charger_status() to make further implementations easier. Signed-off-by: Lukasz Madej --- drivers/charger/charger_max20335.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index b4f98de69f2..b7e59ca9eec 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -52,7 +52,7 @@ static const struct linear_range charger_uv_range = MAX20335_REG_CVC_VREG_MIN_IDX, MAX20335_REG_CVC_VREG_MAX_IDX); -static int max20335_get_status(const struct device *dev, enum charger_status *status) +static int max20335_get_charger_status(const struct device *dev, enum charger_status *status) { const struct charger_max20335_config *const config = dev->config; uint8_t val; @@ -219,7 +219,7 @@ static int max20335_get_prop(const struct device *dev, charger_prop_t prop, { switch (prop) { case CHARGER_PROP_STATUS: - return max20335_get_status(dev, &val->status); + return max20335_get_charger_status(dev, &val->status); case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA: return max20335_get_constant_charge_current(dev, &val->const_charge_current_ua); From e9eb1d841e83fe4e0871a68eef56fff6956144d8 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Fri, 2 Feb 2024 10:20:44 +0100 Subject: [PATCH 0176/2402] drivers: charger: charger_max20335: fix argument name Rename `current_uv` argument name to `voltage_uv` in function max20335_get_constant_charge_voltage() to make the name aligned with its usage. Signed-off-by: Lukasz Madej --- drivers/charger/charger_max20335.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index b7e59ca9eec..82158707251 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -188,7 +188,7 @@ static int max20335_get_constant_charge_current(const struct device *dev, } static int max20335_get_constant_charge_voltage(const struct device *dev, - uint32_t *current_uv) + uint32_t *voltage_uv) { const struct charger_max20335_config *const config = dev->config; uint8_t val; @@ -201,7 +201,7 @@ static int max20335_get_constant_charge_voltage(const struct device *dev, val = FIELD_GET(MAX20335_CHGCNTLA_BAT_REG_CFG_MASK, val); - return linear_range_get_value(&charger_uv_range, val, current_uv); + return linear_range_get_value(&charger_uv_range, val, voltage_uv); } static int max20335_set_enabled(const struct device *dev, bool enable) From 90c32e99d6508b7a86f5bb656024afea6c50a288 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Thu, 1 Feb 2024 11:14:58 +0100 Subject: [PATCH 0177/2402] drivers: charger: charger_max20335: introduce int utilization Utilization of chip interrupt line is mandatory to assure proper charger state control. Handle interrupt to prepare the driver for implementation of such functionality. Modify charger status update so the current state is fetched in the interrupt handler. Use level based interrupts combined with interrupt disabling for a period of time after interrupt handling to reduce number of interrupts triggered by the charger. There may be a case where the charger produces burst of interrupts for a several seconds and if the code attempts to handle every single interrupt separatery then the system might be significantly overloaded. Co-authored-by: Bartosz Bilas Signed-off-by: Lukasz Madej --- drivers/charger/Kconfig.max20335 | 1 + drivers/charger/charger_max20335.c | 189 +++++++++++++++++- .../charger/maxim,max20335-charger.yaml | 5 + tests/drivers/build_all/charger/app.overlay | 8 + tests/drivers/build_all/charger/i2c.dtsi | 1 + 5 files changed, 202 insertions(+), 2 deletions(-) diff --git a/drivers/charger/Kconfig.max20335 b/drivers/charger/Kconfig.max20335 index 7104e5daab6..a6245ba5c18 100644 --- a/drivers/charger/Kconfig.max20335 +++ b/drivers/charger/Kconfig.max20335 @@ -5,6 +5,7 @@ config CHARGER_MAX20335 bool "MAX20335 battery charger driver" default y depends on DT_HAS_MAXIM_MAX20335_CHARGER_ENABLED + select GPIO select I2C select MFD help diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index 82158707251..06e21194c7a 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -17,6 +18,11 @@ LOG_MODULE_REGISTER(max20335_charger); #define MAX20335_REG_STATUS_A 0x02 +#define MAX20335_REG_INT_A 0x05 +#define MAX20335_REG_INT_B 0x06 +#define MAX20335_INT_A_CHG_STAT_MASK BIT(6) +#define MAX20335_REG_INT_MASK_A 0x07 +#define MAX20335_REG_INT_MASK_B 0x08 #define MAX20335_REG_ILIMCNTL 0x09 #define MAX20335_REG_CHG_CNTL_A 0x0A #define MAX20335_CHGCNTLA_BAT_REG_CFG_MASK GENMASK(4, 1) @@ -29,12 +35,23 @@ LOG_MODULE_REGISTER(max20335_charger); #define MAX20335_REG_CVC_VREG_MIN_IDX 0x0U #define MAX20335_REG_CVC_VREG_MAX_IDX 0x0CU +#define INT_ENABLE_DELAY K_MSEC(500) + struct charger_max20335_config { struct i2c_dt_spec bus; + struct gpio_dt_spec int_gpio; uint32_t max_ichg_ua; uint32_t max_vreg_uv; }; +struct charger_max20335_data { + const struct device *dev; + struct gpio_callback gpio_cb; + struct k_work int_routine_work; + struct k_work_delayable int_enable_work; + enum charger_status charger_status; +}; + enum { MAX20335_CHARGER_OFF, MAX20335_CHARGING_SUSPENDED_DUE_TO_TEMPERATURE, @@ -214,12 +231,55 @@ static int max20335_set_enabled(const struct device *dev, bool enable) enable ? MAX20335_CHRG_EN : 0); } +static int max20335_get_interrupt_source(const struct device *dev, uint8_t *int_a, uint8_t *int_b) +{ + const struct charger_max20335_config *config = dev->config; + uint8_t dummy; + uint8_t *int_src; + int ret; + + /* Both INT_A and INT_B registers need to be read to clear all int flags */ + + int_src = (int_a != NULL) ? int_a : &dummy; + ret = i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_INT_A, int_src); + if (ret < 0) { + return ret; + } + + int_src = (int_b != NULL) ? int_b : &dummy; + + return i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_INT_B, int_src); +} + +static int max20335_enable_interrupts(const struct device *dev) +{ + enum {MASK_A_VAL_ENABLE = 0xFF}; + const struct charger_max20335_config *config = dev->config; + int ret; + + ret = max20335_get_interrupt_source(dev, NULL, NULL); + if (ret < 0) { + LOG_WRN("Failed to clear pending interrupts: %d", ret); + return ret; + } + + ret = i2c_reg_write_byte_dt(&config->bus, MAX20335_REG_INT_MASK_A, MASK_A_VAL_ENABLE); + if (ret < 0) { + return ret; + } + + return i2c_reg_write_byte_dt(&config->bus, MAX20335_REG_INT_MASK_B, 0); +} + static int max20335_get_prop(const struct device *dev, charger_prop_t prop, union charger_propval *val) { + struct charger_max20335_data *data = dev->data; + switch (prop) { case CHARGER_PROP_STATUS: - return max20335_get_charger_status(dev, &val->status); + val->status = data->charger_status; + return 0; case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA: return max20335_get_constant_charge_current(dev, &val->const_charge_current_ua); @@ -246,14 +306,137 @@ static int max20335_set_prop(const struct device *dev, charger_prop_t prop, } } +static int max20335_enable_interrupt_pin(const struct device *dev, bool enabled) +{ + const struct charger_max20335_config *const config = dev->config; + gpio_flags_t flags; + int ret; + + flags = enabled ? GPIO_INT_LEVEL_ACTIVE : GPIO_INT_DISABLE; + + ret = gpio_pin_interrupt_configure_dt(&config->int_gpio, flags); + if (ret < 0) { + LOG_ERR("Could not %s interrupt GPIO callback: %d", enabled ? "enable" : "disable", + ret); + } + + return ret; +} + +static void max20335_gpio_callback(const struct device *dev, struct gpio_callback *cb, + uint32_t pins) +{ + struct charger_max20335_data *data = CONTAINER_OF(cb, struct charger_max20335_data, + gpio_cb); + int ret; + + (void) max20335_enable_interrupt_pin(data->dev, false); + + ret = k_work_submit(&data->int_routine_work); + if (ret < 0) { + LOG_WRN("Could not submit int work: %d", ret); + } +} + +static void max20335_int_routine_work_handler(struct k_work *work) +{ + struct charger_max20335_data *data = CONTAINER_OF(work, struct charger_max20335_data, + int_routine_work); + uint8_t int_src_a; + int ret; + + ret = max20335_get_interrupt_source(data->dev, &int_src_a, NULL); + if (ret < 0) { + LOG_WRN("Failed to read interrupt source"); + return; + } + + if ((int_src_a & MAX20335_INT_A_CHG_STAT_MASK) != 0) { + ret = max20335_get_charger_status(data->dev, &data->charger_status); + if (ret < 0) { + LOG_WRN("Failed to read charger status: %d", ret); + } + } + + ret = k_work_reschedule(&data->int_enable_work, INT_ENABLE_DELAY); + if (ret < 0) { + LOG_WRN("Could not reschedule int_enable_work: %d", ret); + } +} + +static void max20335_int_enable_work_handler(struct k_work *work) +{ + struct k_work_delayable *dwork = k_work_delayable_from_work(work); + struct charger_max20335_data *data = CONTAINER_OF(dwork, struct charger_max20335_data, + int_enable_work); + + (void) max20335_enable_interrupt_pin(data->dev, true); +} + +static int max20335_configure_interrupt_pin(const struct device *dev) +{ + struct charger_max20335_data *data = dev->data; + const struct charger_max20335_config *config = dev->config; + int ret; + + if (!gpio_is_ready_dt(&config->int_gpio)) { + LOG_ERR("Interrupt GPIO device not ready"); + return -ENODEV; + } + + ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT); + if (ret < 0) { + LOG_ERR("Could not configure interrupt GPIO"); + return ret; + } + + gpio_init_callback(&data->gpio_cb, max20335_gpio_callback, BIT(config->int_gpio.pin)); + ret = gpio_add_callback_dt(&config->int_gpio, &data->gpio_cb); + if (ret < 0) { + LOG_ERR("Could not add interrupt GPIO callback"); + return ret; + } + + return 0; +} + static int max20335_init(const struct device *dev) { + struct charger_max20335_data *data = dev->data; const struct charger_max20335_config *config = dev->config; + int ret; if (!i2c_is_ready_dt(&config->bus)) { return -ENODEV; } + data->dev = dev; + + ret = max20335_get_charger_status(dev, &data->charger_status); + if (ret != 0) { + LOG_ERR("Failed to read charger status: %d", ret); + return ret; + } + + k_work_init(&data->int_routine_work, max20335_int_routine_work_handler); + k_work_init_delayable(&data->int_enable_work, max20335_int_enable_work_handler); + + ret = max20335_configure_interrupt_pin(dev); + if (ret < 0) { + return ret; + } + + ret = max20335_enable_interrupt_pin(dev, true); + if (ret < 0) { + return ret; + } + + ret = max20335_enable_interrupts(dev); + if (ret < 0) { + LOG_ERR("Failed to enable interrupts"); + return ret; + } + return 0; } @@ -264,13 +447,15 @@ static const struct charger_driver_api max20335_driver_api = { }; #define MAX20335_DEFINE(inst) \ + static struct charger_max20335_data charger_max20335_data_##inst; \ static const struct charger_max20335_config charger_max20335_config_##inst = { \ .bus = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \ + .int_gpio = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \ .max_ichg_ua = DT_INST_PROP(inst, constant_charge_current_max_microamp), \ .max_vreg_uv = DT_INST_PROP(inst, constant_charge_voltage_max_microvolt), \ }; \ \ - DEVICE_DT_INST_DEFINE(inst, &max20335_init, NULL, NULL, \ + DEVICE_DT_INST_DEFINE(inst, &max20335_init, NULL, &charger_max20335_data_##inst, \ &charger_max20335_config_##inst, \ POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \ &max20335_driver_api); diff --git a/dts/bindings/charger/maxim,max20335-charger.yaml b/dts/bindings/charger/maxim,max20335-charger.yaml index f830e03cec5..200951b88c8 100644 --- a/dts/bindings/charger/maxim,max20335-charger.yaml +++ b/dts/bindings/charger/maxim,max20335-charger.yaml @@ -13,3 +13,8 @@ properties: constant-charge-voltage-max-microvolt: required: true + + int-gpios: + type: phandle-array + required: true + description: Interrupt pin diff --git a/tests/drivers/build_all/charger/app.overlay b/tests/drivers/build_all/charger/app.overlay index 1df6a67da98..54267a7103b 100644 --- a/tests/drivers/build_all/charger/app.overlay +++ b/tests/drivers/build_all/charger/app.overlay @@ -10,6 +10,14 @@ #address-cells = <1>; #size-cells = <1>; + test_gpio: gpio@deadbeef { + compatible = "vnd,gpio"; + gpio-controller; + reg = <0xdeadbeef 0x1000>; + #gpio-cells = <0x2>; + status = "okay"; + }; + test_i2c: i2c@11112222 { #address-cells = <1>; #size-cells = <0>; diff --git a/tests/drivers/build_all/charger/i2c.dtsi b/tests/drivers/build_all/charger/i2c.dtsi index b6365e97470..42f7cdf1919 100644 --- a/tests/drivers/build_all/charger/i2c.dtsi +++ b/tests/drivers/build_all/charger/i2c.dtsi @@ -26,6 +26,7 @@ max20335@1 { constant-charge-current-max-microamp = <100000>; constant-charge-voltage-max-microvolt = <4050000>; + int-gpios = <&test_gpio 0 0>; }; }; From d43e627938bcba95e344af19f24c62dc687c4911 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Thu, 1 Feb 2024 12:13:46 +0100 Subject: [PATCH 0178/2402] drivers: charger: charger_max20335: relocate charger state definition An anonymous enum describing charger status is used only by one function therefore reduce scope of this enum. Signed-off-by: Lukasz Madej --- drivers/charger/charger_max20335.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index 06e21194c7a..2b696d8ab83 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -52,17 +52,6 @@ struct charger_max20335_data { enum charger_status charger_status; }; -enum { - MAX20335_CHARGER_OFF, - MAX20335_CHARGING_SUSPENDED_DUE_TO_TEMPERATURE, - MAX20335_PRE_CHARGE_IN_PROGRESS, - MAX20335_FAST_CHARGE_IN_PROGRESS_1, - MAX20335_FAST_CHARGE_IN_PROGRESS_2, - MAX20335_MAINTAIN_CHARGE_IN_PROGRESS, - MAX20335_MAIN_CHARGER_TIMER_DONE, - MAX20335_CHARGER_FAULT_CONDITION, -}; - static const struct linear_range charger_uv_range = LINEAR_RANGE_INIT(MAX20335_REG_CVC_VREG_MIN_UV, MAX20335_REG_CVC_VREG_STEP_UV, @@ -71,6 +60,16 @@ static const struct linear_range charger_uv_range = static int max20335_get_charger_status(const struct device *dev, enum charger_status *status) { + enum { + MAX20335_CHARGER_OFF, + MAX20335_CHARGING_SUSPENDED_DUE_TO_TEMPERATURE, + MAX20335_PRE_CHARGE_IN_PROGRESS, + MAX20335_FAST_CHARGE_IN_PROGRESS_1, + MAX20335_FAST_CHARGE_IN_PROGRESS_2, + MAX20335_MAINTAIN_CHARGE_IN_PROGRESS, + MAX20335_MAIN_CHARGER_TIMER_DONE, + MAX20335_CHARGER_FAULT_CONDITION, + }; const struct charger_max20335_config *const config = dev->config; uint8_t val; int ret; From e38729de63d7a37bf6f15acf0251e492bfeb62e8 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Thu, 1 Feb 2024 12:41:33 +0100 Subject: [PATCH 0179/2402] drivers: charger: charger_max20335: support charger online Add support for charger online property. Signed-off-by: Lukasz Madej --- drivers/charger/charger_max20335.c | 49 ++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index 2b696d8ab83..7564a711e2d 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -18,8 +18,10 @@ LOG_MODULE_REGISTER(max20335_charger); #define MAX20335_REG_STATUS_A 0x02 +#define MAX20335_REG_STATUS_B 0x03 #define MAX20335_REG_INT_A 0x05 #define MAX20335_REG_INT_B 0x06 +#define MAX20335_INT_A_USB_OK_MASK BIT(3) #define MAX20335_INT_A_CHG_STAT_MASK BIT(6) #define MAX20335_REG_INT_MASK_A 0x07 #define MAX20335_REG_INT_MASK_B 0x08 @@ -28,6 +30,7 @@ LOG_MODULE_REGISTER(max20335_charger); #define MAX20335_CHGCNTLA_BAT_REG_CFG_MASK GENMASK(4, 1) #define MAX20335_ILIMCNTL_MASK GENMASK(1, 0) #define MAX20335_STATUS_A_CHG_STAT_MASK GENMASK(2, 0) +#define MAX20335_STATUS_B_USB_OK_MASK BIT(3) #define MAX20335_CHRG_EN_MASK BIT(0) #define MAX20335_CHRG_EN BIT(0) #define MAX20335_REG_CVC_VREG_MIN_UV 4050000U @@ -50,6 +53,7 @@ struct charger_max20335_data { struct k_work int_routine_work; struct k_work_delayable int_enable_work; enum charger_status charger_status; + enum charger_online charger_online; }; static const struct linear_range charger_uv_range = @@ -109,6 +113,35 @@ static int max20335_get_charger_status(const struct device *dev, enum charger_st return 0; } +static int max20335_get_charger_online(const struct device *dev, enum charger_online *online) +{ + enum { + MAX20335_CHGIN_IN_NOT_PRESENT_OR_INVALID, + MAX20335_CHGIN_IN_PRESENT_AND_VALID, + }; + const struct charger_max20335_config *const config = dev->config; + uint8_t val; + int ret; + + ret = i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_STATUS_B, &val); + if (ret) { + return ret; + } + + val = FIELD_GET(MAX20335_STATUS_B_USB_OK_MASK, val); + + switch (val) { + case MAX20335_CHGIN_IN_PRESENT_AND_VALID: + *online = CHARGER_ONLINE_FIXED; + break; + default: + *online = CHARGER_ONLINE_OFFLINE; + break; + }; + + return 0; +} + static int max20335_set_constant_charge_voltage(const struct device *dev, uint32_t voltage_uv) { @@ -276,6 +309,9 @@ static int max20335_get_prop(const struct device *dev, charger_prop_t prop, struct charger_max20335_data *data = dev->data; switch (prop) { + case CHARGER_PROP_ONLINE: + val->online = data->charger_online; + return 0; case CHARGER_PROP_STATUS: val->status = data->charger_status; return 0; @@ -357,6 +393,13 @@ static void max20335_int_routine_work_handler(struct k_work *work) } } + if ((int_src_a & MAX20335_INT_A_USB_OK_MASK) != 0) { + ret = max20335_get_charger_online(data->dev, &data->charger_online); + if (ret < 0) { + LOG_WRN("Failed to read charger online %d", ret); + } + } + ret = k_work_reschedule(&data->int_enable_work, INT_ENABLE_DELAY); if (ret < 0) { LOG_WRN("Could not reschedule int_enable_work: %d", ret); @@ -417,6 +460,12 @@ static int max20335_init(const struct device *dev) return ret; } + ret = max20335_get_charger_online(dev, &data->charger_online); + if (ret != 0) { + LOG_ERR("Failed to read charger online: %d", ret); + return ret; + } + k_work_init(&data->int_routine_work, max20335_int_routine_work_handler); k_work_init_delayable(&data->int_enable_work, max20335_int_enable_work_handler); From d97cebd3ca124eb550f48f47352883b772a75b19 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Thu, 1 Feb 2024 14:14:09 +0100 Subject: [PATCH 0180/2402] drivers: charger: charger_max20335: fix properties set Charger hardware configuration registers are set to zero every time external voltage is applied. Assure proper charger configuration by buffering properties set by application and applying them at external voltage connection event notified via interrupt. Signed-off-by: Lukasz Madej --- drivers/charger/charger_max20335.c | 107 +++++++++++++++++++++++------ 1 file changed, 86 insertions(+), 21 deletions(-) diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index 7564a711e2d..ebe2153f6d3 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -54,6 +54,9 @@ struct charger_max20335_data { struct k_work_delayable int_enable_work; enum charger_status charger_status; enum charger_online charger_online; + bool charger_enabled; + uint32_t charge_current_ua; + uint32_t charge_voltage_uv; }; static const struct linear_range charger_uv_range = @@ -204,8 +207,8 @@ static int max20335_set_constant_charge_current(const struct device *dev, val); } -static int max20335_get_constant_charge_current(const struct device *dev, - uint32_t *current_ua) +static int __maybe_unused max20335_get_constant_charge_current(const struct device *dev, + uint32_t *current_ua) { const struct charger_max20335_config *const config = dev->config; uint8_t val; @@ -236,8 +239,8 @@ static int max20335_get_constant_charge_current(const struct device *dev, return 0; } -static int max20335_get_constant_charge_voltage(const struct device *dev, - uint32_t *voltage_uv) +static int __maybe_unused max20335_get_constant_charge_voltage(const struct device *dev, + uint32_t *voltage_uv) { const struct charger_max20335_config *const config = dev->config; uint8_t val; @@ -255,8 +258,11 @@ static int max20335_get_constant_charge_voltage(const struct device *dev, static int max20335_set_enabled(const struct device *dev, bool enable) { + struct charger_max20335_data *data = dev->data; const struct charger_max20335_config *const config = dev->config; + data->charger_enabled = enable; + return i2c_reg_update_byte_dt(&config->bus, MAX20335_REG_CHG_CNTL_A, MAX20335_CHRG_EN_MASK, @@ -303,6 +309,57 @@ static int max20335_enable_interrupts(const struct device *dev) return i2c_reg_write_byte_dt(&config->bus, MAX20335_REG_INT_MASK_B, 0); } +static int max20335_init_properties(const struct device *dev) +{ + struct charger_max20335_data *data = dev->data; + const struct charger_max20335_config *config = dev->config; + int ret; + + data->charge_current_ua = config->max_ichg_ua; + data->charge_voltage_uv = config->max_vreg_uv; + data->charger_enabled = true; + + ret = max20335_get_charger_status(dev, &data->charger_status); + if (ret < 0) { + LOG_ERR("Failed to read charger status: %d", ret); + return ret; + } + + ret = max20335_get_charger_online(dev, &data->charger_online); + if (ret < 0) { + LOG_ERR("Failed to read charger online: %d", ret); + return ret; + } + + return 0; +} + +static int max20335_update_properties(const struct device *dev) +{ + struct charger_max20335_data *data = dev->data; + int ret; + + ret = max20335_set_constant_charge_current(dev, data->charge_current_ua); + if (ret < 0) { + LOG_ERR("Failed to set charge current: %d", ret); + return ret; + } + + ret = max20335_set_constant_charge_voltage(dev, data->charge_voltage_uv); + if (ret < 0) { + LOG_ERR("Failed to set charge voltage: %d", ret); + return ret; + } + + ret = max20335_set_enabled(dev, data->charger_enabled); + if (ret < 0) { + LOG_ERR("Failed to set enabled: %d", ret); + return ret; + } + + return 0; +} + static int max20335_get_prop(const struct device *dev, charger_prop_t prop, union charger_propval *val) { @@ -316,11 +373,11 @@ static int max20335_get_prop(const struct device *dev, charger_prop_t prop, val->status = data->charger_status; return 0; case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA: - return max20335_get_constant_charge_current(dev, - &val->const_charge_current_ua); + val->const_charge_current_ua = data->charge_current_ua; + return 0; case CHARGER_PROP_CONSTANT_CHARGE_VOLTAGE_UV: - return max20335_get_constant_charge_voltage(dev, - &val->const_charge_voltage_uv); + val->const_charge_voltage_uv = data->charge_voltage_uv; + return 0; default: return -ENOTSUP; } @@ -329,13 +386,24 @@ static int max20335_get_prop(const struct device *dev, charger_prop_t prop, static int max20335_set_prop(const struct device *dev, charger_prop_t prop, const union charger_propval *val) { + struct charger_max20335_data *data = dev->data; + int ret; + switch (prop) { case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA: - return max20335_set_constant_charge_current(dev, - val->const_charge_current_ua); + ret = max20335_set_constant_charge_current(dev, val->const_charge_current_ua); + if (ret == 0) { + data->charge_current_ua = val->const_charge_current_ua; + } + + return ret; case CHARGER_PROP_CONSTANT_CHARGE_VOLTAGE_UV: - return max20335_set_constant_charge_voltage(dev, - val->const_charge_voltage_uv); + ret = max20335_set_constant_charge_voltage(dev, val->const_charge_voltage_uv); + if (ret == 0) { + data->charge_voltage_uv = val->const_charge_voltage_uv; + } + + return ret; default: return -ENOTSUP; } @@ -398,6 +466,10 @@ static void max20335_int_routine_work_handler(struct k_work *work) if (ret < 0) { LOG_WRN("Failed to read charger online %d", ret); } + + if (data->charger_online != CHARGER_ONLINE_OFFLINE) { + (void) max20335_update_properties(data->dev); + } } ret = k_work_reschedule(&data->int_enable_work, INT_ENABLE_DELAY); @@ -454,15 +526,8 @@ static int max20335_init(const struct device *dev) data->dev = dev; - ret = max20335_get_charger_status(dev, &data->charger_status); - if (ret != 0) { - LOG_ERR("Failed to read charger status: %d", ret); - return ret; - } - - ret = max20335_get_charger_online(dev, &data->charger_online); - if (ret != 0) { - LOG_ERR("Failed to read charger online: %d", ret); + ret = max20335_init_properties(dev); + if (ret < 0) { return ret; } From fb99f65fe9a9e7c05f352903a3a41622d61fda8d Mon Sep 17 00:00:00 2001 From: Marcin Gasiorek Date: Tue, 5 Mar 2024 13:44:39 +0100 Subject: [PATCH 0181/2402] net: ip: Fix for improper offset return by `net_pkt_find_offset()` The original packet's link-layer destination and source address can be stored in separately allocated memory. This allocated memory can be placed just after pkt data buffers. In case when `net_pkt_find_offset()` uses condition: `if (buf->data <= ptr && ptr <= (buf->data + buf->len)) {` the offset is set outside the packet's buffer and the function returns incorrect offset instead of error code. Finally the offset is used to set ll address in cloned packet, and this can have unexpected behavior (e.g. crash when cursor will be set to empty memory). Signed-off-by: Marcin Gasiorek --- subsys/net/ip/net_pkt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/ip/net_pkt.c b/subsys/net/ip/net_pkt.c index 38fc288d8f5..d7556a5023d 100644 --- a/subsys/net/ip/net_pkt.c +++ b/subsys/net/ip/net_pkt.c @@ -1817,7 +1817,7 @@ static int32_t net_pkt_find_offset(struct net_pkt *pkt, uint8_t *ptr) buf = pkt->buffer; while (buf) { - if (buf->data <= ptr && ptr <= (buf->data + buf->len)) { + if (buf->data <= ptr && ptr < (buf->data + buf->len)) { ret = offset + (ptr - buf->data); break; } From eaf140e7ff063c2100f8c7dc4402cf6f7ba44506 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Tue, 5 Mar 2024 14:38:32 +0100 Subject: [PATCH 0182/2402] MAINTAINERS: remove inactive CAN collaborator Remove inactive CAN collaborator. Signed-off-by: Henrik Brix Andersen --- MAINTAINERS.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 82b8a2f9344..6e1602dc3fe 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -965,7 +965,6 @@ Release Notes: - henrikbrixandersen collaborators: - alexanderwachter - - karstenkoenig - martinjaeger - str4t0m files: From 0ae587aef9a9a53eec3a1578f4016d31fd1f4122 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 5 Mar 2024 17:50:11 +0000 Subject: [PATCH 0183/2402] it8xxx2_evb: use correct SoC Use SOC_IT81302_BX as the SoC for this board. Fixes #69809 Signed-off-by: Anas Nashif --- boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb | 2 +- boards/ite/it8xxx2_evb/board.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb b/boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb index 9eed36bcacd..8e9b476eb68 100644 --- a/boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb +++ b/boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_IT8XXX2_EVB - select SOC_IT82202_AX + select SOC_IT81302_BX diff --git a/boards/ite/it8xxx2_evb/board.yml b/boards/ite/it8xxx2_evb/board.yml index ff2f8ca7776..a676ec35fa8 100644 --- a/boards/ite/it8xxx2_evb/board.yml +++ b/boards/ite/it8xxx2_evb/board.yml @@ -2,4 +2,4 @@ board: name: it8xxx2_evb vendor: ite socs: - - name: it82202ax + - name: it81302bx From 5f99e771feca8b34171796f9e83e29e80d54524d Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Fri, 1 Mar 2024 21:35:18 +0100 Subject: [PATCH 0184/2402] drivers: can: deprecate can_calc_prescaler() Deprecate the can_calc_prescaler() API function, as it allows for bitrate errors. Bitrate errors between nodes on the same network leads to them drifting apart after the start-of-frame (SOF) synchronization has taken place, leading to bus errors. Signed-off-by: Henrik Brix Andersen --- include/zephyr/drivers/can.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index a4556baedf1..37546cd484f 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -1016,6 +1016,10 @@ __syscall int can_set_bitrate_data(const struct device *dev, uint32_t bitrate_da * The returned bitrate error is remainder of the division of the clock rate by * the bitrate times the timing segments. * + * @deprecated This function allows for bitrate errors, but bitrate errors between nodes on the same + * network leads to them drifting apart after the start-of-frame (SOF) synchronization + * has taken place. + * * @param dev Pointer to the device structure for the driver instance. * @param timing Result is written into the can_timing struct provided. * @param bitrate Target bitrate. @@ -1023,8 +1027,8 @@ __syscall int can_set_bitrate_data(const struct device *dev, uint32_t bitrate_da * @retval 0 or positive bitrate error. * @retval Negative error code on error. */ -int can_calc_prescaler(const struct device *dev, struct can_timing *timing, - uint32_t bitrate); +__deprecated int can_calc_prescaler(const struct device *dev, struct can_timing *timing, + uint32_t bitrate); /** * @brief Configure the bus timing of a CAN controller. From 17b1393f2e5f79a5c74fbffcc5e1265b67082b53 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Sun, 3 Mar 2024 09:22:10 +0100 Subject: [PATCH 0185/2402] doc: releases: release-notes: 3.7: deprecation of can_calc_prescaler() Add a note for the deprecation of can_calc_prescaler(). Signed-off-by: Henrik Brix Andersen --- doc/releases/release-notes-3.7.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index 6ad59d5988f..5d337fbbdf9 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -72,6 +72,10 @@ Drivers and Sensors * CAN + * Deprecated the :c:func:`can_calc_prescaler` API function, as it allows for bitrate + errors. Bitrate errors between nodes on the same network leads to them drifting apart after the + start-of-frame (SOF) synchronization has taken place, leading to bus errors. + * Clock control * Counter From 562ac9d9e69b6a90bf5cf7e3f390c9fe0d3a7790 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Wed, 21 Feb 2024 12:23:35 +0100 Subject: [PATCH 0186/2402] net: Add more specific dependencies for specialized samples Certain samples are supposed to demonstrate technology-specific features, therefore their dependencies in sample.yml could be narrowed to run verify build only on boards which support that specific technology (like Ethernet or OpenThread). Signed-off-by: Robert Lubos --- samples/net/dsa/sample.yaml | 2 +- samples/net/gptp/sample.yaml | 2 +- samples/net/lldp/sample.yaml | 2 +- samples/net/openthread/coprocessor/sample.yaml | 2 +- samples/net/vlan/sample.yaml | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/samples/net/dsa/sample.yaml b/samples/net/dsa/sample.yaml index fd4d4c3c867..fe4bd46d810 100644 --- a/samples/net/dsa/sample.yaml +++ b/samples/net/dsa/sample.yaml @@ -10,4 +10,4 @@ tests: sample.net.dsa: build_only: true platform_allow: ip_k66f - depends_on: netif + depends_on: eth diff --git a/samples/net/gptp/sample.yaml b/samples/net/gptp/sample.yaml index 02591c22a6b..ba77d2eaaba 100644 --- a/samples/net/gptp/sample.yaml +++ b/samples/net/gptp/sample.yaml @@ -18,7 +18,7 @@ tests: - nucleo_f767zi - nucleo_h743zi - nucleo_h745zi_q/stm32h745xx/m7 - depends_on: netif + depends_on: eth integration_platforms: - frdm_k64f sample.net.gpt.nxp_enet_experimental: diff --git a/samples/net/lldp/sample.yaml b/samples/net/lldp/sample.yaml index 4daf567dca2..991133a8d26 100644 --- a/samples/net/lldp/sample.yaml +++ b/samples/net/lldp/sample.yaml @@ -15,4 +15,4 @@ tests: - native_sim_64 integration_platforms: - native_sim - depends_on: netif + depends_on: eth diff --git a/samples/net/openthread/coprocessor/sample.yaml b/samples/net/openthread/coprocessor/sample.yaml index bf2f2a55b32..aa917223de9 100644 --- a/samples/net/openthread/coprocessor/sample.yaml +++ b/samples/net/openthread/coprocessor/sample.yaml @@ -3,7 +3,7 @@ common: tags: - net - openthread - depends_on: netif + depends_on: openthread min_flash: 140 sample: description: Runs the OpenThread stack as NCP BR diff --git a/samples/net/vlan/sample.yaml b/samples/net/vlan/sample.yaml index c364fc40800..06d06ad3a31 100644 --- a/samples/net/vlan/sample.yaml +++ b/samples/net/vlan/sample.yaml @@ -8,4 +8,4 @@ sample: name: VLAN sample app tests: sample.net.vlan: - depends_on: netif + depends_on: eth From 919cb6f614bfc0f76a48944769b9f54f5d3a2383 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Wed, 21 Feb 2024 10:01:43 +0100 Subject: [PATCH 0187/2402] net: sockets: tls: Improve sendmsg() support on DTLS sockets DTLS socket should be able to combine more than one message into a single datagram when calling sendmsg(). Signed-off-by: Robert Lubos --- subsys/net/lib/sockets/Kconfig | 14 ++++ subsys/net/lib/sockets/sockets_tls.c | 119 ++++++++++++++++++++------- 2 files changed, 104 insertions(+), 29 deletions(-) diff --git a/subsys/net/lib/sockets/Kconfig b/subsys/net/lib/sockets/Kconfig index 2ef3e1ba21b..88fa5389528 100644 --- a/subsys/net/lib/sockets/Kconfig +++ b/subsys/net/lib/sockets/Kconfig @@ -188,6 +188,20 @@ config NET_SOCKETS_DTLS_MAX_FRAGMENT_LENGTH With DTLS the MFL should be kept under the network MTU, to avoid IP fragmentation. +config NET_SOCKETS_DTLS_SENDMSG_BUF_SIZE + int "Intermediate buffer size for DTLS sendmsg()" + depends on NET_SOCKETS_ENABLE_DTLS + range 0 65535 + default 0 + help + Size of the intermediate buffer for DTLS sendmsg() function. The + intermediate buffer is needed, as sendmsg() for DGRAM is expected to + send all of the data in a single datagram, therefore all data provided + in msghdr strucure need to be linearized before passing to mbed TLS. + The buffer size can be set to 0, in that case data linearizing for + DTLS sockets is disabled. In result, sendmsg() will only accept msghdr + with a single non-empty iov buffer. + config NET_SOCKETS_TLS_MAX_CONTEXTS int "Maximum number of TLS/DTLS contexts" default 1 diff --git a/subsys/net/lib/sockets/sockets_tls.c b/subsys/net/lib/sockets/sockets_tls.c index e433cdaba76..513d1f68c73 100644 --- a/subsys/net/lib/sockets/sockets_tls.c +++ b/subsys/net/lib/sockets/sockets_tls.c @@ -66,6 +66,12 @@ LOG_MODULE_REGISTER(net_sock_tls, CONFIG_NET_SOCKETS_LOG_LEVEL); #define ALPN_MAX_PROTOCOLS 0 #endif /* CONFIG_NET_SOCKETS_TLS_MAX_APP_PROTOCOLS */ +#if defined(CONFIG_NET_SOCKETS_ENABLE_DTLS) +#define DTLS_SENDMSG_BUF_SIZE (CONFIG_NET_SOCKETS_DTLS_SENDMSG_BUF_SIZE) +#else +#define DTLS_SENDMSG_BUF_SIZE 0 +#endif /* CONFIG_NET_SOCKETS_ENABLE_DTLS */ + static const struct socket_op_vtable tls_sock_fd_op_vtable; #ifndef MBEDTLS_ERR_SSL_PEER_VERIFY_FAILED @@ -2436,15 +2442,94 @@ ssize_t ztls_sendto_ctx(struct tls_context *ctx, const void *buf, size_t len, #endif /* CONFIG_NET_SOCKETS_ENABLE_DTLS */ } +static ssize_t dtls_sendmsg_merge_and_send(struct tls_context *ctx, + const struct msghdr *msg, + int flags) +{ + static K_MUTEX_DEFINE(sendmsg_lock); + static uint8_t sendmsg_buf[DTLS_SENDMSG_BUF_SIZE]; + ssize_t len = 0; + + k_mutex_lock(&sendmsg_lock, K_FOREVER); + + for (int i = 0; i < msg->msg_iovlen; i++) { + struct iovec *vec = msg->msg_iov + i; + + if (vec->iov_len >= 0) { + if (len + vec->iov_len > sizeof(sendmsg_buf)) { + k_mutex_unlock(&sendmsg_lock); + errno = EMSGSIZE; + return -1; + } + + memcpy(sendmsg_buf + len, vec->iov_base, vec->iov_len); + len += vec->iov_len; + } + } + + if (len > 0) { + len = ztls_sendto_ctx(ctx, sendmsg_buf, len, flags, + msg->msg_name, msg->msg_namelen); + } + + k_mutex_unlock(&sendmsg_lock); + + return len; +} + +static ssize_t tls_sendmsg_loop_and_send(struct tls_context *ctx, + const struct msghdr *msg, + int flags) +{ + ssize_t len = 0; + ssize_t ret; + + for (int i = 0; i < msg->msg_iovlen; i++) { + struct iovec *vec = msg->msg_iov + i; + size_t sent = 0; + + if (vec->iov_len == 0) { + continue; + } + + while (sent < vec->iov_len) { + uint8_t *ptr = (uint8_t *)vec->iov_base + sent; + + ret = ztls_sendto_ctx(ctx, ptr, vec->iov_len - sent, + flags, msg->msg_name, + msg->msg_namelen); + if (ret < 0) { + return ret; + } + sent += ret; + } + len += sent; + } + + return len; +} + ssize_t ztls_sendmsg_ctx(struct tls_context *ctx, const struct msghdr *msg, int flags) { - ssize_t len; - ssize_t ret; - int i; + if (msg == NULL) { + errno = EINVAL; + return -1; + } if (IS_ENABLED(CONFIG_NET_SOCKETS_ENABLE_DTLS) && ctx->type == SOCK_DGRAM) { + if (DTLS_SENDMSG_BUF_SIZE > 0) { + /* With one buffer only, there's no need to use + * intermediate buffer. + */ + if (msghdr_non_empty_iov_count(msg) == 1) { + goto send_loop; + } + + return dtls_sendmsg_merge_and_send(ctx, msg, flags); + } + /* * Current mbedTLS API (i.e. mbedtls_ssl_write()) allows only to send a single * contiguous buffer. This means that gather write using sendmsg() can only be @@ -2456,32 +2541,8 @@ ssize_t ztls_sendmsg_ctx(struct tls_context *ctx, const struct msghdr *msg, } } - len = 0; - if (msg) { - for (i = 0; i < msg->msg_iovlen; i++) { - struct iovec *vec = msg->msg_iov + i; - size_t sent = 0; - - if (vec->iov_len == 0) { - continue; - } - - while (sent < vec->iov_len) { - uint8_t *ptr = (uint8_t *)vec->iov_base + sent; - - ret = ztls_sendto_ctx(ctx, ptr, - vec->iov_len - sent, flags, - msg->msg_name, msg->msg_namelen); - if (ret < 0) { - return ret; - } - sent += ret; - } - len += sent; - } - } - - return len; +send_loop: + return tls_sendmsg_loop_and_send(ctx, msg, flags); } static ssize_t recv_tls(struct tls_context *ctx, void *buf, From 88728f32f6ed906533f99d19ae09637444d6f5fe Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Wed, 21 Feb 2024 10:01:47 +0100 Subject: [PATCH 0188/2402] tests: net: sockets: tls: Extend sendmsg tests Add tests that verify that sendmsg() for DTLS works fine if provided with multiple buffers. Modify existing sendmsg() tests, so that we still tests the old behavior if the feature is disabled. Signed-off-by: Robert Lubos --- tests/net/socket/tls/prj.conf | 1 + tests/net/socket/tls/src/main.c | 130 ++++++++++++++++++++++++++++- tests/net/socket/tls/testcase.yaml | 3 + 3 files changed, 133 insertions(+), 1 deletion(-) diff --git a/tests/net/socket/tls/prj.conf b/tests/net/socket/tls/prj.conf index 6a49c5094e6..51e4f7a9032 100644 --- a/tests/net/socket/tls/prj.conf +++ b/tests/net/socket/tls/prj.conf @@ -15,6 +15,7 @@ CONFIG_NET_SOCKETS=y CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_SOCKOPT_TLS=y CONFIG_NET_SOCKETS_ENABLE_DTLS=y +CONFIG_NET_SOCKETS_DTLS_SENDMSG_BUF_SIZE=128 CONFIG_NET_SOCKETS_TLS_MAX_CONTEXTS=4 CONFIG_NET_CONTEXT_RCVTIMEO=y CONFIG_NET_CONTEXT_SNDTIMEO=y diff --git a/tests/net/socket/tls/src/main.c b/tests/net/socket/tls/src/main.c index baeebe2a41b..3dd9f30db0c 100644 --- a/tests/net/socket/tls/src/main.c +++ b/tests/net/socket/tls/src/main.c @@ -598,7 +598,7 @@ static void test_sendmsg_tx_work_handler(struct k_work *work) test_sendmsg(test_data->sock, test_data->msg, 0); } -static void test_dtls_sendmsg(sa_family_t family) +static void test_dtls_sendmsg_no_buf(sa_family_t family) { int rv; uint8_t rx_buf[sizeof(TEST_STR_SMALL) - 1]; @@ -663,13 +663,141 @@ static void test_dtls_sendmsg(sa_family_t family) k_msleep(10); } +ZTEST(net_socket_tls, test_v4_dtls_sendmsg_no_buf) +{ + if (CONFIG_NET_SOCKETS_DTLS_SENDMSG_BUF_SIZE > 0) { + ztest_test_skip(); + } + + test_dtls_sendmsg_no_buf(AF_INET); +} + +ZTEST(net_socket_tls, test_v6_dtls_sendmsg_no_buf) +{ + if (CONFIG_NET_SOCKETS_DTLS_SENDMSG_BUF_SIZE > 0) { + ztest_test_skip(); + } + + test_dtls_sendmsg_no_buf(AF_INET6); +} + +static void test_dtls_sendmsg(sa_family_t family) +{ + int rv; + uint8_t buf[128 + 1] = { 0 }; + uint8_t dummy_byte = 0; + static const char expected_str[] = "testtest"; + struct iovec iov[3] = { + { + .iov_base = TEST_STR_SMALL, + .iov_len = sizeof(TEST_STR_SMALL) - 1, + }, + { + .iov_base = TEST_STR_SMALL, + .iov_len = sizeof(TEST_STR_SMALL) - 1, + }, + {}, + }; + struct msghdr msg = {}; + struct test_sendmsg_data test_data = { + .msg = &msg, + }; + + test_prepare_dtls_connection(family); + + test_data.sock = c_sock; + k_work_init_delayable(&test_data.tx_work, test_sendmsg_tx_work_handler); + + /* sendmsg() with multiple fragments */ + + msg.msg_iov = iov; + msg.msg_iovlen = 2, + + test_work_reschedule(&test_data.tx_work, K_NO_WAIT); + + memset(buf, 0, sizeof(buf)); + rv = recv(s_sock, buf, sizeof(buf), 0); + zassert_equal(rv, sizeof(expected_str) - 1, "recv failed"); + zassert_mem_equal(buf, expected_str, sizeof(expected_str) - 1, "invalid rx data"); + + test_work_wait(&test_data.tx_work); + + /* sendmsg() with multiple fragments and empty fragment inbetween */ + + iov[1].iov_base = NULL; + iov[1].iov_len = 0; + iov[2].iov_base = TEST_STR_SMALL; + iov[2].iov_len = sizeof(TEST_STR_SMALL) - 1; + msg.msg_iov = iov; + msg.msg_iovlen = 3; + + test_work_reschedule(&test_data.tx_work, K_NO_WAIT); + + memset(buf, 0, sizeof(buf)); + rv = recv(s_sock, buf, sizeof(buf), 0); + zassert_equal(rv, sizeof(expected_str) - 1, "recv failed"); + zassert_mem_equal(buf, expected_str, sizeof(expected_str) - 1, "invalid rx data"); + + test_work_wait(&test_data.tx_work); + + /* sendmsg() with single fragment should still work even if larger than + * intermediate buffer size + */ + + memset(buf, 'a', sizeof(buf)); + iov[0].iov_base = buf; + iov[0].iov_len = sizeof(buf); + msg.msg_iov = iov; + msg.msg_iovlen = 1; + + test_work_reschedule(&test_data.tx_work, K_NO_WAIT); + + /* We reuse the buffer, so wait to make sure the message is sent. */ + k_msleep(10); + + memset(buf, 0, sizeof(buf)); + rv = recv(s_sock, buf, sizeof(buf), 0); + zassert_equal(rv, sizeof(buf), "recv failed"); + for (int i = 0; i < sizeof(buf); i++) { + zassert_equal(buf[i], 'a', "invalid rx data"); + } + + test_work_wait(&test_data.tx_work); + + /* sendmsg() exceeding intermediate buf size */ + + iov[0].iov_base = buf; + iov[0].iov_len = sizeof(buf); + iov[1].iov_base = &dummy_byte; + iov[1].iov_len = sizeof(dummy_byte); + msg.msg_iov = iov; + msg.msg_iovlen = 2; + + rv = sendmsg(c_sock, &msg, 0); + zassert_equal(rv, -1, "sendmsg succeeded"); + zassert_equal(errno, EMSGSIZE, "incorrect errno value"); + + test_sockets_close(); + + /* Small delay for the final alert exchange */ + k_msleep(10); +} + ZTEST(net_socket_tls, test_v4_dtls_sendmsg) { + if (CONFIG_NET_SOCKETS_DTLS_SENDMSG_BUF_SIZE == 0) { + ztest_test_skip(); + } + test_dtls_sendmsg(AF_INET); } ZTEST(net_socket_tls, test_v6_dtls_sendmsg) { + if (CONFIG_NET_SOCKETS_DTLS_SENDMSG_BUF_SIZE == 0) { + ztest_test_skip(); + } + test_dtls_sendmsg(AF_INET6); } diff --git a/tests/net/socket/tls/testcase.yaml b/tests/net/socket/tls/testcase.yaml index 00a126769c7..f652305f20b 100644 --- a/tests/net/socket/tls/testcase.yaml +++ b/tests/net/socket/tls/testcase.yaml @@ -18,3 +18,6 @@ tests: extra_configs: - CONFIG_NET_TC_THREAD_PREEMPTIVE=y platform_exclude: mps2/an385 + net.socket.tls.sendmsg_no_buf: + extra_configs: + - CONFIG_NET_SOCKETS_DTLS_SENDMSG_BUF_SIZE=0 From 961b83a431224f57c698b7fe505075f6492536ee Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 5 Mar 2024 07:15:30 -0500 Subject: [PATCH 0189/2402] twister: normalize platform name when packaging When creating a package, normalize platform names. Fixes #69793 Signed-off-by: Anas Nashif --- scripts/pylib/twister/twisterlib/package.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/scripts/pylib/twister/twisterlib/package.py b/scripts/pylib/twister/twisterlib/package.py index aaf065d625d..5ae17e7601c 100644 --- a/scripts/pylib/twister/twisterlib/package.py +++ b/scripts/pylib/twister/twisterlib/package.py @@ -26,7 +26,9 @@ def package(self): jtp = json.load(json_test_plan) for t in jtp['testsuites']: if t['status'] != "filtered": - dirs.append(os.path.join(self.options.outdir, t['platform'], t['name'])) + p = t['platform'] + normalized = p.replace("/", "_") + dirs.append(os.path.join(self.options.outdir, normalized, t['name'])) dirs.extend( [ From c975910f84ffc53eee1f21aaebdcaff8d48c1f7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 22 Jan 2024 13:40:44 +0100 Subject: [PATCH 0190/2402] drivers: spi: nrf: Add new SPIS instances MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for upcomming SPIS instances. Signed-off-by: Krzysztof Chruściński --- drivers/spi/Kconfig.nrfx | 14 ++++++ drivers/spi/spi_nrfx_spis.c | 19 ++------ modules/hal_nordic/nrfx/Kconfig | 70 +++++++++++++++++++++++++++ modules/hal_nordic/nrfx/nrfx_config.h | 42 ++++++++++++++++ soc/nordic/common/Kconfig.peripherals | 42 ++++++++++++++++ 5 files changed, 173 insertions(+), 14 deletions(-) diff --git a/drivers/spi/Kconfig.nrfx b/drivers/spi/Kconfig.nrfx index 4d158b935a7..6e1603ac50b 100644 --- a/drivers/spi/Kconfig.nrfx +++ b/drivers/spi/Kconfig.nrfx @@ -51,6 +51,20 @@ config SPI_NRFX_SPIS select NRFX_SPIS1 if HAS_HW_NRF_SPIS1 select NRFX_SPIS2 if HAS_HW_NRF_SPIS2 select NRFX_SPIS3 if HAS_HW_NRF_SPIS3 + select NRFX_SPIS00 if HAS_HW_NRF_SPIS00 + select NRFX_SPIS20 if HAS_HW_NRF_SPIS20 + select NRFX_SPIS21 if HAS_HW_NRF_SPIS21 + select NRFX_SPIS22 if HAS_HW_NRF_SPIS22 + select NRFX_SPIS30 if HAS_HW_NRF_SPIS30 + select NRFX_SPIS120 if HAS_HW_NRF_SPIS120 + select NRFX_SPIS130 if HAS_HW_NRF_SPIS130 + select NRFX_SPIS131 if HAS_HW_NRF_SPIS131 + select NRFX_SPIS132 if HAS_HW_NRF_SPIS132 + select NRFX_SPIS133 if HAS_HW_NRF_SPIS133 + select NRFX_SPIS134 if HAS_HW_NRF_SPIS134 + select NRFX_SPIS135 if HAS_HW_NRF_SPIS135 + select NRFX_SPIS136 if HAS_HW_NRF_SPIS136 + select NRFX_SPIS137 if HAS_HW_NRF_SPIS137 config SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 depends on SOC_NRF52832 diff --git a/drivers/spi/spi_nrfx_spis.c b/drivers/spi/spi_nrfx_spis.c index d2a61530f00..78bcc9f84be 100644 --- a/drivers/spi/spi_nrfx_spis.c +++ b/drivers/spi/spi_nrfx_spis.c @@ -399,18 +399,9 @@ static int spi_nrfx_init(const struct device *dev) CONFIG_SPI_INIT_PRIORITY, \ &spi_nrfx_driver_api) -#ifdef CONFIG_HAS_HW_NRF_SPIS0 -SPI_NRFX_SPIS_DEFINE(0); -#endif - -#ifdef CONFIG_HAS_HW_NRF_SPIS1 -SPI_NRFX_SPIS_DEFINE(1); -#endif +/* Macro creates device instance if it is enabled in devicetree. */ +#define SPIS_DEVICE(periph, prefix, id, _) \ + IF_ENABLED(CONFIG_HAS_HW_NRF_SPIS##prefix##id, (SPI_NRFX_SPIS_DEFINE(prefix##id);)) -#ifdef CONFIG_HAS_HW_NRF_SPIS2 -SPI_NRFX_SPIS_DEFINE(2); -#endif - -#ifdef CONFIG_HAS_HW_NRF_SPIS3 -SPI_NRFX_SPIS_DEFINE(3); -#endif +/* Macro iterates over nrfx_spis instances enabled in the nrfx_config.h. */ +NRFX_FOREACH_ENABLED(SPIS, SPIS_DEVICE, (), (), _) diff --git a/modules/hal_nordic/nrfx/Kconfig b/modules/hal_nordic/nrfx/Kconfig index a511af42e17..a731013bd4b 100644 --- a/modules/hal_nordic/nrfx/Kconfig +++ b/modules/hal_nordic/nrfx/Kconfig @@ -401,6 +401,76 @@ config NRFX_SPIS3 depends on $(dt_nodelabel_has_compat,spi3,$(DT_COMPAT_NORDIC_NRF_SPIS)) select NRFX_SPIS +config NRFX_SPIS00 + bool "SPIS00 driver instance" + depends on $(dt_nodelabel_has_compat,spi00,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS20 + bool "SPIS20 driver instance" + depends on $(dt_nodelabel_has_compat,spi20,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS21 + bool "SPIS21 driver instance" + depends on $(dt_nodelabel_has_compat,spi21,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS22 + bool "SPIS22 driver instance" + depends on $(dt_nodelabel_has_compat,spi22,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS30 + bool "SPIS30 driver instance" + depends on $(dt_nodelabel_has_compat,spi30,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS120 + bool "SPIS120 driver instance" + depends on $(dt_nodelabel_has_compat,spi120,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS130 + bool "SPIS130 driver instance" + depends on $(dt_nodelabel_has_compat,spi130,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS131 + bool "SPIS131 driver instance" + depends on $(dt_nodelabel_has_compat,spi131,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS132 + bool "SPIS132 driver instance" + depends on $(dt_nodelabel_has_compat,spi132,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS133 + bool "SPIS133 driver instance" + depends on $(dt_nodelabel_has_compat,spi133,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS134 + bool "SPIS134 driver instance" + depends on $(dt_nodelabel_has_compat,spi134,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS135 + bool "SPIS135 driver instance" + depends on $(dt_nodelabel_has_compat,spi135,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS136 + bool "SPIS136 driver instance" + depends on $(dt_nodelabel_has_compat,spi136,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + +config NRFX_SPIS137 + bool "SPIS137 driver instance" + depends on $(dt_nodelabel_has_compat,spi137,$(DT_COMPAT_NORDIC_NRF_SPIS)) + select NRFX_SPIS + config NRFX_SYSTICK bool "SYSTICK driver" depends on CPU_CORTEX_M_HAS_SYSTICK diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index 5ebc243541e..3c923f738a9 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -424,6 +424,48 @@ #ifdef CONFIG_NRFX_SPIS3 #define NRFX_SPIS3_ENABLED 1 #endif +#ifdef CONFIG_NRFX_SPIS00 +#define NRFX_SPIS00_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS20 +#define NRFX_SPIS20_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS21 +#define NRFX_SPIS21_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS22 +#define NRFX_SPIS22_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS30 +#define NRFX_SPIS30_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS120 +#define NRFX_SPIS120_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS130 +#define NRFX_SPIS130_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS131 +#define NRFX_SPIS131_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS132 +#define NRFX_SPIS132_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS133 +#define NRFX_SPIS133_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS134 +#define NRFX_SPIS134_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS135 +#define NRFX_SPIS135_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS136 +#define NRFX_SPIS136_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_SPIS137 +#define NRFX_SPIS130_ENABLED 1 +#endif #ifdef CONFIG_NRFX_SYSTICK #define NRFX_SYSTICK_ENABLED 1 diff --git a/soc/nordic/common/Kconfig.peripherals b/soc/nordic/common/Kconfig.peripherals index ca24384cf8e..7a1c3281dec 100644 --- a/soc/nordic/common/Kconfig.peripherals +++ b/soc/nordic/common/Kconfig.peripherals @@ -291,6 +291,48 @@ config HAS_HW_NRF_SPIS2 config HAS_HW_NRF_SPIS3 def_bool $(dt_nodelabel_enabled_with_compat,spi3,$(DT_COMPAT_NORDIC_NRF_SPIS)) +config HAS_HW_NRF_SPIS00 + def_bool $(dt_nodelabel_enabled_with_compat,spi00,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS20 + def_bool $(dt_nodelabel_enabled_with_compat,spi20,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS21 + def_bool $(dt_nodelabel_enabled_with_compat,spi21,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS22 + def_bool $(dt_nodelabel_enabled_with_compat,spi22,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS30 + def_bool $(dt_nodelabel_enabled_with_compat,spi30,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS120 + def_bool $(dt_nodelabel_enabled_with_compat,spi120,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS130 + def_bool $(dt_nodelabel_enabled_with_compat,spi130,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS131 + def_bool $(dt_nodelabel_enabled_with_compat,spi131,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS132 + def_bool $(dt_nodelabel_enabled_with_compat,spi132,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS133 + def_bool $(dt_nodelabel_enabled_with_compat,spi133,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS134 + def_bool $(dt_nodelabel_enabled_with_compat,spi134,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS135 + def_bool $(dt_nodelabel_enabled_with_compat,spi135,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS136 + def_bool $(dt_nodelabel_enabled_with_compat,spi136,$(DT_COMPAT_NORDIC_NRF_SPIS)) + +config HAS_HW_NRF_SPIS137 + def_bool $(dt_nodelabel_enabled_with_compat,spi137,$(DT_COMPAT_NORDIC_NRF_SPIS)) + config HAS_HW_NRF_SPU def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_SPU)) From 4c880f4b0a5fa6d55d731ddfec8b040361998427 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Sun, 25 Feb 2024 13:12:35 +0000 Subject: [PATCH 0191/2402] drivers: rtc: Create utility function for time validation RTC drivers should validate the `struct rtc_time`'s contents against the provided `mask`. Promote this common code to a new rtc_utils file and modify existing drivers to use this functionality. Extend the test coverage to include verifying this behaviour. This is groundwork ahead of adding support for the RP2040's (as used in the Raspberry Pi Pico) RTC and alarm. Signed-off-by: Andrew Featherstone --- drivers/rtc/CMakeLists.txt | 2 + drivers/rtc/rtc_emul.c | 41 +------------ drivers/rtc/rtc_sam.c | 42 ++------------ drivers/rtc/rtc_utils.c | 58 +++++++++++++++++++ drivers/rtc/rtc_utils.h | 28 +++++++++ tests/drivers/rtc/rtc_api/src/test_alarm.c | 31 ++++++++++ tests/drivers/rtc/rtc_utils/CMakeLists.txt | 13 +++++ tests/drivers/rtc/rtc_utils/prj.conf | 5 ++ tests/drivers/rtc/rtc_utils/src/main.c | 9 +++ .../rtc/rtc_utils/src/test_rtc_utils.c | 36 ++++++++++++ tests/drivers/rtc/rtc_utils/testcase.yaml | 9 +++ 11 files changed, 200 insertions(+), 74 deletions(-) create mode 100644 drivers/rtc/rtc_utils.c create mode 100644 drivers/rtc/rtc_utils.h create mode 100644 tests/drivers/rtc/rtc_utils/CMakeLists.txt create mode 100644 tests/drivers/rtc/rtc_utils/prj.conf create mode 100644 tests/drivers/rtc/rtc_utils/src/main.c create mode 100644 tests/drivers/rtc/rtc_utils/src/test_rtc_utils.c create mode 100644 tests/drivers/rtc/rtc_utils/testcase.yaml diff --git a/drivers/rtc/CMakeLists.txt b/drivers/rtc/CMakeLists.txt index 65d822dbe6e..8bab34ebd31 100644 --- a/drivers/rtc/CMakeLists.txt +++ b/drivers/rtc/CMakeLists.txt @@ -5,6 +5,8 @@ zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/rtc.h) zephyr_library() +zephyr_library_sources(rtc_utils.c) + zephyr_library_sources_ifdef(CONFIG_RTC_AM1805 rtc_am1805.c) zephyr_library_sources_ifdef(CONFIG_RTC_DS1307 rtc_ds1307.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE rtc_handlers.c) diff --git a/drivers/rtc/rtc_emul.c b/drivers/rtc/rtc_emul.c index 9ce6b5dbc25..eb40b9399a4 100644 --- a/drivers/rtc/rtc_emul.c +++ b/drivers/rtc/rtc_emul.c @@ -10,6 +10,8 @@ #include #include +#include "rtc_utils.h" + struct rtc_emul_data; struct rtc_emul_work_delayable { @@ -67,43 +69,6 @@ static bool rtc_emul_is_leap_year(struct rtc_time *datetime) return false; } -#ifdef CONFIG_RTC_ALARM -static bool rtc_emul_validate_alarm_time(const struct rtc_time *timeptr, uint32_t mask) -{ - if ((mask & RTC_ALARM_TIME_MASK_SECOND) && - (timeptr->tm_sec < 0 || timeptr->tm_sec > 59)) { - return false; - } - - if ((mask & RTC_ALARM_TIME_MASK_MINUTE) && - (timeptr->tm_min < 0 || timeptr->tm_min > 59)) { - return false; - } - - if ((mask & RTC_ALARM_TIME_MASK_HOUR) && - (timeptr->tm_hour < 0 || timeptr->tm_hour > 23)) { - return false; - } - - if ((mask & RTC_ALARM_TIME_MASK_MONTH) && - (timeptr->tm_mon < 0 || timeptr->tm_mon > 11)) { - return false; - } - - if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) && - (timeptr->tm_mday < 1 || timeptr->tm_mday > 31)) { - return false; - } - - if ((mask & RTC_ALARM_TIME_MASK_YEAR) && - (timeptr->tm_year < 0 || timeptr->tm_year > 199)) { - return false; - } - - return true; -} -#endif /* CONFIG_RTC_ALARM */ - static int rtc_emul_get_days_in_month(struct rtc_time *datetime) { const uint8_t *dim = (rtc_emul_is_leap_year(datetime) == true) ? @@ -346,7 +311,7 @@ static int rtc_emul_alarm_set_time(const struct device *dev, uint16_t id, uint16 } if (mask > 0) { - if (rtc_emul_validate_alarm_time(timeptr, mask) == false) { + if (rtc_utils_validate_rtc_time(timeptr, mask) == false) { return -EINVAL; } } diff --git a/drivers/rtc/rtc_sam.c b/drivers/rtc/rtc_sam.c index e50edd94e3c..c9868e63652 100644 --- a/drivers/rtc/rtc_sam.c +++ b/drivers/rtc/rtc_sam.c @@ -26,6 +26,11 @@ #define RTC_SAM_CALIBRATE_PPB_QUANTA (1500) #define RTC_SAM_CALIBRATE_PPB_LOW_SCALE (30500) +#define RTC_SAM_TIME_MASK \ + (RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | \ + RTC_ALARM_TIME_MASK_MONTH | RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_YEAR | \ + RTC_ALARM_TIME_MASK_WEEKDAY) + typedef void (*rtc_sam_irq_init_fn_ptr)(void); struct rtc_sam_config { @@ -58,41 +63,6 @@ static void rtc_sam_enable_wp(void) REG_RTC_WPMR = RTC_SAM_WPMR_ENABLE; } -static bool rtc_sam_validate_tm(const struct rtc_time *timeptr, uint32_t mask) -{ - if ((mask & RTC_ALARM_TIME_MASK_SECOND) && - (timeptr->tm_sec < 0 || timeptr->tm_sec > 59)) { - return false; - } - - if ((mask & RTC_ALARM_TIME_MASK_MINUTE) && - (timeptr->tm_min < 0 || timeptr->tm_min > 59)) { - return false; - } - - if ((mask & RTC_ALARM_TIME_MASK_HOUR) && - (timeptr->tm_hour < 0 || timeptr->tm_hour > 23)) { - return false; - } - - if ((mask & RTC_ALARM_TIME_MASK_MONTH) && - (timeptr->tm_mon < 0 || timeptr->tm_mon > 11)) { - return false; - } - - if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) && - (timeptr->tm_mday < 1 || timeptr->tm_mday > 31)) { - return false; - } - - if ((mask & RTC_ALARM_TIME_MASK_YEAR) && - (timeptr->tm_year < 0 || timeptr->tm_year > 199)) { - return false; - } - - return true; -} - static uint32_t rtc_sam_timr_from_tm(const struct rtc_time *timeptr) { uint32_t timr; @@ -126,7 +96,7 @@ static int rtc_sam_set_time(const struct device *dev, const struct rtc_time *tim const struct rtc_sam_config *config = dev->config; Rtc *regs = config->regs; - if (rtc_sam_validate_tm(timeptr, UINT32_MAX) == false) { + if (rtc_utils_validate_rtc_time(timeptr, RTC_SAM_TIME_MASK) == false) { return -EINVAL; } diff --git a/drivers/rtc/rtc_utils.c b/drivers/rtc/rtc_utils.c new file mode 100644 index 00000000000..20e0e8bb78e --- /dev/null +++ b/drivers/rtc/rtc_utils.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2023 Bjarki Arge Andreasen + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include "rtc_utils.h" + +bool rtc_utils_validate_rtc_time(const struct rtc_time *timeptr, uint16_t mask) +{ + if ((mask & RTC_ALARM_TIME_MASK_SECOND) && (timeptr->tm_sec < 0 || timeptr->tm_sec > 59)) { + return false; + } + + if ((mask & RTC_ALARM_TIME_MASK_MINUTE) && (timeptr->tm_min < 0 || timeptr->tm_min > 59)) { + return false; + } + + if ((mask & RTC_ALARM_TIME_MASK_HOUR) && (timeptr->tm_hour < 0 || timeptr->tm_hour > 23)) { + return false; + } + + if ((mask & RTC_ALARM_TIME_MASK_MONTH) && (timeptr->tm_mon < 0 || timeptr->tm_mon > 11)) { + return false; + } + + if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) && + (timeptr->tm_mday < 1 || timeptr->tm_mday > 31)) { + return false; + } + + if ((mask & RTC_ALARM_TIME_MASK_YEAR) && (timeptr->tm_year < 0 || timeptr->tm_year > 199)) { + return false; + } + + if ((mask & RTC_ALARM_TIME_MASK_WEEKDAY) && + (timeptr->tm_wday < 0 || timeptr->tm_wday > 6)) { + return false; + } + + if ((mask & RTC_ALARM_TIME_MASK_YEARDAY) && + (timeptr->tm_yday < 0 || timeptr->tm_yday > 365)) { + return false; + } + + if ((mask & RTC_ALARM_TIME_MASK_NSEC) && + (timeptr->tm_nsec < 0 || timeptr->tm_nsec > 999999999)) { + return false; + } + + return true; +} diff --git a/drivers/rtc/rtc_utils.h b/drivers/rtc/rtc_utils.h new file mode 100644 index 00000000000..1b0953e6c2f --- /dev/null +++ b/drivers/rtc/rtc_utils.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2023 Bjarki Arge Andreasen + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_RTC_RTC_UTILS_H_ +#define ZEPHYR_DRIVERS_RTC_RTC_UTILS_H_ + +#include +#include + +#include + +/** + * @brief Validate a datetime with a mask + * + * Ensure that any fields selected by mask contain a valid value. + * + * @param timeptr The time to set + * @param mask Mask of fields to validate + * + * @return true if the required fields are valid. + */ +bool rtc_utils_validate_rtc_time(const struct rtc_time *timeptr, uint16_t mask); + +#endif /* ZEPHYR_DRIVERS_RTC_RTC_UTILS_H_ */ diff --git a/tests/drivers/rtc/rtc_api/src/test_alarm.c b/tests/drivers/rtc/rtc_api/src/test_alarm.c index 5751524789c..43822089108 100644 --- a/tests/drivers/rtc/rtc_api/src/test_alarm.c +++ b/tests/drivers/rtc/rtc_api/src/test_alarm.c @@ -9,6 +9,7 @@ #include #include #include +#include #include @@ -48,6 +49,36 @@ ZTEST(rtc_api, test_alarm) "Failed to clear and disable alarm callback"); } + /* Every supported alarm field should reject invalid values. */ + for (uint16_t i = 0; i < alarms_count; i++) { + ret = rtc_alarm_get_supported_fields(rtc, i, &alarm_time_mask_supported); + + zassert_ok(ret, "Failed to get supported alarm fields"); + + int *fields[] = { + &alarm_time_set.tm_sec, &alarm_time_set.tm_min, &alarm_time_set.tm_hour, + &alarm_time_set.tm_mday, &alarm_time_set.tm_mon, &alarm_time_set.tm_year, + &alarm_time_set.tm_wday, &alarm_time_set.tm_yday, &alarm_time_set.tm_nsec}; + uint16_t masks[] = {RTC_ALARM_TIME_MASK_SECOND, RTC_ALARM_TIME_MASK_MINUTE, + RTC_ALARM_TIME_MASK_HOUR, RTC_ALARM_TIME_MASK_MONTHDAY, + RTC_ALARM_TIME_MASK_MONTH, RTC_ALARM_TIME_MASK_YEAR, + RTC_ALARM_TIME_MASK_WEEKDAY, RTC_ALARM_TIME_MASK_YEARDAY, + RTC_ALARM_TIME_MASK_NSEC}; + int bad_values[] = {70, 70, 25, 35, 15, 8000, 8, 370, INT32_MAX}; + + ARRAY_FOR_EACH(fields, j) + { + if (masks[j] & alarm_time_mask_supported) { + *fields[j] = bad_values[j]; + ret = rtc_alarm_set_time(rtc, i, masks[j], &alarm_time_set); + zassert_equal( + -EINVAL, ret, + "%s: RTC should reject invalid alarm time in field %zu.", + rtc->name, j); + } + } + } + /* Validate alarms supported fields */ for (uint16_t i = 0; i < alarms_count; i++) { ret = rtc_alarm_get_supported_fields(rtc, i, &alarm_time_mask_supported); diff --git a/tests/drivers/rtc/rtc_utils/CMakeLists.txt b/tests/drivers/rtc/rtc_utils/CMakeLists.txt new file mode 100644 index 00000000000..aac91f6c281 --- /dev/null +++ b/tests/drivers/rtc/rtc_utils/CMakeLists.txt @@ -0,0 +1,13 @@ +# # Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) + +project(rtc_utils) + +target_sources(app PRIVATE + src/main.c + src/test_rtc_utils.c +) diff --git a/tests/drivers/rtc/rtc_utils/prj.conf b/tests/drivers/rtc/rtc_utils/prj.conf new file mode 100644 index 00000000000..64646c7aaf4 --- /dev/null +++ b/tests/drivers/rtc/rtc_utils/prj.conf @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RTC=y +CONFIG_ZTEST=y diff --git a/tests/drivers/rtc/rtc_utils/src/main.c b/tests/drivers/rtc/rtc_utils/src/main.c new file mode 100644 index 00000000000..fe22c136ab1 --- /dev/null +++ b/tests/drivers/rtc/rtc_utils/src/main.c @@ -0,0 +1,9 @@ +/* + * # Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +ZTEST_SUITE(rtc_utils, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/drivers/rtc/rtc_utils/src/test_rtc_utils.c b/tests/drivers/rtc/rtc_utils/src/test_rtc_utils.c new file mode 100644 index 00000000000..88c6da3e2d7 --- /dev/null +++ b/tests/drivers/rtc/rtc_utils/src/test_rtc_utils.c @@ -0,0 +1,36 @@ +/* + * # Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "../../../../drivers/rtc/rtc_utils.h" + +ZTEST(rtc_utils, test_rtc_utils_validate_rtc_time) +{ + /* Arbitrary out-out-range values. */ + const struct rtc_time alarm_time = { + .tm_sec = 70, + .tm_min = 70, + .tm_hour = 25, + .tm_mday = 35, + .tm_mon = 15, + .tm_year = 8000, + .tm_wday = 8, + .tm_yday = 370, + .tm_nsec = INT32_MAX, + }; + uint16_t masks[] = {RTC_ALARM_TIME_MASK_SECOND, RTC_ALARM_TIME_MASK_MINUTE, + RTC_ALARM_TIME_MASK_HOUR, RTC_ALARM_TIME_MASK_MONTHDAY, + RTC_ALARM_TIME_MASK_MONTH, RTC_ALARM_TIME_MASK_YEAR, + RTC_ALARM_TIME_MASK_WEEKDAY, RTC_ALARM_TIME_MASK_YEARDAY, + RTC_ALARM_TIME_MASK_NSEC}; + ARRAY_FOR_EACH(masks, j) + { + bool ret = rtc_utils_validate_rtc_time(&alarm_time, masks[j]); + + zassert_false(ret, "RTC should reject invalid alarm time in field %zu.", j); + } +} diff --git a/tests/drivers/rtc/rtc_utils/testcase.yaml b/tests/drivers/rtc/rtc_utils/testcase.yaml new file mode 100644 index 00000000000..992fac141b8 --- /dev/null +++ b/tests/drivers/rtc/rtc_utils/testcase.yaml @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +tests: + drivers.rtc.rtc_utils: + tags: + - drivers + - rtc + depends_on: rtc From df8c89b52876353302be1722d25d8e709cae2295 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Tue, 7 Nov 2023 16:14:09 +0000 Subject: [PATCH 0192/2402] drivers: rtc: rpi_pico: Add support for the Raspberry Pi Pico RTC This adds the minimal get_time/set_time support for the rp2040 and enables support by default on the Pico boards. This doesn't support configuring the clock source or alarm interrupts yet. Signed-off-by: Andrew Featherstone --- .../raspberrypi/rpi_pico/rpi_pico-common.dtsi | 6 + drivers/rtc/CMakeLists.txt | 1 + drivers/rtc/Kconfig | 5 +- drivers/rtc/Kconfig.rpi_pico | 9 ++ drivers/rtc/rtc_rpi_pico.c | 112 ++++++++++++++++++ dts/arm/rpi_pico/rp2040.dtsi | 8 ++ dts/bindings/rtc/raspberrypi,pico-rtc.yaml | 12 ++ modules/hal_rpi_pico/CMakeLists.txt | 5 + modules/hal_rpi_pico/Kconfig | 5 + 9 files changed, 161 insertions(+), 2 deletions(-) create mode 100644 drivers/rtc/Kconfig.rpi_pico create mode 100644 drivers/rtc/rtc_rpi_pico.c create mode 100644 dts/bindings/rtc/raspberrypi,pico-rtc.yaml diff --git a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi index 95a27d3a009..9c7f1da1817 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi +++ b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi @@ -24,6 +24,7 @@ }; aliases { + rtc = &rtc; watchdog0 = &wdt0; }; @@ -133,6 +134,11 @@ status = "okay"; }; +&rtc { + clocks = <&clocks RPI_PICO_CLKID_CLK_RTC>; + status = "okay"; +}; + &adc { status = "okay"; pinctrl-0 = <&adc_default>; diff --git a/drivers/rtc/CMakeLists.txt b/drivers/rtc/CMakeLists.txt index 8bab34ebd31..26ea1a56567 100644 --- a/drivers/rtc/CMakeLists.txt +++ b/drivers/rtc/CMakeLists.txt @@ -19,3 +19,4 @@ zephyr_library_sources_ifdef(CONFIG_RTC_SHELL rtc_shell.c) zephyr_library_sources_ifdef(CONFIG_RTC_FAKE rtc_fake.c) zephyr_library_sources_ifdef(CONFIG_RTC_SMARTBOND rtc_smartbond.c) zephyr_library_sources_ifdef(CONFIG_RTC_ATMEL_SAM rtc_sam.c) +zephyr_library_sources_ifdef(CONFIG_RTC_RPI_PICO rtc_rpi_pico.c) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 10b228ceeab..3b44235b75c 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -45,11 +45,12 @@ source "drivers/rtc/Kconfig.am1805" source "drivers/rtc/Kconfig.ds1307" source "drivers/rtc/Kconfig.emul" source "drivers/rtc/Kconfig.fake" +source "drivers/rtc/Kconfig.mc146818" source "drivers/rtc/Kconfig.pcf8523" source "drivers/rtc/Kconfig.pcf8563" -source "drivers/rtc/Kconfig.mc146818" +source "drivers/rtc/Kconfig.rpi_pico" source "drivers/rtc/Kconfig.sam" -source "drivers/rtc/Kconfig.stm32" source "drivers/rtc/Kconfig.smartbond" +source "drivers/rtc/Kconfig.stm32" endif # RTC diff --git a/drivers/rtc/Kconfig.rpi_pico b/drivers/rtc/Kconfig.rpi_pico new file mode 100644 index 00000000000..24a872258ff --- /dev/null +++ b/drivers/rtc/Kconfig.rpi_pico @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +config RTC_RPI_PICO + bool "Raspberry Pi Pico RTC driver" + default y + depends on DT_HAS_RASPBERRYPI_PICO_RTC_ENABLED + select PICOSDK_USE_RTC + depends on RESET diff --git a/drivers/rtc/rtc_rpi_pico.c b/drivers/rtc/rtc_rpi_pico.c new file mode 100644 index 00000000000..f628d2e9708 --- /dev/null +++ b/drivers/rtc/rtc_rpi_pico.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define DT_DRV_COMPAT raspberrypi_pico_rtc + +#define CLK_DRV DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)) +#define CLK_ID (clock_control_subsys_t) DT_INST_PHA_BY_IDX(0, clocks, 0, clk_id) + +/* struct tm start time: 1st, Jan, 1900 */ +#define TM_YEAR_REF 1900 +/* See section 4.8.1 of the RP2040 datasheet. */ +#define RP2040_RTC_YEAR_MAX 4095 +struct rtc_rpi_pico_data { + struct k_spinlock lock; +}; + +LOG_MODULE_REGISTER(rtc_rpi, CONFIG_RTC_LOG_LEVEL); + +static int rtc_rpi_pico_init(const struct device *dev) +{ + int ret; + + ret = clock_control_on(CLK_DRV, CLK_ID); + if (ret < 0) { + return ret; + } + + rtc_init(); + return 0; +} + +static int rtc_rpi_pico_set_time(const struct device *dev, const struct rtc_time *timeptr) +{ + struct rtc_rpi_pico_data *data = dev->data; + int err = 0; + + if (timeptr->tm_year + TM_YEAR_REF > RP2040_RTC_YEAR_MAX) { + return -EINVAL; + } + + if (timeptr->tm_wday == -1) { + /* day of the week is expected */ + return -EINVAL; + } + + k_spinlock_key_t key = k_spin_lock(&data->lock); + datetime_t dt = { + .year = timeptr->tm_year + TM_YEAR_REF, + .month = timeptr->tm_mon + 1, + .day = timeptr->tm_mday, + .dotw = timeptr->tm_wday, + .hour = timeptr->tm_hour, + .min = timeptr->tm_min, + .sec = timeptr->tm_sec, + }; + /* Use the validation in the Pico SDK. */ + if (!rtc_set_datetime(&dt)) { + err = -EINVAL; + } + k_spin_unlock(&data->lock, key); + + return err; +} + +static int rtc_rpi_pico_get_time(const struct device *dev, struct rtc_time *timeptr) +{ + struct rtc_rpi_pico_data *data = dev->data; + datetime_t dt; + int err = 0; + k_spinlock_key_t key = k_spin_lock(&data->lock); + + if (!rtc_get_datetime(&dt)) { + err = -ENODATA; + } + + timeptr->tm_sec = dt.sec; + timeptr->tm_min = dt.min; + timeptr->tm_hour = dt.hour; + timeptr->tm_mday = dt.day; + timeptr->tm_mon = dt.month - 1; + timeptr->tm_year = dt.year - TM_YEAR_REF; + timeptr->tm_wday = dt.dotw; + /* unknown values */ + timeptr->tm_yday = -1; + timeptr->tm_isdst = -1; + timeptr->tm_nsec = 0; + k_spin_unlock(&data->lock, key); + + return err; +} + +static const struct rtc_driver_api rtc_rpi_pico_driver_api = { + .set_time = rtc_rpi_pico_set_time, + .get_time = rtc_rpi_pico_get_time, +}; + +static struct rtc_rpi_pico_data rtc_data; + +DEVICE_DT_INST_DEFINE(0, &rtc_rpi_pico_init, NULL, &rtc_data, NULL, POST_KERNEL, + CONFIG_RTC_INIT_PRIORITY, &rtc_rpi_pico_driver_api); diff --git a/dts/arm/rpi_pico/rp2040.dtsi b/dts/arm/rpi_pico/rp2040.dtsi index 72c71bfcfdc..4635aabd752 100644 --- a/dts/arm/rpi_pico/rp2040.dtsi +++ b/dts/arm/rpi_pico/rp2040.dtsi @@ -399,6 +399,14 @@ resets = <&reset RPI_PICO_RESETS_RESET_PIO1>; status = "disabled"; }; + + rtc: rtc@4005c000 { + compatible = "raspberrypi,pico-rtc"; + reg = <0x4005c000 DT_SIZE_K(4)>; + interrupts = <25 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + resets = <&reset RPI_PICO_RESETS_RESET_RTC>; + status = "disabled"; + }; }; pinctrl: pin-controller { diff --git a/dts/bindings/rtc/raspberrypi,pico-rtc.yaml b/dts/bindings/rtc/raspberrypi,pico-rtc.yaml new file mode 100644 index 00000000000..b947a9fc6d6 --- /dev/null +++ b/dts/bindings/rtc/raspberrypi,pico-rtc.yaml @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +description: RaspberryPi Pico RTC + +compatible: "raspberrypi,pico-rtc" + +include: [rtc.yaml, reset-device.yaml] + +properties: + reg: + required: true diff --git a/modules/hal_rpi_pico/CMakeLists.txt b/modules/hal_rpi_pico/CMakeLists.txt index 6474b18055e..b68c2efdb37 100644 --- a/modules/hal_rpi_pico/CMakeLists.txt +++ b/modules/hal_rpi_pico/CMakeLists.txt @@ -113,6 +113,11 @@ if(CONFIG_HAS_RPI_PICO) zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_CLAIM ${rp2_common_dir}/hardware_claim/include) + zephyr_library_sources_ifdef(CONFIG_PICOSDK_USE_RTC + ${rp2_common_dir}/hardware_rtc/rtc.c) + zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_RTC + ${rp2_common_dir}/hardware_rtc/include) + # Some flash driver functions must be executed from the RAM. # Originally pico-sdk places them in the RW data section, so this # implementation does the same. diff --git a/modules/hal_rpi_pico/Kconfig b/modules/hal_rpi_pico/Kconfig index 56f92ea427e..3c37c84f4c0 100644 --- a/modules/hal_rpi_pico/Kconfig +++ b/modules/hal_rpi_pico/Kconfig @@ -49,3 +49,8 @@ config PICOSDK_USE_TIMER bool help Use the TIMER driver from pico-sdk + +config PICOSDK_USE_RTC + bool + help + Use the RTC driver from pico-sdk From 1c50ba489fe3e7419d4a7f3163af9b786d6b77a1 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Thu, 16 Nov 2023 22:35:22 +0000 Subject: [PATCH 0193/2402] drivers: rtc: rpi_pico: Add alarm support to RPi Pico RTC driver This adds support for the alarm functionality of the RPi Pico RTC. Signed-off-by: Andrew Featherstone --- drivers/rtc/rtc_rpi_pico.c | 215 ++++++++++++++++++++- dts/arm/rpi_pico/rp2040.dtsi | 2 + dts/bindings/rtc/raspberrypi,pico-rtc.yaml | 2 +- tests/drivers/rtc/rtc_api/src/test_alarm.c | 20 +- 4 files changed, 228 insertions(+), 11 deletions(-) diff --git a/drivers/rtc/rtc_rpi_pico.c b/drivers/rtc/rtc_rpi_pico.c index f628d2e9708..84a0d2a4dec 100644 --- a/drivers/rtc/rtc_rpi_pico.c +++ b/drivers/rtc/rtc_rpi_pico.c @@ -11,7 +11,11 @@ #include #include +#include #include +#include + +#include "rtc_utils.h" #define DT_DRV_COMPAT raspberrypi_pico_rtc @@ -22,21 +26,72 @@ #define TM_YEAR_REF 1900 /* See section 4.8.1 of the RP2040 datasheet. */ #define RP2040_RTC_YEAR_MAX 4095 +#ifdef CONFIG_RTC_ALARM +static int rtc_rpi_pico_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask, + struct rtc_time *timeptr); +#endif struct rtc_rpi_pico_data { struct k_spinlock lock; + +#ifdef CONFIG_RTC_ALARM + struct rtc_time alarm_time; + uint16_t alarm_mask; + rtc_alarm_callback alarm_callback; + void *alarm_user_data; + bool alarm_pending; +#endif /* CONFIG_RTC_ALARM */ }; +static struct rtc_rpi_pico_data rtc_data; + LOG_MODULE_REGISTER(rtc_rpi, CONFIG_RTC_LOG_LEVEL); +#ifdef CONFIG_RTC_ALARM +static void rtc_rpi_isr(const struct device *dev) +{ + struct rtc_rpi_pico_data *data = dev->data; + + rtc_alarm_callback callback; + void *user_data; + + rtc_disable_alarm(); + + K_SPINLOCK(&data->lock) { + callback = data->alarm_callback; + user_data = data->alarm_user_data; + } + + if (callback != NULL) { + callback(dev, 0, user_data); + } else { + data->alarm_pending = true; + } + /* re-enable the alarm. */ + rtc_enable_alarm(); +} +#endif + static int rtc_rpi_pico_init(const struct device *dev) { int ret; +#ifdef CONFIG_RTC_ALARM + struct rtc_rpi_pico_data *data = dev->data; +#endif ret = clock_control_on(CLK_DRV, CLK_ID); if (ret < 0) { return ret; } +#ifdef CONFIG_RTC_ALARM + data->alarm_mask = 0; + data->alarm_callback = NULL; + data->alarm_pending = false; + + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), rtc_rpi_isr, DEVICE_DT_INST_GET(0), + 0); + irq_enable(DT_INST_IRQN(0)); +#endif rtc_init(); return 0; } @@ -101,12 +156,168 @@ static int rtc_rpi_pico_get_time(const struct device *dev, struct rtc_time *time return err; } +#if defined(CONFIG_RTC_ALARM) +static int rtc_rpi_pico_alarm_get_supported_fields(const struct device *dev, uint16_t id, + uint16_t *supported_fields) +{ + ARG_UNUSED(dev); + + if (id != 0) { + return -EINVAL; + } + *supported_fields = RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | + RTC_ALARM_TIME_MASK_HOUR | RTC_ALARM_TIME_MASK_WEEKDAY | + RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_MONTH | + RTC_ALARM_TIME_MASK_YEAR; + + return 0; +} + +static int rtc_rpi_pico_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask, + const struct rtc_time *alarm) +{ + struct rtc_rpi_pico_data *data = dev->data; + int err = 0; + uint16_t mask_available; + + (void)rtc_rpi_pico_alarm_get_supported_fields(NULL, 0, &mask_available); + + if (mask & ~mask_available) { + return -EINVAL; + } + + if (!rtc_utils_validate_rtc_time(alarm, mask)) { + return -EINVAL; + } + + LOG_INF("Setting alarm"); + + rtc_disable_alarm(); + if (mask == 0) { + /* Disable the alarm */ + data->alarm_mask = 0; + } + k_spinlock_key_t key = k_spin_lock(&data->lock); + + /* Clear before updating. */ + rtc_hw->irq_setup_0 = 0; + rtc_hw->irq_setup_1 = 0; + + /* Set the match enable bits for things we care about */ + if (mask & RTC_ALARM_TIME_MASK_YEAR) { + hw_set_bits(&rtc_hw->irq_setup_0, + RTC_IRQ_SETUP_0_YEAR_ENA_BITS | + ((alarm->tm_year + TM_YEAR_REF) << RTC_IRQ_SETUP_0_YEAR_LSB)); + } + if (mask & RTC_ALARM_TIME_MASK_MONTH) { + hw_set_bits(&rtc_hw->irq_setup_0, + RTC_IRQ_SETUP_0_MONTH_ENA_BITS | + (alarm->tm_mon << RTC_IRQ_SETUP_0_MONTH_LSB)); + } + if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) { + hw_set_bits(&rtc_hw->irq_setup_0, + RTC_IRQ_SETUP_0_DAY_ENA_BITS | + ((alarm->tm_mday + 1) << RTC_IRQ_SETUP_0_DAY_LSB)); + } + if (mask & RTC_ALARM_TIME_MASK_WEEKDAY) { + hw_set_bits(&rtc_hw->irq_setup_1, + RTC_IRQ_SETUP_1_DOTW_ENA_BITS | + (alarm->tm_wday << RTC_IRQ_SETUP_1_DOTW_LSB)); + } + if (mask & RTC_ALARM_TIME_MASK_HOUR) { + hw_set_bits(&rtc_hw->irq_setup_1, + RTC_IRQ_SETUP_1_HOUR_ENA_BITS | + (alarm->tm_hour << RTC_IRQ_SETUP_1_HOUR_LSB)); + } + if (mask & RTC_ALARM_TIME_MASK_MINUTE) { + hw_set_bits(&rtc_hw->irq_setup_1, + RTC_IRQ_SETUP_1_MIN_ENA_BITS | + (alarm->tm_min << RTC_IRQ_SETUP_1_MIN_LSB)); + } + if (mask & RTC_ALARM_TIME_MASK_SECOND) { + hw_set_bits(&rtc_hw->irq_setup_1, + RTC_IRQ_SETUP_1_SEC_ENA_BITS | + (alarm->tm_sec << RTC_IRQ_SETUP_1_SEC_LSB)); + } + data->alarm_time = *alarm; + data->alarm_mask = mask; + k_spin_unlock(&data->lock, key); + + /* Enable the IRQ at the peri */ + rtc_hw->inte = RTC_INTE_RTC_BITS; + + rtc_enable_alarm(); + + return err; +} + +static int rtc_rpi_pico_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask, + struct rtc_time *timeptr) +{ + struct rtc_rpi_pico_data *data = dev->data; + + if (id != 0) { + return -EINVAL; + } + + K_SPINLOCK(&data->lock) { + *timeptr = data->alarm_time; + *mask = data->alarm_mask; + } + + return 0; +} + +static int rtc_rpi_pico_alarm_is_pending(const struct device *dev, uint16_t id) +{ + struct rtc_rpi_pico_data *data = dev->data; + int ret = 0; + + if (id != 0) { + return -EINVAL; + } + + K_SPINLOCK(&data->lock) { + ret = data->alarm_pending ? 1 : 0; + data->alarm_pending = false; + } + + return ret; +} + +static int rtc_rpi_pico_alarm_set_callback(const struct device *dev, uint16_t id, + rtc_alarm_callback callback, void *user_data) +{ + struct rtc_rpi_pico_data *data = dev->data; + + if (id != 0) { + return -EINVAL; + } + + K_SPINLOCK(&data->lock) { + data->alarm_callback = callback; + data->alarm_user_data = user_data; + if ((callback == NULL) && (user_data == NULL)) { + rtc_disable_alarm(); + } + } + + return 0; +} + +#endif /* CONFIG_RTC_ALARM */ + static const struct rtc_driver_api rtc_rpi_pico_driver_api = { .set_time = rtc_rpi_pico_set_time, .get_time = rtc_rpi_pico_get_time, +#if defined(CONFIG_RTC_ALARM) + .alarm_get_supported_fields = rtc_rpi_pico_alarm_get_supported_fields, + .alarm_set_time = rtc_rpi_pico_alarm_set_time, + .alarm_get_time = rtc_rpi_pico_alarm_get_time, + .alarm_is_pending = rtc_rpi_pico_alarm_is_pending, + .alarm_set_callback = rtc_rpi_pico_alarm_set_callback, +#endif /* CONFIG_RTC_ALARM */ }; -static struct rtc_rpi_pico_data rtc_data; - DEVICE_DT_INST_DEFINE(0, &rtc_rpi_pico_init, NULL, &rtc_data, NULL, POST_KERNEL, CONFIG_RTC_INIT_PRIORITY, &rtc_rpi_pico_driver_api); diff --git a/dts/arm/rpi_pico/rp2040.dtsi b/dts/arm/rpi_pico/rp2040.dtsi index 4635aabd752..e04af802277 100644 --- a/dts/arm/rpi_pico/rp2040.dtsi +++ b/dts/arm/rpi_pico/rp2040.dtsi @@ -404,7 +404,9 @@ compatible = "raspberrypi,pico-rtc"; reg = <0x4005c000 DT_SIZE_K(4)>; interrupts = <25 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "rtc"; resets = <&reset RPI_PICO_RESETS_RESET_RTC>; + alarms-count = <1>; status = "disabled"; }; }; diff --git a/dts/bindings/rtc/raspberrypi,pico-rtc.yaml b/dts/bindings/rtc/raspberrypi,pico-rtc.yaml index b947a9fc6d6..cba7a708af8 100644 --- a/dts/bindings/rtc/raspberrypi,pico-rtc.yaml +++ b/dts/bindings/rtc/raspberrypi,pico-rtc.yaml @@ -5,7 +5,7 @@ description: RaspberryPi Pico RTC compatible: "raspberrypi,pico-rtc" -include: [rtc.yaml, reset-device.yaml] +include: [rtc-device.yaml, reset-device.yaml] properties: reg: diff --git a/tests/drivers/rtc/rtc_api/src/test_alarm.c b/tests/drivers/rtc/rtc_api/src/test_alarm.c index 43822089108..fcaf187dbf6 100644 --- a/tests/drivers/rtc/rtc_api/src/test_alarm.c +++ b/tests/drivers/rtc/rtc_api/src/test_alarm.c @@ -55,21 +55,25 @@ ZTEST(rtc_api, test_alarm) zassert_ok(ret, "Failed to get supported alarm fields"); - int *fields[] = { - &alarm_time_set.tm_sec, &alarm_time_set.tm_min, &alarm_time_set.tm_hour, - &alarm_time_set.tm_mday, &alarm_time_set.tm_mon, &alarm_time_set.tm_year, - &alarm_time_set.tm_wday, &alarm_time_set.tm_yday, &alarm_time_set.tm_nsec}; + alarm_time_set = (struct rtc_time) { + .tm_sec = 70, + .tm_min = 70, + .tm_hour = 25, + .tm_mday = 35, + .tm_mon = 15, + .tm_year = 8000, + .tm_wday = 8, + .tm_yday = 370, + .tm_nsec = INT32_MAX, + }; uint16_t masks[] = {RTC_ALARM_TIME_MASK_SECOND, RTC_ALARM_TIME_MASK_MINUTE, RTC_ALARM_TIME_MASK_HOUR, RTC_ALARM_TIME_MASK_MONTHDAY, RTC_ALARM_TIME_MASK_MONTH, RTC_ALARM_TIME_MASK_YEAR, RTC_ALARM_TIME_MASK_WEEKDAY, RTC_ALARM_TIME_MASK_YEARDAY, RTC_ALARM_TIME_MASK_NSEC}; - int bad_values[] = {70, 70, 25, 35, 15, 8000, 8, 370, INT32_MAX}; - - ARRAY_FOR_EACH(fields, j) + ARRAY_FOR_EACH(masks, j) { if (masks[j] & alarm_time_mask_supported) { - *fields[j] = bad_values[j]; ret = rtc_alarm_set_time(rtc, i, masks[j], &alarm_time_set); zassert_equal( -EINVAL, ret, From dcce9f5ba09869183f3de7d8f6e8047b27114d68 Mon Sep 17 00:00:00 2001 From: Mykola Kvach Date: Tue, 9 Jan 2024 11:20:41 +0200 Subject: [PATCH 0194/2402] drivers: pinctrl: r8a779f0: move pfc file from soc to driver dir Move pfc_r8a779f0.c from the 'soc' directory to the 'drivers' directory to avoid code duplication for the ARM64 Spider board. Signed-off-by: Mykola Kvach --- drivers/pinctrl/CMakeLists.txt | 1 + {soc/renesas/rcar/rcar_gen4 => drivers/pinctrl}/pfc_r8a779f0.c | 2 +- soc/renesas/rcar/rcar_gen4/CMakeLists.txt | 1 - 3 files changed, 2 insertions(+), 2 deletions(-) rename {soc/renesas/rcar/rcar_gen4 => drivers/pinctrl}/pfc_r8a779f0.c (99%) diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 9f104c6e323..88c4750a735 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -11,6 +11,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_ITE_IT8XXX2 pinctrl_ite_it8xxx2.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NPCX pinctrl_npcx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMICRO pinctrl_numicro.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c) +zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RCAR_PFC pfc_rcar.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM pinctrl_sam.c) diff --git a/soc/renesas/rcar/rcar_gen4/pfc_r8a779f0.c b/drivers/pinctrl/pfc_r8a779f0.c similarity index 99% rename from soc/renesas/rcar/rcar_gen4/pfc_r8a779f0.c rename to drivers/pinctrl/pfc_r8a779f0.c index 25eba334d77..b72d0ee2b1c 100644 --- a/soc/renesas/rcar/rcar_gen4/pfc_r8a779f0.c +++ b/drivers/pinctrl/pfc_r8a779f0.c @@ -6,7 +6,7 @@ */ #include -#include "pinctrl_soc.h" +#include #include const struct pfc_drive_reg pfc_drive_regs[] = { diff --git a/soc/renesas/rcar/rcar_gen4/CMakeLists.txt b/soc/renesas/rcar/rcar_gen4/CMakeLists.txt index 79be28ffe55..691c155c6e3 100644 --- a/soc/renesas/rcar/rcar_gen4/CMakeLists.txt +++ b/soc/renesas/rcar/rcar_gen4/CMakeLists.txt @@ -2,5 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) -zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") From 0dfb737c6a451611c0930787073f14d6e6804394 Mon Sep 17 00:00:00 2001 From: Mykola Kvach Date: Tue, 9 Jan 2024 17:56:58 +0200 Subject: [PATCH 0195/2402] soc: renesas_rcar: make common pinctrl header for both arm and arm64 archs Make common pinctrl header for both arm and arm64 archs in order to avoid code duplicates. Signed-off-by: Mykola Kvach --- .../drivers/pinctrl/pinctrl_rcar_common.h | 0 soc/renesas/rcar/CMakeLists.txt | 1 - soc/renesas/rcar/rcar_gen3/a57/pinctrl_soc.h | 111 +----------------- soc/renesas/rcar/rcar_gen3/r7/pinctrl_soc.h | 2 +- soc/renesas/rcar/rcar_gen4/pinctrl_soc.h | 2 +- 5 files changed, 4 insertions(+), 112 deletions(-) rename soc/renesas/rcar/common/pinctrl_rcar.h => include/zephyr/drivers/pinctrl/pinctrl_rcar_common.h (100%) diff --git a/soc/renesas/rcar/common/pinctrl_rcar.h b/include/zephyr/drivers/pinctrl/pinctrl_rcar_common.h similarity index 100% rename from soc/renesas/rcar/common/pinctrl_rcar.h rename to include/zephyr/drivers/pinctrl/pinctrl_rcar_common.h diff --git a/soc/renesas/rcar/CMakeLists.txt b/soc/renesas/rcar/CMakeLists.txt index 20bed32f36a..226f3bd626f 100644 --- a/soc/renesas/rcar/CMakeLists.txt +++ b/soc/renesas/rcar/CMakeLists.txt @@ -1,4 +1,3 @@ # SPDX-License-Identifier: Apache-2.0 add_subdirectory(${SOC_SERIES}) -zephyr_include_directories(common) diff --git a/soc/renesas/rcar/rcar_gen3/a57/pinctrl_soc.h b/soc/renesas/rcar/rcar_gen3/a57/pinctrl_soc.h index 0b80eb46634..e02785efd7f 100644 --- a/soc/renesas/rcar/rcar_gen3/a57/pinctrl_soc.h +++ b/soc/renesas/rcar/rcar_gen3/a57/pinctrl_soc.h @@ -1,119 +1,12 @@ /* * Copyright (c) 2021 IoT.bzh + * Copyright (c) 2024 EPAM Systems * * SPDX-License-Identifier: Apache-2.0 - * */ #ifndef ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_ #define ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_ - -#include -#include -#include -#include - -struct rcar_pin_func { - uint8_t bank:5; /* bank number 0 - 18 */ - uint8_t shift:5; /* bit shift 0 - 28 */ - uint8_t func:4; /* choice from 0x0 to 0xF */ -}; -/** Pull-up, pull-down, or bias disable is requested */ -#define RCAR_PIN_FLAGS_PULL_SET BIT(0) -/** Performs on/off control of the pull resistors */ -#define RCAR_PIN_FLAGS_PUEN BIT(1) -/** Select pull-up resistor if set pull-down otherwise */ -#define RCAR_PIN_FLAGS_PUD BIT(2) -/** Alternate function for the pin is requested */ -#define RCAR_PIN_FLAGS_FUNC_SET BIT(3) - -#define RCAR_PIN_PULL_UP (RCAR_PIN_FLAGS_PULL_SET | RCAR_PIN_FLAGS_PUEN | RCAR_PIN_FLAGS_PUD) -#define RCAR_PIN_PULL_DOWN (RCAR_PIN_FLAGS_PULL_SET | RCAR_PIN_FLAGS_PUEN) -#define RCAR_PIN_PULL_DISABLE RCAR_PIN_FLAGS_PULL_SET - -/** Type for R-Car pin. */ -typedef struct pinctrl_soc_pin { - uint16_t pin; - struct rcar_pin_func func; - uint8_t flags; - uint8_t drive_strength; - uint8_t voltage; -} pinctrl_soc_pin_t; - -#define RCAR_IPSR(node_id) DT_PROP_BY_IDX(node_id, pin, 1) -#define RCAR_HAS_IPSR(node_id) DT_PROP_HAS_IDX(node_id, pin, 1) - -/* Offsets are defined in dt-bindings pinctrl-rcar-common.h */ -#define RCAR_PIN_FUNC(node_id) \ - { \ - ((RCAR_IPSR(node_id) >> 10U) & 0x1FU), \ - ((RCAR_IPSR(node_id) >> 4U) & 0x1FU), \ - ((RCAR_IPSR(node_id) & 0xFU)) \ - } - -#define RCAR_PIN_FLAGS(node_id) \ - DT_PROP(node_id, bias_pull_up) * RCAR_PIN_PULL_UP | \ - DT_PROP(node_id, bias_pull_down) * RCAR_PIN_PULL_DOWN | \ - DT_PROP(node_id, bias_disable) * RCAR_PIN_PULL_DISABLE | \ - RCAR_HAS_IPSR(node_id) * RCAR_PIN_FLAGS_FUNC_SET - -#define RCAR_DT_PIN(node_id) \ - { \ - .pin = DT_PROP_BY_IDX(node_id, pin, 0), \ - .func = COND_CODE_1(RCAR_HAS_IPSR(node_id), \ - (RCAR_PIN_FUNC(node_id)), (0)), \ - .flags = RCAR_PIN_FLAGS(node_id), \ - .drive_strength = \ - COND_CODE_1(DT_NODE_HAS_PROP(node_id, drive_strength), \ - (DT_PROP(node_id, drive_strength)), (0)), \ - .voltage = COND_CODE_1(DT_NODE_HAS_PROP(node_id, \ - power_source), \ - (DT_PROP(node_id, power_source)), \ - (PIN_VOLTAGE_NONE)), \ - }, - -/** - * @brief Utility macro to initialize each pin. - * - * @param node_id Node identifier. - * @param state_prop State property name. - * @param idx State property entry index. - */ -#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ - RCAR_DT_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx)) - -/** - * @brief Utility macro to initialize state pins contained in a given property. - * - * @param node_id Node identifier. - * @param prop Property name describing state pins. - */ -#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ - { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } - -struct pfc_drive_reg_field { - uint16_t pin; - uint8_t offset; - uint8_t size; -}; - -struct pfc_drive_reg { - uint32_t reg; - const struct pfc_drive_reg_field fields[8]; -}; - -struct pfc_bias_reg { - uint32_t puen; /** Pull-enable or pull-up control register */ - uint32_t pud; /** Pull-up/down or pull-down control register */ - const uint16_t pins[32]; -}; - -/** - * @brief Utility macro to check if a pin is GPIO capable - * - * @param pin - * @return true if pin is GPIO capable false otherwise - */ -#define RCAR_IS_GP_PIN(pin) (pin < PIN_NOGPSR_START) +#include #endif /* ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_ */ diff --git a/soc/renesas/rcar/rcar_gen3/r7/pinctrl_soc.h b/soc/renesas/rcar/rcar_gen3/r7/pinctrl_soc.h index b4f5da3bff0..2b6cce88818 100644 --- a/soc/renesas/rcar/rcar_gen3/r7/pinctrl_soc.h +++ b/soc/renesas/rcar/rcar_gen3/r7/pinctrl_soc.h @@ -7,6 +7,6 @@ #ifndef ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_ #define ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_ -#include +#include #endif /* ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_ */ diff --git a/soc/renesas/rcar/rcar_gen4/pinctrl_soc.h b/soc/renesas/rcar/rcar_gen4/pinctrl_soc.h index f55b114cddb..b9c5ae88b6e 100644 --- a/soc/renesas/rcar/rcar_gen4/pinctrl_soc.h +++ b/soc/renesas/rcar/rcar_gen4/pinctrl_soc.h @@ -7,6 +7,6 @@ #ifndef ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_ #define ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_ -#include +#include #endif /* ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_ */ From 0af5376b907245b9bad591180a37015dacdbc0d4 Mon Sep 17 00:00:00 2001 From: Mykola Kvach Date: Mon, 29 Jan 2024 18:18:35 +0200 Subject: [PATCH 0196/2402] drivers: pinctrl: move renesas pincontrol drivers to separate directory Moved r8a77951/r8a77961 pfc tables and funcs from soc to drivers/pfc dir. Move all Renesas pinctrl driver source and header files to a separate directory "renesas" and every SoC series to a separate subdirectory. Update the MAINTAINERS file to align with the changes in the pinctrl directory. Signed-off-by: Mykola Kvach --- MAINTAINERS.yml | 5 +- drivers/pinctrl/CMakeLists.txt | 7 +- drivers/pinctrl/Kconfig | 6 +- drivers/pinctrl/renesas/CMakeLists.txt | 8 + drivers/pinctrl/renesas/Kconfig | 4 + .../ra/Kconfig} | 0 .../{ => renesas/ra}/pinctrl_renesas_ra.c | 0 drivers/pinctrl/renesas/rcar/CMakeLists.txt | 11 + .../{Kconfig.rcar => renesas/rcar/Kconfig} | 0 .../pinctrl/renesas/rcar}/pfc_r8a77951.c | 2 +- drivers/pinctrl/renesas/rcar/pfc_r8a77961.c | 546 +++++++++ .../pinctrl/{ => renesas/rcar}/pfc_r8a779f0.c | 0 drivers/pinctrl/{ => renesas/rcar}/pfc_rcar.c | 0 drivers/pinctrl/{ => renesas/rcar}/pfc_rcar.h | 0 .../{Kconfig.rzt2m => renesas/rz/Kconfig} | 0 .../pinctrl/{ => renesas/rz}/pinctrl_rzt2m.c | 0 .../smartbond/Kconfig} | 0 .../smartbond}/pinctrl_smartbond.c | 0 .../pinctrl/renesas/pinctrl-r8a77961.h | 1023 +++++++++++++++-- soc/renesas/rcar/rcar_gen3/CMakeLists.txt | 5 +- soc/renesas/rcar/rcar_gen3/pfc_r8a77961.c | 153 --- 21 files changed, 1504 insertions(+), 266 deletions(-) create mode 100644 drivers/pinctrl/renesas/CMakeLists.txt create mode 100644 drivers/pinctrl/renesas/Kconfig rename drivers/pinctrl/{Kconfig.renesas_ra => renesas/ra/Kconfig} (100%) rename drivers/pinctrl/{ => renesas/ra}/pinctrl_renesas_ra.c (100%) create mode 100644 drivers/pinctrl/renesas/rcar/CMakeLists.txt rename drivers/pinctrl/{Kconfig.rcar => renesas/rcar/Kconfig} (100%) rename {soc/renesas/rcar/rcar_gen3 => drivers/pinctrl/renesas/rcar}/pfc_r8a77951.c (99%) create mode 100644 drivers/pinctrl/renesas/rcar/pfc_r8a77961.c rename drivers/pinctrl/{ => renesas/rcar}/pfc_r8a779f0.c (100%) rename drivers/pinctrl/{ => renesas/rcar}/pfc_rcar.c (100%) rename drivers/pinctrl/{ => renesas/rcar}/pfc_rcar.h (100%) rename drivers/pinctrl/{Kconfig.rzt2m => renesas/rz/Kconfig} (100%) rename drivers/pinctrl/{ => renesas/rz}/pinctrl_rzt2m.c (100%) rename drivers/pinctrl/{Kconfig.smartbond => renesas/smartbond/Kconfig} (100%) rename drivers/pinctrl/{ => renesas/smartbond}/pinctrl_smartbond.c (100%) delete mode 100644 soc/renesas/rcar/rcar_gen3/pfc_r8a77961.c diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 6e1602dc3fe..70899291f67 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3434,6 +3434,7 @@ Renesas SmartBond Platforms: files: - boards/renesas/da14*/ - drivers/*/*smartbond* + - drivers/pinctrl/renesas/smartbond/ - dts/arm/renesas/smartbond/ - dts/bindings/*/renesas,smartbond* - soc/renesas/smartbond/ @@ -3450,6 +3451,7 @@ Renesas RA Platforms: files: - boards/arduino/uno_r4_minima/ - drivers/*/*renesas_ra* + - drivers/pinctrl/renesas/ra/ - dts/arm/renesas/ra/ - dts/bindings/*/*renesas,ra* - soc/renesas/ra/ @@ -3466,6 +3468,7 @@ Renesas RZ Platforms: files: - boards/renesas/rzt2m_*/ - drivers/*/*rzt2m* + - drivers/pinctrl/renesas/rz/ - dts/arm/renesas/rz/ - dts/bindings/*/*rzt2m* - soc/renesas/rzt2m/ @@ -3483,10 +3486,10 @@ Renesas R-Car Platforms: collaborators: - xakep-amatop files: - - dts/arm/renesas/rcar/ - boards/renesas/rcar_*/ - drivers/*/*rcar* - drivers/clock_control/*cpg_mssr* + - drivers/pinctrl/renesas/rcar/ - dts/arm/renesas/rcar/ - dts/arm64/renesas/ - dts/bindings/*/*rcar* diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 88c4750a735..5a292054c08 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -11,8 +11,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_ITE_IT8XXX2 pinctrl_ite_it8xxx2.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NPCX pinctrl_npcx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMICRO pinctrl_numicro.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c) -zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c) -zephyr_library_sources_ifdef(CONFIG_PINCTRL_RCAR_PFC pfc_rcar.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM pinctrl_sam.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM0 pinctrl_sam0.c) @@ -28,7 +26,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_INFINEON_CAT1 pinctrl_ifx_cat1.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQ pinctrl_xlnx_zynq.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQMP pinctrl_xlnx_zynqmp.c) -zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND pinctrl_smartbond.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_XMC4XXX pinctrl_xmc4xxx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_S32 pinctrl_nxp_s32.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_GECKO pinctrl_gecko.c) @@ -37,6 +34,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_EMSDP pinctrl_emsdp.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC32XX pinctrl_ti_cc32xx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMAKER pinctrl_numaker.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_QUICKLOGIC_EOS_S3 pinctrl_eos_s3.c) -zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA pinctrl_renesas_ra.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCU pinctrl_imx_scu.c) -zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M pinctrl_rzt2m.c) + +add_subdirectory(renesas) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f03af874bbf..2ef117cabbe 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -40,7 +40,6 @@ source "drivers/pinctrl/Kconfig.it8xxx2" source "drivers/pinctrl/Kconfig.npcx" source "drivers/pinctrl/Kconfig.numicro" source "drivers/pinctrl/Kconfig.nrf" -source "drivers/pinctrl/Kconfig.rcar" source "drivers/pinctrl/Kconfig.rpi_pico" source "drivers/pinctrl/Kconfig.sam" source "drivers/pinctrl/Kconfig.sam0" @@ -55,7 +54,6 @@ source "drivers/pinctrl/Kconfig.esp32" source "drivers/pinctrl/Kconfig.rv32m1" source "drivers/pinctrl/Kconfig.ifx_cat1" source "drivers/pinctrl/Kconfig.xlnx" -source "drivers/pinctrl/Kconfig.smartbond" source "drivers/pinctrl/Kconfig.xmc4xxx" source "drivers/pinctrl/Kconfig.nxp_s32" source "drivers/pinctrl/Kconfig.gecko" @@ -64,8 +62,8 @@ source "drivers/pinctrl/Kconfig.emsdp" source "drivers/pinctrl/Kconfig.ti_cc32xx" source "drivers/pinctrl/Kconfig.numaker" source "drivers/pinctrl/Kconfig.eos_s3" -source "drivers/pinctrl/Kconfig.renesas_ra" -source "drivers/pinctrl/Kconfig.rzt2m" source "drivers/pinctrl/Kconfig.zynqmp" +rsource "renesas/Kconfig" + endif # PINCTRL diff --git a/drivers/pinctrl/renesas/CMakeLists.txt b/drivers/pinctrl/renesas/CMakeLists.txt new file mode 100644 index 00000000000..be6a33c9210 --- /dev/null +++ b/drivers/pinctrl/renesas/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA ra/pinctrl_renesas_ra.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c) + +add_subdirectory_ifdef(CONFIG_PINCTRL_RCAR_PFC rcar) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig new file mode 100644 index 00000000000..7c84d323bc2 --- /dev/null +++ b/drivers/pinctrl/renesas/Kconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2024 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +rsource "*/Kconfig" diff --git a/drivers/pinctrl/Kconfig.renesas_ra b/drivers/pinctrl/renesas/ra/Kconfig similarity index 100% rename from drivers/pinctrl/Kconfig.renesas_ra rename to drivers/pinctrl/renesas/ra/Kconfig diff --git a/drivers/pinctrl/pinctrl_renesas_ra.c b/drivers/pinctrl/renesas/ra/pinctrl_renesas_ra.c similarity index 100% rename from drivers/pinctrl/pinctrl_renesas_ra.c rename to drivers/pinctrl/renesas/ra/pinctrl_renesas_ra.c diff --git a/drivers/pinctrl/renesas/rcar/CMakeLists.txt b/drivers/pinctrl/renesas/rcar/CMakeLists.txt new file mode 100644 index 00000000000..6d0f8e70a72 --- /dev/null +++ b/drivers/pinctrl/renesas/rcar/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2024 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources(pfc_rcar.c) + +if (CONFIG_SOC_R8A77951_R7 OR CONFIG_SOC_R8A77951_A57) + zephyr_library_sources(pfc_r8a77951.c) +endif() + +zephyr_library_sources_ifdef(CONFIG_SOC_R8A77961 pfc_r8a77961.c) +zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c) diff --git a/drivers/pinctrl/Kconfig.rcar b/drivers/pinctrl/renesas/rcar/Kconfig similarity index 100% rename from drivers/pinctrl/Kconfig.rcar rename to drivers/pinctrl/renesas/rcar/Kconfig diff --git a/soc/renesas/rcar/rcar_gen3/pfc_r8a77951.c b/drivers/pinctrl/renesas/rcar/pfc_r8a77951.c similarity index 99% rename from soc/renesas/rcar/rcar_gen3/pfc_r8a77951.c rename to drivers/pinctrl/renesas/rcar/pfc_r8a77951.c index c5fb3ab967b..ce30d52331f 100644 --- a/soc/renesas/rcar/rcar_gen3/pfc_r8a77951.c +++ b/drivers/pinctrl/renesas/rcar/pfc_r8a77951.c @@ -5,7 +5,7 @@ * */ -#include "pinctrl_soc.h" +#include #include const struct pfc_drive_reg pfc_drive_regs[] = { diff --git a/drivers/pinctrl/renesas/rcar/pfc_r8a77961.c b/drivers/pinctrl/renesas/rcar/pfc_r8a77961.c new file mode 100644 index 00000000000..233005809c3 --- /dev/null +++ b/drivers/pinctrl/renesas/rcar/pfc_r8a77961.c @@ -0,0 +1,546 @@ +/* + * Copyright (c) 2021-2023 IoT.bzh + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include +#include + +const struct pfc_drive_reg pfc_drive_regs[] = { + /* DRVCTRL0 */ + { 0x0300, { + { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ + { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ + { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ + { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ + { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ + { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ + } }, + /* DRVCTRL1 */ + { 0x0304, { + { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ + { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ + { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ + { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ + { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ + { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ + { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ + } }, + /* DRVCTRL2 */ + { 0x0308, { + { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ + { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ + { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ + { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ + { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ + { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ + { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ + { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ + } }, + /* DRVCTRL3 */ + { 0x030c, { + { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ + { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ + { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ + { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + } }, + /* DRVCTRL4 */ + { 0x0310, { + { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ + { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ + { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ + { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ + { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ + { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ + { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ + { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ + } }, + /* DRVCTRL5 */ + { 0x0314, { + { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ + { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ + { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ + { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ + { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ + { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ + { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ + { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ + } }, + /* DRVCTRL6 */ + { 0x0318, { + { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ + { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ + { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ + { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ + { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ + { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ + { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ + { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ + } }, + /* DRVCTRL7 */ + { 0x031c, { + { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ + { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ + { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ + { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ + { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ + { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ + { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ + { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ + } }, + /* DRVCTRL8 */ + { 0x0320, { + { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ + { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ + { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ + { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ + { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ + { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ + { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ + { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ + } }, + /* DRVCTRL9 */ + { 0x0324, { + { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ + { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ + { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ + { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ + { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ + { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ + { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ + { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ + } }, + /* DRVCTRL10 */ + { 0x0328, { + { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ + { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ + { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ + { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ + { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ + { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ + { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ + { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ + } }, + /* DRVCTRL11 */ + { 0x032c, { + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ + } }, + /* DRVCTRL12 */ + { 0x0330, { + { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ + { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ + { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ + { PIN_TMS, 4, 2 }, /* TMS */ + } }, + /* DRVCTRL13 */ + { 0x0334, { + { PIN_TDO, 28, 2 }, /* TDO */ + { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + } }, + /* DRVCTRL14 */ + { 0x0338, { + { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ + { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ + { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ + { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ + { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ + { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ + { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ + { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ + } }, + /* DRVCTRL15 */ + { 0x033c, { + { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ + { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ + { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ + { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ + { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ + { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ + { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ + { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ + } }, + /* DRVCTRL16 */ + { 0x0340, { + { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ + { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ + { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ + { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ + { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ + { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ + { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ + { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ + } }, + /* DRVCTRL17 */ + { 0x0344, { + { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ + { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ + { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ + { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ + { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ + { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ + { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ + { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ + } }, + /* DRVCTRL18 */ + { 0x0348, { + { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ + { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ + { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ + { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ + { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ + { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ + { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ + { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ + } }, + /* DRVCTRL19 */ + { 0x034c, { + { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ + { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ + { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ + { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ + { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ + { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ + { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ + { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ + } }, + /* DRVCTRL20 */ + { 0x0350, { + { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ + { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ + { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ + { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ + { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ + { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ + { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ + { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ + } }, + /* DRVCTRL21 */ + { 0x0354, { + { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ + { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ + { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ + { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ + { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ + { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ + { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ + { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ + } }, + /* DRVCTRL22 */ + { 0x0358, { + { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ + { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ + { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ + { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ + { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ + { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ + { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ + { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ + } }, + /* DRVCTRL23 */ + { 0x035c, { + { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ + { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ + { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ + { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ + { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ + { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ + { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ + { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ + } }, + /* DRVCTRL24 */ + { 0x0360, { + { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ + { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ + { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ + { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ + { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ + { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */ + { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */ + } }, + { }, +}; + +#define PFC_BIAS_REG(r1, r2) \ + .puen = r1, \ + .pud = r2, \ + .pins = + +const struct pfc_bias_reg pfc_bias_regs[] = { + { PFC_BIAS_REG(0x0400, 0x0440) { /* PUEN0, PUD0 */ + [0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ + [1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ + [2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ + [3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ + [4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ + [5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ + [6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ + [7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ + [8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ + [9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ + [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ + [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ + [12] = PIN_RPC_INT_N, /* RPC_INT# */ + [13] = PIN_RPC_WP_N, /* RPC_WP# */ + [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ + [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ + [16] = PIN_AVB_RXC, /* AVB_RXC */ + [17] = PIN_AVB_RD0, /* AVB_RD0 */ + [18] = PIN_AVB_RD1, /* AVB_RD1 */ + [19] = PIN_AVB_RD2, /* AVB_RD2 */ + [20] = PIN_AVB_RD3, /* AVB_RD3 */ + [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ + [22] = PIN_AVB_TXC, /* AVB_TXC */ + [23] = PIN_AVB_TD0, /* AVB_TD0 */ + [24] = PIN_AVB_TD1, /* AVB_TD1 */ + [25] = PIN_AVB_TD2, /* AVB_TD2 */ + [26] = PIN_AVB_TD3, /* AVB_TD3 */ + [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ + [28] = PIN_AVB_MDIO, /* AVB_MDIO */ + [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ + [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ + [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ + } }, + { PFC_BIAS_REG(0x0404, 0x0444) { /* PUEN1, PUD1 */ + [0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ + [1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ + [2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ + [3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ + [4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ + [5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ + [6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ + [7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ + [8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ + [9] = RCAR_GP_PIN(2, 6), /* PWM0 */ + [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ + [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ + [12] = RCAR_GP_PIN(1, 0), /* A0 */ + [13] = RCAR_GP_PIN(1, 1), /* A1 */ + [14] = RCAR_GP_PIN(1, 2), /* A2 */ + [15] = RCAR_GP_PIN(1, 3), /* A3 */ + [16] = RCAR_GP_PIN(1, 4), /* A4 */ + [17] = RCAR_GP_PIN(1, 5), /* A5 */ + [18] = RCAR_GP_PIN(1, 6), /* A6 */ + [19] = RCAR_GP_PIN(1, 7), /* A7 */ + [20] = RCAR_GP_PIN(1, 8), /* A8 */ + [21] = RCAR_GP_PIN(1, 9), /* A9 */ + [22] = RCAR_GP_PIN(1, 10), /* A10 */ + [23] = RCAR_GP_PIN(1, 11), /* A11 */ + [24] = RCAR_GP_PIN(1, 12), /* A12 */ + [25] = RCAR_GP_PIN(1, 13), /* A13 */ + [26] = RCAR_GP_PIN(1, 14), /* A14 */ + [27] = RCAR_GP_PIN(1, 15), /* A15 */ + [28] = RCAR_GP_PIN(1, 16), /* A16 */ + [29] = RCAR_GP_PIN(1, 17), /* A17 */ + [30] = RCAR_GP_PIN(1, 18), /* A18 */ + [31] = RCAR_GP_PIN(1, 19), /* A19 */ + } }, + { PFC_BIAS_REG(0x0408, 0x0448) { /* PUEN2, PUD2 */ + [0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ + [1] = RCAR_GP_PIN(1, 20), /* CS0_N */ + [2] = RCAR_GP_PIN(1, 21), /* CS1_N */ + [3] = RCAR_GP_PIN(1, 22), /* BS_N */ + [4] = RCAR_GP_PIN(1, 23), /* RD_N */ + [5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ + [6] = RCAR_GP_PIN(1, 25), /* WE0_N */ + [7] = RCAR_GP_PIN(1, 26), /* WE1_N */ + [8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ + [9] = PIN_PRESETOUT_N, /* PRESETOUT# */ + [10] = RCAR_GP_PIN(0, 0), /* D0 */ + [11] = RCAR_GP_PIN(0, 1), /* D1 */ + [12] = RCAR_GP_PIN(0, 2), /* D2 */ + [13] = RCAR_GP_PIN(0, 3), /* D3 */ + [14] = RCAR_GP_PIN(0, 4), /* D4 */ + [15] = RCAR_GP_PIN(0, 5), /* D5 */ + [16] = RCAR_GP_PIN(0, 6), /* D6 */ + [17] = RCAR_GP_PIN(0, 7), /* D7 */ + [18] = RCAR_GP_PIN(0, 8), /* D8 */ + [19] = RCAR_GP_PIN(0, 9), /* D9 */ + [20] = RCAR_GP_PIN(0, 10), /* D10 */ + [21] = RCAR_GP_PIN(0, 11), /* D11 */ + [22] = RCAR_GP_PIN(0, 12), /* D12 */ + [23] = RCAR_GP_PIN(0, 13), /* D13 */ + [24] = RCAR_GP_PIN(0, 14), /* D14 */ + [25] = RCAR_GP_PIN(0, 15), /* D15 */ + [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ + [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ + [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ + [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ + [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ + } }, + { PFC_BIAS_REG(0x040c, 0x044c) { /* PUEN3, PUD3 */ + [0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ + [1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ + [2] = PIN_FSCLKST_N, /* FSCLKST# */ + [3] = PIN_EXTALR, /* EXTALR*/ + [4] = PIN_TRST_N, /* TRST# */ + [5] = PIN_TCK, /* TCK */ + [6] = PIN_TMS, /* TMS */ + [7] = PIN_TDI, /* TDI */ + [8] = PIN_NONE, + [9] = PIN_ASEBRK, /* ASEBRK */ + [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ + [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ + [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ + [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ + [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ + [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ + [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ + [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ + [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ + [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ + [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ + [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ + [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ + [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ + [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ + [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ + [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ + [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ + [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ + [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ + [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ + [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ + } }, + { PFC_BIAS_REG(0x0410, 0x0450) { /* PUEN4, PUD4 */ + [0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ + [1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ + [2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ + [3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ + [4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ + [5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ + [6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ + [7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ + [8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ + [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ + [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ + [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ + [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ + [13] = RCAR_GP_PIN(5, 1), /* RX0 */ + [14] = RCAR_GP_PIN(5, 2), /* TX0 */ + [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ + [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ + [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ + [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ + [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ + [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ + [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ + [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ + [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ + [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ + [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ + [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ + [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ + [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ + [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ + [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ + [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ + } }, + { PFC_BIAS_REG(0x0414, 0x0454) { /* PUEN5, PUD5 */ + [0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ + [1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ + [2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ + [3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ + [4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ + [5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ + [6] = PIN_MLB_REF, /* MLB_REF */ + [7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ + [8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ + [9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ + [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ + [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ + [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ + [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ + [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ + [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ + [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ + [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ + [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ + [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ + [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ + [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ + [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ + [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ + [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ + [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ + [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ + [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ + [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ + [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ + [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ + [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ + } }, + { PFC_BIAS_REG(0x0418, 0x0458) { /* PUEN6, PUD6 */ + [0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ + [1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ + [2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ + [3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ + [4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ + [5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ + [6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */ + [7] = PIN_NONE, + [8] = PIN_NONE, + [9] = PIN_NONE, + [10] = PIN_NONE, + [11] = PIN_NONE, + [12] = PIN_NONE, + [13] = PIN_NONE, + [14] = PIN_NONE, + [15] = PIN_NONE, + [16] = PIN_NONE, + [17] = PIN_NONE, + [18] = PIN_NONE, + [19] = PIN_NONE, + [20] = PIN_NONE, + [21] = PIN_NONE, + [22] = PIN_NONE, + [23] = PIN_NONE, + [24] = PIN_NONE, + [25] = PIN_NONE, + [26] = PIN_NONE, + [27] = PIN_NONE, + [28] = PIN_NONE, + [29] = PIN_NONE, + [30] = PIN_NONE, + [31] = PIN_NONE, + } }, + { /* sentinel */ }, +}; + +const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void) +{ + return pfc_bias_regs; +} +const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void) +{ + return pfc_drive_regs; +} + +int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index) +{ + /* There is only one register on Gen 3 */ + *reg_index = 0; + return 0; +} diff --git a/drivers/pinctrl/pfc_r8a779f0.c b/drivers/pinctrl/renesas/rcar/pfc_r8a779f0.c similarity index 100% rename from drivers/pinctrl/pfc_r8a779f0.c rename to drivers/pinctrl/renesas/rcar/pfc_r8a779f0.c diff --git a/drivers/pinctrl/pfc_rcar.c b/drivers/pinctrl/renesas/rcar/pfc_rcar.c similarity index 100% rename from drivers/pinctrl/pfc_rcar.c rename to drivers/pinctrl/renesas/rcar/pfc_rcar.c diff --git a/drivers/pinctrl/pfc_rcar.h b/drivers/pinctrl/renesas/rcar/pfc_rcar.h similarity index 100% rename from drivers/pinctrl/pfc_rcar.h rename to drivers/pinctrl/renesas/rcar/pfc_rcar.h diff --git a/drivers/pinctrl/Kconfig.rzt2m b/drivers/pinctrl/renesas/rz/Kconfig similarity index 100% rename from drivers/pinctrl/Kconfig.rzt2m rename to drivers/pinctrl/renesas/rz/Kconfig diff --git a/drivers/pinctrl/pinctrl_rzt2m.c b/drivers/pinctrl/renesas/rz/pinctrl_rzt2m.c similarity index 100% rename from drivers/pinctrl/pinctrl_rzt2m.c rename to drivers/pinctrl/renesas/rz/pinctrl_rzt2m.c diff --git a/drivers/pinctrl/Kconfig.smartbond b/drivers/pinctrl/renesas/smartbond/Kconfig similarity index 100% rename from drivers/pinctrl/Kconfig.smartbond rename to drivers/pinctrl/renesas/smartbond/Kconfig diff --git a/drivers/pinctrl/pinctrl_smartbond.c b/drivers/pinctrl/renesas/smartbond/pinctrl_smartbond.c similarity index 100% rename from drivers/pinctrl/pinctrl_smartbond.c rename to drivers/pinctrl/renesas/smartbond/pinctrl_smartbond.c diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h index 3703d2f3c59..aa053c5c5f0 100644 --- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2023 EPAM Systems + * Copyright (c) 2021 IoT.bzh + * Copyright (c) 2023-2024 EPAM Systems * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,104 +10,930 @@ #include "pinctrl-rcar-common.h" /* Pins declaration */ -#define PIN_NONE -1 - -#define PIN_SD0_CLK RCAR_GP_PIN(3, 0) -#define PIN_SD0_CMD RCAR_GP_PIN(3, 1) -#define PIN_SD0_DATA0 RCAR_GP_PIN(3, 2) -#define PIN_SD0_DATA1 RCAR_GP_PIN(3, 3) -#define PIN_SD0_DATA2 RCAR_GP_PIN(3, 4) -#define PIN_SD0_DATA3 RCAR_GP_PIN(3, 5) -#define PIN_SD0_CD RCAR_GP_PIN(3, 12) -#define PIN_SD0_WP RCAR_GP_PIN(3, 13) - -#define PIN_SD1_CLK RCAR_GP_PIN(3, 6) -#define PIN_SD1_CMD RCAR_GP_PIN(3, 7) -/* - * note: the next data pins shared with SD2, - * and for SD2 they represent DATA4-DATA7 - */ -#define PIN_SD1_DATA0 RCAR_GP_PIN(3, 8) -#define PIN_SD1_DATA1 RCAR_GP_PIN(3, 9) -#define PIN_SD1_DATA2 RCAR_GP_PIN(3, 10) -#define PIN_SD1_DATA3 RCAR_GP_PIN(3, 11) - -#define PIN_SD1_CD RCAR_GP_PIN(3, 14) -#define PIN_SD1_WP RCAR_GP_PIN(3, 15) - -#define PIN_SD2_CLK RCAR_GP_PIN(4, 0) -#define PIN_SD2_CMD RCAR_GP_PIN(4, 1) -#define PIN_SD2_DATA0 RCAR_GP_PIN(4, 2) -#define PIN_SD2_DATA1 RCAR_GP_PIN(4, 3) -#define PIN_SD2_DATA2 RCAR_GP_PIN(4, 4) -#define PIN_SD2_DATA3 RCAR_GP_PIN(4, 5) -#define PIN_SD2_DS RCAR_GP_PIN(4, 6) - -#define PIN_SD3_CLK RCAR_GP_PIN(4, 7) -#define PIN_SD3_CMD RCAR_GP_PIN(4, 8) -#define PIN_SD3_DATA0 RCAR_GP_PIN(4, 9) -#define PIN_SD3_DATA1 RCAR_GP_PIN(4, 10) -#define PIN_SD3_DATA2 RCAR_GP_PIN(4, 11) -#define PIN_SD3_DATA3 RCAR_GP_PIN(4, 12) -#define PIN_SD3_DATA4 RCAR_GP_PIN(4, 13) -#define PIN_SD3_DATA5 RCAR_GP_PIN(4, 14) -#define PIN_SD3_DATA6 RCAR_GP_PIN(4, 15) -#define PIN_SD3_DATA7 RCAR_GP_PIN(4, 16) -#define PIN_SD3_DS RCAR_GP_PIN(4, 17) - -#define PIN_TX2_A RCAR_GP_PIN(5, 10) -#define PIN_RX2_A RCAR_GP_PIN(5, 11) +#define PIN_NONE -1 +#define PIN_D0 RCAR_GP_PIN(0, 0) +#define PIN_D1 RCAR_GP_PIN(0, 1) +#define PIN_D2 RCAR_GP_PIN(0, 2) +#define PIN_D3 RCAR_GP_PIN(0, 3) +#define PIN_D4 RCAR_GP_PIN(0, 4) +#define PIN_D5 RCAR_GP_PIN(0, 5) +#define PIN_D6 RCAR_GP_PIN(0, 6) +#define PIN_D7 RCAR_GP_PIN(0, 7) +#define PIN_D8 RCAR_GP_PIN(0, 8) +#define PIN_D9 RCAR_GP_PIN(0, 9) +#define PIN_D10 RCAR_GP_PIN(0, 10) +#define PIN_D11 RCAR_GP_PIN(0, 11) +#define PIN_D12 RCAR_GP_PIN(0, 12) +#define PIN_D13 RCAR_GP_PIN(0, 13) +#define PIN_D14 RCAR_GP_PIN(0, 14) +#define PIN_D15 RCAR_GP_PIN(0, 15) +#define PIN_A0 RCAR_GP_PIN(1, 0) +#define PIN_A1 RCAR_GP_PIN(1, 1) +#define PIN_A2 RCAR_GP_PIN(1, 2) +#define PIN_A3 RCAR_GP_PIN(1, 3) +#define PIN_A4 RCAR_GP_PIN(1, 4) +#define PIN_A5 RCAR_GP_PIN(1, 5) +#define PIN_A6 RCAR_GP_PIN(1, 6) +#define PIN_A7 RCAR_GP_PIN(1, 7) +#define PIN_A8 RCAR_GP_PIN(1, 8) +#define PIN_A9 RCAR_GP_PIN(1, 9) +#define PIN_A10 RCAR_GP_PIN(1, 10) +#define PIN_A11 RCAR_GP_PIN(1, 11) +#define PIN_A12 RCAR_GP_PIN(1, 12) +#define PIN_A13 RCAR_GP_PIN(1, 13) +#define PIN_A14 RCAR_GP_PIN(1, 14) +#define PIN_A15 RCAR_GP_PIN(1, 15) +#define PIN_A16 RCAR_GP_PIN(1, 16) +#define PIN_A17 RCAR_GP_PIN(1, 17) +#define PIN_A18 RCAR_GP_PIN(1, 18) +#define PIN_A19 RCAR_GP_PIN(1, 19) +#define PIN_CS0 RCAR_GP_PIN(1, 20) +#define PIN_CS1 RCAR_GP_PIN(1, 21) +#define PIN_BS RCAR_GP_PIN(1, 22) +#define PIN_RD RCAR_GP_PIN(1, 23) +#define PIN_RD_WR RCAR_GP_PIN(1, 24) +#define PIN_WE0 RCAR_GP_PIN(1, 25) +#define PIN_WE1 RCAR_GP_PIN(1, 26) +#define PIN_EX_WAIT0 RCAR_GP_PIN(1, 27) +#define PIN_CLKOUT RCAR_GP_PIN(1, 28) +#define PIN_IRQ0 RCAR_GP_PIN(2, 0) +#define PIN_IRQ1 RCAR_GP_PIN(2, 1) +#define PIN_IRQ2 RCAR_GP_PIN(2, 2) +#define PIN_IRQ3 RCAR_GP_PIN(2, 3) +#define PIN_IRQ4 RCAR_GP_PIN(2, 4) +#define PIN_IRQ5 RCAR_GP_PIN(2, 5) +#define PIN_PWM0 RCAR_GP_PIN(2, 6) +#define PIN_PWM1_A RCAR_GP_PIN(2, 7) +#define PIN_PWM2_A RCAR_GP_PIN(2, 8) +#define PIN_AVB_MDC RCAR_GP_PIN(2, 9) +#define PIN_AVB_MAGIC RCAR_GP_PIN(2, 10) +#define PIN_AVB_PHY_INT RCAR_GP_PIN(2, 11) +#define PIN_AVB_LINK RCAR_GP_PIN(2, 12) +#define PIN_AVB_AVTP_MATCH_A RCAR_GP_PIN(2, 13) +#define PIN_AVB_AVTP_CAPTURE_A RCAR_GP_PIN(2, 14) +#define PIN_SD0_CLK RCAR_GP_PIN(3, 0) +#define PIN_SD0_CMD RCAR_GP_PIN(3, 1) +#define PIN_SD0_DATA0 RCAR_GP_PIN(3, 2) +#define PIN_SD0_DATA1 RCAR_GP_PIN(3, 3) +#define PIN_SD0_DATA2 RCAR_GP_PIN(3, 4) +#define PIN_SD0_DATA3 RCAR_GP_PIN(3, 5) +#define PIN_SD1_CLK RCAR_GP_PIN(3, 6) +#define PIN_SD1_CMD RCAR_GP_PIN(3, 7) +#define PIN_SD1_DATA0 RCAR_GP_PIN(3, 8) +#define PIN_SD1_DATA1 RCAR_GP_PIN(3, 9) +#define PIN_SD1_DATA2 RCAR_GP_PIN(3, 10) +#define PIN_SD1_DATA3 RCAR_GP_PIN(3, 11) +#define PIN_SD0_CD RCAR_GP_PIN(3, 12) +#define PIN_SD0_WP RCAR_GP_PIN(3, 13) +#define PIN_SD1_CD RCAR_GP_PIN(3, 14) +#define PIN_SD1_WP RCAR_GP_PIN(3, 15) +#define PIN_SD2_CLK RCAR_GP_PIN(4, 0) +#define PIN_SD2_CMD RCAR_GP_PIN(4, 1) +#define PIN_SD2_DATA0 RCAR_GP_PIN(4, 2) +#define PIN_SD2_DATA1 RCAR_GP_PIN(4, 3) +#define PIN_SD2_DATA2 RCAR_GP_PIN(4, 4) +#define PIN_SD2_DATA3 RCAR_GP_PIN(4, 5) +#define PIN_SD2_DS RCAR_GP_PIN(4, 6) +#define PIN_SD3_CLK RCAR_GP_PIN(4, 7) +#define PIN_SD3_CMD RCAR_GP_PIN(4, 8) +#define PIN_SD3_DATA0 RCAR_GP_PIN(4, 9) +#define PIN_SD3_DATA1 RCAR_GP_PIN(4, 10) +#define PIN_SD3_DATA2 RCAR_GP_PIN(4, 11) +#define PIN_SD3_DATA3 RCAR_GP_PIN(4, 12) +#define PIN_SD3_DATA4 RCAR_GP_PIN(4, 13) +#define PIN_SD3_DATA5 RCAR_GP_PIN(4, 14) +#define PIN_SD3_DATA6 RCAR_GP_PIN(4, 15) +#define PIN_SD3_DATA7 RCAR_GP_PIN(4, 16) +#define PIN_SD3_DS RCAR_GP_PIN(4, 17) +#define PIN_SCK0 RCAR_GP_PIN(5, 0) +#define PIN_RX0 RCAR_GP_PIN(5, 1) +#define PIN_TX0 RCAR_GP_PIN(5, 2) +#define PIN_CTS0 RCAR_GP_PIN(5, 3) +#define PIN_RTS0 RCAR_GP_PIN(5, 4) +#define PIN_RX1_A RCAR_GP_PIN(5, 5) +#define PIN_TX1_A RCAR_GP_PIN(5, 6) +#define PIN_CTS1 RCAR_GP_PIN(5, 7) +#define PIN_RTS1 RCAR_GP_PIN(5, 8) +#define PIN_SCK2 RCAR_GP_PIN(5, 9) +#define PIN_TX2_A RCAR_GP_PIN(5, 10) +#define PIN_RX2_A RCAR_GP_PIN(5, 11) +#define PIN_HSCK0 RCAR_GP_PIN(5, 12) +#define PIN_HRX0 RCAR_GP_PIN(5, 13) +#define PIN_HTX0 RCAR_GP_PIN(5, 14) +#define PIN_HCTS0 RCAR_GP_PIN(5, 15) +#define PIN_HRTS0 RCAR_GP_PIN(5, 16) +#define PIN_MSIOF0_SCK RCAR_GP_PIN(5, 17) +#define PIN_MSIOF0_SYNC RCAR_GP_PIN(5, 18) +#define PIN_MSIOF0_SS1 RCAR_GP_PIN(5, 19) +#define PIN_MSIOF0_TXD RCAR_GP_PIN(5, 20) +#define PIN_MSIOF0_SS2 RCAR_GP_PIN(5, 21) +#define PIN_MSIOF0_RXD RCAR_GP_PIN(5, 22) +#define PIN_MLB_CLK RCAR_GP_PIN(5, 23) +#define PIN_MLB_SIG RCAR_GP_PIN(5, 24) +#define PIN_MLB_DAT RCAR_GP_PIN(5, 25) +#define PIN_SSI_SCK01239 RCAR_GP_PIN(6, 0) +#define PIN_SSI_WS01239 RCAR_GP_PIN(6, 1) +#define PIN_SSI_SDATA0 RCAR_GP_PIN(6, 2) +#define PIN_SSI_SDATA1_A RCAR_GP_PIN(6, 3) +#define PIN_SSI_SDATA2_A RCAR_GP_PIN(6, 4) +#define PIN_SSI_SCK349 RCAR_GP_PIN(6, 5) +#define PIN_SSI_WS349 RCAR_GP_PIN(6, 6) +#define PIN_SSI_SDATA3 RCAR_GP_PIN(6, 7) +#define PIN_SSI_SCK4 RCAR_GP_PIN(6, 8) +#define PIN_SSI_WS4 RCAR_GP_PIN(6, 9) +#define PIN_SSI_SDAT_A4 RCAR_GP_PIN(6, 10) +#define PIN_SSI_SCK5 RCAR_GP_PIN(6, 11) +#define PIN_SSI_WS5 RCAR_GP_PIN(6, 12) +#define PIN_SSI_SDAT_A5 RCAR_GP_PIN(6, 13) +#define PIN_SSI_SCK6 RCAR_GP_PIN(6, 14) +#define PIN_SSI_WS6 RCAR_GP_PIN(6, 15) +#define PIN_SSI_SDATA6 RCAR_GP_PIN(6, 16) +#define PIN_SSI_SCK78 RCAR_GP_PIN(6, 17) +#define PIN_WS78 RCAR_GP_PIN(6, 18) +#define PIN_SSI_SDATA7 RCAR_GP_PIN(6, 19) +#define PIN_SSI_SDATA8 RCAR_GP_PIN(6, 20) +#define PIN_SSI_SDATA9_A RCAR_GP_PIN(6, 21) +#define PIN_AUDIO_CLKA_A RCAR_GP_PIN(6, 22) +#define PIN_AUDIO_CLKB_B RCAR_GP_PIN(6, 23) +#define PIN_USB0_PWEN RCAR_GP_PIN(6, 24) +#define PIN_USB0_OVC RCAR_GP_PIN(6, 25) +#define PIN_USB1_PWEN RCAR_GP_PIN(6, 26) +#define PIN_USB1_OVC RCAR_GP_PIN(6, 27) +#define PIN_USB30_PWEN RCAR_GP_PIN(6, 28) +#define PIN_USB30_OVC RCAR_GP_PIN(6, 29) +#define PIN_USB2_CH3_PWEN RCAR_GP_PIN(6, 30) +#define PIN_USB2_CH3_OVC RCAR_GP_PIN(6, 31) +#define PIN_AVS1 RCAR_GP_PIN(7, 0) +#define PIN_AVS2 RCAR_GP_PIN(7, 1) +#define PIN_GP7_02 RCAR_GP_PIN(7, 2) +#define PIN_GP7_03 RCAR_GP_PIN(7, 3) +#define PIN_ASEBRK RCAR_NOGP_PIN(1) +#define PIN_AVB_MDIO RCAR_NOGP_PIN(2) +#define PIN_AVB_RD0 RCAR_NOGP_PIN(3) +#define PIN_AVB_RD1 RCAR_NOGP_PIN(4) +#define PIN_AVB_RD2 RCAR_NOGP_PIN(5) +#define PIN_AVB_RD3 RCAR_NOGP_PIN(6) +#define PIN_AVB_RXC RCAR_NOGP_PIN(7) +#define PIN_AVB_RX_CTL RCAR_NOGP_PIN(8) +#define PIN_AVB_TD0 RCAR_NOGP_PIN(9) +#define PIN_AVB_TD1 RCAR_NOGP_PIN(10) +#define PIN_AVB_TD2 RCAR_NOGP_PIN(11) +#define PIN_AVB_TD3 RCAR_NOGP_PIN(12) +#define PIN_AVB_TXC RCAR_NOGP_PIN(13) +#define PIN_AVB_TXCREFCLK RCAR_NOGP_PIN(14) +#define PIN_AVB_TX_CTL RCAR_NOGP_PIN(15) +#define PIN_DU_DOTCLKIN0 RCAR_NOGP_PIN(16) +#define PIN_DU_DOTCLKIN1 RCAR_NOGP_PIN(17) +#define PIN_DU_DOTCLKIN2 RCAR_NOGP_PIN(18) +#define PIN_DU_DOTCLKIN3 RCAR_NOGP_PIN(19) +#define PIN_EXTALR RCAR_NOGP_PIN(20) +#define PIN_FSCLKST_N RCAR_NOGP_PIN(21) +#define PIN_MLB_REF RCAR_NOGP_PIN(22) +#define PIN_PRESETOUT_N RCAR_NOGP_PIN(23) +#define PIN_QSPI0_IO2 RCAR_NOGP_PIN(24) +#define PIN_QSPI0_IO3 RCAR_NOGP_PIN(25) +#define PIN_QSPI0_MISO_IO1 RCAR_NOGP_PIN(26) +#define PIN_QSPI0_MOSI_IO0 RCAR_NOGP_PIN(27) +#define PIN_QSPI0_SPCLK RCAR_NOGP_PIN(28) +#define PIN_QSPI0_SSL RCAR_NOGP_PIN(29) +#define PIN_QSPI1_IO2 RCAR_NOGP_PIN(30) +#define PIN_QSPI1_IO3 RCAR_NOGP_PIN(31) +#define PIN_QSPI1_MISO_IO1 RCAR_NOGP_PIN(32) +#define PIN_QSPI1_MOSI_IO0 RCAR_NOGP_PIN(33) +#define PIN_QSPI1_SPCLK RCAR_NOGP_PIN(34) +#define PIN_QSPI1_SSL RCAR_NOGP_PIN(35) +#define PIN_RPC_INT_N RCAR_NOGP_PIN(36) +#define PIN_RPC_RESET_N RCAR_NOGP_PIN(37) +#define PIN_RPC_WP_N RCAR_NOGP_PIN(38) +#define PIN_TCK RCAR_NOGP_PIN(39) +#define PIN_TDI RCAR_NOGP_PIN(40) +#define PIN_TDO RCAR_NOGP_PIN(41) +#define PIN_TMS RCAR_NOGP_PIN(42) +#define PIN_TRST_N RCAR_NOGP_PIN(43) /* Pinmux function declarations */ -#define FUNC_SD0_CLK IPSR(7, 12, 0) -#define FUNC_SD0_CMD IPSR(7, 16, 0) -#define FUNC_SD0_DAT0 IPSR(7, 20, 0) -#define FUNC_SD0_DAT1 IPSR(7, 24, 0) -#define FUNC_SD0_DAT2 IPSR(8, 0, 0) -#define FUNC_SD0_DAT3 IPSR(8, 4, 0) -#define FUNC_SD0_CD IPSR(11, 8, 0) -#define FUNC_SD0_WP IPSR(11, 12, 0) - -#define FUNC_SD1_CLK IPSR(8, 8, 0) -#define FUNC_SD1_CMD IPSR(8, 12, 0) -#define FUNC_SD1_DAT0 IPSR(8, 16, 0) -#define FUNC_SD1_DAT1 IPSR(8, 20, 0) -#define FUNC_SD1_DAT2 IPSR(8, 24, 0) -#define FUNC_SD1_DAT3 IPSR(8, 28, 0) -#define FUNC_SD1_CD IPSR(11, 16, 0) -#define FUNC_SD1_WP IPSR(11, 20, 0) - -#define FUNC_SD2_CLK IPSR(9, 0, 0) -#define FUNC_SD2_CMD IPSR(9, 4, 0) -#define FUNC_SD2_DAT0 IPSR(9, 8, 0) -#define FUNC_SD2_DAT1 IPSR(9, 12, 0) -#define FUNC_SD2_DAT2 IPSR(9, 16, 0) -#define FUNC_SD2_DAT3 IPSR(9, 20, 0) -#define FUNC_SD2_DAT4 IPSR(8, 16, 1) -#define FUNC_SD2_DAT5 IPSR(8, 20, 1) -#define FUNC_SD2_DAT6 IPSR(8, 24, 1) -#define FUNC_SD2_DAT7 IPSR(8, 28, 1) -#define FUNC_SD2_CD_A IPSR(10, 20, 1) -#define FUNC_SD2_WP_A IPSR(10, 24, 1) -#define FUNC_SD2_CD_B IPSR(13, 0, 3) -#define FUNC_SD2_WP_B IPSR(13, 4, 3) -#define FUNC_SD2_DS IPSR(9, 24, 0) - -#define FUNC_SD3_CLK IPSR(9, 28, 0) -#define FUNC_SD3_CMD IPSR(10, 0, 0) -#define FUNC_SD3_DAT0 IPSR(10, 4, 0) -#define FUNC_SD3_DAT1 IPSR(10, 8, 0) -#define FUNC_SD3_DAT2 IPSR(10, 12, 0) -#define FUNC_SD3_DAT3 IPSR(10, 16, 0) -#define FUNC_SD3_DAT4 IPSR(10, 20, 0) -#define FUNC_SD3_DAT5 IPSR(10, 24, 0) -#define FUNC_SD3_DAT6 IPSR(10, 28, 0) -#define FUNC_SD3_DAT7 IPSR(11, 0, 0) -#define FUNC_SD3_CD IPSR(10, 28, 1) -#define FUNC_SD3_WP IPSR(11, 0, 1) -#define FUNC_SD3_DS IPSR(11, 4, 0) - -#define FUNC_TX2_A IPSR(13, 0, 0) -#define FUNC_RX2_A IPSR(13, 4, 0) +#define FUNC_AVB_MDC IPSR(0, 0, 0) +#define FUNC_MSIOD2_SS2_C IPSR(0, 0, 2) +#define FUNC_AVB_MAGIC IPSR(0, 4, 0) +#define FUNC_MSIOF2_SS1_C IPSR(0, 4, 2) +#define FUNC_SCK4_A IPSR(0, 4, 3) +#define FUNC_AVB_PHY_INT IPSR(0, 8, 0) +#define FUNC_MSIOF2_SYNC_C IPSR(0, 8, 2) +#define FUNC_RX4_A IPSR(0, 8, 3) +#define FUNC_AVB_LINK IPSR(0, 12, 0) +#define FUNC_MSIOF2_SCK_C IPSR(0, 12, 2) +#define FUNC_TX4_A IPSR(0, 12, 3) +#define FUNC_AVB_AVTP_MATCH_A IPSR(0, 16, 0) +#define FUNC_MSIOF2_RXD_C IPSR(0, 16, 2) +#define FUNC_CTS4_N_A IPSR(0, 16, 3) +#define FUNC_AVB_AVTP_CAPTURE_A IPSR(0, 20, 0) +#define FUNC_MSIOF2_TXD_C IPSR(0, 20, 2) +#define FUNC_RTS4_N_A IPSR(0, 20, 3) +#define FUNC_IRQ0 IPSR(0, 24, 0) +#define FUNC_QPOLB IPSR(0, 24, 1) +#define FUNC_DU_CDE IPSR(0, 24, 3) +#define FUNC_VI4_DATA0_B IPSR(0, 24, 4) +#define FUNC_CAN0_TX_B IPSR(0, 24, 5) +#define FUNC_CANFD0_TX_B IPSR(0, 24, 6) +#define FUNC_MSIOF3_SS2_E IPSR(0, 24, 7) +#define FUNC_IRQ1 IPSR(0, 28, 0) +#define FUNC_QPOLA IPSR(0, 28, 1) +#define FUNC_DU_DISP IPSR(0, 28, 3) +#define FUNC_VI4_DATA1_B IPSR(0, 28, 4) +#define FUNC_CAN0_RX_B IPSR(0, 28, 5) +#define FUNC_CANFD0_RX_B IPSR(0, 28, 6) +#define FUNC_MSIOF3_SS1_E IPSR(0, 28, 7) +#define FUNC_IRQ2 IPSR(1, 0, 0) +#define FUNC_QCPV_QDE IPSR(1, 0, 1) +#define FUNC_DU_EXODDF_DU_ODDF_DISP_CDE IPSR(1, 0, 3) +#define FUNC_VI4_DATA2_B IPSR(1, 0, 4) +#define FUNC_MSIOF3_SYNC_E IPSR(1, 0, 7) +#define FUNC_PWM3_B IPSR(1, 0, 9) +#define FUNC_IRQ3 IPSR(1, 4, 0) +#define FUNC_QSTVB_QVE IPSR(1, 4, 1) +#define FUNC_DU_DOTCLKOUT1 IPSR(1, 4, 3) +#define FUNC_VI4_DATA3_B IPSR(1, 4, 4) +#define FUNC_MSIOF3_SCK_E IPSR(1, 4, 7) +#define FUNC_PWM4_B IPSR(1, 4, 9) +#define FUNC_IRQ4 IPSR(1, 8, 0) +#define FUNC_QSTH_QHS IPSR(1, 8, 1) +#define FUNC_DU_EXHSYNC_DU_HSYNC IPSR(1, 8, 3) +#define FUNC_VI4_DATA4_B IPSR(1, 8, 4) +#define FUNC_MSIOF3_RXD_E IPSR(1, 8, 7) +#define FUNC_PWM5_B IPSR(1, 8, 9) +#define FUNC_IRQ5 IPSR(1, 12, 0) +#define FUNC_QSTB_QHE IPSR(1, 12, 1) +#define FUNC_DU_EXVSYNC_DU_VSYNC IPSR(1, 12, 3) +#define FUNC_VI4_DATA5_B IPSR(1, 12, 4) +#define FUNC_MSIOF3_TXD_E IPSR(1, 12, 7) +#define FUNC_PWM6_B IPSR(1, 12, 9) +#define FUNC_PWM0 IPSR(1, 16, 0) +#define FUNC_AVB_AVTP_PPS IPSR(1, 16, 1) +#define FUNC_VI4_DATA6_B IPSR(1, 16, 4) +#define FUNC_IECLK_B IPSR(1, 16, 9) +#define FUNC_PWM1_A IPSR(1, 20, 0) +#define FUNC_HRX3_D IPSR(1, 20, 3) +#define FUNC_VI4_DATA7_B IPSR(1, 20, 4) +#define FUNC_IERX_B IPSR(1, 20, 9) +#define FUNC_PWM2_A IPSR(1, 24, 0) +#define FUNC_HTX3_D IPSR(1, 24, 3) +#define FUNC_IETX_B IPSR(1, 24, 9) +#define FUNC_A0 IPSR(1, 28, 0) +#define FUNC_LCDOUT16 IPSR(1, 28, 1) +#define FUNC_MSIOF3_SYNC_B IPSR(1, 28, 2) +#define FUNC_VI4_DATA8 IPSR(1, 28, 4) +#define FUNC_DU_DB0 IPSR(1, 28, 6) +#define FUNC_PWM3_A IPSR(1, 28, 9) +#define FUNC_A1 IPSR(2, 0, 0) +#define FUNC_LCDOUT17 IPSR(2, 0, 1) +#define FUNC_MSIOF3_TXD_B IPSR(2, 0, 2) +#define FUNC_VI4_DATA9 IPSR(2, 0, 4) +#define FUNC_DU_DB1 IPSR(2, 0, 6) +#define FUNC_PWM4_A IPSR(2, 0, 9) +#define FUNC_A2 IPSR(2, 4, 0) +#define FUNC_LCDOUT18 IPSR(2, 4, 1) +#define FUNC_MSIOF3_SCK_B IPSR(2, 4, 2) +#define FUNC_VI4_DATA10 IPSR(2, 4, 4) +#define FUNC_DU_DB2 IPSR(2, 4, 6) +#define FUNC_PWM5_A IPSR(2, 4, 9) +#define FUNC_A3 IPSR(2, 8, 0) +#define FUNC_LCDOUT19 IPSR(2, 8, 1) +#define FUNC_MSIOF3_RXD_B IPSR(2, 8, 2) +#define FUNC_VI4_DATA11 IPSR(2, 8, 4) +#define FUNC_DU_DB3 IPSR(2, 8, 6) +#define FUNC_PWM6_A IPSR(2, 8, 9) +#define FUNC_A4 IPSR(2, 12, 0) +#define FUNC_LCDOUT20 IPSR(2, 12, 1) +#define FUNC_MSIOF3_SS1_B IPSR(2, 12, 2) +#define FUNC_VI4_DATA12 IPSR(2, 12, 4) +#define FUNC_VI5_DATA12 IPSR(2, 12, 5) +#define FUNC_DU_DB4 IPSR(2, 12, 6) +#define FUNC_A5 IPSR(2, 16, 0) +#define FUNC_LCDOUT21 IPSR(2, 16, 1) +#define FUNC_MSIOF3_SS2_B IPSR(2, 16, 2) +#define FUNC_SCK4_B IPSR(2, 16, 3) +#define FUNC_VI4_DATA13 IPSR(2, 16, 4) +#define FUNC_VI5_DATA13 IPSR(2, 16, 5) +#define FUNC_DU_DB5 IPSR(2, 16, 6) +#define FUNC_A6 IPSR(2, 20, 0) +#define FUNC_LCDOUT22 IPSR(2, 20, 1) +#define FUNC_MSIOF2_SS1_A IPSR(2, 20, 2) +#define FUNC_RX4_B IPSR(2, 20, 3) +#define FUNC_VI4_DATA14 IPSR(2, 20, 4) +#define FUNC_VI5_DATA14 IPSR(2, 20, 5) +#define FUNC_DU_DB6 IPSR(2, 20, 6) +#define FUNC_A7 IPSR(2, 24, 0) +#define FUNC_LCDOUT23 IPSR(2, 24, 1) +#define FUNC_MSIOF2_SS2_A IPSR(2, 24, 2) +#define FUNC_TX4_B IPSR(2, 24, 3) +#define FUNC_VI4_DATA15 IPSR(2, 24, 4) +#define FUNC_VI5_DATA15 IPSR(2, 24, 5) +#define FUNC_DU_DB7 IPSR(2, 24, 6) +#define FUNC_A8 IPSR(2, 28, 0) +#define FUNC_RX3_B IPSR(2, 28, 1) +#define FUNC_MSIOF2_SYNC_A IPSR(2, 28, 2) +#define FUNC_HRX4_B IPSR(2, 28, 3) +#define FUNC_SDA6_A IPSR(2, 28, 7) +#define FUNC_AVB_AVTP_MATCH_B IPSR(2, 28, 8) +#define FUNC_PWM1_B IPSR(2, 28, 9) +#define FUNC_A9 IPSR(3, 0, 0) +#define FUNC_MSIOF2_SCK_A IPSR(3, 0, 2) +#define FUNC_CTS4_N_B IPSR(3, 0, 3) +#define FUNC_VI5_VSYNC_N IPSR(3, 0, 5) +#define FUNC_A10 IPSR(3, 4, 0) +#define FUNC_MSIOF2_RXD_A IPSR(3, 4, 2) +#define FUNC_RTS4_N_B IPSR(3, 4, 3) +#define FUNC_VI5_HSYNC_N IPSR(3, 4, 5) +#define FUNC_A11 IPSR(3, 8, 0) +#define FUNC_TX3_B IPSR(3, 8, 1) +#define FUNC_MSIOF2_TXD_A IPSR(3, 8, 2) +#define FUNC_HTX4_B IPSR(3, 8, 3) +#define FUNC_HSCK4 IPSR(3, 8, 4) +#define FUNC_VI5_FIELD IPSR(3, 8, 5) +#define FUNC_SCL6_A IPSR(3, 8, 7) +#define FUNC_AVB_AVTP_CAPTURE_B IPSR(3, 8, 8) +#define FUNC_PWM2_B IPSR(3, 8, 9) +#define FUNC_A12 IPSR(3, 12, 0) +#define FUNC_LCDOUT12 IPSR(3, 12, 1) +#define FUNC_MSIOF3_SCK_C IPSR(3, 12, 2) +#define FUNC_HRX4_A IPSR(3, 12, 4) +#define FUNC_VI5_DATA8 IPSR(3, 12, 5) +#define FUNC_DU_DG4 IPSR(3, 12, 6) +#define FUNC_A13 IPSR(3, 16, 0) +#define FUNC_LCDOUT13 IPSR(3, 16, 1) +#define FUNC_MSIOF3_SYNC_C IPSR(3, 16, 2) +#define FUNC_HTX4_A IPSR(3, 16, 4) +#define FUNC_VI5_DATA9 IPSR(3, 16, 5) +#define FUNC_DU_DG5 IPSR(3, 16, 6) +#define FUNC_A14 IPSR(3, 20, 0) +#define FUNC_LCDOUT14 IPSR(3, 20, 1) +#define FUNC_MSIOF3_RXD_C IPSR(3, 20, 2) +#define FUNC_HCTS4_N IPSR(3, 20, 4) +#define FUNC_VI5_DATA10 IPSR(3, 20, 5) +#define FUNC_DU_DG6 IPSR(3, 20, 6) +#define FUNC_A15 IPSR(3, 24, 0) +#define FUNC_LCDOUT15 IPSR(3, 24, 1) +#define FUNC_MSIOF3_TXD_C IPSR(3, 24, 2) +#define FUNC_HRTS4_N IPSR(3, 24, 4) +#define FUNC_VI5_DATA11 IPSR(3, 24, 5) +#define FUNC_DU_DG7 IPSR(3, 24, 6) +#define FUNC_A16 IPSR(3, 28, 0) +#define FUNC_LCDOUT8 IPSR(3, 28, 1) +#define FUNC_VI4_FIELD IPSR(3, 28, 4) +#define FUNC_DU_DG0 IPSR(3, 28, 6) +#define FUNC_A17 IPSR(4, 0, 0) +#define FUNC_LCDOUT9 IPSR(4, 0, 1) +#define FUNC_VI4_VSYNC_N IPSR(4, 0, 4) +#define FUNC_DU_DG1 IPSR(4, 0, 6) +#define FUNC_A18 IPSR(4, 4, 0) +#define FUNC_LCDOUT10 IPSR(4, 4, 1) +#define FUNC_VI4_HSYNC_N IPSR(4, 4, 4) +#define FUNC_DU_DG2 IPSR(4, 4, 6) +#define FUNC_A19 IPSR(4, 8, 0) +#define FUNC_LCDOUT11 IPSR(4, 8, 1) +#define FUNC_VI4_CLKENB IPSR(4, 8, 4) +#define FUNC_DU_DG3 IPSR(4, 8, 6) +#define FUNC_CS0_N IPSR(4, 12, 0) +#define FUNC_VI5_CLKENB IPSR(4, 12, 5) +#define FUNC_CS1_N IPSR(4, 16, 0) +#define FUNC_VI5_CLK IPSR(4, 16, 5) +#define FUNC_EX_WAIT0_B IPSR(4, 16, 7) +#define FUNC_BS_N IPSR(4, 20, 0) +#define FUNC_QSTVA_QVS IPSR(4, 20, 1) +#define FUNC_MSIOF3_SCK_D IPSR(4, 20, 2) +#define FUNC_SCK3 IPSR(4, 20, 3) +#define FUNC_HSCK3 IPSR(4, 20, 4) +#define FUNC_CAN1_TX IPSR(4, 20, 8) +#define FUNC_CANFD1_TX IPSR(4, 20, 9) +#define FUNC_IETX_A IPSR(4, 20, 0xA) +#define FUNC_RD_N IPSR(4, 24, 0) +#define FUNC_MSIOF3_SYNC_D IPSR(4, 24, 2) +#define FUNC_RX3_A IPSR(4, 24, 3) +#define FUNC_HRX3_A IPSR(4, 24, 4) +#define FUNC_CAN0_TX_A IPSR(4, 24, 8) +#define FUNC_CANFD0_TX_A IPSR(4, 24, 9) +#define FUNC_RD_WR_N IPSR(4, 28, 0) +#define FUNC_MSIOF3_RXD_D IPSR(4, 28, 2) +#define FUNC_TX3_A IPSR(4, 28, 3) +#define FUNC_HTX3_A IPSR(4, 28, 4) +#define FUNC_CAN0_RX_A IPSR(4, 28, 8) +#define FUNC_CANFD0_RX_A IPSR(4, 28, 9) +#define FUNC_WE0_N IPSR(5, 0, 0) +#define FUNC_MSIOF3_TXD_D IPSR(5, 0, 2) +#define FUNC_CTS3_N IPSR(5, 0, 3) +#define FUNC_HCTS3_N IPSR(5, 0, 4) +#define FUNC_SCL6_B IPSR(5, 0, 7) +#define FUNC_CAN_CLK IPSR(5, 0, 8) +#define FUNC_IECLK_A IPSR(5, 0, 0xA) +#define FUNC_WE1_N IPSR(5, 4, 0) +#define FUNC_MSIOF3_SS1_D IPSR(5, 4, 2) +#define FUNC_RTS3_N IPSR(5, 4, 3) +#define FUNC_HRTS3_N IPSR(5, 4, 4) +#define FUNC_SDA6_B IPSR(5, 4, 7) +#define FUNC_CAN1_RX IPSR(5, 4, 8) +#define FUNC_CANFD1_RX IPSR(5, 4, 9) +#define FUNC_IERX_A IPSR(5, 4, 0xA) +#define FUNC_EX_WAIT0_A IPSR(5, 8, 0) +#define FUNC_QCLK IPSR(5, 8, 1) +#define FUNC_VI4_CLK IPSR(5, 8, 4) +#define FUNC_DU_DOTCLKOUT0 IPSR(5, 8, 6) +#define FUNC_D0 IPSR(5, 12, 0) +#define FUNC_MSIOF2_SS1_B IPSR(5, 12, 1) +#define FUNC_MSIOF3_SCK_A IPSR(5, 12, 2) +#define FUNC_VI4_DATA16 IPSR(5, 12, 4) +#define FUNC_VI5_DATA0 IPSR(5, 12, 5) +#define FUNC_D1 IPSR(5, 16, 0) +#define FUNC_MSIOF2_SS2_B IPSR(5, 16, 1) +#define FUNC_MSIOF3_SYNC_A IPSR(5, 16, 2) +#define FUNC_VI4_DATA17 IPSR(5, 16, 4) +#define FUNC_VI5_DATA1 IPSR(5, 16, 5) +#define FUNC_D2 IPSR(5, 20, 0) +#define FUNC_MSIOF3_RXD_A IPSR(5, 20, 2) +#define FUNC_VI4_DATA18 IPSR(5, 20, 4) +#define FUNC_VI5_DATA2 IPSR(5, 20, 5) +#define FUNC_D3 IPSR(5, 24, 0) +#define FUNC_MSIOF3_TXD_A IPSR(5, 24, 2) +#define FUNC_VI4_DATA19 IPSR(5, 24, 4) +#define FUNC_VI5_DATA3 IPSR(5, 24, 5) +#define FUNC_D4 IPSR(5, 28, 0) +#define FUNC_MSIOF2_SCK_B IPSR(5, 28, 1) +#define FUNC_VI4_DATA20 IPSR(5, 28, 4) +#define FUNC_VI5_DATA4 IPSR(5, 28, 5) +#define FUNC_D5 IPSR(6, 0, 0) +#define FUNC_MSIOF2_SYNC_B IPSR(6, 0, 1) +#define FUNC_VI4_DATA21 IPSR(6, 0, 4) +#define FUNC_VI5_DATA5 IPSR(6, 0, 5) +#define FUNC_D6 IPSR(6, 4, 0) +#define FUNC_MSIOF2_RXD_B IPSR(6, 4, 1) +#define FUNC_VI4_DATA22 IPSR(6, 4, 4) +#define FUNC_VI5_DATA6 IPSR(6, 4, 5) +#define FUNC_D7 IPSR(6, 8, 0) +#define FUNC_MSIOF2_TXD_B IPSR(6, 8, 1) +#define FUNC_VI4_DATA23 IPSR(6, 8, 4) +#define FUNC_VI5_DATA7 IPSR(6, 8, 5) +#define FUNC_D8 IPSR(6, 12, 0) +#define FUNC_LCDOUT0 IPSR(6, 12, 1) +#define FUNC_MSIOF2_SCK_D IPSR(6, 12, 2) +#define FUNC_SCK4_C IPSR(6, 12, 3) +#define FUNC_VI4_DATA0_A IPSR(6, 12, 4) +#define FUNC_DU_DR0 IPSR(6, 12, 6) +#define FUNC_D9 IPSR(6, 16, 0) +#define FUNC_LCDOUT1 IPSR(6, 16, 1) +#define FUNC_MSIOF2_SYNC_D IPSR(6, 16, 2) +#define FUNC_VI4_DATA1_A IPSR(6, 16, 4) +#define FUNC_DU_DR1 IPSR(6, 16, 6) +#define FUNC_D10 IPSR(6, 20, 0) +#define FUNC_LCDOUT2 IPSR(6, 20, 1) +#define FUNC_MSIOF2_RXD_D IPSR(6, 20, 2) +#define FUNC_HRX3_B IPSR(6, 20, 3) +#define FUNC_VI4_DATA2_A IPSR(6, 20, 4) +#define FUNC_CTS4_N_C IPSR(6, 20, 5) +#define FUNC_DU_DR2 IPSR(6, 20, 6) +#define FUNC_D11 IPSR(6, 24, 0) +#define FUNC_LCDOUT3 IPSR(6, 24, 1) +#define FUNC_MSIOF2_TXD_D IPSR(6, 24, 2) +#define FUNC_HTX3_B IPSR(6, 24, 3) +#define FUNC_VI4_DATA3_A IPSR(6, 24, 4) +#define FUNC_RTS4_N_C IPSR(6, 24, 5) +#define FUNC_DU_DR3 IPSR(6, 24, 6) +#define FUNC_D12 IPSR(6, 28, 0) +#define FUNC_LCDOUT4 IPSR(6, 28, 1) +#define FUNC_MSIOF2_SS1_D IPSR(6, 28, 2) +#define FUNC_RX4_C IPSR(6, 28, 3) +#define FUNC_VI4_DATA4_A IPSR(6, 28, 4) +#define FUNC_DU_DR4 IPSR(6, 28, 6) +#define FUNC_D13 IPSR(7, 0, 0) +#define FUNC_LCDOUT5 IPSR(7, 0, 1) +#define FUNC_MSIOF2_SS2_D IPSR(7, 0, 2) +#define FUNC_TX4_C IPSR(7, 0, 3) +#define FUNC_VI4_DATA5_A IPSR(7, 0, 4) +#define FUNC_DU_DR5 IPSR(7, 0, 6) +#define FUNC_D14 IPSR(7, 4, 0) +#define FUNC_LCDOUT6 IPSR(7, 4, 1) +#define FUNC_MSIOF3_SS1_A IPSR(7, 4, 2) +#define FUNC_HRX3_C IPSR(7, 4, 3) +#define FUNC_VI4_DATA6_A IPSR(7, 4, 4) +#define FUNC_DU_DR6 IPSR(7, 4, 6) +#define FUNC_SCL6_C IPSR(7, 4, 7) +#define FUNC_D15 IPSR(7, 8, 0) +#define FUNC_LCDOUT7 IPSR(7, 8, 1) +#define FUNC_MSIOF3_SS2_A IPSR(7, 8, 2) +#define FUNC_HTX3_C IPSR(7, 8, 3) +#define FUNC_VI4_DATA7_A IPSR(7, 8, 4) +#define FUNC_DU_DR7 IPSR(7, 8, 6) +#define FUNC_SDA6_C IPSR(7, 8, 7) +#define FUNC_SD0_CLK IPSR(7, 16, 0) +#define FUNC_MSIOF1_SCK_E IPSR(7, 16, 2) +#define FUNC_STP_OPWM_0_B IPSR(7, 16, 6) +#define FUNC_SD0_CMD IPSR(7, 20, 0) +#define FUNC_MSIOF1_SYNC_E IPSR(7, 20, 2) +#define FUNC_STP_IVCXO27_0_B IPSR(7, 20, 6) +#define FUNC_SD0_DAT0 IPSR(7, 24, 0) +#define FUNC_MSIOF1_RXD_E IPSR(7, 24, 2) +#define FUNC_TS_SCK0_B IPSR(7, 24, 5) +#define FUNC_STP_ISCLK_0_B IPSR(7, 24, 6) +#define FUNC_SD0_DAT1 IPSR(7, 28, 0) +#define FUNC_MSIOF1_TXD_E IPSR(7, 28, 2) +#define FUNC_TS_SPSYNC0_B IPSR(7, 28, 5) +#define FUNC_STP_ISSYNC_0_B IPSR(7, 28, 6) +#define FUNC_SD0_DAT2 IPSR(8, 0, 0) +#define FUNC_MSIOF1_SS1_E IPSR(8, 0, 2) +#define FUNC_TS_SDAT0_B IPSR(8, 0, 5) +#define FUNC_STP_ISD_0_B IPSR(8, 0, 6) +#define FUNC_SD0_DAT3 IPSR(8, 4, 0) +#define FUNC_MSIOF1_SS2_E IPSR(8, 4, 2) +#define FUNC_TS_SDEN0_B IPSR(8, 4, 5) +#define FUNC_STP_ISEN_0_B IPSR(8, 4, 6) +#define FUNC_SD1_CLK IPSR(8, 8, 0) +#define FUNC_MSIOF1_SCK_G IPSR(8, 8, 2) +#define FUNC_SIM0_CLK_A IPSR(8, 8, 5) +#define FUNC_SD1_CMD IPSR(8, 12, 0) +#define FUNC_MSIOF1_SYNC_G IPSR(8, 12, 2) +#define FUNC_NFCE_N_B IPSR(8, 12, 3) +#define FUNC_SIM0_D_A IPSR(8, 12, 5) +#define FUNC_STP_IVCXO27_1_B IPSR(8, 12, 6) +#define FUNC_SD1_DAT0 IPSR(8, 16, 0) +#define FUNC_SD2_DAT4 IPSR(8, 16, 1) +#define FUNC_MSIOF1_RXD_G IPSR(8, 16, 2) +#define FUNC_NFWP_N_B IPSR(8, 16, 3) +#define FUNC_TS_SCK1_B IPSR(8, 16, 5) +#define FUNC_STP_ISCLK_1_B IPSR(8, 16, 6) +#define FUNC_SD1_DAT1 IPSR(8, 20, 0) +#define FUNC_SD2_DAT5 IPSR(8, 20, 1) +#define FUNC_MSIOF1_TXD_G IPSR(8, 20, 2) +#define FUNC_NFDATA14_B IPSR(8, 20, 3) +#define FUNC_TS_SPSYNC1_B IPSR(8, 20, 5) +#define FUNC_STP_ISSYNC_1_B IPSR(8, 20, 6) +#define FUNC_SD1_DAT2 IPSR(8, 24, 0) +#define FUNC_SD2_DAT6 IPSR(8, 24, 1) +#define FUNC_MSIOF1_SS1_G IPSR(8, 24, 2) +#define FUNC_NFDATA15_B IPSR(8, 24, 3) +#define FUNC_TS_SDAT1_B IPSR(8, 24, 5) +#define FUNC_STP_ISD_1_B IPSR(8, 24, 6) +#define FUNC_SD1_DAT3 IPSR(8, 28, 0) +#define FUNC_SD2_DAT7 IPSR(8, 28, 1) +#define FUNC_MSIOF1_SS2_G IPSR(8, 28, 2) +#define FUNC_NFRB_N_B IPSR(8, 28, 3) +#define FUNC_TS_SDEN1_B IPSR(8, 28, 5) +#define FUNC_STP_ISEN_1_B IPSR(8, 28, 6) +#define FUNC_SD2_CLK IPSR(9, 0, 0) +#define FUNC_NFDATA8 IPSR(9, 0, 2) +#define FUNC_SD2_CMD IPSR(9, 4, 0) +#define FUNC_NFDATA9 IPSR(9, 4, 2) +#define FUNC_SD2_DAT0 IPSR(9, 8, 0) +#define FUNC_NFDATA10 IPSR(9, 8, 2) +#define FUNC_SD2_DAT1 IPSR(9, 12, 0) +#define FUNC_NFDATA11 IPSR(9, 12, 2) +#define FUNC_SD2_DAT2 IPSR(9, 16, 0) +#define FUNC_NFDATA12 IPSR(9, 16, 2) +#define FUNC_SD2_DAT3 IPSR(9, 20, 0) +#define FUNC_NFDATA13 IPSR(9, 20, 2) +#define FUNC_SD2_DS IPSR(9, 24, 0) +#define FUNC_NFALE IPSR(9, 24, 2) +#define FUNC_SD3_CLK IPSR(9, 28, 0) +#define FUNC_NFWE_N IPSR(9, 28, 2) +#define FUNC_SD3_CMD IPSR(10, 0, 0) +#define FUNC_NFRE_N IPSR(10, 0, 2) +#define FUNC_SD3_DAT0 IPSR(10, 4, 0) +#define FUNC_NFDATA0 IPSR(10, 4, 2) +#define FUNC_SD3_DAT1 IPSR(10, 8, 0) +#define FUNC_NFDATA1 IPSR(10, 8, 2) +#define FUNC_SD3_DAT2 IPSR(10, 12, 0) +#define FUNC_NFDATA2 IPSR(10, 12, 2) +#define FUNC_SD3_DAT3 IPSR(10, 16, 0) +#define FUNC_NFDATA3 IPSR(10, 16, 2) +#define FUNC_SD3_DAT4 IPSR(10, 20, 0) +#define FUNC_SD2_CD_A IPSR(10, 20, 1) +#define FUNC_NFDATA4 IPSR(10, 20, 2) +#define FUNC_SD3_DAT5 IPSR(10, 24, 0) +#define FUNC_SD2_WP_A IPSR(10, 24, 1) +#define FUNC_NFDATA5 IPSR(10, 24, 2) +#define FUNC_SD3_DAT6 IPSR(10, 28, 0) +#define FUNC_SD3_CD IPSR(10, 28, 1) +#define FUNC_NFDATA6 IPSR(10, 28, 2) +#define FUNC_SD3_DAT7 IPSR(11, 0, 0) +#define FUNC_SD3_WP IPSR(11, 0, 1) +#define FUNC_NFDATA7 IPSR(11, 0, 2) +#define FUNC_SD3_DS IPSR(11, 4, 0) +#define FUNC_NFCLE IPSR(11, 4, 2) +#define FUNC_SD0_CD IPSR(11, 8, 0) +#define FUNC_NFDATA14_A IPSR(11, 8, 2) +#define FUNC_SCL2_B IPSR(11, 8, 4) +#define FUNC_SIM0_RST_A IPSR(11, 8, 5) +#define FUNC_SD0_WP IPSR(11, 12, 0) +#define FUNC_NFDATA15_A IPSR(11, 12, 2) +#define FUNC_SDA2_B IPSR(11, 12, 4) +#define FUNC_SD1_CD IPSR(11, 16, 0) +#define FUNC_NFRB_N_A IPSR(11, 16, 2) +#define FUNC_SIM0_CLK_B IPSR(11, 16, 5) +#define FUNC_SD1_WP IPSR(11, 20, 0) +#define FUNC_NFCE_N_A IPSR(11, 20, 2) +#define FUNC_SIM0_D_B IPSR(11, 20, 5) +#define FUNC_SCK0 IPSR(11, 24, 0) +#define FUNC_HSCK1_B IPSR(11, 24, 1) +#define FUNC_MSIOF1_SS2_B IPSR(11, 24, 2) +#define FUNC_AUDIO_CLKC_B IPSR(11, 24, 3) +#define FUNC_SDA2_A IPSR(11, 24, 4) +#define FUNC_SIM0_RST_B IPSR(11, 24, 5) +#define FUNC_STP_OPWM_0_C IPSR(11, 24, 6) +#define FUNC_RIF0_CLK_B IPSR(11, 24, 7) +#define FUNC_ADICHS2 IPSR(11, 24, 9) +#define FUNC_SCK5_B IPSR(11, 24, 0xA) +#define FUNC_RX0 IPSR(11, 28, 0) +#define FUNC_HRX1_B IPSR(11, 28, 1) +#define FUNC_TS_SCK0_C IPSR(11, 28, 5) +#define FUNC_STP_ISCLK_0_C IPSR(11, 28, 6) +#define FUNC_RIF0_D0_B IPSR(11, 28, 7) +#define FUNC_TX0 IPSR(12, 0, 0) +#define FUNC_HTX1_B IPSR(12, 0, 1) +#define FUNC_TS_SPSYNC0_C IPSR(12, 0, 5) +#define FUNC_STP_ISSYNC_0_C IPSR(12, 0, 6) +#define FUNC_RIF0_D1_B IPSR(12, 0, 7) +#define FUNC_CTS0_N IPSR(12, 4, 0) +#define FUNC_HCTS1_N_B IPSR(12, 4, 1) +#define FUNC_MSIOF1_SYNC_B IPSR(12, 4, 2) +#define FUNC_TS_SPSYNC1_C IPSR(12, 4, 5) +#define FUNC_STP_ISSYNC_1_C IPSR(12, 4, 6) +#define FUNC_RIF1_SYNC_B IPSR(12, 4, 7) +#define FUNC_AUDIO_CLKOUT_C IPSR(12, 4, 8) +#define FUNC_ADICS_SAMP IPSR(12, 4, 9) +#define FUNC_RTS0_N IPSR(12, 8, 0) +#define FUNC_HRTS1_N_B IPSR(12, 8, 1) +#define FUNC_MSIOF1_SS1_B IPSR(12, 8, 2) +#define FUNC_AUDIO_CLKA_B IPSR(12, 8, 3) +#define FUNC_SCL2_A IPSR(12, 8, 4) +#define FUNC_STP_IVCXO27_1_C IPSR(12, 8, 6) +#define FUNC_RIF0_SYNC_B IPSR(12, 8, 7) +#define FUNC_ADICHS1 IPSR(12, 8, 9) +#define FUNC_RX1_A IPSR(12, 12, 0) +#define FUNC_HRX1_A IPSR(12, 12, 1) +#define FUNC_TS_SDAT0_C IPSR(12, 12, 5) +#define FUNC_STP_ISD_0_C IPSR(12, 12, 6) +#define FUNC_RIF1_CLK_C IPSR(12, 12, 7) +#define FUNC_TX1_A IPSR(12, 16, 0) +#define FUNC_HTX1_A IPSR(12, 16, 1) +#define FUNC_TS_SDEN0_C IPSR(12, 16, 5) +#define FUNC_STP_ISEN_0_C IPSR(12, 16, 6) +#define FUNC_RIF1_D0_C IPSR(12, 16, 7) +#define FUNC_CTS1_N IPSR(12, 20, 0) +#define FUNC_HCTS1_N_A IPSR(12, 20, 1) +#define FUNC_MSIOF1_RXD_B IPSR(12, 20, 2) +#define FUNC_TS_SDEN1_C IPSR(12, 20, 5) +#define FUNC_STP_ISEN_1_C IPSR(12, 20, 6) +#define FUNC_RIF1_D0_B IPSR(12, 20, 7) +#define FUNC_ADIDATA IPSR(12, 20, 9) +#define FUNC_RTS1_N IPSR(12, 24, 0) +#define FUNC_HRTS1_N_A IPSR(12, 24, 1) +#define FUNC_MSIOF1_TXD_B IPSR(12, 24, 2) +#define FUNC_TS_SDAT1_C IPSR(12, 24, 5) +#define FUNC_STP_ISD_1_C IPSR(12, 24, 6) +#define FUNC_RIF1_D1_B IPSR(12, 24, 7) +#define FUNC_ADICHS0 IPSR(12, 24, 9) +#define FUNC_SCK2 IPSR(12, 28, 0) +#define FUNC_SCIF_CLK_B IPSR(12, 28, 1) +#define FUNC_MSIOF1_SCK_B IPSR(12, 28, 2) +#define FUNC_TS_SCK1_C IPSR(12, 28, 5) +#define FUNC_STP_ISCLK_1_C IPSR(12, 28, 6) +#define FUNC_RIF1_CLK_B IPSR(12, 28, 7) +#define FUNC_ADICLK IPSR(12, 28, 9) +#define FUNC_TX2_A IPSR(13, 0, 0) +#define FUNC_SD2_CD_B IPSR(13, 0, 3) +#define FUNC_SCL1_A IPSR(13, 0, 4) +#define FUNC_FMCLK_A IPSR(13, 0, 6) +#define FUNC_RIF1_D1_C IPSR(13, 0, 7) +#define FUNC_FSO_CFE_0_N IPSR(13, 0, 9) +#define FUNC_RX2_A IPSR(13, 4, 0) +#define FUNC_SD2_WP_B IPSR(13, 4, 3) +#define FUNC_SDA1_A IPSR(13, 4, 4) +#define FUNC_FMIN_A IPSR(13, 4, 6) +#define FUNC_RIF1_SYNC_C IPSR(13, 4, 7) +#define FUNC_FSO_CFE_1_N IPSR(13, 4, 9) +#define FUNC_HSCK0 IPSR(13, 8, 0) +#define FUNC_MSIOF1_SCK_D IPSR(13, 8, 2) +#define FUNC_AUDIO_CLKB_A IPSR(13, 8, 3) +#define FUNC_SSI_SDATA1_B IPSR(13, 8, 4) +#define FUNC_TS_SCK0_D IPSR(13, 8, 5) +#define FUNC_STP_ISCLK_0_D IPSR(13, 8, 6) +#define FUNC_RIF0_CLK_C IPSR(13, 8, 7) +#define FUNC_RX5_B IPSR(13, 8, 0xA) +#define FUNC_HRX0 IPSR(13, 12, 0) +#define FUNC_MSIOF1_RXD_D IPSR(13, 12, 2) +#define FUNC_SSI_SDATA2_B IPSR(13, 12, 4) +#define FUNC_TS_SDEN0_D IPSR(13, 12, 5) +#define FUNC_STP_ISEN_0_D IPSR(13, 12, 6) +#define FUNC_RIF0_D0_C IPSR(13, 12, 7) +#define FUNC_HTX0 IPSR(13, 16, 0) +#define FUNC_MSIOF1_TXD_D IPSR(13, 16, 2) +#define FUNC_SSI_SDATA9_B IPSR(13, 16, 4) +#define FUNC_TS_SDAT0_D IPSR(13, 16, 5) +#define FUNC_STP_ISD_0_D IPSR(13, 16, 6) +#define FUNC_RIF0_D1_C IPSR(13, 16, 7) +#define FUNC_HCTS0_N IPSR(13, 20, 0) +#define FUNC_RX2_B IPSR(13, 20, 1) +#define FUNC_MSIOF1_SYNC_D IPSR(13, 20, 2) +#define FUNC_SSI_SCK9_A IPSR(13, 20, 4) +#define FUNC_TS_SPSYNC0_D IPSR(13, 20, 5) +#define FUNC_STP_ISSYNC_0_D IPSR(13, 20, 6) +#define FUNC_RIF0_SYNC_C IPSR(13, 20, 7) +#define FUNC_AUDIO_CLKOUT1_A IPSR(13, 20, 8) +#define FUNC_HRTS0_N IPSR(13, 24, 0) +#define FUNC_TX2_B IPSR(13, 24, 1) +#define FUNC_MSIOF1_SS1_D IPSR(13, 24, 2) +#define FUNC_SSI_WS9_A IPSR(13, 24, 4) +#define FUNC_STP_IVCXO27_0_D IPSR(13, 24, 6) +#define FUNC_BPFCLK_A IPSR(13, 24, 7) +#define FUNC_AUDIO_CLKOUT2_A IPSR(13, 24, 8) +#define FUNC_MSIOF0_SYNC IPSR(13, 28, 0) +#define FUNC_AUDIO_CLKOUT_A IPSR(13, 28, 8) +#define FUNC_TX5_B IPSR(13, 28, 0xA) +#define FUNC_BPFCLK_D IPSR(13, 28, 0xD) +#define FUNC_MSIOF0_SS1 IPSR(14, 0, 0) +#define FUNC_RX5_A IPSR(14, 0, 1) +#define FUNC_NFWP_N_A IPSR(14, 0, 2) +#define FUNC_AUDIO_CLKA_C IPSR(14, 0, 3) +#define FUNC_SSI_SCK2_A IPSR(14, 0, 4) +#define FUNC_STP_IVCXO27_0_C IPSR(14, 0, 6) +#define FUNC_AUDIO_CLKOUT3_A IPSR(14, 0, 8) +#define FUNC_TCLK1_B IPSR(14, 0, 0xA) +#define FUNC_MSIOF0_SS2 IPSR(14, 4, 0) +#define FUNC_TX5_A IPSR(14, 4, 1) +#define FUNC_MSIOF1_SS2_D IPSR(14, 4, 2) +#define FUNC_AUDIO_CLKC_A IPSR(14, 4, 3) +#define FUNC_SSI_WS2_A IPSR(14, 4, 4) +#define FUNC_STP_OPWM_0_D IPSR(14, 4, 6) +#define FUNC_AUDIO_CLKOUT_D IPSR(14, 4, 8) +#define FUNC_SPEEDIN_B IPSR(14, 4, 0xA) +#define FUNC_MLB_CLK IPSR(14, 8, 0) +#define FUNC_MSIOF1_SCK_F IPSR(14, 8, 2) +#define FUNC_SCL1_B IPSR(14, 8, 4) +#define FUNC_MLB_SIG IPSR(14, 12, 0) +#define FUNC_RX1_B IPSR(14, 12, 1) +#define FUNC_MSIOF1_SYNC_F IPSR(14, 12, 2) +#define FUNC_SDA1_B IPSR(14, 12, 4) +#define FUNC_MLB_DAT IPSR(14, 16, 0) +#define FUNC_TX1_B IPSR(14, 16, 1) +#define FUNC_MSIOF1_RXD_F IPSR(14, 16, 2) +#define FUNC_SSI_SCK01239 IPSR(14, 20, 0) +#define FUNC_MSIOF1_TXD_F IPSR(14, 20, 2) +#define FUNC_SSI_WS01239 IPSR(14, 24, 0) +#define FUNC_MSIOF1_SS1_F IPSR(14, 24, 2) +#define FUNC_SSI_SDATA0 IPSR(14, 28, 0) +#define FUNC_MSIOF1_SS2_F IPSR(14, 28, 2) +#define FUNC_SSI_SDATA1_A IPSR(15, 0, 0) +#define FUNC_SSI_SDATA2_A IPSR(15, 4, 0) +#define FUNC_SSI_SCK1_B IPSR(15, 4, 4) +#define FUNC_SSI_SCK349 IPSR(15, 8, 0) +#define FUNC_MSIOF1_SS1_A IPSR(15, 8, 2) +#define FUNC_STP_OPWM_0_A IPSR(15, 8, 6) +#define FUNC_SSI_WS349 IPSR(15, 12, 0) +#define FUNC_HCTS2_N_A IPSR(15, 12, 1) +#define FUNC_MSIOF1_SS2_A IPSR(15, 12, 2) +#define FUNC_STP_IVCXO27_0_A IPSR(15, 12, 6) +#define FUNC_SSI_SDATA3 IPSR(15, 16, 0) +#define FUNC_HRTS2_N_A IPSR(15, 16, 1) +#define FUNC_MSIOF1_TXD_A IPSR(15, 16, 2) +#define FUNC_TS_SCK0_A IPSR(15, 16, 5) +#define FUNC_STP_ISCLK_0_A IPSR(15, 16, 6) +#define FUNC_RIF0_D1_A IPSR(15, 16, 7) +#define FUNC_RIF2_D0_A IPSR(15, 16, 8) +#define FUNC_SSI_SCK4 IPSR(15, 20, 0) +#define FUNC_HRX2_A IPSR(15, 20, 1) +#define FUNC_MSIOF1_SCK_A IPSR(15, 20, 2) +#define FUNC_TS_SDAT0_A IPSR(15, 20, 5) +#define FUNC_STP_ISD_0_A IPSR(15, 20, 6) +#define FUNC_RIF0_CLK_A IPSR(15, 20, 7) +#define FUNC_RIF2_CLK_A IPSR(15, 20, 8) +#define FUNC_SSI_WS4 IPSR(15, 24, 0) +#define FUNC_HTX2_A IPSR(15, 24, 1) +#define FUNC_MSIOF1_SYNC_A IPSR(15, 24, 2) +#define FUNC_TS_SDEN0_A IPSR(15, 24, 5) +#define FUNC_STP_ISEN_0_A IPSR(15, 24, 6) +#define FUNC_RIF0_SYNC_A IPSR(15, 24, 7) +#define FUNC_RIF2_SYNC_A IPSR(15, 24, 8) +#define FUNC_SSI_SDATA4 IPSR(15, 28, 0) +#define FUNC_HSCK2_A IPSR(15, 28, 1) +#define FUNC_MSIOF1_RXD_A IPSR(15, 28, 2) +#define FUNC_TS_SPSYNC0_A IPSR(15, 28, 5) +#define FUNC_STP_ISSYNC_0_A IPSR(15, 28, 6) +#define FUNC_RIF0_D0_A IPSR(15, 28, 7) +#define FUNC_RIF2_D1_A IPSR(15, 28, 8) +#define FUNC_SSI_SCK6 IPSR(16, 0, 0) +#define FUNC_SIM0_RST_D IPSR(16, 0, 3) +#define FUNC_SSI_WS6 IPSR(16, 4, 0) +#define FUNC_SIM0_D_D IPSR(16, 4, 3) +#define FUNC_SSI_SDATA6 IPSR(16, 8, 0) +#define FUNC_SIM0_CLK_D IPSR(16, 8, 3) +#define FUNC_SSI_SCK78 IPSR(16, 12, 0) +#define FUNC_HRX2_B IPSR(16, 12, 1) +#define FUNC_MSIOF1_SCK_C IPSR(16, 12, 2) +#define FUNC_TS_SCK1_A IPSR(16, 12, 5) +#define FUNC_STP_ISCLK_1_A IPSR(16, 12, 6) +#define FUNC_RIF1_CLK_A IPSR(16, 12, 7) +#define FUNC_RIF3_CLK_A IPSR(16, 12, 8) +#define FUNC_SSI_WS78 IPSR(16, 16, 0) +#define FUNC_HTX2_B IPSR(16, 16, 1) +#define FUNC_MSIOF1_SYNC_C IPSR(16, 16, 2) +#define FUNC_TS_SDAT1_A IPSR(16, 16, 5) +#define FUNC_STP_ISD_1_A IPSR(16, 16, 6) +#define FUNC_RIF1_SYNC_A IPSR(16, 16, 7) +#define FUNC_RIF3_SYNC_A IPSR(16, 16, 8) +#define FUNC_SSI_SDATA7 IPSR(16, 20, 0) +#define FUNC_HCTS2_N_B IPSR(16, 20, 1) +#define FUNC_MSIOF1_RXD_C IPSR(16, 20, 2) +#define FUNC_TS_SDEN1_A IPSR(16, 20, 5) +#define FUNC_STP_ISEN_1_A IPSR(16, 20, 6) +#define FUNC_RIF1_D0_A IPSR(16, 20, 7) +#define FUNC_RIF3_D0_A IPSR(16, 20, 8) +#define FUNC_TCLK2_A IPSR(16, 20, 0xA) +#define FUNC_SSI_SDATA8 IPSR(16, 24, 0) +#define FUNC_HRTS2_N_B IPSR(16, 24, 1) +#define FUNC_MSIOF1_TXD_C IPSR(16, 24, 2) +#define FUNC_TS_SPSYNC1_A IPSR(16, 24, 5) +#define FUNC_STP_ISSYNC_1_A IPSR(16, 24, 6) +#define FUNC_RIF1_D1_A IPSR(16, 24, 7) +#define FUNC_RIF3_D1_A IPSR(16, 24, 8) +#define FUNC_SSI_SDATA9_A IPSR(16, 28, 0) +#define FUNC_HSCK2_B IPSR(16, 28, 1) +#define FUNC_MSIOF1_SS1_C IPSR(16, 28, 2) +#define FUNC_HSCK1_A IPSR(16, 28, 3) +#define FUNC_SSI_WS1_B IPSR(16, 28, 4) +#define FUNC_SCK1 IPSR(16, 28, 5) +#define FUNC_STP_IVCXO27_1_A IPSR(16, 28, 6) +#define FUNC_SCK5_A IPSR(16, 28, 7) +#define FUNC_AUDIO_CLKA_A IPSR(17, 0, 0) +#define FUNC_AUDIO_CLKB_B IPSR(17, 4, 0) +#define FUNC_SCIF_CLK_A IPSR(17, 4, 1) +#define FUNC_STP_IVCXO27_1_D IPSR(17, 4, 6) +#define FUNC_REMOCON_A IPSR(17, 4, 7) +#define FUNC_TCLK1_A IPSR(17, 4, 0xA) +#define FUNC_USB0_PWEN IPSR(17, 8, 0) +#define FUNC_SIM0_RST_C IPSR(17, 8, 3) +#define FUNC_TS_SCK1_D IPSR(17, 8, 5) +#define FUNC_STP_ISCLK_1_D IPSR(17, 8, 6) +#define FUNC_BPFCLK_B IPSR(17, 8, 7) +#define FUNC_RIF3_CLK_B IPSR(17, 8, 8) +#define FUNC_HSCK2_C IPSR(17, 8, 0xD) +#define FUNC_USB0_OVC IPSR(17, 12, 0) +#define FUNC_SIM0_D_C IPSR(17, 12, 3) +#define FUNC_TS_SDAT1_D IPSR(17, 12, 5) +#define FUNC_STP_ISD_1_D IPSR(17, 12, 6) +#define FUNC_RIF3_SYNC_B IPSR(17, 12, 8) +#define FUNC_HRX2_C IPSR(17, 12, 0xD) +#define FUNC_USB1_PWEN IPSR(17, 16, 0) +#define FUNC_SIM0_CLK_C IPSR(17, 16, 3) +#define FUNC_SSI_SCK1_A IPSR(17, 16, 4) +#define FUNC_TS_SCK0_E IPSR(17, 16, 5) +#define FUNC_STP_ISCLK_0_E IPSR(17, 16, 6) +#define FUNC_FMCLK_B IPSR(17, 16, 7) +#define FUNC_RIF2_CLK_B IPSR(17, 16, 8) +#define FUNC_SPEEDIN_A IPSR(17, 16, 0xA) +#define FUNC_HTX2_C IPSR(17, 16, 0xD) +#define FUNC_USB1_OVC IPSR(17, 20, 0) +#define FUNC_MSIOF1_SS2_C IPSR(17, 20, 2) +#define FUNC_SSI_WS1_A IPSR(17, 20, 4) +#define FUNC_TS_SDAT0_E IPSR(17, 20, 5) +#define FUNC_STP_ISD_0_E IPSR(17, 20, 6) +#define FUNC_FMIN_B IPSR(17, 20, 7) +#define FUNC_RIF2_SYNC_B IPSR(17, 20, 8) +#define FUNC_REMOCON_B IPSR(17, 20, 0xA) +#define FUNC_HCTS2_N_C IPSR(17, 20, 0xD) +#define FUNC_USB30_PWEN IPSR(17, 24, 0) +#define FUNC_AUDIO_CLKOUT_B IPSR(17, 24, 3) +#define FUNC_SSI_SCK2_B IPSR(17, 24, 4) +#define FUNC_TS_SDEN1_D IPSR(17, 24, 5) +#define FUNC_STP_ISEN_1_D IPSR(17, 24, 6) +#define FUNC_STP_OPWM_0_E IPSR(17, 24, 7) +#define FUNC_RIF3_D0_B IPSR(17, 24, 8) +#define FUNC_TCLK2_B IPSR(17, 24, 0xA) +#define FUNC_TPU0TO0 IPSR(17, 24, 0xB) +#define FUNC_BPFCLK_C IPSR(17, 24, 0xC) +#define FUNC_HRTS2_N_C IPSR(17, 24, 0xD) +#define FUNC_USB30_OVC IPSR(17, 28, 0) +#define FUNC_AUDIO_CLKOUT1_B IPSR(17, 28, 3) +#define FUNC_SSI_WS2_B IPSR(17, 28, 4) +#define FUNC_TS_SPSYNC1_D IPSR(17, 28, 5) +#define FUNC_STP_ISSYNC_1_D IPSR(17, 28, 6) +#define FUNC_STP_IVCXO27_0_E IPSR(17, 28, 7) +#define FUNC_RIF3_D1_B IPSR(17, 28, 8) +#define FUNC_FSO_TOE_N IPSR(17, 28, 0xA) +#define FUNC_TPU0TO1 IPSR(17, 28, 0xB) +#define FUNC_GP6_30 IPSR(18, 0, 0) +#define FUNC_AUDIO_CLKOUT2_B IPSR(18, 0, 3) +#define FUNC_SSI_SCK9_B IPSR(18, 0, 4) +#define FUNC_TS_SDEN0_E IPSR(18, 0, 5) +#define FUNC_STP_ISEN_0_E IPSR(18, 0, 6) +#define FUNC_RIF2_D0_B IPSR(18, 0, 8) +#define FUNC_TPU0TO2 IPSR(18, 0, 0xB) +#define FUNC_FMCLK_C IPSR(18, 0, 0xC) +#define FUNC_FMCLK_D IPSR(18, 0, 0xD) +#define FUNC_GP6_31 IPSR(18, 4, 0) +#define FUNC_AUDIO_CLKOUT3_B IPSR(18, 4, 3) +#define FUNC_SSI_WS9_B IPSR(18, 4, 4) +#define FUNC_TS_SPSYNC0_E IPSR(18, 4, 5) +#define FUNC_STP_ISSYNC_0_E IPSR(18, 4, 6) +#define FUNC_RIF2_D1_B IPSR(18, 4, 8) +#define FUNC_TPU0TO3 IPSR(18, 4, 0xB) +#define FUNC_FMIN_C IPSR(18, 4, 0xC) +#define FUNC_FMIN_D IPSR(18, 4, 0xD) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77961_H_ */ diff --git a/soc/renesas/rcar/rcar_gen3/CMakeLists.txt b/soc/renesas/rcar/rcar_gen3/CMakeLists.txt index 7f96e60788e..421ba3ff258 100644 --- a/soc/renesas/rcar/rcar_gen3/CMakeLists.txt +++ b/soc/renesas/rcar/rcar_gen3/CMakeLists.txt @@ -5,14 +5,11 @@ if(CONFIG_SOC_SERIES_RCAR_GEN3_R7) zephyr_sources(r7/soc.c) zephyr_include_directories(r7) - zephyr_library_sources_ifdef(CONFIG_SOC_R8A77951_R7 pfc_r8a77951.c) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") elseif(CONFIG_SOC_SERIES_RCAR_GEN3_A57) zephyr_include_directories(a57) - zephyr_library_sources_ifdef(CONFIG_SOC_R8A77951_A57 pfc_r8a77951.c) - zephyr_library_sources_ifdef(CONFIG_SOC_R8A77961 pfc_r8a77961.c) - zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") endif() diff --git a/soc/renesas/rcar/rcar_gen3/pfc_r8a77961.c b/soc/renesas/rcar/rcar_gen3/pfc_r8a77961.c deleted file mode 100644 index b219e626e44..00000000000 --- a/soc/renesas/rcar/rcar_gen3/pfc_r8a77961.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2023 EPAM Systems - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#include "pinctrl_soc.h" -#include - -const struct pfc_drive_reg pfc_drive_regs[] = { - /* DRVCTRL13 */ - { 0x0334, { - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ - } }, - /* DRVCTRL14 */ - { 0x0338, { - { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ - { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ - { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ - { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ - { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ - { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ - { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ - { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ - } }, - /* DRVCTRL15 */ - { 0x033c, { - { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ - { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ - { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ - { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ - { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ - { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ - { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ - { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ - } }, - /* DRVCTRL16 */ - { 0x0340, { - { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ - { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ - { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ - { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ - { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ - { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ - { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ - { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ - } }, - /* DRVCTRL17 */ - { 0x0344, { - { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ - { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ - { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ - { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ - { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ - { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ - { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ - { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ - } }, - /* DRVCTRL18 */ - { 0x0348, { - { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ - { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ - { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ - { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ - { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ - { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ - { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ - { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ - } }, - { }, -}; - -#define PFC_BIAS_REG(r1, r2) \ - .puen = r1, \ - .pud = r2, \ - .pins = - -const struct pfc_bias_reg pfc_bias_regs[] = { - { PFC_BIAS_REG(0x040c, 0x044c) { /* PUEN3, PUD3 */ - [0 ... 9] = PIN_NONE, - [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ - [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ - [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ - [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ - [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ - [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ - [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ - [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ - [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ - [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ - [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ - [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ - [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ - [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ - [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ - [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ - [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ - [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ - [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ - [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ - [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ - [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ - } }, - { PFC_BIAS_REG(0x0410, 0x0450) { /* PUEN4, PUD4 */ - [0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ - [1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ - [2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ - [3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ - [4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ - [5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ - [6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ - [7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ - [8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ - [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ - [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ - [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ - [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ - [13] = RCAR_GP_PIN(5, 1), /* RX0 */ - [14] = RCAR_GP_PIN(5, 2), /* TX0 */ - [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ - [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ - [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ - [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ - [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ - [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ - [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ - [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ - [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ - [24 ... 31] = PIN_NONE, - } }, - { /* sentinel */ }, -}; -const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void) -{ - return pfc_bias_regs; -} -const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void) -{ - return pfc_drive_regs; -} - -int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index) -{ - /* There is only one register on Gen 3 */ - *reg_index = 0; - return 0; -} From e4e463af812e61bb5bfb4b1087d48e1dbcd9d8d5 Mon Sep 17 00:00:00 2001 From: David Leach Date: Tue, 30 Jan 2024 16:22:54 -0600 Subject: [PATCH 0197/2402] west.yml: Update NXP HAL MCUX-SDK to 2.15.000 Update NXP HAL mcux-sdk to 2.15.000 Signed-off-by: David Leach --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index d63685e9dc8..e998c77b090 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: f436a4529f284067af29ad72af5bd0ad51b09f3e + revision: c5a56361f3e4968a4d1eaa6f91761550b7d81e70 path: modules/hal/nxp groups: - hal From a56c8cfa698851855d93b32275d8780f194573e7 Mon Sep 17 00:00:00 2001 From: Susan Su Date: Wed, 31 Jan 2024 17:45:31 +0800 Subject: [PATCH 0198/2402] drivers: mipi_dsi: dsi_mcux: Remove DSI_DPHY_PLL_VCO definition - The DSI_DPHY_PLL_VCO_MAX and DSI_DPHY_PLL_VCO_MIN macro value is different when changing to different SoC, so the definition is moved to soc level driver header. - Remove the definition in this c file to fix the duplicate definition issue. Signed-off-by: Susan Su --- drivers/mipi_dsi/dsi_mcux.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/mipi_dsi/dsi_mcux.c b/drivers/mipi_dsi/dsi_mcux.c index 0093a2467a0..03b0c39ceaf 100644 --- a/drivers/mipi_dsi/dsi_mcux.c +++ b/drivers/mipi_dsi/dsi_mcux.c @@ -32,10 +32,6 @@ LOG_MODULE_REGISTER(dsi_mcux, CONFIG_MIPI_DSI_LOG_LEVEL); #define DSI_DPHY_PLL_CM_MIN 16U #define DSI_DPHY_PLL_CM_MAX 255U -/* PLL VCO output frequency max value is 1.5GHz, VCO output is (ref_clk / CN ) * CM. */ -#define DSI_DPHY_PLL_VCO_MAX MHZ(1500) -#define DSI_DPHY_PLL_VCO_MIN (DSI_DPHY_PLL_REFCLK_CN_MIN * DSI_DPHY_PLL_CM_MIN) - #define DSI_DPHY_PLL_CO_MIN 0 #define DSI_DPHY_PLL_CO_MAX 3 From f011ad5bb1fa3d337eaf517ec12df1bb68f22e6f Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Thu, 23 Nov 2023 13:01:59 +0200 Subject: [PATCH 0199/2402] drivers: mipi_dbi: smartbond: Add support for MIPI DBI driver class. Add support for the MIPI DBI host controller. Signed-off-by: Ioannis Karachalios --- drivers/mipi_dbi/CMakeLists.txt | 2 + drivers/mipi_dbi/Kconfig | 2 + drivers/mipi_dbi/Kconfig.smartbond | 12 + drivers/mipi_dbi/mipi_dbi_smartbond.c | 620 ++++++++++++++++++ .../mipi-dbi/renesas,smartbond-mipi-dbi.yaml | 54 ++ 5 files changed, 690 insertions(+) create mode 100644 drivers/mipi_dbi/Kconfig.smartbond create mode 100644 drivers/mipi_dbi/mipi_dbi_smartbond.c create mode 100644 dts/bindings/mipi-dbi/renesas,smartbond-mipi-dbi.yaml diff --git a/drivers/mipi_dbi/CMakeLists.txt b/drivers/mipi_dbi/CMakeLists.txt index 5f00319bc82..133e24ca626 100644 --- a/drivers/mipi_dbi/CMakeLists.txt +++ b/drivers/mipi_dbi/CMakeLists.txt @@ -3,3 +3,5 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_sources_ifdef(CONFIG_MIPI_DBI_SPI mipi_dbi_spi.c) + +zephyr_sources_ifdef(CONFIG_MIPI_DBI_SMARTBOND mipi_dbi_smartbond.c) diff --git a/drivers/mipi_dbi/Kconfig b/drivers/mipi_dbi/Kconfig index f8305d29833..89eaa347b7d 100644 --- a/drivers/mipi_dbi/Kconfig +++ b/drivers/mipi_dbi/Kconfig @@ -23,4 +23,6 @@ config MIPI_DBI_INIT_PRIORITY source "drivers/mipi_dbi/Kconfig.spi" +source "drivers/mipi_dbi/Kconfig.smartbond" + endif diff --git a/drivers/mipi_dbi/Kconfig.smartbond b/drivers/mipi_dbi/Kconfig.smartbond new file mode 100644 index 00000000000..a1fb11a560b --- /dev/null +++ b/drivers/mipi_dbi/Kconfig.smartbond @@ -0,0 +1,12 @@ +# Smartbond MIPI DBI host configuration options + +# Copyright (c) 2023 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config MIPI_DBI_SMARTBOND + bool "Smartbond MIPI DBI host controller driver" + depends on DT_HAS_RENESAS_SMARTBOND_MIPI_DBI_ENABLED + default y + select SPI + help + Enable Smartbond MIPI DBI host controller. diff --git a/drivers/mipi_dbi/mipi_dbi_smartbond.c b/drivers/mipi_dbi/mipi_dbi_smartbond.c new file mode 100644 index 00000000000..6187d38d16e --- /dev/null +++ b/drivers/mipi_dbi/mipi_dbi_smartbond.c @@ -0,0 +1,620 @@ +/* + * Copyright (c) 2023 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT renesas_smartbond_mipi_dbi + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +LOG_MODULE_REGISTER(smartbond_mipi_dbi, CONFIG_MIPI_DBI_LOG_LEVEL); + +#define SMARTBOND_IRQN DT_INST_IRQN(0) +#define SMARTBOND_IRQ_PRIO DT_INST_IRQ(0, priority) + +#define PINCTRL_STATE_READ PINCTRL_STATE_PRIV_START + +#define MIPI_DBI_SMARTBOND_IS_READ_SUPPORTED \ + DT_INST_NODE_HAS_PROP(0, spi_dev) + +#define LCDC_SMARTBOND_CLK_DIV(_freq) \ + ((32000000U % (_freq)) ? (96000000U / (_freq)) : (32000000U / (_freq))) + +#define MIPI_DBI_SMARTBOND_IS_PLL_REQUIRED \ + !!(32000000U % DT_PROP(DT_CHOSEN(zephyr_display), mipi_max_frequency)) + +#define MIPI_DBI_SMARTBOND_IS_TE_ENABLED \ + DT_INST_PROP_OR(0, te_enable, 0) + +#define MIPI_DBI_SMARTBOND_IS_DMA_PREFETCH_ENABLED \ + DT_INST_ENUM_IDX_OR(0, dma_prefetch, 0) + +#define MIPI_DBI_SMARTBOND_IS_RESET_AVAILABLE \ + DT_INST_NODE_HAS_PROP(0, reset_gpios) + +#define LCDC_LAYER0_OFFSETX_REG_SET_FIELD(_field, _var, _val) \ + ((_var)) = \ + ((_var) & ~(LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk)) | \ + (((_var) << LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Pos) & \ + LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk) + +struct mipi_dbi_smartbond_data { + /* Provide mutual exclusion when a display operation is requested. */ + struct k_sem device_sem; + /* Provide synchronization between task return and ISR firing */ + struct k_sem sync_sem; + /* Flag indicating whether or not an underflow took place */ + volatile bool underflow_flag; + /* Layer settings */ + lcdc_smartbond_layer_cfg layer; +}; + +struct mipi_dbi_smartbond_config { + /* Reference to device instance's pinctrl configurations */ + const struct pinctrl_dev_config *pcfg; + /* Reset GPIO */ + const struct gpio_dt_spec reset; + /* Host controller's timing settings */ + lcdc_smartbond_timing_cfg timing_cfg; + /* Background default color configuration */ + lcdc_smartbond_bgcolor_cfg bgcolor_cfg; +}; + +/* Mark the device is is progress and so it's not allowed to enter the sleep state. */ +static void mipi_dbi_pm_get(const struct device *dev) +{ +#if CONFIG_PM_DEVICE + /* + * By marking the device as busy, PM will not communicate PM events + * to the device via mipi_dbi_smartbond_pm_action. It's OK if PM is + * not used at all. Executing a single frame requires waiting for + * the frame to be completed. As such, the system might enter the idle + * state if no other tasks are pending and for as long as the frame is + * being sent. + * + * XXX: Another option would be to use a flag and mark when the controller + * is in progress so a negative value other than -ENOSYS, -ENOTSUP or + * -EALREADY is returned in mipi_dbi_smartbond_pm_action. Sideffect + * of this approach is that the sleep state will be aborted at all, + * though the system could enter a low-power state, instead (see comment + * below on how to achieve a low-power state). + */ + pm_device_busy_set(dev); +#endif +#if CONFIG_PM + /* + * LCDC controller resides in PD_SYS which is turned off when the system enters + * the extended sleep state. By calling this API, a reference counter is + * incremented, designating that the specific power domain should not be turned off. + * As a result, a low-power state (i.e. ARM WFI) will be selected, instead (when the + * system is idle). + */ + (void)da1469x_pd_acquire_noconf(MCU_PD_DOMAIN_SYS); +#endif +} + +/* Mark that device is inactive and so it's allowed to enter the sleep state */ +static void mipi_dbi_pm_put(const struct device *dev) +{ +#if CONFIG_PM_DEVICE + (void)pm_device_busy_clear(dev); +#endif +#if CONFIG_PM + (void)da1469x_pd_release_nowait(MCU_PD_DOMAIN_SYS); +#endif +} + +/* Helper function to trigger the LCDC fetching data from frame buffer to the connected display */ +static void mipi_dbi_smartbond_send_single_frame(const struct device *dev) +{ + struct mipi_dbi_smartbond_data *data = dev->data; + +#if MIPI_DBI_SMARTBOND_IS_TE_ENABLED + da1469x_lcdc_te_set_status(true, DT_INST_PROP_OR(0, te_polarity, false)); + /* + * Wait for the TE signal to be asserted so display's refresh status can be synchronized + * with the current frame update. + */ + k_sem_take(&data->sync_sem, K_FOREVER); +#endif + + LCDC->LCDC_INTERRUPT_REG |= LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk; + + /* Setting this bit will enable the host to start outputing pixel data */ + LCDC->LCDC_MODE_REG |= LCDC_LCDC_MODE_REG_LCDC_SFRAME_UPD_Msk; + + /* Wait for frame update to complete */ + k_sem_take(&data->sync_sem, K_FOREVER); + + if (data->underflow_flag) { + LOG_WRN("Underflow took place"); + data->underflow_flag = false; + } +} + +#if MIPI_DBI_SMARTBOND_IS_RESET_AVAILABLE +static int mipi_dbi_smartbond_reset(const struct device *dev, uint32_t delay) +{ + const struct mipi_dbi_smartbond_config *config = dev->config; + int ret; + + if (!gpio_is_ready_dt(&config->reset)) { + LOG_ERR("Reset signal not available"); + return -ENODEV; + } + + ret = gpio_pin_set_dt(&config->reset, 1); + if (ret < 0) { + LOG_ERR("Cannot drive reset signal"); + return ret; + } + k_msleep(delay); + + return gpio_pin_set_dt(&config->reset, 0); +} +#endif + +/* Display pixel to output color format translation */ +static inline uint8_t lcdc_smartbond_pixel_to_ocm(enum display_pixel_format pixfmt) +{ + switch (pixfmt) { + case PIXEL_FORMAT_RGB_565: + return (uint8_t)LCDC_SMARTBOND_OCM_RGB565; + case PIXEL_FORMAT_RGB_888: + return (uint8_t)LCDC_SMARTBOND_OCM_RGB888; + case PIXEL_FORMAT_MONO10: + return (uint8_t)LCDC_SMARTBOND_L0_L1; + default: + LOG_ERR("Unsupported pixel format"); + return 0; + }; +} + +static inline uint8_t lcdc_smartbond_line_mode_translation(uint8_t mode) +{ + switch (mode) { + case MIPI_DBI_MODE_SPI_3WIRE: + return (uint8_t)LCDC_SMARTBOND_MODE_SPI3; + case MIPI_DBI_MODE_SPI_4WIRE: + return (uint8_t)LCDC_SMARTBOND_MODE_SPI4; + default: + LOG_ERR("Unsupported SPI mode"); + return 0; + } +} + +static inline uint8_t lcdc_smartbond_pixel_to_lcm(enum display_pixel_format pixfmt) +{ + switch (pixfmt) { + case PIXEL_FORMAT_RGB_565: + return (uint8_t)LCDC_SMARTBOND_L0_RGB565; + case PIXEL_FORMAT_ARGB_8888: + return (uint8_t)LCDC_SMARTBOND_L0_ARGB8888; + default: + LOG_ERR("Unsupported pixel format"); + return 0; + }; +} + +static void lcdc_smartbond_mipi_dbi_translation(const struct mipi_dbi_config *dbi_config, + lcdc_smartbond_mipi_dbi_cfg *mipi_dbi_cfg, + enum display_pixel_format pixfmt) +{ + mipi_dbi_cfg->cpha = dbi_config->config.operation & SPI_MODE_CPHA; + mipi_dbi_cfg->cpol = dbi_config->config.operation & SPI_MODE_CPOL; + mipi_dbi_cfg->cs_active_high = dbi_config->config.operation & SPI_CS_ACTIVE_HIGH; + mipi_dbi_cfg->line_mode = lcdc_smartbond_line_mode_translation(dbi_config->mode); + mipi_dbi_cfg->color_mode = lcdc_smartbond_pixel_to_ocm(pixfmt); +} + +#if MIPI_DBI_SMARTBOND_IS_READ_SUPPORTED +static int mipi_dbi_smartbond_command_read(const struct device *dev, + const struct mipi_dbi_config *dbi_config, + uint8_t *cmd, size_t num_cmds, + uint8_t *response, size_t len) +{ + struct mipi_dbi_smartbond_data *data = dev->data; + const struct mipi_dbi_smartbond_config *config = dev->config; + int ret = 0; + lcdc_smartbond_mipi_dbi_cfg mipi_dbi_cfg; + + k_sem_take(&data->device_sem, K_FOREVER); + + /* + * Add an arbitrary valid color format to satisfy subroutine. The MIPI DBI command/data + * engine should not be affected. + */ + lcdc_smartbond_mipi_dbi_translation(dbi_config, &mipi_dbi_cfg, PIXEL_FORMAT_RGB_565); + ret = da1469x_lcdc_mipi_dbi_interface_configure(&mipi_dbi_cfg); + if (ret < 0) { + goto _mipi_dbi_read_exit; + } + + /* Check if the cmd/data engine is busy since the #CS line will be overruled. */ + if (da1469x_lcdc_is_busy()) { + LOG_WRN("MIPI DBI host is busy"); + ret = -EBUSY; + goto _mipi_dbi_read_exit; + } + + /* Force CS line to low. Typically, command and data are bound in the same #CS assertion */ + da1469x_lcdc_force_cs_line(true, mipi_dbi_cfg.cs_active_high); + + da1469x_lcdc_send_cmd_data(true, cmd, num_cmds); + + if (len) { + const struct device *spi_dev = DEVICE_DT_GET(DT_INST_PHANDLE(0, spi_dev)); + + struct spi_buf buffer = { + .buf = (void *)response, + .len = len, + }; + struct spi_buf_set buf_set = { + .buffers = &buffer, + .count = 1, + }; + + if (!device_is_ready(spi_dev)) { + LOG_ERR("SPI device is not ready"); + ret = -ENODEV; + goto _mipi_dbi_read_exit; + } + + /* Overwrite CLK and enable DI lines. CS is driven forcefully. */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_READ); + if (ret < 0) { + LOG_ERR("Could not apply MIPI DBI pins' SPI read state (%d)", ret); + goto _mipi_dbi_read_exit; + } + + /* Get response */ + ret = spi_read(spi_dev, &dbi_config->config, &buf_set); + if (ret < 0) { + LOG_ERR("Could not read data from SPI"); + goto _mipi_dbi_read_exit; + } + } + +_mipi_dbi_read_exit: + + /* Restore #CS line */ + da1469x_lcdc_force_cs_line(false, mipi_dbi_cfg.cs_active_high); + + /* Make sure default LCDC pins are applied upon exit */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + LOG_ERR("Could not apply MIPI DBI pins' default state (%d)", ret); + } + + k_sem_give(&data->device_sem); + + return ret; +} +#endif + +static int mipi_dbi_smartbond_command_write(const struct device *dev, + const struct mipi_dbi_config *dbi_config, + uint8_t cmd, const uint8_t *data_buf, + size_t len) +{ + struct mipi_dbi_smartbond_data *data = dev->data; + int ret; + lcdc_smartbond_mipi_dbi_cfg mipi_dbi_cfg; + + k_sem_take(&data->device_sem, K_FOREVER); + + mipi_dbi_pm_get(dev); + + /* + * Add an arbitrary valid color format to satisfy subroutine. The MIPI DBI command/data + * engine should not be affected. + */ + lcdc_smartbond_mipi_dbi_translation(dbi_config, &mipi_dbi_cfg, PIXEL_FORMAT_RGB_565); + ret = da1469x_lcdc_mipi_dbi_interface_configure(&mipi_dbi_cfg); + if (ret < 0) { + k_sem_give(&data->device_sem); + return ret; + } + + /* Command and accompanied data should be transmitted via the DBIB interface */ + da1469x_lcdc_send_cmd_data(true, &cmd, 1); + + if (len) { + /* Data should be transmitted via the DBIB interface */ + da1469x_lcdc_send_cmd_data(false, data_buf, len); + } + + mipi_dbi_pm_put(dev); + + k_sem_give(&data->device_sem); + + return 0; +} + +static int mipi_dbi_smartbond_write_display(const struct device *dev, + const struct mipi_dbi_config *dbi_config, + const uint8_t *framebuf, + struct display_buffer_descriptor *desc, + enum display_pixel_format pixfmt) +{ + struct mipi_dbi_smartbond_data *data = dev->data; + const struct mipi_dbi_smartbond_config *config = dev->config; + lcdc_smartbond_layer_cfg *layer = &data->layer; + int ret = 0; + lcdc_smartbond_mipi_dbi_cfg mipi_dbi_cfg; + uint8_t layer_color = lcdc_smartbond_pixel_to_lcm(pixfmt); + + if (desc->width * desc->height * (DISPLAY_BITS_PER_PIXEL(pixfmt) / 8) != + desc->buf_size) { + LOG_ERR("Incorrect buffer size for given width and height"); + return -EINVAL; + } + + k_sem_take(&data->device_sem, K_FOREVER); + + mipi_dbi_pm_get(dev); + + /* + * Mainly check if the frame generator is busy with a pending frame update (might happen + * when two frame updates take place one after the other and the display interface is + * quite slow). VSYNC interrupt line should be asserted when the last line is being + * outputed. + */ + if (da1469x_lcdc_is_busy()) { + LOG_WRN("MIPI DBI host is busy"); + ret = -EBUSY; + goto _mipi_dbi_write_exit; + } + + lcdc_smartbond_mipi_dbi_translation(dbi_config, &mipi_dbi_cfg, pixfmt); + ret = da1469x_lcdc_mipi_dbi_interface_configure(&mipi_dbi_cfg); + if (ret < 0) { + goto _mipi_dbi_write_exit; + } + + ret = da1469x_lcdc_timings_configure(desc->width, desc->height, + (lcdc_smartbond_timing_cfg *)&config->timing_cfg); + if (ret < 0) { + goto _mipi_dbi_write_exit; + } + + LCDC_SMARTBOND_LAYER_CONFIG(layer, framebuf, 0, 0, desc->width, desc->height, + layer_color, + da1469x_lcdc_stride_calculation(layer_color, desc->width)); + ret = da1469x_lcdc_layer_configure(layer); + if (ret < 0) { + goto _mipi_dbi_write_exit; + } + + /* Trigger single frame update via the LCDC-DMA engine */ + mipi_dbi_smartbond_send_single_frame(dev); + +_mipi_dbi_write_exit: + + mipi_dbi_pm_put(dev); + + k_sem_give(&data->device_sem); + + return ret; +} + +static int mipi_dbi_smartbond_configure(const struct device *dev) +{ + uint8_t clk_div = + LCDC_SMARTBOND_CLK_DIV(DT_PROP(DT_CHOSEN(zephyr_display), mipi_max_frequency)); + const struct mipi_dbi_smartbond_config *config = dev->config; + + /* + * First enable the controller so registers can be written. In serial interfaces + * clock divider is further divided by 2. + */ + da1469x_lcdc_set_status(true, MIPI_DBI_SMARTBOND_IS_PLL_REQUIRED, + (clk_div >= 2 ? clk_div / 2 : clk_div)); + + if (!da1469x_lcdc_check_id()) { + LOG_ERR("Mismatching LCDC ID"); + da1469x_lcdc_set_status(false, 0, 0); + return -EINVAL; + } + + da1469x_lcdc_te_set_status(false, DT_INST_PROP_OR(0, te_polarity, false)); + + da1469x_lcdc_bgcolor_configure((lcdc_smartbond_bgcolor_cfg *)&config->bgcolor_cfg); + + LCDC_LAYER0_OFFSETX_REG_SET_FIELD(LCDC_L0_DMA_PREFETCH, + LCDC->LCDC_LAYER0_OFFSETX_REG, MIPI_DBI_SMARTBOND_IS_DMA_PREFETCH_ENABLED); + + return 0; +} + +static void smartbond_mipi_dbi_isr(const void *arg) +{ + struct mipi_dbi_smartbond_data *data = ((const struct device *)arg)->data; + + /* + * Underflow sticky bit will remain high until cleared by writing + * any value to LCDC_INTERRUPT_REG. + */ + data->underflow_flag = LCDC_STATUS_REG_GET_FIELD(LCDC_STICKY_UNDERFLOW); + + /* Default interrupt mode is level triggering so interrupt should be cleared */ + da1469x_lcdc_te_set_status(false, DT_INST_PROP_OR(0, te_polarity, false)); + + k_sem_give(&data->sync_sem); +} + +static int mipi_dbi_smartbond_resume(const struct device *dev) +{ + const struct mipi_dbi_smartbond_config *config = dev->config; + int ret; + + /* Select default state */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + LOG_ERR("Could not apply LCDC pins' default state (%d)", ret); + return -EIO; + } + +#if MIPI_DBI_SMARTBOND_IS_PLL_REQUIRED + const struct device *clock_dev = DEVICE_DT_GET(DT_NODELABEL(osc)); + + if (!device_is_ready(clock_dev)) { + LOG_WRN("Clock device is not available; PLL cannot be used"); + } else { + ret = z_smartbond_select_sys_clk(SMARTBOND_CLK_PLL96M); + if (ret < 0) { + LOG_WRN("Could not switch to PLL. Requested speed should not be achieved."); + } + } +#endif + + return mipi_dbi_smartbond_configure(dev); +} + +#ifdef CONFIG_PM_DEVICE +static int mipi_dbi_smartbond_suspend(const struct device *dev) +{ + const struct mipi_dbi_smartbond_config *config = dev->config; + int ret; + + /* Select sleep state; it's OK if settings fails for any reason. */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP); + if (ret < 0) { + LOG_WRN("Could not apply MIPI DBI pins' sleep state"); + } + + /* Disable host controller to minimize power consumption. */ + da1469x_lcdc_set_status(false, false, 0); + + return 0; +} + +static int mipi_dbi_smartbond_pm_action(const struct device *dev, enum pm_device_action action) +{ + int ret = 0; + + switch (action) { + case PM_DEVICE_ACTION_SUSPEND: + (void)mipi_dbi_smartbond_suspend(dev); + +#if CONFIG_PM_DEVICE_RUNTIME && CONFIG_PM + da1469x_pd_release_nowait(MCU_PD_DOMAIN_SYS); +#endif + break; + case PM_DEVICE_ACTION_RESUME: + ret = mipi_dbi_smartbond_resume(dev); + +#if CONFIG_PM_DEVICE_RUNTIME && CONFIG_PM + /* + * If resume succeeded, prevent the system from entering the + * extended sleep state (Instead, use __WFI). If not, do not + * as users should not suspend the device and thus releasing + * PD_SYS. + */ + if (ret == 0) { + da1469x_pd_acquire_noconf(MCU_PD_DOMAIN_SYS); + } +#endif + break; + default: + return -ENOTSUP; + } + + return ret; +} +#endif + +static int mipi_dbi_smartbond_init(const struct device *dev) +{ + const struct mipi_dbi_smartbond_config *config = dev->config; + struct mipi_dbi_smartbond_data *data = dev->data; + int ret; + + /* Device should be ready to be acquired */ + k_sem_init(&data->device_sem, 1, 1); + /* Event should be signaled by LCDC ISR */ + k_sem_init(&data->sync_sem, 0, 1); + +#if MIPI_DBI_SMARTBOND_IS_RESET_AVAILABLE + if (gpio_is_ready_dt(&config->reset)) { + ret = gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT_INACTIVE); + if (ret < 0) { + LOG_ERR("Could not configure reset line (%d)", ret); + return -EIO; + } + } +#endif + + IRQ_CONNECT(SMARTBOND_IRQN, SMARTBOND_IRQ_PRIO, smartbond_mipi_dbi_isr, + DEVICE_DT_INST_GET(0), 0); + +#ifdef CONFIG_PM_DEVICE_RUNTIME + /* Make sure device state is marked as suspended */ + pm_device_init_suspended(dev); + + ret = pm_device_runtime_enable(dev); + if ((ret < 0) && (ret != -ENOSYS)) { + return ret; + } +#else + /* Resme if either PM is not used at all or if PM without runtime is used. */ + ret = mipi_dbi_smartbond_resume(dev); + if (ret < 0) { + return ret; + } +#endif + + return 0; +} + +static struct mipi_dbi_driver_api mipi_dbi_smartbond_driver_api = { +#if MIPI_DBI_SMARTBOND_IS_RESET_AVAILABLE + .reset = mipi_dbi_smartbond_reset, +#endif + .command_write = mipi_dbi_smartbond_command_write, + .write_display = mipi_dbi_smartbond_write_display, +#if MIPI_DBI_SMARTBOND_IS_READ_SUPPORTED + .command_read = mipi_dbi_smartbond_command_read, +#endif +}; + +#define SMARTBOND_MIPI_DBI_INIT(inst) \ + PINCTRL_DT_INST_DEFINE(inst); \ + \ + static const struct mipi_dbi_smartbond_config mipi_dbi_smartbond_config_## inst = { \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ + .reset = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, {}), \ + .timing_cfg = { 0 }, \ + .bgcolor_cfg = { 0xFF, 0xFF, 0xFF, 0 }, \ + }; \ + \ + static struct mipi_dbi_smartbond_data mipi_dbi_smartbond_data_## inst; \ + \ + PM_DEVICE_DT_INST_DEFINE(inst, mipi_dbi_smartbond_pm_action); \ + \ + DEVICE_DT_INST_DEFINE(inst, mipi_dbi_smartbond_init, \ + PM_DEVICE_DT_INST_GET(inst), \ + &mipi_dbi_smartbond_data_## inst, \ + &mipi_dbi_smartbond_config_## inst, \ + POST_KERNEL, \ + CONFIG_MIPI_DBI_INIT_PRIORITY, \ + &mipi_dbi_smartbond_driver_api); + +SMARTBOND_MIPI_DBI_INIT(0); diff --git a/dts/bindings/mipi-dbi/renesas,smartbond-mipi-dbi.yaml b/dts/bindings/mipi-dbi/renesas,smartbond-mipi-dbi.yaml new file mode 100644 index 00000000000..2bfd857732c --- /dev/null +++ b/dts/bindings/mipi-dbi/renesas,smartbond-mipi-dbi.yaml @@ -0,0 +1,54 @@ +# Copyright (c) 2023 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +include: [mipi-dbi-controller.yaml, pinctrl-device.yaml] + +description: Renesas Smartbond(tm) MIPI DBI Host + +compatible: "renesas,smartbond-mipi-dbi" + +properties: + reg: + required: true + + interrupts: + required: true + + reset-gpios: + type: phandle-array + description: | + Reset GPIO pin. Used to reset the display during initialization. + + te-enable: + type: boolean + description: | + Boolean to indicate whether the tearing effect (TE) signal is available or not. + + te-inversion: + type: boolean + description: | + Boolean to apply an inversion on the TE signal that triggers the MIPI DBI controller. + + dma-prefetch: + type: string + enum: + - "no-prefetch" + - "prefetch-44-bytes" + - "prefetch-84-bytes" + - "prefetch-116-bytes" + - "prefetch-108-bytes" + description: | + Host controller will wait for at least the specified number of bytes before triggering + a single frame update. The prefetch mechanism should be enabled when frame buffer(s) + is stored into external storage mediums, e.g. PSRAM, that introduce comparable delays. + In such a case it might case that the controller runs into underrun conditions which + results in correpting the whole frame update. It's user's responsibility to ensure that + the selected value does not exceed frame's total size as otherwise the controller will + not be able to trigger the frame update. + + spi-dev: + type: phandle + description: | + SPI bus to use for display read operations. When this property is present, MIPI DBI read + operations will be exhibited by the driver. This is because, the LCDC IP block does not + support read functionality, natively. From 2ad5c4c6a173a85e81793d49b4e6e74b5a332225 Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Tue, 5 Mar 2024 11:08:46 +0200 Subject: [PATCH 0200/2402] dts: renesas: smartbond: Add support for the MIPI DBI host controller. Update SoC DTS configurations to support the Renesas MIPI DBI host controller. Signed-off-by: Ioannis Karachalios --- dts/arm/renesas/smartbond/da1469x.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/dts/arm/renesas/smartbond/da1469x.dtsi b/dts/arm/renesas/smartbond/da1469x.dtsi index 72f7e6fa89f..d5a6340d74c 100644 --- a/dts/arm/renesas/smartbond/da1469x.dtsi +++ b/dts/arm/renesas/smartbond/da1469x.dtsi @@ -16,6 +16,10 @@ zephyr,flash-controller = &flash_controller; }; + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + }; + cpus: cpus { #address-cells = <1>; #size-cells = <0>; @@ -300,6 +304,15 @@ status = "okay"; }; + mipi_dbi: lcdc@30030000 { + compatible = "renesas,smartbond-mipi-dbi"; + reg = <0x30030000 0x18C>; + interrupts = <32 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c: i2c@50020600 { compatible = "renesas,smartbond-i2c"; #address-cells = <1>; From 867650a2159e3d423d61ea35cf6e1f70396c4fa0 Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Tue, 5 Mar 2024 11:25:51 +0200 Subject: [PATCH 0201/2402] boards: renesas: smartbond: Re-assign default peripherals pins Re-assign peripherals' default pins functionality to avoid conflicts with LCD controller's pins usage. The PRO DevKit exhibits a display socket which is routed to dedicated pins. Signed-off-by: Ioannis Karachalios --- .../renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi index 7a92cc56f9b..7075bbef5df 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi @@ -26,20 +26,20 @@ i2c2_default: i2c2_default { group1 { - pinmux = , - ; + pinmux = , + ; bias-pull-up; }; }; spi_controller: spi_controller { group1 { - pinmux = < SMARTBOND_PINMUX(SPI_CLK, 0, 21) >, - ; + pinmux = , + ; output-enable; }; group2 { - pinmux = ; + pinmux = ; input-enable; }; }; From 56700518051f26cb46642694d1d51ca79760977c Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Thu, 23 Nov 2023 13:09:18 +0200 Subject: [PATCH 0202/2402] boards: renesas: smartbond: Add support for the MIPI DBI host driver Update board's DTS configurations to support the Renesas MIPI DBI host controller. Signed-off-by: Ioannis Karachalios --- .../renesas/da1469x_dk_pro/Kconfig.defconfig | 19 ++++++++- .../da1469x_dk_pro-pinctrl.dtsi | 39 +++++++++++++++++++ .../renesas/da1469x_dk_pro/da1469x_dk_pro.dts | 7 ++++ .../da1469x_dk_pro/da1469x_dk_pro.yaml | 1 + 4 files changed, 65 insertions(+), 1 deletion(-) diff --git a/boards/renesas/da1469x_dk_pro/Kconfig.defconfig b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig index ca6a91cea95..90e48078674 100644 --- a/boards/renesas/da1469x_dk_pro/Kconfig.defconfig +++ b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig @@ -5,8 +5,25 @@ if BOARD_DA1469X_DK_PRO +if LVGL + +config LV_Z_BITS_PER_PIXEL + default 16 + +# LCDC imposes display buffer's stride be word aligned config LV_Z_AREA_X_ALIGNMENT_WIDTH default 2 - depends on LVGL + +endif # LVGL + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +config LV_Z_POINTER_INPUT_MSGQ_COUNT + default 70 + +endif # INPUT endif # BOARD_DA1469X_DK_PRO diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi index 7075bbef5df..7fe5111302d 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi @@ -55,4 +55,43 @@ input-enable; }; }; + + /omit-if-no-ref/ mipi_dbi_default: mipi_dbi_default { + group1 { + pinmux = , + , + , + ; + }; + group2 { + /* TE signal - mapped on fixed positions */ + pinmux = ; + }; + }; + + /omit-if-no-ref/ mipi_dbi_sleep: mipi_dbi_sleep { + group1 { + pinmux = , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + /* Same signal can be multiplexed to multiple I/O pins */ + /omit-if-no-ref/ mipi_dbi_read: mipi_dbi_read { + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; }; diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts index deeb86e33e2..826703c7c87 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts @@ -168,3 +168,10 @@ zephyr_udc0: &usbd { pinctrl-0 = <&spi2_controller>; pinctrl-names = "default"; }; + +&mipi_dbi { + pinctrl-0 = <&mipi_dbi_default>; + pinctrl-1 = <&mipi_dbi_read>; + pinctrl-2 = <&mipi_dbi_sleep>; + pinctrl-names = "default", "read", "sleep"; +}; diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml index 4d35304c622..631615c6ffe 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml @@ -19,4 +19,5 @@ supported: - rtc - crypto - dma + - mipi_dbi vendor: renesas From c2b809dacd113df4e88c6e09d2fdbca8932c6e1a Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Thu, 23 Nov 2023 13:13:17 +0200 Subject: [PATCH 0203/2402] samples: drivers: display: Add support for Smartbond Pro DevKit. Add overlay file to support the pro devkit. To build the sample code, one should explicitly select the overlay file at 'west build' invokation via the DTC_OVERLAY_FILE system variable. Signed-off-by: Ioannis Karachalios --- .../boards/da1469x_dk_pro_mipi_dbi.overlay | 31 +++++++++++++++++++ samples/drivers/display/sample.yaml | 10 ++++++ 2 files changed, 41 insertions(+) create mode 100644 samples/drivers/display/boards/da1469x_dk_pro_mipi_dbi.overlay diff --git a/samples/drivers/display/boards/da1469x_dk_pro_mipi_dbi.overlay b/samples/drivers/display/boards/da1469x_dk_pro_mipi_dbi.overlay new file mode 100644 index 00000000000..81a4bdd8645 --- /dev/null +++ b/samples/drivers/display/boards/da1469x_dk_pro_mipi_dbi.overlay @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2023 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + + #include + #include + + / { + chosen { + zephyr,display = &ili9340; + }; + }; + + &mipi_dbi { + reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + status = "okay"; + spi-dev = <&spi2>; + + ili9340: ili9340@0 { + compatible = "ilitek,ili9340"; + mipi-max-frequency = <48000000>; + status = "okay"; + reg = <0>; + width = <240>; + height = <320>; + pixel-format = ; + rotation = <0>; + }; +}; diff --git a/samples/drivers/display/sample.yaml b/samples/drivers/display/sample.yaml index e1d938eda05..2b834dab0f6 100644 --- a/samples/drivers/display/sample.yaml +++ b/samples/drivers/display/sample.yaml @@ -107,6 +107,16 @@ tests: - native_posix_64 - native_sim_64 tags: display + sample.display.mipi_dbi: + platform_allow: + - da1469x_dk_pro + extra_args: DTC_OVERLAY_FILE="boards/da1469x_dk_pro_mipi_dbi.overlay" + tags: + - display + - mipi_dbi + harness: console + harness_config: + fixture: fixture_display sample.display.dummy: platform_allow: - native_posix From 9b88dba65c6a89595be8cf1612c60247826966f9 Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Wed, 31 Jan 2024 16:35:08 +0200 Subject: [PATCH 0204/2402] samples: modules: lvgl: Add support for Smartbond Pro DevKit. Add overlay file to support the pro devkit. To build the sample code, one should explicitly select the overlay file at 'west build' invokation via the DTC_OVERLAY_FILE system variable. Signed-off-by: Ioannis Karachalios --- .../boards/da1469x_dk_pro_mipi_dbi.overlay | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 samples/modules/lvgl/demos/boards/da1469x_dk_pro_mipi_dbi.overlay diff --git a/samples/modules/lvgl/demos/boards/da1469x_dk_pro_mipi_dbi.overlay b/samples/modules/lvgl/demos/boards/da1469x_dk_pro_mipi_dbi.overlay new file mode 100644 index 00000000000..adf3a174c74 --- /dev/null +++ b/samples/modules/lvgl/demos/boards/da1469x_dk_pro_mipi_dbi.overlay @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + + #include + #include + +/ { + chosen { + zephyr,display = &ili9340; + }; + + lvgl_pointer { + input = <&display_touch>; + status = "okay"; + swap-xy; + invert-x; + invert-y; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + + display_touch: ft6206@38 { + compatible = "focaltech,ft5336"; + status = "okay"; + reg = <0x38>; + int-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; +}; + +&mipi_dbi { + reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + status = "okay"; + spi-dev = <&spi2>; + + ili9340: ili9340@0 { + compatible = "ilitek,ili9340"; + mipi-max-frequency = <48000000>; + status = "okay"; + reg = <0>; + width = <240>; + height = <320>; + pixel-format = ; + rotation = <0>; + }; +}; From 63274784291d6e7d039d4659b5ccc28e72a12cf3 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 27 Feb 2024 00:34:33 +0530 Subject: [PATCH 0205/2402] net: lib: Add debug for sockets total and owner This helps in figuring out the need for the number of sockets. Signed-off-by: Chaitanya Tata --- subsys/net/lib/sockets/sockets_service.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/subsys/net/lib/sockets/sockets_service.c b/subsys/net/lib/sockets/sockets_service.c index 89b653d31e5..1719a380d1f 100644 --- a/subsys/net/lib/sockets/sockets_service.c +++ b/subsys/net/lib/sockets/sockets_service.c @@ -190,6 +190,10 @@ static void socket_service_thread(void) /* Create contiguous poll event array to enable socket polling */ STRUCT_SECTION_FOREACH(net_socket_service_desc, svc) { + NET_DBG("Service %s has %d pollable sockets", + COND_CODE_1(CONFIG_NET_SOCKETS_LOG_LEVEL_DBG, + (svc->owner), ("")), + svc->pev_len); get_idx(svc) = count + 1; count += svc->pev_len; } From 6af7ad5a52996d79ce9439d3f1486a800bfded69 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Anders=20Storr=C3=B8?= Date: Wed, 28 Feb 2024 14:38:12 +0100 Subject: [PATCH 0206/2402] Bluetooth: Mesh: Prevent duplicate cdb appkeys MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes issue where it is possible to store the same appkey multiple times in CDB implementation. Signed-off-by: Anders Storrø --- include/zephyr/bluetooth/mesh/cdb.h | 6 ++++-- subsys/bluetooth/mesh/cdb.c | 22 +++++++++++++++------- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/include/zephyr/bluetooth/mesh/cdb.h b/include/zephyr/bluetooth/mesh/cdb.h index 8ea35ec2e55..9b7fbf4af79 100644 --- a/include/zephyr/bluetooth/mesh/cdb.h +++ b/include/zephyr/bluetooth/mesh/cdb.h @@ -249,7 +249,8 @@ void bt_mesh_cdb_node_foreach(bt_mesh_cdb_node_func_t func, void *user_data); * * @param net_idx NetIdx of the subnet. * - * @return The new subnet or NULL if it cannot be allocated. + * @return The new subnet or NULL if it cannot be allocated due to + * lack of resources or the subnet has been already allocated. */ struct bt_mesh_cdb_subnet *bt_mesh_cdb_subnet_alloc(uint16_t net_idx); @@ -328,7 +329,8 @@ int bt_mesh_cdb_subnet_key_export(const struct bt_mesh_cdb_subnet *sub, int key_ * @param net_idx NetIdx of NetKey that the application key is bound to. * @param app_idx AppIdx of the application key. * - * @return The new application key or NULL if it cannot be allocated. + * @return The new application key or NULL if it cannot be allocated due to + * lack of resources or the key has been already allocated. */ struct bt_mesh_cdb_app_key *bt_mesh_cdb_app_key_alloc(uint16_t net_idx, uint16_t app_idx); diff --git a/subsys/bluetooth/mesh/cdb.c b/subsys/bluetooth/mesh/cdb.c index 2735c269798..33c9601807c 100644 --- a/subsys/bluetooth/mesh/cdb.c +++ b/subsys/bluetooth/mesh/cdb.c @@ -94,6 +94,7 @@ struct bt_mesh_cdb bt_mesh_cdb = { }, .app_keys = { [0 ... (CONFIG_BT_MESH_CDB_APP_KEY_COUNT - 1)] = { + .app_idx = BT_MESH_KEY_UNUSED, .net_idx = BT_MESH_KEY_UNUSED, } }, @@ -1024,26 +1025,32 @@ int bt_mesh_cdb_node_key_export(const struct bt_mesh_cdb_node *node, uint8_t out return bt_mesh_key_export(out, &node->dev_key); } -struct bt_mesh_cdb_app_key *bt_mesh_cdb_app_key_alloc(uint16_t net_idx, - uint16_t app_idx) +struct bt_mesh_cdb_app_key *bt_mesh_cdb_app_key_alloc(uint16_t net_idx, uint16_t app_idx) { struct bt_mesh_cdb_app_key *key; + struct bt_mesh_cdb_app_key *vacant_key = NULL; int i; for (i = 0; i < ARRAY_SIZE(bt_mesh_cdb.app_keys); ++i) { key = &bt_mesh_cdb.app_keys[i]; - if (key->net_idx != BT_MESH_KEY_UNUSED) { + if (key->app_idx == app_idx) { + return NULL; + } + + if (key->net_idx != BT_MESH_KEY_UNUSED || vacant_key) { continue; } - key->net_idx = net_idx; - key->app_idx = app_idx; + vacant_key = key; + } - return key; + if (vacant_key) { + vacant_key->net_idx = net_idx; + vacant_key->app_idx = app_idx; } - return NULL; + return vacant_key; } void bt_mesh_cdb_app_key_del(struct bt_mesh_cdb_app_key *key, bool store) @@ -1055,6 +1062,7 @@ void bt_mesh_cdb_app_key_del(struct bt_mesh_cdb_app_key *key, bool store) } key->net_idx = BT_MESH_KEY_UNUSED; + key->app_idx = BT_MESH_KEY_UNUSED; bt_mesh_key_destroy(&key->keys[0].app_key); bt_mesh_key_destroy(&key->keys[1].app_key); memset(key->keys, 0, sizeof(key->keys)); From 4c031e23068f82f2476770b0c811e5a9ca01de17 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 1 Mar 2024 10:43:41 -0800 Subject: [PATCH 0207/2402] x86: prefix x86 SSBD and IBRS related kconfigs with X86 There are two kconfigs that are security related and are x86 specific. Prefix them with X86 to put them under the x86 namespace. Signed-off-by: Daniel Leung --- arch/x86/Kconfig | 22 ++++++++++++++++++++-- arch/x86/core/spec_ctrl.c | 8 ++++---- doc/releases/migration-guide-3.7.rst | 6 ++++++ 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index ae7fdef2f77..1c58de4b908 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -397,7 +397,7 @@ config X86_NO_SPECULATIVE_VULNERABILITIES or is a newer chip which is immune to the class of vulnerabilities which exploit speculative execution side channel attacks. -config DISABLE_SSBD +config X86_DISABLE_SSBD bool "Disable Speculative Store Bypass" depends on USERSPACE default y if !X86_NO_SPECTRE_V4 @@ -417,7 +417,16 @@ config DISABLE_SSBD Even if enabled, will have no effect on CPUs that do not require this feature. -config ENABLE_EXTENDED_IBRS +config DISABLE_SSBD + bool "Disable Speculative Store Bypass [DEPRECATED]" + depends on USERSPACE + default y if !X86_NO_SPECTRE_V4 + select X86_DISABLE_SSBD + select DEPRECATED + help + Deprecated. Use CONFIG_X86_DISABLE_SSBD instead. + +config X86_ENABLE_EXTENDED_IBRS bool "Extended IBRS" depends on USERSPACE default y if !X86_NO_SPECTRE_V2 @@ -426,6 +435,15 @@ config ENABLE_EXTENDED_IBRS Speculation 'always on' feature. This mitigates Indirect Branch Control vulnerabilities (aka Spectre V2). +config ENABLE_EXTENDED_IBRS + bool "Extended IBRS [DEPRECATED]" + depends on USERSPACE + default y if !X86_NO_SPECTRE_V2 + select X86_ENABLE_EXTENDED_IBRS + select DEPRECATED + help + Deprecated. Use CONFIG_X86_ENABLE_EXTENDED_IBRS instead. + config X86_BOUNDS_CHECK_BYPASS_MITIGATION bool depends on USERSPACE diff --git a/arch/x86/core/spec_ctrl.c b/arch/x86/core/spec_ctrl.c index feb6616250e..50daa74bd1a 100644 --- a/arch/x86/core/spec_ctrl.c +++ b/arch/x86/core/spec_ctrl.c @@ -16,19 +16,19 @@ * https://software.intel.com/security-software-guidance/api-app/sites/default/files/336996-Speculative-Execution-Side-Channel-Mitigations.pdf */ -#if defined(CONFIG_DISABLE_SSBD) || defined(CONFIG_ENABLE_EXTENDED_IBRS) +#if defined(CONFIG_X86_DISABLE_SSBD) || defined(CONFIG_X86_ENABLE_EXTENDED_IBRS) static int spec_ctrl_init(void) { uint32_t enable_bits = 0U; uint32_t cpuid7 = z_x86_cpuid_extended_features(); -#ifdef CONFIG_DISABLE_SSBD +#ifdef CONFIG_X86_DISABLE_SSBD if ((cpuid7 & CPUID_SPEC_CTRL_SSBD) != 0U) { enable_bits |= X86_SPEC_CTRL_MSR_SSBD; } #endif -#ifdef CONFIG_ENABLE_EXTENDED_IBRS +#ifdef CONFIG_X86_ENABLE_EXTENDED_IBRS if ((cpuid7 & CPUID_SPEC_CTRL_IBRS) != 0U) { enable_bits |= X86_SPEC_CTRL_MSR_IBRS; } @@ -44,4 +44,4 @@ static int spec_ctrl_init(void) } SYS_INIT(spec_ctrl_init, PRE_KERNEL_1, 0); -#endif /* CONFIG_DISABLE_SSBD || CONFIG_ENABLE_EXTENDED_IBRS */ +#endif /* CONFIG_X86_DISABLE_SSBD || CONFIG_X86_ENABLE_EXTENDED_IBRS */ diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index c73d06bfdb7..d318a2eab1e 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -142,5 +142,11 @@ Userspace Architectures ************* +* x86 + + * Kconfigs ``CONFIG_DISABLE_SSBD`` and ``CONFIG_ENABLE_EXTENDED_IBRS`` + are deprecated. Use :kconfig:option:`CONFIG_X86_DISABLE_SSBD` and + :kconfig:option:`CONFIG_X86_ENABLE_EXTENDED_IBRS` instead. + Xtensa ====== From 0483d68334ce5d62558e8a5b87149ae8379a463b Mon Sep 17 00:00:00 2001 From: Omkar Kulkarni Date: Sun, 3 Mar 2024 21:27:29 +0100 Subject: [PATCH 0208/2402] Bluetooth: Mesh: Add missing model extensions DFD Server, DFU Server, and DFU Client models are extended models that extend other underlaying models. If BT_MESH_MODEL_EXTENSIONS is not enabled, extension hierarchy is not initialized and this results in issues in subscriptions and errors in representation of hierarchy in CDP1. Since extensions are spec defined, force selection of this option here to prevent users forgetting about it. Signed-off-by: Omkar Kulkarni --- subsys/bluetooth/mesh/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/subsys/bluetooth/mesh/Kconfig b/subsys/bluetooth/mesh/Kconfig index 085d72c3b18..b7590b8790e 100644 --- a/subsys/bluetooth/mesh/Kconfig +++ b/subsys/bluetooth/mesh/Kconfig @@ -945,12 +945,14 @@ config BT_MESH_BLOB_IO_FLASH config BT_MESH_DFU_SRV bool "Support for Firmware Update Server model" + depends on BT_MESH_MODEL_EXTENSIONS depends on BT_MESH_BLOB_SRV help Enable the Firmware Update Server model. config BT_MESH_DFU_CLI bool "Support for Firmware Update Client model" + depends on BT_MESH_MODEL_EXTENSIONS depends on BT_MESH_BLOB_CLI help Enable the Firmware Update Client model. From 6bcf73ff14123fc79ccde27d3dedbefcd5168a88 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Wed, 6 Mar 2024 06:30:36 +0900 Subject: [PATCH 0209/2402] boards: espressif: esp32s3_devkitm: Correct filename typo boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_.yaml has needless `_` in filename. Renamed it. Signed-off-by: TOKITA Hiroshi --- ...m_esp32s3_procpu_.yaml => esp32s3_devkitm_esp32s3_procpu.yaml} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename boards/espressif/esp32s3_devkitm/{esp32s3_devkitm_esp32s3_procpu_.yaml => esp32s3_devkitm_esp32s3_procpu.yaml} (100%) diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_.yaml b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu.yaml similarity index 100% rename from boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_.yaml rename to boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu.yaml From 1a94b0ab24c095ba1fbb391411e54e1f937c69ce Mon Sep 17 00:00:00 2001 From: Martin Kiepfer Date: Sun, 7 Jan 2024 16:42:04 +0100 Subject: [PATCH 0210/2402] drivers: regulator: axp192: Bugfix to control DCDC2 output Fix wrong definition of DCDC2 register values. Signed-off-by: Martin Kiepfer --- drivers/regulator/regulator_axp192.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/regulator/regulator_axp192.c b/drivers/regulator/regulator_axp192.c index 56f46cca0db..7edabe9e43a 100644 --- a/drivers/regulator/regulator_axp192.c +++ b/drivers/regulator/regulator_axp192.c @@ -84,9 +84,9 @@ static const struct linear_range dcdc2_ranges[] = { }; static const struct regulator_axp192_desc dcdc2_desc = { - .enable_reg = AXP192_REG_DCDC123_LDO23_CONTROL, - .enable_mask = 0x10U, - .enable_val = 0x10U, + .enable_reg = AXP192_REG_EXTEN_DCDC2_CONTROL, + .enable_mask = 0x01U, + .enable_val = 0x01U, .vsel_reg = AXP192_REG_DCDC2_VOLTAGE, .vsel_mask = 0x3FU, .vsel_bitpos = 0U, From 2a83c5802364b066dd0d55c941c4a381d5ba35cf Mon Sep 17 00:00:00 2001 From: Martin Kiepfer Date: Sun, 7 Jan 2024 16:34:52 +0100 Subject: [PATCH 0211/2402] drivers: gpio: axp192: Add support to control EXTEN pin AXP192 features an EXTEN pin that is on output only. This commit appends control of EXTEN pin to gpio functionality of AXP192. Port-Mapping is as follows: - [0..4]: GPIO0..4 - [5]: EXTEN Signed-off-by: Martin Kiepfer --- drivers/gpio/gpio_axp192.c | 3 +- drivers/mfd/mfd_axp192.c | 99 +++++++++++++++------ dts/bindings/gpio/x-powers,axp192-gpio.yaml | 15 +++- include/zephyr/drivers/mfd/axp192.h | 20 ++++- tests/drivers/build_all/gpio/app.overlay | 2 +- 5 files changed, 102 insertions(+), 37 deletions(-) diff --git a/drivers/gpio/gpio_axp192.c b/drivers/gpio/gpio_axp192.c index cf594c25aba..5b1b41c758c 100644 --- a/drivers/gpio/gpio_axp192.c +++ b/drivers/gpio/gpio_axp192.c @@ -75,8 +75,7 @@ static int gpio_axp192_port_clear_bits_raw(const struct device *dev, gpio_port_p return gpio_axp192_port_set_masked_raw(dev, pins, 0); } -static int gpio_axp192_configure(const struct device *dev, gpio_pin_t pin, - gpio_flags_t flags) +static int gpio_axp192_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) { const struct gpio_axp192_config *config = dev->config; int ret; diff --git a/drivers/mfd/mfd_axp192.c b/drivers/mfd/mfd_axp192.c index dc2da09f823..1286a2ba319 100644 --- a/drivers/mfd/mfd_axp192.c +++ b/drivers/mfd/mfd_axp192.c @@ -22,13 +22,14 @@ LOG_MODULE_REGISTER(mfd_axp192, CONFIG_MFD_LOG_LEVEL); #define AXP192_REG_CHIP_ID 0x03U /* AXP192 GPIO register addresses */ -#define AXP192_GPIO0_REG_FUNC 0x90U -#define AXP192_GPIO1_REG_FUNC 0x92U -#define AXP192_GPIO2_REG_FUNC 0x93U -#define AXP192_GPIO34_REG_FUNC 0x95U -#define AXP192_GPIO012_REG_PINVAL 0x94U -#define AXP192_GPIO34_REG_PINVAL 0x96U -#define AXP192_GPIO012_REG_PULLDOWN 0x97U +#define AXP192_VBUS_CFG_REG 0x30U +#define AXP192_GPIO0_FUNC_REG 0x90U +#define AXP192_GPIO1_FUNC_REG 0x92U +#define AXP192_GPIO2_FUNC_REG 0x93U +#define AXP192_GPIO34_FUNC_REG 0x95U +#define AXP192_GPIO012_PINVAL_REG 0x94U +#define AXP192_GPIO34_PINVAL_REG 0x96U +#define AXP192_GPIO012_PULLDOWN_REG 0x97U /* GPIO function control parameters */ #define AXP192_GPIO012_FUNC_VAL_OUTPUT_OD 0x00U @@ -58,6 +59,9 @@ LOG_MODULE_REGISTER(mfd_axp192, CONFIG_MFD_LOG_LEVEL); (AXP192_GPIO34_FUNC_ENA | AXP192_GPIO4_FUNC_VAL_CHARGE_CTL | \ AXP192_GPIO4_FUNC_VAL_OUTPUT_OD | AXP192_GPIO4_FUNC_VAL_INPUT) +#define AXP192_EXTEN_ENA 0x04U +#define AXP192_EXTEN_MASK 0x04U + /* Pull-Down enable parameters */ #define AXP192_GPIO0_PULLDOWN_ENABLE 0x01U #define AXP192_GPIO1_PULLDOWN_ENABLE 0x02U @@ -84,6 +88,9 @@ LOG_MODULE_REGISTER(mfd_axp192, CONFIG_MFD_LOG_LEVEL); #define AXP192_GPIO4_OUTPUT_VAL 0x02U #define AXP192_GPIO34_OUTPUT_MASK (AXP192_GPIO3_OUTPUT_VAL | AXP192_GPIO4_OUTPUT_VAL) +#define AXP192_GPIO5_OUTPUT_MASK 0x04U +#define AXP192_GPIO5_OUTPUT_VAL 0x04U +#define AXP192_GPIO5_OUTPUT_SHIFT 3U struct mfd_axp192_config { struct i2c_dt_spec i2c; }; @@ -101,27 +108,27 @@ struct mfd_axp192_func_reg_desc { const struct mfd_axp192_func_reg_desc gpio_reg_desc[AXP192_GPIO_MAX_NUM] = { { /* GPIO0 */ - .reg = AXP192_GPIO0_REG_FUNC, + .reg = AXP192_GPIO0_FUNC_REG, .mask = AXP192_GPIO012_FUNC_MASK, }, { /* GPIO1 */ - .reg = AXP192_GPIO1_REG_FUNC, + .reg = AXP192_GPIO1_FUNC_REG, .mask = AXP192_GPIO012_FUNC_MASK, }, { /* GPIO2 */ - .reg = AXP192_GPIO2_REG_FUNC, + .reg = AXP192_GPIO2_FUNC_REG, .mask = AXP192_GPIO012_FUNC_MASK, }, { /* GPIO3 */ - .reg = AXP192_GPIO34_REG_FUNC, + .reg = AXP192_GPIO34_FUNC_REG, .mask = AXP192_GPIO3_FUNC_MASK, }, { /* GPIO4 */ - .reg = AXP192_GPIO34_REG_FUNC, + .reg = AXP192_GPIO34_FUNC_REG, .mask = AXP192_GPIO4_FUNC_MASK, }, }; @@ -144,7 +151,6 @@ static int mfd_axp192_init(const struct device *dev) if (ret < 0) { return ret; } - if (chip_id != AXP192_CHIP_ID) { LOG_ERR("Invalid Chip detected (%d)", chip_id); return -EINVAL; @@ -164,9 +170,11 @@ int mfd_axp192_gpio_func_get(const struct device *dev, uint8_t gpio, enum axp192 return -EINVAL; } - ret = i2c_reg_read_byte_dt(&(config->i2c), gpio_reg_desc[gpio].reg, ®_fnc); - if (ret != 0) { - return ret; + if (gpio < ARRAY_SIZE(gpio_reg_desc)) { + ret = i2c_reg_read_byte_dt(&(config->i2c), gpio_reg_desc[gpio].reg, ®_fnc); + if (ret != 0) { + return ret; + } } switch (gpio) { @@ -245,6 +253,11 @@ int mfd_axp192_gpio_func_get(const struct device *dev, uint8_t gpio, enum axp192 } break; + case 5U: + /* EXTEN is an output only pin */ + *func = AXP192_GPIO_FUNC_OUTPUT_LOW; + break; + default: ret = -EINVAL; } @@ -259,7 +272,7 @@ int mfd_axp192_gpio_func_ctrl(const struct device *dev, const struct device *cli struct mfd_axp192_data *data = dev->data; bool is_output = false; int ret = 0; - uint8_t reg_cfg; + uint8_t reg_cfg = 0; if (!AXP192_GPIO_FUNC_VALID(func)) { LOG_ERR("Invalid function"); @@ -355,18 +368,25 @@ int mfd_axp192_gpio_func_ctrl(const struct device *dev, const struct device *cli } break; + case 5U: + /* EXTEN is an output only pin */ + break; + default: ret = -EINVAL; } + if (ret != 0) { LOG_ERR("Invalid function (0x%x) for gpio %d", func, gpio); return ret; } - ret = i2c_reg_update_byte_dt(&(config->i2c), gpio_reg_desc[gpio].reg, - gpio_reg_desc[gpio].mask, reg_cfg); - if (ret != 0) { - return ret; + if (gpio < ARRAY_SIZE(gpio_reg_desc)) { + ret = i2c_reg_update_byte_dt(&(config->i2c), gpio_reg_desc[gpio].reg, + gpio_reg_desc[gpio].mask, reg_cfg); + if (ret != 0) { + return ret; + } } /* Save gpio configuration state */ @@ -412,7 +432,7 @@ int mfd_axp192_gpio_pd_get(const struct device *dev, uint8_t gpio, bool *enabled return -EINVAL; } - ret = i2c_reg_read_byte_dt(&(config->i2c), AXP192_GPIO012_REG_PULLDOWN, &gpio_val); + ret = i2c_reg_read_byte_dt(&(config->i2c), AXP192_GPIO012_PULLDOWN_REG, &gpio_val); if (ret == 0) { *enabled = ((gpio_val & pd_reg_mask) != 0); @@ -465,7 +485,7 @@ int mfd_axp192_gpio_pd_ctrl(const struct device *dev, uint8_t gpio, bool enable) return -EINVAL; } - ret = i2c_reg_update_byte_dt(&(config->i2c), AXP192_GPIO012_REG_PULLDOWN, reg_pd_mask, + ret = i2c_reg_update_byte_dt(&(config->i2c), AXP192_GPIO012_PULLDOWN_REG, reg_pd_mask, reg_pd_val); return ret; @@ -478,22 +498,31 @@ int mfd_axp192_gpio_read_port(const struct device *dev, uint8_t *value) int ret; uint8_t gpio012_val; uint8_t gpio34_val; + uint8_t gpio5_val; uint8_t gpio_input_val; uint8_t gpio_output_val; /* read gpio0-2 */ - ret = i2c_reg_read_byte_dt(&(config->i2c), AXP192_GPIO012_REG_PINVAL, &gpio012_val); + ret = i2c_reg_read_byte_dt(&(config->i2c), AXP192_GPIO012_PINVAL_REG, &gpio012_val); if (ret != 0) { return ret; } /* read gpio3-4 */ - ret = i2c_reg_read_byte_dt(&(config->i2c), AXP192_GPIO34_REG_PINVAL, &gpio34_val); + ret = i2c_reg_read_byte_dt(&(config->i2c), AXP192_GPIO34_PINVAL_REG, &gpio34_val); + if (ret != 0) { + return ret; + } + + /* read gpio5 */ + ret = i2c_reg_read_byte_dt(&(config->i2c), AXP192_EXTEN_DCDC2_CONTROL_REG, &gpio5_val); if (ret != 0) { return ret; } + LOG_DBG("GPIO012 pinval-reg=0x%x", gpio012_val); LOG_DBG("GPIO34 pinval-reg =0x%x", gpio34_val); + LOG_DBG("GPIO5 pinval-reg =0x%x", gpio5_val); LOG_DBG("Output-Mask =0x%x", data->gpio_mask_output); gpio_input_val = @@ -503,6 +532,8 @@ int mfd_axp192_gpio_read_port(const struct device *dev, uint8_t *value) gpio_output_val = (gpio012_val & AXP192_GPIO012_OUTPUT_MASK); gpio_output_val |= ((gpio34_val & AXP192_GPIO34_OUTPUT_MASK) << 3u); + gpio_output_val |= + (((gpio5_val & AXP192_GPIO5_OUTPUT_MASK) >> AXP192_GPIO5_OUTPUT_SHIFT) << 5u); *value = gpio_input_val & ~(data->gpio_mask_output); *value |= (gpio_output_val & data->gpio_mask_output); @@ -519,9 +550,9 @@ int mfd_axp192_gpio_write_port(const struct device *dev, uint8_t value, uint8_t /* Write gpio0-2. Mask out other port pins */ gpio_reg_val = (value & AXP192_GPIO012_OUTPUT_MASK); - gpio_reg_mask = mask & AXP192_GPIO012_OUTPUT_MASK; + gpio_reg_mask = (mask & AXP192_GPIO012_OUTPUT_MASK); if (gpio_reg_mask != 0) { - ret = i2c_reg_update_byte_dt(&(config->i2c), AXP192_GPIO012_REG_PINVAL, + ret = i2c_reg_update_byte_dt(&(config->i2c), AXP192_GPIO012_PINVAL_REG, gpio_reg_mask, gpio_reg_val); if (ret != 0) { return ret; @@ -533,7 +564,7 @@ int mfd_axp192_gpio_write_port(const struct device *dev, uint8_t value, uint8_t gpio_reg_val = value >> 3U; gpio_reg_mask = (mask >> 3U) & AXP192_GPIO34_OUTPUT_MASK; if (gpio_reg_mask != 0) { - ret = i2c_reg_update_byte_dt(&(config->i2c), AXP192_GPIO34_REG_PINVAL, + ret = i2c_reg_update_byte_dt(&(config->i2c), AXP192_GPIO34_PINVAL_REG, gpio_reg_mask, gpio_reg_val); if (ret != 0) { return ret; @@ -541,6 +572,18 @@ int mfd_axp192_gpio_write_port(const struct device *dev, uint8_t value, uint8_t LOG_DBG("GPIO34 pinval-reg =0x%x mask=0x%x", gpio_reg_val, gpio_reg_mask); } + /* Write gpio5. Mask out other port pins */ + if ((mask & BIT(5)) != 0) { + gpio_reg_mask = AXP192_EXTEN_MASK; + gpio_reg_val = (value & BIT(5)) ? AXP192_EXTEN_ENA : 0U; + ret = i2c_reg_update_byte_dt(&(config->i2c), AXP192_EXTEN_DCDC2_CONTROL_REG, + gpio_reg_mask, gpio_reg_val); + if (ret != 0) { + return ret; + } + LOG_DBG("GPIO5 pinval-reg =0x%x mask=0x%x\n", gpio_reg_val, gpio_reg_mask); + } + return 0; } diff --git a/dts/bindings/gpio/x-powers,axp192-gpio.yaml b/dts/bindings/gpio/x-powers,axp192-gpio.yaml index 4231777d6e3..5a56f60c121 100644 --- a/dts/bindings/gpio/x-powers,axp192-gpio.yaml +++ b/dts/bindings/gpio/x-powers,axp192-gpio.yaml @@ -1,7 +1,18 @@ # Copyright (c) 2023 Martin Kiepfer # SPDX-License-Identifier: Apache-2.0 -description: PXA192 GPIO Controller +description: AXP192 GPIO Controller + + AX192 features 5 native GPIOs. In addition the EXTEN pin can be configured + to be used as an IO as well. + + Pin-Mapping is as follows + [0] GPIO0 + [1] GPIO1 + [2] GPIO2 + [3] GPIO3 + [4] GPIO4 + [5] EXTEN compatible: "x-powers,axp192-gpio" @@ -13,7 +24,7 @@ properties: ngpios: required: true - const: 5 + const: 6 description: | Number of GPIOs available on axp192. diff --git a/include/zephyr/drivers/mfd/axp192.h b/include/zephyr/drivers/mfd/axp192.h index bdbd9025dfa..39ef899dc1d 100644 --- a/include/zephyr/drivers/mfd/axp192.h +++ b/include/zephyr/drivers/mfd/axp192.h @@ -40,23 +40,35 @@ enum axp192_gpio_func { /** * @brief Maximum number of GPIOs supported by AXP192 PMIC. */ -#define AXP192_GPIO_MAX_NUM 5U +#define AXP192_GPIO_MAX_NUM 6U /** * @defgroup mdf_interface_axp192 MFD AXP192 interface + * + * Pins of AXP192 support several different functions. The mfd interface offers + * an API to configure and control these different functions. + * + * The 6 GPIOS are mapped as follows: + * [0]: GPIO0 + * [1]: GPIO1 + * [2]: GPIO2 + * [3]: GPIO3 + * [4]: GPIO4 + * [5]: EXTEN + * * @ingroup mfd_interfaces * @{ */ /** - * @brief Request a GPIO pin to be configured to a specific function. GPIO0..4 + * @brief Request a GPIO pin to be configured to a specific function. GPIO0..5 * of AXP192 feature various functions (see @ref axp192_gpio_func for details). * A GPIO can only be used by one driver instance. Subsequential calls on the * same GPIO will overwrite according function. * * @param dev axp192 mfd device * @param client_dev client device the gpio is used in - * @param gpio GPIO to be configured (0..4) + * @param gpio GPIO to be configured (0..5) * @param func Function to be configured (see @ref axp192_gpio_func for details) * @retval 0 on success * @retval -EINVAL if an invalid GPIO number is passed @@ -80,7 +92,7 @@ int mfd_axp192_gpio_func_get(const struct device *dev, uint8_t gpio, enum axp192 /** * @brief Enable pull-down on specified GPIO pin. AXP192 only supports - * pull-down on GPIO3..4. Pull-ups are not supprted. + * pull-down on GPIO3..5. Pull-ups are not supprted. * * @param dev axp192 mfd device * @param gpio GPIO to control pull-downs diff --git a/tests/drivers/build_all/gpio/app.overlay b/tests/drivers/build_all/gpio/app.overlay index aa6ced36c04..d7de308b2a1 100644 --- a/tests/drivers/build_all/gpio/app.overlay +++ b/tests/drivers/build_all/gpio/app.overlay @@ -199,7 +199,7 @@ compatible = "x-powers,axp192-gpio"; gpio-controller; #gpio-cells = <2>; - ngpios = <5>; + ngpios = <6>; }; }; }; From 0addb90ff73cf4778cd0579f0da9f38590c4f0da Mon Sep 17 00:00:00 2001 From: Martin Kiepfer Date: Sun, 7 Jan 2024 16:40:35 +0100 Subject: [PATCH 0212/2402] drivers: mfd: axp192: add possibility to disable N_VBUSEN functionality By default N_VBUSEN signal is used by the host to define if VBUS signal should be used for power supply (VBUS-IPSOUT). This feature enables the possbibility to change this behaviour. When N_VBUSEN detection is disabled, axp192 will automatically decide to use VBUS (REG10H[7] = 1). Please refer to datasheet for details. Signed-off-by: Martin Kiepfer --- drivers/mfd/mfd_axp192.c | 22 +++++++++++++++++++++- dts/bindings/mfd/x-powers,axp192.yaml | 9 +++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/mfd_axp192.c b/drivers/mfd/mfd_axp192.c index 1286a2ba319..421f5d19a37 100644 --- a/drivers/mfd/mfd_axp192.c +++ b/drivers/mfd/mfd_axp192.c @@ -22,6 +22,7 @@ LOG_MODULE_REGISTER(mfd_axp192, CONFIG_MFD_LOG_LEVEL); #define AXP192_REG_CHIP_ID 0x03U /* AXP192 GPIO register addresses */ +#define AXP192_EXTEN_DCDC2_CONTROL_REG 0x10U #define AXP192_VBUS_CFG_REG 0x30U #define AXP192_GPIO0_FUNC_REG 0x90U #define AXP192_GPIO1_FUNC_REG 0x92U @@ -31,6 +32,9 @@ LOG_MODULE_REGISTER(mfd_axp192, CONFIG_MFD_LOG_LEVEL); #define AXP192_GPIO34_PINVAL_REG 0x96U #define AXP192_GPIO012_PULLDOWN_REG 0x97U +/* VBUS control reg values */ +#define AXP192_VBUS_CFG_VAL_VBUSEN_DISABLE 0x80U + /* GPIO function control parameters */ #define AXP192_GPIO012_FUNC_VAL_OUTPUT_OD 0x00U #define AXP192_GPIO012_FUNC_VAL_INPUT 0x01U @@ -84,6 +88,7 @@ LOG_MODULE_REGISTER(mfd_axp192, CONFIG_MFD_LOG_LEVEL); #define AXP192_GPIO2_OUTPUT_VAL 0x04U #define AXP192_GPIO012_OUTPUT_MASK \ (AXP192_GPIO0_OUTPUT_VAL | AXP192_GPIO1_OUTPUT_VAL | AXP192_GPIO2_OUTPUT_VAL) + #define AXP192_GPIO3_OUTPUT_VAL 0x01U #define AXP192_GPIO4_OUTPUT_VAL 0x02U #define AXP192_GPIO34_OUTPUT_MASK (AXP192_GPIO3_OUTPUT_VAL | AXP192_GPIO4_OUTPUT_VAL) @@ -91,8 +96,10 @@ LOG_MODULE_REGISTER(mfd_axp192, CONFIG_MFD_LOG_LEVEL); #define AXP192_GPIO5_OUTPUT_MASK 0x04U #define AXP192_GPIO5_OUTPUT_VAL 0x04U #define AXP192_GPIO5_OUTPUT_SHIFT 3U + struct mfd_axp192_config { struct i2c_dt_spec i2c; + bool vbusen_disable; }; struct mfd_axp192_data { @@ -137,6 +144,7 @@ static int mfd_axp192_init(const struct device *dev) { const struct mfd_axp192_config *config = dev->config; uint8_t chip_id; + uint8_t vbus_val; int ret; LOG_DBG("Initializing instance"); @@ -156,6 +164,17 @@ static int mfd_axp192_init(const struct device *dev) return -EINVAL; } + /* Disable N_VBUSEN */ + vbus_val = 0; + if (config->vbusen_disable) { + vbus_val = AXP192_VBUS_CFG_VAL_VBUSEN_DISABLE; + } + ret = i2c_reg_update_byte_dt(&config->i2c, AXP192_VBUS_CFG_REG, + AXP192_VBUS_CFG_VAL_VBUSEN_DISABLE, vbus_val); + if (ret < 0) { + return ret; + } + return 0; } @@ -590,6 +609,7 @@ int mfd_axp192_gpio_write_port(const struct device *dev, uint8_t value, uint8_t #define MFD_AXP192_DEFINE(inst) \ static const struct mfd_axp192_config config##inst = { \ .i2c = I2C_DT_SPEC_INST_GET(inst), \ + .vbusen_disable = DT_INST_PROP_OR(inst, vbusen_disable, false), \ }; \ \ static struct mfd_axp192_data data##inst; \ @@ -597,4 +617,4 @@ int mfd_axp192_gpio_write_port(const struct device *dev, uint8_t value, uint8_t DEVICE_DT_INST_DEFINE(inst, mfd_axp192_init, NULL, &data##inst, &config##inst, \ POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, NULL); -DT_INST_FOREACH_STATUS_OKAY(MFD_AXP192_DEFINE) +DT_INST_FOREACH_STATUS_OKAY(MFD_AXP192_DEFINE); diff --git a/dts/bindings/mfd/x-powers,axp192.yaml b/dts/bindings/mfd/x-powers,axp192.yaml index ae181715e88..44fdbac3024 100644 --- a/dts/bindings/mfd/x-powers,axp192.yaml +++ b/dts/bindings/mfd/x-powers,axp192.yaml @@ -10,3 +10,12 @@ include: i2c-device.yaml properties: reg: required: true + + vbusen-disable: + type: boolean + description: | + This option will disable VBUS power control via N_VBUSEN. + By default VBUS power supply is chosen via N_VBUSEN pin. + When disabled, VBUS can by chosen automatically by the pmic + and there is no need by the host to control N_VBUSEN pin. + Please refer to datasheet for details (pin state (REG10H[7] = 1). From a060c48cb0f041ad78bc7889f1e4d5d10bf016df Mon Sep 17 00:00:00 2001 From: Martin Kiepfer Date: Fri, 9 Feb 2024 20:23:15 +0100 Subject: [PATCH 0213/2402] doc: boards: m5stack_core2 documentation updates Minor corrections and updates on current development states Signed-off-by: Martin Kiepfer --- boards/m5stack/m5stack_core2/doc/index.rst | 74 ++++++++++++---------- 1 file changed, 40 insertions(+), 34 deletions(-) diff --git a/boards/m5stack/m5stack_core2/doc/index.rst b/boards/m5stack/m5stack_core2/doc/index.rst index 9dc66f5c9ba..19aece60f05 100644 --- a/boards/m5stack/m5stack_core2/doc/index.rst +++ b/boards/m5stack/m5stack_core2/doc/index.rst @@ -21,6 +21,7 @@ M5Stack Core2 features the following integrated components: - RTC BM8563 - USB CP2104 - SD-Card slot +- Grove connector - IMO 6-axis IMU MPU6886 - MIC SPM1423 - Battery 390mAh 3,7V @@ -50,39 +51,44 @@ of the M5Stack Core2 board. .. _PMU-AXP192: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/AXP192_datasheet_en.pdf .. _VIB-1072_RFN01: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/1027RFN01-33d.pdf -+------------------+--------------------------------------------------------------------------+------------+ -| Key Component | Description | Status | -+==================+==========================================================================+============+ -|| ESP32-D0WDQ6-V2 || This `MPU-ESP32`_ module provides complete Wi-Fi and Bluetooth || supported | -|| module || functionalities and integrates a 16-MB SPI flash. || | -+------------------+--------------------------------------------------------------------------+------------+ -|| 32.768 kHz RTC || External precision 32.768 kHz crystal oscillator serves as a clock with || supported | -|| || low-power consumption while the chip is in Deep-sleep mode. || | -+------------------+--------------------------------------------------------------------------+------------+ -| Status LED | One user LED connected to the GPIO pin. | supported | -+------------------+--------------------------------------------------------------------------+------------+ -|| USB Port || USB interface. Power supply for the board as well as the || supported | -|| || communication interface between a computer and the board. || | -|| || Contains: TypeC x 1, GROVE(I2C+I/O+UART) x 1 || | -+------------------+--------------------------------------------------------------------------+------------+ -| Reset button | Reset button | supported | -+------------------+--------------------------------------------------------------------------+------------+ -| Power Switch | Power on/off button. | supported | -+------------------+--------------------------------------------------------------------------+------------+ -|| LCD screen || Built-in LCD TFT display \(`LCD-ILI9342C`_, 2", 320x240 px\) || supported | -|| || controlled via SPI interface || | -+------------------+--------------------------------------------------------------------------+------------+ -| SD-Card slot | SD-Card connection via SPI-mode. | supported | -+------------------+--------------------------------------------------------------------------+------------+ -|| 6-axis IMU || The `MPU-6886`_ is a 6-axis motion tracker (6DOF IMU) device that || todo | -|| MPU6886 || combines a 3-axis gyroscope and a 3-axis accelerometer. || | -|| || For details please refer to :ref:`m5stack_core2_ext` || | -+------------------+--------------------------------------------------------------------------+------------+ -|| Built-in || The `SPM-1423`_ I2S driven microphone. || todo | -|| microphone || || | -+------------------+--------------------------------------------------------------------------+------------+ -| Built-in speaker | 1W speaker for audio output via I2S interface. | todo | -+------------------+--------------------------------------------------------------------------+------------+ ++------------------+--------------------------------------------------------------------------+-----------+ +| Key Component | Description | Status | ++==================+==========================================================================+===========+ +| ESP32-D0WDQ6-V2 | This `MPU-ESP32`_ module provides complete Wi-Fi and Bluetooth | supported | +| module | functionalities and integrates a 16-MB SPI flash. | | ++------------------+--------------------------------------------------------------------------+-----------+ +| 32.768 kHz RTC | External precision 32.768 kHz crystal oscillator serves as a clock with | supported | +| | low-power consumption while the chip is in Deep-sleep mode. | | ++------------------+--------------------------------------------------------------------------+-----------+ +| Status LED | One user LED connected to the GPIO pin. | supported | ++------------------+--------------------------------------------------------------------------+-----------+ +| USB Port | USB interface. Power supply for the board as well as the | supported | +| | communication interface between a computer and the board. | | +| | Contains: TypeC x 1, GROVE(I2C+I/O+UART) x 1 | | ++------------------+--------------------------------------------------------------------------+-----------+ +| Reset button | Reset button | supported | ++------------------+--------------------------------------------------------------------------+-----------+ +| Power Switch | Power on/off button. | supported | ++------------------+--------------------------------------------------------------------------+-----------+ +| LCD screen | Built-in LCD TFT display \(`LCD-ILI9342C`_, 2", 320x240 px\) | supported | +| | controlled via SPI interface | | ++------------------+--------------------------------------------------------------------------+-----------+ +| SD-Card slot | SD-Card connection via SPI-mode. | supported | ++------------------+--------------------------------------------------------------------------+-----------+ +| 6-axis IMU | The `MPU-6886`_ is a 6-axis motion tracker (6DOF IMU) device that | supported | +| MPU6886 | combines a 3-axis gyroscope and a 3-axis accelerometer. | | +| | For details please refer to :ref:`m5stack_core2_ext` | | ++------------------+--------------------------------------------------------------------------+-----------+ +| Grove port | Note: Grove port requires 5V to be enabled via `bus_5v` regulator | supported | ++------------------+--------------------------------------------------------------------------+-----------+ +| Built-in | The `SPM-1423`_ I2S driven microphone. | todo | +| microphone | | | ++------------------+--------------------------------------------------------------------------+-----------+ +| Built-in speaker | 1W speaker for audio output via I2S interface. | todo | ++------------------+--------------------------------------------------------------------------+-----------+ +| Battery-support | Power supply via battery is supported automatically. But there is no | todo | +| | possibility to query current battery status. | | ++------------------+--------------------------------------------------------------------------+-----------+ Supported Features ================== @@ -190,7 +196,7 @@ M5Stack Core2 debugging is not supported due to pinout limitations. Related Documents ***************** -- `M5StickC PLUS schematic `_ (WEBP) +- `M5Stack-Core2 schematic `_ (PDF) - `ESP32-PICO-D4 Datasheet `_ (PDF) - `M5StickC PLUS docs `_ - `ESP32 Datasheet `_ (PDF) From 61934bb6d6150db0d103059cdf1941181a24b72b Mon Sep 17 00:00:00 2001 From: Martin Kiepfer Date: Sun, 7 Jan 2024 17:44:14 +0100 Subject: [PATCH 0214/2402] boards: m5stack_core2: Add possibility to control 5V_BUS signal This commit fixes #67277 and hence adds possibility to properly utilize grove extension port. 5V_BUS can be enabled via regulator bus_5v. By default this regulator is disabled. Signed-off-by: Martin Kiepfer --- .../m5stack/m5stack_core2/Kconfig.defconfig | 15 ++++++++++--- boards/m5stack/m5stack_core2/doc/index.rst | 21 +++++++++++++++++++ .../m5stack_core2_esp32_procpu.dts | 11 ++++++++-- 3 files changed, 42 insertions(+), 5 deletions(-) diff --git a/boards/m5stack/m5stack_core2/Kconfig.defconfig b/boards/m5stack/m5stack_core2/Kconfig.defconfig index 6057cf0a0f5..2c0a21ef88d 100644 --- a/boards/m5stack/m5stack_core2/Kconfig.defconfig +++ b/boards/m5stack/m5stack_core2/Kconfig.defconfig @@ -19,11 +19,20 @@ choice BT_HCI_BUS_TYPE default BT_ESP32 if BT endchoice +config GPIO_HOGS_INIT_PRIORITY + default 70 + +config MFD_INIT_PRIORITY + default 70 + config REGULATOR_AXP192_INIT_PRIORITY - default 81 + default 71 -config GPIO_HOGS_INIT_PRIORITY - default 82 +config GPIO_AXP192_INIT_PRIORITY + default 72 + +config REGULATOR_FIXED_INIT_PRIORITY + default 75 config INPUT_FT5336_INTERRUPT default y if INPUT diff --git a/boards/m5stack/m5stack_core2/doc/index.rst b/boards/m5stack/m5stack_core2/doc/index.rst index 19aece60f05..96669efcb1b 100644 --- a/boards/m5stack/m5stack_core2/doc/index.rst +++ b/boards/m5stack/m5stack_core2/doc/index.rst @@ -90,6 +90,27 @@ of the M5Stack Core2 board. | | possibility to query current battery status. | | +------------------+--------------------------------------------------------------------------+-----------+ +Power supply +============ +M5Stack Core2 module is equipped with the feature-rich power management IC +(:dtcompatible:`x-powers,axp192-regulator`). +Following regulators are utilized on this module: + +- **vdd_mcu**: + Main power supply for the MCU. +- **lcd_bg**: + Display backlight voltage. +- **v_peri**: + Periphal supply. This regulator controls supply for the display, SD-Card. +- **vib_motor**: + Vibration motor regulator. +- **bus_5v** + BUS_5V supply for Grove port. + Note: This fixed regulator supply is disabled by default. + + +These voltages can be controlled via regulator api. + Supported Features ================== diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.dts index 0ca3efab6cd..3ccb638c974 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.dts +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.dts @@ -163,7 +163,7 @@ compatible = "x-powers,axp192-gpio"; gpio-controller; #gpio-cells = <2>; - ngpios = <5>; + ngpios = <6>; status = "okay"; pwr_led: axp192_gpio1 { @@ -176,11 +176,18 @@ bus_pwr_en: axp192_gpio0 { gpio-hog; gpios = <0 0>; - input; + output-high; + line-name = "bus_pwr_en"; }; }; }; + bus_5v: bus_5v { + compatible = "regulator-fixed"; + regulator-name = "bus_5v"; + enable-gpios = <&axp192_gpio 5 GPIO_ACTIVE_HIGH>; + }; + ft5336_touch: ft5336@38 { compatible = "focaltech,ft5336"; reg = <0x38>; From ad58b39f411d75c263aa213f69d19e0deac463cd Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Thu, 1 Feb 2024 13:21:29 +0100 Subject: [PATCH 0215/2402] logging: Add option to not generate dictionary database always Add option to not generate the logging dictionary database when the zephyr finale image is created. Instead this database can be created by its own build target. This reduces the build time during debugging as the database file is not required as part of the debugging. Fix build byproducts not listing the output file. Add comment so users know which command is executing as this command can take a long time. Signed-off-by: Joakim Andersson --- CMakeLists.txt | 37 ++++++++++++++++++++----------------- subsys/logging/Kconfig.misc | 9 +++++++++ 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 131a7fc8a5e..09a4ec6b55d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1875,27 +1875,30 @@ list(APPEND ) if(CONFIG_LOG_DICTIONARY_DB) - set(log_dict_db_output --json=${PROJECT_BINARY_DIR}/log_dictionary.json) + set(LOG_DICT_DB_NAME ${PROJECT_BINARY_DIR}/log_dictionary.json) + set(LOG_DICT_DB_NAME_ARG --json) elseif(CONFIG_LOG_MIPI_SYST_USE_CATALOG) - set(log_dict_db_output --syst=${PROJECT_BINARY_DIR}/mipi_syst_collateral.xml) + set(LOG_DICT_DB_NAME ${PROJECT_BINARY_DIR}/mipi_syst_collateral.xml) + set(LOG_DICT_DB_NAME_ARG --syst) endif() -if(log_dict_db_output) - list(APPEND - post_build_commands +if(LOG_DICT_DB_NAME_ARG) + if (NOT CONFIG_LOG_DICTIONARY_DB_TARGET) + set(LOG_DICT_DB_ALL_TARGET ALL) + endif() + add_custom_command( + OUTPUT ${LOG_DICT_DB_NAME} COMMAND - ${PYTHON_EXECUTABLE} - ${ZEPHYR_BASE}/scripts/logging/dictionary/database_gen.py - ${KERNEL_ELF_NAME} - ${log_dict_db_output} - --build-header ${PROJECT_BINARY_DIR}/include/generated/version.h - ) - list(APPEND - post_build_byproducts - ${LOG_DICT_DB_NAME} - ) - - unset(log_dict_db_output) + ${PYTHON_EXECUTABLE} + ${ZEPHYR_BASE}/scripts/logging/dictionary/database_gen.py + ${KERNEL_ELF_NAME} + ${LOG_DICT_DB_NAME_ARG}=${LOG_DICT_DB_NAME} + --build-header ${PROJECT_BINARY_DIR}/include/generated/version.h + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} + COMMENT "Generating logging dictionary database: ${LOG_DICT_DB_NAME}" + DEPENDS ${logical_target_for_zephyr_elf} + ) + add_custom_target(log_dict_db_gen ${LOG_DICT_DB_ALL_TARGET} DEPENDS ${LOG_DICT_DB_NAME}) endif() # Add post_build_commands to post-process the final .elf file produced by diff --git a/subsys/logging/Kconfig.misc b/subsys/logging/Kconfig.misc index d333e19ce53..4f10680f4b6 100644 --- a/subsys/logging/Kconfig.misc +++ b/subsys/logging/Kconfig.misc @@ -99,6 +99,15 @@ config LOG_MEM_UTILIZATION config LOG_DICTIONARY_DB bool +config LOG_DICTIONARY_DB_TARGET + bool "Only generated log dictionary database from target" + depends on LOG_DICTIONARY_DB + help + Enable this option to make generating the log dictionary database + only done by its own build target. + This removes the target from the ALL make target and the target + 'log_dict_db_gen' has to be called in addition. + config LOG_MSG_APPEND_RO_STRING_LOC bool help From 0d5a670f4f073ff2185221b76afc1998a08a4074 Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Fri, 1 Mar 2024 12:33:12 +0100 Subject: [PATCH 0216/2402] lib/os/printk.c: use ARG_UNUSED() for char_out() Use ARG_UNUSED() within the function char_out() to handel unused param. Signed-off-by: Florian La Roche --- lib/os/printk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/os/printk.c b/lib/os/printk.c index ac19e9e38fc..71a0d6aeac8 100644 --- a/lib/os/printk.c +++ b/lib/os/printk.c @@ -107,7 +107,7 @@ static int buf_char_out(int c, void *ctx_p) static int char_out(int c, void *ctx_p) { - (void) ctx_p; + ARG_UNUSED(ctx_p); return _char_out(c); } From 5be84131d6f8f68126d58134a7aa307b93050acb Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 4 Mar 2024 13:55:48 +0200 Subject: [PATCH 0217/2402] net: dns: Split long resolving to smaller pieces If getaddrinfo() is called with a long DNS timeout, then split the timeout to smaller pieces with exponential backoff. Reason for this is that if a DNS query is lost, then we do not need to wait for a long time to find it out. Signed-off-by: Jukka Rissanen --- subsys/net/lib/sockets/Kconfig | 22 ++++++++++++++- subsys/net/lib/sockets/getaddrinfo.c | 41 ++++++++++++++++++++++++++-- 2 files changed, 59 insertions(+), 4 deletions(-) diff --git a/subsys/net/lib/sockets/Kconfig b/subsys/net/lib/sockets/Kconfig index 88fa5389528..8b428057e3c 100644 --- a/subsys/net/lib/sockets/Kconfig +++ b/subsys/net/lib/sockets/Kconfig @@ -64,7 +64,27 @@ config NET_SOCKETS_DNS_TIMEOUT help This variable specifies time in milliseconds after which DNS query is considered timeout. Minimum timeout is 1 second and - maximum timeout is 5 min. + maximum timeout is 5 min. If the value is higher than + CONFIG_NET_SOCKETS_DNS_BACKOFF_INTERVAL, then we try multiple + times with exponential backoff until the timeout is reached. + +config NET_SOCKETS_DNS_BACKOFF_INTERVAL + int "Backoff interval for the DNS timeout" + default 5000 + range 1000 300000 + depends on DNS_RESOLVER + help + This variable is related to the DNS timeout. If the DNS timeout is + smaller than this value, then this value is ignored. If the timeout + is larger, then this variable specifies time in milliseconds after + which DNS query is re-tried. If there is no reply, the backoff + interval is doubled and query is retried. + Example: + The CONFIG_NET_SOCKETS_DNS_TIMEOUT is set to 17000 (17 secs). + This value is 5000 (5 sec). If there is no reply from DNS server + within 5 secs, a 2nd query is done with timeout set to 10 sec (5 * 2). + If no reply is received, a 3rd query is done after 15 sec (5 + 5 * 2), + and the timeout is set to 2 sec so that the total timeout is 17 seconds. config NET_SOCKET_MAX_SEND_WAIT int "Max time in milliseconds waiting for a send command" diff --git a/subsys/net/lib/sockets/getaddrinfo.c b/subsys/net/lib/sockets/getaddrinfo.c index 70a611a3f4a..a7f2b54b604 100644 --- a/subsys/net/lib/sockets/getaddrinfo.c +++ b/subsys/net/lib/sockets/getaddrinfo.c @@ -103,19 +103,42 @@ static void dns_resolve_cb(enum dns_resolve_status status, state->idx++; } +static k_timeout_t recalc_timeout(k_timepoint_t end, k_timeout_t timeout) +{ + k_timepoint_t new_timepoint; + + timeout.ticks <<= 1; + + new_timepoint = sys_timepoint_calc(timeout); + + if (sys_timepoint_cmp(end, new_timepoint) < 0) { + timeout = sys_timepoint_timeout(end); + } + + return timeout; +} + static int exec_query(const char *host, int family, struct getaddrinfo_state *ai_state) { enum dns_query_type qtype = DNS_QUERY_TYPE_A; + k_timepoint_t end = sys_timepoint_calc(K_MSEC(CONFIG_NET_SOCKETS_DNS_TIMEOUT)); + k_timeout_t timeout = K_MSEC(MIN(CONFIG_NET_SOCKETS_DNS_TIMEOUT, + CONFIG_NET_SOCKETS_DNS_BACKOFF_INTERVAL)); + int timeout_ms; int st, ret; if (family == AF_INET6) { qtype = DNS_QUERY_TYPE_AAAA; } +again: + timeout_ms = k_ticks_to_ms_floor32(timeout.ticks); + + NET_DBG("Timeout %d", timeout_ms); + ret = dns_get_addr_info(host, qtype, &ai_state->dns_id, - dns_resolve_cb, ai_state, - CONFIG_NET_SOCKETS_DNS_TIMEOUT); + dns_resolve_cb, ai_state, timeout_ms); if (ret == 0) { /* If the DNS query for reason fails so that the * dns_resolve_cb() would not be called, then we want the @@ -123,11 +146,23 @@ static int exec_query(const char *host, int family, * So make the sem timeout longer than the DNS timeout so that * we do not need to start to cancel any pending DNS queries. */ - ret = k_sem_take(&ai_state->sem, K_MSEC(CONFIG_NET_SOCKETS_DNS_TIMEOUT + 100)); + ret = k_sem_take(&ai_state->sem, K_MSEC(timeout_ms + 100)); if (ret == -EAGAIN) { + if (!sys_timepoint_expired(end)) { + timeout = recalc_timeout(end, timeout); + goto again; + } + (void)dns_cancel_addr_info(ai_state->dns_id); st = DNS_EAI_AGAIN; } else { + if (ai_state->status == DNS_EAI_CANCELED) { + if (!sys_timepoint_expired(end)) { + timeout = recalc_timeout(end, timeout); + goto again; + } + } + st = ai_state->status; } } else if (ret == -EPFNOSUPPORT) { From 1d96454dc743e25f6c880f7a575e97579ec4661b Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 4 Mar 2024 13:57:50 +0200 Subject: [PATCH 0218/2402] tests: net: dns: Fix the tests to check the exponential backoff Make sure that we do needed number of exponential backoff queries if configured so. Signed-off-by: Jukka Rissanen --- tests/net/socket/getaddrinfo/src/main.c | 24 +++++++++++++--------- tests/net/socket/getaddrinfo/testcase.yaml | 14 ++++++++----- 2 files changed, 23 insertions(+), 15 deletions(-) diff --git a/tests/net/socket/getaddrinfo/src/main.c b/tests/net/socket/getaddrinfo/src/main.c index d6c9ee0cf20..39999a84caf 100644 --- a/tests/net/socket/getaddrinfo/src/main.c +++ b/tests/net/socket/getaddrinfo/src/main.c @@ -9,6 +9,7 @@ LOG_MODULE_REGISTER(net_test, CONFIG_NET_SOCKETS_LOG_LEVEL); #include #include +#include #include #include #include @@ -35,6 +36,12 @@ static struct sockaddr_in addr_v4; static struct sockaddr_in6 addr_v6; static int queries_received; +static int expected_query_count = + CONFIG_NET_SOCKETS_DNS_BACKOFF_INTERVAL >= CONFIG_NET_SOCKETS_DNS_TIMEOUT ? + 2 : + /* Calculate for both IPv4 and IPv6 so need to double the value */ + 2 * (LOG2CEIL(DIV_ROUND_UP(CONFIG_NET_SOCKETS_DNS_TIMEOUT, + CONFIG_NET_SOCKETS_DNS_BACKOFF_INTERVAL) + 1)); /* The semaphore is there to wait the data to be received. */ static ZTEST_BMEM struct sys_sem wait_data; @@ -230,15 +237,12 @@ ZTEST(net_socket_getaddrinfo, test_getaddrinfo_ok) */ (void)getaddrinfo(QUERY_HOST, NULL, NULL, &res); - if (sys_sem_count_get(&wait_data) != 2) { - zassert_true(false, "Did not receive all queries"); - } - (void)sys_sem_take(&wait_data, K_NO_WAIT); (void)sys_sem_take(&wait_data, K_NO_WAIT); - zassert_equal(queries_received, 2, - "Did not receive both IPv4 and IPv6 query"); + zassert_equal(queries_received, expected_query_count, + "Did not receive both IPv4 and IPv6 query (got %d, expected %d)", + queries_received, expected_query_count); freeaddrinfo(res); } @@ -250,13 +254,13 @@ ZTEST(net_socket_getaddrinfo, test_getaddrinfo_cancelled) ret = getaddrinfo(QUERY_HOST, NULL, NULL, &res); - if (sys_sem_count_get(&wait_data) != 2) { - zassert_true(false, "Did not receive all queries"); - } - (void)sys_sem_take(&wait_data, K_NO_WAIT); (void)sys_sem_take(&wait_data, K_NO_WAIT); + zassert_equal(queries_received, expected_query_count, + "Did not receive both IPv4 and IPv6 query (got %d, expected %d)", + queries_received, expected_query_count); + /* Without a local DNS server this request will be canceled. */ zassert_equal(ret, DNS_EAI_CANCELED, "Invalid result"); diff --git a/tests/net/socket/getaddrinfo/testcase.yaml b/tests/net/socket/getaddrinfo/testcase.yaml index b22bc2a1661..3d7bb633703 100644 --- a/tests/net/socket/getaddrinfo/testcase.yaml +++ b/tests/net/socket/getaddrinfo/testcase.yaml @@ -1,11 +1,15 @@ common: depends_on: netif filter: CONFIG_FULL_LIBC_SUPPORTED + tags: + - net + - socket + - getaddrinfo + - userspace tests: net.socket.get_addr_info: min_ram: 21 - tags: - - net - - socket - - getaddrinfo - - userspace + net.socket.get_addr_info.timeout: + extra_configs: + - CONFIG_NET_SOCKETS_DNS_TIMEOUT=2000 + - CONFIG_NET_SOCKETS_DNS_BACKOFF_INTERVAL=1000 From 8b9464089cb535e507e5083ca0c9c64a170f38d8 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Sun, 3 Mar 2024 16:53:30 +0000 Subject: [PATCH 0219/2402] input: add a pmw3610 driver Add a driver for the Pixart PMW3610 mouse sensor device. Signed-off-by: Fabio Baltieri --- drivers/input/CMakeLists.txt | 1 + drivers/input/Kconfig | 1 + drivers/input/Kconfig.pmw3610 | 10 + drivers/input/input_pmw3610.c | 433 ++++++++++++++++++++++ dts/bindings/input/pixart,pmw3610.yaml | 44 +++ tests/drivers/build_all/input/app.overlay | 15 +- 6 files changed, 503 insertions(+), 1 deletion(-) create mode 100644 drivers/input/Kconfig.pmw3610 create mode 100644 drivers/input/input_pmw3610.c create mode 100644 dts/bindings/input/pixart,pmw3610.yaml diff --git a/drivers/input/CMakeLists.txt b/drivers/input/CMakeLists.txt index d679c9d0fd9..490db67227b 100644 --- a/drivers/input/CMakeLists.txt +++ b/drivers/input/CMakeLists.txt @@ -19,6 +19,7 @@ zephyr_library_sources_ifdef(CONFIG_INPUT_ITE_IT8XXX2_KBD input_ite_it8xxx2_kbd. zephyr_library_sources_ifdef(CONFIG_INPUT_KBD_MATRIX input_kbd_matrix.c) zephyr_library_sources_ifdef(CONFIG_INPUT_NPCX_KBD input_npcx_kbd.c) zephyr_library_sources_ifdef(CONFIG_INPUT_PAT912X input_pat912x.c) +zephyr_library_sources_ifdef(CONFIG_INPUT_PMW3610 input_pmw3610.c) zephyr_library_sources_ifdef(CONFIG_INPUT_STMPE811 input_stmpe811.c) zephyr_library_sources_ifdef(CONFIG_INPUT_XPT2046 input_xpt2046.c) # zephyr-keep-sorted-stop diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index dd113130b30..a71dded2212 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -21,6 +21,7 @@ source "drivers/input/Kconfig.it8xxx2" source "drivers/input/Kconfig.kbd_matrix" source "drivers/input/Kconfig.npcx" source "drivers/input/Kconfig.pat912x" +source "drivers/input/Kconfig.pmw3610" source "drivers/input/Kconfig.sdl" source "drivers/input/Kconfig.stmpe811" source "drivers/input/Kconfig.xpt2046" diff --git a/drivers/input/Kconfig.pmw3610 b/drivers/input/Kconfig.pmw3610 new file mode 100644 index 00000000000..7316a3622d2 --- /dev/null +++ b/drivers/input/Kconfig.pmw3610 @@ -0,0 +1,10 @@ +# Copyright 2024 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config INPUT_PMW3610 + bool "PMW3610 low power laser mouse sensor input driver" + default y + depends on DT_HAS_PIXART_PMW3610_ENABLED + select SPI + help + PMW3610 low power laser mouse sensor input driver diff --git a/drivers/input/input_pmw3610.c b/drivers/input/input_pmw3610.c new file mode 100644 index 00000000000..2933ce2433a --- /dev/null +++ b/drivers/input/input_pmw3610.c @@ -0,0 +1,433 @@ +/* + * Copyright 2024 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT pixart_pmw3610 + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(input_pmw3610, CONFIG_INPUT_LOG_LEVEL); + +/* Page 0 */ +#define PMW3610_PROD_ID 0x00 +#define PMW3610_REV_ID 0x01 +#define PMW3610_MOTION 0x02 +#define PMW3610_DELTA_X_L 0x03 +#define PMW3610_DELTA_Y_L 0x04 +#define PMW3610_DELTA_XY_H 0x05 +#define PMW3610_PERFORMANCE 0x11 +#define PMW3610_BURST_READ 0x12 +#define PMW3610_RUN_DOWNSHIFT 0x1b +#define PMW3610_REST1_RATE 0x1c +#define PMW3610_REST1_DOWNSHIFT 0x1d +#define PMW3610_OBSERVATION1 0x2d +#define PMW3610_POWER_UP_RESET 0x3a +#define PMW3610_SHUTDOWN 0x3b +#define PMW3610_SPI_CLK_ON_REQ 0x41 +#define PWM3610_SPI_PAGE0 0x7f + +/* Page 1 */ +#define PMW3610_RES_STEP 0x05 +#define PWM3610_SPI_PAGE1 0x7f + +/* Burst register offsets */ +#define BURST_MOTION 0 +#define BURST_DELTA_X_L 1 +#define BURST_DELTA_Y_L 2 +#define BURST_DELTA_XY_H 3 +#define BURST_SQUAL 4 +#define BURST_SHUTTER_HI 5 +#define BURST_SHUTTER_LO 6 + +/* Init sequence values */ +#define OBSERVATION1_INIT_MASK 0x0f +#define PERFORMANCE_INIT 0x0d +#define RUN_DOWNSHIFT_INIT 0x04 +#define REST1_RATE_INIT 0x04 +#define REST1_DOWNSHIFT_INIT 0x0f + +#define PRODUCT_ID_PMW3610 0x3e +#define SPI_WRITE BIT(7) +#define MOTION_STATUS_MOTION BIT(7) +#define SPI_CLOCK_ON_REQ_ON 0xba +#define SPI_CLOCK_ON_REQ_OFF 0xb5 +#define RES_STEP_INV_X_BIT 6 +#define RES_STEP_INV_Y_BIT 5 +#define POWER_UP_WAKEUP 0x96 +#define SHUTDOWN_ENABLE 0xe7 +#define SPI_PAGE0_1 0xff +#define SPI_PAGE1_0 0x00 + +#define PMW3610_DATA_SIZE_BITS 12 + +#define RESET_DELAY_MS 10 +#define INIT_OBSERVATION_DELAY_MS 10 +#define CLOCK_ON_DELAY_US 300 + +struct pmw3610_config { + struct spi_dt_spec spi; + struct gpio_dt_spec motion_gpio; + struct gpio_dt_spec reset_gpio; + uint16_t axis_x; + uint16_t axis_y; + bool invert_x; + bool invert_y; +}; + +struct pmw3610_data { + const struct device *dev; + struct k_work motion_work; + struct gpio_callback motion_cb; +}; + +static int pmw3610_read(const struct device *dev, + uint8_t addr, uint8_t *value, uint8_t len) +{ + const struct pmw3610_config *cfg = dev->config; + + const struct spi_buf tx_buf = { + .buf = &addr, + .len = sizeof(addr), + }; + const struct spi_buf_set tx = { + .buffers = &tx_buf, + .count = 1, + }; + + struct spi_buf rx_buf[] = { + { + .buf = NULL, + .len = sizeof(addr), + }, + { + .buf = value, + .len = len, + }, + }; + const struct spi_buf_set rx = { + .buffers = rx_buf, + .count = ARRAY_SIZE(rx_buf), + }; + + return spi_transceive_dt(&cfg->spi, &tx, &rx); +} + +static int pmw3610_read_reg(const struct device *dev, uint8_t addr, uint8_t *value) +{ + return pmw3610_read(dev, addr, value, 1); +} + +static int pmw3610_write_reg(const struct device *dev, uint8_t addr, uint8_t value) +{ + const struct pmw3610_config *cfg = dev->config; + + uint8_t write_buf[] = {addr | SPI_WRITE, value}; + const struct spi_buf tx_buf = { + .buf = write_buf, + .len = sizeof(write_buf), + }; + const struct spi_buf_set tx = { + .buffers = &tx_buf, + .count = 1, + }; + + return spi_write_dt(&cfg->spi, &tx); +} + +static int pmw3610_spi_clk_on(const struct device *dev) +{ + int ret; + + ret = pmw3610_write_reg(dev, PMW3610_SPI_CLK_ON_REQ, SPI_CLOCK_ON_REQ_ON); + + k_sleep(K_USEC(CLOCK_ON_DELAY_US)); + + return ret; +} + +static int pmw3610_spi_clk_off(const struct device *dev) +{ + return pmw3610_write_reg(dev, PMW3610_SPI_CLK_ON_REQ, SPI_CLOCK_ON_REQ_OFF); +} + +static void pmw3610_motion_work_handler(struct k_work *work) +{ + struct pmw3610_data *data = CONTAINER_OF( + work, struct pmw3610_data, motion_work); + const struct device *dev = data->dev; + const struct pmw3610_config *cfg = dev->config; + uint8_t burst_data[4]; + int32_t x, y; + int ret; + + ret = pmw3610_read(dev, PMW3610_BURST_READ, burst_data, sizeof(burst_data)); + if (ret < 0) { + return; + } + + if ((burst_data[BURST_MOTION] & MOTION_STATUS_MOTION) == 0x00) { + return; + } + + x = ((burst_data[BURST_DELTA_XY_H] << 4) & 0xf00) | burst_data[BURST_DELTA_X_L]; + y = ((burst_data[BURST_DELTA_XY_H] << 8) & 0xf00) | burst_data[BURST_DELTA_Y_L]; + + x = sign_extend(x, PMW3610_DATA_SIZE_BITS - 1); + y = sign_extend(y, PMW3610_DATA_SIZE_BITS - 1); + + input_report_rel(data->dev, cfg->axis_x, x, false, K_FOREVER); + input_report_rel(data->dev, cfg->axis_y, y, true, K_FOREVER); +} + +static void pmw3610_motion_handler(const struct device *gpio_dev, + struct gpio_callback *cb, + uint32_t pins) +{ + struct pmw3610_data *data = CONTAINER_OF( + cb, struct pmw3610_data, motion_cb); + + k_work_submit(&data->motion_work); +} + +static int pmw3610_configure(const struct device *dev) +{ + const struct pmw3610_config *cfg = dev->config; + uint8_t val; + int ret; + + if (cfg->reset_gpio.port != NULL) { + if (!gpio_is_ready_dt(&cfg->reset_gpio)) { + LOG_ERR("%s is not ready", cfg->reset_gpio.port->name); + return -ENODEV; + } + + ret = gpio_pin_configure_dt(&cfg->reset_gpio, GPIO_OUTPUT_ACTIVE); + if (ret != 0) { + LOG_ERR("Reset pin configuration failed: %d", ret); + return ret; + } + + k_sleep(K_MSEC(RESET_DELAY_MS)); + + gpio_pin_set_dt(&cfg->reset_gpio, 0); + + k_sleep(K_MSEC(RESET_DELAY_MS)); + } + + ret = pmw3610_read_reg(dev, PMW3610_PROD_ID, &val); + if (ret < 0) { + return ret; + } + + if (val != PRODUCT_ID_PMW3610) { + LOG_ERR("Invalid product id: %02x", val); + return -ENOTSUP; + } + + /* Power-up init sequence */ + + ret = pmw3610_write_reg(dev, PMW3610_OBSERVATION1, 0); + if (ret < 0) { + return ret; + } + + k_sleep(K_MSEC(INIT_OBSERVATION_DELAY_MS)); + + ret = pmw3610_read_reg(dev, PMW3610_OBSERVATION1, &val); + if (ret < 0) { + return ret; + } + + if ((val & OBSERVATION1_INIT_MASK) != OBSERVATION1_INIT_MASK) { + LOG_ERR("Unexpected OBSERVATION1 value: %02x", val); + return -EINVAL; + } + + for (uint8_t reg = PMW3610_MOTION; reg <= PMW3610_DELTA_XY_H; reg++) { + ret = pmw3610_read_reg(dev, reg, &val); + if (ret < 0) { + return ret; + } + } + + ret = pmw3610_write_reg(dev, PMW3610_PERFORMANCE, PERFORMANCE_INIT); + if (ret < 0) { + return ret; + } + + ret = pmw3610_write_reg(dev, PMW3610_RUN_DOWNSHIFT, RUN_DOWNSHIFT_INIT); + if (ret < 0) { + return ret; + } + + ret = pmw3610_write_reg(dev, PMW3610_REST1_RATE, REST1_RATE_INIT); + if (ret < 0) { + return ret; + } + + ret = pmw3610_write_reg(dev, PMW3610_REST1_DOWNSHIFT, REST1_DOWNSHIFT_INIT); + if (ret < 0) { + return ret; + } + + /* Configuration */ + + if (cfg->invert_x || cfg->invert_y) { + ret = pmw3610_spi_clk_on(dev); + if (ret < 0) { + return ret; + } + + ret = pmw3610_write_reg(dev, PWM3610_SPI_PAGE0, SPI_PAGE0_1); + if (ret < 0) { + return ret; + } + + ret = pmw3610_read_reg(dev, PMW3610_RES_STEP, &val); + if (ret < 0) { + return ret; + } + + WRITE_BIT(val, RES_STEP_INV_X_BIT, cfg->invert_x); + WRITE_BIT(val, RES_STEP_INV_Y_BIT, cfg->invert_y); + + ret = pmw3610_write_reg(dev, PMW3610_RES_STEP, val); + if (ret < 0) { + return ret; + } + + ret = pmw3610_write_reg(dev, PWM3610_SPI_PAGE1, SPI_PAGE1_0); + if (ret < 0) { + return ret; + } + + ret = pmw3610_spi_clk_off(dev); + if (ret < 0) { + return ret; + } + } + + return 0; +} + +static int pmw3610_init(const struct device *dev) +{ + const struct pmw3610_config *cfg = dev->config; + struct pmw3610_data *data = dev->data; + int ret; + + if (!spi_is_ready_dt(&cfg->spi)) { + LOG_ERR("%s is not ready", cfg->spi.bus->name); + return -ENODEV; + } + + data->dev = dev; + + k_work_init(&data->motion_work, pmw3610_motion_work_handler); + + if (!gpio_is_ready_dt(&cfg->motion_gpio)) { + LOG_ERR("%s is not ready", cfg->motion_gpio.port->name); + return -ENODEV; + } + + ret = gpio_pin_configure_dt(&cfg->motion_gpio, GPIO_INPUT); + if (ret != 0) { + LOG_ERR("Motion pin configuration failed: %d", ret); + return ret; + } + + gpio_init_callback(&data->motion_cb, pmw3610_motion_handler, + BIT(cfg->motion_gpio.pin)); + + ret = gpio_add_callback_dt(&cfg->motion_gpio, &data->motion_cb); + if (ret < 0) { + LOG_ERR("Could not set motion callback: %d", ret); + return ret; + } + + ret = pmw3610_configure(dev); + if (ret != 0) { + LOG_ERR("Device configuration failed: %d", ret); + return ret; + } + + ret = gpio_pin_interrupt_configure_dt(&cfg->motion_gpio, + GPIO_INT_EDGE_TO_ACTIVE); + if (ret != 0) { + LOG_ERR("Motion interrupt configuration failed: %d", ret); + return ret; + } + + ret = pm_device_runtime_enable(dev); + if (ret < 0) { + LOG_ERR("Failed to enable runtime power management: %d", ret); + return ret; + } + + return 0; +} + +#ifdef CONFIG_PM_DEVICE +static int pmw3610_pm_action(const struct device *dev, + enum pm_device_action action) +{ + int ret; + + switch (action) { + case PM_DEVICE_ACTION_SUSPEND: + ret = pmw3610_write_reg(dev, PMW3610_SHUTDOWN, SHUTDOWN_ENABLE); + if (ret < 0) { + return ret; + } + break; + case PM_DEVICE_ACTION_RESUME: + ret = pmw3610_write_reg(dev, PMW3610_POWER_UP_RESET, POWER_UP_WAKEUP); + if (ret < 0) { + return ret; + } + break; + default: + return -ENOTSUP; + } + + return 0; +} +#endif + +#define PMW3610_SPI_MODE (SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | \ + SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_TRANSFER_MSB) + +#define PMW3610_INIT(n) \ + static const struct pmw3610_config pmw3610_cfg_##n = { \ + .spi = SPI_DT_SPEC_INST_GET(n, PMW3610_SPI_MODE, 0), \ + .motion_gpio = GPIO_DT_SPEC_INST_GET(n, motion_gpios), \ + .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {}), \ + .axis_x = DT_INST_PROP(n, zephyr_axis_x), \ + .axis_y = DT_INST_PROP(n, zephyr_axis_y), \ + .invert_x = DT_INST_PROP(n, invert_x), \ + .invert_y = DT_INST_PROP(n, invert_y), \ + }; \ + \ + static struct pmw3610_data pmw3610_data_##n; \ + \ + PM_DEVICE_DT_INST_DEFINE(n, pmw3610_pm_action); \ + \ + DEVICE_DT_INST_DEFINE(n, pmw3610_init, PM_DEVICE_DT_INST_GET(n), \ + &pmw3610_data_##n, &pmw3610_cfg_##n, \ + POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \ + NULL); + +DT_INST_FOREACH_STATUS_OKAY(PMW3610_INIT) diff --git a/dts/bindings/input/pixart,pmw3610.yaml b/dts/bindings/input/pixart,pmw3610.yaml new file mode 100644 index 00000000000..d65d3715f95 --- /dev/null +++ b/dts/bindings/input/pixart,pmw3610.yaml @@ -0,0 +1,44 @@ +# Copyright 2024 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +description: PMW3610 Low Power Laser Mouse Sensor + +compatible: "pixart,pmw3610" + +include: spi-device.yaml + +properties: + motion-gpios: + type: phandle-array + required: true + description: + GPIO connected to the motion pin, active low. + + reset-gpios: + type: phandle-array + description: + GPIO connected to the reset pin, active low. + + zephyr,axis-x: + type: int + required: true + description: | + The input code for the X axis to report for the device, typically any of + INPUT_REL_*. No report produced for the device X axis if unspecified. + + zephyr,axis-y: + type: int + required: true + description: | + The input code for the Y axis to report for the device, typically any of + INPUT_REL_*. No report produced for the device Y axis if unspecified. + + invert-x: + type: boolean + description: | + Invert X axis values. + + invert-y: + type: boolean + description: | + Invert Y axis values. diff --git a/tests/drivers/build_all/input/app.overlay b/tests/drivers/build_all/input/app.overlay index 6cfaae7066b..5687406d4db 100644 --- a/tests/drivers/build_all/input/app.overlay +++ b/tests/drivers/build_all/input/app.overlay @@ -222,7 +222,8 @@ clock-frequency = <2000000>; /* one entry for every devices */ - cs-gpios = <&test_gpio 0 0>; + cs-gpios = <&test_gpio 0 0>, + <&test_gpio 0 0>; xpt2046@0 { compatible = "xptek,xpt2046"; @@ -236,6 +237,18 @@ max-x = <1>; max-y = <1>; }; + + pmw3610@1 { + compatible = "pixart,pmw3610"; + spi-max-frequency = <0>; + reg = <0x1>; + motion-gpios = <&test_gpio 0 0>; + reset-gpios = <&test_gpio 1 0>; + zephyr,axis-x = <0>; + zephyr,axis-y = <1>; + invert-x; + invert-y; + }; }; }; }; From 0702f0eb45c827472870af730b449b3017d298c1 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Mon, 5 Feb 2024 21:48:58 +0900 Subject: [PATCH 0220/2402] drivers: led_strip: ws2812_gpio: Rename in-gpios property to gpios ws2812-gpio's `in-gpios` property is not used as an input pin. Renaming it to `gpios` to reflect the actual situation. Signed-off-by: TOKITA Hiroshi --- doc/releases/migration-guide-3.7.rst | 6 ++++++ drivers/led_strip/ws2812_gpio.c | 10 +++++----- dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml | 2 +- samples/drivers/led_ws2812/boards/bbc_microbit.overlay | 2 +- .../drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay | 2 +- 5 files changed, 14 insertions(+), 8 deletions(-) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index d318a2eab1e..8eb11887bd5 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -95,6 +95,12 @@ Input Interrupt Controller ==================== +LED Strip +========= + +* The property ``in-gpios`` defined in :dtcompatible:`worldsemi,ws2812-gpio` has been + renamed to ``gpios``. + Sensors ======= diff --git a/drivers/led_strip/ws2812_gpio.c b/drivers/led_strip/ws2812_gpio.c index 478aed26f2e..bba534f1bbe 100644 --- a/drivers/led_strip/ws2812_gpio.c +++ b/drivers/led_strip/ws2812_gpio.c @@ -25,7 +25,7 @@ LOG_MODULE_REGISTER(ws2812_gpio); #include struct ws2812_gpio_cfg { - struct gpio_dt_spec in_gpio; + struct gpio_dt_spec gpio; uint8_t num_colors; const uint8_t *color_mapping; }; @@ -91,7 +91,7 @@ static int send_buf(const struct device *dev, uint8_t *buf, size_t len) { const struct ws2812_gpio_cfg *config = dev->config; volatile uint32_t *base = (uint32_t *)&NRF_GPIO->OUTSET; - const uint32_t val = BIT(config->in_gpio.pin); + const uint32_t val = BIT(config->gpio.pin); struct onoff_manager *mgr = z_nrf_clock_control_get_onoff(CLOCK_CONTROL_NRF_SUBSYS_HF); struct onoff_client cli; @@ -216,7 +216,7 @@ static const uint8_t ws2812_gpio_##idx##_color_mapping[] = \ const struct ws2812_gpio_cfg *cfg = dev->config; \ uint8_t i; \ \ - if (!gpio_is_ready_dt(&cfg->in_gpio)) { \ + if (!gpio_is_ready_dt(&cfg->gpio)) { \ LOG_ERR("GPIO device not ready"); \ return -ENODEV; \ } \ @@ -236,13 +236,13 @@ static const uint8_t ws2812_gpio_##idx##_color_mapping[] = \ } \ } \ \ - return gpio_pin_configure_dt(&cfg->in_gpio, GPIO_OUTPUT); \ + return gpio_pin_configure_dt(&cfg->gpio, GPIO_OUTPUT); \ } \ \ WS2812_COLOR_MAPPING(idx); \ \ static const struct ws2812_gpio_cfg ws2812_gpio_##idx##_cfg = { \ - .in_gpio = GPIO_DT_SPEC_INST_GET(idx, in_gpios), \ + .gpio = GPIO_DT_SPEC_INST_GET(idx, gpios), \ .num_colors = WS2812_NUM_COLORS(idx), \ .color_mapping = ws2812_gpio_##idx##_color_mapping, \ }; \ diff --git a/dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml b/dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml index b819a534f70..c69a63043be 100644 --- a/dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml +++ b/dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml @@ -14,7 +14,7 @@ compatible: "worldsemi,ws2812-gpio" include: [base.yaml, ws2812.yaml] properties: - in-gpios: + gpios: type: phandle-array required: true description: | diff --git a/samples/drivers/led_ws2812/boards/bbc_microbit.overlay b/samples/drivers/led_ws2812/boards/bbc_microbit.overlay index 29aee6629c3..84a36743600 100644 --- a/samples/drivers/led_ws2812/boards/bbc_microbit.overlay +++ b/samples/drivers/led_ws2812/boards/bbc_microbit.overlay @@ -16,7 +16,7 @@ LED_COLOR_ID_RED LED_COLOR_ID_BLUE>; /* P0: */ - in-gpios = <&gpio0 3 0>; + gpios = <&gpio0 3 0>; }; aliases { diff --git a/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay b/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay index 66906ee6af0..1109f498854 100644 --- a/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay +++ b/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay @@ -19,7 +19,7 @@ * Arduino D11 / P0.25, which was chosen to match the pin * used in nrf52dk_nrf52832.overlay. */ - in-gpios = <&gpio0 25 0>; + gpios = <&gpio0 25 0>; }; aliases { From 0f458c9564d76e9e077230dc321cbddb1e801cc9 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Mon, 5 Feb 2024 23:16:10 +0900 Subject: [PATCH 0221/2402] drivers: led_strip: ws2812_rpi_pico_pio: Change `output-pin` to `gpios` For sharing pin definition property with `worldsemi,ws2812-gpio`, rename `output-pin` to `gpios`. Signed-off-by: TOKITA Hiroshi --- boards/adafruit/kb2040/adafruit_kb2040.dts | 2 +- .../qt_py_rp2040/adafruit_qt_py_rp2040.dts | 2 +- drivers/led_strip/ws2812_rpi_pico_pio.c | 9 +++++---- dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml | 10 +--------- .../led_strip/worldsemi,ws2812-rpi_pico-pio.yaml | 10 ++++------ dts/bindings/led_strip/ws2812-gpio.yaml | 15 +++++++++++++++ 6 files changed, 27 insertions(+), 21 deletions(-) create mode 100644 dts/bindings/led_strip/ws2812-gpio.yaml diff --git a/boards/adafruit/kb2040/adafruit_kb2040.dts b/boards/adafruit/kb2040/adafruit_kb2040.dts index c17700aa8fa..45ff45595d2 100644 --- a/boards/adafruit/kb2040/adafruit_kb2040.dts +++ b/boards/adafruit/kb2040/adafruit_kb2040.dts @@ -108,7 +108,7 @@ ws2812: ws2812 { status = "okay"; - output-pin = <17>; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; chain-length = <1>; color-mapping = ; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; chain-length = <1>; color-mapping = #include #include #include @@ -21,7 +22,7 @@ struct ws2812_led_strip_data { struct ws2812_led_strip_config { const struct device *piodev; - uint32_t output_pin; + const uint8_t gpio_pin; uint8_t num_colors; uint32_t frequency; const uint8_t *const color_mapping; @@ -52,11 +53,11 @@ static int ws2812_led_strip_sm_init(const struct device *dev) } sm_config_set_sideset(&sm_config, 1, false, false); - sm_config_set_sideset_pins(&sm_config, config->output_pin); + sm_config_set_sideset_pins(&sm_config, config->gpio_pin); sm_config_set_out_shift(&sm_config, false, true, (config->num_colors == 4 ? 32 : 24)); sm_config_set_fifo_join(&sm_config, PIO_FIFO_JOIN_TX); sm_config_set_clkdiv(&sm_config, clkdiv); - pio_sm_set_consecutive_pindirs(pio, sm, config->output_pin, 1, true); + pio_sm_set_consecutive_pindirs(pio, sm, config->gpio_pin, 1, true); pio_sm_init(pio, sm, -1, &sm_config); pio_sm_set_enabled(pio, sm, true); @@ -187,7 +188,7 @@ static int ws2812_rpi_pico_pio_init(const struct device *dev) \ static const struct ws2812_led_strip_config ws2812_led_strip_##node##_config = { \ .piodev = DEVICE_DT_GET(DT_PARENT(DT_PARENT(node))), \ - .output_pin = DT_PROP(node, output_pin), \ + .gpio_pin = DT_GPIO_PIN_BY_IDX(node, gpios, 0), \ .num_colors = DT_PROP_LEN(node, color_mapping), \ .color_mapping = ws2812_led_strip_##node##_color_mapping, \ .reset_delay = DT_PROP(node, reset_delay), \ diff --git a/dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml b/dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml index c69a63043be..a759d5f6fe5 100644 --- a/dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml +++ b/dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml @@ -11,12 +11,4 @@ description: | compatible: "worldsemi,ws2812-gpio" -include: [base.yaml, ws2812.yaml] - -properties: - gpios: - type: phandle-array - required: true - description: | - GPIO phandle and specifier for the pin connected to the daisy - chain's input pin. Exactly one pin should be given. +include: [base.yaml, ws2812-gpio.yaml] diff --git a/dts/bindings/led_strip/worldsemi,ws2812-rpi_pico-pio.yaml b/dts/bindings/led_strip/worldsemi,ws2812-rpi_pico-pio.yaml index d5d41ed38ee..d0c8d38e63c 100644 --- a/dts/bindings/led_strip/worldsemi,ws2812-rpi_pico-pio.yaml +++ b/dts/bindings/led_strip/worldsemi,ws2812-rpi_pico-pio.yaml @@ -47,18 +47,16 @@ child-binding: Worldsemi WS2812 or compatible LED strip driver based on RaspberryPi Pico's PIO The LED strip node can put up to 4 instances under a single PIO node. - include: ws2812.yaml + include: ws2812-gpio.yaml properties: - output-pin: - type: int - required: true + gpios: description: | - Select the output pin. + Inherited from ws2812-gpio.yaml. Note: This driver does not configure the output pin. You need to configure the pin with pinctrl that is in the parent node configuration - for use by PIO. + for use by PIO. This property only uses the GPIO pin number and ignores flags. frequency: type: int diff --git a/dts/bindings/led_strip/ws2812-gpio.yaml b/dts/bindings/led_strip/ws2812-gpio.yaml new file mode 100644 index 00000000000..abfba22ddf0 --- /dev/null +++ b/dts/bindings/led_strip/ws2812-gpio.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024, TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +include: ws2812.yaml + +description: | + Common definition GPIO based WS2812 node + +properties: + gpios: + type: phandle-array + required: true + description: | + GPIO phandle and specifier for the pin connected to the + led-strip. Exactly one pin should be given. From 7e78df8c408d4a64bb281f4b19d9d030cb438c44 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Tue, 5 Mar 2024 11:05:43 +0900 Subject: [PATCH 0222/2402] samples: drivers: led_ws2812: Rename boards files to follow hwmv2 The esp32s3_devkitm and the nrf5340dk_nrf5340 only have ws2812 in each configurations that is procpu and cpuapp respectively. Rename overlay and conf files to avoid building with unnecessary configurations. Signed-off-by: TOKITA Hiroshi --- .../{esp32s3_devkitm.conf => esp32s3_devkitm_esp32s3_procpu.conf} | 0 ...2s3_devkitm.overlay => esp32s3_devkitm_esp32s3_procpu.overlay} | 0 .../{nrf5340dk_nrf5340.conf => nrf5340dk_nrf5340_cpuapp.conf} | 0 ...nrf5340dk_nrf5340.overlay => nrf5340dk_nrf5340_cpuapp.overlay} | 0 4 files changed, 0 insertions(+), 0 deletions(-) rename samples/drivers/led_ws2812/boards/{esp32s3_devkitm.conf => esp32s3_devkitm_esp32s3_procpu.conf} (100%) rename samples/drivers/led_ws2812/boards/{esp32s3_devkitm.overlay => esp32s3_devkitm_esp32s3_procpu.overlay} (100%) rename samples/drivers/led_ws2812/boards/{nrf5340dk_nrf5340.conf => nrf5340dk_nrf5340_cpuapp.conf} (100%) rename samples/drivers/led_ws2812/boards/{nrf5340dk_nrf5340.overlay => nrf5340dk_nrf5340_cpuapp.overlay} (100%) diff --git a/samples/drivers/led_ws2812/boards/esp32s3_devkitm.conf b/samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.conf similarity index 100% rename from samples/drivers/led_ws2812/boards/esp32s3_devkitm.conf rename to samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.conf diff --git a/samples/drivers/led_ws2812/boards/esp32s3_devkitm.overlay b/samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/esp32s3_devkitm.overlay rename to samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.overlay diff --git a/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340.conf b/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.conf similarity index 100% rename from samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340.conf rename to samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.conf diff --git a/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340.overlay b/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340.overlay rename to samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.overlay From 4440d6a189b83d681568dd40e87d55e0925abf67 Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Thu, 15 Feb 2024 20:31:50 -0800 Subject: [PATCH 0223/2402] kernel/userspace: Fix dynamic thread stack allocation at userspace It wasn't saving adjusted stack size at either the private stack or the k_object, thus failing subsequent checks. Test added to check for this case and prevent regressions. Signed-off-by: Ederson de Souza --- kernel/userspace.c | 2 ++ .../threads/dynamic_thread_stack/prj.conf | 2 ++ .../threads/dynamic_thread_stack/src/main.c | 36 +++++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/kernel/userspace.c b/kernel/userspace.c index 1eaf1a0e306..ecdc1348d09 100644 --- a/kernel/userspace.c +++ b/kernel/userspace.c @@ -341,6 +341,7 @@ static struct k_object *dynamic_object_create(enum k_objects otype, size_t align struct z_stack_data *stack_data = (struct z_stack_data *) ((uint8_t *)dyn->data + adjusted_size - sizeof(*stack_data)); stack_data->priv = (uint8_t *)dyn->data; + stack_data->size = adjusted_size; dyn->kobj.data.stack_data = stack_data; #if defined(CONFIG_ARM_MPU) || defined(CONFIG_ARC_MPU) dyn->kobj.name = (void *)ROUND_UP( @@ -351,6 +352,7 @@ static struct k_object *dynamic_object_create(enum k_objects otype, size_t align #endif #else dyn->kobj.name = dyn->data; + dyn->kobj.data.stack_size = adjusted_size; #endif } else { dyn->data = z_thread_aligned_alloc(align, obj_size_get(otype) + size); diff --git a/tests/kernel/threads/dynamic_thread_stack/prj.conf b/tests/kernel/threads/dynamic_thread_stack/prj.conf index 93c54a25347..1f31fc34e79 100644 --- a/tests/kernel/threads/dynamic_thread_stack/prj.conf +++ b/tests/kernel/threads/dynamic_thread_stack/prj.conf @@ -10,3 +10,5 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_HW_STACK_PROTECTION=n CONFIG_TEST_HW_STACK_PROTECTION=n + +CONFIG_DYNAMIC_OBJECTS=y diff --git a/tests/kernel/threads/dynamic_thread_stack/src/main.c b/tests/kernel/threads/dynamic_thread_stack/src/main.c index e53a6973962..1e93beb3c66 100644 --- a/tests/kernel/threads/dynamic_thread_stack/src/main.c +++ b/tests/kernel/threads/dynamic_thread_stack/src/main.c @@ -35,6 +35,42 @@ static void func(void *arg1, void *arg2, void *arg3) *flag = true; } +/** @brief Check we can create a thread from userspace, using dynamic objects */ +ZTEST_USER(dynamic_thread_stack, test_dynamic_thread_stack_userspace_dyn_obj) +{ + k_tid_t tid; + struct k_thread *th; + k_thread_stack_t *stack; + + if (!IS_ENABLED(CONFIG_USERSPACE)) { + ztest_test_skip(); + } + + if (!IS_ENABLED(CONFIG_DYNAMIC_THREAD_PREFER_ALLOC)) { + ztest_test_skip(); + } + + if (!IS_ENABLED(CONFIG_DYNAMIC_THREAD_ALLOC)) { + ztest_test_skip(); + } + + stack = k_thread_stack_alloc(CONFIG_DYNAMIC_THREAD_STACK_SIZE, K_USER); + zassert_not_null(stack); + + th = k_object_alloc(K_OBJ_THREAD); + zassert_not_null(th); + + tid = k_thread_create(th, stack, CONFIG_DYNAMIC_THREAD_STACK_SIZE, func, + &tflag[0], NULL, NULL, 0, + K_USER | K_INHERIT_PERMS, K_NO_WAIT); + + zassert_not_null(tid); + + zassert_ok(k_thread_join(tid, K_MSEC(TIMEOUT_MS))); + zassert_true(tflag[0]); + zassert_ok(k_thread_stack_free(stack)); +} + /** @brief Exercise the pool-based thread stack allocator */ ZTEST(dynamic_thread_stack, test_dynamic_thread_stack_pool) { From 5e1ce7e0f79f12bda6b1ec3c180a6fcb26fa37ea Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 4 Mar 2024 13:16:27 +0100 Subject: [PATCH 0224/2402] drivers: can: minor improvements to internal timing calculation code Improve the internal CAN timing calculation code readability by unifying variable and function naming, avoiding unnecessary casting, and rewording comments. Signed-off-by: Henrik Brix Andersen --- drivers/can/can_common.c | 111 +++++++++++++++++++++------------------ 1 file changed, 60 insertions(+), 51 deletions(-) diff --git a/drivers/can/can_common.c b/drivers/can/can_common.c index 6541c977255..a301e896dd2 100644 --- a/drivers/can/can_common.c +++ b/drivers/can/can_common.c @@ -97,16 +97,15 @@ int z_impl_can_add_rx_filter_msgq(const struct device *dev, struct k_msgq *msgq, * @see @a can_timing * * @param total_tq Total number of time quanta. - * @param sample_pnt Sampling point in permill of the entire bit time. + * @param sample_pnt Sample point in permille of the entire bit time. * @param[out] res Result is written into the @a can_timing struct provided. - * @param max Maximum timing parameters values. - * @param min Minimum timing parameters values. - * @return Absolute sample point error. + * @param min Pointer to the minimum supported timing parameter values. + * @param max Pointer to the maximum supported timing parameter values. + * @retval 0 or positive sample point error on success. + * @retval -ENOTSUP if the requested sample point cannot be met. */ -static int update_sampling_pnt(uint32_t total_tq, uint32_t sample_pnt, - struct can_timing *res, - const struct can_timing *max, - const struct can_timing *min) +static int update_sample_pnt(uint32_t total_tq, uint32_t sample_pnt, struct can_timing *res, + const struct can_timing *min, const struct can_timing *max) { uint16_t tseg1_max = max->phase_seg1 + max->prop_seg; uint16_t tseg1_min = min->phase_seg1 + min->prop_seg; @@ -123,15 +122,17 @@ static int update_sampling_pnt(uint32_t total_tq, uint32_t sample_pnt, /* Sample point location must be decreased */ tseg1 = tseg1_max; tseg2 = total_tq - CAN_SYNC_SEG - tseg1; + if (tseg2 > max->phase_seg2) { - return -1; + return -ENOTSUP; } } else if (tseg1 < tseg1_min) { /* Sample point location must be increased */ tseg1 = tseg1_min; tseg2 = total_tq - CAN_SYNC_SEG - tseg1; + if (tseg2 < min->phase_seg2) { - return -1; + return -ENOTSUP; } } @@ -160,60 +161,82 @@ static int update_sampling_pnt(uint32_t total_tq, uint32_t sample_pnt, sample_pnt - sample_pnt_res; } -/* Internal function to do the actual calculation */ -static int can_calc_timing_int(uint32_t core_clock, struct can_timing *res, - const struct can_timing *min, - const struct can_timing *max, - uint32_t bitrate, uint16_t sp) +/** + * @brief Internal function for calculating CAN timing parameters. + * + * @param dev Pointer to the device structure for the driver instance. + * @param[out] res Result is written into the @a can_timing struct provided. + * @param min Pointer to the minimum supported timing parameter values. + * @param max Pointer to the maximum supported timing parameter values. + * @param bitrate Target bitrate in bits/s. + * @param sample_pnt Sample point in permille of the entire bit time. + * + * @retval 0 or positive sample point error on success. + * @retval -EINVAL if the requested bitrate or sample point is out of range. + * @retval -ENOTSUP if the requested bitrate is not supported. + * @retval -EIO if @a can_get_core_clock() is not available. + */ +static int can_calc_timing_internal(const struct device *dev, struct can_timing *res, + const struct can_timing *min, const struct can_timing *max, + uint32_t bitrate, uint16_t sample_pnt) { - uint32_t ts = max->prop_seg + max->phase_seg1 + max->phase_seg2 + - CAN_SYNC_SEG; - uint16_t sp_err_min = UINT16_MAX; - int sp_err; + uint32_t total_tq = CAN_SYNC_SEG + max->prop_seg + max->phase_seg1 + max->phase_seg2; struct can_timing tmp_res = { 0 }; + int err_min = INT_MAX; + uint32_t core_clock; + int prescaler; + int err; - if (bitrate == 0 || sp >= 1000) { + if (bitrate == 0 || sample_pnt >= 1000) { return -EINVAL; } - for (int prescaler = MAX(core_clock / (ts * bitrate), 1); - prescaler <= max->prescaler; ++prescaler) { + err = can_get_core_clock(dev, &core_clock); + if (err != 0) { + return -EIO; + } + + for (prescaler = MAX(core_clock / (total_tq * bitrate), 1); + prescaler <= max->prescaler; + prescaler++) { + if (core_clock % (prescaler * bitrate)) { - /* No integer ts */ + /* No integer total_tq for this prescaler setting */ continue; } - ts = core_clock / (prescaler * bitrate); + total_tq = core_clock / (prescaler * bitrate); - sp_err = update_sampling_pnt(ts, sp, &tmp_res, - max, min); - if (sp_err < 0) { - /* No prop_seg, seg1, seg2 combination possible */ + err = update_sample_pnt(total_tq, sample_pnt, &tmp_res, min, max); + if (err < 0) { + /* Sample point cannot be met for this prescaler setting */ continue; } - if (sp_err < sp_err_min) { - sp_err_min = sp_err; + if (err < err_min) { + /* Improved sample point match */ + err_min = err; res->prop_seg = tmp_res.prop_seg; res->phase_seg1 = tmp_res.phase_seg1; res->phase_seg2 = tmp_res.phase_seg2; res->prescaler = (uint16_t)prescaler; - if (sp_err == 0) { - /* No better result than a perfect match*/ + + if (err == 0) { + /* Perfect sample point match */ break; } } } - if (sp_err_min) { - LOG_DBG("SP error: %d 1/1000", sp_err_min); + if (err_min != 0U) { + LOG_DBG("Sample point error: %d 1/1000", err_min); } /* Calculate default sjw as phase_seg2 / 2 and clamp the result */ res->sjw = MIN(res->phase_seg1, res->phase_seg2 / 2); res->sjw = CLAMP(res->sjw, min->sjw, max->sjw); - return sp_err_min == UINT16_MAX ? -ENOTSUP : (int)sp_err_min; + return err_min == INT_MAX ? -ENOTSUP : err_min; } int z_impl_can_calc_timing(const struct device *dev, struct can_timing *res, @@ -221,19 +244,12 @@ int z_impl_can_calc_timing(const struct device *dev, struct can_timing *res, { const struct can_timing *min = can_get_timing_min(dev); const struct can_timing *max = can_get_timing_max(dev); - uint32_t core_clock; - int ret; if (bitrate > 1000000) { return -EINVAL; } - ret = can_get_core_clock(dev, &core_clock); - if (ret != 0) { - return ret; - } - - return can_calc_timing_int(core_clock, res, min, max, bitrate, sample_pnt); + return can_calc_timing_internal(dev, res, min, max, bitrate, sample_pnt); } #ifdef CONFIG_CAN_FD_MODE @@ -242,19 +258,12 @@ int z_impl_can_calc_timing_data(const struct device *dev, struct can_timing *res { const struct can_timing *min = can_get_timing_data_min(dev); const struct can_timing *max = can_get_timing_data_max(dev); - uint32_t core_clock; - int ret; if (bitrate > 8000000) { return -EINVAL; } - ret = can_get_core_clock(dev, &core_clock); - if (ret != 0) { - return ret; - } - - return can_calc_timing_int(core_clock, res, min, max, bitrate, sample_pnt); + return can_calc_timing_internal(dev, res, min, max, bitrate, sample_pnt); } #endif /* CONFIG_CAN_FD_MODE */ From 68f4f12c1b84339e0d21e38fb421fa8c26c303f8 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 4 Mar 2024 13:24:02 +0100 Subject: [PATCH 0225/2402] drivers: can: respect minimum supported prescaler value Respect the minimum supported prescaler value when calculating CAN timing. Signed-off-by: Henrik Brix Andersen --- drivers/can/can_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/can/can_common.c b/drivers/can/can_common.c index a301e896dd2..51e3e1ec651 100644 --- a/drivers/can/can_common.c +++ b/drivers/can/can_common.c @@ -196,7 +196,7 @@ static int can_calc_timing_internal(const struct device *dev, struct can_timing return -EIO; } - for (prescaler = MAX(core_clock / (total_tq * bitrate), 1); + for (prescaler = MAX(core_clock / (total_tq * bitrate), min->prescaler); prescaler <= max->prescaler; prescaler++) { From 99fd397147e99ab8921cdf209a83d795028565e3 Mon Sep 17 00:00:00 2001 From: Armin Brauns Date: Wed, 6 Mar 2024 08:06:25 +0000 Subject: [PATCH 0226/2402] scripts/check_compliance: pass --no-ext-diff to git diff If $GIT_EXTERNAL_DIFF is set, this difftool is used instead of the default internal unified diff, which breaks the Checkpatch check. Signed-off-by: Armin Brauns --- scripts/ci/check_compliance.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index dcad0ca51b9..88ab9b32b91 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -202,7 +202,7 @@ def run(self): if not os.path.exists(checkpatch): self.skip(f'{checkpatch} not found') - diff = subprocess.Popen(('git', 'diff', COMMIT_RANGE), + diff = subprocess.Popen(('git', 'diff', '--no-ext-diff', COMMIT_RANGE), stdout=subprocess.PIPE, cwd=GIT_TOP) try: From 4d97dcf115697d96683547a2e860bb367fa83606 Mon Sep 17 00:00:00 2001 From: Dawid Niedzwiecki Date: Wed, 28 Feb 2024 12:33:00 +0100 Subject: [PATCH 0227/2402] ec_host_cmd: introduce Host Command state Introduce a current state of Host Command subsystem. It makes sures that a backend has been initilized and doesn't allow sending a response twice. There is a possibility, that a command handler that calls ec_host_cmd_send_response function returns anyway (which is a mistake). Signed-off-by: Dawid Niedzwiecki --- include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h | 8 ++++++++ subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c | 12 ++++++++++++ 2 files changed, 20 insertions(+) diff --git a/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h b/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h index cc0127938e3..50bc3fb7780 100644 --- a/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h +++ b/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h @@ -78,6 +78,13 @@ enum ec_host_cmd_log_level { EC_HOST_CMD_DEBUG_MODES /* Number of host command debug modes */ }; +enum ec_host_cmd_state { + EC_HOST_CMD_STATE_DISABLED = 0, + EC_HOST_CMD_STATE_RECEIVING, + EC_HOST_CMD_STATE_PROCESSING, + EC_HOST_CMD_STATE_SENDING, +}; + typedef void (*ec_host_cmd_user_cb_t)(const struct ec_host_cmd_rx_ctx *rx_ctx, void *user_data); typedef enum ec_host_cmd_status (*ec_host_cmd_in_progress_cb_t)(void *user_data); @@ -98,6 +105,7 @@ struct ec_host_cmd { */ ec_host_cmd_user_cb_t user_cb; void *user_data; + enum ec_host_cmd_state state; #ifdef CONFIG_EC_HOST_CMD_DEDICATED_THREAD struct k_thread thread; #endif /* CONFIG_EC_HOST_CMD_DEDICATED_THREAD */ diff --git a/subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c b/subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c index b628c891a5b..265c5bc854c 100644 --- a/subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c +++ b/subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c @@ -292,6 +292,12 @@ int ec_host_cmd_send_response(enum ec_host_cmd_status status, struct ec_host_cmd *hc = &ec_host_cmd; struct ec_host_cmd_tx_buf *tx = &hc->tx; + if (hc->state != EC_HOST_CMD_STATE_PROCESSING) { + LOG_ERR("Unexpected state while sending"); + return -ENOTSUP; + } + hc->state = EC_HOST_CMD_STATE_SENDING; + if (status != EC_HOST_CMD_SUCCESS) { const struct ec_host_cmd_request_header *const rx_header = (const struct ec_host_cmd_request_header *const)hc->rx_ctx.buf; @@ -390,9 +396,13 @@ FUNC_NORETURN static void ec_host_cmd_thread(void *hc_handle, void *arg2, void * .reserved = NULL, }; + __ASSERT(hc->state != EC_HOST_CMD_STATE_DISABLED, "HC backend not initialized"); + while (1) { + hc->state = EC_HOST_CMD_STATE_RECEIVING; /* Wait until RX messages is received on host interface */ k_sem_take(&hc->rx_ready, K_FOREVER); + hc->state = EC_HOST_CMD_STATE_PROCESSING; ec_host_cmd_log_request(rx->buf); @@ -485,6 +495,8 @@ int ec_host_cmd_init(struct ec_host_cmd_backend *backend) return -EIO; } + hc->state = EC_HOST_CMD_STATE_RECEIVING; + /* Check if a backend uses provided buffers. The buffer pointers can be shifted within the * buffer to make space for preamble. Make sure the rx/tx pointers are within the provided * buffers ranges. From c00bd4a8d5b43aa2bc39609627e7d9e87cf86271 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Wed, 7 Feb 2024 07:17:21 +0900 Subject: [PATCH 0228/2402] boards: arm: rpi_pico: Add default serial for connector definition Add `pico_serial` which is alias of `uart0` as a definition related to pico_header. The uart0(GP0 and GP1) is shown as default serial port in pinout diaglam. Signed-off-by: TOKITA Hiroshi --- boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi index 9c7f1da1817..36058ef6483 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi +++ b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi @@ -163,3 +163,4 @@ zephyr_udc0: &usbd { pico_spi: &spi0 {}; pico_i2c0: &i2c0 {}; pico_i2c1: &i2c1 {}; +pico_serial: &uart0 {}; From abdfc4b1fee94b5d9dd5dc2ea0f13766f83bf451 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Fri, 23 Feb 2024 11:26:59 +0100 Subject: [PATCH 0229/2402] logging: support using real time as timestamp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds a option to use real time from posix instant of the system uptime as the logging timestamp. Signed-off-by: Fin Maaß --- subsys/logging/Kconfig.processing | 7 +++++++ subsys/logging/log_core.c | 19 +++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/subsys/logging/Kconfig.processing b/subsys/logging/Kconfig.processing index bc553aa239c..3cf9259c96d 100644 --- a/subsys/logging/Kconfig.processing +++ b/subsys/logging/Kconfig.processing @@ -158,6 +158,13 @@ config LOG_TRACE_SHORT_TIMESTAMP config LOG_TIMESTAMP_64BIT bool "Use 64 bit timestamp" +config LOG_TIMESTAMP_USE_REALTIME + bool "Use real time clock for timestamp" + select LOG_TIMESTAMP_64BIT + depends on POSIX_CLOCK + help + When enabled, real time clock is used for timestamping. + config LOG_SPEED bool "Prefer performance over size" depends on LOG_MODE_DEFERRED diff --git a/subsys/logging/log_core.c b/subsys/logging/log_core.c index 3a2e397a603..b4b6152806c 100644 --- a/subsys/logging/log_core.c +++ b/subsys/logging/log_core.c @@ -23,6 +23,10 @@ #include #include +#ifdef CONFIG_LOG_TIMESTAMP_USE_REALTIME +#include +#endif + LOG_MODULE_REGISTER(log); #ifndef CONFIG_LOG_PROCESS_THREAD_SLEEP_MS @@ -221,6 +225,7 @@ void z_log_vprintk(const char *fmt, va_list ap) fmt, ap); } +#ifndef CONFIG_LOG_TIMESTAMP_USE_REALTIME static log_timestamp_t default_get_timestamp(void) { return IS_ENABLED(CONFIG_LOG_TIMESTAMP_64BIT) ? @@ -232,6 +237,16 @@ static log_timestamp_t default_lf_get_timestamp(void) return IS_ENABLED(CONFIG_LOG_TIMESTAMP_64BIT) ? k_uptime_get() : k_uptime_get_32(); } +#else +static log_timestamp_t default_rt_get_timestamp(void) +{ + struct timespec tspec; + + clock_gettime(CLOCK_REALTIME, &tspec); + + return ((uint64_t)tspec.tv_sec * MSEC_PER_SEC) + (tspec.tv_nsec / NSEC_PER_MSEC); +} +#endif /* CONFIG_LOG_TIMESTAMP_USE_REALTIME */ void log_core_init(void) { @@ -252,6 +267,9 @@ void log_core_init(void) } /* Set default timestamp. */ +#ifdef CONFIG_LOG_TIMESTAMP_USE_REALTIME + log_set_timestamp_func(default_rt_get_timestamp, 1000U); +#else if (sys_clock_hw_cycles_per_sec() > 1000000) { log_set_timestamp_func(default_lf_get_timestamp, 1000U); } else { @@ -259,6 +277,7 @@ void log_core_init(void) CONFIG_SYS_CLOCK_TICKS_PER_SEC : sys_clock_hw_cycles_per_sec(); log_set_timestamp_func(default_get_timestamp, freq); } +#endif /* CONFIG_LOG_TIMESTAMP_USE_REALTIME */ if (IS_ENABLED(CONFIG_LOG_MODE_DEFERRED)) { z_log_msg_init(); From 8f458bb51f1f3b47fbde4f8730687275dcee8a21 Mon Sep 17 00:00:00 2001 From: Ivan Iushkov Date: Mon, 4 Mar 2024 15:35:01 +0100 Subject: [PATCH 0230/2402] modules: crypto: update tinycrypt revision update tinycrypt revision to fix warnings reported by ubsan Signed-off-by: Ivan Iushkov --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index e998c77b090..0f8402dadcf 100644 --- a/west.yml +++ b/west.yml @@ -317,7 +317,7 @@ manifest: groups: - debug - name: tinycrypt - revision: 3e9a49d2672ec01435ffbf0d788db6d95ef28de0 + revision: 1012a3ebee18c15ede5efc8332ee2fc37817670f path: modules/crypto/tinycrypt groups: - crypto From 47db2e050edc960aa348b802aced9053fb1c7842 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 27 Feb 2024 11:44:52 +0200 Subject: [PATCH 0231/2402] doc: migration-guide-3.7: Add IPv4 netmask information The IPv4 netmask handling is changed and it might need adjustments from user if using more than one IPv4 address inside one specific network interface. Signed-off-by: Jukka Rissanen --- doc/releases/migration-guide-3.7.rst | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index 8eb11887bd5..73f96a432ae 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -127,6 +127,13 @@ Networking the long-duration zperf test show with correct throughput result. (:github:`69500`) +* Each IPv4 address assigned to a network interface has an IPv4 netmask + tied to it instead of being set for the whole interface. + If there is only one IPv4 address specified for a network interface, + nothing changes from the user point of view. But, if there is more than + one IPv4 address / network interface, the netmask must be specified + for each IPv4 address separately. (:github:`68419`) + Other Subsystems **************** From a487addc615d6b28fb4b106fb5407eed42c5c214 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Wed, 6 Mar 2024 10:24:57 +0100 Subject: [PATCH 0232/2402] sys: Include sys/util.h header in sys/atomic.h Commit a1358aaedf0d10d5c105a7b0d79e48f16be6cacf introduced ROUND_UP macro use within sys/atomic.h header, but did not include the header (sys/util.h) which actually defines the macro. This commit fixes it. Signed-off-by: Robert Lubos --- include/zephyr/sys/atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/sys/atomic.h b/include/zephyr/sys/atomic.h index 3982e428038..86ba2cdf144 100644 --- a/include/zephyr/sys/atomic.h +++ b/include/zephyr/sys/atomic.h @@ -15,7 +15,7 @@ #include /* IWYU pragma: export */ #include -#include +#include #ifdef __cplusplus extern "C" { From 5f844f5252c9a15b25430c1906fe2256b8285c23 Mon Sep 17 00:00:00 2001 From: Armin Brauns Date: Wed, 6 Mar 2024 13:46:48 +0000 Subject: [PATCH 0233/2402] include: disk.h: make name field in struct disk_info const This isn't modified anywhere, which is good, because it is typically initialized with a string literal, which would likely blow up if you tried. Signed-off-by: Armin Brauns --- include/zephyr/drivers/disk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/drivers/disk.h b/include/zephyr/drivers/disk.h index e12e15345b6..ffa22a9071f 100644 --- a/include/zephyr/drivers/disk.h +++ b/include/zephyr/drivers/disk.h @@ -70,7 +70,7 @@ struct disk_info { /** Internally used list node */ sys_dnode_t node; /** Disk name */ - char *name; + const char *name; /** Disk operations */ const struct disk_operations *ops; /** Device associated to this disk */ From c6a01e73428aa998c3d3492feeb16f9cf06b8605 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Wed, 6 Mar 2024 08:36:52 -0500 Subject: [PATCH 0234/2402] tests: xtensa: fix test identifier start with arch. Signed-off-by: Anas Nashif --- tests/arch/xtensa/save_restore_hifi/testcase.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/arch/xtensa/save_restore_hifi/testcase.yaml b/tests/arch/xtensa/save_restore_hifi/testcase.yaml index 1e84e5649b7..3f44e0b3e88 100644 --- a/tests/arch/xtensa/save_restore_hifi/testcase.yaml +++ b/tests/arch/xtensa/save_restore_hifi/testcase.yaml @@ -1,6 +1,7 @@ tests: - xtensa.save_restore_hifi.mtl: - platform_allow: intel_adsp/ace15_mtpm + arch.xtensa.save_restore_hifi.mtl: + platform_allow: + - intel_adsp/ace15_mtpm tags: - kernel ignore_faults: true From b2cfdc41d2cc95b52749839b5388cf5df9394504 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Wed, 6 Mar 2024 09:19:36 -0500 Subject: [PATCH 0235/2402] MAINTAINERS: add xtensa tests to area Add xtensa arch tests to respective area. Signed-off-by: Anas Nashif --- MAINTAINERS.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 70899291f67..2e7caf8b8ea 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -4608,6 +4608,7 @@ Xtensa arch: - soc/cdns/dc233c/ - soc/cdns/dc233c/ - soc/cdns/xtensa_sample_controller/ + - tests/arch/xtensa/ labels: - "area: Xtensa" From 49653d39dd2ebb0ba6c49b7c64b98c3a5825886c Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 4 Mar 2024 21:54:59 +0100 Subject: [PATCH 0236/2402] drivers: can: extend support for automatic sample point location Extend support for automatic sample point location to also cover can_calc_timing() and can_calc_timing_data(). Previously, automatic sample point location was only supported by can_set_bitrate() and can_set_bitrate_data(). Signed-off-by: Henrik Brix Andersen --- drivers/can/can_common.c | 52 +++++++++++++++++++----------------- include/zephyr/drivers/can.h | 10 +++++-- 2 files changed, 36 insertions(+), 26 deletions(-) diff --git a/drivers/can/can_common.c b/drivers/can/can_common.c index 51e3e1ec651..21df3a3b55e 100644 --- a/drivers/can/can_common.c +++ b/drivers/can/can_common.c @@ -161,6 +161,30 @@ static int update_sample_pnt(uint32_t total_tq, uint32_t sample_pnt, struct can_ sample_pnt - sample_pnt_res; } +/** + * @brief Get the sample point location for a given bitrate + * + * @param bitrate The bitrate in bits/second. + * @return The sample point in permille. + */ +static uint16_t sample_point_for_bitrate(uint32_t bitrate) +{ + uint16_t sample_pnt; + + if (bitrate > 800000) { + /* 75.0% */ + sample_pnt = 750; + } else if (bitrate > 500000) { + /* 80.0% */ + sample_pnt = 800; + } else { + /* 87.5% */ + sample_pnt = 875; + } + + return sample_pnt; +} + /** * @brief Internal function for calculating CAN timing parameters. * @@ -196,6 +220,10 @@ static int can_calc_timing_internal(const struct device *dev, struct can_timing return -EIO; } + if (sample_pnt == 0U) { + sample_pnt = sample_point_for_bitrate(bitrate); + } + for (prescaler = MAX(core_clock / (total_tq * bitrate), min->prescaler); prescaler <= max->prescaler; prescaler++) { @@ -285,30 +313,6 @@ int can_calc_prescaler(const struct device *dev, struct can_timing *timing, return core_clock % (ts * timing->prescaler); } -/** - * @brief Get the sample point location for a given bitrate - * - * @param bitrate The bitrate in bits/second. - * @return The sample point in permille. - */ -static uint16_t sample_point_for_bitrate(uint32_t bitrate) -{ - uint16_t sample_pnt; - - if (bitrate > 800000) { - /* 75.0% */ - sample_pnt = 750; - } else if (bitrate > 500000) { - /* 80.0% */ - sample_pnt = 800; - } else { - /* 87.5% */ - sample_pnt = 875; - } - - return sample_pnt; -} - static int check_timing_in_range(const struct can_timing *timing, const struct can_timing *min, const struct can_timing *max) diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index 37546cd484f..71369d254ba 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -871,13 +871,18 @@ static inline const struct can_timing *z_impl_can_get_timing_max(const struct de * always match perfectly. If no result can be reached for the given parameters, * -EINVAL is returned. * + * If the sample point is set to 0, this function defaults to a sample point of 75.0% + * for bitrates over 800 kbit/s, 80.0% for bitrates over 500 kbit/s, and 87.5% for + * all other bitrates. + * * @note The requested ``sample_pnt`` will not always be matched perfectly. The * algorithm calculates the best possible match. * * @param dev Pointer to the device structure for the driver instance. * @param[out] res Result is written into the @a can_timing struct provided. * @param bitrate Target bitrate in bits/s. - * @param sample_pnt Sampling point in permill of the entire bit time. + * @param sample_pnt Sample point in permille of the entire bit time or 0 for + * automatic sample point location. * * @retval 0 or positive sample point error on success. * @retval -EINVAL if the requested bitrate or sample point is out of range. @@ -947,7 +952,8 @@ static inline const struct can_timing *z_impl_can_get_timing_data_max(const stru * @param dev Pointer to the device structure for the driver instance. * @param[out] res Result is written into the @a can_timing struct provided. * @param bitrate Target bitrate for the data phase in bits/s - * @param sample_pnt Sampling point for the data phase in permille of the entire bit time. + * @param sample_pnt Sample point for the data phase in permille of the entire bit + * time or 0 for automatic sample point location. * * @retval 0 or positive sample point error on success. * @retval -EINVAL if the requested bitrate or sample point is out of range. From 7987d802e30314eff32d485ccd90603d83b36e30 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 4 Mar 2024 21:58:38 +0100 Subject: [PATCH 0237/2402] doc: releases: release-notes: 3.7: mention automatic CAN sample points Add a note on the extended support for automatic CAN sample point location. Signed-off-by: Henrik Brix Andersen --- doc/releases/release-notes-3.7.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index 5d337fbbdf9..ac32db3e9b3 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -75,6 +75,8 @@ Drivers and Sensors * Deprecated the :c:func:`can_calc_prescaler` API function, as it allows for bitrate errors. Bitrate errors between nodes on the same network leads to them drifting apart after the start-of-frame (SOF) synchronization has taken place, leading to bus errors. + * Extended support for automatic sample point location to also cover :c:func:`can_calc_timing` and + :c:func:`can_calc_timing_data`. * Clock control From 0db120abd40cd2f9df3715f958efa21eb7549ec3 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Wed, 6 Mar 2024 10:22:06 +0100 Subject: [PATCH 0238/2402] net: lib: shell: iface: Fix when building ethernet without IP support The count stack variable is also used when CONFIG_NET_L2_ETHERNET_MGMT is enabled. Make sure it is available. Signed-off-by: Pieter De Gendt --- subsys/net/lib/shell/iface.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/lib/shell/iface.c b/subsys/net/lib/shell/iface.c index 5a31c6e8d59..7301cadaced 100644 --- a/subsys/net/lib/shell/iface.c +++ b/subsys/net/lib/shell/iface.c @@ -148,7 +148,7 @@ static void iface_cb(struct net_if *iface, void *user_data) int ret; #endif const char *extra; -#if defined(CONFIG_NET_IP) +#if defined(CONFIG_NET_IP) || defined(CONFIG_NET_L2_ETHERNET_MGMT) int count; #endif From 7c19bc70bff6f03b4c0919f9a73265e50d7fe192 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Dec 2023 18:34:29 +0900 Subject: [PATCH 0239/2402] ci: twister: Use zephyr-runner v2 This commit updates the twister workflow to use the new zephyr-runner v2 CI runner deployment. It also updates the workflow to use the `ci-repo-cache` Docker image, which includes the Zephyr repository cache, because the node level repository cache is no longer available in the zephyr-runner v2. Signed-off-by: Stephanos Ioannidis --- .github/workflows/twister.yaml | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index bab41552887..41434d77f61 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -22,12 +22,11 @@ concurrency: jobs: twister-build-prep: if: github.repository_owner == 'zephyrproject-rtos' - runs-on: zephyr-runner-linux-x64-4xlarge + runs-on: + group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.7 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 options: '--entrypoint /bin/bash' - volumes: - - /repo-cache/zephyrproject:/github/cache/zephyrproject outputs: subset: ${{ steps.output-services.outputs.subset }} size: ${{ steps.output-services.outputs.size }} @@ -54,7 +53,7 @@ jobs: if: github.event_name == 'pull_request_target' continue-on-error: true run: | - git clone --shared /github/cache/zephyrproject/zephyr . + git clone --shared /repo-cache/zephyrproject/zephyr . git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout @@ -76,7 +75,7 @@ jobs: west init -l . || true west config manifest.group-filter -- +ci,+optional west config --global update.narrow true - west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /github/cache/zephyrproject) + west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject) west forall -c 'git reset --hard HEAD' echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV @@ -119,14 +118,13 @@ jobs: echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT twister-build: - runs-on: zephyr-runner-linux-x64-4xlarge + runs-on: + group: zephyr-runner-v2-linux-x64-4xlarge needs: twister-build-prep if: needs.twister-build-prep.outputs.size != 0 container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.7 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 options: '--entrypoint /bin/bash' - volumes: - - /repo-cache/zephyrproject:/github/cache/zephyrproject strategy: fail-fast: false matrix: @@ -152,7 +150,7 @@ jobs: - name: Clone cached Zephyr repository continue-on-error: true run: | - git clone --shared /github/cache/zephyrproject/zephyr . + git clone --shared /repo-cache/zephyrproject/zephyr . git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout @@ -176,15 +174,9 @@ jobs: west init -l . || true west config manifest.group-filter -- +ci,+optional west config --global update.narrow true - west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /github/cache/zephyrproject) + west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject) west forall -c 'git reset --hard HEAD' - # Hotfix until we have kitware ninja in the docker image. - # Needed for full functionality of the job server functionality in twister which only works with - # kitware supplied ninja version. - wget -c https://github.com/Kitware/ninja/releases/download/v1.11.1.g95dee.kitware.jobserver-1/ninja-1.11.1.g95dee.kitware.jobserver-1_x86_64-linux-gnu.tar.gz -O - | tar xz --strip-components=1 - sudo cp ninja /usr/local/bin - echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV - name: Check Environment From 9a9bebb9f962e1a1467aafc73c29ad79eb0d0f19 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Fri, 16 Feb 2024 16:30:49 +0900 Subject: [PATCH 0240/2402] ci: twister: Print cloud service information This commit updates the twister workflow jobs that run on the zephyr-runner v2 to print the underlying cloud service information in the logs to help trace and debug potential runner issues. Signed-off-by: Stephanos Ioannidis --- .github/workflows/twister.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index 41434d77f61..5b9800517ae 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -49,6 +49,12 @@ jobs: # GitHub comes up with a fundamental fix for this problem. git config --global --add safe.directory ${GITHUB_WORKSPACE} + - name: Print cloud service information + run: | + echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" + echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" + echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" + - name: Clone cached Zephyr repository if: github.event_name == 'pull_request_target' continue-on-error: true @@ -139,6 +145,12 @@ jobs: COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} BASE_REF: ${{ github.base_ref }} steps: + - name: Print cloud service information + run: | + echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" + echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" + echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" + - name: Apply container owner mismatch workaround run: | # FIXME: The owner UID of the GITHUB_WORKSPACE directory may not From 1be3aacad3dcb32913cf81cc24c086b26a7bccf2 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Thu, 22 Feb 2024 22:13:09 +0900 Subject: [PATCH 0241/2402] ci: twister: Store ccache data in node cache This commit updates the twister workflow to store ccache data in the zephyr-runner v2 node cache. Signed-off-by: Stephanos Ioannidis --- .github/workflows/twister.yaml | 37 +++++++++------------------------- 1 file changed, 9 insertions(+), 28 deletions(-) diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index 5b9800517ae..9c4da7ee6cd 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -136,6 +136,7 @@ jobs: matrix: subset: ${{fromJSON(needs.twister-build-prep.outputs.subset)}} env: + CCACHE_DIR: /node-cache/ccache-zephyr BSIM_OUT_PATH: /opt/bsim/ BSIM_COMPONENTS_PATH: /opt/bsim/components TWISTER_COMMON: ' --force-color --inline-logs -v -N -M --retry-failed 3 ' @@ -200,32 +201,12 @@ jobs: echo "github.base_ref: ${{ github.base_ref }}" echo "github.ref_name: ${{ github.ref_name }}" - - name: Prepare ccache timestamp/data - id: ccache_cache_timestamp - shell: cmake -P {0} + - name: Set up ccache run: | - string(TIMESTAMP current_date "%Y-%m-%d-%H;%M;%S" UTC) - string(REPLACE "/" "_" repo ${{github.repository}}) - string(REPLACE "-" "_" repo2 ${repo}) - file(APPEND $ENV{GITHUB_OUTPUT} "repo=${repo2}\n") - - - name: use cache - id: cache-ccache - uses: zephyrproject-rtos/action-s3-cache@v1.2.0 - continue-on-error: true - with: - key: ${{ steps.ccache_cache_timestamp.outputs.repo }}-${{ github.ref_name }}-${{github.event_name}}-${{ matrix.subset }}-ccache - path: /github/home/.cache/ccache - aws-s3-bucket: ccache.zephyrproject.org - aws-access-key-id: ${{ vars.AWS_CCACHE_ACCESS_KEY_ID }} - aws-secret-access-key: ${{ secrets.AWS_CCACHE_SECRET_ACCESS_KEY }} - aws-region: us-east-2 - - - name: ccache stats initial - run: | - mkdir -p /github/home/.cache - test -d github/home/.cache/ccache && rm -rf /github/home/.cache/ccache && mv github/home/.cache/ccache /github/home/.cache/ccache - ccache -M 10G -s + mkdir -p ${CCACHE_DIR} + ccache -M 10G + ccache -p + ccache -z -s -vv - if: github.event_name == 'push' name: Run Tests with Twister (Push) @@ -268,10 +249,10 @@ jobs: fi fi - - name: ccache stats post + - name: Print ccache stats + if: always() run: | - ccache -p - ccache -s + ccache -s -vv - name: Upload Unit Test Results if: always() From 3823f1f0dbcc356714f9811894611750e18d6483 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Fri, 23 Feb 2024 16:00:10 +0900 Subject: [PATCH 0242/2402] ci: twister: Use Redis remote storage for ccache This commit updates the twister workflow to, when available, use Redis remote storage backend for the ccache compilation cache data. The Redis cache server is hosted in the Kubernetes cluster in which the zephyr-runner pods run -- the Redis remote storage backend will be ignored if the server is unavailable. Signed-off-by: Stephanos Ioannidis --- .github/workflows/twister.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index 9c4da7ee6cd..b12e287bdb0 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -137,6 +137,7 @@ jobs: subset: ${{fromJSON(needs.twister-build-prep.outputs.subset)}} env: CCACHE_DIR: /node-cache/ccache-zephyr + CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" BSIM_OUT_PATH: /opt/bsim/ BSIM_COMPONENTS_PATH: /opt/bsim/components TWISTER_COMMON: ' --force-color --inline-logs -v -N -M --retry-failed 3 ' From d3f9f391ad468e18311ce351a259e59248125d9b Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Fri, 23 Feb 2024 21:16:17 +0900 Subject: [PATCH 0243/2402] ci: twister: Add `--specs` to ccache ignore option list This commit adds the compiler `--specs=*` flag to the ccache ignore option list because ccache is unable to resolve the toolchain-provided specs file path and will consider source files to be uncacheable if it is unable to read the specified specs file. Note that adding `--specs=*` to the ignore option list is not a problem because it is unlikely for the content of the toolchain libc spec file to change without the compiler executable itself changing. Signed-off-by: Stephanos Ioannidis --- .github/workflows/twister.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index b12e287bdb0..3e58573958a 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -138,6 +138,8 @@ jobs: env: CCACHE_DIR: /node-cache/ccache-zephyr CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" + # `--specs` is ignored because ccache is unable to resolve the toolchain specs file path. + CCACHE_IGNOREOPTIONS: '--specs=*' BSIM_OUT_PATH: /opt/bsim/ BSIM_COMPONENTS_PATH: /opt/bsim/components TWISTER_COMMON: ' --force-color --inline-logs -v -N -M --retry-failed 3 ' From 527435d64285e3488a6837ffb4a27ef45f35ce09 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Sun, 25 Feb 2024 00:03:50 +0900 Subject: [PATCH 0244/2402] ci: twister: Prioritise remote Redis cache storage This commit updates the twister workflow such that ccache only uses remote Redis cache storage when available. The purpose of this to reduce the individual runner local disk IOPS requirement; thereby, reducing the overall load on the SAN. Signed-off-by: Stephanos Ioannidis --- .github/workflows/twister.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index 3e58573958a..f3d8cea8b11 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -138,6 +138,7 @@ jobs: env: CCACHE_DIR: /node-cache/ccache-zephyr CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" + CCACHE_REMOTE_ONLY: "true" # `--specs` is ignored because ccache is unable to resolve the toolchain specs file path. CCACHE_IGNOREOPTIONS: '--specs=*' BSIM_OUT_PATH: /opt/bsim/ From de68ea7ce0931e819bef6d850131741a5ed9b6c6 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 29 Jan 2024 10:53:22 +0000 Subject: [PATCH 0245/2402] ci: twister: Set twister timeout multiplier to 2 This commit sets the twister timeout multiplier to 2, which effectively increases the default test timeout from 60 to 120 seconds, because the new cost-effective Zephyr runners may take longer to execute tests and the default timeout is not sufficient for some tests to complete. Signed-off-by: Stephanos Ioannidis --- .github/workflows/twister.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index f3d8cea8b11..a2e5dc5ac76 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -143,7 +143,7 @@ jobs: CCACHE_IGNOREOPTIONS: '--specs=*' BSIM_OUT_PATH: /opt/bsim/ BSIM_COMPONENTS_PATH: /opt/bsim/components - TWISTER_COMMON: ' --force-color --inline-logs -v -N -M --retry-failed 3 ' + TWISTER_COMMON: ' --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 ' DAILY_OPTIONS: ' -M --build-only --all --show-footprint' PR_OPTIONS: ' --clobber-output --integration' PUSH_OPTIONS: ' --clobber-output -M --show-footprint' From c64d0b9ce5727c40ecf5e8c40d2c59c786fca861 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Wed, 20 Dec 2023 20:15:56 +0900 Subject: [PATCH 0246/2402] testsuite: ztest: Increase ZTEST_TEST_DELAY_MS to 5000 This commit increases the default value of `ZTEST_TEST_DELAY_MS` from 3000 to 5000 milliseconds because the current value of 3000ms may not be sufficient for the hosts with lower CPU clock frequency (e.g. new Zephyr CI runners with cost-effective processors). Signed-off-by: Stephanos Ioannidis --- subsys/testsuite/ztest/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/testsuite/ztest/Kconfig b/subsys/testsuite/ztest/Kconfig index e453d286463..b9a11bf2e27 100644 --- a/subsys/testsuite/ztest/Kconfig +++ b/subsys/testsuite/ztest/Kconfig @@ -34,7 +34,7 @@ config ZTEST_SHELL config ZTEST_CPU_HOLD_TIME_MS int "Time in milliseconds to hold other CPUs for 1cpu type tests" - default 3000 + default 5000 help This option is used to specify the maximum time in milliseconds for which a 1cpu type test may execute on a multicpu system. The default From cb81b295e0b3452672111ba8895c71d574c0ede5 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Tue, 5 Mar 2024 21:07:17 +0900 Subject: [PATCH 0247/2402] tests: kernel: thread_runtime_stats: Relax precision test for QEMU This commit relaxes the idle event statistics test precision requirement for emulated QEMU targets because the cycle counts may be inaccurate when the host CPU is overloaded (e.g. when running tests with twister) and a high failure rate is observed for this test in the CI. Signed-off-by: Stephanos Ioannidis --- .../usage/thread_runtime_stats/src/test_thread_runtime_stats.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c b/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c index 211cc11004c..ff0ceeac7c8 100644 --- a/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c +++ b/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c @@ -17,6 +17,8 @@ #if defined(CONFIG_RISCV) #define IDLE_EVENT_STATS_PRECISION 7 +#elif defined(CONFIG_QEMU_TARGET) +#define IDLE_EVENT_STATS_PRECISION 3 #else #define IDLE_EVENT_STATS_PRECISION 1 #endif From 7df7e834d91041a93d6c62a97e7b2bc985492213 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Wed, 6 Mar 2024 08:23:18 +0900 Subject: [PATCH 0248/2402] ci: twister: Set build job timeout to 24 hours This commit increases the twister build job timeout from the default value of 6 hours to 24 hours because scheduled (weekly) build runs take longer than 6 hours to complete. Signed-off-by: Stephanos Ioannidis --- .github/workflows/twister.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index a2e5dc5ac76..298ccc9de92 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -135,6 +135,7 @@ jobs: fail-fast: false matrix: subset: ${{fromJSON(needs.twister-build-prep.outputs.subset)}} + timeout-minutes: 1440 env: CCACHE_DIR: /node-cache/ccache-zephyr CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" From a7d74f80ce7e4502172d8b9dfa320ad7a43458cc Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 22 Feb 2024 21:56:37 -0500 Subject: [PATCH 0249/2402] kernel: move spinlock validation to own file Move spin_lock validation outside of thread.c into own file. This code really has nothing to do with the thread code. Signed-off-by: Anas Nashif --- kernel/CMakeLists.txt | 5 +++++ kernel/spinlock_validate.c | 40 ++++++++++++++++++++++++++++++++++++++ kernel/thread.c | 39 ------------------------------------- 3 files changed, 45 insertions(+), 39 deletions(-) create mode 100644 kernel/spinlock_validate.c diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt index f519b545564..0ad0bf5d78c 100644 --- a/kernel/CMakeLists.txt +++ b/kernel/CMakeLists.txt @@ -84,6 +84,11 @@ endif() endif() +if(CONFIG_SPIN_VALIDATE) +list(APPEND kernel_files + spinlock_validate.c) +endif() + if(CONFIG_XIP) list(APPEND kernel_files xip.c) diff --git a/kernel/spinlock_validate.c b/kernel/spinlock_validate.c new file mode 100644 index 00000000000..90da6fac1b6 --- /dev/null +++ b/kernel/spinlock_validate.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2018,2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +bool z_spin_lock_valid(struct k_spinlock *l) +{ + uintptr_t thread_cpu = l->thread_cpu; + + if (thread_cpu != 0U) { + if ((thread_cpu & 3U) == _current_cpu->id) { + return false; + } + } + return true; +} + +bool z_spin_unlock_valid(struct k_spinlock *l) +{ + if (l->thread_cpu != (_current_cpu->id | (uintptr_t)_current)) { + return false; + } + l->thread_cpu = 0; + return true; +} + +void z_spin_lock_set_owner(struct k_spinlock *l) +{ + l->thread_cpu = _current_cpu->id | (uintptr_t)_current; +} + +#ifdef CONFIG_KERNEL_COHERENCE +bool z_spin_lock_mem_coherent(struct k_spinlock *l) +{ + return arch_mem_coherent((void *)l); +} +#endif /* CONFIG_KERNEL_COHERENCE */ diff --git a/kernel/thread.c b/kernel/thread.c index 31b92fdb2c6..17094798e8d 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -945,45 +945,6 @@ FUNC_NORETURN void k_thread_user_mode_enter(k_thread_entry_t entry, #endif } -/* These spinlock assertion predicates are defined here because having - * them in spinlock.h is a giant header ordering headache. - */ -#ifdef CONFIG_SPIN_VALIDATE -bool z_spin_lock_valid(struct k_spinlock *l) -{ - uintptr_t thread_cpu = l->thread_cpu; - - if (thread_cpu != 0U) { - if ((thread_cpu & 3U) == _current_cpu->id) { - return false; - } - } - return true; -} - -bool z_spin_unlock_valid(struct k_spinlock *l) -{ - if (l->thread_cpu != (_current_cpu->id | (uintptr_t)_current)) { - return false; - } - l->thread_cpu = 0; - return true; -} - -void z_spin_lock_set_owner(struct k_spinlock *l) -{ - l->thread_cpu = _current_cpu->id | (uintptr_t)_current; -} - -#ifdef CONFIG_KERNEL_COHERENCE -bool z_spin_lock_mem_coherent(struct k_spinlock *l) -{ - return arch_mem_coherent((void *)l); -} -#endif /* CONFIG_KERNEL_COHERENCE */ - -#endif /* CONFIG_SPIN_VALIDATE */ - int z_impl_k_float_disable(struct k_thread *thread) { #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) From 2c31db4cc88e2df261917b174a93cfc90d5fc929 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 22 Feb 2024 22:19:05 -0500 Subject: [PATCH 0250/2402] kernel: split irq_offload ccode into own file Move irq_offload code out of thread.c into own file. This code is not related to threads. Signed-off-by: Anas Nashif --- kernel/CMakeLists.txt | 6 ++++++ kernel/irq_offload.c | 23 +++++++++++++++++++++++ kernel/thread.c | 19 ------------------- 3 files changed, 29 insertions(+), 19 deletions(-) create mode 100644 kernel/irq_offload.c diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt index 0ad0bf5d78c..9f7658b54e5 100644 --- a/kernel/CMakeLists.txt +++ b/kernel/CMakeLists.txt @@ -89,6 +89,12 @@ list(APPEND kernel_files spinlock_validate.c) endif() +if(CONFIG_IRQ_OFFLOAD) +list(APPEND kernel_files + irq_offload.c + ) +endif() + if(CONFIG_XIP) list(APPEND kernel_files xip.c) diff --git a/kernel/irq_offload.c b/kernel/irq_offload.c new file mode 100644 index 00000000000..e27c210a9d5 --- /dev/null +++ b/kernel/irq_offload.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2018,2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +/* Make offload_sem visible outside testing, in order to release + * it outside when error happened. + */ +K_SEM_DEFINE(offload_sem, 1, 1); + +void irq_offload(irq_offload_routine_t routine, const void *parameter) +{ +#ifdef CONFIG_IRQ_OFFLOAD_NESTED + arch_irq_offload(routine, parameter); +#else + k_sem_take(&offload_sem, K_FOREVER); + arch_irq_offload(routine, parameter); + k_sem_give(&offload_sem); +#endif +} diff --git a/kernel/thread.c b/kernel/thread.c index 17094798e8d..e6437ac2c20 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -975,24 +974,6 @@ static inline int z_vrfy_k_float_disable(struct k_thread *thread) #include #endif /* CONFIG_USERSPACE */ -#ifdef CONFIG_IRQ_OFFLOAD -/* Make offload_sem visible outside under testing, in order to release - * it outside when error happened. - */ -K_SEM_DEFINE(offload_sem, 1, 1); - -void irq_offload(irq_offload_routine_t routine, const void *parameter) -{ -#ifdef CONFIG_IRQ_OFFLOAD_NESTED - arch_irq_offload(routine, parameter); -#else - k_sem_take(&offload_sem, K_FOREVER); - arch_irq_offload(routine, parameter); - k_sem_give(&offload_sem); -#endif -} -#endif - #if defined(CONFIG_INIT_STACKS) && defined(CONFIG_THREAD_STACK_INFO) #ifdef CONFIG_STACK_GROWS_UP #error "Unsupported configuration for stack analysis" From 8791012ed199d805c5d399493018b94feb2130ef Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 22 Feb 2024 22:24:36 -0500 Subject: [PATCH 0251/2402] kernel: move essential flag related routines out The functions to manipulate the essential flag indeed operate on threads, but they are misplaced in the thread implementation file. Put them alongside other routines setting other thread flags and cleanup headers a bit. Signed-off-by: Anas Nashif --- kernel/include/kernel_internal.h | 5 --- kernel/include/ksched.h | 32 +++++++++++++++++-- kernel/init.c | 4 +-- kernel/sched.c | 4 +-- kernel/thread.c | 31 +----------------- .../fatal/message_capture/CMakeLists.txt | 5 +++ tests/kernel/fatal/message_capture/src/main.c | 5 +-- tests/kernel/threads/thread_apis/src/main.c | 6 ++-- .../thread_apis/src/test_essential_thread.c | 14 ++++---- 9 files changed, 53 insertions(+), 53 deletions(-) diff --git a/kernel/include/kernel_internal.h b/kernel/include/kernel_internal.h index 16efb3b54e8..a204cd9b834 100644 --- a/kernel/include/kernel_internal.h +++ b/kernel/include/kernel_internal.h @@ -110,11 +110,6 @@ static inline void *z_thread_malloc(size_t size) return z_thread_aligned_alloc(0, size); } -/* set and clear essential thread flag */ - -extern void z_thread_essential_set(void); -extern void z_thread_essential_clear(void); - /* clean up when a thread is aborted */ #if defined(CONFIG_THREAD_MONITOR) diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index be45059a835..e2929b89713 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -13,8 +13,6 @@ #include #include -bool z_is_thread_essential(void); - BUILD_ASSERT(K_LOWEST_APPLICATION_THREAD_PRIO >= K_HIGHEST_APPLICATION_THREAD_PRIO); @@ -169,6 +167,36 @@ static inline void z_mark_thread_as_not_pending(struct k_thread *thread) thread->base.thread_state &= ~_THREAD_PENDING; } +/* + * This function tags the current thread as essential to system operation. + * Exceptions raised by this thread will be treated as a fatal system error. + */ +static inline void z_thread_essential_set(struct k_thread *thread) +{ + thread->base.user_options |= K_ESSENTIAL; +} + +/* + * This function tags the current thread as not essential to system operation. + * Exceptions raised by this thread may be recoverable. + * (This is the default tag for a thread.) + */ +static inline void z_thread_essential_clear(struct k_thread *thread) +{ + thread->base.user_options &= ~K_ESSENTIAL; +} + +/* + * This routine indicates if the current thread is an essential system thread. + * + * Returns true if current thread is essential, false if it is not. + */ +static inline bool z_is_thread_essential(struct k_thread *thread) +{ + return (thread->base.user_options & K_ESSENTIAL) == K_ESSENTIAL; +} + + static inline void z_set_thread_states(struct k_thread *thread, uint32_t states) { thread->base.thread_state |= states; diff --git a/kernel/init.c b/kernel/init.c index e4637d3aff1..a562ba07e6d 100644 --- a/kernel/init.c +++ b/kernel/init.c @@ -370,8 +370,8 @@ static void bg_thread_main(void *unused1, void *unused2, void *unused3) (void)main(); - /* Mark nonessential since main() has no more work to do */ - z_main_thread.base.user_options &= ~K_ESSENTIAL; + /* Mark non-essential since main() has no more work to do */ + z_thread_essential_clear(&z_main_thread); #ifdef CONFIG_COVERAGE_DUMP /* Dump coverage data once the main() has exited. */ diff --git a/kernel/sched.c b/kernel/sched.c index 15d9b1d6164..6f38b2f5ed0 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -1732,7 +1732,7 @@ void z_thread_abort(struct k_thread *thread) { k_spinlock_key_t key = k_spin_lock(&sched_spinlock); - if ((thread->base.user_options & K_ESSENTIAL) != 0) { + if (z_is_thread_essential(thread)) { k_spin_unlock(&sched_spinlock, key); __ASSERT(false, "aborting essential thread %p", thread); k_panic(); @@ -1836,7 +1836,7 @@ static inline void z_vrfy_k_thread_abort(k_tid_t thread) return; } - K_OOPS(K_SYSCALL_VERIFY_MSG(!(thread->base.user_options & K_ESSENTIAL), + K_OOPS(K_SYSCALL_VERIFY_MSG(!z_is_thread_essential(thread), "aborting essential thread %p", thread)); z_impl_k_thread_abort((struct k_thread *)thread); diff --git a/kernel/thread.c b/kernel/thread.c index e6437ac2c20..e0211602847 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -143,35 +143,6 @@ bool k_is_in_isr(void) } EXPORT_SYMBOL(k_is_in_isr); -/* - * This function tags the current thread as essential to system operation. - * Exceptions raised by this thread will be treated as a fatal system error. - */ -void z_thread_essential_set(void) -{ - _current->base.user_options |= K_ESSENTIAL; -} - -/* - * This function tags the current thread as not essential to system operation. - * Exceptions raised by this thread may be recoverable. - * (This is the default tag for a thread.) - */ -void z_thread_essential_clear(void) -{ - _current->base.user_options &= ~K_ESSENTIAL; -} - -/* - * This routine indicates if the current thread is an essential system thread. - * - * Returns true if current thread is essential, false if it is not. - */ -bool z_is_thread_essential(void) -{ - return (_current->base.user_options & K_ESSENTIAL) == K_ESSENTIAL; -} - #ifdef CONFIG_THREAD_CUSTOM_DATA void z_impl_k_thread_custom_data_set(void *value) { @@ -918,7 +889,7 @@ FUNC_NORETURN void k_thread_user_mode_enter(k_thread_entry_t entry, SYS_PORT_TRACING_FUNC(k_thread, user_mode_enter); _current->base.user_options |= K_USER; - z_thread_essential_clear(); + z_thread_essential_clear(_current); #ifdef CONFIG_THREAD_MONITOR _current->entry.pEntry = entry; _current->entry.parameter1 = p1; diff --git a/tests/kernel/fatal/message_capture/CMakeLists.txt b/tests/kernel/fatal/message_capture/CMakeLists.txt index 75e2626fbe4..f2d3f4db562 100644 --- a/tests/kernel/fatal/message_capture/CMakeLists.txt +++ b/tests/kernel/fatal/message_capture/CMakeLists.txt @@ -6,3 +6,8 @@ project(message_capture) FILE(GLOB app_sources src/*.c) target_sources(app PRIVATE ${app_sources}) + +target_include_directories(app PRIVATE + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) diff --git a/tests/kernel/fatal/message_capture/src/main.c b/tests/kernel/fatal/message_capture/src/main.c index 906b68855e9..820a28216f9 100644 --- a/tests/kernel/fatal/message_capture/src/main.c +++ b/tests/kernel/fatal/message_capture/src/main.c @@ -6,10 +6,11 @@ #include #include +#include static volatile int expected_reason = -1; -void z_thread_essential_clear(void); +void z_thread_essential_clear(struct k_thread *thread); void k_sys_fatal_error_handler(unsigned int reason, const z_arch_esf_t *pEsf) { @@ -85,7 +86,7 @@ int main(void) * panic and not an oops). Set the thread non-essential as a * workaround. */ - z_thread_essential_clear(); + z_thread_essential_clear(_current); test_message_capture(); return 0; diff --git a/tests/kernel/threads/thread_apis/src/main.c b/tests/kernel/threads/thread_apis/src/main.c index 2e4a4b90f45..95a970d5792 100644 --- a/tests/kernel/threads/thread_apis/src/main.c +++ b/tests/kernel/threads/thread_apis/src/main.c @@ -229,7 +229,7 @@ static void umode_entry(void *thread_id, void *p2, void *p3) ARG_UNUSED(p2); ARG_UNUSED(p3); - if (!z_is_thread_essential() && + if (!z_is_thread_essential(_current) && (k_current_get() == (k_tid_t)thread_id)) { ztest_test_pass(); } else { @@ -246,9 +246,9 @@ static void umode_entry(void *thread_id, void *p2, void *p3) */ static void enter_user_mode_entry(void *p1, void *p2, void *p3) { - z_thread_essential_set(); + z_thread_essential_set(_current); - zassert_true(z_is_thread_essential(), "Thread isn't set" + zassert_true(z_is_thread_essential(_current), "Thread isn't set" " as essential\n"); k_thread_user_mode_enter(umode_entry, diff --git a/tests/kernel/threads/thread_apis/src/test_essential_thread.c b/tests/kernel/threads/thread_apis/src/test_essential_thread.c index 7cebccf4776..0d2829b2b36 100644 --- a/tests/kernel/threads/thread_apis/src/test_essential_thread.c +++ b/tests/kernel/threads/thread_apis/src/test_essential_thread.c @@ -26,16 +26,16 @@ static void thread_entry(void *p1, void *p2, void *p3) ARG_UNUSED(p2); ARG_UNUSED(p3); - z_thread_essential_set(); + z_thread_essential_set(_current); - if (z_is_thread_essential()) { + if (z_is_thread_essential(_current)) { k_busy_wait(100); } else { zassert_unreachable("The thread is not set as essential"); } - z_thread_essential_clear(); - zassert_false(z_is_thread_essential(), + z_thread_essential_clear(_current); + zassert_false(z_is_thread_essential(_current), "Essential flag of the thread is not cleared"); k_sem_give(&sync_sem); @@ -67,7 +67,7 @@ void k_sys_fatal_error_handler(unsigned int reason, fatal_error_signaled = true; - z_thread_essential_clear(); + z_thread_essential_clear(_current); } static void abort_thread_entry(void *p1, void *p2, void *p3) @@ -76,9 +76,9 @@ static void abort_thread_entry(void *p1, void *p2, void *p3) ARG_UNUSED(p2); ARG_UNUSED(p3); - z_thread_essential_set(); + z_thread_essential_set(_current); - if (z_is_thread_essential()) { + if (z_is_thread_essential(_current)) { k_busy_wait(100); } else { zassert_unreachable("The thread is not set as essential"); From 6e95bdeca6479876366d24bbbff576f0d0587a01 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Fri, 23 Feb 2024 07:24:52 -0500 Subject: [PATCH 0252/2402] kernel: reorg Kconfigs and split them The kernel kconfig is becoming too big and unmanageable with too many options scattered across the file. Move some areas out and reorg main Kconfig slightly. Signed-off-by: Anas Nashif --- kernel/Kconfig | 409 +++++----------------------------------- kernel/Kconfig.device | 63 +++++++ kernel/Kconfig.obj_core | 155 +++++++++++++++ kernel/Kconfig.smp | 107 +++++++++++ 4 files changed, 377 insertions(+), 357 deletions(-) create mode 100644 kernel/Kconfig.device create mode 100644 kernel/Kconfig.obj_core create mode 100644 kernel/Kconfig.smp diff --git a/kernel/Kconfig b/kernel/Kconfig index 1620a3c9aa4..ada381d98cb 100644 --- a/kernel/Kconfig +++ b/kernel/Kconfig @@ -265,43 +265,6 @@ endchoice # DYNAMIC_THREAD_PREFER endif # DYNAMIC_THREADS -config LIBC_ERRNO - bool - help - Use external libc errno, not the internal one. This eliminates any - locally allocated errno storage and usage. - -config ERRNO - bool "Errno support" - default y - help - Enable per-thread errno in the kernel. Application and library code must - include errno.h provided by the C library (libc) to use the errno - symbol. The C library must access the per-thread errno via the - z_errno() symbol. - -config ERRNO_IN_TLS - bool "Store errno in thread local storage (TLS)" - depends on ERRNO && THREAD_LOCAL_STORAGE && !LIBC_ERRNO - default y - help - Use thread local storage to store errno instead of storing it in - the kernel thread struct. This avoids a syscall if userspace is enabled. - -config CURRENT_THREAD_USE_NO_TLS - bool - help - Hidden symbol to not use thread local storage to store current - thread. - -config CURRENT_THREAD_USE_TLS - bool "Store current thread in thread local storage (TLS)" - depends on THREAD_LOCAL_STORAGE && !CURRENT_THREAD_USE_NO_TLS - default y - help - Use thread local storage to store the current thread. This avoids a - syscall if userspace is enabled. - choice SCHED_ALGORITHM prompt "Scheduler priority queue algorithm" default SCHED_DUMB @@ -386,6 +349,46 @@ config WAITQ_DUMB endchoice # WAITQ_ALGORITHM +menu "Misc Kernel related options" +config LIBC_ERRNO + bool + help + Use external libc errno, not the internal one. This eliminates any + locally allocated errno storage and usage. + +config ERRNO + bool "Errno support" + default y + help + Enable per-thread errno in the kernel. Application and library code must + include errno.h provided by the C library (libc) to use the errno + symbol. The C library must access the per-thread errno via the + z_errno() symbol. + +config ERRNO_IN_TLS + bool "Store errno in thread local storage (TLS)" + depends on ERRNO && THREAD_LOCAL_STORAGE && !LIBC_ERRNO + default y + help + Use thread local storage to store errno instead of storing it in + the kernel thread struct. This avoids a syscall if userspace is enabled. + +config CURRENT_THREAD_USE_NO_TLS + bool + help + Hidden symbol to not use thread local storage to store current + thread. + +config CURRENT_THREAD_USE_TLS + bool "Store current thread in thread local storage (TLS)" + depends on THREAD_LOCAL_STORAGE && !CURRENT_THREAD_USE_NO_TLS + default y + help + Use thread local storage to store the current thread. This avoids a + syscall if userspace is enabled. + +endmenu + menu "Kernel Debugging and Metrics" config INIT_STACKS @@ -518,160 +521,9 @@ endif # THREAD_RUNTIME_STATS endmenu -menuconfig OBJ_CORE - bool "Object core framework" - default n - help - This option enables the object core framework. This will link - participating kernel objects and their respective types together - in a way that allows them to both have common information stored - together and for that information to be easily retrieved by - automated means. - -if OBJ_CORE -config OBJ_CORE_CONDVAR - bool "Integrate condition variables into object core framework" - default y - help - When enabled, this option integrates condition variables into the - object core framework. +rsource "Kconfig.obj_core" -config OBJ_CORE_EVENT - bool "Integrate events into object core framework" - default y if EVENTS - help - When enabled, this option integrate kernel events into the object - core framework. - -config OBJ_CORE_FIFO - bool "Integrate FIFOs into object core framework" - default y - help - When enabled, this option integrates FIFOs into the object core - framework. - -config OBJ_CORE_LIFO - bool "Integrate LIFOs into object core framework" - default y - help - When enabled, this option integrates LIFOs into the object core - framework. - -config OBJ_CORE_MAILBOX - bool "Integrate mailboxes into object core framework" - default y - help - When enabled, this option integrates mailboxes into the object core - framework. - -config OBJ_CORE_MEM_SLAB - bool "Integrate memory slabs into object core framework" - default y - help - When enabled, this option integrates memory slabs into the object - core framework. - -config OBJ_CORE_MUTEX - bool "Integrate mutexes into object core framework" - default y - help - When enabled, this option integrates mutexes into the object core - framework. - -config OBJ_CORE_MSGQ - bool "Integrate message queues into object core framework" - default y - help - When enabled, this option integrates message queues into the object - core framework. - -config OBJ_CORE_SEM - bool "Integrate semaphores into object core framework" - default y - help - When enabled, this option integrates semaphores into the object core - framework. - -config OBJ_CORE_PIPE - bool "Integrate pipe into object core framework" - default y if PIPES - help - When enabled, this option integrates pipes into the object core - framework. - -config OBJ_CORE_SEM - bool "Integrate semaphores into object core framework" - default y - help - When enabled, this option integrates semaphores into the object core - framework. - -config OBJ_CORE_STACK - bool "Integrate stacks into object core framework" - default y - help - When enabled, this option integrates stacks into the object core - framework. - -config OBJ_CORE_THREAD - bool "Integrate threads into object core framework" - default y - help - When enabled, this option integrates threads into the object core - framework. - -config OBJ_CORE_TIMER - bool "Integrate timers into object core framework" - default y - help - When enabled, this option integrates timers into the object core - framework. - -config OBJ_CORE_SYSTEM - bool - default y - help - When enabled, this option integrates the internal CPU and kernel - system objects into the object core framework. As these are internal - structures, this option is hidden by default and only available to - advanced users. - -menuconfig OBJ_CORE_STATS - bool "Object core statistics" - default n - help - This option integrates statistics gathering into the object core - framework. - -if OBJ_CORE_STATS -config OBJ_CORE_STATS_MEM_SLAB - bool "Object core statistics for memory slabs" - default y if OBJ_CORE_MEM_SLAB - help - When enabled, this allows memory slab statistics to be integrated - into kernel objects. - -config OBJ_CORE_STATS_THREAD - bool "Object core statistics for threads" - default y if OBJ_CORE_THREAD - select THREAD_RUNTIME_STATS - help - When enabled, this integrates thread runtime statistics into the - object core statistics framework. - -config OBJ_CORE_STATS_SYSTEM - bool "Object core statistics for system level objects" - default y if OBJ_CORE_SYSTEM - select SCHED_THREAD_USAGE_ALL - help - When enabled, this integrates thread runtime statistics at the - CPU and system level into the object core statistics framework. - -endif # OBJ_CORE_STATS - -endif # OBJ_CORE - -menu "Work Queue Options" +menu "System Work Queue Options" config SYSTEM_WORKQUEUE_STACK_SIZE int "System workqueue stack size" default 4096 if COVERAGE_GCOV @@ -777,6 +629,10 @@ config TIMESLICE_PER_THREAD a per-thread basis, with an application callback invoked when a thread reaches the end of its timeslice. +endmenu + +menu "Other Kernel Object Options" + config POLL bool "Async I/O Framework" help @@ -785,10 +641,6 @@ config POLL concurrently, which can be either directly triggered or triggered by the availability of some kernel objects (semaphores and FIFOs). -endmenu - -menu "Other Kernel Object Options" - config MEM_SLAB_TRACE_MAX_UTILIZATION bool "Getting maximum slab utilization" help @@ -976,39 +828,6 @@ config XIP supply a linker command file when building your image. Enabling this option increases both the code and data footprint of the image. -menu "Initialization Priorities" - -config KERNEL_INIT_PRIORITY_OBJECTS - int "Kernel objects initialization priority" - default 30 - help - Kernel objects use this priority for initialization. This - priority needs to be higher than minimal default initialization - priority. - -config KERNEL_INIT_PRIORITY_DEFAULT - int "Default init priority" - default 40 - help - Default minimal init priority for each init level. - -config KERNEL_INIT_PRIORITY_DEVICE - int "Default init priority for device drivers" - default 50 - help - Device driver, that depends on common components, such as - interrupt controller, but does not depend on other devices, - uses this init priority. - -config APPLICATION_INIT_PRIORITY - int "Default init priority for application level drivers" - default 90 - help - This priority level is for end-user drivers such as sensors and display - which have no inward dependencies. - - -endmenu menu "Security Options" @@ -1095,6 +914,9 @@ config BOUNDS_CHECK_BYPASS_MITIGATION macros do nothing. endmenu + +menu "Memory Domains" + config MAX_DOMAIN_PARTITIONS int "Maximum number of partitions per memory domain" default 16 @@ -1143,112 +965,10 @@ config ARCH_MEM_DOMAIN_SYNCHRONOUS_API tables, these APIs don't need to be implemented as the underlying memory management hardware will be reprogrammed on context switch anyway. - -menu "SMP Options" - -config SMP - bool "Symmetric multiprocessing support" - depends on USE_SWITCH - depends on !ATOMIC_OPERATIONS_C - help - When true, kernel will be built with SMP support, allowing - more than one CPU to schedule Zephyr tasks at a time. - -config USE_SWITCH - bool "Use new-style _arch_switch instead of arch_swap" - depends on USE_SWITCH_SUPPORTED - help - The _arch_switch() API is a lower level context switching - primitive than the original arch_swap mechanism. It is required - for an SMP-aware scheduler, or if the architecture does not - provide arch_swap. In uniprocess situations where the - architecture provides both, _arch_switch incurs more somewhat - overhead and may be slower. - -config USE_SWITCH_SUPPORTED - bool - help - Indicates whether _arch_switch() API is supported by the - currently enabled platform. This option should be selected by - platforms that implement it. - -config SMP_BOOT_DELAY - bool "Delay booting secondary cores" - depends on SMP - help - By default Zephyr will boot all available CPUs during start up. - Select this option to skip this and allow custom code - (architecture/SoC/board/application) to boot secondary CPUs at - a later time. - -config MP_NUM_CPUS - int "Number of CPUs/cores [DEPRECATED]" - default MP_MAX_NUM_CPUS - range 1 12 - help - This is deprecated, please use MP_MAX_NUM_CPUS instead. - -config MP_MAX_NUM_CPUS - int "Maximum number of CPUs/cores" - default 1 - range 1 12 - help - Maximum number of multiprocessing-capable cores available to the - multicpu API and SMP features. - -config SCHED_IPI_SUPPORTED - bool - help - True if the architecture supports a call to - arch_sched_ipi() to broadcast an interrupt that will call - z_sched_ipi() on other CPUs in the system. Required for - k_thread_abort() to operate with reasonable latency - (otherwise we might have to wait for the other thread to - take an interrupt, which can be arbitrarily far in the - future). - -config TRACE_SCHED_IPI - bool "Test IPI" - help - When true, it will add a hook into z_sched_ipi(), in order - to check if schedule IPI has called or not, for testing - purpose. - depends on SCHED_IPI_SUPPORTED - depends on MP_MAX_NUM_CPUS>1 - -config KERNEL_COHERENCE - bool "Place all shared data into coherent memory" - depends on ARCH_HAS_COHERENCE - default y if SMP && MP_MAX_NUM_CPUS > 1 - select THREAD_STACK_INFO - help - When available and selected, the kernel will build in a mode - where all shared data is placed in multiprocessor-coherent - (generally "uncached") memory. Thread stacks will remain - cached, as will application memory declared with - __incoherent. This is intended for Zephyr SMP kernels - running on cache-incoherent architectures only. Note that - when this is selected, there is an implicit API change that - assumes cache coherence to any memory passed to the kernel. - Code that creates kernel data structures in uncached regions - may fail strangely. Some assertions exist to catch these - mistakes, but not all circumstances can be tested. - -config TICKET_SPINLOCKS - bool "Ticket spinlocks for lock acquisition fairness [EXPERIMENTAL]" - select EXPERIMENTAL - help - Basic spinlock implementation is based on single - atomic variable and doesn't guarantee locking fairness - across multiple CPUs. It's even possible that single CPU - will win the contention every time which will result - in a live-lock. - Ticket spinlocks provide a FIFO order of lock acquisition - which resolves such unfairness issue at the cost of slightly - increased memory footprint. - endmenu +rsource "Kconfig.smp" + config TICKLESS_KERNEL bool "Tickless kernel" default y if TICKLESS_CAPABLE @@ -1273,30 +993,5 @@ config THREAD_LOCAL_STORAGE endmenu -menu "Device Options" - -config DEVICE_DEPS - bool "Store device dependencies" - help - When enabled, device dependencies will be stored so that they can be - queried at runtime. Device dependencies are typically inferred from - devicetree. Enabling this option will increase ROM usage (or RAM if - dynamic device dependencies are enabled). - -config DEVICE_DEPS_DYNAMIC - bool "Dynamic device dependencies" - depends on DEVICE_DEPS - help - Option that makes it possible to manipulate device dependencies at - runtime. - -config DEVICE_MUTABLE - bool "Mutable devices [EXPERIMENTAL]" - select EXPERIMENTAL - help - Support mutable devices. Mutable devices are instantiated in SRAM - instead of Flash and are runtime modifiable in kernel mode. - -endmenu - +rsource "Kconfig.device" rsource "Kconfig.vm" diff --git a/kernel/Kconfig.device b/kernel/Kconfig.device new file mode 100644 index 00000000000..f9718c4272d --- /dev/null +++ b/kernel/Kconfig.device @@ -0,0 +1,63 @@ +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# Copyright (c) 2024 Intel Corp. +# SPDX-License-Identifier: Apache-2.0 +# +menu "Device Options" + +config DEVICE_DEPS + bool "Store device dependencies" + help + When enabled, device dependencies will be stored so that they can be + queried at runtime. Device dependencies are typically inferred from + devicetree. Enabling this option will increase ROM usage (or RAM if + dynamic device dependencies are enabled). + +config DEVICE_DEPS_DYNAMIC + bool "Dynamic device dependencies" + depends on DEVICE_DEPS + help + Option that makes it possible to manipulate device dependencies at + runtime. + +config DEVICE_MUTABLE + bool "Mutable devices [EXPERIMENTAL]" + select EXPERIMENTAL + help + Support mutable devices. Mutable devices are instantiated in SRAM + instead of Flash and are runtime modifiable in kernel mode. + +endmenu + +menu "Initialization Priorities" + +config KERNEL_INIT_PRIORITY_OBJECTS + int "Kernel objects initialization priority" + default 30 + help + Kernel objects use this priority for initialization. This + priority needs to be higher than minimal default initialization + priority. + +config KERNEL_INIT_PRIORITY_DEFAULT + int "Default init priority" + default 40 + help + Default minimal init priority for each init level. + +config KERNEL_INIT_PRIORITY_DEVICE + int "Default init priority for device drivers" + default 50 + help + Device driver, that depends on common components, such as + interrupt controller, but does not depend on other devices, + uses this init priority. + +config APPLICATION_INIT_PRIORITY + int "Default init priority for application level drivers" + default 90 + help + This priority level is for end-user drivers such as sensors and display + which have no inward dependencies. + + +endmenu diff --git a/kernel/Kconfig.obj_core b/kernel/Kconfig.obj_core new file mode 100644 index 00000000000..5c9a1418ffe --- /dev/null +++ b/kernel/Kconfig.obj_core @@ -0,0 +1,155 @@ +# Copyright (c) 2024 Intel Corp. +# SPDX-License-Identifier: Apache-2.0 +# +menuconfig OBJ_CORE + bool "Object core framework" + default n + help + This option enables the object core framework. This will link + participating kernel objects and their respective types together + in a way that allows them to both have common information stored + together and for that information to be easily retrieved by + automated means. + +if OBJ_CORE +config OBJ_CORE_CONDVAR + bool "Integrate condition variables into object core framework" + default y + help + When enabled, this option integrates condition variables into the + object core framework. + +config OBJ_CORE_EVENT + bool "Integrate events into object core framework" + default y if EVENTS + help + When enabled, this option integrate kernel events into the object + core framework. + +config OBJ_CORE_FIFO + bool "Integrate FIFOs into object core framework" + default y + help + When enabled, this option integrates FIFOs into the object core + framework. + +config OBJ_CORE_LIFO + bool "Integrate LIFOs into object core framework" + default y + help + When enabled, this option integrates LIFOs into the object core + framework. + +config OBJ_CORE_MAILBOX + bool "Integrate mailboxes into object core framework" + default y + help + When enabled, this option integrates mailboxes into the object core + framework. + +config OBJ_CORE_MEM_SLAB + bool "Integrate memory slabs into object core framework" + default y + help + When enabled, this option integrates memory slabs into the object + core framework. + +config OBJ_CORE_MUTEX + bool "Integrate mutexes into object core framework" + default y + help + When enabled, this option integrates mutexes into the object core + framework. + +config OBJ_CORE_MSGQ + bool "Integrate message queues into object core framework" + default y + help + When enabled, this option integrates message queues into the object + core framework. + +config OBJ_CORE_SEM + bool "Integrate semaphores into object core framework" + default y + help + When enabled, this option integrates semaphores into the object core + framework. + +config OBJ_CORE_PIPE + bool "Integrate pipe into object core framework" + default y if PIPES + help + When enabled, this option integrates pipes into the object core + framework. + +config OBJ_CORE_SEM + bool "Integrate semaphores into object core framework" + default y + help + When enabled, this option integrates semaphores into the object core + framework. + +config OBJ_CORE_STACK + bool "Integrate stacks into object core framework" + default y + help + When enabled, this option integrates stacks into the object core + framework. + +config OBJ_CORE_THREAD + bool "Integrate threads into object core framework" + default y + help + When enabled, this option integrates threads into the object core + framework. + +config OBJ_CORE_TIMER + bool "Integrate timers into object core framework" + default y + help + When enabled, this option integrates timers into the object core + framework. + +config OBJ_CORE_SYSTEM + bool + default y + help + When enabled, this option integrates the internal CPU and kernel + system objects into the object core framework. As these are internal + structures, this option is hidden by default and only available to + advanced users. + +menuconfig OBJ_CORE_STATS + bool "Object core statistics" + default n + help + This option integrates statistics gathering into the object core + framework. + +if OBJ_CORE_STATS +config OBJ_CORE_STATS_MEM_SLAB + bool "Object core statistics for memory slabs" + default y if OBJ_CORE_MEM_SLAB + help + When enabled, this allows memory slab statistics to be integrated + into kernel objects. + +config OBJ_CORE_STATS_THREAD + bool "Object core statistics for threads" + default y if OBJ_CORE_THREAD + select THREAD_RUNTIME_STATS + help + When enabled, this integrates thread runtime statistics into the + object core statistics framework. + +config OBJ_CORE_STATS_SYSTEM + bool "Object core statistics for system level objects" + default y if OBJ_CORE_SYSTEM + select SCHED_THREAD_USAGE_ALL + help + When enabled, this integrates thread runtime statistics at the + CPU and system level into the object core statistics framework. + +endif # OBJ_CORE_STATS + +endif # OBJ_CORE diff --git a/kernel/Kconfig.smp b/kernel/Kconfig.smp new file mode 100644 index 00000000000..22279270b19 --- /dev/null +++ b/kernel/Kconfig.smp @@ -0,0 +1,107 @@ +# Copyright (c) 2024 Intel Corp. +# SPDX-License-Identifier: Apache-2.0 +# +menu "SMP Options" + +config SMP + bool "Symmetric multiprocessing support" + depends on USE_SWITCH + depends on !ATOMIC_OPERATIONS_C + help + When true, kernel will be built with SMP support, allowing + more than one CPU to schedule Zephyr tasks at a time. + +config USE_SWITCH + bool "Use new-style _arch_switch instead of arch_swap" + depends on USE_SWITCH_SUPPORTED + help + The _arch_switch() API is a lower level context switching + primitive than the original arch_swap mechanism. It is required + for an SMP-aware scheduler, or if the architecture does not + provide arch_swap. In uniprocess situations where the + architecture provides both, _arch_switch incurs more somewhat + overhead and may be slower. + +config USE_SWITCH_SUPPORTED + bool + help + Indicates whether _arch_switch() API is supported by the + currently enabled platform. This option should be selected by + platforms that implement it. + +config SMP_BOOT_DELAY + bool "Delay booting secondary cores" + depends on SMP + help + By default Zephyr will boot all available CPUs during start up. + Select this option to skip this and allow custom code + (architecture/SoC/board/application) to boot secondary CPUs at + a later time. + +config MP_NUM_CPUS + int "Number of CPUs/cores [DEPRECATED]" + default MP_MAX_NUM_CPUS + range 1 12 + help + This is deprecated, please use MP_MAX_NUM_CPUS instead. + +config MP_MAX_NUM_CPUS + int "Maximum number of CPUs/cores" + default 1 + range 1 12 + help + Maximum number of multiprocessing-capable cores available to the + multicpu API and SMP features. + +config SCHED_IPI_SUPPORTED + bool + help + True if the architecture supports a call to + arch_sched_ipi() to broadcast an interrupt that will call + z_sched_ipi() on other CPUs in the system. Required for + k_thread_abort() to operate with reasonable latency + (otherwise we might have to wait for the other thread to + take an interrupt, which can be arbitrarily far in the + future). + +config TRACE_SCHED_IPI + bool "Test IPI" + help + When true, it will add a hook into z_sched_ipi(), in order + to check if schedule IPI has called or not, for testing + purpose. + depends on SCHED_IPI_SUPPORTED + depends on MP_MAX_NUM_CPUS>1 + +config KERNEL_COHERENCE + bool "Place all shared data into coherent memory" + depends on ARCH_HAS_COHERENCE + default y if SMP && MP_MAX_NUM_CPUS > 1 + select THREAD_STACK_INFO + help + When available and selected, the kernel will build in a mode + where all shared data is placed in multiprocessor-coherent + (generally "uncached") memory. Thread stacks will remain + cached, as will application memory declared with + __incoherent. This is intended for Zephyr SMP kernels + running on cache-incoherent architectures only. Note that + when this is selected, there is an implicit API change that + assumes cache coherence to any memory passed to the kernel. + Code that creates kernel data structures in uncached regions + may fail strangely. Some assertions exist to catch these + mistakes, but not all circumstances can be tested. + +config TICKET_SPINLOCKS + bool "Ticket spinlocks for lock acquisition fairness [EXPERIMENTAL]" + select EXPERIMENTAL + help + Basic spinlock implementation is based on single + atomic variable and doesn't guarantee locking fairness + across multiple CPUs. It's even possible that single CPU + will win the contention every time which will result + in a live-lock. + Ticket spinlocks provide a FIFO order of lock acquisition + which resolves such unfairness issue at the cost of slightly + increased memory footprint. + +endmenu From 077222c975070396df9295597c0332fd14e3f3b7 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 22 Feb 2024 13:51:15 -0500 Subject: [PATCH 0253/2402] kernel: split cpu_mask handling into own file In an effort to cleanup sched.c, move sections of code that can be compiled in based on options into own files. CPU mask here is managed by a kconfig and is not widely used (SMP affinity on multicore systems). Signed-off-by: Anas Nashif --- kernel/CMakeLists.txt | 6 ++++ kernel/cpu_mask.c | 76 +++++++++++++++++++++++++++++++++++++++++++ kernel/sched.c | 68 -------------------------------------- 3 files changed, 82 insertions(+), 68 deletions(-) create mode 100644 kernel/cpu_mask.c diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt index 9f7658b54e5..6a397318681 100644 --- a/kernel/CMakeLists.txt +++ b/kernel/CMakeLists.txt @@ -63,6 +63,12 @@ list(APPEND kernel_files sched.c ) +if(CONFIG_SCHED_CPU_MASK) +list(APPEND kernel_files + cpu_mask.c + ) +endif() + if(CONFIG_MULTITHREADING) list(APPEND kernel_files idle.c diff --git a/kernel/cpu_mask.c b/kernel/cpu_mask.c new file mode 100644 index 00000000000..99d8c4c3967 --- /dev/null +++ b/kernel/cpu_mask.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2018,2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include + +extern struct k_spinlock sched_spinlock; + + +# ifdef CONFIG_SMP +/* Right now we use a two byte for this mask */ +BUILD_ASSERT(CONFIG_MP_MAX_NUM_CPUS <= 16, "Too many CPUs for mask word"); +# endif + + +static int cpu_mask_mod(k_tid_t thread, uint32_t enable_mask, uint32_t disable_mask) +{ + int ret = 0; + +#ifdef CONFIG_SCHED_CPU_MASK_PIN_ONLY + __ASSERT(z_is_thread_prevented_from_running(thread), + "Running threads cannot change CPU pin"); +#endif + + K_SPINLOCK(&sched_spinlock) { + if (z_is_thread_prevented_from_running(thread)) { + thread->base.cpu_mask |= enable_mask; + thread->base.cpu_mask &= ~disable_mask; + } else { + ret = -EINVAL; + } + } + +#if defined(CONFIG_ASSERT) && defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY) + int m = thread->base.cpu_mask; + + __ASSERT((m == 0) || ((m & (m - 1)) == 0), + "Only one CPU allowed in mask when PIN_ONLY"); +#endif + + return ret; +} + +int k_thread_cpu_mask_clear(k_tid_t thread) +{ + return cpu_mask_mod(thread, 0, 0xffffffff); +} + +int k_thread_cpu_mask_enable_all(k_tid_t thread) +{ + return cpu_mask_mod(thread, 0xffffffff, 0); +} + +int k_thread_cpu_mask_enable(k_tid_t thread, int cpu) +{ + return cpu_mask_mod(thread, BIT(cpu), 0); +} + +int k_thread_cpu_mask_disable(k_tid_t thread, int cpu) +{ + return cpu_mask_mod(thread, 0, BIT(cpu)); +} + +int k_thread_cpu_pin(k_tid_t thread, int cpu) +{ + int ret; + + ret = k_thread_cpu_mask_clear(thread); + if (ret == 0) { + return k_thread_cpu_mask_enable(thread, cpu); + } + return ret; +} diff --git a/kernel/sched.c b/kernel/sched.c index 6f38b2f5ed0..4ed3db41b09 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -1580,74 +1580,6 @@ static inline int z_vrfy_k_is_preempt_thread(void) #include #endif -#ifdef CONFIG_SCHED_CPU_MASK -# ifdef CONFIG_SMP -/* Right now we use a two byte for this mask */ -BUILD_ASSERT(CONFIG_MP_MAX_NUM_CPUS <= 16, "Too many CPUs for mask word"); -# endif - - -static int cpu_mask_mod(k_tid_t thread, uint32_t enable_mask, uint32_t disable_mask) -{ - int ret = 0; - -#ifdef CONFIG_SCHED_CPU_MASK_PIN_ONLY - __ASSERT(z_is_thread_prevented_from_running(thread), - "Running threads cannot change CPU pin"); -#endif - - K_SPINLOCK(&sched_spinlock) { - if (z_is_thread_prevented_from_running(thread)) { - thread->base.cpu_mask |= enable_mask; - thread->base.cpu_mask &= ~disable_mask; - } else { - ret = -EINVAL; - } - } - -#if defined(CONFIG_ASSERT) && defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY) - int m = thread->base.cpu_mask; - - __ASSERT((m == 0) || ((m & (m - 1)) == 0), - "Only one CPU allowed in mask when PIN_ONLY"); -#endif - - return ret; -} - -int k_thread_cpu_mask_clear(k_tid_t thread) -{ - return cpu_mask_mod(thread, 0, 0xffffffff); -} - -int k_thread_cpu_mask_enable_all(k_tid_t thread) -{ - return cpu_mask_mod(thread, 0xffffffff, 0); -} - -int k_thread_cpu_mask_enable(k_tid_t thread, int cpu) -{ - return cpu_mask_mod(thread, BIT(cpu), 0); -} - -int k_thread_cpu_mask_disable(k_tid_t thread, int cpu) -{ - return cpu_mask_mod(thread, 0, BIT(cpu)); -} - -int k_thread_cpu_pin(k_tid_t thread, int cpu) -{ - int ret; - - ret = k_thread_cpu_mask_clear(thread); - if (ret == 0) { - return k_thread_cpu_mask_enable(thread, cpu); - } - return ret; -} - -#endif /* CONFIG_SCHED_CPU_MASK */ - static inline void unpend_all(_wait_q_t *wait_q) { struct k_thread *thread; From a6ce422b1073159da9ef3cbb52884ca6488321ef Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 22 Feb 2024 14:10:17 -0500 Subject: [PATCH 0254/2402] kernel: remove cmsis-rtos layering violation We shouldn't be calling hooks from optional and upper layer subsystems in the kernel, instead, just call the hook to set thread status in the API where it is needed. This now clears related bit in cmsis thread status bitarray when terminating a thread in the cmsis rtos v1 layer directly and not in the kenrel code. Signed-off-by: Anas Nashif --- kernel/Kconfig | 5 +++++ kernel/sched.c | 9 ++++----- subsys/portability/cmsis_rtos_v1/Kconfig | 1 + subsys/portability/cmsis_rtos_v1/cmsis_thread.c | 2 +- 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/kernel/Kconfig b/kernel/Kconfig index ada381d98cb..9a326bf546e 100644 --- a/kernel/Kconfig +++ b/kernel/Kconfig @@ -192,6 +192,11 @@ config THREAD_STACK_INFO This option allows each thread to store the thread stack info into the k_thread data structure. +config THREAD_ABORT_HOOK + bool + help + Used by portability layers to modify locally managed status mask. + config THREAD_CUSTOM_DATA bool "Thread custom data" help diff --git a/kernel/sched.c b/kernel/sched.c index 4ed3db41b09..deb045ed591 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -1592,8 +1592,8 @@ static inline void unpend_all(_wait_q_t *wait_q) } } -#ifdef CONFIG_CMSIS_RTOS_V1 -extern void z_thread_cmsis_status_mask_clear(struct k_thread *thread); +#ifdef CONFIG_THREAD_ABORT_HOOK +extern void thread_abort_hook(struct k_thread *thread); #endif /** @@ -1639,9 +1639,8 @@ static void halt_thread(struct k_thread *thread, uint8_t new_state) SYS_PORT_TRACING_FUNC(k_thread, sched_abort, thread); z_thread_monitor_exit(thread); - -#ifdef CONFIG_CMSIS_RTOS_V1 - z_thread_cmsis_status_mask_clear(thread); +#ifdef CONFIG_THREAD_ABORT_HOOK + thread_abort_hook(thread); #endif #ifdef CONFIG_OBJ_CORE_THREAD diff --git a/subsys/portability/cmsis_rtos_v1/Kconfig b/subsys/portability/cmsis_rtos_v1/Kconfig index f409d4f55ff..942ea020118 100644 --- a/subsys/portability/cmsis_rtos_v1/Kconfig +++ b/subsys/portability/cmsis_rtos_v1/Kconfig @@ -6,6 +6,7 @@ config CMSIS_RTOS_V1 depends on THREAD_CUSTOM_DATA depends on POLL depends on THREAD_STACK_INFO + select THREAD_ABORT_HOOK help This enables CMSIS RTOS v1 API support. This is an OS-integration layer which allows applications using CMSIS RTOS APIs to build on diff --git a/subsys/portability/cmsis_rtos_v1/cmsis_thread.c b/subsys/portability/cmsis_rtos_v1/cmsis_thread.c index 9887e560afb..6ce53fe7192 100644 --- a/subsys/portability/cmsis_rtos_v1/cmsis_thread.c +++ b/subsys/portability/cmsis_rtos_v1/cmsis_thread.c @@ -39,7 +39,7 @@ static void zephyr_thread_wrapper(void *arg1, void *arg2, void *arg3) /* clear related bit in cmsis thread status bitarray * when terminating a thread */ -void z_thread_cmsis_status_mask_clear(struct k_thread *thread) +void thread_abort_hook(struct k_thread *thread) { uint32_t offset, instance; From 3ca50f506012c17ae78ac76e43837e955fdca4eb Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Fri, 23 Feb 2024 10:53:01 -0500 Subject: [PATCH 0255/2402] kernel: move z_init_static_threads to where it is being used Move out of thread and put directly in init.c where it is being used. Also remove definition from kernel.h, this is an internal function and should not be in a public header. Signed-off-by: Anas Nashif --- include/zephyr/kernel.h | 15 -------- kernel/include/kthread.h | 30 ++++++++++++++++ kernel/init.c | 53 +++++++++++++++++++++++++++ kernel/thread.c | 78 ++-------------------------------------- 4 files changed, 86 insertions(+), 90 deletions(-) create mode 100644 kernel/include/kthread.h diff --git a/include/zephyr/kernel.h b/include/zephyr/kernel.h index 9f2b750d166..388051f05a6 100644 --- a/include/zephyr/kernel.h +++ b/include/zephyr/kernel.h @@ -5935,21 +5935,6 @@ static inline void k_cpu_atomic_idle(unsigned int key) * private APIs that are utilized by one or more public APIs */ -/** - * @internal - */ -#ifdef CONFIG_MULTITHREADING -/** - * @internal - */ -void z_init_static_threads(void); -#else -/** - * @internal - */ -#define z_init_static_threads() do { } while (false) -#endif - /** * @internal */ diff --git a/kernel/include/kthread.h b/kernel/include/kthread.h new file mode 100644 index 00000000000..8cdec848f21 --- /dev/null +++ b/kernel/include/kthread.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2016-2017 Wind River Systems, Inc. + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_KERNEL_INCLUDE_THREAD_H_ +#define ZEPHYR_KERNEL_INCLUDE_THREAD_H_ + +#include +#include + +#ifdef CONFIG_MULTITHREADING +static inline void thread_schedule_new(struct k_thread *thread, k_timeout_t delay) +{ +#ifdef CONFIG_SYS_CLOCK_EXISTS + if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) { + k_thread_start(thread); + } else { + z_add_thread_timeout(thread, delay); + } +#else + ARG_UNUSED(delay); + k_thread_start(thread); +#endif +} +#endif + +#endif /* ZEPHYR_KERNEL_INCLUDE_THREAD_H_ */ diff --git a/kernel/init.c b/kernel/init.c index a562ba07e6d..81705e87cc5 100644 --- a/kernel/init.c +++ b/kernel/init.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -58,6 +59,57 @@ struct k_thread z_idle_threads[CONFIG_MP_MAX_NUM_CPUS]; static K_KERNEL_PINNED_STACK_ARRAY_DEFINE(z_idle_stacks, CONFIG_MP_MAX_NUM_CPUS, CONFIG_IDLE_STACK_SIZE); + +static void z_init_static_threads(void) +{ + STRUCT_SECTION_FOREACH(_static_thread_data, thread_data) { + z_setup_new_thread( + thread_data->init_thread, + thread_data->init_stack, + thread_data->init_stack_size, + thread_data->init_entry, + thread_data->init_p1, + thread_data->init_p2, + thread_data->init_p3, + thread_data->init_prio, + thread_data->init_options, + thread_data->init_name); + + thread_data->init_thread->init_data = thread_data; + } + +#ifdef CONFIG_USERSPACE + STRUCT_SECTION_FOREACH(k_object_assignment, pos) { + for (int i = 0; pos->objects[i] != NULL; i++) { + k_object_access_grant(pos->objects[i], + pos->thread); + } + } +#endif + + /* + * Non-legacy static threads may be started immediately or + * after a previously specified delay. Even though the + * scheduler is locked, ticks can still be delivered and + * processed. Take a sched lock to prevent them from running + * until they are all started. + * + * Note that static threads defined using the legacy API have a + * delay of K_FOREVER. + */ + k_sched_lock(); + STRUCT_SECTION_FOREACH(_static_thread_data, thread_data) { + k_timeout_t init_delay = Z_THREAD_INIT_DELAY(thread_data); + + if (!K_TIMEOUT_EQ(init_delay, K_FOREVER)) { + thread_schedule_new(thread_data->init_thread, + init_delay); + } + } + k_sched_unlock(); +} +#else +#define z_init_static_threads() do { } while (false) #endif /* CONFIG_MULTITHREADING */ extern const struct init_entry __init_start[]; @@ -312,6 +364,7 @@ static void z_sys_init_run_level(enum init_level level) extern void boot_banner(void); + /** * @brief Mainline for kernel's background thread * diff --git a/kernel/thread.c b/kernel/thread.c index e0211602847..c94cc302fa0 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -432,21 +433,6 @@ static inline void z_vrfy_k_thread_start(struct k_thread *thread) #endif #endif -#ifdef CONFIG_MULTITHREADING -static void schedule_new_thread(struct k_thread *thread, k_timeout_t delay) -{ -#ifdef CONFIG_SYS_CLOCK_EXISTS - if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) { - k_thread_start(thread); - } else { - z_add_thread_timeout(thread, delay); - } -#else - ARG_UNUSED(delay); - k_thread_start(thread); -#endif -} -#endif #if CONFIG_STACK_POINTER_RANDOM int z_stack_adjust_initialized; @@ -717,7 +703,7 @@ k_tid_t z_impl_k_thread_create(struct k_thread *new_thread, prio, options, NULL); if (!K_TIMEOUT_EQ(delay, K_FOREVER)) { - schedule_new_thread(new_thread, delay); + thread_schedule_new(new_thread, delay); } return new_thread; @@ -789,7 +775,7 @@ k_tid_t z_vrfy_k_thread_create(struct k_thread *new_thread, entry, p1, p2, p3, prio, options, NULL); if (!K_TIMEOUT_EQ(delay, K_FOREVER)) { - schedule_new_thread(new_thread, delay); + thread_schedule_new(new_thread, delay); } return new_thread; @@ -798,64 +784,6 @@ k_tid_t z_vrfy_k_thread_create(struct k_thread *new_thread, #endif /* CONFIG_USERSPACE */ #endif /* CONFIG_MULTITHREADING */ -#ifdef CONFIG_MULTITHREADING -#ifdef CONFIG_USERSPACE - -static void grant_static_access(void) -{ - STRUCT_SECTION_FOREACH(k_object_assignment, pos) { - for (int i = 0; pos->objects[i] != NULL; i++) { - k_object_access_grant(pos->objects[i], - pos->thread); - } - } -} -#endif /* CONFIG_USERSPACE */ - -void z_init_static_threads(void) -{ - _FOREACH_STATIC_THREAD(thread_data) { - z_setup_new_thread( - thread_data->init_thread, - thread_data->init_stack, - thread_data->init_stack_size, - thread_data->init_entry, - thread_data->init_p1, - thread_data->init_p2, - thread_data->init_p3, - thread_data->init_prio, - thread_data->init_options, - thread_data->init_name); - - thread_data->init_thread->init_data = thread_data; - } - -#ifdef CONFIG_USERSPACE - grant_static_access(); -#endif - - /* - * Non-legacy static threads may be started immediately or - * after a previously specified delay. Even though the - * scheduler is locked, ticks can still be delivered and - * processed. Take a sched lock to prevent them from running - * until they are all started. - * - * Note that static threads defined using the legacy API have a - * delay of K_FOREVER. - */ - k_sched_lock(); - _FOREACH_STATIC_THREAD(thread_data) { - k_timeout_t init_delay = Z_THREAD_INIT_DELAY(thread_data); - - if (!K_TIMEOUT_EQ(init_delay, K_FOREVER)) { - schedule_new_thread(thread_data->init_thread, - init_delay); - } - } - k_sched_unlock(); -} -#endif void z_init_thread_base(struct _thread_base *thread_base, int priority, uint32_t initial_state, unsigned int options) From 5e591c38f19a5716caf591ae41aed980414c4af9 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Sat, 24 Feb 2024 10:37:06 -0500 Subject: [PATCH 0256/2402] kernel: do not export z_thread_priority_set This function is only being used by a test, so instead of reimplementing a syscall in the test, provide a Kconfig option to provide the functionality that only works with tests and remove some of the duplication and extra code. Signed-off-by: Anas Nashif --- kernel/Kconfig | 7 +++++++ kernel/include/ksched.h | 1 - kernel/sched.c | 21 +++++++-------------- tests/benchmarks/app_kernel/prj_user.conf | 1 + tests/benchmarks/app_kernel/src/master.c | 23 ----------------------- tests/benchmarks/app_kernel/src/pipe_b.c | 4 ++-- 6 files changed, 17 insertions(+), 40 deletions(-) diff --git a/kernel/Kconfig b/kernel/Kconfig index 9a326bf546e..db3990ee9a7 100644 --- a/kernel/Kconfig +++ b/kernel/Kconfig @@ -208,6 +208,13 @@ config THREAD_USERSPACE_LOCAL_DATA depends on USERSPACE default y if ERRNO && !ERRNO_IN_TLS && !LIBC_ERRNO +config USERSPACE_THREAD_MAY_RAISE_PRIORITY + bool "Thread can raise own priority" + depends on USERSPACE + depends on TEST # This should only be enabled by tests. + help + Thread can raise its own priority in userspace mode. + config DYNAMIC_THREAD bool "Support for dynamic threads [EXPERIMENTAL]" select EXPERIMENTAL diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index e2929b89713..499c00d0c3d 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -51,7 +51,6 @@ void z_reschedule_irqlock(uint32_t key); struct k_thread *z_unpend_first_thread(_wait_q_t *wait_q); void z_unpend_thread(struct k_thread *thread); int z_unpend_all(_wait_q_t *wait_q); -void z_thread_priority_set(struct k_thread *thread, int prio); bool z_set_prio(struct k_thread *thread, int prio); void *z_get_next_switch_handle(void *interrupted); void idle(void *unused1, void *unused2, void *unused3); diff --git a/kernel/sched.c b/kernel/sched.c index deb045ed591..703b6adc6a4 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -1013,17 +1013,6 @@ bool z_set_prio(struct k_thread *thread, int prio) return need_sched; } -void z_thread_priority_set(struct k_thread *thread, int prio) -{ - bool need_sched = z_set_prio(thread, prio); - - flag_ipi(); - - if (need_sched && _current->base.sched_locked == 0U) { - z_reschedule_unlocked(); - } -} - static inline bool resched(uint32_t key) { #ifdef CONFIG_SMP @@ -1286,9 +1275,12 @@ void z_impl_k_thread_priority_set(k_tid_t thread, int prio) Z_ASSERT_VALID_PRIO(prio, NULL); __ASSERT(!arch_is_in_isr(), ""); - struct k_thread *th = (struct k_thread *)thread; + bool need_sched = z_set_prio((struct k_thread *)thread, prio); - z_thread_priority_set(th, prio); + flag_ipi(); + if (need_sched && _current->base.sched_locked == 0U) { + z_reschedule_unlocked(); + } } #ifdef CONFIG_USERSPACE @@ -1297,10 +1289,11 @@ static inline void z_vrfy_k_thread_priority_set(k_tid_t thread, int prio) K_OOPS(K_SYSCALL_OBJ(thread, K_OBJ_THREAD)); K_OOPS(K_SYSCALL_VERIFY_MSG(_is_valid_prio(prio, NULL), "invalid thread priority %d", prio)); +#ifndef CONFIG_USERSPACE_THREAD_MAY_RAISE_PRIORITY K_OOPS(K_SYSCALL_VERIFY_MSG((int8_t)prio >= thread->base.prio, "thread priority may only be downgraded (%d < %d)", prio, thread->base.prio)); - +#endif z_impl_k_thread_priority_set(thread, prio); } #include diff --git a/tests/benchmarks/app_kernel/prj_user.conf b/tests/benchmarks/app_kernel/prj_user.conf index e890dbf3c8e..fd222e6fb14 100644 --- a/tests/benchmarks/app_kernel/prj_user.conf +++ b/tests/benchmarks/app_kernel/prj_user.conf @@ -25,3 +25,4 @@ CONFIG_USERSPACE=y # Disable time slicing CONFIG_TIMESLICING=n +CONFIG_USERSPACE_THREAD_MAY_RAISE_PRIORITY=y diff --git a/tests/benchmarks/app_kernel/src/master.c b/tests/benchmarks/app_kernel/src/master.c index 0b5c8976910..ba0cf53a4f7 100644 --- a/tests/benchmarks/app_kernel/src/master.c +++ b/tests/benchmarks/app_kernel/src/master.c @@ -78,29 +78,6 @@ K_PIPE_DEFINE(PIPE_BIGBUFF, 4096, 4); * Custom syscalls */ -/** - * @brief Change a thread's priority - * - * Unlike the normal k_thread_priority_set(), this custom syscall allows - * a user thread to raise its priority. - */ -void z_impl_test_thread_priority_set(k_tid_t thread, int prio) -{ - extern void z_thread_priority_set(struct k_thread *thread, int prio); - - z_thread_priority_set((struct k_thread *)thread, prio); -} - - -#ifdef CONFIG_USERSPACE -static void z_vrfy_test_thread_priority_set(k_tid_t thread, int prio) -{ - z_impl_test_thread_priority_set(thread, prio); -} - -#include -#endif - /** * @brief Obtain a timestamp * diff --git a/tests/benchmarks/app_kernel/src/pipe_b.c b/tests/benchmarks/app_kernel/src/pipe_b.c index 921f217b638..3589b73806a 100644 --- a/tests/benchmarks/app_kernel/src/pipe_b.c +++ b/tests/benchmarks/app_kernel/src/pipe_b.c @@ -115,7 +115,7 @@ void pipe_test(void) PRINT_STRING("| " "non-matching sizes (1_TO_N) to lower priority" " |\n"); - test_thread_priority_set(k_current_get(), TaskPrio - 2); + k_thread_priority_set(k_current_get(), TaskPrio - 2); } PRINT_STRING(dashline); PRINT_1_TO_N_HEADER(); @@ -136,7 +136,7 @@ void pipe_test(void) PRINT_1_TO_N(); } PRINT_STRING(dashline); - test_thread_priority_set(k_current_get(), TaskPrio); + k_thread_priority_set(k_current_get(), TaskPrio); } } From e10665531f1544e1990ad3eadbe7cda319ad613d Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Wed, 6 Mar 2024 14:09:40 -0500 Subject: [PATCH 0257/2402] spelling: add enabeld typo add typo of enabeld. Signed-off-by: Anas Nashif --- scripts/spelling.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/spelling.txt b/scripts/spelling.txt index ffa9e7cb8e3..c06453a7aee 100644 --- a/scripts/spelling.txt +++ b/scripts/spelling.txt @@ -589,6 +589,7 @@ embeded||embedded enabledi||enabled enbale||enable enble||enable +enabeld||enabled enchanced||enhanced encorporating||incorporating encrupted||encrypted From 9e834135423d5c54194a1b2502d2a267c3d44534 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 26 Feb 2024 17:03:35 -0500 Subject: [PATCH 0258/2402] kernel: split thread monitor Move thread monitor related functions, not enabled in most cases outside of thread.c and cleanup headers. Signed-off-by: Anas Nashif --- kernel/CMakeLists.txt | 7 +++ kernel/Kconfig | 1 + kernel/include/kernel_internal.h | 9 ---- kernel/include/kthread.h | 19 +++++++ kernel/sched.c | 1 + kernel/thread.c | 92 -------------------------------- kernel/thread_monitor.c | 85 +++++++++++++++++++++++++++++ 7 files changed, 113 insertions(+), 101 deletions(-) create mode 100644 kernel/thread_monitor.c diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt index 6a397318681..760f46b1bd5 100644 --- a/kernel/CMakeLists.txt +++ b/kernel/CMakeLists.txt @@ -101,6 +101,13 @@ list(APPEND kernel_files ) endif() + +if(CONFIG_THREAD_MONITOR) +list(APPEND kernel_files + thread_monitor.c) +endif() + + if(CONFIG_XIP) list(APPEND kernel_files xip.c) diff --git a/kernel/Kconfig b/kernel/Kconfig index db3990ee9a7..4cb1a17b704 100644 --- a/kernel/Kconfig +++ b/kernel/Kconfig @@ -220,6 +220,7 @@ config DYNAMIC_THREAD select EXPERIMENTAL depends on THREAD_STACK_INFO select DYNAMIC_OBJECTS if USERSPACE + select THREAD_MONITOR help Enable support for dynamic threads and stacks. diff --git a/kernel/include/kernel_internal.h b/kernel/include/kernel_internal.h index a204cd9b834..34ff4c0f883 100644 --- a/kernel/include/kernel_internal.h +++ b/kernel/include/kernel_internal.h @@ -110,15 +110,6 @@ static inline void *z_thread_malloc(size_t size) return z_thread_aligned_alloc(0, size); } -/* clean up when a thread is aborted */ - -#if defined(CONFIG_THREAD_MONITOR) -extern void z_thread_monitor_exit(struct k_thread *thread); -#else -#define z_thread_monitor_exit(thread) \ - do {/* nothing */ \ - } while (false) -#endif /* CONFIG_THREAD_MONITOR */ #ifdef CONFIG_USE_SWITCH /* This is a arch function traditionally, but when the switch-based diff --git a/kernel/include/kthread.h b/kernel/include/kthread.h index 8cdec848f21..96a41d394a3 100644 --- a/kernel/include/kthread.h +++ b/kernel/include/kthread.h @@ -11,6 +11,25 @@ #include #include +#ifdef CONFIG_THREAD_MONITOR +/* This lock protects the linked list of active threads; i.e. the + * initial _kernel.threads pointer and the linked list made up of + * thread->next_thread (until NULL) + */ +extern struct k_spinlock z_thread_monitor_lock; +#endif + +/* clean up when a thread is aborted */ + +#if defined(CONFIG_THREAD_MONITOR) +void z_thread_monitor_exit(struct k_thread *thread); +#else +#define z_thread_monitor_exit(thread) \ + do {/* nothing */ \ + } while (false) +#endif /* CONFIG_THREAD_MONITOR */ + + #ifdef CONFIG_MULTITHREADING static inline void thread_schedule_new(struct k_thread *thread, k_timeout_t delay) { diff --git a/kernel/sched.c b/kernel/sched.c index 703b6adc6a4..408b7ed08cc 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/kernel/thread.c b/kernel/thread.c index c94cc302fa0..105a753df8c 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -69,75 +69,10 @@ SYS_INIT(init_thread_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); #endif -#ifdef CONFIG_THREAD_MONITOR -/* This lock protects the linked list of active threads; i.e. the - * initial _kernel.threads pointer and the linked list made up of - * thread->next_thread (until NULL) - */ -static struct k_spinlock z_thread_monitor_lock; -#endif /* CONFIG_THREAD_MONITOR */ #define _FOREACH_STATIC_THREAD(thread_data) \ STRUCT_SECTION_FOREACH(_static_thread_data, thread_data) -void k_thread_foreach(k_thread_user_cb_t user_cb, void *user_data) -{ -#if defined(CONFIG_THREAD_MONITOR) - struct k_thread *thread; - k_spinlock_key_t key; - - __ASSERT(user_cb != NULL, "user_cb can not be NULL"); - - /* - * Lock is needed to make sure that the _kernel.threads is not being - * modified by the user_cb either directly or indirectly. - * The indirect ways are through calling k_thread_create and - * k_thread_abort from user_cb. - */ - key = k_spin_lock(&z_thread_monitor_lock); - - SYS_PORT_TRACING_FUNC_ENTER(k_thread, foreach); - - for (thread = _kernel.threads; thread; thread = thread->next_thread) { - user_cb(thread, user_data); - } - - SYS_PORT_TRACING_FUNC_EXIT(k_thread, foreach); - - k_spin_unlock(&z_thread_monitor_lock, key); -#else - ARG_UNUSED(user_cb); - ARG_UNUSED(user_data); -#endif -} - -void k_thread_foreach_unlocked(k_thread_user_cb_t user_cb, void *user_data) -{ -#if defined(CONFIG_THREAD_MONITOR) - struct k_thread *thread; - k_spinlock_key_t key; - - __ASSERT(user_cb != NULL, "user_cb can not be NULL"); - - key = k_spin_lock(&z_thread_monitor_lock); - - SYS_PORT_TRACING_FUNC_ENTER(k_thread, foreach_unlocked); - - for (thread = _kernel.threads; thread; thread = thread->next_thread) { - k_spin_unlock(&z_thread_monitor_lock, key); - user_cb(thread, user_data); - key = k_spin_lock(&z_thread_monitor_lock); - } - - SYS_PORT_TRACING_FUNC_EXIT(k_thread, foreach_unlocked); - - k_spin_unlock(&z_thread_monitor_lock, key); -#else - ARG_UNUSED(user_cb); - ARG_UNUSED(user_data); -#endif -} - bool k_is_in_isr(void) { return arch_is_in_isr(); @@ -173,33 +108,6 @@ static inline void *z_vrfy_k_thread_custom_data_get(void) #endif /* CONFIG_USERSPACE */ #endif /* CONFIG_THREAD_CUSTOM_DATA */ -#if defined(CONFIG_THREAD_MONITOR) -/* - * Remove a thread from the kernel's list of active threads. - */ -void z_thread_monitor_exit(struct k_thread *thread) -{ - k_spinlock_key_t key = k_spin_lock(&z_thread_monitor_lock); - - if (thread == _kernel.threads) { - _kernel.threads = _kernel.threads->next_thread; - } else { - struct k_thread *prev_thread; - - prev_thread = _kernel.threads; - while ((prev_thread != NULL) && - (thread != prev_thread->next_thread)) { - prev_thread = prev_thread->next_thread; - } - if (prev_thread != NULL) { - prev_thread->next_thread = thread->next_thread; - } - } - - k_spin_unlock(&z_thread_monitor_lock, key); -} -#endif - int z_impl_k_thread_name_set(struct k_thread *thread, const char *value) { #ifdef CONFIG_THREAD_NAME diff --git a/kernel/thread_monitor.c b/kernel/thread_monitor.c new file mode 100644 index 00000000000..8861529b888 --- /dev/null +++ b/kernel/thread_monitor.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2010-2014 Wind River Systems, Inc. + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +struct k_spinlock z_thread_monitor_lock; +/* + * Remove a thread from the kernel's list of active threads. + */ +void z_thread_monitor_exit(struct k_thread *thread) +{ + k_spinlock_key_t key = k_spin_lock(&z_thread_monitor_lock); + + if (thread == _kernel.threads) { + _kernel.threads = _kernel.threads->next_thread; + } else { + struct k_thread *prev_thread; + + prev_thread = _kernel.threads; + while ((prev_thread != NULL) && + (thread != prev_thread->next_thread)) { + prev_thread = prev_thread->next_thread; + } + if (prev_thread != NULL) { + prev_thread->next_thread = thread->next_thread; + } + } + + k_spin_unlock(&z_thread_monitor_lock, key); +} + + +void k_thread_foreach(k_thread_user_cb_t user_cb, void *user_data) +{ + struct k_thread *thread; + k_spinlock_key_t key; + + __ASSERT(user_cb != NULL, "user_cb can not be NULL"); + + /* + * Lock is needed to make sure that the _kernel.threads is not being + * modified by the user_cb either directly or indirectly. + * The indirect ways are through calling k_thread_create and + * k_thread_abort from user_cb. + */ + key = k_spin_lock(&z_thread_monitor_lock); + + SYS_PORT_TRACING_FUNC_ENTER(k_thread, foreach); + + for (thread = _kernel.threads; thread; thread = thread->next_thread) { + user_cb(thread, user_data); + } + + SYS_PORT_TRACING_FUNC_EXIT(k_thread, foreach); + + k_spin_unlock(&z_thread_monitor_lock, key); +} + +void k_thread_foreach_unlocked(k_thread_user_cb_t user_cb, void *user_data) +{ + struct k_thread *thread; + k_spinlock_key_t key; + + __ASSERT(user_cb != NULL, "user_cb can not be NULL"); + + key = k_spin_lock(&z_thread_monitor_lock); + + SYS_PORT_TRACING_FUNC_ENTER(k_thread, foreach_unlocked); + + for (thread = _kernel.threads; thread; thread = thread->next_thread) { + k_spin_unlock(&z_thread_monitor_lock, key); + user_cb(thread, user_data); + key = k_spin_lock(&z_thread_monitor_lock); + } + + SYS_PORT_TRACING_FUNC_EXIT(k_thread, foreach_unlocked); + + k_spin_unlock(&z_thread_monitor_lock, key); + +} From 6c003bdbcf8ec181922038f9529681d87cdd1109 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 27 Feb 2024 07:48:45 -0500 Subject: [PATCH 0259/2402] kernel: remove unused code in headers List of functions defined in headers and not being used anywhere. Signed-off-by: Anas Nashif --- kernel/include/ksched.h | 36 ------------------------------------ 1 file changed, 36 deletions(-) diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index 499c00d0c3d..4570a0a7332 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -64,11 +64,6 @@ void z_requeue_current(struct k_thread *curr); struct k_thread *z_swap_next_thread(void); void z_thread_abort(struct k_thread *thread); -static inline void z_pend_curr_unlocked(_wait_q_t *wait_q, k_timeout_t timeout) -{ - (void) z_pend_curr_irqlock(arch_irq_lock(), wait_q, timeout); -} - static inline void z_reschedule_unlocked(void) { (void) z_reschedule_irqlock(arch_irq_lock()); @@ -195,18 +190,6 @@ static inline bool z_is_thread_essential(struct k_thread *thread) return (thread->base.user_options & K_ESSENTIAL) == K_ESSENTIAL; } - -static inline void z_set_thread_states(struct k_thread *thread, uint32_t states) -{ - thread->base.thread_state |= states; -} - -static inline void z_reset_thread_states(struct k_thread *thread, - uint32_t states) -{ - thread->base.thread_state &= ~states; -} - static inline bool z_is_under_prio_ceiling(int prio) { return prio >= CONFIG_PRIORITY_CEILING; @@ -268,15 +251,6 @@ static inline bool _is_valid_prio(int prio, void *entry_point) return true; } -static inline void _ready_one_thread(_wait_q_t *wq) -{ - struct k_thread *thread = z_unpend_first_thread(wq); - - if (thread != NULL) { - z_ready_thread(thread); - } -} - static inline void z_sched_lock(void) { __ASSERT(!arch_is_in_isr(), ""); @@ -287,16 +261,6 @@ static inline void z_sched_lock(void) compiler_barrier(); } -static ALWAYS_INLINE void z_sched_unlock_no_reschedule(void) -{ - __ASSERT(!arch_is_in_isr(), ""); - __ASSERT(_current->base.sched_locked != 0U, ""); - - compiler_barrier(); - - ++_current->base.sched_locked; -} - /* * APIs for working with the Zephyr kernel scheduler. Intended for use in * management of IPC objects, either in the core kernel or other IPC From 3dc0c4544b4f2083cf62117adc24c29239614147 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 27 Feb 2024 08:48:37 -0500 Subject: [PATCH 0260/2402] kernel: move float operations out of thread.c Move float operation out and add missing vrfy hook for enabling float. Signed-off-by: Anas Nashif --- kernel/CMakeLists.txt | 1 + kernel/float.c | 47 +++++++++++++++++++++++++++++++++++++++++++ kernel/thread.c | 30 --------------------------- 3 files changed, 48 insertions(+), 30 deletions(-) create mode 100644 kernel/float.c diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt index 760f46b1bd5..6d40e13d09d 100644 --- a/kernel/CMakeLists.txt +++ b/kernel/CMakeLists.txt @@ -57,6 +57,7 @@ list(APPEND kernel_files init.c kheap.c mem_slab.c + float.c thread.c version.c priority_queues.c diff --git a/kernel/float.c b/kernel/float.c new file mode 100644 index 00000000000..69e806d3cd6 --- /dev/null +++ b/kernel/float.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2010-2014 Wind River Systems, Inc. + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include + +int z_impl_k_float_disable(struct k_thread *thread) +{ +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + return arch_float_disable(thread); +#else + ARG_UNUSED(thread); + return -ENOTSUP; +#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ +} + +int z_impl_k_float_enable(struct k_thread *thread, unsigned int options) +{ +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + return arch_float_enable(thread, options); +#else + ARG_UNUSED(thread); + ARG_UNUSED(options); + return -ENOTSUP; +#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ +} + +#ifdef CONFIG_USERSPACE +static inline int z_vrfy_k_float_disable(struct k_thread *thread) +{ + K_OOPS(K_SYSCALL_OBJ(thread, K_OBJ_THREAD)); + return z_impl_k_float_disable(thread); +} +#include + +static inline int z_vrfy_k_float_enable(struct k_thread *thread, unsigned int options) +{ + K_OOPS(K_SYSCALL_OBJ(thread, K_OBJ_THREAD)); + return z_impl_k_float_enable(thread, options); +} +#include + +#endif /* CONFIG_USERSPACE */ diff --git a/kernel/thread.c b/kernel/thread.c index 105a753df8c..4cb20d30e93 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -751,36 +751,6 @@ FUNC_NORETURN void k_thread_user_mode_enter(k_thread_entry_t entry, #endif } -int z_impl_k_float_disable(struct k_thread *thread) -{ -#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) - return arch_float_disable(thread); -#else - ARG_UNUSED(thread); - return -ENOTSUP; -#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ -} - -int z_impl_k_float_enable(struct k_thread *thread, unsigned int options) -{ -#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) - return arch_float_enable(thread, options); -#else - ARG_UNUSED(thread); - ARG_UNUSED(options); - return -ENOTSUP; -#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ -} - -#ifdef CONFIG_USERSPACE -static inline int z_vrfy_k_float_disable(struct k_thread *thread) -{ - K_OOPS(K_SYSCALL_OBJ(thread, K_OBJ_THREAD)); - return z_impl_k_float_disable(thread); -} -#include -#endif /* CONFIG_USERSPACE */ - #if defined(CONFIG_INIT_STACKS) && defined(CONFIG_THREAD_STACK_INFO) #ifdef CONFIG_STACK_GROWS_UP #error "Unsupported configuration for stack analysis" From 595ff63f00e168603e5e53554b736b5978432d1c Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 27 Feb 2024 09:49:07 -0500 Subject: [PATCH 0261/2402] kernel: thread: use consistent thread parameter Use thread wherever it makes sense, using 't' in some places can get confused with 't' used for timeouts for example. Signed-off-by: Anas Nashif --- kernel/sched.c | 24 ++++++++++++------------ kernel/thread.c | 12 ++++++------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/kernel/sched.c b/kernel/sched.c index 408b7ed08cc..9e50c1844fc 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -223,9 +223,9 @@ static ALWAYS_INLINE struct k_thread *runq_best(void) /* _current is never in the run queue until context switch on * SMP configurations, see z_requeue_current() */ -static inline bool should_queue_thread(struct k_thread *th) +static inline bool should_queue_thread(struct k_thread *thread) { - return !IS_ENABLED(CONFIG_SMP) || th != _current; + return !IS_ENABLED(CONFIG_SMP) || thread != _current; } static ALWAYS_INLINE void queue_thread(struct k_thread *thread) @@ -276,10 +276,10 @@ static void signal_pending_ipi(void) * set of CPUs pick a cycle of threads to run and wait for them all to * context switch forever. */ -void z_requeue_current(struct k_thread *curr) +void z_requeue_current(struct k_thread *thread) { - if (z_is_thread_queued(curr)) { - runq_add(curr); + if (z_is_thread_queued(thread)) { + runq_add(thread); } signal_pending_ipi(); } @@ -467,15 +467,15 @@ static void slice_timeout(struct _timeout *t) } } -void z_reset_time_slice(struct k_thread *curr) +void z_reset_time_slice(struct k_thread *thread) { int cpu = _current_cpu->id; z_abort_timeout(&slice_timeouts[cpu]); slice_expired[cpu] = false; - if (sliceable(curr)) { + if (sliceable(thread)) { z_add_timeout(&slice_timeouts[cpu], slice_timeout, - K_TICKS(slice_time(curr) - 1)); + K_TICKS(slice_time(thread) - 1)); } } @@ -489,13 +489,13 @@ void k_sched_time_slice_set(int32_t slice, int prio) } #ifdef CONFIG_TIMESLICE_PER_THREAD -void k_thread_time_slice_set(struct k_thread *th, int32_t thread_slice_ticks, +void k_thread_time_slice_set(struct k_thread *thread, int32_t thread_slice_ticks, k_thread_timeslice_fn_t expired, void *data) { K_SPINLOCK(&sched_spinlock) { - th->base.slice_ticks = thread_slice_ticks; - th->base.slice_expired = expired; - th->base.slice_data = data; + thread->base.slice_ticks = thread_slice_ticks; + thread->base.slice_expired = expired; + thread->base.slice_data = data; } } #endif diff --git a/kernel/thread.c b/kernel/thread.c index 4cb20d30e93..dc512a456d4 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -844,18 +844,18 @@ int z_vrfy_k_thread_stack_space_get(const struct k_thread *thread, #ifdef CONFIG_USERSPACE static inline k_ticks_t z_vrfy_k_thread_timeout_remaining_ticks( - const struct k_thread *t) + const struct k_thread *thread) { - K_OOPS(K_SYSCALL_OBJ(t, K_OBJ_THREAD)); - return z_impl_k_thread_timeout_remaining_ticks(t); + K_OOPS(K_SYSCALL_OBJ(thread, K_OBJ_THREAD)); + return z_impl_k_thread_timeout_remaining_ticks(thread); } #include static inline k_ticks_t z_vrfy_k_thread_timeout_expires_ticks( - const struct k_thread *t) + const struct k_thread *thread) { - K_OOPS(K_SYSCALL_OBJ(t, K_OBJ_THREAD)); - return z_impl_k_thread_timeout_expires_ticks(t); + K_OOPS(K_SYSCALL_OBJ(thread, K_OBJ_THREAD)); + return z_impl_k_thread_timeout_expires_ticks(thread); } #include #endif From c506cdfece0245060b7f44b25a787916ad108be6 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 27 Feb 2024 18:40:04 -0500 Subject: [PATCH 0262/2402] kernel: rename thread/timeout parameter Using t for both thread and timeout can be confusing at times. Signed-off-by: Anas Nashif --- include/zephyr/kernel.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/include/zephyr/kernel.h b/include/zephyr/kernel.h index 388051f05a6..9a7a141cb6f 100644 --- a/include/zephyr/kernel.h +++ b/include/zephyr/kernel.h @@ -639,12 +639,12 @@ k_ticks_t z_timeout_remaining(const struct _timeout *timeout); * executes, in units of system ticks. If the thread is not waiting, * it returns current system time. */ -__syscall k_ticks_t k_thread_timeout_expires_ticks(const struct k_thread *t); +__syscall k_ticks_t k_thread_timeout_expires_ticks(const struct k_thread *thread); static inline k_ticks_t z_impl_k_thread_timeout_expires_ticks( - const struct k_thread *t) + const struct k_thread *thread) { - return z_timeout_expires(&t->base.timeout); + return z_timeout_expires(&thread->base.timeout); } /** @@ -654,12 +654,12 @@ static inline k_ticks_t z_impl_k_thread_timeout_expires_ticks( * next executes, in units of system ticks. If the thread is not * waiting, it returns zero. */ -__syscall k_ticks_t k_thread_timeout_remaining_ticks(const struct k_thread *t); +__syscall k_ticks_t k_thread_timeout_remaining_ticks(const struct k_thread *thread); static inline k_ticks_t z_impl_k_thread_timeout_remaining_ticks( - const struct k_thread *t) + const struct k_thread *thread) { - return z_timeout_remaining(&t->base.timeout); + return z_timeout_remaining(&thread->base.timeout); } #endif /* CONFIG_SYS_CLOCK_EXISTS */ @@ -5938,7 +5938,7 @@ static inline void k_cpu_atomic_idle(unsigned int key) /** * @internal */ -void z_timer_expiration_handler(struct _timeout *t); +void z_timer_expiration_handler(struct _timeout *timeout); /** * INTERNAL_HIDDEN @endcond */ From 477a04a09830740cb7a8efe49edf3fd8f26d6b6b Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Wed, 28 Feb 2024 08:15:15 -0500 Subject: [PATCH 0263/2402] kernel: rename h -> heap Avoid single characker variables that renders code unreadable and might cause conflicts in maing, similar to t for both timeout and thread in some places. Signed-off-by: Anas Nashif --- kernel/kheap.c | 60 +++++++++++++++++++++++++------------------------- kernel/sched.c | 12 +++++----- 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/kernel/kheap.c b/kernel/kheap.c index 71a3da596ad..fd29df2e92c 100644 --- a/kernel/kheap.c +++ b/kernel/kheap.c @@ -12,17 +12,17 @@ #include #include -void k_heap_init(struct k_heap *h, void *mem, size_t bytes) +void k_heap_init(struct k_heap *heap, void *mem, size_t bytes) { - z_waitq_init(&h->wait_q); - sys_heap_init(&h->heap, mem, bytes); + z_waitq_init(&heap->wait_q); + sys_heap_init(&heap->heap, mem, bytes); - SYS_PORT_TRACING_OBJ_INIT(k_heap, h); + SYS_PORT_TRACING_OBJ_INIT(k_heap, heap); } static int statics_init(void) { - STRUCT_SECTION_FOREACH(k_heap, h) { + STRUCT_SECTION_FOREACH(k_heap, heap) { #if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) /* Some heaps may not present at boot, so we need to wait for * paging mechanism to be initialized before we can initialize @@ -37,17 +37,17 @@ static int statics_init(void) * pinned region as they have already been initialized and * possibly already in use. Otherwise initialize. */ - if (lnkr_is_pinned((uint8_t *)h) && - lnkr_is_pinned((uint8_t *)&h->wait_q) && - lnkr_is_region_pinned((uint8_t *)h->heap.init_mem, - h->heap.init_bytes)) { + if (lnkr_is_pinned((uint8_t *)heap) && + lnkr_is_pinned((uint8_t *)&heap->wait_q) && + lnkr_is_region_pinned((uint8_t *)heap->heap.init_mem, + heap->heap.init_bytes)) { do_clear = !do_clear; } if (do_clear) #endif /* CONFIG_DEMAND_PAGING && !CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT */ { - k_heap_init(h, h->heap.init_mem, h->heap.init_bytes); + k_heap_init(heap, heap->heap.init_mem, heap->heap.init_bytes); } } return 0; @@ -62,22 +62,22 @@ SYS_INIT_NAMED(statics_init_pre, statics_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_ SYS_INIT_NAMED(statics_init_post, statics_init, POST_KERNEL, 0); #endif /* CONFIG_DEMAND_PAGING && !CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT */ -void *k_heap_aligned_alloc(struct k_heap *h, size_t align, size_t bytes, +void *k_heap_aligned_alloc(struct k_heap *heap, size_t align, size_t bytes, k_timeout_t timeout) { k_timepoint_t end = sys_timepoint_calc(timeout); void *ret = NULL; - k_spinlock_key_t key = k_spin_lock(&h->lock); + k_spinlock_key_t key = k_spin_lock(&heap->lock); - SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_heap, aligned_alloc, h, timeout); + SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_heap, aligned_alloc, heap, timeout); __ASSERT(!arch_is_in_isr() || K_TIMEOUT_EQ(timeout, K_NO_WAIT), ""); bool blocked_alloc = false; while (ret == NULL) { - ret = sys_heap_aligned_alloc(&h->heap, align, bytes); + ret = sys_heap_aligned_alloc(&heap->heap, align, bytes); if (!IS_ENABLED(CONFIG_MULTITHREADING) || (ret != NULL) || K_TIMEOUT_EQ(timeout, K_NO_WAIT)) { @@ -87,7 +87,7 @@ void *k_heap_aligned_alloc(struct k_heap *h, size_t align, size_t bytes, if (!blocked_alloc) { blocked_alloc = true; - SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_heap, aligned_alloc, h, timeout); + SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_heap, aligned_alloc, heap, timeout); } else { /** * @todo Trace attempt to avoid empty trace segments @@ -95,37 +95,37 @@ void *k_heap_aligned_alloc(struct k_heap *h, size_t align, size_t bytes, } timeout = sys_timepoint_timeout(end); - (void) z_pend_curr(&h->lock, key, &h->wait_q, timeout); - key = k_spin_lock(&h->lock); + (void) z_pend_curr(&heap->lock, key, &heap->wait_q, timeout); + key = k_spin_lock(&heap->lock); } - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_heap, aligned_alloc, h, timeout, ret); + SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_heap, aligned_alloc, heap, timeout, ret); - k_spin_unlock(&h->lock, key); + k_spin_unlock(&heap->lock, key); return ret; } -void *k_heap_alloc(struct k_heap *h, size_t bytes, k_timeout_t timeout) +void *k_heap_alloc(struct k_heap *heap, size_t bytes, k_timeout_t timeout) { - SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_heap, alloc, h, timeout); + SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_heap, alloc, heap, timeout); - void *ret = k_heap_aligned_alloc(h, sizeof(void *), bytes, timeout); + void *ret = k_heap_aligned_alloc(heap, sizeof(void *), bytes, timeout); - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_heap, alloc, h, timeout, ret); + SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_heap, alloc, heap, timeout, ret); return ret; } -void k_heap_free(struct k_heap *h, void *mem) +void k_heap_free(struct k_heap *heap, void *mem) { - k_spinlock_key_t key = k_spin_lock(&h->lock); + k_spinlock_key_t key = k_spin_lock(&heap->lock); - sys_heap_free(&h->heap, mem); + sys_heap_free(&heap->heap, mem); - SYS_PORT_TRACING_OBJ_FUNC(k_heap, free, h); - if (IS_ENABLED(CONFIG_MULTITHREADING) && z_unpend_all(&h->wait_q) != 0) { - z_reschedule(&h->lock, key); + SYS_PORT_TRACING_OBJ_FUNC(k_heap, free, heap); + if (IS_ENABLED(CONFIG_MULTITHREADING) && z_unpend_all(&heap->wait_q) != 0) { + z_reschedule(&heap->lock, key); } else { - k_spin_unlock(&h->lock, key); + k_spin_unlock(&heap->lock, key); } } diff --git a/kernel/sched.c b/kernel/sched.c index 9e50c1844fc..898d8faf673 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -452,9 +452,9 @@ static inline bool sliceable(struct k_thread *thread) return ret; } -static void slice_timeout(struct _timeout *t) +static void slice_timeout(struct _timeout *timeout) { - int cpu = ARRAY_INDEX(slice_timeouts, t); + int cpu = ARRAY_INDEX(slice_timeouts, timeout); slice_expired[cpu] = true; @@ -1225,20 +1225,20 @@ int z_unpend_all(_wait_q_t *wait_q) return need_sched; } -void init_ready_q(struct _ready_q *rq) +void init_ready_q(struct _ready_q *ready_q) { #if defined(CONFIG_SCHED_SCALABLE) - rq->runq = (struct _priq_rb) { + ready_q->runq = (struct _priq_rb) { .tree = { .lessthan_fn = z_priq_rb_lessthan, } }; #elif defined(CONFIG_SCHED_MULTIQ) for (int i = 0; i < ARRAY_SIZE(_kernel.ready_q.runq.queues); i++) { - sys_dlist_init(&rq->runq.queues[i]); + sys_dlist_init(&ready_q->runq.queues[i]); } #else - sys_dlist_init(&rq->runq); + sys_dlist_init(&ready_q->runq); #endif } From 868f099d61a451eb57dbf24e117b08fb9610af5a Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Sat, 24 Feb 2024 11:37:56 -0500 Subject: [PATCH 0264/2402] kernel: sched: z_set_prio -> z_thread_prio_set Rename private function to make it clear what priority we are setting and to be consistent across the code. Signed-off-by: Anas Nashif --- kernel/include/ksched.h | 2 +- kernel/mutex.c | 2 +- kernel/sched.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index 4570a0a7332..d63de10c486 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -51,7 +51,7 @@ void z_reschedule_irqlock(uint32_t key); struct k_thread *z_unpend_first_thread(_wait_q_t *wait_q); void z_unpend_thread(struct k_thread *thread); int z_unpend_all(_wait_q_t *wait_q); -bool z_set_prio(struct k_thread *thread, int prio); +bool z_thread_prio_set(struct k_thread *thread, int prio); void *z_get_next_switch_handle(void *interrupted); void idle(void *unused1, void *unused2, void *unused3); void z_time_slice(void); diff --git a/kernel/mutex.c b/kernel/mutex.c index c652fd85b19..808e06eda46 100644 --- a/kernel/mutex.c +++ b/kernel/mutex.c @@ -96,7 +96,7 @@ static bool adjust_owner_prio(struct k_mutex *mutex, int32_t new_prio) 'y' : 'n', new_prio, mutex->owner->base.prio); - return z_set_prio(mutex->owner, new_prio); + return z_thread_prio_set(mutex->owner, new_prio); } return false; } diff --git a/kernel/sched.c b/kernel/sched.c index 898d8faf673..47f05bf1609 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -987,7 +987,7 @@ void z_unpend_thread(struct k_thread *thread) /* Priority set utility that does no rescheduling, it just changes the * run queue state, returning true if a reschedule is needed later. */ -bool z_set_prio(struct k_thread *thread, int prio) +bool z_thread_prio_set(struct k_thread *thread, int prio) { bool need_sched = 0; @@ -1276,7 +1276,7 @@ void z_impl_k_thread_priority_set(k_tid_t thread, int prio) Z_ASSERT_VALID_PRIO(prio, NULL); __ASSERT(!arch_is_in_isr(), ""); - bool need_sched = z_set_prio((struct k_thread *)thread, prio); + bool need_sched = z_thread_prio_set((struct k_thread *)thread, prio); flag_ipi(); if (need_sched && _current->base.sched_locked == 0U) { From 0d8da5ff930cffed6ff470850cdcebb5aeb11bfb Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Wed, 6 Mar 2024 15:59:36 -0500 Subject: [PATCH 0265/2402] kernel: rename scheduler spinlock variable and make it private rename sched_spinlock to _sched_spinglock to maintain it is privacy and to avoid any misuse. Signed-off-by: Anas Nashif --- kernel/cpu_mask.c | 4 +- kernel/include/ksched.h | 4 +- kernel/include/kswap.h | 14 ++--- kernel/mem_domain.c | 2 +- kernel/sched.c | 112 ++++++++++++++++++++-------------------- 5 files changed, 68 insertions(+), 68 deletions(-) diff --git a/kernel/cpu_mask.c b/kernel/cpu_mask.c index 99d8c4c3967..4efeb29035e 100644 --- a/kernel/cpu_mask.c +++ b/kernel/cpu_mask.c @@ -7,7 +7,7 @@ #include #include -extern struct k_spinlock sched_spinlock; +extern struct k_spinlock _sched_spinlock; # ifdef CONFIG_SMP @@ -25,7 +25,7 @@ static int cpu_mask_mod(k_tid_t thread, uint32_t enable_mask, uint32_t disable_m "Running threads cannot change CPU pin"); #endif - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { if (z_is_thread_prevented_from_running(thread)) { thread->base.cpu_mask |= enable_mask; thread->base.cpu_mask &= ~disable_mask; diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index d63de10c486..8a691acb815 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -277,7 +277,7 @@ static inline void z_sched_lock(void) * Given a wait_q, wake up the highest priority thread on the queue. If the * queue was empty just return false. * - * Otherwise, do the following, in order, holding sched_spinlock the entire + * Otherwise, do the following, in order, holding _sched_spinlock the entire * time so that the thread state is guaranteed not to change: * - Set the thread's swap return values to swap_retval and swap_data * - un-pend and ready the thread, but do not invoke the scheduler. @@ -363,7 +363,7 @@ int z_sched_wait(struct k_spinlock *lock, k_spinlock_key_t key, * @brief Walks the wait queue invoking the callback on each waiting thread * * This function walks the wait queue invoking the callback function on each - * waiting thread while holding sched_spinlock. This can be useful for routines + * waiting thread while holding _sched_spinlock. This can be useful for routines * that need to operate on multiple waiting threads. * * CAUTION! As a wait queue is of indeterminate length, the scheduler will be diff --git a/kernel/include/kswap.h b/kernel/include/kswap.h index 01a72744b00..862969ac79a 100644 --- a/kernel/include/kswap.h +++ b/kernel/include/kswap.h @@ -17,7 +17,7 @@ extern void z_check_stack_sentinel(void); #define z_check_stack_sentinel() /**/ #endif -extern struct k_spinlock sched_spinlock; +extern struct k_spinlock _sched_spinlock; /* In SMP, the irq_lock() is a spinlock which is implicitly released * and reacquired on context switch to preserve the existing @@ -112,11 +112,11 @@ static ALWAYS_INLINE unsigned int do_swap(unsigned int key, * have it. We "release" other spinlocks here. But we never * drop the interrupt lock. */ - if (is_spinlock && lock != NULL && lock != &sched_spinlock) { + if (is_spinlock && lock != NULL && lock != &_sched_spinlock) { k_spin_release(lock); } - if (!is_spinlock || lock != &sched_spinlock) { - (void) k_spin_lock(&sched_spinlock); + if (!is_spinlock || lock != &_sched_spinlock) { + (void) k_spin_lock(&_sched_spinlock); } new_thread = z_swap_next_thread(); @@ -141,7 +141,7 @@ static ALWAYS_INLINE unsigned int do_swap(unsigned int key, #endif #ifdef CONFIG_SPIN_VALIDATE - z_spin_lock_set_owner(&sched_spinlock); + z_spin_lock_set_owner(&_sched_spinlock); #endif arch_cohere_stacks(old_thread, NULL, new_thread); @@ -163,10 +163,10 @@ static ALWAYS_INLINE unsigned int do_swap(unsigned int key, new_thread->switch_handle = NULL; barrier_dmem_fence_full(); /* write barrier */ } - k_spin_release(&sched_spinlock); + k_spin_release(&_sched_spinlock); arch_switch(newsh, &old_thread->switch_handle); } else { - k_spin_release(&sched_spinlock); + k_spin_release(&_sched_spinlock); } if (is_spinlock) { diff --git a/kernel/mem_domain.c b/kernel/mem_domain.c index 268d218ce3e..fd8f05344a1 100644 --- a/kernel/mem_domain.c +++ b/kernel/mem_domain.c @@ -306,7 +306,7 @@ void z_mem_domain_init_thread(struct k_thread *thread) k_spin_unlock(&z_mem_domain_lock, key); } -/* Called when thread aborts during teardown tasks. sched_spinlock is held */ +/* Called when thread aborts during teardown tasks. _sched_spinlock is held */ void z_mem_domain_exit_thread(struct k_thread *thread) { int ret; diff --git a/kernel/sched.c b/kernel/sched.c index 47f05bf1609..a2f3e74bfa9 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -23,7 +23,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); -struct k_spinlock sched_spinlock; +struct k_spinlock _sched_spinlock; static void update_cache(int preempt_ok); static void halt_thread(struct k_thread *thread, uint8_t new_state); @@ -481,7 +481,7 @@ void z_reset_time_slice(struct k_thread *thread) void k_sched_time_slice_set(int32_t slice, int prio) { - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { slice_ticks = k_ms_to_ticks_ceil32(slice); slice_max_prio = prio; z_reset_time_slice(_current); @@ -492,7 +492,7 @@ void k_sched_time_slice_set(int32_t slice, int prio) void k_thread_time_slice_set(struct k_thread *thread, int32_t thread_slice_ticks, k_thread_timeslice_fn_t expired, void *data) { - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { thread->base.slice_ticks = thread_slice_ticks; thread->base.slice_expired = expired; thread->base.slice_data = data; @@ -503,13 +503,13 @@ void k_thread_time_slice_set(struct k_thread *thread, int32_t thread_slice_ticks /* Called out of each timer interrupt */ void z_time_slice(void) { - k_spinlock_key_t key = k_spin_lock(&sched_spinlock); + k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); struct k_thread *curr = _current; #ifdef CONFIG_SWAP_NONATOMIC if (pending_current == curr) { z_reset_time_slice(curr); - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); return; } pending_current = NULL; @@ -518,9 +518,9 @@ void z_time_slice(void) if (slice_expired[_current_cpu->id] && sliceable(curr)) { #ifdef CONFIG_TIMESLICE_PER_THREAD if (curr->base.slice_expired) { - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); curr->base.slice_expired(curr, curr->base.slice_data); - key = k_spin_lock(&sched_spinlock); + key = k_spin_lock(&_sched_spinlock); } #endif if (!z_is_thread_prevented_from_running(curr)) { @@ -528,7 +528,7 @@ void z_time_slice(void) } z_reset_time_slice(curr); } - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); } #endif @@ -623,7 +623,7 @@ static void ready_thread(struct k_thread *thread) void z_ready_thread(struct k_thread *thread) { - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { if (!thread_active_elsewhere(thread)) { ready_thread(thread); } @@ -632,23 +632,23 @@ void z_ready_thread(struct k_thread *thread) void z_move_thread_to_end_of_prio_q(struct k_thread *thread) { - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { move_thread_to_end_of_prio_q(thread); } } void z_sched_start(struct k_thread *thread) { - k_spinlock_key_t key = k_spin_lock(&sched_spinlock); + k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); if (z_has_thread_started(thread)) { - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); return; } z_mark_thread_as_started(thread); ready_thread(thread); - z_reschedule(&sched_spinlock, key); + z_reschedule(&_sched_spinlock, key); } /** @@ -664,7 +664,7 @@ void z_sched_start(struct k_thread *thread) * released before this routine returns. * * @param thread Thread to suspend or abort - * @param key Current key for sched_spinlock + * @param key Current key for _sched_spinlock * @param terminate True if aborting thread, false if suspending thread */ static void z_thread_halt(struct k_thread *thread, k_spinlock_key_t key, @@ -699,7 +699,7 @@ static void z_thread_halt(struct k_thread *thread, k_spinlock_key_t key, if (is_halting(thread) && (thread != _current)) { if (arch_is_in_isr()) { /* ISRs can only spin waiting another CPU */ - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); while (is_halting(thread)) { } @@ -707,25 +707,25 @@ static void z_thread_halt(struct k_thread *thread, k_spinlock_key_t key, * halted (suspended or aborted). Wait for the switch * to happen! */ - key = k_spin_lock(&sched_spinlock); + key = k_spin_lock(&_sched_spinlock); z_sched_switch_spin(thread); - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); } else if (active) { /* Threads can wait on a queue */ add_to_waitq_locked(_current, terminate ? &thread->join_queue : &thread->halt_queue); - z_swap(&sched_spinlock, key); + z_swap(&_sched_spinlock, key); } return; /* lock has been released */ } #endif halt_thread(thread, terminate ? _THREAD_DEAD : _THREAD_SUSPENDED); if ((thread == _current) && !arch_is_in_isr()) { - z_swap(&sched_spinlock, key); + z_swap(&_sched_spinlock, key); __ASSERT(!terminate, "aborted _current back from dead"); } else { - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); } } @@ -735,13 +735,13 @@ void z_impl_k_thread_suspend(struct k_thread *thread) (void)z_abort_thread_timeout(thread); - k_spinlock_key_t key = k_spin_lock(&sched_spinlock); + k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); if ((thread->base.thread_state & _THREAD_SUSPENDED) != 0U) { /* The target thread is already suspended. Nothing to do. */ - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); return; } @@ -763,18 +763,18 @@ void z_impl_k_thread_resume(struct k_thread *thread) { SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_thread, resume, thread); - k_spinlock_key_t key = k_spin_lock(&sched_spinlock); + k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); /* Do not try to resume a thread that was not suspended */ if (!z_is_thread_suspended(thread)) { - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); return; } z_mark_thread_as_not_suspended(thread); ready_thread(thread); - z_reschedule(&sched_spinlock, key); + z_reschedule(&_sched_spinlock, key); SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_thread, resume, thread); } @@ -803,7 +803,7 @@ static void unready_thread(struct k_thread *thread) update_cache(thread == _current); } -/* sched_spinlock must be held */ +/* _sched_spinlock must be held */ static void add_to_waitq_locked(struct k_thread *thread, _wait_q_t *wait_q) { unready_thread(thread); @@ -838,7 +838,7 @@ void z_pend_thread(struct k_thread *thread, _wait_q_t *wait_q, k_timeout_t timeout) { __ASSERT_NO_MSG(thread == _current || is_thread_dummy(thread)); - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { pend_locked(thread, wait_q, timeout); } } @@ -852,7 +852,7 @@ static inline void unpend_thread_no_timeout(struct k_thread *thread) ALWAYS_INLINE void z_unpend_thread_no_timeout(struct k_thread *thread) { - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { if (thread->base.pended_on != NULL) { unpend_thread_no_timeout(thread); } @@ -861,7 +861,7 @@ ALWAYS_INLINE void z_unpend_thread_no_timeout(struct k_thread *thread) void z_sched_wake_thread(struct k_thread *thread, bool is_timeout) { - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { bool killed = (thread->base.thread_state & (_THREAD_DEAD | _THREAD_ABORTING)); @@ -914,7 +914,7 @@ int z_pend_curr_irqlock(uint32_t key, _wait_q_t *wait_q, k_timeout_t timeout) pending_current = _current; int ret = z_swap_irqlock(key); - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { if (pending_current == _current) { pending_current = NULL; } @@ -931,7 +931,7 @@ int z_pend_curr(struct k_spinlock *lock, k_spinlock_key_t key, #if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC) pending_current = _current; #endif - __ASSERT_NO_MSG(sizeof(sched_spinlock) == 0 || lock != &sched_spinlock); + __ASSERT_NO_MSG(sizeof(_sched_spinlock) == 0 || lock != &_sched_spinlock); /* We do a "lock swap" prior to calling z_swap(), such that * the caller's lock gets released as desired. But we ensure @@ -941,17 +941,17 @@ int z_pend_curr(struct k_spinlock *lock, k_spinlock_key_t key, * API that doesn't expect to be called with scheduler lock * held. */ - (void) k_spin_lock(&sched_spinlock); + (void) k_spin_lock(&_sched_spinlock); pend_locked(_current, wait_q, timeout); k_spin_release(lock); - return z_swap(&sched_spinlock, key); + return z_swap(&_sched_spinlock, key); } struct k_thread *z_unpend1_no_timeout(_wait_q_t *wait_q) { struct k_thread *thread = NULL; - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { thread = _priq_wait_best(&wait_q->waitq); if (thread != NULL) { @@ -966,7 +966,7 @@ struct k_thread *z_unpend_first_thread(_wait_q_t *wait_q) { struct k_thread *thread = NULL; - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { thread = _priq_wait_best(&wait_q->waitq); if (thread != NULL) { @@ -991,7 +991,7 @@ bool z_thread_prio_set(struct k_thread *thread, int prio) { bool need_sched = 0; - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { need_sched = z_is_thread_ready(thread); if (need_sched) { @@ -1063,7 +1063,7 @@ void z_reschedule_irqlock(uint32_t key) void k_sched_lock(void) { - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { SYS_PORT_TRACING_FUNC(k_thread, sched_lock); z_sched_lock(); @@ -1072,7 +1072,7 @@ void k_sched_lock(void) void k_sched_unlock(void) { - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { __ASSERT(_current->base.sched_locked != 0U, ""); __ASSERT(!arch_is_in_isr(), ""); @@ -1152,7 +1152,7 @@ void *z_get_next_switch_handle(void *interrupted) #ifdef CONFIG_SMP void *ret = NULL; - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { struct k_thread *old_thread = _current, *new_thread; if (IS_ENABLED(CONFIG_SMP)) { @@ -1180,7 +1180,7 @@ void *z_get_next_switch_handle(void *interrupted) * confused when the "wrong" thread tries to * release the lock. */ - z_spin_lock_set_owner(&sched_spinlock); + z_spin_lock_set_owner(&_sched_spinlock); #endif /* A queued (runnable) old/current thread @@ -1305,7 +1305,7 @@ void z_impl_k_thread_deadline_set(k_tid_t tid, int deadline) { struct k_thread *thread = tid; - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { thread->base.prio_deadline = k_cycle_get_32() + deadline; if (z_is_thread_queued(thread)) { dequeue_thread(thread); @@ -1342,7 +1342,7 @@ void z_impl_k_yield(void) SYS_PORT_TRACING_FUNC(k_thread, yield); - k_spinlock_key_t key = k_spin_lock(&sched_spinlock); + k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); if (!IS_ENABLED(CONFIG_SMP) || z_is_thread_queued(_current)) { @@ -1350,7 +1350,7 @@ void z_impl_k_yield(void) } queue_thread(_current); update_cache(1); - z_swap(&sched_spinlock, key); + z_swap(&_sched_spinlock, key); } #ifdef CONFIG_USERSPACE @@ -1385,7 +1385,7 @@ static int32_t z_tick_sleep(k_ticks_t ticks) #ifdef CONFIG_MULTITHREADING k_timeout_t timeout = Z_TIMEOUT_TICKS(ticks); - k_spinlock_key_t key = k_spin_lock(&sched_spinlock); + k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); #if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC) pending_current = _current; @@ -1394,7 +1394,7 @@ static int32_t z_tick_sleep(k_ticks_t ticks) z_add_thread_timeout(_current, timeout); z_mark_thread_as_suspended(_current); - (void)z_swap(&sched_spinlock, key); + (void)z_swap(&_sched_spinlock, key); __ASSERT(!z_is_thread_state_set(_current, _THREAD_SUSPENDED), ""); @@ -1489,7 +1489,7 @@ void z_impl_k_wakeup(k_tid_t thread) } } - k_spinlock_key_t key = k_spin_lock(&sched_spinlock); + k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); z_mark_thread_as_not_suspended(thread); @@ -1498,9 +1498,9 @@ void z_impl_k_wakeup(k_tid_t thread) } if (arch_is_in_isr()) { - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); } else { - z_reschedule(&sched_spinlock, key); + z_reschedule(&_sched_spinlock, key); } } @@ -1655,17 +1655,17 @@ static void halt_thread(struct k_thread *thread, uint8_t new_state) void z_thread_abort(struct k_thread *thread) { - k_spinlock_key_t key = k_spin_lock(&sched_spinlock); + k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); if (z_is_thread_essential(thread)) { - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); __ASSERT(false, "aborting essential thread %p", thread); k_panic(); return; } if ((thread->base.thread_state & _THREAD_DEAD) != 0U) { - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); return; } @@ -1685,7 +1685,7 @@ void z_impl_k_thread_abort(struct k_thread *thread) int z_impl_k_thread_join(struct k_thread *thread, k_timeout_t timeout) { - k_spinlock_key_t key = k_spin_lock(&sched_spinlock); + k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); int ret = 0; SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_thread, join, thread, timeout); @@ -1704,7 +1704,7 @@ int z_impl_k_thread_join(struct k_thread *thread, k_timeout_t timeout) add_thread_timeout(_current, timeout); SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_thread, join, thread, timeout); - ret = z_swap(&sched_spinlock, key); + ret = z_swap(&_sched_spinlock, key); SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_thread, join, thread, timeout, ret); return ret; @@ -1712,7 +1712,7 @@ int z_impl_k_thread_join(struct k_thread *thread, k_timeout_t timeout) SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_thread, join, thread, timeout, ret); - k_spin_unlock(&sched_spinlock, key); + k_spin_unlock(&_sched_spinlock, key); return ret; } @@ -1777,7 +1777,7 @@ bool z_sched_wake(_wait_q_t *wait_q, int swap_retval, void *swap_data) struct k_thread *thread; bool ret = false; - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { thread = _priq_wait_best(&wait_q->waitq); if (thread != NULL) { @@ -1811,7 +1811,7 @@ int z_sched_waitq_walk(_wait_q_t *wait_q, struct k_thread *thread; int status = 0; - K_SPINLOCK(&sched_spinlock) { + K_SPINLOCK(&_sched_spinlock) { _WAIT_Q_FOR_EACH(wait_q, thread) { /* From d7223e7bba84b3395a695c8371b117f91ba9b771 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Wed, 6 Mar 2024 21:31:03 -0500 Subject: [PATCH 0266/2402] samples: pong: k_thread_foreach needs CONFIG_THREAD_MONITOR When debugging and dumping thread related info, CONFIG_THREAD_MONITOR is needed. Signed-off-by: Anas Nashif --- samples/boards/bbc_microbit/pong/src/main.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/samples/boards/bbc_microbit/pong/src/main.c b/samples/boards/bbc_microbit/pong/src/main.c index 1e0ed6ac659..a8a85b3fc3a 100644 --- a/samples/boards/bbc_microbit/pong/src/main.c +++ b/samples/boards/bbc_microbit/pong/src/main.c @@ -304,18 +304,22 @@ static void game_ended(bool won) k_work_reschedule(&refresh, K_MSEC(RESTART_THRESHOLD)); } +#if CONFIG_THREAD_MONITOR static void game_stack_dump(const struct k_thread *thread, void *user_data) { ARG_UNUSED(user_data); log_stack_usage(thread); } +#endif static void game_refresh(struct k_work *work) { if (sound_state != SOUND_IDLE) { sound_set(SOUND_IDLE); +#if CONFIG_THREAD_MONITOR k_thread_foreach(game_stack_dump, NULL); +#endif } if (pg_state == INIT) { From 6a4514ddc070f4df39be3d11425dba94e891e81b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Stenberg?= Date: Wed, 6 Mar 2024 13:52:57 +0100 Subject: [PATCH 0267/2402] adc: Use int64_t in voltage divider calculation to avoid overflow MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit int32_t overflows above 1.3kOhm if using vref 3300 mV. Signed-off-by: Björn Stenberg --- include/zephyr/drivers/adc/voltage_divider.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/drivers/adc/voltage_divider.h b/include/zephyr/drivers/adc/voltage_divider.h index 692442d4b38..caf6f821ff2 100644 --- a/include/zephyr/drivers/adc/voltage_divider.h +++ b/include/zephyr/drivers/adc/voltage_divider.h @@ -51,7 +51,7 @@ static inline int voltage_divider_scale_dt(const struct voltage_divider_dt_spec } /* voltage scaled by voltage divider values using DT binding */ - *v_to_v = *v_to_v * spec->full_ohms / spec->output_ohms; + *v_to_v = (int64_t)*v_to_v * spec->full_ohms / spec->output_ohms; return 0; } From 7a0398e65711a980e4e3eec328754d4dd0a34adf Mon Sep 17 00:00:00 2001 From: Iuliana Prodan Date: Tue, 5 Mar 2024 01:23:14 +0200 Subject: [PATCH 0268/2402] boards: nxp: set correct rimage target for ADSP Fix typo for rimage target name for imx8qm and imx8qxp boards. For both, rimage name is imx8. Signed-off-by: Iuliana Prodan --- boards/nxp/imx8qm_mek/board.cmake | 2 +- boards/nxp/imx8qxp_mek/board.cmake | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/nxp/imx8qm_mek/board.cmake b/boards/nxp/imx8qm_mek/board.cmake index 0924bf99eec..ad24e2b6c35 100644 --- a/boards/nxp/imx8qm_mek/board.cmake +++ b/boards/nxp/imx8qm_mek/board.cmake @@ -8,5 +8,5 @@ if(CONFIG_SOC_MIMX8QM_ADSP) board_set_flasher_ifnset(misc-flasher) board_finalize_runner_args(misc-flasher) - board_set_rimage_target(imx) + board_set_rimage_target(imx8) endif() diff --git a/boards/nxp/imx8qxp_mek/board.cmake b/boards/nxp/imx8qxp_mek/board.cmake index 699964c5e39..50123811d4d 100644 --- a/boards/nxp/imx8qxp_mek/board.cmake +++ b/boards/nxp/imx8qxp_mek/board.cmake @@ -8,5 +8,5 @@ if(CONFIG_SOC_MIMX8QXP_ADSP) board_set_flasher_ifnset(misc-flasher) board_finalize_runner_args(misc-flasher) - board_set_rimage_target(imx) + board_set_rimage_target(imx8) endif() From 76015745df1d02a01dd240ffa7df95a65cbd0c5b Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 4 Mar 2024 09:45:12 +0100 Subject: [PATCH 0269/2402] Bluetooth: ATT: lock scheduler when sending from user thread `att_req_send_process` is not thread safe. In the case where the current context is pre-emptible (e.g. when a user sends something over GATT from the main thread): The iterator in `att_req_send_process` can get interrupted mid-processing, breaking the logic and resulting in an assert/crash/data corruption. Additionally, the connection state check in this fn is also not thread-safe, the RX thread could pre-empt us and disconnect right before we attempt to send on an ATT bearer that is on it. This is a hotfix until we have a generalized solution for the host API surface. It seems a lot of our logic assumes cooperative priority. Signed-off-by: Jonathan Rico --- subsys/bluetooth/host/att.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/subsys/bluetooth/host/att.c b/subsys/bluetooth/host/att.c index 35be784c209..2ed3dfcb768 100644 --- a/subsys/bluetooth/host/att.c +++ b/subsys/bluetooth/host/att.c @@ -3863,14 +3863,19 @@ int bt_att_req_send(struct bt_conn *conn, struct bt_att_req *req) __ASSERT_NO_MSG(conn); __ASSERT_NO_MSG(req); + k_sched_lock(); + att = att_get(conn); if (!att) { + k_sched_unlock(); return -ENOTCONN; } sys_slist_append(&att->reqs, &req->node); att_req_send_process(att); + k_sched_unlock(); + return 0; } From 3a927a283399a7c85a1cc10a4f8356456e5318d3 Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Fri, 1 Mar 2024 15:29:10 +0800 Subject: [PATCH 0270/2402] Bluetooth: Host: Move BR/EDR files to host/classic Add subfolder "subsys/bluetooth/host/classic". Move BR/EDR source files to the subfolder. Signed-off-by: Lyle Zhu --- subsys/bluetooth/host/CMakeLists.txt | 20 ++-------------- subsys/bluetooth/host/Kconfig | 8 +++++++ subsys/bluetooth/host/classic/CMakeLists.txt | 23 +++++++++++++++++++ subsys/bluetooth/host/{ => classic}/a2dp.c | 4 ++-- .../host/{ => classic}/a2dp_internal.h | 0 subsys/bluetooth/host/{ => classic}/at.c | 0 subsys/bluetooth/host/{ => classic}/at.h | 0 subsys/bluetooth/host/{ => classic}/avdtp.c | 4 ++-- .../host/{ => classic}/avdtp_internal.h | 0 subsys/bluetooth/host/{ => classic}/br.c | 6 ++--- subsys/bluetooth/host/{ => classic}/br.h | 0 subsys/bluetooth/host/{ => classic}/hfp_hf.c | 4 ++-- .../host/{ => classic}/hfp_internal.h | 0 subsys/bluetooth/host/{ => classic}/keys_br.c | 6 ++--- .../bluetooth/host/{ => classic}/l2cap_br.c | 4 ++-- .../host/{ => classic}/l2cap_br_interface.h | 0 .../host/{ => classic}/l2cap_br_internal.h | 0 subsys/bluetooth/host/{ => classic}/rfcomm.c | 4 ++-- .../host/{ => classic}/rfcomm_internal.h | 0 subsys/bluetooth/host/{ => classic}/sdp.c | 4 ++-- .../host/{ => classic}/sdp_internal.h | 0 subsys/bluetooth/host/{ => classic}/ssp.c | 6 ++--- subsys/bluetooth/host/{ => classic}/ssp.h | 0 subsys/bluetooth/host/conn.c | 2 +- subsys/bluetooth/host/hci_core.c | 2 +- subsys/bluetooth/host/l2cap_internal.h | 2 +- tests/bluetooth/at/src/main.c | 2 +- 27 files changed, 58 insertions(+), 43 deletions(-) create mode 100644 subsys/bluetooth/host/classic/CMakeLists.txt rename subsys/bluetooth/host/{ => classic}/a2dp.c (98%) rename subsys/bluetooth/host/{ => classic}/a2dp_internal.h (100%) rename subsys/bluetooth/host/{ => classic}/at.c (100%) rename subsys/bluetooth/host/{ => classic}/at.h (100%) rename subsys/bluetooth/host/{ => classic}/avdtp.c (99%) rename subsys/bluetooth/host/{ => classic}/avdtp_internal.h (100%) rename subsys/bluetooth/host/{ => classic}/br.c (99%) rename subsys/bluetooth/host/{ => classic}/br.h (100%) rename subsys/bluetooth/host/{ => classic}/hfp_hf.c (99%) rename subsys/bluetooth/host/{ => classic}/hfp_internal.h (100%) rename subsys/bluetooth/host/{ => classic}/keys_br.c (98%) rename subsys/bluetooth/host/{ => classic}/l2cap_br.c (99%) rename subsys/bluetooth/host/{ => classic}/l2cap_br_interface.h (100%) rename subsys/bluetooth/host/{ => classic}/l2cap_br_internal.h (100%) rename subsys/bluetooth/host/{ => classic}/rfcomm.c (99%) rename subsys/bluetooth/host/{ => classic}/rfcomm_internal.h (100%) rename subsys/bluetooth/host/{ => classic}/sdp.c (99%) rename subsys/bluetooth/host/{ => classic}/sdp_internal.h (100%) rename subsys/bluetooth/host/{ => classic}/ssp.c (99%) rename subsys/bluetooth/host/{ => classic}/ssp.h (100%) diff --git a/subsys/bluetooth/host/CMakeLists.txt b/subsys/bluetooth/host/CMakeLists.txt index e5ac8c707e0..56cdfb04575 100644 --- a/subsys/bluetooth/host/CMakeLists.txt +++ b/subsys/bluetooth/host/CMakeLists.txt @@ -3,32 +3,16 @@ zephyr_library() zephyr_library_link_libraries(subsys__bluetooth) +add_subdirectory_ifdef(CONFIG_BT_CLASSIC classic) + zephyr_library_sources_ifdef(CONFIG_BT_HCI_RAW hci_raw.c hci_common.c) zephyr_library_sources_ifdef(CONFIG_BT_MONITOR monitor.c) zephyr_library_sources_ifdef(CONFIG_BT_TINYCRYPT_ECC hci_ecc.c) -zephyr_library_sources_ifdef(CONFIG_BT_A2DP a2dp.c) -zephyr_library_sources_ifdef(CONFIG_BT_AVDTP avdtp.c) -zephyr_library_sources_ifdef(CONFIG_BT_RFCOMM rfcomm.c) zephyr_library_sources_ifdef(CONFIG_BT_TESTING testing.c) zephyr_library_sources_ifdef(CONFIG_BT_SETTINGS settings.c) zephyr_library_sources_ifdef(CONFIG_BT_HOST_CCM aes_ccm.c) zephyr_library_sources_ifdef(CONFIG_BT_LONG_WQ long_wq.c) -zephyr_library_sources_ifdef( - CONFIG_BT_BREDR - br.c - keys_br.c - l2cap_br.c - sdp.c - ssp.c - ) - -zephyr_library_sources_ifdef( - CONFIG_BT_HFP_HF - hfp_hf.c - at.c - ) - if(CONFIG_BT_HCI_HOST) zephyr_library_sources( uuid.c diff --git a/subsys/bluetooth/host/Kconfig b/subsys/bluetooth/host/Kconfig index aae4a5151f9..0b0e75dee18 100644 --- a/subsys/bluetooth/host/Kconfig +++ b/subsys/bluetooth/host/Kconfig @@ -1029,6 +1029,7 @@ config BT_CONN_DISABLE_SECURITY config BT_BREDR bool "Bluetooth BR/EDR support [EXPERIMENTAL]" depends on BT_HCI_HOST + select BT_CLASSIC select BT_PERIPHERAL select BT_CENTRAL select BT_SMP @@ -1037,6 +1038,13 @@ config BT_BREDR help This option enables Bluetooth BR/EDR support +config BT_CLASSIC + bool "Bluetooth classic(BR/EDR) support [EXPERIMENTAL]" + depends on BT_BREDR + select EXPERIMENTAL + help + This option enables Bluetooth classic(BR/EDR) support + if BT_BREDR config BT_MAX_SCO_CONN int "Maximum number of simultaneous SCO connections" diff --git a/subsys/bluetooth/host/classic/CMakeLists.txt b/subsys/bluetooth/host/classic/CMakeLists.txt new file mode 100644 index 00000000000..b36e3a46db3 --- /dev/null +++ b/subsys/bluetooth/host/classic/CMakeLists.txt @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_link_libraries(subsys__bluetooth) + +zephyr_library_sources_ifdef(CONFIG_BT_A2DP a2dp.c) +zephyr_library_sources_ifdef(CONFIG_BT_AVDTP avdtp.c) +zephyr_library_sources_ifdef(CONFIG_BT_RFCOMM rfcomm.c) + +zephyr_library_sources_ifdef( + CONFIG_BT_BREDR + br.c + keys_br.c + l2cap_br.c + sdp.c + ssp.c + ) + +zephyr_library_sources_ifdef( + CONFIG_BT_HFP_HF + hfp_hf.c + at.c + ) diff --git a/subsys/bluetooth/host/a2dp.c b/subsys/bluetooth/host/classic/a2dp.c similarity index 98% rename from subsys/bluetooth/host/a2dp.c rename to subsys/bluetooth/host/classic/a2dp.c index 1af7753306e..f6eda168127 100644 --- a/subsys/bluetooth/host/a2dp.c +++ b/subsys/bluetooth/host/classic/a2dp.c @@ -23,8 +23,8 @@ #include "common/assert.h" -#include "hci_core.h" -#include "conn_internal.h" +#include "host/hci_core.h" +#include "host/conn_internal.h" #include "avdtp_internal.h" #include "a2dp_internal.h" diff --git a/subsys/bluetooth/host/a2dp_internal.h b/subsys/bluetooth/host/classic/a2dp_internal.h similarity index 100% rename from subsys/bluetooth/host/a2dp_internal.h rename to subsys/bluetooth/host/classic/a2dp_internal.h diff --git a/subsys/bluetooth/host/at.c b/subsys/bluetooth/host/classic/at.c similarity index 100% rename from subsys/bluetooth/host/at.c rename to subsys/bluetooth/host/classic/at.c diff --git a/subsys/bluetooth/host/at.h b/subsys/bluetooth/host/classic/at.h similarity index 100% rename from subsys/bluetooth/host/at.h rename to subsys/bluetooth/host/classic/at.h diff --git a/subsys/bluetooth/host/avdtp.c b/subsys/bluetooth/host/classic/avdtp.c similarity index 99% rename from subsys/bluetooth/host/avdtp.c rename to subsys/bluetooth/host/classic/avdtp.c index 9f9b63dfe4f..aee20f53532 100644 --- a/subsys/bluetooth/host/avdtp.c +++ b/subsys/bluetooth/host/classic/avdtp.c @@ -18,8 +18,8 @@ #include #include -#include "hci_core.h" -#include "conn_internal.h" +#include "host/hci_core.h" +#include "host/conn_internal.h" #include "l2cap_br_internal.h" #include "avdtp_internal.h" diff --git a/subsys/bluetooth/host/avdtp_internal.h b/subsys/bluetooth/host/classic/avdtp_internal.h similarity index 100% rename from subsys/bluetooth/host/avdtp_internal.h rename to subsys/bluetooth/host/classic/avdtp_internal.h diff --git a/subsys/bluetooth/host/br.c b/subsys/bluetooth/host/classic/br.c similarity index 99% rename from subsys/bluetooth/host/br.c rename to subsys/bluetooth/host/classic/br.c index 8eaf382c9a2..54321a3dfc7 100644 --- a/subsys/bluetooth/host/br.c +++ b/subsys/bluetooth/host/classic/br.c @@ -13,9 +13,9 @@ #include "common/bt_str.h" -#include "hci_core.h" -#include "conn_internal.h" -#include "keys.h" +#include "host/hci_core.h" +#include "host/conn_internal.h" +#include "host/keys.h" #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL #include diff --git a/subsys/bluetooth/host/br.h b/subsys/bluetooth/host/classic/br.h similarity index 100% rename from subsys/bluetooth/host/br.h rename to subsys/bluetooth/host/classic/br.h diff --git a/subsys/bluetooth/host/hfp_hf.c b/subsys/bluetooth/host/classic/hfp_hf.c similarity index 99% rename from subsys/bluetooth/host/hfp_hf.c rename to subsys/bluetooth/host/classic/hfp_hf.c index 4b0e82ee3c7..63ced987f18 100644 --- a/subsys/bluetooth/host/hfp_hf.c +++ b/subsys/bluetooth/host/classic/hfp_hf.c @@ -19,8 +19,8 @@ #include #include -#include "hci_core.h" -#include "conn_internal.h" +#include "host/hci_core.h" +#include "host/conn_internal.h" #include "l2cap_br_internal.h" #include "rfcomm_internal.h" #include "at.h" diff --git a/subsys/bluetooth/host/hfp_internal.h b/subsys/bluetooth/host/classic/hfp_internal.h similarity index 100% rename from subsys/bluetooth/host/hfp_internal.h rename to subsys/bluetooth/host/classic/hfp_internal.h diff --git a/subsys/bluetooth/host/keys_br.c b/subsys/bluetooth/host/classic/keys_br.c similarity index 98% rename from subsys/bluetooth/host/keys_br.c rename to subsys/bluetooth/host/classic/keys_br.c index 47799d49289..2ce745de678 100644 --- a/subsys/bluetooth/host/keys_br.c +++ b/subsys/bluetooth/host/classic/keys_br.c @@ -18,9 +18,9 @@ #include "common/bt_str.h" -#include "hci_core.h" -#include "settings.h" -#include "keys.h" +#include "host/hci_core.h" +#include "host/settings.h" +#include "host/keys.h" #define LOG_LEVEL CONFIG_BT_KEYS_LOG_LEVEL #include diff --git a/subsys/bluetooth/host/l2cap_br.c b/subsys/bluetooth/host/classic/l2cap_br.c similarity index 99% rename from subsys/bluetooth/host/l2cap_br.c rename to subsys/bluetooth/host/classic/l2cap_br.c index d042ac7962d..f1765105e08 100644 --- a/subsys/bluetooth/host/l2cap_br.c +++ b/subsys/bluetooth/host/classic/l2cap_br.c @@ -19,8 +19,8 @@ #include #include -#include "hci_core.h" -#include "conn_internal.h" +#include "host/hci_core.h" +#include "host/conn_internal.h" #include "l2cap_br_internal.h" #include "avdtp_internal.h" #include "a2dp_internal.h" diff --git a/subsys/bluetooth/host/l2cap_br_interface.h b/subsys/bluetooth/host/classic/l2cap_br_interface.h similarity index 100% rename from subsys/bluetooth/host/l2cap_br_interface.h rename to subsys/bluetooth/host/classic/l2cap_br_interface.h diff --git a/subsys/bluetooth/host/l2cap_br_internal.h b/subsys/bluetooth/host/classic/l2cap_br_internal.h similarity index 100% rename from subsys/bluetooth/host/l2cap_br_internal.h rename to subsys/bluetooth/host/classic/l2cap_br_internal.h diff --git a/subsys/bluetooth/host/rfcomm.c b/subsys/bluetooth/host/classic/rfcomm.c similarity index 99% rename from subsys/bluetooth/host/rfcomm.c rename to subsys/bluetooth/host/classic/rfcomm.c index 16e771c659d..d95a712f534 100644 --- a/subsys/bluetooth/host/rfcomm.c +++ b/subsys/bluetooth/host/classic/rfcomm.c @@ -22,8 +22,8 @@ #include -#include "hci_core.h" -#include "conn_internal.h" +#include "host/hci_core.h" +#include "host/conn_internal.h" #include "l2cap_br_internal.h" #include "rfcomm_internal.h" diff --git a/subsys/bluetooth/host/rfcomm_internal.h b/subsys/bluetooth/host/classic/rfcomm_internal.h similarity index 100% rename from subsys/bluetooth/host/rfcomm_internal.h rename to subsys/bluetooth/host/classic/rfcomm_internal.h diff --git a/subsys/bluetooth/host/sdp.c b/subsys/bluetooth/host/classic/sdp.c similarity index 99% rename from subsys/bluetooth/host/sdp.c rename to subsys/bluetooth/host/classic/sdp.c index b93b5ccc362..7cec5b05f9f 100644 --- a/subsys/bluetooth/host/sdp.c +++ b/subsys/bluetooth/host/classic/sdp.c @@ -19,8 +19,8 @@ #include "common/bt_str.h" #include "common/assert.h" -#include "hci_core.h" -#include "conn_internal.h" +#include "host/hci_core.h" +#include "host/conn_internal.h" #include "l2cap_br_internal.h" #include "sdp_internal.h" diff --git a/subsys/bluetooth/host/sdp_internal.h b/subsys/bluetooth/host/classic/sdp_internal.h similarity index 100% rename from subsys/bluetooth/host/sdp_internal.h rename to subsys/bluetooth/host/classic/sdp_internal.h diff --git a/subsys/bluetooth/host/ssp.c b/subsys/bluetooth/host/classic/ssp.c similarity index 99% rename from subsys/bluetooth/host/ssp.c rename to subsys/bluetooth/host/classic/ssp.c index 814a35b32fb..72ac72624a7 100644 --- a/subsys/bluetooth/host/ssp.c +++ b/subsys/bluetooth/host/classic/ssp.c @@ -15,10 +15,10 @@ #include "common/bt_str.h" -#include "keys.h" +#include "host/keys.h" -#include "hci_core.h" -#include "conn_internal.h" +#include "host/hci_core.h" +#include "host/conn_internal.h" #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL #include diff --git a/subsys/bluetooth/host/ssp.h b/subsys/bluetooth/host/classic/ssp.h similarity index 100% rename from subsys/bluetooth/host/ssp.h rename to subsys/bluetooth/host/classic/ssp.h diff --git a/subsys/bluetooth/host/conn.c b/subsys/bluetooth/host/conn.c index 88d9a8b6dff..c6b54f50ca7 100644 --- a/subsys/bluetooth/host/conn.c +++ b/subsys/bluetooth/host/conn.c @@ -38,7 +38,7 @@ #include "l2cap_internal.h" #include "keys.h" #include "smp.h" -#include "ssp.h" +#include "classic/ssp.h" #include "att_internal.h" #include "iso_internal.h" #include "direction_internal.h" diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c index 0c6a96e2aec..91e1deb904a 100644 --- a/subsys/bluetooth/host/hci_core.c +++ b/subsys/bluetooth/host/hci_core.c @@ -52,7 +52,7 @@ #include "settings.h" #if defined(CONFIG_BT_BREDR) -#include "br.h" +#include "classic/br.h" #endif #if defined(CONFIG_BT_DF) diff --git a/subsys/bluetooth/host/l2cap_internal.h b/subsys/bluetooth/host/l2cap_internal.h index 43ade8b90d7..599c512f500 100644 --- a/subsys/bluetooth/host/l2cap_internal.h +++ b/subsys/bluetooth/host/l2cap_internal.h @@ -10,7 +10,7 @@ #include #include -#include "l2cap_br_interface.h" +#include "classic/l2cap_br_interface.h" enum l2cap_conn_list_action { BT_L2CAP_CHAN_LOOKUP, diff --git a/tests/bluetooth/at/src/main.c b/tests/bluetooth/at/src/main.c index 5bfdfdd6896..62391d874a0 100644 --- a/tests/bluetooth/at/src/main.c +++ b/tests/bluetooth/at/src/main.c @@ -10,7 +10,7 @@ #include -#include "subsys/bluetooth/host/at.h" +#include "subsys/bluetooth/host/classic/at.h" #include From 081024b7fa367f5ab919eaf8a0e62ce5e3150d12 Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Fri, 1 Mar 2024 15:38:45 +0800 Subject: [PATCH 0271/2402] Bluetooth: Host: Include full path of l2cap_br_interface.h The header file l2cap_interface.h has been included by tests/bsim/bluetooth/host/* cases. To avoid potential issue, include full path of header l2cap_br_interface.h in file l2cap_interface.h. Signed-off-by: Lyle Zhu --- subsys/bluetooth/host/l2cap_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/bluetooth/host/l2cap_internal.h b/subsys/bluetooth/host/l2cap_internal.h index 599c512f500..9f3471ce29f 100644 --- a/subsys/bluetooth/host/l2cap_internal.h +++ b/subsys/bluetooth/host/l2cap_internal.h @@ -10,7 +10,7 @@ #include #include -#include "classic/l2cap_br_interface.h" +#include "host/classic/l2cap_br_interface.h" enum l2cap_conn_list_action { BT_L2CAP_CHAN_LOOKUP, From 83bfa4c91b28b761fd5dc7617954cb53e11cd3d1 Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Fri, 1 Mar 2024 15:53:45 +0800 Subject: [PATCH 0272/2402] Bluetooth: Host: Move BR headers to subfolder classic Move BR/EDR header files from "include/zephyr/ bluetooth" to subfolder "include/zephyr/bluetooth/ classic". Signed-off-by: Lyle Zhu --- include/zephyr/bluetooth/{ => classic}/a2dp-codec.h | 0 include/zephyr/bluetooth/{ => classic}/a2dp.h | 2 +- include/zephyr/bluetooth/{ => classic}/avdtp.h | 0 include/zephyr/bluetooth/{ => classic}/hfp_hf.h | 0 include/zephyr/bluetooth/{ => classic}/rfcomm.h | 0 include/zephyr/bluetooth/{ => classic}/sdp.h | 0 samples/bluetooth/handsfree/src/main.c | 2 +- subsys/bluetooth/host/classic/a2dp.c | 4 ++-- subsys/bluetooth/host/classic/avdtp.c | 2 +- subsys/bluetooth/host/classic/avdtp_internal.h | 2 +- subsys/bluetooth/host/classic/hfp_hf.c | 4 ++-- subsys/bluetooth/host/classic/rfcomm.c | 2 +- subsys/bluetooth/host/classic/rfcomm_internal.h | 2 +- subsys/bluetooth/host/classic/sdp.c | 2 +- subsys/bluetooth/shell/bredr.c | 4 ++-- subsys/bluetooth/shell/bt.c | 4 ++-- subsys/bluetooth/shell/l2cap.c | 4 ++-- subsys/bluetooth/shell/rfcomm.c | 4 ++-- 18 files changed, 19 insertions(+), 19 deletions(-) rename include/zephyr/bluetooth/{ => classic}/a2dp-codec.h (100%) rename include/zephyr/bluetooth/{ => classic}/a2dp.h (98%) rename include/zephyr/bluetooth/{ => classic}/avdtp.h (100%) rename include/zephyr/bluetooth/{ => classic}/hfp_hf.h (100%) rename include/zephyr/bluetooth/{ => classic}/rfcomm.h (100%) rename include/zephyr/bluetooth/{ => classic}/sdp.h (100%) diff --git a/include/zephyr/bluetooth/a2dp-codec.h b/include/zephyr/bluetooth/classic/a2dp-codec.h similarity index 100% rename from include/zephyr/bluetooth/a2dp-codec.h rename to include/zephyr/bluetooth/classic/a2dp-codec.h diff --git a/include/zephyr/bluetooth/a2dp.h b/include/zephyr/bluetooth/classic/a2dp.h similarity index 98% rename from include/zephyr/bluetooth/a2dp.h rename to include/zephyr/bluetooth/classic/a2dp.h index f7e8ff35ea1..a0650122802 100644 --- a/include/zephyr/bluetooth/a2dp.h +++ b/include/zephyr/bluetooth/classic/a2dp.h @@ -12,7 +12,7 @@ #include -#include +#include #ifdef __cplusplus extern "C" { diff --git a/include/zephyr/bluetooth/avdtp.h b/include/zephyr/bluetooth/classic/avdtp.h similarity index 100% rename from include/zephyr/bluetooth/avdtp.h rename to include/zephyr/bluetooth/classic/avdtp.h diff --git a/include/zephyr/bluetooth/hfp_hf.h b/include/zephyr/bluetooth/classic/hfp_hf.h similarity index 100% rename from include/zephyr/bluetooth/hfp_hf.h rename to include/zephyr/bluetooth/classic/hfp_hf.h diff --git a/include/zephyr/bluetooth/rfcomm.h b/include/zephyr/bluetooth/classic/rfcomm.h similarity index 100% rename from include/zephyr/bluetooth/rfcomm.h rename to include/zephyr/bluetooth/classic/rfcomm.h diff --git a/include/zephyr/bluetooth/sdp.h b/include/zephyr/bluetooth/classic/sdp.h similarity index 100% rename from include/zephyr/bluetooth/sdp.h rename to include/zephyr/bluetooth/classic/sdp.h diff --git a/samples/bluetooth/handsfree/src/main.c b/samples/bluetooth/handsfree/src/main.c index 919c5f9714a..e45cd08bc8c 100644 --- a/samples/bluetooth/handsfree/src/main.c +++ b/samples/bluetooth/handsfree/src/main.c @@ -16,7 +16,7 @@ #include #include -#include +#include static void connected(struct bt_conn *conn) { diff --git a/subsys/bluetooth/host/classic/a2dp.c b/subsys/bluetooth/host/classic/a2dp.c index f6eda168127..0fb6723480e 100644 --- a/subsys/bluetooth/host/classic/a2dp.c +++ b/subsys/bluetooth/host/classic/a2dp.c @@ -18,8 +18,8 @@ #include #include -#include -#include +#include +#include #include "common/assert.h" diff --git a/subsys/bluetooth/host/classic/avdtp.c b/subsys/bluetooth/host/classic/avdtp.c index aee20f53532..5f323bf87c6 100644 --- a/subsys/bluetooth/host/classic/avdtp.c +++ b/subsys/bluetooth/host/classic/avdtp.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include "host/hci_core.h" #include "host/conn_internal.h" diff --git a/subsys/bluetooth/host/classic/avdtp_internal.h b/subsys/bluetooth/host/classic/avdtp_internal.h index 86db8fab45d..5b971fcaac7 100644 --- a/subsys/bluetooth/host/classic/avdtp_internal.h +++ b/subsys/bluetooth/host/classic/avdtp_internal.h @@ -6,7 +6,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include /* @brief A2DP ROLE's */ #define A2DP_SRC_ROLE 0x00 diff --git a/subsys/bluetooth/host/classic/hfp_hf.c b/subsys/bluetooth/host/classic/hfp_hf.c index 63ced987f18..effccb08b0e 100644 --- a/subsys/bluetooth/host/classic/hfp_hf.c +++ b/subsys/bluetooth/host/classic/hfp_hf.c @@ -16,8 +16,8 @@ #include "common/assert.h" -#include -#include +#include +#include #include "host/hci_core.h" #include "host/conn_internal.h" diff --git a/subsys/bluetooth/host/classic/rfcomm.c b/subsys/bluetooth/host/classic/rfcomm.c index d95a712f534..489aab4d292 100644 --- a/subsys/bluetooth/host/classic/rfcomm.c +++ b/subsys/bluetooth/host/classic/rfcomm.c @@ -20,7 +20,7 @@ #include #include -#include +#include #include "host/hci_core.h" #include "host/conn_internal.h" diff --git a/subsys/bluetooth/host/classic/rfcomm_internal.h b/subsys/bluetooth/host/classic/rfcomm_internal.h index 3b94a9829f2..ed5edd93b46 100644 --- a/subsys/bluetooth/host/classic/rfcomm_internal.h +++ b/subsys/bluetooth/host/classic/rfcomm_internal.h @@ -8,7 +8,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include typedef enum { BT_RFCOMM_CFC_UNKNOWN, diff --git a/subsys/bluetooth/host/classic/sdp.c b/subsys/bluetooth/host/classic/sdp.c index 7cec5b05f9f..5a399921fea 100644 --- a/subsys/bluetooth/host/classic/sdp.c +++ b/subsys/bluetooth/host/classic/sdp.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include "common/bt_str.h" #include "common/assert.h" diff --git a/subsys/bluetooth/shell/bredr.c b/subsys/bluetooth/shell/bredr.c index 167aaf91a47..e2da6752d3c 100644 --- a/subsys/bluetooth/shell/bredr.c +++ b/subsys/bluetooth/shell/bredr.c @@ -24,8 +24,8 @@ #include #include #include -#include -#include +#include +#include #include diff --git a/subsys/bluetooth/shell/bt.c b/subsys/bluetooth/shell/bt.c index bbe794969d7..e18ff9f291e 100644 --- a/subsys/bluetooth/shell/bt.c +++ b/subsys/bluetooth/shell/bt.c @@ -29,8 +29,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/subsys/bluetooth/shell/l2cap.c b/subsys/bluetooth/shell/l2cap.c index 45e45f518b1..a29329a3d1c 100644 --- a/subsys/bluetooth/shell/l2cap.c +++ b/subsys/bluetooth/shell/l2cap.c @@ -24,8 +24,8 @@ #include #include #include -#include -#include +#include +#include #include diff --git a/subsys/bluetooth/shell/rfcomm.c b/subsys/bluetooth/shell/rfcomm.c index fd578f9a33d..eece089b3e4 100644 --- a/subsys/bluetooth/shell/rfcomm.c +++ b/subsys/bluetooth/shell/rfcomm.c @@ -24,8 +24,8 @@ #include #include #include -#include -#include +#include +#include #include From 459e1dd10dbdff8456a4cda235e2cf9825f0e9c5 Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Fri, 1 Mar 2024 16:30:24 +0800 Subject: [PATCH 0273/2402] MAINTAINERS: Update Bluetooth Classic file path Move source files of BR/EDR to subfolder "subsys/ bluetooth/host/classic/". Add the path "include/zephyr/bluetooth/classic/" for the header files of BR/EDR. Signed-off-by: Lyle Zhu --- MAINTAINERS.yml | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 2e7caf8b8ea..aa00be3e9a8 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -461,15 +461,8 @@ Bluetooth Classic: - jhedberg - sjanc files: - - subsys/bluetooth/host/a2dp* - - subsys/bluetooth/host/at.* - - subsys/bluetooth/host/avdtp* - - subsys/bluetooth/host/br.* - - subsys/bluetooth/host/hfp* - - subsys/bluetooth/host/l2cap_br* - - subsys/bluetooth/host/rfcomm* - - subsys/bluetooth/host/sdp* - - subsys/bluetooth/host/ssp* + - subsys/bluetooth/host/classic/ + - include/zephyr/bluetooth/classic/ labels: - "area: Bluetooth Classic" tests: From 40cf23daff093bf09169d1fab44c272d9f9f3208 Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Fri, 1 Mar 2024 18:45:44 +0800 Subject: [PATCH 0274/2402] Bluetooth: Rename BT_BREDR to BT_CLASSIC Rename BT_BREDR to BT_CLASSIC Rename CONFIG_BT_BREDR to CONFIG_BT_CLASSIC Signed-off-by: Lyle Zhu --- cmake/linker_script/common/common-rom.cmake | 2 +- doc/zephyr.doxyfile.in | 2 +- drivers/bluetooth/hci/h4.c | 2 +- drivers/bluetooth/hci/hci_b91.c | 2 +- drivers/bluetooth/hci/hci_esp32.c | 4 +- drivers/bluetooth/hci/hci_stm32wba.c | 2 +- drivers/bluetooth/hci/ipc.c | 2 +- include/zephyr/bluetooth/conn.h | 6 +- .../zephyr/linker/common-rom/common-rom-bt.ld | 2 +- samples/bluetooth/handsfree/prj.conf | 2 +- scripts/kconfig/hardened.csv | 2 +- subsys/bluetooth/Kconfig.logging | 2 +- subsys/bluetooth/common/Kconfig | 8 +-- subsys/bluetooth/host/Kconfig | 14 +--- subsys/bluetooth/host/Kconfig.l2cap | 2 +- subsys/bluetooth/host/classic/CMakeLists.txt | 2 +- subsys/bluetooth/host/conn.c | 68 +++++++++---------- subsys/bluetooth/host/conn_internal.h | 12 ++-- subsys/bluetooth/host/hci_core.c | 50 +++++++------- subsys/bluetooth/host/hci_core.h | 14 ++-- subsys/bluetooth/host/id.c | 4 +- subsys/bluetooth/host/l2cap.c | 16 ++--- subsys/bluetooth/host/monitor.c | 6 +- subsys/bluetooth/host/monitor.h | 2 +- subsys/bluetooth/host/smp.c | 34 +++++----- subsys/bluetooth/shell/CMakeLists.txt | 2 +- subsys/bluetooth/shell/bt.c | 46 ++++++------- tests/bluetooth/at/prj.conf | 2 +- .../host/id/bt_br_oob_get_local/prj.conf | 2 +- tests/bluetooth/init/prj_17.conf | 2 +- tests/bluetooth/init/prj_18.conf | 2 +- tests/bluetooth/init/prj_19.conf | 2 +- tests/bluetooth/init/prj_20.conf | 2 +- tests/bluetooth/init/prj_21.conf | 2 +- tests/bluetooth/init/prj_22.conf | 2 +- tests/bluetooth/init/prj_ctlr.conf | 2 +- tests/bluetooth/init/prj_ctlr_4_0.conf | 2 +- tests/bluetooth/init/prj_ctlr_4_0_dbg.conf | 2 +- tests/bluetooth/init/prj_ctlr_5_x_dbg.conf | 2 +- tests/bluetooth/init/prj_ctlr_dbg.conf | 2 +- tests/bluetooth/init/prj_ctlr_ticker.conf | 2 +- tests/bluetooth/init/prj_ctlr_tiny.conf | 2 +- tests/bluetooth/init/prj_llcp.conf | 2 +- tests/bluetooth/shell/prj_br.conf | 2 +- 44 files changed, 168 insertions(+), 176 deletions(-) diff --git a/cmake/linker_script/common/common-rom.cmake b/cmake/linker_script/common/common-rom.cmake index d955c8ad0b6..e2173c54f34 100644 --- a/cmake/linker_script/common/common-rom.cmake +++ b/cmake/linker_script/common/common-rom.cmake @@ -99,7 +99,7 @@ endif() zephyr_iterable_section(NAME bt_l2cap_fixed_chan KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN 4) -if(CONFIG_BT_BREDR) +if(CONFIG_BT_CLASSIC) zephyr_iterable_section(NAME bt_l2cap_br_fixed_chan KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN 4) endif() diff --git a/doc/zephyr.doxyfile.in b/doc/zephyr.doxyfile.in index 29b4651765b..7ba2abe0cc5 100644 --- a/doc/zephyr.doxyfile.in +++ b/doc/zephyr.doxyfile.in @@ -2352,7 +2352,7 @@ INCLUDE_FILE_PATTERNS = PREDEFINED = __DOXYGEN__ \ CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT \ CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN \ - CONFIG_BT_BREDR \ + CONFIG_BT_CLASSIC \ CONFIG_BT_EATT \ CONFIG_BT_L2CAP_SEG_RECV \ CONFIG_BT_MESH_MODEL_EXTENSIONS \ diff --git a/drivers/bluetooth/hci/h4.c b/drivers/bluetooth/hci/h4.c index e5cd81a06b8..288e920141e 100644 --- a/drivers/bluetooth/hci/h4.c +++ b/drivers/bluetooth/hci/h4.c @@ -155,7 +155,7 @@ static inline void get_evt_hdr(void) rx.remaining++; rx.hdr_len++; break; -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) case BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI: case BT_HCI_EVT_EXTENDED_INQUIRY_RESULT: rx.discardable = true; diff --git a/drivers/bluetooth/hci/hci_b91.c b/drivers/bluetooth/hci/hci_b91.c index 738874596d9..61f4ffc2f6c 100644 --- a/drivers/bluetooth/hci/hci_b91.c +++ b/drivers/bluetooth/hci/hci_b91.c @@ -28,7 +28,7 @@ static bool is_hci_event_discardable(const uint8_t *evt_data) uint8_t evt_type = evt_data[0]; switch (evt_type) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) case BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI: case BT_HCI_EVT_EXTENDED_INQUIRY_RESULT: return true; diff --git a/drivers/bluetooth/hci/hci_esp32.c b/drivers/bluetooth/hci/hci_esp32.c index 121157d41bb..cddecbd5123 100644 --- a/drivers/bluetooth/hci/hci_esp32.c +++ b/drivers/bluetooth/hci/hci_esp32.c @@ -32,7 +32,7 @@ static bool is_hci_event_discardable(const uint8_t *evt_data) uint8_t evt_type = evt_data[0]; switch (evt_type) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) case BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI: case BT_HCI_EVT_EXTENDED_INQUIRY_RESULT: return true; @@ -280,7 +280,7 @@ static int bt_esp32_ble_init(void) int ret; esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); -#if defined(CONFIG_BT_BREDR) && defined(CONFIG_SOC_SERIES_ESP32) +#if defined(CONFIG_BT_CLASSIC) && defined(CONFIG_SOC_SERIES_ESP32) esp_bt_mode_t mode = ESP_BT_MODE_BTDM; #else esp_bt_mode_t mode = ESP_BT_MODE_BLE; diff --git a/drivers/bluetooth/hci/hci_stm32wba.c b/drivers/bluetooth/hci/hci_stm32wba.c index fd718d5efb6..9a9d3a1b1c3 100644 --- a/drivers/bluetooth/hci/hci_stm32wba.c +++ b/drivers/bluetooth/hci/hci_stm32wba.c @@ -56,7 +56,7 @@ static bool is_hci_event_discardable(const uint8_t *evt_data) uint8_t evt_type = evt_data[0]; switch (evt_type) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) case BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI: case BT_HCI_EVT_EXTENDED_INQUIRY_RESULT: return true; diff --git a/drivers/bluetooth/hci/ipc.c b/drivers/bluetooth/hci/ipc.c index 56671c702d6..4aad992978e 100644 --- a/drivers/bluetooth/hci/ipc.c +++ b/drivers/bluetooth/hci/ipc.c @@ -34,7 +34,7 @@ static bool is_hci_event_discardable(const uint8_t *evt_data) uint8_t evt_type = evt_data[0]; switch (evt_type) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) case BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI: case BT_HCI_EVT_EXTENDED_INQUIRY_RESULT: return true; diff --git a/include/zephyr/bluetooth/conn.h b/include/zephyr/bluetooth/conn.h index edd37bde31e..4059e0963b2 100644 --- a/include/zephyr/bluetooth/conn.h +++ b/include/zephyr/bluetooth/conn.h @@ -1067,7 +1067,7 @@ struct bt_conn_cb { const bt_addr_le_t *rpa, const bt_addr_le_t *identity); #endif /* CONFIG_BT_SMP */ -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) /** @brief The security level of a connection has changed. * * This callback notifies the application that the security of a @@ -1086,7 +1086,7 @@ struct bt_conn_cb { */ void (*security_changed)(struct bt_conn *conn, bt_security_t level, enum bt_security_err err); -#endif /* defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) */ +#endif /* defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) */ #if defined(CONFIG_BT_REMOTE_INFO) /** @brief Remote information procedures has completed. @@ -1551,7 +1551,7 @@ struct bt_conn_auth_cb { */ void (*pairing_confirm)(struct bt_conn *conn); -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) /** @brief Request the user to enter a passkey. * * This callback will be called for a BR/EDR (Bluetooth Classic) diff --git a/include/zephyr/linker/common-rom/common-rom-bt.ld b/include/zephyr/linker/common-rom/common-rom-bt.ld index c8f5375b2be..842aa31da24 100644 --- a/include/zephyr/linker/common-rom/common-rom-bt.ld +++ b/include/zephyr/linker/common-rom/common-rom-bt.ld @@ -4,7 +4,7 @@ ITERABLE_SECTION_ROM(bt_l2cap_fixed_chan, 4) -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) ITERABLE_SECTION_ROM(bt_l2cap_br_fixed_chan, 4) #endif diff --git a/samples/bluetooth/handsfree/prj.conf b/samples/bluetooth/handsfree/prj.conf index 924d9c0af0e..05f46f32f9c 100644 --- a/samples/bluetooth/handsfree/prj.conf +++ b/samples/bluetooth/handsfree/prj.conf @@ -1,5 +1,5 @@ CONFIG_BT=y -CONFIG_BT_BREDR=y +CONFIG_BT_CLASSIC=y CONFIG_BT_RFCOMM=y CONFIG_BT_HFP_HF=y CONFIG_BT_PERIPHERAL=y diff --git a/scripts/kconfig/hardened.csv b/scripts/kconfig/hardened.csv index 6cc978f7e56..a8caf3a87cc 100644 --- a/scripts/kconfig/hardened.csv +++ b/scripts/kconfig/hardened.csv @@ -52,7 +52,7 @@ ZTEST,n BT_A2DP,n,experimental BT_AUDIO,n,experimental BT_AVDTP,n,experimental -BT_BREDR,n,experimental +BT_CLASSIC,n,experimental BT_CTLR_ADV_DATA_CHAIN,n,experimental BT_CTLR_DTM_HCI_DF_IQ_REPORT,n,experimental BT_CTLR_SET_HOST_FEATURE,n,experimental diff --git a/subsys/bluetooth/Kconfig.logging b/subsys/bluetooth/Kconfig.logging index c103a42c316..6c6c26f0b77 100644 --- a/subsys/bluetooth/Kconfig.logging +++ b/subsys/bluetooth/Kconfig.logging @@ -446,7 +446,7 @@ config BT_DEBUG_A2DP config BT_DEBUG_SDP bool "[DEPRECATED] Bluetooth Service Discovery Protocol (SDP) debug" select DEPRECATED - depends on BT_BREDR + depends on BT_CLASSIC help This option enables debug support for the Bluetooth Service Discovery Protocol (SDP). diff --git a/subsys/bluetooth/common/Kconfig b/subsys/bluetooth/common/Kconfig index 2fdc98694b1..0cfb8dfb106 100644 --- a/subsys/bluetooth/common/Kconfig +++ b/subsys/bluetooth/common/Kconfig @@ -49,7 +49,7 @@ config BT_BUF_ACL_TX_COUNT config BT_BUF_ACL_RX_SIZE int "Maximum supported ACL size for incoming data" - default 200 if BT_BREDR + default 200 if BT_CLASSIC default 70 if BT_EATT default 69 if BT_SMP default 37 if BT_MESH_GATT @@ -139,7 +139,7 @@ config BT_BUF_EVT_DISCARDABLE_SIZE range 43 255 if !BT_EXT_ADV range 58 255 if BT_EXT_ADV # LE Extended Advertising Report event - default 255 if BT_BREDR + default 255 if BT_CLASSIC # Le Advertising Report event default 43 if !BT_EXT_ADV default 58 if BT_EXT_ADV @@ -166,10 +166,10 @@ config BT_BUF_EVT_DISCARDABLE_COUNT config BT_BUF_CMD_TX_SIZE int "Maximum support HCI Command buffer length" - default 255 if (BT_EXT_ADV || BT_BREDR || BT_ISO_CENTRAL) + default 255 if (BT_EXT_ADV || BT_CLASSIC || BT_ISO_CENTRAL) # LE Set Connection CTE Receive Parameters. Value required to store max allowed number # of antenna ids for platforms other than Nordic. - default 83 if (!BT_EXT_ADV && !BT_BREDR && BT_CTLR_DF && BT_CTLR_DF_CONN_CTE_REQ && !SOC_COMPATIBLE_NRF) + default 83 if (!BT_EXT_ADV && !BT_CLASSIC && BT_CTLR_DF && BT_CTLR_DF_CONN_CTE_REQ && !SOC_COMPATIBLE_NRF) # LE Generate DHKey v2 command default 65 range 65 255 diff --git a/subsys/bluetooth/host/Kconfig b/subsys/bluetooth/host/Kconfig index 0b0e75dee18..9805ee0c06f 100644 --- a/subsys/bluetooth/host/Kconfig +++ b/subsys/bluetooth/host/Kconfig @@ -1026,10 +1026,9 @@ config BT_CONN_DISABLE_SECURITY WARNING: This option enables anyone to snoop on-air traffic. Use of this feature in production is strongly discouraged. -config BT_BREDR +config BT_CLASSIC bool "Bluetooth BR/EDR support [EXPERIMENTAL]" depends on BT_HCI_HOST - select BT_CLASSIC select BT_PERIPHERAL select BT_CENTRAL select BT_SMP @@ -1038,14 +1037,7 @@ config BT_BREDR help This option enables Bluetooth BR/EDR support -config BT_CLASSIC - bool "Bluetooth classic(BR/EDR) support [EXPERIMENTAL]" - depends on BT_BREDR - select EXPERIMENTAL - help - This option enables Bluetooth classic(BR/EDR) support - -if BT_BREDR +if BT_CLASSIC config BT_MAX_SCO_CONN int "Maximum number of simultaneous SCO connections" default 1 @@ -1106,7 +1098,7 @@ config BT_COD consult the following link: https://www.bluetooth.com/specifications/assigned-numbers -endif # BT_BREDR +endif # BT_CLASSIC config BT_HCI_VS_EVT_USER bool "User Vendor-Specific event handling" diff --git a/subsys/bluetooth/host/Kconfig.l2cap b/subsys/bluetooth/host/Kconfig.l2cap index acb948c425a..401079f71c6 100644 --- a/subsys/bluetooth/host/Kconfig.l2cap +++ b/subsys/bluetooth/host/Kconfig.l2cap @@ -29,7 +29,7 @@ config BT_L2CAP_TX_FRAG_COUNT config BT_L2CAP_TX_MTU int "Maximum supported L2CAP MTU for L2CAP TX buffers" - default 253 if BT_BREDR + default 253 if BT_CLASSIC default 66 if BT_EATT default 65 if BT_SMP default 64 if BT_BAP_UNICAST_SERVER || \ diff --git a/subsys/bluetooth/host/classic/CMakeLists.txt b/subsys/bluetooth/host/classic/CMakeLists.txt index b36e3a46db3..bfa07bf1c55 100644 --- a/subsys/bluetooth/host/classic/CMakeLists.txt +++ b/subsys/bluetooth/host/classic/CMakeLists.txt @@ -8,7 +8,7 @@ zephyr_library_sources_ifdef(CONFIG_BT_AVDTP avdtp.c) zephyr_library_sources_ifdef(CONFIG_BT_RFCOMM rfcomm.c) zephyr_library_sources_ifdef( - CONFIG_BT_BREDR + CONFIG_BT_CLASSIC br.c keys_br.c l2cap_br.c diff --git a/subsys/bluetooth/host/conn.c b/subsys/bluetooth/host/conn.c index c6b54f50ca7..57822a2e8ef 100644 --- a/subsys/bluetooth/host/conn.c +++ b/subsys/bluetooth/host/conn.c @@ -113,20 +113,20 @@ NET_BUF_POOL_FIXED_DEFINE(frag_pool, CONFIG_BT_L2CAP_TX_FRAG_COUNT, #endif /* CONFIG_BT_L2CAP_TX_FRAG_COUNT > 0 */ -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) const struct bt_conn_auth_cb *bt_auth; sys_slist_t bt_auth_info_cbs = SYS_SLIST_STATIC_INIT(&bt_auth_info_cbs); -#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_SMP || CONFIG_BT_CLASSIC */ static struct bt_conn_cb *callback_list; static struct bt_conn_tx conn_tx[CONFIG_BT_CONN_TX_MAX]; -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) static int bt_hci_connect_br_cancel(struct bt_conn *conn); static struct bt_conn sco_conns[CONFIG_BT_MAX_SCO_CONN]; -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ #endif /* CONFIG_BT_CONN */ #if defined(CONFIG_BT_ISO) @@ -147,11 +147,11 @@ int bt_conn_iso_init(void) struct k_sem *bt_conn_get_pkts(struct bt_conn *conn) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) if (conn->type == BT_CONN_TYPE_BR || !bt_dev.le.acl_mtu) { return &bt_dev.br.pkts; } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ #if defined(CONFIG_BT_ISO) /* Use ISO pkts semaphore if LE Read Buffer Size command returned @@ -581,12 +581,12 @@ static int send_iso(struct bt_conn *conn, struct net_buf *buf, uint8_t flags) static inline uint16_t conn_mtu(struct bt_conn *conn) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) if (conn->type == BT_CONN_TYPE_BR || (conn->type != BT_CONN_TYPE_ISO && !bt_dev.le.acl_mtu)) { return bt_dev.br.mtu; } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ #if defined(CONFIG_BT_ISO) if (conn->type == BT_CONN_TYPE_ISO) { return bt_dev.le.iso_mtu; @@ -1259,7 +1259,7 @@ struct bt_conn *bt_conn_lookup_handle(uint16_t handle, enum bt_conn_type type) } #endif -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) conn = conn_lookup_handle(sco_conns, ARRAY_SIZE(sco_conns), handle); if (conn) { goto found; @@ -1299,7 +1299,7 @@ void bt_conn_foreach(enum bt_conn_type type, func(conn, data); bt_conn_unref(conn); } -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) if (type & BT_CONN_TYPE_SCO) { for (i = 0; i < ARRAY_SIZE(sco_conns); i++) { struct bt_conn *conn = bt_conn_ref(&sco_conns[i]); @@ -1312,7 +1312,7 @@ void bt_conn_foreach(enum bt_conn_type type, bt_conn_unref(conn); } } -#endif /* defined(CONFIG_BT_BREDR) */ +#endif /* defined(CONFIG_BT_CLASSIC) */ #endif /* CONFIG_BT_CONN */ #if defined(CONFIG_BT_ISO) @@ -1406,7 +1406,7 @@ uint8_t bt_conn_index(const struct bt_conn *conn) "Invalid bt_conn pointer"); break; #endif -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) case BT_CONN_TYPE_SCO: index = conn - sco_conns; __ASSERT(index >= 0 && index < ARRAY_SIZE(sco_conns), @@ -1577,11 +1577,11 @@ int bt_conn_disconnect(struct bt_conn *conn, uint8_t reason) return conn_disconnect(conn, reason); } #endif /* CONFIG_BT_ISO */ -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) else if (conn->type == BT_CONN_TYPE_BR) { return bt_hci_connect_br_cancel(conn); } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ else { __ASSERT(false, "Invalid conn type %u", conn->type); } @@ -1934,7 +1934,7 @@ static struct bt_conn *acl_conn_new(void) return bt_conn_new(acl_conns, ARRAY_SIZE(acl_conns)); } -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) void bt_sco_cleanup(struct bt_conn *sco_conn) { bt_conn_unref(sco_conn->sco.acl); @@ -2188,7 +2188,7 @@ static int bt_hci_connect_br_cancel(struct bt_conn *conn) return err; } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ #if defined(CONFIG_BT_SMP) bool bt_conn_ltk_present(const struct bt_conn *conn) @@ -2262,14 +2262,14 @@ int bt_conn_le_start_encryption(struct bt_conn *conn, uint8_t rand[8], } #endif /* CONFIG_BT_SMP */ -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) uint8_t bt_conn_enc_key_size(const struct bt_conn *conn) { if (!conn->encrypt) { return 0; } - if (IS_ENABLED(CONFIG_BT_BREDR) && + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { struct bt_hci_cp_read_encryption_key_size *cp; struct bt_hci_rp_read_encryption_key_size *rp; @@ -2309,13 +2309,13 @@ uint8_t bt_conn_enc_key_size(const struct bt_conn *conn) static void reset_pairing(struct bt_conn *conn) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) if (conn->type == BT_CONN_TYPE_BR) { atomic_clear_bit(conn->flags, BT_CONN_BR_PAIRING); atomic_clear_bit(conn->flags, BT_CONN_BR_PAIRING_INITIATOR); atomic_clear_bit(conn->flags, BT_CONN_BR_LEGACY_SECURE); } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ /* Reset required security level to current operational */ conn->required_sec_level = conn->sec_level; @@ -2348,11 +2348,11 @@ void bt_conn_security_changed(struct bt_conn *conn, uint8_t hci_err, bt_keys_update_usage(conn->id, bt_conn_get_dst(conn)); } -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) if (conn->type == BT_CONN_TYPE_BR) { bt_keys_link_key_update_usage(&conn->br.dst); } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ } #endif @@ -2360,7 +2360,7 @@ void bt_conn_security_changed(struct bt_conn *conn, uint8_t hci_err, static int start_security(struct bt_conn *conn) { - if (IS_ENABLED(CONFIG_BT_BREDR) && conn->type == BT_CONN_TYPE_BR) { + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { return bt_ssp_start_security(conn); } @@ -2610,11 +2610,11 @@ int bt_conn_get_info(const struct bt_conn *conn, struct bt_conn_info *info) info->state = conn_internal_to_public_state(conn->state); info->security.flags = 0; info->security.level = bt_conn_get_security(conn); -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) info->security.enc_key_size = bt_conn_enc_key_size(conn); #else info->security.enc_key_size = 0; -#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_SMP || CONFIG_BT_CLASSIC */ switch (conn->type) { case BT_CONN_TYPE_LE: @@ -2643,7 +2643,7 @@ int bt_conn_get_info(const struct bt_conn *conn, struct bt_conn_info *info) info->security.flags |= BT_SECURITY_FLAG_OOB; } return 0; -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) case BT_CONN_TYPE_BR: info->br.dst = &conn->br.dst; return 0; @@ -2692,7 +2692,7 @@ int bt_conn_get_remote_info(struct bt_conn *conn, case BT_CONN_TYPE_LE: remote_info->le.features = conn->le.features; return 0; -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) case BT_CONN_TYPE_BR: /* TODO: Make sure the HCI commands to read br features and * extended features has finished. */ @@ -3342,7 +3342,7 @@ struct net_buf *bt_conn_create_frag_timeout(size_t reserve, k_timeout_t timeout) #endif /* CONFIG_NET_BUF_LOG */ } -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) int bt_conn_auth_cb_register(const struct bt_conn_auth_cb *cb) { if (!cb) { @@ -3359,7 +3359,7 @@ int bt_conn_auth_cb_register(const struct bt_conn_auth_cb *cb) */ if (!cb->cancel && (cb->passkey_display || cb->passkey_entry || cb->passkey_confirm || -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) cb->pincode_entry || #endif cb->pairing_confirm)) { @@ -3424,7 +3424,7 @@ int bt_conn_auth_passkey_entry(struct bt_conn *conn, unsigned int passkey) return bt_smp_auth_passkey_entry(conn, passkey); } - if (IS_ENABLED(CONFIG_BT_BREDR) && conn->type == BT_CONN_TYPE_BR) { + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { if (!bt_auth) { return -EINVAL; } @@ -3454,7 +3454,7 @@ int bt_conn_auth_passkey_confirm(struct bt_conn *conn) return bt_smp_auth_passkey_confirm(conn); } - if (IS_ENABLED(CONFIG_BT_BREDR) && conn->type == BT_CONN_TYPE_BR) { + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { if (!bt_auth) { return -EINVAL; } @@ -3471,7 +3471,7 @@ int bt_conn_auth_cancel(struct bt_conn *conn) return bt_smp_auth_cancel(conn); } - if (IS_ENABLED(CONFIG_BT_BREDR) && conn->type == BT_CONN_TYPE_BR) { + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { if (!bt_auth) { return -EINVAL; } @@ -3488,7 +3488,7 @@ int bt_conn_auth_pairing_confirm(struct bt_conn *conn) return bt_smp_auth_pairing_confirm(conn); } - if (IS_ENABLED(CONFIG_BT_BREDR) && conn->type == BT_CONN_TYPE_BR) { + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { if (!bt_auth) { return -EINVAL; } @@ -3498,7 +3498,7 @@ int bt_conn_auth_pairing_confirm(struct bt_conn *conn) return -EINVAL; } -#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_SMP || CONFIG_BT_CLASSIC */ struct bt_conn *bt_conn_lookup_index(uint8_t index) { diff --git a/subsys/bluetooth/host/conn_internal.h b/subsys/bluetooth/host/conn_internal.h index a13adff704a..20a10ae5a1f 100644 --- a/subsys/bluetooth/host/conn_internal.h +++ b/subsys/bluetooth/host/conn_internal.h @@ -86,7 +86,7 @@ struct bt_conn_le { #endif }; -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) /* For now reserve space for 2 pages of LMP remote features */ #define LMP_MAX_PAGES 2 @@ -167,11 +167,11 @@ struct bt_conn { /* Which local identity address this connection uses */ uint8_t id; -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) bt_security_t sec_level; bt_security_t required_sec_level; uint8_t encrypt; -#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_SMP || CONFIG_BT_CLASSIC */ #if defined(CONFIG_BT_DF_CONNECTION_CTE_RX) /** @@ -217,7 +217,7 @@ struct bt_conn { union { struct bt_conn_le le; -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) struct bt_conn_br br; struct bt_conn_sco sco; #endif @@ -379,11 +379,11 @@ int bt_conn_le_start_encryption(struct bt_conn *conn, uint8_t rand[8], void bt_conn_identity_resolved(struct bt_conn *conn); #endif /* CONFIG_BT_SMP */ -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) /* Notify higher layers that connection security changed */ void bt_conn_security_changed(struct bt_conn *conn, uint8_t hci_err, enum bt_security_err err); -#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_SMP || CONFIG_BT_CLASSIC */ /* Prepare a PDU to be sent over a connection */ #if defined(CONFIG_NET_BUF_LOG) diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c index 91e1deb904a..2138b8ff2f2 100644 --- a/subsys/bluetooth/host/hci_core.c +++ b/subsys/bluetooth/host/hci_core.c @@ -51,7 +51,7 @@ #include "crypto.h" #include "settings.h" -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) #include "classic/br.h" #endif @@ -881,7 +881,7 @@ static void hci_disconn_complete(struct net_buf *buf) bt_conn_set_state(conn, BT_CONN_DISCONNECTED); if (conn->type != BT_CONN_TYPE_LE) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) if (conn->type == BT_CONN_TYPE_SCO) { bt_sco_cleanup(conn); return; @@ -1935,7 +1935,7 @@ static void unpair(uint8_t id, const bt_addr_le_t *addr) bt_conn_unref(conn); } - if (IS_ENABLED(CONFIG_BT_BREDR)) { + if (IS_ENABLED(CONFIG_BT_CLASSIC)) { /* LE Public may indicate BR/EDR as well */ if (addr->type == BT_ADDR_LE_PUBLIC) { bt_keys_link_key_clear_addr(&addr->a); @@ -1954,7 +1954,7 @@ static void unpair(uint8_t id, const bt_addr_le_t *addr) bt_gatt_clear(id, addr); -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) struct bt_conn_auth_info_cb *listener, *next; SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&bt_auth_info_cbs, listener, @@ -1963,7 +1963,7 @@ static void unpair(uint8_t id, const bt_addr_le_t *addr) listener->bond_deleted(id, addr); } } -#endif /* defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) */ +#endif /* defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) */ } static void unpair_remote(const struct bt_bond_info *info, void *data) @@ -1999,7 +1999,7 @@ int bt_unpair(uint8_t id, const bt_addr_le_t *addr) #endif /* CONFIG_BT_CONN */ -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) enum bt_security_err bt_security_err_get(uint8_t hci_err) { switch (hci_err) { @@ -2019,7 +2019,7 @@ enum bt_security_err bt_security_err_get(uint8_t hci_err) return BT_SECURITY_ERR_UNSPECIFIED; } } -#endif /* defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) */ +#endif /* defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) */ #if defined(CONFIG_BT_SMP) static bool update_sec_level(struct bt_conn *conn) @@ -2039,7 +2039,7 @@ static bool update_sec_level(struct bt_conn *conn) } #endif /* CONFIG_BT_SMP */ -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) static void hci_encrypt_change(struct net_buf *buf) { struct bt_hci_evt_encrypt_change *evt = (void *)buf->data; @@ -2083,7 +2083,7 @@ static void hci_encrypt_change(struct net_buf *buf) } } #endif /* CONFIG_BT_SMP */ -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) if (conn->type == BT_CONN_TYPE_BR) { if (!bt_br_update_sec_level(conn)) { bt_conn_unref(conn); @@ -2101,7 +2101,7 @@ static void hci_encrypt_change(struct net_buf *buf) } } } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ bt_conn_security_changed(conn, status, bt_security_err_get(status)); @@ -2152,14 +2152,14 @@ static void hci_encrypt_key_refresh_complete(struct net_buf *buf) } } #endif /* CONFIG_BT_SMP */ -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) if (conn->type == BT_CONN_TYPE_BR) { if (!bt_br_update_sec_level(conn)) { bt_conn_unref(conn); return; } } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ bt_conn_security_changed(conn, status, bt_security_err_get(status)); if (status) { @@ -2169,7 +2169,7 @@ static void hci_encrypt_key_refresh_complete(struct net_buf *buf) bt_conn_unref(conn); } -#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_SMP || CONFIG_BT_CLASSIC */ #if defined(CONFIG_BT_REMOTE_VERSION) static void bt_hci_evt_read_remote_version_complete(struct net_buf *buf) @@ -2292,9 +2292,9 @@ static void hci_reset_complete(struct net_buf *buf) bt_scan_reset(); } -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) bt_br_discovery_reset(); -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ flags = (atomic_get(bt_dev.flags) & BT_DEV_PERSISTENT_FLAGS); atomic_set(bt_dev.flags, flags); @@ -2658,7 +2658,7 @@ static const struct event_handler normal_events[] = { sizeof(struct bt_hci_evt_vs)), EVENT_HANDLER(BT_HCI_EVT_LE_META_EVENT, hci_le_meta_event, sizeof(struct bt_hci_evt_le_meta_event)), -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) EVENT_HANDLER(BT_HCI_EVT_CONN_REQUEST, bt_hci_conn_req, sizeof(struct bt_hci_evt_conn_request)), EVENT_HANDLER(BT_HCI_EVT_CONN_COMPLETE, bt_hci_conn_complete, @@ -2705,18 +2705,18 @@ static const struct event_handler normal_events[] = { sizeof(struct bt_hci_evt_role_change)), EVENT_HANDLER(BT_HCI_EVT_SYNC_CONN_COMPLETE, bt_hci_synchronous_conn_complete, sizeof(struct bt_hci_evt_sync_conn_complete)), -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ #if defined(CONFIG_BT_CONN) EVENT_HANDLER(BT_HCI_EVT_DISCONN_COMPLETE, hci_disconn_complete, sizeof(struct bt_hci_evt_disconn_complete)), #endif /* CONFIG_BT_CONN */ -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) EVENT_HANDLER(BT_HCI_EVT_ENCRYPT_CHANGE, hci_encrypt_change, sizeof(struct bt_hci_evt_encrypt_change)), EVENT_HANDLER(BT_HCI_EVT_ENCRYPT_KEY_REFRESH_COMPLETE, hci_encrypt_key_refresh_complete, sizeof(struct bt_hci_evt_encrypt_key_refresh_complete)), -#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_SMP || CONFIG_BT_CLASSIC */ #if defined(CONFIG_BT_REMOTE_VERSION) EVENT_HANDLER(BT_HCI_EVT_REMOTE_VERSION_INFO, bt_hci_evt_read_remote_version_complete, @@ -2898,7 +2898,7 @@ static void read_le_features_complete(struct net_buf *buf) } #if defined(CONFIG_BT_CONN) -#if !defined(CONFIG_BT_BREDR) +#if !defined(CONFIG_BT_CLASSIC) static void read_buffer_size_complete(struct net_buf *buf) { struct bt_hci_rp_read_buffer_size *rp = (void *)buf->data; @@ -2918,7 +2918,7 @@ static void read_buffer_size_complete(struct net_buf *buf) k_sem_init(&bt_dev.le.acl_pkts, pkts, pkts); } -#endif /* !defined(CONFIG_BT_BREDR) */ +#endif /* !defined(CONFIG_BT_CLASSIC) */ #endif /* CONFIG_BT_CONN */ static void le_read_buffer_size_complete(struct net_buf *buf) @@ -3433,7 +3433,7 @@ static int le_init(void) return le_set_event_mask(); } -#if !defined(CONFIG_BT_BREDR) +#if !defined(CONFIG_BT_CLASSIC) static int bt_br_init(void) { #if defined(CONFIG_BT_CONN) @@ -3456,7 +3456,7 @@ static int bt_br_init(void) return 0; } -#endif /* !defined(CONFIG_BT_BREDR) */ +#endif /* !defined(CONFIG_BT_CLASSIC) */ static int set_event_mask(void) { @@ -3471,7 +3471,7 @@ static int set_event_mask(void) ev = net_buf_add(buf, sizeof(*ev)); - if (IS_ENABLED(CONFIG_BT_BREDR)) { + if (IS_ENABLED(CONFIG_BT_CLASSIC)) { /* Since we require LE support, we can count on a * Bluetooth 4.0 feature set */ @@ -3748,7 +3748,7 @@ static int hci_init(void) if (err) { return err; } - } else if (IS_ENABLED(CONFIG_BT_BREDR)) { + } else if (IS_ENABLED(CONFIG_BT_CLASSIC)) { LOG_ERR("Non-BR/EDR controller detected"); return -EIO; } diff --git a/subsys/bluetooth/host/hci_core.h b/subsys/bluetooth/host/hci_core.h index 1a3c06414a0..4263706382b 100644 --- a/subsys/bluetooth/host/hci_core.h +++ b/subsys/bluetooth/host/hci_core.h @@ -11,7 +11,7 @@ #define LE_CONN_LATENCY 0x0000 #define LE_CONN_TIMEOUT 0x002a -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) #define LMP_FEAT_PAGES_COUNT 3 #else #define LMP_FEAT_PAGES_COUNT 1 @@ -49,11 +49,11 @@ enum { BT_DEV_ID_PENDING, BT_DEV_STORE_ID, -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) BT_DEV_ISCAN, BT_DEV_PSCAN, BT_DEV_INQUIRY, -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ /* Total number of flags - must be at the end of the enum */ BT_DEV_NUM_FLAGS, @@ -277,7 +277,7 @@ struct bt_dev_le { #endif /* CONFIG_BT_SMP */ }; -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) struct bt_dev_br { /* Max controller's acceptable ACL packet length */ uint16_t mtu; @@ -355,7 +355,7 @@ struct bt_dev { /* LE controller specific features */ struct bt_dev_le le; -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) /* BR/EDR controller specific features */ struct bt_dev_br br; #endif @@ -404,11 +404,11 @@ struct bt_dev { }; extern struct bt_dev bt_dev; -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) extern const struct bt_conn_auth_cb *bt_auth; extern sys_slist_t bt_auth_info_cbs; enum bt_security_err bt_security_err_get(uint8_t hci_err); -#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_SMP || CONFIG_BT_CLASSIC */ /* Data type to store state related with command to be updated * when command completes successfully. diff --git a/subsys/bluetooth/host/id.c b/subsys/bluetooth/host/id.c index 8b492184458..b830c88ffaf 100644 --- a/subsys/bluetooth/host/id.c +++ b/subsys/bluetooth/host/id.c @@ -1902,7 +1902,7 @@ int bt_id_set_adv_own_addr(struct bt_le_ext_adv *adv, uint32_t options, return 0; } -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) int bt_br_oob_get_local(struct bt_br_oob *oob) { CHECKIF(oob == NULL) { @@ -1913,7 +1913,7 @@ int bt_br_oob_get_local(struct bt_br_oob *oob) return 0; } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ int bt_le_oob_get_local(uint8_t id, struct bt_le_oob *oob) { diff --git a/subsys/bluetooth/host/l2cap.c b/subsys/bluetooth/host/l2cap.c index c64278a6aa1..0a736112a49 100644 --- a/subsys/bluetooth/host/l2cap.c +++ b/subsys/bluetooth/host/l2cap.c @@ -357,7 +357,7 @@ void bt_l2cap_connected(struct bt_conn *conn) { struct bt_l2cap_chan *chan; - if (IS_ENABLED(CONFIG_BT_BREDR) && + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { bt_l2cap_br_connected(conn); return; @@ -399,7 +399,7 @@ void bt_l2cap_disconnected(struct bt_conn *conn) { struct bt_l2cap_chan *chan, *next; - if (IS_ENABLED(CONFIG_BT_BREDR) && + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { bt_l2cap_br_disconnected(conn); return; @@ -606,7 +606,7 @@ void bt_l2cap_security_changed(struct bt_conn *conn, uint8_t hci_status) { struct bt_l2cap_chan *chan, *next; - if (IS_ENABLED(CONFIG_BT_BREDR) && + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { l2cap_br_encrypt_change(conn, hci_status); return; @@ -2671,7 +2671,7 @@ void bt_l2cap_recv(struct bt_conn *conn, struct net_buf *buf, bool complete) struct bt_l2cap_chan *chan; uint16_t cid; - if (IS_ENABLED(CONFIG_BT_BREDR) && + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { bt_l2cap_br_recv(conn, buf); return; @@ -2772,7 +2772,7 @@ BT_L2CAP_CHANNEL_DEFINE(le_fixed_chan, BT_L2CAP_CID_LE_SIG, l2cap_accept, NULL); void bt_l2cap_init(void) { - if (IS_ENABLED(CONFIG_BT_BREDR)) { + if (IS_ENABLED(CONFIG_BT_CLASSIC)) { bt_l2cap_br_init(); } } @@ -3000,7 +3000,7 @@ int bt_l2cap_chan_connect(struct bt_conn *conn, struct bt_l2cap_chan *chan, return -EINVAL; } - if (IS_ENABLED(CONFIG_BT_BREDR) && + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { return bt_l2cap_br_chan_connect(conn, chan, psm); } @@ -3025,7 +3025,7 @@ int bt_l2cap_chan_disconnect(struct bt_l2cap_chan *chan) return -ENOTCONN; } - if (IS_ENABLED(CONFIG_BT_BREDR) && + if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) { return bt_l2cap_br_chan_disconnect(chan); } @@ -3119,7 +3119,7 @@ int bt_l2cap_chan_send(struct bt_l2cap_chan *chan, struct net_buf *buf) return -ESHUTDOWN; } - if (IS_ENABLED(CONFIG_BT_BREDR) && + if (IS_ENABLED(CONFIG_BT_CLASSIC) && chan->conn->type == BT_CONN_TYPE_BR) { return bt_l2cap_br_chan_send_cb(chan, buf, NULL, NULL); } diff --git a/subsys/bluetooth/host/monitor.c b/subsys/bluetooth/host/monitor.c index d1c9b58d4c7..708b749a898 100644 --- a/subsys/bluetooth/host/monitor.c +++ b/subsys/bluetooth/host/monitor.c @@ -57,7 +57,7 @@ static struct { atomic_t evt; atomic_t acl_tx; atomic_t acl_rx; -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) atomic_t sco_tx; atomic_t sco_rx; #endif @@ -79,7 +79,7 @@ static void drop_add(uint16_t opcode) case BT_MONITOR_ACL_RX_PKT: atomic_inc(&drops.acl_rx); break; -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) case BT_MONITOR_SCO_TX_PKT: atomic_inc(&drops.sco_tx); break; @@ -194,7 +194,7 @@ static inline void encode_hdr(struct bt_monitor_hdr *hdr, uint32_t timestamp, encode_drops(hdr, BT_MONITOR_EVENT_DROPS, &drops.evt); encode_drops(hdr, BT_MONITOR_ACL_TX_DROPS, &drops.acl_tx); encode_drops(hdr, BT_MONITOR_ACL_RX_DROPS, &drops.acl_rx); -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) encode_drops(hdr, BT_MONITOR_SCO_TX_DROPS, &drops.sco_tx); encode_drops(hdr, BT_MONITOR_SCO_RX_DROPS, &drops.sco_rx); #endif diff --git a/subsys/bluetooth/host/monitor.h b/subsys/bluetooth/host/monitor.h index a4e607823c3..e5a6422bfd8 100644 --- a/subsys/bluetooth/host/monitor.h +++ b/subsys/bluetooth/host/monitor.h @@ -43,7 +43,7 @@ #define BT_MONITOR_BASE_HDR_LEN 6 -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) #define BT_MONITOR_EXT_HDR_MAX 19 #else #define BT_MONITOR_EXT_HDR_MAX 15 diff --git a/subsys/bluetooth/host/smp.c b/subsys/bluetooth/host/smp.c index 95809d23768..3099c0f4ada 100644 --- a/subsys/bluetooth/host/smp.c +++ b/subsys/bluetooth/host/smp.c @@ -57,7 +57,7 @@ LOG_MODULE_REGISTER(bt_smp); #define ID_DIST 0 #endif -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) #define LINK_DIST BT_SMP_DIST_LINK_KEY #else #define LINK_DIST 0 @@ -81,7 +81,7 @@ LOG_MODULE_REGISTER(bt_smp); #define BT_SMP_AUTH_BONDING_FLAGS 0 #endif /* CONFIG_BT_BONDABLE */ -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) #define BT_SMP_AUTH_MASK_SC 0x2f #if defined(CONFIG_BT_SMP_OOB_LEGACY_PAIR_ONLY) @@ -100,7 +100,7 @@ LOG_MODULE_REGISTER(bt_smp); #define BT_SMP_AUTH_DEFAULT (BT_SMP_AUTH_BONDING_FLAGS | BT_SMP_AUTH_SC) #endif /* CONFIG_BT_SMP_OOB_LEGACY_PAIR_ONLY */ -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ enum pairing_method { JUST_WORKS, /* JustWorks pairing */ @@ -247,7 +247,7 @@ static const uint8_t gen_method_sc[5 /* remote */][5 /* local */] = { }; #endif /* !CONFIG_BT_SMP_OOB_LEGACY_PAIR_ONLY */ -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) /* SMP over BR/EDR channel specific context */ struct bt_smp_br { /* Commands that remote is allowed to send */ @@ -276,7 +276,7 @@ struct bt_smp_br { }; static struct bt_smp_br bt_smp_br_pool[CONFIG_BT_MAX_CONN]; -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ static struct bt_smp bt_smp_pool[CONFIG_BT_MAX_CONN]; static bool bondable = IS_ENABLED(CONFIG_BT_BONDABLE); @@ -616,7 +616,7 @@ static bool update_debug_keys_check(struct bt_smp *smp) !defined(CONFIG_BT_SMP_SC_PAIR_ONLY) /* For TX callbacks */ static void smp_pairing_complete(struct bt_smp *smp, uint8_t status); -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) static void smp_pairing_br_complete(struct bt_smp_br *smp, uint8_t status); #endif @@ -641,7 +641,7 @@ static void smp_check_complete(struct bt_conn *conn, uint8_t dist_complete) return; } -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) if (conn->type == BT_CONN_TYPE_BR) { struct bt_smp_br *smp; @@ -678,7 +678,7 @@ static void smp_sign_info_sent(struct bt_conn *conn, void *user_data, int err) } #endif /* CONFIG_BT_SIGNING */ -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) static void sc_derive_link_key(struct bt_smp *smp) { /* constants as specified in Core Spec Vol.3 Part H 2.4.2.4 */ @@ -1590,7 +1590,7 @@ int bt_smp_br_send_pairing_req(struct bt_conn *conn) return 0; } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ static void smp_reset(struct bt_smp *smp) { @@ -1659,7 +1659,7 @@ static void smp_pairing_complete(struct bt_smp *smp, uint8_t status) } if (!status) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) /* * Don't derive if Debug Keys are used. * TODO should we allow this if BR/EDR is already connected? @@ -1669,7 +1669,7 @@ static void smp_pairing_complete(struct bt_smp *smp, uint8_t status) IS_ENABLED(CONFIG_BT_STORE_DEBUG_KEYS))) { sc_derive_link_key(smp); } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ bool bond_flag = atomic_test_bit(smp->flags, SMP_FLAG_BOND); struct bt_conn_auth_info_cb *listener, *next; @@ -5182,7 +5182,7 @@ static int smp_g2_test(void) return 0; } -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) static int smp_h6_test(void) { uint8_t w[16] = { 0x9b, 0x7d, 0x39, 0x0a, 0xa6, 0x10, 0x10, 0x34, @@ -5227,7 +5227,7 @@ static int smp_h7_test(void) return 0; } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ static int smp_h8_test(void) { @@ -5294,7 +5294,7 @@ static int smp_self_test(void) return err; } -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) err = smp_h6_test(); if (err) { LOG_ERR("SMP h6 self test failed"); @@ -5306,7 +5306,7 @@ static int smp_self_test(void) LOG_ERR("SMP h7 self test failed"); return err; } -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ err = smp_h8_test(); if (err) { LOG_ERR("SMP h8 self test failed"); @@ -5946,10 +5946,10 @@ static int bt_smp_accept(struct bt_conn *conn, struct bt_l2cap_chan **chan) } BT_L2CAP_CHANNEL_DEFINE(smp_fixed_chan, BT_L2CAP_CID_SMP, bt_smp_accept, NULL); -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) BT_L2CAP_CHANNEL_DEFINE(smp_br_fixed_chan, BT_L2CAP_CID_BR_SMP, bt_smp_br_accept, NULL); -#endif /* CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_CLASSIC */ int bt_smp_init(void) { diff --git a/subsys/bluetooth/shell/CMakeLists.txt b/subsys/bluetooth/shell/CMakeLists.txt index 6c8509fcd8a..608721307e4 100644 --- a/subsys/bluetooth/shell/CMakeLists.txt +++ b/subsys/bluetooth/shell/CMakeLists.txt @@ -10,7 +10,7 @@ zephyr_library_sources_ifdef( gatt.c ) zephyr_library_sources_ifdef( - CONFIG_BT_BREDR + CONFIG_BT_CLASSIC bredr.c ) zephyr_library_sources_ifdef( diff --git a/subsys/bluetooth/shell/bt.c b/subsys/bluetooth/shell/bt.c index e18ff9f291e..fc5b8359118 100644 --- a/subsys/bluetooth/shell/bt.c +++ b/subsys/bluetooth/shell/bt.c @@ -52,9 +52,9 @@ struct bt_conn *default_conn; static struct bt_conn *pairing_conn; static struct bt_le_oob oob_local; -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) static struct bt_le_oob oob_remote; -#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR) */ +#endif /* CONFIG_BT_SMP || CONFIG_BT_CLASSIC) */ #endif /* CONFIG_BT_CONN */ #if defined(CONFIG_BT_SMP) @@ -631,7 +631,7 @@ void conn_addr_str(struct bt_conn *conn, char *addr, size_t len) } switch (info.type) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) case BT_CONN_TYPE_BR: bt_addr_to_str(info.br.dst, addr, len); break; @@ -773,7 +773,7 @@ static void identity_resolved(struct bt_conn *conn, const bt_addr_le_t *rpa, } #endif -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) static const char *security_err_str(enum bt_security_err err) { switch (err) { @@ -902,7 +902,7 @@ static struct bt_conn_cb conn_callbacks = { #if defined(CONFIG_BT_SMP) .identity_resolved = identity_resolved, #endif -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) .security_changed = security_changed, #endif #if defined(CONFIG_BT_REMOTE_INFO) @@ -1636,7 +1636,7 @@ static ssize_t ad_init(struct bt_data *data_array, const size_t data_array_size, size_t ad_len = 0; /* Set BR/EDR Not Supported if LE-only device */ - ad_flags = IS_ENABLED(CONFIG_BT_BREDR) ? 0 : BT_LE_AD_NO_BREDR; + ad_flags = IS_ENABLED(CONFIG_BT_CLASSIC) ? 0 : BT_LE_AD_NO_BREDR; if (discoverable) { /* A privacy-enabled Set Member should advertise RSI values only when in @@ -3096,14 +3096,14 @@ static int cmd_info(const struct shell *sh, size_t argc, char *argv[]) #endif } -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) if (info.type == BT_CONN_TYPE_BR) { char addr_str[BT_ADDR_STR_LEN]; bt_addr_to_str(info.br.dst, addr_str, sizeof(addr_str)); shell_print(ctx_shell, "Peer address %s", addr_str); } -#endif /* defined(CONFIG_BT_BREDR) */ +#endif /* defined(CONFIG_BT_CLASSIC) */ done: bt_conn_unref(conn); @@ -3284,7 +3284,7 @@ static int cmd_oob(const struct shell *sh, size_t argc, char *argv[]) return 0; } -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) static int cmd_oob_remote(const struct shell *sh, size_t argc, char *argv[]) { @@ -3320,7 +3320,7 @@ static int cmd_oob_clear(const struct shell *sh, size_t argc, char *argv[]) return 0; } -#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR) */ +#endif /* CONFIG_BT_SMP || CONFIG_BT_CLASSIC) */ static int cmd_clear(const struct shell *sh, size_t argc, char *argv[]) { @@ -3341,7 +3341,7 @@ static int cmd_clear(const struct shell *sh, size_t argc, char *argv[]) } if (argc < 3) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) addr.type = BT_ADDR_LE_PUBLIC; err = bt_addr_from_str(argv[1], &addr.a); #else @@ -3368,7 +3368,7 @@ static int cmd_clear(const struct shell *sh, size_t argc, char *argv[]) } #endif /* CONFIG_BT_CONN */ -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) static int cmd_security(const struct shell *sh, size_t argc, char *argv[]) { int err, sec; @@ -3478,7 +3478,7 @@ static void connection_info(struct bt_conn *conn, void *user_data) } switch (info.type) { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) case BT_CONN_TYPE_BR: bt_addr_to_str(info.br.dst, addr, sizeof(addr)); shell_print(ctx_shell, " #%u [BR][%s] %s", info.id, role_str(info.role), addr); @@ -3677,7 +3677,7 @@ static void auth_pairing_failed(struct bt_conn *conn, enum bt_security_err err) security_err_str(err), err); } -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) static void auth_pincode_entry(struct bt_conn *conn, bool highsec) { char addr[BT_ADDR_STR_LEN]; @@ -3740,7 +3740,7 @@ static struct bt_conn_auth_cb auth_cb_display = { #endif .passkey_entry = NULL, .passkey_confirm = NULL, -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) .pincode_entry = auth_pincode_entry, #endif .oob_data_request = NULL, @@ -3755,7 +3755,7 @@ static struct bt_conn_auth_cb auth_cb_display_yes_no = { .passkey_display = auth_passkey_display, .passkey_entry = NULL, .passkey_confirm = auth_passkey_confirm, -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) .pincode_entry = auth_pincode_entry, #endif .oob_data_request = NULL, @@ -3770,7 +3770,7 @@ static struct bt_conn_auth_cb auth_cb_input = { .passkey_display = NULL, .passkey_entry = auth_passkey_entry, .passkey_confirm = NULL, -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) .pincode_entry = auth_pincode_entry, #endif .oob_data_request = NULL, @@ -3782,7 +3782,7 @@ static struct bt_conn_auth_cb auth_cb_input = { }; static struct bt_conn_auth_cb auth_cb_confirm = { -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) .pincode_entry = auth_pincode_entry, #endif .oob_data_request = NULL, @@ -3797,7 +3797,7 @@ static struct bt_conn_auth_cb auth_cb_all = { .passkey_display = auth_passkey_display, .passkey_entry = auth_passkey_entry, .passkey_confirm = auth_passkey_confirm, -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) .pincode_entry = auth_pincode_entry, #endif .oob_data_request = auth_pairing_oob_data_request, @@ -3812,7 +3812,7 @@ static struct bt_conn_auth_cb auth_cb_oob = { .passkey_display = NULL, .passkey_entry = NULL, .passkey_confirm = NULL, -#if defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_CLASSIC) .pincode_entry = NULL, #endif .oob_data_request = auth_pairing_oob_data_request, @@ -4125,7 +4125,7 @@ static int cmd_auth_oob_tk(const struct shell *sh, size_t argc, char *argv[]) return 0; } #endif /* !defined(CONFIG_BT_SMP_SC_PAIR_ONLY) */ -#endif /* CONFIG_BT_SMP) || CONFIG_BT_BREDR */ +#endif /* CONFIG_BT_SMP) || CONFIG_BT_CLASSIC */ static int cmd_default_handler(const struct shell *sh, size_t argc, char **argv) { @@ -4308,7 +4308,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(bt_cmds, #endif /* CONFIG_BT_CENTRAL */ SHELL_CMD_ARG(oob, NULL, HELP_NONE, cmd_oob, 1, 0), SHELL_CMD_ARG(clear, NULL, "[all] ["HELP_ADDR_LE"]", cmd_clear, 2, 1), -#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) +#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC) SHELL_CMD_ARG(security, NULL, " [force-pair]", cmd_security, 1, 2), @@ -4351,7 +4351,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(bt_cmds, SHELL_CMD_ARG(fixed-passkey, NULL, "[passkey]", cmd_fixed_passkey, 1, 1), #endif -#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR) */ +#endif /* CONFIG_BT_SMP || CONFIG_BT_CLASSIC) */ #endif /* CONFIG_BT_CONN */ #if defined(CONFIG_BT_HCI_MESH_EXT) SHELL_CMD(mesh_adv, NULL, HELP_ONOFF, cmd_mesh_adv), diff --git a/tests/bluetooth/at/prj.conf b/tests/bluetooth/at/prj.conf index 42737f3052b..c0eedd5a701 100644 --- a/tests/bluetooth/at/prj.conf +++ b/tests/bluetooth/at/prj.conf @@ -1,5 +1,5 @@ CONFIG_BT=y -CONFIG_BT_BREDR=y +CONFIG_BT_CLASSIC=y CONFIG_BT_HFP_HF=y CONFIG_NET_BUF=y CONFIG_ZTEST=y diff --git a/tests/bluetooth/host/id/bt_br_oob_get_local/prj.conf b/tests/bluetooth/host/id/bt_br_oob_get_local/prj.conf index 8d352723bb4..d895ea85bb7 100644 --- a/tests/bluetooth/host/id/bt_br_oob_get_local/prj.conf +++ b/tests/bluetooth/host/id/bt_br_oob_get_local/prj.conf @@ -1,7 +1,7 @@ CONFIG_ZTEST=y CONFIG_BT=y CONFIG_BT_PERIPHERAL=y -CONFIG_BT_BREDR=y +CONFIG_BT_CLASSIC=y CONFIG_BT_SMP=y CONFIG_BT_ID_MAX=4 CONFIG_ASSERT=y diff --git a/tests/bluetooth/init/prj_17.conf b/tests/bluetooth/init/prj_17.conf index f085ad19fcd..4ee00dca586 100644 --- a/tests/bluetooth/init/prj_17.conf +++ b/tests/bluetooth/init/prj_17.conf @@ -18,5 +18,5 @@ CONFIG_BT_HCI_DRIVER_LOG_LEVEL_DBG=y CONFIG_BT_SMP_SELFTEST=y CONFIG_BT_ATT_LOG_LEVEL_DBG=y CONFIG_BT_GATT_LOG_LEVEL_DBG=y -CONFIG_BT_BREDR=y +CONFIG_BT_CLASSIC=y CONFIG_ZTEST=y diff --git a/tests/bluetooth/init/prj_18.conf b/tests/bluetooth/init/prj_18.conf index 66348e7e53d..cfd8e82240f 100644 --- a/tests/bluetooth/init/prj_18.conf +++ b/tests/bluetooth/init/prj_18.conf @@ -1,4 +1,4 @@ CONFIG_BT=y CONFIG_BT_PERIPHERAL=y -CONFIG_BT_BREDR=y +CONFIG_BT_CLASSIC=y CONFIG_ZTEST=y diff --git a/tests/bluetooth/init/prj_19.conf b/tests/bluetooth/init/prj_19.conf index af0aac027f8..8de6408952a 100644 --- a/tests/bluetooth/init/prj_19.conf +++ b/tests/bluetooth/init/prj_19.conf @@ -1,4 +1,4 @@ CONFIG_BT=y CONFIG_BT_CENTRAL=y -CONFIG_BT_BREDR=y +CONFIG_BT_CLASSIC=y CONFIG_ZTEST=y diff --git a/tests/bluetooth/init/prj_20.conf b/tests/bluetooth/init/prj_20.conf index 96dc6501491..43022222067 100644 --- a/tests/bluetooth/init/prj_20.conf +++ b/tests/bluetooth/init/prj_20.conf @@ -19,7 +19,7 @@ CONFIG_BT_HCI_DRIVER_LOG_LEVEL_DBG=y CONFIG_BT_SMP_SELFTEST=y CONFIG_BT_ATT_LOG_LEVEL_DBG=y CONFIG_BT_GATT_LOG_LEVEL_DBG=y -CONFIG_BT_BREDR=y +CONFIG_BT_CLASSIC=y CONFIG_BT_RFCOMM=y CONFIG_BT_AVDTP=y CONFIG_BT_AVDTP_LOG_LEVEL_DBG=y diff --git a/tests/bluetooth/init/prj_21.conf b/tests/bluetooth/init/prj_21.conf index 8ec212aa4eb..2c0fad1fa13 100644 --- a/tests/bluetooth/init/prj_21.conf +++ b/tests/bluetooth/init/prj_21.conf @@ -18,5 +18,5 @@ CONFIG_BT_HCI_DRIVER_LOG_LEVEL_DBG=y CONFIG_BT_SMP_SELFTEST=y CONFIG_BT_ATT_LOG_LEVEL_DBG=y CONFIG_BT_GATT_LOG_LEVEL_DBG=y -CONFIG_BT_BREDR=y +CONFIG_BT_CLASSIC=y CONFIG_ZTEST=y diff --git a/tests/bluetooth/init/prj_22.conf b/tests/bluetooth/init/prj_22.conf index 5fab545bc2c..ef4fb960870 100644 --- a/tests/bluetooth/init/prj_22.conf +++ b/tests/bluetooth/init/prj_22.conf @@ -1,5 +1,5 @@ CONFIG_BT=y -CONFIG_BT_BREDR=y +CONFIG_BT_CLASSIC=y CONFIG_BT_PERIPHERAL=y CONFIG_BT_SMP=y CONFIG_ZTEST=y diff --git a/tests/bluetooth/init/prj_ctlr.conf b/tests/bluetooth/init/prj_ctlr.conf index d64a64cc2a2..3b5ba787a0f 100644 --- a/tests/bluetooth/init/prj_ctlr.conf +++ b/tests/bluetooth/init/prj_ctlr.conf @@ -10,7 +10,7 @@ CONFIG_BT_SMP_SC_ONLY=y CONFIG_BT_TINYCRYPT_ECC=y CONFIG_BT_L2CAP_DYNAMIC_CHANNEL=y CONFIG_BT_GATT_CLIENT=y -CONFIG_BT_BREDR=n +CONFIG_BT_CLASSIC=n CONFIG_FLASH=y CONFIG_SOC_FLASH_NRF_RADIO_SYNC_TICKER=y CONFIG_ZTEST=y diff --git a/tests/bluetooth/init/prj_ctlr_4_0.conf b/tests/bluetooth/init/prj_ctlr_4_0.conf index eed589e96d8..a92a542f6d7 100644 --- a/tests/bluetooth/init/prj_ctlr_4_0.conf +++ b/tests/bluetooth/init/prj_ctlr_4_0.conf @@ -33,7 +33,7 @@ CONFIG_BT_SIGNING=y CONFIG_BT_SMP_SC_ONLY=y CONFIG_BT_L2CAP_DYNAMIC_CHANNEL=y CONFIG_BT_GATT_CLIENT=y -CONFIG_BT_BREDR=n +CONFIG_BT_CLASSIC=n CONFIG_FLASH=y CONFIG_SOC_FLASH_NRF_RADIO_SYNC_TICKER=y CONFIG_ZTEST=y diff --git a/tests/bluetooth/init/prj_ctlr_4_0_dbg.conf b/tests/bluetooth/init/prj_ctlr_4_0_dbg.conf index 95b9763b073..226c4846d5a 100644 --- a/tests/bluetooth/init/prj_ctlr_4_0_dbg.conf +++ b/tests/bluetooth/init/prj_ctlr_4_0_dbg.conf @@ -35,7 +35,7 @@ CONFIG_BT_SIGNING=y CONFIG_BT_SMP_SC_ONLY=y CONFIG_BT_L2CAP_DYNAMIC_CHANNEL=y CONFIG_BT_GATT_CLIENT=y -CONFIG_BT_BREDR=n +CONFIG_BT_CLASSIC=n CONFIG_FLASH=y CONFIG_SOC_FLASH_NRF_RADIO_SYNC_TICKER=y CONFIG_ZTEST=y diff --git a/tests/bluetooth/init/prj_ctlr_5_x_dbg.conf b/tests/bluetooth/init/prj_ctlr_5_x_dbg.conf index 0436807e8d2..f4dcbdc8fdd 100644 --- a/tests/bluetooth/init/prj_ctlr_5_x_dbg.conf +++ b/tests/bluetooth/init/prj_ctlr_5_x_dbg.conf @@ -71,7 +71,7 @@ CONFIG_BT_HCI_DRIVER_LOG_LEVEL_DBG=y CONFIG_BT_SMP_SELFTEST=y CONFIG_BT_ATT_LOG_LEVEL_DBG=y CONFIG_BT_GATT_LOG_LEVEL_DBG=y -CONFIG_BT_BREDR=n +CONFIG_BT_CLASSIC=n CONFIG_DEBUG=y CONFIG_FLASH=y CONFIG_SOC_FLASH_NRF_RADIO_SYNC_TICKER=n diff --git a/tests/bluetooth/init/prj_ctlr_dbg.conf b/tests/bluetooth/init/prj_ctlr_dbg.conf index ac9efeb9338..d2c887fefa0 100644 --- a/tests/bluetooth/init/prj_ctlr_dbg.conf +++ b/tests/bluetooth/init/prj_ctlr_dbg.conf @@ -53,7 +53,7 @@ CONFIG_BT_HCI_DRIVER_LOG_LEVEL_DBG=y CONFIG_BT_SMP_SELFTEST=y CONFIG_BT_ATT_LOG_LEVEL_DBG=y CONFIG_BT_GATT_LOG_LEVEL_DBG=y -CONFIG_BT_BREDR=n +CONFIG_BT_CLASSIC=n CONFIG_DEBUG=y CONFIG_FLASH=y CONFIG_SOC_FLASH_NRF_RADIO_SYNC_TICKER=n diff --git a/tests/bluetooth/init/prj_ctlr_ticker.conf b/tests/bluetooth/init/prj_ctlr_ticker.conf index efeae970f31..ba983f09a73 100644 --- a/tests/bluetooth/init/prj_ctlr_ticker.conf +++ b/tests/bluetooth/init/prj_ctlr_ticker.conf @@ -56,7 +56,7 @@ CONFIG_BT_HCI_DRIVER_LOG_LEVEL_DBG=y CONFIG_BT_SMP_SELFTEST=y CONFIG_BT_ATT_LOG_LEVEL_DBG=y CONFIG_BT_GATT_LOG_LEVEL_DBG=y -CONFIG_BT_BREDR=n +CONFIG_BT_CLASSIC=n CONFIG_DEBUG=y CONFIG_FLASH=y CONFIG_SOC_FLASH_NRF_RADIO_SYNC_TICKER=n diff --git a/tests/bluetooth/init/prj_ctlr_tiny.conf b/tests/bluetooth/init/prj_ctlr_tiny.conf index f0056881680..19de37a5a84 100644 --- a/tests/bluetooth/init/prj_ctlr_tiny.conf +++ b/tests/bluetooth/init/prj_ctlr_tiny.conf @@ -38,7 +38,7 @@ CONFIG_BT_SMP_SC_ONLY=y CONFIG_BT_TINYCRYPT_ECC=y CONFIG_BT_L2CAP_DYNAMIC_CHANNEL=y CONFIG_BT_GATT_CLIENT=y -CONFIG_BT_BREDR=n +CONFIG_BT_CLASSIC=n CONFIG_BT_ASSERT=n CONFIG_ASSERT=n CONFIG_FLASH=y diff --git a/tests/bluetooth/init/prj_llcp.conf b/tests/bluetooth/init/prj_llcp.conf index 626e6c40e2b..05eb2197c1d 100644 --- a/tests/bluetooth/init/prj_llcp.conf +++ b/tests/bluetooth/init/prj_llcp.conf @@ -10,7 +10,7 @@ CONFIG_BT_SMP_SC_ONLY=y CONFIG_BT_TINYCRYPT_ECC=y CONFIG_BT_L2CAP_DYNAMIC_CHANNEL=y CONFIG_BT_GATT_CLIENT=y -CONFIG_BT_BREDR=n +CONFIG_BT_CLASSIC=n CONFIG_FLASH=y CONFIG_SOC_FLASH_NRF_RADIO_SYNC_TICKER=y CONFIG_BT_CTLR_ADVANCED_FEATURES=y diff --git a/tests/bluetooth/shell/prj_br.conf b/tests/bluetooth/shell/prj_br.conf index 11cad5cfd92..764a0e6b3e4 100644 --- a/tests/bluetooth/shell/prj_br.conf +++ b/tests/bluetooth/shell/prj_br.conf @@ -1,6 +1,6 @@ CONFIG_TEST=y CONFIG_BT=y -CONFIG_BT_BREDR=y +CONFIG_BT_CLASSIC=y CONFIG_BT_RFCOMM=y CONFIG_BT_SHELL=y CONFIG_LOG=y From 4e079831b7d36fb51886f5a909d09aa250273beb Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Mon, 4 Mar 2024 10:03:32 +0800 Subject: [PATCH 0275/2402] doc: releases: migration-guide-3.7: Rename BT_BREDR to BT_CLASSIC Due to the source/header files are moved to subfolder "classic", rename the kconfig option BT_BREDR to BT_CLASSIC to make the folder name and kconfig option name consistent. Signed-off-by: Lyle Zhu --- doc/releases/migration-guide-3.7.rst | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index 73f96a432ae..8baccab3d9a 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -119,6 +119,14 @@ Bluetooth Mesh Bluetooth Audio =============== +Bluetooth Classic +================= + +* The source files of Host BR/EDR have been moved to ``subsys/bluetooth/host/classic``. + The Header files of Host BR/EDR have been moved to ``include/zephyr/bluetooth/classic``. + Removed the :kconfig:option:`CONFIG_BT_BREDR`. It is replaced by new option + :kconfig:option:`CONFIG_BT_CLASSIC`. (:github:`69651`) + Networking ********** From 056fe7d2aef2c5e3713157dbd97f1b152afbed1f Mon Sep 17 00:00:00 2001 From: Jens Rehhoff Thomsen Date: Mon, 5 Feb 2024 17:14:51 +0100 Subject: [PATCH 0276/2402] Bluetooth samples: Add USE_SPECIFIC_BROADCAST_CHANNEL Kconfig Added USE_SPECIFIC_BROADCAST_CHANNEL which enable/disables the use of a specific channel audio location for the broadcast audio sink sample. If USE_SPECIFIC_BROADCAST_CHANNEL is set to no then first valid channel is chosen. In this case broadcast channel with no audio location is also supported. Signed-off-by: Jens Rehhoff Thomsen --- samples/bluetooth/broadcast_audio_sink/Kconfig | 9 ++++++++- samples/bluetooth/broadcast_audio_sink/src/main.c | 10 +++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/samples/bluetooth/broadcast_audio_sink/Kconfig b/samples/bluetooth/broadcast_audio_sink/Kconfig index 5f57423d7f6..72a31d69676 100644 --- a/samples/bluetooth/broadcast_audio_sink/Kconfig +++ b/samples/bluetooth/broadcast_audio_sink/Kconfig @@ -55,11 +55,18 @@ config USE_USB_AUDIO_OUTPUT phone or PC as a USB-in device (such as a USB microphone). USB audio only supports a single audio channel. +config USE_SPECIFIC_BROADCAST_CHANNEL + bool "Use specific Broadcast Channel Audio Location" + default y + depends on USE_USB_AUDIO_OUTPUT + help + Enables the use of a specific Channel Audio Location (see config TARGET_BROADCAST_CHANNEL). + config TARGET_BROADCAST_CHANNEL int "Broadcast Channel Audio Location to sync to" range 0 2 default 1 - depends on USE_USB_AUDIO_OUTPUT + depends on USE_SPECIFIC_BROADCAST_CHANNEL help Channel Audio Location to sync to. These corresponds to the bt_audio_location, supporting mono, left and right channels diff --git a/samples/bluetooth/broadcast_audio_sink/src/main.c b/samples/bluetooth/broadcast_audio_sink/src/main.c index 504aa0c4e6b..3485a275049 100644 --- a/samples/bluetooth/broadcast_audio_sink/src/main.c +++ b/samples/bluetooth/broadcast_audio_sink/src/main.c @@ -364,7 +364,6 @@ static void stream_started_cb(struct bt_bap_stream *stream) sink_stream->valid_cnt = 0U; sink_stream->error_cnt = 0U; - #if defined(CONFIG_LIBLC3) int err; @@ -458,6 +457,15 @@ static bool find_valid_bis_cb(const struct bt_bap_base_subgroup_bis *bis, err = bt_audio_codec_cfg_get_chan_allocation(&codec_cfg, &chan_allocation); if (err != 0) { printk("Could not find channel allocation (err=%d)\n", err); + if (err == -ENODATA && strlen(CONFIG_TARGET_BROADCAST_NAME) > 0U) { + /* Accept no channel allocation data available + * if TARGET_BROADCAST_NAME defined. Use current index. + */ + *bis_index = bis->index; + + return false; + } + return true; } From 95851583b8e7f4417ec87b87c8f94b1c613a857b Mon Sep 17 00:00:00 2001 From: Giancarlo Stasi Date: Tue, 6 Feb 2024 16:00:02 +0100 Subject: [PATCH 0277/2402] Bluetooth: Controller: Vendor Specific: support for Scan Request Reports Add support for vendor specific Set Scan Request Reports command and Scan Request Received Event, available for legacy advertising. Signed-off-by: Giancarlo Stasi --- subsys/bluetooth/controller/Kconfig | 8 +++ subsys/bluetooth/controller/hci/hci.c | 75 +++++++++++++++++++++ subsys/bluetooth/controller/ll_sw/ull_adv.c | 2 +- tests/bluetooth/init/prj_ctlr_4_0_dbg.conf | 3 +- 4 files changed, 86 insertions(+), 2 deletions(-) diff --git a/subsys/bluetooth/controller/Kconfig b/subsys/bluetooth/controller/Kconfig index bbd045b093c..e28406a47ae 100644 --- a/subsys/bluetooth/controller/Kconfig +++ b/subsys/bluetooth/controller/Kconfig @@ -992,6 +992,14 @@ config BT_CTLR_ASSERT_HANDLER and will be invoked whenever the controller code encounters an unrecoverable error. +config BT_CTLR_VS_SCAN_REQ_RX + bool "Use scan request reporting" + depends on BT_HCI_VS_EXT && !BT_CTLR_ADV_EXT + select BT_HCI_VS_EVT + select BT_CTLR_SCAN_REQ_NOTIFY + help + Enables usage of VS Scan Request Reports Command and Scan Request Received Event + endif # BT_CTLR config BT_CTLR_DEBUG_PINS_CPUAPP diff --git a/subsys/bluetooth/controller/hci/hci.c b/subsys/bluetooth/controller/hci/hci.c index c6d9c66ded2..f2c01a3cbb3 100644 --- a/subsys/bluetooth/controller/hci/hci.c +++ b/subsys/bluetooth/controller/hci/hci.c @@ -4802,6 +4802,10 @@ static void vs_read_supported_commands(struct net_buf *buf, rp->commands[0] |= BIT(5) | BIT(7); /* Read Static Addresses, Read Key Hierarchy Roots */ rp->commands[1] |= BIT(0) | BIT(1); +#if defined(CONFIG_BT_CTLR_VS_SCAN_REQ_RX) + /* Set Scan Request Reports */ + rp->commands[1] |= BIT(4); +#endif /* CONFIG_BT_CTLR_VS_SCAN_REQ_RX */ #if defined(CONFIG_BT_CTLR_TX_PWR_DYNAMIC_CONTROL) /* Write Tx Power, Read Tx Power */ rp->commands[1] |= BIT(5) | BIT(6); @@ -4908,6 +4912,20 @@ static void vs_set_min_used_chans(struct net_buf *buf, struct net_buf **evt) } #endif /* CONFIG_BT_CTLR_MIN_USED_CHAN && CONFIG_BT_PERIPHERAL */ +#if defined(CONFIG_BT_CTLR_VS_SCAN_REQ_RX) +static void vs_set_scan_req_reports(struct net_buf *buf, struct net_buf **evt) +{ + struct bt_hci_cp_vs_set_scan_req_reports *cmd = (void *)buf->data; + + if (cmd->enable) { + vs_events_mask |= BT_EVT_MASK_VS_SCAN_REQ_RX; + } else { + vs_events_mask &= ~BT_EVT_MASK_VS_SCAN_REQ_RX; + } + *evt = cmd_complete_status(0x00); +} +#endif /* CONFIG_BT_CTLR_VS_SCAN_REQ_RX */ + #if defined(CONFIG_BT_CTLR_TX_PWR_DYNAMIC_CONTROL) static void vs_write_tx_power_level(struct net_buf *buf, struct net_buf **evt) { @@ -5470,6 +5488,12 @@ int hci_vendor_cmd_handle_common(uint16_t ocf, struct net_buf *cmd, vs_read_key_hierarchy_roots(cmd, evt); break; +#if defined(CONFIG_BT_CTLR_VS_SCAN_REQ_RX) + case BT_OCF(BT_HCI_OP_VS_SET_SCAN_REQ_REPORTS): + vs_set_scan_req_reports(cmd, evt); + break; +#endif /* CONFIG_BT_CTLR_VS_SCAN_REQ_RX */ + #if defined(CONFIG_BT_CTLR_TX_PWR_DYNAMIC_CONTROL) case BT_OCF(BT_HCI_OP_VS_WRITE_TX_POWER_LEVEL): vs_write_tx_power_level(cmd, evt); @@ -7942,6 +7966,7 @@ static void le_big_terminate(struct pdu_data *pdu, #endif /* CONFIG_BT_BROADCASTER */ #if defined(CONFIG_BT_CTLR_SCAN_REQ_NOTIFY) +#if defined(CONFIG_BT_CTLR_ADV_EXT) static void le_scan_req_received(struct pdu_data *pdu_data, struct node_rx_pdu *node_rx, struct net_buf *buf) @@ -7995,6 +8020,50 @@ static void le_scan_req_received(struct pdu_data *pdu_data, sizeof(bt_addr_t)); } } +#endif /* CONFIG_BT_CTLR_ADV_EXT */ + +#if defined(CONFIG_BT_CTLR_VS_SCAN_REQ_RX) +static void le_vs_scan_req_received(struct pdu_data *pdu, + struct node_rx_pdu *node_rx, + struct net_buf *buf) +{ + struct pdu_adv *adv = (void *)pdu; + struct bt_hci_evt_vs_scan_req_rx *sep; + +#if defined(CONFIG_BT_CTLR_PRIVACY) + uint8_t rl_idx; +#endif + + if (!(vs_events_mask & BT_EVT_MASK_VS_SCAN_REQ_RX)) { + return; + } + + sep = vs_event(buf, BT_HCI_EVT_VS_SCAN_REQ_RX, sizeof(*sep)); + sep->addr.type = adv->tx_addr; + memcpy(&sep->addr.a.val[0], &adv->scan_req.scan_addr[0], + sizeof(bt_addr_t)); + +#if defined(CONFIG_BT_CTLR_PRIVACY) + rl_idx = node_rx->hdr.rx_ftr.rl_idx; + if (rl_idx < ll_rl_size_get()) { + /* Store identity address */ + ll_rl_id_addr_get(rl_idx, &sep->addr.type, + &sep->addr.a.val[0]); + /* Mark it as identity address from RPA (0x02, 0x03) */ + sep->addr.type += 2U; + } else { +#else + if (1) { +#endif + sep->addr.type = adv->tx_addr; + memcpy(&sep->addr.a.val[0], &adv->adv_ind.addr[0], + sizeof(bt_addr_t)); + } + + /* The Link Layer currently returns RSSI as an absolute value */ + sep->rssi = -(node_rx->hdr.rx_ftr.rssi); +} +#endif /* CONFIG_BT_CTLR_VS_SCAN_REQ_RX */ #endif /* CONFIG_BT_CTLR_SCAN_REQ_NOTIFY */ #if defined(CONFIG_BT_CONN) @@ -8371,7 +8440,13 @@ static void encode_control(struct node_rx_pdu *node_rx, #if defined(CONFIG_BT_CTLR_SCAN_REQ_NOTIFY) case NODE_RX_TYPE_SCAN_REQ: +#if defined(CONFIG_BT_CTLR_ADV_EXT) le_scan_req_received(pdu_data, node_rx, buf); +#elif defined(CONFIG_BT_CTLR_VS_SCAN_REQ_RX) + le_vs_scan_req_received(pdu_data, node_rx, buf); +#else + LL_ASSERT(0); +#endif /* CONFIG_BT_CTLR_ADV_EXT */ break; #endif /* CONFIG_BT_CTLR_SCAN_REQ_NOTIFY */ diff --git a/subsys/bluetooth/controller/ll_sw/ull_adv.c b/subsys/bluetooth/controller/ll_sw/ull_adv.c index b5595e5e9c2..244719dd45f 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_adv.c +++ b/subsys/bluetooth/controller/ll_sw/ull_adv.c @@ -340,7 +340,7 @@ uint8_t ll_adv_params_set(uint16_t interval, uint8_t adv_type, adv->lll.chan_map = chan_map; adv->lll.filter_policy = filter_policy; -#if defined(CONFIG_BT_CTLR_SCAN_REQ_NOTIFY) +#if defined(CONFIG_BT_CTLR_SCAN_REQ_NOTIFY) && defined(CONFIG_BT_CTLR_ADV_EXT) adv->lll.scan_req_notify = sreq; #endif diff --git a/tests/bluetooth/init/prj_ctlr_4_0_dbg.conf b/tests/bluetooth/init/prj_ctlr_4_0_dbg.conf index 226c4846d5a..53559510ac4 100644 --- a/tests/bluetooth/init/prj_ctlr_4_0_dbg.conf +++ b/tests/bluetooth/init/prj_ctlr_4_0_dbg.conf @@ -27,7 +27,8 @@ CONFIG_BT_CTLR_SCAN_REQ_NOTIFY=n CONFIG_BT_CTLR_SCAN_REQ_RSSI=n CONFIG_BT_CTLR_PROFILE_ISR=n CONFIG_BT_CTLR_DEBUG_PINS=n -CONFIG_BT_HCI_VS_EXT=n +CONFIG_BT_HCI_VS_EXT=y +CONFIG_BT_CTLR_VS_SCAN_REQ_RX=y CONFIG_BT_PERIPHERAL=y CONFIG_BT_CENTRAL=y CONFIG_BT_SMP=y From b32c819b090bf3113dca145329285b7809c4105b Mon Sep 17 00:00:00 2001 From: Ying Zhang Date: Wed, 6 Mar 2024 14:11:26 +0800 Subject: [PATCH 0278/2402] Bluetooth: tester: Add support for BTP_GAP_SET_POWERED command Fill BTP_GAP_SET_POWERED command to support power on/off BT controller Fixes: #67346 Signed-off-by: Ying Zhang --- tests/bluetooth/tester/src/btp_gap.c | 37 ++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/tests/bluetooth/tester/src/btp_gap.c b/tests/bluetooth/tester/src/btp_gap.c index 76d725a57ac..26122fbabac 100644 --- a/tests/bluetooth/tester/src/btp_gap.c +++ b/tests/bluetooth/tester/src/btp_gap.c @@ -228,6 +228,7 @@ static uint8_t supported_commands(const void *cmd, uint16_t cmd_len, tester_set_bit(rp->data, BTP_GAP_READ_SUPPORTED_COMMANDS); tester_set_bit(rp->data, BTP_GAP_READ_CONTROLLER_INDEX_LIST); tester_set_bit(rp->data, BTP_GAP_READ_CONTROLLER_INFO); + tester_set_bit(rp->data, BTP_GAP_SET_POWERED); tester_set_bit(rp->data, BTP_GAP_SET_CONNECTABLE); /* octet 1 */ @@ -449,6 +450,37 @@ static uint8_t set_oob_sc_remote_data(const void *cmd, uint16_t cmd_len, } #endif /* !defined(CONFIG_BT_SMP_OOB_LEGACY_PAIR_ONLY) */ +static uint8_t set_powered(const void *cmd, uint16_t cmd_len, + void *rsp, uint16_t *rsp_len) +{ + const struct btp_gap_set_powered_cmd *cp = cmd; + struct btp_gap_set_powered_rp *rp = rsp; + int err; + + if (cp->powered) { + err = bt_enable(NULL); + if (err < 0) { + LOG_ERR("Unable to enable Bluetooth: %d", err); + return BTP_STATUS_FAILED; + } + bt_conn_cb_register(&conn_callbacks); + atomic_set_bit(¤t_settings, BTP_GAP_SETTINGS_POWERED); + } else { + err = bt_disable(); + if (err < 0) { + LOG_ERR("Unable to disable Bluetooth: %d", err); + return BTP_STATUS_FAILED; + } + bt_conn_cb_unregister(&conn_callbacks); + atomic_clear_bit(¤t_settings, BTP_GAP_SETTINGS_POWERED); + } + rp->current_settings = sys_cpu_to_le32(current_settings); + + *rsp_len = sizeof(*rp); + + return BTP_STATUS_SUCCESS; +} + static uint8_t set_connectable(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) { @@ -1683,6 +1715,11 @@ static const struct btp_handler handlers[] = { .expect_len = 0, .func = controller_info, }, + { + .opcode = BTP_GAP_SET_POWERED, + .expect_len = sizeof(struct btp_gap_set_powered_cmd), + .func = set_powered, + }, { .opcode = BTP_GAP_SET_CONNECTABLE, .expect_len = sizeof(struct btp_gap_set_connectable_cmd), From a5a13201e4f71af235b3fa27de8c16974ef404d8 Mon Sep 17 00:00:00 2001 From: Rubin Gerritsen Date: Tue, 20 Feb 2024 15:05:57 +0100 Subject: [PATCH 0279/2402] Bluetooth: Controller: Remove experimental from LE Set Host Feature Out-of-tree controllers do not necessarily mark the LE Set Host Feature command as experimantal. Add an additional entry to solve this like done for other ISO entries. Signed-off-by: Rubin Gerritsen --- subsys/bluetooth/controller/Kconfig | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/subsys/bluetooth/controller/Kconfig b/subsys/bluetooth/controller/Kconfig index e28406a47ae..4d97152f2d3 100644 --- a/subsys/bluetooth/controller/Kconfig +++ b/subsys/bluetooth/controller/Kconfig @@ -852,11 +852,14 @@ config BT_CTLR_SYNC_ISO_PDU_LEN_MAX endif # BT_CTLR_ADV_EXT config BT_CTLR_SET_HOST_FEATURE - bool "LE Set Host Feature Command [EXPERIMENTAL]" - select EXPERIMENTAL + bool "LE Set Host Feature Command" if !BT_LL_SW_SPLIT help Enables optional LE Set Host Feature Command +config BT_CTLR_SET_HOST_FEATURE + bool "LE Set Host Feature Command (Split Link Layer) [EXPERIMENTAL]" if BT_LL_SW_SPLIT + select EXPERIMENTAL if BT_LL_SW_SPLIT + config BT_CTLR_CENTRAL_ISO bool "LE Connected Isochronous Stream Central" if !BT_LL_SW_SPLIT depends on BT_CTLR_CENTRAL_ISO_SUPPORT && BT_CENTRAL From 94afc4ee3df94ece4289d48b722c851385625906 Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Tue, 13 Feb 2024 15:14:56 +0100 Subject: [PATCH 0280/2402] drivers: dma: pxp: Run clang-format Run clang-format before making changes Signed-off-by: Phi Bang Nguyen --- drivers/dma/dma_mcux_pxp.c | 61 ++++++++++------------- include/zephyr/drivers/dma/dma_mcux_pxp.h | 8 +-- 2 files changed, 31 insertions(+), 38 deletions(-) diff --git a/drivers/dma/dma_mcux_pxp.c b/drivers/dma/dma_mcux_pxp.c index ef6f9f90f28..95ae1949a34 100644 --- a/drivers/dma/dma_mcux_pxp.c +++ b/drivers/dma/dma_mcux_pxp.c @@ -40,7 +40,7 @@ static void dma_mcux_pxp_irq_handler(const struct device *dev) PXP_ClearStatusFlags(config->base, kPXP_CompleteFlag); #ifdef CONFIG_HAS_MCUX_CACHE - DCACHE_InvalidateByRange((uint32_t) data->out_buf_addr, data->out_buf_size); + DCACHE_InvalidateByRange((uint32_t)data->out_buf_addr, data->out_buf_size); #endif if (data->dma_callback) { data->dma_callback(dev, data->user_data, 0, 0); @@ -49,7 +49,7 @@ static void dma_mcux_pxp_irq_handler(const struct device *dev) /* Configure a channel */ static int dma_mcux_pxp_configure(const struct device *dev, uint32_t channel, - struct dma_config *config) + struct dma_config *config) { const struct dma_mcux_pxp_config *dev_config = dev->config; struct dma_mcux_pxp_data *dev_data = dev->data; @@ -102,8 +102,8 @@ static int dma_mcux_pxp_configure(const struct device *dev, uint32_t channel, default: return -ENOTSUP; } - DCACHE_CleanByRange((uint32_t) config->head_block->source_address, - config->head_block->block_size); + DCACHE_CleanByRange((uint32_t)config->head_block->source_address, + config->head_block->block_size); /* * Some notes on how specific fields of the DMA config are used by @@ -127,15 +127,14 @@ static int dma_mcux_pxp_configure(const struct device *dev, uint32_t channel, output_buffer_cfg.buffer0Addr = config->head_block->dest_address; output_buffer_cfg.buffer1Addr = 0U; output_buffer_cfg.pitchBytes = config->dest_data_size; - output_buffer_cfg.width = (config->dest_data_size / bytes_per_pixel); + output_buffer_cfg.width = (config->dest_data_size / bytes_per_pixel); output_buffer_cfg.height = config->dest_burst_length; PXP_SetOutputBufferConfig(dev_config->base, &output_buffer_cfg); /* We only support a process surface that covers the full buffer */ - PXP_SetProcessSurfacePosition(dev_config->base, 0U, 0U, - output_buffer_cfg.width, output_buffer_cfg.height); + PXP_SetProcessSurfacePosition(dev_config->base, 0U, 0U, output_buffer_cfg.width, + output_buffer_cfg.height); /* Setup rotation */ - PXP_SetRotateConfig(dev_config->base, kPXP_RotateProcessSurface, - rotate, kPXP_FlipDisable); + PXP_SetRotateConfig(dev_config->base, kPXP_RotateProcessSurface, rotate, kPXP_FlipDisable); dev_data->ps_buf_addr = config->head_block->source_address; dev_data->ps_buf_size = config->head_block->block_size; @@ -151,7 +150,7 @@ static int dma_mcux_pxp_start(const struct device *dev, uint32_t channel) const struct dma_mcux_pxp_config *config = dev->config; struct dma_mcux_pxp_data *data = dev->data; #ifdef CONFIG_HAS_MCUX_CACHE - DCACHE_CleanByRange((uint32_t) data->ps_buf_addr, data->ps_buf_size); + DCACHE_CleanByRange((uint32_t)data->ps_buf_addr, data->ps_buf_size); #endif ARG_UNUSED(channel); @@ -178,29 +177,23 @@ static int dma_mcux_pxp_init(const struct device *dev) return 0; } -#define DMA_INIT(n) \ - static void dma_pxp_config_func##n(const struct device *dev) \ - { \ - IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), ( \ - IRQ_CONNECT(DT_INST_IRQN(n), \ - DT_INST_IRQ(n, priority), \ - dma_mcux_pxp_irq_handler, \ - DEVICE_DT_INST_GET(n), 0); \ - irq_enable(DT_INST_IRQ(n, irq)); \ - )) \ - } \ - \ - static const struct dma_mcux_pxp_config dma_config_##n = { \ - .base = (PXP_Type *)DT_INST_REG_ADDR(n), \ - .irq_config_func = dma_pxp_config_func##n, \ - }; \ - \ - static struct dma_mcux_pxp_data dma_data_##n; \ - \ - DEVICE_DT_INST_DEFINE(n, \ - &dma_mcux_pxp_init, NULL, \ - &dma_data_##n, &dma_config_##n, \ - PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \ - &dma_mcux_pxp_api); +#define DMA_INIT(n) \ + static void dma_pxp_config_func##n(const struct device *dev) \ + { \ + IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \ + (IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ + dma_mcux_pxp_irq_handler, DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQ(n, irq));)) \ + } \ + \ + static const struct dma_mcux_pxp_config dma_config_##n = { \ + .base = (PXP_Type *)DT_INST_REG_ADDR(n), \ + .irq_config_func = dma_pxp_config_func##n, \ + }; \ + \ + static struct dma_mcux_pxp_data dma_data_##n; \ + \ + DEVICE_DT_INST_DEFINE(n, &dma_mcux_pxp_init, NULL, &dma_data_##n, &dma_config_##n, \ + PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, &dma_mcux_pxp_api); DT_INST_FOREACH_STATUS_OKAY(DMA_INIT) diff --git a/include/zephyr/drivers/dma/dma_mcux_pxp.h b/include/zephyr/drivers/dma/dma_mcux_pxp.h index 8c8c5feb049..6144db70238 100644 --- a/include/zephyr/drivers/dma/dma_mcux_pxp.h +++ b/include/zephyr/drivers/dma/dma_mcux_pxp.h @@ -7,10 +7,10 @@ #ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_MCUX_PXP_H_ #define ZEPHYR_INCLUDE_DRIVERS_DMA_MCUX_PXP_H_ -#define DMA_MCUX_PXP_CMD_MASK 0xE0 +#define DMA_MCUX_PXP_CMD_MASK 0xE0 #define DMA_MCUX_PXP_CMD_SHIFT 0x5 -#define DMA_MCUX_PXP_FMT_MASK 0x1F +#define DMA_MCUX_PXP_FMT_MASK 0x1F #define DMA_MCUX_PXP_FMT_SHIFT 0x0 /* @@ -29,8 +29,8 @@ #define DMA_MCUX_PXP_FMT(x) ((x << DMA_MCUX_PXP_FMT_SHIFT) & DMA_MCUX_PXP_FMT_MASK) #define DMA_MCUX_PXP_CMD(x) ((x << DMA_MCUX_PXP_CMD_SHIFT) & DMA_MCUX_PXP_CMD_MASK) -#define DMA_MCUX_PXP_CMD_ROTATE_0 0 -#define DMA_MCUX_PXP_CMD_ROTATE_90 1 +#define DMA_MCUX_PXP_CMD_ROTATE_0 0 +#define DMA_MCUX_PXP_CMD_ROTATE_90 1 #define DMA_MCUX_PXP_CMD_ROTATE_180 2 #define DMA_MCUX_PXP_CMD_ROTATE_270 3 From 8b191103d74d981f616990bd93d28358b89efaab Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Tue, 13 Feb 2024 15:19:06 +0100 Subject: [PATCH 0281/2402] drivers: dma: pxp: Add support for ARGB8888 format Add support for ARGB8888 pixel format as the camera pipeline on i.MX RT11xx could output images in this format Signed-off-by: Phi Bang Nguyen --- drivers/dma/dma_mcux_pxp.c | 5 +++++ include/zephyr/drivers/dma/dma_mcux_pxp.h | 5 +++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dma_mcux_pxp.c b/drivers/dma/dma_mcux_pxp.c index 95ae1949a34..88f8f39f34b 100644 --- a/drivers/dma/dma_mcux_pxp.c +++ b/drivers/dma/dma_mcux_pxp.c @@ -99,6 +99,11 @@ static int dma_mcux_pxp_configure(const struct device *dev, uint32_t channel, output_buffer_cfg.pixelFormat = kPXP_OutputPixelFormatRGB888; bytes_per_pixel = 3; break; + case DMA_MCUX_PXP_FMT_ARGB8888: + ps_buffer_cfg.pixelFormat = kPXP_PsPixelFormatARGB8888; + output_buffer_cfg.pixelFormat = kPXP_OutputPixelFormatARGB8888; + bytes_per_pixel = 4; + break; default: return -ENOTSUP; } diff --git a/include/zephyr/drivers/dma/dma_mcux_pxp.h b/include/zephyr/drivers/dma/dma_mcux_pxp.h index 6144db70238..7cddab2c3ef 100644 --- a/include/zephyr/drivers/dma/dma_mcux_pxp.h +++ b/include/zephyr/drivers/dma/dma_mcux_pxp.h @@ -34,7 +34,8 @@ #define DMA_MCUX_PXP_CMD_ROTATE_180 2 #define DMA_MCUX_PXP_CMD_ROTATE_270 3 -#define DMA_MCUX_PXP_FMT_RGB565 0 -#define DMA_MCUX_PXP_FMT_RGB888 1 +#define DMA_MCUX_PXP_FMT_RGB565 0 +#define DMA_MCUX_PXP_FMT_RGB888 1 +#define DMA_MCUX_PXP_FMT_ARGB8888 2 #endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_MCUX_PXP_H_ */ From ebf963590f05a4d191aa958de011e2cc36bf6f5c Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Tue, 13 Feb 2024 15:23:46 +0100 Subject: [PATCH 0282/2402] drivers: display: elcdif: Run clang-format Run clang-format before making changes Signed-off-by: Phi Bang Nguyen --- drivers/display/display_mcux_elcdif.c | 193 +++++++++++--------------- 1 file changed, 81 insertions(+), 112 deletions(-) diff --git a/drivers/display/display_mcux_elcdif.c b/drivers/display/display_mcux_elcdif.c index 304638011f1..b6595966772 100644 --- a/drivers/display/display_mcux_elcdif.c +++ b/drivers/display/display_mcux_elcdif.c @@ -55,8 +55,8 @@ struct mcux_elcdif_data { }; #ifdef CONFIG_MCUX_ELCDIF_PXP -static void mcux_elcdif_pxp_callback(const struct device *dma_dev, - void *user_data, uint32_t channel, int ret) +static void mcux_elcdif_pxp_callback(const struct device *dma_dev, void *user_data, + uint32_t channel, int ret) { struct mcux_elcdif_data *data = user_data; @@ -64,10 +64,8 @@ static void mcux_elcdif_pxp_callback(const struct device *dma_dev, } #endif /* CONFIG_MCUX_ELCDIF_PXP */ -static int mcux_elcdif_write(const struct device *dev, const uint16_t x, - const uint16_t y, - const struct display_buffer_descriptor *desc, - const void *buf) +static int mcux_elcdif_write(const struct device *dev, const uint16_t x, const uint16_t y, + const struct display_buffer_descriptor *desc, const void *buf) { const struct mcux_elcdif_config *config = dev->config; struct mcux_elcdif_data *dev_data = dev->data; @@ -77,31 +75,24 @@ static int mcux_elcdif_write(const struct device *dev, const uint16_t x, int ret = 0; bool full_fb = false; - __ASSERT((config->pixel_bytes * desc->pitch * desc->height) <= - desc->buf_size, "Input buffer too small"); + __ASSERT((config->pixel_bytes * desc->pitch * desc->height) <= desc->buf_size, + "Input buffer too small"); LOG_DBG("W=%d, H=%d, @%d,%d", desc->width, desc->height, x, y); - - if ((x == 0) && (y == 0) && - (desc->width == config->rgb_mode.panelWidth) && - (desc->height == config->rgb_mode.panelHeight) && - (desc->pitch == desc->width)) { + if ((x == 0) && (y == 0) && (desc->width == config->rgb_mode.panelWidth) && + (desc->height == config->rgb_mode.panelHeight) && (desc->pitch == desc->width)) { /* We can use the display buffer directly, no need to copy it */ - LOG_DBG("Setting FB from %p->%p", - (void *) dev_data->active_fb, (void *) buf); + LOG_DBG("Setting FB from %p->%p", (void *)dev_data->active_fb, (void *)buf); dev_data->active_fb = buf; full_fb = true; - } else if ((x == 0) && (y == 0) && - (desc->width == config->rgb_mode.panelHeight) && - (desc->height == config->rgb_mode.panelWidth) && - (desc->pitch == desc->width) && - IS_ENABLED(CONFIG_MCUX_ELCDIF_PXP)) { + } else if ((x == 0) && (y == 0) && (desc->width == config->rgb_mode.panelHeight) && + (desc->height == config->rgb_mode.panelWidth) && (desc->pitch == desc->width) && + IS_ENABLED(CONFIG_MCUX_ELCDIF_PXP)) { /* With the PXP, we can rotate this display buffer to align * with output dimensions */ - LOG_DBG("Setting FB from %p->%p", - (void *) dev_data->active_fb, (void *) buf); + LOG_DBG("Setting FB from %p->%p", (void *)dev_data->active_fb, (void *)buf); dev_data->active_fb = buf; full_fb = true; } else { @@ -130,14 +121,14 @@ static int mcux_elcdif_write(const struct device *dev, const uint16_t x, dst += config->pixel_bytes * config->rgb_mode.panelWidth; } - LOG_DBG("Setting FB from %p->%p", (void *) dev_data->active_fb, - (void *) dev_data->fb[dev_data->next_idx]); + LOG_DBG("Setting FB from %p->%p", (void *)dev_data->active_fb, + (void *)dev_data->fb[dev_data->next_idx]); /* Set new active framebuffer */ dev_data->active_fb = dev_data->fb[dev_data->next_idx]; } #ifdef CONFIG_HAS_MCUX_CACHE - DCACHE_CleanByRange((uint32_t) dev_data->active_fb, config->fb_bytes); + DCACHE_CleanByRange((uint32_t)dev_data->active_fb, config->fb_bytes); #endif #ifdef CONFIG_MCUX_ELCDIF_PXP @@ -200,12 +191,10 @@ static int mcux_elcdif_write(const struct device *dev, const uint16_t x, #if CONFIG_MCUX_ELCDIF_FB_NUM != 0 /* Update index of active framebuffer */ - dev_data->next_idx = - (dev_data->next_idx + 1) % CONFIG_MCUX_ELCDIF_FB_NUM; + dev_data->next_idx = (dev_data->next_idx + 1) % CONFIG_MCUX_ELCDIF_FB_NUM; #endif /* Enable frame buffer completion interrupt */ - ELCDIF_EnableInterrupts(config->base, - kELCDIF_CurFrameDoneInterruptEnable); + ELCDIF_EnableInterrupts(config->base, kELCDIF_CurFrameDoneInterruptEnable); /* Wait for frame send to complete */ k_sem_take(&dev_data->sem, K_FOREVER); return ret; @@ -226,8 +215,7 @@ static int mcux_elcdif_display_blanking_on(const struct device *dev) } static int mcux_elcdif_set_pixel_format(const struct device *dev, - const enum display_pixel_format - pixel_format) + const enum display_pixel_format pixel_format) { const struct mcux_elcdif_config *config = dev->config; @@ -239,7 +227,7 @@ static int mcux_elcdif_set_pixel_format(const struct device *dev, } static int mcux_elcdif_set_orientation(const struct device *dev, - const enum display_orientation orientation) + const enum display_orientation orientation) { if (orientation == DISPLAY_ORIENTATION_NORMAL) { return 0; @@ -249,7 +237,7 @@ static int mcux_elcdif_set_orientation(const struct device *dev, } static void mcux_elcdif_get_capabilities(const struct device *dev, - struct display_capabilities *capabilities) + struct display_capabilities *capabilities) { const struct mcux_elcdif_config *config = dev->config; @@ -273,8 +261,7 @@ static void mcux_elcdif_isr(const struct device *dev) /* Disable frame completion interrupt, post to * sem to notify that frame send is complete. */ - ELCDIF_DisableInterrupts(config->base, - kELCDIF_CurFrameDoneInterruptEnable); + ELCDIF_DisableInterrupts(config->base, kELCDIF_CurFrameDoneInterruptEnable); k_sem_give(&dev_data->sem); } } @@ -309,7 +296,7 @@ static int mcux_elcdif_init(const struct device *dev) dev_data->fb[i] = config->fb_ptr + (config->fb_bytes * i); } - rgb_mode.bufferAddr = (uint32_t) config->fb_ptr; + rgb_mode.bufferAddr = (uint32_t)config->fb_ptr; dev_data->active_fb = config->fb_ptr; k_sem_init(&dev_data->sem, 0, 1); @@ -338,82 +325,64 @@ static const struct display_driver_api mcux_elcdif_api = { .set_orientation = mcux_elcdif_set_orientation, }; -#define MCUX_ELCDIF_PIXEL_BYTES(id) \ - (DISPLAY_BITS_PER_PIXEL(DT_INST_PROP(id, pixel_format)) / 8) - -#define MCUX_ELCDIF_DEVICE_INIT(id) \ - PINCTRL_DT_INST_DEFINE(id); \ - static void mcux_elcdif_config_func_##id(const struct device *dev); \ - static uint8_t __aligned(64) frame_buffer_##id[CONFIG_MCUX_ELCDIF_FB_NUM\ - * DT_INST_PROP(id, width) \ - * DT_INST_PROP(id, height) \ - * MCUX_ELCDIF_PIXEL_BYTES(id)]; \ - static const struct mcux_elcdif_config mcux_elcdif_config_##id = { \ - .base = (LCDIF_Type *) DT_INST_REG_ADDR(id), \ - .irq_config_func = mcux_elcdif_config_func_##id, \ - .rgb_mode = { \ - .panelWidth = DT_INST_PROP(id, width), \ - .panelHeight = DT_INST_PROP(id, height), \ - .hsw = DT_PROP(DT_INST_CHILD(id, display_timings), \ - hsync_len), \ - .hfp = DT_PROP(DT_INST_CHILD(id, display_timings), \ - hfront_porch), \ - .hbp = DT_PROP(DT_INST_CHILD(id, display_timings), \ - hback_porch), \ - .vsw = DT_PROP(DT_INST_CHILD(id, display_timings), \ - vsync_len), \ - .vfp = DT_PROP(DT_INST_CHILD(id, display_timings), \ - vfront_porch), \ - .vbp = DT_PROP(DT_INST_CHILD(id, display_timings), \ - vback_porch), \ - .polarityFlags = (DT_PROP(DT_INST_CHILD(id, \ - display_timings), hsync_active) ? \ - kELCDIF_HsyncActiveHigh : \ - kELCDIF_HsyncActiveLow) | \ - (DT_PROP(DT_INST_CHILD(id, \ - display_timings), vsync_active) ? \ - kELCDIF_VsyncActiveHigh : \ - kELCDIF_VsyncActiveLow) | \ - (DT_PROP(DT_INST_CHILD(id, \ - display_timings), de_active) ? \ - kELCDIF_DataEnableActiveHigh : \ - kELCDIF_DataEnableActiveLow) | \ - (DT_PROP(DT_INST_CHILD(id, \ - display_timings), pixelclk_active) ? \ - kELCDIF_DriveDataOnRisingClkEdge : \ - kELCDIF_DriveDataOnFallingClkEdge), \ - .dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH( \ - DT_INST_ENUM_IDX(id, data_bus_width)), \ - }, \ - .pixel_format = DT_INST_PROP(id, pixel_format), \ - .pixel_bytes = MCUX_ELCDIF_PIXEL_BYTES(id), \ - .fb_bytes = DT_INST_PROP(id, width) * DT_INST_PROP(id, height) \ - * MCUX_ELCDIF_PIXEL_BYTES(id), \ - .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(id), \ - .backlight_gpio = GPIO_DT_SPEC_INST_GET(id, backlight_gpios), \ - .fb_ptr = frame_buffer_##id, \ - IF_ENABLED(CONFIG_MCUX_ELCDIF_PXP, \ - (.pxp = DEVICE_DT_GET(DT_INST_PHANDLE(id, nxp_pxp)),)) \ - }; \ - static struct mcux_elcdif_data mcux_elcdif_data_##id = { \ - .next_idx = 0, \ - }; \ - DEVICE_DT_INST_DEFINE(id, \ - &mcux_elcdif_init, \ - NULL, \ - &mcux_elcdif_data_##id, \ - &mcux_elcdif_config_##id, \ - POST_KERNEL, \ - CONFIG_DISPLAY_INIT_PRIORITY, \ - &mcux_elcdif_api); \ - static void mcux_elcdif_config_func_##id(const struct device *dev) \ - { \ - IRQ_CONNECT(DT_INST_IRQN(id), \ - DT_INST_IRQ(id, priority), \ - mcux_elcdif_isr, \ - DEVICE_DT_INST_GET(id), \ - 0); \ - irq_enable(DT_INST_IRQN(id)); \ +#define MCUX_ELCDIF_PIXEL_BYTES(id) (DISPLAY_BITS_PER_PIXEL(DT_INST_PROP(id, pixel_format)) / 8) + +#define MCUX_ELCDIF_DEVICE_INIT(id) \ + PINCTRL_DT_INST_DEFINE(id); \ + static void mcux_elcdif_config_func_##id(const struct device *dev); \ + static uint8_t __aligned(64) \ + frame_buffer_##id[CONFIG_MCUX_ELCDIF_FB_NUM * DT_INST_PROP(id, width) * \ + DT_INST_PROP(id, height) * MCUX_ELCDIF_PIXEL_BYTES(id)]; \ + static const struct mcux_elcdif_config mcux_elcdif_config_##id = { \ + .base = (LCDIF_Type *)DT_INST_REG_ADDR(id), \ + .irq_config_func = mcux_elcdif_config_func_##id, \ + .rgb_mode = \ + { \ + .panelWidth = DT_INST_PROP(id, width), \ + .panelHeight = DT_INST_PROP(id, height), \ + .hsw = DT_PROP(DT_INST_CHILD(id, display_timings), hsync_len), \ + .hfp = DT_PROP(DT_INST_CHILD(id, display_timings), hfront_porch), \ + .hbp = DT_PROP(DT_INST_CHILD(id, display_timings), hback_porch), \ + .vsw = DT_PROP(DT_INST_CHILD(id, display_timings), vsync_len), \ + .vfp = DT_PROP(DT_INST_CHILD(id, display_timings), vfront_porch), \ + .vbp = DT_PROP(DT_INST_CHILD(id, display_timings), vback_porch), \ + .polarityFlags = \ + (DT_PROP(DT_INST_CHILD(id, display_timings), hsync_active) \ + ? kELCDIF_HsyncActiveHigh \ + : kELCDIF_HsyncActiveLow) | \ + (DT_PROP(DT_INST_CHILD(id, display_timings), vsync_active) \ + ? kELCDIF_VsyncActiveHigh \ + : kELCDIF_VsyncActiveLow) | \ + (DT_PROP(DT_INST_CHILD(id, display_timings), de_active) \ + ? kELCDIF_DataEnableActiveHigh \ + : kELCDIF_DataEnableActiveLow) | \ + (DT_PROP(DT_INST_CHILD(id, display_timings), \ + pixelclk_active) \ + ? kELCDIF_DriveDataOnRisingClkEdge \ + : kELCDIF_DriveDataOnFallingClkEdge), \ + .dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH( \ + DT_INST_ENUM_IDX(id, data_bus_width)), \ + }, \ + .pixel_format = DT_INST_PROP(id, pixel_format), \ + .pixel_bytes = MCUX_ELCDIF_PIXEL_BYTES(id), \ + .fb_bytes = DT_INST_PROP(id, width) * DT_INST_PROP(id, height) * \ + MCUX_ELCDIF_PIXEL_BYTES(id), \ + .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(id), \ + .backlight_gpio = GPIO_DT_SPEC_INST_GET(id, backlight_gpios), \ + .fb_ptr = frame_buffer_##id, \ + IF_ENABLED(CONFIG_MCUX_ELCDIF_PXP, \ + (.pxp = DEVICE_DT_GET(DT_INST_PHANDLE(id, nxp_pxp)),))}; \ + static struct mcux_elcdif_data mcux_elcdif_data_##id = { \ + .next_idx = 0, \ + }; \ + DEVICE_DT_INST_DEFINE(id, &mcux_elcdif_init, NULL, &mcux_elcdif_data_##id, \ + &mcux_elcdif_config_##id, POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, \ + &mcux_elcdif_api); \ + static void mcux_elcdif_config_func_##id(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(id), DT_INST_IRQ(id, priority), mcux_elcdif_isr, \ + DEVICE_DT_INST_GET(id), 0); \ + irq_enable(DT_INST_IRQN(id)); \ } DT_INST_FOREACH_STATUS_OKAY(MCUX_ELCDIF_DEVICE_INIT) From f5e970de3fdfd0791bf01a45d0a1d0b09c2d15a5 Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Tue, 13 Feb 2024 15:25:53 +0100 Subject: [PATCH 0283/2402] drivers: display: elcdif: Add support for ARGB8888 format Add support for ARGB8888 pixel format as the camera pipeline on i.MX RT11xx could output images in this format Signed-off-by: Phi Bang Nguyen --- drivers/display/display_mcux_elcdif.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/display/display_mcux_elcdif.c b/drivers/display/display_mcux_elcdif.c index b6595966772..a4dd3ce1c0b 100644 --- a/drivers/display/display_mcux_elcdif.c +++ b/drivers/display/display_mcux_elcdif.c @@ -27,6 +27,8 @@ LOG_MODULE_REGISTER(display_mcux_elcdif, CONFIG_DISPLAY_LOG_LEVEL); +static const uint32_t supported_fmts = PIXEL_FORMAT_BGR_565 | PIXEL_FORMAT_ARGB_8888; + struct mcux_elcdif_config { LCDIF_Type *base; void (*irq_config_func)(const struct device *dev); @@ -150,6 +152,8 @@ static int mcux_elcdif_write(const struct device *dev, const uint16_t x, const u pxp_dma.dma_slot = DMA_MCUX_PXP_FMT(DMA_MCUX_PXP_FMT_RGB565); } else if (config->pixel_format == PIXEL_FORMAT_RGB_888) { pxp_dma.dma_slot = DMA_MCUX_PXP_FMT(DMA_MCUX_PXP_FMT_RGB888); + } else if (config->pixel_format == PIXEL_FORMAT_ARGB_8888) { + pxp_dma.dma_slot = DMA_MCUX_PXP_FMT(DMA_MCUX_PXP_FMT_ARGB8888); } else { /* Cannot rotate */ return -ENOTSUP; @@ -244,7 +248,7 @@ static void mcux_elcdif_get_capabilities(const struct device *dev, memset(capabilities, 0, sizeof(struct display_capabilities)); capabilities->x_resolution = config->rgb_mode.panelWidth; capabilities->y_resolution = config->rgb_mode.panelHeight; - capabilities->supported_pixel_formats = config->pixel_format; + capabilities->supported_pixel_formats = supported_fmts; capabilities->current_pixel_format = config->pixel_format; capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL; } @@ -289,6 +293,8 @@ static int mcux_elcdif_init(const struct device *dev) rgb_mode.pixelFormat = kELCDIF_PixelFormatRGB565; } else if (config->pixel_format == PIXEL_FORMAT_RGB_888) { rgb_mode.pixelFormat = kELCDIF_PixelFormatRGB888; + } else if (config->pixel_format == PIXEL_FORMAT_ARGB_8888) { + rgb_mode.pixelFormat = kELCDIF_PixelFormatXRGB8888; } for (int i = 0; i < CONFIG_MCUX_ELCDIF_FB_NUM; i++) { From 080f26f4d4ec71e8536948a9e367d138ad542155 Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Mon, 19 Feb 2024 18:55:27 +0100 Subject: [PATCH 0284/2402] drivers: display: elcdif: Implement set_format API Implement the set_format API so that applications can change format at runtime instead of using the predefined one in the device tree. Signed-off-by: Phi Bang Nguyen --- drivers/display/Kconfig.mcux_elcdif | 10 +++ drivers/display/display_mcux_elcdif.c | 111 ++++++++++++++------------ 2 files changed, 70 insertions(+), 51 deletions(-) diff --git a/drivers/display/Kconfig.mcux_elcdif b/drivers/display/Kconfig.mcux_elcdif index 7bf2ba28624..43f90374380 100644 --- a/drivers/display/Kconfig.mcux_elcdif +++ b/drivers/display/Kconfig.mcux_elcdif @@ -32,6 +32,16 @@ config MCUX_ELCDIF_FB_NUM implications of this concern you, leave at least one driver framebuffer enabled. +config MCUX_ELCDIF_FB_SIZE + int "Framebuffer size required by the eLCDIF driver" + default 3686400 + help + eLCDIF driver allocates framebuffers to support partial display updates. + The framebuffer size is computed as : panel_width * panel_height * bpp. + The default value is set to afford for a default resolution of 1280x720 and + 4-bytes pixel format, e.g. ARGB8888. Applications should change this value + according to the actual used resolution and format to optimize the heap size. + config MCUX_ELCDIF_PXP bool "Use PXP for display rotation" depends on MCUX_PXP diff --git a/drivers/display/display_mcux_elcdif.c b/drivers/display/display_mcux_elcdif.c index a4dd3ce1c0b..e4b45f89d40 100644 --- a/drivers/display/display_mcux_elcdif.c +++ b/drivers/display/display_mcux_elcdif.c @@ -27,18 +27,17 @@ LOG_MODULE_REGISTER(display_mcux_elcdif, CONFIG_DISPLAY_LOG_LEVEL); +/* Define the heap size. 512 bytes of padding are included for kernel heap structures */ +K_HEAP_DEFINE(display_heap, CONFIG_MCUX_ELCDIF_FB_NUM * CONFIG_MCUX_ELCDIF_FB_SIZE + 512); + static const uint32_t supported_fmts = PIXEL_FORMAT_BGR_565 | PIXEL_FORMAT_ARGB_8888; struct mcux_elcdif_config { LCDIF_Type *base; void (*irq_config_func)(const struct device *dev); elcdif_rgb_mode_config_t rgb_mode; - enum display_pixel_format pixel_format; - size_t pixel_bytes; - size_t fb_bytes; const struct pinctrl_dev_config *pincfg; const struct gpio_dt_spec backlight_gpio; - uint8_t *fb_ptr; const struct device *pxp; }; @@ -47,6 +46,10 @@ struct mcux_elcdif_data { const uint8_t *active_fb; /* Pointers to driver allocated framebuffers */ uint8_t *fb[CONFIG_MCUX_ELCDIF_FB_NUM]; + enum display_pixel_format pixel_format; + size_t pixel_bytes; + size_t fb_bytes; + elcdif_rgb_mode_config_t rgb_mode; struct k_sem sem; /* Tracks index of next active driver framebuffer */ uint8_t next_idx; @@ -77,7 +80,7 @@ static int mcux_elcdif_write(const struct device *dev, const uint16_t x, const u int ret = 0; bool full_fb = false; - __ASSERT((config->pixel_bytes * desc->pitch * desc->height) <= desc->buf_size, + __ASSERT((dev_data->pixel_bytes * desc->pitch * desc->height) <= desc->buf_size, "Input buffer too small"); LOG_DBG("W=%d, H=%d, @%d,%d", desc->width, desc->height, x, y); @@ -110,17 +113,17 @@ static int mcux_elcdif_write(const struct device *dev, const uint16_t x, const u */ src = dev_data->active_fb; dst = dev_data->fb[dev_data->next_idx]; - memcpy(dst, src, config->fb_bytes); + memcpy(dst, src, dev_data->fb_bytes); } /* Now, write the display update into active framebuffer */ src = buf; dst = dev_data->fb[dev_data->next_idx]; - dst += config->pixel_bytes * (y * config->rgb_mode.panelWidth + x); + dst += dev_data->pixel_bytes * (y * config->rgb_mode.panelWidth + x); for (h_idx = 0; h_idx < desc->height; h_idx++) { - memcpy(dst, src, config->pixel_bytes * desc->width); - src += config->pixel_bytes * desc->pitch; - dst += config->pixel_bytes * config->rgb_mode.panelWidth; + memcpy(dst, src, dev_data->pixel_bytes * desc->width); + src += dev_data->pixel_bytes * desc->pitch; + dst += dev_data->pixel_bytes * config->rgb_mode.panelWidth; } LOG_DBG("Setting FB from %p->%p", (void *)dev_data->active_fb, @@ -130,7 +133,7 @@ static int mcux_elcdif_write(const struct device *dev, const uint16_t x, const u } #ifdef CONFIG_HAS_MCUX_CACHE - DCACHE_CleanByRange((uint32_t)dev_data->active_fb, config->fb_bytes); + DCACHE_CleanByRange((uint32_t)dev_data->active_fb, dev_data->fb_bytes); #endif #ifdef CONFIG_MCUX_ELCDIF_PXP @@ -148,11 +151,11 @@ static int mcux_elcdif_write(const struct device *dev, const uint16_t x, const u pxp_block.block_size = desc->buf_size; /* DMA slot sets pixel format and rotation angle */ - if (config->pixel_format == PIXEL_FORMAT_BGR_565) { + if (dev_data->pixel_format == PIXEL_FORMAT_BGR_565) { pxp_dma.dma_slot = DMA_MCUX_PXP_FMT(DMA_MCUX_PXP_FMT_RGB565); - } else if (config->pixel_format == PIXEL_FORMAT_RGB_888) { + } else if (dev_data->pixel_format == PIXEL_FORMAT_RGB_888) { pxp_dma.dma_slot = DMA_MCUX_PXP_FMT(DMA_MCUX_PXP_FMT_RGB888); - } else if (config->pixel_format == PIXEL_FORMAT_ARGB_8888) { + } else if (dev_data->pixel_format == PIXEL_FORMAT_ARGB_8888) { pxp_dma.dma_slot = DMA_MCUX_PXP_FMT(DMA_MCUX_PXP_FMT_ARGB8888); } else { /* Cannot rotate */ @@ -169,8 +172,8 @@ static int mcux_elcdif_write(const struct device *dev, const uint16_t x, const u } pxp_dma.channel_direction = MEMORY_TO_MEMORY; - pxp_dma.source_data_size = desc->width * config->pixel_bytes; - pxp_dma.dest_data_size = config->rgb_mode.panelWidth * config->pixel_bytes; + pxp_dma.source_data_size = desc->width * dev_data->pixel_bytes; + pxp_dma.dest_data_size = config->rgb_mode.panelWidth * dev_data->pixel_bytes; /* Burst lengths are heights of source/dest buffer in pixels */ pxp_dma.source_burst_length = desc->height; pxp_dma.dest_burst_length = config->rgb_mode.panelHeight; @@ -221,13 +224,42 @@ static int mcux_elcdif_display_blanking_on(const struct device *dev) static int mcux_elcdif_set_pixel_format(const struct device *dev, const enum display_pixel_format pixel_format) { + struct mcux_elcdif_data *dev_data = dev->data; const struct mcux_elcdif_config *config = dev->config; - if (pixel_format == config->pixel_format) { - return 0; + if (!(pixel_format & supported_fmts)) { + LOG_ERR("Unsupported pixel format"); + return -ENOTSUP; } - LOG_ERR("Pixel format change not implemented"); - return -ENOTSUP; + + dev_data->pixel_format = pixel_format; + dev_data->pixel_bytes = DISPLAY_BITS_PER_PIXEL(pixel_format) / 8; + dev_data->fb_bytes = + config->rgb_mode.panelWidth * config->rgb_mode.panelHeight * dev_data->pixel_bytes; + + for (int i = 0; i < CONFIG_MCUX_ELCDIF_FB_NUM; i++) { + k_heap_free(&display_heap, dev_data->fb[i]); + dev_data->fb[i] = + k_heap_aligned_alloc(&display_heap, 64, dev_data->fb_bytes, K_FOREVER); + if (dev_data->fb[i] == NULL) { + LOG_ERR("Could not allocate memory for framebuffers"); + return -ENOMEM; + } + memset(dev_data->fb[i], 0, dev_data->fb_bytes); + } + + dev_data->rgb_mode = config->rgb_mode; + if (pixel_format == PIXEL_FORMAT_BGR_565) { + dev_data->rgb_mode.pixelFormat = kELCDIF_PixelFormatRGB565; + } else if (pixel_format == PIXEL_FORMAT_RGB_888) { + dev_data->rgb_mode.pixelFormat = kELCDIF_PixelFormatRGB888; + } else if (pixel_format == PIXEL_FORMAT_ARGB_8888) { + dev_data->rgb_mode.pixelFormat = kELCDIF_PixelFormatXRGB8888; + } + + ELCDIF_RgbModeSetPixelFormat(config->base, dev_data->rgb_mode.pixelFormat); + + return 0; } static int mcux_elcdif_set_orientation(const struct device *dev, @@ -249,7 +281,7 @@ static void mcux_elcdif_get_capabilities(const struct device *dev, capabilities->x_resolution = config->rgb_mode.panelWidth; capabilities->y_resolution = config->rgb_mode.panelHeight; capabilities->supported_pixel_formats = supported_fmts; - capabilities->current_pixel_format = config->pixel_format; + capabilities->current_pixel_format = ((struct mcux_elcdif_data *)dev->data)->pixel_format; capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL; } @@ -286,25 +318,6 @@ static int mcux_elcdif_init(const struct device *dev) return err; } - elcdif_rgb_mode_config_t rgb_mode = config->rgb_mode; - - /* Set the Pixel format */ - if (config->pixel_format == PIXEL_FORMAT_BGR_565) { - rgb_mode.pixelFormat = kELCDIF_PixelFormatRGB565; - } else if (config->pixel_format == PIXEL_FORMAT_RGB_888) { - rgb_mode.pixelFormat = kELCDIF_PixelFormatRGB888; - } else if (config->pixel_format == PIXEL_FORMAT_ARGB_8888) { - rgb_mode.pixelFormat = kELCDIF_PixelFormatXRGB8888; - } - - for (int i = 0; i < CONFIG_MCUX_ELCDIF_FB_NUM; i++) { - /* Record pointers to each driver framebuffer */ - dev_data->fb[i] = config->fb_ptr + (config->fb_bytes * i); - } - - rgb_mode.bufferAddr = (uint32_t)config->fb_ptr; - dev_data->active_fb = config->fb_ptr; - k_sem_init(&dev_data->sem, 0, 1); #ifdef CONFIG_MCUX_ELCDIF_PXP k_sem_init(&dev_data->pxp_done, 0, 1); @@ -316,7 +329,12 @@ static int mcux_elcdif_init(const struct device *dev) config->irq_config_func(dev); - ELCDIF_RgbModeInit(config->base, &rgb_mode); + /* Set default pixel format obtained from device tree */ + mcux_elcdif_set_pixel_format(dev, dev_data->pixel_format); + + dev_data->active_fb = dev_data->fb[0]; + + ELCDIF_RgbModeInit(config->base, &dev_data->rgb_mode); ELCDIF_RgbModeStart(config->base); return 0; @@ -331,14 +349,9 @@ static const struct display_driver_api mcux_elcdif_api = { .set_orientation = mcux_elcdif_set_orientation, }; -#define MCUX_ELCDIF_PIXEL_BYTES(id) (DISPLAY_BITS_PER_PIXEL(DT_INST_PROP(id, pixel_format)) / 8) - #define MCUX_ELCDIF_DEVICE_INIT(id) \ PINCTRL_DT_INST_DEFINE(id); \ static void mcux_elcdif_config_func_##id(const struct device *dev); \ - static uint8_t __aligned(64) \ - frame_buffer_##id[CONFIG_MCUX_ELCDIF_FB_NUM * DT_INST_PROP(id, width) * \ - DT_INST_PROP(id, height) * MCUX_ELCDIF_PIXEL_BYTES(id)]; \ static const struct mcux_elcdif_config mcux_elcdif_config_##id = { \ .base = (LCDIF_Type *)DT_INST_REG_ADDR(id), \ .irq_config_func = mcux_elcdif_config_func_##id, \ @@ -369,17 +382,13 @@ static const struct display_driver_api mcux_elcdif_api = { .dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH( \ DT_INST_ENUM_IDX(id, data_bus_width)), \ }, \ - .pixel_format = DT_INST_PROP(id, pixel_format), \ - .pixel_bytes = MCUX_ELCDIF_PIXEL_BYTES(id), \ - .fb_bytes = DT_INST_PROP(id, width) * DT_INST_PROP(id, height) * \ - MCUX_ELCDIF_PIXEL_BYTES(id), \ .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(id), \ .backlight_gpio = GPIO_DT_SPEC_INST_GET(id, backlight_gpios), \ - .fb_ptr = frame_buffer_##id, \ IF_ENABLED(CONFIG_MCUX_ELCDIF_PXP, \ (.pxp = DEVICE_DT_GET(DT_INST_PHANDLE(id, nxp_pxp)),))}; \ static struct mcux_elcdif_data mcux_elcdif_data_##id = { \ .next_idx = 0, \ + .pixel_format = DT_INST_PROP(id, pixel_format), \ }; \ DEVICE_DT_INST_DEFINE(id, &mcux_elcdif_init, NULL, &mcux_elcdif_data_##id, \ &mcux_elcdif_config_##id, POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, \ From 5607a446581182c1f4f5f0709eaf9ac94cd35cfc Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Wed, 21 Feb 2024 23:09:26 +0100 Subject: [PATCH 0285/2402] samples: drivers: display: Modify heap size configs for RT595 & RT1170 The heap size for i.MX RT1170 is way too much while for i.MX RT595, it is too small to afford for 4-bytes formats, e.g. ARGB8888. Signed-off-by: Phi Bang Nguyen --- .../display/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf | 5 ++++- .../display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf | 2 +- samples/drivers/display/boards/mimxrt1170_evkb_cm7.conf | 5 ++++- .../display/boards/mimxrt595_evk_mimxrt595s_cm33.conf | 8 ++++---- 4 files changed, 13 insertions(+), 7 deletions(-) diff --git a/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf index d5fb0e239e3..af2acc5acf0 100644 --- a/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf +++ b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -4,4 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_HEAP_MEM_POOL_SIZE=4194304 +# Sample will allocate buffer equal to: (panelwidth / 8) * (panelwidth / 4) * pixel depth. For a +# 1280x720 display in a 32-bpp format (e.g. ARGB8888), this is (720 / 8) * (720 / 4) * 4 = 64800 +# bytes. We include 128 bytes of padding for kernel heap structures +CONFIG_HEAP_MEM_POOL_SIZE=64928 diff --git a/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf index 072545354b9..0fbbef94c32 100644 --- a/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf +++ b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -4,4 +4,4 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_HEAP_MEM_POOL_SIZE=4194304 +CONFIG_HEAP_MEM_POOL_SIZE=64928 diff --git a/samples/drivers/display/boards/mimxrt1170_evkb_cm7.conf b/samples/drivers/display/boards/mimxrt1170_evkb_cm7.conf index 072545354b9..c8e665357ca 100644 --- a/samples/drivers/display/boards/mimxrt1170_evkb_cm7.conf +++ b/samples/drivers/display/boards/mimxrt1170_evkb_cm7.conf @@ -4,4 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_HEAP_MEM_POOL_SIZE=4194304 +# Sample will allocate buffer equal to: (panelwidth / 8) * (panelwidth / 4) * pixel depth. For a +# 1280x720 display in a 32-bpp format (e.g. ARGB8888), this is (720 / 8) * (720 / 4) * 4 = 64800 +# bytes. We include 128 bytes of padding for kernel heap structures +CONFIG_HEAP_MEM_POOL_SIZE=64928 diff --git a/samples/drivers/display/boards/mimxrt595_evk_mimxrt595s_cm33.conf b/samples/drivers/display/boards/mimxrt595_evk_mimxrt595s_cm33.conf index 06ab28637ed..c8e665357ca 100644 --- a/samples/drivers/display/boards/mimxrt595_evk_mimxrt595s_cm33.conf +++ b/samples/drivers/display/boards/mimxrt595_evk_mimxrt595s_cm33.conf @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -# Sample will allocate buffer equal to: (height / 8) * (height / 4) * pixel depth -# For the 1280x720 16 bit display, this is (720 / 8) * (720 / 4) * 2 = 32400 bytes -# We include 128 bytes of padding for kernel heap structures -CONFIG_HEAP_MEM_POOL_SIZE=32528 +# Sample will allocate buffer equal to: (panelwidth / 8) * (panelwidth / 4) * pixel depth. For a +# 1280x720 display in a 32-bpp format (e.g. ARGB8888), this is (720 / 8) * (720 / 4) * 4 = 64800 +# bytes. We include 128 bytes of padding for kernel heap structures +CONFIG_HEAP_MEM_POOL_SIZE=64928 From 7540535284509f77dcb96c5cb01bfa13a08dc10a Mon Sep 17 00:00:00 2001 From: Andries Kruithof Date: Thu, 22 Feb 2024 15:53:12 +0100 Subject: [PATCH 0286/2402] Bluetooth: audio: BAP: allow for multiple callbacks The existing implementation allows for only one callback per procedure. This creates problems when for example adding CAP functionality. The callbacks are here implemented as an SLIST Signed-off-by: Andries Kruithof --- include/zephyr/bluetooth/audio/bap.h | 22 +- .../bluetooth/audio/bap_broadcast_assistant.c | 244 ++++++++++-------- 2 files changed, 162 insertions(+), 104 deletions(-) diff --git a/include/zephyr/bluetooth/audio/bap.h b/include/zephyr/bluetooth/audio/bap.h index 9584a459c87..022bc53b3ba 100644 --- a/include/zephyr/bluetooth/audio/bap.h +++ b/include/zephyr/bluetooth/audio/bap.h @@ -2150,6 +2150,8 @@ struct bt_bap_broadcast_assistant_cb { * @param err Error value. 0 on success, GATT error on fail. */ void (*rem_src)(struct bt_conn *conn, int err); + + sys_snode_t _node; }; /** @@ -2193,8 +2195,26 @@ int bt_bap_broadcast_assistant_scan_stop(struct bt_conn *conn); /** * @brief Registers the callbacks used by Broadcast Audio Scan Service client. + * + * @param cb The callback structure. + * + * @retval 0 on success + * @retval -EINVAL if @p cb is NULL + * @retval -EALREADY if @p cb was already registered + */ +int bt_bap_broadcast_assistant_register_cb(struct bt_bap_broadcast_assistant_cb *cb); + +/** + * @brief Unregisters the callbacks used by the Broadcast Audio Scan Service client. + * + * @param cb The callback structure. + * + * @retval 0 on success + * @retval -EINVAL if @p cb is NULL + * @retval -EALREADY if @p cb was not registered */ -void bt_bap_broadcast_assistant_register_cb(struct bt_bap_broadcast_assistant_cb *cb); +int bt_bap_broadcast_assistant_unregister_cb(struct bt_bap_broadcast_assistant_cb *cb); + /** Parameters for adding a source to a Broadcast Audio Scan Service server */ struct bt_bap_broadcast_assistant_add_src_param { diff --git a/subsys/bluetooth/audio/bap_broadcast_assistant.c b/subsys/bluetooth/audio/bap_broadcast_assistant.c index 2c2ecf978b4..17c6330164f 100644 --- a/subsys/bluetooth/audio/bap_broadcast_assistant.c +++ b/subsys/bluetooth/audio/bap_broadcast_assistant.c @@ -64,7 +64,7 @@ struct bap_broadcast_assistant_instance { uint16_t long_read_handle; }; -static struct bt_bap_broadcast_assistant_cb *broadcast_assistant_cbs; +static sys_slist_t broadcast_assistant_cbs = SYS_SLIST_STATIC_INIT(&broadcast_assistant_cbs); static struct bap_broadcast_assistant_instance broadcast_assistant; static struct bt_uuid_16 uuid = BT_UUID_INIT_16(0); @@ -85,6 +85,57 @@ static int16_t lookup_index_by_handle(uint16_t handle) return -1; } +static void bap_broadcast_assistant_discover_complete(struct bt_conn *conn, int err, + uint8_t recv_state_count) +{ + struct bt_bap_broadcast_assistant_cb *listener, *next; + + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&broadcast_assistant_cbs, + listener, next, _node) { + if (listener->discover) { + listener->discover(conn, err, recv_state_count); + } + } +} + +static void bap_broadcast_assistant_recv_state_changed( + struct bt_conn *conn, int err, const struct bt_bap_scan_delegator_recv_state *state) +{ + struct bt_bap_broadcast_assistant_cb *listener, *next; + + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&broadcast_assistant_cbs, + listener, next, _node) { + if (listener->recv_state) { + listener->recv_state(conn, err, state); + } + } +} + +static void bap_broadcast_assistant_recv_state_removed(struct bt_conn *conn, int err, + uint8_t src_id) +{ + struct bt_bap_broadcast_assistant_cb *listener, *next; + + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&broadcast_assistant_cbs, + listener, next, _node) { + if (listener->recv_state_removed) { + listener->recv_state_removed(conn, err, src_id); + } + } +} + +static void bap_broadcast_assistant_scan_results(const struct bt_le_scan_recv_info *info, + uint32_t broadcast_id) +{ + struct bt_bap_broadcast_assistant_cb *listener, *next; + + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&broadcast_assistant_cbs, listener, next, _node) { + if (listener->scan) { + listener->scan(info, broadcast_id); + } + } +} + static bool past_available(const struct bt_conn *conn, const bt_addr_le_t *adv_addr, uint8_t sid) @@ -223,10 +274,7 @@ static uint8_t parse_and_send_recv_state(struct bt_conn *conn, uint16_t handle, &recv_state->addr, recv_state->adv_sid); - if (broadcast_assistant_cbs != NULL && - broadcast_assistant_cbs->recv_state != NULL) { - broadcast_assistant_cbs->recv_state(conn, 0, recv_state); - } + bap_broadcast_assistant_recv_state_changed(conn, 0, recv_state); return BT_GATT_ITER_CONTINUE; } @@ -381,11 +429,9 @@ static uint8_t notify_handler(struct bt_conn *conn, } else { return parse_and_send_recv_state(conn, handle, data, length, &recv_state); } - } else if (broadcast_assistant_cbs != NULL && - broadcast_assistant_cbs->recv_state_removed != NULL) { - broadcast_assistant.past_avail[index] = false; - broadcast_assistant_cbs->recv_state_removed(conn, 0, - broadcast_assistant.src_ids[index]); + } else { + bap_broadcast_assistant_recv_state_removed(conn, 0, + broadcast_assistant.src_ids[index]); } return BT_GATT_ITER_CONTINUE; @@ -429,44 +475,24 @@ static uint8_t read_recv_state_cb(struct bt_conn *conn, uint8_t err, } if (cb_err != 0) { - LOG_DBG("err: %d", cb_err); + LOG_DBG("err %d", cb_err); + if (broadcast_assistant.busy) { broadcast_assistant.busy = false; - if (broadcast_assistant_cbs != NULL && - broadcast_assistant_cbs->discover != NULL) { - broadcast_assistant_cbs->discover(conn, - cb_err, 0); - } + bap_broadcast_assistant_discover_complete(conn, cb_err, 0); } else { - if (broadcast_assistant_cbs != NULL && - broadcast_assistant_cbs->recv_state != NULL) { - broadcast_assistant_cbs->recv_state(conn, - cb_err, - NULL); - } + bap_broadcast_assistant_recv_state_changed(conn, cb_err, NULL); } } else if (handle == last_handle) { if (broadcast_assistant.busy) { + const uint8_t recv_state_cnt = broadcast_assistant.recv_state_cnt; + broadcast_assistant.busy = false; - if (broadcast_assistant_cbs != NULL && - broadcast_assistant_cbs->discover != NULL) { - broadcast_assistant_cbs->discover( - conn, cb_err, - broadcast_assistant.recv_state_cnt); - } + bap_broadcast_assistant_discover_complete(conn, cb_err, recv_state_cnt); } else { - if (broadcast_assistant_cbs != NULL && - broadcast_assistant_cbs->recv_state != NULL) { - if (active_recv_state) { - broadcast_assistant_cbs->recv_state(conn, - cb_err, - &recv_state); - } else { - broadcast_assistant_cbs->recv_state(conn, - cb_err, - NULL); - } - } + bap_broadcast_assistant_recv_state_changed(conn, cb_err, + active_recv_state ? + &recv_state : NULL); } } else { for (uint8_t i = 0U; i < broadcast_assistant.recv_state_cnt; i++) { @@ -510,10 +536,7 @@ static uint8_t char_discover_func(struct bt_conn *conn, err = bt_bap_broadcast_assistant_read_recv_state(conn, 0); if (err != 0) { broadcast_assistant.busy = false; - if (broadcast_assistant_cbs != NULL && - broadcast_assistant_cbs->discover != NULL) { - broadcast_assistant_cbs->discover(conn, err, 0); - } + bap_broadcast_assistant_discover_complete(conn, err, 0); } return BT_GATT_ITER_STOP; @@ -557,12 +580,9 @@ static uint8_t char_discover_func(struct bt_conn *conn, sub_params->value_handle, err); broadcast_assistant.busy = false; - if (broadcast_assistant_cbs != NULL && - broadcast_assistant_cbs->discover != NULL) { - broadcast_assistant_cbs->discover(conn, - err, - 0); - } + LOG_DBG("no handle discover callback"); + + bap_broadcast_assistant_discover_complete(conn, err, 0); return BT_GATT_ITER_STOP; } @@ -584,12 +604,9 @@ static uint8_t service_discover_func(struct bt_conn *conn, (void)memset(params, 0, sizeof(*params)); broadcast_assistant.busy = false; + err = BT_GATT_ERR(BT_ATT_ERR_NOT_SUPPORTED); - if (broadcast_assistant_cbs != NULL && - broadcast_assistant_cbs->discover != NULL) { - err = BT_GATT_ERR(BT_ATT_ERR_NOT_SUPPORTED); - broadcast_assistant_cbs->discover(conn, err, 0); - } + bap_broadcast_assistant_discover_complete(conn, err, 0); return BT_GATT_ITER_STOP; } @@ -611,11 +628,7 @@ static uint8_t service_discover_func(struct bt_conn *conn, if (err != 0) { LOG_DBG("Discover failed (err %d)", err); broadcast_assistant.busy = false; - - if (broadcast_assistant_cbs != NULL && - broadcast_assistant_cbs->discover != NULL) { - broadcast_assistant_cbs->discover(conn, err, 0); - } + bap_broadcast_assistant_discover_complete(conn, err, 0); } } @@ -625,51 +638,50 @@ static uint8_t service_discover_func(struct bt_conn *conn, static void bap_broadcast_assistant_write_cp_cb(struct bt_conn *conn, uint8_t err, struct bt_gatt_write_params *params) { + struct bt_bap_broadcast_assistant_cb *listener, *next; uint8_t opcode = net_buf_simple_pull_u8(&att_buf); broadcast_assistant.busy = false; - if (broadcast_assistant_cbs == NULL) { - return; - } - /* we reset the buffer, so that we are ready for new notifications and writes */ net_buf_simple_reset(&att_buf); - switch (opcode) { - case BT_BAP_BASS_OP_SCAN_STOP: - if (broadcast_assistant_cbs->scan_stop != NULL) { - broadcast_assistant_cbs->scan_stop(conn, err); - } - break; - case BT_BAP_BASS_OP_SCAN_START: - if (broadcast_assistant_cbs->scan_start != NULL) { - broadcast_assistant_cbs->scan_start(conn, err); - } - break; - case BT_BAP_BASS_OP_ADD_SRC: - if (broadcast_assistant_cbs->add_src != NULL) { - broadcast_assistant_cbs->add_src(conn, err); - } - break; - case BT_BAP_BASS_OP_MOD_SRC: - if (broadcast_assistant_cbs->mod_src != NULL) { - broadcast_assistant_cbs->mod_src(conn, err); - } - break; - case BT_BAP_BASS_OP_BROADCAST_CODE: - if (broadcast_assistant_cbs->broadcast_code != NULL) { - broadcast_assistant_cbs->broadcast_code(conn, err); - } - break; - case BT_BAP_BASS_OP_REM_SRC: - if (broadcast_assistant_cbs->rem_src != NULL) { - broadcast_assistant_cbs->rem_src(conn, err); + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&broadcast_assistant_cbs, listener, next, _node) { + switch (opcode) { + case BT_BAP_BASS_OP_SCAN_STOP: + if (listener->scan_stop != NULL) { + listener->scan_stop(conn, err); + } + break; + case BT_BAP_BASS_OP_SCAN_START: + if (listener->scan_start != NULL) { + listener->scan_start(conn, err); + } + break; + case BT_BAP_BASS_OP_ADD_SRC: + if (listener->add_src != NULL) { + listener->add_src(conn, err); + } + break; + case BT_BAP_BASS_OP_MOD_SRC: + if (listener->mod_src != NULL) { + listener->mod_src(conn, err); + } + break; + case BT_BAP_BASS_OP_BROADCAST_CODE: + if (listener->broadcast_code != NULL) { + listener->broadcast_code(conn, err); + } + break; + case BT_BAP_BASS_OP_REM_SRC: + if (listener->rem_src != NULL) { + listener->rem_src(conn, err); + } + break; + default: + LOG_DBG("Unknown opcode 0x%02x", opcode); + break; } - break; - default: - LOG_DBG("Unknown opcode 0x%02x", opcode); - break; } } @@ -729,10 +741,7 @@ static bool broadcast_source_found(struct bt_data *data, void *user_data) LOG_DBG("Found BIS advertiser with address %s SID 0x%02X and broadcast_id 0x%06X", bt_addr_le_str(info->addr), info->sid, broadcast_id); - if (broadcast_assistant_cbs != NULL && - broadcast_assistant_cbs->scan != NULL) { - broadcast_assistant_cbs->scan(info, broadcast_id); - } + bap_broadcast_assistant_scan_results(info, broadcast_id); return false; } @@ -861,9 +870,38 @@ int bt_bap_broadcast_assistant_discover(struct bt_conn *conn) return 0; } -void bt_bap_broadcast_assistant_register_cb(struct bt_bap_broadcast_assistant_cb *cb) +/* TODO: naming is different from e.g. bt_vcp_vol_ctrl_cb_register */ +int bt_bap_broadcast_assistant_register_cb(struct bt_bap_broadcast_assistant_cb *cb) { - broadcast_assistant_cbs = cb; + struct bt_bap_broadcast_assistant_cb *tmp; + + CHECKIF(cb == NULL) { + return -EINVAL; + } + + SYS_SLIST_FOR_EACH_CONTAINER(&broadcast_assistant_cbs, tmp, _node) { + if (tmp == cb) { + LOG_DBG("Already registered"); + return -EALREADY; + } + } + + sys_slist_append(&broadcast_assistant_cbs, &cb->_node); + + return 0; +} + +int bt_bap_broadcast_assistant_unregister_cb(struct bt_bap_broadcast_assistant_cb *cb) +{ + CHECKIF(cb == NULL) { + return -EINVAL; + } + + if (!sys_slist_find_and_remove(&broadcast_assistant_cbs, &cb->_node)) { + return -EALREADY; + } + + return 0; } int bt_bap_broadcast_assistant_scan_start(struct bt_conn *conn, bool start_scan) From fd2ccbc5ba92c00a40e02d03ade841f6244a86bf Mon Sep 17 00:00:00 2001 From: Andries Kruithof Date: Tue, 27 Feb 2024 08:53:05 +0100 Subject: [PATCH 0287/2402] Bluetooth: audio: BAP: set the past_avail status While refactoring the handling of callbacks the setting of past_avail status got deleted (and it was in the wrong place). Adding it back at the correct place. Signed-off-by: Andries Kruithof --- subsys/bluetooth/audio/bap_broadcast_assistant.c | 1 + 1 file changed, 1 insertion(+) diff --git a/subsys/bluetooth/audio/bap_broadcast_assistant.c b/subsys/bluetooth/audio/bap_broadcast_assistant.c index 17c6330164f..557830452d5 100644 --- a/subsys/bluetooth/audio/bap_broadcast_assistant.c +++ b/subsys/bluetooth/audio/bap_broadcast_assistant.c @@ -430,6 +430,7 @@ static uint8_t notify_handler(struct bt_conn *conn, return parse_and_send_recv_state(conn, handle, data, length, &recv_state); } } else { + broadcast_assistant.past_avail[index] = false; bap_broadcast_assistant_recv_state_removed(conn, 0, broadcast_assistant.src_ids[index]); } From d5c3323e81c78b561006f650c94a3c0f3de79f77 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Tue, 27 Feb 2024 16:43:25 +0100 Subject: [PATCH 0288/2402] drivers: crypto: stm32: Allow immutable key The passed key does not have to be modifiable. Adapting the signature to reflect this. This allows the following commit to change cipher_ctx::key::bit_stream to be pointing to an immutable key. Signed-off-by: Reto Schneider --- drivers/crypto/crypto_stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/crypto_stm32.c b/drivers/crypto/crypto_stm32.c index 17250a944a9..680792bbb2c 100644 --- a/drivers/crypto/crypto_stm32.c +++ b/drivers/crypto/crypto_stm32.c @@ -56,7 +56,7 @@ LOG_MODULE_REGISTER(crypto_stm32); struct crypto_stm32_session crypto_stm32_sessions[CRYPTO_MAX_SESSION]; static int copy_reverse_words(uint8_t *dst_buf, int dst_len, - uint8_t *src_buf, int src_len) + const uint8_t *src_buf, int src_len) { int i; From 61499a2c7082e875e1c670173f5b9623b80896dc Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Tue, 27 Feb 2024 14:24:26 +0100 Subject: [PATCH 0289/2402] include: crypto: Constify key This change allows to use ROM-ed key. There is no good reason to modify a passed key, ever. Signed-off-by: Reto Schneider --- include/zephyr/crypto/cipher.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/crypto/cipher.h b/include/zephyr/crypto/cipher.h index 752b58ec0aa..71d8e590b41 100644 --- a/include/zephyr/crypto/cipher.h +++ b/include/zephyr/crypto/cipher.h @@ -118,7 +118,7 @@ struct cipher_ctx { /** To be populated by the app before calling begin_session() */ union { /* Cryptographic key to be used in this session */ - uint8_t *bit_stream; + const uint8_t *bit_stream; /* For cases where key is protected and is not * available to caller */ From 1e11bbe1f860f9f1b99d05c2b5b986ef6bbe3934 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Tue, 27 Feb 2024 14:26:17 +0100 Subject: [PATCH 0290/2402] samples: drivers: crypto: Put keys in ROM This change reduces the RAM consumption. Signed-off-by: Reto Schneider --- samples/drivers/crypto/src/main.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/samples/drivers/crypto/src/main.c b/samples/drivers/crypto/src/main.c index 9be044bdf2c..38205ef5df6 100644 --- a/samples/drivers/crypto/src/main.c +++ b/samples/drivers/crypto/src/main.c @@ -33,7 +33,7 @@ LOG_MODULE_REGISTER(main); #error "You need to enable one crypto device" #endif -static uint8_t key[16] __aligned(32) = { +const static uint8_t key[16] __aligned(32) = { 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c }; @@ -111,7 +111,7 @@ int validate_hw_compatibility(const struct device *dev) void ecb_mode(const struct device *dev) { /* from FIPS-197 test vectors */ - uint8_t ecb_key[16] = { + const uint8_t ecb_key[16] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F }; @@ -119,7 +119,7 @@ void ecb_mode(const struct device *dev) 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF }; - const uint8_t ecb_ciphertext[16] = { + uint8_t ecb_ciphertext[16] = { 0x69, 0xC4, 0xE0, 0xD8, 0x6A, 0x7B, 0x04, 0x30, 0xD8, 0xCD, 0xB7, 0x80, 0x70, 0xB4, 0xC5, 0x5A }; @@ -372,7 +372,7 @@ void ctr_mode(const struct device *dev) } /* RFC 3610 test vector #1 */ -static uint8_t ccm_key[16] = { +const static uint8_t ccm_key[16] = { 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf }; @@ -484,7 +484,7 @@ void ccm_mode(const struct device *dev) } /* MACsec GCM-AES test vector 2.4.1 */ -static uint8_t gcm_key[16] = { +const static uint8_t gcm_key[16] = { 0x07, 0x1b, 0x11, 0x3b, 0x0c, 0xa7, 0x43, 0xfe, 0xcc, 0xcf, 0x3d, 0x05, 0x1f, 0x73, 0x73, 0x82 }; From a472133587c00462e405f0bd2dfdf5d342b0a3e4 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Wed, 28 Feb 2024 14:53:35 +0100 Subject: [PATCH 0291/2402] Bluetooth: BAP: Apply missing guards for Kconfig values Some pieces of code were missing proper guards for Kconfig values, which could cause compile issues The massive amount of #if in bap.c clearly indicates that the file should be split, as it contains many things that are specific for various roles. Signed-off-by: Emil Gydesen --- include/zephyr/bluetooth/audio/audio.h | 4 +- subsys/bluetooth/audio/Kconfig.bap | 2 +- subsys/bluetooth/audio/shell/audio.h | 34 +-- subsys/bluetooth/audio/shell/bap.c | 375 +++++++++++++------------ tests/bluetooth/shell/testcase.yaml | 28 ++ 5 files changed, 247 insertions(+), 196 deletions(-) diff --git a/include/zephyr/bluetooth/audio/audio.h b/include/zephyr/bluetooth/audio/audio.h index c8873909297..42742798900 100644 --- a/include/zephyr/bluetooth/audio/audio.h +++ b/include/zephyr/bluetooth/audio/audio.h @@ -655,7 +655,9 @@ enum bt_audio_dir { .phy = _phy, \ .sdu = _sdu, \ .rtn = _rtn, \ - .latency = _latency, \ + IF_ENABLED(UTIL_OR(IS_ENABLED(CONFIG_BT_BAP_BROADCAST_SOURCE), \ + IS_ENABLED(CONFIG_BT_BAP_UNICAST)), \ + (.latency = _latency,)) \ .pd = _pd, \ }) diff --git a/subsys/bluetooth/audio/Kconfig.bap b/subsys/bluetooth/audio/Kconfig.bap index faee41f8ef8..6e5dc3094b7 100644 --- a/subsys/bluetooth/audio/Kconfig.bap +++ b/subsys/bluetooth/audio/Kconfig.bap @@ -170,8 +170,8 @@ config BT_BAP_BROADCAST_SINK select EXPERIMENTAL select BT_ISO_SYNC_RECEIVER select BT_AUDIO_RX + select BT_PAC_SNK depends on BT_PERIPHERAL - depends on BT_PAC_SNK depends on BT_BAP_SCAN_DELEGATOR help This option enables support for Bluetooth Broadcast Sink Audio using diff --git a/subsys/bluetooth/audio/shell/audio.h b/subsys/bluetooth/audio/shell/audio.h index a9406b1b57a..e767bf0949e 100644 --- a/subsys/bluetooth/audio/shell/audio.h +++ b/subsys/bluetooth/audio/shell/audio.h @@ -58,23 +58,6 @@ struct named_lc3_preset { const struct named_lc3_preset *bap_get_named_preset(bool is_unicast, enum bt_audio_dir dir, const char *preset_arg); -#if defined(CONFIG_BT_BAP_UNICAST) - -#define UNICAST_SERVER_STREAM_COUNT \ - COND_CODE_1(CONFIG_BT_ASCS, (CONFIG_BT_ASCS_ASE_SNK_COUNT + CONFIG_BT_ASCS_ASE_SRC_COUNT), \ - (0)) -#define UNICAST_CLIENT_STREAM_COUNT \ - COND_CODE_1(CONFIG_BT_BAP_UNICAST_CLIENT, \ - (CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT + \ - CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SRC_COUNT), \ - (0)) - -#define BAP_UNICAST_AC_MAX_CONN 2U -#define BAP_UNICAST_AC_MAX_SNK (2U * BAP_UNICAST_AC_MAX_CONN) -#define BAP_UNICAST_AC_MAX_SRC (2U * BAP_UNICAST_AC_MAX_CONN) -#define BAP_UNICAST_AC_MAX_PAIR MAX(BAP_UNICAST_AC_MAX_SNK, BAP_UNICAST_AC_MAX_SRC) -#define BAP_UNICAST_AC_MAX_STREAM (BAP_UNICAST_AC_MAX_SNK + BAP_UNICAST_AC_MAX_SRC) - struct shell_stream { struct bt_cap_stream stream; struct bt_audio_codec_cfg codec_cfg; @@ -124,6 +107,23 @@ struct broadcast_sink { bool syncable; }; +#define BAP_UNICAST_AC_MAX_CONN 2U +#define BAP_UNICAST_AC_MAX_SNK (2U * BAP_UNICAST_AC_MAX_CONN) +#define BAP_UNICAST_AC_MAX_SRC (2U * BAP_UNICAST_AC_MAX_CONN) +#define BAP_UNICAST_AC_MAX_PAIR MAX(BAP_UNICAST_AC_MAX_SNK, BAP_UNICAST_AC_MAX_SRC) +#define BAP_UNICAST_AC_MAX_STREAM (BAP_UNICAST_AC_MAX_SNK + BAP_UNICAST_AC_MAX_SRC) + +#if defined(CONFIG_BT_BAP_UNICAST) + +#define UNICAST_SERVER_STREAM_COUNT \ + COND_CODE_1(CONFIG_BT_ASCS, (CONFIG_BT_ASCS_ASE_SNK_COUNT + CONFIG_BT_ASCS_ASE_SRC_COUNT), \ + (0)) +#define UNICAST_CLIENT_STREAM_COUNT \ + COND_CODE_1(CONFIG_BT_BAP_UNICAST_CLIENT, \ + (CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT + \ + CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SRC_COUNT), \ + (0)) + extern struct shell_stream unicast_streams[CONFIG_BT_MAX_CONN * (UNICAST_SERVER_STREAM_COUNT + UNICAST_CLIENT_STREAM_COUNT)]; diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index 8e4c9947755..afbb7f24c6c 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -38,14 +38,15 @@ #include "shell/bt.h" #include "audio.h" +/* Determines if we can initiate streaming */ +#define IS_BAP_INITIATOR \ + (IS_ENABLED(CONFIG_BT_BAP_BROADCAST_SOURCE) || IS_ENABLED(CONFIG_BT_BAP_UNICAST_CLIENT)) + #if defined(CONFIG_BT_BAP_UNICAST) struct shell_stream unicast_streams[CONFIG_BT_MAX_CONN * (UNICAST_SERVER_STREAM_COUNT + UNICAST_CLIENT_STREAM_COUNT)]; -static const struct bt_audio_codec_qos_pref qos_pref = - BT_AUDIO_CODEC_QOS_PREF(true, BT_GAP_LE_PHY_2M, 0u, 60u, 10000u, 60000u, 10000u, 60000u); - #if defined(CONFIG_BT_BAP_UNICAST_CLIENT) struct bt_bap_unicast_group *default_unicast_group; static struct bt_bap_unicast_client_cb unicast_client_cbs; @@ -66,7 +67,20 @@ struct broadcast_source default_source; static struct bt_bap_stream broadcast_sink_streams[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT]; static struct broadcast_sink default_broadcast_sink; #endif /* CONFIG_BT_BAP_BROADCAST_SINK */ + +#if defined(CONFIG_BT_BAP_UNICAST) || defined(CONFIG_BT_BAP_BROADCAST_SOURCE) static struct bt_bap_stream *default_stream; +#endif /* CONFIG_BT_BAP_UNICAST || CONFIG_BT_BAP_BROADCAST_SOURCE */ + +#if IS_BAP_INITIATOR +/* Default to 16_2_1 */ +struct named_lc3_preset default_sink_preset = {"16_2_1", + BT_BAP_LC3_UNICAST_PRESET_16_2_1(LOCATION, CONTEXT)}; +struct named_lc3_preset default_source_preset = { + "16_2_1", BT_BAP_LC3_UNICAST_PRESET_16_2_1(LOCATION, CONTEXT)}; +static struct named_lc3_preset default_broadcast_source_preset = { + "16_2_1", BT_BAP_LC3_BROADCAST_PRESET_16_2_1(LOCATION, CONTEXT)}; +#endif /* IS_BAP_INITIATOR */ static const struct named_lc3_preset lc3_unicast_presets[] = { {"8_1_1", BT_BAP_LC3_UNICAST_PRESET_8_1_1(LOCATION, CONTEXT)}, @@ -140,13 +154,6 @@ static const struct named_lc3_preset lc3_broadcast_presets[] = { {"48_6_2", BT_BAP_LC3_BROADCAST_PRESET_48_6_2(LOCATION, CONTEXT)}, }; -/* Default to 16_2_1 */ -struct named_lc3_preset default_sink_preset = { - "16_2_1", BT_BAP_LC3_UNICAST_PRESET_16_2_1(LOCATION, CONTEXT)}; -struct named_lc3_preset default_source_preset = { - "16_2_1", BT_BAP_LC3_UNICAST_PRESET_16_2_1(LOCATION, CONTEXT)}; -static struct named_lc3_preset default_broadcast_source_preset = { - "16_2_1", BT_BAP_LC3_BROADCAST_PRESET_16_2_1(LOCATION, CONTEXT)}; static bool initialized; static struct shell_stream *shell_stream_from_bap_stream(struct bt_bap_stream *bap_stream) @@ -159,7 +166,6 @@ static struct shell_stream *shell_stream_from_bap_stream(struct bt_bap_stream *b } #if defined(CONFIG_BT_AUDIO_TX) - static uint16_t get_next_seq_num(struct bt_bap_stream *bap_stream) { struct shell_stream *sh_stream = shell_stream_from_bap_stream(bap_stream); @@ -410,6 +416,25 @@ const struct named_lc3_preset *bap_get_named_preset(bool is_unicast, enum bt_aud return NULL; } +#if defined(CONFIG_BT_PACS) +static const struct bt_audio_codec_cap lc3_codec_cap = + BT_AUDIO_CODEC_CAP_LC3(BT_AUDIO_CODEC_CAP_FREQ_ANY, BT_AUDIO_CODEC_CAP_DURATION_ANY, + BT_AUDIO_CODEC_CAP_CHAN_COUNT_SUPPORT(1, 2), 30, 240, 2, CONTEXT); + +#if defined(CONFIG_BT_PAC_SNK) +static struct bt_pacs_cap cap_sink = { + .codec_cap = &lc3_codec_cap, +}; +#endif /* CONFIG_BT_PAC_SNK */ + +#if defined(CONFIG_BT_PAC_SRC) +static struct bt_pacs_cap cap_source = { + .codec_cap = &lc3_codec_cap, +}; +#endif /* CONFIG_BT_PAC_SRC */ +#endif /* CONFIG_BT_PACS */ + +#if defined(CONFIG_BT_BAP_UNICAST) static void set_unicast_stream(struct bt_bap_stream *stream) { default_stream = stream; @@ -447,6 +472,10 @@ static int cmd_select_unicast(const struct shell *sh, size_t argc, char *argv[]) return 0; } +#if defined(CONFIG_BT_BAP_UNICAST_SERVER) +static const struct bt_audio_codec_qos_pref qos_pref = + BT_AUDIO_CODEC_QOS_PREF(true, BT_GAP_LE_PHY_2M, 0u, 60u, 10000u, 60000u, 10000u, 60000u); + static struct bt_bap_stream *stream_alloc(void) { for (size_t i = 0; i < ARRAY_SIZE(unicast_streams); i++) { @@ -577,10 +606,6 @@ static int lc3_release(struct bt_bap_stream *stream, struct bt_bap_ascs_rsp *rsp return 0; } -static const struct bt_audio_codec_cap lc3_codec_cap = BT_AUDIO_CODEC_CAP_LC3( - BT_AUDIO_CODEC_CAP_FREQ_ANY, BT_AUDIO_CODEC_CAP_DURATION_ANY, - BT_AUDIO_CODEC_CAP_CHAN_COUNT_SUPPORT(1, 2), 30, 240, 2, CONTEXT); - static const struct bt_bap_unicast_server_cb unicast_server_cb = { .config = lc3_config, .reconfig = lc3_reconfig, @@ -592,15 +617,7 @@ static const struct bt_bap_unicast_server_cb unicast_server_cb = { .stop = lc3_stop, .release = lc3_release, }; - -static struct bt_pacs_cap cap_sink = { - .codec_cap = &lc3_codec_cap, -}; - -static struct bt_pacs_cap cap_source = { - .codec_cap = &lc3_codec_cap, -}; -#if defined(CONFIG_BT_BAP_UNICAST) +#endif /* CONFIG_BT_BAP_UNICAST_SERVER */ static uint16_t strmeta(const char *name) { @@ -1409,6 +1426,145 @@ static int cmd_stop(const struct shell *sh, size_t argc, char *argv[]) } #endif /* CONFIG_BT_BAP_UNICAST_CLIENT */ +static int cmd_metadata(const struct shell *sh, size_t argc, char *argv[]) +{ + struct bt_audio_codec_cfg *codec_cfg; + int err; + + if (default_stream == NULL) { + shell_error(sh, "No stream selected"); + return -ENOEXEC; + } + + codec_cfg = default_stream->codec_cfg; + + if (argc > 1) { + err = set_metadata(codec_cfg, argv[1]); + if (err != 0) { + shell_error(sh, "Unable to handle metadata update: %d", err); + return err; + } + } + + err = bt_bap_stream_metadata(default_stream, codec_cfg->meta, codec_cfg->meta_len); + if (err) { + shell_error(sh, "Unable to set Channel metadata"); + return -ENOEXEC; + } + + return 0; +} + +static int cmd_start(const struct shell *sh, size_t argc, char *argv[]) +{ + int err; + + if (default_stream == NULL) { + shell_error(sh, "No stream selected"); + return -ENOEXEC; + } + + err = bt_bap_stream_start(default_stream); + if (err) { + shell_error(sh, "Unable to start Channel"); + return -ENOEXEC; + } + + return 0; +} + +static int cmd_disable(const struct shell *sh, size_t argc, char *argv[]) +{ + int err; + + if (default_stream == NULL) { + shell_error(sh, "No stream selected"); + return -ENOEXEC; + } + + err = bt_bap_stream_disable(default_stream); + if (err) { + shell_error(sh, "Unable to disable Channel"); + return -ENOEXEC; + } + + return 0; +} + +#if defined(CONFIG_BT_BAP_UNICAST_CLIENT) +static void conn_list_eps(struct bt_conn *conn, void *data) +{ + const struct shell *sh = (const struct shell *)data; + uint8_t conn_index = bt_conn_index(conn); + + shell_print(sh, "Conn: %p", conn); + shell_print(sh, " Sinks:"); + +#if CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT > 0 + for (size_t i = 0U; i < ARRAY_SIZE(snks[conn_index]); i++) { + const struct bt_bap_ep *ep = snks[conn_index][i]; + + if (ep != NULL) { + shell_print(sh, " #%u: ep %p", i, ep); + } + } +#endif /* CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT > 0 */ + +#if CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SRC_COUNT > 0 + shell_print(sh, " Sources:"); + + for (size_t i = 0U; i < ARRAY_SIZE(srcs[conn_index]); i++) { + const struct bt_bap_ep *ep = srcs[conn_index][i]; + + if (ep != NULL) { + shell_print(sh, " #%u: ep %p", i, ep); + } + } +#endif /* CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SRC_COUNT > 0 */ +} +#endif /* CONFIG_BT_BAP_UNICAST_CLIENT */ + +#if defined(CONFIG_BT_BAP_UNICAST_CLIENT) +static int cmd_list(const struct shell *sh, size_t argc, char *argv[]) +{ + shell_print(sh, "Configured Channels:"); + + for (size_t i = 0U; i < ARRAY_SIZE(unicast_streams); i++) { + struct bt_bap_stream *stream = &unicast_streams[i].stream.bap_stream; + + if (stream != NULL && stream->conn != NULL) { + shell_print(sh, " %s#%u: stream %p dir 0x%02x group %p", + stream == default_stream ? "*" : " ", i, stream, + stream_dir(stream), stream->group); + } + } + + bt_conn_foreach(BT_CONN_TYPE_LE, conn_list_eps, (void *)sh); + + return 0; +} +#endif /* CONFIG_BT_BAP_UNICAST_CLIENT */ + +static int cmd_release(const struct shell *sh, size_t argc, char *argv[]) +{ + int err; + + if (default_stream == NULL) { + shell_print(sh, "No stream selected"); + return -ENOEXEC; + } + + err = bt_bap_stream_release(default_stream); + if (err) { + shell_error(sh, "Unable to release Channel"); + return -ENOEXEC; + } + + return 0; +} +#endif /* CONFIG_BT_BAP_UNICAST */ + +#if IS_BAP_INITIATOR static ssize_t parse_config_data_args(const struct shell *sh, size_t argn, size_t argc, char *argv[], struct bt_audio_codec_cfg *codec_cfg) { @@ -1977,144 +2133,7 @@ static int cmd_preset(const struct shell *sh, size_t argc, char *argv[]) return 0; } - -static int cmd_metadata(const struct shell *sh, size_t argc, char *argv[]) -{ - struct bt_audio_codec_cfg *codec_cfg; - int err; - - if (default_stream == NULL) { - shell_error(sh, "No stream selected"); - return -ENOEXEC; - } - - codec_cfg = default_stream->codec_cfg; - - if (argc > 1) { - err = set_metadata(codec_cfg, argv[1]); - if (err != 0) { - shell_error(sh, "Unable to handle metadata update: %d", err); - return err; - } - } - - err = bt_bap_stream_metadata(default_stream, codec_cfg->meta, codec_cfg->meta_len); - if (err) { - shell_error(sh, "Unable to set Channel metadata"); - return -ENOEXEC; - } - - return 0; -} - -static int cmd_start(const struct shell *sh, size_t argc, char *argv[]) -{ - int err; - - if (default_stream == NULL) { - shell_error(sh, "No stream selected"); - return -ENOEXEC; - } - - err = bt_bap_stream_start(default_stream); - if (err) { - shell_error(sh, "Unable to start Channel"); - return -ENOEXEC; - } - - return 0; -} - -static int cmd_disable(const struct shell *sh, size_t argc, char *argv[]) -{ - int err; - - if (default_stream == NULL) { - shell_error(sh, "No stream selected"); - return -ENOEXEC; - } - - err = bt_bap_stream_disable(default_stream); - if (err) { - shell_error(sh, "Unable to disable Channel"); - return -ENOEXEC; - } - - return 0; -} - -#if defined(CONFIG_BT_BAP_UNICAST_CLIENT) -static void conn_list_eps(struct bt_conn *conn, void *data) -{ - const struct shell *sh = (const struct shell *)data; - uint8_t conn_index = bt_conn_index(conn); - - shell_print(sh, "Conn: %p", conn); - shell_print(sh, " Sinks:"); - -#if CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT > 0 - for (size_t i = 0U; i < ARRAY_SIZE(snks[conn_index]); i++) { - const struct bt_bap_ep *ep = snks[conn_index][i]; - - if (ep != NULL) { - shell_print(sh, " #%u: ep %p", i, ep); - } - } -#endif /* CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT > 0 */ - -#if CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SRC_COUNT > 0 - shell_print(sh, " Sources:"); - - for (size_t i = 0U; i < ARRAY_SIZE(srcs[conn_index]); i++) { - const struct bt_bap_ep *ep = srcs[conn_index][i]; - - if (ep != NULL) { - shell_print(sh, " #%u: ep %p", i, ep); - } - } -#endif /* CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SRC_COUNT > 0 */ -} -#endif /* CONFIG_BT_BAP_UNICAST_CLIENT */ - -#if defined(CONFIG_BT_BAP_UNICAST_CLIENT) -static int cmd_list(const struct shell *sh, size_t argc, char *argv[]) -{ - shell_print(sh, "Configured Channels:"); - - for (size_t i = 0U; i < ARRAY_SIZE(unicast_streams); i++) { - struct bt_bap_stream *stream = &unicast_streams[i].stream.bap_stream; - - if (stream != NULL && stream->conn != NULL) { - shell_print(sh, " %s#%u: stream %p dir 0x%02x group %p", - stream == default_stream ? "*" : " ", i, stream, - stream_dir(stream), stream->group); - } - } - - bt_conn_foreach(BT_CONN_TYPE_LE, conn_list_eps, (void *)sh); - - return 0; -} -#endif /* CONFIG_BT_BAP_UNICAST_CLIENT */ - -static int cmd_release(const struct shell *sh, size_t argc, char *argv[]) -{ - int err; - - if (default_stream == NULL) { - shell_print(sh, "No stream selected"); - return -ENOEXEC; - } - - err = bt_bap_stream_release(default_stream); - if (err) { - shell_error(sh, "Unable to release Channel"); - return -ENOEXEC; - } - - return 0; -} -#endif /* CONFIG_BT_BAP_UNICAST */ +#endif /* IS_BAP_INITIATOR */ #if defined(CONFIG_BT_BAP_BROADCAST_SINK) #define INVALID_BROADCAST_ID (BT_AUDIO_BROADCAST_ID_MAX + 1) @@ -2344,6 +2363,7 @@ static void audio_recv(struct bt_bap_stream *stream, } #endif /* CONFIG_BT_AUDIO_RX */ +#if defined(CONFIG_BT_BAP_UNICAST) static void stream_enabled_cb(struct bt_bap_stream *stream) { shell_print(ctx_shell, "Stream %p enabled", stream); @@ -2380,6 +2400,7 @@ static void stream_enabled_cb(struct bt_bap_stream *stream) } } } +#endif /* CONFIG_BT_BAP_UNICAST */ static void stream_started_cb(struct bt_bap_stream *bap_stream) { @@ -2408,9 +2429,9 @@ static void stream_stopped_cb(struct bt_bap_stream *stream, uint8_t reason) { printk("Stream %p stopped with reason 0x%02X\n", stream, reason); -#if defined(CONFIG_LIBLC3) +#if defined(CONFIG_LIBLC3) && defined(CONFIG_BT_AUDIO_TX) clear_lc3_sine_data(stream); -#endif /* CONFIG_LIBLC3 */ +#endif /* CONFIG_LIBLC3 && CONFIG_BT_AUDIO_TX*/ #if defined(CONFIG_BT_BAP_BROADCAST_SINK) if (IS_ARRAY_ELEMENT(broadcast_sink_streams, stream)) { @@ -2538,10 +2559,10 @@ static void stream_released_cb(struct bt_bap_stream *stream) } #endif /* CONFIG_BT_BAP_UNICAST_CLIENT */ -#if defined(CONFIG_LIBLC3) +#if defined(CONFIG_LIBLC3) && defined(CONFIG_BT_AUDIO_TX) /* stop sending */ clear_lc3_sine_data(stream); -#endif /* CONFIG_LIBLC3 */ +#endif /* CONFIG_LIBLC3 && defined(CONFIG_BT_AUDIO_TX) */ } #endif /* CONFIG_BT_BAP_UNICAST */ @@ -3040,18 +3061,16 @@ static int cmd_init(const struct shell *sh, size_t argc, char *argv[]) return -ENOEXEC; } - if (IS_ENABLED(CONFIG_BT_BAP_UNICAST_SERVER)) { - bt_bap_unicast_server_register_cb(&unicast_server_cb); - } - - if (IS_ENABLED(CONFIG_BT_BAP_UNICAST_SERVER) || - IS_ENABLED(CONFIG_BT_BAP_BROADCAST_SINK)) { - bt_pacs_cap_register(BT_AUDIO_DIR_SINK, &cap_sink); - } +#if defined(CONFIG_BT_BAP_UNICAST_SERVER) + bt_bap_unicast_server_register_cb(&unicast_server_cb); +#endif /* CONFIG_BT_BAP_UNICAST_SERVER */ - if (IS_ENABLED(CONFIG_BT_BAP_UNICAST_SERVER)) { - bt_pacs_cap_register(BT_AUDIO_DIR_SOURCE, &cap_source); - } +#if defined(CONFIG_BT_PAC_SNK) + bt_pacs_cap_register(BT_AUDIO_DIR_SINK, &cap_sink); +#endif /* CONFIG_BT_PAC_SNK */ +#if defined(CONFIG_BT_PAC_SRC) + bt_pacs_cap_register(BT_AUDIO_DIR_SOURCE, &cap_source); +#endif /* CONFIG_BT_PAC_SNK */ if (IS_ENABLED(CONFIG_BT_PAC_SNK_LOC)) { err = bt_pacs_set_location(BT_AUDIO_DIR_SINK, LOCATION); @@ -3486,9 +3505,11 @@ SHELL_STATIC_SUBCMD_SET_CREATE( SHELL_CMD_ARG(release, NULL, NULL, cmd_release, 1, 0), SHELL_CMD_ARG(select_unicast, NULL, "", cmd_select_unicast, 2, 0), #endif /* CONFIG_BT_BAP_UNICAST */ +#if IS_BAP_INITIATOR SHELL_CMD_ARG(preset, NULL, " [preset] " HELP_CFG_DATA " " HELP_CFG_META, cmd_preset, 2, 34), +#endif /* IS_BAP_INITIATOR */ #if defined(CONFIG_BT_AUDIO_TX) SHELL_CMD_ARG(send, NULL, "Send to Audio Stream [data]", cmd_send, 1, 1), #if defined(CONFIG_LIBLC3) diff --git a/tests/bluetooth/shell/testcase.yaml b/tests/bluetooth/shell/testcase.yaml index b561844db6e..5afef25d98a 100644 --- a/tests/bluetooth/shell/testcase.yaml +++ b/tests/bluetooth/shell/testcase.yaml @@ -204,6 +204,34 @@ tests: build_only: true extra_configs: - CONFIG_BT_PAC_SRC=n + bluetooth.audio_shell.only_unicast_client: + extra_args: CONF_FILE="audio.conf" + build_only: true + extra_configs: + - CONFIG_BT_BAP_UNICAST_SERVER=n + - CONFIG_BT_BAP_BROADCAST_SINK=n + - CONFIG_BT_BAP_BROADCAST_SOURCE=n + bluetooth.audio_shell.only_unicast_server: + extra_args: CONF_FILE="audio.conf" + build_only: true + extra_configs: + - CONFIG_BT_BAP_UNICAST_CLIENT=n + - CONFIG_BT_BAP_BROADCAST_SINK=n + - CONFIG_BT_BAP_BROADCAST_SOURCE=n + bluetooth.audio_shell.only_broadcast_source: + extra_args: CONF_FILE="audio.conf" + build_only: true + extra_configs: + - CONFIG_BT_BAP_UNICAST_SERVER=n + - CONFIG_BT_BAP_UNICAST_CLIENT=n + - CONFIG_BT_BAP_BROADCAST_SINK=n + bluetooth.audio_shell.only_broadcast_sink: + extra_args: CONF_FILE="audio.conf" + build_only: true + extra_configs: + - CONFIG_BT_BAP_UNICAST_SERVER=n + - CONFIG_BT_BAP_UNICAST_CLIENT=n + - CONFIG_BT_BAP_BROADCAST_SOURCE=n bluetooth.audio_shell.no_unicast_client: extra_args: CONF_FILE="audio.conf" build_only: true From 9ce9d577323aedcae4bc1cd88e0cd4a14648d1c6 Mon Sep 17 00:00:00 2001 From: Troels Nilsson Date: Thu, 29 Feb 2024 12:41:11 +0100 Subject: [PATCH 0292/2402] Bluetooth: Controller: Fix per adv interval value check Invalid values should result in BT_HCI_ERR_INVALID_PARAM The interval check should only fail with BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL if the requested range cannot be fulfilled by the controller (ie. there is no overlap with the supported range) Fixes EBQ tests HCI/DDI/BI-53-C through HCI/DDI/BI-61-C and HCI/CCO/BI-64-C Signed-off-by: Troels Nilsson --- subsys/bluetooth/controller/hci/hci.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/subsys/bluetooth/controller/hci/hci.c b/subsys/bluetooth/controller/hci/hci.c index f2c01a3cbb3..dbe64a50681 100644 --- a/subsys/bluetooth/controller/hci/hci.c +++ b/subsys/bluetooth/controller/hci/hci.c @@ -3652,17 +3652,25 @@ static void le_set_per_adv_param(struct net_buf *buf, struct net_buf **evt) const uint32_t min_interval = sys_le16_to_cpu(cmd->min_interval); - /* Compare periodic advertising interval maximum with + if ((min_interval > max_interval) || + (min_interval < BT_HCI_LE_PER_ADV_INTERVAL_MIN)) { + *evt = cmd_complete_status(BT_HCI_ERR_INVALID_PARAM); + return; + } + + /* Compare periodic advertising interval with * implementation supported periodic advertising interval * maximum value defined in the Kconfig * CONFIG_BT_CTLR_ADV_PERIODIC_INTERVAL_MAX. */ - if ((min_interval > max_interval) || - (min_interval < BT_HCI_LE_PER_ADV_INTERVAL_MIN) || - (max_interval > CONFIG_BT_CTLR_ADV_PERIODIC_INTERVAL_MAX)) { + if (min_interval > CONFIG_BT_CTLR_ADV_PERIODIC_INTERVAL_MAX) { *evt = cmd_complete_status(BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL); return; } + + if (max_interval > CONFIG_BT_CTLR_ADV_PERIODIC_INTERVAL_MAX) { + max_interval = CONFIG_BT_CTLR_ADV_PERIODIC_INTERVAL_MAX; + } } status = ll_adv_set_by_hci_handle_get(cmd->handle, &handle); From b764cf0b07aca170414cba55759f9fddeae1bfc3 Mon Sep 17 00:00:00 2001 From: Aleksandr Khromykh Date: Tue, 27 Feb 2024 15:40:14 +0100 Subject: [PATCH 0293/2402] Bluetooth: Mesh: fixed health srv metadata id Assigned Numbers document 4.3.6 Mesh Metadata Identifiers 0x0000 - Health Tests Information Signed-off-by: Aleksandr Khromykh --- include/zephyr/bluetooth/mesh/health_srv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/bluetooth/mesh/health_srv.h b/include/zephyr/bluetooth/mesh/health_srv.h index 3eef7e459f7..90bdb4c81a4 100644 --- a/include/zephyr/bluetooth/mesh/health_srv.h +++ b/include/zephyr/bluetooth/mesh/health_srv.h @@ -188,7 +188,7 @@ struct bt_mesh_health_srv { * * Health Test Information Metadata ID. */ -#define BT_MESH_HEALTH_TEST_INFO_METADATA_ID 0x0001 +#define BT_MESH_HEALTH_TEST_INFO_METADATA_ID 0x0000 #define BT_MESH_HEALTH_TEST_INFO_METADATA(tests) \ { \ From a96293b093eaae820a7df16009ebb1eb113f7ed7 Mon Sep 17 00:00:00 2001 From: Aleksandr Khromykh Date: Thu, 29 Feb 2024 16:24:16 +0100 Subject: [PATCH 0294/2402] doc: Bluetooth: Mesh: add missed lcd shell commands Commit adds description of the Large Composition Data client's shell commands into documentation. Signed-off-by: Aleksandr Khromykh --- doc/connectivity/bluetooth/api/mesh/shell.rst | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/doc/connectivity/bluetooth/api/mesh/shell.rst b/doc/connectivity/bluetooth/api/mesh/shell.rst index c4fef19c6e6..707f2c8a8ab 100644 --- a/doc/connectivity/bluetooth/api/mesh/shell.rst +++ b/doc/connectivity/bluetooth/api/mesh/shell.rst @@ -1763,6 +1763,31 @@ Provisioning Servers on devices in a mesh network. Get a list of all Remote Provisioning Client model instances on the node. +Large Composition Data Client +----------------------------- + +The Large Composition Data Client is an optional Bluetooth Mesh model enabled through the +:kconfig:option:`CONFIG_BT_MESH_LARGE_COMP_DATA_CLI` configuration option. The Large Composition Data Client +model is used to support the functionality of reading pages of Composition Data that do not fit in +a Config Composition Data Status message, and reading the metadata of the model instances. + +``mesh models lcd large-comp-data-get `` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Send the Large Composition Data Get message to query a portion of the Composition Data state of a node. + + * ``Page``: Page number of the Composition Data. + * ``Offset``: Offset within the page. + +``mesh models lcd models-metadata-get `` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Send the Models Metadata Get message to query a portion of a page of the Models Metadata state. + + * ``Page``: Page number of the Models Metadata. + * ``Offset``: Offset within the page. + + Configuration database ====================== From 3605d57ae11ef22aff91acbd69bca2648dd8f0d0 Mon Sep 17 00:00:00 2001 From: Chang An Date: Mon, 4 Mar 2024 14:02:33 +0800 Subject: [PATCH 0295/2402] LE Audio: bt_bap_broadcast_sink_cb.syncable should provide the BIGInfo Modify bt_bap_broadcast_sink_cb.syncable to provide the BIGInfo instead of just the encryption field. Signed-off-by: Chang An --- include/zephyr/bluetooth/audio/bap.h | 4 ++-- samples/bluetooth/broadcast_audio_sink/src/main.c | 4 ++-- samples/bluetooth/public_broadcast_sink/src/main.c | 2 +- samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c | 2 +- subsys/bluetooth/audio/bap_broadcast_sink.c | 2 +- subsys/bluetooth/audio/shell/bap.c | 4 ++-- tests/bluetooth/tester/src/btp_bap_broadcast.c | 6 +++--- tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c | 4 ++-- tests/bsim/bluetooth/audio/src/cap_acceptor_test.c | 4 ++-- .../bluetooth/audio/src/pbp_public_broadcast_sink_test.c | 2 +- 10 files changed, 17 insertions(+), 17 deletions(-) diff --git a/include/zephyr/bluetooth/audio/bap.h b/include/zephyr/bluetooth/audio/bap.h index 022bc53b3ba..86f55ecf0d0 100644 --- a/include/zephyr/bluetooth/audio/bap.h +++ b/include/zephyr/bluetooth/audio/bap.h @@ -1814,9 +1814,9 @@ struct bt_bap_broadcast_sink_cb { * bt_bap_broadcast_sink_sync() to synchronize to the audio stream(s). * * @param sink Pointer to the sink structure. - * @param encrypted Whether or not the broadcast is encrypted + * @param biginfo The BIGInfo report. */ - void (*syncable)(struct bt_bap_broadcast_sink *sink, bool encrypted); + void (*syncable)(struct bt_bap_broadcast_sink *sink, const struct bt_iso_biginfo *biginfo); /* Internally used list node */ sys_snode_t _node; diff --git a/samples/bluetooth/broadcast_audio_sink/src/main.c b/samples/bluetooth/broadcast_audio_sink/src/main.c index 3485a275049..59f7c6d398c 100644 --- a/samples/bluetooth/broadcast_audio_sink/src/main.c +++ b/samples/bluetooth/broadcast_audio_sink/src/main.c @@ -543,11 +543,11 @@ static void base_recv_cb(struct bt_bap_broadcast_sink *sink, const struct bt_bap k_sem_give(&sem_base_received); } -static void syncable_cb(struct bt_bap_broadcast_sink *sink, bool encrypted) +static void syncable_cb(struct bt_bap_broadcast_sink *sink, const struct bt_iso_biginfo *biginfo) { k_sem_give(&sem_syncable); - if (!encrypted) { + if (!biginfo->encryption) { /* Use the semaphore as a boolean */ k_sem_reset(&sem_broadcast_code_received); k_sem_give(&sem_broadcast_code_received); diff --git a/samples/bluetooth/public_broadcast_sink/src/main.c b/samples/bluetooth/public_broadcast_sink/src/main.c index 4d29b5da50b..686ee087a73 100644 --- a/samples/bluetooth/public_broadcast_sink/src/main.c +++ b/samples/bluetooth/public_broadcast_sink/src/main.c @@ -258,7 +258,7 @@ static void broadcast_pa_recv(struct bt_le_per_adv_sync *sync, bt_data_parse(buf, pa_decode_base, NULL); } -static void syncable_cb(struct bt_bap_broadcast_sink *sink, bool encrypted) +static void syncable_cb(struct bt_bap_broadcast_sink *sink, const struct bt_iso_biginfo *biginfo) { k_sem_give(&sem_syncable); } diff --git a/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c b/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c index 67ca7e658ed..fe82040d45a 100644 --- a/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c +++ b/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c @@ -242,7 +242,7 @@ static void broadcast_pa_recv(struct bt_le_per_adv_sync *sync, bt_data_parse(buf, pa_decode_base, NULL); } -static void syncable_cb(struct bt_bap_broadcast_sink *sink, bool encrypted) +static void syncable_cb(struct bt_bap_broadcast_sink *sink, const struct bt_iso_biginfo *biginfo) { k_sem_give(&sem_syncable); } diff --git a/subsys/bluetooth/audio/bap_broadcast_sink.c b/subsys/bluetooth/audio/bap_broadcast_sink.c index bc444876bdd..cdcd7fb477b 100644 --- a/subsys/bluetooth/audio/bap_broadcast_sink.c +++ b/subsys/bluetooth/audio/bap_broadcast_sink.c @@ -900,7 +900,7 @@ static void biginfo_recv(struct bt_le_per_adv_sync *sync, SYS_SLIST_FOR_EACH_CONTAINER(&sink_cbs, listener, _node) { if (listener->syncable != NULL) { - listener->syncable(sink, biginfo->encryption); + listener->syncable(sink, biginfo); } } } diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index afbb7f24c6c..8c9b35330ff 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -2251,7 +2251,7 @@ static void base_recv(struct bt_bap_broadcast_sink *sink, const struct bt_bap_ba } } -static void syncable(struct bt_bap_broadcast_sink *sink, bool encrypted) +static void syncable(struct bt_bap_broadcast_sink *sink, const struct bt_iso_biginfo *biginfo) { if (default_broadcast_sink.bap_sink == sink) { if (default_broadcast_sink.syncable) { @@ -2259,7 +2259,7 @@ static void syncable(struct bt_bap_broadcast_sink *sink, bool encrypted) } shell_print(ctx_shell, "Sink %p is ready to sync %s encryption", sink, - encrypted ? "with" : "without"); + biginfo->encryption ? "with" : "without"); default_broadcast_sink.syncable = true; } } diff --git a/tests/bluetooth/tester/src/btp_bap_broadcast.c b/tests/bluetooth/tester/src/btp_bap_broadcast.c index e855d3b7615..dba69d2a449 100644 --- a/tests/bluetooth/tester/src/btp_bap_broadcast.c +++ b/tests/bluetooth/tester/src/btp_bap_broadcast.c @@ -680,7 +680,7 @@ static void base_recv_cb(struct bt_bap_broadcast_sink *sink, const struct bt_bap LOG_DBG("bis_index_bitfield 0x%08x", broadcaster->bis_index_bitfield); } -static void syncable_cb(struct bt_bap_broadcast_sink *sink, bool encrypted) +static void syncable_cb(struct bt_bap_broadcast_sink *sink, const struct bt_iso_biginfo *biginfo) { int err; uint32_t index_bitfield; @@ -692,10 +692,10 @@ static void syncable_cb(struct bt_bap_broadcast_sink *sink, bool encrypted) return; } - LOG_DBG("Broadcaster PA found, encrypted %d, requested_bis_sync %d", encrypted, + LOG_DBG("Broadcaster PA found, encrypted %d, requested_bis_sync %d", biginfo->encryption, broadcaster->requested_bis_sync); - if (encrypted) { + if (biginfo->encryption) { /* Wait for Set Broadcast Code and start sync at broadcast_code_cb */ return; } diff --git a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c index 03c2073746b..b8e374c08f5 100644 --- a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c +++ b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c @@ -238,10 +238,10 @@ static void base_recv_cb(struct bt_bap_broadcast_sink *sink, const struct bt_bap SET_FLAG(flag_base_received); } -static void syncable_cb(struct bt_bap_broadcast_sink *sink, bool encrypted) +static void syncable_cb(struct bt_bap_broadcast_sink *sink, const struct bt_iso_biginfo *biginfo) { printk("Broadcast sink %p syncable with%s encryption\n", - sink, encrypted ? "" : "out"); + sink, biginfo->encryption ? "" : "out"); SET_FLAG(flag_syncable); } diff --git a/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c b/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c index 3534ff02219..6c110522809 100644 --- a/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c +++ b/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c @@ -150,10 +150,10 @@ static void base_recv_cb(struct bt_bap_broadcast_sink *sink, const struct bt_bap SET_FLAG(flag_base_received); } -static void syncable_cb(struct bt_bap_broadcast_sink *sink, bool encrypted) +static void syncable_cb(struct bt_bap_broadcast_sink *sink, const struct bt_iso_biginfo *biginfo) { printk("Broadcast sink %p syncable with%s encryption\n", - sink, encrypted ? "" : "out"); + sink, biginfo->encryption ? "" : "out"); SET_FLAG(flag_syncable); } diff --git a/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c b/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c index d793d8fd7f3..65178c2550a 100644 --- a/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c +++ b/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c @@ -69,7 +69,7 @@ static void base_recv_cb(struct bt_bap_broadcast_sink *sink, const struct bt_bap k_sem_give(&sem_base_received); } -static void syncable_cb(struct bt_bap_broadcast_sink *sink, bool encrypted) +static void syncable_cb(struct bt_bap_broadcast_sink *sink, const struct bt_iso_biginfo *biginfo) { k_sem_give(&sem_syncable); } From 9eadfef4cfbcf2810e80c7155d7f52b9d7b69ad5 Mon Sep 17 00:00:00 2001 From: Anisetti Avinash Krishna Date: Tue, 5 Mar 2024 15:37:40 +0530 Subject: [PATCH 0296/2402] tests: drivers: gpio: gpio_basic_api: boards: Enabled test for rpl_s Enable gpio_basic_api test for intel_rpl_s_crb platform Signed-off-by: Anisetti Avinash Krishna --- .../gpio_basic_api/boards/intel_rpl_s_crb.overlay | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_s_crb.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_s_crb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_s_crb.overlay new file mode 100644 index 00000000000..b7cacf75cb2 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_s_crb.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +/ { + resources { + compatible = "test-gpio-basic-api"; + + out-gpios = <&gpio_0_i 16 0>; + in-gpios = <&gpio_0_i 17 0>; + }; +}; From f39106cdf71f8d568ede4c56bb6e600a47a1d2fa Mon Sep 17 00:00:00 2001 From: Anisetti Avinash Krishna Date: Tue, 5 Mar 2024 15:45:19 +0530 Subject: [PATCH 0297/2402] boards: intel: rpl: Updated rpl_s yaml with gpio Updated intel_rpl_s_crb yaml file with GPIO to enable GPIO testing. Signed-off-by: Anisetti Avinash Krishna --- boards/intel/rpl/intel_rpl_s_crb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/intel/rpl/intel_rpl_s_crb.yaml b/boards/intel/rpl/intel_rpl_s_crb.yaml index ef51e444e58..d7ee6b71ba2 100644 --- a/boards/intel/rpl/intel_rpl_s_crb.yaml +++ b/boards/intel/rpl/intel_rpl_s_crb.yaml @@ -12,6 +12,7 @@ supported: - watchdog - rtc - pwm + - gpio testing: ignore_tags: - net From f9f44b6dcdd4b80765df8922e8d12fdb9213e13a Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Thu, 7 Mar 2024 07:29:51 +0100 Subject: [PATCH 0298/2402] doc: arch: fix typo in arm_cortex_m.rst fix typo in arm_cortex_m.rst Signed-off-by: Florian La Roche --- doc/hardware/arch/arm_cortex_m.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/hardware/arch/arm_cortex_m.rst b/doc/hardware/arch/arm_cortex_m.rst index 1c074618567..eac559d238d 100644 --- a/doc/hardware/arch/arm_cortex_m.rst +++ b/doc/hardware/arch/arm_cortex_m.rst @@ -99,7 +99,7 @@ Thread stack alignment Each Zephyr thread is defined with its own stack memory. By default, Cortex-M enforces a double word thread stack alignment, see :kconfig:option:`CONFIG_STACK_ALIGN_DOUBLE_WORD`. If MPU-based HW-assisted stack overflow detection (:kconfig:option:`CONFIG_MPU_STACK_GUARD`) is enabled, thread stacks need to be aligned with a larger value, reflected by :kconfig:option:`CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE`. -In Arm v6-M and Arm v7-M architecture variants, thread stacks are additionally required to be align with a value equal to their size, +In Arm v6-M and Arm v7-M architecture variants, thread stacks are additionally required to align with a value equal to their size, in applications that need to support user mode (:kconfig:option:`CONFIG_USERSPACE`). The thread stack sizes in that case need to be a power of two. This is all reflected by :kconfig:option:`CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT`, that is enforced in Arm v6-M and Arm v7-M builds with user mode support. From 99707246527ab2df9212a29f01fbef87c6cce44c Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Wed, 6 Mar 2024 18:41:28 -0500 Subject: [PATCH 0299/2402] ci: twister: increase matrix size for push jobs Increase matrix size to 20 from 15 on push events. Signed-off-by: Anas Nashif --- .github/workflows/twister.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index 298ccc9de92..c77bfd4bf53 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -33,7 +33,7 @@ jobs: fullrun: ${{ steps.output-services.outputs.fullrun }} env: MATRIX_SIZE: 10 - PUSH_MATRIX_SIZE: 15 + PUSH_MATRIX_SIZE: 20 DAILY_MATRIX_SIZE: 80 BSIM_OUT_PATH: /opt/bsim/ BSIM_COMPONENTS_PATH: /opt/bsim/components From 66b8a158993b5f247d56fdeac830d58de4e9fc80 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 15:17:58 +0100 Subject: [PATCH 0300/2402] drivers: mbox: andes_plic_sw: add missing include Driver used spinlocks without including the necessary headers. Signed-off-by: Gerard Marull-Paretas --- drivers/mbox/mbox_andes_plic_sw.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mbox/mbox_andes_plic_sw.c b/drivers/mbox/mbox_andes_plic_sw.c index e2c287ae216..379ba9b627d 100644 --- a/drivers/mbox/mbox_andes_plic_sw.c +++ b/drivers/mbox/mbox_andes_plic_sw.c @@ -9,6 +9,7 @@ #define LOG_LEVEL CONFIG_MBOX_LOG_LEVEL #include #include +#include LOG_MODULE_REGISTER(mbox_andes_plic_sw); #define DT_DRV_COMPAT andestech_plic_sw From 79490b9dc1895ed0d07b3c7f59d1d1d11a16df4f Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 11:48:33 +0100 Subject: [PATCH 0301/2402] drivers: mbox: nxp_imx_mu: add missing include Was causing build failures with IRQ_CONNECT missing. Signed-off-by: Gerard Marull-Paretas --- drivers/mbox/mbox_nxp_imx_mu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mbox/mbox_nxp_imx_mu.c b/drivers/mbox/mbox_nxp_imx_mu.c index 664a88e2065..1755c93f869 100644 --- a/drivers/mbox/mbox_nxp_imx_mu.c +++ b/drivers/mbox/mbox_nxp_imx_mu.c @@ -8,6 +8,7 @@ #include #include +#include #include #include From e43ffcb5cdd49e3c70041397de401225440004ef Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 15:21:58 +0100 Subject: [PATCH 0302/2402] drivers: mbox: nxp_mailbox: add missing include Add irq.h for IRQ_CONNECT. Signed-off-by: Gerard Marull-Paretas --- drivers/mbox/mbox_nxp_mailbox.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mbox/mbox_nxp_mailbox.c b/drivers/mbox/mbox_nxp_mailbox.c index 7c2818f0ffe..cfd0640cddc 100644 --- a/drivers/mbox/mbox_nxp_mailbox.c +++ b/drivers/mbox/mbox_nxp_mailbox.c @@ -8,6 +8,7 @@ #include #include +#include #include #include From c467db26fc989a114895d3c95242273b87be9fd5 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 10:51:21 +0100 Subject: [PATCH 0303/2402] drivers: mbox: fix includes Include what is needed. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/drivers/mbox.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/zephyr/drivers/mbox.h b/include/zephyr/drivers/mbox.h index daa0e77056c..07924587e9c 100644 --- a/include/zephyr/drivers/mbox.h +++ b/include/zephyr/drivers/mbox.h @@ -66,9 +66,12 @@ * */ -#include +#include +#include +#include + #include -#include +#include #ifdef __cplusplus extern "C" { From 2380e5fdaf4fb370d8ae9af88ef7e016c8e08bad Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 11:24:29 +0100 Subject: [PATCH 0304/2402] dts: bindings: test: add vnd,mbox-consumer Add a new binding that should help with samples or MBOX tests by getting information from DT. Signed-off-by: Gerard Marull-Paretas --- dts/bindings/test/vnd,mbox-consumer.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 dts/bindings/test/vnd,mbox-consumer.yaml diff --git a/dts/bindings/test/vnd,mbox-consumer.yaml b/dts/bindings/test/vnd,mbox-consumer.yaml new file mode 100644 index 00000000000..84dd076c5c4 --- /dev/null +++ b/dts/bindings/test/vnd,mbox-consumer.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2021, Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +description: VND MBOX consumer + +compatible: "vnd,mbox-consumer" + +include: base.yaml + +properties: + mboxes: + required: true + + mbox-names: + required: true From ab8574a791694d61c18ad8d870e60f41808f4e13 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 11:25:41 +0100 Subject: [PATCH 0305/2402] samples: drivers: mbox: use DT Instead of hardcoding stuff in the sample (mbox node label and channel ids). Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/Kconfig | 14 ------ .../mbox/boards/adp_xc7k_ae350.overlay | 6 +++ .../lpcxpresso55s69_lpc55s69_cpu0.overlay | 6 +++ .../mbox/boards/mimxrt1160_evk_cm7.conf | 3 -- .../mbox/boards/mimxrt1160_evk_cm7.overlay | 29 ----------- .../mimxrt1160_evk_mimxrt1166_cm7.overlay | 6 +++ .../mimxrt1170_evk_mimxrt1176_cm7_A.overlay | 6 +++ .../mimxrt1170_evk_mimxrt1176_cm7_B.overlay | 6 +++ .../mbox/boards/mimxrt1170_evkb_cm7.conf | 3 -- .../boards/nrf5340bsim_nrf5340_cpuapp.overlay | 12 +++++ .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 12 +++++ ...54h20pdk_nrf54h20_cpuapp_bellboard.overlay | 10 +++- .../nrf54h20pdk_nrf54h20_cpuapp_vevif.conf | 1 - .../nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay | 10 +++- samples/drivers/mbox/remote/Kconfig | 14 ------ .../mbox/remote/boards/adp_xc7k_ae350.overlay | 13 +++++ .../lpcxpresso55s69_lpc55s69_cpu1.overlay | 6 +++ .../remote/boards/mimxrt1160_evk_cm4.conf | 4 -- .../remote/boards/mimxrt1160_evk_cm4.overlay | 48 ------------------ .../mimxrt1160_evk_mimxrt1166_cm4.overlay | 6 +++ .../remote/boards/mimxrt1170_evk_cm4.conf | 4 -- .../remote/boards/mimxrt1170_evk_cm4.overlay | 48 ------------------ .../mimxrt1170_evk_mimxrt1176_cm4.overlay | 6 +++ .../mimxrt1170_evk_mimxrt1176_cm4_B.overlay | 6 +++ .../remote/boards/mimxrt1170_evkb_cm4.conf | 4 -- .../remote/boards/mimxrt1170_evkb_cm4.overlay | 49 ------------------- .../boards/nrf5340bsim_nrf5340_cpunet.overlay | 12 +++++ .../boards/nrf5340dk_nrf5340_cpunet.overlay | 12 +++++ ...54h20pdk_nrf54h20_cpuppr_bellboard.overlay | 10 +++- .../nrf54h20pdk_nrf54h20_cpuppr_vevif.conf | 1 - .../nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay | 10 +++- samples/drivers/mbox/remote/src/main.c | 4 +- samples/drivers/mbox/src/main.c | 6 +-- 33 files changed, 156 insertions(+), 231 deletions(-) delete mode 100644 samples/drivers/mbox/boards/mimxrt1160_evk_cm7.conf delete mode 100644 samples/drivers/mbox/boards/mimxrt1160_evk_cm7.overlay delete mode 100644 samples/drivers/mbox/boards/mimxrt1170_evkb_cm7.conf create mode 100644 samples/drivers/mbox/boards/nrf5340bsim_nrf5340_cpuapp.overlay create mode 100644 samples/drivers/mbox/boards/nrf5340dk_nrf5340_cpuapp.overlay create mode 100644 samples/drivers/mbox/remote/boards/adp_xc7k_ae350.overlay delete mode 100644 samples/drivers/mbox/remote/boards/mimxrt1160_evk_cm4.conf delete mode 100644 samples/drivers/mbox/remote/boards/mimxrt1160_evk_cm4.overlay delete mode 100644 samples/drivers/mbox/remote/boards/mimxrt1170_evk_cm4.conf delete mode 100644 samples/drivers/mbox/remote/boards/mimxrt1170_evk_cm4.overlay delete mode 100644 samples/drivers/mbox/remote/boards/mimxrt1170_evkb_cm4.conf delete mode 100644 samples/drivers/mbox/remote/boards/mimxrt1170_evkb_cm4.overlay create mode 100644 samples/drivers/mbox/remote/boards/nrf5340bsim_nrf5340_cpunet.overlay create mode 100644 samples/drivers/mbox/remote/boards/nrf5340dk_nrf5340_cpunet.overlay diff --git a/samples/drivers/mbox/Kconfig b/samples/drivers/mbox/Kconfig index 3af6e740bfc..afff425e648 100644 --- a/samples/drivers/mbox/Kconfig +++ b/samples/drivers/mbox/Kconfig @@ -16,22 +16,8 @@ config TX_ENABLED help Enable TX -config TX_CHANNEL_ID - int "Channel ID for TX" - default 1 - depends on TX_ENABLED - help - Channel ID for TX - config RX_ENABLED bool "RX enabled" default y help Enable RX - -config RX_CHANNEL_ID - int "Channel ID for RX" - depends on RX_ENABLED - default 0 - help - Channel ID for RX diff --git a/samples/drivers/mbox/boards/adp_xc7k_ae350.overlay b/samples/drivers/mbox/boards/adp_xc7k_ae350.overlay index e9750141670..b79fd18246d 100644 --- a/samples/drivers/mbox/boards/adp_xc7k_ae350.overlay +++ b/samples/drivers/mbox/boards/adp_xc7k_ae350.overlay @@ -16,4 +16,10 @@ compatible = "mmio-sram"; reg = <0x00000000 0x10000000 >; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 1>, <&mbox 0>; + mbox-names = "tx", "rx"; + }; }; diff --git a/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay index b5919c4fd72..4ee8379dc9e 100644 --- a/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay +++ b/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay @@ -26,4 +26,10 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 1>, <&mbox 0>; + mbox-names = "tx", "rx"; + }; }; diff --git a/samples/drivers/mbox/boards/mimxrt1160_evk_cm7.conf b/samples/drivers/mbox/boards/mimxrt1160_evk_cm7.conf deleted file mode 100644 index 583b4950360..00000000000 --- a/samples/drivers/mbox/boards/mimxrt1160_evk_cm7.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_INCLUDE_REMOTE_DIR=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox/boards/mimxrt1160_evk_cm7.overlay b/samples/drivers/mbox/boards/mimxrt1160_evk_cm7.overlay deleted file mode 100644 index 942f67ba6a9..00000000000 --- a/samples/drivers/mbox/boards/mimxrt1160_evk_cm7.overlay +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c48000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c48000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c48000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; -}; diff --git a/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay index 942f67ba6a9..254741183ee 100644 --- a/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay +++ b/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -26,4 +26,10 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 1>, <&mbox 0>; + mbox-names = "tx", "rx"; + }; }; diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay index 942f67ba6a9..254741183ee 100644 --- a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay +++ b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -26,4 +26,10 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 1>, <&mbox 0>; + mbox-names = "tx", "rx"; + }; }; diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay index 942f67ba6a9..254741183ee 100644 --- a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay +++ b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -26,4 +26,10 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 1>, <&mbox 0>; + mbox-names = "tx", "rx"; + }; }; diff --git a/samples/drivers/mbox/boards/mimxrt1170_evkb_cm7.conf b/samples/drivers/mbox/boards/mimxrt1170_evkb_cm7.conf deleted file mode 100644 index 0dfb100ed70..00000000000 --- a/samples/drivers/mbox/boards/mimxrt1170_evkb_cm7.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_SECOND_CORE_MCUX=y -CONFIG_INCLUDE_REMOTE_DIR=y diff --git a/samples/drivers/mbox/boards/nrf5340bsim_nrf5340_cpuapp.overlay b/samples/drivers/mbox/boards/nrf5340bsim_nrf5340_cpuapp.overlay new file mode 100644 index 00000000000..84fbe396fdb --- /dev/null +++ b/samples/drivers/mbox/boards/nrf5340bsim_nrf5340_cpuapp.overlay @@ -0,0 +1,12 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 1>, <&mbox 0>; + mbox-names = "tx", "rx"; + }; +}; diff --git a/samples/drivers/mbox/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/drivers/mbox/boards/nrf5340dk_nrf5340_cpuapp.overlay new file mode 100644 index 00000000000..84fbe396fdb --- /dev/null +++ b/samples/drivers/mbox/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -0,0 +1,12 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 1>, <&mbox 0>; + mbox-names = "tx", "rx"; + }; +}; diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay index 5f0cfe2261d..3618aab1d16 100644 --- a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay +++ b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay @@ -3,6 +3,14 @@ * SPDX-License-Identifier: Apache-2.0 */ -mbox: &cpuapp_bellboard { +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&cpuapp_bellboard 0>; + mbox-names = "rx"; + }; +}; + +&cpuapp_bellboard { status = "okay"; }; diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf index d8d66e9812d..4596bc3a757 100644 --- a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf +++ b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf @@ -1,2 +1 @@ CONFIG_RX_ENABLED=n -CONFIG_TX_CHANNEL_ID=4 diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay index ed631f04cc3..4e01f9a79d5 100644 --- a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay +++ b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay @@ -3,6 +3,14 @@ * SPDX-License-Identifier: Apache-2.0 */ -mbox: &cpuppr_vevif { +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&cpuppr_vevif 4>; + mbox-names = "tx"; + }; +}; + +&cpuppr_vevif { status = "okay"; }; diff --git a/samples/drivers/mbox/remote/Kconfig b/samples/drivers/mbox/remote/Kconfig index 7edb8574359..245890bfe78 100644 --- a/samples/drivers/mbox/remote/Kconfig +++ b/samples/drivers/mbox/remote/Kconfig @@ -9,22 +9,8 @@ config TX_ENABLED help Enable TX -config TX_CHANNEL_ID - int "Channel ID for TX" - default 0 - depends on TX_ENABLED - help - Channel ID for TX - config RX_ENABLED bool "RX enabled" default y help Enable RX - -config RX_CHANNEL_ID - int "Channel ID for RX" - depends on RX_ENABLED - default 1 - help - Channel ID for RX diff --git a/samples/drivers/mbox/remote/boards/adp_xc7k_ae350.overlay b/samples/drivers/mbox/remote/boards/adp_xc7k_ae350.overlay new file mode 100644 index 00000000000..736ea3f3f6d --- /dev/null +++ b/samples/drivers/mbox/remote/boards/adp_xc7k_ae350.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2019 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 0>, <&mbox 1>; + mbox-names = "tx", "rx"; + }; +}; diff --git a/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay b/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay index 36e6f0ff267..c1b12825fc0 100644 --- a/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay +++ b/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay @@ -28,6 +28,12 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 0>, <&mbox 1>; + mbox-names = "tx", "rx"; + }; }; &flexcomm0 { diff --git a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_cm4.conf b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_cm4.conf deleted file mode 100644 index 0d36a72aec6..00000000000 --- a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_cm4.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_BUILD_OUTPUT_INFO_HEADER=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_cm4.overlay deleted file mode 100644 index cc05e9b96c1..00000000000 --- a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_cm4.overlay +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash = &ocram; - zephyr,console = &lpuart1; - zephyr,shell-uart = &lpuart1; - - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /delete-node/ gpt@400f0000; - - /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { - compatible = "nxp,gpt-hw-timer"; - reg = <0x400f0000 0x4000>; - interrupts = <120 0>; - status = "okay"; - }; - - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c4c000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c4c000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; -}; - -/* Disable primary GPT timer */ -&gpt_hw_timer { - status = "disabled"; -}; diff --git a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay index cc05e9b96c1..93538b0acf2 100644 --- a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay +++ b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -40,6 +40,12 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 0>, <&mbox 1>; + mbox-names = "tx", "rx"; + }; }; /* Disable primary GPT timer */ diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_cm4.conf b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_cm4.conf deleted file mode 100644 index 0d36a72aec6..00000000000 --- a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_cm4.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_BUILD_OUTPUT_INFO_HEADER=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_cm4.overlay deleted file mode 100644 index cc05e9b96c1..00000000000 --- a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_cm4.overlay +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash = &ocram; - zephyr,console = &lpuart1; - zephyr,shell-uart = &lpuart1; - - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /delete-node/ gpt@400f0000; - - /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { - compatible = "nxp,gpt-hw-timer"; - reg = <0x400f0000 0x4000>; - interrupts = <120 0>; - status = "okay"; - }; - - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c4c000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c4c000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; -}; - -/* Disable primary GPT timer */ -&gpt_hw_timer { - status = "disabled"; -}; diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay index cc05e9b96c1..93538b0acf2 100644 --- a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -40,6 +40,12 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 0>, <&mbox 1>; + mbox-names = "tx", "rx"; + }; }; /* Disable primary GPT timer */ diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index 392141712a9..c2c38c0b930 100644 --- a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -41,6 +41,12 @@ }; }; + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 0>, <&mbox 1>; + mbox-names = "tx", "rx"; + }; + }; /* Disable primary GPT timer */ diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evkb_cm4.conf b/samples/drivers/mbox/remote/boards/mimxrt1170_evkb_cm4.conf deleted file mode 100644 index 0d36a72aec6..00000000000 --- a/samples/drivers/mbox/remote/boards/mimxrt1170_evkb_cm4.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_BUILD_OUTPUT_INFO_HEADER=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evkb_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evkb_cm4.overlay deleted file mode 100644 index 392141712a9..00000000000 --- a/samples/drivers/mbox/remote/boards/mimxrt1170_evkb_cm4.overlay +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash = &ocram; - zephyr,console = &lpuart1; - zephyr,shell-uart = &lpuart1; - - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /delete-node/ gpt@400f0000; - - /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { - compatible = "nxp,gpt-hw-timer"; - reg = <0x400f0000 0x4000>; - interrupts = <120 0>; - status = "okay"; - }; - - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c4c000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c4c000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; - -}; - -/* Disable primary GPT timer */ -&gpt_hw_timer { - status = "disabled"; -}; diff --git a/samples/drivers/mbox/remote/boards/nrf5340bsim_nrf5340_cpunet.overlay b/samples/drivers/mbox/remote/boards/nrf5340bsim_nrf5340_cpunet.overlay new file mode 100644 index 00000000000..398dafd5d1e --- /dev/null +++ b/samples/drivers/mbox/remote/boards/nrf5340bsim_nrf5340_cpunet.overlay @@ -0,0 +1,12 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 0>, <&mbox 1>; + mbox-names = "tx", "rx"; + }; +}; diff --git a/samples/drivers/mbox/remote/boards/nrf5340dk_nrf5340_cpunet.overlay b/samples/drivers/mbox/remote/boards/nrf5340dk_nrf5340_cpunet.overlay new file mode 100644 index 00000000000..398dafd5d1e --- /dev/null +++ b/samples/drivers/mbox/remote/boards/nrf5340dk_nrf5340_cpunet.overlay @@ -0,0 +1,12 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 0>, <&mbox 1>; + mbox-names = "tx", "rx"; + }; +}; diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay index 5f0cfe2261d..53eec7c680c 100644 --- a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay +++ b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay @@ -3,6 +3,14 @@ * SPDX-License-Identifier: Apache-2.0 */ -mbox: &cpuapp_bellboard { +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&cpuapp_bellboard 0>; + mbox-names = "tx"; + }; +}; + +&cpuapp_bellboard { status = "okay"; }; diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf index 19e03b75c63..0b6bc73d6bc 100644 --- a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf +++ b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf @@ -1,2 +1 @@ CONFIG_TX_ENABLED=n -CONFIG_RX_CHANNEL_ID=4 diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay index ed631f04cc3..365469e86bd 100644 --- a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay +++ b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay @@ -3,6 +3,14 @@ * SPDX-License-Identifier: Apache-2.0 */ -mbox: &cpuppr_vevif { +/ { + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&cpuppr_vevif 4>; + mbox-names = "rx"; + }; +}; + +&cpuppr_vevif { status = "okay"; }; diff --git a/samples/drivers/mbox/remote/src/main.c b/samples/drivers/mbox/remote/src/main.c index 1ca832a697c..30ac421b885 100644 --- a/samples/drivers/mbox/remote/src/main.c +++ b/samples/drivers/mbox/remote/src/main.c @@ -28,7 +28,7 @@ int main(void) printk("Hello from REMOTE\n"); #ifdef CONFIG_RX_ENABLED - struct mbox_channel rx_channel; + const struct mbox_channel rx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx); mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); @@ -46,7 +46,7 @@ int main(void) #endif /* CONFIG_RX_ENABLED */ #ifdef CONFIG_TX_ENABLED - struct mbox_channel tx_channel; + const struct mbox_channel tx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx); mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); diff --git a/samples/drivers/mbox/src/main.c b/samples/drivers/mbox/src/main.c index d4dd21d342f..aa6fbbf5d45 100644 --- a/samples/drivers/mbox/src/main.c +++ b/samples/drivers/mbox/src/main.c @@ -14,7 +14,7 @@ static void callback(const struct device *dev, uint32_t channel, { printk("Pong (on channel %d)\n", channel); } -#endif +#endif /* CONFIG_RX_ENABLED */ int main(void) { @@ -24,7 +24,7 @@ int main(void) printk("Hello from APP\n"); #ifdef CONFIG_RX_ENABLED - struct mbox_channel rx_channel; + const struct mbox_channel rx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx); mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); @@ -42,7 +42,7 @@ int main(void) #endif /* CONFIG_RX_ENABLED */ #ifdef CONFIG_TX_ENABLED - struct mbox_channel tx_channel; + const struct mbox_channel tx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx); mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); From 529bf56aa35e331ba92e2326aeffe9f6b6cbd083 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 11:33:50 +0100 Subject: [PATCH 0306/2402] samples: drivers: mbox_data: use DT Instead of hardcoded stuff in C sources (node label and channel IDs). Signed-off-by: Gerard Marull-Paretas --- .../lpcxpresso55s69_lpc55s69_cpu0.overlay | 6 ++ .../mbox_data/boards/mimxrt1160_evk_cm7.conf | 3 - .../boards/mimxrt1160_evk_cm7.overlay | 29 ---------- .../mimxrt1160_evk_mimxrt1166_cm7.overlay | 6 ++ .../mimxrt1170_evk_mimxrt1176_cm7_A.overlay | 6 ++ .../mimxrt1170_evk_mimxrt1176_cm7_B.overlay | 6 ++ .../mbox_data/boards/mimxrt1170_evkb_cm7.conf | 3 - .../lpcxpresso55s69_lpc55s69_cpu1.overlay | 6 ++ .../remote/boards/mimxrt1160_evk_cm4.conf | 4 -- .../remote/boards/mimxrt1160_evk_cm4.overlay | 54 ------------------ .../mimxrt1160_evk_mimxrt1166_cm4.overlay | 6 ++ .../remote/boards/mimxrt1170_evk_cm4.conf | 4 -- .../remote/boards/mimxrt1170_evk_cm4.overlay | 54 ------------------ .../mimxrt1170_evk_mimxrt1176_cm4.overlay | 6 ++ .../mimxrt1170_evk_mimxrt1176_cm4_B.overlay | 5 ++ .../remote/boards/mimxrt1170_evkb_cm4.conf | 4 -- .../remote/boards/mimxrt1170_evkb_cm4.overlay | 55 ------------------- samples/drivers/mbox_data/remote/src/main.c | 15 +---- samples/drivers/mbox_data/src/main.c | 15 +---- 19 files changed, 53 insertions(+), 234 deletions(-) delete mode 100644 samples/drivers/mbox_data/boards/mimxrt1160_evk_cm7.conf delete mode 100644 samples/drivers/mbox_data/boards/mimxrt1160_evk_cm7.overlay delete mode 100644 samples/drivers/mbox_data/boards/mimxrt1170_evkb_cm7.conf delete mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_cm4.conf delete mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_cm4.overlay delete mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_cm4.conf delete mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_cm4.overlay delete mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1170_evkb_cm4.conf delete mode 100644 samples/drivers/mbox_data/remote/boards/mimxrt1170_evkb_cm4.overlay diff --git a/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay index b5919c4fd72..76773b87fcd 100644 --- a/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay +++ b/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay @@ -26,4 +26,10 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 3>, <&mbox 2>; + mbox-names = "tx", "rx"; + }; }; diff --git a/samples/drivers/mbox_data/boards/mimxrt1160_evk_cm7.conf b/samples/drivers/mbox_data/boards/mimxrt1160_evk_cm7.conf deleted file mode 100644 index 583b4950360..00000000000 --- a/samples/drivers/mbox_data/boards/mimxrt1160_evk_cm7.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_INCLUDE_REMOTE_DIR=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/boards/mimxrt1160_evk_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1160_evk_cm7.overlay deleted file mode 100644 index 870b9928faf..00000000000 --- a/samples/drivers/mbox_data/boards/mimxrt1160_evk_cm7.overlay +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c48000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c48000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c48000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; -}; diff --git a/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay index 870b9928faf..c2014d3d809 100644 --- a/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay +++ b/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -26,4 +26,10 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 3>, <&mbox 2>; + mbox-names = "tx", "rx"; + }; }; diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay index 870b9928faf..c2014d3d809 100644 --- a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay +++ b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -26,4 +26,10 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 3>, <&mbox 2>; + mbox-names = "tx", "rx"; + }; }; diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay index 870b9928faf..c2014d3d809 100644 --- a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay +++ b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -26,4 +26,10 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 3>, <&mbox 2>; + mbox-names = "tx", "rx"; + }; }; diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evkb_cm7.conf b/samples/drivers/mbox_data/boards/mimxrt1170_evkb_cm7.conf deleted file mode 100644 index 0dfb100ed70..00000000000 --- a/samples/drivers/mbox_data/boards/mimxrt1170_evkb_cm7.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_SECOND_CORE_MCUX=y -CONFIG_INCLUDE_REMOTE_DIR=y diff --git a/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay b/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay index 96bd5aa1c3a..a1cfbf7224d 100644 --- a/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay +++ b/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay @@ -26,4 +26,10 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 2>, <&mbox 3>; + mbox-names = "tx", "rx"; + }; }; diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_cm4.conf b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_cm4.conf deleted file mode 100644 index 0d36a72aec6..00000000000 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_cm4.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_BUILD_OUTPUT_INFO_HEADER=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_cm4.overlay deleted file mode 100644 index 3f6115b9c58..00000000000 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_cm4.overlay +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash = &ocram; - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /delete-node/ gpt@400f0000; - - /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { - compatible = "nxp,gpt-hw-timer"; - reg = <0x400f0000 0x4000>; - interrupts = <120 0>; - status = "okay"; - }; - - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c4c000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c4c000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; -}; - -/* Enable secondary LPUART */ -&lpuart2 { - status = "okay"; - current-speed = <115200>; -}; - -/* Disable primary GPT timer */ -&gpt_hw_timer { - status = "disabled"; -}; diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay index 3f6115b9c58..c4cbef58d77 100644 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -40,6 +40,12 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 3>, <&mbox 2>; + mbox-names = "tx", "rx"; + }; }; /* Enable secondary LPUART */ diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_cm4.conf b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_cm4.conf deleted file mode 100644 index 0d36a72aec6..00000000000 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_cm4.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_BUILD_OUTPUT_INFO_HEADER=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_cm4.overlay deleted file mode 100644 index 3f6115b9c58..00000000000 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_cm4.overlay +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash = &ocram; - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /delete-node/ gpt@400f0000; - - /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { - compatible = "nxp,gpt-hw-timer"; - reg = <0x400f0000 0x4000>; - interrupts = <120 0>; - status = "okay"; - }; - - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c4c000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c4c000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; -}; - -/* Enable secondary LPUART */ -&lpuart2 { - status = "okay"; - current-speed = <115200>; -}; - -/* Disable primary GPT timer */ -&gpt_hw_timer { - status = "disabled"; -}; diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay index 3f6115b9c58..c4cbef58d77 100644 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -40,6 +40,12 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 3>, <&mbox 2>; + mbox-names = "tx", "rx"; + }; }; /* Enable secondary LPUART */ diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index e3576826702..c4cbef58d77 100644 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -41,6 +41,11 @@ }; }; + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 3>, <&mbox 2>; + mbox-names = "tx", "rx"; + }; }; /* Enable secondary LPUART */ diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evkb_cm4.conf b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evkb_cm4.conf deleted file mode 100644 index 0d36a72aec6..00000000000 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evkb_cm4.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_BUILD_OUTPUT_INFO_HEADER=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evkb_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evkb_cm4.overlay deleted file mode 100644 index e3576826702..00000000000 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evkb_cm4.overlay +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash = &ocram; - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /delete-node/ gpt@400f0000; - - /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { - compatible = "nxp,gpt-hw-timer"; - reg = <0x400f0000 0x4000>; - interrupts = <120 0>; - status = "okay"; - }; - - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c4c000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c4c000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; - -}; - -/* Enable secondary LPUART */ -&lpuart2 { - status = "okay"; - current-speed = <115200>; -}; - -/* Disable primary GPT timer */ -&gpt_hw_timer { - status = "disabled"; -}; diff --git a/samples/drivers/mbox_data/remote/src/main.c b/samples/drivers/mbox_data/remote/src/main.c index 0f3ad77a4d0..bb73fabbbc1 100644 --- a/samples/drivers/mbox_data/remote/src/main.c +++ b/samples/drivers/mbox_data/remote/src/main.c @@ -15,9 +15,6 @@ static K_SEM_DEFINE(g_mbox_data_rx_sem, 0, 1); static uint32_t g_mbox_received_data; static uint32_t g_mbox_received_channel; -#define TX_ID (2) -#define RX_ID (3) - static void callback(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data) { @@ -29,20 +26,14 @@ static void callback(const struct device *dev, uint32_t channel, void *user_data int main(void) { - struct mbox_channel tx_channel; - struct mbox_channel rx_channel; - const struct device *dev; + const struct mbox_channel tx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx); + const struct mbox_channel rx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx); struct mbox_msg msg = {0}; uint32_t message = 0; printk("mbox_data Server demo started\n"); - dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); - - mbox_init_channel(&tx_channel, dev, TX_ID); - mbox_init_channel(&rx_channel, dev, RX_ID); - - const int max_transfer_size_bytes = mbox_mtu_get(dev); + const int max_transfer_size_bytes = mbox_mtu_get(tx_channel.dev); /* Sample currently supports only transfer size up to 4 bytes */ if ((max_transfer_size_bytes <= 0) || (max_transfer_size_bytes > 4)) { printk("mbox_mtu_get() error\n"); diff --git a/samples/drivers/mbox_data/src/main.c b/samples/drivers/mbox_data/src/main.c index 85df24940c4..b6520418484 100644 --- a/samples/drivers/mbox_data/src/main.c +++ b/samples/drivers/mbox_data/src/main.c @@ -15,9 +15,6 @@ static K_SEM_DEFINE(g_mbox_data_rx_sem, 0, 1); static uint32_t g_mbox_received_data; static uint32_t g_mbox_received_channel; -#define TX_ID (3) -#define RX_ID (2) - static void callback(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data) { @@ -29,20 +26,14 @@ static void callback(const struct device *dev, uint32_t channel, void *user_data int main(void) { - struct mbox_channel tx_channel; - struct mbox_channel rx_channel; - const struct device *dev; + const struct mbox_channel tx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx); + const struct mbox_channel rx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx); struct mbox_msg msg = {0}; uint32_t message = 0; printk("mbox_data Client demo started\n"); - dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); - - mbox_init_channel(&tx_channel, dev, TX_ID); - mbox_init_channel(&rx_channel, dev, RX_ID); - - const int max_transfer_size_bytes = mbox_mtu_get(dev); + const int max_transfer_size_bytes = mbox_mtu_get(tx_channel.dev); /* Sample currently supports only transfer size up to 4 bytes */ if ((max_transfer_size_bytes < 0) || (max_transfer_size_bytes > 4)) { printk("mbox_mtu_get() error\n"); From b39d123163a776245376ec3bff4bc8543304adce Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 12:03:53 +0100 Subject: [PATCH 0307/2402] tests: drivers: mbox: mbox_data: use DT Instead of hardcoding everything in the sample. Signed-off-by: Gerard Marull-Paretas --- .../lpcxpresso55s69_lpc55s69_cpu0.overlay | 8 +++ .../mbox_data/boards/mimxrt1160_evk_cm7.conf | 3 - .../boards/mimxrt1160_evk_cm7.overlay | 29 -------- .../mimxrt1160_evk_mimxrt1166_cm7.overlay | 8 +++ .../mimxrt1170_evk_mimxrt1176_cm7_A.overlay | 8 +++ .../mimxrt1170_evk_mimxrt1176_cm7_B.overlay | 8 +++ .../mbox_data/boards/mimxrt1170_evkb_cm7.conf | 3 - .../lpcxpresso55s69_lpc55s69_cpu1.overlay | 8 +++ .../remote/boards/mimxrt1160_evk_cm4.conf | 4 -- .../remote/boards/mimxrt1160_evk_cm4.overlay | 54 --------------- .../mimxrt1160_evk_mimxrt1166_cm4.overlay | 8 +++ .../remote/boards/mimxrt1170_evk_cm4.conf | 4 -- .../remote/boards/mimxrt1170_evk_cm4.overlay | 54 --------------- .../mimxrt1170_evk_mimxrt1176_cm4.overlay | 8 +++ .../mimxrt1170_evk_mimxrt1176_cm4_B.overlay | 7 ++ .../remote/boards/mimxrt1170_evkb_cm4.conf | 4 -- .../remote/boards/mimxrt1170_evkb_cm4.overlay | 55 --------------- .../drivers/mbox/mbox_data/remote/src/main.c | 69 ++++++++++--------- tests/drivers/mbox/mbox_data/src/main.c | 68 +++++++++--------- 19 files changed, 135 insertions(+), 275 deletions(-) delete mode 100644 tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_cm7.conf delete mode 100644 tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_cm7.overlay delete mode 100644 tests/drivers/mbox/mbox_data/boards/mimxrt1170_evkb_cm7.conf delete mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_cm4.conf delete mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_cm4.overlay delete mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_cm4.conf delete mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_cm4.overlay delete mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evkb_cm4.conf delete mode 100644 tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evkb_cm4.overlay diff --git a/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay index b5919c4fd72..b178929819b 100644 --- a/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay +++ b/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay @@ -26,4 +26,12 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 3>, <&mbox 2>, <&mbox 1>, <&mbox 0>, <&mbox 2>, + <&mbox 3>, <&mbox 0>, <&mbox 1>; + mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", + "rx3"; + }; }; diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_cm7.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_cm7.conf deleted file mode 100644 index 583b4950360..00000000000 --- a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_cm7.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_INCLUDE_REMOTE_DIR=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_cm7.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_cm7.overlay deleted file mode 100644 index 870b9928faf..00000000000 --- a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_cm7.overlay +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c48000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c48000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c48000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; -}; diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay index 870b9928faf..ecec226423a 100644 --- a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -26,4 +26,12 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 3>, <&mbox 2>, <&mbox 1>, <&mbox 0>, <&mbox 2>, + <&mbox 3>, <&mbox 0>, <&mbox 1>; + mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", + "rx3"; + }; }; diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay index 870b9928faf..ecec226423a 100644 --- a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -26,4 +26,12 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 3>, <&mbox 2>, <&mbox 1>, <&mbox 0>, <&mbox 2>, + <&mbox 3>, <&mbox 0>, <&mbox 1>; + mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", + "rx3"; + }; }; diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay index 870b9928faf..ecec226423a 100644 --- a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -26,4 +26,12 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 3>, <&mbox 2>, <&mbox 1>, <&mbox 0>, <&mbox 2>, + <&mbox 3>, <&mbox 0>, <&mbox 1>; + mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", + "rx3"; + }; }; diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evkb_cm7.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evkb_cm7.conf deleted file mode 100644 index 0dfb100ed70..00000000000 --- a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evkb_cm7.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_SECOND_CORE_MCUX=y -CONFIG_INCLUDE_REMOTE_DIR=y diff --git a/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay b/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay index 96bd5aa1c3a..a4ced8e5ec6 100644 --- a/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay +++ b/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay @@ -26,4 +26,12 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 2>, <&mbox 3>, <&mbox 0>, <&mbox 1>, <&mbox 3>, + <&mbox 2>, <&mbox 1>, <&mbox 0>; + mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", + "rx3"; + }; }; diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_cm4.conf b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_cm4.conf deleted file mode 100644 index 0d36a72aec6..00000000000 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_cm4.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_BUILD_OUTPUT_INFO_HEADER=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_cm4.overlay deleted file mode 100644 index 3f6115b9c58..00000000000 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_cm4.overlay +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash = &ocram; - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /delete-node/ gpt@400f0000; - - /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { - compatible = "nxp,gpt-hw-timer"; - reg = <0x400f0000 0x4000>; - interrupts = <120 0>; - status = "okay"; - }; - - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c4c000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c4c000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; -}; - -/* Enable secondary LPUART */ -&lpuart2 { - status = "okay"; - current-speed = <115200>; -}; - -/* Disable primary GPT timer */ -&gpt_hw_timer { - status = "disabled"; -}; diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay index 3f6115b9c58..ccf8543fa67 100644 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -40,6 +40,14 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 2>, <&mbox 3>, <&mbox 0>, <&mbox 1>, <&mbox 3>, + <&mbox 2>, <&mbox 1>, <&mbox 0>; + mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", + "rx3"; + }; }; /* Enable secondary LPUART */ diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_cm4.conf b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_cm4.conf deleted file mode 100644 index 0d36a72aec6..00000000000 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_cm4.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_BUILD_OUTPUT_INFO_HEADER=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_cm4.overlay deleted file mode 100644 index 3f6115b9c58..00000000000 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_cm4.overlay +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash = &ocram; - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /delete-node/ gpt@400f0000; - - /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { - compatible = "nxp,gpt-hw-timer"; - reg = <0x400f0000 0x4000>; - interrupts = <120 0>; - status = "okay"; - }; - - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c4c000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c4c000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; -}; - -/* Enable secondary LPUART */ -&lpuart2 { - status = "okay"; - current-speed = <115200>; -}; - -/* Disable primary GPT timer */ -&gpt_hw_timer { - status = "disabled"; -}; diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay index 3f6115b9c58..ccf8543fa67 100644 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -40,6 +40,14 @@ status = "okay"; }; }; + + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 2>, <&mbox 3>, <&mbox 0>, <&mbox 1>, <&mbox 3>, + <&mbox 2>, <&mbox 1>, <&mbox 0>; + mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", + "rx3"; + }; }; /* Enable secondary LPUART */ diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index e3576826702..ccf8543fa67 100644 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -41,6 +41,13 @@ }; }; + mbox-consumer { + compatible = "vnd,mbox-consumer"; + mboxes = <&mbox 2>, <&mbox 3>, <&mbox 0>, <&mbox 1>, <&mbox 3>, + <&mbox 2>, <&mbox 1>, <&mbox 0>; + mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", + "rx3"; + }; }; /* Enable secondary LPUART */ diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evkb_cm4.conf b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evkb_cm4.conf deleted file mode 100644 index 0d36a72aec6..00000000000 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evkb_cm4.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_MBOX_NXP_IMX_MU=y -CONFIG_BUILD_OUTPUT_INFO_HEADER=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evkb_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evkb_cm4.overlay deleted file mode 100644 index e3576826702..00000000000 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evkb_cm4.overlay +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash = &ocram; - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - - /* Delete ipc chosen property where old IPM mailbox driver bellow is - * configured. - */ - /delete-property/ zephyr,ipc; - }; - - soc { - /delete-node/ gpt@400f0000; - - /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { - compatible = "nxp,gpt-hw-timer"; - reg = <0x400f0000 0x4000>; - interrupts = <120 0>; - status = "okay"; - }; - - /* Delete IPM Driver node nxp,imx-mu */ - /delete-node/ mailbox@40c4c000; - - /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { - compatible = "nxp,mbox-imx-mu"; - reg = <0x40c4c000 0x4000>; - interrupts = <118 0>; - rx-channels = <4>; - #mbox-cells = <1>; - status = "okay"; - }; - }; - -}; - -/* Enable secondary LPUART */ -&lpuart2 { - status = "okay"; - current-speed = <115200>; -}; - -/* Disable primary GPT timer */ -&gpt_hw_timer { - status = "disabled"; -}; diff --git a/tests/drivers/mbox/mbox_data/remote/src/main.c b/tests/drivers/mbox/mbox_data/remote/src/main.c index d9eba4d3b7c..661a48a2a8f 100644 --- a/tests/drivers/mbox/mbox_data/remote/src/main.c +++ b/tests/drivers/mbox/mbox_data/remote/src/main.c @@ -15,20 +15,28 @@ static K_SEM_DEFINE(g_mbox_data_rx_sem, 0, 1); static uint32_t g_mbox_received_data; static uint32_t g_mbox_received_channel; -#define TX_ID0 (2) -#define RX_ID0 (3) -#define TX_ID1 (0) -#define RX_ID1 (1) -#define TX_ID2 (3) -#define RX_ID2 (2) -#define TX_ID3 (1) -#define RX_ID3 (0) - -#define CHANNELS_TO_TEST (4) -#define TX_CHANNEL_INDEX (0) -#define RX_CHANNEL_INDEX (1) -const static uint32_t TEST_CHANNELS[CHANNELS_TO_TEST][2] = { - {TX_ID0, RX_ID0}, {TX_ID1, RX_ID1}, {TX_ID2, RX_ID2}, {TX_ID3, RX_ID3}}; +#define CHANNELS_TO_TEST 4 +#define TX_CHANNEL_INDEX 0 +#define RX_CHANNEL_INDEX 1 + +static const struct mbox_channel channels[CHANNELS_TO_TEST][2] = { + { + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx0), + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx0), + }, + { + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx1), + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx1), + }, + { + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx2), + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx2), + }, + { + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx3), + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx3), + }, +}; static void callback(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data) @@ -43,33 +51,26 @@ static void callback(const struct device *dev, uint32_t channel, void *user_data int main(void) { - struct mbox_channel tx_channel; - struct mbox_channel rx_channel; - const struct device *dev; struct mbox_msg msg = {0}; uint32_t message = 0; - dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); + for (int i = 0; i < ARRAY_SIZE(channels); i++) { + const struct mbox_channel *tx_channel = &channels[i][TX_CHANNEL_INDEX]; + const struct mbox_channel *rx_channel = &channels[i][RX_CHANNEL_INDEX]; - const int max_transfer_size_bytes = mbox_mtu_get(dev); - /* Sample currently supports only transfer size up to 4 bytes */ - if ((max_transfer_size_bytes <= 0) || (max_transfer_size_bytes > 4)) { - printk("mbox_mtu_get() error\n"); - return 0; - } - - for (int i_test_channel = 0; i_test_channel < CHANNELS_TO_TEST; i_test_channel++) { - mbox_init_channel(&tx_channel, dev, - TEST_CHANNELS[i_test_channel][TX_CHANNEL_INDEX]); - mbox_init_channel(&rx_channel, dev, - TEST_CHANNELS[i_test_channel][RX_CHANNEL_INDEX]); + const int max_transfer_size_bytes = mbox_mtu_get(tx_channel->dev); + /* Sample currently supports only transfer size up to 4 bytes */ + if ((max_transfer_size_bytes <= 0) || (max_transfer_size_bytes > 4)) { + printk("mbox_mtu_get() error\n"); + return 0; + } - if (mbox_register_callback(&rx_channel, callback, NULL)) { + if (mbox_register_callback(rx_channel, callback, NULL)) { printk("mbox_register_callback() error\n"); return 0; } - if (mbox_set_enabled(&rx_channel, 1)) { + if (mbox_set_enabled(rx_channel, 1)) { printk("mbox_set_enable() error\n"); return 0; } @@ -87,13 +88,13 @@ int main(void) msg.data = &message; msg.size = max_transfer_size_bytes; - if (mbox_send(&tx_channel, &msg) < 0) { + if (mbox_send(tx_channel, &msg) < 0) { printk("mbox_send() error\n"); return 0; } } /* Disable current rx channel after channel loop */ - mbox_set_enabled(&rx_channel, 0); + mbox_set_enabled(rx_channel, 0); } } diff --git a/tests/drivers/mbox/mbox_data/src/main.c b/tests/drivers/mbox/mbox_data/src/main.c index 82cce00ae7f..9a50e158664 100644 --- a/tests/drivers/mbox/mbox_data/src/main.c +++ b/tests/drivers/mbox/mbox_data/src/main.c @@ -23,23 +23,29 @@ static bool g_received_size_error; static size_t g_received_size; static int g_max_transfer_size_bytes; -static struct mbox_channel g_tx_channel; -static struct mbox_channel g_rx_channel; - -#define TX_ID0 (3) -#define RX_ID0 (2) -#define TX_ID1 (1) -#define RX_ID1 (0) -#define TX_ID2 (2) -#define RX_ID2 (3) -#define TX_ID3 (0) -#define RX_ID3 (1) - -#define CHANNELS_TO_TEST (4) -#define TX_CHANNEL_INDEX (0) -#define RX_CHANNEL_INDEX (1) -const static uint32_t TEST_CHANNELS[CHANNELS_TO_TEST][2] = { - {TX_ID0, RX_ID0}, {TX_ID1, RX_ID1}, {TX_ID2, RX_ID2}, {TX_ID3, RX_ID3}}; +#define CHANNELS_TO_TEST 4 +#define TX_CHANNEL_INDEX 0 +#define RX_CHANNEL_INDEX 1 + +static const struct mbox_channel channels[CHANNELS_TO_TEST][2] = { + { + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx0), + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx0), + }, + { + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx1), + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx1), + }, + { + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx2), + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx2), + }, + { + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx3), + MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx3), + }, +}; + static uint32_t current_channel_index; static void callback(const struct device *dev, uint32_t channel, void *user_data, @@ -62,12 +68,11 @@ static void mbox_data_tests_before(void *f) { zassert_false(current_channel_index >= CHANNELS_TO_TEST, "Channel to test is out of range"); - const struct device *dev; + const struct mbox_channel *tx_channel = &channels[current_channel_index][TX_CHANNEL_INDEX]; + const struct mbox_channel *rx_channel = &channels[current_channel_index][RX_CHANNEL_INDEX]; int ret_val = 0; - dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); - - g_max_transfer_size_bytes = mbox_mtu_get(dev); + g_max_transfer_size_bytes = mbox_mtu_get(tx_channel->dev); /* Test currently supports only transfer size up to 4 bytes */ if ((g_max_transfer_size_bytes < 0) || (g_max_transfer_size_bytes > 4)) { printk("mbox_mtu_get() error\n"); @@ -75,22 +80,21 @@ static void mbox_data_tests_before(void *f) g_max_transfer_size_bytes); } - mbox_init_channel(&g_tx_channel, dev, - TEST_CHANNELS[current_channel_index][TX_CHANNEL_INDEX]); - mbox_init_channel(&g_rx_channel, dev, - TEST_CHANNELS[current_channel_index][RX_CHANNEL_INDEX]); - - ret_val = mbox_register_callback(&g_rx_channel, callback, NULL); + ret_val = mbox_register_callback(rx_channel, callback, NULL); zassert_false(ret_val != 0, "mbox failed to register callback. ret_val", ret_val); - ret_val = mbox_set_enabled(&g_rx_channel, 1); + ret_val = mbox_set_enabled(rx_channel, 1); zassert_false(ret_val != 0, "mbox failed to enable mbox. ret_val: %d", ret_val); } static void mbox_data_tests_after(void *f) { + zassert_false(current_channel_index >= CHANNELS_TO_TEST, "Channel to test is out of range"); + + const struct mbox_channel *rx_channel = &channels[current_channel_index][RX_CHANNEL_INDEX]; + /* Disable channel after test end */ - int ret_val = mbox_set_enabled(&g_rx_channel, 0); + int ret_val = mbox_set_enabled(rx_channel, 0); zassert_false(ret_val != 0, "mbox failed to disable mbox. ret_val: %d", ret_val); @@ -106,12 +110,14 @@ static void mbox_test(const uint32_t data) int ret_val = 0; while (test_count < 100) { + const struct mbox_channel *tx_channel = &channels[current_channel_index][TX_CHANNEL_INDEX]; + /* Main core prepare test data */ msg.data = &test_data; msg.size = g_max_transfer_size_bytes; /* Main core send test data */ - ret_val = mbox_send(&g_tx_channel, &msg); + ret_val = mbox_send(tx_channel, &msg); zassert_false(ret_val < 0, "mbox failed to send. ret_val: %d", ret_val); /* Expect next received data will be incremented by one. @@ -136,7 +142,7 @@ static void mbox_test(const uint32_t data) g_mbox_expected_data, test_data); /* Expect reception of data on current RX channel */ - g_mbox_expected_channel = TEST_CHANNELS[current_channel_index][RX_CHANNEL_INDEX]; + g_mbox_expected_channel = channels[current_channel_index][RX_CHANNEL_INDEX].id; zassert_equal(g_mbox_expected_channel, g_mbox_received_channel, "Received channel does not match!: Expected: %d, Got: %d", g_mbox_expected_channel, g_mbox_received_channel); From 568596590cd722a6e57892b41fa9460e2852ad83 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 12:19:58 +0100 Subject: [PATCH 0308/2402] drivers: mbox: improve Doxygen Fix a few Doxygen issues, e.g. - References to structs - Incorrect usage of `@a`, `@p` - Unnecessary usages of `@typedef` - Incorrect usages of `@retval` - etc. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/drivers/mbox.h | 192 ++++++++++++++++------------------ 1 file changed, 89 insertions(+), 103 deletions(-) diff --git a/include/zephyr/drivers/mbox.h b/include/zephyr/drivers/mbox.h index 07924587e9c..c50d8df4813 100644 --- a/include/zephyr/drivers/mbox.h +++ b/include/zephyr/drivers/mbox.h @@ -1,18 +1,22 @@ -/** - * @file - * - * @brief Generic low-level multi-channel inter-processor mailbox communication API. - */ - /* * Copyright (c) 2021 Carlo Caione - * * SPDX-License-Identifier: Apache-2.0 */ #ifndef ZEPHYR_INCLUDE_DRIVERS_MBOX_H_ #define ZEPHYR_INCLUDE_DRIVERS_MBOX_H_ +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief MBOX Interface * @defgroup mbox_interface MBOX Interface @@ -66,37 +70,18 @@ * */ -#include -#include -#include - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Message struct (to hold data and its size). - */ +/** @brief Message struct (to hold data and its size). */ struct mbox_msg { /** Pointer to the data sent in the message. */ const void *data; - /** Size of the data. */ size_t size; }; -/** - * @brief Provides a type to hold an MBOX channel - * - * Struct type to hold an MBOX device pointer and the channel ID. - */ +/** @brief Provides a type to hold an MBOX channel */ struct mbox_channel { /** MBOX device pointer. */ const struct device *dev; - /** Channel ID. */ uint32_t id; }; @@ -104,92 +89,90 @@ struct mbox_channel { /** * @brief Structure initializer for mbox_channel from devicetree * - * This helper macro expands to a static initializer for a @p mbox_channel by - * reading the relevant device controller and channel number from the + * This helper macro expands to a static initializer for a struct mbox_channel + * by reading the relevant device controller and channel number from the * devicetree. * * Example devicetree fragment: * - * mbox1: mbox-controller@... { ... }; - * + * @code{.devicetree} * n: node { * mboxes = <&mbox1 8>, * <&mbox1 9>; * mbox-names = "tx", "rx"; * }; + * @endcode * * Example usage: * + * @code{.c} * const struct mbox_channel channel = MBOX_DT_CHANNEL_GET(DT_NODELABEL(n), tx); + * @endcode * * @param node_id Devicetree node identifier for the MBOX device * @param name lowercase-and-underscores name of the mboxes element + * + * @return static initializer for a struct mbox_channel */ -#define MBOX_DT_CHANNEL_GET(node_id, name) \ - { \ - .dev = DEVICE_DT_GET(DT_MBOX_CTLR_BY_NAME(node_id, name)), \ - .id = DT_MBOX_CHANNEL_BY_NAME(node_id, name), \ +#define MBOX_DT_CHANNEL_GET(node_id, name) \ + { \ + .dev = DEVICE_DT_GET(DT_MBOX_CTLR_BY_NAME(node_id, name)), \ + .id = DT_MBOX_CHANNEL_BY_NAME(node_id, name), \ } +/** @cond INTERNAL_HIDDEN */ + /** - * @typedef mbox_callback_t - * * @brief Callback API for incoming MBOX messages * * These callbacks execute in interrupt context. Therefore, use only - * interrupt-safe APIS. Registration of callbacks is done via @a + * interrupt-safe APIs. Registration of callbacks is done via * mbox_register_callback() * * The data parameter must be NULL in signalling mode. * - * @param dev Driver instance + * @param dev MBOX device instance * @param channel Channel ID - * @param user_data Pointer to some private data provided at registration - * time + * @param user_data Pointer to some private data provided at registration time * @param data Message struct */ typedef void (*mbox_callback_t)(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data); /** - * @typedef mbox_send_t - * * @brief Callback API to send MBOX messages * - * See @a mbox_send() for function description - * - * @param dev Driver instance + * @param dev MBOX device instance * @param channel Channel ID * @param msg Message struct * - * @return See return values for @a mbox_send() + * @return See the return values for mbox_send() + * @see mbox_send() */ typedef int (*mbox_send_t)(const struct device *dev, uint32_t channel, const struct mbox_msg *msg); /** - * @typedef mbox_mtu_get_t - * * @brief Callback API to get maximum data size * - * See @a mbox_mtu_get() for argument definitions. + * @param dev MBOX device instance + * + * @return See the return values for mbox_mtu_get() + * @see mbox_mtu_get() */ typedef int (*mbox_mtu_get_t)(const struct device *dev); /** - * @typedef mbox_register_callback_t - * * @brief Callback API upon registration * - * See @a mbox_register_callback() for function description - * - * @param dev Driver instance + * @param dev MBOX device instance * @param channel Channel ID * @param cb Callback function to execute on incoming message interrupts. - * @param user_data Application-specific data pointer which will be passed - * to the callback function when executed. + * @param user_data Application-specific data pointer which will be passed to + * the callback function when executed. * - * @return See return values for @a mbox_register_callback() + * @return See return values for mbox_register_callback() + * @see mbox_register_callback() */ typedef int (*mbox_register_callback_t)(const struct device *dev, uint32_t channel, @@ -197,26 +180,24 @@ typedef int (*mbox_register_callback_t)(const struct device *dev, void *user_data); /** - * @typedef mbox_set_enabled_t - * * @brief Callback API upon enablement of interrupts * - * See @a mbox_set_enabled() for function description - * - * @param dev Driver instance + * @param dev MBOX device instance * @param channel Channel ID * @param enable Set to 0 to disable and to nonzero to enable. * - * @return See return values for @a mbox_set_enabled() + * @return See return values for mbox_set_enabled() + * @see mbox_set_enabled() */ typedef int (*mbox_set_enabled_t)(const struct device *dev, uint32_t channel, bool enable); /** - * @typedef mbox_max_channels_get_t - * * @brief Callback API to get maximum number of channels * - * See @a mbox_max_channels_get() for argument definitions. + * @param dev MBOX device instance + * + * @return See return values for mbox_max_channels_get() + * @see mbox_max_channels_get() */ typedef uint32_t (*mbox_max_channels_get_t)(const struct device *dev); @@ -228,20 +209,22 @@ __subsystem struct mbox_driver_api { mbox_set_enabled_t set_enabled; }; +/** @endcond */ + /** * @brief Initialize a channel struct * - * Initialize an @p mbox_channel passed by the user with a provided MBOX device - * and channel ID. This function is needed when the information about the + * Initialize an struct mbox_channel passed by the user with a provided MBOX + * device and channel ID. This function is needed when the information about the * device and the channel ID is not in the DT. In the DT case * MBOX_DT_CHANNEL_GET() must be used instead. * - * @param channel Pointer to the channel struct - * @param dev Driver instance + * @param[out] channel MBOX channel instance + * @param dev MBOX device instance * @param ch_id Channel ID */ -static inline void mbox_init_channel(struct mbox_channel *channel, const struct device *dev, - uint32_t ch_id) +static inline void mbox_init_channel(struct mbox_channel *channel, + const struct device *dev, uint32_t ch_id) { channel->dev = dev; channel->id = ch_id; @@ -250,25 +233,26 @@ static inline void mbox_init_channel(struct mbox_channel *channel, const struct /** * @brief Try to send a message over the MBOX device. * - * Send a message over an @p mbox_channel. The msg parameter must be NULL when - * the driver is used for signalling. + * Send a message over an struct mbox_channel. The msg parameter must be NULL + * when the driver is used for signalling. * * If the msg parameter is not NULL, this data is expected to be delivered on * the receiving side using the data parameter of the receiving callback. * - * @param channel Channel instance pointer - * @param msg Pointer to the message struct + * @param channel MBOX channel instance + * @param msg Message * + * @retval 0 On success. * @retval -EBUSY If the remote hasn't yet read the last data sent. * @retval -EMSGSIZE If the supplied data size is unsupported by the driver. * @retval -EINVAL If there was a bad parameter, such as: too-large channel * descriptor or the device isn't an outbound MBOX channel. - * - * @retval 0 On success, negative value on error. */ -__syscall int mbox_send(const struct mbox_channel *channel, const struct mbox_msg *msg); +__syscall int mbox_send(const struct mbox_channel *channel, + const struct mbox_msg *msg); -static inline int z_impl_mbox_send(const struct mbox_channel *channel, const struct mbox_msg *msg) +static inline int z_impl_mbox_send(const struct mbox_channel *channel, + const struct mbox_msg *msg) { const struct mbox_driver_api *api = (const struct mbox_driver_api *)channel->dev->api; @@ -284,15 +268,16 @@ static inline int z_impl_mbox_send(const struct mbox_channel *channel, const str * @brief Register a callback function on a channel for incoming messages. * * This function doesn't assume anything concerning the status of the - * interrupts. Use @a mbox_set_enabled() to enable or to disable the interrupts + * interrupts. Use mbox_set_enabled() to enable or to disable the interrupts * if needed. * - * @param channel Channel instance pointer. + * @param channel MBOX channel instance * @param cb Callback function to execute on incoming message interrupts. * @param user_data Application-specific data pointer which will be passed - * to the callback function when executed. + * to the callback function when executed. * - * @retval 0 On success, negative value on error. + * @retval 0 On success. + * @retval -errno Negative errno on error. */ static inline int mbox_register_callback(const struct mbox_channel *channel, mbox_callback_t cb, @@ -319,13 +304,14 @@ static inline int mbox_register_callback(const struct mbox_channel *channel, * indirect way (i.e. probing some other peripheral, reading memory regions, * etc...). * - * If this function returns 0, the msg parameter in @a mbox_send() is expected + * If this function returns 0, the msg parameter in mbox_send() is expected * to be NULL. * - * @param dev Driver instance pointer. + * @param dev MBOX device instance. * - * @return Maximum possible size of a message in bytes, 0 for signalling, - * negative value on error. + * @retval >0 Maximum possible size of a message in bytes + * @retval 0 Indicates signalling + * @retval -errno Negative errno on error. */ __syscall int mbox_mtu_get(const struct device *dev); @@ -350,7 +336,7 @@ static inline int z_impl_mbox_mtu_get(const struct device *dev) * Immediately after calling this function with 'enable' set to true, the * channel is considered enabled and ready to receive signal and messages (even * already pending), so the user must take care of installing a proper callback - * (if needed) using @a mbox_register_callback() on the channel before enabling + * (if needed) using mbox_register_callback() on the channel before enabling * it. For this reason it is recommended that all the channels are disabled at * probe time. * @@ -358,15 +344,17 @@ static inline int z_impl_mbox_mtu_get(const struct device *dev) * undefined behavior (in general the driver must take care of gracefully * handling spurious interrupts with no installed callback). * - * @param channel Channel instance pointer. - * @param enable Set to 0 to disable and to nonzero to enable. + * @param channel MBOX channel instance + * @param enable Enable (true) or disable (false) the channel. * - * @retval 0 On success. - * @retval -EINVAL If it isn't an inbound channel. + * @retval 0 On success. + * @retval -EINVAL If it isn't an inbound channel. + * @retval -EALREADY If channel is already @p enable. */ __syscall int mbox_set_enabled(const struct mbox_channel *channel, bool enable); -static inline int z_impl_mbox_set_enabled(const struct mbox_channel *channel, bool enable) +static inline int z_impl_mbox_set_enabled(const struct mbox_channel *channel, + bool enable) { const struct mbox_driver_api *api = (const struct mbox_driver_api *)channel->dev->api; @@ -383,10 +371,10 @@ static inline int z_impl_mbox_set_enabled(const struct mbox_channel *channel, bo * * Return the maximum number of channels supported by the hardware. * - * @param dev Driver instance pointer. + * @param dev MBOX device instance. * - * @return Maximum possible number of supported channels on success, negative - * value on error. + * @return >0 Maximum possible number of supported channels on success + * @return -errno Negative errno on error. */ __syscall uint32_t mbox_max_channels_get(const struct device *dev); @@ -402,14 +390,12 @@ static inline uint32_t z_impl_mbox_max_channels_get(const struct device *dev) return api->max_channels_get(dev); } +/** @} */ + #ifdef __cplusplus } #endif -/** - * @} - */ - #include #endif /* ZEPHYR_INCLUDE_DRIVERS_MBOX_H_ */ From 459d2ef6a42ddbc9008315e60fd06193943bba85 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 12:27:44 +0100 Subject: [PATCH 0309/2402] drivers: mbox: add MBOX_DT_INST_CHANNEL_GET() So that we can improve API experience in instance-based code. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/drivers/mbox.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/zephyr/drivers/mbox.h b/include/zephyr/drivers/mbox.h index c50d8df4813..9ebb297e3c2 100644 --- a/include/zephyr/drivers/mbox.h +++ b/include/zephyr/drivers/mbox.h @@ -120,6 +120,17 @@ struct mbox_channel { .id = DT_MBOX_CHANNEL_BY_NAME(node_id, name), \ } +/** + * @brief Instance version of MBOX_DT_CHANNEL_GET() + * + * @param inst DT_DRV_COMPAT instance number + * @param name lowercase-and-underscores name of the mboxes element + * + * @return static initializer for a struct mbox_channel + */ +#define MBOX_DT_INST_CHANNEL_GET(inst, name) \ + MBOX_DT_CHANNEL_GET(DT_DRV_INST(inst), name) + /** @cond INTERNAL_HIDDEN */ /** From ad136ba38d32fbb9e82b0a2d05749d44d524c7bf Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 12:31:13 +0100 Subject: [PATCH 0310/2402] ipc: ipc_service: backends: use MBOX_DT_INST_CHANNEL_GET Instead of MBOX_DT_CHANNEL_GET(DT_DRV_INST(i), ...). Signed-off-by: Gerard Marull-Paretas --- subsys/ipc/ipc_service/backends/ipc_icbmsg.c | 4 ++-- subsys/ipc/ipc_service/backends/ipc_icmsg.c | 4 ++-- subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c | 4 ++-- subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c | 4 ++-- subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/subsys/ipc/ipc_service/backends/ipc_icbmsg.c b/subsys/ipc/ipc_service/backends/ipc_icbmsg.c index cb4d91d7e8a..928cedf0f38 100644 --- a/subsys/ipc/ipc_service/backends/ipc_icbmsg.c +++ b/subsys/ipc/ipc_service/backends/ipc_icbmsg.c @@ -1263,8 +1263,8 @@ const static struct ipc_service_backend backend_ops = { static const struct icbmsg_config backend_config_##i = \ { \ .control_config = { \ - .mbox_tx = MBOX_DT_CHANNEL_GET(DT_DRV_INST(i), tx), \ - .mbox_rx = MBOX_DT_CHANNEL_GET(DT_DRV_INST(i), rx), \ + .mbox_tx = MBOX_DT_INST_CHANNEL_GET(i, tx), \ + .mbox_rx = MBOX_DT_INST_CHANNEL_GET(i, rx), \ }, \ .tx = { \ .blocks_ptr = (uint8_t *)GET_BLOCKS_ADDR_INST(i, tx, rx), \ diff --git a/subsys/ipc/ipc_service/backends/ipc_icmsg.c b/subsys/ipc/ipc_service/backends/ipc_icmsg.c index 28b94b861e3..adda2c432c2 100644 --- a/subsys/ipc/ipc_service/backends/ipc_icmsg.c +++ b/subsys/ipc/ipc_service/backends/ipc_icmsg.c @@ -56,8 +56,8 @@ static int backend_init(const struct device *instance) #define DEFINE_BACKEND_DEVICE(i) \ static const struct icmsg_config_t backend_config_##i = { \ - .mbox_tx = MBOX_DT_CHANNEL_GET(DT_DRV_INST(i), tx), \ - .mbox_rx = MBOX_DT_CHANNEL_GET(DT_DRV_INST(i), rx), \ + .mbox_tx = MBOX_DT_INST_CHANNEL_GET(i, tx), \ + .mbox_rx = MBOX_DT_INST_CHANNEL_GET(i, rx), \ }; \ \ PBUF_DEFINE(tx_pb_##i, \ diff --git a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c index 5492da0a302..99f2c26139e 100644 --- a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c +++ b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c @@ -278,8 +278,8 @@ static int backend_init(const struct device *instance) #define DEFINE_BACKEND_DEVICE(i) \ static const struct icmsg_config_t backend_config_##i = { \ - .mbox_tx = MBOX_DT_CHANNEL_GET(DT_DRV_INST(i), tx), \ - .mbox_rx = MBOX_DT_CHANNEL_GET(DT_DRV_INST(i), rx), \ + .mbox_tx = MBOX_DT_INST_CHANNEL_GET(i, tx), \ + .mbox_rx = MBOX_DT_INST_CHANNEL_GET(i, rx), \ }; \ \ PBUF_DEFINE(tx_pb_##i, \ diff --git a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c index 2d537dc84a2..2a36c2e6b13 100644 --- a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c +++ b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c @@ -184,8 +184,8 @@ static int backend_init(const struct device *instance) #define DEFINE_BACKEND_DEVICE(i) \ static const struct icmsg_config_t backend_config_##i = { \ - .mbox_tx = MBOX_DT_CHANNEL_GET(DT_DRV_INST(i), tx), \ - .mbox_rx = MBOX_DT_CHANNEL_GET(DT_DRV_INST(i), rx), \ + .mbox_tx = MBOX_DT_INST_CHANNEL_GET(i, tx), \ + .mbox_rx = MBOX_DT_INST_CHANNEL_GET(i, rx), \ }; \ \ PBUF_DEFINE(tx_pb_##i, \ diff --git a/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c b/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c index b2bd408c7de..06a078dbd64 100644 --- a/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c +++ b/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c @@ -798,8 +798,8 @@ static int backend_init(const struct device *instance) .role = DT_ENUM_IDX_OR(DT_DRV_INST(i), role, ROLE_HOST), \ .shm_size = DT_REG_SIZE(DT_INST_PHANDLE(i, memory_region)), \ .shm_addr = BACKEND_SHM_ADDR(i), \ - .mbox_tx = MBOX_DT_CHANNEL_GET(DT_DRV_INST(i), tx), \ - .mbox_rx = MBOX_DT_CHANNEL_GET(DT_DRV_INST(i), rx), \ + .mbox_tx = MBOX_DT_INST_CHANNEL_GET(i, tx), \ + .mbox_rx = MBOX_DT_INST_CHANNEL_GET(i, rx), \ .wq_prio = COND_CODE_1(DT_INST_NODE_HAS_PROP(i, zephyr_priority), \ (DT_INST_PROP_BY_IDX(i, zephyr_priority, 0)), \ (0)), \ From 8be65b66085a3e74b89083828304ab7d8d8ddef5 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 13:20:41 +0100 Subject: [PATCH 0311/2402] drivers: mbox: refactor API This patch refactors the MBOX API, so that it aligns with some common Zephyr principles, main changes include: - There is now a non-DT specific API that takes a regular struct device and a channel identifier, instead of a struct that contains both. This API should be used for cases where DT is not an option. - There is a "dt-spec" variant of the API, meant to be used from devicetree specifications. Signed-off-by: Gerard Marull-Paretas --- drivers/mbox/mbox_handlers.c | 15 +-- include/zephyr/drivers/mbox.h | 183 ++++++++++++++++++++++++---------- 2 files changed, 138 insertions(+), 60 deletions(-) diff --git a/drivers/mbox/mbox_handlers.c b/drivers/mbox/mbox_handlers.c index c4e43f74fe5..c8788907d33 100644 --- a/drivers/mbox/mbox_handlers.c +++ b/drivers/mbox/mbox_handlers.c @@ -7,11 +7,11 @@ #include #include -static inline int z_vrfy_mbox_send(const struct mbox_channel *channel, +static inline int z_vrfy_mbox_send(const struct device *dev, + mbox_channel_id_t channel_id, const struct mbox_msg *msg) { - K_OOPS(K_SYSCALL_MEMORY_READ(channel, sizeof(struct mbox_channel))); - K_OOPS(K_SYSCALL_DRIVER_MBOX(channel->dev, send)); + K_OOPS(K_SYSCALL_DRIVER_MBOX(dev, send)); K_OOPS(K_SYSCALL_MEMORY_READ(msg, sizeof(struct mbox_msg))); K_OOPS(K_SYSCALL_MEMORY_READ(msg->data, msg->size)); @@ -35,11 +35,12 @@ static inline uint32_t z_vrfy_mbox_max_channels_get(const struct device *dev) } #include -static inline int z_vrfy_mbox_set_enabled(const struct mbox_channel *channel, bool enable) +static inline int z_vrfy_mbox_set_enabled(const struct device *dev, + mbox_channel_id_t channel_id, + bool enabled) { - K_OOPS(K_SYSCALL_MEMORY_READ(channel, sizeof(struct mbox_channel))); - K_OOPS(K_SYSCALL_DRIVER_MBOX(channel->dev, set_enabled)); + K_OOPS(K_SYSCALL_DRIVER_MBOX(dev, set_enabled)); - return z_impl_mbox_set_enabled(channel, enable); + return z_impl_mbox_set_enabled(channel_id, enabled); } #include diff --git a/include/zephyr/drivers/mbox.h b/include/zephyr/drivers/mbox.h index 9ebb297e3c2..654e3239ba9 100644 --- a/include/zephyr/drivers/mbox.h +++ b/include/zephyr/drivers/mbox.h @@ -70,6 +70,9 @@ extern "C" { * */ +/** @brief Type for MBOX channel identifiers */ +typedef uint32_t mbox_channel_id_t; + /** @brief Message struct (to hold data and its size). */ struct mbox_msg { /** Pointer to the data sent in the message. */ @@ -78,18 +81,18 @@ struct mbox_msg { size_t size; }; -/** @brief Provides a type to hold an MBOX channel */ -struct mbox_channel { +/** @brief MBOX specification from DT */ +struct mbox_dt_spec { /** MBOX device pointer. */ const struct device *dev; /** Channel ID. */ - uint32_t id; + mbox_channel_id_t channel_id; }; /** - * @brief Structure initializer for mbox_channel from devicetree + * @brief Structure initializer for struct mbox_dt_spec from devicetree * - * This helper macro expands to a static initializer for a struct mbox_channel + * This helper macro expands to a static initializer for a struct mbox_dt_spec * by reading the relevant device controller and channel number from the * devicetree. * @@ -106,18 +109,18 @@ struct mbox_channel { * Example usage: * * @code{.c} - * const struct mbox_channel channel = MBOX_DT_CHANNEL_GET(DT_NODELABEL(n), tx); + * const struct mbox_dt_spec spec = MBOX_DT_SPEC_GET(DT_NODELABEL(n), tx); * @endcode * * @param node_id Devicetree node identifier for the MBOX device * @param name lowercase-and-underscores name of the mboxes element * - * @return static initializer for a struct mbox_channel + * @return static initializer for a struct mbox_dt_spec */ -#define MBOX_DT_CHANNEL_GET(node_id, name) \ +#define MBOX_DT_SPEC_GET(node_id, name) \ { \ .dev = DEVICE_DT_GET(DT_MBOX_CTLR_BY_NAME(node_id, name)), \ - .id = DT_MBOX_CHANNEL_BY_NAME(node_id, name), \ + .channel_id = DT_MBOX_CHANNEL_BY_NAME(node_id, name), \ } /** @@ -126,10 +129,10 @@ struct mbox_channel { * @param inst DT_DRV_COMPAT instance number * @param name lowercase-and-underscores name of the mboxes element * - * @return static initializer for a struct mbox_channel + * @return static initializer for a struct mbox_dt_spec */ -#define MBOX_DT_INST_CHANNEL_GET(inst, name) \ - MBOX_DT_CHANNEL_GET(DT_DRV_INST(inst), name) +#define MBOX_DT_SPEC_INST_GET(inst, name) \ + MBOX_DT_SPEC_GET(DT_DRV_INST(inst), name) /** @cond INTERNAL_HIDDEN */ @@ -143,24 +146,26 @@ struct mbox_channel { * The data parameter must be NULL in signalling mode. * * @param dev MBOX device instance - * @param channel Channel ID + * @param channel_id Channel ID * @param user_data Pointer to some private data provided at registration time * @param data Message struct */ -typedef void (*mbox_callback_t)(const struct device *dev, uint32_t channel, - void *user_data, struct mbox_msg *data); +typedef void (*mbox_callback_t)(const struct device *dev, + mbox_channel_id_t channel_id, void *user_data, + struct mbox_msg *data); /** * @brief Callback API to send MBOX messages * * @param dev MBOX device instance - * @param channel Channel ID + * @param channel_id Channel ID * @param msg Message struct * * @return See the return values for mbox_send() * @see mbox_send() */ -typedef int (*mbox_send_t)(const struct device *dev, uint32_t channel, +typedef int (*mbox_send_t)(const struct device *dev, + mbox_channel_id_t channel_id, const struct mbox_msg *msg); /** @@ -177,7 +182,7 @@ typedef int (*mbox_mtu_get_t)(const struct device *dev); * @brief Callback API upon registration * * @param dev MBOX device instance - * @param channel Channel ID + * @param channel_id Channel ID * @param cb Callback function to execute on incoming message interrupts. * @param user_data Application-specific data pointer which will be passed to * the callback function when executed. @@ -186,21 +191,21 @@ typedef int (*mbox_mtu_get_t)(const struct device *dev); * @see mbox_register_callback() */ typedef int (*mbox_register_callback_t)(const struct device *dev, - uint32_t channel, - mbox_callback_t cb, - void *user_data); + mbox_channel_id_t channel_id, + mbox_callback_t cb, void *user_data); /** * @brief Callback API upon enablement of interrupts * * @param dev MBOX device instance - * @param channel Channel ID - * @param enable Set to 0 to disable and to nonzero to enable. + * @param channel_id Channel ID + * @param enables Set to 0 to disable and to nonzero to enable. * * @return See return values for mbox_set_enabled() * @see mbox_set_enabled() */ -typedef int (*mbox_set_enabled_t)(const struct device *dev, uint32_t channel, bool enable); +typedef int (*mbox_set_enabled_t)(const struct device *dev, + mbox_channel_id_t channel_id, bool enabled); /** * @brief Callback API to get maximum number of channels @@ -223,22 +228,15 @@ __subsystem struct mbox_driver_api { /** @endcond */ /** - * @brief Initialize a channel struct + * @brief Validate if MBOX device instance from a struct mbox_dt_spec is ready. * - * Initialize an struct mbox_channel passed by the user with a provided MBOX - * device and channel ID. This function is needed when the information about the - * device and the channel ID is not in the DT. In the DT case - * MBOX_DT_CHANNEL_GET() must be used instead. + * @param spec MBOX specification from devicetree * - * @param[out] channel MBOX channel instance - * @param dev MBOX device instance - * @param ch_id Channel ID + * @return See return values for mbox_send() */ -static inline void mbox_init_channel(struct mbox_channel *channel, - const struct device *dev, uint32_t ch_id) +static inline bool mbox_is_ready_dt(const struct mbox_dt_spec *spec) { - channel->dev = dev; - channel->id = ch_id; + return device_is_ready(spec->dev); } /** @@ -250,7 +248,8 @@ static inline void mbox_init_channel(struct mbox_channel *channel, * If the msg parameter is not NULL, this data is expected to be delivered on * the receiving side using the data parameter of the receiving callback. * - * @param channel MBOX channel instance + * @param dev MBOX device instance + * @param channel_id MBOX channel identifier * @param msg Message * * @retval 0 On success. @@ -259,20 +258,35 @@ static inline void mbox_init_channel(struct mbox_channel *channel, * @retval -EINVAL If there was a bad parameter, such as: too-large channel * descriptor or the device isn't an outbound MBOX channel. */ -__syscall int mbox_send(const struct mbox_channel *channel, +__syscall int mbox_send(const struct device *dev, mbox_channel_id_t channel_id, const struct mbox_msg *msg); -static inline int z_impl_mbox_send(const struct mbox_channel *channel, +static inline int z_impl_mbox_send(const struct device *dev, + mbox_channel_id_t channel_id, const struct mbox_msg *msg) { const struct mbox_driver_api *api = - (const struct mbox_driver_api *)channel->dev->api; + (const struct mbox_driver_api *)dev->api; if (api->send == NULL) { return -ENOSYS; } - return api->send(channel->dev, channel->id, msg); + return api->send(dev, channel_id, msg); +} + +/** + * @brief Try to send a message over the MBOX device from a struct mbox_dt_spec. + * + * @param spec MBOX specification from devicetree + * @param msg Message + * + * @return See return values for mbox_send() + */ +static inline int mbox_send_dt(const struct mbox_dt_spec *spec, + const struct mbox_msg *msg) +{ + return mbox_send(spec->dev, spec->channel_id, msg); } /** @@ -282,7 +296,8 @@ static inline int z_impl_mbox_send(const struct mbox_channel *channel, * interrupts. Use mbox_set_enabled() to enable or to disable the interrupts * if needed. * - * @param channel MBOX channel instance + * @param dev MBOX device instance + * @param channel_id MBOX channel identifier * @param cb Callback function to execute on incoming message interrupts. * @param user_data Application-specific data pointer which will be passed * to the callback function when executed. @@ -290,18 +305,37 @@ static inline int z_impl_mbox_send(const struct mbox_channel *channel, * @retval 0 On success. * @retval -errno Negative errno on error. */ -static inline int mbox_register_callback(const struct mbox_channel *channel, +static inline int mbox_register_callback(const struct device *dev, + mbox_channel_id_t channel_id, mbox_callback_t cb, void *user_data) { const struct mbox_driver_api *api = - (const struct mbox_driver_api *)channel->dev->api; + (const struct mbox_driver_api *)dev->api; if (api->register_callback == NULL) { return -ENOSYS; } - return api->register_callback(channel->dev, channel->id, cb, user_data); + return api->register_callback(dev, channel_id, cb, user_data); +} + +/** + * @brief Register a callback function on a channel for incoming messages from a + * struct mbox_dt_spec. + * + * @param spec MBOX specification from devicetree + * @param cb Callback function to execute on incoming message interrupts. + * @param user_data Application-specific data pointer which will be passed + * to the callback function when executed. + * + * @return See return values for mbox_register_callback() + */ +static inline int mbox_register_callback_dt(const struct mbox_dt_spec *spec, + mbox_callback_t cb, void *user_data) +{ + return mbox_register_callback(spec->dev, spec->channel_id, cb, + user_data); } /** @@ -338,6 +372,19 @@ static inline int z_impl_mbox_mtu_get(const struct device *dev) return api->mtu_get(dev); } +/** + * @brief Return the maximum number of bytes possible in an outbound message + * from struct mbox_dt_spec. + * + * @param spec MBOX specification from devicetree + * + * @return See return values for mbox_register_callback() + */ +static inline int mbox_mtu_get_dt(const struct mbox_dt_spec *spec) +{ + return mbox_mtu_get(spec->dev); +} + /** * @brief Enable (disable) interrupts and callbacks for inbound channels. * @@ -355,26 +402,44 @@ static inline int z_impl_mbox_mtu_get(const struct device *dev) * undefined behavior (in general the driver must take care of gracefully * handling spurious interrupts with no installed callback). * - * @param channel MBOX channel instance - * @param enable Enable (true) or disable (false) the channel. + * @param dev MBOX device instance + * @param channel_id MBOX channel identifier + * @param enabled Enable (true) or disable (false) the channel. * * @retval 0 On success. * @retval -EINVAL If it isn't an inbound channel. - * @retval -EALREADY If channel is already @p enable. + * @retval -EALREADY If channel is already @p enabled. */ -__syscall int mbox_set_enabled(const struct mbox_channel *channel, bool enable); +__syscall int mbox_set_enabled(const struct device *dev, + mbox_channel_id_t channel_id, bool enabled); -static inline int z_impl_mbox_set_enabled(const struct mbox_channel *channel, - bool enable) +static inline int z_impl_mbox_set_enabled(const struct device *dev, + mbox_channel_id_t channel_id, + bool enabled) { const struct mbox_driver_api *api = - (const struct mbox_driver_api *)channel->dev->api; + (const struct mbox_driver_api *)dev->api; if (api->set_enabled == NULL) { return -ENOSYS; } - return api->set_enabled(channel->dev, channel->id, enable); + return api->set_enabled(dev, channel_id, enabled); +} + +/** + * @brief Enable (disable) interrupts and callbacks for inbound channels from a + * struct mbox_dt_spec. + * + * @param spec MBOX specification from devicetree + * @param enabled Enable (true) or disable (false) the channel. + * + * @return See return values for mbox_set_enabled() + */ +static inline int mbox_set_enabled_dt(const struct mbox_dt_spec *spec, + bool enabled) +{ + return mbox_set_enabled(spec->dev, spec->channel_id, enabled); } /** @@ -401,6 +466,18 @@ static inline uint32_t z_impl_mbox_max_channels_get(const struct device *dev) return api->max_channels_get(dev); } +/** + * @brief Return the maximum number of channels from a struct mbox_dt_spec. + * + * @param spec MBOX specification from devicetree + * + * @return See return values for mbox_max_channels_get() + */ +static inline int mbox_max_channels_get_dt(const struct mbox_dt_spec *spec) +{ + return mbox_max_channels_get(spec->dev); +} + /** @} */ #ifdef __cplusplus From 80cc7d1ee5b5e9a3309a7de007174680ac4d1f50 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 23 Feb 2024 13:23:10 +0100 Subject: [PATCH 0312/2402] drivers: mbox: update MBOX consumers to the new API Update all usages of the MBOX API to the latest API changes (to be squashed for bisectability). Signed-off-by: Gerard Marull-Paretas --- drivers/ethernet/eth_nxp_s32_netc.c | 10 ++--- drivers/ethernet/eth_nxp_s32_netc_priv.h | 4 +- drivers/ethernet/eth_nxp_s32_netc_psi.c | 7 ++-- drivers/ethernet/eth_nxp_s32_netc_vsi.c | 7 ++-- include/zephyr/ipc/icmsg.h | 4 +- .../boards/nrf/nrf53_sync_rtc/net/src/main.c | 7 +--- samples/drivers/mbox/remote/src/main.c | 23 +++++------ samples/drivers/mbox/src/main.c | 23 +++++------ samples/drivers/mbox_data/remote/src/main.c | 22 +++++----- samples/drivers/mbox_data/src/main.c | 22 +++++----- soc/nordic/nrf53/sync_rtc.c | 13 ++---- subsys/ipc/ipc_service/backends/ipc_icbmsg.c | 4 +- subsys/ipc/ipc_service/backends/ipc_icmsg.c | 4 +- .../backends/ipc_icmsg_me_follower.c | 4 +- .../backends/ipc_icmsg_me_initiator.c | 4 +- .../backends/ipc_rpmsg_static_vrings.c | 16 ++++---- subsys/ipc/ipc_service/lib/icmsg.c | 12 +++--- .../drivers/mbox/mbox_data/remote/src/main.c | 32 +++++++-------- tests/drivers/mbox/mbox_data/src/main.c | 40 ++++++++++--------- tests/lib/devicetree/api/src/main.c | 12 +++--- 20 files changed, 128 insertions(+), 142 deletions(-) diff --git a/drivers/ethernet/eth_nxp_s32_netc.c b/drivers/ethernet/eth_nxp_s32_netc.c index f5a3994a9c4..d7679564bce 100644 --- a/drivers/ethernet/eth_nxp_s32_netc.c +++ b/drivers/ethernet/eth_nxp_s32_netc.c @@ -81,13 +81,13 @@ int nxp_s32_eth_initialize_common(const struct device *dev) for (int i = 0; i < NETC_MSIX_EVENTS_COUNT; i++) { msix = &cfg->msix[i]; - if (msix->mbox_channel.dev != NULL) { - err = mbox_register_callback(&msix->mbox_channel, - nxp_s32_eth_msix_wrapper, - (void *)msix); + if (mbox_is_ready_dt(&msix->mbox_spec)) { + err = mbox_register_callback_dt(&msix->mbox_spec, + nxp_s32_eth_msix_wrapper, + (void *)msix); if (err != 0) { LOG_ERR("Failed to register MRU callback on channel %u", - msix->mbox_channel.id); + msix->mbox_spec.channel_id); return err; } } diff --git a/drivers/ethernet/eth_nxp_s32_netc_priv.h b/drivers/ethernet/eth_nxp_s32_netc_priv.h index 4a3496ee58b..b429233b694 100644 --- a/drivers/ethernet/eth_nxp_s32_netc_priv.h +++ b/drivers/ethernet/eth_nxp_s32_netc_priv.h @@ -44,7 +44,7 @@ #define NETC_MSIX(node, name, cb) \ { \ .handler = cb, \ - .mbox_channel = MBOX_DT_CHANNEL_GET(node, name), \ + .mbox_spec = MBOX_DT_SPEC_GET(node, name), \ } /* Tx/Rx ENETC ring definitions */ @@ -100,7 +100,7 @@ struct nxp_s32_eth_msix { void (*handler)(uint8_t chan, const uint32_t *buf, uint8_t buf_size); - struct mbox_channel mbox_channel; + struct mbox_dt_spec mbox_spec; }; struct nxp_s32_eth_config { diff --git a/drivers/ethernet/eth_nxp_s32_netc_psi.c b/drivers/ethernet/eth_nxp_s32_netc_psi.c index 977825ddd7a..465349703ab 100644 --- a/drivers/ethernet/eth_nxp_s32_netc_psi.c +++ b/drivers/ethernet/eth_nxp_s32_netc_psi.c @@ -197,9 +197,10 @@ static void nxp_s32_eth_iface_init(struct net_if *iface) for (int i = 0; i < NETC_MSIX_EVENTS_COUNT; i++) { msix = &cfg->msix[i]; - if (msix->mbox_channel.dev != NULL) { - if (mbox_set_enabled(&msix->mbox_channel, true)) { - LOG_ERR("Failed to enable MRU channel %u", msix->mbox_channel.id); + if (mbox_is_ready_dt(&msix->mbox_spec)) { + if (mbox_set_enabled_dt(&msix->mbox_spec, true)) { + LOG_ERR("Failed to enable MRU channel %u", + msix->mbox_spec.channel_id); } } } diff --git a/drivers/ethernet/eth_nxp_s32_netc_vsi.c b/drivers/ethernet/eth_nxp_s32_netc_vsi.c index 0847db8148c..d4fb06c96da 100644 --- a/drivers/ethernet/eth_nxp_s32_netc_vsi.c +++ b/drivers/ethernet/eth_nxp_s32_netc_vsi.c @@ -66,9 +66,10 @@ static void nxp_s32_eth_iface_init(struct net_if *iface) for (int i = 0; i < NETC_MSIX_EVENTS_COUNT; i++) { msix = &cfg->msix[i]; - if (msix->mbox_channel.dev != NULL) { - if (mbox_set_enabled(&msix->mbox_channel, true)) { - LOG_ERR("Failed to enable MRU channel %u", msix->mbox_channel.id); + if (mbox_is_ready_dt(&msix->mbox_spec)) { + if (mbox_set_enabled_dt(&msix->mbox_spec, true)) { + LOG_ERR("Failed to enable MRU channel %u", + msix->mbox_spec.channel_id); } } } diff --git a/include/zephyr/ipc/icmsg.h b/include/zephyr/ipc/icmsg.h index a3b43690cc4..3bc03804ca8 100644 --- a/include/zephyr/ipc/icmsg.h +++ b/include/zephyr/ipc/icmsg.h @@ -33,8 +33,8 @@ enum icmsg_state { }; struct icmsg_config_t { - struct mbox_channel mbox_tx; - struct mbox_channel mbox_rx; + struct mbox_dt_spec mbox_tx; + struct mbox_dt_spec mbox_rx; }; struct icmsg_data_t { diff --git a/samples/boards/nrf/nrf53_sync_rtc/net/src/main.c b/samples/boards/nrf/nrf53_sync_rtc/net/src/main.c index 17cf5cb67ea..1119aa46e85 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/net/src/main.c +++ b/samples/boards/nrf/nrf53_sync_rtc/net/src/main.c @@ -42,7 +42,6 @@ static void mbox_callback(const struct device *dev, uint32_t channel, static int mbox_init(void) { const struct device *dev; - struct mbox_channel channel; int err; dev = COND_CODE_1(CONFIG_MBOX, (DEVICE_DT_GET(DT_NODELABEL(mbox))), (NULL)); @@ -50,14 +49,12 @@ static int mbox_init(void) return -ENODEV; } - mbox_init_channel(&channel, dev, 2); - - err = mbox_register_callback(&channel, mbox_callback, NULL); + err = mbox_register_callback(dev, 2, mbox_callback, NULL); if (err < 0) { return err; } - return mbox_set_enabled(&channel, true); + return mbox_set_enabled(dev, 2, true); } int main(void) diff --git a/samples/drivers/mbox/remote/src/main.c b/samples/drivers/mbox/remote/src/main.c index 30ac421b885..9fe6c1a79d5 100644 --- a/samples/drivers/mbox/remote/src/main.c +++ b/samples/drivers/mbox/remote/src/main.c @@ -13,47 +13,42 @@ #endif #ifdef CONFIG_RX_ENABLED -static void callback(const struct device *dev, uint32_t channel, +static void callback(const struct device *dev, mbox_channel_id_t channel_id, void *user_data, struct mbox_msg *data) { - printk("Pong (on channel %d)\n", channel); + printk("Pong (on channel %d)\n", channel_id); } #endif /* CONFIG_RX_ENABLED */ int main(void) { int ret; - const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); printk("Hello from REMOTE\n"); #ifdef CONFIG_RX_ENABLED - const struct mbox_channel rx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx); + const struct mbox_dt_spec rx_channel = MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx); - mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); - - ret = mbox_register_callback(&rx_channel, callback, NULL); + ret = mbox_register_callback_dt(&rx_channel, callback, NULL); if (ret < 0) { printk("Could not register callback (%d)\n", ret); return 0; } - ret = mbox_set_enabled(&rx_channel, true); + ret = mbox_set_enabled_dt(&rx_channel, true); if (ret < 0) { - printk("Could not enable RX channel %d (%d)\n", rx_channel.id, ret); + printk("Could not enable RX channel %d (%d)\n", rx_channel.channel_id, ret); return 0; } #endif /* CONFIG_RX_ENABLED */ #ifdef CONFIG_TX_ENABLED - const struct mbox_channel tx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx); - - mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); + const struct mbox_dt_spec tx_channel = MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx); while (1) { - printk("Ping (on channel %d)\n", tx_channel.id); + printk("Ping (on channel %d)\n", tx_channel.channel_id); - ret = mbox_send(&tx_channel, NULL); + ret = mbox_send_dt(&tx_channel, NULL); if (ret < 0) { printk("Could not send (%d)\n", ret); return 0; diff --git a/samples/drivers/mbox/src/main.c b/samples/drivers/mbox/src/main.c index aa6fbbf5d45..221d7bd474f 100644 --- a/samples/drivers/mbox/src/main.c +++ b/samples/drivers/mbox/src/main.c @@ -9,49 +9,44 @@ #include #ifdef CONFIG_RX_ENABLED -static void callback(const struct device *dev, uint32_t channel, +static void callback(const struct device *dev, mbox_channel_id_t channel_id, void *user_data, struct mbox_msg *data) { - printk("Pong (on channel %d)\n", channel); + printk("Pong (on channel %d)\n", channel_id); } #endif /* CONFIG_RX_ENABLED */ int main(void) { int ret; - const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); printk("Hello from APP\n"); #ifdef CONFIG_RX_ENABLED - const struct mbox_channel rx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx); + const struct mbox_dt_spec rx_channel = MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx); - mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); - - ret = mbox_register_callback(&rx_channel, callback, NULL); + ret = mbox_register_callback_dt(&rx_channel, callback, NULL); if (ret < 0) { printk("Could not register callback (%d)\n", ret); return 0; } - ret = mbox_set_enabled(&rx_channel, true); + ret = mbox_set_enabled_dt(&rx_channel, true); if (ret < 0) { - printk("Could not enable RX channel %d (%d)\n", rx_channel.id, ret); + printk("Could not enable RX channel %d (%d)\n", rx_channel.channel_id, ret); return 0; } #endif /* CONFIG_RX_ENABLED */ #ifdef CONFIG_TX_ENABLED - const struct mbox_channel tx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx); - - mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); + const struct mbox_dt_spec tx_channel = MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx); while (1) { k_sleep(K_MSEC(2000)); - printk("Ping (on channel %d)\n", tx_channel.id); + printk("Ping (on channel %d)\n", tx_channel.channel_id); - ret = mbox_send(&tx_channel, NULL); + ret = mbox_send_dt(&tx_channel, NULL); if (ret < 0) { printk("Could not send (%d)\n", ret); return 0; diff --git a/samples/drivers/mbox_data/remote/src/main.c b/samples/drivers/mbox_data/remote/src/main.c index bb73fabbbc1..ae45f26d126 100644 --- a/samples/drivers/mbox_data/remote/src/main.c +++ b/samples/drivers/mbox_data/remote/src/main.c @@ -12,40 +12,40 @@ static K_SEM_DEFINE(g_mbox_data_rx_sem, 0, 1); -static uint32_t g_mbox_received_data; -static uint32_t g_mbox_received_channel; +static mbox_channel_id_t g_mbox_received_data; +static mbox_channel_id_t g_mbox_received_channel; -static void callback(const struct device *dev, uint32_t channel, void *user_data, +static void callback(const struct device *dev, mbox_channel_id_t channel_id, void *user_data, struct mbox_msg *data) { memcpy(&g_mbox_received_data, data->data, data->size); - g_mbox_received_channel = channel; + g_mbox_received_channel = channel_id; k_sem_give(&g_mbox_data_rx_sem); } int main(void) { - const struct mbox_channel tx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx); - const struct mbox_channel rx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx); + const struct mbox_dt_spec tx_channel = MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx); + const struct mbox_dt_spec rx_channel = MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx); struct mbox_msg msg = {0}; uint32_t message = 0; printk("mbox_data Server demo started\n"); - const int max_transfer_size_bytes = mbox_mtu_get(tx_channel.dev); + const int max_transfer_size_bytes = mbox_mtu_get_dt(&tx_channel); /* Sample currently supports only transfer size up to 4 bytes */ if ((max_transfer_size_bytes <= 0) || (max_transfer_size_bytes > 4)) { printk("mbox_mtu_get() error\n"); return 0; } - if (mbox_register_callback(&rx_channel, callback, NULL)) { + if (mbox_register_callback_dt(&rx_channel, callback, NULL)) { printk("mbox_register_callback() error\n"); return 0; } - if (mbox_set_enabled(&rx_channel, 1)) { + if (mbox_set_enabled_dt(&rx_channel, 1)) { printk("mbox_set_enable() error\n"); return 0; } @@ -62,8 +62,8 @@ int main(void) msg.data = &message; msg.size = max_transfer_size_bytes; - printk("Server send (on channel %d) value: %d\n", tx_channel.id, message); - if (mbox_send(&tx_channel, &msg) < 0) { + printk("Server send (on channel %d) value: %d\n", tx_channel.channel_id, message); + if (mbox_send_dt(&tx_channel, &msg) < 0) { printk("mbox_send() error\n"); return 0; } diff --git a/samples/drivers/mbox_data/src/main.c b/samples/drivers/mbox_data/src/main.c index b6520418484..9699b20bb0c 100644 --- a/samples/drivers/mbox_data/src/main.c +++ b/samples/drivers/mbox_data/src/main.c @@ -12,40 +12,40 @@ static K_SEM_DEFINE(g_mbox_data_rx_sem, 0, 1); -static uint32_t g_mbox_received_data; -static uint32_t g_mbox_received_channel; +static mbox_channel_id_t g_mbox_received_data; +static mbox_channel_id_t g_mbox_received_channel; -static void callback(const struct device *dev, uint32_t channel, void *user_data, +static void callback(const struct device *dev, mbox_channel_id_t channel_id, void *user_data, struct mbox_msg *data) { memcpy(&g_mbox_received_data, data->data, data->size); - g_mbox_received_channel = channel; + g_mbox_received_channel = channel_id; k_sem_give(&g_mbox_data_rx_sem); } int main(void) { - const struct mbox_channel tx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx); - const struct mbox_channel rx_channel = MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx); + const struct mbox_dt_spec tx_channel = MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx); + const struct mbox_dt_spec rx_channel = MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx); struct mbox_msg msg = {0}; uint32_t message = 0; printk("mbox_data Client demo started\n"); - const int max_transfer_size_bytes = mbox_mtu_get(tx_channel.dev); + const int max_transfer_size_bytes = mbox_mtu_get_dt(&tx_channel); /* Sample currently supports only transfer size up to 4 bytes */ if ((max_transfer_size_bytes < 0) || (max_transfer_size_bytes > 4)) { printk("mbox_mtu_get() error\n"); return 0; } - if (mbox_register_callback(&rx_channel, callback, NULL)) { + if (mbox_register_callback_dt(&rx_channel, callback, NULL)) { printk("mbox_register_callback() error\n"); return 0; } - if (mbox_set_enabled(&rx_channel, 1)) { + if (mbox_set_enabled_dt(&rx_channel, 1)) { printk("mbox_set_enable() error\n"); return 0; } @@ -54,8 +54,8 @@ int main(void) msg.data = &message; msg.size = max_transfer_size_bytes; - printk("Client send (on channel %d) value: %d\n", tx_channel.id, message); - if (mbox_send(&tx_channel, &msg) < 0) { + printk("Client send (on channel %d) value: %d\n", tx_channel.channel_id, message); + if (mbox_send_dt(&tx_channel, &msg) < 0) { printk("mbox_send() error\n"); return 0; } diff --git a/soc/nordic/nrf53/sync_rtc.c b/soc/nordic/nrf53/sync_rtc.c index 031f93244f7..94616ee3a0c 100644 --- a/soc/nordic/nrf53/sync_rtc.c +++ b/soc/nordic/nrf53/sync_rtc.c @@ -190,14 +190,12 @@ static void remote_callback(void *user_data) } } -static void mbox_callback(const struct device *dev, uint32_t channel, +static void mbox_callback(const struct device *dev, mbox_channel_id_t channel_id, void *user_data, struct mbox_msg *data) { - struct mbox_channel ch; int err; - mbox_init_channel(&ch, dev, channel); - err = mbox_set_enabled(&ch, false); + err = mbox_set_enabled(dev, channel_id, false); (void)err; __ASSERT_NO_MSG(err == 0); @@ -208,7 +206,6 @@ static void mbox_callback(const struct device *dev, uint32_t channel, static int mbox_rx_init(void *user_data) { const struct device *dev; - struct mbox_channel channel; int err; dev = COND_CODE_1(CONFIG_MBOX, (DEVICE_DT_GET(DT_NODELABEL(mbox))), (NULL)); @@ -216,14 +213,12 @@ static int mbox_rx_init(void *user_data) return -ENODEV; } - mbox_init_channel(&channel, dev, CONFIG_NRF53_SYNC_RTC_IPM_IN); - - err = mbox_register_callback(&channel, mbox_callback, user_data); + err = mbox_register_callback(dev, CONFIG_NRF53_SYNC_RTC_IPM_IN, mbox_callback, user_data); if (err < 0) { return err; } - return mbox_set_enabled(&channel, true); + return mbox_set_enabled(dev, CONFIG_NRF53_SYNC_RTC_IPM_IN, true); } /* Setup RTC synchronization. */ diff --git a/subsys/ipc/ipc_service/backends/ipc_icbmsg.c b/subsys/ipc/ipc_service/backends/ipc_icbmsg.c index 928cedf0f38..da2db4ccbc8 100644 --- a/subsys/ipc/ipc_service/backends/ipc_icbmsg.c +++ b/subsys/ipc/ipc_service/backends/ipc_icbmsg.c @@ -1263,8 +1263,8 @@ const static struct ipc_service_backend backend_ops = { static const struct icbmsg_config backend_config_##i = \ { \ .control_config = { \ - .mbox_tx = MBOX_DT_INST_CHANNEL_GET(i, tx), \ - .mbox_rx = MBOX_DT_INST_CHANNEL_GET(i, rx), \ + .mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx), \ + .mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx), \ }, \ .tx = { \ .blocks_ptr = (uint8_t *)GET_BLOCKS_ADDR_INST(i, tx, rx), \ diff --git a/subsys/ipc/ipc_service/backends/ipc_icmsg.c b/subsys/ipc/ipc_service/backends/ipc_icmsg.c index adda2c432c2..40cc06b8a6f 100644 --- a/subsys/ipc/ipc_service/backends/ipc_icmsg.c +++ b/subsys/ipc/ipc_service/backends/ipc_icmsg.c @@ -56,8 +56,8 @@ static int backend_init(const struct device *instance) #define DEFINE_BACKEND_DEVICE(i) \ static const struct icmsg_config_t backend_config_##i = { \ - .mbox_tx = MBOX_DT_INST_CHANNEL_GET(i, tx), \ - .mbox_rx = MBOX_DT_INST_CHANNEL_GET(i, rx), \ + .mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx), \ + .mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx), \ }; \ \ PBUF_DEFINE(tx_pb_##i, \ diff --git a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c index 99f2c26139e..cc374b31f57 100644 --- a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c +++ b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c @@ -278,8 +278,8 @@ static int backend_init(const struct device *instance) #define DEFINE_BACKEND_DEVICE(i) \ static const struct icmsg_config_t backend_config_##i = { \ - .mbox_tx = MBOX_DT_INST_CHANNEL_GET(i, tx), \ - .mbox_rx = MBOX_DT_INST_CHANNEL_GET(i, rx), \ + .mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx), \ + .mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx), \ }; \ \ PBUF_DEFINE(tx_pb_##i, \ diff --git a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c index 2a36c2e6b13..28170f909ec 100644 --- a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c +++ b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c @@ -184,8 +184,8 @@ static int backend_init(const struct device *instance) #define DEFINE_BACKEND_DEVICE(i) \ static const struct icmsg_config_t backend_config_##i = { \ - .mbox_tx = MBOX_DT_INST_CHANNEL_GET(i, tx), \ - .mbox_rx = MBOX_DT_INST_CHANNEL_GET(i, rx), \ + .mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx), \ + .mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx), \ }; \ \ PBUF_DEFINE(tx_pb_##i, \ diff --git a/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c b/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c index 06a078dbd64..6c8f1a72eaf 100644 --- a/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c +++ b/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c @@ -55,8 +55,8 @@ struct backend_config_t { unsigned int role; uintptr_t shm_addr; size_t shm_size; - struct mbox_channel mbox_tx; - struct mbox_channel mbox_rx; + struct mbox_dt_spec mbox_tx; + struct mbox_dt_spec mbox_rx; unsigned int wq_prio_type; unsigned int wq_prio; unsigned int id; @@ -292,7 +292,7 @@ static void virtio_notify_cb(struct virtqueue *vq, void *priv) struct backend_config_t *conf = priv; if (conf->mbox_tx.dev) { - mbox_send(&conf->mbox_tx, NULL); + mbox_send_dt(&conf->mbox_tx, NULL); } } @@ -329,12 +329,12 @@ static int mbox_init(const struct device *instance) k_work_init(&data->mbox_work, mbox_callback_process); - err = mbox_register_callback(&conf->mbox_rx, mbox_callback, data); + err = mbox_register_callback_dt(&conf->mbox_rx, mbox_callback, data); if (err != 0) { return err; } - return mbox_set_enabled(&conf->mbox_rx, 1); + return mbox_set_enabled_dt(&conf->mbox_rx, 1); } static int mbox_deinit(const struct device *instance) @@ -344,7 +344,7 @@ static int mbox_deinit(const struct device *instance) k_tid_t wq_thread; int err; - err = mbox_set_enabled(&conf->mbox_rx, 0); + err = mbox_set_enabled_dt(&conf->mbox_rx, 0); if (err != 0) { return err; } @@ -798,8 +798,8 @@ static int backend_init(const struct device *instance) .role = DT_ENUM_IDX_OR(DT_DRV_INST(i), role, ROLE_HOST), \ .shm_size = DT_REG_SIZE(DT_INST_PHANDLE(i, memory_region)), \ .shm_addr = BACKEND_SHM_ADDR(i), \ - .mbox_tx = MBOX_DT_INST_CHANNEL_GET(i, tx), \ - .mbox_rx = MBOX_DT_INST_CHANNEL_GET(i, rx), \ + .mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx), \ + .mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx), \ .wq_prio = COND_CODE_1(DT_INST_NODE_HAS_PROP(i, zephyr_priority), \ (DT_INST_PROP_BY_IDX(i, zephyr_priority, 0)), \ (0)), \ diff --git a/subsys/ipc/ipc_service/lib/icmsg.c b/subsys/ipc/ipc_service/lib/icmsg.c index 52e2dd10f1b..61fa03689f4 100644 --- a/subsys/ipc/ipc_service/lib/icmsg.c +++ b/subsys/ipc/ipc_service/lib/icmsg.c @@ -32,12 +32,12 @@ static int mbox_deinit(const struct icmsg_config_t *conf, { int err; - err = mbox_set_enabled(&conf->mbox_rx, 0); + err = mbox_set_enabled_dt(&conf->mbox_rx, 0); if (err != 0) { return err; } - err = mbox_register_callback(&conf->mbox_rx, NULL, NULL); + err = mbox_register_callback_dt(&conf->mbox_rx, NULL, NULL); if (err != 0) { return err; } @@ -54,7 +54,7 @@ static void notify_process(struct k_work *item) struct icmsg_data_t *dev_data = CONTAINER_OF(dwork, struct icmsg_data_t, notify_work); - (void)mbox_send(&dev_data->cfg->mbox_tx, NULL); + (void)mbox_send_dt(&dev_data->cfg->mbox_tx, NULL); atomic_t state = atomic_get(&dev_data->state); @@ -181,12 +181,12 @@ static int mbox_init(const struct icmsg_config_t *conf, k_work_init(&dev_data->mbox_work, mbox_callback_process); k_work_init_delayable(&dev_data->notify_work, notify_process); - err = mbox_register_callback(&conf->mbox_rx, mbox_callback, dev_data); + err = mbox_register_callback_dt(&conf->mbox_rx, mbox_callback, dev_data); if (err != 0) { return err; } - return mbox_set_enabled(&conf->mbox_rx, 1); + return mbox_set_enabled_dt(&conf->mbox_rx, 1); } int icmsg_open(const struct icmsg_config_t *conf, @@ -293,7 +293,7 @@ int icmsg_send(const struct icmsg_config_t *conf, __ASSERT_NO_MSG(conf->mbox_tx.dev != NULL); - ret = mbox_send(&conf->mbox_tx, NULL); + ret = mbox_send_dt(&conf->mbox_tx, NULL); if (ret) { return ret; } diff --git a/tests/drivers/mbox/mbox_data/remote/src/main.c b/tests/drivers/mbox/mbox_data/remote/src/main.c index 661a48a2a8f..e44ecd7cc5e 100644 --- a/tests/drivers/mbox/mbox_data/remote/src/main.c +++ b/tests/drivers/mbox/mbox_data/remote/src/main.c @@ -19,22 +19,22 @@ static uint32_t g_mbox_received_channel; #define TX_CHANNEL_INDEX 0 #define RX_CHANNEL_INDEX 1 -static const struct mbox_channel channels[CHANNELS_TO_TEST][2] = { +static const struct mbox_dt_spec channels[CHANNELS_TO_TEST][2] = { { - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx0), - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx0), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx0), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx0), }, { - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx1), - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx1), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx1), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx1), }, { - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx2), - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx2), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx2), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx2), }, { - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx3), - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx3), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx3), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx3), }, }; @@ -55,22 +55,22 @@ int main(void) uint32_t message = 0; for (int i = 0; i < ARRAY_SIZE(channels); i++) { - const struct mbox_channel *tx_channel = &channels[i][TX_CHANNEL_INDEX]; - const struct mbox_channel *rx_channel = &channels[i][RX_CHANNEL_INDEX]; + const struct mbox_dt_spec *tx_channel = &channels[i][TX_CHANNEL_INDEX]; + const struct mbox_dt_spec *rx_channel = &channels[i][RX_CHANNEL_INDEX]; - const int max_transfer_size_bytes = mbox_mtu_get(tx_channel->dev); + const int max_transfer_size_bytes = mbox_mtu_get_dt(tx_channel); /* Sample currently supports only transfer size up to 4 bytes */ if ((max_transfer_size_bytes <= 0) || (max_transfer_size_bytes > 4)) { printk("mbox_mtu_get() error\n"); return 0; } - if (mbox_register_callback(rx_channel, callback, NULL)) { + if (mbox_register_callback_dt(rx_channel, callback, NULL)) { printk("mbox_register_callback() error\n"); return 0; } - if (mbox_set_enabled(rx_channel, 1)) { + if (mbox_set_enabled_dt(rx_channel, 1)) { printk("mbox_set_enable() error\n"); return 0; } @@ -88,13 +88,13 @@ int main(void) msg.data = &message; msg.size = max_transfer_size_bytes; - if (mbox_send(tx_channel, &msg) < 0) { + if (mbox_send_dt(tx_channel, &msg) < 0) { printk("mbox_send() error\n"); return 0; } } /* Disable current rx channel after channel loop */ - mbox_set_enabled(rx_channel, 0); + mbox_set_enabled_dt(rx_channel, 0); } } diff --git a/tests/drivers/mbox/mbox_data/src/main.c b/tests/drivers/mbox/mbox_data/src/main.c index 9a50e158664..461d01ed835 100644 --- a/tests/drivers/mbox/mbox_data/src/main.c +++ b/tests/drivers/mbox/mbox_data/src/main.c @@ -27,22 +27,22 @@ static int g_max_transfer_size_bytes; #define TX_CHANNEL_INDEX 0 #define RX_CHANNEL_INDEX 1 -static const struct mbox_channel channels[CHANNELS_TO_TEST][2] = { +static const struct mbox_dt_spec channels[CHANNELS_TO_TEST][2] = { { - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx0), - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx0), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx0), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx0), }, { - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx1), - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx1), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx1), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx1), }, { - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx2), - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx2), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx2), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx2), }, { - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), tx3), - MBOX_DT_CHANNEL_GET(DT_PATH(mbox_consumer), rx3), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), tx3), + MBOX_DT_SPEC_GET(DT_PATH(mbox_consumer), rx3), }, }; @@ -68,11 +68,11 @@ static void mbox_data_tests_before(void *f) { zassert_false(current_channel_index >= CHANNELS_TO_TEST, "Channel to test is out of range"); - const struct mbox_channel *tx_channel = &channels[current_channel_index][TX_CHANNEL_INDEX]; - const struct mbox_channel *rx_channel = &channels[current_channel_index][RX_CHANNEL_INDEX]; + const struct mbox_dt_spec *tx_channel = &channels[current_channel_index][TX_CHANNEL_INDEX]; + const struct mbox_dt_spec *rx_channel = &channels[current_channel_index][RX_CHANNEL_INDEX]; int ret_val = 0; - g_max_transfer_size_bytes = mbox_mtu_get(tx_channel->dev); + g_max_transfer_size_bytes = mbox_mtu_get_dt(tx_channel); /* Test currently supports only transfer size up to 4 bytes */ if ((g_max_transfer_size_bytes < 0) || (g_max_transfer_size_bytes > 4)) { printk("mbox_mtu_get() error\n"); @@ -80,10 +80,10 @@ static void mbox_data_tests_before(void *f) g_max_transfer_size_bytes); } - ret_val = mbox_register_callback(rx_channel, callback, NULL); + ret_val = mbox_register_callback_dt(rx_channel, callback, NULL); zassert_false(ret_val != 0, "mbox failed to register callback. ret_val", ret_val); - ret_val = mbox_set_enabled(rx_channel, 1); + ret_val = mbox_set_enabled_dt(rx_channel, 1); zassert_false(ret_val != 0, "mbox failed to enable mbox. ret_val: %d", ret_val); } @@ -91,10 +91,10 @@ static void mbox_data_tests_after(void *f) { zassert_false(current_channel_index >= CHANNELS_TO_TEST, "Channel to test is out of range"); - const struct mbox_channel *rx_channel = &channels[current_channel_index][RX_CHANNEL_INDEX]; + const struct mbox_dt_spec *rx_channel = &channels[current_channel_index][RX_CHANNEL_INDEX]; /* Disable channel after test end */ - int ret_val = mbox_set_enabled(rx_channel, 0); + int ret_val = mbox_set_enabled_dt(rx_channel, 0); zassert_false(ret_val != 0, "mbox failed to disable mbox. ret_val: %d", ret_val); @@ -110,14 +110,15 @@ static void mbox_test(const uint32_t data) int ret_val = 0; while (test_count < 100) { - const struct mbox_channel *tx_channel = &channels[current_channel_index][TX_CHANNEL_INDEX]; + const struct mbox_dt_spec *tx_channel = + &channels[current_channel_index][TX_CHANNEL_INDEX]; /* Main core prepare test data */ msg.data = &test_data; msg.size = g_max_transfer_size_bytes; /* Main core send test data */ - ret_val = mbox_send(tx_channel, &msg); + ret_val = mbox_send_dt(tx_channel, &msg); zassert_false(ret_val < 0, "mbox failed to send. ret_val: %d", ret_val); /* Expect next received data will be incremented by one. @@ -142,7 +143,8 @@ static void mbox_test(const uint32_t data) g_mbox_expected_data, test_data); /* Expect reception of data on current RX channel */ - g_mbox_expected_channel = channels[current_channel_index][RX_CHANNEL_INDEX].id; + g_mbox_expected_channel = + channels[current_channel_index][RX_CHANNEL_INDEX].channel_id; zassert_equal(g_mbox_expected_channel, g_mbox_received_channel, "Received channel does not match!: Expected: %d, Got: %d", g_mbox_expected_channel, g_mbox_received_channel); diff --git a/tests/lib/devicetree/api/src/main.c b/tests/lib/devicetree/api/src/main.c index 250c340a20c..84db80926a0 100644 --- a/tests/lib/devicetree/api/src/main.c +++ b/tests/lib/devicetree/api/src/main.c @@ -2660,11 +2660,11 @@ ZTEST(devicetree_api, test_mbox) #undef DT_DRV_COMPAT #define DT_DRV_COMPAT vnd_adc_temp_sensor - const struct mbox_channel channel_tx = MBOX_DT_CHANNEL_GET(TEST_TEMP, tx); - const struct mbox_channel channel_rx = MBOX_DT_CHANNEL_GET(TEST_TEMP, rx); + const struct mbox_dt_spec channel_tx = MBOX_DT_SPEC_GET(TEST_TEMP, tx); + const struct mbox_dt_spec channel_rx = MBOX_DT_SPEC_GET(TEST_TEMP, rx); - zassert_equal(channel_tx.id, 1, ""); - zassert_equal(channel_rx.id, 2, ""); + zassert_equal(channel_tx.channel_id, 1, ""); + zassert_equal(channel_rx.channel_id, 2, ""); zassert_equal(DT_MBOX_CHANNEL_BY_NAME(TEST_TEMP, tx), 1, ""); zassert_equal(DT_MBOX_CHANNEL_BY_NAME(TEST_TEMP, rx), 2, ""); @@ -2677,9 +2677,9 @@ ZTEST(devicetree_api, test_mbox) zassert_equal(DT_MBOX_CHANNEL_BY_NAME(TEST_TEMP, tx), 1, ""); zassert_equal(DT_MBOX_CHANNEL_BY_NAME(TEST_TEMP, rx), 2, ""); - const struct mbox_channel channel_zero = MBOX_DT_CHANNEL_GET(TEST_TEMP, zero); + const struct mbox_dt_spec channel_zero = MBOX_DT_SPEC_GET(TEST_TEMP, zero); - zassert_equal(channel_zero.id, 0, ""); + zassert_equal(channel_zero.channel_id, 0, ""); zassert_equal(DT_MBOX_CHANNEL_BY_NAME(TEST_TEMP, zero), 0, ""); From 053be02994065f3f5fe200fcc1f4d4f2c4c620a5 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Tue, 5 Mar 2024 11:57:57 +0000 Subject: [PATCH 0313/2402] github: upgrade all setup-python actions to v5 The current version is generating a deprecation warning: Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/setup-python@v4. Signed-off-by: Fabio Baltieri --- .github/workflows/devicetree_checks.yml | 2 +- .github/workflows/hello_world_multiplatform.yaml | 2 +- .github/workflows/pylib_tests.yml | 2 +- .github/workflows/scripts_tests.yml | 2 +- .github/workflows/twister_tests.yml | 2 +- .github/workflows/twister_tests_blackbox.yml | 2 +- .github/workflows/west_cmds.yml | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/.github/workflows/devicetree_checks.yml b/.github/workflows/devicetree_checks.yml index c8408f68c09..3b254354bc2 100644 --- a/.github/workflows/devicetree_checks.yml +++ b/.github/workflows/devicetree_checks.yml @@ -37,7 +37,7 @@ jobs: - name: checkout uses: actions/checkout@v4 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v4 + uses: actions/setup-python@v5 with: python-version: ${{ matrix.python-version }} - name: cache-pip-linux diff --git a/.github/workflows/hello_world_multiplatform.yaml b/.github/workflows/hello_world_multiplatform.yaml index e30b09af51d..bcd11ee3ecc 100644 --- a/.github/workflows/hello_world_multiplatform.yaml +++ b/.github/workflows/hello_world_multiplatform.yaml @@ -49,7 +49,7 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python - uses: actions/setup-python@v4 + uses: actions/setup-python@v5 with: python-version: 3.11 diff --git a/.github/workflows/pylib_tests.yml b/.github/workflows/pylib_tests.yml index 70bd107f8e5..fd010bb207b 100644 --- a/.github/workflows/pylib_tests.yml +++ b/.github/workflows/pylib_tests.yml @@ -31,7 +31,7 @@ jobs: - name: checkout uses: actions/checkout@v4 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v4 + uses: actions/setup-python@v5 with: python-version: ${{ matrix.python-version }} - name: cache-pip-linux diff --git a/.github/workflows/scripts_tests.yml b/.github/workflows/scripts_tests.yml index 2e2356910b1..bf04640a30a 100644 --- a/.github/workflows/scripts_tests.yml +++ b/.github/workflows/scripts_tests.yml @@ -46,7 +46,7 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v4 + uses: actions/setup-python@v5 with: python-version: ${{ matrix.python-version }} diff --git a/.github/workflows/twister_tests.yml b/.github/workflows/twister_tests.yml index 70db179a98c..01cf134a695 100644 --- a/.github/workflows/twister_tests.yml +++ b/.github/workflows/twister_tests.yml @@ -36,7 +36,7 @@ jobs: - name: checkout uses: actions/checkout@v4 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v4 + uses: actions/setup-python@v5 with: python-version: ${{ matrix.python-version }} - name: cache-pip-linux diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index 14413ced5b8..78af60ab32c 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -50,7 +50,7 @@ jobs: echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV - name: Set Up Python ${{ matrix.python-version }} - uses: actions/setup-python@v4 + uses: actions/setup-python@v5 with: python-version: ${{ matrix.python-version }} diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml index 96eda2089f7..379086e3d14 100644 --- a/.github/workflows/west_cmds.yml +++ b/.github/workflows/west_cmds.yml @@ -40,7 +40,7 @@ jobs: - name: checkout uses: actions/checkout@v4 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@v4 + uses: actions/setup-python@v5 with: python-version: ${{ matrix.python-version }} - name: cache-pip-linux From 9fa4cd8226ced9ecfcfb34bf0aa5e86d1abceb1f Mon Sep 17 00:00:00 2001 From: Ivan Iushkov Date: Thu, 7 Mar 2024 10:10:02 +0100 Subject: [PATCH 0314/2402] Bluetooth: add missing initilization of sync_info member During manual testing with UBSAN enabled, it was found that bt_le_per_adv_sync_cb synced() callback in application sometimes gets unexpected different values in `sync_info.recv_enabled` field. The UBSAN output contained the following warnings message: runtime error: load of value 65, which is not a valid value for type '_Bool' It tunrned out that struct bt_le_per_adv_sync_synced_info sync_info inside bt_hci_le_past_received_common() contains uninitialized recv_enabled member. Set it to true by default to avoid possible issues. Signed-off-by: Ivan Iushkov --- subsys/bluetooth/host/scan.c | 1 + 1 file changed, 1 insertion(+) diff --git a/subsys/bluetooth/host/scan.c b/subsys/bluetooth/host/scan.c index 0b61305e2c3..ceb4fd2428e 100644 --- a/subsys/bluetooth/host/scan.c +++ b/subsys/bluetooth/host/scan.c @@ -1246,6 +1246,7 @@ static void bt_hci_le_past_received_common(struct net_buf *buf) sync_info.addr = &per_adv_sync->addr; sync_info.sid = per_adv_sync->sid; sync_info.service_data = sys_le16_to_cpu(evt->service_data); + sync_info.recv_enabled = true; #if defined(CONFIG_BT_PER_ADV_SYNC_RSP) sync_info.num_subevents = per_adv_sync->num_subevents; From a55a078909a7e44f8d144a5352fa9f96c2086691 Mon Sep 17 00:00:00 2001 From: Peter Mitsis Date: Thu, 29 Feb 2024 11:21:36 -0500 Subject: [PATCH 0315/2402] tests: Use z_pend_curr() in sched benchmark Replaces the use of z_pend_curr_irqlock() with z_pend_curr() as the former is not used anywhere else anymore. Signed-off-by: Peter Mitsis --- tests/benchmarks/sched/src/main.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tests/benchmarks/sched/src/main.c b/tests/benchmarks/sched/src/main.c index 79a519ccf2c..c516d4ef03c 100644 --- a/tests/benchmarks/sched/src/main.c +++ b/tests/benchmarks/sched/src/main.c @@ -13,14 +13,14 @@ * of specific low level scheduling primitives independent of overhead * from application or API abstractions. It works very simply: a main * thread creates a "partner" thread at a higher priority, the partner - * then sleeps using z_pend_curr_irqlock(). From this initial + * then sleeps using z_pend_curr(). From this initial * state: * * 1. The main thread calls z_unpend_first_thread() * 2. The main thread calls z_ready_thread() * 3. The main thread calls k_yield() * (the kernel switches to the partner thread) - * 4. The partner thread then runs and calls z_pend_curr_irqlock() again + * 4. The partner thread then runs and calls z_pend_curr() again * (the kernel switches to the main thread) * 5. The main thread returns from k_yield() * @@ -49,6 +49,8 @@ enum { uint32_t stamps[NUM_STAMP_STATES]; +static struct k_spinlock lock; + static inline int _stamp(int state) { uint32_t t; @@ -79,9 +81,9 @@ static void partner_fn(void *arg1, void *arg2, void *arg3) printk("Running %p\n", k_current_get()); while (true) { - unsigned int key = irq_lock(); + k_spinlock_key_t key = k_spin_lock(&lock); - z_pend_curr_irqlock(key, &waitq, K_FOREVER); + z_pend_curr(&lock, key, &waitq, K_FOREVER); stamp(PARTNER_AWAKE_PENDING); } } From 9f7695dda0c3068ab6738a9f575a1c6dd363126d Mon Sep 17 00:00:00 2001 From: Peter Mitsis Date: Thu, 29 Feb 2024 11:25:41 -0500 Subject: [PATCH 0316/2402] kernel: Remove unused z_pend_curr_irqlock() The routine z_pend_curr_irqlock() is no longer used anywhere. Signed-off-by: Peter Mitsis --- kernel/include/ksched.h | 1 - kernel/sched.c | 24 ------------------------ 2 files changed, 25 deletions(-) diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index 8a691acb815..5ef720bf54b 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -43,7 +43,6 @@ void z_unpend_thread_no_timeout(struct k_thread *thread); struct k_thread *z_unpend1_no_timeout(_wait_q_t *wait_q); int z_pend_curr(struct k_spinlock *lock, k_spinlock_key_t key, _wait_q_t *wait_q, k_timeout_t timeout); -int z_pend_curr_irqlock(uint32_t key, _wait_q_t *wait_q, k_timeout_t timeout); void z_pend_thread(struct k_thread *thread, _wait_q_t *wait_q, k_timeout_t timeout); void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key); diff --git a/kernel/sched.c b/kernel/sched.c index a2f3e74bfa9..93005ce6bab 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -901,30 +901,6 @@ void z_thread_timeout(struct _timeout *timeout) } #endif -int z_pend_curr_irqlock(uint32_t key, _wait_q_t *wait_q, k_timeout_t timeout) -{ - /* This is a legacy API for pre-switch architectures and isn't - * correctly synchronized for multi-cpu use - */ - __ASSERT_NO_MSG(!IS_ENABLED(CONFIG_SMP)); - - pend_locked(_current, wait_q, timeout); - -#if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC) - pending_current = _current; - - int ret = z_swap_irqlock(key); - K_SPINLOCK(&_sched_spinlock) { - if (pending_current == _current) { - pending_current = NULL; - } - } - return ret; -#else - return z_swap_irqlock(key); -#endif -} - int z_pend_curr(struct k_spinlock *lock, k_spinlock_key_t key, _wait_q_t *wait_q, k_timeout_t timeout) { From 04b240c830241053d1e6c28d63faf8ba0f260bd4 Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Thu, 1 Feb 2024 16:12:06 -0600 Subject: [PATCH 0317/2402] dts: bindings: renamed binding used for pit Renamed pit binding from nxp,kinetis-pit to nxp,pit Signed-off-by: Emilio Benavente --- doc/releases/migration-guide-3.7.rst | 28 +++++++++++++++++++ drivers/counter/CMakeLists.txt | 2 +- drivers/counter/Kconfig | 2 +- drivers/counter/Kconfig.mcux_pit | 11 -------- drivers/counter/Kconfig.nxp_pit | 11 ++++++++ .../{counter_mcux_pit.c => counter_nxp_pit.c} | 2 +- dts/arm/nxp/nxp_k6x.dtsi | 2 +- dts/arm/nxp/nxp_k8x.dtsi | 2 +- dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi | 2 +- dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi | 2 +- .../nxp,pit.yaml} | 8 +++--- .../counter_basic_api/src/test_counter.c | 4 +-- west.yml | 2 +- 13 files changed, 53 insertions(+), 25 deletions(-) delete mode 100644 drivers/counter/Kconfig.mcux_pit create mode 100644 drivers/counter/Kconfig.nxp_pit rename drivers/counter/{counter_mcux_pit.c => counter_nxp_pit.c} (99%) rename dts/bindings/{rtc/nxp,kinetis-pit.yaml => counter/nxp,pit.yaml} (74%) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index 8baccab3d9a..f9c8acd248f 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -40,6 +40,34 @@ zcbor Device Drivers and Devicetree ***************************** +* The :dtcompatible:`nxp,kinetis-pit` pit driver has changed it's compatible + to :dtcompatible:`nxp,pit` and has been updated to support multiple channels. + To configure the individual channels, you must add a child node with the + compatible :dtcompatible:`nxp,pit-channel` and configure as below. + The :kconfig:option:`CONFIG_COUNTER_MCUX_PIT` has also been renamed to + :kconfig:option:`CONFIG_COUNTER_NXP_PIT` with regards to the renaming + of the binding for the pit. + example: + + .. code-block:: devicetree + + / { + pit0: pit@40037000 { + /* Other Pit DT Attributes */ + compatible = "nxp,pit"; + status = "disabled"; + num-channels = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pit0_channel0: pit0_channel@0 { + compatible = "nxp,pit-channel"; + reg = <0>; + status = "disabled"; + }; + }; + + Analog-to-Digital Converter (ADC) ================================= diff --git a/drivers/counter/CMakeLists.txt b/drivers/counter/CMakeLists.txt index 50a1ffad441..e9a0d3c1563 100644 --- a/drivers/counter/CMakeLists.txt +++ b/drivers/counter/CMakeLists.txt @@ -33,7 +33,7 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_LPTMR counter_mcux_lpt zephyr_library_sources_ifdef(CONFIG_COUNTER_MAXIM_DS3231 maxim_ds3231.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_NATIVE_POSIX counter_native_posix.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE counter_handlers.c) -zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_PIT counter_mcux_pit.c) +zephyr_library_sources_ifdef(CONFIG_COUNTER_NXP_PIT counter_nxp_pit.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_XLNX_AXI_TIMER counter_xlnx_axi_timer.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_TMR_ESP32 counter_esp32_tmr.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_RTC_ESP32 counter_esp32_rtc.c) diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index 16adaee75b2..3684b2c63c6 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -68,7 +68,7 @@ source "drivers/counter/Kconfig.maxim_ds3231" source "drivers/counter/Kconfig.native_posix" -source "drivers/counter/Kconfig.mcux_pit" +source "drivers/counter/Kconfig.nxp_pit" source "drivers/counter/Kconfig.xlnx" diff --git a/drivers/counter/Kconfig.mcux_pit b/drivers/counter/Kconfig.mcux_pit deleted file mode 100644 index 56db116195d..00000000000 --- a/drivers/counter/Kconfig.mcux_pit +++ /dev/null @@ -1,11 +0,0 @@ -# MCUXpresso SDK Periodic Interrupt Timer (PIT) - -# Copyright 2020 NXP -# SPDX-License-Identifier: Apache-2.0 - -config COUNTER_MCUX_PIT - bool "MCUX PIT driver" - default y - depends on DT_HAS_NXP_KINETIS_PIT_ENABLED - help - Enable support for the MCUX Periodic Interrupt Timer (PIT). diff --git a/drivers/counter/Kconfig.nxp_pit b/drivers/counter/Kconfig.nxp_pit new file mode 100644 index 00000000000..483f7e3beef --- /dev/null +++ b/drivers/counter/Kconfig.nxp_pit @@ -0,0 +1,11 @@ +# MCUXpresso SDK Periodic Interrupt Timer (PIT) + +# Copyright 2020 NXP +# SPDX-License-Identifier: Apache-2.0 + +config COUNTER_NXP_PIT + bool "NXP PIT driver" + default y + depends on DT_HAS_NXP_PIT_ENABLED + help + Enable support for the NXP Periodic Interrupt Timer (PIT). diff --git a/drivers/counter/counter_mcux_pit.c b/drivers/counter/counter_nxp_pit.c similarity index 99% rename from drivers/counter/counter_mcux_pit.c rename to drivers/counter/counter_nxp_pit.c index 94e57bd4325..3a6f69922f1 100644 --- a/drivers/counter/counter_mcux_pit.c +++ b/drivers/counter/counter_nxp_pit.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT nxp_kinetis_pit +#define DT_DRV_COMPAT nxp_pit #include #include diff --git a/dts/arm/nxp/nxp_k6x.dtsi b/dts/arm/nxp/nxp_k6x.dtsi index 909e07e3792..3b6033f41db 100644 --- a/dts/arm/nxp/nxp_k6x.dtsi +++ b/dts/arm/nxp/nxp_k6x.dtsi @@ -527,7 +527,7 @@ }; pit0: pit@40037000 { - compatible = "nxp,kinetis-pit"; + compatible = "nxp,pit"; reg = <0x40037000 0x1000>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>; interrupts = <48 0>, <49 0>, <50 0>, <51 0>; diff --git a/dts/arm/nxp/nxp_k8x.dtsi b/dts/arm/nxp/nxp_k8x.dtsi index 61e0cd1fc39..220b4b42562 100644 --- a/dts/arm/nxp/nxp_k8x.dtsi +++ b/dts/arm/nxp/nxp_k8x.dtsi @@ -387,7 +387,7 @@ }; pit0: pit@40037000 { - compatible = "nxp,kinetis-pit"; + compatible = "nxp,pit"; reg = <0x40037000 0x1000>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>; interrupts = <48 0>, <49 0>, <50 0>, <51 0>; diff --git a/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi index ec548c264cd..28cb35607eb 100644 --- a/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi @@ -89,7 +89,7 @@ }; pit0: pit@76150000 { - compatible = "nxp,kinetis-pit"; + compatible = "nxp,pit"; reg = <0x76150000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_P0_REG_INTF_CLK>; diff --git a/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi index f316ac86fd9..c7831a241a4 100644 --- a/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi @@ -89,7 +89,7 @@ }; pit0: pit@76950000 { - compatible = "nxp,kinetis-pit"; + compatible = "nxp,pit"; reg = <0x76950000 0x10000>; interrupts = ; clocks = <&clock NXP_S32_P1_REG_INTF_CLK>; diff --git a/dts/bindings/rtc/nxp,kinetis-pit.yaml b/dts/bindings/counter/nxp,pit.yaml similarity index 74% rename from dts/bindings/rtc/nxp,kinetis-pit.yaml rename to dts/bindings/counter/nxp,pit.yaml index ad3ee44ab4c..33006393c29 100644 --- a/dts/bindings/rtc/nxp,kinetis-pit.yaml +++ b/dts/bindings/counter/nxp,pit.yaml @@ -1,11 +1,11 @@ -# Copyright 2020,2023 NXP +# Copyright 2020,2023-2024 NXP # SPDX-License-Identifier: Apache-2.0 -description: NXP MCUX Periodic Interrupt Timer (PIT) +description: NXP Periodic Interrupt Timer (PIT) -compatible: "nxp,kinetis-pit" +compatible: "nxp,pit" -include: [rtc.yaml] +include: base.yaml properties: reg: diff --git a/tests/drivers/counter/counter_basic_api/src/test_counter.c b/tests/drivers/counter/counter_basic_api/src/test_counter.c index 642465c6078..d54363a4931 100644 --- a/tests/drivers/counter/counter_basic_api/src/test_counter.c +++ b/tests/drivers/counter/counter_basic_api/src/test_counter.c @@ -84,8 +84,8 @@ static const struct device *const devices[] = { #ifdef CONFIG_COUNTER_GECKO_STIMER DEVS_FOR_DT_COMPAT(silabs_gecko_stimer) #endif -#ifdef CONFIG_COUNTER_MCUX_PIT - DEVS_FOR_DT_COMPAT(nxp_kinetis_pit) +#ifdef CONFIG_COUNTER_NXP_PIT + DEVS_FOR_DT_COMPAT(nxp_pit) #endif #ifdef CONFIG_COUNTER_XLNX_AXI_TIMER DEVS_FOR_DT_COMPAT(xlnx_xps_timer_1_00_a) diff --git a/west.yml b/west.yml index 0f8402dadcf..e1ff0d95ce4 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: c5a56361f3e4968a4d1eaa6f91761550b7d81e70 + revision: ef5060421fdba7bd86f98e50dc15db9a5c4c1b53 path: modules/hal/nxp groups: - hal From 9cb330e1edcceb824e64ed9582f5d8134ebe795b Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Thu, 1 Feb 2024 16:34:34 -0600 Subject: [PATCH 0318/2402] drivers: counter: update nxp_pit api names Update the api named for the new nxp pit driver. Signed-off-by: Emilio Benavente --- drivers/counter/counter_nxp_pit.c | 90 +++++++++++++++---------------- 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/counter/counter_nxp_pit.c b/drivers/counter/counter_nxp_pit.c index 3a6f69922f1..3783a1d9e9b 100644 --- a/drivers/counter/counter_nxp_pit.c +++ b/drivers/counter/counter_nxp_pit.c @@ -15,7 +15,7 @@ #include LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_COUNTER_LOG_LEVEL); -struct mcux_pit_config { +struct nxp_pit_config { struct counter_config_info info; PIT_Type *base; bool enableRunInDebug; @@ -26,14 +26,14 @@ struct mcux_pit_config { clock_control_subsys_t clock_subsys; }; -struct mcux_pit_data { +struct nxp_pit_data { counter_top_callback_t top_callback; void *top_user_data; }; -static uint32_t mcux_pit_get_top_value(const struct device *dev) +static uint32_t nxp_pit_get_top_value(const struct device *dev) { - const struct mcux_pit_config *config = dev->config; + const struct nxp_pit_config *config = dev->config; pit_chnl_t channel = config->pit_channel; /* @@ -46,20 +46,20 @@ static uint32_t mcux_pit_get_top_value(const struct device *dev) return (config->base->CHANNEL[channel].LDVAL + 1); } -static int mcux_pit_start(const struct device *dev) +static int nxp_pit_start(const struct device *dev) { - const struct mcux_pit_config *config = dev->config; + const struct nxp_pit_config *config = dev->config; - LOG_DBG("period is %d", mcux_pit_get_top_value(dev)); + LOG_DBG("period is %d", nxp_pit_get_top_value(dev)); PIT_EnableInterrupts(config->base, config->pit_channel, kPIT_TimerInterruptEnable); PIT_StartTimer(config->base, config->pit_channel); return 0; } -static int mcux_pit_stop(const struct device *dev) +static int nxp_pit_stop(const struct device *dev) { - const struct mcux_pit_config *config = dev->config; + const struct nxp_pit_config *config = dev->config; PIT_DisableInterrupts(config->base, config->pit_channel, kPIT_TimerInterruptEnable); @@ -68,20 +68,20 @@ static int mcux_pit_stop(const struct device *dev) return 0; } -static int mcux_pit_get_value(const struct device *dev, uint32_t *ticks) +static int nxp_pit_get_value(const struct device *dev, uint32_t *ticks) { - const struct mcux_pit_config *config = dev->config; + const struct nxp_pit_config *config = dev->config; *ticks = PIT_GetCurrentTimerCount(config->base, config->pit_channel); return 0; } -static int mcux_pit_set_top_value(const struct device *dev, +static int nxp_pit_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg) { - const struct mcux_pit_config *config = dev->config; - struct mcux_pit_data *data = dev->data; + const struct nxp_pit_config *config = dev->config; + struct nxp_pit_data *data = dev->data; pit_chnl_t channel = config->pit_channel; if (cfg->ticks == 0) { @@ -106,9 +106,9 @@ static int mcux_pit_set_top_value(const struct device *dev, return 0; } -static uint32_t mcux_pit_get_pending_int(const struct device *dev) +static uint32_t nxp_pit_get_pending_int(const struct device *dev) { - const struct mcux_pit_config *config = dev->config; + const struct nxp_pit_config *config = dev->config; uint32_t mask = PIT_TFLG_TIF_MASK; uint32_t flags; @@ -117,9 +117,9 @@ static uint32_t mcux_pit_get_pending_int(const struct device *dev) return ((flags & mask) == mask); } -static uint32_t mcux_pit_get_frequency(const struct device *dev) +static uint32_t nxp_pit_get_frequency(const struct device *dev) { - const struct mcux_pit_config *config = dev->config; + const struct nxp_pit_config *config = dev->config; uint32_t clock_rate; if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate)) { @@ -130,10 +130,10 @@ static uint32_t mcux_pit_get_frequency(const struct device *dev) return clock_rate; } -static void mcux_pit_isr(const struct device *dev) +static void nxp_pit_isr(const struct device *dev) { - const struct mcux_pit_config *config = dev->config; - struct mcux_pit_data *data = dev->data; + const struct nxp_pit_config *config = dev->config; + struct nxp_pit_data *data = dev->data; uint32_t flags; LOG_DBG("pit counter isr"); @@ -144,9 +144,9 @@ static void mcux_pit_isr(const struct device *dev) } } -static int mcux_pit_init(const struct device *dev) +static int nxp_pit_init(const struct device *dev) { - const struct mcux_pit_config *config = dev->config; + const struct nxp_pit_config *config = dev->config; pit_config_t pit_config; uint32_t clock_rate; @@ -162,37 +162,37 @@ static int mcux_pit_init(const struct device *dev) config->irq_config_func(dev); - clock_rate = mcux_pit_get_frequency(dev); + clock_rate = nxp_pit_get_frequency(dev); PIT_SetTimerPeriod(config->base, config->pit_channel, USEC_TO_COUNT(config->pit_period, clock_rate)); return 0; } -static const struct counter_driver_api mcux_pit_driver_api = { - .start = mcux_pit_start, - .stop = mcux_pit_stop, - .get_value = mcux_pit_get_value, - .set_top_value = mcux_pit_set_top_value, - .get_pending_int = mcux_pit_get_pending_int, - .get_top_value = mcux_pit_get_top_value, - .get_freq = mcux_pit_get_frequency, +static const struct counter_driver_api nxp_pit_driver_api = { + .start = nxp_pit_start, + .stop = nxp_pit_stop, + .get_value = nxp_pit_get_value, + .set_top_value = nxp_pit_set_top_value, + .get_pending_int = nxp_pit_get_pending_int, + .get_top_value = nxp_pit_get_top_value, + .get_freq = nxp_pit_get_frequency, }; -#define COUNTER_MCUX_PIT_IRQ_CONFIG(idx, n) \ +#define COUNTER_NXP_PIT_IRQ_CONFIG(idx, n) \ do { \ IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, idx, irq), \ DT_INST_IRQ_BY_IDX(n, idx, priority), \ - mcux_pit_isr, DEVICE_DT_INST_GET(n), \ + nxp_pit_isr, DEVICE_DT_INST_GET(n), \ COND_CODE_1(DT_INST_IRQ_HAS_NAME(n, flags), \ (DT_INST_IRQ_BY_IDX(n, idx, flags)), (0))); \ irq_enable(DT_INST_IRQ_BY_IDX(n, idx, irq)); \ } while (0) -#define COUNTER_MCUX_PIT_DEVICE(n) \ - static void mcux_pit_irq_config_##n(const struct device *dev); \ - static struct mcux_pit_data mcux_pit_data_##n; \ - static const struct mcux_pit_config mcux_pit_config_##n = { \ +#define COUNTER_NXP_PIT_DEVICE(n) \ + static void nxp_pit_irq_config_##n(const struct device *dev); \ + static struct nxp_pit_data nxp_pit_data_##n; \ + static const struct nxp_pit_config nxp_pit_config_##n = { \ .info = { \ .max_top_value = DT_INST_PROP(n, max_load_value), \ .channels = 0, \ @@ -200,20 +200,20 @@ static const struct counter_driver_api mcux_pit_driver_api = { .base = (PIT_Type *)DT_INST_REG_ADDR(n), \ .pit_channel = DT_INST_PROP(n, pit_channel), \ .pit_period = DT_INST_PROP(n, pit_period), \ - .irq_config_func = mcux_pit_irq_config_##n, \ + .irq_config_func = nxp_pit_irq_config_##n, \ .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ .clock_subsys = (clock_control_subsys_t) \ DT_INST_CLOCKS_CELL(n, name), \ }; \ \ - DEVICE_DT_INST_DEFINE(n, &mcux_pit_init, NULL, \ - &mcux_pit_data_##n, &mcux_pit_config_##n, POST_KERNEL, \ - CONFIG_COUNTER_INIT_PRIORITY, &mcux_pit_driver_api); \ + DEVICE_DT_INST_DEFINE(n, &nxp_pit_init, NULL, \ + &nxp_pit_data_##n, &nxp_pit_config_##n, POST_KERNEL, \ + CONFIG_COUNTER_INIT_PRIORITY, &nxp_pit_driver_api); \ \ - static void mcux_pit_irq_config_##n(const struct device *dev) \ + static void nxp_pit_irq_config_##n(const struct device *dev) \ { \ LISTIFY(DT_NUM_IRQS(DT_DRV_INST(n)), \ - COUNTER_MCUX_PIT_IRQ_CONFIG, (;), n); \ + COUNTER_NXP_PIT_IRQ_CONFIG, (;), n); \ } -DT_INST_FOREACH_STATUS_OKAY(COUNTER_MCUX_PIT_DEVICE) +DT_INST_FOREACH_STATUS_OKAY(COUNTER_NXP_PIT_DEVICE) From 8bb95d33bee5bbf219a9cd8bd428a27ec2bbe17b Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Fri, 2 Feb 2024 11:04:06 -0600 Subject: [PATCH 0319/2402] drivers: counter: Adding Mutli Channel PIT Support Updating the nxp,pit driver to support mutliple channels. Updating the dts and board overlays to account for the changes. Signed-off-by: Emilio Benavente --- drivers/counter/Kconfig.nxp_pit | 4 +- drivers/counter/counter_nxp_pit.c | 277 ++++++++++++++---- dts/arm/nxp/nxp_k6x.dtsi | 33 ++- dts/arm/nxp/nxp_k8x.dtsi | 33 ++- dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi | 38 +++ dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi | 38 +++ dts/bindings/counter/nxp,pit-channel.yaml | 13 + dts/bindings/counter/nxp,pit.yaml | 10 - .../adc/adc_dma/boards/frdm_k64f.overlay | 4 + .../adc/adc_dma/boards/frdm_k82f.overlay | 4 + .../boards/frdm_k64f.overlay | 19 ++ .../boards/frdm_k82f.overlay | 19 ++ .../boards/s32z2xxdc2_s32z270_rtu0.overlay | 8 +- .../boards/s32z2xxdc2_s32z270_rtu1.overlay | 8 +- .../counter_basic_api/src/test_counter.c | 3 +- 15 files changed, 424 insertions(+), 87 deletions(-) create mode 100644 dts/bindings/counter/nxp,pit-channel.yaml create mode 100644 tests/drivers/counter/counter_basic_api/boards/frdm_k64f.overlay create mode 100644 tests/drivers/counter/counter_basic_api/boards/frdm_k82f.overlay diff --git a/drivers/counter/Kconfig.nxp_pit b/drivers/counter/Kconfig.nxp_pit index 483f7e3beef..fc330dd6c4d 100644 --- a/drivers/counter/Kconfig.nxp_pit +++ b/drivers/counter/Kconfig.nxp_pit @@ -5,7 +5,7 @@ config COUNTER_NXP_PIT bool "NXP PIT driver" - default y - depends on DT_HAS_NXP_PIT_ENABLED + default y if DT_HAS_NXP_PIT_CHANNEL_ENABLED && \ + DT_HAS_NXP_PIT_ENABLED help Enable support for the NXP Periodic Interrupt Timer (PIT). diff --git a/drivers/counter/counter_nxp_pit.c b/drivers/counter/counter_nxp_pit.c index 3783a1d9e9b..5cf192a73c4 100644 --- a/drivers/counter/counter_nxp_pit.c +++ b/drivers/counter/counter_nxp_pit.c @@ -1,5 +1,5 @@ /* - * Copyright 2020,2023 NXP + * Copyright 2020,2023-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,26 +15,46 @@ #include LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_COUNTER_LOG_LEVEL); +/* Device holds a pointer to pointer to data */ +#define PIT_CHANNEL_DATA(dev) \ + (*(struct nxp_pit_channel_data *const *const)dev->data) + +/* Device config->data is an array of data pointers ordered by channel number, + * dev->data is a pointer to one of these pointers in that array, + * so the value of the dev->data - dev->config->data is the channel index + */ +#define PIT_CHANNEL_ID(dev) \ + (((struct nxp_pit_channel_data *const *)dev->data) - \ + ((const struct nxp_pit_config *)dev->config)->data) + + +struct nxp_pit_channel_data { + uint32_t top; + counter_top_callback_t top_callback; + void *top_user_data; +}; + + struct nxp_pit_config { struct counter_config_info info; PIT_Type *base; bool enableRunInDebug; - pit_chnl_t pit_channel; - uint32_t pit_period; + int num_channels; +#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts) void (*irq_config_func)(const struct device *dev); +#else + void (**irq_config_func)(const struct device *dev); +#endif const struct device *clock_dev; clock_control_subsys_t clock_subsys; -}; - -struct nxp_pit_data { - counter_top_callback_t top_callback; - void *top_user_data; + struct nxp_pit_channel_data *const *data; + const struct device *const *channels; }; static uint32_t nxp_pit_get_top_value(const struct device *dev) { const struct nxp_pit_config *config = dev->config; - pit_chnl_t channel = config->pit_channel; + pit_chnl_t channel = PIT_CHANNEL_ID(dev); /* * According to RM, the LDVAL trigger = clock ticks -1 @@ -49,21 +69,23 @@ static uint32_t nxp_pit_get_top_value(const struct device *dev) static int nxp_pit_start(const struct device *dev) { const struct nxp_pit_config *config = dev->config; + int channel_id = PIT_CHANNEL_ID(dev); LOG_DBG("period is %d", nxp_pit_get_top_value(dev)); - PIT_EnableInterrupts(config->base, config->pit_channel, + PIT_EnableInterrupts(config->base, channel_id, kPIT_TimerInterruptEnable); - PIT_StartTimer(config->base, config->pit_channel); + PIT_StartTimer(config->base, channel_id); return 0; } static int nxp_pit_stop(const struct device *dev) { const struct nxp_pit_config *config = dev->config; + int channel_id = PIT_CHANNEL_ID(dev); - PIT_DisableInterrupts(config->base, config->pit_channel, + PIT_DisableInterrupts(config->base, channel_id, kPIT_TimerInterruptEnable); - PIT_StopTimer(config->base, config->pit_channel); + PIT_StopTimer(config->base, channel_id); return 0; } @@ -71,8 +93,9 @@ static int nxp_pit_stop(const struct device *dev) static int nxp_pit_get_value(const struct device *dev, uint32_t *ticks) { const struct nxp_pit_config *config = dev->config; + int channel_id = PIT_CHANNEL_ID(dev); - *ticks = PIT_GetCurrentTimerCount(config->base, config->pit_channel); + *ticks = PIT_GetCurrentTimerCount(config->base, channel_id); return 0; } @@ -81,8 +104,8 @@ static int nxp_pit_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg) { const struct nxp_pit_config *config = dev->config; - struct nxp_pit_data *data = dev->data; - pit_chnl_t channel = config->pit_channel; + struct nxp_pit_channel_data *data = PIT_CHANNEL_DATA(dev); + pit_chnl_t channel = PIT_CHANNEL_ID(dev); if (cfg->ticks == 0) { return -EINVAL; @@ -111,8 +134,9 @@ static uint32_t nxp_pit_get_pending_int(const struct device *dev) const struct nxp_pit_config *config = dev->config; uint32_t mask = PIT_TFLG_TIF_MASK; uint32_t flags; + int channel_id = PIT_CHANNEL_ID(dev); - flags = PIT_GetStatusFlags(config->base, config->pit_channel); + flags = PIT_GetStatusFlags(config->base, channel_id); return ((flags & mask) == mask); } @@ -130,19 +154,43 @@ static uint32_t nxp_pit_get_frequency(const struct device *dev) return clock_rate; } +#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts) static void nxp_pit_isr(const struct device *dev) { const struct nxp_pit_config *config = dev->config; - struct nxp_pit_data *data = dev->data; uint32_t flags; LOG_DBG("pit counter isr"); - flags = PIT_GetStatusFlags(config->base, config->pit_channel); - PIT_ClearStatusFlags(config->base, config->pit_channel, flags); - if (data->top_callback) { + + for (int channel_index = 0; + channel_index < config->num_channels; + channel_index++) { + flags = PIT_GetStatusFlags(config->base, channel_index); + if (flags) { + struct nxp_pit_channel_data *data = + PIT_CHANNEL_DATA(config->channels[channel_index]); + PIT_ClearStatusFlags(config->base, channel_index, flags); + data->top_callback(dev, data->top_user_data); + } + } +} +#else +static void nxp_pit_isr(const struct device *dev) +{ + const struct nxp_pit_config *config = dev->config; + struct nxp_pit_channel_data *data = PIT_CHANNEL_DATA(dev); + pit_chnl_t channel = PIT_CHANNEL_ID(dev); + uint32_t flags; + + LOG_DBG("pit counter isr"); + + flags = PIT_GetStatusFlags(config->base, channel); + if (flags) { + PIT_ClearStatusFlags(config->base, channel, flags); data->top_callback(dev, data->top_user_data); } } +#endif /* DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts) */ static int nxp_pit_init(const struct device *dev) { @@ -160,12 +208,27 @@ static int nxp_pit_init(const struct device *dev) PIT_Init(config->base, &pit_config); - config->irq_config_func(dev); - clock_rate = nxp_pit_get_frequency(dev); - PIT_SetTimerPeriod(config->base, config->pit_channel, - USEC_TO_COUNT(config->pit_period, clock_rate)); +#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts) + config->irq_config_func(dev); + for (int channel_index = 0; + channel_index < config->num_channels; + channel_index++) { + PIT_SetTimerPeriod(config->base, channel_index, + USEC_TO_COUNT(config->info.max_top_value, clock_rate)); + } +#else + for (int channel_index = 0; + channel_index < config->num_channels; + channel_index++) { + if (config->irq_config_func[channel_index]) { + config->irq_config_func[channel_index](dev); + PIT_SetTimerPeriod(config->base, channel_index, + USEC_TO_COUNT(config->info.max_top_value, clock_rate)); + } + } +#endif /* DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts) */ return 0; } @@ -179,41 +242,131 @@ static const struct counter_driver_api nxp_pit_driver_api = { .get_freq = nxp_pit_get_frequency, }; -#define COUNTER_NXP_PIT_IRQ_CONFIG(idx, n) \ - do { \ - IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, idx, irq), \ - DT_INST_IRQ_BY_IDX(n, idx, priority), \ - nxp_pit_isr, DEVICE_DT_INST_GET(n), \ - COND_CODE_1(DT_INST_IRQ_HAS_NAME(n, flags), \ - (DT_INST_IRQ_BY_IDX(n, idx, flags)), (0))); \ - irq_enable(DT_INST_IRQ_BY_IDX(n, idx, irq)); \ - } while (0) - -#define COUNTER_NXP_PIT_DEVICE(n) \ - static void nxp_pit_irq_config_##n(const struct device *dev); \ - static struct nxp_pit_data nxp_pit_data_##n; \ - static const struct nxp_pit_config nxp_pit_config_##n = { \ - .info = { \ - .max_top_value = DT_INST_PROP(n, max_load_value), \ - .channels = 0, \ - }, \ - .base = (PIT_Type *)DT_INST_REG_ADDR(n), \ - .pit_channel = DT_INST_PROP(n, pit_channel), \ - .pit_period = DT_INST_PROP(n, pit_period), \ - .irq_config_func = nxp_pit_irq_config_##n, \ - .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ - .clock_subsys = (clock_control_subsys_t) \ - DT_INST_CLOCKS_CELL(n, name), \ - }; \ - \ - DEVICE_DT_INST_DEFINE(n, &nxp_pit_init, NULL, \ - &nxp_pit_data_##n, &nxp_pit_config_##n, POST_KERNEL, \ - CONFIG_COUNTER_INIT_PRIORITY, &nxp_pit_driver_api); \ - \ - static void nxp_pit_irq_config_##n(const struct device *dev) \ - { \ - LISTIFY(DT_NUM_IRQS(DT_DRV_INST(n)), \ - COUNTER_NXP_PIT_IRQ_CONFIG, (;), n); \ - } -DT_INST_FOREACH_STATUS_OKAY(COUNTER_NXP_PIT_DEVICE) +/* Creates a device for a channel (needed for counter API) */ +#define NXP_PIT_CHANNEL_DEV_INIT(node, pit_inst) \ + DEVICE_DT_DEFINE(node, NULL, NULL, \ + (void *) \ + &nxp_pit_##pit_inst##_channel_datas[DT_REG_ADDR(node)], \ + &nxp_pit_##pit_inst##_config, \ + POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, \ + &nxp_pit_driver_api); + +/* Creates a decleration for each pit channel */ +#define NXP_PIT_CHANNEL_DECLARATIONS(node) static struct nxp_pit_channel_data \ + nxp_pit_channel_data_##node; + +/* Initializes an element of the channel data pointer array */ +#define NXP_PIT_INSERT_CHANNEL_INTO_ARRAY(node) \ + [DT_REG_ADDR(node)] = \ + &nxp_pit_channel_data_##node, + +#define NXP_PIT_INSERT_CHANNEL_DEVICE_INTO_ARRAY(node) \ + [DT_REG_ADDR(node)] = DEVICE_DT_GET(node), + + +#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts) +#define NXP_PIT_IRQ_CONFIG_DECLARATIONS(n) \ + static void nxp_pit_irq_config_func_##n(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), \ + DT_INST_IRQ_BY_IDX(n, 0, priority), \ + nxp_pit_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + }; + +#define NXP_PIT_SETUP_IRQ_CONFIG(n) NXP_PIT_IRQ_CONFIG_DECLARATIONS(n); +#define NXP_PIT_SETUP_IRQ_ARRAY(ignored) + +#else +#define NXP_PIT_IRQ_CONFIG_DECLARATIONS(n) \ + static void nxp_pit_irq_config_func_##n(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_IRQN(n), \ + DT_IRQ(n, priority), \ + nxp_pit_isr, \ + DEVICE_DT_GET(n), 0); \ + irq_enable(DT_IRQN(n)); \ + }; + +#define NXP_PIT_SETUP_IRQ_CONFIG(n) \ + DT_INST_FOREACH_CHILD_STATUS_OKAY(n, NXP_PIT_IRQ_CONFIG_DECLARATIONS); + +#define NXP_PIT_INSERT_IRQ_CONFIG_INTO_ARRAY(n) \ + [DT_REG_ADDR(n)] = &nxp_pit_irq_config_func_##n, + +#define NXP_PIT_SETUP_IRQ_ARRAY(n) \ + /* Create Array of IRQs -> 1 irq func per channel */ \ + void (*nxp_pit_irq_config_array[DT_INST_FOREACH_CHILD_SEP_VARGS(n, \ + DT_NODE_HAS_COMPAT, (+), nxp_pit_channel)]) \ + (const struct device *dev) = { \ + DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \ + NXP_PIT_INSERT_IRQ_CONFIG_INTO_ARRAY) \ + }; +#endif + +#define COUNTER_NXP_PIT_DEVICE_INIT(n) \ + \ + /* Setup the IRQ either for parent irq or per channel irq */ \ + NXP_PIT_SETUP_IRQ_CONFIG(n) \ + \ + /* Create channel declarations */ \ + DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \ + NXP_PIT_CHANNEL_DECLARATIONS) \ + \ + /* Array of channel devices */ \ + static struct nxp_pit_channel_data *const \ + nxp_pit_##n##_channel_datas \ + [DT_INST_FOREACH_CHILD_SEP_VARGS( \ + n, DT_NODE_HAS_COMPAT, (+), nxp_pit_channel)] = { \ + DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \ + NXP_PIT_INSERT_CHANNEL_INTO_ARRAY) \ + }; \ + \ + /* forward declaration */ \ + static const struct nxp_pit_config nxp_pit_##n##_config; \ + \ + /* Create all the channel/counter devices */ \ + DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(n, \ + NXP_PIT_CHANNEL_DEV_INIT, n) \ + \ + /* This channel device array is needed by the module device ISR */ \ + const struct device *const nxp_pit_##n##_channels \ + [DT_INST_FOREACH_CHILD_SEP_VARGS( \ + n, DT_NODE_HAS_COMPAT, (+), nxp_pit_channel)] = { \ + DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \ + NXP_PIT_INSERT_CHANNEL_DEVICE_INTO_ARRAY) \ + }; \ + \ + \ + NXP_PIT_SETUP_IRQ_ARRAY(n) \ + \ + /* This config struct is shared by all the channels and parent device */ \ + static const struct nxp_pit_config nxp_pit_##n##_config = { \ + .info = { \ + .max_top_value = \ + DT_INST_PROP(n, max_load_value), \ + .channels = 0, \ + }, \ + .base = (PIT_Type *)DT_INST_REG_ADDR(n), \ + .irq_config_func = COND_CODE_1(DT_NODE_HAS_PROP( \ + DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts), \ + (nxp_pit_irq_config_func_##n), \ + (&nxp_pit_irq_config_array[0])), \ + .num_channels = DT_INST_FOREACH_CHILD_SEP_VARGS( \ + n, DT_NODE_HAS_COMPAT, (+), nxp_pit_channel), \ + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clock_subsys = (clock_control_subsys_t) \ + DT_INST_CLOCKS_CELL(n, name), \ + .data = nxp_pit_##n##_channel_datas, \ + .channels = nxp_pit_##n##_channels, \ + }; \ + \ + /* Init parent device in order to handle ISR and init. */ \ + DEVICE_DT_INST_DEFINE(n, &nxp_pit_init, NULL, \ + NULL, &nxp_pit_##n##_config, POST_KERNEL, \ + CONFIG_COUNTER_INIT_PRIORITY, NULL); + + +DT_INST_FOREACH_STATUS_OKAY(COUNTER_NXP_PIT_DEVICE_INIT) diff --git a/dts/arm/nxp/nxp_k6x.dtsi b/dts/arm/nxp/nxp_k6x.dtsi index 3b6033f41db..2bf247fd797 100644 --- a/dts/arm/nxp/nxp_k6x.dtsi +++ b/dts/arm/nxp/nxp_k6x.dtsi @@ -530,11 +530,38 @@ compatible = "nxp,pit"; reg = <0x40037000 0x1000>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>; - interrupts = <48 0>, <49 0>, <50 0>, <51 0>; status = "disabled"; - pit-channel = <0>; - pit-period = <1000000>; max-load-value = <0xffffffff>; + #address-cells = <1>; + #size-cells = <0>; + + pit0_channel0: pit0_channel@0 { + compatible = "nxp,pit-channel"; + reg = <0>; + interrupts = <48 0>; + status = "disabled"; + }; + + pit0_channel1: pit0_channel@1 { + compatible = "nxp,pit-channel"; + reg = <1>; + interrupts = <49 0>; + status = "disabled"; + }; + + pit0_channel2: pit0_channel@2 { + compatible = "nxp,pit-channel"; + reg = <2>; + interrupts = <50 0>; + status = "disabled"; + }; + + pit0_channel3: pit0_channel@3 { + compatible = "nxp,pit-channel"; + reg = <3>; + interrupts = <51 0>; + status = "disabled"; + }; }; }; }; diff --git a/dts/arm/nxp/nxp_k8x.dtsi b/dts/arm/nxp/nxp_k8x.dtsi index 220b4b42562..a510710f519 100644 --- a/dts/arm/nxp/nxp_k8x.dtsi +++ b/dts/arm/nxp/nxp_k8x.dtsi @@ -390,11 +390,38 @@ compatible = "nxp,pit"; reg = <0x40037000 0x1000>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>; - interrupts = <48 0>, <49 0>, <50 0>, <51 0>; status = "disabled"; - pit-channel = <0>; - pit-period = <1000000>; max-load-value = <0xffffffff>; + #address-cells = <1>; + #size-cells = <0>; + + pit0_channel0: pit0_channel@0 { + compatible = "nxp,pit-channel"; + reg = <0>; + interrupts = <48 0>; + status = "disabled"; + }; + + pit0_channel1: pit0_channel@1 { + compatible = "nxp,pit-channel"; + reg = <1>; + interrupts = <49 0>; + status = "disabled"; + }; + + pit0_channel2: pit0_channel@2 { + compatible = "nxp,pit-channel"; + reg = <2>; + interrupts = <50 0>; + status = "disabled"; + }; + + pit0_channel3: pit0_channel@3 { + compatible = "nxp,pit-channel"; + reg = <3>; + interrupts = <51 0>; + status = "disabled"; + }; }; edma0: dma-controller@40008000 { diff --git a/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi index 28cb35607eb..92596493f6b 100644 --- a/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi @@ -95,6 +95,44 @@ clocks = <&clock NXP_S32_P0_REG_INTF_CLK>; max-load-value = <0x00ffffff>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + pit0_channel0: pit0_channel@0 { + compatible = "nxp,pit-channel"; + reg = <0>; + status = "disabled"; + }; + + pit0_channel1: pit0_channel@1 { + compatible = "nxp,pit-channel"; + reg = <1>; + status = "disabled"; + }; + + pit0_channel2: pit0_channel@2 { + compatible = "nxp,pit-channel"; + reg = <2>; + status = "disabled"; + }; + + pit0_channel3: pit0_channel@3 { + compatible = "nxp,pit-channel"; + reg = <3>; + status = "disabled"; + }; + + pit0_channel4: pit0_channel@4 { + compatible = "nxp,pit-channel"; + reg = <4>; + status = "disabled"; + }; + + pit0_channel5: pit0_channel@5 { + compatible = "nxp,pit-channel"; + reg = <5>; + status = "disabled"; + }; }; }; }; diff --git a/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi index c7831a241a4..6649a44714f 100644 --- a/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi @@ -95,6 +95,44 @@ clocks = <&clock NXP_S32_P1_REG_INTF_CLK>; max-load-value = <0x00ffffff>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + pit0_channel0: pit0_channel@0 { + compatible = "nxp,pit-channel"; + reg = <0>; + status = "disabled"; + }; + + pit0_channel1: pit0_channel@1 { + compatible = "nxp,pit-channel"; + reg = <1>; + status = "disabled"; + }; + + pit0_channel2: pit0_channel@2 { + compatible = "nxp,pit-channel"; + reg = <2>; + status = "disabled"; + }; + + pit0_channel3: pit0_channel@3 { + compatible = "nxp,pit-channel"; + reg = <3>; + status = "disabled"; + }; + + pit0_channel4: pit0_channel@4 { + compatible = "nxp,pit-channel"; + reg = <4>; + status = "disabled"; + }; + + pit0_channel5: pit0_channel@5 { + compatible = "nxp,pit-channel"; + reg = <5>; + status = "disabled"; + }; }; }; }; diff --git a/dts/bindings/counter/nxp,pit-channel.yaml b/dts/bindings/counter/nxp,pit-channel.yaml new file mode 100644 index 00000000000..b543916ed1d --- /dev/null +++ b/dts/bindings/counter/nxp,pit-channel.yaml @@ -0,0 +1,13 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier Apache-2.0 + +description: | + Child node for the Periodic Interrupt Timer node, intended for an individual timer channel + +compatible: "nxp,pit-channel" + +include: base.yaml + +properties: + reg: + required: true diff --git a/dts/bindings/counter/nxp,pit.yaml b/dts/bindings/counter/nxp,pit.yaml index 33006393c29..e9e304168a0 100644 --- a/dts/bindings/counter/nxp,pit.yaml +++ b/dts/bindings/counter/nxp,pit.yaml @@ -14,16 +14,6 @@ properties: clocks: required: true - pit-channel: - type: int - required: true - description: pit channel to active - - pit-period: - type: int - required: true - description: pit default period in us - max-load-value: type: int required: true diff --git a/tests/drivers/adc/adc_dma/boards/frdm_k64f.overlay b/tests/drivers/adc/adc_dma/boards/frdm_k64f.overlay index 0fb2499796d..9de772a5b98 100644 --- a/tests/drivers/adc/adc_dma/boards/frdm_k64f.overlay +++ b/tests/drivers/adc/adc_dma/boards/frdm_k64f.overlay @@ -15,4 +15,8 @@ dma-buf-addr-alignment = <4>; }; +&pit0_channel0 { + status = "okay"; +}; + test_dma: &edma0 { }; diff --git a/tests/drivers/adc/adc_dma/boards/frdm_k82f.overlay b/tests/drivers/adc/adc_dma/boards/frdm_k82f.overlay index b9d8e681122..b2250c934ef 100644 --- a/tests/drivers/adc/adc_dma/boards/frdm_k82f.overlay +++ b/tests/drivers/adc/adc_dma/boards/frdm_k82f.overlay @@ -15,4 +15,8 @@ dma-buf-addr-alignment = <4>; }; +&pit0_channel0 { + status = "okay"; +}; + test_dma: &edma0 { }; diff --git a/tests/drivers/counter/counter_basic_api/boards/frdm_k64f.overlay b/tests/drivers/counter/counter_basic_api/boards/frdm_k64f.overlay new file mode 100644 index 00000000000..8c315523223 --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/frdm_k64f.overlay @@ -0,0 +1,19 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pit0_channel0 { + status = "okay"; +}; + +&pit0_channel1 { + status = "okay"; +}; + +/* channel 2 disabled to test disabled channel not breaking things */ + +&pit0_channel3 { + status = "okay"; +}; diff --git a/tests/drivers/counter/counter_basic_api/boards/frdm_k82f.overlay b/tests/drivers/counter/counter_basic_api/boards/frdm_k82f.overlay new file mode 100644 index 00000000000..8c315523223 --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/frdm_k82f.overlay @@ -0,0 +1,19 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pit0_channel0 { + status = "okay"; +}; + +&pit0_channel1 { + status = "okay"; +}; + +/* channel 2 disabled to test disabled channel not breaking things */ + +&pit0_channel3 { + status = "okay"; +}; diff --git a/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay index d35e70e8a12..bfb4087f17d 100644 --- a/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay +++ b/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay @@ -1,5 +1,5 @@ /* - * Copyright 2022-2023 NXP + * Copyright 2022-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,7 +25,9 @@ }; &pit0 { - pit-channel = <0>; - pit-period = <1000000>; + status = "okay"; +}; + +&pit0_channel0 { status = "okay"; }; diff --git a/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay index d35e70e8a12..bfb4087f17d 100644 --- a/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay +++ b/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay @@ -1,5 +1,5 @@ /* - * Copyright 2022-2023 NXP + * Copyright 2022-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,7 +25,9 @@ }; &pit0 { - pit-channel = <0>; - pit-period = <1000000>; + status = "okay"; +}; + +&pit0_channel0 { status = "okay"; }; diff --git a/tests/drivers/counter/counter_basic_api/src/test_counter.c b/tests/drivers/counter/counter_basic_api/src/test_counter.c index d54363a4931..defa820ffde 100644 --- a/tests/drivers/counter/counter_basic_api/src/test_counter.c +++ b/tests/drivers/counter/counter_basic_api/src/test_counter.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -85,7 +86,7 @@ static const struct device *const devices[] = { DEVS_FOR_DT_COMPAT(silabs_gecko_stimer) #endif #ifdef CONFIG_COUNTER_NXP_PIT - DEVS_FOR_DT_COMPAT(nxp_pit) + DEVS_FOR_DT_COMPAT(nxp_pit_channel) #endif #ifdef CONFIG_COUNTER_XLNX_AXI_TIMER DEVS_FOR_DT_COMPAT(xlnx_xps_timer_1_00_a) From 9815296500e37c4dd46bd8518daa36ad9b853c1c Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Fri, 2 Feb 2024 11:06:11 -0600 Subject: [PATCH 0320/2402] dts: arm: Enabling pit for imx devices Enabled the PIT and Multi channel support for some of the rtXXXX devices. - rt1010 - rt1060 - rt1160 - rt1170 Signed-off-by: Emilio Benavente --- boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts | 6 +- boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts | 6 +- .../mimxrt1160_evk_mimxrt1166_cm7.dts | 10 ++- .../mimxrt1170_evk_mimxrt1176_cm7.dts | 10 ++- .../clock_control/clock_control_mcux_ccm.c | 7 +- .../clock_control_mcux_ccm_rev2.c | 7 +- dts/arm/nxp/nxp_rt1010.dtsi | 4 ++ dts/arm/nxp/nxp_rt10xx.dtsi | 35 ++++++++++ dts/arm/nxp/nxp_rt11xx.dtsi | 66 +++++++++++++++++++ include/zephyr/dt-bindings/clock/imx_ccm.h | 4 +- .../zephyr/dt-bindings/clock/imx_ccm_rev2.h | 5 +- soc/nxp/imxrt/imxrt11xx/soc.c | 6 +- .../boards/mimxrt1010_evk.overlay | 13 ++++ .../boards/mimxrt1060_evk.overlay | 20 ++++++ .../mimxrt1160_evk_mimxrt1166_cm7.overlay | 33 ++++++++++ .../mimxrt1170_evk_mimxrt1176_cm7.overlay | 33 ++++++++++ 16 files changed, 256 insertions(+), 9 deletions(-) create mode 100644 tests/drivers/counter/counter_basic_api/boards/mimxrt1010_evk.overlay create mode 100644 tests/drivers/counter/counter_basic_api/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay create mode 100644 tests/drivers/counter/counter_basic_api/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts index 330de94d692..39b65271fd4 100644 --- a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts @@ -1,6 +1,6 @@ /* * Copyright (c) 2023 TiaC Systems - * Copyright 2019,2023 NXP + * Copyright 2019,2023-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -176,3 +176,7 @@ zephyr_udc0: &usb1 { &systick { status = "okay"; }; + +&pit0 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts index 6e90b878717..0eed6e4fc2b 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NXP + * Copyright 2018,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -288,3 +288,7 @@ arduino_spi: &lpspi1 { &pxp { status = "okay"; }; + +&pit0 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts index 2ed0a1cc23a..010d8e98af9 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, NXP + * Copyright 2021,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -100,3 +100,11 @@ zephyr_udc0: &usb1 { &mailbox_a { status = "okay"; }; + +&pit1 { + status = "okay"; +}; + +&pit2 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts index 48564a03b4d..4040cd63676 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts @@ -1,5 +1,5 @@ /* - * Copyright 2021-22, NXP + * Copyright 2021-2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -148,3 +148,11 @@ zephyr_udc0: &usb1 { &mailbox_a { status = "okay"; }; + +&pit1 { + status = "okay"; +}; + +&pit2 { + status = "okay"; +}; diff --git a/drivers/clock_control/clock_control_mcux_ccm.c b/drivers/clock_control/clock_control_mcux_ccm.c index 14959446d89..82f3c1310f3 100644 --- a/drivers/clock_control/clock_control_mcux_ccm.c +++ b/drivers/clock_control/clock_control_mcux_ccm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NXP + * Copyright 2017,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -326,6 +326,11 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, case IMX_CCM_FLEXSPI2_CLK: *rate = CLOCK_GetClockRootFreq(kCLOCK_Flexspi2ClkRoot); break; +#endif +#ifdef CONFIG_COUNTER_NXP_PIT + case IMX_CCM_PIT_CLK: + *rate = CLOCK_GetFreq(kCLOCK_PerClk); + break; #endif } diff --git a/drivers/clock_control/clock_control_mcux_ccm_rev2.c b/drivers/clock_control/clock_control_mcux_ccm_rev2.c index a30a3b93491..877d43fc7cd 100644 --- a/drivers/clock_control/clock_control_mcux_ccm_rev2.c +++ b/drivers/clock_control/clock_control_mcux_ccm_rev2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, NXP + * Copyright 2021,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -140,6 +140,11 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, case IMX_CCM_FLEXSPI2_CLK: clock_root = kCLOCK_Root_Flexspi2; break; +#endif +#ifdef CONFIG_COUNTER_NXP_PIT + case IMX_CCM_PIT_CLK: + clock_root = kCLOCK_Root_Bus + instance; + break; #endif default: return -EINVAL; diff --git a/dts/arm/nxp/nxp_rt1010.dtsi b/dts/arm/nxp/nxp_rt1010.dtsi index f9f06dc56d0..97ae6aa95c0 100644 --- a/dts/arm/nxp/nxp_rt1010.dtsi +++ b/dts/arm/nxp/nxp_rt1010.dtsi @@ -386,3 +386,7 @@ &gpio5{ pinmux = <&iomuxc_snvs_pmic_on_req_gpio5_io00>; }; + +&pit0 { + interrupts = <24 0>; +}; diff --git a/dts/arm/nxp/nxp_rt10xx.dtsi b/dts/arm/nxp/nxp_rt10xx.dtsi index 3bc5749f271..39486d0b76b 100644 --- a/dts/arm/nxp/nxp_rt10xx.dtsi +++ b/dts/arm/nxp/nxp_rt10xx.dtsi @@ -1087,6 +1087,41 @@ reg = <0x400d8000 0x2a0>; status = "disabled"; }; + + pit0: pit@40084000 { + compatible = "nxp,pit"; + reg = <0x40084000 0x1000>; + clocks = <&ccm IMX_CCM_PIT_CLK 0x0 0>; + interrupts = <122 0>; + max-load-value = <0xffffffff>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + pit0_channel0: pit0_channel@0 { + compatible = "nxp,pit-channel"; + reg = <0>; + status = "disabled"; + }; + + pit0_channel1: pit0_channel@1 { + compatible = "nxp,pit-channel"; + reg = <1>; + status = "disabled"; + }; + + pit0_channel2: pit0_channel@2 { + compatible = "nxp,pit-channel"; + reg = <2>; + status = "disabled"; + }; + + pit0_channel3: pit0_channel@3 { + compatible = "nxp,pit-channel"; + reg = <3>; + status = "disabled"; + }; + }; }; }; diff --git a/dts/arm/nxp/nxp_rt11xx.dtsi b/dts/arm/nxp/nxp_rt11xx.dtsi index 6216b32cb46..b4782ca8755 100644 --- a/dts/arm/nxp/nxp_rt11xx.dtsi +++ b/dts/arm/nxp/nxp_rt11xx.dtsi @@ -1127,6 +1127,72 @@ status = "disabled"; }; + pit1: pit@400D8000 { + compatible = "nxp,pit"; + reg = <0x400D8000 0x4000>; + clocks = <&ccm IMX_CCM_PIT_CLK 0x0 0>; + interrupts = <155 0>; + max-load-value = <0xffffffff>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + pit1_channel0: pit1_channel@0 { + compatible = "nxp,pit-channel"; + reg = <0>; + status = "disabled"; + }; + + pit1_channel1: pit1_channel@1 { + compatible = "nxp,pit-channel"; + reg = <1>; + status = "disabled"; + }; + + pit1_channel2: pit1_channel@2 { + compatible = "nxp,pit-channel"; + reg = <2>; + status = "disabled"; + }; + + pit1_channel3: pit1_channel@3 { + compatible = "nxp,pit-channel"; + reg = <3>; + status = "disabled"; + }; + }; + + pit2: pit@40CB0000 { + compatible = "nxp,pit"; + reg = <0x40CB0000 0x4000>; + clocks = <&ccm IMX_CCM_PIT1_CLK 0x0 0>; + interrupts = <156 0>; + max-load-value = <0xffffffff>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + pit2_channel0: pit2_channel@0 { + compatible = "nxp,pit-channel"; + reg = <0>; + status = "disabled"; + }; + pit2_channel1: pit2_channel@1 { + compatible = "nxp,pit-channel"; + reg = <1>; + status = "disabled"; + }; + pit2_channel2: pit2_channel@2 { + compatible = "nxp,pit-channel"; + reg = <2>; + status = "disabled"; + }; + pit2_channel3: pit2_channel@3 { + compatible = "nxp,pit-channel"; + reg = <2>; + status = "disabled"; + }; + }; }; }; diff --git a/include/zephyr/dt-bindings/clock/imx_ccm.h b/include/zephyr/dt-bindings/clock/imx_ccm.h index b20d1e5aecb..5ad08306be4 100644 --- a/include/zephyr/dt-bindings/clock/imx_ccm.h +++ b/include/zephyr/dt-bindings/clock/imx_ccm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, NXP + * Copyright 2017-2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -61,4 +61,6 @@ #define IMX_CCM_FLEXSPI_CLK 0x0F00UL #define IMX_CCM_FLEXSPI2_CLK 0x0F01UL +#define IMX_CCM_PIT_CLK 0x1000UL + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */ diff --git a/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h b/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h index c36d140b534..0ea1019a75f 100644 --- a/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h +++ b/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, NXP + * Copyright 2021,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -95,5 +95,8 @@ /* FLEXSPI */ #define IMX_CCM_FLEXSPI_CLK 0x4000UL #define IMX_CCM_FLEXSPI2_CLK 0x4001UL +/* PIT */ +#define IMX_CCM_PIT_CLK 0x5000UL +#define IMX_CCM_PIT1_CLK 0x5001UL #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ */ diff --git a/soc/nxp/imxrt/imxrt11xx/soc.c b/soc/nxp/imxrt/imxrt11xx/soc.c index 065039f38a2..9eee69ad66a 100644 --- a/soc/nxp/imxrt/imxrt11xx/soc.c +++ b/soc/nxp/imxrt/imxrt11xx/soc.c @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 NXP + * Copyright 2021-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -346,6 +346,10 @@ static ALWAYS_INLINE void clock_init(void) rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; rootCfg.div = 4; CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); +#elif defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) + rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); #endif /* Configure CSSYS using OSC_RC_48M_DIV2 */ diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1010_evk.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1010_evk.overlay new file mode 100644 index 00000000000..691f93d69ac --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/mimxrt1010_evk.overlay @@ -0,0 +1,13 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pit0_channel0 { + status = "okay"; +}; + +&pit0_channel1 { + status = "okay"; +}; diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk.overlay index 498db19c3f2..8a3cee91a43 100644 --- a/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk.overlay +++ b/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk.overlay @@ -1,3 +1,23 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pit0_channel0 { + status = "okay"; +}; + +&pit0_channel1 { + status = "okay"; +}; + +/* channel 2 disabled to test disabled channel not breaking things */ + +&pit0_channel3 { + status = "okay"; +}; + &qtmr1_timer0 { status = "okay"; primary_source = "kQTMR_ClockDivide_128"; diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay new file mode 100644 index 00000000000..561b27b5b93 --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -0,0 +1,33 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pit1_channel0 { + status = "okay"; +}; + +&pit1_channel1 { + status = "okay"; +}; + +/* channel 2 disabled to test disabled channel not breaking things */ + +&pit1_channel3 { + status = "okay"; +}; + +&pit2_channel0 { + status = "okay"; +}; + +&pit2_channel1 { + status = "okay"; +}; + +/* channel 2 disabled to test disabled channel not breaking things */ + +&pit2_channel3 { + status = "okay"; +}; diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay new file mode 100644 index 00000000000..561b27b5b93 --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay @@ -0,0 +1,33 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pit1_channel0 { + status = "okay"; +}; + +&pit1_channel1 { + status = "okay"; +}; + +/* channel 2 disabled to test disabled channel not breaking things */ + +&pit1_channel3 { + status = "okay"; +}; + +&pit2_channel0 { + status = "okay"; +}; + +&pit2_channel1 { + status = "okay"; +}; + +/* channel 2 disabled to test disabled channel not breaking things */ + +&pit2_channel3 { + status = "okay"; +}; From 25830e3828ccbb05789476ef3d9d1261588f8ad0 Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Wed, 10 Jan 2024 16:02:05 -0600 Subject: [PATCH 0321/2402] boards: arm: Updated the board docs for pit Updated the board documentation to reflect the enablement of the PIT peripheral. Signed-off-by: Emilio Benavente --- boards/nxp/frdm_k64f/doc/index.rst | 2 ++ boards/nxp/frdm_k82f/doc/index.rst | 2 ++ boards/nxp/mimxrt1010_evk/doc/index.rst | 2 ++ boards/nxp/mimxrt1060_evk/doc/index.rst | 2 ++ boards/nxp/mimxrt1160_evk/doc/index.rst | 2 ++ boards/nxp/mimxrt1170_evk/doc/index.rst | 2 ++ 6 files changed, 12 insertions(+) diff --git a/boards/nxp/frdm_k64f/doc/index.rst b/boards/nxp/frdm_k64f/doc/index.rst index 97c158804ee..f144fa0ce97 100644 --- a/boards/nxp/frdm_k64f/doc/index.rst +++ b/boards/nxp/frdm_k64f/doc/index.rst @@ -110,6 +110,8 @@ configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | FTFE | on-chip | flash programming | +-----------+------------+-------------------------------------+ +| PIT | on-chip | pit | ++-----------+------------+-------------------------------------+ The default configuration can be found in :zephyr_file:`boards/nxp/frdm_k64f/frdm_k64f_defconfig` diff --git a/boards/nxp/frdm_k82f/doc/index.rst b/boards/nxp/frdm_k82f/doc/index.rst index 71e6e5133fc..f306dc6dada 100644 --- a/boards/nxp/frdm_k82f/doc/index.rst +++ b/boards/nxp/frdm_k82f/doc/index.rst @@ -104,6 +104,8 @@ already supported, which can also be re-used on this frdm_k82f board: +-----------+------------+-------------------------------------+ | FTFA | on-chip | flash programming | +-----------+------------+-------------------------------------+ +| PIT | on-chip | pit | ++-----------+------------+-------------------------------------+ The default configuration can be found in :zephyr_file:`boards/nxp/frdm_k82f/frdm_k82f_defconfig` diff --git a/boards/nxp/mimxrt1010_evk/doc/index.rst b/boards/nxp/mimxrt1010_evk/doc/index.rst index 6c1eac7a6ff..df15589a0a8 100644 --- a/boards/nxp/mimxrt1010_evk/doc/index.rst +++ b/boards/nxp/mimxrt1010_evk/doc/index.rst @@ -98,6 +98,8 @@ already supported, which can also be re-used on this mimxrt1010_evk board: +-----------+------------+-------------------------------------+ | TRNG | on-chip | entropy | +-----------+------------+-------------------------------------+ +| PIT | on-chip | pit | ++-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: ``boards/arm/mimxrt1010_evk/mimxrt1010_evk_defconfig`` diff --git a/boards/nxp/mimxrt1060_evk/doc/index.rst b/boards/nxp/mimxrt1060_evk/doc/index.rst index de0943ce83c..94d76f49245 100644 --- a/boards/nxp/mimxrt1060_evk/doc/index.rst +++ b/boards/nxp/mimxrt1060_evk/doc/index.rst @@ -150,6 +150,8 @@ already supported, which can also be re-used on this mimxrt1060_evk board: +-----------+------------+-------------------------------------+ | FLEXSPI | on-chip | flash programming | +-----------+------------+-------------------------------------+ +| PIT | on-chip | pit | ++-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: ``boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig`` diff --git a/boards/nxp/mimxrt1160_evk/doc/index.rst b/boards/nxp/mimxrt1160_evk/doc/index.rst index 501182df322..ca680d0a103 100644 --- a/boards/nxp/mimxrt1160_evk/doc/index.rst +++ b/boards/nxp/mimxrt1160_evk/doc/index.rst @@ -143,6 +143,8 @@ already supported, which can also be re-used on this mimxrt1160_evk board: +-----------+------------+-------------------------------------+ | FLEXSPI | on-chip | flash programming | +-----------+------------+-------------------------------------+ +| PIT | on-chip | pit | ++-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: :zephyr_file:`boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig` diff --git a/boards/nxp/mimxrt1170_evk/doc/index.rst b/boards/nxp/mimxrt1170_evk/doc/index.rst index 40dffaba765..13b8d795c16 100644 --- a/boards/nxp/mimxrt1170_evk/doc/index.rst +++ b/boards/nxp/mimxrt1170_evk/doc/index.rst @@ -166,6 +166,8 @@ RT1170 EVKB (`mimxrt1170_evk@B//cm7/cm4`) +-----------+------------+-------------------------------------+-----------------+-----------------+ | SDHC | on-chip | SD host controller | Supported (M7) | Supported (M7) | +-----------+------------+-------------------------------------+-----------------+-----------------+ +| PIT | on-chip | pit | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ The default configuration can be found in the defconfig files: :zephyr_file:`boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig` From 35502592a7c702954697660f390b46e4912f8c56 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Thu, 7 Mar 2024 13:13:57 +0100 Subject: [PATCH 0322/2402] drivers: input: Fix uninitialized closest_mv variable warning Building with GCC 9.4.0 gives the following warning/error: error: closest_mv may be used uninitialized in this function This commit fixes it. Signed-off-by: Robert Lubos --- drivers/input/input_adc_keys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/input_adc_keys.c b/drivers/input/input_adc_keys.c index 2e24ffd097d..d37d79bf098 100644 --- a/drivers/input/input_adc_keys.c +++ b/drivers/input/input_adc_keys.c @@ -70,7 +70,7 @@ static inline int32_t adc_keys_read(const struct device *dev) static inline void adc_keys_process(const struct device *dev) { const struct adc_keys_config *cfg = dev->config; - int32_t sample_mv, closest_mv; + int32_t sample_mv, closest_mv = 0; uint32_t diff, closest_diff = UINT32_MAX; const struct adc_keys_code_config *code_cfg; struct adc_keys_key_state *key_state; From c08b66cfeebfe6faf2171fad0bcbebece5bc838d Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Thu, 8 Feb 2024 17:08:43 +0100 Subject: [PATCH 0323/2402] drivers: adc: set name for acquisition thread of MCP320x Set the name of the acquisition thread for the ADC MCP320x. Signed-off-by: Benedikt Schmidt --- drivers/adc/adc_mcp320x.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/adc/adc_mcp320x.c b/drivers/adc/adc_mcp320x.c index 71ba54bd3af..7fc0e421fd8 100644 --- a/drivers/adc/adc_mcp320x.c +++ b/drivers/adc/adc_mcp320x.c @@ -283,13 +283,15 @@ static int mcp320x_init(const struct device *dev) return -ENODEV; } - k_thread_create(&data->thread, data->stack, + k_tid_t tid = k_thread_create(&data->thread, data->stack, K_KERNEL_STACK_SIZEOF(data->stack), mcp320x_acquisition_thread, data, NULL, NULL, CONFIG_ADC_MCP320X_ACQUISITION_THREAD_PRIO, 0, K_NO_WAIT); + k_thread_name_set(tid, dev->name); + adc_context_unlock_unconditionally(&data->ctx); return 0; From fd5c76ddfdfe4c0e32c77f5baaf0bc62c8c8d950 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Thu, 7 Mar 2024 11:35:04 +0200 Subject: [PATCH 0324/2402] drivers: modem_cellular: allow leaving out the chat_filter parameter Allow not specifying the chat_filter parameter in a device definition, which is equivalent to setting it to "". Signed-off-by: Tomi Fontanilles --- drivers/modem/modem_cellular.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 276c9d38f7b..15f10f11a52 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -1516,7 +1516,7 @@ static int modem_cellular_init(const struct device *dev) .delimiter = data->chat_delimiter, .delimiter_size = strlen(data->chat_delimiter), .filter = data->chat_filter, - .filter_size = strlen(data->chat_filter), + .filter_size = data->chat_filter ? strlen(data->chat_filter) : 0, .argv = data->chat_argv, .argv_size = ARRAY_SIZE(data->chat_argv), .unsol_matches = unsol_matches, From 328ff9ac454aeae3f04e87b17aab545744bc4fa9 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Thu, 7 Mar 2024 10:06:53 +0100 Subject: [PATCH 0325/2402] tests: llext: Set min_ram requirement for readonly_mpu variant Set the minimal RAM requirement for the test variant, so that it does not get built for platforms it won't fit anyway. Signed-off-by: Robert Lubos --- tests/subsys/llext/hello_world/testcase.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/subsys/llext/hello_world/testcase.yaml b/tests/subsys/llext/hello_world/testcase.yaml index 391e2f81c92..d270e568798 100644 --- a/tests/subsys/llext/hello_world/testcase.yaml +++ b/tests/subsys/llext/hello_world/testcase.yaml @@ -13,6 +13,7 @@ tests: - arch:arm:CONFIG_ARM_MPU=n - CONFIG_LLEXT_STORAGE_WRITABLE=n llext.simple.readonly_mpu: + min_ram: 128 arch_exclude: xtensa # for now filter: CONFIG_CPU_HAS_MPU extra_configs: From 959680166afbae548ee2e915e450353f76aa9f4d Mon Sep 17 00:00:00 2001 From: Eve Redero Date: Tue, 5 Mar 2024 16:19:44 +0100 Subject: [PATCH 0326/2402] doc: drivers: gpio: detail scancodes from example Add more explanation and details on how to use USB HID scancodes in gpio-emul-sdl implementation. Signed-off-by: Eve Redero --- dts/bindings/gpio/zephyr,gpio-emul-sdl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/dts/bindings/gpio/zephyr,gpio-emul-sdl.yaml b/dts/bindings/gpio/zephyr,gpio-emul-sdl.yaml index a6c56733444..5a2ed9992ad 100644 --- a/dts/bindings/gpio/zephyr,gpio-emul-sdl.yaml +++ b/dts/bindings/gpio/zephyr,gpio-emul-sdl.yaml @@ -8,10 +8,19 @@ description: | to be a child of a `zephyr,gpio-emul` compatible. Add a list of scancodes for the desired keys to be mapped. + This driver uses USB HID scancodes, they are different from linux key codes, + and thus do not match Zephyr code values as described in input-event-codes.h. Refer to https://www.usb.org/sites/default/files/documents/hut1_12v2.pdf section Keyboard/Keypad (p53) for a list of scancode values. The following example maps the first 3 numeric keys to GPIO pins: + - Scancode 30: "Keyboard 1 and !", mapped to gpio0 0 + - Scancode 31: "Keyboard 2 and @", mapped to gpio0 1 + - Scancode 32: "Keyboard 3 and \#", mapped to gpio0 2 + + The "typical position" column from HID table suggests to match them + with standard keycode values 2, 3 and 4, corresponding to + INPUT_KEY_1, INPUT_KEY_2 and INPUT_KEY_3 in input-event-codes.h. /* gpio0 has to be a zephyr,gpio-emul device */ &gpio0 { From 03fce7dd3cdccef4538745ac9301a10557f483f2 Mon Sep 17 00:00:00 2001 From: Gang Li Date: Wed, 6 Mar 2024 19:54:18 +0800 Subject: [PATCH 0327/2402] net: zperf: Fix multicast data failure to receive server's AckFIN packet In iperf2, for multicast data, if it is a client, it will not wait for the server's AckFIN packet. Because the iperf2 server will not send an AckFIN packet. So in zperf_upload_fin(), an error will occur when the zperf client waits for the server's AckFIN packet. Multicast only send the negative sequence number packet and doesn't wait for a server ack can fix this issue. Signed-off-by: Gang Li --- subsys/net/lib/zperf/zperf_udp_uploader.c | 56 +++++++++++++++-------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/subsys/net/lib/zperf/zperf_udp_uploader.c b/subsys/net/lib/zperf/zperf_udp_uploader.c index 50d15534061..49c211ba73c 100644 --- a/subsys/net/lib/zperf/zperf_udp_uploader.c +++ b/subsys/net/lib/zperf/zperf_udp_uploader.c @@ -50,7 +50,8 @@ static inline int zperf_upload_fin(int sock, uint32_t nb_packets, uint64_t end_time, uint32_t packet_size, - struct zperf_results *results) + struct zperf_results *results, + bool is_mcast_pkt) { uint8_t stats[sizeof(struct zperf_udp_datagram) + sizeof(struct zperf_server_hdr)] = { 0 }; @@ -96,19 +97,24 @@ static inline int zperf_upload_fin(int sock, continue; } - /* Receive statistics */ - ret = zsock_setsockopt(sock, SOL_SOCKET, SO_RCVTIMEO, &rcvtimeo, - sizeof(rcvtimeo)); - if (ret < 0) { - NET_ERR("setsockopt error (%d)", errno); - continue; - } + /* Multicast only send the negative sequence number packet + * and doesn't wait for a server ack + */ + if (!is_mcast_pkt) { + /* Receive statistics */ + ret = zsock_setsockopt(sock, SOL_SOCKET, SO_RCVTIMEO, &rcvtimeo, + sizeof(rcvtimeo)); + if (ret < 0) { + NET_ERR("setsockopt error (%d)", errno); + continue; + } - ret = zsock_recv(sock, stats, sizeof(stats), 0); - if (ret == -EAGAIN) { - NET_WARN("Stats receive timeout"); - } else if (ret < 0) { - NET_ERR("Failed to receive packet (%d)", errno); + ret = zsock_recv(sock, stats, sizeof(stats), 0); + if (ret == -EAGAIN) { + NET_WARN("Stats receive timeout"); + } else if (ret < 0) { + NET_ERR("Failed to receive packet (%d)", errno); + } } } @@ -133,11 +139,12 @@ static inline int zperf_upload_fin(int sock, } static int udp_upload(int sock, int port, - unsigned int duration_in_ms, - unsigned int packet_size, - unsigned int rate_in_kbps, + const struct zperf_upload_params *param, struct zperf_results *results) { + uint32_t duration_in_ms = param->duration_ms; + uint32_t packet_size = param->packet_size; + uint32_t rate_in_kbps = param->rate_kbps; uint32_t packet_duration_us = zperf_packet_duration(packet_size, rate_in_kbps); uint32_t packet_duration = k_us_to_ticks_ceil32(packet_duration_us); uint32_t delay = packet_duration; @@ -145,6 +152,7 @@ static int udp_upload(int sock, int port, int64_t start_time, end_time; int64_t print_time, last_loop_time; uint32_t print_period; + bool is_mcast_pkt = false; int ret; if (packet_size > PACKET_SIZE_MAX) { @@ -248,8 +256,19 @@ static int udp_upload(int sock, int port, end_time = k_uptime_ticks(); + if (param->peer_addr.sa_family == AF_INET) { + if (net_ipv4_is_addr_mcast(&net_sin(¶m->peer_addr)->sin_addr)) { + is_mcast_pkt = true; + } + } else if (param->peer_addr.sa_family == AF_INET6) { + if (net_ipv6_is_addr_mcast(&net_sin6(¶m->peer_addr)->sin6_addr)) { + is_mcast_pkt = true; + } + } else { + return -EINVAL; + } ret = zperf_upload_fin(sock, nb_packets, end_time, packet_size, - results); + results, is_mcast_pkt); if (ret < 0) { return ret; } @@ -290,8 +309,7 @@ int zperf_udp_upload(const struct zperf_upload_params *param, return sock; } - ret = udp_upload(sock, port, param->duration_ms, param->packet_size, - param->rate_kbps, result); + ret = udp_upload(sock, port, param, result); zsock_close(sock); From 39f710136ef78e6b9e7e95e4e2f93045929f12e5 Mon Sep 17 00:00:00 2001 From: TaiJu Wu Date: Sat, 17 Feb 2024 01:06:16 +0800 Subject: [PATCH 0328/2402] sched: finalize_cancel_locked can early return The code `SYS_SLIST_FOR_EACH_CONTAINER_SAFE` just for remove work from `pending_cancels`. After removing work successfully, the function can return early. It is unnecessary to iterate continuously. Signed-off-by: TaiJu Wu --- kernel/work.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/work.c b/kernel/work.c index 11498c186d2..269e73465cb 100644 --- a/kernel/work.c +++ b/kernel/work.c @@ -141,9 +141,9 @@ static void finalize_cancel_locked(struct k_work *work) if (wc->work == work) { sys_slist_remove(&pending_cancels, prev, &wc->node); k_sem_give(&wc->sem); - } else { - prev = &wc->node; + break; } + prev = &wc->node; } } From 0a8cbb6a22c9e1415ff333b18c9ce3d64ee2a3b5 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 5 Mar 2024 23:17:19 +0530 Subject: [PATCH 0329/2402] net: mgmt: Handle loops in the linked list In case the same callback handler is added to the list twice, this can result in a loop. Fixes: #69825. Signed-off-by: Chaitanya Tata --- subsys/net/ip/net_mgmt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/subsys/net/ip/net_mgmt.c b/subsys/net/ip/net_mgmt.c index 106fbac49ed..d6cf10ad471 100644 --- a/subsys/net/ip/net_mgmt.c +++ b/subsys/net/ip/net_mgmt.c @@ -338,6 +338,9 @@ void net_mgmt_add_event_callback(struct net_mgmt_event_callback *cb) (void)k_mutex_lock(&net_mgmt_callback_lock, K_FOREVER); + /* Remove the callback if it already exists to avoid loop */ + sys_slist_find_and_remove(&event_callbacks, &cb->node); + sys_slist_prepend(&event_callbacks, &cb->node); mgmt_add_event_mask(cb->event_mask); From 5af6dfdd0ee62cd036fd81e42bba41dc6019fb20 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 6 Mar 2024 00:36:04 +0530 Subject: [PATCH 0330/2402] tests: Add a test for duplicate event handlers This will help to detect any issues with duplicate handlers, currently, it causes an infinite loop in the handler that processes the single linked list. Also, increase the stack size to pass the synchronous test case. Signed-off-by: Chaitanya Tata --- tests/net/mgmt/src/mgmt.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/tests/net/mgmt/src/mgmt.c b/tests/net/mgmt/src/mgmt.c index 15c23301b26..004b60adb97 100644 --- a/tests/net/mgmt/src/mgmt.c +++ b/tests/net/mgmt/src/mgmt.c @@ -33,7 +33,7 @@ static uint32_t throw_times; static uint32_t throw_sleep; static bool with_info; static bool with_static; -static K_THREAD_STACK_DEFINE(thrower_stack, 512 + CONFIG_TEST_EXTRA_STACK_SIZE); +static K_THREAD_STACK_DEFINE(thrower_stack, 1024 + CONFIG_TEST_EXTRA_STACK_SIZE); static struct k_thread thrower_thread_data; static struct k_sem thrower_lock; @@ -423,4 +423,37 @@ ZTEST(mgmt_fn_test_suite, test_mgmt) "test_synchronous_event_listener failed"); } +static K_SEM_DEFINE(wait_for_event_processing, 0, 1); + +static void net_mgmt_event_handler(struct net_mgmt_event_callback *cb, + uint32_t mgmt_event, struct net_if *iface) +{ + static int cb_call_count; + + ARG_UNUSED(cb); + ARG_UNUSED(iface); + ARG_UNUSED(mgmt_event); + + k_sem_give(&wait_for_event_processing); + cb_call_count++; + zassert_equal(cb_call_count, 1, "Too many calls to event callback"); +} + +ZTEST(mgmt_fn_test_suite, test_mgmt_duplicate_handler) +{ + struct net_mgmt_event_callback cb; + int ret; + + net_mgmt_init_event_callback(&cb, net_mgmt_event_handler, NET_EVENT_IPV6_ADDR_ADD); + net_mgmt_add_event_callback(&cb); + net_mgmt_add_event_callback(&cb); + + net_mgmt_event_notify(NET_EVENT_IPV6_ADDR_ADD, NULL); + + ret = k_sem_take(&wait_for_event_processing, K_MSEC(50)); + zassert_equal(ret, 0, "Event is not processed"); + + net_mgmt_del_event_callback(&cb); +} + ZTEST_SUITE(mgmt_fn_test_suite, NULL, NULL, NULL, NULL, NULL); From 005623df92b727f9fc615ca8fb7b84a809c8321f Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 4 Mar 2024 17:29:10 +0100 Subject: [PATCH 0331/2402] Bluetooth: Controller: nrf5_ppi.h: Use nrfx HAL to set PPI always Quite a few paths used only when there is Coded Phy support were still setting the PPI directly. Let's use the nRFx HAL for this so it works properly also in simulation. Signed-off-by: Alberto Escolar Piedras --- .../nordic/hal/nrf5/radio/radio_nrf5_ppi.h | 80 +++++++------------ 1 file changed, 30 insertions(+), 50 deletions(-) diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h index 60fd8944ac4..a2ce85d5f9b 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h @@ -383,12 +383,8 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void) #define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(index) \ (HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE + (index)) -#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT(chan) \ - NRF_PPI->CH[chan].EEP #define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(cc_offset) \ ((uint32_t)&(SW_SWITCH_TIMER->EVENTS_COMPARE[cc_offset])) -#define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK(chan) \ - NRF_PPI->CH[chan].TEP #define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(index) \ ((uint32_t)&(NRF_PPI->TASKS_CHG[SW_SWITCH_TIMER_TASK_GROUP(index)].DIS)) @@ -409,12 +405,8 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void) */ #define HAL_SW_SWITCH_RADIO_ENABLE_PPI(index) \ (HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE + (index)) -#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(chan) \ - NRF_PPI->CH[chan].EEP #define HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(cc_offset) \ ((uint32_t)&(SW_SWITCH_TIMER->EVENTS_COMPARE[cc_offset])) -#define HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_TASK(chan) \ - NRF_PPI->CH[chan].TEP #define HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_TX \ ((uint32_t)&(NRF_RADIO->TASKS_TXEN)) #define HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_RX \ @@ -533,44 +525,36 @@ static inline void hal_radio_sw_switch_cleanup(void) /* Cancel the SW switch timer running considering S8 timing: * wire the RADIO EVENTS_RATEBOOST event to SW_SWITCH_TIMER TASKS_CAPTURE task. */ -#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_EVT \ - NRF_PPI->CH[HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI].EEP #define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_EVT \ ((uint32_t)&(NRF_RADIO->EVENTS_RATEBOOST)) -#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_TASK \ - NRF_PPI->CH[HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI].TEP #define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_TASK(index) \ ((uint32_t)&(SW_SWITCH_TIMER->TASKS_CAPTURE[index])) static inline void hal_radio_sw_switch_coded_tx_config_set(uint8_t ppi_en, uint8_t ppi_dis, uint8_t cc_s2, uint8_t group_index) { - HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(ppi_en) = - HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(cc_s2); + nrf_ppi_event_endpoint_setup(NRF_PPI, ppi_en, + HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(cc_s2)); - HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_TASK(ppi_en) = - HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_TX; + nrf_ppi_task_endpoint_setup(NRF_PPI, ppi_en, + HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_TX); /* Wire the Group task disable * to the S2 EVENTS_COMPARE. */ - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT( - ppi_dis) = - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(cc_s2); + nrf_ppi_event_endpoint_setup(NRF_PPI, ppi_dis, + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(cc_s2)); - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK( - ppi_dis) = - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK( - group_index); + nrf_ppi_task_endpoint_setup(NRF_PPI, ppi_dis, + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(group_index)); /* Capture CC to cancel the timer that has assumed * S8 reception, if packet will be received in S2. */ - HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_EVT = - HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_EVT; - HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_TASK = - HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_TASK( - group_index); + nrf_ppi_event_endpoint_setup(NRF_PPI, HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI, + HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_EVT); + nrf_ppi_task_endpoint_setup(NRF_PPI, HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI, + HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_TASK(group_index)); nrf_ppi_channels_enable( NRF_PPI, @@ -581,20 +565,18 @@ static inline void hal_radio_sw_switch_coded_config_clear(uint8_t ppi_en, uint8_t ppi_dis, uint8_t cc_reg, uint8_t group_index) { /* Invalidate PPI used when RXing on LE Coded PHY. */ - HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT( - ppi_en) = 0; - HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_TASK( - ppi_en) = 0; + nrf_ppi_event_endpoint_setup(NRF_PPI, ppi_en, 0); + nrf_ppi_task_endpoint_setup(NRF_PPI, ppi_en, 0); } static inline void hal_radio_sw_switch_disable_group_clear(uint8_t ppi_dis, uint8_t cc_reg, uint8_t group_index) { /* Wire the Group task disable to the default EVENTS_COMPARE. */ - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT(ppi_dis) = - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(cc_reg); - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK(ppi_dis) = - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(group_index); + nrf_ppi_event_endpoint_setup(NRF_PPI, ppi_dis, + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(cc_reg)); + nrf_ppi_task_endpoint_setup(NRF_PPI, ppi_dis, + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(group_index)); } #else @@ -638,12 +620,8 @@ static inline void hal_radio_group_task_disable_ppi_setup(void) /* Cancel the SW switch timer running considering PHYEND delay compensation timing: * wire the RADIO EVENTS_CTEPRESENT event to SW_SWITCH_TIMER TASKS_CAPTURE task. */ -#define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_REGISTER_EVT \ - NRF_PPI->CH[HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI].EEP #define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_EVT \ ((uint32_t)&(NRF_RADIO->EVENTS_CTEPRESENT)) -#define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_REGISTER_TASK \ - NRF_PPI->CH[HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI].TEP #define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_TASK(index) \ ((uint32_t)&(SW_SWITCH_TIMER->TASKS_CAPTURE[index])) @@ -673,17 +651,19 @@ hal_radio_sw_switch_phyend_delay_compensation_config_set(uint8_t radio_enable_pp uint8_t phyend_delay_cc) { /* Wire EVENTS_COMPARE[] event to Radio TASKS_TXEN */ - HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(radio_enable_ppi) = - HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(phyend_delay_cc); + nrf_ppi_event_endpoint_setup(NRF_PPI, radio_enable_ppi, + HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(phyend_delay_cc)); - HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_TASK(radio_enable_ppi) = - HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_TX; + nrf_ppi_task_endpoint_setup(NRF_PPI, radio_enable_ppi, + HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_TX); /* Wire Radio CTEPRESENT event to cancel EVENTS_COMPARE[] timer */ - HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_REGISTER_EVT = - HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_EVT; - HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_REGISTER_TASK = - HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_TASK(phyend_delay_cc); + nrf_ppi_event_endpoint_setup(NRF_PPI, + HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI, + HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_EVT); + nrf_ppi_task_endpoint_setup(NRF_PPI, + HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI, + HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_TASK(phyend_delay_cc)); /* Enable CTEPRESENT event to disable EVENTS_COMPARE[] PPI channel */ nrf_ppi_channels_enable(NRF_PPI, @@ -704,8 +684,8 @@ hal_radio_sw_switch_phyend_delay_compensation_config_clear(uint8_t radio_enable_ uint8_t phyend_delay_cc) { /* Invalidate PPI used when */ - HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(radio_enable_ppi) = NRF_PPI_NONE; - HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_TASK(radio_enable_ppi) = NRF_PPI_NONE; + nrf_ppi_event_endpoint_setup(NRF_PPI, radio_enable_ppi, NRF_PPI_NONE); + nrf_ppi_task_endpoint_setup(NRF_PPI, radio_enable_ppi, NRF_PPI_NONE); /* Disable CTEPRESENT event to disable EVENTS_COMPARE[] PPI channel */ nrf_ppi_channels_disable(NRF_PPI, From 7ad69d968a45abf714c52bd01c8a3f8bec7efed3 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 5 Mar 2024 09:55:14 +0100 Subject: [PATCH 0332/2402] Bluetooth: Controller: nrf5_dppi.h: Use nrfx HAL to set subscriptions A few paths used only when there is Coded Phy support were still setting the subscribe registers directly. Let's use the nRFx HAL for this so it works properly also in simulation. Signed-off-by: Alberto Escolar Piedras --- .../nordic/hal/nrf5/radio/radio_nrf5_dppi.h | 25 ++++++------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h index 5783589592a..baf57d46653 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h @@ -415,13 +415,6 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void) & RADIO_PUBLISH_RATEBOOST_EN_Msk)) #define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_TASK(cc_reg) \ SW_SWITCH_TIMER->SUBSCRIBE_CAPTURE[cc_reg] -#define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_TASK \ - (((HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI << \ - TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) \ - & TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk) | \ - ((TIMER_SUBSCRIBE_CAPTURE_EN_Enabled << \ - TIMER_SUBSCRIBE_CAPTURE_EN_Pos) \ - & TIMER_SUBSCRIBE_CAPTURE_EN_Msk)) #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE) /* The 2 adjacent TIMER EVENTS_COMPARE event offsets used for implementing PHYEND delay compensation @@ -445,9 +438,6 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void) ((RADIO_PUBLISH_CTEPRESENT_EN_Enabled << RADIO_PUBLISH_CTEPRESENT_EN_Pos) & \ RADIO_PUBLISH_CTEPRESENT_EN_Msk)) -#define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_REGISTER_TASK(cc_reg) \ - SW_SWITCH_TIMER->SUBSCRIBE_CAPTURE[cc_reg] - #define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_TASK \ (((HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI \ << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) & \ @@ -608,9 +598,9 @@ static inline void hal_radio_sw_switch_coded_tx_config_set(uint8_t ppi_en, */ HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_EVT = HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_EVT; - HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_TASK( - SW_SWITCH_TIMER_EVTS_COMP(group_index)) = - HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_TASK; + nrf_timer_subscribe_set(SW_SWITCH_TIMER, + nrf_timer_capture_task_get(SW_SWITCH_TIMER_EVTS_COMP(group_index)), + HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI); nrf_dppi_channels_enable(NRF_DPPIC, BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI)); @@ -761,8 +751,9 @@ hal_radio_sw_switch_phyend_delay_compensation_config_set(uint8_t radio_enable_pp /* Wire Radio CTEPRESENT event to cancel EVENTS_COMPARE[] timer */ HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_REGISTER_EVT = HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_EVT; - HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_REGISTER_TASK(phyend_delay_cc) = - HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_TASK; + nrf_timer_subscribe_set(SW_SWITCH_TIMER, + nrf_timer_capture_task_get(phyend_delay_cc), + HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI); /* Enable CTEPRESENT event to disable EVENTS_COMPARE[] PPI channel */ nrf_dppi_channels_enable(NRF_DPPIC, @@ -789,8 +780,8 @@ hal_radio_sw_switch_phyend_delay_compensation_config_clear(uint8_t radio_enable_ */ HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(phyend_delay_cc) = NRF_PPI_NONE; - HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_REGISTER_TASK(phyend_delay_cc) = - NRF_PPI_NONE; + nrf_timer_subscribe_clear(SW_SWITCH_TIMER, + nrf_timer_capture_task_get(phyend_delay_cc)); /* Disable CTEPRESENT event to disable EVENTS_COMPARE[] PPI channel */ nrf_dppi_channels_disable(NRF_DPPIC, From f91323ee5da06fa8e26f47317a2dddb2d52da154 Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Tue, 5 Mar 2024 14:18:50 +0100 Subject: [PATCH 0333/2402] drivers: flash: Add flash driver for MRAM Basic driver utilizing the flash API for NVM operations on the nRF54H20. Signed-off-by: Grzegorz Swiderski --- drivers/flash/CMakeLists.txt | 1 + drivers/flash/Kconfig | 2 + drivers/flash/Kconfig.nrf_mram | 19 ++++ drivers/flash/soc_flash_nrf_mram.c | 177 +++++++++++++++++++++++++++++ 4 files changed, 199 insertions(+) create mode 100644 drivers/flash/Kconfig.nrf_mram create mode 100644 drivers/flash/soc_flash_nrf_mram.c diff --git a/drivers/flash/CMakeLists.txt b/drivers/flash/CMakeLists.txt index 4f21b2f65ed..98f24ff123c 100644 --- a/drivers/flash/CMakeLists.txt +++ b/drivers/flash/CMakeLists.txt @@ -129,3 +129,4 @@ zephyr_library_sources_ifdef(CONFIG_FLASH_JESD216 jesd216.c) zephyr_library_sources_ifdef(CONFIG_FLASH_INFINEON_CAT1 flash_ifx_cat1.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NUMAKER soc_flash_numaker.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_RRAM soc_flash_nrf_rram.c) +zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_MRAM soc_flash_nrf_mram.c) diff --git a/drivers/flash/Kconfig b/drivers/flash/Kconfig index 4731a628438..0c24890d44d 100644 --- a/drivers/flash/Kconfig +++ b/drivers/flash/Kconfig @@ -163,4 +163,6 @@ source "drivers/flash/Kconfig.ambiq" source "drivers/flash/Kconfig.nrf_rram" +source "drivers/flash/Kconfig.nrf_mram" + endif # FLASH diff --git a/drivers/flash/Kconfig.nrf_mram b/drivers/flash/Kconfig.nrf_mram new file mode 100644 index 00000000000..0ef65864a62 --- /dev/null +++ b/drivers/flash/Kconfig.nrf_mram @@ -0,0 +1,19 @@ +# +# Copyright (c) 2024 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_FLASH_NRF_MRAM + bool "Nordic Semiconductor flash driver for MRAM" + default y + depends on DT_HAS_NORDIC_MRAM_ENABLED + select FLASH_HAS_DRIVER_ENABLED + select FLASH_HAS_PAGE_LAYOUT + imply MPU_ALLOW_FLASH_WRITE if ARM_MPU + help + Enables Nordic Semiconductor flash driver for MRAM in direct write mode. + + Note that MRAM words are auto-erased when written to, but writing to a + pre-erased area is faster. Hence, the erase API is not required, but + it can be used to amortize write performance for some use cases. diff --git a/drivers/flash/soc_flash_nrf_mram.c b/drivers/flash/soc_flash_nrf_mram.c new file mode 100644 index 00000000000..9b33ee05d6f --- /dev/null +++ b/drivers/flash/soc_flash_nrf_mram.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include + +LOG_MODULE_REGISTER(flash_nrf_mram, CONFIG_FLASH_LOG_LEVEL); + +#define DT_DRV_COMPAT nordic_mram + +#define MRAM_START DT_INST_REG_ADDR(0) +#define MRAM_SIZE DT_INST_REG_SIZE(0) + +#define MRAM_WORD_SIZE 16 +#define MRAM_WORD_MASK 0xf + +#define WRITE_BLOCK_SIZE DT_INST_PROP_OR(0, write_block_size, MRAM_WORD_SIZE) +#define ERASE_BLOCK_SIZE DT_INST_PROP_OR(0, erase_block_size, WRITE_BLOCK_SIZE) + +#define ERASE_VALUE 0xff + +BUILD_ASSERT(MRAM_START > 0, "nordic,mram: start address expected to be non-zero"); +BUILD_ASSERT((ERASE_BLOCK_SIZE % WRITE_BLOCK_SIZE) == 0, + "erase-block-size expected to be a multiple of write-block-size"); + +/** + * @param[in,out] offset Relative offset into memory, from the driver API. + * @param[in] len Number of bytes for the intended operation. + * @param[in] must_align Require MRAM word alignment, if applicable. + * + * @return Absolute address in MRAM, or NULL if @p offset or @p len are not + * within bounds or appropriately aligned. + */ +static uintptr_t validate_and_map_addr(off_t offset, size_t len, bool must_align) +{ + if (unlikely(offset < 0 || offset >= MRAM_SIZE || len > MRAM_SIZE - offset)) { + LOG_ERR("invalid offset: %ld:%zu", offset, len); + return 0; + } + + const uintptr_t addr = MRAM_START + offset; + + if (WRITE_BLOCK_SIZE > 1 && must_align && + unlikely((addr % WRITE_BLOCK_SIZE) != 0 || (len % WRITE_BLOCK_SIZE) != 0)) { + LOG_ERR("invalid alignment: %p:%zu", (void *)addr, len); + return 0; + } + + return addr; +} + +/** + * @param[in] addr_end Last modified MRAM address (not inclusive). + */ +static void commit_changes(uintptr_t addr_end) +{ + /* Barrier following our last write. */ + barrier_dmem_fence_full(); + + if ((WRITE_BLOCK_SIZE & MRAM_WORD_MASK) == 0 || (addr_end & MRAM_WORD_MASK) == 0) { + /* Our last operation was MRAM word-aligned, so we're done. + * Note: if WRITE_BLOCK_SIZE is a multiple of MRAM_WORD_SIZE, + * then this was already checked in validate_and_map_addr(). + */ + return; + } + + /* Get the most significant byte (MSB) of the last MRAM word we were modifying. + * Writing to this byte makes the MRAM controller commit other pending writes to that word. + */ + addr_end |= MRAM_WORD_MASK; + + /* Issue a dummy write, since we didn't have anything to write here. + * Doing this lets us finalize our changes before we exit the driver API. + */ + sys_write8(sys_read8(addr_end), addr_end); +} + +static int nrf_mram_read(const struct device *dev, off_t offset, void *data, size_t len) +{ + ARG_UNUSED(dev); + + const uintptr_t addr = validate_and_map_addr(offset, len, false); + + if (!addr) { + return -EINVAL; + } + + LOG_DBG("read: %p:%zu", (void *)addr, len); + + memcpy(data, (void *)addr, len); + + return 0; +} + +static int nrf_mram_write(const struct device *dev, off_t offset, const void *data, size_t len) +{ + ARG_UNUSED(dev); + + const uintptr_t addr = validate_and_map_addr(offset, len, true); + + if (!addr) { + return -EINVAL; + } + + LOG_DBG("write: %p:%zu", (void *)addr, len); + + memcpy((void *)addr, data, len); + commit_changes(addr + len); + + return 0; +} + +static int nrf_mram_erase(const struct device *dev, off_t offset, size_t size) +{ + ARG_UNUSED(dev); + + const uintptr_t addr = validate_and_map_addr(offset, size, true); + + if (!addr) { + return -EINVAL; + } + + LOG_DBG("erase: %p:%zu", (void *)addr, size); + + memset((void *)addr, ERASE_VALUE, size); + commit_changes(addr + size); + + return 0; +} + +static const struct flash_parameters *nrf_mram_get_parameters(const struct device *dev) +{ + ARG_UNUSED(dev); + + static const struct flash_parameters parameters = { + .write_block_size = WRITE_BLOCK_SIZE, + .erase_value = ERASE_VALUE, + }; + + return ¶meters; +} + +#if defined(CONFIG_FLASH_PAGE_LAYOUT) +static void nrf_mram_page_layout(const struct device *dev, const struct flash_pages_layout **layout, + size_t *layout_size) +{ + ARG_UNUSED(dev); + + static const struct flash_pages_layout pages_layout = { + .pages_count = (MRAM_SIZE) / (ERASE_BLOCK_SIZE), + .pages_size = ERASE_BLOCK_SIZE, + }; + + *layout = &pages_layout; + *layout_size = 1; +} +#endif + +static const struct flash_driver_api nrf_mram_api = { + .read = nrf_mram_read, + .write = nrf_mram_write, + .erase = nrf_mram_erase, + .get_parameters = nrf_mram_get_parameters, +#if defined(CONFIG_FLASH_PAGE_LAYOUT) + .page_layout = nrf_mram_page_layout, +#endif +}; + +DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, NULL, POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY, + &nrf_mram_api); From beab89d6e82bce3de5ef827074e9273811949ddd Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Thu, 7 Mar 2024 15:59:15 +0100 Subject: [PATCH 0334/2402] dts: nordic: nrf54h20_enga: Add erase-block-size to mram1x The MRAM has no concept of erase blocks or pages, so this is treated as driver configuration. Signed-off-by: Grzegorz Swiderski --- dts/common/nordic/nrf54h20_enga.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi index 610fbd81587..70c994ccd06 100644 --- a/dts/common/nordic/nrf54h20_enga.dtsi +++ b/dts/common/nordic/nrf54h20_enga.dtsi @@ -96,6 +96,7 @@ mram1x: mram@e000000 { compatible = "nordic,mram"; reg = <0xe000000 DT_SIZE_K(2048)>; + erase-block-size = <4096>; write-block-size = <16>; }; From c22fa20bf5da58f1d930a0b15070563f3032f782 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Tue, 5 Mar 2024 14:44:31 +0200 Subject: [PATCH 0335/2402] MAINTAINERS: Add NXP DAI maintainer and collabs Add people at NXP working on DAI subsys and drivers. Signed-off-by: Daniel Baluta --- MAINTAINERS.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index aa00be3e9a8..29ed8607d37 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -1105,9 +1105,12 @@ Release Notes: status: maintained maintainers: - kv2019i + - LaurentiuM1234 collaborators: - lgirdwood - juimonen + - iuliana-prodan + - dbaluta files: - drivers/dai/ - doc/hardware/peripherals/audio/dai.rst From 6d99fc6d47a798e224fb2e23c6a0ac7d5be4bf8f Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 4 Mar 2024 16:51:39 +0100 Subject: [PATCH 0336/2402] tests: drivers: build_all: ethernet: Do not set NET_TEST The ethernet drivers can only be built if the NET_TEST option is not selected. Signed-off-by: Pieter De Gendt --- tests/drivers/build_all/ethernet/prj.conf | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/drivers/build_all/ethernet/prj.conf b/tests/drivers/build_all/ethernet/prj.conf index f20cbb1d088..400feb5c6fa 100644 --- a/tests/drivers/build_all/ethernet/prj.conf +++ b/tests/drivers/build_all/ethernet/prj.conf @@ -1,5 +1,4 @@ CONFIG_TEST=y -CONFIG_NET_TEST=y CONFIG_NETWORKING=y CONFIG_NET_L2_ETHERNET=y CONFIG_ENTROPY_GENERATOR=y From 2054b9f982b142d31a7e48f73308c3d26cc89ae7 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 4 Mar 2024 16:12:12 +0100 Subject: [PATCH 0337/2402] tests: drivers: build_all: ethernet: Move app overlay to spi Use the native_sim board to build ethernet drivers for spi devices and add an entry for the default testcase. Signed-off-by: Pieter De Gendt --- .../{app.overlay => spi_devices.overlay} | 0 .../drivers/build_all/ethernet/testcase.yaml | 24 +++++++++---------- 2 files changed, 11 insertions(+), 13 deletions(-) rename tests/drivers/build_all/ethernet/{app.overlay => spi_devices.overlay} (100%) diff --git a/tests/drivers/build_all/ethernet/app.overlay b/tests/drivers/build_all/ethernet/spi_devices.overlay similarity index 100% rename from tests/drivers/build_all/ethernet/app.overlay rename to tests/drivers/build_all/ethernet/spi_devices.overlay diff --git a/tests/drivers/build_all/ethernet/testcase.yaml b/tests/drivers/build_all/ethernet/testcase.yaml index 2cd4ff296c3..ae9e631f528 100644 --- a/tests/drivers/build_all/ethernet/testcase.yaml +++ b/tests/drivers/build_all/ethernet/testcase.yaml @@ -3,17 +3,15 @@ common: tags: - drivers - ethernet + depends_on: + - eth tests: - net.ethernet.build: - min_flash: 42 - min_ram: 32 - platform_exclude: - - frdm_kw41z - - mimxrt1020_evk - - mimxrt1024_evk - - mimxrt1050_evk - - mimxrt1060_evk - - mimxrt1064_evk - depends_on: - - spi - - netif + net.ethernet.build.default: {} + + net.ethernet.build.spi: + extra_args: DTC_OVERLAY_FILE="spi_devices.overlay" + extra_configs: + - CONFIG_SPI=y + platform_allow: + - native_sim + - native_sim_64 From d288452ce1ba0f42477f01577b3a0fe92f0124ef Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Tue, 5 Mar 2024 11:20:39 +0100 Subject: [PATCH 0338/2402] drivers: ethernet: eth_adin2111: Fix build warning on 64bit An overflow compiler warning is generated when building for native_sim_64, add an explicit cast to fix -Werror builds. Signed-off-by: Pieter De Gendt --- drivers/ethernet/eth_adin2111.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index e73beb891d4..5fd0e987362 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -903,7 +903,7 @@ static int adin2111_init(const struct device *dev) } /* configure interrupt masks */ - ctx->imask0 = ~ADIN2111_IMASK0_PHYINTM; + ctx->imask0 = ~((uint32_t)ADIN2111_IMASK0_PHYINTM); ctx->imask1 = ~(ADIN2111_IMASK1_TX_RDY_MASK | ADIN2111_IMASK1_P1_RX_RDY_MASK | ADIN2111_IMASK1_SPI_ERR_MASK | From 91f36191be5f70b90dd5a96309e3fb1518acb2ac Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 4 Mar 2024 16:16:13 +0100 Subject: [PATCH 0339/2402] boards: st: stm32h573i_dk: Add netif:eth support Add build_only for the st,stm32-ethernet driver to the build_all ethernet tests and add an entry for ethernet support to make sure ethernet driver is built. Signed-off-by: Pieter De Gendt --- boards/st/stm32h573i_dk/stm32h573i_dk.yaml | 1 + tests/drivers/build_all/ethernet/testcase.yaml | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.yaml b/boards/st/stm32h573i_dk/stm32h573i_dk.yaml index 8eea15d5d02..421f61c71e7 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.yaml +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.yaml @@ -15,6 +15,7 @@ supported: - dma - adc - dac + - netif:eth - pwm - counter - spi diff --git a/tests/drivers/build_all/ethernet/testcase.yaml b/tests/drivers/build_all/ethernet/testcase.yaml index ae9e631f528..b62da48f165 100644 --- a/tests/drivers/build_all/ethernet/testcase.yaml +++ b/tests/drivers/build_all/ethernet/testcase.yaml @@ -15,3 +15,10 @@ tests: platform_allow: - native_sim - native_sim_64 + + net.ethernet.build.stm32_ethernet: + filter: dt_compat_enabled("st,stm32-ethernet") + extra_configs: + - CONFIG_ETH_STM32_MULTICAST_FILTER=y + platform_allow: + - stm32h573i_dk From 9f4330f365c59aaf89ad8eb93882b917fed2a5fe Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Mon, 4 Mar 2024 10:39:03 -0800 Subject: [PATCH 0340/2402] x86: use CONFIG_PRIVILEGED_STACK_SIZE for stack size Instead of using CONFIG_MMU_PAGE_SIZE for size of the privileged stack, use the actual kconfig CONFIG_PRIVILEGED_STACK_SIZE. This allows for changing the size of privileged stack, and also aligns to the usage of CONFIG_PRIVILEGED_STACK_SIZE. Signed-off-by: Daniel Leung --- arch/x86/Kconfig | 4 ++++ arch/x86/core/userspace.c | 3 +++ include/zephyr/arch/x86/thread_stack.h | 2 +- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 1c58de4b908..487d6e94bd9 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -489,6 +489,10 @@ config X86_EFI_CONSOLE Likewise be sure to disable any other console/printk drivers! +config PRIVILEGED_STACK_SIZE + # Must be multiple of CONFIG_MMU_PAGE_SIZE + default 4096 if X86_MMU + source "arch/x86/core/Kconfig.ia32" source "arch/x86/core/Kconfig.intel64" diff --git a/arch/x86/core/userspace.c b/arch/x86/core/userspace.c index 9380c14d005..750c9775943 100644 --- a/arch/x86/core/userspace.c +++ b/arch/x86/core/userspace.c @@ -11,6 +11,9 @@ #include #include +BUILD_ASSERT((CONFIG_PRIVILEGED_STACK_SIZE > 0) && + (CONFIG_PRIVILEGED_STACK_SIZE % CONFIG_MMU_PAGE_SIZE) == 0); + #ifdef CONFIG_DEMAND_PAGING #include #endif diff --git a/include/zephyr/arch/x86/thread_stack.h b/include/zephyr/arch/x86/thread_stack.h index 5808d8bd99a..a92b04846d4 100644 --- a/include/zephyr/arch/x86/thread_stack.h +++ b/include/zephyr/arch/x86/thread_stack.h @@ -66,7 +66,7 @@ struct z_x86_thread_stack_header { char guard_page[CONFIG_MMU_PAGE_SIZE]; #endif #ifdef CONFIG_USERSPACE - char privilege_stack[CONFIG_MMU_PAGE_SIZE]; + char privilege_stack[CONFIG_PRIVILEGED_STACK_SIZE]; #endif /* CONFIG_USERSPACE */ } __packed __aligned(Z_X86_STACK_BASE_ALIGN); From 3fa291690f329be0001307340da5c41e26759e19 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Mon, 4 Mar 2024 11:32:42 -0800 Subject: [PATCH 0341/2402] xtensa: use CONFIG_PRIVILEGED_STACK_SIZE for stack size Instead of using CONFIG_MMU_PAGE_SIZE for size of the privileged stack, use the actual kconfig CONFIG_PRIVILEGED_STACK_SIZE. This allows for changing the size of privileged stack, and also aligns to the usage of CONFIG_PRIVILEGED_STACK_SIZE. Signed-off-by: Daniel Leung --- arch/xtensa/Kconfig | 4 ++++ arch/xtensa/core/mmu.c | 5 +++++ include/zephyr/arch/xtensa/thread_stack.h | 2 +- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 27153bad4cf..af22ccb90c9 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -206,6 +206,10 @@ config XTENSA_MMU_DOUBLE_MAP This invalidates all TLBs referred by the incoming thread's memory domain when swapping page tables. +config PRIVILEGED_STACK_SIZE + # Must be multiple of CONFIG_MMU_PAGE_SIZE + default 4096 + endif # XTENSA_MMU config XTENSA_SYSCALL_USE_HELPER diff --git a/arch/xtensa/core/mmu.c b/arch/xtensa/core/mmu.c index 294a66dbc22..576b185a099 100644 --- a/arch/xtensa/core/mmu.c +++ b/arch/xtensa/core/mmu.c @@ -9,6 +9,11 @@ #include #include +#ifdef CONFIG_USERSPACE +BUILD_ASSERT((CONFIG_PRIVILEGED_STACK_SIZE > 0) && + (CONFIG_PRIVILEGED_STACK_SIZE % CONFIG_MMU_PAGE_SIZE) == 0); +#endif + #define ASID_INVALID 0 struct tlb_regs { diff --git a/include/zephyr/arch/xtensa/thread_stack.h b/include/zephyr/arch/xtensa/thread_stack.h index b862b7a8c1e..75e5b36f9e1 100644 --- a/include/zephyr/arch/xtensa/thread_stack.h +++ b/include/zephyr/arch/xtensa/thread_stack.h @@ -47,7 +47,7 @@ /* thread stack */ #ifdef CONFIG_XTENSA_MMU struct xtensa_thread_stack_header { - char privilege_stack[CONFIG_MMU_PAGE_SIZE]; + char privilege_stack[CONFIG_PRIVILEGED_STACK_SIZE]; } __packed __aligned(XTENSA_STACK_BASE_ALIGN); #define ARCH_THREAD_STACK_RESERVED \ From e6d7e812b55f55c984f473020d29cb16557f7dd1 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Mon, 26 Feb 2024 15:42:10 +0100 Subject: [PATCH 0342/2402] charger: add charger status and online change notifiers Some applications might be intersted in notification about charger status or charger online updates so they can avoid polling. Add new properties allowing to register such notifications. Signed-off-by: Lukasz Madej --- include/zephyr/drivers/charger.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/zephyr/drivers/charger.h b/include/zephyr/drivers/charger.h index c29e46038f5..457eec939be 100644 --- a/include/zephyr/drivers/charger.h +++ b/include/zephyr/drivers/charger.h @@ -89,6 +89,18 @@ enum charger_property { * is issued to the system, measured in µV */ CHARGER_PROP_SYSTEM_VOLTAGE_NOTIFICATION_UV, + /** + * Configuration to issue a notification to the system based on the charger status change + * + * Value should be of type charger_status_notifier_t + */ + CHARGER_PROP_STATUS_NOTIFICATION, + /** + * Configuration to issue a notification to the system based on the charger online change + * + * Value should be of type charger_online_notifier_t + */ + CHARGER_PROP_ONLINE_NOTIFICATION, /** Reserved to demark end of common charger properties */ CHARGER_PROP_COMMON_COUNT, /** @@ -230,6 +242,20 @@ struct charger_current_notifier { uint32_t duration_us; }; +/** + * @brief The charger status change callback to notify the system + * + * @param status Current charging state + */ +typedef void (*charger_status_notifier_t)(enum charger_status status); + +/** + * @brief The charger online change callback to notify the system + * + * @param online Current external supply state + */ +typedef void (*charger_online_notifier_t)(enum charger_online online); + /** * @brief container for a charger_property value * @@ -267,6 +293,10 @@ union charger_propval { struct charger_current_notifier discharge_current_notification; /** CHARGER_PROP_SYSTEM_VOLTAGE_NOTIFICATION_UV */ uint32_t system_voltage_notification; + /** CHARGER_PROP_STATUS_NOTIFICATION */ + charger_status_notifier_t status_notification; + /** CHARGER_PROP_ONLINE_NOTIFICATION */ + charger_online_notifier_t online_notification; }; /** From f14228744f6097f2cd81fb98839abce172c143d2 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Tue, 6 Feb 2024 15:45:21 +0100 Subject: [PATCH 0343/2402] drivers: charger: charger_max20335: handle charger notifications Add support for status and online notification properties. Fire these notifications from int_routine_handler work directly. Such approach makes the code cleaner and does not affect overall max20335 interrupt processing performance. However application code processing these notifications cannot be blocking. Signed-off-by: Lukasz Madej --- drivers/charger/charger_max20335.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index ebe2153f6d3..6a4b50acf93 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -54,6 +54,8 @@ struct charger_max20335_data { struct k_work_delayable int_enable_work; enum charger_status charger_status; enum charger_online charger_online; + charger_status_notifier_t charger_status_notifier; + charger_online_notifier_t charger_online_notifier; bool charger_enabled; uint32_t charge_current_ua; uint32_t charge_voltage_uv; @@ -404,6 +406,12 @@ static int max20335_set_prop(const struct device *dev, charger_prop_t prop, } return ret; + case CHARGER_PROP_STATUS_NOTIFICATION: + data->charger_status_notifier = val->status_notification; + return 0; + case CHARGER_PROP_ONLINE_NOTIFICATION: + data->charger_online_notifier = val->online_notification; + return 0; default: return -ENOTSUP; } @@ -458,6 +466,10 @@ static void max20335_int_routine_work_handler(struct k_work *work) ret = max20335_get_charger_status(data->dev, &data->charger_status); if (ret < 0) { LOG_WRN("Failed to read charger status: %d", ret); + } else { + if (data->charger_status_notifier != NULL) { + data->charger_status_notifier(data->charger_status); + } } } @@ -465,6 +477,10 @@ static void max20335_int_routine_work_handler(struct k_work *work) ret = max20335_get_charger_online(data->dev, &data->charger_online); if (ret < 0) { LOG_WRN("Failed to read charger online %d", ret); + } else { + if (data->charger_online_notifier != NULL) { + data->charger_online_notifier(data->charger_online); + } } if (data->charger_online != CHARGER_ONLINE_OFFLINE) { From b803e0609946998d96ea232188673f8bf106f36e Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Thu, 8 Feb 2024 12:10:10 +0200 Subject: [PATCH 0344/2402] drivers: dai: sai: use "dmas" property for handshake encoding Since a DMA cell now allows specifying a channel and a MUX value there's no need to fetch these values from the HAL. This, in turn, allows for more flexibility and reduces the coding effort for new platforms that want to use the SAI driver. Signed-off-by: Laurentiu Mihalcea --- drivers/dai/nxp/sai/sai.c | 4 ++-- drivers/dai/nxp/sai/sai.h | 9 +++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/dai/nxp/sai/sai.c b/drivers/dai/nxp/sai/sai.c index 9146c2c67ae..fd279fef2fd 100644 --- a/drivers/dai/nxp/sai/sai.c +++ b/drivers/dai/nxp/sai/sai.c @@ -865,13 +865,13 @@ BUILD_ASSERT(SAI_TX_SYNC_MODE(inst) != SAI_RX_SYNC_MODE(inst) || \ static const struct dai_properties sai_tx_props_##inst = { \ .fifo_address = SAI_TX_FIFO_BASE(inst), \ .fifo_depth = SAI_FIFO_DEPTH(inst) * CONFIG_SAI_FIFO_WORD_SIZE, \ - .dma_hs_id = SAI_TX_DMA_MUX(inst), \ + .dma_hs_id = SAI_TX_RX_DMA_HANDSHAKE(inst, tx), \ }; \ \ static const struct dai_properties sai_rx_props_##inst = { \ .fifo_address = SAI_RX_FIFO_BASE(inst), \ .fifo_depth = SAI_FIFO_DEPTH(inst) * CONFIG_SAI_FIFO_WORD_SIZE, \ - .dma_hs_id = SAI_RX_DMA_MUX(inst), \ + .dma_hs_id = SAI_TX_RX_DMA_HANDSHAKE(inst, rx), \ }; \ \ void irq_config_##inst(void) \ diff --git a/drivers/dai/nxp/sai/sai.h b/drivers/dai/nxp/sai/sai.h index c93a1803d41..b5e07b45395 100644 --- a/drivers/dai/nxp/sai/sai.h +++ b/drivers/dai/nxp/sai/sai.h @@ -137,6 +137,15 @@ LOG_MODULE_REGISTER(nxp_dai_sai); #define SAI_RX_SYNC_MODE(inst)\ DT_INST_PROP_OR(inst, rx_sync_mode, kSAI_ModeAsync) +/* used to retrieve the handshake value for given direction. The handshake + * is computed as follows: + * handshake = CHANNEL_ID | (MUX_VALUE << 8) + * The channel ID and MUX value are each encoded in 8 bits. + */ +#define SAI_TX_RX_DMA_HANDSHAKE(inst, dir)\ + ((DT_INST_DMAS_CELL_BY_NAME(inst, dir, channel) & GENMASK(7, 0)) |\ + ((DT_INST_DMAS_CELL_BY_NAME(inst, dir, mux) << 8) & GENMASK(15, 8))) + /* utility macros */ /* invert a clock's polarity. This works because a clock's polarity is expressed From 5d9acf52a5211a2285bf40cd2d113761d51824d4 Mon Sep 17 00:00:00 2001 From: Miika Karanki Date: Tue, 16 Jan 2024 12:30:44 +0200 Subject: [PATCH 0345/2402] drivers: flash: stm32 ospi: implement non busy wait polling HAL_OSPI_AutoPolling is checking is the status match happened in a busy loop. That CPU intensive operation can cause starvation of other tasks especially on flash erase operations which can take seconds to complete. So, replace the use of HAL_OSPI_AutoPolling with HAL_OSPI_AutoPolling_IT. The match results HAL_OSPI_StatusMatchCallback being called. Signed-off-by: Miika Karanki --- drivers/flash/flash_stm32_ospi.c | 100 ++++++++++++++++++------------- drivers/flash/flash_stm32_ospi.h | 2 + 2 files changed, 60 insertions(+), 42 deletions(-) diff --git a/drivers/flash/flash_stm32_ospi.c b/drivers/flash/flash_stm32_ospi.c index 1b174405715..df01fd5e145 100644 --- a/drivers/flash/flash_stm32_ospi.c +++ b/drivers/flash/flash_stm32_ospi.c @@ -522,14 +522,38 @@ static bool ospi_address_is_valid(const struct device *dev, off_t addr, return (addr >= 0) && ((uint64_t)addr + (uint64_t)size <= flash_size); } +static int stm32_ospi_wait_auto_polling(struct flash_stm32_ospi_data *dev_data, + OSPI_AutoPollingTypeDef *s_config, uint32_t timeout_ms) +{ + dev_data->cmd_status = 0; + if (HAL_OSPI_AutoPolling_IT(&dev_data->hospi, s_config) != HAL_OK) { + LOG_ERR("OSPI AutoPoll failed"); + return -EIO; + } + + if (k_sem_take(&dev_data->sync, K_MSEC(timeout_ms)) != 0) { + LOG_ERR("OSPI AutoPoll wait failed"); + HAL_OSPI_Abort(&dev_data->hospi); + k_sem_reset(&dev_data->sync); + return -EIO; + } + + /* HAL_OSPI_AutoPolling_IT enables transfer error interrupt which sets + * cmd_status. + */ + return dev_data->cmd_status; +} + /* * This function Polls the WEL (write enable latch) bit to become to 0 * When the Chip Erase Cycle is completed, the Write Enable Latch (WEL) bit is cleared. * in nor_mode SPI/OPI OSPI_SPI_MODE or OSPI_OPI_MODE * and nor_rate transfer STR/DTR OSPI_STR_TRANSFER or OSPI_DTR_TRANSFER */ -static int stm32_ospi_mem_erased(OSPI_HandleTypeDef *hospi, uint8_t nor_mode, uint8_t nor_rate) +static int stm32_ospi_mem_erased(struct flash_stm32_ospi_data *dev_data, + uint8_t nor_mode, uint8_t nor_rate) { + OSPI_HandleTypeDef *hospi = &dev_data->hospi; OSPI_AutoPollingTypeDef s_config = {0}; OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate); @@ -566,12 +590,8 @@ static int stm32_ospi_mem_erased(OSPI_HandleTypeDef *hospi, uint8_t nor_mode, ui } /* Start Automatic-Polling mode to wait until the memory is totally erased */ - if (HAL_OSPI_AutoPolling(hospi, &s_config, STM32_OSPI_BULK_ERASE_MAX_TIME) != HAL_OK) { - LOG_ERR("OSPI AutoPoll (WEL) failed"); - return -EIO; - } - - return 0; + return stm32_ospi_wait_auto_polling(dev_data, + &s_config, STM32_OSPI_BULK_ERASE_MAX_TIME); } /* @@ -579,8 +599,10 @@ static int stm32_ospi_mem_erased(OSPI_HandleTypeDef *hospi, uint8_t nor_mode, ui * in nor_mode SPI/OPI OSPI_SPI_MODE or OSPI_OPI_MODE * and nor_rate transfer STR/DTR OSPI_STR_TRANSFER or OSPI_DTR_TRANSFER */ -static int stm32_ospi_mem_ready(OSPI_HandleTypeDef *hospi, uint8_t nor_mode, uint8_t nor_rate) +static int stm32_ospi_mem_ready(struct flash_stm32_ospi_data *dev_data, uint8_t nor_mode, + uint8_t nor_rate) { + OSPI_HandleTypeDef *hospi = &dev_data->hospi; OSPI_AutoPollingTypeDef s_config = {0}; OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate); @@ -616,17 +638,14 @@ static int stm32_ospi_mem_ready(OSPI_HandleTypeDef *hospi, uint8_t nor_mode, uin } /* Start Automatic-Polling mode to wait until the memory is ready WIP=0 */ - if (HAL_OSPI_AutoPolling(hospi, &s_config, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - LOG_ERR("OSPI AutoPoll failed"); - return -EIO; - } - - return 0; + return stm32_ospi_wait_auto_polling(dev_data, &s_config, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); } /* Enables writing to the memory sending a Write Enable and wait it is effective */ -static int stm32_ospi_write_enable(OSPI_HandleTypeDef *hospi, uint8_t nor_mode, uint8_t nor_rate) +static int stm32_ospi_write_enable(struct flash_stm32_ospi_data *dev_data, + uint8_t nor_mode, uint8_t nor_rate) { + OSPI_HandleTypeDef *hospi = &dev_data->hospi; OSPI_AutoPollingTypeDef s_config = {0}; OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate); @@ -679,12 +698,7 @@ static int stm32_ospi_write_enable(OSPI_HandleTypeDef *hospi, uint8_t nor_mode, s_config.Interval = SPI_NOR_AUTO_POLLING_INTERVAL; s_config.AutomaticStop = HAL_OSPI_AUTOMATIC_STOP_ENABLE; - if (HAL_OSPI_AutoPolling(hospi, &s_config, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - LOG_ERR("OSPI config auto polling failed"); - return -EIO; - } - - return 0; + return stm32_ospi_wait_auto_polling(dev_data, &s_config, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); } /* Write Flash configuration register 2 with new dummy cycles */ @@ -796,7 +810,7 @@ static int stm32_ospi_config_mem(const struct device *dev) /* Going to set the OPI mode (STR or DTR transfer rate) */ LOG_DBG("OSPI configuring OctoSPI mode"); - if (stm32_ospi_write_enable(&dev_data->hospi, + if (stm32_ospi_write_enable(dev_data, OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) { LOG_ERR("OSPI write Enable failed"); return -EIO; @@ -808,12 +822,12 @@ static int stm32_ospi_config_mem(const struct device *dev) LOG_ERR("OSPI write CFGR2 failed"); return -EIO; } - if (stm32_ospi_mem_ready(&dev_data->hospi, + if (stm32_ospi_mem_ready(dev_data, OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) { LOG_ERR("OSPI autopolling failed"); return -EIO; } - if (stm32_ospi_write_enable(&dev_data->hospi, + if (stm32_ospi_write_enable(dev_data, OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) { LOG_ERR("OSPI write Enable 2 failed"); return -EIO; @@ -841,7 +855,7 @@ static int stm32_ospi_config_mem(const struct device *dev) } if (dev_cfg->data_rate == OSPI_STR_TRANSFER) { - if (stm32_ospi_mem_ready(&dev_data->hospi, + if (stm32_ospi_mem_ready(dev_data, OSPI_OPI_MODE, OSPI_STR_TRANSFER) != 0) { /* Check Flash busy ? */ LOG_ERR("OSPI flash busy failed"); @@ -859,7 +873,7 @@ static int stm32_ospi_config_mem(const struct device *dev) } if (dev_cfg->data_rate == OSPI_DTR_TRANSFER) { - if (stm32_ospi_mem_ready(&dev_data->hospi, + if (stm32_ospi_mem_ready(dev_data, OSPI_OPI_MODE, OSPI_DTR_TRANSFER) != 0) { /* Check Flash busy ? */ LOG_ERR("OSPI flash busy failed"); @@ -1004,7 +1018,7 @@ static int flash_stm32_ospi_erase(const struct device *dev, off_t addr, ospi_lock_thread(dev); - if (stm32_ospi_mem_ready(&dev_data->hospi, + if (stm32_ospi_mem_ready(dev_data, dev_cfg->data_mode, dev_cfg->data_rate) != 0) { ospi_unlock_thread(dev); LOG_ERR("Erase failed : flash busy"); @@ -1023,7 +1037,7 @@ static int flash_stm32_ospi_erase(const struct device *dev, off_t addr, while ((size > 0) && (ret == 0)) { - ret = stm32_ospi_write_enable(&dev_data->hospi, + ret = stm32_ospi_write_enable(dev_data, dev_cfg->data_mode, dev_cfg->data_rate); if (ret != 0) { LOG_ERR("Erase failed : write enable"); @@ -1044,7 +1058,7 @@ static int flash_stm32_ospi_erase(const struct device *dev, off_t addr, size -= dev_cfg->flash_size; /* Chip (Bulk) erase started, wait until WEL becomes 0 */ - ret = stm32_ospi_mem_erased(&dev_data->hospi, + ret = stm32_ospi_mem_erased(dev_data, dev_cfg->data_mode, dev_cfg->data_rate); if (ret != 0) { LOG_ERR("Chip Erase failed"); @@ -1112,8 +1126,8 @@ static int flash_stm32_ospi_erase(const struct device *dev, off_t addr, size -= SPI_NOR_SECTOR_SIZE; } - ret = stm32_ospi_mem_ready(&dev_data->hospi, - dev_cfg->data_mode, dev_cfg->data_rate); + ret = stm32_ospi_mem_ready(dev_data, dev_cfg->data_mode, + dev_cfg->data_rate); } } @@ -1275,7 +1289,7 @@ static int flash_stm32_ospi_write(const struct device *dev, off_t addr, LOG_DBG("OSPI: write %zu data", size); ospi_lock_thread(dev); - ret = stm32_ospi_mem_ready(&dev_data->hospi, + ret = stm32_ospi_mem_ready(dev_data, dev_cfg->data_mode, dev_cfg->data_rate); if (ret != 0) { ospi_unlock_thread(dev); @@ -1285,7 +1299,7 @@ static int flash_stm32_ospi_write(const struct device *dev, off_t addr, while ((size > 0) && (ret == 0)) { to_write = size; - ret = stm32_ospi_write_enable(&dev_data->hospi, + ret = stm32_ospi_write_enable(dev_data, dev_cfg->data_mode, dev_cfg->data_rate); if (ret != 0) { LOG_ERR("OSPI: write not enabled"); @@ -1315,7 +1329,7 @@ static int flash_stm32_ospi_write(const struct device *dev, off_t addr, addr += to_write; /* Configure automatic polling mode to wait for end of program */ - ret = stm32_ospi_mem_ready(&dev_data->hospi, + ret = stm32_ospi_mem_ready(dev_data, dev_cfg->data_mode, dev_cfg->data_rate); if (ret != 0) { LOG_ERR("OSPI: write PP not ready"); @@ -1660,7 +1674,7 @@ static int stm32_ospi_enable_qe(const struct device *dev) return 0; } - ret = stm32_ospi_write_enable(&data->hospi, OSPI_SPI_MODE, OSPI_STR_TRANSFER); + ret = stm32_ospi_write_enable(data, OSPI_SPI_MODE, OSPI_STR_TRANSFER); if (ret < 0) { return ret; } @@ -1672,7 +1686,7 @@ static int stm32_ospi_enable_qe(const struct device *dev) return ret; } - ret = stm32_ospi_mem_ready(&data->hospi, OSPI_SPI_MODE, OSPI_STR_TRANSFER); + ret = stm32_ospi_mem_ready(data, OSPI_SPI_MODE, OSPI_STR_TRANSFER); if (ret < 0) { return ret; } @@ -2133,6 +2147,13 @@ static int flash_stm32_ospi_init(const struct device *dev) #endif /* CONFIG_SOC_SERIES_STM32H5X */ + /* Initialize semaphores */ + k_sem_init(&dev_data->sem, 1, 1); + k_sem_init(&dev_data->sync, 0, 1); + + /* Run IRQ init */ + dev_cfg->irq_config(dev); + /* Reset NOR flash memory : still with the SPI/STR config for the NOR */ if (stm32_ospi_mem_reset(dev) != 0) { LOG_ERR("OSPI reset failed"); @@ -2142,7 +2163,7 @@ static int flash_stm32_ospi_init(const struct device *dev) LOG_DBG("Reset Mem (SPI/STR)"); /* Check if memory is ready in the SPI/STR mode */ - if (stm32_ospi_mem_ready(&dev_data->hospi, + if (stm32_ospi_mem_ready(dev_data, OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) { LOG_ERR("OSPI memory not ready"); return -EIO; @@ -2165,12 +2186,7 @@ static int flash_stm32_ospi_init(const struct device *dev) return -EIO; } - /* Initialize semaphores */ - k_sem_init(&dev_data->sem, 1, 1); - k_sem_init(&dev_data->sync, 0, 1); - /* Run IRQ init */ - dev_cfg->irq_config(dev); /* Send the instruction to read the SFDP */ const uint8_t decl_nph = 2; diff --git a/drivers/flash/flash_stm32_ospi.h b/drivers/flash/flash_stm32_ospi.h index dfe56106055..52221ba84bb 100644 --- a/drivers/flash/flash_stm32_ospi.h +++ b/drivers/flash/flash_stm32_ospi.h @@ -38,7 +38,9 @@ #define HAL_OSPI_Transmit_DMA HAL_XSPI_Transmit_DMA #define HAL_OSPI_Transmit_IT HAL_XSPI_Transmit_IT #define HAL_OSPI_AutoPolling HAL_XSPI_AutoPolling +#define HAL_OSPI_AutoPolling_IT HAL_XSPI_AutoPolling_IT #define HAL_OSPI_IRQHandler HAL_XSPI_IRQHandler +#define HAL_OSPI_Abort HAL_XSPI_Abort #define HAL_OSPI_ErrorCallback HAL_XSPI_ErrorCallback #define HAL_OSPI_CmdCpltCallback HAL_XSPI_CmdCpltCallback From 004c4769e3881e27d2563678d5aefda531d9717f Mon Sep 17 00:00:00 2001 From: Miika Karanki Date: Thu, 1 Feb 2024 16:31:14 +0200 Subject: [PATCH 0346/2402] drivers: flash: stm32 ospi refactor stm32_ospi_mem_erased args Change to use dev pointer, from where the other parameters were available as well. Signed-off-by: Miika Karanki --- drivers/flash/flash_stm32_ospi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/flash/flash_stm32_ospi.c b/drivers/flash/flash_stm32_ospi.c index df01fd5e145..030dc8bd156 100644 --- a/drivers/flash/flash_stm32_ospi.c +++ b/drivers/flash/flash_stm32_ospi.c @@ -550,9 +550,12 @@ static int stm32_ospi_wait_auto_polling(struct flash_stm32_ospi_data *dev_data, * in nor_mode SPI/OPI OSPI_SPI_MODE or OSPI_OPI_MODE * and nor_rate transfer STR/DTR OSPI_STR_TRANSFER or OSPI_DTR_TRANSFER */ -static int stm32_ospi_mem_erased(struct flash_stm32_ospi_data *dev_data, - uint8_t nor_mode, uint8_t nor_rate) +static int stm32_ospi_mem_erased(const struct device *dev) { + const struct flash_stm32_ospi_config *dev_cfg = dev->config; + struct flash_stm32_ospi_data *dev_data = dev->data; + uint8_t nor_mode = dev_cfg->data_mode; + uint8_t nor_rate = dev_cfg->data_rate; OSPI_HandleTypeDef *hospi = &dev_data->hospi; OSPI_AutoPollingTypeDef s_config = {0}; OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate); @@ -1058,8 +1061,7 @@ static int flash_stm32_ospi_erase(const struct device *dev, off_t addr, size -= dev_cfg->flash_size; /* Chip (Bulk) erase started, wait until WEL becomes 0 */ - ret = stm32_ospi_mem_erased(dev_data, - dev_cfg->data_mode, dev_cfg->data_rate); + ret = stm32_ospi_mem_erased(dev); if (ret != 0) { LOG_ERR("Chip Erase failed"); break; From 53cca3ea4e87abb3289b36192da0ac5e80850a01 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Wed, 21 Feb 2024 12:59:06 +0100 Subject: [PATCH 0347/2402] samples: Bluetooth: Broadcast sink: Add proper parsing decoding of LC3 data The sample assumed that the broadcast audio was always a single frame per block. This commit improves the validation of the codec configuration from the broadcast source, and properly decodes the SDU using the configuration values. Signed-off-by: Emil Gydesen --- .../bluetooth/broadcast_audio_sink/src/main.c | 112 ++++++++++++++---- 1 file changed, 90 insertions(+), 22 deletions(-) diff --git a/samples/bluetooth/broadcast_audio_sink/src/main.c b/samples/bluetooth/broadcast_audio_sink/src/main.c index 59f7c6d398c..979da4f243b 100644 --- a/samples/bluetooth/broadcast_audio_sink/src/main.c +++ b/samples/bluetooth/broadcast_audio_sink/src/main.c @@ -93,7 +93,13 @@ static struct broadcast_sink_stream { #if defined(CONFIG_LIBLC3) struct net_buf *in_buf; struct k_work_delayable lc3_decode_work; -/* Internal lock for protecting net_buf from multiple access */ + + /* LC3 config values */ + enum bt_audio_location chan_allocation; + uint16_t lc3_octets_per_frame; + uint8_t lc3_frames_blocks_per_sdu; + + /* Internal lock for protecting net_buf from multiple access */ struct k_mutex lc3_decoder_mutex; lc3_decoder_t lc3_decoder; lc3_decoder_mem_48k_t lc3_decoder_mem; @@ -131,7 +137,6 @@ static void add_to_usb_ring_buf(const int16_t audio_buf[LC3_MAX_NUM_SAMPLES_STER #endif /* defined(CONFIG_USB_DEVICE_AUDIO) */ #if defined(CONFIG_LIBLC3) -static int frames_per_sdu; static K_SEM_DEFINE(lc3_decoder_sem, 0, 1); static bool do_lc3_decode(struct broadcast_sink_stream *sink_stream, @@ -174,11 +179,29 @@ static void lc3_decoder_thread(void *arg1, void *arg2, void *arg3) } } +static size_t get_chan_cnt(enum bt_audio_location chan_allocation) +{ + size_t cnt = 0U; + + if (chan_allocation == BT_AUDIO_LOCATION_MONO_AUDIO) { + return 1; + } + + while (chan_allocation != 0) { + cnt += chan_allocation & 1U; + chan_allocation >>= 1; + } + + return cnt; +} + /** Decode LC3 data on a stream and returns true if successful */ static bool do_lc3_decode(struct broadcast_sink_stream *sink_stream, int16_t audio_buf[LC3_MAX_NUM_SAMPLES_STEREO]) { - uint16_t octets_per_frame; + const uint8_t frames_blocks_per_sdu = sink_stream->lc3_frames_blocks_per_sdu; + const uint16_t octets_per_frame = sink_stream->lc3_octets_per_frame; + uint16_t frames_per_block; struct net_buf *buf; k_mutex_lock(&sink_stream->lc3_decoder_mutex, K_FOREVER); @@ -194,31 +217,33 @@ static bool do_lc3_decode(struct broadcast_sink_stream *sink_stream, sink_stream->in_buf = NULL; k_mutex_unlock(&sink_stream->lc3_decoder_mutex); - octets_per_frame = buf->len / frames_per_sdu; - if (buf->len != (octets_per_frame * frames_per_sdu)) { - printk("Expected %u frames of size %u, but length is %u\n", frames_per_sdu, - octets_per_frame, buf->len); + frames_per_block = get_chan_cnt(sink_stream->chan_allocation); + if (buf->len != (frames_per_block * octets_per_frame * frames_blocks_per_sdu)) { + printk("Expected %u frame blocks with %u frames of size %u, but length is %u\n", + frames_blocks_per_sdu, frames_per_block, octets_per_frame, buf->len); net_buf_unref(buf); return false; } - for (int i = 0; i < frames_per_sdu; i++) { - const void *data = net_buf_pull_mem(buf, octets_per_frame); - int err; + for (uint8_t i = 0U; i < frames_blocks_per_sdu; i++) { + for (uint16_t j = 0U; j < frames_per_block; j++) { + const void *data = net_buf_pull_mem(buf, octets_per_frame); + int err; - err = lc3_decode(sink_stream->lc3_decoder, data, octets_per_frame, - LC3_PCM_FORMAT_S16, audio_buf, 1); + err = lc3_decode(sink_stream->lc3_decoder, data, octets_per_frame, + LC3_PCM_FORMAT_S16, audio_buf, 1); - if (err == 1) { - printk(" decoder performed PLC\n"); - } else if (err < 0) { - printk(" decoder failed - wrong parameters? (err = %d)\n", err); + if (err == 1) { + printk(" decoder performed PLC\n"); + } else if (err < 0) { + printk(" decoder failed - wrong parameters? (err = %d)\n", err); - net_buf_unref(buf); + net_buf_unref(buf); - return false; + return false; + } } } @@ -229,9 +254,11 @@ static bool do_lc3_decode(struct broadcast_sink_stream *sink_stream, static int lc3_enable(struct broadcast_sink_stream *sink_stream) { - int ret; - int freq_hz; + size_t chan_alloc_bit_cnt; + size_t sdu_size_required; int frame_duration_us; + int freq_hz; + int ret; printk("Enable: stream with codec %p\n", sink_stream->stream.codec_cfg); @@ -251,8 +278,49 @@ static int lc3_enable(struct broadcast_sink_stream *sink_stream) return ret; } - frames_per_sdu = bt_audio_codec_cfg_get_frame_blocks_per_sdu(sink_stream->stream.codec_cfg, - true); + ret = bt_audio_codec_cfg_get_chan_allocation(sink_stream->stream.codec_cfg, + &sink_stream->chan_allocation); + if (ret != 0) { + printk("Error: Channel allocation not set, invalid configuration for LC3"); + return ret; + } + + ret = bt_audio_codec_cfg_get_octets_per_frame(sink_stream->stream.codec_cfg); + if (ret > 0) { + sink_stream->lc3_octets_per_frame = (uint16_t)ret; + } else { + printk("Error: Octets per frame not set, invalid configuration for LC3"); + return ret; + } + + ret = bt_audio_codec_cfg_get_frame_blocks_per_sdu(sink_stream->stream.codec_cfg, true); + if (ret > 0) { + sink_stream->lc3_frames_blocks_per_sdu = (uint8_t)ret; + } else { + printk("Error: Frame blocks per SDU not set, invalid configuration for LC3"); + return ret; + } + + /* An SDU can consist of X frame blocks, each with Y frames (one per channel) of size Z in + * them. The minimum SDU size required for this is X * Y * Z. + */ + chan_alloc_bit_cnt = get_chan_cnt(sink_stream->chan_allocation); + sdu_size_required = chan_alloc_bit_cnt * sink_stream->lc3_octets_per_frame * + sink_stream->lc3_frames_blocks_per_sdu; + if (sdu_size_required < sink_stream->stream.qos->sdu) { + printk("With %zu channels and %u octets per frame and %u frames per block, SDUs " + "shall be at minimum %zu, but the stream has been configured for %u", + chan_alloc_bit_cnt, sink_stream->lc3_octets_per_frame, + sink_stream->lc3_frames_blocks_per_sdu, sdu_size_required, + sink_stream->stream.qos->sdu); + + return -EINVAL; + } + + printk("Enabling LC3 decoder with frame duration %uus, frequency %uHz and with channel " + "allocation 0x%08X, %u octets per frame and %u frame blocks per SDU\n", + frame_duration_us, freq_hz, sink_stream->chan_allocation, + sink_stream->lc3_octets_per_frame, sink_stream->lc3_frames_blocks_per_sdu); #if defined(CONFIG_USB_DEVICE_AUDIO) sink_stream->lc3_decoder = lc3_setup_decoder(frame_duration_us, freq_hz, USB_SAMPLE_RATE, From f497c041598dc9c79f06f60f7bb9ba5993f2d87a Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 6 Mar 2024 14:40:19 -0300 Subject: [PATCH 0348/2402] west.yml: MCUboot sync from upstream Update Zephyr fork of MCUboot to revision: 8b4c70ab6dc03d2826c166dedb56541950defa8c Brings following Zephyr relevant fixes: 8b4c70ab boot: zephyr: Update changed Nordic family Kconfig b794d335 espressif: modify SOC_FAMILY according to new HWMv2 Signed-off-by: Sylvio Alves --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index e1ff0d95ce4..0dbb65acb62 100644 --- a/west.yml +++ b/west.yml @@ -282,7 +282,7 @@ manifest: groups: - crypto - name: mcuboot - revision: fefe701a5de7ffcec001938c978ef57ff7d0592d + revision: 8b4c70ab6dc03d2826c166dedb56541950defa8c path: bootloader/mcuboot - name: mipi-sys-t path: modules/debug/mipi-sys-t From 0f23818153e5b4334afce7a3dea15136a03fa28a Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Thu, 21 Dec 2023 09:49:35 -0500 Subject: [PATCH 0349/2402] posix: env: support for environ, getenv(), setenv(), unsetenv() Support getting and setting POSIX environment variables. Additionally, the thread-safe BSD variant getenv_r() is provided. environ, getenv(), setenv(), and unsetenv() are required by the POSIX_SINGLE_PROCESS Option Group as detailed in Section E.1 of IEEE-1003.1-2017. The POSIX_SINGLE_PROCESS Option Group is required for PSE51, PSE52, PSE53, and PSE54 conformance, and is otherwise mandatory for any POSIX conforming system as per Section A.2.1.3 of IEEE-1003-1.2017. Signed-off-by: Christopher Friedt --- lib/libc/minimal/include/stdlib.h | 10 ++ lib/posix/options/CMakeLists.txt | 1 + lib/posix/options/Kconfig | 1 + lib/posix/options/Kconfig.env | 14 ++ lib/posix/options/env.c | 267 ++++++++++++++++++++++++++++++ 5 files changed, 293 insertions(+) create mode 100644 lib/posix/options/Kconfig.env create mode 100644 lib/posix/options/env.c diff --git a/lib/libc/minimal/include/stdlib.h b/lib/libc/minimal/include/stdlib.h index 84a41ecfdfe..c60f9c17825 100644 --- a/lib/libc/minimal/include/stdlib.h +++ b/lib/libc/minimal/include/stdlib.h @@ -70,6 +70,16 @@ static inline long long llabs(long long __n) return (__n < 0LL) ? -__n : __n; } +char *getenv(const char *name); +#if _POSIX_C_SOURCE >= 200112L +int setenv(const char *name, const char *val, int overwrite); +int unsetenv(const char *name); +#endif + +#ifdef _BSD_SOURCE +int getenv_r(const char *name, char *buf, size_t len); +#endif + #ifdef __cplusplus } #endif diff --git a/lib/posix/options/CMakeLists.txt b/lib/posix/options/CMakeLists.txt index 31c83fe432e..358ae925a43 100644 --- a/lib/posix/options/CMakeLists.txt +++ b/lib/posix/options/CMakeLists.txt @@ -40,6 +40,7 @@ zephyr_library_sources_ifdef(CONFIG_POSIX_API perror.c) zephyr_library_sources_ifdef(CONFIG_POSIX_CLOCK clock.c) zephyr_library_sources_ifdef(CONFIG_POSIX_CLOCK nanosleep.c) zephyr_library_sources_ifdef(CONFIG_POSIX_CLOCK sleep.c) +zephyr_library_sources_ifdef(CONFIG_POSIX_ENV env.c) zephyr_library_sources_ifdef(CONFIG_POSIX_FS fs.c) zephyr_library_sources_ifdef(CONFIG_POSIX_MQUEUE mqueue.c) zephyr_library_sources_ifdef(CONFIG_POSIX_PUTMSG stropts.c) diff --git a/lib/posix/options/Kconfig b/lib/posix/options/Kconfig index 187fd5a6913..06de40ab727 100644 --- a/lib/posix/options/Kconfig +++ b/lib/posix/options/Kconfig @@ -27,6 +27,7 @@ endif # POSIX_CLOCK rsource "Kconfig.barrier" rsource "Kconfig.clock" rsource "Kconfig.cond" +rsource "Kconfig.env" rsource "Kconfig.eventfd" rsource "Kconfig.fdtable" rsource "Kconfig.fnmatch" diff --git a/lib/posix/options/Kconfig.env b/lib/posix/options/Kconfig.env new file mode 100644 index 00000000000..222392d2737 --- /dev/null +++ b/lib/posix/options/Kconfig.env @@ -0,0 +1,14 @@ +# Copyright (c) 2023, Meta +# +# SPDX-License-Identifier: Apache-2.0 + +config POSIX_ENV + bool "Support for environ, getenv(), getenv_r(), setenv(), and unsetenv()" + depends on COMMON_LIBC_MALLOC + default y if POSIX_API + help + Select this option to add support for environment variables. + +module = POSIX_ENV +module-str = POSIX env logging +source "subsys/logging/Kconfig.template.log_config" diff --git a/lib/posix/options/env.c b/lib/posix/options/env.c new file mode 100644 index 00000000000..2607ae2a4be --- /dev/null +++ b/lib/posix/options/env.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2023, Meta + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include +#include + +#define TRACK_ALLOC (IS_ENABLED(CONFIG_POSIX_ENV_LOG_LEVEL_DBG) || IS_ENABLED(CONFIG_ZTEST)) + +LOG_MODULE_REGISTER(posix_env, CONFIG_POSIX_ENV_LOG_LEVEL); + +static struct k_spinlock environ_lock; +static size_t allocated; +char **environ; + +#ifdef CONFIG_ZTEST +size_t posix_env_get_allocated_space(void) +{ + return allocated; +} +#endif + +static size_t environ_size(void) +{ + size_t ret; + + if (environ == NULL) { + return 0; + } + + for (ret = 0; environ[ret] != NULL; ++ret) { + } + + return ret; +} + +static int findenv(const char *name, size_t namelen) +{ + const char *env; + + if (name == NULL || namelen == 0 || strchr(name, '=') != NULL) { + /* Note: '=' is not a valid name character */ + return -EINVAL; + } + + if (environ == NULL) { + return -ENOENT; + } + + for (char **envp = &environ[0]; *envp != NULL; ++envp) { + env = *envp; + if (strncmp(env, name, namelen) == 0 && env[namelen] == '=') { + return envp - environ; + } + } + + return -ENOENT; +} + +char *getenv(const char *name) +{ + int ret; + size_t nsize; + char *val = NULL; + + nsize = (name == NULL) ? 0 : strlen(name); + K_SPINLOCK(&environ_lock) + { + ret = findenv(name, nsize); + if (ret < 0) { + K_SPINLOCK_BREAK; + } + + val = environ[ret] + nsize + 1; + } + + return val; +} + +int getenv_r(const char *name, char *buf, size_t len) +{ + int ret = 0; + size_t vsize; + size_t nsize; + char *val = NULL; + + nsize = (name == NULL) ? 0 : strlen(name); + K_SPINLOCK(&environ_lock) + { + ret = findenv(name, nsize); + if (ret < 0) { + LOG_DBG("No entry for name '%s'", name); + K_SPINLOCK_BREAK; + } + + val = environ[ret] + nsize + 1; + vsize = strlen(val) + 1; + if (vsize > len) { + ret = -ERANGE; + K_SPINLOCK_BREAK; + } + strncpy(buf, val, vsize); + LOG_DBG("Found entry %s", environ[ret]); + } + + if (ret < 0) { + errno = -ret; + ret = -1; + } + + return ret; +} + +int setenv(const char *name, const char *val, int overwrite) +{ + int ret = 0; + char *env; + char **envp; + size_t esize; + const size_t vsize = (val == NULL) ? 0 : strlen(val); + const size_t nsize = (name == NULL) ? 0 : strlen(name); + /* total size of name + '=' + val + '\0' */ + const size_t tsize = nsize + 1 /* '=' */ + vsize + 1 /* '\0' */; + + if (name == NULL || val == NULL) { + LOG_DBG("Invalid name '%s' or value '%s'", name, val); + errno = EINVAL; + return -1; + } + + K_SPINLOCK(&environ_lock) + { + ret = findenv(name, nsize); + if (ret == -EINVAL) { + LOG_DBG("Invalid name '%s'", name); + K_SPINLOCK_BREAK; + } + if (ret >= 0) { + /* name was found in environ */ + esize = strlen(environ[ret]) + 1; + if (overwrite == 0) { + LOG_DBG("Found entry %s", environ[ret]); + ret = 0; + K_SPINLOCK_BREAK; + } + } else { + /* name was not found in environ -> add new entry */ + esize = environ_size(); + envp = realloc(environ, sizeof(char **) * + (esize + 1 /* new entry */ + 1 /* NULL */)); + if (envp == NULL) { + ret = -ENOMEM; + K_SPINLOCK_BREAK; + } + + if (TRACK_ALLOC) { + allocated += sizeof(char **) * (esize + 2); + LOG_DBG("realloc %zu bytes (allocated: %zu)", + sizeof(char **) * (esize + 2), allocated); + } + + environ = envp; + ret = esize; + environ[ret] = NULL; + environ[ret + 1] = NULL; + esize = 0; + } + + if (esize < tsize) { + /* need to malloc or realloc space for new environ entry */ + env = realloc(environ[ret], tsize); + if (env == NULL) { + ret = -ENOMEM; + K_SPINLOCK_BREAK; + } + if (TRACK_ALLOC) { + allocated += tsize - esize; + LOG_DBG("realloc %zu bytes (allocated: %zu)", tsize - esize, + allocated); + } + environ[ret] = env; + } + + strncpy(environ[ret], name, nsize); + environ[ret][nsize] = '='; + strncpy(environ[ret] + nsize + 1, val, vsize + 1); + LOG_DBG("Added entry %s", environ[ret]); + + ret = 0; + } + + if (ret < 0) { + errno = -ret; + ret = -1; + } + + return ret; +} + +int unsetenv(const char *name) +{ + int ret = 0; + char **envp; + size_t esize; + size_t nsize; + + nsize = (name == NULL) ? 0 : strlen(name); + K_SPINLOCK(&environ_lock) + { + ret = findenv(name, nsize); + if (ret < 0) { + ret = (ret == -EINVAL) ? -EINVAL : 0; + K_SPINLOCK_BREAK; + } + + esize = environ_size(); + if (TRACK_ALLOC) { + allocated -= strlen(environ[ret]) + 1; + LOG_DBG("free %zu bytes (allocated: %zu)", strlen(environ[ret]) + 1, + allocated); + } + free(environ[ret]); + + /* shuffle remaining environment variable pointers forward */ + for (; ret < esize; ++ret) { + environ[ret] = environ[ret + 1]; + } + /* environ must be terminated with a NULL pointer */ + environ[ret] = NULL; + + /* reduce environ size and update allocation */ + --esize; + if (esize == 0) { + free(environ); + environ = NULL; + } else { + envp = realloc(environ, (esize + 1 /* NULL */) * sizeof(char **)); + if (envp != NULL) { + environ = envp; + } + } + __ASSERT_NO_MSG((esize >= 1 && environ != NULL) || environ == NULL); + + if (TRACK_ALLOC) { + /* recycle nsize here */ + nsize = ((esize == 0) ? 2 : 1) * sizeof(char **); + allocated -= nsize; + LOG_DBG("free %zu bytes (allocated: %zu)", nsize, allocated); + } + + ret = 0; + } + + if (ret < 0) { + errno = -ret; + ret = -1; + } + + return ret; +} From 8912ba900469cf2c9d0e4582c96ebce262a82cc4 Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Thu, 21 Dec 2023 09:56:18 -0500 Subject: [PATCH 0350/2402] tests: posix: tests for environ, getenv, setenv, unsetenv Add tests for environ, getenv(), setenv(), unsetenv(), and getenv_r(). Signed-off-by: Christopher Friedt --- tests/posix/env/CMakeLists.txt | 13 +++ tests/posix/env/prj.conf | 3 + tests/posix/env/src/env.c | 180 +++++++++++++++++++++++++++++++++ tests/posix/env/testcase.yaml | 32 ++++++ 4 files changed, 228 insertions(+) create mode 100644 tests/posix/env/CMakeLists.txt create mode 100644 tests/posix/env/prj.conf create mode 100644 tests/posix/env/src/env.c create mode 100644 tests/posix/env/testcase.yaml diff --git a/tests/posix/env/CMakeLists.txt b/tests/posix/env/CMakeLists.txt new file mode 100644 index 00000000000..6cd1e565dcc --- /dev/null +++ b/tests/posix/env/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(posix_common) + +FILE(GLOB app_sources src/*.c) + +target_sources(app PRIVATE ${app_sources}) +# For setenv() and unsetenv() +target_compile_options(app PRIVATE -U_POSIX_C_SOURCE -D_POSIX_C_SOURCE=200809L) +# For getenv_r() visibility and testing +target_compile_definitions(app PRIVATE _BSD_SOURCE) diff --git a/tests/posix/env/prj.conf b/tests/posix/env/prj.conf new file mode 100644 index 00000000000..7389f7de33e --- /dev/null +++ b/tests/posix/env/prj.conf @@ -0,0 +1,3 @@ +CONFIG_ZTEST=y +CONFIG_POSIX_ENV=y +CONFIG_COMMON_LIBC_MALLOC=y diff --git a/tests/posix/env/src/env.c b/tests/posix/env/src/env.c new file mode 100644 index 00000000000..1d121a24438 --- /dev/null +++ b/tests/posix/env/src/env.c @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2023, Meta + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#define M_HOME "/home/zephyr" +#define M_UID "1000" +#define M_PWD "/tmp" + +#define _m_alt_home "/this/path/is/much/longer/than" M_HOME + +#define DEFINE_ENVIRON(_handle, _key, _val) char _handle[] = _key "=" _val +#define RESET_ENVIRON(_handle, _key, _val) \ + snprintf(_handle, ARRAY_SIZE(_handle), "%s=%s", _key, _val) + +#if defined(CONFIG_NEWLIB_LIBC) || defined(CONFIG_PICOLIBC) +/* newlib headers seem to be missing this */ +int getenv_r(const char *name, char *val, size_t len); +#endif + +extern char **environ; +static char **old_environ; + +static DEFINE_ENVIRON(home, "HOME", M_HOME); +static DEFINE_ENVIRON(uid, "UID", M_UID); +static DEFINE_ENVIRON(pwd, "PWD", M_PWD); + +static char *environ_for_test[] = {home, uid, pwd, NULL}; + +ZTEST(env, test_getenv) +{ + zassert_equal(getenv(NULL), NULL); + zassert_equal(getenv(""), NULL); + zassert_equal(getenv("invalid=key"), NULL); + zassert_equal(getenv("HOME=" M_HOME), NULL); + zassert_equal(getenv("PWDR"), NULL); + + zassert_mem_equal(getenv("HOME"), M_HOME, strlen(M_HOME) + 1); + zassert_mem_equal(getenv("UID"), M_UID, strlen(M_UID) + 1); + zassert_mem_equal(getenv("PWD"), M_PWD, strlen(M_PWD) + 1); +} + +ZTEST(env, test_getenv_r) +{ + static char buf[16]; + static const int exp_errno[] = { + EINVAL, EINVAL, EINVAL, EINVAL, ENOENT, ENOENT, ENOENT, EINVAL, EINVAL, EINVAL, + }; + static const struct args_s { + const char *name; + char *buf; + size_t size; + } args[] = { + /* invalid input */ + {NULL, NULL, 0}, + {NULL, NULL, 42}, + {NULL, buf, 0}, + {NULL, buf, sizeof(buf)}, + {"hello", NULL, 0}, + {"hello", NULL, 42}, + {"hello", buf, 0}, + + /* invalid names */ + {"", buf, sizeof(buf)}, + {"invalid=key", buf, sizeof(buf)}, + {"HOME=", buf, sizeof(buf)}, + }; + + BUILD_ASSERT(ARRAY_SIZE(exp_errno) == ARRAY_SIZE(args)); + + ARRAY_FOR_EACH(args, i) + { + errno = 0; + zassert_equal(getenv_r(args[i].name, args[i].buf, args[i].size), -1, + "getenv_r(\"%s\", %p, %zu): expected to fail", args[i].name, + args[i].buf, args[i].size); + zassert_equal(errno, exp_errno[i], + "getenv_r(\"%s\", %p, %zu): act_errno: %d exp_errno: %d", + args[i].name, args[i].buf, args[i].size, errno, exp_errno[i]); + } + + zassert_mem_equal(getenv("HOME"), M_HOME, strlen(M_HOME) + 1); + zassert_mem_equal(getenv("UID"), M_UID, strlen(M_UID) + 1); + zassert_mem_equal(getenv("PWD"), M_PWD, strlen(M_PWD) + 1); +} + +ZTEST(env, test_setenv) +{ + zassert_equal(setenv(NULL, NULL, 0), -1); + zassert_equal(errno, EINVAL); + + /* + * bug in picolibc / newlib + * https://github.com/picolibc/picolibc/issues/648 + */ + zassert_equal(setenv("", "42", 0), -1); + zassert_equal(errno, EINVAL); + + zassert_equal(setenv("invalid=key", "42", 0), -1); + zassert_equal(errno, EINVAL); + + /* do not overwrite if environ[key] exists */ + zassert_ok(setenv("HOME", "/root", 0)); + zassert_mem_equal(getenv("HOME"), M_HOME, strlen(M_HOME) + 1); + + /* should overwrite (without malloc) */ + zassert_ok(setenv("HOME", "/root", 1)); + zassert_mem_equal(getenv("HOME"), "/root", strlen("/root") + 1); +} + +ZTEST(env, test_unsetenv) +{ + /* not hardened / application should fault */ + zassert_equal(unsetenv(NULL), -1); + zassert_equal(errno, EINVAL); + + errno = 0; + /* bug in picolibc / newlib */ + zassert_equal(unsetenv(""), -1); + zassert_equal(errno, EINVAL); + + zassert_equal(unsetenv("invalid=key"), -1); + zassert_equal(errno, EINVAL); + + /* restore original environ */ + environ = old_environ; + /* should overwrite (requires realloc) */ + zassert_ok(setenv("HOME", _m_alt_home, 1)); + zassert_mem_equal(getenv("HOME"), _m_alt_home, strlen(_m_alt_home) + 1); + zassert_ok(unsetenv("HOME")); + zassert_is_null(getenv("HOME")); +} + +ZTEST(env, test_watertight) +{ + extern size_t posix_env_get_allocated_space(void); + + char buf[4]; + + /* restore original environ, which should support realloc, free, etc */ + environ = old_environ; + + for (int i = 0; i < 256; ++i) { + snprintf(buf, sizeof(buf), "%u", i); + zassert_ok(setenv("COUNTER", buf, 1)); + zassert_mem_equal(getenv("COUNTER"), buf, strlen(buf)); + zassert_ok(getenv_r("COUNTER", buf, sizeof(buf))); + zassert_equal(atoi(buf), i); + zassert_ok(unsetenv("COUNTER")); + } + + zassert_equal(posix_env_get_allocated_space(), 0); +} + +static void before(void *arg) +{ + old_environ = environ; + + RESET_ENVIRON(home, "HOME", M_HOME); + RESET_ENVIRON(uid, "UID", M_UID); + RESET_ENVIRON(pwd, "PWD", M_PWD); + environ_for_test[0] = home; + environ_for_test[1] = uid; + environ_for_test[2] = pwd; + + zassert_equal((environ = environ_for_test), environ_for_test); +} + +static void after(void *arg) +{ + environ = old_environ; +} + +ZTEST_SUITE(env, NULL, NULL, before, after, NULL); diff --git a/tests/posix/env/testcase.yaml b/tests/posix/env/testcase.yaml new file mode 100644 index 00000000000..305fdfff5f8 --- /dev/null +++ b/tests/posix/env/testcase.yaml @@ -0,0 +1,32 @@ +common: + filter: not CONFIG_NATIVE_LIBC + arch_exclude: + - posix + integration_platforms: + - qemu_riscv64 + tags: posix +tests: + portability.posix.env: {} + portability.posix.env.armclang_std_libc: + toolchain_allow: armclang + extra_configs: + - CONFIG_ARMCLANG_STD_LIBC=y + portability.posix.env.arcmwdtlib: + toolchain_allow: arcmwdt + extra_configs: + - CONFIG_ARCMWDT_LIBC=y + portability.posix.env.minimal: + extra_configs: + - CONFIG_MINIMAL_LIBC=y + - CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=256 + portability.posix.env.newlib: + platform_exclude: + - hifive1 + filter: TOOLCHAIN_HAS_NEWLIB == 1 + extra_configs: + - CONFIG_NEWLIB_LIBC=y + portability.posix.env.picolibc: + tags: picolibc + filter: CONFIG_PICOLIBC_SUPPORTED + extra_configs: + - CONFIG_PICOLIBC=y From 284cecd4cc15f5b4f3a9773d8d17f53867f36b55 Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Sun, 17 Dec 2023 19:21:15 -0500 Subject: [PATCH 0351/2402] doc: posix: add environ, getenv, setenv, and unsetenv Mark environ, getenv(), setevn(), and unsetenv as supported. Signed-off-by: Christopher Friedt --- doc/services/portability/posix/option_groups/index.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst index d0a37584e3d..6b05b08cd2d 100644 --- a/doc/services/portability/posix/option_groups/index.rst +++ b/doc/services/portability/posix/option_groups/index.rst @@ -164,13 +164,13 @@ process applications. :widths: 50,10 confstr(), - environ, + environ,yes errno,yes - getenv(), - setenv(), + getenv(),yes + setenv(),yes sysconf(),yes uname(),yes - unsetenv() + unsetenv(),yes .. _posix_option_group_signals: From 447fc243529a7d557f7184d4d90bec269118292e Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Thu, 21 Dec 2023 11:35:37 -0500 Subject: [PATCH 0352/2402] posix: shell: add an environment variable shell command This service is used to get, set, and unset system environment variables. Note: shell parameter expansion is not supported at this time. Signed-off-by: Christopher Friedt --- lib/posix/shell/CMakeLists.txt | 1 + lib/posix/shell/Kconfig | 1 + lib/posix/shell/Kconfig.env | 9 +++ lib/posix/shell/env.c | 130 +++++++++++++++++++++++++++++++++ 4 files changed, 141 insertions(+) create mode 100644 lib/posix/shell/Kconfig.env create mode 100644 lib/posix/shell/env.c diff --git a/lib/posix/shell/CMakeLists.txt b/lib/posix/shell/CMakeLists.txt index b6dfe6a565f..89510836558 100644 --- a/lib/posix/shell/CMakeLists.txt +++ b/lib/posix/shell/CMakeLists.txt @@ -3,3 +3,4 @@ zephyr_library_sources_ifdef(CONFIG_POSIX_SHELL posix_shell.c) zephyr_library_sources_ifdef(CONFIG_POSIX_UNAME_SHELL uname.c) +zephyr_library_sources_ifdef(CONFIG_POSIX_ENV_SHELL env.c) diff --git a/lib/posix/shell/Kconfig b/lib/posix/shell/Kconfig index d7116b492a8..294d97a8b79 100644 --- a/lib/posix/shell/Kconfig +++ b/lib/posix/shell/Kconfig @@ -10,6 +10,7 @@ config POSIX_SHELL help Compile the parent `posix` shell command. +rsource "Kconfig.env" rsource "Kconfig.uname" endif # SHELL diff --git a/lib/posix/shell/Kconfig.env b/lib/posix/shell/Kconfig.env new file mode 100644 index 00000000000..d2d5fd53b3e --- /dev/null +++ b/lib/posix/shell/Kconfig.env @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Meta +# SPDX-License-Identifier: Apache-2.0 + +config POSIX_ENV_SHELL + bool "Support for shell" + select POSIX_ENV + select POSIX_SHELL + help + This shell provides access to system environment variables. diff --git a/lib/posix/shell/env.c b/lib/posix/shell/env.c new file mode 100644 index 00000000000..48b3b2a94e3 --- /dev/null +++ b/lib/posix/shell/env.c @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2023, Meta + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "posix_shell.h" + +#include +#include +#include + +#include + +#define HELP_ENV_GET "[NAME]" +#define HELP_ENV_SET "NAME VALUE | NAME=VALUE" +#define HELP_ENV_UNSET "NAME.." + +static int cmd_env_get(const struct shell *sh, size_t argc, char **argv) +{ + const char *name; + const char *value; + + switch (argc) { + case 1: { + extern char **environ; + /* list all environment variables */ + if (environ != NULL) { + for (char **envp = environ; *envp != NULL; ++envp) { + shell_print(sh, "%s", *envp); + } + } + } break; + case 2: + /* list a specific environment variable */ + name = argv[1]; + value = getenv(name); + if (value != NULL) { + shell_print(sh, "%s", value); + } + break; + default: + return EXIT_FAILURE; + } + + return EXIT_SUCCESS; +} + +static bool is_shell_env_name(const char *name) +{ + char c; + + if (name == NULL || name[0] == '\0') { + return false; + } + + for (size_t i = 0, N = strlen(name); i < N; ++i) { + c = name[i]; + + if (c == '_') { + continue; + } + + if (isalpha(c)) { + continue; + } + + if (i > 0 && isdigit(c)) { + continue; + } + + return false; + } + + return true; +} + +static int cmd_env_set(const struct shell *sh, size_t argc, char **argv) +{ + int ret; + char *value; + const char *name; + + switch (argc) { + case 2: + name = argv[1]; + value = strchr(argv[1], '='); + if (value != NULL) { + *value = '\0'; + ++value; + } + break; + case 3: + name = argv[1]; + value = argv[2]; + break; + default: + return EXIT_FAILURE; + } + + /* silently drop "poorly conditioned" environment variables */ + if (!is_shell_env_name(name)) { + shell_print(sh, "bad name"); + return EXIT_SUCCESS; + } + + ret = setenv(name, value, 1); + if (ret == -1) { + return EXIT_FAILURE; + } + + return EXIT_SUCCESS; +} + +static int cmd_env_unset(const struct shell *sh, size_t argc, char **argv) +{ + for (--argc, ++argv; argc > 0; --argc, ++argv) { + (void)unsetenv(argv[0]); + } + + return EXIT_SUCCESS; +} + +SHELL_STATIC_SUBCMD_SET_CREATE(sub_env, SHELL_CMD(set, NULL, HELP_ENV_SET, cmd_env_set), + SHELL_CMD(get, NULL, HELP_ENV_GET, cmd_env_get), + SHELL_CMD(unset, NULL, HELP_ENV_UNSET, cmd_env_unset), + SHELL_SUBCMD_SET_END /* Array terminated. */ +); + +POSIX_CMD_ADD(env, &sub_env, "Print system information", NULL, 1, 255); From 529023e6f8ef0699abb07dc28cd7249d01f87e5a Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Sat, 3 Feb 2024 18:49:45 -0500 Subject: [PATCH 0353/2402] posix: manually define _POSIX_C_SOURCE in lib/posix This PR adds declarations for the application conformance feature test macro _POSIX_C_SOURCE. It needs to be defined to value greater than or equal to 200112L by the appplication. However, Zephyr currently does not have a simple and consistent means of specifying this value for POSIX samples, tests, applications, and other libraries. Signed-off-by: Christopher Friedt --- lib/posix/shell/CMakeLists.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/posix/shell/CMakeLists.txt b/lib/posix/shell/CMakeLists.txt index 89510836558..2d809f5b74f 100644 --- a/lib/posix/shell/CMakeLists.txt +++ b/lib/posix/shell/CMakeLists.txt @@ -1,6 +1,12 @@ # Copyright (c) 2024 Meta # SPDX-License-Identifier: Apache-2.0 +zephyr_library() +# For setenv() and unsetenv() +zephyr_library_compile_options(-U_POSIX_C_SOURCE -D_POSIX_C_SOURCE=200809L) +# For getenv_r() visibility +zephyr_library_compile_definitions(_BSD_SOURCE) + zephyr_library_sources_ifdef(CONFIG_POSIX_SHELL posix_shell.c) zephyr_library_sources_ifdef(CONFIG_POSIX_UNAME_SHELL uname.c) zephyr_library_sources_ifdef(CONFIG_POSIX_ENV_SHELL env.c) From 6ef6cf54b4ab48fe38696dccce20c29f1dc80940 Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Sat, 3 Feb 2024 18:52:41 -0500 Subject: [PATCH 0354/2402] samples: posix: add environment variable sample app Add a sample application to demonstrate some basic C and shell interfaces for manipulating environment variables. Signed-off-by: Christopher Friedt --- samples/posix/env/CMakeLists.txt | 12 +++++ samples/posix/env/README.rst | 82 ++++++++++++++++++++++++++++++++ samples/posix/env/prj.conf | 5 ++ samples/posix/env/sample.yaml | 19 ++++++++ samples/posix/env/src/main.c | 70 +++++++++++++++++++++++++++ 5 files changed, 188 insertions(+) create mode 100644 samples/posix/env/CMakeLists.txt create mode 100644 samples/posix/env/README.rst create mode 100644 samples/posix/env/prj.conf create mode 100644 samples/posix/env/sample.yaml create mode 100644 samples/posix/env/src/main.c diff --git a/samples/posix/env/CMakeLists.txt b/samples/posix/env/CMakeLists.txt new file mode 100644 index 00000000000..9d7a3f2e863 --- /dev/null +++ b/samples/posix/env/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(posix_env) + +target_sources(app PRIVATE src/main.c) +# For setenv() and unsetenv() +target_compile_options(app PRIVATE -U_POSIX_C_SOURCE -D_POSIX_C_SOURCE=200809L) +# For getenv_r() visibility and testing +target_compile_definitions(app PRIVATE _BSD_SOURCE) diff --git a/samples/posix/env/README.rst b/samples/posix/env/README.rst new file mode 100644 index 00000000000..6ece6691f79 --- /dev/null +++ b/samples/posix/env/README.rst @@ -0,0 +1,82 @@ +.. _posix-env-sample: + +POSIX Environment Variables +########################### + +Overview +******** + +In this sample application, the POSIX :c:func:`setenv`, function is used to populate several environment +variables in C. Then, all environment variables are then printed. + +If the user sets a new value for the ``ALERT`` environment variable, it is printed to standard +output, and then cleared via :c:func:`unsetenv`. + +Building and Running +******************** + +This project outputs to the console. It can be built and executed on QEMU as follows: + +.. zephyr-app-commands:: + :zephyr-app: samples/posix/env + :host-os: unix + :board: qemu_riscv32 + :goals: run + :compact: + +Sample Output +============= + +The program below shows sample output for a specific Zephyr build. + +.. code-block:: console + + BOARD=qemu_riscv32 + BUILD_VERSION=zephyr-v3.5.0-5372-g3a46f2d052c7 + ALERT= + +Setting Environment Variables +============================= + +The shell command below shows how to create a new environment variable or update the value +associated with an existing environment variable. + +The C code that is part of this sample application displays the value associated with the +``ALERT`` environment variable and then immediately unsets it. + +.. code-block:: console + + uart:~$ posix env set ALERT="Happy Friday!" + uart:~$ ALERT="Happy Friday!" + uart:~$ posix env set HOME="127.0.0.1" + uart:~$ + + +Getting Environment Variables +============================= + +The shell command below may be used to display the value associated with one environment variable. + +.. code-block:: console + + uart:~$ posix env get BOARD + qemu_riscv32 + +The shell command below may be used to display all environment variables and their associated +values. + +.. code-block:: console + + uart:~$ posix env get + BOARD=qemu_riscv32 + BUILD_VERSION=zephyr-v3.5.0-5372-g3a46f2d052c7 + ALERT= + +Unsetting Environment Variables +=============================== + +The shell command below may be used to unset environment variables. + +.. code-block:: console + + uart:~$ posix env unset BOARD diff --git a/samples/posix/env/prj.conf b/samples/posix/env/prj.conf new file mode 100644 index 00000000000..ef33bda5441 --- /dev/null +++ b/samples/posix/env/prj.conf @@ -0,0 +1,5 @@ +CONFIG_POSIX_API=y +CONFIG_SHELL=y +CONFIG_POSIX_ENV_SHELL=y +CONFIG_DYNAMIC_THREAD=y +CONFIG_DYNAMIC_THREAD_POOL_SIZE=1 diff --git a/samples/posix/env/sample.yaml b/samples/posix/env/sample.yaml new file mode 100644 index 00000000000..cf9b166ae7f --- /dev/null +++ b/samples/posix/env/sample.yaml @@ -0,0 +1,19 @@ +sample: + description: posix env sample + name: posix env +common: + tags: posix env + platform_exclude: + - native_posix + - native_posix_64 + integration_platforms: + - qemu_riscv32 + harness: console + harness_config: + type: multi_line + regex: + - "BOARD=.*" + - "BUILD_VERSION=.*" + - "ALERT=.*" +tests: + sample.posix.env: {} diff --git a/samples/posix/env/src/main.c b/samples/posix/env/src/main.c new file mode 100644 index 00000000000..9385abce644 --- /dev/null +++ b/samples/posix/env/src/main.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2023 Meta + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "version.h" + +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef BUILD_VERSION +#define VERSION_BUILD STRINGIFY(BUILD_VERSION) +#else +#define VERSION_BUILD KERNEL_VERSION_STRING +#endif + +#if defined(CONFIG_NEWLIB_LIBC) || defined(CONFIG_PICOLIBC) +/* newlib headers seem to be missing this */ +int getenv_r(const char *name, char *val, size_t len); +#endif + +static void env(void) +{ + extern char **environ; + + if (environ != NULL) { + for (char **envp = environ; *envp != NULL; ++envp) { + printf("%s\n", *envp); + } + } +} + +static void *entry(void *arg) +{ + static char alert_msg_buf[42]; + + setenv("BOARD", CONFIG_BOARD, 1); + setenv("BUILD_VERSION", VERSION_BUILD, 1); + setenv("ALERT", "", 1); + + env(); + + while (true) { + sleep(1); + if (getenv_r("ALERT", alert_msg_buf, sizeof(alert_msg_buf) - 1) < 0 || + strlen(alert_msg_buf) == 0) { + continue; + } + printf("ALERT=%s\n", alert_msg_buf); + unsetenv("ALERT"); + } + + return NULL; +} + +int main(void) +{ + pthread_t th; + + /* create a separate thread so that the shell can start */ + return pthread_create(&th, NULL, entry, NULL); +} From e2f0b92fda1c79bf51cba7a1331c62c3f722129e Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Tue, 5 Mar 2024 15:29:30 +0100 Subject: [PATCH 0355/2402] net: lib: shell: Fix IPv6 neighbor build When building net shell without IPv6 native support we can't use neighbor support. Signed-off-by: Pieter De Gendt --- subsys/net/lib/shell/nbr.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/subsys/net/lib/shell/nbr.c b/subsys/net/lib/shell/nbr.c index 63b62406702..809bba9277f 100644 --- a/subsys/net/lib/shell/nbr.c +++ b/subsys/net/lib/shell/nbr.c @@ -12,12 +12,10 @@ LOG_MODULE_DECLARE(net_shell); static int cmd_net_nbr_rm(const struct shell *sh, size_t argc, char *argv[]) { -#if defined(CONFIG_NET_IPV6) +#if defined(CONFIG_NET_NATIVE_IPV6) struct in6_addr addr; int ret; -#endif -#if defined(CONFIG_NET_IPV6) if (!argv[1]) { PR_WARNING("Neighbor IPv6 address missing.\n"); return -ENOEXEC; @@ -37,16 +35,17 @@ static int cmd_net_nbr_rm(const struct shell *sh, size_t argc, char *argv[]) PR("Neighbor %s removed.\n", net_sprint_ipv6_addr(&addr)); #else + ARG_UNUSED(sh); ARG_UNUSED(argc); ARG_UNUSED(argv); - PR_INFO("IPv6 not enabled.\n"); + PR_INFO("Native IPv6 not enabled.\n"); #endif return 0; } -#if defined(CONFIG_NET_IPV6) +#if defined(CONFIG_NET_NATIVE_IPV6) static void nbr_cb(struct net_nbr *nbr, void *user_data) { struct net_shell_user_data *data = user_data; @@ -111,15 +110,10 @@ static void nbr_cb(struct net_nbr *nbr, void *user_data) static int cmd_net_nbr(const struct shell *sh, size_t argc, char *argv[]) { -#if defined(CONFIG_NET_IPV6) +#if defined(CONFIG_NET_NATIVE_IPV6) int count = 0; struct net_shell_user_data user_data; -#endif - - ARG_UNUSED(argc); - ARG_UNUSED(argv); -#if defined(CONFIG_NET_IPV6) user_data.sh = sh; user_data.user_data = &count; @@ -129,13 +123,17 @@ static int cmd_net_nbr(const struct shell *sh, size_t argc, char *argv[]) PR("No neighbors.\n"); } #else - PR_INFO("IPv6 not enabled.\n"); -#endif /* CONFIG_NET_IPV6 */ + ARG_UNUSED(sh); + ARG_UNUSED(argc); + ARG_UNUSED(argv); + + PR_INFO("Native IPv6 not enabled.\n"); +#endif /* CONFIG_NET_NATIVE_IPV6 */ return 0; } -#if defined(CONFIG_NET_IPV6) && defined(CONFIG_NET_SHELL_DYN_CMD_COMPLETION) +#if defined(CONFIG_NET_NATIVE_IPV6) && defined(CONFIG_NET_SHELL_DYN_CMD_COMPLETION) static char nbr_address_buffer[CONFIG_NET_IPV6_MAX_NEIGHBORS][NET_IPV6_ADDR_LEN]; static void nbr_address_cb(struct net_nbr *nbr, void *user_data) @@ -193,7 +191,7 @@ static void nbr_address_get(size_t idx, struct shell_static_entry *entry) #else #define NBR_ADDRESS_CMD NULL -#endif /* CONFIG_NET_IPV6 && CONFIG_NET_SHELL_DYN_CMD_COMPLETION */ +#endif /* CONFIG_NET_NATIVE_IPV6 && CONFIG_NET_SHELL_DYN_CMD_COMPLETION */ SHELL_STATIC_SUBCMD_SET_CREATE(net_cmd_nbr, SHELL_CMD(rm, NBR_ADDRESS_CMD, From ca52603b0979b9a9426203037173d2850e8189d5 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Sun, 11 Feb 2024 17:36:10 +0000 Subject: [PATCH 0356/2402] MAINTAINERS: Add self to LED strip as collaborator Add myself to LED strip as a collaborator Signed-off-by: Jamie McCrae --- MAINTAINERS.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 29ed8607d37..f55b852581f 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -1559,6 +1559,7 @@ Release Notes: - simonguinot collaborators: - soburi + - thedjnK files: - drivers/led_strip/ - dts/bindings/led_strip/ From 96677e402e76170938c5c61948c27d2d34ecd5bb Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Tue, 5 Mar 2024 23:15:40 +0200 Subject: [PATCH 0357/2402] drivers: display: smartbond: Add support for the display driver class. Exhibit Renesas LCD controller's driver implementation. The driver is intended to employ the controller in the continuous mode so it can drive display panels in the parallel RGB mode. Signed-off-by: Ioannis Karachalios --- drivers/display/CMakeLists.txt | 1 + drivers/display/Kconfig | 1 + drivers/display/Kconfig.renesas_lcdc | 19 + drivers/display/display_renesas_lcdc.c | 582 ++++++++++++++++++ .../display/renesas,smartbond-display.yaml | 37 ++ 5 files changed, 640 insertions(+) create mode 100644 drivers/display/Kconfig.renesas_lcdc create mode 100644 drivers/display/display_renesas_lcdc.c create mode 100644 dts/bindings/display/renesas,smartbond-display.yaml diff --git a/drivers/display/CMakeLists.txt b/drivers/display/CMakeLists.txt index 0350efdd44b..f6138ff99f2 100644 --- a/drivers/display/CMakeLists.txt +++ b/drivers/display/CMakeLists.txt @@ -25,6 +25,7 @@ zephyr_library_sources_ifdef(CONFIG_RM67162 display_rm67162.c) zephyr_library_sources_ifdef(CONFIG_HX8394 display_hx8394.c) zephyr_library_sources_ifdef(CONFIG_GC9X01X display_gc9x01x.c) zephyr_library_sources_ifdef(CONFIG_LED_STRIP_MATRIX display_led_strip_matrix.c) +zephyr_library_sources_ifdef(CONFIG_DISPLAY_RENESAS_LCDC display_renesas_lcdc.c) zephyr_library_sources_ifdef(CONFIG_MICROBIT_DISPLAY mb_display.c diff --git a/drivers/display/Kconfig b/drivers/display/Kconfig index cb811c7965f..6a355da7aeb 100644 --- a/drivers/display/Kconfig +++ b/drivers/display/Kconfig @@ -42,5 +42,6 @@ source "drivers/display/Kconfig.otm8009a" source "drivers/display/Kconfig.hx8394" source "drivers/display/Kconfig.gc9x01x" source "drivers/display/Kconfig.led_strip_matrix" +source "drivers/display/Kconfig.renesas_lcdc" endif # DISPLAY diff --git a/drivers/display/Kconfig.renesas_lcdc b/drivers/display/Kconfig.renesas_lcdc new file mode 100644 index 00000000000..39605487cab --- /dev/null +++ b/drivers/display/Kconfig.renesas_lcdc @@ -0,0 +1,19 @@ +# Smartbond display controller configuration options + +# Copyright (c) 2023 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config DISPLAY_RENESAS_LCDC + bool "Smartbond display controller driver" + depends on DT_HAS_RENESAS_SMARTBOND_DISPLAY_ENABLED + select DMA + default y + help + Enable Smartbond display controller. + +config DISPLAY_RENESAS_LCDC_BUFFER_PSRAM + bool "Allocate the display buffer into PSRAM" + depends on DISPLAY_RENESAS_LCDC + select MEMC + help + Allocate the display buffer into PSRAM diff --git a/drivers/display/display_renesas_lcdc.c b/drivers/display/display_renesas_lcdc.c new file mode 100644 index 00000000000..c09b48ac003 --- /dev/null +++ b/drivers/display/display_renesas_lcdc.c @@ -0,0 +1,582 @@ +/* + * Copyright (c) 2023 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT renesas_smartbond_display + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +LOG_MODULE_REGISTER(smartbond_display, CONFIG_DISPLAY_LOG_LEVEL); + +#define SMARTBOND_IRQN DT_INST_IRQN(0) +#define SMARTBOND_IRQ_PRIO DT_INST_IRQ(0, priority) + +#define LCDC_SMARTBOND_CLK_DIV(_freq) \ + ((32000000U % (_freq)) ? (96000000U / (_freq)) : (32000000U / (_freq))) + +#define LCDC_SMARTBOND_IS_PLL_REQUIRED \ + !!(32000000U % DT_PROP(DT_INST_CHILD(0, display_timings), clock_frequency)) + +#define DISPLAY_SMARTBOND_IS_DMA_PREFETCH_ENABLED \ + DT_INST_ENUM_IDX_OR(0, dma_prefetch, 0) + +#define LCDC_LAYER0_OFFSETX_REG_SET_FIELD(_field, _var, _val)\ + ((_var)) = \ + ((_var) & ~(LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk)) | \ + (((_val) << LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Pos) & \ + LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk) + +#define DISPLAY_SMARTBOND_PIXEL_SIZE(inst) \ + (DISPLAY_BITS_PER_PIXEL(DT_INST_PROP(inst, pixel_format)) / 8) + +#if CONFIG_DISPLAY_RENESAS_LCDC_BUFFER_PSRAM +#define DISPLAY_BUFFER_LINKER_SECTION \ + Z_GENERIC_SECTION(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(psram))) +#else +#define DISPLAY_BUFFER_LINKER_SECTION +#endif + +struct display_smartbond_data { + /* Provide mutual exclusion when a display operation is requested. */ + struct k_sem device_sem; + /* Frame update synchronization token */ + struct k_sem sync_sem; + /* Flag indicating whether or not an underflow took place */ + volatile bool underflow_flag; + /* Layer settings */ + lcdc_smartbond_layer_cfg layer; + /* Frame buffer */ + uint8_t *buffer; + /* DMA device */ + const struct device *dma; + /* DMA configuration structures */ + struct dma_config dma_cfg; + struct dma_block_config dma_block_cfg; + /* DMA memory transfer synchronization token */ + struct k_sem dma_sync_sem; + /* Granted DMA channel used for memory transfers */ + int dma_channel; +}; + +struct display_smartbond_config { + /* Reference to device instance's pinctrl configurations */ + const struct pinctrl_dev_config *pcfg; + /* Display ON/OFF GPIO */ + const struct gpio_dt_spec disp; + /* Host controller's timing settings */ + lcdc_smartbond_timing_cfg timing_cfg; + /* Parallel interface settings */ + lcdc_smartbond_mode_cfg mode; + /* Background default color configuration */ + lcdc_smartbond_bgcolor_cfg bgcolor_cfg; + /* Display dimensions */ + const uint16_t x_res; + const uint16_t y_res; + /* Pixel size in bytes */ + uint8_t pixel_size; + enum display_pixel_format pixel_format; +}; + +/* Display pixel to layer color format translation */ +static uint8_t lcdc_smartbond_pixel_to_lcm(enum display_pixel_format pixel_format) +{ + switch (pixel_format) { + case PIXEL_FORMAT_RGB_565: + return (uint8_t)LCDC_SMARTBOND_L0_RGB565; + case PIXEL_FORMAT_ARGB_8888: + return (uint8_t)LCDC_SMARTBOND_L0_ARGB8888; + default: + LOG_ERR("Unsupported pixel format"); + return 0; + }; +} + +static int display_smartbond_configure(const struct device *dev) +{ + uint8_t clk_div = + LCDC_SMARTBOND_CLK_DIV(DT_PROP(DT_INST_CHILD(0, display_timings), clock_frequency)); + + const struct display_smartbond_config *config = dev->config; + struct display_smartbond_data *data = dev->data; + + int ret = 0; + + /* First enable the controller so registers can be written. */ + da1469x_lcdc_set_status(true, LCDC_SMARTBOND_IS_PLL_REQUIRED, clk_div); + + if (!da1469x_lcdc_check_id()) { + LOG_ERR("Invalid LCDC ID"); + da1469x_lcdc_set_status(false, false, 0); + return -EINVAL; + } + + da1469x_lcdc_parallel_interface_configure((lcdc_smartbond_mode_cfg *)&config->mode); + da1469x_lcdc_bgcolor_configure((lcdc_smartbond_bgcolor_cfg *)&config->bgcolor_cfg); + + /* + * Partial update is not supported and so timing and layer settings can be configured + * once at initialization. + */ + ret = da1469x_lcdc_timings_configure(config->x_res, config->y_res, + (lcdc_smartbond_timing_cfg *)&config->timing_cfg); + if (ret < 0) { + LOG_ERR("Unable to configure timing settings"); + da1469x_lcdc_set_status(false, false, 0); + return ret; + } + + /* + * Stride should be updated at the end of a frame update (typically in ISR context). + * It's OK to update stride here as continuous mode should not be enabled yet. + */ + data->layer.color_format = + lcdc_smartbond_pixel_to_lcm(config->pixel_format); + data->layer.stride = + da1469x_lcdc_stride_calculation(data->layer.color_format, config->x_res); + + ret = da1469x_lcdc_layer_configure(&data->layer); + if (ret < 0) { + LOG_ERR("Unable to configure layer settings"); + da1469x_lcdc_set_status(false, false, 0); + } + + LCDC_LAYER0_OFFSETX_REG_SET_FIELD(LCDC_L0_DMA_PREFETCH, + LCDC->LCDC_LAYER0_OFFSETX_REG, DISPLAY_SMARTBOND_IS_DMA_PREFETCH_ENABLED); + + LCDC->LCDC_MODE_REG |= LCDC_LCDC_MODE_REG_LCDC_MODE_EN_Msk; + + return ret; +} + +static void smartbond_display_isr(const void *arg) +{ + struct display_smartbond_data *data = ((const struct device *)arg)->data; + + data->underflow_flag = LCDC_STATUS_REG_GET_FIELD(LCDC_STICKY_UNDERFLOW); + + /* + * Underflow sticky bit will remain high until cleared by writing + * any value to LCDC_INTERRUPT_REG. + */ + LCDC->LCDC_INTERRUPT_REG &= ~LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk; + + /* Notify that current frame update is completed */ + k_sem_give(&data->sync_sem); +} + +static int display_smartbond_resume(const struct device *dev) +{ + const struct display_smartbond_config *config = dev->config; + int ret; + + /* Select default state */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + LOG_ERR("Could not apply LCDC pins' default state (%d)", ret); + return -EIO; + } + +#if LCDC_SMARTBOND_IS_PLL_REQUIRED + const struct device *clock_dev = DEVICE_DT_GET(DT_NODELABEL(osc)); + + if (!device_is_ready(clock_dev)) { + LOG_WRN("Clock device is not ready"); + return -ENODEV; + } + + ret = z_smartbond_select_sys_clk(SMARTBOND_CLK_PLL96M); + if (ret < 0) { + LOG_WRN("Could not switch to PLL"); + return -EIO; + } +#endif + + return display_smartbond_configure(dev); +} + +static void display_smartbond_dma_cb(const struct device *dma, void *arg, + uint32_t id, int status) +{ + struct display_smartbond_data *data = arg; + + if (status < 0) { + LOG_WRN("DMA transfer did not complete"); + } + + k_sem_give(&data->dma_sync_sem); +} + +static int display_smartbond_dma_config(const struct device *dev) +{ + struct display_smartbond_data *data = dev->data; + + data->dma = DEVICE_DT_GET(DT_NODELABEL(dma)); + if (!device_is_ready(data->dma)) { + LOG_ERR("DMA device is not ready"); + return -ENODEV; + } + + data->dma_cfg.channel_direction = MEMORY_TO_MEMORY; + data->dma_cfg.user_data = data; + data->dma_cfg.dma_callback = display_smartbond_dma_cb; + data->dma_cfg.block_count = 1; + data->dma_cfg.head_block = &data->dma_block_cfg; + + /* Request an arbitrary DMA channel */ + data->dma_channel = dma_request_channel(data->dma, NULL); + if (data->dma_channel < 0) { + LOG_ERR("Could not acquire a DMA channel"); + return -EIO; + } + + return 0; +} + + +static int display_smartbond_init(const struct device *dev) +{ + const struct display_smartbond_config *config = dev->config; + struct display_smartbond_data *data = dev->data; + int ret; + + /* Device should be ready to be acquired */ + k_sem_init(&data->device_sem, 1, 1); + /* Event should be signaled by LCDC ISR */ + k_sem_init(&data->sync_sem, 0, 1); + /* Event should be signaled by DMA ISR */ + k_sem_init(&data->dma_sync_sem, 0, 1); + + /* As per docs, display port should be enabled by default. */ + if (gpio_is_ready_dt(&config->disp)) { + ret = gpio_pin_configure_dt(&config->disp, GPIO_OUTPUT_ACTIVE); + if (ret < 0) { + LOG_ERR("Could not activate display port"); + return -EIO; + } + } + + ret = display_smartbond_resume(dev); + if (ret < 0) { + return ret; + } + + ret = display_smartbond_dma_config(dev); + if (ret < 0) { + return ret; + } + + IRQ_CONNECT(SMARTBOND_IRQN, SMARTBOND_IRQ_PRIO, smartbond_display_isr, + DEVICE_DT_INST_GET(0), 0); + +#if CONFIG_PM + /* + * When in continues mode, the display device should always be refreshed + * and so the controller is not allowed to be turned off. The latter, is + * powered by PD_SYS which is turned off when the SoC enters the extended + * sleep state. By acquiring PD_SYS, the deep sleep state is prevented + * and the system enters the low-power state (i.e. ARM WFI) when possible. + * + * XXX CONFIG_PM_DEVICE_RUNTIME is no supported yet! + */ + da1469x_pd_acquire_noconf(MCU_PD_DOMAIN_SYS); +#endif + + return 0; +} + +static int display_smartbond_blanking_on(const struct device *dev) +{ + const struct display_smartbond_config *config = dev->config; + struct display_smartbond_data *data = dev->data; + int ret = 0; + + k_sem_take(&data->device_sem, K_FOREVER); + + /* + * This bit will force LCD controller's output to blank that is, + * the controller will keep operating without outputting any + * pixel data. + */ + LCDC->LCDC_MODE_REG |= LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Msk; + + /* If enabled, disable display port. */ + if (gpio_is_ready_dt(&config->disp)) { + ret = gpio_pin_configure_dt(&config->disp, GPIO_OUTPUT_INACTIVE); + if (ret < 0) { + LOG_WRN("Display port could not be de-activated"); + } + } + + k_sem_give(&data->device_sem); + + return ret; +} + +static int display_smartbond_blanking_off(const struct device *dev) +{ + const struct display_smartbond_config *config = dev->config; + struct display_smartbond_data *data = dev->data; + int ret = 0; + + k_sem_take(&data->device_sem, K_FOREVER); + + /* If used, enable display port */ + if (gpio_is_ready_dt(&config->disp)) { + ret = gpio_pin_configure_dt(&config->disp, GPIO_OUTPUT_ACTIVE); + if (ret < 0) { + LOG_WRN("Display port could not be activated"); + } + } + + /* + * This bit will force LCD controller's output to blank that is, + * the controller will keep operating without outputting any + * pixel data. + */ + LCDC->LCDC_MODE_REG &= ~LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Msk; + + k_sem_give(&data->device_sem); + + return ret; +} + +static void *display_smartbond_get_framebuffer(const struct device *dev) +{ + struct display_smartbond_data *data = dev->data; + + return ((void *)data->buffer); +} + +static void display_smartbond_get_capabilities(const struct device *dev, + struct display_capabilities *capabilities) +{ + memset(capabilities, 0, sizeof(*capabilities)); + + /* + * Multiple color formats should be supported by LCDC. Currently, RGB56 and ARGB888 + * exposed by display API are supported. In the future we should consider supporting + * more color formats which should require changes in LVGL porting. + * Here, only one color format should be supported as the frame buffer is accessed + * directly by LCDC and is allocated statically during device initialization. The color + * format is defined based on the pixel-format property dictated by lcd-controller + * bindings. + */ + capabilities->supported_pixel_formats = DT_INST_PROP(0, pixel_format); + capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL; + capabilities->current_pixel_format = DT_INST_PROP(0, pixel_format); + capabilities->x_resolution = DT_INST_PROP(0, width); + capabilities->y_resolution = DT_INST_PROP(0, height); +} + +static int display_smartbond_read(const struct device *dev, + const uint16_t x, const uint16_t y, + const struct display_buffer_descriptor *desc, + void *buf) +{ + struct display_smartbond_data *data = dev->data; + const struct display_smartbond_config *config = dev->config; + uint8_t *dst = buf; + const uint8_t *src = data->buffer; + + k_sem_take(&data->device_sem, K_FOREVER); + + /* pointer to upper left pixel of the rectangle */ + src += (x * config->pixel_size); + src += (y * data->layer.stride); + + data->dma_block_cfg.block_size = desc->width * config->pixel_size; + /* + * Source and destination base address is word aligned. + * Data size should be selected based on color depth as + * cursor is shifted multiple of pixel color depth. + */ + data->dma_cfg.source_data_size = data->dma_cfg.dest_data_size = + !(config->pixel_size & 3) ? 4 : + !(config->pixel_size & 1) ? 2 : 1; + + data->dma_cfg.dest_burst_length = data->dma_cfg.source_burst_length = + !((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 7) ? 8 : + !((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 3) ? 4 : 1; + + for (int row = 0; row < desc->height; row++) { + + data->dma_block_cfg.dest_address = (uint32_t)dst; + data->dma_block_cfg.source_address = (uint32_t)src; + + if (dma_config(data->dma, data->dma_channel, &data->dma_cfg)) { + LOG_ERR("Could not configure DMA"); + k_sem_give(&data->device_sem); + return -EIO; + } + + if (dma_start(data->dma, data->dma_channel)) { + LOG_ERR("Could not start DMA"); + k_sem_give(&data->device_sem); + return -EIO; + } + + k_sem_take(&data->dma_sync_sem, K_FOREVER); + + src += data->layer.stride; + dst += (desc->pitch * config->pixel_size); + } + + if (dma_stop(data->dma, data->dma_channel)) { + LOG_WRN("Could not stop DMA"); + } + + k_sem_give(&data->device_sem); + + return 0; +} + +static int display_smartbond_write(const struct device *dev, + const uint16_t x, const uint16_t y, + const struct display_buffer_descriptor *desc, + const void *buf) +{ + struct display_smartbond_data *data = dev->data; + const struct display_smartbond_config *config = dev->config; + uint8_t *dst = data->buffer; + const uint8_t *src = buf; + + k_sem_take(&data->device_sem, K_FOREVER); + + /* pointer to upper left pixel of the rectangle */ + dst += (x * config->pixel_size); + dst += (y * data->layer.stride); + + /* + * Wait for the current frame to finish. Do not disable continuous mode as this + * will have visual artifacts. + */ + LCDC->LCDC_INTERRUPT_REG |= LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk; + k_sem_take(&data->sync_sem, K_FOREVER); + + data->dma_block_cfg.block_size = desc->width * config->pixel_size; + /* + * Source and destination base address is word aligned. + * Data size should be selected based on color depth as + * cursor is shifted multiple of pixel color depth. + */ + data->dma_cfg.source_data_size = data->dma_cfg.dest_data_size = + !(config->pixel_size & 3) ? 4 : + !(config->pixel_size & 1) ? 2 : 1; + + data->dma_cfg.dest_burst_length = data->dma_cfg.source_burst_length = + !((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 7) ? 8 : + !((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 3) ? 4 : 1; + + for (int row = 0; row < desc->height; row++) { + + data->dma_block_cfg.dest_address = (uint32_t)dst; + data->dma_block_cfg.source_address = (uint32_t)src; + + if (dma_config(data->dma, data->dma_channel, &data->dma_cfg)) { + LOG_ERR("Could not configure DMA"); + k_sem_give(&data->device_sem); + return -EIO; + } + + if (dma_start(data->dma, data->dma_channel)) { + LOG_ERR("Could not start DMA"); + k_sem_give(&data->device_sem); + return -EIO; + } + + k_sem_take(&data->dma_sync_sem, K_FOREVER); + + dst += data->layer.stride; + src += (desc->pitch * config->pixel_size); + } + + if (dma_stop(data->dma, data->dma_channel)) { + LOG_WRN("Could not stop DMA"); + } + + k_sem_give(&data->device_sem); + + return 0; +} + + +static struct display_driver_api display_smartbond_driver_api = { + .write = display_smartbond_write, + .read = display_smartbond_read, + .get_framebuffer = display_smartbond_get_framebuffer, + .get_capabilities = display_smartbond_get_capabilities, + .blanking_off = display_smartbond_blanking_off, + .blanking_on = display_smartbond_blanking_on +}; + +#define SMARTBOND_DISPLAY_INIT(inst) \ + PINCTRL_DT_INST_DEFINE(inst); \ + \ + __aligned(4) static uint8_t buffer_ ## inst[(((DT_INST_PROP(inst, width) * \ + DISPLAY_SMARTBOND_PIXEL_SIZE(inst)) + 0x3) & ~0x3) * \ + DT_INST_PROP(inst, height)] DISPLAY_BUFFER_LINKER_SECTION; \ + \ + static const struct display_smartbond_config display_smartbond_config_## inst = { \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ + .disp = GPIO_DT_SPEC_INST_GET_OR(inst, disp_gpios, {}), \ + .timing_cfg.vsync_len = \ + DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_len), \ + .timing_cfg.hsync_len = \ + DT_PROP(DT_INST_CHILD(inst, display_timings), hsync_len), \ + .timing_cfg.hfront_porch = \ + DT_PROP(DT_INST_CHILD(inst, display_timings), hfront_porch), \ + .timing_cfg.vfront_porch = \ + DT_PROP(DT_INST_CHILD(inst, display_timings), vfront_porch), \ + .timing_cfg.hback_porch = \ + DT_PROP(DT_INST_CHILD(inst, display_timings), hback_porch), \ + .timing_cfg.vback_porch = \ + DT_PROP(DT_INST_CHILD(inst, display_timings), vback_porch), \ + .bgcolor_cfg = {0xFF, 0xFF, 0xFF, 0}, \ + .x_res = DT_INST_PROP(inst, width), \ + .y_res = DT_INST_PROP(inst, height), \ + .pixel_size = DISPLAY_SMARTBOND_PIXEL_SIZE(inst), \ + .pixel_format = DT_INST_PROP(0, pixel_format), \ + .mode.vsync_pol = \ + DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_active) ? 0 : 1, \ + .mode.hsync_pol = \ + DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_active) ? 0 : 1, \ + .mode.de_pol = \ + DT_PROP(DT_INST_CHILD(inst, display_timings), de_active) ? 0 : 1, \ + .mode.pixelclk_pol = \ + DT_PROP(DT_INST_CHILD(inst, display_timings), pixelclk_active) ? 0 : 1, \ + }; \ + \ + static struct display_smartbond_data display_smartbond_data_## inst = { \ + .buffer = buffer_ ##inst, \ + .layer.start_x = 0, \ + .layer.start_y = 0, \ + .layer.size_x = DT_INST_PROP(inst, width), \ + .layer.size_y = DT_INST_PROP(inst, height), \ + .layer.frame_buf = (uint32_t)buffer_ ## inst, \ + }; \ + \ + \ + DEVICE_DT_INST_DEFINE(inst, display_smartbond_init, NULL, \ + &display_smartbond_data_## inst, \ + &display_smartbond_config_## inst, \ + POST_KERNEL, \ + CONFIG_DISPLAY_INIT_PRIORITY, \ + &display_smartbond_driver_api); + +SMARTBOND_DISPLAY_INIT(0); diff --git a/dts/bindings/display/renesas,smartbond-display.yaml b/dts/bindings/display/renesas,smartbond-display.yaml new file mode 100644 index 00000000000..befe7e68d08 --- /dev/null +++ b/dts/bindings/display/renesas,smartbond-display.yaml @@ -0,0 +1,37 @@ +# Copyright (c) 2023 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +include: [display-controller.yaml, lcd-controller.yaml, pinctrl-device.yaml] + +description: Renesas Smartbond(tm) display controller + +compatible: "renesas,smartbond-display" + +properties: + reg: + required: true + + interrupts: + required: true + + disp-gpios: + type: phandle-array + description: | + Display ON/OFF port control. + + dma-prefetch: + type: string + enum: + - "no-prefetch" + - "prefetch-44-bytes" + - "prefetch-84-bytes" + - "prefetch-116-bytes" + - "prefetch-108-bytes" + description: | + Host controller will wait for at least the specified number of bytes before triggering + a single frame update. The prefetch mechanism should be enabled when frame buffer(s) + is stored into external storage mediums, e.g. PSRAM, that introduce comparable delays. + In such a case it might case that the controller runs into underrun conditions which + results in correpting the whole frame update. It's user's responsibility to ensure that + the selected value does not exceed frame's total size as otherwise the controller will + not be able to trigger the frame update. From cfc0a1ff347614d6b47fd9fb257674ef2dfe6c12 Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Wed, 3 Jan 2024 21:05:59 +0200 Subject: [PATCH 0358/2402] dts: renesas: smartbond: Add support for the display driver class. Define a single node that reflects the LCDC IP. Instead of defining the same IP block twice with different compatibles (mipi dbi, display) we define a single node for the default display interface and other interfaces like the MIPI DBI should override the compatible entry with the appropriate one within its DTS overlay file. Signed-off-by: Ioannis Karachalios --- dts/arm/renesas/smartbond/da1469x.dtsi | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/dts/arm/renesas/smartbond/da1469x.dtsi b/dts/arm/renesas/smartbond/da1469x.dtsi index d5a6340d74c..ae523ae6719 100644 --- a/dts/arm/renesas/smartbond/da1469x.dtsi +++ b/dts/arm/renesas/smartbond/da1469x.dtsi @@ -304,15 +304,6 @@ status = "okay"; }; - mipi_dbi: lcdc@30030000 { - compatible = "renesas,smartbond-mipi-dbi"; - reg = <0x30030000 0x18C>; - interrupts = <32 0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c: i2c@50020600 { compatible = "renesas,smartbond-i2c"; #address-cells = <1>; @@ -332,6 +323,13 @@ interrupts = <9 0>; }; + lcdc: lcdc@30030000 { + compatible = "renesas,smartbond-display"; + reg = <0x30030000 0x18C>; + interrupts = <32 0>; + status = "disabled"; + }; + spi: spi@50020300 { compatible = "renesas,smartbond-spi"; #address-cells = <1>; From 4a83b9955af0c4205f69d3f93039bfb4e1c396ea Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Sun, 25 Feb 2024 20:30:45 +0200 Subject: [PATCH 0359/2402] boards: renesas: smartbond: Add support for the display driver class. Update board's DTS configurations to support the Renesas LCD controller. Signed-off-by: Ioannis Karachalios --- boards/renesas/da1469x_dk_pro/Kconfig.defconfig | 8 ++++++++ .../da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi | 15 +++++++++++++++ boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts | 4 ++++ boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml | 1 + 4 files changed, 28 insertions(+) diff --git a/boards/renesas/da1469x_dk_pro/Kconfig.defconfig b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig index 90e48078674..c0f49a23a2e 100644 --- a/boards/renesas/da1469x_dk_pro/Kconfig.defconfig +++ b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig @@ -14,6 +14,14 @@ config LV_Z_BITS_PER_PIXEL config LV_Z_AREA_X_ALIGNMENT_WIDTH default 2 +config LV_Z_FLUSH_THREAD + default y + +# Use double buffering to avoid visual artifacts as long as +# the DMA is copying data into driver's frame buffer. +config LV_Z_DOUBLE_VDB + default y + endif # LVGL if INPUT diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi index 7fe5111302d..39daff3ff16 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi @@ -32,6 +32,21 @@ }; }; + display_controller_default: display_controller_default { + group1 { + pinmux = , + , + , + , + , + , + , + , + , + ; + }; + }; + spi_controller: spi_controller { group1 { pinmux = , diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts index 826703c7c87..9c019fa3a0c 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts @@ -21,6 +21,10 @@ zephyr,code-partition = &slot0_partition; }; + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + }; + leds { compatible = "gpio-leds"; red_led: led_0 { diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml index 631615c6ffe..eb29fd6c559 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml @@ -20,4 +20,5 @@ supported: - crypto - dma - mipi_dbi + - display vendor: renesas From 6afea7c51cc802037e0809d4ce1c31a6256fee05 Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Wed, 6 Mar 2024 18:33:27 +0200 Subject: [PATCH 0360/2402] boards: renesas: dts: Add overlay files to support LCDC In order to avoid defining almost the same overlays for different sample codes and/or applications a common overlay file per display interface is defined under the boards dts folder. In doing so, an application/sample code will only have to define another overlay explicitly under application's board folder if more blocks are to be enabled. In either case, users should explicitly invoke the requested overfiles at 'west build' invokation by using the DTC_OVERLAY_FILE system variable. Signed-off-by: Ioannis Karachalios --- .../renesas/da1469x_dk_pro/da1469x_dk_pro.dts | 7 -- .../dts/da1469x_dk_pro_lcdc.overlay | 65 +++++++++++++++++++ .../dts}/da1469x_dk_pro_mipi_dbi.overlay | 11 +++- .../boards/da1469x_dk_pro_mipi_dbi.overlay | 31 --------- samples/drivers/display/sample.yaml | 2 +- 5 files changed, 75 insertions(+), 41 deletions(-) create mode 100644 boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay rename {samples/modules/lvgl/demos/boards => boards/renesas/da1469x_dk_pro/dts}/da1469x_dk_pro_mipi_dbi.overlay (79%) delete mode 100644 samples/drivers/display/boards/da1469x_dk_pro_mipi_dbi.overlay diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts index 9c019fa3a0c..f83098f6f19 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts @@ -172,10 +172,3 @@ zephyr_udc0: &usbd { pinctrl-0 = <&spi2_controller>; pinctrl-names = "default"; }; - -&mipi_dbi { - pinctrl-0 = <&mipi_dbi_default>; - pinctrl-1 = <&mipi_dbi_read>; - pinctrl-2 = <&mipi_dbi_sleep>; - pinctrl-names = "default", "read", "sleep"; -}; diff --git a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay new file mode 100644 index 00000000000..afdfb061c05 --- /dev/null +++ b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2023 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + + #include + #include + +/ { + chosen { + zephyr,display = &lcdc; + }; + + lvgl_pointer { + input = <&display_touch>; + status = "okay"; + swap-xy; + }; +}; + +&dma { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + + display_touch: ft6206@38 { + compatible = "focaltech,ft5336"; + status = "okay"; + reg = <0x38>; + int-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + }; +}; + +&lcdc { + status = "okay"; + pinctrl-0 = <&display_controller_default>; + pinctrl-names = "default"; + width = <480>; + height = <272>; + disp-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + pixel-format = ; + + /* + * Panel settings for the NHD-4.3-480272EF-ASXP-CTP + * display panel model which integrates the SC7283 + * driver IC. + */ + display-timings { + compatible = "zephyr,panel-timing"; + hsync-len = <2>; + hfront-porch = <2>; + hback-porch = <3>; + vsync-len = <2>; + vfront-porch = <2>; + vback-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + clock-frequency = <12000000>; + }; +}; diff --git a/samples/modules/lvgl/demos/boards/da1469x_dk_pro_mipi_dbi.overlay b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay similarity index 79% rename from samples/modules/lvgl/demos/boards/da1469x_dk_pro_mipi_dbi.overlay rename to boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay index adf3a174c74..81dbc363d62 100644 --- a/samples/modules/lvgl/demos/boards/da1469x_dk_pro_mipi_dbi.overlay +++ b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay @@ -32,10 +32,17 @@ }; }; -&mipi_dbi { - reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; +&lcdc { + compatible = "renesas,smartbond-mipi-dbi"; status = "okay"; + reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; spi-dev = <&spi2>; + pinctrl-0 = <&mipi_dbi_default>; + pinctrl-1 = <&mipi_dbi_read>; + pinctrl-2 = <&mipi_dbi_sleep>; + pinctrl-names = "default", "read", "sleep"; + #address-cells = <1>; + #size-cells = <0>; ili9340: ili9340@0 { compatible = "ilitek,ili9340"; diff --git a/samples/drivers/display/boards/da1469x_dk_pro_mipi_dbi.overlay b/samples/drivers/display/boards/da1469x_dk_pro_mipi_dbi.overlay deleted file mode 100644 index 81a4bdd8645..00000000000 --- a/samples/drivers/display/boards/da1469x_dk_pro_mipi_dbi.overlay +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2023 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - - #include - #include - - / { - chosen { - zephyr,display = &ili9340; - }; - }; - - &mipi_dbi { - reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - status = "okay"; - spi-dev = <&spi2>; - - ili9340: ili9340@0 { - compatible = "ilitek,ili9340"; - mipi-max-frequency = <48000000>; - status = "okay"; - reg = <0>; - width = <240>; - height = <320>; - pixel-format = ; - rotation = <0>; - }; -}; diff --git a/samples/drivers/display/sample.yaml b/samples/drivers/display/sample.yaml index 2b834dab0f6..39b56903b92 100644 --- a/samples/drivers/display/sample.yaml +++ b/samples/drivers/display/sample.yaml @@ -110,7 +110,7 @@ tests: sample.display.mipi_dbi: platform_allow: - da1469x_dk_pro - extra_args: DTC_OVERLAY_FILE="boards/da1469x_dk_pro_mipi_dbi.overlay" + extra_args: DTC_OVERLAY_FILE="da1469x_dk_pro_mipi_dbi.overlay" tags: - display - mipi_dbi From 9be8310ac967a0d38459db8b7a285f846612002c Mon Sep 17 00:00:00 2001 From: Maciej Baczmanski Date: Tue, 5 Mar 2024 09:01:16 +0100 Subject: [PATCH 0361/2402] kconfig: shell: fix incorrect shell stack size for Thread Shell stack size is too low for OpenThread without joiner functionality, causing overflow. In this commit, the value of stack size is not changed. Incorrect assigning of value for opentrhead with no joiner functionality has been removed. Signed-off-by: Maciej Baczmanski --- subsys/shell/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/subsys/shell/Kconfig b/subsys/shell/Kconfig index 45e469ac457..618570af1e2 100644 --- a/subsys/shell/Kconfig +++ b/subsys/shell/Kconfig @@ -40,9 +40,8 @@ endif config SHELL_STACK_SIZE int "Shell thread stack size" - default 3168 if OPENTHREAD_SHELL && OPENTHREAD_JOINER + default 3168 if OPENTHREAD_SHELL default 3072 if 64BIT - default 2616 if OPENTHREAD_SHELL default 2048 if MULTITHREADING default 0 if !MULTITHREADING help From 06d2d4eda7349ea6ca4d8ef41eb4e26b97d22205 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 16 Feb 2024 11:22:35 +0100 Subject: [PATCH 0362/2402] boards: thingy52: add vendor note on support status Nordic Semiconductor no longer offers support for this board, so warn users to avoid it for new prototypes. Signed-off-by: Gerard Marull-Paretas --- boards/nordic/thingy52/doc/index.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/boards/nordic/thingy52/doc/index.rst b/boards/nordic/thingy52/doc/index.rst index 0dd8b6067b6..e56f00df343 100644 --- a/boards/nordic/thingy52/doc/index.rst +++ b/boards/nordic/thingy52/doc/index.rst @@ -3,6 +3,11 @@ Thingy:52 ######### +.. warning:: + + Nordic Semiconductor no longer offers support for this board, so it is not + recommended for new prototypes. + Overview ******** From 9ba86ec5458f0fec1052155846c10e27d5596496 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Thu, 7 Mar 2024 15:52:48 +0000 Subject: [PATCH 0363/2402] boards: silabs: fix typo Fix Silabs spelling, use the full name. Signed-off-by: Fabio Baltieri --- boards/silabs/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/silabs/index.rst b/boards/silabs/index.rst index 0b658035e63..20a5d34136f 100644 --- a/boards/silabs/index.rst +++ b/boards/silabs/index.rst @@ -1,7 +1,7 @@ .. _boards-silabs: -Silabgs -####### +Silicon Labs +############ .. toctree:: :maxdepth: 1 From 9412ad306f64e3dcd9f37eb6c3cb3c17dbcebc67 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Wed, 6 Mar 2024 11:50:42 +0100 Subject: [PATCH 0364/2402] net: sockets: packet: Ignore the packet type if LL address is not set In case the LL address is not set on a packet for any reason, don't try to access address structure to determine packet type. Signed-off-by: Robert Lubos --- subsys/net/lib/sockets/sockets_packet.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/subsys/net/lib/sockets/sockets_packet.c b/subsys/net/lib/sockets/sockets_packet.c index bcf063abe29..ce4f83190c4 100644 --- a/subsys/net/lib/sockets/sockets_packet.c +++ b/subsys/net/lib/sockets/sockets_packet.c @@ -144,6 +144,10 @@ static void zpacket_set_eth_pkttype(struct net_if *iface, struct sockaddr_ll *addr, struct net_linkaddr *lladdr) { + if (lladdr == NULL || lladdr->addr == NULL) { + return; + } + if (net_eth_is_addr_broadcast((struct net_eth_addr *)lladdr->addr)) { addr->sll_pkttype = PACKET_BROADCAST; } else if (net_eth_is_addr_multicast( From 7bc4ea1e2fb41836241bc138722028f1fc1056c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 22 Feb 2024 10:05:06 +0100 Subject: [PATCH 0365/2402] log: net: add option to set server ip with struct sockaddr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds a function to set the syslog server ip with a struct sockaddr, so that it can be set without a string. Signed-off-by: Fin Maaß --- include/zephyr/logging/log_backend_net.h | 17 +++++++++- subsys/logging/backends/log_backend_net.c | 38 ++++++++++++++++++++--- 2 files changed, 50 insertions(+), 5 deletions(-) diff --git a/include/zephyr/logging/log_backend_net.h b/include/zephyr/logging/log_backend_net.h index cde5ff3ea28..8f3b0eb9ad7 100644 --- a/include/zephyr/logging/log_backend_net.h +++ b/include/zephyr/logging/log_backend_net.h @@ -8,13 +8,14 @@ #define ZEPHYR_LOG_BACKEND_NET_H_ #include +#include #ifdef __cplusplus extern "C" { #endif /** - * @brief Allows user to set a server IP address at runtime + * @brief Allows user to set a server IP address, provided as string, at runtime * * @details This function allows the user to set an IPv4 or IPv6 address at runtime. It can be * called either before or after the backend has been initialized. If it gets called when @@ -27,6 +28,20 @@ extern "C" { */ bool log_backend_net_set_addr(const char *addr); +/** + * @brief Allows user to set a server IP address, provided as sockaddr structure, at runtime + * + * @details This function allows the user to set an IPv4 or IPv6 address at runtime. It can be + * called either before or after the backend has been initialized. If it gets called when + * the net logger backend context is running, it'll release it and create another one with + * the new address next time process() gets called. + * + * @param addr Pointer to the sockaddr structure that contains the IP address. + * + * @return True if address could be set, false otherwise. + */ +bool log_backend_net_set_ip(const struct sockaddr *addr); + /** * @brief update the hostname * diff --git a/subsys/logging/backends/log_backend_net.c b/subsys/logging/backends/log_backend_net.c index 53fe78f243b..92b2f3f719c 100644 --- a/subsys/logging/backends/log_backend_net.c +++ b/subsys/logging/backends/log_backend_net.c @@ -192,7 +192,7 @@ static int format_set(const struct log_backend *const backend, uint32_t log_type return 0; } -bool log_backend_net_set_addr(const char *addr) +static bool check_net_init_done(void) { bool ret = false; @@ -217,9 +217,18 @@ bool log_backend_net_set_addr(const char *addr) ctx->sock = -1; - if (!ret) { - return ret; - } + return ret; + } + + return true; +} + +bool log_backend_net_set_addr(const char *addr) +{ + bool ret = check_net_init_done(); + + if (!ret) { + return ret; } net_sin(&server_addr)->sin_port = htons(514); @@ -233,6 +242,27 @@ bool log_backend_net_set_addr(const char *addr) return ret; } +bool log_backend_net_set_ip(const struct sockaddr *addr) +{ + bool ret = check_net_init_done(); + + if (!ret) { + return ret; + } + + if ((IS_ENABLED(CONFIG_NET_IPV4) && addr->sa_family == AF_INET) || + (IS_ENABLED(CONFIG_NET_IPV6) && addr->sa_family == AF_INET6)) { + memcpy(&server_addr, addr, sizeof(server_addr)); + + net_port_set_default(&server_addr, 514); + } else { + LOG_ERR("Unknown address family"); + return false; + } + + return ret; +} + #if defined(CONFIG_NET_HOSTNAME_ENABLE) void log_backend_net_hostname_set(char *hostname, size_t len) { From 6e12b0210f3ad4c2c84050554859c1bfd3d85ca0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 22 Feb 2024 14:03:49 +0100 Subject: [PATCH 0366/2402] log: net: move log_backend_net_get() to header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This moves the declaration of log_backend_net_get() to zephyr/logging/log_backend_net.h Signed-off-by: Fin Maaß --- include/zephyr/logging/log_backend_net.h | 9 +++++++++ samples/net/syslog_net/src/main.c | 4 ---- subsys/logging/backends/log_backend_net.c | 2 -- subsys/net/lib/config/init.c | 2 +- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/include/zephyr/logging/log_backend_net.h b/include/zephyr/logging/log_backend_net.h index 8f3b0eb9ad7..d42a511a023 100644 --- a/include/zephyr/logging/log_backend_net.h +++ b/include/zephyr/logging/log_backend_net.h @@ -61,6 +61,15 @@ static inline void log_backend_net_hostname_set(const char *hostname, size_t len } #endif +/** + * @brief Get the net logger backend + * + * @details This function returns the net logger backend. + * + * @return Pointer to the net logger backend. + */ +const struct log_backend *log_backend_net_get(void); + #ifdef __cplusplus } #endif diff --git a/samples/net/syslog_net/src/main.c b/samples/net/syslog_net/src/main.c index b842e0ec03b..f0362648f05 100644 --- a/samples/net/syslog_net/src/main.c +++ b/samples/net/syslog_net/src/main.c @@ -19,10 +19,6 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_LOG_BACKEND_NET), "syslog backend not enabled"); #define SLEEP_BETWEEN_PRINTS 3 -#if defined(CONFIG_LOG_BACKEND_NET) -extern const struct log_backend *log_backend_net_get(void); -#endif - int main(void) { int i, count, sleep; diff --git a/subsys/logging/backends/log_backend_net.c b/subsys/logging/backends/log_backend_net.c index 92b2f3f719c..b9ffd315de3 100644 --- a/subsys/logging/backends/log_backend_net.c +++ b/subsys/logging/backends/log_backend_net.c @@ -42,8 +42,6 @@ static struct log_backend_net_ctx { .sock = -1, }; -const struct log_backend *log_backend_net_get(void); - static int line_out(uint8_t *data, size_t length, void *output_ctx) { struct log_backend_net_ctx *ctx = (struct log_backend_net_ctx *)output_ctx; diff --git a/subsys/net/lib/config/init.c b/subsys/net/lib/config/init.c index 2cc7236dfcc..734ca16998c 100644 --- a/subsys/net/lib/config/init.c +++ b/subsys/net/lib/config/init.c @@ -16,6 +16,7 @@ LOG_MODULE_REGISTER(net_config, CONFIG_NET_CONFIG_LOG_LEVEL); #include #include +#include #include #include #include @@ -30,7 +31,6 @@ LOG_MODULE_REGISTER(net_config, CONFIG_NET_CONFIG_LOG_LEVEL); #include "ieee802154_settings.h" #include "bt_settings.h" -extern const struct log_backend *log_backend_net_get(void); extern int net_init_clock_via_sntp(void); static K_SEM_DEFINE(waiter, 0, 1); From 2b23d1f3f1c03c004d71ff32739b9733a4cd8d59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 22 Feb 2024 17:53:18 +0100 Subject: [PATCH 0367/2402] log: net: Add log_backend_net_start function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds a function to start log_backend_net Signed-off-by: Fin Maaß --- include/zephyr/logging/log_backend_net.h | 7 +++++++ subsys/logging/backends/log_backend_net.c | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/include/zephyr/logging/log_backend_net.h b/include/zephyr/logging/log_backend_net.h index d42a511a023..9a1a3ac8875 100644 --- a/include/zephyr/logging/log_backend_net.h +++ b/include/zephyr/logging/log_backend_net.h @@ -70,6 +70,13 @@ static inline void log_backend_net_hostname_set(const char *hostname, size_t len */ const struct log_backend *log_backend_net_get(void); +/** + * @brief Start the net logger backend + * + * @details This function starts the net logger backend. + */ +void log_backend_net_start(void); + #ifdef __cplusplus } #endif diff --git a/subsys/logging/backends/log_backend_net.c b/subsys/logging/backends/log_backend_net.c index b9ffd315de3..7ec5844ce2e 100644 --- a/subsys/logging/backends/log_backend_net.c +++ b/subsys/logging/backends/log_backend_net.c @@ -269,6 +269,15 @@ void log_backend_net_hostname_set(char *hostname, size_t len) } #endif +void log_backend_net_start(void) +{ + const struct log_backend *backend = log_backend_net_get(); + + if (!log_backend_is_active(backend)) { + log_backend_activate(backend, backend->cb->ctx); + } +} + static void init_net(struct log_backend const *const backend) { ARG_UNUSED(backend); From 0d776d39bbdea4bceff3c849ca87fd33db25ac14 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 22 Feb 2024 10:08:53 +0100 Subject: [PATCH 0368/2402] net: dhcpv4: set log backend net ip via option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds the option to set the log_backend_net ip via dhcpv4 option 7. Signed-off-by: Fin Maaß --- subsys/logging/backends/Kconfig.net | 7 +++++ subsys/net/lib/dhcpv4/dhcpv4.c | 40 +++++++++++++++++++++++++ subsys/net/lib/dhcpv4/dhcpv4_internal.h | 1 + 3 files changed, 48 insertions(+) diff --git a/subsys/logging/backends/Kconfig.net b/subsys/logging/backends/Kconfig.net index 36a5096235b..91de9074324 100644 --- a/subsys/logging/backends/Kconfig.net +++ b/subsys/logging/backends/Kconfig.net @@ -49,6 +49,13 @@ config LOG_BACKEND_NET_AUTOSTART started by the application later on. Otherwise the logging thread might block. +config LOG_BACKEND_NET_USE_DHCPV4_OPTION + bool "Use DHCPv4 Log Server Option to configure syslog server" + depends on NET_DHCPV4 + help + When enabled the syslog server IP address is read from the DHCPv4 + Log Server Option (7). + backend = NET backend-str = net source "subsys/logging/Kconfig.template.log_format_config" diff --git a/subsys/net/lib/dhcpv4/dhcpv4.c b/subsys/net/lib/dhcpv4/dhcpv4.c index 0cf133e6d74..25f84b04e57 100644 --- a/subsys/net/lib/dhcpv4/dhcpv4.c +++ b/subsys/net/lib/dhcpv4/dhcpv4.c @@ -28,6 +28,10 @@ LOG_MODULE_REGISTER(net_dhcpv4, CONFIG_NET_DHCPV4_LOG_LEVEL); #include #include +#include +#include +#include + #include "dhcpv4_internal.h" #include "ipv4.h" #include "net_stats.h" @@ -56,6 +60,9 @@ static sys_slist_t option_vendor_callbacks = SYS_SLIST_STATIC_INIT(&option_vendo static const uint8_t min_req_options[] = { DHCPV4_OPTIONS_SUBNET_MASK, DHCPV4_OPTIONS_ROUTER, +#ifdef CONFIG_LOG_BACKEND_NET_USE_DHCPV4_OPTION + DHCPV4_OPTIONS_LOG_SERVER, +#endif #ifdef CONFIG_NET_DHCPV4_OPTION_NTP_SERVER DHCPV4_OPTIONS_NTP_SERVER, #endif @@ -969,6 +976,39 @@ static bool dhcpv4_parse_options(struct net_pkt *pkt, break; } #endif +#if defined(CONFIG_LOG_BACKEND_NET_USE_DHCPV4_OPTION) + case DHCPV4_OPTIONS_LOG_SERVER: { + struct sockaddr_in log_server = { 0 }; + + /* Log server option may present 1 or more + * addresses. Each 4 bytes in length. Log + * servers should be listed in order + * of preference. Hence we choose the first + * and skip the rest. + */ + if (length % 4 != 0U) { + NET_ERR("options_log_server, bad length"); + return false; + } + + if (net_pkt_read(pkt, log_server.sin_addr.s4_addr, 4) < 0 || + net_pkt_skip(pkt, length - 4U) < 0) { + NET_ERR("options_log_server, short packet"); + return false; + } + + log_server.sin_family = AF_INET; + log_backend_net_set_ip((struct sockaddr *)&log_server); + +#ifdef CONFIG_LOG_BACKEND_NET_AUTOSTART + log_backend_net_start(); +#endif + + NET_DBG("options_log_server: %s", net_sprint_ipv4_addr(&log_server)); + + break; + } +#endif /* CONFIG_LOG_BACKEND_NET_USE_DHCPV4_OPTION */ #if defined(CONFIG_NET_DHCPV4_OPTION_NTP_SERVER) case DHCPV4_OPTIONS_NTP_SERVER: { diff --git a/subsys/net/lib/dhcpv4/dhcpv4_internal.h b/subsys/net/lib/dhcpv4/dhcpv4_internal.h index 69b31ed7c07..77b4087bd0e 100644 --- a/subsys/net/lib/dhcpv4/dhcpv4_internal.h +++ b/subsys/net/lib/dhcpv4/dhcpv4_internal.h @@ -54,6 +54,7 @@ struct dhcp_msg { #define DHCPV4_OPTIONS_SUBNET_MASK 1 #define DHCPV4_OPTIONS_ROUTER 3 #define DHCPV4_OPTIONS_DNS_SERVER 6 +#define DHCPV4_OPTIONS_LOG_SERVER 7 #define DHCPV4_OPTIONS_HOST_NAME 12 #define DHCPV4_OPTIONS_NTP_SERVER 42 #define DHCPV4_OPTIONS_VENDOR_SPECIFIC 43 From a5c2781c045ad09538ab4970d0e6e35080e34da9 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Wed, 6 Mar 2024 15:25:19 +0100 Subject: [PATCH 0369/2402] drivers: Bluetooth: HCI: Reduce logging of No available ISO buffers In the case that there are no more ISO buffers left, "No available ISO buffers" is logged. However, given the nature of ISO where we are (very) likely to get additional ISO very soon after (typically every 7.5 or 10ms for audio), this will get logged a lot, and the logging may in some cases actually prevent the application from handling and freeing existng buffers due to the immense logging, which may make this (minor) issue into a blocking issue. This is fixed by reducing the logging to the first occurence, and then only every 100 afterwards, which has shown to reduce the risk of this effectively blocking the application. Signed-off-by: Emil Gydesen --- drivers/bluetooth/hci/ipc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/bluetooth/hci/ipc.c b/drivers/bluetooth/hci/ipc.c index 4aad992978e..aa5e67b0029 100644 --- a/drivers/bluetooth/hci/ipc.c +++ b/drivers/bluetooth/hci/ipc.c @@ -159,6 +159,7 @@ static struct net_buf *bt_ipc_acl_recv(const uint8_t *data, size_t remaining) static struct net_buf *bt_ipc_iso_recv(const uint8_t *data, size_t remaining) { struct bt_hci_iso_hdr hdr; + static size_t fail_cnt; struct net_buf *buf; size_t buf_tailroom; @@ -174,8 +175,15 @@ static struct net_buf *bt_ipc_iso_recv(const uint8_t *data, size_t remaining) remaining -= sizeof(hdr); net_buf_add_mem(buf, &hdr, sizeof(hdr)); + + fail_cnt = 0U; } else { - LOG_ERR("No available ISO buffers!"); + if ((fail_cnt % 100U) == 0U) { + LOG_ERR("No available ISO buffers (%zu)!", fail_cnt); + } + + fail_cnt++; + return NULL; } From cb26820c519bc8b6e4224f4d450ea908bca879b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 6 Mar 2024 15:18:00 +0100 Subject: [PATCH 0370/2402] hwmv2: scripts: handle Kconfig sources in a Windows compatible way MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move away from os.join.path and only rely on pathlib magic, and serialize all paths using POSIX path separators. This fixes documentation build and compliance check script on Windows. Signed-off-by: Benjamin Cabé --- doc/_extensions/zephyr/kconfig/__init__.py | 8 ++++---- scripts/ci/check_compliance.py | 20 ++++++++++++-------- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/doc/_extensions/zephyr/kconfig/__init__.py b/doc/_extensions/zephyr/kconfig/__init__.py index c268ac474f9..bafa36a55b1 100644 --- a/doc/_extensions/zephyr/kconfig/__init__.py +++ b/doc/_extensions/zephyr/kconfig/__init__.py @@ -97,18 +97,18 @@ def kconfig_load(app: Sphinx) -> Tuple[kconfiglib.Kconfig, Dict[str, str]]: with open(Path(td) / "soc" / "Kconfig.soc", "w") as f: for folder in soc_folders: - f.write('source "' + os.path.join(folder, 'Kconfig.soc') + '"\n') + f.write('source "' + (Path(folder) / 'Kconfig.soc').as_posix() + '"\n') with open(Path(td) / "soc" / "Kconfig", "w") as f: for folder in soc_folders: - f.write('osource "' + os.path.join(folder, 'Kconfig') + '"\n') + f.write('osource "' + (Path(folder) / 'Kconfig').as_posix() + '"\n') (Path(td) / 'arch').mkdir(exist_ok=True) root_args = argparse.Namespace(**{'arch_roots': [Path(ZEPHYR_BASE)], 'arch': None}) v2_archs = list_hardware.find_v2_archs(root_args) kconfig = "" for arch in v2_archs['archs']: - kconfig += 'source "' + str(Path(arch['path']) / 'Kconfig') + '"\n' + kconfig += 'source "' + (Path(arch['path']) / 'Kconfig').as_posix() + '"\n' with open(Path(td) / "arch" / "Kconfig", "w") as f: f.write(kconfig) @@ -126,7 +126,7 @@ def kconfig_load(app: Sphinx) -> Tuple[kconfiglib.Kconfig, Dict[str, str]]: board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", identifier).upper() f.write('config ' + board_str + '\n') f.write('\t bool\n') - f.write('source "' + os.path.join(board.dir, 'Kconfig.') + board.name + '"\n\n') + f.write('source "' + (board.dir / ('Kconfig.' + board.name)).as_posix() + '"\n\n') # base environment os.environ["ZEPHYR_BASE"] = str(ZEPHYR_BASE) diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index 88ab9b32b91..90f1dc3b947 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -441,7 +441,7 @@ def get_v2_model(self, kconfig_dir): with open(kconfig_defconfig_file, 'w') as fp: for board in v2_boards: - fp.write('osource "' + os.path.join(board.dir, 'Kconfig.defconfig') + '"\n') + fp.write('osource "' + (Path(board.dir) / 'Kconfig.defconfig').as_posix() + '"\n') with open(kconfig_boards_file, 'w') as fp: for board in v2_boards: @@ -452,12 +452,16 @@ def get_v2_model(self, kconfig_dir): board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", identifier).upper() fp.write('config ' + board_str + '\n') fp.write('\t bool\n') - fp.write('source "' + os.path.join(board.dir, 'Kconfig.') + board.name + '"\n\n') + fp.write( + 'source "' + (Path(board.dir) / ('Kconfig.' + board.name)).as_posix() + '"\n\n' + ) with open(kconfig_file, 'w') as fp: - fp.write('osource "' + os.path.join(kconfig_dir, 'boards', 'Kconfig.syms.v1') + '"\n') + fp.write( + 'osource "' + (Path(kconfig_dir) / 'boards' / 'Kconfig.syms.v1').as_posix() + '"\n' + ) for board in v2_boards: - fp.write('osource "' + os.path.join(board.dir, 'Kconfig') + '"\n') + fp.write('osource "' + (Path(board.dir) / 'Kconfig').as_posix() + '"\n') kconfig_defconfig_file = os.path.join(kconfig_dir, 'soc', 'Kconfig.defconfig') kconfig_soc_file = os.path.join(kconfig_dir, 'soc', 'Kconfig.soc') @@ -469,15 +473,15 @@ def get_v2_model(self, kconfig_dir): soc_folders = {soc.folder for soc in v2_systems.get_socs()} with open(kconfig_defconfig_file, 'w') as fp: for folder in soc_folders: - fp.write('osource "' + os.path.join(folder, 'Kconfig.defconfig') + '"\n') + fp.write('osource "' + (Path(folder) / 'Kconfig.defconfig').as_posix() + '"\n') with open(kconfig_soc_file, 'w') as fp: for folder in soc_folders: - fp.write('source "' + os.path.join(folder, 'Kconfig.soc') + '"\n') + fp.write('source "' + (Path(folder) / 'Kconfig.soc').as_posix() + '"\n') with open(kconfig_file, 'w') as fp: for folder in soc_folders: - fp.write('source "' + os.path.join(folder, 'Kconfig') + '"\n') + fp.write('source "' + (Path(folder) / 'Kconfig').as_posix() + '"\n') kconfig_file = os.path.join(kconfig_dir, 'arch', 'Kconfig') @@ -486,7 +490,7 @@ def get_v2_model(self, kconfig_dir): with open(kconfig_file, 'w') as fp: for arch in v2_archs['archs']: - fp.write('source "' + os.path.join(arch['path'], 'Kconfig') + '"\n') + fp.write('source "' + (Path(arch['path']) / 'Kconfig').as_posix() + '"\n') def parse_kconfig(self, filename="Kconfig", hwm=None): """ From c9c98d07e769062b189ef957aa55bac73b606c1b Mon Sep 17 00:00:00 2001 From: Elias Speinle Date: Wed, 6 Mar 2024 15:18:26 +0100 Subject: [PATCH 0371/2402] drivers: eth: esp32: support setting mac address during runtime Add support for setting the mac address of the esp32 during runtime. Signed-off-by: Elias Speinle --- drivers/ethernet/eth_esp32.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/ethernet/eth_esp32.c b/drivers/ethernet/eth_esp32.c index 6cf6ba44813..687b24c1e6d 100644 --- a/drivers/ethernet/eth_esp32.c +++ b/drivers/ethernet/eth_esp32.c @@ -57,6 +57,29 @@ static enum ethernet_hw_caps eth_esp32_caps(const struct device *dev) return ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T; } +static int eth_esp32_set_config(const struct device *dev, + enum ethernet_config_type type, + const struct ethernet_config *config) +{ + struct eth_esp32_dev_data *const dev_data = dev->data; + int ret = -ENOTSUP; + + switch (type) { + case ETHERNET_CONFIG_TYPE_MAC_ADDRESS: + memcpy(dev_data->mac_addr, config->mac_address.addr, 6); + emac_hal_set_address(&dev_data->hal, dev_data->mac_addr); + net_if_set_link_addr(dev_data->iface, dev_data->mac_addr, + sizeof(dev_data->mac_addr), + NET_LINK_ETHERNET); + ret = 0; + break; + default: + break; + } + + return ret; +} + static int eth_esp32_send(const struct device *dev, struct net_pkt *pkt) { struct eth_esp32_dev_data *dev_data = dev->data; @@ -318,6 +341,7 @@ static void eth_esp32_iface_init(struct net_if *iface) static const struct ethernet_api eth_esp32_api = { .iface_api.init = eth_esp32_iface_init, .get_capabilities = eth_esp32_caps, + .set_config = eth_esp32_set_config, .send = eth_esp32_send, }; From a653d59b657e43b7efc497b30ad674c45a8ddeab Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Mon, 5 Feb 2024 09:47:32 +0100 Subject: [PATCH 0372/2402] drivers: ethernet: adin2111: fix imask1 tx_ready_mask Fix IAMSK1 TX_READY_MASK bitfield position. Signed-off-by: Angelo Dureghello --- drivers/ethernet/eth_adin2111_priv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ethernet/eth_adin2111_priv.h b/drivers/ethernet/eth_adin2111_priv.h index 843ad3db665..af244c1228d 100644 --- a/drivers/ethernet/eth_adin2111_priv.h +++ b/drivers/ethernet/eth_adin2111_priv.h @@ -92,7 +92,7 @@ /*!< Mask Bit for P1_RX_RDY. Generic SPI only.*/ #define ADIN2111_IMASK1_P1_RX_RDY_MASK BIT(4) /*!< Mask Bit for TX_FRM_DONE. Generic SPI only.*/ -#define ADIN2111_IMASK1_TX_RDY_MASK BIT(4) +#define ADIN2111_IMASK1_TX_RDY_MASK BIT(3) /* MAC Tx Frame Size Register */ #define ADIN2111_TX_FSIZE 0x30U From 5784a3a78ff654f88076e32f52dec28b631b00dc Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Mon, 5 Feb 2024 09:52:39 +0100 Subject: [PATCH 0373/2402] drivers: ethernet: adin2111: always append crc32 to the eth frame Enable appending of a crc32 at the end of the frame by the MAC, always. This is always needed since the driver is not adding it. This field has nothing to do with Generic SPI protocol-related 8-bit CRC, so this patch removes the CONFIG_ETH_ADIN2111_SPI_CFG0 choice related to this setting. Testing without this flag set, packets are not forwareded in the network, since the driver is not appending any crc32 header to the frame. Signed-off-by: Angelo Dureghello --- drivers/ethernet/eth_adin2111.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index 5fd0e987362..21f2820aef9 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -882,11 +882,7 @@ static int adin2111_init(const struct device *dev) return ret; } -#if CONFIG_ETH_ADIN2111_SPI_CFG0 val |= ADIN2111_CONFIG2_CRC_APPEND; -#else - val &= ~ADIN2111_CONFIG2_CRC_APPEND; -#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */ /* configure forwarding of frames with unknown destination address */ /* to the other port. This forwarding is done in hardware. */ From 27f2cfb797b513038b404dce3ffbceb649bfaef0 Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Thu, 8 Feb 2024 12:30:05 +0100 Subject: [PATCH 0374/2402] drivers: ethernet: adin2111: fix generic spi withotut crc8 mode After some debugging related to non-working "Generic SPI without CRC" mode in eval_adin2111_ebz (CONFIG_ETH_ADIN2111_SPI_CFG0=n), noticed that even after proper STATUS0 RESETC bit detection, registers, for a certain period (some msecs) still reads as zero. This patch fixes adin2111_await_device and with it the "Generic SPI without CRC" mode. Signed-off-by: Angelo Dureghello --- drivers/ethernet/eth_adin2111.c | 10 +++++++--- drivers/ethernet/eth_adin2111_priv.h | 3 +++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index 21f2820aef9..7c256356623 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -758,10 +758,14 @@ static int adin2111_await_device(const struct device *dev) /* await reset complete (RESETC) and clear it */ for (count = 0U; count < ADIN2111_RESETC_AWAIT_RETRY_COUNT; ++count) { - ret = eth_adin2111_reg_read(dev, ADIN2111_STATUS0, &val); + ret = eth_adin2111_reg_read(dev, ADIN2111_PHYID, &val); if (ret >= 0) { - /* if out of reset */ - if (val & ADIN2111_STATUS0_RESETC) { + /* + * Even after getting RESETC, for some milliseconds registers are + * still not properly readable (they reads 0), + * so checking OUI read-only value instead. + */ + if ((val >> 10) == ADIN2111_PHYID_OUI) { /* clear RESETC */ ret = eth_adin2111_reg_write(dev, ADIN2111_STATUS0, ADIN2111_STATUS0_RESETC); diff --git a/drivers/ethernet/eth_adin2111_priv.h b/drivers/ethernet/eth_adin2111_priv.h index af244c1228d..81346cd4287 100644 --- a/drivers/ethernet/eth_adin2111_priv.h +++ b/drivers/ethernet/eth_adin2111_priv.h @@ -158,6 +158,9 @@ /* Number of buffer bytes in TxFIFO to provide frame margin upon writes */ #define ADIN2111_TX_FIFO_BUFFER_MARGIN 4U +/* Manufacturer unique ID */ +#define ADIN2111_PHYID_OUI 0xa0ef + enum adin2111_chips_id { ADIN2111_MAC = 0, ADIN1110_MAC, From 06c8460a9e7df1a557efee4590a5ec403b6305d2 Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Thu, 8 Feb 2024 12:57:06 +0100 Subject: [PATCH 0375/2402] drivers: ethernet: adin2111: remove unused header_len variable Non functional change, removing unused variable producing compilation warning in "Generic SPI without CRC8" mode. Signed-off-by: Angelo Dureghello --- drivers/ethernet/eth_adin2111.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index 7c256356623..6fb80d72cdc 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -155,7 +155,6 @@ static int adin2111_read_fifo(const struct device *dev, const uint8_t port) struct adin2111_data *ctx = dev->data; struct net_if *iface; struct net_pkt *pkt; - size_t header_len = ADIN2111_READ_HEADER_SIZE; uint16_t fsize_reg = ((port == 0U) ? ADIN2111_P1_RX_FSIZE : ADIN2111_P2_RX_FSIZE); uint16_t rx_reg = ((port == 0U) ? ADIN2111_P1_RX : ADIN2111_P2_RX); uint32_t fsize; @@ -189,7 +188,6 @@ static int adin2111_read_fifo(const struct device *dev, const uint8_t port) cmd_buf[2] = crc8_ccitt(0, cmd_buf, ADIN2111_SPI_HEADER_SIZE); /* TA */ cmd_buf[3] = 0U; - ++header_len; #else /* TA */ cmd_buf[2] = 0U; From 0ca8b0756b1539c0010935fd76e991f0e905916c Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Wed, 7 Feb 2024 15:20:02 +0100 Subject: [PATCH 0376/2402] drivers: ethernet: adin2111: add Open Alliance SPI support Add Open Alliance spi protocol support. Open Alliance is a chunk-based SPI protocol, based on sending over SPI an ethernet frame divided in smaller chunks, using a specific 32-bit header for each chunk transferred. All chunks can be sent or received by a single dma transfer. Default mode is set to Open Alliance SPI without protection, since the adin2111 dev. board comes shipped this way. Tested: - Open Alliance SPI, no protection (default board shipped) - Open Alliance SPI, protection - Generic SPI, no crc - Generic SPI, with crc8 Signed-off-by: Angelo Dureghello --- boards/adi/eval_adin1110ebz/Kconfig.defconfig | 6 +- .../eval_adin1110ebz/adi_eval_adin1110ebz.dts | 8 + boards/adi/eval_adin2111ebz/Kconfig.defconfig | 8 +- .../eval_adin2111ebz/adi_eval_adin2111ebz.dts | 7 + drivers/ethernet/eth_adin2111.c | 445 ++++++++++++++++-- drivers/ethernet/eth_adin2111_priv.h | 47 ++ dts/bindings/ethernet/adi,adin2111.yaml | 6 + 7 files changed, 485 insertions(+), 42 deletions(-) diff --git a/boards/adi/eval_adin1110ebz/Kconfig.defconfig b/boards/adi/eval_adin1110ebz/Kconfig.defconfig index 9c33c1d288d..0bc99b612de 100644 --- a/boards/adi/eval_adin1110ebz/Kconfig.defconfig +++ b/boards/adi/eval_adin1110ebz/Kconfig.defconfig @@ -5,9 +5,11 @@ if BOARD_ADI_EVAL_ADIN1110EBZ -config SPI_STM32_INTERRUPT +config BOARD + default "adi_eval_adin1110ebz" + +config SPI_STM32_DMA default y - depends on SPI config MDIO_INIT_PRIORITY default 81 diff --git a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts index 71f0ecd46cb..5aa554d3748 100644 --- a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts +++ b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts @@ -197,6 +197,11 @@ pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>; pinctrl-names = "default"; cs-gpios = <&gpiob 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + dmas = <&dmamux1 2 13 (STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC | + STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>, + <&dmamux1 3 12 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC | + STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>; + dma-names = "tx", "rx"; status = "okay"; adin1110: adin1110@0 { @@ -205,6 +210,9 @@ spi-max-frequency = <25000000>; int-gpios = <&gpiob 11 GPIO_ACTIVE_LOW>; reset-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; + status = "okay"; + spi-oa; + spi-oa-protection; port1 { local-mac-address = [ 00 E0 22 FE DA C8 ]; diff --git a/boards/adi/eval_adin2111ebz/Kconfig.defconfig b/boards/adi/eval_adin2111ebz/Kconfig.defconfig index ae255907083..f7d8be766d5 100644 --- a/boards/adi/eval_adin2111ebz/Kconfig.defconfig +++ b/boards/adi/eval_adin2111ebz/Kconfig.defconfig @@ -5,9 +5,8 @@ if BOARD_ADI_EVAL_ADIN2111EBZ -config SPI_STM32_INTERRUPT - default y - depends on SPI +config BOARD + default "adi_eval_adin2111ebz" config MDIO_INIT_PRIORITY default 81 @@ -17,6 +16,9 @@ config PHY_INIT_PRIORITY default 82 depends on NET_L2_ETHERNET && ETH_DRIVER +config SPI_STM32_DMA + default y + if NETWORKING config NET_L2_ETHERNET diff --git a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts index 5602afab008..5db24f04e80 100644 --- a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts +++ b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts @@ -162,6 +162,11 @@ pinctrl-names = "default"; cs-gpios = <&gpiob 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; status = "okay"; + dmas = <&dmamux1 2 13 (STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC | + STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>, + <&dmamux1 3 12 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC | + STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>; + dma-names = "tx", "rx"; adin2111: adin2111@0 { compatible = "adi,adin2111"; @@ -169,6 +174,8 @@ spi-max-frequency = <25000000>; int-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; status = "okay"; + spi-oa; + spi-oa-protection; port1 { local-mac-address = [ 00 E0 22 FE DA C9 ]; diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index 6fb80d72cdc..3048659d4cf 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -25,6 +25,8 @@ LOG_MODULE_REGISTER(eth_adin2111, CONFIG_ETHERNET_LOG_LEVEL); #include "phy/phy_adin2111_priv.h" #include "eth_adin2111_priv.h" +#define DT_DRV_COMPAT adi_adin2111 + /* SPI Communication check retry delay */ #define ADIN2111_DEV_AWAIT_DELAY_POLL_US 100U /* Number of retries SPI Communication check */ @@ -46,6 +48,10 @@ LOG_MODULE_REGISTER(eth_adin2111, CONFIG_ETHERNET_LOG_LEVEL); #define ADIN2111_UNICAST_P1_ADDR_SLOT 2U /* MAC Address Rule and DA Filter Port 2 slot/idx */ #define ADIN2111_UNICAST_P2_ADDR_SLOT 3U +/* As per RM rev. A table 3, t3 >= 50ms, delay for SPI interface to be ready */ +#define ADIN2111_SPI_ACTIVE_DELAY_MS 50U +/* As per RM rev. A page 20: approximately 10 ms (maximum) for internal logic to be ready */ +#define ADIN2111_SW_RESET_DELAY_MS 10U int eth_adin2111_lock(const struct device *dev, k_timeout_t timeout) { @@ -61,43 +67,288 @@ int eth_adin2111_unlock(const struct device *dev) return k_mutex_unlock(&ctx->lock); } -int eth_adin2111_reg_write(const struct device *dev, const uint16_t reg, - const uint32_t val) +static inline bool eth_adin2111_oa_get_parity(const uint32_t x) +{ + uint32_t y; + + y = x ^ (x >> 1); + y = y ^ (y >> 2); + y = y ^ (y >> 4); + y = y ^ (y >> 8); + y = y ^ (y >> 16); + + return !(y & 1); +} + +int eth_adin2111_oa_spi_xfer(const struct device *dev, uint8_t *buf_rx, uint8_t *buf_tx, int len) { const struct adin2111_config *cfg = dev->config; - size_t header_size = ADIN2111_WRITE_HEADER_SIZE; - size_t data_size = sizeof(uint32_t); -#if CONFIG_ETH_ADIN2111_SPI_CFG0 - uint8_t buf[ADIN2111_REG_WRITE_BUF_SIZE_CRC] = { 0 }; -#else - uint8_t buf[ADIN2111_REG_WRITE_BUF_SIZE] = { 0 }; -#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */ - /* spi header */ - *(uint16_t *)buf = htons((ADIN2111_WRITE_TXN_CTRL | reg)); -#if CONFIG_ETH_ADIN2111_SPI_CFG0 - buf[2] = crc8_ccitt(0, buf, header_size); - ++header_size; -#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */ + struct spi_buf tx_buf[1]; + struct spi_buf rx_buf[1]; + struct spi_buf_set tx; + struct spi_buf_set rx; + int ret; - /* reg */ - *(uint32_t *)(buf + header_size) = htonl(val); -#if CONFIG_ETH_ADIN2111_SPI_CFG0 - buf[header_size + data_size] = crc8_ccitt(0, &buf[header_size], data_size); - ++data_size; -#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */ + tx_buf[0].buf = buf_tx; + tx_buf[0].len = len; + rx_buf[0].buf = buf_rx; + rx_buf[0].len = len; - const struct spi_buf spi_tx_buf = { - .buf = buf, - .len = header_size + data_size - }; - const struct spi_buf_set tx = { .buffers = &spi_tx_buf, .count = 1U }; + rx.buffers = rx_buf; + rx.count = 1; + tx.buffers = tx_buf; + tx.count = 1; - return spi_write_dt(&cfg->spi, &tx); + ret = spi_transceive_dt(&cfg->spi, &tx, &rx); + if (ret < 0) { + LOG_ERR("ERRR dma!\n"); + return ret; + } + + return 0; } -int eth_adin2111_reg_read(const struct device *dev, const uint16_t reg, - uint32_t *val) +static int eth_adin2111_reg_read_oa(const struct device *dev, const uint16_t reg, + uint32_t *val) +{ + struct adin2111_data *ctx = dev->data; + uint32_t pval; + uint32_t *hdr = (uint32_t *)ctx->oa_tx_buf; + int len; + int ret; + + *hdr = reg << 8; + if (reg >= 0x30) { + *hdr |= ADIN2111_OA_CTL_MMS; + } + + *hdr |= eth_adin2111_oa_get_parity(*hdr); + *hdr = sys_cpu_to_be32(*hdr); + + len = (ctx->oa_prot) ? ADIN2111_OA_CTL_LEN_PROT : ADIN2111_OA_CTL_LEN; + + ret = eth_adin2111_oa_spi_xfer(dev, ctx->oa_rx_buf, ctx->oa_tx_buf, len); + if (ret < 0) { + return ret; + } + + *val = sys_be32_to_cpu(*(uint32_t *)&ctx->oa_rx_buf[8]); + + /* In protected mode read data is followed by its compliment value */ + if (ctx->oa_prot) { + pval = sys_be32_to_cpu(*(uint32_t *)&ctx->oa_rx_buf[12]); + if (*val != ~pval) { + LOG_ERR("OA protected mode rx error !"); + return -1; + } + } + + return 0; +} + +static int eth_adin2111_reg_write_oa(const struct device *dev, const uint16_t reg, + uint32_t val) +{ + struct adin2111_data *ctx = dev->data; + uint32_t pval; + uint32_t *hdr = (uint32_t *)ctx->oa_tx_buf; + int len; + int ret; + + *hdr = reg << 8 | ADIN2111_OA_CTL_WNR; + if (reg >= 0x30) { + *hdr |= ADIN2111_OA_CTL_MMS; + } + + *hdr |= eth_adin2111_oa_get_parity(*hdr); + *hdr = sys_cpu_to_be32(*hdr); + + len = (ctx->oa_prot) ? ADIN2111_OA_CTL_LEN_PROT : ADIN2111_OA_CTL_LEN; + + *(uint32_t *)&ctx->oa_tx_buf[4] = sys_cpu_to_be32(val); + if (ctx->oa_prot) { + *(uint32_t *)&ctx->oa_tx_buf[8] = sys_cpu_to_be32(~val); + } + + ret = eth_adin2111_oa_spi_xfer(dev, ctx->oa_rx_buf, ctx->oa_tx_buf, len); + if (ret < 0) { + return ret; + } + + if (ctx->oa_prot) { + pval = sys_be32_to_cpu(*(uint32_t *)&ctx->oa_rx_buf[12]); + if (val != ~pval) { + LOG_ERR("OA protected mode tx error !"); + return -1; + } + } + + return 0; +} + +int eth_adin2111_oa_data_read(const struct device *dev, int port) +{ + struct adin2111_data *ctx = dev->data; + struct net_if *iface = ((struct adin2111_port_data *)ctx->port[port]->data)->iface; + struct net_pkt *pkt; + uint32_t hdr, ftr; + int i, len, rx_pos, ret, rca, swo; + + ret = eth_adin2111_reg_read(dev, ADIN2111_BUFSTS, &rca); + if (ret < 0) { + LOG_ERR("can't read BUFSTS"); + return -EIO; + } + + rca &= ADIN2111_BUFSTS_RCA_MASK; + + /* Preare all tx headers */ + for (i = 0, len = 0; i < rca; ++i) { + hdr = ADIN2111_OA_DATA_HDR_DNC; + hdr |= eth_adin2111_oa_get_parity(hdr); + + *(uint32_t *)&ctx->oa_tx_buf[len] = sys_cpu_to_be32(hdr); + + len += sizeof(uint32_t) + ctx->oa_cps; + } + + ret = eth_adin2111_oa_spi_xfer(dev, ctx->oa_rx_buf, ctx->oa_tx_buf, len); + if (ret < 0) { + LOG_ERR("SPI xfer failed"); + return ret; + } + + for (i = 0, rx_pos = 0; i < rca; ++i) { + + ftr = sys_be32_to_cpu(*(uint32_t *)&ctx->oa_rx_buf[rx_pos + ctx->oa_cps]); + + if (eth_adin2111_oa_get_parity(ftr)) { + LOG_ERR("OA RX: Footer parity error !"); + return -EIO; + } + if (!(ftr & ADIN2111_OA_DATA_FTR_SYNC)) { + LOG_ERR("OA RX: Configuration not in sync !"); + return -EIO; + } + if (!(ftr & ADIN2111_OA_DATA_FTR_DV)) { + LOG_DBG("OA RX: Data chunk not valid, skip !"); + goto update_pos; + } + if (ftr & ADIN2111_OA_DATA_FTR_SV) { + swo = (ftr & ADIN2111_OA_DATA_FTR_SWO_MSK) >> ADIN2111_OA_DATA_FTR_SWO; + if (swo != 0) { + LOG_ERR("OA RX: Misalignbed start of frame !"); + return -EIO; + } + /* Reset store cursor */ + ctx->scur = 0; + } + + len = (ftr & ADIN2111_OA_DATA_FTR_EV) ? + ((ftr & ADIN2111_OA_DATA_FTR_EBO_MSK) >> ADIN2111_OA_DATA_FTR_EBO) + 1 : + ctx->oa_cps; + memcpy(&ctx->buf[ctx->scur], &ctx->oa_rx_buf[rx_pos], len); + ctx->scur += len; + + if (ftr & ADIN2111_OA_DATA_FTR_EV) { + pkt = net_pkt_rx_alloc_with_buffer(iface, CONFIG_ETH_ADIN2111_BUFFER_SIZE, + AF_UNSPEC, 0, + K_MSEC(CONFIG_ETH_ADIN2111_TIMEOUT)); + if (!pkt) { + LOG_ERR("OA RX: cannot allcate packet space, skipping."); + return -EIO; + } + /* Skipping CRC32 */ + ret = net_pkt_write(pkt, ctx->buf, ctx->scur - sizeof(uint32_t)); + if (ret < 0) { + net_pkt_unref(pkt); + LOG_ERR("Failed to write pkt, scur %d, err %d", ctx->scur, ret); + return ret; + } + ret = net_recv_data(iface, pkt); + if (ret < 0) { + net_pkt_unref(pkt); + LOG_ERR("Port %u failed to enqueue frame to RX queue, %d", + port, ret); + return ret; + } + } +update_pos: + rx_pos += ctx->oa_cps + sizeof(uint32_t); + } + + return ret; +} + +/* + * Setting up for a single dma transfer. + */ +static int eth_adin2111_send_oa_frame(const struct device *dev, struct net_pkt *pkt, int port) +{ + struct adin2111_data *ctx = dev->data; + uint16_t clen, len = net_pkt_get_len(pkt); + uint32_t hdr; + uint8_t chunks, i; + int ret, txc, cur; + + chunks = len / ctx->oa_cps; + + if (len % ctx->oa_cps) { + chunks++; + } + + ret = eth_adin2111_reg_read(dev, ADIN2111_BUFSTS, &txc); + if (ret < 0) { + LOG_ERR("Cannot read txc"); + return -EIO; + } + + txc = (txc & ADIN2111_BUFSTS_TXC_MASK) >> ADIN2111_BUFSTS_TXC; + if (txc < chunks) { + return -EIO; + } + + /* Prepare for single dma transfer */ + for (i = 1, cur = 0; i <= chunks; i++) { + hdr = ADIN2111_OA_DATA_HDR_DNC | ADIN2111_OA_DATA_HDR_DV | + ADIN2111_OA_DATA_HDR_NORX; + hdr |= (!!port << ADIN2111_OA_DATA_HDR_VS); + if (i == 1) { + hdr |= ADIN2111_OA_DATA_HDR_SV; + } + if (i == chunks) { + hdr |= ADIN2111_OA_DATA_HDR_EV; + hdr |= (ctx->oa_cps - 1) << ADIN2111_OA_DATA_HDR_EBO; + } + + hdr |= eth_adin2111_oa_get_parity(hdr); + + *(uint32_t *)&ctx->oa_tx_buf[cur] = sys_cpu_to_be32(hdr); + cur += sizeof(uint32_t); + + clen = len > ctx->oa_cps ? ctx->oa_cps : len; + ret = net_pkt_read(pkt, &ctx->oa_tx_buf[cur], clen); + if (ret < 0) { + LOG_ERR("Cannot read from tx packet"); + return ret; + } + cur += ctx->oa_cps; + len -= clen; + } + + ret = eth_adin2111_oa_spi_xfer(dev, ctx->oa_rx_buf, ctx->oa_tx_buf, cur); + if (ret < 0) { + LOG_ERR("Error on SPI xfer"); + return ret; + } + + return 0; +} + +static int eth_adin2111_reg_read_generic(const struct device *dev, + const uint16_t reg, + uint32_t *val) { const struct adin2111_config *cfg = dev->config; size_t header_len = ADIN2111_READ_HEADER_SIZE; @@ -149,6 +400,72 @@ int eth_adin2111_reg_read(const struct device *dev, const uint16_t reg, return ret; } +static int eth_adin2111_reg_write_generic(const struct device *dev, + const uint16_t reg, + const uint32_t val) +{ + const struct adin2111_config *cfg = dev->config; + size_t header_size = ADIN2111_WRITE_HEADER_SIZE; + size_t data_size = sizeof(uint32_t); +#if CONFIG_ETH_ADIN2111_SPI_CFG0 + uint8_t buf[ADIN2111_REG_WRITE_BUF_SIZE_CRC] = { 0 }; +#else + uint8_t buf[ADIN2111_REG_WRITE_BUF_SIZE] = { 0 }; +#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */ + + /* spi header */ + *(uint16_t *)buf = htons((ADIN2111_WRITE_TXN_CTRL | reg)); + #if CONFIG_ETH_ADIN2111_SPI_CFG0 + buf[2] = crc8_ccitt(0, buf, header_size); + ++header_size; +#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */ + + /* reg */ + *(uint32_t *)(buf + header_size) = htonl(val); +#if CONFIG_ETH_ADIN2111_SPI_CFG0 + buf[header_size + data_size] = crc8_ccitt(0, &buf[header_size], data_size); + ++data_size; +#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */ + + const struct spi_buf spi_tx_buf = { + .buf = buf, + .len = header_size + data_size + }; + const struct spi_buf_set tx = { .buffers = &spi_tx_buf, .count = 1U }; + + return spi_write_dt(&cfg->spi, &tx); +} + +int eth_adin2111_reg_read(const struct device *dev, const uint16_t reg, + uint32_t *val) +{ + struct adin2111_data *ctx = dev->data; + int rval; + + if (ctx->oa) { + rval = eth_adin2111_reg_read_oa(dev, reg, val); + } else { + rval = eth_adin2111_reg_read_generic(dev, reg, val); + } + + return rval; +} + +int eth_adin2111_reg_write(const struct device *dev, const uint16_t reg, + const uint32_t val) +{ + struct adin2111_data *ctx = dev->data; + int rval; + + if (ctx->oa) { + rval = eth_adin2111_reg_write_oa(dev, reg, val); + } else { + rval = eth_adin2111_reg_write_generic(dev, reg, val); + } + + return rval; +} + static int adin2111_read_fifo(const struct device *dev, const uint8_t port) { const struct adin2111_config *cfg = dev->config; @@ -302,11 +619,13 @@ static void adin2111_offload_thread(void *p1, void *p2, void *p3) goto continue_unlock; } + if (!ctx->oa) { #if CONFIG_ETH_ADIN2111_SPI_CFG0 - if (status0 & ADIN2111_STATUS1_SPI_ERR) { - LOG_WRN("Detected TX SPI CRC error"); + if (status0 & ADIN2111_STATUS1_SPI_ERR) { + LOG_WRN("Detected TX SPI CRC error"); + } +#endif } -#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */ /* handle port 1 phy interrupts */ if (status0 & ADIN2111_STATUS0_PHYINT) { @@ -318,6 +637,22 @@ static void adin2111_offload_thread(void *p1, void *p2, void *p3) adin2111_port_on_phyint(ctx->port[1]); } + if (ctx->oa) { + if (status1 & ADIN2111_STATUS1_P1_RX_RDY) { + ret = eth_adin2111_oa_data_read(dev, 0); + if (ret < 0) { + break; + } + } + if (status1 & ADIN2111_STATUS1_P2_RX_RDY) { + ret = eth_adin2111_oa_data_read(dev, 1); + if (ret < 0) { + break; + } + } + goto continue_unlock; + } + /* handle port 1 rx */ if (status1 & ADIN2111_STATUS1_P1_RX_RDY) { do { @@ -368,7 +703,7 @@ static void adin2111_offload_thread(void *p1, void *p2, void *p3) LOG_ERR("Failed to write IMASK1, %d", ret); } eth_adin2111_unlock(dev); - }; + } } static void adin2111_int_callback(const struct device *dev, @@ -416,6 +751,31 @@ static int adin2111_port_send(const struct device *dev, struct net_pkt *pkt) eth_adin2111_lock(adin, K_FOREVER); + if (ctx->oa) { + uint32_t val, rca = 0; + /* + * By high-traffic zperf test, noted that ADIN2111 does not like we send + * if there is something to be received. It stops to issue rx interrupts + * and zperf transfer hangs. Forcing a receive for this case. + */ + ret = eth_adin2111_reg_read(adin, ADIN2111_BUFSTS, &val); + if (ret < 0) { + return ret; + } + rca = val & ADIN2111_BUFSTS_RCA_MASK; + + if (rca > 0) { + eth_adin2111_unlock(adin); + k_sem_give(&ctx->offload_sem); + k_yield(); + eth_adin2111_lock(adin, K_FOREVER); + } + + ret = eth_adin2111_send_oa_frame(cfg->adin, pkt, htons(cfg->port_idx)); + + goto end_check; + } + /* query remaining tx fifo space */ ret = adin2111_read_tx_space(adin, &tx_space); if (ret < 0) { @@ -497,6 +857,7 @@ static int adin2111_port_send(const struct device *dev, struct net_pkt *pkt) ret = spi_write_dt(&((const struct adin2111_config *) adin->config)->spi, &tx); +end_check: if (ret < 0) { eth_stats_update_errors_tx(data->iface); LOG_ERR("Port %u frame SPI write failed, %d", cfg->port_idx, ret); @@ -670,7 +1031,7 @@ static void adin2111_port_iface_init(struct net_if *iface) /* all ifaces are done, start INT processing */ k_thread_create(&ctx->rx_thread, ctx->rx_thread_stack, - CONFIG_ETH_ADIN2111_IRQ_THREAD_STACK_SIZE, + K_KERNEL_STACK_SIZEOF(ctx->rx_thread_stack), adin2111_offload_thread, (void *)adin, NULL, NULL, CONFIG_ETH_ADIN2111_IRQ_THREAD_PRIO, @@ -839,6 +1200,8 @@ static int adin2111_init(const struct device *dev) return ret; } + k_msleep(ADIN2111_SPI_ACTIVE_DELAY_MS); + ret = adin2111_check_spi(dev); if (ret < 0) { LOG_ERR("Failed to communicate over SPI, %d", ret); @@ -852,6 +1215,8 @@ static int adin2111_init(const struct device *dev) return ret; } + k_msleep(ADIN2111_SW_RESET_DELAY_MS); + ret = adin2111_await_device(dev); if (ret < 0) { LOG_ERR("ADIN did't come out of the reset, %d", ret); @@ -871,6 +1236,10 @@ static int adin2111_init(const struct device *dev) val &= ~ADIN2111_CONFIG0_RXCTE; val &= ~(ADIN2111_CONFIG0_TXCTE | ADIN2111_CONFIG0_TXFCSVE); + if (ctx->oa) { + val |= ADIN2111_CONFIG0_ZARFE; + } + ret = eth_adin2111_reg_write(dev, ADIN2111_CONFIG0, val); if (ret < 0) { LOG_ERR("Failed to write CONFIG0, %d", ret); @@ -966,12 +1335,11 @@ static const struct ethernet_api adin2111_port_api = { NET_L2_GET_CTX_TYPE(ETHERNET_L2), NET_ETH_MTU); #define ADIN2111_SPI_OPERATION ((uint16_t)(SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8))) - #define ADIN2111_MAC_INITIALIZE(inst, dev_id, ifaces, name) \ static uint8_t __aligned(4) name##_buffer_##inst[CONFIG_ETH_ADIN2111_BUFFER_SIZE]; \ static const struct adin2111_config name##_config_##inst = { \ - .id = dev_id, \ - .spi = SPI_DT_SPEC_INST_GET(inst, ADIN2111_SPI_OPERATION, 1), \ + .id = dev_id, \ + .spi = SPI_DT_SPEC_INST_GET(inst, ADIN2111_SPI_OPERATION, 0), \ .interrupt = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \ .reset = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, { 0 }), \ }; \ @@ -981,6 +1349,9 @@ static const struct ethernet_api adin2111_port_api = { .offload_sem = Z_SEM_INITIALIZER(name##_data_##inst.offload_sem, 0, 1), \ .lock = Z_MUTEX_INITIALIZER(name##_data_##inst.lock), \ .buf = name##_buffer_##inst, \ + .oa = DT_INST_PROP(inst, spi_oa), \ + .oa_prot = DT_INST_PROP(inst, spi_oa_protection), \ + .oa_cps = 64, \ }; \ /* adin */ \ DEVICE_DT_DEFINE(DT_DRV_INST(inst), adin2111_init, NULL, \ diff --git a/drivers/ethernet/eth_adin2111_priv.h b/drivers/ethernet/eth_adin2111_priv.h index 81346cd4287..dd042cab756 100644 --- a/drivers/ethernet/eth_adin2111_priv.h +++ b/drivers/ethernet/eth_adin2111_priv.h @@ -33,6 +33,10 @@ #define ADIN2111_CONFIG0_SYNC BIT(15) /* Transmit Frame Check Sequence Validation Enable */ #define ADIN2111_CONFIG0_TXFCSVE BIT(14) +/* Zero Align Receive Frame Enable */ +#define ADIN2111_CONFIG0_ZARFE BIT(12) +/* New packet received only after a new CS assertion */ +#define ADIN2111_CONFIG0_CSARFE BIT(13) /* Transmit Cut Through Enable */ #define ADIN2111_CONFIG0_TXCTE BIT(9) /* Receive Cut Through Enable. Must be 0 for Generic SPI */ @@ -72,9 +76,18 @@ #define ADIN2111_STATUS1_SPI_ERR BIT(10) /* Port 1 RX FIFO Contains Data */ #define ADIN2111_STATUS1_P1_RX_RDY BIT(4) +/* Frame transmitted */ +#define ADIN2111_STATUS1_TX_RDY BIT(3) /* Value to completely clear status register 1 */ #define ADIN2111_STATUS1_CLEAR 0xFFF01F08U +/* Buffer Status Register */ +#define ADIN2111_BUFSTS 0x0BU +/* Rx chunks available */ +#define ADIN2111_BUFSTS_RCA_MASK GENMASK(7, 0) +/* Tx credits */ +#define ADIN2111_BUFSTS_TXC 8U +#define ADIN2111_BUFSTS_TXC_MASK GENMASK(15, 8) /* Interrupt Mask Register 0 */ #define ADIN2111_IMASK0 0x0CU @@ -161,6 +174,34 @@ /* Manufacturer unique ID */ #define ADIN2111_PHYID_OUI 0xa0ef +/* Open Alliance definitions */ +#define ADIN2111_OA_ALLOC_TIMEOUT K_MSEC(10) +/* Max setting to a max RCA of 255 68-bytes ckunks */ +#define ADIN2111_OA_BUF_SZ (255U * 64U) + +#define ADIN2111_OA_CTL_LEN_PROT 16U +#define ADIN2111_OA_CTL_LEN 12U +#define ADIN2111_OA_CTL_MMS BIT(24) +#define ADIN2111_OA_CTL_WNR BIT(29) + +#define ADIN2111_OA_DATA_HDR_DNC BIT(31) +#define ADIN2111_OA_DATA_HDR_NORX BIT(29) +#define ADIN2111_OA_DATA_HDR_VS 22U +#define ADIN2111_OA_DATA_HDR_DV BIT(21) +#define ADIN2111_OA_DATA_HDR_SV BIT(20) +#define ADIN2111_OA_DATA_HDR_EV BIT(14) +#define ADIN2111_OA_DATA_HDR_EBO 8U + +#define ADIN2111_OA_DATA_FTR_SYNC BIT(29) +#define ADIN2111_OA_DATA_FTR_EBO 8U +#define ADIN2111_OA_DATA_FTR_DV BIT(21) +#define ADIN2111_OA_DATA_FTR_SV BIT(20) +#define ADIN2111_OA_DATA_FTR_EV BIT(14) +#define ADIN2111_OA_DATA_FTR_SWO 16U +#define ADIN2111_OA_DATA_FTR_SWO_MSK GENMASK(19, 16) +#define ADIN2111_OA_DATA_FTR_EBO 8U +#define ADIN2111_OA_DATA_FTR_EBO_MSK GENMASK(13, 8) + enum adin2111_chips_id { ADIN2111_MAC = 0, ADIN1110_MAC, @@ -183,6 +224,12 @@ struct adin2111_data { uint32_t imask1; uint16_t ifaces_left_to_init; uint8_t *buf; + uint16_t scur; + bool oa; + bool oa_prot; + uint8_t oa_cps; + uint8_t oa_tx_buf[ADIN2111_OA_BUF_SZ]; + uint8_t oa_rx_buf[ADIN2111_OA_BUF_SZ]; K_KERNEL_STACK_MEMBER(rx_thread_stack, CONFIG_ETH_ADIN2111_IRQ_THREAD_STACK_SIZE); struct k_thread rx_thread; diff --git a/dts/bindings/ethernet/adi,adin2111.yaml b/dts/bindings/ethernet/adi,adin2111.yaml index f1b5c1b53c1..3f9d505d4d7 100644 --- a/dts/bindings/ethernet/adi,adin2111.yaml +++ b/dts/bindings/ethernet/adi,adin2111.yaml @@ -53,6 +53,12 @@ properties: reset-gpios: type: phandle-array description: The reset pin of ADIN2111. + spi-oa: + type: boolean + description: Enables Open Alliance SPI protocol. + spi-oa-protection: + type: boolean + description: Enables Open Alliance SPI protocol protection. child-binding: description: Port properties From 06df4b5ae956f38e0175da721e8fc8f9ceb70db9 Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Tue, 5 Mar 2024 08:44:27 +0100 Subject: [PATCH 0377/2402] drivers: ethernet: adin2111: fix real rx frame size Fix issue related to "generic SPI" mode only, when a packet of 1512 bytes is received, net_pkt_write() fails and thrwos the error: "Still some length to go 2". This is due to net_pkt_rx_alloc_with_buffer() allocating a maximum mtu/size of 1514, and driver is not removing 4 bytes of crc32 from rx buffer, that comes to be 1516 (2 bytes over buffer limit). Fix generic SPI rx frame size removing crc32 bytes. Signed-off-by: Angelo Dureghello --- drivers/ethernet/eth_adin2111.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index 3048659d4cf..74c533bf867 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -496,8 +496,8 @@ static int adin2111_read_fifo(const struct device *dev, const uint8_t port) /* burst read must be in multiples of 4 */ padding_len = ((fsize % 4) == 0) ? 0U : (ROUND_UP(fsize, 4U) - fsize); - /* actual frame length is FSIZE - FRAME HEADER */ - fsize_real = fsize - ADIN2111_FRAME_HEADER_SIZE; + /* actual frame length is FSIZE - FRAME HEADER - CRC32 */ + fsize_real = fsize - (ADIN2111_FRAME_HEADER_SIZE + sizeof(uint32_t)); /* spi header */ *(uint16_t *)cmd_buf = htons((ADIN2111_READ_TXN_CTRL | rx_reg)); From 7b9349405cbda88541235e31d946ac598caa9644 Mon Sep 17 00:00:00 2001 From: Dino Li Date: Thu, 22 Feb 2024 11:50:08 +0800 Subject: [PATCH 0378/2402] ite/it8xxx2: add support for jtag debug interface If enabled, jtag pins will be configured as debug interface at chip startup. Signed-off-by: Dino Li --- soc/ite/ec/common/chip_chipregs.h | 14 ++++++++++++++ soc/ite/ec/common/vector.S | 25 +++++++++++++++++++++++++ soc/ite/ec/it8xxx2/Kconfig | 11 +++++++++++ 3 files changed, 50 insertions(+) diff --git a/soc/ite/ec/common/chip_chipregs.h b/soc/ite/ec/common/chip_chipregs.h index 05f7876ffee..9814e01d512 100644 --- a/soc/ite/ec/common/chip_chipregs.h +++ b/soc/ite/ec/common/chip_chipregs.h @@ -48,11 +48,25 @@ /* --- General Control (GCTRL) --- */ #define IT8XXX2_GCTRL_BASE 0x00F02000 #define IT8XXX2_GCTRL_EIDSR ECREG(IT8XXX2_GCTRL_BASE + 0x31) +#define IT8XXX2_GCTRL_PMER3 ECREG(IT8XXX2_GCTRL_BASE + 0x46) +/* RISC-V JTAG Debug Interface Enable */ +#define IT8XXX2_GCTRL_JTAGEN BIT(1) +/* RISC-V JTAG Debug Interface Selection */ +#define IT8XXX2_GCTRL_JTAGSEL BIT(0) +#define IT8XXX2_GCTRL_JTAG (IT8XXX2_GCTRL_JTAGEN | IT8XXX2_GCTRL_JTAGSEL) /* --- External GPIO Control (EGPIO) --- */ #define IT8XXX2_EGPIO_BASE 0x00F02100 #define IT8XXX2_EGPIO_EGCR ECREG(IT8XXX2_EGPIO_BASE + 0x04) +#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2 +#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01660) +#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF01648) +#elif CONFIG_SOC_IT8XXX2_REG_SET_V1 +#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01610) +#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF016e9) +#endif + /* EGPIO register fields */ /* * 0x04: External GPIO Control diff --git a/soc/ite/ec/common/vector.S b/soc/ite/ec/common/vector.S index 21d97981a2e..2ce64d0f5b9 100644 --- a/soc/ite/ec/common/vector.S +++ b/soc/ite/ec/common/vector.S @@ -26,6 +26,31 @@ SECTION_FUNC(vectors, __start) .option norvc; +#ifdef CONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE + /* Enable JTAG debug interface */ + la t0, IT8XXX2_GCTRL_PMER3 + lb t1, 0(t0) + ori t1, t1, IT8XXX2_GCTRL_JTAG + sb t1, 0(t0) + + la t0, IT8XXX2_JTAG_PINS_BASE + li t1, 0 + /* Configure GPIOA0 as TCK function */ + sb t1, 0(t0) + /* Configure GPIOA1 as TDI function */ + sb t1, 1(t0) + /* Configure GPIOA4 as TDO function */ + sb t1, 4(t0) + /* Configure GPIOA5 as TMS function */ + sb t1, 5(t0) + /* Configure GPIOA6 as TRST function */ + sb t1, 6(t0) + + /* I/O voltage is 3.3V */ + la t0, IT8XXX2_JTAG_VOLT_SET + sb t1, 0(t0) +#endif + /* * Set mtvec (Machine Trap-Vector Base-Address Register) * to _isr_wrapper. diff --git a/soc/ite/ec/it8xxx2/Kconfig b/soc/ite/ec/it8xxx2/Kconfig index 0c65a11c27a..7ba9d832534 100644 --- a/soc/ite/ec/it8xxx2/Kconfig +++ b/soc/ite/ec/it8xxx2/Kconfig @@ -99,6 +99,17 @@ config SOC_IT8XXX2_EC_BUS_24MHZ The clock_frequency of ite,it8xxx2-i2c node (i2c0, i2c1, and i2c2) will be fixed at 400KHz. +config SOC_IT8XXX2_JTAG_DEBUG_INTERFACE + bool "JTAG debug interface" + help + If enabled, the below five pins are configured as JTAG debug interface: + - GPIOA0 -> TCK + - GPIOA1 -> TDI + - GPIOA4 -> TDO + - GPIOA5 -> TMS + - GPIOA6 -> TRST + Supported I/O voltage is 3.3V. + choice prompt "Clock source for PLL reference clock" From 223e81b96888e8231a7c9a8a10bc7af3b3154098 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 6 Mar 2024 07:18:38 -0800 Subject: [PATCH 0379/2402] soc: intel_adsp/ace: use CONFIG_XTENSA_MORE_SPIN_RELAX_NOPS This enables the use of CONFIG_XTENSA_MORE_SPIN_RELAX_NOPS to specify how many NOPs for arch_spin_relax(). This is to keep the atomic_cas() (via s32c1i) from saturating the internal bus with contant RCW ops. The numbers should be further tuned for specific application but these should provide a good start. Signed-off-by: Daniel Leung --- soc/intel/intel_adsp/ace/Kconfig.defconfig.series | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.series b/soc/intel/intel_adsp/ace/Kconfig.defconfig.series index 85d64c3bd0c..b9a548d77c1 100644 --- a/soc/intel/intel_adsp/ace/Kconfig.defconfig.series +++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.series @@ -60,6 +60,20 @@ config LOG_BACKEND_ADSP endif # LOG +config XTENSA_MORE_SPIN_RELAX_NOPS + default y if SMP && MP_MAX_NUM_CPUS > 1 + +if XTENSA_MORE_SPIN_RELAX_NOPS + +config XTENSA_NUM_SPIN_RELAX_NOPS + default 32 if MP_MAX_NUM_CPUS = 1 + default 64 if MP_MAX_NUM_CPUS = 2 + default 96 if MP_MAX_NUM_CPUS = 3 + default 128 if MP_MAX_NUM_CPUS = 4 + default 160 if MP_MAX_NUM_CPUS = 5 + +endif # XTENSA_MORE_SPIN_RELAX_NOPS + rsource "Kconfig.defconfig.ace*" endif # SOC_SERIES_INTEL_ADSP_ACE From 7072e75162452bf8a7a5cf04a4e1552b7371ec35 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 6 Mar 2024 18:14:21 +0200 Subject: [PATCH 0380/2402] net: dhcpv4: Network interface netmask was set too early When we receive the subnet mask option from the server, we cannot yet set the netmask to the network interface as the mask is tied to the IP address we received from the server. We need to delay the setting of netmask until we have added the requested IP address to the interface. Signed-off-by: Jukka Rissanen --- include/zephyr/net/net_if.h | 3 +++ subsys/net/lib/dhcpv4/dhcpv4.c | 9 ++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/zephyr/net/net_if.h b/include/zephyr/net/net_if.h index fabd2cc5f89..bab22da1c05 100644 --- a/include/zephyr/net/net_if.h +++ b/include/zephyr/net/net_if.h @@ -425,6 +425,9 @@ struct net_if_dhcpv4 { /** Requested IP addr */ struct in_addr requested_ip; + /** Received netmask from the server */ + struct in_addr netmask; + /** * DHCPv4 client state in the process of network * address allocation. diff --git a/subsys/net/lib/dhcpv4/dhcpv4.c b/subsys/net/lib/dhcpv4/dhcpv4.c index 25f84b04e57..b278d95401f 100644 --- a/subsys/net/lib/dhcpv4/dhcpv4.c +++ b/subsys/net/lib/dhcpv4/dhcpv4.c @@ -902,9 +902,8 @@ static bool dhcpv4_parse_options(struct net_pkt *pkt, return false; } - net_if_ipv4_set_netmask_by_addr(iface, - &iface->config.dhcpv4.requested_ip, - &netmask); + iface->config.dhcpv4.netmask = netmask; + NET_DBG("options_subnet_mask %s", net_sprint_ipv4_addr(&netmask)); break; @@ -1206,6 +1205,10 @@ static void dhcpv4_handle_msg_ack(struct net_if *iface) return; } + net_if_ipv4_set_netmask_by_addr(iface, + &iface->config.dhcpv4.requested_ip, + &iface->config.dhcpv4.netmask); + dhcpv4_enter_bound(iface); break; From c31d6461982e3c1234c8af0bc1e58cdae3a25ac0 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 6 Mar 2024 11:12:42 -0500 Subject: [PATCH 0381/2402] kernel: timeout: optimize z_timeout_expires() This currently calls timeout_rem() then adds back the result of elapsed() to cancel out the subtraction of another elapsed() call within timeout_rem(). Better not to make any calls to elapsed() in that case, especially given that elapsed() may incur hardware access overhead through sys_clock_elapsed(). Let's move the elapsed() subtraction to the only user of timeout_rem() that needs it and remove its invocation from the z_timeout_expires() path entirely. Signed-off-by: Nicolas Pitre --- kernel/timeout.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/kernel/timeout.c b/kernel/timeout.c index 29f15898035..b667abafe99 100644 --- a/kernel/timeout.c +++ b/kernel/timeout.c @@ -160,10 +160,6 @@ static k_ticks_t timeout_rem(const struct _timeout *timeout) { k_ticks_t ticks = 0; - if (z_is_inactive_timeout(timeout)) { - return 0; - } - for (struct _timeout *t = first(); t != NULL; t = next(t)) { ticks += t->dticks; if (timeout == t) { @@ -171,7 +167,7 @@ static k_ticks_t timeout_rem(const struct _timeout *timeout) } } - return ticks - elapsed(); + return ticks; } k_ticks_t z_timeout_remaining(const struct _timeout *timeout) @@ -179,7 +175,9 @@ k_ticks_t z_timeout_remaining(const struct _timeout *timeout) k_ticks_t ticks = 0; K_SPINLOCK(&timeout_lock) { - ticks = timeout_rem(timeout); + if (!z_is_inactive_timeout(timeout)) { + ticks = timeout_rem(timeout) - elapsed(); + } } return ticks; @@ -190,7 +188,10 @@ k_ticks_t z_timeout_expires(const struct _timeout *timeout) k_ticks_t ticks = 0; K_SPINLOCK(&timeout_lock) { - ticks = curr_tick + timeout_rem(timeout) + elapsed(); + ticks = curr_tick; + if (!z_is_inactive_timeout(timeout)) { + ticks += timeout_rem(timeout); + } } return ticks; From 3b7b232a597eec4544d6ca4fc10bef3f618dbd3b Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Fri, 8 Mar 2024 06:59:37 -0500 Subject: [PATCH 0382/2402] MAINTAINERS: associate lorawan tests with area associate tests to lorwan. Signed-off-by: Anas Nashif --- MAINTAINERS.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index f55b852581f..0350b41269a 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2372,6 +2372,7 @@ LoRa and LoRaWAN: - "area: LoRa" tests: - sample.driver.lora + - lorawan MAINTAINERS file: status: maintained From ad7086a2dfe68c858b70d2266113a8f21f6b6551 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 8 Mar 2024 13:00:54 +0100 Subject: [PATCH 0383/2402] drivers counter nrfx RTC: Fix ISR prototype The ISR prototype is not matching the signature for interrupt handlers, which results in build warnings. Let's fix it. Signed-off-by: Alberto Escolar Piedras --- drivers/counter/counter_nrfx_rtc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/counter/counter_nrfx_rtc.c b/drivers/counter/counter_nrfx_rtc.c index 398921f2bd6..d6888988b8c 100644 --- a/drivers/counter/counter_nrfx_rtc.c +++ b/drivers/counter/counter_nrfx_rtc.c @@ -645,8 +645,10 @@ static void alarm_irq_handle(const struct device *dev, uint32_t chan) } } -static void irq_handler(const struct device *dev) +static void irq_handler(const void *arg) { + const struct device *dev = arg; + top_irq_handle(dev); for (uint32_t i = 0; i < counter_get_num_of_channels(dev); i++) { From 0650a88bed4d8ae51b3a54654c2b900119a2e510 Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Fri, 1 Mar 2024 10:17:27 -0600 Subject: [PATCH 0384/2402] llext: Rework hello_world test case to be "simple" The simple test is there to test the API and simple extensions in unison. Hello world was intended to be the first not the only extension being tested. Also refactors the entry thread to allow for usermode potentially by passing the pointer to the function symbol rather than having it look it up directly. Signed-off-by: Tom Burdick --- cmake/compiler/gcc/target_arm.cmake | 2 - subsys/logging/log_minimal.c | 2 + tests/subsys/llext/hello_world/CMakeLists.txt | 28 --- .../hello_world/src/test/test_llext_simple.c | 88 ---------- tests/subsys/llext/simple/CMakeLists.txt | 28 +++ .../llext/{hello_world => simple}/Kconfig | 0 .../llext/{hello_world => simple}/prj.conf | 4 +- .../src/hello_world_ext.c} | 9 +- tests/subsys/llext/simple/src/logging_ext.c | 26 +++ .../llext/simple/src/test_llext_simple.c | 162 ++++++++++++++++++ .../{hello_world => simple}/testcase.yaml | 1 + 11 files changed, 225 insertions(+), 125 deletions(-) delete mode 100644 tests/subsys/llext/hello_world/CMakeLists.txt delete mode 100644 tests/subsys/llext/hello_world/src/test/test_llext_simple.c create mode 100644 tests/subsys/llext/simple/CMakeLists.txt rename tests/subsys/llext/{hello_world => simple}/Kconfig (100%) rename tests/subsys/llext/{hello_world => simple}/prj.conf (56%) rename tests/subsys/llext/{hello_world/src/llext/hello_world.c => simple/src/hello_world_ext.c} (78%) create mode 100644 tests/subsys/llext/simple/src/logging_ext.c create mode 100644 tests/subsys/llext/simple/src/test_llext_simple.c rename tests/subsys/llext/{hello_world => simple}/testcase.yaml (97%) diff --git a/cmake/compiler/gcc/target_arm.cmake b/cmake/compiler/gcc/target_arm.cmake index 6659c7bf417..77a718cc725 100644 --- a/cmake/compiler/gcc/target_arm.cmake +++ b/cmake/compiler/gcc/target_arm.cmake @@ -51,12 +51,10 @@ set(LLEXT_REMOVE_FLAGS -fdata-sections -g.* -Os - -mcpu=.* ) # Flags to be added to llext code compilation set(LLEXT_APPEND_FLAGS -mlong-calls -mthumb - -mcpu=cortex-m33+nodsp ) diff --git a/subsys/logging/log_minimal.c b/subsys/logging/log_minimal.c index ebfa4ff5d7e..11a27f701bb 100644 --- a/subsys/logging/log_minimal.c +++ b/subsys/logging/log_minimal.c @@ -8,6 +8,7 @@ #include #include #include +#include #define HEXDUMP_BYTES_IN_LINE 8U @@ -19,6 +20,7 @@ void z_log_minimal_printk(const char *fmt, ...) vprintk(fmt, ap); va_end(ap); } +EXPORT_SYMBOL(z_log_minimal_printk); void z_log_minimal_vprintk(const char *fmt, va_list ap) { diff --git a/tests/subsys/llext/hello_world/CMakeLists.txt b/tests/subsys/llext/hello_world/CMakeLists.txt deleted file mode 100644 index 2f107bd5346..00000000000 --- a/tests/subsys/llext/hello_world/CMakeLists.txt +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2023 Intel Corporation. -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(llext_hello_world_test) - -target_sources(app PRIVATE - src/test/test_llext_simple.c -) - -target_include_directories(app PRIVATE - ${ZEPHYR_BASE}/include - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include -) - -# Compile a simple hello world llext to an include file -set(llext_src_file ${PROJECT_SOURCE_DIR}/src/llext/hello_world.c) -set(llext_bin_file ${ZEPHYR_BINARY_DIR}/hello_world.llext) -set(llext_inc_file ${ZEPHYR_BINARY_DIR}/include/generated/hello_world.inc) - -add_llext_target(hello_world - OUTPUT ${llext_bin_file} - SOURCES ${llext_src_file} -) - -generate_inc_file_for_target(app ${llext_bin_file} ${llext_inc_file}) diff --git a/tests/subsys/llext/hello_world/src/test/test_llext_simple.c b/tests/subsys/llext/hello_world/src/test/test_llext_simple.c deleted file mode 100644 index ee68e72d73a..00000000000 --- a/tests/subsys/llext/hello_world/src/test/test_llext_simple.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2023 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#if defined(CONFIG_ARM) /* ARMV7 */ || defined(CONFIG_XTENSA) -#ifndef CONFIG_LLEXT_STORAGE_WRITABLE -const -#endif -static uint8_t hello_world_elf[] __aligned(4) = { -#include "hello_world.inc" -}; -#endif - -K_THREAD_STACK_DEFINE(llext_stack, 1024); -struct k_thread llext_thread; - -#ifdef CONFIG_USERSPACE -void llext_entry(void *arg0, void *arg1, void *arg2) -{ - struct llext *ext = arg0; - - zassert_ok(llext_call_fn(ext, "hello_world"), - "hello_world call should succeed"); -} -#endif /* CONFIG_USERSPACE */ - -/** - * Attempt to load, list, list symbols, call a fn, and unload a - * hello world extension for each supported architecture - * - * This requires a single linked symbol (printk) and a single - * exported symbol from the extension ( void hello_world(void)) - */ -ZTEST(llext, test_llext_simple) -{ - const char name[16] = "hello"; - struct llext_buf_loader buf_loader = - LLEXT_BUF_LOADER(hello_world_elf, ARRAY_SIZE(hello_world_elf)); - struct llext_loader *loader = &buf_loader.loader; - struct llext_load_param ldr_parm = LLEXT_LOAD_PARAM_DEFAULT; - struct llext *ext = NULL; - const void * const printk_fn = llext_find_sym(NULL, "printk"); - - zassert_equal(printk_fn, printk, "printk should be an exported symbol"); - - int res = llext_load(loader, name, &ext, &ldr_parm); - - zassert_ok(res, "load should succeed"); - - const void * const hello_world_fn = llext_find_sym(&ext->exp_tab, "hello_world"); - - zassert_not_null(hello_world_fn, "hello_world should be an exported symbol"); - -#ifdef CONFIG_USERSPACE - struct k_mem_domain domain; - - k_mem_domain_init(&domain, 0, NULL); - - res = llext_add_domain(ext, &domain); - zassert_ok(res, "adding partitions to domain should succeed"); - - /* Should be runnable from newly created thread */ - k_thread_create(&llext_thread, llext_stack, - K_THREAD_STACK_SIZEOF(llext_stack), - &llext_entry, ext, NULL, NULL, - 1, 0, K_FOREVER); - - k_mem_domain_add_thread(&domain, &llext_thread); - - k_thread_start(&llext_thread); - k_thread_join(&llext_thread, K_FOREVER); - -#else /* CONFIG_USERSPACE */ - zassert_ok(llext_call_fn(ext, "hello_world"), - "hello_world call should succeed"); -#endif /* CONFIG_USERSPACE */ - - llext_unload(&ext); -} - -ZTEST_SUITE(llext, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/subsys/llext/simple/CMakeLists.txt b/tests/subsys/llext/simple/CMakeLists.txt new file mode 100644 index 00000000000..03a781fb74d --- /dev/null +++ b/tests/subsys/llext/simple/CMakeLists.txt @@ -0,0 +1,28 @@ +# Copyright (c) 2023 Intel Corporation. +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(llext_simple_test) + +target_sources(app PRIVATE + src/test_llext_simple.c +) + +target_include_directories(app PRIVATE + ${ZEPHYR_BASE}/include + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include +) + +# generate extension targets foreach extension given by name +foreach(ext_name hello_world logging) + set(ext_src ${PROJECT_SOURCE_DIR}/src/${ext_name}_ext.c) + set(ext_bin ${ZEPHYR_BINARY_DIR}/${ext_name}.llext) + set(ext_inc ${ZEPHYR_BINARY_DIR}/include/generated/${ext_name}.inc) + add_llext_target(${ext_name}_ext + OUTPUT ${ext_bin} + SOURCES ${ext_src} + ) + generate_inc_file_for_target(app ${ext_bin} ${ext_inc}) +endforeach() diff --git a/tests/subsys/llext/hello_world/Kconfig b/tests/subsys/llext/simple/Kconfig similarity index 100% rename from tests/subsys/llext/hello_world/Kconfig rename to tests/subsys/llext/simple/Kconfig diff --git a/tests/subsys/llext/hello_world/prj.conf b/tests/subsys/llext/simple/prj.conf similarity index 56% rename from tests/subsys/llext/hello_world/prj.conf rename to tests/subsys/llext/simple/prj.conf index ad4d6c5a0b7..c7ce0544764 100644 --- a/tests/subsys/llext/hello_world/prj.conf +++ b/tests/subsys/llext/simple/prj.conf @@ -1,6 +1,6 @@ CONFIG_ZTEST=y -CONFIG_ZTEST_STACK_SIZE=8192 +CONFIG_ZTEST_STACK_SIZE=4096 CONFIG_LOG=y CONFIG_LLEXT=y -CONFIG_LLEXT_HEAP_SIZE=32 +CONFIG_LLEXT_HEAP_SIZE=16 CONFIG_LLEXT_LOG_LEVEL_DBG=y diff --git a/tests/subsys/llext/hello_world/src/llext/hello_world.c b/tests/subsys/llext/simple/src/hello_world_ext.c similarity index 78% rename from tests/subsys/llext/hello_world/src/llext/hello_world.c rename to tests/subsys/llext/simple/src/hello_world_ext.c index 7ed688d2461..f3cc2106a11 100644 --- a/tests/subsys/llext/hello_world/src/llext/hello_world.c +++ b/tests/subsys/llext/simple/src/hello_world_ext.c @@ -13,14 +13,13 @@ #include #include - -extern void printk(char *fmt, ...); +#include static const uint32_t number = 42; -void hello_world(void) +void test_entry(void) { printk("hello world\n"); - printk("A number is %lu\n", number); + printk("A number is %u\n", number); } -LL_EXTENSION_SYMBOL(hello_world); +LL_EXTENSION_SYMBOL(test_entry); diff --git a/tests/subsys/llext/simple/src/logging_ext.c b/tests/subsys/llext/simple/src/logging_ext.c new file mode 100644 index 00000000000..94298ce2f15 --- /dev/null +++ b/tests/subsys/llext/simple/src/logging_ext.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2023 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This very simple hello world C code can be used as a test case for building + * probably the simplest loadable extension. It requires a single symbol be + * linked, section relocation support, and the ability to export and call out to + * a function. + */ + +#include +#include +#include +LOG_MODULE_REGISTER(logging_ext); + +static const uint32_t number = 42; + +void test_entry(void) +{ + LOG_INF("hello world"); + LOG_INF("A number is %" PRIu32, number); +} +LL_EXTENSION_SYMBOL(test_entry); diff --git a/tests/subsys/llext/simple/src/test_llext_simple.c b/tests/subsys/llext/simple/src/test_llext_simple.c new file mode 100644 index 00000000000..d3d38a2a3ab --- /dev/null +++ b/tests/subsys/llext/simple/src/test_llext_simple.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2023 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(test_llext_simple); + + +#ifdef CONFIG_LLEXT_STORAGE_WRITABLE +#define LLEXT_CONST +#else +#define LLEXT_CONST const +#endif + +struct llext_test { + const char *name; + bool try_userspace; + size_t buf_len; + + LLEXT_CONST uint8_t *buf; +}; + + + +K_THREAD_STACK_DEFINE(llext_stack, 1024); +struct k_thread llext_thread; + +#ifdef CONFIG_USERSPACE +void llext_entry(void *arg0, void *arg1, void *arg2) +{ + void (*fn)(void) = arg0; + + LOG_INF("calling fn %p from thread %p", fn, k_current_get()); + fn(); +} +#endif /* CONFIG_USERSPACE */ + +void load_call_unload(struct llext_test *test_case) +{ + struct llext_buf_loader buf_loader = + LLEXT_BUF_LOADER(test_case->buf, test_case->buf_len); + struct llext_loader *loader = &buf_loader.loader; + struct llext_load_param ldr_parm = LLEXT_LOAD_PARAM_DEFAULT; + struct llext *ext = NULL; + + int res = llext_load(loader, test_case->name, &ext, &ldr_parm); + + zassert_ok(res, "load should succeed"); + + void (*test_entry_fn)() = llext_find_sym(&ext->exp_tab, "test_entry"); + + zassert_not_null(test_entry_fn, "test_entry should be an exported symbol"); + +#ifdef CONFIG_USERSPACE + /* + * Due to the number of MPU regions on some parts with MPU (USERSPACE) + * enabled we need to always call into the extension from a new dedicated + * thread to avoid running out of MPU regions on some parts. + * + * This is part dependent behavior and certainly on MMU capable parts + * this should not be needed! This test however is here to be generic + * across as many parts as possible. + */ + struct k_mem_domain domain; + + k_mem_domain_init(&domain, 0, NULL); + +#ifdef Z_LIBC_PARTITION_EXISTS + k_mem_domain_add_partition(&domain, &z_libc_partition); +#endif + + res = llext_add_domain(ext, &domain); + if (res == -ENOSPC) { + TC_PRINT("Too many memory partitions for this particular hardware\n"); + ztest_test_skip(); + return; + } + zassert_ok(res, "adding partitions to domain should succeed"); + + /* Should be runnable from newly created thread */ + k_thread_create(&llext_thread, llext_stack, + K_THREAD_STACK_SIZEOF(llext_stack), + &llext_entry, test_entry_fn, NULL, NULL, + 1, 0, K_FOREVER); + + k_mem_domain_add_thread(&domain, &llext_thread); + + k_thread_start(&llext_thread); + k_thread_join(&llext_thread, K_FOREVER); + + /* Some extensions may wish to be tried from the context + * of a userspace thread along with the usual supervisor context + * tried above. + */ + if (test_case->try_userspace) { + k_thread_create(&llext_thread, llext_stack, + K_THREAD_STACK_SIZEOF(llext_stack), + &llext_entry, test_entry_fn, NULL, NULL, + 1, K_USER, K_FOREVER); + + k_mem_domain_add_thread(&domain, &llext_thread); + + k_thread_start(&llext_thread); + k_thread_join(&llext_thread, K_FOREVER); + } + + +#else /* CONFIG_USERSPACE */ + zassert_ok(llext_call_fn(ext, "test_entry"), + "test_entry call should succeed"); +#endif /* CONFIG_USERSPACE */ + + llext_unload(&ext); +} +/* + * Attempt to load, list, list symbols, call a fn, and unload each + * extension in the test table. This excercises loading, calling into, and + * unloading each extension which may itself excercise various APIs provided by + * Zephyr. + */ +#define LLEXT_LOAD_UNLOAD(_name, _userspace) \ + ZTEST(llext, test_load_unload_##_name) \ + { \ + struct llext_test test_case = { \ + .name = STRINGIFY(_name), \ + .try_userspace = _userspace, \ + .buf_len = ARRAY_SIZE(_name ## _ext), \ + .buf = _name ## _ext, \ + }; \ + load_call_unload(&test_case); \ + } +static LLEXT_CONST uint8_t hello_world_ext[] __aligned(4) = { + #include "hello_world.inc" +}; +LLEXT_LOAD_UNLOAD(hello_world, false) + +static LLEXT_CONST uint8_t logging_ext[] __aligned(4) = { + #include "logging.inc" +}; +LLEXT_LOAD_UNLOAD(logging, true) + +/* + * Ensure that EXPORT_SYMBOL does indeed provide a symbol and a valid address + * to it. + */ +ZTEST(llext, test_printk_exported) +{ + const void * const printk_fn = llext_find_sym(NULL, "printk"); + + zassert_equal(printk_fn, printk, "printk should be an exported symbol"); +} + + +ZTEST_SUITE(llext, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/subsys/llext/hello_world/testcase.yaml b/tests/subsys/llext/simple/testcase.yaml similarity index 97% rename from tests/subsys/llext/hello_world/testcase.yaml rename to tests/subsys/llext/simple/testcase.yaml index d270e568798..1a10f980af2 100644 --- a/tests/subsys/llext/hello_world/testcase.yaml +++ b/tests/subsys/llext/simple/testcase.yaml @@ -5,6 +5,7 @@ common: - xtensa platform_exclude: - numaker_pfm_m487 # See #63167 + - qemu_cortex_r5 # unsupported relocations tests: llext.simple.readonly: arch_exclude: xtensa # for now From 913ca370c74cdd53bdb052936f40d9dc6a383b66 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Wed, 6 Mar 2024 15:44:39 +0100 Subject: [PATCH 0385/2402] Bluetooth: BAP: Add input validation for bt_bap_ep_get_info The function did not have a NULL check for the parameters, and thus did not fail correctly on invalid input. Signed-off-by: Emil Gydesen --- include/zephyr/bluetooth/audio/bap.h | 3 ++- subsys/bluetooth/audio/bap_stream.c | 16 +++++++++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/include/zephyr/bluetooth/audio/bap.h b/include/zephyr/bluetooth/audio/bap.h index 86f55ecf0d0..fa5d20f00cf 100644 --- a/include/zephyr/bluetooth/audio/bap.h +++ b/include/zephyr/bluetooth/audio/bap.h @@ -415,7 +415,8 @@ struct bt_bap_ep_info { * @param ep The audio stream endpoint object. * @param info The structure object to be filled with the info. * - * @return 0 in case of success or negative value in case of error. + * @retval 0 in case of success + * @retval -EINVAL if @p ep or @p info are NULL */ int bt_bap_ep_get_info(const struct bt_bap_ep *ep, struct bt_bap_ep_info *info); diff --git a/subsys/bluetooth/audio/bap_stream.c b/subsys/bluetooth/audio/bap_stream.c index b10d32303fd..29e058544e9 100644 --- a/subsys/bluetooth/audio/bap_stream.c +++ b/subsys/bluetooth/audio/bap_stream.c @@ -99,7 +99,21 @@ void bt_bap_stream_cb_register(struct bt_bap_stream *stream, int bt_bap_ep_get_info(const struct bt_bap_ep *ep, struct bt_bap_ep_info *info) { - enum bt_audio_dir dir = ep->dir; + enum bt_audio_dir dir; + + CHECKIF(ep == NULL) { + LOG_DBG("ep is NULL"); + + return -EINVAL; + } + + CHECKIF(info == NULL) { + LOG_DBG("info is NULL"); + + return -EINVAL; + } + + dir = ep->dir; info->id = ep->status.id; info->state = ep->status.state; From 20283846d0ed430d006449f175b9383adede4926 Mon Sep 17 00:00:00 2001 From: Graham Harrison Date: Fri, 8 Mar 2024 14:02:40 -0700 Subject: [PATCH 0386/2402] samples: bluetooth: ESS Naming clean up Fix for ESS naming Signed-off-by: Graham Harrison --- samples/bluetooth/peripheral_esp/src/main.c | 110 ++++++++++++++------ 1 file changed, 78 insertions(+), 32 deletions(-) diff --git a/samples/bluetooth/peripheral_esp/src/main.c b/samples/bluetooth/peripheral_esp/src/main.c index f6e1ed31aae..1375b130172 100644 --- a/samples/bluetooth/peripheral_esp/src/main.c +++ b/samples/bluetooth/peripheral_esp/src/main.c @@ -32,20 +32,66 @@ #define SENSOR_3_UPDATE_IVAL 60 /* ESS error definitions */ -#define ESS_ERR_WRITE_REJECT 0x80 -#define ESS_ERR_COND_NOT_SUPP 0x81 +#define ESS_ERR_WRITE_REJECT 0x80 +#define ESS_ERR_COND_NOT_SUPP 0x81 /* ESS Trigger Setting conditions */ -#define ESS_TRIGGER_INACTIVE 0x00 -#define ESS_FIXED_TIME_INTERVAL 0x01 -#define ESS_NO_LESS_THAN_SPECIFIED_TIME 0x02 -#define ESS_VALUE_CHANGED 0x03 -#define ESS_LESS_THAN_REF_VALUE 0x04 -#define ESS_LESS_OR_EQUAL_TO_REF_VALUE 0x05 -#define ESS_GREATER_THAN_REF_VALUE 0x06 -#define ESS_GREATER_OR_EQUAL_TO_REF_VALUE 0x07 -#define ESS_EQUAL_TO_REF_VALUE 0x08 -#define ESS_NOT_EQUAL_TO_REF_VALUE 0x09 +#define ESS_TRIGGER_INACTIVE 0x00 +#define ESS_TRIGGER_FIXED_TIME_INTERVAL 0x01 +#define ESS_TRIGGER_NO_LESS_THAN_SPECIFIED_TIME 0x02 +#define ESS_TRIGGER_VALUE_CHANGED 0x03 +#define ESS_TRIGGER_LESS_THAN_REF_VALUE 0x04 +#define ESS_TRIGGER_LESS_OR_EQUAL_TO_REF_VALUE 0x05 +#define ESS_TRIGGER_GREATER_THAN_REF_VALUE 0x06 +#define ESS_TRIGGER_GREATER_OR_EQUAL_TO_REF_VALUE 0x07 +#define ESS_TRIGGER_EQUAL_TO_REF_VALUE 0x08 +#define ESS_TRIGGER_NOT_EQUAL_TO_REF_VALUE 0x09 + +/* ESS Measurement Descriptor – Sampling Functions */ +#define ESS_DESC_SAMPLING_UNSPECIFIED 0x00 +#define ESS_DESC_SAMPLING_INSTANTANEOUS 0x01 +#define ESS_DESC_SAMPLING_ARITHMETIC_MEAN 0x02 +#define ESS_DESC_SAMPLING_RMS 0x03 +#define ESS_DESC_SAMPLING_MAXIMUM 0x04 +#define ESS_DESC_SAMPLING_MINIMUM 0x05 +#define ESS_DESC_SAMPLING_ACCUMULATED 0x06 +#define ESS_DESC_SAMPLING_COUNT 0x07 + +/* ES Measurement Descriptor - Applications */ +#define ESS_DESC_APP_UNSPECIFIED 0x00 +#define ESS_DESC_APP_AIR 0x01 +#define ESS_DESC_APP_WATER 0x02 +#define ESS_DESC_APP_BAROMETRIC 0x03 +#define ESS_DESC_APP_SOIL 0x04 +#define ESS_DESC_APP_INFRARED 0x05 +#define ESS_DESC_APP_MAP_DATABASE 0x06 +#define ESS_DESC_APP_BAROMETRIC_ELEVATION_SOURCE 0x07 +#define ESS_DESC_APP_GPS_ONLY_ELEVATION_SOURCE 0x08 +#define ESS_DESC_APP_GPS_AND_MAP_DATABASE_ELEVATION_SOURCE 0x09 +#define ESS_DESC_APP_VERTICAL_DATUM_ELEVATION_SOURCE 0x0A +#define ESS_DESC_APP_ONSHORE 0x0B +#define ESS_DESC_APP_ONBOARD_VESSEL_OR_VEHICLE 0x0C +#define ESS_DESC_APP_FRONT 0x0D +#define ESS_DESC_APP_BACK_REAR 0x0E +#define ESS_DESC_APP_UPPER 0x0F +#define ESS_DESC_APP_LOWER 0x10 +#define ESS_DESC_APP_PRIMARY 0x11 +#define ESS_DESC_APP_SECONDARY 0x12 +#define ESS_DESC_APP_OUTDOOR 0x13 +#define ESS_DESC_APP_INDOOR 0x14 +#define ESS_DESC_APP_TOP 0x15 +#define ESS_DESC_APP_BOTTOM 0x16 +#define ESS_DESC_APP_MAIN 0x17 +#define ESS_DESC_APP_BACKUP 0x18 +#define ESS_DESC_APP_AUXILIARY 0x19 +#define ESS_DESC_APP_SUPPLEMENTARY 0x1A +#define ESS_DESC_APP_INSIDE 0x1B +#define ESS_DESC_APP_OUTSIDE 0x1C +#define ESS_DESC_APP_LEFT 0x1D +#define ESS_DESC_APP_RIGHT 0x1E +#define ESS_DESC_APP_INTERNAL 0x1F +#define ESS_DESC_APP_EXTERNAL 0x20 +#define ESS_DESC_APP_SOLAR 0x21 static ssize_t read_u16(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, uint16_t len, uint16_t offset) @@ -96,11 +142,11 @@ static struct temperature_sensor sensor_1 = { .temp_value = 1200, .lower_limit = -10000, .upper_limit = 10000, - .condition = ESS_VALUE_CHANGED, - .meas.sampling_func = 0x00, + .condition = ESS_TRIGGER_VALUE_CHANGED, + .meas.sampling_func = ESS_DESC_SAMPLING_UNSPECIFIED, .meas.meas_period = 0x01, .meas.update_interval = SENSOR_1_UPDATE_IVAL, - .meas.application = 0x1c, + .meas.application = ESS_DESC_APP_OUTSIDE, .meas.meas_uncertainty = 0x04, }; @@ -108,20 +154,20 @@ static struct temperature_sensor sensor_2 = { .temp_value = 1800, .lower_limit = -1000, .upper_limit = 5000, - .condition = ESS_VALUE_CHANGED, - .meas.sampling_func = 0x00, + .condition = ESS_TRIGGER_VALUE_CHANGED, + .meas.sampling_func = ESS_DESC_SAMPLING_UNSPECIFIED, .meas.meas_period = 0x01, .meas.update_interval = SENSOR_2_UPDATE_IVAL, - .meas.application = 0x1b, + .meas.application = ESS_DESC_APP_INSIDE, .meas.meas_uncertainty = 0x04, }; static struct humidity_sensor sensor_3 = { .humid_value = 6233, - .meas.sampling_func = 0x02, + .meas.sampling_func = ESS_DESC_SAMPLING_ARITHMETIC_MEAN, .meas.meas_period = 0x0e10, .meas.update_interval = SENSOR_3_UPDATE_IVAL, - .meas.application = 0x1c, + .meas.application = ESS_DESC_APP_OUTSIDE, .meas.meas_uncertainty = 0x01, }; @@ -191,14 +237,14 @@ static ssize_t read_temp_trigger_setting(struct bt_conn *conn, /* Operand N/A */ case ESS_TRIGGER_INACTIVE: __fallthrough; - case ESS_VALUE_CHANGED: + case ESS_TRIGGER_VALUE_CHANGED: return bt_gatt_attr_read(conn, attr, buf, len, offset, &sensor->condition, sizeof(sensor->condition)); /* Seconds */ - case ESS_FIXED_TIME_INTERVAL: + case ESS_TRIGGER_FIXED_TIME_INTERVAL: __fallthrough; - case ESS_NO_LESS_THAN_SPECIFIED_TIME: { + case ESS_TRIGGER_NO_LESS_THAN_SPECIFIED_TIME: { struct es_trigger_setting_seconds rp; rp.condition = sensor->condition; @@ -226,23 +272,23 @@ static bool check_condition(uint8_t condition, int16_t old_val, int16_t new_val, switch (condition) { case ESS_TRIGGER_INACTIVE: return false; - case ESS_FIXED_TIME_INTERVAL: - case ESS_NO_LESS_THAN_SPECIFIED_TIME: + case ESS_TRIGGER_FIXED_TIME_INTERVAL: + case ESS_TRIGGER_NO_LESS_THAN_SPECIFIED_TIME: /* TODO: Check time requirements */ return false; - case ESS_VALUE_CHANGED: + case ESS_TRIGGER_VALUE_CHANGED: return new_val != old_val; - case ESS_LESS_THAN_REF_VALUE: + case ESS_TRIGGER_LESS_THAN_REF_VALUE: return new_val < ref_val; - case ESS_LESS_OR_EQUAL_TO_REF_VALUE: + case ESS_TRIGGER_LESS_OR_EQUAL_TO_REF_VALUE: return new_val <= ref_val; - case ESS_GREATER_THAN_REF_VALUE: + case ESS_TRIGGER_GREATER_THAN_REF_VALUE: return new_val > ref_val; - case ESS_GREATER_OR_EQUAL_TO_REF_VALUE: + case ESS_TRIGGER_GREATER_OR_EQUAL_TO_REF_VALUE: return new_val >= ref_val; - case ESS_EQUAL_TO_REF_VALUE: + case ESS_TRIGGER_EQUAL_TO_REF_VALUE: return new_val == ref_val; - case ESS_NOT_EQUAL_TO_REF_VALUE: + case ESS_TRIGGER_NOT_EQUAL_TO_REF_VALUE: return new_val != ref_val; default: return false; From 2d11fbe532e80830679b3a4e1a7d300baa511318 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Thu, 15 Feb 2024 18:01:55 +0100 Subject: [PATCH 0387/2402] Bluetooth: BAP: BA: Add additional PAST log in past_available Add additional logging in past_available to easily see the PAST support of the broadcast assistant and scan delegator devices. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/bap_broadcast_assistant.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/subsys/bluetooth/audio/bap_broadcast_assistant.c b/subsys/bluetooth/audio/bap_broadcast_assistant.c index 557830452d5..e8a335a0321 100644 --- a/subsys/bluetooth/audio/bap_broadcast_assistant.c +++ b/subsys/bluetooth/audio/bap_broadcast_assistant.c @@ -140,6 +140,10 @@ static bool past_available(const struct bt_conn *conn, const bt_addr_le_t *adv_addr, uint8_t sid) { + LOG_DBG("%p remote %s PAST, local %s PAST", (void *)conn, + BT_FEAT_LE_PAST_RECV(conn->le.features) ? "supports" : "does not support", + BT_FEAT_LE_PAST_SEND(bt_dev.le.features) ? "supports" : "does not support"); + return BT_FEAT_LE_PAST_RECV(conn->le.features) && BT_FEAT_LE_PAST_SEND(bt_dev.le.features) && bt_le_per_adv_sync_lookup_addr(adv_addr, sid) != NULL; From c1272195f0f0af7f9f121bd25bbcf34d6530b727 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Wed, 14 Feb 2024 10:21:22 +0100 Subject: [PATCH 0388/2402] Bluetooth: BAP: Shell: Modify bcast sink streams to use shell_stream Modify the broadcast_sink_streams to be an array of shell_stream instead of bt_bap_stream, so that it can be used in a similar way as the rest of the streams. To help the transition, a new helper function, bap_stream_from_shell_stream, was added. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/shell/bap.c | 62 ++++++++++++++++++------------ 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index 8c9b35330ff..0d7f5f4565f 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -64,7 +64,7 @@ struct shell_stream broadcast_source_streams[CONFIG_BT_BAP_BROADCAST_SRC_STREAM_ struct broadcast_source default_source; #endif /* CONFIG_BT_BAP_BROADCAST_SOURCE */ #if defined(CONFIG_BT_BAP_BROADCAST_SINK) -static struct bt_bap_stream broadcast_sink_streams[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT]; +static struct shell_stream broadcast_sink_streams[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT]; static struct broadcast_sink default_broadcast_sink; #endif /* CONFIG_BT_BAP_BROADCAST_SINK */ @@ -165,6 +165,11 @@ static struct shell_stream *shell_stream_from_bap_stream(struct bt_bap_stream *b return sh_stream; } +static struct bt_bap_stream *bap_stream_from_shell_stream(struct shell_stream *sh_stream) +{ + return &sh_stream->stream.bap_stream; +} + #if defined(CONFIG_BT_AUDIO_TX) static uint16_t get_next_seq_num(struct bt_bap_stream *bap_stream) { @@ -281,7 +286,7 @@ static void lc3_audio_send_data(struct k_work *work) { struct shell_stream *sh_stream = CONTAINER_OF(k_work_delayable_from_work(work), struct shell_stream, audio_send_work); - struct bt_bap_stream *bap_stream = &sh_stream->stream.bap_stream; + struct bt_bap_stream *bap_stream = bap_stream_from_shell_stream(sh_stream); const uint16_t tx_sdu_len = sh_stream->lc3_frames_per_sdu * sh_stream->lc3_octets_per_frame; struct net_buf *buf; uint8_t *net_buffer; @@ -440,7 +445,7 @@ static void set_unicast_stream(struct bt_bap_stream *stream) default_stream = stream; for (size_t i = 0U; i < ARRAY_SIZE(unicast_streams); i++) { - if (stream == &unicast_streams[i].stream.bap_stream) { + if (stream == bap_stream_from_shell_stream(&unicast_streams[i])) { shell_print(ctx_shell, "Default stream: %u", i + 1); } } @@ -465,7 +470,7 @@ static int cmd_select_unicast(const struct shell *sh, size_t argc, char *argv[]) return -ENOEXEC; } - stream = &unicast_streams[index].stream.bap_stream; + stream = bap_stream_from_shell_stream(&unicast_streams[index]); set_unicast_stream(stream); @@ -479,7 +484,7 @@ static const struct bt_audio_codec_qos_pref qos_pref = static struct bt_bap_stream *stream_alloc(void) { for (size_t i = 0; i < ARRAY_SIZE(unicast_streams); i++) { - struct bt_bap_stream *stream = &unicast_streams[i].stream.bap_stream; + struct bt_bap_stream *stream = bap_stream_from_shell_stream(&unicast_streams[i]); if (!stream->conn) { return stream; @@ -697,11 +702,13 @@ int bap_ac_create_unicast_group(const struct bap_unicast_ac_param *param, */ for (size_t i = 0U; i < snk_cnt; i++) { snk_group_stream_params[i].qos = snk_qos[i]; - snk_group_stream_params[i].stream = &snk_uni_streams[i]->stream.bap_stream; + snk_group_stream_params[i].stream = + bap_stream_from_shell_stream(snk_uni_streams[i]); } for (size_t i = 0U; i < src_cnt; i++) { src_group_stream_params[i].qos = src_qos[i]; - src_group_stream_params[i].stream = &src_uni_streams[i]->stream.bap_stream; + src_group_stream_params[i].stream = + bap_stream_from_shell_stream(src_uni_streams[i]); } for (size_t i = 0U; i < param->conn_cnt; i++) { @@ -1015,7 +1022,7 @@ static int cmd_config(const struct shell *sh, size_t argc, char *argv[]) conn_index = bt_conn_index(default_conn); if (default_stream == NULL) { - bap_stream = &unicast_streams[0].stream.bap_stream; + bap_stream = bap_stream_from_shell_stream(&unicast_streams[0]); } else { bap_stream = default_stream; } @@ -1304,7 +1311,7 @@ static int create_unicast_group(const struct shell *sh) memset(&group_param, 0, sizeof(group_param)); for (size_t i = 0U; i < ARRAY_SIZE(unicast_streams); i++) { - struct bt_bap_stream *stream = &unicast_streams[i].stream.bap_stream; + struct bt_bap_stream *stream = bap_stream_from_shell_stream(&unicast_streams[i]); struct shell_stream *uni_stream = &unicast_streams[i]; if (stream->ep != NULL) { @@ -2434,7 +2441,9 @@ static void stream_stopped_cb(struct bt_bap_stream *stream, uint8_t reason) #endif /* CONFIG_LIBLC3 && CONFIG_BT_AUDIO_TX*/ #if defined(CONFIG_BT_BAP_BROADCAST_SINK) - if (IS_ARRAY_ELEMENT(broadcast_sink_streams, stream)) { + struct shell_stream *sh_stream = shell_stream_from_bap_stream(stream); + + if (IS_ARRAY_ELEMENT(broadcast_sink_streams, sh_stream)) { if (default_broadcast_sink.stream_cnt != 0) { default_broadcast_sink.stream_cnt--; } @@ -2528,7 +2537,7 @@ static void stream_released_cb(struct bt_bap_stream *stream) for (size_t i = 0U; i < ARRAY_SIZE(unicast_streams); i++) { const struct bt_bap_stream *bap_stream = - &unicast_streams[i].stream.bap_stream; + bap_stream_from_shell_stream(&unicast_streams[i]); if (bap_stream->ep != NULL) { struct bt_bap_ep_info ep_info; @@ -2602,7 +2611,7 @@ static int cmd_select_broadcast_source(const struct shell *sh, size_t argc, return -ENOEXEC; } - default_stream = &broadcast_source_streams[index].stream.bap_stream; + default_stream = bap_stream_from_shell_stream(&broadcast_source_streams[index]); return 0; } @@ -2677,7 +2686,8 @@ static int cmd_create_broadcast(const struct shell *sh, size_t argc, (void)memset(stream_params, 0, sizeof(stream_params)); for (size_t i = 0; i < ARRAY_SIZE(stream_params); i++) { - stream_params[i].stream = &broadcast_source_streams[i].stream.bap_stream; + stream_params[i].stream = + bap_stream_from_shell_stream(&broadcast_source_streams[i]); } subgroup_param.params_count = ARRAY_SIZE(stream_params); subgroup_param.params = stream_params; @@ -2696,7 +2706,7 @@ static int cmd_create_broadcast(const struct shell *sh, size_t argc, named_preset->name); if (default_stream == NULL) { - default_stream = &broadcast_source_streams[0].stream.bap_stream; + default_stream = bap_stream_from_shell_stream(&broadcast_source_streams[0]); } return 0; @@ -2901,7 +2911,7 @@ static int cmd_sync_broadcast(const struct shell *sh, size_t argc, char *argv[]) (void)memset(streams, 0, sizeof(streams)); for (size_t i = 0; i < ARRAY_SIZE(streams); i++) { - streams[i] = &broadcast_sink_streams[i]; + streams[i] = bap_stream_from_shell_stream(&broadcast_sink_streams[i]); } err = bt_bap_broadcast_sink_sync(default_broadcast_sink.bap_sink, bis_bitfield, streams, @@ -3105,7 +3115,8 @@ static int cmd_init(const struct shell *sh, size_t argc, char *argv[]) #if defined(CONFIG_BT_BAP_UNICAST) for (i = 0; i < ARRAY_SIZE(unicast_streams); i++) { - bt_bap_stream_cb_register(&unicast_streams[i].stream.bap_stream, &stream_ops); + bt_bap_stream_cb_register(bap_stream_from_shell_stream(&unicast_streams[i]), + &stream_ops); if (IS_ENABLED(CONFIG_BT_BAP_UNICAST_CLIENT) && IS_ENABLED(CONFIG_BT_CAP_INITIATOR)) { @@ -3124,15 +3135,15 @@ static int cmd_init(const struct shell *sh, size_t argc, char *argv[]) bt_le_scan_cb_register(&bap_scan_cb); for (i = 0; i < ARRAY_SIZE(broadcast_sink_streams); i++) { - bt_bap_stream_cb_register(&broadcast_sink_streams[i], - &stream_ops); + bt_bap_stream_cb_register(bap_stream_from_shell_stream(&broadcast_sink_streams[i]), + &stream_ops); } #endif /* CONFIG_BT_BAP_BROADCAST_SOURCE */ #if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) for (i = 0; i < ARRAY_SIZE(broadcast_source_streams); i++) { - bt_bap_stream_cb_register(&broadcast_source_streams[i].stream.bap_stream, - &stream_ops); + bt_bap_stream_cb_register( + bap_stream_from_shell_stream(&broadcast_source_streams[i]), &stream_ops); } #endif /* CONFIG_BT_BAP_BROADCAST_SOURCE */ @@ -3240,7 +3251,7 @@ static int stream_start_sine(struct shell_stream *sh_stream) } sh_stream->tx_active = true; - sh_stream->seq_num = get_next_seq_num(&sh_stream->stream.bap_stream); + sh_stream->seq_num = get_next_seq_num(bap_stream_from_shell_stream(sh_stream)); return 0; } @@ -3265,7 +3276,7 @@ static int cmd_start_sine(const struct shell *sh, size_t argc, char *argv[]) for (size_t i = 0U; i < ARRAY_SIZE(unicast_streams); i++) { struct shell_stream *sh_stream = &unicast_streams[i]; - struct bt_bap_stream *bap_stream = &sh_stream->stream.bap_stream; + struct bt_bap_stream *bap_stream = bap_stream_from_shell_stream(sh_stream); if (!lc3_initialized) { err = init_lc3_encoder(sh_stream); @@ -3294,7 +3305,7 @@ static int cmd_start_sine(const struct shell *sh, size_t argc, char *argv[]) for (size_t i = 0U; i < ARRAY_SIZE(broadcast_source_streams); i++) { struct shell_stream *sh_stream = &broadcast_source_streams[i]; - struct bt_bap_stream *bap_stream = &sh_stream->stream.bap_stream; + struct bt_bap_stream *bap_stream = bap_stream_from_shell_stream(sh_stream); if (!lc3_initialized) { err = init_lc3_encoder(sh_stream); @@ -3364,7 +3375,8 @@ static int cmd_stop_sine(const struct shell *sh, size_t argc, char *argv[]) if (stop_all) { for (size_t i = 0U; i < ARRAY_SIZE(unicast_streams); i++) { - struct bt_bap_stream *bap_stream = &unicast_streams[i].stream.bap_stream; + struct bt_bap_stream *bap_stream = + bap_stream_from_shell_stream(&unicast_streams[i]); if (unicast_streams[i].tx_active) { clear_lc3_sine_data(bap_stream); @@ -3374,7 +3386,7 @@ static int cmd_stop_sine(const struct shell *sh, size_t argc, char *argv[]) for (size_t i = 0U; i < ARRAY_SIZE(broadcast_source_streams); i++) { struct bt_bap_stream *bap_stream = - &broadcast_source_streams[i].stream.bap_stream; + bap_stream_from_shell_stream(&broadcast_source_streams[i]); if (unicast_streams[i].tx_active) { clear_lc3_sine_data(bap_stream); shell_print(sh, "Stopped transmitting on stream %p", bap_stream); From 675c8e86a4923957f4d2bf08f9b56aeb743cd1f1 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Mon, 22 Jan 2024 14:58:48 +0100 Subject: [PATCH 0389/2402] Bluetooth: Audio: Shell: Add human-readable printing of remote caps print_codec_cap has been modified to print the remote caps in a more human-readable way, so it is easier to read and understand the remote server's capabilities. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/shell/audio.h | 163 ++++++++++++++++++++++++++- 1 file changed, 160 insertions(+), 3 deletions(-) diff --git a/subsys/bluetooth/audio/shell/audio.h b/subsys/bluetooth/audio/shell/audio.h index e767bf0949e..16e02087e0c 100644 --- a/subsys/bluetooth/audio/shell/audio.h +++ b/subsys/bluetooth/audio/shell/audio.h @@ -197,15 +197,172 @@ static void print_ltv_array(const struct shell *sh, const char *str, const uint8 bt_audio_data_parse(ltv_data, ltv_data_len, print_ltv_elem, <v_info); } +static inline char *codec_cap_freq_bit_to_str(enum bt_audio_codec_cap_freq freq) +{ + switch (freq) { + case BT_AUDIO_CODEC_CAP_FREQ_8KHZ: + return "8000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_11KHZ: + return "11025 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_16KHZ: + return "16000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_22KHZ: + return "22050 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_24KHZ: + return "24000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_32KHZ: + return "32000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_44KHZ: + return "44100 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_48KHZ: + return "48000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_88KHZ: + return "88200 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_96KHZ: + return "96000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_176KHZ: + return "176400 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_192KHZ: + return "192000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_384KHZ: + return "384000 Hz"; + default: + return "Unknown supported frequency"; + } +} + +static inline void print_codec_cap_freq(const struct shell *sh, enum bt_audio_codec_cap_freq freq) +{ + shell_print(sh, "\tSupported sampling frequencies:"); + /* There can be up to 16 bits set in the field */ + for (size_t i = 0; i < 16; i++) { + const uint16_t bit_val = BIT(i); + + if (freq & bit_val) { + shell_print(sh, "\t\t%s (0x%04X)", codec_cap_freq_bit_to_str(bit_val), + bit_val); + } + } +} + +static inline char *codec_cap_frame_dur_bit_to_str(enum bt_audio_codec_cap_frame_dur frame_dur) +{ + switch (frame_dur) { + case BT_AUDIO_CODEC_CAP_DURATION_7_5: + return "7.5 ms"; + case BT_AUDIO_CODEC_CAP_DURATION_10: + return "10 ms"; + case BT_AUDIO_CODEC_CAP_DURATION_PREFER_7_5: + return "7.5 ms preferred"; + case BT_AUDIO_CODEC_CAP_DURATION_PREFER_10: + return "10 ms preferred"; + default: + return "Unknown frame duration"; + } +} + +static inline void print_codec_cap_frame_dur(const struct shell *sh, + enum bt_audio_codec_cap_frame_dur frame_dur) +{ + shell_print(sh, "\tSupported frame durations:"); + /* There can be up to 8 bits set in the field */ + for (size_t i = 0; i < 8; i++) { + const uint8_t bit_val = BIT(i); + + if (frame_dur & bit_val) { + shell_print(sh, "\t\t%s (0x%02X)", codec_cap_frame_dur_bit_to_str(bit_val), + bit_val); + } + } +} + +static inline char *codec_cap_chan_count_bit_to_str(enum bt_audio_codec_cap_chan_count chan_count) +{ + switch (chan_count) { + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_1: + return "1 channel"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_2: + return "2 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_3: + return "3 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_4: + return "4 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_5: + return "5 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_6: + return "6 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_7: + return "7 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_8: + return "8 channels"; + default: + return "Unknown channel count"; + } +} + +static inline void print_codec_cap_chan_count(const struct shell *sh, + enum bt_audio_codec_cap_chan_count chan_count) +{ + shell_print(sh, "\tSupported channel counts:"); + /* There can be up to 8 bits set in the field */ + for (size_t i = 0; i < 8; i++) { + const uint8_t bit_val = BIT(i); + + if (chan_count & bit_val) { + shell_print(sh, "\t\t%s (0x%02X)", codec_cap_chan_count_bit_to_str(bit_val), + bit_val); + } + } +} + +static inline void print_codec_cap_octets_per_codec_frame( + const struct shell *sh, const struct bt_audio_codec_octets_per_codec_frame *codec_frame) +{ + shell_print(sh, "\tSupported octets per codec frame counts:\n\t\tMin: %u\n\t\tMax: %u", + codec_frame->min, codec_frame->max); +} + +static inline void print_codec_cap_max_codec_frames_per_sdu(const struct shell *sh, + uint8_t codec_frames_per_sdu) +{ + shell_print(sh, "\tSupported max codec frames per SDU: %u", codec_frames_per_sdu); +} + static inline void print_codec_cap(const struct shell *sh, const struct bt_audio_codec_cap *codec_cap) { - shell_print(sh, "codec cap id 0x%02x cid 0x%04x vid 0x%04x count %u", codec_cap->id, - codec_cap->cid, codec_cap->vid, codec_cap->data_len); + shell_print(sh, "codec cap id 0x%02x cid 0x%04x vid 0x%04x", codec_cap->id, codec_cap->cid, + codec_cap->vid); #if CONFIG_BT_AUDIO_CODEC_CAP_MAX_DATA_SIZE > 0 if (codec_cap->id == BT_HCI_CODING_FORMAT_LC3) { - print_ltv_array(sh, "data", codec_cap->data, codec_cap->data_len); + struct bt_audio_codec_octets_per_codec_frame codec_frame; + int ret; + + ret = bt_audio_codec_cap_get_freq(codec_cap); + if (ret >= 0) { + print_codec_cap_freq(sh, (enum bt_audio_codec_cap_freq)ret); + } + + ret = bt_audio_codec_cap_get_frame_dur(codec_cap); + if (ret >= 0) { + print_codec_cap_frame_dur(sh, (enum bt_audio_codec_cap_frame_dur)ret); + } + + ret = bt_audio_codec_cap_get_supported_audio_chan_counts(codec_cap); + if (ret >= 0) { + print_codec_cap_chan_count(sh, (enum bt_audio_codec_cap_chan_count)ret); + } + + ret = bt_audio_codec_cap_get_octets_per_frame(codec_cap, &codec_frame); + if (ret >= 0) { + print_codec_cap_octets_per_codec_frame(sh, &codec_frame); + } + + ret = bt_audio_codec_cap_get_max_codec_frames_per_sdu(codec_cap); + if (ret >= 0) { + print_codec_cap_max_codec_frames_per_sdu(sh, (uint8_t)ret); + } } else { /* If not LC3, we cannot assume it's LTV */ shell_hexdump(sh, codec_cap->data, codec_cap->data_len); } From dd5925301e56f4490d03b5e06dd0b17cf34fc5f7 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Mon, 22 Jan 2024 15:58:05 +0100 Subject: [PATCH 0390/2402] Bluetooth: Audio: Shell: Add human-readable printing of codec configs print_codec_cfg has been modified to print the codec configs in a more human-readable way, so it is easier to read. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/shell/audio.h | 134 ++++++++++++++++++++++++++- 1 file changed, 133 insertions(+), 1 deletion(-) diff --git a/subsys/bluetooth/audio/shell/audio.h b/subsys/bluetooth/audio/shell/audio.h index 16e02087e0c..ac098811499 100644 --- a/subsys/bluetooth/audio/shell/audio.h +++ b/subsys/bluetooth/audio/shell/audio.h @@ -373,6 +373,112 @@ static inline void print_codec_cap(const struct shell *sh, #endif /* CONFIG_BT_AUDIO_CODEC_CAP_MAX_METADATA_SIZE > 0 */ } +static inline void print_codec_cfg_freq(const struct shell *sh, enum bt_audio_codec_cfg_freq freq) +{ + shell_print(sh, "\tSampling frequency: %u Hz (%u)", + bt_audio_codec_cfg_freq_to_freq_hz(freq), freq); +} + +static inline void print_codec_cfg_frame_dur(const struct shell *sh, + enum bt_audio_codec_cfg_frame_dur frame_dur) +{ + shell_print(sh, "\tFrame duration: %u us (%u)", + bt_audio_codec_cfg_frame_dur_to_frame_dur_us(frame_dur), frame_dur); +} + +static inline char *chan_location_bit_to_str(enum bt_audio_location chan_allocation) +{ + switch (chan_allocation) { + case BT_AUDIO_LOCATION_MONO_AUDIO: + return "Mono"; + case BT_AUDIO_LOCATION_FRONT_LEFT: + return "Front left"; + case BT_AUDIO_LOCATION_FRONT_RIGHT: + return "Front right"; + case BT_AUDIO_LOCATION_FRONT_CENTER: + return "Front center"; + case BT_AUDIO_LOCATION_LOW_FREQ_EFFECTS_1: + return "Low frequency effects 1"; + case BT_AUDIO_LOCATION_BACK_LEFT: + return "Back left"; + case BT_AUDIO_LOCATION_BACK_RIGHT: + return "Back right"; + case BT_AUDIO_LOCATION_FRONT_LEFT_OF_CENTER: + return "Front left of center"; + case BT_AUDIO_LOCATION_FRONT_RIGHT_OF_CENTER: + return "Front right of center"; + case BT_AUDIO_LOCATION_BACK_CENTER: + return "Back center"; + case BT_AUDIO_LOCATION_LOW_FREQ_EFFECTS_2: + return "Low frequency effects 2"; + case BT_AUDIO_LOCATION_SIDE_LEFT: + return "Side left"; + case BT_AUDIO_LOCATION_SIDE_RIGHT: + return "Side right"; + case BT_AUDIO_LOCATION_TOP_FRONT_LEFT: + return "Top front left"; + case BT_AUDIO_LOCATION_TOP_FRONT_RIGHT: + return "Top front right"; + case BT_AUDIO_LOCATION_TOP_FRONT_CENTER: + return "Top front center"; + case BT_AUDIO_LOCATION_TOP_CENTER: + return "Top center"; + case BT_AUDIO_LOCATION_TOP_BACK_LEFT: + return "Top back left"; + case BT_AUDIO_LOCATION_TOP_BACK_RIGHT: + return "Top back right"; + case BT_AUDIO_LOCATION_TOP_SIDE_LEFT: + return "Top side left"; + case BT_AUDIO_LOCATION_TOP_SIDE_RIGHT: + return "Top side right"; + case BT_AUDIO_LOCATION_TOP_BACK_CENTER: + return "Top back center"; + case BT_AUDIO_LOCATION_BOTTOM_FRONT_CENTER: + return "Bottom front center"; + case BT_AUDIO_LOCATION_BOTTOM_FRONT_LEFT: + return "Bottom front left"; + case BT_AUDIO_LOCATION_BOTTOM_FRONT_RIGHT: + return "Bottom front right"; + case BT_AUDIO_LOCATION_FRONT_LEFT_WIDE: + return "Front left wide"; + case BT_AUDIO_LOCATION_FRONT_RIGHT_WIDE: + return "Front right wde"; + case BT_AUDIO_LOCATION_LEFT_SURROUND: + return "Left surround"; + case BT_AUDIO_LOCATION_RIGHT_SURROUND: + return "Right surround"; + default: + return "Unknown location"; + } +} + +static inline void print_codec_cfg_chan_allocation(const struct shell *sh, + enum bt_audio_location chan_allocation) +{ + shell_print(sh, "\tChannel allocation:"); + /* There can be up to 32 bits set in the field */ + for (size_t i = 0; i < 32; i++) { + const uint8_t bit_val = BIT(i); + + if (chan_allocation & bit_val) { + shell_print(sh, "\t\t%s (0x%08X)", chan_location_bit_to_str(bit_val), + bit_val); + } + } +} + +static inline void print_codec_cfg_octets_per_frame(const struct shell *sh, + uint16_t octets_per_frame) +{ + shell_print(sh, "\tOctets per codec frame: %u", octets_per_frame); +} + +static inline void print_codec_cfg_frame_blocks_per_sdu(const struct shell *sh, + uint8_t frame_blocks_per_sdu) +{ + shell_print(sh, "\tCodec frame blocks per SDU: %u", frame_blocks_per_sdu); +} + static inline void print_codec_cfg(const struct shell *sh, const struct bt_audio_codec_cfg *codec_cfg) { @@ -381,7 +487,33 @@ static inline void print_codec_cfg(const struct shell *sh, #if CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 if (codec_cfg->id == BT_HCI_CODING_FORMAT_LC3) { - print_ltv_array(sh, "data", codec_cfg->data, codec_cfg->data_len); + enum bt_audio_location chan_allocation; + int ret; + + ret = bt_audio_codec_cfg_get_freq(codec_cfg); + if (ret >= 0) { + print_codec_cfg_freq(sh, (enum bt_audio_codec_cfg_freq)ret); + } + + ret = bt_audio_codec_cfg_get_frame_dur(codec_cfg); + if (ret >= 0) { + print_codec_cfg_frame_dur(sh, (enum bt_audio_codec_cfg_frame_dur)ret); + } + + ret = bt_audio_codec_cfg_get_chan_allocation(codec_cfg, &chan_allocation); + if (ret >= 0) { + print_codec_cfg_chan_allocation(sh, chan_allocation); + } + + ret = bt_audio_codec_cfg_get_octets_per_frame(codec_cfg); + if (ret >= 0) { + print_codec_cfg_octets_per_frame(sh, (uint16_t)ret); + } + + ret = bt_audio_codec_cfg_get_frame_blocks_per_sdu(codec_cfg, false); + if (ret >= 0) { + print_codec_cfg_frame_blocks_per_sdu(sh, (uint8_t)ret); + } } else { /* If not LC3, we cannot assume it's LTV */ shell_hexdump(sh, codec_cfg->data, codec_cfg->data_len); } From f7cbc9b9437a8049d7efad3844001cfca3703a5c Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 23 Jan 2024 15:35:32 +0100 Subject: [PATCH 0391/2402] Bluetooth: Audio: Shell: Add human-readable printing of codec metadata print_codec_cfg and print_codec_cap has been modified to print the codec metadata in a more human-readable way, so it is easier to read. This also adds the (final) human readable support when parsing and printing BASEs. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/shell/audio.h | 368 +++++++++++++++++++++++++-- 1 file changed, 348 insertions(+), 20 deletions(-) diff --git a/subsys/bluetooth/audio/shell/audio.h b/subsys/bluetooth/audio/shell/audio.h index ac098811499..ba185bf0326 100644 --- a/subsys/bluetooth/audio/shell/audio.h +++ b/subsys/bluetooth/audio/shell/audio.h @@ -197,6 +197,202 @@ static void print_ltv_array(const struct shell *sh, const char *str, const uint8 bt_audio_data_parse(ltv_data, ltv_data_len, print_ltv_elem, <v_info); } +static inline char *context_bit_to_str(enum bt_audio_context context) +{ + switch (context) { + case BT_AUDIO_CONTEXT_TYPE_PROHIBITED: + return "Prohibited"; + case BT_AUDIO_CONTEXT_TYPE_UNSPECIFIED: + return "Unspecified"; + case BT_AUDIO_CONTEXT_TYPE_CONVERSATIONAL: + return "Converstation"; + case BT_AUDIO_CONTEXT_TYPE_MEDIA: + return "Media"; + case BT_AUDIO_CONTEXT_TYPE_GAME: + return "Game"; + case BT_AUDIO_CONTEXT_TYPE_INSTRUCTIONAL: + return "Instructional"; + case BT_AUDIO_CONTEXT_TYPE_VOICE_ASSISTANTS: + return "Voice assistant"; + case BT_AUDIO_CONTEXT_TYPE_LIVE: + return "Live"; + case BT_AUDIO_CONTEXT_TYPE_SOUND_EFFECTS: + return "Sound effects"; + case BT_AUDIO_CONTEXT_TYPE_NOTIFICATIONS: + return "Notifications"; + case BT_AUDIO_CONTEXT_TYPE_RINGTONE: + return "Ringtone"; + case BT_AUDIO_CONTEXT_TYPE_ALERTS: + return "Alerts"; + case BT_AUDIO_CONTEXT_TYPE_EMERGENCY_ALARM: + return "Emergency alarm"; + default: + return "Unknown context"; + } +} + +static inline void print_codec_meta_pref_context(const struct shell *sh, + enum bt_audio_context context) +{ + shell_print(sh, "\tPreferred audio contexts:"); + + /* There can be up to 16 bits set in the field */ + for (size_t i = 0U; i < 16; i++) { + const uint16_t bit_val = BIT(i); + + if (context & bit_val) { + shell_print(sh, "\t\t%s (0x%04X)", context_bit_to_str(bit_val), bit_val); + } + } +} + +static inline void print_codec_meta_stream_context(const struct shell *sh, + enum bt_audio_context context) +{ + shell_print(sh, "\tStreaming audio contexts:"); + + /* There can be up to 16 bits set in the field */ + for (size_t i = 0U; i < 16; i++) { + const uint16_t bit_val = BIT(i); + + if (context & bit_val) { + shell_print(sh, "\t\t%s (0x%04X)", context_bit_to_str(bit_val), bit_val); + } + } +} + +static inline void print_codec_meta_program_info(const struct shell *sh, + const uint8_t *program_info, + uint8_t program_info_len) +{ + shell_fprintf(sh, SHELL_NORMAL, "\tProgram info:\n\t\t"); + + for (uint8_t i = 0U; i < program_info_len; i++) { + shell_fprintf(sh, SHELL_NORMAL, "%c", (char)program_info[i]); + } + + shell_fprintf(sh, SHELL_NORMAL, "\n"); +} + +static inline void print_codec_meta_language(const struct shell *sh, uint32_t stream_lang) +{ + uint8_t lang_array[3]; + + sys_put_be24(stream_lang, lang_array); + + shell_print(sh, "\tLanguage: %c%c%c", (char)lang_array[0], (char)lang_array[1], + (char)lang_array[2]); +} + +static inline void print_codec_meta_ccid_list(const struct shell *sh, const uint8_t *ccid_list, + uint8_t ccid_list_len) +{ + shell_print(sh, "\tCCID list:\n"); + + /* There can be up to 16 bits set in the field */ + for (uint8_t i = 0U; i < ccid_list_len; i++) { + + shell_print(sh, "\t\t0x%02X ", ccid_list[i]); + } +} + +static inline char *parental_rating_to_str(enum bt_audio_parental_rating parental_rating) +{ + switch (parental_rating) { + case BT_AUDIO_PARENTAL_RATING_NO_RATING: + return "No rating"; + case BT_AUDIO_PARENTAL_RATING_AGE_ANY: + return "Any"; + case BT_AUDIO_PARENTAL_RATING_AGE_5_OR_ABOVE: + return "Age 5 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_6_OR_ABOVE: + return "Age 6 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_7_OR_ABOVE: + return "Age 7 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_8_OR_ABOVE: + return "Age 8 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_9_OR_ABOVE: + return "Age 9 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_10_OR_ABOVE: + return "Age 10 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_11_OR_ABOVE: + return "Age 11 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_12_OR_ABOVE: + return "Age 12 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_13_OR_ABOVE: + return "Age 13 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_14_OR_ABOVE: + return "Age 14 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_15_OR_ABOVE: + return "Age 15 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_16_OR_ABOVE: + return "Age 16 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_17_OR_ABOVE: + return "Age 17 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_18_OR_ABOVE: + return "Age 18 or above"; + default: + return "Unknown rating"; + } +} + +static inline void print_codec_meta_parental_rating(const struct shell *sh, + enum bt_audio_parental_rating parental_rating) +{ + shell_print(sh, "\tRating: %s (0x%02X)", parental_rating_to_str(parental_rating), + (uint8_t)parental_rating); +} + +static inline void print_codec_meta_program_info_uri(const struct shell *sh, + const uint8_t *program_info_uri, + uint8_t program_info_uri_len) +{ + shell_fprintf(sh, SHELL_NORMAL, "\tProgram info URI:\n\t\t"); + + for (uint8_t i = 0U; i < program_info_uri_len; i++) { + shell_fprintf(sh, SHELL_NORMAL, "%c", (char)program_info_uri[i]); + } + + shell_fprintf(sh, SHELL_NORMAL, "\n"); +} + +static inline void print_codec_meta_audio_active_state(const struct shell *sh, + enum bt_audio_active_state state) +{ + shell_print(sh, "\tAudio active state: %s (0x%02X)", + state == BT_AUDIO_ACTIVE_STATE_ENABLED ? "enabled" : "disabled", + (uint8_t)state); +} + +static inline void print_codec_meta_bcast_audio_immediate_rend_flag(const struct shell *sh) +{ + shell_print(sh, "\tBroadcast audio immediate rendering flag set"); +} + +static inline void print_codec_meta_extended(const struct shell *sh, const uint8_t *extended_meta, + size_t extended_meta_len) +{ + shell_fprintf(sh, SHELL_NORMAL, "\tExtended metadata:\n\t\t"); + + for (uint8_t i = 0U; i < extended_meta_len; i++) { + shell_fprintf(sh, SHELL_NORMAL, "%c", (char)extended_meta[i]); + } + + shell_fprintf(sh, SHELL_NORMAL, "\n"); +} + +static inline void print_codec_meta_vendor(const struct shell *sh, const uint8_t *vendor_meta, + size_t vender_meta_len) +{ + shell_fprintf(sh, SHELL_NORMAL, "\tVender metadata:\n\t\t"); + + for (uint8_t i = 0U; i < vender_meta_len; i++) { + shell_fprintf(sh, SHELL_NORMAL, "%c", (char)vendor_meta[i]); + } + + shell_fprintf(sh, SHELL_NORMAL, "\n"); +} + static inline char *codec_cap_freq_bit_to_str(enum bt_audio_codec_cap_freq freq) { switch (freq) { @@ -335,7 +531,10 @@ static inline void print_codec_cap(const struct shell *sh, codec_cap->vid); #if CONFIG_BT_AUDIO_CODEC_CAP_MAX_DATA_SIZE > 0 - if (codec_cap->id == BT_HCI_CODING_FORMAT_LC3) { + shell_print(sh, "Codec specific capabilities:"); + if (codec_cap->data_len == 0U) { + shell_print(sh, "\tNone"); + } else if (codec_cap->id == BT_HCI_CODING_FORMAT_LC3) { struct bt_audio_codec_octets_per_codec_frame codec_frame; int ret; @@ -369,7 +568,63 @@ static inline void print_codec_cap(const struct shell *sh, #endif /* CONFIG_BT_AUDIO_CODEC_CAP_MAX_DATA_SIZE > 0 */ #if CONFIG_BT_AUDIO_CODEC_CAP_MAX_METADATA_SIZE > 0 - print_ltv_array(sh, "meta", codec_cap->meta, codec_cap->meta_len); + shell_print(sh, "Codec specific metadata:"); + if (codec_cap->meta_len == 0U) { + shell_print(sh, "\tNone"); + } else { + const uint8_t *data; + int ret; + + ret = bt_audio_codec_cap_meta_get_pref_context(codec_cap); + if (ret >= 0) { + print_codec_meta_pref_context(sh, (enum bt_audio_context)ret); + } + + ret = bt_audio_codec_cap_meta_get_stream_context(codec_cap); + if (ret >= 0) { + print_codec_meta_stream_context(sh, (enum bt_audio_context)ret); + } + + ret = bt_audio_codec_cap_meta_get_program_info(codec_cap, &data); + if (ret >= 0) { + print_codec_meta_program_info(sh, data, (uint8_t)ret); + } + + ret = bt_audio_codec_cap_meta_get_stream_lang(codec_cap); + if (ret >= 0) { + print_codec_meta_language(sh, (uint32_t)ret); + } + + ret = bt_audio_codec_cap_meta_get_ccid_list(codec_cap, &data); + if (ret >= 0) { + print_codec_meta_ccid_list(sh, data, (uint8_t)ret); + } + + ret = bt_audio_codec_cap_meta_get_parental_rating(codec_cap); + if (ret >= 0) { + print_codec_meta_parental_rating(sh, (enum bt_audio_parental_rating)ret); + } + + ret = bt_audio_codec_cap_meta_get_audio_active_state(codec_cap); + if (ret >= 0) { + print_codec_meta_audio_active_state(sh, (enum bt_audio_active_state)ret); + } + + ret = bt_audio_codec_cap_meta_get_bcast_audio_immediate_rend_flag(codec_cap); + if (ret >= 0) { + print_codec_meta_bcast_audio_immediate_rend_flag(sh); + } + + ret = bt_audio_codec_cap_meta_get_extended(codec_cap, &data); + if (ret >= 0) { + print_codec_meta_extended(sh, data, (uint8_t)ret); + } + + ret = bt_audio_codec_cap_meta_get_vendor(codec_cap, &data); + if (ret >= 0) { + print_codec_meta_vendor(sh, data, (uint8_t)ret); + } + } #endif /* CONFIG_BT_AUDIO_CODEC_CAP_MAX_METADATA_SIZE > 0 */ } @@ -486,7 +741,10 @@ static inline void print_codec_cfg(const struct shell *sh, codec_cfg->cid, codec_cfg->vid, codec_cfg->data_len); #if CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 - if (codec_cfg->id == BT_HCI_CODING_FORMAT_LC3) { + shell_print(sh, "Codec specific configuration:"); + if (codec_cfg->data_len == 0U) { + shell_print(sh, "\tNone"); + } else if (codec_cfg->id == BT_HCI_CODING_FORMAT_LC3) { enum bt_audio_location chan_allocation; int ret; @@ -520,7 +778,63 @@ static inline void print_codec_cfg(const struct shell *sh, #endif /* CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 */ #if CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE > 0 - print_ltv_array(sh, "meta", codec_cfg->meta, codec_cfg->meta_len); + shell_print(sh, "Codec specific metadata:"); + if (codec_cfg->meta_len == 0U) { + shell_print(sh, "\tNone"); + } else { + const uint8_t *data; + int ret; + + ret = bt_audio_codec_cfg_meta_get_pref_context(codec_cfg); + if (ret >= 0) { + print_codec_meta_pref_context(sh, (enum bt_audio_context)ret); + } + + ret = bt_audio_codec_cfg_meta_get_stream_context(codec_cfg); + if (ret >= 0) { + print_codec_meta_stream_context(sh, (enum bt_audio_context)ret); + } + + ret = bt_audio_codec_cfg_meta_get_program_info(codec_cfg, &data); + if (ret >= 0) { + print_codec_meta_program_info(sh, data, (uint8_t)ret); + } + + ret = bt_audio_codec_cfg_meta_get_stream_lang(codec_cfg); + if (ret >= 0) { + print_codec_meta_language(sh, (uint32_t)ret); + } + + ret = bt_audio_codec_cfg_meta_get_ccid_list(codec_cfg, &data); + if (ret >= 0) { + print_codec_meta_ccid_list(sh, data, (uint8_t)ret); + } + + ret = bt_audio_codec_cfg_meta_get_parental_rating(codec_cfg); + if (ret >= 0) { + print_codec_meta_parental_rating(sh, (enum bt_audio_parental_rating)ret); + } + + ret = bt_audio_codec_cfg_meta_get_audio_active_state(codec_cfg); + if (ret >= 0) { + print_codec_meta_audio_active_state(sh, (enum bt_audio_active_state)ret); + } + + ret = bt_audio_codec_cfg_meta_get_bcast_audio_immediate_rend_flag(codec_cfg); + if (ret >= 0) { + print_codec_meta_bcast_audio_immediate_rend_flag(sh); + } + + ret = bt_audio_codec_cfg_meta_get_extended(codec_cfg, &data); + if (ret >= 0) { + print_codec_meta_extended(sh, data, (uint8_t)ret); + } + + ret = bt_audio_codec_cfg_meta_get_vendor(codec_cfg, &data); + if (ret >= 0) { + print_codec_meta_vendor(sh, data, (uint8_t)ret); + } + } #endif /* CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE > 0 */ } @@ -546,7 +860,15 @@ static inline bool print_base_subgroup_bis_cb(const struct bt_bap_base_subgroup_ shell_print(ctx_shell, "\t\tBIS index: 0x%02X", bis->index); /* Print CC data */ if (codec_id->id == BT_HCI_CODING_FORMAT_LC3) { - print_ltv_array(ctx_shell, "\t\tdata", bis->data, bis->data_len); + struct bt_audio_codec_cfg codec_cfg; + int err; + + err = bt_bap_base_subgroup_bis_codec_to_codec_cfg(bis, &codec_cfg); + if (err == 0) { + print_codec_cfg(ctx_shell, &codec_cfg); + } else { + print_ltv_array(ctx_shell, "\t\tdata", bis->data, bis->data_len); + } } else { /* If not LC3, we cannot assume it's LTV */ shell_hexdump(ctx_shell, bis->data, bis->data_len); } @@ -558,6 +880,7 @@ static inline bool print_base_subgroup_cb(const struct bt_bap_base_subgroup *sub void *user_data) { struct bt_bap_base_codec_id codec_id; + struct bt_audio_codec_cfg codec_cfg; uint8_t *data; int ret; @@ -577,23 +900,28 @@ static inline bool print_base_subgroup_cb(const struct bt_bap_base_subgroup *sub return false; } - /* Print CC data */ - if (codec_id.id == BT_HCI_CODING_FORMAT_LC3) { - print_ltv_array(ctx_shell, "\tdata", data, (uint8_t)ret); - } else { /* If not LC3, we cannot assume it's LTV */ - shell_hexdump(ctx_shell, data, (uint8_t)ret); - } + ret = bt_bap_base_subgroup_codec_to_codec_cfg(subgroup, &codec_cfg); + if (ret == 0) { + print_codec_cfg(ctx_shell, &codec_cfg); + } else { + /* Print CC data */ + if (codec_id.id == BT_HCI_CODING_FORMAT_LC3) { + print_ltv_array(ctx_shell, "\tdata", data, (uint8_t)ret); + } else { /* If not LC3, we cannot assume it's LTV */ + shell_hexdump(ctx_shell, data, (uint8_t)ret); + } - ret = bt_bap_base_get_subgroup_codec_meta(subgroup, &data); - if (ret < 0) { - return false; - } + ret = bt_bap_base_get_subgroup_codec_meta(subgroup, &data); + if (ret < 0) { + return false; + } - /* Print metadata */ - if (codec_id.id == BT_HCI_CODING_FORMAT_LC3) { - print_ltv_array(ctx_shell, "\tdata", data, (uint8_t)ret); - } else { /* If not LC3, we cannot assume it's LTV */ - shell_hexdump(ctx_shell, data, (uint8_t)ret); + /* Print metadata */ + if (codec_id.id == BT_HCI_CODING_FORMAT_LC3) { + print_ltv_array(ctx_shell, "\tdata", data, (uint8_t)ret); + } else { /* If not LC3, we cannot assume it's LTV */ + shell_hexdump(ctx_shell, data, (uint8_t)ret); + } } ret = bt_bap_base_subgroup_foreach_bis(subgroup, print_base_subgroup_bis_cb, &codec_id); From 826ac0755b412a74d6e1a7f4cdd659b57cae0e8c Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Wed, 24 Jan 2024 10:34:23 +0100 Subject: [PATCH 0392/2402] bluetooth: audio: shell: Improve indentation when printing codecs Codecs can be printed at different levels: level 0: Generic and unicast level 1: subgroup codec configs level 2: BIS codec configs This commit ensures that the indentation level is correctly increase based on where the codec configuration data is printed. This also updates the documentation for the BAP shell. Signed-off-by: Emil Gydesen --- doc/connectivity/bluetooth/api/shell/bap.rst | 176 +++++---- subsys/bluetooth/audio/shell/audio.h | 391 ++++++++++++------- subsys/bluetooth/audio/shell/bap.c | 10 +- 3 files changed, 355 insertions(+), 222 deletions(-) diff --git a/doc/connectivity/bluetooth/api/shell/bap.rst b/doc/connectivity/bluetooth/api/shell/bap.rst index ea0d3d13913..8d01943eb3b 100644 --- a/doc/connectivity/bluetooth/api/shell/bap.rst +++ b/doc/connectivity/bluetooth/api/shell/bap.rst @@ -164,54 +164,52 @@ Example Broadcast Sink ********************** Scan for and establish a broadcast sink stream. -The command :code:`bap create_broadcast_sink 0xEF6716` will either use existing periodic advertising -sync (if exist) or start scanning and sync to the periodic advertising before syncing to the BIG. +The command :code:`bap create_broadcast_sink` will either use existing periodic advertising +sync (if exist) or start scanning and sync to the periodic advertising with the provided broadcast +ID before syncing to the BIG. .. code-block:: console uart:~$ bap init - uart:~$ bap broadcast_scan on - Found broadcaster with ID 0xEF6716 and addr 3D:A5:F9:35:0B:19 (random) and sid 0x00 uart:~$ bap create_broadcast_sink 0xEF6716 + No PA sync available, starting scanning for broadcast_id + Found broadcaster with ID 0xEF6716 and addr 03:47:95:75:C0:08 (random) and sid 0x00 Attempting to PA sync to the broadcaster PA synced to broadcast with broadcast ID 0xEF6716 Attempting to sync to the BIG - Received BASE from sink 0x20031fac: + Received BASE from sink 0x20019080: Presentation delay: 40000 - Subgroup count: 2 - Subgroup[0]: - codec cfg id 0x06 cid 0x0000 vid 0x0000 - data_count 4 - data #0: type 0x01 len 1 - 00000000: 03 |. | - data #1: type 0x02 len 1 - 00000000: 01 |. | - data #2: type 0x03 len 4 - 00000000: 01 00 00 00 |.... | - data #3: type 0x04 len 2 - 00000000: 28 00 |(. | - meta_count 4 - meta #0: type 0x02 len 2 - 00000000: 01 00 |.. | - BIS[0] index 0x01 - Subgroup[1]: - codec cfg id 0x06 cid 0x0000 vid 0x0000 - data_count 4 - data #0: type 0x01 len 1 - 00000000: 03 |. | - data #1: type 0x02 len 1 - 00000000: 01 |. | - data #2: type 0x03 len 4 - 00000000: 01 00 00 00 |.... | - data #3: type 0x04 len 2 - 00000000: 28 00 |(. | - meta_count 4 - meta #0: type 0x02 len 2 - 00000000: 01 00 |.. | - BIS[1] index 0x01 - [0]: 0x01 - [1]: 0x01 - Possible indexes: 0x01 0x01 + Subgroup count: 1 + Subgroup 0x20024182: + Codec Format: 0x06 + Company ID : 0x0000 + Vendor ID : 0x0000 + codec cfg id 0x06 cid 0x0000 vid 0x0000 count 16 + Codec specific configuration: + Sampling frequency: 16000 Hz (3) + Frame duration: 10000 us (1) + Channel allocation: + Front left (0x00000001) + Front right (0x00000002) + Octets per codec frame: 40 + Codec specific metadata: + Streaming audio contexts: + Unspecified (0x0001) + BIS index: 0x01 + codec cfg id 0x06 cid 0x0000 vid 0x0000 count 6 + Codec specific configuration: + Channel allocation: + Front left (0x00000001) + Codec specific metadata: + None + BIS index: 0x02 + codec cfg id 0x06 cid 0x0000 vid 0x0000 count 6 + Codec specific configuration: + Channel allocation: + Front right (0x00000002) + Codec specific metadata: + None + Possible indexes: 0x01 0x02 Sink 0x20019110 is ready to sync without encryption uart:~$ bap sync_broadcast 0x01 @@ -280,20 +278,35 @@ characteristics representing remote endpoints. Exchange successful uart:~$ bap discover [type: sink, source] uart:~$ bap discover sink - cap 0x8175940 type 0x01 - codec 0x06 cid 0x0000 vid 0x0000 count 4 - data #0: type 0x01 len 1 - 00000000: 3f |? | - data #1: type 0x02 len 1 - 00000000: 03 |. | - data #2: type 0x03 len 1 - 00000000: 03 |. | - data #3: type 0x04 len 4 - 00000000: 1e 00 f0 00 |.... | - meta #0: type 0x01 len 2 - 00000000: 06 00 |.. | - meta #1: type 0x02 len 2 - 00000000: ff 03 |.. | + conn 0x2000b168: codec_cap 0x2001f8ec dir 0x02 + codec cap id 0x06 cid 0x0000 vid 0x0000 + Codec specific capabilities: + Supported sampling frequencies: + 8000 Hz (0x0001) + 11025 Hz (0x0002) + 16000 Hz (0x0004) + 22050 Hz (0x0008) + 24000 Hz (0x0010) + 32000 Hz (0x0020) + 44100 Hz (0x0040) + 48000 Hz (0x0080) + 88200 Hz (0x0100) + 96000 Hz (0x0200) + 176400 Hz (0x0400) + 192000 Hz (0x0800) + 384000 Hz (0x1000) + Supported frame durations: + 10 ms (0x02) + Supported channel counts: + 1 channel (0x01) + Supported octets per codec frame counts: + Min: 40 + Max: 120 + Supported max codec frames per SDU: 1 + Codec capabilities metadata: + Preferred audio contexts: + Converstation (0x0002) + Media (0x0004) ep 0x81754e0 ep 0x81755d4 Discover complete: err 0 @@ -329,29 +342,34 @@ any stream previously configured. [vendor ]] uart:~$ bap preset sink 16_2_1 - codec 0x06 cid 0x0000 vid 0x0000 count 4 - data #0: type 0x01 len 1 - data #1: type 0x02 len 1 - data #2: type 0x03 len 4 - 00000000: 01 00 00 |... | - data #3: type 0x04 len 2 - 00000000: 28 |( | - meta #0: type 0x02 len 2 - 00000000: 06 |. | + codec cfg id 0x06 cid 0x0000 vid 0x0000 count 16 + Codec specific configuration: + Sampling frequency: 16000 Hz (3) + Frame duration: 10000 us (1) + Channel allocation: + Front left (0x00000001) + Front right (0x00000002) + Octets per codec frame: 40 + Codec specific metadata: + Streaming audio contexts: + Game (0x0008) QoS: interval 10000 framing 0x00 phy 0x02 sdu 40 rtn 2 latency 10 pd 40000 uart:~$ bap preset sink 32_2_1 32_2_1 - codec 0x06 cid 0x0000 vid 0x0000 count 4 - data #0: type 0x01 len 1 - data #1: type 0x02 len 1 - data #2: type 0x03 len 4 - 00000000: 01 00 00 |... | - data #3: type 0x04 len 2 - 00000000: 50 |P | - meta #0: type 0x02 len 2 - 00000000: 06 |. | - QoS: interval 10000 framing 0x00 phy 0x02 sdu 80 rtn 2 latency 10 pd 40000 + codec cfg id 0x06 cid 0x0000 vid 0x0000 count 16 + Codec specific configuration: + Sampling frequency: 32000 Hz (6) + Frame duration: 10000 us (1) + Channel allocation: + Front left (0x00000001) + Front right (0x00000002) + Octets per codec frame: 80 + Codec specific metadata: + Streaming audio contexts: + Game (0x0008) + QoS: interval 10000 framing 0x00 phy 0x02 sdu 80 rtn 2 latency 10 pd 40000 + Configure preset **************** @@ -427,19 +445,9 @@ or in case it is omitted the default preset is used. uart:~$ bap config [loc ] [preset ] uart:~$ bap config sink 0 - ASE Codec Config: conn 0x8173800 ep 0x81754e0 cap 0x816a360 - codec 0x06 cid 0x0000 vid 0x0000 count 3 - data #0: type 0x01 len 1 - 00000000: 02 |. | - data #1: type 0x02 len 1 - 00000000: 01 |. | - data #2: type 0x04 len 2 - 00000000: 28 00 |(. | - meta #0: type 0x02 len 2 - 00000000: 02 00 |.. | - ASE Codec Config stream 0x8179e60 - Default ase: 1 + Setting location to 0x00000000 ASE config: preset 16_2_1 + stream 0x2000df70 config operation rsp_code 0 reason 0 Configure Stream QoS ******************** diff --git a/subsys/bluetooth/audio/shell/audio.h b/subsys/bluetooth/audio/shell/audio.h index ba185bf0326..78d67b873df 100644 --- a/subsys/bluetooth/audio/shell/audio.h +++ b/subsys/bluetooth/audio/shell/audio.h @@ -22,6 +22,8 @@ #include "shell/bt.h" +#define SHELL_PRINT_INDENT_LEVEL_SIZE 2 + extern struct bt_csip_set_member_svc_inst *svc_inst; ssize_t audio_ad_data_add(struct bt_data *data, const size_t data_size, const bool discoverable, @@ -168,30 +170,38 @@ static inline void print_qos(const struct shell *sh, const struct bt_audio_codec struct print_ltv_info { const struct shell *sh; - const char *str; + size_t indent; size_t cnt; }; static bool print_ltv_elem(struct bt_data *data, void *user_data) { struct print_ltv_info *ltv_info = user_data; + const size_t elem_indent = ltv_info->indent += SHELL_PRINT_INDENT_LEVEL_SIZE; + + shell_print(ltv_info->sh, "%*s#%zu: type 0x%02x value_len %u", ltv_info->indent, "", + ltv_info->cnt, data->type, data->data_len); + + shell_fprintf(ltv_info->sh, SHELL_NORMAL, "%*s", elem_indent, ""); + + for (uint8_t i = 0U; i < data->data_len; i++) { + shell_fprintf(ltv_info->sh, SHELL_NORMAL, "%02X", data->data[i]); + } - shell_print(ltv_info->sh, "%s #%zu: type 0x%02x value_len %u", ltv_info->str, ltv_info->cnt, - data->type, data->data_len); - shell_hexdump(ltv_info->sh, data->data, data->data_len); + shell_fprintf(ltv_info->sh, SHELL_NORMAL, "\n"); ltv_info->cnt++; return true; } -static void print_ltv_array(const struct shell *sh, const char *str, const uint8_t *ltv_data, +static void print_ltv_array(const struct shell *sh, size_t indent, const uint8_t *ltv_data, size_t ltv_data_len) { struct print_ltv_info ltv_info = { .sh = sh, - .str = str, .cnt = 0U, + .indent = indent, }; bt_audio_data_parse(ltv_data, ltv_data_len, print_ltv_elem, <v_info); @@ -231,42 +241,51 @@ static inline char *context_bit_to_str(enum bt_audio_context context) } } -static inline void print_codec_meta_pref_context(const struct shell *sh, +static inline void print_codec_meta_pref_context(const struct shell *sh, size_t indent, enum bt_audio_context context) { - shell_print(sh, "\tPreferred audio contexts:"); + shell_print(sh, "%*sPreferred audio contexts:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; /* There can be up to 16 bits set in the field */ for (size_t i = 0U; i < 16; i++) { const uint16_t bit_val = BIT(i); if (context & bit_val) { - shell_print(sh, "\t\t%s (0x%04X)", context_bit_to_str(bit_val), bit_val); + shell_print(sh, "%*s%s (0x%04X)", indent, "", context_bit_to_str(bit_val), + bit_val); } } } -static inline void print_codec_meta_stream_context(const struct shell *sh, +static inline void print_codec_meta_stream_context(const struct shell *sh, size_t indent, enum bt_audio_context context) { - shell_print(sh, "\tStreaming audio contexts:"); + shell_print(sh, "%*sStreaming audio contexts:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; /* There can be up to 16 bits set in the field */ for (size_t i = 0U; i < 16; i++) { const uint16_t bit_val = BIT(i); if (context & bit_val) { - shell_print(sh, "\t\t%s (0x%04X)", context_bit_to_str(bit_val), bit_val); + shell_print(sh, "%*s%s (0x%04X)", indent, "", context_bit_to_str(bit_val), + bit_val); } } } -static inline void print_codec_meta_program_info(const struct shell *sh, +static inline void print_codec_meta_program_info(const struct shell *sh, size_t indent, const uint8_t *program_info, uint8_t program_info_len) { - shell_fprintf(sh, SHELL_NORMAL, "\tProgram info:\n\t\t"); + shell_print(sh, "%*sProgram info:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; + shell_fprintf(sh, SHELL_NORMAL, "%*s", indent, ""); for (uint8_t i = 0U; i < program_info_len; i++) { shell_fprintf(sh, SHELL_NORMAL, "%c", (char)program_info[i]); } @@ -274,25 +293,27 @@ static inline void print_codec_meta_program_info(const struct shell *sh, shell_fprintf(sh, SHELL_NORMAL, "\n"); } -static inline void print_codec_meta_language(const struct shell *sh, uint32_t stream_lang) +static inline void print_codec_meta_language(const struct shell *sh, size_t indent, + uint32_t stream_lang) { uint8_t lang_array[3]; sys_put_be24(stream_lang, lang_array); - shell_print(sh, "\tLanguage: %c%c%c", (char)lang_array[0], (char)lang_array[1], + shell_print(sh, "%*sLanguage: %c%c%c", indent, "", (char)lang_array[0], (char)lang_array[1], (char)lang_array[2]); } -static inline void print_codec_meta_ccid_list(const struct shell *sh, const uint8_t *ccid_list, - uint8_t ccid_list_len) +static inline void print_codec_meta_ccid_list(const struct shell *sh, size_t indent, + const uint8_t *ccid_list, uint8_t ccid_list_len) { - shell_print(sh, "\tCCID list:\n"); + shell_print(sh, "%*sCCID list:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; /* There can be up to 16 bits set in the field */ for (uint8_t i = 0U; i < ccid_list_len; i++) { - - shell_print(sh, "\t\t0x%02X ", ccid_list[i]); + shell_print(sh, "%*s0x%02X ", indent, "", ccid_list[i]); } } @@ -336,18 +357,22 @@ static inline char *parental_rating_to_str(enum bt_audio_parental_rating parenta } } -static inline void print_codec_meta_parental_rating(const struct shell *sh, +static inline void print_codec_meta_parental_rating(const struct shell *sh, size_t indent, enum bt_audio_parental_rating parental_rating) { - shell_print(sh, "\tRating: %s (0x%02X)", parental_rating_to_str(parental_rating), - (uint8_t)parental_rating); + shell_print(sh, "%*sRating: %s (0x%02X)", indent, "", + parental_rating_to_str(parental_rating), (uint8_t)parental_rating); } -static inline void print_codec_meta_program_info_uri(const struct shell *sh, +static inline void print_codec_meta_program_info_uri(const struct shell *sh, size_t indent, const uint8_t *program_info_uri, uint8_t program_info_uri_len) { - shell_fprintf(sh, SHELL_NORMAL, "\tProgram info URI:\n\t\t"); + shell_print(sh, "%*sProgram info URI:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; + + shell_fprintf(sh, SHELL_NORMAL, "%*s", indent, ""); for (uint8_t i = 0U; i < program_info_uri_len; i++) { shell_fprintf(sh, SHELL_NORMAL, "%c", (char)program_info_uri[i]); @@ -356,38 +381,47 @@ static inline void print_codec_meta_program_info_uri(const struct shell *sh, shell_fprintf(sh, SHELL_NORMAL, "\n"); } -static inline void print_codec_meta_audio_active_state(const struct shell *sh, +static inline void print_codec_meta_audio_active_state(const struct shell *sh, size_t indent, enum bt_audio_active_state state) { - shell_print(sh, "\tAudio active state: %s (0x%02X)", + shell_print(sh, "%*sAudio active state: %s (0x%02X)", indent, "", state == BT_AUDIO_ACTIVE_STATE_ENABLED ? "enabled" : "disabled", (uint8_t)state); } -static inline void print_codec_meta_bcast_audio_immediate_rend_flag(const struct shell *sh) +static inline void print_codec_meta_bcast_audio_immediate_rend_flag(const struct shell *sh, + size_t indent) { - shell_print(sh, "\tBroadcast audio immediate rendering flag set"); + shell_print(sh, "%*sBroadcast audio immediate rendering flag set", indent, ""); } -static inline void print_codec_meta_extended(const struct shell *sh, const uint8_t *extended_meta, - size_t extended_meta_len) +static inline void print_codec_meta_extended(const struct shell *sh, size_t indent, + const uint8_t *extended_meta, size_t extended_meta_len) { - shell_fprintf(sh, SHELL_NORMAL, "\tExtended metadata:\n\t\t"); + shell_print(sh, "%*sExtended metadata:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; + + shell_fprintf(sh, SHELL_NORMAL, "%*s", indent, ""); for (uint8_t i = 0U; i < extended_meta_len; i++) { - shell_fprintf(sh, SHELL_NORMAL, "%c", (char)extended_meta[i]); + shell_fprintf(sh, SHELL_NORMAL, "%u", (uint8_t)extended_meta[i]); } shell_fprintf(sh, SHELL_NORMAL, "\n"); } -static inline void print_codec_meta_vendor(const struct shell *sh, const uint8_t *vendor_meta, - size_t vender_meta_len) +static inline void print_codec_meta_vendor(const struct shell *sh, size_t indent, + const uint8_t *vendor_meta, size_t vender_meta_len) { - shell_fprintf(sh, SHELL_NORMAL, "\tVender metadata:\n\t\t"); + shell_print(sh, "%*sVendor metadata:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; + + shell_fprintf(sh, SHELL_NORMAL, "%*s", indent, ""); for (uint8_t i = 0U; i < vender_meta_len; i++) { - shell_fprintf(sh, SHELL_NORMAL, "%c", (char)vendor_meta[i]); + shell_fprintf(sh, SHELL_NORMAL, "%u", (uint8_t)vendor_meta[i]); } shell_fprintf(sh, SHELL_NORMAL, "\n"); @@ -427,16 +461,19 @@ static inline char *codec_cap_freq_bit_to_str(enum bt_audio_codec_cap_freq freq) } } -static inline void print_codec_cap_freq(const struct shell *sh, enum bt_audio_codec_cap_freq freq) +static inline void print_codec_cap_freq(const struct shell *sh, size_t indent, + enum bt_audio_codec_cap_freq freq) { - shell_print(sh, "\tSupported sampling frequencies:"); + shell_print(sh, "%*sSupported sampling frequencies:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; /* There can be up to 16 bits set in the field */ for (size_t i = 0; i < 16; i++) { const uint16_t bit_val = BIT(i); if (freq & bit_val) { - shell_print(sh, "\t\t%s (0x%04X)", codec_cap_freq_bit_to_str(bit_val), - bit_val); + shell_print(sh, "%*s%s (0x%04X)", indent, "", + codec_cap_freq_bit_to_str(bit_val), bit_val); } } } @@ -457,17 +494,19 @@ static inline char *codec_cap_frame_dur_bit_to_str(enum bt_audio_codec_cap_frame } } -static inline void print_codec_cap_frame_dur(const struct shell *sh, +static inline void print_codec_cap_frame_dur(const struct shell *sh, size_t indent, enum bt_audio_codec_cap_frame_dur frame_dur) { - shell_print(sh, "\tSupported frame durations:"); + shell_print(sh, "%*sSupported frame durations:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; /* There can be up to 8 bits set in the field */ for (size_t i = 0; i < 8; i++) { const uint8_t bit_val = BIT(i); if (frame_dur & bit_val) { - shell_print(sh, "\t\t%s (0x%02X)", codec_cap_frame_dur_bit_to_str(bit_val), - bit_val); + shell_print(sh, "%*s%s (0x%02X)", indent, "", + codec_cap_frame_dur_bit_to_str(bit_val), bit_val); } } } @@ -496,149 +535,176 @@ static inline char *codec_cap_chan_count_bit_to_str(enum bt_audio_codec_cap_chan } } -static inline void print_codec_cap_chan_count(const struct shell *sh, +static inline void print_codec_cap_chan_count(const struct shell *sh, size_t indent, enum bt_audio_codec_cap_chan_count chan_count) { - shell_print(sh, "\tSupported channel counts:"); + shell_print(sh, "%*sSupported channel counts:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; /* There can be up to 8 bits set in the field */ for (size_t i = 0; i < 8; i++) { const uint8_t bit_val = BIT(i); if (chan_count & bit_val) { - shell_print(sh, "\t\t%s (0x%02X)", codec_cap_chan_count_bit_to_str(bit_val), - bit_val); + shell_print(sh, "%*s%s (0x%02X)", indent, "", + codec_cap_chan_count_bit_to_str(bit_val), bit_val); } } } static inline void print_codec_cap_octets_per_codec_frame( - const struct shell *sh, const struct bt_audio_codec_octets_per_codec_frame *codec_frame) + const struct shell *sh, size_t indent, + const struct bt_audio_codec_octets_per_codec_frame *codec_frame) { - shell_print(sh, "\tSupported octets per codec frame counts:\n\t\tMin: %u\n\t\tMax: %u", - codec_frame->min, codec_frame->max); + shell_print(sh, "%*sSupported octets per codec frame counts:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; + shell_print(sh, "%*sMin: %u", indent, "", codec_frame->min); + shell_print(sh, "%*sMax: %u", indent, "", codec_frame->max); } -static inline void print_codec_cap_max_codec_frames_per_sdu(const struct shell *sh, +static inline void print_codec_cap_max_codec_frames_per_sdu(const struct shell *sh, size_t indent, uint8_t codec_frames_per_sdu) { - shell_print(sh, "\tSupported max codec frames per SDU: %u", codec_frames_per_sdu); + shell_print(sh, "%*sSupported max codec frames per SDU: %u", indent, "", + codec_frames_per_sdu); } -static inline void print_codec_cap(const struct shell *sh, +static inline void print_codec_cap(const struct shell *sh, size_t indent, const struct bt_audio_codec_cap *codec_cap) { - shell_print(sh, "codec cap id 0x%02x cid 0x%04x vid 0x%04x", codec_cap->id, codec_cap->cid, - codec_cap->vid); + shell_print(sh, "%*scodec cap id 0x%02x cid 0x%04x vid 0x%04x", indent, "", codec_cap->id, + codec_cap->cid, codec_cap->vid); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; #if CONFIG_BT_AUDIO_CODEC_CAP_MAX_DATA_SIZE > 0 - shell_print(sh, "Codec specific capabilities:"); + shell_print(sh, "%*sCodec specific capabilities:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; if (codec_cap->data_len == 0U) { - shell_print(sh, "\tNone"); + shell_print(sh, "%*sNone", indent, ""); } else if (codec_cap->id == BT_HCI_CODING_FORMAT_LC3) { struct bt_audio_codec_octets_per_codec_frame codec_frame; int ret; ret = bt_audio_codec_cap_get_freq(codec_cap); if (ret >= 0) { - print_codec_cap_freq(sh, (enum bt_audio_codec_cap_freq)ret); + print_codec_cap_freq(sh, indent, (enum bt_audio_codec_cap_freq)ret); } ret = bt_audio_codec_cap_get_frame_dur(codec_cap); if (ret >= 0) { - print_codec_cap_frame_dur(sh, (enum bt_audio_codec_cap_frame_dur)ret); + print_codec_cap_frame_dur(sh, indent, + (enum bt_audio_codec_cap_frame_dur)ret); } ret = bt_audio_codec_cap_get_supported_audio_chan_counts(codec_cap); if (ret >= 0) { - print_codec_cap_chan_count(sh, (enum bt_audio_codec_cap_chan_count)ret); + print_codec_cap_chan_count(sh, indent, + (enum bt_audio_codec_cap_chan_count)ret); } ret = bt_audio_codec_cap_get_octets_per_frame(codec_cap, &codec_frame); if (ret >= 0) { - print_codec_cap_octets_per_codec_frame(sh, &codec_frame); + print_codec_cap_octets_per_codec_frame(sh, indent, &codec_frame); } ret = bt_audio_codec_cap_get_max_codec_frames_per_sdu(codec_cap); if (ret >= 0) { - print_codec_cap_max_codec_frames_per_sdu(sh, (uint8_t)ret); + print_codec_cap_max_codec_frames_per_sdu(sh, indent, (uint8_t)ret); } } else { /* If not LC3, we cannot assume it's LTV */ - shell_hexdump(sh, codec_cap->data, codec_cap->data_len); + shell_fprintf(sh, SHELL_NORMAL, "%*s", indent, ""); + + for (uint8_t i = 0U; i < codec_cap->data_len; i++) { + shell_fprintf(sh, SHELL_NORMAL, "%*s%02X", indent, "", codec_cap->data[i]); + } + + shell_fprintf(sh, SHELL_NORMAL, "\n"); } + + /* Reduce for metadata*/ + indent -= SHELL_PRINT_INDENT_LEVEL_SIZE; #endif /* CONFIG_BT_AUDIO_CODEC_CAP_MAX_DATA_SIZE > 0 */ #if CONFIG_BT_AUDIO_CODEC_CAP_MAX_METADATA_SIZE > 0 - shell_print(sh, "Codec specific metadata:"); + shell_print(sh, "%*sCodec capabilities metadata:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; if (codec_cap->meta_len == 0U) { - shell_print(sh, "\tNone"); + shell_print(sh, "%*sNone", indent, ""); } else { const uint8_t *data; int ret; ret = bt_audio_codec_cap_meta_get_pref_context(codec_cap); if (ret >= 0) { - print_codec_meta_pref_context(sh, (enum bt_audio_context)ret); + print_codec_meta_pref_context(sh, indent, (enum bt_audio_context)ret); } ret = bt_audio_codec_cap_meta_get_stream_context(codec_cap); if (ret >= 0) { - print_codec_meta_stream_context(sh, (enum bt_audio_context)ret); + print_codec_meta_stream_context(sh, indent, (enum bt_audio_context)ret); } ret = bt_audio_codec_cap_meta_get_program_info(codec_cap, &data); if (ret >= 0) { - print_codec_meta_program_info(sh, data, (uint8_t)ret); + print_codec_meta_program_info(sh, indent, data, (uint8_t)ret); } ret = bt_audio_codec_cap_meta_get_stream_lang(codec_cap); if (ret >= 0) { - print_codec_meta_language(sh, (uint32_t)ret); + print_codec_meta_language(sh, indent, (uint32_t)ret); } ret = bt_audio_codec_cap_meta_get_ccid_list(codec_cap, &data); if (ret >= 0) { - print_codec_meta_ccid_list(sh, data, (uint8_t)ret); + print_codec_meta_ccid_list(sh, indent, data, (uint8_t)ret); } ret = bt_audio_codec_cap_meta_get_parental_rating(codec_cap); if (ret >= 0) { - print_codec_meta_parental_rating(sh, (enum bt_audio_parental_rating)ret); + print_codec_meta_parental_rating(sh, indent, + (enum bt_audio_parental_rating)ret); } ret = bt_audio_codec_cap_meta_get_audio_active_state(codec_cap); if (ret >= 0) { - print_codec_meta_audio_active_state(sh, (enum bt_audio_active_state)ret); + print_codec_meta_audio_active_state(sh, indent, + (enum bt_audio_active_state)ret); } ret = bt_audio_codec_cap_meta_get_bcast_audio_immediate_rend_flag(codec_cap); if (ret >= 0) { - print_codec_meta_bcast_audio_immediate_rend_flag(sh); + print_codec_meta_bcast_audio_immediate_rend_flag(sh, indent); } ret = bt_audio_codec_cap_meta_get_extended(codec_cap, &data); if (ret >= 0) { - print_codec_meta_extended(sh, data, (uint8_t)ret); + print_codec_meta_extended(sh, indent, data, (uint8_t)ret); } ret = bt_audio_codec_cap_meta_get_vendor(codec_cap, &data); if (ret >= 0) { - print_codec_meta_vendor(sh, data, (uint8_t)ret); + print_codec_meta_vendor(sh, indent, data, (uint8_t)ret); } } #endif /* CONFIG_BT_AUDIO_CODEC_CAP_MAX_METADATA_SIZE > 0 */ } -static inline void print_codec_cfg_freq(const struct shell *sh, enum bt_audio_codec_cfg_freq freq) +static inline void print_codec_cfg_freq(const struct shell *sh, size_t indent, + enum bt_audio_codec_cfg_freq freq) { - shell_print(sh, "\tSampling frequency: %u Hz (%u)", - bt_audio_codec_cfg_freq_to_freq_hz(freq), freq); + shell_print(sh, "%*sSampling frequency: %u Hz (0x%04X)", indent, "", + bt_audio_codec_cfg_freq_to_freq_hz(freq), (uint16_t)freq); } -static inline void print_codec_cfg_frame_dur(const struct shell *sh, +static inline void print_codec_cfg_frame_dur(const struct shell *sh, size_t indent, enum bt_audio_codec_cfg_frame_dur frame_dur) { - shell_print(sh, "\tFrame duration: %u us (%u)", - bt_audio_codec_cfg_frame_dur_to_frame_dur_us(frame_dur), frame_dur); + shell_print(sh, "%*sFrame duration: %u us (0x%02X)", indent, "", + bt_audio_codec_cfg_frame_dur_to_frame_dur_us(frame_dur), (uint8_t)frame_dur); } static inline char *chan_location_bit_to_str(enum bt_audio_location chan_allocation) @@ -707,132 +773,152 @@ static inline char *chan_location_bit_to_str(enum bt_audio_location chan_allocat } } -static inline void print_codec_cfg_chan_allocation(const struct shell *sh, +static inline void print_codec_cfg_chan_allocation(const struct shell *sh, size_t indent, enum bt_audio_location chan_allocation) { - shell_print(sh, "\tChannel allocation:"); + shell_print(sh, "%*sChannel allocation:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; /* There can be up to 32 bits set in the field */ for (size_t i = 0; i < 32; i++) { const uint8_t bit_val = BIT(i); if (chan_allocation & bit_val) { - shell_print(sh, "\t\t%s (0x%08X)", chan_location_bit_to_str(bit_val), - bit_val); + shell_print(sh, "%*s%s (0x%08X)", indent, "", + chan_location_bit_to_str(bit_val), bit_val); } } } -static inline void print_codec_cfg_octets_per_frame(const struct shell *sh, +static inline void print_codec_cfg_octets_per_frame(const struct shell *sh, size_t indent, uint16_t octets_per_frame) { - shell_print(sh, "\tOctets per codec frame: %u", octets_per_frame); + shell_print(sh, "%*sOctets per codec frame: %u", indent, "", octets_per_frame); } -static inline void print_codec_cfg_frame_blocks_per_sdu(const struct shell *sh, +static inline void print_codec_cfg_frame_blocks_per_sdu(const struct shell *sh, size_t indent, uint8_t frame_blocks_per_sdu) { - shell_print(sh, "\tCodec frame blocks per SDU: %u", frame_blocks_per_sdu); + shell_print(sh, "%*sCodec frame blocks per SDU: %u", indent, "", frame_blocks_per_sdu); } -static inline void print_codec_cfg(const struct shell *sh, +static inline void print_codec_cfg(const struct shell *sh, size_t indent, const struct bt_audio_codec_cfg *codec_cfg) { - shell_print(sh, "codec cfg id 0x%02x cid 0x%04x vid 0x%04x count %u", codec_cfg->id, - codec_cfg->cid, codec_cfg->vid, codec_cfg->data_len); + shell_print(sh, "%*scodec cfg id 0x%02x cid 0x%04x vid 0x%04x count %u", indent, "", + codec_cfg->id, codec_cfg->cid, codec_cfg->vid, codec_cfg->data_len); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; #if CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 - shell_print(sh, "Codec specific configuration:"); + shell_print(sh, "%*sCodec specific configuration:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; if (codec_cfg->data_len == 0U) { - shell_print(sh, "\tNone"); + shell_print(sh, "%*sNone", indent, ""); } else if (codec_cfg->id == BT_HCI_CODING_FORMAT_LC3) { enum bt_audio_location chan_allocation; int ret; ret = bt_audio_codec_cfg_get_freq(codec_cfg); if (ret >= 0) { - print_codec_cfg_freq(sh, (enum bt_audio_codec_cfg_freq)ret); + print_codec_cfg_freq(sh, indent, (enum bt_audio_codec_cfg_freq)ret); } ret = bt_audio_codec_cfg_get_frame_dur(codec_cfg); if (ret >= 0) { - print_codec_cfg_frame_dur(sh, (enum bt_audio_codec_cfg_frame_dur)ret); + print_codec_cfg_frame_dur(sh, indent, + (enum bt_audio_codec_cfg_frame_dur)ret); } ret = bt_audio_codec_cfg_get_chan_allocation(codec_cfg, &chan_allocation); if (ret >= 0) { - print_codec_cfg_chan_allocation(sh, chan_allocation); + print_codec_cfg_chan_allocation(sh, indent, chan_allocation); } ret = bt_audio_codec_cfg_get_octets_per_frame(codec_cfg); if (ret >= 0) { - print_codec_cfg_octets_per_frame(sh, (uint16_t)ret); + print_codec_cfg_octets_per_frame(sh, indent, (uint16_t)ret); } ret = bt_audio_codec_cfg_get_frame_blocks_per_sdu(codec_cfg, false); if (ret >= 0) { - print_codec_cfg_frame_blocks_per_sdu(sh, (uint8_t)ret); + print_codec_cfg_frame_blocks_per_sdu(sh, indent, (uint8_t)ret); } } else { /* If not LC3, we cannot assume it's LTV */ - shell_hexdump(sh, codec_cfg->data, codec_cfg->data_len); + shell_fprintf(sh, SHELL_NORMAL, "%*s", indent, ""); + + for (uint8_t i = 0U; i < codec_cfg->data_len; i++) { + shell_fprintf(sh, SHELL_NORMAL, "%*s%02X", indent, "", codec_cfg->data[i]); + } + + shell_fprintf(sh, SHELL_NORMAL, "\n"); } + + /* Reduce for metadata*/ + indent -= SHELL_PRINT_INDENT_LEVEL_SIZE; #endif /* CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 */ #if CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE > 0 - shell_print(sh, "Codec specific metadata:"); + shell_print(sh, "%*sCodec specific metadata:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; if (codec_cfg->meta_len == 0U) { - shell_print(sh, "\tNone"); + shell_print(sh, "%*sNone", indent, ""); } else { const uint8_t *data; int ret; ret = bt_audio_codec_cfg_meta_get_pref_context(codec_cfg); if (ret >= 0) { - print_codec_meta_pref_context(sh, (enum bt_audio_context)ret); + print_codec_meta_pref_context(sh, indent, (enum bt_audio_context)ret); } ret = bt_audio_codec_cfg_meta_get_stream_context(codec_cfg); if (ret >= 0) { - print_codec_meta_stream_context(sh, (enum bt_audio_context)ret); + print_codec_meta_stream_context(sh, indent, (enum bt_audio_context)ret); } ret = bt_audio_codec_cfg_meta_get_program_info(codec_cfg, &data); if (ret >= 0) { - print_codec_meta_program_info(sh, data, (uint8_t)ret); + print_codec_meta_program_info(sh, indent, data, (uint8_t)ret); } ret = bt_audio_codec_cfg_meta_get_stream_lang(codec_cfg); if (ret >= 0) { - print_codec_meta_language(sh, (uint32_t)ret); + print_codec_meta_language(sh, indent, (uint32_t)ret); } ret = bt_audio_codec_cfg_meta_get_ccid_list(codec_cfg, &data); if (ret >= 0) { - print_codec_meta_ccid_list(sh, data, (uint8_t)ret); + print_codec_meta_ccid_list(sh, indent, data, (uint8_t)ret); } ret = bt_audio_codec_cfg_meta_get_parental_rating(codec_cfg); if (ret >= 0) { - print_codec_meta_parental_rating(sh, (enum bt_audio_parental_rating)ret); + print_codec_meta_parental_rating(sh, indent, + (enum bt_audio_parental_rating)ret); } ret = bt_audio_codec_cfg_meta_get_audio_active_state(codec_cfg); if (ret >= 0) { - print_codec_meta_audio_active_state(sh, (enum bt_audio_active_state)ret); + print_codec_meta_audio_active_state(sh, indent, + (enum bt_audio_active_state)ret); } ret = bt_audio_codec_cfg_meta_get_bcast_audio_immediate_rend_flag(codec_cfg); if (ret >= 0) { - print_codec_meta_bcast_audio_immediate_rend_flag(sh); + print_codec_meta_bcast_audio_immediate_rend_flag(sh, indent); } ret = bt_audio_codec_cfg_meta_get_extended(codec_cfg, &data); if (ret >= 0) { - print_codec_meta_extended(sh, data, (uint8_t)ret); + print_codec_meta_extended(sh, indent, data, (uint8_t)ret); } ret = bt_audio_codec_cfg_meta_get_vendor(codec_cfg, &data); if (ret >= 0) { - print_codec_meta_vendor(sh, data, (uint8_t)ret); + print_codec_meta_vendor(sh, indent, data, (uint8_t)ret); } } #endif /* CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE > 0 */ @@ -855,22 +941,40 @@ extern struct broadcast_source default_source; static inline bool print_base_subgroup_bis_cb(const struct bt_bap_base_subgroup_bis *bis, void *user_data) { + size_t indent = 2 * SHELL_PRINT_INDENT_LEVEL_SIZE; struct bt_bap_base_codec_id *codec_id = user_data; - shell_print(ctx_shell, "\t\tBIS index: 0x%02X", bis->index); + shell_print(ctx_shell, "%*sBIS index: 0x%02X", indent, "", bis->index); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; + /* Print CC data */ if (codec_id->id == BT_HCI_CODING_FORMAT_LC3) { - struct bt_audio_codec_cfg codec_cfg; + struct bt_audio_codec_cfg codec_cfg = { + .id = codec_id->id, + .cid = codec_id->cid, + .vid = codec_id->vid, + }; int err; err = bt_bap_base_subgroup_bis_codec_to_codec_cfg(bis, &codec_cfg); if (err == 0) { - print_codec_cfg(ctx_shell, &codec_cfg); + print_codec_cfg(ctx_shell, indent, &codec_cfg); } else { - print_ltv_array(ctx_shell, "\t\tdata", bis->data, bis->data_len); + shell_print(ctx_shell, "%*sCodec specific configuration:", indent, ""); + print_ltv_array(ctx_shell, indent, bis->data, bis->data_len); } } else { /* If not LC3, we cannot assume it's LTV */ - shell_hexdump(ctx_shell, bis->data, bis->data_len); + shell_print(ctx_shell, "%*sCodec specific configuration:", indent, ""); + + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; + shell_fprintf(ctx_shell, SHELL_NORMAL, "%*s", indent, ""); + + for (uint8_t i = 0U; i < bis->data_len; i++) { + shell_fprintf(ctx_shell, SHELL_NORMAL, "%02X", bis->data[i]); + } + + shell_fprintf(ctx_shell, SHELL_NORMAL, "\n"); } return true; @@ -879,6 +983,7 @@ static inline bool print_base_subgroup_bis_cb(const struct bt_bap_base_subgroup_ static inline bool print_base_subgroup_cb(const struct bt_bap_base_subgroup *subgroup, void *user_data) { + size_t indent = 1 * SHELL_PRINT_INDENT_LEVEL_SIZE; struct bt_bap_base_codec_id codec_id; struct bt_audio_codec_cfg codec_cfg; uint8_t *data; @@ -891,24 +996,34 @@ static inline bool print_base_subgroup_cb(const struct bt_bap_base_subgroup *sub return false; } - shell_print(ctx_shell, "\tCodec Format: 0x%02X", codec_id.id); - shell_print(ctx_shell, "\tCompany ID : 0x%04X", codec_id.cid); - shell_print(ctx_shell, "\tVendor ID : 0x%04X", codec_id.vid); - - ret = bt_bap_base_get_subgroup_codec_data(subgroup, &data); - if (ret < 0) { - return false; - } + shell_print(ctx_shell, "%*sCodec Format: 0x%02X", indent, "", codec_id.id); + shell_print(ctx_shell, "%*sCompany ID : 0x%04X", indent, "", codec_id.cid); + shell_print(ctx_shell, "%*sVendor ID : 0x%04X", indent, "", codec_id.vid); ret = bt_bap_base_subgroup_codec_to_codec_cfg(subgroup, &codec_cfg); if (ret == 0) { - print_codec_cfg(ctx_shell, &codec_cfg); + print_codec_cfg(ctx_shell, indent, &codec_cfg); } else { + /* If we cannot store it in a codec_cfg, then we cannot easily print it as such */ + ret = bt_bap_base_get_subgroup_codec_data(subgroup, &data); + if (ret < 0) { + return false; + } + + shell_print(ctx_shell, "%*sCodec specific configuration:", indent, ""); + indent += SHELL_PRINT_INDENT_LEVEL_SIZE; + /* Print CC data */ if (codec_id.id == BT_HCI_CODING_FORMAT_LC3) { - print_ltv_array(ctx_shell, "\tdata", data, (uint8_t)ret); + print_ltv_array(ctx_shell, indent, data, (uint8_t)ret); } else { /* If not LC3, we cannot assume it's LTV */ - shell_hexdump(ctx_shell, data, (uint8_t)ret); + shell_fprintf(ctx_shell, SHELL_NORMAL, "%*s", indent, ""); + + for (uint8_t i = 0U; i < (uint8_t)ret; i++) { + shell_fprintf(ctx_shell, SHELL_NORMAL, "%c", data[i]); + } + + shell_fprintf(ctx_shell, SHELL_NORMAL, "\n"); } ret = bt_bap_base_get_subgroup_codec_meta(subgroup, &data); @@ -916,11 +1031,21 @@ static inline bool print_base_subgroup_cb(const struct bt_bap_base_subgroup *sub return false; } + shell_print(ctx_shell, + "%*sCodec specific metadata:", indent - SHELL_PRINT_INDENT_LEVEL_SIZE, + ""); + /* Print metadata */ if (codec_id.id == BT_HCI_CODING_FORMAT_LC3) { - print_ltv_array(ctx_shell, "\tdata", data, (uint8_t)ret); + print_ltv_array(ctx_shell, indent, data, (uint8_t)ret); } else { /* If not LC3, we cannot assume it's LTV */ - shell_hexdump(ctx_shell, data, (uint8_t)ret); + shell_fprintf(ctx_shell, SHELL_NORMAL, "%*s", indent, ""); + + for (uint8_t i = 0U; i < (uint8_t)ret; i++) { + shell_fprintf(ctx_shell, SHELL_NORMAL, "%c", data[i]); + } + + shell_fprintf(ctx_shell, SHELL_NORMAL, "\n"); } } diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index 0d7f5f4565f..ce1ffebd807 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -500,7 +500,7 @@ static int lc3_config(struct bt_conn *conn, const struct bt_bap_ep *ep, enum bt_ { shell_print(ctx_shell, "ASE Codec Config: conn %p ep %p dir %u", conn, ep, dir); - print_codec_cfg(ctx_shell, codec_cfg); + print_codec_cfg(ctx_shell, 0, codec_cfg); *stream = stream_alloc(); if (*stream == NULL) { @@ -526,7 +526,7 @@ static int lc3_reconfig(struct bt_bap_stream *stream, enum bt_audio_dir dir, { shell_print(ctx_shell, "ASE Codec Reconfig: stream %p", stream); - print_codec_cfg(ctx_shell, codec_cfg); + print_codec_cfg(ctx_shell, 0, codec_cfg); if (default_stream == NULL) { set_unicast_stream(stream); @@ -775,7 +775,7 @@ static void print_remote_codec_cap(const struct bt_conn *conn, shell_print(ctx_shell, "conn %p: codec_cap %p dir 0x%02x", conn, codec_cap, dir); - print_codec_cap(ctx_shell, codec_cap); + print_codec_cap(ctx_shell, 0, codec_cap); } #if CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT > 0 @@ -2135,8 +2135,8 @@ static int cmd_preset(const struct shell *sh, size_t argc, char *argv[]) shell_print(sh, "%s", named_preset->name); - print_codec_cfg(sh, &named_preset->preset.codec_cfg); - print_qos(sh, &named_preset->preset.qos); + print_codec_cfg(ctx_shell, 0, &named_preset->preset.codec_cfg); + print_qos(ctx_shell, &named_preset->preset.qos); return 0; } From 71fd9b2e07a6fa9d7895759fc83685b6849aebb4 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 17:03:46 +0200 Subject: [PATCH 0393/2402] posix: syslog: Fix uninitialized variable error Seen this in compiler lib/posix/options/syslog.c: In function 'setlogmask': lib/posix/options/syslog.c:66:16: error: 'oldpri' may be used uninitialized 66 | return oldpri; | ^~~~~~ lib/posix/options/syslog.c:59:13: note: 'oldpri' was declared here 59 | int oldpri; | ^~~~~~ lib/posix/options/syslog.c: In function 'vsyslog': lib/posix/options/syslog.c:83:33: error: 'mask' may be used uninitialized 83 | if ((BIT(level) & mask) == 0) { | ~~~~~~~~~~~~~~~~~~~~^~~~ lib/posix/options/syslog.c:71:17: note: 'mask' was declared here 71 | uint8_t mask; | ^~~~ Signed-off-by: Jukka Rissanen --- lib/posix/options/syslog.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/posix/options/syslog.c b/lib/posix/options/syslog.c index 576858fb4c8..488e8429954 100644 --- a/lib/posix/options/syslog.c +++ b/lib/posix/options/syslog.c @@ -56,7 +56,7 @@ void syslog(int priority, const char *format, ...) int setlogmask(int maskpri) { - int oldpri; + int oldpri = -1; K_SPINLOCK(&syslog_lock) { oldpri = syslog_mask; @@ -68,7 +68,7 @@ int setlogmask(int maskpri) void vsyslog(int priority, const char *format, va_list ap) { - uint8_t mask; + uint8_t mask = 0; int level = syslog_priority_to_zephyr_log_level(priority); if (level < 0) { From aa87ed5d8a711c50c5db325b543068ac583d2a6b Mon Sep 17 00:00:00 2001 From: Aleksandr Khromykh Date: Fri, 1 Mar 2024 15:47:12 +0100 Subject: [PATCH 0394/2402] Bluetooth: Mesh: make models metadata const Commit adds const qualifier to models metadata. Specification claims: Composition Metadata Page 0 shall not change during a term of a node on the network. Signed-off-by: Aleksandr Khromykh --- doc/releases/migration-guide-3.7.rst | 5 +++++ include/zephyr/bluetooth/mesh/access.h | 4 ++-- include/zephyr/bluetooth/mesh/health_srv.h | 2 +- subsys/bluetooth/mesh/access.c | 6 +++--- subsys/bluetooth/mesh/shell/shell.c | 4 ++-- tests/bluetooth/tester/src/btp_mesh.c | 8 ++++---- tests/bsim/bluetooth/mesh/src/test_lcd.c | 2 +- 7 files changed, 18 insertions(+), 13 deletions(-) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index f9c8acd248f..8dce89635fb 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -144,6 +144,11 @@ Bluetooth Bluetooth Mesh ============== +* The model metadata pointer declaration of :c:struct:`bt_mesh_model` has been changed + to add ``const`` qualifiers. The data pointer of :c:struct:`bt_mesh_models_metadata_entry` + got ``const`` qualifier too. The model's metadata structure and metadata raw value + can be declared as permanent constants in the non-volatile memory. (:github:`69679`) + Bluetooth Audio =============== diff --git a/include/zephyr/bluetooth/mesh/access.h b/include/zephyr/bluetooth/mesh/access.h index a236ede525d..5d2d661710e 100644 --- a/include/zephyr/bluetooth/mesh/access.h +++ b/include/zephyr/bluetooth/mesh/access.h @@ -777,7 +777,7 @@ struct bt_mesh_models_metadata_entry { const uint16_t id; /* Pointer to raw data */ - void *data; + const void * const data; }; /** @@ -924,7 +924,7 @@ struct bt_mesh_model { #if defined(CONFIG_BT_MESH_LARGE_COMP_DATA_SRV) || defined(__DOXYGEN__) /* Pointer to the array of model metadata entries. */ - struct bt_mesh_models_metadata_entry **metadata; + const struct bt_mesh_models_metadata_entry * const * const metadata; #endif }; diff --git a/include/zephyr/bluetooth/mesh/health_srv.h b/include/zephyr/bluetooth/mesh/health_srv.h index 90bdb4c81a4..9eb4008b846 100644 --- a/include/zephyr/bluetooth/mesh/health_srv.h +++ b/include/zephyr/bluetooth/mesh/health_srv.h @@ -159,7 +159,7 @@ struct bt_mesh_health_srv { #ifdef CONFIG_BT_MESH_LARGE_COMP_DATA_SRV /** Pointer to the array with Health Test Info Metadata */ - struct bt_mesh_models_metadata_entry *metadata; + const struct bt_mesh_models_metadata_entry *metadata; #endif }; diff --git a/subsys/bluetooth/mesh/access.c b/subsys/bluetooth/mesh/access.c index 328ec0dd281..51471097c9e 100644 --- a/subsys/bluetooth/mesh/access.c +++ b/subsys/bluetooth/mesh/access.c @@ -174,7 +174,7 @@ static void data_buf_add_le16_offset(struct net_buf_simple *buf, } } -static void data_buf_add_mem_offset(struct net_buf_simple *buf, uint8_t *data, size_t len, +static void data_buf_add_mem_offset(struct net_buf_simple *buf, const uint8_t *data, size_t len, size_t *offset) { if (*offset >= len) { @@ -694,13 +694,13 @@ static int bt_mesh_comp_data_get_page_2(struct net_buf_simple *buf, size_t offse data_buf_add_u8_offset(buf, dev_comp2->record[i].version.z, &offset); data_buf_add_u8_offset(buf, dev_comp2->record[i].elem_offset_cnt, &offset); if (dev_comp2->record[i].elem_offset_cnt) { - data_buf_add_mem_offset(buf, (uint8_t *)dev_comp2->record[i].elem_offset, + data_buf_add_mem_offset(buf, dev_comp2->record[i].elem_offset, dev_comp2->record[i].elem_offset_cnt, &offset); } data_buf_add_le16_offset(buf, dev_comp2->record[i].data_len, &offset); if (dev_comp2->record[i].data_len) { - data_buf_add_mem_offset(buf, (uint8_t *)dev_comp2->record[i].data, + data_buf_add_mem_offset(buf, dev_comp2->record[i].data, dev_comp2->record[i].data_len, &offset); } } diff --git a/subsys/bluetooth/mesh/shell/shell.c b/subsys/bluetooth/mesh/shell/shell.c index 9a0e5ece5e3..53672bea4ba 100644 --- a/subsys/bluetooth/mesh/shell/shell.c +++ b/subsys/bluetooth/mesh/shell/shell.c @@ -145,12 +145,12 @@ static const struct bt_mesh_health_srv_cb health_srv_cb = { #endif /* CONFIG_BT_MESH_SHELL_HEALTH_SRV_INSTANCE */ #ifdef CONFIG_BT_MESH_LARGE_COMP_DATA_SRV -static uint8_t health_tests[] = { +static const uint8_t health_tests[] = { BT_MESH_HEALTH_TEST_INFO(COMPANY_ID_LF, 6, 0x01, 0x02, 0x03, 0x04, 0x34, 0x15), BT_MESH_HEALTH_TEST_INFO(COMPANY_ID_NORDIC_SEMI, 3, 0x01, 0x02, 0x03), }; -static struct bt_mesh_models_metadata_entry health_srv_meta[] = { +static const struct bt_mesh_models_metadata_entry health_srv_meta[] = { BT_MESH_HEALTH_TEST_INFO_METADATA(health_tests), BT_MESH_MODELS_METADATA_END, }; diff --git a/tests/bluetooth/tester/src/btp_mesh.c b/tests/bluetooth/tester/src/btp_mesh.c index ab5fcf515bd..65b3a81c6e2 100644 --- a/tests/bluetooth/tester/src/btp_mesh.c +++ b/tests/bluetooth/tester/src/btp_mesh.c @@ -691,9 +691,9 @@ static uint8_t health_tests[] = { BT_MESH_HEALTH_TEST_INFO(COMPANY_ID_NORDIC_SEMI, 3, 0x01, 0x02, 0x03), }; -static uint8_t zero_metadata[100]; +static const uint8_t zero_metadata[100]; -static struct bt_mesh_models_metadata_entry health_srv_meta[] = { +static const struct bt_mesh_models_metadata_entry health_srv_meta[] = { BT_MESH_HEALTH_TEST_INFO_METADATA(health_tests), { .len = ARRAY_SIZE(zero_metadata), @@ -703,13 +703,13 @@ static struct bt_mesh_models_metadata_entry health_srv_meta[] = { BT_MESH_MODELS_METADATA_END, }; -static uint8_t health_tests_alt[] = { +static const uint8_t health_tests_alt[] = { BT_MESH_HEALTH_TEST_INFO(COMPANY_ID_LF, 6, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66), BT_MESH_HEALTH_TEST_INFO(COMPANY_ID_NORDIC_SEMI, 3, 0x11, 0x22, 0x33), }; -static struct bt_mesh_models_metadata_entry health_srv_meta_alt[] = { +static const struct bt_mesh_models_metadata_entry health_srv_meta_alt[] = { BT_MESH_HEALTH_TEST_INFO_METADATA(health_tests_alt), { .len = ARRAY_SIZE(zero_metadata), diff --git a/tests/bsim/bluetooth/mesh/src/test_lcd.c b/tests/bsim/bluetooth/mesh/src/test_lcd.c index e1c7adde730..cd6a515294e 100644 --- a/tests/bsim/bluetooth/mesh/src/test_lcd.c +++ b/tests/bsim/bluetooth/mesh/src/test_lcd.c @@ -86,7 +86,7 @@ static void test_args_parse(int argc, char *argv[]) bs_args_parse_all_cmd_line(argc, argv, args_struct); } -static struct bt_mesh_models_metadata_entry *dummy_meta_entry[] = {}; +static const struct bt_mesh_models_metadata_entry *dummy_meta_entry[] = {}; /* Empty elements to create large composition/meta data */ #define DUMMY_ELEM(i, _) BT_MESH_ELEM((i) + 2, \ From 28107ae8ce43f7819988165caa7131c6372a5256 Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Thu, 7 Mar 2024 07:32:30 +0100 Subject: [PATCH 0395/2402] logging: fix typo in include file log_msg.h fix typo in include file log_msg.h Signed-off-by: Florian La Roche --- include/zephyr/logging/log_msg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/logging/log_msg.h b/include/zephyr/logging/log_msg.h index 39cbf1cedbc..2d314d47f82 100644 --- a/include/zephyr/logging/log_msg.h +++ b/include/zephyr/logging/log_msg.h @@ -464,7 +464,7 @@ do { \ * * Macro handles creation of log message which includes storing log message * description, timestamp, arguments, copying string arguments into message and - * copying user data into the message space. The are 3 modes of message + * copying user data into the message space. There are 3 modes of message * creation: * - at compile time message size is determined, message is allocated and * content is written directly to the message. It is the fastest but cannot From b680a6ec72da4191eb3ae28ec010cfbf05333936 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Fri, 8 Mar 2024 11:41:38 +0000 Subject: [PATCH 0396/2402] scripts: snippets: Fix path output on windows Fixes an issue with paths being output in windows-style with back slashes, this causes issues for certain escape sequences when cmake interprets them. Replace these paths with posix paths so that they are not treated as possible escape sequences. Signed-off-by: Jamie McCrae --- scripts/snippets.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/snippets.py b/scripts/snippets.py index 48733ee3b55..625f101ec63 100644 --- a/scripts/snippets.py +++ b/scripts/snippets.py @@ -56,7 +56,7 @@ def append_value(variable, value): path = pathobj.parent / value if not path.is_file(): _err(f'snippet file {pathobj}: {variable}: file not found: {path}') - return f'"{path}"' + return f'"{path.as_posix()}"' if variable in ('DTS_EXTRA_CPPFLAGS'): return f'"{value}"' _err(f'unknown append variable: {variable}') From cba1e34ef0424ad5521205881c388774139f3dec Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Thu, 7 Mar 2024 08:08:17 +0000 Subject: [PATCH 0397/2402] drivers: clock_control: Fix npcx leakage Fixes an issue with Kconfig for this leaking into all devices where it should not be Signed-off-by: Jamie McCrae --- drivers/clock_control/Kconfig.npcx | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clock_control/Kconfig.npcx b/drivers/clock_control/Kconfig.npcx index 76e5acf985a..6a3f3fe24a8 100644 --- a/drivers/clock_control/Kconfig.npcx +++ b/drivers/clock_control/Kconfig.npcx @@ -10,9 +10,10 @@ config CLOCK_CONTROL_NPCX help Enable support for NPCX clock controller driver. +if CLOCK_CONTROL_NPCX + config CLOCK_CONTROL_NPCX_EXTERNAL_SRC bool "Generate LFCLK by on-chip Crystal Oscillator" - depends on CLOCK_CONTROL_NPCX help When this option is enabled, the internal 32.768 KHz clock (LFCLK) is generated by the on-chip Crystal Oscillator (XTOSC). @@ -30,3 +31,5 @@ config CLOCK_CONTROL_NPCX_SUPP_FIU1 default y if SOC_SERIES_NPCX4 help Selected if NPCX series supports FIU1 bus. + +endif # CLOCK_CONTROL_NPCX From 69586d16c2fd1e67c4e0e6e98c68313b10639142 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 8 Mar 2024 11:14:53 +0100 Subject: [PATCH 0398/2402] boards: nordic: nrf54h20pdk: add debugging support using J-Link cpuapp/cpurad can be debugged using the J-Link runner. Note: This feature is still experimental and has known issues. For example, setting a breakpoint to main requires to patch init.c with a loop polling a variable so that we stop there until unset from GDB. Signed-off-by: Gerard Marull-Paretas --- boards/nordic/nrf54h20pdk/board.cmake | 12 ++++++++++++ .../nrf54h20pdk/support/nrf54h20_cpurad.JLinkScript | 4 ++++ 2 files changed, 16 insertions(+) create mode 100644 boards/nordic/nrf54h20pdk/support/nrf54h20_cpurad.JLinkScript diff --git a/boards/nordic/nrf54h20pdk/board.cmake b/boards/nordic/nrf54h20pdk/board.cmake index 4c63f1dd05e..f01b5050f34 100644 --- a/boards/nordic/nrf54h20pdk/board.cmake +++ b/boards/nordic/nrf54h20pdk/board.cmake @@ -1,3 +1,15 @@ # SPDX-License-Identifier: Apache-2.0 include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) + +if(CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPURAD) + if(CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPURAD) + set( + JLINK_TOOL_OPT + "-jlinkscriptfile ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpurad.JLinkScript" + ) + endif() + + board_runner_args(jlink "--device=CORTEX-M33" "--speed=4000" "--tool-opt=${JLINK_TOOL_OPT}") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nordic/nrf54h20pdk/support/nrf54h20_cpurad.JLinkScript b/boards/nordic/nrf54h20pdk/support/nrf54h20_cpurad.JLinkScript new file mode 100644 index 00000000000..2fb7e32302e --- /dev/null +++ b/boards/nordic/nrf54h20pdk/support/nrf54h20_cpurad.JLinkScript @@ -0,0 +1,4 @@ +void ConfigTargetSettings(void) { + JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP"); + CORESIGHT_IndexAHBAPToUse = 1; +} From 3a1784432bb13404d6354be69f3d10cea4dae063 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Thu, 7 Mar 2024 16:21:40 -0800 Subject: [PATCH 0399/2402] arch: arm64: correct a comment on CONFIG_ARM64_STACK_PROTECTION There is a #endif comment which was incorrectly marked with CONFIG_HW_STACK_PROTECTION instead of CONFIG_ARM64_STACK_PROTECTION, which is used at #if. So update it. Signed-off-by: Daniel Leung --- arch/arm64/core/cortex_r/arm_mpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/core/cortex_r/arm_mpu.c b/arch/arm64/core/cortex_r/arm_mpu.c index e303a7c0379..2bd6d265c9a 100644 --- a/arch/arm64/core/cortex_r/arm_mpu.c +++ b/arch/arm64/core/cortex_r/arm_mpu.c @@ -735,7 +735,7 @@ static int configure_dynamic_mpu_regions(struct k_thread *thread) atomic_clear(&thread->arch.flushing); return ret < 0 ? ret : 0; } -#endif /* defined(CONFIG_USERSPACE) || defined(CONFIG_HW_STACK_PROTECTION) */ +#endif /* defined(CONFIG_USERSPACE) || defined(CONFIG_ARM64_STACK_PROTECTION) */ #if defined(CONFIG_USERSPACE) int arch_mem_domain_max_partitions_get(void) From 75c9f0fb0ef204e2e4914e60f324a3b5bc5b7b74 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Sun, 10 Mar 2024 17:55:22 +0100 Subject: [PATCH 0400/2402] tests: drivers: can: shell: skip dtiming test if CAN FD is not enabled Skip the "test_can_dtiming" test case if CONFIG_CAN_FD_MODE is not enabled, not the "test_can_timing_missing_value" test case. Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/shell/src/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/drivers/can/shell/src/main.c b/tests/drivers/can/shell/src/main.c index 227606fcb83..6267fd17af1 100644 --- a/tests/drivers/can/shell/src/main.c +++ b/tests/drivers/can/shell/src/main.c @@ -234,8 +234,6 @@ ZTEST(can_shell, test_can_timing_missing_value) const struct shell *sh = shell_backend_dummy_get_ptr(); int err; - Z_TEST_SKIP_IFNDEF(CONFIG_CAN_FD_MODE); - err = shell_execute_cmd(sh, "can timing " FAKE_CAN_NAME); zassert_not_equal(err, 0, " executed shell command without timing"); zassert_equal(fake_can_set_timing_fake.call_count, 0, @@ -254,6 +252,8 @@ ZTEST(can_shell, test_can_dtiming) }; int err; + Z_TEST_SKIP_IFNDEF(CONFIG_CAN_FD_MODE); + fake_can_set_timing_data_fake.custom_fake = can_shell_test_capture_timing; err = shell_execute_cmd(sh, "can dtiming " FAKE_CAN_NAME " 1 2 3 4 5"); From 6fa13e20e34ec164e47f5150b0ca8908a030acaf Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Sun, 10 Mar 2024 18:22:03 +0100 Subject: [PATCH 0401/2402] drivers: can: shell: properly sort mode table entries Properly sort the entries in the can_mode_t translation table. Signed-off-by: Henrik Brix Andersen --- drivers/can/can_shell.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/can/can_shell.c b/drivers/can/can_shell.c index b6b64fe371e..e9573b56a4b 100644 --- a/drivers/can/can_shell.c +++ b/drivers/can/can_shell.c @@ -28,14 +28,15 @@ struct can_shell_mode_mapping { #define CAN_SHELL_MODE_MAPPING(_name, _mode) { .name = _name, .mode = _mode } static const struct can_shell_mode_mapping can_shell_mode_map[] = { - /* Array sorted alphabetically based on name */ + /* zephyr-keep-sorted-start */ CAN_SHELL_MODE_MAPPING("fd", CAN_MODE_FD), CAN_SHELL_MODE_MAPPING("listen-only", CAN_MODE_LISTENONLY), CAN_SHELL_MODE_MAPPING("loopback", CAN_MODE_LOOPBACK), + CAN_SHELL_MODE_MAPPING("manual-recovery", CAN_MODE_MANUAL_RECOVERY), CAN_SHELL_MODE_MAPPING("normal", CAN_MODE_NORMAL), CAN_SHELL_MODE_MAPPING("one-shot", CAN_MODE_ONE_SHOT), CAN_SHELL_MODE_MAPPING("triple-sampling", CAN_MODE_3_SAMPLES), - CAN_SHELL_MODE_MAPPING("manual-recovery", CAN_MODE_MANUAL_RECOVERY), + /* zephyr-keep-sorted-stop */ }; K_MSGQ_DEFINE(can_shell_tx_msgq, sizeof(struct can_shell_tx_event), From 0195f774ba95e40808b89208b12e9e427e982e6a Mon Sep 17 00:00:00 2001 From: Alexandre Poizat Date: Wed, 6 Mar 2024 15:10:21 +0100 Subject: [PATCH 0402/2402] drivers: adc: stm32: disable ADC before writing oversampling bits for g0 Added the STM32G0X SOC series to the list of SOC that need to disable the ADC while setting the oversampling bits to prevent writing over the CKMODE bits. Signed-off-by: Alexandre Poizat --- drivers/adc/adc_stm32.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index ce108e04ce2..8213310ee7b 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -641,11 +641,14 @@ static const uint32_t table_oversampling_ratio[] = { */ static void adc_stm32_oversampling_scope(ADC_TypeDef *adc, uint32_t ovs_scope) { -#if defined(CONFIG_SOC_SERIES_STM32L0X) || \ +#if defined(CONFIG_SOC_SERIES_STM32G0X) || \ + defined(CONFIG_SOC_SERIES_STM32L0X) || \ defined(CONFIG_SOC_SERIES_STM32WLX) /* - * setting OVS bits is conditioned to ADC state: ADC must be disabled - * or enabled without conversion on going : disable it, it will stop + * Setting OVS bits is conditioned to ADC state: ADC must be disabled + * or enabled without conversion on going : disable it, it will stop. + * For the G0 series, ADC must be disabled to prevent CKMODE bitfield + * from getting reset, see errata ES0418 section 2.6.4. */ if (LL_ADC_GetOverSamplingScope(adc) == ovs_scope) { return; From e22958ceaf6020dd595ae28963e5699d5406d7bc Mon Sep 17 00:00:00 2001 From: cyliang tw Date: Mon, 11 Mar 2024 14:59:20 +0800 Subject: [PATCH 0403/2402] soc: nuvoton: numaker: add support for m2l31x series Add initial support for nuvoton numaker m2l31x SoC series including basic init. Signed-off-by: cyliang tw --- dts/arm/nuvoton/m2l31kid.dtsi | 23 ++ dts/arm/nuvoton/m2l31x.dtsi | 221 ++++++++++++++ .../dt-bindings/clock/numaker_m2l31x_clock.h | 274 ++++++++++++++++++ .../dt-bindings/reset/numaker_m2l31x_reset.h | 155 ++++++++++ soc/nuvoton/numaker/m2l31x/CMakeLists.txt | 9 + soc/nuvoton/numaker/m2l31x/Kconfig | 14 + soc/nuvoton/numaker/m2l31x/Kconfig.defconfig | 9 + .../numaker/m2l31x/Kconfig.defconfig.m2l31xxx | 10 + soc/nuvoton/numaker/m2l31x/Kconfig.soc | 19 ++ soc/nuvoton/numaker/m2l31x/soc.c | 86 ++++++ soc/nuvoton/numaker/m2l31x/soc.h | 13 + soc/nuvoton/numaker/soc.yml | 3 + 12 files changed, 836 insertions(+) create mode 100644 dts/arm/nuvoton/m2l31kid.dtsi create mode 100644 dts/arm/nuvoton/m2l31x.dtsi create mode 100644 include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h create mode 100644 include/zephyr/dt-bindings/reset/numaker_m2l31x_reset.h create mode 100644 soc/nuvoton/numaker/m2l31x/CMakeLists.txt create mode 100644 soc/nuvoton/numaker/m2l31x/Kconfig create mode 100644 soc/nuvoton/numaker/m2l31x/Kconfig.defconfig create mode 100644 soc/nuvoton/numaker/m2l31x/Kconfig.defconfig.m2l31xxx create mode 100644 soc/nuvoton/numaker/m2l31x/Kconfig.soc create mode 100644 soc/nuvoton/numaker/m2l31x/soc.c create mode 100644 soc/nuvoton/numaker/m2l31x/soc.h diff --git a/dts/arm/nuvoton/m2l31kid.dtsi b/dts/arm/nuvoton/m2l31kid.dtsi new file mode 100644 index 00000000000..32c793ded8c --- /dev/null +++ b/dts/arm/nuvoton/m2l31kid.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(168)>; + }; + + soc { + rmc: flash-controller@4000c000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(512)>; + }; + }; + }; +}; diff --git a/dts/arm/nuvoton/m2l31x.dtsi b/dts/arm/nuvoton/m2l31x.dtsi new file mode 100644 index 00000000000..00af64b124c --- /dev/null +++ b/dts/arm/nuvoton/m2l31x.dtsi @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +/ { + chosen { + zephyr,flash-controller = &rmc; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m23"; + reg = <0>; + }; + }; + + sysclk: system-clock { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + soc { + scc: system-clock-controller@40000200 { + compatible = "nuvoton,numaker-scc"; + reg = <0x40000200 0x100>; + #clock-cells = <0>; + clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 | + NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>; + core-clock = ; + + pcc: peripheral-clock-controller { + compatible = "nuvoton,numaker-pcc"; + #clock-cells = <3>; + }; + }; + + rst: reset-controller@40000000 { + compatible = "nuvoton,numaker-rst"; + reg = <0x40000000 0x20>; + #reset-cells = <1>; + }; + + rmc: flash-controller@4000c000 { + compatible = "nuvoton,numaker-rmc"; + reg = <0x4000c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + erase-block-size = <4096>; + write-block-size = <4>; + }; + }; + + uart0: serial@40070000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40070000 0x1000>; + interrupts = <36 0>; + resets = <&rst NUMAKER_UART0_RST>; + clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL4_UART0SEL_HIRC + NUMAKER_CLK_CLKDIV0_UART0(1)>; + status = "disabled"; + }; + + uart1: serial@40071000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40071000 0x1000>; + interrupts = <37 0>; + resets = <&rst NUMAKER_UART1_RST>; + clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL4_UART1SEL_HIRC + NUMAKER_CLK_CLKDIV0_UART1(1)>; + status = "disabled"; + }; + + uart2: serial@40072000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40072000 0x1000>; + interrupts = <48 0>; + resets = <&rst NUMAKER_UART2_RST>; + clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL4_UART2SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART2(1)>; + status = "disabled"; + }; + + uart3: serial@40073000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40073000 0x1000>; + interrupts = <49 0>; + resets = <&rst NUMAKER_UART3_RST>; + clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL4_UART3SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART3(1)>; + status = "disabled"; + }; + + uart4: serial@40074000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40074000 0x1000>; + interrupts = <74 0>; + resets = <&rst NUMAKER_UART4_RST>; + clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL4_UART4SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART4(1)>; + status = "disabled"; + }; + + uart5: serial@40075000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40075000 0x1000>; + interrupts = <75 0>; + resets = <&rst NUMAKER_UART5_RST>; + clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL4_UART5SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART5(1)>; + status = "disabled"; + }; + + uart6: serial@40076000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40076000 0x1000>; + interrupts = <102 0>; + resets = <&rst NUMAKER_UART6_RST>; + clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL4_UART6SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART6(1)>; + status = "disabled"; + }; + + uart7: serial@40077000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40077000 0x1000>; + interrupts = <103 0>; + resets = <&rst NUMAKER_UART7_RST>; + clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL4_UART7SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART7(1)>; + status = "disabled"; + }; + + pinctrl: pin-controller@40000080 { + compatible = "nuvoton,numaker-pinctrl"; + reg = <0x40000080 0x20 + 0x40000500 0x80>; + reg-names = "mfos", "mfp"; + }; + + gpioa: gpio@40004000 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40004000 0x40>; + clocks = <&pcc NUMAKER_GPA_MODULE 0 0>; + status = "disabled"; + interrupts = <16 2>; + }; + + gpiob: gpio@40004040 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40004040 0x40>; + clocks = <&pcc NUMAKER_GPB_MODULE 0 0>; + status = "disabled"; + interrupts = <17 2>; + }; + + gpioc: gpio@40004080 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40004080 0x40>; + clocks = <&pcc NUMAKER_GPC_MODULE 0 0>; + status = "disabled"; + interrupts = <18 2>; + }; + + gpiod: gpio@400040c0 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x400040c0 0x40>; + clocks = <&pcc NUMAKER_GPD_MODULE 0 0>; + status = "disabled"; + interrupts = <19 2>; + }; + + gpioe: gpio@40004100 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40004100 0x40>; + clocks = <&pcc NUMAKER_GPE_MODULE 0 0>; + status = "disabled"; + interrupts = <20 2>; + }; + + gpiof: gpio@40004140 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40004140 0x40>; + clocks = <&pcc NUMAKER_GPF_MODULE 0 0>; + status = "disabled"; + interrupts = <21 2>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <2>; +}; diff --git a/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h b/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h new file mode 100644 index 00000000000..fab7f656e4f --- /dev/null +++ b/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M2L31_CLOCK_H +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M2L31_CLOCK_H + +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_LXT 0x00000001 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_PLL 0x00000002 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_LIRC 0x00000003 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_MIRC 0x00000005 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC48M 0x00000006 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC 0x00000007 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_LXT 0x00000001 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_PLL 0x00000002 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_LIRC 0x00000003 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_MIRC 0x00000005 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_HIRC48M 0x00000006 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_HIRC 0x00000007 +#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL0_STCLKSEL_LXT 0x00000008 +#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT_DIV2 0x00000010 +#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x00000018 +#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x00000038 +#define NUMAKER_CLK_CLKSEL0_HCLK1SEL_HIRC 0x00000000 +#define NUMAKER_CLK_CLKSEL0_HCLK1SEL_MIRC 0x00001000 +#define NUMAKER_CLK_CLKSEL0_HCLK1SEL_LXT 0x00002000 +#define NUMAKER_CLK_CLKSEL0_HCLK1SEL_LIRC 0x00003000 +#define NUMAKER_CLK_CLKSEL0_HCLK1SEL_HIRC48M_DIV2 0x00004000 +#define NUMAKER_CLK_CLKSEL0_USBSEL_HIRC48M 0x00000000 +#define NUMAKER_CLK_CLKSEL0_USBSEL_PLL 0x00000100 +#define NUMAKER_CLK_CLKSEL0_EADC0SEL_PLL 0x00000400 +#define NUMAKER_CLK_CLKSEL0_EADC0SEL_HCLK 0x00000800 +#define NUMAKER_CLK_CLKSEL0_EADC0SEL_HCLK0 0x00000800 +#define NUMAKER_CLK_CLKSEL0_EADC0SEL_HIRC 0x00000C00 +#define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HIRC48M 0x01000000 +#define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HCLK 0x02000000 +#define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HCLK0 0x02000000 +#define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HIRC 0x03000000 +#define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HIRC48M 0x04000000 +#define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HCLK 0x08000000 +#define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HCLK0 0x08000000 +#define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HIRC 0x0C000000 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_LXT 0x00000010 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HCLK 0x00000020 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HCLK0 0x00000020 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HIRC 0x00000030 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_LIRC 0x00000040 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HIRC48M 0x00000050 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_PLL 0x00000060 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_MIRC 0x00000070 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_LXT 0x00000100 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_PCLK0 0x00000200 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_EXT 0x00000300 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_LIRC 0x00000500 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_HIRC 0x00000700 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_LXT 0x00001000 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_PCLK0 0x00002000 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_EXT 0x00003000 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_LIRC 0x00005000 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_HIRC 0x00007000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_LXT 0x00010000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_PCLK1 0x00020000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_EXT 0x00030000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_LIRC 0x00050000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_HIRC 0x00070000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_LXT 0x00100000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_PCLK1 0x00200000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_EXT 0x00300000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_LIRC 0x00500000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_HIRC 0x00700000 +#define NUMAKER_CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 0x80000000 +#define NUMAKER_CLK_CLKSEL1_WWDTSEL_HCLK0_DIV2048 0x80000000 +#define NUMAKER_CLK_CLKSEL1_WWDTSEL_LIRC 0xC0000000 +#define NUMAKER_CLK_CLKSEL2_EPWM0SEL_HCLK 0x00000000 +#define NUMAKER_CLK_CLKSEL2_EPWM0SEL_HCLK0 0x00000000 +#define NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0 0x00000001 +#define NUMAKER_CLK_CLKSEL2_EPWM1SEL_HCLK 0x00000000 +#define NUMAKER_CLK_CLKSEL2_EPWM1SEL_HCLK0 0x00000000 +#define NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1 0x00000002 +#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_PLL 0x00000004 +#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_PCLK0 0x00000008 +#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_HIRC 0x0000000C +#define NUMAKER_CLK_CLKSEL2_SPI0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL2_SPI0SEL_PLL 0x00000010 +#define NUMAKER_CLK_CLKSEL2_SPI0SEL_PCLK1 0x00000020 +#define NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC 0x00000030 +#define NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC48M 0x00000040 +#define NUMAKER_CLK_CLKSEL2_TKSEL_HIRC 0x00000000 +#define NUMAKER_CLK_CLKSEL2_TKSEL_MIRC 0x00000080 +#define NUMAKER_CLK_CLKSEL2_SPI1SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL2_SPI1SEL_PLL 0x00001000 +#define NUMAKER_CLK_CLKSEL2_SPI1SEL_PCLK0 0x00002000 +#define NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC 0x00003000 +#define NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC48M 0x00004000 +#define NUMAKER_CLK_CLKSEL3_PWM0SEL_HCLK 0x00000000 +#define NUMAKER_CLK_CLKSEL3_PWM0SEL_HCLK0 0x00000000 +#define NUMAKER_CLK_CLKSEL3_PWM0SEL_PCLK0 0x00000040 +#define NUMAKER_CLK_CLKSEL3_PWM1SEL_HCLK 0x00000000 +#define NUMAKER_CLK_CLKSEL3_PWM1SEL_HCLK0 0x00000000 +#define NUMAKER_CLK_CLKSEL3_PWM1SEL_PCLK1 0x00000080 +#define NUMAKER_CLK_CLKSEL3_SPI2SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL3_SPI2SEL_PLL 0x00000100 +#define NUMAKER_CLK_CLKSEL3_SPI2SEL_PCLK1 0x00000200 +#define NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC 0x00000300 +#define NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC48M 0x00000400 +#define NUMAKER_CLK_CLKSEL3_SPI3SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL3_SPI3SEL_PLL 0x00001000 +#define NUMAKER_CLK_CLKSEL3_SPI3SEL_PCLK0 0x00002000 +#define NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC 0x00003000 +#define NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC48M 0x00004000 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_PLL 0x00000001 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_LXT 0x00000002 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_HIRC 0x00000003 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_MIRC 0x00000004 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_HIRC48M 0x00000005 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_PLL 0x00000010 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_LXT 0x00000020 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_HIRC 0x00000030 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_MIRC 0x00000040 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_HIRC48M 0x00000050 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_PLL 0x00000100 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_LXT 0x00000200 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_HIRC 0x00000300 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_MIRC 0x00000400 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_HIRC48M 0x00000500 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_PLL 0x00001000 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_LXT 0x00002000 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_HIRC 0x00003000 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_MIRC 0x00004000 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_HIRC48M 0x00005000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_PLL 0x00010000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_LXT 0x00020000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_HIRC 0x00030000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_MIRC 0x00040000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_HIRC48M 0x00050000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_PLL 0x00100000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_LXT 0x00200000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_HIRC 0x00300000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_MIRC 0x00400000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_HIRC48M 0x00500000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_PLL 0x01000000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_LXT 0x02000000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_HIRC 0x03000000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_MIRC 0x04000000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_HIRC48M 0x05000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_PLL 0x10000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_LXT 0x20000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_HIRC 0x30000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_MIRC 0x40000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_HIRC48M 0x50000000 +#define NUMAKER_CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << (0)) +#define NUMAKER_CLK_CLKDIV0_HCLK0(x) (((x) - 1UL) << (0)) +#define NUMAKER_CLK_CLKDIV0_USB(x) (((x) - 1UL) << (4)) +#define NUMAKER_CLK_CLKDIV0_UART0(x) (((x) - 1UL) << (8)) +#define NUMAKER_CLK_CLKDIV0_UART1(x) (((x) - 1UL) << (12)) +#define NUMAKER_CLK_CLKDIV0_EADC0(x) (((x) - 1UL) << (16)) +#define NUMAKER_CLK_CLKDIV4_UART2(x) (((x) - 1UL) << (0)) +#define NUMAKER_CLK_CLKDIV4_UART3(x) (((x) - 1UL) << (4)) +#define NUMAKER_CLK_CLKDIV4_UART4(x) (((x) - 1UL) << (8)) +#define NUMAKER_CLK_CLKDIV4_UART5(x) (((x) - 1UL) << (12)) +#define NUMAKER_CLK_CLKDIV4_UART6(x) (((x) - 1UL) << (16)) +#define NUMAKER_CLK_CLKDIV4_UART7(x) (((x) - 1UL) << (20)) +#define NUMAKER_CLK_CLKDIV5_CANFD0(x) (((x) - 1UL) << (0)) +#define NUMAKER_CLK_CLKDIV5_CANFD1(x) (((x) - 1UL) << (4)) +#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV1 0x00000000 +#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 0x00000001 +#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV4 0x00000002 +#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV8 0x00000003 +#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV16 0x00000004 +#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV1 0x00000000 +#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2 0x00000010 +#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV4 0x00000020 +#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV8 0x00000030 +#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV16 0x00000040 +#define NUMAKER_PDMA0_MODULE 0x00000001 +#define NUMAKER_ISP_MODULE 0x00000002 +#define NUMAKER_EBI_MODULE 0x00000003 +#define NUMAKER_ST_MODULE 0x018C0004 +#define NUMAKER_CRC_MODULE 0x00000007 +#define NUMAKER_CRPT_MODULE 0x0000000C +#define NUMAKER_KS_MODULE 0x0000000D +#define NUMAKER_USBH_MODULE 0x00A01090 +#define NUMAKER_GPA_MODULE 0x00000018 +#define NUMAKER_GPB_MODULE 0x00000019 +#define NUMAKER_GPC_MODULE 0x0000001A +#define NUMAKER_GPD_MODULE 0x0000001B +#define NUMAKER_GPE_MODULE 0x0000001C +#define NUMAKER_GPF_MODULE 0x0000001D +#define NUMAKER_GPG_MODULE 0x0000001E +#define NUMAKER_GPH_MODULE 0x0000001F +#define NUMAKER_RTC_MODULE 0x20000001 +#define NUMAKER_TMR0_MODULE 0x25A00002 +#define NUMAKER_TMR1_MODULE 0x25B00003 +#define NUMAKER_TMR2_MODULE 0x25C00004 +#define NUMAKER_TMR3_MODULE 0x25D00005 +#define NUMAKER_CLKO_MODULE 0x26100006 +#define NUMAKER_ACMP01_MODULE 0x20000007 +#define NUMAKER_I2C0_MODULE 0x20000008 +#define NUMAKER_I2C1_MODULE 0x20000009 +#define NUMAKER_I2C2_MODULE 0x2000000A +#define NUMAKER_I2C3_MODULE 0x2000000B +#define NUMAKER_QSPI0_MODULE 0x2908000C +#define NUMAKER_SPI0_MODULE 0x2990000D +#define NUMAKER_SPI1_MODULE 0x29B0000E +#define NUMAKER_SPI2_MODULE 0x2DA0000F +#define NUMAKER_UART0_MODULE 0x31801110 +#define NUMAKER_UART1_MODULE 0x31901191 +#define NUMAKER_UART2_MODULE 0x31A11012 +#define NUMAKER_UART3_MODULE 0x31B11093 +#define NUMAKER_UART4_MODULE 0x31C11114 +#define NUMAKER_UART5_MODULE 0x31D11195 +#define NUMAKER_UART6_MODULE 0x31E11216 +#define NUMAKER_UART7_MODULE 0x31F11297 +#define NUMAKER_OTG_MODULE 0x2000001A +#define NUMAKER_USBD_MODULE 0x20A0109B +#define NUMAKER_EADC0_MODULE 0x2128221C +#define NUMAKER_TRNG_MODULE 0x2000001F +#define NUMAKER_SPI3_MODULE 0x4DB00006 +#define NUMAKER_USCI0_MODULE 0x40000008 +#define NUMAKER_USCI1_MODULE 0x40000009 +#define NUMAKER_WWDT_MODULE 0x4578000B +#define NUMAKER_DAC_MODULE 0x4000000C +#define NUMAKER_EPWM0_MODULE 0x48800010 +#define NUMAKER_EPWM1_MODULE 0x48840011 +#define NUMAKER_EQEI0_MODULE 0x40000016 +#define NUMAKER_EQEI1_MODULE 0x40000017 +#define NUMAKER_TK_MODULE 0x489C0019 +#define NUMAKER_ECAP0_MODULE 0x4000001A +#define NUMAKER_ECAP1_MODULE 0x4000001B +#define NUMAKER_ACMP2_MODULE 0x60000007 +#define NUMAKER_PWM0_MODULE 0x6C980008 +#define NUMAKER_PWM1_MODULE 0x6C9C0009 +#define NUMAKER_UTCPD0_MODULE 0x6000000F +#define NUMAKER_CANRAM0_MODULE 0x80000010 +#define NUMAKER_CANRAM1_MODULE 0x80000011 +#define NUMAKER_CANFD0_MODULE 0x81621014 +#define NUMAKER_CANFD1_MODULE 0x816A1095 +#define NUMAKER_HCLK1_MODULE 0x81B3101C +#define NUMAKER_LPPDMA0_MODULE 0xA0000000 +#define NUMAKER_LPGPIO_MODULE 0xA0000001 +#define NUMAKER_LPSRAM_MODULE 0xA0000002 +#define NUMAKER_WDT_MODULE 0xB5600010 +#define NUMAKER_LPSPI0_MODULE 0xB5080011 +#define NUMAKER_LPI2C0_MODULE 0xA0000012 +#define NUMAKER_LPUART0_MODULE 0xB5031113 +#define NUMAKER_LPTMR0_MODULE 0xB5A00014 +#define NUMAKER_LPTMR1_MODULE 0xB5B00015 +#define NUMAKER_TTMR0_MODULE 0xB5100016 +#define NUMAKER_TTMR1_MODULE 0xB5180017 +#define NUMAKER_LPADC0_MODULE 0xB5431218 +#define NUMAKER_OPA_MODULE 0xA000001B + +#endif diff --git a/include/zephyr/dt-bindings/reset/numaker_m2l31x_reset.h b/include/zephyr/dt-bindings/reset/numaker_m2l31x_reset.h new file mode 100644 index 00000000000..8c41ab4bea7 --- /dev/null +++ b/include/zephyr/dt-bindings/reset/numaker_m2l31x_reset.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H + +/* Beginning of M2L31 BSP sys_reg.h reset module copy */ + +#define LPSCC_IPRST0_LPPDMA0RST_Pos 0 +#define LPSCC_IPRST0_LPGPIORST_Pos 1 +#define LPSCC_IPRST0_LPSRAMRST_Pos 2 +#define LPSCC_IPRST0_WDTRST_Pos 16 +#define LPSCC_IPRST0_LPSPI0RST_Pos 17 +#define LPSCC_IPRST0_LPI2C0RST_Pos 18 +#define LPSCC_IPRST0_LPUART0RST_Pos 19 +#define LPSCC_IPRST0_LPTMR0RST_Pos 20 +#define LPSCC_IPRST0_LPTMR1RST_Pos 21 +#define LPSCC_IPRST0_TTMR0RST_Pos 22 +#define LPSCC_IPRST0_TTMR1RST_Pos 23 +#define LPSCC_IPRST0_LPADC0RST_Pos 24 +#define LPSCC_IPRST0_OPARST_Pos 27 +#define SYS_IPRST0_CHIPRST_Pos 0 +#define SYS_IPRST0_CPURST_Pos 1 +#define SYS_IPRST0_PDMA0RST_Pos 2 +#define SYS_IPRST0_EBIRST_Pos 3 +#define SYS_IPRST0_USBHRST_Pos 4 +#define SYS_IPRST0_CRCRST_Pos 7 +#define SYS_IPRST0_CRPTRST_Pos 12 +#define SYS_IPRST0_CANFD0RST_Pos 20 +#define SYS_IPRST0_CANFD1RST_Pos 21 +#define SYS_IPRST1_GPIORST_Pos 1 +#define SYS_IPRST1_TMR0RST_Pos 2 +#define SYS_IPRST1_TMR1RST_Pos 3 +#define SYS_IPRST1_TMR2RST_Pos 4 +#define SYS_IPRST1_TMR3RST_Pos 5 +#define SYS_IPRST1_ACMP01RST_Pos 7 +#define SYS_IPRST1_I2C0RST_Pos 8 +#define SYS_IPRST1_I2C1RST_Pos 9 +#define SYS_IPRST1_I2C2RST_Pos 10 +#define SYS_IPRST1_I2C3RST_Pos 11 +#define SYS_IPRST1_QSPI0RST_Pos 12 +#define SYS_IPRST1_SPI0RST_Pos 13 +#define SYS_IPRST1_SPI1RST_Pos 14 +#define SYS_IPRST1_SPI2RST_Pos 15 +#define SYS_IPRST1_UART0RST_Pos 16 +#define SYS_IPRST1_UART1RST_Pos 17 +#define SYS_IPRST1_UART2RST_Pos 18 +#define SYS_IPRST1_UART3RST_Pos 19 +#define SYS_IPRST1_UART4RST_Pos 20 +#define SYS_IPRST1_UART5RST_Pos 21 +#define SYS_IPRST1_UART6RST_Pos 22 +#define SYS_IPRST1_UART7RST_Pos 23 +#define SYS_IPRST1_OTGRST_Pos 26 +#define SYS_IPRST1_USBDRST_Pos 27 +#define SYS_IPRST1_EADC0RST_Pos 28 +#define SYS_IPRST1_TRNGRST_Pos 31 +#define SYS_IPRST2_SPI3RST_Pos 6 +#define SYS_IPRST2_USCI0RST_Pos 8 +#define SYS_IPRST2_USCI1RST_Pos 9 +#define SYS_IPRST2_WWDTRST_Pos 11 +#define SYS_IPRST2_DACRST_Pos 12 +#define SYS_IPRST2_EPWM0RST_Pos 16 +#define SYS_IPRST2_EPWM1RST_Pos 17 +#define SYS_IPRST2_EQEI0RST_Pos 22 +#define SYS_IPRST2_EQEI1RST_Pos 23 +#define SYS_IPRST2_TKRST_Pos 25 +#define SYS_IPRST2_ECAP0RST_Pos 26 +#define SYS_IPRST2_ECAP1RST_Pos 27 +#define SYS_IPRST3_ACMP2RST_Pos 7 +#define SYS_IPRST3_PWM0RST_Pos 8 +#define SYS_IPRST3_PWM1RST_Pos 9 +#define SYS_IPRST3_UTCPD0RST_Pos 15 + +/* End of M2L31 BSP sys_reg.h reset module copy */ + +/* Beginning of M2L31 BSP sys.h reset module copy */ + +/*--------------------------------------------------------------------- + * Module Reset Control Resister constant definitions. + *--------------------------------------------------------------------- + */ + +#define NUMAKER_PDMA0_RST ((0UL<<24) | SYS_IPRST0_PDMA0RST_Pos) +#define NUMAKER_EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) +#define NUMAKER_USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos) +#define NUMAKER_CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos) +#define NUMAKER_CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos) +#define NUMAKER_CANFD0_RST ((0UL<<24) | SYS_IPRST0_CANFD0RST_Pos) +#define NUMAKER_CANFD1_RST ((0UL<<24) | SYS_IPRST0_CANFD1RST_Pos) + +#define NUMAKER_GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos) +#define NUMAKER_TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos) +#define NUMAKER_TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos) +#define NUMAKER_TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos) +#define NUMAKER_TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos) +#define NUMAKER_ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos) +#define NUMAKER_I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos) +#define NUMAKER_I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos) +#define NUMAKER_I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos) +#define NUMAKER_I2C3_RST ((4UL<<24) | SYS_IPRST1_I2C3RST_Pos) +#define NUMAKER_QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos) +#define NUMAKER_SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos) +#define NUMAKER_SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos) +#define NUMAKER_SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos) +#define NUMAKER_UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos) +#define NUMAKER_UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos) +#define NUMAKER_UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos) +#define NUMAKER_UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos) +#define NUMAKER_UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos) +#define NUMAKER_UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos) +#define NUMAKER_UART6_RST ((4UL<<24) | SYS_IPRST1_UART6RST_Pos) +#define NUMAKER_UART7_RST ((4UL<<24) | SYS_IPRST1_UART7RST_Pos) +#define NUMAKER_OTG_RST ((4UL<<24) | SYS_IPRST1_OTGRST_Pos) +#define NUMAKER_USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos) +#define NUMAKER_EADC0_RST ((4UL<<24) | SYS_IPRST1_EADC0RST_Pos) +#define NUMAKER_TRNG_RST ((4UL<<24) | SYS_IPRST1_TRNGRST_Pos) + +#define NUMAKER_SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos) +#define NUMAKER_USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos) +#define NUMAKER_USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos) +#define NUMAKER_WWDT_RST ((8UL<<24) | SYS_IPRST2_WWDTRST_Pos) +#define NUMAKER_DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos) +#define NUMAKER_EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos) +#define NUMAKER_EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos) +#define NUMAKER_EQEI0_RST ((8UL<<24) | SYS_IPRST2_EQEI0RST_Pos) +#define NUMAKER_EQEI1_RST ((8UL<<24) | SYS_IPRST2_EQEI1RST_Pos) +#define NUMAKER_TK_RST ((8UL<<24) | SYS_IPRST2_TKRST_Pos) +#define NUMAKER_ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos) +#define NUMAKER_ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos) + +#define NUMAKER_ACMP2_RST ((0x18UL<<24) | SYS_IPRST3_ACMP2RST_Pos) +#define NUMAKER_PWM0_RST ((0x18UL<<24) | SYS_IPRST3_PWM0RST_Pos) +#define NUMAKER_PWM1_RST ((0x18UL<<24) | SYS_IPRST3_PWM1RST_Pos) +#define NUMAKER_UTCPD0_RST ((0x18UL<<24) | SYS_IPRST3_UTCPD0RST_Pos) + +#define NUMAKER_LPPDMA0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPPDMA0RST_Pos) +#define NUMAKER_LPGPIO_RST ((0x80UL<<24) | LPSCC_IPRST0_LPGPIORST_Pos) +#define NUMAKER_LPSRAM_RST ((0x80UL<<24) | LPSCC_IPRST0_LPSRAMRST_Pos) +#define NUMAKER_WDT_RST ((0x80UL<<24) | LPSCC_IPRST0_WDTRST_Pos) +#define NUMAKER_LPSPI0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPSPI0RST_Pos) +#define NUMAKER_LPI2C0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPI2C0RST_Pos) +#define NUMAKER_LPUART0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPUART0RST_Pos) +#define NUMAKER_LPTMR0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPTMR0RST_Pos) +#define NUMAKER_LPTMR1_RST ((0x80UL<<24) | LPSCC_IPRST0_LPTMR1RST_Pos) +#define NUMAKER_TTMR0_RST ((0x80UL<<24) | LPSCC_IPRST0_TTMR0RST_Pos) +#define NUMAKER_TTMR1_RST ((0x80UL<<24) | LPSCC_IPRST0_TTMR1RST_Pos) +#define NUMAKER_LPADC0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPADC0RST_Pos) +#define NUMAKER_OPA_RST ((0x80UL<<24) | LPSCC_IPRST0_OPARST_Pos) + +/* End of M2L31 BSP sys.h reset module copy */ + +#endif diff --git a/soc/nuvoton/numaker/m2l31x/CMakeLists.txt b/soc/nuvoton/numaker/m2l31x/CMakeLists.txt new file mode 100644 index 00000000000..c1295bf59ad --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/numaker/m2l31x/Kconfig b/soc/nuvoton/numaker/m2l31x/Kconfig new file mode 100644 index 00000000000..04b7eba5765 --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_M2L31X + select ARM + select CPU_CORTEX_M23 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_DWT + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + +config SOC_M2L31XXX + select HAS_NUMAKER_HAL diff --git a/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig b/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig new file mode 100644 index 00000000000..906b3b02dc3 --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_M2L31X + +rsource "Kconfig.defconfig.m2l31*" + +endif # SOC_SERIES_M2L31X diff --git a/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig.m2l31xxx b/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig.m2l31xxx new file mode 100644 index 00000000000..42160f9e8ce --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig.m2l31xxx @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_M2L31XXX + +config NUM_IRQS + default 143 + +endif # SOC_M2L31XXX diff --git a/soc/nuvoton/numaker/m2l31x/Kconfig.soc b/soc/nuvoton/numaker/m2l31x/Kconfig.soc new file mode 100644 index 00000000000..c9ce4c857c5 --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/Kconfig.soc @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_M2L31X + bool + select SOC_FAMILY_NUMAKER + help + Enable support for Nuvoton M2L31X MCU series + +config SOC_M2L31XXX + bool + select SOC_SERIES_M2L31X + +config SOC_SERIES + default "m2l31x" if SOC_SERIES_M2L31X + +config SOC + default "m2l31xxx" if SOC_M2L31XXX diff --git a/soc/nuvoton/numaker/m2l31x/soc.c b/soc/nuvoton/numaker/m2l31x/soc.c new file mode 100644 index 00000000000..e766b27cda9 --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/soc.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +/* Hardware and starter kit includes. */ +#include + +void z_arm_platform_init(void) +{ + SystemInit(); + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* + * ------------------- + * Init System Clock + * ------------------- + */ + +#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt) + /* Enable/disable 4~24 MHz external crystal oscillator (HXT) */ + if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_ENABLE) { + CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_DISABLE) { + CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk); + } +#endif + +#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt) + /* Enable/disable 32.768 kHz low-speed external crystal oscillator (LXT) */ + if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_ENABLE) { + CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk); + /* Wait for LXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); + } else if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_DISABLE) { + CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk); + } +#endif + + /* Enable 12 MHz high-speed internal RC oscillator (HIRC) */ + CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Enable 32 KHz low-speed internal RC oscillator (LIRC) */ + CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); + /* Wait for LIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); + +#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48) + /* Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48) */ + if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_ENABLE) { + CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk); + /* Wait for HIRC48 clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk); + } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_DISABLE) { + CLK_DisableXtalRC(CLK_PWRCTL_HIRC48EN_Msk); + } +#endif + +#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv) + /* Set CLK_PCLKDIV register on request */ + CLK->PCLKDIV = DT_PROP(DT_NODELABEL(scc), clk_pclkdiv); +#endif + +#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), core_clock) + /* Set core clock (HCLK) on request */ + CLK_SetCoreClock(DT_PROP(DT_NODELABEL(scc), core_clock)); +#endif + + /* + * Update System Core Clock + * User can use SystemCoreClockUpdate() to calculate SystemCoreClock. + */ + SystemCoreClockUpdate(); + + /* Lock protected registers */ + SYS_LockReg(); +} diff --git a/soc/nuvoton/numaker/m2l31x/soc.h b/soc/nuvoton/numaker/m2l31x/soc.h new file mode 100644 index 00000000000..5381d369676 --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/soc.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_NUVOTON_M2L31X_SOC_H_ +#define ZEPHYR_SOC_ARM_NUVOTON_M2L31X_SOC_H_ + +/* Hardware and starter kit includes. */ +#include + +#endif /* ZEPHYR_SOC_ARM_NUVOTON_M2L31X_SOC_H_*/ diff --git a/soc/nuvoton/numaker/soc.yml b/soc/nuvoton/numaker/soc.yml index cad8f6d1fc4..ec1059c497f 100644 --- a/soc/nuvoton/numaker/soc.yml +++ b/soc/nuvoton/numaker/soc.yml @@ -4,3 +4,6 @@ family: - name: m46x socs: - name: m467 + - name: m2l31x + socs: + - name: m2l31xxx From 47ed29bf49129bd8f6d1099e7632d3c793fd44cb Mon Sep 17 00:00:00 2001 From: cyliang tw Date: Mon, 11 Mar 2024 16:33:47 +0800 Subject: [PATCH 0404/2402] drivers: flash: support for Nuvoton numaker series RMC Add Nuvoton numaker series flash memory controller(RMC) with erase, read & write features of soc-flash. Signed-off-by: cyliang tw --- drivers/flash/CMakeLists.txt | 1 + drivers/flash/Kconfig | 2 + drivers/flash/Kconfig.numaker_rmc | 16 + drivers/flash/soc_flash_numaker_rmc.c | 275 ++++++++++++++++++ .../flash_controller/nuvoton,numaker-rmc.yaml | 9 + modules/Kconfig.nuvoton | 4 + west.yml | 2 +- 7 files changed, 308 insertions(+), 1 deletion(-) create mode 100644 drivers/flash/Kconfig.numaker_rmc create mode 100644 drivers/flash/soc_flash_numaker_rmc.c create mode 100644 dts/bindings/flash_controller/nuvoton,numaker-rmc.yaml diff --git a/drivers/flash/CMakeLists.txt b/drivers/flash/CMakeLists.txt index 98f24ff123c..ac7564c4708 100644 --- a/drivers/flash/CMakeLists.txt +++ b/drivers/flash/CMakeLists.txt @@ -130,3 +130,4 @@ zephyr_library_sources_ifdef(CONFIG_FLASH_INFINEON_CAT1 flash_ifx_cat1.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NUMAKER soc_flash_numaker.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_RRAM soc_flash_nrf_rram.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_MRAM soc_flash_nrf_mram.c) +zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NUMAKER_RMC soc_flash_numaker_rmc.c) diff --git a/drivers/flash/Kconfig b/drivers/flash/Kconfig index 0c24890d44d..6a1f816aa55 100644 --- a/drivers/flash/Kconfig +++ b/drivers/flash/Kconfig @@ -165,4 +165,6 @@ source "drivers/flash/Kconfig.nrf_rram" source "drivers/flash/Kconfig.nrf_mram" +source "drivers/flash/Kconfig.numaker_rmc" + endif # FLASH diff --git a/drivers/flash/Kconfig.numaker_rmc b/drivers/flash/Kconfig.numaker_rmc new file mode 100644 index 00000000000..ae149115255 --- /dev/null +++ b/drivers/flash/Kconfig.numaker_rmc @@ -0,0 +1,16 @@ +# NUMAKER GPIO driver configuration options + +# Copyright (c) 2024 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FLASH_NUMAKER_RMC + bool "Nuvoton NuMaker MCU embedded RRAM memory controller" + default y + select FLASH_HAS_PAGE_LAYOUT + select FLASH_HAS_DRIVER_ENABLED + select HAS_NUMAKER_RMC + depends on DT_HAS_NUVOTON_NUMAKER_RMC_ENABLED + help + This option enables the RMC driver for Nuvoton NuMaker family of + processors. + Say y if you wish to enable NuMaker RMC. diff --git a/drivers/flash/soc_flash_numaker_rmc.c b/drivers/flash/soc_flash_numaker_rmc.c new file mode 100644 index 00000000000..7e7d81f348b --- /dev/null +++ b/drivers/flash/soc_flash_numaker_rmc.c @@ -0,0 +1,275 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Nuvoton Technology Corporation. + */ + +#define DT_DRV_COMPAT nuvoton_numaker_rmc + +#include +#include +#include +#include +#include +#include +#include "flash_priv.h" +#include + +LOG_MODULE_REGISTER(flash_numaker_rmc, CONFIG_FLASH_LOG_LEVEL); + +#define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash) +#define SOC_NV_FLASH_WRITE_BLOCK_SIZE DT_PROP_OR(SOC_NV_FLASH_NODE, write_block_size, 0x04) + +struct flash_numaker_data { + RMC_T *rmc; + struct k_sem write_lock; + uint32_t flash_block_base; +}; + +static const struct flash_parameters flash_numaker_parameters = { + .write_block_size = SOC_NV_FLASH_WRITE_BLOCK_SIZE, + .erase_value = 0xff, +}; + +/* Validate offset and length */ +static bool flash_numaker_is_range_valid(off_t offset, size_t len) +{ + uint32_t aprom_size = RMC_APROM_END - RMC_APROM_BASE; + + /* check for min value */ + if ((offset < 0) || (len == 0)) { + return false; + } + + /* check for max value */ + if (offset >= aprom_size || len > aprom_size || (aprom_size - offset) < len) { + return false; + } + + return true; +} + +/* + * Erase a flash memory area. + * + * param dev Device struct + * param offset The address's offset + * param len The size of the buffer + * return 0 on success + * return -EINVAL erroneous code + */ + +static int flash_numaker_erase(const struct device *dev, off_t offset, size_t len) +{ + struct flash_numaker_data *dev_data = dev->data; + uint32_t rc = 0; + unsigned int key; + int page_nums = len / RMC_FLASH_PAGE_SIZE; + uint32_t addr = dev_data->flash_block_base + offset; + + /* return SUCCESS for len == 0 (required by tests/drivers/flash) */ + if (len == 0) { + return 0; + } + + /* Validate range */ + if (!flash_numaker_is_range_valid(offset, len)) { + return -EINVAL; + } + + /* check alignment and erase only by pages */ + if (((addr % RMC_FLASH_PAGE_SIZE) != 0) || ((len % RMC_FLASH_PAGE_SIZE) != 0)) { + return -EINVAL; + } + + /* take semaphore */ + if (k_sem_take(&dev_data->write_lock, K_NO_WAIT)) { + return -EACCES; + } + + SYS_UnlockReg(); + key = irq_lock(); + while (page_nums) { + /* erase page */ + if (RMC_Erase(addr)) { + LOG_ERR("Erase flash page failed or erase time-out"); + rc = -EIO; + goto done; + } + page_nums--; + addr += RMC_FLASH_PAGE_SIZE; + } + +done: + SYS_LockReg(); + irq_unlock(key); + /* release semaphore */ + k_sem_give(&dev_data->write_lock); + + return rc; +} + +/* + * Read a flash memory area. + * + * param dev Device struct + * param offset The address's offset + * param data The buffer to store or read the value + * param length The size of the buffer + * return 0 on success, + * return -EIO erroneous code + */ +static int flash_numaker_read(const struct device *dev, off_t offset, void *data, size_t len) +{ + struct flash_numaker_data *dev_data = dev->data; + uint32_t addr = dev_data->flash_block_base + offset; + + /* return SUCCESS for len == 0 (required by tests/drivers/flash) */ + if (len == 0) { + return 0; + } + + /* Validate range */ + if (!flash_numaker_is_range_valid(offset, len)) { + return -EINVAL; + } + + /* read flash */ + memcpy(data, (void *)addr, len); + + return 0; +} + +static int32_t flash_numaker_block_write(uint32_t u32_addr, const uint8_t *pu8_data, int block_size) +{ + int32_t retval; + const uint32_t *pu32_data = (const uint32_t *)pu8_data; + + SYS_UnlockReg(); + if (block_size == 4) { + retval = RMC_Write(u32_addr, *pu32_data); + } else if (block_size == 8) { + retval = RMC_Write(u32_addr, *pu32_data) | + RMC_Write(u32_addr + 4, *(pu32_data + 1)); + } else { + retval = -1; + } + SYS_LockReg(); + + return retval; +} + +static int flash_numaker_write(const struct device *dev, off_t offset, const void *data, size_t len) +{ + struct flash_numaker_data *dev_data = dev->data; + uint32_t rc = 0; + unsigned int key; + uint32_t addr = dev_data->flash_block_base + offset; + int block_size = flash_numaker_parameters.write_block_size; + int blocks = len / flash_numaker_parameters.write_block_size; + const uint8_t *pu8_data = (const uint8_t *)data; + + /* return SUCCESS for len == 0 (required by tests/drivers/flash) */ + if (len == 0) { + return 0; + } + + /* Validate range */ + if (!flash_numaker_is_range_valid(offset, len)) { + return -EINVAL; + } + + /* Validate address alignment */ + if ((addr % flash_numaker_parameters.write_block_size) != 0) { + return -EINVAL; + } + + /* Validate write size be multiples of the write block size */ + if ((len % block_size) != 0) { + return -EINVAL; + } + + /* Validate offset be multiples of the write block size */ + if ((offset % block_size) != 0) { + return -EINVAL; + } + + if (k_sem_take(&dev_data->write_lock, K_FOREVER)) { + return -EACCES; + } + + key = irq_lock(); + + while (blocks) { + if (flash_numaker_block_write(addr, pu8_data, block_size)) { + rc = -EIO; + goto done; + } + pu8_data += block_size; + addr += block_size; + blocks--; + } + +done: + irq_unlock(key); + + k_sem_give(&dev_data->write_lock); + + return rc; +} + +#if defined(CONFIG_FLASH_PAGE_LAYOUT) +static const struct flash_pages_layout dev_layout = { + .pages_count = DT_REG_SIZE(SOC_NV_FLASH_NODE) / + DT_PROP(SOC_NV_FLASH_NODE, erase_block_size), + .pages_size = DT_PROP(SOC_NV_FLASH_NODE, erase_block_size), +}; + +static void flash_numaker_pages_layout(const struct device *dev, + const struct flash_pages_layout **layout, + size_t *layout_size) +{ + *layout = &dev_layout; + *layout_size = 1; +} +#endif /* CONFIG_FLASH_PAGE_LAYOUT */ + +static const struct flash_parameters *flash_numaker_get_parameters(const struct device *dev) +{ + ARG_UNUSED(dev); + + return &flash_numaker_parameters; +} + +static struct flash_numaker_data flash_data; + +static const struct flash_driver_api flash_numaker_api = { + .erase = flash_numaker_erase, + .write = flash_numaker_write, + .read = flash_numaker_read, + .get_parameters = flash_numaker_get_parameters, +#if defined(CONFIG_FLASH_PAGE_LAYOUT) + .page_layout = flash_numaker_pages_layout, +#endif +}; + +static int flash_numaker_init(const struct device *dev) +{ + struct flash_numaker_data *dev_data = dev->data; + + k_sem_init(&dev_data->write_lock, 1, 1); + + /* Enable RMC ISP function */ + SYS_UnlockReg(); + RMC_Open(); + /* Enable APROM update. */ + RMC_ENABLE_AP_UPDATE(); + SYS_LockReg(); + dev_data->flash_block_base = (uint32_t)RMC_APROM_BASE; + dev_data->rmc = (RMC_T *)DT_REG_ADDR(DT_NODELABEL(rmc)); + + return 0; +} + +DEVICE_DT_INST_DEFINE(0, flash_numaker_init, NULL, &flash_data, NULL, POST_KERNEL, + CONFIG_FLASH_INIT_PRIORITY, &flash_numaker_api); diff --git a/dts/bindings/flash_controller/nuvoton,numaker-rmc.yaml b/dts/bindings/flash_controller/nuvoton,numaker-rmc.yaml new file mode 100644 index 00000000000..b41aad238a6 --- /dev/null +++ b/dts/bindings/flash_controller/nuvoton,numaker-rmc.yaml @@ -0,0 +1,9 @@ +description: Nuvoton NuMaker RRAM Memory Controller + +compatible: "nuvoton,numaker-rmc" + +include: flash-controller.yaml + +properties: + reg: + required: true diff --git a/modules/Kconfig.nuvoton b/modules/Kconfig.nuvoton index bc4ac6d158f..33dabc67f84 100644 --- a/modules/Kconfig.nuvoton +++ b/modules/Kconfig.nuvoton @@ -71,4 +71,8 @@ menu "Nuvoton NuMaker drivers" bool "NuMaker ADC" help Enable Nuvoton ADC HAL module driver + config HAS_NUMAKER_RMC + bool "NuMaker RMC" + help + Enable Nuvoton RMC HAL module driver endmenu diff --git a/west.yml b/west.yml index 0dbb65acb62..2acf74dcc20 100644 --- a/west.yml +++ b/west.yml @@ -188,7 +188,7 @@ manifest: groups: - hal - name: hal_nuvoton - revision: 68a91bb343ff47e40dbd9189a7d6e3ee801a7135 + revision: cf24f9ebd893b349cec439ef7eaac6554a6b6d6f path: modules/hal/nuvoton groups: - hal From 0418179b12d438cce271fdc594f3fdddd8bef866 Mon Sep 17 00:00:00 2001 From: Georgij Cernysiov Date: Fri, 1 Mar 2024 23:33:17 +0100 Subject: [PATCH 0405/2402] dts: stm32h723.dtsi: fix timers23 address format Fixes: simple-bus unit address format error, expected "4000e000". Signed-off-by: Georgij Cernysiov --- dts/arm/st/h7/stm32h723.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/arm/st/h7/stm32h723.dtsi b/dts/arm/st/h7/stm32h723.dtsi index 88e828bb9a4..0a7d8a3fe61 100644 --- a/dts/arm/st/h7/stm32h723.dtsi +++ b/dts/arm/st/h7/stm32h723.dtsi @@ -136,7 +136,7 @@ }; }; - timers23: timers@0x4000e000 { + timers23: timers@4000e000 { compatible = "st,stm32-timers"; reg = <0x4000e000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x01000000>; From 6ce38c1aa72dd636931a5ab8c0a999949ea02263 Mon Sep 17 00:00:00 2001 From: Nithin Ramesh Myliattil Date: Mon, 12 Feb 2024 16:05:16 +0100 Subject: [PATCH 0406/2402] bluetooth: id: fix adv sets with same id use different RPA The fix is to check if any of the adv set's rpa expired callback returns false, then all adv sets continues with the old RPA. Note: Fix is applicable only to adv sets which shares the same id. Signed-off-by: Nithin Ramesh Myliattil --- include/zephyr/bluetooth/bluetooth.h | 4 + subsys/bluetooth/host/id.c | 59 +++++- tests/bsim/bluetooth/host/compile.sh | 1 + .../host/privacy/peripheral/CMakeLists.txt | 8 +- .../privacy/peripheral/prj_rpa_expired.conf | 25 +++ .../privacy/peripheral/prj_rpa_sharing.conf | 1 - .../privacy/peripheral/src/dut_rpa_expired.c | 178 ++++++++++++++++++ .../src/{dut.c => dut_rpa_rotation.c} | 0 .../host/privacy/peripheral/src/main.c | 29 +-- .../privacy/peripheral/src/main_rpa_expired.c | 32 ++++ .../peripheral/src/main_rpa_rotation.c | 32 ++++ .../peripheral/src/tester_rpa_expired.c | 124 ++++++++++++ .../src/{tester.c => tester_rpa_rotation.c} | 0 .../test_scripts/run_test_rpa_expired.sh | 32 ++++ 14 files changed, 489 insertions(+), 36 deletions(-) create mode 100644 tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_expired.conf create mode 100644 tests/bsim/bluetooth/host/privacy/peripheral/src/dut_rpa_expired.c rename tests/bsim/bluetooth/host/privacy/peripheral/src/{dut.c => dut_rpa_rotation.c} (100%) create mode 100644 tests/bsim/bluetooth/host/privacy/peripheral/src/main_rpa_expired.c create mode 100644 tests/bsim/bluetooth/host/privacy/peripheral/src/main_rpa_rotation.c create mode 100644 tests/bsim/bluetooth/host/privacy/peripheral/src/tester_rpa_expired.c rename tests/bsim/bluetooth/host/privacy/peripheral/src/{tester.c => tester_rpa_rotation.c} (100%) create mode 100755 tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh diff --git a/include/zephyr/bluetooth/bluetooth.h b/include/zephyr/bluetooth/bluetooth.h index 0cfad9b1f6b..073c46a1c08 100644 --- a/include/zephyr/bluetooth/bluetooth.h +++ b/include/zephyr/bluetooth/bluetooth.h @@ -156,6 +156,10 @@ struct bt_le_ext_adv_cb { * the advertising set has expired. The user can use this callback * to synchronize the advertising payload update with the RPA rotation. * + * If rpa sharing is enabled and rpa expired cb of any adv-sets belonging + * to same adv id returns false, then adv-sets will continue with old rpa + * through out the rpa rotations. + * * @param adv The advertising set object. * * @return true to rotate the current RPA, or false to use it for the diff --git a/subsys/bluetooth/host/id.c b/subsys/bluetooth/host/id.c index b830c88ffaf..c49e42bf508 100644 --- a/subsys/bluetooth/host/id.c +++ b/subsys/bluetooth/host/id.c @@ -198,10 +198,13 @@ int bt_id_set_adv_random_addr(struct bt_le_ext_adv *adv, return 0; } -static void adv_rpa_expired(struct bt_le_ext_adv *adv) +/* If rpa sharing is enabled, then rpa expired cb of adv-sets belonging + * to same id is verified to return true. If not, adv-sets will continue + * with old rpa through out the rpa rotations. + */ +static void adv_rpa_expired(struct bt_le_ext_adv *adv, void *data) { bool rpa_invalid = true; - #if defined(CONFIG_BT_EXT_ADV) && defined(CONFIG_BT_PRIVACY) /* Notify the user about the RPA timeout and set the RPA validity. */ if (atomic_test_bit(adv->flags, BT_ADV_RPA_VALID) && @@ -209,12 +212,21 @@ static void adv_rpa_expired(struct bt_le_ext_adv *adv) rpa_invalid = adv->cb->rpa_expired(adv); } #endif - if (rpa_invalid) { - atomic_clear_bit(adv->flags, BT_ADV_RPA_VALID); -#if defined(CONFIG_BT_RPA_SHARING) - bt_addr_copy(&bt_dev.rpa[adv->id], BT_ADDR_NONE); -#endif + if (IS_ENABLED(CONFIG_BT_RPA_SHARING)) { + + if (adv->id >= bt_dev.id_count) { + return; + } + bool *rpa_invalid_set_ptr = data; + + if (!rpa_invalid) { + rpa_invalid_set_ptr[adv->id] = false; + } + } else { + if (rpa_invalid) { + atomic_clear_bit(adv->flags, BT_ADV_RPA_VALID); + } } } @@ -225,10 +237,27 @@ static void adv_rpa_invalidate(struct bt_le_ext_adv *adv, void *data) */ if (!atomic_test_bit(adv->flags, BT_ADV_LIMITED) && !atomic_test_bit(adv->flags, BT_ADV_USE_IDENTITY)) { - adv_rpa_expired(adv); + adv_rpa_expired(adv, data); } } +#if defined(CONFIG_BT_RPA_SHARING) +static void adv_rpa_clear_data(struct bt_le_ext_adv *adv, void *data) +{ + if (adv->id >= bt_dev.id_count) { + return; + } + bool *rpa_invalid_set_ptr = data; + + if (rpa_invalid_set_ptr[adv->id]) { + atomic_clear_bit(adv->flags, BT_ADV_RPA_VALID); + bt_addr_copy(&bt_dev.rpa[adv->id], BT_ADDR_NONE); + } else { + LOG_WRN("Adv sets rpa expired cb with id %d returns false\n", adv->id); + } +} +#endif + static void le_rpa_invalidate(void) { /* Invalidate RPA */ @@ -238,7 +267,17 @@ static void le_rpa_invalidate(void) } if (IS_ENABLED(CONFIG_BT_BROADCASTER)) { - bt_le_ext_adv_foreach(adv_rpa_invalidate, NULL); + + if (bt_dev.id_count == 0) { + return; + } + bool rpa_expired_data[bt_dev.id_count]; + + bt_le_ext_adv_foreach(adv_rpa_invalidate, &rpa_expired_data); +#if defined(CONFIG_BT_RPA_SHARING) + /* rpa_expired data collected. now clear data based on data collected. */ + bt_le_ext_adv_foreach(adv_rpa_clear_data, &rpa_expired_data); +#endif } } @@ -769,7 +808,7 @@ bool bt_id_adv_random_addr_check(const struct bt_le_adv_param *param) void bt_id_adv_limited_stopped(struct bt_le_ext_adv *adv) { - adv_rpa_expired(adv); + adv_rpa_expired(adv, NULL); } #if defined(CONFIG_BT_SMP) diff --git a/tests/bsim/bluetooth/host/compile.sh b/tests/bsim/bluetooth/host/compile.sh index dea5ae073aa..f2a61050216 100755 --- a/tests/bsim/bluetooth/host/compile.sh +++ b/tests/bsim/bluetooth/host/compile.sh @@ -37,6 +37,7 @@ app=tests/bsim/bluetooth/host/misc/unregister_conn_cb compile app=tests/bsim/bluetooth/host/privacy/central compile app=tests/bsim/bluetooth/host/privacy/peripheral compile +app=tests/bsim/bluetooth/host/privacy/peripheral conf_file=prj_rpa_expired.conf compile app=tests/bsim/bluetooth/host/privacy/peripheral conf_file=prj_rpa_sharing.conf compile app=tests/bsim/bluetooth/host/privacy/device compile app=tests/bsim/bluetooth/host/privacy/legacy compile diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/CMakeLists.txt b/tests/bsim/bluetooth/host/privacy/peripheral/CMakeLists.txt index a44cd8b685d..8b6bee0ccf0 100644 --- a/tests/bsim/bluetooth/host/privacy/peripheral/CMakeLists.txt +++ b/tests/bsim/bluetooth/host/privacy/peripheral/CMakeLists.txt @@ -7,9 +7,13 @@ project(bsim_test_rpa_peripheral) target_sources(app PRIVATE src/bs_bt_utils.c - src/tester.c + src/tester_rpa_rotation.c + src/tester_rpa_expired.c src/main.c - src/dut.c + src/main_rpa_rotation.c + src/main_rpa_expired.c + src/dut_rpa_rotation.c + src/dut_rpa_expired.c ) zephyr_include_directories( diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_expired.conf b/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_expired.conf new file mode 100644 index 00000000000..dcab4bc5686 --- /dev/null +++ b/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_expired.conf @@ -0,0 +1,25 @@ +CONFIG_BT=y +CONFIG_BT_PERIPHERAL=y +CONFIG_BT_CENTRAL=y +CONFIG_BT_SMP=y +CONFIG_ASSERT=y + +CONFIG_BT_EXT_ADV=y +CONFIG_BT_PRIVACY=y +CONFIG_BT_RPA_TIMEOUT=10 +CONFIG_BT_EXT_ADV_MAX_ADV_SET=4 +CONFIG_BT_CTLR_ADVANCED_FEATURES=y +CONFIG_BT_CTLR_ADV_DATA_BUF_MAX=4 +CONFIG_BT_ID_MAX=3 + +CONFIG_FLASH=y +CONFIG_FLASH_PAGE_LAYOUT=y +CONFIG_FLASH_MAP=y +CONFIG_NVS=y +CONFIG_SETTINGS=y +CONFIG_BT_SETTINGS=y +# Increased stack due to settings API usage +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048 + +# Enable the RPA sharing mode +CONFIG_BT_RPA_SHARING=y diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_sharing.conf b/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_sharing.conf index bebce9933ca..208efda9c7f 100644 --- a/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_sharing.conf +++ b/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_sharing.conf @@ -18,7 +18,6 @@ CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y CONFIG_BT_SETTINGS=y - # Increased stack due to settings API usage CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048 diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/src/dut_rpa_expired.c b/tests/bsim/bluetooth/host/privacy/peripheral/src/dut_rpa_expired.c new file mode 100644 index 00000000000..9e6b99d537d --- /dev/null +++ b/tests/bsim/bluetooth/host/privacy/peripheral/src/dut_rpa_expired.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bs_bt_utils.h" + +#include +#include + +#include +#include +#include +#include +#include + +#include "common/bt_str.h" + +#define ID_1 1 +#define ID_2 2 + +#define ADV_SET_INDEX_1 0x00 +#define ADV_SET_INDEX_2 0x01 +#define ADV_SET_INDEX_3 0x02 +#define ADV_SET_INDEX_4 0x03 + +static struct bt_le_ext_adv *adv_set[CONFIG_BT_EXT_ADV_MAX_ADV_SET]; + + static const struct bt_data ad_id[] = { + BT_DATA_BYTES(BT_DATA_MANUFACTURER_DATA, ADV_SET_INDEX_1), + BT_DATA_BYTES(BT_DATA_MANUFACTURER_DATA, ADV_SET_INDEX_2), + BT_DATA_BYTES(BT_DATA_MANUFACTURER_DATA, ADV_SET_INDEX_3), + BT_DATA_BYTES(BT_DATA_MANUFACTURER_DATA, ADV_SET_INDEX_4), +}; + +bool rpa_expired_cb_returns_true(struct bt_le_ext_adv *adv) +{ + /* Return true to rotate the current RPA */ + int err; + struct bt_le_ext_adv_info info; + + err = bt_le_ext_adv_get_info(adv, &info); + if (err) { + return false; + } + printk("%s advertiser[%d] RPA %s\n", __func__, info.id, bt_addr_le_str(info.addr)); + + return true; +} + +bool rpa_expired_cb_returns_false(struct bt_le_ext_adv *adv) +{ + /* Return false not to rotate the current RPA */ + int err; + struct bt_le_ext_adv_info info; + + err = bt_le_ext_adv_get_info(adv, &info); + if (err) { + return false; + } + printk("%s advertiser[%d] RPA %s\n", __func__, info.id, bt_addr_le_str(info.addr)); + + return false; +} + +static void create_adv(struct bt_le_ext_adv **adv, int id, bool expired_return) +{ + int err; + struct bt_le_adv_param params; + static struct bt_le_ext_adv_cb cb_adv[] = { + {.rpa_expired = rpa_expired_cb_returns_true}, + {.rpa_expired = rpa_expired_cb_returns_false} + }; + + memset(¶ms, 0, sizeof(struct bt_le_adv_param)); + + params.options |= BT_LE_ADV_OPT_EXT_ADV; + params.id = id; + params.sid = 0; + params.interval_min = BT_GAP_ADV_FAST_INT_MIN_1; + params.interval_max = BT_GAP_ADV_FAST_INT_MAX_1; + + err = bt_le_ext_adv_create(¶ms, expired_return ? &cb_adv[0] : &cb_adv[1], adv); + if (err) { + FAIL("Failed to create advertiser (%d)\n", err); + } +} + +void start_rpa_advertising(void) +{ + int err; + size_t bt_id_count; + + /* Enable bluetooth */ + err = bt_enable(NULL); + if (err) { + FAIL("Failed to enable bluetooth (err %d\n)", err); + } + + err = settings_load(); + if (err) { + FAIL("Failed to enable settings (err %d\n)", err); + } + + bt_id_get(NULL, &bt_id_count); + + if (bt_id_count == 1) { + int id_a; + int id_b; + + printk("No extra identity found in settings, creating new ones...\n"); + + id_a = bt_id_create(NULL, NULL); + if (id_a != ID_1) { + FAIL("bt_id_create id_a failed (err %d)\n", id_a); + } + + id_b = bt_id_create(NULL, NULL); + if (id_b != ID_2) { + FAIL("bt_id_create id_b failed (err %d)\n", id_b); + } + } else { + printk("Extra identities loaded from settings\n"); + } + + bt_id_get(NULL, &bt_id_count); + if (bt_id_count != CONFIG_BT_ID_MAX) { + FAIL("bt_id_get returned incorrect number of identities %u\n", bt_id_count); + } + + for (int i = 0; i < CONFIG_BT_EXT_ADV_MAX_ADV_SET; i++) { + /* Create first 2 advertising sets with one id and for both sets,rpa_expied_cb + * returns true. + * Create remaining 2 sets with different id and last adv set's rpa_expired cb + * returns false. + * + * So for first two adv sets with same id new rpa's will be generated every + * rotation and for last two adv sets with same id, rpa will continue with + * only one rpa through out the rotations since one of the adv set returned + * false. + */ + switch (i) { + case ADV_SET_INDEX_1: + case ADV_SET_INDEX_2: + create_adv(&adv_set[i], ID_1, true); + break; + case ADV_SET_INDEX_3: + create_adv(&adv_set[i], ID_2, true); + break; + case ADV_SET_INDEX_4: + create_adv(&adv_set[i], ID_2, false); + break; + default: + printk("Shouldn't be here\n"); + break; + } + + /* Set extended advertising data */ + err = bt_le_ext_adv_set_data(adv_set[i], &ad_id[i], 1, NULL, 0); + if (err) { + FAIL("Failed to set advertising data for set %d (err %d)\n", i, err); + } + + err = bt_le_ext_adv_start(adv_set[i], BT_LE_EXT_ADV_START_DEFAULT); + if (err) { + FAIL("Failed to start advertising (err %d)\n", err); + } + } +} + +void dut_rpa_expired_procedure(void) +{ + start_rpa_advertising(); + + /* Nothing to do */ + PASS("PASS\n"); +} diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/src/dut.c b/tests/bsim/bluetooth/host/privacy/peripheral/src/dut_rpa_rotation.c similarity index 100% rename from tests/bsim/bluetooth/host/privacy/peripheral/src/dut.c rename to tests/bsim/bluetooth/host/privacy/peripheral/src/dut_rpa_rotation.c diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/src/main.c b/tests/bsim/bluetooth/host/privacy/peripheral/src/main.c index 91a4f3a03db..b84a1787636 100644 --- a/tests/bsim/bluetooth/host/privacy/peripheral/src/main.c +++ b/tests/bsim/bluetooth/host/privacy/peripheral/src/main.c @@ -7,32 +7,15 @@ #include "bs_bt_utils.h" #include "bstests.h" -void tester_procedure(void); -void dut_procedure(void); +extern struct bst_test_list *test_main_rpa_rotation_install(struct bst_test_list *tests); +extern struct bst_test_list *test_main_rpa_expired_install(struct bst_test_list *tests); -static const struct bst_test_instance test_to_add[] = { - { - .test_id = "central", - .test_post_init_f = test_init, - .test_tick_f = test_tick, - .test_main_f = tester_procedure, - }, - { - .test_id = "peripheral", - .test_post_init_f = test_init, - .test_tick_f = test_tick, - .test_main_f = dut_procedure, - }, - BSTEST_END_MARKER, +bst_test_install_t test_installers[] = { + test_main_rpa_rotation_install, + test_main_rpa_expired_install, + NULL, }; -static struct bst_test_list *install(struct bst_test_list *tests) -{ - return bst_add_tests(tests, test_to_add); -}; - -bst_test_install_t test_installers[] = {install, NULL}; - int main(void) { bst_main(); diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/src/main_rpa_expired.c b/tests/bsim/bluetooth/host/privacy/peripheral/src/main_rpa_expired.c new file mode 100644 index 00000000000..f580562d1f7 --- /dev/null +++ b/tests/bsim/bluetooth/host/privacy/peripheral/src/main_rpa_expired.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bs_bt_utils.h" +#include "bstests.h" + +void tester_verify_rpa_procedure(void); +void dut_rpa_expired_procedure(void); + +static const struct bst_test_instance test_to_add[] = { + { + .test_id = "central_rpa_check", + .test_post_init_f = test_init, + .test_tick_f = test_tick, + .test_main_f = tester_verify_rpa_procedure, + }, + { + .test_id = "peripheral_rpa_expired", + .test_post_init_f = test_init, + .test_tick_f = test_tick, + .test_main_f = dut_rpa_expired_procedure, + }, + BSTEST_END_MARKER, +}; + +struct bst_test_list *test_main_rpa_expired_install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, test_to_add); +}; diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/src/main_rpa_rotation.c b/tests/bsim/bluetooth/host/privacy/peripheral/src/main_rpa_rotation.c new file mode 100644 index 00000000000..282dd27f40d --- /dev/null +++ b/tests/bsim/bluetooth/host/privacy/peripheral/src/main_rpa_rotation.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bs_bt_utils.h" +#include "bstests.h" + +void tester_procedure(void); +void dut_procedure(void); + +static const struct bst_test_instance test_to_add[] = { + { + .test_id = "central", + .test_post_init_f = test_init, + .test_tick_f = test_tick, + .test_main_f = tester_procedure, + }, + { + .test_id = "peripheral", + .test_post_init_f = test_init, + .test_tick_f = test_tick, + .test_main_f = dut_procedure, + }, + BSTEST_END_MARKER, +}; + +struct bst_test_list *test_main_rpa_rotation_install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, test_to_add); +}; diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/src/tester_rpa_expired.c b/tests/bsim/bluetooth/host/privacy/peripheral/src/tester_rpa_expired.c new file mode 100644 index 00000000000..aa03a25436a --- /dev/null +++ b/tests/bsim/bluetooth/host/privacy/peripheral/src/tester_rpa_expired.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bs_bt_utils.h" +#include +#include +#include +#include +#include + +#define EXPECTED_NUM_ROTATIONS 5 + +struct adv_set_data_t { + bt_addr_le_t old_addr; + uint8_t rpa_rotations; + int64_t old_time; +}; + +static uint8_t adv_index; +static struct adv_set_data_t adv_set_data[CONFIG_BT_EXT_ADV_MAX_ADV_SET]; + +static bool data_cb(struct bt_data *data, void *user_data) +{ + switch (data->type) { + case BT_DATA_MANUFACTURER_DATA: + adv_index = data->data[0]; + return false; + default: + return true; + } +} + +static void test_address(bt_addr_le_t *addr) +{ + int64_t diff_ms; + static int64_t rpa_timeout_ms = CONFIG_BT_RPA_TIMEOUT * MSEC_PER_SEC; + + if (!BT_ADDR_IS_RPA(&addr->a)) { + FAIL("Bluetooth address is not RPA\n"); + } + + /* Only save the address if this is the first scan */ + if (bt_addr_le_eq(&adv_set_data[adv_index].old_addr, BT_ADDR_LE_ANY)) { + bt_addr_le_copy(&adv_set_data[adv_index].old_addr, addr); + adv_set_data[adv_index].old_time = 0; + return; + } + + diff_ms = k_uptime_get() - adv_set_data[adv_index].old_time; + + if (diff_ms < rpa_timeout_ms) { + return; + } + + adv_set_data[adv_index].rpa_rotations++; + + printk("Ad set %d Old ", adv_index); + print_address(&adv_set_data[adv_index].old_addr); + printk("Ad set %d New ", adv_index); + print_address(addr); + + /* Compare old and new address */ + if (adv_index < 2) { + if (bt_addr_le_eq(addr, &adv_set_data[adv_index].old_addr)) { + FAIL("New RPA should have been generated\n"); + } + } else { + if (!bt_addr_le_eq(addr, &adv_set_data[adv_index].old_addr)) { + FAIL("Adv sets should continue with old rpa\n"); + } + } + + if (adv_set_data[adv_index].rpa_rotations > EXPECTED_NUM_ROTATIONS) { + PASS("PASS\n"); + } + + adv_set_data[adv_index].old_time = k_uptime_get(); + bt_addr_le_copy(&adv_set_data[adv_index].old_addr, addr); +} + +static void cb_device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t type, + struct net_buf_simple *ad) +{ + bt_data_parse(ad, data_cb, NULL); + test_address((bt_addr_le_t *)addr); +} + +void start_rpa_scanning(void) +{ + /* Start passive scanning */ + struct bt_le_scan_param scan_param = { + .type = BT_HCI_LE_SCAN_PASSIVE, + .options = BT_LE_SCAN_OPT_FILTER_DUPLICATE, + .interval = 0x0040, + .window = 0x0020, + }; + + int err = bt_le_scan_start(&scan_param, cb_device_found); + + if (err) { + FAIL("Failed to start scanning"); + } +} + +void tester_verify_rpa_procedure(void) +{ + /* Enable bluetooth */ + int err = bt_enable(NULL); + + if (err) { + FAIL("Failed to enable bluetooth (err %d\n)", err); + } + + err = settings_load(); + if (err) { + FAIL("Failed to enable settings (err %d\n)", err); + } + + start_rpa_scanning(); + /* The rest of the test is driven by the callback */ +} diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/src/tester.c b/tests/bsim/bluetooth/host/privacy/peripheral/src/tester_rpa_rotation.c similarity index 100% rename from tests/bsim/bluetooth/host/privacy/peripheral/src/tester.c rename to tests/bsim/bluetooth/host/privacy/peripheral/src/tester_rpa_rotation.c diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh new file mode 100755 index 00000000000..73d1e199de9 --- /dev/null +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh @@ -0,0 +1,32 @@ +#!/usr/bin/env bash +# Copyright 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +set -eu +bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" + +source "${bash_source_dir}/_env.sh" +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +verbosity_level=2 +simulation_id="rpa_expired" +EXECUTE_TIMEOUT=30 + +cd ${BSIM_OUT_PATH}/bin + +central_exe_rpa_expired="\ +${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_privacy_peripheral_prj_rpa_expired_conf" +peripheral_exe_rpa_expired="${central_exe_rpa_expired}" + +Execute "$central_exe_rpa_expired" \ + -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central_rpa_check \ + -RealEncryption=1 -flash="${simulation_id}.central.log.bin" -flash_erase + +Execute "$peripheral_exe_rpa_expired" \ + -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral_rpa_expired \ + -RealEncryption=1 -flash="${simulation_id}.peripheral.log.bin" -flash_erase + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ + -D=2 -sim_length=70e6 $@ + +wait_for_background_jobs From 6badcad883df4865ee69f5f50cdb1fa237515170 Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Mon, 5 Feb 2024 11:16:34 +0900 Subject: [PATCH 0407/2402] posix: Implement getmsg and getpmsg `getmsg()` and `getpmsg()` are required as part of _XOPEN_STREAMS Option Group. signed-off-by: Gaetan Perrot --- include/zephyr/posix/stropts.h | 2 ++ lib/posix/options/stropts.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/include/zephyr/posix/stropts.h b/include/zephyr/posix/stropts.h index de24435eef5..649f0d87b7a 100644 --- a/include/zephyr/posix/stropts.h +++ b/include/zephyr/posix/stropts.h @@ -20,6 +20,8 @@ struct strbuf { int putmsg(int fildes, const struct strbuf *ctlptr, const struct strbuf *dataptr, int flags); int fdetach(const char *path); int fattach(int fildes, const char *path); +int getmsg(int fildes, struct strbuf *ctlptr, struct strbuf *dataptr, int *flagsp); +int getpmsg(int fildes, struct strbuf *ctlptr, struct strbuf *dataptr, int *bandp, int *flagsp); #ifdef __cplusplus } diff --git a/lib/posix/options/stropts.c b/lib/posix/options/stropts.c index 9db1a790a45..66d44fcbb28 100644 --- a/lib/posix/options/stropts.c +++ b/lib/posix/options/stropts.c @@ -31,6 +31,29 @@ int fattach(int fildes, const char *path) { ARG_UNUSED(fildes); ARG_UNUSED(path); + errno = ENOSYS; + + return -1; +} + +int getmsg(int fildes, struct strbuf *ctlptr, struct strbuf *dataptr, int *flagsp) +{ + ARG_UNUSED(fildes); + ARG_UNUSED(ctlptr); + ARG_UNUSED(dataptr); + ARG_UNUSED(flagsp); + + errno = ENOSYS; + return -1; +} + +int getpmsg(int fildes, struct strbuf *ctlptr, struct strbuf *dataptr, int *bandp, int *flagsp) +{ + ARG_UNUSED(fildes); + ARG_UNUSED(ctlptr); + ARG_UNUSED(dataptr); + ARG_UNUSED(bandp); + ARG_UNUSED(flagsp); errno = ENOSYS; return -1; From dfefac820898fe1cfe3c540b444457c1640f074a Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Mon, 5 Feb 2024 11:17:57 +0900 Subject: [PATCH 0408/2402] doc: posix: mark getmsg and getpmsg as supported `getmsg()` and `getpmsg()` are now implemented, mark it so. There are place holder so will fail with ENOSYS. signed-off-by: Gaetan Perrot --- doc/services/portability/posix/option_groups/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst index 6b05b08cd2d..229ae6b5ec3 100644 --- a/doc/services/portability/posix/option_groups/index.rst +++ b/doc/services/portability/posix/option_groups/index.rst @@ -505,8 +505,8 @@ _XOPEN_STREAMS fattach(),yes (will fail with ``ENOSYS``:ref:`†`) fdetach(),yes (will fail with ``ENOSYS``:ref:`†`) - getmsg(), - getpmsg(), + getmsg(), yes (will fail with ``ENOSYS``:ref:`†`) + getpmsg(), yes (will fail with ``ENOSYS``:ref:`†`) ioctl(),yes isastream(), putmsg(), From 45f907b9fd50d0c12a7ab4e104c5cbcb5602dab5 Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Mon, 5 Feb 2024 11:18:49 +0900 Subject: [PATCH 0409/2402] posix: Implement test for getmsg and getpmsg Add tests for `getmsg()` and `getpmsg()` signed-off-by: Gaetan Perrot --- tests/posix/common/src/stropts.c | 22 ++++++++++++++++++++++ tests/posix/headers/src/stropts_h.c | 2 ++ 2 files changed, 24 insertions(+) diff --git a/tests/posix/common/src/stropts.c b/tests/posix/common/src/stropts.c index 4e2e5e25a17..a1c550062d6 100644 --- a/tests/posix/common/src/stropts.c +++ b/tests/posix/common/src/stropts.c @@ -37,4 +37,26 @@ ZTEST(stropts, test_fattach) zassert_equal(errno, ENOSYS, "Expected errno ENOSYS, got %d", errno); } +ZTEST(stropts, test_getmsg) +{ + struct strbuf *ctrl = NULL; + struct strbuf *data = NULL; + int fd = -1; + int ret = getmsg(fd, ctrl, data, 0); + + zassert_equal(ret, -1, "Expected return value -1, got %d", ret); + zassert_equal(errno, ENOSYS, "Expected errno ENOSYS, got %d", errno); +} + +ZTEST(stropts, test_getpmsg) +{ + struct strbuf *ctrl = NULL; + struct strbuf *data = NULL; + int fd = -1; + int ret = getpmsg(fd, ctrl, data, 0, 0); + + zassert_equal(ret, -1, "Expected return value -1, got %d", ret); + zassert_equal(errno, ENOSYS, "Expected errno ENOSYS, got %d", errno); +} + ZTEST_SUITE(stropts, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/posix/headers/src/stropts_h.c b/tests/posix/headers/src/stropts_h.c index 6f749d3aa3b..2cc5c7a859e 100644 --- a/tests/posix/headers/src/stropts_h.c +++ b/tests/posix/headers/src/stropts_h.c @@ -21,6 +21,8 @@ ZTEST(posix_headers, test_stropts_h) zassert_not_null((void *)putmsg, "putmsg is null"); zassert_not_null((void *)fdetach, "fdetach is null"); zassert_not_null((void *)fattach, "fattach is null"); + zassert_not_null((void *)getmsg, "getmsg is null"); + zassert_not_null((void *)getpmsg, "getpmsg is null"); zassert_true(sizeof(((struct strbuf *)0)->maxlen) > 0, "maxlen size is 0"); zassert_true(sizeof(((struct strbuf *)0)->len) > 0, "len size is 0"); From 0a6e90b3b83319724fdbb9e5592ef541f8193e8c Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 31 Jan 2024 15:36:10 +0200 Subject: [PATCH 0410/2402] xtensa: make assembly-called functions static z_mp_entry() and power_gate_exit() are only called from assembly code in the same file, where they're defined. Make them "static" and add an attribute to let the compiler know, that they aren't unused. Signed-off-by: Guennadi Liakhovetski --- soc/intel/intel_adsp/ace/power.c | 2 +- soc/intel/intel_adsp/cavs/power.c | 2 +- soc/intel/intel_adsp/common/multiprocessing.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/soc/intel/intel_adsp/ace/power.c b/soc/intel/intel_adsp/ace/power.c index 02646e1614c..2a5712d9cbe 100644 --- a/soc/intel/intel_adsp/ace/power.c +++ b/soc/intel/intel_adsp/ace/power.c @@ -179,7 +179,7 @@ void power_gate_entry(uint32_t core_id) z_xt_ints_off(0xffffffff); } -void power_gate_exit(void) +static void __used power_gate_exit(void) { cpu_early_init(); sys_cache_data_flush_and_invd_all(); diff --git a/soc/intel/intel_adsp/cavs/power.c b/soc/intel/intel_adsp/cavs/power.c index 704d7aa9d3f..fa4616e4ba3 100644 --- a/soc/intel/intel_adsp/cavs/power.c +++ b/soc/intel/intel_adsp/cavs/power.c @@ -99,7 +99,7 @@ static ALWAYS_INLINE void _restore_core_context(void) __asm__ volatile("rsync"); } -void power_gate_exit(void) +static void __used power_gate_exit(void) { cpu_early_init(); sys_cache_data_flush_and_invd_all(); diff --git a/soc/intel/intel_adsp/common/multiprocessing.c b/soc/intel/intel_adsp/common/multiprocessing.c index 79d7d1883e0..cf33ad990e1 100644 --- a/soc/intel/intel_adsp/common/multiprocessing.c +++ b/soc/intel/intel_adsp/common/multiprocessing.c @@ -96,7 +96,7 @@ __asm__(".section .text.z_soc_mp_asm_entry, \"x\" \n\t" #undef NOP32 #undef NOP4 -__imr void z_mp_entry(void) +static __imr void __used z_mp_entry(void) { cpu_early_init(); /* Set up the CPU pointer. */ From a454bb9abcabc8c4dbd6cd06100f78ccf19fd675 Mon Sep 17 00:00:00 2001 From: Dominik Ermel Date: Tue, 9 Jan 2024 21:31:19 +0000 Subject: [PATCH 0411/2402] tests/storage/stream_flash: Fix the test_stream_flash_erase_page Fix for test that was failing due to incorrectly testing of stream_flash_erase_page. The stream_flash_erase_page would never be able to erase a page it has been requested to erase. Signed-off-by: Dominik Ermel --- tests/subsys/storage/stream/stream_flash/src/main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/subsys/storage/stream/stream_flash/src/main.c b/tests/subsys/storage/stream/stream_flash/src/main.c index 7e5a0ba13fc..089f68cd72e 100644 --- a/tests/subsys/storage/stream/stream_flash/src/main.c +++ b/tests/subsys/storage/stream/stream_flash/src/main.c @@ -419,14 +419,14 @@ ZTEST(lib_stream_flash, test_stream_flash_erase_page) init_target(); - /* Write out one buf */ - rc = stream_flash_buffered_write(&ctx, write_buf, BUF_LEN, false); + /* Write something to make page dirty */ + rc = flash_write(ctx.fdev, FLASH_BASE, write_buf, BUF_LEN); zassert_equal(rc, 0, "expected success"); rc = stream_flash_erase_page(&ctx, FLASH_BASE); zassert_equal(rc, 0, "expected success"); - VERIFY_ERASED(FLASH_BASE, page_size); + VERIFY_ERASED(0, page_size); /* * Test failure in erase does not change context. From 23750ffd908aea8138c3b4adb8f1b8ca83f1f2c0 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Fri, 26 Jan 2024 16:44:34 +0100 Subject: [PATCH 0412/2402] dts: arm: stm32h7 MPU attribute for the external Memory Define the MPU attribute to be ATTR_MPU_EXTMEM for the external region (qspi- or octo-spi NOR flash) starting at 0x90000000 of the stm32h7 serie. A XiP region should be Included inside with attribute ATTR_MPU_IO, to access the external memory in XIP. The stm32h7a/h7b serie as another external area at 0x70000000. Signed-off-by: Francois Ramu --- dts/arm/st/h7/stm32h7.dtsi | 8 ++++---- dts/arm/st/h7/stm32h7a3.dtsi | 7 +++++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index 64ccfbf7241..28ca326f596 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -45,10 +45,10 @@ }; }; - quadspi_memory: memory@90000000 { - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x90000000 DT_SIZE_M(256)>; - zephyr,memory-region = "QSPI"; + ext_memory: memory@90000000 { + compatible = "zephyr,memory-region"; + reg = <0x90000000 DT_SIZE_M(256)>; /* max addressable area */ + zephyr,memory-region = "EXTMEM"; zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; }; diff --git a/dts/arm/st/h7/stm32h7a3.dtsi b/dts/arm/st/h7/stm32h7a3.dtsi index 8ff4353855a..68f7d82969f 100644 --- a/dts/arm/st/h7/stm32h7a3.dtsi +++ b/dts/arm/st/h7/stm32h7a3.dtsi @@ -152,6 +152,13 @@ zephyr,memory-region = "ITCM"; }; + ext_memory2: memory@70000000 { + compatible = "zephyr,memory-region"; + reg = <0x70000000 DT_SIZE_M(256)>; /* max addressable area */ + zephyr,memory-region = "EXTMEM2"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; + }; + otghs_fs_phy: otghs_fs_phy { compatible = "usb-nop-xceiv"; #phy-cells = <0>; From f62815c02286e6231ede021e191d20eb20e5897c Mon Sep 17 00:00:00 2001 From: Michele Sardo Date: Sun, 25 Feb 2024 13:40:06 +0100 Subject: [PATCH 0413/2402] boards: arm: sensortile_box_pro: init USB console only if present. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid conflict with applications which doesn’t require a console. Signed-off-by: Michele Sardo --- boards/st/sensortile_box_pro/board.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/boards/st/sensortile_box_pro/board.c b/boards/st/sensortile_box_pro/board.c index db3de065f2b..b66edf23be4 100644 --- a/boards/st/sensortile_box_pro/board.c +++ b/boards/st/sensortile_box_pro/board.c @@ -11,7 +11,8 @@ #include #include -#ifdef CONFIG_USB_DEVICE_STACK +#if defined(CONFIG_CONSOLE) && defined(CONFIG_UART_CONSOLE) +#if DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_console), zephyr_cdc_acm_uart) /* * Enable console on USB CDC_ACM */ @@ -29,4 +30,5 @@ static int sensortile_box_pro_usb_console_init(void) /* needs to be done at Application */ SYS_INIT(sensortile_box_pro_usb_console_init, APPLICATION, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); -#endif +#endif /* DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_console), zephyr_cdc_acm_uart) */ +#endif /* defined(CONFIG_CONSOLE) && defined (CONFIG_UART_CONSOLE) */ From 1ec7116042f6f32c11ead15b4cc67589370ef7d6 Mon Sep 17 00:00:00 2001 From: Dominik Ermel Date: Wed, 6 Mar 2024 12:51:46 +0000 Subject: [PATCH 0414/2402] mcumgr/img_mgmt: Fix CONFIG_MCUBOOT_BOOTLOADER_NO_DOWNGRADE Usage of the Kconfig, in code, has been missing CONFIG_, so selected or not it did nothing. Signed-off-by: Dominik Ermel --- subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c index 7de448ac78d..29e222d1de9 100644 --- a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c +++ b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c @@ -469,7 +469,7 @@ os_mgmt_bootloader_info(struct smp_streamer *ctxt) ok = zcbor_tstr_put_lit(zse, "mode") && zcbor_int32_put(zse, BOOTLOADER_MODE); -#if IS_ENABLED(MCUBOOT_BOOTLOADER_NO_DOWNGRADE) +#if IS_ENABLED(CONFIG_MCUBOOT_BOOTLOADER_NO_DOWNGRADE) ok = zcbor_tstr_put_lit(zse, "no-downgrade") && zcbor_bool_encode(zse, true); #endif From 1686ae763d56745ca505b2951af3da35529eb258 Mon Sep 17 00:00:00 2001 From: Gustavo Silva Date: Sat, 2 Mar 2024 17:21:11 -0300 Subject: [PATCH 0415/2402] boards: st: nucleo_h745zi_q: enable USB Add USB OTG FS node to the devicetree of Cortex-M7 core. Signed-off-by: Gustavo Silva --- boards/st/nucleo_h745zi_q/doc/index.rst | 46 ++++++++++--------- .../nucleo_h745zi_q_stm32h745xx_m7.dts | 6 +++ .../nucleo_h745zi_q_stm32h745xx_m7.yaml | 2 + 3 files changed, 32 insertions(+), 22 deletions(-) diff --git a/boards/st/nucleo_h745zi_q/doc/index.rst b/boards/st/nucleo_h745zi_q/doc/index.rst index 265d3385be8..b1593b5e484 100644 --- a/boards/st/nucleo_h745zi_q/doc/index.rst +++ b/boards/st/nucleo_h745zi_q/doc/index.rst @@ -94,32 +94,34 @@ Supported Features The Zephyr nucleo_h745zi_q board configuration supports the following hardware features: -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++-------------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. The default configuration per core can be found in the defconfig files: -:zephyr_file:`boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig`` and +:zephyr_file:`boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig` and :zephyr_file:`boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig` For more details please refer to `STM32 Nucleo-144 board User Manual`_. diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts index 184232867bb..cf22a60ad2a 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts @@ -121,3 +121,9 @@ &rng { status = "okay"; }; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml index c480b150189..904e740e5ed 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml @@ -17,4 +17,6 @@ supported: - i2c - pwm - netif:eth + - usb_cdc + - usb_device vendor: st From 302da95b30d77e1faff0abc9205488eff0885cf3 Mon Sep 17 00:00:00 2001 From: IBEN EL HADJ MESSAOUD Marwa Date: Wed, 28 Feb 2024 13:42:50 +0100 Subject: [PATCH 0416/2402] tests: drivers: i2c: i2c_target_api: add nucleo_f401re Adds i2c3 on the dts of nucleo_f401re. Adds necessary overlay and nucleo_f401re in i2c_target_api test case to enable the board. Signed-off-by: IBEN EL HADJ MESSAOUD Marwa --- boards/st/nucleo_f401re/nucleo_f401re.dts | 7 +++++ .../i2c_target_api/boards/nucleo_f401re.conf | 2 ++ .../boards/nucleo_f401re.overlay | 27 +++++++++++++++++++ .../drivers/i2c/i2c_target_api/testcase.yaml | 1 + 4 files changed, 37 insertions(+) create mode 100644 tests/drivers/i2c/i2c_target_api/boards/nucleo_f401re.conf create mode 100644 tests/drivers/i2c/i2c_target_api/boards/nucleo_f401re.overlay diff --git a/boards/st/nucleo_f401re/nucleo_f401re.dts b/boards/st/nucleo_f401re/nucleo_f401re.dts index c45c1cffb64..fbfdc59bea0 100644 --- a/boards/st/nucleo_f401re/nucleo_f401re.dts +++ b/boards/st/nucleo_f401re/nucleo_f401re.dts @@ -107,6 +107,13 @@ clock-frequency = ; }; +&i2c3 { + pinctrl-0 = <&i2c3_scl_pa8 &i2c3_sda_pc9>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + &spi1 { pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; pinctrl-names = "default"; diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_f401re.conf b/tests/drivers/i2c/i2c_target_api/boards/nucleo_f401re.conf new file mode 100644 index 00000000000..34b2571d125 --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_f401re.conf @@ -0,0 +1,2 @@ +CONFIG_I2C_STM32_INTERRUPT=y +CONFIG_I2C_VIRTUAL=n diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_f401re.overlay b/tests/drivers/i2c/i2c_target_api/boards/nucleo_f401re.overlay new file mode 100644 index 00000000000..5c65f872319 --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_f401re.overlay @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +/* I2C bus pins are exposed on the ST morpho header. + * + * Bus SDA SCL + * Pin Hdr Pin Hdr + * i2c1 PB9 CN5:9 PB8 CN5:10 + * i2c3 PC9 CN10:1 PA8 CN9:8 + * + * Short Pin PB9 to PC9, and PB8 to PA8, for the test to pass. + */ + +&i2c1 { + eeprom0: eeprom@54 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x54>; + size = <1024>; + }; +}; + +&i2c3 { + eeprom1: eeprom@56 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x56>; + size = <1024>; + }; +}; diff --git a/tests/drivers/i2c/i2c_target_api/testcase.yaml b/tests/drivers/i2c/i2c_target_api/testcase.yaml index d3c5a408495..0f14bff2b5c 100644 --- a/tests/drivers/i2c/i2c_target_api/testcase.yaml +++ b/tests/drivers/i2c/i2c_target_api/testcase.yaml @@ -18,6 +18,7 @@ tests: - stm32f3_disco - nucleo_g071rb - nucleo_f207zg + - nucleo_f401re - nucleo_f429zi - nucleo_wl55jc - nucleo_l073rz From 43bce7e125e2ba4dcc660732ed80dc4fd7b7d060 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Fri, 1 Mar 2024 16:07:23 +0100 Subject: [PATCH 0417/2402] tracing: sysview: Remove redundant depends on Remove redundant depends on statements for SEGGER_SYSTEMVIEW. This is already inside an if SEGGER_SYSTEMVIEW so depends on are already added. Signed-off-by: Joakim Andersson --- subsys/tracing/sysview/Kconfig | 5 ----- 1 file changed, 5 deletions(-) diff --git a/subsys/tracing/sysview/Kconfig b/subsys/tracing/sysview/Kconfig index 972fb1aec31..b9002dd8701 100644 --- a/subsys/tracing/sysview/Kconfig +++ b/subsys/tracing/sysview/Kconfig @@ -5,26 +5,21 @@ if SEGGER_SYSTEMVIEW config SEGGER_SYSTEMVIEW_BOOT_ENABLE bool "Start logging SystemView events on system start" - depends on SEGGER_SYSTEMVIEW config SEGGER_SYSVIEW_RTT_BUFFER_SIZE int "Buffer size for SystemView RTT" - depends on SEGGER_SYSTEMVIEW default 4096 config SEGGER_SYSVIEW_RTT_CHANNEL int "RTT channel for SystemView" - depends on SEGGER_SYSTEMVIEW default 0 config SEGGER_SYSVIEW_APP_NAME string "Application name to be displayed in SystemView" - depends on SEGGER_SYSTEMVIEW default "ZephyrSysView" config SEGGER_SYSVIEW_POST_MORTEM_MODE bool "Post-mortem mode for SystemView" - depends on SEGGER_SYSTEMVIEW choice SEGGER_SYSVIEW_SECTION prompt "Choose SystemView data linker section" From f6435e012ecc0819b0f6aaf060c385d6a88f10a0 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 8 Mar 2024 13:47:41 +0100 Subject: [PATCH 0418/2402] manifest: Update nrf hw models to latest * Update the HW models module to 3925b7030736f25f45ceedc3621219125a2d4685 Including the following: * 3925b70: Add new API to convert real peripheral addr to simulated one * 319e3eb: nhw_convert_periph_base_addr: Fix include for nrf5340 Signed-off-by: Alberto Escolar Piedras --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 2acf74dcc20..15f34c2088a 100644 --- a/west.yml +++ b/west.yml @@ -295,7 +295,7 @@ manifest: groups: - tools - name: nrf_hw_models - revision: 52d0b4b7b7431d8da6222cc3b17a8afdcb099baf + revision: 319e3ebd3134935c330980dfac53d05d28c0af9a path: modules/bsim_hw_models/nrf_hw_models - name: open-amp revision: da78aea63159771956fe0c9263f2e6985b66e9d5 From f9d5e8458ce261d6c3574d50d3b16ea031419279 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 8 Mar 2024 11:14:11 +0100 Subject: [PATCH 0419/2402] drivers/counter nrfx: Fix with DT instance not matching device instance 478530ec0aa1fe5f481786c25d50f7a081b22208 introduced a bug where if the DT index while iterating its DT structure initialization does not match the actual peripheral instance, or if the device instance string is not just a simple integer, but a more complex string like "00", or "02", either the wrong peripheral address would be used, or the file would failt to compile. Let's fix this by reverting that change, and instead, for simulation converting the hardcoded DT/real HW address to the valid addr for simulation on the fly. Signed-off-by: Alberto Escolar Piedras --- drivers/counter/counter_nrfx_timer.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/counter/counter_nrfx_timer.c b/drivers/counter/counter_nrfx_timer.c index 47537b16d7d..1fe3a98f8d7 100644 --- a/drivers/counter/counter_nrfx_timer.c +++ b/drivers/counter/counter_nrfx_timer.c @@ -28,6 +28,12 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL); #define COUNTER_OVERFLOW_SHORT NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK #define COUNTER_READ_CC NRF_TIMER_CC_CHANNEL1 +#if defined(CONFIG_SOC_SERIES_BSIM_NRFXX) +#define MAYBE_CONST_CONFIG +#else +#define MAYBE_CONST_CONFIG const +#endif + struct counter_nrfx_data { counter_top_callback_t top_cb; void *top_user_data; @@ -283,7 +289,16 @@ static uint32_t get_pending_int(const struct device *dev) static int init_timer(const struct device *dev, const struct counter_timer_config *config) { - const struct counter_nrfx_config *nrfx_config = dev->config; + MAYBE_CONST_CONFIG struct counter_nrfx_config *nrfx_config = + (MAYBE_CONST_CONFIG struct counter_nrfx_config *)dev->config; + +#if defined(CONFIG_SOC_SERIES_BSIM_NRFXX) + /* For simulated devices we need to convert the hardcoded DT address from the real + * peripheral into the correct one for simulation + */ + nrfx_config->timer = nhw_convert_periph_base_addr(nrfx_config->timer); +#endif + NRF_TIMER_Type *reg = nrfx_config->timer; nrf_timer_bit_width_set(reg, config->bit_width); @@ -430,7 +445,7 @@ static const struct counter_driver_api counter_nrfx_driver_api = { static struct counter_nrfx_ch_data \ counter##idx##_ch_data[CC_TO_ID(DT_INST_PROP(idx, cc_num))]; \ LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_COUNTER_LOG_LEVEL); \ - static const struct counter_nrfx_config nrfx_counter_##idx##_config = { \ + static MAYBE_CONST_CONFIG struct counter_nrfx_config nrfx_counter_##idx##_config = { \ .info = { \ .max_top_value = (uint32_t)BIT64_MASK(DT_INST_PROP(idx, max_bit_width)),\ .freq = TIMER_CLOCK((NRF_TIMER_Type *)DT_INST_REG_ADDR(idx)) / \ @@ -439,7 +454,7 @@ static const struct counter_driver_api counter_nrfx_driver_api = { .channels = CC_TO_ID(DT_INST_PROP(idx, cc_num)), \ }, \ .ch_data = counter##idx##_ch_data, \ - .timer = (NRF_TIMER_Type *)_CONCAT(NRF_TIMER, idx), \ + .timer = (NRF_TIMER_Type *)DT_INST_REG_ADDR(idx), \ LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx) \ }; \ DEVICE_DT_INST_DEFINE(idx, \ From f41c900b031b715b8d7917fb0abb9582d124b97f Mon Sep 17 00:00:00 2001 From: Ryan McClelland Date: Sat, 9 Mar 2024 21:36:45 -0800 Subject: [PATCH 0420/2402] drivers: regulator: fix shell help typo Fix typo with adget shell help Signed-off-by: Ryan McClelland --- drivers/regulator/regulator_shell.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/regulator/regulator_shell.c b/drivers/regulator/regulator_shell.c index 5dddbb5b8d7..c1a24f61a61 100644 --- a/drivers/regulator/regulator_shell.c +++ b/drivers/regulator/regulator_shell.c @@ -389,7 +389,7 @@ static int cmd_adset(const struct shell *sh, size_t argc, char **argv) ret = regulator_set_active_discharge(dev, ad); if (ret < 0) { - shell_error(sh, "Could not set mode (%d)", ret); + shell_error(sh, "Could not set active discharge (%d)", ret); return ret; } @@ -566,7 +566,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE( cmd_adset, 3, 0), SHELL_CMD_ARG(adget, NULL, "Get active discharge\n" - "Usage: adset ", + "Usage: adget ", cmd_adget, 2, 0), SHELL_CMD_ARG(errors, &dsub_device_name, "Get errors\n" From 53a6a2b6bb789536340760297f3b65fa992a58e7 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 11 Mar 2024 14:35:58 +0200 Subject: [PATCH 0421/2402] MAINTAINERS: Fix BSD socket maintainer list The BSD sockets are definitely maintained so fix the status. Signed-off-by: Jukka Rissanen --- MAINTAINERS.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 0350b41269a..516f0bf8860 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2571,8 +2571,8 @@ Networking: - net "Networking: BSD sockets": - status: odd fixes - collaborators: + status: maintained + maintainers: - rlubos - jukkar files: @@ -2580,6 +2580,7 @@ Networking: - subsys/net/lib/sockets/ - tests/net/socket/ labels: + - "area: Networking" - "area: Sockets" tests: - net.socket From 479fd88df45508688b16cafb6121a73ca075855d Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Wed, 14 Feb 2024 15:18:45 +0100 Subject: [PATCH 0422/2402] MAINTAINERS: Remove szymon-czapracki as LE audio collaborator Szymon is not active in the LE Audio development. Signed-off-by: Emil Gydesen --- MAINTAINERS.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 516f0bf8860..136fd0f3ee7 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -435,7 +435,6 @@ Bluetooth Audio: - Casper-Bonde-Bose - MariuszSkamra - sjanc - - szymon-czapracki - asbjornsabo - fredrikdanebjer - kruithofa From e61e6a409229cb5474f8ea5334321424f14d450c Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Mon, 19 Feb 2024 16:50:55 -0600 Subject: [PATCH 0423/2402] samples: drivers: ipm: ipm_mcux: fix build command documentation Documentation for IPM MCUX sample did not provide correct command for building sample. To resolve this, add the "--sysbuild" argument to build command documentation Signed-off-by: Daniel DeGrasse --- samples/drivers/ipm/ipm_mcux/README.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/samples/drivers/ipm/ipm_mcux/README.rst b/samples/drivers/ipm/ipm_mcux/README.rst index 887437403f5..cb75ffb521c 100644 --- a/samples/drivers/ipm/ipm_mcux/README.rst +++ b/samples/drivers/ipm/ipm_mcux/README.rst @@ -28,6 +28,7 @@ Building the application for lpcxpresso54114/lpc54114/m4 :zephyr-app: samples/drivers/ipm/ipm_mcux :board: lpcxpresso54114/lpc54114/m4 :goals: debug + :west-args: --sysbuild Building the application for lpcxpresso55s69/lpc55s69/cpu0 @@ -37,6 +38,7 @@ Building the application for lpcxpresso55s69/lpc55s69/cpu0 :zephyr-app: samples/drivers/ipm/ipm_mcux :board: lpcxpresso55s69/lpc55s69/cpu0 :goals: debug + :west-args: --sysbuild Running ******* From dca836b9b1a79b9365b9e4bf02d0f823fb5477ba Mon Sep 17 00:00:00 2001 From: Robert Zieba Date: Wed, 28 Feb 2024 10:32:53 -0700 Subject: [PATCH 0424/2402] gdbstub: Add custom backend choice By default `GDBSTUB_SERIAL_BACKEND` will be selected as it's the only option here. This can cause problems for code that wants to provide its own custom backend. Add a choice for a custom backend. Signed-off-by: Robert Zieba --- subsys/debug/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/subsys/debug/Kconfig b/subsys/debug/Kconfig index 7da4440c010..1f14b80b47c 100644 --- a/subsys/debug/Kconfig +++ b/subsys/debug/Kconfig @@ -414,6 +414,11 @@ config GDBSTUB_SERIAL_BACKEND help Use serial as backend for GDB +config GDBSTUB_CUSTOM_BACKEND + bool "Use a custom backend" + help + Use a custom backend for GDB + endchoice config GDBSTUB_BUF_SZ From 66eb627b024cdd99a24e299fc04477fa5c323d8e Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 16:57:30 +0200 Subject: [PATCH 0425/2402] tests: net: ieee802154: Invalid number of params in debug print The debug print did not had print modifier for errno which causes compiler error. Signed-off-by: Jukka Rissanen --- tests/net/ieee802154/l2/src/ieee802154_test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/net/ieee802154/l2/src/ieee802154_test.c b/tests/net/ieee802154/l2/src/ieee802154_test.c index 7b4ff21dc52..4d93e2398b0 100644 --- a/tests/net/ieee802154/l2/src/ieee802154_test.c +++ b/tests/net/ieee802154/l2/src/ieee802154_test.c @@ -1152,7 +1152,7 @@ static bool test_recv_and_send_ack_reply(struct ieee802154_pkt_test *t) recv_src_sll.sll_family != AF_PACKET || recv_src_sll.sll_protocol != ETH_P_IEEE802154 || recv_src_sll.sll_halen != IEEE802154_EXT_ADDR_LENGTH || memcmp(recv_src_sll.sll_addr, mac_be, IEEE802154_EXT_ADDR_LENGTH)) { - NET_ERR("*** Received socket address does not compare", errno); + NET_ERR("*** Received socket address does not compare (%d)", -errno); goto release_rx_pkt; } From b6e65dd57ad364c3680e972dde62e4699b73974b Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Thu, 7 Mar 2024 16:06:27 +0100 Subject: [PATCH 0426/2402] cmake: sca: codechecker: Allow processing results even on errors The analyze step for codechecker can have errors. These are printed out to the console, allow to keep processing results for other succeeded analysis. Signed-off-by: Pieter De Gendt --- cmake/sca/codechecker/sca.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/cmake/sca/codechecker/sca.cmake b/cmake/sca/codechecker/sca.cmake index 87b6015ae84..fd7d18ecea0 100644 --- a/cmake/sca/codechecker/sca.cmake +++ b/cmake/sca/codechecker/sca.cmake @@ -26,6 +26,7 @@ add_custom_target(codechecker ALL --name zephyr # Set a default metadata name ${CODECHECKER_ANALYZE_OPTS} ${CMAKE_BINARY_DIR}/compile_commands.json + || ${CMAKE_COMMAND} -E true # allow to continue processing results DEPENDS ${CMAKE_BINARY_DIR}/compile_commands.json ${output_dir}/codechecker.ready BYPRODUCTS ${output_dir}/codechecker.plist VERBATIM From 238b9be5eee1d454c0f959cd97265f25ab43b506 Mon Sep 17 00:00:00 2001 From: Bartosz Sokolski Date: Wed, 31 Jan 2024 16:55:17 +0100 Subject: [PATCH 0427/2402] drivers: i2s_nrfx: add support for divider setup on NRF54L15 Add support for NRF54L15 divider setting which is same as on NRF5340 Signed-off-by: Bartosz Sokolski --- drivers/i2s/i2s_nrfx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2s/i2s_nrfx.c b/drivers/i2s/i2s_nrfx.c index b4a6f55443f..eeb3ca911fb 100644 --- a/drivers/i2s/i2s_nrfx.c +++ b/drivers/i2s/i2s_nrfx.c @@ -100,7 +100,7 @@ static void find_suitable_clock(const struct i2s_nrfx_drv_cfg *drv_cfg, continue; } - if (IS_ENABLED(CONFIG_SOC_SERIES_NRF53X)) { + if (IS_ENABLED(CONFIG_SOC_SERIES_NRF53X) || IS_ENABLED(CONFIG_SOC_SERIES_NRF54LX)) { uint32_t requested_mck = i2s_cfg->frame_clk_freq * ratios[r].ratio_val; /* As specified in the nRF5340 PS: From f2280d119d3a3a69d66b3f3516fc1d4e3d453b8b Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Fri, 8 Mar 2024 08:42:08 -0800 Subject: [PATCH 0428/2402] kernel/sched: Don't touch deadline values on queued threads k_thread_deadline_set() would modify the thread's deadline and then, if it was in the run queue, requeue it to put it at the right spot. Sounds right, right? It's wrong. The deadline field is part of the thread priority, so this results in a mis-ordered list. For dlist backends, that's benign as the removal works anyway, but if CONFIG_SCHED_SCALABLE=y we've now broken the sorting order of an in-tree item and corrupted the rbtree! Fixes #69935 Signed-off-by: Andy Ross --- kernel/sched.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/kernel/sched.c b/kernel/sched.c index 93005ce6bab..57974044f94 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -1280,12 +1280,21 @@ static inline void z_vrfy_k_thread_priority_set(k_tid_t thread, int prio) void z_impl_k_thread_deadline_set(k_tid_t tid, int deadline) { struct k_thread *thread = tid; + int32_t newdl = k_cycle_get_32() + deadline; + /* The prio_deadline field changes the sorting order, so can't + * change it while the thread is in the run queue (dlists + * actually are benign as long as we requeue it before we + * release the lock, but an rbtree will blow up if we break + * sorting!) + */ K_SPINLOCK(&_sched_spinlock) { - thread->base.prio_deadline = k_cycle_get_32() + deadline; if (z_is_thread_queued(thread)) { dequeue_thread(thread); + thread->base.prio_deadline = newdl; queue_thread(thread); + } else { + thread->base.prio_deadline = newdl; } } } From 19ad64b98bf861b1b9313a29db24dbff9080116c Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Fri, 8 Mar 2024 08:45:34 -0800 Subject: [PATCH 0429/2402] tests/kernel/sched/deadline: Add a SCHED_SCALABLE=y case for coverage It turns out the deadline scheduling and the scalable scheduling backend didn't work right together (for almost six years!) because we never had coverage of that combination. Add it explicitly given the known issue in #69935. We might want to consider adding a whole CI target with SCALABLE=y, which we've done for other common tunables to get coverage. Signed-off-by: Andy Ross --- tests/kernel/sched/deadline/testcase.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/kernel/sched/deadline/testcase.yaml b/tests/kernel/sched/deadline/testcase.yaml index b77bb0ee930..bbe2df74127 100644 --- a/tests/kernel/sched/deadline/testcase.yaml +++ b/tests/kernel/sched/deadline/testcase.yaml @@ -1,3 +1,7 @@ tests: kernel.scheduler.deadline: tags: kernel + kernel.scheduler.deadline.scalable: + tags: kernel + extra_configs: + - CONFIG_SCHED_SCALABLE=y From 35ae3e535323aad5526032a013d41e9e0f92fbaf Mon Sep 17 00:00:00 2001 From: Ali Hozhabri Date: Mon, 26 Feb 2024 17:53:29 +0100 Subject: [PATCH 0430/2402] drivers: bluetooth: hci: Move bt_spi_send_aci_config to setup function Move bt_spi_send_aci_config to setup function. Signed-off-by: Ali Hozhabri --- drivers/bluetooth/hci/hci_spi_st.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/bluetooth/hci/hci_spi_st.c b/drivers/bluetooth/hci/hci_spi_st.c index 3473938b3b5..22d75676725 100644 --- a/drivers/bluetooth/hci/hci_spi_st.c +++ b/drivers/bluetooth/hci/hci_spi_st.c @@ -151,12 +151,6 @@ static bool bt_spi_handle_vendor_evt(uint8_t *msg) switch (bt_spi_get_evt(msg)) { case EVT_BLUE_INITIALIZED: { k_sem_give(&sem_initialised); -#if defined(CONFIG_BT_BLUENRG_ACI) - /* force BlueNRG to be on controller mode */ - uint8_t data = 1; - - bt_spi_send_aci_config(BLUENRG_CONFIG_LL_ONLY_OFFSET, &data, 1); -#endif handled = true; } default: @@ -319,6 +313,11 @@ static int bt_spi_bluenrg_setup(const struct bt_hci_setup_params *params) int ret; const bt_addr_t *addr = ¶ms->public_addr; + /* force BlueNRG to be on controller mode */ + uint8_t data = 1; + + bt_spi_send_aci_config(BLUENRG_CONFIG_LL_ONLY_OFFSET, &data, 1); + if (!bt_addr_eq(addr, BT_ADDR_NONE) && !bt_addr_eq(addr, BT_ADDR_ANY)) { ret = bt_spi_send_aci_config( BLUENRG_CONFIG_PUBADDR_OFFSET, From 9d8d20febba51561e1069faf5c05f9040de5eaf6 Mon Sep 17 00:00:00 2001 From: Ali Hozhabri Date: Tue, 27 Feb 2024 18:15:59 +0100 Subject: [PATCH 0431/2402] drivers: bluetooth: hci: Support raw mode in ST HCI SPI BT driver Add raw mode in ST HCI SPI BT driver to support host-less configuration. Remove compilation dependency for BT_QUIRK_NO_RESET as it applies to all configurations. Signed-off-by: Ali Hozhabri --- drivers/bluetooth/hci/hci_spi_st.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/bluetooth/hci/hci_spi_st.c b/drivers/bluetooth/hci/hci_spi_st.c index 22d75676725..82de8bd7ed9 100644 --- a/drivers/bluetooth/hci/hci_spi_st.c +++ b/drivers/bluetooth/hci/hci_spi_st.c @@ -23,6 +23,7 @@ #include #include +#include #define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL #include @@ -86,7 +87,6 @@ static K_SEM_DEFINE(sem_busy, 1, 1); static K_KERNEL_STACK_DEFINE(spi_rx_stack, CONFIG_BT_DRV_RX_STACK_SIZE); static struct k_thread spi_rx_thread_data; -#if defined(CONFIG_BT_BLUENRG_ACI) #define BLUENRG_ACI_WRITE_CONFIG_DATA BT_OP(BT_OGF_VS, 0x000C) #define BLUENRG_CONFIG_PUBADDR_OFFSET 0x00 #define BLUENRG_CONFIG_PUBADDR_LEN 0x06 @@ -94,7 +94,6 @@ static struct k_thread spi_rx_thread_data; #define BLUENRG_CONFIG_LL_ONLY_LEN 0x01 static int bt_spi_send_aci_config(uint8_t offset, const uint8_t *value, size_t value_len); -#endif /* CONFIG_BT_BLUENRG_ACI */ static const struct spi_dt_spec bus = SPI_DT_SPEC_INST_GET( 0, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0); @@ -151,7 +150,9 @@ static bool bt_spi_handle_vendor_evt(uint8_t *msg) switch (bt_spi_get_evt(msg)) { case EVT_BLUE_INITIALIZED: { k_sem_give(&sem_initialised); +#if defined(CONFIG_BT_BLUENRG_ACI) handled = true; +#endif } default: break; @@ -294,8 +295,16 @@ static int bt_spi_send_aci_config(uint8_t offset, const uint8_t *value, size_t v struct net_buf *buf; uint8_t *cmd_data; size_t data_len = 2 + value_len; +#if defined(CONFIG_BT_HCI_RAW) + struct bt_hci_cmd_hdr hdr; + hdr.opcode = sys_cpu_to_le16(BLUENRG_ACI_WRITE_CONFIG_DATA); + hdr.param_len = data_len; + buf = bt_buf_get_tx(BT_BUF_CMD, K_NO_WAIT, &hdr, sizeof(hdr)); +#else buf = bt_hci_cmd_create(BLUENRG_ACI_WRITE_CONFIG_DATA, data_len); +#endif /* CONFIG_BT_HCI_RAW */ + if (!buf) { return -ENOBUFS; } @@ -305,9 +314,14 @@ static int bt_spi_send_aci_config(uint8_t offset, const uint8_t *value, size_t v cmd_data[1] = value_len; memcpy(&cmd_data[2], value, value_len); +#if defined(CONFIG_BT_HCI_RAW) + return bt_send(buf); +#else return bt_hci_cmd_send(BLUENRG_ACI_WRITE_CONFIG_DATA, buf); +#endif /* CONFIG_BT_HCI_RAW */ } +#if !defined(CONFIG_BT_HCI_RAW) static int bt_spi_bluenrg_setup(const struct bt_hci_setup_params *params) { int ret; @@ -331,6 +345,8 @@ static int bt_spi_bluenrg_setup(const struct bt_hci_setup_params *params) return 0; } +#endif /* !CONFIG_BT_HCI_RAW */ + #endif /* CONFIG_BT_BLUENRG_ACI */ static struct net_buf *bt_spi_rx_buf_construct(uint8_t *msg) @@ -579,16 +595,22 @@ static int bt_spi_open(void) /* Device will let us know when it's ready */ k_sem_take(&sem_initialised, K_FOREVER); +#if defined(CONFIG_BT_HCI_RAW) && defined(CONFIG_BT_BLUENRG_ACI) + /* force BlueNRG to be on controller mode */ + uint8_t data = 1; + + bt_spi_send_aci_config(BLUENRG_CONFIG_LL_ONLY_OFFSET, &data, 1); +#endif /* CONFIG_BT_HCI_RAW && CONFIG_BT_BLUENRG_ACI */ return 0; } static const struct bt_hci_driver drv = { .name = DEVICE_DT_NAME(DT_DRV_INST(0)), .bus = BT_HCI_DRIVER_BUS_SPI, -#if defined(CONFIG_BT_BLUENRG_ACI) .quirks = BT_QUIRK_NO_RESET, +#if defined(CONFIG_BT_BLUENRG_ACI) && !defined(CONFIG_BT_HCI_RAW) .setup = bt_spi_bluenrg_setup, -#endif /* CONFIG_BT_BLUENRG_ACI */ +#endif /* CONFIG_BT_BLUENRG_ACI && !CONFIG_BT_HCI_RAW */ .open = bt_spi_open, .send = bt_spi_send, }; From bcf2ee9d49c16d51025a5b2574cc143a9ccd4c75 Mon Sep 17 00:00:00 2001 From: Ali Hozhabri Date: Tue, 27 Feb 2024 18:16:53 +0100 Subject: [PATCH 0432/2402] drivers: bluetooth: hci: Special handling of hci_reset only for ST SPI v1 Exclude devices based on ST SPI protocol v2 from special handling of hci_reset opcode as it is redundant. Signed-off-by: Ali Hozhabri --- drivers/bluetooth/hci/hci_spi_st.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/bluetooth/hci/hci_spi_st.c b/drivers/bluetooth/hci/hci_spi_st.c index 82de8bd7ed9..7f3ee523d29 100644 --- a/drivers/bluetooth/hci/hci_spi_st.c +++ b/drivers/bluetooth/hci/hci_spi_st.c @@ -536,7 +536,7 @@ static int bt_spi_send(struct net_buf *buf) LOG_HEXDUMP_DBG(buf->data, buf->len, "SPI TX"); -#if (DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) || DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v2)) +#if DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) /* * Since a RESET has been requested, the chip will now restart. * Unfortunately the BlueNRG will reply with "reset received" but @@ -547,7 +547,7 @@ static int bt_spi_send(struct net_buf *buf) if (bt_spi_get_cmd(buf->data) == BT_HCI_OP_RESET) { k_sem_take(&sem_initialised, K_FOREVER); } -#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) || DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v2) */ +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) */ net_buf_unref(buf); return ret; From 569f8f0a43dab5525a03ab18ab4bb50f956b9991 Mon Sep 17 00:00:00 2001 From: Ali Hozhabri Date: Fri, 1 Mar 2024 10:24:20 +0100 Subject: [PATCH 0433/2402] boards: Add support for BlueNRG-based boards to run raw mode samples Provide support for BlueNRG-based boards to run samples required raw mode. Signed-off-by: Ali Hozhabri --- .../x_nucleo_bnrg2a1/boards/nucleo_l476rg.overlay | 11 +++++++++++ .../x_nucleo_idb05a1/boards/nucleo_l476rg.overlay | 6 ++++++ boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts | 1 + boards/st/disco_l475_iot1/disco_l475_iot1.dts | 1 + boards/st/sensortile_box/sensortile_box.dts | 1 + boards/st/sensortile_box_pro/sensortile_box_pro.dts | 2 +- boards/st/stm32l562e_dk/stm32l562e_dk.dts | 1 + 7 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 boards/shields/x_nucleo_bnrg2a1/boards/nucleo_l476rg.overlay diff --git a/boards/shields/x_nucleo_bnrg2a1/boards/nucleo_l476rg.overlay b/boards/shields/x_nucleo_bnrg2a1/boards/nucleo_l476rg.overlay new file mode 100644 index 00000000000..cdde24f69a7 --- /dev/null +++ b/boards/shields/x_nucleo_bnrg2a1/boards/nucleo_l476rg.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,bt-c2h-uart = &usart2; + }; +}; diff --git a/boards/shields/x_nucleo_idb05a1/boards/nucleo_l476rg.overlay b/boards/shields/x_nucleo_idb05a1/boards/nucleo_l476rg.overlay index 86c3d24ea57..87356961b33 100644 --- a/boards/shields/x_nucleo_idb05a1/boards/nucleo_l476rg.overlay +++ b/boards/shields/x_nucleo_idb05a1/boards/nucleo_l476rg.overlay @@ -4,6 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +/ { + chosen { + zephyr,bt-c2h-uart = &usart2; + }; +}; + &arduino_spi { pinctrl-0 = <&spi1_sck_pb3 &spi1_miso_pa6 &spi1_mosi_pa7>; }; diff --git a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts index d85c2770ebf..531c5a5b20d 100644 --- a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts +++ b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts @@ -21,6 +21,7 @@ zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; zephyr,flash-controller = &mx25r6435f; + zephyr,bt-c2h-uart = &usart1; }; leds { diff --git a/boards/st/disco_l475_iot1/disco_l475_iot1.dts b/boards/st/disco_l475_iot1/disco_l475_iot1.dts index 81beca8e7c0..572e8768c9e 100644 --- a/boards/st/disco_l475_iot1/disco_l475_iot1.dts +++ b/boards/st/disco_l475_iot1/disco_l475_iot1.dts @@ -21,6 +21,7 @@ zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; zephyr,flash-controller = &mx25r6435f; + zephyr,bt-c2h-uart = &usart1; }; leds { diff --git a/boards/st/sensortile_box/sensortile_box.dts b/boards/st/sensortile_box/sensortile_box.dts index 4c5a9654b3d..102dbb6a73a 100644 --- a/boards/st/sensortile_box/sensortile_box.dts +++ b/boards/st/sensortile_box/sensortile_box.dts @@ -18,6 +18,7 @@ zephyr,shell-uart = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,bt-c2h-uart = &usart1; }; leds { diff --git a/boards/st/sensortile_box_pro/sensortile_box_pro.dts b/boards/st/sensortile_box_pro/sensortile_box_pro.dts index 8c159eb831f..951fb52fd81 100644 --- a/boards/st/sensortile_box_pro/sensortile_box_pro.dts +++ b/boards/st/sensortile_box_pro/sensortile_box_pro.dts @@ -25,7 +25,7 @@ */ zephyr,console = &cdc_acm_uart0; zephyr,shell-uart = &cdc_acm_uart0; - + zephyr,bt-c2h-uart = &cdc_acm_uart0; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk.dts b/boards/st/stm32l562e_dk/stm32l562e_dk.dts index 7473e130fce..2083e93ff0d 100644 --- a/boards/st/stm32l562e_dk/stm32l562e_dk.dts +++ b/boards/st/stm32l562e_dk/stm32l562e_dk.dts @@ -19,6 +19,7 @@ zephyr,shell-uart = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,bt-c2h-uart = &usart1; }; aliases { From b65b6a82082a5670c7462686e68e36cd8d254b87 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 7 Mar 2024 16:38:04 +0200 Subject: [PATCH 0434/2402] posix: socket: Add missing recvmsg() The sys/socket.h was missing recently added recvmsg() call to net/socket.h Signed-off-by: Jukka Rissanen --- include/zephyr/posix/sys/socket.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/zephyr/posix/sys/socket.h b/include/zephyr/posix/sys/socket.h index af4f48e3907..235bd76cc59 100644 --- a/include/zephyr/posix/sys/socket.h +++ b/include/zephyr/posix/sys/socket.h @@ -88,6 +88,11 @@ static inline ssize_t sendmsg(int sock, const struct msghdr *message, return zsock_sendmsg(sock, message, flags); } +static inline ssize_t recvmsg(int sock, struct msghdr *msg, int flags) +{ + return zsock_recvmsg(sock, msg, flags); +} + static inline ssize_t recvfrom(int sock, void *buf, size_t max_len, int flags, struct sockaddr *src_addr, socklen_t *addrlen) { From ba2a8bd795dba0e2792eb241416b30427280109f Mon Sep 17 00:00:00 2001 From: Maciej Baczmanski Date: Thu, 15 Feb 2024 08:55:49 +0100 Subject: [PATCH 0435/2402] manifest: openthread: Regular openthread upmerge Adds `CONFIG_OPENTHREAD_SRP_ADV_PROXY` option Signed-off-by: Maciej Baczmanski --- modules/openthread/CMakeLists.txt | 1 + modules/openthread/Kconfig.features | 5 +++++ west.yml | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/modules/openthread/CMakeLists.txt b/modules/openthread/CMakeLists.txt index 5b64d3be2f5..c638d3394f4 100644 --- a/modules/openthread/CMakeLists.txt +++ b/modules/openthread/CMakeLists.txt @@ -109,6 +109,7 @@ kconfig_to_ot_option(CONFIG_OPENTHREAD_REFERENCE_DEVICE OT_REFERENCE_DEVICE "Ena kconfig_to_ot_option(CONFIG_OPENTHREAD_SETTINGS_RAM OT_SETTINGS_RAM "Enable volatile-only storage of settings") kconfig_to_ot_option(CONFIG_OPENTHREAD_SLAAC OT_SLAAC "Enable SLAAC") kconfig_to_ot_option(CONFIG_OPENTHREAD_SNTP_CLIENT OT_SNTP_CLIENT "Enable SNTP Client support") +kconfig_to_ot_option(CONFIG_OPENTHREAD_SRP_ADV_PROXY OT_SRP_ADV_PROXY "Enable SRP Server Advertising Proxy support") kconfig_to_ot_option(CONFIG_OPENTHREAD_SRP_CLIENT OT_SRP_CLIENT "Enable SRP Client support") kconfig_to_ot_option(CONFIG_OPENTHREAD_SRP_SERVER OT_SRP_SERVER "Enable SRP Server support") kconfig_to_ot_option(CONFIG_OPENTHREAD_TCP_ENABLE OT_TCP "Enable TCP support") diff --git a/modules/openthread/Kconfig.features b/modules/openthread/Kconfig.features index ba3990a348d..cc29a53c650 100644 --- a/modules/openthread/Kconfig.features +++ b/modules/openthread/Kconfig.features @@ -326,6 +326,11 @@ config OPENTHREAD_SLAAC config OPENTHREAD_SNTP_CLIENT bool "SNTP Client support" +config OPENTHREAD_SRP_ADV_PROXY + bool "SRP Server Advertising Proxy support" + depends on OPENTHREAD_SRP_SERVER + depends on OPENTHREAD_BORDER_ROUTING + config OPENTHREAD_SRP_CLIENT bool "SRP Client support" select OPENTHREAD_ECDSA diff --git a/west.yml b/west.yml index 15f34c2088a..4ef280bf07d 100644 --- a/west.yml +++ b/west.yml @@ -301,7 +301,7 @@ manifest: revision: da78aea63159771956fe0c9263f2e6985b66e9d5 path: modules/lib/open-amp - name: openthread - revision: 7761b81d23b10b3d5ee21b8504c67535cde10896 + revision: 49c59ec519cc8b49dd58978d1bc80b7ae7ba88d0 path: modules/lib/openthread - name: percepio path: modules/debug/percepio From 0d53af4aa1358217ee3014f7a049a8bcd298784a Mon Sep 17 00:00:00 2001 From: Kyle Kotowick Date: Sat, 2 Mar 2024 15:55:45 -0500 Subject: [PATCH 0436/2402] drivers: dacx0508: fix for multiple DACs of the same type Presently, this driver cannot handle multiple DACs of the same type without throwing a compile error due to a missing line ending. This PR fixes that issue by adding the missing line ending. Signed-off-by: Kyle Kotowick --- drivers/dac/dac_dacx0508.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dac/dac_dacx0508.c b/drivers/dac/dac_dacx0508.c index c0616080099..49f8b71a818 100644 --- a/drivers/dac/dac_dacx0508.c +++ b/drivers/dac/dac_dacx0508.c @@ -386,7 +386,7 @@ static const struct dac_driver_api dacx0508_driver_api = { &dac##t##_data_##n, \ &dac##t##_config_##n, POST_KERNEL, \ CONFIG_DAC_DACX0508_INIT_PRIORITY, \ - &dacx0508_driver_api) + &dacx0508_driver_api); /* * DAC60508: 12-bit From 444018f133d39c51c2eb3faa195ba2d8d6d86b92 Mon Sep 17 00:00:00 2001 From: Armin Brauns Date: Tue, 5 Mar 2024 14:58:28 +0000 Subject: [PATCH 0437/2402] drivers/sdmmc_stm32: add eMMC support The only difference is calling HAL_MMC_*() instead of HAL_SD_*() functions, and removing the card detect logic. Signed-off-by: Armin Brauns --- drivers/disk/Kconfig.sdmmc | 12 ++- drivers/disk/sdmmc_stm32.c | 174 ++++++++++++++++++++++++++----------- 2 files changed, 134 insertions(+), 52 deletions(-) diff --git a/drivers/disk/Kconfig.sdmmc b/drivers/disk/Kconfig.sdmmc index ccab26c3c7e..a5463eff529 100644 --- a/drivers/disk/Kconfig.sdmmc +++ b/drivers/disk/Kconfig.sdmmc @@ -38,8 +38,10 @@ config SDMMC_STM32 bool "STM32 SDMMC driver" default y depends on DT_HAS_ST_STM32_SDMMC_ENABLED - select USE_STM32_HAL_SD - select USE_STM32_HAL_SD_EX if SOC_SERIES_STM32L4X + select USE_STM32_HAL_SD if !SDMMC_STM32_EMMC + select USE_STM32_HAL_SD_EX if !SDMMC_STM32_EMMC && SOC_SERIES_STM32L4X + select USE_STM32_HAL_MMC if SDMMC_STM32_EMMC + select USE_STM32_HAL_MMC_EX if SDMMC_STM32_EMMC && SOC_SERIES_STM32L4X select USE_STM32_LL_SDMMC select USE_STM32_HAL_DMA if (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32F4X) select DMA if ($(DT_STM32_SDMMC_HAS_DMA) && SOC_SERIES_STM32F4X) @@ -58,6 +60,12 @@ config SDMMC_STM32_HWFC Enable SDMMC Hardware Flow Control to avoid FIFO underrun (TX mode) and overrun (RX mode) errors. +config SDMMC_STM32_EMMC + bool "STM32 SDMMC eMMC mode" + depends on SDMMC_STM32 + help + Use eMMC instead of SDIO (SD card) protocol. These are similar, but not entirely the same. + config SDMMC_STM32_CLOCK_CHECK bool "Runtime SDMMC 48MHz clock check" depends on SDMMC_STM32 diff --git a/drivers/disk/sdmmc_stm32.c b/drivers/disk/sdmmc_stm32.c index 71c2c7cab86..a9cda286e3a 100644 --- a/drivers/disk/sdmmc_stm32.c +++ b/drivers/disk/sdmmc_stm32.c @@ -64,11 +64,19 @@ struct sdmmc_dma_stream { }; #endif +#ifdef CONFIG_SDMMC_STM32_EMMC +typedef MMC_HandleTypeDef HandleTypeDef; +typedef HAL_MMC_CardInfoTypeDef CardInfoTypeDef; +#else +typedef SD_HandleTypeDef HandleTypeDef; +typedef HAL_SD_CardInfoTypeDef CardInfoTypeDef; +#endif + struct stm32_sdmmc_priv { irq_config_func_t irq_config; struct k_sem thread_lock; struct k_sem sync; - SD_HandleTypeDef hsd; + HandleTypeDef hsd; int status; struct k_work work; struct gpio_callback cd_cb; @@ -97,38 +105,32 @@ static void stm32_sdmmc_isr(const struct device *dev) { struct stm32_sdmmc_priv *priv = dev->data; +#ifdef CONFIG_SDMMC_STM32_EMMC + HAL_MMC_IRQHandler(&priv->hsd); +#else HAL_SD_IRQHandler(&priv->hsd); +#endif } -void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) -{ - struct stm32_sdmmc_priv *priv = - CONTAINER_OF(hsd, struct stm32_sdmmc_priv, hsd); - - priv->status = hsd->ErrorCode; - - k_sem_give(&priv->sync); -} - -void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) -{ - struct stm32_sdmmc_priv *priv = - CONTAINER_OF(hsd, struct stm32_sdmmc_priv, hsd); - - priv->status = hsd->ErrorCode; - - k_sem_give(&priv->sync); -} - -void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) -{ - struct stm32_sdmmc_priv *priv = - CONTAINER_OF(hsd, struct stm32_sdmmc_priv, hsd); - - priv->status = hsd->ErrorCode; +#define DEFINE_HAL_CALLBACK(name) \ + void name(HandleTypeDef *hsd) \ + { \ + struct stm32_sdmmc_priv *priv = CONTAINER_OF(hsd, struct stm32_sdmmc_priv, hsd); \ + \ + priv->status = hsd->ErrorCode; \ + \ + k_sem_give(&priv->sync); \ + } - k_sem_give(&priv->sync); -} +#ifdef CONFIG_SDMMC_STM32_EMMC +DEFINE_HAL_CALLBACK(HAL_MMC_TxCpltCallback); +DEFINE_HAL_CALLBACK(HAL_MMC_RxCpltCallback); +DEFINE_HAL_CALLBACK(HAL_MMC_ErrorCallback); +#else +DEFINE_HAL_CALLBACK(HAL_SD_TxCpltCallback); +DEFINE_HAL_CALLBACK(HAL_SD_RxCpltCallback); +DEFINE_HAL_CALLBACK(HAL_SD_ErrorCallback); +#endif static int stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv *priv) { @@ -166,6 +168,7 @@ static int stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv *priv) return clock_control_on(clock, (clock_control_subsys_t)&priv->pclken[0]); } +#if !defined(CONFIG_SDMMC_STM32_EMMC) static int stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv *priv) { const struct device *clock; @@ -175,6 +178,7 @@ static int stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv *priv) return clock_control_off(clock, (clock_control_subsys_t)&priv->pclken); } +#endif #if STM32_SDMMC_USE_DMA @@ -289,7 +293,11 @@ static int stm32_sdmmc_access_init(struct disk_info *disk) return err; } +#ifdef CONFIG_SDMMC_STM32_EMMC + err = HAL_MMC_Init(&priv->hsd); +#else err = HAL_SD_Init(&priv->hsd); +#endif if (err != HAL_OK) { LOG_ERR("failed to init stm32_sdmmc (ErrorCode 0x%X)", priv->hsd.ErrorCode); return -EIO; @@ -303,11 +311,14 @@ static int stm32_sdmmc_access_init(struct disk_info *disk) return 0; } +#if !defined(CONFIG_SDMMC_STM32_EMMC) static void stm32_sdmmc_access_deinit(struct stm32_sdmmc_priv *priv) { HAL_SD_DeInit(&priv->hsd); + stm32_sdmmc_clock_disable(priv); } +#endif static int stm32_sdmmc_access_status(struct disk_info *disk) { @@ -317,6 +328,37 @@ static int stm32_sdmmc_access_status(struct disk_info *disk) return priv->status; } +static int stm32_sdmmc_is_card_in_transfer(HandleTypeDef *hsd) +{ +#ifdef CONFIG_SDMMC_STM32_EMMC + return HAL_MMC_GetCardState(hsd) == HAL_MMC_CARD_TRANSFER; +#else + return HAL_SD_GetCardState(hsd) == HAL_SD_CARD_TRANSFER; +#endif +} + +static int stm32_sdmmc_read_blocks(HandleTypeDef *hsd, uint8_t *data_buf, + uint32_t start_sector, uint32_t num_sector) +{ +#if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma)) + +#ifdef CONFIG_SDMMC_STM32_EMMC + return HAL_MMC_ReadBlocks_DMA(hsd, data_buf, start_sector, num_sector); +#else + return HAL_SD_ReadBlocks_DMA(hsd, data_buf, start_sector, num_sector); +#endif + +#else + +#ifdef CONFIG_SDMMC_STM32_EMMC + return HAL_MMC_ReadBlocks_IT(hsd, data_buf, start_sector, num_sector); +#else + return HAL_SD_ReadBlocks_IT(hsd, data_buf, start_sector, num_sector); +#endif + +#endif +} + static int stm32_sdmmc_access_read(struct disk_info *disk, uint8_t *data_buf, uint32_t start_sector, uint32_t num_sector) { @@ -326,13 +368,7 @@ static int stm32_sdmmc_access_read(struct disk_info *disk, uint8_t *data_buf, k_sem_take(&priv->thread_lock, K_FOREVER); -#if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma)) - err = HAL_SD_ReadBlocks_DMA(&priv->hsd, data_buf, start_sector, - num_sector); -#else - err = HAL_SD_ReadBlocks_IT(&priv->hsd, data_buf, start_sector, - num_sector); -#endif + err = stm32_sdmmc_read_blocks(&priv->hsd, data_buf, start_sector, num_sector); if (err != HAL_OK) { LOG_ERR("sd read block failed %d", err); err = -EIO; @@ -347,7 +383,7 @@ static int stm32_sdmmc_access_read(struct disk_info *disk, uint8_t *data_buf, goto end; } - while (HAL_SD_GetCardState(&priv->hsd) != HAL_SD_CARD_TRANSFER) { + while (!stm32_sdmmc_is_card_in_transfer(&priv->hsd)) { } end: @@ -355,6 +391,29 @@ static int stm32_sdmmc_access_read(struct disk_info *disk, uint8_t *data_buf, return err; } +static int stm32_sdmmc_write_blocks(HandleTypeDef *hsd, + uint8_t *data_buf, + uint32_t start_sector, uint32_t num_sector) +{ +#if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma)) + +#ifdef CONFIG_SDMMC_STM32_EMMC + return HAL_MMC_WriteBlocks_DMA(hsd, data_buf, start_sector, num_sector); +#else + return HAL_SD_WriteBlocks_DMA(hsd, data_buf, start_sector, num_sector); +#endif + +#else + +#ifdef CONFIG_SDMMC_STM32_EMMC + return HAL_MMC_WriteBlocks_IT(hsd, data_buf, start_sector, num_sector); +#else + return HAL_SD_WriteBlocks_IT(hsd, data_buf, start_sector, num_sector); +#endif + +#endif +} + static int stm32_sdmmc_access_write(struct disk_info *disk, const uint8_t *data_buf, uint32_t start_sector, uint32_t num_sector) @@ -365,13 +424,7 @@ static int stm32_sdmmc_access_write(struct disk_info *disk, k_sem_take(&priv->thread_lock, K_FOREVER); -#if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma)) - err = HAL_SD_WriteBlocks_DMA(&priv->hsd, (uint8_t *)data_buf, start_sector, - num_sector); -#else - err = HAL_SD_WriteBlocks_IT(&priv->hsd, (uint8_t *)data_buf, start_sector, - num_sector); -#endif + err = stm32_sdmmc_write_blocks(&priv->hsd, (uint8_t *)data_buf, start_sector, num_sector); if (err != HAL_OK) { LOG_ERR("sd write block failed %d", err); err = -EIO; @@ -386,7 +439,7 @@ static int stm32_sdmmc_access_write(struct disk_info *disk, goto end; } - while (HAL_SD_GetCardState(&priv->hsd) != HAL_SD_CARD_TRANSFER) { + while (!stm32_sdmmc_is_card_in_transfer(&priv->hsd)) { } end: @@ -394,24 +447,33 @@ static int stm32_sdmmc_access_write(struct disk_info *disk, return err; } +static int stm32_sdmmc_get_card_info(HandleTypeDef *hsd, CardInfoTypeDef *info) +{ +#ifdef CONFIG_SDMMC_STM32_EMMC + return HAL_MMC_GetCardInfo(hsd, info); +#else + return HAL_SD_GetCardInfo(hsd, info); +#endif +} + static int stm32_sdmmc_access_ioctl(struct disk_info *disk, uint8_t cmd, void *buff) { const struct device *dev = disk->dev; struct stm32_sdmmc_priv *priv = dev->data; - HAL_SD_CardInfoTypeDef info; + CardInfoTypeDef info; int err; switch (cmd) { case DISK_IOCTL_GET_SECTOR_COUNT: - err = HAL_SD_GetCardInfo(&priv->hsd, &info); + err = stm32_sdmmc_get_card_info(&priv->hsd, &info); if (err != HAL_OK) { return -EIO; } *(uint32_t *)buff = info.LogBlockNbr; break; case DISK_IOCTL_GET_SECTOR_SIZE: - err = HAL_SD_GetCardInfo(&priv->hsd, &info); + err = stm32_sdmmc_get_card_info(&priv->hsd, &info); if (err != HAL_OK) { return -EIO; } @@ -442,6 +504,13 @@ static struct disk_info stm32_sdmmc_info = { .ops = &stm32_sdmmc_ops, }; + +#ifdef CONFIG_SDMMC_STM32_EMMC +static bool stm32_sdmmc_card_present(struct stm32_sdmmc_priv *priv) +{ + return true; +} +#else /* CONFIG_SDMMC_STM32_EMMC */ /* * Check if the card is present or not. If no card detect gpio is set, assume * the card is present. If reading the gpio fails for some reason, assume the @@ -539,6 +608,7 @@ static int stm32_sdmmc_card_detect_uninit(struct stm32_sdmmc_priv *priv) gpio_remove_callback(priv->cd.port, &priv->cd_cb); return 0; } +#endif /* !CONFIG_SDMMC_STM32_EMMC */ static int stm32_sdmmc_pwr_init(struct stm32_sdmmc_priv *priv) { @@ -588,8 +658,6 @@ static int disk_stm32_sdmmc_init(const struct device *dev) return -ENODEV; } - k_work_init(&priv->work, stm32_sdmmc_cd_handler); - /* Configure dt provided device signals when available */ err = pinctrl_apply_state(priv->pcfg, PINCTRL_STATE_DEFAULT); if (err < 0) { @@ -602,10 +670,14 @@ static int disk_stm32_sdmmc_init(const struct device *dev) k_sem_init(&priv->thread_lock, 1, 1); k_sem_init(&priv->sync, 0, 1); +#if !defined(CONFIG_SDMMC_STM32_EMMC) + k_work_init(&priv->work, stm32_sdmmc_cd_handler); + err = stm32_sdmmc_card_detect_init(priv); if (err) { return err; } +#endif err = stm32_sdmmc_pwr_init(priv); if (err) { @@ -628,7 +700,9 @@ static int disk_stm32_sdmmc_init(const struct device *dev) err_pwr: stm32_sdmmc_pwr_uninit(priv); err_card_detect: +#if !defined(CONFIG_SDMMC_STM32_EMMC) stm32_sdmmc_card_detect_uninit(priv); +#endif return err; } From d03778f9e6e8abf740af8c31360443ff6b040ded Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Wed, 28 Feb 2024 13:13:19 +0100 Subject: [PATCH 0438/2402] drivers: adc: reset data ready signal for ADS114s0x Reset the data ready signal for a new read operation with a ADS114s0x. Signed-off-by: Benedikt Schmidt --- drivers/adc/adc_ads114s0x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/adc/adc_ads114s0x.c b/drivers/adc/adc_ads114s0x.c index 936aecf6f1a..16a7bfabfad 100644 --- a/drivers/adc/adc_ads114s0x.c +++ b/drivers/adc/adc_ads114s0x.c @@ -1006,6 +1006,7 @@ static int ads114s0x_adc_perform_read(const struct device *dev) struct ads114s0x_data *data = dev->data; k_sem_take(&data->acquire_signal, K_FOREVER); + k_sem_reset(&data->data_ready_signal); result = ads114s0x_send_start_read(dev); if (result != 0) { From 1bf02c58aec5dd600abe9347dd67493b41cbb173 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 6 Mar 2024 13:50:05 +0200 Subject: [PATCH 0439/2402] nxp: imx8qm/imx8qxp: enable IRQSTEER on QM/QXP boards This commit enables the IRQSTEER interrupt controller on NXP's XTENSA-based i.MX8QM and i.MX8QXP. Signed-off-by: Laurentiu Mihalcea --- .../imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig | 16 ++++ .../imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts | 4 + .../imx8qxp_mek_mimx8qx6_adsp_defconfig | 16 ++++ dts/xtensa/nxp/nxp_imx8.dtsi | 83 +++++++++++++++++-- 4 files changed, 110 insertions(+), 9 deletions(-) diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig index 325b05b84e9..aaf7764dfb5 100644 --- a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig @@ -16,3 +16,19 @@ CONFIG_CLOCK_CONTROL=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y + +# interrupt-related configurations +CONFIG_MULTI_LEVEL_INTERRUPTS=y +CONFIG_2ND_LEVEL_INTERRUPTS=y +CONFIG_2ND_LVL_ISR_TBL_OFFSET=32 +CONFIG_MAX_IRQ_PER_AGGREGATOR=64 +CONFIG_NUM_2ND_LEVEL_AGGREGATORS=8 +CONFIG_2ND_LVL_INTR_00_OFFSET=19 +CONFIG_2ND_LVL_INTR_01_OFFSET=20 +CONFIG_2ND_LVL_INTR_02_OFFSET=21 +CONFIG_2ND_LVL_INTR_03_OFFSET=22 +CONFIG_2ND_LVL_INTR_04_OFFSET=23 +CONFIG_2ND_LVL_INTR_05_OFFSET=24 +CONFIG_2ND_LVL_INTR_06_OFFSET=25 +CONFIG_2ND_LVL_INTR_07_OFFSET=26 +CONFIG_2ND_LEVEL_INTERRUPT_BITS=9 diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts index 24a9ee09d9e..38974c7ca39 100644 --- a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts @@ -26,3 +26,7 @@ pinctrl-0 = <&lpuart2_default>; pinctrl-names = "default"; }; + +&irqsteer { + reg = <0x51080000 DT_SIZE_K(64)>; +}; diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig index 325b05b84e9..aaf7764dfb5 100644 --- a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig @@ -16,3 +16,19 @@ CONFIG_CLOCK_CONTROL=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y + +# interrupt-related configurations +CONFIG_MULTI_LEVEL_INTERRUPTS=y +CONFIG_2ND_LEVEL_INTERRUPTS=y +CONFIG_2ND_LVL_ISR_TBL_OFFSET=32 +CONFIG_MAX_IRQ_PER_AGGREGATOR=64 +CONFIG_NUM_2ND_LEVEL_AGGREGATORS=8 +CONFIG_2ND_LVL_INTR_00_OFFSET=19 +CONFIG_2ND_LVL_INTR_01_OFFSET=20 +CONFIG_2ND_LVL_INTR_02_OFFSET=21 +CONFIG_2ND_LVL_INTR_03_OFFSET=22 +CONFIG_2ND_LVL_INTR_04_OFFSET=23 +CONFIG_2ND_LVL_INTR_05_OFFSET=24 +CONFIG_2ND_LVL_INTR_06_OFFSET=25 +CONFIG_2ND_LVL_INTR_07_OFFSET=26 +CONFIG_2ND_LEVEL_INTERRUPT_BITS=9 diff --git a/dts/xtensa/nxp/nxp_imx8.dtsi b/dts/xtensa/nxp/nxp_imx8.dtsi index 7a8c23cedc4..6d20f56fcd4 100644 --- a/dts/xtensa/nxp/nxp_imx8.dtsi +++ b/dts/xtensa/nxp/nxp_imx8.dtsi @@ -30,6 +30,78 @@ }; }; + irqsteer: interrupt-controller@510a0000 { + compatible = "nxp,irqsteer-intc"; + reg = <0x510a0000 DT_SIZE_K(64)>; + + #size-cells = <0>; + #address-cells = <1>; + + master0: interrupt-controller@0 { + compatible = "nxp,irqsteer-master"; + reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 19 0 0>; + }; + + master1: interrupt-controller@1 { + compatible = "nxp,irqsteer-master"; + reg = <1>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 20 0 0>; + }; + + master2: interrupt-controller@2 { + compatible = "nxp,irqsteer-master"; + reg = <2>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 21 0 0>; + }; + + master3: interrupt-controller@3 { + compatible = "nxp,irqsteer-master"; + reg = <3>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 22 0 0>; + }; + + master4: interrupt-controller@4 { + compatible = "nxp,irqsteer-master"; + reg = <4>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 23 0 0>; + }; + + master5: interrupt-controller@5 { + compatible = "nxp,irqsteer-master"; + reg = <5>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 24 0 0>; + }; + + master6: interrupt-controller@6 { + compatible = "nxp,irqsteer-master"; + reg = <6>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 25 0 0>; + }; + + master7: interrupt-controller@7 { + compatible = "nxp,irqsteer-master"; + reg = <7>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 26 0 0>; + }; + }; + sram0: memory@92400000 { device_type = "memory"; compatible = "mmio-sram"; @@ -64,15 +136,8 @@ lpuart2: serial@5a080000 { compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart"; reg = <0x5a080000 DT_SIZE_K(4)>; - /* TODO: THIS INTID IS JUST A DUMMY ONE UNTIL IRQ_STEER - * DRIVER CAN BE USED ON i.MX8QM/QXP. DO NOT ATTEMPT TO - * ENABLE UART INTERRUPT SUPPORT. - * - * THE CURRENT INTID VALUE IS CHOSEN SUCH THAT gen_isr_tables.py - * WILL BREAK IF YOU ATTEMPT TO IRQ_CONNECT(). - */ - interrupt-parent = <&clic>; - interrupts = <259 0 0>; + interrupt-parent = <&master4>; + interrupts = <3>; /* this is actually LPUART2 clock but the macro indexing starts at 1 */ clocks = <&ccm IMX_CCM_LPUART3_CLK 0x0 0x0>; status = "disabled"; From a9c2d81bd07dd0cc5b637d06e0463322c2312d6a Mon Sep 17 00:00:00 2001 From: Maksim Salau Date: Mon, 29 Jan 2024 19:28:22 +0100 Subject: [PATCH 0440/2402] drivers: adc: add ADC_DT_SPEC_*_BY_NAME() macros The commit adds macros to get ADC io-channel information from devicetree by name. Signed-off-by: Maksim Salau --- include/zephyr/drivers/adc.h | 85 +++++++++++++++++++++++++++++ tests/lib/devicetree/api/src/main.c | 22 ++++++++ 2 files changed, 107 insertions(+) diff --git a/include/zephyr/drivers/adc.h b/include/zephyr/drivers/adc.h index 989ec79ce11..be88e78b067 100644 --- a/include/zephyr/drivers/adc.h +++ b/include/zephyr/drivers/adc.h @@ -316,6 +316,91 @@ struct adc_dt_spec { /** @endcond */ +/** + * @brief Get ADC io-channel information from devicetree by name. + * + * This returns a static initializer for an @p adc_dt_spec structure + * given a devicetree node and a channel name. The node must have + * the "io-channels" property defined. + * + * Example devicetree fragment: + * + * @code{.dts} + * / { + * zephyr,user { + * io-channels = <&adc0 1>, <&adc0 3>; + * io-channel-names = "A0", "A1"; + * }; + * }; + * + * &adc0 { + * #address-cells = <1>; + * #size-cells = <0>; + * + * channel@3 { + * reg = <3>; + * zephyr,gain = "ADC_GAIN_1_5"; + * zephyr,reference = "ADC_REF_VDD_1_4"; + * zephyr,vref-mv = <750>; + * zephyr,acquisition-time = ; + * zephyr,resolution = <12>; + * zephyr,oversampling = <4>; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * static const struct adc_dt_spec adc_chan0 = + * ADC_DT_SPEC_GET_BY_NAME(DT_PATH(zephyr_user), a0); + * static const struct adc_dt_spec adc_chan1 = + * ADC_DT_SPEC_GET_BY_NAME(DT_PATH(zephyr_user), a1); + * + * // Initializes 'adc_chan0' to: + * // { + * // .dev = DEVICE_DT_GET(DT_NODELABEL(adc0)), + * // .channel_id = 1, + * // } + * // and 'adc_chan1' to: + * // { + * // .dev = DEVICE_DT_GET(DT_NODELABEL(adc0)), + * // .channel_id = 3, + * // .channel_cfg_dt_node_exists = true, + * // .channel_cfg = { + * // .channel_id = 3, + * // .gain = ADC_GAIN_1_5, + * // .reference = ADC_REF_VDD_1_4, + * // .acquisition_time = ADC_ACQ_TIME_DEFAULT, + * // }, + * // .vref_mv = 750, + * // .resolution = 12, + * // .oversampling = 4, + * // } + * @endcode + * + * @param node_id Devicetree node identifier. + * @param name Channel name. + * + * @return Static initializer for an adc_dt_spec structure. + */ +#define ADC_DT_SPEC_GET_BY_NAME(node_id, name) \ + ADC_DT_SPEC_STRUCT(DT_IO_CHANNELS_CTLR_BY_NAME(node_id, name), \ + DT_IO_CHANNELS_INPUT_BY_NAME(node_id, name)) + +/** @brief Get ADC io-channel information from a DT_DRV_COMPAT devicetree + * instance by name. + * + * @see ADC_DT_SPEC_GET_BY_NAME() + * + * @param inst DT_DRV_COMPAT instance number + * @param name Channel name. + * + * @return Static initializer for an adc_dt_spec structure. + */ +#define ADC_DT_SPEC_INST_GET_BY_NAME(inst, name) \ + ADC_DT_SPEC_GET_BY_NAME(DT_DRV_INST(inst), name) + /** * @brief Get ADC io-channel information from devicetree. * diff --git a/tests/lib/devicetree/api/src/main.c b/tests/lib/devicetree/api/src/main.c index 84db80926a0..9e35294f7b4 100644 --- a/tests/lib/devicetree/api/src/main.c +++ b/tests/lib/devicetree/api/src/main.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -1121,6 +1122,27 @@ ZTEST(devicetree_api, test_io_channels) zassert_equal(DT_INST_IO_CHANNELS_INPUT(0), 10, ""); } +#undef DT_DRV_COMPAT +#define DT_DRV_COMPAT vnd_adc_temp_sensor +ZTEST(devicetree_api, test_io_channel_names) +{ + struct adc_dt_spec adc_spec; + + /* ADC_DT_SPEC_GET_BY_NAME */ + adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_GET_BY_NAME(TEST_TEMP, ch1); + zassert_equal(adc_spec.channel_id, 10, ""); + + adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_GET_BY_NAME(TEST_TEMP, ch2); + zassert_equal(adc_spec.channel_id, 20, ""); + + /* ADC_DT_SPEC_INST_GET_BY_NAME */ + adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_INST_GET_BY_NAME(0, ch1); + zassert_equal(adc_spec.channel_id, 10, ""); + + adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_INST_GET_BY_NAME(0, ch2); + zassert_equal(adc_spec.channel_id, 20, ""); +} + #undef DT_DRV_COMPAT #define DT_DRV_COMPAT vnd_adc_temp_sensor ZTEST(devicetree_api, test_dma) From afc7c20d5a67e0e95c7e5bee1e0822c4832335ea Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Sun, 10 Mar 2024 18:15:33 +0100 Subject: [PATCH 0441/2402] drivers: can: fix can_get_core_clock() API description The can_get_core_clock() API function returns the core clock rate of the CAN controller, which provides the minimum time quantum (mtq). This clock can be further divided by the CAN clock prescaler, providing the time quantum (tq). Signed-off-by: Henrik Brix Andersen --- include/zephyr/drivers/can.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index 71369d254ba..62e1047f073 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -788,7 +788,9 @@ struct can_device_state { /** * @brief Get the CAN core clock rate * - * Returns the CAN core clock rate. One time quantum is 1/(core clock rate). + * Returns the CAN core clock rate. One minimum time quantum (mtq) is 1/(core clock rate). The CAN + * core clock can be further divided by the CAN clock prescaler (see the @a can_timing struct), + * providing the time quantum (tq). * * @param dev Pointer to the device structure for the driver instance. * @param[out] rate CAN core clock rate in Hz. From 96d9390f5ec5073a03b0a6336e016aaed0b8de92 Mon Sep 17 00:00:00 2001 From: Ian Wakely Date: Sun, 14 Jan 2024 23:01:25 -0500 Subject: [PATCH 0442/2402] boards: shields: Adding Adafruit 5x5 RGB BFF This is a 5x5 grid of WS2812 RGB LEDs. Signed-off-by: Ian Wakely --- .../Kconfig.defconfig | 4 + .../adafruit_neopixel_grid_bff/Kconfig.shield | 5 ++ .../adafruit_neopixel_grid_bff.overlay | 12 +++ .../adafruit_neopixel_grid_bff_display.conf | 2 + ...adafruit_neopixel_grid_bff_display.overlay | 17 +++++ .../boards/adafruit_qt_py_rp2040.conf | 1 + .../boards/adafruit_qt_py_rp2040.overlay | 37 ++++++++++ .../doc/adafruit_neopixel_grid_bff.jpg | Bin 0 -> 43460 bytes .../adafruit_neopixel_grid_bff/doc/index.rst | 69 ++++++++++++++++++ 9 files changed, 147 insertions(+) create mode 100644 boards/shields/adafruit_neopixel_grid_bff/Kconfig.defconfig create mode 100644 boards/shields/adafruit_neopixel_grid_bff/Kconfig.shield create mode 100644 boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff.overlay create mode 100644 boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.conf create mode 100644 boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.overlay create mode 100644 boards/shields/adafruit_neopixel_grid_bff/boards/adafruit_qt_py_rp2040.conf create mode 100644 boards/shields/adafruit_neopixel_grid_bff/boards/adafruit_qt_py_rp2040.overlay create mode 100644 boards/shields/adafruit_neopixel_grid_bff/doc/adafruit_neopixel_grid_bff.jpg create mode 100644 boards/shields/adafruit_neopixel_grid_bff/doc/index.rst diff --git a/boards/shields/adafruit_neopixel_grid_bff/Kconfig.defconfig b/boards/shields/adafruit_neopixel_grid_bff/Kconfig.defconfig new file mode 100644 index 00000000000..95572630641 --- /dev/null +++ b/boards/shields/adafruit_neopixel_grid_bff/Kconfig.defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Ian Wakely +# SPDX-License-Identifier: Apache-2.0 + +# Intentionally left blank. diff --git a/boards/shields/adafruit_neopixel_grid_bff/Kconfig.shield b/boards/shields/adafruit_neopixel_grid_bff/Kconfig.shield new file mode 100644 index 00000000000..91973762750 --- /dev/null +++ b/boards/shields/adafruit_neopixel_grid_bff/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Ian Wakely +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_NEOPIXEL_GRID_BFF + def_bool $(shields_list_contains,adafruit_neopixel_grid_bff) diff --git a/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff.overlay b/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff.overlay new file mode 100644 index 00000000000..9a0cbfb31ae --- /dev/null +++ b/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff.overlay @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024, Ian Wakely + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + led-strip = &bff_led_strip; + }; +}; diff --git a/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.conf b/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.conf new file mode 100644 index 00000000000..889bdb81881 --- /dev/null +++ b/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.conf @@ -0,0 +1,2 @@ +CONFIG_LED_STRIP=y +CONFIG_WS2812_STRIP=y diff --git a/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.overlay b/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.overlay new file mode 100644 index 00000000000..fbb7b9bcec6 --- /dev/null +++ b/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.overlay @@ -0,0 +1,17 @@ +#include "adafruit_neopixel_grid_bff.overlay" + +/ { + chosen { + zephyr,display = &bff_led_matrix; + }; + + bff_led_matrix: bff-led-matrix { + compatible = "led-strip-matrix"; + status = "okay"; + led-strips = <&bff_led_strip>; + width = <5>; + height = <5>; + start-from-right; + circulative; + }; +}; diff --git a/boards/shields/adafruit_neopixel_grid_bff/boards/adafruit_qt_py_rp2040.conf b/boards/shields/adafruit_neopixel_grid_bff/boards/adafruit_qt_py_rp2040.conf new file mode 100644 index 00000000000..9ccb06fb7bc --- /dev/null +++ b/boards/shields/adafruit_neopixel_grid_bff/boards/adafruit_qt_py_rp2040.conf @@ -0,0 +1 @@ +CONFIG_WS2812_STRIP_RPI_PICO_PIO=y diff --git a/boards/shields/adafruit_neopixel_grid_bff/boards/adafruit_qt_py_rp2040.overlay b/boards/shields/adafruit_neopixel_grid_bff/boards/adafruit_qt_py_rp2040.overlay new file mode 100644 index 00000000000..2b2aad5b748 --- /dev/null +++ b/boards/shields/adafruit_neopixel_grid_bff/boards/adafruit_qt_py_rp2040.overlay @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024, Ian Wakely + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + pinctrl_bff_ws2812: pinctrl_bff_ws2812 { + ws2812 { + pinmux = ; + }; + }; +}; + +&pio0 { + status = "okay"; + + bff-ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&pinctrl_bff_ws2812>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + bff_led_strip: bff_led_strip { + status = "okay"; + gpios = <&xiao_d 3 GPIO_ACTIVE_HIGH>; + chain-length = <25>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; diff --git a/boards/shields/adafruit_neopixel_grid_bff/doc/adafruit_neopixel_grid_bff.jpg b/boards/shields/adafruit_neopixel_grid_bff/doc/adafruit_neopixel_grid_bff.jpg new file mode 100644 index 0000000000000000000000000000000000000000..babd176c8c7620e264e43aca13ed45e82791816a GIT binary patch literal 43460 zcmb4qb8sbJ)a{LJdtzG?+nCsx7&o>vF>h?!wllFgv29E^abA93ef8@7`*xkK>grv6 zYS%g4yVqWO_2WiiC`YjDUcOjf#eWiG_uQh=PNQjfsnniG}&!Bw!F<_dr6yK|#S` zA|W7Q{(swNKL8CDj1vqQ0t^iRjs^yS2KG4!AOrxwpuU0y{9l9liVzwW91QT~#Rmg` zL;Sx^0006E{LBBj20(=Pa-u?@eodf-g&ZL4f9 z0}e*`ByyD{ABPef&OuTF3-j6Ri8YBxbQ%A+h4Mpn9A) zUauyNe@Av}N-}V0bKLlHuOoefP*=bM=hF%vM;97qHI0K*4B#@kZ>qTusF`)jpylAQ z{1`|asy8+}Q+CsooZU5f;1^>oP+`)S@4D77)JEl%N^(8T(rqW*mCL8L(T|e{EKgU` zi%4GMMjnrqLOYM`Wq9Pdb>@YjXU=+8MJf?rE3sD`IywzhrJd0*J2_tPSd*K+f*mAc z7&;fRRhTkO+}F`E*HNtKz&ZMZu5(J+x0m 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b/boards/shields/adafruit_neopixel_grid_bff/doc/index.rst new file mode 100644 index 00000000000..f4648e9b02f --- /dev/null +++ b/boards/shields/adafruit_neopixel_grid_bff/doc/index.rst @@ -0,0 +1,69 @@ +.. _adafruit_neopixel_grid_bff: + +Adafruit 5x5 NeoPixel Grid BFF +############################## + +Overview +******** + +The `Adafruit 5x5 NeoPixel Grid BFF`_ is a 5x5 grid of WS2812B RGB LEDs, +which Adafruit refers to as "neopixels". The BFF series of shields are +designed to be compatible with any Adafruit Qt Py or Seeed Studio Xiao +board. + +.. figure:: adafruit_neopixel_grid_bff.jpg + :align: center + :alt: Adafruit 5x5 NeoPixel Grid BFF + + Adafruit 5x5 NeoPixel Grid BFF (Credit: Adafruit) + +Pin Assignments +=============== + ++-----------------------+---------------------------------------------+ +| Shield Connector Pin | Function | ++=======================+=============================================+ +| A3 | WS2812B driver pin [1]_ | ++-----------------------+---------------------------------------------+ + +.. [1] This is the default pin when the board is delivered as is by Adafruit. + It can be changed away from the default using the onboard solder jumpers, + but this shield will no longer work without a matching device tree update. + +Programming +*********** + +LED Strip Example +================= + +Set ``-DSHIELD=adafruit_neopixel_grid_bff`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/led_ws2812 + :board: adafruit_qt_py_rp2040 + :shield: adafruit_neopixel_grid_bff + :goals: build + +LED Display Matrix Example +========================== + +.. warning:: + + When using this example, all of the LEDs will be set to their maximum + brightness. Having all of the LEDs on at once can cause the PCB to overheat + or draw too much current from any on-board voltage regulators. + Adafruit does provide solder pads for your own power supply on the + underside of the BFF for this reason. It is not required, but is strongly + recommended if all of the LEDs are fully on for any significant amount of + time. + +Set ``-DSHIELD=adafruit_neopixel_grid_bff_display`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/display + :board: adafruit_qt_py_rp2040 + :shield: adafruit_neopixel_grid_bff_display + :goals: build + +.. _Adafruit 5x5 NeoPixel Grid BFF: + https://learn.adafruit.com/adafruit-5x5-neopixel-grid-bff/ From f7eac8ab8de9adfa59dd033a4836d69cd630b030 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Sun, 18 Feb 2024 21:21:32 -0300 Subject: [PATCH 0443/2402] hal_espressif: update to include bugfixes Added longjmp patch. Fixes build warning in phy driver. Fixes runtime missing rom function. Fixes missing mcuboot assertion implementation. Added function to retrieve uart port num Signed-off-by: Sylvio Alves --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 4ef280bf07d..2a22ac86ece 100644 --- a/west.yml +++ b/west.yml @@ -152,7 +152,7 @@ manifest: groups: - hal - name: hal_espressif - revision: 67fa60bdffca7ba8ed199aecfaa26f485f24878b + revision: e705cc16c4b63b5b3cad5c395297a4c2b49651fd path: modules/hal/espressif west-commands: west/west-commands.yml groups: From 84638156c74ce881a7b35b5d2460081dff76b032 Mon Sep 17 00:00:00 2001 From: Abderrahmane Jarmouni Date: Fri, 16 Feb 2024 18:47:33 +0100 Subject: [PATCH 0444/2402] samples: subsys: fs: littlefs: add stm32 configs & tests Add & fix configs & test cases for stm32 boards. Signed-off-by: Abderrahmane Jarmouni --- .../fs/littlefs/boards/nucleo_h743zi.overlay | 17 +++++++++ ...eo_h743zi.conf => nucleo_h743zi_qspi.conf} | 11 ------ .../littlefs/boards/nucleo_h7a3zi_q.overlay | 2 +- .../subsys/fs/littlefs/boards/stm32_blk.conf | 2 ++ .../littlefs/boards/stm32f429i_disc1.overlay | 35 +++++++++++++++++++ .../littlefs/boards/stm32f746g_disco.overlay | 27 ++++++++++++++ .../stm32h747i_disco_stm32h747xx_m7.conf | 1 - .../stm32h747i_disco_stm32h747xx_m7.overlay | 25 +++++++++++++ .../fs/littlefs/boards/stm32h750b_dk.overlay | 29 +++++++++++++++ ...2l562e_dk.conf => stm32l562e_dk_ospi.conf} | 0 samples/subsys/fs/littlefs/sample.yaml | 33 ++++++++++++++++- 11 files changed, 168 insertions(+), 14 deletions(-) rename samples/subsys/fs/littlefs/boards/{nucleo_h743zi.conf => nucleo_h743zi_qspi.conf} (50%) create mode 100644 samples/subsys/fs/littlefs/boards/stm32_blk.conf create mode 100644 samples/subsys/fs/littlefs/boards/stm32f429i_disc1.overlay create mode 100644 samples/subsys/fs/littlefs/boards/stm32f746g_disco.overlay create mode 100644 samples/subsys/fs/littlefs/boards/stm32h750b_dk.overlay rename samples/subsys/fs/littlefs/boards/{stm32l562e_dk.conf => stm32l562e_dk_ospi.conf} (100%) diff --git a/samples/subsys/fs/littlefs/boards/nucleo_h743zi.overlay b/samples/subsys/fs/littlefs/boards/nucleo_h743zi.overlay index b7a8c63fed6..32d6ff2b814 100644 --- a/samples/subsys/fs/littlefs/boards/nucleo_h743zi.overlay +++ b/samples/subsys/fs/littlefs/boards/nucleo_h743zi.overlay @@ -1,5 +1,6 @@ /* * Copyright (c) 2022 Lukasz Majewski, DENX Software Engineering GmbH + * Copyright (c) 2024 STMicroelectronics * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +15,22 @@ pinctrl-names = "default"; }; +/ { + fstab { + compatible = "zephyr,fstab"; + lfs1: lfs1 { + compatible = "zephyr,fstab,littlefs"; + read-size = <32>; + prog-size = <32>; + cache-size = <256>; + lookahead-size = <64>; + block-cycles = <512>; + partition = <&storage_partition>; + mount-point = "/lfs1"; + }; + }; +}; + &quadspi { pinctrl-0 = <&quadspi_clk_pf10 &quadspi_bk2_ncs_pc11 &quadspi_bk2_io0_pe7 &quadspi_bk2_io1_pe8 diff --git a/samples/subsys/fs/littlefs/boards/nucleo_h743zi.conf b/samples/subsys/fs/littlefs/boards/nucleo_h743zi_qspi.conf similarity index 50% rename from samples/subsys/fs/littlefs/boards/nucleo_h743zi.conf rename to samples/subsys/fs/littlefs/boards/nucleo_h743zi_qspi.conf index b4576ceceda..c201d93c33a 100644 --- a/samples/subsys/fs/littlefs/boards/nucleo_h743zi.conf +++ b/samples/subsys/fs/littlefs/boards/nucleo_h743zi_qspi.conf @@ -4,20 +4,9 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_DEBUG=y -CONFIG_FILE_SYSTEM_LITTLEFS=y -CONFIG_FLASH=y -CONFIG_FLASH_MAP=y -CONFIG_FLASH_PAGE_LAYOUT=y -CONFIG_FLASH_STM32_QSPI=y - CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=8192 # Littlefs configuration to utilize QSPI operation -CONFIG_FS_LITTLEFS_CACHE_SIZE=256 -CONFIG_FS_LITTLEFS_PROG_SIZE=32 -CONFIG_FS_LITTLEFS_READ_SIZE=32 -CONFIG_FS_LITTLEFS_LOOKAHEAD_SIZE=64 CONFIG_FS_LITTLEFS_FC_HEAP_SIZE=8192 CONFIG_NOCACHE_MEMORY=y diff --git a/samples/subsys/fs/littlefs/boards/nucleo_h7a3zi_q.overlay b/samples/subsys/fs/littlefs/boards/nucleo_h7a3zi_q.overlay index 11e6c131fc7..1bda13f155c 100644 --- a/samples/subsys/fs/littlefs/boards/nucleo_h7a3zi_q.overlay +++ b/samples/subsys/fs/littlefs/boards/nucleo_h7a3zi_q.overlay @@ -29,7 +29,7 @@ /* Use second half of flash for the filesystem. */ lfs1_partition: partition@100000 { label = "storage"; - reg = <0x10000 DT_SIZE_K(1024)>; + reg = <0x100000 DT_SIZE_K(1024)>; }; }; }; diff --git a/samples/subsys/fs/littlefs/boards/stm32_blk.conf b/samples/subsys/fs/littlefs/boards/stm32_blk.conf new file mode 100644 index 00000000000..158dfa58469 --- /dev/null +++ b/samples/subsys/fs/littlefs/boards/stm32_blk.conf @@ -0,0 +1,2 @@ +CONFIG_FS_LITTLEFS_FC_HEAP_SIZE=2048 +CONFIG_MAIN_STACK_SIZE=2048 diff --git a/samples/subsys/fs/littlefs/boards/stm32f429i_disc1.overlay b/samples/subsys/fs/littlefs/boards/stm32f429i_disc1.overlay new file mode 100644 index 00000000000..ad0d8719d92 --- /dev/null +++ b/samples/subsys/fs/littlefs/boards/stm32f429i_disc1.overlay @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + fstab { + compatible = "zephyr,fstab"; + lfs1: lfs1 { + compatible = "zephyr,fstab,littlefs"; + read-size = <1>; + prog-size = <16>; + cache-size = <256>; + lookahead-size = <32>; + block-cycles = <512>; + partition = <&lfs1_partition>; + mount-point = "/lfs1"; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Use second half of flash for the filesystem. */ + lfs1_partition: partition@100000 { + label = "storage"; + reg = <0x100000 DT_SIZE_K(1024)>; + }; + }; +}; diff --git a/samples/subsys/fs/littlefs/boards/stm32f746g_disco.overlay b/samples/subsys/fs/littlefs/boards/stm32f746g_disco.overlay new file mode 100644 index 00000000000..66f9ebb3676 --- /dev/null +++ b/samples/subsys/fs/littlefs/boards/stm32f746g_disco.overlay @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&sdmmc1 { + sdmmc { + compatible = "zephyr,sdmmc-disk"; + }; +}; + +/ { + fstab { + compatible = "zephyr,fstab"; + lfs1: lfs1 { + compatible = "zephyr,fstab,littlefs"; + read-size = <32>; + prog-size = <32>; + cache-size = <256>; + lookahead-size = <64>; + block-cycles = <512>; + partition = <&storage_partition>; + mount-point = "/lfs1"; + }; + }; +}; diff --git a/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.conf b/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.conf index a45f607811f..158dfa58469 100644 --- a/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.conf +++ b/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.conf @@ -1,3 +1,2 @@ -CONFIG_SDMMC_STM32_HWFC=y CONFIG_FS_LITTLEFS_FC_HEAP_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048 diff --git a/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.overlay b/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.overlay index cf1c30e2e87..7479fac1257 100644 --- a/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.overlay +++ b/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.overlay @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 S&C Electric Company + * Copyright (c) 2024 STMicroelectronics * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,3 +10,27 @@ compatible = "zephyr,sdmmc-disk"; }; }; + +/ { + fstab { + compatible = "zephyr,fstab"; + lfs1: lfs1 { + compatible = "zephyr,fstab,littlefs"; + read-size = <32>; + prog-size = <32>; + cache-size = <256>; + lookahead-size = <64>; + block-cycles = <512>; + partition = <&fs_partition>; + mount-point = "/lfs1"; + }; + }; +}; + +&mt25ql512ab1 { + partitions { + fs_partition: partition@0 { + reg = <0x0 DT_SIZE_M(64)>; + }; + }; +}; diff --git a/samples/subsys/fs/littlefs/boards/stm32h750b_dk.overlay b/samples/subsys/fs/littlefs/boards/stm32h750b_dk.overlay new file mode 100644 index 00000000000..3813a5a30be --- /dev/null +++ b/samples/subsys/fs/littlefs/boards/stm32h750b_dk.overlay @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + fstab { + compatible = "zephyr,fstab"; + lfs1: lfs1 { + compatible = "zephyr,fstab,littlefs"; + read-size = <32>; + prog-size = <32>; + cache-size = <256>; + lookahead-size = <64>; + block-cycles = <512>; + partition = <&fs_partition>; + mount-point = "/lfs1"; + }; + }; +}; + +&mt25ql512ab1 { + partitions { + fs_partition: partition@0 { + reg = <0x0 DT_SIZE_M(64)>; + }; + }; +}; diff --git a/samples/subsys/fs/littlefs/boards/stm32l562e_dk.conf b/samples/subsys/fs/littlefs/boards/stm32l562e_dk_ospi.conf similarity index 100% rename from samples/subsys/fs/littlefs/boards/stm32l562e_dk.conf rename to samples/subsys/fs/littlefs/boards/stm32l562e_dk_ospi.conf diff --git a/samples/subsys/fs/littlefs/sample.yaml b/samples/subsys/fs/littlefs/sample.yaml index 6ba8e33e5a7..183b582e400 100644 --- a/samples/subsys/fs/littlefs/sample.yaml +++ b/samples/subsys/fs/littlefs/sample.yaml @@ -20,6 +20,10 @@ tests: - mimxrt1160_evk/mimxrt1166/cm7 - lpcxpresso55s69/lpc55s69/cpu0 - mr_canhubk3 + - stm32f429i_disc1 + - stm32f746g_disco + - stm32h747i_disco/stm32h747xx/m7 + - stm32h750b_dk integration_platforms: - nrf52840dk/nrf52840 sample.filesystem.littlefs.nrf52840dk_spi: @@ -34,8 +38,35 @@ tests: extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_qspi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_qspi.overlay - sample.filesystem.littlefs.stm32h747i_disco_m7_sdmmc: + sample.filesystem.littlefs.stm32h747i_disco_m7_blk: build_only: true platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: + - OVERLAY_CONFIG=boards/stm32_blk.conf - CONF_FILE=prj_blk.conf + extra_configs: + - CONFIG_SDMMC_STM32_HWFC=y + sample.filesystem.littlefs.nucleo_h743zi_qspi: + build_only: true + platform_allow: nucleo_h743zi + extra_args: + - OVERLAY_CONFIG=boards/nucleo_h743zi_qspi.conf + sample.filesystem.littlefs.nucleo_h743zi_blk: + build_only: true + platform_allow: nucleo_h743zi + extra_args: + - OVERLAY_CONFIG=boards/nucleo_h743zi_blk.conf + - CONF_FILE=prj_blk.conf + sample.filesystem.littlefs.stm32l562e_dk_ospi: + build_only: true + platform_allow: stm32l562e_dk + extra_args: + - OVERLAY_CONFIG=boards/stm32l562e_dk_ospi.conf + sample.filesystem.littlefs.stm32f746g_disco_blk: + build_only: true + platform_allow: stm32f746g_disco + extra_args: + - OVERLAY_CONFIG=boards/stm32_blk.conf + - CONF_FILE=prj_blk.conf + extra_configs: + - CONFIG_SDMMC_STM32_HWFC=y From 227462eda948a62776fba13a6c7e7470a6623f16 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Sat, 2 Mar 2024 10:31:52 +0100 Subject: [PATCH 0445/2402] drivers: counter: stm32: move reset_dt_spec from data to config Move 'reset' member, which is const, from driver data to driver config. This allows to reduce flash usage by few bytes. Signed-off-by: Marcin Niestroj --- drivers/counter/counter_ll_stm32_timer.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/counter/counter_ll_stm32_timer.c b/drivers/counter/counter_ll_stm32_timer.c index 2c012d31c40..869b31a31f7 100644 --- a/drivers/counter/counter_ll_stm32_timer.c +++ b/drivers/counter/counter_ll_stm32_timer.c @@ -96,8 +96,6 @@ struct counter_stm32_data { uint32_t guard_period; atomic_t cc_int_pending; uint32_t freq; - /* Reset controller device configuration */ - const struct reset_dt_spec reset; }; struct counter_stm32_ch_data { @@ -113,6 +111,8 @@ struct counter_stm32_config { struct stm32_pclken pclken; void (*irq_config_func)(const struct device *dev); uint32_t irqn; + /* Reset controller device configuration */ + const struct reset_dt_spec reset; LOG_INSTANCE_PTR_DECLARE(log); }; @@ -487,13 +487,13 @@ static int counter_stm32_init_timer(const struct device *dev) } data->freq = tim_clk / (cfg->prescaler + 1U); - if (!device_is_ready(data->reset.dev)) { + if (!device_is_ready(cfg->reset.dev)) { LOG_ERR("reset controller not ready"); return -ENODEV; } /* Reset timer to default state using RCC */ - (void)reset_line_toggle_dt(&data->reset); + (void)reset_line_toggle_dt(&cfg->reset); /* config/enable IRQ */ cfg->irq_config_func(dev); @@ -639,9 +639,7 @@ void counter_stm32_irq_handler(const struct device *dev) BUILD_ASSERT(NUM_CH(TIM(idx)) <= TIMER_MAX_CH, \ "TIMER too many channels"); \ \ - static struct counter_stm32_data counter##idx##_data = { \ - .reset = RESET_DT_SPEC_GET(TIMER(idx)), \ - }; \ + static struct counter_stm32_data counter##idx##_data; \ static struct counter_stm32_ch_data counter##idx##_ch_data[TIMER_MAX_CH]; \ \ static void counter_##idx##_stm32_irq_config(const struct device *dev) \ @@ -671,6 +669,7 @@ void counter_stm32_irq_handler(const struct device *dev) }, \ .irq_config_func = counter_##idx##_stm32_irq_config, \ .irqn = DT_IRQN(TIMER(idx)), \ + .reset = RESET_DT_SPEC_GET(TIMER(idx)), \ }; \ \ DEVICE_DT_INST_DEFINE(idx, \ From 722e04da3c92e7efaecb4b48a75e11f5d0d58b05 Mon Sep 17 00:00:00 2001 From: Gustavo Silva Date: Sun, 4 Feb 2024 15:24:58 -0300 Subject: [PATCH 0446/2402] flash: stm32: configurable write block sizes Add new devicetree bindings for F4 and L1 series for configuration of block size used in flash write operations. Allow byte-size write operations in `flash_stm32f1x.c`. This file is being shared between F0, F1, F3, L0 and L1 series. L0 and L1 series allows for single byte writes. Signed-off-by: Gustavo Silva --- drivers/flash/flash_stm32f1x.c | 2 ++ dts/arm/st/f4/stm32f4.dtsi | 3 ++- dts/arm/st/l0/stm32l0.dtsi | 3 ++- dts/arm/st/l1/stm32l1.dtsi | 3 ++- dts/bindings/mtd/st,stm32f4-nv-flash.yaml | 20 ++++++++++++++++++++ dts/bindings/mtd/st,stm32l0-nv-flash.yaml | 17 +++++++++++++++++ 6 files changed, 45 insertions(+), 3 deletions(-) create mode 100644 dts/bindings/mtd/st,stm32f4-nv-flash.yaml create mode 100644 dts/bindings/mtd/st,stm32l0-nv-flash.yaml diff --git a/drivers/flash/flash_stm32f1x.c b/drivers/flash/flash_stm32f1x.c index 9a2c0bb4a90..5993be1b6d7 100644 --- a/drivers/flash/flash_stm32f1x.c +++ b/drivers/flash/flash_stm32f1x.c @@ -25,6 +25,8 @@ typedef uint64_t flash_prg_t; typedef uint32_t flash_prg_t; #elif FLASH_STM32_WRITE_BLOCK_SIZE == 2 typedef uint16_t flash_prg_t; +#elif FLASH_STM32_WRITE_BLOCK_SIZE == 1 +typedef uint8_t flash_prg_t; #else #error Unknown write block size #endif diff --git a/dts/arm/st/f4/stm32f4.dtsi b/dts/arm/st/f4/stm32f4.dtsi index 010868a00f2..231c8b988f8 100644 --- a/dts/arm/st/f4/stm32f4.dtsi +++ b/dts/arm/st/f4/stm32f4.dtsi @@ -101,7 +101,8 @@ #size-cells = <1>; flash0: flash@8000000 { - compatible = "st,stm32-nv-flash", "soc-nv-flash"; + compatible = "st,stm32f4-nv-flash", "st,stm32-nv-flash", + "soc-nv-flash"; write-block-size = <1>; /* maximum erase time (ms) for a 128K sector */ diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi index 7bb62de1f22..91d290d0d08 100644 --- a/dts/arm/st/l0/stm32l0.dtsi +++ b/dts/arm/st/l0/stm32l0.dtsi @@ -115,7 +115,8 @@ #size-cells = <1>; flash0: flash@8000000 { - compatible = "st,stm32-nv-flash", "soc-nv-flash"; + compatible = "st,stm32l0-nv-flash", "st,stm32-nv-flash", + "soc-nv-flash"; write-block-size = <4>; /* maximum erase time(ms) for a 128B page */ diff --git a/dts/arm/st/l1/stm32l1.dtsi b/dts/arm/st/l1/stm32l1.dtsi index 53dbd64492d..1f6f0644819 100644 --- a/dts/arm/st/l1/stm32l1.dtsi +++ b/dts/arm/st/l1/stm32l1.dtsi @@ -91,7 +91,8 @@ #size-cells = <1>; flash0: flash@8000000 { - compatible = "st,stm32-nv-flash", "soc-nv-flash"; + compatible = "st,stm32f4-nv-flash", "st,stm32-nv-flash", + "soc-nv-flash"; write-block-size = <4>; /* maximum erase time(ms) for a 128B half-page diff --git a/dts/bindings/mtd/st,stm32f4-nv-flash.yaml b/dts/bindings/mtd/st,stm32f4-nv-flash.yaml new file mode 100644 index 00000000000..258e2c209a7 --- /dev/null +++ b/dts/bindings/mtd/st,stm32f4-nv-flash.yaml @@ -0,0 +1,20 @@ +description: | + ST STM32F4 family flash memory. + +include: st,stm32-nv-flash.yaml + +compatible: st,stm32f4-nv-flash + +properties: + write-block-size: + required: true + type: int + enum: + - 1 + - 2 + - 4 + - 8 + default: 1 + description: | + Number of bytes used in write operations. Default value is based on the + reset value of Flash Control Register (FLASH_CR). diff --git a/dts/bindings/mtd/st,stm32l0-nv-flash.yaml b/dts/bindings/mtd/st,stm32l0-nv-flash.yaml new file mode 100644 index 00000000000..682ee48a601 --- /dev/null +++ b/dts/bindings/mtd/st,stm32l0-nv-flash.yaml @@ -0,0 +1,17 @@ +description: | + ST STM32L0 family flash memory. + +include: st,stm32-nv-flash.yaml + +compatible: st,stm32l0-nv-flash + +properties: + write-block-size: + required: true + type: int + enum: + - 1 + - 2 + - 4 + description: | + Number of bytes used in write operations. From fef58a2a695fe8e64e81a9c2868e03afc202b152 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Thu, 29 Feb 2024 13:35:45 +0100 Subject: [PATCH 0447/2402] net: sockets: Stick to NET_SOCKETS_POLL_MAX limit in socket services Socket service pollfd count should not exceed the configured NET_SOCKETS_POLL_MAX limit, as poll() will not be able to monitor sockets beyond that limit anyway. Adding +1 there prevented the library from catching the configuration error. Signed-off-by: Robert Lubos --- subsys/net/lib/sockets/sockets_service.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/subsys/net/lib/sockets/sockets_service.c b/subsys/net/lib/sockets/sockets_service.c index 1719a380d1f..ad5c07de601 100644 --- a/subsys/net/lib/sockets/sockets_service.c +++ b/subsys/net/lib/sockets/sockets_service.c @@ -21,8 +21,7 @@ STRUCT_SECTION_START_EXTERN(net_socket_service_desc); STRUCT_SECTION_END_EXTERN(net_socket_service_desc); static struct service { - /* The +1 is for triggering events from register function */ - struct zsock_pollfd events[1 + CONFIG_NET_SOCKETS_POLL_MAX]; + struct zsock_pollfd events[CONFIG_NET_SOCKETS_POLL_MAX]; int count; } ctx; From 9e2e234003df46c75992e0dd75c50ed03ef43f11 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Thu, 29 Feb 2024 13:35:49 +0100 Subject: [PATCH 0448/2402] net: telnet: Switch TELNET shell backend to use sockets Rework TELNET shell backend to use socket API for communication and socket service library for socket monitoring. Additionally, rework the TX part so that non-blocking TX is used when sending from the system work queue. In case transfer is not possible at the moment, the TX work is rescheduled instead of blocking the system work queue. Signed-off-by: Robert Lubos --- include/zephyr/shell/shell_telnet.h | 17 +- subsys/net/lib/sockets/Kconfig | 1 + subsys/shell/backends/Kconfig.backends | 11 + subsys/shell/backends/shell_telnet.c | 399 ++++++++++++++++--------- 4 files changed, 288 insertions(+), 140 deletions(-) diff --git a/include/zephyr/shell/shell_telnet.h b/include/zephyr/shell/shell_telnet.h index 6d4567b6a7c..2b8324a290a 100644 --- a/include/zephyr/shell/shell_telnet.h +++ b/include/zephyr/shell/shell_telnet.h @@ -7,6 +7,7 @@ #ifndef SHELL_TELNET_H__ #define SHELL_TELNET_H__ +#include #include #ifdef __cplusplus @@ -15,6 +16,8 @@ extern "C" { extern const struct shell_transport_api shell_telnet_transport_api; +#define SHELL_TELNET_POLLFD_COUNT 3 + /** Line buffer structure. */ struct shell_telnet_line_buf { /** Line buffer. */ @@ -35,11 +38,17 @@ struct shell_telnet { /** Buffer for outgoing line. */ struct shell_telnet_line_buf line_out; - /** Network context of TELNET client. */ - struct net_context *client_ctx; + /** Array for sockets used by the telnet service. */ + struct zsock_pollfd fds[SHELL_TELNET_POLLFD_COUNT]; + + /** Input buffer. */ + uint8_t rx_buf[CONFIG_SHELL_CMD_BUFF_SIZE]; + + /** Number of data bytes within the input buffer. */ + size_t rx_len; - /** RX packet FIFO. */ - struct k_fifo rx_fifo; + /** Mutex protecting the input buffer access. */ + struct k_mutex rx_lock; /** The delayed work is used to send non-lf terminated output that has * been around for "too long". This will prove to be useful diff --git a/subsys/net/lib/sockets/Kconfig b/subsys/net/lib/sockets/Kconfig index 8b428057e3c..36b42a3b4ad 100644 --- a/subsys/net/lib/sockets/Kconfig +++ b/subsys/net/lib/sockets/Kconfig @@ -43,6 +43,7 @@ config NET_SOCKETS_POSIX_NAMES config NET_SOCKETS_POLL_MAX int "Max number of supported poll() entries" default 6 if WIFI_NM_WPA_SUPPLICANT + default 4 if SHELL_BACKEND_TELNET default 3 help Maximum number of entries supported for poll() call. diff --git a/subsys/shell/backends/Kconfig.backends b/subsys/shell/backends/Kconfig.backends index e47e3e06613..0baf7772a77 100644 --- a/subsys/shell/backends/Kconfig.backends +++ b/subsys/shell/backends/Kconfig.backends @@ -443,11 +443,22 @@ config SHELL_BACKEND_TELNET bool "TELNET backend." depends on NET_TCP depends on NET_IPV4 || NET_IPV6 + select NET_SOCKETS_SERVICE + select NET_SOCKETS help Enable TELNET backend. if SHELL_BACKEND_TELNET +config SHELL_TELNET_INIT_PRIORITY + int "Initialization priority" + default 95 + range NET_SOCKETS_SERVICE_INIT_PRIO 99 + help + Initialization priority for telnet shell backend. This must be higher + than socket service initialization priority, as socket service has to + be initialized earlier. + config SHELL_PROMPT_TELNET string "Displayed prompt name" default "~$ " diff --git a/subsys/shell/backends/shell_telnet.c b/subsys/shell/backends/shell_telnet.c index 17a8683ac9d..319ea9f7288 100644 --- a/subsys/shell/backends/shell_telnet.c +++ b/subsys/shell/backends/shell_telnet.c @@ -8,9 +8,8 @@ #include #include -#include -#include -#include +#include +#include #include #include "shell_telnet_protocol.h" @@ -33,54 +32,49 @@ struct shell_telnet *sh_telnet; #define TELNET_MIN_COMMAND_LEN 2 #define TELNET_WILL_DO_COMMAND_LEN 3 -#define TELNET_RETRY_SEND_SLEEP_MS 50 +#define SOCK_ID_IPV4_LISTEN 0 +#define SOCK_ID_IPV6_LISTEN 1 +#define SOCK_ID_CLIENT 2 +#define SOCK_ID_MAX 3 /* Basic TELNET implementation. */ +static void telnet_server_cb(struct k_work *work); +static int telnet_init(struct shell_telnet *ctx); + +NET_SOCKET_SERVICE_SYNC_DEFINE_STATIC(telnet_server, NULL, telnet_server_cb, + SHELL_TELNET_POLLFD_COUNT); + + static void telnet_end_client_connection(void) { - struct net_pkt *pkt; + int ret; - (void)net_context_put(sh_telnet->client_ctx); + (void)zsock_close(sh_telnet->fds[SOCK_ID_CLIENT].fd); - sh_telnet->client_ctx = NULL; + sh_telnet->fds[SOCK_ID_CLIENT].fd = -1; sh_telnet->output_lock = false; k_work_cancel_delayable_sync(&sh_telnet->send_work, &sh_telnet->work_sync); - /* Flush the RX FIFO */ - while ((pkt = k_fifo_get(&sh_telnet->rx_fifo, K_NO_WAIT)) != NULL) { - net_pkt_unref(pkt); - } -} - -static void telnet_sent_cb(struct net_context *client, - int status, void *user_data) -{ - if (status < 0) { - telnet_end_client_connection(); - LOG_ERR("Could not send packet %d", status); + ret = net_socket_service_register(&telnet_server, sh_telnet->fds, + ARRAY_SIZE(sh_telnet->fds), NULL); + if (ret < 0) { + LOG_ERR("Failed to register socket service, %d", ret); } } static void telnet_command_send_reply(uint8_t *msg, uint16_t len) { - if (sh_telnet->client_ctx == NULL) { + if (sh_telnet->fds[SOCK_ID_CLIENT].fd < 0) { return; } while (len > 0) { int ret; - ret = net_context_send(sh_telnet->client_ctx, msg, len, telnet_sent_cb, - K_FOREVER, NULL); - - if (ret == -EAGAIN || ret == -ENOBUFS) { - k_sleep(K_MSEC(TELNET_RETRY_SEND_SLEEP_MS)); - continue; - } - + ret = zsock_send(sh_telnet->fds[SOCK_ID_CLIENT].fd, msg, len, 0); if (ret < 0) { LOG_ERR("Failed to send command %d, shutting down", ret); telnet_end_client_connection(); @@ -187,7 +181,7 @@ static void telnet_reply_command(struct telnet_simple_command *cmd) } } -static int telnet_send(void) +static int telnet_send(bool block) { int ret; uint8_t *msg = sh_telnet->line_out.buf; @@ -197,22 +191,25 @@ static int telnet_send(void) return 0; } - if (sh_telnet->client_ctx == NULL) { + if (sh_telnet->fds[SOCK_ID_CLIENT].fd < 0) { return -ENOTCONN; } while (len > 0) { - ret = net_context_send(sh_telnet->client_ctx, msg, - len, telnet_sent_cb, - K_FOREVER, NULL); - - if (ret == -EAGAIN || ret == -ENOBUFS) { - k_sleep(K_MSEC(TELNET_RETRY_SEND_SLEEP_MS)); - continue; + ret = zsock_send(sh_telnet->fds[SOCK_ID_CLIENT].fd, msg, len, + block ? 0 : ZSOCK_MSG_DONTWAIT); + if (!block && (ret < 0) && (errno == EAGAIN)) { + /* Not all data was sent - move the remaining data and + * update length. + */ + memmove(sh_telnet->line_out.buf, msg, len); + sh_telnet->line_out.len = len; + return -EAGAIN; } if (ret < 0) { - LOG_ERR("Failed to send %d, shutting down", ret); + ret = -errno; + LOG_ERR("Failed to send %d, shutting down", -ret); telnet_end_client_connection(); return ret; } @@ -229,18 +226,24 @@ static int telnet_send(void) static void telnet_send_prematurely(struct k_work *work) { - (void)telnet_send(); + int ret; + + /* Use non-blocking send to prevent system workqueue blocking. */ + ret = telnet_send(false); + if (ret == -EAGAIN) { + /* Not all data was sent, reschedule the work. */ + k_work_reschedule(&sh_telnet->send_work, K_MSEC(TELNET_TIMEOUT)); + } } -static inline int telnet_handle_command(struct net_pkt *pkt) +static inline int telnet_handle_command(uint8_t *buf) { /* Commands are two or three bytes. */ - NET_PKT_DATA_ACCESS_CONTIGUOUS_DEFINE(cmd_access, uint16_t); struct telnet_simple_command *cmd; - cmd = (struct telnet_simple_command *)net_pkt_get_data(pkt, - &cmd_access); - if (!cmd || cmd->iac != NVT_CMD_IAC) { + cmd = (struct telnet_simple_command *)buf; + + if (cmd->iac != NVT_CMD_IAC) { return 0; } @@ -262,90 +265,128 @@ static inline int telnet_handle_command(struct net_pkt *pkt) return TELNET_MIN_COMMAND_LEN; } -static void telnet_recv(struct net_context *client, - struct net_pkt *pkt, - union net_ip_header *ip_hdr, - union net_proto_header *proto_hdr, - int status, - void *user_data) +static void telnet_recv(struct zsock_pollfd *pollfd) { - size_t len; + size_t len, off, buf_left; + uint8_t *buf; int ret; - if (!pkt || status) { - telnet_end_client_connection(); + k_mutex_lock(&sh_telnet->rx_lock, K_FOREVER); - LOG_DBG("Telnet client dropped (AF_INET%s) status %d", - net_context_get_family(client) == AF_INET ? - "" : "6", status); + buf_left = sizeof(sh_telnet->rx_buf) - sh_telnet->rx_len; + if (buf_left == 0) { + /* No space left to read TCP stream, try again later. */ + k_mutex_unlock(&sh_telnet->rx_lock); + k_msleep(10); return; } - len = net_pkt_remaining_data(pkt); + buf = sh_telnet->rx_buf + sh_telnet->rx_len; - (void)net_context_update_recv_wnd(client, len); + ret = zsock_recv(pollfd->fd, buf, buf_left, 0); + if (ret < 0) { + LOG_DBG("Telnet client error %d", ret); + goto error; + } else if (ret == 0) { + LOG_DBG("Telnet client closed connection"); + goto error; + } + off = 0; + len = ret; while (len >= TELNET_MIN_COMMAND_LEN) { - ret = telnet_handle_command(pkt); + ret = telnet_handle_command(buf + off); if (ret > 0) { LOG_DBG("Handled command"); - ret = net_pkt_skip(pkt, ret); - if (ret < 0) { - goto unref; - } + off += ret; } else if (ret < 0) { - goto unref; + goto error; } else { break; } - len = net_pkt_remaining_data(pkt); + len -= ret; } if (len == 0) { - goto unref; + k_mutex_unlock(&sh_telnet->rx_lock); + return; } - /* Fifo add */ - k_fifo_put(&sh_telnet->rx_fifo, pkt); + memmove(buf, buf + off, len); + sh_telnet->rx_len += len; + + k_mutex_unlock(&sh_telnet->rx_lock); sh_telnet->shell_handler(SHELL_TRANSPORT_EVT_RX_RDY, sh_telnet->shell_context); return; -unref: - net_pkt_unref(pkt); +error: + k_mutex_unlock(&sh_telnet->rx_lock); + telnet_end_client_connection(); } -static void telnet_accept(struct net_context *client, - struct sockaddr *addr, - socklen_t addrlen, - int error, - void *user_data) +static void telnet_restart_server(void) { - if (error) { - LOG_ERR("Error %d", error); - goto error; + int ret; + + if (sh_telnet->fds[SOCK_ID_IPV4_LISTEN].fd >= 0) { + (void)zsock_close(sh_telnet->fds[SOCK_ID_IPV4_LISTEN].fd); + sh_telnet->fds[SOCK_ID_IPV4_LISTEN].fd = -1; } - if (sh_telnet->client_ctx) { - LOG_INF("A telnet client is already in."); - goto error; + if (sh_telnet->fds[SOCK_ID_IPV6_LISTEN].fd >= 0) { + (void)zsock_close(sh_telnet->fds[SOCK_ID_IPV6_LISTEN].fd); + sh_telnet->fds[SOCK_ID_IPV6_LISTEN].fd = -1; + } + + if (sh_telnet->fds[SOCK_ID_CLIENT].fd >= 0) { + (void)zsock_close(sh_telnet->fds[SOCK_ID_CLIENT].fd); + sh_telnet->fds[SOCK_ID_CLIENT].fd = -1; } - if (net_context_recv(client, telnet_recv, K_NO_WAIT, NULL)) { - LOG_ERR("Unable to setup reception (family %u)", - net_context_get_family(client)); + ret = telnet_init(sh_telnet); + if (ret < 0) { + LOG_ERR("Telnet fatal error, failed to restart server (%d)", ret); + (void)net_socket_service_unregister(&telnet_server); + } +} + +static void telnet_accept(struct zsock_pollfd *pollfd) +{ + int sock, ret = 0; + struct sockaddr addr; + socklen_t addrlen = sizeof(struct sockaddr); + + sock = zsock_accept(pollfd->fd, &addr, &addrlen); + if (sock < 0) { + ret = -errno; + NET_ERR("Telnet accept error (%d)", ret); + return; + } + + if (sh_telnet->fds[SOCK_ID_CLIENT].fd > 0) { + /* Too many connections. */ + ret = 0; + NET_ERR("Telnet client already connected."); goto error; } - net_context_set_accepting(client, false); + sh_telnet->fds[SOCK_ID_CLIENT].fd = sock; + sh_telnet->fds[SOCK_ID_CLIENT].events = ZSOCK_POLLIN; - LOG_DBG("Telnet client connected (family AF_INET%s)", - net_context_get_family(client) == AF_INET ? "" : "6"); + ret = net_socket_service_register(&telnet_server, sh_telnet->fds, + ARRAY_SIZE(sh_telnet->fds), NULL); + if (ret < 0) { + LOG_ERR("Failed to register socket service, (%d)", ret); + sh_telnet->fds[SOCK_ID_CLIENT].fd = -1; + goto error; + } - sh_telnet->client_ctx = client; + LOG_DBG("Telnet client connected (family AF_INET%s)", + addr.sa_family == AF_INET ? "" : "6"); /* Disable echo - if command handling is enabled we reply that we * support echo. @@ -353,61 +394,122 @@ static void telnet_accept(struct net_context *client, (void)telnet_echo_set(sh_telnet->shell_context, false); return; + error: - net_context_put(client); + if (sock > 0) { + (void)zsock_close(sock); + } + + if (ret < 0) { + telnet_restart_server(); + } } -static void telnet_setup_server(struct net_context **ctx, sa_family_t family, - struct sockaddr *addr, socklen_t addrlen) +static void telnet_server_cb(struct k_work *work) { - if (net_context_get(family, SOCK_STREAM, IPPROTO_TCP, ctx)) { - LOG_ERR("No context available"); + struct net_socket_service_event *evt = + CONTAINER_OF(work, struct net_socket_service_event, work); + int sock_error; + socklen_t optlen = sizeof(int); + + if (sh_telnet == NULL) { + return; + } + + if ((evt->event.revents & ZSOCK_POLLERR) || + (evt->event.revents & ZSOCK_POLLNVAL)) { + (void)zsock_getsockopt(evt->event.fd, SOL_SOCKET, + SO_ERROR, &sock_error, &optlen); + NET_ERR("Telnet socket %d error (%d)", evt->event.fd, sock_error); + + if (evt->event.fd == sh_telnet->fds[SOCK_ID_CLIENT].fd) { + return telnet_end_client_connection(); + } + goto error; } - if (net_context_bind(*ctx, addr, addrlen)) { - LOG_ERR("Cannot bind on family AF_INET%s", + if (!(evt->event.revents & ZSOCK_POLLIN)) { + return; + } + + if (evt->event.fd == sh_telnet->fds[SOCK_ID_IPV4_LISTEN].fd) { + return telnet_accept(&sh_telnet->fds[SOCK_ID_IPV4_LISTEN]); + } else if (evt->event.fd == sh_telnet->fds[SOCK_ID_IPV6_LISTEN].fd) { + return telnet_accept(&sh_telnet->fds[SOCK_ID_IPV6_LISTEN]); + } else if (evt->event.fd == sh_telnet->fds[SOCK_ID_CLIENT].fd) { + return telnet_recv(&sh_telnet->fds[SOCK_ID_CLIENT]); + } + + NET_ERR("Unexpected FD received for telnet, restarting service."); + +error: + telnet_restart_server(); +} + +static int telnet_setup_server(struct zsock_pollfd *pollfd, sa_family_t family, + struct sockaddr *addr, socklen_t addrlen) +{ + int ret = 0; + + pollfd->fd = zsock_socket(family, SOCK_STREAM, IPPROTO_TCP); + if (pollfd->fd < 0) { + ret = -errno; + LOG_ERR("Failed to create telnet AF_INET%s socket", family == AF_INET ? "" : "6"); goto error; } - if (net_context_listen(*ctx, 0)) { - LOG_ERR("Cannot listen on"); + if (zsock_bind(pollfd->fd, addr, addrlen) < 0) { + ret = -errno; + LOG_ERR("Cannot bind on family AF_INET%s (%d)", + family == AF_INET ? "" : "6", ret); goto error; } - if (net_context_accept(*ctx, telnet_accept, K_NO_WAIT, NULL)) { - LOG_ERR("Cannot accept"); + if (zsock_listen(pollfd->fd, 1)) { + ret = -errno; + LOG_ERR("Cannot listen on family AF_INET%s (%d)", + family == AF_INET ? "" : "6", ret); goto error; } + pollfd->events = ZSOCK_POLLIN; + LOG_DBG("Telnet console enabled on AF_INET%s", family == AF_INET ? "" : "6"); - return; + return 0; + error: - LOG_ERR("Unable to start telnet on AF_INET%s", - family == AF_INET ? "" : "6"); + LOG_ERR("Unable to start telnet on AF_INET%s (%d)", + family == AF_INET ? "" : "6", ret); - if (*ctx) { - (void)net_context_put(*ctx); - *ctx = NULL; + if (pollfd->fd >= 0) { + (void)zsock_close(pollfd->fd); + pollfd->fd = -1; } + + return ret; } -static int telnet_init(void) +static int telnet_init(struct shell_telnet *ctx) { + int ret; + if (IS_ENABLED(CONFIG_NET_IPV4)) { struct sockaddr_in any_addr4 = { .sin_family = AF_INET, .sin_port = htons(TELNET_PORT), .sin_addr = INADDR_ANY_INIT }; - static struct net_context *ctx4; - telnet_setup_server(&ctx4, AF_INET, - (struct sockaddr *)&any_addr4, - sizeof(any_addr4)); + ret = telnet_setup_server(&ctx->fds[SOCK_ID_IPV4_LISTEN], + AF_INET, (struct sockaddr *)&any_addr4, + sizeof(any_addr4)); + if (ret < 0) { + goto error; + } } if (IS_ENABLED(CONFIG_NET_IPV6)) { @@ -416,16 +518,38 @@ static int telnet_init(void) .sin6_port = htons(TELNET_PORT), .sin6_addr = IN6ADDR_ANY_INIT }; - static struct net_context *ctx6; - telnet_setup_server(&ctx6, AF_INET6, - (struct sockaddr *)&any_addr6, - sizeof(any_addr6)); + ret = telnet_setup_server(&ctx->fds[SOCK_ID_IPV6_LISTEN], + AF_INET6, (struct sockaddr *)&any_addr6, + sizeof(any_addr6)); + if (ret < 0) { + goto error; + } + } + + ret = net_socket_service_register(&telnet_server, ctx->fds, + ARRAY_SIZE(ctx->fds), NULL); + if (ret < 0) { + LOG_ERR("Failed to register socket service, %d", ret); + goto error; } LOG_INF("Telnet shell backend initialized"); return 0; + +error: + if (ctx->fds[SOCK_ID_IPV4_LISTEN].fd >= 0) { + (void)zsock_close(ctx->fds[SOCK_ID_IPV4_LISTEN].fd); + ctx->fds[SOCK_ID_IPV4_LISTEN].fd = -1; + } + + if (ctx->fds[SOCK_ID_IPV6_LISTEN].fd >= 0) { + (void)zsock_close(ctx->fds[SOCK_ID_IPV6_LISTEN].fd); + ctx->fds[SOCK_ID_IPV6_LISTEN].fd = -1; + } + + return ret; } /* Shell API */ @@ -440,17 +564,20 @@ static int init(const struct shell_transport *transport, sh_telnet = (struct shell_telnet *)transport->ctx; memset(sh_telnet, 0, sizeof(struct shell_telnet)); + for (int i = 0; i < ARRAY_SIZE(sh_telnet->fds); i++) { + sh_telnet->fds[i].fd = -1; + } sh_telnet->shell_handler = evt_handler; sh_telnet->shell_context = context; - err = telnet_init(); + err = telnet_init(sh_telnet); if (err != 0) { return err; } - k_fifo_init(&sh_telnet->rx_fifo); k_work_init_delayable(&sh_telnet->send_work, telnet_send_prematurely); + k_mutex_init(&sh_telnet->rx_lock); return 0; } @@ -487,7 +614,7 @@ static int write(const struct shell_transport *transport, return -ENODEV; } - if (sh_telnet->client_ctx == NULL || sh_telnet->output_lock) { + if (sh_telnet->fds[SOCK_ID_CLIENT].fd < 0 || sh_telnet->output_lock) { *cnt = length; return 0; } @@ -517,7 +644,7 @@ static int write(const struct shell_transport *transport, */ if (lb->buf[lb->len - 1] == '\n' || lb->len == TELNET_LINE_SIZE) { - err = telnet_send(); + err = telnet_send(true); if (err != 0) { *cnt = length; return err; @@ -544,42 +671,39 @@ static int write(const struct shell_transport *transport, static int read(const struct shell_transport *transport, void *data, size_t length, size_t *cnt) { - struct net_pkt *pkt; size_t read_len; - bool flush = true; if (sh_telnet == NULL) { return -ENODEV; } - if (sh_telnet->client_ctx == NULL) { + if (sh_telnet->fds[SOCK_ID_CLIENT].fd < 0) { goto no_data; } - pkt = k_fifo_peek_head(&sh_telnet->rx_fifo); - if (pkt == NULL) { + k_mutex_lock(&sh_telnet->rx_lock, K_FOREVER); + + if (sh_telnet->rx_len == 0) { + k_mutex_unlock(&sh_telnet->rx_lock); goto no_data; } - read_len = net_pkt_remaining_data(pkt); + read_len = sh_telnet->rx_len; if (read_len > length) { read_len = length; - flush = false; } + memcpy(data, sh_telnet->rx_buf, read_len); *cnt = read_len; - if (net_pkt_read(pkt, data, read_len) < 0) { - /* Failed to read, get rid of the faulty packet. */ - LOG_ERR("Failed to read net packet."); - *cnt = 0; - flush = true; - } - if (flush) { - (void)k_fifo_get(&sh_telnet->rx_fifo, K_NO_WAIT); - net_pkt_unref(pkt); + sh_telnet->rx_len -= read_len; + if (sh_telnet->rx_len > 0) { + memmove(sh_telnet->rx_buf, sh_telnet->rx_buf + read_len, + sh_telnet->rx_len); } + k_mutex_unlock(&sh_telnet->rx_lock); + return 0; no_data: @@ -597,7 +721,6 @@ const struct shell_transport_api shell_telnet_transport_api = { static int enable_shell_telnet(void) { - bool log_backend = CONFIG_SHELL_TELNET_INIT_LOG_LEVEL > 0; uint32_t level = (CONFIG_SHELL_TELNET_INIT_LOG_LEVEL > LOG_LEVEL_DBG) ? CONFIG_LOG_MAX_LEVEL : CONFIG_SHELL_TELNET_INIT_LOG_LEVEL; @@ -607,7 +730,11 @@ static int enable_shell_telnet(void) return shell_init(&shell_telnet, NULL, cfg_flags, log_backend, level); } -SYS_INIT(enable_shell_telnet, APPLICATION, 0); +BUILD_ASSERT(CONFIG_SHELL_TELNET_INIT_PRIORITY > CONFIG_NET_SOCKETS_SERVICE_INIT_PRIO, + "CONFIG_SHELL_TELNET_INIT_PRIORITY must be higher than " + "CONFIG_NET_SOCKETS_SERVICE_INIT_PRIO"); + +SYS_INIT(enable_shell_telnet, APPLICATION, CONFIG_SHELL_TELNET_INIT_PRIORITY); const struct shell *shell_backend_telnet_get_ptr(void) { From 5bb97a112d4988e3ed1eb5d25be3aa6f9eb2d955 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Thu, 29 Feb 2024 13:35:52 +0100 Subject: [PATCH 0449/2402] net: telnet: Improve command processing Current TELNET implementation wrongly assumed that if the command is present, it will always be included at the beginning of the packet/data buffer. Such assumptions however are not valid for STREAM sockets, where the actual stream data could be fragmented in any way. Therefore, the command parsing needed rework, so that we analyze each byte received for the command escape code, and once received we enter "command parsing" mode. Once no more commands are identified in a data streak, the command bytes are removed from the data buffer before the buffer is provided to the shell subsystem for processing. Signed-off-by: Robert Lubos --- include/zephyr/shell/shell_telnet.h | 3 + subsys/shell/backends/shell_telnet.c | 101 +++++++++++++++++++++------ 2 files changed, 82 insertions(+), 22 deletions(-) diff --git a/include/zephyr/shell/shell_telnet.h b/include/zephyr/shell/shell_telnet.h index 2b8324a290a..6501a63fa1b 100644 --- a/include/zephyr/shell/shell_telnet.h +++ b/include/zephyr/shell/shell_telnet.h @@ -17,6 +17,7 @@ extern "C" { extern const struct shell_transport_api shell_telnet_transport_api; #define SHELL_TELNET_POLLFD_COUNT 3 +#define SHELL_TELNET_MAX_CMD_SIZE 3 /** Line buffer structure. */ struct shell_telnet_line_buf { @@ -49,6 +50,8 @@ struct shell_telnet { /** Mutex protecting the input buffer access. */ struct k_mutex rx_lock; + uint8_t cmd_buf[SHELL_TELNET_MAX_CMD_SIZE]; + uint8_t cmd_len; /** The delayed work is used to send non-lf terminated output that has * been around for "too long". This will prove to be useful diff --git a/subsys/shell/backends/shell_telnet.c b/subsys/shell/backends/shell_telnet.c index 319ea9f7288..e0fff643501 100644 --- a/subsys/shell/backends/shell_telnet.c +++ b/subsys/shell/backends/shell_telnet.c @@ -236,13 +236,19 @@ static void telnet_send_prematurely(struct k_work *work) } } -static inline int telnet_handle_command(uint8_t *buf) +static int telnet_command_length(uint8_t op) { - /* Commands are two or three bytes. */ - struct telnet_simple_command *cmd; + if (op == NVT_CMD_SB || op == NVT_CMD_WILL || op == NVT_CMD_WONT || + op == NVT_CMD_DO || op == NVT_CMD_DONT) { + return TELNET_WILL_DO_COMMAND_LEN; + } - cmd = (struct telnet_simple_command *)buf; + return TELNET_MIN_COMMAND_LEN; +} +static inline int telnet_handle_command(struct telnet_simple_command *cmd) +{ + /* Commands are two or three bytes. */ if (cmd->iac != NVT_CMD_IAC) { return 0; } @@ -257,17 +263,14 @@ static inline int telnet_handle_command(uint8_t *buf) return -EOPNOTSUPP; } - if (cmd->op == NVT_CMD_WILL || cmd->op == NVT_CMD_WONT || - cmd->op == NVT_CMD_DO || cmd->op == NVT_CMD_DONT) { - return TELNET_WILL_DO_COMMAND_LEN; - } - - return TELNET_MIN_COMMAND_LEN; + return 0; } static void telnet_recv(struct zsock_pollfd *pollfd) { - size_t len, off, buf_left; + struct telnet_simple_command *cmd = + (struct telnet_simple_command *)sh_telnet->cmd_buf; + size_t len, off, buf_left, cmd_total_len; uint8_t *buf; int ret; @@ -294,18 +297,70 @@ static void telnet_recv(struct zsock_pollfd *pollfd) off = 0; len = ret; - while (len >= TELNET_MIN_COMMAND_LEN) { - ret = telnet_handle_command(buf + off); - if (ret > 0) { - LOG_DBG("Handled command"); - off += ret; - } else if (ret < 0) { - goto error; - } else { - break; + cmd_total_len = 0; + /* Filter out and process commands from the data buffer. */ + while (off < len) { + if (sh_telnet->cmd_len > 0) { + /* Command mode */ + if (sh_telnet->cmd_len == 1) { + /* Operation */ + cmd->op = *(buf + off); + sh_telnet->cmd_len++; + cmd_total_len++; + off++; + + if (telnet_command_length(cmd->op) > + TELNET_MIN_COMMAND_LEN) { + continue; + } + } else if (sh_telnet->cmd_len == 2) { + /* Option */ + cmd->opt = *(buf + off); + sh_telnet->cmd_len++; + cmd_total_len++; + off++; + } + + ret = telnet_handle_command(cmd); + if (ret < 0) { + goto error; + } else { + LOG_DBG("Handled command"); + } + + memset(cmd, 0, sizeof(*cmd)); + sh_telnet->cmd_len = 0; + + continue; } - len -= ret; + if (*(buf + off) == NVT_CMD_IAC) { + cmd->iac = *(buf + off); + sh_telnet->cmd_len++; + cmd_total_len++; + off++; + continue; + } + + /* Data byte, remove command bytes from the buffer, if any. */ + if (cmd_total_len > 0) { + size_t data_off = off; + + off -= cmd_total_len; + len -= cmd_total_len; + cmd_total_len = 0; + + memmove(buf + off, buf + data_off, len); + } + + off++; + } + + if (cmd_total_len > 0) { + /* In case the buffer ended with command, trim the buffer size + * here. + */ + len -= cmd_total_len; } if (len == 0) { @@ -313,7 +368,6 @@ static void telnet_recv(struct zsock_pollfd *pollfd) return; } - memmove(buf, buf + off, len); sh_telnet->rx_len += len; k_mutex_unlock(&sh_telnet->rx_lock); @@ -376,6 +430,9 @@ static void telnet_accept(struct zsock_pollfd *pollfd) sh_telnet->fds[SOCK_ID_CLIENT].fd = sock; sh_telnet->fds[SOCK_ID_CLIENT].events = ZSOCK_POLLIN; + sh_telnet->rx_len = 0; + sh_telnet->cmd_len = 0; + sh_telnet->line_out.len = 0; ret = net_socket_service_register(&telnet_server, sh_telnet->fds, ARRAY_SIZE(sh_telnet->fds), NULL); From 4300f042bbf7a454a0053c9bc0354ac1b5f4e4e3 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Thu, 29 Feb 2024 13:51:55 +0100 Subject: [PATCH 0450/2402] net: telnet: Fix spelling in command defines Rename command defines to make checkpatch happy. Signed-off-by: Robert Lubos --- subsys/shell/backends/shell_telnet.c | 14 +++++++------- subsys/shell/backends/shell_telnet_protocol.h | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/subsys/shell/backends/shell_telnet.c b/subsys/shell/backends/shell_telnet.c index e0fff643501..e75d5ebaa86 100644 --- a/subsys/shell/backends/shell_telnet.c +++ b/subsys/shell/backends/shell_telnet.c @@ -111,14 +111,14 @@ static void telnet_reply_dont_command(struct telnet_simple_command *cmd) int ret = telnet_echo_set(sh_telnet->shell_context, false); if (ret >= 0) { - cmd->op = NVT_CMD_WONT; + cmd->op = NVT_CMD_WILL_NOT; } else { cmd->op = NVT_CMD_WILL; } break; } default: - cmd->op = NVT_CMD_WONT; + cmd->op = NVT_CMD_WILL_NOT; break; } @@ -139,12 +139,12 @@ static void telnet_reply_do_command(struct telnet_simple_command *cmd) if (ret >= 0) { cmd->op = NVT_CMD_WILL; } else { - cmd->op = NVT_CMD_WONT; + cmd->op = NVT_CMD_WILL_NOT; } break; } default: - cmd->op = NVT_CMD_WONT; + cmd->op = NVT_CMD_WILL_NOT; break; } @@ -172,7 +172,7 @@ static void telnet_reply_command(struct telnet_simple_command *cmd) case NVT_CMD_DO: telnet_reply_do_command(cmd); break; - case NVT_CMD_DONT: + case NVT_CMD_DO_NOT: telnet_reply_dont_command(cmd); break; default: @@ -238,8 +238,8 @@ static void telnet_send_prematurely(struct k_work *work) static int telnet_command_length(uint8_t op) { - if (op == NVT_CMD_SB || op == NVT_CMD_WILL || op == NVT_CMD_WONT || - op == NVT_CMD_DO || op == NVT_CMD_DONT) { + if (op == NVT_CMD_SB || op == NVT_CMD_WILL || op == NVT_CMD_WILL_NOT || + op == NVT_CMD_DO || op == NVT_CMD_DO_NOT) { return TELNET_WILL_DO_COMMAND_LEN; } diff --git a/subsys/shell/backends/shell_telnet_protocol.h b/subsys/shell/backends/shell_telnet_protocol.h index a957484294d..b2ffeff96e6 100644 --- a/subsys/shell/backends/shell_telnet_protocol.h +++ b/subsys/shell/backends/shell_telnet_protocol.h @@ -43,9 +43,9 @@ #define NVT_CMD_GA 249 #define NVT_CMD_SB 250 #define NVT_CMD_WILL 251 -#define NVT_CMD_WONT 252 +#define NVT_CMD_WILL_NOT 252 #define NVT_CMD_DO 253 -#define NVT_CMD_DONT 254 +#define NVT_CMD_DO_NOT 254 #define NVT_CMD_IAC 255 /* Telnet options */ From 36c12482c6ff4349307c93c67e9cd914ed0c6d1c Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Wed, 6 Mar 2024 13:06:19 +0000 Subject: [PATCH 0451/2402] scripts: tests: --package-artifacts fix, blackbox tests Requirements added for bz2. Blackbox test for --package-artifacts added. package.py no longer includes twister-out no matter the outdir. Signed-off-by: Lukasz Mrugala --- scripts/pylib/twister/twisterlib/package.py | 2 +- scripts/requirements-run-test.txt | 3 ++ .../tests/twister_blackbox/test_outfile.py | 53 +++++++++++++++++++ 3 files changed, 57 insertions(+), 1 deletion(-) diff --git a/scripts/pylib/twister/twisterlib/package.py b/scripts/pylib/twister/twisterlib/package.py index 5ae17e7601c..c86c99c1534 100644 --- a/scripts/pylib/twister/twisterlib/package.py +++ b/scripts/pylib/twister/twisterlib/package.py @@ -15,7 +15,7 @@ def __init__(self, env): def make_tarfile(self, output_filename, source_dirs): root = os.path.basename(self.options.outdir) with tarfile.open(output_filename, "w:bz2") as tar: - tar.add("twister-out", recursive=False) + tar.add(self.options.outdir, recursive=False) for d in source_dirs: f = os.path.relpath(d, self.options.outdir) tar.add(d, arcname=os.path.join(root, f)) diff --git a/scripts/requirements-run-test.txt b/scripts/requirements-run-test.txt index 83692128110..a710eb962a5 100644 --- a/scripts/requirements-run-test.txt +++ b/scripts/requirements-run-test.txt @@ -14,3 +14,6 @@ cbor>=1.0.0 # use for twister psutil + +# Artifacts package creation +bz diff --git a/scripts/tests/twister_blackbox/test_outfile.py b/scripts/tests/twister_blackbox/test_outfile.py index 5e019d672fc..46c006323c7 100644 --- a/scripts/tests/twister_blackbox/test_outfile.py +++ b/scripts/tests/twister_blackbox/test_outfile.py @@ -13,6 +13,7 @@ import shutil import pytest import sys +import tarfile from conftest import ZEPHYR_BASE, TEST_DATA, sample_filename_mock, testsuite_filename_mock from twisterlib.testplan import TestPlan @@ -199,3 +200,55 @@ def test_prep_artifacts_for_testing(self, out_path): # However, the cost of testing that this leaves less seems to outweigh the benefits. # So we'll only check for the most important artifact. assert 'zephyr.elf' in zephyr_artifact_list + + def test_package_artifacts(self, out_path): + test_platforms = ['qemu_x86'] + path = os.path.join(TEST_DATA, 'samples', 'hello_world') + package_name = 'PACKAGE' + package_path = os.path.join(out_path, package_name) + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--package-artifacts', package_path] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + # Check whether we have something as basic as zephyr.elf file + with tarfile.open(package_path, "r") as tar: + assert any([path.endswith('zephyr.elf') for path in tar.getnames()]) + + # Delete everything but for the package + for clean_up in os.listdir(os.path.join(out_path)): + if not clean_up.endswith(package_name): + clean_up_path = os.path.join(out_path, clean_up) + if os.path.isfile(clean_up_path): + os.remove(clean_up_path) + else: + shutil.rmtree(os.path.join(out_path, clean_up)) + + # Unpack the package + with tarfile.open(package_path, "r") as tar: + tar.extractall(path=out_path) + + # Why does package.py put files inside the out_path folder? + # It forces us to move files up one directory after extraction. + file_names = os.listdir(os.path.join(out_path, os.path.basename(out_path))) + for file_name in file_names: + shutil.move(os.path.join(out_path, os.path.basename(out_path), file_name), out_path) + + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--test-only'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' From b47c66e3f293c171e388fb285ae4f30e31068e62 Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Wed, 29 Nov 2023 16:55:21 +0100 Subject: [PATCH 0452/2402] drivers: adc: implement voltage biasing for ADS114s08 Implement voltage biasing on the inputs of the ADC ADS114s08. Signed-off-by: Benedikt Schmidt --- drivers/adc/Kconfig | 5 +++++ drivers/adc/Kconfig.ads114s0x | 1 + drivers/adc/adc_ads114s0x.c | 32 +++++++++++++++++++++++++--- dts/bindings/adc/adc-controller.yaml | 7 ++++++ dts/bindings/adc/ti,ads114s08.yaml | 9 ++++++++ include/zephyr/drivers/adc.h | 14 ++++++++++++ 6 files changed, 65 insertions(+), 3 deletions(-) diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index 721de86c98f..ac0babf123f 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -33,6 +33,11 @@ config ADC_CONFIGURABLE_INPUTS config ADC_CONFIGURABLE_EXCITATION_CURRENT_SOURCE_PIN bool +# By selecting or not this option particular ADC drivers indicate if they +# allow a configurable voltage bias pin. +config ADC_CONFIGURABLE_VBIAS_PIN + bool + config ADC_ASYNC bool "Asynchronous call support" select POLL diff --git a/drivers/adc/Kconfig.ads114s0x b/drivers/adc/Kconfig.ads114s0x index 4507ad30217..45191bb92ea 100644 --- a/drivers/adc/Kconfig.ads114s0x +++ b/drivers/adc/Kconfig.ads114s0x @@ -9,6 +9,7 @@ menuconfig ADC_ADS114S0X select SPI select ADC_CONFIGURABLE_INPUTS select ADC_CONFIGURABLE_EXCITATION_CURRENT_SOURCE_PIN + select ADC_CONFIGURABLE_VBIAS_PIN help Enable the driver implementation for the ADS114S0X family diff --git a/drivers/adc/adc_ads114s0x.c b/drivers/adc/adc_ads114s0x.c index 16a7bfabfad..9864fd689f4 100644 --- a/drivers/adc/adc_ads114s0x.c +++ b/drivers/adc/adc_ads114s0x.c @@ -32,6 +32,8 @@ LOG_MODULE_REGISTER(ads114s0x, CONFIG_ADC_LOG_LEVEL); #define ADS114S0X_REF_INTERNAL 2500 #define ADS114S0X_GPIO_MAX 3 #define ADS114S0X_POWER_ON_RESET_TIME_IN_US 2200 +#define ADS114S0X_VBIAS_PIN_MAX 7 +#define ADS114S0X_VBIAS_PIN_MIN 0 /* Not mentioned in the datasheet, but instead determined experimentally. */ #define ADS114S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US 1000 @@ -317,6 +319,14 @@ enum ads114s0x_register { #define ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(target, value) \ ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMUX_I1MUX_POS, \ ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH) +#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH 1 +#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS 7 +#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_GET(value) \ + ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS, \ + ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH) +#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_SET(target, value) \ + ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS, \ + ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH) #define ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH 4 #define ADS114S0X_REGISTER_GPIODAT_DIR_POS 4 #define ADS114S0X_REGISTER_GPIODAT_DIR_GET(value) \ @@ -410,6 +420,7 @@ struct ads114s0x_config { const struct gpio_dt_spec gpio_data_ready; const struct gpio_dt_spec gpio_start_sync; int idac_current; + uint8_t vbias_level; }; struct ads114s0x_data { @@ -597,9 +608,10 @@ static int ads114s0x_channel_setup(const struct device *dev, uint8_t idac_magnitude = 0; uint8_t idac_mux = 0; uint8_t pin_selections[4]; + uint8_t vbias = 0; size_t pin_selections_size; int result; - enum ads114s0x_register register_addresses[6]; + enum ads114s0x_register register_addresses[7]; uint8_t values[ARRAY_SIZE(register_addresses)]; uint16_t acquisition_time_value = ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time); uint16_t acquisition_time_unit = ADC_ACQ_TIME_UNIT(channel_cfg->acquisition_time); @@ -820,20 +832,33 @@ static int ads114s0x_channel_setup(const struct device *dev, } } + ADS114S0X_REGISTER_VBIAS_VB_LEVEL_SET(vbias, config->vbias_level); + + if ((channel_cfg->vbias_pins & + ~GENMASK(ADS114S0X_VBIAS_PIN_MAX, ADS114S0X_VBIAS_PIN_MIN)) != 0) { + LOG_ERR("%s: invalid VBIAS pin selection 0x%08X", dev->name, + channel_cfg->vbias_pins); + return -EINVAL; + } + + vbias |= channel_cfg->vbias_pins; + register_addresses[0] = ADS114S0X_REGISTER_INPMUX; register_addresses[1] = ADS114S0X_REGISTER_PGA; register_addresses[2] = ADS114S0X_REGISTER_DATARATE; register_addresses[3] = ADS114S0X_REGISTER_REF; register_addresses[4] = ADS114S0X_REGISTER_IDACMAG; register_addresses[5] = ADS114S0X_REGISTER_IDACMUX; - BUILD_ASSERT(ARRAY_SIZE(register_addresses) == 6); + register_addresses[6] = ADS114S0X_REGISTER_VBIAS; + BUILD_ASSERT(ARRAY_SIZE(register_addresses) == 7); values[0] = input_mux; values[1] = gain; values[2] = data_rate; values[3] = reference_control; values[4] = idac_magnitude; values[5] = idac_mux; - BUILD_ASSERT(ARRAY_SIZE(values) == 6); + values[6] = vbias; + BUILD_ASSERT(ARRAY_SIZE(values) == 7); result = ads114s0x_write_multiple_registers(dev, register_addresses, values, ARRAY_SIZE(values)); @@ -1474,6 +1499,7 @@ BUILD_ASSERT(CONFIG_ADC_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY, .gpio_data_ready = GPIO_DT_SPEC_INST_GET(n, drdy_gpios), \ .gpio_start_sync = GPIO_DT_SPEC_INST_GET_OR(n, start_sync_gpios, {0}), \ .idac_current = DT_INST_PROP(n, idac_current), \ + .vbias_level = DT_INST_PROP(n, vbias_level), \ }; \ static struct ads114s0x_data data_##n; \ DEVICE_DT_INST_DEFINE(n, ads114s0x_init, NULL, &data_##n, &config_##n, POST_KERNEL, \ diff --git a/dts/bindings/adc/adc-controller.yaml b/dts/bindings/adc/adc-controller.yaml index 4c9c3e3fea6..c52c913d522 100644 --- a/dts/bindings/adc/adc-controller.yaml +++ b/dts/bindings/adc/adc-controller.yaml @@ -160,3 +160,10 @@ child-binding: interpretation depends on the driver. This is used only for drivers which select the ADC_CONFIGURABLE_EXCITATION_CURRENT_SOURCE_PIN Kconfig option. + + zephyr,vbias-pins: + type: int + description: | + Output pin selection for the bias voltage. The actual interpretation + depends on the driver. This is used only for drivers which select + the ADC_CONFIGURABLE_VBIAS_PIN Kconfig option. diff --git a/dts/bindings/adc/ti,ads114s08.yaml b/dts/bindings/adc/ti,ads114s08.yaml index a172439e051..cf91c11652b 100644 --- a/dts/bindings/adc/ti,ads114s08.yaml +++ b/dts/bindings/adc/ti,ads114s08.yaml @@ -45,5 +45,14 @@ properties: description: | IDAC current in microampere, the default value turns the current source off + vbias-level: + type: int + enum: + - 0 + - 1 + default: 0 + description: | + bias voltage level: 0 - (AVDD+AVSS)/2, 1 - (AVDD+AVSS)/12 + io-channel-cells: - input diff --git a/include/zephyr/drivers/adc.h b/include/zephyr/drivers/adc.h index be88e78b067..01ec48672f3 100644 --- a/include/zephyr/drivers/adc.h +++ b/include/zephyr/drivers/adc.h @@ -156,6 +156,18 @@ struct adc_channel_cfg { */ uint8_t current_source_pin[2]; #endif /* CONFIG_ADC_CONFIGURABLE_EXCITATION_CURRENT_SOURCE_PIN */ + +#ifdef CONFIG_ADC_CONFIGURABLE_VBIAS_PIN + /** + * Output pins for the bias voltage. + * This is only available if the driver enables this feature + * via the hidden configuration option ADC_CONFIGURABLE_VBIAS_PIN. + * The field is interpreted as a bitmask, where each bit represents + * one of the input pins. The actual mapping to the physical pins + * depends on the driver itself. + */ + uint32_t vbias_pins; +#endif /* CONFIG_ADC_CONFIGURABLE_VBIAS_PIN */ }; /** @@ -236,6 +248,8 @@ IF_ENABLED(DT_PROP(node_id, zephyr_differential), \ IF_ENABLED(CONFIG_ADC_CONFIGURABLE_EXCITATION_CURRENT_SOURCE_PIN, \ (.current_source_pin_set = DT_NODE_HAS_PROP(node_id, zephyr_current_source_pin), \ .current_source_pin = DT_PROP_OR(node_id, zephyr_current_source_pin, {0}),)) \ +IF_ENABLED(CONFIG_ADC_CONFIGURABLE_VBIAS_PIN, \ + (.vbias_pins = DT_PROP_OR(node_id, zephyr_vbias_pins, 0),)) \ } /** From a10b84299162a04c34a47edf7d51094f0f8ceddf Mon Sep 17 00:00:00 2001 From: Patryk Kuniecki Date: Sat, 20 Jan 2024 02:52:51 +0100 Subject: [PATCH 0453/2402] scripts: tests: twister_blackbox: Add test test_verbose.py Add new test to twister blackbox tests Signed-off-by: Patryk Kuniecki --- scripts/tests/twister_blackbox/test_output.py | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/scripts/tests/twister_blackbox/test_output.py b/scripts/tests/twister_blackbox/test_output.py index e01e69ce06c..4c5a60e5dec 100644 --- a/scripts/tests/twister_blackbox/test_output.py +++ b/scripts/tests/twister_blackbox/test_output.py @@ -20,6 +20,11 @@ @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) class TestOutput: + TESTDATA_1 = [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic') + ), +] @classmethod def setup_class(cls): apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') @@ -123,3 +128,68 @@ def test_inline_logs(self, out_path): split_build_log = build_log.split('\n') for r in split_build_log: assert r in inline_twister_log + + def _get_matches(self, err, regex_line): + matches = [] + for line in err.split('\n'): + columns = line.split() + if len(columns) == 8: + for i in range(8): + match = re.fullmatch(regex_line[i], columns[i]) + if match: + matches.append(match) + if len(matches) == 8: + return matches + else: + matches = [] + return matches + + @pytest.mark.parametrize( + 'test_path', + TESTDATA_1, + ids=[ + 'single_v', + ] + ) + def test_single_v(self, capfd, out_path, test_path): + args = ['--outdir', out_path, '-T', test_path, '-v'] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + regex_line = [r'INFO', r'-', r'\d+/\d+', r'\S+', r'\S+', r'[A-Z]+', r'\(\w+', r'[\d.]+s\)'] + matches = self._get_matches(err, regex_line) + print(matches) + assert str(sys_exit.value) == '0' + assert len(matches) > 0 + + @pytest.mark.parametrize( + 'test_path', + TESTDATA_1, + ids=[ + 'double_v', + ] + ) + def test_double_v(self, capfd, out_path, test_path): + args = ['--outdir', out_path, '-T', test_path, '-vv'] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + regex_line = [r'INFO', r'-', r'\d+/\d+', r'\S+', r'\S+', r'[A-Z]+', r'\(\w+', r'[\d.]+s\)'] + matches = self._get_matches(err, regex_line) + booting_zephyr_regex = re.compile(r'^DEBUG\s+-\s+([^*]+)\*\*\*\s+Booting\s+Zephyr\s+OS\s+build.*$', re.MULTILINE) + info_debug_line_regex = r'^\s*(INFO|DEBUG)' + + assert str(sys_exit.value) == '0' + assert re.search(booting_zephyr_regex, err) is not None + assert re.search(info_debug_line_regex, err) is not None + assert len(matches) > 0 From 0bbc67e9d805853559776f767b92f3add0d412ba Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 8 Mar 2024 17:03:37 +0000 Subject: [PATCH 0454/2402] soc: nxp: imxrt: renable DCDC adjustment for RT11xx DCDC adjustment was enabled by default for RT11xx series before HWMv2 transition. Reenable it, as this is needed for some higher power applications (such as display output) Signed-off-by: Daniel DeGrasse --- soc/nxp/imxrt/imxrt11xx/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/soc/nxp/imxrt/imxrt11xx/Kconfig b/soc/nxp/imxrt/imxrt11xx/Kconfig index 064c28ea238..2f4fed978f9 100644 --- a/soc/nxp/imxrt/imxrt11xx/Kconfig +++ b/soc/nxp/imxrt/imxrt11xx/Kconfig @@ -70,6 +70,7 @@ config ADJUST_LDO bool "Adjust LDO setting" config ADJUST_DCDC + default y bool "Adjust internal DCDC output" endif # SOC_SERIES_IMXRT11XX From 88054a0d3de5e0cbac0dcb0ced845aecdbaf468f Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Fri, 8 Mar 2024 16:00:16 +0000 Subject: [PATCH 0455/2402] dts: arm: nxp: fix rt11xx pit warnings The pit had a few warnings about the format of the register address being uppser case and one of the reg index values were incorrect. Signed-off-by: Emilio Benavente --- dts/arm/nxp/nxp_rt11xx.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/dts/arm/nxp/nxp_rt11xx.dtsi b/dts/arm/nxp/nxp_rt11xx.dtsi index b4782ca8755..317c849e409 100644 --- a/dts/arm/nxp/nxp_rt11xx.dtsi +++ b/dts/arm/nxp/nxp_rt11xx.dtsi @@ -1127,9 +1127,9 @@ status = "disabled"; }; - pit1: pit@400D8000 { + pit1: pit@400d8000 { compatible = "nxp,pit"; - reg = <0x400D8000 0x4000>; + reg = <0x400d8000 0x4000>; clocks = <&ccm IMX_CCM_PIT_CLK 0x0 0>; interrupts = <155 0>; max-load-value = <0xffffffff>; @@ -1162,9 +1162,9 @@ }; }; - pit2: pit@40CB0000 { + pit2: pit@40cb0000 { compatible = "nxp,pit"; - reg = <0x40CB0000 0x4000>; + reg = <0x40cb0000 0x4000>; clocks = <&ccm IMX_CCM_PIT1_CLK 0x0 0>; interrupts = <156 0>; max-load-value = <0xffffffff>; @@ -1189,7 +1189,7 @@ }; pit2_channel3: pit2_channel@3 { compatible = "nxp,pit-channel"; - reg = <2>; + reg = <3>; status = "disabled"; }; }; From 07d1355590fa5d23b7408a3ad1395737b67d725d Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 8 Mar 2024 12:56:12 +0800 Subject: [PATCH 0456/2402] dts: lpcxpresso55s69_lpc55s69_cpu0_ns: add adc0 pinmux add the mising adc0 pinmux for lpcxpresso55s69_lpc55s69_cpu0_ns Signed-off-by: Hake Huang --- boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts index cc2e41e0815..c68006a123f 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts @@ -95,6 +95,8 @@ &adc0 { status = "okay"; + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; }; &dma0 { From b6240133351038c1514598a4236581b42cd436c4 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 8 Mar 2024 12:57:21 +0800 Subject: [PATCH 0457/2402] tests: tests/drivers/adc/adc_api: change the overlay naming to HWV2 update overlay names fixing: #69945 Signed-off-by: Hake Huang --- ...so55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 ...o55s69_ns.overlay => lpcxpresso55s69_lpc55s69_cpu0_ns.overlay} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename tests/drivers/adc/adc_api/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{lpcxpresso55s69_ns.overlay => lpcxpresso55s69_lpc55s69_cpu0_ns.overlay} (100%) diff --git a/tests/drivers/adc/adc_api/boards/lpcxpresso55s69_cpu0.overlay b/tests/drivers/adc/adc_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/lpcxpresso55s69_cpu0.overlay rename to tests/drivers/adc/adc_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/tests/drivers/adc/adc_api/boards/lpcxpresso55s69_ns.overlay b/tests/drivers/adc/adc_api/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/lpcxpresso55s69_ns.overlay rename to tests/drivers/adc/adc_api/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay From e91860d8c7b76cdca51ecf764a3ae9d3d93595cc Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Thu, 7 Mar 2024 16:46:33 +0100 Subject: [PATCH 0458/2402] drivers: adc: stm32: disable dma before calibration For some STM32 series, DMA has to be disabled before starting ADC calibration. Signed-off-by: Guillaume Gautier --- drivers/adc/adc_stm32.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index 8213310ee7b..010512fc533 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -547,6 +547,23 @@ static int adc_stm32_calibrate(const struct device *dev) ADC_TypeDef *adc = config->base; int err; +#if defined(CONFIG_ADC_STM32_DMA) +#if defined(CONFIG_SOC_SERIES_STM32C0X) || \ + defined(CONFIG_SOC_SERIES_STM32F0X) || \ + defined(CONFIG_SOC_SERIES_STM32G0X) || \ + defined(CONFIG_SOC_SERIES_STM32L0X) || \ + defined(CONFIG_SOC_SERIES_STM32WBAX) || \ + defined(CONFIG_SOC_SERIES_STM32WLX) + /* Make sure DMA is disabled before starting calibration */ + LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_NONE); +#elif defined(CONFIG_SOC_SERIES_STM32U5X) + if (adc == ADC4) { + /* Make sure DMA is disabled before starting calibration */ + LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_NONE); + } +#endif /* CONFIG_SOC_SERIES_* */ +#endif /* CONFIG_ADC_STM32_DMA */ + #if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) adc_stm32_disable(adc); adc_stm32_calibration_start(dev); From 3e6034ed43d20fe79f65611b2655387855972988 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Tue, 20 Feb 2024 12:11:33 +0100 Subject: [PATCH 0459/2402] dts: bindings: can: transciever: allow specififying minumum bitrate Some CAN transceivers have a lower limit on their supported bitrate. Add an optional "min-bitrate" for specifying this limit via devicetree. Signed-off-by: Henrik Brix Andersen --- dts/bindings/can/can-controller.yaml | 5 +++++ dts/bindings/phy/can-transceiver.yaml | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/dts/bindings/can/can-controller.yaml b/dts/bindings/can/can-controller.yaml index 6c5cbe822ae..c53d69e3041 100644 --- a/dts/bindings/can/can-controller.yaml +++ b/dts/bindings/can/can-controller.yaml @@ -46,6 +46,11 @@ child-binding: }; properties: + min-bitrate: + type: int + description: | + The minimum bitrate supported by the CAN transceiver in bits/s. + max-bitrate: type: int required: true diff --git a/dts/bindings/phy/can-transceiver.yaml b/dts/bindings/phy/can-transceiver.yaml index 428c386be8f..48145e19795 100644 --- a/dts/bindings/phy/can-transceiver.yaml +++ b/dts/bindings/phy/can-transceiver.yaml @@ -6,6 +6,11 @@ include: phy-controller.yaml properties: + min-bitrate: + type: int + description: | + The minimum bitrate supported by the CAN transceiver in bits/s. + max-bitrate: type: int required: true From 6c21ae41a969fb798db2b258b194e00e8c85807f Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Tue, 20 Feb 2024 12:14:10 +0100 Subject: [PATCH 0460/2402] boards: shields: mcp2515: dfrobot: specify minimum CAN bitrate The NXP TJA1050 supports bitrates from 60kbit/s up to 1Mbit/s. Signed-off-by: Henrik Brix Andersen --- boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay b/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay index 397fac2ef70..7670b02e173 100644 --- a/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay +++ b/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay @@ -19,6 +19,7 @@ sample-point = <875>; can-transceiver { + min-bitrate = <60000>; max-bitrate = <1000000>; }; }; From 653387446e2b1fe9f499b7836405a99f9950070c Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Tue, 20 Feb 2024 12:17:02 +0100 Subject: [PATCH 0461/2402] devicetree: can: add support for getting CAN transceiver minimum bitrate Add support for getting the minimum supported bitrate of a CAN transceiver. Signed-off-by: Henrik Brix Andersen --- include/zephyr/devicetree/can.h | 66 ++++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/include/zephyr/devicetree/can.h b/include/zephyr/devicetree/can.h index 60e27e73945..a98a3ea7f0e 100644 --- a/include/zephyr/devicetree/can.h +++ b/include/zephyr/devicetree/can.h @@ -22,6 +22,60 @@ extern "C" { * @{ */ +/** + * @brief Get the minimum transceiver bitrate for a CAN controller + * + * The bitrate will be limited to the minimum bitrate supported by the CAN + * controller. If no CAN transceiver is present in the devicetree, the minimum + * bitrate will be that of the CAN controller. + * + * Example devicetree fragment: + * + * transceiver0: can-phy0 { + * compatible = "vnd,can-transceiver"; + * min-bitrate = <15000>; + * max-bitrate = <1000000>; + * #phy-cells = <0>; + * }; + * + * can0: can@... { + * compatible = "vnd,can-controller"; + * phys = <&transceiver0>; + * }; + * + * can1: can@... { + * compatible = "vnd,can-controller"; + * + * can-transceiver { + * min-bitrate = <25000>; + * max-bitrate = <2000000>; + * }; + * }; + * + * can2: can@... { + * compatible = "vnd,can-controller"; + * + * can-transceiver { + * max-bitrate = <2000000>; + * }; + * }; + * + * Example usage: + * + * DT_CAN_TRANSCEIVER_MIN_BITRATE(DT_NODELABEL(can0), 10000) // 15000 + * DT_CAN_TRANSCEIVER_MIN_BITRATE(DT_NODELABEL(can1), 0) // 250000 + * DT_CAN_TRANSCEIVER_MIN_BITRATE(DT_NODELABEL(can1), 50000) // 500000 + * DT_CAN_TRANSCEIVER_MIN_BITRATE(DT_NODELABEL(can2), 0) // 0 + * + * @param node_id node identifier + * @param min minimum bitrate supported by the CAN controller + * @return the minimum bitrate supported by the CAN controller/transceiver combination + */ +#define DT_CAN_TRANSCEIVER_MIN_BITRATE(node_id, min) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, phys), \ + MAX(DT_PROP_OR(DT_PHANDLE(node_id, phys), min_bitrate, 0), min), \ + MAX(DT_PROP_OR(DT_CHILD(node_id, can_transceiver), min_bitrate, min), min)) + /** * @brief Get the maximum transceiver bitrate for a CAN controller * @@ -60,11 +114,21 @@ extern "C" { * @param max maximum bitrate supported by the CAN controller * @return the maximum bitrate supported by the CAN controller/transceiver combination */ -#define DT_CAN_TRANSCEIVER_MAX_BITRATE(node_id, max) \ +#define DT_CAN_TRANSCEIVER_MAX_BITRATE(node_id, max) \ COND_CODE_1(DT_NODE_HAS_PROP(node_id, phys), \ MIN(DT_PROP(DT_PHANDLE(node_id, phys), max_bitrate), max), \ MIN(DT_PROP_OR(DT_CHILD(node_id, can_transceiver), max_bitrate, max), max)) +/** + * @brief Get the minimum transceiver bitrate for a DT_DRV_COMPAT CAN controller + * @param inst DT_DRV_COMPAT instance number + * @param min minimum bitrate supported by the CAN controller + * @return the minimum bitrate supported by the CAN controller/transceiver combination + * @see DT_CAN_TRANSCEIVER_MIN_BITRATE() + */ +#define DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(inst, min) \ + DT_CAN_TRANSCEIVER_MIN_BITRATE(DT_DRV_INST(inst), min) + /** * @brief Get the maximum transceiver bitrate for a DT_DRV_COMPAT CAN controller * @param inst DT_DRV_COMPAT instance number From 57c015d0171ff86bde54a6858723ca05bc9492e4 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Tue, 20 Feb 2024 12:58:45 +0100 Subject: [PATCH 0462/2402] tests: lib: devicetree: api: add tests for minimum CAN phy bitrate Add tests for DT_CAN_TRANSCEIVER_MIN_BITRATE() and DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(). Signed-off-by: Henrik Brix Andersen --- tests/lib/devicetree/api/app.overlay | 30 ++++++++++++++++++ tests/lib/devicetree/api/src/main.c | 46 ++++++++++++++++++++++++++-- 2 files changed, 74 insertions(+), 2 deletions(-) diff --git a/tests/lib/devicetree/api/app.overlay b/tests/lib/devicetree/api/app.overlay index 643bb0977cb..03f14f50389 100644 --- a/tests/lib/devicetree/api/app.overlay +++ b/tests/lib/devicetree/api/app.overlay @@ -514,9 +514,17 @@ compatible = "vnd,can-transceiver"; status = "okay"; #phy-cells = <0>; + min-bitrate = <10000>; max-bitrate = <5000000>; }; + test_transceiver1: can-phy1 { + compatible = "vnd,can-transceiver"; + status = "okay"; + #phy-cells = <0>; + max-bitrate = <1000000>; + }; + test_can0: can@55553333 { compatible = "vnd,can-controller"; reg = < 0x55553333 0x1000 >; @@ -534,10 +542,32 @@ status = "okay"; can-transceiver { + min-bitrate = <50000>; max-bitrate = <2000000>; }; }; + test_can2: can@55555555 { + compatible = "vnd,can-controller"; + reg = < 0x55555555 0x1000 >; + sample-point = <875>; + bus-speed = <125000>; + status = "okay"; + + can-transceiver { + max-bitrate = <1000000>; + }; + }; + + test_can3: can@55557777 { + compatible = "vnd,can-controller"; + reg = < 0x55556666 0x1000 >; + sample-point = <875>; + bus-speed = <125000>; + status = "okay"; + phys = <&test_transceiver1>; + }; + /* there should only be one of these */ test_children: test-children { compatible = "vnd,child-bindings"; diff --git a/tests/lib/devicetree/api/src/main.c b/tests/lib/devicetree/api/src/main.c index 9e35294f7b4..52197bcfb74 100644 --- a/tests/lib/devicetree/api/src/main.c +++ b/tests/lib/devicetree/api/src/main.c @@ -70,6 +70,8 @@ #define TEST_CAN_CTRL_0 DT_NODELABEL(test_can0) #define TEST_CAN_CTRL_1 DT_NODELABEL(test_can1) +#define TEST_CAN_CTRL_2 DT_NODELABEL(test_can2) +#define TEST_CAN_CTRL_3 DT_NODELABEL(test_can3) #define TEST_DMA_CTLR_1 DT_NODELABEL(test_dma1) #define TEST_DMA_CTLR_2 DT_NODELABEL(test_dma2) @@ -1326,21 +1328,61 @@ ZTEST(devicetree_api, test_pwms) #define DT_DRV_COMPAT vnd_can_controller ZTEST(devicetree_api, test_can) { + /* DT_CAN_TRANSCEIVER_MIN_BITRATE */ + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_0, 0), 10000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_0, 10000), 10000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_0, 20000), 20000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_1, 0), 50000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_1, 50000), 50000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_1, 100000), 100000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_2, 0), 0, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_2, 10000), 10000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_2, 20000), 20000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_3, 0), 0, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_3, 30000), 30000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MIN_BITRATE(TEST_CAN_CTRL_3, 40000), 40000, ""); + + /* DT_INST_CAN_TRANSCEIVER_MIN_BITRATE */ + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(0, 0), 10000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(0, 10000), 10000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(0, 20000), 20000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(1, 0), 50000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(1, 50000), 50000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(1, 100000), 100000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(2, 0), 0, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(2, 10000), 10000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(2, 20000), 20000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(3, 0), 0, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(3, 30000), 30000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MIN_BITRATE(3, 40000), 40000, ""); + /* DT_CAN_TRANSCEIVER_MAX_BITRATE */ zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_0, 1000000), 1000000, ""); zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_0, 5000000), 5000000, ""); zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_0, 8000000), 5000000, ""); - zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_1, 1250000), 1250000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_1, 125000), 125000, ""); zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_1, 2000000), 2000000, ""); zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_1, 5000000), 2000000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_2, 125000), 125000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_2, 1000000), 1000000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_2, 5000000), 1000000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_3, 125000), 125000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_3, 1000000), 1000000, ""); + zassert_equal(DT_CAN_TRANSCEIVER_MAX_BITRATE(TEST_CAN_CTRL_3, 5000000), 1000000, ""); /* DT_INST_CAN_TRANSCEIVER_MAX_BITRATE */ zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(0, 1000000), 1000000, ""); zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(0, 5000000), 5000000, ""); zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(0, 8000000), 5000000, ""); - zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(1, 1250000), 1250000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(1, 125000), 125000, ""); zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(1, 2000000), 2000000, ""); zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(1, 5000000), 2000000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(2, 125000), 125000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(2, 1000000), 1000000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(2, 5000000), 1000000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(3, 125000), 125000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(3, 1000000), 1000000, ""); + zassert_equal(DT_INST_CAN_TRANSCEIVER_MAX_BITRATE(3, 5000000), 1000000, ""); } ZTEST(devicetree_api, test_macro_names) From 6d35ec718fcb17346db92195fb208d9b136c1f4b Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 26 Feb 2024 22:34:59 +0100 Subject: [PATCH 0463/2402] drivers: can: add support for specifying minimum supported CAN bitrate Add support for specifying the minimum bitrate supported by a CAN controller in CAN_DT_DRIVER_CONFIG_GET() and CAN_DT_DRIVER_CONFIG_INST_GET(). Signed-off-by: Henrik Brix Andersen --- drivers/can/can_fake.c | 2 +- drivers/can/can_loopback.c | 2 +- drivers/can/can_mcp2515.c | 2 +- drivers/can/can_mcp251xfd.c | 2 +- drivers/can/can_mcux_flexcan.c | 2 +- drivers/can/can_native_linux.c | 2 +- drivers/can/can_nxp_s32_canxl.c | 2 +- drivers/can/can_rcar.c | 2 +- drivers/can/can_stm32_bxcan.c | 2 +- drivers/can/can_xmc4xxx.c | 2 +- include/zephyr/drivers/can.h | 11 ++++++++--- include/zephyr/drivers/can/can_mcan.h | 4 ++-- include/zephyr/drivers/can/can_sja1000.h | 2 +- 13 files changed, 21 insertions(+), 16 deletions(-) diff --git a/drivers/can/can_fake.c b/drivers/can/can_fake.c index 9da4ad80b23..7725ebfa13b 100644 --- a/drivers/can/can_fake.c +++ b/drivers/can/can_fake.c @@ -144,7 +144,7 @@ static const struct can_driver_api fake_can_driver_api = { #define FAKE_CAN_INIT(inst) \ static const struct fake_can_config fake_can_config_##inst = { \ - .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 0U), \ + .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 0, 0), \ }; \ \ static struct fake_can_data fake_can_data_##inst; \ diff --git a/drivers/can/can_loopback.c b/drivers/can/can_loopback.c index dcfb2a6cce8..5304c801ea4 100644 --- a/drivers/can/can_loopback.c +++ b/drivers/can/can_loopback.c @@ -440,7 +440,7 @@ static int can_loopback_init(const struct device *dev) #define CAN_LOOPBACK_INIT(inst) \ static const struct can_loopback_config can_loopback_config_##inst = { \ - .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 0U), \ + .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 0, 0), \ }; \ \ static struct can_loopback_data can_loopback_data_##inst; \ diff --git a/drivers/can/can_mcp2515.c b/drivers/can/can_mcp2515.c index 692015cdff3..283bd325262 100644 --- a/drivers/can/can_mcp2515.c +++ b/drivers/can/can_mcp2515.c @@ -1008,7 +1008,7 @@ static int mcp2515_init(const struct device *dev) }; \ \ static const struct mcp2515_config mcp2515_config_##inst = { \ - .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 1000000), \ + .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 0, 1000000), \ .bus = SPI_DT_SPEC_INST_GET(inst, SPI_WORD_SET(8), 0), \ .int_gpio = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \ .int_thread_stack_size = CONFIG_CAN_MCP2515_INT_THREAD_STACK_SIZE, \ diff --git a/drivers/can/can_mcp251xfd.c b/drivers/can/can_mcp251xfd.c index 04ee18bba2a..24f66f4eea6 100644 --- a/drivers/can/can_mcp251xfd.c +++ b/drivers/can/can_mcp251xfd.c @@ -1681,7 +1681,7 @@ static const struct can_driver_api mcp251xfd_api_funcs = { .int_thread_stack = mcp251xfd_int_stack_##inst, \ }; \ static const struct mcp251xfd_config mcp251xfd_config_##inst = { \ - .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 8000000), \ + .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 0, 8000000), \ .bus = SPI_DT_SPEC_INST_GET(inst, SPI_WORD_SET(8), 0), \ .int_gpio_dt = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \ \ diff --git a/drivers/can/can_mcux_flexcan.c b/drivers/can/can_mcux_flexcan.c index 7a1e5dde4e3..38642ca3d99 100644 --- a/drivers/can/can_mcux_flexcan.c +++ b/drivers/can/can_mcux_flexcan.c @@ -1400,7 +1400,7 @@ static const struct can_driver_api mcux_flexcan_fd_driver_api = { static void mcux_flexcan_irq_disable_##id(void); \ \ static const struct mcux_flexcan_config mcux_flexcan_config_##id = { \ - .common = CAN_DT_DRIVER_CONFIG_INST_GET(id, FLEXCAN_MAX_BITRATE(id)), \ + .common = CAN_DT_DRIVER_CONFIG_INST_GET(id, 0, FLEXCAN_MAX_BITRATE(id)), \ .base = (CAN_Type *)DT_INST_REG_ADDR(id), \ .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \ .clock_subsys = (clock_control_subsys_t) \ diff --git a/drivers/can/can_native_linux.c b/drivers/can/can_native_linux.c index 9356588a411..fb3ff59caa9 100644 --- a/drivers/can/can_native_linux.c +++ b/drivers/can/can_native_linux.c @@ -471,7 +471,7 @@ static int can_native_linux_init(const struct device *dev) #define CAN_NATIVE_LINUX_INIT(inst) \ \ static const struct can_native_linux_config can_native_linux_cfg_##inst = { \ - .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 0), \ + .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 0, 0), \ .if_name = DT_INST_PROP(inst, host_interface), \ }; \ \ diff --git a/drivers/can/can_nxp_s32_canxl.c b/drivers/can/can_nxp_s32_canxl.c index 75df1c65858..a5683750696 100644 --- a/drivers/can/can_nxp_s32_canxl.c +++ b/drivers/can/can_nxp_s32_canxl.c @@ -1151,7 +1151,7 @@ static const struct can_driver_api can_nxp_s32_driver_api = { (Canexcel_Ip_RxFifoFilterID_ADDR *)&rx_fifo_filter##n,))\ }; \ static struct can_nxp_s32_config can_nxp_s32_config_##n = { \ - .common = CAN_DT_DRIVER_CONFIG_INST_GET(n, CAN_NXP_S32_MAX_BITRATE), \ + .common = CAN_DT_DRIVER_CONFIG_INST_GET(n, 0, CAN_NXP_S32_MAX_BITRATE), \ .base_sic = (CANXL_SIC_Type *)DT_INST_REG_ADDR_BY_NAME(n, sic), \ IF_ENABLED(CONFIG_CAN_NXP_S32_RX_FIFO, \ (.base_rx_fifo = (CANXL_RXFIFO_Type *) \ diff --git a/drivers/can/can_rcar.c b/drivers/can/can_rcar.c index b389b638a3b..eacebb9222b 100644 --- a/drivers/can/can_rcar.c +++ b/drivers/can/can_rcar.c @@ -1190,7 +1190,7 @@ static const struct can_driver_api can_rcar_driver_api = { PINCTRL_DT_INST_DEFINE(n); \ static void can_rcar_##n##_init(const struct device *dev); \ static const struct can_rcar_cfg can_rcar_cfg_##n = { \ - .common = CAN_DT_DRIVER_CONFIG_INST_GET(n, 1000000), \ + .common = CAN_DT_DRIVER_CONFIG_INST_GET(n, 0, 1000000), \ .reg_addr = DT_INST_REG_ADDR(n), \ .reg_size = DT_INST_REG_SIZE(n), \ .init_func = can_rcar_##n##_init, \ diff --git a/drivers/can/can_stm32_bxcan.c b/drivers/can/can_stm32_bxcan.c index 212d7622d9c..3f8060944e9 100644 --- a/drivers/can/can_stm32_bxcan.c +++ b/drivers/can/can_stm32_bxcan.c @@ -1139,7 +1139,7 @@ static void config_can_##inst##_irq(CAN_TypeDef *can) \ #define CAN_STM32_CONFIG_INST(inst) \ PINCTRL_DT_INST_DEFINE(inst); \ static const struct can_stm32_config can_stm32_cfg_##inst = { \ - .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 1000000), \ + .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 0, 1000000), \ .can = (CAN_TypeDef *)DT_INST_REG_ADDR(inst), \ .master_can = (CAN_TypeDef *)DT_INST_PROP_OR(inst, \ master_can_reg, DT_INST_REG_ADDR(inst)), \ diff --git a/drivers/can/can_xmc4xxx.c b/drivers/can/can_xmc4xxx.c index 3dc0bb9380c..cde7cf0654d 100644 --- a/drivers/can/can_xmc4xxx.c +++ b/drivers/can/can_xmc4xxx.c @@ -925,7 +925,7 @@ static const struct can_driver_api can_xmc4xxx_api_funcs = { \ static struct can_xmc4xxx_data can_xmc4xxx_data_##inst; \ static const struct can_xmc4xxx_config can_xmc4xxx_config_##inst = { \ - .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 1000000), \ + .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 0, 1000000), \ .can = (CAN_NODE_TypeDef *)DT_INST_REG_ADDR(inst), \ .clock_div8 = DT_INST_PROP(inst, clock_div8), \ .irq_config_func = can_xmc4xxx_irq_config_##inst, \ diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index 62e1047f073..4653db11846 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -329,6 +329,8 @@ typedef void (*can_state_change_callback_t)(const struct device *dev, struct can_driver_config { /** Pointer to the device structure for the associated CAN transceiver device or NULL. */ const struct device *phy; + /** The minimum bitrate supported by the CAN controller/transceiver combination. */ + uint32_t min_bitrate; /** The maximum bitrate supported by the CAN controller/transceiver combination. */ uint32_t max_bitrate; /** Initial CAN classic/CAN FD arbitration phase bitrate. */ @@ -347,11 +349,13 @@ struct can_driver_config { * @brief Static initializer for @p can_driver_config struct * * @param node_id Devicetree node identifier + * @param _min_bitrate minimum bitrate supported by the CAN controller * @param _max_bitrate maximum bitrate supported by the CAN controller */ -#define CAN_DT_DRIVER_CONFIG_GET(node_id, _max_bitrate) \ +#define CAN_DT_DRIVER_CONFIG_GET(node_id, _min_bitrate, _max_bitrate) \ { \ .phy = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(node_id, phys)), \ + .min_bitrate = DT_CAN_TRANSCEIVER_MIN_BITRATE(node_id, _min_bitrate), \ .max_bitrate = DT_CAN_TRANSCEIVER_MAX_BITRATE(node_id, _max_bitrate), \ .bus_speed = DT_PROP(node_id, bus_speed), \ .sample_point = DT_PROP_OR(node_id, sample_point, 0), \ @@ -364,11 +368,12 @@ struct can_driver_config { * @brief Static initializer for @p can_driver_config struct from DT_DRV_COMPAT instance * * @param inst DT_DRV_COMPAT instance number + * @param _min_bitrate minimum bitrate supported by the CAN controller * @param _max_bitrate maximum bitrate supported by the CAN controller * @see CAN_DT_DRIVER_CONFIG_GET() */ -#define CAN_DT_DRIVER_CONFIG_INST_GET(inst, _max_bitrate) \ - CAN_DT_DRIVER_CONFIG_GET(DT_DRV_INST(inst), _max_bitrate) +#define CAN_DT_DRIVER_CONFIG_INST_GET(inst, _min_bitrate, _max_bitrate) \ + CAN_DT_DRIVER_CONFIG_GET(DT_DRV_INST(inst), _min_bitrate, _max_bitrate) /** * @brief Common CAN controller driver data. diff --git a/include/zephyr/drivers/can/can_mcan.h b/include/zephyr/drivers/can/can_mcan.h index ca7190412c2..8a4241aa760 100644 --- a/include/zephyr/drivers/can/can_mcan.h +++ b/include/zephyr/drivers/can/can_mcan.h @@ -1294,7 +1294,7 @@ struct can_mcan_config { #ifdef CONFIG_CAN_FD_MODE #define CAN_MCAN_DT_CONFIG_GET(node_id, _custom, _ops, _cbs) \ { \ - .common = CAN_DT_DRIVER_CONFIG_GET(node_id, 8000000), \ + .common = CAN_DT_DRIVER_CONFIG_GET(node_id, 0, 8000000), \ .ops = _ops, \ .callbacks = _cbs, \ .mram_elements = CAN_MCAN_DT_MRAM_ELEMENTS_GET(node_id), \ @@ -1306,7 +1306,7 @@ struct can_mcan_config { #else /* CONFIG_CAN_FD_MODE */ #define CAN_MCAN_DT_CONFIG_GET(node_id, _custom, _ops, _cbs) \ { \ - .common = CAN_DT_DRIVER_CONFIG_GET(node_id, 8000000), \ + .common = CAN_DT_DRIVER_CONFIG_GET(node_id, 0, 1000000), \ .ops = _ops, \ .callbacks = _cbs, \ .mram_elements = CAN_MCAN_DT_MRAM_ELEMENTS_GET(node_id), \ diff --git a/include/zephyr/drivers/can/can_sja1000.h b/include/zephyr/drivers/can/can_sja1000.h index de11d69031d..1d50f9b9a46 100644 --- a/include/zephyr/drivers/can/can_sja1000.h +++ b/include/zephyr/drivers/can/can_sja1000.h @@ -122,7 +122,7 @@ struct can_sja1000_config { */ #define CAN_SJA1000_DT_CONFIG_GET(node_id, _custom, _read_reg, _write_reg, _ocr, _cdr) \ { \ - .common = CAN_DT_DRIVER_CONFIG_GET(node_id, 1000000), \ + .common = CAN_DT_DRIVER_CONFIG_GET(node_id, 0, 1000000), \ .read_reg = _read_reg, \ .write_reg = _write_reg, \ .ocr = _ocr, \ From 621515ccf78f4fd598fd87a7a2e52187a9804ce7 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 26 Feb 2024 22:38:26 +0100 Subject: [PATCH 0464/2402] drivers: can: sja1000: allow front-ends to specify minimum bitrate Allow frontend drivers based on the SJA1000 backend to specify a minimum supported bitrate. The ESP32 TWAI supports bitrates from 25kbit/s to 1Mbit/s. Signed-off-by: Henrik Brix Andersen --- drivers/can/can_esp32_twai.c | 2 +- drivers/can/can_kvaser_pci.c | 2 +- include/zephyr/drivers/can/can_sja1000.h | 13 +++++++++---- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/can/can_esp32_twai.c b/drivers/can/can_esp32_twai.c index 0f7eec51955..aba78aeca74 100644 --- a/drivers/can/can_esp32_twai.c +++ b/drivers/can/can_esp32_twai.c @@ -280,7 +280,7 @@ const struct can_driver_api can_esp32_twai_driver_api = { can_esp32_twai_read_reg, can_esp32_twai_write_reg, \ CAN_SJA1000_OCR_OCMODE_BIPHASE, \ COND_CODE_0(IS_ENABLED(CONFIG_SOC_SERIES_ESP32), (0), \ - (CAN_ESP32_TWAI_DT_CDR_INST_GET(inst)))); \ + (CAN_ESP32_TWAI_DT_CDR_INST_GET(inst))), 25000); \ \ static struct can_sja1000_data can_sja1000_data_##inst = \ CAN_SJA1000_DATA_INITIALIZER(NULL); \ diff --git a/drivers/can/can_kvaser_pci.c b/drivers/can/can_kvaser_pci.c index a1490416076..002ee3bade4 100644 --- a/drivers/can/can_kvaser_pci.c +++ b/drivers/can/can_kvaser_pci.c @@ -168,7 +168,7 @@ const struct can_driver_api can_kvaser_pci_driver_api = { static const struct can_sja1000_config can_sja1000_config_##inst = \ CAN_SJA1000_DT_CONFIG_INST_GET(inst, &can_kvaser_pci_config_##inst, \ can_kvaser_pci_read_reg, can_kvaser_pci_write_reg, \ - CAN_KVASER_PCI_OCR, CAN_KVASER_PCI_CDR); \ + CAN_KVASER_PCI_OCR, CAN_KVASER_PCI_CDR, 0); \ \ static struct can_kvaser_pci_data can_kvaser_pci_data_##inst; \ \ diff --git a/include/zephyr/drivers/can/can_sja1000.h b/include/zephyr/drivers/can/can_sja1000.h index 1d50f9b9a46..fa9647bd9b5 100644 --- a/include/zephyr/drivers/can/can_sja1000.h +++ b/include/zephyr/drivers/can/can_sja1000.h @@ -119,10 +119,12 @@ struct can_sja1000_config { * @param _write_reg Driver frontend SJA100 register write function * @param _ocr Initial SJA1000 Output Control Register (OCR) value * @param _cdr Initial SJA1000 Clock Divider Register (CDR) value + * @param _min_bitrate minimum bitrate supported by the CAN controller */ -#define CAN_SJA1000_DT_CONFIG_GET(node_id, _custom, _read_reg, _write_reg, _ocr, _cdr) \ +#define CAN_SJA1000_DT_CONFIG_GET(node_id, _custom, _read_reg, _write_reg, _ocr, _cdr, \ + _min_bitrate) \ { \ - .common = CAN_DT_DRIVER_CONFIG_GET(node_id, 0, 1000000), \ + .common = CAN_DT_DRIVER_CONFIG_GET(node_id, _min_bitrate, 1000000), \ .read_reg = _read_reg, \ .write_reg = _write_reg, \ .ocr = _ocr, \ @@ -139,10 +141,13 @@ struct can_sja1000_config { * @param _write_reg Driver frontend SJA100 register write function * @param _ocr Initial SJA1000 Output Control Register (OCR) value * @param _cdr Initial SJA1000 Clock Divider Register (CDR) value + * @param _min_bitrate minimum bitrate supported by the CAN controller * @see CAN_SJA1000_DT_CONFIG_GET() */ -#define CAN_SJA1000_DT_CONFIG_INST_GET(inst, _custom, _read_reg, _write_reg, _ocr, _cdr) \ - CAN_SJA1000_DT_CONFIG_GET(DT_DRV_INST(inst), _custom, _read_reg, _write_reg, _ocr, _cdr) +#define CAN_SJA1000_DT_CONFIG_INST_GET(inst, _custom, _read_reg, _write_reg, _ocr, _cdr, \ + _min_bitrate) \ + CAN_SJA1000_DT_CONFIG_GET(DT_DRV_INST(inst), _custom, _read_reg, _write_reg, _ocr, _cdr, \ + _min_bitrate) /** * @brief SJA1000 driver internal RX filter structure. From c769da9e55325156393dc84abe39854aea341e0a Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 26 Feb 2024 22:40:31 +0100 Subject: [PATCH 0465/2402] drivers: can: add can_get_min_bitrate() API function Add a new CAN controller API function can_get_min_bitrate() for getting the minimum supported bitrate of a CAN controller/transceiver combination. Signed-off-by: Henrik Brix Andersen --- drivers/can/can_handlers.c | 10 ++++++++++ include/zephyr/drivers/can.h | 22 ++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/can/can_handlers.c b/drivers/can/can_handlers.c index a5b728ca297..a7f89d5837a 100644 --- a/drivers/can/can_handlers.c +++ b/drivers/can/can_handlers.c @@ -45,6 +45,16 @@ static inline int z_vrfy_can_get_core_clock(const struct device *dev, } #include +static inline int z_vrfy_can_get_min_bitrate(const struct device *dev, + uint32_t *min_bitrate) +{ + K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_CAN)); + K_OOPS(K_SYSCALL_MEMORY_WRITE(min_bitrate, sizeof(*min_bitrate))); + + return z_impl_can_get_min_bitrate(dev, min_bitrate); +} +#include + static inline int z_vrfy_can_get_max_bitrate(const struct device *dev, uint32_t *max_bitrate) { diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index 4653db11846..f621ee14b7a 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -811,6 +811,28 @@ static inline int z_impl_can_get_core_clock(const struct device *dev, uint32_t * return api->get_core_clock(dev, rate); } +/** + * @brief Get minimum supported bitrate + * + * Get the minimum supported bitrate for the CAN controller/transceiver combination. + * + * @param dev Pointer to the device structure for the driver instance. + * @param[out] min_bitrate Minimum supported bitrate in bits/s + * + * @retval -EIO General input/output error. + * @retval -ENOSYS If this function is not implemented by the driver. + */ +__syscall int can_get_min_bitrate(const struct device *dev, uint32_t *min_bitrate); + +static inline int z_impl_can_get_min_bitrate(const struct device *dev, uint32_t *min_bitrate) +{ + const struct can_driver_config *common = (const struct can_driver_config *)dev->config; + + *min_bitrate = common->min_bitrate; + + return 0; +} + /** * @brief Get maximum supported bitrate * From 810eaf1fb0ec1d23fcafa4562e3617c1c5f1ab37 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 26 Feb 2024 22:41:56 +0100 Subject: [PATCH 0466/2402] tests: drivers: can: api: add test for bitrate limits Add test for validating the CAN controller bitrate limits. Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/api/src/classic.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/tests/drivers/can/api/src/classic.c b/tests/drivers/can/api/src/classic.c index b34bd7d98fc..0edfda98015 100644 --- a/tests/drivers/can/api/src/classic.c +++ b/tests/drivers/can/api/src/classic.c @@ -475,6 +475,28 @@ ZTEST(can_classic, test_set_state_change_callback) can_set_state_change_callback(can_dev, NULL, NULL); } +/** + * @brief Test bitrate limits. + */ +ZTEST_USER(can_classic, test_bitrate_limits) +{ + uint32_t min = 0U; + uint32_t max = 0U; + int err; + + err = can_get_min_bitrate(can_dev, &min); + zassert_equal(err, 0, "failed to get min bitrate (err %d)", err); + + err = can_get_max_bitrate(can_dev, &max); + if (err == -ENOSYS) { + ztest_test_skip(); + } + + zassert_equal(err, 0, "failed to get max bitrate (err %d)", err); + + zassert_true(min <= max, "min bitrate must be lower or equal to max bitrate"); +} + /** * @brief Test setting a too high bitrate. */ From 019fde0437698d74fd8aed13c154aabeb2cf60ec Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 26 Feb 2024 22:43:16 +0100 Subject: [PATCH 0467/2402] drivers: can: take minimum supported bitrate into consideration Take the minimum supported bitrate into consideration when validating the bitrate. Signed-off-by: Henrik Brix Andersen --- drivers/can/can_common.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/can/can_common.c b/drivers/can/can_common.c index 21df3a3b55e..cb2e7c3ebcd 100644 --- a/drivers/can/can_common.c +++ b/drivers/can/can_common.c @@ -351,10 +351,13 @@ int z_impl_can_set_timing(const struct device *dev, int z_impl_can_set_bitrate(const struct device *dev, uint32_t bitrate) { struct can_timing timing = { 0 }; + uint32_t min_bitrate; uint32_t max_bitrate; uint16_t sample_pnt; int ret; + (void)can_get_min_bitrate(dev, &min_bitrate); + ret = can_get_max_bitrate(dev, &max_bitrate); if (ret == -ENOSYS) { /* Maximum bitrate unknown */ @@ -363,7 +366,7 @@ int z_impl_can_set_bitrate(const struct device *dev, uint32_t bitrate) return ret; } - if ((max_bitrate > 0) && (bitrate > max_bitrate)) { + if ((bitrate < min_bitrate) || (((max_bitrate > 0) && (bitrate > max_bitrate)))) { return -ENOTSUP; } @@ -404,10 +407,13 @@ int z_impl_can_set_timing_data(const struct device *dev, int z_impl_can_set_bitrate_data(const struct device *dev, uint32_t bitrate_data) { struct can_timing timing_data = { 0 }; + uint32_t min_bitrate; uint32_t max_bitrate; uint16_t sample_pnt; int ret; + (void)can_get_min_bitrate(dev, &min_bitrate); + ret = can_get_max_bitrate(dev, &max_bitrate); if (ret == -ENOSYS) { /* Maximum bitrate unknown */ @@ -416,7 +422,7 @@ int z_impl_can_set_bitrate_data(const struct device *dev, uint32_t bitrate_data) return ret; } - if ((max_bitrate > 0) && (bitrate_data > max_bitrate)) { + if ((bitrate_data < min_bitrate) || ((max_bitrate > 0) && (bitrate_data > max_bitrate))) { return -ENOTSUP; } From a0b4bf21b57c4cf9cac833104f4c2c789d5ff4bb Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 26 Feb 2024 22:44:13 +0100 Subject: [PATCH 0468/2402] tests: drivers: can: timing: report unsupported bitrates Enable testing of all bitrates for all drivers and report which bitrates are not supported by the CAN controller under test. Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/timing/src/main.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tests/drivers/can/timing/src/main.c b/tests/drivers/can/timing/src/main.c index 7f576de6c0b..3aa21ee848f 100644 --- a/tests/drivers/can/timing/src/main.c +++ b/tests/drivers/can/timing/src/main.c @@ -38,10 +38,7 @@ struct can_timing_test { */ static const struct can_timing_test can_timing_tests[] = { /** Standard bitrates. */ -#ifndef CONFIG_CAN_ESP32_TWAI - /* ESP32 TWAI does not support bitrates below 25kbit/s */ { 20000, 875, false }, -#endif /* CONFIG_CAN_ESP32_TWAI */ { 50000, 875, false }, { 125000, 875, false }, { 250000, 875, false }, @@ -186,6 +183,8 @@ static void test_timing_values(const struct device *dev, const struct can_timing if (test->invalid) { zassert_equal(sp_err, -EINVAL, "err %d, expected -EINVAL", sp_err); printk("OK\n"); + } else if (sp_err == -ENOTSUP) { + printk("bitrate not supported\n"); } else { zassert_true(sp_err >= 0, "unknown error %d", sp_err); zassert_true(sp_err <= SAMPLE_POINT_MARGIN, "sample point error %d too large", From 8dd03c63d6ecaea68b664591577570a94a765300 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 4 Mar 2024 10:32:39 +0100 Subject: [PATCH 0469/2402] doc: releases: release-notes: 3.7: support minimum suported CAN bitrates Add release notes related to the added support for minimum supported CAN transceiver/controller bitrates. Signed-off-by: Henrik Brix Andersen --- doc/releases/release-notes-3.7.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index ac32db3e9b3..ddbf8a3e98c 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -77,6 +77,16 @@ Drivers and Sensors start-of-frame (SOF) synchronization has taken place, leading to bus errors. * Extended support for automatic sample point location to also cover :c:func:`can_calc_timing` and :c:func:`can_calc_timing_data`. + * Added optional ``min-bitrate`` devicetree property for CAN transceivers. + * Added devicetree macros :c:macro:`DT_CAN_TRANSCEIVER_MIN_BITRATE` and + :c:macro:`DT_INST_CAN_TRANSCEIVER_MIN_BITRATE` for getting the minimum supported bitrate of a CAN + transceiver. + * Added support for specifying the minimum bitrate supported by a CAN controller in the internal + ``CAN_DT_DRIVER_CONFIG_GET`` and ``CAN_DT_DRIVER_CONFIG_INST_GET`` macros. + * Added a new CAN controller API function :c:func:`can_get_min_bitrate` for getting the minimum + supported bitrate of a CAN controller/transceiver combination. + * Updated the CAN timing functions to take the minimum supported bitrate into consideration when + validating the bitrate. * Clock control From 42fa87d5a8dfc5e17ad42e70af74055ca9f5bf38 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 19 Feb 2024 13:30:00 +0100 Subject: [PATCH 0470/2402] soc: nxp: imx: imx8m: Align resource table to 64bit for i.MX 8M Running samples/subsys/ipc/openamp_rsc_table with some adjustments sometimes results in linux kernel panics. After experimenting it appears to be hit or miss depending on the resource table alignment. Explicitly aligning to 64bit (the native width), no more kernel panics were seen. Signed-off-by: Pieter De Gendt --- soc/nxp/imx/imx8m/m4_mini/linker.ld | 2 +- soc/nxp/imx/imx8m/m7/linker.ld | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/soc/nxp/imx/imx8m/m4_mini/linker.ld b/soc/nxp/imx/imx8m/m4_mini/linker.ld index b1a954f245a..7c0c33e59bf 100644 --- a/soc/nxp/imx/imx8m/m4_mini/linker.ld +++ b/soc/nxp/imx/imx8m/m4_mini/linker.ld @@ -9,7 +9,7 @@ SECTIONS { #ifdef CONFIG_OPENAMP_RSC_TABLE - SECTION_PROLOGUE(.resource_table,, SUBALIGN(4)) + SECTION_PROLOGUE(.resource_table,, SUBALIGN(8)) { KEEP(*(.resource_table*)) } GROUP_LINK_IN(ROMABLE_REGION) diff --git a/soc/nxp/imx/imx8m/m7/linker.ld b/soc/nxp/imx/imx8m/m7/linker.ld index 0b4006dd732..790e9c03074 100644 --- a/soc/nxp/imx/imx8m/m7/linker.ld +++ b/soc/nxp/imx/imx8m/m7/linker.ld @@ -21,7 +21,7 @@ MEMORY SECTIONS { #ifdef CONFIG_OPENAMP_RSC_TABLE - SECTION_PROLOGUE(.resource_table,, SUBALIGN(4)) + SECTION_PROLOGUE(.resource_table,, SUBALIGN(8)) { KEEP(*(.resource_table*)) } GROUP_LINK_IN(ROMABLE_REGION) From 3c8bd58a06522113344a19f867eb42d1339e3a1a Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 30 Jan 2024 19:16:37 +0200 Subject: [PATCH 0471/2402] log: net: Add TCP support to syslog transmitter Allow user to configure the syslog net backend to use TCP instead of UDP. The syslog server address for TCP needs to have "tcp://" URI in front of the address, for example the tcp://192.0.2.2 server address would use TCP as a transport. If there is no URI, then UDP would be used by default. See the relevant RFC at https://www.rfc-editor.org/rfc/rfc6587 for details. Fixes #66728 Signed-off-by: Jukka Rissanen --- subsys/logging/backends/Kconfig.net | 12 +++-- subsys/logging/backends/log_backend_net.c | 53 +++++++++++++++++++---- 2 files changed, 53 insertions(+), 12 deletions(-) diff --git a/subsys/logging/backends/Kconfig.net b/subsys/logging/backends/Kconfig.net index 91de9074324..e9a47c83c84 100644 --- a/subsys/logging/backends/Kconfig.net +++ b/subsys/logging/backends/Kconfig.net @@ -5,12 +5,12 @@ # rsyslog message to be malformed. config LOG_BACKEND_NET bool "Networking backend" - depends on NETWORKING && NET_UDP && !LOG_MODE_IMMEDIATE + depends on NETWORKING && (NET_UDP || NET_TCP) && !LOG_MODE_IMMEDIATE select LOG_OUTPUT help Send syslog messages to network server. - See RFC 5424 (syslog protocol) and RFC 5426 (syslog over UDP) - specifications for details. + See RFC 5424 (syslog protocol) and RFC 5426 (syslog over UDP) and + RFC 6587 (syslog over TCP) specifications for details. if LOG_BACKEND_NET @@ -25,6 +25,12 @@ config LOG_BACKEND_NET_SERVER [2001:db8::1]:514 [2001:db8::2] 2001:db::42 + If you want to use TCP, add "tcp://" in front of the address + like this + tcp://192.0.2.1:514 + tcp://192.0.2.42 + tcp://[2001:db8::1]:514 + UDP is used by default if the URI is missing. config LOG_BACKEND_NET_MAX_BUF_SIZE int "Max syslog message size" diff --git a/subsys/logging/backends/log_backend_net.c b/subsys/logging/backends/log_backend_net.c index 7ec5844ce2e..f002314ac59 100644 --- a/subsys/logging/backends/log_backend_net.c +++ b/subsys/logging/backends/log_backend_net.c @@ -7,6 +7,7 @@ #include LOG_MODULE_REGISTER(log_backend_net, CONFIG_LOG_DEFAULT_LEVEL); +#include #include #include #include @@ -16,11 +17,7 @@ LOG_MODULE_REGISTER(log_backend_net, CONFIG_LOG_DEFAULT_LEVEL); /* Set this to 1 if you want to see what is being sent to server */ #define DEBUG_PRINTING 0 -#if DEBUG_PRINTING -#define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__) -#else -#define DBG(fmt, ...) -#endif +#define DBG(fmt, ...) IF_ENABLED(DEBUG_PRINTING, (printk(fmt, ##__VA_ARGS__))) #if defined(CONFIG_NET_IPV6) || CONFIG_NET_HOSTNAME_ENABLE #define MAX_HOSTNAME_LEN NET_IPV6_ADDR_LEN @@ -38,6 +35,7 @@ static uint32_t log_format_current = CONFIG_LOG_BACKEND_NET_OUTPUT_DEFAULT; static struct log_backend_net_ctx { int sock; + bool is_tcp; } ctx = { .sock = -1, }; @@ -46,12 +44,37 @@ static int line_out(uint8_t *data, size_t length, void *output_ctx) { struct log_backend_net_ctx *ctx = (struct log_backend_net_ctx *)output_ctx; int ret = -ENOMEM; + struct msghdr msg = { 0 }; + struct iovec io_vector[2]; + int pos = 0; if (ctx == NULL) { return length; } - ret = zsock_send(ctx->sock, data, length, ZSOCK_MSG_DONTWAIT); +#if defined(CONFIG_NET_TCP) + char len[sizeof("123456789")]; + + if (ctx->is_tcp) { + (void)snprintk(len, sizeof(len), "%zu ", length); + io_vector[pos].iov_base = (void *)len; + io_vector[pos].iov_len = strlen(len); + pos++; + } +#else + if (ctx->is_tcp) { + return -ENOTSUP; + } +#endif + + io_vector[pos].iov_base = (void *)data; + io_vector[pos].iov_len = length; + pos++; + + msg.msg_iov = io_vector; + msg.msg_iovlen = pos; + + ret = zsock_sendmsg(ctx->sock, &msg, ctx->is_tcp ? 0 : ZSOCK_MSG_DONTWAIT); if (ret < 0) { goto fail; } @@ -69,7 +92,7 @@ static int do_net_init(struct log_backend_net_ctx *ctx) struct sockaddr_in6 local_addr6 = {0}; struct sockaddr_in local_addr4 = {0}; socklen_t server_addr_len; - int ret; + int ret, proto = IPPROTO_UDP, type = SOCK_DGRAM; if (IS_ENABLED(CONFIG_NET_IPV4) && server_addr.sa_family == AF_INET) { local_addr = (struct sockaddr *)&local_addr4; @@ -90,7 +113,12 @@ static int do_net_init(struct log_backend_net_ctx *ctx) local_addr->sa_family = server_addr.sa_family; - ret = zsock_socket(server_addr.sa_family, SOCK_DGRAM, IPPROTO_UDP); + if (ctx->is_tcp) { + proto = IPPROTO_TCP; + type = SOCK_STREAM; + } + + ret = zsock_socket(server_addr.sa_family, type, proto); if (ret < 0) { ret = -errno; DBG("Cannot get socket (%d)\n", ret); @@ -283,8 +311,15 @@ static void init_net(struct log_backend const *const backend) ARG_UNUSED(backend); if (strlen(CONFIG_LOG_BACKEND_NET_SERVER) != 0) { - bool ret = log_backend_net_set_addr(CONFIG_LOG_BACKEND_NET_SERVER); + const char *server = CONFIG_LOG_BACKEND_NET_SERVER; + bool ret; + + if (memcmp(server, "tcp://", sizeof("tcp://") - 1) == 0) { + server += sizeof("tcp://") - 1; + ctx.is_tcp = true; + } + ret = log_backend_net_set_addr(server); if (!ret) { return; } From d5e55d25957f48ccaa18131e93ff85967745f2ea Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 31 Jan 2024 10:55:11 +0200 Subject: [PATCH 0472/2402] log: net: Depend on full featured libc instead of just newlibc For time printout, depend on full featured libc like picolibc instead of just newlibc. Signed-off-by: Jukka Rissanen --- subsys/logging/log_output.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/logging/log_output.c b/subsys/logging/log_output.c index 519c0248ff2..adbda7bfcb2 100644 --- a/subsys/logging/log_output.c +++ b/subsys/logging/log_output.c @@ -255,7 +255,7 @@ static int timestamp_print(const struct log_output *output, length = log_custom_timestamp_print(output, timestamp, print_formatted); } else if (IS_ENABLED(CONFIG_LOG_BACKEND_NET) && flags & LOG_OUTPUT_FLAG_FORMAT_SYSLOG) { -#if defined(CONFIG_NEWLIB_LIBC) +#if defined(CONFIG_REQUIRES_FULL_LIBC) char time_str[sizeof("1970-01-01T00:00:00")]; struct tm *tm; time_t time; From 068d23ab781592abc5b9aa498d094123ae4a8d07 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 31 Jan 2024 14:13:20 +0200 Subject: [PATCH 0473/2402] log: net: Add structured logging support to syslog Add structured logging support to syslog backend. This means that meta data can be included to logging output. Signed-off-by: Jukka Rissanen --- subsys/logging/backends/Kconfig.net | 64 ++++++++ subsys/logging/backends/log_backend_net.c | 4 +- subsys/logging/log_output.c | 171 +++++++++++++++++++++- 3 files changed, 233 insertions(+), 6 deletions(-) diff --git a/subsys/logging/backends/Kconfig.net b/subsys/logging/backends/Kconfig.net index e9a47c83c84..5c91b68b166 100644 --- a/subsys/logging/backends/Kconfig.net +++ b/subsys/logging/backends/Kconfig.net @@ -14,6 +14,70 @@ config LOG_BACKEND_NET if LOG_BACKEND_NET +config LOG_BACKEND_NET_RFC5424_STRUCTURED_DATA + bool "Print structured data according to RFC 5424" + help + Print additional structured data as described in + RFC 5424 chapter 6.3. Note that this might increase the + length of the syslog message a lot. + +config LOG_BACKEND_NET_RFC5424_SDATA_TZKNOWN + bool "RFC 5424 chapter 7.1.1 tzKnown field" + depends on LOG_BACKEND_NET_RFC5424_STRUCTURED_DATA + help + The tzKnown parameter indicates whether the originator knows its time zone. + See RFC 5424 chapter 7.1 for details. + +config LOG_BACKEND_NET_RFC5424_SDATA_ISSYNCED + bool "RFC 5424 chapter 7.1.2 isSynced field" + depends on LOG_BACKEND_NET_RFC5424_STRUCTURED_DATA + help + The isSynced parameter indicates whether the originator is + synchronized to a reliable external time source, e.g., via NTP. + See RFC 5424 chapter 7.1 for details. + +config LOG_BACKEND_NET_RFC5424_SDATA_SOFTWARE + bool "RFC 5424 chapter 7.2.3 software description field" + depends on LOG_BACKEND_NET_RFC5424_STRUCTURED_DATA + help + Software description parameter uniquely identifies the software that + generated the message. + See RFC 5424 chapter 7.2 for details. + +config LOG_BACKEND_NET_RFC5424_SDATA_SOFTWARE_VALUE + string "RFC 5424 chapter 7.2.3 software field value" + default "zephyr" + depends on LOG_BACKEND_NET_RFC5424_SDATA_SOFTWARE + help + User defined value for the software field. + See RFC 5424 chapter 7.2.3 for details. + +config LOG_BACKEND_NET_RFC5424_SDATA_SOFTWARE_VERSION + bool "RFC 5424 chapter 7.2.4 software version field" + depends on LOG_BACKEND_NET_RFC5424_STRUCTURED_DATA + help + Software version parameter uniquely identifies the software that + generated the message. + See RFC 5424 chapter 7.2.4 for details. + +config LOG_BACKEND_NET_RFC5424_SDATA_SEQID + bool "RFC 5424 chapter 7.3.1 sequence id field" + depends on LOG_BACKEND_NET_RFC5424_STRUCTURED_DATA + help + Sequence id parameter tracks the sequence in which the + originator submits messages to the syslog transport for sending. + See RFC 5424 chapter 7.3.1 for details. + +config LOG_BACKEND_NET_RFC5424_SDATA_UPTIME + bool "RFC 5424 chapter 7.3.2 system uptime field" + depends on LOG_BACKEND_NET_RFC5424_STRUCTURED_DATA + help + The system uptime parameter tracks the "time (in hundredths of a + second) since the network management portion of the system was last + re-initialized." For Zephyr this is currently interpreted as the + system uptime. + See RFC 5424 chapter 7.3.2 for details. + config LOG_BACKEND_NET_SERVER string "Syslog server IP address" help diff --git a/subsys/logging/backends/log_backend_net.c b/subsys/logging/backends/log_backend_net.c index f002314ac59..0f15770cd46 100644 --- a/subsys/logging/backends/log_backend_net.c +++ b/subsys/logging/backends/log_backend_net.c @@ -197,7 +197,9 @@ static int do_net_init(struct log_backend_net_ctx *ctx) static void process(const struct log_backend *const backend, union log_msg_generic *msg) { - uint32_t flags = LOG_OUTPUT_FLAG_FORMAT_SYSLOG | LOG_OUTPUT_FLAG_TIMESTAMP; + uint32_t flags = LOG_OUTPUT_FLAG_FORMAT_SYSLOG | + LOG_OUTPUT_FLAG_TIMESTAMP | + LOG_OUTPUT_FLAG_THREAD; if (panic_mode) { return; diff --git a/subsys/logging/log_output.c b/subsys/logging/log_output.c index adbda7bfcb2..dd62fb76aa1 100644 --- a/subsys/logging/log_output.c +++ b/subsys/logging/log_output.c @@ -435,6 +435,169 @@ static void log_msg_hexdump(const struct log_output *output, } while (len); } +#if defined(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_SEQID) +static int32_t get_sequence_id(void) +{ + static int32_t id; + + if (++id < 0) { + id = 1; + } + + return id; +} +#endif + +#if defined(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_TZKNOWN) +static bool is_tzknown(void) +{ + /* TODO: use proper implementation */ + return false; +} +#endif + +#if defined(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_ISSYNCED) +static bool is_synced(void) +{ + /* TODO: use proper implementation */ + return IS_ENABLED(CONFIG_SNTP); +} +#endif + +static int syslog_print(const struct log_output *output, + bool level_on, + bool func_on, + bool *thread_on, + const char *domain, + const char *source, + k_tid_t tid, + uint32_t level, + uint32_t length) +{ + uint32_t len = length; + + /* The syslog output format is: + * HOSTNAME SP APP-NAME SP PROCID SP MSGID SP STRUCTURED-DATA + */ + + /* First HOSTNAME */ + len += print_formatted(output, "%s ", + output->control_block->hostname ? + output->control_block->hostname : + "zephyr"); + + /* Then APP-NAME. We use the thread name here. It should not + * contain any space characters. + */ + if (*thread_on) { + if (IS_ENABLED(CONFIG_THREAD_NAME)) { + if (strstr(k_thread_name_get(tid), " ") != NULL) { + goto do_not_print_name; + } + + len += print_formatted(output, "%s ", + tid == NULL ? + "irq" : + k_thread_name_get(tid)); + } else { +do_not_print_name: + len += print_formatted(output, "%p ", tid); + } + + /* Do not print thread id in the message as it was already + * printed above. + */ + *thread_on = false; + } else { + /* No APP-NAME */ + len += print_formatted(output, "- "); + } + + if (!IS_ENABLED(CONFIG_LOG_BACKEND_NET_RFC5424_STRUCTURED_DATA)) { + /* No PROCID, MSGID or STRUCTURED-DATA */ + len += print_formatted(output, "- - - "); + + return len; + } + + +#if defined(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_SOFTWARE) || \ + defined(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_SOFTWARE_VERSION) +#define STRUCTURED_DATA_ORIGIN_START "[origin" +#define STRUCTURED_DATA_ORIGIN_SW " software=\"%s\"" +#define STRUCTURED_DATA_ORIGIN_SW_VERSION " swVersion=\"%u\"" +#define STRUCTURED_DATA_ORIGIN_END "]" +#define STRUCTURED_DATA_ORIGIN \ + STRUCTURED_DATA_ORIGIN_START \ + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_SOFTWARE, \ + (STRUCTURED_DATA_ORIGIN_SW), ("%s")) \ + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_SOFTWARE_VERSION,\ + (STRUCTURED_DATA_ORIGIN_SW_VERSION), ("%s")) \ + STRUCTURED_DATA_ORIGIN_END +#else +#define STRUCTURED_DATA_ORIGIN "%s%s" +#endif + +#if defined(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_SEQID) || \ + defined(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_UPTIME) +#define STRUCTURED_DATA_META_START "[meta" +#define STRUCTURED_DATA_META_SEQID " sequenceId=\"%d\"" +#define STRUCTURED_DATA_META_UPTIME " sysUpTime=\"%d\"" +#define STRUCTURED_DATA_META_END "]" +#define STRUCTURED_DATA_META \ + STRUCTURED_DATA_META_START \ + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_SEQID, \ + (STRUCTURED_DATA_META_SEQID), ("%s")) \ + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_UPTIME, \ + (STRUCTURED_DATA_META_UPTIME), ("%s")) \ + STRUCTURED_DATA_META_END +#else +#define STRUCTURED_DATA_META "%s%s" +#endif + +#if defined(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_TZKNOWN) || \ + defined(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_ISSYNCED) +#define STRUCTURED_DATA_TIMEQUALITY_START "[timeQuality" +#define STRUCTURED_DATA_TIMEQUALITY_TZKNOWN " tzKnown=\"%d\"" +#define STRUCTURED_DATA_TIMEQUALITY_ISSYNCED " isSynced=\"%d\"" +#define STRUCTURED_DATA_TIMEQUALITY_END "]" +#define STRUCTURED_DATA_TIMEQUALITY \ + STRUCTURED_DATA_TIMEQUALITY_START \ + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_TZKNOWN, \ + (STRUCTURED_DATA_TIMEQUALITY_TZKNOWN), ("%s")) \ + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_ISSYNCED, \ + (STRUCTURED_DATA_TIMEQUALITY_ISSYNCED), ("%s")) \ + STRUCTURED_DATA_TIMEQUALITY_END +#else +#define STRUCTURED_DATA_TIMEQUALITY "%s%s" +#endif + + /* No PROCID or MSGID, but there is structured data. + */ + len += print_formatted(output, + "- - " + STRUCTURED_DATA_META + STRUCTURED_DATA_ORIGIN + STRUCTURED_DATA_TIMEQUALITY, + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_SEQID, + (get_sequence_id()), ("")), + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_UPTIME, + /* in hundredths of a sec */ + (k_uptime_get_32() / 10), ("")), + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_SOFTWARE, + (CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_SOFTWARE_VALUE), + ("")), + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_SOFTWARE_VERSION, + (sys_kernel_version_get()), ("")), + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_TZKNOWN, + (is_tzknown()), ("")), + COND_CODE_1(CONFIG_LOG_BACKEND_NET_RFC5424_SDATA_ISSYNCED, + (is_synced()), ("")) + ); + + return len; +} + static uint32_t prefix_print(const struct log_output *output, uint32_t flags, bool func_on, @@ -466,6 +629,7 @@ static uint32_t prefix_print(const struct log_output *output, length += print_formatted( output, + /* VERSION */ "<%d>1 ", facility * 8 + level_to_rfc5424_severity(level)); @@ -481,11 +645,8 @@ static uint32_t prefix_print(const struct log_output *output, if (IS_ENABLED(CONFIG_LOG_BACKEND_NET) && flags & LOG_OUTPUT_FLAG_FORMAT_SYSLOG) { - length += print_formatted( - output, "%s - - - - ", - output->control_block->hostname ? - output->control_block->hostname : - "zephyr"); + length += syslog_print(output, level_on, func_on, &thread_on, domain, + source_off ? NULL : source, tid, level, length); } else { color_prefix(output, colors_on, level); } From 8c6e3a6d416f92495003e9d6ebf90613f9061f38 Mon Sep 17 00:00:00 2001 From: Bartosz Sokolski Date: Wed, 31 Jan 2024 13:41:12 +0100 Subject: [PATCH 0474/2402] drivers: i2s_nrfx: Fix divider calculation The driver wrongly handled perfect divider matches for clock setting Signed-off-by: Bartosz Sokolski --- drivers/i2s/i2s_nrfx.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/i2s/i2s_nrfx.c b/drivers/i2s/i2s_nrfx.c index eeb3ca911fb..4d4596313e7 100644 --- a/drivers/i2s/i2s_nrfx.c +++ b/drivers/i2s/i2s_nrfx.c @@ -94,7 +94,7 @@ static void find_suitable_clock(const struct i2s_nrfx_drv_cfg *drv_cfg, nrf_i2s_mck_t best_mck_cfg = 0; uint32_t best_mck = 0; - for (r = 0; r < ARRAY_SIZE(ratios); ++r) { + for (r = 0; (best_diff != 0) && (r < ARRAY_SIZE(ratios)); ++r) { /* Only multiples of the frame width can be used as ratios. */ if ((ratios[r].ratio_val % bits_per_frame) != 0) { continue; @@ -124,11 +124,6 @@ static void find_suitable_clock(const struct i2s_nrfx_drv_cfg *drv_cfg, best_mck_cfg = mck_factor * 4096; best_mck = actual_mck; best_r = r; - /* Stop if an exact match is found. */ - if (diff == 0) { - break; - } - best_diff = diff; } } else { @@ -151,7 +146,7 @@ static void find_suitable_clock(const struct i2s_nrfx_drv_cfg *drv_cfg, { 125, NRF_I2S_MCK_32MDIV125 } }; - for (uint8_t d = 0; d < ARRAY_SIZE(dividers); ++d) { + for (uint8_t d = 0; (best_diff != 0) && (d < ARRAY_SIZE(dividers)); ++d) { uint32_t mck_freq = src_freq / dividers[d].divider_val; uint32_t lrck_freq = @@ -165,11 +160,6 @@ static void find_suitable_clock(const struct i2s_nrfx_drv_cfg *drv_cfg, best_mck_cfg = dividers[d].divider_enum; best_mck = mck_freq; best_r = r; - /* Stop if an exact match is found. */ - if (diff == 0) { - break; - } - best_diff = diff; } From 8f0e648e48b4f84e0d31927cdb48f0578d1cdb92 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Mon, 5 Feb 2024 12:50:51 +0100 Subject: [PATCH 0475/2402] Bluetooth: CAP: Shell: Add proper broadcast commands Adds additional broadcast commands and modifies the existing ones to use the CAP API. Signed-off-by: Emil Gydesen --- doc/connectivity/bluetooth/api/shell/cap.rst | 48 +++++ subsys/bluetooth/audio/shell/audio.h | 4 + subsys/bluetooth/audio/shell/bap.c | 25 ++- subsys/bluetooth/audio/shell/cap_initiator.c | 206 +++++++++++++++++-- 4 files changed, 264 insertions(+), 19 deletions(-) diff --git a/doc/connectivity/bluetooth/api/shell/cap.rst b/doc/connectivity/bluetooth/api/shell/cap.rst index cb8d755a458..f4a2490e28d 100644 --- a/doc/connectivity/bluetooth/api/shell/cap.rst +++ b/doc/connectivity/bluetooth/api/shell/cap.rst @@ -74,6 +74,7 @@ Using the CAP Initiator When the Bluetooth stack has been initialized (:code:`bt init`), the Initiator can discover CAS and the optionally included CSIS instance by calling (:code:`cap_initiator discover`). +The CAP initiator also supports broadcast audio as a source. .. code-block:: console @@ -164,6 +165,53 @@ used. uart:~$ cap_initiator unicast_stop all Unicast stop completed +When doing broadcast +-------------------- + +To start a broadcast as the CAP initiator there are a few steps to be done: + +1. Create and configure an extended advertising set with periodic advertising +2. Create and configure a broadcast source +3. Setup extended and periodic advertising data + +The following commands will setup a CAP broadcast source using the 16_2_1 preset (defined by BAP): + + +.. code-block:: console + + bt init + bap init + bt adv-create nconn-nscan ext-adv name + bt per-adv-param + cap_initiator ac_12 16_2_1 + bt adv-data discov + bt per-adv-data + cap_initiator broadcast_start + + +The broadcast source is created by the :code:`cap_initiator ac_12`, :code:`cap_initiator ac_13`, +and :code:`cap_initiator ac_14` commands, configuring the broadcast source for the defined audio +configurations from BAP. The broadcast source can then be stopped with +:code:`cap_initiator broadcast_stop` or deleted with :code:`cap_initiator broadcast_delete`. + +The metadata of the broadcast source can be updated at any time, including when it is already +streaming. To update the metadata the :code:`cap_initiator broadcast_update` command can be used. +The command takes an array of data, and the only requirement (besides having valid data) is that the +streaming context shall be set. For example to set the streaming context to media, the command can +be used as + +.. code-block:: console + + cap_initiator broadcast_update 03020400 + CAP Broadcast source updated with new metadata. Update the advertised base via `bt per-adv-data` + bt per-adv-data + +The :code:`bt per-adv-data` command should be used afterwards to update the data is the advertised +BASE. The data must be little-endian, so in the above example the metadata :code:`03020400` is +setting the metadata entry with :code:`03` as the length, :code:`02` as the type (streaming context) +and :code:`0400` as the value :code:`BT_AUDIO_CONTEXT_TYPE_MEDIA` +(which has the numeric value of 0x). + CAP Commander ************* diff --git a/subsys/bluetooth/audio/shell/audio.h b/subsys/bluetooth/audio/shell/audio.h index 78d67b873df..3f5184aeca8 100644 --- a/subsys/bluetooth/audio/shell/audio.h +++ b/subsys/bluetooth/audio/shell/audio.h @@ -33,6 +33,9 @@ ssize_t csis_ad_data_add(struct bt_data *data, const size_t data_size, const boo size_t cap_acceptor_ad_data_add(struct bt_data data[], size_t data_size, bool discoverable); size_t gmap_ad_data_add(struct bt_data data[], size_t data_size); size_t pbp_ad_data_add(struct bt_data data[], size_t data_size); +ssize_t cap_initiator_ad_data_add(struct bt_data *data_array, const size_t data_array_size, + const bool discoverable, const bool connectable); +ssize_t cap_initiator_pa_data_add(struct bt_data *data_array, const size_t data_array_size); #if defined(CONFIG_BT_AUDIO) /* Must guard before including audio.h as audio.h uses Kconfigs guarded by @@ -91,6 +94,7 @@ struct shell_stream { }; struct broadcast_source { + bool is_cap; union { struct bt_bap_broadcast_source *bap_source; struct bt_cap_broadcast_source *cap_source; diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index ce1ffebd807..23e7c0e0a1a 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -2723,7 +2723,7 @@ static int cmd_start_broadcast(const struct shell *sh, size_t argc, return -ENOEXEC; } - if (default_source.bap_source == NULL) { + if (default_source.bap_source == NULL || default_source.is_cap) { shell_info(sh, "Broadcast source not created"); return -ENOEXEC; } @@ -2741,7 +2741,7 @@ static int cmd_stop_broadcast(const struct shell *sh, size_t argc, char *argv[]) { int err; - if (default_source.bap_source == NULL) { + if (default_source.bap_source == NULL || default_source.is_cap) { shell_info(sh, "Broadcast source not created"); return -ENOEXEC; } @@ -2760,7 +2760,7 @@ static int cmd_delete_broadcast(const struct shell *sh, size_t argc, { int err; - if (default_source.bap_source == NULL) { + if (default_source.bap_source == NULL || default_source.is_cap) { shell_info(sh, "Broadcast source not created"); return -ENOEXEC; } @@ -3659,7 +3659,7 @@ static ssize_t nonconnectable_ad_data_add(struct bt_data *data_array, } #if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) - if (default_source.bap_source) { + if (default_source.bap_source != NULL && !default_source.is_cap) { static uint8_t ad_bap_broadcast_announcement[5] = { BT_UUID_16_ENCODE(BT_UUID_BROADCAST_AUDIO_VAL), }; @@ -3699,15 +3699,24 @@ static ssize_t nonconnectable_ad_data_add(struct bt_data *data_array, ssize_t audio_ad_data_add(struct bt_data *data_array, const size_t data_array_size, const bool discoverable, const bool connectable) { + ssize_t ad_len = 0; + if (!discoverable) { return 0; } if (connectable) { - return connectable_ad_data_add(data_array, data_array_size); + ad_len += connectable_ad_data_add(data_array, data_array_size); } else { - return nonconnectable_ad_data_add(data_array, data_array_size); + ad_len += nonconnectable_ad_data_add(data_array, data_array_size); + } + + if (IS_ENABLED(CONFIG_BT_CAP_INITIATOR)) { + ad_len += cap_initiator_ad_data_add(data_array, data_array_size, discoverable, + connectable); } + + return ad_len; } ssize_t audio_pa_data_add(struct bt_data *data_array, @@ -3716,7 +3725,7 @@ ssize_t audio_pa_data_add(struct bt_data *data_array, size_t ad_len = 0; #if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) - if (default_source.bap_source) { + if (default_source.bap_source != NULL && !default_source.is_cap) { /* Required size of the buffer depends on what has been * configured. We just use the maximum size possible. */ @@ -3734,6 +3743,8 @@ ssize_t audio_pa_data_add(struct bt_data *data_array, data_array[ad_len].data_len = base_buf.len; data_array[ad_len].data = base_buf.data; ad_len++; + } else if (IS_ENABLED(CONFIG_BT_CAP_INITIATOR)) { + return cap_initiator_pa_data_add(data_array, data_array_size); } #endif /* CONFIG_BT_BAP_BROADCAST_SOURCE */ diff --git a/subsys/bluetooth/audio/shell/cap_initiator.c b/subsys/bluetooth/audio/shell/cap_initiator.c index deb4395ae24..d6c21003a16 100644 --- a/subsys/bluetooth/audio/shell/cap_initiator.c +++ b/subsys/bluetooth/audio/shell/cap_initiator.c @@ -1086,11 +1086,116 @@ static int cmd_cap_ac_11_ii(const struct shell *sh, size_t argc, char **argv) #endif /* CONFIG_BT_BAP_UNICAST_CLIENT */ #if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) +static int cmd_broadcast_start(const struct shell *sh, size_t argc, char *argv[]) +{ + struct bt_le_ext_adv *adv = adv_sets[selected_adv]; + int err; + + if (adv == NULL) { + shell_info(sh, "Extended advertising set is NULL"); + + return -ENOEXEC; + } + + if (default_source.cap_source == NULL || !default_source.is_cap) { + shell_info(sh, "CAP Broadcast source not created"); + + return -ENOEXEC; + } + + err = bt_cap_initiator_broadcast_audio_start(default_source.cap_source, + adv_sets[selected_adv]); + if (err != 0) { + shell_error(sh, "Unable to start broadcast source: %d", err); + + return -ENOEXEC; + } + + return 0; +} + +static int cmd_broadcast_update(const struct shell *sh, size_t argc, char *argv[]) +{ + uint8_t meta[CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE]; + size_t len; + int err; + + if (default_source.cap_source == NULL || !default_source.is_cap) { + shell_info(sh, "CAP Broadcast source not created"); + + return -ENOEXEC; + } + + len = hex2bin(argv[1], strlen(argv[1]), meta, sizeof(meta)); + if (len == 0) { + shell_print(sh, "Unable to parse metadata (len was %zu, max len is %d)", + strlen(argv[1]) / 2U + strlen(argv[1]) % 2U, + CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE); + + return -ENOEXEC; + } + + err = bt_cap_initiator_broadcast_audio_update(default_source.cap_source, meta, len); + if (err != 0) { + shell_error(sh, "Unable to update broadcast source: %d", err); + + return -ENOEXEC; + } + + shell_print(sh, "CAP Broadcast source updated with new metadata. Update the advertised " + "base via `bt per-adv-data`"); + + return 0; +} + +static int cmd_broadcast_stop(const struct shell *sh, size_t argc, char *argv[]) +{ + int err; + + if (default_source.cap_source == NULL || !default_source.is_cap) { + shell_info(sh, "CAP Broadcast source not created"); + + return -ENOEXEC; + } + + err = bt_cap_initiator_broadcast_audio_stop(default_source.cap_source); + if (err != 0) { + shell_error(sh, "Unable to stop broadcast source: %d", err); + + return -ENOEXEC; + } + + return 0; +} + +static int cmd_broadcast_delete(const struct shell *sh, size_t argc, char *argv[]) +{ + int err; + + if (default_source.cap_source == NULL || !default_source.is_cap) { + shell_info(sh, "CAP Broadcast source not created"); + + return -ENOEXEC; + } + + err = bt_cap_initiator_broadcast_audio_delete(default_source.cap_source); + if (err != 0) { + shell_error(sh, "Unable to stop broadcast source: %d", err); + + return -ENOEXEC; + } + + default_source.cap_source = NULL; + default_source.is_cap = false; + + return 0; +} + int cap_ac_broadcast(const struct shell *sh, size_t argc, char **argv, const struct bap_broadcast_ac_param *param) { /* TODO: Use CAP API when the CAP shell has broadcast support */ - struct bt_bap_broadcast_source_stream_param stream_params[BAP_UNICAST_AC_MAX_SRC] = {0}; + struct bt_cap_initiator_broadcast_stream_param stream_params[BAP_UNICAST_AC_MAX_SRC] = {0}; uint8_t stereo_data[] = { BT_AUDIO_CODEC_DATA(BT_AUDIO_CODEC_CFG_CHAN_ALLOC, BT_AUDIO_LOCATION_FRONT_RIGHT | BT_AUDIO_LOCATION_FRONT_LEFT)}; @@ -1098,13 +1203,13 @@ int cap_ac_broadcast(const struct shell *sh, size_t argc, char **argv, BT_AUDIO_LOCATION_FRONT_RIGHT)}; uint8_t left_data[] = {BT_AUDIO_CODEC_DATA(BT_AUDIO_CODEC_CFG_CHAN_ALLOC, BT_AUDIO_LOCATION_FRONT_LEFT)}; - struct bt_bap_broadcast_source_subgroup_param subgroup_param = {0}; - struct bt_bap_broadcast_source_param create_param = {0}; + struct bt_cap_initiator_broadcast_subgroup_param subgroup_param = {0}; + struct bt_cap_initiator_broadcast_create_param create_param = {0}; const struct named_lc3_preset *named_preset; struct bt_le_ext_adv *adv; int err; - if (default_source.bap_source != NULL) { + if (default_source.cap_source != NULL) { shell_error(sh, "Broadcast Source already created, please delete first"); return -ENOEXEC; } @@ -1125,7 +1230,7 @@ int cap_ac_broadcast(const struct shell *sh, size_t argc, char **argv, default_source.qos.sdu *= param->chan_cnt; for (size_t i = 0U; i < param->stream_cnt; i++) { - stream_params[i].stream = &broadcast_source_streams[i].stream.bap_stream; + stream_params[i].stream = &broadcast_source_streams[i].stream; if (param->stream_cnt == 1U) { stream_params[i].data_len = ARRAY_SIZE(stereo_data); @@ -1139,14 +1244,14 @@ int cap_ac_broadcast(const struct shell *sh, size_t argc, char **argv, } } - subgroup_param.params_count = param->stream_cnt; - subgroup_param.params = stream_params; + subgroup_param.stream_count = param->stream_cnt; + subgroup_param.stream_params = stream_params; subgroup_param.codec_cfg = &default_source.codec_cfg; - create_param.params_count = 1U; - create_param.params = &subgroup_param; + create_param.subgroup_count = 1U; + create_param.subgroup_params = &subgroup_param; create_param.qos = &default_source.qos; - err = bt_bap_broadcast_source_create(&create_param, &default_source.bap_source); + err = bt_cap_initiator_broadcast_audio_create(&create_param, &default_source.cap_source); if (err != 0) { shell_error(sh, "Failed to create broadcast source: %d", err); return -ENOEXEC; @@ -1156,9 +1261,11 @@ int cap_ac_broadcast(const struct shell *sh, size_t argc, char **argv, * periodic advertising data, the broadcast source needs to be created but not started. */ shell_print(sh, - "Broadcast source for %s created. Start via `bap start_broadcast`, and " - "update/set the base via `bt per-adv data`", + "CAP Broadcast source for %s created. " + "Start via `cap_initiator broadcast_start`, " + "and update / set the base via `bt per-adv data`", param->name); + default_source.is_cap = true; return 0; } @@ -1283,6 +1390,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE( #endif /* UNICAST_SINK_SUPPORTED && UNICAST_SRC_SUPPORTED */ #endif /* CONFIG_BT_BAP_UNICAST_CLIENT */ #if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) + SHELL_CMD_ARG(broadcast_start, NULL, "", cmd_broadcast_start, 1, 0), + SHELL_CMD_ARG(broadcast_update, NULL, "", cmd_broadcast_update, 2, 0), + SHELL_CMD_ARG(broadcast_stop, NULL, "", cmd_broadcast_stop, 1, 0), + SHELL_CMD_ARG(broadcast_delete, NULL, "", cmd_broadcast_delete, 1, 0), SHELL_CMD_ARG(ac_12, NULL, "", cmd_cap_ac_12, 2, 0), #if CONFIG_BT_BAP_BROADCAST_SRC_STREAM_COUNT > 1 SHELL_CMD_ARG(ac_13, NULL, "", cmd_cap_ac_13, 2, 0), @@ -1294,3 +1405,74 @@ SHELL_STATIC_SUBCMD_SET_CREATE( SHELL_CMD_ARG_REGISTER(cap_initiator, &cap_initiator_cmds, "Bluetooth CAP initiator shell commands", cmd_cap_initiator, 1, 1); + +static ssize_t nonconnectable_ad_data_add(struct bt_data *data_array, const size_t data_array_size) +{ +#if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) + if (default_source.cap_source != NULL && default_source.is_cap) { + static uint8_t ad_cap_broadcast_announcement[5] = { + BT_UUID_16_ENCODE(BT_UUID_BROADCAST_AUDIO_VAL), + }; + uint32_t broadcast_id; + int err; + + err = bt_cap_initiator_broadcast_get_id(default_source.cap_source, &broadcast_id); + if (err != 0) { + printk("Unable to get broadcast ID: %d\n", err); + + return -1; + } + + sys_put_le24(broadcast_id, &ad_cap_broadcast_announcement[2]); + data_array[0].type = BT_DATA_SVC_DATA16; + data_array[0].data_len = ARRAY_SIZE(ad_cap_broadcast_announcement); + data_array[0].data = ad_cap_broadcast_announcement; + + return 1; + } +#endif /* CONFIG_BT_BAP_BROADCAST_SOURCE */ + + return 0; +} + +ssize_t cap_initiator_ad_data_add(struct bt_data *data_array, const size_t data_array_size, + const bool discoverable, const bool connectable) +{ + if (!discoverable) { + return 0; + } + + if (!connectable) { + return nonconnectable_ad_data_add(data_array, data_array_size); + } + + return 0; +} + +ssize_t cap_initiator_pa_data_add(struct bt_data *data_array, const size_t data_array_size) +{ +#if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) + if (default_source.cap_source != NULL && default_source.is_cap) { + /* Required size of the buffer depends on what has been + * configured. We just use the maximum size possible. + */ + NET_BUF_SIMPLE_DEFINE_STATIC(base_buf, UINT8_MAX); + int err; + + err = bt_cap_initiator_broadcast_get_base(default_source.cap_source, &base_buf); + if (err != 0) { + printk("Unable to get BASE: %d\n", err); + + return -1; + } + + data_array[0].type = BT_DATA_SVC_DATA16; + data_array[0].data_len = base_buf.len; + data_array[0].data = base_buf.data; + + return 1; + } +#endif /* CONFIG_BT_BAP_BROADCAST_SOURCE */ + + return 0; +} From cb3d1c9ee9f1e82cb5cfd53fb7774a5171ce687c Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Thu, 29 Feb 2024 15:48:32 +0800 Subject: [PATCH 0476/2402] Bluetooth: RFCOMM: Add data sent cb for RFCOMM Currently, the upper layer cannot know whether the data is successfully sent through DLC. Add a field "sent" for RFCOMM DLC ops. Notify upper-layer of the sending result through the field "sent". Signed-off-by: Lyle Zhu --- include/zephyr/bluetooth/classic/rfcomm.h | 8 ++ subsys/bluetooth/host/Kconfig | 9 ++ subsys/bluetooth/host/classic/rfcomm.c | 143 +++++++++++++++++++++- 3 files changed, 157 insertions(+), 3 deletions(-) diff --git a/include/zephyr/bluetooth/classic/rfcomm.h b/include/zephyr/bluetooth/classic/rfcomm.h index cd0a1fff09f..5664506931c 100644 --- a/include/zephyr/bluetooth/classic/rfcomm.h +++ b/include/zephyr/bluetooth/classic/rfcomm.h @@ -62,6 +62,14 @@ struct bt_rfcomm_dlc_ops { * @param buf Buffer containing incoming data. */ void (*recv)(struct bt_rfcomm_dlc *dlc, struct net_buf *buf); + + /** DLC sent callback + * + * @param dlc The dlc which has sent data. + * @param buf Buffer containing data has been sent. + * @param err Sent result. + */ + void (*sent)(struct bt_rfcomm_dlc *dlc, struct net_buf *buf, int err); }; /** @brief Role of RFCOMM session and dlc. Used only by internal APIs diff --git a/subsys/bluetooth/host/Kconfig b/subsys/bluetooth/host/Kconfig index 9805ee0c06f..e124a549785 100644 --- a/subsys/bluetooth/host/Kconfig +++ b/subsys/bluetooth/host/Kconfig @@ -1061,6 +1061,15 @@ config BT_RFCOMM_L2CAP_MTU help Maximum size of L2CAP PDU for RFCOMM frames. +config BT_RFCOMM_TX_MAX + int "Maximum number of pending TX buffers for RFCOMM" + default BT_MAX_CONN + range BT_MAX_CONN 255 + help + Maximum number of pending TX buffers that have an associated + sending buf. Normally this can be left to the default value, which + is equal to the number of session in the stack-internal pool. + config BT_HFP_HF bool "Bluetooth Handsfree profile HF Role support [EXPERIMENTAL]" depends on PRINTK diff --git a/subsys/bluetooth/host/classic/rfcomm.c b/subsys/bluetooth/host/classic/rfcomm.c index 489aab4d292..d72124fef9b 100644 --- a/subsys/bluetooth/host/classic/rfcomm.c +++ b/subsys/bluetooth/host/classic/rfcomm.c @@ -50,6 +50,18 @@ LOG_MODULE_REGISTER(bt_rfcomm); #define SESSION_RTX(_w) CONTAINER_OF(k_work_delayable_from_work(_w), \ struct bt_rfcomm_session, rtx_work) +struct bt_rfcomm_tx { + sys_snode_t node; + struct bt_rfcomm_dlc *dlc; + struct net_buf *buf; +}; + +#define rfcomm_tx_data(buf) ((struct bt_rfcomm_tx **)net_buf_user_data(buf)) + +static struct bt_rfcomm_tx rfcomm_tx[CONFIG_BT_RFCOMM_TX_MAX]; + +static K_FIFO_DEFINE(rfcomm_tx_free); + static struct bt_rfcomm_server *servers; /* Pool for dummy buffers to wake up the tx threads */ @@ -312,11 +324,12 @@ struct net_buf *bt_rfcomm_create_pdu(struct net_buf_pool *pool) sizeof(struct bt_rfcomm_hdr) + 1); } -static int rfcomm_send(struct bt_rfcomm_session *session, struct net_buf *buf) +static int rfcomm_send_cb(struct bt_rfcomm_session *session, struct net_buf *buf, + bt_conn_tx_cb_t cb, void *user_data) { int err; - err = bt_l2cap_chan_send(&session->br_chan.chan, buf); + err = bt_l2cap_br_chan_send_cb(&session->br_chan.chan, buf, cb, user_data); if (err < 0) { net_buf_unref(buf); } @@ -324,6 +337,11 @@ static int rfcomm_send(struct bt_rfcomm_session *session, struct net_buf *buf) return err; } +static int rfcomm_send(struct bt_rfcomm_session *session, struct net_buf *buf) +{ + return rfcomm_send_cb(session, buf, NULL, NULL); +} + static int rfcomm_send_sabm(struct bt_rfcomm_session *session, uint8_t dlci) { struct bt_rfcomm_hdr *hdr; @@ -535,11 +553,103 @@ static void rfcomm_check_fc(struct bt_rfcomm_dlc *dlc) k_sem_give(&dlc->tx_credits); } +static struct bt_rfcomm_tx *bt_rfcomm_tx_alloc(void) +{ + /* The TX context always get freed in the system workqueue, + * so if we're in the same workqueue but there are no immediate + * contexts available, there's no chance we'll get one by waiting. + */ + if (k_current_get() == &k_sys_work_q.thread) { + return k_fifo_get(&rfcomm_tx_free, K_NO_WAIT); + } + + if (IS_ENABLED(CONFIG_BT_RFCOMM_LOG_LEVEL_DBG)) { + struct bt_rfcomm_tx *tx = k_fifo_get(&rfcomm_tx_free, K_NO_WAIT); + + if (tx) { + return tx; + } + + LOG_WRN("Unable to get an immediate free bt_rfcomm_tx"); + } + + return k_fifo_get(&rfcomm_tx_free, K_FOREVER); +} + +static void bt_rfcomm_tx_free(struct bt_rfcomm_tx *tx) +{ + LOG_DBG("Free tx buffer %p", tx); + + tx->buf = NULL; + tx->dlc = NULL; + k_fifo_put(&rfcomm_tx_free, tx); +} + +static void bt_rfcomm_tx_destroy(struct net_buf *buf) +{ + struct bt_rfcomm_tx *tx; + struct bt_rfcomm_dlc *dlc; + struct net_buf *tx_buf; + + LOG_DBG("buf %p", buf); + + if ((buf == NULL) || (buf->len == 0)) { + return; + } + + tx = *rfcomm_tx_data(buf); + tx_buf = tx->buf; + dlc = tx->dlc; + + bt_rfcomm_tx_free(tx); + + if (tx_buf != buf) { + LOG_ERR("Tx buf %p and buf %p are inconsistent", tx_buf, buf); + } + + if (dlc && dlc->ops && dlc->ops->sent) { + dlc->ops->sent(dlc, tx_buf, -ESHUTDOWN); + } + + if (tx_buf != NULL) { + net_buf_unref(tx_buf); + } +} + +static void rfcomm_sent(struct bt_conn *conn, void *user_data, int err) +{ + struct bt_rfcomm_tx *tx; + struct bt_rfcomm_dlc *dlc; + struct net_buf *tx_buf; + + LOG_DBG("conn %p", conn); + + if (user_data == NULL) { + return; + } + + tx = user_data; + + tx_buf = tx->buf; + dlc = tx->dlc; + + bt_rfcomm_tx_free(tx); + + if (dlc && dlc->ops && dlc->ops->sent) { + dlc->ops->sent(dlc, tx_buf, err); + } + + if (tx_buf != NULL) { + net_buf_unref(tx_buf); + } +} + static void rfcomm_dlc_tx_thread(void *p1, void *p2, void *p3) { struct bt_rfcomm_dlc *dlc = p1; k_timeout_t timeout = K_FOREVER; struct net_buf *buf; + struct bt_rfcomm_tx *tx; LOG_DBG("Started for dlc %p", dlc); @@ -553,6 +663,7 @@ static void rfcomm_dlc_tx_thread(void *p1, void *p2, void *p3) dlc->state != BT_RFCOMM_STATE_USER_DISCONNECT) || !buf || !buf->len) { if (buf) { + bt_rfcomm_tx_destroy(buf); net_buf_unref(buf); } break; @@ -561,13 +672,17 @@ static void rfcomm_dlc_tx_thread(void *p1, void *p2, void *p3) rfcomm_check_fc(dlc); if (dlc->state != BT_RFCOMM_STATE_CONNECTED && dlc->state != BT_RFCOMM_STATE_USER_DISCONNECT) { + bt_rfcomm_tx_destroy(buf); net_buf_unref(buf); break; } - if (rfcomm_send(dlc->session, buf) < 0) { + tx = *rfcomm_tx_data(buf); + + if (rfcomm_send_cb(dlc->session, buf, rfcomm_sent, tx) < 0) { /* This fails only if channel is disconnected */ dlc->state = BT_RFCOMM_STATE_DISCONNECTED; + bt_rfcomm_tx_destroy(buf); break; } @@ -580,6 +695,7 @@ static void rfcomm_dlc_tx_thread(void *p1, void *p2, void *p3) /* Give back any allocated buffers */ while ((buf = net_buf_get(&dlc->tx_queue, K_NO_WAIT))) { + bt_rfcomm_tx_destroy(buf); net_buf_unref(buf); } @@ -1411,6 +1527,7 @@ static void rfcomm_handle_data(struct bt_rfcomm_session *session, int bt_rfcomm_dlc_send(struct bt_rfcomm_dlc *dlc, struct net_buf *buf) { + struct bt_rfcomm_tx *tx; uint8_t fcs, cr; if (!buf) { @@ -1427,6 +1544,19 @@ int bt_rfcomm_dlc_send(struct bt_rfcomm_dlc *dlc, struct net_buf *buf) return -EMSGSIZE; } + tx = bt_rfcomm_tx_alloc(); + if (tx == NULL) { + LOG_ERR("No tx buffer"); + return -ENOBUFS; + } + + LOG_DBG("TX buffer %p", tx); + + tx->dlc = dlc; + tx->buf = net_buf_ref(buf); + + *rfcomm_tx_data(buf) = tx; + /* length */ if (buf->len > BT_RFCOMM_MAX_LEN_8) { /* Length is 2 byte */ @@ -1724,6 +1854,7 @@ static int rfcomm_accept(struct bt_conn *conn, struct bt_l2cap_server *server, void bt_rfcomm_init(void) { + int i; static struct bt_l2cap_server server = { .psm = BT_L2CAP_PSM_RFCOMM, .accept = rfcomm_accept, @@ -1731,4 +1862,10 @@ void bt_rfcomm_init(void) }; bt_l2cap_br_server_register(&server); + + k_fifo_init(&rfcomm_tx_free); + + for (i = 0; i < ARRAY_SIZE(rfcomm_tx); i++) { + k_fifo_put(&rfcomm_tx_free, &rfcomm_tx[i]); + } } From 3e8d1182d414edc3c0ee96b2a7d5549e5bfb2e51 Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Fri, 1 Mar 2024 10:39:23 +0800 Subject: [PATCH 0477/2402] Bluetooth: HFP: Add data sent callback Set struct bt_rfcomm_dlc_ops::sent. Get the data sending result through sent callback. Signed-off-by: Lyle Zhu --- subsys/bluetooth/host/classic/hfp_hf.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/subsys/bluetooth/host/classic/hfp_hf.c b/subsys/bluetooth/host/classic/hfp_hf.c index effccb08b0e..cfa4ed4ae39 100644 --- a/subsys/bluetooth/host/classic/hfp_hf.c +++ b/subsys/bluetooth/host/classic/hfp_hf.c @@ -94,6 +94,8 @@ int hfp_hf_send_cmd(struct bt_hfp_hf *hf, at_resp_cb_t resp, net_buf_add(buf, ret); net_buf_add_u8(buf, '\r'); + LOG_DBG("HF %p, DLC %p sending buf %p", hf, &hf->rfcomm_dlc, buf); + ret = bt_rfcomm_dlc_send(&hf->rfcomm_dlc, buf); if (ret < 0) { LOG_ERR("Rfcomm send error :(%d)", ret); @@ -640,6 +642,11 @@ static void hfp_hf_recv(struct bt_rfcomm_dlc *dlc, struct net_buf *buf) } } +static void hfp_hf_sent(struct bt_rfcomm_dlc *dlc, struct net_buf *buf, int err) +{ + LOG_DBG("DLC %p sent cb buf %p (err %d)", dlc, buf, err); +} + static int bt_hfp_hf_accept(struct bt_conn *conn, struct bt_rfcomm_dlc **dlc) { int i; @@ -647,6 +654,7 @@ static int bt_hfp_hf_accept(struct bt_conn *conn, struct bt_rfcomm_dlc **dlc) .connected = hfp_hf_connected, .disconnected = hfp_hf_disconnected, .recv = hfp_hf_recv, + .sent = hfp_hf_sent, }; LOG_DBG("conn %p", conn); From 6d493776e922215b31c53ed8ceef7d08f54ed535 Mon Sep 17 00:00:00 2001 From: Daniel Fladerer Date: Wed, 6 Mar 2024 18:59:26 +0100 Subject: [PATCH 0478/2402] soc: arm: nxp_imx: Add GPIO clock enable for i.MX8ML M7 Core Series Enable clock if GPIO bank is enabled in the devicetree. Signed-off-by: Daniel Fladerer --- soc/nxp/imx/imx8m/m7/soc.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/soc/nxp/imx/imx8m/m7/soc.c b/soc/nxp/imx/imx8m/m7/soc.c index 835985eb663..950212b26a4 100644 --- a/soc/nxp/imx/imx8m/m7/soc.c +++ b/soc/nxp/imx/imx8m/m7/soc.c @@ -148,6 +148,38 @@ static void SOC_ClockInit(void) CLOCK_EnableClock(kCLOCK_Sec_Debug); } +static void gpio_init(void) +{ + +#if defined(CONFIG_GPIO_MCUX_IGPIO) +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay) + + CLOCK_EnableClock(kCLOCK_Gpio1); + +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay) + + CLOCK_EnableClock(kCLOCK_Gpio2); + +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay) + + CLOCK_EnableClock(kCLOCK_Gpio3); + +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay) + + CLOCK_EnableClock(kCLOCK_Gpio4); + +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay) + + CLOCK_EnableClock(kCLOCK_Gpio5); + +#endif +#endif +} + static int nxp_mimx8ml8_init(void) { @@ -157,6 +189,8 @@ static int nxp_mimx8ml8_init(void) /* SoC specific Clock settings */ SOC_ClockInit(); + gpio_init(); + return 0; } From e59ff45ebc484db25c2e765d9185f3cdef046a08 Mon Sep 17 00:00:00 2001 From: Georgij Cernysiov Date: Fri, 1 Mar 2024 23:17:16 +0100 Subject: [PATCH 0479/2402] dts: bindings: serial: stm32: block clock-frequency Blocks 'clock-frequency' property included from 'uart-controller.yml' in the STM32 UART base. Signed-off-by: Georgij Cernysiov --- dts/bindings/serial/st,stm32-uart-base.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/dts/bindings/serial/st,stm32-uart-base.yaml b/dts/bindings/serial/st,stm32-uart-base.yaml index 3c20564bdda..f84b4def057 100644 --- a/dts/bindings/serial/st,stm32-uart-base.yaml +++ b/dts/bindings/serial/st,stm32-uart-base.yaml @@ -4,7 +4,12 @@ # Common fields for STM32 UART peripherals. description: STM32 UART-BASE -include: [uart-controller.yaml, pinctrl-device.yaml, reset-device.yaml] +include: + - name: uart-controller.yaml + property-blocklist: + - clock-frequency + - name: pinctrl-device.yaml + - name: reset-device.yaml properties: reg: From f43d5c4394a9fc371fcf72da0bbf0bc239c3955f Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 4 Mar 2024 11:10:20 +0100 Subject: [PATCH 0480/2402] boards: nordic: nrf54h20pdk: fix cpuppr flash Board defaults to XIP, in which case flash is 64K. Signed-off-by: Gerard Marull-Paretas --- boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml index e3cdc3cd1c8..b19d68e750d 100644 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml @@ -8,6 +8,6 @@ arch: riscv toolchain: - zephyr ram: 28 -flash: 28 +flash: 64 supported: - gpio From 2fe1bb39f29419391f01f058eb58163b500ac69b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 4 Mar 2024 11:20:05 +0100 Subject: [PATCH 0481/2402] soc: nordic: vpr: always select HAS_FLASH_LOAD_OFFSET While not needed when XIP=n, it can be still be selected so that come defconfigs are simplified. Signed-off-by: Gerard Marull-Paretas --- soc/nordic/common/vpr/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/nordic/common/vpr/Kconfig b/soc/nordic/common/vpr/Kconfig index 70ac63e7204..baef3432a90 100644 --- a/soc/nordic/common/vpr/Kconfig +++ b/soc/nordic/common/vpr/Kconfig @@ -14,6 +14,6 @@ config RISCV_CORE_NORDIC_VPR select RISCV_ISA_EXT_ZIFENCEI select RISCV_SOC_HAS_ISR_STACKING select RISCV_SOC_CONTEXT_SAVE - select HAS_FLASH_LOAD_OFFSET if XIP + select HAS_FLASH_LOAD_OFFSET help Enable support for the RISC-V Nordic VPR core. From 8492673ca6568930e7ef163608b69f101599904c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 4 Mar 2024 11:21:17 +0100 Subject: [PATCH 0482/2402] boards: nordic: nrf54h20pdk: add ram variant for cpuppr This new variant allows to easily execute from RAM when building for the PPR core. Signed-off-by: Gerard Marull-Paretas --- boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk | 3 ++- boards/nordic/nrf54h20pdk/board.yml | 3 +++ .../nrf54h20pdk_nrf54h20_cpuppr_ram.yaml | 13 +++++++++++++ .../nrf54h20pdk_nrf54h20_cpuppr_ram_defconfig | 4 ++++ 4 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram.yaml create mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram_defconfig diff --git a/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk b/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk index 4185c95ef2a..616f89b7372 100644 --- a/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk +++ b/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk @@ -4,4 +4,5 @@ config BOARD_NRF54H20PDK select SOC_NRF54H20_ENGA_CPUAPP if BOARD_NRF54H20PDK_NRF54H20_CPUAPP select SOC_NRF54H20_ENGA_CPURAD if BOARD_NRF54H20PDK_NRF54H20_CPURAD - select SOC_NRF54H20_ENGA_CPUPPR if BOARD_NRF54H20PDK_NRF54H20_CPUPPR + select SOC_NRF54H20_ENGA_CPUPPR if BOARD_NRF54H20PDK_NRF54H20_CPUPPR || \ + BOARD_NRF54H20PDK_NRF54H20_CPUPPR_RAM diff --git a/boards/nordic/nrf54h20pdk/board.yml b/boards/nordic/nrf54h20pdk/board.yml index 50e2945307f..633912b4127 100644 --- a/boards/nordic/nrf54h20pdk/board.yml +++ b/boards/nordic/nrf54h20pdk/board.yml @@ -3,3 +3,6 @@ board: vendor: nordic socs: - name: nrf54h20 + variants: + - name: ram + cpucluster: cpuppr diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram.yaml new file mode 100644 index 00000000000..596392b5373 --- /dev/null +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20pdk/nrf54h20/cpuppr/ram +name: nRF54H20-PDK-nRF54H20-PPR-RAM +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 28 +flash: 28 +supported: + - gpio diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram_defconfig new file mode 100644 index 00000000000..bc8ce62afbb --- /dev/null +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram_defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n From 63fbeebb9ac543e1ae97ea31ea8ae458aff26914 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Mon, 4 Mar 2024 13:33:11 +0100 Subject: [PATCH 0483/2402] Bluetooth: BAP: Shell: Add missing err check for bt_bap_ep_get_info Two places we did not have an error check from calling bt_bap_ep_get_info before accessing the result. These have simply been added (without an else), as they are (very) unlikely to fail. This was caught by coverity and thus fixes those coverity issues. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/shell/bap.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index 23e7c0e0a1a..172b43e8c84 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -2541,10 +2541,10 @@ static void stream_released_cb(struct bt_bap_stream *stream) if (bap_stream->ep != NULL) { struct bt_bap_ep_info ep_info; + int err; - bt_bap_ep_get_info(bap_stream->ep, &ep_info); - - if (ep_info.state != BT_BAP_EP_STATE_CODEC_CONFIGURED && + err = bt_bap_ep_get_info(bap_stream->ep, &ep_info); + if (err == 0 && ep_info.state != BT_BAP_EP_STATE_CODEC_CONFIGURED && ep_info.state != BT_BAP_EP_STATE_IDLE) { group_can_be_deleted = false; break; @@ -3439,10 +3439,12 @@ static int cmd_recv_stats(const struct shell *sh, size_t argc, char *argv[]) static void print_ase_info(struct bt_bap_ep *ep, void *user_data) { struct bt_bap_ep_info info; + int err; - bt_bap_ep_get_info(ep, &info); - printk("ASE info: id %u state %u dir %u\n", info.id, info.state, - info.dir); + err = bt_bap_ep_get_info(ep, &info); + if (err == 0) { + printk("ASE info: id %u state %u dir %u\n", info.id, info.state, info.dir); + } } static int cmd_print_ase_info(const struct shell *sh, size_t argc, char *argv[]) From ac2993493b49571f210c35bf1e8e985b918c0afe Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Tue, 5 Mar 2024 16:21:00 -0600 Subject: [PATCH 0484/2402] soc: nxp: imxrt: do not select HAS_PM at family level Not all SOC cores within the NXP iMX RT family support power management (for example, the Fusion F1 DSP has no support). Do not select HAS_PM at the SOC family level, and instead select it at the series level where applicable Fixes #69731 Signed-off-by: Daniel DeGrasse --- soc/nxp/imxrt/Kconfig | 1 - soc/nxp/imxrt/imxrt10xx/Kconfig | 1 + soc/nxp/imxrt/imxrt11xx/Kconfig | 1 + 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/soc/nxp/imxrt/Kconfig b/soc/nxp/imxrt/Kconfig index 6306520fd38..cdcf6c4495d 100644 --- a/soc/nxp/imxrt/Kconfig +++ b/soc/nxp/imxrt/Kconfig @@ -3,7 +3,6 @@ config SOC_FAMILY_NXP_IMXRT select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_PM if SOC_FAMILY_NXP_IMXRT diff --git a/soc/nxp/imxrt/imxrt10xx/Kconfig b/soc/nxp/imxrt/imxrt10xx/Kconfig index 7884383b3a6..51b894ae304 100644 --- a/soc/nxp/imxrt/imxrt10xx/Kconfig +++ b/soc/nxp/imxrt/imxrt10xx/Kconfig @@ -28,6 +28,7 @@ config SOC_SERIES_IMXRT10XX select HAS_MCUX_DCDC select HAS_MCUX_USB_EHCI select HAS_SWO + select HAS_PM config SOC_MIMXRT1011 select CPU_HAS_FPU diff --git a/soc/nxp/imxrt/imxrt11xx/Kconfig b/soc/nxp/imxrt/imxrt11xx/Kconfig index 2f4fed978f9..6e2218dae2c 100644 --- a/soc/nxp/imxrt/imxrt11xx/Kconfig +++ b/soc/nxp/imxrt/imxrt11xx/Kconfig @@ -44,6 +44,7 @@ config SOC_SERIES_IMXRT11XX select HAS_MCUX_IOMUXC select HAS_MCUX_XBARA select HAS_SWO + select HAS_PM config SOC_MIMXRT1176_CM4 select CPU_CORTEX_M4 From 32ce6ef99787bf4923f7d3c60a53d36bb99b624b Mon Sep 17 00:00:00 2001 From: Mark Wang Date: Thu, 7 Mar 2024 16:12:59 +0800 Subject: [PATCH 0485/2402] drivers: serial: uart_mcux_lpuart: support the flow control pin mux Configure the pins of flow control if it is added in device tree. Signed-off-by: Mark Wang --- drivers/serial/uart_mcux_lpuart.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/serial/uart_mcux_lpuart.c b/drivers/serial/uart_mcux_lpuart.c index 3c2f318f90e..17604e92086 100644 --- a/drivers/serial/uart_mcux_lpuart.c +++ b/drivers/serial/uart_mcux_lpuart.c @@ -24,6 +24,8 @@ LOG_MODULE_REGISTER(uart_mcux_lpuart, LOG_LEVEL_ERR); +#define PINCTRL_STATE_FLOWCONTROL PINCTRL_STATE_PRIV_START + #ifdef CONFIG_UART_ASYNC_API struct lpuart_dma_config { const struct device *dma_dev; @@ -1060,7 +1062,16 @@ static int mcux_lpuart_init(const struct device *dev) /* set initial configuration */ mcux_lpuart_configure_init(dev, uart_api_config); - err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); + if (config->flow_ctrl) { + const struct pinctrl_state *state; + + err = pinctrl_lookup_state(config->pincfg, PINCTRL_STATE_FLOWCONTROL, &state); + if (err < 0) { + err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); + } + } else { + err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); + } if (err < 0) { return err; } From c9467d896784b344fd969d626eed01c559e96bf6 Mon Sep 17 00:00:00 2001 From: Mark Wang Date: Thu, 7 Mar 2024 16:54:34 +0800 Subject: [PATCH 0486/2402] boards: nxp: mimxrt1060_evk: try the flow control pin mux in RT1060 test configuring pin mux of lpuart flow control in RT1060 Signed-off-by: Mark Wang --- boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts index 0eed6e4fc2b..7438f4b38b0 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts @@ -109,8 +109,9 @@ arduino_serial: &lpuart3 { pinctrl-0 = <&pinmux_lpuart3>; - pinctrl-1 = <&pinmux_lpuart3_sleep>; - pinctrl-names = "default", "sleep"; + pinctrl-1 = <&pinmux_lpuart3_flow_control>; + pinctrl-2 = <&pinmux_lpuart3_sleep>; + pinctrl-names = "default", "flowcontrol", "sleep"; }; &lcdif { From 624c87af160367e7d0fb5f1adfbf1a689e4e99a6 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 5 Mar 2024 10:24:56 +0100 Subject: [PATCH 0487/2402] dts: arm: nordic: keep NFCT disabled by default Enabling peripherals at SoC dts files should not be done, unless there are good reasons (e.g. always needed peripherals). NFCT node should either be enabled at board level, or, at application level. Signed-off-by: Gerard Marull-Paretas --- dts/arm/nordic/nrf52832.dtsi | 2 +- dts/arm/nordic/nrf52833.dtsi | 2 +- dts/arm/nordic/nrf52840.dtsi | 2 +- dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/dts/arm/nordic/nrf52832.dtsi b/dts/arm/nordic/nrf52832.dtsi index ed5a21b9935..13ee05226b7 100644 --- a/dts/arm/nordic/nrf52832.dtsi +++ b/dts/arm/nordic/nrf52832.dtsi @@ -177,7 +177,7 @@ compatible = "nordic,nrf-nfct"; reg = <0x40005000 0x1000>; interrupts = <5 NRF_DEFAULT_IRQ_PRIORITY>; - status = "okay"; + status = "disabled"; }; gpiote: gpiote0: gpiote@40006000 { diff --git a/dts/arm/nordic/nrf52833.dtsi b/dts/arm/nordic/nrf52833.dtsi index 5ac9cb2d2f8..f22cb36bc14 100644 --- a/dts/arm/nordic/nrf52833.dtsi +++ b/dts/arm/nordic/nrf52833.dtsi @@ -184,7 +184,7 @@ compatible = "nordic,nrf-nfct"; reg = <0x40005000 0x1000>; interrupts = <5 NRF_DEFAULT_IRQ_PRIORITY>; - status = "okay"; + status = "disabled"; }; gpiote: gpiote0: gpiote@40006000 { diff --git a/dts/arm/nordic/nrf52840.dtsi b/dts/arm/nordic/nrf52840.dtsi index 20c18cf3d84..4cfb7abc511 100644 --- a/dts/arm/nordic/nrf52840.dtsi +++ b/dts/arm/nordic/nrf52840.dtsi @@ -179,7 +179,7 @@ compatible = "nordic,nrf-nfct"; reg = <0x40005000 0x1000>; interrupts = <5 NRF_DEFAULT_IRQ_PRIORITY>; - status = "okay"; + status = "disabled"; }; gpiote: gpiote0: gpiote@40006000 { diff --git a/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi b/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi index 94e764ec52c..c9f1ff2fae9 100644 --- a/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi +++ b/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi @@ -449,7 +449,7 @@ nfct: nfct@2d000 { compatible = "nordic,nrf-nfct"; reg = <0x2d000 0x1000>; interrupts = <45 NRF_DEFAULT_IRQ_PRIORITY>; - status = "okay"; + status = "disabled"; }; mutex: mutex@30000 { From d0d7a7909e406705b8ab785c5f010b981dbb730f Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 11 Mar 2024 07:24:50 -0300 Subject: [PATCH 0488/2402] driver: uart: esp32: get port number from reg address ESP32 uart driver requires uart port number to its low level calls. In case uart0 is disabled and uart1 is enabled, driver will set default port num to 0 when it should be 1. This fixes this scenario by retrieving uart pot number based on periphral address. Fixes #69973 Signed-off-by: Sylvio Alves --- drivers/serial/uart_esp32.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/serial/uart_esp32.c b/drivers/serial/uart_esp32.c index be5d2487e13..4899d13d5b1 100644 --- a/drivers/serial/uart_esp32.c +++ b/drivers/serial/uart_esp32.c @@ -71,7 +71,6 @@ struct uart_esp32_config { const struct device *dma_dev; uint8_t tx_dma_channel; uint8_t rx_dma_channel; - bool uart_id; #endif }; @@ -923,7 +922,7 @@ static int uart_esp32_init(const struct device *dev) clock_control_on(config->clock_dev, (clock_control_subsys_t)ESP32_UHCI0_MODULE); uhci_ll_init(data->uhci_dev); uhci_ll_set_eof_mode(data->uhci_dev, UHCI_RX_IDLE_EOF | UHCI_RX_LEN_EOF); - uhci_ll_attach_uart_port(data->uhci_dev, config->uart_id); + uhci_ll_attach_uart_port(data->uhci_dev, uart_hal_get_port_num(&data->hal)); data->uart_dev = dev; k_work_init_delayable(&data->async.tx_timeout_work, uart_esp32_async_tx_timeout); @@ -971,8 +970,7 @@ static const DRAM_ATTR struct uart_driver_api uart_esp32_api = { #define ESP_UART_DMA_INIT(n) \ .dma_dev = ESP32_DT_INST_DMA_CTLR(n, tx), \ .tx_dma_channel = ESP32_DT_INST_DMA_CELL(n, tx, channel), \ - .rx_dma_channel = ESP32_DT_INST_DMA_CELL(n, rx, channel), \ - .uart_id = (DEVICE_DT_GET(DT_NODELABEL(uart0)) != DEVICE_DT_INST_GET(n)), + .rx_dma_channel = ESP32_DT_INST_DMA_CELL(n, rx, channel) #define ESP_UART_UHCI_INIT(n) \ .uhci_dev = COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), (&UHCI0), (NULL)) From c57946173f417b2c3ff644991f2385a6d4716fec Mon Sep 17 00:00:00 2001 From: Magdalena Pastula Date: Fri, 2 Feb 2024 15:50:34 +0100 Subject: [PATCH 0489/2402] tests: drivers: timer: add nrf_grtc_timer tests Add NRF GRTC timer test for nRF54L15. Signed-off-by: Magdalena Pastula --- .../timer/nrf_grtc_timer/CMakeLists.txt | 9 +++++ tests/drivers/timer/nrf_grtc_timer/prj.conf | 2 + tests/drivers/timer/nrf_grtc_timer/src/main.c | 40 +++++++++++++++++++ .../timer/nrf_grtc_timer/testcase.yaml | 4 ++ 4 files changed, 55 insertions(+) create mode 100644 tests/drivers/timer/nrf_grtc_timer/CMakeLists.txt create mode 100644 tests/drivers/timer/nrf_grtc_timer/prj.conf create mode 100644 tests/drivers/timer/nrf_grtc_timer/src/main.c create mode 100644 tests/drivers/timer/nrf_grtc_timer/testcase.yaml diff --git a/tests/drivers/timer/nrf_grtc_timer/CMakeLists.txt b/tests/drivers/timer/nrf_grtc_timer/CMakeLists.txt new file mode 100644 index 00000000000..6dfe69d0045 --- /dev/null +++ b/tests/drivers/timer/nrf_grtc_timer/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(nrf_grtc_timer) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/timer/nrf_grtc_timer/prj.conf b/tests/drivers/timer/nrf_grtc_timer/prj.conf new file mode 100644 index 00000000000..dea03477519 --- /dev/null +++ b/tests/drivers/timer/nrf_grtc_timer/prj.conf @@ -0,0 +1,2 @@ +CONFIG_ZTEST=y +CONFIG_NRF_GRTC_TIMER=y diff --git a/tests/drivers/timer/nrf_grtc_timer/src/main.c b/tests/drivers/timer/nrf_grtc_timer/src/main.c new file mode 100644 index 00000000000..197270cc6a4 --- /dev/null +++ b/tests/drivers/timer/nrf_grtc_timer/src/main.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022, Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include + +#define GRTC_SLEW_TICKS 10 + +ZTEST(nrf_grtc_timer, test_get_ticks) +{ + k_timeout_t t = K_MSEC(1); + + uint64_t exp_ticks = z_nrf_grtc_timer_read() + t.ticks; + int64_t ticks; + + /* Relative 1ms from now timeout converted to GRTC */ + ticks = z_nrf_grtc_timer_get_ticks(t); + zassert_true((ticks >= exp_ticks) && (ticks <= (exp_ticks + GRTC_SLEW_TICKS)), + "Unexpected result %" PRId64 " (expected: %" PRId64 ")", ticks, exp_ticks); + + /* Absolute timeout 1ms in the past */ + t = Z_TIMEOUT_TICKS(Z_TICK_ABS(sys_clock_tick_get() - K_MSEC(1).ticks)); + + exp_ticks = z_nrf_grtc_timer_read() - K_MSEC(1).ticks; + ticks = z_nrf_grtc_timer_get_ticks(t); + zassert_true((ticks >= exp_ticks) && (ticks <= (exp_ticks + GRTC_SLEW_TICKS)), + "Unexpected result %" PRId64 " (expected: %" PRId64 ")", ticks, exp_ticks); + + /* Absolute timeout 10ms in the future */ + t = Z_TIMEOUT_TICKS(Z_TICK_ABS(sys_clock_tick_get() + K_MSEC(10).ticks)); + exp_ticks = z_nrf_grtc_timer_read() + K_MSEC(10).ticks; + ticks = z_nrf_grtc_timer_get_ticks(t); + zassert_true((ticks >= exp_ticks) && (ticks <= (exp_ticks + GRTC_SLEW_TICKS)), + "Unexpected result %" PRId64 " (expected: %" PRId64 ")", ticks, exp_ticks); +} + +ZTEST_SUITE(nrf_grtc_timer, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/drivers/timer/nrf_grtc_timer/testcase.yaml b/tests/drivers/timer/nrf_grtc_timer/testcase.yaml new file mode 100644 index 00000000000..f611a518a70 --- /dev/null +++ b/tests/drivers/timer/nrf_grtc_timer/testcase.yaml @@ -0,0 +1,4 @@ +tests: + drivers.timer.nrf_grtc_timer: + tags: drivers + platform_allow: nrf54l15pdk/nrf54l15/cpuapp From 1e20632b3675e064fe8c53a3e398defa99592c9a Mon Sep 17 00:00:00 2001 From: Magdalena Pastula Date: Mon, 5 Feb 2024 17:04:05 +0100 Subject: [PATCH 0490/2402] tests: drivers: counter: add nRF54L15 overlay Add nRF54L15 overlay for counter_basic_api test. Signed-off-by: Magdalena Pastula --- .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 tests/drivers/counter/counter_basic_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/counter/counter_basic_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay new file mode 100644 index 00000000000..54b47926164 --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay @@ -0,0 +1,34 @@ +&timer00 { + prescaler = <6>; + status = "okay"; +}; + +&timer10 { + prescaler = <4>; + status = "okay"; +}; + +&timer20 { + prescaler = <4>; + status = "okay"; +}; + +&timer21 { + prescaler = <4>; + status = "okay"; +}; + +&timer22 { + prescaler = <4>; + status = "okay"; +}; + +&timer23 { + prescaler = <4>; + status = "okay"; +}; + +&timer24 { + prescaler = <4>; + status = "okay"; +}; From 76f990730f629b011b7c1c34d706fa87bd0585d3 Mon Sep 17 00:00:00 2001 From: Magdalena Pastula Date: Mon, 5 Feb 2024 17:04:53 +0100 Subject: [PATCH 0491/2402] boards: arm: mark counter as supported for nRF54L15 Mark counter as supported for nRF54L15 to allow running counter_basic_api by twister. Signed-off-by: Magdalena Pastula --- boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml index ddcd456fb4a..a6cf750dcc7 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml @@ -12,6 +12,7 @@ toolchain: ram: 256 flash: 1536 supported: + - counter - gpio - i2c - spi From 6cb283d10684346ffab2c8cc3f0cdc9eef280de2 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 11 Mar 2024 13:11:31 +0100 Subject: [PATCH 0492/2402] tests: arch: common: ramfunc: add nrf54h20pdk cpuapp overlays On nRF54H20, we need to configure RAM with execution permissions in order to execute code from it. This patch adds overlays for the nRF54H20 PDK cpuapp cores so that RAM0X region is given execution permissions and so the test runs successfully. Signed-off-by: Gerard Marull-Paretas --- .../ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay diff --git a/tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay b/tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..2deb6756009 --- /dev/null +++ b/tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +&cpuapp_ram0x_region { + perm-execute; +}; From d1bce0efe13b50803f7c65ab4afedb6227d479b0 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Mon, 11 Mar 2024 15:49:22 +0100 Subject: [PATCH 0493/2402] boards: nrf54l15pdk_nrf54l15_cpuapp: enable DCDC mode by default Inductor is present on nRF54L15 PDK so it should be enabled by default. Signed-off-by: Nikodem Kastelik --- boards/nordic/nrf54l15pdk/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 boards/nordic/nrf54l15pdk/Kconfig diff --git a/boards/nordic/nrf54l15pdk/Kconfig b/boards/nordic/nrf54l15pdk/Kconfig new file mode 100644 index 00000000000..638ce57499d --- /dev/null +++ b/boards/nordic/nrf54l15pdk/Kconfig @@ -0,0 +1,13 @@ +# nRF54L15 PDK board configuration + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54L15PDK_NRF54L15_CPUAPP + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_NRF54L_VREG_MAIN_DCDC + default y + +endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP From 5988bc54b0034987bf35d7c533bb169ad33df9fc Mon Sep 17 00:00:00 2001 From: Bjarki Arge Andreasen Date: Thu, 29 Feb 2024 09:43:41 +0100 Subject: [PATCH 0494/2402] MAINTAINERS: Add tomi-font as modem subsys collaborator Add tomi-font as modem subsystem collaborator Signed-off-by: Bjarki Arge Andreasen --- MAINTAINERS.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 136fd0f3ee7..43b516e04df 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2441,6 +2441,8 @@ Modem: status: maintained maintainers: - bjarki-trackunit + collaborators: + - tomi-font files: - subsys/modem/ - include/zephyr/modem/ From 2fc1268c1c02501da3bc8a7f6c987c2d326fbf74 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 21:11:26 +0900 Subject: [PATCH 0495/2402] SDK_VERSION: Use Zephyr SDK 0.16.5-1 This commit updates SDK_VERSION to point to the Zephyr SDK 0.16.5-1 release. Signed-off-by: Stephanos Ioannidis --- SDK_VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/SDK_VERSION b/SDK_VERSION index 19270385eaf..e35e56114f4 100644 --- a/SDK_VERSION +++ b/SDK_VERSION @@ -1 +1 @@ -0.16.5 +0.16.5-1 From 2819c3526a4cd075910e4d4c4a2de775b957d86b Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Sun, 10 Mar 2024 23:36:11 +0900 Subject: [PATCH 0496/2402] ci: doc-build: Use zephyr-runner v2 This commit updates the doc-build workflow to use the new zephyr-runner v2 CI runner deployment. It also installs additional system packages that are not available by default in the zephyr-runner v2. Signed-off-by: Stephanos Ioannidis --- .github/workflows/doc-build.yml | 35 +++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index c67cac82bab..43c7fab056b 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -57,13 +57,29 @@ jobs: if: > github.repository_owner == 'zephyrproject-rtos' && ( needs.doc-file-check.outputs.file_check == 'true' || github.event_name != 'pull_request' ) - runs-on: zephyr-runner-linux-x64-4xlarge + runs-on: + group: zephyr-runner-v2-linux-x64-4xlarge timeout-minutes: 45 concurrency: group: doc-build-html-${{ github.ref }} cancel-in-progress: true steps: + - name: Print cloud service information + run: | + echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" + echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" + echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" + + - name: install-pkgs + run: | + sudo apt-get update + sudo apt-get install -y wget python3-pip git ninja-build graphviz lcov + wget --no-verbose "https://github.com/doxygen/doxygen/releases/download/Release_${DOXYGEN_VERSION//./_}/doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz" + sudo tar xf doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz -C /opt + echo "/opt/doxygen-${DOXYGEN_VERSION}/bin" >> $GITHUB_PATH + echo "${HOME}/.local/bin" >> $GITHUB_PATH + - name: checkout uses: actions/checkout@v4 with: @@ -82,14 +98,6 @@ jobs: git rebase origin/${BASE_REF} git log --graph --oneline HEAD...${PR_HEAD} - - name: install-pkgs - run: | - sudo apt-get update - sudo apt-get install -y ninja-build graphviz lcov - wget --no-verbose "https://github.com/doxygen/doxygen/releases/download/Release_${DOXYGEN_VERSION//./_}/doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz" - tar xf doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz - echo "${PWD}/doxygen-${DOXYGEN_VERSION}/bin" >> $GITHUB_PATH - - name: cache-pip uses: actions/cache@v4 with: @@ -175,7 +183,8 @@ jobs: if: | github.event_name != 'pull_request' && github.repository_owner == 'zephyrproject-rtos' - runs-on: zephyr-runner-linux-x64-4xlarge + runs-on: + group: zephyr-runner-v2-linux-x64-4xlarge container: texlive/texlive:latest timeout-minutes: 60 concurrency: @@ -187,6 +196,12 @@ jobs: run: | git config --global --add safe.directory ${GITHUB_WORKSPACE} + - name: Print cloud service information + run: | + echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" + echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" + echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" + - name: checkout uses: actions/checkout@v4 From 9838633c0e743f7bae876ccd7a7b1c66b97ea97e Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Sun, 10 Mar 2024 23:46:48 +0900 Subject: [PATCH 0497/2402] ci: footprint-tracking: Use zephyr-runner v2 This commit updates the bsim-tests workflow to use the new zephyr-runner v2 CI runner deployment. Signed-off-by: Stephanos Ioannidis --- .github/workflows/footprint-tracking.yml | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/.github/workflows/footprint-tracking.yml b/.github/workflows/footprint-tracking.yml index e028ddd5329..be7969eb05e 100644 --- a/.github/workflows/footprint-tracking.yml +++ b/.github/workflows/footprint-tracking.yml @@ -22,10 +22,11 @@ concurrency: jobs: footprint-tracking: - runs-on: zephyr-runner-linux-x64-4xlarge + runs-on: + group: zephyr-runner-v2-linux-x64-4xlarge if: github.repository_owner == 'zephyrproject-rtos' container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.7 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -40,6 +41,12 @@ jobs: # GitHub comes up with a fundamental fix for this problem. git config --global --add safe.directory ${GITHUB_WORKSPACE} + - name: Print cloud service information + run: | + echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" + echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" + echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" + - name: Update PATH for west run: | echo "$HOME/.local/bin" >> $GITHUB_PATH From c1bd5a613f8a1860b7fb2451e3536b006e51c068 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Sun, 10 Mar 2024 23:56:43 +0900 Subject: [PATCH 0498/2402] ci: codecov: Run on all zephyrproject-rtos organisation repositories This commit updates the codecov workflow to run on all forks under the zephyrproject-rtos organisation. The purpose of this is mainly to simplify the process of testing of this workflow under the zephyr-testing repository. Signed-off-by: Stephanos Ioannidis --- .github/workflows/codecov.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 7a9f6fae6c4..fdaccc8ad8e 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -10,7 +10,7 @@ concurrency: jobs: codecov: - if: github.repository == 'zephyrproject-rtos/zephyr' + if: github.repository_owner == 'zephyrproject-rtos' runs-on: zephyr-runner-linux-x64-4xlarge container: image: ghcr.io/zephyrproject-rtos/ci:v0.26.7 From 354e290a2322f41f8cc771eced55df9e366592b4 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 00:04:58 +0900 Subject: [PATCH 0499/2402] ci: codecov: Use zephyr-runner v2 This commit updates the codecov workflow to use the new zephyr-runner v2 CI runner deployment. It also updates the workflow to use the `ci-repo-cache` Docker image, which includes the Zephyr repository cache, because the node level repository cache is no longer available in the zephyr-runner v2. Signed-off-by: Stephanos Ioannidis --- .github/workflows/codecov.yaml | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index fdaccc8ad8e..d44bd8c251c 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -11,12 +11,11 @@ concurrency: jobs: codecov: if: github.repository_owner == 'zephyrproject-rtos' - runs-on: zephyr-runner-linux-x64-4xlarge + runs-on: + group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.7 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 options: '--entrypoint /bin/bash' - volumes: - - /repo-cache/zephyrproject:/github/cache/zephyrproject strategy: fail-fast: false matrix: @@ -39,6 +38,12 @@ jobs: # GitHub comes up with a fundamental fix for this problem. git config --global --add safe.directory ${GITHUB_WORKSPACE} + - name: Print cloud service information + run: | + echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" + echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" + echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" + - name: Update PATH for west run: | echo "$HOME/.local/bin" >> $GITHUB_PATH @@ -46,7 +51,7 @@ jobs: - name: Clone cached Zephyr repository continue-on-error: true run: | - git clone --shared /github/cache/zephyrproject/zephyr . + git clone --shared /repo-cache/zephyrproject/zephyr . git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: checkout From 36b0b101d49f4c1fc0125cf6232d5ecb5ab1cb6c Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 00:14:52 +0900 Subject: [PATCH 0500/2402] ci: codecov: Store ccache data in node cache This commit updates the codecov workflow to store ccache data in the zephyr-runner v2 node cache. Signed-off-by: Stephanos Ioannidis --- .github/workflows/codecov.yaml | 36 ++++++++++------------------------ 1 file changed, 10 insertions(+), 26 deletions(-) diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index d44bd8c251c..aa24027a599 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -29,6 +29,8 @@ jobs: normalized: 'qemu_x86' - platform: 'unit_testing' normalized: 'unit_testing' + env: + CCACHE_DIR: /node-cache/ccache-zephyr steps: - name: Apply container owner mismatch workaround run: | @@ -72,30 +74,12 @@ jobs: echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV - - name: Prepare ccache keys - id: ccache_cache_prop - shell: cmake -P {0} - run: | - string(REPLACE "/" "_" repo ${{github.repository}}) - string(REPLACE "-" "_" repo2 ${repo}) - file(APPEND $ENV{GITHUB_OUTPUT} "repo=${repo2}\n") - - - name: use cache - id: cache-ccache - uses: zephyrproject-rtos/action-s3-cache@v1.2.0 - with: - key: ${{ steps.ccache_cache_prop.outputs.repo }}-${{github.event_name}}-${{matrix.platform}}-codecov-ccache - path: /github/home/.cache/ccache - aws-s3-bucket: ccache.zephyrproject.org - aws-access-key-id: ${{ vars.AWS_CCACHE_ACCESS_KEY_ID }} - aws-secret-access-key: ${{ secrets.AWS_CCACHE_SECRET_ACCESS_KEY }} - aws-region: us-east-2 - - - name: ccache stats initial + - name: Set up ccache run: | - mkdir -p /github/home/.cache - test -d github/home/.cache/ccache && mv github/home/.cache/ccache /github/home/.cache/ccache - ccache -M 10G -s + mkdir -p ${CCACHE_DIR} + ccache -M 10G + ccache -p + ccache -z -s -vv - name: Run Tests with Twister (Push) continue-on-error: true @@ -108,10 +92,10 @@ jobs: ls -la ./scripts/twister -i --force-color -N -v --filter runnable -p ${{ matrix.platform }} --coverage -T tests --coverage-tool gcovr -xCONFIG_TEST_EXTRA_STACK_SIZE=4096 -e nano - - name: ccache stats post + - name: Print ccache stats + if: always() run: | - ccache -s - ccache -p + ccache -s -vv - name: Rename coverage files if: always() From b57f1b5a159a284783342cc65f8a0e089d62357d Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 00:16:02 +0900 Subject: [PATCH 0501/2402] ci: codecov: Use Redis remote storage for ccache This commit updates the codecov workflow to, when available, use Redis remote storage backend for the ccache compilation cache data. The Redis cache server is hosted in the Kubernetes cluster in which the zephyr-runner pods run -- the Redis remote storage backend will be ignored if the server is unavailable. Signed-off-by: Stephanos Ioannidis --- .github/workflows/codecov.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index aa24027a599..88890767df5 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -31,6 +31,7 @@ jobs: normalized: 'unit_testing' env: CCACHE_DIR: /node-cache/ccache-zephyr + CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" steps: - name: Apply container owner mismatch workaround run: | From ab9f6b456b6daa472a6430bd9b80f28326cb8cc9 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 00:18:02 +0900 Subject: [PATCH 0502/2402] ci: codecov: Add `--specs` to ccache ignore option list This commit adds the compiler `--specs=*` flag to the ccache ignore option list because ccache is unable to resolve the toolchain-provided specs file path and will consider source files to be uncacheable if it is unable to read the specified specs file. Note that adding `--specs=*` to the ignore option list is not a problem because it is unlikely for the content of the toolchain libc spec file to change without the compiler executable itself changing. Signed-off-by: Stephanos Ioannidis --- .github/workflows/codecov.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 88890767df5..aa29a4a529f 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -32,6 +32,8 @@ jobs: env: CCACHE_DIR: /node-cache/ccache-zephyr CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" + # `--specs` is ignored because ccache is unable to resovle the toolchain specs file path. + CCACHE_IGNOREOPTIONS: '--specs=*' steps: - name: Apply container owner mismatch workaround run: | From a636c52b6af5c8a09be408b0e961e919f61cd421 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 00:19:07 +0900 Subject: [PATCH 0503/2402] ci: codecov: Prioritise remote Redis cache storage This commit updates the codecov workflow such that ccache only uses remote Redis cache storage when available. The purpose of this to reduce the individual runner local disk IOPS requirement; thereby, reducing the overall load on the SAN. Signed-off-by: Stephanos Ioannidis --- .github/workflows/codecov.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index aa29a4a529f..d586dd8d63c 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -32,6 +32,7 @@ jobs: env: CCACHE_DIR: /node-cache/ccache-zephyr CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" + CCACHE_REMOTE_ONLY: "true" # `--specs` is ignored because ccache is unable to resovle the toolchain specs file path. CCACHE_IGNOREOPTIONS: '--specs=*' steps: From 550bb4e4a6de5c33c481a5cee84140aed2db37d0 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 17:08:55 +0900 Subject: [PATCH 0504/2402] ci: codecov: Set twister timeout multiplier to 2 This commit sets the codecov workflow twister timeout multiplier to 2, which effectively increases the default test timeout from 60 to 120 seconds, because the new cost-effective Zephyr runners may take longer to execute tests and the default timeout is not sufficient for some tests to complete. Signed-off-by: Stephanos Ioannidis --- .github/workflows/codecov.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index d586dd8d63c..47b3785a47c 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -94,7 +94,10 @@ jobs: pip3 install gcovr==6.0 ./scripts/twister -E ${{matrix.normalized}}-testplan.json ls -la - ./scripts/twister -i --force-color -N -v --filter runnable -p ${{ matrix.platform }} --coverage -T tests --coverage-tool gcovr -xCONFIG_TEST_EXTRA_STACK_SIZE=4096 -e nano + ./scripts/twister \ + -i --force-color -N -v --filter runnable -p ${{ matrix.platform }} --coverage \ + -T tests --coverage-tool gcovr -xCONFIG_TEST_EXTRA_STACK_SIZE=4096 -e nano \ + --timeout-multiplier 2 - name: Print ccache stats if: always() From 64ca699fc89ced6876e6d5c29e7ae6f724606179 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 00:27:42 +0900 Subject: [PATCH 0505/2402] ci: clang: Use zephyr-runner v2 This commit updates the clang workflow to use the new zephyr-runner v2 CI runner deployment. It also updates the workflow to use the `ci-repo-cache` Docker image, which includes the Zephyr repository cache, because the node level repository cache is no longer available in the zephyr-runner v2. Signed-off-by: Stephanos Ioannidis --- .github/workflows/clang.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index 17fbc1c72bd..e6a19a6a317 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -9,12 +9,11 @@ concurrency: jobs: clang-build: if: github.repository_owner == 'zephyrproject-rtos' - runs-on: zephyr-runner-linux-x64-4xlarge + runs-on: + group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.7 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 options: '--entrypoint /bin/bash' - volumes: - - /repo-cache/zephyrproject:/github/cache/zephyrproject strategy: fail-fast: false matrix: @@ -34,10 +33,16 @@ jobs: # GitHub comes up with a fundamental fix for this problem. git config --global --add safe.directory ${GITHUB_WORKSPACE} + - name: Print cloud service information + run: | + echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" + echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" + echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" + - name: Clone cached Zephyr repository continue-on-error: true run: | - git clone --shared /github/cache/zephyrproject/zephyr . + git clone --shared /repo-cache/zephyrproject/zephyr . git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout @@ -63,7 +68,7 @@ jobs: # So first retry to update, if that does not work, remove all modules # and start over. (Workaround until we implement more robust module # west caching). - west update --path-cache /github/cache/zephyrproject 2>&1 1> west.log || west update --path-cache /github/cache/zephyrproject 2>&1 1> west2.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /github/cache/zephyrproject) + west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west2.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject) echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV From cd83f0724b4b554a62eb2025c10a55714247b1fe Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 00:31:32 +0900 Subject: [PATCH 0506/2402] ci: clang: Store ccache data in node cache This commit updates the clang workflow to store ccache data in the zephyr-runner v2 node cache. Signed-off-by: Stephanos Ioannidis --- .github/workflows/clang.yaml | 36 +++++++++--------------------------- 1 file changed, 9 insertions(+), 27 deletions(-) diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index e6a19a6a317..2884fcceb26 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -19,6 +19,7 @@ jobs: matrix: platform: ["native_sim"] env: + CCACHE_DIR: /node-cache/ccache-zephyr LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16 COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} BASE_REF: ${{ github.base_ref }} @@ -79,31 +80,12 @@ jobs: gcc --version ls -la - - name: Prepare ccache timestamp/data - id: ccache_cache_timestamp - shell: cmake -P {0} + - name: Set up ccache run: | - string(TIMESTAMP current_date "%Y-%m-%d-%H;%M;%S" UTC) - string(REPLACE "/" "_" repo ${{github.repository}}) - string(REPLACE "-" "_" repo2 ${repo}) - file(APPEND $ENV{GITHUB_OUTPUT} "repo=${repo2}\n") - - - name: use cache - id: cache-ccache - uses: zephyrproject-rtos/action-s3-cache@v1.2.0 - with: - key: ${{ steps.ccache_cache_timestamp.outputs.repo }}-${{ github.ref_name }}-clang-${{ matrix.platform }}-ccache - path: /github/home/.cache/ccache - aws-s3-bucket: ccache.zephyrproject.org - aws-access-key-id: ${{ vars.AWS_CCACHE_ACCESS_KEY_ID }} - aws-secret-access-key: ${{ secrets.AWS_CCACHE_SECRET_ACCESS_KEY }} - aws-region: us-east-2 - - - name: ccache stats initial - run: | - mkdir -p /github/home/.cache - test -d github/home/.cache/ccache && rm -rf /github/home/.cache/ccache && mv github/home/.cache/ccache /github/home/.cache/ccache - ccache -M 10G -s + mkdir -p ${CCACHE_DIR} + ccache -M 10G + ccache -p + ccache -z -s -vv - name: Run Tests with Twister id: twister @@ -124,10 +106,10 @@ jobs: echo "report_needed=0" >> $GITHUB_OUTPUT fi - - name: ccache stats post + - name: Print ccache stats + if: always() run: | - ccache -s - ccache -p + ccache -s -vv - name: Upload Unit Test Results if: always() && steps.twister.outputs.report_needed != 0 From 4a2884c652228f99028e96c59d254868cc74f690 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 00:32:35 +0900 Subject: [PATCH 0507/2402] ci: clang: Use Redis remote storage for ccache This commit updates the clang workflow to, when available, use Redis remote storage backend for the ccache compilation cache data. The Redis cache server is hosted in the Kubernetes cluster in which the zephyr-runner pods run -- the Redis remote storage backend will be ignored if the server is unavailable. Signed-off-by: Stephanos Ioannidis --- .github/workflows/clang.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index 2884fcceb26..ac8adaeeb0c 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -20,6 +20,7 @@ jobs: platform: ["native_sim"] env: CCACHE_DIR: /node-cache/ccache-zephyr + CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16 COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} BASE_REF: ${{ github.base_ref }} From 95e7eb31e63796e255c3e17b0c7db69300d21b4f Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 00:33:31 +0900 Subject: [PATCH 0508/2402] ci: clang: Prioritise remote Redis cache storage This commit updates the clang workflow such that ccache only uses remote Redis cache storage when available. The purpose of this to reduce the individual runner local disk IOPS requirement; thereby, reducing the overall load on the SAN. Signed-off-by: Stephanos Ioannidis --- .github/workflows/clang.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index ac8adaeeb0c..41c07278edb 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -21,6 +21,7 @@ jobs: env: CCACHE_DIR: /node-cache/ccache-zephyr CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" + CCACHE_REMOTE_ONLY: "true" LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16 COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} BASE_REF: ${{ github.base_ref }} From eba732a7ebee60965f8b71c83558aad5ec3b0fb4 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 21:16:17 +0900 Subject: [PATCH 0509/2402] ci: errno: Switch to CI image v0.26.9 This commit updates the errno workflow to use the CI image v0.26.9, in order to pull in the Zephyr SDK 0.16.5-1 release and keep the image and SDK versions in sync with the rest of the CI workflows. Signed-off-by: Stephanos Ioannidis --- .github/workflows/errno.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/errno.yml b/.github/workflows/errno.yml index e6bea7dca4a..9e5589aeb0a 100644 --- a/.github/workflows/errno.yml +++ b/.github/workflows/errno.yml @@ -10,7 +10,7 @@ jobs: check-errno: runs-on: ubuntu-22.04 container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.7 + image: ghcr.io/zephyrproject-rtos/ci:v0.26.9 steps: - name: Apply container owner mismatch workaround From 121896c0cf69d3ab0c7d348a4f6f0a6d30a3abfd Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Mon, 11 Mar 2024 21:19:14 +0900 Subject: [PATCH 0510/2402] ci: twister_tests_blackbox: Switch to CI image v0.26.9 This commit updates the twister_tests_blackbox workflow to use the CI image v0.26.9, in order to pull in the Zephyr SDK 0.16.5-1 release and keep the image and SDK versions in sync with the rest of the CI workflows. Signed-off-by: Stephanos Ioannidis --- .github/workflows/twister_tests_blackbox.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index 78af60ab32c..131d773478a 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -24,7 +24,7 @@ jobs: python-version: [3.8, 3.9, '3.10', '3.11', '3.12'] os: [ubuntu-22.04] container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.7 + image: ghcr.io/zephyrproject-rtos/ci:v0.26.9 steps: - name: Apply Container Owner Mismatch Workaround From 4d2bc5f5e86bf1dc5a03e793189da7dac7eeff64 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Thu, 22 Feb 2024 14:28:50 +0100 Subject: [PATCH 0511/2402] samples: Bluetooth: Add stereo support for broadcast audio sink The broadcast audio sink now supports stereo if CONFIG_TARGET_BROADCAST_CHANNEL=3 (LEFT | RIGHT). It parses the BASE to find a set of BIS (1 or 2) that contain the channel allocation from CONFIG_TARGET_BROADCAST_CHANNEL. Signed-off-by: Emil Gydesen --- .../bluetooth/broadcast_audio_sink/Kconfig | 10 +- .../bluetooth/broadcast_audio_sink/src/main.c | 439 +++++++++++++----- 2 files changed, 336 insertions(+), 113 deletions(-) diff --git a/samples/bluetooth/broadcast_audio_sink/Kconfig b/samples/bluetooth/broadcast_audio_sink/Kconfig index 72a31d69676..7faffd0716a 100644 --- a/samples/bluetooth/broadcast_audio_sink/Kconfig +++ b/samples/bluetooth/broadcast_audio_sink/Kconfig @@ -35,6 +35,14 @@ config TARGET_BROADCAST_NAME Name of target broadcast device. If not empty string, sink device will only listen to the specified broadcast source. Not case sensitive. +config MAX_CODEC_FRAMES_PER_SDU + int "The maximum number of codec frame per SDU supported" + default 1 + range 1 255 + help + Maximum number of codec frames per SDU supported by this device. Increasing this value + allows support for a greater variaty of broadcasts, but also increases memory usage. + config ENABLE_LC3 bool "Enable the LC3 codec" # By default let's enable it in the platforms we know are capable of supporting it @@ -64,7 +72,7 @@ config USE_SPECIFIC_BROADCAST_CHANNEL config TARGET_BROADCAST_CHANNEL int "Broadcast Channel Audio Location to sync to" - range 0 2 + range 0 3 default 1 depends on USE_SPECIFIC_BROADCAST_CHANNEL help diff --git a/samples/bluetooth/broadcast_audio_sink/src/main.c b/samples/bluetooth/broadcast_audio_sink/src/main.c index 979da4f243b..562b4cc3be4 100644 --- a/samples/bluetooth/broadcast_audio_sink/src/main.c +++ b/samples/bluetooth/broadcast_audio_sink/src/main.c @@ -112,7 +112,8 @@ static struct bt_le_ext_adv *ext_adv; static const struct bt_audio_codec_cap codec_cap = BT_AUDIO_CODEC_CAP_LC3( BT_AUDIO_CODEC_CAP_FREQ_16KHZ | BT_AUDIO_CODEC_CAP_FREQ_24KHZ, - BT_AUDIO_CODEC_CAP_DURATION_10, BT_AUDIO_CODEC_CAP_CHAN_COUNT_SUPPORT(1), 40u, 60u, 1u, + BT_AUDIO_CODEC_CAP_DURATION_10, BT_AUDIO_CODEC_CAP_CHAN_COUNT_SUPPORT(1), 40u, 60u, + CONFIG_MAX_CODEC_FRAMES_PER_SDU, (BT_AUDIO_CONTEXT_TYPE_CONVERSATIONAL | BT_AUDIO_CONTEXT_TYPE_MEDIA)); /* Create a mask for the maximum BIS we can sync to using the number of streams @@ -132,53 +133,18 @@ static int stop_adv(void); RING_BUF_DECLARE(usb_ring_buf, USB_RING_BUF_SIZE); NET_BUF_POOL_DEFINE(usb_tx_buf_pool, USB_ENQUEUE_COUNT, USB_STEREO_SAMPLE_SIZE, 0, net_buf_destroy); -static void mix_mono_to_stereo(int16_t audio_buf[LC3_MAX_NUM_SAMPLES_STEREO]); static void add_to_usb_ring_buf(const int16_t audio_buf[LC3_MAX_NUM_SAMPLES_STEREO]); #endif /* defined(CONFIG_USB_DEVICE_AUDIO) */ #if defined(CONFIG_LIBLC3) static K_SEM_DEFINE(lc3_decoder_sem, 0, 1); -static bool do_lc3_decode(struct broadcast_sink_stream *sink_stream, - int16_t audio_buf[LC3_MAX_NUM_SAMPLES_STEREO]); +static void do_lc3_decode(lc3_decoder_t decoder, const void *in_data, uint8_t octets_per_frame, + int16_t out_data[LC3_MAX_NUM_SAMPLES_MONO]); static void lc3_decoder_thread(void *arg1, void *arg2, void *arg3); K_THREAD_DEFINE(decoder_tid, LC3_ENCODER_STACK_SIZE, lc3_decoder_thread, NULL, NULL, NULL, LC3_ENCODER_PRIORITY, 0, -1); -/* Consumer thread of the decoded stream data */ -static void lc3_decoder_thread(void *arg1, void *arg2, void *arg3) -{ - while (true) { - static int16_t lc3_audio_buf[LC3_MAX_NUM_SAMPLES_STEREO]; - - k_sem_take(&lc3_decoder_sem, K_FOREVER); -#if defined(CONFIG_USB_DEVICE_AUDIO) - - /* For now we only handle one BIS, so always only decode the first element - * in streams. - */ - struct broadcast_sink_stream *stream_for_usb = &streams[0]; - - /* Not enough space to store data */ - if (ring_buf_space_get(&usb_ring_buf) < sizeof(lc3_audio_buf)) { - continue; - } - - /* lc3_audio_buf will be filled with the last decoded value, so e.g. if the stream - * contains both left and right, the lc3_audio_buf will always contain right. - */ - if (do_lc3_decode(stream_for_usb, lc3_audio_buf)) { - mix_mono_to_stereo(lc3_audio_buf); - add_to_usb_ring_buf(lc3_audio_buf); - } -#else - for (size_t i = 0; i < ARRAY_SIZE(streams); i++) { - (void)do_lc3_decode(&streams[i], lc3_audio_buf); - } -#endif /* #if defined(CONFIG_USB_DEVICE_AUDIO) */ - } -} - static size_t get_chan_cnt(enum bt_audio_location chan_allocation) { size_t cnt = 0U; @@ -195,61 +161,171 @@ static size_t get_chan_cnt(enum bt_audio_location chan_allocation) return cnt; } -/** Decode LC3 data on a stream and returns true if successful */ -static bool do_lc3_decode(struct broadcast_sink_stream *sink_stream, - int16_t audio_buf[LC3_MAX_NUM_SAMPLES_STEREO]) +/* Consumer thread of the decoded stream data */ +static void lc3_decoder_thread(void *arg1, void *arg2, void *arg3) { - const uint8_t frames_blocks_per_sdu = sink_stream->lc3_frames_blocks_per_sdu; - const uint16_t octets_per_frame = sink_stream->lc3_octets_per_frame; - uint16_t frames_per_block; - struct net_buf *buf; + while (true) { +#if defined(CONFIG_USB_DEVICE_AUDIO) + static int16_t right_frames[CONFIG_MAX_CODEC_FRAMES_PER_SDU] + [LC3_MAX_NUM_SAMPLES_MONO]; + static int16_t left_frames[CONFIG_MAX_CODEC_FRAMES_PER_SDU] + [LC3_MAX_NUM_SAMPLES_MONO]; + size_t right_frames_cnt = 0; + size_t left_frames_cnt = 0; + + memset(right_frames, 0, sizeof(right_frames)); + memset(left_frames, 0, sizeof(left_frames)); +#else + static int16_t lc3_audio_buf[LC3_MAX_NUM_SAMPLES_MONO]; +#endif /* CONFIG_USB_DEVICE_AUDIO */ - k_mutex_lock(&sink_stream->lc3_decoder_mutex, K_FOREVER); + k_sem_take(&lc3_decoder_sem, K_FOREVER); - if (sink_stream->in_buf == NULL) { - k_mutex_unlock(&sink_stream->lc3_decoder_mutex); + for (size_t i = 0; i < ARRAY_SIZE(streams); i++) { + struct broadcast_sink_stream *stream = &streams[i]; + const uint8_t frames_blocks_per_sdu = stream->lc3_frames_blocks_per_sdu; + const uint16_t octets_per_frame = stream->lc3_octets_per_frame; + uint16_t frames_per_block; + struct net_buf *buf; - return false; - } + k_mutex_lock(&stream->lc3_decoder_mutex, K_FOREVER); - buf = net_buf_ref(sink_stream->in_buf); - net_buf_unref(sink_stream->in_buf); - sink_stream->in_buf = NULL; - k_mutex_unlock(&sink_stream->lc3_decoder_mutex); + if (stream->in_buf == NULL) { + k_mutex_unlock(&stream->lc3_decoder_mutex); - frames_per_block = get_chan_cnt(sink_stream->chan_allocation); - if (buf->len != (frames_per_block * octets_per_frame * frames_blocks_per_sdu)) { - printk("Expected %u frame blocks with %u frames of size %u, but length is %u\n", - frames_blocks_per_sdu, frames_per_block, octets_per_frame, buf->len); + continue; + } - net_buf_unref(buf); + buf = net_buf_ref(stream->in_buf); + net_buf_unref(stream->in_buf); + stream->in_buf = NULL; + k_mutex_unlock(&stream->lc3_decoder_mutex); - return false; - } + frames_per_block = get_chan_cnt(stream->chan_allocation); + if (buf->len != + (frames_per_block * octets_per_frame * frames_blocks_per_sdu)) { + printk("Expected %u frame blocks with %u frames of size %u, but " + "length is %u\n", + frames_blocks_per_sdu, frames_per_block, octets_per_frame, + buf->len); + + net_buf_unref(buf); - for (uint8_t i = 0U; i < frames_blocks_per_sdu; i++) { - for (uint16_t j = 0U; j < frames_per_block; j++) { - const void *data = net_buf_pull_mem(buf, octets_per_frame); - int err; + continue; + } - err = lc3_decode(sink_stream->lc3_decoder, data, octets_per_frame, - LC3_PCM_FORMAT_S16, audio_buf, 1); +#if defined(CONFIG_USB_DEVICE_AUDIO) + const bool has_left = + (stream->chan_allocation & BT_AUDIO_LOCATION_FRONT_LEFT) != 0; + const bool has_right = + (stream->chan_allocation & BT_AUDIO_LOCATION_FRONT_RIGHT) != 0; + const bool is_mono = + stream->chan_allocation == BT_AUDIO_LOCATION_MONO_AUDIO; + + /* Split the SDU into frames*/ + for (uint8_t i = 0U; i < frames_blocks_per_sdu; i++) { + for (uint16_t j = 0U; j < frames_per_block; j++) { + const bool is_left = j == 0 && has_left; + const bool is_right = + has_right && (j == 0 || (j == 1 && has_left)); + const void *data = net_buf_pull_mem(buf, octets_per_frame); + int16_t *out_frame; + + if (is_left) { + out_frame = left_frames[left_frames_cnt++]; + } else if (is_right) { + out_frame = right_frames[right_frames_cnt++]; + } else if (is_mono) { + /* Use left as mono*/ + out_frame = left_frames[left_frames_cnt++]; + } else { + /* unused channel */ + break; + } + + do_lc3_decode(stream->lc3_decoder, data, octets_per_frame, + out_frame); + } + } +#else + /* Dummy behavior: Decode and discard data */ + for (uint8_t i = 0U; i < frames_blocks_per_sdu; i++) { + for (uint16_t j = 0U; j < frames_per_block; j++) { + const void *data = net_buf_pull_mem(buf, octets_per_frame); - if (err == 1) { - printk(" decoder performed PLC\n"); - } else if (err < 0) { - printk(" decoder failed - wrong parameters? (err = %d)\n", err); + do_lc3_decode(stream->lc3_decoder, data, octets_per_frame, + lc3_audio_buf); + } + } +#endif /* CONFIG_USB_DEVICE_AUDIO */ - net_buf_unref(buf); + net_buf_unref(buf); + } - return false; +#if defined(CONFIG_USB_DEVICE_AUDIO) + const bool is_left_only = right_frames_cnt == 0U; + const bool is_right_only = left_frames_cnt == 0U; + + if (!is_left_only && !is_right_only && left_frames_cnt != right_frames_cnt) { + printk("Mismatch between number of left (%zu) and right (%zu) frames, " + "discard SDU", + left_frames_cnt, right_frames_cnt); + continue; + } + + /* Send frames to USB - If we only have a single channel we mix it to stereo */ + for (size_t i = 0U; i < MAX(left_frames_cnt, right_frames_cnt); i++) { + const bool is_single_channel = is_left_only || is_right_only; + static int16_t stereo_frame[LC3_MAX_NUM_SAMPLES_STEREO]; + int16_t *right_frame = right_frames[i]; + int16_t *left_frame = left_frames[i]; + + /* Not enough space to store data */ + if (ring_buf_space_get(&usb_ring_buf) < sizeof(stereo_frame)) { + break; + } + + memset(stereo_frame, 0, sizeof(stereo_frame)); + + /* Generate the stereo frame + * + * If we only have single channel then that is always stored in the + * left_frame, and we mix that to stereo + */ + for (int j = 0; j < LC3_MAX_NUM_SAMPLES_MONO; j++) { + if (is_single_channel) { + /* Mix to stereo */ + if (is_left_only) { + stereo_frame[j * 2] = left_frame[j]; + stereo_frame[j * 2 + 1] = left_frame[j]; + } else if (is_right_only) { + stereo_frame[j * 2] = right_frame[j]; + stereo_frame[j * 2 + 1] = right_frame[j]; + } + } else { + stereo_frame[j * 2] = left_frame[j]; + stereo_frame[j * 2 + 1] = right_frame[j]; + } } + + add_to_usb_ring_buf(stereo_frame); } +#endif /* CONFIG_USB_DEVICE_AUDIO */ } +} - net_buf_unref(buf); +/** Decode LC3 data on a stream and returns true if successful */ +static void do_lc3_decode(lc3_decoder_t decoder, const void *in_data, uint8_t octets_per_frame, + int16_t out_data[LC3_MAX_NUM_SAMPLES_MONO]) +{ + int err; - return true; + err = lc3_decode(decoder, in_data, octets_per_frame, LC3_PCM_FORMAT_S16, out_data, 1); + if (err == 1) { + printk(" decoder performed PLC\n"); + } else if (err < 0) { + printk(" decoder failed - wrong parameters? (err = %d)\n", err); + } } static int lc3_enable(struct broadcast_sink_stream *sink_stream) @@ -342,21 +418,6 @@ static int lc3_enable(struct broadcast_sink_stream *sink_stream) #endif /* defined(CONFIG_LIBLC3) */ #if defined(CONFIG_USB_DEVICE_AUDIO) -/* Duplicate the audio from one channel and put it in both channels */ -static void mix_mono_to_stereo(int16_t audio_buf[LC3_MAX_NUM_SAMPLES_STEREO]) -{ - /* Interleave the channel sample inline - * Take the first LC3_MAX_NUM_SAMPLES_MONO samples from audio_buf and mix it to - * interleaved stereo, so that 012345 becomes 001122334455 - */ - for (int i = LC3_MAX_NUM_SAMPLES_MONO - 1; i >= 0; i--) { - const int16_t sample = audio_buf[i]; - - audio_buf[i * 2] = sample; - audio_buf[i * 2 + 1] = sample; - } -} - /* Move the LC3 data to the USB ring buffer */ static void add_to_usb_ring_buf(const int16_t audio_buf[LC3_MAX_NUM_SAMPLES_STEREO]) { @@ -508,67 +569,221 @@ static struct bt_bap_stream_ops stream_ops = { }; #if defined(CONFIG_TARGET_BROADCAST_CHANNEL) +struct find_valid_bis_data { + struct { + uint8_t index; + enum bt_audio_location chan_allocation; + } bis[BT_ISO_BIS_INDEX_MAX]; + + uint8_t cnt; +}; + +/** + * This is called for each BIS in a subgroup + * + * It returns `false` if the current BIS contains all of the channels we are looking for, + * or if it does not contain any and we are looking for BT_AUDIO_LOCATION_MONO_AUDIO. This stops + * the iteration of the remaining BIS in the subgroup. + * + * It returns `true` if the BIS either contains none or some of the channels we are looking for. + * If it contains some, then that is being stored in the user_data, so that the calling function + * can check if a combination of the BIS satisfy the channel allocations we want. + */ static bool find_valid_bis_cb(const struct bt_bap_base_subgroup_bis *bis, void *user_data) { - int err; + struct find_valid_bis_data *data = user_data; struct bt_audio_codec_cfg codec_cfg = {0}; enum bt_audio_location chan_allocation; - uint8_t *bis_index = user_data; + int err; err = bt_bap_base_subgroup_bis_codec_to_codec_cfg(bis, &codec_cfg); if (err != 0) { - printk("Could not find codec configuration (err=%d)\n", err); + printk("Could not get codec configuration for BIS: %d\n", err); return true; } err = bt_audio_codec_cfg_get_chan_allocation(&codec_cfg, &chan_allocation); if (err != 0) { - printk("Could not find channel allocation (err=%d)\n", err); - if (err == -ENODATA && strlen(CONFIG_TARGET_BROADCAST_NAME) > 0U) { + printk("Could not find channel allocation for BIS: %d\n", err); + + /* Absence of channel allocation is implicitly mono as per the BAP spec */ + if (CONFIG_TARGET_BROADCAST_CHANNEL == BT_AUDIO_LOCATION_MONO_AUDIO) { + data->bis[0].index = bis->index; + data->bis[0].chan_allocation = chan_allocation; + data->cnt = 1; + + return false; + } else if (err == -ENODATA && strlen(CONFIG_TARGET_BROADCAST_NAME) > 0U) { /* Accept no channel allocation data available * if TARGET_BROADCAST_NAME defined. Use current index. */ - *bis_index = bis->index; + data->bis[0].index = bis->index; + data->bis[0].chan_allocation = chan_allocation; + data->cnt = 1; return false; } + } else { + if ((chan_allocation & CONFIG_TARGET_BROADCAST_CHANNEL) == + CONFIG_TARGET_BROADCAST_CHANNEL) { + /* Found single BIS with all channels we want - keep as only and stop + * parsing + */ + data->bis[0].index = bis->index; + data->bis[0].chan_allocation = chan_allocation; + data->cnt = 1; - return true; + return false; + } else if ((chan_allocation & CONFIG_TARGET_BROADCAST_CHANNEL) != 0) { + /* BIS contains part of what we are looking for - Store and see if there are + * other BIS that may fill the gaps + */ + data->bis[data->cnt].index = bis->index; + data->bis[data->cnt].chan_allocation = chan_allocation; + data->cnt++; + } } - if ((CONFIG_TARGET_BROADCAST_CHANNEL == BT_AUDIO_LOCATION_MONO_AUDIO && - chan_allocation == BT_AUDIO_LOCATION_MONO_AUDIO) || - chan_allocation & CONFIG_TARGET_BROADCAST_CHANNEL) { - *bis_index = bis->index; + return true; +} + +/** + * This function searches all the BIS in a subgroup for a set of BIS indexes that satisfy + * CONFIG_TARGET_BROADCAST_CHANNEL + * + * Returns `true` if the right channels were found, otherwise `false`. + */ +static bool find_valid_bis_in_subgroup_bis(const struct bt_bap_base_subgroup *subgroup, + uint32_t *bis_indexes) +{ + struct find_valid_bis_data data = {0}; + int err; - return false; + err = bt_bap_base_subgroup_foreach_bis(subgroup, find_valid_bis_cb, &data); + if (err == -ECANCELED) { + /* We found what we are looking for in a single BIS */ + + *bis_indexes = BIT(data.bis[0].index); + + return true; + } else if (err == 0) { + /* We are finished parsing all BIS - Try to find a combination that satisfy our + * channel allocation. For simplicity this is using a greedy approach, rather than + * an optimal one. + */ + enum bt_audio_location chan_allocation = BT_AUDIO_LOCATION_MONO_AUDIO; + *bis_indexes = 0; + + for (uint8_t i = 0U; i < data.cnt; i++) { + chan_allocation |= data.bis[i].chan_allocation; + *bis_indexes |= BIT(data.bis[i].index); + + if ((chan_allocation & CONFIG_TARGET_BROADCAST_CHANNEL) == + CONFIG_TARGET_BROADCAST_CHANNEL) { + return true; + } + } } - return true; + /* Some error occurred or we did not find expected channel allocation */ + return false; } +/** + * Called for each subgroup in the BASE. Will populate the 32-bit bitfield of BIS indexes if the + * subgroup contains it. + * + * The channel allocation may + * - Not exist at all, implicitly meaning BT_AUDIO_LOCATION_MONO_AUDIO + * - Exist only in the subgroup codec configuration + * - Exist only in the BIS codec configuration + * - Exist in both the subgroup and BIS codec configuration, in which case, the BIS codec + * configuration overwrites the subgroup values + * + * This function returns `true` if the subgroup does not support the channels in + * CONFIG_TARGET_BROADCAST_CHANNEL which makes it iterate over the next subgroup, and returns + * `false` if this subgroup satisfies our CONFIG_TARGET_BROADCAST_CHANNEL. + */ static bool find_valid_bis_in_subgroup_cb(const struct bt_bap_base_subgroup *subgroup, void *user_data) { - return bt_bap_base_subgroup_foreach_bis(subgroup, find_valid_bis_cb, user_data) - == -ECANCELED ? false : true; + enum bt_audio_location chan_allocation; + struct bt_audio_codec_cfg codec_cfg; + uint32_t *bis_indexes = user_data; + int err; + + /* We only want indexes from a single subgroup, so reset between each of them*/ + *bis_indexes = 0U; + + err = bt_bap_base_subgroup_codec_to_codec_cfg(subgroup, &codec_cfg); + if (err != 0) { + printk("Could not get codec configuration: %d\n", err); + + return true; + } + + err = bt_audio_codec_cfg_get_chan_allocation(&codec_cfg, &chan_allocation); + if (err != 0) { + printk("Could not find subgroup channel allocation: %d - Looking in the BISes\n", + err); + + /* Find chan alloc in BIS */ + if (find_valid_bis_in_subgroup_bis(subgroup, bis_indexes)) { + /* Found BISes with correct channel allocation */ + return false; + } + } else { + /* If the subgroup contains a single channel, then we just grab the first BIS index + */ + if (get_chan_cnt(chan_allocation) == 1 && + chan_allocation == CONFIG_TARGET_BROADCAST_CHANNEL) { + uint32_t subgroup_bis_indexes; + + /* Set bis_indexes to the first bit set */ + err = bt_bap_base_subgroup_get_bis_indexes(subgroup, &subgroup_bis_indexes); + if (err != 0) { + /* Should never happen as that would indicate an invalid + * subgroup If it does, we just parse the next subgroup + */ + return true; + } + + /* We found the BIS index we want, stop parsing*/ + *bis_indexes = BIT(find_lsb_set(subgroup_bis_indexes) - 1); + + return false; + } else if ((chan_allocation & CONFIG_TARGET_BROADCAST_CHANNEL) == + CONFIG_TARGET_BROADCAST_CHANNEL) { + /* The subgroup contains all channels we are looking for/ + * We continue searching each BIS to get the minimal amount of BIS that + * satisfy CONFIG_TARGET_BROADCAST_CHANNEL. + */ + + if (find_valid_bis_in_subgroup_bis(subgroup, bis_indexes)) { + /* Found BISes with correct channel allocation */ + return false; + } + } + } + + return true; } -static int base_get_first_valid_bis(const struct bt_bap_base *base, uint32_t *bis_index) +/** + * This function gets a 32-bit bitfield of BIS indexes that cover the channel allocation values in + * CONFIG_TARGET_BROADCAST_CHANNEL. + */ +static int base_get_valid_bis_indexes(const struct bt_bap_base *base, uint32_t *bis_indexes) { int err; - uint8_t valid_bis_index = 0U; - err = bt_bap_base_foreach_subgroup(base, find_valid_bis_in_subgroup_cb, &valid_bis_index); + err = bt_bap_base_foreach_subgroup(base, find_valid_bis_in_subgroup_cb, bis_indexes); if (err != -ECANCELED) { printk("Failed to parse subgroups: %d\n", err); return err != 0 ? err : -ENOENT; } - *bis_index = 0; - *bis_index |= ((uint8_t)1 << valid_bis_index); - return 0; } #endif /* CONFIG_TARGET_BROADCAST_CHANNEL */ @@ -587,7 +802,7 @@ static void base_recv_cb(struct bt_bap_broadcast_sink *sink, const struct bt_bap bt_bap_base_get_subgroup_count(base), sink); #if defined(CONFIG_TARGET_BROADCAST_CHANNEL) - err = base_get_first_valid_bis(base, &base_bis_index_bitfield); + err = base_get_valid_bis_indexes(base, &base_bis_index_bitfield); if (err != 0) { printk("Failed to find a valid BIS\n"); return; From ab5f727660b6504ed9c1f631b66a949259ee614b Mon Sep 17 00:00:00 2001 From: Mikhail Siomin Date: Tue, 5 Mar 2024 00:18:45 +0300 Subject: [PATCH 0512/2402] dts: nxp: Added flexio support for i.MX rt10xx and kinetis ke1xf series Added description of flexio peripherals for i.MX rt10xx and kinetis ke1xf series. Signed-off-by: Mikhail Siomin --- .../twr_ke18f/dts/bindings/nxp,flexio.yaml | 17 ----------------- boards/nxp/twr_ke18f/twr_ke18f.dts | 11 ++++------- dts/arm/nxp/nxp_ke1xf.dtsi | 8 ++++++++ dts/arm/nxp/nxp_rt1040.dtsi | 16 ++++++++++++++++ dts/arm/nxp/nxp_rt1050.dtsi | 8 ++++++++ dts/arm/nxp/nxp_rt1060.dtsi | 16 ++++++++++++++++ dts/arm/nxp/nxp_rt10xx.dtsi | 8 ++++++++ dts/bindings/misc/nxp,flexio.yaml | 19 +++++++++++++++++++ 8 files changed, 79 insertions(+), 24 deletions(-) delete mode 100644 boards/nxp/twr_ke18f/dts/bindings/nxp,flexio.yaml create mode 100644 dts/bindings/misc/nxp,flexio.yaml diff --git a/boards/nxp/twr_ke18f/dts/bindings/nxp,flexio.yaml b/boards/nxp/twr_ke18f/dts/bindings/nxp,flexio.yaml deleted file mode 100644 index eb727805d0d..00000000000 --- a/boards/nxp/twr_ke18f/dts/bindings/nxp,flexio.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2022, NXP -# SPDX-License-Identifier: Apache-2.0 - -description: | - NXP FlexIO binding. This binding does not represent a full FlexIO driver, but - declares pinctrl properties, so that the user can MUX pins at the board level - for the FlexIO. - -compatible: "nxp,flexio" - -include: [base.yaml, pinctrl-device.yaml] - -properties: - pinctrl-0: - required: true - pinctrl-names: - required: true diff --git a/boards/nxp/twr_ke18f/twr_ke18f.dts b/boards/nxp/twr_ke18f/twr_ke18f.dts index 92a11d68842..a926827d0e6 100644 --- a/boards/nxp/twr_ke18f/twr_ke18f.dts +++ b/boards/nxp/twr_ke18f/twr_ke18f.dts @@ -132,13 +132,6 @@ zephyr,code = ; }; }; - - flexio: flexio@4005a000 { - reg = <0x4005a000 0x1000>; - compatible = "nxp,flexio"; - pinctrl-0 = <&flexio_clockout>; - pinctrl-names = "default"; - }; }; &cpu0 { @@ -331,6 +324,10 @@ status = "okay"; }; +&flexio1 { + status = "okay"; +}; + &flash0 { partitions { diff --git a/dts/arm/nxp/nxp_ke1xf.dtsi b/dts/arm/nxp/nxp_ke1xf.dtsi index 0a834b2b67f..5007f58f434 100644 --- a/dts/arm/nxp/nxp_ke1xf.dtsi +++ b/dts/arm/nxp/nxp_ke1xf.dtsi @@ -596,6 +596,14 @@ status = "disabled"; #io-channel-cells = <2>; }; + + flexio1: flexio@4005a000 { + compatible = "nxp,flexio"; + reg = <0x4005a000 0x1000>; + status = "disabled"; + interrupts = <69 0>; + clocks = <&pcc 0x168 KINETIS_PCC_SRC_FIRC_ASYNC>; + }; }; }; diff --git a/dts/arm/nxp/nxp_rt1040.dtsi b/dts/arm/nxp/nxp_rt1040.dtsi index c4aa2d57891..70dd0b0d4ad 100644 --- a/dts/arm/nxp/nxp_rt1040.dtsi +++ b/dts/arm/nxp/nxp_rt1040.dtsi @@ -33,6 +33,22 @@ /delete-node/ csi@402bc000; /* LPSPI at 0x4039c000 is not present */ /delete-node/ spi@4039c000; + + flexio2: flexio@401b0000 { + compatible = "nxp,flexio"; + reg = <0x401b0000 0x4000>; + status = "disabled"; + interrupts = <91 0>; + clocks = <&ccm IMX_CCM_FLEXIO2_3_CLK 0 0>; + }; + + flexio3: flexio@42020000 { + compatible = "nxp,flexio"; + reg = <0x42020000 0x4000>; + status = "disabled"; + interrupts = <156 0>; + clocks = <&ccm IMX_CCM_FLEXIO2_3_CLK 0 0>; + }; }; }; diff --git a/dts/arm/nxp/nxp_rt1050.dtsi b/dts/arm/nxp/nxp_rt1050.dtsi index 0a66b9b791e..12e1c623bce 100644 --- a/dts/arm/nxp/nxp_rt1050.dtsi +++ b/dts/arm/nxp/nxp_rt1050.dtsi @@ -43,6 +43,14 @@ /delete-node/ gpio@42004000; /delete-node/ gpio@42008000; /delete-node/ gpio@4200c000; + + flexio2: flexio@401b0000 { + compatible = "nxp,flexio"; + reg = <0x401b0000 0x4000>; + status = "disabled"; + interrupts = <91 0>; + clocks = <&ccm IMX_CCM_FLEXIO2_3_CLK 0 0>; + }; }; }; diff --git a/dts/arm/nxp/nxp_rt1060.dtsi b/dts/arm/nxp/nxp_rt1060.dtsi index 8a9cba715e0..e6148094192 100644 --- a/dts/arm/nxp/nxp_rt1060.dtsi +++ b/dts/arm/nxp/nxp_rt1060.dtsi @@ -68,6 +68,22 @@ reg = <0x20200000 DT_SIZE_K(512)>; zephyr,memory-region = "OCRAM2"; }; + + flexio2: flexio@401b0000 { + compatible = "nxp,flexio"; + reg = <0x401b0000 0x4000>; + status = "disabled"; + interrupts = <91 0>; + clocks = <&ccm IMX_CCM_FLEXIO2_3_CLK 0 0>; + }; + + flexio3: flexio@42020000 { + compatible = "nxp,flexio"; + reg = <0x42020000 0x4000>; + status = "disabled"; + interrupts = <156 0>; + clocks = <&ccm IMX_CCM_FLEXIO2_3_CLK 0 0>; + }; }; }; diff --git a/dts/arm/nxp/nxp_rt10xx.dtsi b/dts/arm/nxp/nxp_rt10xx.dtsi index 39486d0b76b..771df619dc0 100644 --- a/dts/arm/nxp/nxp_rt10xx.dtsi +++ b/dts/arm/nxp/nxp_rt10xx.dtsi @@ -1122,6 +1122,14 @@ status = "disabled"; }; }; + + flexio1: flexio@401ac000 { + compatible = "nxp,flexio"; + reg = <0x401ac000 0x4000>; + status = "disabled"; + interrupts = <90 0>; + clocks = <&ccm IMX_CCM_FLEXIO1_CLK 0 0>; + }; }; }; diff --git a/dts/bindings/misc/nxp,flexio.yaml b/dts/bindings/misc/nxp,flexio.yaml new file mode 100644 index 00000000000..29dac0209a5 --- /dev/null +++ b/dts/bindings/misc/nxp,flexio.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024, STRIM, ALC +# SPDX-License-Identifier: Apache-2.0 + +description: NXP FlexIO controller + +compatible: "nxp,flexio" + +include: base.yaml + + +properties: + reg: + required: true + + interrupts: + required: true + + clocks: + required: true From b12e8cd2b072cf99cf3e7ee81a92dcf1dd47187f Mon Sep 17 00:00:00 2001 From: Mikhail Siomin Date: Tue, 5 Mar 2024 00:23:54 +0300 Subject: [PATCH 0513/2402] clock: nxp_imx: Added clock control support for FlexIO Added clock control support for flexIO for i.MX series. Signed-off-by: Mikhail Siomin --- .../clock_control/clock_control_mcux_ccm.c | 45 +++++++++++++++++++ include/zephyr/dt-bindings/clock/imx_ccm.h | 3 ++ 2 files changed, 48 insertions(+) diff --git a/drivers/clock_control/clock_control_mcux_ccm.c b/drivers/clock_control/clock_control_mcux_ccm.c index 82f3c1310f3..f3574f00532 100644 --- a/drivers/clock_control/clock_control_mcux_ccm.c +++ b/drivers/clock_control/clock_control_mcux_ccm.c @@ -331,6 +331,51 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, case IMX_CCM_PIT_CLK: *rate = CLOCK_GetFreq(kCLOCK_PerClk); break; +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexio1), okay) && CONFIG_MCUX_FLEXIO + case IMX_CCM_FLEXIO1_CLK: + { + uint32_t flexio_mux = CLOCK_GetMux(kCLOCK_Flexio1Mux); + uint32_t source_clk_freq = 0; + + if (flexio_mux == 0) { + source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + } else if (flexio_mux == 1) { + source_clk_freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2); + #ifdef PLL_VIDEO_OFFSET /* fsl_clock.h */ + } else if (flexio_mux == 2) { + source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllVideo); + #endif + } else { + source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + } + + *rate = source_clk_freq / (CLOCK_GetDiv(kCLOCK_Flexio1PreDiv) + 1) + / (CLOCK_GetDiv(kCLOCK_Flexio1Div) + 1); + } break; +#endif +#if (DT_NODE_HAS_STATUS(DT_NODELABEL(flexio2), okay) \ + || DT_NODE_HAS_STATUS(DT_NODELABEL(flexio3), okay)) && CONFIG_MCUX_FLEXIO + case IMX_CCM_FLEXIO2_3_CLK: + { + uint32_t flexio_mux = CLOCK_GetMux(kCLOCK_Flexio2Mux); + uint32_t source_clk_freq = 0; + + if (flexio_mux == 0) { + source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + } else if (flexio_mux == 1) { + source_clk_freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2); + #ifdef PLL_VIDEO_OFFSET /* fsl_clock.h */ + } else if (flexio_mux == 2) { + source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllVideo); + #endif + } else { + source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + } + + *rate = source_clk_freq / (CLOCK_GetDiv(kCLOCK_Flexio2PreDiv) + 1) + / (CLOCK_GetDiv(kCLOCK_Flexio2Div) + 1); + } break; #endif } diff --git a/include/zephyr/dt-bindings/clock/imx_ccm.h b/include/zephyr/dt-bindings/clock/imx_ccm.h index 5ad08306be4..49bc7db9246 100644 --- a/include/zephyr/dt-bindings/clock/imx_ccm.h +++ b/include/zephyr/dt-bindings/clock/imx_ccm.h @@ -63,4 +63,7 @@ #define IMX_CCM_PIT_CLK 0x1000UL +#define IMX_CCM_FLEXIO1_CLK 0x1100UL +#define IMX_CCM_FLEXIO2_3_CLK 0x1101UL + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */ From 877b10bef17c027a7c3b5593bab78084de1509c5 Mon Sep 17 00:00:00 2001 From: Mikhail Siomin Date: Mon, 11 Mar 2024 23:43:30 +0300 Subject: [PATCH 0514/2402] drivers: mcux: flexio: Added generic MCUX FlexIO driver Added FlexIO driver that distributes hardware resources between interfaces using them. Signed-off-by: Mikhail Siomin --- drivers/misc/CMakeLists.txt | 1 + drivers/misc/Kconfig | 1 + drivers/misc/mcux_flexio/CMakeLists.txt | 6 + drivers/misc/mcux_flexio/Kconfig | 26 ++ drivers/misc/mcux_flexio/mcux_flexio.c | 260 ++++++++++++++++++ .../drivers/misc/nxp_flexio/nxp_flexio.h | 88 ++++++ west.yml | 2 +- 7 files changed, 383 insertions(+), 1 deletion(-) create mode 100644 drivers/misc/mcux_flexio/CMakeLists.txt create mode 100644 drivers/misc/mcux_flexio/Kconfig create mode 100644 drivers/misc/mcux_flexio/mcux_flexio.c create mode 100644 include/zephyr/drivers/misc/nxp_flexio/nxp_flexio.h diff --git a/drivers/misc/CMakeLists.txt b/drivers/misc/CMakeLists.txt index c23bdb185de..1c0da74d998 100644 --- a/drivers/misc/CMakeLists.txt +++ b/drivers/misc/CMakeLists.txt @@ -8,3 +8,4 @@ add_subdirectory_ifdef(CONFIG_NXP_S32_EMIOS nxp_s32_emios) add_subdirectory_ifdef(CONFIG_TIMEAWARE_GPIO timeaware_gpio) add_subdirectory_ifdef(CONFIG_DEVMUX devmux) add_subdirectory_ifdef(CONFIG_NORDIC_VPR_LAUNCHER nordic_vpr_launcher) +add_subdirectory_ifdef(CONFIG_MCUX_FLEXIO mcux_flexio) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 3511b8b6fd4..a87218c120a 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -12,5 +12,6 @@ source "drivers/misc/nxp_s32_emios/Kconfig" source "drivers/misc/timeaware_gpio/Kconfig" source "drivers/misc/devmux/Kconfig" source "drivers/misc/nordic_vpr_launcher/Kconfig" +source "drivers/misc/mcux_flexio/Kconfig" endmenu diff --git a/drivers/misc/mcux_flexio/CMakeLists.txt b/drivers/misc/mcux_flexio/CMakeLists.txt new file mode 100644 index 00000000000..fac2c9078f0 --- /dev/null +++ b/drivers/misc/mcux_flexio/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2024, STRIM, ALC +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(mcux_flexio.c) diff --git a/drivers/misc/mcux_flexio/Kconfig b/drivers/misc/mcux_flexio/Kconfig new file mode 100644 index 00000000000..b5d5a26d1f3 --- /dev/null +++ b/drivers/misc/mcux_flexio/Kconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2024, STRIM, ALC +# SPDX-License-Identifier: Apache-2.0 + +config MCUX_FLEXIO + bool + depends on DT_HAS_NXP_FLEXIO_ENABLED + depends on CLOCK_CONTROL + help + Enable the FlexIO controller driver. + This driver is not user-selectable, + and should be enabled by other FlexIO drivers so + that they can use it to share the resources of the FlexIO device. + +if MCUX_FLEXIO + +config MCUX_FLEXIO_INIT_PRIORITY + int "FlexIO controller driver init priority" + default KERNEL_INIT_PRIORITY_DEVICE + help + MCUX FlexIO device driver initialization priority. + +module = MCUX_FLEXIO +module-str = mcux_flexio +source "subsys/logging/Kconfig.template.log_config" + +endif # MCUX_FLEXIO diff --git a/drivers/misc/mcux_flexio/mcux_flexio.c b/drivers/misc/mcux_flexio/mcux_flexio.c new file mode 100644 index 00000000000..46c39d0910d --- /dev/null +++ b/drivers/misc/mcux_flexio/mcux_flexio.c @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2024, STRIM, ALC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_flexio + +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(mcux_flexio, CONFIG_MCUX_FLEXIO_LOG_LEVEL); + + +struct mcux_flexio_config { + FLEXIO_Type *base; + const struct device *clock_dev; + clock_control_subsys_t clock_subsys; + void (*irq_config_func)(const struct device *dev); + void (*irq_enable_func)(void); + void (*irq_disable_func)(void); +}; + +typedef const struct nxp_flexio_child *nxp_flexio_map_child_t; + +struct mcux_flexio_data { + struct k_mutex lock; + uint32_t shifter_indexes_used; + uint32_t timer_indexes_used; + nxp_flexio_map_child_t *map_shifter_child; + nxp_flexio_map_child_t *map_timer_child; + uint32_t map_shifter_child_count; + uint32_t map_timer_child_count; +}; + + +static int mcux_flexio_child_take_shifter_idx(const struct device *dev) +{ + struct mcux_flexio_data *data = dev->data; + + for (uint32_t i = 0; i < data->map_shifter_child_count; i++) { + if ((data->shifter_indexes_used & BIT(i)) == 0) { + WRITE_BIT(data->shifter_indexes_used, i, 1); + return i; + } + } + + return -ENOBUFS; +} + +static int mcux_flexio_child_take_timer_idx(const struct device *dev) +{ + struct mcux_flexio_data *data = dev->data; + + for (uint32_t i = 0; i < data->map_timer_child_count; i++) { + if ((data->timer_indexes_used & BIT(i)) == 0) { + WRITE_BIT(data->timer_indexes_used, i, 1); + return i; + } + } + + return -ENOBUFS; +} + +static void mcux_flexio_isr(const struct device *dev) +{ + const struct mcux_flexio_config *config = dev->config; + struct mcux_flexio_data *data = dev->data; + FLEXIO_Type *base = config->base; + + nxp_flexio_map_child_t *map_shifter_child = data->map_shifter_child; + uint32_t map_shifter_child_count = data->map_shifter_child_count; + uint32_t shifter_status_flag = FLEXIO_GetShifterStatusFlags(base); + uint32_t shifter_error_flag = FLEXIO_GetShifterErrorFlags(base); + + if (shifter_status_flag || shifter_error_flag) { + for (uint32_t idx = 0; idx < map_shifter_child_count; idx++) { + if (((shifter_status_flag | shifter_error_flag) & BIT(idx)) != 0) { + const struct nxp_flexio_child *child = map_shifter_child[idx]; + + if (child != NULL) { + nxp_flexio_child_isr_t isr = child->isr; + + if (isr != NULL) { + isr(child->user_data); + } + } + } + } + } + + nxp_flexio_map_child_t *map_timer_child = data->map_timer_child; + uint32_t map_timer_child_count = data->map_timer_child_count; + uint32_t timer_status_flag = FLEXIO_GetTimerStatusFlags(base); + + if (timer_status_flag) { + for (uint32_t idx = 0; idx < map_timer_child_count; idx++) { + if ((timer_status_flag & BIT(idx)) != 0) { + const struct nxp_flexio_child *child = map_timer_child[idx]; + + if (child != NULL) { + nxp_flexio_child_isr_t isr = child->isr; + + if (isr != NULL) { + isr(child->user_data); + } + } + } + } + } + + SDK_ISR_EXIT_BARRIER; +} + +static int mcux_flexio_init(const struct device *dev) +{ + const struct mcux_flexio_config *config = dev->config; + struct mcux_flexio_data *data = dev->data; + flexio_config_t flexio_config; + + k_mutex_init(&data->lock); + + FLEXIO_GetDefaultConfig(&flexio_config); + FLEXIO_Init(config->base, &flexio_config); + config->irq_config_func(dev); + + return 0; +} + +void nxp_flexio_irq_enable(const struct device *dev) +{ + const struct mcux_flexio_config *config = dev->config; + + config->irq_enable_func(); +} + +void nxp_flexio_irq_disable(const struct device *dev) +{ + const struct mcux_flexio_config *config = dev->config; + + config->irq_disable_func(); +} + +void nxp_flexio_lock(const struct device *dev) +{ + struct mcux_flexio_data *data = dev->data; + + k_mutex_lock(&data->lock, K_FOREVER); +} + +void nxp_flexio_unlock(const struct device *dev) +{ + struct mcux_flexio_data *data = dev->data; + + k_mutex_unlock(&data->lock); +} + +int nxp_flexio_get_rate(const struct device *dev, uint32_t *rate) +{ + const struct mcux_flexio_config *config = dev->config; + + return clock_control_get_rate(config->clock_dev, config->clock_subsys, rate); +} + +int nxp_flexio_child_attach(const struct device *dev, + const struct nxp_flexio_child *child) +{ + struct mcux_flexio_data *data = dev->data; + const struct nxp_flexio_child_res *child_res = &child->res; + + for (uint32_t i = 0; i < child_res->shifter_count; i++) { + int shifter_idx = mcux_flexio_child_take_shifter_idx(dev); + + if (shifter_idx < 0) { + LOG_ERR("Failed to take shifter index: %d", shifter_idx); + return shifter_idx; + } + child_res->shifter_index[i] = shifter_idx; + data->map_shifter_child[shifter_idx] = child; + LOG_DBG("child %p: shifter_idx[%d] is %d", child, i, shifter_idx); + } + + for (uint32_t i = 0; i < child_res->timer_count; i++) { + int timer_idx = mcux_flexio_child_take_timer_idx(dev); + + if (timer_idx < 0) { + LOG_ERR("Failed to take timer index: %d", timer_idx); + return timer_idx; + } + child_res->timer_index[i] = timer_idx; + data->map_timer_child[timer_idx] = child; + LOG_DBG("child %p: timer_idx[%d] is %d", child, i, timer_idx); + } + + return 0; +} + +#define MCUX_FLEXIO_SHIFTER_COUNT_MAX(n) \ + ARRAY_SIZE(((FLEXIO_Type *)DT_INST_REG_ADDR(n))->SHIFTCTL) + +#define MCUX_FLEXIO_TIMER_COUNT_MAX(n) \ + ARRAY_SIZE(((FLEXIO_Type *)DT_INST_REG_ADDR(n))->TIMCTL) + +#define MCUX_FLEXIO_INIT(n) \ + static void mcux_flexio_irq_config_func_##n(const struct device *dev); \ + static void mcux_flexio_irq_enable_func_##n(void); \ + static void mcux_flexio_irq_disable_func_##n(void); \ + \ + static nxp_flexio_map_child_t \ + nxp_flexio_map_shifter_child_##n[MCUX_FLEXIO_SHIFTER_COUNT_MAX(n)] = {0}; \ + static nxp_flexio_map_child_t \ + nxp_flexio_map_timer_child_##n[MCUX_FLEXIO_TIMER_COUNT_MAX(n)] = {0}; \ + \ + static struct mcux_flexio_data mcux_flexio_data_##n = { \ + .map_shifter_child = nxp_flexio_map_shifter_child_##n, \ + .map_shifter_child_count = ARRAY_SIZE(nxp_flexio_map_shifter_child_##n), \ + .map_timer_child = nxp_flexio_map_timer_child_##n, \ + .map_timer_child_count = ARRAY_SIZE(nxp_flexio_map_timer_child_##n), \ + }; \ + \ + static const struct mcux_flexio_config mcux_flexio_config_##n = { \ + .base = (FLEXIO_Type *)DT_INST_REG_ADDR(n), \ + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clock_subsys = \ + (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \ + .irq_config_func = mcux_flexio_irq_config_func_##n, \ + .irq_enable_func = mcux_flexio_irq_enable_func_##n, \ + .irq_disable_func = mcux_flexio_irq_disable_func_##n, \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, &mcux_flexio_init, \ + NULL, \ + &mcux_flexio_data_##n, \ + &mcux_flexio_config_##n, \ + POST_KERNEL, \ + CONFIG_MCUX_FLEXIO_INIT_PRIORITY, \ + NULL); \ + \ + static void mcux_flexio_irq_config_func_##n(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ + mcux_flexio_isr, DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + } \ + \ + static void mcux_flexio_irq_enable_func_##n(void) \ + { \ + irq_enable(DT_INST_IRQN(n)); \ + } \ + \ + static void mcux_flexio_irq_disable_func_##n(void) \ + { \ + irq_disable(DT_INST_IRQN(n)); \ + } + +DT_INST_FOREACH_STATUS_OKAY(MCUX_FLEXIO_INIT) diff --git a/include/zephyr/drivers/misc/nxp_flexio/nxp_flexio.h b/include/zephyr/drivers/misc/nxp_flexio/nxp_flexio.h new file mode 100644 index 00000000000..a4c3f080162 --- /dev/null +++ b/include/zephyr/drivers/misc/nxp_flexio/nxp_flexio.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2024, STRIM, ALC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_MISC_NXP_FLEXIO_NXP_FLEXIO_H_ +#define ZEPHYR_DRIVERS_MISC_NXP_FLEXIO_NXP_FLEXIO_H_ + +#include + +/** + * @struct nxp_flexio_child_res + * @brief Structure containing information about the required + * resources for a FlexIO child. + */ +struct nxp_flexio_child_res { + uint8_t *shifter_index; + uint8_t shifter_count; + uint8_t *timer_index; + uint8_t timer_count; +}; + +/** + * @typedef nxp_flexio_child_isr_t + * @brief Callback API to inform API user that FlexIO triggered interrupt + * + * This callback is called from IRQ context. + */ +typedef int (*nxp_flexio_child_isr_t)(void *user_data); + +/** + * @struct nxp_flexio_child + * @brief Structure containing the required child data for FlexIO + */ +struct nxp_flexio_child { + nxp_flexio_child_isr_t isr; + void *user_data; + struct nxp_flexio_child_res res; +}; + +/** + * @brief Enable FlexIO IRQ + * @param dev Pointer to the device structure for the FlexIO driver instance + */ +void nxp_flexio_irq_enable(const struct device *dev); + +/** + * @brief Disable FlexIO IRQ + * @param dev Pointer to the device structure for the FlexIO driver instance + */ +void nxp_flexio_irq_disable(const struct device *dev); + +/** + * @brief Lock FlexIO mutex. + * @param dev Pointer to the device structure for the FlexIO driver instance + */ +void nxp_flexio_lock(const struct device *dev); + +/** + * @brief Unlock FlexIO mutex. + * @param dev Pointer to the device structure for the FlexIO driver instance + */ +void nxp_flexio_unlock(const struct device *dev); + +/** + * @brief Obtain the clock rate of sub-system used by the FlexIO + * @param dev Pointer to the device structure for the FlexIO driver instance + * @param[out] rate Subsystem clock rate + * @retval 0 on successful rate reading. + * @retval -EAGAIN if rate cannot be read. Some drivers do not support returning the rate when the + * clock is off. + * @retval -ENOTSUP if reading the clock rate is not supported for the given sub-system. + * @retval -ENOSYS if the interface is not implemented. + */ +int nxp_flexio_get_rate(const struct device *dev, uint32_t *rate); + +/** + * @brief Attach flexio child to flexio controller + * @param dev Pointer to the device structure for the FlexIO driver instance + * @param child Pointer to flexio child + * @retval 0 if successful + * @retval -ENOBUFS if there are not enough available resources + */ +int nxp_flexio_child_attach(const struct device *dev, + const struct nxp_flexio_child *child); + +#endif /* ZEPHYR_DRIVERS_MISC_NXP_FLEXIO_NXP_FLEXIO_H_ */ diff --git a/west.yml b/west.yml index 2a22ac86ece..6a32031c1e6 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: ef5060421fdba7bd86f98e50dc15db9a5c4c1b53 + revision: ac24626660f96dc734714896878dd6e1157c1c29 path: modules/hal/nxp groups: - hal From 8dbfdd6f9f6807c830b9ce833801bc362f4b13e5 Mon Sep 17 00:00:00 2001 From: Mikhail Siomin Date: Mon, 11 Mar 2024 23:45:36 +0300 Subject: [PATCH 0515/2402] drivers: mcux: flexio: Added MCUX FlexIO SPI driver Added SPI driver using FlexIO. Signed-off-by: Mikhail Siomin --- drivers/spi/CMakeLists.txt | 1 + drivers/spi/Kconfig | 2 + drivers/spi/Kconfig.mcux_flexio | 11 + drivers/spi/spi_mcux_flexio.c | 438 +++++++++++++++++++++++++++ dts/bindings/spi/nxp,flexio-spi.yaml | 27 ++ 5 files changed, 479 insertions(+) create mode 100644 drivers/spi/Kconfig.mcux_flexio create mode 100644 drivers/spi/spi_mcux_flexio.c create mode 100644 dts/bindings/spi/nxp,flexio-spi.yaml diff --git a/drivers/spi/CMakeLists.txt b/drivers/spi/CMakeLists.txt index cd4699850f2..d5abf88f407 100644 --- a/drivers/spi/CMakeLists.txt +++ b/drivers/spi/CMakeLists.txt @@ -11,6 +11,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_EMUL spi_emul.c) zephyr_library_sources_ifdef(CONFIG_SPI_STM32 spi_ll_stm32.c) zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_DSPI spi_mcux_dspi.c) zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_FLEXCOMM spi_mcux_flexcomm.c) +zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_FLEXIO spi_mcux_flexio.c) zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI spi_mcux_lpspi.c) zephyr_library_sources_ifdef(CONFIG_SPI_SAM spi_sam.c) zephyr_library_sources_ifdef(CONFIG_SPI_SAM0 spi_sam0.c) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2cb7c83bd1c..acb37b3c43a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -75,6 +75,8 @@ source "drivers/spi/Kconfig.mcux_dspi" source "drivers/spi/Kconfig.mcux_flexcomm" +source "drivers/spi/Kconfig.mcux_flexio" + source "drivers/spi/Kconfig.mcux_lpspi" source "drivers/spi/Kconfig.rv32m1_lpspi" diff --git a/drivers/spi/Kconfig.mcux_flexio b/drivers/spi/Kconfig.mcux_flexio new file mode 100644 index 00000000000..82e04a538aa --- /dev/null +++ b/drivers/spi/Kconfig.mcux_flexio @@ -0,0 +1,11 @@ +# Copyright (c) 2024, STRIM, ALC +# SPDX-License-Identifier: Apache-2.0 + +config SPI_MCUX_FLEXIO + bool "MCUX FlexIO SPI driver" + default y + depends on DT_HAS_NXP_FLEXIO_SPI_ENABLED + depends on CLOCK_CONTROL + select MCUX_FLEXIO + help + Enable support for MCUX FlexIO SPI driver. diff --git a/drivers/spi/spi_mcux_flexio.c b/drivers/spi/spi_mcux_flexio.c new file mode 100644 index 00000000000..69bb996e6fa --- /dev/null +++ b/drivers/spi/spi_mcux_flexio.c @@ -0,0 +1,438 @@ +/* + * Copyright (c) 2024, STRIM, ALC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_flexio_spi + +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(spi_mcux_flexio_spi, CONFIG_SPI_LOG_LEVEL); + +#include "spi_context.h" + + +struct spi_mcux_flexio_config { + FLEXIO_SPI_Type *flexio_spi; + const struct device *flexio_dev; + const struct pinctrl_dev_config *pincfg; + const struct nxp_flexio_child *child; +}; + +struct spi_mcux_flexio_data { + const struct device *dev; + flexio_spi_master_handle_t handle; + struct spi_context ctx; + size_t transfer_len; + uint8_t transfer_flags; +}; + + +static void spi_mcux_transfer_next_packet(const struct device *dev) +{ + const struct spi_mcux_flexio_config *config = dev->config; + struct spi_mcux_flexio_data *data = dev->data; + struct spi_context *ctx = &data->ctx; + flexio_spi_transfer_t transfer; + status_t status; + + if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) { + /* nothing left to rx or tx, we're done! */ + spi_context_cs_control(&data->ctx, false); + spi_context_complete(&data->ctx, dev, 0); + return; + } + + transfer.flags = kFLEXIO_SPI_csContinuous | data->transfer_flags; + + if (ctx->tx_len == 0) { + /* rx only, nothing to tx */ + transfer.txData = NULL; + transfer.rxData = ctx->rx_buf; + transfer.dataSize = ctx->rx_len; + } else if (ctx->rx_len == 0) { + /* tx only, nothing to rx */ + transfer.txData = (uint8_t *) ctx->tx_buf; + transfer.rxData = NULL; + transfer.dataSize = ctx->tx_len; + } else if (ctx->tx_len == ctx->rx_len) { + /* rx and tx are the same length */ + transfer.txData = (uint8_t *) ctx->tx_buf; + transfer.rxData = ctx->rx_buf; + transfer.dataSize = ctx->tx_len; + } else if (ctx->tx_len > ctx->rx_len) { + /* Break up the tx into multiple transfers so we don't have to + * rx into a longer intermediate buffer. Leave chip select + * active between transfers. + */ + transfer.txData = (uint8_t *) ctx->tx_buf; + transfer.rxData = ctx->rx_buf; + transfer.dataSize = ctx->rx_len; + } else { + /* Break up the rx into multiple transfers so we don't have to + * tx from a longer intermediate buffer. Leave chip select + * active between transfers. + */ + transfer.txData = (uint8_t *) ctx->tx_buf; + transfer.rxData = ctx->rx_buf; + transfer.dataSize = ctx->tx_len; + } + + data->transfer_len = transfer.dataSize; + + status = FLEXIO_SPI_MasterTransferNonBlocking(config->flexio_spi, &data->handle, + &transfer); + if (status != kStatus_Success) { + LOG_ERR("Transfer could not start"); + } +} + +static int spi_mcux_flexio_isr(void *user_data) +{ + const struct device *dev = (const struct device *)user_data; + const struct spi_mcux_flexio_config *config = dev->config; + struct spi_mcux_flexio_data *data = dev->data; + + FLEXIO_SPI_MasterTransferHandleIRQ(config->flexio_spi, &data->handle); + + return 0; +} + +static void spi_mcux_master_transfer_callback(FLEXIO_SPI_Type *flexio_spi, + flexio_spi_master_handle_t *handle, status_t status, void *userData) +{ + struct spi_mcux_flexio_data *data = userData; + + spi_context_update_tx(&data->ctx, 1, data->transfer_len); + spi_context_update_rx(&data->ctx, 1, data->transfer_len); + + spi_mcux_transfer_next_packet(data->dev); +} + +static void spi_flexio_master_init(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, + uint8_t pol, uint32_t srcClock_Hz) +{ + assert(base != NULL); + assert(masterConfig != NULL); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + (void)memset(&shifterConfig, 0, sizeof(shifterConfig)); + (void)memset(&timerConfig, 0, sizeof(timerConfig)); + + /* Configure FLEXIO SPI Master */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | + FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | + FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); + if (!masterConfig->enableInDoze) { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } else { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + } else { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for SCK. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = pol ? kFLEXIO_PinActiveLow : kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + /* Low 8-bits are used to configure baudrate. */ + timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps); + timerDiv = timerDiv / 2U - 1U; + /* High 8-bits are used to configure shift clock edges(transfer width). */ + timerCmp = ((uint16_t)masterConfig->dataMode * 2U - 1U) << 8U; + timerCmp |= timerDiv; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); +} + +static int spi_mcux_flexio_configure(const struct device *dev, + const struct spi_config *spi_cfg) +{ + const struct spi_mcux_flexio_config *config = dev->config; + struct spi_mcux_flexio_data *data = dev->data; + + flexio_spi_master_config_t master_config; + uint32_t clock_freq; + uint32_t word_size; + + if (spi_context_configured(&data->ctx, spi_cfg)) { + /* This configuration is already in use */ + return 0; + } + + if (spi_cfg->operation & SPI_HALF_DUPLEX) { + LOG_ERR("Half-duplex not supported"); + return -ENOTSUP; + } + + if (SPI_OP_MODE_GET(spi_cfg->operation) != SPI_OP_MODE_MASTER) { + LOG_ERR("Mode Slave not supported"); + return -ENOTSUP; + } + + FLEXIO_SPI_MasterGetDefaultConfig(&master_config); + + word_size = SPI_WORD_SIZE_GET(spi_cfg->operation); + if ((word_size != 8) && (word_size != 16) && (word_size != 32)) { + LOG_ERR("Word size %d must be 8, 16 or 32", word_size); + return -EINVAL; + } + master_config.dataMode = word_size; + + if (spi_cfg->operation & SPI_TRANSFER_LSB) { + if (word_size == 8) { + data->transfer_flags = kFLEXIO_SPI_8bitLsb; + } else if (word_size == 16) { + data->transfer_flags = kFLEXIO_SPI_16bitLsb; + } else { + data->transfer_flags = kFLEXIO_SPI_32bitLsb; + } + } else { + if (word_size == 8) { + data->transfer_flags = kFLEXIO_SPI_8bitMsb; + } else if (word_size == 16) { + data->transfer_flags = kFLEXIO_SPI_16bitMsb; + } else { + data->transfer_flags = kFLEXIO_SPI_32bitMsb; + } + } + + if (nxp_flexio_get_rate(config->flexio_dev, &clock_freq)) { + return -EINVAL; + } + + master_config.phase = + (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA) + ? kFLEXIO_SPI_ClockPhaseSecondEdge + : kFLEXIO_SPI_ClockPhaseFirstEdge; + + master_config.baudRate_Bps = spi_cfg->frequency; + spi_flexio_master_init(config->flexio_spi, &master_config, + (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL), clock_freq); + + FLEXIO_SPI_MasterTransferCreateHandle(config->flexio_spi, &data->handle, + spi_mcux_master_transfer_callback, + data); + /* No SetDummyData() for FlexIO_SPI */ + + data->ctx.config = spi_cfg; + + return 0; +} + + +static int transceive(const struct device *dev, + const struct spi_config *spi_cfg, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs, + bool asynchronous, + spi_callback_t cb, + void *userdata) +{ + const struct spi_mcux_flexio_config *config = dev->config; + struct spi_mcux_flexio_data *data = dev->data; + int ret; + + spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg); + + nxp_flexio_lock(config->flexio_dev); + ret = spi_mcux_flexio_configure(dev, spi_cfg); + nxp_flexio_unlock(config->flexio_dev); + if (ret) { + goto out; + } + + spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1); + + spi_context_cs_control(&data->ctx, true); + + nxp_flexio_lock(config->flexio_dev); + nxp_flexio_irq_disable(config->flexio_dev); + + spi_mcux_transfer_next_packet(dev); + + nxp_flexio_irq_enable(config->flexio_dev); + nxp_flexio_unlock(config->flexio_dev); + + ret = spi_context_wait_for_completion(&data->ctx); +out: + spi_context_release(&data->ctx, ret); + + return ret; +} + +static int spi_mcux_transceive(const struct device *dev, + const struct spi_config *spi_cfg, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs) +{ + return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL); +} + +#ifdef CONFIG_SPI_ASYNC +static int spi_mcux_transceive_async(const struct device *dev, + const struct spi_config *spi_cfg, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs, + spi_callback_t cb, + void *userdata) +{ + return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata); +} +#endif /* CONFIG_SPI_ASYNC */ + +static int spi_mcux_release(const struct device *dev, + const struct spi_config *spi_cfg) +{ + struct spi_mcux_flexio_data *data = dev->data; + + spi_context_unlock_unconditionally(&data->ctx); + + return 0; +} + +static int spi_mcux_init(const struct device *dev) +{ + const struct spi_mcux_flexio_config *config = dev->config; + struct spi_mcux_flexio_data *data = dev->data; + int err; + + err = nxp_flexio_child_attach(config->flexio_dev, config->child); + if (err < 0) { + return err; + } + + err = spi_context_cs_configure_all(&data->ctx); + if (err < 0) { + return err; + } + + spi_context_unlock_unconditionally(&data->ctx); + + data->dev = dev; + + /* TODO: DMA */ + + err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); + if (err) { + return err; + } + + spi_context_unlock_unconditionally(&data->ctx); + + return 0; +} + +static const struct spi_driver_api spi_mcux_driver_api = { + .transceive = spi_mcux_transceive, +#ifdef CONFIG_SPI_ASYNC + .transceive_async = spi_mcux_transceive_async, +#endif + .release = spi_mcux_release, +}; + +#define SPI_MCUX_FLEXIO_SPI_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + \ + static FLEXIO_SPI_Type flexio_spi_##n = { \ + .flexioBase = (FLEXIO_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \ + .SDOPinIndex = DT_INST_PROP(n, sdo_pin), \ + .SDIPinIndex = DT_INST_PROP(n, sdi_pin), \ + .SCKPinIndex = DT_INST_PROP(n, sck_pin), \ + }; \ + \ + static const struct nxp_flexio_child nxp_flexio_spi_child_##n = { \ + .isr = spi_mcux_flexio_isr, \ + .user_data = (void *)DEVICE_DT_INST_GET(n), \ + .res = { \ + .shifter_index = flexio_spi_##n.shifterIndex, \ + .shifter_count = ARRAY_SIZE(flexio_spi_##n.shifterIndex), \ + .timer_index = flexio_spi_##n.timerIndex, \ + .timer_count = ARRAY_SIZE(flexio_spi_##n.timerIndex) \ + } \ + }; \ + \ + static const struct spi_mcux_flexio_config spi_mcux_flexio_config_##n = { \ + .flexio_spi = &flexio_spi_##n, \ + .flexio_dev = DEVICE_DT_GET(DT_INST_PARENT(n)), \ + .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .child = &nxp_flexio_spi_child_##n, \ + }; \ + \ + static struct spi_mcux_flexio_data spi_mcux_flexio_data_##n = { \ + SPI_CONTEXT_INIT_LOCK(spi_mcux_flexio_data_##n, ctx), \ + SPI_CONTEXT_INIT_SYNC(spi_mcux_flexio_data_##n, ctx), \ + SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, &spi_mcux_init, NULL, \ + &spi_mcux_flexio_data_##n, \ + &spi_mcux_flexio_config_##n, POST_KERNEL, \ + CONFIG_SPI_INIT_PRIORITY, \ + &spi_mcux_driver_api); \ + +DT_INST_FOREACH_STATUS_OKAY(SPI_MCUX_FLEXIO_SPI_INIT) diff --git a/dts/bindings/spi/nxp,flexio-spi.yaml b/dts/bindings/spi/nxp,flexio-spi.yaml new file mode 100644 index 00000000000..3c64d76ded1 --- /dev/null +++ b/dts/bindings/spi/nxp,flexio-spi.yaml @@ -0,0 +1,27 @@ +# Copyright (c) 2024, STRIM, ALC +# SPDX-License-Identifier: Apache-2.0 + +description: NXP FlexIO SPI controller + +compatible: "nxp,flexio-spi" + +include: [spi-controller.yaml, "pinctrl-device.yaml"] + +properties: + sdo-pin: + type: int + required: true + description: | + Pin select for data output. + + sdi-pin: + type: int + required: true + description: | + Pin select for data input. + + sck-pin: + type: int + required: true + description: | + Pin select for clock. From 0157a89f5295b7b3c17d52109d75aa2f85a43c82 Mon Sep 17 00:00:00 2001 From: Mikhail Siomin Date: Mon, 11 Mar 2024 23:47:56 +0300 Subject: [PATCH 0516/2402] tests: spi: spi_loopback: Added MCUX FlexIO SPI test Added FlexIO SPI test. Overlay in the tests for mimxrt1064_evk board only. Signed-off-by: Mikhail Siomin --- .../overlay-mcux-flexio-spi.overlay | 77 +++++++++++++++++++ tests/drivers/spi/spi_loopback/testcase.yaml | 5 ++ 2 files changed, 82 insertions(+) create mode 100644 tests/drivers/spi/spi_loopback/overlay-mcux-flexio-spi.overlay diff --git a/tests/drivers/spi/spi_loopback/overlay-mcux-flexio-spi.overlay b/tests/drivers/spi/spi_loopback/overlay-mcux-flexio-spi.overlay new file mode 100644 index 00000000000..5c56bda88da --- /dev/null +++ b/tests/drivers/spi/spi_loopback/overlay-mcux-flexio-spi.overlay @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2024, STRIM, ALC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + pinmux_flexio3spi0: pinmux_flexio3spi0 { + group0 { + pinmux = + <&iomuxc_gpio_ad_b0_03_gpio1_io03>, /* cs */ + <&iomuxc_gpio_ad_b1_10_flexio3_flexio10>, /* sck */ + <&iomuxc_gpio_ad_b1_01_flexio3_flexio01>, /* sdo */ + <&iomuxc_gpio_ad_b1_04_flexio3_flexio04>; /* sdi */ + drive-strength = "r0-6"; + slew-rate = "slow"; + nxp,speed = "150-mhz"; + }; + }; + pinmux_flexio3spi1: pinmux_flexio3spi1 { + group0 { + pinmux = + <&iomuxc_gpio_ad_b0_02_gpio1_io02>, /* cs */ + <&iomuxc_gpio_ad_b1_11_flexio3_flexio11>, /* sck */ + <&iomuxc_gpio_ad_b1_00_flexio3_flexio00>, /* sdo */ + <&iomuxc_gpio_ad_b1_05_flexio3_flexio05>; /* sdi */ + drive-strength = "r0-6"; + slew-rate = "slow"; + nxp,speed = "150-mhz"; + }; + }; +}; + +&flexio3 { + status = "okay"; + flexio3_spi0: flexio3_spi0 { + compatible = "nxp,flexio-spi"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + sdo-pin = <1>; + sdi-pin = <4>; + sck-pin = <10>; + pinctrl-0 = <&pinmux_flexio3spi0>; + pinctrl-names = "default"; + slow@0 { + status = "okay"; + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <500000>; + }; + }; + flexio3_spi1: flexio3_spi1 { + compatible = "nxp,flexio-spi"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + sdo-pin = <0>; + sdi-pin = <5>; + sck-pin = <11>; + pinctrl-0 = <&pinmux_flexio3spi1>; + pinctrl-names = "default"; + fast@0 { + status = "okay"; + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = <4000000>; + }; + }; +}; + +/* pinmux_lpspi3 overlaps pinmux_flexio3spi1 */ +&lpspi3 { + status = "disabled"; +}; diff --git a/tests/drivers/spi/spi_loopback/testcase.yaml b/tests/drivers/spi/spi_loopback/testcase.yaml index bb2e69961f6..083d383b9bd 100644 --- a/tests/drivers/spi/spi_loopback/testcase.yaml +++ b/tests/drivers/spi/spi_loopback/testcase.yaml @@ -158,3 +158,8 @@ tests: - CONFIG_SPI_PL022_DMA=y - CONFIG_DMA=y platform_allow: rpi_pico + drivers.spi.mcux_flexio_spi.loopback: + extra_args: DTC_OVERLAY_FILE="overlay-mcux-flexio-spi.overlay" + filter: CONFIG_DT_HAS_NXP_FLEXIO_ENABLED and + CONFIG_DT_HAS_NXP_FLEXIO_SPI_ENABLED + platform_allow: mimxrt1064_evk From 0888882262978aad4c1e4a2dbaad5333b013fb16 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 12 Mar 2024 08:37:40 +0100 Subject: [PATCH 0517/2402] tests/bsim broadcast_audio: Increase realtime timeout This test has been seen failing in older slower computers due to timeouts, let's increase the timeout so we don't break in those cases. Note this timeout is just a safety to eventually kill hung simulations even if nobody presses Ctrl+C. Signed-off-by: Alberto Escolar Piedras --- .../broadcast_audio_sink/tests_scripts/broadcast_audio.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/tests_scripts/broadcast_audio.sh b/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/tests_scripts/broadcast_audio.sh index 89a52e57431..e1881cbe920 100755 --- a/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/tests_scripts/broadcast_audio.sh +++ b/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/tests_scripts/broadcast_audio.sh @@ -12,7 +12,7 @@ verbosity_level=2 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -EXECUTE_TIMEOUT=100 +EXECUTE_TIMEOUT=200 cd ${BSIM_OUT_PATH}/bin From e9c88561657bae6ea7fd3b94c9d4c794c82915a0 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 12 Mar 2024 08:56:20 +0100 Subject: [PATCH 0518/2402] tests/bsim audio mcs_mcc: Increase realtime timeout This test has been seen failing in older slower computers due to timeouts, let's increase the timeout so we don't break in those cases. Note this timeout is just a safety to eventually kill hung simulations even if nobody presses Ctrl+C. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/bluetooth/audio/test_scripts/mcs_mcc.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/bsim/bluetooth/audio/test_scripts/mcs_mcc.sh b/tests/bsim/bluetooth/audio/test_scripts/mcs_mcc.sh index 4857a5cad05..f901aa34f41 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/mcs_mcc.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/mcs_mcc.sh @@ -8,7 +8,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source SIMULATION_ID="mcs_mcc" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 +EXECUTE_TIMEOUT=50 cd ${BSIM_OUT_PATH}/bin From d592455cc0cd83169f5fb59ad913e4bb72d8d6a9 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 12 Mar 2024 08:57:16 +0100 Subject: [PATCH 0519/2402] tests/bsim mesh: Increase realtime timeout One of these tests has been seen failing in older slower computers due to timeouts, let's increase the timeout so we don't break in those cases. Note this timeout is just a safety to eventually kill hung simulations even if nobody presses Ctrl+C. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/bluetooth/mesh/_mesh_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/bsim/bluetooth/mesh/_mesh_test.sh b/tests/bsim/bluetooth/mesh/_mesh_test.sh index fa999a5ace8..5df01a1bf78 100755 --- a/tests/bsim/bluetooth/mesh/_mesh_test.sh +++ b/tests/bsim/bluetooth/mesh/_mesh_test.sh @@ -3,7 +3,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -EXECUTE_TIMEOUT=300 +EXECUTE_TIMEOUT=600 function Skip(){ for i in "${SKIP[@]}" ; do From 9f9a6c547bc1ec23e6706d8954d4b3e9dcb7dcb4 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Sun, 10 Mar 2024 23:28:08 +0900 Subject: [PATCH 0520/2402] ci: bsim-tests: Use zephyr-runner v2 This commit updates the bsim-tests workflow to use the new zephyr-runner v2 CI runner deployment. It also updates the workflow to use the `ci-repo-cache` Docker image, which includes the Zephyr repository cache, because the node level repository cache is no longer available in the zephyr-runner v2. Signed-off-by: Stephanos Ioannidis --- .github/workflows/bsim-tests.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 402ae686593..c7cc0895bb8 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -30,12 +30,11 @@ concurrency: jobs: bsim-test: if: github.repository_owner == 'zephyrproject-rtos' - runs-on: zephyr-runner-linux-x64-4xlarge + runs-on: + group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.7 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 options: '--entrypoint /bin/bash' - volumes: - - /repo-cache/zephyrproject:/github/cache/zephyrproject env: ZEPHYR_TOOLCHAIN_VARIANT: zephyr BSIM_OUT_PATH: /opt/bsim/ @@ -55,10 +54,16 @@ jobs: # GitHub comes up with a fundamental fix for this problem. git config --global --add safe.directory ${GITHUB_WORKSPACE} + - name: Print cloud service information + run: | + echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" + echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" + echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" + - name: Clone cached Zephyr repository continue-on-error: true run: | - git clone --shared /github/cache/zephyrproject/zephyr . + git clone --shared /repo-cache/zephyrproject/zephyr . git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout @@ -78,7 +83,7 @@ jobs: west init -l . || true west config manifest.group-filter -- +ci west config --global update.narrow true - west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /github/cache/zephyrproject) + west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject) west forall -c 'git reset --hard HEAD' echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV From 796d09d2a650c3726ea9569397119dae5d2c7711 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Thu, 29 Feb 2024 16:30:41 +0100 Subject: [PATCH 0521/2402] dts: nordic: Add DPPIC and IPCT nodes to nRF54H20 EngA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit And add the corresponding bindings. Move alse the already existing bindings for nrf-dppic, nrf-ppi, and nrf-ipc so they are located together with the new ones and in more appropriate folders (DPPIC and PPI peripherals are not related to ARM, and IPC is for sending and receiving events, not messages, so ipm/ does not seem to be the best fit for it). Signed-off-by: Andrzej Głąbek --- dts/bindings/{ipm => ipc}/nordic,nrf-ipc.yaml | 0 dts/bindings/ipc/nordic,nrf-ipct-common.yaml | 45 +++++++++ dts/bindings/ipc/nordic,nrf-ipct-global.yaml | 17 ++++ dts/bindings/ipc/nordic,nrf-ipct-local.yaml | 12 +++ .../misc/nordic,nrf-dppic-global.yaml | 18 ++++ dts/bindings/misc/nordic,nrf-dppic-links.yaml | 17 ++++ dts/bindings/misc/nordic,nrf-dppic-local.yaml | 13 +++ .../{arm => misc}/nordic,nrf-dppic.yaml | 0 .../{arm => misc}/nordic,nrf-ppi.yaml | 0 .../misc/nordic,split-channel-groups.yaml | 20 ++++ dts/common/nordic/nrf54h20_enga.dtsi | 94 +++++++++++++++++++ 11 files changed, 236 insertions(+) rename dts/bindings/{ipm => ipc}/nordic,nrf-ipc.yaml (100%) create mode 100644 dts/bindings/ipc/nordic,nrf-ipct-common.yaml create mode 100644 dts/bindings/ipc/nordic,nrf-ipct-global.yaml create mode 100644 dts/bindings/ipc/nordic,nrf-ipct-local.yaml create mode 100644 dts/bindings/misc/nordic,nrf-dppic-global.yaml create mode 100644 dts/bindings/misc/nordic,nrf-dppic-links.yaml create mode 100644 dts/bindings/misc/nordic,nrf-dppic-local.yaml rename dts/bindings/{arm => misc}/nordic,nrf-dppic.yaml (100%) rename dts/bindings/{arm => misc}/nordic,nrf-ppi.yaml (100%) create mode 100644 dts/bindings/misc/nordic,split-channel-groups.yaml diff --git a/dts/bindings/ipm/nordic,nrf-ipc.yaml b/dts/bindings/ipc/nordic,nrf-ipc.yaml similarity index 100% rename from dts/bindings/ipm/nordic,nrf-ipc.yaml rename to dts/bindings/ipc/nordic,nrf-ipc.yaml diff --git a/dts/bindings/ipc/nordic,nrf-ipct-common.yaml b/dts/bindings/ipc/nordic,nrf-ipct-common.yaml new file mode 100644 index 00000000000..a75b63577c4 --- /dev/null +++ b/dts/bindings/ipc/nordic,nrf-ipct-common.yaml @@ -0,0 +1,45 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: Nordic IPCT (Interprocessor Communication Transceiver) + +include: base.yaml + +properties: + reg: + required: true + + channels: + type: int + required: true + description: Number of channels implemented by the IPCT instance. + + source-channel-links: + type: array + description: | + Mapping of IPCT channels that are mapped between two IPCT instances on + separate domains, in which a channel on this IPCT node is considered + the source. This array is then comprised of a 3-integer-wide "unit" + that defines one connection of the mapping. The format of this unit + is . Units are sequential + in the array, therefore requiring the length of this property to be + a factor of 3. + + For example, if channel 2 is to be mapped to Radio Core (ID: 3) IPCT + channel 4, then the array "unit" would be <2 NRF_DOMAIN_ID_RADIOCORE 4> + or <2 3 4>. + + sink-channel-links: + type: array + description: | + Mapping of IPCT channels that are mapped between two IPCT instances on + separate domains, in which a channel on this IPCT node is considered + the sink. This array is then comprised of a 3-integer-wide "unit" + that defines one connection of the mapping. The format of this unit + is . Units are sequential + in the array, therefore requiring the length of this property to be + a factor of 3. + + For example, if channel 2 is to be mapped to Radio Core (ID: 3) IPCT + channel 4, then the array "unit" would be <2 NRF_DOMAIN_ID_RADIOCORE 4> + or <2 3 4>. diff --git a/dts/bindings/ipc/nordic,nrf-ipct-global.yaml b/dts/bindings/ipc/nordic,nrf-ipct-global.yaml new file mode 100644 index 00000000000..a1f7776d464 --- /dev/null +++ b/dts/bindings/ipc/nordic,nrf-ipct-global.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: Nordic Global IPCT (Interprocessor Communication Transceiver) + +compatible: "nordic,nrf-ipct-global" + +include: ["nordic,nrf-ipct-common.yaml", "nordic,split-channels.yaml"] + +properties: + global-domain-id: + required: true + type: int + description: | + Global IPCT instances reside on specific buses within the Global Domain, + such as fast and slow, which have different IDs that do not match the + standard Global Domain ID presented in their address. diff --git a/dts/bindings/ipc/nordic,nrf-ipct-local.yaml b/dts/bindings/ipc/nordic,nrf-ipct-local.yaml new file mode 100644 index 00000000000..9f055eb8b79 --- /dev/null +++ b/dts/bindings/ipc/nordic,nrf-ipct-local.yaml @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: Nordic Local IPCT (Interprocessor Communication Transceiver) + +compatible: "nordic,nrf-ipct-local" + +include: "nordic,nrf-ipct-common.yaml" + +properties: + interrupts: + required: true diff --git a/dts/bindings/misc/nordic,nrf-dppic-global.yaml b/dts/bindings/misc/nordic,nrf-dppic-global.yaml new file mode 100644 index 00000000000..3257c519348 --- /dev/null +++ b/dts/bindings/misc/nordic,nrf-dppic-global.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: | + Nordic Global DPPIC + (Distributed Programmable Peripheral Interconnect Controller) + + Updated DPPIC binding set for Nordic products that have global DPPIC instances + with inter-bridge functionality. These instances also have split-ownership + of its channels and channel groups. + +compatible: "nordic,nrf-dppic-global" + +include: + - "nordic,nrf-dppic.yaml" + - "nordic,nrf-dppic-links.yaml" + - "nordic,split-channels.yaml" + - "nordic,split-channel-groups.yaml" diff --git a/dts/bindings/misc/nordic,nrf-dppic-links.yaml b/dts/bindings/misc/nordic,nrf-dppic-links.yaml new file mode 100644 index 00000000000..db12ccb72cb --- /dev/null +++ b/dts/bindings/misc/nordic,nrf-dppic-links.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: Nordic DPPIC Channel Linking + +properties: + source-channels: + type: array + description: | + Channels that are linked to channels of DPPIC instances on separate + bridges as publishing sources. + + sink-channels: + type: array + description: | + Channels that are linked to channels of DPPIC instances on separate + bridges as subscribing sinks. diff --git a/dts/bindings/misc/nordic,nrf-dppic-local.yaml b/dts/bindings/misc/nordic,nrf-dppic-local.yaml new file mode 100644 index 00000000000..bea53bddec8 --- /dev/null +++ b/dts/bindings/misc/nordic,nrf-dppic-local.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +description: | + Nordic Local DPPIC + (Distributed Programmable Peripheral Interconnect Controller) + + Updated DPPIC binding set for Nordic products that have local DPPIC instances + with inter-bridge functionality. + +compatible: "nordic,nrf-dppic-local" + +include: ["nordic,nrf-dppic.yaml", "nordic,nrf-dppic-links.yaml"] diff --git a/dts/bindings/arm/nordic,nrf-dppic.yaml b/dts/bindings/misc/nordic,nrf-dppic.yaml similarity index 100% rename from dts/bindings/arm/nordic,nrf-dppic.yaml rename to dts/bindings/misc/nordic,nrf-dppic.yaml diff --git a/dts/bindings/arm/nordic,nrf-ppi.yaml b/dts/bindings/misc/nordic,nrf-ppi.yaml similarity index 100% rename from dts/bindings/arm/nordic,nrf-ppi.yaml rename to dts/bindings/misc/nordic,nrf-ppi.yaml diff --git a/dts/bindings/misc/nordic,split-channel-groups.yaml b/dts/bindings/misc/nordic,split-channel-groups.yaml new file mode 100644 index 00000000000..868bc5fecec --- /dev/null +++ b/dts/bindings/misc/nordic,split-channel-groups.yaml @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: Nordic Split Channel Groups + +properties: + owned-channel-groups: + type: array + description: | + List of channel groups of a split-ownership peripheral that are to be + owned for use by the compiled domain. + + nonsecure-channel-groups: + type: array + description: | + List of channel groups in a split-ownership, split-security peripheral + that are to be configured as nonsecure. In Trustzone systems, this + property is only evaluated for secure peripherals, as nonsecure channels + are implicitly specified through the owned-channels property. This + property is ignored in non-Trustzone systems. diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi index 70c994ccd06..47aba0df253 100644 --- a/dts/common/nordic/nrf54h20_enga.dtsi +++ b/dts/common/nordic/nrf54h20_enga.dtsi @@ -9,6 +9,12 @@ #include +/* Domain IDs. Can be used to specify channel links in IPCT nodes. */ +#define NRF_DOMAIN_ID_APPLICATION 2 +#define NRF_DOMAIN_ID_RADIOCORE 3 +#define NRF_DOMAIN_ID_GLOBALFAST 12 +#define NRF_DOMAIN_ID_GLOBALSLOW 13 + /delete-node/ &sw_pwm; / { @@ -153,6 +159,15 @@ <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; nordic,ficr-names = "vsup", "coarse", "fine"; }; + + cpuapp_ipct: ipct@13000 { + compatible = "nordic,nrf-ipct-local"; + reg = <0x13000 0x1000>; + status = "disabled"; + channels = <4>; + interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, + <65 NRF_DEFAULT_IRQ_PRIORITY>; + }; }; cpurad_peripherals: peripheral@53000000 { @@ -173,6 +188,21 @@ nordic,ficr-names = "vsup", "coarse", "fine"; }; + dppic020: dppic@22000 { + compatible = "nordic,nrf-dppic-local"; + reg = <0x22000 0x1000>; + status = "disabled"; + }; + + cpurad_ipct: ipct@24000 { + compatible = "nordic,nrf-ipct-local"; + reg = <0x24000 0x1000>; + status = "disabled"; + channels = <8>; + interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, + <65 NRF_DEFAULT_IRQ_PRIORITY>; + }; + egu020: egu@25000 { compatible = "nordic,nrf-egu"; reg = <0x25000 0x1000>; @@ -267,6 +297,20 @@ #mbox-cells = <1>; }; + ipct120: ipct@8d1000 { + compatible = "nordic,nrf-ipct-global"; + reg = <0x8d1000 0x1000>; + status = "disabled"; + channels = <8>; + global-domain-id = <12>; + }; + + dppic120: dppic@8e1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x8e1000 0x1000>; + status = "disabled"; + }; + timer120: timer@8e2000 { compatible = "nordic,nrf-timer"; reg = <0x8e2000 0x1000>; @@ -344,6 +388,20 @@ }; }; + ipct130: ipct@921000 { + compatible = "nordic,nrf-ipct-global"; + reg = <0x921000 0x1000>; + status = "disabled"; + channels = <8>; + global-domain-id = <13>; + }; + + dppic130: dppic@922000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x922000 0x1000>; + status = "disabled"; + }; + rtc130: rtc@928000 { compatible = "nordic,nrf-rtc"; reg = <0x928000 0x1000>; @@ -449,6 +507,12 @@ port = <9>; }; + dppic131: dppic@981000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x981000 0x1000>; + status = "disabled"; + }; + comp: comparator@983000 { compatible = "nordic,nrf-comp"; reg = <0x983000 0x1000>; @@ -471,6 +535,12 @@ interrupts = <389 NRF_DEFAULT_IRQ_PRIORITY>; }; + dppic132: dppic@991000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x991000 0x1000>; + status = "disabled"; + }; + qdec130: qdec@994000 { compatible = "nordic,nrf-qdec"; reg = <0x994000 0x1000>; @@ -492,6 +562,12 @@ cc-num = <16>; }; + dppic133: dppic@9a1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9a1000 0x1000>; + status = "disabled"; + }; + timer130: timer@9a2000 { compatible = "nordic,nrf-timer"; reg = <0x9a2000 0x1000>; @@ -568,6 +644,12 @@ interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; }; + dppic134: dppic@9b1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9b1000 0x1000>; + status = "disabled"; + }; + timer132: timer@9b2000 { compatible = "nordic,nrf-timer"; reg = <0x9b2000 0x1000>; @@ -644,6 +726,12 @@ interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; }; + dppic135: dppic@9c1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9c1000 0x1000>; + status = "disabled"; + }; + timer134: timer@9c2000 { compatible = "nordic,nrf-timer"; reg = <0x9c2000 0x1000>; @@ -720,6 +808,12 @@ interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; }; + dppic136: dppic@9d1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9d1000 0x1000>; + status = "disabled"; + }; + timer136: timer@9d2000 { compatible = "nordic,nrf-timer"; reg = <0x9d2000 0x1000>; From fd9d482e9d8e5708b4474968217838a491533326 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Wed, 6 Mar 2024 12:31:23 +0100 Subject: [PATCH 0522/2402] dts: nordic: Add missing ECB020 node in nRF54H20 EngA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a follow-up to commit 4db40601dd7f0b98a48f3e6072bf44643a4ea3db. There are two ECB instances in nRF54H20 and the above commit added only one of them. Signed-off-by: Andrzej Głąbek --- dts/common/nordic/nrf54h20_enga.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi index 47aba0df253..8552b9534eb 100644 --- a/dts/common/nordic/nrf54h20_enga.dtsi +++ b/dts/common/nordic/nrf54h20_enga.dtsi @@ -210,6 +210,13 @@ interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>; }; + ecb020: ecb@27000 { + compatible = "nordic,nrf-ecb"; + reg = <0x27000 0x1000>; + status = "disabled"; + interrupts = <39 NRF_DEFAULT_IRQ_PRIORITY>; + }; + timer020: timer@28000 { compatible = "nordic,nrf-timer"; reg = <0x28000 0x1000>; From 4991c487d62fe81fcd206050e4d368ab03e22a35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Wed, 6 Mar 2024 12:02:36 +0100 Subject: [PATCH 0523/2402] soc: nordic_nrf: Add address validation entries for nRF54H/L dts nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add entries for checking if the recently added dts nodes for nRF54H20 and nRF54L15 have correct base addresses (if they match those provided by MDK). Signed-off-by: Andrzej Głąbek --- soc/nordic/validate_base_addresses.c | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/soc/nordic/validate_base_addresses.c b/soc/nordic/validate_base_addresses.c index 79083d630dd..e11a4fd3256 100644 --- a/soc/nordic/validate_base_addresses.c +++ b/soc/nordic/validate_base_addresses.c @@ -134,17 +134,39 @@ CHECK_DT_REG(cryptocell, NRF_CRYPTOCELL); CHECK_DT_REG(ctrlap, NRF_CTRLAP); CHECK_DT_REG(dcnf, NRF_DCNF); CHECK_DT_REG(dppic, NRF_DPPIC); +CHECK_DT_REG(dppic00, NRF_DPPIC00); +CHECK_DT_REG(dppic10, NRF_DPPIC10); +CHECK_DT_REG(dppic20, NRF_DPPIC20); +CHECK_DT_REG(dppic30, NRF_DPPIC30); +CHECK_DT_REG(dppic020, NRF_DPPIC020); +CHECK_DT_REG(dppic120, NRF_DPPIC120); +CHECK_DT_REG(dppic130, NRF_DPPIC130); +CHECK_DT_REG(dppic131, NRF_DPPIC131); +CHECK_DT_REG(dppic132, NRF_DPPIC132); +CHECK_DT_REG(dppic133, NRF_DPPIC133); +CHECK_DT_REG(dppic134, NRF_DPPIC134); +CHECK_DT_REG(dppic135, NRF_DPPIC135); +CHECK_DT_REG(dppic136, NRF_DPPIC136); CHECK_DT_REG(ecb, NRF_ECB); +CHECK_DT_REG(ecb020, NRF_ECB020); +CHECK_DT_REG(ecb030, NRF_ECB030); CHECK_DT_REG(egu0, NRF_EGU0); CHECK_DT_REG(egu1, NRF_EGU1); CHECK_DT_REG(egu2, NRF_EGU2); CHECK_DT_REG(egu3, NRF_EGU3); CHECK_DT_REG(egu4, NRF_EGU4); CHECK_DT_REG(egu5, NRF_EGU5); +CHECK_DT_REG(egu10, NRF_EGU10); +CHECK_DT_REG(egu20, NRF_EGU20); +CHECK_DT_REG(egu020, NRF_EGU020); CHECK_DT_REG(ficr, NRF_FICR); CHECK_DT_REG(flash_controller, NRF_NVMC); CHECK_DT_REG(gpio0, NRF_P0); CHECK_DT_REG(gpio1, NRF_P1); +CHECK_DT_REG(gpio2, NRF_P2); +CHECK_DT_REG(gpio6, NRF_P6); +CHECK_DT_REG(gpio7, NRF_P7); +CHECK_DT_REG(gpio9, NRF_P9); CHECK_DT_REG(gpiote, NRF_GPIOTE); CHECK_DT_REG(gpiote0, NRF_GPIOTE0); CHECK_DT_REG(gpiote1, NRF_GPIOTE1); @@ -156,8 +178,25 @@ CHECK_I2C_REG(i2c0, 0); CHECK_I2C_REG(i2c1, 1); CHECK_DT_REG(i2c2, NRF_TWIM2); CHECK_DT_REG(i2c3, NRF_TWIM3); +CHECK_DT_REG(i2c20, NRF_TWIM20); +CHECK_DT_REG(i2c21, NRF_TWIM21); +CHECK_DT_REG(i2c22, NRF_TWIM22); +CHECK_DT_REG(i2c30, NRF_TWIM30); +CHECK_DT_REG(i2c130, NRF_TWIM130); +CHECK_DT_REG(i2c131, NRF_TWIM131); +CHECK_DT_REG(i2c132, NRF_TWIM132); +CHECK_DT_REG(i2c133, NRF_TWIM133); +CHECK_DT_REG(i2c134, NRF_TWIM134); +CHECK_DT_REG(i2c135, NRF_TWIM135); +CHECK_DT_REG(i2c136, NRF_TWIM136); +CHECK_DT_REG(i2c137, NRF_TWIM137); CHECK_DT_REG(i2s0, NRF_I2S0); +CHECK_DT_REG(i2s20, NRF_I2S20); CHECK_DT_REG(ipc, NRF_IPC); +CHECK_DT_REG(cpuapp_ipct, NRF_IPCT); +CHECK_DT_REG(cpurad_ipct, NRF_IPCT); +CHECK_DT_REG(ipct120, NRF_IPCT120); +CHECK_DT_REG(ipct130, NRF_IPCT130); CHECK_DT_REG(kmu, NRF_KMU); CHECK_DT_REG(mutex, NRF_MUTEX); CHECK_DT_REG(mwu, NRF_MWU); @@ -174,18 +213,40 @@ CHECK_DT_REG(pwm3, NRF_PWM3); CHECK_DT_REG(qdec, NRF_QDEC0); /* this should be the same node as qdec0 */ CHECK_DT_REG(qdec0, NRF_QDEC0); CHECK_DT_REG(qdec1, NRF_QDEC1); +CHECK_DT_REG(qdec20, NRF_QDEC20); +CHECK_DT_REG(qdec21, NRF_QDEC21); +CHECK_DT_REG(qdec130, NRF_QDEC130); +CHECK_DT_REG(qdec131, NRF_QDEC131); CHECK_DT_REG(radio, NRF_RADIO); CHECK_DT_REG(regulators, NRF_REGULATORS); CHECK_DT_REG(reset, NRF_RESET); CHECK_DT_REG(rng, NRF_RNG); +CHECK_DT_REG(rtc, NRF_RTC); CHECK_DT_REG(rtc0, NRF_RTC0); CHECK_DT_REG(rtc1, NRF_RTC1); CHECK_DT_REG(rtc2, NRF_RTC2); +CHECK_DT_REG(rtc130, NRF_RTC130); +CHECK_DT_REG(rtc131, NRF_RTC131); CHECK_SPI_REG(spi0, 0); CHECK_SPI_REG(spi1, 1); CHECK_SPI_REG(spi2, 2); CHECK_DT_REG(spi3, NRF_SPIM3); CHECK_DT_REG(spi4, NRF_SPIM4); +CHECK_DT_REG(spi00, NRF_SPIM00); +CHECK_DT_REG(spi20, NRF_SPIM20); +CHECK_DT_REG(spi21, NRF_SPIM21); +CHECK_DT_REG(spi22, NRF_SPIM22); +CHECK_DT_REG(spi30, NRF_SPIM30); +CHECK_DT_REG(spi120, NRF_SPIM120); +CHECK_DT_REG(spi121, NRF_SPIM121); +CHECK_DT_REG(spi130, NRF_SPIM130); +CHECK_DT_REG(spi131, NRF_SPIM131); +CHECK_DT_REG(spi132, NRF_SPIM132); +CHECK_DT_REG(spi133, NRF_SPIM133); +CHECK_DT_REG(spi134, NRF_SPIM134); +CHECK_DT_REG(spi135, NRF_SPIM135); +CHECK_DT_REG(spi136, NRF_SPIM136); +CHECK_DT_REG(spi137, NRF_SPIM137); CHECK_DT_REG(spu, NRF_SPU); CHECK_DT_REG(swi0, NRF_SWI0); CHECK_DT_REG(swi1, NRF_SWI1); @@ -206,6 +267,19 @@ CHECK_DT_REG(timer21, NRF_TIMER21); CHECK_DT_REG(timer22, NRF_TIMER22); CHECK_DT_REG(timer23, NRF_TIMER23); CHECK_DT_REG(timer24, NRF_TIMER24); +CHECK_DT_REG(timer020, NRF_TIMER020); +CHECK_DT_REG(timer021, NRF_TIMER021); +CHECK_DT_REG(timer022, NRF_TIMER022); +CHECK_DT_REG(timer120, NRF_TIMER120); +CHECK_DT_REG(timer121, NRF_TIMER121); +CHECK_DT_REG(timer130, NRF_TIMER130); +CHECK_DT_REG(timer131, NRF_TIMER131); +CHECK_DT_REG(timer132, NRF_TIMER132); +CHECK_DT_REG(timer133, NRF_TIMER133); +CHECK_DT_REG(timer134, NRF_TIMER134); +CHECK_DT_REG(timer135, NRF_TIMER135); +CHECK_DT_REG(timer136, NRF_TIMER136); +CHECK_DT_REG(timer137, NRF_TIMER137); CHECK_UART_REG(uart0, 0); CHECK_DT_REG(uart1, NRF_UARTE1); CHECK_DT_REG(uart2, NRF_UARTE2); @@ -233,6 +307,8 @@ CHECK_DT_REG(wdt0, NRF_WDT0); CHECK_DT_REG(wdt1, NRF_WDT1); CHECK_DT_REG(wdt30, NRF_WDT30); CHECK_DT_REG(wdt31, NRF_WDT31); +CHECK_DT_REG(wdt131, NRF_WDT131); +CHECK_DT_REG(wdt132, NRF_WDT132); /* nRF51/nRF52-specific addresses */ #if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X) From 54014f503c3ef80730a17af36d29762db84a8af0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Tue, 5 Mar 2024 15:34:32 +0100 Subject: [PATCH 0524/2402] manifest: Update hal_nordic revision MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pull in fixes in the nrfx_gppi_dppi_ppib helper so that it can be compiled successfuly. Signed-off-by: Andrzej Głąbek --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 6a32031c1e6..093e3e0d6e9 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: daf875285120be6b2825969b7a0abc3f415b248d + revision: 5470822384781624efb2fda28cbc6a895a227677 path: modules/hal/nordic groups: - hal From 6692d880e90de848d2bc03c95d3c904efa9cdbf5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Fri, 1 Mar 2024 11:16:28 +0100 Subject: [PATCH 0525/2402] modules: hal_nordic: Enable support for DPPI on nRF54H20 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include into compilation the nrfx_gppi_dppi_ppib helper and related interconnect layers when DPPIC nodes are enabled in DTS. Provide macro definitions required by those interconnect layers based on information from devicetree (the nrf_grtc_timer is only modified because a macro that it uses became more generic). Signed-off-by: Andrzej Głąbek --- drivers/timer/nrf_grtc_timer.c | 4 +- modules/hal_nordic/nrfx/CMakeLists.txt | 8 ++ modules/hal_nordic/nrfx/nrfx_config.h | 121 +++++++++++++++++++++++-- 3 files changed, 121 insertions(+), 12 deletions(-) diff --git a/drivers/timer/nrf_grtc_timer.c b/drivers/timer/nrf_grtc_timer.c index 8ac357864cc..c9e51db2469 100644 --- a/drivers/timer/nrf_grtc_timer.c +++ b/drivers/timer/nrf_grtc_timer.c @@ -21,8 +21,8 @@ #if !DT_NODE_HAS_PROP(GRTC_NODE, owned_channels) #error GRTC owned-channels DT property is not defined #endif -#define OWNED_CHANNELS_MASK NRFX_CONFIG_GRTC_MASK_DT(owned_channels) -#define CHILD_OWNED_CHANNELS_MASK NRFX_CONFIG_GRTC_MASK_DT(child_owned_channels) +#define OWNED_CHANNELS_MASK NRFX_CONFIG_MASK_DT(GRTC_NODE, owned_channels) +#define CHILD_OWNED_CHANNELS_MASK NRFX_CONFIG_MASK_DT(GRTC_NODE, child_owned_channels) #if ((OWNED_CHANNELS_MASK | CHILD_OWNED_CHANNELS_MASK) != OWNED_CHANNELS_MASK) #error GRTC child-owned-channels DT property must be a subset of owned-channels #endif diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index 4db5ac891fe..13ee18db7a6 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -163,6 +163,14 @@ if(CONFIG_SOC_SERIES_NRF54LX AND CONFIG_NRFX_DPPI) zephyr_library_sources(${NRFX_DIR}/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib.c) endif() +if(CONFIG_SOC_SERIES_NRF54HX AND + (CONFIG_DT_HAS_NORDIC_NRF_DPPIC_LOCAL_ENABLED OR + CONFIG_DT_HAS_NORDIC_NRF_DPPIC_GLOBAL_ENABLED)) + zephyr_library_sources(${HELPERS_DIR}/nrfx_gppi_dppi_ppib.c) + zephyr_library_sources(${NRFX_DIR}/soc/interconnect/apb/nrfx_interconnect_apb.c) + zephyr_library_sources(${NRFX_DIR}/soc/interconnect/ipct/nrfx_interconnect_ipct.c) +endif() + # Get the SVD file for the current SoC macro(mdk_svd_ifdef feature_toggle filename) if(${feature_toggle}) diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index 3c923f738a9..46d4ac9538f 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -8,6 +8,7 @@ #define NRFX_CONFIG_H__ #include +#include /* * These are mappings of Kconfig options enabling nrfx drivers and particular @@ -798,27 +799,127 @@ #define NRF_PERIPH(P) P##_S #endif +#define NRFX_CONFIG_BIT_DT(node_id, prop, idx) BIT(DT_PROP_BY_IDX(node_id, prop, idx)) +#define NRFX_CONFIG_MASK_DT(node_id, prop) \ + (COND_CODE_1(DT_NODE_HAS_PROP(node_id, prop), \ + (DT_FOREACH_PROP_ELEM_SEP(node_id, prop, NRFX_CONFIG_BIT_DT, (|))), \ + (0))) + /* If the GRTC system timer driver is to be used, prepare definitions required * by the nrfx_grtc driver (NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK and * NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS) based on information from devicetree. */ #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_grtc) -#define NRFX_CONFIG_BIT_DT(node_id, prop, idx) \ - BIT(DT_PROP_BY_IDX(node_id, prop, idx)) -#define NRFX_CONFIG_GRTC_MASK_DT(prop) \ - (COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(0, nordic_nrf_grtc), prop), \ - (DT_FOREACH_PROP_ELEM_SEP(DT_INST(0, nordic_nrf_grtc), prop, \ - NRFX_CONFIG_BIT_DT, (|))), \ - (0))) - #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK \ - (NRFX_CONFIG_GRTC_MASK_DT(owned_channels) & \ - ~NRFX_CONFIG_GRTC_MASK_DT(child_owned_channels)) + (NRFX_CONFIG_MASK_DT(DT_INST(0, nordic_nrf_grtc), owned_channels) & \ + ~NRFX_CONFIG_MASK_DT(DT_INST(0, nordic_nrf_grtc), child_owned_channels)) #define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS \ (DT_PROP_LEN_OR(DT_INST(0, nordic_nrf_grtc), owned_channels, 0) - \ DT_PROP_LEN_OR(DT_INST(0, nordic_nrf_grtc), child_owned_channels, 0)) #endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_grtc) */ +/* If global of local DPPIC peripherals are used, provide the following macro + * definitions required by the interconnect/apb layer: + * - NRFX_DPPI_PUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) + * - NRFX_DPPI_SUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) + * - NRFX_DPPI_PUB_OR_SUB_MASK(inst_num) + * - NRFX_DPPI_CHANNELS_SINGLE_VAR_NAME_BY_INST_NUM(inst_num) + * - NRFX_INTERCONNECT_APB_GLOBAL_DPPI_DEFINE + * - NRFX_INTERCONNECT_APB_LOCAL_DPPI_DEFINE + * based on information from devicetree. + */ +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_dppic_global) || \ + DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_dppic_local) +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 1 +#endif +/* Source (publish) channels masks generation. */ +#define NRFX_DPPI_PUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) \ + NRFX_CONFIG_MASK_DT(DT_NODELABEL(_CONCAT(dppic, inst_num)), source_channels) + +/* Sink (subscribe) channels masks generation. */ +#define NRFX_DPPI_SUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) \ + NRFX_CONFIG_MASK_DT(DT_NODELABEL(_CONCAT(dppic, inst_num)), sink_channels) + +#define NRFX_DPPI_PUB_OR_SUB_MASK(inst_num) \ + UTIL_OR(DT_NODE_HAS_PROP(DT_NODELABEL(_CONCAT(dppic, inst_num)), source_channels), \ + DT_NODE_HAS_PROP(DT_NODELABEL(_CONCAT(dppic, inst_num)), sink_channels)) + +/* Variables names generation. */ +#define NRFX_CONFIG_DPPI_CHANNELS_ENTRY_NAME(node_id) _CONCAT(_CONCAT(m_, node_id), _channels) +#define NRFX_DPPI_CHANNELS_SINGLE_VAR_NAME_BY_INST_NUM(inst_num) \ + NRFX_CONFIG_DPPI_CHANNELS_ENTRY_NAME(DT_NODELABEL(_CONCAT(dppic, inst_num))) + +/* Variables entries generation. */ +#define NRFX_CONFIG_DPPI_CHANNELS_ENTRY(node_id) \ + static nrfx_atomic_t NRFX_CONFIG_DPPI_CHANNELS_ENTRY_NAME(node_id) \ + __attribute__((used)) = \ + NRFX_CONFIG_MASK_DT(node_id, source_channels) | \ + NRFX_CONFIG_MASK_DT(node_id, sink_channels); +#define NRFX_INTERCONNECT_APB_GLOBAL_DPPI_DEFINE \ + DT_FOREACH_STATUS_OKAY(nordic_nrf_dppic_global, NRFX_CONFIG_DPPI_CHANNELS_ENTRY) +#define NRFX_INTERCONNECT_APB_LOCAL_DPPI_DEFINE \ + DT_FOREACH_STATUS_OKAY(nordic_nrf_dppic_local, NRFX_CONFIG_DPPI_CHANNELS_ENTRY) +#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_dppic_global) || ... */ + +/* If local or global DPPIC peripherals are used, provide the following macro + * definitions required by the interconnect/ipct layer: + * - NRFX_IPCTx_PUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) + * - NRFX_IPCTx_SUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) + * - NRFX_IPCT_PUB_OR_SUB_MASK(inst_num) + * - NRFX_IPCTx_CHANNELS_SINGLE_VAR_NAME_BY_INST_NUM(inst_num) + * - NRFX_INTERCONNECT_IPCT_GLOBAL_DEFINE + * - NRFX_INTERCONNECT_IPCT_LOCAL_DEFINE + * based on information from devicetree. + */ +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_ipct_global) || \ + DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_ipct_local) +/* Channels masks generation. */ +#define NRFX_CONFIG_IPCT_MASK_DT(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, owned_channels), \ + (NRFX_CONFIG_MASK_DT(node_id, owned_channels)), \ + (COND_CODE_1(DT_NODE_HAS_COMPAT(node_id, nordic_nrf_ipct_local), \ + (BIT_MASK(DT_PROP(node_id, channels))), (0)))) + +#if defined(NRF_APPLICATION) +#define NRFX_CONFIG_IPCT_LOCAL_NODE DT_NODELABEL(cpuapp_ipct) +#elif defined(NRF_RADIOCORE) +#define NRFX_CONFIG_IPCT_LOCAL_NODE DT_NODELABEL(cpurad_ipct) +#endif +#define NRFX_CONFIG_IPCT_NODE_BY_INST_NUM(inst_num) \ + COND_CODE_1(IS_EMPTY(inst_num), \ + (NRFX_CONFIG_IPCT_LOCAL_NODE), \ + (DT_NODELABEL(_CONCAT(ipct, inst_num)))) + +#define NRFX_IPCTx_PUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) \ + NRFX_CONFIG_IPCT_MASK_DT(NRFX_CONFIG_IPCT_NODE_BY_INST_NUM(inst_num)) + +#define NRFX_IPCTx_SUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) \ + NRFX_CONFIG_IPCT_MASK_DT(NRFX_CONFIG_IPCT_NODE_BY_INST_NUM(inst_num)) + +#define NRFX_IPCT_PUB_OR_SUB_MASK(inst_num) \ + COND_CODE_1(IS_EMPTY(inst_num), \ + (DT_NODE_HAS_STATUS(NRFX_CONFIG_IPCT_LOCAL_NODE, okay)), \ + (DT_NODE_HAS_PROP(DT_NODELABEL(_CONCAT(ipct, inst_num)), owned_channels))) + +/* Variables names generation. */ +#define NRFX_CONFIG_IPCT_CHANNELS_ENTRY_NAME(node_id) _CONCAT(_CONCAT(m_, node_id), _channels) +#define NRFX_IPCTx_CHANNELS_SINGLE_VAR_NAME_BY_INST_NUM(inst_num) \ + COND_CODE_1(IS_EMPTY(inst_num), \ + (NRFX_CONFIG_IPCT_CHANNELS_ENTRY_NAME(NRFX_CONFIG_IPCT_LOCAL_NODE)), \ + (NRFX_CONFIG_IPCT_CHANNELS_ENTRY_NAME(DT_NODELABEL(_CONCAT(ipct, inst_num))))) + +/* Variables entries generation. */ +#define NRFX_CONFIG_IPCT_CHANNELS_ENTRY(node_id) \ + static nrfx_atomic_t NRFX_CONFIG_IPCT_CHANNELS_ENTRY_NAME(node_id) \ + __attribute__((used)) = \ + NRFX_CONFIG_IPCT_MASK_DT(node_id); +#define NRFX_INTERCONNECT_IPCT_LOCAL_DEFINE \ + DT_FOREACH_STATUS_OKAY(nordic_nrf_ipct_local, NRFX_CONFIG_IPCT_CHANNELS_ENTRY) +#define NRFX_INTERCONNECT_IPCT_GLOBAL_DEFINE \ + DT_FOREACH_STATUS_OKAY(nordic_nrf_ipct_global, NRFX_CONFIG_IPCT_CHANNELS_ENTRY) +#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_ipct_global) || ... */ + #include #if defined(NRF51) #include From 9c500a8a827d24d13ae720298d22a4467eb1214a Mon Sep 17 00:00:00 2001 From: Dat Nguyen Duy Date: Tue, 12 Mar 2024 08:58:24 +0700 Subject: [PATCH 0526/2402] drivers: mbox: fix build failures when userspace enabled Fix build failures due to using wrong arguments when calling the implementation functions Signed-off-by: Dat Nguyen Duy --- drivers/mbox/mbox_handlers.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mbox/mbox_handlers.c b/drivers/mbox/mbox_handlers.c index c8788907d33..2340ab016b5 100644 --- a/drivers/mbox/mbox_handlers.c +++ b/drivers/mbox/mbox_handlers.c @@ -15,7 +15,7 @@ static inline int z_vrfy_mbox_send(const struct device *dev, K_OOPS(K_SYSCALL_MEMORY_READ(msg, sizeof(struct mbox_msg))); K_OOPS(K_SYSCALL_MEMORY_READ(msg->data, msg->size)); - return z_impl_mbox_send(channel, msg); + return z_impl_mbox_send(dev, channel_id, msg); } #include @@ -41,6 +41,6 @@ static inline int z_vrfy_mbox_set_enabled(const struct device *dev, { K_OOPS(K_SYSCALL_DRIVER_MBOX(dev, set_enabled)); - return z_impl_mbox_set_enabled(channel_id, enabled); + return z_impl_mbox_set_enabled(dev, channel_id, enabled); } #include From dae5c2995910fb45997eb4f838c8ef455c6906e7 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 6 Mar 2024 11:58:05 -0600 Subject: [PATCH 0527/2402] boards: nxp: lpcxpresso55s69: fix TF-M support Fix TF-M support for lpcxpresso55s69 target. The following issues were resolved: - lpcxpresso55s69 ns defconfig did not explicitly disable CONFIG_TRUSTED_EXECUTION_SECURE (which is set in the secure cpu0 defconfig file) - CONFIG_TFM_BOARD was not being set correctly for the NS target Signed-off-by: Daniel DeGrasse --- .../lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig | 1 + modules/trusted-firmware-m/Kconfig.tfm | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig index b93da92c709..11924b6c377 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig @@ -12,6 +12,7 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_ARM_MPU=n # Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=n CONFIG_TRUSTED_EXECUTION_NONSECURE=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_BUILD_WITH_TFM=y diff --git a/modules/trusted-firmware-m/Kconfig.tfm b/modules/trusted-firmware-m/Kconfig.tfm index 6d3b8a40c04..171ad654307 100644 --- a/modules/trusted-firmware-m/Kconfig.tfm +++ b/modules/trusted-firmware-m/Kconfig.tfm @@ -9,7 +9,7 @@ config ZEPHYR_TRUSTED_FIRMWARE_M_MODULE config TFM_BOARD string - default "nxp/lpcxpresso55s69" if BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 + default "nxp/lpcxpresso55s69" if BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS default "arm/mps2/an521" if BOARD_MPS2_AN521_CPU0_NS default "arm/mps3/an547" if BOARD_MPS3_AN547 default "stm/b_u585i_iot02a" if BOARD_B_U585I_IOT02A From fe2b03178ab9319ed676f2fc67f4081766b2470c Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Fri, 8 Mar 2024 13:52:09 +0000 Subject: [PATCH 0528/2402] gpio: pcal64xxa: switch to 8 bit internal data automatically Convert the internal uint16_t data of the driver to an internal type that automatically switches from uint8_t to uint16_t depending on whether any 16 bit device is present in the system or not. This shrinks the internal structures by few bytes when the extra data is not needed. Signed-off-by: Fabio Baltieri --- drivers/gpio/gpio_pcal64xxa.c | 85 ++++++++++++++++++++--------------- 1 file changed, 49 insertions(+), 36 deletions(-) diff --git a/drivers/gpio/gpio_pcal64xxa.c b/drivers/gpio/gpio_pcal64xxa.c index 3fb7d560fea..687cf53c1bf 100644 --- a/drivers/gpio/gpio_pcal64xxa.c +++ b/drivers/gpio/gpio_pcal64xxa.c @@ -54,17 +54,29 @@ enum pcal6416a_register { PCAL6416A_REG_OUTPUT_PORT_CONFIGURATION = 0x4F, }; +#if DT_HAS_COMPAT_STATUS_OKAY(nxp_pcal6416a) +typedef uint16_t pcal64xxa_data_t; +#define PCAL64XXA_INIT_HIGH UINT16_MAX +#define PRIpcal_data "04" PRIx16 +#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_pcal6408a) +typedef uint8_t pcal64xxa_data_t; +#define PCAL64XXA_INIT_HIGH UINT8_MAX +#define PRIpcal_data "02" PRIx8 +#else +#error "Cannot determine the internal data type size" +#endif + struct pcal64xxa_pins_cfg { - uint16_t configured_as_inputs; - uint16_t outputs_high; - uint16_t pull_ups_selected; - uint16_t pulls_enabled; + pcal64xxa_data_t configured_as_inputs; + pcal64xxa_data_t outputs_high; + pcal64xxa_data_t pull_ups_selected; + pcal64xxa_data_t pulls_enabled; }; struct pcal64xxa_triggers { - uint16_t masked; - uint16_t dual_edge; - uint16_t on_low; + pcal64xxa_data_t masked; + pcal64xxa_data_t dual_edge; + pcal64xxa_data_t on_low; }; struct pcal64xxa_drv_data { @@ -78,7 +90,7 @@ struct pcal64xxa_drv_data { struct gpio_callback int_gpio_cb; struct pcal64xxa_pins_cfg pins_cfg; struct pcal64xxa_triggers triggers; - uint16_t input_port_last; + pcal64xxa_data_t input_port_last; }; typedef int (*pcal64xxa_pins_cfg_apply)(const struct i2c_dt_spec *i2c, @@ -86,9 +98,9 @@ typedef int (*pcal64xxa_pins_cfg_apply)(const struct i2c_dt_spec *i2c, typedef int (*pcal64xxa_triggers_apply)(const struct i2c_dt_spec *i2c, const struct pcal64xxa_triggers *triggers); typedef int (*pcal64xxa_reset_state_apply)(const struct i2c_dt_spec *i2c); -typedef int (*pcal64xxa_inputs_read)(const struct i2c_dt_spec *i2c, uint16_t *int_sources, - uint16_t *input_port); -typedef int (*pcal64xxa_outputs_write)(const struct i2c_dt_spec *i2c, uint16_t outputs); +typedef int (*pcal64xxa_inputs_read)(const struct i2c_dt_spec *i2c, pcal64xxa_data_t *int_sources, + pcal64xxa_data_t *input_port); +typedef int (*pcal64xxa_outputs_write)(const struct i2c_dt_spec *i2c, pcal64xxa_data_t outputs); struct pcal64xxa_chip_api { pcal64xxa_pins_cfg_apply pins_cfg_apply; @@ -183,8 +195,8 @@ static int pcal64xxa_process_input(const struct device *dev, gpio_port_value_t * const struct pcal64xxa_drv_cfg *drv_cfg = dev->config; struct pcal64xxa_drv_data *drv_data = dev->data; int rc; - uint16_t int_sources; - uint16_t input_port; + pcal64xxa_data_t int_sources; + pcal64xxa_data_t input_port; k_sem_take(&drv_data->lock, K_FOREVER); @@ -211,9 +223,10 @@ static int pcal64xxa_process_input(const struct device *dev, gpio_port_value_t * drv_data->input_port_last = input_port; if (int_sources) { - uint16_t dual_edge_triggers = drv_data->triggers.dual_edge; - uint16_t falling_edge_triggers = (~dual_edge_triggers & drv_data->triggers.on_low); - uint16_t fired_triggers = 0; + pcal64xxa_data_t dual_edge_triggers = drv_data->triggers.dual_edge; + pcal64xxa_data_t falling_edge_triggers = + ~dual_edge_triggers & drv_data->triggers.on_low; + pcal64xxa_data_t fired_triggers = 0; /* For dual edge triggers, react to all state changes. */ fired_triggers |= (int_sources & dual_edge_triggers); @@ -271,16 +284,16 @@ static int pcal64xxa_port_get_raw(const struct device *dev, gpio_port_value_t *v return rc; } -static int pcal64xxa_port_set_raw(const struct device *dev, uint16_t mask, uint16_t value, - uint16_t toggle) +static int pcal64xxa_port_set_raw(const struct device *dev, pcal64xxa_data_t mask, + pcal64xxa_data_t value, pcal64xxa_data_t toggle) { const struct pcal64xxa_drv_cfg *drv_cfg = dev->config; struct pcal64xxa_drv_data *drv_data = dev->data; int rc; - uint16_t output; + pcal64xxa_data_t output; - LOG_DBG("setting port with mask 0x%04X with value 0x%04X and toggle 0x%04X", mask, value, - toggle); + LOG_DBG("setting port with mask 0x%" PRIpcal_data " with value 0x%" PRIpcal_data + " and toggle 0x%" PRIpcal_data, mask, value, toggle); if (k_is_in_isr()) { return -EWOULDBLOCK; @@ -313,22 +326,22 @@ static int pcal64xxa_port_set_raw(const struct device *dev, uint16_t mask, uint1 static int pcal64xxa_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, gpio_port_value_t value) { - return pcal64xxa_port_set_raw(dev, (uint16_t)mask, (uint16_t)value, 0); + return pcal64xxa_port_set_raw(dev, (pcal64xxa_data_t)mask, (pcal64xxa_data_t)value, 0); } static int pcal64xxa_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) { - return pcal64xxa_port_set_raw(dev, (uint16_t)pins, (uint16_t)pins, 0); + return pcal64xxa_port_set_raw(dev, (pcal64xxa_data_t)pins, (pcal64xxa_data_t)pins, 0); } static int pcal64xxa_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) { - return pcal64xxa_port_set_raw(dev, (uint16_t)pins, 0, 0); + return pcal64xxa_port_set_raw(dev, (pcal64xxa_data_t)pins, 0, 0); } static int pcal64xxa_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) { - return pcal64xxa_port_set_raw(dev, 0, 0, (uint16_t)pins); + return pcal64xxa_port_set_raw(dev, 0, 0, (pcal64xxa_data_t)pins); } static int pcal64xxa_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, @@ -458,8 +471,8 @@ static int pcal6408a_pins_cfg_apply(const struct i2c_dt_spec *i2c, return 0; } -static int pcal6408a_inputs_read(const struct i2c_dt_spec *i2c, uint16_t *int_sources, - uint16_t *input_port) +static int pcal6408a_inputs_read(const struct i2c_dt_spec *i2c, pcal64xxa_data_t *int_sources, + pcal64xxa_data_t *input_port) { int rc; uint8_t value; @@ -482,7 +495,7 @@ static int pcal6408a_inputs_read(const struct i2c_dt_spec *i2c, uint16_t *int_so return 0; } -static int pcal6408a_outputs_write(const struct i2c_dt_spec *i2c, uint16_t outputs) +static int pcal6408a_outputs_write(const struct i2c_dt_spec *i2c, pcal64xxa_data_t outputs) { int rc; @@ -608,8 +621,8 @@ static int pcal6416a_pins_cfg_apply(const struct i2c_dt_spec *i2c, return 0; } -static int pcal6416a_inputs_read(const struct i2c_dt_spec *i2c, uint16_t *int_sources, - uint16_t *input_port) +static int pcal6416a_inputs_read(const struct i2c_dt_spec *i2c, pcal64xxa_data_t *int_sources, + pcal64xxa_data_t *input_port) { int rc; uint8_t value_low; @@ -644,7 +657,7 @@ static int pcal6416a_inputs_read(const struct i2c_dt_spec *i2c, uint16_t *int_so return 0; } -static int pcal6416a_outputs_write(const struct i2c_dt_spec *i2c, uint16_t outputs) +static int pcal6416a_outputs_write(const struct i2c_dt_spec *i2c, pcal64xxa_data_t outputs) { int rc; @@ -673,8 +686,8 @@ static int pcal6416a_triggers_apply(const struct i2c_dt_spec *i2c, const struct pcal64xxa_triggers *triggers) { int rc; - uint16_t input_latch = ~triggers->masked; - uint16_t interrupt_mask = triggers->masked; + pcal64xxa_data_t input_latch = ~triggers->masked; + pcal64xxa_data_t interrupt_mask = triggers->masked; rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_INPUT_LATCH_0, (uint8_t)input_latch); if (rc != 0) { @@ -742,16 +755,16 @@ int pcal64xxa_init(const struct device *dev) const struct pcal64xxa_drv_cfg *drv_cfg = dev->config; struct pcal64xxa_drv_data *drv_data = dev->data; const struct pcal64xxa_pins_cfg initial_pins_cfg = { - .configured_as_inputs = 0xFFFF, + .configured_as_inputs = PCAL64XXA_INIT_HIGH, .outputs_high = 0, .pull_ups_selected = 0, .pulls_enabled = 0, }; const struct pcal64xxa_triggers initial_triggers = { - .masked = 0xFFFF, + .masked = PCAL64XXA_INIT_HIGH, }; int rc; - uint16_t int_sources; + pcal64xxa_data_t int_sources; LOG_DBG("initializing PCAL64XXA"); From 68616f23d8bd3802faa91514fe028c88d5f3846a Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 16 Feb 2024 15:59:44 +0100 Subject: [PATCH 0529/2402] boards: nucleo_h563zi: Enable I2C Enable i2c1 on nucleo_h563zi (arduino_i2c). Additionally provide a test configuration for i2c_target_api. Signed-off-by: Erwan Gouriou --- .../nucleo_h563zi/arduino_r3_connector.dtsi | 1 + boards/st/nucleo_h563zi/doc/index.rst | 2 ++ .../nucleo_h563zi/nucleo_h563zi-common.dtsi | 6 ++++ boards/st/nucleo_h563zi/nucleo_h563zi.yaml | 1 + .../i2c_target_api/boards/nucleo_h563zi.conf | 2 ++ .../boards/nucleo_h563zi.overlay | 36 +++++++++++++++++++ 6 files changed, 48 insertions(+) create mode 100644 tests/drivers/i2c/i2c_target_api/boards/nucleo_h563zi.conf create mode 100644 tests/drivers/i2c/i2c_target_api/boards/nucleo_h563zi.overlay diff --git a/boards/st/nucleo_h563zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h563zi/arduino_r3_connector.dtsi index cb56530d7e8..fa2515d6d0b 100644 --- a/boards/st/nucleo_h563zi/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h563zi/arduino_r3_connector.dtsi @@ -38,3 +38,4 @@ arduino_serial: &lpuart1 {}; arduino_spi: &spi1 {}; +arduino_i2c: &i2c1 {}; diff --git a/boards/st/nucleo_h563zi/doc/index.rst b/boards/st/nucleo_h563zi/doc/index.rst index 9be05804330..e707e81fefa 100644 --- a/boards/st/nucleo_h563zi/doc/index.rst +++ b/boards/st/nucleo_h563zi/doc/index.rst @@ -168,6 +168,8 @@ The Zephyr nucleo_h563zi board configuration supports the following hardware fea +-----------+------------+-------------------------------------+ | SPI | on-chip | spi bus | +-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c bus | ++-----------+------------+-------------------------------------+ | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi index 9ffb5c9fc0c..28b72527179 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi +++ b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi @@ -72,6 +72,12 @@ status = "okay"; }; +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; + pinctrl-names = "default"; + status = "okay"; +}; + &rcc { clocks = <&pll>; clock-frequency = ; diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi.yaml b/boards/st/nucleo_h563zi/nucleo_h563zi.yaml index 9e04cd2b7de..0130798df9d 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi.yaml +++ b/boards/st/nucleo_h563zi/nucleo_h563zi.yaml @@ -22,4 +22,5 @@ supported: - usb_device - usb - rtc + - i2c vendor: st diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_h563zi.conf b/tests/drivers/i2c/i2c_target_api/boards/nucleo_h563zi.conf new file mode 100644 index 00000000000..34b2571d125 --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_h563zi.conf @@ -0,0 +1,2 @@ +CONFIG_I2C_STM32_INTERRUPT=y +CONFIG_I2C_VIRTUAL=n diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_h563zi.overlay b/tests/drivers/i2c/i2c_target_api/boards/nucleo_h563zi.overlay new file mode 100644 index 00000000000..02574be9b3e --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_h563zi.overlay @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2020 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +/* I2C bus pins are exposed on the ST morpho header. + * + * Bus SDA SCL + * Pin Hdr Pin Hdr + * i2c1 PB9 CN7:4 PB8 CN7:2 + * i2c2 PB11 CN10:34 PB10 CN10:32 + * + * Short Pin PB9 to PB11, and PB8 to PB10, for the test to pass. + */ + +&i2c2 { + pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>; + pinctrl-names = "default"; + status = "okay"; + eeprom0: eeprom@54 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x54>; + size = <1024>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; + pinctrl-names = "default"; + status = "okay"; + eeprom1: eeprom@56 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x56>; + size = <1024>; + }; +}; From 456183f982923446d8b40b32d79a9a2d24d37ab8 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 16 Feb 2024 17:25:13 +0100 Subject: [PATCH 0530/2402] boards: nucleo_h563zi: Fix APB1 bus clock 240MHz as APB1 bus clock is too fast to set I2C base bus speed. Set bus pre-scaler to 2 and reach a safe 120MHz. Signed-off-by: Erwan Gouriou --- boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi index 28b72527179..35fb42aedfa 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi +++ b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi @@ -82,7 +82,7 @@ clocks = <&pll>; clock-frequency = ; ahb-prescaler = <1>; - apb1-prescaler = <1>; + apb1-prescaler = <2>; apb2-prescaler = <1>; apb3-prescaler = <1>; }; From 749c0e41b921649eac2a37828f7964bb2eaa02b3 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 16 Feb 2024 17:39:08 +0100 Subject: [PATCH 0531/2402] boards: stm32h573i_dk: Enable I2C Enable i2c1 on stm32h573i_dk (arduino_i2c). Additionally provide a test configuration for i2c_target_api. Signed-off-by: Erwan Gouriou --- .../st/stm32h573i_dk/arduino_r3_connector.dtsi | 1 + boards/st/stm32h573i_dk/doc/index.rst | 16 ++-------------- boards/st/stm32h573i_dk/stm32h573i_dk.dts | 7 +++++++ boards/st/stm32h573i_dk/stm32h573i_dk.yaml | 1 + 4 files changed, 11 insertions(+), 14 deletions(-) diff --git a/boards/st/stm32h573i_dk/arduino_r3_connector.dtsi b/boards/st/stm32h573i_dk/arduino_r3_connector.dtsi index 87f3e6332df..71ec00853d2 100644 --- a/boards/st/stm32h573i_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32h573i_dk/arduino_r3_connector.dtsi @@ -36,3 +36,4 @@ }; arduino_spi: &spi2 {}; +arduino_i2c: &i2c1 {}; diff --git a/boards/st/stm32h573i_dk/doc/index.rst b/boards/st/stm32h573i_dk/doc/index.rst index f7e0a7adbbe..81d7e1ae002 100644 --- a/boards/st/stm32h573i_dk/doc/index.rst +++ b/boards/st/stm32h573i_dk/doc/index.rst @@ -183,6 +183,8 @@ hardware features: +-----------+------------+-------------------------------------+ | RTC | on-chip | Real Time Clock | +-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c bus | ++-----------+------------+-------------------------------------+ | SPI | on-chip | spi bus | +-----------+------------+-------------------------------------+ | OCTOSPI | on-chip | octospi | @@ -203,20 +205,6 @@ The default configuration can be found in the defconfig and dts files: - :zephyr_file:`boards/st/stm32h573i_dk/stm32h573i_dk_defconfig` - :zephyr_file:`boards/st/stm32h573i_dk/stm32h573i_dk.dts` -Zephyr board options -==================== - -The STM32H573 is an SoC with Cortex-M33 architecture. Zephyr provides support -for building for Secure firmware. - -The BOARD options are summarized below: - -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| stm32h573i_dk | For building Secure firmware | -+----------------------+-----------------------------------------------+ - Connections and IOs =================== diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts index e474977e5a6..46dc702c985 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts @@ -96,6 +96,13 @@ apb3-prescaler = <1>; }; +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; pinctrl-names = "default"; diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.yaml b/boards/st/stm32h573i_dk/stm32h573i_dk.yaml index 421f61c71e7..63ec297be26 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.yaml +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.yaml @@ -23,4 +23,5 @@ supported: - can - usb_device - usb + - i2c vendor: st From caf4a2933896dedff02b478ca67944077d8aad5a Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 16 Feb 2024 17:39:40 +0100 Subject: [PATCH 0532/2402] boards: stm32h573i_dk: Fix APB1 bus clock 240MHz as APB1 bus clock is too fast to set I2C base bus speed. Set bus pre-scaler to 2 and reach a safe 120MHz. Signed-off-by: Erwan Gouriou --- boards/st/stm32h573i_dk/stm32h573i_dk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts index 46dc702c985..78a687cfd13 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts @@ -91,7 +91,7 @@ clocks = <&pll>; clock-frequency = ; ahb-prescaler = <1>; - apb1-prescaler = <1>; + apb1-prescaler = <2>; apb2-prescaler = <1>; apb3-prescaler = <1>; }; From 98903d48c3fcd5cd8789c51ac27953e455a7062d Mon Sep 17 00:00:00 2001 From: Yasushi SHOJI Date: Mon, 15 Jan 2024 16:11:57 +0900 Subject: [PATCH 0533/2402] drivers: sensor: ams_as5600: Fix calculation of fractional part The original calculation has two bugs. One is the calculated value, and the other is that the value is not in one-millionth parts. What the original calculation does is compute a scaled position value by multiplying the raw sensor value (`dev_data->position`) by `AS5600_FULL_ANGLE`, which represents a full rotation in degrees. It then subtracts the product of the whole number of pulses (`val->val1`) and `AS5600_PULSES_PER_REV` from this scaled position value. ((int32_t)dev_data->position * AS5600_FULL_ANGLE) - (val->val1 * AS5600_PULSES_PER_REV); What you actually need is to extract the fractional part of the value by taking the modulo of AS5600_PULSES_PER_REV from the scaled value of the position. (((int32_t)dev_data->position * AS5600_FULL_ANGLE) % AS5600_PULSES_PER_REV) Then convert the value to one-millionth part. * (AS5600_MILLION_UNIT / AS5600_PULSES_PER_REV); Signed-off-by: Yasushi SHOJI --- drivers/sensor/ams_as5600/ams_as5600.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/sensor/ams_as5600/ams_as5600.c b/drivers/sensor/ams_as5600/ams_as5600.c index c5775e74701..68c9e2e90a7 100644 --- a/drivers/sensor/ams_as5600/ams_as5600.c +++ b/drivers/sensor/ams_as5600/ams_as5600.c @@ -19,6 +19,7 @@ LOG_MODULE_REGISTER(ams_as5600, CONFIG_SENSOR_LOG_LEVEL); #define AS5600_ANGLE_REGISTER_H 0x0E #define AS5600_FULL_ANGLE 360 #define AS5600_PULSES_PER_REV 4096 +#define AS5600_MILLION_UNIT 1000000 struct as5600_dev_cfg { struct i2c_dt_spec i2c_port; @@ -60,8 +61,8 @@ static int as5600_get(const struct device *dev, enum sensor_channel chan, val->val1 = ((int32_t)dev_data->position * AS5600_FULL_ANGLE) / AS5600_PULSES_PER_REV; - val->val2 = ((int32_t)dev_data->position * AS5600_FULL_ANGLE) - - (val->val1 * AS5600_PULSES_PER_REV); + val->val2 = (((int32_t)dev_data->position * AS5600_FULL_ANGLE) % + AS5600_PULSES_PER_REV) * (AS5600_MILLION_UNIT / AS5600_PULSES_PER_REV); } else { return -ENOTSUP; } From be60134421f7a02f90f377b78cc9744a6d1972e7 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Fri, 9 Feb 2024 20:32:37 -0500 Subject: [PATCH 0534/2402] west: add native_sim flash, debugserver command Add 'west flash' support which in the case of native_sim just start the built application. Reuse existing runner and rename it to be more generic as it does more than just debugging now. Also add debugserver command. Fixes #36706 Signed-off-by: Anas Nashif --- boards/native/native_posix/board.cmake | 5 +- boards/native/native_sim/board.cmake | 5 +- boards/native/nrf_bsim/board.cmake | 5 +- scripts/west_commands/runners/__init__.py | 2 +- scripts/west_commands/runners/native.py | 81 +++++++++++++++++++++ scripts/west_commands/runners/native_gdb.py | 46 ------------ scripts/west_commands/tests/test_imports.py | 2 +- 7 files changed, 92 insertions(+), 54 deletions(-) create mode 100644 scripts/west_commands/runners/native.py delete mode 100644 scripts/west_commands/runners/native_gdb.py diff --git a/boards/native/native_posix/board.cmake b/boards/native/native_posix/board.cmake index f8c2fd58f87..c3f7c89918d 100644 --- a/boards/native/native_posix/board.cmake +++ b/boards/native/native_posix/board.cmake @@ -3,5 +3,6 @@ set(SUPPORTED_EMU_PLATFORMS native) -board_set_debugger_ifnset(native_gdb) -board_finalize_runner_args(native_gdb) +board_set_debugger_ifnset(native) +board_set_flasher_ifnset(native) +board_finalize_runner_args(native) diff --git a/boards/native/native_sim/board.cmake b/boards/native/native_sim/board.cmake index d9d444c1be9..ca2d2ab8ec5 100644 --- a/boards/native/native_sim/board.cmake +++ b/boards/native/native_sim/board.cmake @@ -2,5 +2,6 @@ set(SUPPORTED_EMU_PLATFORMS native) -board_set_debugger_ifnset(native_gdb) -board_finalize_runner_args(native_gdb) +board_set_debugger_ifnset(native) +board_set_flasher_ifnset(native) +board_finalize_runner_args(native) diff --git a/boards/native/nrf_bsim/board.cmake b/boards/native/nrf_bsim/board.cmake index 70a6c0f0f4d..e94cde5152b 100644 --- a/boards/native/nrf_bsim/board.cmake +++ b/boards/native/nrf_bsim/board.cmake @@ -3,5 +3,6 @@ set(SUPPORTED_EMU_PLATFORMS native) -board_set_debugger_ifnset(native_gdb) -board_finalize_runner_args(native_gdb) +board_set_debugger_ifnset(native) +board_set_flasher_ifnset(native) +board_finalize_runner_args(native) diff --git a/scripts/west_commands/runners/__init__.py b/scripts/west_commands/runners/__init__.py index 850efcd5668..7e88d56edc4 100644 --- a/scripts/west_commands/runners/__init__.py +++ b/scripts/west_commands/runners/__init__.py @@ -40,7 +40,7 @@ def _import_runner_module(runner_name): 'linkserver', 'mdb', 'misc', - 'native_gdb', + 'native', 'nios2', 'nrfjprog', 'nrfutil', diff --git a/scripts/west_commands/runners/native.py b/scripts/west_commands/runners/native.py new file mode 100644 index 00000000000..2cbcf60d3ab --- /dev/null +++ b/scripts/west_commands/runners/native.py @@ -0,0 +1,81 @@ +# Copyright (c) 2023 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +"""This file provides a ZephyrBinaryRunner that launches GDB and enables +flashing (running) a native application.""" + +import argparse +from runners.core import ZephyrBinaryRunner, RunnerCaps, RunnerConfig + +DEFAULT_GDB_PORT = 3333 + +class NativeSimBinaryRunner(ZephyrBinaryRunner): + """Runs the ELF binary under GDB.""" + + def __init__(self, cfg, + tui=False, + gdb_port=DEFAULT_GDB_PORT): + super().__init__(cfg) + self.gdb_port = gdb_port + + if cfg.gdb is None: + self.gdb_cmd = None + else: + self.gdb_cmd = [cfg.gdb] + (['-tui'] if tui else []) + + if self.cfg.gdb is None: + raise ValueError("The provided RunnerConfig is missing the required field 'gdb'.") + + if self.cfg.exe_file is None: + raise ValueError("The provided RunnerConfig is missing the required field 'exe_file'.") + + + @classmethod + def name(cls): + return 'native' + + @classmethod + def capabilities(cls): + return RunnerCaps(commands={'debug', 'debugserver', 'flash'}) + + @classmethod + def do_add_parser(cls, parser: argparse.ArgumentParser): + parser.add_argument('--tui', default=False, action='store_true', + help='if given, GDB uses -tui') + parser.add_argument('--gdb-port', default=DEFAULT_GDB_PORT, + help='gdb port, defaults to {}'.format( + DEFAULT_GDB_PORT)) + + @classmethod + def do_create(cls, cfg: RunnerConfig, args: argparse.Namespace) -> ZephyrBinaryRunner: + return NativeSimBinaryRunner(cfg, + tui=args.tui, + gdb_port=args.gdb_port) + + def do_run(self, command: str, **kwargs): + if command == 'flash': + self.do_flash(**kwargs) + elif command == 'debug': + self.do_debug(**kwargs) + elif command == 'debugserver': + self.do_debugserver(**kwargs) + else: + assert False + + def do_flash(self, **kwargs): + cmd = [self.cfg.exe_file] + self.check_call(cmd) + + def do_debug(self, **kwargs): + # Clues to debug missing RunnerConfig values (in context of `west debug`): + # build/zephyr/runners.yaml is missing `gdb` or `elf_file`. + # board.cmake should have `board_finalize_runner_args(native)`. + # build/CMakeCache.txt should have `CMAKE_GDB`. + + cmd = (self.gdb_cmd + ['--quiet', self.cfg.exe_file]) + self.check_call(cmd) + + def do_debugserver(self, **kwargs): + cmd = (['gdbserver', ':{}'.format(self.gdb_port), self.cfg.exe_file]) + + self.check_call(cmd) diff --git a/scripts/west_commands/runners/native_gdb.py b/scripts/west_commands/runners/native_gdb.py deleted file mode 100644 index 163fe01793b..00000000000 --- a/scripts/west_commands/runners/native_gdb.py +++ /dev/null @@ -1,46 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -"""This file provides a ZephyrBinaryRunner that launches GDB.""" - -import argparse -from runners.core import ZephyrBinaryRunner, RunnerCaps, RunnerConfig - -class NativeGDBBinaryRunner(ZephyrBinaryRunner): - """Runs the ELF binary under GDB.""" - - @classmethod - def name(cls): - return 'native_gdb' - - @classmethod - def capabilities(cls): - return RunnerCaps(commands={'debug'}) - - @classmethod - def do_add_parser(cls, parser: argparse.ArgumentParser): - pass - - @classmethod - def do_create(cls, cfg: RunnerConfig, args: argparse.Namespace) -> ZephyrBinaryRunner: - return NativeGDBBinaryRunner(cfg) - - def do_run(self, command: str, **kwargs): - assert command == 'debug' - - # Clues to debug missing RunnerConfig values (in context of `west debug`): - # build/zephyr/runners.yaml is missing `gdb` or `elf_file`. - # board.cmake should have `board_finalize_runner_args(native_gdb)`. - # build/CMakeCache.txt should have `CMAKE_GDB`. - - if self.cfg.gdb is None: - raise ValueError("The provided RunnerConfig is missing the required field 'gdb'.") - - if self.cfg.exe_file is None: - raise ValueError("The provided RunnerConfig is missing the required field 'exe_file'.") - - self.call([ - self.cfg.gdb, - '--quiet', - self.cfg.exe_file, - ]) diff --git a/scripts/west_commands/tests/test_imports.py b/scripts/west_commands/tests/test_imports.py index 274840f8cbf..89ca44c980b 100644 --- a/scripts/west_commands/tests/test_imports.py +++ b/scripts/west_commands/tests/test_imports.py @@ -31,7 +31,7 @@ def test_runner_imports(): 'mdb-nsim', 'mdb-hw', 'misc-flasher', - 'native_gdb', + 'native', 'nios2', 'nrfjprog', 'nrfutil', From 65d99da6322cda5311185aab0577d9604347aaf3 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Thu, 7 Mar 2024 08:43:26 +0000 Subject: [PATCH 0535/2402] boards: snps: nsim: Fix board usage for filenames Fixes an issue where the board name variable has changed in hwmv2 Signed-off-by: Jamie McCrae --- boards/synopsys/nsim/board.cmake | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/boards/synopsys/nsim/board.cmake b/boards/synopsys/nsim/board.cmake index 06af2286078..84ad168bd95 100644 --- a/boards/synopsys/nsim/board.cmake +++ b/boards/synopsys/nsim/board.cmake @@ -1,15 +1,18 @@ # SPDX-License-Identifier: Apache-2.0 set(SUPPORTED_EMU_PLATFORMS nsim) +string(SUBSTRING "${BOARD_IDENTIFIER}" 1 -1 NSIM_BASE_FILENAME) +string(REPLACE "/" "_" NSIM_BASE_FILENAME "${NSIM_BASE_FILENAME}") + if(NOT (CONFIG_SOC_NSIM_HS_SMP OR CONFIG_SOC_NSIM_HS6X_SMP OR CONFIG_SOC_NSIM_HS5X_SMP)) board_set_flasher_ifnset(arc-nsim) board_set_debugger_ifnset(arc-nsim) - set(NSIM_PROPS "${BOARD}.props") + set(NSIM_PROPS "${NSIM_BASE_FILENAME}.props") board_runner_args(arc-nsim "--props=${NSIM_PROPS}") endif() -string(REPLACE "nsim" "mdb" MDB_ARGS "${BOARD}.args") +string(REPLACE "nsim" "mdb" MDB_ARGS "${NSIM_BASE_FILENAME}.args") board_runner_args(mdb-nsim "--cores=${CONFIG_MP_MAX_NUM_CPUS}" "--nsim_args=${MDB_ARGS}") board_runner_args(mdb-hw "--cores=${CONFIG_MP_MAX_NUM_CPUS}") From 8ea1ca73556149c7ca864e6d0c489c0f84115336 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Mon, 11 Mar 2024 14:24:34 +0000 Subject: [PATCH 0536/2402] boards: snps: nsim: Fix filenames Fixes filenames of support files to match expected names Signed-off-by: Jamie McCrae --- .../nsim/support/{mdb_hs3x_hostlink.args => mdb_hs_hostlink.args} | 0 ...nsim_sem_mpu_stack_guard.args => mdb_sem_mpu_stack_guard.args} | 0 .../support/{nsim_hs3x_hostlink.props => nsim_hs_hostlink.props} | 0 3 files changed, 0 insertions(+), 0 deletions(-) rename boards/synopsys/nsim/support/{mdb_hs3x_hostlink.args => mdb_hs_hostlink.args} (100%) rename boards/synopsys/nsim/support/{nsim_sem_mpu_stack_guard.args => mdb_sem_mpu_stack_guard.args} (100%) rename boards/synopsys/nsim/support/{nsim_hs3x_hostlink.props => nsim_hs_hostlink.props} (100%) diff --git a/boards/synopsys/nsim/support/mdb_hs3x_hostlink.args b/boards/synopsys/nsim/support/mdb_hs_hostlink.args similarity index 100% rename from boards/synopsys/nsim/support/mdb_hs3x_hostlink.args rename to boards/synopsys/nsim/support/mdb_hs_hostlink.args diff --git a/boards/synopsys/nsim/support/nsim_sem_mpu_stack_guard.args b/boards/synopsys/nsim/support/mdb_sem_mpu_stack_guard.args similarity index 100% rename from boards/synopsys/nsim/support/nsim_sem_mpu_stack_guard.args rename to boards/synopsys/nsim/support/mdb_sem_mpu_stack_guard.args diff --git a/boards/synopsys/nsim/support/nsim_hs3x_hostlink.props b/boards/synopsys/nsim/support/nsim_hs_hostlink.props similarity index 100% rename from boards/synopsys/nsim/support/nsim_hs3x_hostlink.props rename to boards/synopsys/nsim/support/nsim_hs_hostlink.props From 8336d8b1e16fb957ce9545e4317b799381aad85d Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Tue, 26 Dec 2023 08:48:48 +0900 Subject: [PATCH 0537/2402] kernel: api: sys_slist find zephyrproject-rtos#65973 add a function to find a node in a slist. signed-off-by: Gaetan Perrot --- include/zephyr/sys/list_gen.h | 25 +++++++++++++++++++++++++ include/zephyr/sys/slist.h | 15 +++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/include/zephyr/sys/list_gen.h b/include/zephyr/sys/list_gen.h index f1aa1b3a510..ba29f7d9bec 100644 --- a/include/zephyr/sys/list_gen.h +++ b/include/zephyr/sys/list_gen.h @@ -234,6 +234,31 @@ return false; \ } +#define Z_GENLIST_FIND(__lname, __nname) \ + static inline bool sys_##__lname##_find( \ + sys_##__lname##_t *list, sys_##__nname##_t *node, sys_##__nname##_t **prev) \ + { \ + sys_##__nname##_t *current = NULL; \ + sys_##__nname##_t *previous = NULL; \ + \ + Z_GENLIST_FOR_EACH_NODE(__lname, list, current) { \ + if (current == node) { \ + if (prev != NULL) { \ + *prev = previous; \ + } \ + return true; \ + } \ + \ + previous = current; \ + } \ + \ + if (prev != NULL) { \ + *prev = previous; \ + } \ + \ + return false; \ + } + #define Z_GENLIST_LEN(__lname, __nname) \ static inline size_t sys_##__lname##_len(sys_##__lname##_t * list) \ { \ diff --git a/include/zephyr/sys/slist.h b/include/zephyr/sys/slist.h index 095c89ffe02..90d93dd0b56 100644 --- a/include/zephyr/sys/slist.h +++ b/include/zephyr/sys/slist.h @@ -420,6 +420,21 @@ Z_GENLIST_REMOVE(slist, snode) static inline bool sys_slist_find_and_remove(sys_slist_t *list, sys_snode_t *node); +/** + * @brief Find if a node is already linked in a singly linked list + * + * This and other sys_slist_*() functions are not thread safe. + * + * @param list A pointer to the list to check + * @param node A pointer to the node to search in the list + * @param[out] prev A pointer to the previous node + * + * @return true if node was found in the list, false otherwise + */ +static inline bool sys_slist_find(sys_slist_t *list, sys_snode_t *node, + sys_snode_t **prev); +Z_GENLIST_FIND(slist, snode) + /** * @brief Compute the size of the given list in O(n) time * From d9e9f75bfc4c8949e824fdd7019eda6185ea13bf Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Mon, 8 Jan 2024 12:41:01 +0900 Subject: [PATCH 0538/2402] kernel: api: implement test for sys_slist_find implement test for sys_slist_find signed-off-by: Gaetan Perrot --- tests/unit/list/slist.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/tests/unit/list/slist.c b/tests/unit/list/slist.c index 49c4b8257b2..53e3ebc70a8 100644 --- a/tests/unit/list/slist.c +++ b/tests/unit/list/slist.c @@ -184,7 +184,7 @@ static inline bool verify_tail_head(sys_slist_t *list, * @see sys_slist_init(), sys_slist_append(), * sys_slist_find_and_remove(), sys_slist_prepend(), * sys_slist_remove(), sys_slist_get(), sys_slist_get_not_empty(), - * sys_slist_append_list(), sys_slist_merge_list() + * sys_slist_append_list(), sys_slist_merge_list(), sys_slist_find() */ ZTEST(dlist_api, test_slist) { @@ -202,6 +202,13 @@ ZTEST(dlist_api, test_slist) &test_node_1.node, true)), "test_list head/tail are wrong"); + /* Find the node 1, previous node should be null */ + sys_snode_t *test_node_1_prev = &test_node_1.node; + + zassert_true(sys_slist_find(&test_list, &test_node_1.node, &test_node_1_prev), + "test_list did not find node "); + zassert_is_null(test_node_1_prev, "test_list previous node not null "); + /* Finding and removing node 1 */ sys_slist_find_and_remove(&test_list, &test_node_1.node); zassert_true((verify_emptyness(&test_list)), @@ -258,6 +265,14 @@ ZTEST(dlist_api, test_slist) &test_node_4.node), "test_list node links are wrong"); + /* Find the node 4 and get the previous node*/ + sys_snode_t *test_node_4_prev = NULL; + + zassert_true(sys_slist_find(&test_list, &test_node_4.node, &test_node_4_prev), + "test_list did not find node"); + zassert_equal(&test_node_2.node, test_node_4_prev, + "test_list previous node wrong "); + /* Finding and removing node 1 */ sys_slist_find_and_remove(&test_list, &test_node_1.node); zassert_true((verify_content_amount(&test_list, 3)), From fa6a7c1b77c6dd1c4c3537a3d46043d85fa624d6 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Thu, 21 Dec 2023 13:23:00 +0100 Subject: [PATCH 0539/2402] Bluetooth: CAP: Commander change microphone gain procedure Adds the CAP Commander Change Microphone Gain procedure. This procedure changes the microphone gain on one or more CAP Acceptors. Signed-off-by: Emil Gydesen --- include/zephyr/bluetooth/audio/cap.h | 33 +++- subsys/bluetooth/audio/cap_commander.c | 233 ++++++++++++++++++++++++- subsys/bluetooth/audio/cap_common.c | 2 + subsys/bluetooth/audio/cap_internal.h | 12 +- 4 files changed, 268 insertions(+), 12 deletions(-) diff --git a/include/zephyr/bluetooth/audio/cap.h b/include/zephyr/bluetooth/audio/cap.h index eac5f4618ca..61f1a875e42 100644 --- a/include/zephyr/bluetooth/audio/cap.h +++ b/include/zephyr/bluetooth/audio/cap.h @@ -713,14 +713,29 @@ struct bt_cap_commander_cb { * * @param conn Pointer to the connection where the error * occurred. NULL if @p err is 0 or if cancelled by - * bt_cap_initiator_unicast_audio_cancel() + * bt_cap_commander_cancel() * @param err 0 on success, BT_GATT_ERR() with a * specific ATT (BT_ATT_ERR_*) error code or -ECANCELED if cancelled - * by bt_cap_initiator_unicast_audio_cancel(). + * by bt_cap_commander_cancel(). */ void (*volume_offset_changed)(struct bt_conn *conn, int err); #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ +#if defined(CONFIG_BT_MICP_MIC_CTLR) +#if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) + /** + * @brief Callback for bt_cap_commander_change_microphone_gain_setting(). + * + * @param conn Pointer to the connection where the error + * occurred. NULL if @p err is 0 or if cancelled by + * bt_cap_commander_cancel() + * @param err 0 on success, BT_GATT_ERR() with a + * specific ATT (BT_ATT_ERR_*) error code or -ECANCELED if cancelled + * by bt_cap_commander_cancel(). + */ + void (*microphone_gain_changed)(struct bt_conn *conn, int err); +#endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ +#endif /* CONFIG_BT_MICP_MIC_CTLR */ }; /** @@ -772,13 +787,13 @@ int bt_cap_commander_discover(struct bt_conn *conn); * It is recommended to do this if any existing procedure takes longer time than expected, which * could indicate a missing response from the Common Audio Profile Acceptor. * - * This does not send any requests to any Common Audio Profile Acceptors involved with the current - * procedure, and thus notifications from the Common Audio Profile Acceptors may arrive after this - * has been called. It is thus recommended to either only use this if a procedure has stalled, or - * wait a short while before starting any new Common Audio Profile procedure after this has been - * called to avoid getting notifications from the cancelled procedure. The wait time depends on - * the connection interval, the number of devices in the previous procedure and the behavior of the - * Common Audio Profile Acceptors. + * This does not send any requests to any Common Audio Profile Acceptors involved with the + * current procedure, and thus notifications from the Common Audio Profile Acceptors may + * arrive after this has been called. It is thus recommended to either only use this if a + * procedure has stalled, or wait a short while before starting any new Common Audio Profile + * procedure after this has been called to avoid getting notifications from the cancelled + * procedure. The wait time depends on the connection interval, the number of devices in the + * previous procedure and the behavior of the Common Audio Profile Acceptors. * * The respective callbacks of the procedure will be called as part of this with the connection * pointer set to NULL and the err value set to -ECANCELED. diff --git a/subsys/bluetooth/audio/cap_commander.c b/subsys/bluetooth/audio/cap_commander.c index b52e1528f7d..95e4affc848 100644 --- a/subsys/bluetooth/audio/cap_commander.c +++ b/subsys/bluetooth/audio/cap_commander.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include "cap_internal.h" @@ -123,6 +124,15 @@ static void cap_commander_unicast_audio_proc_complete(void) break; #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ +#if defined(CONFIG_BT_MICP_MIC_CTLR) +#if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) + case BT_CAP_COMMON_PROC_TYPE_MICROPHONE_GAIN_CHANGE: + if (cap_cb->microphone_gain_changed != NULL) { + cap_cb->microphone_gain_changed(failed_conn, err); + } + break; +#endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ +#endif /* CONFIG_BT_MICP_MIC_CTLR */ case BT_CAP_COMMON_PROC_TYPE_NONE: default: __ASSERT(false, "Invalid proc_type: %u", proc_type); @@ -724,15 +734,236 @@ int bt_cap_commander_change_volume_offset( #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ +#if defined(CONFIG_BT_MICP_MIC_CTLR) +static struct bt_micp_mic_ctlr_cb mic_ctlr_cb; +static bool micp_callbacks_registered; + +static int cap_commander_register_micp_callbacks(void) +{ + int err; + + err = bt_micp_mic_ctlr_cb_register(&mic_ctlr_cb); + if (err != 0) { + LOG_DBG("Failed to register MICP callbacks: %d", err); + + return -ENOEXEC; + } + + micp_callbacks_registered = true; + + return 0; +} + int bt_cap_commander_change_microphone_mute_state( const struct bt_cap_commander_change_microphone_mute_state_param *param) { + if (!micp_callbacks_registered && cap_commander_register_micp_callbacks() != 0) { + LOG_DBG("Failed to register MICP callbacks"); + + return -ENOEXEC; + } + return -ENOSYS; } +#if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) +static bool valid_change_microphone_gain_param( + const struct bt_cap_commander_change_microphone_gain_setting_param *param) +{ + CHECKIF(param == NULL) { + LOG_DBG("param is NULL"); + return false; + } + + CHECKIF(param->count == 0) { + LOG_DBG("Invalid param->count: %u", param->count); + return false; + } + + CHECKIF(param->param == NULL) { + LOG_DBG("param->param is NULL"); + return false; + } + + CHECKIF(param->count > CONFIG_BT_MAX_CONN) { + LOG_DBG("param->count (%zu) is larger than CONFIG_BT_MAX_CONN (%d)", param->count, + CONFIG_BT_MAX_CONN); + return false; + } + + for (size_t i = 0U; i < param->count; i++) { + const union bt_cap_set_member *member = ¶m->param[i].member; + const struct bt_cap_common_client *client = + bt_cap_common_get_client(param->type, member); + struct bt_micp_mic_ctlr *mic_ctlr; + struct bt_micp_included included; + int err; + + if (client == NULL) { + LOG_DBG("Invalid param->param[%zu].member", i); + return false; + } + + mic_ctlr = bt_micp_mic_ctlr_get_by_conn(client->conn); + if (mic_ctlr == NULL) { + LOG_DBG("Microphone control not available for param->param[%zu].member", i); + return false; + } + + err = bt_micp_mic_ctlr_included_get(mic_ctlr, &included); + if (err != 0 || included.aics_cnt == 0) { + LOG_DBG("Microphone audio input control not available for " + "param->param[%zu].member", + i); + return -ENOEXEC; + } + + for (size_t j = 0U; j < i; j++) { + const union bt_cap_set_member *other = ¶m->param[j].member; + + if (other == member) { + LOG_DBG("param->param[%zu].member (%p) is duplicated by " + "param->param[%zu].member (%p)", + j, other, i, member); + return false; + } + } + } + + return true; +} + +static void cap_commander_micp_gain_set_cb(struct bt_aics *inst, int err) +{ + struct bt_cap_common_proc *active_proc = bt_cap_common_get_active_proc(); + struct bt_conn *conn; + int micp_err; + + LOG_DBG("bt_aics %p", (void *)inst); + + micp_err = bt_aics_client_conn_get(inst, &conn); + if (micp_err != 0) { + LOG_ERR("Failed to get conn by aics: %d", micp_err); + return; + } + + LOG_DBG("conn %p", (void *)conn); + if (!bt_cap_common_conn_in_active_proc(conn)) { + /* State change happened outside of a procedure; ignore */ + return; + } + + if (err != 0) { + LOG_DBG("Failed to set gain: %d", err); + bt_cap_common_abort_proc(conn, err); + } else { + active_proc->proc_done_cnt++; + + LOG_DBG("Conn %p gain updated (%zu/%zu streams done)", (void *)conn, + active_proc->proc_done_cnt, active_proc->proc_cnt); + } + + if (bt_cap_common_proc_is_aborted()) { + LOG_DBG("Proc is aborted"); + if (bt_cap_common_proc_all_handled()) { + LOG_DBG("All handled"); + cap_commander_unicast_audio_proc_complete(); + } + + return; + } + + if (!bt_cap_common_proc_is_done()) { + const struct bt_cap_commander_proc_param *proc_param; + + proc_param = &active_proc->proc_param.commander[active_proc->proc_done_cnt]; + conn = proc_param->conn; + active_proc->proc_initiated_cnt++; + err = bt_aics_gain_set(proc_param->change_gain.aics, proc_param->change_gain.gain); + if (err != 0) { + LOG_DBG("Failed to set gain for conn %p: %d", (void *)conn, err); + bt_cap_common_abort_proc(conn, err); + cap_commander_unicast_audio_proc_complete(); + } + } else { + cap_commander_unicast_audio_proc_complete(); + } +} + int bt_cap_commander_change_microphone_gain_setting( const struct bt_cap_commander_change_microphone_gain_setting_param *param) { + const struct bt_cap_commander_proc_param *proc_param; + struct bt_cap_common_proc *active_proc; + struct bt_conn *conn; + int err; - return -ENOSYS; + if (bt_cap_common_proc_is_active()) { + LOG_DBG("A CAP procedure is already in progress"); + + return -EBUSY; + } + + if (!valid_change_microphone_gain_param(param)) { + return -EINVAL; + } + + bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_MICROPHONE_GAIN_CHANGE, param->count); + + mic_ctlr_cb.aics_cb.set_gain = cap_commander_micp_gain_set_cb; + if (!micp_callbacks_registered && cap_commander_register_micp_callbacks() != 0) { + LOG_DBG("Failed to register MICP callbacks"); + + return -ENOEXEC; + } + + active_proc = bt_cap_common_get_active_proc(); + + for (size_t i = 0U; i < param->count; i++) { + const union bt_cap_set_member *member = ¶m->param[i].member; + struct bt_conn *member_conn = bt_cap_common_get_member_conn(param->type, member); + struct bt_micp_mic_ctlr *mic_ctlr; + struct bt_micp_included included; + + if (member_conn == NULL) { + LOG_DBG("Invalid param->param[%zu].member", i); + return -EINVAL; + } + + mic_ctlr = bt_micp_mic_ctlr_get_by_conn(member_conn); + if (mic_ctlr == NULL) { + LOG_DBG("Invalid param->param[%zu].member mic_ctlr", i); + return -EINVAL; + } + + err = bt_micp_mic_ctlr_included_get(mic_ctlr, &included); + if (err != 0 || included.aics_cnt == 0) { + LOG_DBG("Invalid param->param[%zu].member aics", i); + return -EINVAL; + } + + /* Store the necessary parameters as we cannot assume that the supplied parameters + * are kept valid + */ + active_proc->proc_param.commander[i].conn = member_conn; + active_proc->proc_param.commander[i].change_gain.gain = param->param[i].gain; + /* TODO: For now we just use the first AICS instance + * - How should we handle multiple? + */ + active_proc->proc_param.commander[i].change_gain.aics = included.aics[0]; + } + + proc_param = &active_proc->proc_param.commander[0]; + conn = proc_param->conn; + active_proc->proc_initiated_cnt++; + + err = bt_aics_gain_set(proc_param->change_gain.aics, proc_param->change_gain.gain); + if (err != 0) { + LOG_DBG("Failed to set gain for conn %p: %d", (void *)conn, err); + return -ENOEXEC; + } + + return 0; } +#endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ +#endif /* CONFIG_BT_MICP_MIC_CTLR */ diff --git a/subsys/bluetooth/audio/cap_common.c b/subsys/bluetooth/audio/cap_common.c index 0264e82c9bc..277b904355b 100644 --- a/subsys/bluetooth/audio/cap_common.c +++ b/subsys/bluetooth/audio/cap_common.c @@ -123,6 +123,8 @@ static bool active_proc_is_commander(void) case BT_CAP_COMMON_PROC_TYPE_VOLUME_CHANGE: case BT_CAP_COMMON_PROC_TYPE_VOLUME_OFFSET_CHANGE: case BT_CAP_COMMON_PROC_TYPE_VOLUME_MUTE_CHANGE: + case BT_CAP_COMMON_PROC_TYPE_MICROPHONE_GAIN_CHANGE: + case BT_CAP_COMMON_PROC_TYPE_MICROPHONE_MUTE_CHANGE: return true; default: return false; diff --git a/subsys/bluetooth/audio/cap_internal.h b/subsys/bluetooth/audio/cap_internal.h index d3c4276c6e0..4fba04f6568 100644 --- a/subsys/bluetooth/audio/cap_internal.h +++ b/subsys/bluetooth/audio/cap_internal.h @@ -39,6 +39,8 @@ enum bt_cap_common_proc_type { BT_CAP_COMMON_PROC_TYPE_VOLUME_CHANGE, BT_CAP_COMMON_PROC_TYPE_VOLUME_OFFSET_CHANGE, BT_CAP_COMMON_PROC_TYPE_VOLUME_MUTE_CHANGE, + BT_CAP_COMMON_PROC_TYPE_MICROPHONE_GAIN_CHANGE, + BT_CAP_COMMON_PROC_TYPE_MICROPHONE_MUTE_CHANGE, }; enum bt_cap_common_subproc_type { @@ -85,8 +87,14 @@ struct bt_cap_commander_proc_param { struct bt_vocs *vocs; } change_offset; #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ - - /* TODO Add other procedures */ +#if defined(CONFIG_BT_MICP_MIC_CTLR) +#if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) + struct { + int8_t gain; + struct bt_aics *aics; + } change_gain; +#endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ +#endif /* CONFIG_BT_MICP_MIC_CTLR */ }; }; From 89566422652de8725c261f0bfd5fa87fd2a77f02 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Thu, 21 Dec 2023 13:23:54 +0100 Subject: [PATCH 0540/2402] tests: bsim: Bluetooth: CAP Commander Change Microphone Gain Adds bsim test of the CAP Commander Change Microphone Gain procedure. Signed-off-by: Emil Gydesen --- .../bluetooth/audio/src/cap_acceptor_test.c | 30 ++++- .../bluetooth/audio/src/cap_commander_test.c | 112 +++++++++++++++++- 2 files changed, 139 insertions(+), 3 deletions(-) diff --git a/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c b/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c index 6c110522809..da6899d0c3f 100644 --- a/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c +++ b/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include "common.h" @@ -672,7 +673,7 @@ static void init(void) for (size_t i = 0U; i < ARRAY_SIZE(vcp_param.aics_param); i++) { vcp_param.aics_param[i].desc_writable = true; - snprintf(input_desc[i], sizeof(input_desc[i]), "Input %d", i + 1); + snprintf(input_desc[i], sizeof(input_desc[i]), "VCP Input %d", i + 1); vcp_param.aics_param[i].description = input_desc[i]; vcp_param.aics_param[i].type = BT_AICS_INPUT_TYPE_DIGITAL; vcp_param.aics_param[i].status = true; @@ -694,6 +695,33 @@ static void init(void) return; } } + + if (IS_ENABLED(CONFIG_BT_MICP_MIC_DEV)) { + struct bt_micp_mic_dev_register_param micp_param = {0}; + +#if defined(CONFIG_BT_MICP_MIC_DEV_AICS) + char input_desc[CONFIG_BT_MICP_MIC_DEV_AICS_INSTANCE_COUNT][16]; + + for (int i = 0; i < ARRAY_SIZE(micp_param.aics_param); i++) { + micp_param.aics_param[i].desc_writable = true; + snprintf(input_desc[i], sizeof(input_desc[i]), "MICP Input %d", i + 1); + micp_param.aics_param[i].description = input_desc[i]; + micp_param.aics_param[i].type = BT_AICS_INPUT_TYPE_DIGITAL; + micp_param.aics_param[i].status = true; + micp_param.aics_param[i].gain_mode = BT_AICS_MODE_MANUAL; + micp_param.aics_param[i].units = 1; + micp_param.aics_param[i].min_gain = 0; + micp_param.aics_param[i].max_gain = 100; + micp_param.aics_param[i].cb = NULL; + } +#endif /* CONFIG_BT_MICP_MIC_DEV_AICS */ + + err = bt_micp_mic_dev_register(&micp_param); + if (err != 0) { + FAIL("Failed to register MICS (err %d)\n", err); + return; + } + } } static void test_cap_acceptor_unicast(void) diff --git a/tests/bsim/bluetooth/audio/src/cap_commander_test.c b/tests/bsim/bluetooth/audio/src/cap_commander_test.c index f05b7ab8807..d25d94ce42e 100644 --- a/tests/bsim/bluetooth/audio/src/cap_commander_test.c +++ b/tests/bsim/bluetooth/audio/src/cap_commander_test.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include "common.h" @@ -22,10 +23,12 @@ static volatile size_t connected_conn_cnt; CREATE_FLAG(flag_cas_discovered); CREATE_FLAG(flag_vcs_discovered); +CREATE_FLAG(flag_mics_discovered); CREATE_FLAG(flag_mtu_exchanged); CREATE_FLAG(flag_volume_changed); CREATE_FLAG(flag_volume_mute_changed); CREATE_FLAG(flag_volume_offset_changed); +CREATE_FLAG(flag_microphone_gain_changed); static void cap_discovery_complete_cb(struct bt_conn *conn, int err, const struct bt_csip_set_coordinator_csis_inst *csis_inst) @@ -51,6 +54,7 @@ static void cap_discovery_complete_cb(struct bt_conn *conn, int err, SET_FLAG(flag_cas_discovered); } +#if defined(CONFIG_BT_VCP_VOL_CTLR) static void cap_volume_changed_cb(struct bt_conn *conn, int err) { if (err != 0) { @@ -71,6 +75,7 @@ static void cap_volume_mute_changed_cb(struct bt_conn *conn, int err) SET_FLAG(flag_volume_mute_changed); } +#if defined(CONFIG_BT_VCP_VOL_CTLR_VOCS) static void cap_volume_offset_changed_cb(struct bt_conn *conn, int err) { if (err != 0) { @@ -80,12 +85,37 @@ static void cap_volume_offset_changed_cb(struct bt_conn *conn, int err) SET_FLAG(flag_volume_offset_changed); } +#endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ +#endif /* CONFIG_BT_VCP_VOL_CTLR */ + +#if defined(CONFIG_BT_MICP_MIC_CTLR) +#if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) +static void cap_microphone_gain_changed_cb(struct bt_conn *conn, int err) +{ + if (err != 0) { + FAIL("Failed to change volume for conn %p: %d\n", conn, err); + return; + } + + SET_FLAG(flag_microphone_gain_changed); +} +#endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ +#endif /* CONFIG_BT_MICP_MIC_CTLR */ static struct bt_cap_commander_cb cap_cb = { .discovery_complete = cap_discovery_complete_cb, +#if defined(CONFIG_BT_VCP_VOL_CTLR) .volume_changed = cap_volume_changed_cb, .volume_mute_changed = cap_volume_mute_changed_cb, +#if defined(CONFIG_BT_VCP_VOL_CTLR_VOCS) .volume_offset_changed = cap_volume_offset_changed_cb, +#endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ +#endif /* CONFIG_BT_VCP_VOL_CTLR */ +#if defined(CONFIG_BT_MICP_MIC_CTLR) +#if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) + .microphone_gain_changed = cap_microphone_gain_changed_cb, +#endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ +#endif /* CONFIG_BT_MICP_MIC_CTLR */ }; static void cap_vcp_discover_cb(struct bt_vcp_vol_ctlr *vol_ctlr, int err, uint8_t vocs_count, @@ -117,6 +147,22 @@ static struct bt_vcp_vol_ctlr_cb vcp_cb = { .state = cap_vcp_state_cb, }; +static void cap_micp_discover_cb(struct bt_micp_mic_ctlr *mic_ctlr, int err, uint8_t aics_count) +{ + if (err != 0) { + FAIL("Failed to discover MICS: %d\n", err); + + return; + } + + printk("MICS for %p found with %u AICS\n", mic_ctlr, aics_count); + SET_FLAG(flag_mics_discovered); +} + +static struct bt_micp_mic_ctlr_cb micp_cb = { + .discover = cap_micp_discover_cb, +}; + static void att_mtu_updated(struct bt_conn *conn, uint16_t tx, uint16_t rx) { printk("MTU exchanged\n"); @@ -150,6 +196,12 @@ static void init(void) FAIL("Failed to register VCP callbacks (err %d)\n", err); return; } + + err = bt_micp_mic_ctlr_cb_register(&micp_cb); + if (err != 0) { + FAIL("Failed to register MICP callbacks (err %d)\n", err); + return; + } } static void cap_device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t type, @@ -247,13 +299,29 @@ static void discover_vcs(struct bt_conn *conn) err = bt_vcp_vol_ctlr_discover(conn, &vol_ctlr); if (err != 0) { - printk("Failed to discover VCS: %d\n", err); + FAIL("Failed to discover VCS: %d\n", err); return; } WAIT_FOR_FLAG(flag_vcs_discovered); } +static void discover_mics(struct bt_conn *conn) +{ + struct bt_micp_mic_ctlr *mic_ctlr; + int err; + + UNSET_FLAG(flag_mics_discovered); + + err = bt_micp_mic_ctlr_discover(conn, &mic_ctlr); + if (err != 0) { + FAIL("Failed to discover MICS: %d\n", err); + return; + } + + WAIT_FOR_FLAG(flag_mics_discovered); +} + static void test_change_volume(void) { union bt_cap_set_member members[CONFIG_BT_MAX_CONN]; @@ -338,6 +406,35 @@ static void test_change_volume_offset(void) printk("Volume offset changed\n"); } +static void test_change_microphone_gain(void) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[CONFIG_BT_MAX_CONN]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = connected_conn_cnt, + }; + int err; + + printk("Changing microphone gain\n"); + UNSET_FLAG(flag_microphone_gain_changed); + + for (size_t i = 0U; i < param.count; i++) { + member_params[i].member.member = connected_conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + if (err != 0) { + FAIL("Failed to change microphone gain: %d\n", err); + return; + } + + WAIT_FOR_FLAG(flag_microphone_gain_changed); + printk("Microphone gain changed\n"); +} + static void test_main_cap_commander_capture_and_render(void) { init(); @@ -355,6 +452,10 @@ static void test_main_cap_commander_capture_and_render(void) if (IS_ENABLED(CONFIG_BT_VCP_VOL_CTLR)) { discover_vcs(connected_conns[i]); } + + if (IS_ENABLED(CONFIG_BT_MICP_MIC_CTLR)) { + discover_mics(connected_conns[i]); + } } if (IS_ENABLED(CONFIG_BT_CSIP_SET_COORDINATOR)) { @@ -368,7 +469,14 @@ static void test_main_cap_commander_capture_and_render(void) test_change_volume_offset(); } } - /* TODO: Add test of offset (VOCS), Mic (MICP) and gain (AICS) */ + + if (IS_ENABLED(CONFIG_BT_MICP_MIC_CTLR)) { + /* TODO: Add test of mic mute */ + + if (IS_ENABLED(CONFIG_BT_MICP_MIC_CTLR_AICS)) { + test_change_microphone_gain(); + } + } } /* Disconnect all CAP acceptors */ From 6f405f6b8028640dc851c2efe9896bf0fb538ece Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Thu, 21 Dec 2023 13:24:27 +0100 Subject: [PATCH 0541/2402] tests: Bluetooth: CAP Commander Change Microphone Gain unittests Adds unittests for the CAP Commander Change Microphone Gain procedure. Signed-off-by: Emil Gydesen --- .../audio/cap_commander/include/cap_mocks.h | 4 + tests/bluetooth/audio/cap_commander/prj.conf | 3 + .../bluetooth/audio/cap_commander/src/main.c | 228 ++++++++++++++++++ .../audio/cap_commander/uut/CMakeLists.txt | 2 + .../bluetooth/audio/cap_commander/uut/aics.c | 76 ++++++ .../bluetooth/audio/cap_commander/uut/micp.c | 117 +++++++++ .../audio/mocks/include/cap_commander.h | 1 + .../bluetooth/audio/mocks/src/cap_commander.c | 9 +- 8 files changed, 439 insertions(+), 1 deletion(-) create mode 100644 tests/bluetooth/audio/cap_commander/uut/aics.c create mode 100644 tests/bluetooth/audio/cap_commander/uut/micp.c diff --git a/tests/bluetooth/audio/cap_commander/include/cap_mocks.h b/tests/bluetooth/audio/cap_commander/include/cap_mocks.h index a907ab2b42c..b1d9f8246c3 100644 --- a/tests/bluetooth/audio/cap_commander/include/cap_mocks.h +++ b/tests/bluetooth/audio/cap_commander/include/cap_mocks.h @@ -4,8 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +void mock_bt_aics_init(void); +void mock_bt_aics_cleanup(void); void mock_bt_csip_init(void); void mock_bt_csip_cleanup(void); +void mock_bt_micp_init(void); +void mock_bt_micp_cleanup(void); void mock_bt_vcp_init(void); void mock_bt_vcp_cleanup(void); void mock_bt_vocs_init(void); diff --git a/tests/bluetooth/audio/cap_commander/prj.conf b/tests/bluetooth/audio/cap_commander/prj.conf index 247cffed78a..c281867619a 100644 --- a/tests/bluetooth/audio/cap_commander/prj.conf +++ b/tests/bluetooth/audio/cap_commander/prj.conf @@ -10,6 +10,9 @@ CONFIG_BT_VCP_VOL_CTLR=y CONFIG_BT_VOCS_CLIENT_MAX_INSTANCE_COUNT=1 CONFIG_BT_VCP_VOL_CTLR_MAX_VOCS_INST=1 CONFIG_BT_CSIP_SET_COORDINATOR=y +CONFIG_BT_MICP_MIC_CTLR=y +CONFIG_BT_AICS_CLIENT_MAX_INSTANCE_COUNT=1 +CONFIG_BT_MICP_MIC_CTLR_MAX_AICS_INST=1 CONFIG_BT_CAP_COMMANDER=y diff --git a/tests/bluetooth/audio/cap_commander/src/main.c b/tests/bluetooth/audio/cap_commander/src/main.c index f72d3d618e1..435a9fe85dd 100644 --- a/tests/bluetooth/audio/cap_commander/src/main.c +++ b/tests/bluetooth/audio/cap_commander/src/main.c @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -23,7 +24,9 @@ DEFINE_FFF_GLOBALS; static void mock_init_rule_before(const struct ztest_unit_test *test, void *fixture) { mock_cap_commander_init(); + mock_bt_aics_init(); mock_bt_csip_init(); + mock_bt_micp_init(); mock_bt_vcp_init(); mock_bt_vocs_init(); } @@ -31,7 +34,9 @@ static void mock_init_rule_before(const struct ztest_unit_test *test, void *fixt static void mock_destroy_rule_after(const struct ztest_unit_test *test, void *fixture) { mock_cap_commander_cleanup(); + mock_bt_aics_cleanup(); mock_bt_csip_cleanup(); + mock_bt_micp_cleanup(); mock_bt_vcp_cleanup(); mock_bt_vocs_cleanup(); } @@ -867,3 +872,226 @@ ZTEST_F(cap_commander_test_suite, test_commander_change_volume_mute_state_inval_ err = bt_cap_commander_change_volume_mute_state(¶m); zassert_equal(-EINVAL, err, "Unexpected return value %d", err); } + +ZTEST_F(cap_commander_test_suite, test_commander_change_microphone_gain_setting) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.microphone_gain_setting_changed", 1, + mock_cap_commander_microphone_gain_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_suite, test_commander_change_microphone_gain_setting_double) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.microphone_gain_setting_changed", 1, + mock_cap_commander_microphone_gain_changed_cb_fake.call_count); + + /* That that it still works as expected if we set the same value twice */ + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.microphone_gain_setting_changed", 2, + mock_cap_commander_microphone_gain_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_suite, test_commander_change_microphone_gain_setting_inval_param_null) +{ + int err; + + err = bt_cap_commander_change_microphone_gain_setting(NULL); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_suite, + test_commander_change_microphone_gain_setting_inval_param_null_param) +{ + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = NULL, + .count = ARRAY_SIZE(fixture->conns), + }; + int err; + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_suite, + test_commander_change_microphone_gain_setting_inval_param_null_member) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + member_params[ARRAY_SIZE(member_params) - 1].member.member = NULL; + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_suite, test_commander_change_microphone_gain_setting_inval_missing_cas) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ + + err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_suite, test_commander_change_microphone_gain_setting_inval_missing_aics) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_suite, + test_commander_change_microphone_gain_setting_inval_param_zero_count) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = 0U, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_suite, + test_commander_change_microphone_gain_setting_inval_param_inval_count) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = CONFIG_BT_MAX_CONN + 1, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} diff --git a/tests/bluetooth/audio/cap_commander/uut/CMakeLists.txt b/tests/bluetooth/audio/cap_commander/uut/CMakeLists.txt index d91bfbcbe7a..d1455879e57 100644 --- a/tests/bluetooth/audio/cap_commander/uut/CMakeLists.txt +++ b/tests/bluetooth/audio/cap_commander/uut/CMakeLists.txt @@ -11,7 +11,9 @@ add_library(uut STATIC ${ZEPHYR_BASE}/subsys/bluetooth/audio/cap_common.c ${ZEPHYR_BASE}/subsys/logging/log_minimal.c ${ZEPHYR_BASE}/subsys/net/buf_simple.c + aics.c csip.c + micp.c vcp.c vocs.c ) diff --git a/tests/bluetooth/audio/cap_commander/uut/aics.c b/tests/bluetooth/audio/cap_commander/uut/aics.c new file mode 100644 index 00000000000..5a4960a4636 --- /dev/null +++ b/tests/bluetooth/audio/cap_commander/uut/aics.c @@ -0,0 +1,76 @@ +/* csip.c - CAP Commander specific AICS mocks */ + +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +static struct bt_aics { + bool active; + struct bt_conn *conn; + struct bt_aics_cb *cb; +} aics_clients[CONFIG_BT_MAX_CONN * CONFIG_BT_AICS_CLIENT_MAX_INSTANCE_COUNT]; + +int bt_aics_client_conn_get(const struct bt_aics *aics, struct bt_conn **conn) +{ + *conn = aics->conn; + + return 0; +} + +int bt_aics_gain_set(struct bt_aics *aics, int8_t gain) +{ + if (aics != NULL && aics->cb != NULL && aics->cb->set_gain != NULL) { + aics->cb->set_gain(aics, 0); + } + + return 0; +} + +void bt_aics_client_cb_register(struct bt_aics *aics, struct bt_aics_cb *cb) +{ + aics->cb = cb; +} + +struct bt_aics *bt_aics_client_free_instance_get(void) +{ + for (size_t i = 0U; i < ARRAY_SIZE(aics_clients); i++) { + if (!aics_clients[i].active) { + aics_clients[i].active = true; + + return &aics_clients[i]; + } + } + + return NULL; +} + +int bt_aics_discover(struct bt_conn *conn, struct bt_aics *aics, + const struct bt_aics_discover_param *param) +{ + aics->conn = conn; + + if (aics != NULL && aics->cb != NULL && aics->cb->discover != NULL) { + aics->cb->discover(aics, 0); + } + + return 0; +} + +void mock_bt_aics_init(void) +{ +} + +void mock_bt_aics_cleanup(void) +{ + /* Reset everything but the callbacks, as they will not be registered again between each + * test + */ + for (size_t i = 0U; i < ARRAY_SIZE(aics_clients); i++) { + aics_clients[i].active = false; + aics_clients[i].conn = NULL; + } +} diff --git a/tests/bluetooth/audio/cap_commander/uut/micp.c b/tests/bluetooth/audio/cap_commander/uut/micp.c new file mode 100644 index 00000000000..03f17d00c63 --- /dev/null +++ b/tests/bluetooth/audio/cap_commander/uut/micp.c @@ -0,0 +1,117 @@ +/* csip.c - CAP Commander specific MICP mocks */ + +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +static struct bt_micp_mic_ctlr_cb *micp_cb; + +static struct bt_micp_mic_ctlr { + struct bt_conn *conn; + struct bt_aics *aics[CONFIG_BT_MICP_MIC_CTLR_MAX_AICS_INST]; +} mic_ctlrs[CONFIG_BT_MAX_CONN]; + +struct bt_micp_mic_ctlr *bt_micp_mic_ctlr_get_by_conn(const struct bt_conn *conn) +{ + for (size_t i = 0; i < ARRAY_SIZE(mic_ctlrs); i++) { + if (mic_ctlrs[i].conn == conn) { + return &mic_ctlrs[i]; + } + } + + return NULL; +} + +int bt_micp_mic_ctlr_conn_get(const struct bt_micp_mic_ctlr *mic_ctlr, struct bt_conn **conn) +{ + *conn = mic_ctlr->conn; + + return 0; +} + +int bt_micp_mic_ctlr_mute(struct bt_micp_mic_ctlr *mic_ctlr) +{ + if (micp_cb != NULL && micp_cb->mute_written != NULL) { + micp_cb->mute_written(mic_ctlr, 0); + } + + return 0; +} + +int bt_micp_mic_ctlr_unmute(struct bt_micp_mic_ctlr *mic_ctlr) +{ + if (micp_cb != NULL && micp_cb->unmute_written != NULL) { + micp_cb->unmute_written(mic_ctlr, 0); + } + + return 0; +} + +int bt_micp_mic_ctlr_discover(struct bt_conn *conn, struct bt_micp_mic_ctlr **mic_ctlr) +{ + for (size_t i = 0; i < ARRAY_SIZE(mic_ctlrs); i++) { + if (mic_ctlrs[i].conn == NULL) { + for (size_t j = 0U; j < ARRAY_SIZE(mic_ctlrs[i].aics); j++) { + const int err = bt_aics_discover(conn, mic_ctlrs[i].aics[j], NULL); + + if (err != 0) { + return err; + } + } + + mic_ctlrs[i].conn = conn; + *mic_ctlr = &mic_ctlrs[i]; + + return 0; + } + } + + return -ENOMEM; +} + +int bt_micp_mic_ctlr_cb_register(struct bt_micp_mic_ctlr_cb *cb) +{ + micp_cb = cb; + + if (IS_ENABLED(CONFIG_BT_MICP_MIC_CTLR_AICS)) { + for (size_t i = 0U; i < ARRAY_SIZE(mic_ctlrs); i++) { + for (size_t j = 0U; j < ARRAY_SIZE(mic_ctlrs[i].aics); j++) { + bt_aics_client_cb_register(mic_ctlrs[i].aics[j], &cb->aics_cb); + } + } + } + + return 0; +} + +int bt_micp_mic_ctlr_included_get(struct bt_micp_mic_ctlr *mic_ctlr, + struct bt_micp_included *included) +{ + included->aics_cnt = ARRAY_SIZE(mic_ctlr->aics); + included->aics = mic_ctlr->aics; + + return 0; +} + +void mock_bt_micp_init(void) +{ + if (IS_ENABLED(CONFIG_BT_MICP_MIC_CTLR_AICS)) { + for (size_t i = 0U; i < ARRAY_SIZE(mic_ctlrs); i++) { + for (size_t j = 0U; j < ARRAY_SIZE(mic_ctlrs[i].aics); j++) { + mic_ctlrs[i].aics[j] = bt_aics_client_free_instance_get(); + + __ASSERT(mic_ctlrs[i].aics[j], + "Could not allocate AICS client instance"); + } + } + } +} + +void mock_bt_micp_cleanup(void) +{ + memset(mic_ctlrs, 0, sizeof(mic_ctlrs)); +} diff --git a/tests/bluetooth/audio/mocks/include/cap_commander.h b/tests/bluetooth/audio/mocks/include/cap_commander.h index 8ccd2caf7ba..44c3b802895 100644 --- a/tests/bluetooth/audio/mocks/include/cap_commander.h +++ b/tests/bluetooth/audio/mocks/include/cap_commander.h @@ -20,5 +20,6 @@ DECLARE_FAKE_VOID_FUNC(mock_cap_commander_discovery_complete_cb, struct bt_conn DECLARE_FAKE_VOID_FUNC(mock_cap_commander_volume_changed_cb, struct bt_conn *, int); DECLARE_FAKE_VOID_FUNC(mock_cap_commander_volume_mute_changed_cb, struct bt_conn *, int); DECLARE_FAKE_VOID_FUNC(mock_cap_commander_volume_offset_changed_cb, struct bt_conn *, int); +DECLARE_FAKE_VOID_FUNC(mock_cap_commander_microphone_gain_changed_cb, struct bt_conn *, int); #endif /* MOCKS_CAP_COMMANDER_H_ */ diff --git a/tests/bluetooth/audio/mocks/src/cap_commander.c b/tests/bluetooth/audio/mocks/src/cap_commander.c index abf9245273c..073615625e6 100644 --- a/tests/bluetooth/audio/mocks/src/cap_commander.c +++ b/tests/bluetooth/audio/mocks/src/cap_commander.c @@ -13,7 +13,8 @@ FAKE(mock_cap_commander_discovery_complete_cb) \ FAKE(mock_cap_commander_volume_changed_cb) \ FAKE(mock_cap_commander_volume_mute_changed_cb) \ - FAKE(mock_cap_commander_volume_offset_changed_cb) + FAKE(mock_cap_commander_volume_offset_changed_cb) \ + FAKE(mock_cap_commander_microphone_gain_changed_cb) DEFINE_FAKE_VOID_FUNC(mock_cap_commander_discovery_complete_cb, struct bt_conn *, int, const struct bt_csip_set_coordinator_csis_inst *); @@ -21,6 +22,7 @@ DEFINE_FAKE_VOID_FUNC(mock_cap_commander_discovery_complete_cb, struct bt_conn * DEFINE_FAKE_VOID_FUNC(mock_cap_commander_volume_changed_cb, struct bt_conn *, int); DEFINE_FAKE_VOID_FUNC(mock_cap_commander_volume_mute_changed_cb, struct bt_conn *, int); DEFINE_FAKE_VOID_FUNC(mock_cap_commander_volume_offset_changed_cb, struct bt_conn *, int); +DEFINE_FAKE_VOID_FUNC(mock_cap_commander_microphone_gain_changed_cb, struct bt_conn *, int); const struct bt_cap_commander_cb mock_cap_commander_cb = { .discovery_complete = mock_cap_commander_discovery_complete_cb, @@ -31,6 +33,11 @@ const struct bt_cap_commander_cb mock_cap_commander_cb = { .volume_offset_changed = mock_cap_commander_volume_offset_changed_cb, #endif /* CONFIG_BT_VCP_VOL_CTLR */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ +#if defined(CONFIG_BT_MICP_MIC_CTLR) +#if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) + .microphone_gain_changed = mock_cap_commander_microphone_gain_changed_cb, +#endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ +#endif /* CONFIG_BT_MICP_MIC_CTLR */ }; void mock_cap_commander_init(void) From 164529145b61b82fcd51b0339528cb76d47694b3 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Thu, 21 Dec 2023 13:25:07 +0100 Subject: [PATCH 0542/2402] Bluetooth: Audio: Shell: CAP change microphone gain command Adds the change microphone gain command to the CAP commander shell. Signed-off-by: Emil Gydesen --- doc/connectivity/bluetooth/api/shell/cap.rst | 34 ++++++ subsys/bluetooth/audio/shell/cap_commander.c | 107 ++++++++++++++++++- 2 files changed, 140 insertions(+), 1 deletion(-) diff --git a/doc/connectivity/bluetooth/api/shell/cap.rst b/doc/connectivity/bluetooth/api/shell/cap.rst index f4a2490e28d..255a1113484 100644 --- a/doc/connectivity/bluetooth/api/shell/cap.rst +++ b/doc/connectivity/bluetooth/api/shell/cap.rst @@ -339,3 +339,37 @@ Setting the volume mute on all connected devices VCP volume 100, mute 0 VCP unmute done Volume mute change completed + +Setting the microphone gain on one or more devices +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +The gains are set by connection index, so connection index 0 gets the first offset, +and index 1 gets the second offset, etc.: + +.. code-block:: console + + uart:~$ bt connect + Connected: + uart:~$ cap_commander discover + discovery completed with CSIS + uart:~$ micp_mic_ctlr discover + MICP discover done with 1 AICS + uart:~$ + uart:~$ bt connect + Connected: + uart:~$ cap_commander discover + discovery completed with CSIS + uart:~$ micp_mic_ctlr discover + MICP discover done with 1 AICS + uart:~$ + uart:~$ cap_commander change_microphone_gain 10 + Setting microphone gain on 1 connections + AICS inst 0x200140a4 state gain 10, mute 0, mode 0 + Gain set for inst 0x200140a4 + Microphone gain change completed + uart:~$ + uart:~$ cap_commander change_microphone_gain 10 15 + Setting microphone gain on 2 connections + Gain set for inst 0x200140a4 + AICS inst 0x20014188 state gain 15, mute 0, mode 0 + Gain set for inst 0x20014188 + Microphone gain change completed diff --git a/subsys/bluetooth/audio/shell/cap_commander.c b/subsys/bluetooth/audio/shell/cap_commander.c index 4bef73488f5..af65e2eeafc 100644 --- a/subsys/bluetooth/audio/shell/cap_commander.c +++ b/subsys/bluetooth/audio/shell/cap_commander.c @@ -62,6 +62,20 @@ static void cap_volume_offset_changed_cb(struct bt_conn *conn, int err) #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ +#if defined(CONFIG_BT_MICP_MIC_CTLR) +#if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) +static void cap_microphone_gain_changed_cb(struct bt_conn *conn, int err) +{ + if (err != 0) { + shell_error(ctx_shell, "Microphone gain change failed (%d)", err); + return; + } + + shell_print(ctx_shell, "Microphone gain change completed"); +} +#endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ +#endif /* CONFIG_BT_MICP_MIC_CTLR */ + static struct bt_cap_commander_cb cbs = { .discovery_complete = cap_discover_cb, #if defined(CONFIG_BT_VCP_VOL_CTLR) @@ -71,6 +85,11 @@ static struct bt_cap_commander_cb cbs = { .volume_offset_changed = cap_volume_offset_changed_cb, #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ +#if defined(CONFIG_BT_MICP_MIC_CTLR) +#if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) + .microphone_gain_changed = cap_microphone_gain_changed_cb, +#endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ +#endif /* CONFIG_BT_MICP_MIC_CTLR */ }; static int cmd_cap_commander_discover(const struct shell *sh, size_t argc, char *argv[]) @@ -100,7 +119,7 @@ static int cmd_cap_commander_discover(const struct shell *sh, size_t argc, char return err; } -#if defined(CONFIG_BT_VCP_VOL_CTLR) +#if defined(CONFIG_BT_VCP_VOL_CTLR) || defined(CONFIG_BT_MICP_MIC_CTLR_AICS) static void populate_connected_conns(struct bt_conn *conn, void *data) { struct bt_conn **connected_conns = (struct bt_conn **)data; @@ -112,7 +131,9 @@ static void populate_connected_conns(struct bt_conn *conn, void *data) } } } +#endif /* CONFIG_BT_VCP_VOL_CTLR || CONFIG_BT_MICP_MIC_CTLR_AICS */ +#if defined(CONFIG_BT_VCP_VOL_CTLR) static int cmd_cap_commander_change_volume(const struct shell *sh, size_t argc, char *argv[]) { struct bt_conn *connected_conns[CONFIG_BT_MAX_CONN] = {0}; @@ -297,6 +318,83 @@ static int cmd_cap_commander_change_volume_offset(const struct shell *sh, size_t #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ +#if defined(CONFIG_BT_MICP_MIC_CTLR) +#if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) +static int cmd_cap_commander_change_microphone_gain(const struct shell *sh, size_t argc, + char *argv[]) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[CONFIG_BT_MAX_CONN]; + const size_t cap_args = argc - 1; /* First argument is the command itself */ + struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + }; + struct bt_conn *connected_conns[CONFIG_BT_MAX_CONN] = {0}; + size_t conn_cnt = 0U; + int err = 0; + + if (default_conn == NULL) { + shell_error(sh, "Not connected"); + return -ENOEXEC; + } + + /* Populate the array of connected connections */ + bt_conn_foreach(BT_CONN_TYPE_LE, populate_connected_conns, (void *)connected_conns); + for (size_t i = 0; i < ARRAY_SIZE(connected_conns); i++) { + struct bt_conn *conn = connected_conns[i]; + + if (conn == NULL) { + break; + } + + conn_cnt++; + } + + if (cap_args > conn_cnt) { + shell_error(sh, "Cannot use %zu arguments for %zu connections", argc, conn_cnt); + + return -ENOEXEC; + } + + /* TODO: Add support for coordinated sets */ + + for (size_t i = 0U; i < cap_args; i++) { + const char *arg = argv[i + 1]; + long gain; + + gain = shell_strtol(arg, 10, &err); + if (err != 0) { + shell_error(sh, "Failed to parse volume offset from %s", arg); + + return -ENOEXEC; + } + + if (!IN_RANGE(gain, INT8_MIN, INT8_MAX)) { + shell_error(sh, "Invalid gain %lu", gain); + + return -ENOEXEC; + } + + member_params[i].gain = (int8_t)gain; + member_params[i].member.member = connected_conns[i]; + param.count++; + } + + shell_print(sh, "Setting microphone gain on %zu connections", param.count); + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + if (err != 0) { + shell_print(sh, "Failed to change microphone gain: %d", err); + + return -ENOEXEC; + } + + return 0; +} +#endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ +#endif /* CONFIG_BT_MICP_MIC_CTLR */ + static int cmd_cap_commander(const struct shell *sh, size_t argc, char **argv) { if (argc > 1) { @@ -323,6 +421,13 @@ SHELL_STATIC_SUBCMD_SET_CREATE( cmd_cap_commander_change_volume_offset, 2, CONFIG_BT_MAX_CONN - 1), #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ +#if defined(CONFIG_BT_MICP_MIC_CTLR) +#if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) + SHELL_CMD_ARG(change_microphone_gain, NULL, + "Change microphone gain per connection ", + cmd_cap_commander_change_microphone_gain, 2, CONFIG_BT_MAX_CONN - 1), +#endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ +#endif /* CONFIG_BT_MICP_MIC_CTLR */ SHELL_SUBCMD_SET_END); SHELL_CMD_ARG_REGISTER(cap_commander, &cap_commander_cmds, "Bluetooth CAP commander shell commands", From e5573a6ee0cedc272ec7aa4e9ea1ce047f19b6b5 Mon Sep 17 00:00:00 2001 From: Eve Redero Date: Tue, 13 Feb 2024 18:17:41 +0100 Subject: [PATCH 0543/2402] doc: samples: lvgl: add details to lvgl demos readme LVGL demos in this folder are all based on pointer input devices, not any input devices types. Signed-off-by: Eve Redero --- samples/modules/lvgl/demos/README.rst | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/samples/modules/lvgl/demos/README.rst b/samples/modules/lvgl/demos/README.rst index cbc97616808..fe8f1bf7789 100644 --- a/samples/modules/lvgl/demos/README.rst +++ b/samples/modules/lvgl/demos/README.rst @@ -18,15 +18,27 @@ A sample showcasing upstream LVGL demos. * Widgets Shows how the widgets look like out of the box using the built-in material theme. +More details can be found in `LVGL demos Readme`_. + Requirements ************ * A board with display, ideally with 480x272 resolution or higher. +* A pointer input device: touchpad, mouse, or touch screen capable display, compatible with :dtcompatible:`zephyr,lvgl-pointer-input`. + +Note that other input devices types are not demonstrated in these demos, namely keyboards, keypads (:dtcompatible:`zephyr,lvgl-keypad-input`), rotary encoders (:dtcompatible:`zephyr,lvgl-encoder-input`) and hardware buttons (:dtcompatible:`zephyr,lvgl-button-input`). Building and Running ******************** -These demos can be built as follows: +Example building for :ref:`mimxrt1060_evk`: + +.. zephyr-app-commands:: + :zephyr-app: samples/modules/lvgl/demos + :board: mimxrt1060_evk + :goals: build flash + +These demos can be built for simulated display environment as follows: .. zephyr-app-commands:: :zephyr-app: samples/modules/lvgl/demos @@ -59,3 +71,11 @@ These demos can be built as follows: :gen-args: -DCONFIG_LV_Z_DEMO_WIDGETS=y :goals: run :compact: + +Alternatively, if building from a 64-bit host machine, the previous target +board argument may also be replaced by ``native_sim_64``. + +References +********** + +.. _LVGL demos Readme: https://github.com/zephyrproject-rtos/lvgl/blob/zephyr/demos/README.md From cdc36d090c0c0abc1006f8c3f10100b6c54d385f Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Wed, 6 Mar 2024 13:41:16 -0500 Subject: [PATCH 0544/2402] posix: sysconf: add a "small" implementation option Previously, sysconf() was only available as a macro (i.e. the "extra-small" option). This has the advantage of being compile-time constant, and optimized for both space and speed. One disadvantage is that querying an `_SC_` value that was invalid or unsupported would result in a compile error. Provide a "small" implementation of sysconf() (via Kconfig choice) as a normal addressable function. Signed-off-by: Christopher Friedt --- include/zephyr/posix/sys/sysconf.h | 279 +++++++++++++++++++++++++++++ include/zephyr/posix/unistd.h | 153 ++-------------- lib/posix/options/CMakeLists.txt | 1 + lib/posix/options/Kconfig.sysconf | 24 +++ lib/posix/options/sysconf.c | 266 +++++++++++++++++++++++++++ 5 files changed, 585 insertions(+), 138 deletions(-) create mode 100644 include/zephyr/posix/sys/sysconf.h create mode 100644 lib/posix/options/sysconf.c diff --git a/include/zephyr/posix/sys/sysconf.h b/include/zephyr/posix/sys/sysconf.h new file mode 100644 index 00000000000..a88f16493e1 --- /dev/null +++ b/include/zephyr/posix/sys/sysconf.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2024, Meta + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_POSIX_SYS_SYSCONF_H_ +#define ZEPHYR_INCLUDE_POSIX_SYS_SYSCONF_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef CONFIG_POSIX_SYSCONF + +enum { + _SC_ADVISORY_INFO, + _SC_ASYNCHRONOUS_IO, + _SC_BARRIERS, + _SC_CLOCK_SELECTION, + _SC_CPUTIME, + _SC_FSYNC, + _SC_IPV6, + _SC_JOB_CONTROL, + _SC_MAPPED_FILE, + _SC_MEMLOCK, + _SC_MEMLOCK_RANGE, + _SC_MEMORY_PROTECTION, + _SC_MESSAGE_PASSING, + _SC_MONOTONIC_CLOCK, + _SC_PRIORITIZED_IO, + _SC_PRIORITY_SCHEDULING, + _SC_RAW_SOCKETS, + _SC_RE_DUP_MAX, + _SC_READER_WRITER_LOCKS, + _SC_REALTIME_SIGNALS, + _SC_REGEXP, + _SC_SAVED_IDS, + _SC_SEMAPHORES, + _SC_SHARED_MEMORY_OBJECTS, + _SC_SHELL, + _SC_SPAWN, + _SC_SPIN_LOCKS, + _SC_SPORADIC_SERVER, + _SC_SS_REPL_MAX, + _SC_SYNCHRONIZED_IO, + _SC_THREAD_ATTR_STACKADDR, + _SC_THREAD_ATTR_STACKSIZE, + _SC_THREAD_CPUTIME, + _SC_THREAD_PRIO_INHERIT, + _SC_THREAD_PRIO_PROTECT, + _SC_THREAD_PRIORITY_SCHEDULING, + _SC_THREAD_PROCESS_SHARED, + _SC_THREAD_ROBUST_PRIO_INHERIT, + _SC_THREAD_ROBUST_PRIO_PROTECT, + _SC_THREAD_SAFE_FUNCTIONS, + _SC_THREAD_SPORADIC_SERVER, + _SC_THREADS, + _SC_TIMEOUTS, + _SC_TIMERS, + _SC_TRACE, + _SC_TRACE_EVENT_FILTER, + _SC_TRACE_EVENT_NAME_MAX, + _SC_TRACE_INHERIT, + _SC_TRACE_LOG, + _SC_TRACE_NAME_MAX, + _SC_TRACE_SYS_MAX, + _SC_TRACE_USER_EVENT_MAX, + _SC_TYPED_MEMORY_OBJECTS, + _SC_VERSION, + _SC_V7_ILP32_OFF32, + _SC_V7_ILP32_OFFBIG, + _SC_V7_LP64_OFF64, + _SC_V7_LPBIG_OFFBIG, + _SC_V6_ILP32_OFF32, + _SC_V6_ILP32_OFFBIG, + _SC_V6_LP64_OFF64, + _SC_V6_LPBIG_OFFBIG, + _SC_BC_BASE_MAX, + _SC_BC_DIM_MAX, + _SC_BC_SCALE_MAX, + _SC_BC_STRING_MAX, + _SC_2_C_BIND, + _SC_2_C_DEV, + _SC_2_CHAR_TERM, + _SC_COLL_WEIGHTS_MAX, + _SC_DELAYTIMER_MAX, + _SC_EXPR_NEST_MAX, + _SC_2_FORT_DEV, + _SC_2_FORT_RUN, + _SC_LINE_MAX, + _SC_2_LOCALEDEF, + _SC_2_PBS, + _SC_2_PBS_ACCOUNTING, + _SC_2_PBS_CHECKPOINT, + _SC_2_PBS_LOCATE, + _SC_2_PBS_MESSAGE, + _SC_2_PBS_TRACK, + _SC_2_SW_DEV, + _SC_2_UPE, + _SC_2_VERSION, + _SC_XOPEN_CRYPT, + _SC_XOPEN_ENH_I18N, + _SC_XOPEN_REALTIME, + _SC_XOPEN_REALTIME_THREADS, + _SC_XOPEN_SHM, + _SC_XOPEN_STREAMS, + _SC_XOPEN_UNIX, + _SC_XOPEN_UUCP, + _SC_XOPEN_VERSION, + _SC_CLK_TCK, + _SC_GETGR_R_SIZE_MAX, + _SC_GETPW_R_SIZE_MAX, + _SC_AIO_LISTIO_MAX, + _SC_AIO_MAX, + _SC_AIO_PRIO_DELTA_MAX, + _SC_ARG_MAX, + _SC_ATEXIT_MAX, + _SC_CHILD_MAX, + _SC_HOST_NAME_MAX, + _SC_IOV_MAX, + _SC_LOGIN_NAME_MAX, + _SC_NGROUPS_MAX, + _SC_MQ_OPEN_MAX, + _SC_MQ_PRIO_MAX, + _SC_OPEN_MAX, + _SC_PAGE_SIZE, + _SC_PAGESIZE, + _SC_THREAD_DESTRUCTOR_ITERATIONS, + _SC_THREAD_KEYS_MAX, + _SC_THREAD_STACK_MIN, + _SC_THREAD_THREADS_MAX, + _SC_RTSIG_MAX, + _SC_SEM_NSEMS_MAX, + _SC_SEM_VALUE_MAX, + _SC_SIGQUEUE_MAX, + _SC_STREAM_MAX, + _SC_SYMLOOP_MAX, + _SC_TIMER_MAX, + _SC_TTY_NAME_MAX, + _SC_TZNAME_MAX, +}; + +#ifdef CONFIG_POSIX_SYSCONF_IMPL_MACRO +#define __z_posix_sysconf_SC_ADVISORY_INFO _POSIX_ADVISORY_INFO +#define __z_posix_sysconf_SC_ASYNCHRONOUS_IO _POSIX_ASYNCHRONOUS_IO +#define __z_posix_sysconf_SC_BARRIERS _POSIX_BARRIERS +#define __z_posix_sysconf_SC_CLOCK_SELECTION _POSIX_CLOCK_SELECTION +#define __z_posix_sysconf_SC_CPUTIME _POSIX_CPUTIME +#define __z_posix_sysconf_SC_FSYNC _POSIX_FSYNC +#define __z_posix_sysconf_SC_IPV6 _POSIX_IPV6 +#define __z_posix_sysconf_SC_JOB_CONTROL _POSIX_JOB_CONTROL +#define __z_posix_sysconf_SC_MAPPED_FILE _POSIX_MAPPED_FILES +#define __z_posix_sysconf_SC_MEMLOCK _POSIX_MEMLOCK +#define __z_posix_sysconf_SC_MEMLOCK_RANGE _POSIX_MEMLOCK_RANGE +#define __z_posix_sysconf_SC_MEMORY_PROTECTION _POSIX_MEMORY_PROTECTION +#define __z_posix_sysconf_SC_MESSAGE_PASSING _POSIX_MESSAGE_PASSING +#define __z_posix_sysconf_SC_MONOTONIC_CLOCK _POSIX_MONOTONIC_CLOCK +#define __z_posix_sysconf_SC_PRIORITIZED_IO _POSIX_PRIORITIZED_IO +#define __z_posix_sysconf_SC_PRIORITY_SCHEDULING _POSIX_PRIORITY_SCHEDULING +#define __z_posix_sysconf_SC_RAW_SOCKETS _POSIX_RAW_SOCKETS +#define __z_posix_sysconf_SC_RE_DUP_MAX _POSIX_RE_DUP_MAX +#define __z_posix_sysconf_SC_READER_WRITER_LOCKS _POSIX_READER_WRITER_LOCKS +#define __z_posix_sysconf_SC_REALTIME_SIGNALS _POSIX_REALTIME_SIGNALS +#define __z_posix_sysconf_SC_REGEXP _POSIX_REGEXP +#define __z_posix_sysconf_SC_SAVED_IDS _POSIX_SAVED_IDS +#define __z_posix_sysconf_SC_SEMAPHORES _POSIX_SEMAPHORES +#define __z_posix_sysconf_SC_SHARED_MEMORY_OBJECTS _POSIX_SHARED_MEMORY_OBJECTS +#define __z_posix_sysconf_SC_SHELL _POSIX_SHELL +#define __z_posix_sysconf_SC_SPAWN _POSIX_SPAWN +#define __z_posix_sysconf_SC_SPIN_LOCKS _POSIX_SPIN_LOCKS +#define __z_posix_sysconf_SC_SPORADIC_SERVER _POSIX_SPORADIC_SERVER +#define __z_posix_sysconf_SC_SS_REPL_MAX _POSIX_SS_REPL_MAX +#define __z_posix_sysconf_SC_SYNCHRONIZED_IO _POSIX_SYNCHRONIZED_IO +#define __z_posix_sysconf_SC_THREAD_ATTR_STACKADDR _POSIX_THREAD_ATTR_STACKADDR +#define __z_posix_sysconf_SC_THREAD_ATTR_STACKSIZE _POSIX_THREAD_ATTR_STACKSIZE +#define __z_posix_sysconf_SC_THREAD_CPUTIME _POSIX_THREAD_CPUTIME +#define __z_posix_sysconf_SC_THREAD_PRIO_INHERIT _POSIX_THREAD_PRIO_INHERIT +#define __z_posix_sysconf_SC_THREAD_PRIO_PROTECT _POSIX_THREAD_PRIO_PROTECT +#define __z_posix_sysconf_SC_THREAD_PRIORITY_SCHEDULING _POSIX_THREAD_PRIORITY_SCHEDULING +#define __z_posix_sysconf_SC_THREAD_PROCESS_SHARED _POSIX_THREAD_PROCESS_SHARED +#define __z_posix_sysconf_SC_THREAD_ROBUST_PRIO_INHERIT _POSIX_THREAD_ROBUST_PRIO_INHERIT +#define __z_posix_sysconf_SC_THREAD_ROBUST_PRIO_PROTECT _POSIX_THREAD_ROBUST_PRIO_PROTECT +#define __z_posix_sysconf_SC_THREAD_SAFE_FUNCTIONS _POSIX_THREAD_SAFE_FUNCTIONS +#define __z_posix_sysconf_SC_THREAD_SPORADIC_SERVER _POSIX_THREAD_SPORADIC_SERVER +#define __z_posix_sysconf_SC_THREADS _POSIX_THREADS +#define __z_posix_sysconf_SC_TIMEOUTS _POSIX_TIMEOUTS +#define __z_posix_sysconf_SC_TIMERS _POSIX_TIMERS +#define __z_posix_sysconf_SC_TRACE _POSIX_TRACE +#define __z_posix_sysconf_SC_TRACE_EVENT_FILTER _POSIX_TRACE_EVENT_FILTER +#define __z_posix_sysconf_SC_TRACE_EVENT_NAME_MAX _POSIX_TRACE_EVENT_NAME_MAX +#define __z_posix_sysconf_SC_TRACE_INHERIT _POSIX_TRACE_INHERIT +#define __z_posix_sysconf_SC_TRACE_LOG _POSIX_TRACE_LOG +#define __z_posix_sysconf_SC_TRACE_NAME_MAX _POSIX_TRACE_NAME_MAX +#define __z_posix_sysconf_SC_TRACE_SYS_MAX _POSIX_TRACE_SYS_MAX +#define __z_posix_sysconf_SC_TRACE_USER_EVENT_MAX _POSIX_TRACE_USER_EVENT_MAX +#define __z_posix_sysconf_SC_TYPED_MEMORY_OBJECTS _POSIX_TYPED_MEMORY_OBJECTS +#define __z_posix_sysconf_SC_VERSION _POSIX_VERSION +#define __z_posix_sysconf_SC_V7_ILP32_OFF32 _POSIX_V7_ILP32_OFF32 +#define __z_posix_sysconf_SC_V7_ILP32_OFFBIG _POSIX_V7_ILP32_OFFBIG +#define __z_posix_sysconf_SC_V7_LP64_OFF64 _POSIX_V7_LP64_OFF64 +#define __z_posix_sysconf_SC_V7_LPBIG_OFFBIG _POSIX_V7_LPBIG_OFFBIG +#define __z_posix_sysconf_SC_V6_ILP32_OFF32 _POSIX_V6_ILP32_OFF32 +#define __z_posix_sysconf_SC_V6_ILP32_OFFBIG _POSIX_V6_ILP32_OFFBIG +#define __z_posix_sysconf_SC_V6_LP64_OFF64 _POSIX_V6_LP64_OFF64 +#define __z_posix_sysconf_SC_V6_LPBIG_OFFBIG _POSIX_V6_LPBIG_OFFBIG +#define __z_posix_sysconf_SC_BC_BASE_MAX _POSIX2_BC_BASE_MAX +#define __z_posix_sysconf_SC_BC_DIM_MAX _POSIX2_BC_DIM_MAX +#define __z_posix_sysconf_SC_BC_SCALE_MAX _POSIX2_BC_SCALE_MAX +#define __z_posix_sysconf_SC_BC_STRING_MAX _POSIX2_BC_STRING_MAX +#define __z_posix_sysconf_SC_2_C_BIND _POSIX2_C_BIND +#define __z_posix_sysconf_SC_2_C_DEV _POSIX2_C_DEV +#define __z_posix_sysconf_SC_2_CHAR_TERM _POSIX2_CHAR_TERM +#define __z_posix_sysconf_SC_COLL_WEIGHTS_MAX _POSIX2_COLL_WEIGHTS_MAX +#define __z_posix_sysconf_SC_DELAYTIMER_MAX _POSIX2_DELAYTIMER_MAX +#define __z_posix_sysconf_SC_EXPR_NEST_MAX _POSIX2_EXPR_NEST_MAX +#define __z_posix_sysconf_SC_2_FORT_DEV _POSIX2_FORT_DEV +#define __z_posix_sysconf_SC_2_FORT_RUN _POSIX2_FORT_RUN +#define __z_posix_sysconf_SC_LINE_MAX _POSIX2_LINE_MAX +#define __z_posix_sysconf_SC_2_LOCALEDEF _POSIX2_LOCALEDEF +#define __z_posix_sysconf_SC_2_PBS _POSIX2_PBS +#define __z_posix_sysconf_SC_2_PBS_ACCOUNTING _POSIX2_PBS_ACCOUNTING +#define __z_posix_sysconf_SC_2_PBS_CHECKPOINT _POSIX2_PBS_CHECKPOINT +#define __z_posix_sysconf_SC_2_PBS_LOCATE _POSIX2_PBS_LOCATE +#define __z_posix_sysconf_SC_2_PBS_MESSAGE _POSIX2_PBS_MESSAGE +#define __z_posix_sysconf_SC_2_PBS_TRACK _POSIX2_PBS_TRACK +#define __z_posix_sysconf_SC_2_SW_DEV _POSIX2_SW_DEV +#define __z_posix_sysconf_SC_2_UPE _POSIX2_UPE +#define __z_posix_sysconf_SC_2_VERSION _POSIX2_VERSION +#define __z_posix_sysconf_SC_XOPEN_CRYPT _XOPEN_CRYPT +#define __z_posix_sysconf_SC_XOPEN_ENH_I18N _XOPEN_ENH_I18N +#define __z_posix_sysconf_SC_XOPEN_REALTIME _XOPEN_REALTIME +#define __z_posix_sysconf_SC_XOPEN_REALTIME_THREADS _XOPEN_REALTIME_THREADS +#define __z_posix_sysconf_SC_XOPEN_SHM _XOPEN_SHM +#define __z_posix_sysconf_SC_XOPEN_STREAMS _XOPEN_STREAMS +#define __z_posix_sysconf_SC_XOPEN_UNIX _XOPEN_UNIX +#define __z_posix_sysconf_SC_XOPEN_UUCP _XOPEN_UUCP +#define __z_posix_sysconf_SC_XOPEN_VERSION _XOPEN_VERSION +#define __z_posix_sysconf_SC_CLK_TCK (100L) +#define __z_posix_sysconf_SC_GETGR_R_SIZE_MAX (0L) +#define __z_posix_sysconf_SC_GETPW_R_SIZE_MAX (0L) +#define __z_posix_sysconf_SC_AIO_LISTIO_MAX AIO_LISTIO_MAX +#define __z_posix_sysconf_SC_AIO_MAX AIO_MAX +#define __z_posix_sysconf_SC_AIO_PRIO_DELTA_MAX AIO_PRIO_DELTA_MAX +#define __z_posix_sysconf_SC_ARG_MAX ARG_MAX +#define __z_posix_sysconf_SC_ATEXIT_MAX ATEXIT_MAX +#define __z_posix_sysconf_SC_CHILD_MAX CHILD_MAX +#define __z_posix_sysconf_SC_HOST_NAME_MAX HOST_NAME_MAX +#define __z_posix_sysconf_SC_IOV_MAX IOV_MAX +#define __z_posix_sysconf_SC_LOGIN_NAME_MAX LOGIN_NAME_MAX +#define __z_posix_sysconf_SC_NGROUPS_MAX _POSIX_NGROUPS_MAX +#define __z_posix_sysconf_SC_MQ_OPEN_MAX MQ_OPEN_MAX +#define __z_posix_sysconf_SC_MQ_PRIO_MAX MQ_PRIO_MAX +#define __z_posix_sysconf_SC_OPEN_MAX CONFIG_POSIX_MAX_FDS +#define __z_posix_sysconf_SC_PAGE_SIZE PAGE_SIZE +#define __z_posix_sysconf_SC_PAGESIZE PAGESIZE +#define __z_posix_sysconf_SC_THREAD_DESTRUCTOR_ITERATIONS PTHREAD_DESTRUCTOR_ITERATIONS +#define __z_posix_sysconf_SC_THREAD_KEYS_MAX PTHREAD_KEYS_MAX +#define __z_posix_sysconf_SC_THREAD_STACK_MIN PTHREAD_STACK_MIN +#define __z_posix_sysconf_SC_THREAD_THREADS_MAX PTHREAD_THREADS_MAX +#define __z_posix_sysconf_SC_RTSIG_MAX RTSIG_MAX +#define __z_posix_sysconf_SC_SEM_NSEMS_MAX SEM_NSEMS_MAX +#define __z_posix_sysconf_SC_SEM_VALUE_MAX SEM_VALUE_MAX +#define __z_posix_sysconf_SC_SIGQUEUE_MAX SIGQUEUE_MAX +#define __z_posix_sysconf_SC_STREAM_MAX STREAM_MAX +#define __z_posix_sysconf_SC_SYMLOOP_MAX SYMLOOP_MAX +#define __z_posix_sysconf_SC_TIMER_MAX TIMER_MAX +#define __z_posix_sysconf_SC_TTY_NAME_MAX TTY_NAME_MAX +#define __z_posix_sysconf_SC_TZNAME_MAX TZNAME_MAX + +#define sysconf(x) (long)CONCAT(__z_posix_sysconf, x) +#endif + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_POSIX_SYS_SYSCONF_H_ */ diff --git a/include/zephyr/posix/unistd.h b/include/zephyr/posix/unistd.h index 36918c56365..e78c49fbeeb 100644 --- a/include/zephyr/posix/unistd.h +++ b/include/zephyr/posix/unistd.h @@ -7,20 +7,20 @@ #define ZEPHYR_INCLUDE_POSIX_UNISTD_H_ #include "posix_types.h" -#include + +#ifdef CONFIG_POSIX_API +#include +#endif #ifdef CONFIG_NETWORKING /* For zsock_gethostname() */ #include #include #endif - -#ifdef CONFIG_POSIX_API -#include -#endif - #ifdef CONFIG_POSIX_SYSCONF #include #endif +#include +#include #ifdef __cplusplus extern "C" { @@ -34,7 +34,7 @@ extern "C" { /* Internal helper macro to set constant if required Kconfig symbol is enabled */ #define Z_SC_VAL_IFDEF(_def, _val) COND_CODE_1(_def, (_val), (-1L)) -/* Constants for Opitions and Option Groups */ +/* Constants for Options and Option Groups */ #define _POSIX_ADVISORY_INFO (-1L) #define _POSIX_ASYNCHRONOUS_IO (-1L) #define _POSIX_BARRIERS Z_SC_VAL_IFDEF(CONFIG_PTHREAD_IPC, _POSIX_VERSION) @@ -99,6 +99,7 @@ extern "C" { #define _POSIX2_C_BIND _POSIX_VERSION #define _POSIX2_C_DEV (-1L) #define _POSIX2_CHAR_TERM (-1L) +#define _POSIX2_DELAYTIMER_MAX (-1L) #define _POSIX2_FORT_DEV (-1L) #define _POSIX2_FORT_RUN (-1L) #define _POSIX2_LOCALEDEF (-1L) @@ -191,6 +192,10 @@ extern "C" { #define MQ_OPEN_MAX _POSIX_MQ_OPEN_MAX #define MQ_PRIO_MAX _POSIX_MQ_PRIO_MAX +#ifndef ATEXIT_MAX +#define ATEXIT_MAX 8 +#endif + #ifndef PAGE_SIZE #define PAGE_SIZE BIT(CONFIG_POSIX_PAGE_SIZE_BITS) #endif @@ -257,137 +262,9 @@ extern int opterr, optind, optopt; pid_t getpid(void); unsigned sleep(unsigned int seconds); int usleep(useconds_t useconds); - -#ifdef CONFIG_POSIX_SYSCONF -#define __z_posix_sysconf_SC_ADVISORY_INFO _POSIX_ADVISORY_INFO -#define __z_posix_sysconf_SC_ASYNCHRONOUS_IO _POSIX_ASYNCHRONOUS_IO -#define __z_posix_sysconf_SC_BARRIERS _POSIX_BARRIERS -#define __z_posix_sysconf_SC_CLOCK_SELECTION _POSIX_CLOCK_SELECTION -#define __z_posix_sysconf_SC_CPUTIME _POSIX_CPUTIME -#define __z_posix_sysconf_SC_FSYNC _POSIX_FSYNC -#define __z_posix_sysconf_SC_IPV6 _POSIX_IPV6 -#define __z_posix_sysconf_SC_JOB_CONTROL _POSIX_JOB_CONTROL -#define __z_posix_sysconf_SC_MAPPED_FILE _POSIX_MAPPED_FILES -#define __z_posix_sysconf_SC_MEMLOCK _POSIX_MEMLOCK -#define __z_posix_sysconf_SC_MEMLOCK_RANGE _POSIX_MEMLOCK_RANGE -#define __z_posix_sysconf_SC_MEMORY_PROTECTION _POSIX_MEMORY_PROTECTION -#define __z_posix_sysconf_SC_MESSAGE_PASSING _POSIX_MESSAGE_PASSING -#define __z_posix_sysconf_SC_MONOTONIC_CLOCK _POSIX_MONOTONIC_CLOCK -#define __z_posix_sysconf_SC_PRIORITIZED_IO _POSIX_PRIORITIZED_IO -#define __z_posix_sysconf_SC_PRIORITY_SCHEDULING _POSIX_PRIORITY_SCHEDULING -#define __z_posix_sysconf_SC_RAW_SOCKETS _POSIX_RAW_SOCKETS -#define __z_posix_sysconf_SC_RE_DUP_MAX _POSIX_RE_DUP_MAX -#define __z_posix_sysconf_SC_READER_WRITER_LOCKS _POSIX_READER_WRITER_LOCKS -#define __z_posix_sysconf_SC_REALTIME_SIGNALS _POSIX_REALTIME_SIGNALS -#define __z_posix_sysconf_SC_REGEXP _POSIX_REGEXP -#define __z_posix_sysconf_SC_SAVED_IDS _POSIX_SAVED_IDS -#define __z_posix_sysconf_SC_SEMAPHORES _POSIX_SEMAPHORES -#define __z_posix_sysconf_SC_SHARED_MEMORY_OBJECTS _POSIX_SHARED_MEMORY_OBJECTS -#define __z_posix_sysconf_SC_SHELL _POSIX_SHELL -#define __z_posix_sysconf_SC_SPAWN _POSIX_SPAWN -#define __z_posix_sysconf_SC_SPIN_LOCKS _POSIX_SPIN_LOCKS -#define __z_posix_sysconf_SC_SPORADIC_SERVER _POSIX_SPORADIC_SERVER -#define __z_posix_sysconf_SC_SS_REPL_MAX _POSIX_SS_REPL_MAX -#define __z_posix_sysconf_SC_SYNCHRONIZED_IO _POSIX_SYNCHRONIZED_IO -#define __z_posix_sysconf_SC_THREAD_ATTR_STACKADDR _POSIX_THREAD_ATTR_STACKADDR -#define __z_posix_sysconf_SC_THREAD_ATTR_STACKSIZE _POSIX_THREAD_ATTR_STACKSIZE -#define __z_posix_sysconf_SC_THREAD_CPUTIME _POSIX_THREAD_CPUTIME -#define __z_posix_sysconf_SC_THREAD_PRIO_INHERIT _POSIX_THREAD_PRIO_INHERIT -#define __z_posix_sysconf_SC_THREAD_PRIO_PROTECT _POSIX_THREAD_PRIO_PROTECT -#define __z_posix_sysconf_SC_THREAD_PRIORITY_SCHEDULING _POSIX_THREAD_PRIORITY_SCHEDULING -#define __z_posix_sysconf_SC_THREAD_PROCESS_SHARED _POSIX_THREAD_PROCESS_SHARED -#define __z_posix_sysconf_SC_THREAD_ROBUST_PRIO_INHERIT _POSIX_THREAD_ROBUST_PRIO_INHERIT -#define __z_posix_sysconf_SC_THREAD_ROBUST_PRIO_PROTECT _POSIX_THREAD_ROBUST_PRIO_PROTECT -#define __z_posix_sysconf_SC_THREAD_SAFE_FUNCTIONS _POSIX_THREAD_SAFE_FUNCTIONS -#define __z_posix_sysconf_SC_THREAD_SPORADIC_SERVER _POSIX_THREAD_SPORADIC_SERVER -#define __z_posix_sysconf_SC_THREADS _POSIX_THREADS -#define __z_posix_sysconf_SC_TIMEOUTS _POSIX_TIMEOUTS -#define __z_posix_sysconf_SC_TIMERS _POSIX_TIMERS -#define __z_posix_sysconf_SC_TRACE _POSIX_TRACE -#define __z_posix_sysconf_SC_TRACE_EVENT_FILTER _POSIX_TRACE_EVENT_FILTER -#define __z_posix_sysconf_SC_TRACE_EVENT_NAME_MAX _POSIX_TRACE_EVENT_NAME_MAX -#define __z_posix_sysconf_SC_TRACE_INHERIT _POSIX_TRACE_INHERIT -#define __z_posix_sysconf_SC_TRACE_LOG _POSIX_TRACE_LOG -#define __z_posix_sysconf_SC_TRACE_NAME_MAX _POSIX_TRACE_NAME_MAX -#define __z_posix_sysconf_SC_TRACE_SYS_MAX _POSIX_TRACE_SYS_MAX -#define __z_posix_sysconf_SC_TRACE_USER_EVENT_MAX _POSIX_TRACE_USER_EVENT_MAX -#define __z_posix_sysconf_SC_TYPED_MEMORY_OBJECTS _POSIX_TYPED_MEMORY_OBJECTS -#define __z_posix_sysconf_SC_VERSION _POSIX_VERSION -#define __z_posix_sysconf_SC_V7_ILP32_OFF32 _POSIX_V7_ILP32_OFF32 -#define __z_posix_sysconf_SC_V7_ILP32_OFFBIG _POSIX_V7_ILP32_OFFBIG -#define __z_posix_sysconf_SC_V7_LP64_OFF64 _POSIX_V7_LP64_OFF64 -#define __z_posix_sysconf_SC_V7_LPBIG_OFFBIG _POSIX_V7_LPBIG_OFFBIG -#define __z_posix_sysconf_SC_V6_ILP32_OFF32 _POSIX_V6_ILP32_OFF32 -#define __z_posix_sysconf_SC_V6_ILP32_OFFBIG _POSIX_V6_ILP32_OFFBIG -#define __z_posix_sysconf_SC_V6_LP64_OFF64 _POSIX_V6_LP64_OFF64 -#define __z_posix_sysconf_SC_V6_LPBIG_OFFBIG _POSIX_V6_LPBIG_OFFBIG -#define __z_posix_sysconf_SC_BC_BASE_MAX _POSIX2_BC_BASE_MAX -#define __z_posix_sysconf_SC_BC_DIM_MAX _POSIX2_BC_DIM_MAX -#define __z_posix_sysconf_SC_BC_SCALE_MAX _POSIX2_BC_SCALE_MAX -#define __z_posix_sysconf_SC_BC_STRING_MAX _POSIX2_BC_STRING_MAX -#define __z_posix_sysconf_SC_2_C_BIND _POSIX2_C_BIND -#define __z_posix_sysconf_SC_2_C_DEV _POSIX2_C_DEV -#define __z_posix_sysconf_SC_2_CHAR_TERM _POSIX2_CHAR_TERM -#define __z_posix_sysconf_SC_COLL_WEIGHTS_MAX _POSIX2_COLL_WEIGHTS_MAX -#define __z_posix_sysconf_SC_DELAYTIMER_MAX _POSIX2_DELAYTIMER_MAX -#define __z_posix_sysconf_SC_EXPR_NEST_MAX _POSIX2_EXPR_NEST_MAX -#define __z_posix_sysconf_SC_2_FORT_DEV _POSIX2_FORT_DEV -#define __z_posix_sysconf_SC_2_FORT_RUN _POSIX2_FORT_RUN -#define __z_posix_sysconf_SC_LINE_MAX _POSIX2_LINE_MAX -#define __z_posix_sysconf_SC_2_LOCALEDEF _POSIX2_LOCALEDEF -#define __z_posix_sysconf_SC_2_PBS _POSIX2_PBS -#define __z_posix_sysconf_SC_2_PBS_ACCOUNTING _POSIX2_PBS_ACCOUNTING -#define __z_posix_sysconf_SC_2_PBS_CHECKPOINT _POSIX2_PBS_CHECKPOINT -#define __z_posix_sysconf_SC_2_PBS_LOCATE _POSIX2_PBS_LOCATE -#define __z_posix_sysconf_SC_2_PBS_MESSAGE _POSIX2_PBS_MESSAGE -#define __z_posix_sysconf_SC_2_PBS_TRACK _POSIX2_PBS_TRACK -#define __z_posix_sysconf_SC_2_SW_DEV _POSIX2_SW_DEV -#define __z_posix_sysconf_SC_2_UPE _POSIX2_UPE -#define __z_posix_sysconf_SC_2_VERSION _POSIX2_VERSION -#define __z_posix_sysconf_SC_XOPEN_CRYPT _XOPEN_CRYPT -#define __z_posix_sysconf_SC_XOPEN_ENH_I18N _XOPEN_ENH_I18N -#define __z_posix_sysconf_SC_XOPEN_REALTIME _XOPEN_REALTIME -#define __z_posix_sysconf_SC_XOPEN_REALTIME_THREADS _XOPEN_REALTIME_THREADS -#define __z_posix_sysconf_SC_XOPEN_SHM _XOPEN_SHM -#define __z_posix_sysconf_SC_XOPEN_STREAMS _XOPEN_STREAMS -#define __z_posix_sysconf_SC_XOPEN_UNIX _XOPEN_UNIX -#define __z_posix_sysconf_SC_XOPEN_UUCP _XOPEN_UUCP -#define __z_posix_sysconf_SC_XOPEN_VERSION _XOPEN_VERSION -#define __z_posix_sysconf_SC_CLK_TCK (100L) -#define __z_posix_sysconf_SC_GETGR_R_SIZE_MAX (0L) -#define __z_posix_sysconf_SC_GETPW_R_SIZE_MAX (0L) -#define __z_posix_sysconf_SC_AIO_LISTIO_MAX AIO_LISTIO_MAX -#define __z_posix_sysconf_SC_AIO_MAX AIO_MAX -#define __z_posix_sysconf_SC_AIO_PRIO_DELTA_MAX AIO_PRIO_DELTA_MAX -#define __z_posix_sysconf_SC_ARG_MAX ARG_MAX -#define __z_posix_sysconf_SC_ATEXIT_MAX ATEXIT_MAX -#define __z_posix_sysconf_SC_CHILD_MAX CHILD_MAX -#define __z_posix_sysconf_SC_HOST_NAME_MAX HOST_NAME_MAX -#define __z_posix_sysconf_SC_IOV_MAX IOV_MAX -#define __z_posix_sysconf_SC_LOGIN_NAME_MAX LOGIN_NAME_MAX -#define __z_posix_sysconf_SC_NGROUPS_MAX _POSIX_NGROUPS_MAX -#define __z_posix_sysconf_SC_MQ_OPEN_MAX MQ_OPEN_MAX -#define __z_posix_sysconf_SC_MQ_PRIO_MAX MQ_PRIO_MAX -#define __z_posix_sysconf_SC_OPEN_MAX CONFIG_POSIX_MAX_FDS -#define __z_posix_sysconf_SC_PAGE_SIZE PAGE_SIZE -#define __z_posix_sysconf_SC_PAGESIZE PAGESIZE -#define __z_posix_sysconf_SC_THREAD_DESTRUCTOR_ITERATIONS PTHREAD_DESTRUCTOR_ITERATIONS -#define __z_posix_sysconf_SC_THREAD_KEYS_MAX PTHREAD_KEYS_MAX -#define __z_posix_sysconf_SC_THREAD_STACK_MIN PTHREAD_STACK_MIN -#define __z_posix_sysconf_SC_THREAD_THREADS_MAX PTHREAD_THREADS_MAX -#define __z_posix_sysconf_SC_RTSIG_MAX RTSIG_MAX -#define __z_posix_sysconf_SC_SEM_NSEMS_MAX SEM_NSEMS_MAX -#define __z_posix_sysconf_SC_SEM_VALUE_MAX SEM_VALUE_MAX -#define __z_posix_sysconf_SC_SIGQUEUE_MAX SIGQUEUE_MAX -#define __z_posix_sysconf_SC_STREAM_MAX STREAM_MAX -#define __z_posix_sysconf_SC_SYMLOOP_MAX SYMLOOP_MAX -#define __z_posix_sysconf_SC_TIMER_MAX TIMER_MAX -#define __z_posix_sysconf_SC_TTY_NAME_MAX TTY_NAME_MAX -#define __z_posix_sysconf_SC_TZNAME_MAX TZNAME_MAX - -#define sysconf(x) (long)CONCAT(__z_posix_sysconf, x) - -#endif /* CONFIG_POSIX_SYSCONF */ +#ifdef CONFIG_POSIX_SYSCONF_IMPL_FULL +long sysconf(int opt); +#endif #ifdef __cplusplus } diff --git a/lib/posix/options/CMakeLists.txt b/lib/posix/options/CMakeLists.txt index 358ae925a43..3907238cd52 100644 --- a/lib/posix/options/CMakeLists.txt +++ b/lib/posix/options/CMakeLists.txt @@ -45,6 +45,7 @@ zephyr_library_sources_ifdef(CONFIG_POSIX_FS fs.c) zephyr_library_sources_ifdef(CONFIG_POSIX_MQUEUE mqueue.c) zephyr_library_sources_ifdef(CONFIG_POSIX_PUTMSG stropts.c) zephyr_library_sources_ifdef(CONFIG_POSIX_SIGNAL signal.c ${STRSIGNAL_TABLE_H}) +zephyr_library_sources_ifdef(CONFIG_POSIX_SYSCONF_IMPL_FULL sysconf.c) zephyr_library_sources_ifdef(CONFIG_POSIX_SYSLOG syslog.c) zephyr_library_sources_ifdef(CONFIG_POSIX_UNAME uname.c) zephyr_library_sources_ifdef(CONFIG_PTHREAD_IPC _common.c) diff --git a/lib/posix/options/Kconfig.sysconf b/lib/posix/options/Kconfig.sysconf index 32f37f1c29d..7e904d5b672 100644 --- a/lib/posix/options/Kconfig.sysconf +++ b/lib/posix/options/Kconfig.sysconf @@ -21,4 +21,28 @@ config POSIX_PAGE_SIZE_BITS PAGE_SIZE is supported in the range [64, 65536] If CONFIG_POSIX_API=y, PAGE_SIZE defaults to 4096, otherwise, it is 64 bytes. +if POSIX_SYSCONF + +choice POSIX_SYSCONF_IMPL_CHOICE + default POSIX_SYSCONF_IMPL_FULL if CPP + default POSIX_SYSCONF_IMPL_MACRO + prompt "Sysconf implementation method" + +config POSIX_SYSCONF_IMPL_MACRO + bool "Macro" + help + The sysconf() function is implemented compile-time constant via macros. This is the option + with the least overhead. The downside is that sysconf() is not an addressable function. + +config POSIX_SYSCONF_IMPL_FULL + bool "Full" + help + The sysconf() function is implemented as a large integer-integer array. The advantage if this + option is that all sysconf() options can be queried and that the sysconf() symbol is + addressable. + +endchoice + +endif # POSIX_SYSCONF + endmenu # "Sysconf support" diff --git a/lib/posix/options/sysconf.c b/lib/posix/options/sysconf.c new file mode 100644 index 00000000000..78491bd6eb0 --- /dev/null +++ b/lib/posix/options/sysconf.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2024, Meta + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +long sysconf(int x) +{ + switch (x) { + case _SC_ADVISORY_INFO: + return _POSIX_ADVISORY_INFO; + case _SC_ASYNCHRONOUS_IO: + return _POSIX_ASYNCHRONOUS_IO; + case _SC_BARRIERS: + return _POSIX_BARRIERS; + case _SC_CLOCK_SELECTION: + return _POSIX_CLOCK_SELECTION; + case _SC_CPUTIME: + return _POSIX_CPUTIME; + case _SC_FSYNC: + return _POSIX_FSYNC; + case _SC_IPV6: + return _POSIX_IPV6; + case _SC_JOB_CONTROL: + return _POSIX_JOB_CONTROL; + case _SC_MAPPED_FILE: + return _POSIX_MAPPED_FILES; + case _SC_MEMLOCK: + return _POSIX_MEMLOCK; + case _SC_MEMLOCK_RANGE: + return _POSIX_MEMLOCK_RANGE; + case _SC_MEMORY_PROTECTION: + return _POSIX_MEMORY_PROTECTION; + case _SC_MESSAGE_PASSING: + return _POSIX_MESSAGE_PASSING; + case _SC_MONOTONIC_CLOCK: + return _POSIX_MONOTONIC_CLOCK; + case _SC_PRIORITIZED_IO: + return _POSIX_PRIORITIZED_IO; + case _SC_PRIORITY_SCHEDULING: + return _POSIX_PRIORITY_SCHEDULING; + case _SC_RAW_SOCKETS: + return _POSIX_RAW_SOCKETS; + case _SC_RE_DUP_MAX: + return _POSIX_RE_DUP_MAX; + case _SC_READER_WRITER_LOCKS: + return _POSIX_READER_WRITER_LOCKS; + case _SC_REALTIME_SIGNALS: + return _POSIX_REALTIME_SIGNALS; + case _SC_REGEXP: + return _POSIX_REGEXP; + case _SC_SAVED_IDS: + return _POSIX_SAVED_IDS; + case _SC_SEMAPHORES: + return _POSIX_SEMAPHORES; + case _SC_SHARED_MEMORY_OBJECTS: + return _POSIX_SHARED_MEMORY_OBJECTS; + case _SC_SHELL: + return _POSIX_SHELL; + case _SC_SPAWN: + return _POSIX_SPAWN; + case _SC_SPIN_LOCKS: + return _POSIX_SPIN_LOCKS; + case _SC_SPORADIC_SERVER: + return _POSIX_SPORADIC_SERVER; + case _SC_SS_REPL_MAX: + return _POSIX_SS_REPL_MAX; + case _SC_SYNCHRONIZED_IO: + return _POSIX_SYNCHRONIZED_IO; + case _SC_THREAD_ATTR_STACKADDR: + return _POSIX_THREAD_ATTR_STACKADDR; + case _SC_THREAD_ATTR_STACKSIZE: + return _POSIX_THREAD_ATTR_STACKSIZE; + case _SC_THREAD_CPUTIME: + return _POSIX_THREAD_CPUTIME; + case _SC_THREAD_PRIO_INHERIT: + return _POSIX_THREAD_PRIO_INHERIT; + case _SC_THREAD_PRIO_PROTECT: + return _POSIX_THREAD_PRIO_PROTECT; + case _SC_THREAD_PRIORITY_SCHEDULING: + return _POSIX_THREAD_PRIORITY_SCHEDULING; + case _SC_THREAD_PROCESS_SHARED: + return _POSIX_THREAD_PROCESS_SHARED; + case _SC_THREAD_ROBUST_PRIO_INHERIT: + return _POSIX_THREAD_ROBUST_PRIO_INHERIT; + case _SC_THREAD_ROBUST_PRIO_PROTECT: + return _POSIX_THREAD_ROBUST_PRIO_PROTECT; + case _SC_THREAD_SAFE_FUNCTIONS: + return _POSIX_THREAD_SAFE_FUNCTIONS; + case _SC_THREAD_SPORADIC_SERVER: + return _POSIX_THREAD_SPORADIC_SERVER; + case _SC_THREADS: + return _POSIX_THREADS; + case _SC_TIMEOUTS: + return _POSIX_TIMEOUTS; + case _SC_TIMERS: + return _POSIX_TIMERS; + case _SC_TRACE: + return _POSIX_TRACE; + case _SC_TRACE_EVENT_FILTER: + return _POSIX_TRACE_EVENT_FILTER; + case _SC_TRACE_EVENT_NAME_MAX: + return _POSIX_TRACE_EVENT_NAME_MAX; + case _SC_TRACE_INHERIT: + return _POSIX_TRACE_INHERIT; + case _SC_TRACE_LOG: + return _POSIX_TRACE_LOG; + case _SC_TRACE_NAME_MAX: + return _POSIX_TRACE_NAME_MAX; + case _SC_TRACE_SYS_MAX: + return _POSIX_TRACE_SYS_MAX; + case _SC_TRACE_USER_EVENT_MAX: + return _POSIX_TRACE_USER_EVENT_MAX; + case _SC_TYPED_MEMORY_OBJECTS: + return _POSIX_TYPED_MEMORY_OBJECTS; + case _SC_VERSION: + return _POSIX_VERSION; + case _SC_V7_ILP32_OFF32: + return _POSIX_V7_ILP32_OFF32; + case _SC_V7_ILP32_OFFBIG: + return _POSIX_V7_ILP32_OFFBIG; + case _SC_V7_LP64_OFF64: + return _POSIX_V7_LP64_OFF64; + case _SC_V7_LPBIG_OFFBIG: + return _POSIX_V7_LPBIG_OFFBIG; + case _SC_V6_ILP32_OFF32: + return _POSIX_V6_ILP32_OFF32; + case _SC_V6_ILP32_OFFBIG: + return _POSIX_V6_ILP32_OFFBIG; + case _SC_V6_LP64_OFF64: + return _POSIX_V6_LP64_OFF64; + case _SC_V6_LPBIG_OFFBIG: + return _POSIX_V6_LPBIG_OFFBIG; + case _SC_BC_BASE_MAX: + return _POSIX2_BC_BASE_MAX; + case _SC_BC_DIM_MAX: + return _POSIX2_BC_DIM_MAX; + case _SC_BC_SCALE_MAX: + return _POSIX2_BC_SCALE_MAX; + case _SC_BC_STRING_MAX: + return _POSIX2_BC_STRING_MAX; + case _SC_2_C_BIND: + return _POSIX2_C_BIND; + case _SC_2_C_DEV: + return _POSIX2_C_DEV; + case _SC_2_CHAR_TERM: + return _POSIX2_CHAR_TERM; + case _SC_COLL_WEIGHTS_MAX: + return _POSIX2_COLL_WEIGHTS_MAX; + case _SC_DELAYTIMER_MAX: + return _POSIX2_DELAYTIMER_MAX; + case _SC_EXPR_NEST_MAX: + return _POSIX2_EXPR_NEST_MAX; + case _SC_2_FORT_DEV: + return _POSIX2_FORT_DEV; + case _SC_2_FORT_RUN: + return _POSIX2_FORT_RUN; + case _SC_LINE_MAX: + return _POSIX2_LINE_MAX; + case _SC_2_LOCALEDEF: + return _POSIX2_LOCALEDEF; + case _SC_2_PBS: + return _POSIX2_PBS; + case _SC_2_PBS_ACCOUNTING: + return _POSIX2_PBS_ACCOUNTING; + case _SC_2_PBS_CHECKPOINT: + return _POSIX2_PBS_CHECKPOINT; + case _SC_2_PBS_LOCATE: + return _POSIX2_PBS_LOCATE; + case _SC_2_PBS_MESSAGE: + return _POSIX2_PBS_MESSAGE; + case _SC_2_PBS_TRACK: + return _POSIX2_PBS_TRACK; + case _SC_2_SW_DEV: + return _POSIX2_SW_DEV; + case _SC_2_UPE: + return _POSIX2_UPE; + case _SC_2_VERSION: + return _POSIX2_VERSION; + case _SC_XOPEN_CRYPT: + return _XOPEN_CRYPT; + case _SC_XOPEN_ENH_I18N: + return _XOPEN_ENH_I18N; + case _SC_XOPEN_REALTIME: + return _XOPEN_REALTIME; + case _SC_XOPEN_REALTIME_THREADS: + return _XOPEN_REALTIME_THREADS; + case _SC_XOPEN_SHM: + return _XOPEN_SHM; + case _SC_XOPEN_STREAMS: + return _XOPEN_STREAMS; + case _SC_XOPEN_UNIX: + return _XOPEN_UNIX; + case _SC_XOPEN_UUCP: + return _XOPEN_UUCP; + case _SC_XOPEN_VERSION: + return _XOPEN_VERSION; + case _SC_CLK_TCK: + return (100L); + case _SC_GETGR_R_SIZE_MAX: + return (0L); + case _SC_GETPW_R_SIZE_MAX: + return (0L); + case _SC_AIO_LISTIO_MAX: + return AIO_LISTIO_MAX; + case _SC_AIO_MAX: + return AIO_MAX; + case _SC_AIO_PRIO_DELTA_MAX: + return AIO_PRIO_DELTA_MAX; + case _SC_ARG_MAX: + return ARG_MAX; + case _SC_ATEXIT_MAX: + return ATEXIT_MAX; + case _SC_CHILD_MAX: + return CHILD_MAX; + case _SC_HOST_NAME_MAX: + return _POSIX_HOST_NAME_MAX; + case _SC_IOV_MAX: + return IOV_MAX; + case _SC_LOGIN_NAME_MAX: + return LOGIN_NAME_MAX; + case _SC_NGROUPS_MAX: + return _POSIX_NGROUPS_MAX; + case _SC_MQ_OPEN_MAX: + return MQ_OPEN_MAX; + case _SC_MQ_PRIO_MAX: + return MQ_PRIO_MAX; + case _SC_OPEN_MAX: + return CONFIG_POSIX_MAX_FDS; + case _SC_PAGE_SIZE: + return PAGE_SIZE; + case _SC_PAGESIZE: + return PAGESIZE; + case _SC_THREAD_DESTRUCTOR_ITERATIONS: + return PTHREAD_DESTRUCTOR_ITERATIONS; + case _SC_THREAD_KEYS_MAX: + return PTHREAD_KEYS_MAX; + case _SC_THREAD_STACK_MIN: + return PAGE_SIZE; + case _SC_THREAD_THREADS_MAX: + return PTHREAD_THREADS_MAX; + case _SC_RTSIG_MAX: + return RTSIG_MAX; + case _SC_SEM_NSEMS_MAX: + return SEM_NSEMS_MAX; + case _SC_SEM_VALUE_MAX: + return SEM_VALUE_MAX; + case _SC_SIGQUEUE_MAX: + return SIGQUEUE_MAX; + case _SC_STREAM_MAX: + return STREAM_MAX; + case _SC_SYMLOOP_MAX: + return SYMLOOP_MAX; + case _SC_TIMER_MAX: + return TIMER_MAX; + case _SC_TTY_NAME_MAX: + return TTY_NAME_MAX; + case _SC_TZNAME_MAX: + return TZNAME_MAX; + default: + errno = EINVAL; + return -1; + } +} From 5b8b9c9f6ae7f89614a3d230c58d73bcd9578fa0 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 8 Mar 2024 16:39:11 +0100 Subject: [PATCH 0545/2402] manifest: Update nrf hw models to latest * Update the HW models module to ffd0ddec0239a47739892f4e705e97b2285a8508 Including the following: * ffd0dde HAL: RTC2 for nrf52833 was missing * 12e66d1 PPI: Connect RTC tasks * e4f3ab9 TIMER: Fix for CAPTURE task when counter was never started Signed-off-by: Alberto Escolar Piedras --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 093e3e0d6e9..9d3acf9af5b 100644 --- a/west.yml +++ b/west.yml @@ -295,7 +295,7 @@ manifest: groups: - tools - name: nrf_hw_models - revision: 319e3ebd3134935c330980dfac53d05d28c0af9a + revision: ffd0ddec0239a47739892f4e705e97b2285a8508 path: modules/bsim_hw_models/nrf_hw_models - name: open-amp revision: da78aea63159771956fe0c9263f2e6985b66e9d5 From 62e9a3859083807aeab088059efe9333a07b7771 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 8 Mar 2024 14:47:26 +0100 Subject: [PATCH 0546/2402] drivers counter_nrfx_rtc: Fix for simulation For simulation, let's convert the hardcoded DT/real HW address to the valid addr for simulation on the fly. Signed-off-by: Alberto Escolar Piedras --- drivers/counter/counter_nrfx_rtc.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/counter/counter_nrfx_rtc.c b/drivers/counter/counter_nrfx_rtc.c index d6888988b8c..203f980e78d 100644 --- a/drivers/counter/counter_nrfx_rtc.c +++ b/drivers/counter/counter_nrfx_rtc.c @@ -44,6 +44,12 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_COUNTER_LOG_LEVEL); #define CC_ADJUSTED_OFFSET 16 #define CC_ADJ_MASK(chan) (BIT(chan + CC_ADJUSTED_OFFSET)) +#if defined(CONFIG_SOC_SERIES_BSIM_NRFXX) +#define MAYBE_CONST_CONFIG +#else +#define MAYBE_CONST_CONFIG const +#endif + struct counter_nrfx_data { counter_top_callback_t top_cb; void *top_user_data; @@ -534,11 +540,20 @@ static uint32_t get_pending_int(const struct device *dev) static int init_rtc(const struct device *dev, uint32_t prescaler) { - const struct counter_nrfx_config *nrfx_config = dev->config; + MAYBE_CONST_CONFIG struct counter_nrfx_config *nrfx_config = + (MAYBE_CONST_CONFIG struct counter_nrfx_config *) dev->config; struct counter_nrfx_data *data = dev->data; struct counter_top_cfg top_cfg = { .ticks = NRF_RTC_COUNTER_MAX }; + +#if defined(CONFIG_SOC_SERIES_BSIM_NRFXX) + /* For simulated devices we need to convert the hardcoded DT address from the real + * peripheral into the correct one for simulation + */ + nrfx_config->rtc = nhw_convert_periph_base_addr(nrfx_config->rtc); +#endif + NRF_RTC_Type *rtc = nrfx_config->rtc; int err; @@ -705,7 +720,8 @@ static const struct counter_driver_api counter_nrfx_driver_api = { static struct counter_nrfx_ch_data \ counter##idx##_ch_data[DT_INST_PROP(idx, cc_num)]; \ LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_COUNTER_LOG_LEVEL); \ - static const struct counter_nrfx_config nrfx_counter_##idx##_config = {\ + static MAYBE_CONST_CONFIG \ + struct counter_nrfx_config nrfx_counter_##idx##_config = { \ .info = { \ .max_top_value = NRF_RTC_COUNTER_MAX, \ .freq = DT_INST_PROP(idx, clock_frequency) / \ From 16cbf8062006578cd33e67d1868601d4d2a2c069 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 8 Mar 2024 16:35:16 +0100 Subject: [PATCH 0547/2402] tests/drivers/counter/counter_basic_api: Add overlay for nrf52_bsim Add a DT overlay so this test can also be run in the nrf52_bsim simulated board. Signed-off-by: Alberto Escolar Piedras --- .../drivers/counter/counter_basic_api/boards/nrf52_bsim.overlay | 1 + 1 file changed, 1 insertion(+) create mode 100644 tests/drivers/counter/counter_basic_api/boards/nrf52_bsim.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/nrf52_bsim.overlay b/tests/drivers/counter/counter_basic_api/boards/nrf52_bsim.overlay new file mode 100644 index 00000000000..26039327f93 --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/nrf52_bsim.overlay @@ -0,0 +1 @@ +#include "nrf52833dk_nrf52833.overlay" From 7e47979876a744bdc5b796e18ea45a7933fa28f7 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 8 Mar 2024 16:36:05 +0100 Subject: [PATCH 0548/2402] nrf52_bsim: Claim support for counter to enable tests Let's set the counter tag so counter tests run in this platform. Signed-off-by: Alberto Escolar Piedras --- boards/native/nrf_bsim/nrf52_bsim.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/native/nrf_bsim/nrf52_bsim.yaml b/boards/native/nrf_bsim/nrf52_bsim.yaml index 17aba03864e..adff9a6add5 100644 --- a/boards/native/nrf_bsim/nrf52_bsim.yaml +++ b/boards/native/nrf_bsim/nrf52_bsim.yaml @@ -13,3 +13,4 @@ testing: - bsim_skip_CI supported: - gpio + - counter From 2e5a71961eab9c246c6704f86e24f2326063850b Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 8 Mar 2024 16:36:45 +0100 Subject: [PATCH 0549/2402] tests/drivers/counter: Allow on nrf52_bsim Allow all tests which run in the real nrf52840 to also run in the simulated nrf52_bsim. That way we will have runtime tests in CI. Signed-off-by: Alberto Escolar Piedras --- tests/drivers/counter/counter_basic_api/testcase.yaml | 4 +++- tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/tests/drivers/counter/counter_basic_api/testcase.yaml b/tests/drivers/counter/counter_basic_api/testcase.yaml index f4f1120fdf9..3b9098e47e2 100644 --- a/tests/drivers/counter/counter_basic_api/testcase.yaml +++ b/tests/drivers/counter/counter_basic_api/testcase.yaml @@ -12,7 +12,9 @@ tests: - drivers - counter depends_on: counter - platform_allow: nrf52840dk/nrf52840 + platform_allow: + - nrf52840dk/nrf52840 + - nrf52_bsim timeout: 400 extra_configs: - CONFIG_ZERO_LATENCY_IRQS=y diff --git a/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml b/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml index af42d7b327c..2905fe55a1c 100644 --- a/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml +++ b/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml @@ -4,4 +4,6 @@ tests: - drivers - counter depends_on: counter - platform_allow: nrf52840dk/nrf52840 + platform_allow: + - nrf52840dk/nrf52840 + - nrf52_bsim From d706367423b5393f9946c546a04c871cf646ddb8 Mon Sep 17 00:00:00 2001 From: Georgios Vasilakis Date: Fri, 8 Mar 2024 16:01:11 +0100 Subject: [PATCH 0550/2402] soc: nordic: nrf54l: Remove redundant option The option SOC_NRF54L_GLITCHDET_WORKAROUND is not needed anymore becuase the glitch detector is already disabled in the Nordic MDK in the hal_nordic repo. File path in hal_nordic: nrfx/mdk/system_nrf54l.c Signed-off-by: Georgios Vasilakis --- soc/nordic/nrf54l/Kconfig | 6 ------ soc/nordic/nrf54l/soc.c | 4 ---- 2 files changed, 10 deletions(-) diff --git a/soc/nordic/nrf54l/Kconfig b/soc/nordic/nrf54l/Kconfig index 6841e1478f7..c7e00565c54 100644 --- a/soc/nordic/nrf54l/Kconfig +++ b/soc/nordic/nrf54l/Kconfig @@ -43,12 +43,6 @@ config SOC_NRF54L_VREG_MAIN_DCDC config SOC_NRF54L_NORMAL_VOLTAGE_MODE bool "NRF54L Normal Voltage Mode." -config SOC_NRF54L_GLITCHDET_WORKAROUND - bool "Workaround that disables glitch detector" - default y - help - Temporary workaround - disabling glitch detector to limit power consumption. - if NRF_GRTC_TIMER config ELV_GRTC_LFXO_ALLOWED diff --git a/soc/nordic/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c index a7b286fa048..6af0ff4ebcd 100644 --- a/soc/nordic/nrf54l/soc.c +++ b/soc/nordic/nrf54l/soc.c @@ -42,10 +42,6 @@ static int nordicsemi_nrf54l_init(void) /* Enable ICACHE */ sys_cache_instr_enable(); - if (IS_ENABLED(CONFIG_SOC_NRF54L_GLITCHDET_WORKAROUND)) { - nrf_glitchdet_enable_set(NRF_GLITCHDET, false); - } - #if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal) uint32_t xosc32ktrim = NRF_FICR->XOSC32KTRIM; From 6d40cb8038c214d18b3baf48e52364eaab7ee6a0 Mon Sep 17 00:00:00 2001 From: Dominik Ermel Date: Fri, 8 Mar 2024 16:10:24 +0000 Subject: [PATCH 0551/2402] tests/flash: Fix nrf52840dk configurations The commit disables QSPI in SoC configurations, as QSPI got enabled by default and test never really run on SoC. In QSPI configuration erase page size is set to 4096 There is not TC_PRINT showing name of device that the test will run on, in test setup. The nrf52840dk configuration files have been renamed to reflect dk name and SoC. Signed-off-by: Dominik Ermel --- ..._flash_qspi.conf => nrf52840dk_nrf52840_qspi_nor.conf} | 1 + ...f52840_flash_soc.conf => nrf52840dk_nrf52840_soc.conf} | 1 + tests/drivers/flash/common/src/main.c | 1 + tests/drivers/flash/common/testcase.yaml | 8 ++++---- 4 files changed, 7 insertions(+), 4 deletions(-) rename tests/drivers/flash/common/boards/{nrf52840_flash_qspi.conf => nrf52840dk_nrf52840_qspi_nor.conf} (67%) rename tests/drivers/flash/common/boards/{nrf52840_flash_soc.conf => nrf52840dk_nrf52840_soc.conf} (81%) diff --git a/tests/drivers/flash/common/boards/nrf52840_flash_qspi.conf b/tests/drivers/flash/common/boards/nrf52840dk_nrf52840_qspi_nor.conf similarity index 67% rename from tests/drivers/flash/common/boards/nrf52840_flash_qspi.conf rename to tests/drivers/flash/common/boards/nrf52840dk_nrf52840_qspi_nor.conf index f995a2d2993..2f45801a48c 100644 --- a/tests/drivers/flash/common/boards/nrf52840_flash_qspi.conf +++ b/tests/drivers/flash/common/boards/nrf52840dk_nrf52840_qspi_nor.conf @@ -2,3 +2,4 @@ # on nrf52840dk/nrf52840 board CONFIG_NORDIC_QSPI_NOR=y +CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096 diff --git a/tests/drivers/flash/common/boards/nrf52840_flash_soc.conf b/tests/drivers/flash/common/boards/nrf52840dk_nrf52840_soc.conf similarity index 81% rename from tests/drivers/flash/common/boards/nrf52840_flash_soc.conf rename to tests/drivers/flash/common/boards/nrf52840dk_nrf52840_soc.conf index f28de713011..7102a58c245 100644 --- a/tests/drivers/flash/common/boards/nrf52840_flash_soc.conf +++ b/tests/drivers/flash/common/boards/nrf52840dk_nrf52840_soc.conf @@ -2,3 +2,4 @@ # on nrf52840dk/nrf52840 board CONFIG_MPU_ALLOW_FLASH_WRITE=y +CONFIG_NORDIC_QSPI_NOR=n diff --git a/tests/drivers/flash/common/src/main.c b/tests/drivers/flash/common/src/main.c index 91b478109d7..d3c5d8b7cf6 100644 --- a/tests/drivers/flash/common/src/main.c +++ b/tests/drivers/flash/common/src/main.c @@ -54,6 +54,7 @@ static void *flash_driver_setup(void) { int rc; + TC_PRINT("Test will run on device %s\n", flash_dev->name); zassert_true(device_is_ready(flash_dev)); flash_params = flash_get_parameters(flash_dev); diff --git a/tests/drivers/flash/common/testcase.yaml b/tests/drivers/flash/common/testcase.yaml index 0e0b1ce546d..5bfd4a20944 100644 --- a/tests/drivers/flash/common/testcase.yaml +++ b/tests/drivers/flash/common/testcase.yaml @@ -5,20 +5,20 @@ common: tests: drivers.flash.common.nrf_qspi_nor: platform_allow: nrf52840dk/nrf52840 - extra_args: OVERLAY_CONFIG=boards/nrf52840_flash_qspi.conf + extra_args: OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_qspi_nor.conf integration_platforms: - nrf52840dk/nrf52840 drivers.flash.common.nrf_qspi_nor.size_in_bytes: platform_allow: nrf52840dk/nrf52840 extra_args: - - OVERLAY_CONFIG=boards/nrf52840_flash_qspi.conf + - OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_qspi_nor.conf - DTC_OVERLAY_FILE=boards/nrf52840_size_in_bytes.overlay integration_platforms: - nrf52840dk/nrf52840 drivers.flash.common.nrf_qspi_nor_4B_addr: platform_allow: nrf52840dk/nrf52840 extra_args: - - OVERLAY_CONFIG=boards/nrf52840_flash_qspi.conf + - OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_qspi_nor.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_mx25l51245g.overlay harness_config: fixture: external_flash_mx25l51245g @@ -26,7 +26,7 @@ tests: - nrf52840dk/nrf52840 drivers.flash.common.soc_flash_nrf: platform_allow: nrf52840dk/nrf52840 - extra_args: OVERLAY_CONFIG=boards/nrf52840_flash_soc.conf + extra_args: OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_soc.conf integration_platforms: - nrf52840dk/nrf52840 drivers.flash.common.default: From 025032232c740dbae55724b905c36951c62d5cca Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Mon, 11 Mar 2024 22:53:26 +0100 Subject: [PATCH 0552/2402] Bluetooth: BAP: Shell: Fix issue with stopping broadcast sink When the broadcast sink is stopped, the sink was also set to NULL via default_broadcast_sink.bap_sink = NULL; However the lifetime of the broadcast sink does not follow the state of the streams, and it still exists afterwards. The broadcast sink can only be terminated (deleted) via the term_broadcast_sink command. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/shell/bap.c | 1 - 1 file changed, 1 deletion(-) diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index 172b43e8c84..343f14eeddd 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -2451,7 +2451,6 @@ static void stream_stopped_cb(struct bt_bap_stream *stream, uint8_t reason) if (default_broadcast_sink.stream_cnt == 0) { /* All streams in the broadcast sink has been terminated */ default_broadcast_sink.syncable = true; - default_broadcast_sink.bap_sink = NULL; memset(&default_broadcast_sink.received_base, 0, sizeof(default_broadcast_sink.received_base)); default_broadcast_sink.broadcast_id = 0; From f9932c578da534fa4f2733c6f6f838fe0482f0ef Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 11 Mar 2024 13:38:42 -0400 Subject: [PATCH 0553/2402] tests: benchmark: adapt recording of benchmark results We now have a different output, so capture it correctly. Signed-off-by: Anas Nashif --- tests/benchmarks/latency_measure/testcase.yaml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/benchmarks/latency_measure/testcase.yaml b/tests/benchmarks/latency_measure/testcase.yaml index 76ed840c7cf..9036ae7527f 100644 --- a/tests/benchmarks/latency_measure/testcase.yaml +++ b/tests/benchmarks/latency_measure/testcase.yaml @@ -16,7 +16,7 @@ tests: harness_config: type: one_line record: - regex: "(?P.*):(?P.*) cycles ,(?P.*) ns" + regex: "(?P.*) - (?P.*):(?P.*) cycles ,(?P.*) ns" regex: - "PROJECT EXECUTION SUCCESSFUL" @@ -37,7 +37,7 @@ tests: harness_config: type: one_line record: - regex: "(?P.*):(?P.*) cycles ,(?P.*) ns" + regex: "(?P.*) - (?P.*):(?P.*) cycles ,(?P.*) ns" regex: - "PROJECT EXECUTION SUCCESSFUL" @@ -54,7 +54,7 @@ tests: harness_config: type: one_line record: - regex: "(?P.*):(?P.*) cycles ,(?P.*) ns" + regex: "(?P.*) - (?P.*):(?P.*) cycles ,(?P.*) ns" regex: - "PROJECT EXECUTION SUCCESSFUL" @@ -72,7 +72,7 @@ tests: harness_config: type: one_line record: - regex: "(?P.*):(?P.*) cycles ,(?P.*) ns" + regex: "(?P.*) - (?P.*):(?P.*) cycles ,(?P.*) ns" regex: - "PROJECT EXECUTION SUCCESSFUL" @@ -93,7 +93,7 @@ tests: harness_config: type: one_line record: - regex: "(?P.*):(?P.*) cycles ,(?P.*) ns" + regex: "(?P.*) - (?P.*):(?P.*) cycles ,(?P.*) ns" regex: - "PROJECT EXECUTION SUCCESSFUL" @@ -113,7 +113,7 @@ tests: harness_config: type: one_line record: - regex: "(?P.*):(?P.*) cycles ,(?P.*) ns" + regex: "(?P.*) - (?P.*):(?P.*) cycles ,(?P.*) ns" regex: - "PROJECT EXECUTION SUCCESSFUL" @@ -131,6 +131,6 @@ tests: harness_config: type: one_line record: - regex: "(?P.*):(?P.*) cycles ,(?P.*) ns" + regex: "(?P.*) - (?P.*):(?P.*) cycles ,(?P.*) ns" regex: - "PROJECT EXECUTION SUCCESSFUL" From 5b6fadc10d3be7120a808928f11389a6151944d2 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 8 Mar 2024 12:22:00 -0600 Subject: [PATCH 0554/2402] drivers: mipi_dbi: mipi_dbi_spi: do not take spinlock Taking a spinlock will result in interrupts being blocked in the MIPI DBI driver, which is not desired behavior while issuing SPI transfers, since the driver may use interrupts to drive the transfer Fixes #68815 Signed-off-by: Daniel DeGrasse --- drivers/mipi_dbi/mipi_dbi_spi.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/mipi_dbi/mipi_dbi_spi.c b/drivers/mipi_dbi/mipi_dbi_spi.c index 87456868e0d..846158efee6 100644 --- a/drivers/mipi_dbi/mipi_dbi_spi.c +++ b/drivers/mipi_dbi/mipi_dbi_spi.c @@ -25,7 +25,7 @@ struct mipi_dbi_spi_config { struct mipi_dbi_spi_data { /* Used for 3 wire mode */ uint16_t spi_byte; - struct k_spinlock lock; + struct k_mutex lock; }; /* Expands to 1 if the node does not have the `write-only` property */ @@ -58,7 +58,11 @@ static int mipi_dbi_spi_write_helper(const struct device *dev, .count = 1, }; int ret = 0; - k_spinlock_key_t spinlock_key = k_spin_lock(&data->lock); + + ret = k_mutex_lock(&data->lock, K_FOREVER); + if (ret < 0) { + return ret; + } if (dbi_config->mode == MIPI_DBI_MODE_SPI_3WIRE && IS_ENABLED(CONFIG_MIPI_DBI_SPI_3WIRE)) { @@ -124,7 +128,7 @@ static int mipi_dbi_spi_write_helper(const struct device *dev, ret = -ENOTSUP; } out: - k_spin_unlock(&data->lock, spinlock_key); + k_mutex_unlock(&data->lock); return ret; } @@ -164,9 +168,12 @@ static int mipi_dbi_spi_command_read(const struct device *dev, .count = 1, }; int ret = 0; - k_spinlock_key_t spinlock_key = k_spin_lock(&data->lock); struct spi_config tmp_config; + ret = k_mutex_lock(&data->lock, K_FOREVER); + if (ret < 0) { + return ret; + } memcpy(&tmp_config, &dbi_config->config, sizeof(tmp_config)); if (dbi_config->mode == MIPI_DBI_MODE_SPI_3WIRE && IS_ENABLED(CONFIG_MIPI_DBI_SPI_3WIRE)) { @@ -231,7 +238,7 @@ static int mipi_dbi_spi_command_read(const struct device *dev, } out: spi_release(config->spi_dev, &tmp_config); - k_spin_unlock(&data->lock, spinlock_key); + k_mutex_unlock(&data->lock); return ret; } @@ -262,6 +269,7 @@ static int mipi_dbi_spi_reset(const struct device *dev, uint32_t delay) static int mipi_dbi_spi_init(const struct device *dev) { const struct mipi_dbi_spi_config *config = dev->config; + struct mipi_dbi_spi_data *data = dev->data; int ret; if (!device_is_ready(config->spi_dev)) { @@ -291,6 +299,8 @@ static int mipi_dbi_spi_init(const struct device *dev) } } + k_mutex_init(&data->lock); + return 0; } From c15f029a7108117ab62d3275b77cddd8d77e0b81 Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Wed, 21 Feb 2024 00:32:59 +0000 Subject: [PATCH 0555/2402] init.h: restore designated initializers in SYS_INIT_NAMED() As seen in the PR #68125 discussion, commit 19a33c788413 ("init: adjust the SYS_INIT dev field init to play nice with older compilers") entirely threw away designated initializers in SYS_INIT_NAMED() to avoid compatibility issues across toolchains. One key aspect that was probably missed at the time: C and C++ are two different languages and this is especially true with respect to designated initializers. Designated initializers provide safer and more readable code, especially in their much stricter C++ version. So use an #ifdef to restore them in SYS_INIT_NAMED() thanks to a small braces difference between C and C++. Signed-off-by: Marc Herbert --- include/zephyr/init.h | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/include/zephyr/init.h b/include/zephyr/init.h index 2788dc01afd..512ea9f67be 100644 --- a/include/zephyr/init.h +++ b/include/zephyr/init.h @@ -151,6 +151,39 @@ struct init_entry { __attribute__((__section__( \ ".z_init_" #level STRINGIFY(prio)"_" STRINGIFY(sub_prio)"_"))) + +/* Designated initializers where added to C in C99. There were added to + * C++ 20 years later in a much more restricted form. C99 allows many + * variations: out of order, mix of designated and not, overlap, + * override,... but C++ allows none of these. See differences detailed + * in the P0329R0.pdf C++ proposal. + * Note __STDC_VERSION__ is undefined when compiling C++. + */ +#if defined(__STDC_VERSION__) && (__STDC_VERSION__) < 201100 + +/* Anonymous unions require C11. Some pre-C11 gcc versions have early + * support for anonymous unions but they require these braces when + * combined with C99 designated initializers, see longer discussion in + * #69411. + * These braces are compatible with any C version but not with C++20. + */ +# define Z_INIT_SYS_INIT_DEV_NULL { .dev = NULL } + +#else + +/* When using -std=c++20 or higher, g++ (v12.2.0) reject braces for + * initializing anonymous unions because it is technically a mix of + * designated and not designated initializers which is not allowed in + * C++. Interestingly, the _same_ g++ version does accept the braces above + * when using -std=c++17 or lower! + * The tests/lib/cpp/cxx/ added by commit 3d9c428d57bf invoke the C++ + * compiler with a range of different `-std=...` parameters without needing + * any manual configuration. + */ +# define Z_INIT_SYS_INIT_DEV_NULL .dev = NULL + +#endif + /** @endcond */ /** @@ -205,7 +238,8 @@ struct init_entry { #define SYS_INIT_NAMED(name, init_fn_, level, prio) \ static const Z_DECL_ALIGN(struct init_entry) \ Z_INIT_ENTRY_SECTION(level, prio, 0) __used __noasan \ - Z_INIT_ENTRY_NAME(name) = {{ (init_fn_) }, { NULL } } + Z_INIT_ENTRY_NAME(name) = {.init_fn = {.sys = (init_fn_)}, \ + Z_INIT_SYS_INIT_DEV_NULL} /** @} */ From 07426a800c74b6884273719b71627e54e5266923 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Fri, 2 Feb 2024 18:43:44 +0000 Subject: [PATCH 0556/2402] intel_adsp/ace: power: Lock interruption when power gate fails In case the core is not power gated, waiti will restore intlevel. In this case we lock interruption after it. In the bug scenario, the host starts streaming and via SOF APIs, keeps a lock to prevent Zephyr from entering PM_STATE_RUNTIME_IDLE. During the test case, host removes this block and core0 is allowed to enter IDLE state. When core0 enters power gated state, interrrupts are left enabled (so the core can be woken up when something happens). This leaves a race where suitably timed interrupt will actually block entry to power gated state and k_cpu_idle() in power_gate_entry() will return. This is rare, but happens often enough that the relatively short test plan run on SOF pull-requests will trigger this case. Fixes #69807 Signed-off-by: Flavio Ceolin Signed-off-by: Anas Nashif --- soc/intel/intel_adsp/ace/power.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/soc/intel/intel_adsp/ace/power.c b/soc/intel/intel_adsp/ace/power.c index 2a5712d9cbe..b9f1ba9fbd9 100644 --- a/soc/intel/intel_adsp/ace/power.c +++ b/soc/intel/intel_adsp/ace/power.c @@ -176,6 +176,13 @@ void power_gate_entry(uint32_t core_id) soc_cpus_active[core_id] = false; sys_cache_data_flush_range(soc_cpus_active, sizeof(soc_cpus_active)); k_cpu_idle(); + + /* It is unlikely we get in here, but when this happens + * we need to lock interruptions again. + * + * @note Zephyr looks PS.INTLEVEL to check if interruptions are locked. + */ + (void)arch_irq_lock(); z_xt_ints_off(0xffffffff); } From 53561e3766b9fe100247669c3cb29d20f87f3607 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Tue, 12 Mar 2024 16:08:59 +0100 Subject: [PATCH 0557/2402] net: dns: Fix timeout calculation with DNS retransmissions With recently introduced DNS retransmission mechanism, a certain bug could occur when calculating query timeout. If the time until the final DNS timeout (as indicated by CONFIG_NET_SOCKETS_DNS_TIMEOUT) was less than 1 millisecond, the actual millisecond timeout value was rounded down, resulting in 0 ms timeout. This in order was interpreted as invalid argument by dns_get_addr_info() function, so in result, instead of reporting query timeout, the function reported invalid argument error. Fix this by rounding the millisecond timeout up, instead of down, so that in any case, if the final timeout is not due, we always provide non-zero timeout to dns_get_addr_info(). Signed-off-by: Robert Lubos --- subsys/net/lib/sockets/getaddrinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/lib/sockets/getaddrinfo.c b/subsys/net/lib/sockets/getaddrinfo.c index a7f2b54b604..70e32001770 100644 --- a/subsys/net/lib/sockets/getaddrinfo.c +++ b/subsys/net/lib/sockets/getaddrinfo.c @@ -133,7 +133,7 @@ static int exec_query(const char *host, int family, } again: - timeout_ms = k_ticks_to_ms_floor32(timeout.ticks); + timeout_ms = k_ticks_to_ms_ceil32(timeout.ticks); NET_DBG("Timeout %d", timeout_ms); From 3667526b832d4925edac085ac30c653b844bd121 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Mon, 12 Feb 2024 14:39:27 -0600 Subject: [PATCH 0558/2402] boards: lpcxpresso55s69: Fix misnomer pinmux.c is inaptly named since it has nothing to do with pinmux. Also, remove inclusion of iocon.h since this file does not use it, as this file has nothing to do with pinmux. Signed-off-by: Declan Snyder --- boards/nxp/lpcxpresso55s69/CMakeLists.txt | 2 +- boards/nxp/lpcxpresso55s69/{pinmux.c => board.c} | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) rename boards/nxp/lpcxpresso55s69/{pinmux.c => board.c} (92%) diff --git a/boards/nxp/lpcxpresso55s69/CMakeLists.txt b/boards/nxp/lpcxpresso55s69/CMakeLists.txt index 5ee9a437bf5..93ac1145c89 100644 --- a/boards/nxp/lpcxpresso55s69/CMakeLists.txt +++ b/boards/nxp/lpcxpresso55s69/CMakeLists.txt @@ -6,4 +6,4 @@ # zephyr_library() -zephyr_library_sources(pinmux.c) +zephyr_library_sources(board.c) diff --git a/boards/nxp/lpcxpresso55s69/pinmux.c b/boards/nxp/lpcxpresso55s69/board.c similarity index 92% rename from boards/nxp/lpcxpresso55s69/pinmux.c rename to boards/nxp/lpcxpresso55s69/board.c index 36095b2a923..9908b589b98 100644 --- a/boards/nxp/lpcxpresso55s69/pinmux.c +++ b/boards/nxp/lpcxpresso55s69/board.c @@ -6,10 +6,9 @@ #include #include #include -#include #include -static int lpcxpresso_55s69_pinmux_init(void) +static int lpcxpresso_55s69_board_init(void) { #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_i2s, okay)) && \ @@ -52,4 +51,4 @@ static int lpcxpresso_55s69_pinmux_init(void) return 0; } -SYS_INIT(lpcxpresso_55s69_pinmux_init, PRE_KERNEL_1, 0); +SYS_INIT(lpcxpresso_55s69_board_init, PRE_KERNEL_1, 0); From 4ad9f9063848e9ef96a3952ab917938b103081d6 Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Sun, 10 Mar 2024 02:02:18 +0000 Subject: [PATCH 0559/2402] llext.c: fix logging of 64 bits pointers Note `elf64_addr` and friends are defined as uint64_t which is defined as `long long unsigned` which is for some reason different from `size_t`. So they all require a cast. Signed-off-by: Marc Herbert --- subsys/llext/llext.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/subsys/llext/llext.c b/subsys/llext/llext.c index e36dbd86633..309048e4568 100644 --- a/subsys/llext/llext.c +++ b/subsys/llext/llext.c @@ -147,24 +147,24 @@ static int llext_find_tables(struct llext_loader *ldr) i++, pos += ldr->hdr.e_shentsize) { ret = llext_seek(ldr, pos); if (ret != 0) { - LOG_ERR("failed seeking to position %u\n", pos); + LOG_ERR("failed seeking to position %zu\n", pos); return ret; } ret = llext_read(ldr, &shdr, sizeof(elf_shdr_t)); if (ret != 0) { - LOG_ERR("failed reading section header at position %u\n", pos); + LOG_ERR("failed reading section header at position %zu\n", pos); return ret; } - LOG_DBG("section %d at %x: name %d, type %d, flags %x, addr %x, size %d", + LOG_DBG("section %d at %zx: name %d, type %d, flags %zx, addr %zx, size %zd", i, - ldr->hdr.e_shoff + i * ldr->hdr.e_shentsize, + (size_t)ldr->hdr.e_shoff + i * ldr->hdr.e_shentsize, shdr.sh_name, shdr.sh_type, - shdr.sh_flags, - shdr.sh_addr, - shdr.sh_size); + (size_t)shdr.sh_flags, + (size_t)shdr.sh_addr, + (size_t)shdr.sh_size); switch (shdr.sh_type) { case SHT_SYMTAB: @@ -570,9 +570,9 @@ static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, */ uint8_t *text = ext->mem[LLEXT_MEM_TEXT]; - LOG_DBG("Found %p in PLT %u size %u cnt %u text %p", + LOG_DBG("Found %p in PLT %u size %zu cnt %u text %p", (void *)llext_string(ldr, ext, LLEXT_MEM_SHSTRTAB, shdr->sh_name), - shdr->sh_type, shdr->sh_entsize, sh_cnt, (void *)text); + shdr->sh_type, (size_t)shdr->sh_entsize, sh_cnt, (void *)text); const elf_shdr_t *sym_shdr = ldr->sects + LLEXT_MEM_SYMTAB; unsigned int sym_cnt = sym_shdr->sh_size / sym_shdr->sh_entsize; @@ -654,9 +654,9 @@ static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, } } - LOG_DBG("symbol %s offset %#x r-offset %#x .text offset %#x stb %u", + LOG_DBG("symbol %s offset %#zx r-offset %#zx .text offset %#zx stb %u", name, got_offset, - rela.r_offset, ldr->sects[LLEXT_MEM_TEXT].sh_offset, stb); + (size_t)rela.r_offset, (size_t)ldr->sects[LLEXT_MEM_TEXT].sh_offset, stb); } } @@ -717,8 +717,8 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local continue; } - LOG_DBG("relocation section %s (%d) linked to section %d has %d relocations", - name, i, shdr.sh_link, rel_cnt); + LOG_DBG("relocation section %s (%d) linked to section %d has %zd relocations", + name, i, shdr.sh_link, (size_t)rel_cnt); for (int j = 0; j < rel_cnt; j++) { /* get each relocation entry */ @@ -746,10 +746,10 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local name = llext_string(ldr, ext, LLEXT_MEM_STRTAB, sym.st_name); - LOG_DBG("relocation %d:%d info %x (type %d, sym %d) offset %d sym_name " + LOG_DBG("relocation %d:%d info %x (type %d, sym %d) offset %zd sym_name " "%s sym_type %d sym_bind %d sym_ndx %d", i, j, rel.r_info, ELF_R_TYPE(rel.r_info), ELF_R_SYM(rel.r_info), - rel.r_offset, name, ELF_ST_TYPE(sym.st_info), + (size_t)rel.r_offset, name, ELF_ST_TYPE(sym.st_info), ELF_ST_BIND(sym.st_info), sym.st_shndx); uintptr_t link_addr, op_loc; @@ -762,8 +762,8 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local if (link_addr == 0) { LOG_ERR("Undefined symbol with no entry in " - "symbol table %s, offset %d, link section %d", - name, rel.r_offset, shdr.sh_link); + "symbol table %s, offset %zd, link section %d", + name, (size_t)rel.r_offset, shdr.sh_link); return -ENODATA; } } else if (ELF_ST_TYPE(sym.st_info) == STT_SECTION || @@ -780,9 +780,9 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local } LOG_INF("relocating (linking) symbol %s type %d binding %d ndx %d offset " - "%d link section %d", + "%zd link section %d", name, ELF_ST_TYPE(sym.st_info), ELF_ST_BIND(sym.st_info), - sym.st_shndx, rel.r_offset, shdr.sh_link); + sym.st_shndx, (size_t)rel.r_offset, shdr.sh_link); LOG_INF("writing relocation symbol %s type %d sym %d at addr 0x%lx " "addr 0x%lx", @@ -822,7 +822,7 @@ static int do_llext_load(struct llext_loader *ldr, struct llext *ext, ldr->sect_map = k_heap_alloc(&llext_heap, sect_map_sz, K_NO_WAIT); if (!ldr->sect_map) { - LOG_ERR("Failed to allocate memory for section map, size %u", sect_map_sz); + LOG_ERR("Failed to allocate memory for section map, size %zu", sect_map_sz); ret = -ENOMEM; goto out; } From 7eb1d3d57d2d0c0484935199503de97815ea243c Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Sun, 10 Mar 2024 04:23:29 +0000 Subject: [PATCH 0560/2402] llext: elf.h: fix wrong 32 bits length of elf64_rela fields Fixes commit a9a82d557c72 ("llext: use elf_rela_t instead of elf_rel_t") Also switch sign of (unused?) `r_addend` to unsigned. https://refspecs.linuxfoundation.org/elf/gabi4+/ch4.reloc.html Issue found thanks to the following warnings when compiling in 64bits: ``` /__w/zephyr/zephyr/include/zephyr/llext/elf.h:349:29: error: right shift count >= width of type [-Werror=shift-count-overflow] 349 | #define ELF64_R_SYM(i) ((i) >> 32) ``` The name `elf64_word` was admittedly confusing. Signed-off-by: Marc Herbert --- include/zephyr/llext/elf.h | 4 ++-- subsys/llext/llext.c | 9 +++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/include/zephyr/llext/elf.h b/include/zephyr/llext/elf.h index a9fd8f86a94..dd2482b2466 100644 --- a/include/zephyr/llext/elf.h +++ b/include/zephyr/llext/elf.h @@ -338,8 +338,8 @@ struct elf64_rel { struct elf64_rela { elf64_addr r_offset; - elf64_word r_info; - elf64_word r_addend; + elf64_xword r_info; + elf64_sxword r_addend; }; /** @brief Relocation symbol from r_info diff --git a/subsys/llext/llext.c b/subsys/llext/llext.c index 309048e4568..a6ed1e4ac86 100644 --- a/subsys/llext/llext.c +++ b/subsys/llext/llext.c @@ -746,9 +746,10 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local name = llext_string(ldr, ext, LLEXT_MEM_STRTAB, sym.st_name); - LOG_DBG("relocation %d:%d info %x (type %d, sym %d) offset %zd sym_name " + LOG_DBG("relocation %d:%d info %zx (type %zd, sym %zd) offset %zd sym_name " "%s sym_type %d sym_bind %d sym_ndx %d", - i, j, rel.r_info, ELF_R_TYPE(rel.r_info), ELF_R_SYM(rel.r_info), + i, j, (size_t)rel.r_info, (size_t)ELF_R_TYPE(rel.r_info), + (size_t)ELF_R_SYM(rel.r_info), (size_t)rel.r_offset, name, ELF_ST_TYPE(sym.st_info), ELF_ST_BIND(sym.st_info), sym.st_shndx); @@ -784,9 +785,9 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local name, ELF_ST_TYPE(sym.st_info), ELF_ST_BIND(sym.st_info), sym.st_shndx, (size_t)rel.r_offset, shdr.sh_link); - LOG_INF("writing relocation symbol %s type %d sym %d at addr 0x%lx " + LOG_INF("writing relocation symbol %s type %zd sym %zd at addr 0x%lx " "addr 0x%lx", - name, ELF_R_TYPE(rel.r_info), ELF_R_SYM(rel.r_info), + name, (size_t)ELF_R_TYPE(rel.r_info), (size_t)ELF_R_SYM(rel.r_info), op_loc, link_addr); /* relocation */ From 03a79d63877375c62e563238858de22bd20b01b3 Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Sun, 10 Mar 2024 04:32:58 +0000 Subject: [PATCH 0561/2402] llext: elf.h: fix sign of the `r_addend` field of struct elf32_rela The r_addend field is signed (it seems unused for now). Fixes commit a9a82d557c72 ("llext: use elf_rela_t instead of elf_rel_t") https://refspecs.linuxfoundation.org/elf/gabi4+/ch4.reloc.html Signed-off-by: Marc Herbert --- include/zephyr/llext/elf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/llext/elf.h b/include/zephyr/llext/elf.h index dd2482b2466..ac781316581 100644 --- a/include/zephyr/llext/elf.h +++ b/include/zephyr/llext/elf.h @@ -309,7 +309,7 @@ struct elf32_rel { struct elf32_rela { elf32_addr r_offset; elf32_word r_info; - elf32_word r_addend; + elf32_sword r_addend; }; /** From d123a4571a1060835aab8d6ac063ecc3d5c59640 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Sat, 9 Mar 2024 16:07:55 +0000 Subject: [PATCH 0562/2402] input: kbd_matrix: define PRIkbdrow coherently It's not supposed to have the "%" in the macro, reuse the existin one for the data type. Signed-off-by: Fabio Baltieri --- drivers/input/input_kbd_matrix.c | 2 +- include/zephyr/input/input_kbd_matrix.h | 4 ++-- subsys/input/input_utils.c | 2 +- tests/drivers/input/kbd_matrix/src/main.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/input/input_kbd_matrix.c b/drivers/input/input_kbd_matrix.c index 47d8cfc07e1..af7ce88a8d4 100644 --- a/drivers/input/input_kbd_matrix.c +++ b/drivers/input/input_kbd_matrix.c @@ -217,7 +217,7 @@ static bool input_kbd_matrix_check_key_events(const struct device *dev) key_pressed = input_kbd_matrix_scan(dev); for (int c = 0; c < cfg->col_size; c++) { - LOG_DBG("c=%2d u=" PRIkbdrow " p=" PRIkbdrow " n=" PRIkbdrow, + LOG_DBG("c=%2d u=%" PRIkbdrow " p=%" PRIkbdrow " n=%" PRIkbdrow, c, cfg->matrix_unstable_state[c], cfg->matrix_previous_state[c], diff --git a/include/zephyr/input/input_kbd_matrix.h b/include/zephyr/input/input_kbd_matrix.h index 7d3f4f37c43..6a458dcdf2a 100644 --- a/include/zephyr/input/input_kbd_matrix.h +++ b/include/zephyr/input/input_kbd_matrix.h @@ -32,10 +32,10 @@ /** Row entry data type */ #if CONFIG_INPUT_KBD_MATRIX_16_BIT_ROW typedef uint16_t kbd_row_t; -#define PRIkbdrow "%04x" +#define PRIkbdrow "04" PRIx16 #else typedef uint8_t kbd_row_t; -#define PRIkbdrow "%02x" +#define PRIkbdrow "02" PRIx8 #endif #if defined(CONFIG_INPUT_KBD_ACTUAL_KEY_MASK_DYNAMIC) || defined(__DOXYGEN__) diff --git a/subsys/input/input_utils.c b/subsys/input/input_utils.c index 32d26fc7211..45281b6d5d7 100644 --- a/subsys/input/input_utils.c +++ b/subsys/input/input_utils.c @@ -142,7 +142,7 @@ static void kbd_matrix_state_log_entry(char *header, kbd_row_t *data) char *sep = (i + 1) < cfg->col_size ? " " : ""; if (data[i] != 0) { - ret = snprintf(buf, size, PRIkbdrow "%s", data[i], sep); + ret = snprintf(buf, size, "%" PRIkbdrow "%s", data[i], sep); } else { ret = snprintf(buf, size, "%s%s", blank, sep); } diff --git a/tests/drivers/input/kbd_matrix/src/main.c b/tests/drivers/input/kbd_matrix/src/main.c index 0bb9112fc6f..bd09d4441fc 100644 --- a/tests/drivers/input/kbd_matrix/src/main.c +++ b/tests/drivers/input/kbd_matrix/src/main.c @@ -80,7 +80,7 @@ void input_kbd_matrix_drive_column_hook(const struct device *dev, int col) static void state_set_rows_by_column(kbd_row_t c0, kbd_row_t c1, kbd_row_t c2) { memcpy(&state.rows, (kbd_row_t[]){c0, c1, c2}, sizeof(state.rows)); - TC_PRINT("set state [" PRIkbdrow " " PRIkbdrow " " PRIkbdrow "]\n", c0, c1, c2); + TC_PRINT("set state [%" PRIkbdrow " %" PRIkbdrow " %" PRIkbdrow "]\n", c0, c1, c2); } static struct { From 5d2558bdade5109bb43d1e04c83d3c0ddd77ac9b Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Fri, 23 Feb 2024 14:56:16 +0100 Subject: [PATCH 0563/2402] drivers: adc: stm32: dma fixes Add a blank define for the case where DMA channels are defined in ADC node of the dts but STM32_ADC_DMA is not enabled. Otherwise compilation fails. Also fix the way the DMA channel is configured by using a standard DT macro, otherwise it doesn't work for dma-v2bis DMA types. Signed-off-by: Guillaume Gautier --- drivers/adc/adc_stm32.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index 010512fc533..b37c02d839c 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -1570,7 +1570,7 @@ static const struct adc_driver_api api_stm32_driver_api = { #define ADC_DMA_CHANNEL_INIT(index, src_dev, dest_dev) \ .dma = { \ .dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(index, 0)), \ - .channel = STM32_DMA_SLOT_BY_IDX(index, 0, channel), \ + .channel = DT_INST_DMAS_CELL_BY_IDX(index, 0, channel), \ .dma_cfg = { \ .dma_slot = STM32_DMA_SLOT_BY_IDX(index, 0, slot), \ .channel_direction = STM32_DMA_CONFIG_DIRECTION( \ @@ -1696,6 +1696,8 @@ DT_INST_FOREACH_STATUS_OKAY(GENERATE_ISR) .irq_cfg_func = COND_CODE_1(IS_EQ(index, FIRST_WITH_IRQN(index)), \ (UTIL_CAT(ISR_FUNC(index), _init)), (NULL)), +#define ADC_DMA_CHANNEL_INIT(index, src_dev, dest_dev) + #endif /* CONFIG_ADC_STM32_DMA */ #define ADC_DMA_CHANNEL(id, src, dest) \ From 7aa5d33a945b635c8d1199ec63b7bddb9d32a204 Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Fri, 23 Feb 2024 16:07:40 +0100 Subject: [PATCH 0564/2402] include: zephyr: drivers: dma: stm32: Fix macro Macro STM32_DMA_SLOT_BY_IDX should return 0 instead of nothing for dma v2bis. Signed-off-by: Guillaume Gautier --- include/zephyr/drivers/dma/dma_stm32.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/drivers/dma/dma_stm32.h b/include/zephyr/drivers/dma/dma_stm32.h index c4c593457cb..e9ca4598247 100644 --- a/include/zephyr/drivers/dma/dma_stm32.h +++ b/include/zephyr/drivers/dma/dma_stm32.h @@ -33,7 +33,7 @@ /* macro for dma slot (only for dma-v1 or dma-v2 types) */ #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v2bis) #define STM32_DMA_SLOT(id, dir, slot) 0 -#define STM32_DMA_SLOT_BY_IDX(id, idx, slot) +#define STM32_DMA_SLOT_BY_IDX(id, idx, slot) 0 #else #define STM32_DMA_SLOT(id, dir, slot) DT_INST_DMAS_CELL_BY_NAME(id, dir, slot) #define STM32_DMA_SLOT_BY_IDX(id, idx, slot) DT_INST_DMAS_CELL_BY_IDX(id, idx, slot) From 3b502376999b703aab9a9c225fba88f259e4552b Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Fri, 8 Mar 2024 08:49:57 +0100 Subject: [PATCH 0565/2402] drivers: adc: stm32: use correct macros for dma transfer Use the correct dedicated macros for enabling DMA transfer for STM32H7 and U5. Signed-off-by: Guillaume Gautier --- drivers/adc/adc_stm32.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index b37c02d839c..1ed8db1c54a 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -221,12 +221,9 @@ static void adc_stm32_enable_dma_support(ADC_TypeDef *adc) #if defined(ADC_VER_V5_V90) if (adc == ADC3) { - LL_ADC_REG_SetDMATransferMode(adc, - ADC3_CFGR_DMACONTREQ(LL_ADC_REG_DMA_TRANSFER_LIMITED)); - LL_ADC_EnableDMAReq(adc); + LL_ADC_REG_SetDMATransferMode(adc, LL_ADC3_REG_DMA_TRANSFER_LIMITED); } else { - LL_ADC_REG_SetDataTransferMode(adc, - ADC_CFGR_DMACONTREQ(LL_ADC_REG_DMA_TRANSFER_LIMITED)); + LL_ADC_REG_SetDataTransferMode(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED); } #elif defined(ADC_VER_V5_X) LL_ADC_REG_SetDataTransferMode(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED); @@ -238,7 +235,15 @@ static void adc_stm32_enable_dma_support(ADC_TypeDef *adc) #error "The STM32F1 ADC + DMA is not yet supported" -#else /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */ +#elif defined(CONFIG_SOC_SERIES_STM32U5X) /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */ + + if (adc == ADC4) { + LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED_ADC4); + } else { + LL_ADC_REG_SetDataTransferMode(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED); + } + +#else /* defined(CONFIG_SOC_SERIES_STM32U5X) */ /* Default mechanism for other MCUs */ LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED); From ddd2cf1fdc82210bd34bdca7af9e1926a1a2f73e Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Tue, 14 Nov 2023 11:05:12 +0000 Subject: [PATCH 0566/2402] input: convert kscan_mchp_xec.c driver to input Convert the XEC keyboard scanning driver from kscan to input, add the corresponding kscan compatibility node to the current board, build test only. Signed-off-by: Fabio Baltieri --- .../mec1501modular_assy6885/Kconfig.defconfig | 3 + .../mec1501modular_assy6885.dts | 10 +- .../mec15xxevb_assy6853/Kconfig.defconfig | 3 + .../mec15xxevb_assy6853.dts | 10 +- .../mec172xevb_assy6906/Kconfig.defconfig | 3 + .../mec172xevb_assy6906.dts | 6 +- .../mec172xmodular_assy6930/Kconfig.defconfig | 3 + .../mec172xmodular_assy6930.dts | 6 +- drivers/input/CMakeLists.txt | 1 + drivers/input/Kconfig | 1 + drivers/{kscan => input}/Kconfig.xec | 20 +- .../input_xec_kbd.c} | 220 +++++++----------- drivers/kscan/CMakeLists.txt | 1 - drivers/kscan/Kconfig | 1 - dts/arm/microchip/mec1501hsz.dtsi | 4 +- dts/arm/microchip/mec172x_common.dtsi | 4 +- .../microchip,xec-kbd.yaml} | 6 +- 17 files changed, 145 insertions(+), 157 deletions(-) rename drivers/{kscan => input}/Kconfig.xec (75%) rename drivers/{kscan/kscan_mchp_xec.c => input/input_xec_kbd.c} (72%) rename dts/bindings/{kscan/microchip,xec-kscan.yaml => input/microchip,xec-kbd.yaml} (87%) diff --git a/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig b/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig index 1f5c692b90f..0ca8a90ad48 100644 --- a/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig +++ b/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig @@ -3,6 +3,9 @@ if BOARD_MEC1501MODULAR_ASSY6885 +config INPUT + default y if KSCAN + #PS/2 driver is compiled in terms of this flag. config ESPI_PERIPHERAL_8042_KBC default y diff --git a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts index d59ff04a62f..5101b9d30cb 100644 --- a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts +++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts @@ -17,7 +17,7 @@ zephyr,sram = &sram0; zephyr,console = &uart1; zephyr,flash = &flash0; - zephyr,keyboard-scan = &kscan0; + zephyr,keyboard-scan = &kscan_input; }; aliases { @@ -26,7 +26,7 @@ i2c0 = &i2c_smb_0; i2c1 = &i2c_smb_1; - kscan0 = &kscan0; + kscan0 = &kscan_input; watchdog0 = &wdog; }; }; @@ -100,7 +100,7 @@ pinctrl-names = "default"; }; -&kscan0 { +&kbd0 { status = "okay"; pinctrl-0 = < &kso00_gpio040 &kso01_gpio045 &kso02_gpio046 &kso12_gpio125 @@ -118,6 +118,10 @@ &ksi2_gpio021_sleep &ksi3_gpio026_sleep &ksi4_gpio027_sleep &ksi5_gpio030_sleep &ksi6_gpio031_sleep &ksi7_gpio032_sleep >; pinctrl-names = "default", "sleep"; + + kscan_input: kscan-input { + compatible = "zephyr,kscan-input"; + }; }; &peci0 { diff --git a/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig b/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig index c4dae2ad32e..229ba41dff7 100644 --- a/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig +++ b/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig @@ -3,6 +3,9 @@ if BOARD_MEC15XXEVB_ASSY6853 +config INPUT + default y if KSCAN + config ESPI_XEC default y depends on ESPI diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts index fa577a53b7e..7402f6e7074 100644 --- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts +++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts @@ -16,7 +16,7 @@ zephyr,sram = &sram0; zephyr,console = &uart2; zephyr,flash = &flash0; - zephyr,keyboard-scan = &kscan0; + zephyr,keyboard-scan = &kscan_input; }; aliases { @@ -29,7 +29,7 @@ i2c-0 = &i2c_smb_0; i2c1 = &i2c_smb_1; i2c7 = &i2c_smb_2; - kscan0 = &kscan0; + kscan0 = &kscan_input; watchdog0 = &wdog; }; @@ -157,7 +157,7 @@ pinctrl-names = "default"; }; -&kscan0 { +&kbd0 { status = "okay"; pinctrl-0 = < &kso00_gpio040 &kso01_gpio045 &kso02_gpio046 &kso12_gpio125 @@ -175,6 +175,10 @@ &ksi2_gpio021_sleep &ksi3_gpio026_sleep &ksi4_gpio027_sleep &ksi5_gpio030_sleep &ksi6_gpio031_sleep &ksi7_gpio032_sleep >; pinctrl-names = "default", "sleep"; + + kscan_input: kscan-input { + compatible = "zephyr,kscan-input"; + }; }; &peci0 { diff --git a/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig b/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig index c31952ed766..2c93b83e744 100644 --- a/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig +++ b/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig @@ -3,6 +3,9 @@ if BOARD_MEC172XEVB_ASSY6906 +config INPUT + default y if KSCAN + if RTOS_TIMER # XEC RTOS timer HW frequency is fixed at 32768 Hz. diff --git a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts index 35966d882e0..9595fc578e6 100644 --- a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts +++ b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts @@ -213,7 +213,7 @@ pinctrl-names = "default"; }; -&kscan0 { +&kbd0 { status = "okay"; pinctrl-0 = < &ksi0_gpio017 &ksi1_gpio020 &ksi2_gpio021 &ksi3_gpio026 @@ -231,6 +231,10 @@ &kso10_gpio123_sleep &kso11_gpio124_sleep &kso12_gpio125_sleep &kso13_gpio126_sleep >; pinctrl-names = "default", "sleep"; + + kscan_input: kscan-input { + compatible = "zephyr,kscan-input"; + }; }; &ksi0_gpio017 { diff --git a/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig b/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig index c0ad2565043..c3487f561e9 100644 --- a/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig +++ b/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig @@ -3,6 +3,9 @@ if BOARD_MEC172XMODULAR_ASSY6930 +config INPUT + default y if KSCAN + if RTOS_TIMER # XEC RTOS timer HW frequency is fixed at 32768 Hz. diff --git a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts index d355f19afc3..dd7db055485 100644 --- a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts +++ b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts @@ -191,7 +191,7 @@ pinctrl-names = "default"; }; -&kscan0 { +&kbd0 { status = "okay"; pinctrl-0 = < &ksi0_gpio017 &ksi1_gpio020 &ksi2_gpio021 &ksi3_gpio026 @@ -209,6 +209,10 @@ &kso10_gpio123_sleep &kso11_gpio124_sleep &kso12_gpio125_sleep &kso13_gpio126_sleep >; pinctrl-names = "default", "sleep"; + + kscan_input: kscan-input { + compatible = "zephyr,kscan-input"; + }; }; &ksi0_gpio017 { diff --git a/drivers/input/CMakeLists.txt b/drivers/input/CMakeLists.txt index 490db67227b..d1f647cd0e9 100644 --- a/drivers/input/CMakeLists.txt +++ b/drivers/input/CMakeLists.txt @@ -21,6 +21,7 @@ zephyr_library_sources_ifdef(CONFIG_INPUT_NPCX_KBD input_npcx_kbd.c) zephyr_library_sources_ifdef(CONFIG_INPUT_PAT912X input_pat912x.c) zephyr_library_sources_ifdef(CONFIG_INPUT_PMW3610 input_pmw3610.c) zephyr_library_sources_ifdef(CONFIG_INPUT_STMPE811 input_stmpe811.c) +zephyr_library_sources_ifdef(CONFIG_INPUT_XEC_KBD input_xec_kbd.c) zephyr_library_sources_ifdef(CONFIG_INPUT_XPT2046 input_xpt2046.c) # zephyr-keep-sorted-stop diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index a71dded2212..8c68af65fb2 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -24,6 +24,7 @@ source "drivers/input/Kconfig.pat912x" source "drivers/input/Kconfig.pmw3610" source "drivers/input/Kconfig.sdl" source "drivers/input/Kconfig.stmpe811" +source "drivers/input/Kconfig.xec" source "drivers/input/Kconfig.xpt2046" # zephyr-keep-sorted-stop diff --git a/drivers/kscan/Kconfig.xec b/drivers/input/Kconfig.xec similarity index 75% rename from drivers/kscan/Kconfig.xec rename to drivers/input/Kconfig.xec index 10188e8c931..bd6cc73b9c9 100644 --- a/drivers/kscan/Kconfig.xec +++ b/drivers/input/Kconfig.xec @@ -3,47 +3,47 @@ # Copyright (c) 2019 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -menuconfig KSCAN_XEC - bool "Microchip XEC series KSCAN driver" +menuconfig INPUT_XEC_KBD + bool "Microchip XEC series keyboard matrix driver" default y - depends on DT_HAS_MICROCHIP_XEC_KSCAN_ENABLED + depends on DT_HAS_MICROCHIP_XEC_KBD_ENABLED select MULTITHREADING select PINCTRL help Enable the Microchip XEC Kscan IO driver. -if KSCAN_XEC +if INPUT_XEC_KBD -config KSCAN_XEC_COLUMN_SIZE +config INPUT_XEC_COLUMN_SIZE int "Keyscan XEC Column Size" default 16 help Adjust the value to your keyboard columns. The maximum column size for the Microchip XEC family is 18 (from 0 to 17). -config KSCAN_XEC_ROW_SIZE +config INPUT_XEC_ROW_SIZE int "Keyscan XEC Row Size" default 8 help Adjust the value to your keyboard rows. The maximum column size for the Microchip XEC family is 8 (from 0 to 7). -config KSCAN_XEC_DEBOUNCE_DOWN +config INPUT_XEC_DEBOUNCE_DOWN int "Keyscan XEC Debounce Down" default 10 help Determines the time in msecs for debouncing a key press. -config KSCAN_XEC_DEBOUNCE_UP +config INPUT_XEC_DEBOUNCE_UP int "Keyscan XEC Debounce Up" default 20 help Determines the time in msecs for debouncing a key release. -config KSCAN_XEC_POLL_PERIOD +config INPUT_XEC_POLL_PERIOD int "Keyscan XEC Poll Period" default 5 help Defines the poll period in msecs between between matrix scans. -endif # KSCAN_XEC +endif # INPUT_XEC diff --git a/drivers/kscan/kscan_mchp_xec.c b/drivers/input/input_xec_kbd.c similarity index 72% rename from drivers/kscan/kscan_mchp_xec.c rename to drivers/input/input_xec_kbd.c index e3e8fa4043e..d18b2407485 100644 --- a/drivers/kscan/kscan_mchp_xec.c +++ b/drivers/input/input_xec_kbd.c @@ -4,30 +4,28 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT microchip_xec_kscan +#define DT_DRV_COMPAT microchip_xec_kbd #include #include +#include #include -#ifdef CONFIG_SOC_SERIES_MEC172X -#include -#include -#endif -#include #include +#include +#include #include -#include -#include #include -#include #include #include +#ifdef CONFIG_SOC_SERIES_MEC172X +#include +#include +#endif -#define LOG_LEVEL CONFIG_KSCAN_LOG_LEVEL -LOG_MODULE_REGISTER(kscan_mchp_xec); +LOG_MODULE_REGISTER(input_xec_kbd, CONFIG_INPUT_LOG_LEVEL); -#define MAX_MATRIX_KEY_COLS CONFIG_KSCAN_XEC_COLUMN_SIZE -#define MAX_MATRIX_KEY_ROWS CONFIG_KSCAN_XEC_ROW_SIZE +#define MAX_MATRIX_KEY_COLS CONFIG_INPUT_XEC_COLUMN_SIZE +#define MAX_MATRIX_KEY_ROWS CONFIG_INPUT_XEC_ROW_SIZE #define KEYBOARD_COLUMN_DRIVE_ALL -2 #define KEYBOARD_COLUMN_DRIVE_NONE -1 @@ -42,7 +40,7 @@ LOG_MODULE_REGISTER(kscan_mchp_xec); /* Thread stack size */ #define TASK_STACK_SIZE 1024 -struct kscan_xec_config { +struct xec_kbd_config { struct kscan_regs *regs; const struct pinctrl_dev_config *pcfg; uint8_t rsvd[3]; @@ -54,7 +52,7 @@ struct kscan_xec_config { bool wakeup_source; }; -struct kscan_xec_data { +struct xec_kbd_data { /* variables in usec units */ uint32_t deb_time_press; uint32_t deb_time_rel; @@ -71,24 +69,22 @@ struct kscan_xec_data { uint8_t scan_clk_cycle[SCAN_OCURRENCES]; struct k_sem poll_lock; uint8_t scan_cycles_idx; - kscan_callback_t callback; struct k_thread thread; - atomic_t enable_scan; K_KERNEL_STACK_MEMBER(thread_stack, TASK_STACK_SIZE); }; #ifdef CONFIG_SOC_SERIES_MEC172X -static void kscan_clear_girq_status(const struct device *dev) +static void xec_kbd_clear_girq_status(const struct device *dev) { - struct kscan_xec_config const *cfg = dev->config; + struct xec_kbd_config const *cfg = dev->config; mchp_xec_ecia_girq_src_clr(cfg->girq, cfg->girq_pos); } -static void kscan_configure_girq(const struct device *dev, bool enable) +static void xec_kbd_configure_girq(const struct device *dev, bool enable) { - struct kscan_xec_config const *cfg = dev->config; + struct xec_kbd_config const *cfg = dev->config; if (enable) { mchp_xec_ecia_enable(cfg->girq, cfg->girq_pos); @@ -97,24 +93,24 @@ static void kscan_configure_girq(const struct device *dev, bool enable) } } -static void kscan_clr_slp_en(const struct device *dev) +static void xec_kbd_clr_slp_en(const struct device *dev) { - struct kscan_xec_config const *cfg = dev->config; + struct xec_kbd_config const *cfg = dev->config; z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0); } #else -static void kscan_clear_girq_status(const struct device *dev) +static void xec_kbd_clear_girq_status(const struct device *dev) { - struct kscan_xec_config const *cfg = dev->config; + struct xec_kbd_config const *cfg = dev->config; MCHP_GIRQ_SRC(cfg->girq) = BIT(cfg->girq_pos); } -static void kscan_configure_girq(const struct device *dev, bool enable) +static void xec_kbd_configure_girq(const struct device *dev, bool enable) { - struct kscan_xec_config const *cfg = dev->config; + struct xec_kbd_config const *cfg = dev->config; if (enable) { MCHP_GIRQ_ENSET(cfg->girq) = BIT(cfg->girq_pos); @@ -123,7 +119,7 @@ static void kscan_configure_girq(const struct device *dev, bool enable) } } -static void kscan_clr_slp_en(const struct device *dev) +static void xec_kbd_clr_slp_en(const struct device *dev) { ARG_UNUSED(dev); @@ -131,10 +127,9 @@ static void kscan_clr_slp_en(const struct device *dev) } #endif - static void drive_keyboard_column(const struct device *dev, int data) { - struct kscan_xec_config const *cfg = dev->config; + struct xec_kbd_config const *cfg = dev->config; struct kscan_regs *regs = cfg->regs; if (data == KEYBOARD_COLUMN_DRIVE_ALL) { @@ -153,7 +148,7 @@ static void drive_keyboard_column(const struct device *dev, int data) static uint8_t read_keyboard_row(const struct device *dev) { - struct kscan_xec_config const *cfg = dev->config; + struct xec_kbd_config const *cfg = dev->config; struct kscan_regs *regs = cfg->regs; /* In this implementation a 1 means key pressed */ @@ -221,17 +216,17 @@ static bool read_keyboard_matrix(const struct device *dev, uint8_t *new_state) static void scan_matrix_xec_isr(const struct device *dev) { - struct kscan_xec_data *const data = dev->data; + struct xec_kbd_data *const data = dev->data; - kscan_clear_girq_status(dev); + xec_kbd_clear_girq_status(dev); irq_disable(DT_INST_IRQN(0)); k_sem_give(&data->poll_lock); - LOG_DBG(" "); + LOG_DBG(""); } static bool check_key_events(const struct device *dev) { - struct kscan_xec_data *const data = dev->data; + struct xec_kbd_data *const data = dev->data; uint8_t matrix_new_state[MAX_MATRIX_KEY_COLS] = {0U}; bool key_pressed = false; uint32_t cycles_now = k_cycle_get_32(); @@ -322,10 +317,10 @@ static bool check_key_events(const struct device *dev) * application about the keys pressed. */ data->matrix_stable_state[c] ^= mask; - if (atomic_get(&data->enable_scan) == 1U) { - data->callback(dev, r, c, - row_bit ? true : false); - } + + input_report_abs(dev, INPUT_ABS_X, c, false, K_FOREVER); + input_report_abs(dev, INPUT_ABS_Y, r, false, K_FOREVER); + input_report_key(dev, INPUT_BTN_TOUCH, row_bit, true, K_FOREVER); } } @@ -351,8 +346,8 @@ static bool poll_expired(uint32_t start_cycles, int64_t *timeout) void polling_task(const struct device *dev, void *dummy2, void *dummy3) { - struct kscan_xec_config const *cfg = dev->config; - struct kscan_xec_data *const data = dev->data; + struct xec_kbd_config const *cfg = dev->config; + struct xec_kbd_data *const data = dev->data; struct kscan_regs *regs = cfg->regs; uint32_t current_cycles; uint32_t cycles_diff; @@ -366,7 +361,7 @@ void polling_task(const struct device *dev, void *dummy2, void *dummy3) regs->KSI_STS = MCHP_KSCAN_KSO_SEL_REG_MASK; /* Ignore isr when releasing a key as we are polling */ - kscan_clear_girq_status(dev); + xec_kbd_clear_girq_status(dev); NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); irq_enable(DT_INST_IRQN(0)); @@ -377,7 +372,7 @@ void polling_task(const struct device *dev, void *dummy2, void *dummy3) uint32_t start_poll_cycles = k_cycle_get_32(); - while (atomic_get(&data->enable_scan) == 1U) { + while (true) { uint32_t start_period_cycles = k_cycle_get_32(); if (check_key_events(DEVICE_DT_INST_GET(0))) { @@ -407,7 +402,7 @@ void polling_task(const struct device *dev, void *dummy2, void *dummy3) * whole poll period is used */ if (wait_period > data->poll_period) { - LOG_DBG("wait_period : %u", wait_period); + LOG_DBG("wait_period: %u", wait_period); wait_period = data->poll_period; } @@ -420,99 +415,63 @@ void polling_task(const struct device *dev, void *dummy2, void *dummy3) } } -static int kscan_xec_configure(const struct device *dev, - kscan_callback_t callback) -{ - struct kscan_xec_data *const data = dev->data; - - if (!callback) { - return -EINVAL; - } - - data->callback = callback; - - kscan_clear_girq_status(dev); - kscan_configure_girq(dev, 1); - - return 0; -} - -static int kscan_xec_inhibit_interface(const struct device *dev) -{ - struct kscan_xec_data *const data = dev->data; - - atomic_set(&data->enable_scan, 0); - - return 0; -} - -static int kscan_xec_enable_interface(const struct device *dev) -{ - struct kscan_xec_data *const data = dev->data; - - atomic_set(&data->enable_scan, 1); - - return 0; -} - #ifdef CONFIG_PM_DEVICE -static int kscan_xec_pm_action(const struct device *dev, enum pm_device_action action) +static int xec_kbd_pm_action(const struct device *dev, enum pm_device_action action) { - struct kscan_xec_config const *cfg = dev->config; + struct xec_kbd_config const *cfg = dev->config; struct kscan_regs *regs = cfg->regs; - int ret = 0; + int ret; + + if (cfg->wakeup_source) { + return 0; + } switch (action) { case PM_DEVICE_ACTION_RESUME: - if (!(cfg->wakeup_source)) { - ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); - if (ret != 0) { - LOG_ERR("XEC KSCAN pinctrl init failed (%d)", ret); - return ret; - } - regs->KSO_SEL &= ~BIT(MCHP_KSCAN_KSO_EN_POS); - /* Clea Status register */ - regs->KSI_STS = MCHP_KSCAN_KSO_SEL_REG_MASK; - regs->KSI_IEN = MCHP_KSCAN_KSI_IEN_REG_MASK; + ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); + if (ret != 0) { + LOG_ERR("XEC KSCAN pinctrl init failed (%d)", ret); + return ret; } - break; + + regs->KSO_SEL &= ~BIT(MCHP_KSCAN_KSO_EN_POS); + /* Clear status register */ + regs->KSI_STS = MCHP_KSCAN_KSO_SEL_REG_MASK; + regs->KSI_IEN = MCHP_KSCAN_KSI_IEN_REG_MASK; + break; + case PM_DEVICE_ACTION_SUSPEND: - if (!(cfg->wakeup_source)) { - regs->KSO_SEL |= BIT(MCHP_KSCAN_KSO_EN_POS); - regs->KSI_IEN = (~MCHP_KSCAN_KSI_IEN_REG_MASK); - ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP); - if (ret == -ENOENT) { /* pinctrl-1 does not exist. */ - ret = 0; - } + regs->KSO_SEL |= BIT(MCHP_KSCAN_KSO_EN_POS); + regs->KSI_IEN = (~MCHP_KSCAN_KSI_IEN_REG_MASK); + ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP); + if (ret != -ENOENT) { + /* pinctrl-1 does not exist */ + return ret; } - break; + break; + default: - ret = -ENOTSUP; + return -ENOTSUP; } - return ret; + + return 0; } #endif /* CONFIG_PM_DEVICE */ -static const struct kscan_driver_api kscan_xec_driver_api = { - .config = kscan_xec_configure, - .disable_callback = kscan_xec_inhibit_interface, - .enable_callback = kscan_xec_enable_interface, -}; - -static int kscan_xec_init(const struct device *dev) +static int xec_kbd_init(const struct device *dev) { - struct kscan_xec_config const *cfg = dev->config; - struct kscan_xec_data *const data = dev->data; + struct xec_kbd_config const *cfg = dev->config; + struct xec_kbd_data *const data = dev->data; struct kscan_regs *regs = cfg->regs; + int ret; - int ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); - + ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); if (ret != 0) { LOG_ERR("XEC KSCAN pinctrl init failed (%d)", ret); return ret; } - kscan_clr_slp_en(dev); + xec_kbd_clr_slp_en(dev); /* Enable predrive */ regs->KSO_SEL |= BIT(MCHP_KSCAN_KSO_EN_POS); @@ -522,15 +481,14 @@ static int kscan_xec_init(const struct device *dev) /* Time figures are transformed from msec to usec */ data->deb_time_press = (uint32_t) - (CONFIG_KSCAN_XEC_DEBOUNCE_DOWN * MSEC_PER_MS); + (CONFIG_INPUT_XEC_DEBOUNCE_DOWN * MSEC_PER_MS); data->deb_time_rel = (uint32_t) - (CONFIG_KSCAN_XEC_DEBOUNCE_UP * MSEC_PER_MS); + (CONFIG_INPUT_XEC_DEBOUNCE_UP * MSEC_PER_MS); data->poll_period = (uint32_t) - (CONFIG_KSCAN_XEC_POLL_PERIOD * MSEC_PER_MS); + (CONFIG_INPUT_XEC_POLL_PERIOD * MSEC_PER_MS); data->poll_timeout = 100 * MSEC_PER_MS; k_sem_init(&data->poll_lock, 0, 1); - atomic_set(&data->enable_scan, 1); k_thread_create(&data->thread, data->thread_stack, TASK_STACK_SIZE, @@ -542,20 +500,20 @@ static int kscan_xec_init(const struct device *dev) IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), scan_matrix_xec_isr, DEVICE_DT_INST_GET(0), 0); + xec_kbd_clear_girq_status(dev); + xec_kbd_configure_girq(dev, true); + return 0; } -static struct kscan_xec_data kbd_data; +static struct xec_kbd_data kbd_data; PINCTRL_DT_INST_DEFINE(0); -/* To enable wakeup on the KSCAN, the DTS needs to have entries defined - * in the KSCAN node in the DTS specifying it as a wake source; - * Example as below - * - * wakeup-source; +/* To enable wakeup, set the "wakeup-source" on the keyboard scanning device + * node. */ -static struct kscan_xec_config kscan_xec_cfg_0 = { +static struct xec_kbd_config xec_kbd_cfg_0 = { .regs = (struct kscan_regs *)(DT_INST_REG_ADDR(0)), .girq = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 0)), .girq_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 1)), @@ -565,9 +523,9 @@ static struct kscan_xec_config kscan_xec_cfg_0 = { .wakeup_source = DT_INST_PROP(0, wakeup_source) }; -PM_DEVICE_DT_INST_DEFINE(0, kscan_xec_pm_action); +PM_DEVICE_DT_INST_DEFINE(0, xec_kbd_pm_action); -DEVICE_DT_INST_DEFINE(0, kscan_xec_init, - PM_DEVICE_DT_INST_GET(0), &kbd_data, &kscan_xec_cfg_0, - POST_KERNEL, CONFIG_KSCAN_INIT_PRIORITY, - &kscan_xec_driver_api); +DEVICE_DT_INST_DEFINE(0, xec_kbd_init, + PM_DEVICE_DT_INST_GET(0), &kbd_data, &xec_kbd_cfg_0, + POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, + NULL); diff --git a/drivers/kscan/CMakeLists.txt b/drivers/kscan/CMakeLists.txt index 005c53ab4b7..5e846edcb36 100644 --- a/drivers/kscan/CMakeLists.txt +++ b/drivers/kscan/CMakeLists.txt @@ -4,7 +4,6 @@ zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/kscan.h) zephyr_library() -zephyr_library_sources_ifdef(CONFIG_KSCAN_XEC kscan_mchp_xec.c) zephyr_library_sources_ifdef(CONFIG_KSCAN_HT16K33 kscan_ht16k33.c) zephyr_library_sources_ifdef(CONFIG_KSCAN_INPUT kscan_input.c) diff --git a/drivers/kscan/Kconfig b/drivers/kscan/Kconfig index a2a786c31e3..de9b79255ea 100644 --- a/drivers/kscan/Kconfig +++ b/drivers/kscan/Kconfig @@ -10,7 +10,6 @@ menuconfig KSCAN if KSCAN -source "drivers/kscan/Kconfig.xec" source "drivers/kscan/Kconfig.ht16k33" source "drivers/kscan/Kconfig.input" diff --git a/dts/arm/microchip/mec1501hsz.dtsi b/dts/arm/microchip/mec1501hsz.dtsi index d2ffae50623..1c34f16c468 100644 --- a/dts/arm/microchip/mec1501hsz.dtsi +++ b/dts/arm/microchip/mec1501hsz.dtsi @@ -443,8 +443,8 @@ #io-channel-cells = <1>; clktime = <32>; }; - kscan0: kscan@40009c00 { - compatible = "microchip,xec-kscan"; + kbd0: kbd@40009c00 { + compatible = "microchip,xec-kbd"; reg = <0x40009c00 0x18>; interrupts = <135 0>; girqs = <21 25>; diff --git a/dts/arm/microchip/mec172x_common.dtsi b/dts/arm/microchip/mec172x_common.dtsi index 44c1f5190d3..a7bf2aa8f71 100644 --- a/dts/arm/microchip/mec172x_common.dtsi +++ b/dts/arm/microchip/mec172x_common.dtsi @@ -651,8 +651,8 @@ adc0: adc@40007c00 { #io-channel-cells = <1>; clktime = <32>; }; -kscan0: kscan@40009c00 { - compatible = "microchip,xec-kscan"; +kbd0: kbd@40009c00 { + compatible = "microchip,xec-kbd"; reg = <0x40009c00 0x18>; interrupts = <135 0>; girqs = <21 25>; diff --git a/dts/bindings/kscan/microchip,xec-kscan.yaml b/dts/bindings/input/microchip,xec-kbd.yaml similarity index 87% rename from dts/bindings/kscan/microchip,xec-kscan.yaml rename to dts/bindings/input/microchip,xec-kbd.yaml index 3639103e200..f5f2250ec6f 100644 --- a/dts/bindings/kscan/microchip,xec-kscan.yaml +++ b/dts/bindings/input/microchip,xec-kbd.yaml @@ -4,17 +4,19 @@ description: Microchip XEC keyboard matrix controller -compatible: "microchip,xec-kscan" +compatible: "microchip,xec-kbd" -include: [kscan.yaml, pinctrl-device.yaml] +include: [base.yaml, pinctrl-device.yaml] properties: "#address-cells": required: true const: 1 + "#size-cells": type: int const: 0 + reg: required: true From a63b3d1de6915f21db049fa180c4b0ba3757135b Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Mon, 20 Nov 2023 16:36:14 +0000 Subject: [PATCH 0567/2402] input: xec: use the generic keyboard code Split the common keyboard scanning code out of the XEC specific driver and use the generic code instead. Signed-off-by: Fabio Baltieri --- .../mec1501modular_assy6885.dts | 2 + .../mec15xxevb_assy6853.dts | 2 + .../mec172xevb_assy6906.dts | 2 + .../mec172xmodular_assy6930.dts | 2 + drivers/input/Kconfig.xec | 39 +- drivers/input/input_xec_kbd.c | 414 +++--------------- dts/bindings/input/microchip,xec-kbd.yaml | 8 +- 7 files changed, 83 insertions(+), 386 deletions(-) diff --git a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts index 5101b9d30cb..856069de406 100644 --- a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts +++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts @@ -118,6 +118,8 @@ &ksi2_gpio021_sleep &ksi3_gpio026_sleep &ksi4_gpio027_sleep &ksi5_gpio030_sleep &ksi6_gpio031_sleep &ksi7_gpio032_sleep >; pinctrl-names = "default", "sleep"; + row-size = <8>; + col-size = <16>; kscan_input: kscan-input { compatible = "zephyr,kscan-input"; diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts index 7402f6e7074..11daa0efbe3 100644 --- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts +++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts @@ -175,6 +175,8 @@ &ksi2_gpio021_sleep &ksi3_gpio026_sleep &ksi4_gpio027_sleep &ksi5_gpio030_sleep &ksi6_gpio031_sleep &ksi7_gpio032_sleep >; pinctrl-names = "default", "sleep"; + row-size = <8>; + col-size = <16>; kscan_input: kscan-input { compatible = "zephyr,kscan-input"; diff --git a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts index 9595fc578e6..c0427d03d3d 100644 --- a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts +++ b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts @@ -231,6 +231,8 @@ &kso10_gpio123_sleep &kso11_gpio124_sleep &kso12_gpio125_sleep &kso13_gpio126_sleep >; pinctrl-names = "default", "sleep"; + row-size = <8>; + col-size = <16>; kscan_input: kscan-input { compatible = "zephyr,kscan-input"; diff --git a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts index dd7db055485..94a08cd03f1 100644 --- a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts +++ b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts @@ -209,6 +209,8 @@ &kso10_gpio123_sleep &kso11_gpio124_sleep &kso12_gpio125_sleep &kso13_gpio126_sleep >; pinctrl-names = "default", "sleep"; + row-size = <8>; + col-size = <16>; kscan_input: kscan-input { compatible = "zephyr,kscan-input"; diff --git a/drivers/input/Kconfig.xec b/drivers/input/Kconfig.xec index bd6cc73b9c9..b93c47ac5f0 100644 --- a/drivers/input/Kconfig.xec +++ b/drivers/input/Kconfig.xec @@ -3,47 +3,12 @@ # Copyright (c) 2019 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -menuconfig INPUT_XEC_KBD +config INPUT_XEC_KBD bool "Microchip XEC series keyboard matrix driver" default y depends on DT_HAS_MICROCHIP_XEC_KBD_ENABLED + select INPUT_KBD_MATRIX select MULTITHREADING select PINCTRL help Enable the Microchip XEC Kscan IO driver. - -if INPUT_XEC_KBD - -config INPUT_XEC_COLUMN_SIZE - int "Keyscan XEC Column Size" - default 16 - help - Adjust the value to your keyboard columns. The maximum - column size for the Microchip XEC family is 18 (from 0 to 17). - -config INPUT_XEC_ROW_SIZE - int "Keyscan XEC Row Size" - default 8 - help - Adjust the value to your keyboard rows. The maximum - column size for the Microchip XEC family is 8 (from 0 to 7). - -config INPUT_XEC_DEBOUNCE_DOWN - int "Keyscan XEC Debounce Down" - default 10 - help - Determines the time in msecs for debouncing a key press. - -config INPUT_XEC_DEBOUNCE_UP - int "Keyscan XEC Debounce Up" - default 20 - help - Determines the time in msecs for debouncing a key release. - -config INPUT_XEC_POLL_PERIOD - int "Keyscan XEC Poll Period" - default 5 - help - Defines the poll period in msecs between between matrix scans. - -endif # INPUT_XEC diff --git a/drivers/input/input_xec_kbd.c b/drivers/input/input_xec_kbd.c index d18b2407485..660f902a44d 100644 --- a/drivers/input/input_xec_kbd.c +++ b/drivers/input/input_xec_kbd.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -24,394 +25,114 @@ LOG_MODULE_REGISTER(input_xec_kbd, CONFIG_INPUT_LOG_LEVEL); -#define MAX_MATRIX_KEY_COLS CONFIG_INPUT_XEC_COLUMN_SIZE -#define MAX_MATRIX_KEY_ROWS CONFIG_INPUT_XEC_ROW_SIZE - -#define KEYBOARD_COLUMN_DRIVE_ALL -2 -#define KEYBOARD_COLUMN_DRIVE_NONE -1 - -/* Poll period/debouncing rely on the 32KHz clock with 30 usec clock cycles */ -#define CLOCK_32K_HW_CYCLES_TO_US(X) \ - (uint32_t)((((uint64_t)(X) * 1000000U) / sys_clock_hw_cycles_per_sec())) -/* Milliseconds in microseconds */ -#define MSEC_PER_MS 1000U -/* Number of tracked scan times */ -#define SCAN_OCURRENCES 30U -/* Thread stack size */ -#define TASK_STACK_SIZE 1024 - struct xec_kbd_config { + struct input_kbd_matrix_common_config common; + struct kscan_regs *regs; const struct pinctrl_dev_config *pcfg; - uint8_t rsvd[3]; uint8_t girq; uint8_t girq_pos; - uint8_t irq_pri; +#ifdef CONFIG_SOC_SERIES_MEC172X uint8_t pcr_idx; uint8_t pcr_pos; +#endif bool wakeup_source; }; struct xec_kbd_data { - /* variables in usec units */ - uint32_t deb_time_press; - uint32_t deb_time_rel; - int64_t poll_timeout; - uint32_t poll_period; - uint8_t matrix_stable_state[MAX_MATRIX_KEY_COLS]; - uint8_t matrix_unstable_state[MAX_MATRIX_KEY_COLS]; - uint8_t matrix_previous_state[MAX_MATRIX_KEY_COLS]; - /* Index in to the scan_clock_cycle to indicate start of debouncing */ - uint8_t scan_cycle_idx[MAX_MATRIX_KEY_COLS][MAX_MATRIX_KEY_ROWS]; - /* Track previous "elapsed clock cycles" per matrix scan. This - * is used to calculate the debouncing time for every key - */ - uint8_t scan_clk_cycle[SCAN_OCURRENCES]; - struct k_sem poll_lock; - uint8_t scan_cycles_idx; - struct k_thread thread; - - K_KERNEL_STACK_MEMBER(thread_stack, TASK_STACK_SIZE); + struct input_kbd_matrix_common_data common; + bool pm_lock_taken; }; -#ifdef CONFIG_SOC_SERIES_MEC172X static void xec_kbd_clear_girq_status(const struct device *dev) { struct xec_kbd_config const *cfg = dev->config; +#ifdef CONFIG_SOC_SERIES_MEC172X mchp_xec_ecia_girq_src_clr(cfg->girq, cfg->girq_pos); +#else + MCHP_GIRQ_SRC(cfg->girq) = BIT(cfg->girq_pos); +#endif } -static void xec_kbd_configure_girq(const struct device *dev, bool enable) +static void xec_kbd_configure_girq(const struct device *dev) { struct xec_kbd_config const *cfg = dev->config; - if (enable) { - mchp_xec_ecia_enable(cfg->girq, cfg->girq_pos); - } else { - mchp_xec_ecia_disable(cfg->girq, cfg->girq_pos); - } +#ifdef CONFIG_SOC_SERIES_MEC172X + mchp_xec_ecia_enable(cfg->girq, cfg->girq_pos); +#else + MCHP_GIRQ_ENSET(cfg->girq) = BIT(cfg->girq_pos); +#endif } static void xec_kbd_clr_slp_en(const struct device *dev) { +#ifdef CONFIG_SOC_SERIES_MEC172X struct xec_kbd_config const *cfg = dev->config; z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0); -} - #else -static void xec_kbd_clear_girq_status(const struct device *dev) -{ - struct xec_kbd_config const *cfg = dev->config; - - MCHP_GIRQ_SRC(cfg->girq) = BIT(cfg->girq_pos); -} - -static void xec_kbd_configure_girq(const struct device *dev, bool enable) -{ - struct xec_kbd_config const *cfg = dev->config; - - if (enable) { - MCHP_GIRQ_ENSET(cfg->girq) = BIT(cfg->girq_pos); - } else { - MCHP_GIRQ_ENCLR(cfg->girq) = BIT(cfg->girq_pos); - } -} - -static void xec_kbd_clr_slp_en(const struct device *dev) -{ ARG_UNUSED(dev); - mchp_pcr_periph_slp_ctrl(PCR_KEYSCAN, 0); -} #endif +} -static void drive_keyboard_column(const struct device *dev, int data) +static void xec_kbd_drive_column(const struct device *dev, int data) { struct xec_kbd_config const *cfg = dev->config; struct kscan_regs *regs = cfg->regs; - if (data == KEYBOARD_COLUMN_DRIVE_ALL) { + if (data == INPUT_KBD_MATRIX_COLUMN_DRIVE_ALL) { /* KSO output controlled by the KSO_SELECT field */ regs->KSO_SEL = MCHP_KSCAN_KSO_ALL; - } else if (data == KEYBOARD_COLUMN_DRIVE_NONE) { + } else if (data == INPUT_KBD_MATRIX_COLUMN_DRIVE_NONE) { /* Keyboard scan disabled. All KSO output buffers disabled */ regs->KSO_SEL = MCHP_KSCAN_KSO_EN; } else { - /* It is assumed, KEYBOARD_COLUMN_DRIVE_ALL was - * previously set - */ + /* Assume, ALL was previously set */ regs->KSO_SEL = data; } } -static uint8_t read_keyboard_row(const struct device *dev) +static kbd_row_t xec_kbd_read_row(const struct device *dev) { struct xec_kbd_config const *cfg = dev->config; struct kscan_regs *regs = cfg->regs; /* In this implementation a 1 means key pressed */ - return ~(regs->KSI_IN & 0xFF); -} - -static bool is_matrix_ghosting(const uint8_t *state) -{ - /* matrix keyboard designs are susceptible to ghosting. - * An extra key appears to be pressed when 3 keys - * belonging to the same block are pressed. - * for example, in the following block - * - * . . w . q . - * . . . . . . - * . . . . . . - * . . m . a . - * - * the key m would look as pressed if the user pressed keys - * w, q and a simultaneously. A block can also be formed, - * with not adjacent columns. - */ - for (int c = 0; c < MAX_MATRIX_KEY_COLS; c++) { - if (!state[c]) - continue; - - for (int c_n = c + 1; c_n < MAX_MATRIX_KEY_COLS; c_n++) { - /* we and the columns to detect a "block". - * this is an indication of ghosting, due to current - * flowing from a key which was never pressed. in our - * case, current flowing is a bit set to 1 as we - * flipped the bits when the matrix was scanned. - * now we or the columns using z&(z-1) which is - * non-zero only if z has more than one bit set. - */ - uint8_t common_row_bits = state[c] & state[c_n]; - - if (common_row_bits & (common_row_bits - 1)) - return true; - } - } - - return false; -} - -static bool read_keyboard_matrix(const struct device *dev, uint8_t *new_state) -{ - uint8_t row; - uint8_t key_event = 0U; - - for (int col = 0; col < MAX_MATRIX_KEY_COLS; col++) { - drive_keyboard_column(dev, col); - - /* Allow the matrix to stabilize before reading it */ - k_busy_wait(50U); - row = read_keyboard_row(dev); - new_state[col] = row; - key_event |= row; - } - - drive_keyboard_column(dev, KEYBOARD_COLUMN_DRIVE_NONE); - - return key_event != 0U ? true : false; + return ~(regs->KSI_IN & 0xff); } -static void scan_matrix_xec_isr(const struct device *dev) +static void xec_kbd_isr(const struct device *dev) { - struct xec_kbd_data *const data = dev->data; - xec_kbd_clear_girq_status(dev); irq_disable(DT_INST_IRQN(0)); - k_sem_give(&data->poll_lock); - LOG_DBG(""); -} - -static bool check_key_events(const struct device *dev) -{ - struct xec_kbd_data *const data = dev->data; - uint8_t matrix_new_state[MAX_MATRIX_KEY_COLS] = {0U}; - bool key_pressed = false; - uint32_t cycles_now = k_cycle_get_32(); - - if (++data->scan_cycles_idx >= SCAN_OCURRENCES) { - data->scan_cycles_idx = 0U; - } - - data->scan_clk_cycle[data->scan_cycles_idx] = cycles_now; - - /* Scan the matrix */ - key_pressed = read_keyboard_matrix(dev, matrix_new_state); - - /* Abort if ghosting is detected */ - if (is_matrix_ghosting(matrix_new_state)) { - return false; - } - - uint8_t row_changed = 0U; - uint8_t deb_col; - - /* The intent of this loop is to gather information related to key - * changes. - */ - for (int c = 0; c < MAX_MATRIX_KEY_COLS; c++) { - /* Check if there was an update from the previous scan */ - row_changed = matrix_new_state[c] ^ - data->matrix_previous_state[c]; - if (!row_changed) { - continue; - } - - for (int r = 0; r < MAX_MATRIX_KEY_ROWS; r++) { - /* Index all they keys that changed for each row - * in order to debounce each key in terms of it - */ - if (row_changed & BIT(r)) { - data->scan_cycle_idx[c][r] = - data->scan_cycles_idx; - } - } - - data->matrix_unstable_state[c] |= row_changed; - data->matrix_previous_state[c] = matrix_new_state[c]; - } - - for (int c = 0; c < MAX_MATRIX_KEY_COLS; c++) { - deb_col = data->matrix_unstable_state[c]; - - if (!deb_col) { - continue; - } - - /* Debouncing for each row key occurs here */ - for (int r = 0; r < MAX_MATRIX_KEY_ROWS; r++) { - uint8_t mask = BIT(r); - uint8_t row_bit = matrix_new_state[c] & mask; - - /* Continue if we already debounce a key */ - if (!(deb_col & mask)) { - continue; - } - - /* Convert the clock cycle differences to usec */ - uint32_t debt = CLOCK_32K_HW_CYCLES_TO_US(cycles_now - - data->scan_clk_cycle[data->scan_cycle_idx[c][r]]); - - /* Does the key requires more time to be debounced? */ - if (debt < (row_bit ? data->deb_time_press : - data->deb_time_rel)) { - /* Need more time to debounce */ - continue; - } - - data->matrix_unstable_state[c] &= ~row_bit; - - /* Check if there was a change in the stable state */ - if ((data->matrix_stable_state[c] & mask) - == row_bit) { - /* Key state did not change */ - continue; - - } - - /* The current row has been debounced, therefore update - * the stable state. Then, proceed to notify the - * application about the keys pressed. - */ - data->matrix_stable_state[c] ^= mask; - - input_report_abs(dev, INPUT_ABS_X, c, false, K_FOREVER); - input_report_abs(dev, INPUT_ABS_Y, r, false, K_FOREVER); - input_report_key(dev, INPUT_BTN_TOUCH, row_bit, true, K_FOREVER); - } - } - - return key_pressed; + input_kbd_matrix_poll_start(dev); } -static bool poll_expired(uint32_t start_cycles, int64_t *timeout) -{ - uint32_t stop_cycles; - uint32_t cycles_spent; - uint32_t microsecs_spent; - - stop_cycles = k_cycle_get_32(); - cycles_spent = stop_cycles - start_cycles; - microsecs_spent = CLOCK_32K_HW_CYCLES_TO_US(cycles_spent); - - /* Update the timeout value */ - *timeout -= microsecs_spent; - - return *timeout >= 0; - -} - -void polling_task(const struct device *dev, void *dummy2, void *dummy3) +static void xec_kbd_set_detect_mode(const struct device *dev, bool enabled) { struct xec_kbd_config const *cfg = dev->config; - struct xec_kbd_data *const data = dev->data; + struct xec_kbd_data *data = dev->data; struct kscan_regs *regs = cfg->regs; - uint32_t current_cycles; - uint32_t cycles_diff; - uint32_t wait_period; - int64_t local_poll_timeout = data->poll_timeout; - ARG_UNUSED(dummy2); - ARG_UNUSED(dummy3); + if (enabled) { + if (data->pm_lock_taken) { + pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, + PM_ALL_SUBSTATES); + } - while (true) { regs->KSI_STS = MCHP_KSCAN_KSO_SEL_REG_MASK; - /* Ignore isr when releasing a key as we are polling */ xec_kbd_clear_girq_status(dev); NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); irq_enable(DT_INST_IRQN(0)); - - drive_keyboard_column(dev, KEYBOARD_COLUMN_DRIVE_ALL); - - k_sem_take(&data->poll_lock, K_FOREVER); - pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES); - - uint32_t start_poll_cycles = k_cycle_get_32(); - - while (true) { - uint32_t start_period_cycles = k_cycle_get_32(); - - if (check_key_events(DEVICE_DT_INST_GET(0))) { - local_poll_timeout = data->poll_timeout; - start_poll_cycles = k_cycle_get_32(); - } else if (!poll_expired(start_poll_cycles, - &local_poll_timeout)) { - break; - } - - /* Subtract the time invested from the sleep period - * in order to compensate for the time invested - * in debouncing a key - */ - current_cycles = k_cycle_get_32(); - cycles_diff = current_cycles - start_period_cycles; - wait_period = data->poll_period - - CLOCK_32K_HW_CYCLES_TO_US(cycles_diff); - - /* Override wait_period in case it is less than 1 ms */ - if (wait_period < MSEC_PER_MS) { - wait_period = MSEC_PER_MS; - } - - /* wait period results in a larger number when - * current cycles counter wrap. In this case, the - * whole poll period is used - */ - if (wait_period > data->poll_period) { - LOG_DBG("wait_period: %u", wait_period); - - wait_period = data->poll_period; - } - - /* Allow other threads to run while we sleep */ - k_usleep(wait_period); - } - - pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES); + } else { + pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, + PM_ALL_SUBSTATES); + data->pm_lock_taken = true; } } @@ -461,7 +182,6 @@ static int xec_kbd_pm_action(const struct device *dev, enum pm_device_action act static int xec_kbd_init(const struct device *dev) { struct xec_kbd_config const *cfg = dev->config; - struct xec_kbd_data *const data = dev->data; struct kscan_regs *regs = cfg->regs; int ret; @@ -479,53 +199,51 @@ static int xec_kbd_init(const struct device *dev) regs->KSO_SEL &= ~BIT(MCHP_KSCAN_KSO_EN_POS); regs->KSI_IEN = MCHP_KSCAN_KSI_IEN_REG_MASK; - /* Time figures are transformed from msec to usec */ - data->deb_time_press = (uint32_t) - (CONFIG_INPUT_XEC_DEBOUNCE_DOWN * MSEC_PER_MS); - data->deb_time_rel = (uint32_t) - (CONFIG_INPUT_XEC_DEBOUNCE_UP * MSEC_PER_MS); - data->poll_period = (uint32_t) - (CONFIG_INPUT_XEC_POLL_PERIOD * MSEC_PER_MS); - data->poll_timeout = 100 * MSEC_PER_MS; - - k_sem_init(&data->poll_lock, 0, 1); - - k_thread_create(&data->thread, data->thread_stack, - TASK_STACK_SIZE, - (void (*)(void *, void *, void *))polling_task, - (void *)dev, NULL, NULL, - K_PRIO_COOP(4), 0, K_NO_WAIT); - /* Interrupts are enabled in the thread function */ IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), - scan_matrix_xec_isr, DEVICE_DT_INST_GET(0), 0); + xec_kbd_isr, DEVICE_DT_INST_GET(0), 0); xec_kbd_clear_girq_status(dev); - xec_kbd_configure_girq(dev, true); + xec_kbd_configure_girq(dev); - return 0; + return input_kbd_matrix_common_init(dev); } -static struct xec_kbd_data kbd_data; - PINCTRL_DT_INST_DEFINE(0); +PM_DEVICE_DT_INST_DEFINE(0, xec_kbd_pm_action); + +INPUT_KBD_MATRIX_DT_INST_DEFINE(0); + +static const struct input_kbd_matrix_api xec_kbd_api = { + .drive_column = xec_kbd_drive_column, + .read_row = xec_kbd_read_row, + .set_detect_mode = xec_kbd_set_detect_mode, +}; + /* To enable wakeup, set the "wakeup-source" on the keyboard scanning device * node. */ static struct xec_kbd_config xec_kbd_cfg_0 = { + .common = INPUT_KBD_MATRIX_DT_INST_COMMON_CONFIG_INIT(0, &xec_kbd_api), .regs = (struct kscan_regs *)(DT_INST_REG_ADDR(0)), - .girq = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 0)), - .girq_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 1)), - .pcr_idx = (uint8_t)(DT_INST_PROP_BY_IDX(0, pcrs, 0)), - .pcr_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, pcrs, 1)), + .girq = DT_INST_PROP_BY_IDX(0, girqs, 0), + .girq_pos = DT_INST_PROP_BY_IDX(0, girqs, 1), +#ifdef CONFIG_SOC_SERIES_MEC172X + .pcr_idx = DT_INST_PROP_BY_IDX(0, pcrs, 0), + .pcr_pos = DT_INST_PROP_BY_IDX(0, pcrs, 1), +#endif .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), .wakeup_source = DT_INST_PROP(0, wakeup_source) }; -PM_DEVICE_DT_INST_DEFINE(0, xec_kbd_pm_action); +static struct xec_kbd_data kbd_data_0; DEVICE_DT_INST_DEFINE(0, xec_kbd_init, - PM_DEVICE_DT_INST_GET(0), &kbd_data, &xec_kbd_cfg_0, - POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, - NULL); + PM_DEVICE_DT_INST_GET(0), &kbd_data_0, &xec_kbd_cfg_0, + POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL); + +BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, + "only one microchip,xec-kbd compatible node can be supported"); +BUILD_ASSERT(IN_RANGE(DT_INST_PROP(0, row_size), 1, 8), "invalid row-size"); +BUILD_ASSERT(IN_RANGE(DT_INST_PROP(0, col_size), 1, 18), "invalid col-size"); diff --git a/dts/bindings/input/microchip,xec-kbd.yaml b/dts/bindings/input/microchip,xec-kbd.yaml index f5f2250ec6f..2c28c49ec4d 100644 --- a/dts/bindings/input/microchip,xec-kbd.yaml +++ b/dts/bindings/input/microchip,xec-kbd.yaml @@ -6,7 +6,7 @@ description: Microchip XEC keyboard matrix controller compatible: "microchip,xec-kbd" -include: [base.yaml, pinctrl-device.yaml] +include: [kbd-matrix-common.yaml, pinctrl-device.yaml] properties: "#address-cells": @@ -32,3 +32,9 @@ properties: type: array required: true description: ADC PCR register index and bit position + + row-size: + required: true + + col-size: + required: true From 1f5f0cf838aa1e0b5dc303fcb9e96fd9fce70704 Mon Sep 17 00:00:00 2001 From: TaiJu Wu Date: Thu, 7 Mar 2024 03:44:22 +0800 Subject: [PATCH 0568/2402] sched: Remove multi-level queue priority limit Modified bitmask to bitmask array, it can make multilevel queue remove 32 bit prioriry limit. We can scan bitmask array to find which queue have ready thread. Only need the number of queues as priority because the priority is checked on create_thread. Signed-off-by: TaiJu Wu --- doc/kernel/services/scheduling/index.rst | 2 +- include/zephyr/kernel_structs.h | 17 +++++++++-- kernel/Kconfig | 23 +++++++------- kernel/include/priority_q.h | 39 ++++++++++++++++++------ kernel/priority_queues.c | 26 +++++++++++----- 5 files changed, 75 insertions(+), 32 deletions(-) diff --git a/doc/kernel/services/scheduling/index.rst b/doc/kernel/services/scheduling/index.rst index 38837619a1f..87823ad40bf 100644 --- a/doc/kernel/services/scheduling/index.rst +++ b/doc/kernel/services/scheduling/index.rst @@ -82,7 +82,7 @@ runtime overhead and performance scaling when many threads are added. * Traditional multi-queue ready queue (:kconfig:option:`CONFIG_SCHED_MULTIQ`) When selected, the scheduler ready queue will be implemented as the - classic/textbook array of lists, one per priority (max 32 priorities). + classic/textbook array of lists, one per priority. This corresponds to the scheduler algorithm used in Zephyr versions prior to 1.12. diff --git a/include/zephyr/kernel_structs.h b/include/zephyr/kernel_structs.h index 093fcd0a188..ff8bde4e571 100644 --- a/include/zephyr/kernel_structs.h +++ b/include/zephyr/kernel_structs.h @@ -32,6 +32,15 @@ #include #endif +#define K_NUM_THREAD_PRIO (CONFIG_NUM_PREEMPT_PRIORITIES + CONFIG_NUM_COOP_PRIORITIES + 1) + +#if defined(CONFIG_64BIT) +#define PRIQ_BITMAP_SIZE (DIV_ROUND_UP(K_NUM_THREAD_PRIO, 8 * sizeof(uint64_t))) +#else +#define PRIQ_BITMAP_SIZE (DIV_ROUND_UP(K_NUM_THREAD_PRIO, 8 * sizeof(uint32_t))) +#endif + + #ifdef __cplusplus extern "C" { #endif @@ -117,8 +126,12 @@ struct _priq_rb { * to represent their requirements. */ struct _priq_mq { - sys_dlist_t queues[32]; - unsigned int bitmask; /* bit 1< 31 -# error Too many priorities for multiqueue scheduler (max 32) -# endif + +struct prio_info { + uint8_t offset_prio; + uint8_t idx; + uint8_t bit; +}; + +static ALWAYS_INLINE struct prio_info get_prio_info(int8_t old_prio) +{ + struct prio_info ret; + + ret.offset_prio = old_prio - K_HIGHEST_THREAD_PRIO; + ret.idx = ret.offset_prio / NBITS; + ret.bit = ret.offset_prio % NBITS; + + return ret; +} static ALWAYS_INLINE void z_priq_mq_add(struct _priq_mq *pq, struct k_thread *thread) { - int priority_bit = thread->base.prio - K_HIGHEST_THREAD_PRIO; + struct prio_info pos = get_prio_info(thread->base.prio); - sys_dlist_append(&pq->queues[priority_bit], &thread->base.qnode_dlist); - pq->bitmask |= BIT(priority_bit); + sys_dlist_append(&pq->queues[pos.offset_prio], &thread->base.qnode_dlist); + pq->bitmask[pos.idx] |= BIT(pos.bit); } static ALWAYS_INLINE void z_priq_mq_remove(struct _priq_mq *pq, struct k_thread *thread) { - int priority_bit = thread->base.prio - K_HIGHEST_THREAD_PRIO; + struct prio_info pos = get_prio_info(thread->base.prio); sys_dlist_remove(&thread->base.qnode_dlist); - if (sys_dlist_is_empty(&pq->queues[priority_bit])) { - pq->bitmask &= ~BIT(priority_bit); + if (sys_dlist_is_empty(&pq->queues[pos.offset_prio])) { + pq->bitmask[pos.idx] &= ~BIT(pos.bit); } } #endif /* CONFIG_SCHED_MULTIQ */ diff --git a/kernel/priority_queues.c b/kernel/priority_queues.c index 5de9cdccf84..692abfa7c6c 100644 --- a/kernel/priority_queues.c +++ b/kernel/priority_queues.c @@ -6,6 +6,7 @@ #include #include +#include void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread) { @@ -94,16 +95,25 @@ struct k_thread *z_priq_rb_best(struct _priq_rb *pq) struct k_thread *z_priq_mq_best(struct _priq_mq *pq) { - if (!pq->bitmask) { - return NULL; - } - struct k_thread *thread = NULL; - sys_dlist_t *l = &pq->queues[__builtin_ctz(pq->bitmask)]; - sys_dnode_t *n = sys_dlist_peek_head(l); - if (n != NULL) { - thread = CONTAINER_OF(n, struct k_thread, base.qnode_dlist); + for (int i = 0; i < PRIQ_BITMAP_SIZE; ++i) { + if (!pq->bitmask[i]) { + continue; + } + +#ifdef CONFIG_64BIT + sys_dlist_t *l = &pq->queues[i * 64 + u64_count_trailing_zeros(pq->bitmask[i])]; +#else + sys_dlist_t *l = &pq->queues[i * 32 + u32_count_trailing_zeros(pq->bitmask[i])]; +#endif + sys_dnode_t *n = sys_dlist_peek_head(l); + + if (n != NULL) { + thread = CONTAINER_OF(n, struct k_thread, base.qnode_dlist); + break; + } } + return thread; } From be9a85bf6c5e2d639e5d9d992a5a0cb45b2274cc Mon Sep 17 00:00:00 2001 From: TaiJu Wu Date: Tue, 12 Mar 2024 19:07:40 +0000 Subject: [PATCH 0569/2402] test: Remove multi level queue limit test Set total priorities to 71. This setting already exceeds original limit(32) and exceeds 64 to test secondary bitmap. Signed-off-by: TaiJu Wu --- tests/kernel/sched/schedule_api/prj_multiq.conf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/kernel/sched/schedule_api/prj_multiq.conf b/tests/kernel/sched/schedule_api/prj_multiq.conf index 18d04dd8656..6b28a1f39b2 100644 --- a/tests/kernel/sched/schedule_api/prj_multiq.conf +++ b/tests/kernel/sched/schedule_api/prj_multiq.conf @@ -5,3 +5,5 @@ CONFIG_SCHED_MULTIQ=y CONFIG_MAX_THREAD_BYTES=5 CONFIG_MP_MAX_NUM_CPUS=1 CONFIG_ZTEST_FATAL_HOOK=y +CONFIG_NUM_COOP_PRIORITIES=30 +CONFIG_NUM_PREEMPT_PRIORITIES=40 From ba46cd006c682c6b5214061af12a67666198f85d Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Tue, 12 Mar 2024 01:03:12 +0900 Subject: [PATCH 0570/2402] dts: bindings: gpio: arduino-mkr-header: Correct wrong D9/SCK pin number D9/SCK pin is #9 pin, not #0. Signed-off-by: TOKITA Hiroshi --- dts/bindings/gpio/arduino-mkr-header.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/bindings/gpio/arduino-mkr-header.yaml b/dts/bindings/gpio/arduino-mkr-header.yaml index 67e736069ec..2b3c15bbe8f 100644 --- a/dts/bindings/gpio/arduino-mkr-header.yaml +++ b/dts/bindings/gpio/arduino-mkr-header.yaml @@ -28,7 +28,7 @@ description: | 21 A6/D21 D12/SCL 12 0 D0 D11/SDA 11 1 D1 D10/CPIO 10 - 2 D2 D9/SCK 0 + 2 D2 D9/SCK 9 3 D3 D8/COPI 8 4 D4 D7 7 5 D5 D6 6 From 811a74c0199f84e5aa7478c2c7e9ba9073aa4466 Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Mon, 11 Mar 2024 00:08:38 +0000 Subject: [PATCH 0571/2402] boards/Kconfig: $BOARD_REVISION -> $(BOARD_REVISION) Add parentheses missing around $BOARD_REVISION. The syntax without parentheses has been deprecated for at least 5 years: https://github.com/ulfalizer/Kconfiglib/commit/374f48873424f9 That same documentation states "Using the old syntax with an undefined environment variable keeps the string as is." This what actually happens on Windows where `build/zephyr/.config` looks like this: CONFIG_BOARD_REVISION="$BOARD_REVISION" I found this because the behavior differs on Linux where the same, "old" syntax produces this instead: CONFIG_BOARD_REVISION="" This could be because environment variables work differently? (BOARD_REVISION is passed from kconfig.cmake to kconfiglib.py thanks to cmake -E env) Let's not try to debug this and just drop the deprecated syntax. It aligns both Windows and Linux on the same, expected, empty string behavior. Note these are the only two `def_string` found across all Kconfig files right now. Fixes commit c11b7852d15c ("Kconfig: add CONFIG_BOARD_REVISION") Fixes commit e2ff2a88ba76 ("sysbuild: include HWMv2 Kconfig in sysbuild") Signed-off-by: Marc Herbert --- boards/Kconfig | 2 +- share/sysbuild/Kconfig.v2 | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/Kconfig b/boards/Kconfig index 9268b7c0c9d..45ca2f84d6f 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -12,7 +12,7 @@ config BOARD soc/// config BOARD_REVISION - def_string "$BOARD_REVISION" + def_string "$(BOARD_REVISION)" help If the BOARD has a revision field set, this is the revision. Otherwise, it is the empty string. For example, if BOARD is diff --git a/share/sysbuild/Kconfig.v2 b/share/sysbuild/Kconfig.v2 index aa3a656e13f..c8261b08616 100644 --- a/share/sysbuild/Kconfig.v2 +++ b/share/sysbuild/Kconfig.v2 @@ -13,7 +13,7 @@ config BOARD soc/// config BOARD_REVISION - def_string "$BOARD_REVISION" + def_string "$(BOARD_REVISION)" help If the BOARD has a revision field set, this is the revision. Otherwise, it is the empty string. For example, if BOARD is From 233b2e1100904320218eea4ac37c5f4398ceb491 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 4 Apr 2023 23:57:58 +0000 Subject: [PATCH 0572/2402] twister: handler: update missing status of failed tests Some tests report no status even without timeout, so address this case as well. Signed-off-by: Anas Nashif --- scripts/pylib/twister/twisterlib/handlers.py | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py index 525d8f30ec0..5ffba005539 100755 --- a/scripts/pylib/twister/twisterlib/handlers.py +++ b/scripts/pylib/twister/twisterlib/handlers.py @@ -536,6 +536,7 @@ def _update_instance_info(self, harness_state, handler_time, flash_error): self.instance.status = harness_state if harness_state == "failed": self.instance.reason = "Failed" + self.instance.add_missing_case_status("blocked", harness_state) elif not flash_error: self.instance.status = "failed" self.instance.reason = "Timeout" From 6eb3c2e4c1fc97b8474eb61c79946d547f607c7b Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Wed, 5 Apr 2023 11:03:35 +0000 Subject: [PATCH 0573/2402] twister: harness: match exact charachters when we detect tests Avoid detecting garbage. Signed-off-by: Anas Nashif --- scripts/pylib/twister/twisterlib/harness.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/pylib/twister/twisterlib/harness.py b/scripts/pylib/twister/twisterlib/harness.py index ce7d0167dd4..2158430dd5e 100644 --- a/scripts/pylib/twister/twisterlib/harness.py +++ b/scripts/pylib/twister/twisterlib/harness.py @@ -608,7 +608,7 @@ class Test(Harness): RUN_PASSED = "PROJECT EXECUTION SUCCESSFUL" RUN_FAILED = "PROJECT EXECUTION FAILED" test_suite_start_pattern = r"Running TESTSUITE (?P.*)" - ZTEST_START_PATTERN = r"START - (test_)?(.*)" + ZTEST_START_PATTERN = r"START - (test_)?([a-zA-Z0-9_-]+)" def handle(self, line): test_suite_match = re.search(self.test_suite_start_pattern, line) From dbc3246723f231ed288e2721506b9c058a129ca4 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 11 Mar 2024 13:17:18 -0400 Subject: [PATCH 0574/2402] tests: twister: use assert_called_with for multiple calls Do not use assert_called_once_with, we can some functions more than once and test should not prevent that. Signed-off-by: Anas Nashif --- scripts/tests/twister/test_handlers.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/scripts/tests/twister/test_handlers.py b/scripts/tests/twister/test_handlers.py index d2e4b367a79..219d90a89d6 100644 --- a/scripts/tests/twister/test_handlers.py +++ b/scripts/tests/twister/test_handlers.py @@ -1125,13 +1125,13 @@ def test_devicehandler_create_command( ids=['success', 'failed', 'error', 'flash error', 'no status'] ) def test_devicehandler_update_instance_info( - mocked_instance, - harness_state, - flash_error, - expected_status, - expected_reason, - do_add_missing -): + mocked_instance, + harness_state, + flash_error, + expected_status, + expected_reason, + do_add_missing + ): handler = DeviceHandler(mocked_instance, 'build') handler_time = 59 missing_mock = mock.Mock() @@ -1145,7 +1145,7 @@ def test_devicehandler_update_instance_info( assert handler.instance.reason == expected_reason if do_add_missing: - missing_mock.assert_called_once_with('blocked', expected_reason) + missing_mock.assert_called_with('blocked', expected_reason) TESTDATA_15 = [ From 35176b993d4e06cc840b8dff61c905ba8437de50 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 15 Jan 2024 14:14:41 -0500 Subject: [PATCH 0575/2402] twister: fix exception message 'Handling of handler...' is a bit weird to read. Signed-off-by: Anas Nashif --- scripts/pylib/twister/twisterlib/harness.py | 2 +- scripts/tests/twister/test_harness.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/harness.py b/scripts/pylib/twister/twisterlib/harness.py index 2158430dd5e..0c45e43573e 100644 --- a/scripts/pylib/twister/twisterlib/harness.py +++ b/scripts/pylib/twister/twisterlib/harness.py @@ -348,7 +348,7 @@ def generate_command(self): elif handler.type_str == 'build': command.append('--device-type=custom') else: - raise PytestHarnessException(f'Handling of handler {handler.type_str} not implemented yet') + raise PytestHarnessException(f'Support for handler {handler.type_str} not implemented yet') if handler.options.pytest_args: command.extend(handler.options.pytest_args) diff --git a/scripts/tests/twister/test_harness.py b/scripts/tests/twister/test_harness.py index f117a77e3f5..cdf82439fba 100644 --- a/scripts/tests/twister/test_harness.py +++ b/scripts/tests/twister/test_harness.py @@ -355,7 +355,7 @@ def test_pytest_run(caplog): # Arrange timeout = 10 cmd=['command'] - exp_out = 'Handling of handler handler_type not implemented yet' + exp_out = 'Support for handler handler_type not implemented yet' harness = Pytest() harness = mock.create_autospec(harness) From 031cdfa23f8de33f988696d9e66b31dcd9d31a96 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 12 Mar 2024 15:18:27 +0100 Subject: [PATCH 0576/2402] soc: arm: stm32 with USB Type-C dead battery disabled if needed Check the driver configuration to disable the USB Type-C dead battery, only if - a USB PD system is in place (the UCPD node is enabled) - or the user does not require USB PHY anyway Signed-off-by: Francois Ramu --- soc/st/stm32/stm32g4x/soc.c | 10 +++++++--- soc/st/stm32/stm32h5x/soc.c | 9 ++++++--- soc/st/stm32/stm32l5x/soc.c | 7 +++++-- soc/st/stm32/stm32u5x/soc.c | 7 +++++-- 4 files changed, 23 insertions(+), 10 deletions(-) diff --git a/soc/st/stm32/stm32g4x/soc.c b/soc/st/stm32/stm32g4x/soc.c index c8d41f474f9..c52d93232c3 100644 --- a/soc/st/stm32/stm32g4x/soc.c +++ b/soc/st/stm32/stm32g4x/soc.c @@ -38,9 +38,13 @@ static int stm32g4_init(void) LL_DBGMCU_EnableDBGSleepMode(); #if defined(PWR_CR3_UCPD_DBDIS) - /* Disable USB Type-C dead battery pull-down behavior */ - LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); - LL_PWR_DisableUCPDDeadBattery(); + if (IS_ENABLED(CONFIG_DT_HAS_ST_STM32_UCPD_ENABLED) || + !IS_ENABLED(CONFIG_USB_DEVICE_DRIVER)) { + /* Disable USB Type-C dead battery pull-down behavior */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); + LL_PWR_DisableUCPDDeadBattery(); + } + #endif /* PWR_CR3_UCPD_DBDIS */ return 0; } diff --git a/soc/st/stm32/stm32h5x/soc.c b/soc/st/stm32/stm32h5x/soc.c index 206e4deae23..13b25257ed3 100644 --- a/soc/st/stm32/stm32h5x/soc.c +++ b/soc/st/stm32/stm32h5x/soc.c @@ -40,10 +40,13 @@ static int stm32h5_init(void) SystemCoreClock = 32000000; #if defined(PWR_UCPDR_UCPD_DBDIS) - /* Disable USB Type-C dead battery pull-down behavior */ - LL_PWR_DisableUCPDDeadBattery(); -#endif /* PWR_UCPDR_UCPD_DBDIS */ + if (IS_ENABLED(CONFIG_DT_HAS_ST_STM32_UCPD_ENABLED) || + !IS_ENABLED(CONFIG_USB_DEVICE_DRIVER)) { + /* Disable USB Type-C dead battery pull-down behavior */ + LL_PWR_DisableUCPDDeadBattery(); + } +#endif /* PWR_UCPDR_UCPD_DBDIS */ return 0; } diff --git a/soc/st/stm32/stm32l5x/soc.c b/soc/st/stm32/stm32l5x/soc.c index 349868e2eda..a932db07f5d 100644 --- a/soc/st/stm32/stm32l5x/soc.c +++ b/soc/st/stm32/stm32l5x/soc.c @@ -44,8 +44,11 @@ static int stm32l5_init(void) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0); - /* Disable USB Type-C dead battery pull-down behavior */ - LL_PWR_DisableUCPDDeadBattery(); + if (IS_ENABLED(CONFIG_DT_HAS_ST_STM32_UCPD_ENABLED) || + !IS_ENABLED(CONFIG_USB_DEVICE_DRIVER)) { + /* Disable USB Type-C dead battery pull-down behavior */ + LL_PWR_DisableUCPDDeadBattery(); + } return 0; } diff --git a/soc/st/stm32/stm32u5x/soc.c b/soc/st/stm32/stm32u5x/soc.c index d25fec9c680..86a296b68f3 100644 --- a/soc/st/stm32/stm32u5x/soc.c +++ b/soc/st/stm32/stm32u5x/soc.c @@ -42,8 +42,11 @@ static int stm32u5_init(void) /* Enable PWR */ LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR); - /* Disable USB Type-C dead battery pull-down behavior */ - LL_PWR_DisableUCPDDeadBattery(); + if (IS_ENABLED(CONFIG_DT_HAS_ST_STM32_UCPD_ENABLED) || + !IS_ENABLED(CONFIG_USB_DEVICE_DRIVER)) { + /* Disable USB Type-C dead battery pull-down behavior */ + LL_PWR_DisableUCPDDeadBattery(); + } /* Power Configuration */ #if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS) From c63ad6c915fa2d4458a4924c61f650e611321235 Mon Sep 17 00:00:00 2001 From: Kamil Paszkiet Date: Wed, 6 Mar 2024 14:36:39 +0100 Subject: [PATCH 0577/2402] scripts: tests: Blackbox test expansion - coverage Adds tests related to coverage flags: --coverage-tool --coverage-basedir --coverage-formats Move to coverage.py: --coverage --enable-coverage Signed-off-by: Kamil Paszkiet --- .../tests/twister_blackbox/test_coverage.py | 300 ++++++++++++++++++ scripts/tests/twister_blackbox/test_report.py | 74 ----- 2 files changed, 300 insertions(+), 74 deletions(-) create mode 100644 scripts/tests/twister_blackbox/test_coverage.py diff --git a/scripts/tests/twister_blackbox/test_coverage.py b/scripts/tests/twister_blackbox/test_coverage.py new file mode 100644 index 00000000000..798f812e599 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_coverage.py @@ -0,0 +1,300 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions +""" +import importlib +import re +import mock +import os +import pytest +import sys +import json + +from conftest import TEST_DATA, ZEPHYR_BASE, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +class TestCoverage: + TESTDATA_1 = [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), + ['qemu_x86'], + [ + 'coverage.log', 'coverage.json', + 'coverage' + ], + ), + ] + TESTDATA_2 = [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), + ['qemu_x86'], + [ + 'GCOV_COVERAGE_DUMP_START', 'GCOV_COVERAGE_DUMP_END' + ], + ), + ] + TESTDATA_3 = [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2'), + ['qemu_x86'], + [ + 'coverage.log', 'coverage.json', + 'coverage' + ], + r'{"files": \[], "gcovr/format_version": ".*"}' + ), + ] + TESTDATA_4 = [ + ( + 'gcovr', + [ + 'coverage.log', 'coverage.json', + 'coverage', os.path.join('coverage','coverage.xml') + ], + 'xml' + ), + ( + 'gcovr', + [ + 'coverage.log', 'coverage.json', + 'coverage', os.path.join('coverage','coverage.sonarqube.xml') + ], + 'sonarqube' + ), + ( + 'gcovr', + [ + 'coverage.log', 'coverage.json', + 'coverage', os.path.join('coverage','coverage.txt') + ], + 'txt' + ), + ( + 'gcovr', + [ + 'coverage.log', 'coverage.json', + 'coverage', os.path.join('coverage','coverage.csv') + ], + 'csv' + ), + ( + 'gcovr', + [ + 'coverage.log', 'coverage.json', + 'coverage', os.path.join('coverage','coverage.coveralls.json') + ], + 'coveralls' + ), + ( + 'gcovr', + [ + 'coverage.log', 'coverage.json', + 'coverage', os.path.join('coverage','index.html') + ], + 'html' + ), + ( + 'lcov', + [ + 'coverage.log', 'coverage.info', + 'ztest.info', 'coverage', + os.path.join('coverage','index.html') + ], + 'html' + ), + ( + 'lcov', + [ + 'coverage.log', 'coverage.info', + 'ztest.info' + ], + 'lcov' + ), + ] + TESTDATA_5 = [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2'), + ['qemu_x86'], + 'gcovr', + 'Running gcovr -r' + ), + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2'), + ['qemu_x86'], + 'lcov', + 'Running lcov --gcov-tool' + ) + ] + + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @pytest.mark.parametrize( + 'test_path, test_platforms, file_name', + TESTDATA_1, + ids=[ + 'coverage', + ] + ) + def test_coverage(self, capfd, test_path, test_platforms, out_path, file_name): + args = ['-i','--outdir', out_path, '-T', test_path] + \ + ['--coverage', '--coverage-tool', 'gcovr'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == '0' + + for f_name in file_name: + path = os.path.join(out_path, f_name) + assert os.path.exists(path), f'file not found {f_name}' + + @pytest.mark.parametrize( + 'test_path, test_platforms, expected', + TESTDATA_2, + ids=[ + 'enable_coverage', + ] + ) + def test_enable_coverage(self, capfd, test_path, test_platforms, out_path, expected): + args = ['-i','--outdir', out_path, '-T', test_path] + \ + ['--enable-coverage', '-vv'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == '0' + + for line in expected: + match = re.search(line, err) + assert match, f'line not found: {line}' + + @pytest.mark.parametrize( + 'test_path, test_platforms, file_name, expected_content', + TESTDATA_3, + ids=[ + 'coverage_basedir', + ] + ) + def test_coverage_basedir(self, capfd, test_path, test_platforms, out_path, file_name, expected_content): + base_dir = os.path.join(TEST_DATA, "test_dir") + if os.path.exists(base_dir): + os.rmdir(base_dir) + os.mkdir(base_dir) + args = ['--outdir', out_path,'-i', '-T', test_path] + \ + ['--coverage', '--coverage-tool', 'gcovr', '-v', '--coverage-basedir', base_dir] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == '0' + + for f_name in file_name: + path = os.path.join(out_path, f_name) + assert os.path.exists(path), f'file not found {f_name}' + if f_name == 'coverage.json': + with open(path, "r") as json_file: + json_content = json.load(json_file) + pattern = re.compile(expected_content) + assert pattern.match(json.dumps(json_content)) + if os.path.exists(base_dir): + os.rmdir(base_dir) + + @pytest.mark.parametrize( + 'cov_tool, file_name, cov_format', + TESTDATA_4, + ids=[ + 'coverage_format gcovr xml', + 'coverage_format gcovr sonarqube', + 'coverage_format gcovr txt', + 'coverage_format gcovr csv', + 'coverage_format gcovr coveralls', + 'coverage_format gcovr html', + 'coverage_format lcov html', + 'coverage_format lcov lcov', + ] + ) + def test_coverage_format(self, capfd, out_path, cov_tool, file_name, cov_format): + test_path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2') + test_platforms = ['qemu_x86'] + args = ['--outdir', out_path,'-i', '-T', test_path] + \ + ['--coverage', '--coverage-tool', cov_tool, '--coverage-formats', cov_format, '-v'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == '0' + + for f_name in file_name: + path = os.path.join(out_path, f_name) + assert os.path.exists(path), f'file not found {f_name}, probably format {cov_format} not work properly' + + + + @pytest.mark.parametrize( + 'test_path, test_platforms, cov_tool, expected_content', + TESTDATA_5, + ids=[ + 'coverage_tool gcovr', + 'coverage_tool lcov' + ] + ) + def test_coverage_tool(self, capfd, caplog, test_path, test_platforms, out_path, cov_tool, expected_content): + args = ['--outdir', out_path,'-i', '-T', test_path] + \ + ['--coverage', '--coverage-tool', cov_tool, '-v'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == '0' + + assert re.search(expected_content, caplog.text), f'{cov_tool} line not found' diff --git a/scripts/tests/twister_blackbox/test_report.py b/scripts/tests/twister_blackbox/test_report.py index 259579afc5c..80f8f722a3e 100644 --- a/scripts/tests/twister_blackbox/test_report.py +++ b/scripts/tests/twister_blackbox/test_report.py @@ -11,7 +11,6 @@ import mock import os import pytest -import re import shutil import sys @@ -107,25 +106,6 @@ class TestReport: "TEST_LOG_FILE.log" ), ] - TESTDATA_7 = [ - ( - os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86'], - [ - 'coverage.log', 'coverage.json', - 'coverage' - ], - ), - ] - TESTDATA_8 = [ - ( - os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86'], - [ - 'GCOV_COVERAGE_DUMP_START', 'GCOV_COVERAGE_DUMP_END' - ], - ), - ] @classmethod def setup_class(cls): @@ -352,60 +332,6 @@ def test_log_file(self, capfd, test_path, test_platforms, out_path, file_name): assert str(sys_exit.value) == '0' - @pytest.mark.parametrize( - 'test_path, test_platforms, file_name', - TESTDATA_7, - ids=[ - 'coverage', - ] - ) - def test_coverage(self, capfd, test_path, test_platforms, out_path, file_name): - args = ['-i','--outdir', out_path, '-T', test_path, '--coverage', '--coverage-tool', 'gcovr'] + \ - [val for pair in zip( - ['-p'] * len(test_platforms), test_platforms - ) for val in pair] - - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) - - out, err = capfd.readouterr() - sys.stdout.write(out) - sys.stderr.write(err) - - for f_name in file_name: - path = os.path.join(out_path, f_name) - assert os.path.exists(path), f'file not found {f_name}' - - assert str(sys_exit.value) == '0' - - @pytest.mark.parametrize( - 'test_path, test_platforms, expected', - TESTDATA_8, - ids=[ - 'enable_coverage', - ] - ) - def test_enable_coverage(self, capfd, test_path, test_platforms, out_path, expected): - args = ['-i','--outdir', out_path, '-T', test_path, '--enable-coverage', '-vv'] + \ - [val for pair in zip( - ['-p'] * len(test_platforms), test_platforms - ) for val in pair] - - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) - - out, err = capfd.readouterr() - sys.stdout.write(out) - sys.stderr.write(err) - - for line in expected: - match = re.search(line, err) - assert match, f'line not found: {line}' - - assert str(sys_exit.value) == '0' - @pytest.mark.parametrize( 'test_path, expected_testcase_count', [(os.path.join(TEST_DATA, 'tests', 'dummy'), 6),], From 15cb9bcab5536751bfa67bb2bf43767bde0334ff Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 1 Mar 2024 14:25:56 +0100 Subject: [PATCH 0578/2402] boards: st: stm32g0316: Use openocd as debug interface. Default pyocd configuration doesn't allow debugging on this board. Now that Zephyr openocd version support stm32g0 series, use it instead of pyocd. This commit provides working openocd configuration for this board an update documentation. Signed-off-by: Erwan Gouriou --- boards/st/stm32g0316_disco/board.cmake | 1 + boards/st/stm32g0316_disco/doc/index.rst | 10 ++-------- boards/st/stm32g0316_disco/support/openocd.cfg | 5 +++++ 3 files changed, 8 insertions(+), 8 deletions(-) create mode 100644 boards/st/stm32g0316_disco/support/openocd.cfg diff --git a/boards/st/stm32g0316_disco/board.cmake b/boards/st/stm32g0316_disco/board.cmake index e2863d9e32d..43e18743801 100644 --- a/boards/st/stm32g0316_disco/board.cmake +++ b/boards/st/stm32g0316_disco/board.cmake @@ -3,6 +3,7 @@ board_runner_args(pyocd "--target=stm32g031j6mx") board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32G031J6" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/st/stm32g0316_disco/doc/index.rst b/boards/st/stm32g0316_disco/doc/index.rst index 6767a115416..516a1f9623e 100644 --- a/boards/st/stm32g0316_disco/doc/index.rst +++ b/boards/st/stm32g0316_disco/doc/index.rst @@ -88,14 +88,8 @@ Flashing ======== The STM32G0316-DISCO board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is not yet supported by the openocd version included in -the Zephyr SDK. Instead, support can be enabled on pyocd by adding "pack" support with -the following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32g031j6 +interface. +This interface is supported by the openocd version included in the Zephyr SDK. Flashing an application to the STM32G0316-DISCO ----------------------------------------------- diff --git a/boards/st/stm32g0316_disco/support/openocd.cfg b/boards/st/stm32g0316_disco/support/openocd.cfg new file mode 100644 index 00000000000..2d736e0a408 --- /dev/null +++ b/boards/st/stm32g0316_disco/support/openocd.cfg @@ -0,0 +1,5 @@ +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32g0x.cfg] From 2262b294ddddc9cf5accf458f8a12c5fb3c4c2a0 Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Fri, 8 Mar 2024 00:00:36 +0800 Subject: [PATCH 0579/2402] arch: riscv: introduce a Kconfig to mask `mhartid` Configure a new Kconfig (`CONFIG_RISCV_HART_MASK`) so that it is possible to mask the `mhartid` of a processor. This is helpful in the cases when the hart id starts from non-zero value. Signed-off-by: Yong Cong Sin --- arch/riscv/Kconfig | 9 +++++++++ include/zephyr/arch/riscv/arch_inlines.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 2cc051b842d..9f2d24977a9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -229,6 +229,15 @@ config RV_BOOT_HART For RISC-V systems such as MPFS and FU540 this would be set to 1 to skip the E51 HART 0 as it is not usable in SMP configurations. +config RISCV_HART_MASK + int + default -1 + help + Configures the mask for the HART ID. + For RISC-V systems with HART ID starting from non-zero value, + i.e. 128, 129, ..(0x80, 8x81, ..), this can be configured to 63 (0x7f) + such that we can extract the bits that start from 0. + config RISCV_PMP bool "RISC-V PMP Support" select THREAD_STACK_INFO diff --git a/include/zephyr/arch/riscv/arch_inlines.h b/include/zephyr/arch/riscv/arch_inlines.h index 086972bd9e2..36dc2e640f9 100644 --- a/include/zephyr/arch/riscv/arch_inlines.h +++ b/include/zephyr/arch/riscv/arch_inlines.h @@ -14,7 +14,7 @@ static ALWAYS_INLINE uint32_t arch_proc_id(void) { - return csr_read(mhartid); + return csr_read(mhartid) & ((uintptr_t)CONFIG_RISCV_HART_MASK); } static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void) From a30795e1f6cd995066a304a199cef51515755b9e Mon Sep 17 00:00:00 2001 From: Morten Priess Date: Wed, 18 Oct 2023 08:50:21 +0200 Subject: [PATCH 0580/2402] Bluetooth: controller: Fixes for BIGinfo endianness issues The BIGinfo PDU bitsets were not accessed in a portable maner for endianness independence, and need to be handled as bit-manipulations. Add utility functions to access PDU bitset variables independent of endianness. Use macros to abstract the offsets and widths. Conversion of BIG_Handle to LE in HCI layer incorrectly use sys_cpu_to_le16, which fail because target type is 8-bit. Signed-off-by: Morten Priess --- subsys/bluetooth/controller/hci/hci.c | 36 +++--- subsys/bluetooth/controller/ll_sw/pdu.h | 106 ++++++++++++------ .../bluetooth/controller/ll_sw/ull_adv_iso.c | 33 +++--- .../bluetooth/controller/ll_sw/ull_sync_iso.c | 24 ++-- subsys/bluetooth/controller/util/util.c | 54 +++++++++ subsys/bluetooth/controller/util/util.h | 3 + 6 files changed, 176 insertions(+), 80 deletions(-) diff --git a/subsys/bluetooth/controller/hci/hci.c b/subsys/bluetooth/controller/hci/hci.c index dbe64a50681..b46e29c010b 100644 --- a/subsys/bluetooth/controller/hci/hci.c +++ b/subsys/bluetooth/controller/hci/hci.c @@ -7772,19 +7772,23 @@ static void le_per_adv_sync_report(struct pdu_data *pdu_data, sep->sync_handle = sys_cpu_to_le16(node_rx->hdr.handle); - /* NOTE: both sep and bi struct store little-endian values, - * explicit endian-ness conversion not required. + /* NOTE: both sep and bi struct store little-endian values. + * Multi-byte variables extracted using + * PDU_BIG_INFO_ISO_*_GET macros, which return + * value in host-endianness, require conversion. */ - sep->num_bis = bi->num_bis; - sep->nse = bi->nse; - sep->iso_interval = bi->iso_interval; - sep->bn = bi->bn; - sep->pto = bi->pto; - sep->irc = bi->irc; - sep->max_pdu = bi->max_pdu; - sys_put_le24(sys_le24_to_cpu(bi->sdu_interval), - sep->sdu_interval); - sep->max_sdu = bi->max_sdu; + sep->num_bis = PDU_BIG_INFO_NUM_BIS_GET(bi); + sep->nse = PDU_BIG_INFO_NSE_GET(bi); + sep->iso_interval = + sys_cpu_to_le16(PDU_BIG_INFO_ISO_INTERVAL_GET(bi)); + sep->bn = PDU_BIG_INFO_BN_GET(bi); + sep->pto = PDU_BIG_INFO_PTO_GET(bi); + sep->irc = PDU_BIG_INFO_IRC_GET(bi); + + sep->max_pdu = sys_cpu_to_le16(bi->max_pdu); + sys_put_le24(PDU_BIG_INFO_SDU_INTERVAL_GET(bi), + sep->sdu_interval); + sep->max_sdu = sys_cpu_to_le16(PDU_BIG_INFO_MAX_SDU_GET(bi)); sep->phy = HCI_AUX_PHY_TO_HCI_PHY(bi->chm_phy[4] >> 5); sep->framing = (bi->payload_count_framing[4] >> 7) & 0x01; if (bi_size == (PDU_BIG_INFO_ENCRYPTED_SIZE + 1)) { @@ -7833,7 +7837,7 @@ static void le_big_sync_established(struct pdu_data *pdu, evt_size = sizeof(*sep) + (lll->num_bis * sizeof(uint16_t)); sep = meta_evt(buf, BT_HCI_EVT_LE_BIG_SYNC_ESTABLISHED, evt_size); - sep->big_handle = sys_cpu_to_le16(node_rx->hdr.handle); + sep->big_handle = (uint8_t)node_rx->hdr.handle; /* Check for pdu field being aligned before accessing ISO sync * established event. @@ -7879,7 +7883,7 @@ static void le_big_sync_lost(struct pdu_data *pdu, } sep = meta_evt(buf, BT_HCI_EVT_LE_BIG_SYNC_LOST, sizeof(*sep)); - sep->big_handle = sys_cpu_to_le16(node_rx->hdr.handle); + sep->big_handle = (uint8_t)node_rx->hdr.handle; sep->reason = *((uint8_t *)pdu); } #endif /* CONFIG_BT_CTLR_SYNC_ISO */ @@ -7927,7 +7931,7 @@ static void le_big_complete(struct pdu_data *pdu_data, sep = meta_evt(buf, BT_HCI_EVT_LE_BIG_COMPLETE, evt_size); sep->status = BT_HCI_ERR_SUCCESS; - sep->big_handle = sys_cpu_to_le16(node_rx->hdr.handle); + sep->big_handle = (uint8_t)node_rx->hdr.handle; if (sep->status) { return; @@ -7966,7 +7970,7 @@ static void le_big_terminate(struct pdu_data *pdu, } sep = meta_evt(buf, BT_HCI_EVT_LE_BIG_TERMINATE, sizeof(*sep)); - sep->big_handle = sys_cpu_to_le16(node_rx->hdr.handle); + sep->big_handle = (uint8_t)node_rx->hdr.handle; sep->reason = *((uint8_t *)pdu); } #endif /* CONFIG_BT_CTLR_ADV_ISO */ diff --git a/subsys/bluetooth/controller/ll_sw/pdu.h b/subsys/bluetooth/controller/ll_sw/pdu.h index fe6fa8494f5..9f8f3637543 100644 --- a/subsys/bluetooth/controller/ll_sw/pdu.h +++ b/subsys/bluetooth/controller/ll_sw/pdu.h @@ -1128,49 +1128,35 @@ struct pdu_bis { } __packed; struct pdu_big_info { -#ifdef CONFIG_LITTLE_ENDIAN - uint32_t offs:14; - uint32_t offs_units:1; - uint32_t iso_interval:12; - uint32_t num_bis:5; - - uint32_t nse:5; - uint32_t bn:3; - uint32_t sub_interval:20; - uint32_t pto:4; - - uint32_t spacing:20; - uint32_t irc:4; - uint32_t max_pdu:8; - - uint8_t rfu; - - uint32_t seed_access_addr; + /* offs:14 [0].0 - [1].5 + * offs_units:1 [1].6 + * iso_interval:12 [1].7 - [3].2 + * num_bis:5 [3].3 - [3].7 + */ + uint8_t bi_packed_0_3[4]; - uint32_t sdu_interval:20; - uint32_t max_sdu:12; -#else - uint32_t num_bis:5; - uint32_t iso_interval:12; - uint32_t offs_units:1; - uint32_t offs:14; + /* nse:5 [0].0 - [0].4 + * bn:3 [0].5 - [0].7 + * sub_interval:20 [1].0 - [3].3 + * pto:4 [3].4 - [3].7 + */ + uint8_t bi_packed_4_7[4]; - uint32_t pto:4; - uint32_t sub_interval:20; - uint32_t bn:3; - uint32_t nse:5; + /* spacing:20 [0].0 - [2].3 + * irc:4 [2].4 - [2].7 + */ + uint8_t bi_packed_8_11[3]; - uint32_t max_pdu:8; - uint32_t irc:4; - uint32_t spacing:20; + uint8_t max_pdu; uint8_t rfu; uint32_t seed_access_addr; - uint32_t max_sdu:12; - uint32_t sdu_interval:20; -#endif /* CONFIG_LITTLE_ENDIAN */ + /* sdu_interval:20 [0].0 - [2].3 + * max_sdu:12; [2].4 - [3].7 + */ + uint8_t sdu_packed[4]; uint16_t base_crc_init; @@ -1185,6 +1171,56 @@ struct pdu_big_info { #define PDU_BIG_BN_MAX 0x07 #define PDU_BIG_PAYLOAD_COUNT_MAX 28 +#define PDU_BIG_INFO_OFFS_GET(bi) \ + util_get_bits(&(bi)->bi_packed_0_3[0], 0, 14) +#define PDU_BIG_INFO_OFFS_UNITS_GET(bi) \ + util_get_bits(&(bi)->bi_packed_0_3[1], 6, 1) +#define PDU_BIG_INFO_ISO_INTERVAL_GET(bi) \ + util_get_bits(&(bi)->bi_packed_0_3[1], 7, 12) +#define PDU_BIG_INFO_NUM_BIS_GET(bi) \ + util_get_bits(&(bi)->bi_packed_0_3[3], 3, 5) +#define PDU_BIG_INFO_NSE_GET(bi) \ + util_get_bits(&(bi)->bi_packed_4_7[0], 0, 5) +#define PDU_BIG_INFO_BN_GET(bi) \ + util_get_bits(&(bi)->bi_packed_4_7[0], 5, 3) +#define PDU_BIG_INFO_SUB_INTERVAL_GET(bi) \ + util_get_bits(&(bi)->bi_packed_4_7[1], 0, 20) +#define PDU_BIG_INFO_PTO_GET(bi) \ + util_get_bits(&(bi)->bi_packed_4_7[3], 4, 4) +#define PDU_BIG_INFO_SPACING_GET(bi) \ + util_get_bits(&(bi)->bi_packed_8_11[0], 0, 20) +#define PDU_BIG_INFO_IRC_GET(bi) \ + util_get_bits(&(bi)->bi_packed_8_11[2], 4, 4) +#define PDU_BIG_INFO_SDU_INTERVAL_GET(bi) \ + util_get_bits(&(bi)->sdu_packed[0], 0, 20) +#define PDU_BIG_INFO_MAX_SDU_GET(bi) \ + util_get_bits(&(bi)->sdu_packed[2], 4, 12) + +#define PDU_BIG_INFO_OFFS_SET(bi, val) \ + util_set_bits(&(bi)->bi_packed_0_3[0], 0, 14, val) +#define PDU_BIG_INFO_OFFS_UNITS_SET(bi, val) \ + util_set_bits(&(bi)->bi_packed_0_3[1], 6, 1, val) +#define PDU_BIG_INFO_ISO_INTERVAL_SET(bi, val) \ + util_set_bits(&(bi)->bi_packed_0_3[1], 7, 12, val) +#define PDU_BIG_INFO_NUM_BIS_SET(bi, val) \ + util_set_bits(&(bi)->bi_packed_0_3[3], 3, 5, val) +#define PDU_BIG_INFO_NSE_SET(bi, val) \ + util_set_bits(&(bi)->bi_packed_4_7[0], 0, 5, val) +#define PDU_BIG_INFO_BN_SET(bi, val) \ + util_set_bits(&(bi)->bi_packed_4_7[0], 5, 3, val) +#define PDU_BIG_INFO_SUB_INTERVAL_SET(bi, val) \ + util_set_bits(&(bi)->bi_packed_4_7[1], 0, 20, val) +#define PDU_BIG_INFO_PTO_SET(bi, val) \ + util_set_bits(&(bi)->bi_packed_4_7[3], 4, 4, val) +#define PDU_BIG_INFO_SPACING_SET(bi, val) \ + util_set_bits(&(bi)->bi_packed_8_11[0], 0, 20, val) +#define PDU_BIG_INFO_IRC_SET(bi, val) \ + util_set_bits(&(bi)->bi_packed_8_11[2], 4, 4, val) +#define PDU_BIG_INFO_SDU_INTERVAL_SET(bi, val) \ + util_set_bits(&(bi)->sdu_packed[0], 0, 20, val) +#define PDU_BIG_INFO_MAX_SDU_SET(bi, val) \ + util_set_bits(&(bi)->sdu_packed[2], 4, 12, val) + struct pdu_dtm { #ifdef CONFIG_LITTLE_ENDIAN uint8_t type:4; diff --git a/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c b/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c index af2bf66b911..77e75f66dd4 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c +++ b/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c @@ -481,20 +481,21 @@ uint8_t ll_big_create(uint8_t big_handle, uint8_t adv_handle, uint8_t num_bis, * advertising event. */ - big_info->iso_interval = - sys_cpu_to_le16(iso_interval_us / PERIODIC_INT_UNIT_US); - big_info->num_bis = lll_adv_iso->num_bis; - big_info->nse = lll_adv_iso->nse; - big_info->bn = lll_adv_iso->bn; - big_info->sub_interval = sys_cpu_to_le24(lll_adv_iso->sub_interval); - big_info->pto = lll_adv_iso->pto; - big_info->spacing = sys_cpu_to_le24(lll_adv_iso->bis_spacing); - big_info->irc = lll_adv_iso->irc; + PDU_BIG_INFO_ISO_INTERVAL_SET(big_info, iso_interval_us / PERIODIC_INT_UNIT_US); + PDU_BIG_INFO_NUM_BIS_SET(big_info, lll_adv_iso->num_bis); + PDU_BIG_INFO_NSE_SET(big_info, lll_adv_iso->nse); + PDU_BIG_INFO_BN_SET(big_info, lll_adv_iso->bn); + PDU_BIG_INFO_SUB_INTERVAL_SET(big_info, lll_adv_iso->sub_interval); + PDU_BIG_INFO_PTO_SET(big_info, lll_adv_iso->pto); + PDU_BIG_INFO_SPACING_SET(big_info, lll_adv_iso->bis_spacing); + PDU_BIG_INFO_IRC_SET(big_info, lll_adv_iso->irc); + big_info->max_pdu = lll_adv_iso->max_pdu; + (void)memcpy(&big_info->seed_access_addr, lll_adv_iso->seed_access_addr, sizeof(big_info->seed_access_addr)); - big_info->sdu_interval = sys_cpu_to_le24(sdu_interval); - big_info->max_sdu = max_sdu; + PDU_BIG_INFO_SDU_INTERVAL_SET(big_info, sdu_interval); + PDU_BIG_INFO_MAX_SDU_SET(big_info, max_sdu); (void)memcpy(&big_info->base_crc_init, lll_adv_iso->base_crc_init, sizeof(big_info->base_crc_init)); pdu_big_info_chan_map_phy_set(big_info->chm_phy, @@ -1377,12 +1378,12 @@ static inline void big_info_offset_fill(struct pdu_big_info *bi, offs = HAL_TICKER_TICKS_TO_US(ticks_offset) - start_us; offs = offs / OFFS_UNIT_30_US; if (!!(offs >> OFFS_UNIT_BITS)) { - bi->offs = sys_cpu_to_le16(offs / (OFFS_UNIT_300_US / - OFFS_UNIT_30_US)); - bi->offs_units = 1U; + PDU_BIG_INFO_OFFS_SET(bi, offs / (OFFS_UNIT_300_US / + OFFS_UNIT_30_US)); + PDU_BIG_INFO_OFFS_UNITS_SET(bi, 1U); } else { - bi->offs = sys_cpu_to_le16(offs); - bi->offs_units = 0U; + PDU_BIG_INFO_OFFS_SET(bi, offs); + PDU_BIG_INFO_OFFS_UNITS_SET(bi, 0U); } } diff --git a/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c b/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c index 8930f29ebd4..3989dcbf4d9 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c +++ b/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c @@ -424,20 +424,20 @@ void ull_sync_iso_setup(struct ll_sync_iso_set *sync_iso, lll->phy = BIT(bi->chm_phy[4] >> 5); - lll->num_bis = bi->num_bis; - lll->bn = bi->bn; - lll->nse = bi->nse; - lll->sub_interval = sys_le24_to_cpu(bi->sub_interval); + lll->num_bis = PDU_BIG_INFO_NUM_BIS_GET(bi); + lll->bn = PDU_BIG_INFO_BN_GET(bi); + lll->nse = PDU_BIG_INFO_NSE_GET(bi); + lll->sub_interval = PDU_BIG_INFO_SUB_INTERVAL_GET(bi); lll->max_pdu = bi->max_pdu; - lll->pto = bi->pto; + lll->pto = PDU_BIG_INFO_PTO_GET(bi); if (lll->pto) { lll->ptc = lll->bn; } else { lll->ptc = 0U; } - lll->bis_spacing = sys_le24_to_cpu(bi->spacing); - lll->irc = bi->irc; - lll->sdu_interval = sys_le24_to_cpu(bi->sdu_interval); + lll->bis_spacing = PDU_BIG_INFO_SPACING_GET(bi); + lll->irc = PDU_BIG_INFO_IRC_GET(bi); + lll->sdu_interval = PDU_BIG_INFO_SDU_INTERVAL_GET(bi); /* Pick the 39-bit payload count, 1 MSb is framing bit */ lll->payload_count = (uint64_t)bi->payload_count_framing[0]; @@ -479,7 +479,7 @@ void ull_sync_iso_setup(struct ll_sync_iso_set *sync_iso, } } - lll->iso_interval = sys_le16_to_cpu(bi->iso_interval); + lll->iso_interval = PDU_BIG_INFO_ISO_INTERVAL_GET(bi); interval_us = lll->iso_interval * PERIODIC_INT_UNIT_US; sync_iso->timeout_reload = @@ -492,7 +492,7 @@ void ull_sync_iso_setup(struct ll_sync_iso_set *sync_iso, lll_clock_ppm_get(sca)) * interval_us), USEC_PER_SEC); lll->window_widening_max_us = (interval_us >> 1) - EVENT_IFS_US; - if (bi->offs_units) { + if (PDU_BIG_INFO_OFFS_UNITS_GET(bi)) { lll->window_size_event_us = OFFS_UNIT_300_US; } else { lll->window_size_event_us = OFFS_UNIT_30_US; @@ -505,7 +505,7 @@ void ull_sync_iso_setup(struct ll_sync_iso_set *sync_iso, /* Calculate the BIG Offset in microseconds */ sync_iso_offset_us = ftr->radio_end_us; - sync_iso_offset_us += (uint32_t)sys_le16_to_cpu(bi->offs) * + sync_iso_offset_us += PDU_BIG_INFO_OFFS_GET(bi) * lll->window_size_event_us; /* Skip to first selected BIS subevent */ /* FIXME: add support for interleaved packing */ @@ -631,7 +631,6 @@ void ull_sync_iso_estab_done(struct node_rx_event_done *done) { struct ll_sync_iso_set *sync_iso; struct node_rx_sync_iso *se; - struct lll_sync_iso *lll; struct node_rx_pdu *rx; /* switch to normal prepare */ @@ -639,7 +638,6 @@ void ull_sync_iso_estab_done(struct node_rx_event_done *done) /* Get reference to ULL context */ sync_iso = CONTAINER_OF(done->param, struct ll_sync_iso_set, ull); - lll = &sync_iso->lll; /* Prepare BIG Sync Established */ rx = (void *)sync_iso->sync->iso.node_rx_estab; diff --git a/subsys/bluetooth/controller/util/util.c b/subsys/bluetooth/controller/util/util.c index 04f9361d3d8..43c6ac013e8 100644 --- a/subsys/bluetooth/controller/util/util.c +++ b/subsys/bluetooth/controller/util/util.c @@ -312,3 +312,57 @@ void util_bis_aa_le32(uint8_t bis, uint8_t *saa, uint8_t *dst) dst[2] ^= dwh[0]; } #endif /* CONFIG_BT_CTLR_ADV_ISO || CONFIG_BT_CTLR_SYNC_ISO*/ + +/** @brief Get a bit aligned value from a byte array + * Converts bitsets to any size variable (<= 32 bit), which is returned + * as a uint32_t value. + * + * @param data Pointer to bytes containing the requested value + * @param bit_offs Bit offset into data[0] for value LSB + * @param num_bits Number of bits to extract and convert to value + */ +uint32_t util_get_bits(uint8_t *data, uint8_t bit_offs, uint8_t num_bits) +{ + uint32_t value; + uint8_t shift, byteIdx, bits; + + value = 0; + shift = 0; + byteIdx = 0; + + while (num_bits) { + bits = MIN(num_bits, 8 - bit_offs); + value |= ((data[byteIdx] >> bit_offs) & BIT_MASK(bits)) << shift; + shift += bits; + num_bits -= bits; + bit_offs = 0; + byteIdx++; + } + + return value; +} + +/** @brief Set a bit aligned value in a byte array + * Converts a value up to 32 bits to a bitset in a byte array. + * + * @param data Pointer to bytes in which to place the value + * @param bit_offs Bit offset into data[0] for value LSB + * @param num_bits Number of bits to set in data + */ +void util_set_bits(uint8_t *data, uint8_t bit_offs, uint8_t num_bits, + uint32_t value) +{ + uint8_t byteIdx, bits; + + byteIdx = 0; + + while (num_bits) { + bits = MIN(num_bits, 8 - bit_offs); + data[byteIdx] = (data[byteIdx] & ~(BIT_MASK(bits) << bit_offs)) | + ((value & BIT_MASK(bits)) << bit_offs); + value >>= bits; + num_bits -= bits; + bit_offs = 0; + byteIdx++; + } +} diff --git a/subsys/bluetooth/controller/util/util.h b/subsys/bluetooth/controller/util/util.h index 5734767d267..a3869e05ad1 100644 --- a/subsys/bluetooth/controller/util/util.h +++ b/subsys/bluetooth/controller/util/util.h @@ -17,3 +17,6 @@ uint8_t util_ones_count_get(const uint8_t *octets, uint8_t octets_len); int util_aa_le32(uint8_t *dst); int util_saa_le32(uint8_t *dst, uint8_t handle); void util_bis_aa_le32(uint8_t bis, uint8_t *saa, uint8_t *dst); +uint32_t util_get_bits(uint8_t *data, uint8_t bit_offs, uint8_t num_bits); +void util_set_bits(uint8_t *data, uint8_t bit_offs, uint8_t num_bits, + uint32_t value); From f91065b7c983ebff46e09d8d6464d07b9116749e Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Mon, 11 Mar 2024 12:29:33 +0200 Subject: [PATCH 0581/2402] nxp: adsp: enable usage of DCACHE API With the transition to HWMv2, `CONFIG_CPU_HAS_DCACHE` is no longer selected. This causes issues with Sound Open Firmware since this configuration allows the usage of DCACHE-related cache management operations. As such, to fix said issues, select `CONFIG_CPU_HAS_DCACHE` on all NXP ADSP SOCs. Signed-off-by: Laurentiu Mihalcea --- soc/nxp/imx/imx8/Kconfig | 1 + soc/nxp/imx/imx8m/Kconfig | 1 + soc/nxp/imx/imx8ulp/Kconfig | 1 + soc/nxp/imx/imx8x/Kconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/soc/nxp/imx/imx8/Kconfig b/soc/nxp/imx/imx8/Kconfig index e7993616bbd..00615852d01 100644 --- a/soc/nxp/imx/imx8/Kconfig +++ b/soc/nxp/imx/imx8/Kconfig @@ -10,6 +10,7 @@ config SOC_MIMX8QM_ADSP select GEN_ISR_TABLES select XTENSA_SMALL_VECTOR_TABLE_ENTRY select HAS_MCUX + select CPU_HAS_DCACHE config MCUX_CORE_SUFFIX default "_dsp" if SOC_MIMX8QM_ADSP diff --git a/soc/nxp/imx/imx8m/Kconfig b/soc/nxp/imx/imx8m/Kconfig index ed796a8c2da..41b6dc6abd7 100644 --- a/soc/nxp/imx/imx8m/Kconfig +++ b/soc/nxp/imx/imx8m/Kconfig @@ -48,6 +48,7 @@ config SOC_MIMX8MP_ADSP select HAS_MCUX_CCM if CLOCK_CONTROL select HAS_MCUX_IOMUXC if PINCTRL select PINCTRL_IMX if HAS_MCUX_IOMUXC + select CPU_HAS_DCACHE config SOC_MIMX8MP_M7 select ARM diff --git a/soc/nxp/imx/imx8ulp/Kconfig b/soc/nxp/imx/imx8ulp/Kconfig index 5bee7c22107..d0f92357c2d 100644 --- a/soc/nxp/imx/imx8ulp/Kconfig +++ b/soc/nxp/imx/imx8ulp/Kconfig @@ -9,3 +9,4 @@ config SOC_MIMX8ULP_ADSP select ATOMIC_OPERATIONS_BUILTIN select GEN_ISR_TABLES select XTENSA_SMALL_VECTOR_TABLE_ENTRY + select CPU_HAS_DCACHE diff --git a/soc/nxp/imx/imx8x/Kconfig b/soc/nxp/imx/imx8x/Kconfig index b5c9a4e446e..43e1bcfc98c 100644 --- a/soc/nxp/imx/imx8x/Kconfig +++ b/soc/nxp/imx/imx8x/Kconfig @@ -10,6 +10,7 @@ config SOC_MIMX8QXP_ADSP select GEN_ISR_TABLES select XTENSA_SMALL_VECTOR_TABLE_ENTRY select HAS_MCUX + select CPU_HAS_DCACHE config MCUX_CORE_SUFFIX default "_dsp" if SOC_MIMX8QXP_ADSP From 093ffdf117a7a91983dca169ffa76202ae5c9b69 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 12 Mar 2024 15:55:02 +0100 Subject: [PATCH 0582/2402] Bluetooth: Host: Add NULL check for callback_list If no callbacks have been registered then callback_list is NULL, in which case we can skip searching. This also fixes a NULL-pointer acces in the while loop as previous_callback would be NULL when it gets dereferenced as previous_callback->_next. Signed-off-by: Emil Gydesen --- subsys/bluetooth/host/conn.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/subsys/bluetooth/host/conn.c b/subsys/bluetooth/host/conn.c index 57822a2e8ef..4486a9b2838 100644 --- a/subsys/bluetooth/host/conn.c +++ b/subsys/bluetooth/host/conn.c @@ -2434,6 +2434,11 @@ int bt_conn_cb_unregister(struct bt_conn_cb *cb) return -EINVAL; } + if (callback_list == NULL) { + /* No callsback registered */ + return -ENOENT; + } + if (callback_list == cb) { callback_list = callback_list->_next; return 0; From 251f52cbceb8a1682233c1792cbe68d28676318c Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Tue, 12 Mar 2024 23:08:40 +0000 Subject: [PATCH 0583/2402] list_hardware.py: sort rglob(SOC_YML) HWMv2 results This makes .config, autoconf.h, and configs.c deterministic again. Directory listing is not deterministic, it must always be sorted. https://reproducible-builds.org/docs/stable-inputs/ Fixes commit 61bbfb5ba25f ("scripts: introduce list_hardware.py for listing of architectures and SoCs") in collab-hwm branch which was squashed in mega HWMv2 commit 8dc3f856229c ("hwmv2: Introduce Hardware model version 2 and convert devices") SOF CI builds with both Windows and Linux and compares the outputs. This catches practically 100% of build reproducibility issues and caught this one too: https://github.com/thesofproject/sof/actions/runs/8241692987/job/22539664560 HWMv2 was a "big bang" integration on both the Zephyr and SOF sides. So this `rglob()` was a needle in a haystack but with hindsight, this issue is really trivial to reproduce and verify: ``` apt-get install disorderfs mkdir disorderedWorkspace/ disorderfs --shuffle-dirents=yes workspace/ disorderedWorkspace/ ``` ... then just build `samples/hello_world/` twice in disorderedWorkspace/ with any --board and compare the build directories. Signed-off-by: Marc Herbert --- scripts/list_hardware.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/list_hardware.py b/scripts/list_hardware.py index d43cfb29c39..e17ff7b4532 100755 --- a/scripts/list_hardware.py +++ b/scripts/list_hardware.py @@ -173,7 +173,7 @@ def find_v2_systems(args): yml_files = [] systems = Systems() for root in args.soc_roots: - yml_files.extend((root / 'soc').rglob(SOC_YML)) + yml_files.extend(sorted((root / 'soc').rglob(SOC_YML))) for soc_yml in yml_files: if soc_yml.is_file(): From 92ad509902622e99983e4ca6a139ecea38a8821a Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Sun, 25 Feb 2024 06:46:19 +0100 Subject: [PATCH 0584/2402] Bluetooth: Controller: Fix ext adv param checking intervals Fix Extended Advertising Parameter check to exclude legacy high duty cycle directed advertising from validating the intervals as advertising interval parameter values are not applicable for high duty cycle directed advertising. Signed-off-by: Vinayak Kariappa Chettimada --- subsys/bluetooth/controller/hci/hci.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/subsys/bluetooth/controller/hci/hci.c b/subsys/bluetooth/controller/hci/hci.c index b46e29c010b..1bb10f578d2 100644 --- a/subsys/bluetooth/controller/hci/hci.c +++ b/subsys/bluetooth/controller/hci/hci.c @@ -3418,6 +3418,7 @@ static void le_set_ext_adv_param(struct net_buf *buf, struct net_buf **evt) return; } + evt_prop = sys_le16_to_cpu(cmd->props); min_interval = sys_get_le24(cmd->prim_min_interval); if (IS_ENABLED(CONFIG_BT_CTLR_PARAM_CHECK)) { @@ -3428,9 +3429,11 @@ static void le_set_ext_adv_param(struct net_buf *buf, struct net_buf **evt) * supported advertising interval maximum value defined in the * Kconfig CONFIG_BT_CTLR_ADV_INTERVAL_MAX. */ - if ((min_interval > max_interval) || - (min_interval < BT_HCI_LE_PRIM_ADV_INTERVAL_MIN) || - (max_interval > CONFIG_BT_CTLR_ADV_INTERVAL_MAX)) { + if ((!(evt_prop & BT_HCI_LE_ADV_PROP_LEGACY) || + !(evt_prop & BT_HCI_LE_ADV_PROP_HI_DC_CONN)) && + ((min_interval > max_interval) || + (min_interval < BT_HCI_LE_PRIM_ADV_INTERVAL_MIN) || + (max_interval > CONFIG_BT_CTLR_ADV_INTERVAL_MAX))) { *evt = cmd_complete_status(BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL); return; } @@ -3442,7 +3445,6 @@ static void le_set_ext_adv_param(struct net_buf *buf, struct net_buf **evt) return; } - evt_prop = sys_le16_to_cpu(cmd->props); tx_pwr = cmd->tx_power; phy_p = BIT(cmd->prim_adv_phy - 1); phy_s = BIT(cmd->sec_adv_phy - 1); From 11bae5cfa95b356c69a13ca1cd3d11c049a76a9b Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Thu, 29 Feb 2024 14:36:10 +0100 Subject: [PATCH 0585/2402] Bluetooth: Controller: Fix missing radio timer comp and range delay Fix missing PPI to timer start compensation and missing inclusion of range delay in the calculation of packet header receive timeout value. Signed-off-by: Vinayak Kariappa Chettimada --- .../ll_sw/nordic/hal/nrf5/radio/radio.c | 5 ++-- .../ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h | 25 ++++++++++++------- .../controller/ll_sw/nordic/lll/lll_adv.c | 6 +++-- .../controller/ll_sw/nordic/lll/lll_adv_aux.c | 5 ++-- .../ll_sw/nordic/lll/lll_central_iso.c | 4 +-- .../controller/ll_sw/nordic/lll/lll_conn.c | 7 +++--- .../controller/ll_sw/nordic/lll/lll_scan.c | 6 +++-- .../ll_sw/nordic/lll/lll_scan_aux.c | 5 ++-- .../ll_sw/nordic/lll/lll_sync_iso.c | 2 +- .../ll_sw/nordic/lll/lll_tim_internal.h | 6 ----- 10 files changed, 40 insertions(+), 31 deletions(-) diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c index 97919a18dd3..b681fa67a14 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c @@ -874,8 +874,9 @@ void sw_switch(uint8_t dir_curr, uint8_t dir_next, uint8_t phy_curr, uint8_t fla } if (delay < SW_SWITCH_TIMER->CC[cc]) { - nrf_timer_cc_set(SW_SWITCH_TIMER, cc, - (SW_SWITCH_TIMER->CC[cc] - delay)); + nrf_timer_cc_set(SW_SWITCH_TIMER, + cc, + (SW_SWITCH_TIMER->CC[cc] - delay - HAL_RADIO_TMR_START_DELAY_US)); } else { nrf_timer_cc_set(SW_SWITCH_TIMER, cc, 1); } diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h index 842b4189184..dce326d469a 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h @@ -10,7 +10,9 @@ /* Common radio resources */ #include "radio_nrf5_resources.h" -/* Helpers for radio timing conversions */ +/* Helpers for radio timing conversions. + * These has to come before the radio_*.h include below. + */ #define HAL_RADIO_NS2US_CEIL(ns) ((ns + 999)/1000) #define HAL_RADIO_NS2US_ROUND(ns) ((ns + 500)/1000) @@ -42,7 +44,9 @@ #error "Unsupported SoC." #endif -/* Define to reset PPI registration */ +/* Define to reset PPI registration. + * This has to come before the ppi/dppi includes below. + */ #define NRF_PPI_NONE 0 /* This has to come before the ppi/dppi includes below. */ @@ -66,13 +70,6 @@ #include "radio_nrf5_txp.h" -/* SoC specific Radio PDU length field maximum value */ -#if defined(CONFIG_SOC_SERIES_NRF51X) -#define HAL_RADIO_PDU_LEN_MAX (BIT(5) - 1) -#else -#define HAL_RADIO_PDU_LEN_MAX (BIT(8) - 1) -#endif - /* Common NRF_RADIO power-on reset value. Refer to Product Specification, * RADIO Registers section for the documented reset values. * @@ -80,3 +77,13 @@ * In the future if MDK or nRFx header include these, use them instead. */ #define HAL_RADIO_RESET_VALUE_PCNF1 0x00000000UL + +/* SoC specific Radio PDU length field maximum value */ +#if defined(CONFIG_SOC_SERIES_NRF51X) +#define HAL_RADIO_PDU_LEN_MAX (BIT(5) - 1) +#else +#define HAL_RADIO_PDU_LEN_MAX (BIT(8) - 1) +#endif + +/* This is delay between PPI task START and timer actual start counting. */ +#define HAL_RADIO_TMR_START_DELAY_US 1U diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv.c index 851c82692b8..25c08568480 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv.c @@ -1196,8 +1196,10 @@ static void isr_tx(void *param) } #endif /* CONFIG_BT_CTLR_PRIVACY */ - /* +/- 2us active clock jitter, +1 us hcto compensation */ - hcto = radio_tmr_tifs_base_get() + EVENT_IFS_US + 4 + 1; + /* +/- 2us active clock jitter, +1 us PPI to timer start compensation */ + hcto = radio_tmr_tifs_base_get() + EVENT_IFS_US + + (EVENT_CLOCK_JITTER_US << 1) + RANGE_DELAY_US + + HAL_RADIO_TMR_START_DELAY_US; hcto += radio_rx_chain_delay_get(phy_p, 0); hcto += addr_us_get(phy_p); hcto -= radio_tx_chain_delay_get(phy_p, 0); diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_aux.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_aux.c index 6b61c3b559f..e16cddb5d3a 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_aux.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_aux.c @@ -509,9 +509,10 @@ static void isr_tx_rx(void *param) } #endif /* CONFIG_BT_CTLR_PRIVACY */ - /* +/- 2us active clock jitter, +1 us hcto compensation */ + /* +/- 2us active clock jitter, +1 us PPI to timer start compensation */ hcto = radio_tmr_tifs_base_get() + EVENT_IFS_US + - (EVENT_CLOCK_JITTER_US << 1U) + 1U; + (EVENT_CLOCK_JITTER_US << 1) + RANGE_DELAY_US + + HAL_RADIO_TMR_START_DELAY_US; hcto += radio_rx_chain_delay_get(lll->phy_s, PHY_FLAGS_S8); hcto += addr_us_get(lll->phy_s); hcto -= radio_tx_chain_delay_get(lll->phy_s, PHY_FLAGS_S8); diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c index 751c3915fc2..48247b18e6f 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c @@ -500,10 +500,10 @@ static void isr_tx(void *param) /* assert if radio packet ptr is not set and radio started rx */ LL_ASSERT(!radio_is_ready()); - /* +/- 2us active clock jitter, +1 us hcto compensation */ + /* +/- 2us active clock jitter, +1 us PPI to timer start compensation */ hcto = radio_tmr_tifs_base_get() + EVENT_IFS_US + (EVENT_CLOCK_JITTER_US << 1) + RANGE_DELAY_US + - HCTO_START_DELAY_US; + HAL_RADIO_TMR_START_DELAY_US; #if defined(CONFIG_BT_CTLR_PHY) hcto += radio_rx_chain_delay_get(cis_lll->rx.phy, PHY_FLAGS_S8); diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c index 1f3cd8a04af..faf54dac417 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c @@ -579,9 +579,10 @@ void lll_conn_isr_tx(void *param) } #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_TX */ - /* +/- 2us active clock jitter, +1 us hcto compensation */ - hcto = radio_tmr_tifs_base_get() + EVENT_IFS_US + (EVENT_CLOCK_JITTER_US << 1) + - RANGE_DELAY_US + HCTO_START_DELAY_US; + /* +/- 2us active clock jitter, +1 us PPI to timer start compensation */ + hcto = radio_tmr_tifs_base_get() + EVENT_IFS_US + + (EVENT_CLOCK_JITTER_US << 1) + RANGE_DELAY_US + + HAL_RADIO_TMR_START_DELAY_US; #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_TX) hcto += cte_len; #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_TX */ diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c index 7279d407ad8..a4e1a2bd705 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c @@ -805,8 +805,10 @@ static void isr_tx(void *param) } #endif /* CONFIG_BT_CTLR_PRIVACY */ - /* +/- 2us active clock jitter, +1 us hcto compensation */ - hcto = radio_tmr_tifs_base_get() + EVENT_IFS_US + 4 + 1; + /* +/- 2us active clock jitter, +1 us PPI to timer start compensation */ + hcto = radio_tmr_tifs_base_get() + EVENT_IFS_US + + (EVENT_CLOCK_JITTER_US << 1) + RANGE_DELAY_US + + HAL_RADIO_TMR_START_DELAY_US; hcto += radio_rx_chain_delay_get(0, 0); hcto += addr_us_get(0); hcto -= radio_tx_chain_delay_get(0, 0); diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c index 57132835fba..a40e90e20a0 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c @@ -1350,9 +1350,10 @@ static void isr_tx(struct lll_scan_aux *lll_aux, void *pdu_rx, } #endif /* CONFIG_BT_CTLR_PRIVACY */ - /* +/- 2us active clock jitter, +1 us hcto compensation */ + /* +/- 2us active clock jitter, +1 us PPI to timer start compensation */ hcto = radio_tmr_tifs_base_get() + EVENT_IFS_US + - (EVENT_CLOCK_JITTER_US << 1U) + RANGE_DELAY_US + 1U; + (EVENT_CLOCK_JITTER_US << 1) + RANGE_DELAY_US + + HAL_RADIO_TMR_START_DELAY_US; hcto += radio_rx_chain_delay_get(lll_aux->phy, PHY_FLAGS_S8); hcto += addr_us_get(lll_aux->phy); hcto -= radio_tx_chain_delay_get(lll_aux->phy, PHY_FLAGS_S8); diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c index 2c1125e02d4..e9111981d6f 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c @@ -1004,7 +1004,7 @@ static void isr_rx(void *param) * the current subevent we are listening. */ hcto += (((EVENT_CLOCK_JITTER_US << 1) * nse) << 1) + - RANGE_DELAY_US + HCTO_START_DELAY_US; + RANGE_DELAY_US + HAL_RADIO_TMR_START_DELAY_US; } else { /* First subevent PDU was not received, hence setup radio packet * timer header complete timeout from where the first subevent diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_tim_internal.h b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_tim_internal.h index 41aa2b0454b..eb1858ca1bb 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_tim_internal.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_tim_internal.h @@ -12,12 +12,6 @@ #define RANGE_DISTANCE 1000 /* meters */ #define RANGE_DELAY_US (2 * RANGE_DISTANCE * 4 / 1000) -/* This is a compensation of delay between PPI task START and timer start counting. - * HCTO is a timer used to stop Radio peripheral in receive mode if packet address was not - * received. - */ -#define HCTO_START_DELAY_US 1U - static inline uint32_t addr_us_get(uint8_t phy) { switch (phy) { From bd5e906f681a63b1ab0d3beae54f98e4e6ee9a59 Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Fri, 1 Mar 2024 04:47:07 +0100 Subject: [PATCH 0586/2402] Bluetooth: Controller: Fix assertion establishing periodic sync When the AUX_ADV_IND and AUX_SYNC_IND are close to each other, the duration between them is not sufficient to schedule a new instance of ticker to establish synchronization. This processing time introduces latencies detected by the prepare callback. When the sync offset is low, schedule the start of the reception to next periodic interval. Signed-off-by: Vinayak Kariappa Chettimada --- subsys/bluetooth/controller/ll_sw/ull_sync.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/subsys/bluetooth/controller/ll_sw/ull_sync.c b/subsys/bluetooth/controller/ll_sw/ull_sync.c index 93d0b88f72d..1d653748587 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_sync.c +++ b/subsys/bluetooth/controller/ll_sw/ull_sync.c @@ -671,6 +671,7 @@ void ull_sync_setup(struct ll_scan_set *scan, struct ll_scan_aux_set *aux, struct lll_sync *lll; uint16_t sync_handle; uint32_t interval_us; + uint32_t overhead_us; struct pdu_adv *pdu; uint16_t interval; uint32_t slot_us; @@ -819,6 +820,22 @@ void ull_sync_setup(struct ll_scan_set *scan, struct ll_scan_aux_set *aux, sync_offset_us -= EVENT_JITTER_US; sync_offset_us -= ready_delay_us; + /* Minimum prepare tick offset + minimum preempt tick offset are the + * overheads before ULL scheduling can setup radio for reception + */ + overhead_us = HAL_TICKER_TICKS_TO_US(HAL_TICKER_CNTR_CMP_OFFSET_MIN << 1); + + /* CPU execution overhead to setup the radio for reception */ + overhead_us += EVENT_OVERHEAD_END_US + EVENT_OVERHEAD_START_US; + + /* If not sufficient CPU processing time, skip to receiving next + * event. + */ + if ((sync_offset_us - ftr->radio_end_us) < overhead_us) { + sync_offset_us += interval_us; + lll->event_counter++; + } + interval_us -= lll->window_widening_periodic_us; /* Calculate event time reservation */ From cd6674f7c23e03575e9da58f934f53f771c1d6e9 Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Tue, 12 Mar 2024 12:33:38 +0100 Subject: [PATCH 0587/2402] samples: Bluetooth: Broadcast audio sink USB headset on nRF52 Series Broadcast audio sink USB headset on nRF52 Series with USB support. Signed-off-by: Vinayak Kariappa Chettimada --- samples/bluetooth/broadcast_audio_sink/Kconfig | 3 ++- .../boards/nrf52833dk_nrf52833.conf | 3 +++ .../boards/nrf52833dk_nrf52833.overlay | 15 +++++++++++++++ .../boards/nrf52840dongle_nrf52840.conf | 3 +++ .../boards/nrf52840dongle_nrf52840.overlay | 15 +++++++++++++++ .../boards/nrf5340_audio_dk_nrf5340_cpuapp.conf | 6 +----- .../boards/nrf5340dk_nrf5340_cpuapp.conf | 3 --- .../bluetooth/broadcast_audio_sink/sample.yaml | 2 ++ samples/bluetooth/broadcast_audio_sink/src/main.c | 2 +- .../boards/nrf52833dk_nrf52833.conf | 4 +--- .../boards/nrf52840dongle_nrf52840.conf | 4 +--- .../broadcast_audio_source/boards/nrf52_bsim.conf | 1 - .../boards/nrf5340_audio_dk_nrf5340_cpuapp.conf | 4 +--- .../boards/nrf5340bsim_nrf5340_cpuapp.conf | 1 - .../boards/nrf5340dk_nrf5340_cpuapp.conf | 1 - 15 files changed, 45 insertions(+), 22 deletions(-) create mode 100644 samples/bluetooth/broadcast_audio_sink/boards/nrf52833dk_nrf52833.conf create mode 100644 samples/bluetooth/broadcast_audio_sink/boards/nrf52833dk_nrf52833.overlay create mode 100644 samples/bluetooth/broadcast_audio_sink/boards/nrf52840dongle_nrf52840.conf create mode 100644 samples/bluetooth/broadcast_audio_sink/boards/nrf52840dongle_nrf52840.overlay delete mode 100644 samples/bluetooth/broadcast_audio_sink/boards/nrf5340dk_nrf5340_cpuapp.conf delete mode 100644 samples/bluetooth/broadcast_audio_source/boards/nrf52_bsim.conf delete mode 100644 samples/bluetooth/broadcast_audio_source/boards/nrf5340bsim_nrf5340_cpuapp.conf delete mode 100644 samples/bluetooth/broadcast_audio_source/boards/nrf5340dk_nrf5340_cpuapp.conf diff --git a/samples/bluetooth/broadcast_audio_sink/Kconfig b/samples/bluetooth/broadcast_audio_sink/Kconfig index 7faffd0716a..e8e10d84a74 100644 --- a/samples/bluetooth/broadcast_audio_sink/Kconfig +++ b/samples/bluetooth/broadcast_audio_sink/Kconfig @@ -47,7 +47,8 @@ config ENABLE_LC3 bool "Enable the LC3 codec" # By default let's enable it in the platforms we know are capable of supporting it default y - depends on (ARCH_POSIX || SOC_NRF5340_CPUAPP) + depends on CPU_HAS_FPU && \ + (ARCH_POSIX || SOC_COMPATIBLE_NRF52X || SOC_COMPATIBLE_NRF5340_CPUAPP) select LIBLC3 select FPU diff --git a/samples/bluetooth/broadcast_audio_sink/boards/nrf52833dk_nrf52833.conf b/samples/bluetooth/broadcast_audio_sink/boards/nrf52833dk_nrf52833.conf new file mode 100644 index 00000000000..69b3cc51473 --- /dev/null +++ b/samples/bluetooth/broadcast_audio_sink/boards/nrf52833dk_nrf52833.conf @@ -0,0 +1,3 @@ +# Use USB Audio as audio sink +CONFIG_USE_USB_AUDIO_OUTPUT=y +CONFIG_USB_DEVICE_PRODUCT="USB Broadcast Sink" diff --git a/samples/bluetooth/broadcast_audio_sink/boards/nrf52833dk_nrf52833.overlay b/samples/bluetooth/broadcast_audio_sink/boards/nrf52833dk_nrf52833.overlay new file mode 100644 index 00000000000..b8e72f1b61c --- /dev/null +++ b/samples/bluetooth/broadcast_audio_sink/boards/nrf52833dk_nrf52833.overlay @@ -0,0 +1,15 @@ +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; + + hs_0: hs_0 { + compatible = "usb-audio-hs"; + mic-feature-mute; + mic-channel-l; + mic-channel-r; + + hp-feature-mute; + hp-channel-l; + hp-channel-r; + }; +}; diff --git a/samples/bluetooth/broadcast_audio_sink/boards/nrf52840dongle_nrf52840.conf b/samples/bluetooth/broadcast_audio_sink/boards/nrf52840dongle_nrf52840.conf new file mode 100644 index 00000000000..69b3cc51473 --- /dev/null +++ b/samples/bluetooth/broadcast_audio_sink/boards/nrf52840dongle_nrf52840.conf @@ -0,0 +1,3 @@ +# Use USB Audio as audio sink +CONFIG_USE_USB_AUDIO_OUTPUT=y +CONFIG_USB_DEVICE_PRODUCT="USB Broadcast Sink" diff --git a/samples/bluetooth/broadcast_audio_sink/boards/nrf52840dongle_nrf52840.overlay b/samples/bluetooth/broadcast_audio_sink/boards/nrf52840dongle_nrf52840.overlay new file mode 100644 index 00000000000..b8e72f1b61c --- /dev/null +++ b/samples/bluetooth/broadcast_audio_sink/boards/nrf52840dongle_nrf52840.overlay @@ -0,0 +1,15 @@ +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; + + hs_0: hs_0 { + compatible = "usb-audio-hs"; + mic-feature-mute; + mic-channel-l; + mic-channel-r; + + hp-feature-mute; + hp-channel-l; + hp-channel-r; + }; +}; diff --git a/samples/bluetooth/broadcast_audio_sink/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf b/samples/bluetooth/broadcast_audio_sink/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf index f8f7db343e8..69b3cc51473 100644 --- a/samples/bluetooth/broadcast_audio_sink/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf +++ b/samples/bluetooth/broadcast_audio_sink/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf @@ -1,7 +1,3 @@ -# The LC3 codec uses a large amount of stack. This app runs the codec in the work-queue, hence -# inctease stack size for that thread. -CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096 -CONFIG_ENABLE_LC3=y -CONFIG_TARGET_BROADCAST_CHANNEL=1 +# Use USB Audio as audio sink CONFIG_USE_USB_AUDIO_OUTPUT=y CONFIG_USB_DEVICE_PRODUCT="USB Broadcast Sink" diff --git a/samples/bluetooth/broadcast_audio_sink/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/bluetooth/broadcast_audio_sink/boards/nrf5340dk_nrf5340_cpuapp.conf deleted file mode 100644 index 8ab7a163fb6..00000000000 --- a/samples/bluetooth/broadcast_audio_sink/boards/nrf5340dk_nrf5340_cpuapp.conf +++ /dev/null @@ -1,3 +0,0 @@ -# The LC3 codec uses a large amount of stack. This app runs the codec in the work-queue, hence -# inctease stack size for that thread. -CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096 diff --git a/samples/bluetooth/broadcast_audio_sink/sample.yaml b/samples/bluetooth/broadcast_audio_sink/sample.yaml index 1df6e582baa..51b1d04b0ed 100644 --- a/samples/bluetooth/broadcast_audio_sink/sample.yaml +++ b/samples/bluetooth/broadcast_audio_sink/sample.yaml @@ -20,8 +20,10 @@ tests: - nrf52_bsim - nrf52833dk/nrf52820 - nrf52833dk/nrf52833 + - nrf52840dongle/nrf52840 integration_platforms: - nrf52_bsim - nrf52833dk/nrf52833 + - nrf52840dongle/nrf52840 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/broadcast_audio_sink/src/main.c b/samples/bluetooth/broadcast_audio_sink/src/main.c index 562b4cc3be4..c5e89bd9993 100644 --- a/samples/bluetooth/broadcast_audio_sink/src/main.c +++ b/samples/bluetooth/broadcast_audio_sink/src/main.c @@ -1259,7 +1259,7 @@ static int init(void) usb_audio_register(hs_dev, &usb_ops); err = usb_enable(NULL); - if (err != 0) { + if (err && err != -EALREADY) { printk("Failed to enable USB\n"); return err; } diff --git a/samples/bluetooth/broadcast_audio_source/boards/nrf52833dk_nrf52833.conf b/samples/bluetooth/broadcast_audio_source/boards/nrf52833dk_nrf52833.conf index ff68bab6356..8b65fa9a9d8 100644 --- a/samples/bluetooth/broadcast_audio_source/boards/nrf52833dk_nrf52833.conf +++ b/samples/bluetooth/broadcast_audio_source/boards/nrf52833dk_nrf52833.conf @@ -1,5 +1,3 @@ -CONFIG_MAIN_STACK_SIZE=4096 - -# Use USB Audio as input +# Use USB Audio as audio source CONFIG_USE_USB_AUDIO_INPUT=y CONFIG_USB_DEVICE_PRODUCT="Zephyr Broadcast Source" diff --git a/samples/bluetooth/broadcast_audio_source/boards/nrf52840dongle_nrf52840.conf b/samples/bluetooth/broadcast_audio_source/boards/nrf52840dongle_nrf52840.conf index ff68bab6356..8b65fa9a9d8 100644 --- a/samples/bluetooth/broadcast_audio_source/boards/nrf52840dongle_nrf52840.conf +++ b/samples/bluetooth/broadcast_audio_source/boards/nrf52840dongle_nrf52840.conf @@ -1,5 +1,3 @@ -CONFIG_MAIN_STACK_SIZE=4096 - -# Use USB Audio as input +# Use USB Audio as audio source CONFIG_USE_USB_AUDIO_INPUT=y CONFIG_USB_DEVICE_PRODUCT="Zephyr Broadcast Source" diff --git a/samples/bluetooth/broadcast_audio_source/boards/nrf52_bsim.conf b/samples/bluetooth/broadcast_audio_source/boards/nrf52_bsim.conf deleted file mode 100644 index 5df721fba26..00000000000 --- a/samples/bluetooth/broadcast_audio_source/boards/nrf52_bsim.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_MAIN_STACK_SIZE=4096 diff --git a/samples/bluetooth/broadcast_audio_source/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf b/samples/bluetooth/broadcast_audio_source/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf index ff68bab6356..8b65fa9a9d8 100644 --- a/samples/bluetooth/broadcast_audio_source/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf +++ b/samples/bluetooth/broadcast_audio_source/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf @@ -1,5 +1,3 @@ -CONFIG_MAIN_STACK_SIZE=4096 - -# Use USB Audio as input +# Use USB Audio as audio source CONFIG_USE_USB_AUDIO_INPUT=y CONFIG_USB_DEVICE_PRODUCT="Zephyr Broadcast Source" diff --git a/samples/bluetooth/broadcast_audio_source/boards/nrf5340bsim_nrf5340_cpuapp.conf b/samples/bluetooth/broadcast_audio_source/boards/nrf5340bsim_nrf5340_cpuapp.conf deleted file mode 100644 index 5df721fba26..00000000000 --- a/samples/bluetooth/broadcast_audio_source/boards/nrf5340bsim_nrf5340_cpuapp.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_MAIN_STACK_SIZE=4096 diff --git a/samples/bluetooth/broadcast_audio_source/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/bluetooth/broadcast_audio_source/boards/nrf5340dk_nrf5340_cpuapp.conf deleted file mode 100644 index 5df721fba26..00000000000 --- a/samples/bluetooth/broadcast_audio_source/boards/nrf5340dk_nrf5340_cpuapp.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_MAIN_STACK_SIZE=4096 From 9a0b8e7809b0e877d2be664dcc09f9ba117b8a19 Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Wed, 13 Mar 2024 10:49:04 +0800 Subject: [PATCH 0588/2402] posix: sysconf: use Z_SC_VAL_IFDEF for sysconf constants Previously, CONFIG_MAX_TIMER_COUNT and CONFIG_MSG_COUNT_MAX were used without checking if CONFIG_TIMER and CONFIG_POSIX_MQUEUE were enabled. Use Z_SC_VAL_IFDEF() to conditionally define those constants based on their gating Kconfig values, otherwise, they are defined to -1. Signed-off-by: Christopher Friedt --- include/zephyr/posix/unistd.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/zephyr/posix/unistd.h b/include/zephyr/posix/unistd.h index e78c49fbeeb..05d2e4e0588 100644 --- a/include/zephyr/posix/unistd.h +++ b/include/zephyr/posix/unistd.h @@ -134,7 +134,8 @@ extern "C" { #define _POSIX_LOGIN_NAME_MAX (9) #define _POSIX_MAX_CANON (255) #define _POSIX_MAX_INPUT (255) -#define _POSIX_MQ_OPEN_MAX CONFIG_MSG_COUNT_MAX +#define _POSIX_MQ_OPEN_MAX Z_SC_VAL_IFDEF(CONFIG_POSIX_MQUEUE, \ + CONFIG_MSG_COUNT_MAX) #define _POSIX_MQ_PRIO_MAX (32) #define _POSIX_NAME_MAX (14) #define _POSIX_NGROUPS_MAX (8) @@ -216,7 +217,7 @@ extern "C" { #define SIGQUEUE_MAX _POSIX_SIGQUEUE_MAX #define STREAM_MAX _POSIX_STREAM_MAX #define SYMLOOP_MAX _POSIX_SYMLOOP_MAX -#define TIMER_MAX CONFIG_MAX_TIMER_COUNT +#define TIMER_MAX Z_SC_VAL_IFDEF(CONFIG_TIMER, CONFIG_MAX_TIMER_COUNT) #define TTY_NAME_MAX _POSIX_TTY_NAME_MAX #define TZNAME_MAX _POSIX_TZNAME_MAX From c6e482714f2387c19b432e2926775c61d1c887f0 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 11 Mar 2024 14:28:45 +0200 Subject: [PATCH 0589/2402] MAINTAINERS: Add maass-hamburg as DHCPv4 collaborator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adding Fin Maaß (maass-hamburg) as a collaborator to the DHCPv4. Related PR #69992 Signed-off-by: Jukka Rissanen --- MAINTAINERS.yml | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 43b516e04df..8bd82e024c3 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2552,10 +2552,12 @@ Networking: - include/zephyr/net/ieee802154*.h - include/zephyr/net/wifi*.h - include/zephyr/net/buf.h + - include/zephyr/net/dhcpv4*.h - samples/net/gptp/ - samples/net/sockets/coap_*/ - samples/net/lwm2m_client/ - samples/net/wifi/ + - samples/net/dhcpv4_client/ - subsys/net/buf*.c - subsys/net/l2/ethernet/gptp/ - subsys/net/l2/ieee802154/ @@ -2564,6 +2566,8 @@ Networking: - subsys/net/lib/config/ieee802154* - subsys/net/lib/lwm2m/ - subsys/net/lib/tls_credentials/ + - subsys/net/lib/dhcpv4/ + - tests/net/dhcpv4/ - tests/net/ieee802154/ - tests/net/wifi/ labels: @@ -2636,6 +2640,24 @@ Networking: tests: - net.coap +"Networking: DHCPv4": + status: maintained + maintainers: + - rlubos + - jukkar + collaborators: + - maass-hamburg + files: + - subsys/net/lib/dhcpv4/ + - samples/net/dhcpv4_client/ + - tests/net/dhcpv4/ + - include/zephyr/net/dhcpv4*.h + labels: + - "area: Networking" + tests: + - net.dhcpv4_client + - net.dhcpv4_server + "Networking: gPTP": status: maintained maintainers: From 8303b3dab0c439ef520631dc190f6ce582eec75e Mon Sep 17 00:00:00 2001 From: Gerson Fernando Budke Date: Thu, 7 Mar 2024 21:26:02 +0100 Subject: [PATCH 0590/2402] tests: i2s: sam: Add missing overlays Add missing overlays files to allow I2S tests pass on ci. Fixes #69936 Signed-off-by: Gerson Fernando Budke --- .../boards/sam_e70_xplained_same70q21b.overlay | 11 +++++++++++ .../i2s_api/boards/sam_v71_xult_samv71q21b.overlay | 11 +++++++++++ .../boards/sam_e70_xplained_same70q21.overlay | 11 +++++++++++ .../boards/sam_e70_xplained_same70q21b.overlay | 11 +++++++++++ .../i2s_speed/boards/sam_v71_xult_samv71q21.overlay | 11 +++++++++++ .../i2s_speed/boards/sam_v71_xult_samv71q21b.overlay | 11 +++++++++++ 6 files changed, 66 insertions(+) create mode 100644 tests/drivers/i2s/i2s_api/boards/sam_e70_xplained_same70q21b.overlay create mode 100644 tests/drivers/i2s/i2s_api/boards/sam_v71_xult_samv71q21b.overlay create mode 100644 tests/drivers/i2s/i2s_speed/boards/sam_e70_xplained_same70q21.overlay create mode 100644 tests/drivers/i2s/i2s_speed/boards/sam_e70_xplained_same70q21b.overlay create mode 100644 tests/drivers/i2s/i2s_speed/boards/sam_v71_xult_samv71q21.overlay create mode 100644 tests/drivers/i2s/i2s_speed/boards/sam_v71_xult_samv71q21b.overlay diff --git a/tests/drivers/i2s/i2s_api/boards/sam_e70_xplained_same70q21b.overlay b/tests/drivers/i2s/i2s_api/boards/sam_e70_xplained_same70q21b.overlay new file mode 100644 index 00000000000..f8a79e2c8ec --- /dev/null +++ b/tests/drivers/i2s/i2s_api/boards/sam_e70_xplained_same70q21b.overlay @@ -0,0 +1,11 @@ +/* i2s-node0 is the transmitter/receiver */ + +/ { + aliases { + i2s-node0 = &ssc; + }; +}; + +&xdmac { + status = "okay"; +}; diff --git a/tests/drivers/i2s/i2s_api/boards/sam_v71_xult_samv71q21b.overlay b/tests/drivers/i2s/i2s_api/boards/sam_v71_xult_samv71q21b.overlay new file mode 100644 index 00000000000..f8a79e2c8ec --- /dev/null +++ b/tests/drivers/i2s/i2s_api/boards/sam_v71_xult_samv71q21b.overlay @@ -0,0 +1,11 @@ +/* i2s-node0 is the transmitter/receiver */ + +/ { + aliases { + i2s-node0 = &ssc; + }; +}; + +&xdmac { + status = "okay"; +}; diff --git a/tests/drivers/i2s/i2s_speed/boards/sam_e70_xplained_same70q21.overlay b/tests/drivers/i2s/i2s_speed/boards/sam_e70_xplained_same70q21.overlay new file mode 100644 index 00000000000..f8a79e2c8ec --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/sam_e70_xplained_same70q21.overlay @@ -0,0 +1,11 @@ +/* i2s-node0 is the transmitter/receiver */ + +/ { + aliases { + i2s-node0 = &ssc; + }; +}; + +&xdmac { + status = "okay"; +}; diff --git a/tests/drivers/i2s/i2s_speed/boards/sam_e70_xplained_same70q21b.overlay b/tests/drivers/i2s/i2s_speed/boards/sam_e70_xplained_same70q21b.overlay new file mode 100644 index 00000000000..f8a79e2c8ec --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/sam_e70_xplained_same70q21b.overlay @@ -0,0 +1,11 @@ +/* i2s-node0 is the transmitter/receiver */ + +/ { + aliases { + i2s-node0 = &ssc; + }; +}; + +&xdmac { + status = "okay"; +}; diff --git a/tests/drivers/i2s/i2s_speed/boards/sam_v71_xult_samv71q21.overlay b/tests/drivers/i2s/i2s_speed/boards/sam_v71_xult_samv71q21.overlay new file mode 100644 index 00000000000..f8a79e2c8ec --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/sam_v71_xult_samv71q21.overlay @@ -0,0 +1,11 @@ +/* i2s-node0 is the transmitter/receiver */ + +/ { + aliases { + i2s-node0 = &ssc; + }; +}; + +&xdmac { + status = "okay"; +}; diff --git a/tests/drivers/i2s/i2s_speed/boards/sam_v71_xult_samv71q21b.overlay b/tests/drivers/i2s/i2s_speed/boards/sam_v71_xult_samv71q21b.overlay new file mode 100644 index 00000000000..f8a79e2c8ec --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/sam_v71_xult_samv71q21b.overlay @@ -0,0 +1,11 @@ +/* i2s-node0 is the transmitter/receiver */ + +/ { + aliases { + i2s-node0 = &ssc; + }; +}; + +&xdmac { + status = "okay"; +}; From 4cd0dee7ccb8784c649e86f05a9e1ce51e4c12a5 Mon Sep 17 00:00:00 2001 From: Lucas Denefle Date: Mon, 11 Mar 2024 14:26:08 +0000 Subject: [PATCH 0591/2402] modem: modem_cellular: increase fw_version size Fixes an issue introduced with `adcdf64a` Signed-off-by: Lucas Denefle --- drivers/modem/modem_cellular.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 15f10f11a52..8f483ef985f 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -31,7 +31,7 @@ LOG_MODULE_REGISTER(modem_cellular, CONFIG_MODEM_LOG_LEVEL); #define MODEM_CELLULAR_DATA_IMSI_LEN (22) #define MODEM_CELLULAR_DATA_ICCID_LEN (22) #define MODEM_CELLULAR_DATA_MANUFACTURER_LEN (64) -#define MODEM_CELLULAR_DATA_FW_VERSION_LEN (64) +#define MODEM_CELLULAR_DATA_FW_VERSION_LEN (65) /* Magic constants */ #define CSQ_RSSI_UNKNOWN (99) From c36b1039bee165b392c308a2c93b39c59bb0573f Mon Sep 17 00:00:00 2001 From: Lucas Denefle Date: Mon, 11 Mar 2024 14:27:21 +0000 Subject: [PATCH 0592/2402] modem: modem_cellular: increase manufacturer size Fixes an issue introduced with `ae951f5f` Signed-off-by: Lucas Denefle --- drivers/modem/modem_cellular.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 8f483ef985f..96250df392d 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -30,7 +30,7 @@ LOG_MODULE_REGISTER(modem_cellular, CONFIG_MODEM_LOG_LEVEL); #define MODEM_CELLULAR_DATA_MODEL_ID_LEN (64) #define MODEM_CELLULAR_DATA_IMSI_LEN (22) #define MODEM_CELLULAR_DATA_ICCID_LEN (22) -#define MODEM_CELLULAR_DATA_MANUFACTURER_LEN (64) +#define MODEM_CELLULAR_DATA_MANUFACTURER_LEN (65) #define MODEM_CELLULAR_DATA_FW_VERSION_LEN (65) /* Magic constants */ From fe4f002eefc45f44126a18a73c71d14789fff890 Mon Sep 17 00:00:00 2001 From: Lucas Denefle Date: Mon, 11 Mar 2024 14:28:29 +0000 Subject: [PATCH 0593/2402] modem: modem_cellular: increase model_id size Fixes an issue introduced with `08a51bae` Signed-off-by: Lucas Denefle --- drivers/modem/modem_cellular.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 96250df392d..728c4dec6ec 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -27,7 +27,7 @@ LOG_MODULE_REGISTER(modem_cellular, CONFIG_MODEM_LOG_LEVEL); K_MSEC(CONFIG_MODEM_CELLULAR_PERIODIC_SCRIPT_MS) #define MODEM_CELLULAR_DATA_IMEI_LEN (15) -#define MODEM_CELLULAR_DATA_MODEL_ID_LEN (64) +#define MODEM_CELLULAR_DATA_MODEL_ID_LEN (65) #define MODEM_CELLULAR_DATA_IMSI_LEN (22) #define MODEM_CELLULAR_DATA_ICCID_LEN (22) #define MODEM_CELLULAR_DATA_MANUFACTURER_LEN (65) From b287ad70f860170453ed8834cd2b151a2d30bb0a Mon Sep 17 00:00:00 2001 From: Lucas Denefle Date: Mon, 11 Mar 2024 14:29:52 +0000 Subject: [PATCH 0594/2402] modem: modem_cellular: increase imei size Fixes an issue introduced with `b668296a` Signed-off-by: Lucas Denefle --- drivers/modem/modem_cellular.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 728c4dec6ec..9ddd881b7a0 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -26,7 +26,7 @@ LOG_MODULE_REGISTER(modem_cellular, CONFIG_MODEM_LOG_LEVEL); #define MODEM_CELLULAR_PERIODIC_SCRIPT_TIMEOUT \ K_MSEC(CONFIG_MODEM_CELLULAR_PERIODIC_SCRIPT_MS) -#define MODEM_CELLULAR_DATA_IMEI_LEN (15) +#define MODEM_CELLULAR_DATA_IMEI_LEN (16) #define MODEM_CELLULAR_DATA_MODEL_ID_LEN (65) #define MODEM_CELLULAR_DATA_IMSI_LEN (22) #define MODEM_CELLULAR_DATA_ICCID_LEN (22) From 08aa504e661f5ebededed008b9320823f6387d42 Mon Sep 17 00:00:00 2001 From: Lucas Denefle Date: Mon, 11 Mar 2024 14:30:51 +0000 Subject: [PATCH 0595/2402] modem: modem_cellular: increase imsi size Fixes an issue introduced with `080d51bb` Signed-off-by: Lucas Denefle --- drivers/modem/modem_cellular.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 9ddd881b7a0..7c9e6728533 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -28,7 +28,7 @@ LOG_MODULE_REGISTER(modem_cellular, CONFIG_MODEM_LOG_LEVEL); #define MODEM_CELLULAR_DATA_IMEI_LEN (16) #define MODEM_CELLULAR_DATA_MODEL_ID_LEN (65) -#define MODEM_CELLULAR_DATA_IMSI_LEN (22) +#define MODEM_CELLULAR_DATA_IMSI_LEN (23) #define MODEM_CELLULAR_DATA_ICCID_LEN (22) #define MODEM_CELLULAR_DATA_MANUFACTURER_LEN (65) #define MODEM_CELLULAR_DATA_FW_VERSION_LEN (65) From 4809491b2683fedd92ccfdfd090fed66ac29b0df Mon Sep 17 00:00:00 2001 From: Eve Redero Date: Sun, 10 Mar 2024 18:19:58 +0100 Subject: [PATCH 0596/2402] boards: st: st25dv_mb1283_disco: add mb1283 board ST25DV discovery kit, including an LCD color screen. ST25 support not included. Signed-off-by: Eve Redero --- .../st/st25dv_mb1283_disco/Kconfig.defconfig | 12 ++ .../Kconfig.st25dv_mb1283_disco | 7 + boards/st/st25dv_mb1283_disco/board.cmake | 6 + boards/st/st25dv_mb1283_disco/board.yml | 5 + .../docs/img/st25dv_mb1283_disco.jpg | Bin 0 -> 51222 bytes boards/st/st25dv_mb1283_disco/docs/index.rst | 142 +++++++++++++++ .../st25dv_mb1283_disco.dts | 167 ++++++++++++++++++ .../st25dv_mb1283_disco.yaml | 16 ++ .../st25dv_mb1283_disco_defconfig | 21 +++ .../st25dv_mb1283_disco/support/openocd.cfg | 20 +++ .../demos/boards/st25dv_mb1283_disco.conf | 3 + .../demos/boards/st25dv_mb1283_disco.overlay | 16 ++ .../lvgl/boards/st25dv_mb1283_disco.conf | 3 + .../lvgl/boards/st25dv_mb1283_disco.overlay | 23 +++ 14 files changed, 441 insertions(+) create mode 100644 boards/st/st25dv_mb1283_disco/Kconfig.defconfig create mode 100644 boards/st/st25dv_mb1283_disco/Kconfig.st25dv_mb1283_disco create mode 100644 boards/st/st25dv_mb1283_disco/board.cmake create mode 100644 boards/st/st25dv_mb1283_disco/board.yml create mode 100644 boards/st/st25dv_mb1283_disco/docs/img/st25dv_mb1283_disco.jpg create mode 100644 boards/st/st25dv_mb1283_disco/docs/index.rst create mode 100644 boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.dts create mode 100644 boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.yaml create mode 100644 boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco_defconfig create mode 100644 boards/st/st25dv_mb1283_disco/support/openocd.cfg create mode 100644 samples/modules/lvgl/demos/boards/st25dv_mb1283_disco.conf create mode 100644 samples/modules/lvgl/demos/boards/st25dv_mb1283_disco.overlay create mode 100644 samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.conf create mode 100644 samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.overlay diff --git a/boards/st/st25dv_mb1283_disco/Kconfig.defconfig b/boards/st/st25dv_mb1283_disco/Kconfig.defconfig new file mode 100644 index 00000000000..7fd0efa7e0e --- /dev/null +++ b/boards/st/st25dv_mb1283_disco/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ST25DV DISCOVERY board configuration + +# Copyright (c) 2024 Eve Redero +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ST25DV_MB1283_DISCO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_ST25DV_MB1283_DISCO diff --git a/boards/st/st25dv_mb1283_disco/Kconfig.st25dv_mb1283_disco b/boards/st/st25dv_mb1283_disco/Kconfig.st25dv_mb1283_disco new file mode 100644 index 00000000000..8ad1f0b198c --- /dev/null +++ b/boards/st/st25dv_mb1283_disco/Kconfig.st25dv_mb1283_disco @@ -0,0 +1,7 @@ +# ST25DV DISCOVERY board configuration + +# Copyright (c) 2024 Eve Redero +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ST25DV_MB1283_DISCO + select SOC_STM32F405XX diff --git a/boards/st/st25dv_mb1283_disco/board.cmake b/boards/st/st25dv_mb1283_disco/board.cmake new file mode 100644 index 00000000000..16ce5db67ad --- /dev/null +++ b/boards/st/st25dv_mb1283_disco/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=STM32F405RG" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/st25dv_mb1283_disco/board.yml b/boards/st/st25dv_mb1283_disco/board.yml new file mode 100644 index 00000000000..8fc19fff61e --- /dev/null +++ b/boards/st/st25dv_mb1283_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: st25dv_mb1283_disco + vendor: st + socs: + - name: stm32f405xx diff --git a/boards/st/st25dv_mb1283_disco/docs/img/st25dv_mb1283_disco.jpg b/boards/st/st25dv_mb1283_disco/docs/img/st25dv_mb1283_disco.jpg new file mode 100644 index 0000000000000000000000000000000000000000..fa4906788c1710984773ffcd0e083d2b71c426dc GIT binary patch literal 51222 zcmeEtbx>SSl zt=fHm?pD2(KVILeQ|H#{>h9`W=j%S_JNM7hpAEosH6>Lg0165UK;`cP__G3#2Vh}f zU}B(SVPaxpV`Jgqk>KOu;^I-hASNWCp`xRup#lQwnR(gh8M&E&Kz30MZa#h?At5?8 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zKprxcU@bG4Jp~l{P05AW;%NL*btsrhMk}&{;C}oxXZ%;yXv_pUl^|HbBJKd+lOa&+ zSi*PG!!Lz42VadK^XJY#r>3ny3Ya~1UXL|7SBU-TdfcoF&*#;aUsrPSp#RO;|9{f$ dqXp_5oN@rTA9zdO{ePdT{r~72g#NSiUjU~!v2_3d literal 0 HcmV?d00001 diff --git a/boards/st/st25dv_mb1283_disco/docs/index.rst b/boards/st/st25dv_mb1283_disco/docs/index.rst new file mode 100644 index 00000000000..03acec44fc5 --- /dev/null +++ b/boards/st/st25dv_mb1283_disco/docs/index.rst @@ -0,0 +1,142 @@ +.. _st25dv_mb1283_disco_board: + +ST ST25DV Discovery, MB1283 version +################################### + +Overview +******** + +The ST25DV04K device is a dynamic NFC/RFID tag IC with a dual interface. It embeds a +4 Kbits EEPROM memory. It can be operated from an I2C interface, or by a 13.56 MHz +RFID reader, or by a NFC phone. The ST25DV04K Class 5 antenna daughter card, included +in the kit, can be replaced by Class 1 or Class 6 antennas. + +The ST25DV-DISCOVERY is a demonstration kit to evaluate the features and capabilities +of the ST25DV series. +It is based on the NFC ST25DV04K device embedded on a daughter card using a Class 5 antenna +and a STM32 processor driving a mother board. + +.. image:: img/st25dv_mb1283_disco.jpg + :align: center + :alt: ST25DV_MB1283_DISCO + +.. note:: + The ST25DV itself is not implemented yet. + +Hardware +******** + +The ST25DV Discovery kit provides the following hardware components: + +- Main board: ST25DV_Discovery_Mboard: + + - STM32F405VGT6 LQFP100 32-bit microcontroller, with 1 Mbyte Flash memory, 192 + 4 Kbytes SRAM. + - LCD color screen (320 x 200 pixels) + - Touch screen driver + - Different color LEDs (power, user, ST link) + - User push button + - Joystick for menu selection + - Reset button + - On board ST link for microcontroller firmware upgrade and debug + - ST link mini USB + - User micro USB + - USB micro or mini connector for board powering + - Demonstration edition (optional add-on module) with Bluetooth Low Energy module, + Wi-Fi ® module and JTAG 20 pin connector + +It exists in two variants, MB1283 and MB1285. + +- Antenna daughter board: ST25DV_Discovery_ANT_C5: + + - 40 mm x 24 mm, 13.56 MHz inductive antenna etched on the PCB + - ST25DV04K Dynamic NFC / RFID tag + - I 2 C interface connector + - Energy harvesting output (VOUT) with a 10nF capacitance filtering circuit + - GPO configurable as RF WIP/BUSY output, to indicate that an RF operation is ongoing + +The antenna board can be removed, and its 14-pin 0.254mm header connector used as an eval kit header. + +Connections and IOs +=================== + +Default Zephyr Peripheral Mapping +--------------------------------- + +- UART_6 TX/RX : PC6/PC7 (ST-Link Virtual Port Com) +- UART_2 TX/RX : PA2/PA3 (Available on J6 connector) +- I2C1 SCL/SDA : PB6/PB7 (Touchscreen STMPE811, interrupt pin PB5) +- SPI2 SCK/MOSI/CS : PB13/PC3/PB12 (LCD display FRD24048TP, reset pin PC1, DC pin PC0) +- SPI1 SCK/MISO/MOSI/CS : PA5/PA6/PA7/PA4 (External ST25DV connector J6) +- GPIO : PE8/PE9/PE10/PE11/PE12 (Joystick) +- LD1 : PC13 (Orange led) +- LD2 : PC4 (Yellow led) +- GPIO : PE15/PE7 (Available on external ST25DV connector J6) +- GPIO : PE14 (Available on J5 connector) + +Serial Port +=========== + +The Zephyr console output and shell are assigned to UART6, which is connected to the +onboard ST-LINK/V2 Virtual COM port interface. +Default communication settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``st25dv_mb1283_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +If programming fails, press the reset button (black) and release it while "west flash" is running. + +Flashing +======== + +ST25DV Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to ST25DV Discovery +-------------------------------------------- + +First, connect the ST25DV Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: st25dv_mb1283_disco + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! st25dv_mb1283_disco + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: st25dv_mb1283_disco + :goals: debug + + +.. _ST25DV-DISCO website: + https://www.st.com/en/nfc/st25dv-i2c-series-dynamic-nfc-tags.html + +.. _ST25DV datasheet: + https://www.st.com/resource/en/datasheet/st25dv04k.pdf + +.. _STM32F40xxx reference manual: + https://www.st.com/resource/en/reference_manual/rm0090-stm32f405415-stm32f407417-stm32f427437-and-stm32f429439-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.dts b/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.dts new file mode 100644 index 00000000000..0ed6e52a94c --- /dev/null +++ b/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.dts @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2024 Eve Redero + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "st/f4/stm32f405Xg.dtsi" +#include "st/f4/stm32f405vgtx-pinctrl.dtsi" +#include +#include + +/ { + model = "ST ST25DV Discovery Kit with MB1283"; + compatible = "st,st25dv_mb1283_disco", "st,stm32f405", "st,stm32f4"; + + chosen { + zephyr,console = &usart6; + zephyr,shell-uart = &usart6; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,display = &ili9341; + }; + + leds { + compatible = "gpio-leds"; + orange_led: led_1 { + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + }; + yellow_led: led_2 { + gpios = <&gpioc 4 GPIO_ACTIVE_HIGH>; + }; + }; + + buttons: gpio_keys { + compatible = "gpio-keys"; + blue_button: button_1 { + gpios = <&gpioc 14 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + sel_button: button_2 { + gpios = <&gpioe 8 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + left_button: button_3 { + gpios = <&gpioe 9 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + right_button: button_4 { + gpios = <&gpioe 11 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + up_button: button_5 { + gpios = <&gpioe 10 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + down_button: button_6 { + gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &orange_led; + sw0 = &blue_button; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + reset-gpios = <&gpioc 1 GPIO_ACTIVE_HIGH>; + dc-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; + spi-dev = <&spi2>; + #address-cells = <1>; + #size-cells = <0>; + write-only; + + ili9341: ili9341@0 { + compatible = "ilitek,ili9341"; + mipi-max-frequency = ; + reg = <0>; + pixel-format = ; + rotation = <0>; + width = <240>; + height = <320>; + duplex = <0x800>; + }; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <4>; + mul-n = <168>; + div-p = <2>; + div-q = <7>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <4>; + apb2-prescaler = <2>; +}; + +&usart6 { + pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, + <&rcc STM32_SRC_LSI RTC_SEL(2)>; + status = "okay"; +}; + +&spi2 { /* Max 20 Mbit/s */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spi2_mosi_pc3 &spi2_sck_pb13>; + cs-gpios = <&gpiob 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + pinctrl-names = "default"; + status = "okay"; +}; + + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; + + stmpe811: stmpe811@41 { + compatible = "st,stmpe811"; + status = "okay"; + reg = <0x41>; + int-gpios = <&gpiob 5 GPIO_ACTIVE_LOW>; + screen-width = <240>; + screen-height = <320>; + raw-x-min = <240>; + raw-y-min = <200>; + raw-x-max = <3680>; + raw-y-max = <3800>; + panel-driver-settling-time-us = <1000>; + touch-detect-delay-us = <5000>; + touch-average-control = <8>; + tracking-index = <127>; + }; +}; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_id_pa10 &usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.yaml b/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.yaml new file mode 100644 index 00000000000..b4dcf17f828 --- /dev/null +++ b/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.yaml @@ -0,0 +1,16 @@ +identifier: st25dv_mb1283_disco +name: ST ST25DV MB1283 Discovery +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 192 +flash: 1024 +supported: + - gpio + - i2c + - spi + - usb_device +vendor: st diff --git a/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco_defconfig b/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco_defconfig new file mode 100644 index 00000000000..e8b83db5fbb --- /dev/null +++ b/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco_defconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/st/st25dv_mb1283_disco/support/openocd.cfg b/boards/st/st25dv_mb1283_disco/support/openocd.cfg new file mode 100644 index 00000000000..72b4cd7492a --- /dev/null +++ b/boards/st/st25dv_mb1283_disco/support/openocd.cfg @@ -0,0 +1,20 @@ +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32f4x.cfg] + +adapter_khz 1000 + +reset_config srst_only + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/samples/modules/lvgl/demos/boards/st25dv_mb1283_disco.conf b/samples/modules/lvgl/demos/boards/st25dv_mb1283_disco.conf new file mode 100644 index 00000000000..e5f19abc888 --- /dev/null +++ b/samples/modules/lvgl/demos/boards/st25dv_mb1283_disco.conf @@ -0,0 +1,3 @@ +CONFIG_LV_COLOR_DEPTH_32=y +CONFIG_GPIO=y +CONFIG_INPUT=y diff --git a/samples/modules/lvgl/demos/boards/st25dv_mb1283_disco.overlay b/samples/modules/lvgl/demos/boards/st25dv_mb1283_disco.overlay new file mode 100644 index 00000000000..300ad9aeaa9 --- /dev/null +++ b/samples/modules/lvgl/demos/boards/st25dv_mb1283_disco.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024, Eve Redero + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&stmpe811>; + invert-y; + }; +}; diff --git a/samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.conf b/samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.conf new file mode 100644 index 00000000000..e5f19abc888 --- /dev/null +++ b/samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.conf @@ -0,0 +1,3 @@ +CONFIG_LV_COLOR_DEPTH_32=y +CONFIG_GPIO=y +CONFIG_INPUT=y diff --git a/samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.overlay b/samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.overlay new file mode 100644 index 00000000000..1be2cffc5a7 --- /dev/null +++ b/samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.overlay @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024, Eve Redero + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&stmpe811>; + invert-y; + }; + + keypad { + compatible = "zephyr,lvgl-keypad-input"; + input = <&buttons>; + input-codes = ; + lvgl-codes = ; + }; +}; From 8a38ff7161051eb1c610995f2b03ee64f4eaba4f Mon Sep 17 00:00:00 2001 From: Seppo Takalo Date: Mon, 11 Mar 2024 17:11:47 +0200 Subject: [PATCH 0597/2402] net: lwm2m: Handle empty URI On some content-types, it might be impossible to send strings with size of zero. Therefore empty URI should also allow cases where strlen() is zero. Signed-off-by: Seppo Takalo --- subsys/net/lib/lwm2m/CMakeLists.txt | 2 ++ subsys/net/lib/lwm2m/lwm2m_obj_firmware.c | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/subsys/net/lib/lwm2m/CMakeLists.txt b/subsys/net/lib/lwm2m/CMakeLists.txt index 7246ff70999..9971283cffd 100644 --- a/subsys/net/lib/lwm2m/CMakeLists.txt +++ b/subsys/net/lib/lwm2m/CMakeLists.txt @@ -2,6 +2,8 @@ zephyr_library() +zephyr_library_compile_definitions(_POSIX_C_SOURCE=200809L) + zephyr_include_directories(.) zephyr_library_sources( diff --git a/subsys/net/lib/lwm2m/lwm2m_obj_firmware.c b/subsys/net/lib/lwm2m/lwm2m_obj_firmware.c index 082197c83a5..ad313163548 100644 --- a/subsys/net/lib/lwm2m/lwm2m_obj_firmware.c +++ b/subsys/net/lib/lwm2m/lwm2m_obj_firmware.c @@ -305,13 +305,14 @@ static int package_uri_write_cb(uint16_t obj_inst_id, uint16_t res_id, #ifdef CONFIG_LWM2M_FIRMWARE_UPDATE_PULL_SUPPORT uint8_t state = lwm2m_firmware_get_update_state_inst(obj_inst_id); + bool empty_uri = data_len == 0 || strnlen(data, data_len) == 0; if (state == STATE_IDLE) { - if (data_len > 0) { + if (!empty_uri) { lwm2m_firmware_set_update_state_inst(obj_inst_id, STATE_DOWNLOADING); lwm2m_firmware_start_transfer(obj_inst_id, package_uri[obj_inst_id]); } - } else if (state == STATE_DOWNLOADED && data_len == 0U) { + } else if (state == STATE_DOWNLOADED && empty_uri) { /* reset to state idle and result default */ lwm2m_firmware_set_update_result_inst(obj_inst_id, RESULT_DEFAULT); } From 2f691ad8deb7f36ef5e07b9a866166b8b9f42832 Mon Sep 17 00:00:00 2001 From: Glenn Andrews Date: Sat, 9 Mar 2024 11:42:00 -0800 Subject: [PATCH 0598/2402] Driver Input: FT5336 reports touch pressed on no touches See https://github.com/zephyrproject-rtos/zephyr/discussions/69997 The driver thinks that when there are zero touches, the screen is pressed. This changes it so zero touches mean the screen is not pressed. Also, multi-touch is now considered a single touch, and the TOUCH_ID is checked so that only valid touches are registered. Signed-off-by: Glenn Andrews --- drivers/input/input_ft5336.c | 56 ++++++++++++++++++++++++------------ 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/drivers/input/input_ft5336.c b/drivers/input/input_ft5336.c index fea0aa26c11..c13276bd99d 100644 --- a/drivers/input/input_ft5336.c +++ b/drivers/input/input_ft5336.c @@ -13,6 +13,7 @@ #include #include #include +#include #include LOG_MODULE_REGISTER(ft5336, CONFIG_INPUT_LOG_LEVEL); @@ -35,7 +36,13 @@ LOG_MODULE_REGISTER(ft5336, CONFIG_INPUT_LOG_LEVEL); #define EVENT_CONTACT 0x02U #define EVENT_NONE 0x03U -/* REG_Pn_XH: Position */ +/* REG_Pn_YH: Touch ID */ +#define TOUCH_ID_POS 4U +#define TOUCH_ID_MSK 0x0FU + +#define TOUCH_ID_INVALID 0x0FU + +/* REG_Pn_XH and REG_Pn_YH: Position */ #define POSITION_H_MSK 0x0FU /* REG_G_PMODE: Power Consume Mode */ @@ -77,35 +84,46 @@ static int ft5336_process(const struct device *dev) int r; uint8_t points; uint8_t coords[4U]; - uint8_t event; uint16_t row, col; bool pressed; - /* obtain number of touch points (NOTE: multi-touch ignored) */ + /* obtain number of touch points */ r = i2c_reg_read_byte_dt(&config->bus, REG_TD_STATUS, &points); if (r < 0) { return r; } - points = (points >> TOUCH_POINTS_POS) & TOUCH_POINTS_MSK; - if (points != 0U && points != 1U) { - return 0; - } + points = FIELD_GET(TOUCH_POINTS_MSK, points); + if (points != 0) { + /* Any number of touches still counts as one touch. All touch + * points except the first are ignored. Obtain first point + * X, Y coordinates from: + * REG_P1_XH, REG_P1_XL, REG_P1_YH, REG_P1_YL. + * We ignore the Event Flag because Zephyr only cares about + * pressed / not pressed and not press down / lift up + */ + r = i2c_burst_read_dt(&config->bus, REG_P1_XH, coords, sizeof(coords)); + if (r < 0) { + return r; + } - /* obtain first point X, Y coordinates and event from: - * REG_P1_XH, REG_P1_XL, REG_P1_YH, REG_P1_YL. - */ - r = i2c_burst_read_dt(&config->bus, REG_P1_XH, coords, sizeof(coords)); - if (r < 0) { - return r; - } + row = ((coords[0] & POSITION_H_MSK) << 8U) | coords[1]; + col = ((coords[2] & POSITION_H_MSK) << 8U) | coords[3]; - event = (coords[0] >> EVENT_POS) & EVENT_MSK; - row = ((coords[0] & POSITION_H_MSK) << 8U) | coords[1]; - col = ((coords[2] & POSITION_H_MSK) << 8U) | coords[3]; - pressed = (event == EVENT_PRESS_DOWN) || (event == EVENT_CONTACT); + uint8_t touch_id = FIELD_GET(TOUCH_ID_MSK, coords[2]); - LOG_DBG("event: %d, row: %d, col: %d", event, row, col); + if (touch_id != TOUCH_ID_INVALID) { + pressed = true; + LOG_DBG("points: %d, touch_id: %d, row: %d, col: %d", + points, touch_id, row, col); + } else { + pressed = false; + LOG_WRN("bad TOUCH_ID: row: %d, col: %d", row, col); + } + } else { + /* no touch = no press */ + pressed = false; + } if (pressed) { input_report_abs(dev, INPUT_ABS_X, col, false, K_FOREVER); From 7679b8e6b4a7b92817a33c1738a2a18fb7adb783 Mon Sep 17 00:00:00 2001 From: Pratik Farkase Date: Tue, 5 Mar 2024 16:08:37 +0100 Subject: [PATCH 0599/2402] dts: riscv: starfive: add DT includes for JH7110 SOC These list of files add basic support for StarFive JH7110 SOC Device Tree includes for VisionFive2 board. Signed-off-by: Pratik Farkase --- dts/riscv/starfive/jh7110-clk.dtsi | 20 ++ dts/riscv/starfive/jh7110-visionfive-v2.dtsi | 211 +++++++++++++++++++ 2 files changed, 231 insertions(+) create mode 100644 dts/riscv/starfive/jh7110-clk.dtsi create mode 100644 dts/riscv/starfive/jh7110-visionfive-v2.dtsi diff --git a/dts/riscv/starfive/jh7110-clk.dtsi b/dts/riscv/starfive/jh7110-clk.dtsi new file mode 100644 index 00000000000..2c3ab26b12f --- /dev/null +++ b/dts/riscv/starfive/jh7110-clk.dtsi @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2024 Pratik Farkase + * Copyright (c) 2024 Sigma Connectivity WSI AB + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + apb2clk: apb2clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + }; + + uartclk: uartclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; +}; diff --git a/dts/riscv/starfive/jh7110-visionfive-v2.dtsi b/dts/riscv/starfive/jh7110-visionfive-v2.dtsi new file mode 100644 index 00000000000..2a42a5ebe72 --- /dev/null +++ b/dts/riscv/starfive/jh7110-visionfive-v2.dtsi @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2024 Pratik Farkase + * Copyright (c) 2024 Sigma Connectivity WSI AB + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "jh7110-clk.dtsi" +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "starfive,jh7110"; + model = "starfive,jh7110"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + S7_0: cpu@0 { + compatible = "sifive,s7", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv64imac_zicsr_zifencei"; + status = "okay"; + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_1: cpu@1 { + compatible = "sifive,u74", "riscv"; + device_type = "cpu"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x1>; + riscv,isa = "rv64imafdcg"; + tlb-spilt; + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + U74_2: cpu@2 { + compatible = "sifive,u74", "riscv"; + device_type = "cpu"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x2>; + riscv,isa = "rv64imafdcg"; + tlb-split; + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + U74_3: cpu@3 { + compatible = "sifive,u74", "riscv"; + device_type = "cpu"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x3>; + riscv,isa = "rv64imafdcg"; + tlb-split; + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + U74_4: cpu@4 { + compatible = "sifive,u74", "riscv"; + device_type = "cpu"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x4>; + riscv,isa = "rv64imafdcg"; + tlb-split; + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + ram0: memory@8000000 { + device_type = "memory"; + reg = <0x0 0x8000000 0x1 0x0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + #clock-cells = <1>; + compatible = "starfive,jh7110", "simple-bus"; + ranges; + + clint: timer@2000000 { + compatible = "starfive,jh7110-clint", "sifive,clint0"; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + }; + + ccache: cache-controller@2010000 { + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; + interrupt-parent = <&plic>; + interrupts = <1>, <3>, <4>, <2>; + reg = <0x0 0x2010000 0x0 0x4000>; + }; + + plic: interrupt-controller@c000000 { + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; + reg = <0x0 0x0c000000 0x0 0x04000000>; + riscv,max-priority = <7>; + riscv,ndev = <52>; + }; + + uart0: serial@10000000 { + compatible = "ns16550", "snps,dw-apb-uart"; + clocks = <&uartclk>, <&apb2clk>; + clock-names = "baudclk", "apb_pclk"; + clock-frequency = <100000000>; + current-speed = <115200>; + interrupt-parent = <&plic>; + interrupts = <32 1>; + reg = <0x0 0x10000000 0x0 0x10000>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@10010000 { + compatible = "ns16550", "snps,dw-apb-uart"; + clocks = <&uartclk>, <&apb2clk>; + clock-names = "baudclk", "apb_pclk"; + clock-frequency = <100000000>; + current-speed = <115200>; + interrupt-parent = <&plic>; + interrupts = <33 1>; + reg = <0x0 0x10010000 0x0 0x10000>; + reg-shift = <2>; + status = "disabled"; + }; + }; +}; From 2b4ce8b3bb8ee2851c0a07ff85d9798ca7b12aee Mon Sep 17 00:00:00 2001 From: Pratik Farkase Date: Tue, 5 Mar 2024 16:11:44 +0100 Subject: [PATCH 0600/2402] soc: starfive: jh71xx: add jh7110 soc support These list of files add Kconfig support for Starfive JH7110 SOC support. Signed-off-by: Pratik Farkase --- soc/starfive/jh71xx/Kconfig | 10 ++++++++++ soc/starfive/jh71xx/Kconfig.soc | 7 +++++++ soc/starfive/jh71xx/soc.yml | 1 + 3 files changed, 18 insertions(+) diff --git a/soc/starfive/jh71xx/Kconfig b/soc/starfive/jh71xx/Kconfig index 91ef208f9c1..b98817f20c8 100644 --- a/soc/starfive/jh71xx/Kconfig +++ b/soc/starfive/jh71xx/Kconfig @@ -15,3 +15,13 @@ config SOC_JH7100 select RISCV_ISA_EXT_C select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI + +config SOC_JH7110 + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/starfive/jh71xx/Kconfig.soc b/soc/starfive/jh71xx/Kconfig.soc index 48d6d506cc9..c0266b180d9 100644 --- a/soc/starfive/jh71xx/Kconfig.soc +++ b/soc/starfive/jh71xx/Kconfig.soc @@ -12,8 +12,15 @@ config SOC_JH7100 help Starfive JH7100 +config SOC_JH7110 + bool + select SOC_SERIES_STARFIVE_JH71XX + help + Starfive JH7110 + config SOC_SERIES default "starfive_jh71xx" if SOC_SERIES_STARFIVE_JH71XX config SOC default "jh7100" if SOC_JH7100 + default "jh7110" if SOC_JH7110 diff --git a/soc/starfive/jh71xx/soc.yml b/soc/starfive/jh71xx/soc.yml index 1d424c2f540..257d775033b 100644 --- a/soc/starfive/jh71xx/soc.yml +++ b/soc/starfive/jh71xx/soc.yml @@ -2,3 +2,4 @@ series: - name: starfive_jh71xx socs: - name: jh7100 + - name: jh7110 From 5e346f553db5e8a0d38345c4eab67a9588e5c1ad Mon Sep 17 00:00:00 2001 From: Pratik Farkase Date: Tue, 5 Mar 2024 16:14:06 +0100 Subject: [PATCH 0601/2402] boards: starfive: add visionfive2 board these list of patches add support the Starfive Visionfive2 SBC based on the JH7110 SoC. Board identifier is `visionfive2`. Signed-off-by: Kanak Shilledar Signed-off-by: Pratik Farkase --- boards/starfive/index.rst | 10 +++ boards/starfive/visionfive2/Kconfig.defconfig | 12 +++ .../starfive/visionfive2/Kconfig.visionfive2 | 5 ++ boards/starfive/visionfive2/board.yml | 8 ++ .../visionfive2/doc/img/visionfive2.webp | Bin 0 -> 65830 bytes boards/starfive/visionfive2/doc/index.rst | 78 ++++++++++++++++++ boards/starfive/visionfive2/visionfive2.dts | 30 +++++++ boards/starfive/visionfive2/visionfive2.yaml | 9 ++ .../visionfive2/visionfive2_defconfig | 10 +++ 9 files changed, 162 insertions(+) create mode 100644 boards/starfive/index.rst create mode 100644 boards/starfive/visionfive2/Kconfig.defconfig create mode 100644 boards/starfive/visionfive2/Kconfig.visionfive2 create mode 100644 boards/starfive/visionfive2/board.yml create mode 100644 boards/starfive/visionfive2/doc/img/visionfive2.webp create mode 100644 boards/starfive/visionfive2/doc/index.rst create mode 100644 boards/starfive/visionfive2/visionfive2.dts create mode 100644 boards/starfive/visionfive2/visionfive2.yaml create mode 100644 boards/starfive/visionfive2/visionfive2_defconfig diff --git a/boards/starfive/index.rst b/boards/starfive/index.rst new file mode 100644 index 00000000000..3cfcaba6a9c --- /dev/null +++ b/boards/starfive/index.rst @@ -0,0 +1,10 @@ +.. _boards-starfive: + +StarFive +######## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/starfive/visionfive2/Kconfig.defconfig b/boards/starfive/visionfive2/Kconfig.defconfig new file mode 100644 index 00000000000..6a51eec0894 --- /dev/null +++ b/boards/starfive/visionfive2/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Kanak Shilledar +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_VISIONFIVE2_JH7110 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +endif # BOARD_VISIONFIVE2_JH7110 diff --git a/boards/starfive/visionfive2/Kconfig.visionfive2 b/boards/starfive/visionfive2/Kconfig.visionfive2 new file mode 100644 index 00000000000..e451964f979 --- /dev/null +++ b/boards/starfive/visionfive2/Kconfig.visionfive2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Kanak Shilledar +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_VISIONFIVE2_JH7110 + select SOC_JH7110 diff --git a/boards/starfive/visionfive2/board.yml b/boards/starfive/visionfive2/board.yml new file mode 100644 index 00000000000..cc856efaa92 --- /dev/null +++ b/boards/starfive/visionfive2/board.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Kanak Shilledar +# SPDX-License-Identifier: Apache-2.0 + +board: + name: visionfive2 + vendor: starfive + socs: + - name: jh7110 diff --git a/boards/starfive/visionfive2/doc/img/visionfive2.webp b/boards/starfive/visionfive2/doc/img/visionfive2.webp new file mode 100644 index 0000000000000000000000000000000000000000..f5ca68cba0da8d4bf9b2497d8d93476b0d225ede GIT binary patch literal 65830 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zX{v9<&Ld33b@{?$zwodWif50JSU>=70y-TvG^7iu{BqSqNJw`Ms^eE;+J(=W1lTfm zZAE(o07t?w^R&ceuf_Odf+V?39`FD$Csb`=LxkJDYijQ0s>D2)ie3&DA z6x^9WlgI!Q9;1giT&ID5l>rrsB-GmRb+Tlx55~`NCkA%O#gm@vOmJaPJt6;a^NC`^ zxet!1`_ +is a jh7110 signature tool used to generate spl header information +and generate ``zephyr.bin.normal.out``. + +.. code-block:: console + + ./spl_tool -c -f build/zephyr/zephyr.bin + +This will create a new file ``build/zephyr/zephyr.bin.normal.out`` that can be flashed. +This step is necessary as zephyr binary must contain the SPL header info in order +to run it in M-Mode (Machine Mode) since S-Mode (Supervisor Mode) is +currently not supported. + +Flashing +======== + +.. note:: + The following steps use minicom for serial communication, feel free to use + any other serial terminal that supports xmodem based file transfers. + Thanks to @orangecms for his vf2-loader tool which makes the flashing process easier + +git clone the vf2-loader tool from https://github.com/orangecms/vf2-loader.git and +xmodem tool from https://github.com/orangecms/xmodem.rs.git side by side. + +VisionFive2 uses uart for flashing. Refer to +`VisionFive2 Recovery Quick Start Guide +`_ +to connect your serial-to-usb converter. Now power on the board and using +minicom access board's serial and press the reset switch on the board until you see CCCCCC... prompt + +Copy the ``zephyr.bin.normal.out`` from ``build/zephyr/zephyr.bin.normal.out`` +to previously git cloned vf2-loader/ directory and cd into it. +Flash the ``zephyr.bin.normal.out`` using this command: + +.. code-block:: console + + cargo run -- zephyr.bin.normal.out && minicom -D /dev/ttyUSB0 + +.. code-block:: text + + cargo run -- zephyr.bin.normal.out && minicom -D /dev/ttyUSB0 + Finished dev [unoptimized + debuginfo] target(s) in 0.03s + Running `target/debug/vf2-loader zephyr.bin.normal.out` + Welcome to minicom 2.7.1 + OPTIONS: I18n + Compiled on Dec 23 2019, 02:06:26. + Port /dev/ttyUSB0, 14:59:24 + Press CTRL-A Z for help on special keys + 6*** Booting Zephyr OS build v3.6.0-rc3 *** + Hello World! visionfive2 diff --git a/boards/starfive/visionfive2/visionfive2.dts b/boards/starfive/visionfive2/visionfive2.dts new file mode 100644 index 00000000000..48d7045e075 --- /dev/null +++ b/boards/starfive/visionfive2/visionfive2.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 Kanak Shilledar + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "starfive/jh7110-visionfive-v2.dtsi" + +/ { + model = "StarFive VisionFive V2"; + compatible = "starfive,visionfive-v2"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram0; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/starfive/visionfive2/visionfive2.yaml b/boards/starfive/visionfive2/visionfive2.yaml new file mode 100644 index 00000000000..a3288093496 --- /dev/null +++ b/boards/starfive/visionfive2/visionfive2.yaml @@ -0,0 +1,9 @@ +identifier: visionfive2 +name: Visionfive JH7110 (NON-SMP) +type: mcu +arch: riscv64 +toolchain: + - zephyr + - cross-compile +supported: + - uart diff --git a/boards/starfive/visionfive2/visionfive2_defconfig b/boards/starfive/visionfive2/visionfive2_defconfig new file mode 100644 index 00000000000..3d521f84c9a --- /dev/null +++ b/boards/starfive/visionfive2/visionfive2_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Zephyr Kernel Configuration +CONFIG_PRINTK=y +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y From 24a12802a5c64fab3d6e8908bc3a010dca06962c Mon Sep 17 00:00:00 2001 From: Kanak Shilledar Date: Wed, 6 Mar 2024 10:16:45 +0530 Subject: [PATCH 0602/2402] MAINTAINERS: list soc and board files in RISCV Arch added files for VisionFive 2 board and JH7110 SoC under the RISCV Arch area. Signed-off-by: Kanak Shilledar --- CODEOWNERS | 4 +++- MAINTAINERS.yml | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/CODEOWNERS b/CODEOWNERS index bd6bbf17e86..f34087d5484 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -40,6 +40,7 @@ /soc/riscv/riscv-privileged/andes_v5/ @cwshu @kevinwang821020 @jimmyzhe /soc/riscv/riscv-privileged/neorv32/ @henrikbrixandersen /soc/riscv/riscv-privileged/gd32vf103/ @soburi +/soc/starfive/jh71xx/ @pfarwsi /soc/riscv/riscv-privileged/niosv/ @sweeaun /boards/arm/96b_argonkey/ @avisconti /boards/arm/96b_avenger96/ @Mani-Sadhasivam @@ -118,6 +119,7 @@ /boards/riscv/niosv*/ @sweeaun /boards/riscv/sparkfun_red_v_things_plus/ @soburi /boards/riscv/stamp_c3/ @soburi +/boards/starfive/visionfive2/ @kanakshilledar @pfarwsi /boards/shields/atmel_rf2xx/ @nandojve /boards/shields/esp_8266/ @nandojve /boards/shields/inventek_eswifi/ @nandojve @@ -437,7 +439,7 @@ /dts/riscv/microchip/microchip-miv.dtsi @galak /dts/riscv/openisa/rv32m1* @dleach02 /dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda -/dts/riscv/starfive/ @rajnesh-kanwal +/dts/riscv/starfive/ @rajnesh-kanwal @pfarwsi /dts/riscv/andes/andes_v5* @cwshu @kevinwang821020 @jimmyzhe /dts/riscv/niosv/ @sweeaun /dts/arm/armv*m.dtsi @galak @ioannisg diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 8bd82e024c3..80b68128e2b 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2885,12 +2885,14 @@ RISCV arch: - boards/qemu/riscv*/ - boards/sifive/ - boards/sparkfun/red_v_things_plus/ + - boards/starfive/ - dts/bindings/riscv/ - dts/riscv/ - include/zephyr/arch/riscv/ - soc/common/riscv-privileged/ - soc/sifive/ - soc/riscv/ + - soc/starfive/ - tests/arch/riscv/ - doc/hardware/arch/risc-v.rst - drivers/interrupt_controller/intc_plic.c From 6f4cf5c73c18098ad352f9b40b7c6330a4b1adbc Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 7 Mar 2024 15:33:34 -0600 Subject: [PATCH 0603/2402] drivers: pinctrl: Add RW pinctrl driver Add pinctrl driver for NXP RW6XX chip. Signed-off-by: Declan Snyder Co-authored-by: Daniel DeGrasse --- drivers/pinctrl/CMakeLists.txt | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Kconfig.rw | 9 + drivers/pinctrl/pinctrl_rw_iomux.c | 174 ++++++++++++++++++ .../pinctrl/nxp,rw-iomux-pinctrl.yaml | 69 +++++++ 5 files changed, 254 insertions(+) create mode 100644 drivers/pinctrl/Kconfig.rw create mode 100644 drivers/pinctrl/pinctrl_rw_iomux.c create mode 100644 dts/bindings/pinctrl/nxp,rw-iomux-pinctrl.yaml diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 5a292054c08..4eb87c69909 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -34,6 +34,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_EMSDP pinctrl_emsdp.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC32XX pinctrl_ti_cc32xx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMAKER pinctrl_numaker.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_QUICKLOGIC_EOS_S3 pinctrl_eos_s3.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_RW pinctrl_rw_iomux.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCU pinctrl_imx_scu.c) add_subdirectory(renesas) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 2ef117cabbe..cc2c8800a5d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -62,6 +62,7 @@ source "drivers/pinctrl/Kconfig.emsdp" source "drivers/pinctrl/Kconfig.ti_cc32xx" source "drivers/pinctrl/Kconfig.numaker" source "drivers/pinctrl/Kconfig.eos_s3" +source "drivers/pinctrl/Kconfig.rw" source "drivers/pinctrl/Kconfig.zynqmp" rsource "renesas/Kconfig" diff --git a/drivers/pinctrl/Kconfig.rw b/drivers/pinctrl/Kconfig.rw new file mode 100644 index 00000000000..77d293f7b58 --- /dev/null +++ b/drivers/pinctrl/Kconfig.rw @@ -0,0 +1,9 @@ +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_RW + bool "Pin controller driver for NXP RW MCUs" + default y + depends on DT_HAS_NXP_RW_IOMUX_PINCTRL_ENABLED + help + Enable pin controller driver for NXP RW61x series MCUs diff --git a/drivers/pinctrl/pinctrl_rw_iomux.c b/drivers/pinctrl/pinctrl_rw_iomux.c new file mode 100644 index 00000000000..b3b586cac05 --- /dev/null +++ b/drivers/pinctrl/pinctrl_rw_iomux.c @@ -0,0 +1,174 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +static MCI_IO_MUX_Type *mci_iomux = + (MCI_IO_MUX_Type *)DT_REG_ADDR(DT_NODELABEL(pinctrl)); + +static SOCCIU_Type *soc_ctrl = + (SOCCIU_Type *)DT_REG_ADDR(DT_NODELABEL(soc_ctrl)); +static AON_SOC_CIU_Type *aon_soc_ciu = + (AON_SOC_CIU_Type *)DT_REG_ADDR(DT_NODELABEL(aon_soc_ctrl)); + +/* + * GPIO mux option definitions. Stored as a static array, because + * these mux options are needed to clear pin mux settings to + * a known good state before selecting a new alternate function. + */ +static uint64_t gpio_muxes[] = {IOMUX_GPIO_OPS}; + +/* + * Helper function to handle setting pin properties, + * such as pin bias and slew rate + */ +static void configure_pin_props(uint32_t pin_mux, uint8_t gpio_idx) +{ + uint32_t mask, set; + volatile uint32_t *pull_reg = &soc_ctrl->PAD_PU_PD_EN0; + volatile uint32_t *slew_reg = &soc_ctrl->SR_CONFIG0; + volatile uint32_t *sleep_force_en = &soc_ctrl->PAD_SLP_EN0; + volatile uint32_t *sleep_force_val = &soc_ctrl->PAD_SLP_VAL0; + + /* GPIO 22-27 use always on configuration registers */ + if (gpio_idx > 21 && gpio_idx < 28) { + pull_reg = (&aon_soc_ciu->PAD_PU_PD_EN1 - 1); + slew_reg = (&aon_soc_ciu->SR_CONFIG1 - 1); + sleep_force_en = &aon_soc_ciu->PAD_SLP_EN0; + sleep_force_val = &aon_soc_ciu->PAD_SLP_VAL0; + } + /* Calculate register offset for pull and slew regs. + * Use bit shifting as opposed to division + */ + pull_reg += (gpio_idx >> 4); + slew_reg += (gpio_idx >> 4); + sleep_force_en += (gpio_idx >> 5); + sleep_force_val += (gpio_idx >> 5); + /* Set pull-up/pull-down */ + /* Use mask and bitshift here as opposed to modulo and multiplication. + * equivalent to ((gpio_idx % 16) * 2) + */ + mask = 0x3 << ((gpio_idx & 0xF) << 1); + set = IOMUX_PAD_GET_PULL(pin_mux) << ((gpio_idx & 0xF) << 1); + *pull_reg = (*pull_reg & ~mask) | set; + + /* Set slew rate */ + set = IOMUX_PAD_GET_SLEW(pin_mux) << ((gpio_idx & 0xF) << 1); + *slew_reg = (*slew_reg & ~mask) | set; + + /* Set sleep force enable bit */ + mask = (0x1 << (gpio_idx & 0x1F)); + set = (IOMUX_PAD_GET_SLEEP_FORCE_EN(pin_mux) << (gpio_idx & 0x1F)); + *sleep_force_en = (*sleep_force_en & ~mask) | set; + set = (IOMUX_PAD_GET_SLEEP_FORCE_VAL(pin_mux) << (gpio_idx & 0x1F)); + *sleep_force_val = (*sleep_force_val & ~mask) | set; +} + +static void select_gpio_mode(uint8_t gpio_idx) +{ + uint64_t gpio_setting = gpio_muxes[gpio_idx]; + volatile uint32_t *flexcomm_reg = &mci_iomux->FC0; + + /* Clear flexcomm settings */ + flexcomm_reg += IOMUX_GET_FLEXCOMM_CLR_IDX(gpio_setting); + *flexcomm_reg &= ~IOMUX_GET_FLEXCOMM_CLR_MASK(gpio_setting); + /* Clear fsel settings */ + mci_iomux->FSEL &= ~IOMUX_GET_FSEL_CLR_MASK(gpio_setting); + /* Clear CTimer in/out, if required */ + if (IOMUX_GET_SCTIMER_IN_CLR_ENABLE(gpio_setting)) { + mci_iomux->C_TIMER_IN &= + ~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting)); + mci_iomux->C_TIMER_OUT &= + ~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting)); + } + /* Clear SCTimer in/out, if required */ + if (IOMUX_GET_SCTIMER_IN_CLR_ENABLE(gpio_setting)) { + mci_iomux->SC_TIMER &= + ~(0x1 << IOMUX_GET_SCTIMER_IN_CLR_OFFSET(gpio_setting)); + } + if (IOMUX_GET_SCTIMER_OUT_CLR_ENABLE(gpio_setting)) { + mci_iomux->SC_TIMER &= + ~(0x1 << (IOMUX_GET_SCTIMER_OUT_CLR_OFFSET(gpio_setting) + 16)); + } + /* Clear security gpio enable */ + mci_iomux->S_GPIO &= ~(0x1 << (gpio_idx - 32)); +} + + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, + uintptr_t reg) +{ + volatile uint32_t *flexcomm_reg; + volatile uint32_t *iomux_en_reg; + + for (uint8_t i = 0; i < pin_cnt; i++) { + flexcomm_reg = &mci_iomux->FC0; + iomux_en_reg = &soc_ctrl->MCI_IOMUX_EN0; + uint32_t pin_mux = pins[i]; + uint8_t gpio_idx = IOMUX_GET_GPIO_IDX(pin_mux); + uint8_t type = IOMUX_GET_TYPE(pin_mux); + /* + * Before selecting an alternate function, we must clear any + * conflicting pin configuration. We do this by resetting the + * pin to a gpio configuration, then selecting the alternate + * function. + */ + select_gpio_mode(gpio_idx); + switch (type) { + case IOMUX_FLEXCOMM: + flexcomm_reg += IOMUX_GET_FLEXCOMM_IDX(pin_mux); + *flexcomm_reg |= + (0x1 << IOMUX_GET_FLEXCOMM_BIT(pin_mux)); + break; + case IOMUX_FSEL: + mci_iomux->FSEL |= + (0x1 << IOMUX_GET_FSEL_BIT(pin_mux)); + break; + case IOMUX_CTIMER_IN: + mci_iomux->C_TIMER_IN |= + (0x1 << IOMUX_GET_CTIMER_BIT(pin_mux)); + break; + case IOMUX_CTIMER_OUT: + mci_iomux->C_TIMER_OUT |= + (0x1 << IOMUX_GET_CTIMER_BIT(pin_mux)); + break; + case IOMUX_SCTIMER_IN: + mci_iomux->SC_TIMER |= + (0x1 << IOMUX_GET_SCTIMER_BIT(pin_mux)); + break; + case IOMUX_SCTIMER_OUT: + mci_iomux->SC_TIMER |= + (0x1 << (IOMUX_GET_SCTIMER_BIT(pin_mux) + 16)); + break; + case IOMUX_SGPIO: + mci_iomux->S_GPIO |= (0x1 << (gpio_idx - 32)); + break; + case IOMUX_GPIO: + if (gpio_idx > 32) { + mci_iomux->GPIO_GRP1 |= (0x1 << (gpio_idx - 32)); + } else { + mci_iomux->GPIO_GRP0 |= (0x1 << gpio_idx); + } + break; + case IOMUX_AON: + /* No selection bits should be set */ + break; + default: + /* Unsupported type passed */ + return -ENOTSUP; + } + configure_pin_props(pin_mux, gpio_idx); + /* Now, enable pin controller access to this pin */ + if (gpio_idx > 21 && gpio_idx < 28) { + /* GPIO 22-27 use always on soc controller */ + iomux_en_reg = &aon_soc_ciu->MCI_IOMUX_EN0; + } + iomux_en_reg += (gpio_idx >> 5); + *iomux_en_reg |= (0x1 << (gpio_idx & 0x1F)); + } + return 0; +} diff --git a/dts/bindings/pinctrl/nxp,rw-iomux-pinctrl.yaml b/dts/bindings/pinctrl/nxp,rw-iomux-pinctrl.yaml new file mode 100644 index 00000000000..3264c405040 --- /dev/null +++ b/dts/bindings/pinctrl/nxp,rw-iomux-pinctrl.yaml @@ -0,0 +1,69 @@ +# Copyright 2022, NXP +# SPDX-License-Identifier: Apache-2.0 + +description: | + RW61x pin control node. This node defines pin configurations in pin + groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each + group within the pin configuration defines a peripheral's pin configuration. + Each numbered subgroup represents pins with shared configuration for that + peripheral. The 'pinmux' property of each group selects the pins to be + configured with these properties. For example, here is a configuration + for FLEXCOMM0 pins: + + pinmux_flexcomm0_usart: pinmux_flexcomm0_usart { + group0 { + pinmux = , + ; + slew-rate = "normal"; + }; + }; + + If only the required properties are supplied, the pin will be configured + as normal drive strength and no pull. This corresponds to the following + pin settings: + PAD_PU_PD_ENx = (0x0 << pin_index) + SR_CONFIGx = (0x2 << pin_index) + + Note + + Note the inherited pinctrl properties defined below have the following effects: + bias-pull-up: PAD_PU_PD_ENx= (0x1 << pin_index) + bias-pull-down: PAD_PU_PD_ENx= (0x10 << pin_index) + +compatible: "nxp,rw-iomux-pinctrl" + +include: + - name: base.yaml + +child-binding: + description: iMX RW IOMUX pin controller pin group + child-binding: + description: | + iMX RW IOMUX pin controller pin configuration node + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-pull-up + - bias-pull-down + properties: + pinmux: + required: true + type: array + description: | + Pin mux selection for this group. See the SOC level pinctrl header + file in NXP's HAL for a defined list of these options. + slew-rate: + required: true + type: string + enum: + - "slow" + - "normal" + - "fast" + - "ultra" + description: | + Pin output slew rate. Sets the GPIOxx_SR field in the SR_CONFIGx + register. + 0 - slow slew rate + 1 - normal slew rate + 2 - fast slew rate + 3 - fastest slew rate (ultra) From 17ab3d5deb5b7d1f0d0c4d24754ac6e4dfb7e001 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 7 Mar 2024 17:16:01 -0600 Subject: [PATCH 0604/2402] drivers: gpio: mcux_lpc: Support MCI_IO_MUX Support MCI_IO_MUX pinctrl in LPC GPIO driver Signed-off-by: Declan Snyder Co-authored-by: Daniel DeGrasse --- drivers/gpio/gpio_mcux_lpc.c | 47 ++++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio_mcux_lpc.c b/drivers/gpio/gpio_mcux_lpc.c index dae2c92adcb..8895a984dc2 100644 --- a/drivers/gpio/gpio_mcux_lpc.c +++ b/drivers/gpio/gpio_mcux_lpc.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2020,2023 NXP + * Copyright 2017-2020,2022-2023 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -26,6 +26,9 @@ #endif #include #include +#ifdef MCI_IO_MUX +#include +#endif /* Interrupt sources, matching int-source enum in DTS binding definition */ #define INT_SOURCE_PINT 0 @@ -40,8 +43,12 @@ struct gpio_mcux_lpc_config { uint8_t int_source; #ifdef IOPCTL IOPCTL_Type *pinmux_base; -#else +#endif +#ifdef IOCON IOCON_Type *pinmux_base; +#endif +#ifdef MCI_IO_MUX + MCI_IO_MUX_Type * pinmux_base; #endif uint32_t port_no; }; @@ -81,8 +88,8 @@ static int gpio_mcux_lpc_configure(const struct device *dev, gpio_pin_t pin, } /* Select GPIO mux for this pin (func 0 is always GPIO) */ *pinconfig &= ~(IOPCTL_PIO_FSEL_MASK); - -#else /* LPC SOCs */ +#endif +#ifdef IOCON /* LPC SOCs */ volatile uint32_t *pinconfig; IOCON_Type *pinmux_base; @@ -101,6 +108,23 @@ static int gpio_mcux_lpc_configure(const struct device *dev, gpio_pin_t pin, /* Select GPIO mux for this pin (func 0 is always GPIO) */ *pinconfig &= ~(IOCON_PIO_FUNC_MASK); #endif +#ifdef MCI_IO_MUX /* RW61x SOCs */ + /* Construct a pin control state, and apply it directly. */ + pinctrl_soc_pin_t pin_cfg; + + if (config->port_no == 1) { + pin_cfg = IOMUX_GPIO_IDX(pin + 32) | IOMUX_TYPE(IOMUX_GPIO); + } else { + pin_cfg = IOMUX_GPIO_IDX(pin) | IOMUX_TYPE(IOMUX_GPIO); + } + /* Add pull up flags, if required */ + if ((flags & GPIO_PULL_UP) != 0) { + pin_cfg |= IOMUX_PAD_PULL(0x1); + } else if ((flags & GPIO_PULL_DOWN) != 0) { + pin_cfg |= IOMUX_PAD_PULL(0x2); + } + pinctrl_configure_pins(&pin_cfg, 1, 0); +#endif if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) { #ifdef IOPCTL /* RT600 and RT500 series */ @@ -110,7 +134,8 @@ static int gpio_mcux_lpc_configure(const struct device *dev, gpio_pin_t pin, } else if ((flags & GPIO_PULL_DOWN) != 0) { *pinconfig &= ~(IOPCTL_PIO_PULLUP_EN); } -#else /* LPC SOCs */ +#endif +#ifdef IOCON /* LPC SOCs */ *pinconfig &= ~(IOCON_PIO_MODE_PULLUP|IOCON_PIO_MODE_PULLDOWN); if ((flags & GPIO_PULL_UP) != 0) { @@ -122,8 +147,12 @@ static int gpio_mcux_lpc_configure(const struct device *dev, gpio_pin_t pin, } else { #ifdef IOPCTL /* RT600 and RT500 series */ *pinconfig &= ~IOPCTL_PIO_PUPD_EN; -#else /* LPC SOCs */ +#endif +#ifdef IOCON /* LPC SOCs */ *pinconfig &= ~(IOCON_PIO_MODE_PULLUP|IOCON_PIO_MODE_PULLDOWN); +#endif +#ifdef MCI_IO_MUX + #endif } @@ -400,9 +429,13 @@ static const struct gpio_driver_api gpio_mcux_lpc_driver_api = { #ifdef IOPCTL #define PINMUX_BASE IOPCTL -#else +#endif +#ifdef IOCON #define PINMUX_BASE IOCON #endif +#ifdef MCI_IO_MUX +#define PINMUX_BASE MCI_IO_MUX +#endif #define GPIO_MCUX_LPC_MODULE_IRQ_CONNECT(inst) \ do { \ From 52c4aeb7cb1e52e956380710f8dbbaf473b312c4 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 7 Mar 2024 15:47:57 -0600 Subject: [PATCH 0605/2402] dts: nxp: Add RW6XX Devicetree Add SOC devicetree for RW6XX Signed-off-by: Declan Snyder --- dts/arm/nxp/nxp_rw6xx.dtsi | 27 +++ dts/arm/nxp/nxp_rw6xx_common.dtsi | 161 ++++++++++++++++++ dts/arm/nxp/nxp_rw6xx_ns.dtsi | 27 +++ .../dt-bindings/clock/mcux_lpc_syscon_clock.h | 1 + 4 files changed, 216 insertions(+) create mode 100644 dts/arm/nxp/nxp_rw6xx.dtsi create mode 100644 dts/arm/nxp/nxp_rw6xx_common.dtsi create mode 100644 dts/arm/nxp/nxp_rw6xx_ns.dtsi diff --git a/dts/arm/nxp/nxp_rw6xx.dtsi b/dts/arm/nxp/nxp_rw6xx.dtsi new file mode 100644 index 00000000000..3f9bd258b76 --- /dev/null +++ b/dts/arm/nxp/nxp_rw6xx.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram: sram@30000000 { + ranges = <0x20000000 0x30000000 0x130000 + 0x00000000 0x10000000 0x130000>; + }; + + peripheral: peripheral@50000000 { + ranges = <0x0 0x50000000 0x10000000>; + }; + + flexspi: spi@134000 { + reg = <0x50134000 0x1000>, <0x18000000 DT_SIZE_M(128)>; + }; + }; +}; + +#include "nxp_rw6xx_common.dtsi" diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi new file mode 100644 index 00000000000..e2ab6c8f05b --- /dev/null +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -0,0 +1,161 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-m33f"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; +}; + +&sram { + #address-cells = <1>; + #size-cells = <1>; + + sram_data: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20040000 DT_SIZE_K(960)>; + }; + + sram_code: memory@0 { + compatible = "mmio-sram"; + reg = <0x00000000 DT_SIZE_K(256)>; + }; +}; + +&peripheral { + #address-cells = <1>; + #size-cells = <1>; + + clkctl0: clkctl@1000 { + compatible = "nxp,lpc-syscon"; + reg = <0x1000 0x1000>; + #clock-cells = <1>; + }; + + pinctrl: mci_iomux@4000 { + compatible = "nxp,rw-iomux-pinctrl"; + reg = <0x4000 0x1000>; + status = "okay"; + }; + + clkctl1: clkctl@21000 { + compatible = "nxp,lpc-syscon"; + reg = <0x21000 0x1000>; + #clock-cells = <1>; + }; + + hsgpio0: hsgpio@0 { + compatible = "nxp,lpc-gpio"; + reg = <0x100000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + port = <0>; + int-source = "pint"; + }; + + hsgpio1: hsgpio@1 { + compatible = "nxp,lpc-gpio"; + reg = <0x100000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + port = <1>; + int-source = "pint"; + }; + + flexcomm0: flexcomm@106000 { + compatible = "nxp,lpc-flexcomm"; + reg = <0x106000 0x1000>; + interrupts = <14 0>; + clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>; + status = "disabled"; + }; + + flexcomm1: flexcomm@107000 { + compatible = "nxp,lpc-flexcomm"; + reg = <0x107000 0x1000>; + interrupts = <15 0>; + clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>; + status = "disabled"; + }; + + flexcomm2: flexcomm@108000 { + compatible = "nxp,lpc-flexcomm"; + reg = <0x108000 0x1000>; + interrupts = <16 0>; + clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>; + status = "disabled"; + }; + + flexcomm3: flexcomm@109000 { + compatible = "nxp,lpc-flexcomm"; + reg = <0x109000 0x1000>; + interrupts = <17 0>; + clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>; + status = "disabled"; + }; + + flexcomm14: flexcom@126000 { + compatible = "nxp,lpc-flexcomm"; + reg = <0x126000 0x2000>; + interrupts = <20 0>; + clocks = <&clkctl1 MCUX_FLEXCOMM14_CLK>; + status = "disabled"; + }; + + aon_soc_ctrl: aon_soc_ctrl@5000800 { + compatible = "nxp,rw-soc-ctrl"; + reg = <0x5000800 0x1000>; + status = "okay"; + }; + + soc_ctrl: soc_ctrl@5001000 { + compatible = "nxp,rw-soc-ctrl"; + reg = <0x5001000 0x1000>; + status = "okay"; + }; + + pint: pint@25000 { + compatible = "nxp,pint"; + reg = <0x25000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + interrupts = <4 2>, <5 2>, <6 2>, <7 2>, + <35 2>, <36 2>, <37 2>, <38 2>; + num-lines = <8>; + num-inputs = <64>; + }; +}; + +&flexspi { + compatible = "nxp,imx-flexspi"; + status = "disabled"; + interrupts = <42 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkctl1 MCUX_FLEXSPI_CLK>; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/nxp/nxp_rw6xx_ns.dtsi b/dts/arm/nxp/nxp_rw6xx_ns.dtsi new file mode 100644 index 00000000000..a02dac132b3 --- /dev/null +++ b/dts/arm/nxp/nxp_rw6xx_ns.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram: sram@20000000 { + ranges = <0x20000000 0x20000000 0x130000 + 0x00000000 0x00000000 0x130000>; + }; + + peripheral: peripheral@40000000 { + ranges = <0x0 0x40000000 0x10000000>; + }; + + flexspi: spi@134000 { + reg = <0x40134000 0x1000>, <0x08000000 DT_SIZE_M(128)>; + }; + }; +}; + +#include "nxp_rw6xx_common.dtsi" diff --git a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h index 404ba96de96..addf2a349fd 100644 --- a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -22,6 +22,7 @@ #define MCUX_FLEXCOMM12_CLK 12 #define MCUX_FLEXCOMM13_CLK 13 #define MCUX_HS_SPI_CLK 14 +#define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK #define MCUX_PMIC_I2C_CLK 15 #define MCUX_HS_SPI1_CLK 16 From 5f53afca0a42ed561ea08eb4334b63016f0059d2 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 7 Mar 2024 16:26:09 -0600 Subject: [PATCH 0606/2402] soc: nxp: Add RW SOC Family Add SOC definition for NXP RW Family Signed-off-by: Declan Snyder --- MAINTAINERS.yml | 1 + .../clock_control/clock_control_mcux_syscon.c | 3 + modules/Kconfig.mcux | 2 +- soc/nxp/rw/CMakeLists.txt | 13 + soc/nxp/rw/Kconfig | 87 +++ soc/nxp/rw/Kconfig.defconfig | 68 +++ soc/nxp/rw/Kconfig.soc | 60 ++ soc/nxp/rw/boot_header.ld | 10 + soc/nxp/rw/flexspi_clock_setup.c | 24 + soc/nxp/rw/flexspi_clock_setup.h | 13 + soc/nxp/rw/pinctrl_defs.h | 555 ++++++++++++++++++ soc/nxp/rw/pinctrl_soc.h | 46 ++ soc/nxp/rw/soc.c | 189 ++++++ soc/nxp/rw/soc.h | 24 + soc/nxp/rw/soc.yml | 7 + west.yml | 2 +- 16 files changed, 1102 insertions(+), 2 deletions(-) create mode 100644 soc/nxp/rw/CMakeLists.txt create mode 100644 soc/nxp/rw/Kconfig create mode 100644 soc/nxp/rw/Kconfig.defconfig create mode 100644 soc/nxp/rw/Kconfig.soc create mode 100644 soc/nxp/rw/boot_header.ld create mode 100644 soc/nxp/rw/flexspi_clock_setup.c create mode 100644 soc/nxp/rw/flexspi_clock_setup.h create mode 100644 soc/nxp/rw/pinctrl_defs.h create mode 100644 soc/nxp/rw/pinctrl_soc.h create mode 100644 soc/nxp/rw/soc.c create mode 100644 soc/nxp/rw/soc.h create mode 100644 soc/nxp/rw/soc.yml diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 80b68128e2b..2b44108f2a3 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3332,6 +3332,7 @@ NXP Platforms (MCU): - soc/nxp/imxrt/ - soc/nxp/kinetis/ - soc/nxp/lpc/ + - soc/nxp/rw/ - dts/arm/nxp/ - samples/boards/nxp*/ files-regex-exclude: diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index 5386b41ed04..61eb0481abf 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -158,9 +158,12 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( #if defined(CONFIG_PWM_MCUX_SCTIMER) case MCUX_SCTIMER_CLK: #endif + +#ifndef CONFIG_SOC_SERIES_RW6XX case MCUX_BUS_CLK: *rate = CLOCK_GetFreq(kCLOCK_BusClk); break; +#endif #if defined(CONFIG_I3C_MCUX) case MCUX_I3C_CLK: diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux index 21658c1ebd0..c1760ffd649 100644 --- a/modules/Kconfig.mcux +++ b/modules/Kconfig.mcux @@ -6,7 +6,7 @@ config HAS_MCUX bool depends on SOC_FAMILY_KINETIS || SOC_FAMILY_NXP_IMX || SOC_FAMILY_LPC || \ - SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT + SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT || SOC_FAMILY_NXP_RW if HAS_MCUX config MCUX_CORE_SUFFIX diff --git a/soc/nxp/rw/CMakeLists.txt b/soc/nxp/rw/CMakeLists.txt new file mode 100644 index 00000000000..d4c7cd7af4d --- /dev/null +++ b/soc/nxp/rw/CMakeLists.txt @@ -0,0 +1,13 @@ +# Copyright 2022-2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + flexspi_clock_setup.c + ) + +zephyr_linker_sources_ifdef(CONFIG_NXP_RW6XX_BOOT_HEADER + ROM_START SORT_KEY 0 boot_header.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/rw/Kconfig b/soc/nxp/rw/Kconfig new file mode 100644 index 00000000000..563b9671dba --- /dev/null +++ b/soc/nxp/rw/Kconfig @@ -0,0 +1,87 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RW6XX + select ARM + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select CLOCK_CONTROL + select PLATFORM_SPECIFIC_INIT + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select HAS_MCUX_OS_TIMER + select ARM_TRUSTZONE_M + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_MCUX + select HAS_MCUX_FLEXCOMM + select INIT_SYS_PLL + select HAS_MCUX_CACHE + +if SOC_SERIES_RW6XX + +config INIT_SYS_PLL + bool "Initialize SYS PLL" + +menuconfig NXP_RW6XX_BOOT_HEADER + bool "Create boot header" + default y + help + Create data structures required by the boot ROM to boot the + application from an external flash device. + +if NXP_RW6XX_BOOT_HEADER + +choice BOOT_DEVICE + prompt "Boot device selection" + default BOOT_FLEXSPI_NOR + +config BOOT_FLEXSPI_NOR + bool "FlexSPI serial NOR" + +endchoice + +config FLASH_CONFIG_OFFSET + hex "Flash config data offset" + default 0x400 + help + The flash config offset provides the boot ROM with the on-board + flash type and parameters. The boot ROM requires a fixed flash conifg + offset for FlexSPI device. + +config IMAGE_VECTOR_TABLE_OFFSET + hex "Image vector table offset" + default 0x1000 + help + The Image Vector Table (IVT) provides the boot ROM with pointers to + the application entry point and device configuration data. The boot + ROM requires a fixed IVT offset for each type of boot device. + +# Used for default value in FLASH_MCUX_FLEXSPI_XIP +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi +# Macros to shorten Kconfig definitions +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +config FLASH_MCUX_FLEXSPI_XIP + bool "MCUX FlexSPI flash access with xip" + default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) + select XIP + help + Allows for the soc to safely initialize the clocks for the + FlexSpi when planning to execute code in FlexSpi Memory. + +config NXP_RW_ROM_RAMLOADER + depends on !FLASH_MCUX_FLEXSPI_XIP + # Required so that debugger will load image to correct offset + select BUILD_OUTPUT_HEX + bool "Create output image that RW ROM can load from FlexSPI to ram" + help + Builds an output image that the RW BootROM can load from the + FlexSPI boot device into RAM region. The image will be loaded + from FLEXSPI into the region specified by `zephyr,flash` node. + +endif # NXP_RW6XX_BOOT_HEADER + +endif # SOC_SERIES_RW6XX diff --git a/soc/nxp/rw/Kconfig.defconfig b/soc/nxp/rw/Kconfig.defconfig new file mode 100644 index 00000000000..e17dffe663d --- /dev/null +++ b/soc/nxp/rw/Kconfig.defconfig @@ -0,0 +1,68 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RW6XX + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + default 0x1300 if NXP_RW6XX_BOOT_HEADER + +config NUM_IRQS + default 129 +if CORTEX_M_SYSTICK + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 260000000 + +endif # CORTEX_M_SYSTICK + +# The base address is determined from the zephyr,flash node with the following +# precedence: +# FlexSPI base address (if flash node is on a FlexSPI bus) +# node reg property (used for memory regions such as SRAM) + +# Workaround for not being able to have commas in macro arguments + +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi + +# Macros to shorten Kconfig definitions +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +# The RW6xx has no internal flash. If the flash node has a size property, +# use that over the reg property. This is used for the external flash +# present on the board. Otherwise, fallback to the reg property +config FLASH_SIZE + default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ + if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +if NXP_RW_ROM_RAMLOADER + +FLASH_BASE := $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) +FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1) +config BUILD_OUTPUT_ADJUST_LMA + default "$(FLEXSPI_BASE) - $(FLASH_BASE)" + +endif # NXP_RW_ROM_RAMLOADER + +if FLASH_MCUX_FLEXSPI_XIP + +# Avoid RWW hazards by defaulting logging to disabled +choice FLASH_LOG_LEVEL_CHOICE + default FLASH_LOG_LEVEL_OFF +endchoice + +choice MEMC_LOG_LEVEL_CHOICE + default MEMC_LOG_LEVEL_OFF +endchoice + +endif # FLASH_MCUX_FLEXSPI_XIP + +endif # SOC_SERIES_RW6XX diff --git a/soc/nxp/rw/Kconfig.soc b/soc/nxp/rw/Kconfig.soc new file mode 100644 index 00000000000..115b7721f9a --- /dev/null +++ b/soc/nxp/rw/Kconfig.soc @@ -0,0 +1,60 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_RW + bool + +config SOC_FAMILY + default "nxp_rw" if SOC_FAMILY_NXP_RW + +config SOC_SERIES_RW6XX + bool + select SOC_FAMILY_NXP_RW + +config SOC_SERIES + default "rw6xx" if SOC_SERIES_RW6XX + +config SOC_RW610 + bool + select SOC_SERIES_RW6XX + +config SOC_RW612 + bool + select SOC_SERIES_RW6XX + +config SOC + default "rw610" if SOC_RW610 + default "rw612" if SOC_RW612 + +config SOC_PART_NUMBER_RW612ETA1I + bool + select SOC_RW612 + +config SOC_PART_NUMBER_RW612HNA1I + bool + select SOC_RW612 + +config SOC_PART_NUMBER_RW612UKA1I + bool + select SOC_RW612 + +config SOC_PART_NUMBER_RW610ETA1I + bool + select SOC_RW610 + +config SOC_PART_NUMBER_RW610HNA1I + bool + select SOC_RW610 + +config SOC_PART_NUMBER_RW610UKA1I + bool + select SOC_RW610 + +config SOC_PART_NUMBER + string + default "RW612ETA1I" if SOC_PART_NUMBER_RW612ETA1I + default "RW612HNA1I" if SOC_PART_NUMBER_RW612HNA1I + default "RW612UKA1I" if SOC_PART_NUMBER_RW612UKA1I + default "RW610ETA1I" if SOC_PART_NUMBER_RW610ETA1I + default "RW610HNA1I" if SOC_PART_NUMBER_RW610HNA1I + default "RW610UKA1I" if SOC_PART_NUMBER_RW610UKA1I diff --git a/soc/nxp/rw/boot_header.ld b/soc/nxp/rw/boot_header.ld new file mode 100644 index 00000000000..ee0be5b4753 --- /dev/null +++ b/soc/nxp/rw/boot_header.ld @@ -0,0 +1,10 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +. = CONFIG_FLASH_CONFIG_OFFSET; +KEEP(*(.flash_conf)) +. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; +KEEP(*(.boot_hdr.ivt)) diff --git a/soc/nxp/rw/flexspi_clock_setup.c b/soc/nxp/rw/flexspi_clock_setup.c new file mode 100644 index 00000000000..18c74954bd3 --- /dev/null +++ b/soc/nxp/rw/flexspi_clock_setup.c @@ -0,0 +1,24 @@ +/* + * Copyright 2022-2023 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "flexspi_clock_setup.h" +#ifdef CONFIG_MEMC +#include +#include +#endif + +/** + * @brief Set flexspi clock + */ +void __ramfunc set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider) +{ + CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src); + CLKCTL0->FLEXSPIFCLKDIV |= + CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */ + CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1); + while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK) { + } +} diff --git a/soc/nxp/rw/flexspi_clock_setup.h b/soc/nxp/rw/flexspi_clock_setup.h new file mode 100644 index 00000000000..0f4f58d4aae --- /dev/null +++ b/soc/nxp/rw/flexspi_clock_setup.h @@ -0,0 +1,13 @@ +/* + * Copyright 2022-2023 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _FLEXSPI_CLOCK_SETUP_H_ +#define _FLEXSPI_CLOCK_SETUP_H_ + +#include "fsl_common.h" + +void set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider); + +#endif /* _FLEXSPI_CLOCK_SETUP_H_ */ diff --git a/soc/nxp/rw/pinctrl_defs.h b/soc/nxp/rw/pinctrl_defs.h new file mode 100644 index 00000000000..fac97912722 --- /dev/null +++ b/soc/nxp/rw/pinctrl_defs.h @@ -0,0 +1,555 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_DEFS_H_ +#define ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_DEFS_H_ + +/* Internal macros to pack and extract pin configuration data. */ +/* GPIO configuration packing macros */ +#define IOMUX_OFFSET_ENABLE(offset, enable, shift) \ + ((((offset) << 1) | (enable & 0x1)) << shift) +#define IOMUX_SCTIMER_OUT_CLR(offset, enable) \ + IOMUX_OFFSET_ENABLE(offset, enable, 0) +#define IOMUX_SCTIMER_IN_CLR(offset, enable) \ + IOMUX_OFFSET_ENABLE(offset, enable, 4) +#define IOMUX_CTIMER_CLR(offset, enable)\ + IOMUX_OFFSET_ENABLE(offset, enable, 8) +#define IOMUX_FSEL_CLR(mask) ((mask) << 13) +#define IOMUX_FLEXCOMM_CLR(idx, mask) \ + (((mask) << 45) | ((idx) << 56)) + +/* GPIO configuration extraction macros */ +#define IOMUX_GET_SCTIMER_OUT_CLR_ENABLE(mux) ((mux) & 0x1) +#define IOMUX_GET_SCTIMER_OUT_CLR_OFFSET(mux) (((mux) >> 1) & 0x7) +#define IOMUX_GET_SCTIMER_IN_CLR_ENABLE(mux) (((mux) >> 4) & 0x1) +#define IOMUX_GET_SCTIMER_IN_CLR_OFFSET(mux) (((mux) >> 5) & 0x7) +#define IOMUX_GET_CTIMER_CLR_ENABLE(mux) (((mux) >> 8) & 0x1ULL) +#define IOMUX_GET_CTIMER_CLR_OFFSET(mux) (((mux) >> 9) & 0xFULL) +#define IOMUX_GET_FSEL_CLR_MASK(mux) (((mux) >> 13) & 0xFFFFFFFFULL) +#define IOMUX_GET_FLEXCOMM_CLR_MASK(mux) \ + (((mux) >> 45) & 0x7FFULL) +#define IOMUX_GET_FLEXCOMM_CLR_IDX(mux) \ + (((mux) >> 56) & 0xF) + +/* Pin mux type and gpio offset macros */ +#define IOMUX_GPIO_IDX(x) ((x) & 0x7F) +#define IOMUX_TYPE(x) (((x) & 0xF) << 7) +#define IOMUX_GET_GPIO_IDX(mux) ((mux) & 0x7F) +#define IOMUX_GET_TYPE(mux) (((mux) >> 7) & 0xF) + +/* Flexcomm specific macros */ +#define IOMUX_FLEXCOMM_IDX(x) (((x) & 0xF) << 11) +#define IOMUX_FLEXCOMM_BIT(x) (((x) & 0xF) << 15) +#define IOMUX_GET_FLEXCOMM_IDX(mux) (((mux) >> 11) & 0xF) +#define IOMUX_GET_FLEXCOMM_BIT(mux) (((mux) >> 15) & 0xF) + +/* Function select specific macros */ +#define IOMUX_FSEL_BIT(mux) (((mux) & 0x1F) << 11) +#define IOMUX_GET_FSEL_BIT(mux) (((mux) >> 11) & 0x1F) + +/* CTimer specific macros */ +#define IOMUX_CTIMER_BIT(x) (((x) & 0xF) << 11) +#define IOMUX_GET_CTIMER_BIT(mux) (((mux) >> 11) & 0xF) + +/* SCtimer specific macros */ +#define IOMUX_SCTIMER_BIT(x) (((x) & 0xF) << 11) +#define IOMUX_GET_SCTIMER_BIT(mux) (((mux) >> 11) & 0xF) + + +/* Mux Types */ +#define IOMUX_FLEXCOMM 0x0 +#define IOMUX_FSEL 0x1 +#define IOMUX_CTIMER_IN 0x2 +#define IOMUX_CTIMER_OUT 0x3 +#define IOMUX_SCTIMER_IN 0x4 +#define IOMUX_SCTIMER_OUT 0x5 +#define IOMUX_GPIO 0x6 +#define IOMUX_SGPIO 0x7 +#define IOMUX_AON 0x8 + + +/* Pin configuration settings */ +#define IOMUX_PAD_PULL(x) (((x) & 0x3) << 19) +#define IOMUX_PAD_SLEW(x) (((x) & 0x3) << 21) +#define IOMUX_PAD_SLEEP_FORCE(en, val) \ + ((((en) & 0x1) << 24) | (((val) & 0x1) << 23)) +#define IOMUX_PAD_GET_PULL(mux) (((mux) >> 19) & 0x3) +#define IOMUX_PAD_GET_SLEW(mux) (((mux) >> 21) & 0x3) +#define IOMUX_PAD_GET_SLEEP_FORCE_EN(mux) (((mux) >> 24) & 0x1) +#define IOMUX_PAD_GET_SLEEP_FORCE_VAL(mux) (((mux) >> 23) & 0x1) + +/* + * GPIO mux options. These options are used to clear all alternate + * pin functions, so the pin controller will use GPIO mode. + */ + +#define IOMUX_GPIO_CLR_0 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_1 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(1ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_2 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x32eULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_3 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x22eULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_4 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x2dULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x800000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(1ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(1ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_5 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_6 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_7 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0xedULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_8 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_9 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_10 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_11 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(8ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(8ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_12 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8020ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(2ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_13 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(3ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_14 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(4ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_15 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0xedULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_16 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_17 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_18 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0xc600ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_19 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_20 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_21 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(5ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_22 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_23 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_24 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x40000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(6ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_25 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0xedULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x10000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(7ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_26 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x80000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(4ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(4ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_27 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x10000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(5ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(5ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_28 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_29 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_30 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_31 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_32 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_33 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_34 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_35 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(6ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(6ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_36 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(7ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(7ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_37 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(8ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_38 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(9ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_39 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(10ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_40 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_41 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_42 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_43 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_44 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_45 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_46 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_47 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_48 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_49 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_50 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x22000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_51 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x40810ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(11ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_52 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x80810ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(12ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_53 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x100810ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(13ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_54 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0xedULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x200810ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(14ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_55 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x400000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(9ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(9ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_56 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8000800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_57 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8000800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_58 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_59 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_60 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_61 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x20000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_62 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_63 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_OPS \ + IOMUX_GPIO_CLR_0, IOMUX_GPIO_CLR_1, IOMUX_GPIO_CLR_2, IOMUX_GPIO_CLR_3, \ + IOMUX_GPIO_CLR_4, IOMUX_GPIO_CLR_5, IOMUX_GPIO_CLR_6, IOMUX_GPIO_CLR_7, \ + IOMUX_GPIO_CLR_8, IOMUX_GPIO_CLR_9, IOMUX_GPIO_CLR_10, IOMUX_GPIO_CLR_11, \ + IOMUX_GPIO_CLR_12, IOMUX_GPIO_CLR_13, IOMUX_GPIO_CLR_14, IOMUX_GPIO_CLR_15, \ + IOMUX_GPIO_CLR_16, IOMUX_GPIO_CLR_17, IOMUX_GPIO_CLR_18, IOMUX_GPIO_CLR_19, \ + IOMUX_GPIO_CLR_20, IOMUX_GPIO_CLR_21, IOMUX_GPIO_CLR_22, IOMUX_GPIO_CLR_23, \ + IOMUX_GPIO_CLR_24, IOMUX_GPIO_CLR_25, IOMUX_GPIO_CLR_26, IOMUX_GPIO_CLR_27, \ + IOMUX_GPIO_CLR_28, IOMUX_GPIO_CLR_29, IOMUX_GPIO_CLR_30, IOMUX_GPIO_CLR_31, \ + IOMUX_GPIO_CLR_32, IOMUX_GPIO_CLR_33, IOMUX_GPIO_CLR_34, IOMUX_GPIO_CLR_35, \ + IOMUX_GPIO_CLR_36, IOMUX_GPIO_CLR_37, IOMUX_GPIO_CLR_38, IOMUX_GPIO_CLR_39, \ + IOMUX_GPIO_CLR_40, IOMUX_GPIO_CLR_41, IOMUX_GPIO_CLR_42, IOMUX_GPIO_CLR_43, \ + IOMUX_GPIO_CLR_44, IOMUX_GPIO_CLR_45, IOMUX_GPIO_CLR_46, IOMUX_GPIO_CLR_47, \ + IOMUX_GPIO_CLR_48, IOMUX_GPIO_CLR_49, IOMUX_GPIO_CLR_50, IOMUX_GPIO_CLR_51, \ + IOMUX_GPIO_CLR_52, IOMUX_GPIO_CLR_53, IOMUX_GPIO_CLR_54, IOMUX_GPIO_CLR_55, \ + IOMUX_GPIO_CLR_56, IOMUX_GPIO_CLR_57, IOMUX_GPIO_CLR_58, IOMUX_GPIO_CLR_59, \ + IOMUX_GPIO_CLR_60, IOMUX_GPIO_CLR_61, IOMUX_GPIO_CLR_62, IOMUX_GPIO_CLR_63 + +#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_DEFS_H_ */ diff --git a/soc/nxp/rw/pinctrl_soc.h b/soc/nxp/rw/pinctrl_soc.h new file mode 100644 index 00000000000..14b40bd69cd --- /dev/null +++ b/soc/nxp/rw/pinctrl_soc.h @@ -0,0 +1,46 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_SOC_H_ + +#include +#include + +#include "pinctrl_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +typedef uint32_t pinctrl_soc_pin_t; + + +#define Z_PINCTRL_IOMUX_PINCFG(node_id) \ + (IF_ENABLED(DT_PROP(node_id, bias_pull_down), \ + (IOMUX_PAD_PULL(0x2) |)) /* pull down */ \ + IF_ENABLED(DT_PROP(node_id, bias_pull_up), \ + (IOMUX_PAD_PULL(0x1) |)) /* pull up */ \ + IF_ENABLED(DT_NODE_HAS_PROP(node_id, sleep_output), /* force output */ \ + IOMUX_PAD_SLEEP_FORCE(0x1, DT_ENUM_IDX(node_id, sleep_output))) \ + IOMUX_PAD_SLEW(DT_ENUM_IDX(node_id, slew_rate))) /* slew rate */ + + +#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ + DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOMUX_PINCFG(group), + + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ + DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)} + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_SOC_H_ */ diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c new file mode 100644 index 00000000000..4f509ef5425 --- /dev/null +++ b/soc/nxp/rw/soc.c @@ -0,0 +1,189 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include "soc.h" +#include "flexspi_clock_setup.h" +#include "fsl_ocotp.h" +#ifdef CONFIG_NXP_RW6XX_BOOT_HEADER +extern char z_main_stack[]; +extern char _flash_used[]; + +extern void z_arm_reset(void); +extern void z_arm_nmi(void); +extern void z_arm_hard_fault(void); +extern void z_arm_mpu_fault(void); +extern void z_arm_bus_fault(void); +extern void z_arm_usage_fault(void); +extern void z_arm_secure_fault(void); +extern void z_arm_svc(void); +extern void z_arm_debug_monitor(void); +extern void z_arm_pendsv(void); +extern void sys_clock_isr(void); +extern void z_arm_exc_spurious(void); + +__imx_boot_ivt_section void (*const image_vector_table[])(void) = { + (void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */ + z_arm_reset, /* 0x04 */ + z_arm_nmi, /* 0x08 */ + z_arm_hard_fault, /* 0x0C */ + z_arm_mpu_fault, /* 0x10 */ + z_arm_bus_fault, /* 0x14 */ + z_arm_usage_fault, /* 0x18 */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + z_arm_secure_fault, /* 0x1C */ +#else + z_arm_exc_spurious, +#endif /* CONFIG_ARM_SECURE_FIRMWARE */ + (void (*)())_flash_used, /* 0x20, imageLength. */ + 0, /* 0x24, imageType (Plain Image) */ + 0, /* 0x28, authBlockOffset/crcChecksum */ + z_arm_svc, /* 0x2C */ + z_arm_debug_monitor, /* 0x30 */ + (void (*)())image_vector_table, /* 0x34, imageLoadAddress. */ + z_arm_pendsv, /* 0x38 */ +#if defined(CONFIG_SYS_CLOCK_EXISTS) && defined(CONFIG_CORTEX_M_SYSTICK_INSTALL_ISR) + sys_clock_isr, /* 0x3C */ +#else + z_arm_exc_spurious, +#endif +}; +#endif /* CONFIG_NXP_RW6XX_BOOT_HEADER */ + +const clock_avpll_config_t avpll_config = { + .ch1Freq = kCLOCK_AvPllChFreq12p288m, + .ch2Freq = kCLOCK_AvPllChFreq64m, + .enableCali = true +}; + +/** + * @brief Initialize the system clocks and peripheral clocks + * + * This function is called from the power management code as the + * clock needs to be re-initialized on exit from Standby mode. Hence + * this function is relocated to RAM. + */ +__ramfunc void clock_init(void) +{ + POWER_DisableGDetVSensors(); + + if ((PMU->CAU_SLP_CTRL & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK) == 0U) { + /* LPOSC not enabled, enable it */ + CLOCK_EnableClock(kCLOCK_RefClkCauSlp); + } + if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK) != 0U) { + /* REFCLK_SYS not enabled, enable it */ + CLOCK_EnableClock(kCLOCK_RefClkSys); + } + + /* Initialize T3 clocks and t3pll_mci_48_60m_irc configured to 48.3MHz */ + CLOCK_InitT3RefClk(kCLOCK_T3MciIrc48m); + /* Enable FFRO */ + CLOCK_EnableClock(kCLOCK_T3PllMciIrcClk); + /* Enable T3 256M clock and SFRO */ + CLOCK_EnableClock(kCLOCK_T3PllMci256mClk); + + /* Move FLEXSPI clock source to T3 256m / 4 to avoid instruction/data fetch issue in XIP + * when updating PLL and main clock. + */ + set_flexspi_clock(FLEXSPI, 6U, 4U); + + /* First let M33 run on SOSC */ + CLOCK_AttachClk(kSYSOSC_to_MAIN_CLK); + CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1); + + /* tcpu_mci_clk configured to 260MHz, tcpu_mci_flexspi_clk 312MHz. */ + CLOCK_InitTcpuRefClk(3120000000UL, kCLOCK_TcpuFlexspiDiv10); + /* Enable tcpu_mci_clk 260MHz. Keep tcpu_mci_flexspi_clk gated. */ + CLOCK_EnableClock(kCLOCK_TcpuMciClk); + + /* tddr_mci_flexspi_clk 320MHz */ + CLOCK_InitTddrRefClk(kCLOCK_TddrFlexspiDiv10); + CLOCK_EnableClock(kCLOCK_TddrMciFlexspiClk); /* 320MHz */ + + /* Enable AUX0 PLL to 260 MHz */ + CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U); + + /* Init AVPLL and enable both channels */ + CLOCK_InitAvPll(&avpll_config); + CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U); + + /* Configure MainPll to 260MHz, then let CM33 run on Main PLL. */ + CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1U); + CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U); + CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); + + /* Set SYSTICKFCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U); + CLOCK_AttachClk(kSYSTICK_DIV_to_SYSTICK_CLK); + + /* Set PLL FRG clock to 20MHz. */ + CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U); + + /* Call function set_flexspi_clock() to set flexspi clock source to aux0_pll_clk in XIP. */ + set_flexspi_clock(FLEXSPI, 2U, 2U); + +/* Any flexcomm can be USART */ +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay)) && CONFIG_SERIAL + CLOCK_SetFRGClock(&(const clock_frg_clk_config_t){0, kCLOCK_FrgPllDiv, 255, 0}); + CLOCK_AttachClk(kFRG_to_FLEXCOMM0); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_usart, okay)) && CONFIG_SERIAL + CLOCK_SetFRGClock(&(const clock_frg_clk_config_t){1, kCLOCK_FrgPllDiv, 255, 0}); + CLOCK_AttachClk(kFRG_to_FLEXCOMM1); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_usart, okay)) && CONFIG_SERIAL + CLOCK_SetFRGClock(&(const clock_frg_clk_config_t){2, kCLOCK_FrgPllDiv, 255, 0}); + CLOCK_AttachClk(kFRG_to_FLEXCOMM2); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_usart, okay)) && CONFIG_SERIAL + CLOCK_SetFRGClock(&(const clock_frg_clk_config_t){3, kCLOCK_FrgPllDiv, 255, 0}); + CLOCK_AttachClk(kFRG_to_FLEXCOMM3); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm14), nxp_lpc_usart, okay)) && CONFIG_SERIAL + CLOCK_SetFRGClock(&(const clock_frg_clk_config_t){14, kCLOCK_FrgPllDiv, 255, 0}); + CLOCK_AttachClk(kFRG_to_FLEXCOMM14); +#endif + +} + +/** + * + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * + * @return 0 + */ + +static int nxp_rw600_init(void) +{ + + /* Initialize clock */ + clock_init(); + + return 0; +} + +void z_arm_platform_init(void) +{ + /* This is provided by the SDK */ + SystemInit(); +} + +SYS_INIT(nxp_rw600_init, PRE_KERNEL_1, 0); diff --git a/soc/nxp/rw/soc.h b/soc/nxp/rw/soc.h new file mode 100644 index 00000000000..66a2cf836b5 --- /dev/null +++ b/soc/nxp/rw/soc.h @@ -0,0 +1,24 @@ +/* + * Copyright 2022-2023 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#ifndef _ASMLANGUAGE +#include +#include + +/* Add include for DTS generated information */ +#include + +#endif /* !_ASMLANGUAGE */ + + +#ifdef CONFIG_MEMC +uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); +#endif + + +#endif /* _SOC__H_ */ diff --git a/soc/nxp/rw/soc.yml b/soc/nxp/rw/soc.yml new file mode 100644 index 00000000000..324b27ef219 --- /dev/null +++ b/soc/nxp/rw/soc.yml @@ -0,0 +1,7 @@ +family: +- name: nxp_rw + series: + - name: rw61x + socs: + - name: rw612 + - name: rw610 diff --git a/west.yml b/west.yml index 9d3acf9af5b..1eb17cbc69d 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: ac24626660f96dc734714896878dd6e1157c1c29 + revision: 259bc153dd5b9dbc5cbe63d2d644a61ee83b7496 path: modules/hal/nxp groups: - hal From f519087b217d0577c0df3c3e0858ab0ad1dd9fe6 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 7 Mar 2024 16:42:56 -0600 Subject: [PATCH 0607/2402] boards: nxp: Add RD_RW612_BGA board Add rd_rw612_bga board target. Signed-off-by: Declan Snyder --- MAINTAINERS.yml | 1 + boards/nxp/rd_rw612_bga/CMakeLists.txt | 20 +++ boards/nxp/rd_rw612_bga/Kconfig.rd_rw612_bga | 5 + boards/nxp/rd_rw612_bga/board.cmake | 9 ++ boards/nxp/rd_rw612_bga/board.yml | 5 + boards/nxp/rd_rw612_bga/doc/index.rst | 115 ++++++++++++++++++ boards/nxp/rd_rw612_bga/pre_dt_board.cmake | 7 ++ .../rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi | 16 +++ boards/nxp/rd_rw612_bga/rd_rw612_bga.dts | 14 +++ boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 93 ++++++++++++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml | 18 +++ .../nxp/rd_rw612_bga/rd_rw612_bga_defconfig | 14 +++ 12 files changed, 317 insertions(+) create mode 100644 boards/nxp/rd_rw612_bga/CMakeLists.txt create mode 100644 boards/nxp/rd_rw612_bga/Kconfig.rd_rw612_bga create mode 100644 boards/nxp/rd_rw612_bga/board.cmake create mode 100644 boards/nxp/rd_rw612_bga/board.yml create mode 100644 boards/nxp/rd_rw612_bga/doc/index.rst create mode 100644 boards/nxp/rd_rw612_bga/pre_dt_board.cmake create mode 100644 boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi create mode 100644 boards/nxp/rd_rw612_bga/rd_rw612_bga.dts create mode 100644 boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi create mode 100644 boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml create mode 100644 boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 2b44108f2a3..7e7548928b0 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3329,6 +3329,7 @@ NXP Platforms (MCU): - boards/nxp/lpcxpress*/ - boards/nxp/twr_*/ - boards/nxp/vmu*/ + - boards/nxp/*rw*/ - soc/nxp/imxrt/ - soc/nxp/kinetis/ - soc/nxp/lpc/ diff --git a/boards/nxp/rd_rw612_bga/CMakeLists.txt b/boards/nxp/rd_rw612_bga/CMakeLists.txt new file mode 100644 index 00000000000..45052c065fb --- /dev/null +++ b/boards/nxp/rd_rw612_bga/CMakeLists.txt @@ -0,0 +1,20 @@ +# +# Copyright 2022-2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_RW6XX_BOOT_HEADER) + if(NOT DEFINED CONFIG_BOARD_RD_RW612_BGA) + message(WARNING "It appears you are using the board definition for " + "the RD_RW612_BGA, but targeting a custom board. You may need to " + "update your flash configuration block data") + endif() + zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + set(RW612_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/rdrw612bga") + zephyr_library() + zephyr_library_sources(${RW612_BOARD_DIR}/flash_config/flash_config.c) + zephyr_library_include_directories(${RW612_BOARD_DIR}/flash_config) +endif() diff --git a/boards/nxp/rd_rw612_bga/Kconfig.rd_rw612_bga b/boards/nxp/rd_rw612_bga/Kconfig.rd_rw612_bga new file mode 100644 index 00000000000..80151467e90 --- /dev/null +++ b/boards/nxp/rd_rw612_bga/Kconfig.rd_rw612_bga @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RD_RW612_BGA + select SOC_PART_NUMBER_RW612ETA1I diff --git a/boards/nxp/rd_rw612_bga/board.cmake b/boards/nxp/rd_rw612_bga/board.cmake new file mode 100644 index 00000000000..c7b1d7d51d4 --- /dev/null +++ b/boards/nxp/rd_rw612_bga/board.cmake @@ -0,0 +1,9 @@ +# Copyright 2022-2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=RW612" "--reset-after-load") + +board_runner_args(linkserver "--device=RW612:RDRW612") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/rd_rw612_bga/board.yml b/boards/nxp/rd_rw612_bga/board.yml new file mode 100644 index 00000000000..fe2573bfdbb --- /dev/null +++ b/boards/nxp/rd_rw612_bga/board.yml @@ -0,0 +1,5 @@ +board: + name: rd_rw612_bga + vendor: nxp + socs: + - name: rw612 diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst new file mode 100644 index 00000000000..0c6d81c3057 --- /dev/null +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -0,0 +1,115 @@ +.. _rd_rw612_bga: + +NXP RD-RW612-BGA +################ + +Overview +******** + +The RW612 is a highly integrated, low-power tri-radio wireless MCU with an +integrated 260 MHz ARM Cortex-M33 MCU and Wi-Fi 6 + Bluetooth Low Energy (LE) 5.3 / 802.15.4 +radios designed for a broad array of applications, including connected smart home devices, +gaming controllers, enterprise and industrial automation, smart accessories and smart energy. + +The RW612 MCU subsystem includes 1.2 MB of on-chip SRAM and a high-bandwidth Quad SPI interface +with an on-the-fly decryption engine for securely accessing off-chip XIP flash. + +The advanced design of the RW612 delivers tight integration, low power and highly secure +operation in a space- and cost-efficient wireless MCU requiring only a single 3.3 V power supply. + +Hardware +******** + +- 260 MHz ARM Cortex-M33, tri-radio cores for Wifi 6 + BLE 5.3 + 802.15.4 +- 1.2 MB on-chip SRAM + +Supported Features +================== + ++-----------+------------+-----------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+===================================+ +| NVIC | on-chip | nested vector interrupt controller| ++-----------+------------+-----------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-----------------------------------+ +| MCI_IOMUX | on-chip | pinmux | ++-----------+------------+-----------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-----------------------------------+ +| USART | on-chip | serial | ++-----------+------------+-----------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig/` + +Other hardware features are not currently supported + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the JLink Firmware. + +Configuring a Console +===================== + +Connect a USB cable from your PC to J7, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rd_rw612_bga + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v3.4.0 ***** + Hello World! rd_rw612_bga + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rd_rw612_bga + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS zephyr-v3.6.0 ***** + Hello World! rd_rw612_bga + + +Resources +========= + +.. _RW612 Website: + https://www.nxp.com/products/wireless-connectivity/wi-fi-plus-bluetooth-plus-802-15-4/wireless-mcu-with-integrated-tri-radiobr1x1-wi-fi-6-plus-bluetooth-low-energy-5-3-802-15-4:RW612 diff --git a/boards/nxp/rd_rw612_bga/pre_dt_board.cmake b/boards/nxp/rd_rw612_bga/pre_dt_board.cmake new file mode 100644 index 00000000000..2c56668e435 --- /dev/null +++ b/boards/nxp/rd_rw612_bga/pre_dt_board.cmake @@ -0,0 +1,7 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "simple_bus_reg" on RW6XX boards as all GPIO ports use the same register. +list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg") +# Suppress "spi_bus_bridge" as flexcomm node can be used as a SPI device. +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi new file mode 100644 index 00000000000..c9b0bcb8984 --- /dev/null +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi @@ -0,0 +1,16 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + pinmux_flexcomm3_usart: pinmux_flexcomm3_usart { + group0 { + pinmux = ; + slew-rate = "normal"; + }; + }; +}; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dts b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dts new file mode 100644 index 00000000000..23321fd1cdd --- /dev/null +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dts @@ -0,0 +1,14 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "rd_rw612_bga.dtsi" + +/ { + model = "nxp,rd_rw612_bga"; +}; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi new file mode 100644 index 00000000000..810805bd6a9 --- /dev/null +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -0,0 +1,93 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "rd_rw612_bga-pinctrl.dtsi" +/ { + + aliases { + usart-0 = &flexcomm3; + led0 = &green_led; + sw0 = &sw_4; + }; + + chosen { + zephyr,sram = &sram_data; + zephyr,flash = &mx25u51245g; + zephyr,code-partition = &slot0_partition; + zephyr,flash-controller = &mx25u51245g; + zephyr,console = &flexcomm3; + zephyr,shell-uart = &flexcomm3; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&hsgpio1 20 0>; + label = "User LED_GREEN"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + sw_4: sw_4 { + label = "User SW4"; + gpios = <&hsgpio0 25 0>; + }; + }; +}; + +&flexcomm3 { + compatible = "nxp,lpc-usart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm3_usart>; + pinctrl-names = "default"; +}; + +&hsgpio0 { + status = "okay"; +}; + +&flexspi { + status = "okay"; + mx25u51245g: mx25u51245g@0 { + compatible = "nxp,imx-flexspi-nor"; + spi-max-frequency = <133000000>; + reg = <0>; + /* MX25UM51245G is 64MB, 512MBit flash part */ + size = ; + status = "disabled"; + jedec-id = [c2 25 3a]; + erase-block-size = <4096>; + write-block-size = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 0x3e0000>; + }; + slot1_partition: partition@680000 { + label = "image-1"; + reg = <0x680000 0x3e0000>; + }; + storage_partition: partition@a60000 { + label = "storage"; + reg = <0xa60000 0x35a0000>; + }; + }; + }; +}; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml new file mode 100644 index 00000000000..ca3a4fd2de0 --- /dev/null +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -0,0 +1,18 @@ +# +# Copyright 2022-2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: rd_rw612_bga +name: NXP RD_RW612_BGA +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 960 +flash: 65536 +supported: + - gpio diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig b/boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig new file mode 100644 index 00000000000..33107fc36b9 --- /dev/null +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig @@ -0,0 +1,14 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_PINCTRL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y From e1b7b450c82cd8236a36271fab49cbb9067a9d22 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 11 Mar 2024 12:11:39 +0100 Subject: [PATCH 0608/2402] doc/develop api_lifecycle: Mention adding the arch review label For breaking API changes, let's mention explicity the PR should be labelled with the "Architecture Review" label, as that is the one we base the automation on. As otherwise it is not clear enough for developers that they should add it, and without it (and the automation surrounding it), it is too easy for a PR to be merged by mistake. Signed-off-by: Alberto Escolar Piedras --- doc/develop/api/api_lifecycle.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/develop/api/api_lifecycle.rst b/doc/develop/api/api_lifecycle.rst index b34832655c8..f4fae1eef7c 100644 --- a/doc/develop/api/api_lifecycle.rst +++ b/doc/develop/api/api_lifecycle.rst @@ -166,6 +166,8 @@ The Pull Request must include the following: upcoming release - The labels ``API``, ``Breaking API Change`` and ``Release Notes``, as well as any others that are applicable +- The label ``Architecture Review`` if the RFC was not yet discussed and agreed upon in `Zephyr + Architecture meeting`_ Once the steps above have been completed, the outcome of the proposal will depend on the approval of the actual Pull Request by the maintainer of the From f3f42d363bb806db02a1bdbff2cd711f6701238c Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 11 Mar 2024 09:10:20 +0100 Subject: [PATCH 0609/2402] Bluetooth: shell: add bsim runner script Spawns n instances of the bt-shell in separate xterm windows. Assumes in-tree build of the shell, can optionally specify another .exe image. Also add snippet for that use-case (`-S xterm-native-shell`). Signed-off-by: Jonathan Rico --- tests/bluetooth/shell/run-bsim.sh | 43 +++++++++++++++++++ .../snippets/xterm-native-shell/snippet.yml | 4 ++ .../xterm-native-shell.conf | 4 ++ .../xterm-native-shell.overlay | 25 +++++++++++ 4 files changed, 76 insertions(+) create mode 100755 tests/bluetooth/shell/run-bsim.sh create mode 100644 tests/bluetooth/shell/snippets/xterm-native-shell/snippet.yml create mode 100644 tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.conf create mode 100644 tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay diff --git a/tests/bluetooth/shell/run-bsim.sh b/tests/bluetooth/shell/run-bsim.sh new file mode 100755 index 00000000000..88d5e37dc98 --- /dev/null +++ b/tests/bluetooth/shell/run-bsim.sh @@ -0,0 +1,43 @@ +#!/usr/bin/env bash +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +set -e +set -u + +if [ $# -eq 0 ]; then + echo "Usage: run.sh [exe_image]" + shift +fi + +if [ $# -gt 2 ]; then + echo "Too many args" + shift +fi + +echo "Starting simulation. Hit Ctrl-C to exit." + +# Build it with e.g. +# cd $ZEPHYR_BASE/tests/bluetooth/shell +# west build -d build -b nrf52_bsim -S xterm-native-shell $ZEPHYR_BASE/tests/bluetooth/shell +default_image=${ZEPHYR_BASE}/tests/bluetooth/shell/build/zephyr/zephyr.exe + +num_devices=$1 +image="${2:-"${default_image}"}" + +# Cleanup all existing sims +$BSIM_OUT_PATH/components/common/stop_bsim.sh + +# Force sim to real-time +pushd $BSIM_OUT_PATH/components/device_handbrake +./bs_device_handbrake -s=shell-sim -r=10 -d=0 & +popd + +for dev_id in $(seq 1 ${num_devices}); do + echo "Start device $dev_id" + $image -s=shell-sim -d=$dev_id -RealEncryption=1 -rs=$dev_id -attach_uart -wait_uart & +done + +# Start the PHY +pushd $BSIM_OUT_PATH/bin +$BSIM_OUT_PATH/bin/bs_2G4_phy_v1 -s=shell-sim -D=$((num_devices+=1)) diff --git a/tests/bluetooth/shell/snippets/xterm-native-shell/snippet.yml b/tests/bluetooth/shell/snippets/xterm-native-shell/snippet.yml new file mode 100644 index 00000000000..836aa14542d --- /dev/null +++ b/tests/bluetooth/shell/snippets/xterm-native-shell/snippet.yml @@ -0,0 +1,4 @@ +name: xterm-native-shell +append: + EXTRA_CONF_FILE: xterm-native-shell.conf + EXTRA_DTC_OVERLAY_FILE: xterm-native-shell.overlay diff --git a/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.conf b/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.conf new file mode 100644 index 00000000000..b29c9b615a6 --- /dev/null +++ b/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.conf @@ -0,0 +1,4 @@ +CONFIG_NATIVE_UART_0_ON_OWN_PTY=y +CONFIG_UART_NATIVE_WAIT_PTS_READY_ENABLE=y +CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=8192 +CONFIG_LOG_PRINTK=n diff --git a/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay b/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay new file mode 100644 index 00000000000..c47dd06bc38 --- /dev/null +++ b/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay @@ -0,0 +1,25 @@ +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +/* Use the PTY driver instead of the UART peripheral emulation that is now the + * default on nrf52_bsim. */ + +&uart1 { + status = "okay"; + compatible = "zephyr,native-posix-uart"; + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-1; + /delete-property/ pinctrl-names; +}; + +&uart0 { + status = "okay"; + compatible = "zephyr,native-posix-uart"; + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-1; + /delete-property/ pinctrl-names; +}; From 4a55bc00f01eddcd723eb4670b74ced8da30791e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Th=C3=A9o=20Battrel?= Date: Thu, 7 Mar 2024 16:04:25 +0100 Subject: [PATCH 0610/2402] Bluetooth: Shell: Add support for EAD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add new commands to manage the Encrypted Advertising Data feature. Overview of those new commands: - `bt encrypted-ad set-keys`: set key materials (session key and initialisation vector) used for encrypted and decryption of EAD; - `bt encrypted-ad add-ad`: store a given advertising data structure; - `bt encrypted-ad add-ead`: encrypt the given advertising data structres and store the generated AD structure; - `bt encrypted-ad commit-ad`: set the AD of the selected advertiser with the stored AD; - `bt encrypted-ad clear-ad`: remove all stored AD; - `bt encrypted-ad decrypt-scan`: decrypt data using the previously set key materials when receiving AD with type `0x31`. The documentation of the Bluetooth Shell has been updated to include those new commands. Signed-off-by: Théo Battrel --- .../bluetooth/bluetooth-shell.rst | 84 +++++ subsys/bluetooth/shell/bt.c | 340 ++++++++++++++++++ tests/bluetooth/shell/prj.conf | 2 + 3 files changed, 426 insertions(+) diff --git a/doc/connectivity/bluetooth/bluetooth-shell.rst b/doc/connectivity/bluetooth/bluetooth-shell.rst index f639cb0b030..2b38f4c7b6f 100644 --- a/doc/connectivity/bluetooth/bluetooth-shell.rst +++ b/doc/connectivity/bluetooth/bluetooth-shell.rst @@ -228,6 +228,90 @@ Let's now have a look at some extended advertising features. To enable extended This will create an extended advertiser, that is connectable and non-scannable. +Encrypted Advertising Data +========================== + +Zephyr has support for the Encrypted Advertising Data feature. The :code:`bt encrypted-ad` +sub-commands allow managing the advertising data of a given advertiser. + +To encrypt the advertising data, key materials need to be provided, that can be done with :code:`bt +encrypted-ad set-keys `. The session key is 16 bytes long and the +initialisation vector is 8 bytes long. + +You can add advertising data by using :code:`bt encrypted-ad add-ad` and :code:`bt encrypted-ad +add-ead`. The former will take add one advertising data structure (as defined in the Core +Specification), when the later will read the given data, encrypt them and then add the generated +encrypted advertising data structure. It's possible to mix encrypted and non-encrypted data, when +done adding advertising data, :code:`bt encrypted-ad commit-ad` can be used to apply the change to +the data to the selected advertiser. After that the advertiser can be started as described +previously. It's possible to clear the advertising data by using :code:`bt encrypted-ad clear-ad`. + +On the Central side, it's possible to decrypt the received encrypted advertising data by setting the +correct keys material as described earlier and then enabling the decrypting of the data with +:code:`bt encrypted-ad decrypt-scan on`. + +.. note:: + + To see the advertising data in the scan report :code:`bt scan-verbose-output` need to be + enabled. + +.. note:: + + It's possible to increase the length of the advertising data by increasing the value of + :kconfig:option:`CONFIG_BT_CTLR_ADV_DATA_LEN_MAX` and + :kconfig:option:`CONFIG_BT_CTLR_SCAN_DATA_LEN_MAX`. + +Here is a simple example demonstrating the usage of EAD: + +.. tabs:: + + .. group-tab:: Peripheral + + .. code-block:: console + + uart:~$ bt init + ... + uart:~$ bt adv-create conn-nscan ext-adv + Created adv id: 0, adv: 0x81769a0 + uart:~$ bt encrypted-ad set-keys 9ba22d3824efc70feb800c80294cba38 2e83f3d4d47695b6 + session key set to: + 00000000: 9b a2 2d 38 24 ef c7 0f eb 80 0c 80 29 4c ba 38 |..-8$... ....)L.8| + initialisation vector set to: + 00000000: 2e 83 f3 d4 d4 76 95 b6 |.....v.. | + uart:~$ bt encrypted-ad add-ad 06097368656C6C + uart:~$ bt encrypted-ad add-ead 03ffdead03ffbeef + uart:~$ bt encrypted-ad commit-ad + Advertising data for Advertiser[0] 0x81769a0 updated. + uart:~$ bt adv-start + Advertiser[0] 0x81769a0 set started + + .. group-tab:: Central + + .. code-block:: console + + uart:~$ bt init + ... + uart:~$ bt scan-verbose-output on + uart:~$ bt encrypted-ad set-keys 9ba22d3824efc70feb800c80294cba38 2e83f3d4d47695b6 + session key set to: + 00000000: 9b a2 2d 38 24 ef c7 0f eb 80 0c 80 29 4c ba 38 |..-8$... ....)L.8| + initialisation vector set to: + 00000000: 2e 83 f3 d4 d4 76 95 b6 |.....v.. | + uart:~$ bt encrypted-ad decrypt-scan on + Received encrypted advertising data will now be decrypted using provided key materials. + uart:~$ bt scan on + Bluetooth active scan enabled + [DEVICE]: 68:49:30:68:49:30 (random), AD evt type 5, RSSI -59 shell C:1 S:0 D:0 SR:0 E:1 Prim: LE 1M, Secn: LE 2M, Interval: 0x0000 (0 us), SID: 0x0 + [SCAN DATA START - EXT_ADV] + Type 0x09: shell + Type 0x31: Encrypted Advertising Data: 0xe2, 0x17, 0xed, 0x04, 0xe7, 0x02, 0x1d, 0xc9, 0x40, 0x07, uart:~0x18, 0x90, 0x6c, 0x4b, 0xfe, 0x34, 0xad + [START DECRYPTED DATA] + Type 0xff: 0xde, 0xad + Type 0xff: 0xbe, 0xef + [END DECRYPTED DATA] + [SCAN DATA END] + ... + Filter Accept List ****************** diff --git a/subsys/bluetooth/shell/bt.c b/subsys/bluetooth/shell/bt.c index fc5b8359118..f69702ba184 100644 --- a/subsys/bluetooth/shell/bt.c +++ b/subsys/bluetooth/shell/bt.c @@ -32,6 +32,7 @@ #include #include #include +#include #include @@ -216,6 +217,30 @@ static struct bt_scan_filter { static const char scan_response_label[] = "[DEVICE]: "; static bool scan_verbose_output; +#if defined(CONFIG_BT_EAD) +static uint8_t bt_shell_ead_session_key[BT_EAD_KEY_SIZE] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, + 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, + 0xCC, 0xCD, 0xCE, 0xCF}; +static uint8_t bt_shell_ead_iv[BT_EAD_IV_SIZE] = {0xFB, 0x56, 0xE1, 0xDA, 0xDC, 0x7E, 0xAD, 0xF5}; + +/* this is the number of ad struct allowed */ +#define BT_SHELL_EAD_MAX_AD 10 +static size_t bt_shell_ead_ad_len; + +#if defined(CONFIG_BT_CTLR_ADV_DATA_LEN_MAX) +/* this is the maximum total size of the ad data */ +#define BT_SHELL_EAD_DATA_MAX_SIZE CONFIG_BT_CTLR_ADV_DATA_LEN_MAX +#else +#define BT_SHELL_EAD_DATA_MAX_SIZE 31 +#endif +static size_t bt_shell_ead_data_size; +static uint8_t bt_shell_ead_data[BT_SHELL_EAD_DATA_MAX_SIZE] = {0}; + +int ead_update_ad(void); +#endif + +static bool bt_shell_ead_decrypt_scan; + /** * @brief Compares two strings without case sensitivy * @@ -383,6 +408,36 @@ static bool data_verbose_cb(struct bt_data *data, void *user_data) case BT_DATA_CSIS_RSI: print_data_set(3, data->data, data->data_len); break; + case BT_DATA_ENCRYPTED_AD_DATA: + shell_fprintf(ctx_shell, SHELL_INFO, "Encrypted Advertising Data: "); + print_data_set(1, data->data, data->data_len); + + if (bt_shell_ead_decrypt_scan) { +#if defined(CONFIG_BT_EAD) + shell_fprintf(ctx_shell, SHELL_INFO, "\n%*s[START DECRYPTED DATA]\n", + strlen(scan_response_label), ""); + + int ead_err; + struct net_buf_simple decrypted_buf; + size_t decrypted_data_size = BT_EAD_DECRYPTED_PAYLOAD_SIZE(data->data_len); + uint8_t decrypted_data[decrypted_data_size]; + + ead_err = bt_ead_decrypt(bt_shell_ead_session_key, bt_shell_ead_iv, + data->data, data->data_len, decrypted_data); + if (ead_err) { + shell_error(ctx_shell, "Error during decryption (err %d)", ead_err); + } + + net_buf_simple_init_with_data(&decrypted_buf, &decrypted_data[0], + decrypted_data_size); + + bt_data_parse(&decrypted_buf, &data_verbose_cb, user_data); + + shell_fprintf(ctx_shell, SHELL_INFO, "%*s[END DECRYPTED DATA]", + strlen(scan_response_label), ""); +#endif + } + break; default: print_data_set(1, data->data, data->data_len); } @@ -581,6 +636,13 @@ static bool adv_rpa_expired(struct bt_le_ext_adv *adv) adv_index, adv, keep_rpa ? "not expired" : "expired"); +#if defined(CONFIG_BT_EAD) + /* EAD must be updated each time the RPA is updated */ + if (!keep_rpa) { + ead_update_ad(); + } +#endif + return keep_rpa; } #endif /* defined(CONFIG_BT_PRIVACY) */ @@ -4127,6 +4189,267 @@ static int cmd_auth_oob_tk(const struct shell *sh, size_t argc, char *argv[]) #endif /* !defined(CONFIG_BT_SMP_SC_PAIR_ONLY) */ #endif /* CONFIG_BT_SMP) || CONFIG_BT_CLASSIC */ +#if defined(CONFIG_BT_EAD) +static int cmd_encrypted_ad_set_keys(const struct shell *sh, size_t argc, char *argv[]) +{ + size_t len; + + const char *session_key = argv[1]; + const char *iv = argv[2]; + + len = hex2bin(session_key, strlen(session_key), bt_shell_ead_session_key, BT_EAD_KEY_SIZE); + if (len != BT_EAD_KEY_SIZE) { + shell_error(sh, "Failed to set session key"); + return -ENOEXEC; + } + + len = hex2bin(iv, strlen(iv), bt_shell_ead_iv, BT_EAD_IV_SIZE); + if (len != BT_EAD_IV_SIZE) { + shell_error(sh, "Failed to set initialisation vector"); + return -ENOEXEC; + } + + shell_info(sh, "session key set to:"); + shell_hexdump(sh, bt_shell_ead_session_key, BT_EAD_KEY_SIZE); + shell_info(sh, "initialisation vector set to:"); + shell_hexdump(sh, bt_shell_ead_iv, BT_EAD_IV_SIZE); + + return 0; +} + +int encrypted_ad_store_ad(const struct shell *sh, uint8_t type, const uint8_t *data, + uint8_t data_len) +{ + /* data_len is the size of the data, add two bytes for the size of the type + * and the length that will be stored with the data + */ + uint8_t new_data_size = data_len + 2; + + if (bt_shell_ead_data_size + new_data_size > BT_SHELL_EAD_DATA_MAX_SIZE) { + shell_error(sh, "Failed to add data (trying to add %d but %d already used on %d)", + new_data_size, bt_shell_ead_data_size, BT_SHELL_EAD_DATA_MAX_SIZE); + return -ENOEXEC; + } + + /* the length is the size of the data + the size of the type */ + bt_shell_ead_data[bt_shell_ead_data_size] = data_len + 1; + bt_shell_ead_data[bt_shell_ead_data_size + 1] = type; + memcpy(&bt_shell_ead_data[bt_shell_ead_data_size + 2], data, data_len); + + bt_shell_ead_data_size += new_data_size; + bt_shell_ead_ad_len += 1; + + return 0; +} + +bool is_payload_valid_ad(uint8_t *payload, size_t payload_size) +{ + size_t idx = 0; + bool is_valid = true; + + uint8_t ad_len; + + while (idx < payload_size) { + ad_len = payload[idx]; + + if (payload_size <= ad_len) { + is_valid = false; + break; + } + + idx += ad_len + 1; + } + + if (idx != payload_size) { + is_valid = false; + } + + return is_valid; +} + +static int cmd_encrypted_ad_add_ead(const struct shell *sh, size_t argc, char *argv[]) +{ + size_t len; + + char *hex_payload = argv[1]; + size_t hex_payload_size = strlen(hex_payload); + + uint8_t payload[BT_SHELL_EAD_DATA_MAX_SIZE] = {0}; + uint8_t payload_size = hex_payload_size / 2 + hex_payload_size % 2; + + uint8_t ead_size = BT_EAD_ENCRYPTED_PAYLOAD_SIZE(payload_size); + + if (ead_size > BT_SHELL_EAD_DATA_MAX_SIZE) { + shell_error(sh, + "Failed to add data. Maximum AD size is %d, passed data size after " + "encryption is %d", + BT_SHELL_EAD_DATA_MAX_SIZE, ead_size); + return -ENOEXEC; + } + + len = hex2bin(hex_payload, hex_payload_size, payload, BT_SHELL_EAD_DATA_MAX_SIZE); + if (len != payload_size) { + shell_error(sh, "Failed to add data"); + return -ENOEXEC; + } + + /* check that the given advertising data structures are valid before encrypting them */ + if (!is_payload_valid_ad(payload, payload_size)) { + shell_error(sh, "Failed to add data. Advertising structure are malformed."); + return -ENOEXEC; + } + + /* store not-yet encrypted AD but claim the expected size of encrypted AD */ + return encrypted_ad_store_ad(sh, BT_DATA_ENCRYPTED_AD_DATA, payload, ead_size); +} + +static int cmd_encrypted_ad_add_ad(const struct shell *sh, size_t argc, char *argv[]) +{ + size_t len; + uint8_t ad_len; + uint8_t ad_type; + + char *hex_payload = argv[1]; + size_t hex_payload_size = strlen(hex_payload); + + uint8_t payload[BT_SHELL_EAD_DATA_MAX_SIZE] = {0}; + uint8_t payload_size = hex_payload_size / 2 + hex_payload_size % 2; + + len = hex2bin(hex_payload, hex_payload_size, payload, BT_SHELL_EAD_DATA_MAX_SIZE); + if (len != payload_size) { + shell_error(sh, "Failed to add data"); + return -ENOEXEC; + } + + /* the length received is the length of ad data + the length of the data + * type but `bt_data` struct `data_len` field is only the size of the + * data + */ + ad_len = payload[0] - 1; + ad_type = payload[1]; + + /* if the ad data is malformed or there is more than 1 ad data passed we + * fail + */ + if (len != ad_len + 2) { + shell_error(sh, + "Failed to add data. Data need to be formated as specified in the " + "Core Spec. Only one non-encrypted AD payload can be added at a time."); + return -ENOEXEC; + } + + return encrypted_ad_store_ad(sh, ad_type, payload, payload_size); +} + +static int cmd_encrypted_ad_clear_ad(const struct shell *sh, size_t argc, char *argv[]) +{ + memset(bt_shell_ead_data, 0, BT_SHELL_EAD_DATA_MAX_SIZE); + + bt_shell_ead_ad_len = 0; + bt_shell_ead_data_size = 0; + + shell_info(sh, "Advertising data has been cleared."); + + return 0; +} + +int ead_encrypt_ad(const uint8_t *payload, uint8_t payload_size, uint8_t *encrypted_payload) +{ + int err; + + err = bt_ead_encrypt(bt_shell_ead_session_key, bt_shell_ead_iv, payload, payload_size, + encrypted_payload); + if (err != 0) { + shell_error(ctx_shell, "Failed to encrypt AD."); + return -1; + } + + return 0; +} + +int ead_update_ad(void) +{ + int err; + size_t idx = 0; + struct bt_le_ext_adv *adv = adv_sets[selected_adv]; + + struct bt_data *ad; + size_t ad_structs_idx = 0; + struct bt_data ad_structs[BT_SHELL_EAD_MAX_AD] = {0}; + + size_t encrypted_data_buf_len = 0; + uint8_t encrypted_data_buf[BT_SHELL_EAD_DATA_MAX_SIZE] = {0}; + + while (idx < bt_shell_ead_data_size && ad_structs_idx < BT_SHELL_EAD_MAX_AD) { + ad = &ad_structs[ad_structs_idx]; + + /* the data_len from bt_data struct doesn't include the size of the type */ + ad->data_len = bt_shell_ead_data[idx] - 1; + + if (ad->data_len < 0) { + /* if the len is less than 0 that mean there is not even a type field */ + shell_error(ctx_shell, "Failed to update AD due to malformed AD."); + return -ENOEXEC; + } + + ad->type = bt_shell_ead_data[idx + 1]; + + if (ad->data_len > 0) { + if (ad->type == BT_DATA_ENCRYPTED_AD_DATA) { + /* for EAD the size used to store the non-encrypted data + * is the size of those data when encrypted + */ + ead_encrypt_ad(&bt_shell_ead_data[idx + 2], + BT_EAD_DECRYPTED_PAYLOAD_SIZE(ad->data_len), + &encrypted_data_buf[encrypted_data_buf_len]); + + ad->data = &encrypted_data_buf[encrypted_data_buf_len]; + encrypted_data_buf_len += ad->data_len; + } else { + ad->data = &bt_shell_ead_data[idx + 2]; + } + } + + ad_structs_idx += 1; + idx += ad->data_len + 2; + } + + err = bt_le_ext_adv_set_data(adv, ad_structs, bt_shell_ead_ad_len, NULL, 0); + if (err != 0) { + shell_error(ctx_shell, "Failed to set advertising data (err %d)", err); + return -ENOEXEC; + } + + shell_info(ctx_shell, "Advertising data for Advertiser[%d] %p updated.", selected_adv, adv); + + return 0; +} + +static int cmd_encrypted_ad_commit_ad(const struct shell *sh, size_t argc, char *argv[]) +{ + return ead_update_ad(); +} + +static int cmd_encrypted_ad_decrypt_scan(const struct shell *sh, size_t argc, char *argv[]) +{ + const char *action = argv[1]; + + if (strcmp(action, "on") == 0) { + bt_shell_ead_decrypt_scan = true; + shell_info(sh, "Received encrypted advertising data will now be decrypted using " + "provided key materials."); + } else if (strcmp(action, "off") == 0) { + bt_shell_ead_decrypt_scan = false; + shell_info(sh, "Received encrypted advertising data will now longer be decrypted."); + } else { + shell_error(sh, "Invalid option."); + return -ENOEXEC; + } + + return 0; +} +#endif + static int cmd_default_handler(const struct shell *sh, size_t argc, char **argv) { if (argc == 1) { @@ -4174,6 +4497,19 @@ SHELL_STATIC_SUBCMD_SET_CREATE(bt_scan_filter_clear_cmds, ); #endif /* CONFIG_BT_OBSERVER */ +#if defined(CONFIG_BT_EAD) +SHELL_STATIC_SUBCMD_SET_CREATE( + bt_encrypted_ad_cmds, + SHELL_CMD_ARG(set-keys, NULL, " ", cmd_encrypted_ad_set_keys, 3, + 0), + SHELL_CMD_ARG(add-ead, NULL, "", cmd_encrypted_ad_add_ead, 2, 0), + SHELL_CMD_ARG(add-ad, NULL, "", cmd_encrypted_ad_add_ad, 2, 0), + SHELL_CMD(clear-ad, NULL, HELP_NONE, cmd_encrypted_ad_clear_ad), + SHELL_CMD(commit-ad, NULL, HELP_NONE, cmd_encrypted_ad_commit_ad), + SHELL_CMD_ARG(decrypt-scan, NULL, HELP_ONOFF, cmd_encrypted_ad_decrypt_scan, 2, 0), + SHELL_SUBCMD_SET_END); +#endif + SHELL_STATIC_SUBCMD_SET_CREATE(bt_cmds, SHELL_CMD_ARG(init, NULL, "[no-settings-load], [sync]", cmd_init, 1, 2), @@ -4262,6 +4598,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE(bt_cmds, cmd_per_adv_sync_delete, 1, 1), SHELL_CMD_ARG(per-adv-sync-select, NULL, "[adv]", cmd_per_adv_sync_select, 1, 1), #endif /* defined(CONFIG_BT_PER_ADV_SYNC) */ +#if defined(CONFIG_BT_EAD) + SHELL_CMD(encrypted-ad, &bt_encrypted_ad_cmds, "Manage advertiser with encrypted data", + cmd_default_handler), +#endif /* CONFIG_BT_EAD */ #if defined(CONFIG_BT_CONN) #if defined(CONFIG_BT_PER_ADV_SYNC_TRANSFER_RECEIVER) SHELL_CMD_ARG(past-subscribe, NULL, "[conn] [skip ] " diff --git a/tests/bluetooth/shell/prj.conf b/tests/bluetooth/shell/prj.conf index 168ccf62a7f..185167de1d1 100644 --- a/tests/bluetooth/shell/prj.conf +++ b/tests/bluetooth/shell/prj.conf @@ -46,6 +46,8 @@ CONFIG_BT_PER_ADV_SYNC=y CONFIG_BT_USER_DATA_LEN_UPDATE=y CONFIG_BT_AUTO_DATA_LEN_UPDATE=y +CONFIG_BT_EAD=y + CONFIG_BT_USER_PHY_UPDATE=y CONFIG_BT_AUTO_PHY_UPDATE=y From 2d2e35b766244665b81d8e56b1264fddbca42157 Mon Sep 17 00:00:00 2001 From: Ryan Erickson Date: Mon, 11 Mar 2024 11:29:23 -0500 Subject: [PATCH 0611/2402] boards: mg100: add hl7800 node label Add HL7800 modem node label. Signed-off-by: Ryan Erickson --- boards/lairdconnect/mg100/mg100.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/lairdconnect/mg100/mg100.dts b/boards/lairdconnect/mg100/mg100.dts index 67f4b3677a5..7c6fbb92d24 100644 --- a/boards/lairdconnect/mg100/mg100.dts +++ b/boards/lairdconnect/mg100/mg100.dts @@ -106,7 +106,7 @@ pinctrl-0 = <&uart1_default>; pinctrl-1 = <&uart1_sleep>; pinctrl-names = "default", "sleep"; - hl7800 { + hl7800: hl7800 { compatible = "swir,hl7800"; status = "okay"; mdm-reset-gpios = <&gpio1 15 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; From 971b3e2826e2131b72e827e8e1c3e5292ec491d8 Mon Sep 17 00:00:00 2001 From: Ryan Erickson Date: Mon, 11 Mar 2024 11:30:05 -0500 Subject: [PATCH 0612/2402] boards: pinnacle_100_dvk: add hl7800 node label Add HL7800 modem node label. Signed-off-by: Ryan Erickson --- boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts index b50c526be4c..1e3006dd0d3 100644 --- a/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts +++ b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts @@ -122,7 +122,7 @@ pinctrl-0 = <&uart1_default>; pinctrl-1 = <&uart1_sleep>; pinctrl-names = "default", "sleep"; - hl7800 { + hl7800: hl7800 { compatible = "swir,hl7800"; status = "okay"; mdm-reset-gpios = <&gpio1 15 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; From 06c62e4c1770f2fcd082bf50669a1869e17b4c73 Mon Sep 17 00:00:00 2001 From: Ryan Erickson Date: Mon, 11 Mar 2024 12:41:47 -0500 Subject: [PATCH 0613/2402] modem: modem_cellular: fixes for hl7800 Add connect match for dialing PPP connection. Ensure PDP authentication is disabled. Request manufacturer, firmware version, and IMSI from the modem. Signed-off-by: Ryan Erickson --- drivers/modem/modem_cellular.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 7c9e6728533..1c8e9b08347 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -443,6 +443,10 @@ MODEM_CHAT_MATCHES_DEFINE(dial_abort_matches, MODEM_CHAT_MATCH("NO CARRIER", "", NULL), MODEM_CHAT_MATCH("NO DIALTONE", "", NULL)); +#if DT_HAS_COMPAT_STATUS_OKAY(swir_hl7800) +MODEM_CHAT_MATCH_DEFINE(connect_match, "CONNECT", "", NULL); +#endif + static void modem_cellular_log_state_changed(enum modem_cellular_state last_state, enum modem_cellular_state new_state) { @@ -1854,6 +1858,13 @@ MODEM_CHAT_SCRIPT_CMDS_DEFINE(swir_hl7800_init_chat_script_cmds, MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGSN", imei_match), MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMM", cgmm_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMI", cgmi_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMR", cgmr_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CIMI", cimi_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT+CMUX=0,0,5,127", 0)); MODEM_CHAT_SCRIPT_DEFINE(swir_hl7800_init_chat_script, swir_hl7800_init_chat_script_cmds, @@ -1867,8 +1878,9 @@ MODEM_CHAT_SCRIPT_CMDS_DEFINE(swir_hl7800_dial_chat_script_cmds, CONFIG_MODEM_CELLULAR_APN "\",,,\"IPV4\"", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+WPPP=0", ok_match), MODEM_CHAT_SCRIPT_CMD_RESP("AT+CFUN=1", ok_match), - MODEM_CHAT_SCRIPT_CMD_RESP_NONE("ATD*99***1#", 0)); + MODEM_CHAT_SCRIPT_CMD_RESP("ATD*99***1#", connect_match)); MODEM_CHAT_SCRIPT_CMDS_DEFINE(swir_hl7800_periodic_chat_script_cmds, MODEM_CHAT_SCRIPT_CMD_RESP("AT+CREG?", ok_match), From cf628c67794f3fb105e0ec09acf789899d2568fa Mon Sep 17 00:00:00 2001 From: Ryan Erickson Date: Mon, 11 Mar 2024 11:36:35 -0500 Subject: [PATCH 0614/2402] samples: net: cellular_modem: fix kconfig warning for logging Logging needs to be on for CONFIG_MODEM_MODULES_LOG_LEVEL_DBG to work. Signed-off-by: Ryan Erickson --- samples/net/cellular_modem/prj.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/samples/net/cellular_modem/prj.conf b/samples/net/cellular_modem/prj.conf index ab44ca9528e..3bd03d662d6 100644 --- a/samples/net/cellular_modem/prj.conf +++ b/samples/net/cellular_modem/prj.conf @@ -24,5 +24,6 @@ CONFIG_PM_DEVICE=y CONFIG_MODEM_CELLULAR=y # Logging +CONFIG_LOG=y CONFIG_MODEM_MODULES_LOG_LEVEL_DBG=y #CONFIG_MODEM_CMUX_LOG_LEVEL_DBG=y From ebd74fe33268c48d3e4ac5c40b8d8fb7152005b6 Mon Sep 17 00:00:00 2001 From: Ryan Erickson Date: Mon, 11 Mar 2024 11:37:24 -0500 Subject: [PATCH 0615/2402] samples: net: cellular_modem: add pinnacle 100 support Add support for Pinnacle 100 DVK. Signed-off-by: Ryan Erickson --- samples/net/cellular_modem/boards/pinnacle_100_dvk.conf | 2 ++ samples/net/cellular_modem/boards/pinnacle_100_dvk.overlay | 6 ++++++ 2 files changed, 8 insertions(+) create mode 100644 samples/net/cellular_modem/boards/pinnacle_100_dvk.conf create mode 100644 samples/net/cellular_modem/boards/pinnacle_100_dvk.overlay diff --git a/samples/net/cellular_modem/boards/pinnacle_100_dvk.conf b/samples/net/cellular_modem/boards/pinnacle_100_dvk.conf new file mode 100644 index 00000000000..c19245d045f --- /dev/null +++ b/samples/net/cellular_modem/boards/pinnacle_100_dvk.conf @@ -0,0 +1,2 @@ +CONFIG_MODEM_HL7800=n +CONFIG_UART_ASYNC_API=y diff --git a/samples/net/cellular_modem/boards/pinnacle_100_dvk.overlay b/samples/net/cellular_modem/boards/pinnacle_100_dvk.overlay new file mode 100644 index 00000000000..862ae86a094 --- /dev/null +++ b/samples/net/cellular_modem/boards/pinnacle_100_dvk.overlay @@ -0,0 +1,6 @@ +/ { + aliases { + modem-uart = &uart1; + modem = &hl7800; + }; +}; From 2ca67b56fbdf05aad2a2299a96f3b323e6825e62 Mon Sep 17 00:00:00 2001 From: Ryan Erickson Date: Mon, 11 Mar 2024 11:37:58 -0500 Subject: [PATCH 0616/2402] samples: net: cellular_modem: add mg100 support Add support for mg100 gateway. Signed-off-by: Ryan Erickson --- samples/net/cellular_modem/boards/mg100.conf | 2 ++ samples/net/cellular_modem/boards/mg100.overlay | 6 ++++++ 2 files changed, 8 insertions(+) create mode 100644 samples/net/cellular_modem/boards/mg100.conf create mode 100644 samples/net/cellular_modem/boards/mg100.overlay diff --git a/samples/net/cellular_modem/boards/mg100.conf b/samples/net/cellular_modem/boards/mg100.conf new file mode 100644 index 00000000000..c19245d045f --- /dev/null +++ b/samples/net/cellular_modem/boards/mg100.conf @@ -0,0 +1,2 @@ +CONFIG_MODEM_HL7800=n +CONFIG_UART_ASYNC_API=y diff --git a/samples/net/cellular_modem/boards/mg100.overlay b/samples/net/cellular_modem/boards/mg100.overlay new file mode 100644 index 00000000000..862ae86a094 --- /dev/null +++ b/samples/net/cellular_modem/boards/mg100.overlay @@ -0,0 +1,6 @@ +/ { + aliases { + modem-uart = &uart1; + modem = &hl7800; + }; +}; From 685b3d2d3daf73677f321335938e604c82c59ce5 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 15:14:25 -0500 Subject: [PATCH 0617/2402] boards: nxp: rd_rw612_bga: set CONFIG_TRUSTED_EXECUTION_SECURE RD RW612 BGA board is built targeting secure mode execution. If CONFIG_TRUSTED_EXECUTION_SECURE is not set, base address declarations in CMSIS header files will be incorrect, causing a variety of issues. Fix this. Signed-off-by: Daniel DeGrasse --- boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig b/boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig index 33107fc36b9..b987fa24dc0 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig @@ -12,3 +12,4 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y +CONFIG_TRUSTED_EXECUTION_SECURE=y From f82cacbab83b3f8a80c43f9021f248f7261b91e3 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Mon, 12 Feb 2024 15:05:11 +0200 Subject: [PATCH 0618/2402] dts: xtensa: nxp_imx8: add EDMA0 node Add node for NXP's i.MX8QM/i.MX8QXP AUDIO EDMA0 IP. Signed-off-by: Laurentiu Mihalcea --- dts/xtensa/nxp/nxp_imx8.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/dts/xtensa/nxp/nxp_imx8.dtsi b/dts/xtensa/nxp/nxp_imx8.dtsi index 6d20f56fcd4..80b715a7f16 100644 --- a/dts/xtensa/nxp/nxp_imx8.dtsi +++ b/dts/xtensa/nxp/nxp_imx8.dtsi @@ -114,6 +114,16 @@ reg = <0x92c00000 DT_SIZE_K(512)>; }; + edma0: dma@591f0000 { + compatible = "nxp,edma"; + reg = <0x591f0000 (DT_SIZE_K(64) * 33)>; + valid-channels = <6>, <7>, <14>, <15>; + interrupts-extended = <&master6 58>, <&master6 58>, + <&master5 29>, <&master5 29>; + #dma-cells = <2>; + status = "disabled"; + }; + /* LSIO MU2, used to interact with the SCFW */ scu_mu: mailbox@5d1d0000 { reg = <0x5d1d0000 DT_SIZE_K(64)>; From 8c2b55d97d97c9c0128881dcf2cf25ed4364fa8b Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Sun, 30 Jul 2023 05:23:42 -0500 Subject: [PATCH 0619/2402] dts: nxp: Add binding for NXP Flexcomm device This binding is for the NXP FlexComm Interface. The driver will setup an interface for use as a UART, SPI or I2C device. Signed-off-by: Mahesh Mahadevan --- dts/bindings/mfd/nxp,lp-flexcomm.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 dts/bindings/mfd/nxp,lp-flexcomm.yaml diff --git a/dts/bindings/mfd/nxp,lp-flexcomm.yaml b/dts/bindings/mfd/nxp,lp-flexcomm.yaml new file mode 100644 index 00000000000..5c6f96246a7 --- /dev/null +++ b/dts/bindings/mfd/nxp,lp-flexcomm.yaml @@ -0,0 +1,16 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +description: Low Power Flexcomm + +compatible: "nxp,lp-flexcomm" + +include: [base.yaml] + +properties: + reg: + required: true + + interrupts: + required: true From 72fd8d14da1ac5b78aa0676c5462502ab9c56baf Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Sun, 30 Jul 2023 05:27:30 -0500 Subject: [PATCH 0620/2402] drivers: mfd: Add NXP LP Flexcomm driver 1. This driver allows to configure the Low Power Flexcomm interface as a UART, SPI or I2C device. 2. Manages the interrupts and dispatches it to the appropriate device driver. 3. A Flexcomm interface can be configured to be used as I2C and UART device. However a SPI device cannot be used concurrently with I2C or UART. Add checks for this feature. Signed-off-by: Mahesh Mahadevan --- drivers/mfd/CMakeLists.txt | 1 + drivers/mfd/Kconfig | 1 + drivers/mfd/Kconfig.lpflexcomm | 14 ++ drivers/mfd/mfd_nxp_lp_flexcomm.c | 169 +++++++++++++++++++ include/zephyr/drivers/mfd/nxp_lp_flexcomm.h | 16 ++ 5 files changed, 201 insertions(+) create mode 100644 drivers/mfd/Kconfig.lpflexcomm create mode 100644 drivers/mfd/mfd_nxp_lp_flexcomm.c create mode 100644 include/zephyr/drivers/mfd/nxp_lp_flexcomm.h diff --git a/drivers/mfd/CMakeLists.txt b/drivers/mfd/CMakeLists.txt index 5141a86c2ee..8c45cb181bf 100644 --- a/drivers/mfd/CMakeLists.txt +++ b/drivers/mfd/CMakeLists.txt @@ -9,3 +9,4 @@ zephyr_library_sources_ifdef(CONFIG_MFD_NPM1300 mfd_npm1300.c) zephyr_library_sources_ifdef(CONFIG_MFD_NPM6001 mfd_npm6001.c) zephyr_library_sources_ifdef(CONFIG_MFD_AXP192 mfd_axp192.c) zephyr_library_sources_ifdef(CONFIG_MFD_AD5592 mfd_ad5592.c) +zephyr_library_sources_ifdef(CONFIG_NXP_LP_FLEXCOMM mfd_nxp_lp_flexcomm.c) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 1a400d6383e..2ffdcbcca52 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -24,5 +24,6 @@ source "drivers/mfd/Kconfig.max20335" source "drivers/mfd/Kconfig.nct38xx" source "drivers/mfd/Kconfig.npm1300" source "drivers/mfd/Kconfig.npm6001" +source "drivers/mfd/Kconfig.lpflexcomm" endif # MFD diff --git a/drivers/mfd/Kconfig.lpflexcomm b/drivers/mfd/Kconfig.lpflexcomm new file mode 100644 index 00000000000..d59faa9b89b --- /dev/null +++ b/drivers/mfd/Kconfig.lpflexcomm @@ -0,0 +1,14 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config NXP_LP_FLEXCOMM + bool "Driver for the NXP Low Power FlexComm Interface" + default y + depends on DT_HAS_NXP_LP_FLEXCOMM_ENABLED + help + Enabled the Low Power FlexComm shim driver. + LP FLexcomm allows enablement of LPUART and LPI2C + at the same time with reduced interface. This driver + checks concurrent enablement and returns and error for + unsupported concurrent enablement. diff --git a/drivers/mfd/mfd_nxp_lp_flexcomm.c b/drivers/mfd/mfd_nxp_lp_flexcomm.c new file mode 100644 index 00000000000..ec6a325d3d0 --- /dev/null +++ b/drivers/mfd/mfd_nxp_lp_flexcomm.c @@ -0,0 +1,169 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_lp_flexcomm + +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(mfd_nxp_lp_flexcomm, CONFIG_MFD_LOG_LEVEL); + +struct nxp_lp_flexcomm_child { + const struct device *dev; + uint8_t periph; + child_isr_t lp_flexcomm_child_isr; +}; + +struct nxp_lp_flexcomm_data { + struct nxp_lp_flexcomm_child *children; + size_t num_children; +}; + +struct nxp_lp_flexcomm_config { + LP_FLEXCOMM_Type *base; + void (*irq_config_func)(const struct device *dev); +}; + +void nxp_lp_flexcomm_isr(const struct device *dev) +{ + uint32_t interrupt_status; + const struct nxp_lp_flexcomm_config *config = dev->config; + struct nxp_lp_flexcomm_data *data = dev->data; + uint32_t instance = LP_FLEXCOMM_GetInstance(config->base); + struct nxp_lp_flexcomm_child *child; + + interrupt_status = LP_FLEXCOMM_GetInterruptStatus(instance); + if ((interrupt_status & + ((uint32_t)kLPFLEXCOMM_I2cSlaveInterruptFlag | + (uint32_t)kLPFLEXCOMM_I2cMasterInterruptFlag)) != 0U) { + child = &data->children[LP_FLEXCOMM_PERIPH_LPI2C]; + + if (child->lp_flexcomm_child_isr != NULL) { + child->lp_flexcomm_child_isr(child->dev); + } + } + if ((interrupt_status & + ((uint32_t)kLPFLEXCOMM_UartRxInterruptFlag | + (uint32_t)kLPFLEXCOMM_UartTxInterruptFlag)) != 0U) { + child = &data->children[LP_FLEXCOMM_PERIPH_LPUART]; + + if (child->lp_flexcomm_child_isr != NULL) { + child->lp_flexcomm_child_isr(child->dev); + } + } + if (((interrupt_status & + (uint32_t)kLPFLEXCOMM_SpiInterruptFlag)) != 0U) { + child = &data->children[LP_FLEXCOMM_PERIPH_LPSPI]; + + if (child->lp_flexcomm_child_isr != NULL) { + child->lp_flexcomm_child_isr(child->dev); + } + } +} + +void nxp_lp_flexcomm_setirqhandler(const struct device *dev, const struct device *child_dev, + LP_FLEXCOMM_PERIPH_T periph, child_isr_t handler) +{ + struct nxp_lp_flexcomm_data *data = dev->data; + struct nxp_lp_flexcomm_child *child; + + child = &data->children[periph]; + + /* Store the interrupt handler and the child device node */ + child->lp_flexcomm_child_isr = handler; + child->dev = child_dev; +} + +static int nxp_lp_flexcomm_init(const struct device *dev) +{ + const struct nxp_lp_flexcomm_config *config = dev->config; + struct nxp_lp_flexcomm_data *data = dev->data; + uint32_t instance; + struct nxp_lp_flexcomm_child *child = NULL; + bool spi_found = false; + bool uart_found = false; + bool i2c_found = false; + + for (int i = 1; i < data->num_children; i++) { + child = &data->children[i]; + if (child->periph == LP_FLEXCOMM_PERIPH_LPSPI) { + spi_found = true; + } + if (child->periph == LP_FLEXCOMM_PERIPH_LPI2C) { + i2c_found = true; + } + if (child->periph == LP_FLEXCOMM_PERIPH_LPUART) { + uart_found = true; + } + } + + /* If SPI is enabled with another interface type return an error */ + if (spi_found && (i2c_found || uart_found)) { + return -EINVAL; + } + + instance = LP_FLEXCOMM_GetInstance(config->base); + + if (uart_found && i2c_found) { + LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2CAndLPUART); + } else if (uart_found) { + LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPUART); + } else if (i2c_found) { + LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2C); + } else if (spi_found) { + LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPSPI); + } + + config->irq_config_func(dev); + + return 0; +} + +#define MCUX_FLEXCOMM_CHILD_INIT(child_node_id) \ + [DT_NODE_CHILD_IDX(child_node_id) + 1] = { \ + .periph = DT_NODE_CHILD_IDX(child_node_id) + 1, \ + }, + +#define NXP_LP_FLEXCOMM_INIT(n) \ + \ + static struct nxp_lp_flexcomm_child \ + nxp_lp_flexcomm_children_##n[LP_FLEXCOMM_PERIPH_LPI2C + 1] = { \ + DT_INST_FOREACH_CHILD_STATUS_OKAY(n, MCUX_FLEXCOMM_CHILD_INIT) \ + }; \ + \ + static void nxp_lp_flexcomm_config_func_##n(const struct device *dev); \ + \ + static const struct nxp_lp_flexcomm_config nxp_lp_flexcomm_config_##n = { \ + .base = (LP_FLEXCOMM_Type *)DT_INST_REG_ADDR(n), \ + .irq_config_func = nxp_lp_flexcomm_config_func_##n, \ + }; \ + \ + static struct nxp_lp_flexcomm_data nxp_lp_flexcomm_data_##n = { \ + .children = nxp_lp_flexcomm_children_##n, \ + .num_children = ARRAY_SIZE(nxp_lp_flexcomm_children_##n), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, \ + &nxp_lp_flexcomm_init, \ + NULL, \ + &nxp_lp_flexcomm_data_##n, \ + &nxp_lp_flexcomm_config_##n, \ + PRE_KERNEL_1, \ + CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \ + NULL); \ + \ + static void nxp_lp_flexcomm_config_func_##n(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ + nxp_lp_flexcomm_isr, DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + } + +DT_INST_FOREACH_STATUS_OKAY(NXP_LP_FLEXCOMM_INIT) diff --git a/include/zephyr/drivers/mfd/nxp_lp_flexcomm.h b/include/zephyr/drivers/mfd/nxp_lp_flexcomm.h new file mode 100644 index 00000000000..0faed3c9ddf --- /dev/null +++ b/include/zephyr/drivers/mfd/nxp_lp_flexcomm.h @@ -0,0 +1,16 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_DRIVERS_NXP_LP_FLEXCOMM_H_ +#define ZEPHYR_DRIVERS_NXP_LP_FLEXCOMM_H_ + +#include "fsl_lpflexcomm.h" + +typedef void (*child_isr_t)(const struct device *dev); + +void nxp_lp_flexcomm_setirqhandler(const struct device *dev, const struct device *child_dev, + LP_FLEXCOMM_PERIPH_T periph, child_isr_t handler); + +#endif /* ZEPHYR_DRIVERS_NXP_LP_FLEXCOMM_H_ */ From 301ebf83f3abe3931be78ea7b627b034611d5dd2 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 12 Mar 2024 13:57:45 -0500 Subject: [PATCH 0621/2402] drivers: uart: Use the NXP Flexcomm driver to interrupt handling The Low Power Flexcomm driver manages the interrupt handling and provides an API to register interrupt callbacks. Register the NXP LPUART interrupt handler. Signed-off-by: Mahesh Mahadevan --- drivers/serial/Kconfig.mcux_lpuart | 1 + drivers/serial/uart_mcux_lpuart.c | 24 +++++++++++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/serial/Kconfig.mcux_lpuart b/drivers/serial/Kconfig.mcux_lpuart index 5833c49268e..71c0a41663b 100644 --- a/drivers/serial/Kconfig.mcux_lpuart +++ b/drivers/serial/Kconfig.mcux_lpuart @@ -13,6 +13,7 @@ config UART_MCUX_LPUART select SERIAL_SUPPORT_ASYNC select DMA if UART_ASYNC_API select PINCTRL + select MFD if DT_HAS_NXP_LP_FLEXCOMM_ENABLED help Enable the MCUX LPUART driver. diff --git a/drivers/serial/uart_mcux_lpuart.c b/drivers/serial/uart_mcux_lpuart.c index 17604e92086..5bc8f126712 100644 --- a/drivers/serial/uart_mcux_lpuart.c +++ b/drivers/serial/uart_mcux_lpuart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017,2021 NXP + * Copyright 2017,2021,2023-2024 NXP * Copyright (c) 2020 Softube * * SPDX-License-Identifier: Apache-2.0 @@ -21,6 +21,9 @@ #include #include +#if CONFIG_NXP_LP_FLEXCOMM +#include +#endif LOG_MODULE_REGISTER(uart_mcux_lpuart, LOG_LEVEL_ERR); @@ -36,6 +39,9 @@ struct lpuart_dma_config { struct mcux_lpuart_config { LPUART_Type *base; +#ifdef CONFIG_NXP_LP_FLEXCOMM + const struct device *parent_dev; +#endif const struct device *clock_dev; const struct pinctrl_dev_config *pincfg; clock_control_subsys_t clock_subsys; @@ -1077,8 +1083,17 @@ static int mcux_lpuart_init(const struct device *dev) } #ifdef CONFIG_UART_MCUX_LPUART_ISR_SUPPORT +#if CONFIG_NXP_LP_FLEXCOMM + /* When using LP Flexcomm driver, register the interrupt handler + * so we receive notification from the LP Flexcomm interrupt handler. + */ + nxp_lp_flexcomm_setirqhandler(config->parent_dev, dev, + LP_FLEXCOMM_PERIPH_LPUART, mcux_lpuart_isr); +#else + /* Interrupt is managed by this driver */ config->irq_config_func(dev); #endif +#endif #ifdef CONFIG_PM data->pm_state_lock_on = false; @@ -1205,10 +1220,17 @@ static const struct uart_driver_api mcux_lpuart_driver_api = { : DT_INST_PROP(n, nxp_rs485_mode)\ ? UART_CFG_FLOW_CTRL_RS485 \ : UART_CFG_FLOW_CTRL_NONE +#ifdef CONFIG_NXP_LP_FLEXCOMM +#define PARENT_DEV(n) \ + .parent_dev = DEVICE_DT_GET(DT_INST_PARENT(n)), +#else +#define PARENT_DEV(n) +#endif /* CONFIG_NXP_LP_FLEXCOMM */ #define LPUART_MCUX_DECLARE_CFG(n) \ static const struct mcux_lpuart_config mcux_lpuart_##n##_config = { \ .base = (LPUART_Type *) DT_INST_REG_ADDR(n), \ + PARENT_DEV(n) \ .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \ .baud_rate = DT_INST_PROP(n, current_speed), \ From 742a8e85d8036dfb31ac3c37f03c8b1732c41bf3 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Wed, 24 Jan 2024 23:12:24 +0000 Subject: [PATCH 0622/2402] drivers: clock: Enable PORT & LP Flexcomm in NXP syscon driver 1. Add support to enable PORT control clocks 2. Add support for LP Flexcomm 3. MCX family has a different Clock API for USDHC. Signed-off-by: Mahesh Mahadevan --- .../clock_control/clock_control_mcux_syscon.c | 64 ++++++++++++++++++- .../dt-bindings/clock/mcux_lpc_syscon_clock.h | 9 ++- 2 files changed, 71 insertions(+), 2 deletions(-) diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index 61eb0481abf..32074ea224d 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-23, NXP + * Copyright 2020-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -33,6 +33,28 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev, } #endif /* defined(CONFIG_COUNTER_NXP_MRT) */ +#if defined(CONFIG_PINCTRL_NXP_KINETIS) + switch ((uint32_t)sub_system) { + case MCUX_PORT0_CLK: + CLOCK_EnableClock(kCLOCK_Port0); + break; + case MCUX_PORT1_CLK: + CLOCK_EnableClock(kCLOCK_Port1); + break; + case MCUX_PORT2_CLK: + CLOCK_EnableClock(kCLOCK_Port2); + break; + case MCUX_PORT3_CLK: + CLOCK_EnableClock(kCLOCK_Port3); + break; + case MCUX_PORT4_CLK: + CLOCK_EnableClock(kCLOCK_Port4); + break; + default: + break; + } +#endif /* defined(CONFIG_PINCTRL_NXP_KINETIS) */ + return 0; } @@ -109,9 +131,47 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( case MCUX_HS_SPI1_CLK: *rate = CLOCK_GetFlexCommClkFreq(16); break; +#elif defined(CONFIG_NXP_LP_FLEXCOMM) + case MCUX_FLEXCOMM0_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(0); + break; + case MCUX_FLEXCOMM1_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(1); + break; + case MCUX_FLEXCOMM2_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(2); + break; + case MCUX_FLEXCOMM3_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(3); + break; + case MCUX_FLEXCOMM4_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(4); + break; + case MCUX_FLEXCOMM5_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(5); + break; + case MCUX_FLEXCOMM6_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(6); + break; + case MCUX_FLEXCOMM7_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(7); + break; + case MCUX_FLEXCOMM8_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(8); + break; + case MCUX_FLEXCOMM9_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(9); + break; + #endif #if (defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT) + +#if CONFIG_SOC_FAMILY_NXP_MCX + case MCUX_USDHC1_CLK: + *rate = CLOCK_GetUsdhcClkFreq(); + break; +#else case MCUX_USDHC1_CLK: *rate = CLOCK_GetSdioClkFreq(0); break; @@ -120,6 +180,8 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( break; #endif +#endif + #if (defined(FSL_FEATURE_SOC_SDIF_COUNT) && \ (FSL_FEATURE_SOC_SDIF_COUNT)) && \ CONFIG_MCUX_SDIF diff --git a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h index addf2a349fd..c3965e6cbb5 100644 --- a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2020-2023, NXP + * Copyright 2020-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -59,4 +59,11 @@ #define MCUX_MRT_CLK 40 +#define MCUX_PORT0_CLK 41 +#define MCUX_PORT1_CLK 42 +#define MCUX_PORT2_CLK 43 +#define MCUX_PORT3_CLK 44 +#define MCUX_PORT4_CLK 45 +#define MCUX_PORT5_CLK 46 + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */ From bb9386473b6d6de97553d0fc1ec310fb87d81a96 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Mon, 11 Mar 2024 14:11:43 -0500 Subject: [PATCH 0623/2402] dts: nxp_lpuart: Interrupts is no longer a required property Some NXP SoC's have a FlexComm interface which manages interrupts. Signed-off-by: Mahesh Mahadevan --- drivers/serial/uart_mcux_lpuart.c | 3 ++- dts/bindings/serial/nxp,kinetis-lpuart.yaml | 3 --- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/serial/uart_mcux_lpuart.c b/drivers/serial/uart_mcux_lpuart.c index 5bc8f126712..e434860a264 100644 --- a/drivers/serial/uart_mcux_lpuart.c +++ b/drivers/serial/uart_mcux_lpuart.c @@ -1152,7 +1152,8 @@ static const struct uart_driver_api mcux_lpuart_driver_api = { #define MCUX_LPUART_IRQ_DEFINE(n) \ static void mcux_lpuart_config_func_##n(const struct device *dev) \ { \ - MCUX_LPUART_IRQ_INSTALL(n, 0); \ + IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \ + (MCUX_LPUART_IRQ_INSTALL(n, 0);)) \ \ IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 1), \ (MCUX_LPUART_IRQ_INSTALL(n, 1);)) \ diff --git a/dts/bindings/serial/nxp,kinetis-lpuart.yaml b/dts/bindings/serial/nxp,kinetis-lpuart.yaml index 8fbf2f2bd22..1b8f5400722 100644 --- a/dts/bindings/serial/nxp,kinetis-lpuart.yaml +++ b/dts/bindings/serial/nxp,kinetis-lpuart.yaml @@ -8,9 +8,6 @@ properties: reg: required: true - interrupts: - required: true - nxp,loopback: type: boolean description: | From 61d1a711fc0240beeec13f08eb66323baf61b20c Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 12 Mar 2024 13:52:08 -0500 Subject: [PATCH 0624/2402] drivers: uart: Use the register define instead of enum define The enum define is not implemented with the same name on all SoC's. Use the register define instead. Signed-off-by: Mahesh Mahadevan --- drivers/serial/uart_mcux_lpuart.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/serial/uart_mcux_lpuart.c b/drivers/serial/uart_mcux_lpuart.c index e434860a264..0ac8bff42f6 100644 --- a/drivers/serial/uart_mcux_lpuart.c +++ b/drivers/serial/uart_mcux_lpuart.c @@ -150,7 +150,7 @@ static void mcux_lpuart_poll_out(const struct device *dev, unsigned char c) #endif while (!(LPUART_GetStatusFlags(config->base) - & kLPUART_TxDataRegEmptyFlag)) { + & LPUART_STAT_TDRE_MASK)) { } /* Lock interrupts while we send data */ key = irq_lock(); @@ -215,7 +215,7 @@ static int mcux_lpuart_fifo_fill(const struct device *dev, while ((len - num_tx > 0) && (LPUART_GetStatusFlags(config->base) - & kLPUART_TxDataRegEmptyFlag)) { + & LPUART_STAT_TDRE_MASK)) { LPUART_WriteByte(config->base, tx_data[num_tx++]); } @@ -301,7 +301,7 @@ static int mcux_lpuart_irq_tx_ready(const struct device *dev) uint32_t flags = LPUART_GetStatusFlags(config->base); return (LPUART_GetEnabledInterrupts(config->base) & mask) - && (flags & kLPUART_TxDataRegEmptyFlag); + && (flags & LPUART_STAT_TDRE_MASK); } static void mcux_lpuart_irq_rx_enable(const struct device *dev) From 879fe74dcd3ad19f0e8b4617996a1b3f19f5454e Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Thu, 23 Feb 2023 20:49:10 -0600 Subject: [PATCH 0625/2402] dts: pinctrl: Add input buffer for kinetis pinctrl Some versions that use the kinetis pinctrl use the input buffer Signed-off-by: Mahesh Mahadevan --- dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml b/dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml index c5b2f5d6020..819ab7e2ab7 100644 --- a/dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml +++ b/dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml @@ -1,4 +1,4 @@ -# Copyright (c) 2022-2023, NXP +# Copyright 2022-2024 NXP # SPDX-License-Identifier: Apache-2.0 description: | @@ -44,6 +44,7 @@ child-binding: - drive-open-drain - bias-pull-up - bias-pull-down + - input-enable properties: pinmux: From 205a8fed793f1f6e8e209e853f1df864e2d94524 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Wed, 22 Feb 2023 14:26:55 -0600 Subject: [PATCH 0626/2402] drivers: pinctrl: Add support for more ports MCX has more port modules which requires updating the pinctrl driver Signed-off-by: Mahesh Mahadevan --- drivers/pinctrl/pinctrl_kinetis.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl_kinetis.c b/drivers/pinctrl/pinctrl_kinetis.c index 45ac0ebe3cf..13b0c8ac720 100644 --- a/drivers/pinctrl/pinctrl_kinetis.c +++ b/drivers/pinctrl/pinctrl_kinetis.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 NXP + * Copyright 2022-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,6 +25,9 @@ static PORT_Type *ports[] = { #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 4 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)), #endif +#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 5 + (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portf)), +#endif }; #define PIN(mux) (((mux) & 0xFC00000) >> 22) From 5254fcbd0ab55856d5f94ded420cb20334814c28 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Tue, 17 Jan 2023 17:19:41 -0600 Subject: [PATCH 0627/2402] drivers: gpio_mcux: Add support for GPIO ICR Add support for devices that use the kinetis GPIO/PORT scheme but with the slight modification that the interrupt control bits are in the GPIO peripheral instead of the PORT peripheral. Signed-off-by: Declan Snyder --- drivers/gpio/gpio_mcux.c | 68 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio_mcux.c b/drivers/gpio/gpio_mcux.c index 6c40460ee69..8fa48abc8c6 100644 --- a/drivers/gpio/gpio_mcux.c +++ b/drivers/gpio/gpio_mcux.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016 Freescale Semiconductor, Inc. - * Copyright (c) 2017, NXP + * Copyright 2017, 2023-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -96,7 +96,7 @@ static int gpio_mcux_configure(const struct device *dev, pcr |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; } else if ((flags & GPIO_PULL_DOWN) != 0) { - /* Enable the pull and select the pulldown resistor (deselect + /* Enable the pull and select the pulldown resistor, deselect * the pullup resistor. */ pcr |= PORT_PCR_PE_MASK; @@ -178,6 +178,7 @@ static int gpio_mcux_port_toggle_bits(const struct device *dev, uint32_t mask) return 0; } +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev, uint32_t pin, enum gpio_int_mode mode, @@ -213,6 +214,54 @@ static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev, return PORT_PCR_IRQC(port_interrupt); } +#endif /* !defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT */ + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \ + FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) + +#define GPIO_MCUX_INTERRUPT_DISABLED 0 +#define GPIO_MCUX_INTERRUPT_LOGIC_0 0x8 +#define GPIO_MCUX_INTERRUPT_RISING_EDGE 0x9 +#define GPIO_MCUX_INTERRUPT_FALLING_EDGE 0xA +#define GPIO_MCUX_INTERRUPT_BOTH_EDGE 0xB +#define GPIO_MCUX_INTERRUPT_LOGIC_1 0xC + +static uint32_t get_gpio_icr_irqc_value_from_flags(const struct device *dev, + uint32_t pin, + enum gpio_int_mode mode, + enum gpio_int_trig trig) +{ + uint8_t gpio_interrupt = 0; + + if (mode == GPIO_INT_MODE_DISABLED) { + gpio_interrupt = GPIO_MCUX_INTERRUPT_DISABLED; + } else { + if (mode == GPIO_INT_MODE_LEVEL) { + if (trig == GPIO_INT_TRIG_LOW) { + gpio_interrupt = GPIO_MCUX_INTERRUPT_LOGIC_0; + } else { + gpio_interrupt = GPIO_MCUX_INTERRUPT_LOGIC_1; + } + } else { + switch (trig) { + case GPIO_INT_TRIG_LOW: + gpio_interrupt = GPIO_MCUX_INTERRUPT_FALLING_EDGE; + break; + case GPIO_INT_TRIG_HIGH: + gpio_interrupt = GPIO_MCUX_INTERRUPT_RISING_EDGE; + break; + case GPIO_INT_TRIG_BOTH: + gpio_interrupt = GPIO_MCUX_INTERRUPT_BOTH_EDGE; + break; + default: + return -EINVAL; + } + } + } + + return GPIO_ICR_IRQC(gpio_interrupt); +} +#endif /* (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) */ static int gpio_mcux_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, enum gpio_int_mode mode, @@ -239,9 +288,16 @@ static int gpio_mcux_pin_interrupt_configure(const struct device *dev, return -ENOTSUP; } +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig); port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr; +#elif (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \ + FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) + uint32_t icr = get_gpio_icr_irqc_value_from_flags(dev, pin, mode, trig); + + gpio_base->ICR[pin] = (gpio_base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | icr; +#endif /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */ return 0; } @@ -260,10 +316,18 @@ static void gpio_mcux_port_isr(const struct device *dev) struct gpio_mcux_data *data = dev->data; uint32_t int_status; +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) int_status = config->port_base->ISFR; /* Clear the port interrupts */ config->port_base->ISFR = int_status; +#elif (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \ + FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) + int_status = config->gpio_base->ISFR[0]; + + /* Clear the gpio interrupts */ + config->gpio_base->ISFR[0] = int_status; +#endif /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */ gpio_fire_callbacks(&data->callbacks, dev, int_status); } From 739b9bc5e90fd1a413c661e000bb8e29b9b59572 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Wed, 22 Feb 2023 14:31:40 -0600 Subject: [PATCH 0628/2402] dts: mcxn94x: Add initial support for NXP MCXN94X Add initial support for NXP MCXN94X Signed-off-by: Mahesh Mahadevan --- dts/arm/nxp/nxp_mcxn94x.dtsi | 38 ++ dts/arm/nxp/nxp_mcxn94x_common.dtsi | 549 ++++++++++++++++++++++++++++ dts/arm/nxp/nxp_mcxn94x_ns.dtsi | 23 ++ 3 files changed, 610 insertions(+) create mode 100644 dts/arm/nxp/nxp_mcxn94x.dtsi create mode 100644 dts/arm/nxp/nxp_mcxn94x_common.dtsi create mode 100644 dts/arm/nxp/nxp_mcxn94x_ns.dtsi diff --git a/dts/arm/nxp/nxp_mcxn94x.dtsi b/dts/arm/nxp/nxp_mcxn94x.dtsi new file mode 100644 index 00000000000..7c594e66eae --- /dev/null +++ b/dts/arm/nxp/nxp_mcxn94x.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + sram: sram@14000000 { + ranges = <0x4000000 0x14000000 0x20000000>; + }; + + peripheral: peripheral@50000000 { + ranges = <0x0 0x50000000 0x10000000>; + + ftfe: flash-controller@43000 { + ranges = <0x0 0x10000000 0x4000000>; + }; + }; + + flexspi: spi@500c8000 { + reg = <0x500c8000 0x1000>, <0x90000000 DT_SIZE_M(8)>; + }; + }; +}; + +#include "nxp_mcxn94x_common.dtsi" + +/* + * Explicitly enable FMU after we include the common dtsi file, + * which will set it to disabled. + */ +&fmu { + status = "okay"; +}; diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi new file mode 100644 index 00000000000..6b32d7823e3 --- /dev/null +++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi @@ -0,0 +1,549 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-m33f"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + cpu@1 { + compatible = "arm,cortex-m33"; + reg = <1>; + }; + }; + + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,kinetis-pinctrl"; + status = "okay"; + }; +}; + +&sram { + #address-cells = <1>; + #size-cells = <1>; + + sramx: memory@4000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x4000000 DT_SIZE_K(96)>; + zephyr,memory-region = "SRAM1"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; + + /* mcxn94x Memory configurations: + * + * RAM blocks RAMA through SRAM4 are contiguous address ranges + * + * MCXN94X: 512KB RAM, RAMX: 96K, RAMA: 32K, RAMB: 32K, + * RAMC: 64K, RAMD: 64K, RAME: 64K + * RAMF: 64K, RAMG: 64K, RAMH: 32K + */ + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(416)>; + }; +}; + +&peripheral { + #address-cells = <1>; + #size-cells = <1>; + + syscon: syscon@0 { + compatible = "nxp,lpc-syscon"; + reg = <0x0 0x4000>; + #clock-cells = <1>; + }; + + porta: pinmux@116000 { + compatible = "nxp,kinetis-pinmux"; + reg = <0x116000 0x1000>; + clocks = <&syscon MCUX_PORT0_CLK>; + }; + + portb: pinmux@117000 { + compatible = "nxp,kinetis-pinmux"; + reg = <0x117000 0x1000>; + clocks = <&syscon MCUX_PORT1_CLK>; + }; + + portc: pinmux@118000 { + compatible = "nxp,kinetis-pinmux"; + reg = <0x118000 0x1000>; + clocks = <&syscon MCUX_PORT2_CLK>; + }; + + portd: pinmux@119000 { + compatible = "nxp,kinetis-pinmux"; + reg = <0x119000 0x1000>; + clocks = <&syscon MCUX_PORT3_CLK>; + }; + + porte: pinmux@11a000 { + compatible = "nxp,kinetis-pinmux"; + reg = <0x11a000 0x1000>; + clocks = <&syscon MCUX_PORT4_CLK>; + }; + + portf: pinmux@42000 { + compatible = "nxp,kinetis-pinmux"; + reg = <0x42000 0x1000>; + clocks = <&syscon MCUX_PORT5_CLK>; + }; + + gpio0: gpio@96000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x96000 0x1000>; + interrupts = <17 0>,<18 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&porta>; + }; + + gpio1: gpio@98000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x98000 0x1000>; + interrupts = <19 0>,<20 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&portb>; + }; + + gpio2: gpio@9a000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x9a000 0x1000>; + interrupts = <21 0>,<22 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&portc>; + }; + + gpio3: gpio@9c000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x9c000 0x1000>; + interrupts = <23 0>,<24 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&portd>; + }; + + gpio4: gpio@9e000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x9e000 0x1000>; + interrupts = <25 0>,<26 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&porte>; + }; + + gpio5: gpio@40000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x40000 0x1000>; + interrupts = <27 0>,<28 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&portf>; + }; + + flexcomm0: flexcomm@92000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x92000 0x1000>; + interrupts = <35 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm0_lpuart0: lpuart@92000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x92000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM0_CLK>; + status = "disabled"; + }; + flexcomm0_lpspi0: lpspi@92000 { + compatible = "nxp,imx-lpspi"; + reg = <0x92000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM0_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm0_lpi2c0: lpi2c@92800 { + compatible = "nxp,imx-lpi2c"; + reg = <0x92800 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM0_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm1: flexcomm@93000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x93000 0x1000>; + interrupts = <36 0>; + status = "disabled"; + + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm1_lpuart1: lpuart@93000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x93000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM1_CLK>; + status = "disabled"; + }; + flexcomm1_lpspi1: lpspi@93000 { + compatible = "nxp,imx-lpspi"; + reg = <0x93000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM1_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm1_lpi2c1: lpi2c@93800 { + compatible = "nxp,imx-lpi2c"; + reg = <0x93800 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM1_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm2: flexcomm@94000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x94000 0x1000>; + interrupts = <37 0>; + status = "disabled"; + + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm2_lpuart2: lpuart@94000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x94000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM2_CLK>; + status = "disabled"; + }; + flexcomm2_lpspi2: lpspi@94000 { + compatible = "nxp,imx-lpspi"; + reg = <0x94000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM2_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm2_lpi2c2: lpi2c@94800 { + compatible = "nxp,imx-lpi2c"; + reg = <0x94800 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM2_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm3: flexcomm@95000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x95000 0x1000>; + interrupts = <38 0>; + status = "disabled"; + + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm3_lpuart3: lpuart@95000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x95000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM3_CLK>; + status = "disabled"; + }; + flexcomm3_lpspi3: lpspi@95000 { + compatible = "nxp,imx-lpspi"; + reg = <0x95000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM3_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm3_lpi2c3: lpi2c@95800 { + compatible = "nxp,imx-lpi2c"; + reg = <0x95800 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM3_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm4: flexcomm@b4000 { + compatible = "nxp,lp-flexcomm"; + reg = <0xb4000 0x1000>; + interrupts = <39 0>; + status = "disabled"; + + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm4_lpuart4: lpuart@b4000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0xb4000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM4_CLK>; + status = "disabled"; + }; + flexcomm4_lpspi4: lpspi@b4000 { + compatible = "nxp,imx-lpspi"; + reg = <0xb4000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM4_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm4_lpi2c4: lpi2c@b4800 { + compatible = "nxp,imx-lpi2c"; + reg = <0xb4800 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM4_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm5: flexcomm@b5000 { + compatible = "nxp,lp-flexcomm"; + reg = <0xb5000 0x1000>; + interrupts = <40 0>; + status = "disabled"; + + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm5_lpuart5: lpuart@b5000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0xb5000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM5_CLK>; + status = "disabled"; + }; + flexcomm5_lpspi5: lpspi@b5000 { + compatible = "nxp,imx-lpspi"; + reg = <0xb5000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM5_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm5_lpi2c5: lpi2c@b5800 { + compatible = "nxp,imx-lpi2c"; + reg = <0xb5800 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM5_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm6: flexcomm@b6000 { + compatible = "nxp,lp-flexcomm"; + reg = <0xb6000 0x1000>; + interrupts = <41 0>; + status = "disabled"; + + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm6_lpuart6: lpuart@b6000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0xb6000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM6_CLK>; + status = "disabled"; + }; + flexcomm6_lpspi6: lpspi@b6000 { + compatible = "nxp,imx-lpspi"; + reg = <0xb6000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM6_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm6_lpi2c6: lpi2c@b6800 { + compatible = "nxp,imx-lpi2c"; + reg = <0xb6800 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM6_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm7: flexcomm@b7000 { + compatible = "nxp,lp-flexcomm"; + reg = <0xb7000 0x1000>; + interrupts = <42 0>; + status = "disabled"; + + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm7_lpuart7: lpuart@b7000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0xb7000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM7_CLK>; + status = "disabled"; + }; + flexcomm7_lpspi7: lpspi@b7000 { + compatible = "nxp,imx-lpspi"; + reg = <0xb7000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM7_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm7_lpi2c7: lpi2c@b7800 { + compatible = "nxp,imx-lpi2c"; + reg = <0xb7800 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM7_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm8: flexcomm@b8000 { + compatible = "nxp,lp-flexcomm"; + reg = <0xb8000 0x1000>; + interrupts = <43 0>; + status = "disabled"; + + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm8_lpuart8: lpuart@b8000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0xb8000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM8_CLK>; + status = "disabled"; + }; + flexcomm8_lpspi8: lpspi@b8000 { + compatible = "nxp,imx-lpspi"; + reg = <0xb8000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM8_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm8_lpi2c8: lpi2c@b8800 { + compatible = "nxp,imx-lpi2c"; + reg = <0xb8800 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM8_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm9: flexcomm@b9000 { + compatible = "nxp,lp-flexcomm"; + reg = <0xb9000 0x1000>; + interrupts = <44 0>; + status = "disabled"; + + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm9_lpuart9: lpuart@b9000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0xb9000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM9_CLK>; + status = "disabled"; + }; + flexcomm9_lpspi9: lpspi@b9000 { + compatible = "nxp,imx-lpspi"; + reg = <0xb9000 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM9_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm9_lpi2c9: lpi2c@b9800 { + compatible = "nxp,imx-lpi2c"; + reg = <0xb9800 0x1000>; + clocks = <&syscon MCUX_FLEXCOMM9_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + fmu: flash-controller@43000 { + compatible = "nxp,iap-mcx"; + reg = <0x43000 0x1000>; + interrupts = <138 0>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + flash: flash@0 { + compatible = "soc-nv-flash"; + reg = <0 DT_SIZE_M(2)>; + erase-block-size = <8192>; + write-block-size = <16>; + }; + }; + + os_timer: timers@49000 { + compatible = "nxp,os-timer"; + reg = <0x49000 0x1000>; + interrupts = <57 0>; + status = "disabled"; + }; +}; + +&systick { + /* + * MCXN94X relies by default on the OS Timer for system clock + * implementation, so the SysTick node is not to be enabled. + */ + status = "disabled"; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/nxp/nxp_mcxn94x_ns.dtsi b/dts/arm/nxp/nxp_mcxn94x_ns.dtsi new file mode 100644 index 00000000000..e92def96214 --- /dev/null +++ b/dts/arm/nxp/nxp_mcxn94x_ns.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + soc { + sram: sram@4000000 { + ranges = <0x4000000 0x4000000 0x20000000>; + }; + + peripheral: peripheral@40000000 { + ranges = <0x0 0x40000000 0x10000000>; + }; + + flexspi: spi@400c8000 { + reg = <0x400c8000 0x1000>, <0x80000000 DT_SIZE_M(8)>; + }; + }; +}; + +#include "nxp_mcxn94x_common.dtsi" From f93e37e84b29464d4dfbfa0ad1860f26f557b97c Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 5 Mar 2024 16:45:15 -0600 Subject: [PATCH 0629/2402] soc: mcxn947: Add support for NXP MCXN947 Add initial support for NXP MCXN947 SoC Signed-off-by: Emilio Benavente Signed-off-by: Mahesh Mahadevan --- MAINTAINERS.yml | 1 + modules/Kconfig.mcux | 5 ++- soc/nxp/mcx/CMakeLists.txt | 7 ++++ soc/nxp/mcx/Kconfig | 13 ++++++++ soc/nxp/mcx/Kconfig.defconfig | 12 +++++++ soc/nxp/mcx/Kconfig.soc | 10 ++++++ soc/nxp/mcx/mcxnx4x/CMakeLists.txt | 17 ++++++++++ soc/nxp/mcx/mcxnx4x/Kconfig | 38 ++++++++++++++++++++++ soc/nxp/mcx/mcxnx4x/Kconfig.defconfig | 46 +++++++++++++++++++++++++++ soc/nxp/mcx/mcxnx4x/Kconfig.soc | 34 ++++++++++++++++++++ soc/nxp/mcx/mcxnx4x/pinctrl_soc.h | 46 +++++++++++++++++++++++++++ soc/nxp/mcx/mcxnx4x/soc.c | 40 +++++++++++++++++++++++ soc/nxp/mcx/mcxnx4x/soc.h | 27 ++++++++++++++++ soc/nxp/mcx/soc.yml | 9 ++++++ 14 files changed, 304 insertions(+), 1 deletion(-) create mode 100644 soc/nxp/mcx/CMakeLists.txt create mode 100644 soc/nxp/mcx/Kconfig create mode 100644 soc/nxp/mcx/Kconfig.defconfig create mode 100644 soc/nxp/mcx/Kconfig.soc create mode 100644 soc/nxp/mcx/mcxnx4x/CMakeLists.txt create mode 100644 soc/nxp/mcx/mcxnx4x/Kconfig create mode 100644 soc/nxp/mcx/mcxnx4x/Kconfig.defconfig create mode 100644 soc/nxp/mcx/mcxnx4x/Kconfig.soc create mode 100644 soc/nxp/mcx/mcxnx4x/pinctrl_soc.h create mode 100644 soc/nxp/mcx/mcxnx4x/soc.c create mode 100644 soc/nxp/mcx/mcxnx4x/soc.h create mode 100644 soc/nxp/mcx/soc.yml diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 7e7548928b0..b61853be4ee 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3334,6 +3334,7 @@ NXP Platforms (MCU): - soc/nxp/kinetis/ - soc/nxp/lpc/ - soc/nxp/rw/ + - soc/nxp/mcx/ - dts/arm/nxp/ - samples/boards/nxp*/ files-regex-exclude: diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux index c1760ffd649..3f20250f58b 100644 --- a/modules/Kconfig.mcux +++ b/modules/Kconfig.mcux @@ -1,12 +1,15 @@ # MCUXpresso SDK # Copyright (c) 2016, Freescale Semiconductor, Inc. +# Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 config HAS_MCUX bool depends on SOC_FAMILY_KINETIS || SOC_FAMILY_NXP_IMX || SOC_FAMILY_LPC || \ - SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT || SOC_FAMILY_NXP_RW + SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT || SOC_FAMILY_NXP_RW || \ + SOC_FAMILY_NXP_MCX + if HAS_MCUX config MCUX_CORE_SUFFIX diff --git a/soc/nxp/mcx/CMakeLists.txt b/soc/nxp/mcx/CMakeLists.txt new file mode 100644 index 00000000000..025698dfbc3 --- /dev/null +++ b/soc/nxp/mcx/CMakeLists.txt @@ -0,0 +1,7 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/nxp/mcx/Kconfig b/soc/nxp/mcx/Kconfig new file mode 100644 index 00000000000..b8ac7a08f17 --- /dev/null +++ b/soc/nxp/mcx/Kconfig @@ -0,0 +1,13 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_MCX + select HAS_SEGGER_RTT + select CLOCK_CONTROL + select ARM + +if SOC_FAMILY_NXP_MCX + +rsource "*/Kconfig" + +endif # SOC_FAMILY_NXP_MCX diff --git a/soc/nxp/mcx/Kconfig.defconfig b/soc/nxp/mcx/Kconfig.defconfig new file mode 100644 index 00000000000..9e41c34f199 --- /dev/null +++ b/soc/nxp/mcx/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NXP_MCX + +config SERIAL_INIT_PRIORITY + default 55 + depends on SERIAL + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_NXP_MCX diff --git a/soc/nxp/mcx/Kconfig.soc b/soc/nxp/mcx/Kconfig.soc new file mode 100644 index 00000000000..d69ee818fab --- /dev/null +++ b/soc/nxp/mcx/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_MCX + bool + +config SOC_FAMILY + default "nxp_mcx" if SOC_FAMILY_NXP_MCX + +rsource "*/Kconfig.soc" diff --git a/soc/nxp/mcx/mcxnx4x/CMakeLists.txt b/soc/nxp/mcx/mcxnx4x/CMakeLists.txt new file mode 100644 index 00000000000..0a382670bc2 --- /dev/null +++ b/soc/nxp/mcx/mcxnx4x/CMakeLists.txt @@ -0,0 +1,17 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +# Pass this flag so the SDK I2C, UART and SPI drivers do not init the LP +# Flexcomm SDK driver +zephyr_compile_definitions_ifdef(CONFIG_NXP_LP_FLEXCOMM LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER=1) + +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/mcx/mcxnx4x/Kconfig b/soc/nxp/mcx/mcxnx4x/Kconfig new file mode 100644 index 00000000000..c36f8b0b001 --- /dev/null +++ b/soc/nxp/mcx/mcxnx4x/Kconfig @@ -0,0 +1,38 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MCXNX4X + select HAS_MCUX + select HAS_MCUX_FLEXCOMM + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_DWT + select PLATFORM_SPECIFIC_INIT + +config SOC_MCXN947_CPU0 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select HAS_MCUX_CACHE + +if SOC_SERIES_MCXNX4X + +config SECOND_CORE_MCUX + bool "MCXN94X's second core" + depends on HAS_MCUX + help + Indicates the second core will be enabled, and the part will run + in dual core mode. + +config FLASH_DISABLE_CACHE64 + bool "Disable the CACHE64 cache for FlexSPI flash accesses" + help + Disable cache64 cache. + +config MCUX_CORE_SUFFIX + default "_cm33_core0" if SOC_MCXN947_CPU0 + default "_cm33_core1" if SOC_MCXN947_CPU1 + +endif # SOC_SERIES_MCXNX4X diff --git a/soc/nxp/mcx/mcxnx4x/Kconfig.defconfig b/soc/nxp/mcx/mcxnx4x/Kconfig.defconfig new file mode 100644 index 00000000000..0c64fdaa649 --- /dev/null +++ b/soc/nxp/mcx/mcxnx4x/Kconfig.defconfig @@ -0,0 +1,46 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MCXNX4X + +config NUM_IRQS + default 155 + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +config ZTEST_NO_YIELD + default y if (PM && ZTEST) + +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi + +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) +DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(DT_FLASH_PARENT_IS_FLEXSPI) + +config FLASH_SIZE + default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ + if $(DT_FLASH_HAS_SIZE_PROP) + +if MCUX_OS_TIMER + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +endif # MCUX_OS_TIMER + +if CORTEX_M_SYSTICK + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 150000000 + +endif # CORTEX_M_SYSTICK + +endif # SOC_SERIES_MCXNX4X diff --git a/soc/nxp/mcx/mcxnx4x/Kconfig.soc b/soc/nxp/mcx/mcxnx4x/Kconfig.soc new file mode 100644 index 00000000000..460d3632a27 --- /dev/null +++ b/soc/nxp/mcx/mcxnx4x/Kconfig.soc @@ -0,0 +1,34 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MCXNX4X + bool + select SOC_FAMILY_NXP_MCX + +config SOC_SERIES + default "mcxnx4x" if SOC_SERIES_MCXNX4X + +config SOC_MCXN947 + bool + select SOC_SERIES_MCXNX4X + +config SOC_MCXN947_CPU0 + bool + select SOC_MCXN947 + +config SOC_MCXN947_CPU1 + bool + select SOC_MCXN947 + +config SOC + default "mcxn947" if SOC_MCXN947 + +config SOC_PART_NUMBER_MCXN947VDF + bool + +config SOC_PART_NUMBER_MCXN947VNL + bool + +config SOC_PART_NUMBER + default "MCXN947VDF" if SOC_PART_NUMBER_MCXN947VDF + default "MCXN947VNL" if SOC_PART_NUMBER_MCXN947VNL diff --git a/soc/nxp/mcx/mcxnx4x/pinctrl_soc.h b/soc/nxp/mcx/mcxnx4x/pinctrl_soc.h new file mode 100644 index 00000000000..4869fb58180 --- /dev/null +++ b/soc/nxp/mcx/mcxnx4x/pinctrl_soc.h @@ -0,0 +1,46 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_NXP_MCX_COMMON_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_NXP_MCX_COMMON_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef uint32_t pinctrl_soc_pin_t; + +#define Z_PINCTRL_MCX_PINCFG(node_id) \ + (PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \ + PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \ + PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \ + PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \ + PORT_PCR_ODE(DT_PROP(node_id, drive_open_drain)) | \ + PORT_PCR_SRE(DT_ENUM_IDX(node_id, slew_rate)) | \ + PORT_PCR_IBE(DT_PROP(node_id, input_enable)) | \ + PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter))) + +#define Z_PINCTRL_KINETIS_PCR_MASK \ + (PORT_PCR_IBE_MASK | PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | \ + PORT_PCR_ODE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_SRE_MASK | \ + PORT_PCR_PE_MASK | PORT_PCR_PS_MASK) + + +#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ + DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_MCX_PINCFG(group), + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ + DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_NXP_MCX_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/nxp/mcx/mcxnx4x/soc.c b/soc/nxp/mcx/mcxnx4x/soc.c new file mode 100644 index 00000000000..784721b2850 --- /dev/null +++ b/soc/nxp/mcx/mcxnx4x/soc.c @@ -0,0 +1,40 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for nxp_mcxn94x platform + * + * This module provides routines to initialize and support board-level + * hardware for the nxp_mcxn94x platform. + */ + +#include +#include +#include +#include + +#ifdef CONFIG_PLATFORM_SPECIFIC_INIT + +void z_arm_platform_init(void) +{ + SystemInit(); +} + +#endif + +#define FLEXCOMM_CHECK_2(n) \ + BUILD_ASSERT((DT_NODE_HAS_COMPAT(n, nxp_kinetis_lpuart) == 0) && \ + (DT_NODE_HAS_COMPAT(n, nxp_imx_lpi2c) == 0), \ + "Do not enable SPI and UART/I2C on the same Flexcomm node"); + +/* For SPI node enabled, check if UART or I2C is also enabled on the same parent Flexcomm node */ +#define FLEXCOMM_CHECK(n) DT_FOREACH_CHILD_STATUS_OKAY(DT_PARENT(n), FLEXCOMM_CHECK_2) + +/* SPI cannot be exist with UART or I2C on the same FlexComm Interface + * Throw a build error if user is enabling SPI and UART/I2C on a Flexcomm node. + */ +DT_FOREACH_STATUS_OKAY(nxp_imx_lpspi, FLEXCOMM_CHECK) diff --git a/soc/nxp/mcx/mcxnx4x/soc.h b/soc/nxp/mcx/mcxnx4x/soc.h new file mode 100644 index 00000000000..185b400f772 --- /dev/null +++ b/soc/nxp/mcx/mcxnx4x/soc.h @@ -0,0 +1,27 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#ifndef _ASMLANGUAGE + +#include +#include + +#define PORT_MUX_GPIO kPORT_MuxAlt0 /* GPIO setting for the Port Mux Register */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/soc/nxp/mcx/soc.yml b/soc/nxp/mcx/soc.yml new file mode 100644 index 00000000000..8181b0069b6 --- /dev/null +++ b/soc/nxp/mcx/soc.yml @@ -0,0 +1,9 @@ +family: +- name: nxp_mcx + series: + - name: mcxnx4x + socs: + - name: mcxn947 + cpuclusters: + - name: cpu0 + - name: cpu1 From eaea4ec43e904b6180b61a78edd39daee26e4664 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Wed, 6 Mar 2024 00:15:06 -0600 Subject: [PATCH 0630/2402] boards: frdm_mcxn947: Add support for frdm_mcxn947 board Add support for frdm_mcxn947 board Signed-off-by: Emilio Benavente ` Signed-off-by: Mahesh Mahadevan --- boards/nxp/frdm_mcxn947/CMakeLists.txt | 8 ++ boards/nxp/frdm_mcxn947/Kconfig | 8 ++ boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 | 7 + boards/nxp/frdm_mcxn947/board.c | 131 ++++++++++++++++++ boards/nxp/frdm_mcxn947/board.cmake | 18 +++ boards/nxp/frdm_mcxn947/board.yml | 5 + .../frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi | 19 +++ boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 49 +++++++ .../frdm_mcxn947_mcxn947_cpu0.dts | 86 ++++++++++++ .../frdm_mcxn947_mcxn947_cpu0.yaml | 20 +++ .../frdm_mcxn947_mcxn947_cpu0_defconfig | 18 +++ 11 files changed, 369 insertions(+) create mode 100644 boards/nxp/frdm_mcxn947/CMakeLists.txt create mode 100644 boards/nxp/frdm_mcxn947/Kconfig create mode 100644 boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 create mode 100644 boards/nxp/frdm_mcxn947/board.c create mode 100644 boards/nxp/frdm_mcxn947/board.cmake create mode 100644 boards/nxp/frdm_mcxn947/board.yml create mode 100644 boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi create mode 100644 boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi create mode 100644 boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts create mode 100644 boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml create mode 100644 boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig diff --git a/boards/nxp/frdm_mcxn947/CMakeLists.txt b/boards/nxp/frdm_mcxn947/CMakeLists.txt new file mode 100644 index 00000000000..df4c3939ca7 --- /dev/null +++ b/boards/nxp/frdm_mcxn947/CMakeLists.txt @@ -0,0 +1,8 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/nxp/frdm_mcxn947/Kconfig b/boards/nxp/frdm_mcxn947/Kconfig new file mode 100644 index 00000000000..23271bc179f --- /dev/null +++ b/boards/nxp/frdm_mcxn947/Kconfig @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INIT_PRIORITY + int "Board initialization priority" + default 1 + help + Board initialization priority. diff --git a/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 b/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 new file mode 100644 index 00000000000..944d25af1b1 --- /dev/null +++ b/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 @@ -0,0 +1,7 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXN947 + select SOC_MCXN947_CPU0 if BOARD_FRDM_MCXN947_MCXN947_CPU0 + select SOC_MCXN947_CPU1 if BOARD_FRDM_MCXN947_MCXN947_CPU1 + select SOC_PART_NUMBER_MCXN947VDF diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c new file mode 100644 index 00000000000..89b57008207 --- /dev/null +++ b/boards/nxp/frdm_mcxn947/board.c @@ -0,0 +1,131 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include + +/* Board xtal frequency in Hz */ +#define BOARD_XTAL0_CLK_HZ 24000000U +/* Core clock frequency: 150MHz */ +#define CLOCK_INIT_CORE_CLOCK 150000000U +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +__ramfunc static void enable_lpcac(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK; + SYSCON->LPCAC_CTRL &= ~(SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK | + SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK); +} + +/* Update Active mode voltage for OverDrive mode. */ +void power_mode_od(void) +{ + /* Set the DCDC VDD regulator to 1.2 V voltage level */ + spc_active_mode_dcdc_option_t opt = { + .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, + .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength, + }; + SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt); + + /* Set the LDO_CORE VDD regulator to 1.2 V voltage level */ + spc_active_mode_core_ldo_option_t ldo_opt = { + .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, + .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength, + }; + SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt); + + /* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */ + spc_sram_voltage_config_t cfg = { + .operateVoltage = kSPC_sramOperateAt1P2V, + .requestVoltageUpdate = true, + }; + SPC_SetSRAMOperateVoltage(SPC0, &cfg); +} + +static int frdm_mcxn947_init(void) +{ + /* Do not re-run this clock init code if using MCUBoot */ +#ifndef CONFIG_BOOTLOADER_MCUBOOT + enable_lpcac(); + + power_mode_od(); + + /* Enable SCG clock */ + CLOCK_EnableClock(kCLOCK_Scg); + + /* FRO OSC setup - begin, enable the FRO for safety switching */ + + /* Switch to FRO 12M first to ensure we can change the clock setting */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); + + /* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U)); + + /* Enable FRO HF(48MHz) output */ + CLOCK_SetupFROHFClocking(48000000U); + + /* Set up PLL0 */ + const pll_setup_t pll0Setup = { + .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | + SCG_APLLCTRL_SELP(13U), + .pllndiv = SCG_APLLNDIV_NDIV(8U), + .pllpdiv = SCG_APLLPDIV_PDIV(1U), + .pllmdiv = SCG_APLLMDIV_MDIV(50U), + .pllRate = 150000000U + }; + /* Configure PLL0 to the desired values */ + CLOCK_SetPLL0Freq(&pll0Setup); + /* PLL0 Monitor is disabled */ + CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); + + /* Switch MAIN_CLK to PLL0 */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); + + /* Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay) + CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u); + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer), okay) + CLOCK_AttachClk(kCLK_1M_to_OSTIMER); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay) + CLOCK_EnableClock(kCLOCK_Gpio0); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay) + CLOCK_EnableClock(kCLOCK_Gpio1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay) + CLOCK_EnableClock(kCLOCK_Gpio2); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay) + CLOCK_EnableClock(kCLOCK_Gpio3); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay) + CLOCK_EnableClock(kCLOCK_Gpio4); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay) + CLOCK_EnableClock(kCLOCK_Gpio5); +#endif + + /* Set SystemCoreClock variable. */ + SystemCoreClock = CLOCK_INIT_CORE_CLOCK; + + return 0; +} + +SYS_INIT(frdm_mcxn947_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY); diff --git a/boards/nxp/frdm_mcxn947/board.cmake b/boards/nxp/frdm_mcxn947/board.cmake new file mode 100644 index 00000000000..1eea0002274 --- /dev/null +++ b/boards/nxp/frdm_mcxn947/board.cmake @@ -0,0 +1,18 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MCXN947_CPU0) + board_runner_args(jlink "--device=MCXN947_M33_0" "--reset-after-load") + board_runner_args(linkserver "--device=MCXN947:MCX-N9XX-EVK:cm33_core0") + board_runner_args(linkserver "--override=/device/memory/1/flash-driver=MCXN9xx_S.cfx") + board_runner_args(linkserver "--override=/device/memory/1/location=0x10000000") +else() + message(FATAL_ERROR "Support for cpu1 not available yet") +endif() + + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/frdm_mcxn947/board.yml b/boards/nxp/frdm_mcxn947/board.yml new file mode 100644 index 00000000000..b74b1880cb9 --- /dev/null +++ b/boards/nxp/frdm_mcxn947/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_mcxn947 + vendor: nxp + socs: + - name: mcxn947 diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi new file mode 100644 index 00000000000..f9d6e6d36ae --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi new file mode 100644 index 00000000000..5b8f52568de --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -0,0 +1,49 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "frdm_mcxn947-pinctrl.dtsi" + +/ { + aliases{ + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + label = "Green LED"; + status = "disabled"; + }; + blue_led: led_2 { + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + status = "disabled"; + }; + red_led: led_3 { + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + label = "Red LED"; + status = "disabled"; + }; + }; +}; + +&flexcomm4_lpuart4 { + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm4_lpuart>; + pinctrl-names = "default"; +}; + +/* + * MCXN947 board uses OS timer as the kernel timer + * In case we need to switch to SYSTICK timer, then + * replace &os_timer with &systick + */ +&os_timer { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts new file mode 100644 index 00000000000..ebbf77d32fe --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_mcxn947.dtsi" + +/ { + model = "NXP FRDM_N94 board"; + compatible = "nxp,mcxn947", "nxp,mcx"; + + cpus { + /delete-node/ cpu@1; + }; + + aliases{ + sw0 = &user_button_3; + sw1 = &user_button_2; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash; + zephyr,flash-controller = &fmu; + zephyr,console = &flexcomm4_lpuart4; + zephyr,shell-uart = &flexcomm4_lpuart4; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_2: button_0 { + label = "User SW2"; + gpios = <&gpio0 29 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + user_button_3: button_1 { + label = "User SW3"; + gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +/* + * Default for this board is to allocate SRAM0-5 to cpu0 but the + * application can have an application specific device tree to + * allocate the SRAM0-7 differently. + * + * For example, SRAM0-6 could be allocated to cpu0 with only SRAM7 + * for cpu1. This would require the value of sram0 to have a DT_SIZE_K + * of 384. You would have to make updates to cpu1 sram settings as well. + */ +&sram0 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(320)>; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&green_led { + status = "okay"; +}; + +&red_led { + status = "okay"; +}; + +&flexcomm4 { + status = "okay"; +}; + +&flexcomm4_lpuart4 { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml new file mode 100644 index 00000000000..fb213bb25a6 --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -0,0 +1,20 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_mcxn947/mcxn947/cpu0 +name: NXP FRDM MCXN947 (CPU0) +type: mcu +arch: arm +ram: 320 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_serial + - gpio +vendor: nxp diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig new file mode 100644 index 00000000000..41ce4376bdc --- /dev/null +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig @@ -0,0 +1,18 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y From 8fa1c6d9c6cbc7972f482b17584c48b4ea952e55 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Wed, 6 Mar 2024 21:33:26 -0600 Subject: [PATCH 0631/2402] west.yml: Get changes for MCXN947 support Get HAL updates for MCXN947 support Signed-off-by: Mahesh Mahadevan --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 1eb17cbc69d..093a45b7ea0 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 259bc153dd5b9dbc5cbe63d2d644a61ee83b7496 + revision: 3c4f74b405ca174fe3eb5f3b74c355376ee9a69f path: modules/hal/nxp groups: - hal From 870806cbc0b04a18ae8b03315eff626a7d61f35a Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 8 Mar 2024 02:48:41 +0000 Subject: [PATCH 0632/2402] doc: frdm_mcxn947: Add documentation for FRDM-MCXN947 Add documentation for FRDM-MCXN947 Signed-off-by: Mahesh Mahadevan --- boards/nxp/frdm_mcxn947/doc/frdm_mcxn947.webp | Bin 0 -> 41800 bytes boards/nxp/frdm_mcxn947/doc/index.rst | 202 ++++++++++++++++++ 2 files changed, 202 insertions(+) create mode 100644 boards/nxp/frdm_mcxn947/doc/frdm_mcxn947.webp create mode 100644 boards/nxp/frdm_mcxn947/doc/index.rst diff --git a/boards/nxp/frdm_mcxn947/doc/frdm_mcxn947.webp b/boards/nxp/frdm_mcxn947/doc/frdm_mcxn947.webp new file mode 100644 index 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z8GRXUpY8DX)ksJ%b6@H=%iAGWU%OP%pW1+VFMoUDrpe2c3Dj6bVBA|2 zPP^0u2h_G4HDD!Vl?Er#Xk!D=BgeTnptZU;u%iw@3!s=;<^gr|L5hx80c3EW4t3%P z-_8sRAvC<9K#UfQ+wyah|5yEbL=pMHzgjPIgK{S|KzF zuR2lh-M88A`H2g!_H=j|qnuMXD=7ZLkvE&hZ9`#4T~Fy!F$FKcCa&*|!(wqSo-m`6 zaftJUacM%Tu#Ru$7^x&v$`g{Kjf|}e-eF4 ztQXk%f)z@T@Q4Hu?Q(5nhAUSQG(hQOPx*i*Iwd^1ll{TjTL4+V2ncPUQ)LvxkhwL0 zjs)`O3N!2@)$$qBV+*!EYX>Wi^B~ZgM+zI8iw0H)7IA7&Lu(Iwny?E>std@QBj=Tl z4?;pJJ?sK+xS?CCt$KOB$1=oK2M|WUJBPm-oe{Of=GB*Sul}al@0k}R1~}Zd!B!tM z;nxu>M4ykbTQ|6#fyGvS?4sVg^GwHY$eET}Gz#hRrbz(~5`7jGS({ZcM>a_NbJj>FpE(&@>nD zz~iC*&2@5GZnz4uLA79q$<0+W%D=(Z*ML Date: Wed, 13 Mar 2024 20:56:23 +0800 Subject: [PATCH 0633/2402] boards: lpcxpresso54114 : fix board.cmake config error board config missing CONFIG_ which will cause west build can not create correct debuger inform Signed-off-by: Hake Huang --- boards/nxp/lpcxpresso54114/board.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/nxp/lpcxpresso54114/board.cmake b/boards/nxp/lpcxpresso54114/board.cmake index 0a88f68d928..e9db2a143c4 100644 --- a/boards/nxp/lpcxpresso54114/board.cmake +++ b/boards/nxp/lpcxpresso54114/board.cmake @@ -4,9 +4,9 @@ # SPDX-License-Identifier: Apache-2.0 # -if(BOARD_LPCXPRESSO54114_LPC54114_M4 OR CONFIG_SECOND_CORE_MCUX) +if(CONFIG_BOARD_LPCXPRESSO54114_LPC54114_M4 OR CONFIG_SECOND_CORE_MCUX) board_runner_args(jlink "--device=LPC54114J256_M4" "--reset-after-load") -elseif(BOARD_LPCXPRESSO54114_LPC54114_M0) +elseif(CONFIG_BOARD_LPCXPRESSO54114_LPC54114_M0) board_runner_args(jlink "--device=LPC54114J256_M0" "--reset-after-load") endif() From 074a541fb02ba7b17fb9046aa35b4f5a714296a9 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Tue, 12 Mar 2024 16:38:18 +0100 Subject: [PATCH 0634/2402] tests: Bluetooth: add minimal coverage for `BT_RECV_WORKQ_SYS` Run the l2cap stress test so we have some minimal runtime coverage of that config. Signed-off-by: Jonathan Rico --- tests/bsim/bluetooth/host/l2cap/compile.sh | 1 + .../host/l2cap/stress/prj_syswq.conf | 57 +++++++++++++++++++ .../l2cap/stress/tests_scripts/l2cap_syswq.sh | 27 +++++++++ 3 files changed, 85 insertions(+) create mode 100644 tests/bsim/bluetooth/host/l2cap/stress/prj_syswq.conf create mode 100755 tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh diff --git a/tests/bsim/bluetooth/host/l2cap/compile.sh b/tests/bsim/bluetooth/host/l2cap/compile.sh index a4dd31c4b66..c86527f00e1 100755 --- a/tests/bsim/bluetooth/host/l2cap/compile.sh +++ b/tests/bsim/bluetooth/host/l2cap/compile.sh @@ -22,6 +22,7 @@ source ${ZEPHYR_BASE}/tests/bsim/compile.source app=tests/bsim/bluetooth/host/l2cap/general compile app=tests/bsim/bluetooth/host/l2cap/userdata compile app=tests/bsim/bluetooth/host/l2cap/stress compile +app=tests/bsim/bluetooth/host/l2cap/stress conf_file=prj_syswq.conf compile app=tests/bsim/bluetooth/host/l2cap/split/dut compile app=tests/bsim/bluetooth/host/l2cap/split/tester compile app=tests/bsim/bluetooth/host/l2cap/credits compile diff --git a/tests/bsim/bluetooth/host/l2cap/stress/prj_syswq.conf b/tests/bsim/bluetooth/host/l2cap/stress/prj_syswq.conf new file mode 100644 index 00000000000..040efd6df26 --- /dev/null +++ b/tests/bsim/bluetooth/host/l2cap/stress/prj_syswq.conf @@ -0,0 +1,57 @@ +CONFIG_BT=y +CONFIG_BT_CENTRAL=y +CONFIG_BT_PERIPHERAL=y +CONFIG_BT_DEVICE_NAME="L2CAP stress test" + +CONFIG_BT_EATT=n +CONFIG_BT_L2CAP_ECRED=n + +CONFIG_BT_SMP=y # Next config depends on it +CONFIG_BT_L2CAP_DYNAMIC_CHANNEL=y + +# Disable auto-initiated procedures so they don't +# mess with the test's execution. +CONFIG_BT_AUTO_PHY_UPDATE=n +CONFIG_BT_AUTO_DATA_LEN_UPDATE=n +CONFIG_BT_GAP_AUTO_UPDATE_CONN_PARAMS=n + +# L2CAP MPS +# 23+27+27=77 makes exactly three full packets +CONFIG_BT_L2CAP_TX_MTU=77 + +# Use this to send L2CAP PDUs without any fragmentation. +# In this particular case, we prefer fragmenting to test that code path. +# CONFIG_BT_BUF_ACL_TX_SIZE=81 + +# L2CAP PDUs will be fragmented in 3 ACL packets. +CONFIG_BT_BUF_ACL_TX_SIZE=27 + +CONFIG_BT_BUF_ACL_TX_COUNT=4 + +# The minimum value for this is +# L2AP MPS + L2CAP header (4) +CONFIG_BT_BUF_ACL_RX_SIZE=81 + +# Governs BT_CONN_TX_MAX, and so must be >= than the max number of +# peers, since we attempt to send one SDU per peer. The test execution +# is a bit slowed down by having this at the very minimum, but we want +# to keep it that way as to stress the stack as much as possible. +CONFIG_BT_L2CAP_TX_BUF_COUNT=6 + +CONFIG_BT_CTLR_DATA_LENGTH_MAX=27 +CONFIG_BT_CTLR_RX_BUFFERS=10 + +CONFIG_BT_MAX_CONN=10 + +CONFIG_LOG=y +CONFIG_ASSERT=y +CONFIG_NET_BUF_POOL_USAGE=y + +CONFIG_BT_L2CAP_LOG_LEVEL_DBG=y +# CONFIG_BT_CONN_LOG_LEVEL_DBG=y +CONFIG_LOG_THREAD_ID_PREFIX=y +CONFIG_THREAD_NAME=y + +CONFIG_ARCH_POSIX_TRAP_ON_FATAL=y + +CONFIG_BT_RECV_WORKQ_SYS=y diff --git a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh new file mode 100755 index 00000000000..40492162279 --- /dev/null +++ b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh @@ -0,0 +1,27 @@ +#!/usr/bin/env bash +# Copyright (c) 2022 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +# EATT test +simulation_id="l2cap_stress_syswq" +verbosity_level=2 +EXECUTE_TIMEOUT=120 + +cd ${BSIM_OUT_PATH}/bin + +bsim_exe=./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_stress_prj_syswq_conf + +Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=43 + +Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=42 +Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=2 -testid=peripheral -rs=10 +Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=3 -testid=peripheral -rs=23 +Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=4 -testid=peripheral -rs=7884 +Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=5 -testid=peripheral -rs=230 +Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=6 -testid=peripheral -rs=9 + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=7 -sim_length=400e6 $@ + +wait_for_background_jobs From 584f653de22282b9832743d7d9b1b0fd5228077b Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Tue, 12 Mar 2024 11:46:48 +0100 Subject: [PATCH 0635/2402] Bluetooth: conn: Don't deadlock on `BT_RECV_WORKQ_SYS` My recent change overlooked this configuration, which is not tested in CI currently. If someone had enabled it, they would've just gotten an unfixable assert. The correct test would be checking if the current thread is the system wq, but I think the compiler can't know that and can't remove the "dead" code. Signed-off-by: Jonathan Rico --- subsys/bluetooth/host/conn.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/subsys/bluetooth/host/conn.c b/subsys/bluetooth/host/conn.c index 4486a9b2838..25241b11815 100644 --- a/subsys/bluetooth/host/conn.c +++ b/subsys/bluetooth/host/conn.c @@ -212,6 +212,9 @@ static void tx_free(struct bt_conn_tx *tx) #if defined(CONFIG_BT_CONN_TX) static void tx_notify(struct bt_conn *conn) { + __ASSERT_NO_MSG(k_current_get() == + k_work_queue_thread_get(&k_sys_work_q)); + LOG_DBG("conn %p", conn); while (1) { @@ -377,15 +380,22 @@ static void bt_acl_recv(struct bt_conn *conn, struct net_buf *buf, static void wait_for_tx_work(struct bt_conn *conn) { #if defined(CONFIG_BT_CONN_TX) - struct k_work_sync sync; + LOG_DBG("conn %p", conn); - /* API docs mention undefined behavior if syncing on work item from wq - * execution context. - */ - __ASSERT_NO_MSG(k_current_get() != &k_sys_work_q.thread); + if (IS_ENABLED(CONFIG_BT_RECV_WORKQ_SYS)) { + tx_notify(conn); + } else { + struct k_work_sync sync; - k_work_submit(&conn->tx_complete_work); - k_work_flush(&conn->tx_complete_work, &sync); + /* API docs mention undefined behavior if syncing on work item + * from wq execution context. + */ + __ASSERT_NO_MSG(k_current_get() != + k_work_queue_thread_get(&k_sys_work_q)); + + k_work_submit(&conn->tx_complete_work); + k_work_flush(&conn->tx_complete_work, &sync); + } #else ARG_UNUSED(conn); #endif /* CONFIG_BT_CONN_TX */ @@ -1495,8 +1505,6 @@ static void tx_complete_work(struct k_work *work) struct bt_conn *conn = CONTAINER_OF(work, struct bt_conn, tx_complete_work); - LOG_DBG("conn %p", conn); - tx_notify(conn); } #endif /* CONFIG_BT_CONN_TX */ From ebbc96534c9657d3143527415d3c9e62e175027b Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Thu, 7 Mar 2024 11:00:09 +0800 Subject: [PATCH 0636/2402] ITE: drivers/i2c: Change GPIO output type to open-drain in recovery mode If I2C recovery mode uses GPIO push-pull to drive(3.3v), it will result leakage in a pull-up voltage of 1.8V on the power rail, leading to damage to 1.8V devices, including SoC, sensors. Therefore, the recovery mode should be changed to GPIO open-drain type to avoid this. Signed-off-by: Tim Lin --- drivers/i2c/i2c_ite_enhance.c | 4 ++-- drivers/i2c/i2c_ite_it8xxx2.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/i2c_ite_enhance.c b/drivers/i2c/i2c_ite_enhance.c index 9a84ea1582a..c36d3597936 100644 --- a/drivers/i2c/i2c_ite_enhance.c +++ b/drivers/i2c/i2c_ite_enhance.c @@ -1272,9 +1272,9 @@ static int i2c_enhance_recover_bus(const struct device *dev) int i, status; /* Set SCL of I2C as GPIO pin */ - gpio_pin_configure_dt(&config->scl_gpios, GPIO_OUTPUT); + gpio_pin_configure_dt(&config->scl_gpios, GPIO_OUTPUT | GPIO_OPEN_DRAIN); /* Set SDA of I2C as GPIO pin */ - gpio_pin_configure_dt(&config->sda_gpios, GPIO_OUTPUT); + gpio_pin_configure_dt(&config->sda_gpios, GPIO_OUTPUT | GPIO_OPEN_DRAIN); /* * In I2C recovery bus, 1ms sleep interval for bitbanging i2c diff --git a/drivers/i2c/i2c_ite_it8xxx2.c b/drivers/i2c/i2c_ite_it8xxx2.c index 734a38e5b25..4f130e3aaa2 100644 --- a/drivers/i2c/i2c_ite_it8xxx2.c +++ b/drivers/i2c/i2c_ite_it8xxx2.c @@ -1191,9 +1191,9 @@ static int i2c_it8xxx2_recover_bus(const struct device *dev) int i, status; /* Set SCL of I2C as GPIO pin */ - gpio_pin_configure_dt(&config->scl_gpios, GPIO_OUTPUT); + gpio_pin_configure_dt(&config->scl_gpios, GPIO_OUTPUT | GPIO_OPEN_DRAIN); /* Set SDA of I2C as GPIO pin */ - gpio_pin_configure_dt(&config->sda_gpios, GPIO_OUTPUT); + gpio_pin_configure_dt(&config->sda_gpios, GPIO_OUTPUT | GPIO_OPEN_DRAIN); /* * In I2C recovery bus, 1ms sleep interval for bitbanging i2c From 87f77ca35fa361647eb69631c508ef6a89adeafc Mon Sep 17 00:00:00 2001 From: Tom Chang Date: Wed, 6 Mar 2024 10:23:33 +0800 Subject: [PATCH 0637/2402] drivers: espi: npcx: fix warning when using ESPI_OOB_RX_ASYNC macro This CL prevents unused warnings when CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC is used. Signed-off-by: Tom Chang --- drivers/espi/espi_npcx.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/espi/espi_npcx.c b/drivers/espi/espi_npcx.c index 628de842690..f2005d24dba 100644 --- a/drivers/espi/espi_npcx.c +++ b/drivers/espi/espi_npcx.c @@ -917,10 +917,9 @@ static int espi_npcx_receive_oob(const struct device *dev, struct espi_oob_packet *pckt) { struct espi_reg *const inst = HAL_INSTANCE(dev); - struct espi_npcx_data *const data = dev->data; uint8_t *oob_buf = pckt->buf; uint32_t oob_data; - int idx_rx_buf, sz_oob_rx, ret; + int idx_rx_buf, sz_oob_rx; /* Check eSPI bus status first */ if (IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_BERR)) { @@ -929,6 +928,9 @@ static int espi_npcx_receive_oob(const struct device *dev, } #if !defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC) + struct espi_npcx_data *const data = dev->data; + int ret; + /* Wait until get oob package or timeout */ ret = k_sem_take(&data->oob_rx_lock, K_MSEC(ESPI_OOB_MAX_TIMEOUT)); if (ret == -EAGAIN) { From fcbf03a2dc18aca5e31fa0e00230a96f736b98f4 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Tue, 12 Mar 2024 10:19:10 -0500 Subject: [PATCH 0638/2402] soc: nxp: imxrt: correct FCB offset for iMXRT1011 SOC to 0x400 Unlike the remainder of the RT10xx series, the RT1011 SOC requires that the flash configuration block be placed at an offset of 0x400 bytes, instead of the start of the flash. Fixes #70090 Signed-off-by: Daniel DeGrasse --- soc/nxp/imxrt/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/nxp/imxrt/Kconfig b/soc/nxp/imxrt/Kconfig index cdcf6c4495d..b249dbb312b 100644 --- a/soc/nxp/imxrt/Kconfig +++ b/soc/nxp/imxrt/Kconfig @@ -88,7 +88,7 @@ endchoice # BOOT_DEVICE config FLEXSPI_CONFIG_BLOCK_OFFSET hex "FlexSPI config block offset" - default 0x400 if SOC_SERIES_IMXRT5XX || SOC_SERIES_IMXRT6XX + default 0x400 if SOC_SERIES_IMXRT5XX || SOC_SERIES_IMXRT6XX || SOC_MIMXRT1011 default 0x0 if BOOT_FLEXSPI_NOR help FlexSPI configuration block consists of parameters regarding specific From 7845c0e3d6409d19deba8873ecbae0db6ebb9407 Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Sat, 13 Jan 2024 07:00:30 +0100 Subject: [PATCH 0639/2402] Bluetooth: Controller: Ticker low latency with lazy skip Update the legacy low latency variant of the ticker implementation to skip to next periodic interval when ticks to expire is behind the current tick. This makes the low latency variant of the implementation consistent with the default ticker implementation. Also, cleanup conditional compiles in the implementation. Signed-off-by: Vinayak Kariappa Chettimada --- subsys/bluetooth/controller/ticker/ticker.c | 94 +++++++++++++-------- 1 file changed, 61 insertions(+), 33 deletions(-) diff --git a/subsys/bluetooth/controller/ticker/ticker.c b/subsys/bluetooth/controller/ticker/ticker.c index 83bd6437d59..639cd0ed57d 100644 --- a/subsys/bluetooth/controller/ticker/ticker.c +++ b/subsys/bluetooth/controller/ticker/ticker.c @@ -494,7 +494,11 @@ static void ticker_by_next_slot_get(struct ticker_instance *instance, break; } } else -#endif /* CONFIG_BT_TICKER_NEXT_SLOT_GET_MATCH */ +#else /* !CONFIG_BT_TICKER_NEXT_SLOT_GET_MATCH */ + ARG_UNUSED(fp_match_op_func); + ARG_UNUSED(match_op_context); +#endif /* !CONFIG_BT_TICKER_NEXT_SLOT_GET_MATCH */ + #if !defined(CONFIG_BT_TICKER_SLOT_AGNOSTIC) if (ticker->ticks_slot) { /* Matching not used and node has slot ticks */ @@ -519,13 +523,17 @@ static void ticker_by_next_slot_get(struct ticker_instance *instance, if (remainder) { *remainder = ticker->remainder_current; } -#endif /* CONFIG_BT_TICKER_REMAINDER_GET */ +#else /* !CONFIG_BT_TICKER_REMAINDER_GET */ + ARG_UNUSED(remainder); +#endif /* !CONFIG_BT_TICKER_REMAINDER_GET */ #if defined(CONFIG_BT_TICKER_LAZY_GET) if (lazy) { *lazy = ticker->lazy_current; } -#endif /* CONFIG_BT_TICKER_LAZY_GET */ +#else /* !CONFIG_BT_TICKER_LAZY_GET */ + ARG_UNUSED(lazy); +#endif /* !CONFIG_BT_TICKER_LAZY_GET */ } *ticker_id_head = _ticker_id_head; @@ -602,7 +610,7 @@ static uint8_t ticker_enqueue(struct ticker_instance *instance, uint8_t id) return id; } -#else /* !CONFIG_BT_TICKER_LOW_LAT */ +#else /* CONFIG_BT_TICKER_LOW_LAT */ /** * @brief Enqueue ticker node @@ -699,7 +707,7 @@ static uint8_t ticker_enqueue(struct ticker_instance *instance, uint8_t id) return id; } -#endif /* !CONFIG_BT_TICKER_LOW_LAT */ +#endif /* CONFIG_BT_TICKER_LOW_LAT */ /** * @brief Dequeue ticker node @@ -1727,7 +1735,9 @@ static inline uint32_t ticker_job_node_update(struct ticker_instance *instance, ticker_mark_expire_info_outdated(instance, user_op->id); } } -#endif /* CONFIG_BT_TICKER_EXT_EXPIRE_INFO */ +#else /* !CONFIG_BT_TICKER_EXT_EXPIRE_INFO */ + ARG_UNUSED(instance); +#endif /* !CONFIG_BT_TICKER_EXT_EXPIRE_INFO */ ticker->next = *insert_head; *insert_head = user_op->id; @@ -2003,12 +2013,9 @@ static inline void ticker_job_worker_bh(struct ticker_instance *instance, { struct ticker_node *node; uint32_t ticks_expired; - -#if !defined(CONFIG_BT_TICKER_LOW_LAT) uint32_t ticks_latency; ticks_latency = ticker_ticks_diff_get(ticks_now, ticks_previous); -#endif /* !CONFIG_BT_TICKER_LOW_LAT */ node = &instance->nodes[0]; ticks_expired = 0U; @@ -2032,13 +2039,12 @@ static inline void ticker_job_worker_bh(struct ticker_instance *instance, /* decrement ticks_elapsed and collect expired ticks */ ticks_elapsed -= ticks_to_expire; + ticks_latency -= ticks_to_expire; ticks_expired += ticks_to_expire; state = (ticker->req - ticker->ack) & 0xff; #if !defined(CONFIG_BT_TICKER_LOW_LAT) - ticks_latency -= ticks_to_expire; - /* Node with lazy count did not expire with callback, but * was either a collision or re-scheduled. This node should * not define the active slot reservation (slot_previous). @@ -2150,9 +2156,11 @@ static inline void ticker_job_worker_bh(struct ticker_instance *instance, } ticks_to_expire_prep(ticker, instance->ticks_current, - (ticks_previous + ticks_expired)); -#else /* !CONFIG_BT_TICKER_LOW_LAT */ + ((ticks_previous + ticks_expired) & + HAL_TICKER_CNTR_MASK)); +#else /* CONFIG_BT_TICKER_LOW_LAT */ uint32_t count; + uint16_t lazy; /* Prepare for next interval */ ticks_to_expire = 0U; @@ -2161,15 +2169,31 @@ static inline void ticker_job_worker_bh(struct ticker_instance *instance, ticks_to_expire += ticker->ticks_periodic; ticks_to_expire += ticker_remainder_inc(ticker); } + + /* Skip intervals that have elapsed w.r.t. current + * ticks. + */ + lazy = 0U; + + /* Schedule to a tick in the future */ + while (ticks_to_expire < ticks_latency) { + ticks_to_expire += ticker->ticks_periodic; + ticks_to_expire += ticker_remainder_inc(ticker); + lazy++; + } + + /* Use the calculated ticks to expire and laziness. */ ticker->ticks_to_expire = ticks_to_expire; + ticker->lazy_current = ticker->lazy_periodic + lazy; ticks_to_expire_prep(ticker, instance->ticks_current, - (ticks_previous + ticks_expired)); + ((ticks_previous + ticks_expired) & + HAL_TICKER_CNTR_MASK)); - /* Reset latency to periodic offset */ - ticker->lazy_current = ticker->lazy_periodic; + /* Reset force state of the node */ ticker->force = 0U; -#endif /* !CONFIG_BT_TICKER_LOW_LAT */ +#endif /* CONFIG_BT_TICKER_LOW_LAT */ + /* Add to insert list */ ticker->next = *insert_head; *insert_head = id_expired; @@ -2243,8 +2267,12 @@ static inline uint32_t ticker_job_op_start(struct ticker_instance *instance, } ticker_mark_expire_info_outdated(instance, user_op->id); -#endif /* CONFIG_BT_TICKER_EXT_EXPIRE_INFO */ -#endif /* CONFIG_BT_TICKER_EXT */ +#else /* !CONFIG_BT_TICKER_EXT_EXPIRE_INFO */ + ARG_UNUSED(instance); +#endif /* !CONFIG_BT_TICKER_EXT_EXPIRE_INFO */ +#else /* !CONFIG_BT_TICKER_EXT */ + ARG_UNUSED(instance); +#endif /* !CONFIG_BT_TICKER_EXT */ ticker->ticks_periodic = start->ticks_periodic; ticker->remainder_periodic = start->remainder_periodic; @@ -2574,7 +2602,7 @@ static uint8_t ticker_job_reschedule_in_window(struct ticker_instance *instance, return rescheduled; } #endif /* CONFIG_BT_TICKER_EXT && !CONFIG_BT_TICKER_SLOT_AGNOSTIC */ -#else /* !CONFIG_BT_TICKER_LOW_LAT */ +#else /* CONFIG_BT_TICKER_LOW_LAT */ /** * @brief Insert new ticker node @@ -2687,7 +2715,7 @@ static inline uint8_t ticker_job_insert(struct ticker_instance *instance, return TICKER_STATUS_SUCCESS; } -#endif /* !CONFIG_BT_TICKER_LOW_LAT */ +#endif /* CONFIG_BT_TICKER_LOW_LAT */ /** * @brief Insert and start ticker nodes for all users @@ -2988,10 +3016,8 @@ ticker_job_compare_update(struct ticker_instance *instance, ticks_to_expire = ticker->ticks_to_expire; /* If ticks_to_expire is zero, then immediately trigger the worker. - * Under BT_TICKER_LOW_LAT, mesh loopback test fails pending - * investigation hence immediate trigger not used for BT_TICKER_LOW_LAT. */ - if (!IS_ENABLED(CONFIG_BT_TICKER_LOW_LAT) && !ticks_to_expire) { + if (!ticks_to_expire) { return 1U; } @@ -3011,12 +3037,7 @@ ticker_job_compare_update(struct ticker_instance *instance, cc = instance->ticks_current; ticks_diff = ticker_ticks_diff_get(ctr_curr, cc); - /* Under BT_TICKER_LOW_LAT, bsim test fails, pending - * investigation immediate trigger not used for - * BT_TICKER_LOW_LAT. - */ - if (!IS_ENABLED(CONFIG_BT_TICKER_LOW_LAT) && - (ticks_diff >= ticks_to_expire)) { + if (ticks_diff >= ticks_to_expire) { return 1U; } @@ -3157,9 +3178,14 @@ void ticker_job(void *param) /* Handle inquiries */ ticker_job_list_inquire(instance); } -#endif /* CONFIG_BT_TICKER_JOB_IDLE_GET || - * CONFIG_BT_TICKER_NEXT_SLOT_GET || - * CONFIG_BT_TICKER_PRIORITY_SET +#else /* !CONFIG_BT_TICKER_JOB_IDLE_GET && + * !CONFIG_BT_TICKER_NEXT_SLOT_GET && + * !CONFIG_BT_TICKER_PRIORITY_SET + */ + ARG_UNUSED(pending); +#endif /* !CONFIG_BT_TICKER_JOB_IDLE_GET && + * !CONFIG_BT_TICKER_NEXT_SLOT_GET && + * !CONFIG_BT_TICKER_PRIORITY_SET */ #if defined(CONFIG_BT_TICKER_EXT_EXPIRE_INFO) @@ -3466,6 +3492,8 @@ uint8_t ticker_start_us(uint8_t instance_index, uint8_t user_id, user_op->params.start.ticks_first = ticks_first; #if defined(CONFIG_BT_TICKER_REMAINDER) user_op->params.start.remainder_first = remainder_first; +#else /* !CONFIG_BT_TICKER_REMAINDER */ + ARG_UNUSED(remainder_first); #endif /* !CONFIG_BT_TICKER_REMAINDER */ user_op->params.start.ticks_periodic = ticks_periodic; user_op->params.start.remainder_periodic = remainder_periodic; From 14191f11fde5ff5841d7fde1ac91ba5e68c4851c Mon Sep 17 00:00:00 2001 From: Morten Priess Date: Mon, 11 Mar 2024 14:09:32 +0100 Subject: [PATCH 0640/2402] Bluetooth: controller: Fix ISO Broadcast control subevent channel - Calculate broadcaster channel for control subevent - Calculate sync receiver channel for control subevent - Fix broadcast CSTF only set in first subevent - Remove ctrl_chan_use from LLL, as there is no longer a reason for storing it. Signed-off-by: Morten Priess --- subsys/bluetooth/controller/ll_sw/lll_adv.h | 1 - .../bluetooth/controller/ll_sw/lll_sync_iso.h | 1 - .../controller/ll_sw/nordic/lll/lll_adv_iso.c | 18 +++++++++++++----- .../controller/ll_sw/nordic/lll/lll_sync_iso.c | 11 +++++++++-- 4 files changed, 22 insertions(+), 9 deletions(-) diff --git a/subsys/bluetooth/controller/ll_sw/lll_adv.h b/subsys/bluetooth/controller/ll_sw/lll_adv.h index 21723dfeb2f..2b55bee7f0d 100644 --- a/subsys/bluetooth/controller/ll_sw/lll_adv.h +++ b/subsys/bluetooth/controller/ll_sw/lll_adv.h @@ -74,7 +74,6 @@ struct lll_adv_iso { uint8_t term_ack:1; uint8_t term_reason; - uint8_t ctrl_chan_use; uint8_t ctrl_expire; uint16_t ctrl_instant; diff --git a/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h b/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h index 830153b1433..c81d7d21e00 100644 --- a/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h +++ b/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h @@ -66,7 +66,6 @@ struct lll_sync_iso { uint8_t term_reason; - uint8_t ctrl_chan_use; uint16_t ctrl_instant; uint8_t stream_count; diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_iso.c index 60f8967738f..e89d5437f4b 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_iso.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_iso.c @@ -342,7 +342,6 @@ static int prepare_cb_common(struct lll_prepare_param *p) lll->cssn++; } - lll->ctrl_chan_use = data_chan_use; pdu->cstf = 1U; } else { pdu->cstf = 0U; @@ -463,11 +462,11 @@ static void isr_tx_common(void *param, radio_isr_cb_t isr_done) { struct pdu_bis *pdu = NULL; + uint8_t data_chan_use = 0; struct lll_adv_iso *lll; uint8_t access_addr[4]; uint64_t payload_count; uint16_t data_chan_id; - uint8_t data_chan_use; uint8_t crc_init[3]; uint8_t bis; @@ -528,7 +527,6 @@ static void isr_tx_common(void *param, /* control subevent to use bis = 0 and se_n = 1 */ bis = 0U; payload_count = lll->payload_count - lll->bn; - data_chan_use = lll->ctrl_chan_use; } else if (((lll->chm_req - lll->chm_ack) & CHM_STATE_MASK) == CHM_STATE_SEND) { @@ -552,7 +550,6 @@ static void isr_tx_common(void *param, /* control subevent to use bis = 0 and se_n = 1 */ bis = 0U; payload_count = lll->payload_count - lll->bn; - data_chan_use = lll->ctrl_chan_use; } else { struct lll_adv_iso_stream *stream; @@ -658,7 +655,7 @@ static void isr_tx_common(void *param, pdu = (void *)tx->pdu; } pdu->cssn = lll->cssn; - pdu->cstf = 0U; + pdu->cstf = (lll->term_req || !!(lll->chm_req - lll->chm_ack)); #else /* TEST_WITH_DUMMY_PDU */ pdu = radio_pkt_scratch_get(); @@ -687,6 +684,17 @@ static void isr_tx_common(void *param, } pdu->rfu = 0U; + if (!bis) { + const uint16_t event_counter = payload_count / lll->bn; + + /* Calculate the radio channel to use for ISO event */ + data_chan_use = lll_chan_iso_event(event_counter, data_chan_id, + lll->data_chan_map, + lll->data_chan_count, + &lll->data_chan_prn_s, + &lll->data_chan_remap_idx); + } + lll_chan_set(data_chan_use); /* Encryption */ diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c index e9111981d6f..13d101ed346 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c @@ -255,7 +255,6 @@ static int prepare_cb_common(struct lll_prepare_param *p) lll->data_chan_count, &lll->data_chan_prn_s, &lll->data_chan_remap_idx); - lll->ctrl_chan_use = data_chan_use; /* Initialize stream current */ lll->stream_curr = 0U; @@ -876,7 +875,15 @@ static void isr_rx(void *param) /* Set the channel to use */ if (!bis) { - data_chan_use = lll->ctrl_chan_use; + const uint16_t event_counter = + (lll->payload_count / lll->bn) - 1U; + + /* Calculate the radio channel to use for ISO event */ + data_chan_use = lll_chan_iso_event(event_counter, data_chan_id, + lll->data_chan_map, + lll->data_chan_count, + &lll->data_chan_prn_s, + &lll->data_chan_remap_idx); } else if (!skipped) { data_chan_use = lll->next_chan_use; } else { From 85b503e23b17aef4e4a6d172ec99eac17a1db25e Mon Sep 17 00:00:00 2001 From: Morten Priess Date: Thu, 5 Oct 2023 16:33:55 +0200 Subject: [PATCH 0641/2402] Bluetooth: controller: ISO Sync Receiver vendor data path fixes Add checks for vendor specific data path in ULL and HCI driver, to enable use of vendor data path for BIS reception. Signed-off-by: Morten Priess --- subsys/bluetooth/controller/hci/hci_driver.c | 3 +- subsys/bluetooth/controller/ll_sw/ull_iso.c | 41 +++++++++++++++----- 2 files changed, 33 insertions(+), 11 deletions(-) diff --git a/subsys/bluetooth/controller/hci/hci_driver.c b/subsys/bluetooth/controller/hci/hci_driver.c index fa3966c945f..7904836cdc7 100644 --- a/subsys/bluetooth/controller/hci/hci_driver.c +++ b/subsys/bluetooth/controller/hci/hci_driver.c @@ -458,7 +458,8 @@ static inline struct net_buf *encode_node(struct node_rx_pdu *node_rx, /* Check validity of the data path sink. FIXME: A channel disconnect race * may cause ISO data pending without valid data path. */ - if (stream && stream->dp) { + if (stream && stream->dp && + (stream->dp->path_id == BT_HCI_DATAPATH_ID_HCI)) { isoal_rx.meta = &node_rx->hdr.rx_iso_meta; isoal_rx.pdu = (void *)node_rx->pdu; err = isoal_rx_pdu_recombine(stream->dp->sink_hdl, &isoal_rx); diff --git a/subsys/bluetooth/controller/ll_sw/ull_iso.c b/subsys/bluetooth/controller/ll_sw/ull_iso.c index f1853b75d83..a60e66ba81b 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_iso.c +++ b/subsys/bluetooth/controller/ll_sw/ull_iso.c @@ -1569,14 +1569,14 @@ static void iso_rx_cig_ref_point_update(struct ll_conn_iso_group *cig, static void iso_rx_demux(void *param) { -#if defined(CONFIG_BT_CTLR_CONN_ISO) - struct ll_conn_iso_stream *cis; - struct ll_conn_iso_group *cig; +#if defined(CONFIG_BT_CTLR_CONN_ISO) || \ + defined(CONFIG_BT_CTLR_SYNC_ISO) struct ll_iso_datapath *dp; +#endif /* CONFIG_BT_CTLR_CONN_ISO || CONFIG_BT_CTLR_SYNC_ISO */ struct node_rx_pdu *rx_pdu; -#endif /* CONFIG_BT_CTLR_CONN_ISO */ struct node_rx_hdr *rx; memq_link_t *link; + uint16_t handle; do { link = memq_peek(memq_ull_iso_rx.head, memq_ull_iso_rx.tail, @@ -1596,14 +1596,35 @@ static void iso_rx_demux(void *param) (void)memq_dequeue(memq_ull_iso_rx.tail, &memq_ull_iso_rx.head, NULL); -#if defined(CONFIG_BT_CTLR_CONN_ISO) rx_pdu = (struct node_rx_pdu *)rx; - cis = ll_conn_iso_stream_get(rx_pdu->hdr.handle); - cig = cis->group; - dp = cis->hdr.datapath_out; + handle = rx_pdu->hdr.handle; + dp = NULL; - iso_rx_cig_ref_point_update(cig, cis, &rx_pdu->hdr.rx_iso_meta); + if (false) { +#if defined(CONFIG_BT_CTLR_CONN_ISO) + } else if (IS_CIS_HANDLE(handle)) { + struct ll_conn_iso_stream *cis; + struct ll_conn_iso_group *cig; + + cis = ll_conn_iso_stream_get(handle); + cig = cis->group; + dp = cis->hdr.datapath_out; + iso_rx_cig_ref_point_update(cig, cis, + &rx_pdu->hdr.rx_iso_meta); +#endif /* CONFIG_BT_CTLR_CONN_ISO */ +#if defined(CONFIG_BT_CTLR_SYNC_ISO) + } else if (IS_SYNC_ISO_HANDLE(handle)) { + struct lll_sync_iso_stream *sync_stream; + uint16_t stream_handle; + + stream_handle = LL_BIS_SYNC_IDX_FROM_HANDLE(handle); + sync_stream = ull_sync_iso_stream_get(stream_handle); + dp = sync_stream ? sync_stream->dp : NULL; +#endif /* CONFIG_BT_CTLR_SYNC_ISO */ + } + +#if defined(CONFIG_BT_CTLR_CONN_ISO) || defined(CONFIG_BT_CTLR_SYNC_ISO) if (dp && dp->path_id != BT_HCI_DATAPATH_ID_HCI) { /* If vendor specific datapath pass to ISO AL here, * in case of HCI destination it will be passed in @@ -1620,7 +1641,7 @@ static void iso_rx_demux(void *param) LL_ASSERT(err == ISOAL_STATUS_OK); /* TODO handle err */ } -#endif /* CONFIG_BT_CTLR_CONN_ISO */ +#endif /* CONFIG_BT_CTLR_CONN_ISO || CONFIG_BT_CTLR_SYNC_ISO */ /* Let ISO PDU start its long journey upwards */ ll_iso_rx_put(link, rx); From 5d99bf198f2131553ad2c3b2ffdba0824d3cbad5 Mon Sep 17 00:00:00 2001 From: Mateusz Michalek Date: Wed, 31 Jan 2024 17:00:20 +0100 Subject: [PATCH 0642/2402] dts: arm: nrf54l: Add nodes required by MCUboot The commit adds partitons on rram0. Signed-off-by: Mateusz Michalek --- .../nrf54l15pdk_nrf54l15_cpuapp.dts | 25 ++++++++++++++++--- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts index e8b13920a19..d26dc8d1c17 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -141,13 +141,30 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - slot0_partition: partition@0 { - label = "image-0"; + boot_partition: partition@0 { + label = "mcuboot"; reg = <0x0 DT_SIZE_K(64)>; }; - storage_partition: partition@f2000 { + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(348)>; + }; + slot0_ns_partition: partition@67000 { + label = "image-0-nonsecure"; + reg = <0x67000 DT_SIZE_K(348)>; + }; + slot1_partition: partition@be000 { + label = "image-1"; + reg = <0xbe000 DT_SIZE_K(348)>; + }; + slot1_ns_partition: partition@115000 { + label = "image-1-nonsecure"; + reg = <0x115000 DT_SIZE_K(348)>; + }; + /* 32k from 0x16c000 to 0x173fff reserved for TF-M partitions */ + storage_partition: partition@174000 { label = "storage"; - reg = <0xf2000 DT_SIZE_K(24)>; + reg = <0x174000 DT_SIZE_K(36)>; }; }; }; From 040a3423f763d4c7fa4ff47ded9f98c53b84cb6f Mon Sep 17 00:00:00 2001 From: Mateusz Michalek Date: Fri, 16 Feb 2024 12:57:30 +0100 Subject: [PATCH 0643/2402] dts: arm: add uart-mcumgr choosen for 54L15 setting uart20 as default uart-mcumgr Signed-off-by: Mateusz Michalek --- boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts index d26dc8d1c17..c801ddc8dc5 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -16,6 +16,7 @@ chosen { zephyr,console = &uart20; zephyr,shell-uart = &uart20; + zephyr,uart-mcumgr = &uart20; zephyr,sram = &sram0; zephyr,flash = &rram0; zephyr,code-partition = &slot0_partition; From e64fc33e058b70011ca7344764c0876fb4c8f2d6 Mon Sep 17 00:00:00 2001 From: Andrzej Puzdrowski Date: Tue, 13 Feb 2024 12:44:45 +0100 Subject: [PATCH 0644/2402] linker: Set ROM offset for MCUboot with NRF54L Due to number of IRQs the ROM offset, that contains MCUboot, needs to be moved to address that is aligned with 2048 byte long vector table. This comes from Cortex-M requirement where vector table needs to be placed at offset equal to lowest power of two number that will fit vector table. Signed-off-by: Dominik Ermel Signed-off-by: Mateusz Michalek Signed-off-by: Andrzej Puzdrowski --- boards/nordic/nrf54l15pdk/Kconfig.defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/boards/nordic/nrf54l15pdk/Kconfig.defconfig b/boards/nordic/nrf54l15pdk/Kconfig.defconfig index bd9c7231616..1c83abbb020 100644 --- a/boards/nordic/nrf54l15pdk/Kconfig.defconfig +++ b/boards/nordic/nrf54l15pdk/Kconfig.defconfig @@ -6,4 +6,7 @@ if BOARD_NRF54L15PDK_NRF54L15_CPUAPP config BT_CTLR default BT +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP From c5b2a16dd2dd84f410de9d4196a7ac5dccecd852 Mon Sep 17 00:00:00 2001 From: Fengming Ye Date: Mon, 11 Mar 2024 18:57:37 +0900 Subject: [PATCH 0645/2402] net: zperf: fix download ipv6 bind fail on specific ip address For command zperf udp download 5001 192.168.10.1, zperf will bind both ipv4 and ipv6 sockets on ipv4 address. But bind ipv6 socket will fail, thus command return fail. Fix it by check ip address when zperf download. For ipv4 address only bind ipv4 socket. For ipv6 address only bind ipv6 socket. For unspecific address bind both ipv4 and ipv6 sockets. Signed-off-by: Fengming Ye --- subsys/net/lib/zperf/zperf_tcp_receiver.c | 7 +++++-- subsys/net/lib/zperf/zperf_udp_receiver.c | 7 +++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/subsys/net/lib/zperf/zperf_tcp_receiver.c b/subsys/net/lib/zperf/zperf_tcp_receiver.c index 42a0cb844a9..f119f5621f9 100644 --- a/subsys/net/lib/zperf/zperf_tcp_receiver.c +++ b/subsys/net/lib/zperf/zperf_tcp_receiver.c @@ -278,12 +278,15 @@ static int tcp_bind_listen_connection(struct zsock_pollfd *pollfd, static int zperf_tcp_receiver_init(void) { int ret; + int family; for (int i = 0; i < ARRAY_SIZE(fds); i++) { fds[i].fd = -1; } - if (IS_ENABLED(CONFIG_NET_IPV4)) { + family = tcp_server_addr.sa_family; + + if (IS_ENABLED(CONFIG_NET_IPV4) && (family == AF_INET || family == AF_UNSPEC)) { struct sockaddr_in *in4_addr = zperf_get_sin(); const struct in_addr *addr = NULL; @@ -329,7 +332,7 @@ static int zperf_tcp_receiver_init(void) } } - if (IS_ENABLED(CONFIG_NET_IPV6)) { + if (IS_ENABLED(CONFIG_NET_IPV6) && (family == AF_INET6 || family == AF_UNSPEC)) { struct sockaddr_in6 *in6_addr = zperf_get_sin6(); const struct in6_addr *addr = NULL; diff --git a/subsys/net/lib/zperf/zperf_udp_receiver.c b/subsys/net/lib/zperf/zperf_udp_receiver.c index 2e213e24961..5f6c7c539fd 100644 --- a/subsys/net/lib/zperf/zperf_udp_receiver.c +++ b/subsys/net/lib/zperf/zperf_udp_receiver.c @@ -311,12 +311,15 @@ static void udp_svc_handler(struct k_work *work) static int zperf_udp_receiver_init(void) { int ret; + int family; for (int i = 0; i < ARRAY_SIZE(fds); i++) { fds[i].fd = -1; } - if (IS_ENABLED(CONFIG_NET_IPV4)) { + family = udp_server_addr.sa_family; + + if (IS_ENABLED(CONFIG_NET_IPV4) && (family == AF_INET || family == AF_UNSPEC)) { const struct in_addr *in4_addr = NULL; in4_addr_my = zperf_get_sin(); @@ -365,7 +368,7 @@ static int zperf_udp_receiver_init(void) fds[SOCK_ID_IPV4].events = ZSOCK_POLLIN; } - if (IS_ENABLED(CONFIG_NET_IPV6)) { + if (IS_ENABLED(CONFIG_NET_IPV6) && (family == AF_INET6 || family == AF_UNSPEC)) { const struct in6_addr *in6_addr = NULL; in6_addr_my = zperf_get_sin6(); From 276dc8c1388f931ea859f165700e7bcd8d72ddbe Mon Sep 17 00:00:00 2001 From: Charles Dias Date: Thu, 1 Feb 2024 18:38:00 -0300 Subject: [PATCH 0646/2402] boards: arm: fk7b0m1_vbt6: add support to external NOR Flash Updates the DTS file by adding support for QSPI and SPI NOR Flash. Signed-off-by: Charles Dias --- boards/fanke/fk7b0m1_vbt6/doc/index.rst | 57 ++++++++++------------ boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts | 55 +++++++++++++++++++++ 2 files changed, 82 insertions(+), 30 deletions(-) diff --git a/boards/fanke/fk7b0m1_vbt6/doc/index.rst b/boards/fanke/fk7b0m1_vbt6/doc/index.rst index 220fc514d4c..dfabfd54e88 100644 --- a/boards/fanke/fk7b0m1_vbt6/doc/index.rst +++ b/boards/fanke/fk7b0m1_vbt6/doc/index.rst @@ -57,7 +57,7 @@ More information about STM32H7B0VB can be found here: Supported Features ================== -The Zephyr nucleo_h723zg board configuration supports the following hardware +The Zephyr fk7b0m1_vbt6 board configuration supports the following hardware features: +-------------+------------+-------------------------------------+ @@ -65,6 +65,8 @@ features: +=============+============+=====================================+ | NVIC | on-chip | nested vector interrupt controller | +-------------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-------------+------------+-------------------------------------+ | UART | on-chip | serial port | +-------------+------------+-------------------------------------+ | PINMUX | on-chip | pinmux | @@ -75,19 +77,20 @@ features: +-------------+------------+-------------------------------------+ | Backup SRAM | on-chip | Backup SRAM | +-------------+------------+-------------------------------------+ +| SPI | on-chip | spi bus | ++-------------+------------+-------------------------------------+ +| OCTOSPI | on-chip | octospi | ++-------------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. The default configuration per core can be found in :zephyr_file:`boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig` -Connections and IOs -=================== - -Available pins: ---------------- +Pin Mapping +=========== -Nucleo FK7B0M1-VBT6 board has 6 GPIO controllers. These controllers are responsible for pin muxing, +FK7B0M1-VBT6 board has 5 GPIO controllers. These controllers are responsible for pin muxing, input/output, pull-up, etc. .. figure:: img/fk7b0m1_vbt6_pins.webp @@ -97,29 +100,17 @@ input/output, pull-up, etc. FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd) -LED ---- - -- User LED (blue) = PC1 - -Push buttons -------------------------- - -- BOOT = SW1 = BOOT0 -- RESET = SW2 = NRST -- User button = SW3 = PC13 +Default Zephyr Peripheral Mapping: +---------------------------------- -UART ------ +The FK7B0M1-VBT6 board is configured as follows -- TX device = USART1 PA9 -- RX device = USART1 PA10 - -USB ---- - -- USB D- = PA11 -- USB D+ = PA12 +- UART_1 TX/RX : PA9/PA10 (available on the header pins) +- User LED (blue) : PC1 +- User PB : PC13 +- SPI1 NCS/CLK/MISO/MOSI : PA15/PB3/PB4/PB5 (NOR Flash) +- QuadSPI NCS/CLK/IO0/IO1/IO2/IO3 : PB6/PB2/PD11/PD12/PE2/PD13 (NOR Flash) +- USB DM/DP : PA11/PA12 System Clock ============ @@ -136,13 +127,19 @@ The Zephyr console output is assigned to UART1. The default communication settin Programming and Debugging ************************* +Applications for the ``fk7b0m1_vbt6`` board configuration can be built and flashed in the usual +way (see :ref:`build_an_application` and :ref:`application_run` for more details). + +Flashing +======== + The FK7B0M1-VBT6 board does not include an on-board debugger. As a result, it requires an external debugger, such as ST-Link, for programming and debugging purposes. The board provides header pins for the Serial Wire Debug (SWD) interface. -Flashing -======== +Flashing an application to FK7B0M1-VBT6 +--------------------------------------- To begin, connect the ST-Link Debug Programmer to the FK7B0M1-VBT6 board using the SWD interface. Next, connect the ST-Link to your host computer via a USB port. diff --git a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts index 536c7b6e780..090a29a1981 100644 --- a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts +++ b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts @@ -41,6 +41,7 @@ aliases { led0 = &user_led; sw0 = &user_button; + spi-flash0 = &w25q64jvssiq_spi; }; }; @@ -75,6 +76,60 @@ d3ppre = <2>; }; +&octospi1 { + pinctrl-0 = <&octospim_p1_clk_pb2 &octospim_p1_ncs_pb6 + &octospim_p1_io0_pd11 &octospim_p1_io1_pd12 + &octospim_p1_io2_pe2 &octospim_p1_io3_pd13>; + pinctrl-names = "default"; + status = "okay"; + + /* Winbond external flash */ + w25q64jvssiq_qspi: qspi-nor-flash@0 { + compatible = "st,stm32-ospi-nor"; + reg = <0 DT_SIZE_M(8)>; /* 64 Mbits */ + ospi-max-frequency = ; + spi-bus-width = ; + data-rate = ; + writeoc = "PP_1_1_4"; + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + slot0_partition: partition@0 { + reg = <0x00000000 DT_SIZE_M(8)>; /* 64 Mbits */ + }; + }; + }; +}; + +&spi6 { + pinctrl-0 = <&spi6_sck_pb3 &spi6_miso_pb4 &spi6_mosi_pb5>; + cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + status = "okay"; + w25q64jvssiq_spi: spi-nor-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = ; + size = ; /* 64 Mbits */ + status = "okay"; + jedec-id = [ef 40 17]; + has-dpd; + t-enter-dpd = <3500>; + t-exit-dpd = <3500>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + storage_partition: partition@0 { + label = "storage"; + reg = <0x00000000 DT_SIZE_M(8)>; /* 64 Mbits */ + }; + }; + }; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; pinctrl-names = "default"; From c803b1e1f444d10ecb4495eca1ce85926dc8cbc4 Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Tue, 12 Mar 2024 16:59:22 +0800 Subject: [PATCH 0647/2402] Samples: Bluetooth: HF: Fix link key missing issue The bonding info is not loaded after the Bluetooth initialization again. Call settings_load after the Bluetooth initialized. Signed-off-by: Lyle Zhu --- samples/bluetooth/handsfree/src/main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/samples/bluetooth/handsfree/src/main.c b/samples/bluetooth/handsfree/src/main.c index e45cd08bc8c..6aeb7219f0a 100644 --- a/samples/bluetooth/handsfree/src/main.c +++ b/samples/bluetooth/handsfree/src/main.c @@ -17,6 +17,7 @@ #include #include #include +#include static void connected(struct bt_conn *conn) { @@ -88,6 +89,10 @@ static void bt_ready(int err) return; } + if (IS_ENABLED(CONFIG_SETTINGS)) { + settings_load(); + } + printk("Bluetooth initialized\n"); err = bt_br_set_connectable(true); From 752079a07029e9d2feb3583ed5a6096a972b501d Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 13 Mar 2024 09:41:28 +0100 Subject: [PATCH 0648/2402] samples: drivers: mbox: fix nRF54H20 vevif/bellboard regexes Both VEVIF and BELLBOARD test cases are unidirectional from the core executing the test (cpuapp). For VEVIF, cpuapp pings, and for BELLBOARD, cpuapp pongs. Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/sample.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml index 75a39dc4939..de33b04a3a0 100644 --- a/samples/drivers/mbox/sample.yaml +++ b/samples/drivers/mbox/sample.yaml @@ -42,7 +42,6 @@ tests: ordered: false regex: - "Ping \\(on channel 4\\)" - - "Pong \\(on channel 4\\)" sample.drivers.mbox.nrf54h20_bellboard: platform_allow: @@ -61,7 +60,6 @@ tests: type: multi_line ordered: false regex: - - "Ping \\(on channel 0\\)" - "Pong \\(on channel 0\\)" sample.drivers.mbox.simu: From 154b2b9c1cae8d0593cf078de7e68e05bde3ed79 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Wed, 13 Mar 2024 23:44:49 +0000 Subject: [PATCH 0649/2402] input: pat912x: fix build with default cpi setting Fix up the BUILD_ASSERT so that it does not trigger if the resolution cpi is not specified in the devicetree and left to the default value. Also use the correct spelling for "cpi". Signed-off-by: Fabio Baltieri --- drivers/input/input_pat912x.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/input/input_pat912x.c b/drivers/input/input_pat912x.c index be47d1d8dd2..2e0602fcedc 100644 --- a/drivers/input/input_pat912x.c +++ b/drivers/input/input_pat912x.c @@ -325,10 +325,10 @@ static int pat912x_pm_action(const struct device *dev, #endif #define PAT912X_INIT(n) \ - BUILD_ASSERT(IN_RANGE(DT_INST_PROP(n, res_x_cpi), 0, RES_MAX), \ - "invalid res-x-cpy"); \ - BUILD_ASSERT(IN_RANGE(DT_INST_PROP(n, res_y_cpi), 0, RES_MAX), \ - "invalid res-y-cpy"); \ + BUILD_ASSERT(IN_RANGE(DT_INST_PROP_OR(n, res_x_cpi, 0), 0, RES_MAX), \ + "invalid res-x-cpi"); \ + BUILD_ASSERT(IN_RANGE(DT_INST_PROP_OR(n, res_y_cpi, 0), 0, RES_MAX), \ + "invalid res-y-cpi"); \ BUILD_ASSERT(DT_INST_PROP(n, sleep1_enable) || \ !DT_INST_PROP(n, sleep2_enable), \ "invalid sleep configuration"); \ From f34f06058890e8a2628429bf67917dc8d6996487 Mon Sep 17 00:00:00 2001 From: Chen Xingyu Date: Thu, 14 Mar 2024 11:56:01 +0800 Subject: [PATCH 0650/2402] include: drivers: led: Correct comment for `struct led_info` The comments for `index` and `num_colors` in `struct led_info` were mistakenly swapped. This commit corrects them to accurately reflect their actual purpose. Signed-off-by: Chen Xingyu --- include/zephyr/drivers/led.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/zephyr/drivers/led.h b/include/zephyr/drivers/led.h index cb178a9442d..8f01da811b6 100644 --- a/include/zephyr/drivers/led.h +++ b/include/zephyr/drivers/led.h @@ -36,9 +36,9 @@ extern "C" { struct led_info { /** LED label */ const char *label; - /** Number of colors per LED */ - uint32_t index; /** Index of the LED on the controller */ + uint32_t index; + /** Number of colors per LED */ uint8_t num_colors; /** Mapping of the LED colors */ const uint8_t *color_mapping; From ebced020ec82d96f037c3a7c0e022322bbb1dd1d Mon Sep 17 00:00:00 2001 From: Maochen Wang Date: Tue, 12 Mar 2024 18:35:16 +0800 Subject: [PATCH 0651/2402] net: arp: Fix failed to add the arp table in stress test During stress test with WiFi connect, disconnect, ping and throughput traffic, ARP table updating failed issue may occur. In arp_prepare(), if packet allocate failed, should add the arp entry back to arp_free_entries, to avoid this entry is leak forever. Signed-off-by: Maochen Wang --- subsys/net/l2/ethernet/arp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/subsys/net/l2/ethernet/arp.c b/subsys/net/l2/ethernet/arp.c index 5619c1b28d0..27e27b50f25 100644 --- a/subsys/net/l2/ethernet/arp.c +++ b/subsys/net/l2/ethernet/arp.c @@ -416,6 +416,13 @@ struct net_pkt *net_arp_prepare(struct net_pkt *pkt, NET_DBG("Resending ARP %p", req); } + if (!req && entry) { + /* Add the arp entry back to arp_free_entries, to avoid the + * arp entry is leak due to ARP packet allocated failed. + */ + sys_slist_prepend(&arp_free_entries, &entry->node); + } + k_mutex_unlock(&arp_mutex); return req; } From 9d801c4fdc79df587e22c7d3b45b3ce19cd4a5d1 Mon Sep 17 00:00:00 2001 From: Daniel Nejezchleb Date: Wed, 13 Mar 2024 18:43:12 +0100 Subject: [PATCH 0652/2402] net: tcp: Fix possible deadlock in tcp The mutex was removed in tcp_recv() where it doesn't seem to be needed anymore as tcp_conn_search() got tcp_mutex. In the other areas the tcp_mutex was narrowed down to protect only the list. Signed-off-by: Daniel Nejezchleb --- subsys/net/ip/tcp.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/subsys/net/ip/tcp.c b/subsys/net/ip/tcp.c index b2d59d49d66..3c8f17bec7f 100644 --- a/subsys/net/ip/tcp.c +++ b/subsys/net/ip/tcp.c @@ -720,8 +720,6 @@ static void tcp_conn_release(struct k_work *work) } #endif - k_mutex_lock(&tcp_lock, K_FOREVER); - /* Application is no longer there, unref any remaining packets on the * fifo (although there shouldn't be any at this point.) */ @@ -761,11 +759,11 @@ static void tcp_conn_release(struct k_work *work) net_context_unref(conn->context); conn->context = NULL; + k_mutex_lock(&tcp_lock, K_FOREVER); sys_slist_find_and_remove(&tcp_conns, &conn->next); + k_mutex_unlock(&tcp_lock); k_mem_slab_free(&tcp_conns_slab, (void *)conn); - - k_mutex_unlock(&tcp_lock); } #if defined(CONFIG_NET_TEST) @@ -2092,7 +2090,9 @@ static struct tcp *tcp_conn_alloc(void) tcp_conn_ref(conn); + k_mutex_lock(&tcp_lock, K_FOREVER); sys_slist_append(&tcp_conns, &conn->next); + k_mutex_unlock(&tcp_lock); out: NET_DBG("conn: %p", conn); @@ -2113,19 +2113,15 @@ int net_tcp_get(struct net_context *context) int ret = 0; struct tcp *conn; - k_mutex_lock(&tcp_lock, K_FOREVER); - conn = tcp_conn_alloc(); if (conn == NULL) { ret = -ENOMEM; - goto out; + return ret; } /* Mutually link the net_context and tcp connection */ conn->context = context; context->tcp = conn; -out: - k_mutex_unlock(&tcp_lock); return ret; } @@ -2154,6 +2150,8 @@ static struct tcp *tcp_conn_search(struct net_pkt *pkt) struct tcp *conn; struct tcp *tmp; + k_mutex_lock(&tcp_lock, K_FOREVER); + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&tcp_conns, conn, tmp, next) { found = tcp_conn_cmp(conn, pkt); if (found) { @@ -2161,6 +2159,8 @@ static struct tcp *tcp_conn_search(struct net_pkt *pkt) } } + k_mutex_unlock(&tcp_lock); + return found ? conn : NULL; } @@ -2179,8 +2179,6 @@ static enum net_verdict tcp_recv(struct net_conn *net_conn, ARG_UNUSED(net_conn); ARG_UNUSED(proto); - k_mutex_lock(&tcp_lock, K_FOREVER); - conn = tcp_conn_search(pkt); if (conn) { goto in; @@ -2200,8 +2198,6 @@ static enum net_verdict tcp_recv(struct net_conn *net_conn, conn->accepted_conn = conn_old; } in: - k_mutex_unlock(&tcp_lock); - if (conn) { verdict = tcp_in(conn, pkt); } else { @@ -4270,7 +4266,6 @@ void net_tcp_foreach(net_tcp_cb_t cb, void *user_data) k_mutex_lock(&tcp_lock, K_FOREVER); SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&tcp_conns, conn, tmp, next) { - if (atomic_get(&conn->ref_count) > 0) { k_mutex_unlock(&tcp_lock); cb(conn, user_data); From 42c8b7fb00a8f6343966e140b4bba593bb92cfdb Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Wed, 13 Mar 2024 13:49:17 +0000 Subject: [PATCH 0653/2402] boards: actinius: Move common folder Moves the common folder to the vendor directory Signed-off-by: Jamie McCrae --- boards/{common/actinius => actinius/common}/CMakeLists.txt | 0 boards/{common/actinius => actinius/common}/Kconfig | 0 .../actinius => actinius/common}/actinius_board_common.c | 0 boards/actinius/icarus/CMakeLists.txt | 2 +- boards/actinius/icarus/Kconfig.defconfig | 2 +- boards/actinius/icarus_bee/CMakeLists.txt | 2 +- boards/actinius/icarus_bee/Kconfig.defconfig | 2 +- boards/actinius/icarus_som/CMakeLists.txt | 2 +- boards/actinius/icarus_som/Kconfig.defconfig | 2 +- boards/actinius/icarus_som_dk/CMakeLists.txt | 2 +- boards/actinius/icarus_som_dk/Kconfig.defconfig | 2 +- 11 files changed, 8 insertions(+), 8 deletions(-) rename boards/{common/actinius => actinius/common}/CMakeLists.txt (100%) rename boards/{common/actinius => actinius/common}/Kconfig (100%) rename boards/{common/actinius => actinius/common}/actinius_board_common.c (100%) diff --git a/boards/common/actinius/CMakeLists.txt b/boards/actinius/common/CMakeLists.txt similarity index 100% rename from boards/common/actinius/CMakeLists.txt rename to boards/actinius/common/CMakeLists.txt diff --git a/boards/common/actinius/Kconfig b/boards/actinius/common/Kconfig similarity index 100% rename from boards/common/actinius/Kconfig rename to boards/actinius/common/Kconfig diff --git a/boards/common/actinius/actinius_board_common.c b/boards/actinius/common/actinius_board_common.c similarity index 100% rename from boards/common/actinius/actinius_board_common.c rename to boards/actinius/common/actinius_board_common.c diff --git a/boards/actinius/icarus/CMakeLists.txt b/boards/actinius/icarus/CMakeLists.txt index 9a434a4d73d..6e24c3f3b20 100644 --- a/boards/actinius/icarus/CMakeLists.txt +++ b/boards/actinius/icarus/CMakeLists.txt @@ -3,4 +3,4 @@ # # SPDX-License-Identifier: Apache-2.0 -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) +add_subdirectory(${ZEPHYR_BASE}/boards/actinius/common actinius_common) diff --git a/boards/actinius/icarus/Kconfig.defconfig b/boards/actinius/icarus/Kconfig.defconfig index 80f8e6cab5d..b5a635ca0d4 100644 --- a/boards/actinius/icarus/Kconfig.defconfig +++ b/boards/actinius/icarus/Kconfig.defconfig @@ -5,7 +5,7 @@ if BOARD_ACTINIUS_ICARUS -source "boards/common/actinius/Kconfig" +source "boards/actinius/common/Kconfig" # For the secure version of the board the firmware is linked at the beginning # of the flash, or into the code-partition defined in DT if it is intended to diff --git a/boards/actinius/icarus_bee/CMakeLists.txt b/boards/actinius/icarus_bee/CMakeLists.txt index 7ddd62dbb2d..7c43b7e76fc 100644 --- a/boards/actinius/icarus_bee/CMakeLists.txt +++ b/boards/actinius/icarus_bee/CMakeLists.txt @@ -3,4 +3,4 @@ # # SPDX-License-Identifier: Apache-2.0 -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) +add_subdirectory(${ZEPHYR_BASE}/boards/actinius/common actinius_common) diff --git a/boards/actinius/icarus_bee/Kconfig.defconfig b/boards/actinius/icarus_bee/Kconfig.defconfig index 3eaf7f5f1c6..3c191e96ced 100644 --- a/boards/actinius/icarus_bee/Kconfig.defconfig +++ b/boards/actinius/icarus_bee/Kconfig.defconfig @@ -5,7 +5,7 @@ if BOARD_ACTINIUS_ICARUS_BEE -source "boards/common/actinius/Kconfig" +source "boards/actinius/common/Kconfig" # For the secure version of the board the firmware is linked at the beginning # of the flash, or into the code-partition defined in DT if it is intended to diff --git a/boards/actinius/icarus_som/CMakeLists.txt b/boards/actinius/icarus_som/CMakeLists.txt index 7ddd62dbb2d..7c43b7e76fc 100644 --- a/boards/actinius/icarus_som/CMakeLists.txt +++ b/boards/actinius/icarus_som/CMakeLists.txt @@ -3,4 +3,4 @@ # # SPDX-License-Identifier: Apache-2.0 -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) +add_subdirectory(${ZEPHYR_BASE}/boards/actinius/common actinius_common) diff --git a/boards/actinius/icarus_som/Kconfig.defconfig b/boards/actinius/icarus_som/Kconfig.defconfig index 43730eb6945..42d244ac763 100644 --- a/boards/actinius/icarus_som/Kconfig.defconfig +++ b/boards/actinius/icarus_som/Kconfig.defconfig @@ -5,7 +5,7 @@ if BOARD_ACTINIUS_ICARUS_SOM -source "boards/common/actinius/Kconfig" +source "boards/actinius/common/Kconfig" # For the secure version of the board the firmware is linked at the beginning # of the flash, or into the code-partition defined in DT if it is intended to diff --git a/boards/actinius/icarus_som_dk/CMakeLists.txt b/boards/actinius/icarus_som_dk/CMakeLists.txt index 4e57b25bdf1..0001d45c219 100644 --- a/boards/actinius/icarus_som_dk/CMakeLists.txt +++ b/boards/actinius/icarus_som_dk/CMakeLists.txt @@ -3,4 +3,4 @@ # # SPDX-License-Identifier: Apache-2.0 -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) +add_subdirectory(${ZEPHYR_BASE}/boards/actinius/common actinius_common) diff --git a/boards/actinius/icarus_som_dk/Kconfig.defconfig b/boards/actinius/icarus_som_dk/Kconfig.defconfig index 62e848d3468..3993f59dbf2 100644 --- a/boards/actinius/icarus_som_dk/Kconfig.defconfig +++ b/boards/actinius/icarus_som_dk/Kconfig.defconfig @@ -5,7 +5,7 @@ if BOARD_ACTINIUS_ICARUS_SOM_DK -source "boards/common/actinius/Kconfig" +source "boards/actinius/common/Kconfig" # For the secure version of the board the firmware is linked at the beginning # of the flash, or into the code-partition defined in DT if it is intended to From e36d15c971c3102ce6b45ae8b89b60c76121c69d Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Fri, 8 Mar 2024 12:35:22 +0100 Subject: [PATCH 0654/2402] manifest: hal_nordic: update revision to have nrfx 3.4.0 release New hal_nordic revision contains nrfx 3.4.0 which adds support for nRF54H20 and nRF54L15 devices. Signed-off-by: Nikodem Kastelik --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 093a45b7ea0..ed24e557701 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: 5470822384781624efb2fda28cbc6a895a227677 + revision: 13ac55b5b52c905642e9c54f069109d188aa5840 path: modules/hal/nordic groups: - hal From cb6f44c3b966be0953f4794e729c7fbe3053b0ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Tue, 12 Mar 2024 12:11:57 +0100 Subject: [PATCH 0655/2402] drivers: nrf_qspi_nor: Handle anomaly 159 on nRF5340 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The nrfx_qspi driver in nrfx 3.4.0 started checking conditions that could trigger anomaly 159 on nRF5340 so make sure that QSPI transfers are only performed with properly configured clocks (PCLK192M undivided and HCLK128M divided by 2). Signed-off-by: Andrzej Głąbek --- drivers/flash/nrf_qspi_nor.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/flash/nrf_qspi_nor.c b/drivers/flash/nrf_qspi_nor.c index c0e8c397d8e..c2ac5f3f3ba 100644 --- a/drivers/flash/nrf_qspi_nor.c +++ b/drivers/flash/nrf_qspi_nor.c @@ -21,6 +21,7 @@ LOG_MODULE_REGISTER(qspi_nor, CONFIG_FLASH_LOG_LEVEL); #include "spi_nor.h" #include "jesd216.h" #include "flash_priv.h" +#include #include #include #include @@ -101,6 +102,11 @@ BUILD_ASSERT(INST_0_SCK_FREQUENCY >= (NRF_QSPI_BASE_CLOCK_FREQ / 16), /* For requested SCK >= 96 MHz, use HFCLK192M / 1 / (2*1) = 96 MHz */ #define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_1 #define INST_0_SCK_CFG NRF_QSPI_FREQ_DIV1 +/* If anomaly 159 is to be prevented, only /1 divider can be used. */ +#elif NRF53_ERRATA_159_ENABLE_WORKAROUND +#define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_1 +#define INST_0_SCK_CFG (DIV_ROUND_UP(NRF_QSPI_BASE_CLOCK_FREQ, \ + INST_0_SCK_FREQUENCY) - 1) #elif (INST_0_SCK_FREQUENCY >= (NRF_QSPI_BASE_CLOCK_FREQ / 2)) /* For 96 MHz > SCK >= 48 MHz, use HFCLK192M / 2 / (2*1) = 48 MHz */ #define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_2 @@ -115,6 +121,13 @@ BUILD_ASSERT(INST_0_SCK_FREQUENCY >= (NRF_QSPI_BASE_CLOCK_FREQ / 16), #define INST_0_SCK_CFG (DIV_ROUND_UP(NRF_QSPI_BASE_CLOCK_FREQ / 2, \ INST_0_SCK_FREQUENCY) - 1) #endif +/* After the base clock divider is changed, some time is needed for the new + * setting to take effect. This value specifies the delay (in microseconds) + * to be applied to ensure that the clock is ready when the QSPI operation + * starts. It was measured with a logic analyzer (unfortunately, the nRF5340 + * specification does not provide any numbers in this regard). + */ +#define BASE_CLOCK_SWITCH_DELAY_US 7 #else /* @@ -230,6 +243,12 @@ static inline int qspi_get_zephyr_ret_code(nrfx_err_t res) return -EINVAL; case NRFX_ERROR_INVALID_STATE: return -ECANCELED; +#if NRF53_ERRATA_159_ENABLE_WORKAROUND + case NRFX_ERROR_FORBIDDEN: + LOG_ERR("nRF5340 anomaly 159 conditions detected"); + LOG_ERR("Set the CPU clock to 64 MHz before starting QSPI operation"); + return -ECANCELED; +#endif case NRFX_ERROR_BUSY: case NRFX_ERROR_TIMEOUT: default: @@ -262,6 +281,7 @@ static inline void qspi_clock_div_change(void) * before a QSPI transfer is performed. */ nrf_clock_hfclk192m_div_set(NRF_CLOCK, BASE_CLOCK_DIV); + k_busy_wait(BASE_CLOCK_SWITCH_DELAY_US); #endif } From d60df3d0d516ac8794a712fc4dd77a7b5814dd24 Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Thu, 14 Mar 2024 10:53:45 +0100 Subject: [PATCH 0656/2402] boards/starfive/visionfive2: use `riscv` in the `arch` field This commit changes the value of the `arch` from `riscv64` to `riscv`, so that it is in line with the rest of the RISC-V boards. Signed-off-by: Filip Kokosinski --- boards/starfive/visionfive2/visionfive2.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/starfive/visionfive2/visionfive2.yaml b/boards/starfive/visionfive2/visionfive2.yaml index a3288093496..59fe38f12c3 100644 --- a/boards/starfive/visionfive2/visionfive2.yaml +++ b/boards/starfive/visionfive2/visionfive2.yaml @@ -1,7 +1,7 @@ identifier: visionfive2 name: Visionfive JH7110 (NON-SMP) type: mcu -arch: riscv64 +arch: riscv toolchain: - zephyr - cross-compile From 9882cf11cc47f5896a7793e0fec23f03cefa2b94 Mon Sep 17 00:00:00 2001 From: Tomas Galbicka Date: Thu, 14 Mar 2024 09:36:01 +0100 Subject: [PATCH 0657/2402] drivers: mbox: Fix nxp,mbox kconfig depends on This commit fixes Kconfig.nxp_mailbox depends on is now set to correct value DT_HAS_NXP_MBOX_MAILBOX_ENABLED. Signed-off-by: Tomas Galbicka --- drivers/mbox/Kconfig.nxp_mailbox | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mbox/Kconfig.nxp_mailbox b/drivers/mbox/Kconfig.nxp_mailbox index fa1c2dc79d1..79ffee05acf 100644 --- a/drivers/mbox/Kconfig.nxp_mailbox +++ b/drivers/mbox/Kconfig.nxp_mailbox @@ -4,6 +4,6 @@ config MBOX_NXP_MAILBOX bool "NXP Mailbox driver for MBOX" default y - depends on DT_HAS_NXP_LPC_MAILBOX_ENABLED + depends on DT_HAS_NXP_MBOX_MAILBOX_ENABLED help Driver for NXP Mailbox Unit around MBOX. From 3c2b68eb61e559fb082a990ef80075d5d2af0a7f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20G=C5=82=C4=85b?= Date: Thu, 14 Mar 2024 09:14:07 +0100 Subject: [PATCH 0658/2402] drivers: watchdog: wdt_nrfx.c Fix channel id check in wdt_feed() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A Bug in the watchdog driver code allows an unconfigured WDT timer channel to be feed. The first configured WDT timer channel has an id of zero. At this point, data->m_allocated_channels is equal to one. The condition of the if statement is invalid and allows channel one to be feed. Change the test condition from greater to greater-or-equal. Add check if channel id is less than zero. Signed-off-by: Sebastian Głąb --- drivers/watchdog/wdt_nrfx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/wdt_nrfx.c b/drivers/watchdog/wdt_nrfx.c index 8967d1e162b..5601470b540 100644 --- a/drivers/watchdog/wdt_nrfx.c +++ b/drivers/watchdog/wdt_nrfx.c @@ -128,7 +128,7 @@ static int wdt_nrf_feed(const struct device *dev, int channel_id) const struct wdt_nrfx_config *config = dev->config; struct wdt_nrfx_data *data = dev->data; - if (channel_id > data->m_allocated_channels) { + if ((channel_id >= data->m_allocated_channels) || (channel_id < 0)) { return -EINVAL; } From dde7c47e6a6f0e5d56208b8f2a6d09512b9f6d14 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Thu, 14 Mar 2024 08:43:49 +0100 Subject: [PATCH 0659/2402] soc: nordic: Fix validation of base addresses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use `DT_REG_HAS_IDX()` instead of `DT_NODE_EXISTS()` when checking if for a given nodelabel the base address of the associated node should be validated, so that the validation is performed only if the base address is available. This prevents build failures in cases like the os_mgmt_datetime test where the `rtc` nodelabel is used for an emulated RTC. Signed-off-by: Andrzej Głąbek --- soc/nordic/validate_base_addresses.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/nordic/validate_base_addresses.c b/soc/nordic/validate_base_addresses.c index e11a4fd3256..1d7d5190ba5 100644 --- a/soc/nordic/validate_base_addresses.c +++ b/soc/nordic/validate_base_addresses.c @@ -90,7 +90,7 @@ */ #define CHECK_DT_REG(lbl, mdk_addr) \ BUILD_ASSERT( \ - UTIL_OR(UTIL_NOT(DT_NODE_EXISTS(DT_NODELABEL(lbl))), \ + UTIL_OR(UTIL_NOT(DT_REG_HAS_IDX(DT_NODELABEL(lbl), 0)), \ (DT_REG_ADDR(DT_NODELABEL(lbl)) == (uint32_t)(mdk_addr)))) /** From 2d9a2cec8d14ecf794c3f7bf0b91d8574c063419 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Thu, 14 Mar 2024 11:44:01 +0100 Subject: [PATCH 0660/2402] modules: tf-m: Prevent unwanted updating of HAL Since the move to HW model v2, the MCUxpresso NXP SDK drivers got updated during the build due to a missed rename. This caused parallel builds and CI to become flaky. This fixes issue #70215. Signed-off-by: Reto Schneider --- modules/trusted-firmware-m/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/trusted-firmware-m/CMakeLists.txt b/modules/trusted-firmware-m/CMakeLists.txt index 146d1751203..d70e0121f75 100644 --- a/modules/trusted-firmware-m/CMakeLists.txt +++ b/modules/trusted-firmware-m/CMakeLists.txt @@ -226,7 +226,7 @@ if (CONFIG_BUILD_WITH_TFM) string(REPLACE "toolchain" "toolchain_ns" TFM_TOOLCHAIN_NS_FILE ${TFM_TOOLCHAIN_FILE}) - if(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0) + if(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS) # Supply path to NXP HAL sources used for TF-M build set(TFM_PLATFORM_NXP_HAL_FILE_PATH ${ZEPHYR_TRUSTED_FIRMWARE_M_MODULE_DIR}/platform/ext/target/nxp/) list(APPEND TFM_CMAKE_ARGS -DTFM_PLATFORM_NXP_HAL_FILE_PATH=${TFM_PLATFORM_NXP_HAL_FILE_PATH}) From 947d4a13c30b42fd0849a592e615d31ecdf82f9c Mon Sep 17 00:00:00 2001 From: Stefan Schwendeler Date: Fri, 24 Feb 2023 13:38:24 +0100 Subject: [PATCH 0661/2402] net: lwm2m: removes redundant newline for log and shell calls All the shell and logger calls here already add a newline. Signed-off-by: Stefan Schwendeler --- subsys/net/lib/lwm2m/lwm2m_shell.c | 96 +++++++++++++++--------------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/subsys/net/lib/lwm2m/lwm2m_shell.c b/subsys/net/lib/lwm2m/lwm2m_shell.c index 13f38fefe66..5f4d3e20269 100644 --- a/subsys/net/lib/lwm2m/lwm2m_shell.c +++ b/subsys/net/lib/lwm2m/lwm2m_shell.c @@ -57,7 +57,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME); static void send_cb(enum lwm2m_send_status status) { - LOG_INF("SEND status: %d\n", status); + LOG_INF("SEND status: %d", status); } static int cmd_send(const struct shell *sh, size_t argc, char **argv) @@ -68,12 +68,12 @@ static int cmd_send(const struct shell *sh, size_t argc, char **argv) struct lwm2m_obj_path lwm2m_path_list[CONFIG_LWM2M_COMPOSITE_PATH_LIST_SIZE]; if (!ctx) { - shell_error(sh, "no lwm2m context yet\n"); + shell_error(sh, "no lwm2m context yet"); return -ENOEXEC; } if (argc < 2) { - shell_error(sh, "no path(s)\n"); + shell_error(sh, "no path(s)"); shell_help(sh); return -EINVAL; } @@ -94,7 +94,7 @@ static int cmd_send(const struct shell *sh, size_t argc, char **argv) ret = lwm2m_send_cb(ctx, lwm2m_path_list, path_cnt, send_cb); if (ret < 0) { - shell_error(sh, "can't do send operation, request failed (%d)\n", ret); + shell_error(sh, "can't do send operation, request failed (%d)", ret); return -ENOEXEC; } return 0; @@ -105,7 +105,7 @@ static int cmd_exec(const struct shell *sh, size_t argc, char **argv) struct lwm2m_ctx *ctx = lwm2m_rd_client_ctx(); if (!ctx) { - shell_error(sh, "no lwm2m context yet\n"); + shell_error(sh, "no lwm2m context yet"); return -ENOEXEC; } @@ -114,19 +114,19 @@ static int cmd_exec(const struct shell *sh, size_t argc, char **argv) int ret = lwm2m_string_to_path(pathstr, &path, '/'); /* translate path -> path_obj */ if (ret < 0) { - shell_error(sh, "Illegal path (PATH %s)\n", pathstr); + shell_error(sh, "Illegal path (PATH %s)", pathstr); return -EINVAL; } struct lwm2m_engine_res *res = lwm2m_engine_get_res(&path); if (res == NULL) { - shell_error(sh, "Resource not found\n"); + shell_error(sh, "Resource not found"); return -EINVAL; } if (!res->execute_cb) { - shell_error(sh, "No execute callback\n!"); + shell_error(sh, "No execute callback!"); return -EINVAL; } @@ -136,7 +136,7 @@ static int cmd_exec(const struct shell *sh, size_t argc, char **argv) ret = res->execute_cb(path.obj_inst_id, param, param_len); if (ret < 0) { - shell_error(sh, "returned (err %d)\n", ret); + shell_error(sh, "returned (err %d)", ret); return -ENOEXEC; } @@ -148,12 +148,12 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) struct lwm2m_ctx *ctx = lwm2m_rd_client_ctx(); if (!ctx) { - shell_error(sh, "no lwm2m context yet\n"); + shell_error(sh, "no lwm2m context yet"); return -ENOEXEC; } if (argc < 2) { - shell_error(sh, "no arguments or path(s)\n"); + shell_error(sh, "no arguments or path(s)"); shell_help(sh); return -EINVAL; } @@ -189,7 +189,7 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) if (ret != 0) { goto out; } - shell_print(sh, "%.*s\n", buff_len, buff); + shell_print(sh, "%.*s", buff_len, buff); } else if (strcmp(dtype, "-s8") == 0) { int8_t temp = 0; @@ -197,7 +197,7 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) if (ret != 0) { goto out; } - shell_print(sh, "%d\n", temp); + shell_print(sh, "%d", temp); } else if (strcmp(dtype, "-s16") == 0) { int16_t temp = 0; @@ -205,7 +205,7 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) if (ret != 0) { goto out; } - shell_print(sh, "%d\n", temp); + shell_print(sh, "%d", temp); } else if (strcmp(dtype, "-s32") == 0) { int32_t temp = 0; @@ -213,7 +213,7 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) if (ret != 0) { goto out; } - shell_print(sh, "%d\n", temp); + shell_print(sh, "%d", temp); } else if (strcmp(dtype, "-s64") == 0) { int64_t temp = 0; @@ -221,7 +221,7 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) if (ret != 0) { goto out; } - shell_print(sh, "%lld\n", temp); + shell_print(sh, "%lld", temp); } else if (strcmp(dtype, "-u8") == 0) { uint8_t temp = 0; @@ -229,7 +229,7 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) if (ret != 0) { goto out; } - shell_print(sh, "%d\n", temp); + shell_print(sh, "%d", temp); } else if (strcmp(dtype, "-u16") == 0) { uint16_t temp = 0; @@ -237,7 +237,7 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) if (ret != 0) { goto out; } - shell_print(sh, "%d\n", temp); + shell_print(sh, "%d", temp); } else if (strcmp(dtype, "-u32") == 0) { uint32_t temp = 0; @@ -245,7 +245,7 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) if (ret != 0) { goto out; } - shell_print(sh, "%d\n", temp); + shell_print(sh, "%d", temp); } else if (strcmp(dtype, "-f") == 0) { double temp = 0; @@ -253,7 +253,7 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) if (ret != 0) { goto out; } - shell_print(sh, "%f\n", temp); + shell_print(sh, "%f", temp); } else if (strcmp(dtype, "-b") == 0) { bool temp; @@ -261,7 +261,7 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) if (ret != 0) { goto out; } - shell_print(sh, "%d\n", temp); + shell_print(sh, "%d", temp); } else if (strcmp(dtype, "-t") == 0) { time_t temp; @@ -269,15 +269,15 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv) if (ret != 0) { goto out; } - shell_print(sh, "%lld\n", temp); + shell_print(sh, "%lld", temp); } else { - shell_error(sh, "can't recognize data type %s\n", dtype); + shell_error(sh, "can't recognize data type %s", dtype); shell_help(sh); return -EINVAL; } return 0; out: - shell_error(sh, "can't do read operation, request failed (err %d)\n", ret); + shell_error(sh, "can't do read operation, request failed (err %d)", ret); return -EINVAL; } @@ -286,12 +286,12 @@ static int cmd_write(const struct shell *sh, size_t argc, char **argv) struct lwm2m_ctx *ctx = lwm2m_rd_client_ctx(); if (!ctx) { - shell_error(sh, "no lwm2m context yet\n"); + shell_error(sh, "no lwm2m context yet"); return -ENOEXEC; } if (argc < 3) { - shell_error(sh, "no arguments or path(s)\n"); + shell_error(sh, "no arguments or path(s)"); shell_help(sh); return -EINVAL; } @@ -346,13 +346,13 @@ static int cmd_write(const struct shell *sh, size_t argc, char **argv) } else if (strcmp(dtype, "-t") == 0) { ret = lwm2m_set_time(&path, strtoll(value, &e, 10)); } else { - shell_error(sh, "can't recognize data type %s\n", + shell_error(sh, "can't recognize data type %s", dtype); shell_help(sh); return -EINVAL; } if (*e != '\0') { - shell_error(sh, "Invalid number: %s\n", value); + shell_error(sh, "Invalid number: %s", value); shell_help(sh); return -EINVAL; } @@ -361,7 +361,7 @@ static int cmd_write(const struct shell *sh, size_t argc, char **argv) if (ret < 0) { shell_error( sh, - "can't do write operation, request failed (err %d)\n", + "can't do write operation, request failed (err %d)", ret); return -ENOEXEC; } @@ -375,14 +375,14 @@ static int cmd_create_or_delete(const struct shell *sh, bool delete, size_t argc int ret; if (argc < 2) { - shell_error(sh, "No object ID given\n"); + shell_error(sh, "No object ID given"); shell_help(sh); return -EINVAL; } ret = lwm2m_string_to_path(argv[1], &path, '/'); if (ret < 0) { - shell_error(sh, "failed to read path (%d)\n", ret); + shell_error(sh, "failed to read path (%d)", ret); return -ENOEXEC; } @@ -411,7 +411,7 @@ static int cmd_create_or_delete(const struct shell *sh, bool delete, size_t argc } if (ret < 0) { - shell_error(sh, "operation failed, %d\n", ret); + shell_error(sh, "operation failed, %d", ret); return -ENOEXEC; } @@ -433,18 +433,18 @@ static int cmd_start(const struct shell *sh, size_t argc, char **argv) struct lwm2m_ctx *ctx = lwm2m_rd_client_ctx(); if (!ctx) { - shell_error(sh, "no lwm2m context yet\n"); + shell_error(sh, "no lwm2m context yet"); return -ENOEXEC; } uint32_t bootstrap_flag = 0; if (argc == 3) { - shell_error(sh, "no specifier or value\n"); + shell_error(sh, "no specifier or value"); shell_help(sh); return -EINVAL; } else if (argc == 4) { if (strcmp(argv[2], "-b") != 0) { - shell_error(sh, "unknown specifier %s\n", argv[2]); + shell_error(sh, "unknown specifier %s", argv[2]); shell_help(sh); return -EINVAL; } @@ -453,7 +453,7 @@ static int cmd_start(const struct shell *sh, size_t argc, char **argv) bootstrap_flag = strtol(argv[3], &e, 10); if (*e != '\0') { - shell_error(sh, "Invalid number: %s\n", argv[3]); + shell_error(sh, "Invalid number: %s", argv[3]); shell_help(sh); return -EINVAL; } @@ -463,7 +463,7 @@ static int cmd_start(const struct shell *sh, size_t argc, char **argv) if (ret < 0) { shell_error( sh, - "can't do start operation, request failed (err %d)\n", + "can't do start operation, request failed (err %d)", ret); return -ENOEXEC; } @@ -475,14 +475,14 @@ static int cmd_stop(const struct shell *sh, size_t argc, char **argv) struct lwm2m_ctx *ctx = lwm2m_rd_client_ctx(); if (!ctx) { - shell_error(sh, "no lwm2m context yet\n"); + shell_error(sh, "no lwm2m context yet"); return -ENOEXEC; } bool forcefully = true; if (argc == 2) { if (strcmp(argv[1], "-f") != 0) { - shell_error(sh, "can't recognize specifier %s\n", + shell_error(sh, "can't recognize specifier %s", argv[1]); shell_help(sh); return -EINVAL; @@ -494,7 +494,7 @@ static int cmd_stop(const struct shell *sh, size_t argc, char **argv) if (ret < 0) { shell_error( sh, - "can't do stop operation, request failed (err %d)\n", + "can't do stop operation, request failed (err %d)", ret); return -ENOEXEC; } @@ -508,7 +508,7 @@ static int cmd_update(const struct shell *sh, size_t argc, char **argv) struct lwm2m_ctx *ctx = lwm2m_rd_client_ctx(); if (!ctx) { - shell_error(sh, "no lwm2m context yet\n"); + shell_error(sh, "no lwm2m context yet"); return -ENOEXEC; } lwm2m_rd_client_update(); @@ -562,7 +562,7 @@ static int cmd_cache(const struct shell *sh, size_t argc, char **argv) struct lwm2m_obj_path obj_path; if (argc != 3) { - shell_error(sh, "wrong parameters\n"); + shell_error(sh, "wrong parameters"); return -EINVAL; } @@ -573,30 +573,30 @@ static int cmd_cache(const struct shell *sh, size_t argc, char **argv) } if (obj_path.level < 3) { - shell_error(sh, "Path string not correct\n"); + shell_error(sh, "Path string not correct"); return -EINVAL; } if (lwm2m_cache_entry_get_by_object(&obj_path)) { - shell_error(sh, "Cache already enabled for %s\n", argv[1]); + shell_error(sh, "Cache already enabled for %s", argv[1]); return -ENOEXEC; } elems = atoi(argv[2]); if (elems < 1) { - shell_error(sh, "Size must be 1 or more (given %d)\n", elems); + shell_error(sh, "Size must be 1 or more (given %d)", elems); return -EINVAL; } cache = k_malloc(sizeof(struct lwm2m_time_series_elem) * elems); if (!cache) { - shell_error(sh, "Out of memory\n"); + shell_error(sh, "Out of memory"); return -ENOEXEC; } rc = lwm2m_enable_cache(&obj_path, cache, elems); if (rc) { - shell_error(sh, "lwm2m_enable_cache(%u/%u/%u/%u, %p, %d) returned %d\n", + shell_error(sh, "lwm2m_enable_cache(%u/%u/%u/%u, %p, %d) returned %d", obj_path.obj_id, obj_path.obj_inst_id, obj_path.res_id, obj_path.res_inst_id, cache, elems, rc); k_free(cache); @@ -605,7 +605,7 @@ static int cmd_cache(const struct shell *sh, size_t argc, char **argv) return 0; #else - shell_error(sh, "No heap configured\n"); + shell_error(sh, "No heap configured"); return -ENOEXEC; #endif } From 49c6da51cec2d0808a5624769fc7d1560274fe64 Mon Sep 17 00:00:00 2001 From: Takuya Sasaki Date: Tue, 12 Mar 2024 13:27:45 +0900 Subject: [PATCH 0662/2402] net: conn: Move net_conn_change_callback() to static The net_conn_change_callback() is not currently being called by anyone, so this commit moves to static function, and replaces the change callback parameter process in net_conn_register(). Signed-off-by: Takuya Sasaki --- subsys/net/ip/connection.c | 36 ++++++++++++------------------------ subsys/net/ip/connection.h | 13 ------------- 2 files changed, 12 insertions(+), 37 deletions(-) diff --git a/subsys/net/ip/connection.c b/subsys/net/ip/connection.c index 267521e1680..c1521a938ff 100644 --- a/subsys/net/ip/connection.c +++ b/subsys/net/ip/connection.c @@ -268,6 +268,16 @@ static struct net_conn *conn_find_handler(struct net_if *iface, return NULL; } +static void net_conn_change_callback(struct net_conn *conn, + net_conn_cb_t cb, void *user_data) +{ + NET_DBG("[%zu] connection handler %p changed callback", + conn - conns, conn); + + conn->cb = cb; + conn->user_data = user_data; +} + int net_conn_register(uint16_t proto, uint8_t family, const struct sockaddr *remote_addr, const struct sockaddr *local_addr, @@ -376,8 +386,8 @@ int net_conn_register(uint16_t proto, uint8_t family, net_sin(&conn->local_addr)->sin_port = htons(local_port); } - conn->cb = cb; - conn->user_data = user_data; + net_conn_change_callback(conn, cb, user_data); + conn->flags = flags; conn->proto = proto; conn->family = family; @@ -422,28 +432,6 @@ int net_conn_unregister(struct net_conn_handle *handle) return 0; } -int net_conn_change_callback(struct net_conn_handle *handle, - net_conn_cb_t cb, void *user_data) -{ - struct net_conn *conn = (struct net_conn *)handle; - - if (conn < &conns[0] || conn > &conns[CONFIG_NET_MAX_CONN]) { - return -EINVAL; - } - - if (!(conn->flags & NET_CONN_IN_USE)) { - return -ENOENT; - } - - NET_DBG("[%zu] connection handler %p changed callback", - conn - conns, conn); - - conn->cb = cb; - conn->user_data = user_data; - - return 0; -} - static bool conn_addr_cmp(struct net_pkt *pkt, union net_ip_header *ip_hdr, struct sockaddr *addr, diff --git a/subsys/net/ip/connection.h b/subsys/net/ip/connection.h index ee7ee0efc7d..9fb40acd18e 100644 --- a/subsys/net/ip/connection.h +++ b/subsys/net/ip/connection.h @@ -156,19 +156,6 @@ static inline int net_conn_unregister(struct net_conn_handle *handle) } #endif -/** - * @brief Change the callback and user_data for a registered connection - * handle. - * - * @param handle A handle registered with net_conn_register() - * @param cb Callback to be called - * @param user_data User data supplied by caller. - * - * @return Return 0 if the the change succeed, <0 otherwise. - */ -int net_conn_change_callback(struct net_conn_handle *handle, - net_conn_cb_t cb, void *user_data); - /** * @brief Called by net_core.c when a network packet is received. * From ef18518e91415e6811a96e7c954e14075bd94549 Mon Sep 17 00:00:00 2001 From: Takuya Sasaki Date: Wed, 13 Mar 2024 19:21:10 +0900 Subject: [PATCH 0663/2402] net: conn: Add static function for changing remote This commit adds the new static function for change the remote address and port to connection, and replaces the changing process for remote address and port in net_conn_register(). Signed-off-by: Takuya Sasaki --- subsys/net/ip/connection.c | 89 ++++++++++++++++++++++++-------------- 1 file changed, 57 insertions(+), 32 deletions(-) diff --git a/subsys/net/ip/connection.c b/subsys/net/ip/connection.c index c1521a938ff..902eaaa2f96 100644 --- a/subsys/net/ip/connection.c +++ b/subsys/net/ip/connection.c @@ -278,6 +278,53 @@ static void net_conn_change_callback(struct net_conn *conn, conn->user_data = user_data; } +static int net_conn_change_remote(struct net_conn *conn, + const struct sockaddr *remote_addr, + uint16_t remote_port) +{ + NET_DBG("[%zu] connection handler %p changed remote", + conn - conns, conn); + + if (remote_addr) { + if (IS_ENABLED(CONFIG_NET_IPV6) && + remote_addr->sa_family == AF_INET6) { + memcpy(&conn->remote_addr, remote_addr, + sizeof(struct sockaddr_in6)); + + if (!net_ipv6_is_addr_unspecified( + &net_sin6(remote_addr)-> + sin6_addr)) { + conn->flags |= NET_CONN_REMOTE_ADDR_SPEC; + } + } else if (IS_ENABLED(CONFIG_NET_IPV4) && + remote_addr->sa_family == AF_INET) { + memcpy(&conn->remote_addr, remote_addr, + sizeof(struct sockaddr_in)); + + if (net_sin(remote_addr)->sin_addr.s_addr) { + conn->flags |= NET_CONN_REMOTE_ADDR_SPEC; + } + } else { + NET_ERR("Remote address family not set"); + return -EINVAL; + } + + conn->flags |= NET_CONN_REMOTE_ADDR_SET; + } else { + conn->flags &= ~NET_CONN_REMOTE_ADDR_SPEC; + conn->flags &= ~NET_CONN_REMOTE_ADDR_SET; + } + + if (remote_port) { + conn->flags |= NET_CONN_REMOTE_PORT_SPEC; + net_sin(&conn->remote_addr)->sin_port = htons(remote_port); + } else { + conn->flags &= ~NET_CONN_REMOTE_PORT_SPEC; + } + + return 0; +} + int net_conn_register(uint16_t proto, uint8_t family, const struct sockaddr *remote_addr, const struct sockaddr *local_addr, @@ -290,6 +337,7 @@ int net_conn_register(uint16_t proto, uint8_t family, { struct net_conn *conn; uint8_t flags = 0U; + int ret; conn = conn_find_handler(context != NULL ? net_context_get_iface(context) : NULL, proto, family, remote_addr, local_addr, @@ -307,33 +355,6 @@ int net_conn_register(uint16_t proto, uint8_t family, return -ENOENT; } - if (remote_addr) { - if (IS_ENABLED(CONFIG_NET_IPV6) && - remote_addr->sa_family == AF_INET6) { - memcpy(&conn->remote_addr, remote_addr, - sizeof(struct sockaddr_in6)); - - if (!net_ipv6_is_addr_unspecified( - &net_sin6(remote_addr)-> - sin6_addr)) { - flags |= NET_CONN_REMOTE_ADDR_SPEC; - } - } else if (IS_ENABLED(CONFIG_NET_IPV4) && - remote_addr->sa_family == AF_INET) { - memcpy(&conn->remote_addr, remote_addr, - sizeof(struct sockaddr_in)); - - if (net_sin(remote_addr)->sin_addr.s_addr) { - flags |= NET_CONN_REMOTE_ADDR_SPEC; - } - } else { - NET_ERR("Remote address family not set"); - goto error; - } - - flags |= NET_CONN_REMOTE_ADDR_SET; - } - if (local_addr) { if (IS_ENABLED(CONFIG_NET_IPV6) && local_addr->sa_family == AF_INET6) { @@ -376,11 +397,6 @@ int net_conn_register(uint16_t proto, uint8_t family, } } - if (remote_port) { - flags |= NET_CONN_REMOTE_PORT_SPEC; - net_sin(&conn->remote_addr)->sin_port = htons(remote_port); - } - if (local_port) { flags |= NET_CONN_LOCAL_PORT_SPEC; net_sin(&conn->local_addr)->sin_port = htons(local_port); @@ -393,6 +409,15 @@ int net_conn_register(uint16_t proto, uint8_t family, conn->family = family; conn->context = context; + /* + * Since the net_conn_change_remote() updates the flags in connection, + * must to be called after set the flags to connection. + */ + ret = net_conn_change_remote(conn, remote_addr, remote_port); + if (ret) { + goto error; + } + if (handle) { *handle = (struct net_conn_handle *)conn; } From 46ca624be41d6f0029d2d499c2473e718f09f869 Mon Sep 17 00:00:00 2001 From: Takuya Sasaki Date: Wed, 13 Mar 2024 19:27:41 +0900 Subject: [PATCH 0664/2402] net: conn: Add internal function for update connection This commit adds the new internal function for update the callback, user data, remote address, and port for a registered connection handle. Signed-off-by: Takuya Sasaki --- subsys/net/ip/connection.c | 24 ++++++++++++++++++++++++ subsys/net/ip/connection.h | 18 ++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/subsys/net/ip/connection.c b/subsys/net/ip/connection.c index 902eaaa2f96..c5542d1238a 100644 --- a/subsys/net/ip/connection.c +++ b/subsys/net/ip/connection.c @@ -457,6 +457,30 @@ int net_conn_unregister(struct net_conn_handle *handle) return 0; } +int net_conn_update(struct net_conn_handle *handle, + net_conn_cb_t cb, + void *user_data, + const struct sockaddr *remote_addr, + uint16_t remote_port) +{ + struct net_conn *conn = (struct net_conn *)handle; + int ret; + + if (conn < &conns[0] || conn > &conns[CONFIG_NET_MAX_CONN]) { + return -EINVAL; + } + + if (!(conn->flags & NET_CONN_IN_USE)) { + return -ENOENT; + } + + net_conn_change_callback(conn, cb, user_data); + + ret = net_conn_change_remote(conn, remote_addr, remote_port); + + return ret; +} + static bool conn_addr_cmp(struct net_pkt *pkt, union net_ip_header *ip_hdr, struct sockaddr *addr, diff --git a/subsys/net/ip/connection.h b/subsys/net/ip/connection.h index 9fb40acd18e..cc495cde7a7 100644 --- a/subsys/net/ip/connection.h +++ b/subsys/net/ip/connection.h @@ -156,6 +156,24 @@ static inline int net_conn_unregister(struct net_conn_handle *handle) } #endif +/** + * @brief Update the callback, user data, remote address, and port + * for a registered connection handle. + * + * @param handle A handle registered with net_conn_register() + * @param cb Callback to be called + * @param user_data User data supplied by caller. + * @param remote_addr Remote address + * @param remote_port Remote port + * + * @return Return 0 if the the change succeed, <0 otherwise. + */ +int net_conn_update(struct net_conn_handle *handle, + net_conn_cb_t cb, + void *user_data, + const struct sockaddr *remote_addr, + uint16_t remote_port); + /** * @brief Called by net_core.c when a network packet is received. * From 4f802e11974591f758f84b2653d1b31f9c5e4f93 Mon Sep 17 00:00:00 2001 From: Takuya Sasaki Date: Sun, 10 Mar 2024 20:32:44 +0900 Subject: [PATCH 0665/2402] net: context: Fix the ICMP error on udp When receiving a UDP packet, net_conn_input() searches for a matching connection within `conn_used`. However, when receiving UDP packets simultaneously from multiple clients, we may encounter a situation where the connection that was supposed to be bound cannot be found within `conn_used`, and raise the ICMP error. This is because, within recv_udp(), to avoid the failure of bind_default(), we temporarily remove it from `conn_used` using net_conn_unregister(). If the context already has a connection handler, it means it's already registered. In that case, all we have to do is 1) update the callback registered in the net_context and 2) update the user_data and remote address and port using net_conn_update(). Fixes #70020 Signed-off-by: Takuya Sasaki --- subsys/net/ip/net_context.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/subsys/net/ip/net_context.c b/subsys/net/ip/net_context.c index ae7a4a4e848..38d60dc028b 100644 --- a/subsys/net/ip/net_context.c +++ b/subsys/net/ip/net_context.c @@ -2401,9 +2401,24 @@ static int recv_udp(struct net_context *context, ARG_UNUSED(timeout); + /* If the context already has a connection handler, it means it's + * already registered. In that case, all we have to do is 1) update + * the callback registered in the net_context and 2) update the + * user_data and remote address and port using net_conn_update(). + * + * The callback function passed to net_conn_update() must be the same + * function as the one passed to net_conn_register(), not the callback + * set for the net context passed by recv_udp(). + */ if (context->conn_handler) { - net_conn_unregister(context->conn_handler); - context->conn_handler = NULL; + context->recv_cb = cb; + ret = net_conn_update(context->conn_handler, + net_context_packet_received, + user_data, + context->flags & NET_CONTEXT_REMOTE_ADDR_SET ? + &context->remote : NULL, + ntohs(net_sin(&context->remote)->sin_port)); + return ret; } ret = bind_default(context); From 7d1edd1fcb3516f0b8b8c07fe55086675d3e382f Mon Sep 17 00:00:00 2001 From: Takuya Sasaki Date: Tue, 12 Mar 2024 16:30:24 +0900 Subject: [PATCH 0666/2402] net: context: Fix the ICMP error on raw This commit applies the issues detected in UDP to recv_raw() as well. Please refer to the previous commit log for details. Signed-off-by: Takuya Sasaki --- subsys/net/ip/net_context.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/subsys/net/ip/net_context.c b/subsys/net/ip/net_context.c index 38d60dc028b..6bf60bc0e37 100644 --- a/subsys/net/ip/net_context.c +++ b/subsys/net/ip/net_context.c @@ -2512,11 +2512,22 @@ static int recv_raw(struct net_context *context, ARG_UNUSED(timeout); - context->recv_cb = cb; - + /* If the context already has a connection handler, it means it's + * already registered. In that case, all we have to do is 1) update + * the callback registered in the net_context and 2) update the + * user_data using net_conn_update(). + * + * The callback function passed to net_conn_update() must be the same + * function as the one passed to net_conn_register(), not the callback + * set for the net context passed by recv_raw(). + */ if (context->conn_handler) { - net_conn_unregister(context->conn_handler); - context->conn_handler = NULL; + context->recv_cb = cb; + ret = net_conn_update(context->conn_handler, + net_context_raw_packet_received, + user_data, + NULL, 0); + return ret; } ret = bind_default(context); @@ -2524,6 +2535,8 @@ static int recv_raw(struct net_context *context, return ret; } + context->recv_cb = cb; + ret = net_conn_register(net_context_get_proto(context), net_context_get_family(context), NULL, local_addr, 0, 0, From b610312314d4f34ac0a49ec93f40ae5068093dd9 Mon Sep 17 00:00:00 2001 From: Emil Lindqvist Date: Mon, 15 Jan 2024 13:43:37 +0100 Subject: [PATCH 0667/2402] modem_cellular: add registration status API This commit implements a network registration status API, including return of reject cause in case of denial. Signed-off-by: Emil Lindqvist --- drivers/modem/modem_cellular.c | 53 +++++++++++++++++++++++-------- include/zephyr/drivers/cellular.h | 40 +++++++++++++++++++++++ 2 files changed, 80 insertions(+), 13 deletions(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 1c8e9b08347..f5081d5f69a 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -102,9 +102,9 @@ struct modem_cellular_data { uint8_t *chat_argv[32]; /* Status */ - uint8_t registration_status_gsm; - uint8_t registration_status_gprs; - uint8_t registration_status_lte; + enum cellular_registration_status registration_status_gsm; + enum cellular_registration_status registration_status_gprs; + enum cellular_registration_status registration_status_lte; uint8_t rssi; uint8_t rsrp; uint8_t rsrq; @@ -376,22 +376,19 @@ static void modem_cellular_chat_on_imsi(struct modem_chat *chat, char **argv, ui static bool modem_cellular_is_registered(struct modem_cellular_data *data) { - return (data->registration_status_gsm == 1) - || (data->registration_status_gsm == 5) - || (data->registration_status_gprs == 1) - || (data->registration_status_gprs == 5) - || (data->registration_status_lte == 1) - || (data->registration_status_lte == 5); + return (data->registration_status_gsm == CELLULAR_REGISTRATION_REGISTERED_HOME) + || (data->registration_status_gsm == CELLULAR_REGISTRATION_REGISTERED_ROAMING) + || (data->registration_status_gprs == CELLULAR_REGISTRATION_REGISTERED_HOME) + || (data->registration_status_gprs == CELLULAR_REGISTRATION_REGISTERED_ROAMING) + || (data->registration_status_lte == CELLULAR_REGISTRATION_REGISTERED_HOME) + || (data->registration_status_lte == CELLULAR_REGISTRATION_REGISTERED_ROAMING); } static void modem_cellular_chat_on_cxreg(struct modem_chat *chat, char **argv, uint16_t argc, void *user_data) { struct modem_cellular_data *data = (struct modem_cellular_data *)user_data; - uint8_t registration_status; - bool is_registered; - - is_registered = modem_cellular_is_registered(data); + enum cellular_registration_status registration_status = 0; if (argc == 2) { registration_status = atoi(argv[1]); @@ -1410,10 +1407,40 @@ static int modem_cellular_get_modem_info(const struct device *dev, return ret; } +static int modem_cellular_get_registration_status(const struct device *dev, + enum cellular_access_technology tech, + enum cellular_registration_status *status) +{ + int ret = 0; + struct modem_cellular_data *data = (struct modem_cellular_data *)dev->data; + + switch (tech) { + case CELLULAR_ACCESS_TECHNOLOGY_GSM: + *status = data->registration_status_gsm; + break; + case CELLULAR_ACCESS_TECHNOLOGY_GPRS: + case CELLULAR_ACCESS_TECHNOLOGY_UMTS: + case CELLULAR_ACCESS_TECHNOLOGY_EDGE: + *status = data->registration_status_gprs; + break; + case CELLULAR_ACCESS_TECHNOLOGY_LTE: + case CELLULAR_ACCESS_TECHNOLOGY_LTE_CAT_M1: + case CELLULAR_ACCESS_TECHNOLOGY_LTE_CAT_M2: + case CELLULAR_ACCESS_TECHNOLOGY_NB_IOT: + *status = data->registration_status_lte; + break; + default: + ret = -ENODATA; + break; + } + + return ret; +} const static struct cellular_driver_api modem_cellular_api = { .get_signal = modem_cellular_get_signal, .get_modem_info = modem_cellular_get_modem_info, + .get_registration_status = modem_cellular_get_registration_status, }; #ifdef CONFIG_PM_DEVICE diff --git a/include/zephyr/drivers/cellular.h b/include/zephyr/drivers/cellular.h index fba05e6e440..3ff832e5c09 100644 --- a/include/zephyr/drivers/cellular.h +++ b/include/zephyr/drivers/cellular.h @@ -76,6 +76,15 @@ enum cellular_modem_info_type { CELLULAR_MODEM_INFO_SIM_ICCID, }; +enum cellular_registration_status { + CELLULAR_REGISTRATION_NOT_REGISTERED = 0, + CELLULAR_REGISTRATION_REGISTERED_HOME, + CELLULAR_REGISTRATION_SEARCHING, + CELLULAR_REGISTRATION_DENIED, + CELLULAR_REGISTRATION_UNKNOWN, + CELLULAR_REGISTRATION_REGISTERED_ROAMING, +}; + /** API for configuring networks */ typedef int (*cellular_api_configure_networks)(const struct device *dev, const struct cellular_network *networks, @@ -95,12 +104,18 @@ typedef int (*cellular_api_get_modem_info)(const struct device *dev, const enum cellular_modem_info_type type, char *info, size_t size); +/** API for getting registration status */ +typedef int (*cellular_api_get_registration_status)(const struct device *dev, + enum cellular_access_technology tech, + enum cellular_registration_status *status); + /** Cellular driver API */ __subsystem struct cellular_driver_api { cellular_api_configure_networks configure_networks; cellular_api_get_supported_networks get_supported_networks; cellular_api_get_signal get_signal; cellular_api_get_modem_info get_modem_info; + cellular_api_get_registration_status get_registration_status; }; /** @@ -210,6 +225,31 @@ static inline int cellular_get_modem_info(const struct device *dev, return api->get_modem_info(dev, type, info, size); } +/** + * @brief Get network registration status for the device + * + * @param dev Cellular network device instance + * @param tech Which access technology to get status for + * @param status Registration status for given access technology + * + * @retval 0 if successful. + * @retval -ENOSYS if API is not supported by cellular network device. + * @retval -ENODATA if modem does not provide info requested + * @retval Negative errno-code from chat module otherwise. + */ +static inline int cellular_get_registration_status(const struct device *dev, + enum cellular_access_technology tech, + enum cellular_registration_status *status) +{ + const struct cellular_driver_api *api = (const struct cellular_driver_api *)dev->api; + + if (api->get_registration_status == NULL) { + return -ENOSYS; + } + + return api->get_registration_status(dev, tech, status); +} + #ifdef __cplusplus } #endif From 136a3d3671376a719fa2b1450adccc758dce05ca Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Tue, 12 Mar 2024 14:14:23 +0000 Subject: [PATCH 0668/2402] west.yml: MCUboot synchronization from upstream Update Zephyr fork of MCUboot to revision: 9fb7ce5d026db42768d63f04cc60ce022d27b555 Brings following Zephyr relevant fixes: - 9fb7ce5d boot: zephyr: Fix estimated size calculation - 7ace8bd4 zephyr: boards: Remove CONFIG_FPROTECT from nrf54l15 Signed-off-by: Jamie McCrae --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index ed24e557701..99ccbd49d4f 100644 --- a/west.yml +++ b/west.yml @@ -282,7 +282,7 @@ manifest: groups: - crypto - name: mcuboot - revision: 8b4c70ab6dc03d2826c166dedb56541950defa8c + revision: 9fb7ce5d026db42768d63f04cc60ce022d27b555 path: bootloader/mcuboot - name: mipi-sys-t path: modules/debug/mipi-sys-t From 3c3bee96ef0f3e26d2eaeb18a1789e1415f71920 Mon Sep 17 00:00:00 2001 From: Kurtis Dinelle Date: Sat, 20 Jan 2024 11:23:30 -0800 Subject: [PATCH 0669/2402] drivers: sensor: tsl2591 Add the tsl2591 sensor to drivers. Signed-off-by: Kurtis Dinelle --- drivers/sensor/CMakeLists.txt | 1 + drivers/sensor/Kconfig | 1 + drivers/sensor/tsl2591/CMakeLists.txt | 6 + drivers/sensor/tsl2591/Kconfig | 63 +++ drivers/sensor/tsl2591/tsl2591.c | 535 ++++++++++++++++++ drivers/sensor/tsl2591/tsl2591.h | 151 +++++ drivers/sensor/tsl2591/tsl2591_trigger.c | 156 +++++ dts/bindings/sensor/ams,tsl2591.yaml | 17 + include/zephyr/drivers/sensor/tsl2591.h | 68 +++ tests/drivers/build_all/sensor/i2c.dtsi | 6 + .../sensor/sensors_trigger_global.conf | 1 + .../sensor/sensors_trigger_none.conf | 1 + .../build_all/sensor/sensors_trigger_own.conf | 1 + 13 files changed, 1007 insertions(+) create mode 100644 drivers/sensor/tsl2591/CMakeLists.txt create mode 100644 drivers/sensor/tsl2591/Kconfig create mode 100644 drivers/sensor/tsl2591/tsl2591.c create mode 100644 drivers/sensor/tsl2591/tsl2591.h create mode 100644 drivers/sensor/tsl2591/tsl2591_trigger.c create mode 100644 dts/bindings/sensor/ams,tsl2591.yaml create mode 100644 include/zephyr/drivers/sensor/tsl2591.h diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index e9ccd669faa..d90be761d2f 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -158,6 +158,7 @@ add_subdirectory_ifdef(CONFIG_TMP112 tmp112) add_subdirectory_ifdef(CONFIG_TMP116 tmp116) add_subdirectory_ifdef(CONFIG_TSL2540 tsl2540) add_subdirectory_ifdef(CONFIG_TSL2561 tsl2561) +add_subdirectory_ifdef(CONFIG_TSL2591 tsl2591) add_subdirectory_ifdef(CONFIG_VCMP_IT8XXX2 ite_vcmp_it8xxx2) add_subdirectory_ifdef(CONFIG_VCNL4040 vcnl4040) add_subdirectory_ifdef(CONFIG_VCNL36825T vcnl36825t) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index a85d949678c..5f5860543a3 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -238,6 +238,7 @@ source "drivers/sensor/tmp112/Kconfig" source "drivers/sensor/tmp116/Kconfig" source "drivers/sensor/tsl2540/Kconfig" source "drivers/sensor/tsl2561/Kconfig" +source "drivers/sensor/tsl2591/Kconfig" source "drivers/sensor/vcnl4040/Kconfig" source "drivers/sensor/vcnl36825t/Kconfig" source "drivers/sensor/veml7700/Kconfig" diff --git a/drivers/sensor/tsl2591/CMakeLists.txt b/drivers/sensor/tsl2591/CMakeLists.txt new file mode 100644 index 00000000000..deccc02f8e5 --- /dev/null +++ b/drivers/sensor/tsl2591/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(tsl2591.c) +zephyr_library_sources_ifdef(CONFIG_TSL2591_TRIGGER tsl2591_trigger.c) diff --git a/drivers/sensor/tsl2591/Kconfig b/drivers/sensor/tsl2591/Kconfig new file mode 100644 index 00000000000..4718f577e12 --- /dev/null +++ b/drivers/sensor/tsl2591/Kconfig @@ -0,0 +1,63 @@ +# Copyright (c) 2023 Kurtis Dinelle +# SPDX-License-Identifier: Apache-2.0 + +menuconfig TSL2591 + bool "OSRAM-AMS TSL2591 light sensor" + default y + depends on DT_HAS_AMS_TSL2591_ENABLED + select I2C + help + Enable driver for TSL2591 sensor. + +if TSL2591 +config TSL2591_FETCH_WAIT + bool "Wait for valid sensor reading before fetch" + help + If set, the driver will automatically wait for the duration of an integration cycle + during a fetch call if necessary. + +config TSL2591_WARN_SATURATED + bool "Warn if sensor is potentially saturated" + help + If set, the driver will warn if the sensor ADC is + potentially saturated after a data fetch. + +config TSL2591_TRIGGER + bool + +choice + prompt "Trigger mode" + default TSL2591_TRIGGER_NONE + help + Specify the type of triggering to be used by the driver. + +config TSL2591_TRIGGER_NONE + bool "No trigger" + +config TSL2591_TRIGGER_GLOBAL_THREAD + bool "Use global thread" + depends on GPIO + select TSL2591_TRIGGER + +config TSL2591_TRIGGER_OWN_THREAD + bool "Use own thread" + depends on GPIO + select TSL2591_TRIGGER + +endchoice + +config TSL2591_THREAD_PRIORITY + int "Thread priority" + depends on TSL2591_TRIGGER_OWN_THREAD + default 10 + help + Priority of thread used by the driver to handle interrupts. + +config TSL2591_THREAD_STACK_SIZE + int "Thread stack size" + depends on TSL2591_TRIGGER_OWN_THREAD + default 1024 + help + Stack size of thread used by the driver to handle interrupts. + +endif # TSL2591 diff --git a/drivers/sensor/tsl2591/tsl2591.c b/drivers/sensor/tsl2591/tsl2591.c new file mode 100644 index 00000000000..ee2c0b56cb4 --- /dev/null +++ b/drivers/sensor/tsl2591/tsl2591.c @@ -0,0 +1,535 @@ +/* + * Copyright (c) 2023 Kurtis Dinelle + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ams_tsl2591 + +#include +#include +#include +#include "tsl2591.h" + +LOG_MODULE_REGISTER(TSL2591, CONFIG_SENSOR_LOG_LEVEL); + +static int tsl2591_reg_read(const struct device *dev, uint8_t reg, uint8_t *buf, uint8_t size) +{ + const struct tsl2591_config *config = dev->config; + uint8_t cmd = TSL2591_NORMAL_CMD | reg; + + return i2c_write_read_dt(&config->i2c, &cmd, 1U, buf, size); +} + +static int tsl2591_reg_write(const struct device *dev, uint8_t reg, uint8_t val) +{ + const struct tsl2591_config *config = dev->config; + uint8_t cmd[2] = {TSL2591_NORMAL_CMD | reg, val}; + + return i2c_write_dt(&config->i2c, cmd, 2U); +} + +int tsl2591_reg_update(const struct device *dev, uint8_t reg, uint8_t mask, uint8_t val) +{ + uint8_t old_value, new_value; + int ret; + + ret = tsl2591_reg_read(dev, reg, &old_value, 1U); + if (ret < 0) { + return ret; + } + + new_value = (old_value & ~mask) | (val & mask); + if (new_value == old_value) { + return 0; + } + + return tsl2591_reg_write(dev, reg, new_value); +} + +static int tsl2591_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + struct tsl2591_data *data = dev->data; + uint8_t als_data[4]; + int ret; + +#ifdef CONFIG_TSL2591_FETCH_WAIT + uint8_t status; + + ret = tsl2591_reg_read(dev, TSL2591_REG_STATUS, &status, 1U); + if (ret < 0) { + LOG_ERR("Failed to read status register"); + return ret; + } + + /* Check if ALS has completed an integration cycle since AEN asserted. + * If not, sleep for the duration of an integration cycle to ensure valid reading. + */ + if (!(status & TSL2591_AVALID_MASK)) { + k_msleep((data->atime / 100) * TSL2591_MAX_TIME_STEP); + } + + /* Reassert AEN to determine if next reading is valid */ + ret = tsl2591_reg_update(dev, TSL2591_REG_ENABLE, TSL2591_AEN_MASK, TSL2591_AEN_OFF); + if (ret < 0) { + LOG_ERR("Failed to disable ALS"); + return ret; + } + + ret = tsl2591_reg_update(dev, TSL2591_REG_ENABLE, TSL2591_AEN_MASK, TSL2591_AEN_ON); + if (ret < 0) { + LOG_ERR("Failed to re-enable ALS"); + return ret; + } +#endif + + switch (chan) { + case SENSOR_CHAN_ALL: + ret = tsl2591_reg_read(dev, TSL2591_REG_C0DATAL, als_data, 4U); + if (ret < 0) { + LOG_ERR("Failed to read ALS data"); + return ret; + } + + data->vis_count = sys_get_le16(als_data); + data->ir_count = sys_get_le16(als_data + 2); + break; + case SENSOR_CHAN_LIGHT: + ret = tsl2591_reg_read(dev, TSL2591_REG_C0DATAL, als_data, 2U); + if (ret < 0) { + LOG_ERR("Failed to read ALS visible light data"); + return ret; + } + + data->vis_count = sys_get_le16(als_data); + break; + case SENSOR_CHAN_IR: + ret = tsl2591_reg_read(dev, TSL2591_REG_C1DATAL, als_data, 2U); + if (ret < 0) { + LOG_ERR("Failed to read ALS infrared data"); + return ret; + } + + data->ir_count = sys_get_le16(als_data); + break; + default: + LOG_ERR("Unsupported sensor channel"); + return -ENOTSUP; + } + +#ifdef CONFIG_TSL2591_WARN_SATURATED + uint16_t max_count = data->atime == 100 ? TSL2591_MAX_ADC_100 : TSL2591_MAX_ADC; + bool vis_saturated = (chan == SENSOR_CHAN_ALL || chan == SENSOR_CHAN_LIGHT) && + (data->vis_count >= max_count); + bool ir_saturated = (chan == SENSOR_CHAN_ALL || chan == SENSOR_CHAN_IR) && + (data->ir_count >= max_count); + if (vis_saturated || ir_saturated) { + LOG_WRN("Sensor ADC potentially saturated, reading may be invalid"); + return -EOVERFLOW; + } +#endif + + return 0; +} + +static int tsl2591_channel_get(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + const struct tsl2591_data *data = dev->data; + int64_t cpl = data->atime * data->again; + int64_t strength; + + /* Unfortunately, datasheet does not provide a lux conversion formula for this particular + * device. There is still ongoing discussion about the proper formula, though this + * implementation uses a slightly modified version of the Adafruit library formula: + * https://github.com/adafruit/Adafruit_TSL2591_Library/ + * + * Since the device relies on both visible and IR readings to calculate lux, + * read SENSOR_CHAN_ALL to get a closer approximation of lux. Reading SENSOR_CHAN_LIGHT or + * SENSOR_CHAN_IR individually can be more closely thought of as relative strength + * as opposed to true lux. + */ + switch (chan) { + case SENSOR_CHAN_ALL: + if (data->vis_count > 0) { + cpl *= 1000000; + strength = + (data->vis_count - data->ir_count) * + (1000000 - (((int64_t)data->ir_count * 1000000) / data->vis_count)); + } else { + strength = 0; + } + break; + case SENSOR_CHAN_LIGHT: + strength = data->vis_count; + break; + case SENSOR_CHAN_IR: + strength = data->ir_count; + break; + default: + LOG_ERR("Unsupported sensor channel"); + return -ENOTSUP; + } + + strength *= TSL2591_LUX_DF; + val->val1 = strength / cpl; + val->val2 = ((strength % cpl) * 1000000) / cpl; + + return 0; +} + +#ifdef CONFIG_TSL2591_TRIGGER +static int tsl2591_set_threshold(const struct device *dev, enum sensor_attribute attr, + const struct sensor_value *val) +{ + const struct tsl2591_data *data = dev->data; + const struct tsl2591_config *config = dev->config; + uint64_t cpl; + uint32_t raw; + uint16_t thld; + uint8_t thld_reg; + uint8_t cmd[3]; + int ret; + + /* Convert from relative strength of visible light to raw value */ + cpl = data->atime * data->again; + raw = ((val->val1 * cpl) / TSL2591_LUX_DF) + + ((val->val2 * cpl) / (1000000U * TSL2591_LUX_DF)); + + if (raw > TSL2591_MAX_ADC) { + LOG_ERR("Given value would overflow threshold register"); + return -EOVERFLOW; + } + + thld = sys_cpu_to_le16(raw); + thld_reg = attr == SENSOR_ATTR_LOWER_THRESH ? TSL2591_REG_AILTL : TSL2591_REG_AIHTL; + + cmd[0] = TSL2591_NORMAL_CMD | thld_reg; + bytecpy(cmd + 1, &thld, 2U); + + ret = i2c_write_dt(&config->i2c, cmd, 3U); + if (ret < 0) { + LOG_ERR("Failed to set interrupt threshold"); + } + + return ret; +} + +static int tsl2591_set_persist(const struct device *dev, int32_t persist_filter) +{ + uint8_t persist_mode; + int ret; + + switch (persist_filter) { + case 0: + persist_mode = TSL2591_PERSIST_EVERY; + break; + case 1: + persist_mode = TSL2591_PERSIST_1; + break; + case 2: + persist_mode = TSL2591_PERSIST_2; + break; + case 3: + persist_mode = TSL2591_PERSIST_3; + break; + case 5: + persist_mode = TSL2591_PERSIST_5; + break; + case 10: + persist_mode = TSL2591_PERSIST_10; + break; + case 15: + persist_mode = TSL2591_PERSIST_15; + break; + case 20: + persist_mode = TSL2591_PERSIST_20; + break; + case 25: + persist_mode = TSL2591_PERSIST_25; + break; + case 30: + persist_mode = TSL2591_PERSIST_30; + break; + case 35: + persist_mode = TSL2591_PERSIST_35; + break; + case 40: + persist_mode = TSL2591_PERSIST_40; + break; + case 45: + persist_mode = TSL2591_PERSIST_45; + break; + case 50: + persist_mode = TSL2591_PERSIST_50; + break; + case 55: + persist_mode = TSL2591_PERSIST_55; + break; + case 60: + persist_mode = TSL2591_PERSIST_60; + break; + default: + LOG_ERR("Invalid persist filter"); + return -EINVAL; + } + + ret = tsl2591_reg_write(dev, TSL2591_REG_PERSIST, persist_mode); + if (ret < 0) { + LOG_ERR("Failed to set persist filter"); + } + + return ret; +} +#endif + +static int tsl2591_set_gain(const struct device *dev, enum sensor_gain_tsl2591 gain) +{ + struct tsl2591_data *data = dev->data; + uint8_t gain_mode; + int ret; + + switch (gain) { + case TSL2591_SENSOR_GAIN_LOW: + data->again = TSL2591_GAIN_SCALE_LOW; + gain_mode = TSL2591_GAIN_MODE_LOW; + break; + case TSL2591_SENSOR_GAIN_MED: + data->again = TSL2591_GAIN_SCALE_MED; + gain_mode = TSL2591_GAIN_MODE_MED; + break; + case TSL2591_SENSOR_GAIN_HIGH: + data->again = TSL2591_GAIN_SCALE_HIGH; + gain_mode = TSL2591_GAIN_MODE_HIGH; + break; + case TSL2591_SENSOR_GAIN_MAX: + data->again = TSL2591_GAIN_SCALE_MAX; + gain_mode = TSL2591_GAIN_MODE_MAX; + break; + default: + LOG_ERR("Invalid gain mode"); + return -EINVAL; + } + + ret = tsl2591_reg_update(dev, TSL2591_REG_CONFIG, TSL2591_AGAIN_MASK, gain_mode); + if (ret < 0) { + LOG_ERR("Failed to set gain mode"); + } + + return ret; +} + +static int tsl2591_set_integration(const struct device *dev, int32_t integration_time) +{ + struct tsl2591_data *data = dev->data; + uint8_t atime_mode; + int ret; + + switch (integration_time) { + case 100: + atime_mode = TSL2591_INTEGRATION_100MS; + break; + case 200: + atime_mode = TSL2591_INTEGRATION_200MS; + break; + case 300: + atime_mode = TSL2591_INTEGRATION_300MS; + break; + case 400: + atime_mode = TSL2591_INTEGRATION_400MS; + break; + case 500: + atime_mode = TSL2591_INTEGRATION_500MS; + break; + case 600: + atime_mode = TSL2591_INTEGRATION_600MS; + break; + default: + LOG_ERR("Invalid integration time"); + return -EINVAL; + } + + ret = tsl2591_reg_update(dev, TSL2591_REG_CONFIG, TSL2591_ATIME_MASK, atime_mode); + if (ret < 0) { + LOG_ERR("Failed to set integration time"); + return ret; + } + + data->atime = integration_time; + + return 0; +} + +static int tsl2591_attr_set(const struct device *dev, enum sensor_channel chan, + enum sensor_attribute attr, const struct sensor_value *val) +{ + const struct tsl2591_data *data = dev->data; + int ret; + + ret = tsl2591_reg_update(dev, TSL2591_REG_ENABLE, TSL2591_POWER_MASK, TSL2591_POWER_OFF); + if (ret < 0) { + LOG_ERR("Unable to power down device"); + return ret; + } + +#ifdef CONFIG_TSL2591_TRIGGER + if (attr == SENSOR_ATTR_UPPER_THRESH || attr == SENSOR_ATTR_LOWER_THRESH) { + if (chan == SENSOR_CHAN_LIGHT) { + ret = tsl2591_set_threshold(dev, attr, val); + } else { + LOG_ERR("Attribute not supported for channel"); + ret = -ENOTSUP; + } + goto exit; + } +#endif + + switch ((enum sensor_attribute_tsl2591)attr) { + case SENSOR_ATTR_GAIN_MODE: + ret = tsl2591_set_gain(dev, (enum sensor_gain_tsl2591)val->val1); + break; + case SENSOR_ATTR_INTEGRATION_TIME: + ret = tsl2591_set_integration(dev, val->val1); + break; + +#ifdef CONFIG_TSL2591_TRIGGER + case SENSOR_ATTR_INT_PERSIST: + ret = tsl2591_set_persist(dev, val->val1); + break; +#endif + default: + LOG_ERR("Invalid sensor attribute"); + ret = -EINVAL; + goto exit; /* So the compiler doesn't warn if triggers not enabled */ + } + +exit: + if (data->powered_on) { + ret = tsl2591_reg_update(dev, TSL2591_REG_ENABLE, TSL2591_POWER_MASK, + TSL2591_POWER_ON); + } + + return ret; +} + +static int tsl2591_setup(const struct device *dev) +{ + struct tsl2591_data *data = dev->data; + uint8_t device_id; + int ret; + + ret = tsl2591_reg_write(dev, TSL2591_REG_CONFIG, TSL2591_SRESET); + if (ret < 0) { + LOG_ERR("Failed to reset device"); + return ret; + } + + ret = tsl2591_reg_read(dev, TSL2591_REG_ID, &device_id, 1U); + if (ret < 0) { + LOG_ERR("Failed to read device ID"); + return ret; + } + + if (device_id != TSL2591_DEV_ID) { + LOG_ERR("Device with ID 0x%02x is not supported", device_id); + return -ENOTSUP; + } + + /* Set initial values to match sensor values on reset */ + data->again = TSL2591_GAIN_SCALE_LOW; + data->atime = 100U; + + ret = tsl2591_reg_write(dev, TSL2591_REG_ENABLE, TSL2591_POWER_ON); + if (ret < 0) { + LOG_ERR("Failed to perform initial power up of device"); + return ret; + } + + data->powered_on = true; + + return 0; +} + +static int tsl2591_init(const struct device *dev) +{ + const struct tsl2591_config *config = dev->config; + int ret; + + if (!i2c_is_ready_dt(&config->i2c)) { + LOG_ERR("I2C dev %s not ready", config->i2c.bus->name); + return -ENODEV; + } + + ret = tsl2591_setup(dev); + if (ret < 0) { + LOG_ERR("Failed to setup device"); + return ret; + } + +#ifdef CONFIG_TSL2591_TRIGGER + ret = tsl2591_initialize_int(dev); + if (ret < 0) { + LOG_ERR("Failed to initialize interrupt!"); + return ret; + } +#endif + + return 0; +} + +static const struct sensor_driver_api tsl2591_driver_api = { +#ifdef CONFIG_TSL2591_TRIGGER + .trigger_set = tsl2591_trigger_set, +#endif + .attr_set = tsl2591_attr_set, + .sample_fetch = tsl2591_sample_fetch, + .channel_get = tsl2591_channel_get}; + +#ifdef CONFIG_PM_DEVICE +static int tsl2591_pm_action(const struct device *dev, enum pm_device_action action) +{ + struct tsl2591_data *data = dev->data; + int ret; + + switch (action) { + case PM_DEVICE_ACTION_RESUME: + ret = tsl2591_reg_update(dev, TSL2591_REG_ENABLE, TSL2591_POWER_MASK, + TSL2591_POWER_ON); + if (ret < 0) { + LOG_ERR("Failed to power on device"); + return ret; + } + + data->powered_on = true; + break; + case PM_DEVICE_ACTION_SUSPEND: + ret = tsl2591_reg_update(dev, TSL2591_REG_ENABLE, TSL2591_POWER_MASK, + TSL2591_POWER_OFF); + if (ret < 0) { + LOG_ERR("Failed to power off device"); + return ret; + } + + data->powered_on = false; + break; + default: + LOG_ERR("Unsupported PM action"); + return -ENOTSUP; + } + + return 0; +} +#endif + +#define TSL2591_INIT_INST(n) \ + static struct tsl2591_data tsl2591_data_##n; \ + static const struct tsl2591_config tsl2591_config_##n = { \ + .i2c = I2C_DT_SPEC_INST_GET(n), \ + IF_ENABLED(CONFIG_TSL2591_TRIGGER, \ + (.int_gpio = GPIO_DT_SPEC_INST_GET_OR(n, int_gpios, {0}),))}; \ + PM_DEVICE_DT_INST_DEFINE(n, tsl2591_pm_action); \ + SENSOR_DEVICE_DT_INST_DEFINE(n, tsl2591_init, PM_DEVICE_DT_INST_GET(n), &tsl2591_data_##n, \ + &tsl2591_config_##n, POST_KERNEL, \ + CONFIG_SENSOR_INIT_PRIORITY, &tsl2591_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(TSL2591_INIT_INST) diff --git a/drivers/sensor/tsl2591/tsl2591.h b/drivers/sensor/tsl2591/tsl2591.h new file mode 100644 index 00000000000..ef2fb5d797b --- /dev/null +++ b/drivers/sensor/tsl2591/tsl2591.h @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2023 Kurtis Dinelle + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_TSL2591_TSL2591_H_ +#define ZEPHYR_DRIVERS_SENSOR_TSL2591_TSL2591_H_ + +#include +#include +#include +#include + +/* Device Identification */ +#define TSL2591_DEV_ID 0x50 + +/* Command: CMD:7 | TRANSACTION:6:5 | ADDR/SF:4:0 */ +#define TSL2591_NORMAL_CMD (BIT(7) | BIT(5)) +#define TSL2591_SPECIAL_CMD (BIT(7) | BIT(6) | BIT(5)) +#define TSL2591_CLEAR_INT_CMD (TSL2591_SPECIAL_CMD | 0x7) + +/* Enable: (0x00): NPIEN:7 | SAI:6 | Reserved:5 | AIEN:4 | Reserved:3:2 | AEN:1 | PON:0 */ +#define TSL2591_POWER_MASK (BIT(1) | BIT(0)) +#define TSL2591_POWER_ON (BIT(1) | BIT(0)) +#define TSL2591_POWER_OFF (0) +#define TSL2591_AEN_MASK (BIT(1)) +#define TSL2591_AEN_ON (BIT(1)) +#define TSL2591_AEN_OFF (0) +#define TSL2591_AIEN_MASK (BIT(4)) +#define TSL2591_AIEN_ON (BIT(4)) +#define TSL2591_AIEN_OFF (0) + +/* Config/Control: (0x01): SRESET:7 | Reserved:6 | AGAIN:5:4 | Reserved:3 | ATIME:2:0 */ +#define TSL2591_SRESET (BIT(7)) +#define TSL2591_AGAIN_MASK (BIT(5) | BIT(4)) +#define TSL2591_ATIME_MASK (BIT(2) | BIT(1) | BIT(0)) + +/* Status: (0x13): Reserved:7:6 | NPINTR:5 | AINT:4 | Reserved:3:1 | AVALID:0 */ +#define TSL2591_AVALID_MASK (BIT(0)) + +/* Register Addresses */ +#define TSL2591_REG_ENABLE 0x00 +#define TSL2591_REG_CONFIG 0x01 +#define TSL2591_REG_AILTL 0x04 +#define TSL2591_REG_AILTH 0x05 +#define TSL2591_REG_AIHTL 0x06 +#define TSL2591_REG_AIHTH 0x07 +#define TSL2591_REG_NPAILTL 0x08 +#define TSL2591_REG_NPAILTH 0x09 +#define TSL2591_REG_NPAIHTL 0x0A +#define TSL2591_REG_NPAIHTH 0x0B +#define TSL2591_REG_PERSIST 0x0C +#define TSL2591_REG_PID 0x11 +#define TSL2591_REG_ID 0x12 +#define TSL2591_REG_STATUS 0x13 +#define TSL2591_REG_C0DATAL 0x14 +#define TSL2591_REG_C0DATAH 0x15 +#define TSL2591_REG_C1DATAL 0x16 +#define TSL2591_REG_C1DATAH 0x17 + +/* Integration Time Modes */ +#define TSL2591_INTEGRATION_100MS 0x00 +#define TSL2591_INTEGRATION_200MS 0x01 +#define TSL2591_INTEGRATION_300MS 0x02 +#define TSL2591_INTEGRATION_400MS 0x03 +#define TSL2591_INTEGRATION_500MS 0x04 +#define TSL2591_INTEGRATION_600MS 0x05 + +/* Gain Modes */ +#define TSL2591_GAIN_MODE_LOW 0x00 +#define TSL2591_GAIN_MODE_MED 0x10 +#define TSL2591_GAIN_MODE_HIGH 0x20 +#define TSL2591_GAIN_MODE_MAX 0x30 + +/* Gain Scales (Typical Values) + * See datasheet, used only for lux calculation. + */ +#define TSL2591_GAIN_SCALE_LOW 1U +#define TSL2591_GAIN_SCALE_MED 25U +#define TSL2591_GAIN_SCALE_HIGH 400U +#define TSL2591_GAIN_SCALE_MAX 9200U + +/* Persistence Filters */ +#define TSL2591_PERSIST_EVERY 0x00 +#define TSL2591_PERSIST_1 0x01 +#define TSL2591_PERSIST_2 0x02 +#define TSL2591_PERSIST_3 0x03 +#define TSL2591_PERSIST_5 0x04 +#define TSL2591_PERSIST_10 0x05 +#define TSL2591_PERSIST_15 0x06 +#define TSL2591_PERSIST_20 0x07 +#define TSL2591_PERSIST_25 0x08 +#define TSL2591_PERSIST_30 0x09 +#define TSL2591_PERSIST_35 0x0A +#define TSL2591_PERSIST_40 0x0B +#define TSL2591_PERSIST_45 0x0C +#define TSL2591_PERSIST_50 0x0D +#define TSL2591_PERSIST_55 0x0E +#define TSL2591_PERSIST_60 0x0F + +/* Device factor coefficient for lux calculations */ +#define TSL2591_LUX_DF 408 + +/* Max integration time (in ms) for single step */ +#define TSL2591_MAX_TIME_STEP 105 + +/* Max ADC Counts */ +#define TSL2591_MAX_ADC 65535 +#define TSL2591_MAX_ADC_100 36863 + +struct tsl2591_config { + const struct i2c_dt_spec i2c; +#ifdef CONFIG_TSL2591_TRIGGER + const struct gpio_dt_spec int_gpio; +#endif +}; + +struct tsl2591_data { + uint16_t vis_count; + uint16_t ir_count; + uint16_t again; + uint16_t atime; + bool powered_on; + +#ifdef CONFIG_TSL2591_TRIGGER + const struct device *dev; + struct gpio_callback gpio_cb; + sensor_trigger_handler_t th_handler; + const struct sensor_trigger *th_trigger; + +#if defined(CONFIG_TSL2591_TRIGGER_OWN_THREAD) + K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_TSL2591_THREAD_STACK_SIZE); + struct k_sem trig_sem; + struct k_thread thread; +#elif defined(CONFIG_TSL2591_TRIGGER_GLOBAL_THREAD) + struct k_work work; +#endif + +#endif +}; + +int tsl2591_reg_update(const struct device *dev, uint8_t reg, uint8_t mask, uint8_t val); + +#ifdef CONFIG_TSL2591_TRIGGER +int tsl2591_trigger_set(const struct device *dev, const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); +int tsl2591_initialize_int(const struct device *dev); +#endif + +#endif /* ZEPHYR_DRIVERS_SENSOR_TSL2591_TSL2591_H_ */ diff --git a/drivers/sensor/tsl2591/tsl2591_trigger.c b/drivers/sensor/tsl2591/tsl2591_trigger.c new file mode 100644 index 00000000000..ea0e34d3f81 --- /dev/null +++ b/drivers/sensor/tsl2591/tsl2591_trigger.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2023 Kurtis Dinelle + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "tsl2591.h" + +LOG_MODULE_DECLARE(TSL2591, CONFIG_SENSOR_LOG_LEVEL); + +static inline void tsl2591_setup_int(const struct device *dev, bool enable) +{ + const struct tsl2591_config *config = dev->config; + gpio_flags_t flags = enable ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE; + + gpio_pin_interrupt_configure_dt(&config->int_gpio, flags); +} + +static void tsl2591_gpio_callback(const struct device *dev, struct gpio_callback *cb, uint32_t pins) +{ + ARG_UNUSED(dev); + ARG_UNUSED(pins); + + struct tsl2591_data *data = CONTAINER_OF(cb, struct tsl2591_data, gpio_cb); + + tsl2591_setup_int(data->dev, false); + +#if defined(CONFIG_TSL2591_TRIGGER_OWN_THREAD) + k_sem_give(&data->trig_sem); +#elif defined(CONFIG_TSL2591_TRIGGER_GLOBAL_THREAD) + k_work_submit(&data->work); +#endif +} + +static void tsl2591_handle_int(const struct device *dev) +{ + struct tsl2591_data *data = dev->data; + const struct tsl2591_config *config = dev->config; + uint8_t clear_cmd; + int ret; + + /* Interrupt must be cleared manually */ + clear_cmd = TSL2591_CLEAR_INT_CMD; + ret = i2c_write_dt(&config->i2c, &clear_cmd, 1U); + if (ret < 0) { + LOG_ERR("Failed to clear interrupt"); + return; + } + + if (data->th_handler != NULL) { + data->th_handler(dev, data->th_trigger); + } + + tsl2591_setup_int(dev, true); +} + +#ifdef CONFIG_TSL2591_TRIGGER_OWN_THREAD +static void tsl2591_thread(void *p1, void *p2, void *p3) +{ + ARG_UNUSED(p2); + ARG_UNUSED(p3); + + struct tsl2591_data *data = p1; + + while (1) { + k_sem_take(&data->trig_sem, K_FOREVER); + tsl2591_handle_int(data->dev); + } +} +#endif + +#ifdef CONFIG_TSL2591_TRIGGER_GLOBAL_THREAD +static void tsl2591_work_handler(struct k_work *work) +{ + struct tsl2591_data *data = CONTAINER_OF(work, struct tsl2591_data, work); + + tsl2591_handle_int(data->dev); +} +#endif + +int tsl2591_trigger_set(const struct device *dev, const struct sensor_trigger *trig, + sensor_trigger_handler_t handler) +{ + struct tsl2591_data *data = dev->data; + const struct tsl2591_config *config = dev->config; + int ret; + + if (!config->int_gpio.port) { + return -ENOTSUP; + } + + if (trig->chan != SENSOR_CHAN_LIGHT) { + LOG_ERR("Unsupported sensor trigger channel"); + return -ENOTSUP; + } + + if (trig->type != SENSOR_TRIG_THRESHOLD) { + LOG_ERR("Unsupported sensor trigger type"); + return -ENOTSUP; + } + + data->th_handler = handler; + data->th_trigger = trig; + tsl2591_setup_int(dev, true); + + ret = tsl2591_reg_update(dev, TSL2591_REG_ENABLE, TSL2591_AIEN_MASK, TSL2591_AIEN_ON); + if (ret < 0) { + LOG_ERR("Failed to enable interrupt on sensor"); + } + + return ret; +} + +int tsl2591_initialize_int(const struct device *dev) +{ + struct tsl2591_data *data = dev->data; + const struct tsl2591_config *config = dev->config; + int ret; + + if (!gpio_is_ready_dt(&config->int_gpio)) { + LOG_ERR("%s: gpio controller %s not ready", dev->name, config->int_gpio.port->name); + return -ENODEV; + } + + ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT | config->int_gpio.dt_flags); + if (ret < 0) { + LOG_ERR("Failed to configure gpio pin for input"); + return ret; + } + + gpio_init_callback(&data->gpio_cb, tsl2591_gpio_callback, BIT(config->int_gpio.pin)); + + ret = gpio_add_callback(config->int_gpio.port, &data->gpio_cb); + if (ret < 0) { + LOG_DBG("Failed to set gpio callback"); + return ret; + } + + data->dev = dev; + +#if defined(CONFIG_TSL2591_TRIGGER_OWN_THREAD) + ret = k_sem_init(&data->trig_sem, 0, K_SEM_MAX_LIMIT); + if (ret < 0) { + LOG_ERR("Failed to initialize trigger semaphore"); + return ret; + } + + k_thread_create(&data->thread, data->thread_stack, CONFIG_TSL2591_THREAD_STACK_SIZE, + tsl2591_thread, data, NULL, NULL, + K_PRIO_COOP(CONFIG_TSL2591_THREAD_PRIORITY), 0, K_NO_WAIT); +#elif defined(CONFIG_TSL2591_TRIGGER_GLOBAL_THREAD) + data->work.handler = tsl2591_work_handler; +#endif + + return 0; +} diff --git a/dts/bindings/sensor/ams,tsl2591.yaml b/dts/bindings/sensor/ams,tsl2591.yaml new file mode 100644 index 00000000000..6d4f71d881e --- /dev/null +++ b/dts/bindings/sensor/ams,tsl2591.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2023 Kurtis Dinelle +# SPDX-License-Identifier: Apache-2.0 + +description: | + OSRAM ams TSL2591 ambient light sensor. + +compatible: "ams,tsl2591" + +include: [sensor-device.yaml, i2c-device.yaml] + +properties: + int-gpios: + type: phandle-array + description: | + The interrupt pin of the TSL2591 is open-drain, active low. + If connected directly, the MCU pin should be configured + as pull-up, active low. diff --git a/include/zephyr/drivers/sensor/tsl2591.h b/include/zephyr/drivers/sensor/tsl2591.h new file mode 100644 index 00000000000..b8685ff464d --- /dev/null +++ b/include/zephyr/drivers/sensor/tsl2591.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2023 Kurtis Dinelle + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Extended public API for AMS's TSL2591 ambient light sensor + * + * This exposes attributes for the TSL2591 which can be used for + * setting the on-chip gain, integration time, and persist filter parameters. + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_TSL2591_H_ +#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TSL2591_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum sensor_attribute_tsl2591 { + /* Sensor ADC Gain Mode + * Rather than set this value directly, can only be set to operate in one of four modes: + * + * TSL2591_SENSOR_GAIN_LOW + * TSL2591_SENSOR_GAIN_MED + * TSL2591_SENSOR_GAIN_HIGH + * TSL2591_SENSOR_GAIN_MAX + * + * See datasheet for actual typical gain scales these modes correspond to. + */ + SENSOR_ATTR_GAIN_MODE = SENSOR_ATTR_PRIV_START + 1, + + /* Sensor ADC Integration Time (in ms) + * Can only be set to one of six values: + * + * 100, 200, 300, 400, 500, or 600 + */ + SENSOR_ATTR_INTEGRATION_TIME, + + /* Sensor ALS Interrupt Persist Filter + * Represents the number of consecutive sensor readings outside of a set threshold + * before triggering an interrupt. Can only be set to one of sixteen values: + * + * 0, 1, 2, 3, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, or 60 + * + * Setting this to 0 causes an interrupt to generate every ALS cycle, + * regardless of threshold. + * Setting this to 1 is equivalent to the no-persist interrupt mode. + */ + SENSOR_ATTR_INT_PERSIST +}; + +enum sensor_gain_tsl2591 { + TSL2591_SENSOR_GAIN_LOW, + TSL2591_SENSOR_GAIN_MED, + TSL2591_SENSOR_GAIN_HIGH, + TSL2591_SENSOR_GAIN_MAX +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_TSL2591_H_ */ diff --git a/tests/drivers/build_all/sensor/i2c.dtsi b/tests/drivers/build_all/sensor/i2c.dtsi index 88826c9d0a1..a949cc1b289 100644 --- a/tests/drivers/build_all/sensor/i2c.dtsi +++ b/tests/drivers/build_all/sensor/i2c.dtsi @@ -932,3 +932,9 @@ test_i2c_ens160: ens160@83 { reg = <0x83>; int-gpios = <&test_gpio 0 0>; }; + +test_i2c_tsl2591: tsl2591@84 { + compatible = "ams,tsl2591"; + reg = <0x84>; + int-gpios = <&test_gpio 0 0>; +}; diff --git a/tests/drivers/build_all/sensor/sensors_trigger_global.conf b/tests/drivers/build_all/sensor/sensors_trigger_global.conf index b888b0541fc..75d24e13857 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_global.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_global.conf @@ -57,6 +57,7 @@ CONFIG_TMAG5170_TRIGGER_GLOBAL_THREAD=y CONFIG_TMD2620_TRIGGER_GLOBAL_THREAD=y CONFIG_TMP007_TRIGGER_GLOBAL_THREAD=y CONFIG_TSL2540_TRIGGER_GLOBAL_THREAD=y +CONFIG_TSL2591_TRIGGER_GLOBAL_THREAD=y CONFIG_VCNL4040_TRIGGER_GLOBAL_THREAD=y CONFIG_WSEN_HIDS_TRIGGER_GLOBAL_THREAD=y CONFIG_WSEN_TIDS_TRIGGER_GLOBAL_THREAD=y diff --git a/tests/drivers/build_all/sensor/sensors_trigger_none.conf b/tests/drivers/build_all/sensor/sensors_trigger_none.conf index a1e0692a8a1..665975a0d62 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_none.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_none.conf @@ -57,6 +57,7 @@ CONFIG_TMAG5170_TRIGGER_NONE=y CONFIG_TMD2620_TRIGGER_NONE=y CONFIG_TMP007_TRIGGER_NONE=y CONFIG_TSL2540_TRIGGER_NONE=y +CONFIG_TSL2591_TRIGGER_NONE=y CONFIG_VCNL4040_TRIGGER_NONE=y CONFIG_WSEN_HIDS_TRIGGER_NONE=y CONFIG_WSEN_TIDS_TRIGGER_NONE=y diff --git a/tests/drivers/build_all/sensor/sensors_trigger_own.conf b/tests/drivers/build_all/sensor/sensors_trigger_own.conf index 9d965e00cbc..71aed7dfaab 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_own.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_own.conf @@ -55,6 +55,7 @@ CONFIG_TCN75A_TRIGGER_OWN_THREAD=y CONFIG_TMAG5170_TRIGGER_OWN_THREAD=y CONFIG_TMP007_TRIGGER_OWN_THREAD=y CONFIG_TSL2540_TRIGGER_OWN_THREAD=y +CONFIG_TSL2591_TRIGGER_OWN_THREAD=y CONFIG_VCNL4040_TRIGGER_OWN_THREAD=y CONFIG_WSEN_HIDS_TRIGGER_OWN_THREAD=y CONFIG_WSEN_TIDS_TRIGGER_OWN_THREAD=y From 6057a830602fcab7f1b8206be5c4ee3102763e4e Mon Sep 17 00:00:00 2001 From: Jun Lin Date: Wed, 7 Feb 2024 11:30:58 +0800 Subject: [PATCH 0670/2402] drivers: entropy: npcx: add rng driver support This commit add the rng driver support by using the npcx drgb API. Signed-off-by: Jun Lin --- drivers/crypto/crypto_npcx_sha.c | 20 +- drivers/entropy/CMakeLists.txt | 1 + drivers/entropy/Kconfig | 1 + drivers/entropy/Kconfig.npcx | 59 ++++++ drivers/entropy/entropy_npcx_drbg.c | 234 ++++++++++++++++++++++++ dts/arm/nuvoton/npcx9mfp.dtsi | 13 ++ dts/bindings/rng/nuvoton,npcx-drbg.yaml | 19 ++ soc/nuvoton/npcx/common/soc_ncl.h | 56 ++++++ 8 files changed, 385 insertions(+), 18 deletions(-) create mode 100644 drivers/entropy/Kconfig.npcx create mode 100644 drivers/entropy/entropy_npcx_drbg.c create mode 100644 dts/bindings/rng/nuvoton,npcx-drbg.yaml create mode 100644 soc/nuvoton/npcx/common/soc_ncl.h diff --git a/drivers/crypto/crypto_npcx_sha.c b/drivers/crypto/crypto_npcx_sha.c index 7354ea5877b..8aa30846ae2 100644 --- a/drivers/crypto/crypto_npcx_sha.c +++ b/drivers/crypto/crypto_npcx_sha.c @@ -13,28 +13,12 @@ #include LOG_MODULE_REGISTER(sha_npcx, CONFIG_CRYPTO_LOG_LEVEL); +#include "soc_ncl.h" + #define NPCX_HASH_CAPS_SUPPORT (CAP_SEPARATE_IO_BUFS | CAP_SYNC_OPS) #define NPCX_SHA256_HANDLE_SIZE DT_INST_PROP(0, context_buffer_size) #define NPCX_SHA_MAX_SESSION 1 -/* The status code returns from Nuvoton Cryptographic Library ROM APIs */ -enum ncl_status { - NCL_STATUS_OK = 0xA5A5, - NCL_STATUS_FAIL = 0x5A5A, - NCL_STATUS_INVALID_PARAM = 0x02, - NCL_STATUS_PARAM_NOT_SUPPORTED, - NCL_STATUS_SYSTEM_BUSY, - NCL_STATUS_AUTHENTICATION_FAIL, - NCL_STATUS_NO_RESPONSE, - NCL_STATUS_HARDWARE_ERROR, -}; -enum ncl_sha_type { - NCL_SHA_TYPE_2_256 = 0, - NCL_SHA_TYPE_2_384 = 1, - NCL_SHA_TYPE_2_512 = 2, - NCL_SHA_TYPE_NUM -}; - /* The following table holds the function pointer for each SHA API in NPCX ROM. */ struct npcx_ncl_sha { /* Get the SHA context size required by SHA APIs. */ diff --git a/drivers/entropy/CMakeLists.txt b/drivers/entropy/CMakeLists.txt index 11e361517c2..02a32ed252a 100644 --- a/drivers/entropy/CMakeLists.txt +++ b/drivers/entropy/CMakeLists.txt @@ -33,6 +33,7 @@ zephyr_library_sources_ifdef(CONFIG_ENTROPY_NEORV32_TRNG entropy_neorv32_t zephyr_library_sources_ifdef(CONFIG_ENTROPY_BT_HCI entropy_bt_hci.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_SE entropy_gecko_se.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_PSA_CRYPTO_RNG entropy_psa_crypto.c) +zephyr_library_sources_ifdef(CONFIG_ENTROPY_NPCX_DRBG entropy_npcx_drbg.c) if (CONFIG_BUILD_WITH_TFM) target_include_directories(${ZEPHYR_CURRENT_LIBRARY} PRIVATE diff --git a/drivers/entropy/Kconfig b/drivers/entropy/Kconfig index e932f62c6bf..34c020256bf 100644 --- a/drivers/entropy/Kconfig +++ b/drivers/entropy/Kconfig @@ -35,6 +35,7 @@ source "drivers/entropy/Kconfig.gecko" source "drivers/entropy/Kconfig.neorv32" source "drivers/entropy/Kconfig.bt_hci" source "drivers/entropy/Kconfig.psa_crypto" +source "drivers/entropy/Kconfig.npcx" config ENTROPY_HAS_DRIVER bool diff --git a/drivers/entropy/Kconfig.npcx b/drivers/entropy/Kconfig.npcx new file mode 100644 index 00000000000..fd4c91d82d9 --- /dev/null +++ b/drivers/entropy/Kconfig.npcx @@ -0,0 +1,59 @@ +# NPCX DRBG driver configuration options + +# Copyright (c) 2024 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +menuconfig ENTROPY_NPCX_DRBG + bool "NPCX DRBG driver" + default y + depends on DT_HAS_NUVOTON_NPCX_DRBG_ENABLED && SOC_NPCX9MFP + select ENTROPY_HAS_DRIVER + help + This option enables the deterministic random bit generator (DRBG) + driver for NPCX family of processors. + +if ENTROPY_NPCX_DRBG + +choice + prompt "DRBG Security Strength Selection" + default ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_128B + help + The chosen security strength defines the amount of entropy bits + generated internally and passed to the conditioning component. + +config ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_112B + bool "DRBG security strength 112 bits" + +config ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_128B + bool "DRBG security strength 128 bits" + +config ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_192B + bool "DRBG security strength 192 bits" + +config ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_256B + bool "DRBG security strength 256 bits" + +config ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_128B_TEST + bool "DRBG security strength 12b bits test" + +config ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_256B_TEST + bool "DRBG security strength 256 bits test" + +endchoice + +config ENTROPY_NPCX_DRBG_SECURITY_STRENGTH + int + default 0 if ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_112B + default 1 if ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_128B + default 2 if ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_192B + default 3 if ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_256B + default 4 if ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_128B_TEST + default 5 if ENTROPY_NPCX_DRBG_SECURITY_STRENGTH_256B_TEST + +config ENTROPY_NPCX_DRBG_RESEED_INTERVAL + int "DRBG Reseed Interval" + default 100 + help + Number of gererations allowed until next reseeding. + +endif diff --git a/drivers/entropy/entropy_npcx_drbg.c b/drivers/entropy/entropy_npcx_drbg.c new file mode 100644 index 00000000000..d00ee532d00 --- /dev/null +++ b/drivers/entropy/entropy_npcx_drbg.c @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nuvoton_npcx_drbg + +#include +#include +#include +#include + +#include +LOG_MODULE_REGISTER(entropy_npcx_drbg, CONFIG_ENTROPY_LOG_LEVEL); + +#include "soc_ncl.h" + +/* Reseed after 100 number generations */ +#define NPCX_DRBG_SECURITY_STRENGTH \ + ((enum ncl_drbg_security_strength)CONFIG_ENTROPY_NPCX_DRBG_SECURITY_STRENGTH) +#define NPCX_DRBG_RESEED_INTERVAL CONFIG_ENTROPY_NPCX_DRBG_RESEED_INTERVAL + +#define NPCX_DRBG_HANDLE_SIZE DT_INST_PROP(0, context_buffer_size) +struct entropy_npcx_drbg_dev_data { + struct k_sem sem_lock; + uint8_t handle[NPCX_DRBG_HANDLE_SIZE] __aligned(4); +}; + +/* + * The base address of the table that holds the function pointer for each + * DRBG API in ROM. + */ +#define NPCX_NCL_DRBG_BASE_ADDR ((const struct npcx_ncl_drbg *)DT_INST_REG_ADDR_BY_IDX(0, 0)) +/* The following table holds the function pointer for each DRBG API in NPCX ROM. */ +struct npcx_ncl_drbg { + /* Get the DRBG context size required by DRBG APIs. */ + uint32_t (*get_context_size)(void); + /* Initialize DRBG context. */ + enum ncl_status (*init_context)(void *ctx); + /* Power on/off DRBG module. */ + enum ncl_status (*power)(void *ctx, uint8_t enable); + /* Finalize DRBG context. */ + enum ncl_status (*finalize_context)(void *ctx); + /* Initialize the DRBG hardware module and enable interrupts. */ + enum ncl_status (*init)(void *ctx, bool int_enable); + /* + * Configure DRBG, pres_resistance enables/disables (1/0) prediction + * resistance + */ + enum ncl_status (*config)(void *ctx, uint32_t reseed_interval, uint8_t pred_resistance); + /* + * This routine creates a first instantiation of the DRBG mechanism + * parameters. The routine pulls an initial seed from the HW RNG module + * and resets the reseed counter. DRBG and SHA modules should be + * activated prior to the this operation. + */ + enum ncl_status (*instantiate)(void *ctx, enum ncl_drbg_security_strength sec_strength, + const uint8_t *pers_string, uint32_t pers_string_len); + /* Uninstantiate DRBG module */ + enum ncl_status (*uninstantiate)(void *ctx); + /* Reseeds the internal state of the given instantce */ + enum ncl_status (*reseed)(void *ctc, uint8_t *add_data, uint32_t add_data_len); + /* Generates a random number from the current internal state. */ + enum ncl_status (*generate)(void *ctx, const uint8_t *add_data, uint32_t add_data_len, + uint8_t *out_buff, uint32_t out_buff_len); + /* Clear all DRBG SSPs (Sensitive Security Parameters) in HW & driver */ + enum ncl_status (*clear)(void *ctx); +}; +#define NPCX_NCL_DRBG ((const struct npcx_ncl_drbg *)NPCX_NCL_DRBG_BASE_ADDR) + +/* The 2nd index of the reg property holds the address of NCL_SHA_Power ROM API */ +#define NPCX_NCL_SHA_POWER_ADDR ((const struct npcx_ncl_drbg *)DT_INST_REG_ADDR_BY_IDX(0, 1)) +struct npcx_ncl_sha { + /* Power on/off SHA module. */ + enum ncl_status (*power)(void *ctx, uint8_t on); +}; +#define NPCX_NCL_SHA_POWER ((const struct npcx_ncl_sha *)NPCX_NCL_SHA_POWER_ADDR) + +static int entropy_npcx_drbg_enable_sha_power(void *ctx, bool enable) +{ + enum ncl_status ncl_ret; + + ncl_ret = NPCX_NCL_SHA_POWER->power(ctx, enable); + if (ncl_ret != NCL_STATUS_OK) { + LOG_ERR("Fail to %s SHA power: err 0x%02x", enable ? "enable" : "disable", ncl_ret); + return -EIO; + } + + return 0; +} + +static int entropy_npcx_drbg_enable_drbg_power(void *ctx, bool enable) +{ + enum ncl_status ncl_ret; + + ncl_ret = NPCX_NCL_DRBG->power(ctx, enable); + if (ncl_ret != NCL_STATUS_OK) { + LOG_ERR("Fail to %s DRBG power: err 0x%02x", enable ? "enable" : "disable", + ncl_ret); + return -EIO; + } + + return 0; +} + +static int entropy_npcx_drbg_get_entropy(const struct device *dev, uint8_t *buf, uint16_t len) +{ + struct entropy_npcx_drbg_dev_data *const data = dev->data; + enum ncl_status ncl_ret; + void *ctx = data->handle; + int ret = 0; + + k_sem_take(&data->sem_lock, K_FOREVER); + + ret = entropy_npcx_drbg_enable_sha_power(ctx, true); + if (ret != 0) { + goto err_exit; + } + + ncl_ret = NPCX_NCL_DRBG->generate(ctx, NULL, 0, buf, len); + if (ncl_ret != NCL_STATUS_OK) { + LOG_ERR("Fail to generate: err 0x%02x", ncl_ret); + ret = -EIO; + goto err_exit; + } + + ret = entropy_npcx_drbg_enable_sha_power(ctx, false); + +err_exit: + k_sem_give(&data->sem_lock); + + return ret; +} + +static int entropy_npcx_drbg_init(const struct device *dev) +{ + struct entropy_npcx_drbg_dev_data *const data = dev->data; + uint32_t handle_size_required; + enum ncl_status ncl_ret; + void *ctx = data->handle; + int ret; + + handle_size_required = NPCX_NCL_DRBG->get_context_size(); + if (handle_size_required != NPCX_DRBG_HANDLE_SIZE) { + LOG_ERR("Unexpected NCL DRBG context_size = %d", handle_size_required); + return -ENOSR; + } + + ret = entropy_npcx_drbg_enable_sha_power(ctx, true); + if (ret != 0) { + return ret; + } + + ret = entropy_npcx_drbg_enable_drbg_power(ctx, true); + if (ret != 0) { + return ret; + } + + ncl_ret = NPCX_NCL_DRBG->init_context(ctx); + if (ncl_ret != NCL_STATUS_OK) { + LOG_ERR("Fail to init ctx: err 0x%02x", ncl_ret); + return -EIO; + } + + ncl_ret = NPCX_NCL_DRBG->init(ctx, false); + if (ncl_ret != NCL_STATUS_OK) { + LOG_ERR("Fail to init: err 0x%02x", ncl_ret); + return -EIO; + } + + ncl_ret = NPCX_NCL_DRBG->config(ctx, NPCX_DRBG_RESEED_INTERVAL, false); + if (ncl_ret != NCL_STATUS_OK) { + LOG_ERR("Fail to config: err 0x%02x", ncl_ret); + return -EIO; + } + + ncl_ret = NPCX_NCL_DRBG->instantiate(ctx, NPCX_DRBG_SECURITY_STRENGTH, NULL, 0); + if (ncl_ret != NCL_STATUS_OK) { + LOG_ERR("Fail to config: err 0x%02x", ncl_ret); + return -EIO; + } + + ret = entropy_npcx_drbg_enable_sha_power(ctx, false); + if (ret != 0) { + return ret; + } + + /* Locking semaphore initialized to 1 (unlocked) */ + k_sem_init(&data->sem_lock, 1, 1); + + return 0; +} + +#ifdef CONFIG_PM_DEVICE +static int entropy_npcx_drbg_suspend(const struct device *dev) +{ + struct entropy_npcx_drbg_dev_data *const data = dev->data; + void *ctx = data->handle; + + return entropy_npcx_drbg_enable_drbg_power(ctx, false); +} + +static int entropy_npcx_drbg_resume(const struct device *dev) +{ + struct entropy_npcx_drbg_dev_data *const data = dev->data; + void *ctx = data->handle; + + return entropy_npcx_drbg_enable_drbg_power(ctx, true); +} + +static int entropy_npcx_drbg_pm_action(const struct device *dev, enum pm_device_action action) +{ + switch (action) { + case PM_DEVICE_ACTION_SUSPEND: + return entropy_npcx_drbg_suspend(dev); + case PM_DEVICE_ACTION_RESUME: + return entropy_npcx_drbg_resume(dev); + default: + return -ENOTSUP; + } +} +#endif /* CONFIG_PM_DEVICE */ + +static const struct entropy_driver_api entropy_npcx_drbg_api = { + .get_entropy = entropy_npcx_drbg_get_entropy, +}; + +static struct entropy_npcx_drbg_dev_data entropy_npcx_drbg_data; + +PM_DEVICE_DT_INST_DEFINE(0, entropy_npcx_drbg_pm_action); + +DEVICE_DT_INST_DEFINE(0, entropy_npcx_drbg_init, PM_DEVICE_DT_INST_GET(0), &entropy_npcx_drbg_data, + NULL, PRE_KERNEL_1, CONFIG_ENTROPY_INIT_PRIORITY, &entropy_npcx_drbg_api); diff --git a/dts/arm/nuvoton/npcx9mfp.dtsi b/dts/arm/nuvoton/npcx9mfp.dtsi index fb646513f43..ea605873eb5 100644 --- a/dts/arm/nuvoton/npcx9mfp.dtsi +++ b/dts/arm/nuvoton/npcx9mfp.dtsi @@ -8,6 +8,10 @@ #include "npcx/npcx9.dtsi" / { + chosen { + zephyr,entropy = &drbg0; + }; + flash0: flash@10058000 { reg = <0x10058000 DT_SIZE_K(416)>; }; @@ -27,6 +31,15 @@ reg = <0x200D7000 DT_SIZE_K(4)>; }; + soc { + drbg0: drbg@110 { + compatible = "nuvoton,npcx-drbg"; + reg = <0x110 0x2c 0x15c 0x04>; + context-buffer-size = <240>; + status = "disabled"; + }; + }; + soc-id { device-id = <0x2b>; }; diff --git a/dts/bindings/rng/nuvoton,npcx-drbg.yaml b/dts/bindings/rng/nuvoton,npcx-drbg.yaml new file mode 100644 index 00000000000..462d743ad85 --- /dev/null +++ b/dts/bindings/rng/nuvoton,npcx-drbg.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +description: NPCX Deterministic Random Bit Generator + +compatible: "nuvoton,npcx-drbg" + +include: base.yaml + +properties: + reg: + required: true + + context-buffer-size: + type: int + required: true + description: | + Size of the pre-allocated buffer for the DRBG ROM API to store the + intermediate/final computation result. diff --git a/soc/nuvoton/npcx/common/soc_ncl.h b/soc/nuvoton/npcx/common/soc_ncl.h new file mode 100644 index 00000000000..dcdbe19fd9b --- /dev/null +++ b/soc/nuvoton/npcx/common/soc_ncl.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _NUVOTON_NPCX_SOC_NCL_H_ +#define _NUVOTON_NPCX_SOC_NCL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* The status code returns from Nuvoton Cryptographic Library ROM APIs */ +enum ncl_status { + NCL_STATUS_OK = 0xA5A5, + NCL_STATUS_FAIL = 0x5A5A, + NCL_STATUS_INVALID_PARAM = 0x02, + NCL_STATUS_PARAM_NOT_SUPPORTED = 0x03, + NCL_STATUS_SYSTEM_BUSY = 0x04, + NCL_STATUS_AUTHENTICATION_FAIL = 0x05, + NCL_STATUS_NO_RESPONSE = 0x06, + NCL_STATUS_HARDWARE_ERROR = 0x07 +}; + +enum ncl_sha_type { + NCL_SHA_TYPE_2_256 = 0, + NCL_SHA_TYPE_2_384 = 1, + NCL_SHA_TYPE_2_512 = 2, + NCL_SHA_TYPE_NUM +}; + +/* + * This enum defines the security strengths supported by this DRBG mechanism. + * The internally generated entropy and nonce sizes are derived from these + * values. The supported actual sizes: + * Security strength (bits) 112 128 192 256 128_Test 256_Test + * + * Entropy size (Bytes) 32 48 64 96 111 128 + * Nonce size (Bytes) 16 16 24 32 16 0 + */ +enum ncl_drbg_security_strength { + NCL_DRBG_SECURITY_STRENGTH_112B = 0, + NCL_DRBG_SECURITY_STRENGTH_128B, + NCL_DRBG_SECURITY_STRENGTH_192B, + NCL_DRBG_SECURITY_STRENGTH_256B, + NCL_DRBG_SECURITY_STRENGTH_128B_TEST, + NCL_DRBG_SECURITY_STRENGTH_256B_TEST, + NCL_DRBG_MAX_SECURITY_STRENGTH +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _NUVOTON_NPCX_SOC_NCL_H_ */ From 6c6495bb43b68e34801060536cb27dc560d0adc3 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Tue, 27 Feb 2024 06:09:30 +0000 Subject: [PATCH 0671/2402] xtensa: mmu: Fix rasid initial value RASID must not use 0 for any slot. According with documentation: """The operation of the processor is undefined if any two of the four ASIDs are equal or if it contains an ASID of zero""" Signed-off-by: Flavio Ceolin --- arch/xtensa/core/mmu.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/xtensa/core/mmu.c b/arch/xtensa/core/mmu.c index 576b185a099..c1073ac0247 100644 --- a/arch/xtensa/core/mmu.c +++ b/arch/xtensa/core/mmu.c @@ -125,6 +125,16 @@ void xtensa_init_paging(uint32_t *l1_page) { extern char z_xt_init_pc; /* defined in asm below */ struct tlb_regs regs; + unsigned int initial_rasid; + + /* The initial rasid after hardware initialization is 0x04030201. + * 1 is hardwired to ring 0, other slots must be different + * from each other and must not be 0. + * + * For our initial implementation we just set the 4th slot (ring 3), + * to use the ASID value used for memory that is shared with all threads. + */ + initial_rasid = 0xff030201; #if CONFIG_MP_MAX_NUM_CPUS > 1 /* The incoherent cache can get into terrible trouble if it's @@ -161,7 +171,7 @@ void xtensa_init_paging(uint32_t *l1_page) "isync\n" "iitlb %8\n" /* invalidate pc */ "isync\n" /* <--- traps a ITLB miss */ - :: "r"(regs.ptevaddr), "r"(regs.rasid), + :: "r"(regs.ptevaddr), "r"(initial_rasid), "r"(regs.ptepin_at), "r"(regs.ptepin_as), "r"(regs.vecpin_at), "r"(regs.vecpin_as), "r"(idtlb_pte), "r"(idtlb_stk), "r"(iitlb_pc)); From 5cac834bb65113bb93e9a5546bf75732c36f1ddb Mon Sep 17 00:00:00 2001 From: Bjarki Arge Andreasen Date: Tue, 12 Mar 2024 16:48:18 +0100 Subject: [PATCH 0672/2402] llext: arch_elf_relocate: pass opval unmodified The opval argument of arch_elf_relocate() was modified by adding the value stored at opaddr before passing it to arch_elf_relocate(). This presumed that the addend would always be stored as a raw value at opaddr, which is not the case for all relocation types. This PR modifies opval to be the absolute address of opval, and moves the addition of the addend from llext_link_plt() to the implementation of arch_elf_relocate(). Signed-off-by: Bjarki Arge Andreasen --- arch/arm/core/elf.c | 3 +++ subsys/llext/llext.c | 5 ++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/core/elf.c b/arch/arm/core/elf.c index e16af6199e6..d68b59501f5 100644 --- a/arch/arm/core/elf.c +++ b/arch/arm/core/elf.c @@ -26,6 +26,9 @@ void arch_elf_relocate(elf_rela_t *rel, uintptr_t opaddr, uintptr_t opval) switch (reloc_type) { case R_ARM_ABS32: + /* Add the addend stored at opaddr to opval */ + opval += *((uint32_t *)opaddr); + /* Update the absolute address of a load/store instruction */ *((uint32_t *)opaddr) = (uint32_t)opval; break; diff --git a/subsys/llext/llext.c b/subsys/llext/llext.c index a6ed1e4ac86..9af133d6757 100644 --- a/subsys/llext/llext.c +++ b/subsys/llext/llext.c @@ -769,10 +769,9 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local } } else if (ELF_ST_TYPE(sym.st_info) == STT_SECTION || ELF_ST_TYPE(sym.st_info) == STT_FUNC) { - /* Current relocation location holds an offset into the section */ + /* Link address is relative to the start of the section */ link_addr = (uintptr_t)ext->mem[ldr->sect_map[sym.st_shndx]] - + sym.st_value - + *((uintptr_t *)op_loc); + + sym.st_value; LOG_INF("found section symbol %s addr 0x%lx", name, link_addr); } else { From 9b583cc539e337ca95ef91a1458389ec0d1fa94f Mon Sep 17 00:00:00 2001 From: Bjarki Arge Andreasen Date: Tue, 12 Mar 2024 14:13:53 +0100 Subject: [PATCH 0673/2402] llext: arm: Add R_ARM_ARM_THM_CALL reloc support Add support for the relocation type R_ARM_ARM_THM_CALL which is produced for the ARM Thumb BL and BLX (branch immediate) instructions. These instructions are used for non-static functions like void test1(void) { } void main(void) { test1(); } Without support for this relocation, test1() has to be static. Signed-off-by: Bjarki Arge Andreasen --- arch/arm/core/elf.c | 49 ++++++++++++++++++++++++++++++++++++++ include/zephyr/llext/elf.h | 1 + 2 files changed, 50 insertions(+) diff --git a/arch/arm/core/elf.c b/arch/arm/core/elf.c index d68b59501f5..e3c137e49f2 100644 --- a/arch/arm/core/elf.c +++ b/arch/arm/core/elf.c @@ -7,9 +7,48 @@ #include #include #include +#include LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL); +#define ARM_BL_BLX_UPPER_S_BIT BIT(10) +#define ARM_BL_BLX_ADDEND_OFFSET 0 +#define ARM_BL_BLX_ADDEND_SIZE 11 +#define ARM_BL_BLX_ADDEND_MASK 0x7FF +#define ARM_BL_BLX_HDR_MASK 0xF800 +#define ARM_BL_BLX_LOWER_T1T2_BIT BIT(12) + +static int32_t arm_bl_blx_decode_addend(uintptr_t opaddr) +{ + uint16_t upper = *((uint16_t *)opaddr); + uint16_t lower = *(((uint16_t *)opaddr) + 1); + + int32_t addend = upper & ARM_BL_BLX_UPPER_S_BIT ? UINT32_MAX : 0; + + addend <<= ARM_BL_BLX_ADDEND_SIZE; + addend |= upper & ARM_BL_BLX_ADDEND_MASK; + addend <<= ARM_BL_BLX_ADDEND_SIZE; + addend |= lower & ARM_BL_BLX_ADDEND_MASK; + + return lower & ARM_BL_BLX_LOWER_T1T2_BIT ? addend << 1 : addend << 2; +} + +static void arm_bl_blx_encode_addend(uintptr_t opaddr, int32_t addend) +{ + uint16_t upper = *((uint16_t *)opaddr); + uint16_t lower = *(((uint16_t *)opaddr) + 1); + + addend = upper & ARM_BL_BLX_UPPER_S_BIT ? addend >> 1 : addend >> 2; + + upper &= ARM_BL_BLX_HDR_MASK; + lower &= ARM_BL_BLX_HDR_MASK; + upper |= (addend >> ARM_BL_BLX_ADDEND_SIZE) & ARM_BL_BLX_ADDEND_MASK; + lower |= addend & ARM_BL_BLX_ADDEND_MASK; + + *((uint16_t *)opaddr) = upper; + *(((uint16_t *)opaddr) + 1) = lower; +} + /** * @brief Architecture specific function for relocating partially linked (static) elf * @@ -32,6 +71,16 @@ void arch_elf_relocate(elf_rela_t *rel, uintptr_t opaddr, uintptr_t opval) /* Update the absolute address of a load/store instruction */ *((uint32_t *)opaddr) = (uint32_t)opval; break; + case R_ARM_THM_CALL: + /* Decode the initial addend */ + int32_t addend = arm_bl_blx_decode_addend(opaddr); + + /* Calculate and add the branch offset (addend) */ + addend += ((int32_t)opval) - ((int32_t)opaddr); + + /* Encode the addend */ + arm_bl_blx_encode_addend(opaddr, addend); + break; default: LOG_DBG("Unsupported ARM elf relocation type %d at address %lx", reloc_type, opaddr); diff --git a/include/zephyr/llext/elf.h b/include/zephyr/llext/elf.h index ac781316581..53445bfb6bd 100644 --- a/include/zephyr/llext/elf.h +++ b/include/zephyr/llext/elf.h @@ -371,6 +371,7 @@ struct elf64_rela { #define R_ARM_ABS32 2 #define R_ARM_REL32 3 #define R_ARM_COPY 4 +#define R_ARM_THM_CALL 10 #define R_ARM_CALL 28 #define R_ARM_V4BX 40 From d80945a9683fc0feb129fce7ea45e8ceeafd07b7 Mon Sep 17 00:00:00 2001 From: Bjarki Arge Andreasen Date: Tue, 12 Mar 2024 14:19:58 +0100 Subject: [PATCH 0674/2402] tests: llext: add relative jump test ext.c Validate the new relocations for BL and BLX instructions by creating a new test extension which contains a chain of global functions in a pseudo random order to (hopefully) generate relative jumps in both positive and negative directions. Signed-off-by: Bjarki Arge Andreasen --- tests/subsys/llext/simple/CMakeLists.txt | 2 +- .../llext/simple/src/relative_jump_ext.c | 59 +++++++++++++++++++ .../llext/simple/src/test_llext_simple.c | 5 ++ 3 files changed, 65 insertions(+), 1 deletion(-) create mode 100644 tests/subsys/llext/simple/src/relative_jump_ext.c diff --git a/tests/subsys/llext/simple/CMakeLists.txt b/tests/subsys/llext/simple/CMakeLists.txt index 03a781fb74d..e39f4f89008 100644 --- a/tests/subsys/llext/simple/CMakeLists.txt +++ b/tests/subsys/llext/simple/CMakeLists.txt @@ -16,7 +16,7 @@ target_include_directories(app PRIVATE ) # generate extension targets foreach extension given by name -foreach(ext_name hello_world logging) +foreach(ext_name hello_world logging relative_jump) set(ext_src ${PROJECT_SOURCE_DIR}/src/${ext_name}_ext.c) set(ext_bin ${ZEPHYR_BINARY_DIR}/${ext_name}.llext) set(ext_inc ${ZEPHYR_BINARY_DIR}/include/generated/${ext_name}.inc) diff --git a/tests/subsys/llext/simple/src/relative_jump_ext.c b/tests/subsys/llext/simple/src/relative_jump_ext.c new file mode 100644 index 00000000000..0619f201cef --- /dev/null +++ b/tests/subsys/llext/simple/src/relative_jump_ext.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2024 Trackunit Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This test is designed to test linking global symbols, which for some architectures + * like ARM generate relative jumps rather than jumping to absolute addresses. Multiple + * global functions are created to hopefully generate both positive and negative relative + * jumps. + */ + +#include +#include +#include + +void test_relative_jump_1(void); +void test_relative_jump_2(void); +void test_relative_jump_3(void); +void test_relative_jump_4(void); +void test_relative_jump_5(void); + +void test_relative_jump_5(void) +{ + printk("relative jump 5\n"); +} + +void test_relative_jump_4(void) +{ + printk("relative jump 4\n"); + test_relative_jump_5(); +} + +void test_relative_jump_2(void) +{ + printk("relative jump 2\n"); + test_relative_jump_3(); +} + +void test_relative_jump_1(void) +{ + printk("relative jump 1\n"); + test_relative_jump_2(); +} + +void test_relative_jump_3(void) +{ + printk("relative jump 3\n"); + test_relative_jump_4(); +} + +void test_entry(void) +{ + printk("enter\n"); + test_relative_jump_1(); + printk("exit\n"); +} +LL_EXTENSION_SYMBOL(test_entry); diff --git a/tests/subsys/llext/simple/src/test_llext_simple.c b/tests/subsys/llext/simple/src/test_llext_simple.c index d3d38a2a3ab..14d224f4779 100644 --- a/tests/subsys/llext/simple/src/test_llext_simple.c +++ b/tests/subsys/llext/simple/src/test_llext_simple.c @@ -147,6 +147,11 @@ static LLEXT_CONST uint8_t logging_ext[] __aligned(4) = { }; LLEXT_LOAD_UNLOAD(logging, true) +static LLEXT_CONST uint8_t relative_jump_ext[] __aligned(4) = { + #include "relative_jump.inc" +}; +LLEXT_LOAD_UNLOAD(relative_jump, true) + /* * Ensure that EXPORT_SYMBOL does indeed provide a symbol and a valid address * to it. From 67d7c13da9d07f85bc40159702f4dd675672b807 Mon Sep 17 00:00:00 2001 From: Bjarki Arge Andreasen Date: Wed, 13 Mar 2024 07:46:00 +0100 Subject: [PATCH 0675/2402] tests: llext: Update testcase to filter on ARCH_HAS_USERSPACE Change the filter from CPU_HAS_MPU to ARCH_HAS_USERSPACE to when filtering boards which support userspace. Signed-off-by: Bjarki Arge Andreasen --- tests/subsys/llext/simple/testcase.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/subsys/llext/simple/testcase.yaml b/tests/subsys/llext/simple/testcase.yaml index 1a10f980af2..bd683e2d3b0 100644 --- a/tests/subsys/llext/simple/testcase.yaml +++ b/tests/subsys/llext/simple/testcase.yaml @@ -16,7 +16,7 @@ tests: llext.simple.readonly_mpu: min_ram: 128 arch_exclude: xtensa # for now - filter: CONFIG_CPU_HAS_MPU + filter: CONFIG_ARCH_HAS_USERSPACE extra_configs: - CONFIG_USERSPACE=y - CONFIG_LLEXT_STORAGE_WRITABLE=n @@ -50,7 +50,7 @@ tests: - CONFIG_MODULES=y - CONFIG_LLEXT_TEST_HELLO=m llext.simple.modules_enabled_readonly_mpu: - filter: CONFIG_CPU_HAS_MPU + filter: CONFIG_ARCH_HAS_USERSPACE arch_exclude: xtensa # for now platform_key: - simulation From d0a8c4158c841f865c6d8360efaa0c92a2d29374 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Tue, 12 Mar 2024 20:26:06 +0000 Subject: [PATCH 0676/2402] input: gpio_keys: fix suspend race condition Change the suspend/resume code to ensure that the interrupt are disabled before changing the pin configuration. The current sequence has been reported to cause spurious readouts on some platforms, this takes the existing code and duplicates for the suspend and resume case, but swaps the interrupt disable and configure for the suspend case. Signed-off-by: Fabio Baltieri --- drivers/input/input_gpio_keys.c | 74 ++++++++++++++++++--------------- 1 file changed, 41 insertions(+), 33 deletions(-) diff --git a/drivers/input/input_gpio_keys.c b/drivers/input/input_gpio_keys.c index cd277c19fdc..7fca24a55ed 100644 --- a/drivers/input/input_gpio_keys.c +++ b/drivers/input/input_gpio_keys.c @@ -207,51 +207,59 @@ static int gpio_keys_pm_action(const struct device *dev, const struct gpio_keys_config *cfg = dev->config; struct gpio_keys_data *data = dev->data; struct gpio_keys_pin_data *pin_data = cfg->pin_data; - gpio_flags_t gpio_flags; - gpio_flags_t int_flags; int ret; switch (action) { case PM_DEVICE_ACTION_SUSPEND: - gpio_flags = GPIO_DISCONNECTED; - int_flags = GPIO_INT_DISABLE; atomic_set(&data->suspended, 1); - break; - case PM_DEVICE_ACTION_RESUME: - gpio_flags = GPIO_INPUT; - int_flags = GPIO_INT_EDGE_BOTH; - atomic_set(&data->suspended, 0); - break; - default: - return -ENOTSUP; - } - for (int i = 0; i < cfg->num_keys; i++) { - const struct gpio_dt_spec *gpio = &cfg->pin_cfg[i].spec; - - ret = gpio_pin_configure_dt(gpio, gpio_flags); - if (ret != 0) { - LOG_ERR("Pin %d configuration failed: %d", i, ret); - return ret; + for (int i = 0; i < cfg->num_keys; i++) { + const struct gpio_dt_spec *gpio = &cfg->pin_cfg[i].spec; + + if (!cfg->polling_mode) { + ret = gpio_pin_interrupt_configure_dt(gpio, GPIO_INT_DISABLE); + if (ret < 0) { + LOG_ERR("interrupt configuration failed: %d", ret); + return ret; + } + } + + ret = gpio_pin_configure_dt(gpio, GPIO_DISCONNECTED); + if (ret != 0) { + LOG_ERR("Pin %d configuration failed: %d", i, ret); + return ret; + } } - if (cfg->polling_mode) { - continue; - } + return 0; + case PM_DEVICE_ACTION_RESUME: + atomic_set(&data->suspended, 0); - ret = gpio_pin_interrupt_configure_dt(gpio, int_flags); - if (ret < 0) { - LOG_ERR("interrupt configuration failed: %d", ret); - return ret; + for (int i = 0; i < cfg->num_keys; i++) { + const struct gpio_dt_spec *gpio = &cfg->pin_cfg[i].spec; + + ret = gpio_pin_configure_dt(gpio, GPIO_INPUT); + if (ret != 0) { + LOG_ERR("Pin %d configuration failed: %d", i, ret); + return ret; + } + + if (cfg->polling_mode) { + k_work_reschedule(&pin_data[0].work, + K_MSEC(cfg->debounce_interval_ms)); + } else { + ret = gpio_pin_interrupt_configure_dt(gpio, GPIO_INT_EDGE_BOTH); + if (ret < 0) { + LOG_ERR("interrupt configuration failed: %d", ret); + return ret; + } + } } - } - if (action == PM_DEVICE_ACTION_RESUME && cfg->polling_mode) { - k_work_reschedule(&pin_data[0].work, - K_MSEC(cfg->debounce_interval_ms)); + return 0; + default: + return -ENOTSUP; } - - return 0; } #endif From 7c2f26bd2a51fcc667d53154a9d650412630eb70 Mon Sep 17 00:00:00 2001 From: Rubin Gerritsen Date: Mon, 11 Mar 2024 13:53:09 +0100 Subject: [PATCH 0677/2402] Bluetooth: Host: Add macros for contiuous scanner It is often desired to maximize the chances of receiving advertising when scanning. To achieve this, the scanner should be enabled all the time. Some controller implementations (like Nordic's SoftDevice Controller) handle scheduling differently when scan_window = scan_interval. Having a macro that defines this scanning configuration simplifies writing applications. Signed-off-by: Rubin Gerritsen --- include/zephyr/bluetooth/bluetooth.h | 25 +++++++++++++++++++ include/zephyr/bluetooth/gap.h | 1 + .../host/att/pipeline/dut/src/main.c | 8 +----- tests/bsim/bluetooth/ll/cis/src/main.c | 11 +------- 4 files changed, 28 insertions(+), 17 deletions(-) diff --git a/include/zephyr/bluetooth/bluetooth.h b/include/zephyr/bluetooth/bluetooth.h index 073c46a1c08..bca9dbed22d 100644 --- a/include/zephyr/bluetooth/bluetooth.h +++ b/include/zephyr/bluetooth/bluetooth.h @@ -2129,6 +2129,18 @@ struct bt_le_scan_cb { BT_GAP_SCAN_FAST_INTERVAL, \ BT_GAP_SCAN_FAST_WINDOW) +/** + * @brief Helper macro to enable active scanning to discover new devices with window == interval. + * + * Continuous scanning should be used to maximize the chances of receiving advertising packets. + */ +#define BT_LE_SCAN_ACTIVE_CONTINUOUS BT_LE_SCAN_PARAM(BT_LE_SCAN_TYPE_ACTIVE, \ + BT_LE_SCAN_OPT_FILTER_DUPLICATE, \ + BT_GAP_SCAN_FAST_INTERVAL_MIN, \ + BT_GAP_SCAN_FAST_WINDOW) +BUILD_ASSERT(BT_GAP_SCAN_FAST_WINDOW == BT_GAP_SCAN_FAST_INTERVAL_MIN, + "Continuous scanning is requested by setting window and interval equal."); + /** * @brief Helper macro to enable passive scanning to discover new devices. * @@ -2140,6 +2152,19 @@ struct bt_le_scan_cb { BT_GAP_SCAN_FAST_INTERVAL, \ BT_GAP_SCAN_FAST_WINDOW) +/** + * @brief Helper macro to enable passive scanning to discover new devices with window==interval. + * + * This macro should be used if information required for device identification + * (e.g., UUID) are known to be placed in Advertising Data. + */ +#define BT_LE_SCAN_PASSIVE_CONTINUOUS BT_LE_SCAN_PARAM(BT_LE_SCAN_TYPE_PASSIVE, \ + BT_LE_SCAN_OPT_FILTER_DUPLICATE, \ + BT_GAP_SCAN_FAST_INTERVAL_MIN, \ + BT_GAP_SCAN_FAST_WINDOW) +BUILD_ASSERT(BT_GAP_SCAN_FAST_WINDOW == BT_GAP_SCAN_FAST_INTERVAL_MIN, + "Continuous scanning is requested by setting window and interval equal."); + /** * @brief Helper macro to enable active scanning to discover new devices. * Include scanning on Coded PHY in addition to 1M PHY. diff --git a/include/zephyr/bluetooth/gap.h b/include/zephyr/bluetooth/gap.h index 02fa8878c6b..16026d218e1 100644 --- a/include/zephyr/bluetooth/gap.h +++ b/include/zephyr/bluetooth/gap.h @@ -708,6 +708,7 @@ extern "C" { * @name Defined GAP timers * @{ */ +#define BT_GAP_SCAN_FAST_INTERVAL_MIN 0x0030 /* 30 ms */ #define BT_GAP_SCAN_FAST_INTERVAL 0x0060 /* 60 ms */ #define BT_GAP_SCAN_FAST_WINDOW 0x0030 /* 30 ms */ #define BT_GAP_SCAN_SLOW_INTERVAL_1 0x0800 /* 1.28 s */ diff --git a/tests/bsim/bluetooth/host/att/pipeline/dut/src/main.c b/tests/bsim/bluetooth/host/att/pipeline/dut/src/main.c index 1a3c1480e1e..6481ce909b4 100644 --- a/tests/bsim/bluetooth/host/att/pipeline/dut/src/main.c +++ b/tests/bsim/bluetooth/host/att/pipeline/dut/src/main.c @@ -151,16 +151,10 @@ static struct bt_conn *connect(void) { int err; struct bt_conn *conn; - struct bt_le_scan_param scan_param = { - .type = BT_LE_SCAN_TYPE_ACTIVE, - .options = BT_LE_SCAN_OPT_NONE, - .interval = BT_GAP_SCAN_FAST_INTERVAL, - .window = BT_GAP_SCAN_FAST_WINDOW, - }; UNSET_FLAG(is_connected); - err = bt_le_scan_start(&scan_param, device_found); + err = bt_le_scan_start(BT_LE_SCAN_ACTIVE_CONTINUOUS, device_found); ASSERT(!err, "Scanning failed to start (err %d)\n", err); LOG_DBG("Central initiating connection..."); diff --git a/tests/bsim/bluetooth/ll/cis/src/main.c b/tests/bsim/bluetooth/ll/cis/src/main.c index 665c8e0daa4..e54b2e5224c 100644 --- a/tests/bsim/bluetooth/ll/cis/src/main.c +++ b/tests/bsim/bluetooth/ll/cis/src/main.c @@ -45,9 +45,6 @@ static K_SEM_DEFINE(sem_iso_data, CONFIG_BT_ISO_TX_BUF_COUNT, CONFIG_BT_ISO_TX_BUF_COUNT); static bt_addr_le_t peer_addr; -#define SCAN_INTERVAL 0x0010 -#define SCAN_WINDOW 0x0010 - #define CREATE_CONN_INTERVAL 0x0010 #define CREATE_CONN_WINDOW 0x0010 @@ -69,12 +66,6 @@ static bt_addr_le_t peer_addr; #define ADV_INTERVAL_MIN 0x0020 #define ADV_INTERVAL_MAX 0x0020 -#define BT_LE_SCAN_CUSTOM \ - BT_LE_SCAN_PARAM(BT_LE_SCAN_TYPE_PASSIVE, \ - BT_LE_SCAN_OPT_NONE, \ - SCAN_INTERVAL, \ - SCAN_WINDOW) - #define BT_CONN_LE_CREATE_CONN_CUSTOM \ BT_CONN_LE_CREATE_PARAM(BT_CONN_LE_OPT_NONE, \ CREATE_CONN_INTERVAL, \ @@ -451,7 +442,7 @@ static void test_cis_central(void) int chan; printk("Start scanning (%d)...", i); - err = bt_le_scan_start(BT_LE_SCAN_CUSTOM, NULL); + err = bt_le_scan_start(BT_LE_SCAN_PASSIVE_CONTINUOUS, NULL); if (err) { FAIL("Could not start scan: %d\n", err); return; From 3ad8d32d184a72804540440b323877024a0a0969 Mon Sep 17 00:00:00 2001 From: sukrit buddeewong Date: Wed, 28 Feb 2024 03:29:33 +0900 Subject: [PATCH 0678/2402] net: mqtt: Implement ALPN Support for socket mqtt Implement the ALPN Support for Mqtt Library allow mqtt to have ability to utilize ALPN for connect to server that support ALPN, such as AWS IoT Core Signed-off-by: sukrit buddeewong --- include/zephyr/net/mqtt.h | 13 +++++++++++++ subsys/net/lib/mqtt/Kconfig | 6 ++++++ subsys/net/lib/mqtt/mqtt_transport_socket_tls.c | 13 +++++++++++++ 3 files changed, 32 insertions(+) diff --git a/include/zephyr/net/mqtt.h b/include/zephyr/net/mqtt.h index f1071af64f2..0067c9ae8bd 100644 --- a/include/zephyr/net/mqtt.h +++ b/include/zephyr/net/mqtt.h @@ -356,6 +356,19 @@ struct mqtt_sec_config { /** Indicates the list of security tags to be used for the session. */ const sec_tag_t *sec_tag_list; +#if defined(CONFIG_MQTT_LIB_TLS_USE_ALPN) + /** + * Pointer to array of string indicating the ALPN protocol name. + * May be NULL to skip ALPN protocol negotiation. + */ + const char **alpn_protocol_name_list; + + /** + * Indicate number of ALPN protocol name in alpn protocol name list. + */ + uint32_t alpn_protocol_name_count; +#endif + /** Peer hostname for ceritificate verification. * May be NULL to skip hostname verification. */ diff --git a/subsys/net/lib/mqtt/Kconfig b/subsys/net/lib/mqtt/Kconfig index 25aa600c87f..11e59b527e9 100644 --- a/subsys/net/lib/mqtt/Kconfig +++ b/subsys/net/lib/mqtt/Kconfig @@ -29,6 +29,12 @@ config MQTT_LIB_TLS help Enable TLS support for socket MQTT Library +config MQTT_LIB_TLS_USE_ALPN + bool "ALPN support for MQTT" + depends on MQTT_LIB_TLS + help + Enable ALPN protocol for socket MQTT Library. + config MQTT_LIB_WEBSOCKET bool "Websocket support for socket MQTT Library" help diff --git a/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c b/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c index c835656b6cf..a33cee5aecf 100644 --- a/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c +++ b/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c @@ -69,6 +69,19 @@ int mqtt_client_tls_connect(struct mqtt_client *client) } } +#if defined(CONFIG_MQTT_LIB_TLS_USE_ALPN) + if (tls_config->alpn_protocol_name_list != NULL && + tls_config->alpn_protocol_name_count > 0) { + ret = zsock_setsockopt(client->transport.tls.sock, SOL_TLS, + TLS_ALPN_LIST, tls_config->alpn_protocol_name_list, + sizeof(const char *) * tls_config->alpn_protocol_name_count); + if (ret < 0) { + goto error; + } + } + +#endif + if (tls_config->hostname) { ret = zsock_setsockopt(client->transport.tls.sock, SOL_TLS, TLS_HOSTNAME, tls_config->hostname, From ddb147d0a45df2b52af1065a49770566847ab975 Mon Sep 17 00:00:00 2001 From: sukrit buddeewong Date: Thu, 29 Feb 2024 02:53:14 +0900 Subject: [PATCH 0679/2402] sample: net: mqtt: add ALPN Sample code for aws due to MQTT now have ALPN support the example code of using ALPN to connect MQTT over port 443 need to be added Signed-off-by: sukrit buddeewong --- samples/net/cloud/aws_iot_mqtt/Kconfig | 6 ++++++ samples/net/cloud/aws_iot_mqtt/README.rst | 1 + samples/net/cloud/aws_iot_mqtt/prj.conf | 3 +++ samples/net/cloud/aws_iot_mqtt/src/dhcp.c | 2 +- samples/net/cloud/aws_iot_mqtt/src/main.c | 14 ++++++++++++-- 5 files changed, 23 insertions(+), 3 deletions(-) diff --git a/samples/net/cloud/aws_iot_mqtt/Kconfig b/samples/net/cloud/aws_iot_mqtt/Kconfig index b1d99ed6d70..a80d28db5c6 100644 --- a/samples/net/cloud/aws_iot_mqtt/Kconfig +++ b/samples/net/cloud/aws_iot_mqtt/Kconfig @@ -14,6 +14,12 @@ config AWS_ENDPOINT Endpoint (hostname) of the AWS MQTT broker. Note that the endpoint is different when using AWS Device Advisor. +config AWS_MQTT_PORT + int "MQTT Port" + default 8883 + help + Set port of AWS MQTT broker. + config AWS_THING_NAME string "AWS Thing name" default "myThingName" diff --git a/samples/net/cloud/aws_iot_mqtt/README.rst b/samples/net/cloud/aws_iot_mqtt/README.rst index 8ad0d1f9738..6bb6d872dc7 100644 --- a/samples/net/cloud/aws_iot_mqtt/README.rst +++ b/samples/net/cloud/aws_iot_mqtt/README.rst @@ -45,6 +45,7 @@ Core region, thing, and device advisor configuration: - :kconfig:option:`CONFIG_AWS_ENDPOINT`: The AWS IoT Core broker endpoint, found in the AWS IoT Core console. This will be specific if running a test suite using device advisor. +- :kconfig:option:`CONFIG_AWS_MQTT_PORT`: Port number for AWS IoT Core MQTT broker. - :kconfig:option:`CONFIG_AWS_THING_NAME`: The name of the thing created in AWS IoT Core. Associated with the certificate it will be used as the client id. We will use ``zephyr_sample`` in this example. diff --git a/samples/net/cloud/aws_iot_mqtt/prj.conf b/samples/net/cloud/aws_iot_mqtt/prj.conf index 6738212e44c..b7f1d1f9857 100644 --- a/samples/net/cloud/aws_iot_mqtt/prj.conf +++ b/samples/net/cloud/aws_iot_mqtt/prj.conf @@ -1,4 +1,5 @@ CONFIG_AWS_ENDPOINT="a31gokdeokxhl8-ats.iot.eu-west-1.amazonaws.com" +CONFIG_AWS_MQTT_PORT=8883 CONFIG_AWS_THING_NAME="zephyr_sample" CONFIG_AWS_PUBLISH_TOPIC="zephyr_sample/data" CONFIG_AWS_SUBSCRIBE_TOPIC="zephyr_sample/downlink" @@ -45,6 +46,7 @@ CONFIG_NET_BUF_TX_COUNT=32 CONFIG_MQTT_LIB=y CONFIG_MQTT_LIB_TLS=y CONFIG_MQTT_KEEPALIVE=60 +CONFIG_MQTT_LIB_TLS_USE_ALPN=y # TLS CONFIG_MBEDTLS=y @@ -58,3 +60,4 @@ CONFIG_MBEDTLS_AES_ROM_TABLES=y CONFIG_MBEDTLS_TLS_VERSION_1_2=y CONFIG_MBEDTLS_MEMORY_DEBUG=y CONFIG_MBEDTLS_HAVE_TIME_DATE=y +CONFIG_MBEDTLS_SSL_ALPN=y diff --git a/samples/net/cloud/aws_iot_mqtt/src/dhcp.c b/samples/net/cloud/aws_iot_mqtt/src/dhcp.c index 250d0ffd684..26e95bcff00 100644 --- a/samples/net/cloud/aws_iot_mqtt/src/dhcp.c +++ b/samples/net/cloud/aws_iot_mqtt/src/dhcp.c @@ -35,7 +35,7 @@ static void handler(struct net_mgmt_event_callback *cb, } for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) { - if (iface->config.ip.ipv4->unicast[i].addr_type != + if (iface->config.ip.ipv4->unicast[i].ipv4.addr_type != NET_ADDR_DHCP) { continue; } diff --git a/samples/net/cloud/aws_iot_mqtt/src/main.c b/samples/net/cloud/aws_iot_mqtt/src/main.c index 09999d2e4eb..f1f56ffa27c 100644 --- a/samples/net/cloud/aws_iot_mqtt/src/main.c +++ b/samples/net/cloud/aws_iot_mqtt/src/main.c @@ -30,7 +30,7 @@ LOG_MODULE_REGISTER(aws, LOG_LEVEL_DBG); #define SNTP_SERVER "0.pool.ntp.org" -#define AWS_BROKER_PORT "8883" +#define AWS_BROKER_PORT CONFIG_AWS_MQTT_PORT #define MQTT_BUFFER_SIZE 256u #define APP_BUFFER_SIZE 4096u @@ -54,6 +54,10 @@ static uint32_t messages_received_counter; static bool do_publish; /* Trigger client to publish */ static bool do_subscribe; /* Trigger client to subscribe */ +#if (CONFIG_AWS_MQTT_PORT == 443 && !defined(CONFIG_MQTT_LIB_WEBSOCKET)) +static const char * const alpn_list[] = {"x-amzn-mqtt-ca"}; +#endif + #define TLS_TAG_DEVICE_CERTIFICATE 1 #define TLS_TAG_DEVICE_PRIVATE_KEY 1 #define TLS_TAG_AWS_CA_CERTIFICATE 2 @@ -266,6 +270,10 @@ static void aws_client_setup(void) tls_config->sec_tag_count = ARRAY_SIZE(sec_tls_tags); tls_config->hostname = CONFIG_AWS_ENDPOINT; tls_config->cert_nocopy = TLS_CERT_NOCOPY_NONE; +#if (CONFIG_AWS_MQTT_PORT == 443 && !defined(CONFIG_MQTT_LIB_WEBSOCKET)) + tls_config->alpn_protocol_name_list = alpn_list; + tls_config->alpn_protocol_name_count = ARRAY_SIZE(alpn_list); +#endif } struct backoff_context { @@ -443,8 +451,10 @@ static int resolve_broker_addr(struct sockaddr_in *broker) .ai_socktype = SOCK_STREAM, .ai_protocol = 0, }; + char port_string[6] = {0}; - ret = zsock_getaddrinfo(CONFIG_AWS_ENDPOINT, AWS_BROKER_PORT, &hints, &ai); + sprintf(port_string, "%d", AWS_BROKER_PORT); + ret = zsock_getaddrinfo(CONFIG_AWS_ENDPOINT, port_string, &hints, &ai); if (ret == 0) { char addr_str[INET_ADDRSTRLEN]; From d1444856c074bd7f00f1fc07d7187965e7bbb4cb Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Thu, 14 Mar 2024 14:58:00 -0500 Subject: [PATCH 0680/2402] soc: nxp: imxrt: fix dependencies of NXP_IMXRT_BOOT_HEADER for RT11xx Dependencies of NXP_IMXRT_BOOT_HEADER were set incorrectly for the RT11xx series part when building a dual core image. The boot header should be enabled by default for the primary M7 core, and always disabled when MCUBOOT is used or the M4 core is targeted Signed-off-by: Daniel DeGrasse --- soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig index b66e4ff851c..9bd744062f4 100644 --- a/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig +++ b/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig @@ -29,7 +29,8 @@ if SECOND_CORE_MCUX # RT Boot header is only needed on primary core config NXP_IMXRT_BOOT_HEADER - depends on CPU_CORTEX_M7 + default y + depends on !(CPU_CORTEX_M4 || BOOTLOADER_MCUBOOT) endif endif From cd2d987e8289ae02a4d31740394315394e4234d7 Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Mon, 4 Mar 2024 23:15:10 +0100 Subject: [PATCH 0681/2402] drivers: video: sw_generator: Fix minor macro usage VIDEO_PATTERN_FPS should be coherently used across the entire code file. Signed-off-by: Phi Bang Nguyen --- drivers/video/video_sw_generator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/video_sw_generator.c b/drivers/video/video_sw_generator.c index 3b9724ba42e..b7af6138aaf 100644 --- a/drivers/video/video_sw_generator.c +++ b/drivers/video/video_sw_generator.c @@ -55,7 +55,7 @@ static int video_sw_generator_stream_start(const struct device *dev) { struct video_sw_generator_data *data = dev->data; - k_work_schedule(&data->buf_work, K_MSEC(33)); + k_work_schedule(&data->buf_work, K_MSEC(1000 / VIDEO_PATTERN_FPS)); return 0; } From c720ee1b1ee3170bc6aec5c7c9784bea7cda16f3 Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Tue, 13 Feb 2024 14:21:27 +0100 Subject: [PATCH 0682/2402] include: video: Add XRGB32 pixel format Add XRGB32 pixel format Signed-off-by: Phi Bang Nguyen --- include/zephyr/drivers/video.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/zephyr/drivers/video.h b/include/zephyr/drivers/video.h index 9a29d9f055e..ee9e2f2feee 100644 --- a/include/zephyr/drivers/video.h +++ b/include/zephyr/drivers/video.h @@ -611,6 +611,9 @@ void video_buffer_release(struct video_buffer *buf); /** RGB565 pixel format */ #define VIDEO_PIX_FMT_RGB565 video_fourcc('R', 'G', 'B', 'P') /* 16 RGB-5-6-5 */ +/** XRGB32 pixel format */ +#define VIDEO_PIX_FMT_XRGB32 video_fourcc('B', 'X', '2', '4') /* 32 XRGB-8-8-8-8 */ + /** * @} */ From d1275f7fde40c67416257c8e6bc383d73a612419 Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Fri, 2 Feb 2024 00:41:35 +0100 Subject: [PATCH 0683/2402] drivers: video: sw_generator: Support XRGB32 pixel format Add support for XRGB32 pixel format as this is useful to test camera and display drivers on i.MX RT11xx Signed-off-by: Phi Bang Nguyen --- drivers/video/video_sw_generator.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/video/video_sw_generator.c b/drivers/video/video_sw_generator.c index b7af6138aaf..ada1c7277e2 100644 --- a/drivers/video/video_sw_generator.c +++ b/drivers/video/video_sw_generator.c @@ -72,6 +72,9 @@ static int video_sw_generator_stream_stop(const struct device *dev) /* Black, Blue, Red, Purple, Green, Aqua, Yellow, White */ uint16_t rgb565_colorbar_value[] = {0x0000, 0x001F, 0xF800, 0xF81F, 0x07E0, 0x07FF, 0xFFE0, 0xFFFF}; +uint32_t xrgb32_colorbar_value[] = {0xFF000000, 0xFF0000FF, 0xFFFF0000, 0xFFFF00FF, + 0xFF00FF00, 0xFF00FFFF, 0xFFFFFF00, 0xFFFFFFFF}; + static void __fill_buffer_colorbar(struct video_sw_generator_data *data, struct video_buffer *vbuf) { int bw = data->fmt.width / 8; @@ -84,6 +87,10 @@ static void __fill_buffer_colorbar(struct video_sw_generator_data *data, struct uint16_t *pixel = (uint16_t *)&vbuf->buffer[i]; *pixel = rgb565_colorbar_value[color_idx]; i += 2; + } else if (data->fmt.pixelformat == VIDEO_PIX_FMT_XRGB32) { + uint32_t *pixel = (uint32_t *)&vbuf->buffer[i]; + *pixel = xrgb32_colorbar_value[color_idx]; + i += 4; } } } @@ -184,6 +191,14 @@ static const struct video_format_cap fmts[] = {{ .height_max = 1080, .width_step = 1, .height_step = 1, + }, { + .pixelformat = VIDEO_PIX_FMT_XRGB32, + .width_min = 64, + .width_max = 1920, + .height_min = 64, + .height_max = 1080, + .width_step = 1, + .height_step = 1, }, {0}}; From 4b8d3dbed8a19a28a37b3fb5b46787ddb14d98b0 Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Tue, 13 Feb 2024 14:17:30 +0100 Subject: [PATCH 0684/2402] drivers: video: sw_generator: Fix set_format Add code to handle invalid formats when setting format Signed-off-by: Phi Bang Nguyen --- drivers/video/video_sw_generator.c | 56 ++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/drivers/video/video_sw_generator.c b/drivers/video/video_sw_generator.c index ada1c7277e2..9b0f3e238b5 100644 --- a/drivers/video/video_sw_generator.c +++ b/drivers/video/video_sw_generator.c @@ -7,6 +7,10 @@ #include +#define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL +#include +LOG_MODULE_REGISTER(video_sw_generator); + #define VIDEO_PATTERN_COLOR_BAR 0 #define VIDEO_PATTERN_FPS 30 @@ -23,15 +27,48 @@ struct video_sw_generator_data { struct k_poll_signal *signal; }; +static const struct video_format_cap fmts[] = {{ + .pixelformat = VIDEO_PIX_FMT_RGB565, + .width_min = 64, + .width_max = 1920, + .height_min = 64, + .height_max = 1080, + .width_step = 1, + .height_step = 1, + }, { + .pixelformat = VIDEO_PIX_FMT_XRGB32, + .width_min = 64, + .width_max = 1920, + .height_min = 64, + .height_max = 1080, + .width_step = 1, + .height_step = 1, + }, + {0}}; + static int video_sw_generator_set_fmt(const struct device *dev, enum video_endpoint_id ep, struct video_format *fmt) { struct video_sw_generator_data *data = dev->data; + int i = 0; if (ep != VIDEO_EP_OUT) { return -EINVAL; } + for (i = 0; i < ARRAY_SIZE(fmts); ++i) { + if (fmt->pixelformat == fmts[i].pixelformat && fmt->width >= fmts[i].width_min && + fmt->width <= fmts[i].width_max && fmt->height >= fmts[i].height_min && + fmt->height <= fmts[i].height_max) { + break; + } + } + + if (i == ARRAY_SIZE(fmts)) { + LOG_ERR("Unsupported pixel format or resolution"); + return -ENOTSUP; + } + data->fmt = *fmt; return 0; @@ -183,25 +220,6 @@ static int video_sw_generator_flush(const struct device *dev, enum video_endpoin return 0; } -static const struct video_format_cap fmts[] = {{ - .pixelformat = VIDEO_PIX_FMT_RGB565, - .width_min = 64, - .width_max = 1920, - .height_min = 64, - .height_max = 1080, - .width_step = 1, - .height_step = 1, - }, { - .pixelformat = VIDEO_PIX_FMT_XRGB32, - .width_min = 64, - .width_max = 1920, - .height_min = 64, - .height_max = 1080, - .width_step = 1, - .height_step = 1, - }, - {0}}; - static int video_sw_generator_get_caps(const struct device *dev, enum video_endpoint_id ep, struct video_caps *caps) { From 41b3c71586870cab696539218322b297ab119b3d Mon Sep 17 00:00:00 2001 From: Serhiy Katsyuba Date: Mon, 26 Feb 2024 18:03:24 +0100 Subject: [PATCH 0685/2402] drivers: dma: intel_adsp_hda: Fix L1 exit condition Transition to a low power DMI L1 state should be allowed only after all pending DMA channels transfers have started. Signed-off-by: Serhiy Katsyuba --- drivers/dma/dma_intel_adsp_hda.c | 34 +++++++++++++++---- .../common/include/intel_adsp_hda.h | 13 +++++++ 2 files changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/dma/dma_intel_adsp_hda.c b/drivers/dma/dma_intel_adsp_hda.c index abfd085adb5..e713e7afb13 100644 --- a/drivers/dma/dma_intel_adsp_hda.c +++ b/drivers/dma/dma_intel_adsp_hda.c @@ -438,8 +438,9 @@ void intel_adsp_hda_dma_isr(void) #if CONFIG_DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT struct dma_context *dma_ctx; const struct intel_adsp_hda_dma_cfg *cfg; - bool clear_l1_exit = false; + bool triggered_interrupts = false; int i, j; + int expected_interrupts = 0; const struct device *host_dev[] = { #if CONFIG_DMA_INTEL_ADSP_HDA_HOST_OUT DT_FOREACH_STATUS_OKAY(intel_adsp_hda_host_out, DEVICE_DT_GET_AND_COMMA) @@ -449,25 +450,44 @@ void intel_adsp_hda_dma_isr(void) #endif }; + /* + * To initiate transfer, DSP must be in L0 state. Once the transfer is started, DSP can go + * to the low power L1 state, and the transfer will be able to continue and finish in L1 + * state. Interrupts are configured to trigger after the first 32 bytes of data arrive. + * Once such an interrupt arrives, the transfer has already started. If all expected + * transfers have started, it is safe to allow the low power L1 state. + */ + for (i = 0; i < ARRAY_SIZE(host_dev); i++) { dma_ctx = (struct dma_context *)host_dev[i]->data; cfg = host_dev[i]->config; for (j = 0; j < dma_ctx->dma_channels; j++) { - if (atomic_test_bit(dma_ctx->atomic, j)) { - clear_l1_exit |= - intel_adsp_hda_check_buffer_interrupt(cfg->base, - cfg->regblock_size, - j); + if (!atomic_test_bit(dma_ctx->atomic, j)) + continue; + + if (!intel_adsp_hda_is_buffer_interrupt_enabled(cfg->base, + cfg->regblock_size, j)) + continue; + + if (intel_adsp_hda_check_buffer_interrupt(cfg->base, + cfg->regblock_size, j)) { + triggered_interrupts = true; intel_adsp_hda_disable_buffer_interrupt(cfg->base, cfg->regblock_size, j); intel_adsp_hda_clear_buffer_interrupt(cfg->base, cfg->regblock_size, j); + } else { + expected_interrupts++; } } } - if (clear_l1_exit) { + /* + * Allow entering low power L1 state only after all enabled interrupts arrived, i.e., + * transfers started on all channels. + */ + if (triggered_interrupts && expected_interrupts == 0) { intel_adsp_allow_dmi_l1_state(); } #endif diff --git a/soc/intel/intel_adsp/common/include/intel_adsp_hda.h b/soc/intel/intel_adsp/common/include/intel_adsp_hda.h index 628a84cd1a0..47285c03ad5 100644 --- a/soc/intel/intel_adsp/common/include/intel_adsp_hda.h +++ b/soc/intel/intel_adsp/common/include/intel_adsp_hda.h @@ -444,6 +444,19 @@ static inline void intel_adsp_hda_disable_buffer_interrupt(uint32_t base, uint32 *DGCS(base, regblock_size, sid) &= ~DGCS_BSCIE; } +/** + * @brief Check if BSC interrupt enabled + * + * @param base Base address of the IP register block + * @param regblock_size Register block size + * @param sid Stream ID + */ +static inline bool intel_adsp_hda_is_buffer_interrupt_enabled(uint32_t base, + uint32_t regblock_size, uint32_t sid) +{ + return (*DGCS(base, regblock_size, sid) & DGCS_BSCIE) == DGCS_BSCIE; +} + static inline void intel_adsp_force_dmi_l0_state(void) { #ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE From 31450fcb1286920d8270c9489425684ed1195933 Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Wed, 27 Dec 2023 20:43:16 +0100 Subject: [PATCH 0686/2402] drivers: gpio: split up driver for BD8LB600FS into a GPIO and MFD Split up the driver for the low side switch BD8LB600FS into a GPIO and MFD part. Signed-off-by: Benedikt Schmidt --- drivers/gpio/Kconfig.bd8lb600fs | 5 +- drivers/gpio/gpio_bd8lb600fs.c | 212 +++++---------- drivers/mfd/CMakeLists.txt | 1 + drivers/mfd/Kconfig | 1 + drivers/mfd/Kconfig.bd8lb600fs | 11 + drivers/mfd/mfd_bd8lb600fs.c | 242 ++++++++++++++++++ ...lb600fs.yaml => rohm,bd8lb600fs-gpio.yaml} | 17 +- dts/bindings/mfd/rohm,bd8lb600fs.yaml | 31 +++ include/zephyr/drivers/mfd/bd8lb600fs.h | 60 +++++ .../build_all/gpio/adc_ads1145s0x_gpio.conf | 3 +- tests/drivers/build_all/gpio/app.overlay | 13 +- tests/drivers/build_all/gpio/prj.conf | 1 + 12 files changed, 432 insertions(+), 165 deletions(-) create mode 100644 drivers/mfd/Kconfig.bd8lb600fs create mode 100644 drivers/mfd/mfd_bd8lb600fs.c rename dts/bindings/gpio/{rohm,bd8lb600fs.yaml => rohm,bd8lb600fs-gpio.yaml} (77%) create mode 100644 dts/bindings/mfd/rohm,bd8lb600fs.yaml create mode 100644 include/zephyr/drivers/mfd/bd8lb600fs.h diff --git a/drivers/gpio/Kconfig.bd8lb600fs b/drivers/gpio/Kconfig.bd8lb600fs index 517219dc965..1587c1462d1 100644 --- a/drivers/gpio/Kconfig.bd8lb600fs +++ b/drivers/gpio/Kconfig.bd8lb600fs @@ -1,13 +1,14 @@ # BD8LB600FS GPIO configuration options # Copyright (c) 2022 SILA Embedded Solutions GmbH +# Copyright (c) 2024 SILA Embedded Solutions GmbH # SPDX-License-Identifier: Apache-2.0 menuconfig GPIO_BD8LB600FS bool "BD8LB600FS SPI-based GPIO chip" default y - depends on DT_HAS_ROHM_BD8LB600FS_ENABLED - depends on SPI + depends on DT_HAS_ROHM_BD8LB600FS_GPIO_ENABLED + select MFD help Enable driver for BD8LB600FS SPI-based GPIO chip. diff --git a/drivers/gpio/gpio_bd8lb600fs.c b/drivers/gpio/gpio_bd8lb600fs.c index ad49e4a7768..4a2e5f7229f 100644 --- a/drivers/gpio/gpio_bd8lb600fs.c +++ b/drivers/gpio/gpio_bd8lb600fs.c @@ -1,111 +1,51 @@ /* * Copyright (c) 2022 SILA Embedded Solutions GmbH + * Copyright (c) 2024 SILA Embedded Solutions GmbH * * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT rohm_bd8lb600fs - -#include +#define DT_DRV_COMPAT rohm_bd8lb600fs_gpio #include #include #include #include #include -#include +#include #include -#include LOG_MODULE_REGISTER(gpio_bd8lb600fs, CONFIG_GPIO_LOG_LEVEL); -#define OUTPUT_OFF_WITH_OPEN_LOAD_DETECTION 0b11 -#define OUTPUT_ON 0b10 -#define WAIT_TIME_RESET_ACTIVE_IN_US 1000 -#define WAIT_TIME_RESET_INACTIVE_TO_CS_IN_US 10 - -struct bd8lb600fs_config { +struct bd8lb600fs_gpio_config { /* gpio_driver_config needs to be first */ struct gpio_driver_config common; - - struct spi_dt_spec bus; - const struct gpio_dt_spec gpio_reset; + const struct device *parent_dev; int gpios_count; }; -struct bd8lb600fs_drv_data { +struct bd8lb600fs_gpio_data { /* gpio_driver_data needs to be first */ struct gpio_driver_data data; - uint32_t state; /* each bit is one output channel, bit 0 = channel 1, ... */ - uint32_t configured; /* each bit defines if the output channel is configured, see state */ + /* each bit is one output channel, bit 0 = channel 1, ... */ + uint32_t state; + /* each bit defines if the output channel is configured, see state */ + uint32_t configured; struct k_mutex lock; - int instance_count_actual; - int gpios_count_actual; }; -static int write_state(const struct device *dev, uint32_t state) -{ - const struct bd8lb600fs_config *config = dev->config; - struct bd8lb600fs_drv_data *drv_data = dev->data; - - LOG_DBG("%s: writing state 0x%08X to BD8LB600FS", dev->name, state); - - uint16_t state_converted = 0; - uint8_t buffer_tx[8]; - const struct spi_buf tx_buf = { - .buf = buffer_tx, - .len = drv_data->instance_count_actual * sizeof(state_converted), - }; - const struct spi_buf_set tx = { - .buffers = &tx_buf, - .count = 1, - }; - - memset(buffer_tx, 0x00, sizeof(buffer_tx)); - - for (size_t j = 0; j < drv_data->instance_count_actual; ++j) { - int instance_position = (drv_data->instance_count_actual - j - 1) * 2; - - state_converted = 0; - - for (size_t i = 0; i < 8; ++i) { - if ((state & BIT(i + j*8)) == 0) { - state_converted |= OUTPUT_OFF_WITH_OPEN_LOAD_DETECTION << (i * 2); - } else { - state_converted |= OUTPUT_ON << (i * 2); - } - } - - LOG_DBG("%s: configuration for instance %zu: %04X (position %i)", - dev->name, - j, - state_converted, - instance_position); - sys_put_be16(state_converted, buffer_tx + instance_position); - } - - LOG_HEXDUMP_DBG(buffer_tx, ARRAY_SIZE(buffer_tx), "configuration written out"); - - int result = spi_write_dt(&config->bus, &tx); - - if (result != 0) { - LOG_ERR("spi_write failed with error %i", result); - return result; - } - - return 0; -} - -static int bd8lb600fs_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) +static int bd8lb600fs_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, + gpio_flags_t flags) { - struct bd8lb600fs_drv_data *drv_data = dev->data; + const struct bd8lb600fs_gpio_config *config = dev->config; + struct bd8lb600fs_gpio_data *data = dev->data; /* cannot execute a bus operation in an ISR context */ if (k_is_in_isr()) { return -EWOULDBLOCK; } - if (pin >= drv_data->gpios_count_actual) { + if (pin >= config->gpios_count) { LOG_ERR("invalid pin number %i", pin); return -EINVAL; } @@ -140,158 +80,126 @@ static int bd8lb600fs_pin_configure(const struct device *dev, gpio_pin_t pin, gp return -ENOTSUP; } - k_mutex_lock(&drv_data->lock, K_FOREVER); + k_mutex_lock(&data->lock, K_FOREVER); if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) { - WRITE_BIT(drv_data->state, pin, 0); + WRITE_BIT(data->state, pin, 0); } else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) { - WRITE_BIT(drv_data->state, pin, 1); + WRITE_BIT(data->state, pin, 1); } - WRITE_BIT(drv_data->configured, pin, 1); + WRITE_BIT(data->configured, pin, 1); - int result = write_state(dev, drv_data->state); + int result = mfd_bd8lb600fs_set_outputs(config->parent_dev, data->state); - k_mutex_unlock(&drv_data->lock); + k_mutex_unlock(&data->lock); return result; } -static int bd8lb600fs_port_get_raw(const struct device *dev, uint32_t *value) +static int bd8lb600fs_gpio_port_get_raw(const struct device *dev, uint32_t *value) { LOG_ERR("input pins are not available"); return -ENOTSUP; } -static int bd8lb600fs_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value) +static int bd8lb600fs_gpio_port_set_masked_raw(const struct device *dev, uint32_t mask, + uint32_t value) { - struct bd8lb600fs_drv_data *drv_data = dev->data; + const struct bd8lb600fs_gpio_config *config = dev->config; + struct bd8lb600fs_gpio_data *data = dev->data; /* cannot execute a bus operation in an ISR context */ if (k_is_in_isr()) { return -EWOULDBLOCK; } - k_mutex_lock(&drv_data->lock, K_FOREVER); - drv_data->state = (drv_data->state & ~mask) | (mask & value); + k_mutex_lock(&data->lock, K_FOREVER); + data->state = (data->state & ~mask) | (mask & value); - int result = write_state(dev, drv_data->state); + int result = mfd_bd8lb600fs_set_outputs(config->parent_dev, data->state); - k_mutex_unlock(&drv_data->lock); + k_mutex_unlock(&data->lock); return result; } -static int bd8lb600fs_port_set_bits_raw(const struct device *dev, uint32_t mask) +static int bd8lb600fs_gpio_port_set_bits_raw(const struct device *dev, uint32_t mask) { - return bd8lb600fs_port_set_masked_raw(dev, mask, mask); + return bd8lb600fs_gpio_port_set_masked_raw(dev, mask, mask); } -static int bd8lb600fs_port_clear_bits_raw(const struct device *dev, uint32_t mask) +static int bd8lb600fs_gpio_port_clear_bits_raw(const struct device *dev, uint32_t mask) { - return bd8lb600fs_port_set_masked_raw(dev, mask, 0); + return bd8lb600fs_gpio_port_set_masked_raw(dev, mask, 0); } -static int bd8lb600fs_port_toggle_bits(const struct device *dev, uint32_t mask) +static int bd8lb600fs_gpio_port_toggle_bits(const struct device *dev, uint32_t mask) { - struct bd8lb600fs_drv_data *drv_data = dev->data; + const struct bd8lb600fs_gpio_config *config = dev->config; + struct bd8lb600fs_gpio_data *data = dev->data; /* cannot execute a bus operation in an ISR context */ if (k_is_in_isr()) { return -EWOULDBLOCK; } - k_mutex_lock(&drv_data->lock, K_FOREVER); - drv_data->state ^= mask; + k_mutex_lock(&data->lock, K_FOREVER); + data->state ^= mask; - int result = write_state(dev, drv_data->state); + int result = mfd_bd8lb600fs_set_outputs(config->parent_dev, data->state); - k_mutex_unlock(&drv_data->lock); + k_mutex_unlock(&data->lock); return result; } static const struct gpio_driver_api api_table = { - .pin_configure = bd8lb600fs_pin_configure, - .port_get_raw = bd8lb600fs_port_get_raw, - .port_set_masked_raw = bd8lb600fs_port_set_masked_raw, - .port_set_bits_raw = bd8lb600fs_port_set_bits_raw, - .port_clear_bits_raw = bd8lb600fs_port_clear_bits_raw, - .port_toggle_bits = bd8lb600fs_port_toggle_bits, + .pin_configure = bd8lb600fs_gpio_pin_configure, + .port_get_raw = bd8lb600fs_gpio_port_get_raw, + .port_set_masked_raw = bd8lb600fs_gpio_port_set_masked_raw, + .port_set_bits_raw = bd8lb600fs_gpio_port_set_bits_raw, + .port_clear_bits_raw = bd8lb600fs_gpio_port_clear_bits_raw, + .port_toggle_bits = bd8lb600fs_gpio_port_toggle_bits, }; -static int bd8lb600fs_init(const struct device *dev) +static int bd8lb600fs_gpio_init(const struct device *dev) { - const struct bd8lb600fs_config *config = dev->config; - struct bd8lb600fs_drv_data *drv_data = dev->data; - - if (!spi_is_ready_dt(&config->bus)) { - LOG_ERR("SPI bus %s not ready", config->bus.bus->name); - return -ENODEV; - } + const struct bd8lb600fs_gpio_config *config = dev->config; + struct bd8lb600fs_gpio_data *data = dev->data; - if (!gpio_is_ready_dt(&config->gpio_reset)) { - LOG_ERR("%s: reset GPIO is not ready", dev->name); + if (!device_is_ready(config->parent_dev)) { + LOG_ERR("MFD parent is not ready"); return -ENODEV; } - int result = k_mutex_init(&drv_data->lock); + int result = k_mutex_init(&data->lock); if (result != 0) { LOG_ERR("unable to initialize mutex"); return result; } - drv_data->instance_count_actual = config->gpios_count / 8; - - if (config->gpios_count % 8 != 0) { - LOG_ERR("%s: number of GPIOs %i is not a multiple of 8", - dev->name, config->gpios_count); - return -EINVAL; - } - - if (drv_data->instance_count_actual > 4) { - LOG_ERR("%s: only a maximum of 4 devices are supported for the daisy chaining", - dev->name); - return -EINVAL; - } - - drv_data->gpios_count_actual = drv_data->instance_count_actual * 8; - - result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE); - - if (result != 0) { - LOG_ERR("failed to initialize GPIO for reset"); - return result; - } - - k_busy_wait(WAIT_TIME_RESET_ACTIVE_IN_US); - gpio_pin_set_dt(&config->gpio_reset, 0); - k_busy_wait(WAIT_TIME_RESET_INACTIVE_TO_CS_IN_US); - return 0; } -#define BD8LB600FS_INIT(inst) \ - static const struct bd8lb600fs_config bd8lb600fs_##inst##_config = { \ +#define BD8LB600FS_GPIO_INIT(inst) \ + static const struct bd8lb600fs_gpio_config bd8lb600fs_##inst##_config = { \ .common = \ { \ .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \ }, \ - .bus = SPI_DT_SPEC_INST_GET( \ - inst, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \ - .gpio_reset = GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(inst), reset_gpios, 0), \ - .gpios_count = DT_INST_PROP(inst, ngpios), \ + .parent_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \ + .gpios_count = DT_INST_PROP(inst, ngpios), \ }; \ \ - static struct bd8lb600fs_drv_data bd8lb600fs_##inst##_drvdata = { \ + static struct bd8lb600fs_gpio_data bd8lb600fs_##inst##_data = { \ .state = 0x00, \ .configured = 0x00, \ }; \ \ - /* This has to be initialized after the SPI peripheral. */ \ - DEVICE_DT_INST_DEFINE(inst, bd8lb600fs_init, NULL, &bd8lb600fs_##inst##_drvdata, \ + DEVICE_DT_INST_DEFINE(inst, bd8lb600fs_gpio_init, NULL, &bd8lb600fs_##inst##_data, \ &bd8lb600fs_##inst##_config, POST_KERNEL, \ CONFIG_GPIO_BD8LB600FS_INIT_PRIORITY, &api_table); -DT_INST_FOREACH_STATUS_OKAY(BD8LB600FS_INIT) +DT_INST_FOREACH_STATUS_OKAY(BD8LB600FS_GPIO_INIT) diff --git a/drivers/mfd/CMakeLists.txt b/drivers/mfd/CMakeLists.txt index 8c45cb181bf..0b8e4f00304 100644 --- a/drivers/mfd/CMakeLists.txt +++ b/drivers/mfd/CMakeLists.txt @@ -10,3 +10,4 @@ zephyr_library_sources_ifdef(CONFIG_MFD_NPM6001 mfd_npm6001.c) zephyr_library_sources_ifdef(CONFIG_MFD_AXP192 mfd_axp192.c) zephyr_library_sources_ifdef(CONFIG_MFD_AD5592 mfd_ad5592.c) zephyr_library_sources_ifdef(CONFIG_NXP_LP_FLEXCOMM mfd_nxp_lp_flexcomm.c) +zephyr_library_sources_ifdef(CONFIG_MFD_BD8LB600FS mfd_bd8lb600fs.c) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 2ffdcbcca52..238e5645ab0 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -20,6 +20,7 @@ config MFD_INIT_PRIORITY source "drivers/mfd/Kconfig.ad5592" source "drivers/mfd/Kconfig.axp192" +source "drivers/mfd/Kconfig.bd8lb600fs" source "drivers/mfd/Kconfig.max20335" source "drivers/mfd/Kconfig.nct38xx" source "drivers/mfd/Kconfig.npm1300" diff --git a/drivers/mfd/Kconfig.bd8lb600fs b/drivers/mfd/Kconfig.bd8lb600fs new file mode 100644 index 00000000000..4029f1f2e85 --- /dev/null +++ b/drivers/mfd/Kconfig.bd8lb600fs @@ -0,0 +1,11 @@ +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX -License-Identifier: Apache-2.0 + +config MFD_BD8LB600FS + bool "BD8LB600FS low side switch multi-function device driver" + default y + depends on DT_HAS_ROHM_BD8LB600FS_ENABLED + # using select SPI at this point introduces a cyclic dependency + depends on SPI + help + Enable the Rohm BD8LB600FS low side switch multi-function device driver diff --git a/drivers/mfd/mfd_bd8lb600fs.c b/drivers/mfd/mfd_bd8lb600fs.c new file mode 100644 index 00000000000..02e977e702d --- /dev/null +++ b/drivers/mfd/mfd_bd8lb600fs.c @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT rohm_bd8lb600fs + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(rohm_bd8lb600fs, CONFIG_MFD_LOG_LEVEL); + +#define OUTPUT_OFF_WITH_OPEN_LOAD_DETECTION 0b11 +#define OUTPUT_ON 0b10 +#define WAIT_TIME_RESET_ACTIVE_IN_US 1000 +#define WAIT_TIME_RESET_INACTIVE_TO_CS_IN_US 10 + +struct bd8lb600fs_config { + struct spi_dt_spec bus; + const struct gpio_dt_spec gpio_reset; + size_t instance_count; +}; + +struct bd8lb600fs_data { + /* each bit is one output channel, bit 0 = channel 1, ... */ + uint32_t state; + /* each bit defines if an open load was detected, see state */ + uint32_t old; + /* each bit defines if an over current or over temperature was detected, see state */ + uint32_t ocp_or_tsd; + struct k_mutex lock; +}; + +static void bd8lb600fs_fill_tx_buffer(const struct device *dev, uint8_t *buffer, size_t buffer_size) +{ + const struct bd8lb600fs_config *config = dev->config; + struct bd8lb600fs_data *data = dev->data; + uint16_t state_converted = 0; + + LOG_DBG("%s: writing state 0x%08X to BD8LB600FS", dev->name, data->state); + + memset(buffer, 0x00, buffer_size); + + for (size_t j = 0; j < config->instance_count; ++j) { + int instance_position = (config->instance_count - j - 1) * 2; + + state_converted = 0; + + for (size_t i = 0; i < 8; ++i) { + if ((data->state & BIT(i + j * 8)) == 0) { + state_converted |= OUTPUT_OFF_WITH_OPEN_LOAD_DETECTION << (i * 2); + } else { + state_converted |= OUTPUT_ON << (i * 2); + } + } + + LOG_DBG("%s: configuration for instance %zu: %04X (position %i)", dev->name, j, + state_converted, instance_position); + sys_put_be16(state_converted, buffer + instance_position); + } +} + +static void bd8lb600fs_parse_rx_buffer(const struct device *dev, uint8_t *buffer) +{ + const struct bd8lb600fs_config *config = dev->config; + struct bd8lb600fs_data *data = dev->data; + + data->old = 0; + data->ocp_or_tsd = 0; + + for (size_t j = 0; j < config->instance_count; ++j) { + int instance_position = (config->instance_count - j - 1) * 2; + uint16_t current = sys_get_be16(buffer + instance_position); + + for (size_t i = 0; i < 8; ++i) { + if ((BIT(2 * i + 1) & current) != 0) { + WRITE_BIT(data->old, i + j * 8, 1); + } + if ((BIT(2 * i) & current) != 0) { + WRITE_BIT(data->ocp_or_tsd, i + j * 8, 1); + } + } + } + + LOG_DBG("%s: received 0x%08X open load state from BD8LB600FS", dev->name, data->old); + LOG_DBG("%s: received 0x%08X OCP or TSD state from BD8LB600FS", dev->name, + data->ocp_or_tsd); +} + +static int bd8lb600fs_transceive_state(const struct device *dev) +{ + const struct bd8lb600fs_config *config = dev->config; + + uint8_t buffer_tx[8]; + const struct spi_buf tx_buf = { + .buf = buffer_tx, + .len = config->instance_count * sizeof(uint16_t), + }; + const struct spi_buf_set tx = { + .buffers = &tx_buf, + .count = 1, + }; + uint8_t buffer_rx[8]; + const struct spi_buf rx_buf = { + .buf = buffer_rx, + .len = config->instance_count * sizeof(uint16_t), + }; + const struct spi_buf_set rx = { + .buffers = &rx_buf, + .count = 1, + }; + + bd8lb600fs_fill_tx_buffer(dev, buffer_tx, ARRAY_SIZE(buffer_tx)); + + int result = spi_transceive_dt(&config->bus, &tx, &rx); + + if (result != 0) { + LOG_ERR("spi_transceive failed with error %i", result); + return result; + } + + bd8lb600fs_parse_rx_buffer(dev, buffer_rx); + + return 0; +} + +static int bd8lb600fs_write_state(const struct device *dev) +{ + const struct bd8lb600fs_config *config = dev->config; + + uint8_t buffer_tx[8]; + const struct spi_buf tx_buf = { + .buf = buffer_tx, + .len = config->instance_count * sizeof(uint16_t), + }; + const struct spi_buf_set tx = { + .buffers = &tx_buf, + .count = 1, + }; + + bd8lb600fs_fill_tx_buffer(dev, buffer_tx, ARRAY_SIZE(buffer_tx)); + + int result = spi_write_dt(&config->bus, &tx); + + if (result != 0) { + LOG_ERR("spi_transceive failed with error %i", result); + return result; + } + + return 0; +} + +int mfd_bd8lb600fs_set_outputs(const struct device *dev, uint32_t values) +{ + struct bd8lb600fs_data *data = dev->data; + int result; + + k_mutex_lock(&data->lock, K_FOREVER); + data->state = values; + result = bd8lb600fs_write_state(dev); + k_mutex_unlock(&data->lock); + + return result; +} + +int mfd_bd8lb600fs_get_output_diagnostics(const struct device *dev, uint32_t *old, + uint32_t *ocp_or_tsd) +{ + struct bd8lb600fs_data *data = dev->data; + int result; + + k_mutex_lock(&data->lock, K_FOREVER); + result = bd8lb600fs_transceive_state(dev); + *old = data->old; + *ocp_or_tsd = data->ocp_or_tsd; + k_mutex_unlock(&data->lock); + + return result; +} + +static int bd8lb600fs_init(const struct device *dev) +{ + const struct bd8lb600fs_config *config = dev->config; + struct bd8lb600fs_data *data = dev->data; + + if (!spi_is_ready_dt(&config->bus)) { + LOG_ERR("SPI bus %s not ready", config->bus.bus->name); + return -ENODEV; + } + + if (!gpio_is_ready_dt(&config->gpio_reset)) { + LOG_ERR("%s: reset GPIO is not ready", dev->name); + return -ENODEV; + } + + int result = k_mutex_init(&data->lock); + + if (result != 0) { + LOG_ERR("unable to initialize mutex"); + return result; + } + + result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE); + + if (result != 0) { + LOG_ERR("failed to initialize GPIO for reset"); + return result; + } + + k_busy_wait(WAIT_TIME_RESET_ACTIVE_IN_US); + gpio_pin_set_dt(&config->gpio_reset, 0); + k_busy_wait(WAIT_TIME_RESET_INACTIVE_TO_CS_IN_US); + + return 0; +} + +#define BD8LB600FS_INIT(inst) \ + static const struct bd8lb600fs_config bd8lb600fs_##inst##_config = { \ + .bus = SPI_DT_SPEC_INST_GET( \ + inst, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \ + .gpio_reset = GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(inst), reset_gpios, 0), \ + .instance_count = DT_INST_PROP(inst, instance_count), \ + }; \ + \ + static struct bd8lb600fs_data bd8lb600fs_##inst##_data = { \ + .state = 0x00, \ + }; \ + \ + /* This has to be initialized after the SPI peripheral. */ \ + DEVICE_DT_INST_DEFINE(inst, bd8lb600fs_init, NULL, &bd8lb600fs_##inst##_data, \ + &bd8lb600fs_##inst##_config, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \ + NULL); + +DT_INST_FOREACH_STATUS_OKAY(BD8LB600FS_INIT) diff --git a/dts/bindings/gpio/rohm,bd8lb600fs.yaml b/dts/bindings/gpio/rohm,bd8lb600fs-gpio.yaml similarity index 77% rename from dts/bindings/gpio/rohm,bd8lb600fs.yaml rename to dts/bindings/gpio/rohm,bd8lb600fs-gpio.yaml index 205b44ce83b..96c2d2832e9 100644 --- a/dts/bindings/gpio/rohm,bd8lb600fs.yaml +++ b/dts/bindings/gpio/rohm,bd8lb600fs-gpio.yaml @@ -1,5 +1,6 @@ # # Copyright (c) 2022 SILA Embedded Solutions GmbH +# Copyright (c) 2024 SILA Embedded Solutions GmbH # # SPDX-License-Identifier: Apache-2.0 # @@ -9,9 +10,11 @@ description: | Multiple instances may be daisy chained, which can be configured via the number of supported GPIOs. -compatible: "rohm,bd8lb600fs" +compatible: "rohm,bd8lb600fs-gpio" -include: [gpio-controller.yaml, spi-device.yaml] +include: gpio-controller.yaml + +on-bus: bd8lb600fs properties: "#gpio-cells": @@ -20,16 +23,16 @@ properties: ngpios: type: int required: true + enum: + - 8 + - 16 + - 24 + - 32 description: | Number of pins for the expander. This must be a multiple of 8. The number of pins also defines how many devices are daisy chained. Set to 8 for one instance without daisy chaining. - reset-gpios: - type: phandle-array - required: true - description: GPIO for reset - gpio-cells: - pin - flags diff --git a/dts/bindings/mfd/rohm,bd8lb600fs.yaml b/dts/bindings/mfd/rohm,bd8lb600fs.yaml new file mode 100644 index 00000000000..e3122807a48 --- /dev/null +++ b/dts/bindings/mfd/rohm,bd8lb600fs.yaml @@ -0,0 +1,31 @@ +# +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +description: Rohm BD8LB600FS SPI Gpio Expander MFD + +compatible: "rohm,bd8lb600fs" + +include: spi-device.yaml + +bus: bd8lb600fs + +properties: + reset-gpios: + type: phandle-array + required: true + description: GPIO for reset + + instance-count: + type: int + required: true + default: 1 + enum: + - 1 + - 2 + - 3 + - 4 + description: + number of daisy chained instances, defaults to no daisy chaining diff --git a/include/zephyr/drivers/mfd/bd8lb600fs.h b/include/zephyr/drivers/mfd/bd8lb600fs.h new file mode 100644 index 00000000000..1d6c2b17b5d --- /dev/null +++ b/include/zephyr/drivers/mfd/bd8lb600fs.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_BD8LB600FS_H_ +#define ZEPHYR_INCLUDE_DRIVERS_MFD_BD8LB600FS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @defgroup mdf_interface_bd8lb600fs MFD BD8LB600FS interface + * @ingroup mfd_interfaces + * @{ + */ + +/** + * @brief set outputs + * + * @param[in] dev instance of BD8LB600FS MFD + * @param[in] values values for outputs, one bit per output + * + * @retval 0 if successful + */ +int mfd_bd8lb600fs_set_outputs(const struct device *dev, uint32_t values); +/** + * @brief get output diagnostics + * + * Fetch the current diagnostics from all instances, as multiple + * instances might be daisy chained together. Each bit in old + * and ocp_or_tsd corresponds to one output. A set bit means that the + * function is active, therefore either there is an open load, an over + * current or a too high temperature. + * + * OLD - open load + * OCP - over current protection + * TSD - thermal shutdown + * + * @param[in] dev instance of BD8LB600FS MFD + * @param[out] old open load values + * @param[out] ocp_or_tsd over current protection or thermal shutdown values + * + * @retval 0 if successful + */ +int mfd_bd8lb600fs_get_output_diagnostics(const struct device *dev, uint32_t *old, + uint32_t *ocp_or_tsd); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_BD8LB600FS_H_ */ diff --git a/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.conf b/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.conf index 64290a4a491..826107aabc4 100644 --- a/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.conf +++ b/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.conf @@ -1,3 +1,4 @@ CONFIG_ADC=y CONFIG_ADC_ADS114S0X_GPIO=y -CONFIG_ADC_INIT_PRIORITY=80 +CONFIG_ADC_INIT_PRIORITY=81 +CONFIG_GPIO_BD8LB600FS_INIT_PRIORITY=81 diff --git a/tests/drivers/build_all/gpio/app.overlay b/tests/drivers/build_all/gpio/app.overlay index d7de308b2a1..53380f932ca 100644 --- a/tests/drivers/build_all/gpio/app.overlay +++ b/tests/drivers/build_all/gpio/app.overlay @@ -245,12 +245,19 @@ test_spi_bd8lb600fs: bd8lb600fs@2 { compatible = "rohm,bd8lb600fs"; + status = "okay"; spi-max-frequency = <0>; reg = <0x02>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; reset-gpios = <&test_gpio 0 0>; + instance-count = <1>; + + bd8lb600fs_gpio: bd8lb600fs_gpio { + compatible = "rohm,bd8lb600fs-gpio"; + status = "okay"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; }; test_spi_ad5592: ad5592@3 { diff --git a/tests/drivers/build_all/gpio/prj.conf b/tests/drivers/build_all/gpio/prj.conf index 6e24ab48c84..24c22489fbb 100644 --- a/tests/drivers/build_all/gpio/prj.conf +++ b/tests/drivers/build_all/gpio/prj.conf @@ -4,3 +4,4 @@ CONFIG_TEST_USERSPACE=y CONFIG_I2C=y CONFIG_GPIO_PCA95XX_INTERRUPT=y CONFIG_SPI=y +CONFIG_GPIO_BD8LB600FS_INIT_PRIORITY=81 From 4e4049d939eaf573435e4d32c93ff049c15631de Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Wed, 27 Dec 2023 20:44:33 +0100 Subject: [PATCH 0687/2402] drivers: sensor: add diagnostics sensor for BD8LB600FS Implement a sensor for the output diagnostics of the low side switch BD8LB600FS. Signed-off-by: Benedikt Schmidt --- drivers/sensor/CMakeLists.txt | 1 + drivers/sensor/Kconfig | 1 + drivers/sensor/bd8lb600fs/CMakeLists.txt | 5 ++ drivers/sensor/bd8lb600fs/Kconfig | 12 +++ .../bd8lb600fs/bd8lb600fs_diagnostics.c | 77 +++++++++++++++++++ .../bd8lb600fs/bd8lb600fs_diagnostics.h | 23 ++++++ .../sensor/rohm,bd8lb600fs-diagnostics.yaml | 17 ++++ include/zephyr/drivers/sensor/bd8lb600fs.h | 24 ++++++ 8 files changed, 160 insertions(+) create mode 100644 drivers/sensor/bd8lb600fs/CMakeLists.txt create mode 100644 drivers/sensor/bd8lb600fs/Kconfig create mode 100644 drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.c create mode 100644 drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.h create mode 100644 dts/bindings/sensor/rohm,bd8lb600fs-diagnostics.yaml create mode 100644 include/zephyr/drivers/sensor/bd8lb600fs.h diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index d90be761d2f..d6e60d6b380 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -17,6 +17,7 @@ add_subdirectory_ifdef(CONFIG_AMG88XX amg88xx) add_subdirectory_ifdef(CONFIG_AMS_AS5600 ams_as5600) add_subdirectory_ifdef(CONFIG_AMS_IAQ_CORE ams_iAQcore) add_subdirectory_ifdef(CONFIG_APDS9960 apds9960) +add_subdirectory_ifdef(CONFIG_BD8LB600FS_DIAGNOSTICS bd8lb600fs) add_subdirectory_ifdef(CONFIG_BH1750 bh1750) add_subdirectory_ifdef(CONFIG_BMA280 bma280) add_subdirectory_ifdef(CONFIG_BMA4XX bma4xx) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 5f5860543a3..d3957f257b9 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -97,6 +97,7 @@ source "drivers/sensor/amg88xx/Kconfig" source "drivers/sensor/ams_as5600/Kconfig" source "drivers/sensor/ams_iAQcore/Kconfig" source "drivers/sensor/apds9960/Kconfig" +source "drivers/sensor/bd8lb600fs/Kconfig" source "drivers/sensor/bh1750/Kconfig" source "drivers/sensor/bma280/Kconfig" source "drivers/sensor/bma4xx/Kconfig" diff --git a/drivers/sensor/bd8lb600fs/CMakeLists.txt b/drivers/sensor/bd8lb600fs/CMakeLists.txt new file mode 100644 index 00000000000..c1911ec5cc4 --- /dev/null +++ b/drivers/sensor/bd8lb600fs/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(bd8lb600fs_diagnostics.c) diff --git a/drivers/sensor/bd8lb600fs/Kconfig b/drivers/sensor/bd8lb600fs/Kconfig new file mode 100644 index 00000000000..7fcbc2aa03c --- /dev/null +++ b/drivers/sensor/bd8lb600fs/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BD8LB600FS_DIAGNOSTICS + bool "Sensors of BD8LB600FS" + default y + depends on DT_HAS_ROHM_BD8LB600FS_DIAGNOSTICS_ENABLED + select MFD + help + Enable driver for the open load detection, over current + protection and thermal shutdown sensors of the low side + switch BD8LB600FS. diff --git a/drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.c b/drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.c new file mode 100644 index 00000000000..0f062411294 --- /dev/null +++ b/drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT rohm_bd8lb600fs_diagnostics + +#include +#include +#include +#include + +#include "bd8lb600fs_diagnostics.h" + +LOG_MODULE_REGISTER(BD8LB600FS_DIAGNOSTICS, CONFIG_SENSOR_LOG_LEVEL); + +static int bd8lb600fs_diagnostics_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + const struct bd8lb600fs_diagnostics_config *config = dev->config; + struct bd8lb600fs_diagnostics_data *data = dev->data; + + __ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL); + return mfd_bd8lb600fs_get_output_diagnostics(config->parent_dev, &data->old, + &data->ocp_or_tsd); +} + +static int bd8lb600fs_diagnostics_channel_get(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + struct bd8lb600fs_diagnostics_data *data = dev->data; + + switch (chan) { + case SENSOR_CHAN_BD8LB600FS_OPEN_LOAD: + val->val1 = data->old; + val->val2 = 0; + return 0; + case SENSOR_CHAN_BD8LB600FS_OVER_CURRENT_OR_THERMAL_SHUTDOWN: + val->val1 = data->ocp_or_tsd; + val->val2 = 0; + return 0; + default: + LOG_ERR("%s: requesting unsupported channel %i", dev->name, chan); + return -ENOTSUP; + } +} + +static const struct sensor_driver_api bd8lb600fs_diagnostics_driver_api = { + .sample_fetch = bd8lb600fs_diagnostics_sample_fetch, + .channel_get = bd8lb600fs_diagnostics_channel_get, +}; + +static int bd8lb600fs_diagnostics_init(const struct device *dev) +{ + const struct bd8lb600fs_diagnostics_config *config = dev->config; + + if (!device_is_ready(config->parent_dev)) { + LOG_ERR("%s: parent device is not ready", dev->name); + return -ENODEV; + } + + return 0; +} + +#define BD8LB600FS_DIAGNOSTICS_DEFINE(inst) \ + static struct bd8lb600fs_diagnostics_data bd8lb600fs_diagnostics_data_##inst; \ + \ + static const struct bd8lb600fs_diagnostics_config bd8lb600fs_diagnostics_config_##inst = { \ + .parent_dev = DEVICE_DT_GET(DT_PARENT(DT_DRV_INST(inst))), \ + }; \ + \ + SENSOR_DEVICE_DT_INST_DEFINE( \ + inst, bd8lb600fs_diagnostics_init, NULL, &bd8lb600fs_diagnostics_data_##inst, \ + &bd8lb600fs_diagnostics_config_##inst, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, \ + &bd8lb600fs_diagnostics_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(BD8LB600FS_DIAGNOSTICS_DEFINE) diff --git a/drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.h b/drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.h new file mode 100644 index 00000000000..c0d90dfdba0 --- /dev/null +++ b/drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_BD8LB600FS_BD8LB600FS_DIAGNOSTICS_H_ +#define ZEPHYR_DRIVERS_SENSOR_BD8LB600FS_BD8LB600FS_DIAGNOSTICS_H_ + +#include + +struct bd8lb600fs_diagnostics_data { + /* open load detection */ + uint32_t old; + /* over current protection or thermal shutdown*/ + uint32_t ocp_or_tsd; +}; + +struct bd8lb600fs_diagnostics_config { + const struct device *parent_dev; +}; + +#endif /* ZEPHYR_DRIVERS_SENSOR_BD8LB600FS_BD8LB600FS_DIAGNOSTICS_H_ */ diff --git a/dts/bindings/sensor/rohm,bd8lb600fs-diagnostics.yaml b/dts/bindings/sensor/rohm,bd8lb600fs-diagnostics.yaml new file mode 100644 index 00000000000..a7980ab1130 --- /dev/null +++ b/dts/bindings/sensor/rohm,bd8lb600fs-diagnostics.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +description: | + Open load detection, over current protection and thermal shutdown + sensor of the low side switch BD8LB600FS + +compatible: "rohm,bd8lb600fs-diagnostics" + +include: sensor-device.yaml + +on-bus: bd8lb600fs + +properties: + "#sensor-cells": + type: int + const: 0 diff --git a/include/zephyr/drivers/sensor/bd8lb600fs.h b/include/zephyr/drivers/sensor/bd8lb600fs.h new file mode 100644 index 00000000000..ae7679f61db --- /dev/null +++ b/include/zephyr/drivers/sensor/bd8lb600fs.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_BD8LB600FS_H_ +#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_BD8LB600FS_H_ + +#include + +enum sensor_channel_bd8lb600fs { + /** + * Open load detected, + * boolean with one bit per output + */ + SENSOR_CHAN_BD8LB600FS_OPEN_LOAD = SENSOR_ATTR_PRIV_START, + /** + * Over current protection or thermal shutdown, + * boolean with one bit per output + */ + SENSOR_CHAN_BD8LB600FS_OVER_CURRENT_OR_THERMAL_SHUTDOWN, +}; + +#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_BD8LB600FS_H_ */ From b839f411613e500a8d20592d40709d1317feadca Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Mon, 29 Jan 2024 13:04:59 +0100 Subject: [PATCH 0688/2402] tests: drivers: build_all: sensor: add BD8LB600FS diagnostics Add the BD8LB600FS diagnostics sensor driver to the build all tests. Signed-off-by: Benedikt Schmidt --- tests/drivers/build_all/sensor/app.overlay | 3 ++- tests/drivers/build_all/sensor/spi.dtsi | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/tests/drivers/build_all/sensor/app.overlay b/tests/drivers/build_all/sensor/app.overlay index 8128e68b70e..898ae96ec0d 100644 --- a/tests/drivers/build_all/sensor/app.overlay +++ b/tests/drivers/build_all/sensor/app.overlay @@ -125,7 +125,8 @@ <&test_gpio 0 0>, /* 0x27 */ <&test_gpio 0 0>, /* 0x28 */ <&test_gpio 0 0>, /* 0x29 */ - <&test_gpio 0 0>; /* 0x2A */ + <&test_gpio 0 0>, /* 0x2A */ + <&test_gpio 0 0>; /* 0x2B */ #include "spi.dtsi" }; diff --git a/tests/drivers/build_all/sensor/spi.dtsi b/tests/drivers/build_all/sensor/spi.dtsi index 0cbd74e4670..c7edf356893 100644 --- a/tests/drivers/build_all/sensor/spi.dtsi +++ b/tests/drivers/build_all/sensor/spi.dtsi @@ -337,3 +337,18 @@ test_spi_ens160: ens160@2a { spi-max-frequency = <0>; int-gpios = <&test_gpio 0 0>; }; + +test_spi_bd8lb600fs: bd8lb600fs@2b { + compatible = "rohm,bd8lb600fs"; + reg = <0x2b>; + spi-max-frequency = <0>; + reset-gpios = <&test_gpio 0 0>; + instance-count = <1>; + status = "okay"; + + bd8lb600fs_diagnostics: bd8lb600fs_diagnostics { + compatible = "rohm,bd8lb600fs-diagnostics"; + status = "okay"; + #sensor-cells = <0>; + }; +}; From 33c6bdab9ad19d43f468d70f066810850de44463 Mon Sep 17 00:00:00 2001 From: Lauren Murphy Date: Sun, 25 Feb 2024 12:37:26 -0800 Subject: [PATCH 0689/2402] llext: add STT_OBJECT relocation Adds STT_OBJECT relocation. Fixes #67701. Signed-off-by: Lauren Murphy --- subsys/llext/llext.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/subsys/llext/llext.c b/subsys/llext/llext.c index 9af133d6757..aaafe578f14 100644 --- a/subsys/llext/llext.c +++ b/subsys/llext/llext.c @@ -768,7 +768,8 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local return -ENODATA; } } else if (ELF_ST_TYPE(sym.st_info) == STT_SECTION || - ELF_ST_TYPE(sym.st_info) == STT_FUNC) { + ELF_ST_TYPE(sym.st_info) == STT_FUNC || + ELF_ST_TYPE(sym.st_info) == STT_OBJECT) { /* Link address is relative to the start of the section */ link_addr = (uintptr_t)ext->mem[ldr->sect_map[sym.st_shndx]] + sym.st_value; @@ -776,6 +777,7 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local LOG_INF("found section symbol %s addr 0x%lx", name, link_addr); } else { /* Nothing to relocate here */ + LOG_DBG("not relocated"); continue; } From ce243944375e46e94346bfb3dcbe8c499fc4996b Mon Sep 17 00:00:00 2001 From: Lauren Murphy Date: Mon, 11 Mar 2024 13:20:41 -0700 Subject: [PATCH 0690/2402] llext: add object test case Adds a case to the simple llext test testing global non-static object relocation. Signed-off-by: Lauren Murphy --- tests/subsys/llext/simple/CMakeLists.txt | 2 +- tests/subsys/llext/simple/src/object_ext.c | 26 +++++++++++++++++++ .../llext/simple/src/test_llext_simple.c | 5 ++++ 3 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 tests/subsys/llext/simple/src/object_ext.c diff --git a/tests/subsys/llext/simple/CMakeLists.txt b/tests/subsys/llext/simple/CMakeLists.txt index e39f4f89008..4a9f311d8fa 100644 --- a/tests/subsys/llext/simple/CMakeLists.txt +++ b/tests/subsys/llext/simple/CMakeLists.txt @@ -16,7 +16,7 @@ target_include_directories(app PRIVATE ) # generate extension targets foreach extension given by name -foreach(ext_name hello_world logging relative_jump) +foreach(ext_name hello_world logging relative_jump object) set(ext_src ${PROJECT_SOURCE_DIR}/src/${ext_name}_ext.c) set(ext_bin ${ZEPHYR_BINARY_DIR}/${ext_name}.llext) set(ext_inc ${ZEPHYR_BINARY_DIR}/include/generated/${ext_name}.inc) diff --git a/tests/subsys/llext/simple/src/object_ext.c b/tests/subsys/llext/simple/src/object_ext.c new file mode 100644 index 00000000000..dd2f9250228 --- /dev/null +++ b/tests/subsys/llext/simple/src/object_ext.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This code demonstrates object relocation support. + */ + +#include +#include +#include + +/* Test non-static global object relocation */ +int number = 42; +const char *string = "hello"; + +void test_entry(void) +{ + printk("number: %d\n", number); + number = 0; + printk("number, updated: %d\n", number); + printk("string: %s\n", string); +} +LL_EXTENSION_SYMBOL(test_entry); diff --git a/tests/subsys/llext/simple/src/test_llext_simple.c b/tests/subsys/llext/simple/src/test_llext_simple.c index 14d224f4779..dcb31ac9e4a 100644 --- a/tests/subsys/llext/simple/src/test_llext_simple.c +++ b/tests/subsys/llext/simple/src/test_llext_simple.c @@ -152,6 +152,11 @@ static LLEXT_CONST uint8_t relative_jump_ext[] __aligned(4) = { }; LLEXT_LOAD_UNLOAD(relative_jump, true) +static LLEXT_CONST uint8_t object_ext[] __aligned(4) = { + #include "object.inc" +}; +LLEXT_LOAD_UNLOAD(object, true) + /* * Ensure that EXPORT_SYMBOL does indeed provide a symbol and a valid address * to it. From 7bfaca4c58e853efe2368812c43c9d925ea92435 Mon Sep 17 00:00:00 2001 From: Carlo Kirchmeier Date: Wed, 6 Mar 2024 09:48:19 +0100 Subject: [PATCH 0691/2402] net: dns: Add DNS cache for improved performance In order to reduce dns resolve requests when using the dns resolver an optional cache was introduced. This cache retains query requests for the TTL duration and therefore prevents premature refetching of DNS RRs. Signed-off-by: Carlo Kirchmeier --- subsys/net/lib/dns/CMakeLists.txt | 1 + subsys/net/lib/dns/Kconfig | 28 ++++++ subsys/net/lib/dns/dns_cache.c | 162 ++++++++++++++++++++++++++++++ subsys/net/lib/dns/dns_cache.h | 100 ++++++++++++++++++ subsys/net/lib/dns/resolve.c | 40 ++++++-- 5 files changed, 321 insertions(+), 10 deletions(-) create mode 100644 subsys/net/lib/dns/dns_cache.c create mode 100644 subsys/net/lib/dns/dns_cache.h diff --git a/subsys/net/lib/dns/CMakeLists.txt b/subsys/net/lib/dns/CMakeLists.txt index 1dae89ea37d..974e162b4aa 100644 --- a/subsys/net/lib/dns/CMakeLists.txt +++ b/subsys/net/lib/dns/CMakeLists.txt @@ -7,6 +7,7 @@ zephyr_library_sources(dns_pack.c) zephyr_library_sources_ifdef(CONFIG_DNS_RESOLVER resolve.c) zephyr_library_sources_ifdef(CONFIG_DNS_SD dns_sd.c) +zephyr_library_sources_ifdef(CONFIG_DNS_RESOLVER_CACHE dns_cache.c) if(CONFIG_MDNS_RESPONDER) zephyr_library_sources(mdns_responder.c) diff --git a/subsys/net/lib/dns/Kconfig b/subsys/net/lib/dns/Kconfig index 39c74b39941..4503c3e8dc8 100644 --- a/subsys/net/lib/dns/Kconfig +++ b/subsys/net/lib/dns/Kconfig @@ -69,6 +69,14 @@ config DNS_RESOLVER_MAX_SERVERS DNS server is enough. Each connection to DNS server will use one network context. +config DNS_RESOLVER_MAX_QUERY_LEN + int "Max length of a DNS query" + range 1 255 + default 255 + help + Max length of a DNS query that should be looked up including the + trailing 0. So e.g. "example.com" would have a query len of 12. + menuconfig DNS_SERVER_IP_ADDRESSES bool "Set DNS server IP addresses" help @@ -128,6 +136,26 @@ module-str = Log level for DNS resolver module-help = Enables DNS resolver code to output debug messages. source "subsys/net/Kconfig.template.log_config.net" +menuconfig DNS_RESOLVER_CACHE + bool "DNS resolver cache" + help + This option enables the dns resolver cache. DNS queries + will be cached based on TTL and delivered from cache + whenever possible. This reduces network usage. + +if DNS_RESOLVER_CACHE + +config DNS_RESOLVER_CACHE_MAX_ENTRIES + int "Number of cache entries supported by the dns cache" + default 6 + help + This defines how many entries the DNS cache can hold. If + not enough entries for caching are available the oldest + entry gets replaced. Adjusting this value will affect + RAM usage. + +endif # DNS_RESOLVER_CACHE + endif # DNS_RESOLVER config MDNS_RESPONDER diff --git a/subsys/net/lib/dns/dns_cache.c b/subsys/net/lib/dns/dns_cache.c new file mode 100644 index 00000000000..9364189f22e --- /dev/null +++ b/subsys/net/lib/dns/dns_cache.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2024 Endress+Hauser AG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "dns_cache.h" + +LOG_MODULE_REGISTER(net_dns_cache, CONFIG_DNS_RESOLVER_LOG_LEVEL); + +static void dns_cache_clean(struct dns_cache const *cache); + +int dns_cache_flush(struct dns_cache *cache) +{ + k_mutex_lock(cache->lock, K_FOREVER); + for (size_t i = 0; i < cache->size; i++) { + cache->entries[i].in_use = false; + } + k_mutex_unlock(cache->lock); + + return 0; +} + +int dns_cache_add(struct dns_cache *cache, char const *query, struct dns_addrinfo const *addrinfo, + uint32_t ttl) +{ + k_timepoint_t closest_to_expiry = sys_timepoint_calc(K_FOREVER); + size_t index_to_replace = 0; + bool found_empty = false; + + if (cache == NULL || query == NULL || addrinfo == NULL || ttl == 0) { + return -EINVAL; + } + + if (strlen(query) >= CONFIG_DNS_RESOLVER_MAX_QUERY_LEN) { + NET_WARN("Query string to big to be processed %u >= " + "CONFIG_DNS_RESOLVER_MAX_QUERY_LEN", + strlen(query)); + return -EINVAL; + } + + k_mutex_lock(cache->lock, K_FOREVER); + + NET_DBG("Add \"%s\" with TTL %" PRIu32, query, ttl); + + dns_cache_clean(cache); + + for (size_t i = 0; i < cache->size; i++) { + if (!cache->entries[i].in_use) { + index_to_replace = i; + found_empty = true; + break; + } else if (sys_timepoint_cmp(closest_to_expiry, cache->entries[i].expiry) > 0) { + index_to_replace = i; + closest_to_expiry = cache->entries[i].expiry; + } + } + + if (!found_empty) { + NET_DBG("Overwrite \"%s\"", cache->entries[index_to_replace].query); + } + + strncpy(cache->entries[index_to_replace].query, query, + CONFIG_DNS_RESOLVER_MAX_QUERY_LEN - 1); + cache->entries[index_to_replace].data = *addrinfo; + cache->entries[index_to_replace].expiry = sys_timepoint_calc(K_SECONDS(ttl)); + cache->entries[index_to_replace].in_use = true; + + k_mutex_unlock(cache->lock); + + return 0; +} + +int dns_cache_remove(struct dns_cache *cache, char const *query) +{ + NET_DBG("Remove all entries with query \"%s\"", query); + if (strlen(query) >= CONFIG_DNS_RESOLVER_MAX_QUERY_LEN) { + NET_WARN("Query string to big to be processed %u >= " + "CONFIG_DNS_RESOLVER_MAX_QUERY_LEN", + strlen(query)); + return -EINVAL; + } + + k_mutex_lock(cache->lock, K_FOREVER); + + dns_cache_clean(cache); + + for (size_t i = 0; i < cache->size; i++) { + if (cache->entries[i].in_use && strcmp(cache->entries[i].query, query) == 0) { + cache->entries[i].in_use = false; + } + } + + k_mutex_unlock(cache->lock); + + return 0; +} + +int dns_cache_find(struct dns_cache const *cache, const char *query, struct dns_addrinfo *addrinfo, + size_t addrinfo_array_len) +{ + size_t found = 0; + + NET_DBG("Find \"%s\"", query); + if (cache == NULL || query == NULL || addrinfo == NULL || addrinfo_array_len <= 0) { + return -EINVAL; + } + if (strlen(query) >= CONFIG_DNS_RESOLVER_MAX_QUERY_LEN) { + NET_WARN("Query string to big to be processed %u >= " + "CONFIG_DNS_RESOLVER_MAX_QUERY_LEN", + strlen(query)); + return -EINVAL; + } + + k_mutex_lock(cache->lock, K_FOREVER); + + dns_cache_clean(cache); + + for (size_t i = 0; i < cache->size; i++) { + if (!cache->entries[i].in_use) { + continue; + } + if (strcmp(cache->entries[i].query, query) != 0) { + continue; + } + if (found >= addrinfo_array_len) { + NET_WARN("Found \"%s\" but not enough space in provided buffer.", query); + found++; + } else { + addrinfo[found] = cache->entries[i].data; + found++; + NET_DBG("Found \"%s\"", query); + } + } + + k_mutex_unlock(cache->lock); + + if (found > addrinfo_array_len) { + return -ENOSR; + } + + if (found == 0) { + NET_DBG("Could not find \"%s\"", query); + } + return found; +} + +/* Needs to be called when lock is already acquired */ +static void dns_cache_clean(struct dns_cache const *cache) +{ + for (size_t i = 0; i < cache->size; i++) { + if (!cache->entries[i].in_use) { + continue; + } + + if (sys_timepoint_expired(cache->entries[i].expiry)) { + NET_DBG("Remove \"%s\"", cache->entries[i].query); + cache->entries[i].in_use = false; + } + } +} diff --git a/subsys/net/lib/dns/dns_cache.h b/subsys/net/lib/dns/dns_cache.h new file mode 100644 index 00000000000..b389c491713 --- /dev/null +++ b/subsys/net/lib/dns/dns_cache.h @@ -0,0 +1,100 @@ +/** @file + * @brief DNS cache + * + * An cache holding dns records for faster dns resolving. + */ + +/* + * Copyright (c) 2024 Endress+Hauser AG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_NET_DNS_CACHE_H_ +#define ZEPHYR_INCLUDE_NET_DNS_CACHE_H_ + +#include +#include +#include +#include + +struct dns_cache_entry { + char query[CONFIG_DNS_RESOLVER_MAX_QUERY_LEN]; + struct dns_addrinfo data; + k_timepoint_t expiry; + bool in_use; +}; + +struct dns_cache { + size_t size; + struct dns_cache_entry *entries; + struct k_mutex *lock; +}; + +/** + * @brief Statically define and initialize a DNS queue. + * + * The cache can be accessed outside the module where it is defined using: + * + * @code extern struct dns_cache ; @endcode + * + * @param name Name of the cache. + */ +#define DNS_CACHE_DEFINE(name, cache_size) \ + static K_MUTEX_DEFINE(name##_mutex); \ + static struct dns_cache_entry name##_entries[cache_size]; \ + static struct dns_cache name = { \ + .entries = name##_entries, .size = cache_size, .lock = &name##_mutex}; + +/** + * @brief Flushes the dns cache removing all its entries. + * + * @param cache Cache to be flushed + * @retval 0 on success + * @retval On error, a negative value is returned. + */ +int dns_cache_flush(struct dns_cache *cache); + +/** + * @brief Adds a new entry to the dns cache removing the one closest to expiry + * if no free space is available. + * + * @param cache Cache where the entry should be added. + * @param query Query which should be persisted in the cache. + * @param addrinfo Addrinfo resulting from the query which will be returned + * upon cache hit. + * @param ttl Time to live for the entry in seconds. This usually represents + * the TTL of the RR. + * @retval 0 on success + * @retval On error, a negative value is returned. + */ +int dns_cache_add(struct dns_cache *cache, char const *query, struct dns_addrinfo const *addrinfo, + uint32_t ttl); + +/** + * @brief Removes all entries with the given query + * + * @param cache Cache where the entries should be removed. + * @param query Query which should be searched for. + * @retval 0 on success + * @retval On error, a negative value is returned. + */ +int dns_cache_remove(struct dns_cache *cache, char const *query); + +/** + * @brief Tries to find the specified query entry within the cache. + * + * @param cache Cache where the entry should be searched. + * @param query Query which should be searched for. + * @param addrinfo dns_addrinfo array which will be written if the query was found. + * @param addrinfo_array_len Array size of the dns_addrinfo array + * @retval on success the amount of dns_addrinfo written into the addrinfo array will be returned. + * A cache miss will therefore return a 0. + * @retval On error a negative value is returned. + * -ENOSR means there was not enough space in the addrinfo array to accommodate all cache hits the + * array will however be filled with valid data. + */ +int dns_cache_find(struct dns_cache const *cache, const char *query, struct dns_addrinfo *addrinfo, + size_t addrinfo_array_len); + +#endif /* ZEPHYR_INCLUDE_NET_DNS_CACHE_H_ */ diff --git a/subsys/net/lib/dns/resolve.c b/subsys/net/lib/dns/resolve.c index 06aa7e9ef8b..a1e367f5ec5 100644 --- a/subsys/net/lib/dns/resolve.c +++ b/subsys/net/lib/dns/resolve.c @@ -26,6 +26,7 @@ LOG_MODULE_REGISTER(net_dns_resolve, CONFIG_DNS_RESOLVER_LOG_LEVEL); #include #include "dns_pack.h" #include "dns_internal.h" +#include "dns_cache.h" #define DNS_SERVER_COUNT CONFIG_DNS_RESOLVER_MAX_SERVERS #define SERVER_COUNT (DNS_SERVER_COUNT + DNS_MAX_MCAST_SERVERS) @@ -38,14 +39,7 @@ LOG_MODULE_REGISTER(net_dns_resolve, CONFIG_DNS_RESOLVER_LOG_LEVEL); #define DNS_BUF_TIMEOUT K_MSEC(500) /* ms */ -/* RFC 1035, 3.1. Name space definitions - * To simplify implementations, the total length of a domain name (i.e., - * label octets and label length octets) is restricted to 255 octets or - * less. - */ -#define DNS_MAX_NAME_LEN 255 - -#define DNS_QUERY_MAX_SIZE (DNS_MSG_HEADER_SIZE + DNS_MAX_NAME_LEN + \ +#define DNS_QUERY_MAX_SIZE (DNS_MSG_HEADER_SIZE + CONFIG_DNS_RESOLVER_MAX_QUERY_LEN + \ DNS_QTYPE_LEN + DNS_QCLASS_LEN) /* This value is recommended by RFC 1035 */ @@ -71,9 +65,13 @@ LOG_MODULE_REGISTER(net_dns_resolve, CONFIG_DNS_RESOLVER_LOG_LEVEL); NET_BUF_POOL_DEFINE(dns_msg_pool, DNS_RESOLVER_BUF_CTR, DNS_RESOLVER_MAX_BUF_SIZE, 0, NULL); -NET_BUF_POOL_DEFINE(dns_qname_pool, DNS_RESOLVER_BUF_CTR, DNS_MAX_NAME_LEN, +NET_BUF_POOL_DEFINE(dns_qname_pool, DNS_RESOLVER_BUF_CTR, CONFIG_DNS_RESOLVER_MAX_QUERY_LEN, 0, NULL); +#ifdef CONFIG_DNS_RESOLVER_CACHE +DNS_CACHE_DEFINE(dns_cache, CONFIG_DNS_RESOLVER_CACHE_MAX_ENTRIES); +#endif /* CONFIG_DNS_RESOLVER_CACHE */ + static struct dns_resolve_context dns_default_ctx; /* Must be invoked with context lock held */ @@ -635,6 +633,10 @@ int dns_validate_msg(struct dns_resolve_context *ctx, invoke_query_callback(DNS_EAI_INPROGRESS, &info, &ctx->queries[*query_idx]); +#ifdef CONFIG_DNS_RESOLVER_CACHE + dns_cache_add(&dns_cache, + ctx->queries[*query_idx].query, &info, ttl); +#endif /* CONFIG_DNS_RESOLVER_CACHE */ items++; break; @@ -1123,6 +1125,9 @@ int dns_resolve_name(struct dns_resolve_context *ctx, int failure = 0; bool mdns_query = false; uint8_t hop_limit; +#ifdef CONFIG_DNS_RESOLVER_CACHE + struct dns_addrinfo cached_info[CONFIG_DNS_RESOLVER_AI_MAX_ENTRIES] = {0}; +#endif /* CONFIG_DNS_RESOLVER_CACHE */ if (!ctx || !query || !cb) { return -EINVAL; @@ -1184,6 +1189,21 @@ int dns_resolve_name(struct dns_resolve_context *ctx, } try_resolve: +#ifdef CONFIG_DNS_RESOLVER_CACHE + ret = dns_cache_find(&dns_cache, query, cached_info, sizeof(cached_info)); + if (ret > 0) { + /* The query was cached, no + * need to continue further. + */ + for (size_t cache_index = 0; cache_index < ret; cache_index++) { + cb(DNS_EAI_INPROGRESS, &cached_info[cache_index], user_data); + } + cb(DNS_EAI_ALLDONE, NULL, user_data); + + return 0; + } +#endif /* CONFIG_DNS_RESOLVER_CACHE */ + k_mutex_lock(&ctx->lock, K_FOREVER); if (ctx->state != DNS_RESOLVE_CONTEXT_ACTIVE) { @@ -1220,7 +1240,7 @@ int dns_resolve_name(struct dns_resolve_context *ctx, } ret = dns_msg_pack_qname(&dns_qname->len, dns_qname->data, - DNS_MAX_NAME_LEN, ctx->queries[i].query); + CONFIG_DNS_RESOLVER_MAX_QUERY_LEN, ctx->queries[i].query); if (ret < 0) { goto quit; } From 21ce4a271eca01c1297abe66462d67545f76602b Mon Sep 17 00:00:00 2001 From: Carlo Kirchmeier Date: Wed, 6 Mar 2024 09:49:02 +0100 Subject: [PATCH 0692/2402] tests: net: dns: Add DNS cache tests Added tests in order to verify the functionality of the newly added DNS cache. Signed-off-by: Carlo Kirchmeier --- tests/net/lib/dns_cache/CMakeLists.txt | 9 ++ tests/net/lib/dns_cache/prj.conf | 12 +++ tests/net/lib/dns_cache/src/main.c | 135 +++++++++++++++++++++++++ tests/net/lib/dns_cache/testcase.yaml | 11 ++ 4 files changed, 167 insertions(+) create mode 100644 tests/net/lib/dns_cache/CMakeLists.txt create mode 100644 tests/net/lib/dns_cache/prj.conf create mode 100644 tests/net/lib/dns_cache/src/main.c create mode 100644 tests/net/lib/dns_cache/testcase.yaml diff --git a/tests/net/lib/dns_cache/CMakeLists.txt b/tests/net/lib/dns_cache/CMakeLists.txt new file mode 100644 index 00000000000..744013970b5 --- /dev/null +++ b/tests/net/lib/dns_cache/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(dns_cache) + +target_include_directories(app PRIVATE ${ZEPHYR_BASE}/subsys/net/lib/dns) +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/tests/net/lib/dns_cache/prj.conf b/tests/net/lib/dns_cache/prj.conf new file mode 100644 index 00000000000..023d41a029a --- /dev/null +++ b/tests/net/lib/dns_cache/prj.conf @@ -0,0 +1,12 @@ +CONFIG_ZTEST=y + +CONFIG_NETWORKING=y +CONFIG_NET_TEST=y +CONFIG_NET_L2_ETHERNET=n + +CONFIG_MAIN_STACK_SIZE=1344 +CONFIG_DNS_RESOLVER=y +CONFIG_DNS_RESOLVER_CACHE=y + +CONFIG_ENTROPY_GENERATOR=y +CONFIG_TEST_RANDOM_GENERATOR=y diff --git a/tests/net/lib/dns_cache/src/main.c b/tests/net/lib/dns_cache/src/main.c new file mode 100644 index 00000000000..cadb907cf9a --- /dev/null +++ b/tests/net/lib/dns_cache/src/main.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2024 Endress+Hauser AG + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "dns_cache.h" + +#define TEST_DNS_CACHE_SIZE 12 +#define TEST_DNS_CACHE_DEFAULT_TTL 1 +DNS_CACHE_DEFINE(test_dns_cache, TEST_DNS_CACHE_SIZE); + +void clear_cache(void *fixture) +{ + ARG_UNUSED(fixture); + dns_cache_flush(&test_dns_cache); +} + +ZTEST_SUITE(net_dns_cache_test, NULL, NULL, clear_cache, NULL, NULL); + +ZTEST(net_dns_cache_test, test_simple_cache_entry) +{ + struct dns_addrinfo info_write = {.ai_family = AF_INET}; + struct dns_addrinfo info_read = {0}; + const char *query = "example.com"; + + zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write, TEST_DNS_CACHE_DEFAULT_TTL), + "Cache entry adding should work."); + zassert_equal(1, dns_cache_find(&test_dns_cache, query, &info_read, 1)); + zassert_equal(AF_INET, info_read.ai_family); +} + +ZTEST(net_dns_cache_test, test_not_cached) +{ + struct dns_addrinfo info_read = {0}; + const char *query = "example.com"; + + zassert_equal(0, dns_cache_find(&test_dns_cache, query, &info_read, 1)); + zassert_equal(0, info_read.ai_family); +} + +ZTEST(net_dns_cache_test, test_fill_cache) +{ + struct dns_addrinfo info_write = {.ai_family = AF_INET}; + struct dns_addrinfo info_read[TEST_DNS_CACHE_SIZE] = {0}; + const char *query = "example.com"; + + for (size_t i = 0; i < TEST_DNS_CACHE_SIZE; i++) { + zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write, + TEST_DNS_CACHE_DEFAULT_TTL), + "Cache entry adding should work."); + } + zassert_equal(TEST_DNS_CACHE_SIZE, + dns_cache_find(&test_dns_cache, query, info_read, TEST_DNS_CACHE_SIZE)); + zassert_equal(AF_INET, info_read[TEST_DNS_CACHE_SIZE - 1].ai_family); +} + +ZTEST(net_dns_cache_test, test_flush) +{ + struct dns_addrinfo info_write = {.ai_family = AF_INET}; + struct dns_addrinfo info_read[TEST_DNS_CACHE_SIZE] = {0}; + const char *query = "example.com"; + + for (size_t i = 0; i < TEST_DNS_CACHE_SIZE; i++) { + zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write, + TEST_DNS_CACHE_DEFAULT_TTL), + "Cache entry adding should work."); + } + zassert_ok(dns_cache_flush(&test_dns_cache)); + zassert_equal(0, dns_cache_find(&test_dns_cache, query, info_read, TEST_DNS_CACHE_SIZE)); + zassert_equal(0, info_read[TEST_DNS_CACHE_SIZE - 1].ai_family); +} + +ZTEST(net_dns_cache_test, test_fill_cache_to_small) +{ + struct dns_addrinfo info_write = {.ai_family = AF_INET}; + struct dns_addrinfo info_read[TEST_DNS_CACHE_SIZE - 1] = {0}; + const char *query = "example.com"; + + for (size_t i = 0; i < TEST_DNS_CACHE_SIZE; i++) { + zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write, + TEST_DNS_CACHE_DEFAULT_TTL), + "Cache entry adding should work."); + } + zassert_equal(-ENOSR, + dns_cache_find(&test_dns_cache, query, info_read, TEST_DNS_CACHE_SIZE - 1)); + zassert_equal(AF_INET, info_read[TEST_DNS_CACHE_SIZE - 2].ai_family); +} + +ZTEST(net_dns_cache_test, test_closest_expiry_removed) +{ + struct dns_addrinfo info_write = {.ai_family = AF_INET}; + struct dns_addrinfo info_read = {0}; + const char *closest_expiry = "example.com"; + + zassert_ok(dns_cache_add(&test_dns_cache, closest_expiry, &info_write, + TEST_DNS_CACHE_DEFAULT_TTL), + "Cache entry adding should work."); + k_sleep(K_MSEC(1)); + for (size_t i = 0; i < TEST_DNS_CACHE_SIZE; i++) { + zassert_ok(dns_cache_add(&test_dns_cache, "example2.com", &info_write, + TEST_DNS_CACHE_DEFAULT_TTL), + "Cache entry adding should work."); + } + zassert_equal(0, dns_cache_find(&test_dns_cache, closest_expiry, &info_read, 1)); + zassert_equal(0, info_read.ai_family); +} + +ZTEST(net_dns_cache_test, test_expired_entries_removed) +{ + struct dns_addrinfo info_write = {.ai_family = AF_INET}; + struct dns_addrinfo info_read[3] = {0}; + const char *query = "example.com"; + + zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write, TEST_DNS_CACHE_DEFAULT_TTL), + "Cache entry adding should work."); + zassert_ok( + dns_cache_add(&test_dns_cache, query, &info_write, TEST_DNS_CACHE_DEFAULT_TTL * 2), + "Cache entry adding should work."); + zassert_ok( + dns_cache_add(&test_dns_cache, query, &info_write, TEST_DNS_CACHE_DEFAULT_TTL * 3), + "Cache entry adding should work."); + zassert_equal(3, dns_cache_find(&test_dns_cache, query, info_read, 3)); + zassert_equal(AF_INET, info_read[0].ai_family); + k_sleep(K_MSEC(TEST_DNS_CACHE_DEFAULT_TTL * 1000 + 1)); + zassert_equal(2, dns_cache_find(&test_dns_cache, query, info_read, 3)); + zassert_equal(AF_INET, info_read[0].ai_family); + k_sleep(K_MSEC(TEST_DNS_CACHE_DEFAULT_TTL * 1000 + 1)); + zassert_equal(1, dns_cache_find(&test_dns_cache, query, info_read, 3)); + zassert_equal(AF_INET, info_read[0].ai_family); + k_sleep(K_MSEC(1)); + zassert_equal(1, dns_cache_find(&test_dns_cache, query, info_read, 3)); + zassert_equal(AF_INET, info_read[0].ai_family); +} diff --git a/tests/net/lib/dns_cache/testcase.yaml b/tests/net/lib/dns_cache/testcase.yaml new file mode 100644 index 00000000000..a14a8f6fe7d --- /dev/null +++ b/tests/net/lib/dns_cache/testcase.yaml @@ -0,0 +1,11 @@ +common: + tags: + - dns + - net + min_ram: 21 + depends_on: netif + integration_platforms: + - native_sim +tests: + net.dns.cache: + build_only: false From c2179bcef05e0a15f9efe40f96a5e803a05c24c2 Mon Sep 17 00:00:00 2001 From: Jun Lin Date: Tue, 27 Feb 2024 17:03:25 +0800 Subject: [PATCH 0693/2402] soc: npcx: add support for npcx9m7fb Add new SoC npcx9m7fb support for npcx9 series. Signed-off-by: Jun Lin --- dts/arm/nuvoton/npcx9m7fb.dtsi | 42 ++++++++++++++++++++++++++++++ soc/nuvoton/npcx/Kconfig | 2 +- soc/nuvoton/npcx/npcx9/Kconfig.soc | 7 +++++ soc/nuvoton/npcx/soc.yml | 1 + 4 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 dts/arm/nuvoton/npcx9m7fb.dtsi diff --git a/dts/arm/nuvoton/npcx9m7fb.dtsi b/dts/arm/nuvoton/npcx9m7fb.dtsi new file mode 100644 index 00000000000..32a7bfe5792 --- /dev/null +++ b/dts/arm/nuvoton/npcx9m7fb.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2023 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "npcx/npcx9.dtsi" + +/ { + flash0: flash@10070000 { + reg = <0x10070000 DT_SIZE_K(320)>; + }; + + flash1: flash@64000000 { + reg = <0x64000000 DT_SIZE_K(1024)>; + }; + + sram0: memory@200c0000 { + compatible = "mmio-sram"; + reg = <0x200C0000 DT_SIZE_K(64)>; + }; + + soc-id { + device-id = <0x62>; + }; +}; + +&qspi_fiu0 { + int_flash: w25q80@0 { + compatible ="nuvoton,npcx-fiu-nor"; + size = ; + reg = <0>; + status = "okay"; + + /* quad spi bus configuration of nor flash device */ + qspi-flags = ; + mapped-addr = <0x64000000>; + pinctrl-0 = <&int_flash_sl>; + pinctrl-names = "default"; + }; +}; diff --git a/soc/nuvoton/npcx/Kconfig b/soc/nuvoton/npcx/Kconfig index bb3e92738bc..e704cc70a10 100644 --- a/soc/nuvoton/npcx/Kconfig +++ b/soc/nuvoton/npcx/Kconfig @@ -35,7 +35,7 @@ config NPCX_HEADER_CHIP default "npcx7m7" if SOC_NPCX7M7FC default "npcx9m3" if SOC_NPCX9M3F default "npcx9m6" if SOC_NPCX9M6F - default "npcx9m7" if SOC_NPCX9M7F + default "npcx9m7" if SOC_NPCX9M7F || SOC_NPCX9M7FB default "npcx9mfp" if SOC_NPCX9MFP default "npcx4m3" if SOC_NPCX4M3F default "npcx4m8" if SOC_NPCX4M8F diff --git a/soc/nuvoton/npcx/npcx9/Kconfig.soc b/soc/nuvoton/npcx/npcx9/Kconfig.soc index 30f045eb0bf..c7abe79ffd4 100644 --- a/soc/nuvoton/npcx/npcx9/Kconfig.soc +++ b/soc/nuvoton/npcx/npcx9/Kconfig.soc @@ -27,6 +27,12 @@ config SOC_NPCX9M7F help NPCX9M7F +config SOC_NPCX9M7FB + bool + select SOC_SERIES_NPCX9 + help + NPCX9M7FB + config SOC_NPCX9MFP bool select SOC_SERIES_NPCX9 @@ -40,4 +46,5 @@ config SOC default "npcx9m3f" if SOC_NPCX9M3F default "npcx9m6f" if SOC_NPCX9M6F default "npcx9m7f" if SOC_NPCX9M7F + default "npcx9m7fb" if SOC_NPCX9M7FB default "npcx9mfp" if SOC_NPCX9MFP diff --git a/soc/nuvoton/npcx/soc.yml b/soc/nuvoton/npcx/soc.yml index 2aab050969c..55c155a8698 100644 --- a/soc/nuvoton/npcx/soc.yml +++ b/soc/nuvoton/npcx/soc.yml @@ -15,4 +15,5 @@ family: - name: npcx9m3f - name: npcx9m6f - name: npcx9m7f + - name: npcx9m7fb - name: npcx9mfp From 0bf4ec6d7b488e01c0497224ec364596a751d39f Mon Sep 17 00:00:00 2001 From: Jun Lin Date: Tue, 30 Jan 2024 16:33:32 +0800 Subject: [PATCH 0694/2402] drivers: gpio: npcx: workaround both trigger issue for npcx9m7fb Apply the workaround for the issue "MIWU Any Edge Trigger Condition" in the NPCX99nFB_Errata. Signed-off-by: Jun Lin --- drivers/interrupt_controller/Kconfig.npcx | 7 ++ drivers/interrupt_controller/intc_miwu.c | 99 ++++++++++++++++++++++- soc/nuvoton/npcx/common/reg/reg_def.h | 2 + 3 files changed, 105 insertions(+), 3 deletions(-) diff --git a/drivers/interrupt_controller/Kconfig.npcx b/drivers/interrupt_controller/Kconfig.npcx index 514834754e7..d262285bc77 100644 --- a/drivers/interrupt_controller/Kconfig.npcx +++ b/drivers/interrupt_controller/Kconfig.npcx @@ -11,3 +11,10 @@ config NPCX_MIWU This option enables the Multi-Input Wake-Up Unit (MIWU) driver for NPCX family of processors. This is required for GPIO, RTC, LPC/eSPI interrupt support. + +config NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + bool + default y if SOC_NPCX9M7FB + help + Workaround the issue "MIWU Any Edge Trigger Condition" + in the npcx9m7fb SoC errata. diff --git a/drivers/interrupt_controller/intc_miwu.c b/drivers/interrupt_controller/intc_miwu.c index 81c5c515b17..726a2f93345 100644 --- a/drivers/interrupt_controller/intc_miwu.c +++ b/drivers/interrupt_controller/intc_miwu.c @@ -82,6 +82,10 @@ struct intc_miwu_config { struct intc_miwu_data { /* Callback functions list for each MIWU group */ sys_slist_t cb_list_grp[8]; +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + uint8_t both_edge_pins[8]; + struct k_spinlock lock; +#endif }; BUILD_ASSERT(sizeof(struct miwu_io_params) == sizeof(gpio_port_pins_t), @@ -121,6 +125,23 @@ static void intc_miwu_dispatch_isr(sys_slist_t *cb_list, uint8_t mask) } } +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND +static void npcx_miwu_set_pseudo_both_edge(uint8_t table, uint8_t group, uint8_t bit) +{ + const struct intc_miwu_config *config = miwu_devs[table]->config; + const uint32_t base = config->base; + uint8_t pmask = BIT(bit); + + if (IS_BIT_SET(NPCX_WKST(base, group), bit)) { + /* Current signal level is high, set falling edge triger. */ + NPCX_WKEDG(base, group) |= pmask; + } else { + /* Current signal level is low, set rising edge triger. */ + NPCX_WKEDG(base, group) &= ~pmask; + } +} +#endif + static void intc_miwu_isr_pri(int wui_table, int wui_group) { const struct intc_miwu_config *config = miwu_devs[wui_table]->config; @@ -128,10 +149,26 @@ static void intc_miwu_isr_pri(int wui_table, int wui_group) const uint32_t base = config->base; uint8_t mask = NPCX_WKPND(base, wui_group) & NPCX_WKEN(base, wui_group); +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + uint8_t new_mask = mask; + + while (new_mask != 0) { + uint8_t pending_bit = find_lsb_set(new_mask) - 1; + uint8_t pending_mask = BIT(pending_bit); + + NPCX_WKPCL(base, wui_group) = pending_mask; + if ((data->both_edge_pins[wui_group] & pending_mask) != 0) { + npcx_miwu_set_pseudo_both_edge(wui_table, wui_group, pending_bit); + } + + new_mask &= ~pending_mask; + }; +#else /* Clear pending bits before dispatch ISR */ if (mask) { NPCX_WKPCL(base, wui_group) = mask; } +#endif /* Dispatch registered gpio isrs */ intc_miwu_dispatch_isr(&data->cb_list_grp[wui_group], mask); @@ -143,7 +180,21 @@ void npcx_miwu_irq_enable(const struct npcx_wui *wui) const struct intc_miwu_config *config = miwu_devs[wui->table]->config; const uint32_t base = config->base; +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + k_spinlock_key_t key; + struct intc_miwu_data *data = miwu_devs[wui->table]->data; + + key = k_spin_lock(&data->lock); +#endif + NPCX_WKEN(base, wui->group) |= BIT(wui->bit); + +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + if ((data->both_edge_pins[wui->group] & BIT(wui->bit)) != 0) { + npcx_miwu_set_pseudo_both_edge(wui->table, wui->group, wui->bit); + } + k_spin_unlock(&data->lock, key); +#endif } void npcx_miwu_irq_disable(const struct npcx_wui *wui) @@ -182,10 +233,26 @@ bool npcx_miwu_irq_get_and_clear_pending(const struct npcx_wui *wui) { const struct intc_miwu_config *config = miwu_devs[wui->table]->config; const uint32_t base = config->base; +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + k_spinlock_key_t key; + struct intc_miwu_data *data = miwu_devs[wui->table]->data; +#endif + bool pending = IS_BIT_SET(NPCX_WKPND(base, wui->group), wui->bit); if (pending) { +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + key = k_spin_lock(&data->lock); + + NPCX_WKPCL(base, wui->group) = BIT(wui->bit); + + if ((data->both_edge_pins[wui->group] & BIT(wui->bit)) != 0) { + npcx_miwu_set_pseudo_both_edge(wui->table, wui->group, wui->bit); + } + k_spin_unlock(&data->lock, key); +#else NPCX_WKPCL(base, wui->group) = BIT(wui->bit); +#endif } return pending; @@ -197,10 +264,19 @@ int npcx_miwu_interrupt_configure(const struct npcx_wui *wui, const struct intc_miwu_config *config = miwu_devs[wui->table]->config; const uint32_t base = config->base; uint8_t pmask = BIT(wui->bit); + int ret = 0; +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + struct intc_miwu_data *data = miwu_devs[wui->table]->data; + k_spinlock_key_t key; +#endif /* Disable interrupt of wake-up input source before configuring it */ npcx_miwu_irq_disable(wui); +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + key = k_spin_lock(&data->lock); + data->both_edge_pins[wui->group] &= ~BIT(wui->bit); +#endif /* Handle interrupt for level trigger */ if (mode == NPCX_MIWU_MODE_LEVEL) { /* Set detection mode to level */ @@ -215,7 +291,8 @@ int npcx_miwu_interrupt_configure(const struct npcx_wui *wui, NPCX_WKEDG(base, wui->group) |= pmask; break; default: - return -EINVAL; + ret = -EINVAL; + goto early_exit; } /* Handle interrupt for edge trigger */ } else { @@ -234,11 +311,17 @@ int npcx_miwu_interrupt_configure(const struct npcx_wui *wui, break; /* Handle interrupting on both edges */ case NPCX_MIWU_TRIG_BOTH: +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + NPCX_WKAEDG(base, wui->group) &= ~pmask; + data->both_edge_pins[wui->group] |= BIT(wui->bit); +#else /* Enable any edge */ NPCX_WKAEDG(base, wui->group) |= pmask; +#endif break; default: - return -EINVAL; + ret = -EINVAL; + goto early_exit; } } @@ -251,7 +334,17 @@ int npcx_miwu_interrupt_configure(const struct npcx_wui *wui, */ NPCX_WKPCL(base, wui->group) |= pmask; - return 0; +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + if ((data->both_edge_pins[wui->group] & BIT(wui->bit)) != 0) { + npcx_miwu_set_pseudo_both_edge(wui->table, wui->group, wui->bit); + } +#endif + +early_exit: +#ifdef CONFIG_NPCX_MIWU_BOTH_EDGE_TRIG_WORKAROUND + k_spin_unlock(&data->lock, key); +#endif + return ret; } void npcx_miwu_init_gpio_callback(struct miwu_callback *callback, diff --git a/soc/nuvoton/npcx/common/reg/reg_def.h b/soc/nuvoton/npcx/common/reg/reg_def.h index a4a23e543e6..3bcf8d9a0e3 100644 --- a/soc/nuvoton/npcx/common/reg/reg_def.h +++ b/soc/nuvoton/npcx/common/reg/reg_def.h @@ -396,6 +396,8 @@ struct uart_reg { (*(volatile uint8_t *)(base + NPCX_WKINEN_OFFSET(group))) #define NPCX_WKMOD(base, group) \ (*(volatile uint8_t *)(base + NPCX_WKMOD_OFFSET(group))) +#define NPCX_WKST(base, group) \ + (*(volatile uint8_t *)(base + NPCX_WKST_OFFSET(group))) /* * General-Purpose I/O (GPIO) device registers From 0907aff2ae70b88e8a9f0b74b767739eb0029772 Mon Sep 17 00:00:00 2001 From: Jun Lin Date: Tue, 20 Feb 2024 10:16:53 +0800 Subject: [PATCH 0695/2402] soc: npcx: workaround VCC1_RST hang issue for npcx9m7fb SoC Apply the bypass for the issue "Possible Hang-Up After VCC1_RST Reset" in the NPCX99nFB_Errata. Signed-off-by: Jun Lin --- soc/nuvoton/npcx/common/reg/reg_def.h | 8 ++++++++ soc/nuvoton/npcx/npcx9/CMakeLists.txt | 4 ++++ soc/nuvoton/npcx/npcx9/Kconfig.soc | 8 ++++++++ soc/nuvoton/npcx/npcx9/soc.c | 27 +++++++++++++++++++++++++++ 4 files changed, 47 insertions(+) create mode 100644 soc/nuvoton/npcx/npcx9/soc.c diff --git a/soc/nuvoton/npcx/common/reg/reg_def.h b/soc/nuvoton/npcx/common/reg/reg_def.h index 3bcf8d9a0e3..f13dfd507f8 100644 --- a/soc/nuvoton/npcx/common/reg/reg_def.h +++ b/soc/nuvoton/npcx/common/reg/reg_def.h @@ -240,6 +240,14 @@ struct scfg_reg { #define NPCX_LV_GPIO_CTL(base, n) \ (*(volatile uint8_t *)(base + NPCX_LV_GPIO_CTL_OFFSET(n))) +#define NPCX_JEN_CTL1_OFFSET 0x120 +#define NPCX_JEN_CTL1(base) (*(volatile uint8_t *)(base + (NPCX_JEN_CTL1_OFFSET))) + +#define NPCX_JEN_CTL1_JEN_EN FIELD(0, 4) +#define NPCX_JEN_CTL1_JEN_HEN FIELD(4, 4) +#define NPCX_JEN_CTL1_JEN_ENABLE 0x9 +#define NPCX_JEN_CTL1_JEN_DISABLE 0x6 + /* SCFG register fields */ #define NPCX_DEVCNT_F_SPI_TRIS 6 #define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2) diff --git a/soc/nuvoton/npcx/npcx9/CMakeLists.txt b/soc/nuvoton/npcx/npcx9/CMakeLists.txt index 7137403126d..ea6ef98230a 100644 --- a/soc/nuvoton/npcx/npcx9/CMakeLists.txt +++ b/soc/nuvoton/npcx/npcx9/CMakeLists.txt @@ -5,4 +5,8 @@ zephyr_include_directories( ${ZEPHYR_BASE}/drivers ) +zephyr_sources( + soc.c +) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/npcx/npcx9/Kconfig.soc b/soc/nuvoton/npcx/npcx9/Kconfig.soc index c7abe79ffd4..274aaddf1ec 100644 --- a/soc/nuvoton/npcx/npcx9/Kconfig.soc +++ b/soc/nuvoton/npcx/npcx9/Kconfig.soc @@ -48,3 +48,11 @@ config SOC default "npcx9m7f" if SOC_NPCX9M7F default "npcx9m7fb" if SOC_NPCX9M7FB default "npcx9mfp" if SOC_NPCX9MFP + +config NPCX_VCC1_RST_HANG_WORKAROUND + bool + depends on SOC_NPCX9M7FB + default y + help + Workaround the issue "Possible Hang-Up After VCC1_RST Reset" + in the npcx9m7fb SoC errata. diff --git a/soc/nuvoton/npcx/npcx9/soc.c b/soc/nuvoton/npcx/npcx9/soc.c new file mode 100644 index 00000000000..a1427a84088 --- /dev/null +++ b/soc/nuvoton/npcx/npcx9/soc.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +static int soc_npcx9_init(void) +{ + if (IS_ENABLED(CONFIG_NPCX_VCC1_RST_HANG_WORKAROUND)) { + uintptr_t scfg_base = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg); + + SET_FIELD(NPCX_JEN_CTL1(scfg_base), NPCX_JEN_CTL1_JEN_HEN, + NPCX_JEN_CTL1_JEN_DISABLE); + } + + return 0; +} + +SYS_INIT(soc_npcx9_init, PRE_KERNEL_1, 0); From 7dd7175336b9f71cdd53ef3a5fd761c8999e7723 Mon Sep 17 00:00:00 2001 From: Krisna Resi Date: Wed, 13 Mar 2024 15:32:50 +0700 Subject: [PATCH 0696/2402] drivers: rtc: Fix RTC alarm when using both CONFIG_COUNTER and CONFIG_PM It is found that when we use CONFIG_COUNTER and CONFIG_PM concurrently, the RTC alarm callback can be used only once (in some cases, it just won't work at all, e.g., using CONFIG_BT). By set the DBP bit on PWR control register 1 via LL_PWR_EnableBkUpAccess function to temporarily disable write protection every time we assign RTC alarm, we can register alarm callback correctly. Tested on Nucleo WB55RG. Fixes: #68673 Signed-off-by: Krisna Resi --- drivers/counter/counter_ll_stm32_rtc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/counter/counter_ll_stm32_rtc.c b/drivers/counter/counter_ll_stm32_rtc.c index 317bd367391..128586a4a0a 100644 --- a/drivers/counter/counter_ll_stm32_rtc.c +++ b/drivers/counter/counter_ll_stm32_rtc.c @@ -240,6 +240,12 @@ tick_t rtc_stm32_read(const struct device *dev) #endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */ ARG_UNUSED(dev); + /* Enable Backup access */ +#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || \ + defined(PWR_DBPCR_DBP) || defined(PWR_DBPR_DBP) + LL_PWR_EnableBkUpAccess(); +#endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPR_DBP */ + /* Read time and date registers. Make sure value of the previous register * hasn't been changed while reading the next one. */ @@ -295,6 +301,12 @@ tick_t rtc_stm32_read(const struct device *dev) ARG_UNUSED(dev); + /* Enable Backup access */ +#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || \ + defined(PWR_DBPCR_DBP) || defined(PWR_DBPR_DBP) + LL_PWR_EnableBkUpAccess(); +#endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPR_DBP */ + rtc_time = LL_RTC_TIME_Get(RTC); ticks = rtc_time; From 8a0cf76a76df8443aa553cef21b49af8a3fac01c Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Tue, 27 Feb 2024 12:56:37 +0100 Subject: [PATCH 0697/2402] Bluetooth: Controller: Fix Broadcast ISO context get function Fix Broadcast ISO context get function for out-of-bound access. Signed-off-by: Vinayak Kariappa Chettimada --- subsys/bluetooth/controller/ll_sw/ull_adv_iso.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c b/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c index 77e75f66dd4..d4e655fcf0d 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c +++ b/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c @@ -1002,7 +1002,7 @@ static int init_reset(void) static struct ll_adv_iso_set *adv_iso_get(uint8_t handle) { - if (handle >= CONFIG_BT_CTLR_ADV_SET) { + if (handle >= CONFIG_BT_CTLR_ADV_ISO_SET) { return NULL; } From add8f5aba471c879750b6e52afdbe7185d72ce80 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:21 +0800 Subject: [PATCH 0698/2402] dts: binding: gpio: Add kb1200 gpio A new gpio controller addition Signed-off-by: Steven Chang --- dts/bindings/gpio/ene,kb1200-gpio.yaml | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 dts/bindings/gpio/ene,kb1200-gpio.yaml diff --git a/dts/bindings/gpio/ene,kb1200-gpio.yaml b/dts/bindings/gpio/ene,kb1200-gpio.yaml new file mode 100644 index 00000000000..a87d33138db --- /dev/null +++ b/dts/bindings/gpio/ene,kb1200-gpio.yaml @@ -0,0 +1,33 @@ +# Copyright (c) 2023 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: | + ENE KB1200 GPIO(General purpose IO) Port node + + The GPIO controller provides group control of GPIO functions. Each port + group contains 32 pins. GPIO_00~GPIO_1F belong to the Port0 group, + GPIO_20~GPIO_3F belong to the Port1 group, and so on. + + In particular, the 32 pins of the port group do not share the same IRQ + interrupt, but are assigned to two different IRQ interrupts in groups of 16 + pins. This means that single port group provide two interrupt source. + ex.Port0 group GPIO_00~GPIO_0F shares IRQ18, and Port0 group + GPIO_10~GPIO_1F shares IRQ19. + +compatible: "ene,kb1200-gpio" + +include: [gpio-controller.yaml, base.yaml] + +properties: + reg: + required: true + + interrupts: + required: true + + "#gpio-cells": + const: 2 + +gpio-cells: + - pin + - flags From dc9fc3aff12969bd545feca4245da0bc2b129f50 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:24 +0800 Subject: [PATCH 0699/2402] dts: binding: pinctrl: Add kb1200 pinctrl A new pinctrl controller addition Signed-off-by: Steven Chang --- dts/bindings/pinctrl/ene,kb1200-pinctrl.yaml | 86 ++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 dts/bindings/pinctrl/ene,kb1200-pinctrl.yaml diff --git a/dts/bindings/pinctrl/ene,kb1200-pinctrl.yaml b/dts/bindings/pinctrl/ene,kb1200-pinctrl.yaml new file mode 100644 index 00000000000..dbafb47bac2 --- /dev/null +++ b/dts/bindings/pinctrl/ene,kb1200-pinctrl.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: Apache-2.0 + +description: | + The ENE KB1200 pin controller is a singleton node responsible for controlling + pin function selection and pin properties. For example, you can use these + nodes to select peripheral pin functions. + + Here is a list of supported standard pin properties: + - bias-disable: Disable pull-up/down resistor. + - bias-pull-up: Enable pull-up resistor. + - bias-pull-down: Enable pull-down resistor. + - drive-push-pull: Output driver is push-pull. + - drive-open-drain: Output driver is open-drain. + - output-disable: Disable GPIO output driver data + - output-enable: Ensable GPIO output driver data + - output-high: GPIO output data high + - output-low: GPIO output data low + - low-power-enable: Support input data ViH/ViL with low vlotage range(ex. 1.8V domain) + + Here is a list of support pinmux type: + - PINMUX_FUNC_A : GPIO Function + - PINMUX_FUNC_B : AltOutput 1 Function + - PINMUX_FUNC_C : AltOutput 2 Function + - PINMUX_FUNC_D : AltOutput 3 Function + - PINMUX_FUNC_E : AltOutput 4 Function + (Note. Alt-input function does not need to set pinmux type other than PINMUX_FUNC_A) + + An example for KB1200, include the chip level pinctrl DTSI file in the + board level DTS: + + #include + + We want to use the I2C0_0 port of the KB1200 controller and enable the + internal 3.3V pull-up if its i2c frequency won't exceed 400kHz. And we + need to set I2C0_0 pinmux type as PINMUX_FUNC_B (the alt-output 1 + function) not a GPIO. + + To change a pin's pinctrl default properties, add a reference to the + pin in the board's DTS file and set the properties as below: + + &i2c0_0 { + pinctrl-0 = <&i2c0_clk_gpio2c &i2c0_dat_gpio2d>; + pinctrl-names = "default"; + } + + /omit-if-no-ref/ i2c0_clk_gpio2c: i2c0_clk_gpio2c { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c0_dat_gpio2d: i2c0_dat_gpio2d { + pinmux = ; + bias-pull-up; + }; + +compatible: "ene,kb1200-pinctrl" + +include: base.yaml + +properties: + reg: + required: true + +child-binding: + description: | + This binding gives a base representation of the ENE KB1200 pins + configuration + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-pull-down + - bias-pull-up + - drive-push-pull + - drive-open-drain + - output-disable + - output-enable + - output-high + - output-low + - low-power-enable + + properties: + pinmux: + type: int + required: true + description: Pinmux selection From bf644dd5aebbb3a1bf8d809e28cf22819feec946 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:24 +0800 Subject: [PATCH 0700/2402] dts: binding: serial: Add kb1200 uart A new uart controller addition Signed-off-by: Steven Chang --- dts/bindings/serial/ene,kb1200-uart.yaml | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 dts/bindings/serial/ene,kb1200-uart.yaml diff --git a/dts/bindings/serial/ene,kb1200-uart.yaml b/dts/bindings/serial/ene,kb1200-uart.yaml new file mode 100644 index 00000000000..281806030ae --- /dev/null +++ b/dts/bindings/serial/ene,kb1200-uart.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2023 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: ENE KB1200 UART + +compatible: "ene,kb1200-uart" + +include: [uart-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + interrupts: + required: true + + current-speed: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true From a3ac4af848d9e88cb9d155e8267b96b1d1c4b675 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:24 +0800 Subject: [PATCH 0701/2402] dts: binding: misc: Add kb1200 misc A new general configuration addition Signed-off-by: Steven Chang --- dts/bindings/misc/ene,kb1200-gcfg.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 dts/bindings/misc/ene,kb1200-gcfg.yaml diff --git a/dts/bindings/misc/ene,kb1200-gcfg.yaml b/dts/bindings/misc/ene,kb1200-gcfg.yaml new file mode 100644 index 00000000000..a8700fe02f1 --- /dev/null +++ b/dts/bindings/misc/ene,kb1200-gcfg.yaml @@ -0,0 +1,12 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: ENE, General Configuration node + +compatible: "ene,kb1200-gcfg" + +include: [base.yaml] + +properties: + reg: + required: true From 5b4c782bdfd47e93d8d5d64c531ab4cfe5b05792 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:25 +0800 Subject: [PATCH 0702/2402] dts: binding: misc: Add kb1200 pmu A new power manager addition Signed-off-by: Steven Chang --- dts/bindings/misc/ene,kb1200-pmu.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 dts/bindings/misc/ene,kb1200-pmu.yaml diff --git a/dts/bindings/misc/ene,kb1200-pmu.yaml b/dts/bindings/misc/ene,kb1200-pmu.yaml new file mode 100644 index 00000000000..d6516a4e42f --- /dev/null +++ b/dts/bindings/misc/ene,kb1200-pmu.yaml @@ -0,0 +1,12 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: ENE, Power Manager node + +compatible: "ene,kb1200-pmu" + +include: [base.yaml] + +properties: + reg: + required: true From 9897761aa521cb4cd925332df68c6aae5aeebf9e Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:25 +0800 Subject: [PATCH 0703/2402] dts: kb1200 dtsi Add dtsi for ENE KB1200 Signed-off-by: Steven Chang --- dts/arm/ene/kb1200.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 dts/arm/ene/kb1200.dtsi diff --git a/dts/arm/ene/kb1200.dtsi b/dts/arm/ene/kb1200.dtsi new file mode 100644 index 00000000000..f977d871a53 --- /dev/null +++ b/dts/arm/ene/kb1200.dtsi @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m4"; + reg = <0>; + clock-frequency = ; + }; + }; + + sram0: memory@20040000 { + compatible = "mmio-sram"; + reg = <0x20040000 0x10000>; + }; + + soc { + flash-controller@50100000 { + compatible = "ene,kb1200-flash-controller"; + reg = <0x50100000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@10000000 { + compatible = "soc-nv-flash"; + reg = <0x10000000 0x40000>; + }; + }; + + pmu: pmu@40010000 { + compatible = "ene,kb1200-pmu"; + reg = <0x40010000 0x100>; + }; + + gcfg: gcfg@40000000 { + compatible = "ene,kb1200-gcfg"; + reg = <0x40000000 0x100>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; From 388091a4afbbb142fb5cb146ddf60015be046c75 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:26 +0800 Subject: [PATCH 0704/2402] soc: kb1200 soc Add support for ENE KB1200 SOC Signed-off-by: Steven Chang --- soc/ene/kb1200/CMakeLists.txt | 7 ++ soc/ene/kb1200/Kconfig | 9 +++ soc/ene/kb1200/Kconfig.defconfig | 18 +++++ soc/ene/kb1200/Kconfig.soc | 10 +++ soc/ene/kb1200/reg/adc.h | 32 ++++++++ soc/ene/kb1200/reg/fsmbm.h | 125 +++++++++++++++++++++++++++++++ soc/ene/kb1200/reg/gcfg.h | 55 ++++++++++++++ soc/ene/kb1200/reg/gpio.h | 55 ++++++++++++++ soc/ene/kb1200/reg/gptd.h | 28 +++++++ soc/ene/kb1200/reg/pmu.h | 45 +++++++++++ soc/ene/kb1200/reg/pwm.h | 40 ++++++++++ soc/ene/kb1200/reg/ser.h | 58 ++++++++++++++ soc/ene/kb1200/reg/tacho.h | 39 ++++++++++ soc/ene/kb1200/reg/wdt.h | 41 ++++++++++ soc/ene/kb1200/soc.c | 49 ++++++++++++ soc/ene/kb1200/soc.h | 12 +++ soc/ene/kb1200/soc.yml | 2 + 17 files changed, 625 insertions(+) create mode 100644 soc/ene/kb1200/CMakeLists.txt create mode 100644 soc/ene/kb1200/Kconfig create mode 100644 soc/ene/kb1200/Kconfig.defconfig create mode 100644 soc/ene/kb1200/Kconfig.soc create mode 100644 soc/ene/kb1200/reg/adc.h create mode 100644 soc/ene/kb1200/reg/fsmbm.h create mode 100644 soc/ene/kb1200/reg/gcfg.h create mode 100644 soc/ene/kb1200/reg/gpio.h create mode 100644 soc/ene/kb1200/reg/gptd.h create mode 100644 soc/ene/kb1200/reg/pmu.h create mode 100644 soc/ene/kb1200/reg/pwm.h create mode 100644 soc/ene/kb1200/reg/ser.h create mode 100644 soc/ene/kb1200/reg/tacho.h create mode 100644 soc/ene/kb1200/reg/wdt.h create mode 100644 soc/ene/kb1200/soc.c create mode 100644 soc/ene/kb1200/soc.h create mode 100644 soc/ene/kb1200/soc.yml diff --git a/soc/ene/kb1200/CMakeLists.txt b/soc/ene/kb1200/CMakeLists.txt new file mode 100644 index 00000000000..8fbefde1116 --- /dev/null +++ b/soc/ene/kb1200/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2023 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(soc.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ene/kb1200/Kconfig b/soc/ene/kb1200/Kconfig new file mode 100644 index 00000000000..102065edeb8 --- /dev/null +++ b/soc/ene/kb1200/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_KB1200 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU diff --git a/soc/ene/kb1200/Kconfig.defconfig b/soc/ene/kb1200/Kconfig.defconfig new file mode 100644 index 00000000000..cb52d61d806 --- /dev/null +++ b/soc/ene/kb1200/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2023 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_KB1200 + +config NUM_IRQS + default 64 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config BUILD_OUTPUT_BIN + default y + +config BUILD_OUTPUT_HEX + default y + +endif # SOC_KB1200 diff --git a/soc/ene/kb1200/Kconfig.soc b/soc/ene/kb1200/Kconfig.soc new file mode 100644 index 00000000000..4648e79748a --- /dev/null +++ b/soc/ene/kb1200/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_KB1200 + bool + help + ENE KB1200 + +config SOC + default "kb1200" if SOC_KB1200 diff --git a/soc/ene/kb1200/reg/adc.h b/soc/ene/kb1200/reg/adc.h new file mode 100644 index 00000000000..86802f67e8e --- /dev/null +++ b/soc/ene/kb1200/reg/adc.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ENE_KB1200_ADC_H +#define ENE_KB1200_ADC_H + +/** + * Structure type to access Analog to Digital Converter (ADC). + */ +struct adc_regs { + volatile uint32_t ADCCFG; /* Configuration Register */ + volatile uint32_t Reserved[3]; /* Reserved */ + volatile uint32_t ADCDAT[14]; /* Data Register */ +}; + +#define ADC_CHANNEL_BIT_POS 16 +#define ADC_CHANNEL_BIT_MASK 0x3FFF0000 + +#define ADC_RESOLUTION 10 /* Unit:bits */ +#define ADC_VREF_ANALOG 3300 /* Unit:mV */ +#define ADC_MAX_CHAN 14 + +#define ADC_FUNCTION_ENABLE 0x0001 +#define ADC_INVALID_VALUE 0x8000 + +#define ADC_WAIT_TIME 100 +#define ADC_WAIT_CNT 100 + +#endif /* ENE_KB1200_ADDA_H */ diff --git a/soc/ene/kb1200/reg/fsmbm.h b/soc/ene/kb1200/reg/fsmbm.h new file mode 100644 index 00000000000..33f96ae0c0e --- /dev/null +++ b/soc/ene/kb1200/reg/fsmbm.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2024 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ENE_KB1200_FSMBM_H +#define ENE_KB1200_FSMBM_H + +/** + * Structure type to access Flexible SMBus Master (FSMBM). + */ +struct fsmbm_regs { + volatile uint32_t FSMBMCFG; /* Configuration Register */ + volatile uint8_t FSMBMIE; /* Interrupt Enable Register */ + volatile uint8_t Reserved0[3]; + volatile uint8_t FSMBMPF; /* Event Pending Flag Register */ + volatile uint8_t Reserved1[3]; + volatile uint8_t FSMBMFRT; /* Protocol Control Register */ + volatile uint8_t Reserved2[3]; + volatile uint16_t FSMBMPEC; /* PEC Value Register */ + volatile uint16_t Reserved3; + volatile uint8_t FSMBMSTS; /* Status Register */ + volatile uint8_t Reserved4[3]; + volatile uint8_t FSMBMADR; /* Slave Address Register */ + volatile uint8_t Reserved5[3]; + volatile uint8_t FSMBMCMD; /* Command Register */ + volatile uint8_t Reserved6[3]; + volatile uint8_t FSMBMDAT[32]; /* Data Register */ + volatile uint8_t FSMBMPRTC_P; /* Protocol Register */ + volatile uint8_t FSMBMPRTC_C; /* Protocol Register */ + volatile uint16_t Reserved7; + volatile uint8_t FSMBMNADR; /* HostNotify Slave Address Register */ + volatile uint8_t Reserved8[3]; + volatile uint16_t FSMBMNDAT; /* HostNotify Data Register */ + volatile uint16_t Reserved9; +}; + +#define FSMBM_NUM 10 + +/* data->state */ +#define STATE_IDLE 0 +#define STATE_SENDING 1 +#define STATE_RECEIVING 2 +#define STATE_COMPLETE 3 + +/* PROTOCOL */ +#define FLEXIBLE_PROTOCOL 0x7F + +/* Error code */ +#define FSMBM_NO_ERROR 0x00 +#define FSMBM_DEVICE_ADDR_NO_ACK 0x10 +#define FSMBM_CMD_NO_ACK 0x12 +#define FSMBM_DEVICE_DATA_NO_ACK 0x13 +#define FSMBM_LOST_ARBITRATION 0x17 +#define FSMBM_SMBUS_TIMEOUT 0x18 +#define FSMBM_UNSUPPORTED_PRTC 0x19 +#define FSMBM_SMBUS_BUSY 0x1A +#define FSMBM_STOP_FAIL 0x1E +#define FSMBM_PEC_ERROR 0x1F +/* Packet Form */ +#define ___NONE 0x00 +#define ___STOP 0x01 +#define __PEC_ 0x02 +#define __PEC_STOP 0x03 +#define _CNT__ 0x04 +#define _CNT__STOP 0x05 +#define _CNT_PEC_ 0x06 +#define _CNT_PEC_STOP 0x07 +#define CMD___ 0x08 +#define CMD___STOP 0x09 +#define CMD__PEC_ 0x0A +#define CMD__PEC_STOP 0x0B +#define CMD_CNT__ 0x0C +#define CMD_CNT__STOP 0x0D +#define CMD_CNT_PEC_ 0x0E +#define CMD_CNT_PEC_STOP 0x0F + +#define FLEXIBLE_CMD 0x08 +#define FLEXIBLE_CNT 0x04 +#define FLEXIBLE_PEC 0x02 +#define FLEXIBLE_STOP 0x01 +/* HW */ +#define FSMBM_BUFFER_SIZE 0x20 +#define FSMBM_MAXCNT 0xFF + +#define FSMBM_WRITE 0x00 +#define FSMBM_READ 0x01 + +/* Clock Setting = 1 / (1u + (1u * N)) ,50% Duty Cycle */ +#define FSMBM_CLK_1M 0x0000 +#define FSMBM_CLK_500K 0x0101 +#define FSMBM_CLK_333K 0x0202 +#define FSMBM_CLK_250K 0x0303 +#define FSMBM_CLK_200K 0x0404 +#define FSMBM_CLK_167K 0x0505 +#define FSMBM_CLK_143K 0x0606 +#define FSMBM_CLK_125K 0x0707 +#define FSMBM_CLK_111K 0x0808 +#define FSMBM_CLK_100K 0x0909 +#define FSMBM_CLK_91K 0x0A0A +#define FSMBM_CLK_83K 0x0B0B +#define FSMBM_CLK_71K 0x0D0D +#define FSMBM_CLK_63K 0x0F0F +#define FSMBM_CLK_50K 0x1313 +#define FSMBM_CLK_40K 0x1818 +#define FSMBM_CLK_30K 0x2020 +#define FSMBM_CLK_20K 0x3131 +#define FSMBM_CLK_10K 0x6363 +/* Other(non 50% Duty Cycle) */ +#define FSMBM_CLK_400K 0x0102 + +#define FSMBM_COMPLETE_EVENT 0x01 +#define FSMBM_HOST_NOTIFY_EVENT 0x02 +#define FSMBM_BLOCK_FINISH_EVENT 0x04 + +#define FSMBM_FUNCTION_ENABLE 0x01 +#define FSMBM_TIMEOUT_ENABLE 0x02 +#define FSMBM_HW_RESET 0x10 + +#define FSMBM_CLK_POS 16 +#define FSMBM_CLK_MASK 0xFFFF +#define FSMBM_STS_MASK 0x1F + +#endif /* ENE_KB1200_FSMBM_H */ diff --git a/soc/ene/kb1200/reg/gcfg.h b/soc/ene/kb1200/reg/gcfg.h new file mode 100644 index 00000000000..8e1c0224c5d --- /dev/null +++ b/soc/ene/kb1200/reg/gcfg.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ENE_KB1200_GCFG_H +#define ENE_KB1200_GCFG_H + +/** + * Structure type to access General Configuration (GCFG). + */ +struct gcfg_regs { + volatile uint8_t IDV; /*Version ID Register */ + volatile uint8_t Reserved0; /*Reserved */ + volatile uint16_t IDC; /*Chip ID Register */ + volatile uint32_t FWID; /*Firmware ID Register */ + volatile uint32_t MCURST; /*MCU Reset Control Register */ + volatile uint32_t RSTFLAG; /*Reset Pending Flag Register */ + volatile uint32_t GPIOALT; /*GPIO Alternate Register */ + volatile uint8_t VCCSTA; /*VCC Status Register */ + volatile uint8_t Reserved1[3]; /*Reserved */ + volatile uint16_t GPIOMUX; /*GPIO MUX Control Register */ + volatile uint16_t Reserved2; /*Reserved */ + volatile uint16_t I2CSPMS; /*I2CS Pin Map Selection Register */ + volatile uint16_t Reserved3; /*Reserved */ + volatile uint8_t CLKCFG; /*Clock Configuration Register */ + volatile uint8_t Reserved4[3]; /*Reserved */ + volatile uint32_t DPLLFREQ; /*DPLL Frequency Register */ + volatile uint32_t Reserved5; /*Reserved */ + volatile uint32_t GCFGMISC; /*Misc. Register */ + volatile uint8_t EXTIE; /*Extended Command Interrupt Enable Register */ + volatile uint8_t Reserved6[3]; /*Reserved */ + volatile uint8_t EXTPF; /*Extended Command Pending Flag Register */ + volatile uint8_t Reserved7[3]; /*Reserved */ + volatile uint32_t EXTARG; /*Extended Command Argument0/1/2 Register */ + volatile uint8_t EXTCMD; /*Extended Command Port Register */ + volatile uint8_t Reserved8[3]; /*Reserved */ + volatile uint32_t ADCOTR; /*ADCO Register */ + volatile uint32_t IDSR; /*IDSR Register */ + volatile uint32_t Reserved9[14]; /*Reserved */ + volatile uint32_t TRAPMODE; + volatile uint32_t CLK1UCFG; + volatile uint32_t LDO15TRIM; + volatile uint32_t Reserved10; + volatile uint32_t WWTR; + volatile uint32_t ECMISC2; + volatile uint32_t DPLLCTRL; +}; + +#define GCFG_CLKCFG_96M 0x00000004 +#define GCFG_CLKCFG_48M 0x00000014 +#define GCFG_CLKCFG_24M 0x00000024 + +#endif /* ENE_KB1200_GCFG_H */ diff --git a/soc/ene/kb1200/reg/gpio.h b/soc/ene/kb1200/reg/gpio.h new file mode 100644 index 00000000000..559d29e459a --- /dev/null +++ b/soc/ene/kb1200/reg/gpio.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ENE_KB1200_GPIO_H +#define ENE_KB1200_GPIO_H + +/** + * Structure type to access General Purpose Input/Output (GPIO). + */ +struct gpio_regs { + volatile uint32_t GPIOFS; /*Function Selection Register */ + volatile uint32_t Reserved1[3]; + volatile uint32_t GPIOOE; /*Output Enable Register */ + volatile uint32_t Reserved2[3]; + volatile uint32_t GPIOD; /*Output Data Register */ + volatile uint32_t Reserved3[3]; + volatile uint32_t GPIOIN; /*Input Data Register */ + volatile uint32_t Reserved4[3]; + volatile uint32_t GPIOPU; /*Pull Up Register */ + volatile uint32_t Reserved5[3]; + volatile uint32_t GPIOOD; /*Open Drain Register */ + volatile uint32_t Reserved6[3]; + volatile uint32_t GPIOIE; /*Input Enable Register */ + volatile uint32_t Reserved7[3]; + volatile uint32_t GPIODC; /*Driving Control Register */ + volatile uint32_t Reserved8[3]; + volatile uint32_t GPIOLV; /*Low Voltage Mode Enable Register */ + volatile uint32_t Reserved9[3]; + volatile uint32_t GPIOPD; /*Pull Down Register */ + volatile uint32_t Reserved10[3]; + volatile uint32_t GPIOFL; /*Function Lock Register */ + volatile uint32_t Reserved11[3]; +}; + +#define NUM_KB1200_GPIO_PORTS 4 + +/*-- Constant Define --------------------------------------------*/ +#define GPIO00_PWMLED0_PWM8 0x00 +#define GPIO01_SERRXD1_UARTSIN 0x01 +#define GPIO03_SERTXD1_UARTSOUT 0x03 +#define GPIO22_ESBDAT_PWM9 0x22 +#define GPIO28_32KOUT_SERCLK2 0x28 +#define GPIO36_UARTSOUT_SERTXD2 0x36 +#define GPIO5C_KSO6_P80DAT 0x5C +#define GPIO5D_KSO7_P80CLK 0x5D +#define GPIO5E_KSO8_SERRXD1 0x5E +#define GPIO5F_KSO9_SERTXD1 0x5F +#define GPIO71_SDA8_UARTRTS 0x71 +#define GPIO38_SCL4_PWM1 0x38 + + +#endif /* ENE_KB1200_GPIO_H */ diff --git a/soc/ene/kb1200/reg/gptd.h b/soc/ene/kb1200/reg/gptd.h new file mode 100644 index 00000000000..cbc9e92cac3 --- /dev/null +++ b/soc/ene/kb1200/reg/gptd.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ENE_KB1200_GPTD_H +#define ENE_KB1200_GPTD_H + +/** + * Structure type to access GPIO Trigger Detector (GPTD). + */ +struct gptd_regs { + volatile uint32_t GPTDIE; /*Interrupt Enable Register */ + volatile uint32_t Reserved1[3]; + volatile uint32_t GPTDPF; /*Event Pending Flag Register */ + volatile uint32_t Reserved2[3]; + volatile uint32_t GPTDCHG; /*Change Trigger Register */ + volatile uint32_t Reserved3[3]; + volatile uint32_t GPTDEL; /*Level/Edge Trigger Register */ + volatile uint32_t Reserved4[3]; + volatile uint32_t GPTDPS; /*Polarity Selection Register */ + volatile uint32_t Reserved5[3]; + volatile uint32_t GPTDWE; /*WakeUP Enable Register */ + volatile uint32_t Reserved6[3]; +}; + +#endif /* ENE_KB1200_GPTD_H */ diff --git a/soc/ene/kb1200/reg/pmu.h b/soc/ene/kb1200/reg/pmu.h new file mode 100644 index 00000000000..413e4a50f8e --- /dev/null +++ b/soc/ene/kb1200/reg/pmu.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ENE_KB1200_PMU_H +#define ENE_KB1200_PMU_H + +/** + * Structure type to access Power Management Unit (PMU). + */ +struct pmu_regs { + volatile uint8_t PMUIDLE; /*IDLE wakeup by Interrupt Register */ + volatile uint8_t Reserved0[3]; /*Reserved */ + volatile uint32_t PMUSTOP; /*STOP Wakeup Source Register */ + volatile uint8_t PMUSTOPC; /*STOP Control Register */ + volatile uint8_t Reserved1[3]; /*Reserved */ + volatile uint8_t PMUCTRL; /*Control Register */ + volatile uint8_t Reserved2[3]; /*Reserved */ + volatile uint8_t PMUSTAF; /*Status Flag */ + volatile uint8_t Reserved3[3]; /*Reserved */ +}; + +/* STOP Wakeup Source */ +#define PMU_STOP_WU_GPTD 0x00000001 +#define PMU_STOP_WU_VC0 0x00000002 +#define PMU_STOP_WU_VC1 0x00000004 +#define PMU_STOP_WU_IKB 0x00000010 +#define PMU_STOP_WU_WDT 0x00000100 +#define PMU_STOP_WU_HIBTMR 0x00000400 +#define PMU_STOP_WU_eSPI 0x00010000 +#define PMU_STOP_WU_SPIS 0x00010000 +#define PMU_STOP_WU_I2CD32 0x00020000 +#define PMU_STOP_WU_EDI32 0x00040000 +#define PMU_STOP_WU_SWD 0x00080000 +#define PMU_STOP_WU_ITIM 0x00100000 +#define PMU_STOP_WU_I2CS0 0x01000000 +#define PMU_STOP_WU_I2CS1 0x02000000 +#define PMU_STOP_WU_I2CS2 0x04000000 +#define PMU_STOP_WU_I2CS3 0x08000000 + +#define PMU_IDLE_WU_ENABLE 0x00000001 + +#endif /* ENE_KB1200_PMU_H */ diff --git a/soc/ene/kb1200/reg/pwm.h b/soc/ene/kb1200/reg/pwm.h new file mode 100644 index 00000000000..23a0b70e37a --- /dev/null +++ b/soc/ene/kb1200/reg/pwm.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ENE_KB1200_PWM_H +#define ENE_KB1200_PWM_H + +/** + * Structure type to access Pulse Width Modulation (PWM). + */ +struct pwm_regs { + volatile uint16_t PWMCFG; /*Configuration Register */ + volatile uint16_t Reserved0; /*Reserved */ + volatile uint16_t PWMHIGH; /*High Length Register */ + volatile uint16_t Reserved1; /*Reserved */ + volatile uint16_t PWMCYC; /*Cycle Length Register */ + volatile uint16_t Reserved2; /*Reserved */ + volatile uint32_t PWMCHC; /*Current High/Cycle Length Register */ +}; + +#define PWM_SOURCE_CLK_32M 0x0000 +#define PWM_SOURCE_CLK_1M 0x4000 +#define PWM_SOURCE_CLK_32_768K 0x8000 + +#define PWM_PRESCALER_BIT_S 8 + +#define PWM_RULE0 0x0000 +#define PWM_RULE1 0x0080 + +#define PWM_PUSHPULL 0x0000 +#define PWM_OPENDRAIN 0x0002 +#define PWM_ENABLE 0x0001 + +#define PWM_INPUT_FREQ_HI 32000000u +#define PWM_MAX_PRESCALER (1UL << (6)) +#define PWM_MAX_CYCLES (1UL << (14)) + +#endif /* ENE_KB1200_PWM_H */ diff --git a/soc/ene/kb1200/reg/ser.h b/soc/ene/kb1200/reg/ser.h new file mode 100644 index 00000000000..33570aaaf5b --- /dev/null +++ b/soc/ene/kb1200/reg/ser.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ENE_KB1200_SER_H +#define ENE_KB1200_SER_H + +/** + * Structure type to access Serial Port Interface (SER). + */ +struct serial_regs { + volatile uint32_t SERCFG; /*Configuration Register */ + volatile uint32_t SERIE; /*Interrupt Enable Register */ + volatile uint32_t SERPF; /*Pending flag Register */ + volatile uint32_t SERSTS; /*Status Register */ + volatile uint32_t SERRBUF; /*Rx Data Buffer Register */ + volatile uint32_t SERTBUF; /*Tx Data Buffer Register */ + volatile uint32_t SERCTRL; /*Control Register */ +}; + +#define DIVIDER_BASE_CLK 24000000 + +#define SERCTRL_MODE0 0 /* shift */ +#define SERCTRL_MODE1 1 /* 8-bit */ +#define SERCTRL_MODE2 2 /* 9-bit */ +#define SERCTRL_MODE3 3 /* 9-bit */ + +#define SERCFG_RX_ENABLE 0x01 +#define SERCFG_TX_ENABLE 0x02 + +#define SERCFG_PARITY_NONE 0 +#define SERCFG_PARITY_ODD 1 +#define SERCFG_PARITY_EVEN 3 + +/* Pending Flag */ +#define SERPF_RX_CNT_FULL 0x01 +#define SERPF_TX_EMPTY 0x02 +#define SERPF_RX_ERROR 0x04 + +/* Interrupt Enable */ +#define SERIE_RX_ENABLE 0x01 +#define SERIE_TX_ENABLE 0x02 +#define SERIE_RX_ERROR 0x04 + +/* Status Flag */ +#define SERSTS_FRAME_ERROR 0x0200 +#define SERSTS_PARITY_ERROR 0x0100 +#define SERSTS_RX_TIMEOUT 0x0080 +#define SERSTS_RX_BUSY 0x0040 +#define SERSTS_RX_OVERRUN 0x0020 +#define SERSTS_RX_EMPTY 0x0010 +#define SERSTS_TX_BUSY 0x0004 +#define SERSTS_TX_OVERRUN 0x0002 +#define SERSTS_TX_FULL 0x0001 + +#endif /* ENE_KB1200_SER_H */ diff --git a/soc/ene/kb1200/reg/tacho.h b/soc/ene/kb1200/reg/tacho.h new file mode 100644 index 00000000000..bfa7c6fa0e0 --- /dev/null +++ b/soc/ene/kb1200/reg/tacho.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2024 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ENE_KB1200_TACHO_H +#define ENE_KB1200_TACHO_H + +/** + * brief Structure type to access TACHO. + */ +struct tacho_regs { + volatile uint16_t TACHOCFG; /*Configuration Register */ + volatile uint16_t Reserved0; /*Reserved */ + volatile uint8_t TACHOIE; /*Interrupt Enable Register */ + volatile uint8_t Reserved1[3]; /*Reserved */ + volatile uint8_t TACHOPF; /*Event Pending Flag Register */ + volatile uint8_t Reserved2[3]; /*Reserved */ + volatile uint16_t TACHOCV; /*TACHO0 Counter Value Register */ + volatile uint16_t Reserved3; /*Reserved */ +}; + +#define TACHO_CNT_MAX_VALUE 0x7FFF + +#define TACHO_TIMEOUT_EVENT 0x02 +#define TACHO_UPDATE_EVENT 0x01 + +#define TACHO_MONITOR_CLK_64US 0 +#define TACHO_MONITOR_CLK_16US 1 +#define TACHO_MONITOR_CLK_8US 2 +#define TACHO_MONITOR_CLK_2US 3 + +#define TACHO_FUNCTION_ENABLE 0x0001 +#define TACHO_RING_EDGE_SAMPLE 0x0000 +#define TACHO_EDGE_CHANGE_SAMPLE 0x0080 +#define TACHO_FILTER_ENABLE 0x8000 + +#endif /* ENE_KB1200_TACHO_H */ diff --git a/soc/ene/kb1200/reg/wdt.h b/soc/ene/kb1200/reg/wdt.h new file mode 100644 index 00000000000..cd053327069 --- /dev/null +++ b/soc/ene/kb1200/reg/wdt.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2024 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ENE_KB1200_WDT_H +#define ENE_KB1200_WDT_H + +/** + * brief Structure type to access Watch Dog Timer (WDT). + */ +struct wdt_regs { + volatile uint8_t WDTCFG; /*Configuration Register */ + volatile uint8_t WDTCFG_T; /*Configuration Reset Type Register */ + volatile uint16_t Reserved0; /*Reserved */ + volatile uint8_t WDTIE; /*Interrupt Enable Register */ + volatile uint8_t Reserved1[3]; /*Reserved */ + volatile uint8_t WDTPF; /*Event Pending Flag Register */ + volatile uint8_t Reserved2[3]; /*Reserved */ + volatile uint16_t WDTM; /*WDT Match Value Register */ + volatile uint16_t Reserved3; /*Reserved */ + volatile uint8_t WDTSCR[4]; /*FW Scratch(4 bytes) Register */ +}; + +#define WDT_MIN_CNT 3U +#define WDT_SAMPLE_TIME 31.25 + +#define WDT_RESET_WHOLE_CHIP_WO_GPIO 0 +#define WDT_RESET_WHOLE_CHIP 1 +#define WDT_RESET_ONLY_MCU 2 + +#define WDT_DISABLE_PASSWORD 0x90 +#define WDT_ADCO32K 0x00 +#define WDT_PHER32K 0x02 +#define WDT_FUNCTON_ENABLE 0x01 + +#define WDT_HALF_WAY_EVENT 0x01 +#define WDT_RESET_EVENT 0x02 + +#endif /* ENE_KB1200_WDT_H */ diff --git a/soc/ene/kb1200/soc.c b/soc/ene/kb1200/soc.c new file mode 100644 index 00000000000..6abf0180fb9 --- /dev/null +++ b/soc/ene/kb1200/soc.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#define PMU_BASE DT_REG_ADDR(DT_NODELABEL(pmu)) +#define GCFG_BASE DT_REG_ADDR(DT_NODELABEL(gcfg)) + +static void pmu_init(void) +{ + struct pmu_regs *pmu = ((struct pmu_regs *)PMU_BASE); + + /* Interrupt Event Wakeup from IDLE mode Enable */ + pmu->PMUIDLE |= PMU_IDLE_WU_ENABLE; + /* GPTD wake up from STOP mode enable. */ + pmu->PMUSTOP |= PMU_STOP_WU_GPTD; + /* SWD EDI32 wake up from STOP mode enable */ + pmu->PMUSTOP |= (PMU_STOP_WU_EDI32 | PMU_STOP_WU_SWD); +} +static void clock_init(void) +{ + struct gcfg_regs *gcfg = ((struct gcfg_regs *)GCFG_BASE); + + if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 96000000) { + /* AHB/APB clock select 96MHz/48MHz */ + gcfg->CLKCFG = GCFG_CLKCFG_96M; + } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 48000000) { + /* AHB/APB clock select 48MHz/24MHz */ + gcfg->CLKCFG = GCFG_CLKCFG_48M; + } else { + /* AHB/APB clock select 24MHz/12MHz */ + gcfg->CLKCFG = GCFG_CLKCFG_24M; + } +} + +static int kb1200_init(void) +{ + clock_init(); + pmu_init(); + return 0; +} + +SYS_INIT(kb1200_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/ene/kb1200/soc.h b/soc/ene/kb1200/soc.h new file mode 100644 index 00000000000..d5dd6ebcee2 --- /dev/null +++ b/soc/ene/kb1200/soc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _KB1200_SOC_H_ +#define _KB1200_SOC_H_ + +#include + +#endif /* _KB1200_SOC_H_ */ diff --git a/soc/ene/kb1200/soc.yml b/soc/ene/kb1200/soc.yml new file mode 100644 index 00000000000..41062ef67cb --- /dev/null +++ b/soc/ene/kb1200/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: kb1200 From 05276b63e846827b135de3cfbbd1c8604dc64cef Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:26 +0800 Subject: [PATCH 0705/2402] dts: pinctrl: kb1200 pinctrl dtsi Add pinctrl dtsi for ENE KB1200 Signed-off-by: Steven Chang --- dts/arm/ene/kb1200.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/dts/arm/ene/kb1200.dtsi b/dts/arm/ene/kb1200.dtsi index f977d871a53..544e387c6c5 100644 --- a/dts/arm/ene/kb1200.dtsi +++ b/dts/arm/ene/kb1200.dtsi @@ -52,6 +52,14 @@ compatible = "ene,kb1200-gcfg"; reg = <0x40000000 0x100>; }; + + pinctrl: pin-controller@50000000 { + compatible = "ene,kb1200-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x100>; + status = "okay"; + }; }; }; From 64b4a3fe0877ee2ee33060dc1dd840ae7d560994 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:27 +0800 Subject: [PATCH 0706/2402] drivers: pinctrl: initial device driver for ENE KB1200 Add pinctrl driver for ENE KB1200 Signed-off-by: Steven Chang --- drivers/pinctrl/CMakeLists.txt | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Kconfig.ene | 9 + drivers/pinctrl/pinctrl_ene_kb1200.c | 181 ++++++++++++++++++ .../dt-bindings/pinctrl/ene-kb1200-pinctrl.h | 48 +++++ soc/ene/kb1200/pinctrl_soc.h | 52 +++++ 6 files changed, 292 insertions(+) create mode 100644 drivers/pinctrl/Kconfig.ene create mode 100644 drivers/pinctrl/pinctrl_ene_kb1200.c create mode 100644 include/zephyr/dt-bindings/pinctrl/ene-kb1200-pinctrl.h create mode 100644 soc/ene/kb1200/pinctrl_soc.h diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 4eb87c69909..a0e246ba687 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -35,6 +35,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC32XX pinctrl_ti_cc32xx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMAKER pinctrl_numaker.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_QUICKLOGIC_EOS_S3 pinctrl_eos_s3.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RW pinctrl_rw_iomux.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_ENE_KB1200 pinctrl_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCU pinctrl_imx_scu.c) add_subdirectory(renesas) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index cc2c8800a5d..df96253c9f9 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -63,6 +63,7 @@ source "drivers/pinctrl/Kconfig.ti_cc32xx" source "drivers/pinctrl/Kconfig.numaker" source "drivers/pinctrl/Kconfig.eos_s3" source "drivers/pinctrl/Kconfig.rw" +source "drivers/pinctrl/Kconfig.ene" source "drivers/pinctrl/Kconfig.zynqmp" rsource "renesas/Kconfig" diff --git a/drivers/pinctrl/Kconfig.ene b/drivers/pinctrl/Kconfig.ene new file mode 100644 index 00000000000..d885aa57fd5 --- /dev/null +++ b/drivers/pinctrl/Kconfig.ene @@ -0,0 +1,9 @@ +# Copyright (c) 2023 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_ENE_KB1200 + bool "ENE KB1200 Pin controller driver" + default y + depends on DT_HAS_ENE_KB1200_PINCTRL_ENABLED + help + Enable pin controller driver for ENE KB1200 MCUs diff --git a/drivers/pinctrl/pinctrl_ene_kb1200.c b/drivers/pinctrl/pinctrl_ene_kb1200.c new file mode 100644 index 00000000000..27500325719 --- /dev/null +++ b/drivers/pinctrl/pinctrl_ene_kb1200.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ene_kb1200_pinctrl + +#include +#include +#include +#include +#include +#include +#include + +/* + * PINMUX_FUNC_A : GPIO Function + * PINMUX_FUNC_B : AltOutput 1 Function + * PINMUX_FUNC_C : AltOutput 2 Function + * PINMUX_FUNC_D : AltOutput 3 Function + * PINMUX_FUNC_E : AltOutput 4 Function + * + * GPIO Alternate Output Function Selection + * (PINMUX_FUNC_A) (PINMUX_FUNC_B) (PINMUX_FUNC_C) (PINMUX_FUNC_D) (PINMUX_FUNC_E) + * GPIO00 PWMLED0 PWM8 + * GPIO01 SER_RXD1 UART_SIN SBUD_DAT + * GPIO03 SER_TXD1 UART_SOUT SBUD_CLK + * GPIO22 ESBDAT PWM9 + * GPIO28 32KOUT SERCLK2 + * GPIO36 UARTSOUT SERTXD2 + * GPIO5C KSO6 P80DAT + * GPIO5D KSO7 P80CLK + * GPIO5E KSO8 SERRXD1 + * GPIO5F KSO9 SERTXD1 + * GPIO71 SDA8 UARTRTS + * GPIO38 SCL4 PWM1 + */ + +/* + * f is function number + * b[7:5] = pin bank + * b[4:0] = pin position in bank + * b[11:8] = function + */ + +#define ENE_KB1200_PINMUX_PIN(p) FIELD_GET(GENMASK(4, 0), p) +#define ENE_KB1200_PINMUX_PORT(p) FIELD_GET(GENMASK(7, 5), p) +#define ENE_KB1200_PINMUX_FUNC(p) FIELD_GET(GENMASK(11, 8), p) +#define ENE_KB1200_PINMUX_PORT_PIN(p) FIELD_GET(GENMASK(7, 0), p) + +static const uint32_t gcfg_reg_addr = DT_REG_ADDR(DT_NODELABEL(gcfg)); +static const uint32_t gpio_reg_bases[] = { + DT_REG_ADDR(DT_NODELABEL(gpio0x1x)), + DT_REG_ADDR(DT_NODELABEL(gpio2x3x)), + DT_REG_ADDR(DT_NODELABEL(gpio4x5x)), + DT_REG_ADDR(DT_NODELABEL(gpio6x7x)), +}; + +static int kb1200_config_pin(uint32_t gpio, uint32_t conf, uint32_t func) +{ + uint32_t port = ENE_KB1200_PINMUX_PORT(gpio); + uint32_t pin = (uint32_t)ENE_KB1200_PINMUX_PIN(gpio); + struct gpio_regs *gpio_regs = (struct gpio_regs *)gpio_reg_bases[port]; + struct gcfg_regs *gcfg_regs = (struct gcfg_regs *)gcfg_reg_addr; + + if (port >= NUM_KB1200_GPIO_PORTS) { + return -EINVAL; + } + + if (func == PINMUX_FUNC_GPIO) { /* only GPIO function */ + WRITE_BIT(gpio_regs->GPIOFS, pin, 0); + } else { + func -= 1; /*for change to GPIOALT setting value*/ + switch (gpio) { + case GPIO00_PWMLED0_PWM8: + WRITE_BIT(gcfg_regs->GPIOALT, 0, func); + break; + case GPIO01_SERRXD1_UARTSIN: + gcfg_regs->GPIOMUX = (gcfg_regs->GPIOMUX & ~(3 << 9)) | (func << 9); + break; + case GPIO03_SERTXD1_UARTSOUT: + gcfg_regs->GPIOMUX = (gcfg_regs->GPIOMUX & ~(3 << 9)) | (func << 9); + break; + case GPIO22_ESBDAT_PWM9: + WRITE_BIT(gcfg_regs->GPIOALT, 1, func); + break; + case GPIO28_32KOUT_SERCLK2: + WRITE_BIT(gcfg_regs->GPIOALT, 2, func); + break; + case GPIO36_UARTSOUT_SERTXD2: + WRITE_BIT(gcfg_regs->GPIOALT, 3, func); + break; + case GPIO5C_KSO6_P80DAT: + WRITE_BIT(gcfg_regs->GPIOALT, 4, func); + break; + case GPIO5D_KSO7_P80CLK: + WRITE_BIT(gcfg_regs->GPIOALT, 5, func); + break; + case GPIO5E_KSO8_SERRXD1: + WRITE_BIT(gcfg_regs->GPIOALT, 6, func); + break; + case GPIO5F_KSO9_SERTXD1: + WRITE_BIT(gcfg_regs->GPIOALT, 7, func); + break; + case GPIO71_SDA8_UARTRTS: + WRITE_BIT(gcfg_regs->GPIOALT, 8, func); + break; + case GPIO38_SCL4_PWM1: + WRITE_BIT(gcfg_regs->GPIOALT, 9, func); + break; + } + WRITE_BIT(gpio_regs->GPIOFS, pin, 1); + } + /*Input always enable for loopback*/ + WRITE_BIT(gpio_regs->GPIOIE, pin, 1); + + if (conf & BIT(ENE_KB1200_NO_PUD_POS)) { + WRITE_BIT(gpio_regs->GPIOPU, pin, 0); + WRITE_BIT(gpio_regs->GPIOPD, pin, 0); + } + if (conf & BIT(ENE_KB1200_PU_POS)) { + WRITE_BIT(gpio_regs->GPIOPU, pin, 1); + } + if (conf & BIT(ENE_KB1200_PD_POS)) { + WRITE_BIT(gpio_regs->GPIOPD, pin, 1); + } + + if (conf & BIT(ENE_KB1200_OUT_DIS_POS)) { + WRITE_BIT(gpio_regs->GPIOOE, pin, 0); + } + if (conf & BIT(ENE_KB1200_OUT_EN_POS)) { + WRITE_BIT(gpio_regs->GPIOOE, pin, 1); + } + + if (conf & BIT(ENE_KB1200_OUT_LO_POS)) { + WRITE_BIT(gpio_regs->GPIOD, pin, 0); + } + if (conf & BIT(ENE_KB1200_OUT_HI_POS)) { + WRITE_BIT(gpio_regs->GPIOD, pin, 1); + } + + if (conf & BIT(ENE_KB1200_PUSH_PULL_POS)) { + WRITE_BIT(gpio_regs->GPIOOD, pin, 0); + } + if (conf & BIT(ENE_KB1200_OPEN_DRAIN_POS)) { + WRITE_BIT(gpio_regs->GPIOOD, pin, 1); + } + + if (conf & BIT(ENE_KB1200_PIN_LOW_POWER_POS)) { + WRITE_BIT(gpio_regs->GPIOLV, pin, 1); + } + + return 0; +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + uint32_t portpin, pinmux, func; + int ret; + + ARG_UNUSED(reg); + + for (uint8_t i = 0U; i < pin_cnt; i++) { + pinmux = pins[i]; + + func = ENE_KB1200_PINMUX_FUNC(pinmux); + if (func >= PINMUX_FUNC_MAX) { + return -EINVAL; + } + + portpin = ENE_KB1200_PINMUX_PORT_PIN(pinmux); + + ret = kb1200_config_pin(portpin, pinmux, func); + if (ret < 0) { + return ret; + } + } + + return 0; +} diff --git a/include/zephyr/dt-bindings/pinctrl/ene-kb1200-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ene-kb1200-pinctrl.h new file mode 100644 index 00000000000..7ed0320d9f8 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/ene-kb1200-pinctrl.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ENE_KB1200_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ENE_KB1200_PINCTRL_H_ + +#include + +#define PINMUX_FUNC_GPIO 0x00 +#define PINMUX_FUNC_A 0x00 +#define PINMUX_FUNC_B 0x01 +#define PINMUX_FUNC_C 0x02 +#define PINMUX_FUNC_D 0x03 +#define PINMUX_FUNC_MAX 0x04 + +#define ENE_KB1200_NO_PUD_POS 12 +#define ENE_KB1200_PD_POS 13 +#define ENE_KB1200_PU_POS 14 +#define ENE_KB1200_PUSH_PULL_POS 15 +#define ENE_KB1200_OPEN_DRAIN_POS 16 +#define ENE_KB1200_OUT_DIS_POS 17 +#define ENE_KB1200_OUT_EN_POS 18 +#define ENE_KB1200_OUT_HI_POS 19 +#define ENE_KB1200_OUT_LO_POS 20 +#define ENE_KB1200_PIN_LOW_POWER_POS 21 + +#define ENE_KB1200_PINMUX_PORT_POS 5 +#define ENE_KB1200_PINMUX_PORT_MSK 0x7 +#define ENE_KB1200_PINMUX_PIN_POS 0 +#define ENE_KB1200_PINMUX_PIN_MSK 0x1f +#define ENE_KB1200_PINMUX_FUNC_POS 8 +#define ENE_KB1200_PINMUX_FUNC_MSK 0xf + +/* + * f is function number + * b[7:5] = pin bank + * b[4:0] = pin position in bank + * b[11:8] = function + */ +#define ENE_KB1200_PINMUX(n, f) \ + (((((n) >> 5) & ENE_KB1200_PINMUX_PORT_MSK) << ENE_KB1200_PINMUX_PORT_POS) | \ + (((n) & ENE_KB1200_PINMUX_PIN_MSK) << ENE_KB1200_PINMUX_PIN_POS) | \ + (((f) & ENE_KB1200_PINMUX_FUNC_MSK) << ENE_KB1200_PINMUX_FUNC_POS)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ENE_KB1200_PINCTRL_H_ */ diff --git a/soc/ene/kb1200/pinctrl_soc.h b/soc/ene/kb1200/pinctrl_soc.h new file mode 100644 index 00000000000..74fdc0ae8aa --- /dev/null +++ b/soc/ene/kb1200/pinctrl_soc.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_KB1200_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_KB1200_PINCTRL_SOC_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +typedef uint32_t pinctrl_soc_pin_t; + +/* initialize pinmux member fields of pinctrl_pin_t */ +#define Z_PINCTRL_ENE_KB1200_PINMUX_INIT(node_id) (uint32_t)(DT_PROP(node_id, pinmux)) + +#define Z_PINCTRL_STATE_PINCFG_INIT(node_id) \ + ((DT_PROP(node_id, bias_disable) << ENE_KB1200_NO_PUD_POS) | \ + (DT_PROP(node_id, bias_pull_down) << ENE_KB1200_PD_POS) | \ + (DT_PROP(node_id, bias_pull_up) << ENE_KB1200_PU_POS) | \ + (DT_PROP(node_id, drive_push_pull) << ENE_KB1200_PUSH_PULL_POS) | \ + (DT_PROP(node_id, drive_open_drain) << ENE_KB1200_OPEN_DRAIN_POS) | \ + (DT_PROP(node_id, output_disable) << ENE_KB1200_OUT_DIS_POS) | \ + (DT_PROP(node_id, output_enable) << ENE_KB1200_OUT_EN_POS) | \ + (DT_PROP(node_id, output_high) << ENE_KB1200_OUT_HI_POS) | \ + (DT_PROP(node_id, output_low) << ENE_KB1200_OUT_LO_POS) | \ + (DT_PROP(node_id, low_power_enable) << ENE_KB1200_PIN_LOW_POWER_POS)) + +/* initialize pin structure members */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ + (Z_PINCTRL_ENE_KB1200_PINMUX_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx)) | \ + Z_PINCTRL_STATE_PINCFG_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx))), + +/* Use DT FOREACH macro to initialize each used pin */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { \ + DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) \ + } + +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_KB1200_PINCTRL_SOC_H_ */ From f66e8afe7c87039211900b4e4ca6474a480afe6b Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:27 +0800 Subject: [PATCH 0707/2402] dts: gpio: kb1200 gpio device nodes Add GPIO device nodes for ENE KB1200 Signed-off-by: Steven Chang --- dts/arm/ene/kb1200.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/dts/arm/ene/kb1200.dtsi b/dts/arm/ene/kb1200.dtsi index 544e387c6c5..69cc91645be 100644 --- a/dts/arm/ene/kb1200.dtsi +++ b/dts/arm/ene/kb1200.dtsi @@ -59,6 +59,45 @@ #size-cells = <1>; reg = <0x50000000 0x100>; status = "okay"; + gpio0x1x: gpio@50000000 { + compatible = "ene,kb1200-gpio"; + reg = <0x50000000 0x04>, <0x50010000 0x04>; + interrupts = <2 3>, <3 3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + status = "disabled"; + }; + + gpio2x3x: gpio@50000004 { + compatible = "ene,kb1200-gpio"; + reg = <0x50000004 0x04>, <0x50010004 0x04>; + interrupts = <4 3>, <5 3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + status = "disabled"; + }; + + gpio4x5x: gpio@50000008 { + compatible = "ene,kb1200-gpio"; + reg = <0x50000008 0x04>, <0x50010008 0x04>; + interrupts = <6 3>, <7 3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + status = "disabled"; + }; + + gpio6x7x: gpio@5000000c { + compatible = "ene,kb1200-gpio"; + reg = <0x5000000C 0x04>, <0x5001000C 0x04>; + interrupts = <8 3>, <9 3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + status = "disabled"; + }; }; }; }; From 62245b3ba919ecd792dcae6c5dc0fa19627a6724 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:27 +0800 Subject: [PATCH 0708/2402] drivers: gpio: initial device driver for ENE KB1200 Add GPIO driver for ENE KB1200 Signed-off-by: Steven Chang --- drivers/gpio/CMakeLists.txt | 1 + drivers/gpio/Kconfig | 2 + drivers/gpio/Kconfig.ene | 9 ++ drivers/gpio/gpio_ene_kb1200.c | 210 +++++++++++++++++++++++++++++++++ 4 files changed, 222 insertions(+) create mode 100644 drivers/gpio/Kconfig.ene create mode 100644 drivers/gpio/gpio_ene_kb1200.c diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 3e4ae12dc4a..8d019f91ab1 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -89,6 +89,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_TLE9104 gpio_tle9104.c) zephyr_library_sources_ifdef(CONFIG_GPIO_ALTERA_PIO gpio_altera_pio.c) zephyr_library_sources_ifdef(CONFIG_GPIO_BCM2711 gpio_bcm2711.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RA gpio_renesas_ra.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_ENE_KB1200 gpio_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RZT2M gpio_rzt2m.c) zephyr_library_sources_ifdef(CONFIG_GPIO_AMBIQ gpio_ambiq.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ff9d02704d8..fb481cb229d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -236,6 +236,8 @@ source "drivers/gpio/Kconfig.bcm2711" source "drivers/gpio/Kconfig.renesas_ra" +source "drivers/gpio/Kconfig.ene" + source "drivers/gpio/Kconfig.rzt2m" source "drivers/gpio/Kconfig.ambiq" diff --git a/drivers/gpio/Kconfig.ene b/drivers/gpio/Kconfig.ene new file mode 100644 index 00000000000..7dfc2c8318d --- /dev/null +++ b/drivers/gpio/Kconfig.ene @@ -0,0 +1,9 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config GPIO_ENE_KB1200 + bool "ENE KB1200 GPIO Driver" + default y + depends on DT_HAS_ENE_KB1200_GPIO_ENABLED + help + Enable support for the kb1200 GPIO controllers. diff --git a/drivers/gpio/gpio_ene_kb1200.c b/drivers/gpio/gpio_ene_kb1200.c new file mode 100644 index 00000000000..aedeae7b177 --- /dev/null +++ b/drivers/gpio/gpio_ene_kb1200.c @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ene_kb1200_gpio + +#include +#include +#include +#include +#include +#include + +struct gpio_kb1200_data { + /* gpio_driver_data needs to be first */ + struct gpio_driver_data common; + sys_slist_t cb; +}; + +struct gpio_kb1200_config { + /* gpio_driver_config needs to be first */ + struct gpio_driver_config common; + /* base address of GPIO port */ + struct gpio_regs *gpio_regs; + struct gptd_regs *gptd_regs; +}; + +static void gpio_kb1200_isr(const struct device *dev) +{ + const struct gpio_kb1200_config *config = dev->config; + struct gpio_kb1200_data *context = dev->data; + uint32_t pending_flag = config->gptd_regs->GPTDPF; + + gpio_fire_callbacks(&context->cb, dev, pending_flag); + config->gptd_regs->GPTDPF |= pending_flag; +} + +static int kb1200_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) +{ + const struct gpio_kb1200_config *config = dev->config; + + WRITE_BIT(config->gpio_regs->GPIOFS, pin, 0); + if ((flags & GPIO_OUTPUT) != 0) { + WRITE_BIT(config->gpio_regs->GPIOIE, pin, 1); + if ((flags & GPIO_SINGLE_ENDED) != 0) { + if (flags & GPIO_LINE_OPEN_DRAIN) { + WRITE_BIT(config->gpio_regs->GPIOOD, pin, 1); + } + } else { + WRITE_BIT(config->gpio_regs->GPIOOD, pin, 0); + } + if (flags & GPIO_PULL_UP) { + WRITE_BIT(config->gpio_regs->GPIOPU, pin, 1); + } else { + WRITE_BIT(config->gpio_regs->GPIOPU, pin, 0); + } + if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) { + WRITE_BIT(config->gpio_regs->GPIOD, pin, 1); + } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) { + WRITE_BIT(config->gpio_regs->GPIOD, pin, 0); + } + WRITE_BIT(config->gpio_regs->GPIOOE, pin, 1); + } else { + WRITE_BIT(config->gpio_regs->GPIOOE, pin, 0); + if (flags & GPIO_PULL_UP) { + WRITE_BIT(config->gpio_regs->GPIOPU, pin, 1); + } else { + WRITE_BIT(config->gpio_regs->GPIOPU, pin, 0); + } + WRITE_BIT(config->gpio_regs->GPIOIE, pin, 1); + } + return 0; +} + +static int kb1200_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value) +{ + const struct gpio_kb1200_config *config = dev->config; + + *value = config->gpio_regs->GPIOIN; + return 0; +} + +static int kb1200_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, + gpio_port_value_t value) +{ + const struct gpio_kb1200_config *config = dev->config; + + config->gpio_regs->GPIOD |= (value & mask); + return 0; +} + +static int kb1200_gpio_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_kb1200_config *config = dev->config; + + config->gpio_regs->GPIOD |= pins; + return 0; +} + +static int kb1200_gpio_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_kb1200_config *config = dev->config; + + config->gpio_regs->GPIOD &= ~pins; + return 0; +} + +static int kb1200_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_kb1200_config *config = dev->config; + + config->gpio_regs->GPIOD ^= pins; + return 0; +} + +static int kb1200_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, + enum gpio_int_mode mode, enum gpio_int_trig trig) +{ + const struct gpio_kb1200_config *config = dev->config; + + /* Check if GPIO port needs interrupt support */ + if ((mode & GPIO_INT_DISABLE) || (mode & GPIO_INT_ENABLE) == 0) { + /* Set the mask to disable the interrupt */ + WRITE_BIT(config->gptd_regs->GPTDIE, pin, 0); + } else { + if (mode & GPIO_INT_EDGE) { + WRITE_BIT(config->gptd_regs->GPTDEL, pin, 0); + if (trig & GPIO_INT_HIGH_1) { + if (trig & GPIO_INT_LOW_0) { /* Falling & Rising edge trigger */ + /* Enable toggle trigger */ + WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 1); + } else { /* Rising edge */ + /* Disable toggle trigger */ + WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 0); + WRITE_BIT(config->gptd_regs->GPTDPS, pin, 1); + } + } else { /* Falling edge */ + /* Disable Toggle trigger */ + WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 0); + WRITE_BIT(config->gptd_regs->GPTDPS, pin, 0); + } + } else { + WRITE_BIT(config->gptd_regs->GPTDEL, pin, 1); + /* Disable Toggle trigger */ + WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 0); + if (trig & GPIO_INT_HIGH_1) { + WRITE_BIT(config->gptd_regs->GPTDPS, pin, 1); + } else { + WRITE_BIT(config->gptd_regs->GPTDPS, pin, 0); + } + } + /* clear pending flag */ + WRITE_BIT(config->gptd_regs->GPTDPF, pin, 1); + /* Enable the interrupt */ + WRITE_BIT(config->gptd_regs->GPTDIE, pin, 1); + } + return 0; +} + +static int kb1200_gpio_manage_callback(const struct device *dev, struct gpio_callback *cb, bool set) +{ + struct gpio_kb1200_data *context = dev->data; + + gpio_manage_callback(&context->cb, cb, set); + return 0; +} + +static uint32_t kb1200_gpio_get_pending_int(const struct device *dev) +{ + const struct gpio_kb1200_config *const config = dev->config; + + return config->gptd_regs->GPTDPF; +} + +static const struct gpio_driver_api kb1200_gpio_api = { + .pin_configure = kb1200_gpio_pin_configure, + .port_get_raw = kb1200_gpio_port_get_raw, + .port_set_masked_raw = kb1200_gpio_port_set_masked_raw, + .port_set_bits_raw = kb1200_gpio_port_set_bits_raw, + .port_clear_bits_raw = kb1200_gpio_port_clear_bits_raw, + .port_toggle_bits = kb1200_gpio_port_toggle_bits, + .pin_interrupt_configure = kb1200_gpio_pin_interrupt_configure, + .manage_callback = kb1200_gpio_manage_callback, + .get_pending_int = kb1200_gpio_get_pending_int, +}; + +#define KB1200_GPIO_INIT(n) \ + static int kb1200_gpio_##n##_init(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), DT_INST_IRQ_BY_IDX(n, 0, priority), \ + gpio_kb1200_isr, DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQ_BY_IDX(n, 0, irq)); \ + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 1, irq), DT_INST_IRQ_BY_IDX(n, 1, priority), \ + gpio_kb1200_isr, DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQ_BY_IDX(n, 1, irq)); \ + return 0; \ + }; \ + static const struct gpio_kb1200_config port_##n##_kb1200_config = { \ + .common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n)}, \ + .gpio_regs = (struct gpio_regs *)DT_INST_REG_ADDR_BY_IDX(n, 0), \ + .gptd_regs = (struct gptd_regs *)DT_INST_REG_ADDR_BY_IDX(n, 1), \ + }; \ + static struct gpio_kb1200_data gpio_kb1200_##n##_data; \ + DEVICE_DT_INST_DEFINE(n, &kb1200_gpio_##n##_init, NULL, &gpio_kb1200_##n##_data, \ + &port_##n##_kb1200_config, POST_KERNEL, \ + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &kb1200_gpio_api); + +DT_INST_FOREACH_STATUS_OKAY(KB1200_GPIO_INIT) From 543d550c5430a4bed18b38635a57d4495ecef7e2 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:28 +0800 Subject: [PATCH 0709/2402] dts: uart: kb1200 uart device nodes Add uart device nodes and pinctrl nodes for ENE KB1200 Signed-off-by: Steven Chang --- dts/arm/ene/kb1200-pinctrl.dtsi | 32 ++++++++++++++++++++++++++++++++ dts/arm/ene/kb1200.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 dts/arm/ene/kb1200-pinctrl.dtsi diff --git a/dts/arm/ene/kb1200-pinctrl.dtsi b/dts/arm/ene/kb1200-pinctrl.dtsi new file mode 100644 index 00000000000..056bf9ddcd9 --- /dev/null +++ b/dts/arm/ene/kb1200-pinctrl.dtsi @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + /omit-if-no-ref/ uart0_tx_gpio03: uart0_tx_gpio03 { + pinmux = ; + output-enable; + }; + /omit-if-no-ref/ uart0_rx_gpio01: uart0_rx_gpio01 { + pinmux = ; + }; + /omit-if-no-ref/ uart1_tx_gpio36: uart1_tx_gpio36 { + pinmux = ; + output-enable; + }; + /omit-if-no-ref/ uart1_rx_gpio28: uart1_rx_gpio28 { + pinmux = ; + }; + /omit-if-no-ref/ uart2_tx_gpio04: uart2_tx_gpio04 { + pinmux = ; + output-enable; + }; + /omit-if-no-ref/ uart2_rx_gpio55: uart2_rx_gpio55 { + pinmux = ; + }; +}; diff --git a/dts/arm/ene/kb1200.dtsi b/dts/arm/ene/kb1200.dtsi index 69cc91645be..1d20b3c8e01 100644 --- a/dts/arm/ene/kb1200.dtsi +++ b/dts/arm/ene/kb1200.dtsi @@ -99,6 +99,30 @@ status = "disabled"; }; }; + + uart0: serial@40310000 { + compatible = "ene,kb1200-uart"; + reg = <0x40310000 0x4c>; + interrupts = <20 3>; + current-speed = <115200>; + status = "disabled"; + }; + + uart1: serial@40310020 { + compatible = "ene,kb1200-uart"; + reg = <0x40310020 0x4c>; + interrupts = <20 3>; + current-speed = <115200>; + status = "disabled"; + }; + + uart2: serial@40310040 { + compatible = "ene,kb1200-uart"; + reg = <0x40310040 0x4c>; + interrupts = <20 3>; + current-speed = <115200>; + status = "disabled"; + }; }; }; From 9f22c8951bfc751f159c4fb335fcdaeba9dfa680 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:28 +0800 Subject: [PATCH 0710/2402] drivers: uart: initial device driver for ENE KB1200 Add uart driver for ENE KB1200 Signed-off-by: Steven Chang --- drivers/serial/CMakeLists.txt | 1 + drivers/serial/Kconfig | 2 + drivers/serial/Kconfig.ene | 12 + drivers/serial/uart_ene_kb1200.c | 380 +++++++++++++++++++++++++++++++ 4 files changed, 395 insertions(+) create mode 100644 drivers/serial/Kconfig.ene create mode 100644 drivers/serial/uart_ene_kb1200.c diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index 1648f3a7081..4480e676234 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -73,6 +73,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_SEDI uart_sedi.c) zephyr_library_sources_ifdef(CONFIG_UART_BCM2711_MU uart_bcm2711.c) zephyr_library_sources_ifdef(CONFIG_UART_INTEL_LW uart_intel_lw.c) zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RA uart_renesas_ra.c) +zephyr_library_sources_ifdef(CONFIG_UART_ENE_KB1200 uart_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_UART_RZT2M uart_rzt2m.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index a3041b2cae6..86b9114b33b 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -270,6 +270,8 @@ source "drivers/serial/Kconfig.intel_lw" source "drivers/serial/Kconfig.renesas_ra" +source "drivers/serial/Kconfig.ene" + source "drivers/serial/Kconfig.rzt2m" endif # SERIAL diff --git a/drivers/serial/Kconfig.ene b/drivers/serial/Kconfig.ene new file mode 100644 index 00000000000..dd2b246f3d8 --- /dev/null +++ b/drivers/serial/Kconfig.ene @@ -0,0 +1,12 @@ +# Copyright (c) 2023 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config UART_ENE_KB1200 + bool "ENE KB1200 serial driver" + default y + depends on DT_HAS_ENE_KB1200_UART_ENABLED + select SERIAL_HAS_DRIVER + select SERIAL_SUPPORT_INTERRUPT + select PINCTRL + help + This option enables the KB1200 serial driver. diff --git a/drivers/serial/uart_ene_kb1200.c b/drivers/serial/uart_ene_kb1200.c new file mode 100644 index 00000000000..00105bd1783 --- /dev/null +++ b/drivers/serial/uart_ene_kb1200.c @@ -0,0 +1,380 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ene_kb1200_uart + +#include +#include +#include +#include + +struct kb1200_uart_config { +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + void (*irq_cfg_func)(void); +#endif + struct serial_regs *ser; + const struct pinctrl_dev_config *pcfg; +}; + +struct kb1200_uart_data { + uart_irq_callback_user_data_t callback; + struct uart_config current_config; + void *callback_data; + uint8_t pending_flag_data; +}; + +static int kb1200_uart_err_check(const struct device *dev) +{ + const struct kb1200_uart_config *config = dev->config; + int err = 0; + + if (config->ser->SERSTS & SERSTS_RX_OVERRUN) { + err |= UART_ERROR_OVERRUN; + } + if (config->ser->SERSTS & SERSTS_PARITY_ERROR) { + err |= UART_ERROR_PARITY; + } + if (config->ser->SERSTS & SERSTS_FRAME_ERROR) { + err |= UART_ERROR_FRAMING; + } + return err; +} + +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE +static int kb1200_uart_configure(const struct device *dev, const struct uart_config *cfg) +{ + uint16_t reg_baudrate = 0; + uint8_t reg_parity = 0; + int ret = 0; + const struct kb1200_uart_config *config = dev->config; + struct kb1200_uart_data *data = dev->data; + + reg_baudrate = (DIVIDER_BASE_CLK / cfg->baudrate) - 1; + + switch (cfg->parity) { + case UART_CFG_PARITY_NONE: + reg_parity = SERCFG_PARITY_NONE; + break; + case UART_CFG_PARITY_ODD: + reg_parity = SERCFG_PARITY_ODD; + break; + case UART_CFG_PARITY_EVEN: + reg_parity = SERCFG_PARITY_EVEN; + break; + case UART_CFG_PARITY_MARK: + case UART_CFG_PARITY_SPACE: + default: + ret = -ENOTSUP; + break; + } + + switch (cfg->stop_bits) { + case UART_CFG_STOP_BITS_1: + break; + case UART_CFG_STOP_BITS_0_5: + case UART_CFG_STOP_BITS_1_5: + case UART_CFG_STOP_BITS_2: + default: + ret = -ENOTSUP; + break; + } + + switch (cfg->data_bits) { + case UART_CFG_DATA_BITS_8: + break; + case UART_CFG_DATA_BITS_5: + case UART_CFG_DATA_BITS_6: + case UART_CFG_DATA_BITS_7: + case UART_CFG_DATA_BITS_9: + default: + ret = -ENOTSUP; + break; + } + + switch (cfg->flow_ctrl) { + case UART_CFG_FLOW_CTRL_NONE: + break; + case UART_CFG_FLOW_CTRL_RTS_CTS: + case UART_CFG_FLOW_CTRL_DTR_DSR: + case UART_CFG_FLOW_CTRL_RS485: + default: + ret = -ENOTSUP; + break; + } + config->ser->SERCFG = + (reg_baudrate << 16) | (reg_parity << 2) | (SERIE_RX_ENABLE | SERIE_TX_ENABLE); + config->ser->SERCTRL = SERCTRL_MODE1; + data->current_config = *cfg; + return ret; +} + +static int kb1200_uart_config_get(const struct device *dev, struct uart_config *cfg) +{ + struct kb1200_uart_data *data = dev->data; + + *cfg = data->current_config; + return 0; +} +#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN +static int kb1200_uart_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size) +{ + const struct kb1200_uart_config *config = dev->config; + uint16_t tx_bytes = 0U; + + while ((size - tx_bytes) > 0) { + /* Check Tx FIFO not Full*/ + while (config->ser->SERSTS & SERSTS_TX_FULL) + ; + /* Put a character into Tx FIFO */ + config->ser->SERTBUF = tx_data[tx_bytes]; + tx_bytes++; + } + return tx_bytes; +} + +static int kb1200_uart_fifo_read(const struct device *dev, uint8_t *rx_data, const int size) +{ + const struct kb1200_uart_config *config = dev->config; + uint16_t rx_bytes = 0U; + + /* Check Rx FIFO not Empty*/ + while ((size - rx_bytes > 0) && (!(config->ser->SERSTS & SERSTS_RX_EMPTY))) { + /* Put a character into Tx FIFO */ + rx_data[rx_bytes] = config->ser->SERRBUF; + rx_bytes++; + } + return rx_bytes; +} + +static void kb1200_uart_irq_tx_enable(const struct device *dev) +{ + const struct kb1200_uart_config *config = dev->config; + + config->ser->SERPF = SERPF_TX_EMPTY; + config->ser->SERIE |= SERIE_TX_ENABLE; +} + +static void kb1200_uart_irq_tx_disable(const struct device *dev) +{ + const struct kb1200_uart_config *config = dev->config; + + config->ser->SERIE &= ~SERIE_TX_ENABLE; + config->ser->SERPF = SERPF_TX_EMPTY; +} + +static int kb1200_uart_irq_tx_ready(const struct device *dev) +{ + struct kb1200_uart_data *data = dev->data; + + return (data->pending_flag_data & SERPF_TX_EMPTY) ? 1 : 0; +} + +static void kb1200_uart_irq_rx_enable(const struct device *dev) +{ + const struct kb1200_uart_config *config = dev->config; + + config->ser->SERPF = SERPF_RX_CNT_FULL; + config->ser->SERIE |= SERIE_RX_ENABLE; +} + +static void kb1200_uart_irq_rx_disable(const struct device *dev) +{ + const struct kb1200_uart_config *config = dev->config; + + config->ser->SERIE &= (~SERIE_RX_ENABLE); + config->ser->SERPF = SERPF_RX_CNT_FULL; +} + +static int kb1200_uart_irq_rx_ready(const struct device *dev) +{ + struct kb1200_uart_data *data = dev->data; + + return (data->pending_flag_data & SERPF_RX_CNT_FULL) ? 1 : 0; +} + +static void kb1200_uart_irq_err_enable(const struct device *dev) +{ + const struct kb1200_uart_config *config = dev->config; + + config->ser->SERPF = SERPF_RX_ERROR; + config->ser->SERIE |= SERIE_RX_ERROR; +} + +static void kb1200_uart_irq_err_disable(const struct device *dev) +{ + const struct kb1200_uart_config *config = dev->config; + + config->ser->SERIE &= (~SERIE_RX_ERROR); + config->ser->SERPF = SERPF_RX_ERROR; +} + +static int kb1200_uart_irq_is_pending(const struct device *dev) +{ + struct kb1200_uart_data *data = dev->data; + + return (data->pending_flag_data) ? 1 : 0; +} + +static int kb1200_uart_irq_update(const struct device *dev) +{ + struct kb1200_uart_data *data = dev->data; + const struct kb1200_uart_config *config = dev->config; + + data->pending_flag_data = (config->ser->SERPF) & (config->ser->SERIE); + /*clear pending flag*/ + config->ser->SERPF = data->pending_flag_data; + return 1; +} + +static void kb1200_uart_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb, + void *cb_data) +{ + struct kb1200_uart_data *data = dev->data; + + data->callback = cb; + data->callback_data = cb_data; +} + +static void kb1200_uart_irq_handler(const struct device *dev) +{ + struct kb1200_uart_data *data = dev->data; + + if (data->callback) { + data->callback(dev, data->callback_data); + } +} +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ + +static int kb1200_uart_poll_in(const struct device *dev, unsigned char *c) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + return kb1200_uart_fifo_read(dev, c, 1) ? 0 : -1; +#else + const struct kb1200_uart_config *config = dev->config; + + /* Check Rx FIFO not Empty*/ + if (config->ser->SERSTS & SERSTS_RX_EMPTY) { + return -1; + } + /* Put a character into Tx FIFO */ + *c = config->ser->SERRBUF; + return 0; +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ +} + +static void kb1200_uart_poll_out(const struct device *dev, unsigned char c) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + kb1200_uart_fifo_fill(dev, &c, 1); +#else + const struct kb1200_uart_config *config = dev->config; + + /* Wait Tx FIFO not Full*/ + while (config->ser->SERSTS & SER_TxFull) { + ; + } + /* Put a character into Tx FIFO */ + config->ser->SERTBUF = c; +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ +} + +static const struct uart_driver_api kb1200_uart_api = { + .poll_in = kb1200_uart_poll_in, + .poll_out = kb1200_uart_poll_out, + .err_check = kb1200_uart_err_check, +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + .configure = kb1200_uart_configure, + .config_get = kb1200_uart_config_get, +#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + .fifo_fill = kb1200_uart_fifo_fill, + .fifo_read = kb1200_uart_fifo_read, + .irq_tx_enable = kb1200_uart_irq_tx_enable, + .irq_tx_disable = kb1200_uart_irq_tx_disable, + .irq_tx_ready = kb1200_uart_irq_tx_ready, + .irq_rx_enable = kb1200_uart_irq_rx_enable, + .irq_rx_disable = kb1200_uart_irq_rx_disable, + .irq_rx_ready = kb1200_uart_irq_rx_ready, + .irq_err_enable = kb1200_uart_irq_err_enable, + .irq_err_disable = kb1200_uart_irq_err_disable, + .irq_is_pending = kb1200_uart_irq_is_pending, + .irq_update = kb1200_uart_irq_update, + .irq_callback_set = kb1200_uart_irq_callback_set, +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ +}; + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + +/* GPIO module instances */ +#define KB1200_UART_DEV(inst) DEVICE_DT_INST_GET(inst), +static const struct device *const uart_devices[] = {DT_INST_FOREACH_STATUS_OKAY(KB1200_UART_DEV)}; +static void kb1200_uart_isr_wrap(const struct device *dev) +{ + for (size_t i = 0; i < ARRAY_SIZE(uart_devices); i++) { + const struct device *dev_ = uart_devices[i]; + const struct kb1200_uart_config *config = dev_->config; + + if (config->ser->SERIE & config->ser->SERPF) { + kb1200_uart_irq_handler(dev_); + } + } +} +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ + +static int kb1200_uart_init(const struct device *dev) +{ + int ret; + const struct kb1200_uart_config *config = dev->config; + struct kb1200_uart_data *data = dev->data; + + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret != 0) { + return ret; + } + + kb1200_uart_configure(dev, &data->current_config); +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + config->irq_cfg_func(); +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ + + return 0; +} + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN +static bool init_irq = true; +static void kb1200_uart_irq_init(void) +{ + if (init_irq) { + init_irq = false; + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), kb1200_uart_isr_wrap, NULL, + 0); + irq_enable(DT_INST_IRQN(0)); + } +} +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ + +#define KB1200_UART_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + static struct kb1200_uart_data kb1200_uart_data_##n = { \ + .current_config = { \ + .baudrate = DT_INST_PROP(n, current_speed), \ + .parity = UART_CFG_PARITY_NONE, \ + .stop_bits = UART_CFG_STOP_BITS_1, \ + .data_bits = UART_CFG_DATA_BITS_8, \ + .flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \ + }, \ + }; \ + static const struct kb1200_uart_config kb1200_uart_config_##n = { \ + IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, (.irq_cfg_func = kb1200_uart_irq_init,)) \ + .ser = (struct serial_regs *)DT_INST_REG_ADDR(n), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n)}; \ + DEVICE_DT_INST_DEFINE(n, &kb1200_uart_init, NULL, &kb1200_uart_data_##n, \ + &kb1200_uart_config_##n, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \ + &kb1200_uart_api); + +DT_INST_FOREACH_STATUS_OKAY(KB1200_UART_INIT) From 1d08664451e98f0bc40540c760e80d145f5f2c52 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:29 +0800 Subject: [PATCH 0711/2402] dts: binding: adc: Add kb1200 adc A new adc controller addition Signed-off-by: Steven Chang --- dts/bindings/adc/ene,kb1200-adc.yaml | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 dts/bindings/adc/ene,kb1200-adc.yaml diff --git a/dts/bindings/adc/ene,kb1200-adc.yaml b/dts/bindings/adc/ene,kb1200-adc.yaml new file mode 100644 index 00000000000..f95923ebb65 --- /dev/null +++ b/dts/bindings/adc/ene,kb1200-adc.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: ENE KB1200 ADC controller + +compatible: "ene,kb1200-adc" + +include: [adc-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + "#io-channel-cells": + const: 1 + + pinctrl-0: + required: true + + pinctrl-names: + required: true + +io-channel-cells: + - input From 4d45103589de18caa6e12c9177def17058456bb4 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:29 +0800 Subject: [PATCH 0712/2402] dts: adc: kb1200 adc device nodes Add adc device nodes and pinctrl nodes for ENE KB1200 Signed-off-by: Steven Chang --- dts/arm/ene/kb1200-pinctrl.dtsi | 36 +++++++++++++++++++++++++++++++++ dts/arm/ene/kb1200.dtsi | 7 +++++++ 2 files changed, 43 insertions(+) diff --git a/dts/arm/ene/kb1200-pinctrl.dtsi b/dts/arm/ene/kb1200-pinctrl.dtsi index 056bf9ddcd9..525f46d8083 100644 --- a/dts/arm/ene/kb1200-pinctrl.dtsi +++ b/dts/arm/ene/kb1200-pinctrl.dtsi @@ -29,4 +29,40 @@ /omit-if-no-ref/ uart2_rx_gpio55: uart2_rx_gpio55 { pinmux = ; }; + /omit-if-no-ref/ adc0_gpio0a: adc0_gpio0a { + pinmux = ; + }; + /omit-if-no-ref/ adc1_gpio0b: adc1_gpio0b { + pinmux = ; + }; + /omit-if-no-ref/ adc2_gpio0c: adc2_gpio0c { + pinmux = ; + }; + /omit-if-no-ref/ adc3_gpio0d: adc3_gpio0d { + pinmux = ; + }; + /omit-if-no-ref/ adc4_gpio0e: adc4_gpio0e { + pinmux = ; + }; + /omit-if-no-ref/ adc5_gpio0f: adc5_gpio0f { + pinmux = ; + }; + /omit-if-no-ref/ adc6_gpio10: adc6_gpio10 { + pinmux = ; + }; + /omit-if-no-ref/ adc7_gpio11: adc7_gpio11 { + pinmux = ; + }; + /omit-if-no-ref/ adc8_gpio12: adc8_gpio12 { + pinmux = ; + }; + /omit-if-no-ref/ adc9_gpio13: adc9_gpio13 { + pinmux = ; + }; + /omit-if-no-ref/ adc10_gpio14: adc10_gpio14 { + pinmux = ; + }; + /omit-if-no-ref/ adc11_gpio15: adc11_gpio15 { + pinmux = ; + }; }; diff --git a/dts/arm/ene/kb1200.dtsi b/dts/arm/ene/kb1200.dtsi index 1d20b3c8e01..bf7a529c7ea 100644 --- a/dts/arm/ene/kb1200.dtsi +++ b/dts/arm/ene/kb1200.dtsi @@ -123,6 +123,13 @@ current-speed = <115200>; status = "disabled"; }; + + adc0: adc0@40130000 { + compatible = "ene,kb1200-adc"; + reg = <0x40130000 0x100>; + status = "disabled"; + #io-channel-cells = <1>; + }; }; }; From 7d12798a2228ecfd818918037a0ede83a363899e Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:30 +0800 Subject: [PATCH 0713/2402] drivers: adc: initial device driver for ENE KB1200 Add adc driver for ENE KB1200 Signed-off-by: Steven Chang --- drivers/adc/CMakeLists.txt | 1 + drivers/adc/Kconfig | 2 + drivers/adc/Kconfig.ene | 10 ++ drivers/adc/adc_ene_kb1200.c | 256 +++++++++++++++++++++++++++++++++++ 4 files changed, 269 insertions(+) create mode 100644 drivers/adc/Kconfig.ene create mode 100644 drivers/adc/adc_ene_kb1200.c diff --git a/drivers/adc/CMakeLists.txt b/drivers/adc/CMakeLists.txt index 808fb1a6698..edc1baf898a 100644 --- a/drivers/adc/CMakeLists.txt +++ b/drivers/adc/CMakeLists.txt @@ -49,3 +49,4 @@ zephyr_library_sources_ifdef(CONFIG_ADC_MAX11102_17 adc_max11102_17.c) zephyr_library_sources_ifdef(CONFIG_ADC_AD5592 adc_ad5592.c) zephyr_library_sources_ifdef(CONFIG_ADC_LTC2451 adc_ltc2451.c) zephyr_library_sources_ifdef(CONFIG_ADC_NUMAKER adc_numaker.c) +zephyr_library_sources_ifdef(CONFIG_ADC_ENE_KB1200 adc_ene_kb1200.c) diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index ac0babf123f..fb4aa3681b3 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -126,4 +126,6 @@ source "drivers/adc/Kconfig.ltc2451" source "drivers/adc/Kconfig.numaker" +source "drivers/adc/Kconfig.ene" + endif # ADC diff --git a/drivers/adc/Kconfig.ene b/drivers/adc/Kconfig.ene new file mode 100644 index 00000000000..f021314488b --- /dev/null +++ b/drivers/adc/Kconfig.ene @@ -0,0 +1,10 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config ADC_ENE_KB1200 + bool "ENE KB1200 ADC driver" + default y + depends on DT_HAS_ENE_KB1200_ADC_ENABLED + select PINCTRL + help + Enable ADC driver for ENE KB1200. diff --git a/drivers/adc/adc_ene_kb1200.c b/drivers/adc/adc_ene_kb1200.c new file mode 100644 index 00000000000..27d903abd2b --- /dev/null +++ b/drivers/adc/adc_ene_kb1200.c @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2024 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ene_kb1200_adc + +#include +#include +#include +#include +#include + +#define ADC_CONTEXT_USES_KERNEL_TIMER +#include "adc_context.h" + +struct adc_kb1200_config { + /* ADC Register base address */ + struct adc_regs *adc; + /* Pin control */ + const struct pinctrl_dev_config *pcfg; +}; + +struct adc_kb1200_data { + struct adc_context ctx; + const struct device *adc_dev; + uint16_t *buffer; + uint16_t *repeat_buffer; + uint16_t *buf_end; +}; + +/* ADC local functions */ +static bool adc_kb1200_validate_buffer_size(const struct adc_sequence *sequence) +{ + int chan_count = 0; + size_t buff_need; + uint32_t chan_mask; + + for (chan_mask = 0x80; chan_mask != 0; chan_mask >>= 1) { + if (chan_mask & sequence->channels) { + chan_count++; + } + } + + buff_need = chan_count * sizeof(uint16_t); + + if (sequence->options) { + buff_need *= 1 + sequence->options->extra_samplings; + } + + if (buff_need > sequence->buffer_size) { + return false; + } + + return true; +} +/* ADC Sample Flow (by using adc_context.h api function) + * 1. Start ADC sampling (set up flag ctx->sync) + * adc_context_start_read() -> adc_context_start_sampling() + * 2. Wait ADC sample finish (by monitor flag ctx->sync) + * adc_context_wait_for_completion + * 3. Finish ADC sample (isr clear flag ctx->sync) + * adc_context_on_sampling_done -> adc_context_complete + */ +static int adc_kb1200_start_read(const struct device *dev, const struct adc_sequence *sequence) +{ + const struct adc_kb1200_config *config = dev->config; + struct adc_kb1200_data *data = dev->data; + int error; + + if (!sequence->channels || (sequence->channels & ~BIT_MASK(ADC_MAX_CHAN))) { + printk("Invalid ADC channels.\n"); + return -EINVAL; + } + /* Fixed 10 bit resolution of ene ADC */ + if (sequence->resolution != ADC_RESOLUTION) { + printk("Unfixed 10 bit ADC resolution.\n"); + return -ENOTSUP; + } + /* Check sequence->buffer_size is enough */ + if (!adc_kb1200_validate_buffer_size(sequence)) { + printk("ADC buffer size too small.\n"); + return -ENOMEM; + } + + /* assign record buffer pointer */ + data->buffer = sequence->buffer; + data->buf_end = data->buffer + sequence->buffer_size / sizeof(uint16_t); + /* store device for adc_context_start_read() */ + data->adc_dev = dev; + /* Inform adc start sampling */ + adc_context_start_read(&data->ctx, sequence); + /* Since kb1200 adc has no irq. So need polling the adc conversion + * flag to be valid, then record adc value. + */ + uint32_t channels = (config->adc->ADCCFG & ADC_CHANNEL_BIT_MASK) >> ADC_CHANNEL_BIT_POS; + + while (channels) { + int count; + int ch_num; + + count = 0; + ch_num = find_lsb_set(channels) - 1; + /* wait valid flag */ + while (config->adc->ADCDAT[ch_num] & ADC_INVALID_VALUE) { + k_busy_wait(ADC_WAIT_TIME); + count++; + if (count >= ADC_WAIT_CNT) { + printk("ADC busy timeout...\n"); + error = -EBUSY; + break; + } + } + /* check buffer size is enough then record adc value */ + if (data->buffer < data->buf_end) { + *data->buffer = (uint16_t)(config->adc->ADCDAT[ch_num]); + data->buffer++; + } else { + error = -EINVAL; + break; + } + + /* clear completed channel */ + channels &= ~BIT(ch_num); + } + /* Besause polling the adc conversion flag. don't need wait_for_completion*/ + + /* Inform adc sampling is done */ + adc_context_on_sampling_done(&data->ctx, dev); + return error; +} + +/* ADC api functions */ +static int adc_kb1200_channel_setup(const struct device *dev, + const struct adc_channel_cfg *channel_cfg) +{ + if (channel_cfg->channel_id >= ADC_MAX_CHAN) { + printk("Invalid channel %d.\n", channel_cfg->channel_id); + return -EINVAL; + } + + if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) { + printk("Unsupported channel acquisition time.\n"); + return -ENOTSUP; + } + + if (channel_cfg->differential) { + printk("Differential channels are not supported.\n"); + return -ENOTSUP; + } + + if (channel_cfg->gain != ADC_GAIN_1) { + printk("Unsupported channel gain %d.\n", channel_cfg->gain); + return -ENOTSUP; + } + + if (channel_cfg->reference != ADC_REF_INTERNAL) { + printk("Unsupported channel reference.\n"); + return -ENOTSUP; + } + printk("ADC channel %d configured.\n", channel_cfg->channel_id); + return 0; +} + +static int adc_kb1200_read(const struct device *dev, const struct adc_sequence *sequence) +{ + struct adc_kb1200_data *data = dev->data; + int error; + + adc_context_lock(&data->ctx, false, NULL); + error = adc_kb1200_start_read(dev, sequence); + adc_context_release(&data->ctx, error); + + return error; +} + +#if defined(CONFIG_ADC_ASYNC) +static int adc_kb1200_read_async(const struct device *dev, const struct adc_sequence *sequence, + struct k_poll_signal *async) +{ + struct adc_kb1200_data *data = dev->data; + int error; + + adc_context_lock(&data->ctx, true, async); + error = adc_kb1200_start_read(dev, sequence); + adc_context_release(&data->ctx, error); + + return error; +} +#endif /* CONFIG_ADC_ASYNC */ + +/* ADC api function (using by adc_context.H function) */ +static void adc_context_start_sampling(struct adc_context *ctx) +{ + struct adc_kb1200_data *data = CONTAINER_OF(ctx, struct adc_kb1200_data, ctx); + const struct device *dev = data->adc_dev; + const struct adc_kb1200_config *config = dev->config; + + data->repeat_buffer = data->buffer; + config->adc->ADCCFG = (config->adc->ADCCFG & ~ADC_CHANNEL_BIT_MASK) | + (ctx->sequence.channels << ADC_CHANNEL_BIT_POS); + config->adc->ADCCFG |= ADC_FUNCTION_ENABLE; +} + +static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling) +{ + struct adc_kb1200_data *data = CONTAINER_OF(ctx, struct adc_kb1200_data, ctx); + + if (repeat_sampling) { + data->buffer = data->repeat_buffer; + } +} + +struct adc_driver_api adc_kb1200_api = { + .channel_setup = adc_kb1200_channel_setup, + .read = adc_kb1200_read, + .ref_internal = ADC_VREF_ANALOG, +#if defined(CONFIG_ADC_ASYNC) + .read_async = adc_kb1200_read_async, +#endif +}; + +static int adc_kb1200_init(const struct device *dev) +{ + const struct adc_kb1200_config *config = dev->config; + struct adc_kb1200_data *data = dev->data; + int ret; + + adc_context_unlock_unconditionally(&data->ctx); + /* Configure pin-mux for ADC device */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + printk("ADC pinctrl setup failed (%d).\n", ret); + return ret; + } + + return 0; +} + +#define ADC_KB1200_DEVICE(inst) \ + PINCTRL_DT_INST_DEFINE(inst); \ + static struct adc_kb1200_data adc_kb1200_data_##inst = { \ + ADC_CONTEXT_INIT_TIMER(adc_kb1200_data_##inst, ctx), \ + ADC_CONTEXT_INIT_LOCK(adc_kb1200_data_##inst, ctx), \ + ADC_CONTEXT_INIT_SYNC(adc_kb1200_data_##inst, ctx), \ + }; \ + static const struct adc_kb1200_config adc_kb1200_config_##inst = { \ + .adc = (struct adc_regs *)DT_INST_REG_ADDR(inst), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ + }; \ + DEVICE_DT_INST_DEFINE(inst, &adc_kb1200_init, NULL, &adc_kb1200_data_##inst, \ + &adc_kb1200_config_##inst, PRE_KERNEL_1, \ + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &adc_kb1200_api); + +DT_INST_FOREACH_STATUS_OKAY(ADC_KB1200_DEVICE) From 340d49e360a9f09cdb13b6f091a8fbe582d62c7a Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:30 +0800 Subject: [PATCH 0714/2402] dts: binding: pwm: Add kb1200 pwm A new pwm controller addition Signed-off-by: Steven Chang --- dts/bindings/pwm/ene,kb1200-pwm.yaml | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 dts/bindings/pwm/ene,kb1200-pwm.yaml diff --git a/dts/bindings/pwm/ene,kb1200-pwm.yaml b/dts/bindings/pwm/ene,kb1200-pwm.yaml new file mode 100644 index 00000000000..db60f553df8 --- /dev/null +++ b/dts/bindings/pwm/ene,kb1200-pwm.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: ENE, Pulse Width Modulator (PWM) node + +compatible: "ene,kb1200-pwm" + +include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true + +pwm-cells: + - channel + - period + - flags From 14c6468bddac2ebda6d33f1dccf60f3624d37698 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:30 +0800 Subject: [PATCH 0715/2402] dts: pwm: kb1200 pwm device nodes Add pwm device nodes and pinctrl nodes for ENE KB1200 Signed-off-by: Steven Chang --- dts/arm/ene/kb1200-pinctrl.dtsi | 36 ++++++++++++++ dts/arm/ene/kb1200.dtsi | 84 +++++++++++++++++++++++++++++++++ 2 files changed, 120 insertions(+) diff --git a/dts/arm/ene/kb1200-pinctrl.dtsi b/dts/arm/ene/kb1200-pinctrl.dtsi index 525f46d8083..ea587875bb4 100644 --- a/dts/arm/ene/kb1200-pinctrl.dtsi +++ b/dts/arm/ene/kb1200-pinctrl.dtsi @@ -65,4 +65,40 @@ /omit-if-no-ref/ adc11_gpio15: adc11_gpio15 { pinmux = ; }; + /omit-if-no-ref/ pwm0_gpio3a: pwm0_gpio3a { + pinmux = ; + }; + /omit-if-no-ref/ pwm1_gpio38: pwm1_gpio38 { + pinmux = ; + }; + /omit-if-no-ref/ pwm2_gpio3b: pwm2_gpio3b { + pinmux = ; + }; + /omit-if-no-ref/ pwm3_gpio26: pwm3_gpio26 { + pinmux = ; + }; + /omit-if-no-ref/ pwm4_gpio31: pwm4_gpio31 { + pinmux = ; + }; + /omit-if-no-ref/ pwm5_gpio30: pwm5_gpio30 { + pinmux = ; + }; + /omit-if-no-ref/ pwm6_gpio37: pwm6_gpio37 { + pinmux = ; + }; + /omit-if-no-ref/ pwm7_gpio23: pwm7_gpio23 { + pinmux = ; + }; + /omit-if-no-ref/ pwm8_gpio00: pwm8_gpio00 { + pinmux = ; + }; + /omit-if-no-ref/ pwm9_gpio22: pwm9_gpio22 { + pinmux = ; + }; + /omit-if-no-ref/ fanpwm0_gpio49: fanpwm0_gpio49 { + pinmux = ; + }; + /omit-if-no-ref/ fanpwm1_gpio74: fanpwm1_gpio74 { + pinmux = ; + }; }; diff --git a/dts/arm/ene/kb1200.dtsi b/dts/arm/ene/kb1200.dtsi index bf7a529c7ea..9e2ae0b4a39 100644 --- a/dts/arm/ene/kb1200.dtsi +++ b/dts/arm/ene/kb1200.dtsi @@ -130,6 +130,90 @@ status = "disabled"; #io-channel-cells = <1>; }; + + pwm0: pwm@40210000 { + compatible = "ene,kb1200-pwm"; + reg = <0x40210000 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@40210010 { + compatible = "ene,kb1200-pwm"; + reg = <0x40210010 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@40210020 { + compatible = "ene,kb1200-pwm"; + reg = <0x40210020 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@40210030 { + compatible = "ene,kb1200-pwm"; + reg = <0x40210030 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm@40210040 { + compatible = "ene,kb1200-pwm"; + reg = <0x40210040 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@40210050 { + compatible = "ene,kb1200-pwm"; + reg = <0x40210050 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@40210060 { + compatible = "ene,kb1200-pwm"; + reg = <0x40210060 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@40210070 { + compatible = "ene,kb1200-pwm"; + reg = <0x40210070 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@40210080 { + compatible = "ene,kb1200-pwm"; + reg = <0x40210080 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@40210090 { + compatible = "ene,kb1200-pwm"; + reg = <0x40210090 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + fanpwm0: pwm@40200000 { + compatible = "ene,kb1200-pwm"; + reg = <0x40200000 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + fanpwm1: pwm@40200010 { + compatible = "ene,kb1200-pwm"; + reg = <0x40200010 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; }; }; From 1147c39fe9f7d63d92801523df71f6451023e698 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:31 +0800 Subject: [PATCH 0716/2402] drivers: pwm: initial device driver for ENE KB1200 Add pwm driver for ENE KB1200 Signed-off-by: Steven Chang --- drivers/pwm/CMakeLists.txt | 1 + drivers/pwm/Kconfig | 2 + drivers/pwm/Kconfig.ene | 10 +++ drivers/pwm/pwm_ene_kb1200.c | 123 +++++++++++++++++++++++++++++++++++ 4 files changed, 136 insertions(+) create mode 100644 drivers/pwm/Kconfig.ene create mode 100644 drivers/pwm/pwm_ene_kb1200.c diff --git a/drivers/pwm/CMakeLists.txt b/drivers/pwm/CMakeLists.txt index 2bf100aceb2..2ac86d3e38e 100644 --- a/drivers/pwm/CMakeLists.txt +++ b/drivers/pwm/CMakeLists.txt @@ -40,6 +40,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_XMC4XXX_CCU8 pwm_xmc4xxx_ccu8.c) zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_CTIMER pwm_mcux_ctimer.c) zephyr_library_sources_ifdef(CONFIG_PWM_NUMAKER pwm_numaker.c) zephyr_library_sources_ifdef(CONFIG_PWM_NXP_S32_EMIOS pwm_nxp_s32_emios.c) +zephyr_library_sources_ifdef(CONFIG_PWM_ENE_KB1200 pwm_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE pwm_handlers.c) zephyr_library_sources_ifdef(CONFIG_PWM_CAPTURE pwm_capture.c) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8942ebd89b0..d8a412078f9 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -100,4 +100,6 @@ source "drivers/pwm/Kconfig.numaker" source "drivers/pwm/Kconfig.nxp_s32_emios" +source "drivers/pwm/Kconfig.ene" + endif # PWM diff --git a/drivers/pwm/Kconfig.ene b/drivers/pwm/Kconfig.ene new file mode 100644 index 00000000000..612c52a77db --- /dev/null +++ b/drivers/pwm/Kconfig.ene @@ -0,0 +1,10 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config PWM_ENE_KB1200 + bool "ENE KB1200 PWM driver" + default y + depends on DT_HAS_ENE_KB1200_PWM_ENABLED + select PINCTRL + help + This option enables the PWM driver for KB1200 processors. diff --git a/drivers/pwm/pwm_ene_kb1200.c b/drivers/pwm/pwm_ene_kb1200.c new file mode 100644 index 00000000000..a54afa878b0 --- /dev/null +++ b/drivers/pwm/pwm_ene_kb1200.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2024 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ene_kb1200_pwm + +#include +#include +#include + +/* Device config */ +struct pwm_kb1200_config { + /* pwm controller base address */ + struct pwm_regs *pwm; + const struct pinctrl_dev_config *pcfg; +}; + +/* Driver data */ +struct pwm_kb1200_data { + /* PWM cycles per second */ + uint32_t cycles_per_sec; +}; + +/* PWM api functions */ +static int pwm_kb1200_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles, + uint32_t pulse_cycles, pwm_flags_t flags) +{ + /* Single channel for each pwm device */ + ARG_UNUSED(channel); + const struct pwm_kb1200_config *config = dev->config; + int prescaler; + uint32_t high_len; + uint32_t cycle_len; + + /* + * Calculate PWM prescaler that let period_cycles map to + * maximum pwm period cycles and won't exceed it. + * Then prescaler = ceil (period_cycles / pwm_max_period_cycles) + */ + prescaler = DIV_ROUND_UP(period_cycles, PWM_MAX_CYCLES); + if (prescaler > PWM_MAX_PRESCALER) { + return -EINVAL; + } + + /* If pulse_cycles is 0, switch PWM off and return. */ + if (pulse_cycles == 0) { + config->pwm->PWMCFG &= ~PWM_ENABLE; + return 0; + } + + high_len = (pulse_cycles / prescaler); + cycle_len = (period_cycles / prescaler); + + /* Select PWM inverted polarity (ie. active-low pulse). */ + if (flags & PWM_POLARITY_INVERTED) { + high_len = cycle_len - high_len; + } + + /* Set PWM prescaler. */ + config->pwm->PWMCFG = (config->pwm->PWMCFG & ~GENMASK(13, 8)) | ((prescaler - 1) << 8); + + /* + * period_cycles: PWM Cycle Length + * pulse_cycles : PWM High Length + */ + config->pwm->PWMHIGH = high_len; + config->pwm->PWMCYC = cycle_len; + + /* Start pwm */ + config->pwm->PWMCFG |= PWM_ENABLE; + + return 0; +} + +static int pwm_kb1200_get_cycles_per_sec(const struct device *dev, uint32_t channel, + uint64_t *cycles) +{ + /* Single channel for each pwm device */ + ARG_UNUSED(channel); + ARG_UNUSED(dev); + + if (cycles) { + /* User does not have to know about lowest clock, + * the driver will select the most relevant one. + */ + *cycles = PWM_INPUT_FREQ_HI; /*32Mhz*/ + } + return 0; +} + +static const struct pwm_driver_api pwm_kb1200_driver_api = { + .set_cycles = pwm_kb1200_set_cycles, + .get_cycles_per_sec = pwm_kb1200_get_cycles_per_sec, +}; + +static int pwm_kb1200_init(const struct device *dev) +{ + int ret; + const struct pwm_kb1200_config *config = dev->config; + + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret != 0) { + return ret; + } + config->pwm->PWMCFG = PWM_SOURCE_CLK_32M | PWM_RULE1 | PWM_PUSHPULL; + + return 0; +} + +#define KB1200_PWM_INIT(inst) \ + PINCTRL_DT_INST_DEFINE(inst); \ + static const struct pwm_kb1200_config pwm_kb1200_cfg_##inst = { \ + .pwm = (struct pwm_regs *)DT_INST_REG_ADDR(inst), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ + }; \ + static struct pwm_kb1200_data pwm_kb1200_data_##inst; \ + DEVICE_DT_INST_DEFINE(inst, &pwm_kb1200_init, NULL, &pwm_kb1200_data_##inst, \ + &pwm_kb1200_cfg_##inst, PRE_KERNEL_1, CONFIG_PWM_INIT_PRIORITY, \ + &pwm_kb1200_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(KB1200_PWM_INIT) From 1b4921623de4ffd9da6ed472e83ffb3b8aebd034 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:31 +0800 Subject: [PATCH 0717/2402] dts: binding: tach: Add kb1200 tach A new tach controller addition Signed-off-by: Steven Chang --- dts/bindings/tach/ene,kb1200-tach.yaml | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 dts/bindings/tach/ene,kb1200-tach.yaml diff --git a/dts/bindings/tach/ene,kb1200-tach.yaml b/dts/bindings/tach/ene,kb1200-tach.yaml new file mode 100644 index 00000000000..4f89d9a882d --- /dev/null +++ b/dts/bindings/tach/ene,kb1200-tach.yaml @@ -0,0 +1,34 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: ENE, KB1200-Tachometer node + +compatible: "ene,kb1200-tach" + +include: [tach.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + pulses-per-round: + required: true + type: int + description: number of pulses (holes) per round of tachometer's input (encoder) + + sample-time-us: + required: true + type: int + enum: + - 2 + - 8 + - 16 + - 64 + description: | + sampling time of tachometer. Please notice that it must be 2/8/16/64 us. + + pinctrl-0: + required: true + + pinctrl-names: + required: true From d0bfe81ce9d0883be92b0d0ff3cecf36f5e3441a Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:32 +0800 Subject: [PATCH 0718/2402] dts: tach: kb1200 tach device nodes Add tach device nodes and pinctrl nodes for ENE KB1200 Signed-off-by: Steven Chang --- dts/arm/ene/kb1200-pinctrl.dtsi | 12 ++++++++++++ dts/arm/ene/kb1200.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/dts/arm/ene/kb1200-pinctrl.dtsi b/dts/arm/ene/kb1200-pinctrl.dtsi index ea587875bb4..d0d0586c888 100644 --- a/dts/arm/ene/kb1200-pinctrl.dtsi +++ b/dts/arm/ene/kb1200-pinctrl.dtsi @@ -101,4 +101,16 @@ /omit-if-no-ref/ fanpwm1_gpio74: fanpwm1_gpio74 { pinmux = ; }; + /omit-if-no-ref/ tach0_gpio48: tach0_gpio48 { + pinmux = ; + }; + /omit-if-no-ref/ tach1_gpio4e: tach1_gpio4e { + pinmux = ; + }; + /omit-if-no-ref/ tach2_gpio0e: tach2_gpio0e { + pinmux = ; + }; + /omit-if-no-ref/ tach3_gpio43: tach3_gpio43 { + pinmux = ; + }; }; diff --git a/dts/arm/ene/kb1200.dtsi b/dts/arm/ene/kb1200.dtsi index 9e2ae0b4a39..21447ef3b03 100644 --- a/dts/arm/ene/kb1200.dtsi +++ b/dts/arm/ene/kb1200.dtsi @@ -214,6 +214,30 @@ #pwm-cells = <3>; status = "disabled"; }; + + tach0: tach@40100000 { + compatible = "ene,kb1200-tach"; + reg = <0x40100000 0x10>; + status = "disabled"; + }; + + tach1: tach@40100010 { + compatible = "ene,kb1200-tach"; + reg = <0x40100010 0x10>; + status = "disabled"; + }; + + tach2: tach@40100020 { + compatible = "ene,kb1200-tach"; + reg = <0x40100020 0x10>; + status = "disabled"; + }; + + tach3: tach@40100030 { + compatible = "ene,kb1200-tach"; + reg = <0x40100030 0x10>; + status = "disabled"; + }; }; }; From 1b028ca2ceeb7e9bfcde84bc8d097981c0dcf0cc Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:32 +0800 Subject: [PATCH 0719/2402] drivers: tach: initial device driver for ENE KB1200 Add tachmeter driver for ENE KB1200 Signed-off-by: Steven Chang --- drivers/sensor/CMakeLists.txt | 1 + drivers/sensor/Kconfig | 1 + drivers/sensor/ene_tach_kb1200/CMakeLists.txt | 4 + drivers/sensor/ene_tach_kb1200/Kconfig | 12 ++ .../sensor/ene_tach_kb1200/tach_ene_kb1200.c | 143 ++++++++++++++++++ 5 files changed, 161 insertions(+) create mode 100644 drivers/sensor/ene_tach_kb1200/CMakeLists.txt create mode 100644 drivers/sensor/ene_tach_kb1200/Kconfig create mode 100644 drivers/sensor/ene_tach_kb1200/tach_ene_kb1200.c diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index d6e60d6b380..86f65c04ee4 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -172,6 +172,7 @@ add_subdirectory_ifdef(CONFIG_WSEN_PADS wsen_pads) add_subdirectory_ifdef(CONFIG_WSEN_PDUS wsen_pdus) add_subdirectory_ifdef(CONFIG_WSEN_TIDS wsen_tids) add_subdirectory_ifdef(CONFIG_XMC4XXX_TEMP xmc4xxx_temp) +add_subdirectory_ifdef(CONFIG_TACH_ENE_KB1200 ene_tach_kb1200) zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/sensor.h) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index d3957f257b9..f939950d01c 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -252,5 +252,6 @@ source "drivers/sensor/wsen_pads/Kconfig" source "drivers/sensor/wsen_pdus/Kconfig" source "drivers/sensor/wsen_tids/Kconfig" source "drivers/sensor/xmc4xxx_temp/Kconfig" +source "drivers/sensor/ene_tach_kb1200/Kconfig" endif # SENSOR diff --git a/drivers/sensor/ene_tach_kb1200/CMakeLists.txt b/drivers/sensor/ene_tach_kb1200/CMakeLists.txt new file mode 100644 index 00000000000..a99828fc6e5 --- /dev/null +++ b/drivers/sensor/ene_tach_kb1200/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources_ifdef(CONFIG_TACH_ENE_KB1200 tach_ene_kb1200.c) diff --git a/drivers/sensor/ene_tach_kb1200/Kconfig b/drivers/sensor/ene_tach_kb1200/Kconfig new file mode 100644 index 00000000000..fa0555cf937 --- /dev/null +++ b/drivers/sensor/ene_tach_kb1200/Kconfig @@ -0,0 +1,12 @@ +# KB1200 tachometer sensor configuration options + +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config TACH_ENE_KB1200 + bool "ENE KB1200 tachometer sensor" + default y + depends on DT_HAS_ENE_KB1200_TACH_ENABLED + select PINCTRL + help + Enable tachometer sensor for ENE KB1200. diff --git a/drivers/sensor/ene_tach_kb1200/tach_ene_kb1200.c b/drivers/sensor/ene_tach_kb1200/tach_ene_kb1200.c new file mode 100644 index 00000000000..d7493109e47 --- /dev/null +++ b/drivers/sensor/ene_tach_kb1200/tach_ene_kb1200.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2024 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ene_kb1200_tach + +#include +#include +#include + +/* Device config */ +struct tach_kb1200_config { + /* tachometer controller base address */ + struct tacho_regs *tacho; + /* number of pulses (holes) per round of tachometer's input (encoder) */ + int pulses_per_round; + /* sampling clock timing of tachometer (us) */ + int sample_time_us; + const struct pinctrl_dev_config *pcfg; +}; + +/* Driver data */ +struct tach_kb1200_data { + /* Captured counts of tachometer */ + uint32_t capture; +}; + +/* TACH local functions */ +static int tach_kb1200_configure(const struct device *dev) +{ + const struct tach_kb1200_config *const config = dev->config; + uint8_t sample_us = 0; + + /* Configure clock module and its frequency of tachometer */ + switch (config->sample_time_us) { + case 2: + sample_us = TACHO_MONITOR_CLK_2US; + break; + case 8: + sample_us = TACHO_MONITOR_CLK_8US; + break; + case 16: + sample_us = TACHO_MONITOR_CLK_16US; + break; + case 64: + sample_us = TACHO_MONITOR_CLK_64US; + break; + default: + return -ENOTSUP; + } + config->tacho->TACHOCFG = (sample_us << 4) | TACHO_FUNCTION_ENABLE; + + return 0; +} + +/* TACH api functions */ +int tach_kb1200_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + ARG_UNUSED(chan); + struct tach_kb1200_data *const data = dev->data; + const struct tach_kb1200_config *const config = dev->config; + + /* Check tachometer timeout flag*/ + if (config->tacho->TACHOPF & TACHO_TIMEOUT_EVENT) { + /* Clear timeout flags and update flag */ + config->tacho->TACHOPF = (TACHO_TIMEOUT_EVENT | TACHO_UPDATE_EVENT); + data->capture = 0; + return 0; + } + + /* Check tachometer update flag is set */ + if (config->tacho->TACHOPF & TACHO_UPDATE_EVENT) { + /* Clear pending flags */ + config->tacho->TACHOPF = TACHO_UPDATE_EVENT; + /* Save captured count */ + data->capture = config->tacho->TACHOCV & TACHO_CNT_MAX_VALUE; + } + return 0; +} + +static int tach_kb1200_channel_get(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + struct tach_kb1200_data *const data = dev->data; + const struct tach_kb1200_config *const config = dev->config; + + if (chan != SENSOR_CHAN_RPM) { + return -ENOTSUP; + } + + if (data->capture > 0) { + /* + * RPM = (60000000/t) / n + * t: One Pulses length(us) = sample_time_us * cnt + * n: One Round pulses Number + */ + val->val1 = (60000000 / (config->sample_time_us * data->capture)) / + config->pulses_per_round; + } else { + val->val1 = 0U; + } + val->val2 = 0U; + + return 0; +} + +/* TACH driver registration */ +static int tach_kb1200_init(const struct device *dev) +{ + int ret; + const struct tach_kb1200_config *config = dev->config; + + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret != 0) { + return ret; + } + + tach_kb1200_configure(dev); + + return 0; +} + +static const struct sensor_driver_api tach_kb1200_driver_api = { + .sample_fetch = tach_kb1200_sample_fetch, + .channel_get = tach_kb1200_channel_get, +}; + +#define KB1200_TACH_INIT(inst) \ + PINCTRL_DT_INST_DEFINE(inst); \ + static const struct tach_kb1200_config tach_cfg_##inst = { \ + .tacho = (struct tacho_regs *)DT_INST_REG_ADDR(inst), \ + .pulses_per_round = DT_INST_PROP(inst, pulses_per_round), \ + .sample_time_us = DT_INST_PROP(inst, sample_time_us), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ + }; \ + static struct tach_kb1200_data tach_data_##inst; \ + SENSOR_DEVICE_DT_INST_DEFINE(inst, tach_kb1200_init, NULL, &tach_data_##inst, \ + &tach_cfg_##inst, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, \ + &tach_kb1200_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(KB1200_TACH_INIT) From c1bec14de027266fe92dbb586f3c8c993fa22ba8 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:33 +0800 Subject: [PATCH 0720/2402] dts: binding: watchdog: Add kb1200 watchdog A new watchdog controller addition Signed-off-by: Steven Chang --- dts/bindings/watchdog/ene,kb1200-watchdog.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 dts/bindings/watchdog/ene,kb1200-watchdog.yaml diff --git a/dts/bindings/watchdog/ene,kb1200-watchdog.yaml b/dts/bindings/watchdog/ene,kb1200-watchdog.yaml new file mode 100644 index 00000000000..9a05e6c4fed --- /dev/null +++ b/dts/bindings/watchdog/ene,kb1200-watchdog.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: ENE watchdog timer + +include: [base.yaml] + +compatible: "ene,kb1200-watchdog" + +properties: + reg: + required: true + + interrupts: + required: true From 4fe1a856584c6d5b13e95143be81ff7293dbcfbb Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:33 +0800 Subject: [PATCH 0721/2402] dts: watchdog: kb1200 watchdog device nodes Add watchdog device nodes and pinctrl nodes for ENE KB1200 Signed-off-by: Steven Chang --- dts/arm/ene/kb1200.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/dts/arm/ene/kb1200.dtsi b/dts/arm/ene/kb1200.dtsi index 21447ef3b03..0d974998b29 100644 --- a/dts/arm/ene/kb1200.dtsi +++ b/dts/arm/ene/kb1200.dtsi @@ -238,6 +238,13 @@ reg = <0x40100030 0x10>; status = "disabled"; }; + + wdt0: watchdog@40060000 { + compatible = "ene,kb1200-watchdog"; + reg = <0x40060000 0x100>; + interrupts = <0 0>; + status = "disabled"; + }; }; }; From 5c354ca05523933b89ba4d49c18df11f8f767db6 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:34 +0800 Subject: [PATCH 0722/2402] drivers: watchdog: initial device driver for ENE KB1200 Add watchdog driver for ENE KB1200 Signed-off-by: Steven Chang --- drivers/watchdog/CMakeLists.txt | 1 + drivers/watchdog/Kconfig | 2 + drivers/watchdog/Kconfig.ene | 9 ++ drivers/watchdog/wdt_ene_kb1200.c | 173 ++++++++++++++++++++++++++++++ 4 files changed, 185 insertions(+) create mode 100644 drivers/watchdog/Kconfig.ene create mode 100644 drivers/watchdog/wdt_ene_kb1200.c diff --git a/drivers/watchdog/CMakeLists.txt b/drivers/watchdog/CMakeLists.txt index 9414b865b55..cfec0ef05fe 100644 --- a/drivers/watchdog/CMakeLists.txt +++ b/drivers/watchdog/CMakeLists.txt @@ -41,6 +41,7 @@ zephyr_library_sources_ifdef(CONFIG_WDT_OPENTITAN wdt_opentitan.c) zephyr_library_sources_ifdef(CONFIG_WDT_AMBIQ wdt_ambiq.c) zephyr_library_sources_ifdef(CONFIG_WDT_XMC4XXX wdt_xmc4xxx.c) zephyr_library_sources_ifdef(CONFIG_WWDT_NUMAKER wdt_wwdt_numaker.c) +zephyr_library_sources_ifdef(CONFIG_WDT_ENE_KB1200 wdt_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_WDT_DW wdt_dw.c wdt_dw_common.c) zephyr_library_sources_ifdef(CONFIG_WDT_INTEL_ADSP wdt_intel_adsp.c wdt_dw_common.c) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f10dc5582e8..96cc4a61e0d 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -124,4 +124,6 @@ source "drivers/watchdog/Kconfig.xmc4xxx" source "drivers/watchdog/Kconfig.numaker" +source "drivers/watchdog/Kconfig.ene" + endif # WATCHDOG diff --git a/drivers/watchdog/Kconfig.ene b/drivers/watchdog/Kconfig.ene new file mode 100644 index 00000000000..114c69b4c2b --- /dev/null +++ b/drivers/watchdog/Kconfig.ene @@ -0,0 +1,9 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config WDT_ENE_KB1200 + bool "ENE KB1200 watchdog driver" + default y + depends on DT_HAS_ENE_KB1200_WATCHDOG_ENABLED + help + This option enables the KB1200 watchdog driver. diff --git a/drivers/watchdog/wdt_ene_kb1200.c b/drivers/watchdog/wdt_ene_kb1200.c new file mode 100644 index 00000000000..008b4623de8 --- /dev/null +++ b/drivers/watchdog/wdt_ene_kb1200.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2024 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ene_kb1200_watchdog + +#include +#include +#include +#include +#include + +/* Device config */ +struct wdt_kb1200_config { + struct wdt_regs *wdt; +}; + +/* Device data */ +struct wdt_kb1200_data { + wdt_callback_t cb; + bool timeout_installed; +}; + +/* WDT api functions */ +static int wdt_kb1200_setup(const struct device *dev, uint8_t options) +{ + struct wdt_kb1200_config const *cfg = dev->config; + struct wdt_kb1200_data *data = dev->data; + + if (!data->timeout_installed) { + printk("No valid WDT timeout installed"); + return -EINVAL; + } + if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) { + printk("WDT_OPT_PAUSE_HALTED_BY_DBG is not supported"); + return -ENOTSUP; + } + + /* Setting Clock Source */ + if (options & WDT_OPT_PAUSE_IN_SLEEP) { + cfg->wdt->WDTCFG = WDT_ADCO32K; + } else { + cfg->wdt->WDTCFG = WDT_PHER32K; + } + /* Clear Pending Flag */ + cfg->wdt->WDTPF = (WDT_HALF_WAY_EVENT | WDT_RESET_EVENT); + /* WDT enable */ + cfg->wdt->WDTCFG |= WDT_FUNCTON_ENABLE; + + return 0; +} + +static int wdt_kb1200_disable(const struct device *dev) +{ + struct wdt_kb1200_config const *cfg = dev->config; + struct wdt_kb1200_data *data = dev->data; + + if (!(cfg->wdt->WDTCFG & WDT_FUNCTON_ENABLE)) { + return -EALREADY; + } + /* WDT disable, write bit 7~4 = 1001b */ + cfg->wdt->WDTCFG = (cfg->wdt->WDTCFG & ~WDT_FUNCTON_ENABLE) | WDT_DISABLE_PASSWORD; + /* Clear Pending Flag */ + cfg->wdt->WDTPF = (WDT_HALF_WAY_EVENT | WDT_RESET_EVENT); + /* Need disable IE,or the wdt-half-event interrupt will be entered */ + cfg->wdt->WDTIE &= ~WDT_HALF_WAY_EVENT; + data->timeout_installed = false; + + return 0; +} + +static int wdt_kb1200_install_timeout(const struct device *dev, + const struct wdt_timeout_cfg *config) +{ + struct wdt_kb1200_config const *cfg = dev->config; + struct wdt_kb1200_data *data = dev->data; + + /* Watchdog Counter Match Value */ + if (config->window.min > 0U) { + data->timeout_installed = false; + return -EINVAL; + } + cfg->wdt->WDTM = (config->window.max) / WDT_SAMPLE_TIME; + /* (HW design) The counter match value must be >= 3 */ + if (cfg->wdt->WDTM < WDT_MIN_CNT) { + data->timeout_installed = false; + return -EINVAL; + } + + /* Watchdog behavior flags */ + if ((config->flags & WDT_FLAG_RESET_MASK) == WDT_FLAG_RESET_SOC) { + /* Reset: SoC */ + cfg->wdt->WDTCFG_T = WDT_RESET_WHOLE_CHIP_WO_GPIO; + } else if ((config->flags & WDT_FLAG_RESET_MASK) == WDT_FLAG_RESET_CPU_CORE) { + /* Reset: CPU core */ + cfg->wdt->WDTCFG_T = WDT_RESET_WHOLE_CHIP; + } else { + /* Reset: none */ + cfg->wdt->WDTCFG_T = WDT_RESET_ONLY_MCU; + } + + /* Watchdog callback function */ + data->cb = config->callback; + if (data->cb) { + cfg->wdt->WDTIE |= WDT_HALF_WAY_EVENT; + } else { + /* If the callback function is NULL,the SoC will be reset directly. + * But still need enable interrupt. + */ + cfg->wdt->WDTIE |= WDT_HALF_WAY_EVENT; + } + data->timeout_installed = true; + + return 0; +} + +static int wdt_kb1200_feed(const struct device *dev, int channel_id) +{ + struct wdt_kb1200_config const *cfg = dev->config; + + ARG_UNUSED(dev); + ARG_UNUSED(channel_id); + + if (!(cfg->wdt->WDTCFG & WDT_FUNCTON_ENABLE)) { + return -EINVAL; + } + /* Re-enable to reset counter */ + cfg->wdt->WDTCFG |= WDT_FUNCTON_ENABLE; + /* Clear Pending Flag */ + cfg->wdt->WDTPF = WDT_HALF_WAY_EVENT; + + return 0; +} + +static void wdt_kb1200_isr(const struct device *dev) +{ + struct wdt_kb1200_data *data = dev->data; + + if (data->cb) { + data->cb(dev, 0); + } +} + +static const struct wdt_driver_api wdt_kb1200_api = { + .setup = wdt_kb1200_setup, + .disable = wdt_kb1200_disable, + .install_timeout = wdt_kb1200_install_timeout, + .feed = wdt_kb1200_feed, +}; + +static int wdt_kb1200_init(const struct device *dev) +{ + if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) { + wdt_kb1200_disable(dev); + } + + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), wdt_kb1200_isr, + DEVICE_DT_INST_GET(0), 0); + irq_enable(DT_INST_IRQN(0)); + + return 0; +} + +static const struct wdt_kb1200_config wdt_kb1200_config = { + .wdt = (struct wdt_regs *)DT_INST_REG_ADDR(0), +}; + +static struct wdt_kb1200_data wdt_kb1200_dev_data; + +DEVICE_DT_INST_DEFINE(0, wdt_kb1200_init, NULL, &wdt_kb1200_dev_data, &wdt_kb1200_config, + PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_kb1200_api); From 9cf861d6b5700f26cffb890c891f8ad3fc4258c1 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:34 +0800 Subject: [PATCH 0723/2402] dts: binding: i2c: Add kb1200 i2c A new i2c controller addition Signed-off-by: Steven Chang --- dts/bindings/i2c/ene,kb1200-i2c.yaml | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 dts/bindings/i2c/ene,kb1200-i2c.yaml diff --git a/dts/bindings/i2c/ene,kb1200-i2c.yaml b/dts/bindings/i2c/ene,kb1200-i2c.yaml new file mode 100644 index 00000000000..3a20c8d05fb --- /dev/null +++ b/dts/bindings/i2c/ene,kb1200-i2c.yaml @@ -0,0 +1,21 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: ENE I2C/SMB controller + +compatible: "ene,kb1200-i2c" + +include: [i2c-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + interrupts: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true From b27fac08de965ff36fe697dedb1c2b13e4acdef4 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:34 +0800 Subject: [PATCH 0724/2402] dts: i2c: kb1200 i2c device nodes Add i2c device nodes and pinctrl nodes for ENE KB1200 Signed-off-by: Steven Chang --- dts/arm/ene/kb1200-pinctrl.dtsi | 80 +++++++++++++++++++++++++++++ dts/arm/ene/kb1200.dtsi | 90 +++++++++++++++++++++++++++++++++ 2 files changed, 170 insertions(+) diff --git a/dts/arm/ene/kb1200-pinctrl.dtsi b/dts/arm/ene/kb1200-pinctrl.dtsi index d0d0586c888..d65a4b4849b 100644 --- a/dts/arm/ene/kb1200-pinctrl.dtsi +++ b/dts/arm/ene/kb1200-pinctrl.dtsi @@ -113,4 +113,84 @@ /omit-if-no-ref/ tach3_gpio43: tach3_gpio43 { pinmux = ; }; + /omit-if-no-ref/ i2c0_clk_gpio2c: i2c0_clk_gpio2c { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c0_dat_gpio2d: i2c0_dat_gpio2d { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c1_clk_gpio2e: i2c1_clk_gpio2e { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c1_dat_gpio2f: i2c1_dat_gpio2f { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c2_clk_gpio32: i2c2_clk_gpio32 { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c2_dat_gpio33: i2c2_dat_gpio33 { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c3_clk_gpio34: i2c3_clk_gpio34 { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c3_dat_gpio35: i2c3_dat_gpio35 { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c4_clk_gpio38: i2c4_clk_gpio38 { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c4_dat_gpio39: i2c4_dat_gpio39 { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c5_clk_gpio4a: i2c5_clk_gpio4a { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c5_dat_gpio4b: i2c5_dat_gpio4b { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c6_clk_gpio4c: i2c6_clk_gpio4c { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c6_dat_gpio4d: i2c6_dat_gpio4d { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c7_clk_gpio50: i2c7_clk_gpio50 { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c7_dat_gpio51: i2c7_dat_gpio51 { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c8_clk_gpio70: i2c8_clk_gpio70 { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c8_dat_gpio71: i2c8_dat_gpio71 { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c9_clk_gpio72: i2c9_clk_gpio72 { + pinmux = ; + bias-pull-up; + }; + /omit-if-no-ref/ i2c9_dat_gpio73: i2c9_dat_gpio73 { + pinmux = ; + bias-pull-up; + }; }; diff --git a/dts/arm/ene/kb1200.dtsi b/dts/arm/ene/kb1200.dtsi index 0d974998b29..d14dc7e98d8 100644 --- a/dts/arm/ene/kb1200.dtsi +++ b/dts/arm/ene/kb1200.dtsi @@ -245,6 +245,96 @@ interrupts = <0 0>; status = "disabled"; }; + + i2c0: i2c@40340000 { + compatible = "ene,kb1200-i2c"; + reg = <0x40340000 0x1000>; + interrupts = <17 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@40341000 { + compatible = "ene,kb1200-i2c"; + reg = <0x40341000 0x1000>; + interrupts = <17 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@40342000 { + compatible = "ene,kb1200-i2c"; + reg = <0x40342000 0x1000>; + interrupts = <17 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@40343000 { + compatible = "ene,kb1200-i2c"; + reg = <0x40343000 0x1000>; + interrupts = <17 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@40344000 { + compatible = "ene,kb1200-i2c"; + reg = <0x40344000 0x1000>; + interrupts = <17 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@40345000 { + compatible = "ene,kb1200-i2c"; + reg = <0x40345000 0x1000>; + interrupts = <17 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@40346000 { + compatible = "ene,kb1200-i2c"; + reg = <0x40346000 0x1000>; + interrupts = <17 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@40347000 { + compatible = "ene,kb1200-i2c"; + reg = <0x40347000 0x1000>; + interrupts = <17 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@40348000 { + compatible = "ene,kb1200-i2c"; + reg = <0x40348000 0x1000>; + interrupts = <17 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@40349000 { + compatible = "ene,kb1200-i2c"; + reg = <0x40349000 0x1000>; + interrupts = <17 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; From b231905e387b29f03c404ca3655664fa23d533c7 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:35 +0800 Subject: [PATCH 0725/2402] drivers: i2c: initial device driver for ENE KB1200 Add i2c driver for ENE KB1200 Signed-off-by: Steven Chang --- drivers/i2c/CMakeLists.txt | 1 + drivers/i2c/Kconfig | 1 + drivers/i2c/Kconfig.ene | 10 + drivers/i2c/i2c_ene_kb1200.c | 354 +++++++++++++++++++++++++++++++++++ 4 files changed, 366 insertions(+) create mode 100644 drivers/i2c/Kconfig.ene create mode 100644 drivers/i2c/i2c_ene_kb1200.c diff --git a/drivers/i2c/CMakeLists.txt b/drivers/i2c/CMakeLists.txt index 53d924850f2..13878b66d3b 100644 --- a/drivers/i2c/CMakeLists.txt +++ b/drivers/i2c/CMakeLists.txt @@ -63,6 +63,7 @@ zephyr_library_sources_ifdef(CONFIG_I2C_XILINX_AXI i2c_xilinx_axi.c) zephyr_library_sources_ifdef(CONFIG_I2C_MCHP_MSS i2c_mchp_mss.c) zephyr_library_sources_ifdef(CONFIG_I2C_SEDI i2c_sedi.c) zephyr_library_sources_ifdef(CONFIG_I2C_AMBIQ i2c_ambiq.c) +zephyr_library_sources_ifdef(CONFIG_I2C_ENE_KB1200 i2c_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_GPIO_I2C_SWITCH gpio_i2c_switch.c) zephyr_library_sources_ifdef(CONFIG_I2C_NUMAKER i2c_numaker.c) diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index bba632dfe95..c0bcda79090 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -119,6 +119,7 @@ source "drivers/i2c/Kconfig.sedi" source "drivers/i2c/Kconfig.ambiq" source "drivers/i2c/Kconfig.numaker" source "drivers/i2c/Kconfig.mcux" +source "drivers/i2c/Kconfig.ene" config I2C_INIT_PRIORITY int "Init priority" diff --git a/drivers/i2c/Kconfig.ene b/drivers/i2c/Kconfig.ene new file mode 100644 index 00000000000..7b9d84ac6b4 --- /dev/null +++ b/drivers/i2c/Kconfig.ene @@ -0,0 +1,10 @@ +# Copyright (c) 2024 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config I2C_ENE_KB1200 + bool "ENE KB1200 I2C driver" + default y + depends on DT_HAS_ENE_KB1200_I2C_ENABLED + select PINCTRL + help + Enable the ENE KB1200 I2C driver. diff --git a/drivers/i2c/i2c_ene_kb1200.c b/drivers/i2c/i2c_ene_kb1200.c new file mode 100644 index 00000000000..3c78932e0a0 --- /dev/null +++ b/drivers/i2c/i2c_ene_kb1200.c @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2024 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ene_kb1200_i2c + +#include +#include +#include +#include +#include + +struct i2c_kb1200_config { + struct fsmbm_regs *fsmbm; + const struct pinctrl_dev_config *pcfg; +}; + +struct i2c_kb1200_data { + struct k_sem mutex; + volatile uint8_t *msg_buf; + volatile uint32_t msg_len; + volatile uint8_t msg_flags; + volatile int state; + volatile uint32_t index; + volatile int err_code; +}; + +/* I2C Master local functions */ +static void i2c_kb1200_isr(const struct device *dev) +{ + const struct i2c_kb1200_config *config = dev->config; + struct i2c_kb1200_data *data = dev->data; + + if (data->state == STATE_SENDING) { + if (config->fsmbm->FSMBMPF & FSMBM_BLOCK_FINISH_EVENT) { + /* continue block */ + uint32_t remain = data->msg_len - data->index; + uint32_t send_bytes = + remain > FSMBM_BUFFER_SIZE ? FSMBM_BUFFER_SIZE : remain; + memcpy((void *)&config->fsmbm->FSMBMDAT[0], + (void *)&data->msg_buf[data->index], send_bytes); + data->index += send_bytes; + /* Increase CNT setting let hw can't match counter */ + config->fsmbm->FSMBMPRTC_C += send_bytes; + /* If it was the last protocol recover the correct length value*/ + if (data->msg_len == data->index) { + config->fsmbm->FSMBMPRTC_C -= 1; + } + config->fsmbm->FSMBMPF = FSMBM_BLOCK_FINISH_EVENT; + } else if (config->fsmbm->FSMBMPF & FSMBM_COMPLETE_EVENT) { + /* complete */ + if (((config->fsmbm->FSMBMSTS & FSMBM_STS_MASK) == FSMBM_SMBUS_BUSY) && + ((config->fsmbm->FSMBMFRT & ___STOP) == ___NONE)) { + /* while packet finish without STOP, the error message is + * FSMBM_SMBUS_BUSY + */ + data->err_code = 0; + } else { + data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK; + } + data->state = STATE_COMPLETE; + config->fsmbm->FSMBMPF = FSMBM_COMPLETE_EVENT; + } else { + data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK; + data->state = STATE_COMPLETE; + } + } else if (data->state == STATE_RECEIVING) { + uint32_t remain = data->msg_len - data->index; + uint32_t receive_bytes = (remain > FSMBM_BUFFER_SIZE) ? FSMBM_BUFFER_SIZE : remain; + + memcpy((void *)&data->msg_buf[data->index], (void *)&config->fsmbm->FSMBMDAT[0], + receive_bytes); + data->index += receive_bytes; + if (config->fsmbm->FSMBMPF & FSMBM_BLOCK_FINISH_EVENT) { + /* continue block */ + /* Check next protocl information */ + remain = data->msg_len - data->index; + uint32_t NextLen = + (remain > FSMBM_BUFFER_SIZE) ? FSMBM_BUFFER_SIZE : remain; + /* Increase CNT setting let hw can't match counter */ + config->fsmbm->FSMBMPRTC_C += NextLen; + /* If it was the last protocol recover the correct length value */ + if (data->msg_len == (data->index + NextLen)) { + config->fsmbm->FSMBMPRTC_C -= 1; + } + config->fsmbm->FSMBMPF = FSMBM_BLOCK_FINISH_EVENT; + } else if (config->fsmbm->FSMBMPF & FSMBM_COMPLETE_EVENT) { + /* complete */ + if (((config->fsmbm->FSMBMSTS & FSMBM_STS_MASK) == FSMBM_SMBUS_BUSY) && + ((config->fsmbm->FSMBMFRT & ___STOP) == ___NONE)) { + /* while packet finish without STOP, the error message is + * FSMBM_SMBUS_BUSY + */ + data->err_code = 0; + } else { + data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK; + } + data->state = STATE_COMPLETE; + config->fsmbm->FSMBMPF = FSMBM_COMPLETE_EVENT; + } else { + data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK; + data->state = STATE_COMPLETE; + } + } else if (data->state == STATE_COMPLETE) { + config->fsmbm->FSMBMPF = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT); + } +} + +static int i2c_kb1200_poll_write(const struct device *dev, struct i2c_msg msg, uint16_t addr) +{ + const struct i2c_kb1200_config *config = dev->config; + struct i2c_kb1200_data *data = dev->data; + uint8_t send_bytes; + + if (msg.flags & I2C_MSG_STOP) { + /* No CMD, No CNT, No PEC, with STOP*/ + config->fsmbm->FSMBMFRT = ___STOP; + } else { + /* No CMD, No CNT, No PEC, no STOP*/ + config->fsmbm->FSMBMFRT = ___NONE; + } + data->msg_len = msg.len; + data->msg_buf = msg.buf; + data->msg_flags = msg.flags; + data->state = STATE_IDLE; + data->index = 0; + data->err_code = 0; + + send_bytes = (msg.len > FSMBM_BUFFER_SIZE) ? FSMBM_BUFFER_SIZE : msg.len; + memcpy((void *)&config->fsmbm->FSMBMDAT[0], (void *)&data->msg_buf[data->index], + send_bytes); + data->index += send_bytes; + data->state = STATE_SENDING; + + config->fsmbm->FSMBMCMD = 0; + config->fsmbm->FSMBMADR = (addr & ~BIT(0)) | FSMBM_WRITE; + config->fsmbm->FSMBMPF = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT); + /* If data over bufferSize increase 1 to force continue transmit */ + if (msg.len >= (FSMBM_BUFFER_SIZE + 1)) { + config->fsmbm->FSMBMPRTC_C = FSMBM_BUFFER_SIZE + 1; + } else { + config->fsmbm->FSMBMPRTC_C = send_bytes; + } + config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT); + config->fsmbm->FSMBMPRTC_P = FLEXIBLE_PROTOCOL; + while (data->state != STATE_COMPLETE) + ; + data->state = STATE_IDLE; + if (data->err_code != 0) { + /* reset HW */ + config->fsmbm->FSMBMCFG |= FSMBM_HW_RESET; + return data->err_code; + } + return 0; +} + +static int i2c_kb1200_poll_read(const struct device *dev, struct i2c_msg msg, uint16_t addr) +{ + const struct i2c_kb1200_config *config = dev->config; + struct i2c_kb1200_data *data = dev->data; + + if (msg.flags & I2C_MSG_STOP) { + /* No CMD, No CNT, No PEC, with STOP*/ + config->fsmbm->FSMBMFRT = ___STOP; + } else { + /* No CMD, No CNT, No PEC, no STOP*/ + config->fsmbm->FSMBMFRT = ___NONE; + } + data->msg_len = msg.len; + data->msg_buf = msg.buf; + data->msg_flags = msg.flags; + data->state = STATE_IDLE; + data->index = 0; + data->err_code = 0; + data->state = STATE_RECEIVING; + + config->fsmbm->FSMBMCMD = 0; + config->fsmbm->FSMBMADR = (addr & ~BIT(0)) | FSMBM_READ; + config->fsmbm->FSMBMPF = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT); + /* If data over bufferSize increase 1 to force continue receive */ + if (msg.len >= (FSMBM_BUFFER_SIZE + 1)) { + config->fsmbm->FSMBMPRTC_C = FSMBM_BUFFER_SIZE + 1; + } else { + config->fsmbm->FSMBMPRTC_C = msg.len; + } + config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT); + config->fsmbm->FSMBMPRTC_P = FLEXIBLE_PROTOCOL; + while (data->state != STATE_COMPLETE) + ; + data->state = STATE_IDLE; + if (data->err_code != 0) { + /* reset HW */ + config->fsmbm->FSMBMCFG |= FSMBM_HW_RESET; + return data->err_code; + } + return 0; +} + +/* I2C Master api functions */ +static int i2c_kb1200_configure(const struct device *dev, uint32_t dev_config) +{ + const struct i2c_kb1200_config *config = dev->config; + + if (!(dev_config & I2C_MODE_CONTROLLER)) { + return -ENOTSUP; + } + + if (dev_config & I2C_ADDR_10_BITS) { + return -ENOTSUP; + } + + uint32_t speed = I2C_SPEED_GET(dev_config); + + switch (speed) { + case I2C_SPEED_STANDARD: + config->fsmbm->FSMBMCFG = (FSMBM_CLK_100K << FSMBM_CLK_POS); + break; + case I2C_SPEED_FAST: + config->fsmbm->FSMBMCFG = (FSMBM_CLK_400K << FSMBM_CLK_POS); + break; + case I2C_SPEED_FAST_PLUS: + config->fsmbm->FSMBMCFG = (FSMBM_CLK_1M << FSMBM_CLK_POS); + break; + default: + return -EINVAL; + } + + config->fsmbm->FSMBMPF = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT); + config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT); + /* HW reset, Enable FSMBM function, Timeout function*/ + config->fsmbm->FSMBMCFG |= FSMBM_HW_RESET | FSMBM_TIMEOUT_ENABLE | FSMBM_FUNCTION_ENABLE; + + return 0; +} + +static int i2c_kb1200_get_config(const struct device *dev, uint32_t *dev_config) +{ + const struct i2c_kb1200_config *config = dev->config; + + if ((config->fsmbm->FSMBMCFG & FSMBM_FUNCTION_ENABLE) == 0x00) { + printk("Cannot find i2c controller on 0x%p!\n", config->fsmbm); + return -EIO; + } + + switch ((config->fsmbm->FSMBMCFG >> FSMBM_CLK_POS) & FSMBM_CLK_MASK) { + case FSMBM_CLK_100K: + *dev_config = I2C_MODE_CONTROLLER | I2C_SPEED_SET(I2C_SPEED_STANDARD); + break; + case FSMBM_CLK_400K: + *dev_config = I2C_MODE_CONTROLLER | I2C_SPEED_SET(I2C_SPEED_FAST); + break; + case FSMBM_CLK_1M: + *dev_config = I2C_MODE_CONTROLLER | I2C_SPEED_SET(I2C_SPEED_FAST_PLUS); + break; + default: + return -ERANGE; + } + + return 0; +} + +static int i2c_kb1200_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs, + uint16_t addr) +{ + struct i2c_kb1200_data *data = dev->data; + int ret; + + /* get the mutex */ + k_sem_take(&data->mutex, K_FOREVER); + for (int i = 0U; i < num_msgs; i++) { + if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) { + ret = i2c_kb1200_poll_write(dev, msgs[i], addr); + if (ret) { + printk("%s Write error: 0x%X\n", dev->name, ret); + break; + } + } else { + ret = i2c_kb1200_poll_read(dev, msgs[i], addr); + if (ret) { + printk("%s Read error: 0x%X\n", dev->name, ret); + break; + } + } + } + /* release the mutex */ + k_sem_give(&data->mutex); + + return ret; +} + +/* I2C Master driver registration */ +static const struct i2c_driver_api i2c_kb1200_api = { + .configure = i2c_kb1200_configure, + .get_config = i2c_kb1200_get_config, + .transfer = i2c_kb1200_transfer, +}; + +#define KB1200_FSMBM_DEV(inst) DEVICE_DT_INST_GET(inst), +static const struct device *const fsmbm_devices[] = {DT_INST_FOREACH_STATUS_OKAY(KB1200_FSMBM_DEV)}; +static void i2c_kb1200_isr_wrap(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(fsmbm_devices); i++) { + const struct device *dev_ = fsmbm_devices[i]; + const struct i2c_kb1200_config *config = dev_->config; + + if (config->fsmbm->FSMBMIE & config->fsmbm->FSMBMPF) { + i2c_kb1200_isr(dev_); + } + } +} + +static bool init_irq = true; +static void kb1200_fsmbm_irq_init(void) +{ + if (init_irq) { + init_irq = false; + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), i2c_kb1200_isr_wrap, NULL, + 0); + irq_enable(DT_INST_IRQN(0)); + } +} + +static int i2c_kb1200_init(const struct device *dev) +{ + int ret; + const struct i2c_kb1200_config *config = dev->config; + struct i2c_kb1200_data *data = dev->data; + + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret != 0) { + return ret; + } + + /* init mutex */ + k_sem_init(&data->mutex, 1, 1); + kb1200_fsmbm_irq_init(); + + return 0; +} + +#define I2C_KB1200_DEVICE(inst) \ + PINCTRL_DT_INST_DEFINE(inst); \ + static struct i2c_kb1200_data i2c_kb1200_data_##inst; \ + static const struct i2c_kb1200_config i2c_kb1200_config_##inst = { \ + .fsmbm = (struct fsmbm_regs *)DT_INST_REG_ADDR(inst), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ + }; \ + DEVICE_DT_INST_DEFINE(inst, &i2c_kb1200_init, NULL, &i2c_kb1200_data_##inst, \ + &i2c_kb1200_config_##inst, PRE_KERNEL_1, \ + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &i2c_kb1200_api); + +DT_INST_FOREACH_STATUS_OKAY(I2C_KB1200_DEVICE) From 7613724851f952f81de4d9ebdff502f00e1ffe17 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:35 +0800 Subject: [PATCH 0726/2402] doc: CODEOWNERS Add owner to CODEOWNERS Signed-off-by: Steven Chang --- CODEOWNERS | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/CODEOWNERS b/CODEOWNERS index f34087d5484..045a393f7db 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -21,6 +21,7 @@ /soc/arm/aspeed/ @aspeeddylan /soc/atmel/ @nandojve /soc/arm/bcm*/ @sbranden +/soc/arm/ene/ @ene-steven /soc/arm/infineon_cat1/ @ifyall @npal-cy /soc/arm/infineon_xmc/ @parthitce /soc/arm/silabs_exx32/efm32pg1b/ @rdmeneze @@ -42,6 +43,7 @@ /soc/riscv/riscv-privileged/gd32vf103/ @soburi /soc/starfive/jh71xx/ @pfarwsi /soc/riscv/riscv-privileged/niosv/ @sweeaun +/boards/ene/ @ene-steven /boards/arm/96b_argonkey/ @avisconti /boards/arm/96b_avenger96/ @Mani-Sadhasivam /boards/arm/96b_carbon/ @idlethread @@ -164,6 +166,7 @@ /drivers/adc/adc_rpi_pico.c @soburi /drivers/adc/*ads114s0x* @benediktibk /drivers/adc/*max11102_17* @benediktibk +/drivers/adc/*kb1200* @ene-steven /drivers/adc/adc_ad5592.c @bbilas /drivers/audio/*nrfx* @anangl /drivers/auxdisplay/*pt6314* @xingrz @@ -239,6 +242,7 @@ /drivers/gpio/*ads114s0x* @benediktibk /drivers/gpio/*bd8lb600fs* @benediktibk /drivers/gpio/*pcal64xxa* @benediktibk +/drivers/gpio/*kb1200* @ene-steven /drivers/gpio/gpio_altera_pio.c @shilinte /drivers/gpio/gpio_ad5592.c @bbilas /drivers/i2c/i2c_common.c @sjg20 @@ -252,6 +256,7 @@ /drivers/i2c/Kconfig.test @mbolivar-ampere /drivers/i2c/i2c_test.c @mbolivar-ampere /drivers/i2c/*rcar* @aaillet +/drivers/i2c/*kb1200* @ene-steven /drivers/i2s/*litex* @mateusz-holenko @kgugala @pgielda /drivers/i2s/i2s_ll_stm32* @avisconti /drivers/i2s/*nrfx* @anangl @@ -289,6 +294,7 @@ /drivers/modem/Kconfig.simcom-sim7080 @lgehreke /drivers/pinctrl/*esp32* @sylvioalves /drivers/pinctrl/*it8xxx2* @ite +/drivers/pinctrl/*kb1200* @ene-steven /drivers/pm_cpu_ops/psci_shell.c @nbalabak @gdengi /drivers/power_domain/ @ceolin /drivers/ps2/*xec* @franciscomunoz @sjvasanth1 @@ -307,6 +313,7 @@ /drivers/pwm/*esp32* @LucasTambor /drivers/pwm/*rcar* @aaillet /drivers/pwm/*max31790* @benediktibk +/drivers/pwm/*kb1200* @ene-steven /drivers/regulator/* @gmarull /drivers/regulator/regulator_max20335.c @bbilas /drivers/regulator/regulator_pca9420.c @danieldegrasse @@ -326,6 +333,7 @@ /drivers/sensor/qdec_stm32/ @valeriosetti /drivers/sensor/rpi_pico_temp/ @soburi /drivers/sensor/st*/ @avisconti +/drivers/sensor/ene_tack_kb1200/ @ene-steven /drivers/serial/*b91* @andy-liu-telink /drivers/serial/uart_altera_jtag.c @nashif @gohshunjing /drivers/serial/uart_altera.c @gohshunjing @@ -350,6 +358,7 @@ /drivers/serial/Kconfig.it8xxx2 @GTLin08 /drivers/serial/uart_ite_it8xxx2.c @GTLin08 /drivers/serial/*intel_lw* @shilinte +/drivers/serial/*kb1200* @ene-steven /drivers/disk/sdmmc_sdhc.h @JunYangNXP /drivers/disk/sdmmc_stm32.c @anthonybrandon /drivers/ptp_clock/ @tbursztyka @jukkar @@ -396,6 +405,7 @@ /drivers/watchdog/*rpi_pico* @thedjnK /drivers/watchdog/*dw* @softwarecki @pbalsundar /drivers/watchdog/*ifx* @sreeramIfx +/drivers/watchdog/*kb1200* @ene-steven /drivers/wifi/esp_at/ @mniestroj /drivers/wifi/eswifi/ @loicpoulain @nandojve /drivers/wifi/winc1500/ @kludentwo @@ -406,6 +416,7 @@ /dts/arm/atmel/ @galak @nandojve /dts/arm/broadcom/ @sbranden /dts/arm/cypress/ @ifyall @npal-cy +/dts/arm/ene/kb1200 @ene-steven /dts/arm/gd/ @nandojve /dts/arm/infineon/xmc4* @parthitce @ifyall @npal-cy /dts/arm/infineon/psoc6/ @ifyall @npal-cy From 3a5bbb12ed6a6727196f4ee4bbb95cd5679c8959 Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Fri, 15 Mar 2024 10:46:35 +0800 Subject: [PATCH 0727/2402] board: ENE kb1200_evb board Add support for ENE kb1200_evb board Signed-off-by: Steven Chang --- boards/ene/index.rst | 10 ++ boards/ene/kb1200_evb/Kconfig.kb1200_evb | 5 + boards/ene/kb1200_evb/board.cmake | 6 + boards/ene/kb1200_evb/board.yml | 5 + boards/ene/kb1200_evb/doc/index.rst | 86 +++++++++++ boards/ene/kb1200_evb/kb1200_evb.dts | 157 +++++++++++++++++++++ boards/ene/kb1200_evb/kb1200_evb.yaml | 13 ++ boards/ene/kb1200_evb/kb1200_evb_defconfig | 11 ++ boards/ene/kb1200_evb/support/openocd.cfg | 52 +++++++ 9 files changed, 345 insertions(+) create mode 100644 boards/ene/index.rst create mode 100644 boards/ene/kb1200_evb/Kconfig.kb1200_evb create mode 100644 boards/ene/kb1200_evb/board.cmake create mode 100644 boards/ene/kb1200_evb/board.yml create mode 100644 boards/ene/kb1200_evb/doc/index.rst create mode 100644 boards/ene/kb1200_evb/kb1200_evb.dts create mode 100644 boards/ene/kb1200_evb/kb1200_evb.yaml create mode 100644 boards/ene/kb1200_evb/kb1200_evb_defconfig create mode 100644 boards/ene/kb1200_evb/support/openocd.cfg diff --git a/boards/ene/index.rst b/boards/ene/index.rst new file mode 100644 index 00000000000..aea3d8ee661 --- /dev/null +++ b/boards/ene/index.rst @@ -0,0 +1,10 @@ +.. _boards-ene: + +ENE +### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/ene/kb1200_evb/Kconfig.kb1200_evb b/boards/ene/kb1200_evb/Kconfig.kb1200_evb new file mode 100644 index 00000000000..6cf67b86769 --- /dev/null +++ b/boards/ene/kb1200_evb/Kconfig.kb1200_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2023 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KB1200_EVB + select SOC_KB1200 diff --git a/boards/ene/kb1200_evb/board.cmake b/boards/ene/kb1200_evb/board.cmake new file mode 100644 index 00000000000..cab2daca270 --- /dev/null +++ b/boards/ene/kb1200_evb/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=KB1200" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ene/kb1200_evb/board.yml b/boards/ene/kb1200_evb/board.yml new file mode 100644 index 00000000000..d8dd4b412c7 --- /dev/null +++ b/boards/ene/kb1200_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: kb1200_evb + vendor: ene + socs: + - name: kb1200 diff --git a/boards/ene/kb1200_evb/doc/index.rst b/boards/ene/kb1200_evb/doc/index.rst new file mode 100644 index 00000000000..6558b8dad54 --- /dev/null +++ b/boards/ene/kb1200_evb/doc/index.rst @@ -0,0 +1,86 @@ +.. _ene_kb1200_evb: + +ENE KB1200_EVB +############## + +Overview +******** + +The KB1200_EVB kit is a development platform to evaluate the +ENE KB1200 series microcontrollers. This board needs to be mated with +part number KB1200. + + +Hardware +******** + +- ARM Cortex-M4F Processor +- 512KB Flash and 320KB RAM +- ADC & GPIO headers +- SER1, SER2 and SER3 +- FAN PWM interface +- ENE Debug interface + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port/controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PMU | on-chip | power management | ++-----------+------------+-------------------------------------+ +| PSL | on-chip | power switch logic | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pulse width modulator | ++-----------+------------+-------------------------------------+ +| TACH | on-chip | tachometer sensor | ++-----------+------------+-------------------------------------+ +| SER | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +System Clock +============ + +The KB1200 MCU is configured to use the 96Mhz internal oscillator with the +on-chip DPLL to generate a resulting EC clock rate of 96MHz/48MHz/24MHz/12MHz. +See Processor clock control register (refer 5.1 General Configuration) + +Programming and Debugging +************************* + +Flashing +======== + +If the correct headers are installed, this board supports SWD Debug Interface. + +To flash with SWD, install the drivers for your programmer, for example: +SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ + +Debugging +========= + +Use SWD with a J-Link + +References +========== + +.. target-notes:: diff --git a/boards/ene/kb1200_evb/kb1200_evb.dts b/boards/ene/kb1200_evb/kb1200_evb.dts new file mode 100644 index 00000000000..b6baf1a55d1 --- /dev/null +++ b/boards/ene/kb1200_evb/kb1200_evb.dts @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "KB1200 board"; + compatible = "ene,kb1200"; + + aliases { + uart0 = &uart0; + led0 = &led0; + led1 = &led1; + sw0 = &user_button; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User"; + gpios = <&gpio0x1x 0x10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + /* green led */ + led0: led_0 { + gpios = <&gpio0x1x 0x0f GPIO_ACTIVE_HIGH>; + label = "LED0"; + }; + /* blue led */ + led1: led_1 { + gpios = <&gpio0x1x 0x11 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_tx_gpio03 &uart0_rx_gpio01>; + pinctrl-names = "default"; + status = "okay"; + current-speed = <115200>; +}; + +&uart1 { + pinctrl-0 = <&uart1_tx_gpio36 &uart1_rx_gpio28>; + pinctrl-names = "default"; + status = "okay"; + current-speed = <115200>; +}; + +&uart2 { + pinctrl-0 = <&uart2_tx_gpio04 &uart2_rx_gpio55>; + pinctrl-names = "default"; + status = "okay"; + current-speed = <115200>; +}; + +&gpio0x1x { + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_gpio0a &adc1_gpio0b &adc2_gpio0c &adc3_gpio0d>; + pinctrl-names = "default"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_gpio3a>; + pinctrl-names = "default"; +}; + +&pwm4 { + status = "okay"; + pinctrl-0 = <&pwm4_gpio31>; + pinctrl-names = "default"; +}; + +&pwm5 { + status = "okay"; + pinctrl-0 = <&pwm5_gpio30>; + pinctrl-names = "default"; +}; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6_gpio37>; + pinctrl-names = "default"; +}; + +&tach0 { + status = "okay"; + pinctrl-0 = <&tach0_gpio48>; + pinctrl-names = "default"; + pulses-per-round = <2>; + sample-time-us = <2>; +}; + +&tach1 { + status = "okay"; + pinctrl-0 = <&tach1_gpio4e>; + pinctrl-names = "default"; + pulses-per-round = <1>; + sample-time-us = <8>; +}; + +&tach2 { + status = "okay"; + pinctrl-0 = <&tach2_gpio0e>; + pinctrl-names = "default"; + pulses-per-round = <2>; + sample-time-us = <16>; +}; + +&tach3 { + status = "okay"; + pinctrl-0 = <&tach3_gpio43>; + pinctrl-names = "default"; + pulses-per-round = <1>; + sample-time-us = <64>; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_clk_gpio2c &i2c0_dat_gpio2d>; + pinctrl-names = "default"; +}; + +&i2c8 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c8_clk_gpio70 &i2c8_dat_gpio71>; + pinctrl-names = "default"; +}; diff --git a/boards/ene/kb1200_evb/kb1200_evb.yaml b/boards/ene/kb1200_evb/kb1200_evb.yaml new file mode 100644 index 00000000000..efa85b9c830 --- /dev/null +++ b/boards/ene/kb1200_evb/kb1200_evb.yaml @@ -0,0 +1,13 @@ +identifier: kb1200_evb +name: KB1200 EVB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - uart +ram: 64 +flash: 256 diff --git a/boards/ene/kb1200_evb/kb1200_evb_defconfig b/boards/ene/kb1200_evb/kb1200_evb_defconfig new file mode 100644 index 00000000000..5dfbb78fbf7 --- /dev/null +++ b/boards/ene/kb1200_evb/kb1200_evb_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2023 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable console & UART driver +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/ene/kb1200_evb/support/openocd.cfg b/boards/ene/kb1200_evb/support/openocd.cfg new file mode 100644 index 00000000000..56444e04413 --- /dev/null +++ b/boards/ene/kb1200_evb/support/openocd.cfg @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find interface/jlink.cfg] + +transport select swd + +source [find target/swj-dp.tcl] + + +# Set Chipname +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME kb1200 +} + +# SWD DAP ID of ENE KB1200 Cortex-M4. +if { [info exists CPUDAPID ] } { + set _CPUDAPID $CPUDAPID +} else { + set _CPUDAPID 0x2ba01477 +} + +# Work-area is a space in RAM used for flash programming +# By default use 32kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +# Debug Adapter Target Settings +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# Initial JTAG/SWD speed +# For safety purposes, set for the lowest cpu clock configuration +# 4MHz / 6 = 666KHz, so use 600KHz for it +adapter speed 600 + +# For safety purposes, set for the lowest cpu clock configuration +$_TARGETNAME configure -event reset-start {adapter speed 600} + +# use sysresetreq to perform a system reset +cortex_m reset_config sysresetreq + +# ENE internal spi flash +flash bank ispif eneispif 0x60000000 0 0 0 $_TARGETNAME 0x50101000 From d435acf28d55f442c35d5dbf76d93b529187656d Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Tue, 13 Jun 2023 08:28:41 +0530 Subject: [PATCH 0728/2402] Bluetooth: Controller: Fix CIS accept fails with unsupp parameters Fix CIS accepted by Host being failed in the Controller with reason 0x20 Unsupported LL Parameter Value, by relaxing the check that the ACL connection is sufficiently placed such that the time reservation using in the Controller implementation does not overlap with the CIG event. Signed-off-by: Vinayak Kariappa Chettimada --- subsys/bluetooth/controller/Kconfig.ll_sw_split | 10 ++++++++++ subsys/bluetooth/controller/ll_sw/ull_peripheral_iso.c | 3 ++- tests/bluetooth/init/prj_ctlr_5_x_dbg.conf | 1 + tests/bluetooth/init/prj_ctlr_dbg.conf | 2 ++ 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/subsys/bluetooth/controller/Kconfig.ll_sw_split b/subsys/bluetooth/controller/Kconfig.ll_sw_split index 97f7161bf07..ba43622604a 100644 --- a/subsys/bluetooth/controller/Kconfig.ll_sw_split +++ b/subsys/bluetooth/controller/Kconfig.ll_sw_split @@ -536,6 +536,16 @@ config BT_CTLR_SCAN_ENABLE_STRICT Enforce returning HCI Error Command Disallowed on enabling/disabling already enabled/disabled scanning. +config BT_CTLR_CIS_ACCEPT_MIN_OFFSET_STRICT + bool "Enforce Strict CIS Minimum Offset Check" + depends on BT_CTLR_PERIPHERAL_ISO + help + Enforce strict check of CIS minimum offset accepted by the peripheral + considering that there will be no overlap of ACL connection with the + CIG events. Radio and CPU overheads for an ACL connection event is + considered and checks the CIS minimum offset is greater than the time + reservation for the ACL connection. + config BT_CTLR_ISOAL_SN_STRICT bool "Enforce Strict Tx ISO Data Sequence Number use" depends on !BT_CTLR_ISOAL_PSN_IGNORE && (BT_CTLR_ADV_ISO || \ diff --git a/subsys/bluetooth/controller/ll_sw/ull_peripheral_iso.c b/subsys/bluetooth/controller/ll_sw/ull_peripheral_iso.c index 843bf877935..b7718a3091f 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_peripheral_iso.c +++ b/subsys/bluetooth/controller/ll_sw/ull_peripheral_iso.c @@ -104,7 +104,8 @@ uint8_t ll_cis_accept(uint16_t handle) if (conn) { uint32_t cis_offset_min; - if (IS_ENABLED(CONFIG_BT_CTLR_PERIPHERAL_ISO_EARLY_CIG_START)) { + if (IS_ENABLED(CONFIG_BT_CTLR_PERIPHERAL_ISO_EARLY_CIG_START) || + !IS_ENABLED(CONFIG_BT_CTLR_CIS_ACCEPT_MIN_OFFSET_STRICT)) { /* Early start allows offset down to spec defined minimum */ cis_offset_min = CIS_MIN_OFFSET_MIN; } else { diff --git a/tests/bluetooth/init/prj_ctlr_5_x_dbg.conf b/tests/bluetooth/init/prj_ctlr_5_x_dbg.conf index f4dcbdc8fdd..f37e9c6f309 100644 --- a/tests/bluetooth/init/prj_ctlr_5_x_dbg.conf +++ b/tests/bluetooth/init/prj_ctlr_5_x_dbg.conf @@ -39,6 +39,7 @@ CONFIG_BT_CTLR_ADV_RESERVE_MAX=n CONFIG_BT_CTLR_ADV_ISO_RESERVE_MAX=n CONFIG_BT_CTLR_SYNC_ISO_RESERVE_MAX=n CONFIG_BT_CTLR_CENTRAL_RESERVE_MAX=n +CONFIG_BT_CTLR_CIS_ACCEPT_MIN_OFFSET_STRICT=y CONFIG_BT_CTLR_EVENT_OVERHEAD_RESERVE_MAX=n CONFIG_BT_CTLR_PROFILE_ISR=y CONFIG_BT_CTLR_DEBUG_PINS=y diff --git a/tests/bluetooth/init/prj_ctlr_dbg.conf b/tests/bluetooth/init/prj_ctlr_dbg.conf index d2c887fefa0..f2bf1f7ffd4 100644 --- a/tests/bluetooth/init/prj_ctlr_dbg.conf +++ b/tests/bluetooth/init/prj_ctlr_dbg.conf @@ -21,6 +21,8 @@ CONFIG_BT_CTLR_LLL_PRIO=0 CONFIG_BT_CTLR_ULL_HIGH_PRIO=1 CONFIG_BT_CTLR_XTAL_ADVANCED=n CONFIG_BT_CTLR_SCHED_ADVANCED=n +CONFIG_BT_CTLR_CIS_ACCEPT_MIN_OFFSET_STRICT=n +CONFIG_BT_CTLR_EVENT_OVERHEAD_RESERVE_MAX=y CONFIG_BT_CTLR_RADIO_ENABLE_FAST=y CONFIG_BT_CTLR_TIFS_HW=n CONFIG_BT_CTLR_TX_RETRY_DISABLE=y From ca147ff6376f57378fe2b28f72495849e5c2d8a2 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Thu, 22 Feb 2024 12:58:38 +0100 Subject: [PATCH 0729/2402] modules: hal_nordic: nrfx: include config for nrf54l15 Both nRF54L15 and nRF54L15 EngA uses same nrfx config file. Signed-off-by: Nikodem Kastelik --- modules/hal_nordic/nrfx/nrfx_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index 46d4ac9538f..56c69447c92 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -949,7 +949,7 @@ #include #elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) #include -#elif defined(NRF54L15_ENGA_XXAA) && defined(NRF_APPLICATION) +#elif (defined(NRF54L15_XXAA) || defined(NRF54L15_ENGA_XXAA)) && defined(NRF_APPLICATION) #include #else #error "Unknown device." From 2f40474c146ada6bd625cc291bd67f0d2036658c Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Thu, 14 Mar 2024 16:51:51 +0200 Subject: [PATCH 0730/2402] nxp: imx8ulp: correct value of `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` The core clock of 8ULP's HIFI4 DSP runs at 475.2MHz. As such, correct the value of `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` to reflect this. Signed-off-by: Laurentiu Mihalcea --- soc/nxp/imx/imx8ulp/Kconfig.defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/nxp/imx/imx8ulp/Kconfig.defconfig b/soc/nxp/imx/imx8ulp/Kconfig.defconfig index 424892563af..f29f1c7d56e 100644 --- a/soc/nxp/imx/imx8ulp/Kconfig.defconfig +++ b/soc/nxp/imx/imx8ulp/Kconfig.defconfig @@ -6,7 +6,7 @@ if SOC_SERIES_IMX8ULP if SOC_MIMX8ULP_ADSP config SYS_CLOCK_HW_CYCLES_PER_SEC - default 528000000 + default 475200000 config SYS_CLOCK_TICKS_PER_SEC default 50000 From 15f1e62cb9b0b3968b5cf2dcace534e3fe44c391 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 14 Mar 2024 17:03:51 +0100 Subject: [PATCH 0731/2402] MAINTAINERS: Add myself to hawkbit as a collaborator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add myself to hawkbit as a collaborator Signed-off-by: Fin Maaß --- MAINTAINERS.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index b61853be4ee..5f9dfda220b 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2475,6 +2475,7 @@ hawkBit: status: odd fixes collaborators: - ycsin + - maass-hamburg files: - subsys/mgmt/hawkbit/ - include/zephyr/mgmt/hawkbit.h From bc559240048df61c1c849b63e4e56dfa096429ab Mon Sep 17 00:00:00 2001 From: Glenn Andrews Date: Thu, 14 Mar 2024 22:12:33 -0700 Subject: [PATCH 0732/2402] twister: qemu: Fix device tests skipped when QEMU not installed https://github.com/zephyrproject-rtos/zephyr/pull/67595 introduces a bug where if QEMU_BIN_PATH is not set on a Windows PC, on-device tests are skipped. This fixes that issue. Signed-off-by: Glenn Andrews --- scripts/pylib/twister/twisterlib/testinstance.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/pylib/twister/twisterlib/testinstance.py b/scripts/pylib/twister/twisterlib/testinstance.py index 850da363278..5f00cbe901a 100644 --- a/scripts/pylib/twister/twisterlib/testinstance.py +++ b/scripts/pylib/twister/twisterlib/testinstance.py @@ -215,7 +215,7 @@ def check_runnable(self, enable_slow=False, filter='buildable', fixtures=[], har return False # check presence of QEMU on Windows - if 'QEMU_BIN_PATH' not in os.environ: + if self.platform.simulation == 'qemu' and 'QEMU_BIN_PATH' not in os.environ: return False # we asked for build-only on the command line From b0f9f16f1403c7b6a742351c39b5ffc5d05abe37 Mon Sep 17 00:00:00 2001 From: Matthias Alleman Date: Thu, 14 Mar 2024 15:55:46 +0100 Subject: [PATCH 0733/2402] lib: posix: shell: Fix compiler warning of lib__posix__shell This PR fixes the following compiler warning: No SOURCES given to Zephyr library: lib__posix__shell Signed-off-by: Matthias Alleman --- lib/posix/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/posix/CMakeLists.txt b/lib/posix/CMakeLists.txt index fed728c17ba..d62108b66f0 100644 --- a/lib/posix/CMakeLists.txt +++ b/lib/posix/CMakeLists.txt @@ -1,4 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 add_subdirectory(options) -add_subdirectory(shell) +add_subdirectory_ifdef(CONFIG_POSIX_SHELL shell) From 02b2be0f13792015ee7430e0847f7b671d73585b Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Wed, 13 Mar 2024 12:07:25 +0100 Subject: [PATCH 0734/2402] manifest: hal_silabs: update module Brings the following fix: gecko/cmake: replace 'SOC_GECKO_SERIESx' with 'SOC_FAMILY_SILABS_Sx' Fixes: #69902 Signed-off-by: Piotr Dymacz --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 99ccbd49d4f..278266018cc 100644 --- a/west.yml +++ b/west.yml @@ -219,7 +219,7 @@ manifest: groups: - hal - name: hal_silabs - revision: 59c6c6e2e8862f0ff5c6087ef055793bed125778 + revision: 442d0fb1d02cc4b2bb159fbff378029998b89049 path: modules/hal/silabs groups: - hal From 2a8b298ee876039afe973c6ddfadce18ed1a85ff Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Tue, 20 Feb 2024 17:55:32 +0800 Subject: [PATCH 0735/2402] subsys/mgmt/hawkbit: optimize log message A lot of the log messages are using highest level, optimize them to recycle as much messages as possible. When building the sample with `CONFIG_HAWKBIT_LOG_LEVEL_DBG` on `frdm_k64f`, the FLASH size is reduced from 150860 B to 150048 B, saving ~800 bytes. Signed-off-by: Yong Cong Sin --- subsys/mgmt/hawkbit/hawkbit.c | 141 +++++++++++++++++----------------- 1 file changed, 71 insertions(+), 70 deletions(-) diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c index eba80d2d70e..0d12474f380 100644 --- a/subsys/mgmt/hawkbit/hawkbit.c +++ b/subsys/mgmt/hawkbit/hawkbit.c @@ -233,7 +233,7 @@ static bool start_http_client(void) } if (ret != 0) { - LOG_ERR("Could not resolve dns: %d", ret); + LOG_ERR("Failed to resolve dns: %d", ret); return false; } @@ -278,7 +278,7 @@ static bool start_http_client(void) static void cleanup_connection(void) { if (zsock_close(hb_context.sock) < 0) { - LOG_ERR("Could not close the socket"); + LOG_ERR("Failed to close the socket"); } } @@ -389,14 +389,14 @@ static int hawkbit_find_cancelAction_base(struct hawkbit_ctl_res *res, char *can helper = strstr(href, "cancelAction/"); if (!helper) { /* A badly formatted cancel base is a server error */ - LOG_ERR("Missing cancelBase/ in href %s", href); + LOG_ERR("Missing %s/ in href %s", "cancelAction", href); return -EINVAL; } len = strlen(helper); if (len > CANCEL_BASE_SIZE - 1) { /* Lack of memory is an application error */ - LOG_ERR("cancelBase %s is too big (len %zu, max %zu)", helper, len, + LOG_ERR("%s %s is too big (len %zu, max %zu)", "cancelAction", helper, len, CANCEL_BASE_SIZE - 1); return -ENOMEM; } @@ -415,7 +415,7 @@ static int hawkbit_find_cancelAction_base(struct hawkbit_ctl_res *res, char *can hb_context.action_id = strtol(helper, &endptr, 10); if (hb_context.action_id <= 0) { - LOG_ERR("Invalid action ID: %d", hb_context.action_id); + LOG_ERR("Invalid action_id: %d", hb_context.action_id); return -EINVAL; } @@ -443,14 +443,14 @@ static int hawkbit_find_deployment_base(struct hawkbit_ctl_res *res, char *deplo helper = strstr(href, "deploymentBase/"); if (!helper) { /* A badly formatted deployment base is a server error */ - LOG_ERR("Missing deploymentBase/ in href %s", href); + LOG_ERR("Missing %s/ in href %s", "deploymentBase", href); return -EINVAL; } len = strlen(helper); if (len > DEPLOYMENT_BASE_SIZE - 1) { /* Lack of memory is an application error */ - LOG_ERR("deploymentBase %s is too big (len %zu, max %zu)", helper, len, + LOG_ERR("%s %s is too big (len %zu, max %zu)", "deploymentBase", helper, len, DEPLOYMENT_BASE_SIZE - 1); return -ENOMEM; } @@ -476,7 +476,7 @@ static int hawkbit_parse_deployment(struct hawkbit_dep_res *res, int32_t *json_a hb_context.action_id = strtol(res->id, &endptr, 10); if (hb_context.action_id < 0) { - LOG_ERR("Negative action ID: %d", hb_context.action_id); + LOG_ERR("Invalid action_id: %d", hb_context.action_id); return -EINVAL; } @@ -484,7 +484,7 @@ static int hawkbit_parse_deployment(struct hawkbit_dep_res *res, int32_t *json_a num_chunks = res->deployment.num_chunks; if (num_chunks != 1) { - LOG_ERR("Expecting one chunk (got %d)", num_chunks); + LOG_ERR("Expecting 1 chunk (got %d)", num_chunks); return -ENOSPC; } @@ -496,7 +496,7 @@ static int hawkbit_parse_deployment(struct hawkbit_dep_res *res, int32_t *json_a num_artifacts = chunk->num_artifacts; if (num_artifacts != 1) { - LOG_ERR("Expecting one artifact (got %d)", num_artifacts); + LOG_ERR("Expecting 1 artifact (got %d)", num_artifacts); return -EINVAL; } @@ -519,22 +519,22 @@ static int hawkbit_parse_deployment(struct hawkbit_dep_res *res, int32_t *json_a */ href = artifact->_links.download_http.href; if (!href) { - LOG_ERR("Missing expected download-http href"); + LOG_ERR("Missing expected %s href", "download-http"); return -EINVAL; } helper = strstr(href, "/DEFAULT/controller/v1"); if (!helper) { - LOG_ERR("Unexpected download-http href format: %s", helper); + LOG_ERR("Unexpected %s href format: %s", "download-http", helper); return -EINVAL; } len = strlen(helper); if (len == 0) { - LOG_ERR("Empty download-http"); + LOG_ERR("Empty %s", "download-http"); return -EINVAL; } else if (len > DOWNLOAD_HTTP_SIZE - 1) { - LOG_ERR("download-http %s is too big (len: %zu, max: %zu)", helper, len, + LOG_ERR("%s %s is too big (len %zu, max %zu)", "download-http", helper, len, DOWNLOAD_HTTP_SIZE - 1); return -ENOMEM; } @@ -551,19 +551,19 @@ static void hawkbit_dump_deployment(struct hawkbit_dep_res *d) struct hawkbit_dep_res_arts *a = &c->artifacts[0]; struct hawkbit_dep_res_links *l = &a->_links; - LOG_DBG("id=%s", d->id); - LOG_DBG("download=%s", d->deployment.download); - LOG_DBG("update=%s", d->deployment.update); - LOG_DBG("chunks[0].part=%s", c->part); - LOG_DBG("chunks[0].name=%s", c->name); - LOG_DBG("chunks[0].version=%s", c->version); - LOG_DBG("chunks[0].artifacts[0].filename=%s", a->filename); - LOG_DBG("chunks[0].artifacts[0].hashes.sha1=%s", a->hashes.sha1); - LOG_DBG("chunks[0].artifacts[0].hashes.md5=%s", a->hashes.md5); - LOG_DBG("chunks[0].artifacts[0].hashes.sha256=%s", a->hashes.sha256); + LOG_DBG("%s=%s", "id", d->id); + LOG_DBG("%s=%s", "download", d->deployment.download); + LOG_DBG("%s=%s", "update", d->deployment.update); + LOG_DBG("chunks[0].%s=%s", "part", c->part); + LOG_DBG("chunks[0].%s=%s", "name", c->name); + LOG_DBG("chunks[0].%s=%s", "version", c->version); + LOG_DBG("chunks[0].artifacts[0].%s=%s", "filename", a->filename); + LOG_DBG("chunks[0].artifacts[0].%s=%s", "hashes.sha1", a->hashes.sha1); + LOG_DBG("chunks[0].artifacts[0].%s=%s", "hashes.md5", a->hashes.md5); + LOG_DBG("chunks[0].artifacts[0].%s=%s", "hashes.sha256", a->hashes.sha256); LOG_DBG("chunks[0].size=%d", a->size); - LOG_DBG("download-http=%s", l->download_http.href); - LOG_DBG("md5sum =%s", l->md5sum_http.href); + LOG_DBG("%s=%s", "download-http", l->download_http.href); + LOG_DBG("%s=%s", "md5sum-http", l->md5sum_http.href); } int hawkbit_init(void) @@ -582,7 +582,7 @@ int hawkbit_init(void) fs.offset = STORAGE_OFFSET; rc = flash_get_page_info_by_offs(fs.flash_device, fs.offset, &info); if (rc) { - LOG_ERR("Unable to get storage page info: %d", rc); + LOG_ERR("Failed to get storage page info: %d", rc); return -EIO; } @@ -591,23 +591,23 @@ int hawkbit_init(void) rc = nvs_mount(&fs); if (rc) { - LOG_ERR("Storage flash mount failed: %d", rc); + LOG_ERR("Failed to mount storage flash: %d", rc); return rc; } rc = nvs_read(&fs, ADDRESS_ID, &action_id, sizeof(action_id)); - LOG_DBG("Action id: current %d", action_id); + LOG_DBG("Current action_id: %d", action_id); image_ok = boot_is_img_confirmed(); - LOG_INF("Image is%s confirmed OK", image_ok ? "" : " not"); + LOG_INF("Current image is%s confirmed", image_ok ? "" : " not"); if (!image_ok) { ret = boot_write_img_confirmed(); if (ret < 0) { - LOG_ERR("Couldn't confirm this image: %d", ret); + LOG_ERR("Failed to confirm current image: %d", ret); return ret; } - LOG_DBG("Marked image as OK"); + LOG_DBG("Marked current image as OK"); ret = boot_erase_img_bank(FIXED_PARTITION_ID(SLOT1_LABEL)); if (ret) { LOG_ERR("Failed to erase second slot: %d", ret); @@ -691,7 +691,7 @@ static void response_cb(struct http_response *rsp, enum http_final_call final_da hb_context.dl.downloaded_size, json_ctl_res_descr, ARRAY_SIZE(json_ctl_res_descr), &hawkbit_results.base); if (ret < 0) { - LOG_ERR("JSON parse error (HAWKBIT_PROBE): %d", ret); + LOG_ERR("JSON parse error (%s): %d", "HAWKBIT_PROBE", ret); hb_context.code_status = HAWKBIT_METADATA_ERROR; } } @@ -734,7 +734,9 @@ static void response_cb(struct http_response *rsp, enum http_final_call final_da if (final_data == HTTP_DATA_FINAL) { if (hb_context.dl.http_content_size != hb_context.dl.downloaded_size) { - LOG_ERR("HTTP response len mismatch"); + LOG_ERR("HTTP response len mismatch, expected %d, got %d", + hb_context.dl.http_content_size, + hb_context.dl.downloaded_size); hb_context.code_status = HAWKBIT_METADATA_ERROR; break; } @@ -744,7 +746,7 @@ static void response_cb(struct http_response *rsp, enum http_final_call final_da hb_context.dl.downloaded_size, json_dep_res_descr, ARRAY_SIZE(json_dep_res_descr), &hawkbit_results.dep); if (ret < 0) { - LOG_ERR("DeploymentBase JSON parse error: %d", ret); + LOG_ERR("JSON parse error (%s): %d", "deploymentBase", ret); hb_context.code_status = HAWKBIT_METADATA_ERROR; } } @@ -763,7 +765,7 @@ static void response_cb(struct http_response *rsp, enum http_final_call final_da ret = flash_img_buffered_write(&hb_context.flash_ctx, body_data, body_len, final_data == HTTP_DATA_FINAL); if (ret < 0) { - LOG_ERR("Flash write error: %d", ret); + LOG_ERR("Failed to write flash: %d", ret); hb_context.code_status = HAWKBIT_DOWNLOAD_ERROR; break; } @@ -775,7 +777,7 @@ static void response_cb(struct http_response *rsp, enum http_final_call final_da if (downloaded > hb_context.dl.download_progress) { hb_context.dl.download_progress = downloaded; - LOG_DBG("Download percentage: %d%% ", hb_context.dl.download_progress); + LOG_DBG("Downloaded: %d%% ", hb_context.dl.download_progress); } if (final_data == HTTP_DATA_FINAL) { @@ -833,7 +835,7 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type ret = http_client_req(hb_context.sock, &hb_context.http_req, HAWKBIT_RECV_TIMEOUT, "HAWKBIT_PROBE"); if (ret < 0) { - LOG_ERR("Unable to send HTTP request (HAWKBIT_PROBE): %d", ret); + LOG_ERR("Unable to send HTTP request (%s): %d", "HAWKBIT_PROBE", ret); return false; } @@ -853,7 +855,8 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type hb_context.status_buffer, hb_context.status_buffer_size - 1); if (ret) { - LOG_ERR("Can't encode the JSON script (HAWKBIT_CONFIG_DEVICE): %d", ret); + LOG_ERR("Can't encode the JSON script (%s): %d", "HAWKBIT_CONFIG_DEVICE", + ret); return false; } @@ -864,7 +867,8 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type ret = http_client_req(hb_context.sock, &hb_context.http_req, HAWKBIT_RECV_TIMEOUT, "HAWKBIT_CONFIG_DEVICE"); if (ret < 0) { - LOG_ERR("Unable to send HTTP request (HAWKBIT_CONFIG_DEVICE): %d", ret); + LOG_ERR("Unable to send HTTP request (%s): %d", "HAWKBIT_CONFIG_DEVICE", + ret); return false; } @@ -883,7 +887,7 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type hb_context.status_buffer, hb_context.status_buffer_size - 1); if (ret) { - LOG_ERR("Can't encode the JSON script (HAWKBIT_CLOSE): %d", ret); + LOG_ERR("Can't encode the JSON script (%s): %d", "HAWKBIT_CLOSE", ret); return false; } @@ -894,7 +898,7 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type ret = http_client_req(hb_context.sock, &hb_context.http_req, HAWKBIT_RECV_TIMEOUT, "HAWKBIT_CLOSE"); if (ret < 0) { - LOG_ERR("Unable to send HTTP request (HAWKBIT_CLOSE): %d", ret); + LOG_ERR("Unable to send HTTP request (%s): %d", "HAWKBIT_CLOSE", ret); return false; } @@ -905,8 +909,8 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type ret = http_client_req(hb_context.sock, &hb_context.http_req, HAWKBIT_RECV_TIMEOUT, "HAWKBIT_PROBE_DEPLOYMENT_BASE"); if (ret < 0) { - LOG_ERR("Unable to send HTTP request (HAWKBIT_PROBE_DEPLOYMENT_BASE): %d", - ret); + LOG_ERR("Unable to send HTTP request (%s): %d", + "HAWKBIT_PROBE_DEPLOYMENT_BASE", ret); return false; } @@ -930,7 +934,7 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type &feedback, hb_context.status_buffer, hb_context.status_buffer_size - 1); if (ret) { - LOG_ERR("Can't encode the JSON script (HAWKBIT_REPORT): %d", ret); + LOG_ERR("Can't encode the JSON script (%s): %d", "HAWKBIT_REPORT", ret); return ret; } @@ -941,7 +945,7 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type ret = http_client_req(hb_context.sock, &hb_context.http_req, HAWKBIT_RECV_TIMEOUT, "HAWKBIT_REPORT"); if (ret < 0) { - LOG_ERR("Unable to send HTTP request (HAWKBIT_REPORT): %d", ret); + LOG_ERR("Unable to send HTTP request (%s): %d", "HAWKBIT_REPORT", ret); return false; } @@ -951,7 +955,7 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type ret = http_client_req(hb_context.sock, &hb_context.http_req, HAWKBIT_RECV_TIMEOUT, "HAWKBIT_DOWNLOAD"); if (ret < 0) { - LOG_ERR("Unable to send HTTP request (HAWKBIT_DOWNLOAD): %d", ret); + LOG_ERR("Unable to send HTTP request (%s): %d", "HAWKBIT_DOWNLOAD", ret); return false; } @@ -981,7 +985,7 @@ enum hawkbit_response hawkbit_probe(void) hb_context.response_data = malloc(RESPONSE_BUFFER_SIZE); if (!boot_is_img_confirmed()) { - LOG_ERR("The current image is not confirmed"); + LOG_ERR("Current image is not confirmed"); hb_context.code_status = HAWKBIT_UNCONFIRMED_IMAGE; goto error; } @@ -1004,7 +1008,7 @@ enum hawkbit_response hawkbit_probe(void) /* * Query the hawkbit base polling resource. */ - LOG_INF("Polling target data from Hawkbit"); + LOG_INF("Polling target data from hawkBit"); memset(hb_context.url_buffer, 0, sizeof(hb_context.url_buffer)); hb_context.dl.http_content_size = 0; @@ -1016,7 +1020,7 @@ enum hawkbit_response hawkbit_probe(void) if (!send_request(HTTP_GET, HAWKBIT_PROBE, HAWKBIT_STATUS_FINISHED_NONE, HAWKBIT_STATUS_EXEC_NONE)) { - LOG_ERR("Send request failed (HAWKBIT_PROBE)"); + LOG_ERR("Send request failed (%s)", "HAWKBIT_PROBE"); hb_context.code_status = HAWKBIT_NETWORKING_ERROR; goto cleanup; } @@ -1043,7 +1047,7 @@ enum hawkbit_response hawkbit_probe(void) if (!send_request(HTTP_POST, HAWKBIT_CLOSE, HAWKBIT_STATUS_FINISHED_SUCCESS, HAWKBIT_STATUS_EXEC_CLOSED)) { - LOG_ERR("Send request failed (HAWKBIT_CLOSE)"); + LOG_ERR("Send request failed (%s)", "HAWKBIT_CLOSE"); hb_context.code_status = HAWKBIT_NETWORKING_ERROR; goto cleanup; } @@ -1058,12 +1062,12 @@ enum hawkbit_response hawkbit_probe(void) memset(hb_context.url_buffer, 0, sizeof(hb_context.url_buffer)); hb_context.dl.http_content_size = 0; hb_context.url_buffer_size = URL_BUFFER_SIZE; - snprintk(hb_context.url_buffer, hb_context.url_buffer_size, "%s/%s-%s/configData", - HAWKBIT_JSON_URL, CONFIG_BOARD, device_id); + snprintk(hb_context.url_buffer, hb_context.url_buffer_size, "%s/%s-%s/%s", + HAWKBIT_JSON_URL, CONFIG_BOARD, device_id, "configData"); if (!send_request(HTTP_PUT, HAWKBIT_CONFIG_DEVICE, HAWKBIT_STATUS_FINISHED_SUCCESS, HAWKBIT_STATUS_EXEC_CLOSED)) { - LOG_ERR("Send request failed (HAWKBIT_CONFIG_DEVICE)"); + LOG_ERR("Send request failed (%s)", "HAWKBIT_CONFIG_DEVICE"); hb_context.code_status = HAWKBIT_NETWORKING_ERROR; goto cleanup; } @@ -1092,7 +1096,7 @@ enum hawkbit_response hawkbit_probe(void) if (!send_request(HTTP_GET, HAWKBIT_PROBE_DEPLOYMENT_BASE, HAWKBIT_STATUS_FINISHED_NONE, HAWKBIT_STATUS_EXEC_NONE)) { - LOG_ERR("Send request failed (HAWKBIT_PROBE_DEPLOYMENT_BASE)"); + LOG_ERR("Send request failed (%s)", "HAWKBIT_PROBE_DEPLOYMENT_BASE"); hb_context.code_status = HAWKBIT_NETWORKING_ERROR; goto cleanup; } @@ -1107,7 +1111,7 @@ enum hawkbit_response hawkbit_probe(void) ret = hawkbit_parse_deployment(&hawkbit_results.dep, &hb_context.json_action_id, download_http, &file_size); if (ret < 0) { - LOG_ERR("Unable to parse deployment base: %d", ret); + LOG_ERR("Failed to parse deploymentBase: %d", ret); goto cleanup; } @@ -1119,12 +1123,12 @@ enum hawkbit_response hawkbit_probe(void) memset(hb_context.url_buffer, 0, sizeof(hb_context.url_buffer)); hb_context.url_buffer_size = URL_BUFFER_SIZE; snprintk(hb_context.url_buffer, hb_context.url_buffer_size, - "%s/%s-%s/deploymentBase/%d/feedback", HAWKBIT_JSON_URL, CONFIG_BOARD, - device_id, hb_context.json_action_id); + "%s/%s-%s/%s/%d/feedback", HAWKBIT_JSON_URL, CONFIG_BOARD, + device_id, "deploymentBase", hb_context.json_action_id); if (!send_request(HTTP_POST, HAWKBIT_REPORT, HAWKBIT_STATUS_FINISHED_SUCCESS, HAWKBIT_STATUS_EXEC_CLOSED)) { - LOG_ERR("Send request failed (HAWKBIT_REPORT)"); + LOG_ERR("Send request failed (%s)", "HAWKBIT_REPORT"); hb_context.code_status = HAWKBIT_NETWORKING_ERROR; goto cleanup; } @@ -1143,12 +1147,9 @@ enum hawkbit_response hawkbit_probe(void) flash_img_init(&hb_context.flash_ctx); - ret = (int)send_request(HTTP_GET, HAWKBIT_DOWNLOAD, - HAWKBIT_STATUS_FINISHED_NONE, - HAWKBIT_STATUS_EXEC_NONE); - - if (!ret) { - LOG_ERR("Send request failed (HAWKBIT_DOWNLOAD): %d", ret); + if (send_request(HTTP_GET, HAWKBIT_DOWNLOAD, HAWKBIT_STATUS_FINISHED_NONE, + HAWKBIT_STATUS_EXEC_NONE)) { + LOG_ERR("Send request failed (%s)", "HAWKBIT_DOWNLOAD"); hb_context.code_status = HAWKBIT_NETWORKING_ERROR; goto cleanup; } @@ -1159,7 +1160,7 @@ enum hawkbit_response hawkbit_probe(void) /* Check if download finished */ if (!hb_context.final_data_received) { - LOG_ERR("Download is not complete"); + LOG_ERR("Download incomplete"); hb_context.code_status = HAWKBIT_DOWNLOAD_ERROR; goto cleanup; } @@ -1168,7 +1169,7 @@ enum hawkbit_response hawkbit_probe(void) fic.match = hb_context.dl.file_hash; fic.clen = hb_context.dl.downloaded_size; if (flash_img_check(&hb_context.flash_ctx, &fic, FIXED_PARTITION_ID(SLOT1_LABEL))) { - LOG_ERR("Firmware - flash validation has failed"); + LOG_ERR("Failed to validate stored firmware"); hb_context.code_status = HAWKBIT_DOWNLOAD_ERROR; goto cleanup; } @@ -1199,7 +1200,7 @@ static void autohandler(struct k_work *work) { switch (hawkbit_probe()) { case HAWKBIT_UNCONFIRMED_IMAGE: - LOG_ERR("Image is unconfirmed"); + LOG_ERR("Current image is not confirmed"); LOG_ERR("Rebooting to previous confirmed image"); LOG_ERR("If this image is flashed using a hardware tool"); LOG_ERR("Make sure that it is a confirmed image"); @@ -1212,7 +1213,7 @@ static void autohandler(struct k_work *work) break; case HAWKBIT_CANCEL_UPDATE: - LOG_INF("Hawkbit update cancelled from server"); + LOG_INF("hawkBit update cancelled from server"); break; case HAWKBIT_OK: @@ -1240,7 +1241,7 @@ static void autohandler(struct k_work *work) break; case HAWKBIT_PROBE_IN_PROGRESS: - LOG_INF("Hawkbit is already running"); + LOG_INF("hawkBit is already running"); break; } From 90be983d4d0fc91b73b9f669e5fa7e37d6020c3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Fri, 15 Mar 2024 08:05:59 +0100 Subject: [PATCH 0736/2402] logging: backends: multidomain: Fix compilation warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix compilation warning due to taking member from a packed structure and assigning it to a pointer. Compiler warns that it may be unaligned. However, it is ensured that it will be aligned by operations preceding this assignment. Signed-off-by: Krzysztof Chruściński --- subsys/logging/backends/log_multidomain_backend.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/subsys/logging/backends/log_multidomain_backend.c b/subsys/logging/backends/log_multidomain_backend.c index 603c433b5d6..5cf5087a603 100644 --- a/subsys/logging/backends/log_multidomain_backend.c +++ b/subsys/logging/backends/log_multidomain_backend.c @@ -32,13 +32,16 @@ static void process(const struct log_backend *const backend, return; } - /* Need to ensure that package is aligned to a pointer size. */ + /* Need to ensure that package is aligned to a pointer size even though + * it is in the packed structured. + */ uint32_t msg_len = Z_LOG_MSG_LEN(fsc_plen, dlen); uint8_t buf[msg_len + sizeof(void *)] __aligned(sizeof(void *)); size_t msg_offset = offsetof(struct log_multidomain_msg, data); struct log_multidomain_msg *out_msg = (struct log_multidomain_msg *)&buf[sizeof(void *) - msg_offset]; - struct log_msg *out_log_msg = (struct log_msg *)out_msg->data.log_msg.data; + uintptr_t out_log_msg_ptr = (uintptr_t)out_msg->data.log_msg.data; + struct log_msg *out_log_msg = (struct log_msg *)out_log_msg_ptr; /* Set ipc message id. */ out_msg->id = Z_LOG_MULTIDOMAIN_ID_MSG; From 8c1914227818d44755b71da4a8a40b77a628d959 Mon Sep 17 00:00:00 2001 From: YunZe Li Date: Fri, 8 Mar 2024 11:22:32 +0800 Subject: [PATCH 0737/2402] drivers: watchdog: fix wdt_counter_setup option checking condition The expression (options & WDT_OPT_PAUSE_IN_SLEEP) is duplicated. Fix it by replacing the second one with (options &WDT_OPT_PAUSE_HALTED_BY_DBG). Signed-off-by: YunZe Li --- drivers/watchdog/wdt_counter.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/wdt_counter.c b/drivers/watchdog/wdt_counter.c index 9d08d25dfa7..a26e5d23eec 100644 --- a/drivers/watchdog/wdt_counter.c +++ b/drivers/watchdog/wdt_counter.c @@ -33,7 +33,7 @@ static int wdt_counter_setup(const struct device *dev, uint8_t options) const struct wdt_counter_config *config = dev->config; const struct device *counter = config->counter; - if ((options & WDT_OPT_PAUSE_IN_SLEEP) || (options & WDT_OPT_PAUSE_IN_SLEEP)) { + if ((options & WDT_OPT_PAUSE_IN_SLEEP) || (options & WDT_OPT_PAUSE_HALTED_BY_DBG)) { return -ENOTSUP; } From 10670b751511629ab9112ee1185d127f8fb52a23 Mon Sep 17 00:00:00 2001 From: Fengming Ye Date: Tue, 12 Mar 2024 11:12:05 +0900 Subject: [PATCH 0738/2402] net: zperf: multicast support on multi interfaces Zperf upload multicast always use default interface. Zperf download multicast cannot receive packets from other than 224.0.0.1 which is default multicast group. Add zperf upload/download option -I for multicast. So that user can select interface for multicast. Add join multicast group for zperf download. Use the "device list" command to get the interface name as follows: "- ua (READY)" #uAP interface name "- ml (READY)" #STA interface name Multicast traffic commands: zperf udp upload -a -I ua 224.0.0.2 5001 10 1470 1M zperf udp download -I ua 5001 224.0.0.3 Signed-off-by: Fengming Ye --- include/zephyr/net/zperf.h | 3 + subsys/net/lib/zperf/zperf_shell.c | 98 ++++++++++++++++++++++- subsys/net/lib/zperf/zperf_udp_receiver.c | 85 ++++++++++++++++++++ subsys/net/lib/zperf/zperf_udp_uploader.c | 12 +++ 4 files changed, 196 insertions(+), 2 deletions(-) diff --git a/include/zephyr/net/zperf.h b/include/zephyr/net/zperf.h index 842d96f9bb3..a6290483300 100644 --- a/include/zephyr/net/zperf.h +++ b/include/zephyr/net/zperf.h @@ -18,6 +18,7 @@ #define ZEPHYR_INCLUDE_NET_ZPERF_H_ #include +#include #ifdef __cplusplus extern "C" { @@ -34,6 +35,7 @@ struct zperf_upload_params { uint32_t duration_ms; uint32_t rate_kbps; uint16_t packet_size; + char if_name[IFNAMSIZ]; struct { uint8_t tos; int tcp_nodelay; @@ -44,6 +46,7 @@ struct zperf_upload_params { struct zperf_download_params { uint16_t port; struct sockaddr addr; + char if_name[IFNAMSIZ]; }; struct zperf_results { diff --git a/subsys/net/lib/zperf/zperf_shell.c b/subsys/net/lib/zperf/zperf_shell.c index 3e56e8c2eb5..d5c99da6be9 100644 --- a/subsys/net/lib/zperf/zperf_shell.c +++ b/subsys/net/lib/zperf/zperf_shell.c @@ -368,6 +368,53 @@ static void udp_session_cb(enum zperf_status status, } } +/* + * parse download options with '-' + * return < 0 if parse error + * return 0 if no '-' options + * return > 0 num of argc we parsed + * and following parse starts from this num + */ +static int shell_cmd_download(const struct shell *sh, size_t argc, + char *argv[], + struct zperf_download_params *param) +{ + int opt_cnt = 0; + size_t i; + + for (i = 1; i < argc; ++i) { + if (*argv[i] != '-') { + break; + } + + switch (argv[i][1]) { + case 'I': + /* + * IFNAMSIZ by default CONFIG_NET_INTERFACE_NAME_LEN + * is at least 1 so no overflow risk here + */ + i++; + if (i >= argc) { + shell_fprintf(sh, SHELL_WARNING, + "-I \n"); + return -ENOEXEC; + } + (void)memset(param->if_name, 0x0, IFNAMSIZ); + strncpy(param->if_name, argv[i], IFNAMSIZ - 1); + + opt_cnt += 2; + break; + + default: + shell_fprintf(sh, SHELL_WARNING, + "Unrecognized argument: %s\n", argv[i]); + return -ENOEXEC; + } + } + + return opt_cnt; +} + static int cmd_udp_download_stop(const struct shell *sh, size_t argc, char *argv[]) { @@ -390,8 +437,16 @@ static int cmd_udp_download(const struct shell *sh, size_t argc, if (IS_ENABLED(CONFIG_NET_UDP)) { struct zperf_download_params param = { 0 }; int ret; + int start; + + start = shell_cmd_download(sh, argc, argv, ¶m); + if (start < 0) { + shell_fprintf(sh, SHELL_WARNING, + "Unable to parse option.\n"); + return -ENOEXEC; + } - ret = zperf_bind_host(sh, argc, argv, ¶m); + ret = zperf_bind_host(sh, argc - start, &argv[start], ¶m); if (ret < 0) { shell_fprintf(sh, SHELL_WARNING, "Unable to bind host.\n"); @@ -801,6 +856,19 @@ static int shell_cmd_upload(const struct shell *sh, size_t argc, break; #endif /* CONFIG_NET_CONTEXT_PRIORITY */ + case 'I': + i++; + if (i >= argc) { + shell_fprintf(sh, SHELL_WARNING, + "-I \n"); + return -ENOEXEC; + } + (void)memset(param.if_name, 0x0, IFNAMSIZ); + strncpy(param.if_name, argv[i], IFNAMSIZ - 1); + + opt_cnt += 2; + break; + default: shell_fprintf(sh, SHELL_WARNING, "Unrecognized argument: %s\n", argv[i]); @@ -987,6 +1055,19 @@ static int shell_cmd_upload2(const struct shell *sh, size_t argc, break; #endif /* CONFIG_NET_CONTEXT_PRIORITY */ + case 'I': + i++; + if (i >= argc) { + shell_fprintf(sh, SHELL_WARNING, + "-I \n"); + return -ENOEXEC; + } + (void)memset(param.if_name, 0x0, IFNAMSIZ); + strncpy(param.if_name, argv[i], IFNAMSIZ - 1); + + opt_cnt += 2; + break; + default: shell_fprintf(sh, SHELL_WARNING, "Unrecognized argument: %s\n", argv[i]); @@ -1177,8 +1258,16 @@ static int cmd_tcp_download(const struct shell *sh, size_t argc, if (IS_ENABLED(CONFIG_NET_TCP)) { struct zperf_download_params param = { 0 }; int ret; + int start; + + start = shell_cmd_download(sh, argc, argv, ¶m); + if (start < 0) { + shell_fprintf(sh, SHELL_WARNING, + "Unable to parse option.\n"); + return -ENOEXEC; + } - ret = zperf_bind_host(sh, argc, argv, ¶m); + ret = zperf_bind_host(sh, argc - start, &argv[start], ¶m); if (ret < 0) { shell_fprintf(sh, SHELL_WARNING, "Unable to bind host.\n"); @@ -1345,6 +1434,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_udp, #ifdef CONFIG_NET_CONTEXT_PRIORITY "-p: Specify custom packet priority\n" #endif /* CONFIG_NET_CONTEXT_PRIORITY */ + "-I: Specify host interface name\n" "Example: udp upload 192.0.2.2 1111 1 1K 1M\n" "Example: udp upload 2001:db8::2\n", cmd_udp_upload), @@ -1362,6 +1452,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_udp, #ifdef CONFIG_NET_CONTEXT_PRIORITY "-p: Specify custom packet priority\n" #endif /* CONFIG_NET_CONTEXT_PRIORITY */ + "-I: Specify host interface name\n" "Example: udp upload2 v4 1 1K 1M\n" "Example: udp upload2 v6\n" #if defined(CONFIG_NET_IPV6) && defined(MY_IP6ADDR_SET) @@ -1375,8 +1466,11 @@ SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_udp, , cmd_udp_upload2), SHELL_CMD(download, &zperf_cmd_udp_download, + "[] command options (optional): [-I eth0]\n" "[]: Server port to listen on/connect to\n" "[]: Bind to , an interface address\n" + "Available options:\n" + "-I : Specify host interface name\n" "Example: udp download 5001 192.168.0.1\n", cmd_udp_download), SHELL_SUBCMD_SET_END diff --git a/subsys/net/lib/zperf/zperf_udp_receiver.c b/subsys/net/lib/zperf/zperf_udp_receiver.c index 5f6c7c539fd..9991cf50fcc 100644 --- a/subsys/net/lib/zperf/zperf_udp_receiver.c +++ b/subsys/net/lib/zperf/zperf_udp_receiver.c @@ -23,6 +23,10 @@ LOG_MODULE_DECLARE(net_zperf, CONFIG_NET_ZPERF_LOG_LEVEL); #define NET_LOG_ENABLED 1 #include "net_private.h" +/* To support multicast */ +#include "ipv6.h" +#include "zephyr/net/igmp.h" + static struct sockaddr_in6 *in6_addr_my; static struct sockaddr_in *in4_addr_my; @@ -45,6 +49,7 @@ static void udp_svc_handler(struct k_work *work); NET_SOCKET_SERVICE_SYNC_DEFINE_STATIC(svc_udp, NULL, udp_svc_handler, SOCK_ID_MAX); +static char udp_server_iface_name[IFNAMSIZ]; static inline void build_reply(struct zperf_udp_datagram *hdr, struct zperf_server_hdr *stat, @@ -225,6 +230,63 @@ static void udp_received(int sock, const struct sockaddr *addr, uint8_t *data, } } +static void zperf_udp_join_mcast_ipv4(char *if_name, struct in_addr *addr) +{ + struct net_if *iface = NULL; + + if (if_name[0]) { + iface = net_if_get_by_index(net_if_get_by_name(if_name)); + if (iface == NULL) + iface = net_if_get_default(); + } else { + iface = net_if_get_default(); + } + + if (iface != NULL) { + net_ipv4_igmp_join(iface, addr, NULL); + } +} + +static void zperf_udp_join_mcast_ipv6(char *if_name, struct in6_addr *addr) +{ + struct net_if *iface = NULL; + + if (if_name[0]) { + iface = net_if_get_by_index(net_if_get_by_name(if_name)); + if (iface == NULL) + iface = net_if_get_default(); + } else { + iface = net_if_get_default(); + } + + if (iface != NULL) { + net_ipv6_mld_join(iface, addr); + } +} + +static void zperf_udp_leave_mcast(int sock) +{ + struct net_if *iface = NULL; + struct sockaddr addr = {0}; + socklen_t addr_len = NET_IPV6_ADDR_SIZE; + + zsock_getsockname(sock, &addr, &addr_len); + + if (IS_ENABLED(CONFIG_NET_IPV4) && addr.sa_family == AF_INET) { + struct sockaddr_in *addr4 = (struct sockaddr_in *)&addr; + + if (net_ipv4_is_addr_mcast(&addr4->sin_addr)) + net_ipv4_igmp_leave(iface, &addr4->sin_addr); + } + + if (IS_ENABLED(CONFIG_NET_IPV6) && addr.sa_family == AF_INET6) { + struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *)&addr; + + if (net_ipv6_is_addr_mcast(&addr6->sin6_addr)) + net_ipv6_mld_leave(iface, &addr6->sin6_addr); + } +} + static void udp_receiver_cleanup(void) { int i; @@ -233,6 +295,7 @@ static void udp_receiver_cleanup(void) for (i = 0; i < ARRAY_SIZE(fds); i++) { if (fds[i].fd >= 0) { + zperf_udp_leave_mcast(fds[i].fd); zsock_close(fds[i].fd); fds[i].fd = -1; } @@ -350,6 +413,11 @@ static int zperf_udp_receiver_init(void) in4_addr_my->sin_addr.s_addr = INADDR_ANY; } + if (net_ipv4_is_addr_mcast(&in4_addr_my->sin_addr)) { + zperf_udp_join_mcast_ipv4(udp_server_iface_name, + &in4_addr_my->sin_addr); + } + NET_INFO("Binding to %s", net_sprint_ipv4_addr(&in4_addr_my->sin_addr)); @@ -402,6 +470,11 @@ static int zperf_udp_receiver_init(void) sizeof(struct in6_addr)); } + if (net_ipv6_is_addr_mcast(&in6_addr_my->sin6_addr)) { + zperf_udp_join_mcast_ipv6(udp_server_iface_name, + &in6_addr_my->sin6_addr); + } + NET_INFO("Binding to %s", net_sprint_ipv6_addr(&in6_addr_my->sin6_addr)); @@ -451,6 +524,18 @@ int zperf_udp_download(const struct zperf_download_params *param, udp_server_port = param->port; memcpy(&udp_server_addr, ¶m->addr, sizeof(struct sockaddr)); + if (param->if_name[0]) { + /* + * IFNAMSIZ by default CONFIG_NET_INTERFACE_NAME_LEN + * is at least 1 so no overflow risk here + */ + (void)memset(udp_server_iface_name, 0, IFNAMSIZ); + strncpy(udp_server_iface_name, param->if_name, IFNAMSIZ); + udp_server_iface_name[IFNAMSIZ - 1] = 0; + } else { + udp_server_iface_name[0] = 0; + } + ret = zperf_udp_receiver_init(); if (ret < 0) { udp_receiver_cleanup(); diff --git a/subsys/net/lib/zperf/zperf_udp_uploader.c b/subsys/net/lib/zperf/zperf_udp_uploader.c index 49c211ba73c..548a0a55f10 100644 --- a/subsys/net/lib/zperf/zperf_udp_uploader.c +++ b/subsys/net/lib/zperf/zperf_udp_uploader.c @@ -288,6 +288,7 @@ int zperf_udp_upload(const struct zperf_upload_params *param, int port = 0; int sock; int ret; + struct ifreq req; if (param == NULL || result == NULL) { return -EINVAL; @@ -309,6 +310,17 @@ int zperf_udp_upload(const struct zperf_upload_params *param, return sock; } + if (param->if_name[0]) { + (void)memset(req.ifr_name, 0, sizeof(req.ifr_name)); + strncpy(req.ifr_name, param->if_name, IFNAMSIZ); + req.ifr_name[IFNAMSIZ - 1] = 0; + + if (zsock_setsockopt(sock, SOL_SOCKET, SO_BINDTODEVICE, &req, + sizeof(struct ifreq)) != 0) { + NET_WARN("setsockopt SO_BINDTODEVICE error (%d)", -errno); + } + } + ret = udp_upload(sock, port, param, result); zsock_close(sock); From fb54eb5ab13323d45cecae01cd842a06c196b49b Mon Sep 17 00:00:00 2001 From: Bjarki Arge Andreasen Date: Wed, 13 Mar 2024 11:41:45 +0100 Subject: [PATCH 0739/2402] llext: symbol.h: Explicit typecast in EXPORT_SYMBOL macros Some compilers (especially C++ compilers) will complain with invalid conversion (-fpermissive) if the void pointers are not explicitly typecast. This PR adds said typecast. Signed-off-by: Bjarki Arge Andreasen --- include/zephyr/llext/symbol.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/zephyr/llext/symbol.h b/include/zephyr/llext/symbol.h index 19f34649026..993e2c4a519 100644 --- a/include/zephyr/llext/symbol.h +++ b/include/zephyr/llext/symbol.h @@ -76,12 +76,12 @@ struct llext_symtable { */ #define EXPORT_SYMBOL(x) \ static const STRUCT_SECTION_ITERABLE(llext_const_symbol, x ## _sym) = { \ - .name = STRINGIFY(x), .addr = &x, \ + .name = STRINGIFY(x), .addr = (const void *)&x, \ } #define LL_EXTENSION_SYMBOL(x) \ struct llext_symbol Z_GENERIC_SECTION(".exported_sym") __used \ - symbol_##x = {STRINGIFY(x), &x} + symbol_##x = {STRINGIFY(x), (void *)&x} /** * @brief Export a system call to a table of symbols From 7b916593ec084c29ecaae247789922e4c2458a2a Mon Sep 17 00:00:00 2001 From: Maochen Wang Date: Fri, 15 Mar 2024 16:21:12 +0800 Subject: [PATCH 0740/2402] net: igmp: Fix double unref of igmp packet If send the igmp packet when lower interface is down, the packet will be freed twice and show error log. Remove the net_pkt_unref in igmp_send(), and let the caller free it. Signed-off-by: Maochen Wang --- subsys/net/ip/igmp.c | 1 - 1 file changed, 1 deletion(-) diff --git a/subsys/net/ip/igmp.c b/subsys/net/ip/igmp.c index 2de3b2f9f94..f4be802f968 100644 --- a/subsys/net/ip/igmp.c +++ b/subsys/net/ip/igmp.c @@ -255,7 +255,6 @@ static int igmp_send(struct net_pkt *pkt) ret = net_send_data(pkt); if (ret < 0) { net_stats_update_ipv4_igmp_drop(net_pkt_iface(pkt)); - net_pkt_unref(pkt); return ret; } From ceff785434b970a4570d82023dc136ef8a050f3f Mon Sep 17 00:00:00 2001 From: Vidar Berg Date: Wed, 13 Mar 2024 14:02:16 +0100 Subject: [PATCH 0741/2402] drivers: bluetooth: hci: Apply workaround for HW anomaly on nRF53 Use the nrf_reset_network_force_off() function to release and set the force-off signal.This ensures that the workaround for errata 161 is applied. Signed-off-by: Vidar Berg --- drivers/bluetooth/hci/nrf53_support.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/bluetooth/hci/nrf53_support.c b/drivers/bluetooth/hci/nrf53_support.c index 7fa91f4eb2f..995586eb325 100644 --- a/drivers/bluetooth/hci/nrf53_support.c +++ b/drivers/bluetooth/hci/nrf53_support.c @@ -6,6 +6,7 @@ #include #include +#include #if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) #include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> #else @@ -19,9 +20,9 @@ LOG_MODULE_REGISTER(bt_hci_nrf53_support); int bt_hci_transport_teardown(const struct device *dev) { ARG_UNUSED(dev); - /* Put core into reset */ - NRF_RESET->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Hold; - LOG_DBG("Network MCU reseted."); + /* Put the Network MCU in Forced-OFF mode. */ + nrf_reset_network_force_off(NRF_RESET, true); + LOG_DBG("Network MCU placed in Forced-OFF mode"); return 0; } @@ -41,7 +42,8 @@ int bt_hci_transport_setup(const struct device *dev) NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; #endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ - NRF_RESET->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release; + /* Release the Network MCU, 'Release force off signal' */ + nrf_reset_network_force_off(NRF_RESET, false); return 0; } From ca4ff1e6fe97dc00e316d6833ac4ee5c01da43e2 Mon Sep 17 00:00:00 2001 From: Michele Sardo Date: Fri, 1 Mar 2024 16:32:20 +0100 Subject: [PATCH 0742/2402] drivers: spi: keep SPI enabled if SPI_HOLD_ON_CS is used Keep the SPI enabled when performing multiple transaction with SPI_HOLD_ON_CS. In such case, the end of transaction is marked by application calling spi_release. Signed-off-by: Michele Sardo --- drivers/spi/spi_ll_stm32.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi_ll_stm32.c b/drivers/spi/spi_ll_stm32.c index 7f444f664ba..e24b9722d06 100644 --- a/drivers/spi/spi_ll_stm32.c +++ b/drivers/spi/spi_ll_stm32.c @@ -448,9 +448,9 @@ static void spi_stm32_complete(const struct device *dev, int status) { const struct spi_stm32_config *cfg = dev->config; SPI_TypeDef *spi = cfg->spi; -#ifdef CONFIG_SPI_STM32_INTERRUPT struct spi_stm32_data *data = dev->data; +#ifdef CONFIG_SPI_STM32_INTERRUPT ll_func_disable_int_tx_empty(spi); ll_func_disable_int_rx_not_empty(spi); ll_func_disable_int_errors(spi); @@ -493,7 +493,9 @@ static void spi_stm32_complete(const struct device *dev, int status) } #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */ - ll_func_disable_spi(spi); + if (!(data->ctx.config->operation & SPI_HOLD_ON_CS)) { + ll_func_disable_spi(spi); + } #ifdef CONFIG_SPI_STM32_INTERRUPT spi_context_complete(&data->ctx, dev, status); @@ -687,8 +689,10 @@ static int spi_stm32_release(const struct device *dev, const struct spi_config *config) { struct spi_stm32_data *data = dev->data; + const struct spi_stm32_config *cfg = dev->config; spi_context_unlock_unconditionally(&data->ctx); + ll_func_disable_spi(cfg->spi); return 0; } From aa58fb0f0ae52895d9d33367eaa1b89a4bd22656 Mon Sep 17 00:00:00 2001 From: Michele Sardo Date: Fri, 1 Mar 2024 16:32:42 +0100 Subject: [PATCH 0743/2402] drivers: bluetooth: hci: Enable SPI_LOCK_ON mode Use SPI_LOCK_ON to lock configuration for multiple transaction while CS is kept low. Change control of CS line from direct GPIO manipulation to SPI driver API. Signed-off-by: Michele Sardo --- drivers/bluetooth/hci/hci_spi_st.c | 35 ++++++++++++------------------ 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/drivers/bluetooth/hci/hci_spi_st.c b/drivers/bluetooth/hci/hci_spi_st.c index 7f3ee523d29..b9e1c450447 100644 --- a/drivers/bluetooth/hci/hci_spi_st.c +++ b/drivers/bluetooth/hci/hci_spi_st.c @@ -96,7 +96,7 @@ static struct k_thread spi_rx_thread_data; static int bt_spi_send_aci_config(uint8_t offset, const uint8_t *value, size_t value_len); static const struct spi_dt_spec bus = SPI_DT_SPEC_INST_GET( - 0, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0); + 0, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8) | SPI_LOCK_ON, 0); static struct spi_buf spi_tx_buf; static struct spi_buf spi_rx_buf; @@ -171,16 +171,10 @@ static bool bt_spi_handle_vendor_evt(uint8_t *msg) /* as long as IRQ pin is high */ #define READ_CONDITION IS_IRQ_HIGH -static void assert_cs(void) -{ - gpio_pin_set_dt(&bus.config.cs.gpio, 0); - gpio_pin_set_dt(&bus.config.cs.gpio, 1); -} - static void release_cs(bool data_transaction) { ARG_UNUSED(data_transaction); - gpio_pin_set_dt(&bus.config.cs.gpio, 0); + spi_release_dt(&bus); } static int bt_spi_get_header(uint8_t op, uint16_t *size) @@ -210,7 +204,8 @@ static int bt_spi_get_header(uint8_t op, uint16_t *size) return 0; } } - assert_cs(); + /* Make sure CS is raised before a new attempt */ + gpio_pin_set_dt(&bus.config.cs.gpio, 0); ret = bt_spi_transceive(header_master, 5, header_slave, 5); if (ret) { /* SPI transaction failed */ @@ -229,16 +224,6 @@ static int bt_spi_get_header(uint8_t op, uint16_t *size) #define READ_CONDITION false -static void assert_cs(uint16_t delay) -{ - gpio_pin_set_dt(&bus.config.cs.gpio, 0); - if (delay) { - k_sleep(K_USEC(delay)); - } - gpio_pin_set_dt(&bus.config.cs.gpio, 1); - gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_DISABLE); -} - static void release_cs(bool data_transaction) { /* Consume possible event signals */ @@ -250,7 +235,7 @@ static void release_cs(bool data_transaction) } } gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_EDGE_TO_ACTIVE); - gpio_pin_set_dt(&bus.config.cs.gpio, 0); + spi_release_dt(&bus); } static int bt_spi_get_header(uint8_t op, uint16_t *size) @@ -276,7 +261,15 @@ static int bt_spi_get_header(uint8_t op, uint16_t *size) return -EINVAL; } - assert_cs(cs_delay); + if (cs_delay) { + k_sleep(K_USEC(cs_delay)); + } + /* Perform a zero byte SPI transaction to acquire the SPI lock and lower CS + * while waiting for IRQ to be raised + */ + bt_spi_transceive(header_master, 0, header_slave, 0); + gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_DISABLE); + /* Wait up to a maximum time of 100 ms */ if (!WAIT_FOR(IS_IRQ_HIGH, 100000, k_usleep(100))) { LOG_ERR("IRQ pin did not raise"); From ae4e71f7902d325f7957659f78d55ff172812be1 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 15 Mar 2024 13:50:46 +0100 Subject: [PATCH 0744/2402] boards/nxp/frdm_mcxn947: Fix twister yaml This board's twister yaml file claims to support the arduino-serial tests, but it does not provide the necessary DTS node, which is causing failures in CI. Let's remove the tag from the twister board definition. Signed-off-by: Alberto Escolar Piedras --- boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml index fb213bb25a6..31825f6b518 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -15,6 +15,5 @@ toolchain: - gnuarmemb - xtools supported: - - arduino_serial - gpio vendor: nxp From cb0a12311bc4ba12f49ce641b1380186e9930ba0 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Wed, 13 Mar 2024 14:50:20 +0100 Subject: [PATCH 0745/2402] net: tcp: Remove redundant debug logs Debug logs in helper functions like tcp_unsent_len() or tcp_window_full() are not very helpful and generate a heavy, unnecessary log output. Therefore, tcp_unsent_len() will no longer generate log, and tcp_window_full() will print out a log only when the window is actually full, which could be an useful information. Also, reduce the log load during TX, as currently redundant logs were printed in tcp_out_ext(), tcp_send_process_no_lock() and finally in tcp_send(). Signed-off-by: Robert Lubos --- subsys/net/ip/tcp.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/subsys/net/ip/tcp.c b/subsys/net/ip/tcp.c index 3c8f17bec7f..598af5050e6 100644 --- a/subsys/net/ip/tcp.c +++ b/subsys/net/ip/tcp.c @@ -324,8 +324,6 @@ static const char *tcp_th(struct net_pkt *pkt) static void tcp_send(struct net_pkt *pkt) { - NET_DBG("%s", tcp_th(pkt)); - tcp_pkt_ref(pkt); if (tcp_send_cb) { @@ -1463,6 +1461,8 @@ void net_tcp_reply_rst(struct net_pkt *pkt) goto err; } + NET_DBG("%s", tcp_th(rst)); + tcp_send(rst); return; @@ -1520,8 +1520,6 @@ static int tcp_out_ext(struct tcp *conn, uint8_t flags, struct net_pkt *data, goto out; } - NET_DBG("%s", tcp_th(pkt)); - if (tcp_send_cb) { ret = tcp_send_cb(pkt); goto out; @@ -1631,7 +1629,9 @@ static bool tcp_window_full(struct tcp *conn) window_full = window_full || (conn->send_data_total >= conn->ca.cwnd); #endif - NET_DBG("conn: %p window_full=%hu", conn, window_full); + if (window_full) { + NET_DBG("conn: %p TX window_full", conn); + } return window_full; } @@ -1662,8 +1662,6 @@ static int tcp_unsent_len(struct tcp *conn) #endif } out: - NET_DBG("unsent_len=%d", unsent_len); - return unsent_len; } From 5158ea4af0a5ab6b670ca0c4718e64eb7e6891c6 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 13 Mar 2024 14:56:24 +0100 Subject: [PATCH 0746/2402] ci: Ensure twister steps use the bsim version from the manifest The west manifest may point to a newer version of bsim than the one avaliable in the docker image. Let's ensure we run with that one. This is equivalent to the change done in 933d338c9783cce55466fed000baf2f3beeac891 for the bsim-tests workflow. Note that the update and rebuild is incremental, so if the docker image already has the right version the operation is very fast (~1 second) Signed-off-by: Alberto Escolar Piedras --- .github/workflows/clang.yaml | 11 +++++++++++ .github/workflows/codecov.yaml | 11 +++++++++++ .github/workflows/twister.yaml | 11 +++++++++++ 3 files changed, 33 insertions(+) diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index 41c07278edb..96ac41fd37e 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -89,6 +89,17 @@ jobs: ccache -p ccache -z -s -vv + - name: Update BabbleSim to manifest revision + run: | + export BSIM_VERSION=$( west list bsim -f {revision} ) + echo "Manifest points to bsim sha $BSIM_VERSION" + cd /opt/bsim_west/bsim + git fetch -n origin ${BSIM_VERSION} + git config --global advice.detachedHead false + git checkout ${BSIM_VERSION} + west update + make everything -s -j 8 + - name: Run Tests with Twister id: twister run: | diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 47b3785a47c..402ed3e1862 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -85,6 +85,17 @@ jobs: ccache -p ccache -z -s -vv + - name: Update BabbleSim to manifest revision + run: | + export BSIM_VERSION=$( west list bsim -f {revision} ) + echo "Manifest points to bsim sha $BSIM_VERSION" + cd /opt/bsim_west/bsim + git fetch -n origin ${BSIM_VERSION} + git config --global advice.detachedHead false + git checkout ${BSIM_VERSION} + west update + make everything -s -j 8 + - name: Run Tests with Twister (Push) continue-on-error: true run: | diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index c77bfd4bf53..4bf097c7df2 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -213,6 +213,17 @@ jobs: ccache -p ccache -z -s -vv + - name: Update BabbleSim to manifest revision + run: | + export BSIM_VERSION=$( west list bsim -f {revision} ) + echo "Manifest points to bsim sha $BSIM_VERSION" + cd /opt/bsim_west/bsim + git fetch -n origin ${BSIM_VERSION} + git config --global advice.detachedHead false + git checkout ${BSIM_VERSION} + west update + make everything -s -j 8 + - if: github.event_name == 'push' name: Run Tests with Twister (Push) run: | From cbef9169733399d80f6e5057faf5b95490f9644f Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 08:38:29 +0100 Subject: [PATCH 0747/2402] ci: bsim update step: Do not affect global git config When updating the bsim install in the docker image's /opt/bsim_west to the version pointed in the Zephyr manifest, we are detaching the head to that version. We suppress the "You are in 'detached HEAD' state..." git warning as it is just noise in CI. So far we were doing it by globally supressing that warning. Let's instead just supress it for the command in question so we don't change global git config against expectations. Signed-off-by: Alberto Escolar Piedras --- .github/workflows/bsim-tests.yaml | 3 +-- .github/workflows/clang.yaml | 3 +-- .github/workflows/codecov.yaml | 3 +-- .github/workflows/twister.yaml | 3 +-- 4 files changed, 4 insertions(+), 8 deletions(-) diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index c7cc0895bb8..15e640b03a0 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -145,8 +145,7 @@ jobs: echo "Manifest points to bsim sha $BSIM_VERSION" cd /opt/bsim_west/bsim git fetch -n origin ${BSIM_VERSION} - git config --global advice.detachedHead false - git checkout ${BSIM_VERSION} + git -c advice.detachedHead=false checkout ${BSIM_VERSION} west update make everything -s -j 8 diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index 96ac41fd37e..edba96022e7 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -95,8 +95,7 @@ jobs: echo "Manifest points to bsim sha $BSIM_VERSION" cd /opt/bsim_west/bsim git fetch -n origin ${BSIM_VERSION} - git config --global advice.detachedHead false - git checkout ${BSIM_VERSION} + git -c advice.detachedHead=false checkout ${BSIM_VERSION} west update make everything -s -j 8 diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 402ed3e1862..158489d5ba1 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -91,8 +91,7 @@ jobs: echo "Manifest points to bsim sha $BSIM_VERSION" cd /opt/bsim_west/bsim git fetch -n origin ${BSIM_VERSION} - git config --global advice.detachedHead false - git checkout ${BSIM_VERSION} + git -c advice.detachedHead=false checkout ${BSIM_VERSION} west update make everything -s -j 8 diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index 4bf097c7df2..0ac79809a3e 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -219,8 +219,7 @@ jobs: echo "Manifest points to bsim sha $BSIM_VERSION" cd /opt/bsim_west/bsim git fetch -n origin ${BSIM_VERSION} - git config --global advice.detachedHead false - git checkout ${BSIM_VERSION} + git -c advice.detachedHead=false checkout ${BSIM_VERSION} west update make everything -s -j 8 From db7a2bada2865391193219d7ef7a6a013d0656b3 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 16:34:17 +0100 Subject: [PATCH 0748/2402] native_posix: Remove twister definition for old native_sim/posix_64 Remove the hwmv1 twister board definitions for native_posix_64 / native_sim_64 in preparation to transition to the new definitions for hwmv2 Signed-off-by: Alberto Escolar Piedras --- .../native/native_posix/native_posix_64.yaml | 21 ------------------- boards/native/native_sim/native_sim_64.yaml | 20 ------------------ 2 files changed, 41 deletions(-) delete mode 100644 boards/native/native_posix/native_posix_64.yaml delete mode 100644 boards/native/native_sim/native_sim_64.yaml diff --git a/boards/native/native_posix/native_posix_64.yaml b/boards/native/native_posix/native_posix_64.yaml deleted file mode 100644 index 544dac9cc2a..00000000000 --- a/boards/native/native_posix/native_posix_64.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: native_posix_64 -name: Native 64-bit POSIX port -type: native -simulation: native -arch: posix -ram: 65536 -flash: 65536 -toolchain: - - host - - llvm -supported: - - can - - counter - - dma - - eeprom - - netif:eth - - usb_device - - adc - - gpio - - rtc -vendor: zephyr diff --git a/boards/native/native_sim/native_sim_64.yaml b/boards/native/native_sim/native_sim_64.yaml deleted file mode 100644 index 52841d23b2b..00000000000 --- a/boards/native/native_sim/native_sim_64.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: native_sim_64 -name: Native Simulation port - 64-bit -type: native -simulation: native -arch: posix -ram: 65536 -flash: 65536 -toolchain: - - host - - llvm -supported: - - can - - counter - - eeprom - - netif:eth - - usb_device - - adc - - gpio - - rtc -vendor: zephyr From 1dd67be2e16a3ec7143fc0128fbe3c330cdfa47e Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:04:46 +0100 Subject: [PATCH 0749/2402] samples/net/telnet: Filter out for NATIVE_APPLICATION This sample enables EVENTFD (through NET_SOCKETS_SERVICE) which is not kconfig compatible with the old NATIVE_APPLICATION targets (native_posix[//64]) Let's explicity filter out this platforms to avoid the sample from failing to build Signed-off-by: Alberto Escolar Piedras --- samples/net/telnet/sample.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/samples/net/telnet/sample.yaml b/samples/net/telnet/sample.yaml index e5e737cbbcd..c3987d33634 100644 --- a/samples/net/telnet/sample.yaml +++ b/samples/net/telnet/sample.yaml @@ -7,3 +7,6 @@ tests: tags: - net - telnet + platform_exclude: + - native_posix + - native_posix/native/64 From ae358704d247729bdd3bad66565469e9fae2e0e6 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:24:38 +0100 Subject: [PATCH 0750/2402] docs/Kconfig help: Replace native_[posix,sim]_64 Replace uses of native_[posix,sim]_64 in the documentation and kconfig help messages with native_[posix,sim]/native/64 to match the hwmv2 naming. Signed-off-by: Alberto Escolar Piedras --- arch/posix/Kconfig | 2 +- boards/native/doc/arch_soc.rst | 2 +- boards/native/native_posix/doc/index.rst | 2 +- boards/native/native_sim/doc/index.rst | 2 +- doc/develop/beyond-GSG.rst | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/posix/Kconfig b/arch/posix/Kconfig index 4ebc8f87c18..a31e1349b21 100644 --- a/arch/posix/Kconfig +++ b/arch/posix/Kconfig @@ -27,7 +27,7 @@ menuconfig ARCH_POSIX_LIBFUZZER help Build the posix app as a LLVM libfuzzer target. Requires support from the toolchain (currently only clang works, and - only on native_posix_64), and should normally be used in + only on native_posix/native/64), and should normally be used in concert with some of CONFIG_ASAN/UBSAN/MSAN for validation. The application needs to implement the LLVMFuzzerTestOneInput() entry point, which runs in the host diff --git a/boards/native/doc/arch_soc.rst b/boards/native/doc/arch_soc.rst index fcc6734d2a6..09edd476349 100644 --- a/boards/native/doc/arch_soc.rst +++ b/boards/native/doc/arch_soc.rst @@ -66,7 +66,7 @@ This port is designed and tested to run in Linux. The 32 bit version of this port does not directly work in Windows Subsystem for Linux (WSL) because WSL does not support native 32-bit binaries. You may want to consider WSL2, or, if using :ref:`native_sim `, - you can also just use the ``native_sim_64`` + you can also just use the ``native_sim/native/64`` target: Check :ref:`32 and 64bit versions`. Otherwise `with some tinkering `_ it diff --git a/boards/native/native_posix/doc/index.rst b/boards/native/native_posix/doc/index.rst index 61e6c164327..950f68193ad 100644 --- a/boards/native/native_posix/doc/index.rst +++ b/boards/native/native_posix/doc/index.rst @@ -91,6 +91,6 @@ dependent on the size of pointers and longs. This target requires either a 64 bit system with multilib support installed or one with a 32bit userspace. -The 64 bit version, ``native_posix_64``, compiles your code targeting the +The 64 bit version, ``native_posix/native/64``, compiles your code targeting the LP64 ABI (x86-64 in x86 systems), where pointers and longs are 64 bits. You can use this target if you cannot compile or run 32 bit binaries. diff --git a/boards/native/native_sim/doc/index.rst b/boards/native/native_sim/doc/index.rst index 9c772691698..3745db84b56 100644 --- a/boards/native/native_sim/doc/index.rst +++ b/boards/native/native_sim/doc/index.rst @@ -166,7 +166,7 @@ dependent on the size of pointers and longs. This target requires either a 64 bit system with multilib support installed or one with a 32bit userspace. -The 64 bit version, ``native_sim_64``, compiles your code targeting the +The 64 bit version, ``native_sim/native/64``, compiles your code targeting the LP64 ABI (x86-64 in x86 systems), where pointers and longs are 64 bits. You can use this target if you cannot compile or run 32 bit binaries. diff --git a/doc/develop/beyond-GSG.rst b/doc/develop/beyond-GSG.rst index 8c965877a43..921cc992912 100644 --- a/doc/develop/beyond-GSG.rst +++ b/doc/develop/beyond-GSG.rst @@ -306,7 +306,7 @@ Run a Sample Application natively (Linux) You can compile some samples to run as host programs on Linux. See :ref:`native_sim` for more information. On 64-bit host operating systems, you -need to install a 32-bit C library, or build targeting :ref:`native_sim_64 `. +need to install a 32-bit C library, or build targeting :ref:`native_sim/native/64`. First, build Hello World for ``native_sim``. From bb18a30f8908ae7ace9be76ab79fe851f56753ef Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:26:54 +0100 Subject: [PATCH 0751/2402] arch/posix cmake: Replace native_posix w native_sim and use hwmv2 names Let's fix the error messages: * native_posix is in general replaced with native_sim * let's use hwmv2 names Signed-off-by: Alberto Escolar Piedras --- arch/posix/Linux.aarch64.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/posix/Linux.aarch64.cmake b/arch/posix/Linux.aarch64.cmake index 6354c3efbc9..c428fef864a 100644 --- a/arch/posix/Linux.aarch64.cmake +++ b/arch/posix/Linux.aarch64.cmake @@ -18,7 +18,7 @@ if (CONFIG_64BIT) if (${WORDSIZE} STREQUAL "32") message(FATAL_ERROR "CONFIG_64BIT=y but this Aarch64 machine has a 32-bit userspace.\n" - "If you were targeting native_posix_64, target native_posix instead.\n" + "If you were targeting native_sim/native/64, target native_sim instead.\n" "Otherwise, be sure to define CONFIG_64BIT appropriately.\n" ) endif() @@ -27,7 +27,7 @@ else () if (${WORDSIZE} STREQUAL "64") message(FATAL_ERROR "CONFIG_64BIT=n but this Aarch64 machine has a 64-bit userspace.\n" - "If you were targeting native_posix, target native_posix_64 instead.\n" + "If you were targeting native_sim, target native_sim/native/64 instead.\n" "Otherwise, be sure to define CONFIG_64BIT appropriately.\n" ) endif() From cbe76fbc7e0d522d2b9584c44472fb51ccf077b4 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:31:13 +0100 Subject: [PATCH 0752/2402] samples lvgl/accelerometer_chart: Use hwmv2 native targets For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- .../lvgl/accelerometer_chart/boards/native_posix_64.conf | 1 - .../lvgl/accelerometer_chart/boards/native_posix_64.overlay | 1 - .../modules/lvgl/accelerometer_chart/boards/native_sim_64.conf | 1 - .../lvgl/accelerometer_chart/boards/native_sim_64.overlay | 1 - samples/modules/lvgl/accelerometer_chart/sample.yaml | 2 +- 5 files changed, 1 insertion(+), 5 deletions(-) delete mode 100644 samples/modules/lvgl/accelerometer_chart/boards/native_posix_64.conf delete mode 100644 samples/modules/lvgl/accelerometer_chart/boards/native_posix_64.overlay delete mode 100644 samples/modules/lvgl/accelerometer_chart/boards/native_sim_64.conf delete mode 100644 samples/modules/lvgl/accelerometer_chart/boards/native_sim_64.overlay diff --git a/samples/modules/lvgl/accelerometer_chart/boards/native_posix_64.conf b/samples/modules/lvgl/accelerometer_chart/boards/native_posix_64.conf deleted file mode 100644 index e01c80e9dfa..00000000000 --- a/samples/modules/lvgl/accelerometer_chart/boards/native_posix_64.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_BMI160_TRIGGER_NONE=y diff --git a/samples/modules/lvgl/accelerometer_chart/boards/native_posix_64.overlay b/samples/modules/lvgl/accelerometer_chart/boards/native_posix_64.overlay deleted file mode 100644 index 2b055bf3de6..00000000000 --- a/samples/modules/lvgl/accelerometer_chart/boards/native_posix_64.overlay +++ /dev/null @@ -1 +0,0 @@ -#include "native_posix.overlay" diff --git a/samples/modules/lvgl/accelerometer_chart/boards/native_sim_64.conf b/samples/modules/lvgl/accelerometer_chart/boards/native_sim_64.conf deleted file mode 100644 index e01c80e9dfa..00000000000 --- a/samples/modules/lvgl/accelerometer_chart/boards/native_sim_64.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_BMI160_TRIGGER_NONE=y diff --git a/samples/modules/lvgl/accelerometer_chart/boards/native_sim_64.overlay b/samples/modules/lvgl/accelerometer_chart/boards/native_sim_64.overlay deleted file mode 100644 index 6a3daca3241..00000000000 --- a/samples/modules/lvgl/accelerometer_chart/boards/native_sim_64.overlay +++ /dev/null @@ -1 +0,0 @@ -#include "native_sim.overlay" diff --git a/samples/modules/lvgl/accelerometer_chart/sample.yaml b/samples/modules/lvgl/accelerometer_chart/sample.yaml index 943a242d00c..4561a127b93 100644 --- a/samples/modules/lvgl/accelerometer_chart/sample.yaml +++ b/samples/modules/lvgl/accelerometer_chart/sample.yaml @@ -15,4 +15,4 @@ tests: modules: - lvgl integration_platforms: - - native_sim_64 + - native_sim/native/64 From b08a007c28e90a49c227f16901c33b9649adfe79 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:34:45 +0100 Subject: [PATCH 0753/2402] samples lvgl/demos: Use hwmv2 native targets For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- samples/modules/lvgl/demos/README.rst | 2 +- samples/modules/lvgl/demos/boards/native_posix_64.overlay | 6 ------ .../{native_posix_64.conf => native_posix_native_64.conf} | 0 samples/modules/lvgl/demos/boards/native_sim_64.overlay | 6 ------ .../{native_sim_64.conf => native_sim_native_64.conf} | 0 5 files changed, 1 insertion(+), 13 deletions(-) delete mode 100644 samples/modules/lvgl/demos/boards/native_posix_64.overlay rename samples/modules/lvgl/demos/boards/{native_posix_64.conf => native_posix_native_64.conf} (100%) delete mode 100644 samples/modules/lvgl/demos/boards/native_sim_64.overlay rename samples/modules/lvgl/demos/boards/{native_sim_64.conf => native_sim_native_64.conf} (100%) diff --git a/samples/modules/lvgl/demos/README.rst b/samples/modules/lvgl/demos/README.rst index fe8f1bf7789..f835cc3f4a2 100644 --- a/samples/modules/lvgl/demos/README.rst +++ b/samples/modules/lvgl/demos/README.rst @@ -73,7 +73,7 @@ These demos can be built for simulated display environment as follows: :compact: Alternatively, if building from a 64-bit host machine, the previous target -board argument may also be replaced by ``native_sim_64``. +board argument may also be replaced by ``native_sim/native/64``. References ********** diff --git a/samples/modules/lvgl/demos/boards/native_posix_64.overlay b/samples/modules/lvgl/demos/boards/native_posix_64.overlay deleted file mode 100644 index ab50aa66f82..00000000000 --- a/samples/modules/lvgl/demos/boards/native_posix_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2023, Fabian Blatz - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_posix.overlay" diff --git a/samples/modules/lvgl/demos/boards/native_posix_64.conf b/samples/modules/lvgl/demos/boards/native_posix_native_64.conf similarity index 100% rename from samples/modules/lvgl/demos/boards/native_posix_64.conf rename to samples/modules/lvgl/demos/boards/native_posix_native_64.conf diff --git a/samples/modules/lvgl/demos/boards/native_sim_64.overlay b/samples/modules/lvgl/demos/boards/native_sim_64.overlay deleted file mode 100644 index 47fdc4be34c..00000000000 --- a/samples/modules/lvgl/demos/boards/native_sim_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2023, Fabian Blatz - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_sim.overlay" diff --git a/samples/modules/lvgl/demos/boards/native_sim_64.conf b/samples/modules/lvgl/demos/boards/native_sim_native_64.conf similarity index 100% rename from samples/modules/lvgl/demos/boards/native_sim_64.conf rename to samples/modules/lvgl/demos/boards/native_sim_native_64.conf From dda9ab949b06c1648f0a3ed7b2b77a2ccc726075 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:36:27 +0100 Subject: [PATCH 0754/2402] samples/drivers: Use hwmv2 native targets For the 64 bit targets, change identifiers to the new hwmv2 ones. Signed-off-by: Alberto Escolar Piedras --- samples/drivers/display/sample.yaml | 4 ++-- samples/drivers/eeprom/sample.yaml | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/samples/drivers/display/sample.yaml b/samples/drivers/display/sample.yaml index 39b56903b92..c6188d37d14 100644 --- a/samples/drivers/display/sample.yaml +++ b/samples/drivers/display/sample.yaml @@ -104,8 +104,8 @@ tests: sample.display.sdl: build_only: true platform_allow: - - native_posix_64 - - native_sim_64 + - native_posix/native/64 + - native_sim/native/64 tags: display sample.display.mipi_dbi: platform_allow: diff --git a/samples/drivers/eeprom/sample.yaml b/samples/drivers/eeprom/sample.yaml index 1c592eb8781..95fb7f88418 100644 --- a/samples/drivers/eeprom/sample.yaml +++ b/samples/drivers/eeprom/sample.yaml @@ -7,11 +7,11 @@ tests: platform_allow: - gd32f450i_eval - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - - native_sim_64 + - native_sim/native/64 harness: console harness_config: type: one_line From 1b25efda6cd4644523ad160465329f620154ce65 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:38:21 +0100 Subject: [PATCH 0755/2402] samples/net/gptp: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- samples/net/gptp/boards/native_posix_64.conf | 8 -------- samples/net/gptp/boards/native_sim_64.conf | 8 -------- samples/net/gptp/sample.yaml | 4 ++-- 3 files changed, 2 insertions(+), 18 deletions(-) delete mode 100644 samples/net/gptp/boards/native_posix_64.conf delete mode 100644 samples/net/gptp/boards/native_sim_64.conf diff --git a/samples/net/gptp/boards/native_posix_64.conf b/samples/net/gptp/boards/native_posix_64.conf deleted file mode 100644 index c514520186c..00000000000 --- a/samples/net/gptp/boards/native_posix_64.conf +++ /dev/null @@ -1,8 +0,0 @@ -# Settings for native_posix ethernet driver -CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK=y - -#CONFIG_ETH_NATIVE_POSIX_RANDOM_MAC=y -CONFIG_ETH_NATIVE_POSIX_MAC_ADDR="00:00:5e:00:53:2a" - -# Assume 1 ms accuracy for native_posix simulated clock -CONFIG_NET_GPTP_CLOCK_ACCURACY_1MS=y diff --git a/samples/net/gptp/boards/native_sim_64.conf b/samples/net/gptp/boards/native_sim_64.conf deleted file mode 100644 index c514520186c..00000000000 --- a/samples/net/gptp/boards/native_sim_64.conf +++ /dev/null @@ -1,8 +0,0 @@ -# Settings for native_posix ethernet driver -CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK=y - -#CONFIG_ETH_NATIVE_POSIX_RANDOM_MAC=y -CONFIG_ETH_NATIVE_POSIX_MAC_ADDR="00:00:5e:00:53:2a" - -# Assume 1 ms accuracy for native_posix simulated clock -CONFIG_NET_GPTP_CLOCK_ACCURACY_1MS=y diff --git a/samples/net/gptp/sample.yaml b/samples/net/gptp/sample.yaml index ba77d2eaaba..93d1d9aa498 100644 --- a/samples/net/gptp/sample.yaml +++ b/samples/net/gptp/sample.yaml @@ -12,9 +12,9 @@ tests: - frdm_k64f - sam_e70_xplained/same70q21 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - nucleo_f767zi - nucleo_h743zi - nucleo_h745zi_q/stm32h745xx/m7 From 7ea52466ee2b71b60fd3f8182d00526f9a6beb96 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:40:27 +0100 Subject: [PATCH 0756/2402] samples/net/gptp: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- samples/net/mqtt_sn_publisher/README.rst | 2 +- samples/net/mqtt_sn_publisher/boards/native_posix_64.conf | 6 ------ samples/net/mqtt_sn_publisher/boards/native_sim_64.conf | 1 - samples/net/mqtt_sn_publisher/sample.yaml | 2 +- 4 files changed, 2 insertions(+), 9 deletions(-) delete mode 100644 samples/net/mqtt_sn_publisher/boards/native_posix_64.conf delete mode 100644 samples/net/mqtt_sn_publisher/boards/native_sim_64.conf diff --git a/samples/net/mqtt_sn_publisher/README.rst b/samples/net/mqtt_sn_publisher/README.rst index 48b8dab5dec..6701ab7e777 100644 --- a/samples/net/mqtt_sn_publisher/README.rst +++ b/samples/net/mqtt_sn_publisher/README.rst @@ -67,7 +67,7 @@ Then, locate your zephyr directory and type: .. zephyr-app-commands:: :zephyr-app: samples/net/mqtt_sn_publisher - :board: native_sim_64 + :board: native_sim/native/64 :goals: run :compact: diff --git a/samples/net/mqtt_sn_publisher/boards/native_posix_64.conf b/samples/net/mqtt_sn_publisher/boards/native_posix_64.conf deleted file mode 100644 index 357bbc8f5df..00000000000 --- a/samples/net/mqtt_sn_publisher/boards/native_posix_64.conf +++ /dev/null @@ -1,6 +0,0 @@ -# Configuration options for MQTT-SN sample - -# Copyright (c) 2022 René Beckmann -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y diff --git a/samples/net/mqtt_sn_publisher/boards/native_sim_64.conf b/samples/net/mqtt_sn_publisher/boards/native_sim_64.conf deleted file mode 100644 index 0843e94acbd..00000000000 --- a/samples/net/mqtt_sn_publisher/boards/native_sim_64.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME=y diff --git a/samples/net/mqtt_sn_publisher/sample.yaml b/samples/net/mqtt_sn_publisher/sample.yaml index ca11e3e96f3..1f307b2fd7a 100644 --- a/samples/net/mqtt_sn_publisher/sample.yaml +++ b/samples/net/mqtt_sn_publisher/sample.yaml @@ -13,6 +13,6 @@ tests: - qemu_x86 - pinnacle_100_dvk - mg100 - - native_sim_64 + - native_sim/native/64 integration_platforms: - qemu_x86 From 86d71c7d835dc504fb06d2473007c2ba54da1c64 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:42:14 +0100 Subject: [PATCH 0757/2402] samples/net/sockets/*: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- samples/net/sockets/coap_server/boards/native_posix_64.conf | 3 --- samples/net/sockets/coap_server/boards/native_sim_64.conf | 4 ---- samples/net/sockets/echo_service/sample.yaml | 2 +- samples/net/sockets/packet/sample.yaml | 4 ++-- samples/net/sockets/txtime/sample.yaml | 4 ++-- 5 files changed, 5 insertions(+), 12 deletions(-) delete mode 100644 samples/net/sockets/coap_server/boards/native_posix_64.conf delete mode 100644 samples/net/sockets/coap_server/boards/native_sim_64.conf diff --git a/samples/net/sockets/coap_server/boards/native_posix_64.conf b/samples/net/sockets/coap_server/boards/native_posix_64.conf deleted file mode 100644 index b8f2d57be74..00000000000 --- a/samples/net/sockets/coap_server/boards/native_posix_64.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_NET_L2_ETHERNET=y -CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y -CONFIG_NATIVE_UART_0_ON_STDINOUT=y diff --git a/samples/net/sockets/coap_server/boards/native_sim_64.conf b/samples/net/sockets/coap_server/boards/native_sim_64.conf deleted file mode 100644 index ac091ebe5db..00000000000 --- a/samples/net/sockets/coap_server/boards/native_sim_64.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_NET_L2_ETHERNET=y -CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME=y -CONFIG_NATIVE_UART_0_ON_STDINOUT=y -CONFIG_PICOLIBC=y diff --git a/samples/net/sockets/echo_service/sample.yaml b/samples/net/sockets/echo_service/sample.yaml index aee10686c0f..5feb3cc826c 100644 --- a/samples/net/sockets/echo_service/sample.yaml +++ b/samples/net/sockets/echo_service/sample.yaml @@ -8,7 +8,7 @@ common: # eventfd does not work properly with native_posix so exclude it here platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 tests: sample.net.sockets.service.echo: tags: diff --git a/samples/net/sockets/packet/sample.yaml b/samples/net/sockets/packet/sample.yaml index d02c03c7d68..dc816ac52e8 100644 --- a/samples/net/sockets/packet/sample.yaml +++ b/samples/net/sockets/packet/sample.yaml @@ -6,9 +6,9 @@ tests: harness: net platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tags: diff --git a/samples/net/sockets/txtime/sample.yaml b/samples/net/sockets/txtime/sample.yaml index 189f6901bfc..feb099bd63b 100644 --- a/samples/net/sockets/txtime/sample.yaml +++ b/samples/net/sockets/txtime/sample.yaml @@ -4,9 +4,9 @@ common: # We can only run this in platforms that support PTP clock and TXTIME platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - qemu_x86 - qemu_x86_64 integration_platforms: From ada74bf6318ceb9f69606d8006676ae7d95cd3c8 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:44:41 +0100 Subject: [PATCH 0758/2402] samples/subsys/display/lvgl: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- samples/subsys/display/lvgl/README.rst | 2 +- samples/subsys/display/lvgl/boards/native_posix_64.conf | 3 --- samples/subsys/display/lvgl/boards/native_posix_64.overlay | 6 ------ samples/subsys/display/lvgl/boards/native_sim_64.conf | 3 --- samples/subsys/display/lvgl/boards/native_sim_64.overlay | 6 ------ samples/subsys/display/lvgl/sample.yaml | 2 +- 6 files changed, 2 insertions(+), 20 deletions(-) delete mode 100644 samples/subsys/display/lvgl/boards/native_posix_64.conf delete mode 100644 samples/subsys/display/lvgl/boards/native_posix_64.overlay delete mode 100644 samples/subsys/display/lvgl/boards/native_sim_64.conf delete mode 100644 samples/subsys/display/lvgl/boards/native_sim_64.overlay diff --git a/samples/subsys/display/lvgl/README.rst b/samples/subsys/display/lvgl/README.rst index 34b58f4c866..a4e2f401bda 100644 --- a/samples/subsys/display/lvgl/README.rst +++ b/samples/subsys/display/lvgl/README.rst @@ -80,7 +80,7 @@ Example building for :ref:`native_sim `: :goals: build run Alternatively, if building from a 64-bit host machine, the previous target -board argument may also be replaced by ``native_sim_64``. +board argument may also be replaced by ``native_sim/native/64``. References ********** diff --git a/samples/subsys/display/lvgl/boards/native_posix_64.conf b/samples/subsys/display/lvgl/boards/native_posix_64.conf deleted file mode 100644 index e5f19abc888..00000000000 --- a/samples/subsys/display/lvgl/boards/native_posix_64.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_LV_COLOR_DEPTH_32=y -CONFIG_GPIO=y -CONFIG_INPUT=y diff --git a/samples/subsys/display/lvgl/boards/native_posix_64.overlay b/samples/subsys/display/lvgl/boards/native_posix_64.overlay deleted file mode 100644 index 060625d230c..00000000000 --- a/samples/subsys/display/lvgl/boards/native_posix_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2022, Basalte bv - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_posix.overlay" diff --git a/samples/subsys/display/lvgl/boards/native_sim_64.conf b/samples/subsys/display/lvgl/boards/native_sim_64.conf deleted file mode 100644 index e5f19abc888..00000000000 --- a/samples/subsys/display/lvgl/boards/native_sim_64.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_LV_COLOR_DEPTH_32=y -CONFIG_GPIO=y -CONFIG_INPUT=y diff --git a/samples/subsys/display/lvgl/boards/native_sim_64.overlay b/samples/subsys/display/lvgl/boards/native_sim_64.overlay deleted file mode 100644 index 5308ee48680..00000000000 --- a/samples/subsys/display/lvgl/boards/native_sim_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2023, Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_sim.overlay" diff --git a/samples/subsys/display/lvgl/sample.yaml b/samples/subsys/display/lvgl/sample.yaml index 7d8eb7a3b1b..c0ab07d48e8 100644 --- a/samples/subsys/display/lvgl/sample.yaml +++ b/samples/subsys/display/lvgl/sample.yaml @@ -19,7 +19,7 @@ tests: modules: - lvgl integration_platforms: - - native_sim_64 + - native_sim/native/64 sample.display.lvgl.rk055hdmipi4m: # This sample is intended to test the RT1170 and RT595, which require # a display shield to work with LVGL From 1d96cab18da8b2946ce2016cdbe9668991aa6101 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:46:12 +0100 Subject: [PATCH 0759/2402] samples/subsys/settings: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- samples/subsys/settings/boards/native_posix_64.conf | 5 ----- samples/subsys/settings/boards/native_posix_64.overlay | 1 - samples/subsys/settings/boards/native_sim_64.conf | 5 ----- samples/subsys/settings/boards/native_sim_64.overlay | 1 - samples/subsys/settings/sample.yaml | 4 ++-- 5 files changed, 2 insertions(+), 14 deletions(-) delete mode 100644 samples/subsys/settings/boards/native_posix_64.conf delete mode 100644 samples/subsys/settings/boards/native_posix_64.overlay delete mode 100644 samples/subsys/settings/boards/native_sim_64.conf delete mode 100644 samples/subsys/settings/boards/native_sim_64.overlay diff --git a/samples/subsys/settings/boards/native_posix_64.conf b/samples/subsys/settings/boards/native_posix_64.conf deleted file mode 100644 index 21877f886f3..00000000000 --- a/samples/subsys/settings/boards/native_posix_64.conf +++ /dev/null @@ -1,5 +0,0 @@ -# Enable the LittleFS file system. -CONFIG_FILE_SYSTEM=y -CONFIG_FILE_SYSTEM_LITTLEFS=y -CONFIG_SETTINGS_FILE=y -CONFIG_SETTINGS_FILE_PATH="/ff/settings/run" diff --git a/samples/subsys/settings/boards/native_posix_64.overlay b/samples/subsys/settings/boards/native_posix_64.overlay deleted file mode 100644 index 6a3daca3241..00000000000 --- a/samples/subsys/settings/boards/native_posix_64.overlay +++ /dev/null @@ -1 +0,0 @@ -#include "native_sim.overlay" diff --git a/samples/subsys/settings/boards/native_sim_64.conf b/samples/subsys/settings/boards/native_sim_64.conf deleted file mode 100644 index 21877f886f3..00000000000 --- a/samples/subsys/settings/boards/native_sim_64.conf +++ /dev/null @@ -1,5 +0,0 @@ -# Enable the LittleFS file system. -CONFIG_FILE_SYSTEM=y -CONFIG_FILE_SYSTEM_LITTLEFS=y -CONFIG_SETTINGS_FILE=y -CONFIG_SETTINGS_FILE_PATH="/ff/settings/run" diff --git a/samples/subsys/settings/boards/native_sim_64.overlay b/samples/subsys/settings/boards/native_sim_64.overlay deleted file mode 100644 index 6a3daca3241..00000000000 --- a/samples/subsys/settings/boards/native_sim_64.overlay +++ /dev/null @@ -1 +0,0 @@ -#include "native_sim.overlay" diff --git a/samples/subsys/settings/sample.yaml b/samples/subsys/settings/sample.yaml index 2cd51d1405d..101c290bb96 100644 --- a/samples/subsys/settings/sample.yaml +++ b/samples/subsys/settings/sample.yaml @@ -8,9 +8,9 @@ tests: platform_allow: - qemu_x86 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - mr_canhubk3 integration_platforms: - native_sim From 272495a358e3ae314f708d615e904aacf3f41292 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:49:04 +0100 Subject: [PATCH 0760/2402] samples/subsys/zbus/uart_bridge: Remove redundant overlays Remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- samples/subsys/zbus/uart_bridge/boards/native_posix_64.conf | 1 - samples/subsys/zbus/uart_bridge/boards/native_sim_64.conf | 1 - 2 files changed, 2 deletions(-) delete mode 100644 samples/subsys/zbus/uart_bridge/boards/native_posix_64.conf delete mode 100644 samples/subsys/zbus/uart_bridge/boards/native_sim_64.conf diff --git a/samples/subsys/zbus/uart_bridge/boards/native_posix_64.conf b/samples/subsys/zbus/uart_bridge/boards/native_posix_64.conf deleted file mode 100644 index b552360756c..00000000000 --- a/samples/subsys/zbus/uart_bridge/boards/native_posix_64.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE=y diff --git a/samples/subsys/zbus/uart_bridge/boards/native_sim_64.conf b/samples/subsys/zbus/uart_bridge/boards/native_sim_64.conf deleted file mode 100644 index b552360756c..00000000000 --- a/samples/subsys/zbus/uart_bridge/boards/native_sim_64.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE=y From 442a3e2c5c3cc6933ff13979e9b7295c2a8e771b Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:53:26 +0100 Subject: [PATCH 0761/2402] samples/net several: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- samples/net/ipv4_autoconf/sample.yaml | 4 ++-- samples/net/lldp/sample.yaml | 4 ++-- samples/net/zperf/boards/native_posix_64.conf | 1 - samples/net/zperf/sample.yaml | 2 +- 4 files changed, 5 insertions(+), 6 deletions(-) delete mode 100644 samples/net/zperf/boards/native_posix_64.conf diff --git a/samples/net/ipv4_autoconf/sample.yaml b/samples/net/ipv4_autoconf/sample.yaml index 07260fee0ad..0322a31ad75 100644 --- a/samples/net/ipv4_autoconf/sample.yaml +++ b/samples/net/ipv4_autoconf/sample.yaml @@ -6,9 +6,9 @@ common: platform_allow: - qemu_x86 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim sample: diff --git a/samples/net/lldp/sample.yaml b/samples/net/lldp/sample.yaml index 991133a8d26..ee465be7883 100644 --- a/samples/net/lldp/sample.yaml +++ b/samples/net/lldp/sample.yaml @@ -10,9 +10,9 @@ tests: sample.net.lldp: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim depends_on: eth diff --git a/samples/net/zperf/boards/native_posix_64.conf b/samples/net/zperf/boards/native_posix_64.conf deleted file mode 100644 index eb56d825c96..00000000000 --- a/samples/net/zperf/boards/native_posix_64.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y diff --git a/samples/net/zperf/sample.yaml b/samples/net/zperf/sample.yaml index b3aa90f569f..ece4f52cafb 100644 --- a/samples/net/zperf/sample.yaml +++ b/samples/net/zperf/sample.yaml @@ -5,7 +5,7 @@ common: # TODO: Does not work properly with native_posix, need more TLC platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 - sam_e70_xplained/same70q21 min_ram: 64 sample: From cb2016c2a0512f2020b00f72365f9293af65a748 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:54:46 +0100 Subject: [PATCH 0762/2402] samples/posix: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- samples/posix/env/sample.yaml | 2 +- samples/posix/uname/sample.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/samples/posix/env/sample.yaml b/samples/posix/env/sample.yaml index cf9b166ae7f..c276b6b55f1 100644 --- a/samples/posix/env/sample.yaml +++ b/samples/posix/env/sample.yaml @@ -5,7 +5,7 @@ common: tags: posix env platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 integration_platforms: - qemu_riscv32 harness: console diff --git a/samples/posix/uname/sample.yaml b/samples/posix/uname/sample.yaml index f4b8b82abac..6b0b0817c16 100644 --- a/samples/posix/uname/sample.yaml +++ b/samples/posix/uname/sample.yaml @@ -5,7 +5,7 @@ common: tags: posix platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 integration_platforms: - native_sim - qemu_riscv64 From af047e18913f20438b2bf4867c768068f48921ef Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:55:19 +0100 Subject: [PATCH 0763/2402] samples/subsys: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. Signed-off-by: Alberto Escolar Piedras --- samples/subsys/canbus/isotp/sample.yaml | 4 ++-- samples/subsys/debug/fuzz/README.rst | 4 ++-- samples/subsys/debug/fuzz/sample.yaml | 2 +- samples/subsys/usb/hid/sample.yaml | 4 ++-- samples/subsys/usb/testusb/sample.yaml | 2 +- samples/subsys/usb/webusb/sample.yaml | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/samples/subsys/canbus/isotp/sample.yaml b/samples/subsys/canbus/isotp/sample.yaml index 0036552b67b..67d3901a23b 100644 --- a/samples/subsys/canbus/isotp/sample.yaml +++ b/samples/subsys/canbus/isotp/sample.yaml @@ -24,9 +24,9 @@ tests: - CONFIG_SAMPLE_CAN_FD_MODE=y platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 harness: console harness_config: type: one_line diff --git a/samples/subsys/debug/fuzz/README.rst b/samples/subsys/debug/fuzz/README.rst index 90ff197c86a..126594436a3 100644 --- a/samples/subsys/debug/fuzz/README.rst +++ b/samples/subsys/debug/fuzz/README.rst @@ -24,7 +24,7 @@ toolchain is installed in your host environment, and build with: Thread model: posix InstalledDir: /usr/bin $ export ZEPHYR_TOOLCHAIN_VARIANT=llvm - $ west build -t run -b native_posix_64 samples/subsys/debug/fuzz + $ west build -t run -b native_posix/native/64 samples/subsys/debug/fuzz Over 10-20 seconds or so (runtimes can be quite variable) you will see it discover and recurse deeper into the test's deliberately @@ -43,7 +43,7 @@ Example output: INFO: Loaded 1 PC tables (2112 PCs): 2112 [0x55cbe336f498,0x55cbe3377898), INFO: -max_len is not provided; libFuzzer will not generate inputs larger than 4096 bytes *** Booting Zephyr OS build zephyr-v3.1.0-3976-g806034e02865 *** - Hello World! native_posix_64 + Hello World! native_posix/native/64 INFO: A corpus is not provided, starting from an empty corpus #2 INITED cov: 101 ft: 102 corp: 1/1b exec/s: 0 rss: 30Mb # diff --git a/samples/subsys/debug/fuzz/sample.yaml b/samples/subsys/debug/fuzz/sample.yaml index 569cea91d66..3b1dc0b92ec 100644 --- a/samples/subsys/debug/fuzz/sample.yaml +++ b/samples/subsys/debug/fuzz/sample.yaml @@ -4,7 +4,7 @@ sample: tests: sample.debug.fuzz: toolchain_allow: llvm - platform_allow: native_posix_64 + platform_allow: native_posix/native/64 harness: console harness_config: type: one_line diff --git a/samples/subsys/usb/hid/sample.yaml b/samples/subsys/usb/hid/sample.yaml index ba6cf22a2d4..69c874bb238 100644 --- a/samples/subsys/usb/hid/sample.yaml +++ b/samples/subsys/usb/hid/sample.yaml @@ -16,9 +16,9 @@ tests: tags: usb platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 build_only: true integration_platforms: - native_sim diff --git a/samples/subsys/usb/testusb/sample.yaml b/samples/subsys/usb/testusb/sample.yaml index 5109af2855a..c251eaded73 100644 --- a/samples/subsys/usb/testusb/sample.yaml +++ b/samples/subsys/usb/testusb/sample.yaml @@ -6,5 +6,5 @@ tests: tags: usb platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 harness: button diff --git a/samples/subsys/usb/webusb/sample.yaml b/samples/subsys/usb/webusb/sample.yaml index d3bc602a868..c68c0366eaa 100644 --- a/samples/subsys/usb/webusb/sample.yaml +++ b/samples/subsys/usb/webusb/sample.yaml @@ -6,5 +6,5 @@ tests: tags: usb platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 harness: TBD From 05f1b2c2078e715e36b855d560ea0aa96ab4ffa3 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:56:10 +0100 Subject: [PATCH 0764/2402] samples misc: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. Signed-off-by: Alberto Escolar Piedras --- samples/basic/hash_map/Kconfig | 2 +- samples/modules/nanopb/sample.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/samples/basic/hash_map/Kconfig b/samples/basic/hash_map/Kconfig index a721e93b2e2..36ea3306392 100644 --- a/samples/basic/hash_map/Kconfig +++ b/samples/basic/hash_map/Kconfig @@ -18,7 +18,7 @@ config TEST_LIB_HASH_MAP_MAX_ENTRIES CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE - For native_posix_64, the number of entries can be configured + For native_sim, the number of entries can be configured independently of the arena size since the native libc is used. config TEST_LIB_HASH_MAP_DURATION_S diff --git a/samples/modules/nanopb/sample.yaml b/samples/modules/nanopb/sample.yaml index eb990848d18..06511ab8e59 100644 --- a/samples/modules/nanopb/sample.yaml +++ b/samples/modules/nanopb/sample.yaml @@ -16,4 +16,4 @@ tests: - nanopb integration_platforms: - native_sim - - native_sim_64 + - native_sim/native/64 From 68975aa837cf7c5514465c608a46013a699b2baf Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 14:58:03 +0100 Subject: [PATCH 0765/2402] tests/bluetooth: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- tests/bluetooth/addr/testcase.yaml | 4 ++-- tests/bluetooth/bluetooth/testcase.yaml | 4 ++-- tests/bluetooth/bt_crypto/testcase.yaml | 4 ++-- tests/bluetooth/bt_crypto_ccm/testcase.yaml | 4 ++-- tests/bluetooth/gatt/testcase.yaml | 4 ++-- tests/bluetooth/hci_prop_evt/testcase.yaml | 4 ++-- tests/bluetooth/host_long_adv_recv/testcase.yaml | 4 ++-- tests/bluetooth/l2cap/testcase.yaml | 4 ++-- tests/bluetooth/shell/boards/native_sim_64.conf | 16 ---------------- tests/bluetooth/shell/testcase.yaml | 12 ++++++------ tests/bluetooth/uuid/testcase.yaml | 4 ++-- 11 files changed, 24 insertions(+), 40 deletions(-) delete mode 100644 tests/bluetooth/shell/boards/native_sim_64.conf diff --git a/tests/bluetooth/addr/testcase.yaml b/tests/bluetooth/addr/testcase.yaml index 736d4b5a2ba..c4746b2da29 100644 --- a/tests/bluetooth/addr/testcase.yaml +++ b/tests/bluetooth/addr/testcase.yaml @@ -2,9 +2,9 @@ tests: bluetooth.addr: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - qemu_x86 - qemu_cortex_m3 tags: diff --git a/tests/bluetooth/bluetooth/testcase.yaml b/tests/bluetooth/bluetooth/testcase.yaml index 7f8ac610821..a7dccced9ea 100644 --- a/tests/bluetooth/bluetooth/testcase.yaml +++ b/tests/bluetooth/bluetooth/testcase.yaml @@ -4,9 +4,9 @@ tests: - qemu_x86 - qemu_cortex_m3 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - qemu_x86 tags: bluetooth diff --git a/tests/bluetooth/bt_crypto/testcase.yaml b/tests/bluetooth/bt_crypto/testcase.yaml index 5de0839b29e..e486846175e 100644 --- a/tests/bluetooth/bt_crypto/testcase.yaml +++ b/tests/bluetooth/bt_crypto/testcase.yaml @@ -2,9 +2,9 @@ tests: bluetooth.bt_crypto: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - qemu_x86 - qemu_cortex_m3 integration_platforms: diff --git a/tests/bluetooth/bt_crypto_ccm/testcase.yaml b/tests/bluetooth/bt_crypto_ccm/testcase.yaml index b1827e56aff..43c35f6a757 100644 --- a/tests/bluetooth/bt_crypto_ccm/testcase.yaml +++ b/tests/bluetooth/bt_crypto_ccm/testcase.yaml @@ -2,9 +2,9 @@ tests: bluetooth.bt_crypto_ccm: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tags: bluetooth diff --git a/tests/bluetooth/gatt/testcase.yaml b/tests/bluetooth/gatt/testcase.yaml index 9a02af34de0..5e1fa97a4b9 100644 --- a/tests/bluetooth/gatt/testcase.yaml +++ b/tests/bluetooth/gatt/testcase.yaml @@ -2,9 +2,9 @@ tests: bluetooth.gatt: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - qemu_x86 - qemu_cortex_m3 integration_platforms: diff --git a/tests/bluetooth/hci_prop_evt/testcase.yaml b/tests/bluetooth/hci_prop_evt/testcase.yaml index 6f41a722e80..dde90adf9bc 100644 --- a/tests/bluetooth/hci_prop_evt/testcase.yaml +++ b/tests/bluetooth/hci_prop_evt/testcase.yaml @@ -4,9 +4,9 @@ tests: - qemu_x86 - qemu_cortex_m3 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tags: diff --git a/tests/bluetooth/host_long_adv_recv/testcase.yaml b/tests/bluetooth/host_long_adv_recv/testcase.yaml index a94b021d1ef..7957d03a796 100644 --- a/tests/bluetooth/host_long_adv_recv/testcase.yaml +++ b/tests/bluetooth/host_long_adv_recv/testcase.yaml @@ -2,9 +2,9 @@ tests: bluetooth.host_long_adv_recv: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tags: diff --git a/tests/bluetooth/l2cap/testcase.yaml b/tests/bluetooth/l2cap/testcase.yaml index 18a2fc52858..8996672c866 100644 --- a/tests/bluetooth/l2cap/testcase.yaml +++ b/tests/bluetooth/l2cap/testcase.yaml @@ -2,9 +2,9 @@ tests: bluetooth.l2cap: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - qemu_x86 - qemu_cortex_m3 integration_platforms: diff --git a/tests/bluetooth/shell/boards/native_sim_64.conf b/tests/bluetooth/shell/boards/native_sim_64.conf deleted file mode 100644 index a2ab2f4e87a..00000000000 --- a/tests/bluetooth/shell/boards/native_sim_64.conf +++ /dev/null @@ -1,16 +0,0 @@ -CONFIG_NO_OPTIMIZATIONS=y -# Allows for copying larger amount of data into the shell -CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=4096 - -# For native posix k_sleep is used in the data path as well as for shell input -# detection, hence data processing is at least two ticks per packet. To support -# 5ms ISO interval bidirectional data the system shall never stall for more -# than 1.5 ms in average. -CONFIG_SYS_CLOCK_TICKS_PER_SEC=500 - -# For LC3 the following configs are needed -CONFIG_FPU=y -CONFIG_LIBLC3=y -# The LC3 codec uses a large amount of stack. This app runs the codec in the work-queue, hence -# inctease stack size for that thread. -CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096 diff --git a/tests/bluetooth/shell/testcase.yaml b/tests/bluetooth/shell/testcase.yaml index 5afef25d98a..7ce46d768fe 100644 --- a/tests/bluetooth/shell/testcase.yaml +++ b/tests/bluetooth/shell/testcase.yaml @@ -12,9 +12,9 @@ tests: platform_allow: - qemu_x86 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 @@ -36,9 +36,9 @@ tests: depends_on: usb_device platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - nrf52840dk/nrf52840 integration_platforms: - native_sim @@ -54,9 +54,9 @@ tests: - qemu_cortex_m3 - qemu_x86 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim platform_exclude: nrf52dk/nrf52810 diff --git a/tests/bluetooth/uuid/testcase.yaml b/tests/bluetooth/uuid/testcase.yaml index d7ad13764d1..20e43e29a27 100644 --- a/tests/bluetooth/uuid/testcase.yaml +++ b/tests/bluetooth/uuid/testcase.yaml @@ -2,9 +2,9 @@ tests: bluetooth.uuid: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - qemu_x86 - qemu_cortex_m3 integration_platforms: From 844f75a78cef1210ac778870af7ecc575d4b01a1 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:01:03 +0100 Subject: [PATCH 0766/2402] tests/drivers/adc: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- tests/drivers/adc/adc_api/boards/native_posix_64.overlay | 6 ------ tests/drivers/adc/adc_api/boards/native_sim_64.overlay | 7 ------- tests/drivers/adc/adc_rescale/boards/native_sim_64.overlay | 6 ------ tests/drivers/adc/adc_rescale/testcase.yaml | 2 +- 4 files changed, 1 insertion(+), 20 deletions(-) delete mode 100644 tests/drivers/adc/adc_api/boards/native_posix_64.overlay delete mode 100644 tests/drivers/adc/adc_api/boards/native_sim_64.overlay delete mode 100644 tests/drivers/adc/adc_rescale/boards/native_sim_64.overlay diff --git a/tests/drivers/adc/adc_api/boards/native_posix_64.overlay b/tests/drivers/adc/adc_api/boards/native_posix_64.overlay deleted file mode 100644 index 705d229e000..00000000000 --- a/tests/drivers/adc/adc_api/boards/native_posix_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright 2021 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_posix.overlay" diff --git a/tests/drivers/adc/adc_api/boards/native_sim_64.overlay b/tests/drivers/adc/adc_api/boards/native_sim_64.overlay deleted file mode 100644 index 6b622000bdf..00000000000 --- a/tests/drivers/adc/adc_api/boards/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_posix.overlay" diff --git a/tests/drivers/adc/adc_rescale/boards/native_sim_64.overlay b/tests/drivers/adc/adc_rescale/boards/native_sim_64.overlay deleted file mode 100644 index 13b1a7899b9..00000000000 --- a/tests/drivers/adc/adc_rescale/boards/native_sim_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright 2023 The ChromiumOS Authors - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_sim.overlay" diff --git a/tests/drivers/adc/adc_rescale/testcase.yaml b/tests/drivers/adc/adc_rescale/testcase.yaml index a03f30895cc..f5fa6bfc711 100644 --- a/tests/drivers/adc/adc_rescale/testcase.yaml +++ b/tests/drivers/adc/adc_rescale/testcase.yaml @@ -5,4 +5,4 @@ tests: depends_on: adc platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 From 054de9f9c3c834a75f4a7f75128a37b58f8a57be Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:03:59 +0100 Subject: [PATCH 0767/2402] tests/drivers/build_all: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- tests/drivers/build_all/adc/boards/native_sim_64.overlay | 6 ------ tests/drivers/build_all/adc/testcase.yaml | 2 +- tests/drivers/build_all/can/boards/native_posix_64.overlay | 7 ------- tests/drivers/build_all/can/boards/native_sim_64.overlay | 7 ------- tests/drivers/build_all/can/testcase.yaml | 4 ++-- tests/drivers/build_all/ethernet/testcase.yaml | 2 +- tests/drivers/build_all/modem/testcase.yaml | 2 +- 7 files changed, 5 insertions(+), 25 deletions(-) delete mode 100644 tests/drivers/build_all/adc/boards/native_sim_64.overlay delete mode 100644 tests/drivers/build_all/can/boards/native_posix_64.overlay delete mode 100644 tests/drivers/build_all/can/boards/native_sim_64.overlay diff --git a/tests/drivers/build_all/adc/boards/native_sim_64.overlay b/tests/drivers/build_all/adc/boards/native_sim_64.overlay deleted file mode 100644 index 16e56822d5f..00000000000 --- a/tests/drivers/build_all/adc/boards/native_sim_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.overlay" diff --git a/tests/drivers/build_all/adc/testcase.yaml b/tests/drivers/build_all/adc/testcase.yaml index 9c4afb9cc0d..f0345bef853 100644 --- a/tests/drivers/build_all/adc/testcase.yaml +++ b/tests/drivers/build_all/adc/testcase.yaml @@ -8,7 +8,7 @@ tests: # will cover I2C, SPI, and emul based drivers platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 extra_args: "CONFIG_GPIO=y" drivers.adc.cc32xx.build: platform_allow: cc3220sf_launchxl diff --git a/tests/drivers/build_all/can/boards/native_posix_64.overlay b/tests/drivers/build_all/can/boards/native_posix_64.overlay deleted file mode 100644 index 6c218eaa9cc..00000000000 --- a/tests/drivers/build_all/can/boards/native_posix_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2023 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_posix.overlay" diff --git a/tests/drivers/build_all/can/boards/native_sim_64.overlay b/tests/drivers/build_all/can/boards/native_sim_64.overlay deleted file mode 100644 index 84e4247ccc8..00000000000 --- a/tests/drivers/build_all/can/boards/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2023 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.overlay" diff --git a/tests/drivers/build_all/can/testcase.yaml b/tests/drivers/build_all/can/testcase.yaml index bf38398ed4b..74b1e3ad845 100644 --- a/tests/drivers/build_all/can/testcase.yaml +++ b/tests/drivers/build_all/can/testcase.yaml @@ -22,6 +22,6 @@ tests: drivers.can.build_all.native_linux: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 diff --git a/tests/drivers/build_all/ethernet/testcase.yaml b/tests/drivers/build_all/ethernet/testcase.yaml index b62da48f165..623e1cb00ee 100644 --- a/tests/drivers/build_all/ethernet/testcase.yaml +++ b/tests/drivers/build_all/ethernet/testcase.yaml @@ -14,7 +14,7 @@ tests: - CONFIG_SPI=y platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 net.ethernet.build.stm32_ethernet: filter: dt_compat_enabled("st,stm32-ethernet") diff --git a/tests/drivers/build_all/modem/testcase.yaml b/tests/drivers/build_all/modem/testcase.yaml index 303e0ee44e8..c373bbbe477 100644 --- a/tests/drivers/build_all/modem/testcase.yaml +++ b/tests/drivers/build_all/modem/testcase.yaml @@ -2,7 +2,7 @@ common: build_only: true platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 - qemu_x86 - qemu_x86_64 From 42dbca31b4c8183ea47e3cfdbfafb2e2407ae32c Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:08:03 +0100 Subject: [PATCH 0768/2402] tests/drivers/dma: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- .../boards/native_posix_64.overlay | 12 ------------ ...ve_posix_64.conf => native_posix_native_64.conf} | 0 tests/drivers/dma/chan_blen_transfer/testcase.yaml | 2 +- .../boards/native_posix_64.overlay | 12 ------------ ...ve_posix_64.conf => native_posix_native_64.conf} | 0 tests/drivers/dma/chan_link_transfer/testcase.yaml | 4 ++-- .../loop_transfer/boards/native_posix_64.overlay | 12 ------------ ...ve_posix_64.conf => native_posix_native_64.conf} | 0 tests/drivers/dma/loop_transfer/testcase.yaml | 2 +- .../scatter_gather/boards/native_posix_64.overlay | 13 ------------- ...ve_posix_64.conf => native_posix_native_64.conf} | 0 tests/drivers/dma/scatter_gather/testcase.yaml | 4 ++-- 12 files changed, 6 insertions(+), 55 deletions(-) delete mode 100644 tests/drivers/dma/chan_blen_transfer/boards/native_posix_64.overlay rename tests/drivers/dma/chan_blen_transfer/boards/{native_posix_64.conf => native_posix_native_64.conf} (100%) delete mode 100644 tests/drivers/dma/chan_link_transfer/boards/native_posix_64.overlay rename tests/drivers/dma/chan_link_transfer/boards/{native_posix_64.conf => native_posix_native_64.conf} (100%) delete mode 100644 tests/drivers/dma/loop_transfer/boards/native_posix_64.overlay rename tests/drivers/dma/loop_transfer/boards/{native_posix_64.conf => native_posix_native_64.conf} (100%) delete mode 100644 tests/drivers/dma/scatter_gather/boards/native_posix_64.overlay rename tests/drivers/dma/scatter_gather/boards/{native_posix_64.conf => native_posix_native_64.conf} (100%) diff --git a/tests/drivers/dma/chan_blen_transfer/boards/native_posix_64.overlay b/tests/drivers/dma/chan_blen_transfer/boards/native_posix_64.overlay deleted file mode 100644 index 28f19ac0f0d..00000000000 --- a/tests/drivers/dma/chan_blen_transfer/boards/native_posix_64.overlay +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2023 Meta - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&dma { - dma-channels = <2>; - status = "okay"; -}; - -tst_dma0: &dma { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/native_posix_64.conf b/tests/drivers/dma/chan_blen_transfer/boards/native_posix_native_64.conf similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/native_posix_64.conf rename to tests/drivers/dma/chan_blen_transfer/boards/native_posix_native_64.conf diff --git a/tests/drivers/dma/chan_blen_transfer/testcase.yaml b/tests/drivers/dma/chan_blen_transfer/testcase.yaml index 22c62b9d50b..bbb6b2ca7eb 100644 --- a/tests/drivers/dma/chan_blen_transfer/testcase.yaml +++ b/tests/drivers/dma/chan_blen_transfer/testcase.yaml @@ -7,7 +7,7 @@ tests: - dma integration_platforms: - native_posix - - native_posix_64 + - native_posix/native/64 filter: dt_nodelabel_enabled("tst_dma0") drivers.dma.chan_blen_transfer.low_footprint: tags: diff --git a/tests/drivers/dma/chan_link_transfer/boards/native_posix_64.overlay b/tests/drivers/dma/chan_link_transfer/boards/native_posix_64.overlay deleted file mode 100644 index 082fc972cab..00000000000 --- a/tests/drivers/dma/chan_link_transfer/boards/native_posix_64.overlay +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2023 Meta - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&dma { - dma-channels = <2>; - status = "okay"; -}; - -dma0: &dma { }; diff --git a/tests/drivers/dma/chan_link_transfer/boards/native_posix_64.conf b/tests/drivers/dma/chan_link_transfer/boards/native_posix_native_64.conf similarity index 100% rename from tests/drivers/dma/chan_link_transfer/boards/native_posix_64.conf rename to tests/drivers/dma/chan_link_transfer/boards/native_posix_native_64.conf diff --git a/tests/drivers/dma/chan_link_transfer/testcase.yaml b/tests/drivers/dma/chan_link_transfer/testcase.yaml index 23bb9c6bc8a..74f8b7ca13c 100644 --- a/tests/drivers/dma/chan_link_transfer/testcase.yaml +++ b/tests/drivers/dma/chan_link_transfer/testcase.yaml @@ -17,8 +17,8 @@ tests: - lpcxpresso55s69/lpc55s69/cpu0 - lpcxpresso55s36 - native_posix - - native_posix_64 + - native_posix/native/64 integration_platforms: - frdm_k64f - native_posix - - native_posix_64 + - native_posix/native/64 diff --git a/tests/drivers/dma/loop_transfer/boards/native_posix_64.overlay b/tests/drivers/dma/loop_transfer/boards/native_posix_64.overlay deleted file mode 100644 index 28f19ac0f0d..00000000000 --- a/tests/drivers/dma/loop_transfer/boards/native_posix_64.overlay +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2023 Meta - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&dma { - dma-channels = <2>; - status = "okay"; -}; - -tst_dma0: &dma { }; diff --git a/tests/drivers/dma/loop_transfer/boards/native_posix_64.conf b/tests/drivers/dma/loop_transfer/boards/native_posix_native_64.conf similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/native_posix_64.conf rename to tests/drivers/dma/loop_transfer/boards/native_posix_native_64.conf diff --git a/tests/drivers/dma/loop_transfer/testcase.yaml b/tests/drivers/dma/loop_transfer/testcase.yaml index cee3d848e04..81da4ff93b1 100644 --- a/tests/drivers/dma/loop_transfer/testcase.yaml +++ b/tests/drivers/dma/loop_transfer/testcase.yaml @@ -6,5 +6,5 @@ tests: - dma integration_platforms: - native_posix - - native_posix_64 + - native_posix/native/64 filter: dt_nodelabel_enabled("tst_dma0") diff --git a/tests/drivers/dma/scatter_gather/boards/native_posix_64.overlay b/tests/drivers/dma/scatter_gather/boards/native_posix_64.overlay deleted file mode 100644 index 8afb0753c10..00000000000 --- a/tests/drivers/dma/scatter_gather/boards/native_posix_64.overlay +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2023 Meta - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&dma { - dma-channels = <2>; - dma-requests = <4>; - status = "okay"; -}; - -test_dma0: &dma { }; diff --git a/tests/drivers/dma/scatter_gather/boards/native_posix_64.conf b/tests/drivers/dma/scatter_gather/boards/native_posix_native_64.conf similarity index 100% rename from tests/drivers/dma/scatter_gather/boards/native_posix_64.conf rename to tests/drivers/dma/scatter_gather/boards/native_posix_native_64.conf diff --git a/tests/drivers/dma/scatter_gather/testcase.yaml b/tests/drivers/dma/scatter_gather/testcase.yaml index 78b5e0f115e..76b8dbe3ca6 100644 --- a/tests/drivers/dma/scatter_gather/testcase.yaml +++ b/tests/drivers/dma/scatter_gather/testcase.yaml @@ -10,9 +10,9 @@ tests: - mimxrt1060_evk - lpcxpresso55s36 - native_posix - - native_posix_64 + - native_posix/native/64 filter: dt_alias_exists("dma0") integration_platforms: - intel_adsp/cavs25 - native_posix - - native_posix_64 + - native_posix/native/64 From 821d2efdb9c31bb7f484a017ca5834230fd9dbbc Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:10:21 +0100 Subject: [PATCH 0769/2402] tests/subsys/logging: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- .../log_backend_fs/boards/native_sim_64.conf | 1 - .../boards/native_sim_64.overlay | 36 ------------------- .../logging/log_backend_fs/testcase.yaml | 2 +- 3 files changed, 1 insertion(+), 38 deletions(-) delete mode 100644 tests/subsys/logging/log_backend_fs/boards/native_sim_64.conf delete mode 100644 tests/subsys/logging/log_backend_fs/boards/native_sim_64.overlay diff --git a/tests/subsys/logging/log_backend_fs/boards/native_sim_64.conf b/tests/subsys/logging/log_backend_fs/boards/native_sim_64.conf deleted file mode 100644 index 92c00c89a36..00000000000 --- a/tests/subsys/logging/log_backend_fs/boards/native_sim_64.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_LOG_MODE_DEFERRED=y diff --git a/tests/subsys/logging/log_backend_fs/boards/native_sim_64.overlay b/tests/subsys/logging/log_backend_fs/boards/native_sim_64.overlay deleted file mode 100644 index 822dd511251..00000000000 --- a/tests/subsys/logging/log_backend_fs/boards/native_sim_64.overlay +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2021 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/delete-node/ &storage_partition; - -/ { - fstab { - compatible = "zephyr,fstab"; - lfs1: lfs1 { - compatible = "zephyr,fstab,littlefs"; - mount-point = "/lfs1"; - partition = <&lfs1_part>; - read-size = <16>; - prog-size = <16>; - cache-size = <64>; - lookahead-size = <32>; - block-cycles = <512>; - }; - }; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - lfs1_part: partition@fc000 { - label = "storage"; - reg = <0x000fc000 0x00010000>; - }; - }; -}; diff --git a/tests/subsys/logging/log_backend_fs/testcase.yaml b/tests/subsys/logging/log_backend_fs/testcase.yaml index 60ad3a0a295..af3eb759fbd 100644 --- a/tests/subsys/logging/log_backend_fs/testcase.yaml +++ b/tests/subsys/logging/log_backend_fs/testcase.yaml @@ -9,7 +9,7 @@ common: - littlefs platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 - nrf52840dk/nrf52840 - mr_canhubk3 integration_platforms: From 73ab92e530036abadd0ca5f5f0e09cbf08895548 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:13:06 +0100 Subject: [PATCH 0770/2402] tests/drivers/gpio: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- .../gpio/gpio_api_1pin/boards/native_sim_64.overlay | 6 ------ .../gpio/gpio_basic_api/boards/native_sim_64.overlay | 6 ------ .../boards/native_sim_64.overlay | 1 - .../gpio/gpio_enable_disable_interrupt/testcase.yaml | 2 +- .../gpio/gpio_get_direction/boards/native_sim_64.overlay | 1 - tests/drivers/gpio/gpio_hogs/boards/native_sim_64.overlay | 7 ------- tests/drivers/gpio/gpio_hogs/testcase.yaml | 4 ++-- ...ive_posix_64.overlay => native_posix_native_64.overlay} | 0 tests/drivers/gpio/gpio_reserved_ranges/testcase.yaml | 4 ++-- 9 files changed, 5 insertions(+), 26 deletions(-) delete mode 100644 tests/drivers/gpio/gpio_api_1pin/boards/native_sim_64.overlay delete mode 100644 tests/drivers/gpio/gpio_basic_api/boards/native_sim_64.overlay delete mode 100644 tests/drivers/gpio/gpio_enable_disable_interrupt/boards/native_sim_64.overlay delete mode 100644 tests/drivers/gpio/gpio_get_direction/boards/native_sim_64.overlay delete mode 100644 tests/drivers/gpio/gpio_hogs/boards/native_sim_64.overlay rename tests/drivers/gpio/gpio_reserved_ranges/boards/{native_posix_64.overlay => native_posix_native_64.overlay} (100%) diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/native_sim_64.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/native_sim_64.overlay deleted file mode 100644 index 2a9749002bd..00000000000 --- a/tests/drivers/gpio/gpio_api_1pin/boards/native_sim_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2020 Friedt Professional Engineering Services, Inc - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_sim.overlay" diff --git a/tests/drivers/gpio/gpio_basic_api/boards/native_sim_64.overlay b/tests/drivers/gpio/gpio_basic_api/boards/native_sim_64.overlay deleted file mode 100644 index 2a9749002bd..00000000000 --- a/tests/drivers/gpio/gpio_basic_api/boards/native_sim_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2020 Friedt Professional Engineering Services, Inc - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_sim.overlay" diff --git a/tests/drivers/gpio/gpio_enable_disable_interrupt/boards/native_sim_64.overlay b/tests/drivers/gpio/gpio_enable_disable_interrupt/boards/native_sim_64.overlay deleted file mode 100644 index 6a3daca3241..00000000000 --- a/tests/drivers/gpio/gpio_enable_disable_interrupt/boards/native_sim_64.overlay +++ /dev/null @@ -1 +0,0 @@ -#include "native_sim.overlay" diff --git a/tests/drivers/gpio/gpio_enable_disable_interrupt/testcase.yaml b/tests/drivers/gpio/gpio_enable_disable_interrupt/testcase.yaml index 0e88895295e..d2e691d74b4 100644 --- a/tests/drivers/gpio/gpio_enable_disable_interrupt/testcase.yaml +++ b/tests/drivers/gpio/gpio_enable_disable_interrupt/testcase.yaml @@ -7,4 +7,4 @@ tests: filter: dt_compat_enabled("test-gpio-enable-disable-interrupt") platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 diff --git a/tests/drivers/gpio/gpio_get_direction/boards/native_sim_64.overlay b/tests/drivers/gpio/gpio_get_direction/boards/native_sim_64.overlay deleted file mode 100644 index 6a3daca3241..00000000000 --- a/tests/drivers/gpio/gpio_get_direction/boards/native_sim_64.overlay +++ /dev/null @@ -1 +0,0 @@ -#include "native_sim.overlay" diff --git a/tests/drivers/gpio/gpio_hogs/boards/native_sim_64.overlay b/tests/drivers/gpio/gpio_hogs/boards/native_sim_64.overlay deleted file mode 100644 index d3b3d261734..00000000000 --- a/tests/drivers/gpio/gpio_hogs/boards/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2023 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 -*/ - -#include "native_sim.overlay" diff --git a/tests/drivers/gpio/gpio_hogs/testcase.yaml b/tests/drivers/gpio/gpio_hogs/testcase.yaml index 357ed4388c3..998d68d7c67 100644 --- a/tests/drivers/gpio/gpio_hogs/testcase.yaml +++ b/tests/drivers/gpio/gpio_hogs/testcase.yaml @@ -6,7 +6,7 @@ tests: depends_on: gpio platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 - frdm_k64f - nrf52840dk/nrf52840 - nucleo_g474re @@ -18,4 +18,4 @@ tests: - s32z2xxdc2@D/s32z270/rtu1 integration_platforms: - native_sim - - native_sim_64 + - native_sim/native/64 diff --git a/tests/drivers/gpio/gpio_reserved_ranges/boards/native_posix_64.overlay b/tests/drivers/gpio/gpio_reserved_ranges/boards/native_posix_native_64.overlay similarity index 100% rename from tests/drivers/gpio/gpio_reserved_ranges/boards/native_posix_64.overlay rename to tests/drivers/gpio/gpio_reserved_ranges/boards/native_posix_native_64.overlay diff --git a/tests/drivers/gpio/gpio_reserved_ranges/testcase.yaml b/tests/drivers/gpio/gpio_reserved_ranges/testcase.yaml index 015cf79c3fc..428212480df 100644 --- a/tests/drivers/gpio/gpio_reserved_ranges/testcase.yaml +++ b/tests/drivers/gpio/gpio_reserved_ranges/testcase.yaml @@ -5,7 +5,7 @@ tests: filter: dt_compat_enabled("test-gpio-reserved-ranges") platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim - - native_sim_64 + - native_sim/native/64 From 7edcc4eb06d8c2f99a3fb6a09236f3508c48478a Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:14:47 +0100 Subject: [PATCH 0771/2402] tests/drivers/input: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- .../input/gpio_kbd_matrix/boards/native_sim_64.overlay | 7 ------- tests/drivers/input/gpio_kbd_matrix/testcase.yaml | 2 +- tests/drivers/input/gpio_keys/boards/native_sim_64.overlay | 6 ------ tests/drivers/input/gpio_keys/testcase.yaml | 2 +- .../drivers/input/kbd_matrix/boards/native_sim_64.overlay | 7 ------- tests/drivers/input/kbd_matrix/testcase.yaml | 2 +- 6 files changed, 3 insertions(+), 23 deletions(-) delete mode 100644 tests/drivers/input/gpio_kbd_matrix/boards/native_sim_64.overlay delete mode 100644 tests/drivers/input/gpio_keys/boards/native_sim_64.overlay delete mode 100644 tests/drivers/input/kbd_matrix/boards/native_sim_64.overlay diff --git a/tests/drivers/input/gpio_kbd_matrix/boards/native_sim_64.overlay b/tests/drivers/input/gpio_kbd_matrix/boards/native_sim_64.overlay deleted file mode 100644 index 1cf720283b3..00000000000 --- a/tests/drivers/input/gpio_kbd_matrix/boards/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright 2023 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.overlay" diff --git a/tests/drivers/input/gpio_kbd_matrix/testcase.yaml b/tests/drivers/input/gpio_kbd_matrix/testcase.yaml index a92532de3a0..15ccb135a20 100644 --- a/tests/drivers/input/gpio_kbd_matrix/testcase.yaml +++ b/tests/drivers/input/gpio_kbd_matrix/testcase.yaml @@ -3,7 +3,7 @@ common: platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 tags: - drivers - input diff --git a/tests/drivers/input/gpio_keys/boards/native_sim_64.overlay b/tests/drivers/input/gpio_keys/boards/native_sim_64.overlay deleted file mode 100644 index a906fce7488..00000000000 --- a/tests/drivers/input/gpio_keys/boards/native_sim_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright 2023 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_sim.overlay" diff --git a/tests/drivers/input/gpio_keys/testcase.yaml b/tests/drivers/input/gpio_keys/testcase.yaml index be4cb2b17e9..6a3aeaa3388 100644 --- a/tests/drivers/input/gpio_keys/testcase.yaml +++ b/tests/drivers/input/gpio_keys/testcase.yaml @@ -7,6 +7,6 @@ tests: - input platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim diff --git a/tests/drivers/input/kbd_matrix/boards/native_sim_64.overlay b/tests/drivers/input/kbd_matrix/boards/native_sim_64.overlay deleted file mode 100644 index 1cf720283b3..00000000000 --- a/tests/drivers/input/kbd_matrix/boards/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright 2023 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.overlay" diff --git a/tests/drivers/input/kbd_matrix/testcase.yaml b/tests/drivers/input/kbd_matrix/testcase.yaml index fc49c031a68..f9bb0c9bff6 100644 --- a/tests/drivers/input/kbd_matrix/testcase.yaml +++ b/tests/drivers/input/kbd_matrix/testcase.yaml @@ -3,7 +3,7 @@ common: platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 tags: - drivers - input From 8d59309cca6cfea5ea4e368d4d50ea127b2923b4 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:16:20 +0100 Subject: [PATCH 0772/2402] tests/drivers/flash_simulator: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- .../flash_simulator/boards/native_posix_64.overlay | 7 ------- .../drivers/flash_simulator/boards/native_sim_64.overlay | 7 ------- tests/drivers/flash_simulator/testcase.yaml | 8 ++++---- 3 files changed, 4 insertions(+), 18 deletions(-) delete mode 100644 tests/drivers/flash_simulator/boards/native_posix_64.overlay delete mode 100644 tests/drivers/flash_simulator/boards/native_sim_64.overlay diff --git a/tests/drivers/flash_simulator/boards/native_posix_64.overlay b/tests/drivers/flash_simulator/boards/native_posix_64.overlay deleted file mode 100644 index 3467d3e6b38..00000000000 --- a/tests/drivers/flash_simulator/boards/native_posix_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_posix.overlay" diff --git a/tests/drivers/flash_simulator/boards/native_sim_64.overlay b/tests/drivers/flash_simulator/boards/native_sim_64.overlay deleted file mode 100644 index 59b29bd8512..00000000000 --- a/tests/drivers/flash_simulator/boards/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.overlay" diff --git a/tests/drivers/flash_simulator/testcase.yaml b/tests/drivers/flash_simulator/testcase.yaml index 04b435c4942..11efcf49278 100644 --- a/tests/drivers/flash_simulator/testcase.yaml +++ b/tests/drivers/flash_simulator/testcase.yaml @@ -7,9 +7,9 @@ tests: platform_allow: - qemu_x86 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - nucleo_f411re integration_platforms: - qemu_x86 @@ -25,6 +25,6 @@ tests: - native_sim drivers.flash.flash_simulator.native_64_erase_value_0x00: extra_args: DTC_OVERLAY_FILE=boards/native_64_ev_0x00.overlay - platform_allow: native_posix_64 native_sim_64 + platform_allow: native_posix/native/64 native_sim/native/64 integration_platforms: - - native_sim_64 + - native_sim/native/64 From b2fa6067a309ff3f6b2319146e725db00c0a09d1 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:18:12 +0100 Subject: [PATCH 0773/2402] tests/drivers/udc: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. Signed-off-by: Alberto Escolar Piedras --- .../boards/{native_sim_64.conf => native_sim_native_64.conf} | 0 .../{native_sim_64.overlay => native_sim_native_64.overlay} | 0 tests/drivers/udc/testcase.yaml | 2 +- 3 files changed, 1 insertion(+), 1 deletion(-) rename tests/drivers/udc/boards/{native_sim_64.conf => native_sim_native_64.conf} (100%) rename tests/drivers/udc/boards/{native_sim_64.overlay => native_sim_native_64.overlay} (100%) diff --git a/tests/drivers/udc/boards/native_sim_64.conf b/tests/drivers/udc/boards/native_sim_native_64.conf similarity index 100% rename from tests/drivers/udc/boards/native_sim_64.conf rename to tests/drivers/udc/boards/native_sim_native_64.conf diff --git a/tests/drivers/udc/boards/native_sim_64.overlay b/tests/drivers/udc/boards/native_sim_native_64.overlay similarity index 100% rename from tests/drivers/udc/boards/native_sim_64.overlay rename to tests/drivers/udc/boards/native_sim_native_64.overlay diff --git a/tests/drivers/udc/testcase.yaml b/tests/drivers/udc/testcase.yaml index e43a7a11c16..00ac41fda81 100644 --- a/tests/drivers/udc/testcase.yaml +++ b/tests/drivers/udc/testcase.yaml @@ -5,4 +5,4 @@ tests: - drivers platform_allow: - nrf52840dk/nrf52840 - - native_sim_64 + - native_sim/native/64 From 40a88a7b4828192659495b6d8e69d35bcdd07b44 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:19:47 +0100 Subject: [PATCH 0774/2402] tests/drivers/kscan: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- .../drivers/kscan/kscan_input/boards/native_sim_64.overlay | 6 ------ tests/drivers/kscan/kscan_input/testcase.yaml | 2 +- 2 files changed, 1 insertion(+), 7 deletions(-) delete mode 100644 tests/drivers/kscan/kscan_input/boards/native_sim_64.overlay diff --git a/tests/drivers/kscan/kscan_input/boards/native_sim_64.overlay b/tests/drivers/kscan/kscan_input/boards/native_sim_64.overlay deleted file mode 100644 index a906fce7488..00000000000 --- a/tests/drivers/kscan/kscan_input/boards/native_sim_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright 2023 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_sim.overlay" diff --git a/tests/drivers/kscan/kscan_input/testcase.yaml b/tests/drivers/kscan/kscan_input/testcase.yaml index e9565c5de0f..82f2c1df2d9 100644 --- a/tests/drivers/kscan/kscan_input/testcase.yaml +++ b/tests/drivers/kscan/kscan_input/testcase.yaml @@ -4,7 +4,7 @@ tests: drivers.input.kscan_input: platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 tags: - drivers - kscan From de0fb67c9f5fb0844fc9bad76c697f04d92dc278 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:20:44 +0100 Subject: [PATCH 0775/2402] tests/drivers several: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. Signed-off-by: Alberto Escolar Piedras --- tests/drivers/can/shell/testcase.yaml | 2 +- tests/drivers/clock_control/fixed_clock/testcase.yaml | 2 +- tests/drivers/eeprom/api/testcase.yaml | 10 +++++----- tests/drivers/eeprom/shell/testcase.yaml | 2 +- tests/drivers/gnss/gnss_dump/testcase.yaml | 4 ++-- tests/drivers/pinctrl/api/testcase.yaml | 4 ++-- tests/drivers/regulator/api/testcase.yaml | 4 ++-- tests/drivers/rtc/shell/testcase.yaml | 2 +- 8 files changed, 15 insertions(+), 15 deletions(-) diff --git a/tests/drivers/can/shell/testcase.yaml b/tests/drivers/can/shell/testcase.yaml index 6261e8fcb8f..dc7b6bb89d2 100644 --- a/tests/drivers/can/shell/testcase.yaml +++ b/tests/drivers/can/shell/testcase.yaml @@ -2,7 +2,7 @@ tests: drivers.can.shell: integration_platforms: - native_sim - - native_sim_64 + - native_sim/native/64 tags: - drivers - can diff --git a/tests/drivers/clock_control/fixed_clock/testcase.yaml b/tests/drivers/clock_control/fixed_clock/testcase.yaml index dc4d34c6e5c..fdff14bd9c3 100644 --- a/tests/drivers/clock_control/fixed_clock/testcase.yaml +++ b/tests/drivers/clock_control/fixed_clock/testcase.yaml @@ -4,4 +4,4 @@ tests: - drivers - clock platform_allow: - - native_sim_64 + - native_sim/native/64 diff --git a/tests/drivers/eeprom/api/testcase.yaml b/tests/drivers/eeprom/api/testcase.yaml index 8bc76b3e9e6..3f2032b6305 100644 --- a/tests/drivers/eeprom/api/testcase.yaml +++ b/tests/drivers/eeprom/api/testcase.yaml @@ -8,9 +8,9 @@ tests: # Tests overwrite EEPROM content, only run on select boards platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - qemu_x86 - nucleo_l152re - nucleo_l073rz @@ -23,9 +23,9 @@ tests: - OVERLAY_CONFIG=at2x_emul.conf platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim drivers.eeprom.api.build: @@ -33,7 +33,7 @@ tests: build_only: true platform_exclude: - native_sim - - native_sim_64 + - native_sim/native/64 - qemu_x86 - nucleo_l152re - nucleo_l073rz diff --git a/tests/drivers/eeprom/shell/testcase.yaml b/tests/drivers/eeprom/shell/testcase.yaml index fd78ec2c70f..74725bd687e 100644 --- a/tests/drivers/eeprom/shell/testcase.yaml +++ b/tests/drivers/eeprom/shell/testcase.yaml @@ -2,7 +2,7 @@ tests: drivers.eeprom.shell: integration_platforms: - native_sim - - native_sim_64 + - native_sim/native/64 tags: - drivers - eeprom diff --git a/tests/drivers/gnss/gnss_dump/testcase.yaml b/tests/drivers/gnss/gnss_dump/testcase.yaml index 74a652e2bfd..09e36eb619d 100644 --- a/tests/drivers/gnss/gnss_dump/testcase.yaml +++ b/tests/drivers/gnss/gnss_dump/testcase.yaml @@ -5,9 +5,9 @@ tests: tags: gnss platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim harness: console diff --git a/tests/drivers/pinctrl/api/testcase.yaml b/tests/drivers/pinctrl/api/testcase.yaml index 90a6f48a496..206f0077abb 100644 --- a/tests/drivers/pinctrl/api/testcase.yaml +++ b/tests/drivers/pinctrl/api/testcase.yaml @@ -4,9 +4,9 @@ common: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tests: diff --git a/tests/drivers/regulator/api/testcase.yaml b/tests/drivers/regulator/api/testcase.yaml index 6aa48cc3aa2..decaddce353 100644 --- a/tests/drivers/regulator/api/testcase.yaml +++ b/tests/drivers/regulator/api/testcase.yaml @@ -4,9 +4,9 @@ common: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tests: diff --git a/tests/drivers/rtc/shell/testcase.yaml b/tests/drivers/rtc/shell/testcase.yaml index f8af8b53153..21867499fd5 100644 --- a/tests/drivers/rtc/shell/testcase.yaml +++ b/tests/drivers/rtc/shell/testcase.yaml @@ -2,7 +2,7 @@ tests: drivers.rtc.shell: integration_platforms: - native_sim - - native_sim_64 + - native_sim/native/64 tags: - drivers - rtc From ac1610ec72cb8e7293b0deb63ceaf0d4bc1086c9 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:21:18 +0100 Subject: [PATCH 0776/2402] tests/net: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones Signed-off-by: Alberto Escolar Piedras --- tests/net/dhcpv4/server/testcase.yaml | 2 +- tests/net/ieee802154/6lo_fragment/testcase.yaml | 4 ++-- tests/net/ieee802154/custom_l2/testcase.yaml | 4 ++-- tests/net/ieee802154/l2/testcase.yaml | 4 ++-- tests/net/socket/af_packet/testcase.yaml | 2 +- tests/net/socket/af_packet_ipproto_raw/testcase.yaml | 2 +- tests/net/socket/can/testcase.yaml | 2 +- tests/net/socket/service/testcase.yaml | 2 +- tests/net/traffic_class/testcase.yaml | 6 +++--- 9 files changed, 14 insertions(+), 14 deletions(-) diff --git a/tests/net/dhcpv4/server/testcase.yaml b/tests/net/dhcpv4/server/testcase.yaml index 3b1c23d6048..02e92596d6f 100644 --- a/tests/net/dhcpv4/server/testcase.yaml +++ b/tests/net/dhcpv4/server/testcase.yaml @@ -4,7 +4,7 @@ common: # eventfd API does not work with native_posix so exclude it here platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 tests: net.dhcpv4_server: extra_configs: diff --git a/tests/net/ieee802154/6lo_fragment/testcase.yaml b/tests/net/ieee802154/6lo_fragment/testcase.yaml index dad5d24d7b2..41d7347a422 100644 --- a/tests/net/ieee802154/6lo_fragment/testcase.yaml +++ b/tests/net/ieee802154/6lo_fragment/testcase.yaml @@ -2,9 +2,9 @@ tests: net.ieee802154.fragment: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tags: diff --git a/tests/net/ieee802154/custom_l2/testcase.yaml b/tests/net/ieee802154/custom_l2/testcase.yaml index 97c58a16ba1..280ccce704e 100644 --- a/tests/net/ieee802154/custom_l2/testcase.yaml +++ b/tests/net/ieee802154/custom_l2/testcase.yaml @@ -2,9 +2,9 @@ tests: net.ieee802154.custom_l2: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tags: diff --git a/tests/net/ieee802154/l2/testcase.yaml b/tests/net/ieee802154/l2/testcase.yaml index 795bd13304c..147254a1b0b 100644 --- a/tests/net/ieee802154/l2/testcase.yaml +++ b/tests/net/ieee802154/l2/testcase.yaml @@ -1,9 +1,9 @@ common: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tags: diff --git a/tests/net/socket/af_packet/testcase.yaml b/tests/net/socket/af_packet/testcase.yaml index 7888ec51315..963047cf322 100644 --- a/tests/net/socket/af_packet/testcase.yaml +++ b/tests/net/socket/af_packet/testcase.yaml @@ -8,7 +8,7 @@ common: # needs root permission. platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 tests: net.socket.af_packet: min_ram: 21 diff --git a/tests/net/socket/af_packet_ipproto_raw/testcase.yaml b/tests/net/socket/af_packet_ipproto_raw/testcase.yaml index 316cc0d1700..503f52deadc 100644 --- a/tests/net/socket/af_packet_ipproto_raw/testcase.yaml +++ b/tests/net/socket/af_packet_ipproto_raw/testcase.yaml @@ -8,7 +8,7 @@ common: # needs root permission. platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 tests: net.socket.af_packet.ipproto_raw: min_ram: 21 diff --git a/tests/net/socket/can/testcase.yaml b/tests/net/socket/can/testcase.yaml index 6d5a2a495da..5acc2530b75 100644 --- a/tests/net/socket/can/testcase.yaml +++ b/tests/net/socket/can/testcase.yaml @@ -2,7 +2,7 @@ tests: net.socket.can: integration_platforms: - native_sim - - native_sim_64 + - native_sim/native/64 tags: - net - can diff --git a/tests/net/socket/service/testcase.yaml b/tests/net/socket/service/testcase.yaml index a2ea34cfe88..0db82aea218 100644 --- a/tests/net/socket/service/testcase.yaml +++ b/tests/net/socket/service/testcase.yaml @@ -7,7 +7,7 @@ common: platform_exclude: - mps2/an385 - native_posix - - native_posix_64 + - native_posix/native/64 tests: net.socket.service: min_ram: 21 diff --git a/tests/net/traffic_class/testcase.yaml b/tests/net/traffic_class/testcase.yaml index a69fe29edcb..a8e80952af7 100644 --- a/tests/net/traffic_class/testcase.yaml +++ b/tests/net/traffic_class/testcase.yaml @@ -1,11 +1,11 @@ common: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - - native_sim_64 + - native_sim/native/64 tags: - net - traffic_class From 185c60673b1717ee695339e55aad6b9888e1ba14 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:21:51 +0100 Subject: [PATCH 0777/2402] tests/boards/native_sim: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones Signed-off-by: Alberto Escolar Piedras --- tests/boards/native_sim/cpu_wait/testcase.yaml | 4 ++-- tests/boards/native_sim/rtc/testcase.yaml | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/boards/native_sim/cpu_wait/testcase.yaml b/tests/boards/native_sim/cpu_wait/testcase.yaml index cd9ea17b066..aeec84197ef 100644 --- a/tests/boards/native_sim/cpu_wait/testcase.yaml +++ b/tests/boards/native_sim/cpu_wait/testcase.yaml @@ -3,8 +3,8 @@ tests: boards.native_sim.cpu_wait: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim diff --git a/tests/boards/native_sim/rtc/testcase.yaml b/tests/boards/native_sim/rtc/testcase.yaml index cbffa6103dd..1b3da5135b2 100644 --- a/tests/boards/native_sim/rtc/testcase.yaml +++ b/tests/boards/native_sim/rtc/testcase.yaml @@ -3,9 +3,9 @@ tests: boards.native.rtc: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim build_only: true From 2c6db3b717d1424fb8937118eaf246842107ad7a Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:22:27 +0100 Subject: [PATCH 0778/2402] tests/lib: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones Signed-off-by: Alberto Escolar Piedras --- tests/lib/c_lib/thrd/testcase.yaml | 2 +- tests/lib/cpp/libcxx/testcase.yaml | 2 +- tests/lib/gui/lvgl/testcase.yaml | 4 ++-- tests/lib/hash_map/Kconfig | 2 +- tests/lib/ringbuffer/testcase.yaml | 2 +- tests/lib/time/testcase.yaml | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/lib/c_lib/thrd/testcase.yaml b/tests/lib/c_lib/thrd/testcase.yaml index ecba688407f..a1f79c8cfdf 100644 --- a/tests/lib/c_lib/thrd/testcase.yaml +++ b/tests/lib/c_lib/thrd/testcase.yaml @@ -6,7 +6,7 @@ common: - qemu_x86 platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 tests: libraries.libc.c11_threads.minimal: tags: minimal_libc diff --git a/tests/lib/cpp/libcxx/testcase.yaml b/tests/lib/cpp/libcxx/testcase.yaml index fdf0318ebd2..f9ddf58679d 100644 --- a/tests/lib/cpp/libcxx/testcase.yaml +++ b/tests/lib/cpp/libcxx/testcase.yaml @@ -49,4 +49,4 @@ tests: - CONFIG_CPP_EXCEPTIONS=y integration_platforms: - native_sim - - native_sim_64 + - native_sim/native/64 diff --git a/tests/lib/gui/lvgl/testcase.yaml b/tests/lib/gui/lvgl/testcase.yaml index fca009d9113..f878a4c4363 100644 --- a/tests/lib/gui/lvgl/testcase.yaml +++ b/tests/lib/gui/lvgl/testcase.yaml @@ -3,8 +3,8 @@ common: - display - gui platform_allow: - - native_posix_64 - - native_sim_64 + - native_posix/native/64 + - native_sim/native/64 - native_sim integration_platforms: - native_sim diff --git a/tests/lib/hash_map/Kconfig b/tests/lib/hash_map/Kconfig index 85ef6993151..421670a1cae 100644 --- a/tests/lib/hash_map/Kconfig +++ b/tests/lib/hash_map/Kconfig @@ -18,7 +18,7 @@ config TEST_LIB_HASH_MAP_MAX_ENTRIES CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE - For native_posix_64, the number of entries can be configured + For native_sim, the number of entries can be configured independently of the arena size since the native libc is used. source "Kconfig.zephyr" diff --git a/tests/lib/ringbuffer/testcase.yaml b/tests/lib/ringbuffer/testcase.yaml index 851735384f5..2733ffe3f76 100644 --- a/tests/lib/ringbuffer/testcase.yaml +++ b/tests/lib/ringbuffer/testcase.yaml @@ -8,7 +8,7 @@ tests: libraries.ring_buffer: integration_platforms: - native_sim - - native_sim_64 + - native_sim/native/64 libraries.ring_buffer.concurrent: platform_allow: qemu_x86 diff --git a/tests/lib/time/testcase.yaml b/tests/lib/time/testcase.yaml index 9b002ace2d9..bf949559f03 100644 --- a/tests/lib/time/testcase.yaml +++ b/tests/lib/time/testcase.yaml @@ -6,4 +6,4 @@ tests: - mps2/an385 platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 From 9ccf2074e46c65899ac2b40cd5b583c3d4cc76ce Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:23:04 +0100 Subject: [PATCH 0779/2402] tests/misc/check_init_priorities: Use hwmv2 native targets ident For the 64 bit targets, change identifiers to the new hwmv2 ones And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- .../misc/check_init_priorities/boards/native_sim_64.overlay | 6 ------ tests/misc/check_init_priorities/testcase.yaml | 2 +- 2 files changed, 1 insertion(+), 7 deletions(-) delete mode 100644 tests/misc/check_init_priorities/boards/native_sim_64.overlay diff --git a/tests/misc/check_init_priorities/boards/native_sim_64.overlay b/tests/misc/check_init_priorities/boards/native_sim_64.overlay deleted file mode 100644 index a906fce7488..00000000000 --- a/tests/misc/check_init_priorities/boards/native_sim_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright 2023 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_sim.overlay" diff --git a/tests/misc/check_init_priorities/testcase.yaml b/tests/misc/check_init_priorities/testcase.yaml index 5d4a2a4e9a4..571cba0e100 100644 --- a/tests/misc/check_init_priorities/testcase.yaml +++ b/tests/misc/check_init_priorities/testcase.yaml @@ -5,7 +5,7 @@ tests: build_only: true platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 - native_posix integration_platforms: - native_sim From 822778ddab0f488faf511435c16563ccd1ca9900 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 15:24:59 +0100 Subject: [PATCH 0780/2402] tests/posix: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones Signed-off-by: Alberto Escolar Piedras --- tests/posix/common/testcase.yaml | 2 +- tests/posix/fs/testcase.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/posix/common/testcase.yaml b/tests/posix/common/testcase.yaml index 1562b00320b..83569976878 100644 --- a/tests/posix/common/testcase.yaml +++ b/tests/posix/common/testcase.yaml @@ -2,7 +2,7 @@ common: filter: not CONFIG_NATIVE_LIBC platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 tags: posix min_ram: 64 timeout: 240 diff --git a/tests/posix/fs/testcase.yaml b/tests/posix/fs/testcase.yaml index 1c90ad9f0f0..eba6a94439c 100644 --- a/tests/posix/fs/testcase.yaml +++ b/tests/posix/fs/testcase.yaml @@ -4,7 +4,7 @@ common: - nios2 platform_exclude: - native_posix - - native_posix_64 + - native_posix/native/64 tags: - posix - filesystem From 00f239736424c4b56f037b6b3ba7aae0271453a6 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 16:26:38 +0100 Subject: [PATCH 0781/2402] tests/subsys/settings: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- tests/subsys/settings/fcb/boards/native_sim_64.overlay | 7 ------- tests/subsys/settings/fcb/testcase.yaml | 2 +- tests/subsys/settings/file/boards/native_sim_64.overlay | 7 ------- tests/subsys/settings/file/testcase.yaml | 2 +- tests/subsys/settings/functional/fcb/testcase.yaml | 8 ++++---- .../subsys/settings/functional/file/native_sim_64.overlay | 7 ------- tests/subsys/settings/functional/file/testcase.yaml | 2 +- tests/subsys/settings/functional/nvs/testcase.yaml | 8 ++++---- 8 files changed, 11 insertions(+), 32 deletions(-) delete mode 100644 tests/subsys/settings/fcb/boards/native_sim_64.overlay delete mode 100644 tests/subsys/settings/file/boards/native_sim_64.overlay delete mode 100644 tests/subsys/settings/functional/file/native_sim_64.overlay diff --git a/tests/subsys/settings/fcb/boards/native_sim_64.overlay b/tests/subsys/settings/fcb/boards/native_sim_64.overlay deleted file mode 100644 index 8dbed8eb97a..00000000000 --- a/tests/subsys/settings/fcb/boards/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2019 Jan Van Winkel - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.overlay" diff --git a/tests/subsys/settings/fcb/testcase.yaml b/tests/subsys/settings/fcb/testcase.yaml index 01dc9f5bf0f..64b00e65bec 100644 --- a/tests/subsys/settings/fcb/testcase.yaml +++ b/tests/subsys/settings/fcb/testcase.yaml @@ -4,7 +4,7 @@ tests: - nrf52840dk/nrf52840 - nrf52dk/nrf52832 - native_sim - - native_sim_64 + - native_sim/native/64 - mr_canhubk3 integration_platforms: - nrf52840dk/nrf52840 diff --git a/tests/subsys/settings/file/boards/native_sim_64.overlay b/tests/subsys/settings/file/boards/native_sim_64.overlay deleted file mode 100644 index 55d159158f8..00000000000 --- a/tests/subsys/settings/file/boards/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2019 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.overlay" diff --git a/tests/subsys/settings/file/testcase.yaml b/tests/subsys/settings/file/testcase.yaml index c98239ca2ad..32d0c2576d6 100644 --- a/tests/subsys/settings/file/testcase.yaml +++ b/tests/subsys/settings/file/testcase.yaml @@ -6,7 +6,7 @@ tests: platform_allow: - nrf52840dk/nrf52840 - native_sim - - native_sim_64 + - native_sim/native/64 - mr_canhubk3 tags: - settings diff --git a/tests/subsys/settings/functional/fcb/testcase.yaml b/tests/subsys/settings/functional/fcb/testcase.yaml index eaad89b64e6..420a63c6430 100644 --- a/tests/subsys/settings/functional/fcb/testcase.yaml +++ b/tests/subsys/settings/functional/fcb/testcase.yaml @@ -4,9 +4,9 @@ tests: - nrf52840dk/nrf52840 - nrf52dk/nrf52832 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - mr_canhubk3 integration_platforms: - nrf52840dk/nrf52840 @@ -17,9 +17,9 @@ tests: extra_args: DTC_OVERLAY_FILE=./chosen.overlay platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - mr_canhubk3 integration_platforms: - native_sim diff --git a/tests/subsys/settings/functional/file/native_sim_64.overlay b/tests/subsys/settings/functional/file/native_sim_64.overlay deleted file mode 100644 index 8dbed8eb97a..00000000000 --- a/tests/subsys/settings/functional/file/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2019 Jan Van Winkel - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.overlay" diff --git a/tests/subsys/settings/functional/file/testcase.yaml b/tests/subsys/settings/functional/file/testcase.yaml index bb4b9036f4b..00565155e17 100644 --- a/tests/subsys/settings/functional/file/testcase.yaml +++ b/tests/subsys/settings/functional/file/testcase.yaml @@ -4,7 +4,7 @@ tests: - nrf52840dk/nrf52840 - nrf52dk/nrf52832 - native_sim - - native_sim_64 + - native_sim/native/64 - mr_canhubk3 integration_platforms: - native_sim diff --git a/tests/subsys/settings/functional/nvs/testcase.yaml b/tests/subsys/settings/functional/nvs/testcase.yaml index 3f0cf37b796..8abb0039b19 100644 --- a/tests/subsys/settings/functional/nvs/testcase.yaml +++ b/tests/subsys/settings/functional/nvs/testcase.yaml @@ -3,9 +3,9 @@ tests: platform_allow: - qemu_x86 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 tags: - settings - nvs @@ -13,9 +13,9 @@ tests: extra_args: DTC_OVERLAY_FILE=./chosen.overlay platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 tags: - settings - nvs From 0df3c62461fc87099370e8215eb162d8c34fcc60 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 16:28:55 +0100 Subject: [PATCH 0782/2402] tests/subsys/input: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- tests/subsys/input/kbd_matrix_state_dump/testcase.yaml | 4 ++-- tests/subsys/input/longpress/boards/native_sim_64.overlay | 6 ------ tests/subsys/input/longpress/testcase.yaml | 2 +- tests/subsys/input/shell/testcase.yaml | 4 ++-- 4 files changed, 5 insertions(+), 11 deletions(-) delete mode 100644 tests/subsys/input/longpress/boards/native_sim_64.overlay diff --git a/tests/subsys/input/kbd_matrix_state_dump/testcase.yaml b/tests/subsys/input/kbd_matrix_state_dump/testcase.yaml index 187a2046831..24bd4c12502 100644 --- a/tests/subsys/input/kbd_matrix_state_dump/testcase.yaml +++ b/tests/subsys/input/kbd_matrix_state_dump/testcase.yaml @@ -4,9 +4,9 @@ common: tags: input platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim harness: console diff --git a/tests/subsys/input/longpress/boards/native_sim_64.overlay b/tests/subsys/input/longpress/boards/native_sim_64.overlay deleted file mode 100644 index a906fce7488..00000000000 --- a/tests/subsys/input/longpress/boards/native_sim_64.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright 2023 Google LLC - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "native_sim.overlay" diff --git a/tests/subsys/input/longpress/testcase.yaml b/tests/subsys/input/longpress/testcase.yaml index 8ad1d41a31a..046690c96bb 100644 --- a/tests/subsys/input/longpress/testcase.yaml +++ b/tests/subsys/input/longpress/testcase.yaml @@ -4,7 +4,7 @@ tests: input.input_longpress: platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 tags: - drivers - input diff --git a/tests/subsys/input/shell/testcase.yaml b/tests/subsys/input/shell/testcase.yaml index 2848957f74a..857ab120567 100644 --- a/tests/subsys/input/shell/testcase.yaml +++ b/tests/subsys/input/shell/testcase.yaml @@ -5,9 +5,9 @@ tests: tags: input platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim harness: console From 5ddb8d499ebb59a26a098007df495f30415fd44b Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 16:30:29 +0100 Subject: [PATCH 0783/2402] tests/subsys/fs: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- tests/subsys/fs/ext2/boards/native_sim_64.overlay | 7 ------- tests/subsys/fs/ext2/testcase.yaml | 6 +++--- tests/subsys/fs/fcb/testcase.yaml | 4 ++-- tests/subsys/fs/littlefs/boards/native_sim_64.overlay | 7 ------- tests/subsys/fs/littlefs/testcase.yaml | 2 +- 5 files changed, 6 insertions(+), 20 deletions(-) delete mode 100644 tests/subsys/fs/ext2/boards/native_sim_64.overlay delete mode 100644 tests/subsys/fs/littlefs/boards/native_sim_64.overlay diff --git a/tests/subsys/fs/ext2/boards/native_sim_64.overlay b/tests/subsys/fs/ext2/boards/native_sim_64.overlay deleted file mode 100644 index f3f8b087d9b..00000000000 --- a/tests/subsys/fs/ext2/boards/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2023 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.overlay" diff --git a/tests/subsys/fs/ext2/testcase.yaml b/tests/subsys/fs/ext2/testcase.yaml index 76ec97de3c8..bfe58c979f6 100644 --- a/tests/subsys/fs/ext2/testcase.yaml +++ b/tests/subsys/fs/ext2/testcase.yaml @@ -4,7 +4,7 @@ tests: filesystem.ext2.default: platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 - hifive_unmatched - bl5340_dvk/nrf5340/cpuapp extra_args: @@ -13,7 +13,7 @@ tests: filesystem.ext2.big: platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 extra_args: - CONF_FILE=prj_big.conf - EXTRA_DTC_OVERLAY_FILE="ramdisk_big.overlay" @@ -29,5 +29,5 @@ tests: filesystem.ext2.flash: platform_allow: - native_sim - - native_sim_64 + - native_sim/native/64 extra_args: CONF_FILE=prj_flash.conf diff --git a/tests/subsys/fs/fcb/testcase.yaml b/tests/subsys/fs/fcb/testcase.yaml index 9070bbaf7bb..e01566b6721 100644 --- a/tests/subsys/fs/fcb/testcase.yaml +++ b/tests/subsys/fs/fcb/testcase.yaml @@ -5,9 +5,9 @@ tests: - nrf52dk/nrf52832 - nrf51dk/nrf51822 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - mr_canhubk3 tags: flash_circural_buffer integration_platforms: diff --git a/tests/subsys/fs/littlefs/boards/native_sim_64.overlay b/tests/subsys/fs/littlefs/boards/native_sim_64.overlay deleted file mode 100644 index 8dbed8eb97a..00000000000 --- a/tests/subsys/fs/littlefs/boards/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2019 Jan Van Winkel - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.overlay" diff --git a/tests/subsys/fs/littlefs/testcase.yaml b/tests/subsys/fs/littlefs/testcase.yaml index 1a125021bf7..b64ffa43d96 100644 --- a/tests/subsys/fs/littlefs/testcase.yaml +++ b/tests/subsys/fs/littlefs/testcase.yaml @@ -5,7 +5,7 @@ common: platform_allow: - nrf52840dk/nrf52840 - native_sim - - native_sim_64 + - native_sim/native/64 - mimxrt1060_evk - mr_canhubk3 integration_platforms: From 94a868152727a0b6290e4632eb7f6ae4f5b37661 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 16:31:14 +0100 Subject: [PATCH 0784/2402] tests/subsys/dfu: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. And remove redundant overlays (which were equal for the 32 and 64 bit versions) Signed-off-by: Alberto Escolar Piedras --- tests/subsys/dfu/img_util/testcase.yaml | 4 ++-- tests/subsys/dfu/mcuboot/testcase.yaml | 4 ++-- tests/subsys/dfu/mcuboot_multi/native_sim_64.overlay | 7 ------- tests/subsys/dfu/mcuboot_multi/testcase.yaml | 2 +- 4 files changed, 5 insertions(+), 12 deletions(-) delete mode 100644 tests/subsys/dfu/mcuboot_multi/native_sim_64.overlay diff --git a/tests/subsys/dfu/img_util/testcase.yaml b/tests/subsys/dfu/img_util/testcase.yaml index 58cc48f98a6..54b8de1320e 100644 --- a/tests/subsys/dfu/img_util/testcase.yaml +++ b/tests/subsys/dfu/img_util/testcase.yaml @@ -2,9 +2,9 @@ common: platform_allow: - nrf52840dk/nrf52840 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - nrf52840dk/nrf52840 tests: diff --git a/tests/subsys/dfu/mcuboot/testcase.yaml b/tests/subsys/dfu/mcuboot/testcase.yaml index 3b1ddc39a3c..14e2429ce0a 100644 --- a/tests/subsys/dfu/mcuboot/testcase.yaml +++ b/tests/subsys/dfu/mcuboot/testcase.yaml @@ -3,9 +3,9 @@ tests: platform_allow: - nrf52840dk/nrf52840 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 tags: dfu_mcuboot integration_platforms: - nrf52840dk/nrf52840 diff --git a/tests/subsys/dfu/mcuboot_multi/native_sim_64.overlay b/tests/subsys/dfu/mcuboot_multi/native_sim_64.overlay deleted file mode 100644 index 3e51723713a..00000000000 --- a/tests/subsys/dfu/mcuboot_multi/native_sim_64.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2020 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.overlay" diff --git a/tests/subsys/dfu/mcuboot_multi/testcase.yaml b/tests/subsys/dfu/mcuboot_multi/testcase.yaml index 9f641191803..5ded74912ab 100644 --- a/tests/subsys/dfu/mcuboot_multi/testcase.yaml +++ b/tests/subsys/dfu/mcuboot_multi/testcase.yaml @@ -3,7 +3,7 @@ tests: platform_allow: - nrf52840dk/nrf52840 - native_sim - - native_sim_64 + - native_sim/native/64 tags: dfu_mcuboot integration_platforms: - nrf52840dk/nrf52840 From 8abdc4966474d7ba56539d288ba7fb50a694c1e2 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 16:31:59 +0100 Subject: [PATCH 0785/2402] tests/subsys several: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones. Signed-off-by: Alberto Escolar Piedras --- tests/subsys/mem_mgmt/mem_attr/testcase.yaml | 4 ++-- tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml | 4 ++-- tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml | 4 ++-- tests/subsys/openthread/testcase.yaml | 4 ++-- tests/subsys/pm/policy_api/testcase.yaml | 4 ++-- tests/subsys/storage/flash_map/testcase.yaml | 8 ++++---- tests/subsys/storage/stream/stream_flash/testcase.yaml | 4 ++-- tests/subsys/testsuite/fff_fake_contexts/testcase.yaml | 6 +++--- tests/subsys/usb/os_desc/testcase.yaml | 4 ++-- 9 files changed, 21 insertions(+), 21 deletions(-) diff --git a/tests/subsys/mem_mgmt/mem_attr/testcase.yaml b/tests/subsys/mem_mgmt/mem_attr/testcase.yaml index 63e5c1668d6..3acc3206ff9 100644 --- a/tests/subsys/mem_mgmt/mem_attr/testcase.yaml +++ b/tests/subsys/mem_mgmt/mem_attr/testcase.yaml @@ -1,9 +1,9 @@ common: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tests: diff --git a/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml b/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml index 7243c980375..d48228dcb96 100644 --- a/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml @@ -8,9 +8,9 @@ tests: platform_allow: - qemu_cortex_m3 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - qemu_riscv32/qemu_virt_riscv32/smp - qemu_riscv64 tags: diff --git a/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml b/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml index 07bf722bbf9..dc4247c6a6a 100644 --- a/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml @@ -7,9 +7,9 @@ tests: settings.mgmt: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - nrf52840dk/nrf52840 tags: - settings_mgmt diff --git a/tests/subsys/openthread/testcase.yaml b/tests/subsys/openthread/testcase.yaml index d017c38370a..c019aa9a8c5 100644 --- a/tests/subsys/openthread/testcase.yaml +++ b/tests/subsys/openthread/testcase.yaml @@ -1,9 +1,9 @@ common: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tags: diff --git a/tests/subsys/pm/policy_api/testcase.yaml b/tests/subsys/pm/policy_api/testcase.yaml index 5df6032ab1d..168a92a79f0 100644 --- a/tests/subsys/pm/policy_api/testcase.yaml +++ b/tests/subsys/pm/policy_api/testcase.yaml @@ -5,9 +5,9 @@ common: tags: pm platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tests: diff --git a/tests/subsys/storage/flash_map/testcase.yaml b/tests/subsys/storage/flash_map/testcase.yaml index 027b3865fdd..3ed44f28e07 100644 --- a/tests/subsys/storage/flash_map/testcase.yaml +++ b/tests/subsys/storage/flash_map/testcase.yaml @@ -4,9 +4,9 @@ tests: - nrf51dk/nrf51822 - qemu_x86 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - mr_canhubk3 tags: flash_map integration_platforms: @@ -28,9 +28,9 @@ tests: - nrf51dk/nrf51822 - qemu_x86 - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - mr_canhubk3 tags: flash_map integration_platforms: diff --git a/tests/subsys/storage/stream/stream_flash/testcase.yaml b/tests/subsys/storage/stream/stream_flash/testcase.yaml index e61557feadc..a2df663d871 100644 --- a/tests/subsys/storage/stream/stream_flash/testcase.yaml +++ b/tests/subsys/storage/stream/stream_flash/testcase.yaml @@ -1,9 +1,9 @@ common: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tests: diff --git a/tests/subsys/testsuite/fff_fake_contexts/testcase.yaml b/tests/subsys/testsuite/fff_fake_contexts/testcase.yaml index 894e0f1aa99..0c8638d5ede 100644 --- a/tests/subsys/testsuite/fff_fake_contexts/testcase.yaml +++ b/tests/subsys/testsuite/fff_fake_contexts/testcase.yaml @@ -8,10 +8,10 @@ tests: testing.testsuite.fff_fake_contexts: integration_platforms: - qemu_cortex_m3 - - native_sim_64 + - native_sim/native/64 tags: test_framework platform_allow: - qemu_cortex_m3 - - native_posix_64 - - native_sim_64 + - native_posix/native/64 + - native_sim/native/64 - native_sim diff --git a/tests/subsys/usb/os_desc/testcase.yaml b/tests/subsys/usb/os_desc/testcase.yaml index 18b8ac279cc..aa989b9ddb4 100644 --- a/tests/subsys/usb/os_desc/testcase.yaml +++ b/tests/subsys/usb/os_desc/testcase.yaml @@ -2,9 +2,9 @@ tests: usb.osdesc: platform_allow: - native_posix - - native_posix_64 + - native_posix/native/64 - native_sim - - native_sim_64 + - native_sim/native/64 - frdm_k64f tags: - usb From 0d5ac4ef116ca5c2679bdec197360ab5fa40650d Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 16:32:19 +0100 Subject: [PATCH 0786/2402] tests/ztest: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones Signed-off-by: Alberto Escolar Piedras --- tests/ztest/base/testcase.yaml | 2 +- tests/ztest/fail/testcase.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/ztest/base/testcase.yaml b/tests/ztest/base/testcase.yaml index ee566d5dd8a..5cbc7b38ccb 100644 --- a/tests/ztest/base/testcase.yaml +++ b/tests/ztest/base/testcase.yaml @@ -9,7 +9,7 @@ tests: platform_allow: - native_posix - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim testing.ztest.base.verbose_0: diff --git a/tests/ztest/fail/testcase.yaml b/tests/ztest/fail/testcase.yaml index 2a0820fa85e..ef6d42b49ec 100644 --- a/tests/ztest/fail/testcase.yaml +++ b/tests/ztest/fail/testcase.yaml @@ -8,7 +8,7 @@ common: platform_allow: - native_posix - native_sim - - native_sim_64 + - native_sim/native/64 integration_platforms: - native_sim tests: From 88e48375ec24eb46a29d34db5bab863f7eecb2f1 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 16:32:56 +0100 Subject: [PATCH 0787/2402] tests/modules/nanopb: Use hwmv2 native targets identifiers For the 64 bit targets, change identifiers to the new hwmv2 ones Signed-off-by: Alberto Escolar Piedras --- tests/modules/nanopb/testcase.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/modules/nanopb/testcase.yaml b/tests/modules/nanopb/testcase.yaml index 33547630064..dfe6e51004a 100644 --- a/tests/modules/nanopb/testcase.yaml +++ b/tests/modules/nanopb/testcase.yaml @@ -6,4 +6,4 @@ tests: - nanopb integration_platforms: - native_sim - - native_sim_64 + - native_sim/native/64 From 0108c6ba3873705153c5194482fcf03c008222a1 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 13:34:19 +0100 Subject: [PATCH 0788/2402] native_sim: Add twister definition for native_sim/native/64 Which will replace the old native_sim_64 to align it with the hwmv2 naming conventions. Signed-off-by: Alberto Escolar Piedras --- .../native_sim/native_sim_native_64.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 boards/native/native_sim/native_sim_native_64.yaml diff --git a/boards/native/native_sim/native_sim_native_64.yaml b/boards/native/native_sim/native_sim_native_64.yaml new file mode 100644 index 00000000000..66decdebf4d --- /dev/null +++ b/boards/native/native_sim/native_sim_native_64.yaml @@ -0,0 +1,20 @@ +identifier: native_sim/native/64 +name: Native Simulation port - 64-bit variant +type: native +simulation: native +arch: posix +ram: 65536 +flash: 65536 +toolchain: + - host + - llvm +supported: + - can + - counter + - eeprom + - netif:eth + - usb_device + - adc + - gpio + - rtc +vendor: zephyr From 13a7258ea4e3d3edd1ed8696e595789240a2eef8 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 13:35:44 +0100 Subject: [PATCH 0789/2402] native_posix: Add twister definition for native_sim/native/64 Which will replace the old native_sim_64 to align it with the hwmv2 naming conventions. Signed-off-by: Alberto Escolar Piedras --- .../native_posix/native_posix_native_64.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 boards/native/native_posix/native_posix_native_64.yaml diff --git a/boards/native/native_posix/native_posix_native_64.yaml b/boards/native/native_posix/native_posix_native_64.yaml new file mode 100644 index 00000000000..f7081ced878 --- /dev/null +++ b/boards/native/native_posix/native_posix_native_64.yaml @@ -0,0 +1,21 @@ +identifier: native_posix/native/64 +name: Native 64-bit POSIX port +type: native +simulation: native +arch: posix +ram: 65536 +flash: 65536 +toolchain: + - host + - llvm +supported: + - can + - counter + - dma + - eeprom + - netif:eth + - usb_device + - adc + - gpio + - rtc +vendor: zephyr From 6525d6c1e8c223c458681ee4236f4dbd4960b9f2 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Fri, 8 Mar 2024 13:09:34 +0800 Subject: [PATCH 0790/2402] samples: tfm_integration: lpc55s69: enable tfm samples Enable lpcxpresso55s69/lpc55s69/cpu0/ns for supported tfm samples Signed-off-by: Hake Huang --- samples/tfm_integration/psa_protected_storage/sample.yaml | 1 + samples/tfm_integration/tfm_secure_partition/sample.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/samples/tfm_integration/psa_protected_storage/sample.yaml b/samples/tfm_integration/psa_protected_storage/sample.yaml index 4c3e2b277a9..0488e1a06cc 100644 --- a/samples/tfm_integration/psa_protected_storage/sample.yaml +++ b/samples/tfm_integration/psa_protected_storage/sample.yaml @@ -9,6 +9,7 @@ common: - nrf5340dk/nrf5340/cpuapp/ns - nrf9160dk/nrf9160/ns - bl5340_dvk/nrf5340/cpuapp/ns + - lpcxpresso55s69/lpc55s69/cpu0/ns integration_platforms: - mps2/an521/cpu0/ns harness: console diff --git a/samples/tfm_integration/tfm_secure_partition/sample.yaml b/samples/tfm_integration/tfm_secure_partition/sample.yaml index 7cd36b08475..03b84ca634b 100644 --- a/samples/tfm_integration/tfm_secure_partition/sample.yaml +++ b/samples/tfm_integration/tfm_secure_partition/sample.yaml @@ -6,6 +6,7 @@ common: - v2m_musca_s1/musca_s1/ns - nrf5340dk/nrf5340/cpuapp/ns - nrf9160dk/nrf9160/ns + - lpcxpresso55s69/lpc55s69/cpu0/ns integration_platforms: - mps2/an521/cpu0/ns harness: console From feb58c29060adefbf9fa7e239810989d240973c8 Mon Sep 17 00:00:00 2001 From: Morten Priess Date: Mon, 11 Mar 2024 15:12:00 +0100 Subject: [PATCH 0791/2402] Bluetooth: controller: Add handling of HCI reset for sync_iso Properly shut down ticker and initialize data at HCI reset. Signed-off-by: Morten Priess --- .../bluetooth/controller/ll_sw/ull_sync_iso.c | 26 ++++++++++++++++--- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c b/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c index 3989dcbf4d9..00f6a2bea6f 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c +++ b/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c @@ -790,16 +790,34 @@ uint32_t ull_big_sync_delay(const struct lll_sync_iso *lll_iso) lll_iso->phy); } +static void disable(uint8_t sync_idx) +{ + struct ll_sync_iso_set *sync_iso; + int err; + + sync_iso = &ll_sync_iso[sync_idx]; + + err = ull_ticker_stop_with_mark(TICKER_ID_SCAN_SYNC_ISO_BASE + + sync_idx, sync_iso, &sync_iso->lll); + LL_ASSERT(err == 0 || err == -EALREADY); +} + static int init_reset(void) { - /* Add initializations common to power up initialization and HCI reset - * initializations. - */ + uint8_t idx; + + /* Disable all active BIGs (uses blocking ull_ticker_stop_with_mark) */ + for (idx = 0U; idx < CONFIG_BT_CTLR_SCAN_SYNC_ISO_SET; idx++) { + disable(idx); + } mem_init((void *)stream_pool, sizeof(struct lll_sync_iso_stream), CONFIG_BT_CTLR_SYNC_ISO_STREAM_COUNT, &stream_free); - return 0; + memset(&ll_sync_iso, 0, sizeof(ll_sync_iso)); + + /* Initialize LLL */ + return lll_sync_iso_init(); } static struct ll_sync_iso_set *sync_iso_get(uint8_t handle) From 6f374d850a808f9b1f770d31ccdb4db9eaa88512 Mon Sep 17 00:00:00 2001 From: Morten Priess Date: Mon, 11 Mar 2024 15:19:18 +0100 Subject: [PATCH 0792/2402] Bluetooth: controller: Parameter check for ISO sync recv qualification Add HCI input parameter validation according to spec for passing qualification tests. - Conditional compile of LE Set PA Receive Enable feature - Store BIGinfo encryption state and number of streams - Do not report BIGinfo if phy is invalid or unsupported - Return disallowed ll_read_iso_tx_sync uses sync recever handle - Validate BIS indices in ll_big_sync_create Signed-off-by: Morten Priess --- subsys/bluetooth/controller/hci/hci.c | 11 +++++++++ subsys/bluetooth/controller/ll_sw/ull_iso.c | 3 +++ .../bluetooth/controller/ll_sw/ull_scan_aux.c | 19 ++++++++++++++- subsys/bluetooth/controller/ll_sw/ull_sync.c | 8 +++---- .../bluetooth/controller/ll_sw/ull_sync_iso.c | 23 +++++++++++++++++-- .../controller/ll_sw/ull_sync_types.h | 5 ++++ 6 files changed, 62 insertions(+), 7 deletions(-) diff --git a/subsys/bluetooth/controller/hci/hci.c b/subsys/bluetooth/controller/hci/hci.c index 1bb10f578d2..2069d58094e 100644 --- a/subsys/bluetooth/controller/hci/hci.c +++ b/subsys/bluetooth/controller/hci/hci.c @@ -887,8 +887,10 @@ static void read_supported_commands(struct net_buf *buf, struct net_buf **evt) */ rp->commands[38] |= BIT(3) | BIT(4) | BIT(5) | BIT(6); #endif /* CONFIG_BT_CTLR_SYNC_PERIODIC_ADV_LIST */ +#if defined(CONFIG_BT_CTLR_SYNC_PERIODIC) /* LE Set PA Receive Enable */ rp->commands[40] |= BIT(5); +#endif /* CONFIG_BT_CTLR_SYNC_PERIODIC */ #if defined(CONFIG_BT_CTLR_SYNC_ISO) /* LE BIG Create Sync, LE BIG Terminate Sync */ rp->commands[43] |= BIT(0) | BIT(1); @@ -7749,6 +7751,7 @@ static void le_per_adv_sync_report(struct pdu_data *pdu_data, struct bt_hci_evt_le_biginfo_adv_report *sep; struct pdu_big_info *bi; uint8_t bi_size; + uint8_t phy; /* FIXME: Parse and find the BIGInfo */ if (acad[PDU_ADV_DATA_HEADER_TYPE_OFFSET] != BT_DATA_BIG_INFO) { @@ -7758,6 +7761,14 @@ static void le_per_adv_sync_report(struct pdu_data *pdu_data, bi_size = acad[PDU_ADV_DATA_HEADER_LEN_OFFSET]; bi = (void *)&acad[PDU_ADV_DATA_HEADER_DATA_OFFSET]; + /* Do not report if phy is invalid or unsupported */ + phy = (bi->chm_phy[4] >> 5); + if ((phy > EXT_ADV_AUX_PHY_LE_CODED) || + (!IS_ENABLED(CONFIG_BT_CTLR_PHY_CODED) && + (phy == EXT_ADV_AUX_PHY_LE_CODED))) { + return; + } + /* Allocate new event buffer if periodic advertising report was * constructed with the caller supplied buffer. */ diff --git a/subsys/bluetooth/controller/ll_sw/ull_iso.c b/subsys/bluetooth/controller/ll_sw/ull_iso.c index a60e66ba81b..23a2a869ca7 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_iso.c +++ b/subsys/bluetooth/controller/ll_sw/ull_iso.c @@ -189,6 +189,9 @@ uint8_t ll_read_iso_tx_sync(uint16_t handle, uint16_t *seq, } return BT_HCI_ERR_SUCCESS; + + } else if (IS_SYNC_ISO_HANDLE(handle)) { + return BT_HCI_ERR_CMD_DISALLOWED; } return BT_HCI_ERR_UNKNOWN_CONN_ID; diff --git a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c index d4df9257924..f6560ab397a 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c +++ b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c @@ -454,10 +454,27 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_hdr *rx) /* Periodic Advertising Channel Map Indication */ ull_sync_chm_update(rx->handle, ptr, acad_len); +#if defined(CONFIG_BT_CTLR_SYNC_ISO) + struct ll_sync_set *sync_set; + struct pdu_big_info *bi; + uint8_t bi_size; + + sync_set = HDR_LLL2ULL(sync_lll); + + /* Provide encryption information for BIG sync creation */ + bi_size = ptr[PDU_ADV_DATA_HEADER_LEN_OFFSET] - + PDU_ADV_DATA_HEADER_TYPE_SIZE; + sync_set->enc = (bi_size == PDU_BIG_INFO_ENCRYPTED_SIZE); + + /* Store number of BISes in the BIG */ + bi = (void *)&ptr[PDU_ADV_DATA_HEADER_DATA_OFFSET]; + sync_set->num_bis = PDU_BIG_INFO_NUM_BIS_GET(bi); + /* Broadcast ISO synchronize */ - if (IS_ENABLED(CONFIG_BT_CTLR_SYNC_ISO) && sync_iso) { + if (sync_iso) { ull_sync_iso_setup(sync_iso, rx, ptr, acad_len); } +#endif /* CONFIG_BT_CTLR_SYNC_ISO */ } /* Do not ULL schedule auxiliary PDU reception if no aux pointer diff --git a/subsys/bluetooth/controller/ll_sw/ull_sync.c b/subsys/bluetooth/controller/ll_sw/ull_sync.c index 1d653748587..4c2bec76483 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_sync.c +++ b/subsys/bluetooth/controller/ll_sw/ull_sync.c @@ -201,6 +201,10 @@ uint8_t ll_sync_create(uint8_t options, uint8_t sid, uint8_t adv_addr_type, sync->skip = skip; sync->is_stop = 0U; +#if defined(CONFIG_BT_CTLR_SYNC_ISO) + sync->enc = 0U; +#endif /* CONFIG_BT_CTLR_SYNC_ISO */ + /* NOTE: Use timeout not zero to represent sync context used for sync * create. */ @@ -1492,7 +1496,6 @@ static struct pdu_cte_info *pdu_cte_info_get(struct pdu_adv *pdu) { struct pdu_adv_com_ext_adv *com_hdr; struct pdu_adv_ext_hdr *hdr; - uint8_t *dptr; com_hdr = &pdu->adv_ext_ind; hdr = &com_hdr->ext_hdr; @@ -1501,9 +1504,6 @@ static struct pdu_cte_info *pdu_cte_info_get(struct pdu_adv *pdu) return NULL; } - /* Skip flags in extended advertising header */ - dptr = hdr->data; - /* Make sure there are no fields that are not allowd for AUX_SYNC_IND and AUX_CHAIN_IND */ LL_ASSERT(!hdr->adv_addr); LL_ASSERT(!hdr->tgt_addr); diff --git a/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c b/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c index 00f6a2bea6f..50172cff8b1 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c +++ b/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c @@ -86,6 +86,7 @@ uint8_t ll_big_sync_create(uint8_t big_handle, uint16_t sync_handle, struct node_rx_hdr *node_rx; struct ll_sync_set *sync; struct lll_sync_iso *lll; + int8_t last_index; sync = ull_sync_is_enabled_get(sync_handle); if (!sync || sync->iso.sync_iso) { @@ -107,11 +108,29 @@ uint8_t ll_big_sync_create(uint8_t big_handle, uint16_t sync_handle, return BT_HCI_ERR_CMD_DISALLOWED; } - /* TODO: Check parameters */ + /* TODO: Check remaining parameters */ + + /* Check BIS indices */ + last_index = -1; + for (uint8_t i = 0U; i < num_bis; i++) { + /* Stream index must be in valid range and in ascending order */ + if (!IN_RANGE(bis[i], 0x01, 0x1F) || (bis[i] <= last_index)) { + return BT_HCI_ERR_INVALID_PARAM; + + } else if (bis[i] > sync->num_bis) { + return BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL; + } + last_index = bis[i]; + } + + /* Check if requested encryption matches */ + if (encryption != sync->enc) { + return BT_HCI_ERR_ENC_MODE_NOT_ACCEPTABLE; + } /* Check if free BISes available */ if (mem_free_count_get(stream_free) < num_bis) { - return BT_HCI_ERR_MEM_CAPACITY_EXCEEDED; + return BT_HCI_ERR_INSUFFICIENT_RESOURCES; } link_sync_estab = ll_rx_link_alloc(); diff --git a/subsys/bluetooth/controller/ll_sw/ull_sync_types.h b/subsys/bluetooth/controller/ll_sw/ull_sync_types.h index 81da8abd2b9..36532d76102 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_sync_types.h +++ b/subsys/bluetooth/controller/ll_sw/ull_sync_types.h @@ -57,6 +57,11 @@ struct ll_sync_set { uint8_t is_stop:1; /* sync terminate or cancel requested */ uint8_t sync_expire:3; /* countdown of 6 before fail to establish */ +#if defined(CONFIG_BT_CTLR_SYNC_ISO) + uint8_t enc : 1; + uint8_t num_bis : 5; +#endif /* CONFIG_BT_CTLR_SYNC_ISO */ + #if defined(CONFIG_BT_CTLR_CHECK_SAME_PEER_SYNC) uint8_t sid; #endif /* CONFIG_BT_CTLR_CHECK_SAME_PEER_SYNC */ From 5d054a7eb8fa7786e6459bf348e3ea1ff7208566 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 15 Mar 2024 00:12:13 +0100 Subject: [PATCH 0793/2402] Bluetooth: TMAP: Shell: Improve logging of role The role is a 16-bit value, and is best logged as %04X. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/shell/tmap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/subsys/bluetooth/audio/shell/tmap.c b/subsys/bluetooth/audio/shell/tmap.c index c4b73b7670a..d5e6ee4ae66 100644 --- a/subsys/bluetooth/audio/shell/tmap.c +++ b/subsys/bluetooth/audio/shell/tmap.c @@ -26,7 +26,7 @@ static int cmd_tmap_init(const struct shell *sh, size_t argc, char **argv) (BT_TMAP_BMR_SUPPORTED ? BT_TMAP_ROLE_BMR : 0U); int err; - shell_info(sh, "Registering TMAS with role: %u", role); + shell_info(sh, "Registering TMAS with role: 0x%04X", role); err = bt_tmap_register(role); if (err != 0) { @@ -45,7 +45,7 @@ static void tmap_discover_cb(enum bt_tmap_role role, struct bt_conn *conn, int e return; } - shell_print(ctx_shell, "tmap discovered for conn %p: role 0x%02x", conn, role); + shell_print(ctx_shell, "tmap discovered for conn %p: role 0x%04x", conn, role); } static const struct bt_tmap_cb tmap_cb = { From ba2b167a40d1f526c4e3d8d0e767bd452974bd65 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Wed, 28 Feb 2024 13:56:58 +0100 Subject: [PATCH 0794/2402] boards: nucleo_wba: Add flash partitions Add flash partitions which can be used with mcuboot. Signed-off-by: Erwan Gouriou --- boards/st/nucleo_wba52cg/nucleo_wba52cg.dts | 30 +++++++++++++++++++++ boards/st/nucleo_wba55cg/nucleo_wba55cg.dts | 23 +++++++++++++--- 2 files changed, 49 insertions(+), 4 deletions(-) diff --git a/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts b/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts index 67bc009bd8a..0c08acc0bfe 100644 --- a/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts +++ b/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts @@ -22,6 +22,7 @@ zephyr,shell-uart = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; }; leds: leds { @@ -138,3 +139,32 @@ stm32_lp_tick_source: &lptim1 { &rng { status = "okay"; }; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 DT_SIZE_K(448)>; + }; + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x00080000 DT_SIZE_K(448)>; + }; + scratch_partition: partition@f0000 { + label = "image-scratch"; + reg = <0x000f0000 DT_SIZE_K(16)>; + }; + storage_partition: partition@f4000 { + label = "storage"; + reg = <0x000f4000 DT_SIZE_K(48)>; + }; + }; +}; diff --git a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts index 3a2ad07c1b0..88dd4083209 100644 --- a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts +++ b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts @@ -23,6 +23,7 @@ zephyr,shell-uart = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; }; leds: leds { @@ -141,11 +142,25 @@ stm32_lp_tick_source: &lptim1 { #address-cells = <1>; #size-cells = <1>; - /* Last 16K of flash: Min 2 sectors */ - storage_partition: partition@f8000 { + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 DT_SIZE_K(448)>; + }; + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x00080000 DT_SIZE_K(448)>; + }; + scratch_partition: partition@f0000 { + label = "image-scratch"; + reg = <0x000f0000 DT_SIZE_K(16)>; + }; + storage_partition: partition@f4000 { label = "storage"; - reg = <0x000f8000 DT_SIZE_K(16)>; + reg = <0x000f4000 DT_SIZE_K(48)>; }; - }; }; From 94477c099c338278767fa8285562c51d82717894 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Tue, 12 Mar 2024 14:29:45 +0100 Subject: [PATCH 0795/2402] boards: st: nucleo_wba: Fix openocd configuration Using Zephyr SDK 0.16.5, openocd can be used to debug WBA based boards. Fix documentation and clean up board.cmake configuration for nucleo_wba52cg from a local configuration which shouldn't have been upstreamed Signed-off-by: Erwan Gouriou --- boards/st/nucleo_wba52cg/board.cmake | 3 --- .../st/nucleo_wba52cg/doc/nucleo_wba52cg.rst | 20 +------------------ boards/st/nucleo_wba55cg/board.cmake | 1 + .../st/nucleo_wba55cg/doc/nucleo_wba55cg.rst | 20 +------------------ 4 files changed, 3 insertions(+), 41 deletions(-) diff --git a/boards/st/nucleo_wba52cg/board.cmake b/boards/st/nucleo_wba52cg/board.cmake index 27c19f19b00..4ad8bc417ea 100644 --- a/boards/st/nucleo_wba52cg/board.cmake +++ b/boards/st/nucleo_wba52cg/board.cmake @@ -1,7 +1,4 @@ board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") -set(OPENOCD "/local/mcu/tools/openocd/src/openocd" CACHE FILEPATH "" FORCE) -set(OPENOCD_DEFAULT_PATH /local/mcu/tools/openocd/tcl) - include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst b/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst index cb72fdfb831..16439ab6dd0 100644 --- a/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst +++ b/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst @@ -225,29 +225,11 @@ Programming and Debugging Nucleo WBA52CG board includes an ST-LINK/V3 embedded debug tool interface. It could be used for flash and debug using either OpenOCD or STM32Cube ecosystem tools. -OpenOCD Support -=============== - -For now, openocd support is available only on upstream OpenOCD. You can check -`OpenOCD official Github mirror`_. -In order to use it, you should clone and compile it following usual README -guidelines. -Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in -:zephyr_file:`boards/st/nucleo_wba52cg/board.cmake` to point the build -to the paths of the OpenOCD binary and its scripts, before -including the common openocd.board.cmake file: - - .. code-block:: none - - set(OPENOCD "/src/openocd" CACHE FILEPATH "" FORCE) - set(OPENOCD_DEFAULT_PATH /tcl) - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - Flashing ======== STM32CubeProgrammer is configured as flashing tool by default. -If available OpenOCD could be used. Same process applies with both tools. +If available, OpenOCD could be used. Same process applies with both tools. Flashing an application to Nucleo WBA52CG ----------------------------------------- diff --git a/boards/st/nucleo_wba55cg/board.cmake b/boards/st/nucleo_wba55cg/board.cmake index 50f543d4e6a..4ad8bc417ea 100644 --- a/boards/st/nucleo_wba55cg/board.cmake +++ b/boards/st/nucleo_wba55cg/board.cmake @@ -1,3 +1,4 @@ board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst index 362d74f0e91..2423d6bc36a 100644 --- a/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst +++ b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst @@ -236,29 +236,11 @@ Programming and Debugging Nucleo WBA55CG board includes an ST-LINK/V3 embedded debug tool interface. It could be used for flash and debug using either OpenOCD or STM32Cube ecosystem tools. -OpenOCD Support -=============== - -For now, openocd support is available only on upstream OpenOCD. You can check -`OpenOCD official Github mirror`_. -In order to use it, you should clone and compile it following usual README -guidelines. -Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in -:zephyr_file:`boards/st/nucleo_wba55cg/board.cmake` to point the build -to the paths of the OpenOCD binary and its scripts, before -including the common openocd.board.cmake file: - - .. code-block:: none - - set(OPENOCD "/src/openocd" CACHE FILEPATH "" FORCE) - set(OPENOCD_DEFAULT_PATH /tcl) - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - Flashing ======== STM32CubeProgrammer is configured as flashing tool by default. -If available OpenOCD could be used. Same process applies with both tools. +If available, OpenOCD could be used. Same process applies with both tools. Flashing an application to Nucleo WBA55CG ----------------------------------------- From 20f747bb630b4ce9e84d5e3e7f525df19f33cc43 Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Wed, 13 Mar 2024 13:56:27 +0100 Subject: [PATCH 0796/2402] drivers: sensor: qdec_stm32: fix inverted polarity Use the Polarity member instead of the ActivityInput. Signed-off-by: Jeppe Odgaard --- drivers/sensor/qdec_stm32/qdec_stm32.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/sensor/qdec_stm32/qdec_stm32.c b/drivers/sensor/qdec_stm32/qdec_stm32.c index e00baedab33..ebb1f65e921 100644 --- a/drivers/sensor/qdec_stm32/qdec_stm32.c +++ b/drivers/sensor/qdec_stm32/qdec_stm32.c @@ -108,8 +108,8 @@ static int qdec_stm32_initialize(const struct device *dev) LL_TIM_ENCODER_StructInit(&init_props); if (dev_cfg->is_input_polarity_inverted) { - init_props.IC1ActiveInput = LL_TIM_IC_POLARITY_FALLING; - init_props.IC2ActiveInput = LL_TIM_IC_POLARITY_FALLING; + init_props.IC1Polarity = LL_TIM_IC_POLARITY_FALLING; + init_props.IC2Polarity = LL_TIM_IC_POLARITY_FALLING; } init_props.IC1Filter = dev_cfg->input_filtering_level * LL_TIM_IC_FILTER_FDIV1_N2; From f2d79470f3faaa53da5707ef766dfab8e7da234b Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 13 Mar 2024 13:43:31 +0100 Subject: [PATCH 0797/2402] Manifest: Update bsim to version v2.2 Which includes BLE coded phy support Signed-off-by: Alberto Escolar Piedras --- west.yml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/west.yml b/west.yml index 278266018cc..4dfc6142933 100644 --- a/west.yml +++ b/west.yml @@ -34,7 +34,7 @@ manifest: path: modules/lib/acpica - name: bsim repo-path: babblesim-manifest - revision: 384a091445c57b44ac8cbd18ebd245b47c71db94 + revision: 68f6282c6a7f54641b75f5f9fc953c85e272a983 path: tools/bsim groups: - babblesim @@ -42,21 +42,21 @@ manifest: remote: babblesim repo-path: base path: tools/bsim/components - revision: 19d62424c0802c6c9fc15528febe666e40f372a1 + revision: 4bd907be0b2abec3b31a23fd8ca98db2a07209d2 groups: - babblesim - name: babblesim_ext_2G4_libPhyComv1 remote: babblesim repo-path: ext_2G4_libPhyComv1 path: tools/bsim/components/ext_2G4_libPhyComv1 - revision: 9018113a362fa6c9e8f4b9cab9e5a8f12cc46b94 + revision: 93f5eba512c438b0c9ebc1b1a947517c865b3643 groups: - babblesim - name: babblesim_ext_2G4_phy_v1 remote: babblesim repo-path: ext_2G4_phy_v1 path: tools/bsim/components/ext_2G4_phy_v1 - revision: d47c6dd90035b41b14f6921785ccb7b8484868e2 + revision: 1ab9a884621d9ca719ef23536ca47d10494220c6 groups: - babblesim - name: babblesim_ext_2G4_channel_NtNcable @@ -77,14 +77,14 @@ manifest: remote: babblesim repo-path: ext_2G4_modem_magic path: tools/bsim/components/ext_2G4_modem_magic - revision: cb70771794f0bf6f262aa474848611c68ae8f1ed + revision: edfcda2d3937a74be0a59d6cd47e0f50183453da groups: - babblesim - name: babblesim_ext_2G4_modem_BLE_simple remote: babblesim repo-path: ext_2G4_modem_BLE_simple path: tools/bsim/components/ext_2G4_modem_BLE_simple - revision: 809ab073159c9ab6686c2fea5749b0702e0909f7 + revision: a38d2d24b04a6f970a225d1316047256ebf5a539 groups: - babblesim - name: babblesim_ext_2G4_device_burst_interferer @@ -105,7 +105,7 @@ manifest: remote: babblesim repo-path: ext_2G4_device_playback path: tools/bsim/components/ext_2G4_device_playback - revision: 85c645929cf1ce995d8537107d9dcbd12ed64036 + revision: abb48cd71ddd4e2a9022f4bf49b2712524c483e8 groups: - babblesim - name: babblesim_ext_libCryptov1 From 81ea7fc889d893e7f03874d4b91c6f59a374e0fc Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 13 Mar 2024 13:44:40 +0100 Subject: [PATCH 0798/2402] manifest: Update nRF hw models to latest * Update the HW models module to df94612a846b8b1da166d3e4e4273df54de02340 Including the following: * df94612 GPIO: Add test API to be notified on output changes * 0da9163 HW models: Use libUtil bs_create_folders_in_path * c7798a4 CodedPhy: Several fixes and added documentation * 534c8d4 RADIO: Move CCM decryption trigger to CRCEND * bde13fc RADIO: Preliminary Coded Phy support * ff2a79d RADIO: Refactored modulation selection * f3823e5 RADIO: Fix in Tx packet end time * d6ebdd9 RADIO: Refactored Address selection Signed-off-by: Alberto Escolar Piedras --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 4dfc6142933..7d5073e9e5a 100644 --- a/west.yml +++ b/west.yml @@ -295,7 +295,7 @@ manifest: groups: - tools - name: nrf_hw_models - revision: ffd0ddec0239a47739892f4e705e97b2285a8508 + revision: df94612a846b8b1da166d3e4e4273df54de02340 path: modules/bsim_hw_models/nrf_hw_models - name: open-amp revision: da78aea63159771956fe0c9263f2e6985b66e9d5 From b7787792f1207423e0e3c22dff26a8c317bb9207 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 7 Mar 2024 11:36:56 +0100 Subject: [PATCH 0799/2402] Bluetooth: Controller: Nordic HAL: Use HAL to configure Timer's CC Use the HAL always when setting the TIMERs CC registers, (also for coded Phy) to ensure things work properly for simulation. Signed-off-by: Alberto Escolar Piedras --- .../ll_sw/nordic/hal/nrf5/radio/radio.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c index b681fa67a14..71b8f3c4c79 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c @@ -752,8 +752,8 @@ void sw_switch(uint8_t dir_curr, uint8_t dir_next, uint8_t phy_curr, uint8_t fla #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE) if (dir_curr == SW_SWITCH_RX && end_evt_delay_en == END_EVT_DELAY_ENABLED && !(phy_curr & PHY_CODED)) { - SW_SWITCH_TIMER->CC[phyend_delay_cc] = - SW_SWITCH_TIMER->CC[cc] - RADIO_EVENTS_PHYEND_DELAY_US; + nrf_timer_cc_set(SW_SWITCH_TIMER, phyend_delay_cc, + SW_SWITCH_TIMER->CC[cc] - RADIO_EVENTS_PHYEND_DELAY_US); if (delay < SW_SWITCH_TIMER->CC[cc]) { nrf_timer_cc_set(SW_SWITCH_TIMER, phyend_delay_cc, (SW_SWITCH_TIMER->CC[phyend_delay_cc] - delay)); @@ -783,6 +783,7 @@ void sw_switch(uint8_t dir_curr, uint8_t dir_next, uint8_t phy_curr, uint8_t fla SW_SWITCH_TIMER_S2_EVTS_COMP(sw_tifs_toggle); uint32_t delay_s2; + uint32_t new_cc_s2_value; /* Calculate assuming reception on S2 coding scheme. */ delay_s2 = HAL_RADIO_NS2US_ROUND( @@ -790,13 +791,15 @@ void sw_switch(uint8_t dir_curr, uint8_t dir_next, uint8_t phy_curr, uint8_t fla flags_next) + hal_radio_rx_chain_delay_ns_get(phy_curr, 0)); - SW_SWITCH_TIMER->CC[cc_s2] = SW_SWITCH_TIMER->CC[cc]; + new_cc_s2_value = SW_SWITCH_TIMER->CC[cc]; - if (delay_s2 < SW_SWITCH_TIMER->CC[cc_s2]) { - SW_SWITCH_TIMER->CC[cc_s2] -= delay_s2; + if (delay_s2 < new_cc_s2_value) { + new_cc_s2_value -= delay_s2; } else { - SW_SWITCH_TIMER->CC[cc_s2] = 1; + new_cc_s2_value = 1; } + nrf_timer_cc_set(SW_SWITCH_TIMER, cc_s2, + new_cc_s2_value); /* Setup the Tx start for S2 using a dedicated compare, * setup a PPI to disable PPI group on that compare @@ -1527,7 +1530,7 @@ void radio_tmr_sample(void) nrf_timer_task_trigger(EVENT_TIMER, HAL_EVENT_TIMER_SAMPLE_TASK); tmr_sample_val = EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET]; - EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET] = cc; + nrf_timer_cc_set(EVENT_TIMER, HAL_EVENT_TIMER_SAMPLE_CC_OFFSET, cc); #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */ nrf_timer_task_trigger(EVENT_TIMER, HAL_EVENT_TIMER_SAMPLE_TASK); From 4442477d9301f8cee30b263acecb10736b334e0e Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 22 Feb 2024 15:56:21 +0100 Subject: [PATCH 0800/2402] Bluetooth: Controller: Add coded phy radio timings for nrf52_bsim Add Coded Phy radio timings for the nrf52_bsim Signed-off-by: Alberto Escolar Piedras --- .../nordic/hal/nrf5/radio/radio_sim_nrf52.h | 223 ++++++++++++++++++ .../nordic/hal/nrf5/radio/radio_sim_nrf5340.h | 208 ++++++++++++++++ 2 files changed, 431 insertions(+) diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf52.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf52.h index 1b8c1583547..9f78ae78b27 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf52.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf52.h @@ -64,6 +64,51 @@ HAL_RADIO_NS2US_ROUND( \ HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS) +/* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode) + * in microseconds for LE CODED PHY [S2]. + */ +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_FAST_NS 42000 +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_FAST_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_FAST_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode) + * in microseconds for LE 2M PHY [S2]. + */ +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_DEFAULT_NS 132000 +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_DEFAULT_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_DEFAULT_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE 2M PHY [S2]. + */ +/* 129.5 + 2.2 */ +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS 132000 +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_ROUND( \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode) + * in microseconds for LE CODED PHY [S8]. + */ +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_FAST_NS 42000 +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_FAST_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_FAST_NS) +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode) + * in microseconds for LE 2M PHY [S8]. + */ +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_DEFAULT_NS 122000 +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_DEFAULT_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_DEFAULT_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE 2M PHY [S8]. + */ + /* 129.5 + 2.2 */ +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS 132000 +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_ROUND( \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS) + /* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) * in microseconds for LE 1M PHY. */ @@ -108,6 +153,54 @@ HAL_RADIO_NS2US_CEIL(\ HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) + * in microseconds for LE Coded PHY [S2]. + */ +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_FAST_NS 40000 +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_FAST_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_FAST_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode) + * in microseconds for LE Coded PHY [S2]. + */ +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_DEFAULT_NS 120000 +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_DEFAULT_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_DEFAULT_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode + * and no HW TIFS auto-switch) in microseconds for LE Coded PHY [S2]. + */ +/* 129.5 + 0.2 */ +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS 130000 +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_CEIL( \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) + * in microseconds for LE Coded PHY [S8]. + */ +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_FAST_NS 40000 +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_FAST_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_FAST_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode) + * in microseconds for LE Coded PHY [S8]. + */ +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_DEFAULT_NS 120000 +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_DEFAULT_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_DEFAULT_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE Coded PHY [S8]. + */ +/* 129.5 + 0.2 */ +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS 130000 +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_CEIL( \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS) + + #define HAL_RADIO_NRF52833_TX_CHAIN_DELAY_NS 1000 #define HAL_RADIO_NRF52833_TX_CHAIN_DELAY_US \ HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52833_TX_CHAIN_DELAY_NS) @@ -120,6 +213,12 @@ #define HAL_RADIO_NRF52833_RX_CHAIN_DELAY_2M_US \ HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF52833_RX_CHAIN_DELAY_2M_NS) +#define HAL_RADIO_NRF52833_RX_CHAIN_DELAY_S2_US 30 +#define HAL_RADIO_NRF52833_RX_CHAIN_DELAY_S2_NS 30000 +#define HAL_RADIO_NRF52833_RX_CHAIN_DELAY_S8_US 30 +#define HAL_RADIO_NRF52833_RX_CHAIN_DELAY_S8_NS 30000 + + #if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) #define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_1M_US \ HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_1M_FAST_US @@ -131,6 +230,16 @@ #define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_2M_NS \ HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_2M_FAST_NS +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_US \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_FAST_US +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_NS \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_FAST_NS + +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_US \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_FAST_US +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_NS \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_FAST_NS + #define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_1M_US \ HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_1M_FAST_US #define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_1M_NS \ @@ -141,6 +250,16 @@ #define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_2M_NS \ HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_2M_FAST_NS +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_US \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_FAST_US +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_NS \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_FAST_NS + +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_US \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_FAST_US +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_NS \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_FAST_NS + #else /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ #if defined(CONFIG_BT_CTLR_TIFS_HW) #define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_1M_US \ @@ -153,6 +272,16 @@ #define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_2M_NS \ HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_2M_DEFAULT_NS +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_US \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_DEFAULT_US +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_NS \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_DEFAULT_NS + +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_US \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_DEFAULT_US +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_NS \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_DEFAULT_NS + #define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_1M_US \ HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_1M_DEFAULT_US #define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_1M_NS \ @@ -163,6 +292,16 @@ #define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_2M_NS \ HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_2M_DEFAULT_NS +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_US \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_DEFAULT_US +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_NS \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_DEFAULT_NS + +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_US \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_DEFAULT_US +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_NS \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_DEFAULT_NS + #else /* !CONFIG_BT_CTLR_TIFS_HW */ #define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_1M_US \ HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_US @@ -174,6 +313,16 @@ #define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_2M_NS \ HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_US \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_NS \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS + +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_US \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_NS \ + HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS + #define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_1M_US \ HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_US #define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_1M_NS \ @@ -183,6 +332,16 @@ HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_US #define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_2M_NS \ HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS + +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_US \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_NS \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS + +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_US \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_NS \ + HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS #endif /* !CONFIG_BT_CTLR_TIFS_HW */ #endif /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ @@ -213,6 +372,16 @@ static inline uint32_t hal_radio_phy_mode_get(uint8_t phy, uint8_t flags) case BIT(1): mode = RADIO_MODE_MODE_Ble_2Mbit; break; + +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + mode = RADIO_MODE_MODE_Ble_LR125Kbit; + } else { + mode = RADIO_MODE_MODE_Ble_LR500Kbit; + } + break; +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } return mode; @@ -296,6 +465,15 @@ static inline uint32_t hal_radio_tx_ready_delay_us_get(uint8_t phy, uint8_t flag return HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_1M_US; case BIT(1): return HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_2M_US; + +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_US; + } else { + return HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_US; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } } @@ -309,6 +487,16 @@ static inline uint32_t hal_radio_rx_ready_delay_us_get(uint8_t phy, uint8_t flag return HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_1M_US; case BIT(1): return HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_2M_US; + +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_US; + } else { + return HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_US; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ + } } @@ -330,6 +518,15 @@ static inline uint32_t hal_radio_rx_chain_delay_us_get(uint8_t phy, uint8_t flag return HAL_RADIO_NRF52833_RX_CHAIN_DELAY_1M_US; case BIT(1): return HAL_RADIO_NRF52833_RX_CHAIN_DELAY_2M_US; + +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52833_RX_CHAIN_DELAY_S8_US; + } else { + return HAL_RADIO_NRF52833_RX_CHAIN_DELAY_S2_US; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } } @@ -343,6 +540,15 @@ static inline uint32_t hal_radio_tx_ready_delay_ns_get(uint8_t phy, uint8_t flag return HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_1M_NS; case BIT(1): return HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_2M_NS; + +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S8_NS; + } else { + return HAL_RADIO_NRF52833_TXEN_TXIDLE_TX_S2_NS; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } } @@ -356,6 +562,14 @@ static inline uint32_t hal_radio_rx_ready_delay_ns_get(uint8_t phy, uint8_t flag return HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_1M_NS; case BIT(1): return HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_2M_NS; +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S8_NS; + } else { + return HAL_RADIO_NRF52833_RXEN_RXIDLE_RX_S2_NS; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } } @@ -377,5 +591,14 @@ static inline uint32_t hal_radio_rx_chain_delay_ns_get(uint8_t phy, uint8_t flag return HAL_RADIO_NRF52833_RX_CHAIN_DELAY_1M_NS; case BIT(1): return HAL_RADIO_NRF52833_RX_CHAIN_DELAY_2M_NS; + +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF52833_RX_CHAIN_DELAY_S8_NS; + } else { + return HAL_RADIO_NRF52833_RX_CHAIN_DELAY_S2_NS; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } } diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf5340.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf5340.h index c0cd88b30b0..101ace5d9e1 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf5340.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf5340.h @@ -75,6 +75,51 @@ HAL_RADIO_NS2US_ROUND( \ HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS) +/* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode) + * in microseconds for LE CODED PHY [S2]. + */ +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_FAST_NS 42000 +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_FAST_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_FAST_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode) + * in microseconds for LE 2M PHY [S2]. + */ +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NS 132000 +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE 2M PHY [S2]. + */ +/* 129.5 + 2.2 */ +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS 132000 +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_ROUND( \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode) + * in microseconds for LE CODED PHY [S8]. + */ +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_FAST_NS 42000 +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_FAST_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_FAST_NS) +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode) + * in microseconds for LE 2M PHY [S8]. + */ +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NS 122000 +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_US \ + HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NS) + +/* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE 2M PHY [S8]. + */ + /* 129.5 + 2.2 */ +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS 132000 +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_ROUND( \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS) + /* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) * in microseconds for LE 1M PHY. */ @@ -121,6 +166,52 @@ HAL_RADIO_NS2US_CEIL( \ HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS) +/* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) + * in microseconds for LE Coded PHY [S2]. + */ +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_FAST_NS 40000 +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_FAST_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_FAST_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode) + * in microseconds for LE Coded PHY [S2]. + */ +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NS 120000 +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode + * and no HW TIFS auto-switch) in microseconds for LE Coded PHY [S2]. + */ +/* 129.5 + 0.2 */ +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS 130000 +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_CEIL( \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode) + * in microseconds for LE Coded PHY [S8]. + */ +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_FAST_NS 40000 +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_FAST_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_FAST_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode) + * in microseconds for LE Coded PHY [S8]. + */ +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NS 120000 +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_US \ + HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NS) + +/* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode and + * no HW TIFS auto-switch) in microseconds for LE Coded PHY [S8]. + */ +/* 129.5 + 0.2 */ +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS 130000 +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_US \ + HAL_RADIO_NS2US_CEIL( \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS) + #define HAL_RADIO_NRF5340_TX_CHAIN_DELAY_NS 1000 #define HAL_RADIO_NRF5340_TX_CHAIN_DELAY_US \ HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF5340_TX_CHAIN_DELAY_NS) @@ -129,6 +220,10 @@ #define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_1M_NS 9000 #define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_2M_US 5 #define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_2M_NS 5000 +#define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S2_US 30 +#define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S2_NS 30000 +#define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S8_US 30 +#define HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S8_NS 30000 #if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST) #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_US \ @@ -141,6 +236,16 @@ #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_NS \ HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_FAST_NS +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_US \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_FAST_US +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_NS \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_FAST_NS + +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_US \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_FAST_US +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_NS \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_FAST_NS + #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_US \ HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_FAST_US #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_NS \ @@ -151,6 +256,16 @@ #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_NS \ HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_FAST_NS +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_US \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_FAST_US +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_NS \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_FAST_NS + +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_US \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_FAST_US +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_NS \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_FAST_NS + #else /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ #if defined(CONFIG_BT_CTLR_TIFS_HW) #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_US \ @@ -163,6 +278,16 @@ #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_NS \ HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_NS +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_US \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_US +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_NS \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NS + +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_US \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_US +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_NS \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NS + #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_US \ HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_US #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_NS \ @@ -173,6 +298,16 @@ #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_NS \ HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_NS +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_US \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_US +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_NS \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NS + +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_US \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_US +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_NS \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NS + #else /* !CONFIG_BT_CTLR_TIFS_HW */ #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_US \ HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_US @@ -184,6 +319,16 @@ #define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_NS \ HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_US \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_NS \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS + +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_US \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_NS \ + HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS + #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_US \ HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_US #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_NS \ @@ -194,6 +339,16 @@ #define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_NS \ HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_US \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_NS \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS + +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_US \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_US +#define HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_NS \ + HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS + #endif /* !CONFIG_BT_CTLR_TIFS_HW */ #endif /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */ @@ -345,6 +500,15 @@ static inline uint32_t hal_radio_tx_ready_delay_us_get(uint8_t phy, uint8_t flag return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_US; case BIT(1): return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_US; + +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_US; + } else { + return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_US; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } } @@ -358,6 +522,15 @@ static inline uint32_t hal_radio_rx_ready_delay_us_get(uint8_t phy, uint8_t flag return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_US; case BIT(1): return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_US; + +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_US; + } else { + return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_US; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } } @@ -379,6 +552,15 @@ static inline uint32_t hal_radio_rx_chain_delay_us_get(uint8_t phy, uint8_t flag return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_1M_US; case BIT(1): return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_2M_US; + +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S8_US; + } else { + return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S2_US; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } } @@ -392,6 +574,15 @@ static inline uint32_t hal_radio_tx_ready_delay_ns_get(uint8_t phy, uint8_t flag return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_1M_NS; case BIT(1): return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_2M_NS; + +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S8_NS; + } else { + return HAL_RADIO_NRF5340_TXEN_TXIDLE_TX_S2_NS; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } } @@ -405,6 +596,15 @@ static inline uint32_t hal_radio_rx_ready_delay_ns_get(uint8_t phy, uint8_t flag return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_1M_NS; case BIT(1): return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_2M_NS; + +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S8_NS; + } else { + return HAL_RADIO_NRF5340_RXEN_RXIDLE_RX_S2_NS; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } } @@ -427,5 +627,13 @@ static inline uint32_t hal_radio_rx_chain_delay_ns_get(uint8_t phy, uint8_t flag case BIT(1): return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_2M_NS; +#if defined(CONFIG_BT_CTLR_PHY_CODED) + case BIT(2): + if (flags & 0x01) { + return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S8_NS; + } else { + return HAL_RADIO_NRF5340_RX_CHAIN_DELAY_S2_NS; + } +#endif /* CONFIG_BT_CTLR_PHY_CODED */ } } From 84df9f5e71337b9e78f6ec7e836d1529b86b4dff Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 22 Feb 2024 16:01:22 +0100 Subject: [PATCH 0801/2402] nrf52_bsim: Enable CodedPhy support in DTS The RADIO HW model supports coded phy now, let's enable it. Signed-off-by: Alberto Escolar Piedras --- boards/native/nrf_bsim/nrf52_bsim.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/boards/native/nrf_bsim/nrf52_bsim.dts b/boards/native/nrf_bsim/nrf52_bsim.dts index d591c7920c6..bb6321c4d53 100644 --- a/boards/native/nrf_bsim/nrf52_bsim.dts +++ b/boards/native/nrf_bsim/nrf52_bsim.dts @@ -68,7 +68,6 @@ &radio { /* These features are not yet supported by the RADIO model */ /delete-property/ dfe-supported; - /delete-property/ ble-coded-phy-supported; }; &gpiote { From cf362a018c4d4cf6eeef94f8309028b600ad5abd Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 13 Mar 2024 13:54:31 +0100 Subject: [PATCH 0802/2402] nrf53_bsim: Enable CodedPhy support in DTS The RADIO HW model supports coded phy now, let's enable it. Signed-off-by: Alberto Escolar Piedras --- boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts index 7553a2cfc55..020003a7b99 100644 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts @@ -53,7 +53,6 @@ &radio { /* These features are not yet supported by the RADIO model */ /delete-property/ dfe-supported; - /delete-property/ ble-coded-phy-supported; }; &ieee802154 { From 4163ea02073e147269c268dda9522c54ee9f5b11 Mon Sep 17 00:00:00 2001 From: Samy Francelet Date: Wed, 13 Mar 2024 21:01:55 +0100 Subject: [PATCH 0803/2402] drivers: eswifi: Add option for maximum data size Default MAX_DATA_SIZE might be too small depending on application (e.g. handling the scan result with 12 APs detected) Added config option for MAX_DATA_SIZE and warning for the user Signed-off-by: Samy Francelet --- drivers/wifi/eswifi/Kconfig.eswifi | 8 ++++++++ drivers/wifi/eswifi/eswifi.h | 4 +--- drivers/wifi/eswifi/eswifi_core.c | 7 +++++++ 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/wifi/eswifi/Kconfig.eswifi b/drivers/wifi/eswifi/Kconfig.eswifi index e9337c2d786..76baee01da3 100644 --- a/drivers/wifi/eswifi/Kconfig.eswifi +++ b/drivers/wifi/eswifi/Kconfig.eswifi @@ -30,6 +30,14 @@ config WIFI_ESWIFI_BUS_UART endchoice +config WIFI_ESWIFI_MAX_DATA_SIZE + int "esWiFi message size" + default 1600 + range 500 4000 + help + This option sets the size of the esWiFi message buffer. + It can be increased to handle larger messages, like scan results. + config WIFI_ESWIFI_THREAD_PRIO int "esWiFi threads priority" default 2 diff --git a/drivers/wifi/eswifi/eswifi.h b/drivers/wifi/eswifi/eswifi.h index 447b4b2f3d4..54bf00f0f78 100644 --- a/drivers/wifi/eswifi/eswifi.h +++ b/drivers/wifi/eswifi/eswifi.h @@ -16,8 +16,6 @@ #include "eswifi_offload.h" -#define MAX_DATA_SIZE 1600 - #define AT_OK_STR "\r\nOK\r\n> " #define AT_OK_STR_LEN 8 #define AT_RSP_DELIMITER "\r\n" @@ -71,7 +69,7 @@ struct eswifi_dev { enum eswifi_request req; enum eswifi_role role; uint8_t mac[6]; - char buf[MAX_DATA_SIZE]; + char buf[CONFIG_WIFI_ESWIFI_MAX_DATA_SIZE]; struct k_mutex mutex; atomic_val_t mutex_owner; unsigned int mutex_depth; diff --git a/drivers/wifi/eswifi/eswifi_core.c b/drivers/wifi/eswifi/eswifi_core.c index 2ee8b597d1b..813f6496d13 100644 --- a/drivers/wifi/eswifi/eswifi_core.c +++ b/drivers/wifi/eswifi/eswifi_core.c @@ -141,6 +141,13 @@ int eswifi_at_cmd_rsp(struct eswifi_dev *eswifi, char *cmd, char **rsp) return -EIO; } + if (len >= CONFIG_WIFI_ESWIFI_MAX_DATA_SIZE) { + LOG_WRN("Buffer might be too small for response!"); + LOG_WRN("Data length %d", len); + LOG_WRN("See CONFIG_WIFI_ESWIFI_MAX_DATA_SIZE (in build: %d)", + CONFIG_WIFI_ESWIFI_MAX_DATA_SIZE); + } + /* * Check response, format should be "\r\n[DATA]\r\nOK\r\n>" * Data is in arbitrary format (not only ASCII) From 417747886c4aac46c96dd02b1a4ff8d8f2bba0a2 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Wed, 17 Jan 2024 16:02:54 -0800 Subject: [PATCH 0804/2402] tests: sprintf: Avoid buffer overrun fwrite parameters are "size_t size" and "size_t nmemb", when writing a string we should set sizeof(char) and len(string). The test is doing it wrongly and making the function read more memory than it should. Signed-off-by: Flavio Ceolin --- tests/lib/sprintf/src/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/lib/sprintf/src/main.c b/tests/lib/sprintf/src/main.c index 19859b0fc33..af22d97fadd 100644 --- a/tests/lib/sprintf/src/main.c +++ b/tests/lib/sprintf/src/main.c @@ -909,10 +909,10 @@ ZTEST(sprintf, test_fwrite) ret = fwrite("This 3", 0, 4, stdout); zassert_equal(ret, 0, "fwrite failed!"); - ret = fwrite("This 3", 4, 4, stdout); + ret = fwrite("This 3", 1, 4, stdout); zassert_equal(ret, 4, "fwrite failed!"); - ret = fwrite("This 3", 4, 4, stdin); + ret = fwrite("This 3", 1, 4, stdin); zassert_equal(ret, 0, "fwrite failed!"); } From 765a4eb0b805c4b6c558cbf23056f23338316953 Mon Sep 17 00:00:00 2001 From: Ren Chen Date: Wed, 7 Feb 2024 09:52:17 +0800 Subject: [PATCH 0805/2402] drivers: timer: it8xxx2: enhances the accuracy of hw cycle calculation This commit enhances the accuracy of hardware cycle calculation before setting the IT8xxx2 event timer. The next target cycle is calculated by the last, elapsed, and expected timeout ticks. And then, the difference in hardware cycles between the target cycle and the current cycle is set into the event timer. This increased accuracy effectively resolves the clock drift issue. Tested with: west build -p always -b it8xxx2_evb tests/kernel/timer/timer_api -T kernel.timer.tickless west build -p always -b it8xxx2_evb tests/kernel/timer/timer_behavior -T kernel.timer.timer Fixes #67474 #67833 Signed-off-by: Ruibin Chang Signed-off-by: Ren Chen --- drivers/timer/ite_it8xxx2_timer.c | 36 ++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/timer/ite_it8xxx2_timer.c b/drivers/timer/ite_it8xxx2_timer.c index 69d42790ac7..62ab394de2d 100644 --- a/drivers/timer/ite_it8xxx2_timer.c +++ b/drivers/timer/ite_it8xxx2_timer.c @@ -76,6 +76,9 @@ const int32_t z_sys_timer_irq_for_test = DT_IRQ_BY_IDX(DT_NODELABEL(timer), 5, i static struct k_spinlock lock; /* Last HW count that we called sys_clock_announce() */ static volatile uint32_t last_announced_hw_cnt; +/* Last system (kernel) elapse and ticks */ +static volatile uint32_t last_elapsed; +static volatile uint32_t last_ticks; enum ext_timer_raw_cnt { EXT_NOT_RAW_CNT = 0, @@ -194,6 +197,8 @@ static void evt_timer_isr(const void *unused) uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)) - last_announced_hw_cnt) / HW_CNT_PER_SYS_TICK; last_announced_hw_cnt += (dticks * HW_CNT_PER_SYS_TICK); + last_ticks += dticks; + last_elapsed = 0; sys_clock_announce(dticks); } else { @@ -246,21 +251,26 @@ void sys_clock_set_timeout(int32_t ticks, bool idle) */ k_spin_unlock(&lock, key); return; - } else if (ticks <= 1) { - /* - * Ticks <= 1 means the kernel wants the tick announced - * as soon as possible, ideally no more than one system tick - * in the future. So set event timer count to 1 system tick or - * at least 1 hw count. - */ - hw_cnt = MAX((1 * HW_CNT_PER_SYS_TICK), 1); } else { + uint32_t next_cycs; + uint32_t now; + uint32_t dcycles; + /* - * Set event timer count to EVENT_TIMER_MAX_CNT, after - * interrupt fired the remaining time will be set again - * by sys_clock_announce(). + * If ticks <= 1 means the kernel wants the tick announced + * as soon as possible, ideally no more than one system tick + * in the future. So set event timer count to 1 HW tick. */ - hw_cnt = MIN((ticks * HW_CNT_PER_SYS_TICK), EVENT_TIMER_MAX_CNT); + ticks = CLAMP(ticks, 1, (int32_t)EVEN_TIMER_MAX_CNT_SYS_TICK); + + next_cycs = (last_ticks + last_elapsed + ticks) * HW_CNT_PER_SYS_TICK; + now = ~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)); + if (unlikely(next_cycs <= now)) { + hw_cnt = 1; + } else { + dcycles = next_cycs - now; + hw_cnt = MIN(dcycles, EVENT_TIMER_MAX_CNT); + } } /* Set event timer 24-bit count */ @@ -292,6 +302,8 @@ uint32_t sys_clock_elapsed(void) */ uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)) - last_announced_hw_cnt) / HW_CNT_PER_SYS_TICK; + last_elapsed = dticks; + k_spin_unlock(&lock, key); return dticks; From 8347abd001d17028943ad0e09e9c2a918bcc3c45 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 6 Mar 2024 11:55:54 -0600 Subject: [PATCH 0806/2402] drivers: counter: counter_nxp_mrt: include soc.h for MRT CMSIS defines Include soc.h in nxp MRT driver, so that CMSIS register definitions will be available in this file Signed-off-by: Daniel DeGrasse --- drivers/counter/counter_nxp_mrt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/counter/counter_nxp_mrt.c b/drivers/counter/counter_nxp_mrt.c index 741e7b34d40..209d0314b3e 100644 --- a/drivers/counter/counter_nxp_mrt.c +++ b/drivers/counter/counter_nxp_mrt.c @@ -21,6 +21,7 @@ #include #include #include +#include #define LOG_MODULE_NAME counter_mrt #include From ec5df8a0e5fb76c3d21db324c4204ad0e89a5213 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Tue, 5 Mar 2024 18:16:15 -0600 Subject: [PATCH 0807/2402] treewide: fix board identifier in overlays for lpcxpresso55s69 Fix board identifier in overlays for the lpcxpresso55s69_cpu0 target. Board identifiers were renamed with the following command: for file in $(find . -name "lpcxpresso55s69_cpu0.*"); do; mv $file ${file/_cpu0/_lpc55s69_cpu0}; done Additionally, remove lpcxpresso55s69_ns overlay targets where they are no longer needed (or rename them where they are) Signed-off-by: Daniel DeGrasse --- ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 .../boards/lpcxpresso55s69_ns.overlay | 27 -------------- ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 .../lpcxpresso55s69_lpc55s69_cpu0_ns.overlay | 36 ------------------- ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 ... lpcxpresso55s69_lpc55s69_cpu0_ns.overlay} | 0 ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 .../boards/lpcxpresso55s69_ns.overlay | 7 ---- ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 ...onf => lpcxpresso55s69_lpc55s69_cpu0.conf} | 0 ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 ...onf => lpcxpresso55s69_lpc55s69_cpu0.conf} | 0 ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 ...onf => lpcxpresso55s69_lpc55s69_cpu0.conf} | 0 ... => lpcxpresso55s69_lpc55s69_cpu0.overlay} | 0 15 files changed, 70 deletions(-) rename boards/shields/mikroe_eth_click/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) delete mode 100644 boards/shields/mikroe_eth_click/boards/lpcxpresso55s69_ns.overlay rename samples/drivers/adc/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) delete mode 100644 tests/drivers/adc/adc_api/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay rename tests/drivers/counter/counter_basic_api/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{lpcxpresso55s69_ns.overlay => lpcxpresso55s69_lpc55s69_cpu0_ns.overlay} (100%) rename tests/drivers/dma/loop_transfer/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) delete mode 100644 tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_ns.overlay rename tests/drivers/gpio/gpio_basic_api/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) rename tests/drivers/i2s/i2s_api/boards/{lpcxpresso55s69_cpu0.conf => lpcxpresso55s69_lpc55s69_cpu0.conf} (100%) rename tests/drivers/i2s/i2s_api/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) rename tests/drivers/i2s/i2s_speed/boards/{lpcxpresso55s69_cpu0.conf => lpcxpresso55s69_lpc55s69_cpu0.conf} (100%) rename tests/drivers/i2s/i2s_speed/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{lpcxpresso55s69_cpu0.conf => lpcxpresso55s69_lpc55s69_cpu0.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{lpcxpresso55s69_cpu0.overlay => lpcxpresso55s69_lpc55s69_cpu0.overlay} (100%) diff --git a/boards/shields/mikroe_eth_click/boards/lpcxpresso55s69_cpu0.overlay b/boards/shields/mikroe_eth_click/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from boards/shields/mikroe_eth_click/boards/lpcxpresso55s69_cpu0.overlay rename to boards/shields/mikroe_eth_click/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/boards/shields/mikroe_eth_click/boards/lpcxpresso55s69_ns.overlay b/boards/shields/mikroe_eth_click/boards/lpcxpresso55s69_ns.overlay deleted file mode 100644 index 1b69e264f21..00000000000 --- a/boards/shields/mikroe_eth_click/boards/lpcxpresso55s69_ns.overlay +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (C) 2020, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/delete-node/ ð_click; - -&mikrobus_spi { - status = "okay"; - - cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>, - <&gpio1 1 GPIO_ACTIVE_LOW>, - <&gpio1 12 GPIO_ACTIVE_LOW>, - <&gpio1 26 GPIO_ACTIVE_LOW>; - - /* LPCXpresso55xxx boards all use SSEL1. */ - eth_click_mikroe_eth_click: eth_click@1 { - compatible = "microchip,enc28j60"; - reg = <0x1>; - full-duplex; - local-mac-address = [00 00 00 01 02 03]; - /* Errata B7/1 specifies min 8Mhz, 20MHz max according to RM */ - spi-max-frequency = <10000000>; - int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; /* INT */ - }; -}; diff --git a/samples/drivers/adc/boards/lpcxpresso55s69_cpu0.overlay b/samples/drivers/adc/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from samples/drivers/adc/boards/lpcxpresso55s69_cpu0.overlay rename to samples/drivers/adc/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/tests/drivers/adc/adc_api/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay b/tests/drivers/adc/adc_api/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay deleted file mode 100644 index 5d3877139e5..00000000000 --- a/tests/drivers/adc/adc_api/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay +++ /dev/null @@ -1,36 +0,0 @@ -/* - * SPDX-License-Identifier: Apache-2.0 - * - * Copyright (c) 2023 Benjamin Björnsson - */ - -#include - -/ { - zephyr,user { - io-channels = <&adc0 0>, <&adc0 4>; - }; -}; - -&adc0 { - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_EXTERNAL0"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - zephyr,input-positive = ; - }; - - channel@4 { - reg = <4>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_EXTERNAL0"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - zephyr,input-positive = ; - }; -}; diff --git a/tests/drivers/counter/counter_basic_api/boards/lpcxpresso55s69_cpu0.overlay b/tests/drivers/counter/counter_basic_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/lpcxpresso55s69_cpu0.overlay rename to tests/drivers/counter/counter_basic_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s69_ns.overlay b/tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s69_ns.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_cpu0.overlay b/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_cpu0.overlay rename to tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_ns.overlay b/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_ns.overlay deleted file mode 100644 index 5e4c6a1c43c..00000000000 --- a/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_ns.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2022 Kumar Gala - * - * SPDX-License-Identifier: Apache-2.0 - */ - -tst_dma0: &dma0 { }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s69_cpu0.overlay b/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s69_cpu0.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/tests/drivers/i2s/i2s_api/boards/lpcxpresso55s69_cpu0.conf b/tests/drivers/i2s/i2s_api/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from tests/drivers/i2s/i2s_api/boards/lpcxpresso55s69_cpu0.conf rename to tests/drivers/i2s/i2s_api/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/tests/drivers/i2s/i2s_api/boards/lpcxpresso55s69_cpu0.overlay b/tests/drivers/i2s/i2s_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from tests/drivers/i2s/i2s_api/boards/lpcxpresso55s69_cpu0.overlay rename to tests/drivers/i2s/i2s_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/tests/drivers/i2s/i2s_speed/boards/lpcxpresso55s69_cpu0.conf b/tests/drivers/i2s/i2s_speed/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/lpcxpresso55s69_cpu0.conf rename to tests/drivers/i2s/i2s_speed/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/tests/drivers/i2s/i2s_speed/boards/lpcxpresso55s69_cpu0.overlay b/tests/drivers/i2s/i2s_speed/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/lpcxpresso55s69_cpu0.overlay rename to tests/drivers/i2s/i2s_speed/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_cpu0.conf b/tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_cpu0.conf rename to tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_cpu0.overlay b/tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_cpu0.overlay rename to tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay From 868f0cdfecdd36adc42c46c69d0f80274fe2291f Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Tue, 5 Mar 2024 18:24:14 -0600 Subject: [PATCH 0808/2402] boards: update lpcxpresso55s69_cpu0 name in build commands Update lpcxpresso55s69_cpu0 (and ns target) names in build commands in the board documentation. Also, correct the documentation for dual core images on this part, as it was out of date. Signed-off-by: Daniel DeGrasse --- boards/nxp/lpcxpresso55s69/doc/index.rst | 32 +++++++------------ .../mikroe_wifi_bt_click/doc/index.rst | 2 +- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/boards/nxp/lpcxpresso55s69/doc/index.rst b/boards/nxp/lpcxpresso55s69/doc/index.rst index 449d80b7af6..c156de1efa3 100644 --- a/boards/nxp/lpcxpresso55s69/doc/index.rst +++ b/boards/nxp/lpcxpresso55s69/doc/index.rst @@ -335,13 +335,14 @@ see the following message in the terminal: .. code-block:: console ***** Booting Zephyr OS v1.14.0 ***** - Hello World! lpcxpresso55s69_cpu0 + Hello World! lpcxpresso55s69 Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| ---------------------------------------------------------------------- -The TF-M integration samples can be run using the ``lpcxpresso55s69_ns`` target. -To run we need to manually flash the resulting image (``tfm_merged.hex``) with -a J-Link as follows (reset and erase are for recovering a locked core): +The TF-M integration samples can be run using the +``lpcxpresso55s69/lpc55s69/cpu0/ns`` target. To run we need to manually flash +the resulting image (``tfm_merged.hex``) with a J-Link as follows +(reset and erase are for recovering a locked core): .. code-block:: console @@ -354,20 +355,11 @@ We need to reset the board manually after flashing the image to run this code. Building a dual-core image -------------------------- -The dual-core samples are run using ``lpcxpresso55s69_cpu0`` target, -``lpcxpresso55s69_cpu1`` will be automatically built and merged in a single -image when ``SECOND_CORE_MCUX`` is selected. -To run we need to manually flash the resulting image (``multicore.bin``) with a -J-Link as follows (reset and erase are for recovering a locked core): - - .. code-block:: console - - JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1 - J-Link>r - J-Link>erase - J-Link>loadfile build/multicore.bin - -We need to reset the board manually after flashing the image to run this code. +The dual-core samples are run using ``lpcxpresso55s69/lpc55s69/cpu0`` target. +Images built for ``lpcxpresso55s69/lpc55s69/cpu1`` will be loaded from flash +and executed on the second core when ``SECOND_CORE_MCUX`` is selected. For +an example of building for both cores with sysbuild, see +``samples/subsys/ipc/openamp/`` Debugging ========= @@ -377,7 +369,7 @@ Here is an example for the :ref:`hello_world` application. This example uses the .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: lpcxpresso55s69_cpu0 + :board: lpcxpresso55s69/lpc55s69/cpu0 :goals: debug Open a serial terminal, step through the application in your debugger, and you @@ -386,7 +378,7 @@ should see the following message in the terminal: .. code-block:: console ***** Booting Zephyr OS zephyr-v1.14.0 ***** - Hello World! lpcxpresso55s69_cpu0 + Hello World! lpcxpresso55s69 .. _LPC55S69 SoC Website: https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/high-efficiency-arm-cortex-m33-based-microcontroller-family:LPC55S6x diff --git a/boards/shields/mikroe_wifi_bt_click/doc/index.rst b/boards/shields/mikroe_wifi_bt_click/doc/index.rst index 8673caa4583..07ba1ce29b3 100644 --- a/boards/shields/mikroe_wifi_bt_click/doc/index.rst +++ b/boards/shields/mikroe_wifi_bt_click/doc/index.rst @@ -95,7 +95,7 @@ See the example below for lpcxpresso55s69 board using Mikrobus serial: .. zephyr-app-commands:: :zephyr-app: samples/net/wifi - :board: lpcxpresso55s69_cpu0 + :board: lpcxpresso55s69/lpc55s69/cpu0 :shield: mikroe_wifi_bt_click_mikrobus :goals: build flash From 3c68a20d7503752c31a447af4114676cb4cb4bf6 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Thu, 14 Mar 2024 11:30:19 -0500 Subject: [PATCH 0809/2402] boards: frdm_mcxn947: Move the GPIO button nodes to the common file Move the GPIO button dts nodes to the common dts file so it be selected by either cpu core. Also fix an error in the GPIO setting for one of the switches. Signed-off-by: Mahesh Mahadevan --- boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 16 ++++++++++++++ .../frdm_mcxn947_mcxn947_cpu0.dts | 21 ++++--------------- 2 files changed, 20 insertions(+), 17 deletions(-) diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 5b8f52568de..b7b0f94207d 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -11,6 +11,8 @@ led0 = &red_led; led1 = &green_led; led2 = &blue_led; + sw0 = &user_button_2; + sw1 = &user_button_3; }; leds { @@ -31,6 +33,20 @@ status = "disabled"; }; }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_2: button_0 { + label = "User SW2"; + gpios = <&gpio0 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + status = "disabled"; + }; + user_button_3: button_1 { + label = "User SW3"; + gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + status = "disabled"; + }; + }; }; &flexcomm4_lpuart4 { diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts index ebbf77d32fe..331bacf00e6 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts @@ -17,11 +17,6 @@ /delete-node/ cpu@1; }; - aliases{ - sw0 = &user_button_3; - sw1 = &user_button_2; - }; - chosen { zephyr,sram = &sram0; zephyr,flash = &flash; @@ -29,18 +24,6 @@ zephyr,console = &flexcomm4_lpuart4; zephyr,shell-uart = &flexcomm4_lpuart4; }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_2: button_0 { - label = "User SW2"; - gpios = <&gpio0 29 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - }; - user_button_3: button_1 { - label = "User SW3"; - gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - }; - }; }; /* @@ -77,6 +60,10 @@ status = "okay"; }; +&user_button_2 { + status = "okay"; +}; + &flexcomm4 { status = "okay"; }; From e807b7e1c2f261a30e349a8bd297f36ef6f862bb Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 15 Mar 2024 17:15:14 +0100 Subject: [PATCH 0810/2402] samples/basic/hash_map: Remove clarification sentence This current sentence would need to be clarified a bit further to be really correct: It is only when building with the host C library that it applies, but with native_sim we can build with other libC's. The twister tests definitions are testing only with embedded C libraries, and there is anyway no harm if somebody defines the heap size even if using the host libC. So as such it would seem better to just remove this sentence. Signed-off-by: Alberto Escolar Piedras --- samples/basic/hash_map/Kconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/samples/basic/hash_map/Kconfig b/samples/basic/hash_map/Kconfig index 36ea3306392..f6f1aa0e836 100644 --- a/samples/basic/hash_map/Kconfig +++ b/samples/basic/hash_map/Kconfig @@ -18,9 +18,6 @@ config TEST_LIB_HASH_MAP_MAX_ENTRIES CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE - For native_sim, the number of entries can be configured - independently of the arena size since the native libc is used. - config TEST_LIB_HASH_MAP_DURATION_S int "Duration of test (in seconds)" default 3 From ee4131afc10b236d66e227dcf75d71f8c5d1e8e8 Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Thu, 14 Mar 2024 18:04:09 +0800 Subject: [PATCH 0811/2402] tests: gpio_basic_api: change imx93 evk board name Updated according to hardware model v2 board name changes. Signed-off-by: Jiafei Pan --- .../{mimx93_evk_a55.overlay => imx93_evk_mimx9352_a55.overlay} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename tests/drivers/gpio/gpio_basic_api/boards/{mimx93_evk_a55.overlay => imx93_evk_mimx9352_a55.overlay} (100%) diff --git a/tests/drivers/gpio/gpio_basic_api/boards/mimx93_evk_a55.overlay b/tests/drivers/gpio/gpio_basic_api/boards/imx93_evk_mimx9352_a55.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/mimx93_evk_a55.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/imx93_evk_mimx9352_a55.overlay From c2447d4230aac5eaa4fd1295b13773dce4802a18 Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Fri, 15 Mar 2024 16:23:05 +0800 Subject: [PATCH 0812/2402] boards: imx93_evk: add led1 alias So that it can be used to run basic thread sample application. Signed-off-by: Jiafei Pan --- boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts index a519801e875..6cd176d0ce3 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts @@ -31,6 +31,7 @@ aliases { led0 = &led_r; + led1 = &led_g; sw0 = &btn_1; }; From 774aa3605f571b9f8fadc4e88d50bdd4222f7a2f Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Fri, 15 Mar 2024 08:31:09 +0000 Subject: [PATCH 0813/2402] boards: lairdconnect: bl5340_dvk: Fix file name Fixes an wrong file name for a file that had been renamed as part of the hwmv2 port Signed-off-by: Jamie McCrae --- boards/lairdconnect/bl5340_dvk/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/lairdconnect/bl5340_dvk/CMakeLists.txt b/boards/lairdconnect/bl5340_dvk/CMakeLists.txt index ab8867f56a4..3c648fe1afa 100644 --- a/boards/lairdconnect/bl5340_dvk/CMakeLists.txt +++ b/boards/lairdconnect/bl5340_dvk/CMakeLists.txt @@ -5,7 +5,7 @@ if((CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS) AND CONFIG_BOARD_ENABLE_CPUNET) zephyr_library() - zephyr_library_sources(bl5340_dvk_cpunet_reset.c) + zephyr_library_sources(bl5340_dvk_nrf5340_cpunet_reset.c) if(CONFIG_BUILD_WITH_TFM) zephyr_library_include_directories( From fa6e894e1d2e3e536572f8add198823d825564df Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Wed, 13 Mar 2024 16:44:48 -0500 Subject: [PATCH 0814/2402] soc: nxp: rw: Clock SPI Flexcomms Clock flexcomms if used as SPI Signed-off-by: Declan Snyder --- soc/nxp/rw/soc.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c index 4f509ef5425..75b2cf58956 100644 --- a/soc/nxp/rw/soc.c +++ b/soc/nxp/rw/soc.c @@ -159,6 +159,28 @@ __ramfunc void clock_init(void) CLOCK_AttachClk(kFRG_to_FLEXCOMM14); #endif +/* Clock flexcomms when used as SPI */ +#ifdef CONFIG_SPI +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_spi, okay)) + /* Set up Flexcomm0 FRG to clock at 260 MHz from main clock */ + const clock_frg_clk_config_t flexcomm0_frg = {0, kCLOCK_FrgMainClk, 255, 0}; + + CLOCK_SetFRGClock(&flexcomm0_frg); + CLOCK_AttachClk(kFRG_to_FLEXCOMM0); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_spi, okay)) + CLOCK_AttachClk(kSFRO_to_FLEXCOMM1); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_spi, okay)) + CLOCK_AttachClk(kSFRO_to_FLEXCOMM2); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_spi, okay)) + CLOCK_AttachClk(kSFRO_to_FLEXCOMM3); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm14), nxp_lpc_spi, okay)) + CLOCK_AttachClk(kSFRO_to_FLEXCOMM14); +#endif +#endif /* CONFIG_SPI */ } /** From ba1ab8cc5e575feaf9e77ae684fa9965758a6985 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Wed, 13 Mar 2024 16:45:18 -0500 Subject: [PATCH 0815/2402] boards: rd_rw612_bga: Enable FC0 as SPI Enable flexcomm0 as SPI on rd_rw612_bga Signed-off-by: Declan Snyder --- boards/nxp/rd_rw612_bga/doc/index.rst | 2 ++ boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi | 10 ++++++++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 9 +++++++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml | 1 + 4 files changed, 22 insertions(+) diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index 0c6d81c3057..782fdd66175 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -39,6 +39,8 @@ Supported Features +-----------+------------+-----------------------------------+ | USART | on-chip | serial | +-----------+------------+-----------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-----------------------------------+ The default configuration can be found in the defconfig file: diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi index c9b0bcb8984..23ae103c891 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi @@ -13,4 +13,14 @@ slew-rate = "normal"; }; }; + + pinmux_flexcomm0_spi: pinmux_flexcomm0_spi { + group0 { + pinmux = , + , + , + ; + slew-rate = "ultra"; + }; + }; }; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index 810805bd6a9..49e86acb7d1 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -39,6 +39,15 @@ }; }; +arduino_spi: &flexcomm0 { + compatible = "nxp,lpc-spi"; + pinctrl-0 = <&pinmux_flexcomm0_spi>; + pinctrl-names = "default"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; +}; + &flexcomm3 { compatible = "nxp,lpc-usart"; status = "okay"; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml index ca3a4fd2de0..ac37d0a026e 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -16,3 +16,4 @@ ram: 960 flash: 65536 supported: - gpio + - spi From d1029da0899c83fa76c7ba797df94a4463375fc4 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Wed, 13 Mar 2024 16:45:53 -0500 Subject: [PATCH 0816/2402] tests: spi_loopback: Support rd_rw612_bga Add rd_rw612_bga to spi loopback test Signed-off-by: Declan Snyder --- .../spi_loopback/boards/rd_rw612_bga.overlay | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 tests/drivers/spi/spi_loopback/boards/rd_rw612_bga.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/rd_rw612_bga.overlay b/tests/drivers/spi/spi_loopback/boards/rd_rw612_bga.overlay new file mode 100644 index 00000000000..6877b199911 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/rd_rw612_bga.overlay @@ -0,0 +1,19 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Connect JP19 and J5 pins 4-5 */ +&flexcomm0 { + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <500000>; + }; + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = <16000000>; + }; +}; From 010f39a409e0e8cebc85ace58b98ea758f47edf9 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Wed, 13 Mar 2024 21:59:35 +0200 Subject: [PATCH 0817/2402] soc: intel_adsp_cavs: store PS when power gating secondary core When non-primary core is powered down and restart with sequence of: - PM state set to SOFT_OFF - once target core is idle, cut power with soc_adsp_halt_cpu() - power up core again with k_smp_cpu_resume() The execution will continue from stored DSP core context, but will hit an assert in z_smp_cpu_mobile() as the PS.INTLEVEL is zero. Fix this issue by storing and restoring PS register in this flow. Link: https://github.com/zephyrproject-rtos/zephyr/issues/70181 Signed-off-by: Kai Vehmanen --- soc/intel/intel_adsp/cavs/power.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/soc/intel/intel_adsp/cavs/power.c b/soc/intel/intel_adsp/cavs/power.c index fa4616e4ba3..be47f8dc109 100644 --- a/soc/intel/intel_adsp/cavs/power.c +++ b/soc/intel/intel_adsp/cavs/power.c @@ -58,6 +58,7 @@ struct core_state { uint32_t a1; uint32_t excsave2; uint32_t intenable; + uint32_t ps; }; static struct core_state core_desc[CONFIG_MP_MAX_NUM_CPUS] = {{0}}; @@ -83,6 +84,7 @@ static ALWAYS_INLINE void _save_core_context(void) { uint32_t core_id = arch_proc_id(); + core_desc[core_id].ps = XTENSA_RSR("PS"); core_desc[core_id].excsave2 = XTENSA_RSR(ZSR_CPU_STR); __asm__ volatile("mov %0, a0" : "=r"(core_desc[core_id].a0)); __asm__ volatile("mov %0, a1" : "=r"(core_desc[core_id].a1)); @@ -93,6 +95,7 @@ static ALWAYS_INLINE void _restore_core_context(void) { uint32_t core_id = arch_proc_id(); + XTENSA_WSR("PS", core_desc[core_id].ps); XTENSA_WSR(ZSR_CPU_STR, core_desc[core_id].excsave2); __asm__ volatile("mov a0, %0" :: "r"(core_desc[core_id].a0)); __asm__ volatile("mov a1, %0" :: "r"(core_desc[core_id].a1)); From 9395771d8bc37a00149266d8cb988d6b660adc80 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 11:41:04 +0100 Subject: [PATCH 0818/2402] boards: doc: Fix dead links in Arduino Nicla Sense ME doc page MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Updated 3 dead (404) links in the doc page for Arduino Nicla Sense ME. Also uniformized indenting of sphinx links in the process. Signed-off-by: Benjamin Cabé --- boards/arduino/nicla_sense_me/doc/index.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/arduino/nicla_sense_me/doc/index.rst b/boards/arduino/nicla_sense_me/doc/index.rst index f7c2b005c17..6a6eb3a0d1b 100644 --- a/boards/arduino/nicla_sense_me/doc/index.rst +++ b/boards/arduino/nicla_sense_me/doc/index.rst @@ -131,13 +131,13 @@ References .. target-notes:: .. _Arduino Nicla Sense ME: - https://docs.arduino.cc/hardware/nicla-sense-me + https://docs.arduino.cc/hardware/nicla-sense-me .. _datasheet: https://docs.arduino.cc/resources/datasheets/ABX00050-datasheet.pdf .. _full pinout: - https://docs.arduino.cc/static/b35956b631d757a0455c286da441641b/ABX00050-full-pinout.pdf + https://docs.arduino.cc/resources/pinouts/ABX00050-full-pinout.pdf .. _schematics: - https://docs.arduino.cc/static/ebd652e859efba8536a7e275c79d5f79/ABX00050-schematics.pdf + https://docs.arduino.cc/resources/schematics/ABX00050-schematics.pdf From 910ec65b0d0358a1a961ae9cd37eafc54efe664d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 11:41:06 +0100 Subject: [PATCH 0819/2402] boards: Fix dead link in Laird Connectivity Sentrius BT610 Sensor page MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix dead link to Sentrius™ BT610 Thermistor Coefficient Calculator page. Signed-off-by: Benjamin Cabé --- boards/lairdconnect/bt610/doc/bt610.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/lairdconnect/bt610/doc/bt610.rst b/boards/lairdconnect/bt610/doc/bt610.rst index 25798b12810..168153b5e26 100644 --- a/boards/lairdconnect/bt610/doc/bt610.rst +++ b/boards/lairdconnect/bt610/doc/bt610.rst @@ -612,4 +612,4 @@ References .. _TI TMUX1204 datasheet: https://www.ti.com/lit/gpn/TMUX1204 .. _TI TCA9538 datasheet: https://www.ti.com/lit/gpn/TCA9538 .. _Macronix MX25R6435FZNIL0 datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7913/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.5.pdf -.. _BT610 Zephyr Application Thermistor Calibration: https://www.lairdconnect.com/documentation/application-note-bt610-zephyr-application-thermistor-calibration +.. _BT610 Zephyr Application Thermistor Calibration: https://www.lairdconnect.com/technology/bt610-thermistor-coefficient-calculator From 8190fb6257eabf49081628bd44aa1e757a33b615 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 11:41:07 +0100 Subject: [PATCH 0820/2402] boards: doc: fix dead link to Keyestudio CAN-BUS Shield page MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix an HTTP 404 for the link to Keyestudio CAN-BUS Shield product page. Signed-off-by: Benjamin Cabé --- boards/shields/mcp2515/doc/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/shields/mcp2515/doc/index.rst b/boards/shields/mcp2515/doc/index.rst index 70082c0b9cc..c989f05368a 100644 --- a/boards/shields/mcp2515/doc/index.rst +++ b/boards/shields/mcp2515/doc/index.rst @@ -374,7 +374,7 @@ example: https://www.microchip.com/en-us/product/MCP2515 .. _Keyestudio Website: - https://www.keyestudio.com/products/2019new-keyestudio-can-bus-shield-mcp2551-chip-with-sd-socket-for-arduino-uno-r3 + https://www.keyestudio.com/2019new-keyestudio-can-bus-shield-mcp2551-chip-with-sd-socket-for-arduino-uno-r3-p0543.html .. _Keyestudio Wiki: https://wiki.keyestudio.com/KS0411_keyestudio_CAN-BUS_Shield From 8f09325e4a8ea77bdbeff0bac68b03ebd011e9c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 11:41:07 +0100 Subject: [PATCH 0821/2402] doc: boards: Update E73-TBB product page link MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit E73-TBB board now lives at cdebyte.com. Fixes #67099. Signed-off-by: Benjamin Cabé --- boards/ebyte/e73_tbb/doc/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/ebyte/e73_tbb/doc/index.rst b/boards/ebyte/e73_tbb/doc/index.rst index f05a3454b6e..7f18da86159 100644 --- a/boards/ebyte/e73_tbb/doc/index.rst +++ b/boards/ebyte/e73_tbb/doc/index.rst @@ -218,5 +218,5 @@ References .. target-notes:: -.. _E73-TBB website: https://www.ebyte.com/en/product-view-news.html?id=889 +.. _E73-TBB website: https://www.cdebyte.com/products/E73-TBB .. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com From c75b99e96353f94d38887012749ef7006fdd927e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 11:44:32 +0100 Subject: [PATCH 0822/2402] doc: boards: update links to DWM1001 web page MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This board's docs are now to be found on Qorvo website, update links accordingly. Originally reported in #67099. Signed-off-by: Benjamin Cabé --- boards/qorvo/decawave_dwm1001_dev/doc/index.rst | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/boards/qorvo/decawave_dwm1001_dev/doc/index.rst b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst index 55fa3f681fc..4699de8c381 100644 --- a/boards/qorvo/decawave_dwm1001_dev/doc/index.rst +++ b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst @@ -11,8 +11,9 @@ connector and charging circuit, LEDs, buttons, Raspberry-Pi and USB connector. In addition, the board comes with J-Link OB adding debugging and Virtual COM Port capabilities. -See `Decawave DWM1001-DEV website`_ for more information about the development -board, `Decawave DWM1001 website`_ about the board itself, and `nRF52832 website`_ for the official reference on the IC itself. +See `Qorvo (Decawave) DWM1001-DEV website`_ for more information about the development +board, `Qorvo (Decawave) DWM1001 website`_ about the board itself, and `nRF52832 website`_ for the +official reference on the IC itself. Programming and Debugging ************************* @@ -53,5 +54,5 @@ References .. target-notes:: .. _nRF52832 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52832 -.. _Decawave DWM1001 website: https://www.decawave.com/product/dwm1001-module -.. _Decawave DWM1001-DEV website: https://www.decawave.com/product/dwm1001-development-board +.. _Qorvo (Decawave) DWM1001 website: https://www.qorvo.com/products/p/DWM1001C +.. _Qorvo (Decawave) DWM1001-DEV website: https://www.qorvo.com/products/p/DWM1001-DEV From 72a36668dba9c23d63d6149bec2b43cc85cd82df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 11:45:37 +0100 Subject: [PATCH 0823/2402] doc: boards: acn52832 remove 404 link MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Aconno doesn't seem to be around anymore. Remove deadlink to product page. Issue originally reported in #67099 Signed-off-by: Benjamin Cabé --- boards/aconno/acn52832/doc/index.rst | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/boards/aconno/acn52832/doc/index.rst b/boards/aconno/acn52832/doc/index.rst index d40bc402f16..ff0c98cd91a 100644 --- a/boards/aconno/acn52832/doc/index.rst +++ b/boards/aconno/acn52832/doc/index.rst @@ -23,8 +23,7 @@ nRF52832 ARM Cortex-M4F CPU and the following devices: * :abbr:`UART (Universal asynchronous receiver-transmitter)` * :abbr:`WDT (Watchdog Timer)` -See `acn52832 website`_ for more information about the board and `Nordic infocenter`_ for more -information about the SoC. +See `Nordic infocenter`_ for more information about the SoC. Hardware ******** @@ -130,5 +129,4 @@ References ********** .. target-notes:: -.. _acn52832 website: https://aconno.de/products/acn52832/ .. _Nordic infocenter: https://infocenter.nordicsemi.com/ From fd265dba614c655d1bc4561035d0e3c9ba603fa8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 13:38:00 +0100 Subject: [PATCH 0824/2402] doc: samples: use https URL for adt7420 sample MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit http://www.analog.com/adt7420 does not exist anymore nor redirect to https, so update the link to be https Signed-off-by: Benjamin Cabé --- samples/sensor/adt7420/README.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/samples/sensor/adt7420/README.rst b/samples/sensor/adt7420/README.rst index 762195bdcef..86b6ceea8c2 100644 --- a/samples/sensor/adt7420/README.rst +++ b/samples/sensor/adt7420/README.rst @@ -18,7 +18,7 @@ upper and lower window boundaries. References ********** - - ADT7420: http://www.analog.com/adt7420 + - ADT7420: https://www.analog.com/adt7420 Wiring ******* From e914c60ae1561d42070adebc5047b1ada65d6033 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 13:40:06 +0100 Subject: [PATCH 0825/2402] boards: intel_adsp: fix dead link MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Chromium OS disk format documentation has moved. Signed-off-by: Benjamin Cabé --- boards/intel/adsp/doc/chromebooks_adsp.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/intel/adsp/doc/chromebooks_adsp.rst b/boards/intel/adsp/doc/chromebooks_adsp.rst index a89d2b75881..b19dd483d38 100644 --- a/boards/intel/adsp/doc/chromebooks_adsp.rst +++ b/boards/intel/adsp/doc/chromebooks_adsp.rst @@ -408,7 +408,7 @@ Upstream documentation from which these instructions were drawn: This page has the best reference for the boot process: -http://www.chromium.org/chromium-os/chromiumos-design-docs/disk-format +https://www.chromium.org/chromium-os/developer-library/reference/device/disk-format This is great too, with an eye toward booting things other than ChromeOS: From 9da1390b55f4381d320be626fe776f5a9b8b125c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 13:42:31 +0100 Subject: [PATCH 0826/2402] asamples: drivers: ht16k33: fix product link MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update URL to product page to HTTPS & more recent version. Signed-off-by: Benjamin Cabé --- samples/drivers/ht16k33/README.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/samples/drivers/ht16k33/README.rst b/samples/drivers/ht16k33/README.rst index f0bde1a1079..a7e747f2f92 100644 --- a/samples/drivers/ht16k33/README.rst +++ b/samples/drivers/ht16k33/README.rst @@ -40,4 +40,4 @@ References .. target-notes:: -.. _Holtek HT16K33: http://www.holtek.com/productdetail/-/vg/HT16K33 +.. _Holtek HT16K33: https://www.holtek.com/page/vg/HT16K33A From 1015ae3d4fbcc0aa31f133e50ffbe0ea8a0fd35b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 13:48:31 +0100 Subject: [PATCH 0827/2402] doc: hwmv2: board_porting: fix broken links MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DTS files for FRDM-K64F and Hexiwear K64 have moved. Signed-off-by: Benjamin Cabé --- doc/hardware/porting/board_porting.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/hardware/porting/board_porting.rst b/doc/hardware/porting/board_porting.rst index 04ccc33bb1c..ebd8ca5e28c 100644 --- a/doc/hardware/porting/board_porting.rst +++ b/doc/hardware/porting/board_porting.rst @@ -448,8 +448,8 @@ This section contains concrete examples related to writing your board's devicetree. The FRDM-K64F and Hexiwear K64 board devicetrees are defined in -:zephyr_file:`frdm_k64fs.dts ` and -:zephyr_file:`hexiwear_k64.dts ` +:zephyr_file:`frdm_k64fs.dts ` and +:zephyr_file:`hexiwear_k64.dts ` respectively. Both boards have NXP SoCs from the same Kinetis SoC family, the K6X. From 12188e23629d840e144c1ce28dd2c928195b1e79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 13:50:46 +0100 Subject: [PATCH 0828/2402] boards: hwmv2: fix dead links for Laird Connect boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit typo in vendor name was causing dead links Signed-off-by: Benjamin Cabé --- boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst | 2 +- boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst | 2 +- boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst | 2 +- .../bl654_sensor_board/doc/bl654_sensor_board.rst | 2 +- boards/lairdconnect/bl654_usb/doc/bl654_usb.rst | 4 ++-- boards/lairdconnect/bt510/doc/bt510.rst | 2 +- boards/lairdconnect/bt610/doc/bt610.rst | 2 +- boards/lairdconnect/mg100/doc/index.rst | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-) diff --git a/boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst b/boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst index a0d6657d4c1..9acbb30d46e 100644 --- a/boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst +++ b/boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst @@ -260,7 +260,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/laird_connect/bl652_dvk/bl652_dvk.dts`. +:zephyr_file:`boards/lairdconnect/bl652_dvk/bl652_dvk.dts`. References ********** diff --git a/boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst b/boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst index 8e4c76b4d09..71270f6f4e8 100644 --- a/boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst +++ b/boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst @@ -167,7 +167,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/laird_connect/bl653_dvk/bl653_dvk.dts`. +:zephyr_file:`boards/lairdconnect/bl653_dvk/bl653_dvk.dts`. Using UART1 *********** diff --git a/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst b/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst index f4cbc11e332..79011edddf2 100644 --- a/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst +++ b/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst @@ -173,7 +173,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/laird_connect/bl654_dvk/bl654_dvk.dts`. +:zephyr_file:`boards/lairdconnect/bl654_dvk/bl654_dvk.dts`. References diff --git a/boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst b/boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst index b3114b2948f..c990c934952 100644 --- a/boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst +++ b/boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst @@ -238,7 +238,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/laird_connect/bl654_sensor_board/bl654_sensor_board.dts`. +:zephyr_file:`boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.dts`. References diff --git a/boards/lairdconnect/bl654_usb/doc/bl654_usb.rst b/boards/lairdconnect/bl654_usb/doc/bl654_usb.rst index d2fd722f504..3bb3139b615 100644 --- a/boards/lairdconnect/bl654_usb/doc/bl654_usb.rst +++ b/boards/lairdconnect/bl654_usb/doc/bl654_usb.rst @@ -105,7 +105,7 @@ Applications for the ``bl654_usb`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). The ``bl654_usb`` board cannot be used for debugging. The compatible BL654 DVK board can be used for development. Documentation can be found at the :ref:`bl654_dvk` -site and :zephyr_file:`boards/laird_connect/bl654_dvk/doc/bl654_dvk.rst` +site and :zephyr_file:`boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst` Flashing ======== @@ -175,7 +175,7 @@ the board is working properly with Zephyr: You can build and flash the example to make sure Zephyr is running correctly on your board. The LED definitions can be found in -:zephyr_file:`boards/laird_connect/bl654_usb/bl654_usb.dts`. +:zephyr_file:`boards/lairdconnect/bl654_usb/bl654_usb.dts`. References diff --git a/boards/lairdconnect/bt510/doc/bt510.rst b/boards/lairdconnect/bt510/doc/bt510.rst index cbee5deabb8..13459f69ea7 100644 --- a/boards/lairdconnect/bt510/doc/bt510.rst +++ b/boards/lairdconnect/bt510/doc/bt510.rst @@ -244,7 +244,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button, LED and sensor device definitions can be found in -:zephyr_file:`boards/laird_connect/bt510/bt510.dts`. +:zephyr_file:`boards/lairdconnect/bt510/bt510.dts`. References diff --git a/boards/lairdconnect/bt610/doc/bt610.rst b/boards/lairdconnect/bt610/doc/bt610.rst index 168153b5e26..baf9827e3d6 100644 --- a/boards/lairdconnect/bt610/doc/bt610.rst +++ b/boards/lairdconnect/bt610/doc/bt610.rst @@ -598,7 +598,7 @@ on the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button, LED and sensor device definitions can be found in -:zephyr_file:`boards/laird_connect/bt610/bt610.dts`. +:zephyr_file:`boards/lairdconnect/bt610/bt610.dts`. References diff --git a/boards/lairdconnect/mg100/doc/index.rst b/boards/lairdconnect/mg100/doc/index.rst index e89fb09cf0a..611f0db5465 100644 --- a/boards/lairdconnect/mg100/doc/index.rst +++ b/boards/lairdconnect/mg100/doc/index.rst @@ -231,7 +231,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/laird_connect/mg100/mg100.dts`. +:zephyr_file:`boards/lairdconnect/mg100/mg100.dts`. References ********** From 46ff3bd239503b0480990352f22c6f00e84777e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 13:55:21 +0100 Subject: [PATCH 0829/2402] boards: hwmv2: doc: fix dead links for Nordic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fixes a few broken links to Nordic DTS files Signed-off-by: Benjamin Cabé --- boards/nordic/nrf9160dk/doc/index.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/nordic/nrf9160dk/doc/index.rst b/boards/nordic/nrf9160dk/doc/index.rst index 0e8a3171a22..0527bbe00b5 100644 --- a/boards/nordic/nrf9160dk/doc/index.rst +++ b/boards/nordic/nrf9160dk/doc/index.rst @@ -250,7 +250,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/nordic_nrf/nrf9160dk/nrf9160dk_nrf9160_common.dtsi`. +:zephyr_file:`boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi`. .. _nrf9160dk_nrf52840: @@ -498,8 +498,8 @@ following: }; A few helper .dtsi files are provided in the directories -:zephyr_file:`boards/nordic_nrf/nrf9160dk/dts/nrf52840` and -:zephyr_file:`boards/nordic_nrf/nrf9160dk/dts/nrf9160`. They can serve as examples of +:zephyr_file:`boards/nordic/nrf9160dk/dts/nrf52840` and +:zephyr_file:`boards/nordic/nrf9160dk/dts/nrf9160`. They can serve as examples of how to configure and use the above routings. You can also include them from respective devicetree overlay files in your applications to conveniently configure the signal routing between nRF9160 and nRF52840 on the nRF9160 DK. From 0f0f2422d89eb7a9564e51f615fad80fb91cbd7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 13:57:06 +0100 Subject: [PATCH 0830/2402] doc: boards: hwmv2: fix dead link for rpi4b MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix typo in raspberrypi vendor name causing dead link Signed-off-by: Benjamin Cabé --- boards/raspberrypi/rpi_4b/doc/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/raspberrypi/rpi_4b/doc/index.rst b/boards/raspberrypi/rpi_4b/doc/index.rst index e31845fdea9..6f840ec55e5 100644 --- a/boards/raspberrypi/rpi_4b/doc/index.rst +++ b/boards/raspberrypi/rpi_4b/doc/index.rst @@ -35,7 +35,7 @@ hardware features: Other hardware features have not been enabled yet for this board. The default configuration can be found in -:zephyr_file:`boards/raspberry_pi/rpi_4b/rpi_4b_defconfig` +:zephyr_file:`boards/raspberrypi/rpi_4b/rpi_4b_defconfig` Programming and Debugging ************************* From 9bf13638a189cd152e738154db257993424fb8f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 13:59:59 +0100 Subject: [PATCH 0831/2402] doc: boards: hwmv2: fix dead links for Seeed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Seeed Studio boards live in boards/seeed so update file links accordingly. Signed-off-by: Benjamin Cabé --- boards/seeed/lora_e5_mini/doc/index.rst | 4 ++-- boards/seeed/seeeduino_xiao/doc/index.rst | 2 +- boards/seeed/wio_terminal/doc/index.rst | 2 +- boards/seeed/xiao_ble/doc/index.rst | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/boards/seeed/lora_e5_mini/doc/index.rst b/boards/seeed/lora_e5_mini/doc/index.rst index 0b4120f2c8c..7f36a92e7d6 100644 --- a/boards/seeed/lora_e5_mini/doc/index.rst +++ b/boards/seeed/lora_e5_mini/doc/index.rst @@ -102,8 +102,8 @@ Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in: -- :zephyr_file:`boards/seeed_studio/lora_e5_mini/lora_e5_mini_defconfig` -- :zephyr_file:`boards/seeed_studio/lora_e5_mini/lora_e5_mini.dts` +- :zephyr_file:`boards/seeed/lora_e5_mini/lora_e5_mini_defconfig` +- :zephyr_file:`boards/seeed/lora_e5_mini/lora_e5_mini.dts` Connections and IOs diff --git a/boards/seeed/seeeduino_xiao/doc/index.rst b/boards/seeed/seeeduino_xiao/doc/index.rst index 17033e22ff7..aa11b812c38 100644 --- a/boards/seeed/seeeduino_xiao/doc/index.rst +++ b/boards/seeed/seeeduino_xiao/doc/index.rst @@ -59,7 +59,7 @@ features: Other hardware features are not currently supported by Zephyr. The default configuration can be found in the Kconfig file -:zephyr_file:`boards/seeed_studio/seeeduino_xiao/seeeduino_xiao_defconfig`. +:zephyr_file:`boards/seeed/seeeduino_xiao/seeeduino_xiao_defconfig`. Connections and IOs =================== diff --git a/boards/seeed/wio_terminal/doc/index.rst b/boards/seeed/wio_terminal/doc/index.rst index e12212be4cc..73cef0f3c5b 100644 --- a/boards/seeed/wio_terminal/doc/index.rst +++ b/boards/seeed/wio_terminal/doc/index.rst @@ -92,7 +92,7 @@ The wio_terminal board configuration supports the following hardware features: Other hardware features are not currently supported by Zephyr. The default configuration can be found in the Kconfig file -:zephyr_file:`boards/seeed_studio/wio_terminal/wio_terminal_defconfig`. +:zephyr_file:`boards/seeed/wio_terminal/wio_terminal_defconfig`. Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. To use the RTC, set :kconfig:option:`CONFIG_CORTEX_M_SYSTICK=n` and set diff --git a/boards/seeed/xiao_ble/doc/index.rst b/boards/seeed/xiao_ble/doc/index.rst index a7f0778d3b3..eda1476149e 100644 --- a/boards/seeed/xiao_ble/doc/index.rst +++ b/boards/seeed/xiao_ble/doc/index.rst @@ -182,7 +182,7 @@ properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The LED definitions can be found in -:zephyr_file:`boards/seeed_studio/xiao_ble/xiao_ble_common.dtsi`. +:zephyr_file:`boards/seeed/xiao_ble/xiao_ble_common.dtsi`. Testing shell over USB in the XIAO BLE (Sense) ********************************************** From 5edd2b37f55583df638cf31df085d18d2dbbbe3a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 14:01:42 +0100 Subject: [PATCH 0832/2402] doc: boards: silabs: fix bad links MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix minor typos causing dead links Signed-off-by: Benjamin Cabé --- boards/silabs/efr32_radio/doc/brd4187c.rst | 2 +- boards/silabs/efr32mg_sltb004a/doc/index.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/silabs/efr32_radio/doc/brd4187c.rst b/boards/silabs/efr32_radio/doc/brd4187c.rst index 63f106bd072..f5a3cd808dd 100644 --- a/boards/silabs/efr32_radio/doc/brd4187c.rst +++ b/boards/silabs/efr32_radio/doc/brd4187c.rst @@ -97,7 +97,7 @@ means Pin number 2 on PORTA, as used in the board's datasheets and manuals. +-------+-------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig`` +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig` System Clock ============ diff --git a/boards/silabs/efr32mg_sltb004a/doc/index.rst b/boards/silabs/efr32mg_sltb004a/doc/index.rst index fb595bbc7a8..ae06df99fc5 100644 --- a/boards/silabs/efr32mg_sltb004a/doc/index.rst +++ b/boards/silabs/efr32mg_sltb004a/doc/index.rst @@ -83,7 +83,7 @@ The efr32mg_sltb004a board configuration supports the following hardware feature +-----------+------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig`` +:zephyr_file:`boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig` Other hardware features are currently not supported by the port. From 62d79c899b866789d6a8583ce39e339a04f453e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 14:04:11 +0100 Subject: [PATCH 0833/2402] doc: boards: hwmv2: fix dead links to u-blox DTS fils MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit U-Blox boards live in /boards/u-blox, not /boards/ublox This commit fixes bad links accordingly. Signed-off-by: Benjamin Cabé --- boards/u-blox/ubx_bmd300eval/doc/index.rst | 2 +- boards/u-blox/ubx_bmd330eval/doc/index.rst | 2 +- boards/u-blox/ubx_bmd340eval/doc/index.rst | 2 +- boards/u-blox/ubx_bmd345eval/doc/index.rst | 2 +- boards/u-blox/ubx_bmd360eval/doc/index.rst | 2 +- boards/u-blox/ubx_bmd380eval/doc/index.rst | 2 +- boards/u-blox/ubx_evkannab1/doc/index.rst | 2 +- boards/u-blox/ubx_evkninab1/doc/index.rst | 2 +- boards/u-blox/ubx_evkninab3/doc/index.rst | 2 +- boards/u-blox/ubx_evkninab4/doc/index.rst | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/boards/u-blox/ubx_bmd300eval/doc/index.rst b/boards/u-blox/ubx_bmd300eval/doc/index.rst index 43e8d1d9fe9..d1aea13208f 100644 --- a/boards/u-blox/ubx_bmd300eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd300eval/doc/index.rst @@ -387,7 +387,7 @@ There are 2 samples that allow you to test that the buttons You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions -can be found in :zephyr_file:`boards/ublox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts`. +can be found in :zephyr_file:`boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts`. References ********** diff --git a/boards/u-blox/ubx_bmd330eval/doc/index.rst b/boards/u-blox/ubx_bmd330eval/doc/index.rst index d23b576f8f5..3f065cfc6d2 100644 --- a/boards/u-blox/ubx_bmd330eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd330eval/doc/index.rst @@ -378,7 +378,7 @@ There are 2 samples that allow you to test that the buttons You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions -can be found in :zephyr_file:`boards/ublox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts`. +can be found in :zephyr_file:`boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts`. References ********** diff --git a/boards/u-blox/ubx_bmd340eval/doc/index.rst b/boards/u-blox/ubx_bmd340eval/doc/index.rst index bb1afcfa7fa..4e1fed4e8a1 100644 --- a/boards/u-blox/ubx_bmd340eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd340eval/doc/index.rst @@ -448,7 +448,7 @@ There are 2 samples that allow you to test that the buttons You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/ublox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts`. +:zephyr_file:`boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts`. Using UART1 *********** diff --git a/boards/u-blox/ubx_bmd345eval/doc/index.rst b/boards/u-blox/ubx_bmd345eval/doc/index.rst index e63507eb4fc..0bcb1d201da 100644 --- a/boards/u-blox/ubx_bmd345eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd345eval/doc/index.rst @@ -460,7 +460,7 @@ There are 2 samples that allow you to test that the buttons You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/ublox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts`. +:zephyr_file:`boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts`. Using UART1 *********** diff --git a/boards/u-blox/ubx_bmd360eval/doc/index.rst b/boards/u-blox/ubx_bmd360eval/doc/index.rst index 9ce29132c13..556620a1764 100644 --- a/boards/u-blox/ubx_bmd360eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd360eval/doc/index.rst @@ -376,7 +376,7 @@ There are 2 samples that allow you to test that the buttons You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions -can be found in :zephyr_file:`boards/ublox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts`. +can be found in :zephyr_file:`boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts`. References ********** diff --git a/boards/u-blox/ubx_bmd380eval/doc/index.rst b/boards/u-blox/ubx_bmd380eval/doc/index.rst index 1c89222536e..1547cfc301e 100644 --- a/boards/u-blox/ubx_bmd380eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd380eval/doc/index.rst @@ -445,7 +445,7 @@ There are 2 samples that allow you to test that the buttons You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/ublox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts`. +:zephyr_file:`boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts`. Using UART1 *********** diff --git a/boards/u-blox/ubx_evkannab1/doc/index.rst b/boards/u-blox/ubx_evkannab1/doc/index.rst index 88ed4f55113..f464ab5265b 100644 --- a/boards/u-blox/ubx_evkannab1/doc/index.rst +++ b/boards/u-blox/ubx_evkannab1/doc/index.rst @@ -150,7 +150,7 @@ and LEDs on the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/ublox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts`. +:zephyr_file:`boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts`. Note that the buttons on the EVK-ANNA-B1 are marked SW1 and SW2, which are named sw0 and sw1 in the dts file. diff --git a/boards/u-blox/ubx_evkninab1/doc/index.rst b/boards/u-blox/ubx_evkninab1/doc/index.rst index 9b296624ad8..9073c223585 100644 --- a/boards/u-blox/ubx_evkninab1/doc/index.rst +++ b/boards/u-blox/ubx_evkninab1/doc/index.rst @@ -158,7 +158,7 @@ and LEDs on the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/ublox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts`. +:zephyr_file:`boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts`. Note that the buttons on the EVK-NINA-B1 are marked SW1 and SW2, which are named sw0 and sw1 in the dts file. diff --git a/boards/u-blox/ubx_evkninab3/doc/index.rst b/boards/u-blox/ubx_evkninab3/doc/index.rst index 941c58eccd0..fb8b0159b34 100644 --- a/boards/u-blox/ubx_evkninab3/doc/index.rst +++ b/boards/u-blox/ubx_evkninab3/doc/index.rst @@ -261,7 +261,7 @@ There are 2 samples that allow you to test that the buttons You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/ublox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts`. +:zephyr_file:`boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts`. Using UART1 *********** diff --git a/boards/u-blox/ubx_evkninab4/doc/index.rst b/boards/u-blox/ubx_evkninab4/doc/index.rst index 872b778b7e3..5ad6289b590 100644 --- a/boards/u-blox/ubx_evkninab4/doc/index.rst +++ b/boards/u-blox/ubx_evkninab4/doc/index.rst @@ -153,7 +153,7 @@ and LEDs on the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/ublox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts`. +:zephyr_file:`boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts`. Note that the buttons on the EVK-NINA-B4 are marked SW1 and SW2, which are named sw0 and sw1 in the dts file. From 975ca7888ffb78f12da3a2875aacea6d260a369b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 14:16:52 +0100 Subject: [PATCH 0834/2402] doc: boards: hwmv2: fix dead links to Wurth Electronik DTS fils MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Wurth Electronik boards live in /boards/we, not /boards/wurth_elektronik This commit fixes bad links accordingly. Signed-off-by: Benjamin Cabé --- boards/we/proteus2ev/doc/index.rst | 2 +- boards/we/proteus3ev/doc/index.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/we/proteus2ev/doc/index.rst b/boards/we/proteus2ev/doc/index.rst index 7bdd621fd90..5492b4159fe 100644 --- a/boards/we/proteus2ev/doc/index.rst +++ b/boards/we/proteus2ev/doc/index.rst @@ -150,7 +150,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/wurth_elektronik/proteus2ev/we_proteus2ev_nrf52832.dts`. +:zephyr_file:`boards/we/proteus2ev/we_proteus2ev_nrf52832.dts`. References ********** diff --git a/boards/we/proteus3ev/doc/index.rst b/boards/we/proteus3ev/doc/index.rst index 59c5116d509..dd6c5f47d6c 100644 --- a/boards/we/proteus3ev/doc/index.rst +++ b/boards/we/proteus3ev/doc/index.rst @@ -151,7 +151,7 @@ LEDs on the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/wurth_elektronik/proteus3ev/we_proteus3ev_nrf52840.dts`. +:zephyr_file:`boards/we/proteus3ev/we_proteus3ev_nrf52840.dts`. References ********** From e7b6a08d8ffd3ef283dd5fa2b625896f1d443b54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 14:40:36 +0100 Subject: [PATCH 0835/2402] doc: soc: hwmv2: fix altera dead links MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fixing dead links to some Altera SoC files Signed-off-by: Benjamin Cabé --- boards/altr/max10/doc/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/altr/max10/doc/index.rst b/boards/altr/max10/doc/index.rst index 64d7f14257f..ca66d77a0a7 100644 --- a/boards/altr/max10/doc/index.rst +++ b/boards/altr/max10/doc/index.rst @@ -92,11 +92,11 @@ Reference CPU ============= A reference CPU design of a Nios II/f core is included in the Zephyr tree -in the :zephyr_file:`soc/altera/zephyr_nios2f/cpu` directory. +in the :zephyr_file:`soc/altr/zephyr_nios2f/cpu` directory. Flash this CPU using the ``nios2-configure-sof`` SDK tool with the FPGA configuration file -:zephyr_file:`soc/altera/zephyr_nios2f/cpu/ghrd_10m50da.sof`: +:zephyr_file:`soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof`: .. code-block:: console From 40d3ffa603d45a7f1357a045b08e190b1600c898 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 14:50:08 +0100 Subject: [PATCH 0836/2402] doc: fix double backticks in sphinx roles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fixed a few improperly formatted sphinx roles causing dead references. Signed-off-by: Benjamin Cabé --- boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst | 2 +- boards/st/nucleo_h723zg/doc/index.rst | 2 +- doc/connectivity/bluetooth/api/shell/cap.rst | 2 +- doc/connectivity/bluetooth/api/shell/csip.rst | 2 +- doc/develop/getting_started/index.rst | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst index 038666ad623..d7a261dbb5c 100644 --- a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst +++ b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst @@ -62,7 +62,7 @@ hardware features: Other hardware features have not been enabled yet for this board. The default configuration can be found in -:zephyr_file:`boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig`` +:zephyr_file:`boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig` Programming and Debugging ************************* diff --git a/boards/st/nucleo_h723zg/doc/index.rst b/boards/st/nucleo_h723zg/doc/index.rst index cce94294255..0c24a479920 100644 --- a/boards/st/nucleo_h723zg/doc/index.rst +++ b/boards/st/nucleo_h723zg/doc/index.rst @@ -119,7 +119,7 @@ features: Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig files: -:zephyr_file:`boards/st/nucleo_h723zg/nucleo_h723zg_defconfig`` +:zephyr_file:`boards/st/nucleo_h723zg/nucleo_h723zg_defconfig` For more details please refer to `STM32 Nucleo-144 board User Manual`_. diff --git a/doc/connectivity/bluetooth/api/shell/cap.rst b/doc/connectivity/bluetooth/api/shell/cap.rst index 255a1113484..a21bc52a74b 100644 --- a/doc/connectivity/bluetooth/api/shell/cap.rst +++ b/doc/connectivity/bluetooth/api/shell/cap.rst @@ -39,7 +39,7 @@ Setting a new SIRK ------------------ This command can modify the currently used SIRK. To get the new RSI to advertise on air, -:code:`bt adv-data`` or :code:`bt advertise` must be called again to set the new advertising data. +:code:`bt adv-data` or :code:`bt advertise` must be called again to set the new advertising data. If :code:`CONFIG_BT_CSIP_SET_MEMBER_NOTIFIABLE` is enabled, this will also notify connected clients. diff --git a/doc/connectivity/bluetooth/api/shell/csip.rst b/doc/connectivity/bluetooth/api/shell/csip.rst index f6de277cee3..c4efa0a6f93 100644 --- a/doc/connectivity/bluetooth/api/shell/csip.rst +++ b/doc/connectivity/bluetooth/api/shell/csip.rst @@ -169,7 +169,7 @@ Setting a new SIRK ------------------ This command can modify the currently used SIRK. To get the new RSI to advertise on air, -:code:`bt adv-data`` or :code:`bt advertise` must be called again to set the new advertising data. +:code:`bt adv-data` or :code:`bt advertise` must be called again to set the new advertising data. If :code:`CONFIG_BT_CSIP_SET_MEMBER_NOTIFIABLE` is enabled, this will also notify connected clients. diff --git a/doc/develop/getting_started/index.rst b/doc/develop/getting_started/index.rst index 39e68ba6a02..cbe67aade59 100644 --- a/doc/develop/getting_started/index.rst +++ b/doc/develop/getting_started/index.rst @@ -170,7 +170,7 @@ The current minimum required version for the main dependencies are: #. `Install chocolatey`_. #. Open a ``cmd.exe`` terminal window as **Administrator**. To do so, press the Windows key, - type ``cmd.exe``, right-click the :guilabel:`Command Prompt`` search result, and choose + type ``cmd.exe``, right-click the :guilabel:`Command Prompt` search result, and choose :guilabel:`Run as Administrator`. #. Disable global confirmation to avoid having to confirm the From b27ebd5b3d56c5cc1ee5c7aa1d50abcfef0754c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 15:09:59 +0100 Subject: [PATCH 0837/2402] doc: boards: hwmv2: fix dead links to Broadcom files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Broadcom boards live in /boards/brcm, not /boards/broadcom This commit fixes bad links accordingly. Signed-off-by: Benjamin Cabé --- boards/brcm/bcm958401m2/doc/index.rst | 2 +- boards/brcm/bcm958402m2/doc/a72.rst | 2 +- boards/brcm/bcm958402m2/doc/m7.rst | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/brcm/bcm958401m2/doc/index.rst b/boards/brcm/bcm958401m2/doc/index.rst index e053bc2ce05..494497f99f1 100644 --- a/boards/brcm/bcm958401m2/doc/index.rst +++ b/boards/brcm/bcm958401m2/doc/index.rst @@ -32,7 +32,7 @@ features: Other hardware features have not been enabled yet for this board. The default configuration can be found in -:zephyr_file:`boards/broadcom/bcm958401m2/bcm958401m2_defconfig` +:zephyr_file:`boards/brcm/bcm958401m2/bcm958401m2_defconfig` Connections and IOs =================== diff --git a/boards/brcm/bcm958402m2/doc/a72.rst b/boards/brcm/bcm958402m2/doc/a72.rst index 80fdd0ea4e5..b1c50d00788 100644 --- a/boards/brcm/bcm958402m2/doc/a72.rst +++ b/boards/brcm/bcm958402m2/doc/a72.rst @@ -32,7 +32,7 @@ hardware features: Other hardware features have not been enabled yet for this board. The default configuration can be found in -:zephyr_file:`boards/broadcom/bcm958402m2/bcm958402m2_bcm58402_a72_defconfig` +:zephyr_file:`boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72_defconfig` Programming and Debugging ************************* diff --git a/boards/brcm/bcm958402m2/doc/m7.rst b/boards/brcm/bcm958402m2/doc/m7.rst index 6edf1387964..aa9507a7926 100644 --- a/boards/brcm/bcm958402m2/doc/m7.rst +++ b/boards/brcm/bcm958402m2/doc/m7.rst @@ -32,7 +32,7 @@ hardware features: Other hardware features have not been enabled yet for this board. The default configuration can be found in -:zephyr_file:`boards/broadcom/bcm958402m2/bcm958402m2_bcm58402_m7_defconfig` +:zephyr_file:`boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7_defconfig` Programming and Debugging ************************* From e6990302cbc6c5a736cb07cb3db52592dc99c2ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 15:17:37 +0100 Subject: [PATCH 0838/2402] doc: hwmv2: boards: fix broken NXP links MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix bad links to some NXP board files (and make references actual "links") Signed-off-by: Benjamin Cabé --- boards/nxp/lpcxpresso11u68/doc/index.rst | 2 +- boards/nxp/lpcxpresso55s28/doc/index.rst | 2 +- boards/nxp/lpcxpresso55s69/doc/index.rst | 2 +- boards/nxp/mimxrt1010_evk/doc/index.rst | 2 +- boards/nxp/mimxrt1015_evk/doc/index.rst | 2 +- boards/nxp/mimxrt1020_evk/doc/index.rst | 2 +- boards/nxp/mimxrt1024_evk/doc/index.rst | 2 +- boards/nxp/mimxrt1040_evk/doc/index.rst | 2 +- boards/nxp/mimxrt1050_evk/doc/index.rst | 2 +- boards/nxp/mimxrt1060_evk/doc/index.rst | 2 +- boards/nxp/mimxrt1062_fmurt6/doc/index.rst | 2 +- boards/nxp/mimxrt1064_evk/doc/index.rst | 2 +- boards/nxp/mimxrt685_evk/doc/index.rst | 2 +- boards/nxp/vmu_rt1170/doc/index.rst | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/boards/nxp/lpcxpresso11u68/doc/index.rst b/boards/nxp/lpcxpresso11u68/doc/index.rst index 23198a359ea..244fb7427b0 100644 --- a/boards/nxp/lpcxpresso11u68/doc/index.rst +++ b/boards/nxp/lpcxpresso11u68/doc/index.rst @@ -109,7 +109,7 @@ probe (based on a NXP LPC43xx MCU). This MCU provides either a CMSIS-DAP or a J-Link interface. It depends on the embedded firmware image. The default OpenOCD configuration supports the CMSIS-DAP interface. If you want to switch to J-Link, then you need to edit the -``boards/arm/lpcxpresso11u68/support/openocd.cfg`` file and to replace:: +:zephyr_file:`boards/nxp/lpcxpresso11u68/support/openocd.cfg` file and to replace:: source [find interface/cmsis-dap.cfg] diff --git a/boards/nxp/lpcxpresso55s28/doc/index.rst b/boards/nxp/lpcxpresso55s28/doc/index.rst index 7750254d423..1e97071456f 100644 --- a/boards/nxp/lpcxpresso55s28/doc/index.rst +++ b/boards/nxp/lpcxpresso55s28/doc/index.rst @@ -88,7 +88,7 @@ already supported, which can also be re-used on this lpcxpresso55s28 board: Other hardware features are not currently enabled. The default configuration file -``boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig`` +:zephyr_file:`boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig` Connections and IOs =================== diff --git a/boards/nxp/lpcxpresso55s69/doc/index.rst b/boards/nxp/lpcxpresso55s69/doc/index.rst index c156de1efa3..1d909d18942 100644 --- a/boards/nxp/lpcxpresso55s69/doc/index.rst +++ b/boards/nxp/lpcxpresso55s69/doc/index.rst @@ -108,7 +108,7 @@ Targets available ================== The default configuration file -``boards/arm/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig`` +:zephyr_file:`boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig` only enables the first core. CPU0 is the only target that can run standalone. diff --git a/boards/nxp/mimxrt1010_evk/doc/index.rst b/boards/nxp/mimxrt1010_evk/doc/index.rst index df15589a0a8..7982b8c1e75 100644 --- a/boards/nxp/mimxrt1010_evk/doc/index.rst +++ b/boards/nxp/mimxrt1010_evk/doc/index.rst @@ -102,7 +102,7 @@ already supported, which can also be re-used on this mimxrt1010_evk board: +-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1010_evk/mimxrt1010_evk_defconfig`` +:zephyr_file:`boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig` Other hardware features are not currently supported by the port. diff --git a/boards/nxp/mimxrt1015_evk/doc/index.rst b/boards/nxp/mimxrt1015_evk/doc/index.rst index f7d6bc1db6e..6a08355ff00 100644 --- a/boards/nxp/mimxrt1015_evk/doc/index.rst +++ b/boards/nxp/mimxrt1015_evk/doc/index.rst @@ -100,7 +100,7 @@ already supported, which can also be re-used on this mimxrt1015_evk board: +-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig`` +:zephyr_file:`boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig` Other hardware features are not currently supported by the port. diff --git a/boards/nxp/mimxrt1020_evk/doc/index.rst b/boards/nxp/mimxrt1020_evk/doc/index.rst index 751ec16687b..5a05337264e 100644 --- a/boards/nxp/mimxrt1020_evk/doc/index.rst +++ b/boards/nxp/mimxrt1020_evk/doc/index.rst @@ -120,7 +120,7 @@ already supported, which can also be re-used on this mimxrt1020_evk board: +-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1020_evk/mimxrt1020_evk_defconfig`` +:zephyr_file:`boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig` Other hardware features are not currently supported by the port. diff --git a/boards/nxp/mimxrt1024_evk/doc/index.rst b/boards/nxp/mimxrt1024_evk/doc/index.rst index c04a3f5d090..76f0d329993 100644 --- a/boards/nxp/mimxrt1024_evk/doc/index.rst +++ b/boards/nxp/mimxrt1024_evk/doc/index.rst @@ -125,7 +125,7 @@ already supported, which can also be re-used on this mimxrt1024_evk board: +-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig`` +:zephyr_file:`boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig` Other hardware features are not currently supported by the port. diff --git a/boards/nxp/mimxrt1040_evk/doc/index.rst b/boards/nxp/mimxrt1040_evk/doc/index.rst index c2f1e1561ce..f01049b7bbd 100644 --- a/boards/nxp/mimxrt1040_evk/doc/index.rst +++ b/boards/nxp/mimxrt1040_evk/doc/index.rst @@ -121,7 +121,7 @@ already supported, which can also be re-used on this mimxrt1040_evk board: The default configuration can be found in the defconfig file: - ``boards/arm/mimxrt1040_evk/mimxrt1040_evk_defconfig`` + :zephyr_file:`boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig` Other hardware features are not currently supported by the port. diff --git a/boards/nxp/mimxrt1050_evk/doc/index.rst b/boards/nxp/mimxrt1050_evk/doc/index.rst index 165f3491f2c..8c5fb87a59b 100644 --- a/boards/nxp/mimxrt1050_evk/doc/index.rst +++ b/boards/nxp/mimxrt1050_evk/doc/index.rst @@ -147,7 +147,7 @@ already supported, which can also be re-used on this mimxrt1050_evk board: The default configuration can be found in the defconfig file: - ``boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig`` + :zephyr_file:`boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig` Other hardware features are not currently supported by the port. diff --git a/boards/nxp/mimxrt1060_evk/doc/index.rst b/boards/nxp/mimxrt1060_evk/doc/index.rst index 94d76f49245..3b2c159685c 100644 --- a/boards/nxp/mimxrt1060_evk/doc/index.rst +++ b/boards/nxp/mimxrt1060_evk/doc/index.rst @@ -154,7 +154,7 @@ already supported, which can also be re-used on this mimxrt1060_evk board: +-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig`` +:zephyr_file:`boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig` Other hardware features are not currently supported by the port. diff --git a/boards/nxp/mimxrt1062_fmurt6/doc/index.rst b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst index 2c801c454af..dd16e7481e2 100644 --- a/boards/nxp/mimxrt1062_fmurt6/doc/index.rst +++ b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst @@ -122,7 +122,7 @@ already supported, which can also be re-used on this mimxrt1060_evk board: +-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig`` +:zephyr_file:`boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig` Other hardware features are not currently supported by the port. diff --git a/boards/nxp/mimxrt1064_evk/doc/index.rst b/boards/nxp/mimxrt1064_evk/doc/index.rst index 38d284f1c47..ffdfcd11b7a 100644 --- a/boards/nxp/mimxrt1064_evk/doc/index.rst +++ b/boards/nxp/mimxrt1064_evk/doc/index.rst @@ -152,7 +152,7 @@ configuration supports the following hardware features: +-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig`` +:zephyr_file:`boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig` Other hardware features are not currently supported by the port. diff --git a/boards/nxp/mimxrt685_evk/doc/index.rst b/boards/nxp/mimxrt685_evk/doc/index.rst index 3b0357ffb02..bbaa6d11c41 100644 --- a/boards/nxp/mimxrt685_evk/doc/index.rst +++ b/boards/nxp/mimxrt685_evk/doc/index.rst @@ -111,7 +111,7 @@ already supported, which can also be re-used on this mimxrt685_evk board: The default configuration can be found in the defconfig file: - ``boards/arm/mimxrt685_evk/mimxrt685_evk_defconfig`` + :zephyr_file:`boards/nxp/mimxrt685_evk/mimxrt685_evk_defconfig` Other hardware features are not currently supported by the port. diff --git a/boards/nxp/vmu_rt1170/doc/index.rst b/boards/nxp/vmu_rt1170/doc/index.rst index 28d57464b4f..0249dfe3d6d 100644 --- a/boards/nxp/vmu_rt1170/doc/index.rst +++ b/boards/nxp/vmu_rt1170/doc/index.rst @@ -125,7 +125,7 @@ following hardware features: +-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: -``boards/arm/vmu_rt1170/vmu_rt1170_defconfig`` +:zephyr_file:`boards/nxp/vmu_rt1170/vmu_rt1170_defconfig` Other hardware features are not currently supported by the port. From 36a9a9cee057887425f04a4ffebff5700a89c4cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 15:26:25 +0100 Subject: [PATCH 0839/2402] doc: guidelines: fix dead links MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix zephyr_file and zephyr_raw broken links Signed-off-by: Benjamin Cabé --- doc/contribute/documentation/guidelines.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/doc/contribute/documentation/guidelines.rst b/doc/contribute/documentation/guidelines.rst index 55db8e2e556..052f038302c 100644 --- a/doc/contribute/documentation/guidelines.rst +++ b/doc/contribute/documentation/guidelines.rst @@ -263,12 +263,12 @@ markup (double backticks) to indicate a ``filename``. For references to files that are in the Zephyr GitHub tree, a special role can be used that creates a hyperlink to that file. For example a reference to the reST file used to create this document can be generated -using ``:zephyr_file:`doc/contribute/documentation/index.rst``` that will -show up as :zephyr_file:`doc/contribute/documentation/index.rst`, a link to +using ``:zephyr_file:`doc/contribute/documentation/guidelines.rst``` that will +show up as :zephyr_file:`doc/contribute/documentation/guidelines.rst`, a link to the "blob" file in the github repo. There's also a -``:zephyr_raw:`doc/guides/documentation/index.rst``` role that will +``:zephyr_raw:`doc/contribute/documentation/guidelines.rst``` role that will link to the "raw" content, -:zephyr_raw:`doc/contribute/documentation/index.rst`. (You can click on +:zephyr_raw:`doc/contribute/documentation/guidelines.rst`. (You can click on these links to see the difference.) .. _internal-linking: From 9518d1d80af499d8869fd209a550d114e7e14c27 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 15:27:00 +0100 Subject: [PATCH 0840/2402] doc: boards: hwmv2: fix teensy dead link MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix a dead reference to teensy40_defconfig file Signed-off-by: Benjamin Cabé --- boards/pjrc/teensy4/doc/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/pjrc/teensy4/doc/index.rst b/boards/pjrc/teensy4/doc/index.rst index 02ac4de8aae..52d8b2aed3d 100644 --- a/boards/pjrc/teensy4/doc/index.rst +++ b/boards/pjrc/teensy4/doc/index.rst @@ -69,7 +69,7 @@ features: The default configuration can be found in the defconfig file: -``boards/arm/teensy4/teensy40_defconfig`` +:zephyr_file:`boards/pjrc/teensy4/teensy40_defconfig` The teensy41 board configuration supports additional hardware @@ -85,7 +85,7 @@ features: The default configuration can be found in the defconfig file: -``boards/arm/teensy4/teensy41_defconfig`` +:zephyr_file:`boards/pjrc/teensy4/teensy41_defconfig` Other hardware features are not currently supported by the port. From 3ca384beb87c99d01276c52208b98d7b8a4030f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 15:27:23 +0100 Subject: [PATCH 0841/2402] doc: boards: hwmv2: fix seagate faze dead link MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix a dead reference to faze/support/openocd.cfg Signed-off-by: Benjamin Cabé --- boards/seagate/faze/doc/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/seagate/faze/doc/index.rst b/boards/seagate/faze/doc/index.rst index 1d61d997cd0..fbb0b5e0084 100644 --- a/boards/seagate/faze/doc/index.rst +++ b/boards/seagate/faze/doc/index.rst @@ -102,7 +102,7 @@ Flashing The NXP LPC11U67 MCU can be flashed by connecting an external debug probe to the SWD port (on-board 4-pins J2 header). In the default OpenOCD configuration -(``boards/arm/faze/support/openocd.cfg``) the ST Link interface is selected. +(:zephyr_file:`boards/seagate/faze/support/openocd.cfg`) the ST Link interface is selected. You may need to replace it with the interface of your debug probe. Once the debug probe is connected to both the FaZe board and your host computer From 27f91456a41b5849a731ee075a4910c22a8c2f40 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 13 Mar 2024 15:54:05 +0100 Subject: [PATCH 0842/2402] doc: dts: fix link to reel board DTS file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix broken link following hwmv2 migration Signed-off-by: Benjamin Cabé --- doc/build/dts/intro-input-output.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/build/dts/intro-input-output.rst b/doc/build/dts/intro-input-output.rst index 365d9fd3c37..698012d5821 100644 --- a/doc/build/dts/intro-input-output.rst +++ b/doc/build/dts/intro-input-output.rst @@ -34,7 +34,7 @@ The devicetree files inside the :file:`zephyr` directory look like this: Generally speaking, every supported board has a :file:`BOARD.dts` file describing its hardware. For example, the ``reel_board`` has -:zephyr_file:`boards/arm/reel_board/reel_board.dts`. +:zephyr_file:`boards/phytec/reel_board/reel_board.dts`. :file:`BOARD.dts` includes one or more ``.dtsi`` files. These ``.dtsi`` files describe the CPU or system-on-chip Zephyr runs on, perhaps by including other From d89e8052da79f9542a18cb14d53d5d2e00976ef1 Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Tue, 12 Mar 2024 15:53:39 +0800 Subject: [PATCH 0843/2402] ITE: soc: it8xxx2: Add missing Kconfig file of it82302ax variant Previous adjustments to hwmv2 lost this Kconfig file. Test: west build -p always -b it82xx2_evb samples/hello_world config BOARD_IT82XX2_EVB select SOC_IT82302_AX Signed-off-by: Tim Lin --- soc/ite/ec/it8xxx2/Kconfig.defconfig.it82302ax | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 soc/ite/ec/it8xxx2/Kconfig.defconfig.it82302ax diff --git a/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82302ax b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82302ax new file mode 100644 index 00000000000..e1cff23886e --- /dev/null +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82302ax @@ -0,0 +1,9 @@ +# Copyright (c) 2024 ITE Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_IT82302_AX + +config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN + default n + +endif From be881d4cf269d3126722ce42e3c198b5960a3f3b Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Wed, 14 Feb 2024 15:23:52 +0200 Subject: [PATCH 0844/2402] arch: xtensa: add isync to interrupt vector On Intel ADSP platforms, additional "isync" is needed in interrupt vector to synchronize icache when core is woken up from deeper sleep state by an interrupt. This is only needed if DSP clock gating is enabled. Signed-off-by: Kai Vehmanen --- arch/xtensa/include/xtensa_asm2_s.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/xtensa/include/xtensa_asm2_s.h b/arch/xtensa/include/xtensa_asm2_s.h index 98bba884f12..ad99e279491 100644 --- a/arch/xtensa/include/xtensa_asm2_s.h +++ b/arch/xtensa/include/xtensa_asm2_s.h @@ -604,6 +604,11 @@ _Level\LVL\()Vector: s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET +#ifdef CONFIG_ADSP_IDLE_CLOCK_GATING + /* Needed when waking from low-power waiti state */ + isync +#endif + /* Level "1" is the exception handler, which uses a different * calling convention. No special register holds the * interrupted PS, instead we just assume that the CPU has From f913af8a4db102c31d200ec6aab497838cb09f1f Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Sun, 4 Feb 2024 00:10:27 +0900 Subject: [PATCH 0845/2402] doc: posix: mark putmsg as supported Mark `putmsg()` as implemented but will fail with ``ENOSYS`` Was missing on the documentation before. signed-off-by: Gaetan Perrot --- doc/services/portability/posix/conformance/index.rst | 2 +- doc/services/portability/posix/option_groups/index.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/services/portability/posix/conformance/index.rst b/doc/services/portability/posix/conformance/index.rst index 0c38955337e..2fe9156f943 100644 --- a/doc/services/portability/posix/conformance/index.rst +++ b/doc/services/portability/posix/conformance/index.rst @@ -109,7 +109,7 @@ POSIX System Interfaces _XOPEN_CRYPT, -1, _XOPEN_REALTIME, -1, _XOPEN_REALTIME_THREADS, -1, - :ref:`_XOPEN_STREAMS`, -1, :kconfig:option:`CONFIG_NET_SOCKETS` + :ref:`_XOPEN_STREAMS`, -1, :ref:`†` _XOPEN_UNIX, -1, POSIX Shell and Utilities diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst index 229ae6b5ec3..59991b275f8 100644 --- a/doc/services/portability/posix/option_groups/index.rst +++ b/doc/services/portability/posix/option_groups/index.rst @@ -509,7 +509,7 @@ _XOPEN_STREAMS getpmsg(), yes (will fail with ``ENOSYS``:ref:`†`) ioctl(),yes isastream(), - putmsg(), + putmsg(), yes (will fail with ``ENOSYS``:ref:`†`) putpmsg(), From b519041948b83845e4a7b200f1c5cc91a73221a4 Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Thu, 29 Feb 2024 16:49:44 +0900 Subject: [PATCH 0846/2402] doc: posix: sched functions will fail with ENOSYS Mark `sched_setparam()` , `sched_setscheduler()` and `sched_rr_get_interval()` have implemented but will fail with ``ENOSYS`` Were missing on the documentation before. signed-off-by: Gaetan Perrot --- doc/services/portability/posix/option_groups/index.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst index 59991b275f8..0fe00546d6c 100644 --- a/doc/services/portability/posix/option_groups/index.rst +++ b/doc/services/portability/posix/option_groups/index.rst @@ -379,9 +379,9 @@ _POSIX_PRIORITY_SCHEDULING sched_get_priority_min(),yes sched_getparam(),yes sched_getscheduler(),yes - sched_rr_get_interval(),yes - sched_setparam(),yes - sched_setscheduler(),yes + sched_rr_get_interval(),yes (will fail with ``ENOSYS``:ref:`†`) + sched_setparam(),yes (will fail with ``ENOSYS``:ref:`†`) + sched_setscheduler(),yes (will fail with ``ENOSYS``:ref:`†`) sched_yield(),yes .. _posix_option_reader_writer_locks: From 4f3db943b9b3ab8616654f1b8b48acf74f06fd0e Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 12 Mar 2024 20:52:30 +0000 Subject: [PATCH 0847/2402] boards: xenvm: ignore userspace tests Ignore userspace tag completely. Disabling USERSPACE in board kconfig is not right, this will always be overidden by the application and we will have build failures. The HW supports userspace and most filters in tests depend on this capability. Signed-off-by: Anas Nashif --- boards/xen/xenvm/xenvm.yaml | 3 +++ boards/xen/xenvm/xenvm_defconfig | 3 --- boards/xen/xenvm/xenvm_xenvm_gicv3.yaml | 3 +++ 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/boards/xen/xenvm/xenvm.yaml b/boards/xen/xenvm/xenvm.yaml index 2cd38e3c399..dc72d05e550 100644 --- a/boards/xen/xenvm/xenvm.yaml +++ b/boards/xen/xenvm/xenvm.yaml @@ -7,3 +7,6 @@ toolchain: - cross-compile ram: 16384 vendor: xen +testing: + ignore_tags: + - userspace diff --git a/boards/xen/xenvm/xenvm_defconfig b/boards/xen/xenvm/xenvm_defconfig index 38885a73413..2115f9175bd 100644 --- a/boards/xen/xenvm/xenvm_defconfig +++ b/boards/xen/xenvm/xenvm_defconfig @@ -10,7 +10,4 @@ CONFIG_UART_CONSOLE=y # Enable logging subsys CONFIG_LOG=y CONFIG_LOG_MODE_MINIMAL=n - -CONFIG_USERSPACE=n - CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y diff --git a/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml b/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml index a680dd6d0cf..edf816e4979 100644 --- a/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml +++ b/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml @@ -7,3 +7,6 @@ toolchain: - cross-compile ram: 16384 vendor: xen +testing: + ignore_tags: + - userspace From 3981b9a5603d20760d819b2dbd62e63e61108ac6 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Sun, 17 Mar 2024 10:03:33 +0100 Subject: [PATCH 0848/2402] tests/drivers/build_all/w1: Add gpio dependency This driver enables CONFIG_GPIO, so if we try to target a board which does not support it it will fail. Let's add the required tag in the testcase yaml. Signed-off-by: Alberto Escolar Piedras --- tests/drivers/build_all/w1/testcase.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/drivers/build_all/w1/testcase.yaml b/tests/drivers/build_all/w1/testcase.yaml index f0e1d11aeb9..f1ddfc682dd 100644 --- a/tests/drivers/build_all/w1/testcase.yaml +++ b/tests/drivers/build_all/w1/testcase.yaml @@ -7,5 +7,7 @@ tests: tags: - drivers - w1 + depends_on: + - gpio integration_platforms: - native_posix From 4c06e5abba83c8d6587b626f799e832aabfabde1 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Wed, 6 Mar 2024 21:50:05 +0100 Subject: [PATCH 0849/2402] dts: bindings: can: make initial sample point properties optional Make the properties for setting the initial sample points for both the classic/arbitration phase and the data phase optional. Signed-off-by: Henrik Brix Andersen --- dts/bindings/can/can-controller.yaml | 5 ++++- dts/bindings/can/can-fd-controller.yaml | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/dts/bindings/can/can-controller.yaml b/dts/bindings/can/can-controller.yaml index c53d69e3041..adc738d7319 100644 --- a/dts/bindings/can/can-controller.yaml +++ b/dts/bindings/can/can-controller.yaml @@ -10,9 +10,12 @@ properties: Initial bitrate in bit/s. sample-point: type: int - required: true description: | Initial sample point in per mille (e.g. 875 equals 87.5%). + + If this is unset (or if it is set to 0), the initial sample point will default to 75.0% for + bitrates over 800 kbit/s, 80.0% for bitrates over 500 kbit/s, and 87.5% for all other + bitrates. phys: type: phandle description: | diff --git a/dts/bindings/can/can-fd-controller.yaml b/dts/bindings/can/can-fd-controller.yaml index cbef3b1ac9e..a29749d93ba 100644 --- a/dts/bindings/can/can-fd-controller.yaml +++ b/dts/bindings/can/can-fd-controller.yaml @@ -10,9 +10,12 @@ properties: Initial data phase bitrate in bit/s. sample-point-data: type: int - required: true description: | Initial data phase sample point in per mille (e.g. 875 equals 87.5%). + + If this is unset (or if it is set to 0), the initial sample point will default to 75.0% for + bitrates over 800 kbit/s, 80.0% for bitrates over 500 kbit/s, and 87.5% for all other + bitrates. tx-delay-comp-offset: type: int default: 0 From 41960ab3665829d01a784ff9df08d06ddbef77ee Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Wed, 6 Mar 2024 21:56:23 +0100 Subject: [PATCH 0850/2402] dts: bindings: can: remove optional sample point properties Remove all optional, initial CAN sample point properties and rely on the CAN timing calculations to automatically pick the preferred sample point location based on the initial bitrate. Signed-off-by: Henrik Brix Andersen --- boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts | 1 - boards/native/native_sim/native_sim.dts | 2 -- boards/nxp/mr_canhubk3/mr_canhubk3.dts | 12 ------------ boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi | 4 ---- boards/nxp/ucans32k1sic/ucans32k1sic.dts | 4 ---- boards/qemu/x86/qemu_x86.dts | 1 - .../shields/mcp2515/adafruit_can_picowbell.overlay | 1 - boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay | 1 - .../mcp2515/keyestudio_can_bus_ks0411.overlay | 1 - .../mikroe_mcp2518fd_click.overlay | 2 -- boards/shields/tcan4550evm/tcan4550evm.overlay | 2 -- boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts | 2 -- dts/arm/atmel/samc21.dtsi | 4 ---- dts/arm/atmel/same5x.dtsi | 4 ---- dts/arm/atmel/same70.dtsi | 4 ---- dts/arm/nuvoton/m46x.dtsi | 8 -------- dts/arm/nxp/nxp_k66.dtsi | 1 - dts/arm/nxp/nxp_k6x.dtsi | 1 - dts/arm/nxp/nxp_ke1xf.dtsi | 2 -- dts/arm/nxp/nxp_lpc55S0x_common.dtsi | 2 -- dts/arm/nxp/nxp_lpc55S1x_common.dtsi | 2 -- dts/arm/nxp/nxp_lpc55S3x_common.dtsi | 2 -- dts/arm/nxp/nxp_rt10xx.dtsi | 4 ---- dts/arm/nxp/nxp_rt11xx.dtsi | 6 ------ dts/arm/renesas/rcar/gen3/rcar_gen3_cr7.dtsi | 1 - dts/arm/st/f0/stm32f042.dtsi | 1 - dts/arm/st/f0/stm32f072.dtsi | 1 - dts/arm/st/f0/stm32f091.dtsi | 1 - dts/arm/st/f1/stm32f103X8.dtsi | 1 - dts/arm/st/f1/stm32f105.dtsi | 2 -- dts/arm/st/f3/stm32f3.dtsi | 1 - dts/arm/st/f4/stm32f405.dtsi | 2 -- dts/arm/st/f4/stm32f412.dtsi | 2 -- dts/arm/st/f4/stm32f413.dtsi | 1 - dts/arm/st/f4/stm32f446.dtsi | 2 -- dts/arm/st/f7/stm32f7.dtsi | 1 - dts/arm/st/f7/stm32f745.dtsi | 1 - dts/arm/st/g0/stm32g0b1.dtsi | 4 ---- dts/arm/st/g4/stm32g4.dtsi | 2 -- dts/arm/st/g4/stm32g473.dtsi | 2 -- dts/arm/st/g4/stm32g491.dtsi | 2 -- dts/arm/st/h5/stm32h5.dtsi | 2 -- dts/arm/st/h5/stm32h562.dtsi | 2 -- dts/arm/st/h7/stm32h7.dtsi | 4 ---- dts/arm/st/h7/stm32h723.dtsi | 2 -- dts/arm/st/l4/stm32l431.dtsi | 1 - dts/arm/st/l4/stm32l432.dtsi | 1 - dts/arm/st/l4/stm32l451.dtsi | 1 - dts/arm/st/l4/stm32l471.dtsi | 1 - dts/arm/st/l4/stm32l496.dtsi | 1 - dts/arm/st/l4/stm32l4p5.dtsi | 1 - dts/arm/st/u5/stm32u5.dtsi | 2 -- dts/bindings/can/microchip,mcp251xfd.yaml | 2 -- dts/bindings/can/nxp,flexcan-fd.yaml | 2 -- dts/bindings/can/nxp,flexcan.yaml | 1 - dts/bindings/can/ti,tcan4x5x.yaml | 2 -- dts/riscv/espressif/esp32c3/esp32c3_common.dtsi | 1 - dts/xtensa/espressif/esp32/esp32_common.dtsi | 1 - dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi | 1 - dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi | 1 - tests/drivers/can/shell/app.overlay | 3 --- tests/lib/devicetree/api/app.overlay | 4 ---- 62 files changed, 136 deletions(-) diff --git a/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts index 19cad242f1f..df37b32e3c7 100644 --- a/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts +++ b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts @@ -208,7 +208,6 @@ &can_node1 { status = "okay"; bus-speed = <125000>; - sample-point = <875>; input-src = "RXDC"; pinctrl-0 = <&can_tx_p1_12_node1 &can_rx_p1_13_node1>; pinctrl-names = "default"; diff --git a/boards/native/native_sim/native_sim.dts b/boards/native/native_sim/native_sim.dts index 76f34769b5e..aa4f2eab0c8 100644 --- a/boards/native/native_sim/native_sim.dts +++ b/boards/native/native_sim/native_sim.dts @@ -190,7 +190,6 @@ can_loopback0: can_loopback0 { status = "okay"; compatible = "zephyr,can-loopback"; - sample-point = <875>; bus-speed = <125000>; }; @@ -201,7 +200,6 @@ * name, e.g.: sudo ip link property add dev vcan0 altname zcan0 */ host-interface = "zcan0"; - sample-point = <875>; bus-speed = <125000>; }; diff --git a/boards/nxp/mr_canhubk3/mr_canhubk3.dts b/boards/nxp/mr_canhubk3/mr_canhubk3.dts index b0866f7073a..d0928d50739 100644 --- a/boards/nxp/mr_canhubk3/mr_canhubk3.dts +++ b/boards/nxp/mr_canhubk3/mr_canhubk3.dts @@ -330,9 +330,7 @@ pinctrl-names = "default"; phys = <&can_phy0>; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; status = "okay"; }; @@ -341,9 +339,7 @@ pinctrl-names = "default"; phys = <&can_phy1>; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; }; &flexcan2 { @@ -351,9 +347,7 @@ pinctrl-names = "default"; phys = <&can_phy2>; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; }; &flexcan3 { @@ -361,9 +355,7 @@ pinctrl-names = "default"; phys = <&can_phy3>; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; }; &flexcan4 { @@ -371,9 +363,7 @@ pinctrl-names = "default"; phys = <&can_phy4>; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; }; &flexcan5 { @@ -381,9 +371,7 @@ pinctrl-names = "default"; phys = <&can_phy5>; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; }; &lpi2c0 { diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi index 10fda8bb439..297b4926d11 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi @@ -35,9 +35,7 @@ pinctrl-0 = <&can0_default>; pinctrl-names = "default"; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; status = "okay"; }; @@ -45,7 +43,5 @@ pinctrl-0 = <&can1_default>; pinctrl-names = "default"; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; }; diff --git a/boards/nxp/ucans32k1sic/ucans32k1sic.dts b/boards/nxp/ucans32k1sic/ucans32k1sic.dts index 6996a12d6d0..9f6b37248c7 100644 --- a/boards/nxp/ucans32k1sic/ucans32k1sic.dts +++ b/boards/nxp/ucans32k1sic/ucans32k1sic.dts @@ -175,9 +175,7 @@ pinctrl-names = "default"; phys = <&can_phy0>; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; status = "okay"; }; @@ -186,8 +184,6 @@ pinctrl-names = "default"; phys = <&can_phy1>; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; status = "okay"; }; diff --git a/boards/qemu/x86/qemu_x86.dts b/boards/qemu/x86/qemu_x86.dts index 85e3f56c36e..fbe6042c178 100644 --- a/boards/qemu/x86/qemu_x86.dts +++ b/boards/qemu/x86/qemu_x86.dts @@ -62,7 +62,6 @@ interrupts = <11 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupt-parent = <&intc>; bus-speed = <125000>; - sample-point = <875>; can-transceiver { max-bitrate = <1000000>; diff --git a/boards/shields/mcp2515/adafruit_can_picowbell.overlay b/boards/shields/mcp2515/adafruit_can_picowbell.overlay index 163d7958318..8a9d719e641 100644 --- a/boards/shields/mcp2515/adafruit_can_picowbell.overlay +++ b/boards/shields/mcp2515/adafruit_can_picowbell.overlay @@ -16,7 +16,6 @@ reg = <0x0>; osc-freq = <16000000>; bus-speed = <125000>; - sample-point = <875>; can-transceiver { max-bitrate = <1000000>; diff --git a/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay b/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay index 7670b02e173..e520218830e 100644 --- a/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay +++ b/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay @@ -16,7 +16,6 @@ reg = <0x0>; osc-freq = <16000000>; bus-speed = <125000>; - sample-point = <875>; can-transceiver { min-bitrate = <60000>; diff --git a/boards/shields/mcp2515/keyestudio_can_bus_ks0411.overlay b/boards/shields/mcp2515/keyestudio_can_bus_ks0411.overlay index 43089f65d84..e4136cf577b 100644 --- a/boards/shields/mcp2515/keyestudio_can_bus_ks0411.overlay +++ b/boards/shields/mcp2515/keyestudio_can_bus_ks0411.overlay @@ -16,7 +16,6 @@ reg = <0x0>; osc-freq = <16000000>; bus-speed = <125000>; - sample-point = <875>; can-transceiver { max-bitrate = <1000000>; diff --git a/boards/shields/mikroe_mcp2518fd_click/mikroe_mcp2518fd_click.overlay b/boards/shields/mikroe_mcp2518fd_click/mikroe_mcp2518fd_click.overlay index afd647b760a..43094d1d72a 100644 --- a/boards/shields/mikroe_mcp2518fd_click/mikroe_mcp2518fd_click.overlay +++ b/boards/shields/mikroe_mcp2518fd_click/mikroe_mcp2518fd_click.overlay @@ -11,9 +11,7 @@ osc-freq = <40000000>; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; }; }; diff --git a/boards/shields/tcan4550evm/tcan4550evm.overlay b/boards/shields/tcan4550evm/tcan4550evm.overlay index 61c62ef4c0c..d25d8ff0e62 100644 --- a/boards/shields/tcan4550evm/tcan4550evm.overlay +++ b/boards/shields/tcan4550evm/tcan4550evm.overlay @@ -28,8 +28,6 @@ reset-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; /* D8 */ int-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ bosch,mram-cfg = <0x0 15 15 7 7 0 10 10>; - sample-point = <875>; - sample-point-data = <875>; bus-speed = <125000>; bus-speed-data = <1000000>; status = "okay"; diff --git a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts index 4198ec2b34a..2ca13215b5e 100644 --- a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts +++ b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts @@ -157,8 +157,6 @@ phys = <&transceiver0>; bus-speed = <125000>; bus-speed-data = <1000000>; - sample-point = <875>; - sample-point-data = <875>; status = "okay"; }; diff --git a/dts/arm/atmel/samc21.dtsi b/dts/arm/atmel/samc21.dtsi index 72b28386a4b..095e98437f0 100644 --- a/dts/arm/atmel/samc21.dtsi +++ b/dts/arm/atmel/samc21.dtsi @@ -53,8 +53,6 @@ clock-names = "GCLK", "MCLK"; bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>; divider = <12>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; @@ -67,8 +65,6 @@ clock-names = "GCLK", "MCLK"; bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>; divider = <12>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; }; diff --git a/dts/arm/atmel/same5x.dtsi b/dts/arm/atmel/same5x.dtsi index c4b1762e5b3..750094cfafe 100644 --- a/dts/arm/atmel/same5x.dtsi +++ b/dts/arm/atmel/same5x.dtsi @@ -36,8 +36,6 @@ clock-names = "GCLK", "MCLK"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; divider = <12>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; @@ -50,8 +48,6 @@ clock-names = "GCLK", "MCLK"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; divider = <12>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; }; diff --git a/dts/arm/atmel/same70.dtsi b/dts/arm/atmel/same70.dtsi index 878ad822d68..12846be7e3b 100644 --- a/dts/arm/atmel/same70.dtsi +++ b/dts/arm/atmel/same70.dtsi @@ -425,8 +425,6 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; divider = <6>; bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; @@ -438,8 +436,6 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; divider = <6>; bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/nuvoton/m46x.dtsi b/dts/arm/nuvoton/m46x.dtsi index 020c5848809..1d0e15a61d4 100644 --- a/dts/arm/nuvoton/m46x.dtsi +++ b/dts/arm/nuvoton/m46x.dtsi @@ -443,8 +443,6 @@ NUMAKER_CLK_CLKDIV5_CANFD0(1)>; bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; status = "disabled"; - sample-point = <875>; - sample-point-data = <875>; }; canfd1: canfd@40024000 { @@ -459,8 +457,6 @@ NUMAKER_CLK_CLKDIV5_CANFD1(1)>; bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; status = "disabled"; - sample-point = <875>; - sample-point-data = <875>; }; canfd2: canfd@40028000 { @@ -475,8 +471,6 @@ NUMAKER_CLK_CLKDIV5_CANFD2(1)>; bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; status = "disabled"; - sample-point = <875>; - sample-point-data = <875>; }; canfd3: canfd@4002c000 { @@ -491,8 +485,6 @@ NUMAKER_CLK_CLKDIV5_CANFD3(1)>; bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; status = "disabled"; - sample-point = <875>; - sample-point-data = <875>; }; emac: ethernet@40012000 { diff --git a/dts/arm/nxp/nxp_k66.dtsi b/dts/arm/nxp/nxp_k66.dtsi index 2c2470fcf88..f5595674c90 100644 --- a/dts/arm/nxp/nxp_k66.dtsi +++ b/dts/arm/nxp/nxp_k66.dtsi @@ -31,7 +31,6 @@ "rx-warning", "wake-up"; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 4>; clk-source = <1>; - sample-point = <875>; status = "disabled"; }; }; diff --git a/dts/arm/nxp/nxp_k6x.dtsi b/dts/arm/nxp/nxp_k6x.dtsi index 2bf247fd797..20f3d90e999 100644 --- a/dts/arm/nxp/nxp_k6x.dtsi +++ b/dts/arm/nxp/nxp_k6x.dtsi @@ -504,7 +504,6 @@ interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning", "rx-warning", "wake-up"; clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 4>; clk-source = <1>; - sample-point = <875>; status = "disabled"; }; diff --git a/dts/arm/nxp/nxp_ke1xf.dtsi b/dts/arm/nxp/nxp_ke1xf.dtsi index 5007f58f434..6d2bacf26ea 100644 --- a/dts/arm/nxp/nxp_ke1xf.dtsi +++ b/dts/arm/nxp/nxp_ke1xf.dtsi @@ -405,7 +405,6 @@ "mb-0-15"; clocks = <&scg KINETIS_SCG_BUS_CLK>; clk-source = <1>; - sample-point = <875>; status = "disabled"; }; @@ -417,7 +416,6 @@ "mb-0-15"; clocks = <&scg KINETIS_SCG_BUS_CLK>; clk-source = <1>; - sample-point = <875>; status = "disabled"; }; diff --git a/dts/arm/nxp/nxp_lpc55S0x_common.dtsi b/dts/arm/nxp/nxp_lpc55S0x_common.dtsi index c579a917698..c2f8295e575 100644 --- a/dts/arm/nxp/nxp_lpc55S0x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S0x_common.dtsi @@ -223,8 +223,6 @@ interrupt-names = "int0", "int1"; clocks = <&syscon MCUX_MCAN_CLK>; bosch,mram-cfg = <0x0 15 15 8 8 0 15 15>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi index 304bf2e68d9..05ad85196be 100644 --- a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi @@ -218,8 +218,6 @@ interrupt-names = "int0", "int1"; clocks = <&syscon MCUX_MCAN_CLK>; bosch,mram-cfg = <0x0 15 15 8 8 0 15 15>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/nxp/nxp_lpc55S3x_common.dtsi b/dts/arm/nxp/nxp_lpc55S3x_common.dtsi index 18ca28d03e8..16b90cb7392 100644 --- a/dts/arm/nxp/nxp_lpc55S3x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S3x_common.dtsi @@ -328,8 +328,6 @@ interrupt-names = "int0", "int1"; clocks = <&syscon MCUX_MCAN_CLK>; bosch,mram-cfg = <0x0 15 15 8 8 0 15 15>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/nxp/nxp_rt10xx.dtsi b/dts/arm/nxp/nxp_rt10xx.dtsi index 771df619dc0..714b4a303bd 100644 --- a/dts/arm/nxp/nxp_rt10xx.dtsi +++ b/dts/arm/nxp/nxp_rt10xx.dtsi @@ -872,7 +872,6 @@ interrupt-names = "common"; clocks = <&ccm IMX_CCM_CAN_CLK 0x68 14>; clk-source = <2>; - sample-point = <875>; status = "disabled"; }; @@ -883,7 +882,6 @@ interrupt-names = "common"; clocks = <&ccm IMX_CCM_CAN_CLK 0x68 18>; clk-source = <2>; - sample-point = <875>; status = "disabled"; }; @@ -894,8 +892,6 @@ interrupt-names = "common"; clocks = <&ccm IMX_CCM_CAN_CLK 0x84 6>; clk-source = <2>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/nxp/nxp_rt11xx.dtsi b/dts/arm/nxp/nxp_rt11xx.dtsi index 317c849e409..92f95a194ff 100644 --- a/dts/arm/nxp/nxp_rt11xx.dtsi +++ b/dts/arm/nxp/nxp_rt11xx.dtsi @@ -806,8 +806,6 @@ interrupt-names = "common", "error"; clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>; clk-source = <0>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; @@ -818,8 +816,6 @@ interrupt-names = "common", "error"; clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 18>; clk-source = <0>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; @@ -830,8 +826,6 @@ interrupt-names = "common", "error"; clocks = <&ccm IMX_CCM_CAN3_CLK 0x84 6>; clk-source = <0>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/renesas/rcar/gen3/rcar_gen3_cr7.dtsi b/dts/arm/renesas/rcar/gen3/rcar_gen3_cr7.dtsi index 0f1cecf7d89..f55d6ec06e2 100644 --- a/dts/arm/renesas/rcar/gen3/rcar_gen3_cr7.dtsi +++ b/dts/arm/renesas/rcar/gen3/rcar_gen3_cr7.dtsi @@ -94,7 +94,6 @@ interrupt-parent = <&gic>; interrupts = ; - sample-point = <875>; status = "disabled"; }; diff --git a/dts/arm/st/f0/stm32f042.dtsi b/dts/arm/st/f0/stm32f042.dtsi index 52744d1ff47..aa692352905 100644 --- a/dts/arm/st/f0/stm32f042.dtsi +++ b/dts/arm/st/f0/stm32f042.dtsi @@ -44,7 +44,6 @@ interrupts = <30 0>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; status = "disabled"; - sample-point = <875>; }; timers15: timers@40014000 { diff --git a/dts/arm/st/f0/stm32f072.dtsi b/dts/arm/st/f0/stm32f072.dtsi index 1c7ad8b1b67..a529d7238f7 100644 --- a/dts/arm/st/f0/stm32f072.dtsi +++ b/dts/arm/st/f0/stm32f072.dtsi @@ -16,7 +16,6 @@ interrupts = <30 0>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; status = "disabled"; - sample-point = <875>; }; usb: usb@40005c00 { diff --git a/dts/arm/st/f0/stm32f091.dtsi b/dts/arm/st/f0/stm32f091.dtsi index 67497b09d8d..ee46f86c319 100644 --- a/dts/arm/st/f0/stm32f091.dtsi +++ b/dts/arm/st/f0/stm32f091.dtsi @@ -58,7 +58,6 @@ interrupts = <30 0>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; status = "disabled"; - sample-point = <875>; }; dma2: dma@40020400 { diff --git a/dts/arm/st/f1/stm32f103X8.dtsi b/dts/arm/st/f1/stm32f103X8.dtsi index ae7150291be..c34699026d3 100644 --- a/dts/arm/st/f1/stm32f103X8.dtsi +++ b/dts/arm/st/f1/stm32f103X8.dtsi @@ -54,7 +54,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; status = "disabled"; - sample-point = <875>; }; }; diff --git a/dts/arm/st/f1/stm32f105.dtsi b/dts/arm/st/f1/stm32f105.dtsi index 1a2ec793d99..6d62e2ce658 100644 --- a/dts/arm/st/f1/stm32f105.dtsi +++ b/dts/arm/st/f1/stm32f105.dtsi @@ -40,7 +40,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; status = "disabled"; - sample-point = <875>; }; can2: can@40006800 { @@ -51,7 +50,6 @@ /* also enabling clock for can1 (master instance) */ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>; status = "disabled"; - sample-point = <875>; }; dac1: dac@40007400 { diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi index e4a64b24304..725ed0eacb6 100644 --- a/dts/arm/st/f3/stm32f3.dtsi +++ b/dts/arm/st/f3/stm32f3.dtsi @@ -420,7 +420,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; status = "disabled"; - sample-point = <875>; }; dma1: dma@40020000 { diff --git a/dts/arm/st/f4/stm32f405.dtsi b/dts/arm/st/f4/stm32f405.dtsi index a462d48a266..be2941822e1 100644 --- a/dts/arm/st/f4/stm32f405.dtsi +++ b/dts/arm/st/f4/stm32f405.dtsi @@ -212,7 +212,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; status = "disabled"; - sample-point = <875>; }; can2: can@40006800 { @@ -224,7 +223,6 @@ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>; master-can-reg = <0x40006400>; status = "disabled"; - sample-point = <875>; }; rng: rng@50060800 { diff --git a/dts/arm/st/f4/stm32f412.dtsi b/dts/arm/st/f4/stm32f412.dtsi index 07f93afc963..5c7024b295f 100644 --- a/dts/arm/st/f4/stm32f412.dtsi +++ b/dts/arm/st/f4/stm32f412.dtsi @@ -222,7 +222,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; status = "disabled"; - sample-point = <875>; }; can2: can@40006800 { @@ -234,7 +233,6 @@ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>; master-can-reg = <0x40006400>; status = "disabled"; - sample-point = <875>; }; }; }; diff --git a/dts/arm/st/f4/stm32f413.dtsi b/dts/arm/st/f4/stm32f413.dtsi index ac61c7d351b..91f0eda924f 100644 --- a/dts/arm/st/f4/stm32f413.dtsi +++ b/dts/arm/st/f4/stm32f413.dtsi @@ -79,7 +79,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x08000000>; status = "disabled"; - sample-point = <875>; }; }; }; diff --git a/dts/arm/st/f4/stm32f446.dtsi b/dts/arm/st/f4/stm32f446.dtsi index 7b15fe2a9cf..2756b2abd80 100644 --- a/dts/arm/st/f4/stm32f446.dtsi +++ b/dts/arm/st/f4/stm32f446.dtsi @@ -65,7 +65,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; status = "disabled"; - sample-point = <875>; }; can2: can@40006800 { @@ -77,7 +76,6 @@ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>; master-can-reg = <0x40006400>; status = "disabled"; - sample-point = <875>; }; usbotg_fs: usb@50000000 { diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index cfd98d4bb4d..600f959b4fd 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -403,7 +403,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; status = "disabled"; - sample-point = <875>; }; timers1: timers@40010000 { diff --git a/dts/arm/st/f7/stm32f745.dtsi b/dts/arm/st/f7/stm32f745.dtsi index 551e3af6f3f..f42d2e54283 100644 --- a/dts/arm/st/f7/stm32f745.dtsi +++ b/dts/arm/st/f7/stm32f745.dtsi @@ -73,7 +73,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>; status = "disabled"; - sample-point = <875>; }; mac: ethernet@40028000 { diff --git a/dts/arm/st/g0/stm32g0b1.dtsi b/dts/arm/st/g0/stm32g0b1.dtsi index f6a8ae129e0..fd83aa7b232 100644 --- a/dts/arm/st/g0/stm32g0b1.dtsi +++ b/dts/arm/st/g0/stm32g0b1.dtsi @@ -38,8 +38,6 @@ interrupt-names = "int0", "int1"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>; bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; @@ -51,8 +49,6 @@ interrupt-names = "int0", "int1"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>; bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi index d42ff353a73..1450efbee38 100644 --- a/dts/arm/st/g4/stm32g4.dtsi +++ b/dts/arm/st/g4/stm32g4.dtsi @@ -390,8 +390,6 @@ interrupt-names = "int0", "int1"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/st/g4/stm32g473.dtsi b/dts/arm/st/g4/stm32g473.dtsi index 0cdcc317f0a..0f538669ff3 100644 --- a/dts/arm/st/g4/stm32g473.dtsi +++ b/dts/arm/st/g4/stm32g473.dtsi @@ -103,8 +103,6 @@ interrupt-names = "int0", "int1"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; bosch,mram-cfg = <0x6a0 28 8 3 3 0 3 3>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; }; diff --git a/dts/arm/st/g4/stm32g491.dtsi b/dts/arm/st/g4/stm32g491.dtsi index 1e616accc77..f51eb356157 100644 --- a/dts/arm/st/g4/stm32g491.dtsi +++ b/dts/arm/st/g4/stm32g491.dtsi @@ -18,8 +18,6 @@ interrupt-names = "int0", "int1"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi index dff30f083da..087ca1b5653 100644 --- a/dts/arm/st/h5/stm32h5.dtsi +++ b/dts/arm/st/h5/stm32h5.dtsi @@ -441,8 +441,6 @@ interrupt-names = "int0", "int1"; clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>; bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/st/h5/stm32h562.dtsi b/dts/arm/st/h5/stm32h562.dtsi index 0e407a02be0..a88b7b8a063 100644 --- a/dts/arm/st/h5/stm32h562.dtsi +++ b/dts/arm/st/h5/stm32h562.dtsi @@ -330,8 +330,6 @@ /* common clock FDCAN 1 & 2 */ clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>; bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; }; diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index 28ca326f596..95c5590a871 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -516,8 +516,6 @@ interrupts = <19 0>, <21 0>, <63 0>; interrupt-names = "int0", "int1", "calib"; bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; @@ -529,8 +527,6 @@ interrupts = <20 0>, <22 0>, <63 0>; interrupt-names = "int0", "int1", "calib"; bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/st/h7/stm32h723.dtsi b/dts/arm/st/h7/stm32h723.dtsi index 0a7d8a3fe61..662ecef5da9 100644 --- a/dts/arm/st/h7/stm32h723.dtsi +++ b/dts/arm/st/h7/stm32h723.dtsi @@ -123,8 +123,6 @@ interrupts = <159 0>, <160 0>, <63 0>; interrupt-names = "int0", "int1", "calib"; bosch,mram-cfg = <0x6a0 28 8 3 3 0 3 3>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l431.dtsi b/dts/arm/st/l4/stm32l431.dtsi index 7fb1d7b4bd4..ab445732782 100644 --- a/dts/arm/st/l4/stm32l431.dtsi +++ b/dts/arm/st/l4/stm32l431.dtsi @@ -107,7 +107,6 @@ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - sample-point = <875>; status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l432.dtsi b/dts/arm/st/l4/stm32l432.dtsi index 9db0a1e244e..b0774c10632 100644 --- a/dts/arm/st/l4/stm32l432.dtsi +++ b/dts/arm/st/l4/stm32l432.dtsi @@ -57,7 +57,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN status = "disabled"; - sample-point = <875>; }; usb: usb@40006800 { diff --git a/dts/arm/st/l4/stm32l451.dtsi b/dts/arm/st/l4/stm32l451.dtsi index c22e4ef0820..d92624861c4 100644 --- a/dts/arm/st/l4/stm32l451.dtsi +++ b/dts/arm/st/l4/stm32l451.dtsi @@ -141,7 +141,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN status = "disabled"; - sample-point = <875>; }; sdmmc1: sdmmc@40012800 { diff --git a/dts/arm/st/l4/stm32l471.dtsi b/dts/arm/st/l4/stm32l471.dtsi index 53a7fe28f02..11cf6d1f359 100644 --- a/dts/arm/st/l4/stm32l471.dtsi +++ b/dts/arm/st/l4/stm32l471.dtsi @@ -232,7 +232,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN status = "disabled"; - sample-point = <875>; }; sdmmc1: sdmmc@40012800 { diff --git a/dts/arm/st/l4/stm32l496.dtsi b/dts/arm/st/l4/stm32l496.dtsi index 4bba5f13ecc..9a685455b7b 100644 --- a/dts/arm/st/l4/stm32l496.dtsi +++ b/dts/arm/st/l4/stm32l496.dtsi @@ -56,7 +56,6 @@ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>; //RCC_APB1ENR1_CAN2EN master-can-reg = <0x40006400>; status = "disabled"; - sample-point = <875>; }; aes: aes@50060000 { diff --git a/dts/arm/st/l4/stm32l4p5.dtsi b/dts/arm/st/l4/stm32l4p5.dtsi index 648fa936a5f..d802ffbcfc8 100644 --- a/dts/arm/st/l4/stm32l4p5.dtsi +++ b/dts/arm/st/l4/stm32l4p5.dtsi @@ -291,7 +291,6 @@ interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN status = "disabled"; - sample-point = <875>; }; aes: aes@50060000 { diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi index 43f4830bf72..bd9bb445858 100644 --- a/dts/arm/st/u5/stm32u5.dtsi +++ b/dts/arm/st/u5/stm32u5.dtsi @@ -801,8 +801,6 @@ interrupt-names = "int0", "int1"; clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>; bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; - sample-point = <875>; - sample-point-data = <875>; status = "disabled"; }; diff --git a/dts/bindings/can/microchip,mcp251xfd.yaml b/dts/bindings/can/microchip,mcp251xfd.yaml index b35cb0fa48a..e4350760594 100644 --- a/dts/bindings/can/microchip,mcp251xfd.yaml +++ b/dts/bindings/can/microchip,mcp251xfd.yaml @@ -20,9 +20,7 @@ description: | osc-freq = <40000000>; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <875>; }; }; diff --git a/dts/bindings/can/nxp,flexcan-fd.yaml b/dts/bindings/can/nxp,flexcan-fd.yaml index 72c36292cc0..f55eb780c2d 100644 --- a/dts/bindings/can/nxp,flexcan-fd.yaml +++ b/dts/bindings/can/nxp,flexcan-fd.yaml @@ -15,8 +15,6 @@ description: | interrupt-names = "common"; clocks = <&ccm IMX_CCM_CAN_CLK 0x84 6>; clk-source = <2>; - sample-point = <875>; - sample-point-data = <875>; bus-speed = <125000>; bus-speed-data = <1000000>; pinctrl-0 = <&pinmux_flexcan3>; diff --git a/dts/bindings/can/nxp,flexcan.yaml b/dts/bindings/can/nxp,flexcan.yaml index f23d0f45d81..736382d68bd 100644 --- a/dts/bindings/can/nxp,flexcan.yaml +++ b/dts/bindings/can/nxp,flexcan.yaml @@ -13,7 +13,6 @@ description: | interrupt-names = "warning", "error", "wake-up", "mb-0-15"; clocks = <&scg KINETIS_SCG_BUS_CLK>; clk-source = <1>; - sample-point = <875>; bus-speed = <125000>; pinctrl-0 = <&pinmux_flexcan0>; pinctrl-names = "default"; diff --git a/dts/bindings/can/ti,tcan4x5x.yaml b/dts/bindings/can/ti,tcan4x5x.yaml index 8f57f66ae85..5c74989093c 100644 --- a/dts/bindings/can/ti,tcan4x5x.yaml +++ b/dts/bindings/can/ti,tcan4x5x.yaml @@ -16,8 +16,6 @@ description: | reset-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; int-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; bosch,mram-cfg = <0x0 15 15 5 5 0 10 10>; - sample-point = <875>; - sample-point-data = <875>; bus-speed = <125000>; bus-speed-data = <1000000>; status = "okay"; diff --git a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi index caee77fc6ef..6ad2f612866 100644 --- a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi +++ b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi @@ -218,7 +218,6 @@ interrupts = ; interrupt-parent = <&intc>; clocks = <&rtc ESP32_TWAI_MODULE>; - sample-point = <875>; status = "disabled"; }; diff --git a/dts/xtensa/espressif/esp32/esp32_common.dtsi b/dts/xtensa/espressif/esp32/esp32_common.dtsi index b7aba9f2350..6fff7be912a 100644 --- a/dts/xtensa/espressif/esp32/esp32_common.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_common.dtsi @@ -354,7 +354,6 @@ interrupts = ; interrupt-parent = <&intc>; clocks = <&rtc ESP32_TWAI_MODULE>; - sample-point = <875>; status = "disabled"; }; diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi index 727b26e4a53..1bb8c000ed5 100644 --- a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi +++ b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi @@ -339,7 +339,6 @@ interrupts = ; interrupt-parent = <&intc>; clocks = <&rtc ESP32_TWAI_MODULE>; - sample-point = <875>; status = "disabled"; }; }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi index 27a90f797d0..a879187cbd4 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi @@ -281,7 +281,6 @@ interrupts = ; interrupt-parent = <&intc>; clocks = <&rtc ESP32_TWAI_MODULE>; - sample-point = <875>; status = "disabled"; }; diff --git a/tests/drivers/can/shell/app.overlay b/tests/drivers/can/shell/app.overlay index 2e6c8c99790..5d9827e2f35 100644 --- a/tests/drivers/can/shell/app.overlay +++ b/tests/drivers/can/shell/app.overlay @@ -8,10 +8,7 @@ fake_can: fake_can { compatible = "zephyr,fake-can"; status = "okay"; - sample-point = <875>; bus-speed = <125000>; - sample-point = <875>; bus-speed-data = <1000000>; - sample-point-data = <750>; }; }; diff --git a/tests/lib/devicetree/api/app.overlay b/tests/lib/devicetree/api/app.overlay index 03f14f50389..5ee7171d932 100644 --- a/tests/lib/devicetree/api/app.overlay +++ b/tests/lib/devicetree/api/app.overlay @@ -528,7 +528,6 @@ test_can0: can@55553333 { compatible = "vnd,can-controller"; reg = < 0x55553333 0x1000 >; - sample-point = <875>; bus-speed = <125000>; status = "okay"; phys = <&test_transceiver0>; @@ -537,7 +536,6 @@ test_can1: can@55554444 { compatible = "vnd,can-controller"; reg = < 0x55554444 0x1000 >; - sample-point = <875>; bus-speed = <125000>; status = "okay"; @@ -550,7 +548,6 @@ test_can2: can@55555555 { compatible = "vnd,can-controller"; reg = < 0x55555555 0x1000 >; - sample-point = <875>; bus-speed = <125000>; status = "okay"; @@ -562,7 +559,6 @@ test_can3: can@55557777 { compatible = "vnd,can-controller"; reg = < 0x55556666 0x1000 >; - sample-point = <875>; bus-speed = <125000>; status = "okay"; phys = <&test_transceiver1>; From 2f6b41a694ee47dac5c431a81b7673026b0908c3 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Wed, 6 Mar 2024 22:27:37 +0100 Subject: [PATCH 0851/2402] doc: releases: release-notes: 3.7: mention optional CAN DTS properties Add a note about the ``sample-point`` and ``sample-point-data`` CAN devicetree properties now being optional. Signed-off-by: Henrik Brix Andersen --- doc/releases/release-notes-3.7.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index ddbf8a3e98c..542ac776f26 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -87,6 +87,7 @@ Drivers and Sensors supported bitrate of a CAN controller/transceiver combination. * Updated the CAN timing functions to take the minimum supported bitrate into consideration when validating the bitrate. + * Made the ``sample-point`` and ``sample-point-data`` devicetree properties optional. * Clock control From a55f67d2840dc66c207f83a4dc106d2059e3a067 Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Thu, 14 Mar 2024 09:02:31 +0100 Subject: [PATCH 0852/2402] drivers: misc: nordic_vpr_launcher: Update src/exec memory size check Firstly, build-asserting the execution/source memory sizes to be equal wasn't working, due to the wrong (non-inst) DT API being used. Secondly, this assert can be relaxed so that the source memory region only needs to have greater than or equal size to the execution region, as VPR firmware needs to fit into execution memory first and foremost. This will come in handy, since MRAM partitions (typical source memory) have stricter alignment requirements than RAM regions. Signed-off-by: Grzegorz Swiderski --- .../nordic_vpr_launcher/nordic_vpr_launcher.c | 24 +++++++++---------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c b/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c index 64d4969081b..11b75a2c0e5 100644 --- a/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c +++ b/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c @@ -22,7 +22,7 @@ struct nordic_vpr_launcher_config { uintptr_t exec_addr; #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(source_memory) uintptr_t src_addr; - size_t src_size; + size_t size; #endif }; @@ -31,10 +31,10 @@ static int nordic_vpr_launcher_init(const struct device *dev) const struct nordic_vpr_launcher_config *config = dev->config; #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(source_memory) - if (config->src_size > 0U) { + if (config->size > 0U) { LOG_DBG("Loading VPR (%p) from %p to %p (%zu bytes)", config->vpr, - (void *)config->src_addr, (void *)config->exec_addr, config->src_size); - memcpy((void *)config->exec_addr, (void *)config->src_addr, config->src_size); + (void *)config->src_addr, (void *)config->exec_addr, config->size); + memcpy((void *)config->exec_addr, (void *)config->src_addr, config->size); } #endif @@ -51,19 +51,17 @@ static int nordic_vpr_launcher_init(const struct device *dev) COND_CODE_0(DT_FIXED_PARTITION_EXISTS(node_id), (0), (DT_REG_ADDR(DT_GPARENT(node_id))))) #define NORDIC_VPR_LAUNCHER_DEFINE(inst) \ - COND_CODE_1(DT_NODE_HAS_PROP(inst, source_memory), \ - (BUILD_ASSERT((DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)) == \ - DT_REG_SIZE(DT_INST_PHANDLE(inst, source_memory))), \ - "Source/execution memory sizes mismatch");), \ - ()) \ + IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, source_memory), \ + (BUILD_ASSERT((DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)) <= \ + DT_REG_SIZE(DT_INST_PHANDLE(inst, source_memory))), \ + "Execution memory exceeds source memory size");)) \ \ static const struct nordic_vpr_launcher_config config##inst = { \ .vpr = (NRF_VPR_Type *)DT_INST_REG_ADDR(inst), \ .exec_addr = VPR_ADDR(DT_INST_PHANDLE(inst, execution_memory)), \ - COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, source_memory), \ - (.src_addr = VPR_ADDR(DT_INST_PHANDLE(inst, source_memory)), \ - .src_size = DT_REG_SIZE(DT_INST_PHANDLE(inst, source_memory)),), \ - ())}; \ + IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, source_memory), \ + (.src_addr = VPR_ADDR(DT_INST_PHANDLE(inst, source_memory)), \ + .size = DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)),))}; \ \ DEVICE_DT_INST_DEFINE(inst, nordic_vpr_launcher_init, NULL, NULL, &config##inst, \ POST_KERNEL, CONFIG_NORDIC_VPR_LAUNCHER_INIT_PRIORITY, NULL); From 303c56fbb2d23aab6d6e55263caec581b63f0df6 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 26 Feb 2024 08:38:10 +0100 Subject: [PATCH 0853/2402] net: ip: Add helper NET_NATIVE_IP kconfig symbol Introduce a NET_NATIVE_IP symbol similar to IPv4/IPv6 variants. Signed-off-by: Pieter De Gendt --- subsys/net/ip/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/subsys/net/ip/Kconfig b/subsys/net/ip/Kconfig index 5ffba57a691..a673c6524b0 100644 --- a/subsys/net/ip/Kconfig +++ b/subsys/net/ip/Kconfig @@ -33,6 +33,11 @@ config NET_NATIVE # Hidden options for enabling native IPv6/IPv4. Using these options # avoids having "defined(CONFIG_NET_IPV6) && defined(CONFIG_NET_NATIVE)" # in the code as we can have "defined(CONFIG_NET_NATIVE_IPV6)" instead. +config NET_NATIVE_IP + bool + depends on NET_NATIVE + default y if NET_IP + config NET_NATIVE_IPV6 bool depends on NET_NATIVE From 63133be42cc63a44a43e52cbd23b722f0c823055 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Fri, 23 Feb 2024 11:57:10 +0100 Subject: [PATCH 0854/2402] net: iface: Allow catch-all multicast monitor Registering a multicast monitor with a NULL interface will receive all events. Signed-off-by: Pieter De Gendt --- include/zephyr/net/net_if.h | 2 +- subsys/net/ip/net_if.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/zephyr/net/net_if.h b/include/zephyr/net/net_if.h index bab22da1c05..91f1aa63285 100644 --- a/include/zephyr/net/net_if.h +++ b/include/zephyr/net/net_if.h @@ -1498,7 +1498,7 @@ struct net_if_mcast_monitor { * * @param mon Monitor handle. This is a pointer to a monitor storage structure * which should be allocated by caller, but does not need to be initialized. - * @param iface Network interface + * @param iface Network interface or NULL for all interfaces * @param cb Monitor callback */ void net_if_mcast_mon_register(struct net_if_mcast_monitor *mon, diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 70b21d6b866..36acfcb50f6 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -994,7 +994,7 @@ void net_if_mcast_monitor(struct net_if *iface, SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&mcast_monitor_callbacks, mon, tmp, node) { - if (iface == mon->iface) { + if (iface == mon->iface || mon->iface == NULL) { mon->cb(iface, addr, is_joined); } } From 64bc6187253a6efe48e40525bacca101c7644e8f Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Fri, 23 Feb 2024 12:10:16 +0100 Subject: [PATCH 0855/2402] net: ethernet: mgmt: Add HW MAC address filtering Add an ethernet management API to set or unset HW MAC address filtering. Signed-off-by: Pieter De Gendt --- include/zephyr/net/ethernet.h | 12 ++++++++++++ include/zephyr/net/ethernet_mgmt.h | 8 ++++++++ subsys/net/l2/ethernet/ethernet.c | 26 ++++++++++++++++++++++++++ subsys/net/l2/ethernet/ethernet_mgmt.c | 10 ++++++++++ 4 files changed, 56 insertions(+) diff --git a/include/zephyr/net/ethernet.h b/include/zephyr/net/ethernet.h index faa6cf7fc0b..b1f4ebe7498 100644 --- a/include/zephyr/net/ethernet.h +++ b/include/zephyr/net/ethernet.h @@ -1045,6 +1045,18 @@ int net_eth_promisc_mode(struct net_if *iface, bool enable); */ int net_eth_txinjection_mode(struct net_if *iface, bool enable); +/** + * @brief Set or unset HW filtering for MAC address @p mac. + * + * @param iface Network interface + * @param mac Pointer to an ethernet MAC address + * @param type Filter type, either source or destination + * @param enable Set (true) or unset (false) + * + * @return 0 if filter set or unset was successful, <0 otherwise. + */ +int net_eth_mac_filter(struct net_if *iface, struct net_eth_addr *mac, + enum ethernet_filter_type type, bool enable); /** * @brief Return PTP clock that is tied to this ethernet network interface. * diff --git a/include/zephyr/net/ethernet_mgmt.h b/include/zephyr/net/ethernet_mgmt.h index 18039e9f3aa..ae339b68577 100644 --- a/include/zephyr/net/ethernet_mgmt.h +++ b/include/zephyr/net/ethernet_mgmt.h @@ -54,6 +54,7 @@ enum net_request_ethernet_cmd { NET_REQUEST_ETHERNET_CMD_SET_T1S_PARAM, NET_REQUEST_ETHERNET_CMD_SET_TXINJECTION_MODE, NET_REQUEST_ETHERNET_CMD_GET_TXINJECTION_MODE, + NET_REQUEST_ETHERNET_CMD_SET_MAC_FILTER, }; #define NET_REQUEST_ETHERNET_SET_AUTO_NEGOTIATION \ @@ -146,6 +147,11 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_ETHERNET_SET_TXINJECTION_MODE); NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_ETHERNET_GET_TXINJECTION_MODE); +#define NET_REQUEST_ETHERNET_SET_MAC_FILTER \ + (_NET_ETHERNET_BASE | NET_REQUEST_ETHERNET_CMD_SET_MAC_FILTER) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_ETHERNET_SET_MAC_FILTER); + struct net_eth_addr; struct ethernet_qav_param; struct ethernet_qbv_param; @@ -173,6 +179,8 @@ struct ethernet_req_params { struct ethernet_txtime_param txtime_param; struct ethernet_t1s_param t1s_param; + struct ethernet_filter filter; + int priority_queues_num; int ports_num; }; diff --git a/subsys/net/l2/ethernet/ethernet.c b/subsys/net/l2/ethernet/ethernet.c index 70cc81bd32d..dc9523989dd 100644 --- a/subsys/net/l2/ethernet/ethernet.c +++ b/subsys/net/l2/ethernet/ethernet.c @@ -1215,6 +1215,32 @@ int net_eth_txinjection_mode(struct net_if *iface, bool enable) ¶ms, sizeof(struct ethernet_req_params)); } +int net_eth_mac_filter(struct net_if *iface, struct net_eth_addr *mac, + enum ethernet_filter_type type, bool enable) +{ +#ifdef CONFIG_NET_L2_ETHERNET_MGMT + struct ethernet_req_params params; + + if (!(net_eth_get_hw_capabilities(iface) & ETHERNET_HW_FILTERING)) { + return -ENOTSUP; + } + + memcpy(¶ms.filter.mac_address, mac, sizeof(struct net_eth_addr)); + params.filter.type = type; + params.filter.set = enable; + + return net_mgmt(NET_REQUEST_ETHERNET_SET_MAC_FILTER, iface, ¶ms, + sizeof(struct ethernet_req_params)); +#else + ARG_UNUSED(iface); + ARG_UNUSED(mac); + ARG_UNUSED(type); + ARG_UNUSED(enable); + + return -ENOTSUP; +#endif +} + void ethernet_init(struct net_if *iface) { struct ethernet_context *ctx = net_if_l2_data(iface); diff --git a/subsys/net/l2/ethernet/ethernet_mgmt.c b/subsys/net/l2/ethernet/ethernet_mgmt.c index 899aa7a9516..5078c07dbca 100644 --- a/subsys/net/l2/ethernet/ethernet_mgmt.c +++ b/subsys/net/l2/ethernet/ethernet_mgmt.c @@ -207,6 +207,13 @@ static int ethernet_set_config(uint32_t mgmt_request, config.txinjection_mode = params->txinjection_mode; type = ETHERNET_CONFIG_TYPE_TXINJECTION_MODE; + } else if (mgmt_request == NET_REQUEST_ETHERNET_SET_MAC_FILTER) { + if (!is_hw_caps_supported(dev, ETHERNET_HW_FILTERING)) { + return -ENOTSUP; + } + + memcpy(&config.filter, ¶ms->filter, sizeof(struct ethernet_filter)); + type = ETHERNET_CONFIG_TYPE_FILTER; } else { return -EINVAL; } @@ -247,6 +254,9 @@ NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_ETHERNET_SET_T1S_PARAM, NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_ETHERNET_SET_TXINJECTION_MODE, ethernet_set_config); +NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_ETHERNET_SET_MAC_FILTER, + ethernet_set_config); + static int ethernet_get_config(uint32_t mgmt_request, struct net_if *iface, void *data, size_t len) From af8ba2a361adb7fb9d544258428f4de61765f2f9 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Fri, 23 Feb 2024 12:11:48 +0100 Subject: [PATCH 0856/2402] net: ethernet: Register multicast monitor for MAC filtering Register a multicast monitor for ethernet if HW MAC filtering is supported Signed-off-by: Pieter De Gendt --- subsys/net/l2/ethernet/ethernet.c | 54 +++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/subsys/net/l2/ethernet/ethernet.c b/subsys/net/l2/ethernet/ethernet.c index dc9523989dd..972ad0812cc 100644 --- a/subsys/net/l2/ethernet/ethernet.c +++ b/subsys/net/l2/ethernet/ethernet.c @@ -37,6 +37,10 @@ static const struct net_eth_addr multicast_eth_addr __unused = { static const struct net_eth_addr broadcast_eth_addr = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } }; +#if defined(CONFIG_NET_NATIVE_IP) && !defined(CONFIG_NET_RAW_MODE) +static struct net_if_mcast_monitor mcast_monitor; +#endif + const struct net_eth_addr *net_eth_broadcast_addr(void) { return &broadcast_eth_addr; @@ -183,6 +187,50 @@ enum net_verdict ethernet_check_ipv4_bcast_addr(struct net_pkt *pkt, return NET_OK; } +#if defined(CONFIG_NET_NATIVE_IP) && !defined(CONFIG_NET_RAW_MODE) +static void ethernet_mcast_monitor_cb(struct net_if *iface, const struct net_addr *addr, + bool is_joined) +{ + struct ethernet_config cfg = { + .filter = { + .set = is_joined, + .type = ETHERNET_FILTER_TYPE_DST_MAC_ADDRESS, + }, + }; + const struct device *dev; + const struct ethernet_api *api; + + /* Make sure we're an ethernet device */ + if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { + return; + } + + dev = net_if_get_device(iface); + api = dev->api; + + if (!(api->get_capabilities(dev) & ETHERNET_HW_FILTERING) || api->set_config == NULL) { + return; + } + + switch (addr->family) { +#if defined(CONFIG_NET_IPV4) + case AF_INET: + net_eth_ipv4_mcast_to_mac_addr(&addr->in_addr, &cfg.filter.mac_address); + break; +#endif /* CONFIG_NET_IPV4 */ +#if defined(CONFIG_NET_IPV6) + case AF_INET6: + net_eth_ipv6_mcast_to_mac_addr(&addr->in6_addr, &cfg.filter.mac_address); + break; +#endif /* CONFIG_NET_IPV6 */ + default: + return; + } + + api->set_config(dev, ETHERNET_CONFIG_TYPE_FILTER, &cfg); +} +#endif + static enum net_verdict ethernet_recv(struct net_if *iface, struct net_pkt *pkt) { @@ -1259,6 +1307,12 @@ void ethernet_init(struct net_if *iface) ctx->ethernet_l2_flags |= NET_L2_PROMISC_MODE; } +#if defined(CONFIG_NET_NATIVE_IP) && !defined(CONFIG_NET_RAW_MODE) + if (net_eth_get_hw_capabilities(iface) & ETHERNET_HW_FILTERING) { + net_if_mcast_mon_register(&mcast_monitor, NULL, ethernet_mcast_monitor_cb); + } +#endif + #if defined(CONFIG_NET_VLAN) if (!(net_eth_get_hw_capabilities(iface) & ETHERNET_HW_VLAN)) { return; From d052822d5da390f5ac86afe551d922a0d56cae25 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Fri, 23 Feb 2024 12:13:17 +0100 Subject: [PATCH 0857/2402] drivers: ethernet: eth_mcux: Implement HW MAC address filtering Replace the multicast monitor with a HW MAC filter configuration. Signed-off-by: Pieter De Gendt --- drivers/ethernet/eth_mcux.c | 42 ++++++++++--------------------------- 1 file changed, 11 insertions(+), 31 deletions(-) diff --git a/drivers/ethernet/eth_mcux.c b/drivers/ethernet/eth_mcux.c index a00b7ff57cc..9751ab2e44c 100644 --- a/drivers/ethernet/eth_mcux.c +++ b/drivers/ethernet/eth_mcux.c @@ -1165,42 +1165,11 @@ static int eth_init(const struct device *dev) return 0; } -#if defined(CONFIG_NET_NATIVE_IPV4) || defined(CONFIG_NET_NATIVE_IPV6) -static void net_if_mcast_cb(struct net_if *iface, - const struct net_addr *addr, - bool is_joined) -{ - const struct device *dev = net_if_get_device(iface); - struct eth_context *context = dev->data; - struct net_eth_addr mac_addr; - - if (IS_ENABLED(CONFIG_NET_IPV4) && addr->family == AF_INET) { - net_eth_ipv4_mcast_to_mac_addr(&addr->in_addr, &mac_addr); - } else if (IS_ENABLED(CONFIG_NET_IPV6) && addr->family == AF_INET6) { - net_eth_ipv6_mcast_to_mac_addr(&addr->in6_addr, &mac_addr); - } else { - return; - } - - if (is_joined) { - ENET_AddMulticastGroup(context->base, mac_addr.addr); - } else { - ENET_LeaveMulticastGroup(context->base, mac_addr.addr); - } -} -#endif /* CONFIG_NET_NATIVE_IPV4 || CONFIG_NET_NATIVE_IPV6 */ - static void eth_iface_init(struct net_if *iface) { const struct device *dev = net_if_get_device(iface); struct eth_context *context = dev->data; -#if defined(CONFIG_NET_NATIVE_IPV4) || defined(CONFIG_NET_NATIVE_IPV6) - static struct net_if_mcast_monitor mon; - - net_if_mcast_mon_register(&mon, iface, net_if_mcast_cb); -#endif /* CONFIG_NET_NATIVE_IPV4 || CONFIG_NET_NATIVE_IPV6 */ - net_if_set_link_addr(iface, context->mac_addr, sizeof(context->mac_addr), NET_LINK_ETHERNET); @@ -1227,6 +1196,7 @@ static enum ethernet_hw_caps eth_mcux_get_capabilities(const struct device *dev) ARG_UNUSED(dev); return ETHERNET_HW_VLAN | ETHERNET_LINK_10BASE_T | + ETHERNET_HW_FILTERING | #if defined(CONFIG_PTP_CLOCK_MCUX) ETHERNET_PTP | #endif @@ -1262,6 +1232,16 @@ static int eth_mcux_set_config(const struct device *dev, context->mac_addr[2], context->mac_addr[3], context->mac_addr[4], context->mac_addr[5]); return 0; + case ETHERNET_CONFIG_TYPE_FILTER: + /* The ENET driver does not modify the address buffer but the API is not const */ + if (config->filter.set) { + ENET_AddMulticastGroup(context->base, + (uint8_t *)config->filter.mac_address.addr); + } else { + ENET_LeaveMulticastGroup(context->base, + (uint8_t *)config->filter.mac_address.addr); + } + return 0; default: break; } From a3f74ac50e56d1ce44392b0b30056ff642b6f0e1 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Fri, 23 Feb 2024 15:56:21 +0100 Subject: [PATCH 0858/2402] drivers: ethernet: eth_nxp_s32_gmac: Fix multicast filter Update multicast filter with HW filtering and fix missing CONFIG_ prefix. Signed-off-by: Pieter De Gendt --- drivers/ethernet/eth_nxp_s32_gmac.c | 49 +++++++++-------------------- 1 file changed, 14 insertions(+), 35 deletions(-) diff --git a/drivers/ethernet/eth_nxp_s32_gmac.c b/drivers/ethernet/eth_nxp_s32_gmac.c index e6efb3f72c7..6a7af367ae2 100644 --- a/drivers/ethernet/eth_nxp_s32_gmac.c +++ b/drivers/ethernet/eth_nxp_s32_gmac.c @@ -296,46 +296,11 @@ static int eth_nxp_s32_stop(const struct device *dev) return err; } -#if defined(ETH_NXP_S32_MULTICAST_FILTER) -static void eth_nxp_s32_mcast_cb(struct net_if *iface, const struct net_addr *addr, bool is_joined) -{ - const struct device *dev = net_if_get_device(iface); - const struct eth_nxp_s32_config *cfg = dev->config; - struct net_eth_addr mac_addr; - - switch (addr->family) { -#if defined(CONFIG_NET_IPV4) - case AF_INET: - net_eth_ipv4_mcast_to_mac_addr(&addr->in_addr, &mac_addr); - break; -#endif /* CONFIG_NET_IPV4 */ -#if defined(CONFIG_NET_IPV6) - case AF_INET6: - net_eth_ipv6_mcast_to_mac_addr(&addr->in6_addr, &mac_addr); - break; -#endif /* CONFIG_NET_IPV6 */ - default: - return -EINVAL; - } - - if (is_joined) { - Gmac_Ip_AddDstAddrToHashFilter(cfg->instance, mac_addr.addr); - } else { - Gmac_Ip_RemoveDstAddrFromHashFilter(cfg->instance, mac_addr.addr); - } -} -#endif /* ETH_NXP_S32_MULTICAST_FILTER */ - static void eth_nxp_s32_iface_init(struct net_if *iface) { const struct device *dev = net_if_get_device(iface); const struct eth_nxp_s32_config *cfg = dev->config; struct eth_nxp_s32_data *ctx = dev->data; -#if defined(ETH_NXP_S32_MULTICAST_FILTER) - static struct net_if_mcast_monitor mon; - - net_if_mcast_mon_register(&mon, iface, eth_nxp_s32_mcast_cb); -#endif /* ETH_NXP_S32_MULTICAST_FILTER */ /* For VLAN, this value is only used to get the correct L2 driver. * The iface pointer in context should contain the main interface @@ -603,6 +568,17 @@ static int eth_nxp_s32_set_config(const struct device *dev, res = -EALREADY; } break; +#endif +#if defined(CONFIG_ETH_NXP_S32_MULTICAST_FILTER) + case ETHERNET_HW_FILTERING: + if (config->filter.set) { + Gmac_Ip_AddDstAddrToHashFilter(cfg->instance, + config->filter.mac_address.addr); + } else { + Gmac_Ip_RemoveDstAddrFromHashFilter(cfg->instance, + config->filter.mac_address.addr); + } + break; #endif default: res = -ENOTSUP; @@ -629,6 +605,9 @@ static enum ethernet_hw_caps eth_nxp_s32_get_capabilities(const struct device *d #endif #if defined(CONFIG_NET_PROMISCUOUS_MODE) | ETHERNET_PROMISC_MODE +#endif +#if defined(CONFIG_ETH_NXP_S32_MULTICAST_FILTER) + | ETHERNET_HW_FILTERING #endif ); } From 28e10630c2378116856f13446f9288d50c279eaf Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 26 Feb 2024 09:24:16 +0100 Subject: [PATCH 0859/2402] drivers: ethernet: eth_enet: Implement HW MAC address filtering Replace the multicast monitor with a HW MAC filter configuration. Signed-off-by: Pieter De Gendt --- drivers/ethernet/eth_nxp_enet.c | 37 ++++++++++----------------------- 1 file changed, 11 insertions(+), 26 deletions(-) diff --git a/drivers/ethernet/eth_nxp_enet.c b/drivers/ethernet/eth_nxp_enet.c index 864a488f554..0679e377467 100644 --- a/drivers/ethernet/eth_nxp_enet.c +++ b/drivers/ethernet/eth_nxp_enet.c @@ -124,29 +124,6 @@ static inline struct net_if *get_iface(struct nxp_enet_mac_data *data, uint16_t return iface ? iface : data->iface; } -static void net_if_mcast_cb(struct net_if *iface, - const struct net_addr *addr, - bool is_joined) -{ - const struct device *dev = net_if_get_device(iface); - const struct nxp_enet_mac_config *config = dev->config; - struct net_eth_addr mac_addr; - - if (IS_ENABLED(CONFIG_NET_IPV4) && addr->family == AF_INET) { - net_eth_ipv4_mcast_to_mac_addr(&addr->in_addr, &mac_addr); - } else if (IS_ENABLED(CONFIG_NET_IPV6) && addr->family == AF_INET6) { - net_eth_ipv6_mcast_to_mac_addr(&addr->in6_addr, &mac_addr); - } else { - return; - } - - if (is_joined) { - ENET_AddMulticastGroup(config->base, mac_addr.addr); - } else { - ENET_LeaveMulticastGroup(config->base, mac_addr.addr); - } -} - #if defined(CONFIG_PTP_CLOCK_NXP_ENET) static bool eth_get_ptp_data(struct net_if *iface, struct net_pkt *pkt) { @@ -266,9 +243,6 @@ static void eth_nxp_enet_iface_init(struct net_if *iface) const struct device *dev = net_if_get_device(iface); struct nxp_enet_mac_data *data = dev->data; const struct nxp_enet_mac_config *config = dev->config; - static struct net_if_mcast_monitor mon; - - net_if_mcast_mon_register(&mon, iface, net_if_mcast_cb); net_if_set_link_addr(iface, data->mac_addr, sizeof(data->mac_addr), @@ -297,6 +271,7 @@ static enum ethernet_hw_caps eth_nxp_enet_get_capabilities(const struct device * ARG_UNUSED(dev); return ETHERNET_HW_VLAN | ETHERNET_LINK_10BASE_T | + ETHERNET_HW_FILTERING | #if defined(CONFIG_PTP_CLOCK_NXP_ENET) ETHERNET_PTP | #endif @@ -332,6 +307,16 @@ static int eth_nxp_enet_set_config(const struct device *dev, data->mac_addr[2], data->mac_addr[3], data->mac_addr[4], data->mac_addr[5]); return 0; + case ETHERNET_CONFIG_TYPE_FILTER: + /* The ENET driver does not modify the address buffer but the API is not const */ + if (cfg->filter.set) { + ENET_AddMulticastGroup(config->base, + (uint8_t *)cfg->filter.mac_address.addr); + } else { + ENET_LeaveMulticastGroup(config->base, + (uint8_t *)cfg->filter.mac_address.addr); + } + return 0; default: break; } From f900bfc3decbe4e6f1a9e40da89efb0711550e37 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Fri, 1 Mar 2024 10:58:53 +0100 Subject: [PATCH 0860/2402] drivers: ethernet: eth_stm32: Rework HW MAC address filtering Rework the driver to use HW MAC address filtering as an ethernet capability. Use a counter table for CRC indexes added/removed. Signed-off-by: Pieter De Gendt --- drivers/ethernet/eth_stm32_hal.c | 189 ++++---------------------- drivers/ethernet/eth_stm32_hal_priv.h | 3 + 2 files changed, 29 insertions(+), 163 deletions(-) diff --git a/drivers/ethernet/eth_stm32_hal.c b/drivers/ethernet/eth_stm32_hal.c index b9d4c19186d..fcea86e4049 100644 --- a/drivers/ethernet/eth_stm32_hal.c +++ b/drivers/ethernet/eth_stm32_hal.c @@ -100,22 +100,6 @@ static ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB] __eth_stm32_desc; static uint8_t dma_rx_buffer[ETH_RXBUFNB][ETH_STM32_RX_BUF_SIZE] __eth_stm32_buf; static uint8_t dma_tx_buffer[ETH_TXBUFNB][ETH_STM32_TX_BUF_SIZE] __eth_stm32_buf; -#if defined(CONFIG_ETH_STM32_MULTICAST_FILTER) - -static struct net_if_mcast_monitor mcast_monitor; - -static K_MUTEX_DEFINE(multicast_addr_lock); - -#if defined(CONFIG_NET_NATIVE_IPV6) -static struct in6_addr multicast_ipv6_joined_addrs[NET_IF_MAX_IPV6_MADDR] = {0}; -#endif /* CONFIG_NET_NATIVE_IPV6 */ - -#if defined(CONFIG_NET_NATIVE_IPV4) -static struct in_addr multicast_ipv4_joined_addrs[NET_IF_MAX_IPV4_MADDR] = {0}; -#endif /* CONFIG_NET_NATIVE_IPV4 */ - -#endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */ - #if defined(CONFIG_ETH_STM32_HAL_API_V2) BUILD_ASSERT(ETH_STM32_RX_BUF_SIZE % 4 == 0, "Rx buffer size must be a multiple of 4"); @@ -1305,62 +1289,6 @@ static int eth_initialize(const struct device *dev) } #if defined(CONFIG_ETH_STM32_MULTICAST_FILTER) - -#if defined(CONFIG_NET_NATIVE_IPV6) -static void add_ipv6_multicast_addr(const struct in6_addr *addr) -{ - uint32_t i; - - for (i = 0; i < NET_IF_MAX_IPV6_MADDR; i++) { - if (net_ipv6_is_addr_unspecified(&multicast_ipv6_joined_addrs[i])) { - net_ipv6_addr_copy_raw((uint8_t *)&multicast_ipv6_joined_addrs[i], - (uint8_t *)addr); - break; - } - } -} - -static void remove_ipv6_multicast_addr(const struct in6_addr *addr) -{ - uint32_t i; - - for (i = 0; i < NET_IF_MAX_IPV6_MADDR; i++) { - if (net_ipv6_addr_cmp(&multicast_ipv6_joined_addrs[i], addr)) { - net_ipv6_addr_copy_raw((uint8_t *)&multicast_ipv6_joined_addrs[i], - (uint8_t *)net_ipv6_unspecified_address); - break; - } - } -} -#endif /* CONFIG_NET_NATIVE_IPV6 */ - -#if defined(CONFIG_NET_NATIVE_IPV4) -static void add_ipv4_multicast_addr(const struct in_addr *addr) -{ - uint32_t i; - - for (i = 0; i < NET_IF_MAX_IPV4_MADDR; i++) { - if (net_ipv4_is_addr_unspecified(&multicast_ipv4_joined_addrs[i])) { - net_ipv4_addr_copy_raw((uint8_t *)&multicast_ipv4_joined_addrs[i], - (uint8_t *)addr); - break; - } - } -} - -static void remove_ipv4_multicast_addr(const struct in_addr *addr) -{ - uint32_t i; - - for (i = 0; i < NET_IF_MAX_IPV4_MADDR; i++) { - if (net_ipv4_addr_cmp(&multicast_ipv4_joined_addrs[i], addr)) { - multicast_ipv4_joined_addrs[i].s_addr = 0; - break; - } - } -} -#endif /* CONFIG_NET_NATIVE_IPV4 */ - static uint32_t reverse(uint32_t val) { uint32_t res = 0; @@ -1375,112 +1303,43 @@ static uint32_t reverse(uint32_t val) return res; } -static void net_if_stm32_mcast_cb(struct net_if *iface, - const struct net_addr *addr, - bool is_joined) +static void eth_stm32_mcast_filter(const struct device *dev, const struct ethernet_filter *filter) { - ARG_UNUSED(addr); - - const struct device *dev; - struct eth_stm32_hal_dev_data *dev_data; + struct eth_stm32_hal_dev_data *dev_data = (struct eth_stm32_hal_dev_data *)dev->data; ETH_HandleTypeDef *heth; - struct net_eth_addr mac_addr; uint32_t crc; uint32_t hash_table[2]; uint32_t hash_index; - int i; - - dev = net_if_get_device(iface); - - dev_data = (struct eth_stm32_hal_dev_data *)dev->data; heth = &dev_data->heth; - hash_table[0] = 0; - hash_table[1] = 0; + crc = reverse(crc32_ieee(filter->mac_address.addr, sizeof(struct net_eth_addr))); + hash_index = (crc >> 26) & 0x3f; + + __ASSERT_NO_MSG(hash_index < ARRAY_SIZE(dev_data->hash_index_cnt)); - if (is_joined) { - /* Save a copy of the hash table which we update with - * the hash for a single multicast address for join - */ #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X) - hash_table[0] = heth->Instance->MACHT0R; - hash_table[1] = heth->Instance->MACHT1R; + hash_table[0] = heth->Instance->MACHT0R; + hash_table[1] = heth->Instance->MACHT1R; #else - hash_table[0] = heth->Instance->MACHTLR; - hash_table[1] = heth->Instance->MACHTHR; + hash_table[0] = heth->Instance->MACHTLR; + hash_table[1] = heth->Instance->MACHTHR; #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */ - } - - k_mutex_lock(&multicast_addr_lock, K_FOREVER); -#if defined(CONFIG_NET_NATIVE_IPV6) - if (is_joined) { - /* When joining only update the hash filter with the joining - * multicast address. - */ - add_ipv6_multicast_addr(&addr->in6_addr); - - net_eth_ipv6_mcast_to_mac_addr(&addr->in6_addr, &mac_addr); - crc = reverse(crc32_ieee(mac_addr.addr, - sizeof(struct net_eth_addr))); - hash_index = (crc >> 26) & 0x3f; + if (filter->set) { + dev_data->hash_index_cnt[hash_index]++; hash_table[hash_index / 32] |= (1 << (hash_index % 32)); } else { - /* When leaving its better to compute the full hash table - * for all the multicast addresses that we're aware of. - */ - remove_ipv6_multicast_addr(&addr->in6_addr); - - for (i = 0; i < NET_IF_MAX_IPV6_MADDR; i++) { - if (net_ipv6_is_addr_unspecified(&multicast_ipv6_joined_addrs[i])) { - continue; - } - - net_eth_ipv6_mcast_to_mac_addr(&multicast_ipv6_joined_addrs[i], - &mac_addr); - crc = reverse(crc32_ieee(mac_addr.addr, - sizeof(struct net_eth_addr))); - hash_index = (crc >> 26) & 0x3f; - hash_table[hash_index / 32] |= (1 << (hash_index % 32)); + if (dev_data->hash_index_cnt[hash_index] == 0) { + __ASSERT_NO_MSG(false); + return; } - } -#endif /* CONFIG_NET_IPV6 */ -#if defined(CONFIG_NET_NATIVE_IPV4) - if (is_joined) { - /* When joining only update the hash filter with the joining - * multicast address. - */ - add_ipv4_multicast_addr(&addr->in_addr); - - net_eth_ipv4_mcast_to_mac_addr(&addr->in_addr, &mac_addr); - crc = reverse(crc32_ieee(mac_addr.addr, - sizeof(struct net_eth_addr))); - hash_index = (crc >> 26) & 0x3f; - hash_table[hash_index / 32] |= (1 << (hash_index % 32)); - } else { - /* When leaving its better to compute the full hash table - * for all the multicast addresses that we're aware of. - */ - remove_ipv4_multicast_addr(&addr->in_addr); - - for (i = 0; i < NET_IF_MAX_IPV4_MADDR; i++) { - if (net_ipv4_is_addr_unspecified(&multicast_ipv4_joined_addrs[i])) { - continue; - } - - net_eth_ipv4_mcast_to_mac_addr(&multicast_ipv4_joined_addrs[i], - &mac_addr); - crc = reverse(crc32_ieee(mac_addr.addr, - sizeof(struct net_eth_addr))); - hash_index = (crc >> 26) & 0x3f; - hash_table[hash_index / 32] |= (1 << (hash_index % 32)); + dev_data->hash_index_cnt[hash_index]--; + if (dev_data->hash_index_cnt[hash_index] == 0) { + hash_table[hash_index / 32] &= ~(1 << (hash_index % 32)); } } -#endif /* CONFIG_NET_IPV4 */ - - k_mutex_unlock(&multicast_addr_lock); #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X) heth->Instance->MACHT0R = hash_table[0]; @@ -1516,10 +1375,6 @@ static void eth_iface_init(struct net_if *iface) is_first_init = true; } -#if defined(CONFIG_ETH_STM32_MULTICAST_FILTER) - net_if_mcast_mon_register(&mcast_monitor, iface, net_if_stm32_mcast_cb); -#endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */ - /* Register Ethernet MAC Address with the upper layer */ net_if_set_link_addr(iface, dev_data->mac_addr, sizeof(dev_data->mac_addr), @@ -1575,6 +1430,9 @@ static enum ethernet_hw_caps eth_stm32_hal_get_capabilities(const struct device #endif #if defined(CONFIG_NET_DSA) | ETHERNET_DSA_MASTER_PORT +#endif +#if defined(CONFIG_ETH_STM32_MULTICAST_FILTER) + | ETHERNET_HW_FILTERING #endif ; } @@ -1622,6 +1480,11 @@ static int eth_stm32_hal_set_config(const struct device *dev, ret = 0; #endif /* CONFIG_NET_PROMISCUOUS_MODE */ break; +#if defined(CONFIG_ETH_STM32_MULTICAST_FILTER) + case ETHERNET_CONFIG_TYPE_FILTER: + eth_stm32_mcast_filter(dev, &config->filter); + break; +#endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */ default: break; } diff --git a/drivers/ethernet/eth_stm32_hal_priv.h b/drivers/ethernet/eth_stm32_hal_priv.h index 99644585dff..55ae396c90d 100644 --- a/drivers/ethernet/eth_stm32_hal_priv.h +++ b/drivers/ethernet/eth_stm32_hal_priv.h @@ -49,6 +49,9 @@ struct eth_stm32_hal_dev_data { CONFIG_ETH_STM32_HAL_RX_THREAD_STACK_SIZE); struct k_thread rx_thread; bool link_up; +#if defined(CONFIG_ETH_STM32_MULTICAST_FILTER) + uint8_t hash_index_cnt[64]; +#endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */ #if defined(CONFIG_PTP_CLOCK_STM32_HAL) const struct device *ptp_clock; float clk_ratio; From 76cd676050e6f31508cd8b65591bf903b300594b Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Fri, 1 Mar 2024 15:56:19 +0100 Subject: [PATCH 0861/2402] drivers: ethernet: eth_nxp_s32: Implement HW MAC address filtering Replace the multicast monitor with a HW MAC filter configuration. Signed-off-by: Pieter De Gendt --- drivers/ethernet/eth_nxp_s32_netc.c | 22 ++++++++-------------- drivers/ethernet/eth_nxp_s32_netc_priv.h | 2 +- drivers/ethernet/eth_nxp_s32_netc_psi.c | 5 ----- drivers/ethernet/eth_nxp_s32_netc_vsi.c | 5 ----- 4 files changed, 9 insertions(+), 25 deletions(-) diff --git a/drivers/ethernet/eth_nxp_s32_netc.c b/drivers/ethernet/eth_nxp_s32_netc.c index d7679564bce..81090646c60 100644 --- a/drivers/ethernet/eth_nxp_s32_netc.c +++ b/drivers/ethernet/eth_nxp_s32_netc.c @@ -116,32 +116,22 @@ int nxp_s32_eth_initialize_common(const struct device *dev) return 0; } -#if defined(CONFIG_NET_IPV6) -void nxp_s32_eth_mcast_cb(struct net_if *iface, const struct net_addr *addr, bool is_joined) +void nxp_s32_eth_mcast_filter(const struct device *dev, const struct ethernet_filter *filter) { - const struct device *dev = net_if_get_device(iface); const struct nxp_s32_eth_config *cfg = dev->config; - struct net_eth_addr mac_addr; Netc_Eth_Ip_StatusType status; - if (addr->family != AF_INET6) { - return; - } - - net_eth_ipv6_mcast_to_mac_addr(&addr->in6_addr, &mac_addr); - - if (is_joined) { + if (filter->set) { status = Netc_Eth_Ip_AddMulticastDstAddrToHashFilter(cfg->si_idx, - mac_addr.addr); + filter->mac_address.addr); } else { status = Netc_Eth_Ip_RemoveMulticastDstAddrFromHashFilter(cfg->si_idx, - mac_addr.addr); + filter->mac_address.addr); } if (status != NETC_ETH_IP_STATUS_SUCCESS) { LOG_ERR("Failed to update multicast hash table: %d", status); } } -#endif /* CONFIG_NET_IPV6 */ int nxp_s32_eth_tx(const struct device *dev, struct net_pkt *pkt) { @@ -317,6 +307,7 @@ enum ethernet_hw_caps nxp_s32_eth_get_capabilities(const struct device *dev) | ETHERNET_LINK_100BASE_T | ETHERNET_LINK_1000BASE_T | ETHERNET_HW_RX_CHKSUM_OFFLOAD + | ETHERNET_HW_FILTERING #if defined(CONFIG_NET_VLAN) | ETHERNET_HW_VLAN #endif @@ -344,6 +335,9 @@ int nxp_s32_eth_set_config(const struct device *dev, enum ethernet_config_type t ctx->mac_addr[0], ctx->mac_addr[1], ctx->mac_addr[2], ctx->mac_addr[3], ctx->mac_addr[4], ctx->mac_addr[5]); break; + case ETHERNET_CONFIG_TYPE_FILTER: + nxp_s32_eth_mcast_filter(dev, &config->filter); + break; default: res = -ENOTSUP; break; diff --git a/drivers/ethernet/eth_nxp_s32_netc_priv.h b/drivers/ethernet/eth_nxp_s32_netc_priv.h index b429233b694..e259b67ca96 100644 --- a/drivers/ethernet/eth_nxp_s32_netc_priv.h +++ b/drivers/ethernet/eth_nxp_s32_netc_priv.h @@ -131,7 +131,7 @@ struct nxp_s32_eth_data { int nxp_s32_eth_initialize_common(const struct device *dev); int nxp_s32_eth_tx(const struct device *dev, struct net_pkt *pkt); enum ethernet_hw_caps nxp_s32_eth_get_capabilities(const struct device *dev); -void nxp_s32_eth_mcast_cb(struct net_if *iface, const struct net_addr *addr, bool is_joined); +void nxp_s32_eth_mcast_filter(const struct device *dev, const struct ethernet_filter *filter); int nxp_s32_eth_set_config(const struct device *dev, enum ethernet_config_type type, const struct ethernet_config *config); extern void Netc_Eth_Ip_MSIX_Rx(uint8_t si_idx); diff --git a/drivers/ethernet/eth_nxp_s32_netc_psi.c b/drivers/ethernet/eth_nxp_s32_netc_psi.c index 465349703ab..c4219a7d763 100644 --- a/drivers/ethernet/eth_nxp_s32_netc_psi.c +++ b/drivers/ethernet/eth_nxp_s32_netc_psi.c @@ -156,11 +156,6 @@ static void nxp_s32_eth_iface_init(struct net_if *iface) struct nxp_s32_eth_data *ctx = dev->data; const struct nxp_s32_eth_config *cfg = dev->config; const struct nxp_s32_eth_msix *msix; -#if defined(CONFIG_NET_IPV6) - static struct net_if_mcast_monitor mon; - - net_if_mcast_mon_register(&mon, iface, nxp_s32_eth_mcast_cb); -#endif /* CONFIG_NET_IPV6 */ /* * For VLAN, this value is only used to get the correct L2 driver. diff --git a/drivers/ethernet/eth_nxp_s32_netc_vsi.c b/drivers/ethernet/eth_nxp_s32_netc_vsi.c index d4fb06c96da..f015934b524 100644 --- a/drivers/ethernet/eth_nxp_s32_netc_vsi.c +++ b/drivers/ethernet/eth_nxp_s32_netc_vsi.c @@ -37,11 +37,6 @@ static void nxp_s32_eth_iface_init(struct net_if *iface) struct nxp_s32_eth_data *ctx = dev->data; const struct nxp_s32_eth_config *cfg = dev->config; const struct nxp_s32_eth_msix *msix; -#if defined(CONFIG_NET_IPV6) - static struct net_if_mcast_monitor mon; - - net_if_mcast_mon_register(&mon, iface, nxp_s32_eth_mcast_cb); -#endif /* CONFIG_NET_IPV6 */ /* * For VLAN, this value is only used to get the correct L2 driver. From 669edc0d5e250d0f9e3fe151380c8b913de62ed8 Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Fri, 2 Feb 2024 17:45:25 +0900 Subject: [PATCH 0862/2402] posix: Implement set and get scope APIs for pthread attr Implement `pthread_attr_setscope()` and `pthread_attr_getscope()` are required as part of _POSIX_THREAD_PRIORITY_SCHEDULING Option Group. signed-off-by: Gaetan Perrot --- include/zephyr/posix/pthread.h | 8 ++++++ lib/posix/options/posix_internal.h | 1 + lib/posix/options/pthread.c | 44 ++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+) diff --git a/include/zephyr/posix/pthread.h b/include/zephyr/posix/pthread.h index 023473cdb13..7ffdb1318d8 100644 --- a/include/zephyr/posix/pthread.h +++ b/include/zephyr/posix/pthread.h @@ -39,6 +39,12 @@ extern "C" { #define PTHREAD_CANCEL_DEFERRED 0 #define PTHREAD_CANCEL_ASYNCHRONOUS 1 +/* Pthread scope */ +#undef PTHREAD_SCOPE_PROCESS +#define PTHREAD_SCOPE_PROCESS 1 +#undef PTHREAD_SCOPE_SYSTEM +#define PTHREAD_SCOPE_SYSTEM 0 + /* Passed to pthread_once */ #define PTHREAD_ONCE_INIT {0} @@ -419,6 +425,8 @@ int pthread_attr_getstack(const pthread_attr_t *attr, void **stackaddr, size_t *stacksize); int pthread_attr_setstack(pthread_attr_t *attr, void *stackaddr, size_t stacksize); +int pthread_attr_getscope(const pthread_attr_t *attr, int *contentionscope); +int pthread_attr_setscope(pthread_attr_t *attr, int contentionscope); #ifdef CONFIG_PTHREAD_IPC int pthread_once(pthread_once_t *once, void (*initFunc)(void)); #endif diff --git a/lib/posix/options/posix_internal.h b/lib/posix/options/posix_internal.h index 17d8c29d438..a723da17f92 100644 --- a/lib/posix/options/posix_internal.h +++ b/lib/posix/options/posix_internal.h @@ -29,6 +29,7 @@ struct posix_thread_attr { uint16_t guardsize : CONFIG_POSIX_PTHREAD_ATTR_GUARDSIZE_BITS; int8_t priority; uint8_t schedpolicy: 2; + bool contentionscope: 1; union { bool caller_destroys: 1; bool initialized: 1; diff --git a/lib/posix/options/pthread.c b/lib/posix/options/pthread.c index da771fef9b5..086d6a940ad 100644 --- a/lib/posix/options/pthread.c +++ b/lib/posix/options/pthread.c @@ -384,6 +384,49 @@ int pthread_attr_setstack(pthread_attr_t *_attr, void *stackaddr, size_t stacksi return 0; } +/** + * @brief Get scope attributes in thread attributes object. + * + * See IEEE 1003.1 + */ +int pthread_attr_getscope(const pthread_attr_t *_attr, int *contentionscope) +{ + struct posix_thread_attr *attr = (struct posix_thread_attr *)_attr; + + if (!__attr_is_initialized(attr) || contentionscope == NULL) { + return EINVAL; + } + *contentionscope = attr->contentionscope; + return 0; +} + +/** + * @brief Set scope attributes in thread attributes object. + * + * See IEEE 1003.1 + */ +int pthread_attr_setscope(pthread_attr_t *_attr, int contentionscope) +{ + struct posix_thread_attr *attr = (struct posix_thread_attr *)_attr; + + if (!__attr_is_initialized(attr)) { + LOG_DBG("attr %p is not initialized", attr); + return EINVAL; + } + if (!(contentionscope == PTHREAD_SCOPE_PROCESS || + contentionscope == PTHREAD_SCOPE_SYSTEM)) { + LOG_DBG("%s contentionscope %d", "Invalid", contentionscope); + return EINVAL; + } + if (contentionscope == PTHREAD_SCOPE_PROCESS) { + /* Zephyr does not yet support processes or process scheduling */ + LOG_DBG("%s contentionscope %d", "Unsupported", contentionscope); + return ENOTSUP; + } + attr->contentionscope = contentionscope; + return 0; +} + static void posix_thread_recycle_work_handler(struct k_work *work) { ARG_UNUSED(work); @@ -797,6 +840,7 @@ int pthread_attr_init(pthread_attr_t *_attr) *attr = (struct posix_thread_attr){0}; attr->guardsize = CONFIG_POSIX_PTHREAD_ATTR_GUARDSIZE_DEFAULT; + attr->contentionscope = PTHREAD_SCOPE_SYSTEM; if (DYNAMIC_STACK_SIZE > 0) { attr->stack = k_thread_stack_alloc(DYNAMIC_STACK_SIZE + attr->guardsize, From 990ebd5c94e9cf6d87e2adce06af9d3af5b6d55b Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Fri, 2 Feb 2024 17:45:46 +0900 Subject: [PATCH 0863/2402] doc: posix: mark set and get scope APIs for pthread attr as supported `pthread_attr_setscope()` and `pthread_attr_getscope()` are now implemented, mark it so. signed-off-by: Gaetan Perrot --- doc/services/portability/posix/option_groups/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst index 0fe00546d6c..0f5888b0f51 100644 --- a/doc/services/portability/posix/option_groups/index.rst +++ b/doc/services/portability/posix/option_groups/index.rst @@ -440,10 +440,10 @@ _POSIX_THREAD_PRIORITY_SCHEDULING pthread_attr_getinheritsched(), pthread_attr_getschedpolicy(),yes - pthread_attr_getscope(), + pthread_attr_getscope(),yes pthread_attr_setinheritsched(), pthread_attr_setschedpolicy(),yes - pthread_attr_setscope(), + pthread_attr_setscope(),yes pthread_getschedparam(),yes pthread_setschedparam(),yes pthread_setschedprio(),yes From 99f62a749cbbb0da676b6320c2c9492e3914b2d1 Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Sun, 4 Feb 2024 23:28:26 +0900 Subject: [PATCH 0864/2402] posix: Implement tests for set and get scope APIs for pthread attr Add tests for `pthread_attr_setscope()` and `pthread_attr_getscope()` signed-off-by: Gaetan Perrot --- tests/posix/common/src/pthread_attr.c | 42 +++++++++++++++++++++++++++ tests/posix/headers/src/pthread_h.c | 8 ++--- 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/tests/posix/common/src/pthread_attr.c b/tests/posix/common/src/pthread_attr.c index 99568a85298..d6ff3a5ee8d 100644 --- a/tests/posix/common/src/pthread_attr.c +++ b/tests/posix/common/src/pthread_attr.c @@ -439,6 +439,48 @@ ZTEST(pthread_attr, test_pthread_attr_setstacksize) } } +ZTEST(pthread_attr, test_pthread_attr_getscope) +{ + int contentionscope = BIOS_FOOD; + + /* degenerate cases */ + { + if (false) { + /* undefined behaviour */ + zassert_equal(pthread_attr_getscope(NULL, NULL), EINVAL); + zassert_equal(pthread_attr_getscope(NULL, &contentionscope), EINVAL); + zassert_equal(pthread_attr_getscope(&uninit_attr, &contentionscope), + EINVAL); + } + zassert_equal(pthread_attr_getscope(&attr, NULL), EINVAL); + } + + zassert_ok(pthread_attr_getscope(&attr, &contentionscope)); + zassert_equal(contentionscope, PTHREAD_SCOPE_SYSTEM); +} + +ZTEST(pthread_attr, test_pthread_attr_setscope) +{ + int contentionscope = BIOS_FOOD; + + /* degenerate cases */ + { + if (false) { + /* undefined behaviour */ + zassert_equal(pthread_attr_setscope(NULL, PTHREAD_SCOPE_SYSTEM), EINVAL); + zassert_equal(pthread_attr_setscope(NULL, contentionscope), EINVAL); + zassert_equal(pthread_attr_setscope((pthread_attr_t *)&uninit_attr, + contentionscope), EINVAL); + } + zassert_equal(pthread_attr_setscope(&attr, 3), EINVAL); + } + + zassert_equal(pthread_attr_setscope(&attr, PTHREAD_SCOPE_PROCESS), ENOTSUP); + zassert_ok(pthread_attr_setscope(&attr, PTHREAD_SCOPE_SYSTEM)); + zassert_ok(pthread_attr_getscope(&attr, &contentionscope)); + zassert_equal(contentionscope, PTHREAD_SCOPE_SYSTEM); +} + ZTEST(pthread_attr, test_pthread_attr_large_stacksize) { size_t actual_size; diff --git a/tests/posix/headers/src/pthread_h.c b/tests/posix/headers/src/pthread_h.c index 73467d14bf9..17b7768f879 100644 --- a/tests/posix/headers/src/pthread_h.c +++ b/tests/posix/headers/src/pthread_h.c @@ -53,8 +53,8 @@ ZTEST(posix_headers, test_pthread_h) zassert_not_equal(-1, PTHREAD_PROCESS_SHARED); zassert_not_equal(-1, PTHREAD_PROCESS_PRIVATE); - /* zassert_not_equal(-1, PTHREAD_SCOPE_PROCESS); */ /* not implemented */ - /* zassert_not_equal(-1, PTHREAD_SCOPE_SYSTEM); */ /* not implemented */ + zassert_not_equal(-1, PTHREAD_SCOPE_PROCESS); + zassert_not_equal(-1, PTHREAD_SCOPE_SYSTEM); pthread_cond_t cond = PTHREAD_COND_INITIALIZER; pthread_mutex_t mu = PTHREAD_MUTEX_INITIALIZER; @@ -68,7 +68,7 @@ ZTEST(posix_headers, test_pthread_h) /* zassert_not_null(pthread_attr_getinheritsched); */ /* not implemented */ zassert_not_null(pthread_attr_getschedparam); zassert_not_null(pthread_attr_getschedpolicy); - /* zassert_not_null(pthread_attr_getscope); */ /* not implemented */ + zassert_not_null(pthread_attr_getscope); zassert_not_null(pthread_attr_getstack); zassert_not_null(pthread_attr_getstacksize); zassert_not_null(pthread_attr_init); @@ -77,7 +77,7 @@ ZTEST(posix_headers, test_pthread_h) /* zassert_not_null(pthread_attr_setinheritsched); */ /* not implemented */ zassert_not_null(pthread_attr_setschedparam); zassert_not_null(pthread_attr_setschedpolicy); - /* zassert_not_null(pthread_attr_setscope); */ /* not implemented */ + zassert_not_null(pthread_attr_setscope); zassert_not_null(pthread_attr_setstack); zassert_not_null(pthread_attr_setstacksize); zassert_not_null(pthread_barrier_destroy); From 8ec839f76c8cce8becc3c71e7727123c4aa8c5e1 Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Mon, 18 Mar 2024 14:33:42 +0800 Subject: [PATCH 0865/2402] Bluetooth: Host: Change __line__ to __LINE__ The building error is reported in Ubuntu if CONFIG_NET_BUF_LOG is true. Change __line__ to __LINE__ to fix building error. Signed-off-by: Lyle Zhu --- subsys/bluetooth/host/conn_internal.h | 2 +- subsys/bluetooth/host/iso_internal.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/subsys/bluetooth/host/conn_internal.h b/subsys/bluetooth/host/conn_internal.h index 20a10ae5a1f..2f41e748068 100644 --- a/subsys/bluetooth/host/conn_internal.h +++ b/subsys/bluetooth/host/conn_internal.h @@ -397,7 +397,7 @@ struct net_buf *bt_conn_create_pdu_timeout_debug(struct net_buf_pool *pool, #define bt_conn_create_pdu(_pool, _reserve) \ bt_conn_create_pdu_timeout_debug(_pool, _reserve, K_FOREVER, \ - __func__, __line__) + __func__, __LINE__) #else struct net_buf *bt_conn_create_pdu_timeout(struct net_buf_pool *pool, size_t reserve, k_timeout_t timeout); diff --git a/subsys/bluetooth/host/iso_internal.h b/subsys/bluetooth/host/iso_internal.h index a48607c61c3..7a37413e7f3 100644 --- a/subsys/bluetooth/host/iso_internal.h +++ b/subsys/bluetooth/host/iso_internal.h @@ -117,7 +117,7 @@ struct net_buf *bt_iso_create_pdu_timeout_debug(struct net_buf_pool *pool, #define bt_iso_create_pdu(_pool, _reserve) \ bt_iso_create_pdu_timeout_debug(_pool, _reserve, K_FOREVER, \ - __func__, __line__) + __func__, __LINE__) #else struct net_buf *bt_iso_create_pdu_timeout(struct net_buf_pool *pool, size_t reserve, k_timeout_t timeout); From ba871733e00210b57e3eea714e845623da44bd8d Mon Sep 17 00:00:00 2001 From: Jonathon Penix Date: Fri, 26 Jan 2024 14:19:08 -0800 Subject: [PATCH 0866/2402] cmake: llvm: riscv: Set RISC-V flags when building with clang Ensure --target and -march/-mabi/-mcmodel are set appropriately when building with clang targeting RISC-V. Signed-off-by: Jonathon Penix --- cmake/compiler/clang/target.cmake | 2 ++ cmake/toolchain/llvm/target.cmake | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/cmake/compiler/clang/target.cmake b/cmake/compiler/clang/target.cmake index 8dd1460280b..d258cdadcf4 100644 --- a/cmake/compiler/clang/target.cmake +++ b/cmake/compiler/clang/target.cmake @@ -31,6 +31,8 @@ if(NOT "${ARCH}" STREQUAL "posix") ) include(${ZEPHYR_BASE}/cmake/compiler/clang/target_arm.cmake) + elseif("${ARCH}" STREQUAL "riscv") + include(${ZEPHYR_BASE}/cmake/compiler/gcc/target_riscv.cmake) endif() if(DEFINED CMAKE_C_COMPILER_TARGET) diff --git a/cmake/toolchain/llvm/target.cmake b/cmake/toolchain/llvm/target.cmake index 5c06af5f25f..a2240c02364 100644 --- a/cmake/toolchain/llvm/target.cmake +++ b/cmake/toolchain/llvm/target.cmake @@ -33,6 +33,12 @@ elseif("${ARCH}" STREQUAL "x86") else() set(triple i686-pc-none-elf) endif() +elseif("${ARCH}" STREQUAL "riscv") + if(CONFIG_64BIT) + set(triple riscv64-unknown-elf) + else() + set(triple riscv32-unknown-elf) + endif() endif() if(DEFINED triple) From 82a47cc06d25af774b15aa1d0037afde8ca3d7cb Mon Sep 17 00:00:00 2001 From: Jonathon Penix Date: Fri, 26 Jan 2024 15:16:34 -0800 Subject: [PATCH 0867/2402] kconfig: llvm: riscv: Advertise TLS support when using llvm for RISC-V clang and lld support TLS for RISC-V, so advertise this support in Kconfig. I believe other non-RISC-V targets also have TLS support in LLVM, but I'm not sure on the exact subset. As TLS support in LLVM wasn't automatically advertised previously, gate this on RISC-V for now as it a) shouldn't break other targets and b) prevents us from improperly claiming support for unsupported targets. Signed-off-by: Jonathon Penix --- cmake/toolchain/llvm/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cmake/toolchain/llvm/Kconfig b/cmake/toolchain/llvm/Kconfig index b16d0273939..0e2e3e85863 100644 --- a/cmake/toolchain/llvm/Kconfig +++ b/cmake/toolchain/llvm/Kconfig @@ -17,3 +17,8 @@ config LLVM_USE_LLD Use LLVM built-in lld linker with llvm/clang. endchoice + +config TOOLCHAIN_LLVM_SUPPORTS_THREAD_LOCAL_STORAGE + depends on RISCV + def_bool y + select TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE From 6622f0b3aa919b0b4a066c88cba7441ec34fbf81 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 15 Mar 2024 13:17:01 +0100 Subject: [PATCH 0868/2402] Bluetooth: Controller: Correct PPI->Timer start delay for simulation In the simulated bsim boards there is no jittery delay from a (D)PPI event until a TIMER starts. The timer starts instantaneously so we do not need to compensate for it. Signed-off-by: Alberto Escolar Piedras --- .../controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h index dce326d469a..b9401a54292 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h @@ -86,4 +86,8 @@ #endif /* This is delay between PPI task START and timer actual start counting. */ +#if !defined(CONFIG_SOC_SERIES_BSIM_NRFXX) #define HAL_RADIO_TMR_START_DELAY_US 1U +#else /* For simulated targets there is no delay for the PPI task -> TIMER start */ +#define HAL_RADIO_TMR_START_DELAY_US 0U +#endif From 1861583ce29701fc6afa23233b9f0a75f7e60257 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Thu, 14 Mar 2024 13:55:18 +0100 Subject: [PATCH 0869/2402] Bluetooth: Mesh: Warn if can't listen to unprov beacons until proved When calling `mesh prov beacon-listen on` shell command before provisioning the local device, the stack won't report unprovisioned beacons. This is because the scanner has not been started yet. This behavior confuses users. Print a warning that the device needs to be provisioned first before it can listen to unprovisioned beacons. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/shell/shell.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/subsys/bluetooth/mesh/shell/shell.c b/subsys/bluetooth/mesh/shell/shell.c index 53672bea4ba..78c503c29ac 100644 --- a/subsys/bluetooth/mesh/shell/shell.c +++ b/subsys/bluetooth/mesh/shell/shell.c @@ -726,6 +726,11 @@ static int cmd_beacon_listen(const struct shell *sh, size_t argc, return err; } + if (!bt_mesh_is_provisioned()) { + shell_error(sh, "Not yet provisioned"); + return -EINVAL; + } + if (val) { bt_mesh_shell_prov.unprovisioned_beacon = print_unprovisioned_beacon; #if defined(CONFIG_BT_MESH_PB_GATT_CLIENT) From 9f71b8023bc1917174099cd2f1422bcf0ba8d333 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Thu, 14 Mar 2024 10:37:01 +0000 Subject: [PATCH 0870/2402] sysbuild: Add support for COMPILER_WARNINGS_AS_ERRORS Adds support for the Kconfig option to enable compiler warnings being treated as errors in all images that are build. This is a sticky-set option which means enabling it in sysbuild will enable it in all images, if it is then disabled in sysbuild it will not be disabled in any of the images as a result and would need to be manually unselected. Signed-off-by: Jamie McCrae --- share/sysbuild/Kconfig | 6 ++++++ share/sysbuild/build/Kconfig | 8 ++++++++ share/sysbuild/cmake/modules/sysbuild_extensions.cmake | 7 +++++-- .../image_configurations/ALL_image_default.cmake | 10 ++++++++++ 4 files changed, 29 insertions(+), 2 deletions(-) create mode 100644 share/sysbuild/build/Kconfig create mode 100644 share/sysbuild/image_configurations/ALL_image_default.cmake diff --git a/share/sysbuild/Kconfig b/share/sysbuild/Kconfig index 9f1a1cf30af..d8a0cf25b8e 100644 --- a/share/sysbuild/Kconfig +++ b/share/sysbuild/Kconfig @@ -42,3 +42,9 @@ config WARN_DEPRECATED features are enabled. rsource "images/Kconfig" + +menu "Build options" + +rsource "build/Kconfig" + +endmenu diff --git a/share/sysbuild/build/Kconfig b/share/sysbuild/build/Kconfig new file mode 100644 index 00000000000..dfa423cd3e8 --- /dev/null +++ b/share/sysbuild/build/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +config COMPILER_WARNINGS_AS_ERRORS + bool "Treat warnings as errors" + help + Turn on "warning as error" toolchain flags for all images if set. diff --git a/share/sysbuild/cmake/modules/sysbuild_extensions.cmake b/share/sysbuild/cmake/modules/sysbuild_extensions.cmake index 05cde48a0e0..40f73d26da2 100644 --- a/share/sysbuild/cmake/modules/sysbuild_extensions.cmake +++ b/share/sysbuild/cmake/modules/sysbuild_extensions.cmake @@ -372,11 +372,14 @@ function(ExternalZephyrProject_Add) set_target_properties(${ZBUILD_APPLICATION} PROPERTIES MAIN_APP True) endif() + set(image_default "${CMAKE_SOURCE_DIR}/image_configurations/ALL_image_default.cmake") + if(DEFINED ZBUILD_APP_TYPE) - set(image_default "${CMAKE_SOURCE_DIR}/image_configurations/${ZBUILD_APP_TYPE}_image_default.cmake") - set_target_properties(${ZBUILD_APPLICATION} PROPERTIES IMAGE_CONF_SCRIPT ${image_default}) + list(APPEND image_default "${CMAKE_SOURCE_DIR}/image_configurations/${ZBUILD_APP_TYPE}_image_default.cmake") endif() + set_target_properties(${ZBUILD_APPLICATION} PROPERTIES IMAGE_CONF_SCRIPT "${image_default}") + if(DEFINED ZBUILD_BOARD) # Only set image specific board if provided. # The sysbuild BOARD is exported through sysbuild cache, and will be used diff --git a/share/sysbuild/image_configurations/ALL_image_default.cmake b/share/sysbuild/image_configurations/ALL_image_default.cmake new file mode 100644 index 00000000000..d270704ad59 --- /dev/null +++ b/share/sysbuild/image_configurations/ALL_image_default.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +# This sysbuild CMake file sets the sysbuild controlled settings as properties +# on all images. + +if(SB_CONFIG_COMPILER_WARNINGS_AS_ERRORS) + set_config_bool(${ZCMAKE_APPLICATION} CONFIG_COMPILER_WARNINGS_AS_ERRORS y) +endif() From 5af2140927d520a62424c81c1cab23a5f7a11823 Mon Sep 17 00:00:00 2001 From: Maciej Perkowski Date: Thu, 14 Mar 2024 12:48:54 +0100 Subject: [PATCH 0871/2402] twister: Use proper warnings-to-errors command for sysbuild If sysbuild is used a flag SB_CONFIG_COMPILER_WARNINGS_AS_ERRORS has to be used in order to turn warings to errors on all images. Align pytest tests with the change. Fixes: #67360 Signed-off-by: Maciej Perkowski --- scripts/pylib/twister/twisterlib/runner.py | 6 +++++- scripts/tests/twister/test_runner.py | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/runner.py b/scripts/pylib/twister/twisterlib/runner.py index be3d64adc08..28e3dae80cd 100644 --- a/scripts/pylib/twister/twisterlib/runner.py +++ b/scripts/pylib/twister/twisterlib/runner.py @@ -329,11 +329,15 @@ def run_cmake(self, args="", filter_stages=[]): warnings_as_errors = 'n' gen_defines_args = "" + warning_command = 'CONFIG_COMPILER_WARNINGS_AS_ERRORS' + if self.testsuite.sysbuild: + warning_command = 'SB_' + warning_command + logger.debug("Running cmake on %s for %s" % (self.source_dir, self.platform.name)) cmake_args = [ f'-B{self.build_dir}', f'-DTC_RUNID={self.instance.run_id}', - f'-DCONFIG_COMPILER_WARNINGS_AS_ERRORS={warnings_as_errors}', + f'-D{warning_command}={warnings_as_errors}', f'-DEXTRA_GEN_DEFINES_ARGS={gen_defines_args}', f'-G{self.env.generator}' ] diff --git a/scripts/tests/twister/test_runner.py b/scripts/tests/twister/test_runner.py index 7a492e94918..b07ab333f89 100644 --- a/scripts/tests/twister/test_runner.py +++ b/scripts/tests/twister/test_runner.py @@ -368,7 +368,7 @@ def mock_popen(*args, **kwargs): None, None, [os.path.join('dummy', 'cmake'), '-B' + os.path.join('build', 'dir'), '-DTC_RUNID=1', - '-DCONFIG_COMPILER_WARNINGS_AS_ERRORS=y', + '-DSB_CONFIG_COMPILER_WARNINGS_AS_ERRORS=y', '-DEXTRA_GEN_DEFINES_ARGS=--edtlib-Werror', '-Gdummy_generator', '-S' + os.path.join('source', 'dir'), 'arg1', 'arg2', @@ -382,7 +382,7 @@ def mock_popen(*args, **kwargs): 'error', 'Cmake build failure', [os.path.join('dummy', 'cmake'), '-B' + os.path.join('build', 'dir'), '-DTC_RUNID=1', - '-DCONFIG_COMPILER_WARNINGS_AS_ERRORS=n', + '-DSB_CONFIG_COMPILER_WARNINGS_AS_ERRORS=n', '-DEXTRA_GEN_DEFINES_ARGS=', '-Gdummy_generator', '-Szephyr_base/share/sysbuild', '-DAPP_DIR=' + os.path.join('source', 'dir'), From 369e40b27bca1f08fefe23924f7dc82dd096c53f Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Fri, 15 Mar 2024 08:29:53 +0000 Subject: [PATCH 0872/2402] samples: ipc: rpmsg_service: Add sample file, remove broken builds Adds a sample file so that this sample is built in CI and removes all configurations that do not build Signed-off-by: Jamie McCrae --- .../subsys/ipc/rpmsg_service/Kconfig.sysbuild | 10 ++-------- .../boards/bl5340_dvk_nrf5340_cpuapp.conf | 1 - .../boards/esp32_devkitc_wrover.conf | 1 - .../boards/esp32_devkitc_wrover.overlay | 19 ------------------- .../rpmsg_service/boards/esp32s3_devkitm.conf | 1 - .../boards/esp32s3_devkitm.overlay | 19 ------------------- .../boards/nrf5340dk_nrf5340_cpuapp.conf | 1 - .../esp32_devkitc_wrover_appcpu.overlay | 19 ------------------- samples/subsys/ipc/rpmsg_service/sample.yaml | 13 +++++++++++++ 9 files changed, 15 insertions(+), 69 deletions(-) delete mode 100644 samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_nrf5340_cpuapp.conf delete mode 100644 samples/subsys/ipc/rpmsg_service/boards/esp32_devkitc_wrover.conf delete mode 100644 samples/subsys/ipc/rpmsg_service/boards/esp32_devkitc_wrover.overlay delete mode 100644 samples/subsys/ipc/rpmsg_service/boards/esp32s3_devkitm.conf delete mode 100644 samples/subsys/ipc/rpmsg_service/boards/esp32s3_devkitm.overlay delete mode 100644 samples/subsys/ipc/rpmsg_service/boards/nrf5340dk_nrf5340_cpuapp.conf delete mode 100644 samples/subsys/ipc/rpmsg_service/remote/boards/esp32_devkitc_wrover_appcpu.overlay create mode 100644 samples/subsys/ipc/rpmsg_service/sample.yaml diff --git a/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild b/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild index 9af87af157f..b75f2d4b6f6 100644 --- a/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild +++ b/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild @@ -6,11 +6,5 @@ source "share/sysbuild/Kconfig" config RPMSG_REMOTE_BOARD string - default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" - default "bl5340_dvk/nrf5340/cpunet" if $(BOARD) = "bl5340_dvk" - default "lpcxpresso54114/lpc54114/m0" if $(BOARD) = "lpcxpresso54114" - default "mps2_an521_remote" if $(BOARD) = "mps2_an521" - default "v2m_musca_b1_ns" if $(BOARD) = "v2m_musca_b1" - default "esp32_devkitc_wroom_appcpu" if $(BOARD) = "esp32_devkitc_wroom" - default "esp32_devkitc_wrover_appcpu" if $(BOARD) = "esp32_devkitc_wrover" - default "esp32s3_devkitm_appcpu" if $(BOARD) = "esp32s3_devkitm" + default "mps2/an521/cpu1" if $(BOARD) = "mps2" + default "v2m_musca_b1/musca_b1/ns" if $(BOARD) = "v2m_musca_b1" diff --git a/samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_nrf5340_cpuapp.conf b/samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_nrf5340_cpuapp.conf deleted file mode 100644 index 0af6c0de769..00000000000 --- a/samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_nrf5340_cpuapp.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_BOARD_ENABLE_CPUNET=y diff --git a/samples/subsys/ipc/rpmsg_service/boards/esp32_devkitc_wrover.conf b/samples/subsys/ipc/rpmsg_service/boards/esp32_devkitc_wrover.conf deleted file mode 100644 index 0bef3d481fd..00000000000 --- a/samples/subsys/ipc/rpmsg_service/boards/esp32_devkitc_wrover.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SOC_ESP32_PROCPU=y diff --git a/samples/subsys/ipc/rpmsg_service/boards/esp32_devkitc_wrover.overlay b/samples/subsys/ipc/rpmsg_service/boards/esp32_devkitc_wrover.overlay deleted file mode 100644 index ad437c16e49..00000000000 --- a/samples/subsys/ipc/rpmsg_service/boards/esp32_devkitc_wrover.overlay +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2023 Felipe Neves - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - /* - * shared memory reserved for the inter-processor communication - */ - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - }; -}; - -&ipm0 { - status = "okay"; -}; diff --git a/samples/subsys/ipc/rpmsg_service/boards/esp32s3_devkitm.conf b/samples/subsys/ipc/rpmsg_service/boards/esp32s3_devkitm.conf deleted file mode 100644 index a8ee714a955..00000000000 --- a/samples/subsys/ipc/rpmsg_service/boards/esp32s3_devkitm.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SOC_ESP32S3_PROCPU=y diff --git a/samples/subsys/ipc/rpmsg_service/boards/esp32s3_devkitm.overlay b/samples/subsys/ipc/rpmsg_service/boards/esp32s3_devkitm.overlay deleted file mode 100644 index ad437c16e49..00000000000 --- a/samples/subsys/ipc/rpmsg_service/boards/esp32s3_devkitm.overlay +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2023 Felipe Neves - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - /* - * shared memory reserved for the inter-processor communication - */ - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - }; -}; - -&ipm0 { - status = "okay"; -}; diff --git a/samples/subsys/ipc/rpmsg_service/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/subsys/ipc/rpmsg_service/boards/nrf5340dk_nrf5340_cpuapp.conf deleted file mode 100644 index 0af6c0de769..00000000000 --- a/samples/subsys/ipc/rpmsg_service/boards/nrf5340dk_nrf5340_cpuapp.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_BOARD_ENABLE_CPUNET=y diff --git a/samples/subsys/ipc/rpmsg_service/remote/boards/esp32_devkitc_wrover_appcpu.overlay b/samples/subsys/ipc/rpmsg_service/remote/boards/esp32_devkitc_wrover_appcpu.overlay deleted file mode 100644 index 6da59669fc5..00000000000 --- a/samples/subsys/ipc/rpmsg_service/remote/boards/esp32_devkitc_wrover_appcpu.overlay +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2023 Felipe Neves - * - * SPDX-License-Identifier: Apache-2.0 - */ - - / { - chosen { - /* - * shared memory reserved for the inter-processor communication - */ - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - }; -}; - -&ipm0 { - status = "okay"; -}; diff --git a/samples/subsys/ipc/rpmsg_service/sample.yaml b/samples/subsys/ipc/rpmsg_service/sample.yaml new file mode 100644 index 00000000000..af23b5b0449 --- /dev/null +++ b/samples/subsys/ipc/rpmsg_service/sample.yaml @@ -0,0 +1,13 @@ +sample: + name: IPC Service example integration (rpmsg backend) +tests: + sample.ipc.rpmsg_service: + platform_allow: + - mps2/an521/cpu0 + - v2m_musca_b1/musca_b1 + integration_platforms: + - mps2/an521/cpu0 + - v2m_musca_b1/musca_b1 + tags: ipc + sysbuild: true + harness: remote From 1a55caf8263e11bc22f93b88e2ccf99eb30f690f Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 18 Mar 2024 06:58:32 -0400 Subject: [PATCH 0873/2402] soc: esp32: make SCHED_CPU_MASK depend on SCHED_DUMB Forcing SCHED_CPU_MASK without SCHED_DUMB results in a global warning from Kconfig. Signed-off-by: Anas Nashif --- soc/espressif/esp32/Kconfig.defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/espressif/esp32/Kconfig.defconfig b/soc/espressif/esp32/Kconfig.defconfig index 7d793d2ecaa..17bda587b97 100644 --- a/soc/espressif/esp32/Kconfig.defconfig +++ b/soc/espressif/esp32/Kconfig.defconfig @@ -27,7 +27,7 @@ config SCHED_IPI_SUPPORTED default y config SCHED_CPU_MASK - default y + default y if SCHED_DUMB config MP_MAX_NUM_CPUS default 2 From 25877f01b5150e8522962963d4b76c457386d64e Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 12 Mar 2024 12:28:35 -0400 Subject: [PATCH 0874/2402] doc: fix typo Bluetooth -> Bluetoth Fixes #67435 Signed-off-by: Anas Nashif --- boards/raspberrypi/rpi_pico/doc/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/raspberrypi/rpi_pico/doc/index.rst b/boards/raspberrypi/rpi_pico/doc/index.rst index f535d85506a..8db18d96f04 100644 --- a/boards/raspberrypi/rpi_pico/doc/index.rst +++ b/boards/raspberrypi/rpi_pico/doc/index.rst @@ -9,7 +9,7 @@ Overview The Raspberry Pi Pico and Pico W are small, low-cost, versatile boards from Raspberry Pi. They are equipped with an RP2040 SoC, an on-board LED, a USB connector, and an SWD interface. The Pico W additionally contains an -Infineon CYW43439 2.4 GHz Wi-Fi/Bluetoth module. The USB bootloader allows the +Infineon CYW43439 2.4 GHz Wi-Fi/Bluetooth module. The USB bootloader allows the ability to flash without any adapter, in a drag-and-drop manner. It is also possible to flash and debug the boards with their SWD interface, using an external adapter. From 3bc1524f5db698164ac655bd4f9cd102c2308f5c Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 16:52:31 -0500 Subject: [PATCH 0875/2402] dts: arm: nxp: rw6xx: add dma0 definition Add DMA0 definition for RW61x SOC Signed-off-by: Daniel DeGrasse --- dts/arm/nxp/nxp_rw6xx_common.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index e2ab6c8f05b..923ad2bf47a 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -145,6 +145,15 @@ num-lines = <8>; num-inputs = <64>; }; + + dma0: dma-controller@104000 { + compatible = "nxp,lpc-dma"; + reg = <0x104000 0x1000>; + interrupts = <1 0>; + status = "disabled"; + #dma-cells = <1>; + dma-channels = <33>; + }; }; &flexspi { From f378fd02821e1dea1cc5a4c743caafbc3953d211 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Thu, 22 Feb 2024 18:30:56 -0600 Subject: [PATCH 0876/2402] drivers: dma: dma_mcux_lpc: add workaround for RW61x flexspi RW61x DMA has the *unique* restriction that DMA access is not routed through the FlexSPI cache engine, only via the non-cached address space. To enable DMA to read from the FlexSPI AHB space directly, fixup any address passed to the DMA engine that is in the FlexSPI AHB cached region to be in the non cached region Signed-off-by: Daniel DeGrasse --- drivers/dma/dma_mcux_lpc.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/dma/dma_mcux_lpc.c b/drivers/dma/dma_mcux_lpc.c index f8d9ab81e08..449ca0de97f 100644 --- a/drivers/dma/dma_mcux_lpc.c +++ b/drivers/dma/dma_mcux_lpc.c @@ -114,6 +114,28 @@ static void dma_mcux_lpc_irq_handler(const struct device *dev) #endif } +#ifdef CONFIG_SOC_SERIES_RW6XX +static inline void rw6xx_dma_addr_fixup(struct dma_block_config *block) +{ + /* RW6xx AHB design does not route DMA engine through FlexSPI CACHE. + * Therefore, to use DMA from the FlexSPI space we must adjust the + * source address to use the non cached FlexSPI region. + * FlexSPI cached region is at 0x800_0000 (nonsecure) or 0x1800_0000 + * (secure). We move the address into non cached region, which is at + * 0x4800_0000 or 0x5800_000. + */ + if (((block->source_address & 0xF8000000) == 0x18000000) || + ((block->source_address & 0xF8000000) == 0x8000000)) { + block->source_address = block->source_address + 0x40000000; + } + if (((block->dest_address & 0xF8000000) == 0x18000000) || + ((block->dest_address & 0xF8000000) == 0x8000000)) { + block->dest_address = block->dest_address + 0x40000000; + } + +} +#endif + static int dma_mcux_lpc_queue_descriptors(struct channel_data *data, struct dma_block_config *block, uint8_t src_inc, @@ -228,6 +250,9 @@ static int dma_mcux_lpc_queue_descriptors(struct channel_data *data, dest_inc, MIN(local_block.block_size, max_xfer_bytes)); +#ifdef CONFIG_SOC_SERIES_RW6XX + rw6xx_dma_addr_fixup(&local_block); +#endif DMA_SetupDescriptor(data->curr_descriptor, xfer_config, (void *)local_block.source_address, @@ -271,6 +296,9 @@ static int dma_mcux_lpc_queue_descriptors(struct channel_data *data, MIN(local_block.block_size, max_xfer_bytes)); /* Mark this as invalid */ xfer_config &= ~DMA_CHANNEL_XFERCFG_CFGVALID_MASK; +#ifdef CONFIG_SOC_SERIES_RW6XX + rw6xx_dma_addr_fixup(&local_block); +#endif DMA_SetupDescriptor(data->curr_descriptor, xfer_config, (void *)local_block.source_address, @@ -586,6 +614,10 @@ static int dma_mcux_lpc_configure(const struct device *dev, uint32_t channel, assert(block_config->source_address == ROUND_UP(block_config->source_address, width)); assert(block_config->dest_address == ROUND_UP(block_config->dest_address, width)); +#ifdef CONFIG_SOC_SERIES_RW6XX + rw6xx_dma_addr_fixup(block_config); +#endif + DMA_SubmitChannelTransferParameter(p_handle, xfer_config, (void *)block_config->source_address, From d921659d6a4ffa9d47896c23f9292c238c183d19 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 16:56:14 -0500 Subject: [PATCH 0877/2402] boards: nxp: rd_rw612_bga: enable DMA support Enable support for dma controller on RD RW612 BGA board, and add overlay to enable board in dma loop transfer test Signed-off-by: Daniel DeGrasse --- boards/nxp/rd_rw612_bga/doc/index.rst | 2 ++ boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 4 ++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml | 1 + .../drivers/dma/loop_transfer/boards/rd_rw612_bga.overlay | 7 +++++++ 4 files changed, 14 insertions(+) create mode 100644 tests/drivers/dma/loop_transfer/boards/rd_rw612_bga.overlay diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index 782fdd66175..1d7b795fc98 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -39,6 +39,8 @@ Supported Features +-----------+------------+-----------------------------------+ | USART | on-chip | serial | +-----------+------------+-----------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-----------------------------------+ | SPI | on-chip | spi | +-----------+------------+-----------------------------------+ diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index 49e86acb7d1..0e6e625ac57 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -100,3 +100,7 @@ arduino_spi: &flexcomm0 { }; }; }; + +&dma0 { + status = "okay"; +}; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml index ac37d0a026e..8d654c639a0 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -15,5 +15,6 @@ toolchain: ram: 960 flash: 65536 supported: + - dma - gpio - spi diff --git a/tests/drivers/dma/loop_transfer/boards/rd_rw612_bga.overlay b/tests/drivers/dma/loop_transfer/boards/rd_rw612_bga.overlay new file mode 100644 index 00000000000..eb0aab63133 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/rd_rw612_bga.overlay @@ -0,0 +1,7 @@ +/* + * Copyright 2023-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +tst_dma0: &dma0 { }; From 0e4b5de6ca5e09241526dbd3b1a238fc8df6ad23 Mon Sep 17 00:00:00 2001 From: Tom Chang Date: Tue, 5 Mar 2024 11:15:37 +0800 Subject: [PATCH 0878/2402] drivers: espi: npcx: workaround Global Reset issue Apply the workaround for the issue "eSPI global reset" in the NPCX49nF_Errata Signed-off-by: Tom Chang --- drivers/espi/Kconfig.npcx | 6 ++++++ drivers/espi/espi_npcx.c | 43 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/drivers/espi/Kconfig.npcx b/drivers/espi/Kconfig.npcx index 3f1d511caa1..d746d89f961 100644 --- a/drivers/espi/Kconfig.npcx +++ b/drivers/espi/Kconfig.npcx @@ -118,4 +118,10 @@ config ESPI_NPCX_SUPP_VW_GPIO help Selected if NPCX series supports virtual wire GPIOs in eSPI module. +config ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND + bool + default y if SOC_SERIES_NPCX4 && ESPI_FLASH_CHANNEL + help + Workaround the issue "Global Reset" in the npcx4 SoC errata. + endif #ESPI_NPCX diff --git a/drivers/espi/espi_npcx.c b/drivers/espi/espi_npcx.c index f2005d24dba..15cb5d489dc 100644 --- a/drivers/espi/espi_npcx.c +++ b/drivers/espi/espi_npcx.c @@ -46,6 +46,10 @@ struct espi_npcx_data { #if defined(CONFIG_ESPI_FLASH_CHANNEL) struct k_sem flash_rx_lock; #endif +#ifdef CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND + /* tell the interrupt handler that it is a fake request */ + bool fake_req_flag; +#endif }; /* Driver convenience defines */ @@ -190,6 +194,13 @@ static int espi_npcx_send_vwire(const struct device *dev, enum espi_vwire_signal signal, uint8_t level); static void espi_vw_send_bootload_done(const struct device *dev); +#if defined(CONFIG_ESPI_FLASH_CHANNEL) +static int espi_npcx_flash_parse_completion_with_data(const struct device *dev, + struct espi_flash_packet *pckt); +static void espi_npcx_flash_prepare_tx_header(const struct device *dev, int cyc_type, + int flash_addr, int flash_len, int tx_payload); +#endif + /* eSPI local initialization functions */ static void espi_init_wui_callback(const struct device *dev, struct miwu_callback *callback, const struct npcx_wui *wui, @@ -232,6 +243,20 @@ static void espi_bus_reset_isr(const struct device *dev) /* Do nothing! This signal is handled in ESPI_RST VW signal ISR */ } +#if defined(CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND) +static void espi_npcx_flash_fake_request(const struct device *dev) +{ + struct espi_reg *const inst = HAL_INSTANCE(dev); + struct espi_npcx_data *const data = dev->data; + + inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AMTEN); + + data->fake_req_flag = true; + + espi_npcx_flash_prepare_tx_header(dev, ESPI_FLASH_READ_CYCLE_TYPE, 0, 16, 0); +} +#endif + static void espi_bus_cfg_update_isr(const struct device *dev) { int chan; @@ -259,6 +284,13 @@ static void espi_bus_cfg_update_isr(const struct device *dev) NPCX_ESPI_HOST_CH_EN(chan)); evt.evt_details = BIT(chan); +#if defined(CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND) + if (chan == NPCX_ESPI_CH_FLASH && evt.evt_data == 1 && + IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) { + espi_npcx_flash_fake_request(dev); + } +#endif + if (evt.evt_data) { inst->ESPICFG |= BIT(chan); } else { @@ -358,6 +390,17 @@ static void espi_bus_flash_rx_isr(const struct device *dev) /* Controller Attached Flash Access */ if ((inst->ESPICFG & BIT(NPCX_ESPICFG_FLCHANMODE)) == 0) { +#ifdef CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND + if (data->fake_req_flag == true) { + uint8_t pckt_buf[16]; + struct espi_flash_packet pckt; + + pckt.buf = &pckt_buf[0]; + espi_npcx_flash_parse_completion_with_data(dev, &pckt); + data->fake_req_flag = false; + return; + } +#endif k_sem_give(&data->flash_rx_lock); } else { /* Target Attached Flash Access */ #if defined(CONFIG_ESPI_SAF) From e3d7c3b6e91aa4ce544ff581226391567a4cc6db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Mon, 11 Mar 2024 12:53:48 +0100 Subject: [PATCH 0879/2402] modules: hal_nordic: Align nRF54H20 nrfx_configs with nrfx templates MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - add new entries that appeared in nrfx 3.4.0 - correct the default IRQ priority value for PPR (it is intended to be the lowest prority, so unlike for ARM cores, for RISC-V it should be the lowest value) Signed-off-by: Andrzej Głąbek --- .../nrfx_config_nrf54h20_enga_application.h | 27 +++++++++++++++++ .../nrfx/nrfx_config_nrf54h20_enga_ppr.h | 29 ++++++++++++++++++- .../nrfx_config_nrf54h20_enga_radiocore.h | 27 +++++++++++++++++ 3 files changed, 82 insertions(+), 1 deletion(-) diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h index e6c79341b9a..af74d9d3dc3 100644 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h @@ -331,6 +331,33 @@ #define NRFX_GRTC_ENABLED 0 #endif +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + /** * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS * diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h index 369fe18a81f..65b3e2fa958 100644 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h @@ -18,7 +18,7 @@ * Integer value. Minimum: 0. Maximum: 3. */ #ifndef NRFX_DEFAULT_IRQ_PRIORITY -#define NRFX_DEFAULT_IRQ_PRIORITY 3 +#define NRFX_DEFAULT_IRQ_PRIORITY 0 #endif /** @@ -277,6 +277,33 @@ #define NRFX_GRTC_ENABLED 0 #endif +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + /** * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS * diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h index 7b9a1c4b733..ca7bf3aca63 100644 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h @@ -385,6 +385,33 @@ #define NRFX_GRTC_ENABLED 0 #endif +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + /** * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS * From e977a8d623865ad0c31dd9b32d7afb186c51dbc6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Tue, 12 Mar 2024 16:19:55 +0100 Subject: [PATCH 0880/2402] drivers: pinctrl_nrf: Set clockpin bitfield when necessary MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For certain peripheral signal lines in nRF54H20, it is required to set the clockpin bitfield for pins assigned to them, otherwise the peripheral may not work properly, for example, there will be no output from UART. Signed-off-by: Andrzej Głąbek --- drivers/pinctrl/pinctrl_nrf.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c index 12ee1d52294..950037bc8ab 100644 --- a/drivers/pinctrl/pinctrl_nrf.c +++ b/drivers/pinctrl/pinctrl_nrf.c @@ -40,16 +40,19 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = { #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uart) #define NRF_PSEL_UART(reg, line) ((NRF_UART_Type *)reg)->PSEL##line #elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uarte) +#include #define NRF_PSEL_UART(reg, line) ((NRF_UARTE_Type *)reg)->PSEL.line #endif #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spi) #define NRF_PSEL_SPIM(reg, line) ((NRF_SPI_Type *)reg)->PSEL##line #elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spim) +#include #define NRF_PSEL_SPIM(reg, line) ((NRF_SPIM_Type *)reg)->PSEL.line #endif #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spis) +#include #if defined(NRF51) #define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL##line #else @@ -64,6 +67,7 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = { #define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL.line #endif #elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twim) +#include #define NRF_PSEL_TWIM(reg, line) ((NRF_TWIM_Type *)reg)->PSEL.line #endif @@ -97,6 +101,9 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uint32_t write = NO_WRITE; nrf_gpio_pin_dir_t dir; nrf_gpio_pin_input_t input; +#if NRF_GPIO_HAS_CLOCKPIN + bool clockpin = false; +#endif if (drive_idx < ARRAY_SIZE(drive_modes)) { drive = drive_modes[drive_idx]; @@ -115,6 +122,9 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, write = 1U; dir = NRF_GPIO_PIN_DIR_OUTPUT; input = NRF_GPIO_PIN_INPUT_DISCONNECT; +#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_UARTE_CLOCKPIN_TXD_NEEDED) + clockpin = true; +#endif break; case NRF_FUN_UART_RX: NRF_PSEL_UART(reg, RXD) = psel; @@ -126,6 +136,9 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, write = 1U; dir = NRF_GPIO_PIN_DIR_OUTPUT; input = NRF_GPIO_PIN_INPUT_DISCONNECT; +#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_UARTE_CLOCKPIN_RTS_NEEDED) + clockpin = true; +#endif break; case NRF_FUN_UART_CTS: NRF_PSEL_UART(reg, CTS) = psel; @@ -139,12 +152,18 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, write = 0U; dir = NRF_GPIO_PIN_DIR_OUTPUT; input = NRF_GPIO_PIN_INPUT_CONNECT; +#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIM_CLOCKPIN_SCK_NEEDED) + clockpin = true; +#endif break; case NRF_FUN_SPIM_MOSI: NRF_PSEL_SPIM(reg, MOSI) = psel; write = 0U; dir = NRF_GPIO_PIN_DIR_OUTPUT; input = NRF_GPIO_PIN_INPUT_DISCONNECT; +#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIM_CLOCKPIN_MOSI_NEEDED) + clockpin = true; +#endif break; case NRF_FUN_SPIM_MISO: NRF_PSEL_SPIM(reg, MISO) = psel; @@ -157,6 +176,9 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, NRF_PSEL_SPIS(reg, SCK) = psel; dir = NRF_GPIO_PIN_DIR_INPUT; input = NRF_GPIO_PIN_INPUT_CONNECT; +#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIS_CLOCKPIN_SCK_NEEDED) + clockpin = true; +#endif break; case NRF_FUN_SPIS_MOSI: NRF_PSEL_SPIS(reg, MOSI) = psel; @@ -167,6 +189,9 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, NRF_PSEL_SPIS(reg, MISO) = psel; dir = NRF_GPIO_PIN_DIR_INPUT; input = NRF_GPIO_PIN_INPUT_DISCONNECT; +#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIS_CLOCKPIN_MISO_NEEDED) + clockpin = true; +#endif break; case NRF_FUN_SPIS_CSN: NRF_PSEL_SPIS(reg, CSN) = psel; @@ -188,6 +213,9 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, } dir = NRF_GPIO_PIN_DIR_INPUT; input = NRF_GPIO_PIN_INPUT_CONNECT; +#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_TWIM_CLOCKPIN_SCL_NEEDED) + clockpin = true; +#endif break; case NRF_FUN_TWIM_SDA: NRF_PSEL_TWIM(reg, SDA) = psel; @@ -196,6 +224,9 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, } dir = NRF_GPIO_PIN_DIR_INPUT; input = NRF_GPIO_PIN_INPUT_CONNECT; +#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_TWIM_CLOCKPIN_SDA_NEEDED) + clockpin = true; +#endif break; #endif /* defined(NRF_PSEL_TWIM) */ #if defined(NRF_PSEL_I2S) @@ -348,6 +379,9 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]), drive, NRF_GPIO_PIN_NOSENSE); +#if NRF_GPIO_HAS_CLOCKPIN + nrf_gpio_pin_clock_set(pin, clockpin); +#endif } } From 4011015fb4eb7fb6127a2dccce95d5de97fb081c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Mon, 11 Mar 2024 12:54:43 +0100 Subject: [PATCH 0881/2402] soc: nordic: Add initial support for nRF54H20 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Kconfig symbols that allow building for the nRF54H20 (not EngA) SoC. Signed-off-by: Andrzej Głąbek --- soc/nordic/common/vpr/Kconfig.defconfig | 2 +- soc/nordic/nrf54h/CMakeLists.txt | 2 +- soc/nordic/nrf54h/Kconfig | 25 +++++++++++++++++++ .../nrf54h/Kconfig.defconfig.nrf54h20_cpuapp | 14 +++++++++++ .../nrf54h/Kconfig.defconfig.nrf54h20_cpuppr | 12 +++++++++ .../nrf54h/Kconfig.defconfig.nrf54h20_cpurad | 14 +++++++++++ soc/nordic/nrf54h/Kconfig.soc | 18 +++++++++++++ 7 files changed, 85 insertions(+), 2 deletions(-) create mode 100644 soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp create mode 100644 soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuppr create mode 100644 soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpurad diff --git a/soc/nordic/common/vpr/Kconfig.defconfig b/soc/nordic/common/vpr/Kconfig.defconfig index f0014455b3a..a89593170f6 100644 --- a/soc/nordic/common/vpr/Kconfig.defconfig +++ b/soc/nordic/common/vpr/Kconfig.defconfig @@ -5,7 +5,7 @@ CPU_PATH := $(dt_nodelabel_path,cpu) CPU_ID := $(dt_node_reg_addr_int,$(CPU_PATH)) config RV_BOOT_HART - default $(CPU_ID) + default $(CPU_ID) if SOC_NRF54H20_ENGA_CPUPPR config RISCV_MCAUSE_EXCEPTION_MASK default 0xFFF diff --git a/soc/nordic/nrf54h/CMakeLists.txt b/soc/nordic/nrf54h/CMakeLists.txt index 67a6dab6f8a..77290a332da 100644 --- a/soc/nordic/nrf54h/CMakeLists.txt +++ b/soc/nordic/nrf54h/CMakeLists.txt @@ -1,7 +1,7 @@ # Copyright (c) 2024 Nordic Semiconductor # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_NRF54H20_ENGA_CPUAPP OR CONFIG_SOC_NRF54H20_ENGA_CPURAD) +if(CONFIG_ARM) zephyr_include_directories(.) zephyr_library_sources(soc.c) endif() diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig index d9d5b0789f9..81b6c04993c 100644 --- a/soc/nordic/nrf54h/Kconfig +++ b/soc/nordic/nrf54h/Kconfig @@ -7,6 +7,31 @@ config SOC_SERIES_NRF54HX select HAS_NRFX select HAS_NORDIC_DRIVERS +config SOC_NRF54H20_CPUAPP + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_FPU + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +config SOC_NRF54H20_CPURAD + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_FPU + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +config SOC_NRF54H20_CPUPPR + depends on RISCV_CORE_NORDIC_VPR + config SOC_NRF54H20_ENGA_CPUAPP select ARM select ARMV8_M_DSP diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp new file mode 100644 index 00000000000..1a53fb5ff32 --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF54H20 Application MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF54H20_CPUAPP + +config NUM_IRQS + default 471 + +config NRF_REGTOOL_GENERATE_UICR + default y + +endif # SOC_NRF54H20_CPUAPP diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuppr b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuppr new file mode 100644 index 00000000000..ae05e5e89d4 --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuppr @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF54H20_CPUPPR + +config NUM_IRQS + default 496 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +endif # SOC_NRF54H20_CPUPPR diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpurad b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpurad new file mode 100644 index 00000000000..4437e7aadc4 --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpurad @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF54H20 Radio MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF54H20_CPURAD + +config NUM_IRQS + default 471 + +config NRF_REGTOOL_GENERATE_UICR + default y + +endif # SOC_NRF54H20_CPURAD diff --git a/soc/nordic/nrf54h/Kconfig.soc b/soc/nordic/nrf54h/Kconfig.soc index 7ea87db22a4..2a190994183 100644 --- a/soc/nordic/nrf54h/Kconfig.soc +++ b/soc/nordic/nrf54h/Kconfig.soc @@ -9,6 +9,24 @@ config SOC_NRF54H20 help nRF54H20 +config SOC_NRF54H20_CPUAPP + bool + select SOC_NRF54H20 + help + nRF54H20 CPUAPP + +config SOC_NRF54H20_CPURAD + bool + select SOC_NRF54H20 + help + nRF54H20 CPURAD + +config SOC_NRF54H20_CPUPPR + bool + select SOC_NRF54H20 + help + nRF54H20 CPUPPR + config SOC_NRF54H20_ENGA_CPUAPP bool select SOC_NRF54H20 From 029081a3f7a81a31f2cd5afffaa1190f8045c275 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Mon, 11 Mar 2024 12:54:25 +0100 Subject: [PATCH 0882/2402] dts: nordic: Add initial support for nRF54H20 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add definition of the nRF54H20 SoC with its Application, Radio, and Peripheral Processor (PPR) cores and an initial set of peripherals. Signed-off-by: Andrzej Głąbek --- dts/arm/nordic/nrf54h20_cpuapp.dtsi | 51 + dts/arm/nordic/nrf54h20_cpurad.dtsi | 51 + dts/common/nordic/nrf54h20.dtsi | 948 ++++++++++++++++++ dts/riscv/nordic/nrf54h20_cpuppr.dtsi | 48 + .../misc/nordic-nrf-ficr-nrf54h20.h | 85 ++ 5 files changed, 1183 insertions(+) create mode 100644 dts/arm/nordic/nrf54h20_cpuapp.dtsi create mode 100644 dts/arm/nordic/nrf54h20_cpurad.dtsi create mode 100644 dts/common/nordic/nrf54h20.dtsi create mode 100644 dts/riscv/nordic/nrf54h20_cpuppr.dtsi create mode 100644 include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h diff --git a/dts/arm/nordic/nrf54h20_cpuapp.dtsi b/dts/arm/nordic/nrf54h20_cpuapp.dtsi new file mode 100644 index 00000000000..d82c69262c0 --- /dev/null +++ b/dts/arm/nordic/nrf54h20_cpuapp.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +cpu: &cpuapp {}; +systick: &cpuapp_systick {}; +nvic: &cpuapp_nvic {}; +cpuppr_vevif: &cpuppr_vevif_remote {}; + +/delete-node/ &cpuppr; +/delete-node/ &cpurad; +/delete-node/ &cpurad_peripherals; +/delete-node/ &cpurad_ppb; +/delete-node/ &cpurad_ram0; + +/ { + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpuapp_nvic>; + ranges; + }; +}; + +&cpuapp_ppb { + compatible = "simple-bus"; + ranges; +}; + +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-local"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&gpiote130 { + interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&grtc { + interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>; +}; diff --git a/dts/arm/nordic/nrf54h20_cpurad.dtsi b/dts/arm/nordic/nrf54h20_cpurad.dtsi new file mode 100644 index 00000000000..2f463f2d427 --- /dev/null +++ b/dts/arm/nordic/nrf54h20_cpurad.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +cpu: &cpurad {}; +systick: &cpurad_systick {}; +nvic: &cpurad_nvic {}; +cpuppr_vevif: &cpuppr_vevif_remote {}; + +/delete-node/ &cpuapp; +/delete-node/ &cpuapp_peripherals; +/delete-node/ &cpuapp_ppb; +/delete-node/ &cpuapp_ram0; +/delete-node/ &cpuppr; + +/ { + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpurad_nvic>; + ranges; + }; +}; + +&cpurad_ppb { + compatible = "simple-bus"; + ranges; +}; + +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-local"; +}; + +&gpiote130 { + interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&grtc { + interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>; +}; diff --git a/dts/common/nordic/nrf54h20.dtsi b/dts/common/nordic/nrf54h20.dtsi new file mode 100644 index 00000000000..78e4c5b6549 --- /dev/null +++ b/dts/common/nordic/nrf54h20.dtsi @@ -0,0 +1,948 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +/* Domain IDs. Can be used to specify channel links in IPCT nodes. */ +#define NRF_DOMAIN_ID_APPLICATION 2 +#define NRF_DOMAIN_ID_RADIOCORE 3 +#define NRF_DOMAIN_ID_GLOBALFAST 12 +#define NRF_DOMAIN_ID_GLOBALSLOW 13 + +/delete-node/ &sw_pwm; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpuapp: cpu@2 { + compatible = "arm,cortex-m33"; + reg = <2>; + device_type = "cpu"; + clock-frequency = ; + }; + + cpurad: cpu@3 { + compatible = "arm,cortex-m33"; + reg = <3>; + device_type = "cpu"; + clock-frequency = ; + }; + + cpuppr: cpu@d { + compatible = "nordic,vpr"; + reg = <13>; + device_type = "cpu"; + clock-frequency = ; + riscv,isa = "rv32emc"; + nordic,bus-width = <32>; + + cpuppr_vevif_local: mailbox { + compatible = "nordic,nrf-vevif-local"; + status = "disabled"; + interrupt-parent = <&cpuppr_clic>; + interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, + <1 NRF_DEFAULT_IRQ_PRIORITY>, + <2 NRF_DEFAULT_IRQ_PRIORITY>, + <3 NRF_DEFAULT_IRQ_PRIORITY>, + <4 NRF_DEFAULT_IRQ_PRIORITY>, + <5 NRF_DEFAULT_IRQ_PRIORITY>, + <6 NRF_DEFAULT_IRQ_PRIORITY>, + <7 NRF_DEFAULT_IRQ_PRIORITY>, + <8 NRF_DEFAULT_IRQ_PRIORITY>, + <9 NRF_DEFAULT_IRQ_PRIORITY>, + <10 NRF_DEFAULT_IRQ_PRIORITY>, + <11 NRF_DEFAULT_IRQ_PRIORITY>, + <12 NRF_DEFAULT_IRQ_PRIORITY>, + <13 NRF_DEFAULT_IRQ_PRIORITY>, + <14 NRF_DEFAULT_IRQ_PRIORITY>, + <15 NRF_DEFAULT_IRQ_PRIORITY>; + #mbox-cells = <1>; + nordic,tasks = <16>; + nordic,tasks-mask = <0xfffffff0>; + }; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + + cpurad_uicr_ext: memory@e1ff000 { + reg = <0xe1ff000 DT_SIZE_K(2)>; + }; + + cpuapp_uicr_ext: memory@e1ff800 { + reg = <0xe1ff800 DT_SIZE_K(2)>; + }; + }; + + clocks { + fll16m: fll16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + mram1x: mram@e000000 { + compatible = "nordic,mram"; + reg = <0xe000000 DT_SIZE_K(2048)>; + erase-block-size = <4096>; + write-block-size = <16>; + }; + + cpuapp_uicr: uicr@fff8000 { + compatible = "nordic,nrf-uicr-v2"; + reg = <0xfff8000 DT_SIZE_K(2)>; + domain = <2>; + ptr-ext-uicr = <&cpuapp_uicr_ext>; + }; + + cpurad_uicr: uicr@fffa000 { + compatible = "nordic,nrf-uicr-v2"; + reg = <0xfffa000 DT_SIZE_K(2)>; + domain = <3>; + ptr-ext-uicr = <&cpurad_uicr_ext>; + }; + + ficr: ficr@fffe000 { + compatible = "nordic,nrf-ficr"; + reg = <0xfffe000 DT_SIZE_K(2)>; + #nordic,ficr-cells = <1>; + }; + + cpuapp_ram0: sram@22000000 { + compatible = "mmio-sram"; + reg = <0x22000000 DT_SIZE_K(32)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000000 0x8000>; + }; + + cpurad_ram0: sram@23000000 { + compatible = "mmio-sram"; + reg = <0x23000000 DT_SIZE_K(192)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x23000000 0x30000>; + }; + + cpuapp_peripherals: peripheral@52000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x52000000 0x1000000>; + + cpuapp_hsfll: clock@d000 { + compatible = "nordic,nrf-hsfll"; + #clock-cells = <0>; + reg = <0xd000 0x1000>; + clocks = <&fll16m>; + clock-frequency = ; + nordic,ficrs = + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; + nordic,ficr-names = "vsup", "coarse", "fine"; + }; + + cpuapp_ipct: ipct@13000 { + compatible = "nordic,nrf-ipct-local"; + reg = <0x13000 0x1000>; + status = "disabled"; + channels = <4>; + interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, + <65 NRF_DEFAULT_IRQ_PRIORITY>; + }; + }; + + cpurad_peripherals: peripheral@53000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53000000 0x1000000>; + + cpurad_hsfll: clock@d000 { + compatible = "nordic,nrf-hsfll"; + #clock-cells = <0>; + reg = <0xd000 0x1000>; + clocks = <&fll16m>; + clock-frequency = ; + nordic,ficrs = + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; + nordic,ficr-names = "vsup", "coarse", "fine"; + }; + + dppic020: dppic@22000 { + compatible = "nordic,nrf-dppic-local"; + reg = <0x22000 0x1000>; + status = "disabled"; + }; + + cpurad_ipct: ipct@24000 { + compatible = "nordic,nrf-ipct-local"; + reg = <0x24000 0x1000>; + status = "disabled"; + channels = <8>; + interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, + <65 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + egu020: egu@25000 { + compatible = "nordic,nrf-egu"; + reg = <0x25000 0x1000>; + status = "disabled"; + interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + timer020: timer@28000 { + compatible = "nordic,nrf-timer"; + reg = <0x28000 0x1000>; + status = "disabled"; + cc-num = <8>; + interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer021: timer@29000 { + compatible = "nordic,nrf-timer"; + reg = <0x29000 0x1000>; + status = "disabled"; + cc-num = <8>; + interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer022: timer@2a000 { + compatible = "nordic,nrf-timer"; + reg = <0x2a000 0x1000>; + status = "disabled"; + cc-num = <8>; + interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + rtc: rtc@2b000 { + compatible = "nordic,nrf-rtc"; + reg = <0x2b000 0x1000>; + status = "disabled"; + cc-num = <4>; + clock-frequency = <32768>; + interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>; + prescaler = <1>; + }; + + radio: radio@2c000 { + compatible = "nordic,nrf-radio"; + reg = <0x2c000 0x1000>; + status = "disabled"; + ble-2mbps-supported; + ble-coded-phy-supported; + dfe-supported; + ieee802154-supported; + interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>; + + cpurad_ieee802154: ieee802154 { + compatible = "nordic,nrf-ieee802154"; + status = "disabled"; + }; + }; + + ecb030: ecb@3b000 { + compatible = "nordic,nrf-ecb"; + reg = <0x3b000 0x1000>; + interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + ccm031: ccm@3c000 { + compatible = "nordic,nrf-ccm"; + reg = <0x3c000 0x1000>; + interrupts = <60 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + ecb031: ecb@3d000 { + compatible = "nordic,nrf-ecb"; + reg = <0x3d000 0x1000>; + status = "disabled"; + interrupts = <61 NRF_DEFAULT_IRQ_PRIORITY>; + }; + }; + + global_peripherals: peripheral@5f000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5f000000 0x1000000>; + + cpusec_bellboard: mailbox@99000 { + reg = <0x99000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + cpuapp_bellboard: mailbox@9a000 { + reg = <0x9a000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + cpurad_bellboard: mailbox@9b000 { + reg = <0x9b000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + ipct120: ipct@8d1000 { + compatible = "nordic,nrf-ipct-global"; + reg = <0x8d1000 0x1000>; + status = "disabled"; + channels = <8>; + global-domain-id = <12>; + }; + + dppic120: dppic@8e1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x8e1000 0x1000>; + status = "disabled"; + }; + + timer120: timer@8e2000 { + compatible = "nordic,nrf-timer"; + reg = <0x8e2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer121: timer@8e3000 { + compatible = "nordic,nrf-timer"; + reg = <0x8e3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + spi120: spi@8e6000 { + compatible = "nordic,nrf-spim"; + reg = <0x8e6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart120: uart@8e6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x8e6000 0x1000>; + status = "disabled"; + interrupts = <229 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + spi121: spi@8e7000 { + compatible = "nordic,nrf-spim"; + reg = <0x8e7000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + cpuppr_vpr: vpr@908000 { + compatible = "nordic,nrf-vpr-coprocessor"; + reg = <0x908000 0x1000>; + status = "disabled"; + cpu = <13>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x908000 0x4000>; + + cpuppr_vevif_remote: mailbox@0 { + compatible = "nordic,nrf-vevif-remote"; + reg = <0x0 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + nordic,tasks = <16>; + nordic,tasks-mask = <0xfffffff0>; + }; + + cpuppr_clic: interrupt-controller@1000 { + compatible = "nordic,nrf-clic"; + reg = <0x1000 0x3000>; + status = "disabled"; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + }; + }; + + ipct130: ipct@921000 { + compatible = "nordic,nrf-ipct-global"; + reg = <0x921000 0x1000>; + status = "disabled"; + channels = <8>; + global-domain-id = <13>; + }; + + dppic130: dppic@922000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x922000 0x1000>; + status = "disabled"; + }; + + rtc130: rtc@928000 { + compatible = "nordic,nrf-rtc"; + reg = <0x928000 0x1000>; + status = "disabled"; + cc-num = <4>; + clock-frequency = <32768>; + interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>; + prescaler = <1>; + }; + + rtc131: rtc@929000 { + compatible = "nordic,nrf-rtc"; + reg = <0x929000 0x1000>; + status = "disabled"; + cc-num = <4>; + clock-frequency = <32768>; + interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>; + prescaler = <1>; + }; + + wdt131: watchdog@92b000 { + compatible = "nordic,nrf-wdt"; + reg = <0x92b000 0x1000>; + status = "disabled"; + interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + wdt132: watchdog@92c000 { + compatible = "nordic,nrf-wdt"; + reg = <0x92c000 0x1000>; + status = "disabled"; + interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + gpiote130: gpiote@934000 { + compatible = "nordic,nrf-gpiote"; + reg = <0x934000 0x1000>; + status = "disabled"; + instance = <130>; + }; + + gpio0: gpio@938000 { + compatible = "nordic,nrf-gpio"; + reg = <0x938000 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <12>; + port = <0>; + }; + + gpio1: gpio@938200 { + compatible = "nordic,nrf-gpio"; + reg = <0x938200 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <12>; + port = <1>; + }; + + gpio2: gpio@938400 { + compatible = "nordic,nrf-gpio"; + reg = <0x938400 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <12>; + port = <2>; + }; + + gpio6: gpio@938c00 { + compatible = "nordic,nrf-gpio"; + reg = <0x938c00 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + ngpios = <14>; + port = <6>; + }; + + gpio7: gpio@938e00 { + compatible = "nordic,nrf-gpio"; + reg = <0x938e00 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + port = <7>; + }; + + gpio9: gpio@939200 { + compatible = "nordic,nrf-gpio"; + reg = <0x939200 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <6>; + port = <9>; + }; + + dppic131: dppic@981000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x981000 0x1000>; + status = "disabled"; + }; + + comp: comparator@983000 { + compatible = "nordic,nrf-comp"; + reg = <0x983000 0x1000>; + status = "disabled"; + interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>; + #io-channel-cells = <1>; + }; + + temp: temperature-sensor@984000 { + compatible = "nordic,nrf-temp"; + reg = <0x984000 0x1000>; + interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + nfct: nfct@985000 { + compatible = "nordic,nrf-nfct"; + reg = <0x985000 0x1000>; + status = "disabled"; + interrupts = <389 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + dppic132: dppic@991000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x991000 0x1000>; + status = "disabled"; + }; + + qdec130: qdec@994000 { + compatible = "nordic,nrf-qdec"; + reg = <0x994000 0x1000>; + status = "disabled"; + interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + qdec131: qdec@995000 { + compatible = "nordic,nrf-qdec"; + reg = <0x995000 0x1000>; + status = "disabled"; + interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + grtc: grtc@99c000 { + compatible = "nordic,nrf-grtc"; + reg = <0x99c000 0x1000>; + status = "disabled"; + cc-num = <16>; + }; + + dppic133: dppic@9a1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9a1000 0x1000>; + status = "disabled"; + }; + + timer130: timer@9a2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9a2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer131: timer@9a3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9a3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + i2c130: i2c@9a5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9a5000 0x1000>; + status = "disabled"; + interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi130: spi@9a5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9a5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart130: uart@9a5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9a5000 0x1000>; + status = "disabled"; + interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + i2c131: i2c@9a6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9a6000 0x1000>; + status = "disabled"; + interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi131: spi@9a6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9a6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart131: uart@9a6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9a6000 0x1000>; + status = "disabled"; + interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + dppic134: dppic@9b1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9b1000 0x1000>; + status = "disabled"; + }; + + timer132: timer@9b2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9b2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer133: timer@9b3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9b3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + i2c132: i2c@9b5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9b5000 0x1000>; + status = "disabled"; + interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi132: spi@9b5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9b5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart132: uart@9b5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9b5000 0x1000>; + status = "disabled"; + interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + i2c133: i2c@9b6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9b6000 0x1000>; + status = "disabled"; + interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi133: spi@9b6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9b6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart133: uart@9b6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9b6000 0x1000>; + status = "disabled"; + interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + dppic135: dppic@9c1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9c1000 0x1000>; + status = "disabled"; + }; + + timer134: timer@9c2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9c2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer135: timer@9c3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9c3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + i2c134: i2c@9c5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9c5000 0x1000>; + status = "disabled"; + interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi134: spi@9c5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9c5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart134: uart@9c5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9c5000 0x1000>; + status = "disabled"; + interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + i2c135: i2c@9c6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9c6000 0x1000>; + status = "disabled"; + interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi135: spi@9c6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9c6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart135: uart@9c6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9c6000 0x1000>; + status = "disabled"; + interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + dppic136: dppic@9d1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9d1000 0x1000>; + status = "disabled"; + }; + + timer136: timer@9d2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9d2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer137: timer@9d3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9d3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + i2c136: i2c@9d5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9d5000 0x1000>; + status = "disabled"; + interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi136: spi@9d5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9d5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart136: uart@9d5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9d5000 0x1000>; + status = "disabled"; + interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + i2c137: i2c@9d6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9d6000 0x1000>; + status = "disabled"; + interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi137: spi@9d6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9d6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart137: uart@9d6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9d6000 0x1000>; + status = "disabled"; + interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; + }; + }; + }; + + cpuapp_ppb: cpuapp-ppb-bus { + #address-cells = <1>; + #size-cells = <1>; + + cpuapp_systick: timer@e000e010 { + compatible = "arm,armv8m-systick"; + reg = <0xe000e010 0x10>; + status = "disabled"; + }; + + cpuapp_nvic: interrupt-controller@e000e100 { + compatible = "arm,v8m-nvic"; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <3>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + }; + }; + + cpurad_ppb: cpurad-ppb-bus { + #address-cells = <1>; + #size-cells = <1>; + + cpurad_systick: timer@e000e010 { + compatible = "arm,armv8m-systick"; + reg = <0xe000e010 0x10>; + status = "disabled"; + }; + + cpurad_nvic: interrupt-controller@e000e100 { + compatible = "arm,v8m-nvic"; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <3>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + }; + }; +}; diff --git a/dts/riscv/nordic/nrf54h20_cpuppr.dtsi b/dts/riscv/nordic/nrf54h20_cpuppr.dtsi new file mode 100644 index 00000000000..d74147bc04b --- /dev/null +++ b/dts/riscv/nordic/nrf54h20_cpuppr.dtsi @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +cpu: &cpuppr {}; +clic: &cpuppr_clic {}; +cpuppr_vevif: &cpuppr_vevif_local {}; + +/delete-node/ &cpuapp; +/delete-node/ &cpuapp_peripherals; +/delete-node/ &cpuapp_ppb; +/delete-node/ &cpuapp_ram0; +/delete-node/ &cpurad; +/delete-node/ &cpurad_peripherals; +/delete-node/ &cpurad_ppb; +/delete-node/ &cpurad_ram0; + +/ { + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpuppr_clic>; + ranges; + }; +}; + +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&gpiote130 { + interrupts = <104 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&grtc { + interrupts = <108 NRF_DEFAULT_IRQ_PRIORITY>; +}; diff --git a/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h b/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h new file mode 100644 index 00000000000..4ebd8fb6614 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +/* autogenerated using Nordic HAL utils/gen_offsets.py script */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_H_ + +#define NRF_FICR_BLE_ADDRTYPE 0x00CU +#define NRF_FICR_BLE_ADDR_0 0x010U +#define NRF_FICR_BLE_ADDR_1 0x014U +#define NRF_FICR_BLE_ER_0 0x018U +#define NRF_FICR_BLE_ER_1 0x01CU +#define NRF_FICR_BLE_ER_2 0x020U +#define NRF_FICR_BLE_ER_3 0x024U +#define NRF_FICR_BLE_IR_0 0x028U +#define NRF_FICR_BLE_IR_1 0x02CU +#define NRF_FICR_BLE_IR_2 0x030U +#define NRF_FICR_BLE_IR_3 0x034U +#define NRF_FICR_NFC_TAGHEADER_0 0x040U +#define NRF_FICR_NFC_TAGHEADER_1 0x044U +#define NRF_FICR_NFC_TAGHEADER_2 0x048U +#define NRF_FICR_NFC_TAGHEADER_3 0x04CU +#define NRF_FICR_INFO_CONFIGID 0x050U +#define NRF_FICR_INFO_PART 0x054U +#define NRF_FICR_INFO_VARIANT 0x058U +#define NRF_FICR_INFO_PACKAGE 0x05CU +#define NRF_FICR_INFO_RAM 0x060U +#define NRF_FICR_INFO_MRAM 0x064U +#define NRF_FICR_INFO_CODEPAGESIZE 0x068U +#define NRF_FICR_INFO_CODESIZE 0x06CU +#define NRF_FICR_INFO_DEVICETYPE 0x070U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CAL_0 0x388U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CAL_1 0x38CU +#define NRF_FICR_TRIM_GLOBAL_SAADC_CAL_2 0x390U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALREF 0x394U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_0 0x398U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_1 0x39CU +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_2 0x3A0U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_3 0x3A4U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_4 0x3A8U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_5 0x3ACU +#define NRF_FICR_TRIM_GLOBAL_NFCT_BIASCFG 0x3B4U +#define NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE 0x3B8U +#define NRF_FICR_TRIM_GLOBAL_COMP_REFTRIM 0x3C0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP 0x3C8U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0 0x3CCU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_1 0x3D0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_2 0x3D4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_3 0x3D8U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_4 0x3DCU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_5 0x3E0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0 0x3E4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_1 0x3E8U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_2 0x3ECU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_3 0x3F0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_4 0x3F4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_5 0x3F8U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_TCOEF 0x3FCU +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_0_TRIM 0x400U +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_1_TRIM 0x404U +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_2_TRIM 0x408U +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_3_TRIM 0x40CU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP 0x410U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_0 0x414U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1 0x418U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_2 0x41CU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_3 0x420U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_4 0x424U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_5 0x428U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_0 0x42CU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1 0x430U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_2 0x434U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_3 0x438U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_4 0x43CU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_5 0x440U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_TCOEF 0x444U +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_0_TRIM 0x448U +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_1_TRIM 0x44CU +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_2_TRIM 0x450U +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_3_TRIM 0x454U + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_H_ */ From eac91bf8acce7f453d41b13ac7ad795e6768fdaf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Mon, 11 Mar 2024 12:55:01 +0100 Subject: [PATCH 0883/2402] modules: hal_nordic: Add nrfx configuration needed for nRF54H20 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add cmake and nrfx_config entries that allow building for the nRF54H20 SoC. Signed-off-by: Andrzej Głąbek --- modules/hal_nordic/nrfx/CMakeLists.txt | 9 + modules/hal_nordic/nrfx/nrfx_config.h | 10 +- .../nrfx/nrfx_config_nrf54h20_application.h | 1937 ++++++++++++++++ .../nrfx/nrfx_config_nrf54h20_ppr.h | 1865 +++++++++++++++ .../nrfx/nrfx_config_nrf54h20_radiocore.h | 2001 +++++++++++++++++ 5 files changed, 5820 insertions(+), 2 deletions(-) create mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_application.h create mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_ppr.h create mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_radiocore.h diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index 13ee18db7a6..84cb67093d7 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -36,6 +36,12 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF5340_CPUAPP NRF5340_XXAA_APP zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF5340_CPUAPP NRF5340_XXAA_APPLICATION) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF5340_CPUNET NRF5340_XXAA_NETWORK) zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF5340_CPUNET NRF5340_XXAA_NETWORK) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_CPUAPP NRF54H20_XXAA + NRF_APPLICATION) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_CPURAD NRF54H20_XXAA + NRF_RADIOCORE) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_CPUPPR NRF54H20_XXAA + NRF_PPR) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_ENGA NRF54L15_ENGA_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_ENGA_CPUAPP NRF_APPLICATION) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9120 NRF9120_XXAA) @@ -188,6 +194,9 @@ mdk_svd_ifdef(CONFIG_SOC_NRF52833 nrf52833.svd) mdk_svd_ifdef(CONFIG_SOC_NRF52840 nrf52840.svd) mdk_svd_ifdef(CONFIG_SOC_NRF5340_CPUAPP nrf5340_application.svd) mdk_svd_ifdef(CONFIG_SOC_NRF5340_CPUNET nrf5340_network.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUAPP nrf54h20_application.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUPPR nrf54h20_ppr.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPURAD nrf54h20_radiocore.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUAPP nrf54h20_enga_application.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUPPR nrf54h20_enga_ppr.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPURAD nrf54h20_enga_radiocore.svd) diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index 56c69447c92..693c6993029 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -941,16 +941,22 @@ #include #elif defined(NRF5340_XXAA_NETWORK) #include +#elif defined(NRF54H20_XXAA) && defined(NRF_APPLICATION) + #include +#elif defined(NRF54H20_XXAA) && defined(NRF_RADIOCORE) + #include +#elif defined(NRF54H20_XXAA) && defined(NRF_PPR) + #include #elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_APPLICATION) #include #elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_RADIOCORE) #include #elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_PPR) #include -#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) - #include #elif (defined(NRF54L15_XXAA) || defined(NRF54L15_ENGA_XXAA)) && defined(NRF_APPLICATION) #include +#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) + #include #else #error "Unknown device." #endif diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_application.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_application.h new file mode 100644 index 00000000000..5b91d921c7c --- /dev/null +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_application.h @@ -0,0 +1,1937 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NRFX_CONFIG_NRF54H20_APPLICATION_H__ +#define NRFX_CONFIG_NRF54H20_APPLICATION_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + +/** + * @brief NRFX_DEFAULT_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_DEFAULT_IRQ_PRIORITY +#define NRFX_DEFAULT_IRQ_PRIORITY 7 +#endif + +/** + * @brief NRFX_BELLBOARD_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD_ENABLED +#define NRFX_BELLBOARD_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_BELLBOARD0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD0_ENABLED +#define NRFX_BELLBOARD0_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD1_ENABLED +#define NRFX_BELLBOARD1_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD2_ENABLED +#define NRFX_BELLBOARD2_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD3_ENABLED +#define NRFX_BELLBOARD3_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED +#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL +#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0 +#endif + +/** + * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e +#endif + +/** + * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 +#endif + +/** + * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 +#endif + +/** + * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 +#endif + +/** + * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f +#endif + +/** + * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 +#endif + +/** + * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df +#endif + +/** + * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf +#endif + +/** + * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e +#endif + +/** + * @brief NRFX_EGU_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +/** + * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_EGU130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU130_ENABLED +#define NRFX_EGU130_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS + * + * Integer value. Minimum: 0. Maximum: 15. + */ +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_GPIOTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE130_ENABLED +#define NRFX_GPIOTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_ENABLED +#define NRFX_GRTC_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS + * + * Integer value. + */ +#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS +#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK + */ +#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK +#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000f0 +#endif + +/** + * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED +#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL +#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_LPCOMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_MVDMA_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA_ENABLED +#define NRFX_MVDMA_ENABLED 0 +#endif + +/** + * @brief NRFX_MVDMA120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA120_ENABLED +#define NRFX_MVDMA120_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_ENABLED +#define NRFX_NFCT_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver. + * + * Integer value. Minimum: 0. Maximum: 5. + */ +#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID +#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED +#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL +#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PDM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_BOX_0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_3_ENABLED +#define NRFX_PRS_BOX_3_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_4_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_4_ENABLED +#define NRFX_PRS_BOX_4_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_5_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_5_ENABLED +#define NRFX_PRS_BOX_5_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_6_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_6_ENABLED +#define NRFX_PRS_BOX_6_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_7_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_7_ENABLED +#define NRFX_PRS_BOX_7_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_8_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_8_ENABLED +#define NRFX_PRS_BOX_8_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_9_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_9_ENABLED +#define NRFX_PRS_BOX_9_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PWM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM120_ENABLED +#define NRFX_PWM120_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM130_ENABLED +#define NRFX_PWM130_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM131_ENABLED +#define NRFX_PWM131_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM132_ENABLED +#define NRFX_PWM132_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM133_ENABLED +#define NRFX_PWM133_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_QDEC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC130_ENABLED +#define NRFX_QDEC130_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC131_ENABLED +#define NRFX_QDEC131_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_RTC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC130_ENABLED +#define NRFX_RTC130_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC131_ENABLED +#define NRFX_RTC131_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM120_ENABLED +#define NRFX_SPIM120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM121_ENABLED +#define NRFX_SPIM121_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM130_ENABLED +#define NRFX_SPIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM131_ENABLED +#define NRFX_SPIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM132_ENABLED +#define NRFX_SPIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM133_ENABLED +#define NRFX_SPIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM134_ENABLED +#define NRFX_SPIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM135_ENABLED +#define NRFX_SPIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM136_ENABLED +#define NRFX_SPIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM137_ENABLED +#define NRFX_SPIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIS120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS120_ENABLED +#define NRFX_SPIS120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS130_ENABLED +#define NRFX_SPIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS131_ENABLED +#define NRFX_SPIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS132_ENABLED +#define NRFX_SPIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS133_ENABLED +#define NRFX_SPIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS134_ENABLED +#define NRFX_SPIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS135_ENABLED +#define NRFX_SPIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS136_ENABLED +#define NRFX_SPIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS137_ENABLED +#define NRFX_SPIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_SYSTICK_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_ENABLED +#define NRFX_TEMP_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED +#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL +#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER120_ENABLED +#define NRFX_TIMER120_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER121_ENABLED +#define NRFX_TIMER121_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER130_ENABLED +#define NRFX_TIMER130_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER131_ENABLED +#define NRFX_TIMER131_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER132_ENABLED +#define NRFX_TIMER132_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER133_ENABLED +#define NRFX_TIMER133_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER134_ENABLED +#define NRFX_TIMER134_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER135_ENABLED +#define NRFX_TIMER135_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER136_ENABLED +#define NRFX_TIMER136_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER137_ENABLED +#define NRFX_TIMER137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM130_ENABLED +#define NRFX_TWIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM131_ENABLED +#define NRFX_TWIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM132_ENABLED +#define NRFX_TWIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM133_ENABLED +#define NRFX_TWIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM134_ENABLED +#define NRFX_TWIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM135_ENABLED +#define NRFX_TWIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM136_ENABLED +#define NRFX_TWIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM137_ENABLED +#define NRFX_TWIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance + * would be initialized only once. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +/** + * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS130_ENABLED +#define NRFX_TWIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS131_ENABLED +#define NRFX_TWIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS132_ENABLED +#define NRFX_TWIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS133_ENABLED +#define NRFX_TWIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS134_ENABLED +#define NRFX_TWIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS135_ENABLED +#define NRFX_TWIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS136_ENABLED +#define NRFX_TWIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS137_ENABLED +#define NRFX_TWIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for + * configuring GPIO pins is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for + * configuring PSEL registers is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking + * of TX transfers. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_TX_LINK +#define NRFX_UARTE_CONFIG_TX_LINK 1 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED +#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 +#endif + +/** + * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_UARTE120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE120_ENABLED +#define NRFX_UARTE120_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE130_ENABLED +#define NRFX_UARTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE131_ENABLED +#define NRFX_UARTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE132_ENABLED +#define NRFX_UARTE132_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE133_ENABLED +#define NRFX_UARTE133_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE134_ENABLED +#define NRFX_UARTE134_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE135_ENABLED +#define NRFX_UARTE135_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE136_ENABLED +#define NRFX_UARTE136_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE137_ENABLED +#define NRFX_UARTE137_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_WDT010_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT010_ENABLED +#define NRFX_WDT010_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT011_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT011_ENABLED +#define NRFX_WDT011_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT131_ENABLED +#define NRFX_WDT131_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT132_ENABLED +#define NRFX_WDT132_ENABLED 0 +#endif + +#endif /* NRFX_CONFIG_NRF54H20_APPLICATION_H__ */ diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_ppr.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_ppr.h new file mode 100644 index 00000000000..4a4e6c08a8a --- /dev/null +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_ppr.h @@ -0,0 +1,1865 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NRFX_CONFIG_NRF54H20_PPR_H__ +#define NRFX_CONFIG_NRF54H20_PPR_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + +/** + * @brief NRFX_DEFAULT_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_DEFAULT_IRQ_PRIORITY +#define NRFX_DEFAULT_IRQ_PRIORITY 0 +#endif + +/** + * @brief NRFX_COMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED +#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL +#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030 +#endif + +/** + * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e +#endif + +/** + * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 +#endif + +/** + * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 +#endif + +/** + * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 +#endif + +/** + * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 +#endif + +/** + * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df +#endif + +/** + * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf +#endif + +/** + * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e +#endif + +/** + * @brief NRFX_EGU_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +/** + * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_EGU130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU130_ENABLED +#define NRFX_EGU130_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS + * + * Integer value. Minimum: 0. Maximum: 15. + */ +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_GPIOTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE130_ENABLED +#define NRFX_GPIOTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_ENABLED +#define NRFX_GRTC_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS + * + * Integer value. + */ +#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS +#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 2 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK + */ +#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK +#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000c0 +#endif + +/** + * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED +#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL +#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_LPCOMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_MVDMA_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA_ENABLED +#define NRFX_MVDMA_ENABLED 0 +#endif + +/** + * @brief NRFX_MVDMA120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA120_ENABLED +#define NRFX_MVDMA120_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_ENABLED +#define NRFX_NFCT_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver. + * + * Integer value. Minimum: 0. Maximum: 5. + */ +#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID +#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED +#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL +#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PDM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_BOX_0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_3_ENABLED +#define NRFX_PRS_BOX_3_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_4_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_4_ENABLED +#define NRFX_PRS_BOX_4_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_5_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_5_ENABLED +#define NRFX_PRS_BOX_5_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_6_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_6_ENABLED +#define NRFX_PRS_BOX_6_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_7_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_7_ENABLED +#define NRFX_PRS_BOX_7_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_8_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_8_ENABLED +#define NRFX_PRS_BOX_8_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_9_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_9_ENABLED +#define NRFX_PRS_BOX_9_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PWM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM120_ENABLED +#define NRFX_PWM120_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM130_ENABLED +#define NRFX_PWM130_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM131_ENABLED +#define NRFX_PWM131_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM132_ENABLED +#define NRFX_PWM132_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM133_ENABLED +#define NRFX_PWM133_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_QDEC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC130_ENABLED +#define NRFX_QDEC130_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC131_ENABLED +#define NRFX_QDEC131_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_RTC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC130_ENABLED +#define NRFX_RTC130_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC131_ENABLED +#define NRFX_RTC131_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM120_ENABLED +#define NRFX_SPIM120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM121_ENABLED +#define NRFX_SPIM121_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM130_ENABLED +#define NRFX_SPIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM131_ENABLED +#define NRFX_SPIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM132_ENABLED +#define NRFX_SPIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM133_ENABLED +#define NRFX_SPIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM134_ENABLED +#define NRFX_SPIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM135_ENABLED +#define NRFX_SPIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM136_ENABLED +#define NRFX_SPIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM137_ENABLED +#define NRFX_SPIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIS120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS120_ENABLED +#define NRFX_SPIS120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS130_ENABLED +#define NRFX_SPIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS131_ENABLED +#define NRFX_SPIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS132_ENABLED +#define NRFX_SPIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS133_ENABLED +#define NRFX_SPIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS134_ENABLED +#define NRFX_SPIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS135_ENABLED +#define NRFX_SPIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS136_ENABLED +#define NRFX_SPIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS137_ENABLED +#define NRFX_SPIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_ENABLED +#define NRFX_TEMP_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED +#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL +#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER120_ENABLED +#define NRFX_TIMER120_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER121_ENABLED +#define NRFX_TIMER121_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER130_ENABLED +#define NRFX_TIMER130_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER131_ENABLED +#define NRFX_TIMER131_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER132_ENABLED +#define NRFX_TIMER132_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER133_ENABLED +#define NRFX_TIMER133_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER134_ENABLED +#define NRFX_TIMER134_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER135_ENABLED +#define NRFX_TIMER135_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER136_ENABLED +#define NRFX_TIMER136_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER137_ENABLED +#define NRFX_TIMER137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM130_ENABLED +#define NRFX_TWIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM131_ENABLED +#define NRFX_TWIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM132_ENABLED +#define NRFX_TWIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM133_ENABLED +#define NRFX_TWIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM134_ENABLED +#define NRFX_TWIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM135_ENABLED +#define NRFX_TWIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM136_ENABLED +#define NRFX_TWIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM137_ENABLED +#define NRFX_TWIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance + * would be initialized only once. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +/** + * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS130_ENABLED +#define NRFX_TWIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS131_ENABLED +#define NRFX_TWIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS132_ENABLED +#define NRFX_TWIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS133_ENABLED +#define NRFX_TWIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS134_ENABLED +#define NRFX_TWIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS135_ENABLED +#define NRFX_TWIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS136_ENABLED +#define NRFX_TWIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS137_ENABLED +#define NRFX_TWIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for + * configuring GPIO pins is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for + * configuring PSEL registers is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking + * of TX transfers. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_TX_LINK +#define NRFX_UARTE_CONFIG_TX_LINK 1 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED +#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 +#endif + +/** + * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_UARTE120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE120_ENABLED +#define NRFX_UARTE120_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE130_ENABLED +#define NRFX_UARTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE131_ENABLED +#define NRFX_UARTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE132_ENABLED +#define NRFX_UARTE132_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE133_ENABLED +#define NRFX_UARTE133_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE134_ENABLED +#define NRFX_UARTE134_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE135_ENABLED +#define NRFX_UARTE135_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE136_ENABLED +#define NRFX_UARTE136_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE137_ENABLED +#define NRFX_UARTE137_ENABLED 0 +#endif + +/** + * @brief NRFX_VEVIF_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_VEVIF_ENABLED +#define NRFX_VEVIF_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_WDT131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT131_ENABLED +#define NRFX_WDT131_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT132_ENABLED +#define NRFX_WDT132_ENABLED 0 +#endif + +#endif /* NRFX_CONFIG_NRF54H20_PPR_H__ */ diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_radiocore.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_radiocore.h new file mode 100644 index 00000000000..274073e6a38 --- /dev/null +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_radiocore.h @@ -0,0 +1,2001 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NRFX_CONFIG_NRF54H20_RADIOCORE_H__ +#define NRFX_CONFIG_NRF54H20_RADIOCORE_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + +/** + * @brief NRFX_DEFAULT_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_DEFAULT_IRQ_PRIORITY +#define NRFX_DEFAULT_IRQ_PRIORITY 7 +#endif + +/** + * @brief NRFX_BELLBOARD_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD_ENABLED +#define NRFX_BELLBOARD_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_BELLBOARD0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD0_ENABLED +#define NRFX_BELLBOARD0_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD1_ENABLED +#define NRFX_BELLBOARD1_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD2_ENABLED +#define NRFX_BELLBOARD2_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD3_ENABLED +#define NRFX_BELLBOARD3_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED +#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL +#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0 +#endif + +/** + * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e +#endif + +/** + * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 +#endif + +/** + * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 +#endif + +/** + * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 +#endif + +/** + * @brief NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f +#endif + +/** + * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 +#endif + +/** + * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df +#endif + +/** + * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf +#endif + +/** + * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e +#endif + +/** + * @brief NRFX_EGU_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +/** + * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_EGU020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU020_ENABLED +#define NRFX_EGU020_ENABLED 0 +#endif + +/** + * @brief NRFX_EGU130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU130_ENABLED +#define NRFX_EGU130_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS + * + * Integer value. Minimum: 0. Maximum: 15. + */ +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_GPIOTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE130_ENABLED +#define NRFX_GPIOTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_ENABLED +#define NRFX_GRTC_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS + * + * Integer value. + */ +#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS +#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK + */ +#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK +#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f00 +#endif + +/** + * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED +#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL +#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030 +#endif + +/** + * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000c0 +#endif + +/** + * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_LPCOMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_MVDMA_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA_ENABLED +#define NRFX_MVDMA_ENABLED 0 +#endif + +/** + * @brief NRFX_MVDMA120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA120_ENABLED +#define NRFX_MVDMA120_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_ENABLED +#define NRFX_NFCT_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver. + * + * Integer value. Minimum: 0. Maximum: 5. + */ +#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID +#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED +#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL +#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PDM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_BOX_0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_3_ENABLED +#define NRFX_PRS_BOX_3_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_4_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_4_ENABLED +#define NRFX_PRS_BOX_4_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_5_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_5_ENABLED +#define NRFX_PRS_BOX_5_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_6_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_6_ENABLED +#define NRFX_PRS_BOX_6_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_7_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_7_ENABLED +#define NRFX_PRS_BOX_7_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_8_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_8_ENABLED +#define NRFX_PRS_BOX_8_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_9_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_9_ENABLED +#define NRFX_PRS_BOX_9_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PWM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM120_ENABLED +#define NRFX_PWM120_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM130_ENABLED +#define NRFX_PWM130_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM131_ENABLED +#define NRFX_PWM131_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM132_ENABLED +#define NRFX_PWM132_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM133_ENABLED +#define NRFX_PWM133_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_QDEC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC130_ENABLED +#define NRFX_QDEC130_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC131_ENABLED +#define NRFX_QDEC131_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_RTC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC130_ENABLED +#define NRFX_RTC130_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC131_ENABLED +#define NRFX_RTC131_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM120_ENABLED +#define NRFX_SPIM120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM121_ENABLED +#define NRFX_SPIM121_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM130_ENABLED +#define NRFX_SPIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM131_ENABLED +#define NRFX_SPIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM132_ENABLED +#define NRFX_SPIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM133_ENABLED +#define NRFX_SPIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM134_ENABLED +#define NRFX_SPIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM135_ENABLED +#define NRFX_SPIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM136_ENABLED +#define NRFX_SPIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM137_ENABLED +#define NRFX_SPIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIS120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS120_ENABLED +#define NRFX_SPIS120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS130_ENABLED +#define NRFX_SPIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS131_ENABLED +#define NRFX_SPIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS132_ENABLED +#define NRFX_SPIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS133_ENABLED +#define NRFX_SPIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS134_ENABLED +#define NRFX_SPIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS135_ENABLED +#define NRFX_SPIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS136_ENABLED +#define NRFX_SPIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS137_ENABLED +#define NRFX_SPIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_SYSTICK_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_ENABLED +#define NRFX_TEMP_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED +#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL +#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER020_ENABLED +#define NRFX_TIMER020_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER021_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER021_ENABLED +#define NRFX_TIMER021_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER022_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER022_ENABLED +#define NRFX_TIMER022_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER120_ENABLED +#define NRFX_TIMER120_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER121_ENABLED +#define NRFX_TIMER121_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER130_ENABLED +#define NRFX_TIMER130_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER131_ENABLED +#define NRFX_TIMER131_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER132_ENABLED +#define NRFX_TIMER132_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER133_ENABLED +#define NRFX_TIMER133_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER134_ENABLED +#define NRFX_TIMER134_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER135_ENABLED +#define NRFX_TIMER135_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER136_ENABLED +#define NRFX_TIMER136_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER137_ENABLED +#define NRFX_TIMER137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM130_ENABLED +#define NRFX_TWIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM131_ENABLED +#define NRFX_TWIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM132_ENABLED +#define NRFX_TWIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM133_ENABLED +#define NRFX_TWIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM134_ENABLED +#define NRFX_TWIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM135_ENABLED +#define NRFX_TWIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM136_ENABLED +#define NRFX_TWIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM137_ENABLED +#define NRFX_TWIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance + * would be initialized only once. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +/** + * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS130_ENABLED +#define NRFX_TWIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS131_ENABLED +#define NRFX_TWIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS132_ENABLED +#define NRFX_TWIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS133_ENABLED +#define NRFX_TWIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS134_ENABLED +#define NRFX_TWIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS135_ENABLED +#define NRFX_TWIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS136_ENABLED +#define NRFX_TWIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS137_ENABLED +#define NRFX_TWIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for + * configuring GPIO pins is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for + * configuring PSEL registers is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking + * of TX transfers. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_TX_LINK +#define NRFX_UARTE_CONFIG_TX_LINK 1 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED +#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 +#endif + +/** + * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_UARTE120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE120_ENABLED +#define NRFX_UARTE120_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE130_ENABLED +#define NRFX_UARTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE131_ENABLED +#define NRFX_UARTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE132_ENABLED +#define NRFX_UARTE132_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE133_ENABLED +#define NRFX_UARTE133_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE134_ENABLED +#define NRFX_UARTE134_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE135_ENABLED +#define NRFX_UARTE135_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE136_ENABLED +#define NRFX_UARTE136_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE137_ENABLED +#define NRFX_UARTE137_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_WDT010_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT010_ENABLED +#define NRFX_WDT010_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT011_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT011_ENABLED +#define NRFX_WDT011_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT131_ENABLED +#define NRFX_WDT131_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT132_ENABLED +#define NRFX_WDT132_ENABLED 0 +#endif + +#endif /* NRFX_CONFIG_NRF54H20_RADIOCORE_H__ */ From d0ce78f23028385b3e512f92d1b8ce925602db6f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Tue, 12 Mar 2024 15:00:05 +0100 Subject: [PATCH 0884/2402] boards: nordic: Add support for nRF54H20 DK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add targets for the Application, Radio, and PPR cores in the nRF54H20 SoC on the nRF54H20 DK board. Signed-off-by: Andrzej Głąbek --- boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk | 8 + boards/nordic/nrf54h20dk/board.cmake | 13 ++ boards/nordic/nrf54h20dk/board.yml | 8 + boards/nordic/nrf54h20dk/doc/index.rst | 154 +++++++++++++++ boards/nordic/nrf54h20dk/nrf54h20dk_defconfig | 9 + .../nrf54h20dk_nrf54h20-ipc_conf.dtsi | 36 ++++ .../nrf54h20dk_nrf54h20-memory_map.dtsi | 184 ++++++++++++++++++ .../nrf54h20dk_nrf54h20-pinctrl.dtsi | 53 +++++ .../nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 171 ++++++++++++++++ .../nrf54h20dk_nrf54h20_cpuapp.yaml | 15 ++ .../nrf54h20dk_nrf54h20_cpuapp_defconfig | 21 ++ .../nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts | 56 ++++++ .../nrf54h20dk_nrf54h20_cpuppr.yaml | 13 ++ .../nrf54h20dk_nrf54h20_cpuppr_defconfig | 4 + .../nrf54h20dk_nrf54h20_cpuppr_ram.yaml | 13 ++ .../nrf54h20dk_nrf54h20_cpuppr_ram_defconfig | 4 + .../nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts | 84 ++++++++ .../nrf54h20dk_nrf54h20_cpurad.yaml | 15 ++ .../nrf54h20dk_nrf54h20_cpurad_defconfig | 18 ++ .../support/nrf54h20_cpurad.JLinkScript | 4 + 20 files changed, 883 insertions(+) create mode 100644 boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk create mode 100644 boards/nordic/nrf54h20dk/board.cmake create mode 100644 boards/nordic/nrf54h20dk/board.yml create mode 100644 boards/nordic/nrf54h20dk/doc/index.rst create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_defconfig create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.yaml create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram.yaml create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.yaml create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_defconfig create mode 100644 boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript diff --git a/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk b/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk new file mode 100644 index 00000000000..fb9e66406f8 --- /dev/null +++ b/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54H20DK + select SOC_NRF54H20_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPUAPP + select SOC_NRF54H20_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD + select SOC_NRF54H20_CPUPPR if BOARD_NRF54H20DK_NRF54H20_CPUPPR || \ + BOARD_NRF54H20DK_NRF54H20_CPUPPR_RAM diff --git a/boards/nordic/nrf54h20dk/board.cmake b/boards/nordic/nrf54h20dk/board.cmake new file mode 100644 index 00000000000..32d1daac179 --- /dev/null +++ b/boards/nordic/nrf54h20dk/board.cmake @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD) + if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD) + set( + JLINK_TOOL_OPT + "-jlinkscriptfile ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpurad.JLinkScript" + ) + endif() + + board_runner_args(jlink "--device=CORTEX-M33" "--speed=4000" "--tool-opt=${JLINK_TOOL_OPT}") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nordic/nrf54h20dk/board.yml b/boards/nordic/nrf54h20dk/board.yml new file mode 100644 index 00000000000..156f817f86d --- /dev/null +++ b/boards/nordic/nrf54h20dk/board.yml @@ -0,0 +1,8 @@ +board: + name: nrf54h20dk + vendor: nordic + socs: + - name: nrf54h20 + variants: + - name: ram + cpucluster: cpuppr diff --git a/boards/nordic/nrf54h20dk/doc/index.rst b/boards/nordic/nrf54h20dk/doc/index.rst new file mode 100644 index 00000000000..6b8a08f0953 --- /dev/null +++ b/boards/nordic/nrf54h20dk/doc/index.rst @@ -0,0 +1,154 @@ +.. _nrf54h20dk_nrf54h20: + +nRF54H20 DK +########### + +Overview +******** + +.. note:: + + All software for the nRF54H20 SoC is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The nRF54H20 DK is a single-board development kit for evaluation and development +on the Nordic nRF54H20 System-on-Chip (SoC). + +The nRF54H20 is a multicore SoC with: + +* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security + Extensions, running at up to 320 MHz, referred to as the **application core** +* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security + Extensions, running at up to 256 MHz, referred to as the **radio core**. + +The ``nrf54h20dk/nrf54h20/cpuapp`` build target provides support for +the application core on the nRF54H20 SoC. +The ``nrf54h20dk/nrf54h20/cpurad`` build target provides support for +the radio core on the nRF54H20 SoC. + +nRF54H20 SoC provides support for the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`GRTC (Global real-time counter)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* MRAM +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +Hardware +******** + +nRF54H20 DK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +Supported Features +================== + +The ``nrf54h20dk/nrf54h20/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``nrf54h20dk/nrf54h20/cpurad`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +LEDs +---- + +* LED1 (green) = P9.0 +* LED2 (green) = P9.1 +* LED3 (green) = P9.2 +* LED4 (green) = P9.3 + +Push buttons +------------ + +* BUTTON1 = P0.8 +* BUTTON2 = P0.9 +* BUTTON3 = P0.10 +* BUTTON4 = P0.11 +* RESET (SW1) + +Programming and Debugging +************************* + +Applications for both the ``nrf54h20dk/nrf54h20/cpuapp`` and +``nrf54h20dk/nrf54h20/cpurad`` targets can be built, flashed, +and debugged in the usual way. See :ref:`build_an_application` +and :ref:`application_run` for more details on building and running. + +Flashing +======== + +As an example, this section shows how to build and flash the :ref:`hello_world` +application. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF54H20 DK, complete the following steps: + +1. Connect the nRF54H20 DK to your computer using the IMCU USB port on the DK. +#. Build the sample by running the following command: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf54h20dk/nrf54h20/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF54H20 DK +*********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs +on the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts`. diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_defconfig new file mode 100644 index 00000000000..bad567cbd74 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi new file mode 100644 index 00000000000..9c3d971b9bc --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + ipc { + cpusec_cpuapp_ipc: ipc-1-2 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpusec_bellboard 12>, + <&cpuapp_bellboard 0>; + }; + + cpusec_cpurad_ipc: ipc-1-3 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpusec_bellboard 18>, + <&cpurad_bellboard 0>; + }; + + cpuapp_cpurad_ipc: ipc-2-3 { + status = "disabled"; + mboxes = <&cpuapp_bellboard 18>, + <&cpurad_bellboard 12>; + }; + + cpuapp_cpuppr_ipc: ipc-2-13 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpuapp_bellboard 13>, + <&cpuppr_vevif 12>; + }; + }; +}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi new file mode 100644 index 00000000000..6b6402eb90f --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + reserved-memory { + cpuapp_ram0x_region: memory@2f000000 { + compatible = "nordic,owned-memory"; + reg = <0x2f000000 DT_SIZE_K(260)>; + status = "disabled"; + perm-read; + perm-write; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f000000 0x41000>; + + cpusec_cpuapp_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpuapp_cpusec_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + + cpuapp_data: memory@1000 { + reg = <0x1000 DT_SIZE_K(256)>; + }; + }; + + cpurad_ram0x_region: memory@2f041000 { + compatible = "nordic,owned-memory"; + reg = <0x2f041000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f041000 0x1000>; + + cpusec_cpurad_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpurad_cpusec_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + }; + + cpuapp_cpurad_ram0x_region: memory@2f0bf000 { + compatible = "nordic,owned-memory"; + reg = <0x2f0bf000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f0bf000 0x1000>; + + cpuapp_cpurad_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpurad_cpuapp_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + }; + + shared_ram20_region: memory@2f88f000 { + compatible = "nordic,owned-memory"; + reg = <0x2f88f000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f88f000 0x1000>; + + cpuapp_cpusys_ipc_shm: memory@ce0 { + reg = <0xce0 0x80>; + }; + + cpusys_cpuapp_ipc_shm: memory@d60 { + reg = <0xd60 0x80>; + }; + + cpurad_cpusys_ipc_shm: memory@e00 { + reg = <0xe00 0x80>; + }; + + cpusys_cpurad_ipc_shm: memory@e80 { + reg = <0xe80 0x80>; + }; + }; + + cpuppr_ram3x_region: memory@2fc00000 { + compatible = "nordic,owned-memory"; + reg = <0x2fc00000 DT_SIZE_K(64)>; + status = "disabled"; + perm-read; + perm-write; + perm-execute; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2fc00000 0x10000>; + + cpuppr_code_data: memory@0 { + reg = <0x0 DT_SIZE_K(62)>; + }; + + cpuapp_cpuppr_ipc_shm: memory@f800 { + reg = <0xf800 DT_SIZE_K(1)>; + }; + + cpuppr_cpuapp_ipc_shm: memory@fc00 { + reg = <0xfc00 DT_SIZE_K(1)>; + }; + }; + + shared_ram3x_region: memory@2fc12000 { + compatible = "nordic,owned-memory"; + reg = <0x2fc12000 DT_SIZE_K(8)>; + status = "disabled"; + perm-read; + perm-write; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2fc12000 0x2000>; + + cpuapp_dma_region: memory@e80 { + compatible = "zephyr,memory-region"; + reg = <0xe80 DT_SIZE_K(4)>; + status = "disabled"; + #memory-region-cells = <0>; + zephyr,memory-region = "DMA_RAM3x_APP"; + }; + + cpurad_dma_region: memory@1e80 { + compatible = "zephyr,memory-region"; + reg = <0x1e80 0x80>; + status = "disabled"; + #memory-region-cells = <0>; + zephyr,memory-region = "DMA_RAM3x_RAD"; + }; + }; + }; +}; + +&mram1x { + cpurad_rx_partitions: cpurad-rx-partitions { + compatible = "nordic,owned-partitions", "fixed-partitions"; + status = "disabled"; + perm-read; + perm-execute; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + + cpurad_slot0_partition: partition@66000 { + reg = <0x66000 DT_SIZE_K(256)>; + }; + }; + + cpuapp_rx_partitions: cpuapp-rx-partitions { + compatible = "nordic,owned-partitions", "fixed-partitions"; + status = "disabled"; + perm-read; + perm-execute; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + + cpuapp_slot0_partition: partition@a6000 { + reg = <0xa6000 DT_SIZE_K(512)>; + }; + + cpuppr_code_partition: partition@126000 { + reg = <0x126000 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi new file mode 100644 index 00000000000..6c6da3fa747 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart135_default: uart135_default { + group1 { + psels = , + ; + }; + + group2 { + bias-pull-up; + psels = , + ; + }; + }; + + /omit-if-no-ref/ uart135_sleep: uart135_sleep { + group1 { + low-power-enable; + psels = , + , + , + ; + }; + }; + + /omit-if-no-ref/ uart136_default: uart136_default { + group1 { + psels = , + ; + }; + + group2 { + bias-pull-up; + psels = , + ; + }; + }; + + /omit-if-no-ref/ uart136_sleep: uart136_sleep { + group1 { + low-power-enable; + psels = , + , + , + ; + }; + }; +}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts new file mode 100644 index 00000000000..3873fec457e --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf54h20dk_nrf54h20-memory_map.dtsi" +#include "nrf54h20dk_nrf54h20-ipc_conf.dtsi" +#include "nrf54h20dk_nrf54h20-pinctrl.dtsi" + +/delete-node/ &cpusec_cpurad_ipc; + +/ { + compatible = "nordic,nrf54h20dk_nrf54h20-cpuapp"; + model = "Nordic nRF54H20 DK nRF54H20 Application MCU"; + + chosen { + zephyr,console = &uart136; + zephyr,code-partition = &cpuapp_slot0_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpuapp_data; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio0 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + + led2: led_2 { + gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + + led3: led_3 { + gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; +}; + +&cpuapp_ram0x_region { + status = "okay"; +}; + +&shared_ram3x_region { + status = "okay"; +}; + +&cpuapp_bellboard { + interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0"; + /* irq0: 0: cpuapp-cpusec, 13: cpuapp-cpuppr, 18: cpuapp-cpurad */ + nordic,interrupt-mapping = <0x00042001 0>; +}; + +&cpusec_cpuapp_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuapp_cpusec_ipc_shm>; + rx-region = <&cpusec_cpuapp_ipc_shm>; +}; + +&cpuapp_cpurad_ipc { + compatible = "zephyr,ipc-icmsg-me-initiator"; + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpurad_ipc_shm>; + rx-region = <&cpurad_cpuapp_ipc_shm>; +}; + +&cpuapp_cpuppr_ipc { + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpuppr_ipc_shm>; + rx-region = <&cpuppr_cpuapp_ipc_shm>; +}; + +&cpuapp_dma_region { + status = "okay"; +}; + +&cpuapp_rx_partitions { + status = "okay"; +}; + +&cpuppr_vpr { + execution-memory = <&cpuppr_code_partition>; +}; + +&gpiote130 { + status = "okay"; + owned-channels = <0 1 2 3 4 5 6 7>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio9 { + status = "okay"; +}; + +&grtc { + status = "okay"; + child-owned-channels = <5 6>; + nonsecure-channels = <5 6>; + owned-channels = <4 5 6>; +}; + +&uart135 { + current-speed = <115200>; + pinctrl-0 = <&uart135_default>; + pinctrl-1 = <&uart135_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart136 { + status = "okay"; + memory-regions = <&cpuapp_dma_region>; + current-speed = <115200>; + pinctrl-0 = <&uart136_default>; + pinctrl-1 = <&uart136_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.yaml new file mode 100644 index 00000000000..0ba6bfe3ba2 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk/nrf54h20/cpuapp +name: nRF54H20-DK-nRF54H20-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 256 +flash: 512 +supported: + - gpio diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig new file mode 100644 index 00000000000..b014eb7b031 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_USE_DT_CODE_PARTITION=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot be applied +# as the (0x0 - 0x400) region is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts new file mode 100644 index 00000000000..edce1a8b275 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf54h20dk_nrf54h20-memory_map.dtsi" +#include "nrf54h20dk_nrf54h20-ipc_conf.dtsi" +#include "nrf54h20dk_nrf54h20-pinctrl.dtsi" + +/delete-node/ &cpuapp_cpurad_ipc; +/delete-node/ &cpusec_cpuapp_ipc; +/delete-node/ &cpusec_cpurad_ipc; + +/ { + compatible = "nordic,nrf54h20dk_nrf54h20-cpuppr"; + model = "Nordic nRF54H20 DK nRF54H20 Peripheral Processor MCU"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart135; + zephyr,code-partition = &cpuppr_code_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpuppr_code_data; + }; +}; + +&cpuapp_cpuppr_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuppr_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpuppr_ipc_shm>; +}; + +&grtc { + status = "okay"; + owned-channels = <5>; +}; + +&uart135 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart135_default>; + pinctrl-1 = <&uart135_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart136 { + current-speed = <115200>; + pinctrl-0 = <&uart136_default>; + pinctrl-1 = <&uart136_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml new file mode 100644 index 00000000000..876debfb62c --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk/nrf54h20/cpuppr +name: nRF54H20-DK-nRF54H20-PPR +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 62 +flash: 64 +supported: + - gpio diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig new file mode 100644 index 00000000000..0e657c5081e --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram.yaml new file mode 100644 index 00000000000..f35f6f0cbdc --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk/nrf54h20/cpuppr/ram +name: nRF54H20-DK-nRF54H20-PPR-RAM +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 62 +flash: 62 +supported: + - gpio diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig new file mode 100644 index 00000000000..bc8ce62afbb --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts new file mode 100644 index 00000000000..1998f4fc131 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf54h20dk_nrf54h20-memory_map.dtsi" +#include "nrf54h20dk_nrf54h20-ipc_conf.dtsi" +#include "nrf54h20dk_nrf54h20-pinctrl.dtsi" + +/delete-node/ &cpuapp_cpuppr_ipc; +/delete-node/ &cpusec_cpuapp_ipc; + +/ { + compatible = "nordic,nrf54h20dk_nrf54h20-cpurad"; + model = "Nordic nRF54H20 DK nRF54H20 Radio MCU"; + + chosen { + zephyr,console = &uart135; + zephyr,code-partition = &cpurad_slot0_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpurad_ram0; + }; +}; + +&shared_ram3x_region { + status = "okay"; +}; + +&cpurad_bellboard { + interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0"; + /* irq0: 0: cpurad-cpusec, 12: cpurad-cpuapp */ + nordic,interrupt-mapping = <0x00001001 0>; +}; + +&cpusec_cpurad_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpurad_cpusec_ipc_shm>; + rx-region = <&cpusec_cpurad_ipc_shm>; +}; + +&cpuapp_cpurad_ipc { + compatible = "zephyr,ipc-icmsg-me-follower"; + mbox-names = "tx", "rx"; + tx-region = <&cpurad_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpurad_ipc_shm>; +}; + +&cpurad_dma_region { + status = "okay"; +}; + +&cpurad_rx_partitions { + status = "okay"; +}; + +&grtc { + status = "okay"; + child-owned-channels = <8 9 10 11 12>; + interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>, + <108 NRF_DEFAULT_IRQ_PRIORITY>; + nonsecure-channels = <8 9 10 11 12>; + owned-channels = <7 8 9 10 11 12 13 14>; +}; + +&uart135 { + status = "okay"; + memory-regions = <&cpurad_dma_region>; + current-speed = <115200>; + pinctrl-0 = <&uart135_default>; + pinctrl-1 = <&uart135_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart136 { + current-speed = <115200>; + pinctrl-0 = <&uart136_default>; + pinctrl-1 = <&uart136_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.yaml new file mode 100644 index 00000000000..420d854cbca --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk/nrf54h20/cpurad +name: nRF54H20-DK-nRF54H20-Radio +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 192 +flash: 256 +supported: + - gpio diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_defconfig new file mode 100644 index 00000000000..1a62a205502 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_USE_DT_CODE_PARTITION=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot be applied +# as the (0x0 - 0x400) region is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y diff --git a/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript b/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript new file mode 100644 index 00000000000..2fb7e32302e --- /dev/null +++ b/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript @@ -0,0 +1,4 @@ +void ConfigTargetSettings(void) { + JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP"); + CORESIGHT_IndexAHBAPToUse = 1; +} From 7cda16528c2c47f821f9233b8aff59ed26a518b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Wed, 13 Mar 2024 17:20:12 +0100 Subject: [PATCH 0885/2402] samples: Replace nRF54H20 PDK with nRF54H20 DK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit nRF54H20 PDK is superseded by nRF54H20 DK and will no longer be supported. Signed-off-by: Andrzej Głąbek --- samples/drivers/mbox/CMakeLists.txt | 2 +- samples/drivers/mbox/Kconfig.sysbuild | 2 +- ...nrf54h20dk_nrf54h20_cpuapp_bellboard.conf} | 0 ...54h20dk_nrf54h20_cpuapp_bellboard.overlay} | 0 ... => nrf54h20dk_nrf54h20_cpuapp_vevif.conf} | 0 ... nrf54h20dk_nrf54h20_cpuapp_vevif.overlay} | 0 samples/drivers/mbox/remote/CMakeLists.txt | 2 +- ...nrf54h20dk_nrf54h20_cpuppr_bellboard.conf} | 0 ...54h20dk_nrf54h20_cpuppr_bellboard.overlay} | 0 ... => nrf54h20dk_nrf54h20_cpuppr_vevif.conf} | 0 ... nrf54h20dk_nrf54h20_cpuppr_vevif.overlay} | 0 samples/drivers/mbox/sample.yaml | 24 +++++++++---------- 12 files changed, 15 insertions(+), 15 deletions(-) rename samples/drivers/mbox/boards/{nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf => nrf54h20dk_nrf54h20_cpuapp_bellboard.conf} (100%) rename samples/drivers/mbox/boards/{nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay => nrf54h20dk_nrf54h20_cpuapp_bellboard.overlay} (100%) rename samples/drivers/mbox/boards/{nrf54h20pdk_nrf54h20_cpuapp_vevif.conf => nrf54h20dk_nrf54h20_cpuapp_vevif.conf} (100%) rename samples/drivers/mbox/boards/{nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay => nrf54h20dk_nrf54h20_cpuapp_vevif.overlay} (100%) rename samples/drivers/mbox/remote/boards/{nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf => nrf54h20dk_nrf54h20_cpuppr_bellboard.conf} (100%) rename samples/drivers/mbox/remote/boards/{nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay => nrf54h20dk_nrf54h20_cpuppr_bellboard.overlay} (100%) rename samples/drivers/mbox/remote/boards/{nrf54h20pdk_nrf54h20_cpuppr_vevif.conf => nrf54h20dk_nrf54h20_cpuppr_vevif.conf} (100%) rename samples/drivers/mbox/remote/boards/{nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay => nrf54h20dk_nrf54h20_cpuppr_vevif.overlay} (100%) diff --git a/samples/drivers/mbox/CMakeLists.txt b/samples/drivers/mbox/CMakeLists.txt index 6b54d013431..dee828b30ba 100644 --- a/samples/drivers/mbox/CMakeLists.txt +++ b/samples/drivers/mbox/CMakeLists.txt @@ -18,7 +18,7 @@ if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "mimxrt1170_evk") OR ("${BOARD}" STREQUAL "mimxrt1160_evk") OR ("${BOARD}" STREQUAL "lpcxpresso55s69") OR - ("${BOARD}" STREQUAL "nrf54h20pdk")) + ("${BOARD}" STREQUAL "nrf54h20dk")) message(STATUS "${BOARD} compile as Main in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/Kconfig.sysbuild b/samples/drivers/mbox/Kconfig.sysbuild index 9dfa36077ee..dfc99e4aea1 100644 --- a/samples/drivers/mbox/Kconfig.sysbuild +++ b/samples/drivers/mbox/Kconfig.sysbuild @@ -14,4 +14,4 @@ string default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" - default "nrf54h20pdk/nrf54h20/cpuppr" if $(BOARD) = "nrf54h20pdk" + default "nrf54h20dk/nrf54h20/cpuppr" if $(BOARD) = "nrf54h20dk" diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf b/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.conf similarity index 100% rename from samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf rename to samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.conf diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay b/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.overlay similarity index 100% rename from samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay rename to samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.overlay diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf b/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_vevif.conf similarity index 100% rename from samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf rename to samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_vevif.conf diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay b/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_vevif.overlay similarity index 100% rename from samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay rename to samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_vevif.overlay diff --git a/samples/drivers/mbox/remote/CMakeLists.txt b/samples/drivers/mbox/remote/CMakeLists.txt index d0ba1a94e57..9a16f7588c6 100644 --- a/samples/drivers/mbox/remote/CMakeLists.txt +++ b/samples/drivers/mbox/remote/CMakeLists.txt @@ -16,7 +16,7 @@ if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "mimxrt1160_evk") OR ("${BOARD}" STREQUAL "lpcxpresso55s69") OR ("${BOARD}" STREQUAL "adp_xc7k") OR - ("${BOARD}" STREQUAL "nrf54h20pdk")) + ("${BOARD}" STREQUAL "nrf54h20dk")) message(STATUS "${BOARD} compile as remote in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf b/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.conf similarity index 100% rename from samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf rename to samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.conf diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay b/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.overlay similarity index 100% rename from samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay rename to samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.overlay diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf b/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_vevif.conf similarity index 100% rename from samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf rename to samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_vevif.conf diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay b/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_vevif.overlay similarity index 100% rename from samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay rename to samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_vevif.overlay diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml index de33b04a3a0..be5ba74edf7 100644 --- a/samples/drivers/mbox/sample.yaml +++ b/samples/drivers/mbox/sample.yaml @@ -26,15 +26,15 @@ tests: sample.drivers.mbox.nrf54h20_vevif: platform_allow: - - nrf54h20pdk/nrf54h20/cpuapp + - nrf54h20dk/nrf54h20/cpuapp integration_platforms: - - nrf54h20pdk/nrf54h20/cpuapp + - nrf54h20dk/nrf54h20/cpuapp extra_args: mbox_SNIPPET=nordic-ppr - mbox_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf - mbox_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay - remote_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf - remote_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay + mbox_EXTRA_CONF_FILE=boards/nrf54h20dk_nrf54h20_cpuapp_vevif.conf + mbox_DTC_OVERLAY_FILE=boards/nrf54h20dk_nrf54h20_cpuapp_vevif.overlay + remote_EXTRA_CONF_FILE=boards/nrf54h20dk_nrf54h20_cpuppr_vevif.conf + remote_DTC_OVERLAY_FILE=boards/nrf54h20dk_nrf54h20_cpuppr_vevif.overlay sysbuild: true harness: console harness_config: @@ -45,15 +45,15 @@ tests: sample.drivers.mbox.nrf54h20_bellboard: platform_allow: - - nrf54h20pdk/nrf54h20/cpuapp + - nrf54h20dk/nrf54h20/cpuapp integration_platforms: - - nrf54h20pdk/nrf54h20/cpuapp + - nrf54h20dk/nrf54h20/cpuapp extra_args: mbox_SNIPPET=nordic-ppr - mbox_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf - mbox_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay - remote_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf - remote_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay + mbox_EXTRA_CONF_FILE=boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.conf + mbox_DTC_OVERLAY_FILE=boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.overlay + remote_EXTRA_CONF_FILE=boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.conf + remote_DTC_OVERLAY_FILE=boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.overlay sysbuild: true harness: console harness_config: From 3a6fadf27024bd39bab2b5a43283cc709515dc2a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Wed, 13 Mar 2024 17:24:31 +0100 Subject: [PATCH 0886/2402] snippets: Replace nRF54H20 PDK with nRF54H20 DK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit nRF54H20 PDK is superseded by nRF54H20 DK and will no longer be supported. Signed-off-by: Andrzej Głąbek --- ...4h20_cpuapp.overlay => nrf54h20dk_nrf54h20_cpuapp.overlay} | 4 ++-- snippets/nordic-ppr-ram/nordic-ppr-ram.overlay | 2 +- snippets/nordic-ppr-ram/snippet.yml | 4 ++-- ...4h20_cpuapp.overlay => nrf54h20dk_nrf54h20_cpuapp.overlay} | 0 snippets/nordic-ppr/snippet.yml | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) rename snippets/nordic-ppr-ram/boards/{nrf54h20pdk_nrf54h20_cpuapp.overlay => nrf54h20dk_nrf54h20_cpuapp.overlay} (71%) rename snippets/nordic-ppr/boards/{nrf54h20pdk_nrf54h20_cpuapp.overlay => nrf54h20dk_nrf54h20_cpuapp.overlay} (100%) diff --git a/snippets/nordic-ppr-ram/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay b/snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay similarity index 71% rename from snippets/nordic-ppr-ram/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay rename to snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index 5597c886b85..ea866358fc0 100644 --- a/snippets/nordic-ppr-ram/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay +++ b/snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -3,12 +3,12 @@ * SPDX-License-Identifier: Apache-2.0 */ -&cpuppr_ram3x_region { +&cpuppr_code_data { status = "okay"; }; &cpuppr_vpr { - execution-memory = <&cpuppr_ram3x_region>; + execution-memory = <&cpuppr_code_data>; }; &uart135 { diff --git a/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay b/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay index e69c3a0d2bf..71c45c1b9f4 100644 --- a/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay +++ b/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay @@ -11,5 +11,5 @@ /* code partition size must match RAM size */ &cpuppr_code_partition { - reg = <0x126000 DT_SIZE_K(28)>; + reg = <0x126000 DT_SIZE_K(62)>; }; diff --git a/snippets/nordic-ppr-ram/snippet.yml b/snippets/nordic-ppr-ram/snippet.yml index 2b5b987d3e6..2919e466393 100644 --- a/snippets/nordic-ppr-ram/snippet.yml +++ b/snippets/nordic-ppr-ram/snippet.yml @@ -3,6 +3,6 @@ append: EXTRA_DTC_OVERLAY_FILE: nordic-ppr-ram.overlay boards: - nrf54h20pdk/nrf54h20/cpuapp: + nrf54h20dk/nrf54h20/cpuapp: append: - EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20pdk_nrf54h20_cpuapp.overlay + EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay diff --git a/snippets/nordic-ppr/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay b/snippets/nordic-ppr/boards/nrf54h20dk_nrf54h20_cpuapp.overlay similarity index 100% rename from snippets/nordic-ppr/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay rename to snippets/nordic-ppr/boards/nrf54h20dk_nrf54h20_cpuapp.overlay diff --git a/snippets/nordic-ppr/snippet.yml b/snippets/nordic-ppr/snippet.yml index ce8c3437c4c..8257e6f0a22 100644 --- a/snippets/nordic-ppr/snippet.yml +++ b/snippets/nordic-ppr/snippet.yml @@ -3,6 +3,6 @@ append: EXTRA_DTC_OVERLAY_FILE: nordic-ppr.overlay boards: - nrf54h20pdk/nrf54h20/cpuapp: + nrf54h20dk/nrf54h20/cpuapp: append: - EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20pdk_nrf54h20_cpuapp.overlay + EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay From 787e24576105b4d428deb64792715dbf8ce67b08 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Wed, 13 Mar 2024 17:25:13 +0100 Subject: [PATCH 0887/2402] tests: Replace nRF54H20 PDK with nRF54H20 DK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit nRF54H20 PDK is superseded by nRF54H20 DK and will no longer be supported. Signed-off-by: Andrzej Głąbek --- ...4h20_cpuapp.overlay => nrf54h20dk_nrf54h20_cpuapp.overlay} | 0 tests/lib/cpp/cxx/testcase.yaml | 4 ++-- 2 files changed, 2 insertions(+), 2 deletions(-) rename tests/arch/common/ramfunc/boards/{nrf54h20pdk_nrf54h20_cpuapp.overlay => nrf54h20dk_nrf54h20_cpuapp.overlay} (100%) diff --git a/tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay b/tests/arch/common/ramfunc/boards/nrf54h20dk_nrf54h20_cpuapp.overlay similarity index 100% rename from tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay rename to tests/arch/common/ramfunc/boards/nrf54h20dk_nrf54h20_cpuapp.overlay diff --git a/tests/lib/cpp/cxx/testcase.yaml b/tests/lib/cpp/cxx/testcase.yaml index 5d130869605..9554ccf631b 100644 --- a/tests/lib/cpp/cxx/testcase.yaml +++ b/tests/lib/cpp/cxx/testcase.yaml @@ -37,8 +37,8 @@ tests: # Exclude nRF54L15 and nRF54H20 as Nordic HAL is not compatible with C++98. platform_exclude: - nrf54l15pdk/nrf54l15/cpuapp - - nrf54h20pdk/nrf54h20/cpuapp - - nrf54h20pdk/nrf54h20/cpurad + - nrf54h20dk/nrf54h20/cpuapp + - nrf54h20dk/nrf54h20/cpurad build_only: true extra_configs: - CONFIG_STD_CPP98=y From fbf03a406321b5ab955055db9b5ea0a2db0d02d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Wed, 13 Mar 2024 17:26:33 +0100 Subject: [PATCH 0888/2402] boards: nordic: Remove definition of nRF54H20 PDK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit nRF54H20 PDK is superseded by nRF54H20 DK and will no longer be supported. The board was superseded by nRF54H20 DK. Signed-off-by: Andrzej Głąbek --- boards/deprecated.cmake | 9 - boards/nordic/nrf54h20pdk/Kconfig.defconfig | 10 - boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk | 8 - boards/nordic/nrf54h20pdk/board.cmake | 15 -- boards/nordic/nrf54h20pdk/board.yml | 8 - .../doc/img/nrf54h20pdk_nrf54h20.webp | Bin 27232 -> 0 bytes boards/nordic/nrf54h20pdk/doc/index.rst | 153 --------------- .../nordic/nrf54h20pdk/nrf54h20pdk_defconfig | 9 - .../nrf54h20pdk_nrf54h20-ipc_conf.dtsi | 36 ---- .../nrf54h20pdk_nrf54h20-memory_map.dtsi | 177 ------------------ .../nrf54h20pdk_nrf54h20-pinctrl.dtsi | 53 ------ .../nrf54h20pdk_nrf54h20_cpuapp.dts | 171 ----------------- .../nrf54h20pdk_nrf54h20_cpuapp.yaml | 15 -- .../nrf54h20pdk_nrf54h20_cpuapp_defconfig | 21 --- .../nrf54h20pdk_nrf54h20_cpuppr.dts | 56 ------ .../nrf54h20pdk_nrf54h20_cpuppr.yaml | 13 -- .../nrf54h20pdk_nrf54h20_cpuppr_defconfig | 4 - .../nrf54h20pdk_nrf54h20_cpuppr_ram.yaml | 13 -- .../nrf54h20pdk_nrf54h20_cpuppr_ram_defconfig | 4 - .../nrf54h20pdk_nrf54h20_cpurad.dts | 84 --------- .../nrf54h20pdk_nrf54h20_cpurad.yaml | 15 -- .../nrf54h20pdk_nrf54h20_cpurad_defconfig | 18 -- boards/nordic/nrf54h20pdk/pre_dt_board.cmake | 7 - .../support/nrf54h20_cpurad.JLinkScript | 4 - 24 files changed, 903 deletions(-) delete mode 100644 boards/nordic/nrf54h20pdk/Kconfig.defconfig delete mode 100644 boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk delete mode 100644 boards/nordic/nrf54h20pdk/board.cmake delete mode 100644 boards/nordic/nrf54h20pdk/board.yml delete mode 100644 boards/nordic/nrf54h20pdk/doc/img/nrf54h20pdk_nrf54h20.webp delete mode 100644 boards/nordic/nrf54h20pdk/doc/index.rst delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_defconfig delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-ipc_conf.dtsi delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-pinctrl.dtsi delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.yaml delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp_defconfig delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_defconfig delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram.yaml delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram_defconfig delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.yaml delete mode 100644 boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad_defconfig delete mode 100644 boards/nordic/nrf54h20pdk/pre_dt_board.cmake delete mode 100644 boards/nordic/nrf54h20pdk/support/nrf54h20_cpurad.JLinkScript diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 43334da2a33..4cfd9678c2e 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -455,15 +455,6 @@ set(nrf5340dk_nrf5340_cpuapp_ns_DEPRECATED set(nrf5340dk_nrf5340_cpunet_DEPRECATED nrf5340dk/nrf5340/cpunet ) -set(nrf54h20pdk_nrf54h20_cpuapp_DEPRECATED - nrf54h20pdk/nrf54h20/cpuapp -) -set(nrf54h20pdk_nrf54h20_cpuppr_DEPRECATED - nrf54h20pdk/nrf54h20/cpuppr -) -set(nrf54h20pdk_nrf54h20_cpurad_DEPRECATED - nrf54h20pdk/nrf54h20/cpurad -) set(nrf54l15pdk_nrf54l15_cpuapp_DEPRECATED nrf54l15pdk/nrf54l15/cpuapp ) diff --git a/boards/nordic/nrf54h20pdk/Kconfig.defconfig b/boards/nordic/nrf54h20pdk/Kconfig.defconfig deleted file mode 100644 index 5aa509ba12e..00000000000 --- a/boards/nordic/nrf54h20pdk/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF54H20PDK - -# Data cache is disabled due to a HW issue in the EngA SoC revision. -config DCACHE - default n - -endif # BOARD_NRF54H20PDK diff --git a/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk b/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk deleted file mode 100644 index 616f89b7372..00000000000 --- a/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF54H20PDK - select SOC_NRF54H20_ENGA_CPUAPP if BOARD_NRF54H20PDK_NRF54H20_CPUAPP - select SOC_NRF54H20_ENGA_CPURAD if BOARD_NRF54H20PDK_NRF54H20_CPURAD - select SOC_NRF54H20_ENGA_CPUPPR if BOARD_NRF54H20PDK_NRF54H20_CPUPPR || \ - BOARD_NRF54H20PDK_NRF54H20_CPUPPR_RAM diff --git a/boards/nordic/nrf54h20pdk/board.cmake b/boards/nordic/nrf54h20pdk/board.cmake deleted file mode 100644 index f01b5050f34..00000000000 --- a/boards/nordic/nrf54h20pdk/board.cmake +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) - -if(CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPURAD) - if(CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPURAD) - set( - JLINK_TOOL_OPT - "-jlinkscriptfile ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpurad.JLinkScript" - ) - endif() - - board_runner_args(jlink "--device=CORTEX-M33" "--speed=4000" "--tool-opt=${JLINK_TOOL_OPT}") - include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -endif() diff --git a/boards/nordic/nrf54h20pdk/board.yml b/boards/nordic/nrf54h20pdk/board.yml deleted file mode 100644 index 633912b4127..00000000000 --- a/boards/nordic/nrf54h20pdk/board.yml +++ /dev/null @@ -1,8 +0,0 @@ -board: - name: nrf54h20pdk - vendor: nordic - socs: - - name: nrf54h20 - variants: - - name: ram - cpucluster: cpuppr diff --git a/boards/nordic/nrf54h20pdk/doc/img/nrf54h20pdk_nrf54h20.webp b/boards/nordic/nrf54h20pdk/doc/img/nrf54h20pdk_nrf54h20.webp deleted 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"zephyr,ipc-icmsg"; - status = "disabled"; - mboxes = <&cpuapp_bellboard 13>, - <&cpuppr_vevif 12>; - }; - }; -}; diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi deleted file mode 100644 index 560700b1756..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - reserved-memory { - cpuapp_ram0x_region: memory@2f000000 { - compatible = "nordic,owned-memory"; - reg = <0x2f000000 DT_SIZE_K(260)>; - status = "disabled"; - perm-read; - perm-write; - perm-secure; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f000000 0x41000>; - - cpusec_cpuapp_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; - - cpuapp_cpusec_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; - - cpuapp_data: memory@1000 { - reg = <0x1000 DT_SIZE_K(256)>; - }; - }; - - cpurad_ram0x_region: memory@2f041000 { - compatible = "nordic,owned-memory"; - reg = <0x2f041000 DT_SIZE_K(4)>; - status = "disabled"; - perm-read; - perm-write; - perm-secure; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f041000 0x1000>; - - cpusec_cpurad_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; - - cpurad_cpusec_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; - }; - - cpuapp_cpurad_ram0x_region: memory@2f0bf000 { - compatible = "nordic,owned-memory"; - reg = <0x2f0bf000 DT_SIZE_K(4)>; - status = "disabled"; - perm-read; - perm-write; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f0bf000 0x1000>; - - cpuapp_cpurad_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; - - cpurad_cpuapp_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; - }; - - shared_ram20_region: memory@2f88f000 { - compatible = "nordic,owned-memory"; - reg = <0x2f88f000 DT_SIZE_K(4)>; - status = "disabled"; - perm-read; - perm-write; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f88f000 0x1000>; - - cpuapp_cpusys_ipc_shm: memory@ce0 { - reg = <0xce0 0x80>; - }; - - cpusys_cpuapp_ipc_shm: memory@d60 { - reg = <0xd60 0x80>; - }; - - cpurad_cpusys_ipc_shm: memory@e00 { - reg = <0xe00 0x80>; - }; - - cpusys_cpurad_ipc_shm: memory@e80 { - reg = <0xe80 0x80>; - }; - }; - - cpuppr_ram3x_region: memory@2fc00000 { - compatible = "nordic,owned-memory"; - reg = <0x2fc00000 DT_SIZE_K(28)>; - status = "disabled"; - perm-read; - perm-write; - perm-execute; - }; - - shared_ram3x_region: memory@2fc07000 { - compatible = "nordic,owned-memory"; - reg = <0x2fc07000 DT_SIZE_K(4)>; - status = "disabled"; - perm-read; - perm-write; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2fc07000 0x1000>; - - cpuapp_cpuppr_ipc_shm: memory@0 { - reg = <0x0 0x340>; - }; - - cpuppr_cpuapp_ipc_shm: memory@340 { - reg = <0x340 0x340>; - }; - - cpuapp_dma_region: memory@680 { - compatible = "zephyr,memory-region"; - reg = <0x680 DT_SIZE_K(2)>; - status = "disabled"; - #memory-region-cells = <0>; - zephyr,memory-region = "DMA_RAM3x_APP"; - }; - - cpurad_dma_region: memory@e80 { - compatible = "zephyr,memory-region"; - reg = <0xe80 0x80>; - status = "disabled"; - #memory-region-cells = <0>; - zephyr,memory-region = "DMA_RAM3x_RAD"; - }; - }; - }; -}; - -&mram1x { - cpurad_rx_partitions: cpurad-rx-partitions { - compatible = "nordic,owned-partitions", "fixed-partitions"; - status = "disabled"; - perm-read; - perm-execute; - perm-secure; - #address-cells = <1>; - #size-cells = <1>; - - cpurad_slot0_partition: partition@66000 { - reg = <0x66000 DT_SIZE_K(256)>; - }; - }; - - cpuapp_rx_partitions: cpuapp-rx-partitions { - compatible = "nordic,owned-partitions", "fixed-partitions"; - status = "disabled"; - perm-read; - perm-execute; - perm-secure; - #address-cells = <1>; - #size-cells = <1>; - - cpuapp_slot0_partition: partition@a6000 { - reg = <0xa6000 DT_SIZE_K(512)>; - }; - - cpuppr_code_partition: partition@126000 { - reg = <0x126000 DT_SIZE_K(64)>; - }; - }; -}; diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-pinctrl.dtsi b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-pinctrl.dtsi deleted file mode 100644 index d3b79120322..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-pinctrl.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - /omit-if-no-ref/ uart135_default: uart135_default { - group1 { - psels = , - ; - }; - - group2 { - bias-pull-up; - psels = , - ; - }; - }; - - /omit-if-no-ref/ uart135_sleep: uart135_sleep { - group1 { - low-power-enable; - psels = , - , - , - ; - }; - }; - - /omit-if-no-ref/ uart136_default: uart136_default { - group1 { - psels = , - ; - }; - - group2 { - bias-pull-up; - psels = , - ; - }; - }; - - /omit-if-no-ref/ uart136_sleep: uart136_sleep { - group1 { - low-power-enable; - psels = , - , - , - ; - }; - }; -}; diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts deleted file mode 100644 index b2db9e4b9b1..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "nrf54h20pdk_nrf54h20-memory_map.dtsi" -#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" -#include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" - -/delete-node/ &cpusec_cpurad_ipc; - -/ { - compatible = "nordic,nrf54h20pdk_nrf54h20-cpuapp"; - model = "Nordic nRF54H20 PDK nRF54H20 Application MCU"; - - chosen { - zephyr,console = &uart136; - zephyr,code-partition = &cpuapp_slot0_partition; - zephyr,flash = &mram1x; - zephyr,sram = &cpuapp_data; - }; - - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - led3 = &led3; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - sw3 = &button3; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 0"; - zephyr,code = ; - }; - - button1: button_1 { - gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 1"; - zephyr,code = ; - }; - - button2: button_2 { - gpios = <&gpio0 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 2"; - zephyr,code = ; - }; - - button3: button_3 { - gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 3"; - zephyr,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0: led_0 { - gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; - label = "Green LED 0"; - }; - - led1: led_1 { - gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; - label = "Green LED 1"; - }; - - led2: led_2 { - gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; - label = "Green LED 2"; - }; - - led3: led_3 { - gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; - label = "Green LED 3"; - }; - }; -}; - -&cpuapp_ram0x_region { - status = "okay"; -}; - -&shared_ram3x_region { - status = "okay"; -}; - -&cpuapp_bellboard { - interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; - interrupt-names = "irq0"; - /* irq0: 0: cpuapp-cpusec, 13: cpuapp-cpuppr, 18: cpuapp-cpurad */ - nordic,interrupt-mapping = <0x00042001 0>; -}; - -&cpusec_cpuapp_ipc { - mbox-names = "tx", "rx"; - tx-region = <&cpuapp_cpusec_ipc_shm>; - rx-region = <&cpusec_cpuapp_ipc_shm>; -}; - -&cpuapp_cpurad_ipc { - compatible = "zephyr,ipc-icmsg-me-initiator"; - mbox-names = "rx", "tx"; - tx-region = <&cpuapp_cpurad_ipc_shm>; - rx-region = <&cpurad_cpuapp_ipc_shm>; -}; - -&cpuapp_cpuppr_ipc { - mbox-names = "rx", "tx"; - tx-region = <&cpuapp_cpuppr_ipc_shm>; - rx-region = <&cpuppr_cpuapp_ipc_shm>; -}; - -&cpuapp_dma_region { - status = "okay"; -}; - -&cpuapp_rx_partitions { - status = "okay"; -}; - -&cpuppr_vpr { - execution-memory = <&cpuppr_code_partition>; -}; - -&gpiote130 { - status = "okay"; - owned-channels = <0 1 2 3 4 5 6 7>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio9 { - status = "okay"; -}; - -&grtc { - status = "okay"; - child-owned-channels = <5 6>; - nonsecure-channels = <5 6>; - owned-channels = <4 5 6>; -}; - -&uart135 { - current-speed = <115200>; - pinctrl-0 = <&uart135_default>; - pinctrl-1 = <&uart135_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart136 { - status = "okay"; - memory-regions = <&cpuapp_dma_region>; - current-speed = <115200>; - pinctrl-0 = <&uart136_default>; - pinctrl-1 = <&uart136_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.yaml deleted file mode 100644 index 3c2b266c530..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54h20pdk/nrf54h20/cpuapp -name: nRF54H20-PDK-nRF54H20-Application -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 32 -flash: 368 -supported: - - gpio diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp_defconfig deleted file mode 100644 index b014eb7b031..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_USE_DT_CODE_PARTITION=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# MPU-based null-pointer dereferencing detection cannot be applied -# as the (0x0 - 0x400) region is unmapped for this target. -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y - -# Enable cache -CONFIG_CACHE_MANAGEMENT=y -CONFIG_EXTERNAL_CACHE=y - -# Enable GPIO -CONFIG_GPIO=y diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts deleted file mode 100644 index f98abb9e44b..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "nrf54h20pdk_nrf54h20-memory_map.dtsi" -#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" -#include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" - -/delete-node/ &cpuapp_cpurad_ipc; -/delete-node/ &cpusec_cpuapp_ipc; -/delete-node/ &cpusec_cpurad_ipc; - -/ { - compatible = "nordic,nrf54h20pdk_nrf54h20-cpuppr"; - model = "Nordic nRF54H20 PDK nRF54H20 Peripheral Processor MCU"; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - zephyr,console = &uart135; - zephyr,code-partition = &cpuppr_code_partition; - zephyr,flash = &mram1x; - zephyr,sram = &cpuppr_ram3x_region; - }; -}; - -&cpuapp_cpuppr_ipc { - mbox-names = "tx", "rx"; - tx-region = <&cpuppr_cpuapp_ipc_shm>; - rx-region = <&cpuapp_cpuppr_ipc_shm>; -}; - -&grtc { - status = "okay"; - owned-channels = <5>; -}; - -&uart135 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart135_default>; - pinctrl-1 = <&uart135_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart136 { - current-speed = <115200>; - pinctrl-0 = <&uart136_default>; - pinctrl-1 = <&uart136_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml deleted file mode 100644 index b19d68e750d..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54h20pdk/nrf54h20/cpuppr -name: nRF54H20-PDK-nRF54H20-PPR -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 28 -flash: 64 -supported: - - gpio diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_defconfig deleted file mode 100644 index 0e657c5081e..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram.yaml deleted file mode 100644 index 596392b5373..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54h20pdk/nrf54h20/cpuppr/ram -name: nRF54H20-PDK-nRF54H20-PPR-RAM -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 28 -flash: 28 -supported: - - gpio diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram_defconfig deleted file mode 100644 index bc8ce62afbb..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_ram_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_XIP=n diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts deleted file mode 100644 index 8d2629df62e..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "nrf54h20pdk_nrf54h20-memory_map.dtsi" -#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" -#include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" - -/delete-node/ &cpuapp_cpuppr_ipc; -/delete-node/ &cpusec_cpuapp_ipc; - -/ { - compatible = "nordic,nrf54h20pdk_nrf54h20-cpurad"; - model = "Nordic nRF54H20 PDK nRF54H20 Radio MCU"; - - chosen { - zephyr,console = &uart135; - zephyr,code-partition = &cpurad_slot0_partition; - zephyr,flash = &mram1x; - zephyr,sram = &cpurad_ram0; - }; -}; - -&shared_ram3x_region { - status = "okay"; -}; - -&cpurad_bellboard { - interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; - interrupt-names = "irq0"; - /* irq0: 0: cpurad-cpusec, 12: cpurad-cpuapp */ - nordic,interrupt-mapping = <0x00001001 0>; -}; - -&cpusec_cpurad_ipc { - mbox-names = "tx", "rx"; - tx-region = <&cpurad_cpusec_ipc_shm>; - rx-region = <&cpusec_cpurad_ipc_shm>; -}; - -&cpuapp_cpurad_ipc { - compatible = "zephyr,ipc-icmsg-me-follower"; - mbox-names = "tx", "rx"; - tx-region = <&cpurad_cpuapp_ipc_shm>; - rx-region = <&cpuapp_cpurad_ipc_shm>; -}; - -&cpurad_dma_region { - status = "okay"; -}; - -&cpurad_rx_partitions { - status = "okay"; -}; - -&grtc { - status = "okay"; - child-owned-channels = <8 9 10 11 12>; - interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>, - <108 NRF_DEFAULT_IRQ_PRIORITY>; - nonsecure-channels = <8 9 10 11 12>; - owned-channels = <7 8 9 10 11 12 13 14>; -}; - -&uart135 { - status = "okay"; - memory-regions = <&cpurad_dma_region>; - current-speed = <115200>; - pinctrl-0 = <&uart135_default>; - pinctrl-1 = <&uart135_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart136 { - current-speed = <115200>; - pinctrl-0 = <&uart136_default>; - pinctrl-1 = <&uart136_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.yaml deleted file mode 100644 index 138adf12001..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54h20pdk/nrf54h20/cpurad -name: nRF54H20-PDK-nRF54H20-Radio -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 32 -flash: 368 -supported: - - gpio diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad_defconfig deleted file mode 100644 index 1a62a205502..00000000000 --- a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_USE_DT_CODE_PARTITION=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# MPU-based null-pointer dereferencing detection cannot be applied -# as the (0x0 - 0x400) region is unmapped for this target. -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y - -# Enable cache -CONFIG_CACHE_MANAGEMENT=y -CONFIG_EXTERNAL_CACHE=y diff --git a/boards/nordic/nrf54h20pdk/pre_dt_board.cmake b/boards/nordic/nrf54h20pdk/pre_dt_board.cmake deleted file mode 100644 index 5e0fecebdc8..00000000000 --- a/boards/nordic/nrf54h20pdk/pre_dt_board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Allow common DTS files to be included from the other board directory. -# To be removed after HWMv2 (#51831), once both directories can be merged into one. -string(REGEX REPLACE "/riscv/(.*$)" "/arm/\\1" BOARD_DIR_ARM "${BOARD_DIR}") -list(APPEND DTS_EXTRA_CPPFLAGS -isystem "${BOARD_DIR_ARM}") diff --git a/boards/nordic/nrf54h20pdk/support/nrf54h20_cpurad.JLinkScript b/boards/nordic/nrf54h20pdk/support/nrf54h20_cpurad.JLinkScript deleted file mode 100644 index 2fb7e32302e..00000000000 --- a/boards/nordic/nrf54h20pdk/support/nrf54h20_cpurad.JLinkScript +++ /dev/null @@ -1,4 +0,0 @@ -void ConfigTargetSettings(void) { - JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP"); - CORESIGHT_IndexAHBAPToUse = 1; -} From cec6ab0dcd5f5a823fb30239a656f614cac60dd2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Wed, 13 Mar 2024 17:29:33 +0100 Subject: [PATCH 0889/2402] modules: hal_nordic: Remove support for nRF54H20 EngA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was a preview revision of the SoC that will no longer be supported. Signed-off-by: Andrzej Głąbek --- modules/hal_nordic/nrfx/CMakeLists.txt | 10 - modules/hal_nordic/nrfx/nrfx_config.h | 6 - .../nrfx_config_nrf54h20_enga_application.h | 1962 ---------------- .../nrfx/nrfx_config_nrf54h20_enga_ppr.h | 1882 --------------- .../nrfx_config_nrf54h20_enga_radiocore.h | 2043 ----------------- 5 files changed, 5903 deletions(-) delete mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h delete mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h delete mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index 84cb67093d7..e3850ab9346 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -47,13 +47,6 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_ENGA_CPUAPP NRF_APPLICATION zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9120 NRF9120_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9160 NRF9160_XXAA) -zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUAPP NRF54H20_ENGA_XXAA - NRF_APPLICATION) -zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPURAD NRF54H20_ENGA_XXAA - NRF_RADIOCORE) -zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUPPR NRF54H20_ENGA_XXAA - NRF_PPR) - zephyr_compile_definitions_ifdef(CONFIG_NRF_APPROTECT_LOCK ENABLE_APPROTECT) zephyr_compile_definitions_ifdef(CONFIG_NRF_APPROTECT_USER_HANDLING @@ -197,8 +190,5 @@ mdk_svd_ifdef(CONFIG_SOC_NRF5340_CPUNET nrf5340_network.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUAPP nrf54h20_application.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUPPR nrf54h20_ppr.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPURAD nrf54h20_radiocore.svd) -mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUAPP nrf54h20_enga_application.svd) -mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUPPR nrf54h20_enga_ppr.svd) -mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPURAD nrf54h20_enga_radiocore.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9120 nrf9120.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9160 nrf9160.svd) diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index 693c6993029..89c07938293 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -947,12 +947,6 @@ #include #elif defined(NRF54H20_XXAA) && defined(NRF_PPR) #include -#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_APPLICATION) - #include -#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_RADIOCORE) - #include -#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_PPR) - #include #elif (defined(NRF54L15_XXAA) || defined(NRF54L15_ENGA_XXAA)) && defined(NRF_APPLICATION) #include #elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h deleted file mode 100644 index af74d9d3dc3..00000000000 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h +++ /dev/null @@ -1,1962 +0,0 @@ -/* - * Copyright (c) 2024, Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef NRFX_CONFIG_NRF54H20_ENGA_APPLICATION_H__ -#define NRFX_CONFIG_NRF54H20_ENGA_APPLICATION_H__ - -#ifndef NRFX_CONFIG_H__ -#error "This file should not be included directly. Include nrfx_config.h instead." -#endif - - -/** - * @brief NRFX_DEFAULT_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_DEFAULT_IRQ_PRIORITY -#define NRFX_DEFAULT_IRQ_PRIORITY 7 -#endif - -/** - * @brief NRFX_BELLBOARD_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD_ENABLED -#define NRFX_BELLBOARD_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_BELLBOARD0_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD0_ENABLED -#define NRFX_BELLBOARD0_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD1_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD1_ENABLED -#define NRFX_BELLBOARD1_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD2_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD2_ENABLED -#define NRFX_BELLBOARD2_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD3_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD3_ENABLED -#define NRFX_BELLBOARD3_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_ENABLED -#define NRFX_COMP_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_CONFIG_LOG_ENABLED -#define NRFX_COMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_COMP_CONFIG_LOG_LEVEL -#define NRFX_COMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_ENABLED -#define NRFX_DPPI_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED -#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL -#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0 -#endif - -/** - * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e -#endif - -/** - * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 -#endif - -/** - * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 -#endif - -/** - * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 -#endif - -/** - * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f -#endif - -/** - * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 -#endif - -/** - * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df -#endif - -/** - * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf -#endif - -/** - * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e -#endif - -/** - * @brief NRFX_GPIOTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - * - * Integer value. Minimum: 0. Maximum: 15. - */ -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS -#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED -#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL -#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_GPIOTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE130_ENABLED -#define NRFX_GPIOTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_ENABLED -#define NRFX_GRTC_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED -#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOEN - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOEN -#define NRFX_GRTC_CONFIG_AUTOEN 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOSTART - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOSTART -#define NRFX_GRTC_CONFIG_AUTOSTART 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS - * - * Integer value. - */ -#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS -#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK - */ -#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK -#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000f0 -#endif - -/** - * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED -#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL -#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_I2S_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S_ENABLED -#define NRFX_I2S_ENABLED 0 -#endif - -/** - * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_I2S_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S_CONFIG_LOG_ENABLED -#define NRFX_I2S_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_I2S_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_I2S_CONFIG_LOG_LEVEL -#define NRFX_I2S_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_I2S130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S130_ENABLED -#define NRFX_I2S130_ENABLED 0 -#endif - -/** - * @brief NRFX_I2S131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S131_ENABLED -#define NRFX_I2S131_ENABLED 0 -#endif - -/** - * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_LPCOMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_ENABLED -#define NRFX_LPCOMP_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED -#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL -#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_MVDMA_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_MVDMA_ENABLED -#define NRFX_MVDMA_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_ENABLED -#define NRFX_NFCT_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver. - * - * Integer value. Minimum: 0. Maximum: 5. - */ -#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID -#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED -#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL -#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PDM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_ENABLED -#define NRFX_PDM_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_CONFIG_LOG_ENABLED -#define NRFX_PDM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PDM_CONFIG_LOG_LEVEL -#define NRFX_PDM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_ENABLED -#define NRFX_PRS_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_CONFIG_LOG_ENABLED -#define NRFX_PRS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PRS_CONFIG_LOG_LEVEL -#define NRFX_PRS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_BOX_0_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_0_ENABLED -#define NRFX_PRS_BOX_0_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_1_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_1_ENABLED -#define NRFX_PRS_BOX_1_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_2_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_2_ENABLED -#define NRFX_PRS_BOX_2_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_3_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_3_ENABLED -#define NRFX_PRS_BOX_3_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_4_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_4_ENABLED -#define NRFX_PRS_BOX_4_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_5_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_5_ENABLED -#define NRFX_PRS_BOX_5_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_6_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_6_ENABLED -#define NRFX_PRS_BOX_6_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_7_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_7_ENABLED -#define NRFX_PRS_BOX_7_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_8_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_8_ENABLED -#define NRFX_PRS_BOX_8_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_9_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_9_ENABLED -#define NRFX_PRS_BOX_9_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_ENABLED -#define NRFX_PWM_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_CONFIG_LOG_ENABLED -#define NRFX_PWM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PWM_CONFIG_LOG_LEVEL -#define NRFX_PWM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PWM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM120_ENABLED -#define NRFX_PWM120_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM130_ENABLED -#define NRFX_PWM130_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM131_ENABLED -#define NRFX_PWM131_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM132_ENABLED -#define NRFX_PWM132_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM133_ENABLED -#define NRFX_PWM133_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_ENABLED -#define NRFX_QDEC_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED -#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL -#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_QDEC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC130_ENABLED -#define NRFX_QDEC130_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC131_ENABLED -#define NRFX_QDEC131_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_CONFIG_LOG_ENABLED -#define NRFX_RTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_RTC_CONFIG_LOG_LEVEL -#define NRFX_RTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_RTC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC130_ENABLED -#define NRFX_RTC130_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC131_ENABLED -#define NRFX_RTC131_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_ENABLED -#define NRFX_SAADC_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED -#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL -#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED -#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL -#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM120_ENABLED -#define NRFX_SPIM120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM121_ENABLED -#define NRFX_SPIM121_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM130_ENABLED -#define NRFX_SPIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM131_ENABLED -#define NRFX_SPIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM132_ENABLED -#define NRFX_SPIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM133_ENABLED -#define NRFX_SPIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM134_ENABLED -#define NRFX_SPIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM135_ENABLED -#define NRFX_SPIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM136_ENABLED -#define NRFX_SPIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM137_ENABLED -#define NRFX_SPIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED -#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL -#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIS120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS120_ENABLED -#define NRFX_SPIS120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS130_ENABLED -#define NRFX_SPIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS131_ENABLED -#define NRFX_SPIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS132_ENABLED -#define NRFX_SPIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS133_ENABLED -#define NRFX_SPIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS134_ENABLED -#define NRFX_SPIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS135_ENABLED -#define NRFX_SPIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS136_ENABLED -#define NRFX_SPIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS137_ENABLED -#define NRFX_SPIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_SYSTICK_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SYSTICK_ENABLED -#define NRFX_SYSTICK_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_ENABLED -#define NRFX_TEMP_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED -#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL -#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED -#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL -#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER120_ENABLED -#define NRFX_TIMER120_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER121_ENABLED -#define NRFX_TIMER121_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER130_ENABLED -#define NRFX_TIMER130_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER131_ENABLED -#define NRFX_TIMER131_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER132_ENABLED -#define NRFX_TIMER132_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER133_ENABLED -#define NRFX_TIMER133_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER134_ENABLED -#define NRFX_TIMER134_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER135_ENABLED -#define NRFX_TIMER135_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER136_ENABLED -#define NRFX_TIMER136_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER137_ENABLED -#define NRFX_TIMER137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED -#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL -#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM130_ENABLED -#define NRFX_TWIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM131_ENABLED -#define NRFX_TWIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM132_ENABLED -#define NRFX_TWIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM133_ENABLED -#define NRFX_TWIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM134_ENABLED -#define NRFX_TWIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM135_ENABLED -#define NRFX_TWIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM136_ENABLED -#define NRFX_TWIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM137_ENABLED -#define NRFX_TWIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ENABLED -#define NRFX_TWIS_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED -#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance - * would be initialized only once. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -/** - * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_NO_SYNC_MODE -#define NRFX_TWIS_NO_SYNC_MODE 0 -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL -#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS130_ENABLED -#define NRFX_TWIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS131_ENABLED -#define NRFX_TWIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS132_ENABLED -#define NRFX_TWIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS133_ENABLED -#define NRFX_TWIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS134_ENABLED -#define NRFX_TWIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS135_ENABLED -#define NRFX_TWIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS136_ENABLED -#define NRFX_TWIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS137_ENABLED -#define NRFX_TWIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for - * configuring GPIO pins is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for - * configuring PSEL registers is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking - * of TX transfers. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_TX_LINK -#define NRFX_UARTE_CONFIG_TX_LINK 1 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED -#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 -#endif - -/** - * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED -#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL -#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_UARTE120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE120_ENABLED -#define NRFX_UARTE120_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE130_ENABLED -#define NRFX_UARTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE131_ENABLED -#define NRFX_UARTE131_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE132_ENABLED -#define NRFX_UARTE132_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE133_ENABLED -#define NRFX_UARTE133_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE134_ENABLED -#define NRFX_UARTE134_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE135_ENABLED -#define NRFX_UARTE135_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE136_ENABLED -#define NRFX_UARTE136_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE137_ENABLED -#define NRFX_UARTE137_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_NO_IRQ -#define NRFX_WDT_CONFIG_NO_IRQ 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_LOG_ENABLED -#define NRFX_WDT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_WDT_CONFIG_LOG_LEVEL -#define NRFX_WDT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_WDT010_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT010_ENABLED -#define NRFX_WDT010_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT011_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT011_ENABLED -#define NRFX_WDT011_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT131_ENABLED -#define NRFX_WDT131_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT132_ENABLED -#define NRFX_WDT132_ENABLED 0 -#endif - -#endif /* NRFX_CONFIG_NRF54H20_ENGA_APPLICATION_H__ */ diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h deleted file mode 100644 index 65b3e2fa958..00000000000 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h +++ /dev/null @@ -1,1882 +0,0 @@ -/* - * Copyright (c) 2024, Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef NRFX_CONFIG_NRF54H20_ENGA_PPR_H__ -#define NRFX_CONFIG_NRF54H20_ENGA_PPR_H__ - -#ifndef NRFX_CONFIG_H__ -#error "This file should not be included directly. Include nrfx_config.h instead." -#endif - - -/** - * @brief NRFX_DEFAULT_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_DEFAULT_IRQ_PRIORITY -#define NRFX_DEFAULT_IRQ_PRIORITY 0 -#endif - -/** - * @brief NRFX_COMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_ENABLED -#define NRFX_COMP_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_CONFIG_LOG_ENABLED -#define NRFX_COMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_COMP_CONFIG_LOG_LEVEL -#define NRFX_COMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_ENABLED -#define NRFX_DPPI_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED -#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL -#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030 -#endif - -/** - * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e -#endif - -/** - * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 -#endif - -/** - * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 -#endif - -/** - * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 -#endif - -/** - * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 -#endif - -/** - * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df -#endif - -/** - * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf -#endif - -/** - * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e -#endif - -/** - * @brief NRFX_GPIOTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - * - * Integer value. Minimum: 0. Maximum: 15. - */ -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS -#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED -#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL -#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_GPIOTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE130_ENABLED -#define NRFX_GPIOTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_ENABLED -#define NRFX_GRTC_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED -#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOEN - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOEN -#define NRFX_GRTC_CONFIG_AUTOEN 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOSTART - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOSTART -#define NRFX_GRTC_CONFIG_AUTOSTART 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS - * - * Integer value. - */ -#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS -#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 2 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK - */ -#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK -#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000c0 -#endif - -/** - * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED -#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL -#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_I2S_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S_ENABLED -#define NRFX_I2S_ENABLED 0 -#endif - -/** - * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_I2S_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S_CONFIG_LOG_ENABLED -#define NRFX_I2S_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_I2S_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_I2S_CONFIG_LOG_LEVEL -#define NRFX_I2S_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_I2S130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S130_ENABLED -#define NRFX_I2S130_ENABLED 0 -#endif - -/** - * @brief NRFX_I2S131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S131_ENABLED -#define NRFX_I2S131_ENABLED 0 -#endif - -/** - * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_LPCOMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_ENABLED -#define NRFX_LPCOMP_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED -#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL -#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_NFCT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_ENABLED -#define NRFX_NFCT_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for - * workarounds in the driver. - * - * Integer value. Minimum: 0. Maximum: 5. - */ -#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID -#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED -#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL -#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PDM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_ENABLED -#define NRFX_PDM_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_CONFIG_LOG_ENABLED -#define NRFX_PDM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PDM_CONFIG_LOG_LEVEL -#define NRFX_PDM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_ENABLED -#define NRFX_PRS_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_CONFIG_LOG_ENABLED -#define NRFX_PRS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PRS_CONFIG_LOG_LEVEL -#define NRFX_PRS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_BOX_0_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_0_ENABLED -#define NRFX_PRS_BOX_0_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_1_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_1_ENABLED -#define NRFX_PRS_BOX_1_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_2_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_2_ENABLED -#define NRFX_PRS_BOX_2_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_3_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_3_ENABLED -#define NRFX_PRS_BOX_3_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_4_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_4_ENABLED -#define NRFX_PRS_BOX_4_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_5_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_5_ENABLED -#define NRFX_PRS_BOX_5_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_6_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_6_ENABLED -#define NRFX_PRS_BOX_6_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_7_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_7_ENABLED -#define NRFX_PRS_BOX_7_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_8_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_8_ENABLED -#define NRFX_PRS_BOX_8_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_9_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_9_ENABLED -#define NRFX_PRS_BOX_9_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_ENABLED -#define NRFX_PWM_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_CONFIG_LOG_ENABLED -#define NRFX_PWM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PWM_CONFIG_LOG_LEVEL -#define NRFX_PWM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PWM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM120_ENABLED -#define NRFX_PWM120_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM130_ENABLED -#define NRFX_PWM130_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM131_ENABLED -#define NRFX_PWM131_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM132_ENABLED -#define NRFX_PWM132_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM133_ENABLED -#define NRFX_PWM133_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_ENABLED -#define NRFX_QDEC_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED -#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL -#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_QDEC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC130_ENABLED -#define NRFX_QDEC130_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC131_ENABLED -#define NRFX_QDEC131_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_CONFIG_LOG_ENABLED -#define NRFX_RTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_RTC_CONFIG_LOG_LEVEL -#define NRFX_RTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_RTC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC130_ENABLED -#define NRFX_RTC130_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC131_ENABLED -#define NRFX_RTC131_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_ENABLED -#define NRFX_SAADC_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED -#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL -#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED -#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL -#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM120_ENABLED -#define NRFX_SPIM120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM121_ENABLED -#define NRFX_SPIM121_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM130_ENABLED -#define NRFX_SPIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM131_ENABLED -#define NRFX_SPIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM132_ENABLED -#define NRFX_SPIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM133_ENABLED -#define NRFX_SPIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM134_ENABLED -#define NRFX_SPIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM135_ENABLED -#define NRFX_SPIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM136_ENABLED -#define NRFX_SPIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM137_ENABLED -#define NRFX_SPIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED -#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL -#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIS120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS120_ENABLED -#define NRFX_SPIS120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS130_ENABLED -#define NRFX_SPIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS131_ENABLED -#define NRFX_SPIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS132_ENABLED -#define NRFX_SPIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS133_ENABLED -#define NRFX_SPIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS134_ENABLED -#define NRFX_SPIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS135_ENABLED -#define NRFX_SPIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS136_ENABLED -#define NRFX_SPIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS137_ENABLED -#define NRFX_SPIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_ENABLED -#define NRFX_TEMP_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED -#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL -#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED -#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL -#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER120_ENABLED -#define NRFX_TIMER120_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER121_ENABLED -#define NRFX_TIMER121_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER130_ENABLED -#define NRFX_TIMER130_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER131_ENABLED -#define NRFX_TIMER131_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER132_ENABLED -#define NRFX_TIMER132_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER133_ENABLED -#define NRFX_TIMER133_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER134_ENABLED -#define NRFX_TIMER134_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER135_ENABLED -#define NRFX_TIMER135_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER136_ENABLED -#define NRFX_TIMER136_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER137_ENABLED -#define NRFX_TIMER137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED -#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL -#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM130_ENABLED -#define NRFX_TWIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM131_ENABLED -#define NRFX_TWIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM132_ENABLED -#define NRFX_TWIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM133_ENABLED -#define NRFX_TWIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM134_ENABLED -#define NRFX_TWIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM135_ENABLED -#define NRFX_TWIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM136_ENABLED -#define NRFX_TWIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM137_ENABLED -#define NRFX_TWIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ENABLED -#define NRFX_TWIS_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED -#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance - * would be initialized only once. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -/** - * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_NO_SYNC_MODE -#define NRFX_TWIS_NO_SYNC_MODE 0 -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL -#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS130_ENABLED -#define NRFX_TWIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS131_ENABLED -#define NRFX_TWIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS132_ENABLED -#define NRFX_TWIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS133_ENABLED -#define NRFX_TWIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS134_ENABLED -#define NRFX_TWIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS135_ENABLED -#define NRFX_TWIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS136_ENABLED -#define NRFX_TWIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS137_ENABLED -#define NRFX_TWIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for - * configuring GPIO pins is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for - * configuring PSEL registers is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking of TX - * transfers. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_TX_LINK -#define NRFX_UARTE_CONFIG_TX_LINK 1 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED -#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 -#endif - -/** - * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED -#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL -#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_UARTE120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE120_ENABLED -#define NRFX_UARTE120_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE130_ENABLED -#define NRFX_UARTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE131_ENABLED -#define NRFX_UARTE131_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE132_ENABLED -#define NRFX_UARTE132_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE133_ENABLED -#define NRFX_UARTE133_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE134_ENABLED -#define NRFX_UARTE134_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE135_ENABLED -#define NRFX_UARTE135_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE136_ENABLED -#define NRFX_UARTE136_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE137_ENABLED -#define NRFX_UARTE137_ENABLED 0 -#endif - -/** - * @brief NRFX_VEVIF_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_VEVIF_ENABLED -#define NRFX_VEVIF_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_NO_IRQ -#define NRFX_WDT_CONFIG_NO_IRQ 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_LOG_ENABLED -#define NRFX_WDT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_WDT_CONFIG_LOG_LEVEL -#define NRFX_WDT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_WDT131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT131_ENABLED -#define NRFX_WDT131_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT132_ENABLED -#define NRFX_WDT132_ENABLED 0 -#endif - -#endif /* NRFX_CONFIG_NRF54H20_ENGA_PPR_H__ */ diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h deleted file mode 100644 index ca7bf3aca63..00000000000 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h +++ /dev/null @@ -1,2043 +0,0 @@ -/* - * Copyright (c) 2024, Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef NRFX_CONFIG_NRF54H20_ENGA_RADIOCORE_H__ -#define NRFX_CONFIG_NRF54H20_ENGA_RADIOCORE_H__ - -#ifndef NRFX_CONFIG_H__ -#error "This file should not be included directly. Include nrfx_config.h instead." -#endif - -/** - * @brief NRFX_DEFAULT_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_DEFAULT_IRQ_PRIORITY -#define NRFX_DEFAULT_IRQ_PRIORITY 7 -#endif - -/** - * @brief NRFX_BELLBOARD_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD_ENABLED -#define NRFX_BELLBOARD_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_BELLBOARD0_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD0_ENABLED -#define NRFX_BELLBOARD0_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD1_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD1_ENABLED -#define NRFX_BELLBOARD1_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD2_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD2_ENABLED -#define NRFX_BELLBOARD2_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD3_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD3_ENABLED -#define NRFX_BELLBOARD3_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_ENABLED -#define NRFX_COMP_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_CONFIG_LOG_ENABLED -#define NRFX_COMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_COMP_CONFIG_LOG_LEVEL -#define NRFX_COMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_ENABLED -#define NRFX_DPPI_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED -#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL -#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0 -#endif - -/** - * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e -#endif - -/** - * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 -#endif - -/** - * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 -#endif - -/** - * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 -#endif - -/** - * @brief NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f -#endif - -/** - * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 -#endif - -/** - * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df -#endif - -/** - * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf -#endif - -/** - * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e -#endif - -/** - * @brief NRFX_EGU_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_EGU_ENABLED -#define NRFX_EGU_ENABLED 0 -#endif - -/** - * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_EGU020_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_EGU020_ENABLED -#define NRFX_EGU020_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - * - * Integer value. Minimum: 0. Maximum: 15. - */ -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS -#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED -#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL -#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_GPIOTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE130_ENABLED -#define NRFX_GPIOTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_ENABLED -#define NRFX_GRTC_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED -#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOEN - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOEN -#define NRFX_GRTC_CONFIG_AUTOEN 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOSTART - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOSTART -#define NRFX_GRTC_CONFIG_AUTOSTART 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS - * - * Integer value. - */ -#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS -#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK - */ -#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK -#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f00 -#endif - -/** - * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED -#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL -#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_I2S_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S_ENABLED -#define NRFX_I2S_ENABLED 0 -#endif - -/** - * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_I2S_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S_CONFIG_LOG_ENABLED -#define NRFX_I2S_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_I2S_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_I2S_CONFIG_LOG_LEVEL -#define NRFX_I2S_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_I2S130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S130_ENABLED -#define NRFX_I2S130_ENABLED 0 -#endif - -/** - * @brief NRFX_I2S131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_I2S131_ENABLED -#define NRFX_I2S131_ENABLED 0 -#endif - -/** - * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030 -#endif - -/** - * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000c0 -#endif - -/** - * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_LPCOMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_ENABLED -#define NRFX_LPCOMP_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED -#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL -#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_MVDMA_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_MVDMA_ENABLED -#define NRFX_MVDMA_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_ENABLED -#define NRFX_NFCT_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver. - * - * Integer value. Minimum: 0. Maximum: 5. - */ -#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID -#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED -#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL -#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PDM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_ENABLED -#define NRFX_PDM_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_CONFIG_LOG_ENABLED -#define NRFX_PDM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PDM_CONFIG_LOG_LEVEL -#define NRFX_PDM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_ENABLED -#define NRFX_PRS_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_CONFIG_LOG_ENABLED -#define NRFX_PRS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PRS_CONFIG_LOG_LEVEL -#define NRFX_PRS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_BOX_0_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_0_ENABLED -#define NRFX_PRS_BOX_0_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_1_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_1_ENABLED -#define NRFX_PRS_BOX_1_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_2_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_2_ENABLED -#define NRFX_PRS_BOX_2_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_3_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_3_ENABLED -#define NRFX_PRS_BOX_3_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_4_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_4_ENABLED -#define NRFX_PRS_BOX_4_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_5_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_5_ENABLED -#define NRFX_PRS_BOX_5_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_6_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_6_ENABLED -#define NRFX_PRS_BOX_6_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_7_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_7_ENABLED -#define NRFX_PRS_BOX_7_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_8_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_8_ENABLED -#define NRFX_PRS_BOX_8_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_9_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_9_ENABLED -#define NRFX_PRS_BOX_9_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_ENABLED -#define NRFX_PWM_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_CONFIG_LOG_ENABLED -#define NRFX_PWM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PWM_CONFIG_LOG_LEVEL -#define NRFX_PWM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PWM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM120_ENABLED -#define NRFX_PWM120_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM130_ENABLED -#define NRFX_PWM130_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM131_ENABLED -#define NRFX_PWM131_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM132_ENABLED -#define NRFX_PWM132_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM133_ENABLED -#define NRFX_PWM133_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_ENABLED -#define NRFX_QDEC_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED -#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL -#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_QDEC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC130_ENABLED -#define NRFX_QDEC130_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC131_ENABLED -#define NRFX_QDEC131_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_CONFIG_LOG_ENABLED -#define NRFX_RTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_RTC_CONFIG_LOG_LEVEL -#define NRFX_RTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_RTC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC130_ENABLED -#define NRFX_RTC130_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC131_ENABLED -#define NRFX_RTC131_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_ENABLED -#define NRFX_SAADC_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED -#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL -#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED -#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL -#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM120_ENABLED -#define NRFX_SPIM120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM121_ENABLED -#define NRFX_SPIM121_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM130_ENABLED -#define NRFX_SPIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM131_ENABLED -#define NRFX_SPIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM132_ENABLED -#define NRFX_SPIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM133_ENABLED -#define NRFX_SPIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM134_ENABLED -#define NRFX_SPIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM135_ENABLED -#define NRFX_SPIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM136_ENABLED -#define NRFX_SPIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM137_ENABLED -#define NRFX_SPIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED -#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL -#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIS120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS120_ENABLED -#define NRFX_SPIS120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS130_ENABLED -#define NRFX_SPIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS131_ENABLED -#define NRFX_SPIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS132_ENABLED -#define NRFX_SPIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS133_ENABLED -#define NRFX_SPIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS134_ENABLED -#define NRFX_SPIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS135_ENABLED -#define NRFX_SPIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS136_ENABLED -#define NRFX_SPIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS137_ENABLED -#define NRFX_SPIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_SYSTICK_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SYSTICK_ENABLED -#define NRFX_SYSTICK_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_ENABLED -#define NRFX_TEMP_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED -#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL -#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED -#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL -#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER020_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER020_ENABLED -#define NRFX_TIMER020_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER021_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER021_ENABLED -#define NRFX_TIMER021_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER022_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER022_ENABLED -#define NRFX_TIMER022_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER120_ENABLED -#define NRFX_TIMER120_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER121_ENABLED -#define NRFX_TIMER121_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER130_ENABLED -#define NRFX_TIMER130_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER131_ENABLED -#define NRFX_TIMER131_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER132_ENABLED -#define NRFX_TIMER132_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER133_ENABLED -#define NRFX_TIMER133_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER134_ENABLED -#define NRFX_TIMER134_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER135_ENABLED -#define NRFX_TIMER135_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER136_ENABLED -#define NRFX_TIMER136_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER137_ENABLED -#define NRFX_TIMER137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED -#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL -#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM130_ENABLED -#define NRFX_TWIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM131_ENABLED -#define NRFX_TWIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM132_ENABLED -#define NRFX_TWIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM133_ENABLED -#define NRFX_TWIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM134_ENABLED -#define NRFX_TWIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM135_ENABLED -#define NRFX_TWIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM136_ENABLED -#define NRFX_TWIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM137_ENABLED -#define NRFX_TWIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ENABLED -#define NRFX_TWIS_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED -#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance - * would be initialized only once. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -/** - * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_NO_SYNC_MODE -#define NRFX_TWIS_NO_SYNC_MODE 0 -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL -#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS130_ENABLED -#define NRFX_TWIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS131_ENABLED -#define NRFX_TWIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS132_ENABLED -#define NRFX_TWIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS133_ENABLED -#define NRFX_TWIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS134_ENABLED -#define NRFX_TWIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS135_ENABLED -#define NRFX_TWIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS136_ENABLED -#define NRFX_TWIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS137_ENABLED -#define NRFX_TWIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for - * configuring GPIO pins is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for - * configuring PSEL registers is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking - * of TX transfers. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_TX_LINK -#define NRFX_UARTE_CONFIG_TX_LINK 1 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED -#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 -#endif - -/** - * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED -#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL -#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_UARTE120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE120_ENABLED -#define NRFX_UARTE120_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE130_ENABLED -#define NRFX_UARTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE131_ENABLED -#define NRFX_UARTE131_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE132_ENABLED -#define NRFX_UARTE132_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE133_ENABLED -#define NRFX_UARTE133_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE134_ENABLED -#define NRFX_UARTE134_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE135_ENABLED -#define NRFX_UARTE135_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE136_ENABLED -#define NRFX_UARTE136_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE137_ENABLED -#define NRFX_UARTE137_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_NO_IRQ -#define NRFX_WDT_CONFIG_NO_IRQ 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_LOG_ENABLED -#define NRFX_WDT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_WDT_CONFIG_LOG_LEVEL -#define NRFX_WDT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_WDT010_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT010_ENABLED -#define NRFX_WDT010_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT011_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT011_ENABLED -#define NRFX_WDT011_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT131_ENABLED -#define NRFX_WDT131_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT132_ENABLED -#define NRFX_WDT132_ENABLED 0 -#endif - -#endif /* NRFX_CONFIG_NRF54H20_ENGA_RADIOCORE_H__ */ From a8bb9fd1c1129a550930ebacfd573e720b03b335 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Wed, 13 Mar 2024 17:40:30 +0100 Subject: [PATCH 0890/2402] dts: Remove support for nRF54H20 EngA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was a preview revision of the SoC that will no longer be supported. Signed-off-by: Andrzej Głąbek --- dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi | 51 - dts/arm/nordic/nrf54h20_enga_cpurad.dtsi | 51 - dts/common/nordic/nrf54h20_enga.dtsi | 941 ------------------ dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi | 48 - .../misc/nordic-nrf-ficr-nrf54h20-enga.h | 96 -- 5 files changed, 1187 deletions(-) delete mode 100644 dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi delete mode 100644 dts/arm/nordic/nrf54h20_enga_cpurad.dtsi delete mode 100644 dts/common/nordic/nrf54h20_enga.dtsi delete mode 100644 dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi delete mode 100644 include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20-enga.h diff --git a/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi b/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi deleted file mode 100644 index 7252b3d5a04..00000000000 --- a/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -cpu: &cpuapp {}; -systick: &cpuapp_systick {}; -nvic: &cpuapp_nvic {}; -cpuppr_vevif: &cpuppr_vevif_remote {}; - -/delete-node/ &cpuppr; -/delete-node/ &cpurad; -/delete-node/ &cpurad_peripherals; -/delete-node/ &cpurad_ppb; -/delete-node/ &cpurad_ram0; - -/ { - soc { - compatible = "simple-bus"; - interrupt-parent = <&cpuapp_nvic>; - ranges; - }; -}; - -&cpuapp_ppb { - compatible = "simple-bus"; - ranges; -}; - -&cpusec_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpuapp_bellboard { - compatible = "nordic,nrf-bellboard-local"; -}; - -&cpurad_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&gpiote130 { - interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; -}; - -&grtc { - interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>; -}; diff --git a/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi b/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi deleted file mode 100644 index d2aaa790349..00000000000 --- a/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -cpu: &cpurad {}; -systick: &cpurad_systick {}; -nvic: &cpurad_nvic {}; -cpuppr_vevif: &cpuppr_vevif_remote {}; - -/delete-node/ &cpuapp; -/delete-node/ &cpuapp_peripherals; -/delete-node/ &cpuapp_ppb; -/delete-node/ &cpuapp_ram0; -/delete-node/ &cpuppr; - -/ { - soc { - compatible = "simple-bus"; - interrupt-parent = <&cpurad_nvic>; - ranges; - }; -}; - -&cpurad_ppb { - compatible = "simple-bus"; - ranges; -}; - -&cpusec_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpuapp_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpurad_bellboard { - compatible = "nordic,nrf-bellboard-local"; -}; - -&gpiote130 { - interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; -}; - -&grtc { - interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>; -}; diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi deleted file mode 100644 index 8552b9534eb..00000000000 --- a/dts/common/nordic/nrf54h20_enga.dtsi +++ /dev/null @@ -1,941 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#include - -/* Domain IDs. Can be used to specify channel links in IPCT nodes. */ -#define NRF_DOMAIN_ID_APPLICATION 2 -#define NRF_DOMAIN_ID_RADIOCORE 3 -#define NRF_DOMAIN_ID_GLOBALFAST 12 -#define NRF_DOMAIN_ID_GLOBALSLOW 13 - -/delete-node/ &sw_pwm; - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpuapp: cpu@2 { - compatible = "arm,cortex-m33"; - reg = <2>; - device_type = "cpu"; - clock-frequency = ; - }; - - cpurad: cpu@3 { - compatible = "arm,cortex-m33"; - reg = <3>; - device_type = "cpu"; - clock-frequency = ; - }; - - cpuppr: cpu@d { - compatible = "nordic,vpr"; - reg = <13>; - device_type = "cpu"; - clock-frequency = ; - riscv,isa = "rv32emc"; - nordic,bus-width = <32>; - - cpuppr_vevif_local: mailbox { - compatible = "nordic,nrf-vevif-local"; - status = "disabled"; - interrupt-parent = <&cpuppr_clic>; - interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, - <1 NRF_DEFAULT_IRQ_PRIORITY>, - <2 NRF_DEFAULT_IRQ_PRIORITY>, - <3 NRF_DEFAULT_IRQ_PRIORITY>, - <4 NRF_DEFAULT_IRQ_PRIORITY>, - <5 NRF_DEFAULT_IRQ_PRIORITY>, - <6 NRF_DEFAULT_IRQ_PRIORITY>, - <7 NRF_DEFAULT_IRQ_PRIORITY>, - <8 NRF_DEFAULT_IRQ_PRIORITY>, - <9 NRF_DEFAULT_IRQ_PRIORITY>, - <10 NRF_DEFAULT_IRQ_PRIORITY>, - <11 NRF_DEFAULT_IRQ_PRIORITY>, - <12 NRF_DEFAULT_IRQ_PRIORITY>, - <13 NRF_DEFAULT_IRQ_PRIORITY>, - <14 NRF_DEFAULT_IRQ_PRIORITY>, - <15 NRF_DEFAULT_IRQ_PRIORITY>; - #mbox-cells = <1>; - nordic,tasks = <16>; - nordic,tasks-mask = <0xfffffff0>; - }; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - - cpurad_uicr_ext: memory@e1ff000 { - reg = <0xe1ff000 DT_SIZE_K(2)>; - }; - - cpuapp_uicr_ext: memory@e1ff800 { - reg = <0xe1ff800 DT_SIZE_K(2)>; - }; - }; - - clocks { - fll16m: fll16m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = ; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - - mram1x: mram@e000000 { - compatible = "nordic,mram"; - reg = <0xe000000 DT_SIZE_K(2048)>; - erase-block-size = <4096>; - write-block-size = <16>; - }; - - cpuapp_uicr: uicr@fff8000 { - compatible = "nordic,nrf-uicr-v2"; - reg = <0xfff8000 DT_SIZE_K(2)>; - domain = <2>; - ptr-ext-uicr = <&cpuapp_uicr_ext>; - }; - - cpurad_uicr: uicr@fffa000 { - compatible = "nordic,nrf-uicr-v2"; - reg = <0xfffa000 DT_SIZE_K(2)>; - domain = <3>; - ptr-ext-uicr = <&cpurad_uicr_ext>; - }; - - ficr: ficr@fffe000 { - compatible = "nordic,nrf-ficr"; - reg = <0xfffe000 DT_SIZE_K(2)>; - #nordic,ficr-cells = <1>; - }; - - cpuapp_ram0: sram@22000000 { - compatible = "mmio-sram"; - reg = <0x22000000 DT_SIZE_K(32)>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000000 0x8000>; - }; - - cpurad_ram0: sram@23000000 { - compatible = "mmio-sram"; - reg = <0x23000000 DT_SIZE_K(64)>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x23000000 0x10000>; - }; - - cpuapp_peripherals: peripheral@52000000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x52000000 0x1000000>; - - cpuapp_hsfll: clock@d000 { - compatible = "nordic,nrf-hsfll"; - #clock-cells = <0>; - reg = <0xd000 0x1000>; - clocks = <&fll16m>; - clock-frequency = ; - nordic,ficrs = - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; - nordic,ficr-names = "vsup", "coarse", "fine"; - }; - - cpuapp_ipct: ipct@13000 { - compatible = "nordic,nrf-ipct-local"; - reg = <0x13000 0x1000>; - status = "disabled"; - channels = <4>; - interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, - <65 NRF_DEFAULT_IRQ_PRIORITY>; - }; - }; - - cpurad_peripherals: peripheral@53000000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53000000 0x1000000>; - - cpurad_hsfll: clock@d000 { - compatible = "nordic,nrf-hsfll"; - #clock-cells = <0>; - reg = <0xd000 0x1000>; - clocks = <&fll16m>; - clock-frequency = ; - nordic,ficrs = - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; - nordic,ficr-names = "vsup", "coarse", "fine"; - }; - - dppic020: dppic@22000 { - compatible = "nordic,nrf-dppic-local"; - reg = <0x22000 0x1000>; - status = "disabled"; - }; - - cpurad_ipct: ipct@24000 { - compatible = "nordic,nrf-ipct-local"; - reg = <0x24000 0x1000>; - status = "disabled"; - channels = <8>; - interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, - <65 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - egu020: egu@25000 { - compatible = "nordic,nrf-egu"; - reg = <0x25000 0x1000>; - status = "disabled"; - interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - ecb020: ecb@27000 { - compatible = "nordic,nrf-ecb"; - reg = <0x27000 0x1000>; - status = "disabled"; - interrupts = <39 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - timer020: timer@28000 { - compatible = "nordic,nrf-timer"; - reg = <0x28000 0x1000>; - status = "disabled"; - cc-num = <8>; - interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer021: timer@29000 { - compatible = "nordic,nrf-timer"; - reg = <0x29000 0x1000>; - status = "disabled"; - cc-num = <8>; - interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer022: timer@2a000 { - compatible = "nordic,nrf-timer"; - reg = <0x2a000 0x1000>; - status = "disabled"; - cc-num = <8>; - interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - rtc: rtc@2b000 { - compatible = "nordic,nrf-rtc"; - reg = <0x2b000 0x1000>; - status = "disabled"; - cc-num = <4>; - clock-frequency = <32768>; - interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>; - prescaler = <1>; - }; - - radio: radio@2c000 { - compatible = "nordic,nrf-radio"; - reg = <0x2c000 0x1000>; - status = "disabled"; - ble-2mbps-supported; - ble-coded-phy-supported; - dfe-supported; - ieee802154-supported; - interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>; - - cpurad_ieee802154: ieee802154 { - compatible = "nordic,nrf-ieee802154"; - status = "disabled"; - }; - }; - - ecb030: ecb@3b000 { - compatible = "nordic,nrf-ecb"; - reg = <0x3b000 0x1000>; - interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>; - status = "disabled"; - }; - }; - - global_peripherals: peripheral@5f000000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5f000000 0x1000000>; - - cpusec_bellboard: mailbox@99000 { - reg = <0x99000 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - }; - - cpuapp_bellboard: mailbox@9a000 { - reg = <0x9a000 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - }; - - cpurad_bellboard: mailbox@9b000 { - reg = <0x9b000 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - }; - - ipct120: ipct@8d1000 { - compatible = "nordic,nrf-ipct-global"; - reg = <0x8d1000 0x1000>; - status = "disabled"; - channels = <8>; - global-domain-id = <12>; - }; - - dppic120: dppic@8e1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x8e1000 0x1000>; - status = "disabled"; - }; - - timer120: timer@8e2000 { - compatible = "nordic,nrf-timer"; - reg = <0x8e2000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer121: timer@8e3000 { - compatible = "nordic,nrf-timer"; - reg = <0x8e3000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - uart120: uart@8e5000 { - compatible = "nordic,nrf-uarte"; - reg = <0x8e5000 0x1000>; - status = "disabled"; - interrupts = <229 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - spi120: spi@8e6000 { - compatible = "nordic,nrf-spim"; - reg = <0x8e6000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi121: spi@8e7000 { - compatible = "nordic,nrf-spim"; - reg = <0x8e7000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - cpuppr_vpr: vpr@908000 { - compatible = "nordic,nrf-vpr-coprocessor"; - reg = <0x908000 0x1000>; - status = "disabled"; - cpu = <13>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x908000 0x4000>; - - cpuppr_vevif_remote: mailbox@0 { - compatible = "nordic,nrf-vevif-remote"; - reg = <0x0 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - nordic,tasks = <16>; - nordic,tasks-mask = <0xfffffff0>; - }; - - cpuppr_clic: interrupt-controller@1000 { - compatible = "nordic,nrf-clic"; - reg = <0x1000 0x3000>; - status = "disabled"; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - }; - }; - - ipct130: ipct@921000 { - compatible = "nordic,nrf-ipct-global"; - reg = <0x921000 0x1000>; - status = "disabled"; - channels = <8>; - global-domain-id = <13>; - }; - - dppic130: dppic@922000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x922000 0x1000>; - status = "disabled"; - }; - - rtc130: rtc@928000 { - compatible = "nordic,nrf-rtc"; - reg = <0x928000 0x1000>; - status = "disabled"; - cc-num = <4>; - clock-frequency = <32768>; - interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>; - prescaler = <1>; - }; - - rtc131: rtc@929000 { - compatible = "nordic,nrf-rtc"; - reg = <0x929000 0x1000>; - status = "disabled"; - cc-num = <4>; - clock-frequency = <32768>; - interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>; - prescaler = <1>; - }; - - wdt131: watchdog@92b000 { - compatible = "nordic,nrf-wdt"; - reg = <0x92b000 0x1000>; - status = "disabled"; - interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - wdt132: watchdog@92c000 { - compatible = "nordic,nrf-wdt"; - reg = <0x92c000 0x1000>; - status = "disabled"; - interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - gpiote130: gpiote@934000 { - compatible = "nordic,nrf-gpiote"; - reg = <0x934000 0x1000>; - status = "disabled"; - instance = <130>; - }; - - gpio0: gpio@938000 { - compatible = "nordic,nrf-gpio"; - reg = <0x938000 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - gpiote-instance = <&gpiote130>; - ngpios = <12>; - port = <0>; - }; - - gpio1: gpio@938200 { - compatible = "nordic,nrf-gpio"; - reg = <0x938200 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - gpiote-instance = <&gpiote130>; - ngpios = <12>; - port = <1>; - }; - - gpio2: gpio@938400 { - compatible = "nordic,nrf-gpio"; - reg = <0x938400 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - gpiote-instance = <&gpiote130>; - ngpios = <12>; - port = <2>; - }; - - gpio6: gpio@938c00 { - compatible = "nordic,nrf-gpio"; - reg = <0x938c00 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - ngpios = <14>; - port = <6>; - }; - - gpio7: gpio@938e00 { - compatible = "nordic,nrf-gpio"; - reg = <0x938e00 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - ngpios = <8>; - port = <7>; - }; - - gpio9: gpio@939200 { - compatible = "nordic,nrf-gpio"; - reg = <0x939200 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - gpiote-instance = <&gpiote130>; - ngpios = <6>; - port = <9>; - }; - - dppic131: dppic@981000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x981000 0x1000>; - status = "disabled"; - }; - - comp: comparator@983000 { - compatible = "nordic,nrf-comp"; - reg = <0x983000 0x1000>; - status = "disabled"; - interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>; - #io-channel-cells = <1>; - }; - - temp: temperature-sensor@984000 { - compatible = "nordic,nrf-temp"; - reg = <0x984000 0x1000>; - interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>; - status = "disabled"; - }; - - nfct: nfct@985000 { - compatible = "nordic,nrf-nfct"; - reg = <0x985000 0x1000>; - status = "disabled"; - interrupts = <389 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - dppic132: dppic@991000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x991000 0x1000>; - status = "disabled"; - }; - - qdec130: qdec@994000 { - compatible = "nordic,nrf-qdec"; - reg = <0x994000 0x1000>; - status = "disabled"; - interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - qdec131: qdec@995000 { - compatible = "nordic,nrf-qdec"; - reg = <0x995000 0x1000>; - status = "disabled"; - interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - grtc: grtc@99c000 { - compatible = "nordic,nrf-grtc"; - reg = <0x99c000 0x1000>; - status = "disabled"; - cc-num = <16>; - }; - - dppic133: dppic@9a1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9a1000 0x1000>; - status = "disabled"; - }; - - timer130: timer@9a2000 { - compatible = "nordic,nrf-timer"; - reg = <0x9a2000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer131: timer@9a3000 { - compatible = "nordic,nrf-timer"; - reg = <0x9a3000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - i2c130: i2c@9a5000 { - compatible = "nordic,nrf-twim"; - reg = <0x9a5000 0x1000>; - status = "disabled"; - interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi130: spi@9a5000 { - compatible = "nordic,nrf-spim"; - reg = <0x9a5000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart130: uart@9a5000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9a5000 0x1000>; - status = "disabled"; - interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - i2c131: i2c@9a6000 { - compatible = "nordic,nrf-twim"; - reg = <0x9a6000 0x1000>; - status = "disabled"; - interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi131: spi@9a6000 { - compatible = "nordic,nrf-spim"; - reg = <0x9a6000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart131: uart@9a6000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9a6000 0x1000>; - status = "disabled"; - interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - dppic134: dppic@9b1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9b1000 0x1000>; - status = "disabled"; - }; - - timer132: timer@9b2000 { - compatible = "nordic,nrf-timer"; - reg = <0x9b2000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer133: timer@9b3000 { - compatible = "nordic,nrf-timer"; - reg = <0x9b3000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - i2c132: i2c@9b5000 { - compatible = "nordic,nrf-twim"; - reg = <0x9b5000 0x1000>; - status = "disabled"; - interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi132: spi@9b5000 { - compatible = "nordic,nrf-spim"; - reg = <0x9b5000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart132: uart@9b5000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9b5000 0x1000>; - status = "disabled"; - interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - i2c133: i2c@9b6000 { - compatible = "nordic,nrf-twim"; - reg = <0x9b6000 0x1000>; - status = "disabled"; - interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi133: spi@9b6000 { - compatible = "nordic,nrf-spim"; - reg = <0x9b6000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart133: uart@9b6000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9b6000 0x1000>; - status = "disabled"; - interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - dppic135: dppic@9c1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9c1000 0x1000>; - status = "disabled"; - }; - - timer134: timer@9c2000 { - compatible = "nordic,nrf-timer"; - reg = <0x9c2000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer135: timer@9c3000 { - compatible = "nordic,nrf-timer"; - reg = <0x9c3000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - i2c134: i2c@9c5000 { - compatible = "nordic,nrf-twim"; - reg = <0x9c5000 0x1000>; - status = "disabled"; - interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi134: spi@9c5000 { - compatible = "nordic,nrf-spim"; - reg = <0x9c5000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart134: uart@9c5000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9c5000 0x1000>; - status = "disabled"; - interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - i2c135: i2c@9c6000 { - compatible = "nordic,nrf-twim"; - reg = <0x9c6000 0x1000>; - status = "disabled"; - interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi135: spi@9c6000 { - compatible = "nordic,nrf-spim"; - reg = <0x9c6000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart135: uart@9c6000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9c6000 0x1000>; - status = "disabled"; - interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - dppic136: dppic@9d1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9d1000 0x1000>; - status = "disabled"; - }; - - timer136: timer@9d2000 { - compatible = "nordic,nrf-timer"; - reg = <0x9d2000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer137: timer@9d3000 { - compatible = "nordic,nrf-timer"; - reg = <0x9d3000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - i2c136: i2c@9d5000 { - compatible = "nordic,nrf-twim"; - reg = <0x9d5000 0x1000>; - status = "disabled"; - interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi136: spi@9d5000 { - compatible = "nordic,nrf-spim"; - reg = <0x9d5000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart136: uart@9d5000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9d5000 0x1000>; - status = "disabled"; - interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - i2c137: i2c@9d6000 { - compatible = "nordic,nrf-twim"; - reg = <0x9d6000 0x1000>; - status = "disabled"; - interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi137: spi@9d6000 { - compatible = "nordic,nrf-spim"; - reg = <0x9d6000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart137: uart@9d6000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9d6000 0x1000>; - status = "disabled"; - interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; - }; - }; - }; - - cpuapp_ppb: cpuapp-ppb-bus { - #address-cells = <1>; - #size-cells = <1>; - - cpuapp_systick: timer@e000e010 { - compatible = "arm,armv8m-systick"; - reg = <0xe000e010 0x10>; - status = "disabled"; - }; - - cpuapp_nvic: interrupt-controller@e000e100 { - compatible = "arm,v8m-nvic"; - reg = <0xe000e100 0xc00>; - arm,num-irq-priority-bits = <3>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - }; - }; - - cpurad_ppb: cpurad-ppb-bus { - #address-cells = <1>; - #size-cells = <1>; - - cpurad_systick: timer@e000e010 { - compatible = "arm,armv8m-systick"; - reg = <0xe000e010 0x10>; - status = "disabled"; - }; - - cpurad_nvic: interrupt-controller@e000e100 { - compatible = "arm,v8m-nvic"; - reg = <0xe000e100 0xc00>; - arm,num-irq-priority-bits = <3>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - }; - }; -}; diff --git a/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi b/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi deleted file mode 100644 index 0af6618688f..00000000000 --- a/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -cpu: &cpuppr {}; -clic: &cpuppr_clic {}; -cpuppr_vevif: &cpuppr_vevif_local {}; - -/delete-node/ &cpuapp; -/delete-node/ &cpuapp_peripherals; -/delete-node/ &cpuapp_ppb; -/delete-node/ &cpuapp_ram0; -/delete-node/ &cpurad; -/delete-node/ &cpurad_peripherals; -/delete-node/ &cpurad_ppb; -/delete-node/ &cpurad_ram0; - -/ { - soc { - compatible = "simple-bus"; - interrupt-parent = <&cpuppr_clic>; - ranges; - }; -}; - -&cpusec_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpuapp_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpurad_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&gpiote130 { - interrupts = <104 NRF_DEFAULT_IRQ_PRIORITY>; -}; - -&grtc { - interrupts = <108 NRF_DEFAULT_IRQ_PRIORITY>; -}; diff --git a/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20-enga.h b/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20-enga.h deleted file mode 100644 index 60b788a3516..00000000000 --- a/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20-enga.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -/* autogenerated using Nordic HAL utils/gen_offsets.py script */ - -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_ENGA_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_ENGA_H_ - -#define NRF_FICR_BLE_ADDRTYPE 0x00CU -#define NRF_FICR_BLE_ADDR_0 0x010U -#define NRF_FICR_BLE_ADDR_1 0x014U -#define NRF_FICR_BLE_ER_0 0x018U -#define NRF_FICR_BLE_ER_1 0x01CU -#define NRF_FICR_BLE_ER_2 0x020U -#define NRF_FICR_BLE_ER_3 0x024U -#define NRF_FICR_BLE_IR_0 0x028U -#define NRF_FICR_BLE_IR_1 0x02CU -#define NRF_FICR_BLE_IR_2 0x030U -#define NRF_FICR_BLE_IR_3 0x034U -#define NRF_FICR_NFC_TAGHEADER_0 0x040U -#define NRF_FICR_NFC_TAGHEADER_1 0x044U -#define NRF_FICR_NFC_TAGHEADER_2 0x048U -#define NRF_FICR_NFC_TAGHEADER_3 0x04CU -#define NRF_FICR_INFO_CONFIGID 0x050U -#define NRF_FICR_INFO_PART 0x054U -#define NRF_FICR_INFO_VARIANT 0x058U -#define NRF_FICR_INFO_PACKAGE 0x05CU -#define NRF_FICR_INFO_RAM 0x060U -#define NRF_FICR_INFO_MRAM 0x064U -#define NRF_FICR_INFO_CODEPAGESIZE 0x068U -#define NRF_FICR_INFO_CODESIZE 0x06CU -#define NRF_FICR_INFO_DEVICETYPE 0x070U -#define NRF_FICR_TRIM_GLOBAL_SAADC_CALVREF 0x384U -#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_0 0x388U -#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_1 0x38CU -#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_2 0x390U -#define NRF_FICR_TRIM_GLOBAL_SAADC_CALOFFSET 0x394U -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_0 0x398U -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_1 0x39CU -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_2 0x3A0U -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_3 0x3A4U -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_4 0x3A8U -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_5 0x3ACU -#define NRF_FICR_TRIM_GLOBAL_SAADC_CALIREF 0x3B0U -#define NRF_FICR_TRIM_GLOBAL_SAADC_CALVREFTC 0x3B4U -#define NRF_FICR_TRIM_GLOBAL_NFCT_BIASCFG 0x3BCU -#define NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE 0x3C0U -#define NRF_FICR_TRIM_GLOBAL_COMP_REFTRIM 0x3D0U -#define NRF_FICR_TRIM_GLOBAL_COMP_RCALTRIM 0x3D4U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP 0x3D8U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0 0x3DCU -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_1 0x3E0U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_2 0x3E4U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_3 0x3E8U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_4 0x3ECU -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_5 0x3F0U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0 0x3F4U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_1 0x3F8U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_2 0x3FCU -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_3 0x400U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_4 0x404U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_5 0x408U -#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_0_TRIM 0x40CU -#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_1_TRIM 0x410U -#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_2_TRIM 0x414U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP 0x418U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_0 0x41CU -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1 0x420U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_2 0x424U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_3 0x428U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_4 0x42CU -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_5 0x430U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_0 0x434U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1 0x438U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_2 0x43CU -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_3 0x440U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_4 0x444U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_5 0x448U -#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_0_TRIM 0x44CU -#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_1_TRIM 0x450U -#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_2_TRIM 0x454U -#define NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL0 0x458U -#define NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL1 0x45CU -#define NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL2 0x460U -#define NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_RXCTRL 0x464U -#define NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_OVRRXTRIMCODE 0x468U -#define NRF_FICR_TRIM_RADIOCORE_RADIO_RXAGC_CALIBRATION 0x46CU -#define NRF_FICR_TRIM_RADIOCORE_RADIO_PVTTOT 0x470U -#define NRF_FICR_TRIM_RADIOCORE_RADIO_KDTC 0x474U -#define NRF_FICR_TRIM_RADIOCORE_RADIO_TXHFGAIN 0x478U -#define NRF_FICR_TRIM_RADIOCORE_RADIO_PVTTOFIX 0x47CU -#define NRF_FICR_TRIM_RADIOCORE_RADIO_LOOPGAIN 0x480U - -#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_ENGA_H_ */ From 4d16e5b7d9166e1bb57cdfb55da56f9538a57a9b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Wed, 13 Mar 2024 17:41:37 +0100 Subject: [PATCH 0891/2402] soc: nordic: Remove support for nRF54H20 EngA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was a preview revision of the SoC that will no longer be supported. Signed-off-by: Andrzej Głąbek --- soc/nordic/common/vpr/Kconfig.defconfig | 6 ----- soc/nordic/nrf54h/Kconfig | 25 ------------------- .../Kconfig.defconfig.nrf54h20_enga_cpuapp | 14 ----------- .../Kconfig.defconfig.nrf54h20_enga_cpuppr | 12 --------- .../Kconfig.defconfig.nrf54h20_enga_cpurad | 14 ----------- soc/nordic/nrf54h/Kconfig.soc | 18 ------------- soc/nordic/nrf54h/soc.c | 10 -------- 7 files changed, 99 deletions(-) delete mode 100644 soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp delete mode 100644 soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr delete mode 100644 soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad diff --git a/soc/nordic/common/vpr/Kconfig.defconfig b/soc/nordic/common/vpr/Kconfig.defconfig index a89593170f6..ccab6b62c1d 100644 --- a/soc/nordic/common/vpr/Kconfig.defconfig +++ b/soc/nordic/common/vpr/Kconfig.defconfig @@ -1,12 +1,6 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -CPU_PATH := $(dt_nodelabel_path,cpu) -CPU_ID := $(dt_node_reg_addr_int,$(CPU_PATH)) - -config RV_BOOT_HART - default $(CPU_ID) if SOC_NRF54H20_ENGA_CPUPPR - config RISCV_MCAUSE_EXCEPTION_MASK default 0xFFF diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig index 81b6c04993c..2b967bece7c 100644 --- a/soc/nordic/nrf54h/Kconfig +++ b/soc/nordic/nrf54h/Kconfig @@ -32,31 +32,6 @@ config SOC_NRF54H20_CPURAD config SOC_NRF54H20_CPUPPR depends on RISCV_CORE_NORDIC_VPR -config SOC_NRF54H20_ENGA_CPUAPP - select ARM - select ARMV8_M_DSP - select CPU_CORTEX_M33 - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CPU_HAS_FPU - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -config SOC_NRF54H20_ENGA_CPURAD - select ARM - select ARMV8_M_DSP - select CPU_CORTEX_M33 - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CPU_HAS_FPU - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -config SOC_NRF54H20_ENGA_CPUPPR - depends on RISCV_CORE_NORDIC_VPR - if SOC_NRF54H20 config NRF_ENABLE_ICACHE diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp deleted file mode 100644 index af261c3e0a3..00000000000 --- a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp +++ /dev/null @@ -1,14 +0,0 @@ -# Nordic Semiconductor nRF54H20 Application MCU - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF54H20_ENGA_CPUAPP - -config NUM_IRQS - default 471 - -config NRF_REGTOOL_GENERATE_UICR - default y - -endif # SOC_NRF54H20_ENGA_CPUAPP diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr deleted file mode 100644 index 3d48375b97d..00000000000 --- a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF54H20_ENGA_CPUPPR - -config NUM_IRQS - default 496 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -endif # SOC_NRF54H20_ENGA_CPUPPR diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad deleted file mode 100644 index e83eea71b48..00000000000 --- a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad +++ /dev/null @@ -1,14 +0,0 @@ -# Nordic Semiconductor nRF54H20 Radio MCU - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF54H20_ENGA_CPURAD - -config NUM_IRQS - default 471 - -config NRF_REGTOOL_GENERATE_UICR - default y - -endif # SOC_NRF54H20_ENGA_CPURAD diff --git a/soc/nordic/nrf54h/Kconfig.soc b/soc/nordic/nrf54h/Kconfig.soc index 2a190994183..100923206fd 100644 --- a/soc/nordic/nrf54h/Kconfig.soc +++ b/soc/nordic/nrf54h/Kconfig.soc @@ -27,23 +27,5 @@ config SOC_NRF54H20_CPUPPR help nRF54H20 CPUPPR -config SOC_NRF54H20_ENGA_CPUAPP - bool - select SOC_NRF54H20 - help - nRF54H20 ENGA CPUAPP - -config SOC_NRF54H20_ENGA_CPURAD - bool - select SOC_NRF54H20 - help - nRF54H20 ENGA CPURAD - -config SOC_NRF54H20_ENGA_CPUPPR - bool - select SOC_NRF54H20 - help - nRF54H20 ENGA CPUPPR - config SOC default "nrf54h20" if SOC_NRF54H20 diff --git a/soc/nordic/nrf54h/soc.c b/soc/nordic/nrf54h/soc.c index 9fefd414152..cf134dc99b1 100644 --- a/soc/nordic/nrf54h/soc.c +++ b/soc/nordic/nrf54h/soc.c @@ -44,10 +44,6 @@ static void power_domain_init(void) nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true); nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true); - -#if defined(CONFIG_SOC_NRF54H20_ENGA_CPUAPP) - nrf_lrcconf_poweron_force_set(NRF_LRCCONF000, NRF_LRCCONF_POWER_DOMAIN_0, true); -#endif } static int trim_hsfll(void) @@ -69,12 +65,6 @@ static int trim_hsfll(void) nrf_hsfll_trim_set(hsfll, &trim); nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE); -#if defined(CONFIG_SOC_NRF54H20_ENGA_CPUAPP) || defined(CONFIG_SOC_NRF54H20_ENGA_CPURAD) - /* In this HW revision, HSFLL task frequency change needs to be - * triggered additional time to take effect. - */ - nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE); -#endif LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP); LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE); From 6ff7ec220e25ac1ba1a1803831ee3407acd26e76 Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Thu, 14 Mar 2024 08:39:38 +0100 Subject: [PATCH 0892/2402] boards: nrf54h20dk: Make execution from RAM default for PPR In practice, PPR is intended to be running code from RAM, so make this the default choice for the `nrf54h20dk/nrf54h20/cpuppr` board target. Keep the MRAM execution option as a `xip` variant of that target, replacing the `ram` one. Align the default `cpuapp` configuration for copying PPR's image to RAM before it boots the child processor. Signed-off-by: Grzegorz Swiderski --- boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk | 2 +- boards/nordic/nrf54h20dk/board.yml | 2 +- boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 3 ++- boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml | 2 +- .../nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig | 3 +++ ..._cpuppr_ram.yaml => nrf54h20dk_nrf54h20_cpuppr_xip.yaml} | 6 +++--- ...m_defconfig => nrf54h20dk_nrf54h20_cpuppr_xip_defconfig} | 2 +- 7 files changed, 12 insertions(+), 8 deletions(-) rename boards/nordic/nrf54h20dk/{nrf54h20dk_nrf54h20_cpuppr_ram.yaml => nrf54h20dk_nrf54h20_cpuppr_xip.yaml} (62%) rename boards/nordic/nrf54h20dk/{nrf54h20dk_nrf54h20_cpuppr_ram_defconfig => nrf54h20dk_nrf54h20_cpuppr_xip_defconfig} (86%) diff --git a/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk b/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk index fb9e66406f8..23bea2ba1e1 100644 --- a/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk +++ b/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk @@ -5,4 +5,4 @@ config BOARD_NRF54H20DK select SOC_NRF54H20_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPUAPP select SOC_NRF54H20_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD select SOC_NRF54H20_CPUPPR if BOARD_NRF54H20DK_NRF54H20_CPUPPR || \ - BOARD_NRF54H20DK_NRF54H20_CPUPPR_RAM + BOARD_NRF54H20DK_NRF54H20_CPUPPR_XIP diff --git a/boards/nordic/nrf54h20dk/board.yml b/boards/nordic/nrf54h20dk/board.yml index 156f817f86d..fed4c28d3e8 100644 --- a/boards/nordic/nrf54h20dk/board.yml +++ b/boards/nordic/nrf54h20dk/board.yml @@ -4,5 +4,5 @@ board: socs: - name: nrf54h20 variants: - - name: ram + - name: xip cpucluster: cpuppr diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 3873fec457e..a8ea9fe730f 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -131,7 +131,8 @@ }; &cpuppr_vpr { - execution-memory = <&cpuppr_code_partition>; + execution-memory = <&cpuppr_code_data>; + source-memory = <&cpuppr_code_partition>; }; &gpiote130 { diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml index 876debfb62c..b986a456623 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml @@ -8,6 +8,6 @@ arch: riscv toolchain: - zephyr ram: 62 -flash: 64 +flash: 62 supported: - gpio diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig index 0e657c5081e..76aa51244f1 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig @@ -2,3 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from RAM +CONFIG_XIP=n diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip.yaml similarity index 62% rename from boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram.yaml rename to boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip.yaml index f35f6f0cbdc..d0b1f448119 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram.yaml +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip.yaml @@ -1,13 +1,13 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: nrf54h20dk/nrf54h20/cpuppr/ram -name: nRF54H20-DK-nRF54H20-PPR-RAM +identifier: nrf54h20dk/nrf54h20/cpuppr/xip +name: nRF54H20-DK-nRF54H20-PPR (MRAM XIP) type: mcu arch: riscv toolchain: - zephyr ram: 62 -flash: 62 +flash: 64 supported: - gpio diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_defconfig similarity index 86% rename from boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig rename to boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_defconfig index bc8ce62afbb..d3d1bf7799f 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_defconfig @@ -1,4 +1,4 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -CONFIG_XIP=n +CONFIG_XIP=y From 13bebdbf3ad4d4a6f0292720955ef41cb792f0cb Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Thu, 14 Mar 2024 08:39:38 +0100 Subject: [PATCH 0893/2402] snippets: Remove nordic-ppr-ram The `nordic-ppr` snippet can now be used instead, since RAM execution is default for PPR. Signed-off-by: Grzegorz Swiderski --- snippets/nordic-ppr-ram/README.rst | 11 ----------- .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 16 ---------------- snippets/nordic-ppr-ram/nordic-ppr-ram.overlay | 15 --------------- snippets/nordic-ppr-ram/snippet.yml | 8 -------- 4 files changed, 50 deletions(-) delete mode 100644 snippets/nordic-ppr-ram/README.rst delete mode 100644 snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay delete mode 100644 snippets/nordic-ppr-ram/nordic-ppr-ram.overlay delete mode 100644 snippets/nordic-ppr-ram/snippet.yml diff --git a/snippets/nordic-ppr-ram/README.rst b/snippets/nordic-ppr-ram/README.rst deleted file mode 100644 index 501e5073357..00000000000 --- a/snippets/nordic-ppr-ram/README.rst +++ /dev/null @@ -1,11 +0,0 @@ -.. _nordic-ppr-ram: - -Nordic boot PPR snippet with execution from RAM (nordic-ppr-ram) -################################################################ - -Overview -******** - -This snippet allows users to build Zephyr with the capability to boot Nordic PPR -(Peripheral Processor) from another core. PPR code is executed from RAM. Note -that PPR image must be built with :kconfig:option:`CONFIG_XIP` disabled. diff --git a/snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay deleted file mode 100644 index ea866358fc0..00000000000 --- a/snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * SPDX-License-Identifier: Apache-2.0 - */ - -&cpuppr_code_data { - status = "okay"; -}; - -&cpuppr_vpr { - execution-memory = <&cpuppr_code_data>; -}; - -&uart135 { - status = "reserved"; -}; diff --git a/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay b/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay deleted file mode 100644 index 71c45c1b9f4..00000000000 --- a/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * SPDX-License-Identifier: Apache-2.0 - */ - -/* code is sourced from cpuppr code partition */ -&cpuppr_vpr { - status = "okay"; - source-memory = <&cpuppr_code_partition>; -}; - -/* code partition size must match RAM size */ -&cpuppr_code_partition { - reg = <0x126000 DT_SIZE_K(62)>; -}; diff --git a/snippets/nordic-ppr-ram/snippet.yml b/snippets/nordic-ppr-ram/snippet.yml deleted file mode 100644 index 2919e466393..00000000000 --- a/snippets/nordic-ppr-ram/snippet.yml +++ /dev/null @@ -1,8 +0,0 @@ -name: nordic-ppr-ram -append: - EXTRA_DTC_OVERLAY_FILE: nordic-ppr-ram.overlay - -boards: - nrf54h20dk/nrf54h20/cpuapp: - append: - EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay From 74f9f866f2385c426437d698eb9bea0ea590f121 Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Thu, 14 Mar 2024 08:39:39 +0100 Subject: [PATCH 0894/2402] snippets: Add nordic-ppr-xip This replacement for the `nordic-ppr-ram` snippet does the opposite: enable PPR execution in place from MRAM. Signed-off-by: Grzegorz Swiderski --- snippets/nordic-ppr-xip/README.rst | 12 ++++++++++++ .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 17 +++++++++++++++++ snippets/nordic-ppr-xip/nordic-ppr-xip.overlay | 8 ++++++++ snippets/nordic-ppr-xip/snippet.yml | 8 ++++++++ 4 files changed, 45 insertions(+) create mode 100644 snippets/nordic-ppr-xip/README.rst create mode 100644 snippets/nordic-ppr-xip/boards/nrf54h20dk_nrf54h20_cpuapp.overlay create mode 100644 snippets/nordic-ppr-xip/nordic-ppr-xip.overlay create mode 100644 snippets/nordic-ppr-xip/snippet.yml diff --git a/snippets/nordic-ppr-xip/README.rst b/snippets/nordic-ppr-xip/README.rst new file mode 100644 index 00000000000..64977da2989 --- /dev/null +++ b/snippets/nordic-ppr-xip/README.rst @@ -0,0 +1,12 @@ +.. _nordic-ppr-xip: + +Nordic boot PPR snippet with execution in place (nordic-ppr-xip) +################################################################ + +Overview +******** + +This snippet allows users to build Zephyr with the capability to boot Nordic PPR +(Peripheral Processor) from another core. PPR code is to be executed from MRAM, +so the PPR image must be built for the ``xip`` board variant, or with +:kconfig:option:`CONFIG_XIP` enabled. diff --git a/snippets/nordic-ppr-xip/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/snippets/nordic-ppr-xip/boards/nrf54h20dk_nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..4d02921660b --- /dev/null +++ b/snippets/nordic-ppr-xip/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&cpuppr_ram3x_region { + status = "okay"; +}; + +&cpuppr_vpr { + execution-memory = <&cpuppr_code_partition>; + /delete-property/ source-memory; +}; + +&uart135 { + status = "reserved"; +}; diff --git a/snippets/nordic-ppr-xip/nordic-ppr-xip.overlay b/snippets/nordic-ppr-xip/nordic-ppr-xip.overlay new file mode 100644 index 00000000000..e33885fc10d --- /dev/null +++ b/snippets/nordic-ppr-xip/nordic-ppr-xip.overlay @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&cpuppr_vpr { + status = "okay"; +}; diff --git a/snippets/nordic-ppr-xip/snippet.yml b/snippets/nordic-ppr-xip/snippet.yml new file mode 100644 index 00000000000..4fa136b20e2 --- /dev/null +++ b/snippets/nordic-ppr-xip/snippet.yml @@ -0,0 +1,8 @@ +name: nordic-ppr-xip +append: + EXTRA_DTC_OVERLAY_FILE: nordic-ppr-xip.overlay + +boards: + nrf54h20dk/nrf54h20/cpuapp: + append: + EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay From eb9c57868f7fda380828604bcad34e435704fdd8 Mon Sep 17 00:00:00 2001 From: Pisit Sawangvonganan Date: Sat, 16 Mar 2024 16:36:36 +0700 Subject: [PATCH 0895/2402] drivers: mdio: fix incorrect return usage in `mdio_bus_enable/disable` Remove incorrect return statements in the `z_impl_mdio_bus_enable` and `z_impl_mdio_bus_disable` functions within the MDIO driver API. These functions are intended to call the `bus_enable` and `bus_disable` methods of the MDIO driver API without returning a value, as they are defined to return void. Signed-off-by: Pisit Sawangvonganan --- include/zephyr/drivers/mdio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/zephyr/drivers/mdio.h b/include/zephyr/drivers/mdio.h index 9ee8deebd41..687064acae3 100644 --- a/include/zephyr/drivers/mdio.h +++ b/include/zephyr/drivers/mdio.h @@ -73,7 +73,7 @@ static inline void z_impl_mdio_bus_enable(const struct device *dev) const struct mdio_driver_api *api = (const struct mdio_driver_api *)dev->api; - return api->bus_enable(dev); + api->bus_enable(dev); } /** @@ -89,7 +89,7 @@ static inline void z_impl_mdio_bus_disable(const struct device *dev) const struct mdio_driver_api *api = (const struct mdio_driver_api *)dev->api; - return api->bus_disable(dev); + api->bus_disable(dev); } /** From 731ba72423481fbc8e9f0b5bdf321423bad82bb3 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 16:28:30 +0100 Subject: [PATCH 0896/2402] tests/bsim: Reorder tests to avoid failure in GATT/SR/GAS/BV-01-C GATT/SR/GAS/BV-01-C has just broken due to what appears like a minor timing change. This indicates the test may be too time sensitive. Just reordering the tests, it passes again. So let's reorder the test list, and we get the minor benefit of havign them move alphabetically ordered. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/bluetooth/ll/edtt/tests_scripts/gatt.llcp.test_list | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/bsim/bluetooth/ll/edtt/tests_scripts/gatt.llcp.test_list b/tests/bsim/bluetooth/ll/edtt/tests_scripts/gatt.llcp.test_list index 8736cd5b6e4..d606038298c 100644 --- a/tests/bsim/bluetooth/ll/edtt/tests_scripts/gatt.llcp.test_list +++ b/tests/bsim/bluetooth/ll/edtt/tests_scripts/gatt.llcp.test_list @@ -37,6 +37,7 @@ GATT/SR/GAR/BI-21-C #GATT/SR/GAR/BI-22-C https://github.com/EDTTool/EDTT/issues/82 GATT/SR/GAR/BV-06-C GATT/SR/GAR/BV-07-C +GATT/SR/GAS/BV-01-C GATT/SR/GAW/BV-01-C GATT/SR/GAW/BV-03-C GATT/SR/GAW/BI-02-C @@ -58,7 +59,6 @@ GATT/SR/GAW/BI-32-C GATT/SR/GAW/BI-33-C GATT/SR/GAN/BV-01-C GATT/SR/GAI/BV-01-C -GATT/SR/GAS/BV-01-C GATT/SR/UNS/BI-01-C GATT/SR/UNS/BI-02-C GATT/SR/GPA/BV-01-C From 337769c7dbb2f95710d23cef1ad2f40cbf8baf2c Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 15 Mar 2024 16:54:15 +0100 Subject: [PATCH 0897/2402] tests/drivers/build_all/w1: Run on native_sim instead of native_posix native_posix is being replaced with native_sim, let's have these tests be run on native_sim instead. Signed-off-by: Alberto Escolar Piedras --- tests/drivers/build_all/w1/testcase.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/drivers/build_all/w1/testcase.yaml b/tests/drivers/build_all/w1/testcase.yaml index f1ddfc682dd..23134ad3d1d 100644 --- a/tests/drivers/build_all/w1/testcase.yaml +++ b/tests/drivers/build_all/w1/testcase.yaml @@ -10,4 +10,4 @@ tests: depends_on: - gpio integration_platforms: - - native_posix + - native_sim From 3fd545b05b45ec62a67b426ce809c804c86b8593 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Mon, 18 Mar 2024 16:57:28 +0100 Subject: [PATCH 0898/2402] mgmt: hawkbit: Fix condition in hawkbit_probe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix send_request condition in hawkbit_probe function Signed-off-by: Fin Maaß --- subsys/mgmt/hawkbit/hawkbit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c index 0d12474f380..296039b5018 100644 --- a/subsys/mgmt/hawkbit/hawkbit.c +++ b/subsys/mgmt/hawkbit/hawkbit.c @@ -1147,7 +1147,7 @@ enum hawkbit_response hawkbit_probe(void) flash_img_init(&hb_context.flash_ctx); - if (send_request(HTTP_GET, HAWKBIT_DOWNLOAD, HAWKBIT_STATUS_FINISHED_NONE, + if (!send_request(HTTP_GET, HAWKBIT_DOWNLOAD, HAWKBIT_STATUS_FINISHED_NONE, HAWKBIT_STATUS_EXEC_NONE)) { LOG_ERR("Send request failed (%s)", "HAWKBIT_DOWNLOAD"); hb_context.code_status = HAWKBIT_NETWORKING_ERROR; From 1408d1e5b8cefcb0f4d52c1ffb41849f70826f39 Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Sun, 10 Mar 2024 01:09:07 +0000 Subject: [PATCH 0899/2402] tests: llext: compile architectures not supported yet For now llext supports a very limited number of architectures. This restriction is enforced by add_llext_target() in CMake at configuration time. Add a new `LOADER_BUILD_ONLY` conditional in tests/subsys/llext/simple/ and a new `llext.simple.loader_build`, `build_only` test that does not invoke `add_llext_target()` and only compiles the llext framework code. This helps find and fix bugs in `subsys/llext/*.c` and make it ready to be used when add_llext_target() limitations are lifted. Note this is pure `tests/` change without any change in the actual llext framework code. The existing test is only modified to conditionally invoke add_llext_target(). Signed-off-by: Marc Herbert --- tests/subsys/llext/simple/CMakeLists.txt | 2 ++ .../llext/simple/src/test_llext_simple.c | 3 +++ tests/subsys/llext/simple/testcase.yaml | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+) diff --git a/tests/subsys/llext/simple/CMakeLists.txt b/tests/subsys/llext/simple/CMakeLists.txt index 4a9f311d8fa..87a71554ba4 100644 --- a/tests/subsys/llext/simple/CMakeLists.txt +++ b/tests/subsys/llext/simple/CMakeLists.txt @@ -15,6 +15,7 @@ target_include_directories(app PRIVATE ${ZEPHYR_BASE}/arch/${ARCH}/include ) +if(NOT LOADER_BUILD_ONLY) # generate extension targets foreach extension given by name foreach(ext_name hello_world logging relative_jump object) set(ext_src ${PROJECT_SOURCE_DIR}/src/${ext_name}_ext.c) @@ -26,3 +27,4 @@ foreach(ext_name hello_world logging relative_jump object) ) generate_inc_file_for_target(app ${ext_bin} ${ext_inc}) endforeach() +endif() diff --git a/tests/subsys/llext/simple/src/test_llext_simple.c b/tests/subsys/llext/simple/src/test_llext_simple.c index dcb31ac9e4a..6f92951dd56 100644 --- a/tests/subsys/llext/simple/src/test_llext_simple.c +++ b/tests/subsys/llext/simple/src/test_llext_simple.c @@ -120,6 +120,8 @@ void load_call_unload(struct llext_test *test_case) llext_unload(&ext); } + +#ifndef LOADER_BUILD_ONLY /* * Attempt to load, list, list symbols, call a fn, and unload each * extension in the test table. This excercises loading, calling into, and @@ -151,6 +153,7 @@ static LLEXT_CONST uint8_t relative_jump_ext[] __aligned(4) = { #include "relative_jump.inc" }; LLEXT_LOAD_UNLOAD(relative_jump, true) +#endif /* ! LOADER_BUILD_ONLY */ static LLEXT_CONST uint8_t object_ext[] __aligned(4) = { #include "object.inc" diff --git a/tests/subsys/llext/simple/testcase.yaml b/tests/subsys/llext/simple/testcase.yaml index bd683e2d3b0..2a90bd1fadb 100644 --- a/tests/subsys/llext/simple/testcase.yaml +++ b/tests/subsys/llext/simple/testcase.yaml @@ -6,7 +6,25 @@ common: platform_exclude: - numaker_pfm_m487 # See #63167 - qemu_cortex_r5 # unsupported relocations + tests: + # add_llext_target() supports a fairly limited number of + # CONFIG_urations. For instance, invoking add_llext_target() + # currently blocks us from compiling subsys/llext/*.c in 64bits mode; + # CMake aborts before even invoking the compiler. + # + # While there is in practice no value in compiling subsys/llext/*.c + # without actually running it to load some extension, let's keep it in + # good shape and ready to be used when add_llext_target() + # limitations get lifted in the future. + llext.simple.loader_build: + build_only: true + # How to override the above and allow ANY arch? + arch_allow: arm arm64 x86 x86_64 xtensa posix + extra_args: + - LOADER_BUILD_ONLY=1 + - EXTRA_CFLAGS=-DLOADER_BUILD_ONLY=1 + llext.simple.readonly: arch_exclude: xtensa # for now filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE From 6a0c38680f615aa03a4531c1457f36c4d0a1ea54 Mon Sep 17 00:00:00 2001 From: Fengming Ye Date: Fri, 15 Mar 2024 14:46:14 +0900 Subject: [PATCH 0900/2402] net: ipv6: fix link local ping fail with default router When we receive Router Advertisement with life time, we will add this as default router, like typing command "net iface" and has show below IPv6 default router : fe80:xxxx::xxxx When this default router is backend A and we ping backend B with link local address, we will use default router A and send echo request to backend A instead of B, which will receive Redirect and no reply. Fix it by link local address does not check route. Signed-off-by: Fengming Ye --- subsys/net/ip/ipv6_nbr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/subsys/net/ip/ipv6_nbr.c b/subsys/net/ip/ipv6_nbr.c index 992078062f0..a2da488a4f7 100644 --- a/subsys/net/ip/ipv6_nbr.c +++ b/subsys/net/ip/ipv6_nbr.c @@ -866,6 +866,8 @@ enum net_verdict net_ipv6_prepare_for_send(struct net_pkt *pkt) if (net_if_ipv6_addr_onlink(&iface, (struct in6_addr *)ip_hdr->dst)) { nexthop = (struct in6_addr *)ip_hdr->dst; net_pkt_set_iface(pkt, iface); + } else if (net_ipv6_is_ll_addr((struct in6_addr *)ip_hdr->dst)) { + nexthop = (struct in6_addr *)ip_hdr->dst; } else { /* We need to figure out where the destination * host is located. From 816a1381fa553fca48c99bec2da315d2a0982e6f Mon Sep 17 00:00:00 2001 From: Savin Weeraratne Date: Fri, 15 Mar 2024 19:35:45 +1100 Subject: [PATCH 0901/2402] net: ipv4: Allow IGMP packets with zero src address IGMP queries sent out by a proxy querier can have a source IP address 0.0.0.0 Allow these incoming packets. Fixes #69917 Signed-off-by: Savin Weeraratne --- subsys/net/ip/ipv4.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/subsys/net/ip/ipv4.c b/subsys/net/ip/ipv4.c index b637fb5e5e0..cf318b1416d 100644 --- a/subsys/net/ip/ipv4.c +++ b/subsys/net/ip/ipv4.c @@ -317,7 +317,8 @@ enum net_verdict net_ipv4_input(struct net_pkt *pkt, bool is_loopback) } if (net_ipv4_is_addr_unspecified((struct in_addr *)hdr->src) && - !net_ipv4_is_addr_bcast(net_pkt_iface(pkt), (struct in_addr *)hdr->dst)) { + !net_ipv4_is_addr_bcast(net_pkt_iface(pkt), (struct in_addr *)hdr->dst) && + (hdr->proto != IPPROTO_IGMP)) { NET_DBG("DROP: src addr is %s", "unspecified"); goto drop; } From 62ac753a6148b7b5e381bd86f72174b82b2d99c5 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 15 Mar 2024 00:02:43 +0100 Subject: [PATCH 0902/2402] Bluetooth: CAP: Fix issue with codec_cfg in CAP uni start The codecs used for the bap bt_bap_stream_config was only valid for the lifetime of the procedure, which meant that by the end of the procedure the stream->codec_cfg became invalid. This is fixed by using the pointer provided to the CAP API, and documentating the lifetime of the codec_cfg. Signed-off-by: Emil Gydesen --- include/zephyr/bluetooth/audio/cap.h | 3 +++ subsys/bluetooth/audio/cap_initiator.c | 7 +++---- subsys/bluetooth/audio/cap_internal.h | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/zephyr/bluetooth/audio/cap.h b/include/zephyr/bluetooth/audio/cap.h index 61f1a875e42..35a30f742ac 100644 --- a/include/zephyr/bluetooth/audio/cap.h +++ b/include/zephyr/bluetooth/audio/cap.h @@ -226,6 +226,9 @@ struct bt_cap_unicast_audio_start_stream_param { * The @p codec_cfg.meta shall include a list of CCIDs * (@ref BT_AUDIO_METADATA_TYPE_CCID_LIST) as well as a non-0 * stream context (@ref BT_AUDIO_METADATA_TYPE_STREAM_CONTEXT) bitfield. + * + * This value is assigned to the @p stream, and shall remain valid while the stream is + * non-idle. */ struct bt_audio_codec_cfg *codec_cfg; }; diff --git a/subsys/bluetooth/audio/cap_initiator.c b/subsys/bluetooth/audio/cap_initiator.c index b6923bc0e4e..cd57f97e11c 100644 --- a/subsys/bluetooth/audio/cap_initiator.c +++ b/subsys/bluetooth/audio/cap_initiator.c @@ -507,8 +507,7 @@ static int cap_initiator_unicast_audio_configure( active_proc->proc_param.initiator[i].stream = cap_stream; active_proc->proc_param.initiator[i].start.ep = stream_param->ep; active_proc->proc_param.initiator[i].start.conn = conn; - memcpy(&active_proc->proc_param.initiator[i].start.codec_cfg, - stream_param->codec_cfg, sizeof(*stream_param->codec_cfg)); + active_proc->proc_param.initiator[i].start.codec_cfg = stream_param->codec_cfg; } /* Store the information about the active procedure so that we can @@ -519,7 +518,7 @@ static int cap_initiator_unicast_audio_configure( proc_param = &active_proc->proc_param.initiator[0]; bap_stream = &proc_param->stream->bap_stream; - codec_cfg = &proc_param->start.codec_cfg; + codec_cfg = proc_param->start.codec_cfg; conn = proc_param->start.conn; ep = proc_param->start.ep; active_proc->proc_initiated_cnt++; @@ -603,7 +602,7 @@ void bt_cap_initiator_codec_configured(struct bt_cap_stream *cap_stream) next_cap_stream = proc_param->stream; conn = proc_param->start.conn; ep = proc_param->start.ep; - codec_cfg = &proc_param->start.codec_cfg; + codec_cfg = proc_param->start.codec_cfg; bap_stream = &next_cap_stream->bap_stream; active_proc->proc_initiated_cnt++; diff --git a/subsys/bluetooth/audio/cap_internal.h b/subsys/bluetooth/audio/cap_internal.h index 4fba04f6568..2c56ef1f742 100644 --- a/subsys/bluetooth/audio/cap_internal.h +++ b/subsys/bluetooth/audio/cap_internal.h @@ -59,7 +59,7 @@ struct bt_cap_initiator_proc_param { struct { struct bt_conn *conn; struct bt_bap_ep *ep; - struct bt_audio_codec_cfg codec_cfg; + struct bt_audio_codec_cfg *codec_cfg; } start; struct { /** Codec Specific Capabilities Metadata count */ From 8ccccbbb880f77792d3476373c75613def462910 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Tue, 12 Mar 2024 13:45:35 +0100 Subject: [PATCH 0903/2402] tests: drivers: can: move min/max timing tests to API test suite Move the test for setting the minimum/maximum supported timing parameters from the CAN timing tests to the CAN API tests as these are validating basic API behavior. Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/api/src/canfd.c | 34 +++++++++++++++ tests/drivers/can/api/src/classic.c | 34 +++++++++++++++ tests/drivers/can/timing/src/main.c | 64 ----------------------------- 3 files changed, 68 insertions(+), 64 deletions(-) diff --git a/tests/drivers/can/api/src/canfd.c b/tests/drivers/can/api/src/canfd.c index 4a7f3704e19..6caf72e5568 100644 --- a/tests/drivers/can/api/src/canfd.c +++ b/tests/drivers/can/api/src/canfd.c @@ -375,6 +375,40 @@ ZTEST_USER(canfd, test_filters_preserved_through_fd_to_classic_mode_change) check_filters_preserved_between_modes(CAN_MODE_FD, CAN_MODE_NORMAL); } +/** + * @brief Test that the minimum timing values for the data phase can be set. + */ +ZTEST_USER(canfd, test_set_timing_data_min) +{ + int err; + + err = can_stop(can_dev); + zassert_equal(err, 0, "failed to stop CAN controller (err %d)", err); + + err = can_set_timing_data(can_dev, can_get_timing_data_min(can_dev)); + zassert_equal(err, 0, "failed to set minimum timing data parameters (err %d)", err); + + err = can_start(can_dev); + zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); +} + +/** + * @brief Test that the maximum timing values for the data phase can be set. + */ +ZTEST_USER(canfd, test_set_timing_data_max) +{ + int err; + + err = can_stop(can_dev); + zassert_equal(err, 0, "failed to stop CAN controller (err %d)", err); + + err = can_set_timing_data(can_dev, can_get_timing_data_max(can_dev)); + zassert_equal(err, 0, "failed to set maximum timing data parameters (err %d)", err); + + err = can_start(can_dev); + zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); +} + /** * @brief Test setting data phase bitrate is not allowed while started. */ diff --git a/tests/drivers/can/api/src/classic.c b/tests/drivers/can/api/src/classic.c index 0edfda98015..097dc53dec8 100644 --- a/tests/drivers/can/api/src/classic.c +++ b/tests/drivers/can/api/src/classic.c @@ -540,6 +540,40 @@ ZTEST_USER(can_classic, test_set_bitrate) zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); } +/** + * @brief Test that the minimum timing values can be set. + */ +ZTEST_USER(can_classic, test_set_timing_min) +{ + int err; + + err = can_stop(can_dev); + zassert_equal(err, 0, "failed to stop CAN controller (err %d)", err); + + err = can_set_timing(can_dev, can_get_timing_min(can_dev)); + zassert_equal(err, 0, "failed to set minimum timing parameters (err %d)", err); + + err = can_start(can_dev); + zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); +} + +/** + * @brief Test that the maximum timing values can be set. + */ +ZTEST_USER(can_classic, test_set_timing_max) +{ + int err; + + err = can_stop(can_dev); + zassert_equal(err, 0, "failed to stop CAN controller (err %d)", err); + + err = can_set_timing(can_dev, can_get_timing_max(can_dev)); + zassert_equal(err, 0, "failed to set maximum timing parameters (err %d)", err); + + err = can_start(can_dev); + zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); +} + /** * @brief Test sending a message with no filters installed. * diff --git a/tests/drivers/can/timing/src/main.c b/tests/drivers/can/timing/src/main.c index 3aa21ee848f..956d673015f 100644 --- a/tests/drivers/can/timing/src/main.c +++ b/tests/drivers/can/timing/src/main.c @@ -244,70 +244,6 @@ ZTEST_USER(can_timing, test_timing_data) } } -/** - * @brief Test that the minimum timing values can be set. - */ -ZTEST_USER(can_timing, test_set_timing_min) -{ - const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); - int err; - - err = can_set_timing(dev, can_get_timing_min(dev)); - zassert_equal(err, 0, "failed to set minimum timing parameters (err %d)", err); -} - -/** - * @brief Test that the minimum timing values for the data phase can be set. - */ -ZTEST_USER(can_timing, test_set_timing_data_min) -{ - const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); - can_mode_t cap; - int err; - - err = can_get_capabilities(dev, &cap); - zassert_equal(err, 0, "failed to get CAN controller capabilities (err %d)", err); - - if ((cap & CAN_MODE_FD) == 0) { - ztest_test_skip(); - } - - err = can_set_timing_data(dev, can_get_timing_data_min(dev)); - zassert_equal(err, 0, "failed to set minimum timing data parameters (err %d)", err); -} - -/** - * @brief Test that the maximum timing values can be set. - */ -ZTEST_USER(can_timing, test_set_timing_max) -{ - const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); - int err; - - err = can_set_timing(dev, can_get_timing_max(dev)); - zassert_equal(err, 0, "failed to set maximum timing parameters (err %d)", err); -} - -/** - * @brief Test that the maximum timing values for the data phase can be set. - */ -ZTEST_USER(can_timing, test_set_timing_data_max) -{ - const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); - can_mode_t cap; - int err; - - err = can_get_capabilities(dev, &cap); - zassert_equal(err, 0, "failed to get CAN controller capabilities (err %d)", err); - - if ((cap & CAN_MODE_FD) == 0) { - ztest_test_skip(); - } - - err = can_set_timing_data(dev, can_get_timing_data_max(dev)); - zassert_equal(err, 0, "failed to set maximum timing data parameters (err %d)", err); -} - void *can_timing_setup(void) { const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); From fa00a73e765f20259b9d9c96da5334b3c4496215 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Tue, 12 Mar 2024 14:04:25 +0100 Subject: [PATCH 0904/2402] tests: drivers: can: move tests for too high bitrates to API test suite Move the tests for setting a too high bitrate from the CAN timing tests to the CAN API tests as these are validating basic API behavior. Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/api/src/canfd.c | 26 ++++++++++++++++++++++++++ tests/drivers/can/api/src/classic.c | 14 +++++++------- tests/drivers/can/timing/src/main.c | 4 ---- 3 files changed, 33 insertions(+), 11 deletions(-) diff --git a/tests/drivers/can/api/src/canfd.c b/tests/drivers/can/api/src/canfd.c index 6caf72e5568..a2c01a28869 100644 --- a/tests/drivers/can/api/src/canfd.c +++ b/tests/drivers/can/api/src/canfd.c @@ -392,6 +392,32 @@ ZTEST_USER(canfd, test_set_timing_data_min) zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); } +/** + * @brief Test setting a too high data phase bitrate. + */ +ZTEST_USER(canfd, test_set_bitrate_too_high) +{ + uint32_t max = 8000000U; + int expected = -EINVAL; + int err; + + err = can_get_max_bitrate(can_dev, &max); + if (err != -ENOSYS) { + zassert_equal(err, 0, "failed to get max bitrate (err %d)", err); + zassert_not_equal(max, 0, "max bitrate is 0"); + expected = -ENOTSUP; + } + + err = can_stop(can_dev); + zassert_equal(err, 0, "failed to stop CAN controller (err %d)", err); + + err = can_set_bitrate_data(can_dev, max + 1); + zassert_equal(err, expected, "too high data phase bitrate accepted"); + + err = can_start(can_dev); + zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); +} + /** * @brief Test that the maximum timing values for the data phase can be set. */ diff --git a/tests/drivers/can/api/src/classic.c b/tests/drivers/can/api/src/classic.c index 097dc53dec8..f40aff2e431 100644 --- a/tests/drivers/can/api/src/classic.c +++ b/tests/drivers/can/api/src/classic.c @@ -502,22 +502,22 @@ ZTEST_USER(can_classic, test_bitrate_limits) */ ZTEST_USER(can_classic, test_set_bitrate_too_high) { - uint32_t max = 0U; + uint32_t max = 1000000U; + int expected = -EINVAL; int err; err = can_get_max_bitrate(can_dev, &max); - if (err == -ENOSYS) { - ztest_test_skip(); + if (err != -ENOSYS) { + zassert_equal(err, 0, "failed to get max bitrate (err %d)", err); + zassert_not_equal(max, 0, "max bitrate is 0"); + expected = -ENOTSUP; } - zassert_equal(err, 0, "failed to get max bitrate (err %d)", err); - zassert_not_equal(max, 0, "max bitrate is 0"); - err = can_stop(can_dev); zassert_equal(err, 0, "failed to stop CAN controller (err %d)", err); err = can_set_bitrate(can_dev, max + 1); - zassert_equal(err, -ENOTSUP, "too high bitrate accepted"); + zassert_equal(err, expected, "too high bitrate accepted"); err = can_start(can_dev); zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); diff --git a/tests/drivers/can/timing/src/main.c b/tests/drivers/can/timing/src/main.c index 956d673015f..4300ec2e4af 100644 --- a/tests/drivers/can/timing/src/main.c +++ b/tests/drivers/can/timing/src/main.c @@ -50,8 +50,6 @@ static const struct can_timing_test can_timing_tests[] = { { 125000, 800, false }, /** Valid bitrate, invalid sample point. */ { 125000, 1000, true }, - /** Invalid classic/arbitration bitrate, valid sample point. */ - { 1000000 + 1, 750, true }, }; /** @@ -67,8 +65,6 @@ static const struct can_timing_test can_timing_data_tests[] = { { 500000, 800, false }, /** Valid bitrate, invalid sample point. */ { 500000, 1000, true }, - /** Invalid CAN FD bitrate, valid sample point. */ - { 8000000 + 1, 750, true }, }; #endif /* CONFIG_CAN_FD_MODE */ From d0ec48cb60f8d70528183ac0b24e97b09230fbf9 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Wed, 13 Mar 2024 09:51:11 +0100 Subject: [PATCH 0905/2402] tests: drivers: can: move tests for invalid sample points to API test suite Move the tests for using invalid sample points from the CAN timing tests to the CAN API tests as these are validating basic API behavior. Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/api/src/canfd.c | 12 ++++++++++++ tests/drivers/can/api/src/classic.c | 12 ++++++++++++ tests/drivers/can/timing/src/main.c | 4 ---- 3 files changed, 24 insertions(+), 4 deletions(-) diff --git a/tests/drivers/can/api/src/canfd.c b/tests/drivers/can/api/src/canfd.c index a2c01a28869..ec881b07343 100644 --- a/tests/drivers/can/api/src/canfd.c +++ b/tests/drivers/can/api/src/canfd.c @@ -418,6 +418,18 @@ ZTEST_USER(canfd, test_set_bitrate_too_high) zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); } +/** + * @brief Test using an invalid sample point. + */ +ZTEST_USER(canfd, test_invalid_sample_point) +{ + struct can_timing timing; + int err; + + err = can_calc_timing_data(can_dev, &timing, TEST_BITRATE_3, 1000); + zassert_equal(err, -EINVAL, "invalid sample point of 100.0% accepted (err %d)", err); +} + /** * @brief Test that the maximum timing values for the data phase can be set. */ diff --git a/tests/drivers/can/api/src/classic.c b/tests/drivers/can/api/src/classic.c index f40aff2e431..c59e3466774 100644 --- a/tests/drivers/can/api/src/classic.c +++ b/tests/drivers/can/api/src/classic.c @@ -523,6 +523,18 @@ ZTEST_USER(can_classic, test_set_bitrate_too_high) zassert_equal(err, 0, "failed to start CAN controller (err %d)", err); } +/** + * @brief Test using an invalid sample point. + */ +ZTEST_USER(can_classic, test_invalid_sample_point) +{ + struct can_timing timing; + int err; + + err = can_calc_timing(can_dev, &timing, TEST_BITRATE_1, 1000); + zassert_equal(err, -EINVAL, "invalid sample point of 100.0% accepted (err %d)", err); +} + /** * @brief Test setting bitrate. */ diff --git a/tests/drivers/can/timing/src/main.c b/tests/drivers/can/timing/src/main.c index 4300ec2e4af..252cbbb36d7 100644 --- a/tests/drivers/can/timing/src/main.c +++ b/tests/drivers/can/timing/src/main.c @@ -48,8 +48,6 @@ static const struct can_timing_test can_timing_tests[] = { /** Additional, valid sample points. */ { 125000, 900, false }, { 125000, 800, false }, - /** Valid bitrate, invalid sample point. */ - { 125000, 1000, true }, }; /** @@ -63,8 +61,6 @@ static const struct can_timing_test can_timing_data_tests[] = { /** Additional, valid sample points. */ { 500000, 900, false }, { 500000, 800, false }, - /** Valid bitrate, invalid sample point. */ - { 500000, 1000, true }, }; #endif /* CONFIG_CAN_FD_MODE */ From 675ce0d255ea3d4d88559ab5c349f586c1f5085a Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Wed, 13 Mar 2024 09:54:25 +0100 Subject: [PATCH 0906/2402] tests: drivers: can: timing: remove support for invalid test configs Remove now unused support for specifying invalid timing test configurations. Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/timing/src/main.c | 37 +++++++++++++---------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/tests/drivers/can/timing/src/main.c b/tests/drivers/can/timing/src/main.c index 252cbbb36d7..2aab917a69f 100644 --- a/tests/drivers/can/timing/src/main.c +++ b/tests/drivers/can/timing/src/main.c @@ -29,8 +29,6 @@ struct can_timing_test { uint32_t bitrate; /** Desired sample point in permille */ uint16_t sp; - /** Do these values represent an invalid CAN timing? */ - bool invalid; }; /** @@ -38,16 +36,16 @@ struct can_timing_test { */ static const struct can_timing_test can_timing_tests[] = { /** Standard bitrates. */ - { 20000, 875, false }, - { 50000, 875, false }, - { 125000, 875, false }, - { 250000, 875, false }, - { 500000, 875, false }, - { 800000, 800, false }, - { 1000000, 750, false }, + { 20000, 875 }, + { 50000, 875 }, + { 125000, 875 }, + { 250000, 875 }, + { 500000, 875 }, + { 800000, 800 }, + { 1000000, 750 }, /** Additional, valid sample points. */ - { 125000, 900, false }, - { 125000, 800, false }, + { 125000, 900 }, + { 125000, 800 }, }; /** @@ -56,11 +54,11 @@ static const struct can_timing_test can_timing_tests[] = { #ifdef CONFIG_CAN_FD_MODE static const struct can_timing_test can_timing_data_tests[] = { /** Standard bitrates. */ - { 500000, 875, false }, - { 1000000, 750, false }, + { 500000, 875 }, + { 1000000, 750 }, /** Additional, valid sample points. */ - { 500000, 900, false }, - { 500000, 800, false }, + { 500000, 900 }, + { 500000, 800 }, }; #endif /* CONFIG_CAN_FD_MODE */ @@ -155,8 +153,8 @@ static void test_timing_values(const struct device *dev, const struct can_timing int sp_err; int err; - printk("testing bitrate %u, sample point %u.%u%% (%s): ", - test->bitrate, test->sp / 10, test->sp % 10, test->invalid ? "invalid" : "valid"); + printk("testing bitrate %u, sample point %u.%u%%: ", + test->bitrate, test->sp / 10, test->sp % 10); if (data_phase) { if (IS_ENABLED(CONFIG_CAN_FD_MODE)) { @@ -172,10 +170,7 @@ static void test_timing_values(const struct device *dev, const struct can_timing sp_err = can_calc_timing(dev, &timing, test->bitrate, test->sp); } - if (test->invalid) { - zassert_equal(sp_err, -EINVAL, "err %d, expected -EINVAL", sp_err); - printk("OK\n"); - } else if (sp_err == -ENOTSUP) { + if (sp_err == -ENOTSUP) { printk("bitrate not supported\n"); } else { zassert_true(sp_err >= 0, "unknown error %d", sp_err); From f9dc6f7d132db44470752b5bf22717d662d11170 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Thu, 14 Mar 2024 12:17:28 +0100 Subject: [PATCH 0907/2402] tests: drivers: can: timing: do not test additional sample points Remove tests for additional sample points as this does not provide any real value. The purpose of this test suite is to see if the selected CAN clock allows meeting the standard bitrates and sample points used by Zephyr. Any tweaking needed for a specific board or system design is left up to the user and not something that can be covered by testing a few additional sample point locations. Change a few comments and remove an unneeded conditional while here. Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/timing/src/main.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/tests/drivers/can/timing/src/main.c b/tests/drivers/can/timing/src/main.c index 2aab917a69f..8f33dc0a008 100644 --- a/tests/drivers/can/timing/src/main.c +++ b/tests/drivers/can/timing/src/main.c @@ -25,7 +25,7 @@ * @brief Defines a set of CAN timing test values */ struct can_timing_test { - /** Desired bitrate in bits/s */ + /** Bitrate in bit/s */ uint32_t bitrate; /** Desired sample point in permille */ uint16_t sp; @@ -43,24 +43,16 @@ static const struct can_timing_test can_timing_tests[] = { { 500000, 875 }, { 800000, 800 }, { 1000000, 750 }, - /** Additional, valid sample points. */ - { 125000, 900 }, - { 125000, 800 }, }; /** - * @brief List of CAN timing values to test for the data phase. + * @brief List of CAN FD data phase timing values to test. */ -#ifdef CONFIG_CAN_FD_MODE static const struct can_timing_test can_timing_data_tests[] = { /** Standard bitrates. */ { 500000, 875 }, { 1000000, 750 }, - /** Additional, valid sample points. */ - { 500000, 900 }, - { 500000, 800 }, }; -#endif /* CONFIG_CAN_FD_MODE */ /** * @brief Assert that a CAN timing struct matches the specified bitrate @@ -70,7 +62,7 @@ static const struct can_timing_test can_timing_data_tests[] = { * * @param dev pointer to the device structure for the driver instance * @param timing pointer to the CAN timing struct - * @param bitrate the CAN bitrate in bits/s + * @param bitrate the CAN bitrate in bit/s */ static void assert_bitrate_correct(const struct device *dev, struct can_timing *timing, uint32_t bitrate) From 9f174ec4529a2211cb1b06b11bd230970dfebe2f Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Thu, 14 Mar 2024 12:28:30 +0100 Subject: [PATCH 0908/2402] tests: drivers: can: timing: add tests for all CiA recommended bitrates Add tests for all CAN bitrates recommended by CAN in Automation (CiA). The newly added bitrate tests are guarded by new, local Kconfig option (CONFIG_TEST_ALL_BITRATES) to avoid breaking existing board tests. Some boards may need adjustments to their CAN core clock in order to pass the newly added tests. Once a board is confirmed to meet these additional checks, this Kconfig can be enabled for that board to avoid future regressions. Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/timing/Kconfig | 40 +++++++++++++++++++++++++++ tests/drivers/can/timing/src/main.c | 42 ++++++++++++++++++++++++++--- 2 files changed, 78 insertions(+), 4 deletions(-) create mode 100644 tests/drivers/can/timing/Kconfig diff --git a/tests/drivers/can/timing/Kconfig b/tests/drivers/can/timing/Kconfig new file mode 100644 index 00000000000..59a84c66fb1 --- /dev/null +++ b/tests/drivers/can/timing/Kconfig @@ -0,0 +1,40 @@ +# Copyright (c) 2024 Vestas Wind Systems A/S +# SPDX-License-Identifier: Apache-2.0 + +mainmenu "CAN timing test" + +config TEST_ALL_BITRATES + bool "Test all CAN in Automation (CiA) recommended bitrates" + help + Enable test of all bitrates recommended by CAN in Automation (CiA). Not all CAN + controllers can meet all of the bitrates listed below, and some board configurations may + impose limits on which bitrates can be met due to limitations in the CAN core clock + frequency selection. + + CiA 301 lists the following nominal bitrates as recommended: + - 10 kbit/s + - 20 kbit/s + - 50 kbit/s + - 125 kbit/s + - 250 kbit/s + - 500 kbit/s + - 800 kbit/s + - 1 Mbit/s + + CiA 601-2 lists the following exemplary CAN FD data phase bitrates: + - 1.0 Mbit/s + - 2.0 Mbit/s + - 4.0 Mbit/s + - 5.0 Mbit/s + - 8.0 Mbit/s + + CiA 601-3 recommends the following CAN FD core clock frequencies for good node + interoperability. The higher the frequency, the better: + - 20 MHz + - 40 MHz + - 80 MHz + + If this option is not enabled, the tests will be limited to a historical, safe set of CAN + bitrates. + +source "Kconfig.zephyr" diff --git a/tests/drivers/can/timing/src/main.c b/tests/drivers/can/timing/src/main.c index 8f33dc0a008..e50db686ee2 100644 --- a/tests/drivers/can/timing/src/main.c +++ b/tests/drivers/can/timing/src/main.c @@ -35,7 +35,10 @@ struct can_timing_test { * @brief List of CAN timing values to test. */ static const struct can_timing_test can_timing_tests[] = { - /** Standard bitrates. */ + /* CiA 301 recommended bitrates */ +#ifdef CONFIG_TEST_ALL_BITRATES + { 10000, 875 }, +#endif /* CONFIG_TEST_ALL_BITRATES */ { 20000, 875 }, { 50000, 875 }, { 125000, 875 }, @@ -49,9 +52,14 @@ static const struct can_timing_test can_timing_tests[] = { * @brief List of CAN FD data phase timing values to test. */ static const struct can_timing_test can_timing_data_tests[] = { - /** Standard bitrates. */ - { 500000, 875 }, + /* CiA 601-2 recommended data phase bitrates */ { 1000000, 750 }, +#ifdef CONFIG_TEST_ALL_BITRATES + { 2000000, 750 }, + { 4000000, 750 }, + { 5000000, 750 }, + { 8000000, 750 }, +#endif /* CONFIG_TEST_ALL_BITRATES */ }; /** @@ -230,13 +238,39 @@ void *can_timing_setup(void) int err; zassert_true(device_is_ready(dev), "CAN device not ready"); + k_object_access_grant(dev, k_current_get()); err = can_get_core_clock(dev, &core_clock); zassert_equal(err, 0, "failed to get core CAN clock"); printk("testing on device %s @ %u Hz\n", dev->name, core_clock); - k_object_access_grant(dev, k_current_get()); + if (IS_ENABLED(CONFIG_CAN_FD_MODE)) { + can_mode_t cap; + + err = can_get_capabilities(dev, &cap); + zassert_equal(err, 0, "failed to get CAN controller capabilities (err %d)", err); + + if ((cap & CAN_MODE_FD) != 0) { + switch (core_clock) { + case MHZ(20): + break; + case MHZ(40): + break; + case MHZ(80): + break; + default: + TC_PRINT("Warning: CiA 601-3 recommends a CAN FD core clock of " + "20, 40, or 80 MHz for good node interoperability\n"); + break; + } + } + } + + if (!IS_ENABLED(CONFIG_TEST_ALL_BITRATES)) { + TC_PRINT("Warning: Testing limited selection of bitrates " + "(CONFIG_TEST_ALL_BITRATES=n)\n"); + } return NULL; } From cae4dd8e1aeaee64bdf76b366510ecf3f81e54fa Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Thu, 14 Mar 2024 12:35:28 +0100 Subject: [PATCH 0909/2402] tests: drivers: can: timing: assert at least one bitrate test supported Some CAN controllers may be unable to meet all bitrates due to timing restrictions, but assert that at least one of the tested bitrates was supported. Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/timing/src/main.c | 30 +++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/tests/drivers/can/timing/src/main.c b/tests/drivers/can/timing/src/main.c index e50db686ee2..8453e50f768 100644 --- a/tests/drivers/can/timing/src/main.c +++ b/tests/drivers/can/timing/src/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Vestas Wind Systems A/S + * Copyright (c) 2022-2024 Vestas Wind Systems A/S * Copyright (c) 2019 Alexander Wachter * * SPDX-License-Identifier: Apache-2.0 @@ -141,20 +141,21 @@ static void assert_sp_within_margin(struct can_timing *timing, uint16_t sp, uint * Test a set of CAN timing values on a specified CAN controller device * instance. * - * @param dev pointer to the device structure for the driver instance - * @param test pointer to the set of CAN timing values + * @param dev pointer to the device structure for the driver instance + * @param test pointer to the set of CAN timing values + * returns true if bitrate was supported, false otherwise */ -static void test_timing_values(const struct device *dev, const struct can_timing_test *test, +static bool test_timing_values(const struct device *dev, const struct can_timing_test *test, bool data_phase) { const struct can_timing *max = NULL; const struct can_timing *min = NULL; struct can_timing timing = { 0 }; - int sp_err; + int sp_err = -EINVAL; int err; printk("testing bitrate %u, sample point %u.%u%%: ", - test->bitrate, test->sp / 10, test->sp % 10); + test->bitrate, test->sp / 10, test->sp % 10); if (data_phase) { if (IS_ENABLED(CONFIG_CAN_FD_MODE)) { @@ -172,6 +173,7 @@ static void test_timing_values(const struct device *dev, const struct can_timing if (sp_err == -ENOTSUP) { printk("bitrate not supported\n"); + return false; } else { zassert_true(sp_err >= 0, "unknown error %d", sp_err); zassert_true(sp_err <= SAMPLE_POINT_MARGIN, "sample point error %d too large", @@ -194,6 +196,8 @@ static void test_timing_values(const struct device *dev, const struct can_timing printk("OK, sample point error %d.%d%%\n", sp_err / 10, sp_err % 10); } + + return true; } /** @@ -202,11 +206,16 @@ static void test_timing_values(const struct device *dev, const struct can_timing ZTEST_USER(can_timing, test_timing) { const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); + int count = 0; int i; for (i = 0; i < ARRAY_SIZE(can_timing_tests); i++) { - test_timing_values(dev, &can_timing_tests[i], false); + if (test_timing_values(dev, &can_timing_tests[i], false)) { + count++; + } } + + zassert_true(count > 0, "no bitrates supported"); } /** @@ -216,6 +225,7 @@ ZTEST_USER(can_timing, test_timing_data) { const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); can_mode_t cap; + int count = 0; int err; int i; @@ -227,8 +237,12 @@ ZTEST_USER(can_timing, test_timing_data) } for (i = 0; i < ARRAY_SIZE(can_timing_data_tests); i++) { - test_timing_values(dev, &can_timing_data_tests[i], true); + if (test_timing_values(dev, &can_timing_data_tests[i], true)) { + count++; + } } + + zassert_true(count > 0, "no data phase bitrates supported"); } void *can_timing_setup(void) From 7a1ec980e001ae2dc29d8f1de8f0990f1cc2346e Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Thu, 14 Mar 2024 12:38:37 +0100 Subject: [PATCH 0910/2402] drivers: can: loopback: use CiA recommeded configurations ranges Use the CAN clock and configuration ranges recommended by CAN in Automation (CiA). Signed-off-by: Henrik Brix Andersen --- drivers/can/can_loopback.c | 50 +++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/drivers/can/can_loopback.c b/drivers/can/can_loopback.c index 5304c801ea4..8a419cb446a 100644 --- a/drivers/can/can_loopback.c +++ b/drivers/can/can_loopback.c @@ -13,6 +13,7 @@ #include #include #include +#include LOG_MODULE_REGISTER(can_loopback, CONFIG_CAN_LOG_LEVEL); @@ -351,8 +352,11 @@ static void can_loopback_set_state_change_callback(const struct device *dev, static int can_loopback_get_core_clock(const struct device *dev, uint32_t *rate) { - /* Return 16MHz as an realistic value for the testcases */ - *rate = 16000000; + ARG_UNUSED(dev); + + /* Recommended CAN clock from from CiA 601-3 */ + *rate = MHZ(80); + return 0; } @@ -376,35 +380,37 @@ static const struct can_driver_api can_loopback_driver_api = { .set_state_change_callback = can_loopback_set_state_change_callback, .get_core_clock = can_loopback_get_core_clock, .get_max_filters = can_loopback_get_max_filters, + /* Recommended configuration ranges from CiA 601-2 */ .timing_min = { - .sjw = 0x1, - .prop_seg = 0x01, - .phase_seg1 = 0x01, - .phase_seg2 = 0x01, - .prescaler = 0x01 + .sjw = 1, + .prop_seg = 0, + .phase_seg1 = 2, + .phase_seg2 = 2, + .prescaler = 1 }, .timing_max = { - .sjw = 0x0F, - .prop_seg = 0x0F, - .phase_seg1 = 0x0F, - .phase_seg2 = 0x0F, - .prescaler = 0xFFFF + .sjw = 128, + .prop_seg = 0, + .phase_seg1 = 256, + .phase_seg2 = 128, + .prescaler = 32 }, #ifdef CONFIG_CAN_FD_MODE .set_timing_data = can_loopback_set_timing_data, + /* Recommended configuration ranges from CiA 601-2 */ .timing_data_min = { - .sjw = 0x1, - .prop_seg = 0x01, - .phase_seg1 = 0x01, - .phase_seg2 = 0x01, - .prescaler = 0x01 + .sjw = 1, + .prop_seg = 0, + .phase_seg1 = 1, + .phase_seg2 = 1, + .prescaler = 1 }, .timing_data_max = { - .sjw = 0x0F, - .prop_seg = 0x0F, - .phase_seg1 = 0x0F, - .phase_seg2 = 0x0F, - .prescaler = 0xFFFF + .sjw = 16, + .prop_seg = 0, + .phase_seg1 = 32, + .phase_seg2 = 16, + .prescaler = 32 }, #endif /* CONFIG_CAN_FD_MODE */ }; From 91751f4fc22f319c4df40610956af0630e2c0618 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Thu, 14 Mar 2024 12:40:53 +0100 Subject: [PATCH 0911/2402] drivers: can: fake: use CiA recommeded configurations ranges Use the CAN clock and configuration ranges recommended by CAN in Automation (CiA). Adjust the CAN shell test, which makes use of the fake CAN controller driver, to match the new timing limits. Signed-off-by: Henrik Brix Andersen --- drivers/can/can_fake.c | 46 ++++++++++++++++-------------- tests/drivers/can/shell/src/main.c | 24 ++++++++-------- 2 files changed, 37 insertions(+), 33 deletions(-) diff --git a/drivers/can/can_fake.c b/drivers/can/can_fake.c index 7725ebfa13b..508894b53d0 100644 --- a/drivers/can/can_fake.c +++ b/drivers/can/can_fake.c @@ -8,6 +8,7 @@ #include #include #include +#include #ifdef CONFIG_ZTEST #include @@ -60,7 +61,8 @@ static int fake_can_get_core_clock_delegate(const struct device *dev, uint32_t * { ARG_UNUSED(dev); - *rate = 16000000; + /* Recommended CAN clock from from CiA 601-3 */ + *rate = MHZ(80); return 0; } @@ -109,35 +111,37 @@ static const struct can_driver_api fake_can_driver_api = { .set_state_change_callback = fake_can_set_state_change_callback, .get_core_clock = fake_can_get_core_clock, .get_max_filters = fake_can_get_max_filters, + /* Recommended configuration ranges from CiA 601-2 */ .timing_min = { - .sjw = 0x01, - .prop_seg = 0x01, - .phase_seg1 = 0x01, - .phase_seg2 = 0x01, - .prescaler = 0x01 + .sjw = 1, + .prop_seg = 0, + .phase_seg1 = 2, + .phase_seg2 = 2, + .prescaler = 1 }, .timing_max = { - .sjw = 0x0f, - .prop_seg = 0x0f, - .phase_seg1 = 0x0f, - .phase_seg2 = 0x0f, - .prescaler = 0xffff + .sjw = 128, + .prop_seg = 0, + .phase_seg1 = 256, + .phase_seg2 = 128, + .prescaler = 32 }, #ifdef CONFIG_CAN_FD_MODE .set_timing_data = fake_can_set_timing_data, + /* Recommended configuration ranges from CiA 601-2 */ .timing_data_min = { - .sjw = 0x01, - .prop_seg = 0x01, - .phase_seg1 = 0x01, - .phase_seg2 = 0x01, - .prescaler = 0x01 + .sjw = 1, + .prop_seg = 0, + .phase_seg1 = 1, + .phase_seg2 = 1, + .prescaler = 1 }, .timing_data_max = { - .sjw = 0x0f, - .prop_seg = 0x0f, - .phase_seg1 = 0x0f, - .phase_seg2 = 0x0f, - .prescaler = 0xffff + .sjw = 16, + .prop_seg = 0, + .phase_seg1 = 32, + .phase_seg2 = 16, + .prescaler = 32 }, #endif /* CONFIG_CAN_FD_MODE */ }; diff --git a/tests/drivers/can/shell/src/main.c b/tests/drivers/can/shell/src/main.c index 6267fd17af1..2fe62381228 100644 --- a/tests/drivers/can/shell/src/main.c +++ b/tests/drivers/can/shell/src/main.c @@ -212,17 +212,17 @@ ZTEST(can_shell, test_can_timing) { const struct shell *sh = shell_backend_dummy_get_ptr(); struct can_timing expected = { - .sjw = 1U, - .prop_seg = 2U, - .phase_seg1 = 3U, - .phase_seg2 = 4U, - .prescaler = 5U, + .sjw = 16U, + .prop_seg = 0U, + .phase_seg1 = 217U, + .phase_seg2 = 32U, + .prescaler = 32U, }; int err; fake_can_set_timing_fake.custom_fake = can_shell_test_capture_timing; - err = shell_execute_cmd(sh, "can timing " FAKE_CAN_NAME " 1 2 3 4 5"); + err = shell_execute_cmd(sh, "can timing " FAKE_CAN_NAME " 16 0 217 32 32"); zassert_ok(err, "failed to execute shell command (err %d)", err); zassert_equal(fake_can_set_timing_fake.call_count, 1, "set_timing function not called"); zassert_equal(fake_can_set_timing_fake.arg0_val, fake_can_dev, "wrong device pointer"); @@ -244,11 +244,11 @@ ZTEST(can_shell, test_can_dtiming) { const struct shell *sh = shell_backend_dummy_get_ptr(); struct can_timing expected = { - .sjw = 1U, - .prop_seg = 2U, - .phase_seg1 = 3U, - .phase_seg2 = 4U, - .prescaler = 5U, + .sjw = 5U, + .prop_seg = 0U, + .phase_seg1 = 29U, + .phase_seg2 = 10U, + .prescaler = 2U, }; int err; @@ -256,7 +256,7 @@ ZTEST(can_shell, test_can_dtiming) fake_can_set_timing_data_fake.custom_fake = can_shell_test_capture_timing; - err = shell_execute_cmd(sh, "can dtiming " FAKE_CAN_NAME " 1 2 3 4 5"); + err = shell_execute_cmd(sh, "can dtiming " FAKE_CAN_NAME " 5 0 29 10 2"); zassert_ok(err, "failed to execute shell command (err %d)", err); zassert_equal(fake_can_set_timing_data_fake.call_count, 1, "set_timing_data function not called"); From a472870b6d1ccdf2ae6ffaab7e5c28e91fe73a1d Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Thu, 14 Mar 2024 12:41:31 +0100 Subject: [PATCH 0912/2402] tests: drivers: can: timing: enable all bitrates on simulators/emulators Enable testing of all CiA recommended bitrates on the following simulated/emulated boards: - native_sim - native_sim_64 - native_posix - native_posix_64 - qemu_x86 - qemu_x86_64 Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/timing/boards/native_posix.conf | 1 + tests/drivers/can/timing/boards/native_posix_64.conf | 1 + tests/drivers/can/timing/boards/native_sim.conf | 1 + tests/drivers/can/timing/boards/native_sim_64.conf | 1 + tests/drivers/can/timing/boards/qemu_x86.conf | 1 + tests/drivers/can/timing/boards/qemu_x86_64.conf | 1 + 6 files changed, 6 insertions(+) create mode 100644 tests/drivers/can/timing/boards/native_posix.conf create mode 100644 tests/drivers/can/timing/boards/native_posix_64.conf create mode 100644 tests/drivers/can/timing/boards/native_sim.conf create mode 100644 tests/drivers/can/timing/boards/native_sim_64.conf create mode 100644 tests/drivers/can/timing/boards/qemu_x86.conf create mode 100644 tests/drivers/can/timing/boards/qemu_x86_64.conf diff --git a/tests/drivers/can/timing/boards/native_posix.conf b/tests/drivers/can/timing/boards/native_posix.conf new file mode 100644 index 00000000000..7b071f3a54f --- /dev/null +++ b/tests/drivers/can/timing/boards/native_posix.conf @@ -0,0 +1 @@ +CONFIG_TEST_ALL_BITRATES=y diff --git a/tests/drivers/can/timing/boards/native_posix_64.conf b/tests/drivers/can/timing/boards/native_posix_64.conf new file mode 100644 index 00000000000..7b071f3a54f --- /dev/null +++ b/tests/drivers/can/timing/boards/native_posix_64.conf @@ -0,0 +1 @@ +CONFIG_TEST_ALL_BITRATES=y diff --git a/tests/drivers/can/timing/boards/native_sim.conf b/tests/drivers/can/timing/boards/native_sim.conf new file mode 100644 index 00000000000..7b071f3a54f --- /dev/null +++ b/tests/drivers/can/timing/boards/native_sim.conf @@ -0,0 +1 @@ +CONFIG_TEST_ALL_BITRATES=y diff --git a/tests/drivers/can/timing/boards/native_sim_64.conf b/tests/drivers/can/timing/boards/native_sim_64.conf new file mode 100644 index 00000000000..7b071f3a54f --- /dev/null +++ b/tests/drivers/can/timing/boards/native_sim_64.conf @@ -0,0 +1 @@ +CONFIG_TEST_ALL_BITRATES=y diff --git a/tests/drivers/can/timing/boards/qemu_x86.conf b/tests/drivers/can/timing/boards/qemu_x86.conf new file mode 100644 index 00000000000..7b071f3a54f --- /dev/null +++ b/tests/drivers/can/timing/boards/qemu_x86.conf @@ -0,0 +1 @@ +CONFIG_TEST_ALL_BITRATES=y diff --git a/tests/drivers/can/timing/boards/qemu_x86_64.conf b/tests/drivers/can/timing/boards/qemu_x86_64.conf new file mode 100644 index 00000000000..7b071f3a54f --- /dev/null +++ b/tests/drivers/can/timing/boards/qemu_x86_64.conf @@ -0,0 +1 @@ +CONFIG_TEST_ALL_BITRATES=y From c6583e7672dfa9189fe87a32484aa992f824f67a Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Thu, 14 Mar 2024 19:34:11 +0100 Subject: [PATCH 0913/2402] tests: drivers: can: timing: enable all bitrates on select boards Enable testing of all CiA recommended bitrates on the following boards: - stm32h735g_disco Signed-off-by: Henrik Brix Andersen --- tests/drivers/can/timing/boards/stm32h735g_disco.conf | 1 + 1 file changed, 1 insertion(+) create mode 100644 tests/drivers/can/timing/boards/stm32h735g_disco.conf diff --git a/tests/drivers/can/timing/boards/stm32h735g_disco.conf b/tests/drivers/can/timing/boards/stm32h735g_disco.conf new file mode 100644 index 00000000000..7b071f3a54f --- /dev/null +++ b/tests/drivers/can/timing/boards/stm32h735g_disco.conf @@ -0,0 +1 @@ +CONFIG_TEST_ALL_BITRATES=y From ab7580046a51d46e5668858e2fef038c0449f476 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Wed, 13 Mar 2024 17:07:52 -0500 Subject: [PATCH 0914/2402] soc: rw: Support I2C Flexcomms Support I2C flexcomms by clocking in soc.c and adding DT header Signed-off-by: Declan Snyder --- dts/arm/nxp/nxp_rw6xx_common.dtsi | 1 + soc/nxp/rw/soc.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index 923ad2bf47a..4579255f12d 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { cpus { diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c index 75b2cf58956..01c1d22c764 100644 --- a/soc/nxp/rw/soc.c +++ b/soc/nxp/rw/soc.c @@ -159,6 +159,23 @@ __ramfunc void clock_init(void) CLOCK_AttachClk(kFRG_to_FLEXCOMM14); #endif +/* Any flexcomm can be I2C */ +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_i2c, okay)) && CONFIG_I2C + CLOCK_AttachClk(kSFRO_to_FLEXCOMM0); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2c, okay)) && CONFIG_I2C + CLOCK_AttachClk(kSFRO_to_FLEXCOMM1); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2c, okay)) && CONFIG_I2C + CLOCK_AttachClk(kSFRO_to_FLEXCOMM2); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2c, okay)) && CONFIG_I2C + CLOCK_AttachClk(kSFRO_to_FLEXCOMM3); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm14), nxp_lpc_i2c, okay)) && CONFIG_I2C + CLOCK_AttachClk(kSFRO_to_FLEXCOMM14); +#endif + /* Clock flexcomms when used as SPI */ #ifdef CONFIG_SPI #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_spi, okay)) From 402aa08b86c62ddb5e718b2251f628f80074e99f Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Wed, 13 Mar 2024 17:08:23 -0500 Subject: [PATCH 0915/2402] boards: rd_rw612_bga: Enable I2C Enable Flexcomm2 as I2C on RD_RW612_BGA Signed-off-by: Declan Snyder --- boards/nxp/rd_rw612_bga/doc/index.rst | 3 +++ boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi | 8 ++++++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 11 +++++++++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml | 1 + 4 files changed, 23 insertions(+) diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index 1d7b795fc98..d80f1ee8e73 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -43,6 +43,9 @@ Supported Features +-----------+------------+-----------------------------------+ | SPI | on-chip | spi | +-----------+------------+-----------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-----------------------------------+ + The default configuration can be found in the defconfig file: diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi index 23ae103c891..9b2a44a7c76 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi @@ -23,4 +23,12 @@ slew-rate = "ultra"; }; }; + + pinmux_flexcomm2_i2c: pinmux_flexcomm2_i2c { + group0 { + pinmux = ; + slew-rate = "normal"; + bias-pull-up; + }; + }; }; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index 0e6e625ac57..f1c16e09962 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -11,6 +11,7 @@ usart-0 = &flexcomm3; led0 = &green_led; sw0 = &sw_4; + i2c-0 = &flexcomm2; }; chosen { @@ -48,6 +49,16 @@ arduino_spi: &flexcomm0 { #size-cells = <0>; }; +arduino_i2c: &flexcomm2 { + compatible = "nxp,lpc-i2c"; + status = "okay"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinmux_flexcomm2_i2c>; + pinctrl-names = "default"; +}; + &flexcomm3 { compatible = "nxp,lpc-usart"; status = "okay"; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml index 8d654c639a0..f51228c6c90 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -18,3 +18,4 @@ supported: - dma - gpio - spi + - i2c From b0b4bc0517d801d2d21b7c0860d5bf4677451817 Mon Sep 17 00:00:00 2001 From: Magdalena Pastula Date: Tue, 12 Mar 2024 17:32:53 +0100 Subject: [PATCH 0916/2402] soc: nordic: nrf54l: add two new Kconfig options Add SOC_NRF54LX_DISABLE_FICR_TRIMCNF and SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE config options. Signed-off-by: Magdalena Pastula --- soc/nordic/nrf54l/Kconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/soc/nordic/nrf54l/Kconfig b/soc/nordic/nrf54l/Kconfig index c7e00565c54..c087a514566 100644 --- a/soc/nordic/nrf54l/Kconfig +++ b/soc/nordic/nrf54l/Kconfig @@ -27,6 +27,22 @@ config SOC_NRF54LX_SKIP_CLOCK_CONFIG With this option, the CPU clock frequency is not set during system initialization. The CPU runs with the default, hardware-selected frequency. +config SOC_NRF54LX_DISABLE_FICR_TRIMCNF + bool "Disable trimming of the device" + default y if TRUSTED_EXECUTION_NONSECURE + help + Disable trimming of the device. When the device is trimmed it + will copy all the trimming values from FICR into the target + addresses. When TF-M is enabled it will trim the device before + booting this image. + +config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE + bool "Skip disabling glitch detector" + default n + help + With this option, the glitch detector is not disabled during system initialization. + The CPU runs with the default state of glitch detector. + config SOC_NRF_FORCE_CONSTLAT bool "Force constant-latency mode" help From 92f1b3ff96901a706bc5b144281117ddab6311a5 Mon Sep 17 00:00:00 2001 From: Magdalena Pastula Date: Tue, 12 Mar 2024 17:33:59 +0100 Subject: [PATCH 0917/2402] modules: hal_nordic: nrfx: propagate new configs to nrfx Add support for propagating SOC_NRF54LX_DISABLE_FICR_TRIMCNF and SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE values to nrfx. Signed-off-by: Magdalena Pastula --- modules/hal_nordic/nrfx/CMakeLists.txt | 2 ++ soc/nordic/nrf54l/Kconfig | 5 ++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index e3850ab9346..463c4790743 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -156,6 +156,8 @@ if(CONFIG_SOC_NRF54L15) endif() zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG NRF_SKIP_CLOCK_CONFIGURATION) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_DISABLE_FICR_TRIMCNF NRF_DISABLE_FICR_TRIMCNF) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE NRF_SKIP_GLITCHDETECTOR_DISABLE) if(CONFIG_SOC_SERIES_NRF54LX AND CONFIG_NRFX_DPPI) zephyr_library_sources(${HELPERS_DIR}/nrfx_gppi_dppi_ppib_lumos.c) diff --git a/soc/nordic/nrf54l/Kconfig b/soc/nordic/nrf54l/Kconfig index c087a514566..640e090005d 100644 --- a/soc/nordic/nrf54l/Kconfig +++ b/soc/nordic/nrf54l/Kconfig @@ -33,12 +33,11 @@ config SOC_NRF54LX_DISABLE_FICR_TRIMCNF help Disable trimming of the device. When the device is trimmed it will copy all the trimming values from FICR into the target - addresses. When TF-M is enabled it will trim the device before - booting this image. + addresses. config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE bool "Skip disabling glitch detector" - default n + default y if TRUSTED_EXECUTION_NONSECURE help With this option, the glitch detector is not disabled during system initialization. The CPU runs with the default state of glitch detector. From ce154b94d014cf2f177aee62124abdfabd0ba988 Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Tue, 27 Feb 2024 15:27:59 +0800 Subject: [PATCH 0918/2402] Bluetooth: Host: Add SCO connection management Currently, SCO connections and disconnections are agnostic to upper-layer. Add two functions, bt_sco_connected and bt_sco_disconnected, to notify the SCO connect changes. For Central side, pass "struct bt_sco_chan" object when calling bt_conn_create_sco. it uses to manage the SCO channel for upper- layer. For Peripheral side, two functions bt_sco_server_register and bt_sco_server_unregister are added to monitor SCO connection request for upper-layer. The upper-layer could accept or reject SCO connect When the connection request received. If the connect is accepted, the "struct bt_sco_chan" object could be passed by "sco_server->accept". Signed-off-by: Lyle Zhu --- include/zephyr/bluetooth/conn.h | 13 - subsys/bluetooth/host/classic/CMakeLists.txt | 1 + subsys/bluetooth/host/classic/br.c | 58 +- subsys/bluetooth/host/classic/sco.c | 528 +++++++++++++++++++ subsys/bluetooth/host/classic/sco_internal.h | 166 ++++++ subsys/bluetooth/host/conn.c | 121 ++--- subsys/bluetooth/host/conn_internal.h | 9 + 7 files changed, 767 insertions(+), 129 deletions(-) create mode 100644 subsys/bluetooth/host/classic/sco.c create mode 100644 subsys/bluetooth/host/classic/sco_internal.h diff --git a/include/zephyr/bluetooth/conn.h b/include/zephyr/bluetooth/conn.h index 4059e0963b2..ca8a7bb3fb9 100644 --- a/include/zephyr/bluetooth/conn.h +++ b/include/zephyr/bluetooth/conn.h @@ -1774,19 +1774,6 @@ struct bt_br_conn_param { struct bt_conn *bt_conn_create_br(const bt_addr_t *peer, const struct bt_br_conn_param *param); -/** @brief Initiate an SCO connection to a remote device. - * - * Allows initiate new SCO link to remote peer using its address. - * - * The caller gets a new reference to the connection object which must be - * released with bt_conn_unref() once done using the object. - * - * @param peer Remote address. - * - * @return Valid connection object on success or NULL otherwise. - */ -struct bt_conn *bt_conn_create_sco(const bt_addr_t *peer); - #ifdef __cplusplus } #endif diff --git a/subsys/bluetooth/host/classic/CMakeLists.txt b/subsys/bluetooth/host/classic/CMakeLists.txt index bfa07bf1c55..48b3935f86f 100644 --- a/subsys/bluetooth/host/classic/CMakeLists.txt +++ b/subsys/bluetooth/host/classic/CMakeLists.txt @@ -14,6 +14,7 @@ zephyr_library_sources_ifdef( l2cap_br.c sdp.c ssp.c + sco.c ) zephyr_library_sources_ifdef( diff --git a/subsys/bluetooth/host/classic/br.c b/subsys/bluetooth/host/classic/br.c index 54321a3dfc7..d176994a552 100644 --- a/subsys/bluetooth/host/classic/br.c +++ b/subsys/bluetooth/host/classic/br.c @@ -16,6 +16,7 @@ #include "host/hci_core.h" #include "host/conn_internal.h" #include "host/keys.h" +#include "sco_internal.h" #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL #include @@ -49,34 +50,6 @@ static int reject_conn(const bt_addr_t *bdaddr, uint8_t reason) return 0; } -static int accept_sco_conn(const bt_addr_t *bdaddr, struct bt_conn *sco_conn) -{ - struct bt_hci_cp_accept_sync_conn_req *cp; - struct net_buf *buf; - int err; - - buf = bt_hci_cmd_create(BT_HCI_OP_ACCEPT_SYNC_CONN_REQ, sizeof(*cp)); - if (!buf) { - return -ENOBUFS; - } - - cp = net_buf_add(buf, sizeof(*cp)); - bt_addr_copy(&cp->bdaddr, bdaddr); - cp->pkt_type = sco_conn->sco.pkt_type; - cp->tx_bandwidth = 0x00001f40; - cp->rx_bandwidth = 0x00001f40; - cp->max_latency = 0x0007; - cp->retrans_effort = 0x01; - cp->content_format = BT_VOICE_CVSD_16BIT; - - err = bt_hci_cmd_send_sync(BT_HCI_OP_ACCEPT_SYNC_CONN_REQ, buf, NULL); - if (err) { - return err; - } - - return 0; -} - static int accept_conn(const bt_addr_t *bdaddr) { struct bt_hci_cp_accept_conn_req *cp; @@ -100,28 +73,6 @@ static int accept_conn(const bt_addr_t *bdaddr) return 0; } -static void bt_esco_conn_req(struct bt_hci_evt_conn_request *evt) -{ - struct bt_conn *sco_conn; - - sco_conn = bt_conn_add_sco(&evt->bdaddr, evt->link_type); - if (!sco_conn) { - reject_conn(&evt->bdaddr, BT_HCI_ERR_INSUFFICIENT_RESOURCES); - return; - } - - if (accept_sco_conn(&evt->bdaddr, sco_conn)) { - LOG_ERR("Error accepting connection from %s", bt_addr_str(&evt->bdaddr)); - reject_conn(&evt->bdaddr, BT_HCI_ERR_UNSPECIFIED); - bt_sco_cleanup(sco_conn); - return; - } - - sco_conn->role = BT_HCI_ROLE_PERIPHERAL; - bt_conn_set_state(sco_conn, BT_CONN_CONNECTING); - bt_conn_unref(sco_conn); -} - void bt_hci_conn_req(struct net_buf *buf) { struct bt_hci_evt_conn_request *evt = (void *)buf->data; @@ -130,7 +81,12 @@ void bt_hci_conn_req(struct net_buf *buf) LOG_DBG("conn req from %s, type 0x%02x", bt_addr_str(&evt->bdaddr), evt->link_type); if (evt->link_type != BT_HCI_ACL) { - bt_esco_conn_req(evt); + uint8_t err; + + err = bt_esco_conn_req(evt); + if (err != BT_HCI_ERR_SUCCESS) { + reject_conn(&evt->bdaddr, err); + } return; } diff --git a/subsys/bluetooth/host/classic/sco.c b/subsys/bluetooth/host/classic/sco.c new file mode 100644 index 00000000000..b41a68611f5 --- /dev/null +++ b/subsys/bluetooth/host/classic/sco.c @@ -0,0 +1,528 @@ +/* sco.c - Bluetooth sco handling */ + +/* + * Copyright (c) 2015-2016 Intel Corporation + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include +#include + +#include +#include +#include + +#include "common/bt_str.h" + +#include "host/addr_internal.h" +#include "host/hci_core.h" +#include "br.h" +#include "host/conn_internal.h" +#include "sco_internal.h" + +#define LOG_LEVEL CONFIG_BT_CONN_LOG_LEVEL +#include +LOG_MODULE_REGISTER(bt_sco); + +struct bt_sco_server *sco_server; + +#define SCO_CHAN(_sco) ((_sco)->sco.chan); + +int bt_sco_server_register(struct bt_sco_server *server) +{ + CHECKIF(!server) { + LOG_DBG("Invalid parameter: server %p", server); + return -EINVAL; + } + + if (sco_server) { + return -EADDRINUSE; + } + + if (!server->accept) { + return -EINVAL; + } + + if (server->sec_level > BT_SECURITY_L3) { + return -EINVAL; + } + + LOG_DBG("%p", server); + + sco_server = server; + + return 0; +} + +int bt_sco_server_unregister(struct bt_sco_server *server) +{ + CHECKIF(!server) { + LOG_DBG("Invalid parameter: server %p", server); + return -EINVAL; + } + + if (sco_server != server) { + return -EINVAL; + } + + sco_server = NULL; + + return 0; +} + +void bt_sco_connected(struct bt_conn *sco) +{ + struct bt_sco_chan *chan; + + if (sco == NULL || sco->type != BT_CONN_TYPE_SCO) { + LOG_ERR("Invalid parameters: sco %p sco->type %u", sco, sco ? sco->type : 0); + return; + } + + LOG_DBG("%p", sco); + + chan = SCO_CHAN(sco); + + if (chan == NULL) { + LOG_ERR("Could not lookup chan from connected SCO"); + return; + } + + bt_sco_chan_set_state(chan, BT_SCO_STATE_CONNECTED); + + if (chan->ops && chan->ops->connected) { + chan->ops->connected(chan); + } +} + +void bt_sco_disconnected(struct bt_conn *sco) +{ + struct bt_sco_chan *chan; + + if (sco == NULL || sco->type != BT_CONN_TYPE_SCO) { + LOG_ERR("Invalid parameters: sco %p sco->type %u", sco, sco ? sco->type : 0); + return; + } + LOG_DBG("%p", sco); + + chan = SCO_CHAN(sco); + if (chan == NULL) { + LOG_ERR("Could not lookup chan from connected SCO"); + return; + } + + bt_sco_chan_set_state(chan, BT_SCO_STATE_DISCONNECTED); + + bt_sco_cleanup_acl(sco); + + chan->sco = NULL; + + if (chan->ops && chan->ops->disconnected) { + chan->ops->disconnected(chan, sco->err); + } +} + +static uint8_t sco_server_check_security(struct bt_conn *conn) +{ + if (IS_ENABLED(CONFIG_BT_CONN_DISABLE_SECURITY)) { + return BT_HCI_ERR_SUCCESS; + } + + if (conn->sec_level >= sco_server->sec_level) { + return BT_HCI_ERR_SUCCESS; + } + + return BT_HCI_ERR_INSUFFICIENT_SECURITY; +} + +#if defined(CONFIG_BT_CONN_LOG_LEVEL_DBG) +const char *bt_sco_chan_state_str(uint8_t state) +{ + switch (state) { + case BT_SCO_STATE_DISCONNECTED: + return "disconnected"; + case BT_SCO_STATE_CONNECTING: + return "connecting"; + case BT_SCO_STATE_ENCRYPT_PENDING: + return "encryption pending"; + case BT_SCO_STATE_CONNECTED: + return "connected"; + case BT_SCO_STATE_DISCONNECTING: + return "disconnecting"; + default: + return "unknown"; + } +} + +void bt_sco_chan_set_state_debug(struct bt_sco_chan *chan, + enum bt_sco_state state, + const char *func, int line) +{ + LOG_DBG("chan %p sco %p %s -> %s", chan, chan->sco, bt_sco_chan_state_str(chan->state), + bt_sco_chan_state_str(state)); + + /* check transitions validness */ + switch (state) { + case BT_SCO_STATE_DISCONNECTED: + /* regardless of old state always allows this states */ + break; + case BT_SCO_STATE_ENCRYPT_PENDING: + __fallthrough; + case BT_SCO_STATE_CONNECTING: + if (chan->state != BT_SCO_STATE_DISCONNECTED) { + LOG_WRN("%s()%d: invalid transition", func, line); + } + break; + case BT_SCO_STATE_CONNECTED: + if (chan->state != BT_SCO_STATE_CONNECTING) { + LOG_WRN("%s()%d: invalid transition", func, line); + } + break; + case BT_SCO_STATE_DISCONNECTING: + if (chan->state != BT_SCO_STATE_CONNECTING && + chan->state != BT_SCO_STATE_CONNECTED) { + LOG_WRN("%s()%d: invalid transition", func, line); + } + break; + default: + LOG_ERR("%s()%d: unknown (%u) state was set", func, line, state); + return; + } + + chan->state = state; +} +#else +void bt_sco_chan_set_state(struct bt_sco_chan *chan, enum bt_sco_state state) +{ + chan->state = state; +} +#endif /* CONFIG_BT_CONN_LOG_LEVEL_DBG */ + + +static void bt_sco_chan_add(struct bt_conn *sco, struct bt_sco_chan *chan) +{ + /* Attach SCO channel to the connection */ + chan->sco = sco; + sco->sco.chan = chan; + + LOG_DBG("sco %p chan %p", sco, chan); +} + +static int sco_accept(struct bt_conn *acl, struct bt_conn *sco) +{ + struct bt_sco_accept_info accept_info; + struct bt_sco_chan *chan; + int err; + + CHECKIF(!sco || sco->type != BT_CONN_TYPE_SCO) { + LOG_ERR("Invalid parameters: sco %p sco->type %u", sco, sco ? sco->type : 0); + return -EINVAL; + } + + LOG_DBG("%p", sco); + + accept_info.acl = acl; + memcpy(accept_info.dev_class, sco->sco.dev_class, sizeof(accept_info.dev_class)); + accept_info.link_type = sco->sco.link_type; + + err = sco_server->accept(&accept_info, &chan); + if (err < 0) { + LOG_ERR("Server failed to accept: %d", err); + return err; + } + + if (chan->ops == NULL) { + LOG_ERR("invalid parameter: chan %p chan->ops %p", chan, chan->ops); + return -EINVAL; + } + + chan->required_sec_level = sco_server->sec_level; + + bt_sco_chan_add(sco, chan); + bt_sco_chan_set_state(chan, BT_SCO_STATE_CONNECTING); + + return 0; +} + +static int accept_sco_conn(const bt_addr_t *bdaddr, struct bt_conn *sco_conn) +{ + struct bt_hci_cp_accept_sync_conn_req *cp; + struct net_buf *buf; + int err; + + err = sco_accept(sco_conn->sco.acl, sco_conn); + if (err) { + return err; + } + + buf = bt_hci_cmd_create(BT_HCI_OP_ACCEPT_SYNC_CONN_REQ, sizeof(*cp)); + if (!buf) { + return -ENOBUFS; + } + + cp = net_buf_add(buf, sizeof(*cp)); + bt_addr_copy(&cp->bdaddr, bdaddr); + cp->pkt_type = sco_conn->sco.pkt_type; + cp->tx_bandwidth = 0x00001f40; + cp->rx_bandwidth = 0x00001f40; + cp->max_latency = 0x0007; + cp->retrans_effort = 0x01; + cp->content_format = BT_VOICE_CVSD_16BIT; + + err = bt_hci_cmd_send_sync(BT_HCI_OP_ACCEPT_SYNC_CONN_REQ, buf, NULL); + if (err) { + return err; + } + + return 0; +} + +uint8_t bt_esco_conn_req(struct bt_hci_evt_conn_request *evt) +{ + struct bt_conn *sco_conn; + uint8_t sec_err; + + if (sco_server == NULL) { + LOG_ERR("No SCO server registered"); + return BT_HCI_ERR_UNSPECIFIED; + } + + sco_conn = bt_conn_add_sco(&evt->bdaddr, evt->link_type); + if (!sco_conn) { + return BT_HCI_ERR_INSUFFICIENT_RESOURCES; + } + + sec_err = sco_server_check_security(sco_conn->sco.acl); + if (BT_HCI_ERR_SUCCESS != sec_err) { + LOG_DBG("Insufficient security %u", sec_err); + bt_sco_cleanup(sco_conn); + return sec_err; + } + + memcpy(sco_conn->sco.dev_class, evt->dev_class, sizeof(sco_conn->sco.dev_class)); + sco_conn->sco.link_type = evt->link_type; + + if (accept_sco_conn(&evt->bdaddr, sco_conn)) { + LOG_ERR("Error accepting connection from %s", bt_addr_str(&evt->bdaddr)); + bt_sco_cleanup(sco_conn); + return BT_HCI_ERR_UNSPECIFIED; + } + + sco_conn->role = BT_HCI_ROLE_PERIPHERAL; + bt_conn_set_state(sco_conn, BT_CONN_CONNECTING); + bt_conn_unref(sco_conn); + + return BT_HCI_ERR_SUCCESS; +} + +void bt_sco_cleanup_acl(struct bt_conn *sco) +{ + LOG_DBG("%p", sco); + + if (sco->sco.acl) { + bt_conn_unref(sco->sco.acl); + sco->sco.acl = NULL; + } +} + +static int sco_chan_connect_security(struct bt_conn *sco, struct bt_sco_chan *chan) +{ + struct bt_conn *acl; + + acl = sco->sco.acl; + + if (acl->sec_level < chan->required_sec_level) { + int err; + + err = bt_conn_set_security(acl, chan->required_sec_level); + if (err != 0) { + LOG_DBG("Failed to set security: %d", err); + + /* Restore states */ + bt_sco_cleanup_acl(sco); + bt_sco_chan_set_state(chan, BT_SCO_STATE_DISCONNECTED); + + return err; + } + bt_sco_chan_set_state(chan, BT_SCO_STATE_ENCRYPT_PENDING); + } + + return 0; +} + +static int sco_setup_sync_conn(struct bt_conn *sco_conn) +{ + struct net_buf *buf; + struct bt_hci_cp_setup_sync_conn *cp; + int err; + + buf = bt_hci_cmd_create(BT_HCI_OP_SETUP_SYNC_CONN, sizeof(*cp)); + if (!buf) { + return -ENOBUFS; + } + + cp = net_buf_add(buf, sizeof(*cp)); + + (void)memset(cp, 0, sizeof(*cp)); + + LOG_DBG("handle : %x", sco_conn->sco.acl->handle); + + cp->handle = sco_conn->sco.acl->handle; + cp->pkt_type = sco_conn->sco.pkt_type; + cp->tx_bandwidth = 0x00001f40; + cp->rx_bandwidth = 0x00001f40; + cp->max_latency = 0x0007; + cp->retrans_effort = 0x01; + cp->content_format = BT_VOICE_CVSD_16BIT; + + err = bt_hci_cmd_send_sync(BT_HCI_OP_SETUP_SYNC_CONN, buf, NULL); + if (err < 0) { + return err; + } + return 0; +} + +struct bt_conn *bt_conn_create_sco(const bt_addr_t *peer, struct bt_sco_chan *chan) +{ + struct bt_conn *sco_conn; + int link_type; + + sco_conn = bt_conn_lookup_addr_sco(peer); + if (sco_conn) { + switch (sco_conn->state) { + case BT_CONN_CONNECTING: + case BT_CONN_CONNECTED: + return sco_conn; + default: + bt_conn_unref(sco_conn); + return NULL; + } + } + + if (BT_FEAT_LMP_ESCO_CAPABLE(bt_dev.features)) { + link_type = BT_HCI_ESCO; + } else { + link_type = BT_HCI_SCO; + } + + sco_conn = bt_conn_add_sco(peer, link_type); + if (!sco_conn) { + return NULL; + } + + sco_conn->sco.link_type = link_type; + + bt_sco_chan_add(sco_conn, chan); + bt_conn_set_state(chan->sco, BT_CONN_CONNECTING); + bt_sco_chan_set_state(chan, BT_SCO_STATE_CONNECTING); + + if (sco_chan_connect_security(sco_conn, chan) != 0) { + bt_sco_cleanup(sco_conn); + return NULL; + } + + if (chan->state == BT_SCO_STATE_ENCRYPT_PENDING) { + return sco_conn; + } + + if (sco_setup_sync_conn(sco_conn) < 0) { + bt_conn_set_state(chan->sco, BT_CONN_DISCONNECTED); + bt_sco_chan_set_state(chan, BT_SCO_STATE_DISCONNECTED); + bt_sco_cleanup(sco_conn); + return NULL; + } + + return sco_conn; +} + +struct sco_conns_scanning_data { + struct bt_conn *acl; + struct bt_conn *sco[CONFIG_BT_MAX_SCO_CONN]; +}; + +static void sco_conns_scanning_cb(struct bt_conn *sco, void *user_data) +{ + struct sco_conns_scanning_data *data; + struct bt_sco_chan *chan; + int i; + + data = (struct sco_conns_scanning_data *)user_data; + + if (sco->sco.acl != data->acl) { + return; + } + + chan = SCO_CHAN(sco); + if (chan->state != BT_SCO_STATE_ENCRYPT_PENDING) { + return; + } + + for (i = 0; i < CONFIG_BT_MAX_SCO_CONN; i++) { + if (data->sco[i] == NULL) { + data->sco[i] = sco; + break; + } + } + bt_sco_chan_set_state(chan, BT_SCO_STATE_DISCONNECTED); +} + +void bt_sco_security_changed(struct bt_conn *acl, uint8_t hci_status) +{ + struct sco_conns_scanning_data data; + struct bt_sco_chan *chan; + int err; + int i; + uint8_t hci_err; + + /* The peripheral does not accept any SCO requests if security is + * insufficient, so we only need to handle central here. + * BT_SCO_STATE_ENCRYPT_PENDING is only set by the central. + */ + if (!IS_ENABLED(CONFIG_BT_CENTRAL) || + acl->role != BT_CONN_ROLE_CENTRAL) { + return; + } + + (void)memset(&data, 0, sizeof(data)); + + bt_conn_foreach(BT_CONN_TYPE_SCO, sco_conns_scanning_cb, &data); + + for (i = 0; i < CONFIG_BT_MAX_SCO_CONN; i++) { + struct bt_conn *sco; + + sco = data.sco[i]; + if (sco != NULL) { + chan = SCO_CHAN(sco); + hci_err = hci_status; + + if (hci_status == BT_HCI_ERR_SUCCESS) { + err = sco_setup_sync_conn(sco); + if (err < 0) { + LOG_ERR("Failed to setup sync conn: %d", err); + bt_sco_cleanup(sco); + hci_err = BT_HCI_ERR_UNSPECIFIED; + } else { + /* Set connection states */ + bt_sco_chan_set_state(chan, BT_SCO_STATE_CONNECTING); + } + } + + if (hci_err != BT_HCI_ERR_SUCCESS) { + LOG_DBG("Failed to encrypt ACL %p for SCO %p: %u", acl, + sco, hci_status); + + /* Notify upper-layer that the SCO connection + * cannot be created due to the error. + */ + if (chan->ops->disconnected) { + chan->ops->disconnected(chan, hci_err); + } + } + } + } +} diff --git a/subsys/bluetooth/host/classic/sco_internal.h b/subsys/bluetooth/host/classic/sco_internal.h new file mode 100644 index 00000000000..79e745a209d --- /dev/null +++ b/subsys/bluetooth/host/classic/sco_internal.h @@ -0,0 +1,166 @@ +/** @file + * @brief Internal APIs for Bluetooth SCO handling. + */ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @brief Life-span states of SCO channel. Used only by internal APIs + * dealing with setting channel to proper state depending on operational + * context. + */ +enum bt_sco_state { + /** Channel disconnected */ + BT_SCO_STATE_DISCONNECTED, + /** Channel is pending ACL encryption before connecting */ + BT_SCO_STATE_ENCRYPT_PENDING, + /** Channel in connecting state */ + BT_SCO_STATE_CONNECTING, + /** Channel ready for upper layer traffic on it */ + BT_SCO_STATE_CONNECTED, + /** Channel in disconnecting state */ + BT_SCO_STATE_DISCONNECTING, +}; + +struct bt_sco_chan; +struct bt_sco_chan_ops { + /** @brief Channel connected callback + * + * If this callback is provided it will be called whenever the + * connection completes. + * + * @param chan The channel that has been connected + */ + void (*connected)(struct bt_sco_chan *chan); + + /** @brief Channel disconnected callback + * + * If this callback is provided it will be called whenever the + * channel is disconnected, including when a connection gets + * rejected or when setting security fails. + * + * @param chan The channel that has been Disconnected + * @param reason BT_HCI_ERR_* reason for the disconnection. + */ + void (*disconnected)(struct bt_sco_chan *chan, uint8_t reason); +}; + +struct bt_sco_chan { + struct bt_conn *sco; + /** Channel operations reference */ + struct bt_sco_chan_ops *ops; + + enum bt_sco_state state; + + /** @brief The required security level of the channel + * + * This value can be set as the central before calling bt_conn_create_sco(). + * The value is overwritten to @ref bt_iso_server::sec_level for the + * peripheral once a channel has been accepted. + * + * Only available when @kconfig{CONFIG_BT_SMP} is enabled. + */ + bt_security_t required_sec_level; +}; + +/** @brief Initiate an SCO connection to a remote device. + * + * Allows initiate new SCO link to remote peer using its address. + * + * The caller gets a new reference to the connection object which must be + * released with bt_conn_unref() once done using the object. + * + * @param peer Remote address. + * @param chan sco chan object. + * + * @return Valid connection object on success or NULL otherwise. + */ +struct bt_conn *bt_conn_create_sco(const bt_addr_t *peer, struct bt_sco_chan *chan); + +/** @brief SCO Accept Info Structure */ +struct bt_sco_accept_info { + /** The ACL connection that is requesting authorization */ + struct bt_conn *acl; + + /** class code of peer device */ + uint8_t dev_class[3]; + + /** link type */ + uint8_t link_type; +}; + +/** @brief SCO Server structure. */ +struct bt_sco_server { + /** Required minimum security level. + * Only available when @kconfig{CONFIG_BT_SMP} is enabled. + */ + bt_security_t sec_level; + /** @brief Server accept callback + * + * This callback is called whenever a new incoming connection requires + * authorization. + * + * @param info The SCO accept information structure + * @param chan Pointer to receive the allocated channel + * + * @return 0 in case of success or negative value in case of error. + */ + int (*accept)(const struct bt_sco_accept_info *info, + struct bt_sco_chan **chan); +}; + +/** @brief Register SCO server. + * + * Register SCO server, each new connection is authorized using the accept() + * callback which in case of success shall allocate the channel structure + * to be used by the new connection. + * + * @param server Server structure. + * + * @return 0 in case of success or negative value in case of error. + */ +int bt_sco_server_register(struct bt_sco_server *server); + +/** @brief Unregister SCO server. + * + * Unregister previously registered SCO server. + * + * @param server Server structure. + * + * @return 0 in case of success or negative value in case of error. + */ +int bt_sco_server_unregister(struct bt_sco_server *server); + +/** @brief sco channel connected. + * + * sco channel connected + * + * @param sco SCO connection object. + */ +void bt_sco_connected(struct bt_conn *sco); + +/** @brief sco channel disconnected. + * + * sco channel disconnected + * + * @param sco SCO connection object. + */ +void bt_sco_disconnected(struct bt_conn *sco); + +/* Notify SCO connected channels of security changed */ +void bt_sco_security_changed(struct bt_conn *acl, uint8_t hci_status); + +uint8_t bt_esco_conn_req(struct bt_hci_evt_conn_request *evt); + + +#if defined(CONFIG_BT_CONN_LOG_LEVEL_DBG) +void bt_sco_chan_set_state_debug(struct bt_sco_chan *chan, + enum bt_sco_state state, + const char *func, int line); +#define bt_sco_chan_set_state(_chan, _state) \ + bt_sco_chan_set_state_debug(_chan, _state, __func__, __LINE__) +#else +void bt_sco_chan_set_state(struct bt_sco_chan *chan, enum bt_sco_state state); +#endif /* CONFIG_BT_CONN_LOG_LEVEL_DBG */ diff --git a/subsys/bluetooth/host/conn.c b/subsys/bluetooth/host/conn.c index 25241b11815..615abe9009c 100644 --- a/subsys/bluetooth/host/conn.c +++ b/subsys/bluetooth/host/conn.c @@ -42,6 +42,7 @@ #include "att_internal.h" #include "iso_internal.h" #include "direction_internal.h" +#include "classic/sco_internal.h" #define LOG_LEVEL CONFIG_BT_CONN_LOG_LEVEL #include @@ -1104,7 +1105,9 @@ void bt_conn_set_state(struct bt_conn *conn, bt_conn_state_t state) switch (conn->state) { case BT_CONN_CONNECTED: if (conn->type == BT_CONN_TYPE_SCO) { - /* TODO: Notify sco connected */ + if (IS_ENABLED(CONFIG_BT_CLASSIC)) { + bt_sco_connected(conn); + } break; } k_fifo_init(&conn->tx_queue); @@ -1138,7 +1141,9 @@ void bt_conn_set_state(struct bt_conn *conn, bt_conn_state_t state) case BT_CONN_DISCONNECTED: #if defined(CONFIG_BT_CONN) if (conn->type == BT_CONN_TYPE_SCO) { - /* TODO: Notify sco disconnected */ + if (IS_ENABLED(CONFIG_BT_CLASSIC)) { + bt_sco_disconnected(conn); + } bt_conn_unref(conn); break; } @@ -1831,6 +1836,29 @@ static struct bt_conn *conn_lookup_iso(struct bt_conn *conn) } #endif /* CONFIG_BT_ISO */ +#if defined(CONFIG_BT_CLASSIC) +static struct bt_conn *conn_lookup_sco(struct bt_conn *conn) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(sco_conns); i++) { + struct bt_conn *sco = bt_conn_ref(&sco_conns[i]); + + if (sco == NULL) { + continue; + } + + if (sco->sco.acl == conn) { + return sco; + } + + bt_conn_unref(sco); + } + + return NULL; +} +#endif /* CONFIG_BT_CLASSIC */ + static void deferred_work(struct k_work *work) { struct k_work_delayable *dwork = k_work_delayable_from_work(work); @@ -1871,7 +1899,28 @@ static void deferred_work(struct k_work *work) iso = conn_lookup_iso(conn); } #endif +#if defined(CONFIG_BT_CLASSIC) + struct bt_conn *sco; + + /* Mark all SCO channels associated + * with ACL conn as not connected, and + * remove ACL reference + */ + sco = conn_lookup_sco(conn); + while (sco != NULL) { + struct bt_sco_chan *chan = sco->sco.chan; + + if (chan != NULL) { + bt_sco_chan_set_state(chan, + BT_SCO_STATE_DISCONNECTING); + } + bt_sco_cleanup_acl(sco); + + bt_conn_unref(sco); + sco = conn_lookup_sco(conn); + } +#endif /* CONFIG_BT_CLASSIC */ bt_l2cap_disconnected(conn); notify_disconnected(conn); @@ -1945,8 +1994,7 @@ static struct bt_conn *acl_conn_new(void) #if defined(CONFIG_BT_CLASSIC) void bt_sco_cleanup(struct bt_conn *sco_conn) { - bt_conn_unref(sco_conn->sco.acl); - sco_conn->sco.acl = NULL; + bt_sco_cleanup_acl(sco_conn); bt_conn_unref(sco_conn); } @@ -2006,67 +2054,6 @@ struct bt_conn *bt_conn_create_br(const bt_addr_t *peer, return conn; } -struct bt_conn *bt_conn_create_sco(const bt_addr_t *peer) -{ - struct bt_hci_cp_setup_sync_conn *cp; - struct bt_conn *sco_conn; - struct net_buf *buf; - int link_type; - - sco_conn = bt_conn_lookup_addr_sco(peer); - if (sco_conn) { - switch (sco_conn->state) { - case BT_CONN_CONNECTING: - case BT_CONN_CONNECTED: - return sco_conn; - default: - bt_conn_unref(sco_conn); - return NULL; - } - } - - if (BT_FEAT_LMP_ESCO_CAPABLE(bt_dev.features)) { - link_type = BT_HCI_ESCO; - } else { - link_type = BT_HCI_SCO; - } - - sco_conn = bt_conn_add_sco(peer, link_type); - if (!sco_conn) { - return NULL; - } - - buf = bt_hci_cmd_create(BT_HCI_OP_SETUP_SYNC_CONN, sizeof(*cp)); - if (!buf) { - bt_sco_cleanup(sco_conn); - return NULL; - } - - cp = net_buf_add(buf, sizeof(*cp)); - - (void)memset(cp, 0, sizeof(*cp)); - - LOG_ERR("handle : %x", sco_conn->sco.acl->handle); - - cp->handle = sco_conn->sco.acl->handle; - cp->pkt_type = sco_conn->sco.pkt_type; - cp->tx_bandwidth = 0x00001f40; - cp->rx_bandwidth = 0x00001f40; - cp->max_latency = 0x0007; - cp->retrans_effort = 0x01; - cp->content_format = BT_VOICE_CVSD_16BIT; - - if (bt_hci_cmd_send_sync(BT_HCI_OP_SETUP_SYNC_CONN, buf, - NULL) < 0) { - bt_sco_cleanup(sco_conn); - return NULL; - } - - bt_conn_set_state(sco_conn, BT_CONN_CONNECTING); - - return sco_conn; -} - struct bt_conn *bt_conn_lookup_addr_sco(const bt_addr_t *peer) { int i; @@ -2338,6 +2325,10 @@ void bt_conn_security_changed(struct bt_conn *conn, uint8_t hci_err, bt_iso_security_changed(conn, hci_err); } + if (IS_ENABLED(CONFIG_BT_CLASSIC)) { + bt_sco_security_changed(conn, hci_err); + } + for (struct bt_conn_cb *cb = callback_list; cb; cb = cb->_next) { if (cb->security_changed) { cb->security_changed(conn, conn->sec_level, err); diff --git a/subsys/bluetooth/host/conn_internal.h b/subsys/bluetooth/host/conn_internal.h index 2f41e748068..cce4af3fd8c 100644 --- a/subsys/bluetooth/host/conn_internal.h +++ b/subsys/bluetooth/host/conn_internal.h @@ -104,7 +104,13 @@ struct bt_conn_br { struct bt_conn_sco { /* Reference to ACL Connection */ struct bt_conn *acl; + + /* Reference to the struct bt_sco_chan */ + struct bt_sco_chan *chan; + uint16_t pkt_type; + uint8_t dev_class[3]; + uint8_t link_type; }; #endif @@ -293,6 +299,9 @@ struct bt_conn *bt_conn_add_br(const bt_addr_t *peer); /* Add a new SCO connection */ struct bt_conn *bt_conn_add_sco(const bt_addr_t *peer, int link_type); +/* Cleanup SCO ACL reference */ +void bt_sco_cleanup_acl(struct bt_conn *sco_conn); + /* Cleanup SCO references */ void bt_sco_cleanup(struct bt_conn *sco_conn); From faeb9bf6813ba7a3532a2492b92e381905e03e0c Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Wed, 28 Feb 2024 19:08:47 +0800 Subject: [PATCH 0919/2402] Bluetooth: Host: Add SCO Connect notify for HFP Call bt_sco_server_register to register SCO server. Manage the SCO connection request. Get SCO connect/disconnect status via SCO channel ops. Notify the uppper layer of the SCO connection status changes through bt_hfp_hf_cb:: sco_connected and bt_hfp_hf_cb:: sco_disconnected. Signed-off-by: Lyle Zhu --- include/zephyr/bluetooth/classic/hfp_hf.h | 18 +++++++ subsys/bluetooth/host/classic/hfp_hf.c | 56 ++++++++++++++++++++ subsys/bluetooth/host/classic/hfp_internal.h | 2 + 3 files changed, 76 insertions(+) diff --git a/include/zephyr/bluetooth/classic/hfp_hf.h b/include/zephyr/bluetooth/classic/hfp_hf.h index 3ac9a87328e..ded881351ca 100644 --- a/include/zephyr/bluetooth/classic/hfp_hf.h +++ b/include/zephyr/bluetooth/classic/hfp_hf.h @@ -64,6 +64,24 @@ struct bt_hfp_hf_cb { * @param conn Connection object. */ void (*disconnected)(struct bt_conn *conn); + /** HF SCO/eSCO connected Callback + * + * If this callback is provided it will be called whenever the + * SCO/eSCO connection completes. + * + * @param conn Connection object. + * @param sco_conn SCO/eSCO Connection object. + */ + void (*sco_connected)(struct bt_conn *conn, struct bt_conn *sco_conn); + /** HF SCO/eSCO disconnected Callback + * + * If this callback is provided it will be called whenever the + * SCO/eSCO connection gets disconnected. + * + * @param conn Connection object. + * @param reason BT_HCI_ERR_* reason for the disconnection. + */ + void (*sco_disconnected)(struct bt_conn *sco_conn, uint8_t reason); /** HF indicator Callback * * This callback provides service indicator value to the application diff --git a/subsys/bluetooth/host/classic/hfp_hf.c b/subsys/bluetooth/host/classic/hfp_hf.c index cfa4ed4ae39..63872f8af47 100644 --- a/subsys/bluetooth/host/classic/hfp_hf.c +++ b/subsys/bluetooth/host/classic/hfp_hf.c @@ -24,6 +24,7 @@ #include "l2cap_br_internal.h" #include "rfcomm_internal.h" #include "at.h" +#include "sco_internal.h" #include "hfp_internal.h" #define LOG_LEVEL CONFIG_BT_HFP_HF_LOG_LEVEL @@ -691,6 +692,54 @@ static int bt_hfp_hf_accept(struct bt_conn *conn, struct bt_rfcomm_dlc **dlc) return -ENOMEM; } +static void hfp_hf_sco_connected(struct bt_sco_chan *chan) +{ + if ((bt_hf != NULL) && (bt_hf->sco_connected)) { + bt_hf->sco_connected(chan->sco->sco.acl, chan->sco); + } +} + +static void hfp_hf_sco_disconnected(struct bt_sco_chan *chan, uint8_t reason) +{ + if ((bt_hf != NULL) && (bt_hf->sco_disconnected)) { + bt_hf->sco_disconnected(chan->sco, reason); + } +} + +static int bt_hfp_hf_sco_accept(const struct bt_sco_accept_info *info, + struct bt_sco_chan **chan) +{ + int i; + static struct bt_sco_chan_ops ops = { + .connected = hfp_hf_sco_connected, + .disconnected = hfp_hf_sco_disconnected, + }; + + LOG_DBG("conn %p", info->acl); + + for (i = 0; i < ARRAY_SIZE(bt_hfp_hf_pool); i++) { + struct bt_hfp_hf *hf = &bt_hfp_hf_pool[i]; + + if (NULL == hf->rfcomm_dlc.session) { + continue; + } + + if (info->acl != hf->rfcomm_dlc.session->br_chan.chan.conn) { + continue; + } + + hf->chan.ops = &ops; + + *chan = &hf->chan; + + return 0; + } + + LOG_ERR("Unable to establish HF connection (%p)", info->acl); + + return -ENOMEM; +} + static void hfp_hf_init(void) { static struct bt_rfcomm_server chan = { @@ -699,6 +748,13 @@ static void hfp_hf_init(void) }; bt_rfcomm_server_register(&chan); + + static struct bt_sco_server sco_server = { + .sec_level = BT_SECURITY_L0, + .accept = bt_hfp_hf_sco_accept, + }; + + bt_sco_server_register(&sco_server); } int bt_hfp_hf_register(struct bt_hfp_hf_cb *cb) diff --git a/subsys/bluetooth/host/classic/hfp_internal.h b/subsys/bluetooth/host/classic/hfp_internal.h index 933e2578d26..50c883fedec 100644 --- a/subsys/bluetooth/host/classic/hfp_internal.h +++ b/subsys/bluetooth/host/classic/hfp_internal.h @@ -48,6 +48,8 @@ struct bt_hfp_hf { struct bt_rfcomm_dlc rfcomm_dlc; /* ACL connection handle */ struct bt_conn *acl; + /* SCO Channel */ + struct bt_sco_chan chan; char hf_buffer[HF_MAX_BUF_LEN]; struct at_client at; uint32_t hf_features; From 39162fd71a2cc698f7f8a9b79b70e87f5fbd69bb Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Fri, 15 Mar 2024 16:04:07 +0800 Subject: [PATCH 0920/2402] Bluetooth: Host: Remove SCO security check Remove SCO security management code block. Currently, security related checks are not necessary. It can be added if needed. Signed-off-by: Lyle Zhu --- subsys/bluetooth/host/classic/sco.c | 123 ------------------- subsys/bluetooth/host/classic/sco_internal.h | 14 --- subsys/bluetooth/host/conn.c | 4 - 3 files changed, 141 deletions(-) diff --git a/subsys/bluetooth/host/classic/sco.c b/subsys/bluetooth/host/classic/sco.c index b41a68611f5..95054184455 100644 --- a/subsys/bluetooth/host/classic/sco.c +++ b/subsys/bluetooth/host/classic/sco.c @@ -241,8 +241,6 @@ static int sco_accept(struct bt_conn *acl, struct bt_conn *sco) return -EINVAL; } - chan->required_sec_level = sco_server->sec_level; - bt_sco_chan_add(sco, chan); bt_sco_chan_set_state(chan, BT_SCO_STATE_CONNECTING); @@ -330,31 +328,6 @@ void bt_sco_cleanup_acl(struct bt_conn *sco) } } -static int sco_chan_connect_security(struct bt_conn *sco, struct bt_sco_chan *chan) -{ - struct bt_conn *acl; - - acl = sco->sco.acl; - - if (acl->sec_level < chan->required_sec_level) { - int err; - - err = bt_conn_set_security(acl, chan->required_sec_level); - if (err != 0) { - LOG_DBG("Failed to set security: %d", err); - - /* Restore states */ - bt_sco_cleanup_acl(sco); - bt_sco_chan_set_state(chan, BT_SCO_STATE_DISCONNECTED); - - return err; - } - bt_sco_chan_set_state(chan, BT_SCO_STATE_ENCRYPT_PENDING); - } - - return 0; -} - static int sco_setup_sync_conn(struct bt_conn *sco_conn) { struct net_buf *buf; @@ -421,15 +394,6 @@ struct bt_conn *bt_conn_create_sco(const bt_addr_t *peer, struct bt_sco_chan *ch bt_conn_set_state(chan->sco, BT_CONN_CONNECTING); bt_sco_chan_set_state(chan, BT_SCO_STATE_CONNECTING); - if (sco_chan_connect_security(sco_conn, chan) != 0) { - bt_sco_cleanup(sco_conn); - return NULL; - } - - if (chan->state == BT_SCO_STATE_ENCRYPT_PENDING) { - return sco_conn; - } - if (sco_setup_sync_conn(sco_conn) < 0) { bt_conn_set_state(chan->sco, BT_CONN_DISCONNECTED); bt_sco_chan_set_state(chan, BT_SCO_STATE_DISCONNECTED); @@ -439,90 +403,3 @@ struct bt_conn *bt_conn_create_sco(const bt_addr_t *peer, struct bt_sco_chan *ch return sco_conn; } - -struct sco_conns_scanning_data { - struct bt_conn *acl; - struct bt_conn *sco[CONFIG_BT_MAX_SCO_CONN]; -}; - -static void sco_conns_scanning_cb(struct bt_conn *sco, void *user_data) -{ - struct sco_conns_scanning_data *data; - struct bt_sco_chan *chan; - int i; - - data = (struct sco_conns_scanning_data *)user_data; - - if (sco->sco.acl != data->acl) { - return; - } - - chan = SCO_CHAN(sco); - if (chan->state != BT_SCO_STATE_ENCRYPT_PENDING) { - return; - } - - for (i = 0; i < CONFIG_BT_MAX_SCO_CONN; i++) { - if (data->sco[i] == NULL) { - data->sco[i] = sco; - break; - } - } - bt_sco_chan_set_state(chan, BT_SCO_STATE_DISCONNECTED); -} - -void bt_sco_security_changed(struct bt_conn *acl, uint8_t hci_status) -{ - struct sco_conns_scanning_data data; - struct bt_sco_chan *chan; - int err; - int i; - uint8_t hci_err; - - /* The peripheral does not accept any SCO requests if security is - * insufficient, so we only need to handle central here. - * BT_SCO_STATE_ENCRYPT_PENDING is only set by the central. - */ - if (!IS_ENABLED(CONFIG_BT_CENTRAL) || - acl->role != BT_CONN_ROLE_CENTRAL) { - return; - } - - (void)memset(&data, 0, sizeof(data)); - - bt_conn_foreach(BT_CONN_TYPE_SCO, sco_conns_scanning_cb, &data); - - for (i = 0; i < CONFIG_BT_MAX_SCO_CONN; i++) { - struct bt_conn *sco; - - sco = data.sco[i]; - if (sco != NULL) { - chan = SCO_CHAN(sco); - hci_err = hci_status; - - if (hci_status == BT_HCI_ERR_SUCCESS) { - err = sco_setup_sync_conn(sco); - if (err < 0) { - LOG_ERR("Failed to setup sync conn: %d", err); - bt_sco_cleanup(sco); - hci_err = BT_HCI_ERR_UNSPECIFIED; - } else { - /* Set connection states */ - bt_sco_chan_set_state(chan, BT_SCO_STATE_CONNECTING); - } - } - - if (hci_err != BT_HCI_ERR_SUCCESS) { - LOG_DBG("Failed to encrypt ACL %p for SCO %p: %u", acl, - sco, hci_status); - - /* Notify upper-layer that the SCO connection - * cannot be created due to the error. - */ - if (chan->ops->disconnected) { - chan->ops->disconnected(chan, hci_err); - } - } - } - } -} diff --git a/subsys/bluetooth/host/classic/sco_internal.h b/subsys/bluetooth/host/classic/sco_internal.h index 79e745a209d..1018f0a0b54 100644 --- a/subsys/bluetooth/host/classic/sco_internal.h +++ b/subsys/bluetooth/host/classic/sco_internal.h @@ -53,16 +53,6 @@ struct bt_sco_chan { struct bt_sco_chan_ops *ops; enum bt_sco_state state; - - /** @brief The required security level of the channel - * - * This value can be set as the central before calling bt_conn_create_sco(). - * The value is overwritten to @ref bt_iso_server::sec_level for the - * peripheral once a channel has been accepted. - * - * Only available when @kconfig{CONFIG_BT_SMP} is enabled. - */ - bt_security_t required_sec_level; }; /** @brief Initiate an SCO connection to a remote device. @@ -149,12 +139,8 @@ void bt_sco_connected(struct bt_conn *sco); */ void bt_sco_disconnected(struct bt_conn *sco); -/* Notify SCO connected channels of security changed */ -void bt_sco_security_changed(struct bt_conn *acl, uint8_t hci_status); - uint8_t bt_esco_conn_req(struct bt_hci_evt_conn_request *evt); - #if defined(CONFIG_BT_CONN_LOG_LEVEL_DBG) void bt_sco_chan_set_state_debug(struct bt_sco_chan *chan, enum bt_sco_state state, diff --git a/subsys/bluetooth/host/conn.c b/subsys/bluetooth/host/conn.c index 615abe9009c..85e0945de1c 100644 --- a/subsys/bluetooth/host/conn.c +++ b/subsys/bluetooth/host/conn.c @@ -2325,10 +2325,6 @@ void bt_conn_security_changed(struct bt_conn *conn, uint8_t hci_err, bt_iso_security_changed(conn, hci_err); } - if (IS_ENABLED(CONFIG_BT_CLASSIC)) { - bt_sco_security_changed(conn, hci_err); - } - for (struct bt_conn_cb *cb = callback_list; cb; cb = cb->_next) { if (cb->security_changed) { cb->security_changed(conn, conn->sec_level, err); From 7a21c6f16aa0bffa93975841d5e1890ca6d0705f Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Tue, 19 Mar 2024 07:33:54 +0000 Subject: [PATCH 0921/2402] tests: llext: fix conflict between BUILD_ONLY and "object" case Fix conflict between commit ce243944375e ("llext: add object test case") and commit 1408d1e5b8ce ("tests: llext: compile architectures not supported yet") which were tested separately but merged at the same time. Github "Merge Queues" can avoid this (and save resources) but: - they're not used by Zephyr CI - they provide confusing feedback Signed-off-by: Marc Herbert --- tests/subsys/llext/simple/src/test_llext_simple.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/subsys/llext/simple/src/test_llext_simple.c b/tests/subsys/llext/simple/src/test_llext_simple.c index 6f92951dd56..3d64afdfc17 100644 --- a/tests/subsys/llext/simple/src/test_llext_simple.c +++ b/tests/subsys/llext/simple/src/test_llext_simple.c @@ -153,12 +153,12 @@ static LLEXT_CONST uint8_t relative_jump_ext[] __aligned(4) = { #include "relative_jump.inc" }; LLEXT_LOAD_UNLOAD(relative_jump, true) -#endif /* ! LOADER_BUILD_ONLY */ static LLEXT_CONST uint8_t object_ext[] __aligned(4) = { #include "object.inc" }; LLEXT_LOAD_UNLOAD(object, true) +#endif /* ! LOADER_BUILD_ONLY */ /* * Ensure that EXPORT_SYMBOL does indeed provide a symbol and a valid address From cb99303dd44cbab95265ae59ab8e6b34e91d016a Mon Sep 17 00:00:00 2001 From: Erik Tamlin Date: Fri, 2 Feb 2024 19:36:44 +0100 Subject: [PATCH 0922/2402] west: percepio: update module Update the percepio module to use TraceRecorder v4.8.2 and DevAlert (DFM) v2.1.0 Signed-off-by: Erik Tamlin --- modules/percepio/CMakeLists.txt | 20 ++++++++++++++++++-- west.yml | 2 +- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/modules/percepio/CMakeLists.txt b/modules/percepio/CMakeLists.txt index 49de379e7f9..62fe2b058f9 100644 --- a/modules/percepio/CMakeLists.txt +++ b/modules/percepio/CMakeLists.txt @@ -102,14 +102,14 @@ if(CONFIG_PERCEPIO_DFM) set(DFM_DIR ${ZEPHYR_CURRENT_MODULE_DIR}/DFM) - zephyr_library_sources_ifdef( - CONFIG_PERCEPIO_DFM + zephyr_library_sources( ${DFM_DIR}/dfm.c ${DFM_DIR}/dfmAlert.c ${DFM_DIR}/dfmCloud.c ${DFM_DIR}/dfmEntry.c ${DFM_DIR}/dfmSession.c ${DFM_DIR}/dfmStorage.c + ${DFM_DIR}/dfmRetainedMemory.c ${DFM_DIR}/kernelports/Zephyr/dfmKernelPort.c ) @@ -133,6 +133,16 @@ if(CONFIG_PERCEPIO_DFM) ) endif() + if(CONFIG_PERCEPIO_DFM_CFG_STORAGEPORT_FILESYSTEM) + zephyr_library_sources( + ${DFM_DIR}/kernelports/Zephyr/storageports/Filesystem/dfmStoragePort.c + ) + + zephyr_include_directories( + ${DFM_DIR}/kernelports/Zephyr/storageports/Filesystem/include/ + ) + endif() + if(CONFIG_PERCEPIO_DFM_CFG_CLOUDPORT_NONE) zephyr_library_sources( ${DFM_DIR}/cloudports/Dummy/dfmCloudPort.c @@ -154,6 +164,12 @@ if(CONFIG_PERCEPIO_DFM) ) endif() + if(CONFIG_PERCEPIO_DFM_CFG_RETAINED_MEMORY) + zephyr_library_sources( + ${DFM_DIR}/kernelports/Zephyr/dfmRetainedMemoryPort.c + ) + endif() + zephyr_include_directories( ${DFM_DIR}/kernelports/Zephyr/config ${DFM_DIR}/kernelports/Zephyr/include diff --git a/west.yml b/west.yml index 7d5073e9e5a..6136fd8638a 100644 --- a/west.yml +++ b/west.yml @@ -305,7 +305,7 @@ manifest: path: modules/lib/openthread - name: percepio path: modules/debug/percepio - revision: 0fbc5b72aeab8a6434523a3a7bc8111c17f0bc73 + revision: 7f6fb3f12ea1493a2f8ab6a876fb255a39db47c8 groups: - debug - name: picolibc From 053e5f93ac7192d5fcffd33fc5c2164ec6e4bffa Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Thu, 14 Mar 2024 13:27:53 +0100 Subject: [PATCH 0923/2402] twister: use enum for the `arch` field in Twister platform schema This commit adds an enum to the `arch` field of the Twister platform schema. This helps better filter boards for testcases which use architecture-based filters, and helps maintain uniformity in naming convetion. Signed-off-by: Filip Kokosinski --- scripts/schemas/twister/platform-schema.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/scripts/schemas/twister/platform-schema.yaml b/scripts/schemas/twister/platform-schema.yaml index f1ba2d88748..b5c3339fc03 100644 --- a/scripts/schemas/twister/platform-schema.yaml +++ b/scripts/schemas/twister/platform-schema.yaml @@ -41,6 +41,23 @@ mapping: type: str "arch": type: str + enum: + [ + # architectures + "arc", + "arm", + "arm64", + "mips", + "nios2", + "posix", + "riscv", + "sparc", + "x86", + "xtensa", + + # unit testing + "unit", + ] "vendor": type: str "tier": From 9d9d1ff380bac29b89811bb691def9c2afe5590f Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Tue, 5 Mar 2024 17:56:23 +0800 Subject: [PATCH 0924/2402] ITE: drivers/i2c/target: Remove hardware reset setting In the interrupt pending routine, only the interrupt status needs to be cleared at the end of the interrupt routine. There is no need to do a hardware reset(HALT) to avoid clearing the next transfer interrupt when the current transfer is completed. Test: Testing this function does not cause I2C data/clk to get stuck on the system platform. Signed-off-by: Tim Lin --- drivers/i2c/i2c_ite_enhance.c | 4 ---- soc/ite/ec/common/chip_chipregs.h | 2 -- 2 files changed, 6 deletions(-) diff --git a/drivers/i2c/i2c_ite_enhance.c b/drivers/i2c/i2c_ite_enhance.c index c36d3597936..bea5ddefdb9 100644 --- a/drivers/i2c/i2c_ite_enhance.c +++ b/drivers/i2c/i2c_ite_enhance.c @@ -1045,10 +1045,6 @@ static void target_i2c_isr_dma(const struct device *dev, /* Write clear the peripheral status */ IT8XXX2_I2C_IRQ_ST(base) = interrupt_status; - if (interrupt_status & IT8XXX2_I2C_INT_ANY) { - /* Hardware reset */ - IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT; - } } static int target_i2c_isr_pio(const struct device *dev, diff --git a/soc/ite/ec/common/chip_chipregs.h b/soc/ite/ec/common/chip_chipregs.h index 9814e01d512..b42ceb0fd89 100644 --- a/soc/ite/ec/common/chip_chipregs.h +++ b/soc/ite/ec/common/chip_chipregs.h @@ -1433,8 +1433,6 @@ enum chip_pll_mode { #define IT8XXX2_I2C_IDR_CLR BIT(2) #define IT8XXX2_I2C_SLVDATAFLG BIT(1) #define IT8XXX2_I2C_P_CLR BIT(0) -#define IT8XXX2_I2C_INT_ANY (IT8XXX2_I2C_CNT_HOLD | IT8XXX2_I2C_IDW_CLR | \ - IT8XXX2_I2C_IDR_CLR | IT8XXX2_I2C_SLVDATAFLG) /* 0x13: Nack Status */ #define IT8XXX2_I2C_NST_CNS BIT(7) #define IT8XXX2_I2C_NST_ID_NACK BIT(3) From 28d08ada28ea4600eb06eda45e7b0c4a63686e14 Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Fri, 25 Aug 2023 15:24:48 -0700 Subject: [PATCH 0925/2402] include/zephyr: Add 'version' and 'since' tag to groups Based on information from doc/develop/api/overview.rst, add current version for some groups representing APIs, following the following table: - Experimental: 0.1.0 - Unstable: 0.8.0 - Stable: 1.0.0 Also based on doc/develop/api/overview.rst, add 'since' tag to the groups. Signed-off-by: Ederson de Souza Signed-off-by: Anas Nashif --- doc/_doxygen/groups.dox | 2 ++ include/zephyr/audio/codec.h | 2 ++ include/zephyr/audio/dmic.h | 2 ++ include/zephyr/bluetooth/bluetooth.h | 2 ++ include/zephyr/crypto/crypto.h | 2 ++ include/zephyr/device.h | 2 ++ include/zephyr/devicetree.h | 2 ++ include/zephyr/drivers/adc.h | 2 ++ include/zephyr/drivers/auxdisplay.h | 2 ++ include/zephyr/drivers/can.h | 2 ++ include/zephyr/drivers/can/transceiver.h | 2 ++ include/zephyr/drivers/clock_control.h | 2 ++ include/zephyr/drivers/counter.h | 2 ++ include/zephyr/drivers/dac.h | 2 ++ include/zephyr/drivers/dai.h | 2 ++ include/zephyr/drivers/disk.h | 2 ++ include/zephyr/drivers/display.h | 2 ++ include/zephyr/drivers/dma.h | 2 ++ include/zephyr/drivers/edac.h | 2 ++ include/zephyr/drivers/eeprom.h | 2 ++ include/zephyr/drivers/entropy.h | 2 ++ include/zephyr/drivers/flash.h | 2 ++ include/zephyr/drivers/fuel_gauge.h | 2 ++ include/zephyr/drivers/gnss.h | 2 ++ include/zephyr/drivers/gpio.h | 2 ++ include/zephyr/drivers/hwinfo.h | 2 ++ include/zephyr/drivers/i2c.h | 2 ++ include/zephyr/drivers/i2c/target/eeprom.h | 2 ++ include/zephyr/drivers/i2s.h | 2 ++ include/zephyr/drivers/i3c.h | 2 ++ include/zephyr/drivers/ipm.h | 2 ++ include/zephyr/drivers/kscan.h | 2 ++ include/zephyr/drivers/led.h | 2 ++ include/zephyr/drivers/lora.h | 2 ++ include/zephyr/drivers/mbox.h | 2 ++ include/zephyr/drivers/mipi_dbi.h | 2 ++ include/zephyr/drivers/mipi_dsi.h | 2 ++ include/zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h | 2 ++ include/zephyr/drivers/peci.h | 2 ++ include/zephyr/drivers/pinctrl.h | 2 ++ include/zephyr/drivers/pwm.h | 2 ++ include/zephyr/drivers/regulator.h | 2 ++ include/zephyr/drivers/reset.h | 2 ++ include/zephyr/drivers/retained_mem.h | 2 ++ include/zephyr/drivers/rtc.h | 2 ++ include/zephyr/drivers/sdhc.h | 2 ++ include/zephyr/drivers/sensor.h | 2 ++ include/zephyr/drivers/smbus.h | 2 ++ include/zephyr/drivers/spi.h | 2 ++ include/zephyr/drivers/uart.h | 4 ++++ include/zephyr/drivers/usb_c/usbc_tcpc.h | 2 ++ include/zephyr/drivers/usb_c/usbc_vbus.h | 2 ++ include/zephyr/drivers/video.h | 2 ++ include/zephyr/drivers/w1.h | 2 ++ include/zephyr/drivers/watchdog.h | 2 ++ include/zephyr/dsp/dsp.h | 2 ++ include/zephyr/fs/fcb.h | 2 ++ include/zephyr/fs/fs.h | 2 ++ include/zephyr/fs/nvs.h | 2 ++ include/zephyr/input/input.h | 2 ++ include/zephyr/kernel.h | 2 ++ include/zephyr/llext/llext.h | 2 ++ include/zephyr/logging/log.h | 2 ++ include/zephyr/logging/log_ctrl.h | 2 ++ include/zephyr/lorawan/lorawan.h | 2 ++ include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h | 2 ++ include/zephyr/mgmt/mcumgr/mgmt/mgmt.h | 2 ++ include/zephyr/net/coap.h | 2 ++ include/zephyr/net/conn_mgr_connectivity.h | 2 ++ include/zephyr/net/ieee802154.h | 4 ++++ include/zephyr/net/ieee802154_mgmt.h | 2 ++ include/zephyr/net/ieee802154_radio.h | 2 ++ include/zephyr/net/lwm2m.h | 2 ++ include/zephyr/net/mqtt.h | 2 ++ include/zephyr/net/net_core.h | 2 ++ include/zephyr/pm/pm.h | 2 ++ include/zephyr/random/random.h | 2 ++ include/zephyr/retention/blinfo.h | 2 ++ include/zephyr/retention/retention.h | 2 ++ include/zephyr/rtio/rtio.h | 2 ++ include/zephyr/settings/settings.h | 2 ++ include/zephyr/shell/shell.h | 2 ++ include/zephyr/storage/flash_map.h | 2 ++ include/zephyr/storage/stream_flash.h | 2 ++ include/zephyr/sys/barrier.h | 2 ++ include/zephyr/sys/util.h | 2 ++ include/zephyr/task_wdt/task_wdt.h | 2 ++ include/zephyr/usb_c/usbc.h | 2 ++ 88 files changed, 180 insertions(+) diff --git a/doc/_doxygen/groups.dox b/doc/_doxygen/groups.dox index 65b229a0ce9..c0c5ab1a7be 100644 --- a/doc/_doxygen/groups.dox +++ b/doc/_doxygen/groups.dox @@ -68,6 +68,8 @@ @brief Modem APIs @defgroup modem Modem APIs +@since 3.5 +@version 0.1.0 @{ @} diff --git a/include/zephyr/audio/codec.h b/include/zephyr/audio/codec.h index 082fd3e4ae3..1f56f006666 100644 --- a/include/zephyr/audio/codec.h +++ b/include/zephyr/audio/codec.h @@ -18,6 +18,8 @@ * @brief Abstraction for audio codecs * * @defgroup audio_codec_interface Audio Codec Interface + * @since 1.13 + * @version 0.1.0 * @ingroup audio_interface * @{ */ diff --git a/include/zephyr/audio/dmic.h b/include/zephyr/audio/dmic.h index e0582c45deb..9cf89ff1aaa 100644 --- a/include/zephyr/audio/dmic.h +++ b/include/zephyr/audio/dmic.h @@ -28,6 +28,8 @@ * @brief Abstraction for digital microphones * * @defgroup audio_dmic_interface Digital Microphone Interface + * @since 1.13 + * @version 0.1.0 * @ingroup audio_interface * @{ */ diff --git a/include/zephyr/bluetooth/bluetooth.h b/include/zephyr/bluetooth/bluetooth.h index bca9dbed22d..e9be94518ca 100644 --- a/include/zephyr/bluetooth/bluetooth.h +++ b/include/zephyr/bluetooth/bluetooth.h @@ -34,6 +34,8 @@ extern "C" { /** * @brief Generic Access Profile (GAP) * @defgroup bt_gap Generic Access Profile (GAP) + * @since 1.0 + * @version 1.0.0 * @ingroup bluetooth * @{ */ diff --git a/include/zephyr/crypto/crypto.h b/include/zephyr/crypto/crypto.h index 09168c3a522..b2e0b0f6e44 100644 --- a/include/zephyr/crypto/crypto.h +++ b/include/zephyr/crypto/crypto.h @@ -27,6 +27,8 @@ /** * @brief Crypto APIs * @defgroup crypto Crypto + * @since 1.7 + * @version 1.0.0 * @ingroup os_services * @{ */ diff --git a/include/zephyr/device.h b/include/zephyr/device.h index 00d1c1552f9..607cd76f6f2 100644 --- a/include/zephyr/device.h +++ b/include/zephyr/device.h @@ -24,6 +24,8 @@ extern "C" { /** * @brief Device Model * @defgroup device_model Device Model + * @since 1.0 + * @version 1.0.0 * @{ */ diff --git a/include/zephyr/devicetree.h b/include/zephyr/devicetree.h index 53eccff85a8..8ea39bf31c1 100644 --- a/include/zephyr/devicetree.h +++ b/include/zephyr/devicetree.h @@ -28,6 +28,8 @@ /** * @brief devicetree.h API * @defgroup devicetree Devicetree + * @since 2.2 + * @version 1.0.0 * @{ * @} */ diff --git a/include/zephyr/drivers/adc.h b/include/zephyr/drivers/adc.h index 01ec48672f3..18357cbd014 100644 --- a/include/zephyr/drivers/adc.h +++ b/include/zephyr/drivers/adc.h @@ -24,6 +24,8 @@ extern "C" { /** * @brief ADC driver APIs * @defgroup adc_interface ADC driver APIs + * @since 1.0 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/auxdisplay.h b/include/zephyr/drivers/auxdisplay.h index 0e1a99d919e..de106f5016e 100644 --- a/include/zephyr/drivers/auxdisplay.h +++ b/include/zephyr/drivers/auxdisplay.h @@ -15,6 +15,8 @@ /** * @brief Auxiliary (Text) Display Interface * @defgroup auxdisplay_interface Text Display Interface + * @since 3.4 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index f621ee14b7a..dabdde2c94a 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -30,6 +30,8 @@ extern "C" { /** * @brief CAN Interface * @defgroup can_interface CAN Interface + * @since 1.12 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/can/transceiver.h b/include/zephyr/drivers/can/transceiver.h index 19c22e7733d..c6f0b3c85cc 100644 --- a/include/zephyr/drivers/can/transceiver.h +++ b/include/zephyr/drivers/can/transceiver.h @@ -17,6 +17,8 @@ extern "C" { /** * @brief CAN Transceiver Driver APIs * @defgroup can_transceiver CAN Transceiver + * @since 3.1 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/clock_control.h b/include/zephyr/drivers/clock_control.h index 43947eb3735..d0806163769 100644 --- a/include/zephyr/drivers/clock_control.h +++ b/include/zephyr/drivers/clock_control.h @@ -17,6 +17,8 @@ /** * @brief Clock Control Interface * @defgroup clock_control_interface Clock Control Interface + * @since 1.0 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/counter.h b/include/zephyr/drivers/counter.h index 5da1a257d21..b21af71319f 100644 --- a/include/zephyr/drivers/counter.h +++ b/include/zephyr/drivers/counter.h @@ -16,6 +16,8 @@ /** * @brief Counter Interface * @defgroup counter_interface Counter Interface + * @since 1.14 + * @version 0.8.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/dac.h b/include/zephyr/drivers/dac.h index 3ad68c4c58e..57f61cce00b 100644 --- a/include/zephyr/drivers/dac.h +++ b/include/zephyr/drivers/dac.h @@ -21,6 +21,8 @@ extern "C" { /** * @brief DAC driver APIs * @defgroup dac_interface DAC driver APIs + * @since 2.3 + * @version 0.8.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/dai.h b/include/zephyr/drivers/dai.h index e0969292fbb..2e6f5704540 100644 --- a/include/zephyr/drivers/dai.h +++ b/include/zephyr/drivers/dai.h @@ -14,6 +14,8 @@ /** * @defgroup dai_interface DAI Interface + * @since 3.1 + * @version 0.1.0 * @ingroup io_interfaces * @brief DAI Interface * diff --git a/include/zephyr/drivers/disk.h b/include/zephyr/drivers/disk.h index ffa22a9071f..623b65118b3 100644 --- a/include/zephyr/drivers/disk.h +++ b/include/zephyr/drivers/disk.h @@ -21,6 +21,8 @@ /** * @brief Disk Driver Interface * @defgroup disk_driver_interface Disk Driver Interface + * @since 1.6 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/display.h b/include/zephyr/drivers/display.h index 010443e319f..854c728148a 100644 --- a/include/zephyr/drivers/display.h +++ b/include/zephyr/drivers/display.h @@ -15,6 +15,8 @@ /** * @brief Display Interface * @defgroup display_interface Display Interface + * @since 1.14 + * @version 0.8.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/dma.h b/include/zephyr/drivers/dma.h index 2905c6fc434..25e524c1e4f 100644 --- a/include/zephyr/drivers/dma.h +++ b/include/zephyr/drivers/dma.h @@ -24,6 +24,8 @@ extern "C" { /** * @brief DMA Interface * @defgroup dma_interface DMA Interface + * @since 1.5 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/edac.h b/include/zephyr/drivers/edac.h index bbdd304bb8e..e54cfc601a4 100644 --- a/include/zephyr/drivers/edac.h +++ b/include/zephyr/drivers/edac.h @@ -18,6 +18,8 @@ /** * @defgroup edac EDAC API + * @since 2.5 + * @version 0.8.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/eeprom.h b/include/zephyr/drivers/eeprom.h index 7da3d2a079d..2ab4d1f6082 100644 --- a/include/zephyr/drivers/eeprom.h +++ b/include/zephyr/drivers/eeprom.h @@ -19,6 +19,8 @@ /** * @brief EEPROM Interface * @defgroup eeprom_interface EEPROM Interface + * @since 2.1 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/entropy.h b/include/zephyr/drivers/entropy.h index 1e1573d29a8..dcb0c2d5ee5 100644 --- a/include/zephyr/drivers/entropy.h +++ b/include/zephyr/drivers/entropy.h @@ -16,6 +16,8 @@ /** * @brief Entropy Interface * @defgroup entropy_interface Entropy Interface + * @since 1.10 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/flash.h b/include/zephyr/drivers/flash.h index ae24ac96a75..d26e521ce90 100644 --- a/include/zephyr/drivers/flash.h +++ b/include/zephyr/drivers/flash.h @@ -45,6 +45,8 @@ struct flash_pages_layout { /** * @brief FLASH Interface * @defgroup flash_interface FLASH Interface + * @since 1.2 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/fuel_gauge.h b/include/zephyr/drivers/fuel_gauge.h index 760201d6f76..f4274ea161b 100644 --- a/include/zephyr/drivers/fuel_gauge.h +++ b/include/zephyr/drivers/fuel_gauge.h @@ -11,6 +11,8 @@ /** * @brief Fuel Gauge Interface * @defgroup fuel_gauge_interface Fuel Gauge Interface + * @since 3.3 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/gnss.h b/include/zephyr/drivers/gnss.h index 4c25bd84a43..c5448cefffc 100644 --- a/include/zephyr/drivers/gnss.h +++ b/include/zephyr/drivers/gnss.h @@ -15,6 +15,8 @@ /** * @brief GNSS Interface * @defgroup gnss_interface GNSS Interface + * @since 3.6 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/gpio.h b/include/zephyr/drivers/gpio.h index e6aca5490cf..1c5cd6e3390 100644 --- a/include/zephyr/drivers/gpio.h +++ b/include/zephyr/drivers/gpio.h @@ -32,6 +32,8 @@ extern "C" { /** * @brief GPIO Driver APIs * @defgroup gpio_interface GPIO Driver APIs + * @since 1.0 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/hwinfo.h b/include/zephyr/drivers/hwinfo.h index 7e9b7201e38..df412cdf29d 100644 --- a/include/zephyr/drivers/hwinfo.h +++ b/include/zephyr/drivers/hwinfo.h @@ -16,6 +16,8 @@ /** * @brief Hardware Information Interface * @defgroup hwinfo_interface Hardware Info Interface + * @since 1.14 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/i2c.h b/include/zephyr/drivers/i2c.h index 8f8b91aa67f..17dbb14010a 100644 --- a/include/zephyr/drivers/i2c.h +++ b/include/zephyr/drivers/i2c.h @@ -15,6 +15,8 @@ /** * @brief I2C Interface * @defgroup i2c_interface I2C Interface + * @since 1.0 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/i2c/target/eeprom.h b/include/zephyr/drivers/i2c/target/eeprom.h index 5dfde70d16a..e1d4a79cbee 100644 --- a/include/zephyr/drivers/i2c/target/eeprom.h +++ b/include/zephyr/drivers/i2c/target/eeprom.h @@ -15,6 +15,8 @@ /** * @brief I2C EEPROM Target Driver API * @defgroup i2c_eeprom_target_api I2C EEPROM Target Driver API + * @since 1.13 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/i2s.h b/include/zephyr/drivers/i2s.h index 8ef83ddee7f..987744638ab 100644 --- a/include/zephyr/drivers/i2s.h +++ b/include/zephyr/drivers/i2s.h @@ -14,6 +14,8 @@ /** * @defgroup i2s_interface I2S Interface + * @since 1.9 + * @version 1.0.0 * @ingroup io_interfaces * @brief I2S (Inter-IC Sound) Interface * diff --git a/include/zephyr/drivers/i3c.h b/include/zephyr/drivers/i3c.h index a814b7d436b..b5411dcd9a3 100644 --- a/include/zephyr/drivers/i3c.h +++ b/include/zephyr/drivers/i3c.h @@ -11,6 +11,8 @@ /** * @brief I3C Interface * @defgroup i3c_interface I3C Interface + * @since 3.2 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/ipm.h b/include/zephyr/drivers/ipm.h index 10ba85f8736..1d8ee204c4a 100644 --- a/include/zephyr/drivers/ipm.h +++ b/include/zephyr/drivers/ipm.h @@ -16,6 +16,8 @@ /** * @brief IPM Interface * @defgroup ipm_interface IPM Interface + * @since 1.0 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/kscan.h b/include/zephyr/drivers/kscan.h index 64e9e8bbb74..0c878df4ec3 100644 --- a/include/zephyr/drivers/kscan.h +++ b/include/zephyr/drivers/kscan.h @@ -28,6 +28,8 @@ extern "C" { /** * @brief KSCAN APIs * @defgroup kscan_interface Keyboard Scan Driver APIs + * @since 2.1 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/led.h b/include/zephyr/drivers/led.h index 8f01da811b6..f63a779fa9f 100644 --- a/include/zephyr/drivers/led.h +++ b/include/zephyr/drivers/led.h @@ -15,6 +15,8 @@ /** * @brief LED Interface * @defgroup led_interface LED Interface + * @since 1.12 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/lora.h b/include/zephyr/drivers/lora.h index 47ad4dbb483..a96ca885496 100644 --- a/include/zephyr/drivers/lora.h +++ b/include/zephyr/drivers/lora.h @@ -15,6 +15,8 @@ * @file * @brief Public LoRa APIs * @defgroup lora_api LoRa APIs + * @since 2.2 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/mbox.h b/include/zephyr/drivers/mbox.h index 654e3239ba9..f0ca6337bfb 100644 --- a/include/zephyr/drivers/mbox.h +++ b/include/zephyr/drivers/mbox.h @@ -20,6 +20,8 @@ extern "C" { /** * @brief MBOX Interface * @defgroup mbox_interface MBOX Interface + * @since 1.0 + * @version 0.1.0 * @ingroup io_interfaces * @{ * diff --git a/include/zephyr/drivers/mipi_dbi.h b/include/zephyr/drivers/mipi_dbi.h index 25192682b28..d0a75e18058 100644 --- a/include/zephyr/drivers/mipi_dbi.h +++ b/include/zephyr/drivers/mipi_dbi.h @@ -24,6 +24,8 @@ /** * @brief MIPI-DBI driver APIs * @defgroup mipi_dbi_interface MIPI-DBI driver APIs + * @since 3.6 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/mipi_dsi.h b/include/zephyr/drivers/mipi_dsi.h index f26a6928196..6ff8f0465ec 100644 --- a/include/zephyr/drivers/mipi_dsi.h +++ b/include/zephyr/drivers/mipi_dsi.h @@ -15,6 +15,8 @@ /** * @brief MIPI-DSI driver APIs * @defgroup mipi_dsi_interface MIPI-DSI driver APIs + * @since 3.1 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h b/include/zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h index b65b697f54f..2c805d923ae 100644 --- a/include/zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h +++ b/include/zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h @@ -14,6 +14,8 @@ /** * @brief Time-aware GPIO Interface * @defgroup tgpio_interface Time-aware GPIO Interface + * @since 3.5 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/peci.h b/include/zephyr/drivers/peci.h index af3f287a662..03970314b53 100644 --- a/include/zephyr/drivers/peci.h +++ b/include/zephyr/drivers/peci.h @@ -15,6 +15,8 @@ /** * @brief PECI Interface 3.0 * @defgroup peci_interface PECI Interface + * @since 2.1 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/pinctrl.h b/include/zephyr/drivers/pinctrl.h index e03456c76c3..3c2fefbe8a7 100644 --- a/include/zephyr/drivers/pinctrl.h +++ b/include/zephyr/drivers/pinctrl.h @@ -14,6 +14,8 @@ /** * @brief Pin Controller Interface * @defgroup pinctrl_interface Pin Controller Interface + * @since 3.0 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/pwm.h b/include/zephyr/drivers/pwm.h index 3affc596af7..b8a4cbd12ee 100644 --- a/include/zephyr/drivers/pwm.h +++ b/include/zephyr/drivers/pwm.h @@ -16,6 +16,8 @@ /** * @brief PWM Interface * @defgroup pwm_interface PWM Interface + * @since 1.0 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/regulator.h b/include/zephyr/drivers/regulator.h index 46a085d9239..463777eab9d 100644 --- a/include/zephyr/drivers/regulator.h +++ b/include/zephyr/drivers/regulator.h @@ -13,6 +13,8 @@ /** * @brief Regulator Interface * @defgroup regulator_interface Regulator Interface + * @since 2.4 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/reset.h b/include/zephyr/drivers/reset.h index fc49133e403..4e601ea8f9d 100644 --- a/include/zephyr/drivers/reset.h +++ b/include/zephyr/drivers/reset.h @@ -15,6 +15,8 @@ /** * @brief Reset Controller Interface * @defgroup reset_controller_interface Reset Controller Interface + * @since 3.1 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/retained_mem.h b/include/zephyr/drivers/retained_mem.h index 1a4ea8e0ccc..7f7003c300b 100644 --- a/include/zephyr/drivers/retained_mem.h +++ b/include/zephyr/drivers/retained_mem.h @@ -30,6 +30,8 @@ BUILD_ASSERT(!(sizeof(off_t) > sizeof(size_t)), /** * @brief Retained memory driver interface * @defgroup retained_mem_interface Retained memory driver interface + * @since 3.4 + * @version 0.8.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/rtc.h b/include/zephyr/drivers/rtc.h index 3cd704c7c89..ac5d5c0d350 100644 --- a/include/zephyr/drivers/rtc.h +++ b/include/zephyr/drivers/rtc.h @@ -16,6 +16,8 @@ /** * @brief RTC Interface * @defgroup rtc_interface RTC Interface + * @since 3.4 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/sdhc.h b/include/zephyr/drivers/sdhc.h index 092fca8a9ef..7934d059896 100644 --- a/include/zephyr/drivers/sdhc.h +++ b/include/zephyr/drivers/sdhc.h @@ -19,6 +19,8 @@ /** * @brief SDHC interface * @defgroup sdhc_interface SDHC interface + * @since 3.1 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/sensor.h b/include/zephyr/drivers/sensor.h index 53d55e1f1a3..70972361097 100644 --- a/include/zephyr/drivers/sensor.h +++ b/include/zephyr/drivers/sensor.h @@ -15,6 +15,8 @@ /** * @brief Sensor Interface * @defgroup sensor_interface Sensor Interface + * @since 1.2 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/smbus.h b/include/zephyr/drivers/smbus.h index c0348c367f1..da4a5c3a936 100644 --- a/include/zephyr/drivers/smbus.h +++ b/include/zephyr/drivers/smbus.h @@ -15,6 +15,8 @@ /** * @brief SMBus Interface * @defgroup smbus_interface SMBus Interface + * @since 3.4 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/spi.h b/include/zephyr/drivers/spi.h index 7042c73be0a..067d3419de5 100644 --- a/include/zephyr/drivers/spi.h +++ b/include/zephyr/drivers/spi.h @@ -15,6 +15,8 @@ /** * @brief SPI Interface * @defgroup spi_interface SPI Interface + * @since 1.0 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/uart.h b/include/zephyr/drivers/uart.h index 6d68da64a58..8db89e262f2 100644 --- a/include/zephyr/drivers/uart.h +++ b/include/zephyr/drivers/uart.h @@ -16,6 +16,8 @@ /** * @brief UART Interface * @defgroup uart_interface UART Interface + * @since 1.0 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ @@ -150,6 +152,8 @@ typedef void (*uart_irq_config_func_t)(const struct device *dev); * @} * * @defgroup uart_async Async UART API + * @since 1.14 + * @version 0.8.0 * @{ */ diff --git a/include/zephyr/drivers/usb_c/usbc_tcpc.h b/include/zephyr/drivers/usb_c/usbc_tcpc.h index 1b62a39db68..94b6b2049f6 100644 --- a/include/zephyr/drivers/usb_c/usbc_tcpc.h +++ b/include/zephyr/drivers/usb_c/usbc_tcpc.h @@ -18,6 +18,8 @@ /** * @brief USB Type-C Port Controller API * @defgroup usb_type_c_port_controller_api USB Type-C Port Controller API + * @since 3.1 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/usb_c/usbc_vbus.h b/include/zephyr/drivers/usb_c/usbc_vbus.h index 5ef9413dda4..eb159d7c509 100644 --- a/include/zephyr/drivers/usb_c/usbc_vbus.h +++ b/include/zephyr/drivers/usb_c/usbc_vbus.h @@ -18,6 +18,8 @@ /** * @brief USB-C VBUS API * @defgroup usbc_vbus_api USB-C VBUS API + * @since 3.3 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/video.h b/include/zephyr/drivers/video.h index ee9e2f2feee..d1a41b7d176 100644 --- a/include/zephyr/drivers/video.h +++ b/include/zephyr/drivers/video.h @@ -15,6 +15,8 @@ /** * @brief Video Interface * @defgroup video_interface Video Interface + * @since 2.1 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/w1.h b/include/zephyr/drivers/w1.h index a23f3577c5b..ed691f66733 100644 --- a/include/zephyr/drivers/w1.h +++ b/include/zephyr/drivers/w1.h @@ -26,6 +26,8 @@ extern "C" { /** * @brief 1-Wire Interface * @defgroup w1_interface 1-Wire Interface + * @since 3.2 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/watchdog.h b/include/zephyr/drivers/watchdog.h index d2bfb051839..5c53d10bbc7 100644 --- a/include/zephyr/drivers/watchdog.h +++ b/include/zephyr/drivers/watchdog.h @@ -11,6 +11,8 @@ /** * @brief Watchdog Interface * @defgroup watchdog_interface Watchdog Interface + * @since 1.0 + * @version 1.0.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/dsp/dsp.h b/include/zephyr/dsp/dsp.h index cfaa817cf2e..beef08fb184 100644 --- a/include/zephyr/dsp/dsp.h +++ b/include/zephyr/dsp/dsp.h @@ -32,6 +32,8 @@ /** * @brief DSP Interface * @defgroup math_dsp DSP Interface + * @since 3.3 + * @version 0.1.0 */ #include diff --git a/include/zephyr/fs/fcb.h b/include/zephyr/fs/fcb.h index 9e9cddf0079..959a60b3286 100644 --- a/include/zephyr/fs/fcb.h +++ b/include/zephyr/fs/fcb.h @@ -24,6 +24,8 @@ extern "C" { /** * @defgroup fcb Flash Circular Buffer (FCB) + * @since 1.11 + * @version 1.0.0 * @ingroup file_system_storage * @{ * @} diff --git a/include/zephyr/fs/fs.h b/include/zephyr/fs/fs.h index 73782134c8a..f52cba8c1ba 100644 --- a/include/zephyr/fs/fs.h +++ b/include/zephyr/fs/fs.h @@ -20,6 +20,8 @@ extern "C" { /** * @brief File System APIs * @defgroup file_system_api File System APIs + * @since 1.5 + * @version 1.0.0 * @ingroup os_services * @{ */ diff --git a/include/zephyr/fs/nvs.h b/include/zephyr/fs/nvs.h index 1d0a4e3b1d3..313e9016095 100644 --- a/include/zephyr/fs/nvs.h +++ b/include/zephyr/fs/nvs.h @@ -19,6 +19,8 @@ extern "C" { /** * @brief Non-volatile Storage (NVS) * @defgroup nvs Non-volatile Storage (NVS) + * @since 1.12 + * @version 1.0.0 * @ingroup file_system_storage * @{ * @} diff --git a/include/zephyr/input/input.h b/include/zephyr/input/input.h index 0f6f8fdc54e..eb1b798d15c 100644 --- a/include/zephyr/input/input.h +++ b/include/zephyr/input/input.h @@ -10,6 +10,8 @@ /** * @brief Input Interface * @defgroup input_interface Input Interface + * @since 3.4 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/kernel.h b/include/zephyr/kernel.h index 9a7a141cb6f..da43eea9771 100644 --- a/include/zephyr/kernel.h +++ b/include/zephyr/kernel.h @@ -38,6 +38,8 @@ BUILD_ASSERT(sizeof(intptr_t) == sizeof(long)); /** * @brief Kernel APIs * @defgroup kernel_apis Kernel APIs + * @since 1.0 + * @version 1.0.0 * @{ * @} */ diff --git a/include/zephyr/llext/llext.h b/include/zephyr/llext/llext.h index 0a006dc53b7..e09e21c14f6 100644 --- a/include/zephyr/llext/llext.h +++ b/include/zephyr/llext/llext.h @@ -21,6 +21,8 @@ extern "C" { /** * @brief Linkable loadable extensions * @defgroup llext Linkable loadable extensions + * @since 3.5 + * @version 0.1.0 * @ingroup os_services * @{ */ diff --git a/include/zephyr/logging/log.h b/include/zephyr/logging/log.h index d04f5b1ab82..3baba971dc6 100644 --- a/include/zephyr/logging/log.h +++ b/include/zephyr/logging/log.h @@ -18,6 +18,8 @@ extern "C" { /** * @brief Logging * @defgroup logging Logging + * @since 1.13 + * @version 1.0.0 * @ingroup os_services * @{ * @} diff --git a/include/zephyr/logging/log_ctrl.h b/include/zephyr/logging/log_ctrl.h index 9e5e3e3c077..56b0458c2ec 100644 --- a/include/zephyr/logging/log_ctrl.h +++ b/include/zephyr/logging/log_ctrl.h @@ -18,6 +18,7 @@ extern "C" { /** * @brief Logger * @defgroup logger Logger system + * @since 1.13 * @ingroup logging * @{ * @} @@ -26,6 +27,7 @@ extern "C" { /** * @brief Logger control API * @defgroup log_ctrl Logger control API + * @since 1.13 * @ingroup logger * @{ */ diff --git a/include/zephyr/lorawan/lorawan.h b/include/zephyr/lorawan/lorawan.h index b0f0117d91d..1bad5130730 100644 --- a/include/zephyr/lorawan/lorawan.h +++ b/include/zephyr/lorawan/lorawan.h @@ -11,6 +11,8 @@ * @file * @brief Public LoRaWAN APIs * @defgroup lorawan_api LoRaWAN APIs + * @since 2.5 + * @version 0.1.0 * @ingroup connectivity * @{ */ diff --git a/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h b/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h index 50bc3fb7780..0014254df05 100644 --- a/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h +++ b/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h @@ -10,6 +10,8 @@ /** * @brief EC Host Command Interface * @defgroup ec_host_cmd_interface EC Host Command Interface + * @since 2.4 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/mgmt/mcumgr/mgmt/mgmt.h b/include/zephyr/mgmt/mcumgr/mgmt/mgmt.h index 7699dd57cc6..9a139b3a04b 100644 --- a/include/zephyr/mgmt/mcumgr/mgmt/mgmt.h +++ b/include/zephyr/mgmt/mcumgr/mgmt/mgmt.h @@ -20,6 +20,8 @@ extern "C" { /** * @brief MCUmgr mgmt API * @defgroup mcumgr_mgmt_api MCUmgr mgmt API + * @since 1.11 + * @version 1.0.0 * @ingroup mcumgr * @{ */ diff --git a/include/zephyr/net/coap.h b/include/zephyr/net/coap.h index da241a7734a..43073a5b20b 100644 --- a/include/zephyr/net/coap.h +++ b/include/zephyr/net/coap.h @@ -17,6 +17,8 @@ /** * @brief COAP library * @defgroup coap COAP Library + * @since 1.10 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/include/zephyr/net/conn_mgr_connectivity.h b/include/zephyr/net/conn_mgr_connectivity.h index 0d92cdbf8d7..d083509b437 100644 --- a/include/zephyr/net/conn_mgr_connectivity.h +++ b/include/zephyr/net/conn_mgr_connectivity.h @@ -25,6 +25,8 @@ extern "C" { /** * @brief Connection Manager Connectivity API * @defgroup conn_mgr_connectivity Connection Manager Connectivity API + * @since 3.4 + * @version 0.1.0 * @ingroup networking * @{ */ diff --git a/include/zephyr/net/ieee802154.h b/include/zephyr/net/ieee802154.h index e4ef8bba6f8..927a9036db3 100644 --- a/include/zephyr/net/ieee802154.h +++ b/include/zephyr/net/ieee802154.h @@ -26,6 +26,8 @@ extern "C" { /** * @defgroup ieee802154 IEEE 802.15.4 and Thread APIs + * @since 1.0 + * @version 0.8.0 * @ingroup connectivity * * @brief IEEE 802.15.4 native and OpenThread L2, configuration, management and @@ -76,6 +78,8 @@ extern "C" { /** * @defgroup ieee802154_l2 IEEE 802.15.4 L2 + * @since 1.0 + * @version 0.8.0 * @ingroup ieee802154 * * @brief IEEE 802.15.4 L2 APIs diff --git a/include/zephyr/net/ieee802154_mgmt.h b/include/zephyr/net/ieee802154_mgmt.h index 3711e818d24..1f08c0b73c0 100644 --- a/include/zephyr/net/ieee802154_mgmt.h +++ b/include/zephyr/net/ieee802154_mgmt.h @@ -23,6 +23,8 @@ extern "C" { /** * @defgroup ieee802154_mgmt IEEE 802.15.4 Net Management + * @since 1.0 + * @version 0.8.0 * @ingroup ieee802154 * * @brief IEEE 802.15.4 net management library diff --git a/include/zephyr/net/ieee802154_radio.h b/include/zephyr/net/ieee802154_radio.h index 259d67b4321..922d43c4b51 100644 --- a/include/zephyr/net/ieee802154_radio.h +++ b/include/zephyr/net/ieee802154_radio.h @@ -29,6 +29,8 @@ extern "C" { /** * @defgroup ieee802154_driver IEEE 802.15.4 Drivers + * @since 1.0 + * @version 0.8.0 * @ingroup ieee802154 * * @brief IEEE 802.15.4 driver API diff --git a/include/zephyr/net/lwm2m.h b/include/zephyr/net/lwm2m.h index ac6a7b6039d..e68f5fb47ad 100644 --- a/include/zephyr/net/lwm2m.h +++ b/include/zephyr/net/lwm2m.h @@ -8,6 +8,8 @@ /** @file lwm2m.h * * @defgroup lwm2m_api LwM2M high-level API + * @since 1.9 + * @version 0.8.0 * @ingroup networking * @{ * @brief LwM2M high-level API diff --git a/include/zephyr/net/mqtt.h b/include/zephyr/net/mqtt.h index 0067c9ae8bd..987b3726caf 100644 --- a/include/zephyr/net/mqtt.h +++ b/include/zephyr/net/mqtt.h @@ -7,6 +7,8 @@ /** @file mqtt.h * * @defgroup mqtt_socket MQTT Client library + * @since 1.14 + * @version 0.8.0 * @ingroup networking * @{ * @brief MQTT Client Implementation diff --git a/include/zephyr/net/net_core.h b/include/zephyr/net/net_core.h index 7def1b09ff7..0ec70fd6212 100644 --- a/include/zephyr/net/net_core.h +++ b/include/zephyr/net/net_core.h @@ -29,6 +29,8 @@ extern "C" { /** * @brief Networking * @defgroup networking Networking + * @since 1.0 + * @version 1.0.0 * @ingroup connectivity * @{ * @} diff --git a/include/zephyr/pm/pm.h b/include/zephyr/pm/pm.h index 03062eefd12..09138bf1871 100644 --- a/include/zephyr/pm/pm.h +++ b/include/zephyr/pm/pm.h @@ -21,6 +21,7 @@ extern "C" { /** * @brief System and device power management * @defgroup subsys_pm Power Management (PM) + * @since 1.2 * @ingroup os_services * @{ * @} @@ -29,6 +30,7 @@ extern "C" { /** * @brief System Power Management API * @defgroup subsys_pm_sys System + * @since 1.2 * @ingroup subsys_pm * @{ */ diff --git a/include/zephyr/random/random.h b/include/zephyr/random/random.h index e4b52f683aa..e9c2e2968f5 100644 --- a/include/zephyr/random/random.h +++ b/include/zephyr/random/random.h @@ -28,6 +28,8 @@ /** * @brief Random Function APIs * @defgroup random_api Random Function APIs + * @since 1.0 + * @version 1.0.0 * @ingroup crypto * @{ */ diff --git a/include/zephyr/retention/blinfo.h b/include/zephyr/retention/blinfo.h index 0ecd051771f..e3a6e6b570d 100644 --- a/include/zephyr/retention/blinfo.h +++ b/include/zephyr/retention/blinfo.h @@ -27,6 +27,8 @@ extern "C" { /** * @brief Bootloader info interface * @defgroup bootloader_info_interface Bootloader info interface + * @since 3.5 + * @version 0.1.0 * @ingroup retention_api * @{ */ diff --git a/include/zephyr/retention/retention.h b/include/zephyr/retention/retention.h index 2ad3bb804f4..b92007d1eed 100644 --- a/include/zephyr/retention/retention.h +++ b/include/zephyr/retention/retention.h @@ -26,6 +26,8 @@ extern "C" { /** * @brief Retention API * @defgroup retention_api Retention API + * @since 3.4 + * @version 0.1.0 * @ingroup os_services * @{ */ diff --git a/include/zephyr/rtio/rtio.h b/include/zephyr/rtio/rtio.h index b38644c6efb..4fc8cf23bda 100644 --- a/include/zephyr/rtio/rtio.h +++ b/include/zephyr/rtio/rtio.h @@ -46,6 +46,8 @@ extern "C" { /** * @brief RTIO * @defgroup rtio RTIO + * @since 3.2 + * @version 0.1.0 * @ingroup os_services * @{ */ diff --git a/include/zephyr/settings/settings.h b/include/zephyr/settings/settings.h index d26696761ee..0bae0658d43 100644 --- a/include/zephyr/settings/settings.h +++ b/include/zephyr/settings/settings.h @@ -28,6 +28,8 @@ extern "C" { /** * @defgroup settings Settings + * @since 1.12 + * @version 1.0.0 * @ingroup file_system_storage * @{ */ diff --git a/include/zephyr/shell/shell.h b/include/zephyr/shell/shell.h index 0bcb831c90d..30b1654fdfd 100644 --- a/include/zephyr/shell/shell.h +++ b/include/zephyr/shell/shell.h @@ -69,6 +69,8 @@ extern "C" { /** * @brief Shell API * @defgroup shell_api Shell API + * @since 1.14 + * @version 1.0.0 * @ingroup os_services * @{ */ diff --git a/include/zephyr/storage/flash_map.h b/include/zephyr/storage/flash_map.h index 12f4f4c34a2..37b7c7f3223 100644 --- a/include/zephyr/storage/flash_map.h +++ b/include/zephyr/storage/flash_map.h @@ -18,6 +18,8 @@ * @brief Abstraction over flash partitions/areas and their drivers * * @defgroup flash_area_api flash area Interface + * @since 1.11 + * @version 1.0.0 * @ingroup storage_apis * @{ */ diff --git a/include/zephyr/storage/stream_flash.h b/include/zephyr/storage/stream_flash.h index 282e51af9b3..9202d5d8cc7 100644 --- a/include/zephyr/storage/stream_flash.h +++ b/include/zephyr/storage/stream_flash.h @@ -17,6 +17,8 @@ * @brief Abstraction over stream writes to flash * * @defgroup stream_flash Stream to flash interface + * @since 2.3 + * @version 0.1.0 * @ingroup storage_apis * @{ */ diff --git a/include/zephyr/sys/barrier.h b/include/zephyr/sys/barrier.h index 5390cb38cf0..49acfc590ce 100644 --- a/include/zephyr/sys/barrier.h +++ b/include/zephyr/sys/barrier.h @@ -25,6 +25,8 @@ extern "C" { /** * @addtogroup barrier_apis Barrier Services APIs + * @since 3.4 + * @version 0.1.0 * @ingroup kernel_apis * @{ */ diff --git a/include/zephyr/sys/util.h b/include/zephyr/sys/util.h index 72af79a473f..3a1bf3f553b 100644 --- a/include/zephyr/sys/util.h +++ b/include/zephyr/sys/util.h @@ -38,6 +38,8 @@ extern "C" { /** * @defgroup sys-util Utility Functions + * @since 2.4 + * @version 0.1.0 * @ingroup utilities * @{ */ diff --git a/include/zephyr/task_wdt/task_wdt.h b/include/zephyr/task_wdt/task_wdt.h index 3b064168fc4..e14ef5814fe 100644 --- a/include/zephyr/task_wdt/task_wdt.h +++ b/include/zephyr/task_wdt/task_wdt.h @@ -24,6 +24,8 @@ /** * @brief Task Watchdog APIs * @defgroup task_wdt_api Task Watchdog APIs + * @since 2.5 + * @version 0.8.0 * @ingroup os_services * @{ */ diff --git a/include/zephyr/usb_c/usbc.h b/include/zephyr/usb_c/usbc.h index db3045d03c1..5926793777b 100644 --- a/include/zephyr/usb_c/usbc.h +++ b/include/zephyr/usb_c/usbc.h @@ -25,6 +25,8 @@ extern "C" { /** * @brief USB-C Device APIs * @defgroup _usbc_device_api USB-C Device API + * @since 3.3 + * @version 0.1.0 * @{ */ From 4fe0a1dc7f84ff8748c93a1a1c8286a8a88800db Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Tue, 31 Oct 2023 16:25:14 -0700 Subject: [PATCH 0926/2402] doc: Include doxmlparser on requirements.txt It will be necessary to parse the doxygen XML files to extract `since` and `version` from them. Signed-off-by: Ederson de Souza --- doc/requirements.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/requirements.txt b/doc/requirements.txt index b1f20fbed1d..a1055014861 100644 --- a/doc/requirements.txt +++ b/doc/requirements.txt @@ -16,3 +16,6 @@ pykwalify # Used by pytest-twister-harness plugin pytest + +# Doxygen doxmlparser +doxmlparser From 9ab243d671ad09d8c148aa49586c717c7745e99b Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Fri, 25 Aug 2023 13:58:52 -0700 Subject: [PATCH 0927/2402] doc: Generate develop/api/overview.rst API table from doxygen A new extension, api_overview.py, is used to, leveraging doxygen's Python module doxmlparser, parse the doxygen generated XML files. All groups ('defgroup' and 'addtogroup' tags) are collected, alongside their 'version' and 'since' info. From there, a new Sphinx directive `api-overview-table` is populated, including the name of the group, and if available, their 'since' and 'version' information. Signed-off-by: Ederson de Souza Signed-off-by: Anas Nashif --- doc/_extensions/zephyr/api_overview.py | 173 +++++++++++ doc/conf.py | 4 + doc/develop/api/api_lifecycle.rst | 25 ++ doc/develop/api/overview.rst | 407 +++---------------------- 4 files changed, 236 insertions(+), 373 deletions(-) create mode 100644 doc/_extensions/zephyr/api_overview.py diff --git a/doc/_extensions/zephyr/api_overview.py b/doc/_extensions/zephyr/api_overview.py new file mode 100644 index 00000000000..74a4d35ba69 --- /dev/null +++ b/doc/_extensions/zephyr/api_overview.py @@ -0,0 +1,173 @@ +# Copyright (c) 2023 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +import doxmlparser + +from docutils import nodes +from doxmlparser.compound import DoxCompoundKind +from pathlib import Path +from sphinx.application import Sphinx +from sphinx.util.docutils import SphinxDirective +from typing import Any, Dict + + +class ApiOverview(SphinxDirective): + """ + This is a Zephyr directive to generate a table containing an overview + of all APIs. This table will show the API name, version and since which + version it is present - all information extracted from Doxygen XML output. + + It is exclusively used by the doc/develop/api/overview.rst page. + + Configuration options: + + api_overview_doxygen_xml_dir: Doxygen xml output directory + api_overview_doxygen_base_url: Doxygen base html directory + """ + + def run(self): + return [self.env.api_overview_table] + + +def get_group(innergroup, all_groups): + try: + return [ + g + for g in all_groups + if g.get_compounddef()[0].get_id() == innergroup.get_refid() + ][0] + except IndexError as e: + raise Exception(f"Unexpected group {innergroup.get_refid()}") from e + + +def visit_group(app, group, all_groups, rows, indent=0): + version = since = "" + github_uri = "https://github.com/zephyrproject-rtos/zephyr/releases/tag/" + cdef = group.get_compounddef()[0] + + ssects = [ + s for p in cdef.get_detaileddescription().get_para() for s in p.get_simplesect() + ] + for sect in ssects: + if sect.get_kind() == "since": + since = sect.get_para()[0].get_valueOf_() + elif sect.get_kind() == "version": + version = sect.get_para()[0].get_valueOf_() + + if since: + since_url = nodes.inline() + reference = nodes.reference(text=f"v{since.strip()}.0", refuri=f"{github_uri}/v{since.strip()}.0") + reference.attributes["internal"] = True + since_url += reference + else: + since_url = nodes.Text("") + + url_base = Path(app.config.api_overview_doxygen_base_url) + url = url_base / f"{cdef.get_id()}.html" + + title = cdef.get_title() + + row_node = nodes.row() + + # Next entry will contain the spacer and the link with API name + entry = nodes.entry() + span = nodes.Text("".join(["\U000000A0"] * indent)) + entry += span + + # API name with link + inline = nodes.inline() + reference = nodes.reference(text=title, refuri=str(url)) + reference.attributes["internal"] = True + inline += reference + entry += inline + row_node += entry + + version_node = nodes.Text(version) + # Finally, add version and since + for cell in [version_node, since_url]: + entry = nodes.entry() + entry += cell + row_node += entry + rows.append(row_node) + + for innergroup in cdef.get_innergroup(): + visit_group( + app, get_group(innergroup, all_groups), all_groups, rows, indent + 6 + ) + + +def parse_xml_dir(dir_name): + groups = [] + root = doxmlparser.index.parse(Path(dir_name) / "index.xml", True) + for compound in root.get_compound(): + if compound.get_kind() == DoxCompoundKind.GROUP: + file_name = Path(dir_name) / f"{compound.get_refid()}.xml" + groups.append(doxmlparser.compound.parse(file_name, True)) + + return groups + + +def generate_table(app, toplevel, groups): + table = nodes.table() + tgroup = nodes.tgroup() + + thead = nodes.thead() + thead_row = nodes.row() + for header_name in ["API", "Version", "Available in Zephyr Since"]: + colspec = nodes.colspec() + tgroup += colspec + + entry = nodes.entry() + entry += nodes.Text(header_name) + thead_row += entry + thead += thead_row + tgroup += thead + + rows = [] + tbody = nodes.tbody() + for t in toplevel: + visit_group(app, t, groups, rows) + tbody.extend(rows) + tgroup += tbody + + table += tgroup + + return table + + +def sync_contents(app: Sphinx) -> None: + if app.config.doxyrunner_outdir: + doxygen_out_dir = Path(app.config.doxyrunner_outdir) + else: + doxygen_out_dir = Path(app.outdir) / "_doxygen" + + doxygen_xml_dir = doxygen_out_dir / "xml" + groups = parse_xml_dir(doxygen_xml_dir) + + toplevel = [ + g + for g in groups + if g.get_compounddef()[0].get_id() + not in [ + i.get_refid() + for h in [j.get_compounddef()[0].get_innergroup() for j in groups] + for i in h + ] + ] + + app.builder.env.api_overview_table = generate_table(app, toplevel, groups) + + +def setup(app) -> Dict[str, Any]: + app.add_config_value("api_overview_doxygen_xml_dir", "html/doxygen/xml", "env") + app.add_config_value("api_overview_doxygen_base_url", "../../doxygen/html", "env") + + app.add_directive("api-overview-table", ApiOverview) + + app.connect("builder-inited", sync_contents) + + return { + "version": "0.1", + "parallel_read_safe": True, + "parallel_write_safe": True, + } diff --git a/doc/conf.py b/doc/conf.py index c9b8453a28b..5af6ce51fce 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -95,6 +95,7 @@ "sphinx_togglebutton", "zephyr.external_content", "zephyr.domain", + "zephyr.api_overview", ] # Only use SVG converter when it is really needed, e.g. LaTeX. @@ -364,6 +365,9 @@ linkcheck_workers = 10 linkcheck_anchors = False +# -- Options for zephyr.api_overview -------------------------------------- + +api_overview_doxygen_base_url = "../../doxygen/html" def setup(app): # theme customizations diff --git a/doc/develop/api/api_lifecycle.rst b/doc/develop/api/api_lifecycle.rst index f4fae1eef7c..9b17163caca 100644 --- a/doc/develop/api/api_lifecycle.rst +++ b/doc/develop/api/api_lifecycle.rst @@ -20,6 +20,9 @@ no longer optimal or supported by the underlying platforms. An up-to-date table of all APIs and their maturity level can be found in the :ref:`api_overview` page. + +.. _api_lifecycle_experimental: + Experimental ************* @@ -36,6 +39,10 @@ The following requirements apply to all new APIs: of said API (in the case of peripheral APIs, this corresponds to one driver) - At least one sample using the new API (may only build on one single board) +When introducing a new and experimental API, mark the API version in the headers +where the API is defined. An experimental API shall have a version where the minor +version is up to one (0.1.z). (see `api overview `) + Peripheral APIs (Hardware Related) ================================== @@ -46,6 +53,8 @@ the Architecture working group consisting of representatives from different vend The API shall be promoted to ``unstable`` when it has at least two implementations on different hardware platforms. +.. _api_lifecycle_unstable: + Unstable ******** @@ -53,6 +62,10 @@ The API is in the process of settling, but has not yet had sufficient real-world testing to be considered stable. The API is considered generic in nature and can be used on different hardware platforms. +When the API changes status to unstable API, mark the API version in the headers +where the API is defined. Unstable APIs shall have a version where the minor +version is larger than one (0.y.z | y > 1 ). (see `api overview `) + .. note:: Changes will not be announced. @@ -69,6 +82,8 @@ Hardware Agnostic APIs For hardware agnostic APIs, multiple applications using it are required to promote an API from ``experimental`` to ``unstable``. +.. _api_lifecycle_stable: + Stable ******* @@ -94,6 +109,11 @@ In order to declare an API ``stable``, the following steps need to be followed: `Zephyr Architecture meeting`_ where, barring any objections, the Pull Request will be merged + +When the API changes status to stable API, mark the API version in the headers +where the API is defined. Stable APIs shall have a version where the major +version is one or larger (x.y.z | x >= 1 ). (see `api overview `) + .. _breaking_api_changes: Introducing breaking API changes @@ -177,6 +197,11 @@ for it to be discussed and ultimately even voted on in the `Zephyr TSC meeting`_ If the Pull Request is merged then an email must be sent to the ``devel`` and ``user`` mailing lists informing them of the change. +The API version shall be changed to signal backward incompatible changes. This +is achieved by incrementing the major version (X.y.z | X > 1). It MAY also +include minor and patch level changes. Patch and minor versions MUST be reset to +0 when major version is incremented. (see `api overview `) + .. note:: Breaking API changes will be listed and described in the migration guide. diff --git a/doc/develop/api/overview.rst b/doc/develop/api/overview.rst index 62343f2192c..422aa43d94e 100644 --- a/doc/develop/api/overview.rst +++ b/doc/develop/api/overview.rst @@ -7,388 +7,49 @@ The table lists Zephyr's APIs and information about them, including their current :ref:`stability level `. More details about API changes between major releases are available in the :ref:`zephyr_release_notes`. -.. Keep this list sorted by the name of the API as it appears - in the HTML, *NOT* the :ref: label +The version column uses `semantic version `_, and has the +following expectations: -.. list-table:: - :header-rows: 1 + * Major version zero (0.y.z) is for initial development. Anything MAY + change at any time. The public API SHOULD NOT be considered stable. - * - API - - Status - - Version Introduced + * If minor version is up to one (0.1.z), API is considered + :ref:`experimental `. + * If minor version is larger than one (0.y.z | y > 1), API is considered + :ref:`unstable `. - * - :ref:`adc_api` - - Stable - - 1.0 + * Version 1.0.0 defines the public API. The way in which the version number + is incremented after this release is dependent on this public API and how it + changes. - * - :ref:`audio_codec_api` - - Experimental - - 1.13 + * APIs with major versions equal or larger than one (x.y.z | x >= 1 ) are + considered :ref:`stable `. + * All existing stable APIs in Zephyr will be start with version 1.0.0. - * - :ref:`audio_dmic_api` - - Experimental - - 1.13 + * Patch version Z (x.y.Z | x > 0) MUST be incremented if only backwards + compatible bug fixes are introduced. A bug fix is defined as an internal + change that fixes incorrect behavior. - * - :ref:`auxdisplay_api` - - Experimental - - 3.4 + * Minor version Y (x.Y.z | x > 0) MUST be incremented if new, backwards + compatible functionality is introduced to the public API. It MUST be + incremented if any public API functionality is marked as deprecated. It MAY + be incremented if substantial new functionality or improvements are + introduced within the private code. It MAY include patch level changes. + Patch version MUST be reset to 0 when minor version is incremented. - * - :ref:`barriers_api` - - Experimental - - 3.4 + * Major version X (x.Y.z | x > 0) MUST be incremented if a compatibility + breaking change was made to the API. - * - :ref:`blinfo_api` - - Experimental - - 3.5 +.. note:: + Version for existing APIs are initially set based on the current state of the + APIs: - * - :ref:`bluetooth_api` - - Stable - - 1.0 + - 0.1.0 denotes an :ref:`experimental ` API + - 0.8.0 denote an :ref:`unstable ` API, + - and finally 1.0.0 indicates a :ref:`stable ` APIs. - * - :ref:`clock_control_api` - - Stable - - 1.0 + Changes to APIs in the future will require adapting the version following the + guidelines above. - * - :ref:`coap_sock_interface` - - Unstable - - 1.10 - * - :ref:`conn_mgr_docs` - - Experimental - - 3.4.0 - - * - :ref:`can_api` - - Stable - - 1.14 - - * - :ref:`can_transceiver_api` - - Experimental - - 3.1 - - * - :ref:`charger_api` - - Experimental - - 3.5 - - * - :ref:`counter_api` - - Unstable - - 1.14 - - * - :ref:`crypto_api` - - Stable - - 1.7 - - * - :ref:`dac_api` - - Unstable - - 2.3 - - * - :ref:`dai_api` - - Experimental - - 3.1 - - * - :ref:`dma_api` - - Stable - - 1.5 - - * - :ref:`device_model_api` - - Stable - - 1.0 - - * - :ref:`devicetree_api` - - Stable - - 2.2 - - * - :ref:`disk_access_api` - - Stable - - 1.6 - - * - :ref:`display_api` - - Unstable - - 1.14 - - * - :ref:`ec_host_cmd_backend_api` - - Experimental - - 2.4 - - * - :ref:`edac_api` - - Unstable - - 2.5 - - * - :ref:`eeprom_api` - - Stable - - 2.1 - - * - :ref:`entropy_api` - - Stable - - 1.10 - - * - :ref:`file_system_api` - - Stable - - 1.5 - - * - :ref:`flash_api` - - Stable - - 1.2 - - * - :ref:`fcb_api` - - Stable - - 1.11 - - * - :ref:`fuel_gauge_api` - - Experimental - - 3.3 - - * - :ref:`flash_map_api` - - Stable - - 1.11 - - * - :ref:`gnss_api` - - Experimental - - 3.6 - - * - :ref:`gpio_api` - - Stable - - 1.0 - - * - :ref:`hwinfo_api` - - Stable - - 1.14 - - * - :ref:`i2c_eeprom_target_api` - - Stable - - 1.13 - - * - :ref:`i2c_api` - - Stable - - 1.0 - - * - :ref:`i2c-target-api` - - Experimental - - 1.12 - - * - :ref:`i2s_api` - - Stable - - 1.9 - - * - :ref:`i3c_api` - - Experimental - - 3.2 - - * - :ref:`ieee802154_driver_api` - - Unstable - - 1.0 - - * - :ref:`ieee802154_l2_api` - - Unstable - - 1.0 - - * - :ref:`ieee802154_mgmt_api` - - Unstable - - 1.0 - - * - :ref:`input` - - Experimental - - 3.4 - - * - :ref:`ipm_api` - - Stable - - 1.0 - - * - :ref:`kscan_api` - - Stable - - 2.1 - - * - :ref:`kernel_api` - - Stable - - 1.0 - - * - :ref:`led_api` - - Stable - - 1.12 - - * - :ref:`lwm2m_interface` - - Unstable - - 1.9 - - * - :ref:`llext` - - Experimental - - 3.5 - - * - :ref:`logging_api` - - Stable - - 1.13 - - * - :ref:`lora_api` - - Experimental - - 2.2 - - * - :ref:`lorawan_api` - - Experimental - - 2.5 - - * - :ref:`mbox_api` - - Experimental - - 1.0 - - * - :ref:`mcu_mgr` - - Stable - - 1.11 - - * - :ref:`modem` - - Experimental - - 3.5 - - * - :ref:`mqtt_socket_interface` - - Unstable - - 1.14 - - * - :ref:`mipi_dbi_api` - - Experimental - - 3.6 - - * - :ref:`mipi_dsi_api` - - Experimental - - 3.1 - - * - :ref:`misc_api` - - Stable - - 1.0 - - * - :ref:`networking_api` - - Stable - - 1.0 - - * - :ref:`nvs_api` - - Stable - - 1.12 - - * - :ref:`peci_api` - - Stable - - 2.1 - - * - :ref:`ps2_api` - - Stable - - 2.1 - - * - :ref:`pwm_api` - - Stable - - 1.0 - - * - :ref:`pinctrl_api` - - Experimental - - 3.0 - - * - :ref:`pm_api` - - Experimental - - 1.2 - - * - :ref:`random_api` - - Stable - - 1.0 - - * - :ref:`regulator_api` - - Experimental - - 2.4 - - * - :ref:`reset_api` - - Experimental - - 3.1 - - * - :ref:`retained_mem_api` - - Unstable - - 3.4 - - * - :ref:`retention_api` - - Experimental - - 3.4 - - * - :ref:`rtc_api` - - Experimental - - 3.4 - - * - :ref:`rtio_api` - - Experimental - - 3.2 - - * - :ref:`smbus_api` - - Experimental - - 3.4 - - * - :ref:`spi_api` - - Stable - - 1.0 - - * - :ref:`sensor_api` - - Stable - - 1.2 - - * - :ref:`settings_api` - - Stable - - 1.12 - - * - :ref:`shell_api` - - Stable - - 1.14 - - * - :ref:`stream_flash` - - Experimental - - 2.3 - - * - :ref:`sdhc_api` - - Experimental - - 3.1 - - * - :ref:`task_wdt_api` - - Unstable - - 2.5 - - * - :ref:`tcpc_api` - - Experimental - - 3.1 - - * - :ref:`tgpio_api` - - Experimental - - 3.5 - - * - :ref:`uart_api` - - Stable - - 1.0 - - * - :ref:`UART async ` - - Unstable - - 1.14 - - * - :ref:`usb_api` - - Stable - - 1.5 - - * - :ref:`usbc_api` - - Experimental - - 3.3 - - * - :ref:`usermode_api` - - Stable - - 1.11 - - * - :ref:`usbc_vbus_api` - - Experimental - - 3.3 - - * - :ref:`util_api` - - Experimental - - 2.4 - - * - :ref:`video_api` - - Stable - - 2.1 - - * - :ref:`w1_api` - - Experimental - - 3.2 - - * - :ref:`watchdog_api` - - Stable - - 1.0 - - * - :ref:`zdsp_api` - - Experimental - - 3.3 +.. api-overview-table:: From 611d284fc6466b96943be9489364e1f9f34df73f Mon Sep 17 00:00:00 2001 From: Marina Kalashina Date: Mon, 10 Jul 2023 13:11:06 +0300 Subject: [PATCH 0928/2402] doc: develop: tools: CLion tutorial MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds a tutorial on how to set up, build, and debug a sample Zephyr application in CLion. Signed-off-by: Marina Kalashina Signed-off-by: Benjamin Cabé --- doc/develop/tools/clion.rst | 207 ++++++++++++++++++ doc/develop/tools/img/clion_cmakeprofile.webp | Bin 0 -> 74510 bytes .../tools/img/clion_debug_threads.webp | Bin 0 -> 82226 bytes .../tools/img/clion_gdbserverconfig.webp | Bin 0 -> 39700 bytes .../tools/img/clion_segger_settings.webp | Bin 0 -> 26012 bytes .../tools/img/clion_toolchain_mingw.webp | Bin 0 -> 44568 bytes doc/develop/tools/index.rst | 1 + 7 files changed, 208 insertions(+) create mode 100644 doc/develop/tools/clion.rst create mode 100644 doc/develop/tools/img/clion_cmakeprofile.webp create mode 100644 doc/develop/tools/img/clion_debug_threads.webp create mode 100644 doc/develop/tools/img/clion_gdbserverconfig.webp create mode 100644 doc/develop/tools/img/clion_segger_settings.webp create mode 100644 doc/develop/tools/img/clion_toolchain_mingw.webp diff --git a/doc/develop/tools/clion.rst b/doc/develop/tools/clion.rst new file mode 100644 index 00000000000..d72e2ed28d6 --- /dev/null +++ b/doc/develop/tools/clion.rst @@ -0,0 +1,207 @@ +.. _clion_ide: + +CLion +##### + +CLion_ is a cross-platform C/C++ IDE that supports multi-threaded RTOS debugging. + +This guide describes the process of setting up, building, and debugging Zephyr's +:zephyr:code-sample:`multi-thread-blinky` sample in CLion. + +The instructions have been tested on Windows. In terms of the CLion workflow, the steps would be the +same for macOS and Linux, but make sure to select the correct environment file and to adjust the +paths. + +Get CLion +********* + +`Download CLion`_ and install it. + +Initialize a new workspace +************************** + +This guide gives details on how to build and debug the :zephyr:code-sample:`multi-thread-blinky` +sample application, but the instructions would be similar for any Zephyr project and :ref:`workspace +layout `. + +Before you start, make sure you have a working Zephyr development environment, as per the +instructions in the :ref:`getting_started`. + +Open the project in CLion +************************** + +#. In CLion, click :guilabel:`Open` on the Welcome screen or select :menuselection:`File --> Open` + from the main menu. + +#. Navigate to your Zephyr workspace (i.e.the :file:`zephyrproject` folder in your HOME directory if + you have followed the Getting Started instructions), then select + :file:`zephyr/samples/basic/threads` or another sample project folder. + + Click :guilabel:`OK`. + +#. If prompted, click :guilabel:`Trust Project`. + + See the `Project security`_ section in CLion web help for more information on project security. + +Configure the toolchain and CMake profile +***************************************** + +CLion will open the :guilabel:`Open Project Wizard` with the CMake profile settings. If that does +not happen, go to :menuselection:`Settings --> Build, Execution, Deployment --> CMake`. + +#. Click :guilabel:`Manage Toolchains` next to the :guilabel:`Toolchain` field. This will open the + :guilabel:`Toolchain` settings dialog. + +#. We recommend that you use the :guilabel:`Bundled MinGW` toolchain with default settings on + Windows, or the :guilabel:`System` (default) toolchain on Unix machines. + +#. Click :menuselection:`Add environment --> From file` and select + ``..\.venv\Scripts\activate.bat``. + + .. figure:: img/clion_toolchain_mingw.webp + :width: 600px + :align: center + :alt: MinGW toolchain with environment script + + Click :guilabel:`Apply` to save the changes. + +#. Back in the CMake profile settings dialog, specify your board in the :guilabel:`CMake options` + field. For example: + + .. code-block:: + + -DBOARD=nrf52840dk/nrf52840 + + .. figure:: img/clion_cmakeprofile.webp + :width: 600px + :align: center + :alt: CMake profile + +#. Click :guilabel:`Apply` to save the changes. + + CMake load should finish successfully. + +Configure Zephyr parameters for debug +************************************* + +#. In the configuration switcher on the top right, select :guilabel:`guiconfig` and click the hammer + icon. + +#. Use the GUI application to set the following flags: + + .. code-block:: + + DEBUG_THREAD_INFO + THREAD_RUNTIME_STATS + DEBUG_OPTIMIZATIONS + +Build the project +***************** + +In the configuration switcher, select **zephyr_final** and click the hammer icon. + +Note that other CMake targets like ``puncover`` or ``hardenconfig`` can also be called at this +point. + + +Enable RTOS integration +*********************** + +#. Go to :menuselection:`Settings --> Build, Execution, Deployment --> Embedded Development --> RTOS + Integration`. + +#. Set the :guilabel:`Enable RTOS Integration` checkbox. + + This option enables Zephyr tasks view during debugging. See `Multi-threaded RTOS debug`_ in CLion + web help for more information. + + You can leave the option set to :guilabel:`Auto`. CLion will detect Zephyr automatically. + +Create an Embedded GDB Server configuration +******************************************* + +In order to debug a Zephyr application in CLion, you need to create a run/debug configuration out of +the Embedded GDB Server template. + +Instructions below show the case of a Nordic Semiconductor board and a Segger J-Link debug probe. If +your setup is different, make sure to adjust the configuration settings accordingly. + +#. Select :menuselection:`Run --> New Embedded Configuration` from the main menu. + +#. Configure the settings: + + .. list-table:: + :header-rows: 1 + + * - Option + - Value + + * - :guilabel:`Name` (optional) + - Zephyr-threads + + * - :guilabel:`GDB Server Type` + - Segger JLink + + * - :guilabel:`Location` + - The path to ``JLinkGDBServerCL.exe`` on Windows or the ``JLinkGDBServer`` binary on + macOS/Linux. + + * - :guilabel:`Debugger` + - Bundled GDB + + .. note:: For non-ARM and non-x86 architectures, use a GDB executable + from Zephyr SDK. Make sure to pick a version with Python support + (for example, **riscv64-zephyr-elf-gdb-py**) and check that Python + is present in the system ``PATH``. + + * - :guilabel:`Target` + - zephyr-final + + * - :guilabel:`Executable binary` + - zephyr-final + + * - :guilabel:`Download binary` + - Always + + * - :guilabel:`TCP/IP port` + - Auto + + .. figure:: img/clion_gdbserverconfig.webp + :width: 500px + :align: center + :alt: Embedded GDB server configuration + +#. Click :guilabel:`Next` to set the Segger J-Link parameters. + + .. figure:: img/clion_segger_settings.webp + :width: 500px + :align: center + :alt: Segger J-Link parameters + +#. Click :guilabel:`Create` when ready. + +Start debugging +*************** + +#. Place breakpoints by clicking in the left gutter next to the code lines. + +#. Make sure that **Zephyr-threads** is selected in the configuration switcher and click the bug + icon or press :kbd:`Ctrl+D`. + +#. When a breakpoint is hit, CLion opens the Debug tool window. + + Zephyr tasks are listed in the :guilabel:`Threads & Variables` pane. You can switch between them + and inspect the variables for each task. + + .. figure:: img/clion_debug_threads.webp + :width: 800px + :align: center + :alt: Viewing Zephyr tasks during a debug session + + Refer to `CLion web help`_ for detailed description of the IDE debug capabilities. + +.. _CLion: https://www.jetbrains.com/clion/ +.. _Download CLion: https://www.jetbrains.com/clion/download +.. _Project security: https://www.jetbrains.com/help/clion/project-security.html#projects_security +.. _Multi-threaded RTOS debug: https://www.jetbrains.com/help/clion/rtos-debug.html +.. _CLion web help: https://www.jetbrains.com/help/clion/debugging-code.html diff --git a/doc/develop/tools/img/clion_cmakeprofile.webp b/doc/develop/tools/img/clion_cmakeprofile.webp new file mode 100644 index 0000000000000000000000000000000000000000..e723137b132af3809f2739cf4e125858ca119737 GIT binary patch literal 74510 zcmbSyb9|&(_IGSs9ox2Tqmzzp+fF*RZQJPBcG5v79kXL6_0G&r&(7}7;`dhlaX+7` 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znWYHc1aEA|Y4`vD09M-W4-XvUXLZdL<3i7ub^EvSXNmMmN>IlDhn&8gvC`^|33Oa4 ztrS!H4y%0`el7DGhJgXK6h#;{h$N&HZdItpPGu7C!DZUjE5ratp z6AwTxGI=SGyt6%0U)y7fSR}5?AQeXCjJoUA%>B&cIe={X2d^#WLC!XqIPxO+%WVF_ zKuF^F5TQ0y`(0H-5j7%TMdj(dq`3&k8Me3v%|f~wJT_ufQXK9NV#+{+Hylx(Oojgz z9pu*bT^TfRCxp);Z_snwl{3{JH9#0}V8U9Z0zj_Q$v+fgx$UE!7nO P000000000000000AR&qr literal 0 HcmV?d00001 diff --git a/doc/develop/tools/index.rst b/doc/develop/tools/index.rst index bb47db37f88..91fda588e93 100644 --- a/doc/develop/tools/index.rst +++ b/doc/develop/tools/index.rst @@ -6,4 +6,5 @@ Tools and IDEs .. toctree:: :maxdepth: 1 + clion.rst coccinelle.rst From b39f54253702d41155c399adaa9a93af2e1df0d3 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Tue, 19 Mar 2024 10:02:21 +0100 Subject: [PATCH 0929/2402] drivers: can: loopback: remove info log at driver initialization Remove the LOG_INF() at driver initialization. Signed-off-by: Henrik Brix Andersen --- drivers/can/can_loopback.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/can/can_loopback.c b/drivers/can/can_loopback.c index 8a419cb446a..433b623de6a 100644 --- a/drivers/can/can_loopback.c +++ b/drivers/can/can_loopback.c @@ -439,8 +439,6 @@ static int can_loopback_init(const struct device *dev) return -1; } - LOG_INF("Init of %s done", dev->name); - return 0; } From f4972347d453658c115dc773e9425448f49616d7 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 19 Mar 2024 09:48:44 +0100 Subject: [PATCH 0930/2402] tests/bsim/bt l2cap/stress: Increase runtime timeout This test has been seen failing in the new runners due to a (realtime) timeout. Let's double the timeout so it does not. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh index d3bed84907b..f365f96a7e8 100755 --- a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh +++ b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh @@ -7,7 +7,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # EATT test simulation_id="l2cap_stress" verbosity_level=2 -EXECUTE_TIMEOUT=120 +EXECUTE_TIMEOUT=240 cd ${BSIM_OUT_PATH}/bin From 0ff402657b3012d6cfdd06096cd83fa3457dcb37 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Fri, 15 Mar 2024 13:31:11 +0200 Subject: [PATCH 0931/2402] nxp: sai: add support for passing TX/RX data line through DTS Some SAI instances are mutliline, meaning they can have multiple TX/RX data lines (channels). Depending on the board, the index of the TX/RX data lines that are connected to the consumer (e.g: the codec) may not always be 0. This commit fixes this issue by adding support for passing the index of the used TX/RX data lines through the DTS. Signed-off-by: Laurentiu Mihalcea --- drivers/dai/nxp/sai/sai.c | 20 +++++++++++++++++--- drivers/dai/nxp/sai/sai.h | 26 ++++++++++++++++++++++---- dts/bindings/dai/nxp,dai-sai.yaml | 25 +++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 7 deletions(-) diff --git a/drivers/dai/nxp/sai/sai.c b/drivers/dai/nxp/sai/sai.c index fd279fef2fd..9af53287eb5 100644 --- a/drivers/dai/nxp/sai/sai.c +++ b/drivers/dai/nxp/sai/sai.c @@ -744,7 +744,8 @@ static int sai_trigger_start(const struct device *dev, * * TODO: for now we only support 1 data line per direction. */ - sai_tx_rx_set_dline_mask(dir, data->regmap, 0x1); + sai_tx_rx_set_dline_mask(dir, data->regmap, + SAI_TX_RX_DLINE_MASK(dir, cfg)); /* this will also enable the async side */ SAI_TX_RX_ENABLE_DISABLE(dir, data->regmap, true); @@ -862,14 +863,25 @@ BUILD_ASSERT(SAI_TX_SYNC_MODE(inst) != SAI_RX_SYNC_MODE(inst) || \ SAI_TX_SYNC_MODE(inst) != kSAI_ModeSync, \ "transmitter and receiver can't be both SYNC with each other"); \ \ +BUILD_ASSERT(SAI_DLINE_COUNT(inst) != -1, \ + "bad or unsupported SAI instance. Is the base address correct?"); \ + \ +BUILD_ASSERT(SAI_TX_DLINE_INDEX(inst) >= 0 && \ + (SAI_TX_DLINE_INDEX(inst) < SAI_DLINE_COUNT(inst)), \ + "invalid TX data line index"); \ + \ +BUILD_ASSERT(SAI_RX_DLINE_INDEX(inst) >= 0 && \ + (SAI_RX_DLINE_INDEX(inst) < SAI_DLINE_COUNT(inst)), \ + "invalid RX data line index"); \ + \ static const struct dai_properties sai_tx_props_##inst = { \ - .fifo_address = SAI_TX_FIFO_BASE(inst), \ + .fifo_address = SAI_TX_FIFO_BASE(inst, SAI_TX_DLINE_INDEX(inst)), \ .fifo_depth = SAI_FIFO_DEPTH(inst) * CONFIG_SAI_FIFO_WORD_SIZE, \ .dma_hs_id = SAI_TX_RX_DMA_HANDSHAKE(inst, tx), \ }; \ \ static const struct dai_properties sai_rx_props_##inst = { \ - .fifo_address = SAI_RX_FIFO_BASE(inst), \ + .fifo_address = SAI_RX_FIFO_BASE(inst, SAI_RX_DLINE_INDEX(inst)), \ .fifo_depth = SAI_FIFO_DEPTH(inst) * CONFIG_SAI_FIFO_WORD_SIZE, \ .dma_hs_id = SAI_TX_RX_DMA_HANDSHAKE(inst, rx), \ }; \ @@ -896,6 +908,8 @@ static struct sai_config sai_config_##inst = { \ .irq_config = irq_config_##inst, \ .tx_sync_mode = SAI_TX_SYNC_MODE(inst), \ .rx_sync_mode = SAI_RX_SYNC_MODE(inst), \ + .tx_dline = SAI_TX_DLINE_INDEX(inst), \ + .rx_dline = SAI_RX_DLINE_INDEX(inst), \ }; \ \ static struct sai_data sai_data_##inst = { \ diff --git a/drivers/dai/nxp/sai/sai.h b/drivers/dai/nxp/sai/sai.h index b5e07b45395..10296717e83 100644 --- a/drivers/dai/nxp/sai/sai.h +++ b/drivers/dai/nxp/sai/sai.h @@ -102,12 +102,12 @@ LOG_MODULE_REGISTER(nxp_dai_sai); FSL_FEATURE_SAI_FIFO_COUNTn(UINT_TO_I2S(DT_INST_REG_ADDR(inst))) / 2) /* used to retrieve TDR0's address based on SAI's physical address */ -#define SAI_TX_FIFO_BASE(inst)\ - POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->TDR[0])) +#define SAI_TX_FIFO_BASE(inst, idx)\ + POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->TDR[idx])) /* used to retrieve RDR0's address based on SAI's physical address */ -#define SAI_RX_FIFO_BASE(inst)\ - POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->RDR[0])) +#define SAI_RX_FIFO_BASE(inst, idx)\ + POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->RDR[idx])) /* internal macro used to retrieve the default TX/RX FIFO's size (in FIFO words) */ #define _SAI_FIFO_DEPTH(inst)\ @@ -146,6 +146,16 @@ LOG_MODULE_REGISTER(nxp_dai_sai); ((DT_INST_DMAS_CELL_BY_NAME(inst, dir, channel) & GENMASK(7, 0)) |\ ((DT_INST_DMAS_CELL_BY_NAME(inst, dir, mux) << 8) & GENMASK(15, 8))) +/* used to retrieve the number of supported transmission/receive lines */ +#define SAI_DLINE_COUNT(inst)\ + FSL_FEATURE_SAI_CHANNEL_COUNTn(UINT_TO_I2S(DT_INST_REG_ADDR(inst))) + +/* used to retrieve the index of the transmission line */ +#define SAI_TX_DLINE_INDEX(inst) DT_INST_PROP_OR(inst, tx_dataline, 0) + +/* used to retrieve the index of the receive line */ +#define SAI_RX_DLINE_INDEX(inst) DT_INST_PROP_OR(inst, rx_dataline, 0) + /* utility macros */ /* invert a clock's polarity. This works because a clock's polarity is expressed @@ -215,6 +225,12 @@ LOG_MODULE_REGISTER(nxp_dai_sai); #define SAI_TX_RX_DIR_IS_SW_ENABLED(dir, data)\ ((dir) == DAI_DIR_TX ? data->tx_enabled : data->rx_enabled) +/* used to compute the mask for the transmission/receive lines based on + * the index passed from the DTS. + */ +#define SAI_TX_RX_DLINE_MASK(dir, cfg)\ + ((dir) == DAI_DIR_TX ? BIT((cfg)->tx_dline) : BIT((cfg)->rx_dline)) + struct sai_clock_data { uint32_t *clocks; uint32_t clock_num; @@ -253,6 +269,8 @@ struct sai_config { /* TX synchronization mode - may be SYNC or ASYNC */ sai_sync_mode_t tx_sync_mode; void (*irq_config)(void); + uint32_t tx_dline; + uint32_t rx_dline; }; /* this needs to perfectly match SOF's struct sof_ipc_dai_sai_params */ diff --git a/dts/bindings/dai/nxp,dai-sai.yaml b/dts/bindings/dai/nxp,dai-sai.yaml index ae9cd201880..ec2bc88c392 100644 --- a/dts/bindings/dai/nxp,dai-sai.yaml +++ b/dts/bindings/dai/nxp,dai-sai.yaml @@ -84,3 +84,28 @@ properties: If this property is not specified, the receiver will be set to ASYNC. If one side is SYNC then the other MUST be ASYNC. Failing to meet this condition will result in a failed BUILD_ASSERT(). + tx-dataline: + type: int + description: | + Use this property to specify which transmission data line the SAI should + use. To find out which transmission line you should use you can: + 1) Check the TRM and see if your SAI instance is multiline. If not then + you're going to use transmission line 0. + 2) If your SAI is multiline then you need to check the datasheet and see + the index of the transmission line that's connected to your consumer + (e.g: the codec). + The indexing of the data line starts at 0. If this property is not specified + then the index of the transmission data line will be 0. + Please note that "channel" and "data line" are synnonyms in this context. + rx-dataline: + type: int + description: | + Use this property to specify which receive transmission data line the SAI should + use. To find out which receive line you should use you can: + 1) Check the TRM and see if your SAI instance is multiline. If not then + you're going to use receive line 0. + 2) If your SAI is multiline then you need to check the datasheet and see + the index of the receive line that's connected to your consumer (e.g: the codec). + The indexing of the data line starts at 0. If this property is not specified + then the index of the receive data line will be 0. + Please note that "channel" and "data line" are synnonyms in this context. From d952d6a364037aad85d5e70fe4be1cf294be9aab Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Fri, 15 Mar 2024 11:16:21 +0000 Subject: [PATCH 0932/2402] input: rename the internal callback struct to input_callback Rename the internal input callback structure to input_callback. This is for coherency with "INPUT_CALLBACK_DEFINE" and other similar code paths in Zephyr, and also to avoid confusion with terminology. This is an internal structure, applications should not have any references to it so there should be no need for any release note entries. Signed-off-by: Fabio Baltieri --- cmake/linker_script/common/common-rom.cmake | 2 +- include/zephyr/input/input.h | 10 +++++----- include/zephyr/linker/common-rom/common-rom-misc.ld | 2 +- subsys/input/input.c | 6 +++--- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/cmake/linker_script/common/common-rom.cmake b/cmake/linker_script/common/common-rom.cmake index e2173c54f34..77cd911ab4f 100644 --- a/cmake/linker_script/common/common-rom.cmake +++ b/cmake/linker_script/common/common-rom.cmake @@ -207,7 +207,7 @@ if (CONFIG_HTTP_SERVER) endif() if(CONFIG_INPUT) - zephyr_iterable_section(NAME input_listener KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN 4) + zephyr_iterable_section(NAME input_callback KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN 4) endif() if(CONFIG_USBD_MSC_CLASS) diff --git a/include/zephyr/input/input.h b/include/zephyr/input/input.h index eb1b798d15c..32e9bf9fa8e 100644 --- a/include/zephyr/input/input.h +++ b/include/zephyr/input/input.h @@ -52,7 +52,7 @@ struct input_event { /** * @brief Report a new input event. * - * This causes all the listeners for the specified device to be triggered, + * This causes all the callbacks for the specified device to be executed, * either synchronously or through the input thread if utilized. * * @param dev Device generating the event or NULL. @@ -118,9 +118,9 @@ static inline int input_report_abs(const struct device *dev, bool input_queue_empty(void); /** - * @brief Input listener callback structure. + * @brief Input callback structure. */ -struct input_listener { +struct input_callback { /** @ref device pointer or NULL. */ const struct device *dev; /** The callback function. */ @@ -138,8 +138,8 @@ struct input_listener { * @param _callback The callback function. */ #define INPUT_CALLBACK_DEFINE(_dev, _callback) \ - static const STRUCT_SECTION_ITERABLE(input_listener, \ - _input_listener__##_callback) = { \ + static const STRUCT_SECTION_ITERABLE(input_callback, \ + _input_callback__##_callback) = { \ .dev = _dev, \ .callback = _callback, \ } diff --git a/include/zephyr/linker/common-rom/common-rom-misc.ld b/include/zephyr/linker/common-rom/common-rom-misc.ld index 189a9e31885..6c03bfb79a4 100644 --- a/include/zephyr/linker/common-rom/common-rom-misc.ld +++ b/include/zephyr/linker/common-rom/common-rom-misc.ld @@ -27,7 +27,7 @@ #endif #if defined(CONFIG_INPUT) - ITERABLE_SECTION_ROM(input_listener, 4) + ITERABLE_SECTION_ROM(input_callback, 4) #endif #if defined(CONFIG_EMUL) diff --git a/subsys/input/input.c b/subsys/input/input.c index 5e9f45d8de7..907788e1853 100644 --- a/subsys/input/input.c +++ b/subsys/input/input.c @@ -20,9 +20,9 @@ K_MSGQ_DEFINE(input_msgq, sizeof(struct input_event), static void input_process(struct input_event *evt) { - STRUCT_SECTION_FOREACH(input_listener, listener) { - if (listener->dev == NULL || listener->dev == evt->dev) { - listener->callback(evt); + STRUCT_SECTION_FOREACH(input_callback, callback) { + if (callback->dev == NULL || callback->dev == evt->dev) { + callback->callback(evt); } } } From 315ee38b95a2356eb3cd266ce4bc789f48d7c59c Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 27 Feb 2024 14:13:10 +0100 Subject: [PATCH 0933/2402] ADSP: don't use timer interrupts on secondary cores When running SOF on Intel ADSP we choose to only serve the timer interrupt on the primary core. Signed-off-by: Guennadi Liakhovetski --- drivers/timer/intel_adsp_timer.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/timer/intel_adsp_timer.c b/drivers/timer/intel_adsp_timer.c index 330e5bbd425..d1f37b123c2 100644 --- a/drivers/timer/intel_adsp_timer.c +++ b/drivers/timer/intel_adsp_timer.c @@ -210,7 +210,6 @@ static void irq_init(void) void smp_timer_init(void) { - irq_init(); } /* Runs on core 0 only */ From ff2dd7f25a997d93a58d4e8bb24b9acc7401e103 Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Tue, 16 Jan 2024 21:45:30 +0100 Subject: [PATCH 0934/2402] dts: xtensa: intel: Reorder ACE 1.5 power domain nodes This patch reorders the power domain node definitions in the ACE 1.5 Meteorlake DTS file to improve readability and facilitate comparison with the documentation. Changes include: - Reordering power domain nodes by their bit positions. - No changes to the bit positions themselves; they remain as originally defined. This reordering does not affect the functionality but makes the DTS file more maintainable and easier to cross-reference with the hardware specification. Signed-off-by: Tomasz Leman --- dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi | 28 ++++++++++----------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi index de8aa8ed6fd..c4f497cdc4c 100644 --- a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi @@ -385,37 +385,37 @@ compatible = "intel,adsp-power-domain"; bit-position = <15>; }; - hub_hp_domain: hub_hp_domain { + ml1_domain: ml1_domain { compatible = "intel,adsp-power-domain"; - bit-position = <6>; + bit-position = <13>; }; - io0_domain: io0_domain { + ml0_domain: ml0_domain { compatible = "intel,adsp-power-domain"; - bit-position = <8>; + bit-position = <12>; }; - io1_domain: io1_domain { + io3_domain: io3_domain { compatible = "intel,adsp-power-domain"; - bit-position = <9>; + bit-position = <11>; }; io2_domain: io2_domain { compatible = "intel,adsp-power-domain"; bit-position = <10>; }; - io3_domain: io3_domain { + io1_domain: io1_domain { compatible = "intel,adsp-power-domain"; - bit-position = <11>; + bit-position = <9>; }; - hst_domain: hst_domain { + io0_domain: io0_domain { compatible = "intel,adsp-power-domain"; - bit-position = <4>; + bit-position = <8>; }; - ml0_domain: ml0_domain { + hub_hp_domain: hub_hp_domain { compatible = "intel,adsp-power-domain"; - bit-position = <12>; + bit-position = <6>; }; - ml1_domain: ml1_domain { + hst_domain: hst_domain { compatible = "intel,adsp-power-domain"; - bit-position = <13>; + bit-position = <4>; }; }; From 64a81ffb23ba76f2e1d961187e7ae3941d144cac Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Fri, 16 Feb 2024 16:44:49 +0100 Subject: [PATCH 0935/2402] dts: xtensa: intel_adsp: ace15: Update power domain for hda link nodes Changing the power domain from 'hst_domain' to 'io0_domain' for the HDA DMA link in/out nodes. This aligns the power domain assignments with the actual hardware configuration and ensures that the power management subsystem can accurately manage the power states of these interfaces. Signed-off-by: Tomasz Leman --- dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi index c4f497cdc4c..a6fac22ba06 100644 --- a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi @@ -461,7 +461,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <32>; - power-domain = <&hst_domain>; + power-domain = <&io0_domain>; status = "okay"; }; @@ -473,7 +473,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <32>; - power-domain = <&hst_domain>; + power-domain = <&io0_domain>; status = "okay"; }; From a39a61015c597fa1cd17a37041dfaeb958095844 Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Tue, 16 Jan 2024 19:23:03 +0100 Subject: [PATCH 0936/2402] dts: xtensa: intel: Reorder LNL power domains This patch reorders the power domain definitions for the Intel ADSP ACE 2.0 LNL (Lunarlake) platform in the Device Tree Source (DTS). Changes include: - Removing the definitions for io2_domain, io3_domain, and ml1_domain, which are no longer present in the ACE 2.0 LNL configuration. - Renaming and reassigning bit positions to existing power domains to reflect the updated power management architecture. The reordering ensures that the DTS reflects the current power domain architecture of the ACE 2.0 LNL platform, facilitating accurate power management within the SoC. Signed-off-by: Tomasz Leman --- dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi | 26 ++++++---------------- 1 file changed, 7 insertions(+), 19 deletions(-) diff --git a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi index 726e94bc271..fa2a722953a 100644 --- a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi @@ -426,37 +426,25 @@ compatible = "intel,adsp-power-domain"; bit-position = <15>; }; - hub_hp_domain: hub_hpp_domain { - compatible = "intel,adsp-power-domain"; - bit-position = <6>; - }; - io0_domain: io0_domain { + ml0_domain: ml0_domain { compatible = "intel,adsp-power-domain"; - bit-position = <8>; + bit-position = <12>; }; io1_domain: io1_domain { compatible = "intel,adsp-power-domain"; bit-position = <9>; }; - io2_domain: io2_domain { + io0_domain: io0_domain { compatible = "intel,adsp-power-domain"; - bit-position = <10>; + bit-position = <8>; }; - io3_domain: io3_domain { + hub_hp_domain: hub_hp_domain { compatible = "intel,adsp-power-domain"; - bit-position = <11>; + bit-position = <6>; }; hst_domain: hst_domain { compatible = "intel,adsp-power-domain"; - bit-position = <4>; - }; - ml0_domain: ml0_domain { - compatible = "intel,adsp-power-domain"; - bit-position = <12>; - }; - ml1_domain: ml1_domain { - compatible = "intel,adsp-power-domain"; - bit-position = <13>; + bit-position = <5>; }; }; From 4ea52bdd1297e6e84fc56df8b685b71f76a6991c Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Tue, 16 Jan 2024 22:20:27 +0100 Subject: [PATCH 0937/2402] soc: xtensa: intel: Update power status bitfields for LNL This patch updates the power status register bitfield definitions in the power management header for the Intel ADSP ACE 2.0 LNL platform. Modifications include: - Adjusting the 'ioxpgs' field from 4 bits to 2 bits. - Adding a 'rsvd11' field with 2 bits to reflect reserved space. - Changing the 'mlpgs' field from 2 bits to 1 bit. - Updating the 'rsvd14' field from 1 bit to 2 bits for alignment. These changes ensure that the power status register bitfields match the latest hardware specification for the ACE 2.0 LNL SoC, which is crucial for accurate power domain status monitoring. Signed-off-by: Tomasz Leman --- soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_power.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_power.h b/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_power.h index 5d12c79fdcb..d25ffba2ae3 100644 --- a/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_power.h +++ b/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_power.h @@ -38,9 +38,10 @@ struct ace_pwrsts { uint16_t hstpgs : 1; uint16_t hubhppgs : 1; uint16_t dspulppgs : 1; - uint16_t ioxpgs : 4; - uint16_t mlpgs : 2; - uint16_t rsvd14 : 1; + uint16_t ioxpgs : 2; + uint16_t rsvd11 : 2; + uint16_t mlpgs : 1; + uint16_t rsvd14 : 2; uint16_t hubulppgs : 1; }; From 81658e67e7c02f8d8d7688ca18b17681f2c13caa Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Fri, 16 Feb 2024 16:57:37 +0100 Subject: [PATCH 0938/2402] dts: xtensa: intel_adsp: Remove ALH nodes from ACE 2.0 LNL DTS Remove the Audio Link Hub (ALH) nodes from the ACE 2.0 LNL DTS file. This patch cleans up the Device Tree Source by removing the individual ALH stream/FIFO nodes. The ALH hardware is not present in the ACE 2.0 architecture, and these nodes are therefore not applicable. Signed-off-by: Tomasz Leman --- dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi | 106 --------------------- 1 file changed, 106 deletions(-) diff --git a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi index fa2a722953a..f654133f0ef 100644 --- a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi @@ -176,112 +176,6 @@ status = "okay"; }; - /* - * FIXME this is modeling individual alh channels/instances - * with node labels, which has problems. A better representation - * is discussed here: - * - * https://github.com/zephyrproject-rtos/zephyr/pull/50287#discussion_r974591009 - * - * The hardware actually supports 16 ALH streams/FIFOs. Below description does - * not fully represent hardware capabilities and is expected to be modified. - */ - alh0: alh0@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh1: alh1@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh2: alh2@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh3: alh3@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh4: alh4@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh5: alh5@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh6: alh6@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh7: alh7@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh8: alh8@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh9: alh9@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh10: alh10@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh11: alh11@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh12: alh12@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh13: alh13@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh14: alh14@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - - alh15: alh15@24400 { - compatible = "intel,alh-dai"; - reg = <0x00024400 0x00024600>; - status = "okay"; - }; - ssp0: ssp@28100 { compatible = "intel,ssp-dai"; #address-cells = <1>; From 8858a024c0151e3b4cd35262bed935248211d6b1 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Mon, 5 Feb 2024 15:55:56 +0100 Subject: [PATCH 0939/2402] ipc: Add thread name to mbox work queues Add thread name to mbox work queues when thread names are enabled. Signed-off-by: Joakim Andersson --- .../ipc_service/backends/ipc_rpmsg_static_vrings.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c b/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c index 6c8f1a72eaf..24653585202 100644 --- a/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c +++ b/subsys/ipc/ipc_service/backends/ipc_rpmsg_static_vrings.c @@ -30,6 +30,12 @@ #define STATE_BUSY (1) #define STATE_INITED (2) +#if defined(CONFIG_THREAD_MAX_NAME_LEN) +#define THREAD_MAX_NAME_LEN CONFIG_THREAD_MAX_NAME_LEN +#else +#define THREAD_MAX_NAME_LEN 1 +#endif + K_THREAD_STACK_ARRAY_DEFINE(mbox_stack, NUM_INSTANCES, WQ_STACK_SIZE); struct backend_data_t { @@ -327,6 +333,13 @@ static int mbox_init(const struct device *instance) k_work_queue_init(&data->mbox_wq); k_work_queue_start(&data->mbox_wq, mbox_stack[conf->id], WQ_STACK_SIZE, prio, NULL); + if (IS_ENABLED(CONFIG_THREAD_NAME)) { + char name[THREAD_MAX_NAME_LEN]; + + snprintk(name, sizeof(name), "mbox_wq #%d", conf->id); + k_thread_name_set(&data->mbox_wq.thread, name); + } + k_work_init(&data->mbox_work, mbox_callback_process); err = mbox_register_callback_dt(&conf->mbox_rx, mbox_callback, data); From 638a47f804deb7b76f996ce2c85c49b5b5e4a8dd Mon Sep 17 00:00:00 2001 From: TaiJu Wu Date: Thu, 14 Mar 2024 04:02:16 +0000 Subject: [PATCH 0940/2402] MAINTAINERS: Add myself to kernel collaborator Add myself to kernel as a collaborator Signed-off-by: TaiJu Wu --- MAINTAINERS.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 5f9dfda220b..fddbfb902d5 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2176,6 +2176,7 @@ Kernel: - dcpleung - cfriedt - npitre + - TaiJuWu files: - doc/kernel/ - include/zephyr/kernel*.h From ecf29a2f46f83207d1f0f20dff0ff7cb90e7e1e7 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 19 Mar 2024 09:56:28 +0100 Subject: [PATCH 0941/2402] tests/bsim/bt l2cap/stress: Be more silent This test was way too verbose (produced a log over 65000 lines long). Let's mute it a bit. If the test fails, developers can raise the log level as needed. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/bluetooth/host/l2cap/stress/prj.conf | 2 +- tests/bsim/bluetooth/host/l2cap/stress/src/main.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/bsim/bluetooth/host/l2cap/stress/prj.conf b/tests/bsim/bluetooth/host/l2cap/stress/prj.conf index a28127716fc..fecd8ba08d1 100644 --- a/tests/bsim/bluetooth/host/l2cap/stress/prj.conf +++ b/tests/bsim/bluetooth/host/l2cap/stress/prj.conf @@ -47,7 +47,7 @@ CONFIG_LOG=y CONFIG_ASSERT=y CONFIG_NET_BUF_POOL_USAGE=y -CONFIG_BT_L2CAP_LOG_LEVEL_DBG=y +# CONFIG_BT_L2CAP_LOG_LEVEL_DBG=y # CONFIG_BT_CONN_LOG_LEVEL_DBG=y CONFIG_LOG_THREAD_ID_PREFIX=y CONFIG_THREAD_NAME=y diff --git a/tests/bsim/bluetooth/host/l2cap/stress/src/main.c b/tests/bsim/bluetooth/host/l2cap/stress/src/main.c index 1eed057519b..b20dafea3fa 100644 --- a/tests/bsim/bluetooth/host/l2cap/stress/src/main.c +++ b/tests/bsim/bluetooth/host/l2cap/stress/src/main.c @@ -11,7 +11,7 @@ #define LOG_MODULE_NAME main #include -LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL_DBG); +LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL_INF); CREATE_FLAG(is_connected); CREATE_FLAG(flag_l2cap_connected); From 893f50547756265248c8b3b7da0c12f96423ea47 Mon Sep 17 00:00:00 2001 From: Aleksander Wasaznik Date: Wed, 6 Mar 2024 11:19:33 +0100 Subject: [PATCH 0942/2402] sys: `atomic_builtin.h`: Add missing include `atomic_builtin.h` uses `NULL`, which is defined in `stddef.h`. Signed-off-by: Aleksander Wasaznik --- include/zephyr/sys/atomic_builtin.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/zephyr/sys/atomic_builtin.h b/include/zephyr/sys/atomic_builtin.h index 5b81a76f050..b45f561a7f3 100644 --- a/include/zephyr/sys/atomic_builtin.h +++ b/include/zephyr/sys/atomic_builtin.h @@ -11,6 +11,7 @@ #define ZEPHYR_INCLUDE_SYS_ATOMIC_BUILTIN_H_ #include +#include #include #ifdef __cplusplus From aeea1d10de8859d9368cbf07be0b9c3726c79a67 Mon Sep 17 00:00:00 2001 From: Glenn Andrews Date: Wed, 13 Mar 2024 17:12:35 -0700 Subject: [PATCH 0943/2402] Lib: SMF: Fix typo in documentation Fixes a typo found by @bryceschober Spell-checked the rest of the document and found no issues. Signed-off-by: Glenn Andrews --- doc/services/smf/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/services/smf/index.rst b/doc/services/smf/index.rst index 38e68cfcf51..ad15393120f 100644 --- a/doc/services/smf/index.rst +++ b/doc/services/smf/index.rst @@ -513,7 +513,7 @@ a state machine for testing initial transitions and :c:func:`smf_set_handled`. The statechart for this test is below. .. graphviz:: - :caption: Test state machine for initial trnasitions and ``smf_set_handled`` + :caption: Test state machine for initial transitions and ``smf_set_handled`` digraph smf_hierarchical_initial { compound=true; From c45026fc084ff28d70608ef8625991d4acec3ebc Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Wed, 13 Mar 2024 17:12:43 +0100 Subject: [PATCH 0944/2402] testsuite: ztest: Fix argument name As per current definition of the Z_TEST macro, defined in include/zephyr/ztest_test_new.h, the passed parameter is named 'fixture', not 'this'. Signed-off-by: Reto Schneider --- subsys/testsuite/ztest/include/zephyr/ztest_test.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/subsys/testsuite/ztest/include/zephyr/ztest_test.h b/subsys/testsuite/ztest/include/zephyr/ztest_test.h index 1370bd1a2aa..b6bec89a0b8 100644 --- a/subsys/testsuite/ztest/include/zephyr/ztest_test.h +++ b/subsys/testsuite/ztest/include/zephyr/ztest_test.h @@ -461,7 +461,7 @@ void ztest_skip_failed_assumption(void); * @brief Define a test function * * This macro behaves exactly the same as ZTEST(), but the function takes an argument for the - * fixture of type `struct suite##_fixture*` named `this`. + * fixture of type `struct suite##_fixture*` named `fixture`. * * @param suite The name of the test suite to attach this test * @param fn The test function to call. @@ -472,7 +472,7 @@ void ztest_skip_failed_assumption(void); * @brief Define a test function that should run as a user thread * * If CONFIG_USERSPACE is not enabled, this is functionally identical to ZTEST_F(). The test - * function takes a single fixture argument of type `struct suite##_fixture*` named `this`. + * function takes a single fixture argument of type `struct suite##_fixture*` named `fixture`. * * @param suite The name of the test suite to attach this test * @param fn The test function to call. From 107b335cce0eac5577b74df47bbeacb46f2dd165 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Tue, 19 Mar 2024 17:36:06 +0100 Subject: [PATCH 0945/2402] ci: doc-build: increase timeout for doc build jobs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With the introduction of the new runners, the time it takes to build the documentation in CI has slowed down to the point that the job often times out. Applied a conservative 2x factor to the timeouts that were in place. Signed-off-by: Benjamin Cabé --- .github/workflows/doc-build.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index 43c7fab056b..d1bcfe3e06f 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -59,7 +59,7 @@ jobs: ( needs.doc-file-check.outputs.file_check == 'true' || github.event_name != 'pull_request' ) runs-on: group: zephyr-runner-v2-linux-x64-4xlarge - timeout-minutes: 45 + timeout-minutes: 90 concurrency: group: doc-build-html-${{ github.ref }} cancel-in-progress: true @@ -186,7 +186,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: texlive/texlive:latest - timeout-minutes: 60 + timeout-minutes: 120 concurrency: group: doc-build-pdf-${{ github.ref }} cancel-in-progress: true From 210c7c2f21b4f32385920e960748250f74487238 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 15 Mar 2024 16:51:52 +0100 Subject: [PATCH 0946/2402] boards native_sim[64]: Claim support for dma The native_sim boards support the DMA emulator just like native_posix. The tag was just never added in the native_sim twister yaml. Let's add it. Signed-off-by: Alberto Escolar Piedras --- boards/native/native_sim/native_sim.yaml | 1 + boards/native/native_sim/native_sim_native_64.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/boards/native/native_sim/native_sim.yaml b/boards/native/native_sim/native_sim.yaml index 999b52aa16b..bed88ab7f3a 100644 --- a/boards/native/native_sim/native_sim.yaml +++ b/boards/native/native_sim/native_sim.yaml @@ -11,6 +11,7 @@ toolchain: supported: - can - counter + - dma - eeprom - netif:eth - usb_device diff --git a/boards/native/native_sim/native_sim_native_64.yaml b/boards/native/native_sim/native_sim_native_64.yaml index 66decdebf4d..535cf513658 100644 --- a/boards/native/native_sim/native_sim_native_64.yaml +++ b/boards/native/native_sim/native_sim_native_64.yaml @@ -11,6 +11,7 @@ toolchain: supported: - can - counter + - dma - eeprom - netif:eth - usb_device From 6161207e301f8a712bbc3f6601256ce1cbc9b7f6 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 15 Mar 2024 16:53:30 +0100 Subject: [PATCH 0947/2402] tests/drivers/dma: Run on native_sim instead of native_posix native_posix is being replaced with native_sim, let's have this tests be run on native_sim instead. Signed-off-by: Alberto Escolar Piedras --- .../boards/{native_posix.conf => native_sim.conf} | 0 .../boards/{native_posix.overlay => native_sim.overlay} | 0 ...ive_posix_native_64.conf => native_sim_native_64.conf} | 0 tests/drivers/dma/chan_blen_transfer/testcase.yaml | 4 ++-- .../boards/{native_posix.conf => native_sim.conf} | 0 .../boards/{native_posix.overlay => native_sim.overlay} | 0 ...ive_posix_native_64.conf => native_sim_native_64.conf} | 0 tests/drivers/dma/chan_link_transfer/testcase.yaml | 8 ++++---- .../boards/{native_posix.conf => native_sim.conf} | 0 .../boards/{native_posix.overlay => native_sim.overlay} | 0 ...ive_posix_native_64.conf => native_sim_native_64.conf} | 0 tests/drivers/dma/loop_transfer/testcase.yaml | 4 ++-- .../boards/{native_posix.conf => native_sim.conf} | 0 .../boards/{native_posix.overlay => native_sim.overlay} | 0 ...ive_posix_native_64.conf => native_sim_native_64.conf} | 0 tests/drivers/dma/scatter_gather/testcase.yaml | 8 ++++---- 16 files changed, 12 insertions(+), 12 deletions(-) rename tests/drivers/dma/chan_blen_transfer/boards/{native_posix.conf => native_sim.conf} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{native_posix.overlay => native_sim.overlay} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{native_posix_native_64.conf => native_sim_native_64.conf} (100%) rename tests/drivers/dma/chan_link_transfer/boards/{native_posix.conf => native_sim.conf} (100%) rename tests/drivers/dma/chan_link_transfer/boards/{native_posix.overlay => native_sim.overlay} (100%) rename tests/drivers/dma/chan_link_transfer/boards/{native_posix_native_64.conf => native_sim_native_64.conf} (100%) rename tests/drivers/dma/loop_transfer/boards/{native_posix.conf => native_sim.conf} (100%) rename tests/drivers/dma/loop_transfer/boards/{native_posix.overlay => native_sim.overlay} (100%) rename tests/drivers/dma/loop_transfer/boards/{native_posix_native_64.conf => native_sim_native_64.conf} (100%) rename tests/drivers/dma/scatter_gather/boards/{native_posix.conf => native_sim.conf} (100%) rename tests/drivers/dma/scatter_gather/boards/{native_posix.overlay => native_sim.overlay} (100%) rename tests/drivers/dma/scatter_gather/boards/{native_posix_native_64.conf => native_sim_native_64.conf} (100%) diff --git a/tests/drivers/dma/chan_blen_transfer/boards/native_posix.conf b/tests/drivers/dma/chan_blen_transfer/boards/native_sim.conf similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/native_posix.conf rename to tests/drivers/dma/chan_blen_transfer/boards/native_sim.conf diff --git a/tests/drivers/dma/chan_blen_transfer/boards/native_posix.overlay b/tests/drivers/dma/chan_blen_transfer/boards/native_sim.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/native_posix.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/native_sim.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/native_posix_native_64.conf b/tests/drivers/dma/chan_blen_transfer/boards/native_sim_native_64.conf similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/native_posix_native_64.conf rename to tests/drivers/dma/chan_blen_transfer/boards/native_sim_native_64.conf diff --git a/tests/drivers/dma/chan_blen_transfer/testcase.yaml b/tests/drivers/dma/chan_blen_transfer/testcase.yaml index bbb6b2ca7eb..fb8a8966397 100644 --- a/tests/drivers/dma/chan_blen_transfer/testcase.yaml +++ b/tests/drivers/dma/chan_blen_transfer/testcase.yaml @@ -6,8 +6,8 @@ tests: tags: - dma integration_platforms: - - native_posix - - native_posix/native/64 + - native_sim + - native_sim/native/64 filter: dt_nodelabel_enabled("tst_dma0") drivers.dma.chan_blen_transfer.low_footprint: tags: diff --git a/tests/drivers/dma/chan_link_transfer/boards/native_posix.conf b/tests/drivers/dma/chan_link_transfer/boards/native_sim.conf similarity index 100% rename from tests/drivers/dma/chan_link_transfer/boards/native_posix.conf rename to tests/drivers/dma/chan_link_transfer/boards/native_sim.conf diff --git a/tests/drivers/dma/chan_link_transfer/boards/native_posix.overlay b/tests/drivers/dma/chan_link_transfer/boards/native_sim.overlay similarity index 100% rename from tests/drivers/dma/chan_link_transfer/boards/native_posix.overlay rename to tests/drivers/dma/chan_link_transfer/boards/native_sim.overlay diff --git a/tests/drivers/dma/chan_link_transfer/boards/native_posix_native_64.conf b/tests/drivers/dma/chan_link_transfer/boards/native_sim_native_64.conf similarity index 100% rename from tests/drivers/dma/chan_link_transfer/boards/native_posix_native_64.conf rename to tests/drivers/dma/chan_link_transfer/boards/native_sim_native_64.conf diff --git a/tests/drivers/dma/chan_link_transfer/testcase.yaml b/tests/drivers/dma/chan_link_transfer/testcase.yaml index 74f8b7ca13c..e22eb92057a 100644 --- a/tests/drivers/dma/chan_link_transfer/testcase.yaml +++ b/tests/drivers/dma/chan_link_transfer/testcase.yaml @@ -16,9 +16,9 @@ tests: - mimxrt1024_evk - lpcxpresso55s69/lpc55s69/cpu0 - lpcxpresso55s36 - - native_posix - - native_posix/native/64 + - native_sim + - native_sim/native/64 integration_platforms: - frdm_k64f - - native_posix - - native_posix/native/64 + - native_sim + - native_sim/native/64 diff --git a/tests/drivers/dma/loop_transfer/boards/native_posix.conf b/tests/drivers/dma/loop_transfer/boards/native_sim.conf similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/native_posix.conf rename to tests/drivers/dma/loop_transfer/boards/native_sim.conf diff --git a/tests/drivers/dma/loop_transfer/boards/native_posix.overlay b/tests/drivers/dma/loop_transfer/boards/native_sim.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/native_posix.overlay rename to tests/drivers/dma/loop_transfer/boards/native_sim.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/native_posix_native_64.conf b/tests/drivers/dma/loop_transfer/boards/native_sim_native_64.conf similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/native_posix_native_64.conf rename to tests/drivers/dma/loop_transfer/boards/native_sim_native_64.conf diff --git a/tests/drivers/dma/loop_transfer/testcase.yaml b/tests/drivers/dma/loop_transfer/testcase.yaml index 81da4ff93b1..cde5c2fe5de 100644 --- a/tests/drivers/dma/loop_transfer/testcase.yaml +++ b/tests/drivers/dma/loop_transfer/testcase.yaml @@ -5,6 +5,6 @@ tests: - drivers - dma integration_platforms: - - native_posix - - native_posix/native/64 + - native_sim + - native_sim/native/64 filter: dt_nodelabel_enabled("tst_dma0") diff --git a/tests/drivers/dma/scatter_gather/boards/native_posix.conf b/tests/drivers/dma/scatter_gather/boards/native_sim.conf similarity index 100% rename from tests/drivers/dma/scatter_gather/boards/native_posix.conf rename to tests/drivers/dma/scatter_gather/boards/native_sim.conf diff --git a/tests/drivers/dma/scatter_gather/boards/native_posix.overlay b/tests/drivers/dma/scatter_gather/boards/native_sim.overlay similarity index 100% rename from tests/drivers/dma/scatter_gather/boards/native_posix.overlay rename to tests/drivers/dma/scatter_gather/boards/native_sim.overlay diff --git a/tests/drivers/dma/scatter_gather/boards/native_posix_native_64.conf b/tests/drivers/dma/scatter_gather/boards/native_sim_native_64.conf similarity index 100% rename from tests/drivers/dma/scatter_gather/boards/native_posix_native_64.conf rename to tests/drivers/dma/scatter_gather/boards/native_sim_native_64.conf diff --git a/tests/drivers/dma/scatter_gather/testcase.yaml b/tests/drivers/dma/scatter_gather/testcase.yaml index 76b8dbe3ca6..407793a96de 100644 --- a/tests/drivers/dma/scatter_gather/testcase.yaml +++ b/tests/drivers/dma/scatter_gather/testcase.yaml @@ -9,10 +9,10 @@ tests: - frdm_k64f - mimxrt1060_evk - lpcxpresso55s36 - - native_posix - - native_posix/native/64 + - native_sim + - native_sim/native/64 filter: dt_alias_exists("dma0") integration_platforms: - intel_adsp/cavs25 - - native_posix - - native_posix/native/64 + - native_sim + - native_sim/native/64 From a4b0e8a7067c9072fcedb928d909234288bdf683 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 15 Mar 2024 16:54:47 +0100 Subject: [PATCH 0948/2402] twister tests: Let's use native_sim instead of native_posix native_posix is being replaced with native_sim, let's use native_sim instead in twister tests. Signed-off-by: Alberto Escolar Piedras --- .../test_data/tests/always_build_error/dummy/test_data.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/tests/twister_blackbox/test_data/tests/always_build_error/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/always_build_error/dummy/test_data.yaml index af7ba6f7bd7..db29b1a2a9f 100644 --- a/scripts/tests/twister_blackbox/test_data/tests/always_build_error/dummy/test_data.yaml +++ b/scripts/tests/twister_blackbox/test_data/tests/always_build_error/dummy/test_data.yaml @@ -1,8 +1,8 @@ tests: always_fail.dummy: platform_allow: - - native_posix + - native_sim - qemu_x86 - qemu_x86_64 integration_platforms: - - native_posix + - native_sim From d0ae602cef934be062155d71e0e9e9560a0e01a2 Mon Sep 17 00:00:00 2001 From: Lauren Murphy Date: Fri, 15 Mar 2024 12:46:42 -0700 Subject: [PATCH 0949/2402] tflite-micro: update README to pull optional module tflite-micro is an optional module now, and needs to be pulled for the sample to build. Fixes #69942. Signed-off-by: Lauren Murphy --- samples/modules/tflite-micro/hello_world/README.rst | 7 +++++++ samples/modules/tflite-micro/magic_wand/README.rst | 7 +++++++ samples/modules/tflite-micro/tflm_ethosu/README.rst | 7 +++++++ 3 files changed, 21 insertions(+) diff --git a/samples/modules/tflite-micro/hello_world/README.rst b/samples/modules/tflite-micro/hello_world/README.rst index 6b639da4473..daafcec0ea8 100644 --- a/samples/modules/tflite-micro/hello_world/README.rst +++ b/samples/modules/tflite-micro/hello_world/README.rst @@ -34,6 +34,13 @@ Building and Running The sample should work on most boards since it does not rely on any sensors. +Add the tflite-micro module to your West manifest and pull it: + +.. code-block:: console + + west config manifest.project-filter -- +tflite-micro + west update + The reference kernel application can be built and executed on QEMU as follows: .. zephyr-app-commands:: diff --git a/samples/modules/tflite-micro/magic_wand/README.rst b/samples/modules/tflite-micro/magic_wand/README.rst index 4a3dadbf7c4..41f05ae7278 100644 --- a/samples/modules/tflite-micro/magic_wand/README.rst +++ b/samples/modules/tflite-micro/magic_wand/README.rst @@ -24,6 +24,13 @@ from an accelerometer. Building and Running ******************** +Add the tflite-micro module to your West manifest and pull it: + +.. code-block:: console + + west config manifest.project-filter -- +tflite-micro + west update + The application can be built for the :ref:`litex-vexriscv` for emulation in Renode as follows: diff --git a/samples/modules/tflite-micro/tflm_ethosu/README.rst b/samples/modules/tflite-micro/tflm_ethosu/README.rst index 3ebefa36095..a099f8140c7 100644 --- a/samples/modules/tflite-micro/tflm_ethosu/README.rst +++ b/samples/modules/tflite-micro/tflm_ethosu/README.rst @@ -19,6 +19,13 @@ Ethos-U custom operator. Building and running ******************** +Add the tflite-micro module to your West manifest and pull it: + +.. code-block:: console + + west config manifest.project-filter -- +tflite-micro + west update + This application can be built and run on any Arm Ethos-U capable platform, for example Corstone(TM)-300. A reference implementation of Corstone-300 can be downloaded either as a FPGA bitfile for the From 58ef5fb78edea63be482f8b080074cddbccf3915 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 12 Mar 2024 15:02:42 -0700 Subject: [PATCH 0950/2402] tracing: segger-sysview: add missing thread abort enter/exit Tracing with sysview is missing both sys_port_trace_k_thread_abort_enter()/_exit() which exist on other tracing backends. So add them. Signed-off-by: Daniel Leung --- subsys/tracing/sysview/tracing_sysview.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/subsys/tracing/sysview/tracing_sysview.h b/subsys/tracing/sysview/tracing_sysview.h index a7cb25c2748..8d50f02c827 100644 --- a/subsys/tracing/sysview/tracing_sysview.h +++ b/subsys/tracing/sysview/tracing_sysview.h @@ -78,6 +78,12 @@ void sys_trace_thread_info(struct k_thread *thread); #define sys_port_trace_k_thread_abort(thread) \ SEGGER_SYSVIEW_RecordU32(TID_THREAD_ABORT, (uint32_t)(uintptr_t)thread) +#define sys_port_trace_k_thread_abort_enter(thread) \ + SEGGER_SYSVIEW_RecordU32(TID_THREAD_ABORT, (uint32_t)(uintptr_t)thread) + +#define sys_port_trace_k_thread_abort_exit(thread) \ + SEGGER_SYSVIEW_RecordEndCall(TID_THREAD_ABORT) + #define sys_port_trace_k_thread_suspend_enter(thread) \ SEGGER_SYSVIEW_RecordU32(TID_THREAD_SUSPEND, (uint32_t)(uintptr_t)thread) From a951f96766178e36f57972f964f3fd38a9ad491a Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 12 Mar 2024 12:40:10 -0700 Subject: [PATCH 0951/2402] arm: cortex_m: tracing for custom thread abort func ARM/Cortex-M has a custom implementation for thread abort (z_impl_k_thread_abort) which lacks the tracing function calls as in the generic version. So add them. Signed-off-by: Daniel Leung --- arch/arm/core/cortex_m/thread_abort.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/core/cortex_m/thread_abort.c b/arch/arm/core/cortex_m/thread_abort.c index 1ea84200cb8..99af8671107 100644 --- a/arch/arm/core/cortex_m/thread_abort.c +++ b/arch/arm/core/cortex_m/thread_abort.c @@ -25,6 +25,8 @@ void z_impl_k_thread_abort(k_tid_t thread) { + SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_thread, abort, thread); + if (_current == thread) { if (arch_is_in_isr()) { /* ARM is unlike most arches in that this is true @@ -49,4 +51,6 @@ void z_impl_k_thread_abort(k_tid_t thread) } z_thread_abort(thread); + + SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_thread, abort, thread); } From dadbe105f2028d9c1333762621cda626000ee57d Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 12 Mar 2024 12:41:36 -0700 Subject: [PATCH 0952/2402] posix: tracing for custom thread abort func POSIX has a custom implementation for thread abort (z_impl_k_thread_abort) which lacks the tracing function calls as in the generic version. So add them. Signed-off-by: Daniel Leung --- arch/posix/core/thread.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/posix/core/thread.c b/arch/posix/core/thread.c index e1ebc6fbc80..cc7fc355554 100644 --- a/arch/posix/core/thread.c +++ b/arch/posix/core/thread.c @@ -20,6 +20,11 @@ #include "posix_core.h" #include +#ifdef CONFIG_TRACING +#include +#include +#endif + /* Note that in this arch we cheat quite a bit: we use as stack a normal * pthreads stack and therefore we ignore the stack size */ @@ -62,6 +67,8 @@ void z_impl_k_thread_abort(k_tid_t thread) unsigned int key; int thread_idx; + SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_thread, abort, thread); + posix_thread_status_t *tstatus = (posix_thread_status_t *) thread->callee_saved.thread_status; @@ -103,5 +110,7 @@ void z_impl_k_thread_abort(k_tid_t thread) /* The abort handler might have altered the ready queue. */ z_reschedule_irqlock(key); + + SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_thread, abort, thread); } #endif From 81ec61c085e8782ed39ca9ad727bc3468ad66fbd Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Thu, 14 Mar 2024 15:54:28 -0500 Subject: [PATCH 0953/2402] drivers: clock_control: clock_control_mcux_syscon: make clock IDs unique Syscon clock driver previously used a sequence where clock IDs increased sequentially. This had a few disadvantages: - if a new SOC was introduced with more instances of a given IP, the clock ID could not be sequential with the remaining IDs - chance of collisions between clock IDs was relatively high To resolve this, define LPC clock IDs using a bitmask macro. Note that the CTIMER clock IDs are used within SOC clock files to perform clock init, and the macro requires that the clock ID expand to an integer rather than a expression with bitshifts (hence why the macro is not used for these IDs) Signed-off-by: Daniel DeGrasse --- .../clock_control/clock_control_mcux_syscon.c | 10 +-- drivers/counter/counter_mcux_ctimer.c | 2 +- .../dt-bindings/clock/mcux_lpc_syscon_clock.h | 87 ++++++++++--------- 3 files changed, 53 insertions(+), 46 deletions(-) diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index 32074ea224d..43148b40ed8 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -197,19 +197,19 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( #endif /* defined(CONFIG_CAN_MCUX_MCAN) */ #if defined(CONFIG_COUNTER_MCUX_CTIMER) || defined(CONFIG_PWM_MCUX_CTIMER) - case (MCUX_CTIMER0_CLK + MCUX_CTIMER_CLK_OFFSET): + case MCUX_CTIMER0_CLK: *rate = CLOCK_GetCTimerClkFreq(0); break; - case (MCUX_CTIMER1_CLK + MCUX_CTIMER_CLK_OFFSET): + case MCUX_CTIMER1_CLK: *rate = CLOCK_GetCTimerClkFreq(1); break; - case (MCUX_CTIMER2_CLK + MCUX_CTIMER_CLK_OFFSET): + case MCUX_CTIMER2_CLK: *rate = CLOCK_GetCTimerClkFreq(2); break; - case (MCUX_CTIMER3_CLK + MCUX_CTIMER_CLK_OFFSET): + case MCUX_CTIMER3_CLK: *rate = CLOCK_GetCTimerClkFreq(3); break; - case (MCUX_CTIMER4_CLK + MCUX_CTIMER_CLK_OFFSET): + case MCUX_CTIMER4_CLK: *rate = CLOCK_GetCTimerClkFreq(4); break; #endif diff --git a/drivers/counter/counter_mcux_ctimer.c b/drivers/counter/counter_mcux_ctimer.c index 339b7fb01a9..5ae3b3cacae 100644 --- a/drivers/counter/counter_mcux_ctimer.c +++ b/drivers/counter/counter_mcux_ctimer.c @@ -300,7 +300,7 @@ static const struct counter_driver_api mcux_ctimer_driver_api = { .base = (CTIMER_Type *)DT_INST_REG_ADDR(id), \ .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \ .clock_subsys = \ - (clock_control_subsys_t)(DT_INST_CLOCKS_CELL(id, name) + MCUX_CTIMER_CLK_OFFSET),\ + (clock_control_subsys_t)(DT_INST_CLOCKS_CELL(id, name)),\ .mode = DT_INST_PROP(id, mode), \ .input = DT_INST_PROP(id, input), \ .prescale = DT_INST_PROP(id, prescale), \ diff --git a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h index c3965e6cbb5..9b7eccb8a4f 100644 --- a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -7,63 +7,70 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ -#define MCUX_FLEXCOMM0_CLK 0 -#define MCUX_FLEXCOMM1_CLK 1 -#define MCUX_FLEXCOMM2_CLK 2 -#define MCUX_FLEXCOMM3_CLK 3 -#define MCUX_FLEXCOMM4_CLK 4 -#define MCUX_FLEXCOMM5_CLK 5 -#define MCUX_FLEXCOMM6_CLK 6 -#define MCUX_FLEXCOMM7_CLK 7 -#define MCUX_FLEXCOMM8_CLK 8 -#define MCUX_FLEXCOMM9_CLK 9 -#define MCUX_FLEXCOMM10_CLK 10 -#define MCUX_FLEXCOMM11_CLK 11 -#define MCUX_FLEXCOMM12_CLK 12 -#define MCUX_FLEXCOMM13_CLK 13 -#define MCUX_HS_SPI_CLK 14 -#define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK -#define MCUX_PMIC_I2C_CLK 15 -#define MCUX_HS_SPI1_CLK 16 - -#define MCUX_USDHC1_CLK 20 -#define MCUX_USDHC2_CLK 21 +/* Note- clock identifiers in this file must be unique, + * as the driver uses them in a switch case + */ -#define MCUX_CTIMER_CLK_OFFSET 22 +#define MCUX_LPC_CLK_ID(high, low) ((high << 8) | (low)) +/* These IDs are used within SOC macros, and thus cannot be defined + * using the standard MCUX_LPC_CLK_ID form + */ #define MCUX_CTIMER0_CLK 0 #define MCUX_CTIMER1_CLK 1 #define MCUX_CTIMER2_CLK 2 #define MCUX_CTIMER3_CLK 3 #define MCUX_CTIMER4_CLK 4 -#define MCUX_MCAN_CLK 27 +#define MCUX_FLEXCOMM0_CLK MCUX_LPC_CLK_ID(0x01, 0x00) +#define MCUX_FLEXCOMM1_CLK MCUX_LPC_CLK_ID(0x01, 0x01) +#define MCUX_FLEXCOMM2_CLK MCUX_LPC_CLK_ID(0x01, 0x02) +#define MCUX_FLEXCOMM3_CLK MCUX_LPC_CLK_ID(0x01, 0x03) +#define MCUX_FLEXCOMM4_CLK MCUX_LPC_CLK_ID(0x01, 0x04) +#define MCUX_FLEXCOMM5_CLK MCUX_LPC_CLK_ID(0x01, 0x05) +#define MCUX_FLEXCOMM6_CLK MCUX_LPC_CLK_ID(0x01, 0x06) +#define MCUX_FLEXCOMM7_CLK MCUX_LPC_CLK_ID(0x01, 0x07) +#define MCUX_FLEXCOMM8_CLK MCUX_LPC_CLK_ID(0x01, 0x08) +#define MCUX_FLEXCOMM9_CLK MCUX_LPC_CLK_ID(0x01, 0x09) +#define MCUX_FLEXCOMM10_CLK MCUX_LPC_CLK_ID(0x01, 0x0A) +#define MCUX_FLEXCOMM11_CLK MCUX_LPC_CLK_ID(0x01, 0x0B) +#define MCUX_FLEXCOMM12_CLK MCUX_LPC_CLK_ID(0x01, 0x0C) +#define MCUX_FLEXCOMM13_CLK MCUX_LPC_CLK_ID(0x01, 0x0D) +#define MCUX_HS_SPI_CLK MCUX_LPC_CLK_ID(0x01, 0x0E) +#define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK +#define MCUX_PMIC_I2C_CLK MCUX_LPC_CLK_ID(0x01, 0x0F) +#define MCUX_HS_SPI1_CLK MCUX_LPC_CLK_ID(0x01, 0x10) + +#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00) +#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01) + +#define MCUX_MCAN_CLK MCUX_LPC_CLK_ID(0x03, 0x00) -#define MCUX_BUS_CLK 28 +#define MCUX_BUS_CLK MCUX_LPC_CLK_ID(0x04, 0x00) -#define MCUX_SDIF_CLK 29 +#define MCUX_SDIF_CLK MCUX_LPC_CLK_ID(0x05, 0x00) -#define MCUX_I3C_CLK 30 +#define MCUX_I3C_CLK MCUX_LPC_CLK_ID(0x06, 0x00) -#define MCUX_MIPI_DSI_DPHY_CLK 31 -#define MCUX_MIPI_DSI_ESC_CLK 32 +#define MCUX_MIPI_DSI_DPHY_CLK MCUX_LPC_CLK_ID(0x07, 0x00) +#define MCUX_MIPI_DSI_ESC_CLK MCUX_LPC_CLK_ID(0x07, 0x01) -#define MCUX_LCDIF_PIXEL_CLK 33 +#define MCUX_LCDIF_PIXEL_CLK MCUX_LPC_CLK_ID(0x08, 0x00) -#define MCUX_SCTIMER_CLK 34 +#define MCUX_SCTIMER_CLK MCUX_LPC_CLK_ID(0x09, 0x00) -#define MCUX_DMIC_CLK 35 +#define MCUX_DMIC_CLK MCUX_LPC_CLK_ID(0x0A, 0x00) -#define MCUX_FLEXSPI_CLK 36 -#define MCUX_FLEXSPI2_CLK 37 +#define MCUX_FLEXSPI_CLK MCUX_LPC_CLK_ID(0x0A, 0x00) +#define MCUX_FLEXSPI2_CLK MCUX_LPC_CLK_ID(0x0A, 0x01) -#define MCUX_MRT_CLK 40 +#define MCUX_MRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x00) -#define MCUX_PORT0_CLK 41 -#define MCUX_PORT1_CLK 42 -#define MCUX_PORT2_CLK 43 -#define MCUX_PORT3_CLK 44 -#define MCUX_PORT4_CLK 45 -#define MCUX_PORT5_CLK 46 +#define MCUX_PORT0_CLK MCUX_LPC_CLK_ID(0x0C, 0x00) +#define MCUX_PORT1_CLK MCUX_LPC_CLK_ID(0x0C, 0x01) +#define MCUX_PORT2_CLK MCUX_LPC_CLK_ID(0x0C, 0x02) +#define MCUX_PORT3_CLK MCUX_LPC_CLK_ID(0x0C, 0x03) +#define MCUX_PORT4_CLK MCUX_LPC_CLK_ID(0x0C, 0x04) +#define MCUX_PORT5_CLK MCUX_LPC_CLK_ID(0x0C, 0x05) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */ From 8f4ac0d4ab450d17c852a5af2c80a8f6500f985e Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 17:13:50 +0200 Subject: [PATCH 0954/2402] net: trickle: Rename interval function The function inteval_timeout() was missing "r", the function should be called interval_timeout() Signed-off-by: Jukka Rissanen --- subsys/net/lib/trickle/trickle.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/subsys/net/lib/trickle/trickle.c b/subsys/net/lib/trickle/trickle.c index bc0925d8ce5..a1149dd030c 100644 --- a/subsys/net/lib/trickle/trickle.c +++ b/subsys/net/lib/trickle/trickle.c @@ -103,7 +103,7 @@ static inline void reschedule(struct net_trickle *trickle) k_work_reschedule(&trickle->timer, K_MSEC(diff)); } -static void inteval_timeout(struct net_trickle *trickle) +static void interval_timeout(struct net_trickle *trickle) { NET_DBG("Trickle timeout at %d", k_uptime_get_32()); @@ -130,7 +130,7 @@ static void trickle_timeout(struct k_work *work) if (trickle->double_to) { double_interval_timeout(trickle); } else { - inteval_timeout(trickle); + interval_timeout(trickle); } } From 2ea9de65c7fb09521bf8711b44c8bd9287f826fa Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 19 Mar 2024 16:49:24 -0400 Subject: [PATCH 0955/2402] ci: verify twister schema changes Run twister tests when schema changes. Signed-off-by: Anas Nashif --- .github/workflows/twister_tests.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/twister_tests.yml b/.github/workflows/twister_tests.yml index 01cf134a695..e7fe29f9e4a 100644 --- a/.github/workflows/twister_tests.yml +++ b/.github/workflows/twister_tests.yml @@ -14,6 +14,7 @@ on: - 'scripts/twister' - 'scripts/tests/twister/**' - '.github/workflows/twister_tests.yml' + - 'scripts/schemas/twister/' pull_request: branches: - main @@ -23,6 +24,7 @@ on: - 'scripts/twister' - 'scripts/tests/twister/**' - '.github/workflows/twister_tests.yml' + - 'scripts/schemas/twister/' jobs: twister-tests: From 313d135cb2469f7e69a92bd138435f7c71a659a9 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 19 Mar 2024 16:48:01 -0400 Subject: [PATCH 0956/2402] twister: do not use non-existing architectures Do not use non-existing architectures, we now have an enum in the schema. Signed-off-by: Anas Nashif --- .../1_level/2_level/board_config_1.yaml | 2 +- .../1_level/2_level/board_config_2.yaml | 2 +- .../1_level/2_level/board_config_3.yaml | 2 +- scripts/tests/twister/test_platform.py | 6 +++--- scripts/tests/twister/test_testinstance.py | 4 ++-- scripts/tests/twister/test_testplan.py | 20 +++++++++---------- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_1.yaml b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_1.yaml index 248e068ff68..b801812080c 100644 --- a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_1.yaml +++ b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_1.yaml @@ -1,7 +1,7 @@ identifier: demo_board_1 name: DEMO_Board_1 type: mcu -arch: arm_demo +arch: arm toolchain: - zephyr - gnuarmemb diff --git a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_2.yaml b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_2.yaml index 4da98f397fc..7336ba1c2f4 100644 --- a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_2.yaml +++ b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_2.yaml @@ -1,7 +1,7 @@ identifier: demo_board_2 name: DEMO_Board_2 type: mcu -arch: x86_demo +arch: x86 toolchain: - zephyr - gnuarmemb diff --git a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_3.yaml b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_3.yaml index a80ccb1d747..57118726f3c 100644 --- a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_3.yaml +++ b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_3.yaml @@ -1,7 +1,7 @@ identifier: demo_board_3 name: DEMO_Board_3 type: mcu -arch: arm_demo +arch: arm toolchain: - zephyr - gnuarmemb diff --git a/scripts/tests/twister/test_platform.py b/scripts/tests/twister/test_platform.py index b3a17231a20..4da0bb4133f 100644 --- a/scripts/tests/twister/test_platform.py +++ b/scripts/tests/twister/test_platform.py @@ -21,11 +21,11 @@ ( """\ identifier: dummy empty -arch: arch0 +arch: arc """, { 'name': 'dummy empty', - 'arch': 'arch0', + 'arch': 'arc', 'twister': True, 'ram': 128, 'timeout_multiplier': 1.0, @@ -44,7 +44,7 @@ 'env': [], 'env_satisfied': True }, - '' + '' ), ( """\ diff --git a/scripts/tests/twister/test_testinstance.py b/scripts/tests/twister/test_testinstance.py index bf3b1ff1ded..1b1c99a2143 100644 --- a/scripts/tests/twister/test_testinstance.py +++ b/scripts/tests/twister/test_testinstance.py @@ -99,9 +99,9 @@ def test_check_build_or_run( (False, False, False, ["demo_board_2"], 'native', ["CONFIG_LOG=y"], 'CONFIG_LOG=y'), (False, False, False, ["demo_board_2"], 'native', - ["arch:x86_demo:CONFIG_LOG=y"], 'CONFIG_LOG=y'), + ["arch:x86:CONFIG_LOG=y"], 'CONFIG_LOG=y'), (False, False, False, ["demo_board_2"], 'native', - ["arch:arm_demo:CONFIG_LOG=y"], ''), + ["arch:arm:CONFIG_LOG=y"], ''), (False, False, False, ["demo_board_2"], 'native', ["platform:demo_board_2:CONFIG_LOG=y"], 'CONFIG_LOG=y'), (False, False, False, ["demo_board_2"], 'native', diff --git a/scripts/tests/twister/test_testplan.py b/scripts/tests/twister/test_testplan.py index 1f765c475c1..02eae84494c 100644 --- a/scripts/tests/twister/test_testplan.py +++ b/scripts/tests/twister/test_testplan.py @@ -101,7 +101,7 @@ def test_get_platforms_short(class_testplan, platforms_list): ("platform_allow", ['demo_board_1'], None, None, "Not in testsuite platform allow list"), ("toolchain_exclude", ['zephyr'], None, None, "In test case toolchain exclude"), ("platform_exclude", ['demo_board_2'], None, None, "In test case platform exclude"), - ("arch_exclude", ['x86_demo'], None, None, "In test case arch exclude"), + ("arch_exclude", ['x86'], None, None, "In test case arch exclude"), ("arch_allow", ['arm'], None, None, "Not in test case arch allow list"), ("skip", True, None, None, "Skip filter"), ("tags", set(['sensor', 'bluetooth']), "ignore_tags", ['bluetooth'], "Excluded tags per platform (exclude_tags)"), @@ -1088,7 +1088,7 @@ def test_testplan_add_configurations( ): # tmp_path # └ boards <- board root - # ├ arch1 + # ├ x86 # │ ├ p1 # │ | ├ p1e1.yaml # │ | └ p1e2.yaml @@ -1096,7 +1096,7 @@ def test_testplan_add_configurations( # │ ├ p2.yaml # │ └ p2-1.yaml <- duplicate # │ └ p2-2.yaml <- load error - # └ arch2 + # └ arm # └ p3 # ├ p3.yaml # └ p3_B.conf @@ -1104,7 +1104,7 @@ def test_testplan_add_configurations( tmp_board_root_dir = tmp_path / 'boards' tmp_board_root_dir.mkdir() - tmp_arch1_dir = tmp_board_root_dir / 'arch1' + tmp_arch1_dir = tmp_board_root_dir / 'x86' tmp_arch1_dir.mkdir() tmp_p1_dir = tmp_arch1_dir / 'p1' @@ -1129,7 +1129,7 @@ def test_testplan_add_configurations( identifier: p1e1 name: Platform 1 Edition 1 type: native -arch: arch1 +arch: x86 vendor: vendor1 toolchain: - zephyr @@ -1142,7 +1142,7 @@ def test_testplan_add_configurations( identifier: p1e2 name: Platform 1 Edition 2 type: native -arch: arch1 +arch: x86 vendor: vendor1 toolchain: - zephyr @@ -1172,7 +1172,7 @@ def test_testplan_add_configurations( identifier: p2 name: Platform 2 type: sim -arch: arch1 +arch: x86 vendor: vendor2 toolchain: - zephyr @@ -1192,7 +1192,7 @@ def test_testplan_add_configurations( identifier: p2_2 name: Platform 2 2 type: sim -arch: arch1 +arch: x86 vendor: vendor2 toolchain: - zephyr @@ -1200,7 +1200,7 @@ def test_testplan_add_configurations( p2_2_yamlfile = tmp_p2_dir / 'p2-2.yaml' p2_2_yamlfile.write_text(p2_2_yaml) - tmp_arch2_dir = tmp_board_root_dir / 'arch2' + tmp_arch2_dir = tmp_board_root_dir / 'arm' tmp_arch2_dir.mkdir() tmp_p3_dir = tmp_arch2_dir / 'p3' @@ -1221,7 +1221,7 @@ def test_testplan_add_configurations( identifier: p3 name: Platform 3 type: unit -arch: arch2 +arch: arm vendor: vendor3 toolchain: - zephyr From 7ffafd9b6473d229e712bc67e9759042a49483f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20G=C5=82=C4=85b?= Date: Wed, 13 Mar 2024 14:53:54 +0100 Subject: [PATCH 0957/2402] drivers: watchdog: wdt_nrfx.c: Fix error code value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align driver implementation to the watchdog driver API. https://docs.zephyrproject.org/latest/hardware/peripherals/watchdog.html int wdt_disable(const struct device *dev) shall return: 0 – If successful. -EFAULT – If watchdog instance is not enabled. -EPERM – If watchdog can not be disabled directly by application code. -errno – In case of any other failure. Signed-off-by: Sebastian Głąb --- drivers/watchdog/wdt_nrfx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/wdt_nrfx.c b/drivers/watchdog/wdt_nrfx.c index 5601470b540..57b4dba828c 100644 --- a/drivers/watchdog/wdt_nrfx.c +++ b/drivers/watchdog/wdt_nrfx.c @@ -65,7 +65,8 @@ static int wdt_nrf_disable(const struct device *dev) err_code = nrfx_wdt_stop(&config->wdt); if (err_code != NRFX_SUCCESS) { - return -ENOTSUP; + /* This can only happen if wdt_nrf_setup() is not called first. */ + return -EFAULT; } return 0; From decf714f7a62b3ef2fb2e92b37442da10142525c Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Sun, 17 Mar 2024 22:36:07 +0800 Subject: [PATCH 0958/2402] twister: add linkserver support with hardwaremap in hardwaremap the dev-id is used to select debug probe and linkserver accept the --probe. so and this support Signed-off-by: Hake Huang --- scripts/pylib/twister/twisterlib/handlers.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py index 5ffba005539..d156fa6b3d2 100755 --- a/scripts/pylib/twister/twisterlib/handlers.py +++ b/scripts/pylib/twister/twisterlib/handlers.py @@ -514,6 +514,11 @@ def _create_command(self, runner, hardware): command_extra_args.append("cmsis_dap_serial %s" % board_id) elif runner == "jlink": command.append("--tool-opt=-SelectEmuBySN %s" % board_id) + elif runner == "linkserver": + # for linkserver + # --probe=# select by probe index + # --probe= select by probe serial number + command.append("--probe=%s" % board_id) elif runner == "stm32cubeprogrammer": command.append("--tool-opt=sn=%s" % board_id) From f82a86c21b1278f9185373edd001691d7998cac3 Mon Sep 17 00:00:00 2001 From: Aleksander Wasaznik Date: Wed, 13 Mar 2024 19:11:43 +0100 Subject: [PATCH 0959/2402] Bluetooth: testlib: `bt_testlib_connect`: better error logs Changes to logging: - Don't log "Connected" if there was an error. - Identify the relevant bt_conn object in log messages by its index. - Special case non-fatal errors: - Failure due to out of free conn object is INF. - Improve transparancy of error messages: - For errno, include the name of the API. - For HCI errors, include the common prefix of the symbols 'BT_HCI_ERR_' so they are easier to look up. This change includes some light refactoring to make the code more understandable, but does not change any behavior. Signed-off-by: Aleksander Wasaznik --- tests/bluetooth/common/testlib/src/connect.c | 88 +++++++++++++------- 1 file changed, 57 insertions(+), 31 deletions(-) diff --git a/tests/bluetooth/common/testlib/src/connect.c b/tests/bluetooth/common/testlib/src/connect.c index e8f5a90224e..9e181a574e3 100644 --- a/tests/bluetooth/common/testlib/src/connect.c +++ b/tests/bluetooth/common/testlib/src/connect.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2023 Nordic Semiconductor ASA +/* Copyright (c) 2023-2024 Nordic Semiconductor ASA * SPDX-License-Identifier: Apache-2.0 */ @@ -12,10 +12,10 @@ LOG_MODULE_REGISTER(bt_testlib_connect, LOG_LEVEL_INF); struct bt_testlib_connect_closure { - uint8_t conn_err; - struct bt_conn **conn; + uint8_t conn_cb_connected_err; + struct bt_conn **connp; struct k_mutex lock; - struct k_condvar done; + struct k_condvar conn_cb_connected_match; }; /* Context pool (with capacity of one). */ @@ -23,63 +23,89 @@ static K_SEM_DEFINE(g_ctx_free, 1, 1); static K_MUTEX_DEFINE(g_ctx_lock); static struct bt_testlib_connect_closure *g_ctx; -static void connected_cb(struct bt_conn *conn, uint8_t conn_err) +static void on_conn_cb_connected(struct bt_conn *conn, uint8_t conn_err) { /* Loop over each (allocated) item in pool. */ k_mutex_lock(&g_ctx_lock, K_FOREVER); - if (g_ctx && conn == *g_ctx->conn) { - g_ctx->conn_err = conn_err; - k_condvar_signal(&g_ctx->done); + if (g_ctx && conn == *g_ctx->connp) { + g_ctx->conn_cb_connected_err = conn_err; + k_condvar_signal(&g_ctx->conn_cb_connected_match); } k_mutex_unlock(&g_ctx_lock); } -BT_CONN_CB_DEFINE(conn_callbacks) = { - .connected = connected_cb, +BT_CONN_CB_DEFINE(conn_cb) = { + .connected = on_conn_cb_connected, }; -int bt_testlib_connect(const bt_addr_le_t *peer, struct bt_conn **conn) +int bt_testlib_connect(const bt_addr_le_t *peer, struct bt_conn **connp) { - int api_err; + int err; struct bt_testlib_connect_closure ctx = { - .conn = conn, + .connp = connp, }; + uint8_t conn_index; - __ASSERT_NO_MSG(conn); - __ASSERT_NO_MSG(*conn == NULL); + __ASSERT_NO_MSG(connp); + __ASSERT_NO_MSG(*connp == NULL); - k_condvar_init(&ctx.done); + k_condvar_init(&ctx.conn_cb_connected_match); + /* If multiple threads call into this funciton, they will wait + * for their turn here. The Zephyr host does not support + * concurrent connection creation. + */ k_sem_take(&g_ctx_free, K_FOREVER); k_mutex_lock(&g_ctx_lock, K_FOREVER); g_ctx = &ctx; - api_err = bt_conn_le_create(peer, BT_CONN_LE_CREATE_CONN, BT_LE_CONN_PARAM_DEFAULT, conn); + err = bt_conn_le_create(peer, BT_CONN_LE_CREATE_CONN, BT_LE_CONN_PARAM_DEFAULT, connp); - if (!api_err) { - LOG_INF("Connecting.. conn %u", bt_conn_index(*conn)); - k_condvar_wait(&ctx.done, &g_ctx_lock, K_FOREVER); - LOG_INF("Connect complete"); + if (!err) { + conn_index = bt_conn_index(*connp); + LOG_INF("bt_conn_le_create ok conn %u", conn_index); + + k_condvar_wait(&ctx.conn_cb_connected_match, &g_ctx_lock, K_FOREVER); } g_ctx = NULL; k_mutex_unlock(&g_ctx_lock); k_sem_give(&g_ctx_free); - if (api_err) { - LOG_ERR("bt_conn_le_create err %d", api_err); - __ASSERT_NO_MSG(api_err < 0); - return api_err; + /* Merge the error codes. The errors from `bt_conn_le_create` + * are negative, leaving the positive space for the HCI errors + * from `conn_cb_connected`. + */ + __ASSERT_NO_MSG(err <= 0); + __ASSERT_NO_MSG(0 <= ctx.conn_cb_connected_err); + __ASSERT_NO_MSG(!err || !ctx.conn_cb_connected_err); + err = err + ctx.conn_cb_connected_err; + + /* This is just logging. */ + switch (err) { + case -ENOMEM: + LOG_INF("bt_conn_le_create -ENOMEM: No free connection objects available."); + break; + case 0: + LOG_INF("conn %u: connected", conn_index); + break; + case BT_HCI_ERR_UNKNOWN_CONN_ID: + LOG_INF("conn %u: timed out", conn_index); + break; + default: + if (err < 0) { + LOG_ERR("bt_conn_le_create err %d", err); + } else { + LOG_ERR("conn %u: BT_HCI_ERR_ 0x%02x", conn_index, err); + } } - if (ctx.conn_err) { - LOG_ERR("Connect HCI err %d", ctx.conn_err); - __ASSERT_NO_MSG(ctx.conn_err >= 0); - return ctx.conn_err; - } + /* Note: `connp` is never unrefed in this funciton, even in case + * of errors. This is as documented. + */ - return 0; + return err; } From 16ba4bd564ac87421f8c1ace35cb55c643669ccf Mon Sep 17 00:00:00 2001 From: Aleksander Wasaznik Date: Sat, 16 Mar 2024 16:55:33 +0100 Subject: [PATCH 0960/2402] Bluetooth: CI: trigger bsim on testlib change Some bsim tests have a dependency on testlib. Since testlib does not have a stable API, it's a good idea to run the bsim tests. Signed-off-by: Aleksander Wasaznik --- .github/workflows/bsim-tests.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 15e640b03a0..97a84732980 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -8,6 +8,7 @@ on: - "west.yml" - "subsys/bluetooth/**" - "tests/bsim/**" + - "tests/bluetooth/common/testlib/**" - "samples/bluetooth/**" - "boards/posix/**" - "soc/posix/**" From 857abb8276a59ce79ac85a99012c7ca9905e1813 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Mon, 29 Jan 2024 15:04:45 -0800 Subject: [PATCH 0961/2402] xtensa: userspace: simplify syscall trampoline a bit There is no need to do a call4 and jx. Simply do a callx4 is enough. Also amended the now incorrect comment about how syscall trampoline is set up. It is now a straight call4 instead of the old 2x call4. Signed-off-by: Daniel Leung --- arch/xtensa/core/userspace.S | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/xtensa/core/userspace.S b/arch/xtensa/core/userspace.S index c798e129762..cd446c49c3b 100644 --- a/arch/xtensa/core/userspace.S +++ b/arch/xtensa/core/userspace.S @@ -122,9 +122,14 @@ _id_ok: wur.THREADPTR a0 #endif - /* Set syscall parameters. We have an initial call4 to set up the - * the stack and then a new call4 for the syscall function itself. - * So parameters should be put as if it was a call8. + /* Set syscall parameters by moving them into place before we do + * a call4 for the syscall function itself. + * arg1 = a6 + * arg2 = a3 (clobbered above, so we need to reload it) + * arg3 = a4 + * arg4 = a5 + * arg5 = a8 + * arg6 = a9 */ mov a10, a8 mov a11, a9 @@ -141,7 +146,7 @@ _id_ok: wsr.ps a0 rsync - call4 _syscall_call0 + callx4 a2 /* copy return value. Lets put it in the top of stack * because registers will be clobbered in @@ -152,12 +157,6 @@ _id_ok: j _syscall_returned -.align 4 -_syscall_call0: - /* We want an ENTRY to set a bit in windowstart */ - jx a2 - - _syscall_returned: call0 xtensa_restore_high_regs From 5db5e8e1097aa28a02722c4096cb950202593fff Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 30 Jan 2024 14:23:06 -0800 Subject: [PATCH 0962/2402] xtensa: userspace: fix incorrectly passed syscall frame pointer Calling z_mrsh_* functions require 7 arguments where the 7th is the stack frame. Only the first 6 arguments are passed by registers where the 7th must be done via stack. However, this is not being done and an incorrect argument was being passed to the z_mrsh_* functions as stack frame pointer. An obvious issue would be dumping of stack during kernel oops, as incorrect data was being printed or crashes due to inaccessible memory. So fix it by properly populating the stack with correct stack frame pointer as outgoing argument for the caller of z_mrsh_* functions. Signed-off-by: Daniel Leung --- arch/xtensa/core/userspace.S | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/xtensa/core/userspace.S b/arch/xtensa/core/userspace.S index cd446c49c3b..75d46cb1216 100644 --- a/arch/xtensa/core/userspace.S +++ b/arch/xtensa/core/userspace.S @@ -135,7 +135,15 @@ _id_ok: mov a11, a9 mov a8, a4 mov a9, a5 - l32i a3, a1, 0 + + /* Stack frame pointer is the 7th argument to z_mrsh_*() + * as ssf, and must be put on stack to be consumed. + */ + mov a3, a1 + addi a1, a1, -4 + s32i a3, a1, 0 + + l32i a3, a1, 4 l32i a7, a3, ___xtensa_irq_bsa_t_a3_OFFSET @@ -148,6 +156,12 @@ _id_ok: callx4 a2 + /* Going back before stack frame pointer on stack to + * actual the stack frame. So restoration of registers + * can be done properly when finishing syscalls. + */ + addi a1, a1, 4 + /* copy return value. Lets put it in the top of stack * because registers will be clobbered in * xtensa_restore_high_regs From b019dcb05efdc4009c0792669aba2d6c11686d30 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 26 Jan 2024 15:10:47 -0800 Subject: [PATCH 0963/2402] xtensa: userspace: use syscall to check if user context For CPU without THREADPTR, we need an alternative way to figure out if we are in user context. This extends the user context check to do that via a brief syscall. Signed-off-by: Daniel Leung --- arch/xtensa/core/CMakeLists.txt | 21 +++++++++++++-- arch/xtensa/core/gen_zsr.py | 10 +++++++ arch/xtensa/core/syscall_helper.c | 20 ++++++++++++++ arch/xtensa/core/userspace.S | 39 ++++++++++++++++++++++++++++ include/zephyr/arch/xtensa/syscall.h | 9 +++++++ 5 files changed, 97 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index 7119c1046c7..5f5ba829dca 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -23,8 +23,7 @@ zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c) zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c) zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c) zephyr_library_sources_ifdef(CONFIG_XTENSA_MMU ptables.c mmu.c) -zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S) -zephyr_library_sources_ifdef(CONFIG_XTENSA_SYSCALL_USE_HELPER syscall_helper.c) +zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S syscall_helper.c) zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) zephyr_library_sources_ifdef(CONFIG_SMP smp.c) zephyr_library_sources_ifdef(CONFIG_XTENSA_HIFI_SHARING xtensa_hifi.S) @@ -57,12 +56,30 @@ add_custom_command(OUTPUT ${CORE_ISA_DM} -I${SOC_FULL_DIR} ${CORE_ISA_IN} -o ${CORE_ISA_DM}) +if(CONFIG_USERSPACE AND NOT CONFIG_THREAD_LOCAL_STORAGE) + # It is possible that the SoC does not have THREADPTR. + # This means that we cannot use THREADPTR as a shortcut to + # in arch_is_user_context(). However, whether a SoC has + # THREADPTR is in core-isa.h which can be parsed in gen_zsr.py. + # There, if there is no THREADPTR, we need a scratch register + # so we can do arch_is_user_context() via syscall. + set(MAY_NEED_SYSCALL_SCRATCH_REG true) +else() + # With thread local storage, the variable is_user_mode is + # stored in the thread's TLS area. There is no need for + # scratch register. + set(MAY_NEED_SYSCALL_SCRATCH_REG false) +endif() + # Generates a list of device-specific scratch register choices set(ZSR_H ${CMAKE_BINARY_DIR}/zephyr/include/generated/zsr.h) add_custom_command(OUTPUT ${ZSR_H} DEPENDS ${CORE_ISA_DM} COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_zsr.py $<$:--mmu> + $<$:--syscall-scratch> $<$:--coherence> ${CORE_ISA_DM} ${ZSR_H}) add_custom_target(zsr_h DEPENDS ${ZSR_H}) add_dependencies(zephyr_interface zsr_h) + +unset(MAY_NEED_SYSCALL_SCRATCH_REG) diff --git a/arch/xtensa/core/gen_zsr.py b/arch/xtensa/core/gen_zsr.py index 7f0ec46b8e9..26797a7fe57 100755 --- a/arch/xtensa/core/gen_zsr.py +++ b/arch/xtensa/core/gen_zsr.py @@ -18,6 +18,8 @@ def parse_args(): help="Enable scratch registers for CONFIG_KERNEL_COHERENCE") parser.add_argument("--mmu", action="store_true", help="Enable scratch registers for MMU usage") + parser.add_argument("--syscall-scratch", action="store_true", + help="Enable scratch registers for syscalls if needed") parser.add_argument("coreisa", help="Path to preprocessed core-isa.h") parser.add_argument("outfile", @@ -50,6 +52,14 @@ def get(s): # Use MISC registers first if available, that's what they're for regs = [ f"MISC{n}" for n in range(0, int(get("XCHAL_NUM_MISC_REGS"))) ] +if args.syscall_scratch: + # If there is no THREADPTR, we need to use syscall for + # arch_is_user_context() where the code needs a scratch + # register. + have_threadptr = int(get("XCHAL_HAVE_THREADPTR")) + if have_threadptr == 0: + NEEDED.append("SYSCALL_SCRATCH") + # Next come EXCSAVE. Also record our highest non-debug interrupt level. maxint = 0 for il in range(1, 1 + int(get("XCHAL_NUM_INTLEVELS"))): diff --git a/arch/xtensa/core/syscall_helper.c b/arch/xtensa/core/syscall_helper.c index f8fb7ec903e..da2a5551c9a 100644 --- a/arch/xtensa/core/syscall_helper.c +++ b/arch/xtensa/core/syscall_helper.c @@ -6,6 +6,7 @@ #include +#ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER uintptr_t xtensa_syscall_helper(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, uintptr_t arg4, uintptr_t arg5, uintptr_t arg6, @@ -27,3 +28,22 @@ uintptr_t xtensa_syscall_helper(uintptr_t arg1, uintptr_t arg2, return a2; } +#endif /* CONFIG_XTENSA_SYSCALL_USE_HELPER */ + +#if XCHAL_HAVE_THREADPTR == 0 +#include +#include + +bool xtensa_is_user_context(void) +{ + uint32_t ret; + + __asm__ volatile(".global xtensa_is_user_context_epc\n" + " xtensa_is_user_context_epc:\n" + " syscall\n" + " mov %0, a2\n" + : "=r"(ret) : : "a2"); + + return ret != 0; +} +#endif /* XCHAL_HAVE_THREADPTR */ diff --git a/arch/xtensa/core/userspace.S b/arch/xtensa/core/userspace.S index 75d46cb1216..7aaa27fdd4b 100644 --- a/arch/xtensa/core/userspace.S +++ b/arch/xtensa/core/userspace.S @@ -10,6 +10,8 @@ #include #include +#include + /** * syscall number arg1, arg2, arg3, arg4, arg5, arg6 * -------------- ---------------------------------- @@ -20,6 +22,37 @@ .global xtensa_do_syscall .align 4 xtensa_do_syscall: +#if XCHAL_HAVE_THREADPTR == 0 + wsr a2, ZSR_SYSCALL_SCRATCH + rsync + + movi a0, xtensa_is_user_context_epc + rsr.epc1 a2 + bne a0, a2, _not_checking_user_context + + addi a2, a2, 3 + wsr.epc1 a2 + + movi a0, PS_RING_MASK + rsr.ps a2 + and a2, a2, a0 + + /* Need to set return to 1 if RING != 0, + * so we won't be leaking which ring we are in + * right now. + */ + beqz a2, _is_user_context_return + + movi a2, 1 + +_is_user_context_return: + rsr a0, ZSR_A0SAVE + + rfe + +_not_checking_user_context: + rsr a2, ZSR_SYSCALL_SCRATCH +#endif rsr a0, ZSR_CPU l32i a0, a0, ___cpu_t_current_OFFSET l32i a0, a0, _thread_offset_to_psp @@ -105,6 +138,7 @@ _id_ok: add a2, a2, a3 l32i a2, a2, 0 +#if XCHAL_HAVE_THREADPTR /* Clear up the threadptr because it is used * to check if a thread is running on user mode. Since * we are in a interruption we don't want the system @@ -121,6 +155,7 @@ _id_ok: movi a0, 0 wur.THREADPTR a0 #endif +#endif /* XCHAL_HAVE_THREADPTR */ /* Set syscall parameters by moving them into place before we do * a call4 for the syscall function itself. @@ -189,6 +224,7 @@ _syscall_returned: wsr a3, SCOMPARE1 #endif +#if XCHAL_HAVE_THREADPTR #ifdef CONFIG_THREAD_LOCAL_STORAGE l32i a3, a1, ___xtensa_irq_bsa_t_threadptr_OFFSET movi a0, is_user_mode@tpoff @@ -200,6 +236,7 @@ _syscall_returned: l32i a3, a3, ___cpu_t_current_OFFSET wur.THREADPTR a3 #endif +#endif /* XCHAL_HAVE_THREADPTR */ l32i a3, a1, ___xtensa_irq_bsa_t_ps_OFFSET wsr.ps a3 @@ -265,6 +302,7 @@ xtensa_userspace_enter: l32i a6, a1, 24 call4 xtensa_swap_update_page_tables +#if XCHAL_HAVE_THREADPTR #ifdef CONFIG_THREAD_LOCAL_STORAGE rur.threadptr a3 movi a0, is_user_mode@tpoff @@ -276,6 +314,7 @@ xtensa_userspace_enter: l32i a3, a3, ___cpu_t_current_OFFSET wur.THREADPTR a3 #endif +#endif /* XCHAL_HAVE_THREADPTR */ /* Set now z_thread_entry parameters, we are simulating a call4 * call, so parameters start at a6, a7, ... diff --git a/include/zephyr/arch/xtensa/syscall.h b/include/zephyr/arch/xtensa/syscall.h index b8b0bea8cdb..c1bbd29174c 100644 --- a/include/zephyr/arch/xtensa/syscall.h +++ b/include/zephyr/arch/xtensa/syscall.h @@ -24,6 +24,8 @@ #include #include +#include + #ifdef __cplusplus extern "C" { #endif @@ -201,6 +203,7 @@ static SYSINL uintptr_t arch_syscall_invoke0(uintptr_t call_id) */ static inline bool arch_is_user_context(void) { +#if XCHAL_HAVE_THREADPTR uint32_t thread; __asm__ volatile( @@ -218,6 +221,12 @@ static inline bool arch_is_user_context(void) #else return !!thread; #endif + +#else /* XCHAL_HAVE_THREADPTR */ + extern bool xtensa_is_user_context(void); + + return xtensa_is_user_context(); +#endif /* XCHAL_HAVE_THREADPTR */ } #undef SYSINL From da584af9aa480b562e371cab39135f1c6571bd8b Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Mon, 29 Jan 2024 12:14:15 -0800 Subject: [PATCH 0964/2402] xtensa: move two kconfigs out of CPU_HAS_MMU block Both CONFIG_XTENSA_SYSCALL_USE_HELPER and CONFIG_XTENSA_INSECURE_USERSPACE are also applicable to MPU. So move them out of the CPU_HAS_MMU block. Signed-off-by: Daniel Leung --- arch/xtensa/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index af22ccb90c9..a410e2bd2dc 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -212,10 +212,12 @@ config PRIVILEGED_STACK_SIZE endif # XTENSA_MMU +endif # CPU_HAS_MMU + config XTENSA_SYSCALL_USE_HELPER bool "Use userspace syscall helper" default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xt-clang" - depends on USERSPACE + depends on XTENSA_MMU && USERSPACE help Use syscall helpers for passing more then 3 arguments. This is a workaround for toolchains where they have @@ -223,9 +225,7 @@ config XTENSA_SYSCALL_USE_HELPER config XTENSA_INSECURE_USERSPACE bool - default y if USERSPACE - depends on XTENSA_MMU - -endif # CPU_HAS_MMU + default y + depends on XTENSA_MMU && USERSPACE endmenu From df350c7469fdbd46df7e00d1a586b6d0c704205e Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 15 Mar 2024 17:37:23 -0700 Subject: [PATCH 0965/2402] xtensa: add MPU support for kernel mode This enables support for MPU on Xtensa. Currently this is for kernel mode only. Signed-off-by: Daniel Leung --- arch/xtensa/Kconfig | 28 + arch/xtensa/core/CMakeLists.txt | 1 + arch/xtensa/core/mpu.c | 702 +++++++++++++++++++++++++ arch/xtensa/include/kernel_arch_func.h | 4 + arch/xtensa/include/xtensa_mpu_priv.h | 415 +++++++++++++++ include/zephyr/arch/xtensa/arch.h | 6 + include/zephyr/arch/xtensa/mpu.h | 247 +++++++++ 7 files changed, 1403 insertions(+) create mode 100644 arch/xtensa/core/mpu.c create mode 100644 arch/xtensa/include/xtensa_mpu_priv.h create mode 100644 include/zephyr/arch/xtensa/mpu.h diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index a410e2bd2dc..6ed703b2521 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -214,6 +214,34 @@ endif # XTENSA_MMU endif # CPU_HAS_MMU +if CPU_HAS_MPU + +menuconfig XTENSA_MPU + bool "Xtensa MPU Support" + select MPU + select SRAM_REGION_PERMISSIONS + select XTENSA_SMALL_VECTOR_TABLE_ENTRY + select EXPERIMENTAL + # TODO: the target the MPU code developed on (basically sample_controller + # plus MPU minus s32c1i) does not have cache or SMP capability. + # Need to verify functionalities with targets supporting these. + depends on !CACHE && !SMP + help + Enable support for Xtensa Memory Protection Unit. + +if XTENSA_MPU + +config XTENSA_MPU_DEFAULT_MEM_TYPE + hex "Default Memory Type" + default 0x18 + help + Default memory type for memory regions: non-cacheable memory, + non-shareable, non-bufferable and interruptible. + +endif # XTENSA_MPU + +endif # CPU_HAS_MPU + config XTENSA_SYSCALL_USE_HELPER bool "Use userspace syscall helper" default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xt-clang" diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index 5f5ba829dca..fab15a803da 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -23,6 +23,7 @@ zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c) zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c) zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c) zephyr_library_sources_ifdef(CONFIG_XTENSA_MMU ptables.c mmu.c) +zephyr_library_sources_ifdef(CONFIG_XTENSA_MPU mpu.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S syscall_helper.c) zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) zephyr_library_sources_ifdef(CONFIG_SMP smp.c) diff --git a/arch/xtensa/core/mpu.c b/arch/xtensa/core/mpu.c new file mode 100644 index 00000000000..d34aeee892b --- /dev/null +++ b/arch/xtensa/core/mpu.c @@ -0,0 +1,702 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +extern char _heap_end[]; +extern char _heap_start[]; + +/** MPU foreground map for kernel mode. */ +static struct xtensa_mpu_map xtensa_mpu_map_fg_kernel; + +/* + * Additional information about the MPU maps: foreground and background + * maps. + * + * + * Some things to keep in mind: + * - Each MPU region is described by TWO entries: + * [entry_a_address, entry_b_address). For contiguous memory regions, + * this should not much of an issue. However, disjoint memory regions + * "waste" another entry to describe the end of those regions. + * We might run out of available entries in the MPU map because of + * this. + * - The last entry is a special case as there is no more "next" + * entry in the map. In this case, the end of memory is + * the implicit boundary. In another word, the last entry + * describes the region between the start address of this entry + * and the end of memory. + * - Current implementation has following limitations: + * - All enabled entries are grouped towards the end of the map. + * - Except the last entry which can be disabled. This is + * the end of the last foreground region. With a disabled + * entry, memory after this will use the background map + * for access control. + * - No disabled MPU entries allowed in between. + * + * + * For foreground map to be valid, its entries must follow these rules: + * - The start addresses must always be in non-descending order. + * - The access rights and memory type fields must contain valid values. + * - The segment field needs to be correct for each entry. + * - MBZ fields must contain only zeroes. + * - Although the start address occupies 27 bits of the register, + * it does not mean all 27 bits are usable. The macro + * XCHAL_MPU_ALIGN_BITS provided by the toolchain indicates + * that only bits of and left of this value are valid. This + * corresponds to the minimum segment size (MINSEGMENTSIZE) + * definied in the processor configuration. + */ + +/** + * Static definition of all code and data memory regions of the + * current Zephyr image. This information must be available and + * need to be processed upon MPU initialization. + */ +static const struct xtensa_mpu_range mpu_zephyr_ranges[] = { + /* Region for vector handlers. */ + { + .start = (uintptr_t)XCHAL_VECBASE_RESET_VADDR, + /* + * There is nothing from the Xtensa overlay about how big + * the vector handler region is. So we make an assumption + * that vecbase and .text are contiguous. + * + * SoC can override as needed if this is not the case, + * especially if the SoC reset/startup code relocates + * vecbase. + */ + .end = (uintptr_t)__text_region_start, + .access_rights = XTENSA_MPU_ACCESS_P_RX_U_RX, + .memory_type = CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, + }, + /* + * Mark the zephyr execution regions (data, bss, noinit, etc.) + * cacheable, read / write and non-executable + */ + { + /* This includes .data, .bss and various kobject sections. */ + .start = (uintptr_t)_image_ram_start, + .end = (uintptr_t)_image_ram_end, + .access_rights = XTENSA_MPU_ACCESS_P_RW_U_NA, + .memory_type = CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, + }, +#if K_HEAP_MEM_POOL_SIZE > 0 + /* System heap memory */ + { + .start = (uintptr_t)_heap_start, + .end = (uintptr_t)_heap_end, + .access_rights = XTENSA_MPU_ACCESS_P_RW_U_NA, + .memory_type = CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, + }, +#endif + /* Mark text segment cacheable, read only and executable */ + { + .start = (uintptr_t)__text_region_start, + .end = (uintptr_t)__text_region_end, + .access_rights = XTENSA_MPU_ACCESS_P_RX_U_RX, + .memory_type = CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, + }, + /* Mark rodata segment cacheable, read only and non-executable */ + { + .start = (uintptr_t)__rodata_region_start, + .end = (uintptr_t)__rodata_region_end, + .access_rights = XTENSA_MPU_ACCESS_P_RO_U_RO, + .memory_type = CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, + }, +}; + +/** + * Return the pointer to the entry encompassing @a addr out of an array of MPU entries. + * + * Returning the entry where @a addr is greater or equal to the entry's start address, + * and where @a addr is less than the starting address of the next entry. + * + * @param[in] entries Array of MPU entries. + * @param[in] addr Address to be matched to one background entry. + * @param[in] first_enabled_idx The index of the first enabled entry. + * Use 0 if not sure. + * @param[out] exact Set to true if address matches exactly. + * NULL if do not care. + * @param[out] entry_idx Set to the index of the entry array if entry is found. + * NULL if do not care. + * + * @return Pointer to the map entry encompassing @a addr, or NULL if no such entry found. + */ +static const +struct xtensa_mpu_entry *check_addr_in_mpu_entries(const struct xtensa_mpu_entry *entries, + uintptr_t addr, uint8_t first_enabled_idx, + bool *exact, uint8_t *entry_idx) +{ + const struct xtensa_mpu_entry *ret = NULL; + uintptr_t s_addr, e_addr; + uint8_t idx; + + if (first_enabled_idx >= XTENSA_MPU_NUM_ENTRIES) { + goto out_null; + } + + if (addr < xtensa_mpu_entry_start_address_get(&entries[first_enabled_idx])) { + /* Before the start address of very first entry. So no match. */ + goto out_null; + } + + /* Loop through the map except the last entry (which is a special case). */ + for (idx = first_enabled_idx; idx < (XTENSA_MPU_NUM_ENTRIES - 1); idx++) { + s_addr = xtensa_mpu_entry_start_address_get(&entries[idx]); + e_addr = xtensa_mpu_entry_start_address_get(&entries[idx + 1]); + + if ((addr >= s_addr) && (addr < e_addr)) { + ret = &entries[idx]; + goto out; + } + } + + idx = XTENSA_MPU_NUM_ENTRIES - 1; + s_addr = xtensa_mpu_entry_start_address_get(&entries[idx]); + if (addr >= s_addr) { + /* Last entry encompasses the start address to end of memory. */ + ret = &entries[idx]; + } + +out: + if (ret != NULL) { + if (exact != NULL) { + if (addr == s_addr) { + *exact = true; + } else { + *exact = false; + } + } + + if (entry_idx != NULL) { + *entry_idx = idx; + } + } + +out_null: + return ret; +} + +/** + * Find the first enabled MPU entry. + * + * @param entries Array of MPU entries with XTENSA_MPU_NUM_ENTRIES elements. + * + * @return Index of the first enabled entry. + * @retval XTENSA_MPU_NUM_ENTRIES if no entry is enabled. + */ +static inline uint8_t find_first_enabled_entry(const struct xtensa_mpu_entry *entries) +{ + int first_enabled_idx; + + for (first_enabled_idx = 0; first_enabled_idx < XTENSA_MPU_NUM_ENTRIES; + first_enabled_idx++) { + if (entries[first_enabled_idx].as.p.enable) { + break; + } + } + + return first_enabled_idx; +} + +/** + * Compare two MPU entries. + * + * This is used by qsort to compare two MPU entries on their ordering + * based on starting address. + * + * @param a First MPU entry. + * @param b Second MPU entry. + * + * @retval -1 First address is less than second address. + * @retval 0 First address is equal to second address. + * @retval 1 First address is great than second address. + */ +static int compare_entries(const void *a, const void *b) +{ + struct xtensa_mpu_entry *e_a = (struct xtensa_mpu_entry *)a; + struct xtensa_mpu_entry *e_b = (struct xtensa_mpu_entry *)b; + + uintptr_t addr_a = xtensa_mpu_entry_start_address_get(e_a); + uintptr_t addr_b = xtensa_mpu_entry_start_address_get(e_b); + + if (addr_a < addr_b) { + return -1; + } else if (addr_a == addr_b) { + return 0; + } else { + return 1; + } +} + +/** + * Sort the MPU entries base on starting address. + * + * This sorts the MPU entries in ascending order of starting address. + * After sorting, it rewrites the segment numbers of all entries. + */ +static void sort_entries(struct xtensa_mpu_entry *entries) +{ + qsort(entries, XTENSA_MPU_NUM_ENTRIES, sizeof(entries[0]), compare_entries); + + for (uint32_t idx = 0; idx < XTENSA_MPU_NUM_ENTRIES; idx++) { + /* Segment value must correspond to the index. */ + entries[idx].at.p.segment = idx; + } +} + +/** + * Consolidate the MPU entries. + * + * This removes consecutive entries where the attributes are the same. + * + * @param entries Array of MPU entries with XTENSA_MPU_NUM_ENTRIES elements. + * @param first_enabled_idx Index of first enabled entry. + * + * @return Index of the first enabled entry after consolidation. + */ +static uint8_t consolidate_entries(struct xtensa_mpu_entry *entries, + uint8_t first_enabled_idx) +{ + uint8_t new_first; + uint8_t idx_0 = first_enabled_idx; + uint8_t idx_1 = first_enabled_idx + 1; + bool to_consolidate = false; + + /* For each a pair of entries... */ + while (idx_1 < XTENSA_MPU_NUM_ENTRIES) { + struct xtensa_mpu_entry *entry_0 = &entries[idx_0]; + struct xtensa_mpu_entry *entry_1 = &entries[idx_1]; + bool mark_disable_0 = false; + bool mark_disable_1 = false; + + if (xtensa_mpu_entries_has_same_attributes(entry_0, entry_1)) { + /* + * If both entry has same attributes (access_rights and memory type), + * they can be consolidated into one by removing the higher indexed + * one. + */ + mark_disable_1 = true; + } else if (xtensa_mpu_entries_has_same_address(entry_0, entry_1)) { + /* + * If both entries have the same address, the higher index + * one always override the lower one. So remove the lower indexed + * one. + */ + mark_disable_0 = true; + } + + /* + * Marking an entry as disabled here so it can be removed later. + * + * The MBZ field of the AS register is re-purposed to indicate that + * this is an entry to be removed. + */ + if (mark_disable_1) { + /* Remove the higher indexed entry. */ + to_consolidate = true; + + entry_1->as.p.mbz = 1U; + + /* Skip ahead for next comparison. */ + idx_1++; + continue; + } else if (mark_disable_0) { + /* Remove the lower indexed entry. */ + to_consolidate = true; + + entry_0->as.p.mbz = 1U; + } + + idx_0 = idx_1; + idx_1++; + } + + if (to_consolidate) { + uint8_t read_idx = XTENSA_MPU_NUM_ENTRIES - 1; + uint8_t write_idx = XTENSA_MPU_NUM_ENTRIES; + + /* Go through the map from the end and copy enabled entries in place. */ + while (read_idx >= first_enabled_idx) { + struct xtensa_mpu_entry *entry_rd = &entries[read_idx]; + + if (entry_rd->as.p.mbz != 1U) { + struct xtensa_mpu_entry *entry_wr; + + write_idx--; + entry_wr = &entries[write_idx]; + + *entry_wr = *entry_rd; + entry_wr->at.p.segment = write_idx; + } + + read_idx--; + } + + /* New first enabled entry is where the last written entry is. */ + new_first = write_idx; + + for (idx_0 = 0; idx_0 < new_first; idx_0++) { + struct xtensa_mpu_entry *e = &entries[idx_0]; + + /* Shortcut to zero out address and enabled bit. */ + e->as.raw = 0U; + + /* Segment value must correspond to the index. */ + e->at.p.segment = idx_0; + + /* No access at all for both kernel and user modes. */ + e->at.p.access_rights = XTENSA_MPU_ACCESS_P_NA_U_NA; + + /* Use default memory type for disabled entries. */ + e->at.p.memory_type = CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE; + } + } else { + /* No need to conlidate entries. Map is same as before. */ + new_first = first_enabled_idx; + } + + return new_first; +} + +/** + * Add a memory region to the MPU map. + * + * This adds a memory region to the MPU map, by setting the appropriate + * start and end entries. This may re-use existing entries or add new + * entries to the map. + * + * @param[in,out] map Pointer to MPU map. + * @param[in] start_addr Start address of the region. + * @param[in] end_addr End address of the region. + * @param[in] access_rights Access rights of this region. + * @param[in] memory_type Memory type of this region. + * @param[out] first_idx Return index of first enabled entry if not NULL. + * + * @retval 0 Successful in adding the region. + * @retval -EINVAL Invalid values in function arguments. + */ +static int mpu_map_region_add(struct xtensa_mpu_map *map, + uintptr_t start_addr, uintptr_t end_addr, + uint32_t access_rights, uint32_t memory_type, + uint8_t *first_idx) +{ + int ret; + bool exact_s, exact_e; + uint8_t idx_s, idx_e, first_enabled_idx; + struct xtensa_mpu_entry *entry_slot_s, *entry_slot_e, prev_entry; + + struct xtensa_mpu_entry *entries = map->entries; + + if (start_addr >= end_addr) { + ret = -EINVAL; + goto out; + } + + first_enabled_idx = find_first_enabled_entry(entries); + if (first_enabled_idx >= XTENSA_MPU_NUM_ENTRIES) { + + /* + * If the last entry in the map is not enabled and the start + * address is NULL, we can assume the map has not been populated + * at all. This is because we group all enabled entries at + * the end of map. + */ + struct xtensa_mpu_entry *last_entry = &entries[XTENSA_MPU_NUM_ENTRIES - 1]; + + if (!xtensa_mpu_entry_enable_get(last_entry) && + (xtensa_mpu_entry_start_address_get(last_entry) == 0U)) { + /* Empty table, so populate the entries as-is. */ + if (end_addr == 0xFFFFFFFFU) { + /* + * Region goes to end of memory, so only need to + * program one entry. + */ + entry_slot_s = &entries[XTENSA_MPU_NUM_ENTRIES - 1]; + + xtensa_mpu_entry_set(entry_slot_s, start_addr, true, + access_rights, memory_type); + } else { + /* + * Populate the last two entries to indicate + * a memory region. Notice that the second entry + * is not enabled as it is merely marking the end of + * a region and is not the starting of another + * enabled MPU region. + */ + entry_slot_s = &entries[XTENSA_MPU_NUM_ENTRIES - 2]; + entry_slot_e = &entries[XTENSA_MPU_NUM_ENTRIES - 1]; + + xtensa_mpu_entry_set(entry_slot_s, start_addr, true, + access_rights, memory_type); + xtensa_mpu_entry_set(entry_slot_e, end_addr, false, + XTENSA_MPU_ACCESS_P_NA_U_NA, + CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE); + } + + ret = 0; + goto out; + } + + first_enabled_idx = consolidate_entries(entries, first_enabled_idx); + + if (first_enabled_idx >= XTENSA_MPU_NUM_ENTRIES) { + ret = -EINVAL; + goto out; + } + } + + entry_slot_s = (struct xtensa_mpu_entry *) + check_addr_in_mpu_entries(entries, start_addr, first_enabled_idx, + &exact_s, &idx_s); + entry_slot_e = (struct xtensa_mpu_entry *) + check_addr_in_mpu_entries(entries, end_addr, first_enabled_idx, + &exact_e, &idx_e); + + __ASSERT_NO_MSG(entry_slot_s != NULL); + __ASSERT_NO_MSG(entry_slot_e != NULL); + __ASSERT_NO_MSG(start_addr < end_addr); + + if ((entry_slot_s == NULL) || (entry_slot_e == NULL)) { + ret = -EINVAL; + goto out; + } + + /* + * Figure out if we need to add new slots for either addresses. + * If the addresses match exactly the addresses current in map, + * we can reuse those entries without adding new one. + */ + if (!exact_s || !exact_e) { + uint8_t needed = (exact_s ? 0 : 1) + (exact_e ? 0 : 1); + + /* Check if there are enough empty slots. */ + if (first_enabled_idx < needed) { + ret = -ENOMEM; + goto out; + } + } + + /* + * Need to keep track of the attributes of the memory region before + * we start adding entries, as we will need to apply the same + * attributes to the "ending address" entry to preseve the attributes + * of existing map. + */ + prev_entry = *entry_slot_e; + + /* + * Entry for beginning of new region. + * + * - Use existing entry if start addresses are the same for existing + * and incoming region. We can simply reuse the entry. + * - Add an entry if incoming region is within existing region. + */ + if (!exact_s) { + /* + * Put a new entry before the first enabled entry. + * We will sort the entries later. + */ + first_enabled_idx--; + + entry_slot_s = &entries[first_enabled_idx]; + } + + xtensa_mpu_entry_set(entry_slot_s, start_addr, true, access_rights, memory_type); + + /* + * Entry for ending of region. + * + * - Add an entry if incoming region is within existing region. + * - If the end address matches exactly to existing entry, there is + * no need to do anything. + */ + if (!exact_e) { + /* + * Put a new entry before the first enabled entry. + * We will sort the entries later. + */ + first_enabled_idx--; + + entry_slot_e = &entries[first_enabled_idx]; + + /* + * Since we are going to punch a hole in the map, + * we need to preserve the attribute of existing region + * between the end address and next entry. + */ + *entry_slot_e = prev_entry; + xtensa_mpu_entry_start_address_set(entry_slot_e, end_addr); + } + + /* Sort the entries in ascending order of starting address */ + sort_entries(entries); + + /* + * Need to figure out where the start and end entries are as sorting + * may change their positions. + */ + entry_slot_s = (struct xtensa_mpu_entry *) + check_addr_in_mpu_entries(entries, start_addr, first_enabled_idx, + &exact_s, &idx_s); + entry_slot_e = (struct xtensa_mpu_entry *) + check_addr_in_mpu_entries(entries, end_addr, first_enabled_idx, + &exact_e, &idx_e); + + /* Both must be exact match. */ + __ASSERT_NO_MSG(exact_s); + __ASSERT_NO_MSG(exact_e); + + if (end_addr == 0xFFFFFFFFU) { + /* + * If end_addr = 0xFFFFFFFFU, entry_slot_e and idx_e both + * point to the last slot. Because the incoming region goes + * to the end of memory, we simply cheat by including + * the last entry by incrementing idx_e so the loop to + * update entries will change the attribute of last entry + * in map. + */ + idx_e++; + } + + /* + * Any existing entries between the "newly" popluated start and + * end entries must bear the same attributes. So modify them + * here. + */ + for (int idx = idx_s + 1; idx < idx_e; idx++) { + xtensa_mpu_entry_attributes_set(&entries[idx], access_rights, memory_type); + } + + if (first_idx != NULL) { + *first_idx = first_enabled_idx; + } + + ret = 0; + +out: + return ret; +} + +/** + * Write the MPU map to hardware. + * + * @param map Pointer to foreground MPU map. + */ +void xtensa_mpu_map_write(struct xtensa_mpu_map *map) +{ + int entry; + + /* + * Clear MPU entries first, then write MPU entries in reverse order. + * + * Remember that the boundary of each memory region is marked by + * two consecutive entries, and that the addresses of all entries + * must not be in descending order (i.e. equal or increasing). + * To ensure this, we clear out the entries first then write them + * in reverse order. This avoids any intermediate invalid + * configuration with regard to ordering. + */ + for (entry = 0; entry < XTENSA_MPU_NUM_ENTRIES; entry++) { + __asm__ volatile("wptlb %0, %1\n\t" : : "a"(entry), "a"(0)); + } + + for (entry = XTENSA_MPU_NUM_ENTRIES - 1; entry >= 0; entry--) { + __asm__ volatile("wptlb %0, %1\n\t" + : : "a"(map->entries[entry].at), "a"(map->entries[entry].as)); + } +} + +/** + * Perform necessary steps to enable MPU. + */ +void xtensa_mpu_init(void) +{ + unsigned int entry; + uint8_t first_enabled_idx; + + /* Disable all foreground segments before we start configuration. */ + xtensa_mpu_mpuenb_write(0); + + /* + * Clear the foreground MPU map so we can populate it later with valid entries. + * Note that we still need to make sure the map is valid, and cannot be totally + * zeroed. + */ + for (entry = 0; entry < XTENSA_MPU_NUM_ENTRIES; entry++) { + /* Make sure to zero out everything as a start, especially the MBZ fields. */ + struct xtensa_mpu_entry ent = {0}; + + /* Segment value must correspond to the index. */ + ent.at.p.segment = entry; + + /* No access at all for both kernel and user modes. */ + ent.at.p.access_rights = XTENSA_MPU_ACCESS_P_NA_U_NA; + + /* Use default memory type for disabled entries. */ + ent.at.p.memory_type = CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE; + + xtensa_mpu_map_fg_kernel.entries[entry] = ent; + } + + /* + * Add necessary MPU entries for the memory regions of base Zephyr image. + */ + for (entry = 0; entry < ARRAY_SIZE(mpu_zephyr_ranges); entry++) { + const struct xtensa_mpu_range *range = &mpu_zephyr_ranges[entry]; + + int ret = mpu_map_region_add(&xtensa_mpu_map_fg_kernel, + range->start, range->end, + range->access_rights, range->memory_type, + &first_enabled_idx); + + ARG_UNUSED(ret); + __ASSERT(ret == 0, "Unable to add region [0x%08x, 0x%08x): %d", + (unsigned int)range->start, + (unsigned int)range->end, + ret); + } + + /* + * Now for the entries for memory regions needed by SoC. + */ + for (entry = 0; entry < xtensa_soc_mpu_ranges_num; entry++) { + const struct xtensa_mpu_range *range = &xtensa_soc_mpu_ranges[entry]; + + int ret = mpu_map_region_add(&xtensa_mpu_map_fg_kernel, + range->start, range->end, + range->access_rights, range->memory_type, + &first_enabled_idx); + + ARG_UNUSED(ret); + __ASSERT(ret == 0, "Unable to add region [0x%08x, 0x%08x): %d", + (unsigned int)range->start, + (unsigned int)range->end, + ret); + } + + /* Consolidate entries so we have a compact map at boot. */ + consolidate_entries(xtensa_mpu_map_fg_kernel.entries, first_enabled_idx); + + /* Write the map into hardware. There is no turning back now. */ + xtensa_mpu_map_write(&xtensa_mpu_map_fg_kernel); +} diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h index f303a8a0c3a..8dfa53f7a7e 100644 --- a/arch/xtensa/include/kernel_arch_func.h +++ b/arch/xtensa/include/kernel_arch_func.h @@ -72,6 +72,10 @@ static ALWAYS_INLINE void arch_kernel_init(void) #ifdef CONFIG_XTENSA_MMU xtensa_mmu_init(); #endif + +#ifdef CONFIG_XTENSA_MPU + xtensa_mpu_init(); +#endif } void xtensa_switch(void *switch_to, void **switched_from); diff --git a/arch/xtensa/include/xtensa_mpu_priv.h b/arch/xtensa/include/xtensa_mpu_priv.h new file mode 100644 index 00000000000..86a6462d06b --- /dev/null +++ b/arch/xtensa/include/xtensa_mpu_priv.h @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_ARCH_XTENSA_XTENSA_MPU_PRIV_H_ +#define ZEPHYR_ARCH_XTENSA_XTENSA_MPU_PRIV_H_ + +#include + +#include +#include +#include + +#include + +/** + * @defgroup xtensa_mpu_internal_apis Xtensa Memory Protection Unit (MPU) Internal APIs + * @ingroup xtensa_mpu_apis + * @{ + */ + +/** + * @name Bit shifts and masks for MPU entry registers. + * + * @{ + */ + +/** + * Number of bits to shift for start address in MPU entry register. + * + * This is only used for aligning the value to the MPU entry register, + * and is different than the hardware alignment requirement. + */ +#define XTENSA_MPU_ENTRY_REG_START_ADDR_SHIFT 5U + +/** + * Bit mask of start address in MPU entry register. + * + * This is only used for aligning the value to the MPU entry register, + * and is different than the hardware alignment requirement. + */ +#define XTENSA_MPU_ENTRY_REG_START_ADDR_MASK 0xFFFFFFE0U + +/** Number of bits to shift for enable bit in MPU entry register. */ +#define XTENSA_MPU_ENTRY_REG_ENABLE_SHIFT 0U + +/** Bit mask of enable bit in MPU entry register. */ +#define XTENSA_MPU_ENTRY_REG_ENABLE_MASK BIT(XTENSA_MPU_ENTRY_ENABLE_SHIFT) + +/** Number of bits to shift for lock bit in MPU entry register. */ +#define XTENSA_MPU_ENTRY_REG_LOCK_SHIFT 1U + +/** Bit mask of lock bit in MPU entry register. */ +#define XTENSA_MPU_ENTRY_REG_LOCK_MASK BIT(XTENSA_MPU_ENTRY_LOCK_SHIFT) + +/** Number of bits to shift for access rights in MPU entry register. */ +#define XTENSA_MPU_ENTRY_REG_ACCESS_RIGHTS_SHIFT 8U + +/** Bit mask of access rights in MPU entry register. */ +#define XTENSA_MPU_ENTRY_REG_ACCESS_RIGHTS_MASK \ + (0xFU << XTENSA_MPU_ENTRY_REG_ACCESS_RIGHTS_SHIFT) + +/** Number of bits to shift for memory type in MPU entry register. */ +#define XTENSA_MPU_ENTRY_REG_MEMORY_TYPE_SHIFT 12U + +/** Bit mask of memory type in MPU entry register. */ +#define XTENSA_MPU_ENTRY_REG_MEMORY_TYPE_MASK \ + (0x1FFU << XTENSA_MPU_ENTRY_REG_MEMORY_TYPE_SHIFT) + +/** + * @} + */ + +/** + * Define one MPU entry of type struct xtensa_mpu_entry. + * + * @note This needs a comma at the end if used in array declaration. + * + * @param saddr Start address. + * @param en Enable bit + * @param rights Access rights. + * @param memtype Memory type. + */ +#define XTENSA_MPU_ENTRY(saddr, en, rights, memtype) \ + { \ + .as.p.enable = en, \ + .as.p.lock = 0, \ + .as.p.mbz = 0, \ + .as.p.start_addr = (saddr >> XTENSA_MPU_ENTRY_START_ADDR_SHIFT), \ + .at.p.segment = 0, \ + .at.p.mbz1 = 0, \ + .at.p.access_rights = rights, \ + .at.p.memory_type = memtype, \ + .at.p.mbz2 = 0, \ + } + +/** + * @brief Read MPUCFG register. + * + * This returns the bitmask of enabled MPU entries (foreground segments). + * + * @return Value of MPUCFG register. + */ +static ALWAYS_INLINE uint32_t xtensa_mpu_mpucfg_read(void) +{ + uint32_t mpucfg; + + __asm__ __volatile__("rsr.mpucfg %0" : "=a" (mpucfg)); + + return mpucfg; +} + +/** + * @brief Read MPUENB register. + * + * This returns the enable bits for MPU entries. + * + * @return Value of MPUENB register. + */ +static ALWAYS_INLINE uint32_t xtensa_mpu_mpuenb_read(void) +{ + uint32_t mpuenb; + + __asm__ __volatile__("rsr.mpuenb %0" : "=a" (mpuenb)); + + return mpuenb; +} + +/** + * @brief Write MPUENB register. + * + * This writes the enable bits for MPU entries. + * + * @param mpuenb Value to be written. + */ +static ALWAYS_INLINE void xtensa_mpu_mpuenb_write(uint32_t mpuenb) +{ + __asm__ __volatile__("wsr.mpuenb %0" : : "a"(mpuenb)); +} + +/** + * @name MPU entry internal helper functions. + * + * @{ + */ + +/** + * @brief Return the start address encoded in the MPU entry. + * + * @param entry Pointer to the MPU entry. + * + * @return Start address. + */ +static ALWAYS_INLINE +uintptr_t xtensa_mpu_entry_start_address_get(const struct xtensa_mpu_entry *entry) +{ + return (entry->as.p.start_addr << XTENSA_MPU_ENTRY_REG_START_ADDR_SHIFT); +} + +/** + * @brief Set the start address encoded in the MPU entry. + * + * @param entry Pointer to the MPU entry. + * @param addr Start address. + */ +static ALWAYS_INLINE +void xtensa_mpu_entry_start_address_set(struct xtensa_mpu_entry *entry, uintptr_t addr) +{ + entry->as.p.start_addr = addr >> XTENSA_MPU_ENTRY_REG_START_ADDR_SHIFT; +} + +/** + * @brief Return the lock bit encoded in the MPU entry. + * + * @param entry Pointer to the MPU entry. + * + * @retval True Lock bit is set. + * @retval False Lock bit is not set. + */ +static ALWAYS_INLINE +bool xtensa_mpu_entry_lock_get(const struct xtensa_mpu_entry *entry) +{ + return entry->as.p.lock != 0; +} + +/** + * @brief Set the lock bit encoded in the MPU entry. + * + * @param entry Pointer to the MPU entry. + * @param lock True if to lock the MPU entry. + */ +static ALWAYS_INLINE +void xtensa_mpu_entry_lock_set(struct xtensa_mpu_entry *entry, bool lock) +{ + entry->as.p.lock = lock ? 1 : 0; +} + +/** + * @brief Return the enable bit encoded in the MPU entry. + * + * @param entry Pointer to the MPU entry. + * + * @retval True Enable bit is set. + * @retval False Enable bit is not set. + */ +static ALWAYS_INLINE +bool xtensa_mpu_entry_enable_get(const struct xtensa_mpu_entry *entry) +{ + return entry->as.p.enable != 0; +} + +/** + * @brief Set the enable bit encoded in the MPU entry. + * + * @param entry Pointer to the MPU entry. + * @param en True if to enable the MPU entry. + */ +static ALWAYS_INLINE +void xtensa_mpu_entry_enable_set(struct xtensa_mpu_entry *entry, bool en) +{ + entry->as.p.enable = en ? 1 : 0; +} + +/** + * @brief Return the access rights encoded in the MPU entry. + * + * @param entry Pointer to the MPU entry. + * + * @return Access right value. + */ +static ALWAYS_INLINE +uint8_t xtensa_mpu_entry_access_rights_get(const struct xtensa_mpu_entry *entry) +{ + return entry->at.p.access_rights; +} + +/** + * @brief Set the lock bit encoded in the MPU entry. + * + * @param entry Pointer to the MPU entry. + * @param access_rights Access rights to be set. + */ +static ALWAYS_INLINE +void xtensa_mpu_entry_access_rights_set(struct xtensa_mpu_entry *entry, uint8_t access_rights) +{ + entry->at.p.access_rights = access_rights; +} + +/** + * @brief Return the memory type encoded in the MPU entry. + * + * @param entry Pointer to the MPU entry. + * + * @return Memory type value. + */ +static ALWAYS_INLINE +uint16_t xtensa_mpu_entry_memory_type_get(const struct xtensa_mpu_entry *entry) +{ + return entry->at.p.memory_type; +} + +/** + * @brief Set the memory type in the MPU entry. + * + * @param entry Pointer to the MPU entry. + * @param memory_type Memory type to be set. + */ +static ALWAYS_INLINE +void xtensa_mpu_entry_memory_type_set(struct xtensa_mpu_entry *entry, uint16_t memory_type) +{ + entry->at.p.memory_type = memory_type; +} + +/** + * @brief Set both access rights and memory type of a MPU entry. + * + * @param entry Pointer to the MPU entry. + * @param access_rights Access rights value. + * @param memory_type Memory type value. + */ +static inline +void xtensa_mpu_entry_attributes_set(struct xtensa_mpu_entry *entry, + uint8_t access_rights, uint16_t memory_type) +{ + xtensa_mpu_entry_access_rights_set(entry, access_rights); + xtensa_mpu_entry_memory_type_set(entry, memory_type); +} + +/** + * @brief Set fields in MPU entry so it will be functional. + * + * This sets the starting address, enable bit, access rights and memory type + * of an entry. + * + * Note that this preserves the valud of the segment field. + * + * @param entry Pointer to the entry to be manipulated. + * @param start_address Start address to be set. + * @param enable Whether this entry should be enabled. + * @param access_rights Access rights for the entry. + * @param memory_type Memory type for the entry. + */ +static inline +void xtensa_mpu_entry_set(struct xtensa_mpu_entry *entry, uintptr_t start_address, + bool enable, uint8_t access_rights, uint16_t memory_type) +{ + uint8_t segment = entry->at.p.segment; + + /* Clear out the fields, and make sure MBZ fields are zero. */ + entry->as.raw = 0; + entry->at.raw = 0; + + xtensa_mpu_entry_start_address_set(entry, start_address); + xtensa_mpu_entry_enable_set(entry, enable); + xtensa_mpu_entry_access_rights_set(entry, access_rights); + xtensa_mpu_entry_memory_type_set(entry, memory_type); + + entry->at.p.segment = segment; +} + +/** + * @brief Test if two MPU entries have same access rights. + * + * @param entry1 MPU entry #1 + * @param entry2 MPU entry #2. + * + * @return True if access rights are the same, false otherwise. + */ +static inline +bool xtensa_mpu_entries_has_same_access_rights(const struct xtensa_mpu_entry *entry1, + const struct xtensa_mpu_entry *entry2) +{ + return entry1->at.p.access_rights == entry2->at.p.access_rights; +} + +/** + * @brief Test if two MPU entries have same memory types. + * + * @param entry1 MPU entry #1. + * @param entry2 MPU entry #2. + * + * @return True if memory types are the same, false otherwise. + */ +static inline +bool xtensa_mpu_entries_has_same_memory_type(const struct xtensa_mpu_entry *entry1, + const struct xtensa_mpu_entry *entry2) +{ + return entry1->at.p.memory_type == entry2->at.p.memory_type; +} + +/** + * @brief Test if two MPU entries have same access rights and memory types. + * + * @param entry1 MPU entry #1. + * @param entry2 MPU entry #2. + * + * @return True if access rights and memory types are the same, false otherwise. + */ +static inline +bool xtensa_mpu_entries_has_same_attributes(const struct xtensa_mpu_entry *entry1, + const struct xtensa_mpu_entry *entry2) +{ + return xtensa_mpu_entries_has_same_access_rights(entry1, entry2) && + xtensa_mpu_entries_has_same_memory_type(entry1, entry2); +} + +/** + * @brief Test if two entries has the same addresses. + * + * @param entry1 MPU entry #1. + * @param entry2 MPU entry #2. + * + * @return True if they have the same address, false otherwise. + */ +static inline +bool xtensa_mpu_entries_has_same_address(const struct xtensa_mpu_entry *entry1, + const struct xtensa_mpu_entry *entry2) +{ + return xtensa_mpu_entry_start_address_get(entry1) + == xtensa_mpu_entry_start_address_get(entry2); +} + +/** + * @} + */ + +/** + * @name MPU access rights helper functions. + * + * @{ + */ + +/** + * @brief Test if the access rights is valid. + * + * @param access_rights Access rights value. + * + * @return True if access rights is valid, false otherwise. + */ +static ALWAYS_INLINE bool xtensa_mpu_access_rights_is_valid(uint8_t access_rights) +{ + return (access_rights != 1) && (access_rights <= 15); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ZEPHYR_ARCH_XTENSA_XTENSA_MPU_PRIV_H_ */ diff --git a/include/zephyr/arch/xtensa/arch.h b/include/zephyr/arch/xtensa/arch.h index f3358cafe2f..9c8ab6a2091 100644 --- a/include/zephyr/arch/xtensa/arch.h +++ b/include/zephyr/arch/xtensa/arch.h @@ -35,7 +35,13 @@ #include +#ifdef CONFIG_XTENSA_MMU #include +#endif + +#ifdef CONFIG_XTENSA_MPU +#include +#endif /** * @defgroup xtensa_apis Xtensa APIs diff --git a/include/zephyr/arch/xtensa/mpu.h b/include/zephyr/arch/xtensa/mpu.h new file mode 100644 index 00000000000..0ccda6dfd42 --- /dev/null +++ b/include/zephyr/arch/xtensa/mpu.h @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include + +#include + +#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MPU_H +#define ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MPU_H + +/** + * @defgroup xtensa_mpu_apis Xtensa Memory Protection Unit (MPU) APIs + * @ingroup xtensa_apis + * @{ + */ + +/** Number of available entries in the MPU table. */ +#define XTENSA_MPU_NUM_ENTRIES XCHAL_MPU_ENTRIES + +/** + * @name MPU memory region access rights. + * + * @note These are NOT bit masks, and must be used as whole value. + * + * @{ + */ + +/** Kernel and user modes no access. */ +#define XTENSA_MPU_ACCESS_P_NA_U_NA (0) + +/** Kernel mode execution only. */ +#define XTENSA_MPU_ACCESS_P_X_U_NA (2) + +/** User mode execution only. */ +#define XTENSA_MPU_ACCESS_P_NA_U_X (3) + +/** Kernel mode read only. */ +#define XTENSA_MPU_ACCESS_P_RO_U_NA (4) + +/** Kernel mode read and execution. */ +#define XTENSA_MPU_ACCESS_P_RX_U_NA (5) + +/** Kernel mode read and write. */ +#define XTENSA_MPU_ACCESS_P_RW_U_NA (6) + +/** Kernel mode read, write and execution. */ +#define XTENSA_MPU_ACCESS_P_RWX_U_NA (7) + +/** Kernel and user modes write only. */ +#define XTENSA_MPU_ACCESS_P_WO_U_WO (8) + +/** Kernel mode read, write. User mode read, write and execution. */ +#define XTENSA_MPU_ACCESS_P_RW_U_RWX (9) + +/** Kernel mode read and write. User mode read only. */ +#define XTENSA_MPU_ACCESS_P_RW_U_RO (10) + +/** Kernel mode read, write and execution. User mode read and execution. */ +#define XTENSA_MPU_ACCESS_P_RWX_U_RX (11) + +/** Kernel and user modes read only. */ +#define XTENSA_MPU_ACCESS_P_RO_U_RO (12) + +/** Kernel and user modes read and execution. */ +#define XTENSA_MPU_ACCESS_P_RX_U_RX (13) + +/** Kernel and user modes read and write. */ +#define XTENSA_MPU_ACCESS_P_RW_U_RW (14) + +/** Kernel and user modes read, write and execution. */ +#define XTENSA_MPU_ACCESS_P_RWX_U_RWX (15) + +/** + * @} + */ + +/** + * @brief Foreground MPU Entry. + * + * This holds the as, at register values for one MPU entry which can be + * used directly by WPTLB. + */ +struct xtensa_mpu_entry { + /** + * Content of as register for WPTLB. + * + * This contains the start address, the enable bit, and the lock bit. + */ + union { + /** Raw value. */ + uint32_t raw; + + /** Individual parts. */ + struct { + /** + * Enable bit for this entry. + * + * Modifying this will also modify the corresponding bit of + * the MPUENB register. + */ + uint32_t enable:1; + + /** + * Lock bit for this entry. + * + * Usable only if MPULOCKABLE parameter is enabled in + * processor configuration. + * + * Once set: + * - This cannot be cleared until reset. + * - This entry can no longer be modified. + * - The start address of the next entry also + * cannot be modified. + */ + uint32_t lock:1; + + /** Must be zero. */ + uint32_t mbz:3; + + /** + * Start address of this MPU entry. + * + * Effective bits in this portion are affected by the minimum + * segment size of each MPU entry, ranging from 32 bytes to 4GB. + */ + uint32_t start_addr:27; + } p; + } as; + + /** + * Content of at register for WPTLB. + * + * This contains the memory type, access rights, and the segment number. + */ + union { + /** Raw value. */ + uint32_t raw; + + /** Individual parts. */ + struct { + /** The segment number of this MPU entry. */ + uint32_t segment:5; + + /** Must be zero (part 1). */ + uint32_t mbz1:3; + + /** + * Access rights associated with this MPU entry. + * + * This dictates the access right from the start address of + * this entry, to the start address of next entry. + * + * Refer to XTENSA_MPU_ACCESS_* macros for available rights. + */ + uint32_t access_rights:4; + + /** + * Memory type associated with this MPU entry. + * + * This dictates the memory type from the start address of + * this entry, to the start address of next entry. + * + * This affects how the hardware treats the memory, for example, + * cacheable vs non-cacheable, shareable vs non-shareable. + * Refer to the Xtensa Instruction Set Architecture (ISA) manual + * for general description, and the processor manual for processor + * specific information. + */ + uint32_t memory_type:9; + + /** Must be zero (part 2). */ + uint32_t mbz2:11; + } p; + } at; +}; + +/** + * @brief Struct to hold foreground MPU map and its entries. + */ +struct xtensa_mpu_map { + /** + * Array of MPU entries. + */ + struct xtensa_mpu_entry entries[XTENSA_MPU_NUM_ENTRIES]; +}; + +/** + * Struct to describe a memory region [start, end). + */ +struct xtensa_mpu_range { + /** Start address (inclusive) of the memory region. */ + const uintptr_t start; + + /** + * End address (exclusive) of the memory region. + * + * Use 0xFFFFFFFF for the end of memory. + */ + const uintptr_t end; + + /** Access rights for the memory region. */ + const uint8_t access_rights:4; + + /** + * Memory type for the region. + * + * Refer to the Xtensa Instruction Set Architecture (ISA) manual + * for general description, and the processor manual for processor + * specific information. + */ + const uint16_t memory_type:9; +} __packed; + +/** + * @brief Additional memory regions required by SoC. + * + * These memory regions will be setup by MPU initialization code at boot. + * + * Must be defined in the SoC layer. + */ +extern const struct xtensa_mpu_range xtensa_soc_mpu_ranges[]; + +/** + * @brief Number of SoC additional memory regions. + * + * Must be defined in the SoC layer. + */ +extern const int xtensa_soc_mpu_ranges_num; + +/** + * @brief Initialize hardware MPU. + * + * This initializes the MPU hardware and setup the memory regions at boot. + */ +void xtensa_mpu_init(void); + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MPU_H */ From 2fc55f39383e32e8cbbaaac0ea37fd4f3254e971 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 26 Jan 2024 14:15:14 -0800 Subject: [PATCH 0966/2402] tests: kernel/mem_protect/userspace: support for Xtensa MPU Add support to test for Xtensa MPU. Signed-off-by: Daniel Leung --- tests/kernel/mem_protect/userspace/src/main.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/tests/kernel/mem_protect/userspace/src/main.c b/tests/kernel/mem_protect/userspace/src/main.c index 5a544940633..81a039d040a 100644 --- a/tests/kernel/mem_protect/userspace/src/main.c +++ b/tests/kernel/mem_protect/userspace/src/main.c @@ -22,8 +22,13 @@ #if defined(CONFIG_XTENSA) #include +#if defined(CONFIG_XTENSA_MMU) #include #endif +#if defined(CONFIG_XTENSA_MPU) +#include +#endif +#endif #if defined(CONFIG_ARC) #include @@ -259,6 +264,7 @@ ZTEST_USER(userspace, test_disable_mmu_mpu) #elif defined(CONFIG_XTENSA) set_fault(K_ERR_CPU_EXCEPTION); +#if defined(CONFIG_XTENSA_MMU) /* Reset way 6 to do identity mapping. * Complier would complain addr going out of range if we * simply do addr = i * 0x20000000 inside the loop. So @@ -274,6 +280,20 @@ ZTEST_USER(userspace, test_disable_mmu_mpu) addr += 0x20000000; } +#endif + +#if defined(CONFIG_XTENSA_MPU) + /* Technically, simply clearing out all foreground MPU entries + * allows the background map to take over, so it is not exactly + * disabling MPU. However, this test is about catching userspace + * trying to manipulate the MPU regions. So as long as there is + * kernel OOPS, we would be fine. + */ + for (int i = 0; i < XTENSA_MPU_NUM_ENTRIES; i++) { + __asm__ volatile("wptlb %0, %1\n\t" : : "a"(i), "a"(0)); + } +#endif + #else #error "Not implemented for this architecture" #endif From aa09b41f29a9e44263f427038cb0f1431164e9d2 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 30 Jan 2024 11:15:40 -0800 Subject: [PATCH 0967/2402] tests: kernel/userspace: skip other thread tests if needed With memory domain enabled, all threads within the same domain have access to each other threads' stacks, especially with CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API enabled (as it is expected behavior). So update the conditions to skip both tests to read and write to other threads' stacks. Signed-off-by: Daniel Leung --- tests/kernel/mem_protect/userspace/src/main.c | 20 +++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/tests/kernel/mem_protect/userspace/src/main.c b/tests/kernel/mem_protect/userspace/src/main.c index 81a039d040a..edf5e8cd687 100644 --- a/tests/kernel/mem_protect/userspace/src/main.c +++ b/tests/kernel/mem_protect/userspace/src/main.c @@ -553,8 +553,16 @@ ZTEST_USER(userspace, test_read_other_stack) /* Try to read from another thread's stack. */ unsigned int val; -#ifdef CONFIG_MMU +#if defined(CONFIG_MMU) || defined(CONFIG_MPU) +#if defined(CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API) + /* With memory domain enabled, all threads within the same domain + * have access to each other threads' stacks, especially with + * CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API=y (as it is expected + * behavior). The access would not fault which the test expects. + * So skip this test. + */ ztest_test_skip(); +#endif #endif k_thread_create(&test_thread, test_stack, STACKSIZE, uthread_read_body, &val, NULL, NULL, @@ -575,8 +583,16 @@ ZTEST_USER(userspace, test_write_other_stack) /* Try to write to another thread's stack. */ unsigned int val; -#ifdef CONFIG_MMU +#if defined(CONFIG_MMU) || defined(CONFIG_MPU) +#if defined(CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API) + /* With memory domain enabled, all threads within the same domain + * have access to each other threads' stacks, especially with + * CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API=y (as it is expected + * behavior). The access would not fault which the test expects. + * So skip this test. + */ ztest_test_skip(); +#endif #endif k_thread_create(&test_thread, test_stack, STACKSIZE, uthread_write_body, &val, NULL, NULL, From 57d591700bd408bd203ca717248e9cac3a59add9 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 30 Jan 2024 14:33:42 -0800 Subject: [PATCH 0968/2402] xtensa: mpu: enable userspace support This extends the Xtensa MPU to support userspace. Signed-off-by: Daniel Leung --- arch/xtensa/Kconfig | 9 +- arch/xtensa/core/mpu.c | 358 ++++++++++++++++++++++ arch/xtensa/core/offsets/offsets.c | 5 + arch/xtensa/core/userspace.S | 12 + arch/xtensa/core/vector_handlers.c | 4 +- arch/xtensa/core/xtensa_asm2_util.S | 9 +- arch/xtensa/include/xtensa_asm2_s.h | 5 + arch/xtensa/include/xtensa_mpu_priv.h | 32 ++ include/zephyr/arch/xtensa/arch.h | 3 + include/zephyr/arch/xtensa/mpu.h | 79 +++++ include/zephyr/arch/xtensa/thread.h | 12 + include/zephyr/arch/xtensa/thread_stack.h | 15 +- 12 files changed, 535 insertions(+), 8 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 6ed703b2521..4d813498d98 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -221,6 +221,8 @@ menuconfig XTENSA_MPU select MPU select SRAM_REGION_PERMISSIONS select XTENSA_SMALL_VECTOR_TABLE_ENTRY + select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE + select CURRENT_THREAD_USE_NO_TLS if USERSPACE select EXPERIMENTAL # TODO: the target the MPU code developed on (basically sample_controller # plus MPU minus s32c1i) does not have cache or SMP capability. @@ -238,6 +240,9 @@ config XTENSA_MPU_DEFAULT_MEM_TYPE Default memory type for memory regions: non-cacheable memory, non-shareable, non-bufferable and interruptible. + If userspace is enabled, it will be used to restore the memory type of + the region being removed from a memory domain. + endif # XTENSA_MPU endif # CPU_HAS_MPU @@ -245,7 +250,7 @@ endif # CPU_HAS_MPU config XTENSA_SYSCALL_USE_HELPER bool "Use userspace syscall helper" default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xt-clang" - depends on XTENSA_MMU && USERSPACE + depends on (XTENSA_MMU || XTENSA_MPU) && USERSPACE help Use syscall helpers for passing more then 3 arguments. This is a workaround for toolchains where they have @@ -254,6 +259,6 @@ config XTENSA_SYSCALL_USE_HELPER config XTENSA_INSECURE_USERSPACE bool default y - depends on XTENSA_MMU && USERSPACE + depends on (XTENSA_MMU || XTENSA_MPU) && USERSPACE endmenu diff --git a/arch/xtensa/core/mpu.c b/arch/xtensa/core/mpu.c index d34aeee892b..4efcf33d4b4 100644 --- a/arch/xtensa/core/mpu.c +++ b/arch/xtensa/core/mpu.c @@ -6,6 +6,7 @@ #include #include +#include #include #include @@ -21,6 +22,11 @@ #include #include +#ifdef CONFIG_USERSPACE +BUILD_ASSERT((CONFIG_PRIVILEGED_STACK_SIZE > 0) && + (CONFIG_PRIVILEGED_STACK_SIZE % XCHAL_MPU_ALIGN) == 0); +#endif + extern char _heap_end[]; extern char _heap_start[]; @@ -602,10 +608,25 @@ static int mpu_map_region_add(struct xtensa_mpu_map *map, * * @param map Pointer to foreground MPU map. */ +#ifdef CONFIG_USERSPACE +/* With userspace enabled, the pointer to per memory domain MPU map is stashed + * inside the thread struct. If we still only take struct xtensa_mpu_map as + * argument, a wrapper function is needed. To avoid the cost associated with + * calling that wrapper function, takes thread pointer directly as argument + * when userspace is enabled. Not to mention that writing the map to hardware + * is already a costly operation per context switch. So every little bit helps. + */ +void xtensa_mpu_map_write(struct k_thread *thread) +#else void xtensa_mpu_map_write(struct xtensa_mpu_map *map) +#endif { int entry; +#ifdef CONFIG_USERSPACE + struct xtensa_mpu_map *map = thread->arch.mpu_map; +#endif + /* * Clear MPU entries first, then write MPU entries in reverse order. * @@ -698,5 +719,342 @@ void xtensa_mpu_init(void) consolidate_entries(xtensa_mpu_map_fg_kernel.entries, first_enabled_idx); /* Write the map into hardware. There is no turning back now. */ +#ifdef CONFIG_USERSPACE + struct k_thread dummy_map_thread; + + dummy_map_thread.arch.mpu_map = &xtensa_mpu_map_fg_kernel; + xtensa_mpu_map_write(&dummy_map_thread); +#else xtensa_mpu_map_write(&xtensa_mpu_map_fg_kernel); +#endif +} + +#ifdef CONFIG_USERSPACE +int arch_mem_domain_init(struct k_mem_domain *domain) +{ + domain->arch.mpu_map = xtensa_mpu_map_fg_kernel; + + return 0; +} + +int arch_mem_domain_max_partitions_get(void) +{ + /* + * Due to each memory region requiring 2 MPU entries to describe, + * it is hard to figure out how many partitions are available. + * For example, if all those partitions are contiguous, it only + * needs 2 entries (1 if the end of region already has an entry). + * If they are all disjoint, it will need (2 * n) entries to + * describe all of them. So just use CONFIG_MAX_DOMAIN_PARTITIONS + * here and let the application set this instead. + */ + return CONFIG_MAX_DOMAIN_PARTITIONS; +} + +int arch_mem_domain_partition_remove(struct k_mem_domain *domain, + uint32_t partition_id) +{ + int ret; + uint32_t perm; + struct xtensa_mpu_map *map = &domain->arch.mpu_map; + struct k_mem_partition *partition = &domain->partitions[partition_id]; + uintptr_t end_addr = partition->start + partition->size; + + if (end_addr <= partition->start) { + ret = -EINVAL; + goto out; + } + + /* + * This is simply to get rid of the user permissions and retain + * whatever the kernel permissions are. So that we won't be + * setting the memory region permission incorrectly, for example, + * marking read only region writable. + * + * Note that Zephyr does not do RWX partitions so we can treat it + * as invalid. + */ + switch (partition->attr) { + case XTENSA_MPU_ACCESS_P_RO_U_NA: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RX_U_NA: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RO_U_RO: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RX_U_RX: + perm = XTENSA_MPU_ACCESS_P_RO_U_NA; + break; + + case XTENSA_MPU_ACCESS_P_RW_U_NA: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_NA: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RWX: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RO: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_RX: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RW: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_RWX: + perm = XTENSA_MPU_ACCESS_P_RW_U_NA; + break; + + default: + /* _P_X_U_NA is not a valid permission for userspace, so ignore. + * _P_NA_U_X becomes _P_NA_U_NA when removing user permissions. + * _P_WO_U_WO has not kernel only counterpart so just force no access. + * If we get here with _P_NA_P_NA, there is something seriously + * wrong with the userspace and/or application code. + */ + perm = XTENSA_MPU_ACCESS_P_NA_U_NA; + break; + } + + /* + * Reset the memory region attributes by simply "adding" + * a region with default attributes. If entries already + * exist for the region, the corresponding entries will + * be updated with the default attributes. Or new entries + * will be added to carve a hole in existing regions. + */ + ret = mpu_map_region_add(map, partition->start, end_addr, + perm, + CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, + NULL); + +out: + return ret; +} + +int arch_mem_domain_partition_add(struct k_mem_domain *domain, + uint32_t partition_id) +{ + int ret; + struct xtensa_mpu_map *map = &domain->arch.mpu_map; + struct k_mem_partition *partition = &domain->partitions[partition_id]; + uintptr_t end_addr = partition->start + partition->size; + + if (end_addr <= partition->start) { + ret = -EINVAL; + goto out; + } + + ret = mpu_map_region_add(map, partition->start, end_addr, + (uint8_t)partition->attr, + CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, + NULL); + +out: + return ret; +} + +int arch_mem_domain_thread_add(struct k_thread *thread) +{ + int ret = 0; + + /* New memory domain we are being added to */ + struct k_mem_domain *domain = thread->mem_domain_info.mem_domain; + + /* + * this is only set for threads that were migrating from some other + * memory domain; new threads this is NULL. + */ + struct xtensa_mpu_map *old_map = thread->arch.mpu_map; + + bool is_user = (thread->base.user_options & K_USER) != 0; + bool is_migration = (old_map != NULL) && is_user; + + uintptr_t stack_end_addr = thread->stack_info.start + thread->stack_info.size; + + if (stack_end_addr < thread->stack_info.start) { + /* Account for wrapping around back to 0. */ + stack_end_addr = 0xFFFFFFFFU; + } + + /* + * Allow USER access to the thread's stack in its new domain if + * we are migrating. If we are not migrating this is done in + * xtensa_user_stack_perms(). + */ + if (is_migration) { + /* Add stack to new domain's MPU map. */ + ret = mpu_map_region_add(&domain->arch.mpu_map, + thread->stack_info.start, stack_end_addr, + XTENSA_MPU_ACCESS_P_RW_U_RW, + CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, + NULL); + + /* Probably this fails due to no more available slots in MPU map. */ + __ASSERT_NO_MSG(ret == 0); + } + + thread->arch.mpu_map = &domain->arch.mpu_map; + + /* + * Remove thread stack from old memory domain if we are + * migrating away from old memory domain. This is done + * by simply remove USER access from the region. + */ + if (is_migration) { + /* + * Remove stack from old MPU map by... + * "adding" a new memory region to the map + * as this carves a hole in the existing map. + */ + ret = mpu_map_region_add(old_map, + thread->stack_info.start, stack_end_addr, + XTENSA_MPU_ACCESS_P_RW_U_NA, + CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, + NULL); + } + + /* + * Need to switch to new MPU map if this is the current + * running thread. + */ + if (thread == _current_cpu->current) { + xtensa_mpu_map_write(thread); + } + + return ret; +} + +int arch_mem_domain_thread_remove(struct k_thread *thread) +{ + uintptr_t stack_end_addr; + int ret; + + struct k_mem_domain *domain = thread->mem_domain_info.mem_domain; + + if ((thread->base.user_options & K_USER) == 0) { + ret = 0; + goto out; + } + + if ((thread->base.thread_state & _THREAD_DEAD) == 0) { + /* Thread is migrating to another memory domain and not + * exiting for good; we weren't called from + * z_thread_abort(). Resetting the stack region will + * take place in the forthcoming thread_add() call. + */ + ret = 0; + goto out; + } + + stack_end_addr = thread->stack_info.start + thread->stack_info.size; + if (stack_end_addr < thread->stack_info.start) { + /* Account for wrapping around back to 0. */ + stack_end_addr = 0xFFFFFFFFU; + } + + /* + * Restore permissions on the thread's stack area since it is no + * longer a member of the domain. + */ + ret = mpu_map_region_add(&domain->arch.mpu_map, + thread->stack_info.start, stack_end_addr, + XTENSA_MPU_ACCESS_P_RW_U_NA, + CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, + NULL); + + xtensa_mpu_map_write(thread); + +out: + return ret; +} + +int arch_buffer_validate(void *addr, size_t size, int write) +{ + uintptr_t aligned_addr; + size_t aligned_size, addr_offset; + int ret = 0; + + /* addr/size arbitrary, fix this up into an aligned region */ + aligned_addr = ROUND_DOWN((uintptr_t)addr, XCHAL_MPU_ALIGN); + addr_offset = (uintptr_t)addr - aligned_addr; + aligned_size = ROUND_UP(size + addr_offset, XCHAL_MPU_ALIGN); + + for (size_t offset = 0; offset < aligned_size; + offset += XCHAL_MPU_ALIGN) { + uint32_t probed = xtensa_pptlb_probe(aligned_addr + offset); + + uint8_t access_rights = (probed & XTENSA_MPU_PPTLB_ACCESS_RIGHTS_MASK) + >> XTENSA_MPU_PPTLB_ACCESS_RIGHTS_SHIFT; + + if (write) { + /* Need to check write permission. */ + switch (access_rights) { + case XTENSA_MPU_ACCESS_P_WO_U_WO: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RWX: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RW: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_RWX: + /* These permissions are okay. */ + break; + default: + ret = -EPERM; + goto out; + } + } else { + /* Only check read permission. */ + switch (access_rights) { + case XTENSA_MPU_ACCESS_P_RW_U_RWX: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RO: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_RX: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RO_U_RO: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RX_U_RX: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RW_U_RW: + __fallthrough; + case XTENSA_MPU_ACCESS_P_RWX_U_RWX: + /* These permissions are okay. */ + break; + default: + ret = -EPERM; + goto out; + } + } + } + +out: + return ret; } + +void xtensa_user_stack_perms(struct k_thread *thread) +{ + int ret; + + uintptr_t stack_end_addr = thread->stack_info.start + thread->stack_info.size; + + if (stack_end_addr < thread->stack_info.start) { + /* Account for wrapping around back to 0. */ + stack_end_addr = 0xFFFFFFFFU; + } + + (void)memset((void *)thread->stack_info.start, + (IS_ENABLED(CONFIG_INIT_STACKS)) ? 0xAA : 0x00, + thread->stack_info.size - thread->stack_info.delta); + + /* Add stack to new domain's MPU map. */ + ret = mpu_map_region_add(thread->arch.mpu_map, + thread->stack_info.start, stack_end_addr, + XTENSA_MPU_ACCESS_P_RW_U_RW, + CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, + NULL); + + xtensa_mpu_map_write(thread); + + /* Probably this fails due to no more available slots in MPU map. */ + ARG_UNUSED(ret); + __ASSERT_NO_MSG(ret == 0); +} + +#endif /* CONFIG_USERSPACE */ diff --git a/arch/xtensa/core/offsets/offsets.c b/arch/xtensa/core/offsets/offsets.c index df3c4f8cae6..69df38275bf 100644 --- a/arch/xtensa/core/offsets/offsets.c +++ b/arch/xtensa/core/offsets/offsets.c @@ -67,8 +67,13 @@ GEN_OFFSET_SYM(_xtensa_irq_bsa_t, hifi); #ifdef CONFIG_USERSPACE GEN_OFFSET_SYM(_thread_arch_t, psp); +#ifdef CONFIG_XTENSA_MMU GEN_OFFSET_SYM(_thread_arch_t, ptables); #endif +#ifdef CONFIG_XTENSA_MPU +GEN_OFFSET_SYM(_thread_arch_t, mpu_map); +#endif +#endif GEN_ABS_SYM_END diff --git a/arch/xtensa/core/userspace.S b/arch/xtensa/core/userspace.S index 7aaa27fdd4b..42fe86f52ed 100644 --- a/arch/xtensa/core/userspace.S +++ b/arch/xtensa/core/userspace.S @@ -300,7 +300,12 @@ xtensa_userspace_enter: call4 xtensa_user_stack_perms l32i a6, a1, 24 +#ifdef CONFIG_XTENSA_MMU call4 xtensa_swap_update_page_tables +#endif +#ifdef CONFIG_XTENSA_MPU + call4 xtensa_mpu_map_write +#endif #if XCHAL_HAVE_THREADPTR #ifdef CONFIG_THREAD_LOCAL_STORAGE @@ -337,7 +342,14 @@ xtensa_userspace_enter: * We have to set callinc as well, since the called * function will do "entry" */ +#ifdef CONFIG_XTENSA_MMU movi a0, PS_WOE|PS_CALLINC(1)|PS_UM|PS_RING(2) +#endif +#ifdef CONFIG_XTENSA_MPU + /* MPU only has RING 0 and 1. */ + movi a0, PS_WOE|PS_CALLINC(1)|PS_UM|PS_RING(1) +#endif + wsr a0, EPS2 movi a0, 0 diff --git a/arch/xtensa/core/vector_handlers.c b/arch/xtensa/core/vector_handlers.c index 1c2fcd2b134..b8dca1c1967 100644 --- a/arch/xtensa/core/vector_handlers.c +++ b/arch/xtensa/core/vector_handlers.c @@ -364,14 +364,14 @@ void *xtensa_excint1_c(int *interrupted_stack) _current_cpu->nested = 1; } -#ifdef CONFIG_XTENSA_MMU +#if defined(CONFIG_XTENSA_MMU) || defined(CONFIG_XTENSA_MPU) #ifdef CONFIG_USERSPACE fixup_out: #endif if (is_dblexc) { __asm__ volatile("wsr.depc %0" : : "r"(0)); } -#endif /* CONFIG_XTENSA_MMU */ +#endif /* CONFIG_XTENSA_MMU || CONFIG_XTENSA_MPU */ return return_to(interrupted_stack); diff --git a/arch/xtensa/core/xtensa_asm2_util.S b/arch/xtensa/core/xtensa_asm2_util.S index 94e6aa1381d..dad8f199359 100644 --- a/arch/xtensa/core/xtensa_asm2_util.S +++ b/arch/xtensa/core/xtensa_asm2_util.S @@ -286,7 +286,12 @@ noflush: /* Switch page tables */ rsr a6, ZSR_CPU l32i a6, a6, ___cpu_t_current_OFFSET +#ifdef CONFIG_XTENSA_MMU call4 xtensa_swap_update_page_tables +#endif +#ifdef CONFIG_XTENSA_MPU + call4 xtensa_mpu_map_write +#endif l32i a2, a3, 0 l32i a2, a2, 0 @@ -394,9 +399,11 @@ _Level1RealVector: rsr.exccause a0 #ifdef CONFIG_XTENSA_MMU beqi a0, EXCCAUSE_ITLB_MISS, _handle_tlb_miss_user +#endif /* CONFIG_XTENSA_MMU */ #ifdef CONFIG_USERSPACE beqi a0, EXCCAUSE_SYSCALL, _syscall #endif /* CONFIG_USERSPACE */ +#ifdef CONFIG_XTENSA_MMU addi a0, a0, -EXCCAUSE_DTLB_MISS beqz a0, _handle_tlb_miss_user rsr.exccause a0 @@ -426,12 +433,12 @@ _handle_tlb_miss_user: l32i a0, a0, 0 rsr a0, ZSR_A0SAVE rfe +#endif /* CONFIG_XTENSA_MMU */ #ifdef CONFIG_USERSPACE _syscall: rsr a0, ZSR_A0SAVE j xtensa_do_syscall #endif /* CONFIG_USERSPACE */ -#endif /* CONFIG_XTENSA_MMU */ .popsection /* In theory you can have levels up to 15, but known hardware only uses 7. */ diff --git a/arch/xtensa/include/xtensa_asm2_s.h b/arch/xtensa/include/xtensa_asm2_s.h index ad99e279491..8ca152088a7 100644 --- a/arch/xtensa/include/xtensa_asm2_s.h +++ b/arch/xtensa/include/xtensa_asm2_s.h @@ -549,7 +549,12 @@ _do_call_\@: rsr a6, ZSR_CPU l32i a6, a6, ___cpu_t_current_OFFSET +#ifdef CONFIG_XTENSA_MMU call4 xtensa_swap_update_page_tables +#endif +#ifdef CONFIG_XTENSA_MPU + call4 xtensa_mpu_map_write +#endif l32i a1, a1, 0 l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF diff --git a/arch/xtensa/include/xtensa_mpu_priv.h b/arch/xtensa/include/xtensa_mpu_priv.h index 86a6462d06b..69df1b1037a 100644 --- a/arch/xtensa/include/xtensa_mpu_priv.h +++ b/arch/xtensa/include/xtensa_mpu_priv.h @@ -73,6 +73,23 @@ * @} */ +/** + * @name Bit shifts and masks for MPU PPTLB return value. + * + * @{ + */ + +/** Bit shift for segment value. */ +#define XTENSA_MPU_PPTLB_ACCESS_RIGHTS_SHIFT 8U + +/** Mask for segment value. */ +#define XTENSA_MPU_PPTLB_ACCESS_RIGHTS_MASK 0x00000F00U + +/** + * @} + */ + + /** * Define one MPU entry of type struct xtensa_mpu_entry. * @@ -140,6 +157,21 @@ static ALWAYS_INLINE void xtensa_mpu_mpuenb_write(uint32_t mpuenb) __asm__ __volatile__("wsr.mpuenb %0" : : "a"(mpuenb)); } +/** + * @brief Probe for protection TLB entry from an address. + * + * @param addr Probe address. + * + * @return Return of the PPTLB instruction. + */ +static ALWAYS_INLINE uint32_t xtensa_pptlb_probe(uintptr_t addr) +{ + uint32_t ret; + + __asm__ __volatile__("pptlb %0, %1\n\t" : "=a"(ret) : "a"(addr)); + return ret; +} + /** * @name MPU entry internal helper functions. * diff --git a/include/zephyr/arch/xtensa/arch.h b/include/zephyr/arch/xtensa/arch.h index 9c8ab6a2091..0b29df511b7 100644 --- a/include/zephyr/arch/xtensa/arch.h +++ b/include/zephyr/arch/xtensa/arch.h @@ -65,6 +65,9 @@ struct arch_mem_domain { uint32_t *ptables __aligned(CONFIG_MMU_PAGE_SIZE); uint8_t asid; bool dirty; +#endif +#ifdef CONFIG_XTENSA_MPU + struct xtensa_mpu_map mpu_map; #endif sys_snode_t node; }; diff --git a/include/zephyr/arch/xtensa/mpu.h b/include/zephyr/arch/xtensa/mpu.h index 0ccda6dfd42..364e84e59d5 100644 --- a/include/zephyr/arch/xtensa/mpu.h +++ b/include/zephyr/arch/xtensa/mpu.h @@ -190,6 +190,85 @@ struct xtensa_mpu_map { struct xtensa_mpu_entry entries[XTENSA_MPU_NUM_ENTRIES]; }; +/** + * @name Memory domain and partitions + * @{ + */ + +typedef uint32_t k_mem_partition_attr_t; + +static inline bool xtensa_mem_partition_is_executable(k_mem_partition_attr_t access_rights) +{ + bool is_exec; + + switch (access_rights) { + case XTENSA_MPU_ACCESS_P_X_U_NA: + case XTENSA_MPU_ACCESS_P_NA_U_X: + case XTENSA_MPU_ACCESS_P_RX_U_NA: + case XTENSA_MPU_ACCESS_P_RWX_U_NA: + case XTENSA_MPU_ACCESS_P_RW_U_RWX: + case XTENSA_MPU_ACCESS_P_RWX_U_RX: + case XTENSA_MPU_ACCESS_P_RX_U_RX: + case XTENSA_MPU_ACCESS_P_RWX_U_RWX: + is_exec = true; + break; + default: + is_exec = false; + break; + }; + + return is_exec; +} + +static inline bool xtensa_mem_partition_is_writable(k_mem_partition_attr_t access_rights) +{ + bool is_writable; + + switch (access_rights) { + case XTENSA_MPU_ACCESS_P_RW_U_NA: + case XTENSA_MPU_ACCESS_P_RWX_U_NA: + case XTENSA_MPU_ACCESS_P_WO_U_WO: + case XTENSA_MPU_ACCESS_P_RW_U_RWX: + case XTENSA_MPU_ACCESS_P_RW_U_RO: + case XTENSA_MPU_ACCESS_P_RWX_U_RX: + case XTENSA_MPU_ACCESS_P_RW_U_RW: + case XTENSA_MPU_ACCESS_P_RWX_U_RWX: + is_writable = true; + break; + default: + is_writable = false; + break; + }; + + return is_writable; +} + +#define K_MEM_PARTITION_IS_EXECUTABLE(access_rights) \ + (xtensa_mem_partition_is_executable(access_rights)) + +#define K_MEM_PARTITION_IS_WRITABLE(access_rights) \ + (xtensa_mem_partition_is_writable(access_rights)) + +/* Read-Write access permission attributes */ +#define K_MEM_PARTITION_P_RW_U_RW \ + ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RW_U_RW}) +#define K_MEM_PARTITION_P_RW_U_NA \ + ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RW_U_NA}) +#define K_MEM_PARTITION_P_RO_U_RO \ + ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RO_U_RO}) +#define K_MEM_PARTITION_P_RO_U_NA \ + ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RO_U_NA}) +#define K_MEM_PARTITION_P_NA_U_NA \ + ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_NA_U_NA}) + +/* Execution-allowed attributes */ +#define K_MEM_PARTITION_P_RX_U_RX \ + ((k_mem_partition_attr_t) {XTENSA_MPU_ACCESS_P_RX_U_RX}) + +/** + * @} + */ + /** * Struct to describe a memory region [start, end). */ diff --git a/include/zephyr/arch/xtensa/thread.h b/include/zephyr/arch/xtensa/thread.h index 2bebe2722bc..73f8a95e595 100644 --- a/include/zephyr/arch/xtensa/thread.h +++ b/include/zephyr/arch/xtensa/thread.h @@ -10,6 +10,10 @@ #include #ifndef _ASMLANGUAGE +#ifdef CONFIG_XTENSA_MPU +#include +#endif + /* Xtensa doesn't use these structs, but Zephyr core requires they be * defined so they can be included in struct _thread_base. Dummy * field exists for sizeof compatibility with C++. @@ -24,7 +28,15 @@ typedef struct _callee_saved _callee_saved_t; struct _thread_arch { uint32_t last_cpu; #ifdef CONFIG_USERSPACE + +#ifdef CONFIG_XTENSA_MMU uint32_t *ptables; +#endif + +#ifdef CONFIG_XTENSA_MPU + /* Pointer to the memory domain's MPU map. */ + struct xtensa_mpu_map *mpu_map; +#endif /* Initial privilege mode stack pointer when doing a system call. * Un-set for surpervisor threads. diff --git a/include/zephyr/arch/xtensa/thread_stack.h b/include/zephyr/arch/xtensa/thread_stack.h index 75e5b36f9e1..816eaf3b97c 100644 --- a/include/zephyr/arch/xtensa/thread_stack.h +++ b/include/zephyr/arch/xtensa/thread_stack.h @@ -9,6 +9,7 @@ #include #include +#include #ifdef CONFIG_KERNEL_COHERENCE #define ARCH_STACK_PTR_ALIGN XCHAL_DCACHE_LINESIZE @@ -17,9 +18,15 @@ #endif -#if CONFIG_USERSPACE +#ifdef CONFIG_USERSPACE +#ifdef CONFIG_XTENSA_MMU #define XTENSA_STACK_BASE_ALIGN CONFIG_MMU_PAGE_SIZE #define XTENSA_STACK_SIZE_ALIGN CONFIG_MMU_PAGE_SIZE +#endif +#ifdef CONFIG_XTENSA_MPU +#define XTENSA_STACK_BASE_ALIGN XCHAL_MPU_ALIGN +#define XTENSA_STACK_SIZE_ALIGN XCHAL_MPU_ALIGN +#endif #else #define XTENSA_STACK_BASE_ALIGN ARCH_STACK_PTR_ALIGN #define XTENSA_STACK_SIZE_ALIGN ARCH_STACK_PTR_ALIGN @@ -45,14 +52,16 @@ #ifndef _ASMLANGUAGE /* thread stack */ -#ifdef CONFIG_XTENSA_MMU struct xtensa_thread_stack_header { +#if defined(CONFIG_XTENSA_MMU) || defined(CONFIG_XTENSA_MPU) char privilege_stack[CONFIG_PRIVILEGED_STACK_SIZE]; +#endif /* CONFIG_XTENSA_MPU */ } __packed __aligned(XTENSA_STACK_BASE_ALIGN); +#if defined(CONFIG_XTENSA_MMU) || defined(CONFIG_XTENSA_MPU) #define ARCH_THREAD_STACK_RESERVED \ sizeof(struct xtensa_thread_stack_header) -#endif /* CONFIG_XTENSA_MMU */ +#endif /* CONFIG_XTENSA_MMU || CONFIG_XTENSA_MPU */ #define ARCH_THREAD_STACK_OBJ_ALIGN(size) XTENSA_STACK_BASE_ALIGN #define ARCH_THREAD_STACK_SIZE_ADJUST(size) \ From f7165395b4a54d7a536b3584e66ddbf9e7f8fadf Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 16 Feb 2024 12:30:18 -0800 Subject: [PATCH 0969/2402] xtensa: mpu: introduce CONFIG_XTENSA_MPU_ONLY_SOC_RANGES This allows the SoC to have total control on what MPU ranges to be programmed at boot. This overrides the generic ranges in the architecture core code. Signed-off-by: Daniel Leung --- arch/xtensa/Kconfig | 8 ++++++++ arch/xtensa/core/mpu.c | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 4d813498d98..8aa3d0fa96c 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -243,6 +243,14 @@ config XTENSA_MPU_DEFAULT_MEM_TYPE If userspace is enabled, it will be used to restore the memory type of the region being removed from a memory domain. +config XTENSA_MPU_ONLY_SOC_RANGES + bool + help + Enable this by the SoC to indicate to the architecture code to use + the MPU ranges specified by SoC only, and skip the common ranges + defined in the core architecture code. This gives total control to + the SoC on the MPU ranges. + endif # XTENSA_MPU endif # CPU_HAS_MPU diff --git a/arch/xtensa/core/mpu.c b/arch/xtensa/core/mpu.c index 4efcf33d4b4..29e33629771 100644 --- a/arch/xtensa/core/mpu.c +++ b/arch/xtensa/core/mpu.c @@ -72,6 +72,7 @@ static struct xtensa_mpu_map xtensa_mpu_map_fg_kernel; * definied in the processor configuration. */ +#ifndef CONFIG_XTENSA_MPU_ONLY_SOC_RANGES /** * Static definition of all code and data memory regions of the * current Zephyr image. This information must be available and @@ -129,6 +130,7 @@ static const struct xtensa_mpu_range mpu_zephyr_ranges[] = { .memory_type = CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, }, }; +#endif /* !CONFIG_XTENSA_MPU_ONLY_SOC_RANGES */ /** * Return the pointer to the entry encompassing @a addr out of an array of MPU entries. @@ -679,6 +681,7 @@ void xtensa_mpu_init(void) xtensa_mpu_map_fg_kernel.entries[entry] = ent; } +#ifndef CONFIG_XTENSA_MPU_ONLY_SOC_RANGES /* * Add necessary MPU entries for the memory regions of base Zephyr image. */ @@ -696,6 +699,7 @@ void xtensa_mpu_init(void) (unsigned int)range->end, ret); } +#endif /* !CONFIG_XTENSA_MPU_ONLY_SOC_RANGES */ /* * Now for the entries for memory regions needed by SoC. From f0750df3da292bb6d46f05b1a4bb24e5ffc7e0bf Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 14 Mar 2024 11:48:54 +0100 Subject: [PATCH 0970/2402] nrf5_bsim cmake: Check that the simulator version is new enough Add a cmake check to ensure the simulator is new enough and guide users to update it and rebuild if it isn't, so they get a better experience than by just getting a build or runtime error. Signed-off-by: Alberto Escolar Piedras --- cmake/modules/FindBabbleSim.cmake | 35 +++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/cmake/modules/FindBabbleSim.cmake b/cmake/modules/FindBabbleSim.cmake index 550a55c14f3..adf73babcf8 100644 --- a/cmake/modules/FindBabbleSim.cmake +++ b/cmake/modules/FindBabbleSim.cmake @@ -60,3 +60,38 @@ endif() #Many apps cmake files (in and out of tree) expect these environment variables. Lets provide them: set(ENV{BSIM_COMPONENTS_PATH} ${BSIM_COMPONENTS_PATH}) set(ENV{BSIM_OUT_PATH} ${BSIM_OUT_PATH}) + +# Let's check that it is new enough and built, +# so we provide better information to users than a compile error: + +# Internal function to print a descriptive error message +# Do NOT use it outside of this module. It uses variables internal to it +function(bsim_handle_not_built_error) + get_filename_component(BSIM_ROOT_PATH ${BSIM_COMPONENTS_PATH}/.. ABSOLUTE) + message(FATAL_ERROR "Please ensure you have the latest babblesim and rebuild it." + "If you got it from Zephyr's manifest, you can do:\n\ + west update\n\ + cd ${BSIM_ROOT_PATH}; make everything -j 8\n" + ) +endfunction(bsim_handle_not_built_error) + +# Internal function to check that a bsim component is at least the desired version +# Do NOT use it outside of this module. It uses variables internal to it +function(bsim_check_build_version bs_comp req_comp_ver) + set(version_file ${BSIM_OUT_PATH}/lib/${bs_comp}.version) + if (EXISTS ${version_file}) + file(READ ${version_file} found_version) + string(STRIP ${found_version} found_version) + else() + message(WARNING "BabbleSim was never compiled (${version_file} not found)") + bsim_handle_not_built_error() + endif() + + if (found_version VERSION_LESS req_comp_ver) + message(WARNING + "Built ${bs_comp} version = ${found_version} < ${req_comp_ver} (required version)") + bsim_handle_not_built_error() + endif() +endfunction(bsim_check_build_version) + +bsim_check_build_version(bs_2G4_phy_v1 2.4) From 42ff35dc055dd13cbecdf2cd56918022f416bcf4 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 14 Mar 2024 16:33:50 -0500 Subject: [PATCH 0971/2402] dts: rw6xx: Add TRNG Entry Add DT entry for TRNG on RW6XX Signed-off-by: Declan Snyder --- dts/arm/nxp/nxp_rw6xx_common.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index 4579255f12d..0490fc9ee82 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -10,6 +10,10 @@ #include / { + chosen { + zephyr,entropy = &trng; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -65,6 +69,13 @@ #clock-cells = <1>; }; + trng: random@14000 { + compatible = "nxp,kinetis-trng"; + reg = <0x14000 0x1000>; + status = "okay"; + interrupts = <123 0>; + }; + hsgpio0: hsgpio@0 { compatible = "nxp,lpc-gpio"; reg = <0x100000 0x4000>; From f69241ae6f27862e80277cacbdd40daffd2498f3 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 14 Mar 2024 16:34:13 -0500 Subject: [PATCH 0972/2402] boards: rd_rw612_bga: Indicate entropy support Indicate support for entropy in the board yaml and doc. Signed-off-by: Declan Snyder --- boards/nxp/rd_rw612_bga/doc/index.rst | 2 ++ boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml | 1 + 2 files changed, 3 insertions(+) diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index d80f1ee8e73..59ec7f265bb 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -45,6 +45,8 @@ Supported Features +-----------+------------+-----------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-----------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-----------------------------------+ The default configuration can be found in the defconfig file: diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml index f51228c6c90..fb876b54fa1 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -19,3 +19,4 @@ supported: - gpio - spi - i2c + - entropy From 7ff94f3207cb0c0432ade66ace2dfcd3dc12208a Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Thu, 14 Mar 2024 13:25:44 +0800 Subject: [PATCH 0973/2402] iboards: mimxrt1010_evk: add gpio support in tags add gpio support in tags for mimxrt1010_evk Signed-off-by: Hake Huang --- boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml index e611af6c798..5441b064091 100644 --- a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml @@ -26,4 +26,5 @@ supported: - usb_device - spi - adc + - gpio vendor: nxp From 80e222e8343bd231f90d0bed500e28084146faf2 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Thu, 14 Mar 2024 13:29:15 +0800 Subject: [PATCH 0974/2402] boards: mimxrt1024_evk: add arduino_header support add gpio support in board tags add arduino_header support in dts Signed-off-by: Hake Huang --- boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts | 35 +++++++++++++++++++ boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml | 3 ++ 2 files changed, 38 insertions(+) diff --git a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts index 7377cd0f1d8..4872416bbc1 100644 --- a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts @@ -57,6 +57,41 @@ zephyr,code = ; }; }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 26 0>, /* A0 */ + <1 0 &gpio1 27 0>, /* A1 */ + <2 0 &gpio1 28 0>, /* A2 */ + <3 0 &gpio1 29 0>, /* A3 */ + <4 0 &gpio1 31 0>, /* A4 */ + <5 0 &gpio1 30 0>, /* A5 */ + <6 0 &gpio1 25 0>, /* D0 */ + <7 0 &gpio1 24 0>, /* D1 */ + <8 0 &gpio1 9 0>, /* D2 */ + <9 0 &gpio1 7 0>, /* D3 */ + <10 0 &gpio1 5 0>, /* D4 */ + <11 0 &gpio1 6 0>, /* D5 */ + <12 0 &gpio1 14 0>, /* D6 */ + <13 0 &gpio1 22 0>, /* D7 */ + <14 0 &gpio1 23 0>, /* D8 */ + <15 0 &gpio1 15 0>, /* D9 */ + <16 0 &gpio1 11 0>, /* D10 */ + <17 0 &gpio1 12 0>, /* D11 */ + <18 0 &gpio1 13 0>, /* D12 */ + <19 0 &gpio1 10 0>, /* D13 */ + <20 0 &gpio3 23 0>, /* D14 */ + <21 0 &gpio3 22 0>; /* D15 */ + }; +}; + +arduino_serial: &lpuart2 { + pinctrl-0 = <&pinmux_lpuart2>; + pinctrl-1 = <&pinmux_lpuart2_sleep>; + pinctrl-names = "default", "sleep"; }; &w25q32jvwj0 { diff --git a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml index 4a0350c9cd4..ca12b2517c0 100644 --- a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml @@ -15,6 +15,8 @@ toolchain: ram: 32768 flash: 4096 supported: + - arduino_gpio + - arduino_serial - can - dma - hwinfo @@ -25,4 +27,5 @@ supported: - adc - usb_device - pwm + - gpio vendor: nxp From ba37f6ac572ccb06033a10b4b0180dfee55d865b Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Fri, 1 Mar 2024 20:56:56 +0100 Subject: [PATCH 0975/2402] boards: nucleo_g070rb: add ST Morpho connector nexus node Add a new GPIO nexus node for the ST Morpho connector in the board. Signed-off-by: Marcin Niestroj --- boards/st/nucleo_g070rb/nucleo_g070rb.dts | 1 + .../st/nucleo_g070rb/st_morpho_connector.dtsi | 75 +++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 boards/st/nucleo_g070rb/st_morpho_connector.dtsi diff --git a/boards/st/nucleo_g070rb/nucleo_g070rb.dts b/boards/st/nucleo_g070rb/nucleo_g070rb.dts index 57e1d3ebd01..7e976c93059 100644 --- a/boards/st/nucleo_g070rb/nucleo_g070rb.dts +++ b/boards/st/nucleo_g070rb/nucleo_g070rb.dts @@ -8,6 +8,7 @@ #include #include #include "arduino_r3_connector.dtsi" +#include "st_morpho_connector.dtsi" #include / { diff --git a/boards/st/nucleo_g070rb/st_morpho_connector.dtsi b/boards/st/nucleo_g070rb/st_morpho_connector.dtsi new file mode 100644 index 00000000000..e3c04c7ecb0 --- /dev/null +++ b/boards/st/nucleo_g070rb/st_morpho_connector.dtsi @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024 Marcin Niestroj + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + st_morpho_header: st-morpho-header { + compatible = "st-morpho-header"; + #gpio-cells = <2>; + gpio-map-mask = ; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , /* SB23=ON, R31=OFF */ + , + , /* SB24=ON, R32=OFF */ + , + , + , + , + , + , + , + , /* SB4=ON, SB2=OFF */ + , + , /* SB3=ON, SB5=OFF */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; From 76829948a5f5dff9e968bdefaa5e02dc5780ea21 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Fri, 1 Mar 2024 20:57:36 +0100 Subject: [PATCH 0976/2402] boards: nucleo_g071rb: add ST Morpho connector nexus node Add a new GPIO nexus node for the ST Morpho connector in the board. Signed-off-by: Marcin Niestroj --- boards/st/nucleo_g071rb/nucleo_g071rb.dts | 1 + .../st/nucleo_g071rb/st_morpho_connector.dtsi | 75 +++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 boards/st/nucleo_g071rb/st_morpho_connector.dtsi diff --git a/boards/st/nucleo_g071rb/nucleo_g071rb.dts b/boards/st/nucleo_g071rb/nucleo_g071rb.dts index 9c510e49864..ba832c389cc 100644 --- a/boards/st/nucleo_g071rb/nucleo_g071rb.dts +++ b/boards/st/nucleo_g071rb/nucleo_g071rb.dts @@ -9,6 +9,7 @@ #include #include #include "arduino_r3_connector.dtsi" +#include "st_morpho_connector.dtsi" #include / { diff --git a/boards/st/nucleo_g071rb/st_morpho_connector.dtsi b/boards/st/nucleo_g071rb/st_morpho_connector.dtsi new file mode 100644 index 00000000000..e3c04c7ecb0 --- /dev/null +++ b/boards/st/nucleo_g071rb/st_morpho_connector.dtsi @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024 Marcin Niestroj + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + st_morpho_header: st-morpho-header { + compatible = "st-morpho-header"; + #gpio-cells = <2>; + gpio-map-mask = ; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , /* SB23=ON, R31=OFF */ + , + , /* SB24=ON, R32=OFF */ + , + , + , + , + , + , + , + , /* SB4=ON, SB2=OFF */ + , + , /* SB3=ON, SB5=OFF */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; From cdf6c455c69f9b16329ffdb4426aabbe328bb4ac Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Fri, 1 Mar 2024 20:57:43 +0100 Subject: [PATCH 0977/2402] boards: nucleo_g0b1re: add ST Morpho connector nexus node Add a new GPIO nexus node for the ST Morpho connector in the board. Signed-off-by: Marcin Niestroj --- boards/st/nucleo_g0b1re/nucleo_g0b1re.dts | 1 + .../st/nucleo_g0b1re/st_morpho_connector.dtsi | 75 +++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 boards/st/nucleo_g0b1re/st_morpho_connector.dtsi diff --git a/boards/st/nucleo_g0b1re/nucleo_g0b1re.dts b/boards/st/nucleo_g0b1re/nucleo_g0b1re.dts index 337d73ebe89..ec79bd3575d 100644 --- a/boards/st/nucleo_g0b1re/nucleo_g0b1re.dts +++ b/boards/st/nucleo_g0b1re/nucleo_g0b1re.dts @@ -8,6 +8,7 @@ #include #include #include "arduino_r3_connector.dtsi" +#include "st_morpho_connector.dtsi" #include / { diff --git a/boards/st/nucleo_g0b1re/st_morpho_connector.dtsi b/boards/st/nucleo_g0b1re/st_morpho_connector.dtsi new file mode 100644 index 00000000000..e3c04c7ecb0 --- /dev/null +++ b/boards/st/nucleo_g0b1re/st_morpho_connector.dtsi @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024 Marcin Niestroj + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + st_morpho_header: st-morpho-header { + compatible = "st-morpho-header"; + #gpio-cells = <2>; + gpio-map-mask = ; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , /* SB23=ON, R31=OFF */ + , + , /* SB24=ON, R32=OFF */ + , + , + , + , + , + , + , + , /* SB4=ON, SB2=OFF */ + , + , /* SB3=ON, SB5=OFF */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; From 864af13666419305ab0271d3fb2056ab3b42a2c9 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 9 Feb 2024 14:08:26 +0200 Subject: [PATCH 0978/2402] Revert "hostap: Remove commented Kconfig options" The following commits will re-introduce functionality that the earlier commit removed, so revert the earlier commit. This reverts commit 64423e269ec92406c61af6b83298966d755ca4c8. Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 61e21bee34e..a24763b4da1 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -10,7 +10,9 @@ config WIFI_NM_WPA_SUPPLICANT select POSIX_CLOCK select POSIX_SIGNAL select POSIX_API +# depends on !POSIX_API select NET_SOCKETS +# select NET_SOCKETS_POSIX_NAMES select NET_SOCKETS_PACKET select NET_SOCKETPAIR select NET_L2_WIFI_MGMT @@ -78,10 +80,35 @@ choice WIFI_NM_WPA_SUPPLICANT_CRYPTO_BACKEND config WIFI_NM_WPA_SUPPLICANT_CRYPTO_PSA bool "PSA Crypto support for WiFi" select WIFI_NM_WPA_SUPPLICANT_WEP + # Legacy crypto, still needed + #select MBEDTLS + #select MBEDTLS_CMAC_C + #select MBEDTLS_GCM_C + #select MBEDTLS_TLS_LIBRARY + #select MBEDTLS_PK_WRITE_C + #select MBEDTLS_X509_LIBRARY + #select MBEDTLS_X509_CRT_PARSE_C + #select MBEDTLS_CIPHER_C + #select MBEDTLS_CIPHER_MODE_CTR + #select MBEDTLS_CIPHER_MODE_CBC + #select MBEDTLS_SSL_TLS_C + #select MBEDTLS_KEY_EXCHANGE_ALL_ENABLED + #select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + #select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED config WIFI_NM_WPA_SUPPLICANT_CRYPTO bool "Legacy Crypto support for WiFi" select WIFI_NM_WPA_SUPPLICANT_WEP + #select MBEDTLS + #select MBEDTLS_CIPHER_MODE_CBC + #select MBEDTLS_CIPHER_MODE_CTR + #select MBEDTLS_LEGACY_CRYPTO_C + #select MBEDTLS_ECP_C + #select MBEDTLS_CTR_DRBG_C + #select MBEDTLS_PK_WRITE_C + #select MBEDTLS_KEY_EXCHANGE_ALL_ENABLED + #select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + #select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED config WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE bool "No Crypto support for WiFi" From c99aac00c4ef9d04395d97833b387cb9e904ed0b Mon Sep 17 00:00:00 2001 From: Krishna T Date: Wed, 29 Mar 2023 15:40:26 +0530 Subject: [PATCH 0979/2402] hostap: Switch to PSA Kconfig We need to use PSA MbedTLS template to get entropy working. Rather than having a single set of options which makes dependency management tough, have a separate entry for PSA based MbedTLS which is enabled by for NS variants only. Also, don't use MbedTLS APIs for entropy, instead use the Zephyr APIs that can work for both NS and S builds. Signed-off-by: Krishna T Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 59 +++++++++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 24 deletions(-) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index a24763b4da1..e6753be47e3 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -80,35 +80,46 @@ choice WIFI_NM_WPA_SUPPLICANT_CRYPTO_BACKEND config WIFI_NM_WPA_SUPPLICANT_CRYPTO_PSA bool "PSA Crypto support for WiFi" select WIFI_NM_WPA_SUPPLICANT_WEP + select PSA_WANT_ALG_CMAC + select PSA_WANT_ALG_CBC_PKCS7 + select PSA_WANT_ALG_CTR + select PSA_WANT_ALG_ECDSA + select PSA_WANT_ALG_CTR_DRBG + select PSA_WANT_ALG_RSA_PSS + select PSA_WANT_ALG_DETERMINISTIC_ECDSA + select PSA_WANT_ALG_SHA_512 + select PSA_WANT_ALG_SHA_1 + select PSA_WANT_KEY_TYPE_RSA_KEY_PAIR + select PSA_WANT_ECC_SECP_R1_256 # Legacy crypto, still needed - #select MBEDTLS - #select MBEDTLS_CMAC_C - #select MBEDTLS_GCM_C - #select MBEDTLS_TLS_LIBRARY - #select MBEDTLS_PK_WRITE_C - #select MBEDTLS_X509_LIBRARY - #select MBEDTLS_X509_CRT_PARSE_C - #select MBEDTLS_CIPHER_C - #select MBEDTLS_CIPHER_MODE_CTR - #select MBEDTLS_CIPHER_MODE_CBC - #select MBEDTLS_SSL_TLS_C - #select MBEDTLS_KEY_EXCHANGE_ALL_ENABLED - #select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED - #select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + select MBEDTLS + select MBEDTLS_CMAC_C + select MBEDTLS_GCM_C + select MBEDTLS_TLS_LIBRARY + select MBEDTLS_PK_WRITE_C + select MBEDTLS_X509_LIBRARY + select MBEDTLS_X509_CRT_PARSE_C + select MBEDTLS_CIPHER_C + select MBEDTLS_CIPHER_MODE_CTR + select MBEDTLS_CIPHER_MODE_CBC + select MBEDTLS_SSL_TLS_C + select MBEDTLS_KEY_EXCHANGE_ALL_ENABLED + select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED config WIFI_NM_WPA_SUPPLICANT_CRYPTO bool "Legacy Crypto support for WiFi" select WIFI_NM_WPA_SUPPLICANT_WEP - #select MBEDTLS - #select MBEDTLS_CIPHER_MODE_CBC - #select MBEDTLS_CIPHER_MODE_CTR - #select MBEDTLS_LEGACY_CRYPTO_C - #select MBEDTLS_ECP_C - #select MBEDTLS_CTR_DRBG_C - #select MBEDTLS_PK_WRITE_C - #select MBEDTLS_KEY_EXCHANGE_ALL_ENABLED - #select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED - #select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + select MBEDTLS + select MBEDTLS_CIPHER_MODE_CBC + select MBEDTLS_CIPHER_MODE_CTR + select MBEDTLS_LEGACY_CRYPTO_C + select MBEDTLS_ECP_C + select MBEDTLS_CTR_DRBG_C + select MBEDTLS_PK_WRITE_C + select MBEDTLS_KEY_EXCHANGE_ALL_ENABLED + select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED config WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE bool "No Crypto support for WiFi" From 465c59f94786d816f9d2126b3969d5d997d60536 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Fri, 7 Jul 2023 12:16:29 +0200 Subject: [PATCH 0980/2402] hostap: Kconfig: Fix PSA dependency on random numbers Fix PSA dependency on random number support. Random number generated is wanted, instead of a specific PRNG algorithm. Signed-off-by: Joakim Andersson Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index e6753be47e3..58b9c9ba9b6 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -84,7 +84,7 @@ config WIFI_NM_WPA_SUPPLICANT_CRYPTO_PSA select PSA_WANT_ALG_CBC_PKCS7 select PSA_WANT_ALG_CTR select PSA_WANT_ALG_ECDSA - select PSA_WANT_ALG_CTR_DRBG + select PSA_WANT_GENERATE_RANDOM select PSA_WANT_ALG_RSA_PSS select PSA_WANT_ALG_DETERMINISTIC_ECDSA select PSA_WANT_ALG_SHA_512 From 103a8606d940b2de9913e98c860b9275999f4716 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Wed, 12 Jul 2023 15:59:05 +0200 Subject: [PATCH 0981/2402] hostap: kconfig: Enable AES key type for AES block cipher support Enable the PSA key type which enables AES block cipher support. Signed-off-by: Joakim Andersson Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 58b9c9ba9b6..88b5b62693d 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -80,6 +80,7 @@ choice WIFI_NM_WPA_SUPPLICANT_CRYPTO_BACKEND config WIFI_NM_WPA_SUPPLICANT_CRYPTO_PSA bool "PSA Crypto support for WiFi" select WIFI_NM_WPA_SUPPLICANT_WEP + select PSA_WANT_KEY_TYPE_AES select PSA_WANT_ALG_CMAC select PSA_WANT_ALG_CBC_PKCS7 select PSA_WANT_ALG_CTR From 8b16d8cffa5dcc8831bdab04b589eeb04e5f0ba2 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Fri, 15 Sep 2023 00:59:58 +0530 Subject: [PATCH 0982/2402] hostap: Fix memory leak The control interface is initialized on every interface add but only de-initialized on WPA supplicant termination. This leaks all cleanups in the control interface dei-init. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 34b91b65ed6..f9813b75dc7 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -284,6 +284,8 @@ static int del_interface(struct supplicant_context *ctx, struct net_if *iface) goto out; } + zephyr_wpa_ctrl_deinit(wpa_s); + ret = zephyr_wpa_cli_global_cmd_v("interface_remove %s", ifname); if (ret) { LOG_ERR("Failed to remove interface %s", ifname); @@ -509,7 +511,6 @@ static void handler(void) eloop_unregister_read_sock(ctx->event_socketpair[0]); - zephyr_wpa_ctrl_deinit(ctx->supplicant); zephyr_global_wpa_ctrl_deinit(); fst_global_deinit(); From 5a87ce5e1037aa82c464de7681e772dbc95d5105 Mon Sep 17 00:00:00 2001 From: Vivekananda Uppunda Date: Wed, 13 Sep 2023 06:48:28 +0530 Subject: [PATCH 0983/2402] hostap: Provide setting mode related changes to hostap module This change provides mode setting API to hostap module. Signed-off-by: Vivekananda Uppunda Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 12 ++++++++++++ modules/hostap/src/supp_api.h | 9 +++++++++ modules/hostap/src/supp_main.c | 1 + 3 files changed, 22 insertions(+) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 3b78940a4f5..17e11ab969c 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -633,3 +633,15 @@ int supplicant_reg_domain(const struct device *dev, return wifi_mgmt_api->reg_domain(dev, reg_domain); } + +int supplicant_mode(const struct device *dev, struct wifi_mode_info *mode) +{ + const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_mgmt_api(dev); + + if (!wifi_mgmt_api || !wifi_mgmt_api->mode) { + wpa_printf(MSG_ERROR, "Setting mode not supported"); + return -ENOTSUP; + } + + return wifi_mgmt_api->mode(dev, mode); +} diff --git a/modules/hostap/src/supp_api.h b/modules/hostap/src/supp_api.h index 9be68e59d6e..6c0304d4a9e 100644 --- a/modules/hostap/src/supp_api.h +++ b/modules/hostap/src/supp_api.h @@ -107,4 +107,13 @@ int supplicant_get_power_save_config(const struct device *dev, struct wifi_ps_co */ int supplicant_reg_domain(const struct device *dev, struct wifi_reg_domain *reg_domain); +/** + * @brief Set Wi-Fi mode of operation + * + * @param dev Wi-Fi interface name to use + * @param mode Mode setting to set + * @return 0 for OK; -1 for ERROR + */ +int supplicant_mode(const struct device *dev, struct wifi_mode_info *mode); + #endif /* ZEPHYR_SUPP_MGMT_H */ diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index f9813b75dc7..83f0157565c 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -49,6 +49,7 @@ static const struct wifi_mgmt_ops mgmt_ops = { .set_twt = supplicant_set_twt, .get_power_save_config = supplicant_get_power_save_config, .reg_domain = supplicant_reg_domain, + .mode = supplicant_mode, }; DEFINE_WIFI_NM_INSTANCE(wifi_supplicant, &mgmt_ops); From 5ffecde1404314a1a12c80ebd77b1c5ff041a646 Mon Sep 17 00:00:00 2001 From: Vivekananda Uppunda Date: Wed, 13 Sep 2023 07:00:28 +0530 Subject: [PATCH 0984/2402] hostap: Add Packet filter support This set of changes brings in packet filter API for Monitor and promiscuous mode operation Signed-off-by: Vivekananda Uppunda Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 12 ++++++++++++ modules/hostap/src/supp_api.h | 9 +++++++++ modules/hostap/src/supp_main.c | 1 + 3 files changed, 22 insertions(+) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 17e11ab969c..7a1eb547469 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -645,3 +645,15 @@ int supplicant_mode(const struct device *dev, struct wifi_mode_info *mode) return wifi_mgmt_api->mode(dev, mode); } + +int supplicant_filter(const struct device *dev, struct wifi_filter_info *filter) +{ + const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_mgmt_api(dev); + + if (!wifi_mgmt_api || !wifi_mgmt_api->filter) { + wpa_printf(MSG_ERROR, "Setting filter not supported"); + return -ENOTSUP; + } + + return wifi_mgmt_api->filter(dev, filter); +} diff --git a/modules/hostap/src/supp_api.h b/modules/hostap/src/supp_api.h index 6c0304d4a9e..02bb8236061 100644 --- a/modules/hostap/src/supp_api.h +++ b/modules/hostap/src/supp_api.h @@ -116,4 +116,13 @@ int supplicant_reg_domain(const struct device *dev, struct wifi_reg_domain *reg_ */ int supplicant_mode(const struct device *dev, struct wifi_mode_info *mode); +/** + * @brief Set Wi-Fi packet filter for sniffing operation + * + * @param dev Wi-Fi interface name to use + * @param filter Filter settings to set + * @return 0 for OK; -1 for ERROR + */ +int supplicant_filter(const struct device *dev, struct wifi_filter_info *filter); + #endif /* ZEPHYR_SUPP_MGMT_H */ diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 83f0157565c..d02639535ff 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -50,6 +50,7 @@ static const struct wifi_mgmt_ops mgmt_ops = { .get_power_save_config = supplicant_get_power_save_config, .reg_domain = supplicant_reg_domain, .mode = supplicant_mode, + .filter = supplicant_filter, }; DEFINE_WIFI_NM_INSTANCE(wifi_supplicant, &mgmt_ops); From c8d0e5f5fc6bfd96f52ee49a90aa2c9cfb416e1e Mon Sep 17 00:00:00 2001 From: Vivekananda Uppunda Date: Wed, 13 Sep 2023 08:13:37 +0530 Subject: [PATCH 0985/2402] hostap: Add channel set support This set of changes introduces an API to set the channel when the device is working in independent Monitor or TX injection mode Signed-off-by: Vivekananda Uppunda Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 12 ++++++++++++ modules/hostap/src/supp_api.h | 9 +++++++++ modules/hostap/src/supp_main.c | 1 + 3 files changed, 22 insertions(+) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 7a1eb547469..4e69b9ab5f2 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -657,3 +657,15 @@ int supplicant_filter(const struct device *dev, struct wifi_filter_info *filter) return wifi_mgmt_api->filter(dev, filter); } + +int supplicant_channel(const struct device *dev, struct wifi_channel_info *channel) +{ + const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_mgmt_api(dev); + + if (!wifi_mgmt_api || !wifi_mgmt_api->channel) { + wpa_printf(MSG_ERROR, "Setting channel not supported"); + return -ENOTSUP; + } + + return wifi_mgmt_api->channel(dev, channel); +} diff --git a/modules/hostap/src/supp_api.h b/modules/hostap/src/supp_api.h index 02bb8236061..d2017e90ed4 100644 --- a/modules/hostap/src/supp_api.h +++ b/modules/hostap/src/supp_api.h @@ -125,4 +125,13 @@ int supplicant_mode(const struct device *dev, struct wifi_mode_info *mode); */ int supplicant_filter(const struct device *dev, struct wifi_filter_info *filter); +/** + * @brief Set Wi-Fi channel for monitor or TX injection mode + * + * @param dev Wi-Fi interface name to use + * @param channel Channel settings to set + * @return 0 for OK; -1 for ERROR + */ +int supplicant_channel(const struct device *dev, struct wifi_channel_info *channel); + #endif /* ZEPHYR_SUPP_MGMT_H */ diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index d02639535ff..4ab22b6c9c0 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -51,6 +51,7 @@ static const struct wifi_mgmt_ops mgmt_ops = { .reg_domain = supplicant_reg_domain, .mode = supplicant_mode, .filter = supplicant_filter, + .channel = supplicant_channel, }; DEFINE_WIFI_NM_INSTANCE(wifi_supplicant, &mgmt_ops); From a9e282c285b2009612a13dda4e3d19bf754e59fd Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 10 Oct 2023 00:50:17 +0530 Subject: [PATCH 0986/2402] hostap: Fix missing dependencies for PSA Due to a bug in Kconfig, both legacy and PSA crypto were enabled earlier, so, the dependencies for PSA were missed as they were provided by legacy. Signed-off-by: Chaitanya Tata --- modules/hostap/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 88b5b62693d..30550f80854 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -104,6 +104,8 @@ config WIFI_NM_WPA_SUPPLICANT_CRYPTO_PSA select MBEDTLS_CIPHER_MODE_CTR select MBEDTLS_CIPHER_MODE_CBC select MBEDTLS_SSL_TLS_C + select MBEDTLS_ECP_C + select MBEDTLS_CTR_DRBG_C select MBEDTLS_KEY_EXCHANGE_ALL_ENABLED select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED From 73e89a2416b099041fd6ce7b772a3219ef427135 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 7 Aug 2023 22:05:45 +0530 Subject: [PATCH 0987/2402] hostap: Enable TLS only for Enterprise This hardly saves flash but helps us in doing PSA port stagewise, personal first and then enterprise. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/CMakeLists.txt | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/modules/hostap/CMakeLists.txt b/modules/hostap/CMakeLists.txt index b24320acec5..78d1666a2a8 100644 --- a/modules/hostap/CMakeLists.txt +++ b/modules/hostap/CMakeLists.txt @@ -183,11 +183,10 @@ zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO ${HOSTAP_SRC_BASE}/rsn_supp/wpa.c ${HOSTAP_SRC_BASE}/rsn_supp/preauth.c ${HOSTAP_SRC_BASE}/rsn_supp/wpa_ie.c - -# ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls-bignum.c -# ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls-ec.c -# ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls.c -# ${HOSTAP_SRC_BASE}/crypto/tls_mbedtls.c + ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls-bignum.c + ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls-ec.c + ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls.c + ${HOSTAP_SRC_BASE}/crypto/tls_mbedtls.c ${HOSTAP_SRC_BASE}/crypto/aes-wrap.c ${HOSTAP_SRC_BASE}/crypto/aes-unwrap.c ${HOSTAP_SRC_BASE}/crypto/rc4.c @@ -197,6 +196,9 @@ zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO ${HOSTAP_SRC_BASE}/crypto/sha384-prf.c ) +zephyr_library_sources_ifndef(CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE + ${COMMON_SRC_BASE}/crypto/tls_none.c +) zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_WPA3 ${HOSTAP_SRC_BASE}/common/sae.c @@ -281,10 +283,10 @@ zephyr_library_sources_ifndef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE ) zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE + ${HOSTAP_SRC_BASE}/crypto/tls_mbedtls.c ${HOSTAP_SRC_BASE}/eap_peer/eap_tls.c ${HOSTAP_SRC_BASE}/eap_peer/eap_tls_common.c - ${HOSTAP_SRC_BASE}/eap_peer/eap_peap.c ${HOSTAP_SRC_BASE}/eap_common/eap_peap_common.c ${HOSTAP_SRC_BASE}/eap_peer/eap_ttls.c From 68fb2e97ae14f8bcdfb0234ab8b95e727feafc1c Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 10 Oct 2023 19:19:26 +0530 Subject: [PATCH 0988/2402] hostap: Fix the macro rename The macro for crypto has been renamed (and as a choice), so, use the new macro to see if the crypto has been enabled. Fixes WPA2/WPA3 association. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_main.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 4ab22b6c9c0..f1ca532f294 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -11,6 +11,10 @@ LOG_MODULE_REGISTER(wifi_supplicant, CONFIG_WIFI_NM_WPA_SUPPLICANT_LOG_LEVEL); #include #include +#if !defined(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE) && !defined(CONFIG_MBEDTLS_ENABLE_HEAP) +#include +#endif /* !CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE && !CONFIG_MBEDTLS_ENABLE_HEAP */ + #include #include #include @@ -466,10 +470,10 @@ static void handler(void) struct supplicant_context *ctx; struct wpa_params params; -#if defined(CONFIG_WPA_SUPP_CRYPTO) && !defined(CONFIG_MBEDTLS_ENABLE_HEAP) +#if !defined(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE) && !defined(CONFIG_MBEDTLS_ENABLE_HEAP) /* Needed for crypto operation as default is no-op and fails */ mbedtls_platform_set_calloc_free(calloc, free); -#endif /* CONFIG_WPA_SUPP_CRYPTO */ +#endif /* !CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE && !CONFIG_MBEDTLS_ENABLE_HEAP */ ctx = get_default_context(); From 65ebae81dc4d814450e9a51317efc12958ed3e19 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 11 Oct 2023 00:56:29 +0530 Subject: [PATCH 0989/2402] hostapd: Use dedicated WPA supplicant workqueue This should solve latency issues with using system workqueue and can now closely implement the configured timeout. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 6 ++++-- modules/hostap/src/supp_main.c | 5 +++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 4e69b9ab5f2..7914aec5292 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -43,6 +43,7 @@ enum status_thread_state { K_MUTEX_DEFINE(wpa_supplicant_mutex); +extern struct k_work_q *get_workq(void); struct wpa_supp_api_ctrl { const struct device *dev; @@ -164,7 +165,8 @@ static void supp_shell_connect_status(struct k_work *work) goto out; } - k_work_reschedule(&wpa_supp_status_work, K_SECONDS(OP_STATUS_POLLING_INTERVAL)); + k_work_reschedule_for_queue(get_workq(), &wpa_supp_status_work, + K_SECONDS(OP_STATUS_POLLING_INTERVAL)); ctrl->status_thread_state = STATUS_THREAD_RUNNING; k_mutex_unlock(&wpa_supplicant_mutex); return; @@ -184,7 +186,7 @@ static inline void wpa_supp_restart_status_work(void) wpas_api_ctrl.terminate = 0; /* Start afresh */ - k_work_reschedule(&wpa_supp_status_work, K_MSEC(10)); + k_work_reschedule_for_queue(get_workq(), &wpa_supp_status_work, K_MSEC(10)); } static inline int chan_to_freq(int chan) diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index f1ca532f294..7887d1e2623 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -86,6 +86,11 @@ struct wpa_global *zephyr_get_default_supplicant_context(void) return get_default_context()->supplicant; } +struct k_work_q *get_workq(void) +{ + return &get_default_context()->iface_wq; +} + int zephyr_wifi_send_event(const struct wpa_supplicant_event_msg *msg) { struct supplicant_context *ctx; From c1a0ac883faa2460915dd2f2a67c55cb4ef36303 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 11 Oct 2023 20:19:36 +0530 Subject: [PATCH 0990/2402] hostap: Add an option to remove advanced features For a memory constrained system, basic Wi-Fi is enough, so, add a configuration option to compiled out advanced Wi-Fi features. This also supports choosing individual features if needed. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/CMakeLists.txt | 57 +++++++++++++++++++++++++++++------ modules/hostap/Kconfig | 28 +++++++++++++++++ 2 files changed, 76 insertions(+), 9 deletions(-) diff --git a/modules/hostap/CMakeLists.txt b/modules/hostap/CMakeLists.txt index 78d1666a2a8..47a9ea0807e 100644 --- a/modules/hostap/CMakeLists.txt +++ b/modules/hostap/CMakeLists.txt @@ -32,10 +32,37 @@ zephyr_library_compile_definitions( CONFIG_NO_PBKDF2 CONFIG_SHA256 CONFIG_CTRL_IFACE_ZEPHYR -# CONFIG_MBO -# CONFIG_WNM CONFIG_SUITEB192 - ) +) + + +zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE + CONFIG_NO_PBKDF2 +) + +zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_NO_DEBUG + CONFIG_NO_STDOUT_DEBUG +) + +zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_ROBUST_AV + CONFIG_ROBUST_AV +) + +zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_WMM_AC + CONFIG_WMM_AC +) + +zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_RRM + CONFIG_RRM +) + +zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_MBO + CONFIG_MBO +) + +zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM + CONFIG_WNM +) zephyr_library_include_directories( ${CMAKE_CURRENT_SOURCE_DIR}/src @@ -79,9 +106,6 @@ zephyr_library_sources( ${WIFI_NM_WPA_SUPPLICANT_BASE}/config.c ${WIFI_NM_WPA_SUPPLICANT_BASE}/notify.c ${WIFI_NM_WPA_SUPPLICANT_BASE}/eap_register.c - ${WIFI_NM_WPA_SUPPLICANT_BASE}/op_classes.c - ${WIFI_NM_WPA_SUPPLICANT_BASE}/rrm.c - ${WIFI_NM_WPA_SUPPLICANT_BASE}/wmm_ac.c ${WIFI_NM_WPA_SUPPLICANT_BASE}/config_none.c ${WIFI_NM_WPA_SUPPLICANT_BASE}/bssid_ignore.c ${WIFI_NM_WPA_SUPPLICANT_BASE}/wpas_glue.c @@ -92,9 +116,6 @@ zephyr_library_sources( ${WIFI_NM_WPA_SUPPLICANT_BASE}/sme.c ${WIFI_NM_WPA_SUPPLICANT_BASE}/wpa_supplicant.c ${WIFI_NM_WPA_SUPPLICANT_BASE}/events.c - ${WIFI_NM_WPA_SUPPLICANT_BASE}/robust_av.c -# ${WIFI_NM_WPA_SUPPLICANT_BASE}/mbo.c -# ${WIFI_NM_WPA_SUPPLICANT_BASE}/wnm_sta.c ${WIFI_NM_WPA_SUPPLICANT_BASE}/wpa_cli_cmds.c ${WIFI_NM_WPA_SUPPLICANT_BASE}/ctrl_iface_zephyr.c ${WIFI_NM_WPA_SUPPLICANT_BASE}/wpa_cli_zephyr.c @@ -105,6 +126,24 @@ zephyr_library_sources( src/supp_events.c ) +# Advanced features +zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_RRM + ${WPA_SUPPLICANT_BASE}/op_classes.c + ${WPA_SUPPLICANT_BASE}/rrm.c +) +zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_WMM_AC + ${WPA_SUPPLICANT_BASE}/wmm_ac.c +) +zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_ROBUST_AV + ${WPA_SUPPLICANT_BASE}/robust_av.c +) +zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_MBO + ${WPA_SUPPLICANT_BASE}/mbo.c +) +zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM + ${WPA_SUPPLICANT_BASE}/wnm_sta.c +) + zephyr_library_sources_ifdef(CONFIG_WPA_CLI src/wpa_cli.c ) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 30550f80854..6985a0aff6c 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -63,6 +63,34 @@ config WIFI_NM_WPA_SUPPLICANT_DEBUG_LEVEL if WIFI_NM_WPA_SUPPLICANT +# Memory optimizations +config WIFI_NM_WPA_SUPPLICANT_ADVANCED_FEATURES + bool "Advanced features" + default y + +if WIFI_NM_WPA_SUPPLICANT_ADVANCED_FEATURES + +config WIFI_NM_WPA_SUPPLICANT_ROBUST_AV + bool "Robust Audio Video streaming support" + default y + +config WIFI_NM_WPA_SUPPLICANT_WMM_AC + bool "WMM admission control" + default y + +config WIFI_NM_WPA_SUPPLICANT_MBO + bool "Agile Multiband support" + default y + +config WIFI_NM_WPA_SUPPLICANT_WNM + bool "Wireless Network Management support" + default y + +config WIFI_NM_WPA_SUPPLICANT_RRM + bool "Radio Resource Management support" + default y +endif + config WIFI_NM_WPA_SUPPLICANT_WEP bool "WEP (Legacy crypto) support" From 028d3a4f0fa49f16869b765b9e71273a3c54ed2d Mon Sep 17 00:00:00 2001 From: Ravi Dondaputi Date: Wed, 21 Jun 2023 12:36:11 +0530 Subject: [PATCH 0991/2402] hostap: Automatically fetch support channels If a specific band is configured, automatically fetch and configure the supported channels. Signed-off-by: Ravi Dondaputi Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 68 +++++++++++++++++++++++++++++++++++ modules/hostap/src/supp_api.h | 2 ++ 2 files changed, 70 insertions(+) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 7914aec5292..ca20d1e1a93 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -178,6 +178,55 @@ static void supp_shell_connect_status(struct k_work *work) k_mutex_unlock(&wpa_supplicant_mutex); } +static struct hostapd_hw_modes *get_mode_by_band(struct wpa_supplicant *wpa_s, uint8_t band) +{ + enum hostapd_hw_mode hw_mode; + bool is_6ghz = (band == WIFI_FREQ_BAND_6_GHZ) ? true : false; + + if (band == WIFI_FREQ_BAND_2_4_GHZ) { + hw_mode = HOSTAPD_MODE_IEEE80211G; + } else if ((band == WIFI_FREQ_BAND_5_GHZ) || + (band == WIFI_FREQ_BAND_6_GHZ)) { + hw_mode = HOSTAPD_MODE_IEEE80211A; + } else { + return NULL; + } + + return get_mode(wpa_s->hw.modes, wpa_s->hw.num_modes, hw_mode, is_6ghz); +} + +static int wpa_supp_supported_channels(struct wpa_supplicant *wpa_s, uint8_t band, char **chan_list) +{ + struct hostapd_hw_modes *mode = NULL; + int i; + int offset, retval; + int size; + char *_chan_list; + + mode = get_mode_by_band(wpa_s, band); + if (!mode) { + return -EINVAL; + } + + size = ((mode->num_channels) * CHAN_NUM_LEN) + 1; + _chan_list = k_malloc(size); + if (!_chan_list) { + wpa_printf(MSG_ERROR, "Mem alloc failed for channel list"); + return -ENOMEM; + } + + retval = 0; + offset = 0; + for (i = 0; i < mode->num_channels; i++) { + retval = snprintf(_chan_list + offset, CHAN_NUM_LEN, " %d", + mode->channels[i].freq); + offset += retval; + } + *chan_list = _chan_list; + + return 0; +} + static inline void wpa_supp_restart_status_work(void) { /* Terminate synchronously */ @@ -242,6 +291,7 @@ static inline enum wifi_security_type wpas_key_mgmt_to_zephyr(int key_mgmt) int supplicant_connect(const struct device *dev, struct wifi_connect_req_params *params) { struct add_network_resp resp = {0}; + char *chan_list = NULL; struct wpa_supplicant *wpa_s; int ret = 0; @@ -288,6 +338,24 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params if (!wpa_cli_cmd_v("set_network %d ieee80211w 0", resp.network_id)) { goto out; + + if (params->band) { + ret = wpa_supp_supported_channels(wpa_s, params->band, &chan_list); + if (ret < 0) { + if (!wpa_cli_cmd_v("remove_network %d", resp.network_id)) { + goto out; + } + } + + if (chan_list) { + if (!wpa_cli_cmd_v("set_network %d freq_list%s", resp.network_id, + chan_list)) { + k_free(chan_list); + goto out; + } + + k_free(chan_list); + } } if (params->security != WIFI_SECURITY_TYPE_NONE) { diff --git a/modules/hostap/src/supp_api.h b/modules/hostap/src/supp_api.h index d2017e90ed4..a6402906d66 100644 --- a/modules/hostap/src/supp_api.h +++ b/modules/hostap/src/supp_api.h @@ -16,6 +16,8 @@ #define MAC_ADDR_LEN 6 #endif +#define CHAN_NUM_LEN 6 /* for space-separated channel numbers string */ + /** * @brief Request a connection * From 99e472b79e974ce3c68ffc69334974567827251f Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Thu, 2 Nov 2023 22:21:13 +0530 Subject: [PATCH 0992/2402] hostap: Add support for MbedTLS builtin This allows the WPA supplicant to build using the builtin MbedTLS. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 6985a0aff6c..eeb2badf1f0 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -138,19 +138,16 @@ config WIFI_NM_WPA_SUPPLICANT_CRYPTO_PSA select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED -config WIFI_NM_WPA_SUPPLICANT_CRYPTO +config WIFI_NM_WPA_SUPPLICANT_CRYPTO_LEGACY_BUILTIN bool "Legacy Crypto support for WiFi" - select WIFI_NM_WPA_SUPPLICANT_WEP select MBEDTLS - select MBEDTLS_CIPHER_MODE_CBC - select MBEDTLS_CIPHER_MODE_CTR - select MBEDTLS_LEGACY_CRYPTO_C - select MBEDTLS_ECP_C - select MBEDTLS_CTR_DRBG_C + select MBEDTLS_CIPHER_MODE_CTR_ENABLED + select MBEDTLS_CIPHER_MODE_CBC_ENABLED select MBEDTLS_PK_WRITE_C - select MBEDTLS_KEY_EXCHANGE_ALL_ENABLED - select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED - select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + select MBEDTLS_ECP_C + select MBEDTLS_ECP_ALL_ENABLED + select MBEDTLS_PKCS5_C + select MBEDTLS_MAC_CMAC_ENABLED config WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE bool "No Crypto support for WiFi" From 5c24db3b1fd19c4e0cdfb47aa0bff6b61adf795a Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Fri, 3 Nov 2023 00:00:18 +0530 Subject: [PATCH 0993/2402] hostap: Fix supported channels for unknown band By default Wi-Fi works on all bands, so, the band will be unknown, in which case no need to configure a specific frequency list to WPA supplicant. Only when a use provides a specific band then this is needed. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index ca20d1e1a93..07fec21e182 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -205,6 +205,7 @@ static int wpa_supp_supported_channels(struct wpa_supplicant *wpa_s, uint8_t ban mode = get_mode_by_band(wpa_s, band); if (!mode) { + wpa_printf(MSG_ERROR, "Unsupported or invalid band: %d", band); return -EINVAL; } @@ -339,7 +340,7 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params if (!wpa_cli_cmd_v("set_network %d ieee80211w 0", resp.network_id)) { goto out; - if (params->band) { + if (params->band != WIFI_FREQ_BAND_UNKNOWN) { ret = wpa_supp_supported_channels(wpa_s, params->band, &chan_list); if (ret < 0) { if (!wpa_cli_cmd_v("remove_network %d", resp.network_id)) { From 2559fafb1351bb324ebdb2665b764b13dd7cd2cf Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Fri, 3 Nov 2023 00:36:17 +0530 Subject: [PATCH 0994/2402] hostap: Check for band and channel compatibility If a user provides both band and channel then check if they are compatible or not. Also, move the multiple remove network cleanup to goto. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 54 +++++++++++++++++++++++++++++------ 1 file changed, 45 insertions(+), 9 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 07fec21e182..daf4e0bb244 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -228,6 +228,28 @@ static int wpa_supp_supported_channels(struct wpa_supplicant *wpa_s, uint8_t ban return 0; } +static int wpa_supp_band_chan_compat(struct wpa_supplicant *wpa_s, uint8_t band, uint8_t channel) +{ + struct hostapd_hw_modes *mode = NULL; + int i; + + mode = get_mode_by_band(wpa_s, band); + if (!mode) { + wpa_printf(MSG_ERROR, "Unsupported or invalid band: %d", band); + return -EINVAL; + } + + for (i = 0; i < mode->num_channels; i++) { + if (mode->channels[i].freq == channel) { + return mode->channels[i].freq; + } + } + + wpa_printf(MSG_ERROR, "Channel %d not supported for band %d", channel, band); + + return -EINVAL; +} + static inline void wpa_supp_restart_status_work(void) { /* Terminate synchronously */ @@ -343,9 +365,7 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params if (params->band != WIFI_FREQ_BAND_UNKNOWN) { ret = wpa_supp_supported_channels(wpa_s, params->band, &chan_list); if (ret < 0) { - if (!wpa_cli_cmd_v("remove_network %d", resp.network_id)) { - goto out; - } + goto rem_net; } if (chan_list) { @@ -400,7 +420,7 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params ret = -1; wpa_printf(MSG_ERROR, "Unsupported security type: %d", params->security); - goto out; + goto rem_net; } if (params->mfp) { @@ -417,12 +437,21 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params } if (params->channel != WIFI_CHANNEL_ANY) { - int freq = chan_to_freq(params->channel); + int freq; - if (freq < 0) { - ret = -1; - wpa_printf(MSG_ERROR, "Invalid channel %d", params->channel); - goto out; + if (params->band != WIFI_FREQ_BAND_UNKNOWN) { + freq = wpa_supp_band_chan_compat(wpa_s, params->band, params->channel); + if (freq < 0) { + goto rem_net; + } + } else { + freq = chan_to_freq(params->channel); + if (freq < 0) { + ret = -1; + wpa_printf(MSG_ERROR, "Invalid channel %d", + params->channel); + goto rem_net; + } } zephyr_wpa_cli_cmd_v("set_network %d scan_freq %d", @@ -439,6 +468,13 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params wpas_api_ctrl.requested_op = CONNECT; wpas_api_ctrl.connection_timeout = params->timeout; + goto out; + +rem_net: + if (!wpa_cli_cmd_v("remove_network %d", resp.network_id)) { + goto out; + } + out: k_mutex_unlock(&wpa_supplicant_mutex); From ef5dda3378da64b61d03f09f28151755fc78f05a Mon Sep 17 00:00:00 2001 From: Emanuele Di Santo Date: Wed, 8 Nov 2023 10:42:49 +0100 Subject: [PATCH 0995/2402] hostap: kconfig: let entry be a menuconfig wpa_supplicant has a lot of entries, and it appears in the top-level menu. Let it be a menuconfig, so that it gets its own menu page with all the options, instead of expanding in the top-level menu when selected. Signed-off-by: Emanuele Di Santo Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index eeb2badf1f0..e12d3179208 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -5,7 +5,7 @@ # SPDX-License-Identifier: Apache-2.0 # -config WIFI_NM_WPA_SUPPLICANT +menuconfig WIFI_NM_WPA_SUPPLICANT bool "WPA Suplicant from hostap project [EXPERIMENTAL]" select POSIX_CLOCK select POSIX_SIGNAL From 786fee7ae52bc4db355352a131e2897cc4bf483e Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Thu, 23 Nov 2023 21:24:19 +0530 Subject: [PATCH 0996/2402] hostap: Fix WFA mandatory features MBO and WMM-AC are mandatory for WFA certification, so cannot be disabled for memory saving. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index e12d3179208..71461ebe4d8 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -74,12 +74,13 @@ config WIFI_NM_WPA_SUPPLICANT_ROBUST_AV bool "Robust Audio Video streaming support" default y +# Hidden as these are mandatory for WFA certification config WIFI_NM_WPA_SUPPLICANT_WMM_AC - bool "WMM admission control" + bool default y config WIFI_NM_WPA_SUPPLICANT_MBO - bool "Agile Multiband support" + bool default y config WIFI_NM_WPA_SUPPLICANT_WNM From 9e9a067c0281b782e6f62e31dd50214ba86da3c1 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 29 Nov 2023 21:24:28 +0530 Subject: [PATCH 0997/2402] hostap: Fix WPA-PSK handling WPA-PSK was added a bit late, so, it wasn't properly implemented, use both key management and protocol version to properly handle WPA-PSK in both connection and also in the status. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index daf4e0bb244..91a1001ad50 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -294,13 +294,17 @@ static inline enum wifi_frequency_bands wpas_band_to_zephyr(enum wpa_radio_work_ } } -static inline enum wifi_security_type wpas_key_mgmt_to_zephyr(int key_mgmt) +static inline enum wifi_security_type wpas_key_mgmt_to_zephyr(int key_mgmt, int proto) { switch (key_mgmt) { case WPA_KEY_MGMT_NONE: return WIFI_SECURITY_TYPE_NONE; case WPA_KEY_MGMT_PSK: - return WIFI_SECURITY_TYPE_PSK; + if (proto == WPA_PROTO_RSN) { + return WIFI_SECURITY_TYPE_PSK; + } else { + return WIFI_SECURITY_TYPE_WPA_PSK; + } case WPA_KEY_MGMT_PSK_SHA256: return WIFI_SECURITY_TYPE_PSK_SHA256; case WPA_KEY_MGMT_SAE: @@ -406,7 +410,8 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params resp.network_id)) { goto out; } - } else if (params->security == WIFI_SECURITY_TYPE_PSK) { + } else if (params->security == WIFI_SECURITY_TYPE_PSK || + params->security == WIFI_SECURITY_TYPE_WPA_PSK) { if (!wpa_cli_cmd_v("set_network %d psk \"%s\"", resp.network_id, params->psk)) { goto out; @@ -416,6 +421,18 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params resp.network_id)) { goto out; } + + if (params->security == WIFI_SECURITY_TYPE_WPA_PSK) { + if (!wpa_cli_cmd_v("set_network %d proto WPA", + resp.network_id)) { + goto out; + } + } else { + if (!wpa_cli_cmd_v("set_network %d proto RSN", + resp.network_id)) { + goto out; + } + } } else { ret = -1; wpa_printf(MSG_ERROR, "Unsupported security type: %d", @@ -567,7 +584,7 @@ int supplicant_status(const struct device *dev, struct wifi_iface_status *status os_memcpy(status->bssid, wpa_s->bssid, WIFI_MAC_ADDR_LEN); status->band = wpas_band_to_zephyr(wpas_freq_to_band(wpa_s->assoc_freq)); - status->security = wpas_key_mgmt_to_zephyr(wpa_s->key_mgmt); + status->security = wpas_key_mgmt_to_zephyr(wpa_s->key_mgmt, wpa_s->wpa_proto); status->mfp = ssid->ieee80211w; /* Same mapping */ ieee80211_freq_to_chan(wpa_s->assoc_freq, &channel); status->channel = channel; From 51731525ad802792c8053acecc0bc03fa5eef396 Mon Sep 17 00:00:00 2001 From: Ravi Dondaputi Date: Tue, 5 Dec 2023 16:21:32 +0530 Subject: [PATCH 0998/2402] hostap: Set frequency before enabling the network Enabling a network would trigger a scan. Since frequency is being set after enable_network, first scan is issued without any specific frequency. Signed-off-by: Ravi Dondaputi Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 91a1001ad50..f2e22addcc5 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -448,11 +448,6 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params } } - /* enable and select network */ - if (!wpa_cli_cmd_v("enable_network %d", resp.network_id)) { - goto out; - } - if (params->channel != WIFI_CHANNEL_ANY) { int freq; @@ -475,6 +470,11 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params resp.network_id, freq); } + /* enable and select network */ + if (!wpa_cli_cmd_v("enable_network %d", resp.network_id)) { + goto out; + } + if (!wpa_cli_cmd_v("select_network %d", resp.network_id)) { goto out; } From dc24fba40ee8e8624e00335e63ba39784ea6a487 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 6 Dec 2023 02:19:03 +0530 Subject: [PATCH 0999/2402] hostap: Fix MAC address parsing with newlib nano If the WPA supplicant internal event has a MAC address, and the sample is compiled with newlib-nano then then the parsing fails because of lack of support for C99 formatting options in nano [1]. Fix this by using supported specifier, even the code that encodes the message uses the same format specifier. [1] - https://docs.zephyrproject.org/latest/develop/languages/c/newlib.html#formatted-output Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_events.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index 3fd6c2cb700..e8ca5a7d971 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -9,8 +9,6 @@ #include "includes.h" #include "common.h" -#define MAC_STR_FORMAT "%2hhx:%2hhx:%2hhx:%2hhx:%2hhx:%2hhx" - static const char * const supplicant_event_map[] = { "CTRL-EVENT-CONNECTED", "CTRL-EVENT-DISCONNECTED", @@ -36,7 +34,6 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat int ret = 1; /* For cases where parsing is not being done*/ int event = -1; int i; - unsigned char *mac; union supplicant_event_data *data; data = (union supplicant_event_data *)event_data->data; @@ -58,29 +55,25 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat switch (event_data->event) { case SUPPLICANT_EVENT_CONNECTED: - mac = data->connected.bssid; ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-CONNECTED - Connection to") - 1, - MAC_STR_FORMAT, - &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + MACSTR, MAC2STR(data->connected.bssid)); event_data->data_len = sizeof(data->connected); break; case SUPPLICANT_EVENT_DISCONNECTED: - mac = data->disconnected.bssid; ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-DISCONNECTED bssid=") - 1, - MAC_STR_FORMAT" reason=%d", &mac[0], &mac[1], &mac[2], - &mac[3], &mac[4], &mac[5], &data->disconnected.reason_code); + MACSTR" reason=%d", MAC2STR(data->disconnected.bssid), + &data->disconnected.reason_code); event_data->data_len = sizeof(data->disconnected); break; case SUPPLICANT_EVENT_ASSOC_REJECT: /* TODO */ break; case SUPPLICANT_EVENT_AUTH_REJECT: - mac = data->auth_reject.bssid; ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-AUTH-REJECT ") - 1, - MAC_STR_FORMAT + MACSTR " auth_type=%u auth_transaction=%u status_code=%u", - &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5], + MAC2STR(data->auth_reject.bssid), &data->auth_reject.auth_type, &data->auth_reject.auth_transaction, &data->auth_reject.status_code); @@ -104,17 +97,17 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat case SUPPLICANT_EVENT_BSS_ADDED: mac = data->bss_added.bssid; ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-BSS-ADDED ") - 1, - "%u "MAC_STR_FORMAT, + "%u "MACSTR, &data->bss_added.id, - &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + MAC2STR(data->bss_added.bssid)); event_data->data_len = sizeof(data->bss_added); break; case SUPPLICANT_EVENT_BSS_REMOVED: mac = data->bss_removed.bssid; ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-BSS-REMOVED ") - 1, - "%u "MAC_STR_FORMAT, + "%u "MACSTR, &data->bss_removed.id, - &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + MAC2STR(data->bss_removed.bssid)); event_data->data_len = sizeof(data->bss_removed); break; case SUPPLICANT_EVENT_TERMINATING: From 74f83259a1dd428f27c1372ab7abfcf7194c5c15 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Fri, 8 Dec 2023 16:17:45 +0530 Subject: [PATCH 1000/2402] hostap: Fix build warnings Using "%02x" needs an unsigned integer, but all MAC addresses use "unsigned char/char" as the data type, so, to avoid warnings, use a temporary array. Also, the macro from the WPA supplicant doesn't use the address of the array element and causes warnings, so re-define the macro with address of the element. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_events.c | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index e8ca5a7d971..9fb44acac26 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -9,6 +9,9 @@ #include "includes.h" #include "common.h" +/* Re-defines MAC2STR with address of the element */ +#define MACADDR2STR(a) &(a)[0], &(a)[1], &(a)[2], &(a)[3], &(a)[4], &(a)[5] + static const char * const supplicant_event_map[] = { "CTRL-EVENT-CONNECTED", "CTRL-EVENT-DISCONNECTED", @@ -28,6 +31,15 @@ static const char * const supplicant_event_map[] = { "CTRL-EVENT-DSCP-POLICY", }; +static void copy_mac_addr(const unsigned int *src, uint8_t *dst) +{ + int i; + + for (i = 0; i < ETH_ALEN; i++) { + dst[i] = src[i]; + } +} + static int supplicant_process_status(struct supplicant_int_event_data *event_data, char *supplicant_status) { @@ -35,6 +47,7 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat int event = -1; int i; union supplicant_event_data *data; + unsigned int tmp_mac_addr[ETH_ALEN]; data = (union supplicant_event_data *)event_data->data; @@ -57,14 +70,16 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat case SUPPLICANT_EVENT_CONNECTED: ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-CONNECTED - Connection to") - 1, - MACSTR, MAC2STR(data->connected.bssid)); + MACSTR, MACADDR2STR(tmp_mac_addr)); event_data->data_len = sizeof(data->connected); + copy_mac_addr(tmp_mac_addr, data->connected.bssid); break; case SUPPLICANT_EVENT_DISCONNECTED: ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-DISCONNECTED bssid=") - 1, - MACSTR" reason=%d", MAC2STR(data->disconnected.bssid), + MACSTR" reason=%d", MACADDR2STR(tmp_mac_addr), &data->disconnected.reason_code); event_data->data_len = sizeof(data->disconnected); + copy_mac_addr(tmp_mac_addr, data->disconnected.bssid); break; case SUPPLICANT_EVENT_ASSOC_REJECT: /* TODO */ @@ -73,11 +88,12 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-AUTH-REJECT ") - 1, MACSTR " auth_type=%u auth_transaction=%u status_code=%u", - MAC2STR(data->auth_reject.bssid), + MACADDR2STR(tmp_mac_addr), &data->auth_reject.auth_type, &data->auth_reject.auth_transaction, &data->auth_reject.status_code); event_data->data_len = sizeof(data->auth_reject); + copy_mac_addr(tmp_mac_addr, data->auth_reject.bssid); break; case SUPPLICANT_EVENT_SSID_TEMP_DISABLED: ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-SSID-TEMP-DISABLED ") - 1, @@ -99,7 +115,8 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-BSS-ADDED ") - 1, "%u "MACSTR, &data->bss_added.id, - MAC2STR(data->bss_added.bssid)); + MACADDR2STR(tmp_mac_addr)); + copy_mac_addr(tmp_mac_addr, data->bss_added.bssid); event_data->data_len = sizeof(data->bss_added); break; case SUPPLICANT_EVENT_BSS_REMOVED: @@ -107,8 +124,9 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-BSS-REMOVED ") - 1, "%u "MACSTR, &data->bss_removed.id, - MAC2STR(data->bss_removed.bssid)); + MACADDR2STR(tmp_mac_addr)); event_data->data_len = sizeof(data->bss_removed); + copy_mac_addr(tmp_mac_addr, data->bss_removed.bssid); break; case SUPPLICANT_EVENT_TERMINATING: case SUPPLICANT_EVENT_SCAN_STARTED: From e5c90db6d63d3971daf3cf9ad4c1aa679db9e2b7 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Thu, 7 Dec 2023 21:15:28 +0530 Subject: [PATCH 1001/2402] hostap: Implement detailed connection result Use the newly added enumerations to translate from WPA supplicant status codes to Zephyr Wi-Fi management status codes. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_events.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index 9fb44acac26..3ba1a287ab4 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -8,6 +8,9 @@ #include "includes.h" #include "common.h" +#include "common/ieee802_11_defs.h" + +#include /* Re-defines MAC2STR with address of the element */ #define MACADDR2STR(a) &(a)[0], &(a)[1], &(a)[2], &(a)[3], &(a)[4], &(a)[5] @@ -40,6 +43,18 @@ static void copy_mac_addr(const unsigned int *src, uint8_t *dst) } } +static enum wifi_conn_status wpas_to_wifi_mgmt_conn_status(int status) +{ + switch (status) { + case WLAN_STATUS_SUCCESS: + return WIFI_STATUS_CONN_SUCCESS; + case WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT: + return WIFI_STATUS_CONN_WRONG_PASSWORD; + default: + return WIFI_STATUS_CONN_FAIL; + } +} + static int supplicant_process_status(struct supplicant_int_event_data *event_data, char *supplicant_status) { @@ -166,7 +181,9 @@ int supplicant_send_wifi_mgmt_event(const char *ifname, enum net_event_wifi_cmd switch (event) { case NET_EVENT_WIFI_CMD_CONNECT_RESULT: - wifi_mgmt_raise_connect_result_event(iface, *(int *)supplicant_status); + wifi_mgmt_raise_connect_result_event( + iface, + wpas_to_wifi_mgmt_conn_status(*(int *)supplicant_status)); break; case NET_EVENT_WIFI_CMD_DISCONNECT_RESULT: wifi_mgmt_raise_disconnect_result_event(iface, *(int *)supplicant_status); From 046edbb1b74712e8951593640a3227ad491f0f01 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Thu, 7 Dec 2023 21:27:28 +0530 Subject: [PATCH 1002/2402] hostap: Implement detailed disconnection result Use the newly added enumerations to translate from WPA supplicant status codes to Zephyr Wi-Fi management status codes. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_events.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index 3ba1a287ab4..5c2354f4ed4 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -55,6 +55,20 @@ static enum wifi_conn_status wpas_to_wifi_mgmt_conn_status(int status) } } +static enum wifi_disconn_reason wpas_to_wifi_mgmt_diconn_status(int status) +{ + switch (status) { + case WLAN_REASON_DEAUTH_LEAVING: + return WIFI_REASON_DISCONN_AP_LEAVING; + case WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY: + return WIFI_REASON_DISCONN_INACTIVITY; + case WLAN_REASON_UNSPECIFIED: + /* fall through */ + default: + return WIFI_REASON_DISCONN_UNSPECIFIED; + } +} + static int supplicant_process_status(struct supplicant_int_event_data *event_data, char *supplicant_status) { @@ -186,7 +200,9 @@ int supplicant_send_wifi_mgmt_event(const char *ifname, enum net_event_wifi_cmd wpas_to_wifi_mgmt_conn_status(*(int *)supplicant_status)); break; case NET_EVENT_WIFI_CMD_DISCONNECT_RESULT: - wifi_mgmt_raise_disconnect_result_event(iface, *(int *)supplicant_status); + wifi_mgmt_raise_disconnect_result_event( + iface, + wpas_to_wifi_mgmt_diconn_status(*(int *)supplicant_status)); break; case NET_EVENT_SUPPLICANT_CMD_INT_EVENT: event_data.data = &data; From e4698b414c677813c4367729371bdbce1749e89c Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Thu, 7 Dec 2023 21:30:59 +0530 Subject: [PATCH 1003/2402] hostap: Use the new enum for timeout For connection timeout use the newly added enumeration. Signed-off-by: Chaitanya Tata --- modules/hostap/src/supp_events.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index 5c2354f4ed4..3b754904b28 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -50,6 +50,9 @@ static enum wifi_conn_status wpas_to_wifi_mgmt_conn_status(int status) return WIFI_STATUS_CONN_SUCCESS; case WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT: return WIFI_STATUS_CONN_WRONG_PASSWORD; + /* Handle non-supplicant errors */ + case -ETIMEDOUT: + return WIFI_STATUS_CONN_TIMEOUT; default: return WIFI_STATUS_CONN_FAIL; } From 3ae757aae8d76ad976fe5414b6babfb5d5deec4a Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 11 Dec 2023 15:45:15 +0530 Subject: [PATCH 1004/2402] hostap: Convert the unsupported event to warning This is a implementation gap and shouldn't be exposed to customers. But when we run with debug it still helps to identify any important events that are not handled. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_events.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index 3b754904b28..20af75a8280 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -92,7 +92,8 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat } if (i >= ARRAY_SIZE(supplicant_event_map)) { - wpa_printf(MSG_ERROR, "Event not supported: %s\n", supplicant_status); + /* This is not a bug but rather implementation gap (intentional or not) */ + wpa_printf(MSG_DEBUG, "Event not supported: %s", supplicant_status); return -ENOTSUP; } From bb4eed2eb17ce5e0104bf7caf50f3404302a6723 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 11 Dec 2023 16:17:06 +0530 Subject: [PATCH 1005/2402] hostap: Move to data driven design Instead of assuming that the array is perfectly aligned with enum, moved to a data driven design, this decouples from the enum numbering and also helps avoid repetition of the event string while parsing. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_events.c | 118 ++++++++++++++++--------------- 1 file changed, 60 insertions(+), 58 deletions(-) diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index 20af75a8280..e3abda35a3e 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -15,23 +15,25 @@ /* Re-defines MAC2STR with address of the element */ #define MACADDR2STR(a) &(a)[0], &(a)[1], &(a)[2], &(a)[3], &(a)[4], &(a)[5] -static const char * const supplicant_event_map[] = { - "CTRL-EVENT-CONNECTED", - "CTRL-EVENT-DISCONNECTED", - "CTRL-EVENT-ASSOC-REJECT", - "CTRL-EVENT-AUTH-REJECT", - "CTRL-EVENT-TERMINATING", - "CTRL-EVENT-SSID-TEMP-DISABLED", - "CTRL-EVENT-SSID-REENABLED", - "CTRL-EVENT-SCAN-STARTED", - "CTRL-EVENT-SCAN-RESULTS", - "CTRL-EVENT-SCAN-FAILED", - "CTRL-EVENT-BSS-ADDED", - "CTRL-EVENT-BSS-REMOVED", - "CTRL-EVENT-NETWORK-NOT-FOUND", - "CTRL-EVENT-NETWORK-ADDED", - "CTRL-EVENT-NETWORK-REMOVED", - "CTRL-EVENT-DSCP-POLICY", +static const struct wpa_supp_event_info { + const char *event_str; + enum supplicant_event_num event; +} wpa_supp_event_info[] = { + { "CTRL-EVENT-CONNECTED", SUPPLICANT_EVENT_CONNECTED }, + { "CTRL-EVENT-DISCONNECTED", SUPPLICANT_EVENT_DISCONNECTED }, + { "CTRL-EVENT-ASSOC-REJECT", SUPPLICANT_EVENT_ASSOC_REJECT }, + { "CTRL-EVENT-AUTH-REJECT", SUPPLICANT_EVENT_AUTH_REJECT }, + { "CTRL-EVENT-SSID-TEMP-DISABLED", SUPPLICANT_EVENT_SSID_TEMP_DISABLED }, + { "CTRL-EVENT-SSID-REENABLED", SUPPLICANT_EVENT_SSID_REENABLED }, + { "CTRL-EVENT-BSS-ADDED", SUPPLICANT_EVENT_BSS_ADDED }, + { "CTRL-EVENT-BSS-REMOVED", SUPPLICANT_EVENT_BSS_REMOVED }, + { "CTRL-EVENT-TERMINATING", SUPPLICANT_EVENT_TERMINATING }, + { "CTRL-EVENT-SCAN-STARTED", SUPPLICANT_EVENT_SCAN_STARTED }, + { "CTRL-EVENT-SCAN-FAILED", SUPPLICANT_EVENT_SCAN_FAILED }, + { "CTRL-EVENT-NETWORK-NOT-FOUND", SUPPLICANT_EVENT_NETWORK_NOT_FOUND }, + { "CTRL-EVENT-NETWORK-ADDED", SUPPLICANT_EVENT_NETWORK_ADDED }, + { "CTRL-EVENT-NETWORK-REMOVED", SUPPLICANT_EVENT_NETWORK_REMOVED }, + { "CTRL-EVENT-DSCP-POLICY", SUPPLICANT_EVENT_DSCP_POLICY }, }; static void copy_mac_addr(const unsigned int *src, uint8_t *dst) @@ -76,41 +78,45 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat char *supplicant_status) { int ret = 1; /* For cases where parsing is not being done*/ - int event = -1; int i; union supplicant_event_data *data; unsigned int tmp_mac_addr[ETH_ALEN]; + unsigned int event_prefix_len; + char *event_no_prefix; + struct wpa_supp_event_info event_info; data = (union supplicant_event_data *)event_data->data; - for (i = 0; i < ARRAY_SIZE(supplicant_event_map); i++) { - if (strncmp(supplicant_status, supplicant_event_map[i], - strlen(supplicant_event_map[i])) == 0) { - event = i; + for (i = 0; i < ARRAY_SIZE(wpa_supp_event_info); i++) { + if (strncmp(supplicant_status, wpa_supp_event_info[i].event_str, + strlen(wpa_supp_event_info[i].event_str)) == 0) { + event_info = wpa_supp_event_info[i]; break; } } - if (i >= ARRAY_SIZE(supplicant_event_map)) { + if (i >= ARRAY_SIZE(wpa_supp_event_info)) { /* This is not a bug but rather implementation gap (intentional or not) */ wpa_printf(MSG_DEBUG, "Event not supported: %s", supplicant_status); return -ENOTSUP; } - event_data->event = event; + /* Skip the event prefix and a space */ + event_prefix_len = strlen(event_info.event_str) + 1; + event_no_prefix = supplicant_status + event_prefix_len; + event_data->event = event_info.event; switch (event_data->event) { case SUPPLICANT_EVENT_CONNECTED: - ret = sscanf(supplicant_status + - sizeof("CTRL-EVENT-CONNECTED - Connection to") - 1, - MACSTR, MACADDR2STR(tmp_mac_addr)); + ret = sscanf(event_no_prefix, "- Connection to" + MACSTR, MACADDR2STR(tmp_mac_addr)); event_data->data_len = sizeof(data->connected); copy_mac_addr(tmp_mac_addr, data->connected.bssid); break; case SUPPLICANT_EVENT_DISCONNECTED: - ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-DISCONNECTED bssid=") - 1, - MACSTR" reason=%d", MACADDR2STR(tmp_mac_addr), - &data->disconnected.reason_code); + ret = sscanf(event_no_prefix, + MACSTR" reason=%d", MACADDR2STR(tmp_mac_addr), + &data->disconnected.reason_code); event_data->data_len = sizeof(data->disconnected); copy_mac_addr(tmp_mac_addr, data->disconnected.bssid); break; @@ -118,46 +124,42 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat /* TODO */ break; case SUPPLICANT_EVENT_AUTH_REJECT: - ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-AUTH-REJECT ") - 1, - MACSTR - " auth_type=%u auth_transaction=%u status_code=%u", - MACADDR2STR(tmp_mac_addr), - &data->auth_reject.auth_type, - &data->auth_reject.auth_transaction, - &data->auth_reject.status_code); + ret = sscanf(event_no_prefix, MACSTR + " auth_type=%u auth_transaction=%u status_code=%u", + MACADDR2STR(tmp_mac_addr), + &data->auth_reject.auth_type, + &data->auth_reject.auth_transaction, + &data->auth_reject.status_code); event_data->data_len = sizeof(data->auth_reject); copy_mac_addr(tmp_mac_addr, data->auth_reject.bssid); break; case SUPPLICANT_EVENT_SSID_TEMP_DISABLED: - ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-SSID-TEMP-DISABLED ") - 1, - "id=%d ssid=%s auth_failures=%u duration=%d reason=%s", - &data->temp_disabled.id, data->temp_disabled.ssid, - &data->temp_disabled.auth_failures, - &data->temp_disabled.duration, - data->temp_disabled.reason_code); + ret = sscanf(event_no_prefix, + "id=%d ssid=%s auth_failures=%u duration=%d reason=%s", + &data->temp_disabled.id, data->temp_disabled.ssid, + &data->temp_disabled.auth_failures, + &data->temp_disabled.duration, + data->temp_disabled.reason_code); event_data->data_len = sizeof(data->temp_disabled); break; case SUPPLICANT_EVENT_SSID_REENABLED: - ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-SSID-REENABLED ") - 1, - "id=%d ssid=%s", &data->reenabled.id, - data->reenabled.ssid); + ret = sscanf(event_no_prefix, + "id=%d ssid=%s", &data->reenabled.id, + data->reenabled.ssid); event_data->data_len = sizeof(data->reenabled); break; case SUPPLICANT_EVENT_BSS_ADDED: - mac = data->bss_added.bssid; - ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-BSS-ADDED ") - 1, - "%u "MACSTR, - &data->bss_added.id, - MACADDR2STR(tmp_mac_addr)); + ret = sscanf(event_no_prefix, "%u "MACSTR, + &data->bss_added.id, + MACADDR2STR(tmp_mac_addr)); copy_mac_addr(tmp_mac_addr, data->bss_added.bssid); event_data->data_len = sizeof(data->bss_added); break; case SUPPLICANT_EVENT_BSS_REMOVED: - mac = data->bss_removed.bssid; - ret = sscanf(supplicant_status + sizeof("CTRL-EVENT-BSS-REMOVED ") - 1, - "%u "MACSTR, - &data->bss_removed.id, - MACADDR2STR(tmp_mac_addr)); + ret = sscanf(event_no_prefix, + "%u "MACSTR, + &data->bss_removed.id, + MACADDR2STR(tmp_mac_addr)); event_data->data_len = sizeof(data->bss_removed); copy_mac_addr(tmp_mac_addr, data->bss_removed.bssid); break; @@ -167,7 +169,7 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat case SUPPLICANT_EVENT_NETWORK_NOT_FOUND: case SUPPLICANT_EVENT_NETWORK_ADDED: case SUPPLICANT_EVENT_NETWORK_REMOVED: - strncpy(data->supplicant_event_str, supplicant_event_map[event], + strncpy(data->supplicant_event_str, event_info.event_str, sizeof(data->supplicant_event_str)); event_data->data_len = strlen(data->supplicant_event_str) + 1; case SUPPLICANT_EVENT_DSCP_POLICY: @@ -179,7 +181,7 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat if (ret <= 0) { wpa_printf(MSG_ERROR, "%s Parse failed: %s", - supplicant_event_map[event_data->event], strerror(errno)); + event_info.event_str, strerror(errno)); } return ret; From 6eedef1bb62ea04d300a307081069d565dfd82be Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 11 Dec 2023 20:44:07 +0530 Subject: [PATCH 1006/2402] hostap: Add missing sources for AP mode These were missed in the original support. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/CMakeLists.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/modules/hostap/CMakeLists.txt b/modules/hostap/CMakeLists.txt index 47a9ea0807e..53933b928d4 100644 --- a/modules/hostap/CMakeLists.txt +++ b/modules/hostap/CMakeLists.txt @@ -189,6 +189,9 @@ zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_AP ${HOSTAP_SRC_BASE}/eap_server/eap_server_identity.c ${HOSTAP_SRC_BASE}/eap_server/eap_server_methods.c ${HOSTAP_SRC_BASE}/eapol_auth/eapol_auth_sm.c + ${HOSTAP_SRC_BASE}/ap/mbo_ap.c + ${HOSTAP_SRC_BASE}/ap/ctrl_iface_ap.c + ${HOSTAP_SRC_BASE}/utils/crc32.c ) zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_AP From d99ba9ca4fa4efd33c7232ac45eb1d7c7fdf19a1 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 11 Dec 2023 20:44:32 +0530 Subject: [PATCH 1007/2402] hostap: Fix the configuration macro hostapd macros should be used directly without prefixing with CONFIG. Signed-off-by: Chaitanya Tata --- modules/hostap/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/hostap/CMakeLists.txt b/modules/hostap/CMakeLists.txt index 53933b928d4..50082e582e5 100644 --- a/modules/hostap/CMakeLists.txt +++ b/modules/hostap/CMakeLists.txt @@ -199,7 +199,7 @@ zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_AP CONFIG_NO_RADIUS CONFIG_NO_VLAN CONFIG_NO_ACCOUNTING - CONFIG_NEED_AP_MLME + NEED_AP_MLME CONFIG_IEEE80211AX CONFIG_EAP_SERVER CONFIG_EAP_SERVER_IDENTITY From 8607327721f5d683b7ec74afe3ba66a911480b6f Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 11 Dec 2023 20:58:40 +0530 Subject: [PATCH 1008/2402] hostap: Move WPA CLI commands to helper function This prepares for the upcoming AP mode support and moves re-usable code to a common helper function. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 66 +++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 27 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index f2e22addcc5..98df3a5daa1 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -314,30 +314,16 @@ static inline enum wifi_security_type wpas_key_mgmt_to_zephyr(int key_mgmt, int } } -/* Public API */ -int supplicant_connect(const struct device *dev, struct wifi_connect_req_params *params) +static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, + struct wifi_connect_req_params *params, + bool mode_ap) { + int ret; struct add_network_resp resp = {0}; char *chan_list = NULL; struct wpa_supplicant *wpa_s; int ret = 0; - if (!net_if_is_admin_up(net_if_lookup_by_dev(dev))) { - wpa_printf(MSG_ERROR, - "Interface %s is down, dropping connect", - dev->name); - return -1; - } - - k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER); - - wpa_s = get_wpa_s_handle(dev); - if (!wpa_s) { - ret = -1; - wpa_printf(MSG_ERROR, "Device %s not found", dev->name); - goto out; - } - if (!wpa_cli_cmd_v("remove_network all")) { goto out; } @@ -348,7 +334,7 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params goto out; } - wpa_printf(MSG_DEBUG, "NET added: %d\n", resp.network_id); + wpa_printf(MSG_DEBUG, "NET added: %d", resp.network_id); if (!wpa_cli_cmd_v("set_network %d ssid \"%s\"", resp.network_id, params->ssid)) { @@ -475,23 +461,49 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params goto out; } - if (!wpa_cli_cmd_v("select_network %d", resp.network_id)) { + return 0; + +rem_net: + if (!wpa_cli_cmd_v("remove_network %d", resp.network_id)) { goto out; } - zephyr_wpa_cli_cmd_v("select_network %d", resp.network_id); +out: + return ret; +} - wpas_api_ctrl.dev = dev; - wpas_api_ctrl.requested_op = CONNECT; - wpas_api_ctrl.connection_timeout = params->timeout; +/* Public API */ +int supplicant_connect(const struct device *dev, struct wifi_connect_req_params *params) +{ + struct wpa_supplicant *wpa_s; + int ret = 0; - goto out; + if (!net_if_is_admin_up(net_if_lookup_by_dev(dev))) { + wpa_printf(MSG_ERROR, + "Interface %s is down, dropping connect", + dev->name); + return -1; + } -rem_net: - if (!wpa_cli_cmd_v("remove_network %d", resp.network_id)) { + k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER); + + wpa_s = get_wpa_s_handle(dev); + if (!wpa_s) { + ret = -1; + wpa_printf(MSG_ERROR, "Device %s not found", dev->name); + goto out; + } + + ret = wpas_add_and_config_network(wpa_s, params, false); + if (ret) { + wpa_printf(MSG_ERROR, "Failed to add and configure network for STA mode: %d", ret); goto out; } + wpas_api_ctrl.dev = dev; + wpas_api_ctrl.requested_op = CONNECT; + wpas_api_ctrl.connection_timeout = params->timeout; + out: k_mutex_unlock(&wpa_supplicant_mutex); From e59910aaa4330768b54e858b2eef8cddef8e0c1e Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 11 Dec 2023 21:09:53 +0530 Subject: [PATCH 1009/2402] hostap: Refactor disconnect and Remove unused variable WPA supplicant handle is not used anymore. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 79 +++++++++++++++++------------------ 1 file changed, 38 insertions(+), 41 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 98df3a5daa1..6875299328e 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -472,6 +472,43 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, return ret; } +static int wpas_disconnect_network(const struct device *dev) +{ + struct net_if *iface = net_if_lookup_by_dev(dev); + int ret = 0; + + if (!iface) { + ret = -ENOENT; + wpa_printf(MSG_ERROR, "Interface for device %s not found", dev->name); + return ret; + } + + k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER); + + wpas_api_ctrl.dev = dev; + wpas_api_ctrl.requested_op = DISCONNECT; + + if (!wpa_cli_cmd_v("disconnect")) { + goto out; + } + +out: + k_mutex_unlock(&wpa_supplicant_mutex); + + if (ret) { + wpa_printf(MSG_ERROR, "Disconnect failed: %s", strerror(-ret)); + return ret; + } + + wpa_supp_restart_status_work(); + + ret = wait_for_disconnect_complete(dev); + + wifi_mgmt_raise_disconnect_complete_event(iface, ret); + + return ret; +} + /* Public API */ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params *params) { @@ -516,47 +553,7 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params int supplicant_disconnect(const struct device *dev) { - struct net_if *iface = net_if_lookup_by_dev(dev); - struct wpa_supplicant *wpa_s; - int ret; - - if (!iface) { - ret = -ENOENT; - wpa_printf(MSG_ERROR, "Interface for device %s not found", dev->name); - return ret; - } - - k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER); - - wpa_s = get_wpa_s_handle(dev); - if (!wpa_s) { - ret = -EINVAL; - wpa_printf(MSG_ERROR, "Device %s not found", dev->name); - goto out; - } - - wpas_api_ctrl.dev = dev; - wpas_api_ctrl.requested_op = DISCONNECT; - - if (!wpa_cli_cmd_v("disconnect")) { - goto out; - } - -out: - k_mutex_unlock(&wpa_supplicant_mutex); - - if (ret) { - wpa_printf(MSG_ERROR, "Disconnect failed: %s", strerror(-ret)); - return ret; - } - - wpa_supp_restart_status_work(); - - ret = wait_for_disconnect_complete(dev); - - wifi_mgmt_raise_disconnect_complete_event(iface, ret); - - return ret; + return wpas_disconnect_network(dev); } int supplicant_status(const struct device *dev, struct wifi_iface_status *status) From f35de25ff1a8554832a684ec498a4e8dcb720638 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 11 Dec 2023 21:19:51 +0530 Subject: [PATCH 1010/2402] hostap: Basic AP mode support Implement AP mode Wi-Fi management operations. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 60 ++++++++++++++++++++++++++++++++-- modules/hostap/src/supp_api.h | 19 +++++++++++ modules/hostap/src/supp_main.c | 4 +++ 3 files changed, 81 insertions(+), 2 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 6875299328e..078a2a408a7 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -336,6 +336,12 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, wpa_printf(MSG_DEBUG, "NET added: %d", resp.network_id); + if (mode_ap) { + if (!wpa_cli_cmd_v("set_network %d mode 2", resp.network_id)) { + goto out; + } + } + if (!wpa_cli_cmd_v("set_network %d ssid \"%s\"", resp.network_id, params->ssid)) { goto out; @@ -452,8 +458,17 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, } } - zephyr_wpa_cli_cmd_v("set_network %d scan_freq %d", - resp.network_id, freq); + if (mode_ap) { + if (!wpa_cli_cmd_v("set_network %d frequency %d", + resp.network_id, freq)) { + goto out; + } + } else { + if (!wpa_cli_cmd_v("set_network %d scan_freq %d", + resp.network_id, freq)) { + goto out; + } + } } /* enable and select network */ @@ -802,3 +817,44 @@ int supplicant_channel(const struct device *dev, struct wifi_channel_info *chann return wifi_mgmt_api->channel(dev, channel); } + +#ifdef CONFIG_AP +int supplicant_ap_enable(const struct device *dev, + struct wifi_connect_req_params *params) +{ + struct wpa_supplicant *wpa_s; + int ret; + + if (!net_if_is_admin_up(net_if_lookup_by_dev(dev))) { + wpa_printf(MSG_ERROR, + "Interface %s is down, dropping connect", + dev->name); + return -1; + } + + k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER); + + wpa_s = get_wpa_s_handle(dev); + if (!wpa_s) { + ret = -1; + wpa_printf(MSG_ERROR, "Interface %s not found", dev->name); + goto out; + } + + ret = wpas_add_and_config_network(wpa_s, params, true); + if (ret) { + wpa_printf(MSG_ERROR, "Failed to add and configure network for AP mode: %d", ret); + goto out; + } + +out: + k_mutex_unlock(&wpa_supplicant_mutex); + + return ret; +} + +int supplicant_ap_disable(const struct device *dev) +{ + return wpas_disconnect_network(dev); +} +#endif /* CONFIG_AP */ diff --git a/modules/hostap/src/supp_api.h b/modules/hostap/src/supp_api.h index a6402906d66..b01f52dca3a 100644 --- a/modules/hostap/src/supp_api.h +++ b/modules/hostap/src/supp_api.h @@ -136,4 +136,23 @@ int supplicant_filter(const struct device *dev, struct wifi_filter_info *filter) */ int supplicant_channel(const struct device *dev, struct wifi_channel_info *channel); +#ifdef CONFIG_AP +/** + * @brief Set Wi-Fi AP configuration + * + * @param dev Wi-Fi interface name to use + * @param params AP configuration parameters to set + * @return 0 for OK; -1 for ERROR + */ +int supplicant_ap_enable(const struct device *dev, + struct wifi_connect_req_params *params); + +/** + * @brief Disable Wi-Fi AP + * @param dev Wi-Fi interface name to use + * @return 0 for OK; -1 for ERROR + */ +int supplicant_ap_disable(const struct device *dev); + +#endif /* CONFIG_AP */ #endif /* ZEPHYR_SUPP_MGMT_H */ diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 7887d1e2623..0c1bc5fea0a 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -56,6 +56,10 @@ static const struct wifi_mgmt_ops mgmt_ops = { .mode = supplicant_mode, .filter = supplicant_filter, .channel = supplicant_channel, +#ifdef CONFIG_AP + .ap_enable = supplicant_ap_enable, + .ap_disable = supplicant_ap_disable, +#endif /* CONFIG_AP */ }; DEFINE_WIFI_NM_INSTANCE(wifi_supplicant, &mgmt_ops); From e648f0c24a50e9ae0c1c1b8e872603fa481b09f8 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 19 Feb 2024 16:35:39 +0200 Subject: [PATCH 1011/2402] hostap: Make sure CONFIG_AP gets enabled in AP mode If user enables AP mode, make sure CONFIG_AP symbol is enabled so that access point sources get compiled etc. Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 71461ebe4d8..02653066959 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -249,6 +249,8 @@ config TESTING_OPTIONS config AP bool + depends on WIFI_NM_WPA_SUPPLICANT_AP + default y if WIFI_NM_WPA_SUPPLICANT_AP config NO_RADIUS bool From 03304184bb461f853300be01314bffe765a091d9 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Thu, 14 Dec 2023 20:32:21 +0530 Subject: [PATCH 1012/2402] hostap: Skip RSSI retrieval for AP mode RSSI is only applicable for STA mode, as for AP there are multiple peers. This causes failure and unnecessary delay, so just skip the retrieval. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 078a2a408a7..751a12ecefd 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -646,14 +646,16 @@ int supplicant_status(const struct device *dev, struct wifi_iface_status *status } } - ret = z_wpa_ctrl_signal_poll(&signal_poll); - if (!ret) { - status->rssi = signal_poll.rssi; + if (IS_ENABLED(CONFIG_AP) && status->iface_mode == WIFI_MODE_INFRA) { + ret = z_wpa_ctrl_signal_poll(&signal_poll); + if (!ret) { + status->rssi = signal_poll.rssi; + } else { + wpa_printf(MSG_WARNING, "%s:Failed to read RSSI", __func__); + status->rssi = -WPA_INVALID_NOISE; + } } else { - wpa_printf(MSG_WARNING, "%s:Failed to read RSSI\n", - __func__); status->rssi = -WPA_INVALID_NOISE; - ret = 0; } conn_info = os_zalloc(sizeof(struct wpa_conn_info)); From f0d856ff7244ffdaaa6bc68b601f3e2a6082d425 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 18 Dec 2023 17:31:47 +0530 Subject: [PATCH 1013/2402] hostap: Skip searching for exiting networks Before starting AP mode, we don't need to search for existing networks and join them, as the use-case is starting SoftAP. This speeds up the AP mode operation significantly. Signed-off-by: Chaitanya Tata --- modules/hostap/src/supp_api.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 751a12ecefd..051c22f5468 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -843,6 +843,9 @@ int supplicant_ap_enable(const struct device *dev, goto out; } + /* No need to check for existing network to join for SoftAP*/ + wpa_s->conf->ap_scan = 2; + ret = wpas_add_and_config_network(wpa_s, params, true); if (ret) { wpa_printf(MSG_ERROR, "Failed to add and configure network for AP mode: %d", ret); @@ -857,6 +860,29 @@ int supplicant_ap_enable(const struct device *dev, int supplicant_ap_disable(const struct device *dev) { - return wpas_disconnect_network(dev); + struct wpa_supplicant *wpa_s; + int ret = -1; + + k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER); + + wpa_s = get_wpa_s_handle(dev); + if (!wpa_s) { + ret = -1; + wpa_printf(MSG_ERROR, "Interface %s not found", dev->name); + goto out; + } + + ret = wpas_disconnect_network(dev); + if (ret) { + wpa_printf(MSG_ERROR, "Failed to disconnect from network"); + goto out; + } + + /* Restore ap_scan to default value */ + wpa_s->conf->ap_scan = 1; + +out: + k_mutex_unlock(&wpa_supplicant_mutex); + return ret; } #endif /* CONFIG_AP */ From 8a5a5fb4b80e261858c833d39e6d7e80142086c4 Mon Sep 17 00:00:00 2001 From: Kapil Bhatt Date: Wed, 20 Dec 2023 16:18:24 +0530 Subject: [PATCH 1014/2402] hostap: Add interactive keyword for commands The keyword is added into array argv of wpa_cli. The commands which require to be interactive this keyword will allow ro print output for them. Signed-off-by: Kapil Bhatt --- modules/hostap/src/wpa_cli.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/modules/hostap/src/wpa_cli.c b/modules/hostap/src/wpa_cli.c index 2a61d274e33..cbd66b1279d 100644 --- a/modules/hostap/src/wpa_cli.c +++ b/modules/hostap/src/wpa_cli.c @@ -25,6 +25,9 @@ static int cmd_wpa_cli(const struct shell *sh, return -EINVAL; } + argv[argc] = "interactive"; + argc++; + /* Remove wpa_cli from the argument list */ return z_wpa_ctrl_zephyr_cmd(argc - 1, &argv[1]); } From e5972171ca62263bd564571183aa4ea8fe938cf9 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Thu, 21 Dec 2023 13:55:19 +0530 Subject: [PATCH 1015/2402] hostap: Fix RSSI check for STA mode RSSI should only be retrieved for STA mode, but the check was wrong. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 051c22f5468..aa02d5d3bbe 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -646,16 +646,14 @@ int supplicant_status(const struct device *dev, struct wifi_iface_status *status } } - if (IS_ENABLED(CONFIG_AP) && status->iface_mode == WIFI_MODE_INFRA) { + status->rssi = -WPA_INVALID_NOISE; + if (status->iface_mode == WIFI_MODE_INFRA) { ret = z_wpa_ctrl_signal_poll(&signal_poll); if (!ret) { status->rssi = signal_poll.rssi; } else { wpa_printf(MSG_WARNING, "%s:Failed to read RSSI", __func__); - status->rssi = -WPA_INVALID_NOISE; } - } else { - status->rssi = -WPA_INVALID_NOISE; } conn_info = os_zalloc(sizeof(struct wpa_conn_info)); From 967bedeedcc609006a1436baaf5822de24e311c9 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 20 Dec 2023 02:02:32 +0530 Subject: [PATCH 1016/2402] hostap: Fix management frame receive The management frame structure in the WPA supplicant only has a pointer, so, it need a deep-copy before passing it to WPA supplicant, else driver ends up freeing causing invalid memory contents. Signed-off-by: Chaitanya Tata --- modules/hostap/src/supp_main.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 0c1bc5fea0a..7bdfc89c5cf 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -448,10 +448,13 @@ static void event_socket_handler(int sock, void *eloop_ctx, void *user_data) } if (msg.data) { - if (msg.event == EVENT_AUTH) { - union wpa_event_data *data = msg.data; + union wpa_event_data *data = msg.data; + /* Free up deep copied data */ + if (msg.event == EVENT_AUTH) { os_free((char *)data->auth.ies); + } else if (msg.event == EVENT_RX_MGMT) { + os_free((char *)data->rx_mgmt.frame); } os_free(msg.data); From f4b1c6c5d4c45742df9c746004b99d07cba32429 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Thu, 21 Dec 2023 20:22:22 +0530 Subject: [PATCH 1017/2402] hostap: Add checks for mode switching Don't allow automatic switching between modes, use disconnect/ap disable to explicitly allow switch. Signed-off-by: Chaitanya Tata --- modules/hostap/src/supp_api.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index aa02d5d3bbe..066507dc53b 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -546,6 +546,13 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params goto out; } + /* Allow connect in STA mode only even if we are connected already */ + if (wpa_s->current_ssid && wpa_s->current_ssid->mode != WPAS_MODE_INFRA) { + ret = -EBUSY; + wpa_printf(MSG_ERROR, "Interface %s is not in STA mode", dev->name); + goto out; + } + ret = wpas_add_and_config_network(wpa_s, params, false); if (ret) { wpa_printf(MSG_ERROR, "Failed to add and configure network for STA mode: %d", ret); @@ -841,6 +848,12 @@ int supplicant_ap_enable(const struct device *dev, goto out; } + if (wpa_s->wpa_state != WPA_DISCONNECTED) { + ret = -EBUSY; + wpa_printf(MSG_ERROR, "Interface %s is not in disconnected state", dev->name); + goto out; + } + /* No need to check for existing network to join for SoftAP*/ wpa_s->conf->ap_scan = 2; From ce85b6ce0a2479ddf80bb0b0e02048cfca25931d Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 26 Dec 2023 01:00:21 +0530 Subject: [PATCH 1018/2402] hostap: Add a connect/disconnect event helpers These can be abstracted from the core WPA supplicant. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_events.c | 34 ++++++++++++++++++++++++++++++-- modules/hostap/src/supp_events.h | 2 ++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index e3abda35a3e..62043d6fc67 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -9,6 +9,7 @@ #include "includes.h" #include "common.h" #include "common/ieee802_11_defs.h" +#include "wpa_supplicant_i.h" #include @@ -187,6 +188,35 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat return ret; } +int supplicant_send_wifi_mgmt_conn_event(void *ctx, int status_code) +{ + struct wpa_supplicant *wpa_s = ctx; + int status = wpas_to_wifi_mgmt_conn_status(status_code); + + return supplicant_send_wifi_mgmt_event(wpa_s->ifname, + NET_EVENT_WIFI_CMD_CONNECT_RESULT, + (void *)&status, + sizeof(int)); +} + +int supplicant_send_wifi_mgmt_disc_event(void *ctx, int reason_code) +{ + struct wpa_supplicant *wpa_s = ctx; + int status = wpas_to_wifi_mgmt_diconn_status(reason_code); + enum net_event_wifi_cmd event; + + if (wpa_s->wpa_state >= WPA_COMPLETED) { + event = NET_EVENT_WIFI_CMD_DISCONNECT_RESULT; + } else { + event = NET_EVENT_WIFI_CMD_CONNECT_RESULT; + } + + return supplicant_send_wifi_mgmt_event(wpa_s->ifname, + event, + (void *)&status, + sizeof(int)); +} + int supplicant_send_wifi_mgmt_event(const char *ifname, enum net_event_wifi_cmd event, void *supplicant_status, size_t len) { @@ -203,12 +233,12 @@ int supplicant_send_wifi_mgmt_event(const char *ifname, enum net_event_wifi_cmd case NET_EVENT_WIFI_CMD_CONNECT_RESULT: wifi_mgmt_raise_connect_result_event( iface, - wpas_to_wifi_mgmt_conn_status(*(int *)supplicant_status)); + *(int *)supplicant_status); break; case NET_EVENT_WIFI_CMD_DISCONNECT_RESULT: wifi_mgmt_raise_disconnect_result_event( iface, - wpas_to_wifi_mgmt_diconn_status(*(int *)supplicant_status)); + *(int *)supplicant_status); break; case NET_EVENT_SUPPLICANT_CMD_INT_EVENT: event_data.data = &data; diff --git a/modules/hostap/src/supp_events.h b/modules/hostap/src/supp_events.h index 41e64d57f54..f2030ed9b90 100644 --- a/modules/hostap/src/supp_events.h +++ b/modules/hostap/src/supp_events.h @@ -52,6 +52,8 @@ int supplicant_send_wifi_mgmt_event(const char *ifname, int supplicant_generate_state_event(const char *ifname, enum net_event_supplicant_cmd event, int status); +int supplicant_send_wifi_mgmt_conn_event(void *ctx, int status_code); +int supplicant_send_wifi_mgmt_disc_event(void *ctx, int reason_code); #define REASON_CODE_LEN 18 #define NM_WIFI_EVENT_STR_LEN 64 From 3bf20deec0d368dd1b6e9ec990bd81d294caaa99 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 26 Dec 2023 01:34:31 +0530 Subject: [PATCH 1019/2402] hostap: Implement AP mode events These events are used by AP mode, tied to AP-ENABLED and AP-DISABLED events in the hostapd/wpa_supplicant. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 27 ++++++++++++++-- modules/hostap/src/supp_events.c | 54 ++++++++++++++++++++++++++++++-- modules/hostap/src/supp_events.h | 6 ++++ 3 files changed, 82 insertions(+), 5 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 066507dc53b..f9db87ccc78 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -7,6 +7,7 @@ #include #include +#include #include "includes.h" #include "common.h" @@ -490,6 +491,8 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, static int wpas_disconnect_network(const struct device *dev) { struct net_if *iface = net_if_lookup_by_dev(dev); + struct wpa_supplicant *wpa_s; + bool is_ap = false; int ret = 0; if (!iface) { @@ -498,8 +501,19 @@ static int wpas_disconnect_network(const struct device *dev) return ret; } + wpa_s = get_wpa_s_handle(dev); + if (!wpa_s) { + ret = -1; + wpa_printf(MSG_ERROR, "Interface %s not found", dev->name); + goto out; + } + k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER); + if (wpa_s->current_ssid && wpa_s->current_ssid->mode == WPAS_MODE_AP) { + is_ap = true; + } + wpas_api_ctrl.dev = dev; wpas_api_ctrl.requested_op = DISCONNECT; @@ -518,8 +532,17 @@ static int wpas_disconnect_network(const struct device *dev) wpa_supp_restart_status_work(); ret = wait_for_disconnect_complete(dev); - - wifi_mgmt_raise_disconnect_complete_event(iface, ret); +#ifdef CONFIG_AP + if (is_ap) { + supplicant_send_wifi_mgmt_ap_status(wpa_s, + NET_EVENT_WIFI_CMD_AP_DISABLE_RESULT, + ret == 0 ? WIFI_STATUS_AP_SUCCESS : WIFI_STATUS_AP_FAIL); + } else { +#else + { +#endif /* CONFIG_AP */ + wifi_mgmt_raise_disconnect_complete_event(iface, ret); + } return ret; } diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index 62043d6fc67..6108d4acc24 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -192,9 +192,20 @@ int supplicant_send_wifi_mgmt_conn_event(void *ctx, int status_code) { struct wpa_supplicant *wpa_s = ctx; int status = wpas_to_wifi_mgmt_conn_status(status_code); + enum net_event_wifi_cmd event; + + if (!wpa_s || !wpa_s->current_ssid) { + return -EINVAL; + } + + if (wpa_s->current_ssid->mode == WPAS_MODE_AP) { + event = NET_EVENT_WIFI_CMD_AP_ENABLE_RESULT; + } else { + event = NET_EVENT_WIFI_CMD_CONNECT_RESULT; + } return supplicant_send_wifi_mgmt_event(wpa_s->ifname, - NET_EVENT_WIFI_CMD_CONNECT_RESULT, + event, (void *)&status, sizeof(int)); } @@ -205,10 +216,22 @@ int supplicant_send_wifi_mgmt_disc_event(void *ctx, int reason_code) int status = wpas_to_wifi_mgmt_diconn_status(reason_code); enum net_event_wifi_cmd event; + if (!wpa_s || !wpa_s->current_ssid) { + return -EINVAL; + } + if (wpa_s->wpa_state >= WPA_COMPLETED) { - event = NET_EVENT_WIFI_CMD_DISCONNECT_RESULT; + if (wpa_s->current_ssid->mode == WPAS_MODE_AP) { + event = NET_EVENT_WIFI_CMD_AP_DISABLE_RESULT; + } else { + event = NET_EVENT_WIFI_CMD_DISCONNECT_RESULT; + } } else { - event = NET_EVENT_WIFI_CMD_CONNECT_RESULT; + if (wpa_s->current_ssid->mode == WPAS_MODE_AP) { + event = NET_EVENT_WIFI_CMD_AP_ENABLE_RESULT; + } else { + event = NET_EVENT_WIFI_CMD_CONNECT_RESULT; + } } return supplicant_send_wifi_mgmt_event(wpa_s->ifname, @@ -217,6 +240,21 @@ int supplicant_send_wifi_mgmt_disc_event(void *ctx, int reason_code) sizeof(int)); } +#ifdef CONFIG_AP +int supplicant_send_wifi_mgmt_ap_status(void *ctx, + enum net_event_wifi_cmd event, + enum wifi_ap_status ap_status) +{ + struct wpa_supplicant *wpa_s = ctx; + int status = ap_status; + + return supplicant_send_wifi_mgmt_event(wpa_s->ifname, + event, + (void *)&status, + sizeof(int)); +} +#endif /* CONFIG_AP */ + int supplicant_send_wifi_mgmt_event(const char *ifname, enum net_event_wifi_cmd event, void *supplicant_status, size_t len) { @@ -240,6 +278,16 @@ int supplicant_send_wifi_mgmt_event(const char *ifname, enum net_event_wifi_cmd iface, *(int *)supplicant_status); break; +#ifdef CONFIG_AP + case NET_EVENT_WIFI_CMD_AP_ENABLE_RESULT: + wifi_mgmt_raise_ap_enable_result_event(iface, + *(int *)supplicant_status); + break; + case NET_EVENT_WIFI_CMD_AP_DISABLE_RESULT: + wifi_mgmt_raise_ap_disable_result_event(iface, + *(int *)supplicant_status); + break; +#endif /* CONFIG_AP */ case NET_EVENT_SUPPLICANT_CMD_INT_EVENT: event_data.data = &data; if (supplicant_process_status(&event_data, (char *)supplicant_status) > 0) { diff --git a/modules/hostap/src/supp_events.h b/modules/hostap/src/supp_events.h index f2030ed9b90..2cf796b45e6 100644 --- a/modules/hostap/src/supp_events.h +++ b/modules/hostap/src/supp_events.h @@ -55,6 +55,12 @@ int supplicant_generate_state_event(const char *ifname, int supplicant_send_wifi_mgmt_conn_event(void *ctx, int status_code); int supplicant_send_wifi_mgmt_disc_event(void *ctx, int reason_code); +#ifdef CONFIG_AP +int supplicant_send_wifi_mgmt_ap_status(void *ctx, + enum net_event_wifi_cmd event, + enum wifi_ap_status); +#endif /* CONFIG_AP */ + #define REASON_CODE_LEN 18 #define NM_WIFI_EVENT_STR_LEN 64 #define ETH_ALEN 6 From bf2863e3e59e6d215475329fdfd00860b751ceaf Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 27 Dec 2023 00:36:58 +0530 Subject: [PATCH 1020/2402] hostap: Implement AP connected station events These are to intimate the applications about connected Stations. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_events.c | 63 ++++++++++++++++++++++++++++++++ modules/hostap/src/supp_events.h | 3 ++ 2 files changed, 66 insertions(+) diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index 6108d4acc24..01a4512b95a 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -11,6 +11,12 @@ #include "common/ieee802_11_defs.h" #include "wpa_supplicant_i.h" +#ifdef CONFIG_AP +#include "ap/sta_info.h" +#include "ap/ieee802_11.h" +#include "ap/hostapd.h" +#endif /* CONFIG_AP */ + #include /* Re-defines MAC2STR with address of the element */ @@ -241,6 +247,30 @@ int supplicant_send_wifi_mgmt_disc_event(void *ctx, int reason_code) } #ifdef CONFIG_AP +static enum wifi_link_mode get_sta_link_mode(struct wpa_supplicant *wpa_s, struct sta_info *sta) +{ + if (sta->flags & WLAN_STA_HE) { + return WIFI_6; + } else if (sta->flags & WLAN_STA_VHT) { + return WIFI_5; + } else if (sta->flags & WLAN_STA_HT) { + return WIFI_4; + } else if (sta->flags & WLAN_STA_NONERP) { + return WIFI_1; + } else if (wpa_s->assoc_freq > 4000) { + return WIFI_2; + } else if (wpa_s->assoc_freq > 2000) { + return WIFI_3; + } else { + return WIFI_LINK_MODE_UNKNOWN; + } +} + +static bool is_twt_capable(struct wpa_supplicant *wpa_s, struct sta_info *sta) +{ + return hostapd_get_he_twt_responder(wpa_s->ap_iface->bss[0], IEEE80211_MODE_AP); +} + int supplicant_send_wifi_mgmt_ap_status(void *ctx, enum net_event_wifi_cmd event, enum wifi_ap_status ap_status) @@ -253,6 +283,31 @@ int supplicant_send_wifi_mgmt_ap_status(void *ctx, (void *)&status, sizeof(int)); } + +int supplicant_send_wifi_mgmt_ap_sta_event(void *ctx, + enum net_event_wifi_cmd event, + void *data) +{ + struct sta_info *sta = data; + struct wpa_supplicant *wpa_s = ctx; + struct wifi_ap_sta_info sta_info = { 0 }; + + if (!wpa_s || !sta) { + return -EINVAL; + } + + memcpy(sta_info.mac, sta->addr, sizeof(sta_info.mac)); + + if (event == NET_EVENT_WIFI_CMD_AP_STA_CONNECTED) { + sta_info.link_mode = get_sta_link_mode(wpa_s, sta); + sta_info.twt_capable = is_twt_capable(wpa_s, sta); + } + + return supplicant_send_wifi_mgmt_event(wpa_s->ifname, + event, + (void *)&sta_info, + sizeof(sta_info)); +} #endif /* CONFIG_AP */ int supplicant_send_wifi_mgmt_event(const char *ifname, enum net_event_wifi_cmd event, @@ -287,6 +342,14 @@ int supplicant_send_wifi_mgmt_event(const char *ifname, enum net_event_wifi_cmd wifi_mgmt_raise_ap_disable_result_event(iface, *(int *)supplicant_status); break; + case NET_EVENT_WIFI_CMD_AP_STA_CONNECTED: + wifi_mgmt_raise_ap_sta_connected_event(iface, + (struct wifi_ap_sta_info *)supplicant_status); + break; + case NET_EVENT_WIFI_CMD_AP_STA_DISCONNECTED: + wifi_mgmt_raise_ap_sta_disconnected_event(iface, + (struct wifi_ap_sta_info *)supplicant_status); + break; #endif /* CONFIG_AP */ case NET_EVENT_SUPPLICANT_CMD_INT_EVENT: event_data.data = &data; diff --git a/modules/hostap/src/supp_events.h b/modules/hostap/src/supp_events.h index 2cf796b45e6..4ef8ea19f8e 100644 --- a/modules/hostap/src/supp_events.h +++ b/modules/hostap/src/supp_events.h @@ -59,6 +59,9 @@ int supplicant_send_wifi_mgmt_disc_event(void *ctx, int reason_code); int supplicant_send_wifi_mgmt_ap_status(void *ctx, enum net_event_wifi_cmd event, enum wifi_ap_status); +int supplicant_send_wifi_mgmt_ap_sta_event(void *ctx, + enum net_event_wifi_cmd event, + void *data); #endif /* CONFIG_AP */ #define REASON_CODE_LEN 18 From b5ed2b45f14805fb516bdb0ad5132a3e24b1ff79 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 3 Jan 2024 17:42:00 +0530 Subject: [PATCH 1021/2402] hostap: Add mode check for disconnect This way we reject disconnect in AP mode and ap disable in STA mode, though both have same functionality we treat them differently to keep it clean. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index f9db87ccc78..550dd08317e 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -488,7 +488,7 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, return ret; } -static int wpas_disconnect_network(const struct device *dev) +static int wpas_disconnect_network(const struct device *dev, int cur_mode) { struct net_if *iface = net_if_lookup_by_dev(dev); struct wpa_supplicant *wpa_s; @@ -510,10 +510,15 @@ static int wpas_disconnect_network(const struct device *dev) k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER); - if (wpa_s->current_ssid && wpa_s->current_ssid->mode == WPAS_MODE_AP) { - is_ap = true; + if (!wpa_s->current_ssid || wpa_s->current_ssid->mode != cur_mode) { + ret = -EBUSY; + wpa_printf(MSG_ERROR, "Interface %s is not in %s mode", dev->name, + cur_mode == WPAS_MODE_INFRA ? "STA" : "AP"); + goto out; } + is_ap = (cur_mode == WPAS_MODE_AP); + wpas_api_ctrl.dev = dev; wpas_api_ctrl.requested_op = DISCONNECT; @@ -598,7 +603,7 @@ int supplicant_connect(const struct device *dev, struct wifi_connect_req_params int supplicant_disconnect(const struct device *dev) { - return wpas_disconnect_network(dev); + return wpas_disconnect_network(dev, WPAS_MODE_INFRA); } int supplicant_status(const struct device *dev, struct wifi_iface_status *status) @@ -906,7 +911,7 @@ int supplicant_ap_disable(const struct device *dev) goto out; } - ret = wpas_disconnect_network(dev); + ret = wpas_disconnect_network(dev, WPAS_MODE_AP); if (ret) { wpa_printf(MSG_ERROR, "Failed to disconnect from network"); goto out; From 8729141da168c26fdf61e244941f9b039d6a99a9 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 8 Jan 2024 21:59:49 +0530 Subject: [PATCH 1022/2402] hostap: Fix SSID check If the interface is in associated state, then current SSID will always be set, so, add an early check and use SSID info freely after that. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 47 +++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 22 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 550dd08317e..cf9be4450b8 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -640,6 +640,14 @@ int supplicant_status(const struct device *dev, struct wifi_iface_status *status struct wpa_ssid *ssid = wpa_s->current_ssid; u8 channel; struct signal_poll_resp signal_poll; + u8 *_ssid = ssid->ssid; + size_t ssid_len = ssid->ssid_len; + struct status_resp cli_status; + + if (!ssid) { + wpa_printf(MSG_ERROR, "Failed to get current ssid"); + goto out; + } os_memcpy(status->bssid, wpa_s->bssid, WIFI_MAC_ADDR_LEN); status->band = wpas_band_to_zephyr(wpas_freq_to_band(wpa_s->assoc_freq)); @@ -648,37 +656,32 @@ int supplicant_status(const struct device *dev, struct wifi_iface_status *status ieee80211_freq_to_chan(wpa_s->assoc_freq, &channel); status->channel = channel; - if (ssid) { - u8 *_ssid = ssid->ssid; - size_t ssid_len = ssid->ssid_len; - struct status_resp cli_status; + if (ssid_len == 0) { + int _res = z_wpa_ctrl_status(&cli_status); - if (ssid_len == 0) { - int _res = z_wpa_ctrl_status(&cli_status); + if (_res < 0) { + ssid_len = 0; + } else { + ssid_len = cli_status.ssid_len; + } - if (_res < 0) { - ssid_len = 0; - } else { - ssid_len = cli_status.ssid_len; - } + _ssid = cli_status.ssid; + } - _ssid = cli_status.ssid; - } - os_memcpy(status->ssid, _ssid, ssid_len); - status->ssid_len = ssid_len; - status->iface_mode = ssid->mode; - if (wpa_s->connection_set == 1) { - status->link_mode = - wpa_s->connection_he ? WIFI_6 : + os_memcpy(status->ssid, _ssid, ssid_len); + status->ssid_len = ssid_len; + status->iface_mode = ssid->mode; + + if (wpa_s->connection_set == 1) { + status->link_mode = wpa_s->connection_he ? WIFI_6 : wpa_s->connection_vht ? WIFI_5 : wpa_s->connection_ht ? WIFI_4 : wpa_s->connection_g ? WIFI_3 : wpa_s->connection_a ? WIFI_2 : wpa_s->connection_b ? WIFI_1 : WIFI_0; - } else { - status->link_mode = WIFI_LINK_MODE_UNKNOWN; - } + } else { + status->link_mode = WIFI_LINK_MODE_UNKNOWN; } status->rssi = -WPA_INVALID_NOISE; From d8600d57cc8d83503de101d9a418293e4692fe01 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 8 Jan 2024 22:03:56 +0530 Subject: [PATCH 1023/2402] hostap: Fix the security mode in AP For AP we should use the security mode from the SSID as stations can have a different security than the configure one. E.g., WPA/WPA2 in AP vs WPA in STA1 and WPA2 in STA2. Signed-off-by: Chaitanya Tata --- modules/hostap/src/supp_api.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index cf9be4450b8..6eb3201f221 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -643,15 +643,20 @@ int supplicant_status(const struct device *dev, struct wifi_iface_status *status u8 *_ssid = ssid->ssid; size_t ssid_len = ssid->ssid_len; struct status_resp cli_status; + bool is_ap; + int proto; if (!ssid) { wpa_printf(MSG_ERROR, "Failed to get current ssid"); goto out; } + is_ap = ssid->mode == WPAS_MODE_AP; + /* For AP its always the configured one */ + proto = is_ap ? ssid->proto : wpa_s->wpa_proto; os_memcpy(status->bssid, wpa_s->bssid, WIFI_MAC_ADDR_LEN); status->band = wpas_band_to_zephyr(wpas_freq_to_band(wpa_s->assoc_freq)); - status->security = wpas_key_mgmt_to_zephyr(wpa_s->key_mgmt, wpa_s->wpa_proto); + status->security = wpas_key_mgmt_to_zephyr(wpa_s->key_mgmt, proto); status->mfp = ssid->ieee80211w; /* Same mapping */ ieee80211_freq_to_chan(wpa_s->assoc_freq, &channel); status->channel = channel; From 2a144e8bfe33c5f848178a0aa802afcc94d52e61 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 17 Jan 2024 00:56:55 +0530 Subject: [PATCH 1024/2402] hostap: Fix WPA version for WPA3 and WPA2-PSK-256 The WPA version was only been set for WPA-PSK and WPA2-PSK, but for others it wasn't set. For AP mode this causes issues as WPA-IE is considered and WPA3/WPA2-PSK-256 aren't allowed, they need RSN. Explicitly set the version for all to RSN, except for WPA-PSK. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 6eb3201f221..85e346579c5 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -377,6 +377,14 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, } if (params->security != WIFI_SECURITY_TYPE_NONE) { + /* Except for WPA-PSK, rest all are under WPA2 */ + if (params->security != WIFI_SECURITY_TYPE_WPA_PSK) { + if (!wpa_cli_cmd_v("set_network %d proto RSN", + resp.network_id)) { + goto out; + } + } + if (params->security == WIFI_SECURITY_TYPE_SAE) { if (params->sae_password) { if (!wpa_cli_cmd_v("set_network %d sae_password \"%s\"", @@ -420,11 +428,6 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, resp.network_id)) { goto out; } - } else { - if (!wpa_cli_cmd_v("set_network %d proto RSN", - resp.network_id)) { - goto out; - } } } else { ret = -1; From b3a6f8c2db2f19845a299fb8c7d17f202b104094 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 23 Jan 2024 21:01:21 +0530 Subject: [PATCH 1025/2402] hostap: Implement STA disconnect in AP mode Use the WPA cli command to disconnect a station in AP mode. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 35 ++++++++++++++++++++++++++++++++++ modules/hostap/src/supp_api.h | 9 +++++++++ modules/hostap/src/supp_main.c | 1 + 3 files changed, 45 insertions(+) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 85e346579c5..15d89982875 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -935,4 +935,39 @@ int supplicant_ap_disable(const struct device *dev) k_mutex_unlock(&wpa_supplicant_mutex); return ret; } + +int supplicant_ap_sta_disconnect(const struct device *dev, + const uint8_t *mac_addr) +{ + struct wpa_supplicant *wpa_s; + int ret = -1; + + k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER); + + wpa_s = get_wpa_s_handle(dev); + if (!wpa_s) { + ret = -1; + wpa_printf(MSG_ERROR, "Interface %s not found", dev->name); + goto out; + } + + if (!mac_addr) { + ret = -EINVAL; + wpa_printf(MSG_ERROR, "Invalid MAC address"); + goto out; + } + + if (!wpa_cli_cmd_v("disassociate %02x:%02x:%02x:%02x:%02x:%02x", + mac_addr[0], mac_addr[1], mac_addr[2], + mac_addr[3], mac_addr[4], mac_addr[5])) { + goto out; + } + + ret = 0; + +out: + k_mutex_unlock(&wpa_supplicant_mutex); + + return ret; +} #endif /* CONFIG_AP */ diff --git a/modules/hostap/src/supp_api.h b/modules/hostap/src/supp_api.h index b01f52dca3a..04d720d7509 100644 --- a/modules/hostap/src/supp_api.h +++ b/modules/hostap/src/supp_api.h @@ -154,5 +154,14 @@ int supplicant_ap_enable(const struct device *dev, */ int supplicant_ap_disable(const struct device *dev); +/** + * @brief Set Wi-Fi AP STA disconnect + * @param dev Wi-Fi interface name to use + * @param mac_addr MAC address of the station to disconnect + * @return 0 for OK; -1 for ERROR + */ +int supplicant_ap_sta_disconnect(const struct device *dev, + const uint8_t *mac_addr); + #endif /* CONFIG_AP */ #endif /* ZEPHYR_SUPP_MGMT_H */ diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 7bdfc89c5cf..7f342ff9ff9 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -59,6 +59,7 @@ static const struct wifi_mgmt_ops mgmt_ops = { #ifdef CONFIG_AP .ap_enable = supplicant_ap_enable, .ap_disable = supplicant_ap_disable, + .ap_sta_disconnect = supplicant_ap_sta_disconnect, #endif /* CONFIG_AP */ }; From 675346705f6a9f10afbabe72825a52b280a08c21 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Fri, 26 Jan 2024 02:44:31 +0530 Subject: [PATCH 1026/2402] hostap: Fix channel comparison Due to a typo, channel and frequency were compared causing the connection to fail for any combination. Signed-off-by: Chaitanya Tata --- modules/hostap/src/supp_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 15d89982875..4c6263b39f9 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -241,7 +241,7 @@ static int wpa_supp_band_chan_compat(struct wpa_supplicant *wpa_s, uint8_t band, } for (i = 0; i < mode->num_channels; i++) { - if (mode->channels[i].freq == channel) { + if (mode->channels[i].chan == channel) { return mode->channels[i].freq; } } From e1729b44efc9962649308682188d5866467b9e76 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 16 Feb 2024 17:10:50 +0200 Subject: [PATCH 1027/2402] hostap: Fix compilation issues The big cherry-picking left some invalid code so remove/fix it in order to pass the compilation. Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 3 +-- modules/hostap/src/supp_main.c | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 4c6263b39f9..afa6c052f14 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -319,10 +319,8 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, struct wifi_connect_req_params *params, bool mode_ap) { - int ret; struct add_network_resp resp = {0}; char *chan_list = NULL; - struct wpa_supplicant *wpa_s; int ret = 0; if (!wpa_cli_cmd_v("remove_network all")) { @@ -358,6 +356,7 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, if (!wpa_cli_cmd_v("set_network %d ieee80211w 0", resp.network_id)) { goto out; + } if (params->band != WIFI_FREQ_BAND_UNKNOWN) { ret = wpa_supp_supported_channels(wpa_s, params->band, &chan_list); diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 7f342ff9ff9..572d2b4a716 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -160,7 +160,6 @@ struct wpa_supplicant *zephyr_get_handle_by_ifname(const char *ifname) { struct wpa_supplicant *wpa_s = NULL; struct supplicant_context *ctx = get_default_context(); - int ret; wpa_s = wpa_supplicant_get_iface(ctx->supplicant, ifname); if (!wpa_s) { From 5af390c600479138d81e18d2c7fb8f158b6629c1 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 16 Feb 2024 17:15:41 +0200 Subject: [PATCH 1028/2402] hostap: Fix missing items in Kconfig and CMakeLists.txt files Various settings in Kconfig and CMakeLists.txt file were plain wrong or missing. Signed-off-by: Jukka Rissanen --- modules/hostap/CMakeLists.txt | 43 +++++++++++++++++------------------ modules/hostap/Kconfig | 26 ++++++++++++++++----- 2 files changed, 41 insertions(+), 28 deletions(-) diff --git a/modules/hostap/CMakeLists.txt b/modules/hostap/CMakeLists.txt index 50082e582e5..19a8a67920b 100644 --- a/modules/hostap/CMakeLists.txt +++ b/modules/hostap/CMakeLists.txt @@ -28,8 +28,6 @@ zephyr_library_compile_definitions( CONFIG_NO_CONFIG_BLOBS CONFIG_CTRL_IFACE CONFIG_NO_RANDOM_POOL - CONFIG_NO_WPA - CONFIG_NO_PBKDF2 CONFIG_SHA256 CONFIG_CTRL_IFACE_ZEPHYR CONFIG_SUITEB192 @@ -56,6 +54,10 @@ zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_RRM CONFIG_RRM ) +zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_ROBUST_AV + CONFIG_ROBUST_AV +) + zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_MBO CONFIG_MBO ) @@ -98,8 +100,6 @@ zephyr_library_sources( ${HOSTAP_SRC_BASE}/utils/eloop.c ${HOSTAP_SRC_BASE}/utils/os_zephyr.c ${HOSTAP_SRC_BASE}/utils/wpa_debug_zephyr.c - ${HOSTAP_SRC_BASE}/crypto/crypto_none.c - ${HOSTAP_SRC_BASE}/crypto/tls_none.c ${HOSTAP_SRC_BASE}/l2_packet/l2_packet_zephyr.c ${HOSTAP_SRC_BASE}/drivers/driver_zephyr.c @@ -128,20 +128,20 @@ zephyr_library_sources( # Advanced features zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_RRM - ${WPA_SUPPLICANT_BASE}/op_classes.c - ${WPA_SUPPLICANT_BASE}/rrm.c + ${WIFI_NM_WPA_SUPPLICANT_BASE}/op_classes.c + ${WIFI_NM_WPA_SUPPLICANT_BASE}/rrm.c ) zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_WMM_AC - ${WPA_SUPPLICANT_BASE}/wmm_ac.c + ${WIFI_NM_WPA_SUPPLICANT_BASE}/wmm_ac.c ) zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_ROBUST_AV - ${WPA_SUPPLICANT_BASE}/robust_av.c + ${WIFI_NM_WPA_SUPPLICANT_BASE}/robust_av.c ) zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_MBO - ${WPA_SUPPLICANT_BASE}/mbo.c + ${WIFI_NM_WPA_SUPPLICANT_BASE}/mbo.c ) zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM - ${WPA_SUPPLICANT_BASE}/wnm_sta.c + ${WIFI_NM_WPA_SUPPLICANT_BASE}/wnm_sta.c ) zephyr_library_sources_ifdef(CONFIG_WPA_CLI @@ -206,21 +206,21 @@ zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_AP ) -zephyr_library_sources_ifndef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO +zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE ${HOSTAP_SRC_BASE}/crypto/crypto_none.c ${HOSTAP_SRC_BASE}/crypto/tls_none.c ) -zephyr_library_compile_definitions_ifndef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO +zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE CONFIG_NO_WPA CONFIG_CRYPTO_INTERNAL ) -zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO +zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_WEP CONFIG_WEP ) -zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO +zephyr_library_sources_ifndef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE ${HOSTAP_SRC_BASE}/common/wpa_common.c ${HOSTAP_SRC_BASE}/rsn_supp/wpa.c ${HOSTAP_SRC_BASE}/rsn_supp/preauth.c @@ -238,10 +238,6 @@ zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO ${HOSTAP_SRC_BASE}/crypto/sha384-prf.c ) -zephyr_library_sources_ifndef(CONFIG_WPA_SUPP_CRYPTO_ENTERPRISE - ${COMMON_SRC_BASE}/crypto/tls_none.c -) - zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_WPA3 ${HOSTAP_SRC_BASE}/common/sae.c ${HOSTAP_SRC_BASE}/common/dragonfly.c @@ -255,10 +251,13 @@ zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_WPA3 CONFIG_ECC ) -zephyr_library_include_directories_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO +zephyr_library_include_directories_ifndef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE ${CMAKE_SOURCE_DIR} ) +zephyr_library_link_libraries_ifndef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE + mbedTLS) + zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_P2P ${WIFI_NM_WPA_SUPPLICANT_BASE}/p2p_supplicant.c ${WIFI_NM_WPA_SUPPLICANT_BASE}/p2p_supplicant_sd.c @@ -312,9 +311,9 @@ zephyr_library_sources_ifndef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE ${HOSTAP_SRC_BASE}/rsn_supp/preauth.c ${HOSTAP_SRC_BASE}/rsn_supp/wpa_ie.c -# ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls-bignum.c -# ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls-ec.c -# ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls.c + ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls-bignum.c + ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls-ec.c + ${HOSTAP_SRC_BASE}/crypto/crypto_mbedtls.c ${HOSTAP_SRC_BASE}/crypto/aes-wrap.c ${HOSTAP_SRC_BASE}/crypto/aes-unwrap.c ${HOSTAP_SRC_BASE}/crypto/rc4.c diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 02653066959..10b9bf2fb76 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -10,9 +10,7 @@ menuconfig WIFI_NM_WPA_SUPPLICANT select POSIX_CLOCK select POSIX_SIGNAL select POSIX_API -# depends on !POSIX_API select NET_SOCKETS -# select NET_SOCKETS_POSIX_NAMES select NET_SOCKETS_PACKET select NET_SOCKETPAIR select NET_L2_WIFI_MGMT @@ -97,9 +95,8 @@ config WIFI_NM_WPA_SUPPLICANT_WEP choice WIFI_NM_WPA_SUPPLICANT_CRYPTO_BACKEND prompt "WPA supplicant crypto implementation" - default WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE default WIFI_NM_WPA_SUPPLICANT_CRYPTO_PSA if BUILD_WITH_TFM - default WIFI_NM_WPA_SUPPLICANT_CRYPTO if !BUILD_WITH_TFM + default WIFI_NM_WPA_SUPPLICANT_CRYPTO_LEGACY_BUILTIN if !BUILD_WITH_TFM help Select the crypto implementation to use for WPA supplicant. @@ -136,8 +133,6 @@ config WIFI_NM_WPA_SUPPLICANT_CRYPTO_PSA select MBEDTLS_ECP_C select MBEDTLS_CTR_DRBG_C select MBEDTLS_KEY_EXCHANGE_ALL_ENABLED - select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED - select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED config WIFI_NM_WPA_SUPPLICANT_CRYPTO_LEGACY_BUILTIN bool "Legacy Crypto support for WiFi" @@ -149,6 +144,12 @@ config WIFI_NM_WPA_SUPPLICANT_CRYPTO_LEGACY_BUILTIN select MBEDTLS_ECP_ALL_ENABLED select MBEDTLS_PKCS5_C select MBEDTLS_MAC_CMAC_ENABLED +# select MBEDTLS_CIPHER_MODE_CBC +# select MBEDTLS_CIPHER_MODE_CTR +# select MBEDTLS_LEGACY_CRYPTO_C +# select MBEDTLS_CTR_DRBG_C +# select MBEDTLS_PK_WRITE_C +# select MBEDTLS_KEY_EXCHANGE_ALL_ENABLED config WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE bool "No Crypto support for WiFi" @@ -370,4 +371,17 @@ config WPA_CRYPTO config WPA_SUPP_CRYPTO bool +config ROBUST_AV + bool + default y + depends on WIFI_NM_WPA_SUPPLICANT_ROBUST_AV + +config RRM + bool + default y + depends on WIFI_NM_WPA_SUPPLICANT_RRM + +config WMM_AC + bool + endif # WIFI_NM_WPA_SUPPLICANT From 57b4ff137d9981a5a461faf588d2731d0ca497ce Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 28 Feb 2024 11:33:51 +0200 Subject: [PATCH 1029/2402] hostap: Replace menuconfig by config This avoid compliance warning Found pointless 'menuconfig' symbols without children. Use regular 'config' symbols instead. See https://docs.zephyrproject.org/latest/build/kconfig/tips.html#menuconfig-symbols. WIFI_NM_WPA_SUPPLICANT modules/hostap/Kconfig:8 WIFI_NM_WPA_SUPPLICANT modules/hostap/Kconfig:8 Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 10b9bf2fb76..eda27e30b38 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -5,7 +5,7 @@ # SPDX-License-Identifier: Apache-2.0 # -menuconfig WIFI_NM_WPA_SUPPLICANT +config WIFI_NM_WPA_SUPPLICANT bool "WPA Suplicant from hostap project [EXPERIMENTAL]" select POSIX_CLOCK select POSIX_SIGNAL @@ -19,6 +19,8 @@ menuconfig WIFI_NM_WPA_SUPPLICANT help WPA supplicant as a network management backend for WIFI_NM. +if WIFI_NM_WPA_SUPPLICANT + config WIFI_NM_WPA_SUPPLICANT_THREAD_STACK_SIZE int "Stack size for wpa_supplicant thread" default 8192 @@ -59,8 +61,6 @@ config WIFI_NM_WPA_SUPPLICANT_DEBUG_LEVEL runtime filtering can also be configured in addition to the compile-time filtering. -if WIFI_NM_WPA_SUPPLICANT - # Memory optimizations config WIFI_NM_WPA_SUPPLICANT_ADVANCED_FEATURES bool "Advanced features" From d5dd3a0a5483df1aeb6a8c3287fa345624065683 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 28 Feb 2024 11:36:12 +0200 Subject: [PATCH 1030/2402] hostap: Remove PSA crypto support The PSA is referring to Kconfig symbols that are only found in Nordic downstream repo so we cannot use it anyway atm. Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 41 +++-------------------------------------- 1 file changed, 3 insertions(+), 38 deletions(-) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index eda27e30b38..472857caf12 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -95,47 +95,12 @@ config WIFI_NM_WPA_SUPPLICANT_WEP choice WIFI_NM_WPA_SUPPLICANT_CRYPTO_BACKEND prompt "WPA supplicant crypto implementation" - default WIFI_NM_WPA_SUPPLICANT_CRYPTO_PSA if BUILD_WITH_TFM - default WIFI_NM_WPA_SUPPLICANT_CRYPTO_LEGACY_BUILTIN if !BUILD_WITH_TFM + default WIFI_NM_WPA_SUPPLICANT_CRYPTO help Select the crypto implementation to use for WPA supplicant. -# To easily manage the crypto dependencies we separate the crypto -# implementations into two Kconfig options. One for the legacy crypto -# and one for the PSA crypto. -config WIFI_NM_WPA_SUPPLICANT_CRYPTO_PSA - bool "PSA Crypto support for WiFi" - select WIFI_NM_WPA_SUPPLICANT_WEP - select PSA_WANT_KEY_TYPE_AES - select PSA_WANT_ALG_CMAC - select PSA_WANT_ALG_CBC_PKCS7 - select PSA_WANT_ALG_CTR - select PSA_WANT_ALG_ECDSA - select PSA_WANT_GENERATE_RANDOM - select PSA_WANT_ALG_RSA_PSS - select PSA_WANT_ALG_DETERMINISTIC_ECDSA - select PSA_WANT_ALG_SHA_512 - select PSA_WANT_ALG_SHA_1 - select PSA_WANT_KEY_TYPE_RSA_KEY_PAIR - select PSA_WANT_ECC_SECP_R1_256 - # Legacy crypto, still needed - select MBEDTLS - select MBEDTLS_CMAC_C - select MBEDTLS_GCM_C - select MBEDTLS_TLS_LIBRARY - select MBEDTLS_PK_WRITE_C - select MBEDTLS_X509_LIBRARY - select MBEDTLS_X509_CRT_PARSE_C - select MBEDTLS_CIPHER_C - select MBEDTLS_CIPHER_MODE_CTR - select MBEDTLS_CIPHER_MODE_CBC - select MBEDTLS_SSL_TLS_C - select MBEDTLS_ECP_C - select MBEDTLS_CTR_DRBG_C - select MBEDTLS_KEY_EXCHANGE_ALL_ENABLED - -config WIFI_NM_WPA_SUPPLICANT_CRYPTO_LEGACY_BUILTIN - bool "Legacy Crypto support for WiFi" +config WIFI_NM_WPA_SUPPLICANT_CRYPTO + bool "Crypto support for WiFi" select MBEDTLS select MBEDTLS_CIPHER_MODE_CTR_ENABLED select MBEDTLS_CIPHER_MODE_CBC_ENABLED From b8e5ac18f18def9bc3fac59aa5372f1517660264 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 16 Feb 2024 17:17:04 +0200 Subject: [PATCH 1031/2402] manifest: Update to proper hostap Hostap changes from Nordic downstream. Signed-off-by: Jukka Rissanen --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 6136fd8638a..6d9f3fa1481 100644 --- a/west.yml +++ b/west.yml @@ -256,7 +256,7 @@ manifest: - name: hostap repo-path: hostap path: modules/lib/hostap - revision: dee924caf7218d0ee2c2698c217559b1292a46d0 + revision: 9ad92f5249a6743f55787bb783d3398113b136c0 - name: libmetal revision: 243eed541b9c211a2ce8841c788e62ddce84425e path: modules/hal/libmetal From 5eb045dc837a9db07318ccba7246845ce24c2c16 Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Fri, 23 Feb 2024 14:22:58 +0100 Subject: [PATCH 1032/2402] tests: drivers: adc: adc_api: add dma test Move ADC DMA tests directly into adc_api test for Kinetis and STM32 boards. Needs to disable CONFIG_TEST_USERSPACE for this subtest because of caching issue for STM32H7 (as it was done dor adc_dma test). Signed-off-by: Guillaume Gautier --- tests/drivers/adc/adc_api/Kconfig | 12 ++++++ .../adc/adc_api/boards/frdm_k64f.overlay | 13 ++++++ .../adc/adc_api/boards/frdm_k82f.overlay | 13 ++++++ .../adc/adc_api/boards/nucleo_f401re.overlay | 8 ++++ .../adc/adc_api/boards/nucleo_h743zi.conf | 1 + .../adc/adc_api/boards/nucleo_h743zi.overlay | 22 ++++++++++ .../adc/adc_api/boards/nucleo_l476rg.overlay | 7 ++++ .../adc_api/boards/nucleo_u575zi_q.overlay | 7 ++++ .../adc/adc_api/overlay-dma-kinetis.conf | 13 ++++++ .../adc/adc_api/overlay-dma-stm32.conf | 8 ++++ tests/drivers/adc/adc_api/src/test_adc.c | 41 ++++++++++++++++++- tests/drivers/adc/adc_api/testcase.yaml | 26 +++++++++++- 12 files changed, 168 insertions(+), 3 deletions(-) create mode 100644 tests/drivers/adc/adc_api/Kconfig create mode 100644 tests/drivers/adc/adc_api/boards/nucleo_h743zi.conf create mode 100644 tests/drivers/adc/adc_api/overlay-dma-kinetis.conf create mode 100644 tests/drivers/adc/adc_api/overlay-dma-stm32.conf diff --git a/tests/drivers/adc/adc_api/Kconfig b/tests/drivers/adc/adc_api/Kconfig new file mode 100644 index 00000000000..5807a1c155f --- /dev/null +++ b/tests/drivers/adc/adc_api/Kconfig @@ -0,0 +1,12 @@ +# ADC API test configuration options + +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +mainmenu "ADC API Test" + +source "Kconfig.zephyr" + +config ADC_API_SAMPLE_INTERVAL_US + int "Interval between repeatead samples in us" + default 0 diff --git a/tests/drivers/adc/adc_api/boards/frdm_k64f.overlay b/tests/drivers/adc/adc_api/boards/frdm_k64f.overlay index 133796bdd48..515f024aa12 100644 --- a/tests/drivers/adc/adc_api/boards/frdm_k64f.overlay +++ b/tests/drivers/adc/adc_api/boards/frdm_k64f.overlay @@ -13,6 +13,11 @@ &adc0 { #address-cells = <1>; #size-cells = <0>; + clk-source = <0>; + hw-trigger-src = <4>; + continuous-convert; + high-speed; + periodic-trigger; status = "okay"; channel@e { @@ -23,3 +28,11 @@ zephyr,resolution = <12>; }; }; + +test_counter: &pit0_channel0 { + status = "okay"; +}; + +&edma0 { + dma-buf-addr-alignment = <4>; +}; diff --git a/tests/drivers/adc/adc_api/boards/frdm_k82f.overlay b/tests/drivers/adc/adc_api/boards/frdm_k82f.overlay index 6123508222b..bf918e836d1 100644 --- a/tests/drivers/adc/adc_api/boards/frdm_k82f.overlay +++ b/tests/drivers/adc/adc_api/boards/frdm_k82f.overlay @@ -13,6 +13,11 @@ &adc0 { #address-cells = <1>; #size-cells = <0>; + clk-source = <0>; + hw-trigger-src = <4>; + continuous-convert; + high-speed; + periodic-trigger; status = "okay"; channel@f { @@ -23,3 +28,11 @@ zephyr,resolution = <12>; }; }; + +test_counter: &pit0_channel0 { + status = "okay"; +}; + +&edma0 { + dma-buf-addr-alignment = <4>; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_f401re.overlay b/tests/drivers/adc/adc_api/boards/nucleo_f401re.overlay index ebb788c73b7..75e74d1e58e 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_f401re.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_f401re.overlay @@ -12,6 +12,10 @@ }; &adc1 { + dmas = <&dma2 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | + STM32_DMA_PERIPH_16BITS) STM32_DMA_FIFO_FULL>; + dma-names = "dma"; + pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1>; #address-cells = <1>; #size-cells = <0>; @@ -32,3 +36,7 @@ zephyr,resolution = <12>; }; }; + +&dma2 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_h743zi.conf b/tests/drivers/adc/adc_api/boards/nucleo_h743zi.conf new file mode 100644 index 00000000000..c448e14811f --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/nucleo_h743zi.conf @@ -0,0 +1 @@ +CONFIG_NOCACHE_MEMORY=y diff --git a/tests/drivers/adc/adc_api/boards/nucleo_h743zi.overlay b/tests/drivers/adc/adc_api/boards/nucleo_h743zi.overlay index bccc2ff8016..7d7ff39af70 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_h743zi.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_h743zi.overlay @@ -4,6 +4,8 @@ * Copyright (c) Benjamin Björnsson */ +#include + / { zephyr,user { /* adjust channel number according to pinmux in board.dts */ @@ -11,7 +13,15 @@ }; }; +&sram2 { + zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >; +}; + &adc1 { + dmas = <&dmamux1 0 9 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | + STM32_DMA_PERIPH_16BITS)>; + dma-names = "dmamux"; + #address-cells = <1>; #size-cells = <0>; @@ -31,3 +41,15 @@ zephyr,resolution = <16>; }; }; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_l476rg.overlay b/tests/drivers/adc/adc_api/boards/nucleo_l476rg.overlay index 3ac9ae1b77b..96603bab0b2 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_l476rg.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_l476rg.overlay @@ -12,6 +12,9 @@ }; &adc1 { + dmas = <&dma1 1 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dma-names = "dma"; + #address-cells = <1>; #size-cells = <0>; @@ -23,3 +26,7 @@ zephyr,resolution = <10>; }; }; + +&dma1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_u575zi_q.overlay b/tests/drivers/adc/adc_api/boards/nucleo_u575zi_q.overlay index 33fbcb51723..3b49f0af403 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_u575zi_q.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_u575zi_q.overlay @@ -12,6 +12,9 @@ }; &adc1 { + dmas = <&gpdma1 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dma-names = "gpdma"; + #address-cells = <1>; #size-cells = <0>; @@ -23,3 +26,7 @@ zephyr,resolution = <12>; }; }; + +&gpdma1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/overlay-dma-kinetis.conf b/tests/drivers/adc/adc_api/overlay-dma-kinetis.conf new file mode 100644 index 00000000000..f8db1824c20 --- /dev/null +++ b/tests/drivers/adc/adc_api/overlay-dma-kinetis.conf @@ -0,0 +1,13 @@ +# +# Copyright (c) 2020, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_TEST_USERSPACE=n +CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA=y +CONFIG_ADC_MCUX_ADC16_HW_TRIGGER=y +CONFIG_COUNTER=y +CONFIG_ADC_ASYNC=y +CONFIG_DMA=y +CONFIG_ADC_API_SAMPLE_INTERVAL_US=30000 diff --git a/tests/drivers/adc/adc_api/overlay-dma-stm32.conf b/tests/drivers/adc/adc_api/overlay-dma-stm32.conf new file mode 100644 index 00000000000..2ba3e6f898b --- /dev/null +++ b/tests/drivers/adc/adc_api/overlay-dma-stm32.conf @@ -0,0 +1,8 @@ +# +# Copyright (c) 2024 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_TEST_USERSPACE=n +CONFIG_ADC_STM32_DMA=y diff --git a/tests/drivers/adc/adc_api/src/test_adc.c b/tests/drivers/adc/adc_api/src/test_adc.c index 250982b1d69..f1c62ed7624 100644 --- a/tests/drivers/adc/adc_api/src/test_adc.c +++ b/tests/drivers/adc/adc_api/src/test_adc.c @@ -7,6 +7,8 @@ #include +#include +#include #include #include @@ -18,8 +20,18 @@ #define INVALID_ADC_VALUE SHRT_MIN #endif +#if CONFIG_NOCACHE_MEMORY +#define __NOCACHE __attribute__((__section__(".nocache"))) +#else /* CONFIG_NOCACHE_MEMORY */ +#define __NOCACHE +#endif /* CONFIG_NOCACHE_MEMORY */ + #define BUFFER_SIZE 6 +#ifdef CONFIG_TEST_USERSPACE static ZTEST_BMEM int16_t m_sample_buffer[BUFFER_SIZE]; +#else +static __aligned(32) int16_t m_sample_buffer[BUFFER_SIZE] __NOCACHE; +#endif #define DT_SPEC_AND_COMMA(node_id, prop, idx) ADC_DT_SPEC_GET_BY_IDX(node_id, idx), @@ -43,6 +55,26 @@ const struct device *get_adc_device(void) return adc_channels[0].dev; } +#if DT_NODE_HAS_STATUS(DT_NODELABEL(test_counter), okay) && \ + defined(CONFIG_COUNTER) +static void init_counter(void) +{ + int err; + const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(test_counter)); + struct counter_top_cfg top_cfg = { .callback = NULL, + .user_data = NULL, + .flags = 0 }; + + zassert_true(device_is_ready(dev), "Counter device is not ready"); + + counter_start(dev); + top_cfg.ticks = counter_us_to_ticks(dev, CONFIG_ADC_API_SAMPLE_INTERVAL_US); + err = counter_set_top_value(dev, &top_cfg); + zassert_equal(0, err, "%s: Counter failed to set top value (err: %d)", + dev->name, err); +} +#endif + static void init_adc(void) { int i, ret; @@ -57,6 +89,11 @@ static void init_adc(void) for (i = 0; i < BUFFER_SIZE; ++i) { m_sample_buffer[i] = INVALID_ADC_VALUE; } + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(test_counter), okay) && \ + defined(CONFIG_COUNTER) + init_counter(); +#endif } static void check_samples(int expected_count) @@ -156,7 +193,7 @@ static int test_task_asynchronous_call(void) const struct adc_sequence_options options = { .extra_samplings = 4, /* Start consecutive samplings as fast as possible. */ - .interval_us = 0, + .interval_us = CONFIG_ADC_API_SAMPLE_INTERVAL_US, }; struct adc_sequence sequence = { .options = &options, @@ -295,7 +332,7 @@ static int test_task_repeated_samplings(void) */ .extra_samplings = 2, /* Start consecutive samplings as fast as possible. */ - .interval_us = 0, + .interval_us = CONFIG_ADC_API_SAMPLE_INTERVAL_US, }; struct adc_sequence sequence = { .options = &options, diff --git a/tests/drivers/adc/adc_api/testcase.yaml b/tests/drivers/adc/adc_api/testcase.yaml index 5e8217cb2c3..8d6af2c8ead 100644 --- a/tests/drivers/adc/adc_api/testcase.yaml +++ b/tests/drivers/adc/adc_api/testcase.yaml @@ -9,6 +9,30 @@ tests: min_flash: 40 drivers.adc.b_u585i_iot02a_adc4: extra_args: - DTC_OVERLAY_FILE="boards/b_u585i_iot02a_adc4.overlay" + - DTC_OVERLAY_FILE="boards/b_u585i_iot02a_adc4.overlay" platform_allow: - b_u585i_iot02a + drivers.adc.dma_st_stm32: + extra_args: + - OVERLAY_CONFIG="overlay-dma-stm32.conf" + depends_on: + - adc + - dma + min_flash: 40 + platform_allow: + - nucleo_f401re + - nucleo_h743zi + - nucleo_l476rg + - nucleo_u575zi_q + drivers.adc.dma_nxp_kinetis: + extra_args: + - OVERLAY_CONFIG="overlay-dma-kinetis.conf" + depends_on: + - adc + - dma + min_flash: 40 + platform_allow: + - frdm_k64f + - frdm_k82f + integration_platforms: + - frdm_k82f From 4102d3c452e891fda0ced538bf771dfac76e40e0 Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Wed, 28 Feb 2024 08:40:39 +0100 Subject: [PATCH 1033/2402] tests: drivers: adc: remove adc_dma test adc_dma test is now redundant with adc_api test, so it can be removed. Signed-off-by: Guillaume Gautier --- tests/drivers/adc/adc_dma/CMakeLists.txt | 9 - .../drivers/adc/adc_dma/boards/frdm_k64f.conf | 10 - .../adc/adc_dma/boards/frdm_k64f.overlay | 22 - .../drivers/adc/adc_dma/boards/frdm_k82f.conf | 10 - .../adc/adc_dma/boards/frdm_k82f.overlay | 22 - .../adc/adc_dma/boards/nucleo_f401re.conf | 8 - .../adc/adc_dma/boards/nucleo_f401re.overlay | 35 -- .../adc/adc_dma/boards/nucleo_h743zi.conf | 8 - .../adc/adc_dma/boards/nucleo_h743zi.overlay | 37 -- .../adc/adc_dma/boards/nucleo_l476rg.conf | 8 - .../adc/adc_dma/boards/nucleo_l476rg.overlay | 17 - .../adc/adc_dma/boards/nucleo_u575zi_q.conf | 8 - .../adc_dma/boards/nucleo_u575zi_q.overlay | 26 - tests/drivers/adc/adc_dma/prj.conf | 5 - tests/drivers/adc/adc_dma/src/main.c | 11 - tests/drivers/adc/adc_dma/src/test_adc.c | 555 ------------------ tests/drivers/adc/adc_dma/testcase.yaml | 19 - 17 files changed, 810 deletions(-) delete mode 100644 tests/drivers/adc/adc_dma/CMakeLists.txt delete mode 100644 tests/drivers/adc/adc_dma/boards/frdm_k64f.conf delete mode 100644 tests/drivers/adc/adc_dma/boards/frdm_k64f.overlay delete mode 100644 tests/drivers/adc/adc_dma/boards/frdm_k82f.conf delete mode 100644 tests/drivers/adc/adc_dma/boards/frdm_k82f.overlay delete mode 100644 tests/drivers/adc/adc_dma/boards/nucleo_f401re.conf delete mode 100644 tests/drivers/adc/adc_dma/boards/nucleo_f401re.overlay delete mode 100644 tests/drivers/adc/adc_dma/boards/nucleo_h743zi.conf delete mode 100644 tests/drivers/adc/adc_dma/boards/nucleo_h743zi.overlay delete mode 100644 tests/drivers/adc/adc_dma/boards/nucleo_l476rg.conf delete mode 100644 tests/drivers/adc/adc_dma/boards/nucleo_l476rg.overlay delete mode 100644 tests/drivers/adc/adc_dma/boards/nucleo_u575zi_q.conf delete mode 100644 tests/drivers/adc/adc_dma/boards/nucleo_u575zi_q.overlay delete mode 100644 tests/drivers/adc/adc_dma/prj.conf delete mode 100644 tests/drivers/adc/adc_dma/src/main.c delete mode 100644 tests/drivers/adc/adc_dma/src/test_adc.c delete mode 100644 tests/drivers/adc/adc_dma/testcase.yaml diff --git a/tests/drivers/adc/adc_dma/CMakeLists.txt b/tests/drivers/adc/adc_dma/CMakeLists.txt deleted file mode 100644 index 0f0e44fef50..00000000000 --- a/tests/drivers/adc/adc_dma/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(adc_dma) - -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/adc/adc_dma/boards/frdm_k64f.conf b/tests/drivers/adc/adc_dma/boards/frdm_k64f.conf deleted file mode 100644 index a0c2eeaa0db..00000000000 --- a/tests/drivers/adc/adc_dma/boards/frdm_k64f.conf +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) 2020, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA=y -CONFIG_ADC_MCUX_ADC16_HW_TRIGGER=y -CONFIG_COUNTER=y -CONFIG_ADC_ASYNC=y diff --git a/tests/drivers/adc/adc_dma/boards/frdm_k64f.overlay b/tests/drivers/adc/adc_dma/boards/frdm_k64f.overlay deleted file mode 100644 index 9de772a5b98..00000000000 --- a/tests/drivers/adc/adc_dma/boards/frdm_k64f.overlay +++ /dev/null @@ -1,22 +0,0 @@ -/* -* Copyright (c) 2020, NXP -* -* SPDX-License-Identifier: Apache-2.0 -*/ -&adc0 { - clk-source = <0>; - hw-trigger-src = <4>; - continuous-convert; - high-speed; - periodic-trigger; -}; - -&edma0 { - dma-buf-addr-alignment = <4>; -}; - -&pit0_channel0 { - status = "okay"; -}; - -test_dma: &edma0 { }; diff --git a/tests/drivers/adc/adc_dma/boards/frdm_k82f.conf b/tests/drivers/adc/adc_dma/boards/frdm_k82f.conf deleted file mode 100644 index a0c2eeaa0db..00000000000 --- a/tests/drivers/adc/adc_dma/boards/frdm_k82f.conf +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) 2020, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA=y -CONFIG_ADC_MCUX_ADC16_HW_TRIGGER=y -CONFIG_COUNTER=y -CONFIG_ADC_ASYNC=y diff --git a/tests/drivers/adc/adc_dma/boards/frdm_k82f.overlay b/tests/drivers/adc/adc_dma/boards/frdm_k82f.overlay deleted file mode 100644 index b2250c934ef..00000000000 --- a/tests/drivers/adc/adc_dma/boards/frdm_k82f.overlay +++ /dev/null @@ -1,22 +0,0 @@ -/* -* Copyright (c) 2020, NXP -* -* SPDX-License-Identifier: Apache-2.0 -*/ -&adc0 { - clk-source = <0>; - hw-trigger-src = <4>; - continuous-convert; - high-speed; - periodic-trigger; -}; - -&edma0 { - dma-buf-addr-alignment = <4>; -}; - -&pit0_channel0 { - status = "okay"; -}; - -test_dma: &edma0 { }; diff --git a/tests/drivers/adc/adc_dma/boards/nucleo_f401re.conf b/tests/drivers/adc/adc_dma/boards/nucleo_f401re.conf deleted file mode 100644 index 84de9de3807..00000000000 --- a/tests/drivers/adc/adc_dma/boards/nucleo_f401re.conf +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2024 STMicroelectronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_ADC_STM32_DMA=y -CONFIG_ADC_ASYNC=y diff --git a/tests/drivers/adc/adc_dma/boards/nucleo_f401re.overlay b/tests/drivers/adc/adc_dma/boards/nucleo_f401re.overlay deleted file mode 100644 index d2cfa562c62..00000000000 --- a/tests/drivers/adc/adc_dma/boards/nucleo_f401re.overlay +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2024 STMicroelectronics - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&adc1 { - dmas = <&dma2 0 0 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC | - STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS) 0x03>; - dma-names = "dma"; - - pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; - - channel@1 { - reg = <1>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; -}; - -test_dma: &dma2 { - status = "okay"; -}; diff --git a/tests/drivers/adc/adc_dma/boards/nucleo_h743zi.conf b/tests/drivers/adc/adc_dma/boards/nucleo_h743zi.conf deleted file mode 100644 index 675ebf0d5aa..00000000000 --- a/tests/drivers/adc/adc_dma/boards/nucleo_h743zi.conf +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2023 Nobleo Technology -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_ADC_STM32_DMA=y -CONFIG_ADC_ASYNC=y diff --git a/tests/drivers/adc/adc_dma/boards/nucleo_h743zi.overlay b/tests/drivers/adc/adc_dma/boards/nucleo_h743zi.overlay deleted file mode 100644 index fdedd2a4635..00000000000 --- a/tests/drivers/adc/adc_dma/boards/nucleo_h743zi.overlay +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2023 Nobleo Technology - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&adc1 { - dmas = < &dmamux1 0 9 (STM32_DMA_PERIPH_TO_MEMORY | - STM32_DMA_MEM_INC | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS) >; - dma-names = "dmamux"; - - #address-cells = <1>; - #size-cells = <0>; - - channel@1 { - reg = <1>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; -}; - -/* ADC driver expects a buffer in a non-cachable memory region */ -&sram4 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; -}; - -&dma1 { - status = "okay"; -}; - -test_dma: &dmamux1 { - status = "okay"; -}; diff --git a/tests/drivers/adc/adc_dma/boards/nucleo_l476rg.conf b/tests/drivers/adc/adc_dma/boards/nucleo_l476rg.conf deleted file mode 100644 index e3fe93c1c0c..00000000000 --- a/tests/drivers/adc/adc_dma/boards/nucleo_l476rg.conf +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2023 Hein Wessels, Nobleo Technology -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_ADC_STM32_DMA=y -CONFIG_ADC_ASYNC=y diff --git a/tests/drivers/adc/adc_dma/boards/nucleo_l476rg.overlay b/tests/drivers/adc/adc_dma/boards/nucleo_l476rg.overlay deleted file mode 100644 index 990a83f351b..00000000000 --- a/tests/drivers/adc/adc_dma/boards/nucleo_l476rg.overlay +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2023 Hein Wessels, Nobleo Technology - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&adc1 { - dmas = < &dma1 1 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS) >; - dma-names = "dma"; - - #address-cells = <1>; - #size-cells = <0>; -}; - -test_dma: &dma1 { - status = "okay"; -}; diff --git a/tests/drivers/adc/adc_dma/boards/nucleo_u575zi_q.conf b/tests/drivers/adc/adc_dma/boards/nucleo_u575zi_q.conf deleted file mode 100644 index 0203963c25c..00000000000 --- a/tests/drivers/adc/adc_dma/boards/nucleo_u575zi_q.conf +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2023 Brett Witherspoon -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_ADC_STM32_DMA=y -CONFIG_ADC_ASYNC=y diff --git a/tests/drivers/adc/adc_dma/boards/nucleo_u575zi_q.overlay b/tests/drivers/adc/adc_dma/boards/nucleo_u575zi_q.overlay deleted file mode 100644 index e884dbc072a..00000000000 --- a/tests/drivers/adc/adc_dma/boards/nucleo_u575zi_q.overlay +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2023 Brett Witherspoon - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&adc1 { - dmas = <&gpdma1 0 0 (STM32_DMA_PERIPH_TO_MEMORY | - STM32_DMA_MEM_INC | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS) >; - dma-names = "dmamux"; - - #address-cells = <1>; - #size-cells = <0>; - - channel@1 { - reg = <1>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; -}; - -test_dma: &gpdma1 { - status = "okay"; -}; diff --git a/tests/drivers/adc/adc_dma/prj.conf b/tests/drivers/adc/adc_dma/prj.conf deleted file mode 100644 index e2b567f4bd8..00000000000 --- a/tests/drivers/adc/adc_dma/prj.conf +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_ZTEST=y - -CONFIG_ADC=y -CONFIG_ADC_LOG_LEVEL_INF=y -CONFIG_DMA=y diff --git a/tests/drivers/adc/adc_dma/src/main.c b/tests/drivers/adc/adc_dma/src/main.c deleted file mode 100644 index 2e968001c97..00000000000 --- a/tests/drivers/adc/adc_dma/src/main.c +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2020, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#include -#include - -ZTEST_SUITE(adc_dma, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/drivers/adc/adc_dma/src/test_adc.c b/tests/drivers/adc/adc_dma/src/test_adc.c deleted file mode 100644 index 126dc2b3bf5..00000000000 --- a/tests/drivers/adc/adc_dma/src/test_adc.c +++ /dev/null @@ -1,555 +0,0 @@ -/* - * Copyright (c) 2018 Nordic Semiconductor ASA - * Copyright (c) 2016 Intel Corporation - * Copyright (c) 2020, NXP - * Copyright (c) 2023, Nobleo Technology - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#include -#include -#include -#include -#include - -#if defined(CONFIG_BOARD_FRDM_K64F) - -#define ADC_DEVICE_NODE DT_INST(0, nxp_kinetis_adc16) -#define ADC_RESOLUTION 12 -#define ADC_GAIN ADC_GAIN_1 -#define ADC_REFERENCE ADC_REF_INTERNAL -#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT -#define ADC_1ST_CHANNEL_ID 26 -#define COUNTER_NODE_NAME pit0 -#define HW_TRIGGER_INTERVAL (30000U) -#define SAMPLE_INTERVAL_US HW_TRIGGER_INTERVAL - -#elif defined(CONFIG_BOARD_FRDM_K82F) - -#define ADC_DEVICE_NODE DT_INST(0, nxp_kinetis_adc16) -#define ADC_RESOLUTION 12 -#define ADC_GAIN ADC_GAIN_1 -#define ADC_REFERENCE ADC_REF_INTERNAL -#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT -#define ADC_1ST_CHANNEL_ID 26 -#define COUNTER_NODE_NAME pit0 -#define HW_TRIGGER_INTERVAL (30000U) -#define SAMPLE_INTERVAL_US HW_TRIGGER_INTERVAL - -#elif defined(CONFIG_BOARD_NUCLEO_F401RE) - -#define ADC_DEVICE_NODE DT_INST(0, st_stm32_adc) -#define ADC_RESOLUTION 12 -#define ADC_GAIN ADC_GAIN_1 -#define ADC_REFERENCE ADC_REF_INTERNAL -#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_MAX -#define ADC_1ST_CHANNEL_ID 0 -#define ADC_2ND_CHANNEL_ID 1 -#define ALIGNMENT 32 - -#elif defined(CONFIG_BOARD_NUCLEO_H743ZI) - -#define ADC_DEVICE_NODE DT_INST(0, st_stm32_adc) -#define ADC_RESOLUTION 12 -#define ADC_GAIN ADC_GAIN_1 -#define ADC_REFERENCE ADC_REF_INTERNAL -#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT -#define ADC_1ST_CHANNEL_ID 1 -#define ADC_2ND_CHANNEL_ID 7 -#define ALIGNMENT 32 -#define BUFFER_MEM_REGION __attribute__((__section__("SRAM4.dma"))) - -#elif defined(CONFIG_BOARD_NUCLEO_U575ZI_Q) - -#define ADC_DEVICE_NODE DT_INST(0, st_stm32_adc) -#define ADC_RESOLUTION 12 -#define ADC_GAIN ADC_GAIN_1 -#define ADC_REFERENCE ADC_REF_INTERNAL -#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT -#define ADC_1ST_CHANNEL_ID 1 -#define ADC_2ND_CHANNEL_ID 7 -#define ALIGNMENT 32 - -#elif defined(CONFIG_BOARD_NUCLEO_L476RG) - -#define ADC_DEVICE_NODE DT_INST(0, st_stm32_adc) -#define ADC_RESOLUTION 12 -#define ADC_GAIN ADC_GAIN_1 -#define ADC_REFERENCE ADC_REF_INTERNAL -#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT -#define ADC_1ST_CHANNEL_ID 1 -#define ADC_2ND_CHANNEL_ID 7 -#define ALIGNMENT 32 - -#endif - -/* Invalid value that is not supposed to be written by the driver. It is used - * to mark the sample buffer entries as empty. If needed, it can be overridden - * for a particular board by providing a specific definition above. - */ -#if !defined(INVALID_ADC_VALUE) -#define INVALID_ADC_VALUE SHRT_MIN -#endif - -/* Memory region where buffers will be placed. By default placed in ZTEST_BMEM - * but can be overwritten for a particular board. - */ -#if !defined(BUFFER_MEM_REGION) -#define BUFFER_MEM_REGION EMPTY -#endif - -/* The sample interval between consecutive samplings. Some drivers require - * specific values to function. - */ -#if !defined(SAMPLE_INTERVAL_US) -#define SAMPLE_INTERVAL_US 0 -#endif - -#define BUFFER_SIZE 24 -#ifndef ALIGNMENT -#define ALIGNMENT DMA_BUF_ADDR_ALIGNMENT(DT_NODELABEL(test_dma)) -#endif - -static BUFFER_MEM_REGION __aligned(ALIGNMENT) int16_t m_sample_buffer[BUFFER_SIZE]; -static BUFFER_MEM_REGION __aligned(ALIGNMENT) int16_t m_sample_buffer2[2][BUFFER_SIZE]; -static int current_buf_inx; - -#if defined(CONFIG_ADC_ASYNC) -static struct k_poll_signal async_sig; -#endif - -static const struct adc_channel_cfg m_1st_channel_cfg = { - .gain = ADC_GAIN, - .reference = ADC_REFERENCE, - .acquisition_time = ADC_ACQUISITION_TIME, - .channel_id = ADC_1ST_CHANNEL_ID, -#if defined(CONFIG_ADC_CONFIGURABLE_INPUTS) - .input_positive = ADC_1ST_CHANNEL_INPUT, -#endif -}; -#if defined(ADC_2ND_CHANNEL_ID) -static const struct adc_channel_cfg m_2nd_channel_cfg = { - .gain = ADC_GAIN, - .reference = ADC_REFERENCE, - .acquisition_time = ADC_ACQUISITION_TIME, - .channel_id = ADC_2ND_CHANNEL_ID, -#if defined(CONFIG_ADC_CONFIGURABLE_INPUTS) - .input_positive = ADC_2ND_CHANNEL_INPUT, -#endif -}; -#endif /* defined(ADC_2ND_CHANNEL_ID) */ - -#if defined(COUNTER_NODE_NAME) -static void init_counter(void) -{ - int err; - const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(COUNTER_NODE_NAME)); - struct counter_top_cfg top_cfg = { .callback = NULL, - .user_data = NULL, - .flags = 0 }; - - zassert_true(device_is_ready(dev), "Counter device is not ready"); - - counter_start(dev); - top_cfg.ticks = counter_us_to_ticks(dev, HW_TRIGGER_INTERVAL); - err = counter_set_top_value(dev, &top_cfg); - zassert_equal(0, err, "%s: Counter failed to set top value (err: %d)", - dev->name, err); -} -#endif - -static const struct device *init_adc(void) -{ - int i, ret; - const struct device *const adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE); - - zassert_true(device_is_ready(adc_dev), "ADC device is not ready"); - - ret = adc_channel_setup(adc_dev, &m_1st_channel_cfg); - zassert_equal(ret, 0, - "Setting up of the first channel failed with code %d", - ret); - -#if defined(ADC_2ND_CHANNEL_ID) - ret = adc_channel_setup(adc_dev, &m_2nd_channel_cfg); - zassert_equal(ret, 0, - "Setting up of the second channel failed with code %d", - ret); -#endif /* defined(ADC_2ND_CHANNEL_ID) */ - - for (i = 0; i < BUFFER_SIZE; ++i) { - m_sample_buffer[i] = INVALID_ADC_VALUE; - m_sample_buffer2[0][i] = INVALID_ADC_VALUE; - m_sample_buffer2[1][i] = INVALID_ADC_VALUE; - } - -#if defined(CONFIG_ADC_ASYNC) - k_poll_signal_init(&async_sig); -#endif - -#if defined(COUNTER_NODE_NAME) - init_counter(); -#endif - - return adc_dev; -} - -static void check_samples(int expected_count) -{ - int i; - - TC_PRINT("Samples read: "); - for (i = 0; i < BUFFER_SIZE; i++) { - int16_t sample_value = m_sample_buffer[i]; - - TC_PRINT("0x%04x ", sample_value); - if (i && i % 10 == 0) { - TC_PRINT("\n"); - } - - if (i < expected_count) { - zassert_not_equal(INVALID_ADC_VALUE, sample_value, - "[%u] should be filled", i); - } else { - zassert_equal(INVALID_ADC_VALUE, sample_value, - "[%u] should be empty", i); - } - } - TC_PRINT("\n"); -} - -static void check_samples2(int expected_count) -{ - int i; - - TC_PRINT("Samples read: "); - for (i = 0; i < BUFFER_SIZE; i++) { - int16_t sample_value = m_sample_buffer2[current_buf_inx][i]; - - TC_PRINT("0x%04x ", sample_value); - if (i && i % 10 == 0) { - TC_PRINT("\n"); - } - - if (i < expected_count) { - zassert_not_equal(INVALID_ADC_VALUE, sample_value, - "[%u] should be filled", i); - } else { - zassert_equal(INVALID_ADC_VALUE, sample_value, - "[%u] should be empty", i); - } - } - TC_PRINT("\n"); -} - -/* - * test_adc_sample_one_channel - */ -static int test_task_one_channel(void) -{ - int ret; - const struct adc_sequence sequence = { - .channels = BIT(ADC_1ST_CHANNEL_ID), - .buffer = m_sample_buffer, - .buffer_size = sizeof(m_sample_buffer), - .resolution = ADC_RESOLUTION, - }; - - const struct device *adc_dev = init_adc(); - - if (!adc_dev) { - return TC_FAIL; - } - - ret = adc_read(adc_dev, &sequence); - zassert_equal(ret, 0, "adc_read() failed with code %d", ret); - - check_samples(1); - - return TC_PASS; -} - -ZTEST_USER(adc_dma, test_adc_sample_one_channel) -{ - zassert_true(test_task_one_channel() == TC_PASS); -} - -/* - * test_adc_sample_two_channels - */ -#if defined(ADC_2ND_CHANNEL_ID) -static int test_task_two_channels(void) -{ - int ret; - const struct adc_sequence sequence = { - .channels = BIT(ADC_1ST_CHANNEL_ID) | BIT(ADC_2ND_CHANNEL_ID), - .buffer = m_sample_buffer, - .buffer_size = sizeof(m_sample_buffer), - .resolution = ADC_RESOLUTION, - }; - - const struct device *adc_dev = init_adc(); - - if (!adc_dev) { - return TC_FAIL; - } - - ret = adc_read(adc_dev, &sequence); - zassert_equal(ret, 0, "adc_read() failed with code %d", ret); - - check_samples(2); - - return TC_PASS; -} -#endif /* defined(ADC_2ND_CHANNEL_ID) */ - -ZTEST_USER(adc_dma, test_adc_sample_two_channels) -{ -#if defined(ADC_2ND_CHANNEL_ID) - zassert_true(test_task_two_channels() == TC_PASS); -#else - ztest_test_skip(); -#endif /* defined(ADC_2ND_CHANNEL_ID) */ -} - -/* - * test_adc_asynchronous_call - */ -#if defined(CONFIG_ADC_ASYNC) -static int test_task_asynchronous_call(void) -{ - int ret; - const struct adc_sequence_options options = { - .extra_samplings = 4, - /* Start consecutive samplings as fast as possible. */ - .interval_us = SAMPLE_INTERVAL_US, - }; - const struct adc_sequence sequence = { - .options = &options, - .channels = BIT(ADC_1ST_CHANNEL_ID), - .buffer = m_sample_buffer, - .buffer_size = sizeof(m_sample_buffer), - .resolution = ADC_RESOLUTION, - }; - struct k_poll_event async_evt = K_POLL_EVENT_INITIALIZER( - K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &async_sig); - const struct device *adc_dev = init_adc(); - - if (!adc_dev) { - return TC_FAIL; - } - - ret = adc_read_async(adc_dev, &sequence, &async_sig); - zassert_equal(ret, 0, "adc_read_async() failed with code %d", ret); - - ret = k_poll(&async_evt, 1, K_MSEC(1000)); - zassert_equal(ret, 0, "k_poll failed with error %d", ret); - - check_samples(1 + options.extra_samplings); - - return TC_PASS; -} -#endif /* defined(CONFIG_ADC_ASYNC) */ - -ZTEST_USER(adc_dma, test_adc_asynchronous_call) -{ -#if defined(CONFIG_ADC_ASYNC) - zassert_true(test_task_asynchronous_call() == TC_PASS); -#else - ztest_test_skip(); -#endif /* defined(CONFIG_ADC_ASYNC) */ -} - -/* - * test_adc_sample_with_interval - */ -static enum adc_action -sample_with_interval_callback(const struct device *dev, - const struct adc_sequence *sequence, - uint16_t sampling_index) -{ - struct adc_sequence *seq = (struct adc_sequence *)sequence; - int _inx = current_buf_inx; - - memcpy(m_sample_buffer, m_sample_buffer2[_inx], - sizeof(m_sample_buffer)); - current_buf_inx = (current_buf_inx == 0) ? 1 : 0; - seq->buffer = m_sample_buffer2[current_buf_inx]; - return ADC_ACTION_CONTINUE; -} - -static int test_task_with_interval(void) -{ - int ret; - int count = 2; - int64_t time_stamp; - int64_t milliseconds_spent; - - const struct adc_sequence_options options = { - .interval_us = 100 * 1000, /* 10 ms - much larger than expected sampling time */ - .callback = sample_with_interval_callback, - .extra_samplings = 1, - }; - const struct adc_sequence sequence = { - .options = &options, - .channels = BIT(ADC_1ST_CHANNEL_ID), - .buffer = m_sample_buffer2[0], - .buffer_size = sizeof(m_sample_buffer2[0]), - .resolution = ADC_RESOLUTION, - }; - - const struct device *adc_dev = init_adc(); - - if (!adc_dev) { - return TC_FAIL; - } - - current_buf_inx = 0; - - while (count--) { - time_stamp = k_uptime_get(); - ret = adc_read(adc_dev, &sequence); - milliseconds_spent = k_uptime_delta(&time_stamp); - zassert_true(milliseconds_spent >= (options.interval_us / 1000UL)); - zassert_equal(ret, 0, "adc_read() failed with code %d", ret); - } - check_samples2(1 + options.extra_samplings); - return TC_PASS; -} - -ZTEST(adc_dma, test_adc_sample_with_interval) -{ - zassert_true(test_task_with_interval() == TC_PASS); -} - -/* - * test_adc_repeated_samplings - */ -static uint8_t m_samplings_done; -static enum adc_action -repeated_samplings_callback(const struct device *dev, - const struct adc_sequence *sequence, - uint16_t sampling_index) -{ - ++m_samplings_done; - TC_PRINT("%s: done %d\n", __func__, m_samplings_done); - if (m_samplings_done == 1U) { -#if defined(ADC_2ND_CHANNEL_ID) - check_samples(2); -#else - check_samples(1); -#endif /* defined(ADC_2ND_CHANNEL_ID) */ - - /* After first sampling continue normally. */ - return ADC_ACTION_CONTINUE; - } -#if defined(ADC_2ND_CHANNEL_ID) - check_samples(4); -#else - check_samples(2); -#endif /* defined(ADC_2ND_CHANNEL_ID) */ - - /* - * The second sampling is repeated 9 times (the samples are - * written in the same place), then the sequence is finished - * prematurely. - */ - if (m_samplings_done < 10) { - return ADC_ACTION_REPEAT; - } else { - return ADC_ACTION_FINISH; - } - -} - -static int test_task_repeated_samplings(void) -{ - int ret; - const struct adc_sequence_options options = { - .callback = repeated_samplings_callback, - /* - * This specifies that 3 samplings are planned. However, - * the callback function above is constructed in such way - * that the first sampling is done normally, the second one - * is repeated 9 times, and then the sequence is finished. - * Hence, the third sampling will not take place. - */ - .extra_samplings = 2, - /* Start consecutive samplings as fast as possible. */ - .interval_us = SAMPLE_INTERVAL_US, - }; - const struct adc_sequence sequence = { - .options = &options, -#if defined(ADC_2ND_CHANNEL_ID) - .channels = BIT(ADC_1ST_CHANNEL_ID) | BIT(ADC_2ND_CHANNEL_ID), -#else - .channels = BIT(ADC_1ST_CHANNEL_ID), -#endif /* defined(ADC_2ND_CHANNEL_ID) */ - .buffer = m_sample_buffer, - .buffer_size = sizeof(m_sample_buffer), - .resolution = ADC_RESOLUTION, - }; - - const struct device *adc_dev = init_adc(); - - if (!adc_dev) { - return TC_FAIL; - } - - ret = adc_read(adc_dev, &sequence); - zassert_equal(ret, 0, "adc_read() failed with code %d", ret); - - return TC_PASS; -} - -ZTEST(adc_dma, test_adc_repeated_samplings) -{ - zassert_true(test_task_repeated_samplings() == TC_PASS); -} - -/* - * test_adc_invalid_request - */ -static int test_task_invalid_request(void) -{ - int ret; - struct adc_sequence sequence = { - .channels = BIT(ADC_1ST_CHANNEL_ID), - .buffer = m_sample_buffer, - .buffer_size = sizeof(m_sample_buffer), - .resolution = 0, /* intentionally invalid value */ - }; - - const struct device *adc_dev = init_adc(); - - if (!adc_dev) { - return TC_FAIL; - } - - ret = adc_read(adc_dev, &sequence); - zassert_not_equal(ret, 0, "adc_read() unexpectedly succeeded"); - -#if defined(CONFIG_ADC_ASYNC) - ret = adc_read_async(adc_dev, &sequence, &async_sig); - zassert_not_equal(ret, 0, "adc_read_async() unexpectedly succeeded"); -#endif - - /* - * Make the sequence parameters valid, now the request should succeed. - */ - sequence.resolution = ADC_RESOLUTION; - - ret = adc_read(adc_dev, &sequence); - zassert_equal(ret, 0, "adc_read() failed with code %d", ret); - - check_samples(1); - - return TC_PASS; -} - -ZTEST_USER(adc_dma, test_adc_invalid_request) -{ - zassert_true(test_task_invalid_request() == TC_PASS); -} diff --git a/tests/drivers/adc/adc_dma/testcase.yaml b/tests/drivers/adc/adc_dma/testcase.yaml deleted file mode 100644 index 3c5d18e2285..00000000000 --- a/tests/drivers/adc/adc_dma/testcase.yaml +++ /dev/null @@ -1,19 +0,0 @@ -common: - tags: - - adc - - dma - - trigger -tests: - drivers.adc.dma: - depends_on: - - adc - - dma - platform_allow: - - frdm_k82f - - frdm_k64f - - nucleo_f401re - - nucleo_h743zi - - nucleo_u575zi_q - - nucleo_l476rg - integration_platforms: - - frdm_k82f From edbfe9a4c7e2db2f5f96802d1bd791707b873d5c Mon Sep 17 00:00:00 2001 From: Guillaume Gautier Date: Wed, 28 Feb 2024 08:42:04 +0100 Subject: [PATCH 1034/2402] tests: drivers: adc: adc_api: boards: add stm32 boards Add STM32 boards overlays for all series supporting ADC DMA. Signed-off-by: Guillaume Gautier --- .../adc/adc_api/boards/b_u585i_iot02a.overlay | 7 +++++++ .../adc/adc_api/boards/disco_l475_iot1.overlay | 7 +++++++ .../adc/adc_api/boards/nucleo_f091rc.overlay | 7 +++++++ .../adc/adc_api/boards/nucleo_f207zg.overlay | 8 ++++++++ .../adc/adc_api/boards/nucleo_f429zi.overlay | 8 ++++++++ .../adc/adc_api/boards/nucleo_f746zg.overlay | 8 ++++++++ .../adc/adc_api/boards/nucleo_g071rb.overlay | 12 ++++++++++++ .../adc/adc_api/boards/nucleo_g474re.overlay | 12 ++++++++++++ .../adc/adc_api/boards/nucleo_l073rz.overlay | 7 +++++++ .../adc/adc_api/boards/nucleo_l152re.overlay | 7 +++++++ .../adc/adc_api/boards/nucleo_wb55rg.overlay | 12 ++++++++++++ .../adc/adc_api/boards/nucleo_wba52cg.overlay | 7 +++++++ .../adc/adc_api/boards/nucleo_wl55jc.overlay | 12 ++++++++++++ .../adc/adc_api/boards/stm32f3_disco.overlay | 7 +++++++ .../adc/adc_api/boards/stm32h573i_dk.overlay | 7 +++++++ tests/drivers/adc/adc_api/testcase.yaml | 15 +++++++++++++++ 16 files changed, 143 insertions(+) diff --git a/tests/drivers/adc/adc_api/boards/b_u585i_iot02a.overlay b/tests/drivers/adc/adc_api/boards/b_u585i_iot02a.overlay index 90377971a58..d8e3d9dc30d 100644 --- a/tests/drivers/adc/adc_api/boards/b_u585i_iot02a.overlay +++ b/tests/drivers/adc/adc_api/boards/b_u585i_iot02a.overlay @@ -12,6 +12,9 @@ }; &adc1 { + dmas = <&gpdma1 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dma-names = "gpdma"; + pinctrl-0 = <&adc1_in15_pb0 &adc1_in16_pb1>; #address-cells = <1>; #size-cells = <0>; @@ -36,3 +39,7 @@ &adc4 { status = "disabled"; }; + +&gpdma1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/disco_l475_iot1.overlay b/tests/drivers/adc/adc_api/boards/disco_l475_iot1.overlay index 42d8f177261..55d094cd73c 100644 --- a/tests/drivers/adc/adc_api/boards/disco_l475_iot1.overlay +++ b/tests/drivers/adc/adc_api/boards/disco_l475_iot1.overlay @@ -12,6 +12,9 @@ }; &adc1 { + dmas = <&dma1 1 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dma-names = "dma"; + #address-cells = <1>; #size-cells = <0>; @@ -31,3 +34,7 @@ zephyr,resolution = <12>; }; }; + +&dma1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_f091rc.overlay b/tests/drivers/adc/adc_api/boards/nucleo_f091rc.overlay index d8d89d460a0..27c7967d755 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_f091rc.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_f091rc.overlay @@ -12,6 +12,9 @@ }; &adc1 { + dmas = <&dma1 1 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dma-names = "dma"; + pinctrl-0 = <&adc_in0_pa0 &adc_in1_pa1>; #address-cells = <1>; #size-cells = <0>; @@ -32,3 +35,7 @@ zephyr,resolution = <12>; }; }; + +&dma1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_f207zg.overlay b/tests/drivers/adc/adc_api/boards/nucleo_f207zg.overlay index 3f87caeb294..ed807ca3ca6 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_f207zg.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_f207zg.overlay @@ -12,6 +12,10 @@ }; &adc1 { + dmas = <&dma2 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | + STM32_DMA_PERIPH_16BITS) STM32_DMA_FIFO_FULL>; + dma-names = "dma"; + pinctrl-0 = <&adc1_in0_pa0 &adc1_in3_pa3>; #address-cells = <1>; #size-cells = <0>; @@ -32,3 +36,7 @@ zephyr,resolution = <12>; }; }; + +&dma2 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_f429zi.overlay b/tests/drivers/adc/adc_api/boards/nucleo_f429zi.overlay index 3f87caeb294..ed807ca3ca6 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_f429zi.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_f429zi.overlay @@ -12,6 +12,10 @@ }; &adc1 { + dmas = <&dma2 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | + STM32_DMA_PERIPH_16BITS) STM32_DMA_FIFO_FULL>; + dma-names = "dma"; + pinctrl-0 = <&adc1_in0_pa0 &adc1_in3_pa3>; #address-cells = <1>; #size-cells = <0>; @@ -32,3 +36,7 @@ zephyr,resolution = <12>; }; }; + +&dma2 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_f746zg.overlay b/tests/drivers/adc/adc_api/boards/nucleo_f746zg.overlay index 3f87caeb294..ed807ca3ca6 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_f746zg.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_f746zg.overlay @@ -12,6 +12,10 @@ }; &adc1 { + dmas = <&dma2 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | + STM32_DMA_PERIPH_16BITS) STM32_DMA_FIFO_FULL>; + dma-names = "dma"; + pinctrl-0 = <&adc1_in0_pa0 &adc1_in3_pa3>; #address-cells = <1>; #size-cells = <0>; @@ -32,3 +36,7 @@ zephyr,resolution = <12>; }; }; + +&dma2 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_g071rb.overlay b/tests/drivers/adc/adc_api/boards/nucleo_g071rb.overlay index a40478a6ee1..dfc942a6839 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_g071rb.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_g071rb.overlay @@ -12,6 +12,10 @@ }; &adc1 { + dmas = <&dmamux1 0 5 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | + STM32_DMA_PERIPH_16BITS)>; + dma-names = "dmamux"; + #address-cells = <1>; #size-cells = <0>; @@ -31,3 +35,11 @@ zephyr,resolution = <12>; }; }; + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_g474re.overlay b/tests/drivers/adc/adc_api/boards/nucleo_g474re.overlay index 7407481014a..3a95d7a9190 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_g474re.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_g474re.overlay @@ -12,6 +12,10 @@ }; &adc1 { + dmas = <&dmamux1 0 5 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | + STM32_DMA_PERIPH_16BITS)>; + dma-names = "dmamux"; + pinctrl-0 = <&adc1_in1_pa0 &adc1_in2_pa1>; #address-cells = <1>; #size-cells = <0>; @@ -32,3 +36,11 @@ zephyr,resolution = <12>; }; }; + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_l073rz.overlay b/tests/drivers/adc/adc_api/boards/nucleo_l073rz.overlay index d8d89d460a0..f29fa43278e 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_l073rz.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_l073rz.overlay @@ -12,6 +12,9 @@ }; &adc1 { + dmas = <&dma1 1 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dma-names = "dma"; + pinctrl-0 = <&adc_in0_pa0 &adc_in1_pa1>; #address-cells = <1>; #size-cells = <0>; @@ -32,3 +35,7 @@ zephyr,resolution = <12>; }; }; + +&dma1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_l152re.overlay b/tests/drivers/adc/adc_api/boards/nucleo_l152re.overlay index d8d89d460a0..27c7967d755 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_l152re.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_l152re.overlay @@ -12,6 +12,9 @@ }; &adc1 { + dmas = <&dma1 1 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dma-names = "dma"; + pinctrl-0 = <&adc_in0_pa0 &adc_in1_pa1>; #address-cells = <1>; #size-cells = <0>; @@ -32,3 +35,7 @@ zephyr,resolution = <12>; }; }; + +&dma1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_wb55rg.overlay b/tests/drivers/adc/adc_api/boards/nucleo_wb55rg.overlay index d88a1e3d08c..6b96f3c7636 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_wb55rg.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_wb55rg.overlay @@ -12,6 +12,10 @@ }; &adc1 { + dmas = <&dmamux1 0 5 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | + STM32_DMA_PERIPH_16BITS)>; + dma-names = "dmamux"; + pinctrl-0 = <&adc1_in3_pc2 &adc1_in4_pc3>; #address-cells = <1>; #size-cells = <0>; @@ -33,3 +37,11 @@ zephyr,resolution = <12>; }; }; + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_wba52cg.overlay b/tests/drivers/adc/adc_api/boards/nucleo_wba52cg.overlay index fa018756494..e5dc2af539f 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_wba52cg.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_wba52cg.overlay @@ -12,6 +12,9 @@ }; &adc4 { + dmas = <&gpdma1 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dma-names = "gpdma"; + pinctrl-0 = <&adc4_in7_pa2 &adc4_in8_pa1>; #address-cells = <1>; #size-cells = <0>; @@ -33,3 +36,7 @@ zephyr,resolution = <12>; }; }; + +&gpdma1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_wl55jc.overlay b/tests/drivers/adc/adc_api/boards/nucleo_wl55jc.overlay index 6e8e84b6678..3348e91f3a4 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_wl55jc.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_wl55jc.overlay @@ -12,6 +12,10 @@ }; &adc1 { + dmas = <&dmamux1 0 5 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | + STM32_DMA_PERIPH_16BITS)>; + dma-names = "dmamux"; + pinctrl-0 = <&adc_in4_pb2 &adc_in5_pb1>; #address-cells = <1>; #size-cells = <0>; @@ -32,3 +36,11 @@ zephyr,resolution = <12>; }; }; + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/stm32f3_disco.overlay b/tests/drivers/adc/adc_api/boards/stm32f3_disco.overlay index 06897f4a6e4..6140352992b 100644 --- a/tests/drivers/adc/adc_api/boards/stm32f3_disco.overlay +++ b/tests/drivers/adc/adc_api/boards/stm32f3_disco.overlay @@ -12,6 +12,9 @@ }; &adc1 { + dmas = <&dma1 1 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dma-names = "dma"; + pinctrl-0 = <&adc1_in1_pa0 &adc1_in2_pa1>; #address-cells = <1>; #size-cells = <0>; @@ -32,3 +35,7 @@ zephyr,resolution = <12>; }; }; + +&dma1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/boards/stm32h573i_dk.overlay b/tests/drivers/adc/adc_api/boards/stm32h573i_dk.overlay index 4a71e03421d..683264ab20c 100644 --- a/tests/drivers/adc/adc_api/boards/stm32h573i_dk.overlay +++ b/tests/drivers/adc/adc_api/boards/stm32h573i_dk.overlay @@ -13,6 +13,9 @@ }; &adc1 { + dmas = <&gpdma1 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dma-names = "gpdma"; + pinctrl-0 = < &adc1_inp3_pa6 &adc1_inp6_pf12>; #address-cells = <1>; #size-cells = <0>; @@ -33,3 +36,7 @@ zephyr,resolution = <12>; }; }; + +&gpdma1 { + status = "okay"; +}; diff --git a/tests/drivers/adc/adc_api/testcase.yaml b/tests/drivers/adc/adc_api/testcase.yaml index 8d6af2c8ead..e187756ed03 100644 --- a/tests/drivers/adc/adc_api/testcase.yaml +++ b/tests/drivers/adc/adc_api/testcase.yaml @@ -20,10 +20,25 @@ tests: - dma min_flash: 40 platform_allow: + - b_u585i_iot02a + - disco_l475_iot1 + - nucleo_f091rc + - nucleo_f207zg - nucleo_f401re + - nucleo_f429zi + - nucleo_f746zg + - nucleo_g071rb + - nucleo_g474re - nucleo_h743zi + - nucleo_l073rz + - nucleo_l152re - nucleo_l476rg - nucleo_u575zi_q + - nucleo_wb55rg + - nucleo_wba52cg + - nucleo_wl55jc + - stm32f3_disco + - stm32h573i_dk drivers.adc.dma_nxp_kinetis: extra_args: - OVERLAY_CONFIG="overlay-dma-kinetis.conf" From 2c5b9922091115404a935c844851324688c8f454 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Thu, 14 Mar 2024 00:23:14 +0000 Subject: [PATCH 1035/2402] input: pmw3610: add few config options Add config options for resolution, force awake and smart mode. Signed-off-by: Fabio Baltieri --- drivers/input/input_pmw3610.c | 154 +++++++++++++++++++++- dts/bindings/input/pixart,pmw3610.yaml | 20 +++ include/zephyr/input/input_pmw3610.h | 26 ++++ tests/drivers/build_all/input/app.overlay | 2 + 4 files changed, 200 insertions(+), 2 deletions(-) create mode 100644 include/zephyr/input/input_pmw3610.h diff --git a/drivers/input/input_pmw3610.c b/drivers/input/input_pmw3610.c index 2933ce2433a..5458910be9a 100644 --- a/drivers/input/input_pmw3610.c +++ b/drivers/input/input_pmw3610.c @@ -13,10 +13,12 @@ #include #include #include +#include #include #include #include #include +#include #include LOG_MODULE_REGISTER(input_pmw3610, CONFIG_INPUT_LOG_LEVEL); @@ -34,6 +36,7 @@ LOG_MODULE_REGISTER(input_pmw3610, CONFIG_INPUT_LOG_LEVEL); #define PMW3610_REST1_RATE 0x1c #define PMW3610_REST1_DOWNSHIFT 0x1d #define PMW3610_OBSERVATION1 0x2d +#define PMW3610_SMART_MODE 0x32 #define PMW3610_POWER_UP_RESET 0x3a #define PMW3610_SHUTDOWN 0x3b #define PMW3610_SPI_CLK_ON_REQ 0x41 @@ -52,6 +55,10 @@ LOG_MODULE_REGISTER(input_pmw3610, CONFIG_INPUT_LOG_LEVEL); #define BURST_SHUTTER_HI 5 #define BURST_SHUTTER_LO 6 +#define BURST_DATA_LEN_NORMAL (BURST_DELTA_XY_H + 1) +#define BURST_DATA_LEN_SMART (BURST_SHUTTER_LO + 1) +#define BURST_DATA_LEN_MAX MAX(BURST_DATA_LEN_NORMAL, BURST_DATA_LEN_SMART) + /* Init sequence values */ #define OBSERVATION1_INIT_MASK 0x0f #define PERFORMANCE_INIT 0x0d @@ -66,10 +73,17 @@ LOG_MODULE_REGISTER(input_pmw3610, CONFIG_INPUT_LOG_LEVEL); #define SPI_CLOCK_ON_REQ_OFF 0xb5 #define RES_STEP_INV_X_BIT 6 #define RES_STEP_INV_Y_BIT 5 +#define RES_STEP_RES_MASK 0x1f +#define PERFORMANCE_FMODE_MASK (0x0f << 4) +#define PERFORMANCE_FMODE_NORMAL (0x00 << 4) +#define PERFORMANCE_FMODE_FORCE_AWAKE (0x0f << 4) #define POWER_UP_WAKEUP 0x96 #define SHUTDOWN_ENABLE 0xe7 #define SPI_PAGE0_1 0xff #define SPI_PAGE1_0 0x00 +#define SHUTTER_SMART_THRESHOLD 45 +#define SMART_MODE_ENABLE 0x00 +#define SMART_MODE_DISABLE 0x80 #define PMW3610_DATA_SIZE_BITS 12 @@ -77,20 +91,28 @@ LOG_MODULE_REGISTER(input_pmw3610, CONFIG_INPUT_LOG_LEVEL); #define INIT_OBSERVATION_DELAY_MS 10 #define CLOCK_ON_DELAY_US 300 +#define RES_STEP 200 +#define RES_MIN 200 +#define RES_MAX 3200 + struct pmw3610_config { struct spi_dt_spec spi; struct gpio_dt_spec motion_gpio; struct gpio_dt_spec reset_gpio; uint16_t axis_x; uint16_t axis_y; + int16_t res_cpi; bool invert_x; bool invert_y; + bool force_awake; + bool smart_mode; }; struct pmw3610_data { const struct device *dev; struct k_work motion_work; struct gpio_callback motion_cb; + bool smart_flag; }; static int pmw3610_read(const struct device *dev, @@ -169,11 +191,18 @@ static void pmw3610_motion_work_handler(struct k_work *work) work, struct pmw3610_data, motion_work); const struct device *dev = data->dev; const struct pmw3610_config *cfg = dev->config; - uint8_t burst_data[4]; + uint8_t burst_data[BURST_DATA_LEN_MAX]; + uint8_t burst_data_len; int32_t x, y; int ret; - ret = pmw3610_read(dev, PMW3610_BURST_READ, burst_data, sizeof(burst_data)); + if (cfg->smart_mode) { + burst_data_len = BURST_DATA_LEN_SMART; + } else { + burst_data_len = BURST_DATA_LEN_NORMAL; + } + + ret = pmw3610_read(dev, PMW3610_BURST_READ, burst_data, burst_data_len); if (ret < 0) { return; } @@ -190,6 +219,34 @@ static void pmw3610_motion_work_handler(struct k_work *work) input_report_rel(data->dev, cfg->axis_x, x, false, K_FOREVER); input_report_rel(data->dev, cfg->axis_y, y, true, K_FOREVER); + + if (cfg->smart_mode) { + uint16_t shutter_val = sys_get_be16(&burst_data[BURST_SHUTTER_HI]); + + if (data->smart_flag && shutter_val < SHUTTER_SMART_THRESHOLD) { + pmw3610_spi_clk_on(dev); + + ret = pmw3610_write_reg(dev, PMW3610_SMART_MODE, SMART_MODE_ENABLE); + if (ret < 0) { + return; + } + + pmw3610_spi_clk_off(dev); + + data->smart_flag = false; + } else if (!data->smart_flag && shutter_val > SHUTTER_SMART_THRESHOLD) { + pmw3610_spi_clk_on(dev); + + ret = pmw3610_write_reg(dev, PMW3610_SMART_MODE, SMART_MODE_DISABLE); + if (ret < 0) { + return; + } + + pmw3610_spi_clk_off(dev); + + data->smart_flag = true; + } + } } static void pmw3610_motion_handler(const struct device *gpio_dev, @@ -202,6 +259,87 @@ static void pmw3610_motion_handler(const struct device *gpio_dev, k_work_submit(&data->motion_work); } +int pmw3610_set_resolution(const struct device *dev, uint16_t res_cpi) +{ + uint8_t val; + int ret; + + if (!IN_RANGE(res_cpi, RES_MIN, RES_MAX)) { + LOG_ERR("res_cpi out of range: %d", res_cpi); + return -EINVAL; + } + + ret = pmw3610_spi_clk_on(dev); + if (ret < 0) { + return ret; + } + + ret = pmw3610_write_reg(dev, PWM3610_SPI_PAGE0, SPI_PAGE0_1); + if (ret < 0) { + return ret; + } + + ret = pmw3610_read_reg(dev, PMW3610_RES_STEP, &val); + if (ret < 0) { + return ret; + } + + val &= ~RES_STEP_RES_MASK; + val |= res_cpi / RES_STEP; + + ret = pmw3610_write_reg(dev, PMW3610_RES_STEP, val); + if (ret < 0) { + return ret; + } + + ret = pmw3610_write_reg(dev, PWM3610_SPI_PAGE1, SPI_PAGE1_0); + if (ret < 0) { + return ret; + } + + ret = pmw3610_spi_clk_off(dev); + if (ret < 0) { + return ret; + } + + return 0; +} + +int pmw3610_force_awake(const struct device *dev, bool enable) +{ + uint8_t val; + int ret; + + ret = pmw3610_read_reg(dev, PMW3610_PERFORMANCE, &val); + if (ret < 0) { + return ret; + } + + val &= ~PERFORMANCE_FMODE_MASK; + if (enable) { + val |= PERFORMANCE_FMODE_FORCE_AWAKE; + } else { + val |= PERFORMANCE_FMODE_NORMAL; + } + + ret = pmw3610_spi_clk_on(dev); + if (ret < 0) { + return ret; + } + + ret = pmw3610_write_reg(dev, PMW3610_PERFORMANCE, val); + if (ret < 0) { + return ret; + } + + ret = pmw3610_spi_clk_off(dev); + if (ret < 0) { + return ret; + } + + return 0; +} + static int pmw3610_configure(const struct device *dev) { const struct pmw3610_config *cfg = dev->config; @@ -320,6 +458,12 @@ static int pmw3610_configure(const struct device *dev) } } + if (cfg->res_cpi > 0) { + pmw3610_set_resolution(dev, cfg->res_cpi); + } + + pmw3610_force_awake(dev, cfg->force_awake); + return 0; } @@ -411,14 +555,20 @@ static int pmw3610_pm_action(const struct device *dev, SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_TRANSFER_MSB) #define PMW3610_INIT(n) \ + BUILD_ASSERT(IN_RANGE(DT_INST_PROP_OR(n, res_cpi, RES_MIN), \ + RES_MIN, RES_MAX), "invalid res-cpi"); \ + \ static const struct pmw3610_config pmw3610_cfg_##n = { \ .spi = SPI_DT_SPEC_INST_GET(n, PMW3610_SPI_MODE, 0), \ .motion_gpio = GPIO_DT_SPEC_INST_GET(n, motion_gpios), \ .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {}), \ .axis_x = DT_INST_PROP(n, zephyr_axis_x), \ .axis_y = DT_INST_PROP(n, zephyr_axis_y), \ + .res_cpi = DT_INST_PROP_OR(n, res_cpi, -1), \ .invert_x = DT_INST_PROP(n, invert_x), \ .invert_y = DT_INST_PROP(n, invert_y), \ + .force_awake = DT_INST_PROP(n, force_awake), \ + .smart_mode = DT_INST_PROP(n, smart_mode), \ }; \ \ static struct pmw3610_data pmw3610_data_##n; \ diff --git a/dts/bindings/input/pixart,pmw3610.yaml b/dts/bindings/input/pixart,pmw3610.yaml index d65d3715f95..ffa36abb904 100644 --- a/dts/bindings/input/pixart,pmw3610.yaml +++ b/dts/bindings/input/pixart,pmw3610.yaml @@ -33,6 +33,13 @@ properties: The input code for the Y axis to report for the device, typically any of INPUT_REL_*. No report produced for the device Y axis if unspecified. + res-cpi: + type: int + description: | + CPI resolution for the sensor, range from 200 to 3200, rounded down to + the closest supported value in increments of 200. This can also be + changed in runtime using the pmw3610_set_resolution() API. + invert-x: type: boolean description: | @@ -42,3 +49,16 @@ properties: type: boolean description: | Invert Y axis values. + + force-awake: + type: boolean + description: | + Initialize the sensor in "force awake" mode. This can also be enabled or + disabled in runtime by the application using the pmw3610_force_awake() + API. + + smart-mode: + type: boolean + description: | + Enable the "smart mode" algorithm as described in the device datasheet. + This should improve sensor tracking across a wider range of surfaces. diff --git a/include/zephyr/input/input_pmw3610.h b/include/zephyr/input/input_pmw3610.h new file mode 100644 index 00000000000..d7903bb55e6 --- /dev/null +++ b/include/zephyr/input/input_pmw3610.h @@ -0,0 +1,26 @@ +/* + * Copyright 2024 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_INPUT_PMW3610_H_ +#define ZEPHYR_INCLUDE_INPUT_PMW3610_H_ + +/** + * @brief Set resolution on a pmw3610 device + * + * @param dev pmw3610 device. + * @param res_cpi CPI resolution, 200 to 3200. + */ +int pmw3610_set_resolution(const struct device *dev, uint16_t res_cpi); + +/** + * @brief Set force awake mode on a pmw3610 device + * + * @param dev pmw3610 device. + * @param enable whether to enable or disable force awake mode. + */ +int pmw3610_force_awake(const struct device *dev, bool enable); + +#endif /* ZEPHYR_INCLUDE_INPUT_PMW3610_H_ */ diff --git a/tests/drivers/build_all/input/app.overlay b/tests/drivers/build_all/input/app.overlay index 5687406d4db..996af07499a 100644 --- a/tests/drivers/build_all/input/app.overlay +++ b/tests/drivers/build_all/input/app.overlay @@ -248,6 +248,8 @@ zephyr,axis-y = <1>; invert-x; invert-y; + force-awake; + smart-mode; }; }; }; From c82b38c7be850a6451ef3f897b81241305d302dd Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Thu, 14 Mar 2024 19:50:43 +0000 Subject: [PATCH 1036/2402] input: pmw3610: run the whole init with spi clock on Move the pmw3610_spi_clk_on and pmw3610_spi_clk_off calls so that the "on" call is before the first write. The datasheet calls for doing this before any write operations, though some writes seems to work without this in place, other seems to behave erroneously. The non static functions do it on their own as they can be called separately. Signed-off-by: Fabio Baltieri --- drivers/input/input_pmw3610.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/input/input_pmw3610.c b/drivers/input/input_pmw3610.c index 5458910be9a..bcf55496b2d 100644 --- a/drivers/input/input_pmw3610.c +++ b/drivers/input/input_pmw3610.c @@ -376,6 +376,10 @@ static int pmw3610_configure(const struct device *dev) } /* Power-up init sequence */ + ret = pmw3610_spi_clk_on(dev); + if (ret < 0) { + return ret; + } ret = pmw3610_write_reg(dev, PMW3610_OBSERVATION1, 0); if (ret < 0) { @@ -424,11 +428,6 @@ static int pmw3610_configure(const struct device *dev) /* Configuration */ if (cfg->invert_x || cfg->invert_y) { - ret = pmw3610_spi_clk_on(dev); - if (ret < 0) { - return ret; - } - ret = pmw3610_write_reg(dev, PWM3610_SPI_PAGE0, SPI_PAGE0_1); if (ret < 0) { return ret; @@ -452,12 +451,15 @@ static int pmw3610_configure(const struct device *dev) return ret; } - ret = pmw3610_spi_clk_off(dev); - if (ret < 0) { - return ret; - } } + ret = pmw3610_spi_clk_off(dev); + if (ret < 0) { + return ret; + } + + /* The remaining functions call spi_clk_on/off independently. */ + if (cfg->res_cpi > 0) { pmw3610_set_resolution(dev, cfg->res_cpi); } From c531e4c2ac34a9eca268efb78834cf5245d745d0 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Mon, 18 Mar 2024 14:16:40 +0100 Subject: [PATCH 1037/2402] scripts: test for imported ELFFile instead of setting it to None mypy fails with: Incompatible types in assignment (expression has type "None", variable has type "Type[ELFFile]") this happens because of the code: try: from elftools.elf.elffile import ELFFile except ImportError: ELFFile = None ELFFile is set to None to allow later code to check if ELFFile was imported by checking against None. Instead of setting ELFFile to None, then update testing code to check if the class has been loaded, as: if globals().get('ELFFile') is None: Update the try-catch to `pass`. Removed ELFFile cargo cult from intel_cyclonev.py and fix pylint warnings. Disable duplicate code check. The intel_cyclonev.py is already based upon openocd.py, so although the duplication detection is correct then this should not prevent other code changes / fixes to those files from being applied. Signed-off-by: Torsten Rasmussen --- scripts/west_commands/runners/intel_cyclonev.py | 16 ++++------------ scripts/west_commands/runners/openocd.py | 8 +++++--- 2 files changed, 9 insertions(+), 15 deletions(-) diff --git a/scripts/west_commands/runners/intel_cyclonev.py b/scripts/west_commands/runners/intel_cyclonev.py index eb67c860800..c6bfb65eeef 100644 --- a/scripts/west_commands/runners/intel_cyclonev.py +++ b/scripts/west_commands/runners/intel_cyclonev.py @@ -11,11 +11,6 @@ from os import path from pathlib import Path -try: - from elftools.elf.elffile import ELFFile -except ImportError: - ELFFile = None - from runners.core import ZephyrBinaryRunner, RunnerCaps DEFAULT_OPENOCD_TCL_PORT = 6333 @@ -195,7 +190,7 @@ def to_num(self, number): def read_version(self): self.require(self.openocd_cmd[0]) - # OpenOCD prints in stderr, need redirect to get output + # OpenOCD prints in stderr, need redirect to get output out = self.check_output([self.openocd_cmd[0], '--version'], stderr=subprocess.STDOUT).decode() @@ -210,9 +205,6 @@ def supports_thread_info(self): def do_run(self, command, **kwargs): self.require(self.openocd_cmd[0]) - if ELFFile is None: - raise RuntimeError( - 'elftools missing; please "pip3 install elftools"') self.cfg_cmd = [] if self.openocd_config is not None: @@ -272,11 +264,11 @@ def do_flash_elf(self, **kwargs): self.require(gdb_cmd[0]) self.print_gdbserver_message() - cmd1 = (echo + server_cmd) + cmd1 = echo + server_cmd self.check_call(cmd1) - cmd2 = (echo + gdb_cmd) + cmd2 = echo + gdb_cmd self.check_call(cmd2) - cmd3 = (echo + gdb_cmd2) + cmd3 = echo + gdb_cmd2 self.check_call(cmd3) self.run_server_and_client(server_cmd, gdb_cmd) diff --git a/scripts/west_commands/runners/openocd.py b/scripts/west_commands/runners/openocd.py index ff92d4f58f4..dd7c6882a36 100644 --- a/scripts/west_commands/runners/openocd.py +++ b/scripts/west_commands/runners/openocd.py @@ -1,6 +1,8 @@ # Copyright (c) 2017 Linaro Limited. # # SPDX-License-Identifier: Apache-2.0 +# +# pylint: disable=duplicate-code '''Runner for openocd.''' @@ -13,7 +15,7 @@ try: from elftools.elf.elffile import ELFFile except ImportError: - ELFFile = None + pass from runners.core import ZephyrBinaryRunner @@ -189,7 +191,7 @@ def to_num(self, number): def read_version(self): self.require(self.openocd_cmd[0]) - # OpenOCD prints in stderr, need redirect to get output + # OpenOCD prints in stderr, need redirect to get output out = self.check_output([self.openocd_cmd[0], '--version'], stderr=subprocess.STDOUT).decode() @@ -204,7 +206,7 @@ def supports_thread_info(self): def do_run(self, command, **kwargs): self.require(self.openocd_cmd[0]) - if ELFFile is None: + if globals().get('ELFFile') is None: raise RuntimeError( 'elftools missing; please "pip3 install elftools"') From 7bea89ac4491423a23be17f171f18145f6d4fb11 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 18 Mar 2024 10:32:19 +0100 Subject: [PATCH 1038/2402] scripts: west_commands: runners: nrfjprog: drop nRF54H support nRF54Hx series is no longer supported in nrfjprog. nrfutil is now required. Signed-off-by: Gerard Marull-Paretas --- scripts/west_commands/runners/nrfjprog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/west_commands/runners/nrfjprog.py b/scripts/west_commands/runners/nrfjprog.py index 723080d56c3..cfcf43c9e78 100644 --- a/scripts/west_commands/runners/nrfjprog.py +++ b/scripts/west_commands/runners/nrfjprog.py @@ -48,7 +48,7 @@ def do_exec_op(self, op, force=False): families = {'NRF51_FAMILY': 'NRF51', 'NRF52_FAMILY': 'NRF52', 'NRF53_FAMILY': 'NRF53', 'NRF54L_FAMILY': 'NRF54L', - 'NRF54H_FAMILY': 'NRF54H', 'NRF91_FAMILY': 'NRF91'} + 'NRF91_FAMILY': 'NRF91'} cores = {'NRFDL_DEVICE_CORE_APPLICATION': 'CP_APPLICATION', 'NRFDL_DEVICE_CORE_NETWORK': 'CP_NETWORK'} From 0387214bfcafa30e11f8b4d11889f8b55a998fff Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 18 Mar 2024 10:55:53 +0100 Subject: [PATCH 1039/2402] scripts: west_commands: runners: nrfutil: use x-execute-batch execute-batch is now named x-execute-batch, as it is an experimental option. Signed-off-by: Gerard Marull-Paretas --- scripts/west_commands/runners/nrfutil.py | 2 +- scripts/west_commands/tests/test_nrf.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/west_commands/runners/nrfutil.py b/scripts/west_commands/runners/nrfutil.py index 719e432a23b..50db41abae2 100644 --- a/scripts/west_commands/runners/nrfutil.py +++ b/scripts/west_commands/runners/nrfutil.py @@ -97,7 +97,7 @@ def _exec_batch(self): self._ops = [] self._op_id = 1 self.logger.debug(f'Executing batch in: {json_file}') - self._exec(['execute-batch', '--batch-path', f'{json_file}', + self._exec(['x-execute-batch', '--batch-path', f'{json_file}', '--serial-number', f'{self.dev_id}']) def do_exec_op(self, op, force=False): diff --git a/scripts/west_commands/tests/test_nrf.py b/scripts/west_commands/tests/test_nrf.py index 405e6ea9d6c..a15fe2302e5 100644 --- a/scripts/west_commands/tests/test_nrf.py +++ b/scripts/west_commands/tests/test_nrf.py @@ -521,7 +521,7 @@ def check_expected(tool, test_case, check_fn, get_snr, tmpdir, runner_config): # Extract filename nrfutil_args = check_fn.call_args_list[0].args[0] tmpfile = nrfutil_args[nrfutil_args.index('--batch-path') + 1] - cmds = (['nrfutil', '--json', 'device', 'execute-batch', '--batch-path', + cmds = (['nrfutil', '--json', 'device', 'x-execute-batch', '--batch-path', tmpfile, '--serial-number', expected[0]],) else: cmds = expected From acc0a43fb919f84600a84467fda71b164796b7cc Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 18 Mar 2024 11:42:50 +0100 Subject: [PATCH 1040/2402] scripts: west_commands: runners: nrfutil: provide live feedback nrfutil runner uses the batch-mode, so no live feedback is provided to the user. However, batch-mode reports batch progress containing human-readable strings of the operation being done. This patch changes the _exec() implementation to parse the subprocess output in real-time, logging to info the 'batch_update' reports. Note that only the first batch update of a sequence (percentage = 0) is logged because first, percentage resolution seems to be pretty bad, and, because logging messages cannot be easily _appended_. Signed-off-by: Gerard Marull-Paretas --- scripts/west_commands/runners/nrfutil.py | 51 ++++++++++++++---------- 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/scripts/west_commands/runners/nrfutil.py b/scripts/west_commands/runners/nrfutil.py index 50db41abae2..a7ff512bb9f 100644 --- a/scripts/west_commands/runners/nrfutil.py +++ b/scripts/west_commands/runners/nrfutil.py @@ -10,8 +10,10 @@ import sys import subprocess +from runners.core import _DRY_RUN from runners.nrf_common import NrfBinaryRunner + class NrfUtilBinaryRunner(NrfBinaryRunner): '''Runner front-end for nrfutil.''' @@ -40,27 +42,34 @@ def do_create(cls, cfg, args): recover=args.recover) def _exec(self, args): - try: - out = self.check_output(['nrfutil', '--json', 'device'] + args) - except subprocess.CalledProcessError as e: - # https://docs.python.org/3/reference/compound_stmts.html#except-clause - cpe = e - out = cpe.stdout - else: - cpe = None - finally: - # https://github.com/ndjson/ndjson-spec - out = [json.loads(s) for s in - out.decode(sys.getdefaultencoding()).split('\n') if len(s)] - self.logger.debug(f'output: {out}') - if cpe: - if 'execute-batch' in args: - for o in out: - if o['type'] == 'batch_end' and o['data']['error']: - cpe.returncode = o['data']['error']['code'] - raise cpe - - return out + jout_all = [] + + cmd = ['nrfutil', '--json', 'device'] + args + self._log_cmd(cmd) + + if _DRY_RUN: + return {} + + with subprocess.Popen(cmd, stdout=subprocess.PIPE) as p: + for line in iter(p.stdout.readline, b''): + # https://github.com/ndjson/ndjson-spec + jout = json.loads(line.decode(sys.getdefaultencoding())) + jout_all.append(jout) + + if 'x-execute-batch' in args: + if jout['type'] == 'batch_update': + pld = jout['data']['data'] + if ( + pld['type'] == 'task_progress' and + pld['data']['progress']['progressPercentage'] == 0 + ): + self.logger.info(pld['data']['progress']['description']) + elif jout['type'] == 'batch_end' and jout['data']['error']: + raise subprocess.CalledProcessError( + jout['data']['error']['code'], cmd + ) + + return jout_all def do_get_boards(self): out = self._exec(['list']) From 78706dffdbc502e2f99cf6807ad33cf1708a7467 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 18 Mar 2024 11:46:26 +0100 Subject: [PATCH 1041/2402] scripts: west_commands: runners: nrf_common: update nRF54H support nRF54H can only be flashed using nrfutil now, so some workaround present in the nrf_common module are no longer needed, e.g. UICR erasing. Signed-off-by: Gerard Marull-Paretas --- scripts/west_commands/runners/nrf_common.py | 62 ++++++++++----------- scripts/west_commands/runners/nrfjprog.py | 3 +- scripts/west_commands/tests/test_nrf.py | 21 ++++--- 3 files changed, 44 insertions(+), 42 deletions(-) diff --git a/scripts/west_commands/runners/nrf_common.py b/scripts/west_commands/runners/nrf_common.py index 76662c72ea9..1ea09f8f595 100644 --- a/scripts/west_commands/runners/nrf_common.py +++ b/scripts/west_commands/runners/nrf_common.py @@ -29,10 +29,6 @@ 'NRFDL_DEVICE_CORE_APPLICATION': (0x00FF8000, 0x00FF8800), 'NRFDL_DEVICE_CORE_NETWORK': (0x01FF8000, 0x01FF8800), }, - 'NRF54H_FAMILY': { - 'NRFDL_DEVICE_CORE_APPLICATION': (0x0FFF8000, 0x0FFF8800), - 'NRFDL_DEVICE_CORE_NETWORK': (0x0FFFA000, 0x0FFFA800), - }, 'NRF91_FAMILY': { 'NRFDL_DEVICE_CORE_APPLICATION': (0x00FF8000, 0x00FF8800), } @@ -42,8 +38,7 @@ class NrfBinaryRunner(ZephyrBinaryRunner): '''Runner front-end base class for nrf tools.''' def __init__(self, cfg, family, softreset, dev_id, erase=False, - reset=True, tool_opt=[], force=False, recover=False, - erase_all_uicrs=False): + reset=True, tool_opt=[], force=False, recover=False): super().__init__(cfg) self.hex_ = cfg.hex_file if family and not family.endswith('_FAMILY'): @@ -55,7 +50,6 @@ def __init__(self, cfg, family, softreset, dev_id, erase=False, self.reset = bool(reset) self.force = force self.recover = bool(recover) - self.erase_all_uicrs = bool(erase_all_uicrs) self.tool_opt = [] for opts in [shlex.split(opt) for opt in tool_opt]: @@ -92,11 +86,6 @@ def do_add_parser(cls, parser): help='''erase all user available non-volatile memory and disable read back protection before flashing (erases flash for both cores on nRF53)''') - parser.add_argument('--erase-all-uicrs', required=False, - action='store_true', - help='''Erase all UICR registers before flashing - (nRF54H only). When not set, only UICR registers - present in the hex file will be erased.''') parser.set_defaults(reset=True) @@ -261,14 +250,36 @@ def program_hex(self): # Get the command use to actually program self.hex_. self.logger.info('Flashing file: {}'.format(self.hex_)) - # What type of erase argument should we pass to the tool? - if self.erase: - erase_arg = 'ERASE_ALL' + # What type of erase/core arguments should we pass to the tool? + core = None + + if self.family == 'NRF54H_FAMILY': + erase_arg = 'ERASE_NONE' + + if self.erase: + self.exec_op('erase', core='NRFDL_DEVICE_CORE_APPLICATION') + self.exec_op('erase', core='NRFDL_DEVICE_CORE_NETWORK') + + if self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPUAPP'): + if not self.erase: + self.exec_op('erase', core='NRFDL_DEVICE_CORE_APPLICATION', + chip_erase_mode='ERASE_UICR', + qspi_erase_mode='ERASE_NONE') + core = 'NRFDL_DEVICE_CORE_APPLICATION' + elif self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPURAD'): + if not self.erase: + self.exec_op('erase', core='NRFDL_DEVICE_CORE_NETWORK', + chip_erase_mode='ERASE_UICR', + qspi_erase_mode='ERASE_NONE') + core = 'NRFDL_DEVICE_CORE_NETWORK' else: - if self.family == 'NRF52_FAMILY': - erase_arg = 'ERASE_PAGES_INCLUDING_UICR' + if self.erase: + erase_arg = 'ERASE_ALL' else: - erase_arg = 'ERASE_PAGES' + if self.family == 'NRF52_FAMILY': + erase_arg = 'ERASE_PAGES_INCLUDING_UICR' + else: + erase_arg = 'ERASE_PAGES' xip_ranges = { 'NRF52_FAMILY': (0x12000000, 0x19FFFFFF), @@ -284,24 +295,11 @@ def program_hex(self): if self.family == 'NRF53_FAMILY': # nRF53 requires special treatment due to the extra coprocessor. self.program_hex_nrf53(erase_arg, qspi_erase_opt) - elif self.family == 'NRF54H_FAMILY': - self.program_hex_nrf54h() else: - self.op_program(self.hex_, erase_arg, qspi_erase_opt, defer=True) + self.op_program(self.hex_, erase_arg, qspi_erase_opt, defer=True, core=core) self.flush(force=False) - def program_hex_nrf54h(self): - if self.erase_all_uicrs: - uicrs = UICR_RANGES['NRF54H_FAMILY'] - else: - uicrs = self.hex_get_uicrs() - - for uicr_core, range in uicrs.items(): - self.exec_op('erasepage', defer=True, core=uicr_core, page=range[0]) - - self.op_program(self.hex_, 'NO_ERASE', None, defer=True) - def program_hex_nrf53(self, erase_arg, qspi_erase_opt): # program_hex() helper for nRF53. diff --git a/scripts/west_commands/runners/nrfjprog.py b/scripts/west_commands/runners/nrfjprog.py index cfcf43c9e78..f4bdfa74f97 100644 --- a/scripts/west_commands/runners/nrfjprog.py +++ b/scripts/west_commands/runners/nrfjprog.py @@ -32,8 +32,7 @@ def do_create(cls, cfg, args): args.dev_id, erase=args.erase, reset=args.reset, tool_opt=args.tool_opt, force=args.force, - recover=args.recover, - erase_all_uicrs=args.erase_all_uicrs) + recover=args.recover) def do_get_boards(self): snrs = self.check_output(['nrfjprog', '--ids']) diff --git a/scripts/west_commands/tests/test_nrf.py b/scripts/west_commands/tests/test_nrf.py index a15fe2302e5..d3f429ef775 100644 --- a/scripts/west_commands/tests/test_nrf.py +++ b/scripts/west_commands/tests/test_nrf.py @@ -5,6 +5,7 @@ import argparse import functools +import io import os from pathlib import Path import shlex @@ -523,14 +524,16 @@ def check_expected(tool, test_case, check_fn, get_snr, tmpdir, runner_config): tmpfile = nrfutil_args[nrfutil_args.index('--batch-path') + 1] cmds = (['nrfutil', '--json', 'device', 'x-execute-batch', '--batch-path', tmpfile, '--serial-number', expected[0]],) + call_args = [call(nrfutil_args)] else: cmds = expected + call_args = check_fn.call_args_list if callable(cmds): - assert (check_fn.call_args_list == + assert (call_args == [call(x) for x in cmds(tmpdir, runner_config.hex_file)]) else: - assert check_fn.call_args_list == [call(x) for x in cmds] + assert call_args == [call(x) for x in cmds] if not test_case.snr: get_snr.assert_called_once_with('*') @@ -542,10 +545,11 @@ def check_expected(tool, test_case, check_fn, get_snr, tmpdir, runner_config): @patch('runners.core.ZephyrBinaryRunner.require') @patch('runners.nrfjprog.NrfBinaryRunner.get_board_snr', side_effect=get_board_snr_patch) -@patch('runners.nrfjprog.NrfBinaryRunner.check_output') +@patch('runners.nrfutil.subprocess.Popen') @patch('runners.nrfjprog.NrfBinaryRunner.check_call') -def test_init(check_call, check_output, get_snr, require, tool, test_case, +def test_init(check_call, popen, get_snr, require, tool, test_case, runner_config, tmpdir): + popen.return_value.__enter__.return_value.stdout = io.BytesIO(b'') require.side_effect = functools.partial(require_patch, tool) runner_config = fix_up_runner_config(test_case, runner_config, tmpdir) @@ -564,7 +568,7 @@ def test_init(check_call, check_output, get_snr, require, tool, test_case, runner.run('flash') assert require.called - CHECK_FN_MAP = {'nrfjprog': check_call, 'nrfutil': check_output} + CHECK_FN_MAP = {'nrfjprog': check_call, 'nrfutil': popen} check_expected(tool, test_case, CHECK_FN_MAP[tool], get_snr, tmpdir, runner_config) @@ -573,10 +577,11 @@ def test_init(check_call, check_output, get_snr, require, tool, test_case, @patch('runners.core.ZephyrBinaryRunner.require') @patch('runners.nrfjprog.NrfBinaryRunner.get_board_snr', side_effect=get_board_snr_patch) -@patch('runners.nrfjprog.NrfBinaryRunner.check_output') +@patch('runners.nrfutil.subprocess.Popen') @patch('runners.nrfjprog.NrfBinaryRunner.check_call') -def test_create(check_call, check_output, get_snr, require, tool, test_case, +def test_create(check_call, popen, get_snr, require, tool, test_case, runner_config, tmpdir): + popen.return_value.__enter__.return_value.stdout = io.BytesIO(b'') require.side_effect = functools.partial(require_patch, tool) runner_config = fix_up_runner_config(test_case, runner_config, tmpdir) @@ -603,6 +608,6 @@ def test_create(check_call, check_output, get_snr, require, tool, test_case, assert require.called - CHECK_FN_MAP = {'nrfjprog': check_call, 'nrfutil': check_output} + CHECK_FN_MAP = {'nrfjprog': check_call, 'nrfutil': popen} check_expected(tool, test_case, CHECK_FN_MAP[tool], get_snr, tmpdir, runner_config) From db237875376e3ef548f3691994a7fbb35caef254 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 18 Mar 2024 11:47:31 +0100 Subject: [PATCH 1042/2402] boards: nordic: nrf54h20dk: enable nrfutil Board can be programmed using nrfutil. Signed-off-by: Gerard Marull-Paretas --- boards/nordic/nrf54h20dk/board.cmake | 2 ++ 1 file changed, 2 insertions(+) diff --git a/boards/nordic/nrf54h20dk/board.cmake b/boards/nordic/nrf54h20dk/board.cmake index 32d1daac179..6361f7fe7b4 100644 --- a/boards/nordic/nrf54h20dk/board.cmake +++ b/boards/nordic/nrf54h20dk/board.cmake @@ -1,5 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) + if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD) if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD) set( From d05d51d869cb26ee705f59d0bfda0e638fcd123e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tomasz=20Mo=C5=84?= Date: Thu, 29 Feb 2024 10:49:27 +0100 Subject: [PATCH 1043/2402] samples: bluetooth: hci_usb: Use common USB sample initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert hci_usb sample to use common USB sample initialization code. Signed-off-by: Tomasz Moń --- samples/bluetooth/hci_usb/CMakeLists.txt | 1 + samples/bluetooth/hci_usb/Kconfig | 9 +++ samples/bluetooth/hci_usb/src/main.c | 59 ++------------------ samples/bluetooth/hci_usb/usbd_next_prj.conf | 2 + 4 files changed, 18 insertions(+), 53 deletions(-) create mode 100644 samples/bluetooth/hci_usb/Kconfig diff --git a/samples/bluetooth/hci_usb/CMakeLists.txt b/samples/bluetooth/hci_usb/CMakeLists.txt index 714d9c369a5..9abfd997851 100644 --- a/samples/bluetooth/hci_usb/CMakeLists.txt +++ b/samples/bluetooth/hci_usb/CMakeLists.txt @@ -4,4 +4,5 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) project(hci_usb) +include(${ZEPHYR_BASE}/samples/subsys/usb/common/common.cmake) target_sources(app PRIVATE src/main.c) diff --git a/samples/bluetooth/hci_usb/Kconfig b/samples/bluetooth/hci_usb/Kconfig new file mode 100644 index 00000000000..825eba9059d --- /dev/null +++ b/samples/bluetooth/hci_usb/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Source common USB sample options used to initialize new experimental USB +# device stack. The scope of these options is limited to USB samples in project +# tree, you cannot use them in your own application. +source "samples/subsys/usb/common/Kconfig.sample_usbd" + +source "Kconfig.zephyr" diff --git a/samples/bluetooth/hci_usb/src/main.c b/samples/bluetooth/hci_usb/src/main.c index 429358fe8e7..8e91caadd33 100644 --- a/samples/bluetooth/hci_usb/src/main.c +++ b/samples/bluetooth/hci_usb/src/main.c @@ -10,65 +10,18 @@ #include #if defined(CONFIG_USB_DEVICE_STACK_NEXT) -USBD_CONFIGURATION_DEFINE(config_1, - USB_SCD_SELF_POWERED, - 200); - -USBD_DESC_LANG_DEFINE(sample_lang); -USBD_DESC_MANUFACTURER_DEFINE(sample_mfr, "ZEPHYR"); -USBD_DESC_PRODUCT_DEFINE(sample_product, "Zephyr USBD BT HCI"); -USBD_DESC_SERIAL_NUMBER_DEFINE(sample_sn, "0123456789ABCDEF"); - - -USBD_DEVICE_DEFINE(sample_usbd, - DEVICE_DT_GET(DT_NODELABEL(zephyr_udc0)), - 0x2fe3, 0x000b); +#include static int enable_usb_device_next(void) { - int err; - - err = usbd_add_descriptor(&sample_usbd, &sample_lang); - if (err) { - return err; - } - - err = usbd_add_descriptor(&sample_usbd, &sample_mfr); - if (err) { - return err; - } - - err = usbd_add_descriptor(&sample_usbd, &sample_product); - if (err) { - return err; - } + struct usbd_contex *sample_usbd = sample_usbd_init_device(); - err = usbd_add_descriptor(&sample_usbd, &sample_sn); - if (err) { - return err; + if (sample_usbd == NULL) { + printk("Failed to initialize USB device"); + return -ENODEV; } - err = usbd_add_configuration(&sample_usbd, &config_1); - if (err) { - return err; - } - - err = usbd_register_class(&sample_usbd, "bt_hci_0", 1); - if (err) { - return err; - } - - err = usbd_init(&sample_usbd); - if (err) { - return err; - } - - err = usbd_enable(&sample_usbd); - if (err) { - return err; - } - - return 0; + return usbd_enable(sample_usbd); } #endif /* CONFIG_USB_DEVICE_STACK_NEXT */ diff --git a/samples/bluetooth/hci_usb/usbd_next_prj.conf b/samples/bluetooth/hci_usb/usbd_next_prj.conf index e3071e15764..e1daa84f47d 100644 --- a/samples/bluetooth/hci_usb/usbd_next_prj.conf +++ b/samples/bluetooth/hci_usb/usbd_next_prj.conf @@ -8,6 +8,8 @@ CONFIG_BT=y CONFIG_BT_HCI_RAW=y CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_SAMPLE_USBD_PID=0x000b +CONFIG_SAMPLE_USBD_PRODUCT="Zephyr USBD BT HCI" CONFIG_USBD_BT_HCI=y CONFIG_LOG=y From 68eb97ea05450f3ebfd718470db84e42e988cbf6 Mon Sep 17 00:00:00 2001 From: Carles Cufi Date: Tue, 19 Mar 2024 17:24:50 +0100 Subject: [PATCH 1044/2402] doc: add board terminology section to board porting guide Add a terminology section to the board porting guide. This provides a single location where terminologies used for boards can be found and linked to. Signed-off-by: Carles Cufi --- doc/develop/getting_started/index.rst | 2 +- doc/glossary.rst | 65 ++++++- .../porting/board/board-terminology.svg | 3 + doc/hardware/porting/board_porting.rst | 180 +++++++++--------- 4 files changed, 161 insertions(+), 89 deletions(-) create mode 100644 doc/hardware/porting/board/board-terminology.svg diff --git a/doc/develop/getting_started/index.rst b/doc/develop/getting_started/index.rst index cbe67aade59..5946e37d068 100644 --- a/doc/develop/getting_started/index.rst +++ b/doc/develop/getting_started/index.rst @@ -568,7 +568,7 @@ another sample. cluster for which the sample must be built. For example to build :zephyr:code-sample:`blinky` for the ``cpuapp`` core on the :ref:`nRF5340DK ` the board must be provided as: - ``nrf5340dk/nrf5340/cpuapp``. Also read :ref:`board_and_identifiers` for more + ``nrf5340dk/nrf5340/cpuapp``. See also :ref:`board_terminology` for more details. Flash the Sample diff --git a/doc/glossary.rst b/doc/glossary.rst index 8571f4b6d49..240727d9e24 100644 --- a/doc/glossary.rst +++ b/doc/glossary.rst @@ -35,10 +35,14 @@ Glossary of Terms Both application code and kernel code execute as privileged code within a single shared address space. + architecture + An instruction set architecture (ISA) along with a programming model. + board A target system with a defined set of devices and capabilities, which can load and execute an application image. It may be an actual - hardware system or a simulated system running under QEMU. + hardware system or a simulated system running under QEMU. A board can + contain one or more :term:`SoCs `. The Zephyr kernel supports a :ref:`variety of boards `. board configuration @@ -49,6 +53,45 @@ Glossary of Terms specified by the build system can be over-ridden by the application, if desired. + board name + The human-readable name of a :term:`board`. Uniquely and descriptively + identifies a particular system, but does not include additional + information that may be required to actually build a Zephyr image for it. + See :ref:`board_terminology` for additional details. + + board qualifiers + The set of additional tokens, separated by a forward slash (`/`) that + follow the :term:`board name` (and optionally :term:`board revision`) to + form the :term:`board target`. The currently accepted qualifiers are + :term:`SoC`, :term:`CPU cluster` and :term:`variant`. + See :ref:`board_terminology` for additional details. + + board revision + An optional version string that identifies a particular revision of a + hardware system. This is useful to avoid duplication of board files + whenever small changes are introduced to a hardware system. + See :ref:`porting_board_revisions` and :ref:`application_board_version` + for more information. + + board target + The full string that can be provided to any of the Zephyr build tools to + compile and link an image for a particular hardware system. This string + uniquely identifies the combination of :term:`board name`, :term:`board + revision` and :term:`board qualifiers`. + See :ref:`board_terminology` for additional details. + + CPU cluster + A group of one or more :term:`CPU cores `, all executing the same image + within the same address space and in a symmetrical (SMP) configuration. + Only :term:`CPU cores ` of the same :term:`architecture` can be in a single + cluster. Multiple CPU clusters (each of one or more cores) can coexist in + the same :term:`SoC`. + + CPU core + A single processing unit, with its own Program Counter, executing program + instructions sequentially. CPU cores are part of a :term:`CPU cluster`, + which can contain one or more cores. + device runtime power management Device Runtime Power Management (PM) refers the capability of devices to save energy independently of the system power state. Devices will keep @@ -85,12 +128,30 @@ Glossary of Terms integrated circuit that are not in use. SoC - `System on a chip`_ + A `System on a chip`_, that is, an integrated circuit that contains at + least one :term:`CPU cluster` (in turn with at least one :term:`CPU core`), + as well as peripherals and memory. + + SoC family + One or more :term:`SoCs ` or :term:`SoC series` that share enough + in common to consider them related and under a single family denomination. + + SoC series + A number of different :term:`SoCs ` that share similar characteristics and + features, and that the vendor typically names and markets together. system power state System power states describe the power consumption of the system as a whole. System power states are represented by :c:enum:`pm_state`. + variant + In the context of :term:`board qualifiers`, a variant designates a + particular type or configuration of a build for a combination of :term:`SoC` + and :term:`CPU cluster`. Common uses of the variant concept include + introducing both secure and non-secure builds for platforms with Trusted + Execution Environment support, or selecting the type of RAM used in a + build. + west A multi-repo meta-tool developed for the Zephyr project. See :ref:`west`. diff --git a/doc/hardware/porting/board/board-terminology.svg b/doc/hardware/porting/board/board-terminology.svg new file mode 100644 index 00000000000..60c3d8a8ebe --- /dev/null +++ b/doc/hardware/porting/board/board-terminology.svg @@ -0,0 +1,3 @@ + + +
    bl5340_dvk@1.2.0/nrf5340/cpuapp/ns
    bl5340_dvk@1.2.0/nrf5340/cpuapp/ns
    Board name
    Board name
    Board qualifiers
    Board qualifiers
    Board target
    Board target
    Board revision
    Board revision
    SoC
    SoC
    CPU cluster
    CPU cluster
    Variant
    Variant     \ No newline at end of file diff --git a/doc/hardware/porting/board_porting.rst b/doc/hardware/porting/board_porting.rst index ebd8ca5e28c..d638a52a253 100644 --- a/doc/hardware/porting/board_porting.rst +++ b/doc/hardware/porting/board_porting.rst @@ -65,112 +65,120 @@ complete conversion reference. .. _example-application conversion Pull Request: https://github.com/zephyrproject-rtos/example-application/pull/58 .. _conversion script: https://github.com/zephyrproject-rtos/zephyr/blob/main/scripts/utils/board_v1_to_v2.py -.. _board_and_identifiers: - -Board and board identifiers -*************************** - -A board may be a physical piece of hardware or an emulated board. -Furthermore a board may contain one or multiple SoCs. Also, each SoC may contain -one or multiple CPU clusters. A CPU cluster refers to a group of CPU cores. -Only CPU cores of same architecture can be in the same cluster. In the case -where a physical SoC considers a CPU cluster to contain CPU cores of different -architectures then those must be modelled as multiple clusters, where all CPU -cores within a cluster is having the same architecture. -It is possible to have only a single CPU core within a CPU cluster. - -It's possible to define variants for dedicated use-cases. -Examples of such use-cases are: - -- Variant which enables non-secure builds for SoCs containing a security - processor. -- Variant enabling / changing the type of RAM used in by the build. +.. _hw_support_hierarchy: -A ``/`` is used as separator between the board name and the following: -SoC, CPU cluster, and variant identifiers. +Hardware support hierarchy +************************** -If a board contains only a single core SoC, then the SoC can be omitted when -building. +Zephyr's hardware support hierarchy has the following levels, from most to least +specific: -Let's say there is a board named ``plank`` with a single-core SoC ``soc1``. -The board including the identifier is: ``plank/soc1``. +- :term:`board`, which has one or more +- :term:`SoC`, each of which optionally belong to a +- :term:`SoC series`, which in turn may optionally belong to an +- :term:`SoC family`. Each SoC has one or more +- :term:`CPU cluster`, each containing one or more +- :term:`CPU core`, of a particular +- :term:`architecture` -As ``plank`` is a single SoC board, then the following is sufficient: ``plank`` -to use as board when building. +You can visualize the hierarchy in the diagram below: -If ``plank`` defines board variants, then those are identified by appending the -``/`` name after the SoC, for example to build for the ``foo`` variant, -use: ``plank/soc1/foo``, and if omitting the SoC use: ``plank//foo``. -Here the double ``//`` indicates to the build system that the SoC has been -omitted. +.. figure:: board/hierarchy.png + :width: 500px + :align: center + :alt: Hardware support Hierarchy -So to build hello world for ``plank``, variant ``foo``, you can do: + Hardware support Hierarchy -.. code-block:: console +Below are some examples of the hierarchy described in this section, in the form +of a :term:`board` per row with its corresponding hierarchy entries. Notice how +the :term:`SoC series` and :term:`SoC family` levels are not always used. - west build -b plank//foo samples/hello_world - -When using multi-core SoCs, the CPU cluster is identified after the SoC -identifier. +.. table:: -If ``soc1`` above has two cores, ``first`` and ``second``, then those are -identified as: ``plank/soc1/first`` and ``plank/soc1/second``. + +--------------------------------------------+--------------------------+-------------+--------------------+--------------------+----------------+----------------------+ + | :term:`board name` | :term:`board qualifiers` | :term:`SoC` | :term:`SoC Series` | :term:`SoC family` | CPU core | :term:`architecture` | + +============================================+==========================+=============+====================+====================+================+======================+ + | :ref:`nrf52dk ` | nrf52832 | nRF52832 | nRF52 | Nordic nRF | Arm Cortex-M4 | ARMv7-M | + +--------------------------------------------+--------------------------+-------------+--------------------+--------------------+----------------+----------------------+ + | :ref:`frdm_k64f ` | mk64f12 | MK64F12 | Kinetis K6x | NXP Kinetis | Arm Cortex-M4 | ARMv7-M | + +--------------------------------------------+--------------------------+-------------+--------------------+--------------------+----------------+----------------------+ + | :ref:`rv32m1_vega ` | openisa_rv32m1/ri5cy | RV32M1 | (Not used) | (Not used) | RI5CY | RISC-V RV32 | + +--------------------------------------------+--------------------------+-------------+--------------------+--------------------+----------------+----------------------+ + | :ref:`nrf5340dk ` | nrf5340/cpuapp | nRF5340 | nRF53 | Nordic nRF | Arm Cortex-M33 | ARMv8-M | + | +--------------------------+-------------+--------------------+--------------------+----------------+----------------------+ + | | nrf5340/cpunet | nRF5340 | nRF53 | Nordic nRF | Arm Cortex-M33 | ARMv8-M | + +--------------------------------------------+--------------------------+-------------+--------------------+--------------------+----------------+----------------------+ + | :ref:`mimx8mp_evk ` | mimx8ml8/a53 | i.MX8M Plus | i.MX8M | NXP i.MX | Arm Cortex-A53 | ARMv8-A | + | +--------------------------+-------------+--------------------+--------------------+----------------+----------------------+ + | | mimx8ml8/m7 | i.MX8M Plus | i.MX8M | NXP i.MX | Arm Cortex-M7 | ARMv7-M | + +--------------------------------------------+--------------------------+-------------+--------------------+--------------------+----------------+----------------------+ + +Additional details about terminology can be found in the next section. + +.. _board_terminology: + +Board terminology +***************** + +The previous section introduced the hierarchical manner in which Zephyr +classifies and implements hardware support. +This section focuses on the terminology used around hardware support, and in +particular when defining and working with boards and SoCs. + +The overall set of terms used around the concept of board in Zephyr is depicted +in the image below, which uses the :ref:`bl5340_dvk` board as reference. + +.. figure:: board/board-terminology.svg + :width: 500px + :align: center + :alt: Board terminology diagram -And similar to before, if the board has only a single SoC, the SoC can be -omitted, that is ``plank//first`` and ``plank//second`` is an identical short -form. + Board terminology diagram -.. _hw_support_hierarchy: +The diagram shows the different terms that are used to describe boards: -Boards, SoCs, etc. -****************** +- The :term:`board name`: ``bl5340_dvk`` +- The optional :term:`board revision`: ``1.2.0`` +- The :term:`board qualifiers`, that optionally describe the :term:`SoC`, + :term:`CPU cluster` and :term:`variant`: ``nrf5340/cpuapp/ns`` +- The :term:`board target`, which uniquely identifies a combination of the above + and can be used to specify the hardware to build for when using the tooling + provided by Zephyr: ``bl5340_dvk@1.2.0/nrf5340/cpuapp/ns`` -Zephyr's hardware support hierarchy has these layers, from most to least -specific: +Formally this can also be seen as +:samp:`{board name}[@{revision}][/{board qualifiers}]`, which can be extended to +:samp:`{board name}[@{revision}][/{SoC}[/{CPU cluster}][/{variant}]]`. -- Board: a specific board which usually corresponds to a physical board. - A board may contain multiple SoCs. - A build targets a specific CPU cluster on a board which has multiple - CPUs, be these in different SOCs or in a SOC with multiple AMP CPU - clusters. -- SoC: the exact system on a chip the board's CPU is part of -- SoC series: a smaller group of tightly related SoCs -- SoC family: a wider group of SoCs with similar characteristics -- CPU Cluster: a cluster of one or more CPU cores. -- CPU core: a particular CPU in an architecture -- Architecture: an instruction set architecture +If a board contains only one single-core SoC, then the SoC can be omitted from +the board target. This implies that if the board does not define any board +qualifiers, the board name can be used as a board target. Conversely, if +board qualifiers are part of the board definition, then the SoC can be omitted +by leaving it out but including the corresponding forward-slashes: ``//``. -You can visualize the hierarchy like this: +Continuing with the example above, The board :ref:`bl5340_dvk` is a single SoC +board where the SoC defines two CPU clusters: ``cpuapp`` and ``cpunet``. One of +the CPU clusters, ``cpuapp``, additionally defines a non-secure board variant, +``ns``. -.. figure:: board/hierarchy.png - :width: 500px - :align: center - :alt: Configuration Hierarchy +The board qualifiers ``nrf5340/cpuapp/ns`` can be read as: - Configuration Hierarchy -Here are some examples. Notice how the SoC series and family levels are -not always used. +- ``nrf5340``: The SoC, which is a Nordic nRF5340 dual-core SoC +- ``cpuapp``: The CPU cluster ``cpuapp``, which consists of a single Cortex-M33 + CPU core. The number of cores in a CPU cluster cannot be determined from the + board qualifiers. +- ``ns``: a variant, in this case ``ns`` is a common variant name is + Zephyr denoting a non-secure build for boards supporting :ref:`tfm`. -.. table:: +Not all SoCs define CPU clusters or variants. For example a simple board +like the :ref:`thingy52_nrf52832` contains a single SoC with no CPU clusters and +no variants. +For ``thingy52`` the board target ``thingy52/nrf52832`` can be read as: - +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ - | Board | Identifier | SoC | SoC Series | SoC family | CPU core | Architecture | - +============================================+=======================+=============+===============+===============+================+==============+ - | :ref:`nrf52dk ` | /nrf52832 | nRF52832 | nRF52 | Nordic nRF | Arm Cortex-M4 | Arm | - +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ - | :ref:`frdm_k64f ` | /mk64f12 | MK64F12 | Kinetis K6x | NXP Kinetis | Arm Cortex-M4 | Arm | - +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ - | :ref:`rv32m1_vega ` | /openisa_rv32m1/ri5cy | RV32M1 | (Not used) | (Not used) | RI5CY | RISC-V | - +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ - | :ref:`nrf5340dk ` | /nrf5340/cpuapp | nRF5340 | nRF53 | Nordic nRF | Arm Cortex-M33 | Arm | - | +-----------------------+-------------+---------------+---------------+----------------+--------------+ - | | /nrf5340/cpunet | nRF5340 | nRF53 | Nordic nRF | Arm Cortex-M33 | Arm | - +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ - | :ref:`mimx8mp_evk ` | /mimx8m/a53 | i.MX8M Plus | i.MXM8M A53 | NXP i.MX | Arm Cortex-A53 | Arm64 | - | +-----------------------+-------------+---------------+---------------+----------------+--------------+ - | | /mimx8m/m7 | i.MX8M Plus | i.MXM8MM M4 | NXP i.MX | Arm Cortex-M7 | Arm | - +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ +- ``thingy52``: board name. +- ``nrf52832``: The board qualifiers, in this case identical to the SoC, which + is a Nordic nRF52832. Make sure your SoC is supported From 961c985ee4a9c412fbf5da217ff3ed98ff762262 Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Thu, 1 Feb 2024 17:26:59 +0100 Subject: [PATCH 1045/2402] drivers: pwm: split up driver for MAX31790 into a MFD Split up the driver for the PWM controller MAX31790 into a multi function device driver. Signed-off-by: Benedikt Schmidt --- drivers/mfd/CMakeLists.txt | 1 + drivers/mfd/Kconfig | 1 + drivers/mfd/Kconfig.max31790 | 10 + drivers/mfd/mfd_max31790.c | 81 +++++++ drivers/pwm/Kconfig.max31790 | 4 +- drivers/pwm/pwm_max31790.c | 219 +++++------------- dts/bindings/mfd/maxim,max31790.yaml | 14 ++ ...,max31790.yaml => maxim,max31790-pwm.yaml} | 9 +- include/zephyr/drivers/mfd/max31790.h | 70 ++++++ tests/drivers/build_all/pwm/max31790.overlay | 9 +- tests/drivers/build_all/pwm/prj.conf | 2 + 11 files changed, 249 insertions(+), 171 deletions(-) create mode 100644 drivers/mfd/Kconfig.max31790 create mode 100644 drivers/mfd/mfd_max31790.c create mode 100644 dts/bindings/mfd/maxim,max31790.yaml rename dts/bindings/pwm/{maxim,max31790.yaml => maxim,max31790-pwm.yaml} (66%) create mode 100644 include/zephyr/drivers/mfd/max31790.h diff --git a/drivers/mfd/CMakeLists.txt b/drivers/mfd/CMakeLists.txt index 0b8e4f00304..135643a14a3 100644 --- a/drivers/mfd/CMakeLists.txt +++ b/drivers/mfd/CMakeLists.txt @@ -9,5 +9,6 @@ zephyr_library_sources_ifdef(CONFIG_MFD_NPM1300 mfd_npm1300.c) zephyr_library_sources_ifdef(CONFIG_MFD_NPM6001 mfd_npm6001.c) zephyr_library_sources_ifdef(CONFIG_MFD_AXP192 mfd_axp192.c) zephyr_library_sources_ifdef(CONFIG_MFD_AD5592 mfd_ad5592.c) +zephyr_library_sources_ifdef(CONFIG_MFD_MAX31790 mfd_max31790.c) zephyr_library_sources_ifdef(CONFIG_NXP_LP_FLEXCOMM mfd_nxp_lp_flexcomm.c) zephyr_library_sources_ifdef(CONFIG_MFD_BD8LB600FS mfd_bd8lb600fs.c) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 238e5645ab0..724359a8bc8 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -22,6 +22,7 @@ source "drivers/mfd/Kconfig.ad5592" source "drivers/mfd/Kconfig.axp192" source "drivers/mfd/Kconfig.bd8lb600fs" source "drivers/mfd/Kconfig.max20335" +source "drivers/mfd/Kconfig.max31790" source "drivers/mfd/Kconfig.nct38xx" source "drivers/mfd/Kconfig.npm1300" source "drivers/mfd/Kconfig.npm6001" diff --git a/drivers/mfd/Kconfig.max31790 b/drivers/mfd/Kconfig.max31790 new file mode 100644 index 00000000000..2c542982d9f --- /dev/null +++ b/drivers/mfd/Kconfig.max31790 @@ -0,0 +1,10 @@ +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX -License-Identifier: Apache-2.0 + +config MFD_MAX31790 + bool "Maxim Integrated MAX31790 I2C configurable PWM controller" + default y + depends on DT_HAS_MAXIM_MAX31790_ENABLED + select I2C + help + Enable driver for Maxim Integrated MAX31790. diff --git a/drivers/mfd/mfd_max31790.c b/drivers/mfd/mfd_max31790.c new file mode 100644 index 00000000000..f89bcc87fdd --- /dev/null +++ b/drivers/mfd/mfd_max31790.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT maxim_max31790 + +#include +#include +#include +#include +#include +#include + + +LOG_MODULE_REGISTER(max_max31790, CONFIG_MFD_LOG_LEVEL); + +struct max31790_config { + struct i2c_dt_spec i2c; +}; + +static void max31790_set_globalconfiguration_i2cwatchdog(uint8_t *destination, uint8_t value) +{ + uint8_t length = MAX37190_GLOBALCONFIGURATION_I2CWATCHDOG_LENGTH; + uint8_t pos = MAX37190_GLOBALCONFIGURATION_I2CWATCHDOG_POS; + + *destination &= ~GENMASK(pos + length - 1, pos); + *destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value); +} + +static int max31790_init(const struct device *dev) +{ + const struct max31790_config *config = dev->config; + int result; + uint8_t reg_value; + + if (!i2c_is_ready_dt(&config->i2c)) { + LOG_ERR("I2C device not ready"); + return -ENODEV; + } + + reg_value = 0; + reg_value &= ~MAX37190_GLOBALCONFIGURATION_STANDBY_BIT; + reg_value |= MAX37190_GLOBALCONFIGURATION_RESET_BIT; + reg_value |= MAX37190_GLOBALCONFIGURATION_BUSTIMEOUT_BIT; + reg_value &= ~MAX37190_GLOBALCONFIGURATION_OSCILLATORSELECTION_BIT; + max31790_set_globalconfiguration_i2cwatchdog(®_value, 0); + reg_value &= ~MAX37190_GLOBALCONFIGURATION_I2CWATCHDOGSTATUS_BIT; + + result = i2c_reg_write_byte_dt(&config->i2c, MAX37190_REGISTER_GLOBALCONFIGURATION, + reg_value); + if (result != 0) { + return result; + } + + k_sleep(K_USEC(MAX31790_RESET_TIMEOUT_IN_US)); + + result = i2c_reg_read_byte_dt(&config->i2c, MAX37190_REGISTER_GLOBALCONFIGURATION, + ®_value); + if (result != 0) { + return result; + } + + if ((reg_value & MAX37190_GLOBALCONFIGURATION_STANDBY_BIT) != 0) { + LOG_ERR("PWM controller is still in standby"); + return -ENODEV; + } + + return 0; +} + +#define MAX31790_INIT(inst) \ + static const struct max31790_config max31790_##inst##_config = { \ + .i2c = I2C_DT_SPEC_INST_GET(inst), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(inst, max31790_init, NULL, NULL, &max31790_##inst##_config, \ + POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, NULL); + +DT_INST_FOREACH_STATUS_OKAY(MAX31790_INIT); diff --git a/drivers/pwm/Kconfig.max31790 b/drivers/pwm/Kconfig.max31790 index f513d789277..928855fadc4 100644 --- a/drivers/pwm/Kconfig.max31790 +++ b/drivers/pwm/Kconfig.max31790 @@ -7,7 +7,7 @@ config PWM_MAX31790 bool "MAX31790 6-channel I2C-bus PWM controller" default y - depends on DT_HAS_MAXIM_MAX31790_ENABLED - select I2C + depends on DT_HAS_MAXIM_MAX31790_PWM_ENABLED + select MFD help Enable driver for MAX31790 6-channel I2C-bus PWM controller. diff --git a/drivers/pwm/pwm_max31790.c b/drivers/pwm/pwm_max31790.c index dab9ee58159..a655c8b10b7 100644 --- a/drivers/pwm/pwm_max31790.c +++ b/drivers/pwm/pwm_max31790.c @@ -4,68 +4,28 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT maxim_max31790 +#define DT_DRV_COMPAT maxim_max31790_pwm #include #include +#include #include #include +#include #include #include #include LOG_MODULE_REGISTER(pwm_max31790, CONFIG_PWM_LOG_LEVEL); -#define MAX31790_OSCILLATOR_FREQUENCY_IN_HZ 32768 -#define MAX31790_PWMTARGETDUTYCYCLE_MAXIMUM ((1 << 9) - 1) -#define MAX31790_CHANNEL_COUNT 6 - -struct max31790_config { +struct max31790_pwm_config { struct i2c_dt_spec i2c; }; -struct max31790_data { +struct max31790_pwm_data { struct k_mutex lock; }; -#define MAX37190_REGISTER_GLOBALCONFIGURATION 0x00 -#define MAX37190_REGISTER_PWMFREQUENCY 0x01 -#define MAX37190_REGISTER_FANCONFIGURATION(channel) (0x02 + channel) -#define MAX31790_REGISTER_PWMOUTTARGETDUTYCYCLEMSB(channel) (0x40 + 2 * channel) -#define MAX31790_REGISTER_FANDYNAMICS(channel) (0x08 + channel) -#define MAX31790_REGISTER_TACHTARGETCOUNTMSB(channel) (0x50 + 2 * channel) - -#define MAX37190_GLOBALCONFIGURATION_STANDBY_BIT BIT(7) -#define MAX37190_FANXCONFIGURATION_MONITOR_BIT BIT(4) -#define MAX37190_FANXCONFIGURATION_TACHINPUTENABLED_BIT BIT(3) -#define MAX37190_FANXCONFIGURATION_LOCKEDROTOR_BIT BIT(2) -#define MAX37190_FANXCONFIGURATION_LOCKEDROTORPOLARITY_BIT BIT(1) -#define MAX37190_FANXCONFIGURATION_TACH_BIT BIT(0) -#define MAX37190_FANXCONFIGURATION_MODE_BIT BIT(7) -#define MAX37190_FANXDYNAMICS_ASYMMETRICRATEOFCHANGE_BIT BIT(1) - -#define MAX37190_FANXDYNAMICS_SPEEDRANGE_LENGTH 3 -#define MAX37190_FANXDYNAMICS_SPEEDRANGE_POS 5 -#define MAX37190_FANXDYNAMICS_PWMRATEOFCHANGE_LENGTH 3 -#define MAX37190_FANXDYNAMICS_PWMRATEOFCHANGE_POS 2 -#define MAX37190_PWMFREQUENCY_PWM_LENGTH 4 -#define MAX37190_PWMFREQUENCY_PWM4TO6_POS 4 -#define MAX37190_PWMFREQUENCY_PWM1TO3_LENGTH 4 -#define MAX37190_PWMFREQUENCY_PWM1TO3_POS 0 -#define MAX37190_FANXCONFIGURATION_SPINUP_LENGTH 2 -#define MAX37190_FANXCONFIGURATION_SPINUP_POS 5 - -#define PWM_MAX31790_FLAG_SPEED_RANGE_GET(flags) \ - FIELD_GET(GENMASK(MAX37190_FANXDYNAMICS_SPEEDRANGE_LENGTH + \ - PWM_MAX31790_FLAG_SPEED_RANGE_POS - 1, \ - PWM_MAX31790_FLAG_SPEED_RANGE_POS), \ - flags) -#define PWM_MAX31790_FLAG_PWM_RATE_OF_CHANGE_GET(flags) \ - FIELD_GET(GENMASK(MAX37190_FANXDYNAMICS_PWMRATEOFCHANGE_LENGTH + \ - PWM_MAX31790_FLAG_PWM_RATE_OF_CHANGE_POS - 1, \ - PWM_MAX31790_FLAG_PWM_RATE_OF_CHANGE_POS), \ - flags) - static void max31790_set_fandynamics_speedrange(uint8_t *destination, uint8_t value) { uint8_t length = MAX37190_FANXDYNAMICS_SPEEDRANGE_LENGTH; @@ -110,54 +70,6 @@ static void max31790_set_fanconfiguration_spinup(uint8_t *destination, uint8_t v *destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value); } -static int max31790_read_register(const struct device *dev, uint8_t address, uint8_t *value) -{ - const struct max31790_config *config = dev->config; - int result; - - result = i2c_reg_read_byte_dt(&config->i2c, address, value); - if (result != 0) { - LOG_ERR("unable to read register 0x%02X, error %i", address, result); - } - - LOG_DBG("read value 0x%02X from register 0x%02X", *value, address); - - return result; -} - -static int max31790_write_register_uint8(const struct device *dev, uint8_t address, uint8_t value) -{ - const struct max31790_config *config = dev->config; - int result; - - LOG_DBG("writing value 0x%02X to register 0x%02X", value, address); - result = i2c_reg_write_byte_dt(&config->i2c, address, value); - if (result != 0) { - LOG_ERR("unable to write register 0x%02X, error %i", address, result); - } - - return result; -} - -static int max31790_write_register_uint16(const struct device *dev, uint8_t address, uint16_t value) -{ - const struct max31790_config *config = dev->config; - int result; - uint8_t buffer[] = { - address, - value >> 8, - value, - }; - - LOG_DBG("writing value 0x%04X to address 0x%02X", value, address); - result = i2c_write_dt(&config->i2c, buffer, sizeof(buffer)); - if (result != 0) { - LOG_ERR("unable to write to address 0x%02X, error %i", address, result); - } - - return result; -} - static bool max31790_convert_pwm_frequency_into_hz(uint16_t *result, uint8_t pwm_frequency) { switch (pwm_frequency) { @@ -252,28 +164,31 @@ static int max31790_set_cycles_internal(const struct device *dev, uint32_t chann uint32_t period_count, uint32_t pulse_count, pwm_flags_t flags) { + const struct max31790_pwm_config *config = dev->config; int result; uint8_t pwm_frequency_channel_value; uint8_t value_pwm_frequency; uint8_t value_fan_configuration; uint8_t value_fan_dynamics; - uint8_t value_speed_range = PWM_MAX31790_FLAG_SPEED_RANGE_GET(flags); - uint8_t value_pwm_rate_of_change = PWM_MAX31790_FLAG_PWM_RATE_OF_CHANGE_GET(flags); + uint8_t value_speed_range = MAX31790_FLAG_SPEED_RANGE_GET(flags); + uint8_t value_pwm_rate_of_change = MAX31790_FLAG_PWM_RATE_OF_CHANGE_GET(flags); + uint8_t buffer[3]; if (!max31790_convert_pwm_frequency_into_register(&pwm_frequency_channel_value, period_count)) { return -EINVAL; } - result = max31790_read_register(dev, MAX37190_REGISTER_PWMFREQUENCY, &value_pwm_frequency); + result = i2c_reg_read_byte_dt(&config->i2c, MAX37190_REGISTER_PWMFREQUENCY, + &value_pwm_frequency); if (result != 0) { return result; } max31790_set_pwmfrequency(&value_pwm_frequency, channel, pwm_frequency_channel_value); - result = max31790_write_register_uint8(dev, MAX37190_REGISTER_PWMFREQUENCY, - value_pwm_frequency); + result = i2c_reg_write_byte_dt(&config->i2c, MAX37190_REGISTER_PWMFREQUENCY, + value_pwm_frequency); if (result != 0) { return result; } @@ -299,46 +214,56 @@ static int max31790_set_cycles_internal(const struct device *dev, uint32_t chann if ((flags & PWM_MAX31790_FLAG_RPM_MODE) == 0) { LOG_DBG("PWM mode"); - uint16_t pwm_target_duty_cycle = - pulse_count * MAX31790_PWMTARGETDUTYCYCLE_MAXIMUM / period_count; + uint16_t tach_target_count = MAX31790_TACHTARGETCOUNT_MAXIMUM; value_fan_configuration &= ~MAX37190_FANXCONFIGURATION_MODE_BIT; + buffer[0] = MAX31790_REGISTER_TACHTARGETCOUNTMSB(channel); + sys_put_be16(tach_target_count << 5, buffer + 1); - result = max31790_write_register_uint16( - dev, MAX31790_REGISTER_PWMOUTTARGETDUTYCYCLEMSB(channel), - pwm_target_duty_cycle); - if (result != 0) { - return result; - } + result = i2c_write_dt(&config->i2c, buffer, sizeof(buffer)); } else { LOG_DBG("RPM mode"); value_fan_configuration |= MAX37190_FANXCONFIGURATION_MODE_BIT; + buffer[0] = MAX31790_REGISTER_TACHTARGETCOUNTMSB(channel); + sys_put_be16(pulse_count << 5, buffer + 1); - result = max31790_write_register_uint16( - dev, MAX31790_REGISTER_TACHTARGETCOUNTMSB(channel), pulse_count); - if (result != 0) { - return result; - } + result = i2c_write_dt(&config->i2c, buffer, sizeof(buffer)); } - result = max31790_write_register_uint8(dev, MAX37190_REGISTER_FANCONFIGURATION(channel), - value_fan_configuration); if (result != 0) { return result; } - result = max31790_write_register_uint8(dev, MAX31790_REGISTER_FANDYNAMICS(channel), - value_fan_dynamics); + result = i2c_reg_write_byte_dt(&config->i2c, MAX37190_REGISTER_FANCONFIGURATION(channel), + value_fan_configuration); if (result != 0) { return result; } + result = i2c_reg_write_byte_dt(&config->i2c, MAX31790_REGISTER_FANDYNAMICS(channel), + value_fan_dynamics); + if (result != 0) { + return result; + } + + if ((flags & PWM_MAX31790_FLAG_RPM_MODE) == 0) { + uint16_t pwm_target_duty_cycle = + pulse_count * MAX31790_PWMTARGETDUTYCYCLE_MAXIMUM / period_count; + buffer[0] = MAX31790_REGISTER_PWMOUTTARGETDUTYCYCLEMSB(channel); + sys_put_be16(pwm_target_duty_cycle << 7, buffer + 1); + + result = i2c_write_dt(&config->i2c, buffer, sizeof(buffer)); + if (result != 0) { + return result; + } + } + return 0; } static int max31790_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_count, uint32_t pulse_count, pwm_flags_t flags) { - struct max31790_data *data = dev->data; + struct max31790_pwm_data *data = dev->data; int result; LOG_DBG("set period %i with pulse %i for channel %i and flags 0x%04X", period_count, @@ -362,7 +287,8 @@ static int max31790_set_cycles(const struct device *dev, uint32_t channel, uint3 static int max31790_get_cycles_per_sec(const struct device *dev, uint32_t channel, uint64_t *cycles) { - struct max31790_data *data = dev->data; + const struct max31790_pwm_config *config = dev->config; + struct max31790_pwm_data *data = dev->data; int result; bool success; uint8_t pwm_frequency_register; @@ -375,9 +301,8 @@ static int max31790_get_cycles_per_sec(const struct device *dev, uint32_t channe } k_mutex_lock(&data->lock, K_FOREVER); - result = max31790_read_register(dev, MAX37190_REGISTER_GLOBALCONFIGURATION, - &pwm_frequency_register); - + result = i2c_reg_read_byte_dt(&config->i2c, MAX37190_REGISTER_GLOBALCONFIGURATION, + &pwm_frequency_register); if (result != 0) { k_mutex_unlock(&data->lock); return result; @@ -385,7 +310,6 @@ static int max31790_get_cycles_per_sec(const struct device *dev, uint32_t channe pwm_frequency = max31790_get_pwmfrequency(pwm_frequency_register, channel); success = max31790_convert_pwm_frequency_into_hz(&pwm_frequency_in_hz, pwm_frequency); - if (!success) { k_mutex_unlock(&data->lock); return -EINVAL; @@ -397,17 +321,15 @@ static int max31790_get_cycles_per_sec(const struct device *dev, uint32_t channe return 0; } -static const struct pwm_driver_api max31790_api = { +static const struct pwm_driver_api max31790_pwm_api = { .set_cycles = max31790_set_cycles, .get_cycles_per_sec = max31790_get_cycles_per_sec, }; -static int max31790_init(const struct device *dev) +static int max31790_pwm_init(const struct device *dev) { - const struct max31790_config *config = dev->config; - struct max31790_data *data = dev->data; - int result; - uint8_t reg_value; + const struct max31790_pwm_config *config = dev->config; + struct max31790_pwm_data *data = dev->data; k_mutex_init(&data->lock); @@ -416,45 +338,18 @@ static int max31790_init(const struct device *dev) return -ENODEV; } - result = max31790_read_register(dev, MAX37190_REGISTER_GLOBALCONFIGURATION, ®_value); - if (result != 0) { - return result; - } - - if ((reg_value & MAX37190_GLOBALCONFIGURATION_STANDBY_BIT) != 0) { - LOG_DBG("taking PWM controller out of standby"); - - reg_value &= ~MAX37190_GLOBALCONFIGURATION_STANDBY_BIT; - result = max31790_write_register_uint8(dev, MAX37190_REGISTER_GLOBALCONFIGURATION, - reg_value); - if (result != 0) { - return result; - } - - result = max31790_read_register(dev, MAX37190_REGISTER_GLOBALCONFIGURATION, - ®_value); - if (result != 0) { - return result; - } - - if ((reg_value & MAX37190_GLOBALCONFIGURATION_STANDBY_BIT) != 0) { - LOG_ERR("unable to take PWM controller out of standby"); - return -ENODEV; - } - } - return 0; } -#define MAX31790_INIT(inst) \ - static const struct max31790_config max31790_##inst##_config = { \ - .i2c = I2C_DT_SPEC_INST_GET(inst), \ +#define MAX31790_PWM_INIT(inst) \ + static const struct max31790_pwm_config max31790_pwm_##inst##_config = { \ + .i2c = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \ }; \ \ - static struct max31790_data max31790_##inst##_data; \ + static struct max31790_pwm_data max31790_pwm_##inst##_data; \ \ - DEVICE_DT_INST_DEFINE(inst, max31790_init, NULL, &max31790_##inst##_data, \ - &max31790_##inst##_config, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \ - &max31790_api); + DEVICE_DT_INST_DEFINE(inst, max31790_pwm_init, NULL, &max31790_pwm_##inst##_data, \ + &max31790_pwm_##inst##_config, POST_KERNEL, \ + CONFIG_PWM_INIT_PRIORITY, &max31790_pwm_api); -DT_INST_FOREACH_STATUS_OKAY(MAX31790_INIT); +DT_INST_FOREACH_STATUS_OKAY(MAX31790_PWM_INIT); diff --git a/dts/bindings/mfd/maxim,max31790.yaml b/dts/bindings/mfd/maxim,max31790.yaml new file mode 100644 index 00000000000..7d35b9f4e2a --- /dev/null +++ b/dts/bindings/mfd/maxim,max31790.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +description: Maxim MAX31790 6-channel I2C-bus PWM controller, MFD device + +compatible: "maxim,max31790" + +include: i2c-device.yaml + +bus: max31790 + +properties: + reg: + required: true diff --git a/dts/bindings/pwm/maxim,max31790.yaml b/dts/bindings/pwm/maxim,max31790-pwm.yaml similarity index 66% rename from dts/bindings/pwm/maxim,max31790.yaml rename to dts/bindings/pwm/maxim,max31790-pwm.yaml index e6d2ec17881..a663013140f 100644 --- a/dts/bindings/pwm/maxim,max31790.yaml +++ b/dts/bindings/pwm/maxim,max31790-pwm.yaml @@ -3,14 +3,13 @@ description: Maxim MAX31790 6-channel I2C-bus PWM controller -compatible: "maxim,max31790" +compatible: "maxim,max31790-pwm" -include: [pwm-controller.yaml, i2c-device.yaml, base.yaml] +include: [pwm-controller.yaml, base.yaml] -properties: - reg: - required: true +on-bus: max31790 +properties: "#pwm-cells": const: 2 diff --git a/include/zephyr/drivers/mfd/max31790.h b/include/zephyr/drivers/mfd/max31790.h new file mode 100644 index 00000000000..28085e301d3 --- /dev/null +++ b/include/zephyr/drivers/mfd/max31790.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_MAX31790_H_ +#define ZEPHYR_INCLUDE_DRIVERS_MFD_MAX31790_H_ + +#include +#include + +#define MAX31790_OSCILLATOR_FREQUENCY_IN_HZ 32768 +#define MAX31790_PWMTARGETDUTYCYCLE_MAXIMUM ((1 << 9) - 1) +#define MAX31790_TACHTARGETCOUNT_MAXIMUM ((1 << 11) - 1) +#define MAX31790_CHANNEL_COUNT 6 +#define MAX31790_RESET_TIMEOUT_IN_US 1000 + +#define MAX37190_REGISTER_GLOBALCONFIGURATION 0x00 +#define MAX37190_REGISTER_PWMFREQUENCY 0x01 +#define MAX37190_REGISTER_FANCONFIGURATION(channel) (0x02 + channel) +#define MAX31790_REGISTER_FANDYNAMICS(channel) (0x08 + channel) +#define MAX37190_REGISTER_FANFAULTSTATUS1 0x11 +#define MAX37190_REGISTER_TACHCOUNTMSB(channel) (0x18 + 2 * channel) +#define MAX31790_REGISTER_PWMOUTTARGETDUTYCYCLEMSB(channel) (0x40 + 2 * channel) +#define MAX31790_REGISTER_TACHTARGETCOUNTMSB(channel) (0x50 + 2 * channel) + +#define MAX37190_GLOBALCONFIGURATION_STANDBY_BIT BIT(7) +#define MAX37190_GLOBALCONFIGURATION_RESET_BIT BIT(6) +#define MAX37190_GLOBALCONFIGURATION_BUSTIMEOUT_BIT BIT(5) +#define MAX37190_GLOBALCONFIGURATION_OSCILLATORSELECTION_BIT BIT(3) +#define MAX37190_GLOBALCONFIGURATION_I2CWATCHDOGSTATUS_BIT BIT(0) +#define MAX37190_FANXCONFIGURATION_MONITOR_BIT BIT(4) +#define MAX37190_FANXCONFIGURATION_TACHINPUTENABLED_BIT BIT(3) +#define MAX37190_FANXCONFIGURATION_LOCKEDROTOR_BIT BIT(2) +#define MAX37190_FANXCONFIGURATION_LOCKEDROTORPOLARITY_BIT BIT(1) +#define MAX37190_FANXCONFIGURATION_TACH_BIT BIT(0) +#define MAX37190_FANXCONFIGURATION_MODE_BIT BIT(7) +#define MAX37190_FANXDYNAMICS_ASYMMETRICRATEOFCHANGE_BIT BIT(1) + +#define MAX37190_GLOBALCONFIGURATION_I2CWATCHDOG_LENGTH 2 +#define MAX37190_GLOBALCONFIGURATION_I2CWATCHDOG_POS 1 +#define MAX37190_FANXDYNAMICS_SPEEDRANGE_LENGTH 3 +#define MAX37190_FANXDYNAMICS_SPEEDRANGE_POS 5 +#define MAX37190_FANXDYNAMICS_PWMRATEOFCHANGE_LENGTH 3 +#define MAX37190_FANXDYNAMICS_PWMRATEOFCHANGE_POS 2 +#define MAX37190_PWMFREQUENCY_PWM_LENGTH 4 +#define MAX37190_PWMFREQUENCY_PWM4TO6_POS 4 +#define MAX37190_PWMFREQUENCY_PWM1TO3_LENGTH 4 +#define MAX37190_PWMFREQUENCY_PWM1TO3_POS 0 +#define MAX37190_FANXCONFIGURATION_SPINUP_LENGTH 2 +#define MAX37190_FANXCONFIGURATION_SPINUP_POS 5 + +#define MAX31790_FANXDYNAMCIS_SPEED_RANGE_GET(value) \ + FIELD_GET(GENMASK(MAX37190_FANXDYNAMICS_SPEEDRANGE_LENGTH + \ + MAX37190_FANXDYNAMICS_SPEEDRANGE_POS - 1, \ + MAX37190_FANXDYNAMICS_SPEEDRANGE_POS), \ + value) + +#define MAX31790_FLAG_SPEED_RANGE_GET(flags) \ + FIELD_GET(GENMASK(MAX37190_FANXDYNAMICS_SPEEDRANGE_LENGTH + \ + PWM_MAX31790_FLAG_SPEED_RANGE_POS - 1, \ + PWM_MAX31790_FLAG_SPEED_RANGE_POS), \ + flags) +#define MAX31790_FLAG_PWM_RATE_OF_CHANGE_GET(flags) \ + FIELD_GET(GENMASK(MAX37190_FANXDYNAMICS_PWMRATEOFCHANGE_LENGTH + \ + PWM_MAX31790_FLAG_PWM_RATE_OF_CHANGE_POS - 1, \ + PWM_MAX31790_FLAG_PWM_RATE_OF_CHANGE_POS), \ + flags) + +#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_MAX31790_H_ */ diff --git a/tests/drivers/build_all/pwm/max31790.overlay b/tests/drivers/build_all/pwm/max31790.overlay index b92274a1673..6163d6aa890 100644 --- a/tests/drivers/build_all/pwm/max31790.overlay +++ b/tests/drivers/build_all/pwm/max31790.overlay @@ -11,7 +11,12 @@ compatible = "maxim,max31790"; status = "okay"; reg = <0x20>; - pwm-controller; - #pwm-cells = <2>; + + max31790_max31790_pwm: max31790_max31790_pwm { + compatible = "maxim,max31790-pwm"; + status = "okay"; + pwm-controller; + #pwm-cells = <2>; + }; }; }; diff --git a/tests/drivers/build_all/pwm/prj.conf b/tests/drivers/build_all/pwm/prj.conf index 346c909b60c..88ad49a87c6 100644 --- a/tests/drivers/build_all/pwm/prj.conf +++ b/tests/drivers/build_all/pwm/prj.conf @@ -1 +1,3 @@ CONFIG_PWM=y +CONFIG_MFD_INIT_PRIORITY=80 +CONFIG_PWM_INIT_PRIORITY=81 From 04f38ffba28757388f38dce953487bf80e354346 Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Thu, 1 Feb 2024 17:50:01 +0100 Subject: [PATCH 1046/2402] drivers: sensor: add sensors for MAX31790 Add sensors for fan speed and fan fault for the PWM controller MAX31790. Signed-off-by: Benedikt Schmidt --- drivers/sensor/CMakeLists.txt | 1 + drivers/sensor/Kconfig | 1 + drivers/sensor/max31790/CMakeLists.txt | 6 + drivers/sensor/max31790/Kconfig | 25 ++++ drivers/sensor/max31790/max31790_fan_fault.c | 81 ++++++++++ drivers/sensor/max31790/max31790_fan_fault.h | 20 +++ drivers/sensor/max31790/max31790_fan_speed.c | 138 ++++++++++++++++++ drivers/sensor/max31790/max31790_fan_speed.h | 21 +++ .../sensor/maxim,max31790-fan-fault.yaml | 10 ++ .../sensor/maxim,max31790-fan-speed.yaml | 23 +++ include/zephyr/drivers/sensor/max31790.h | 16 ++ 11 files changed, 342 insertions(+) create mode 100644 drivers/sensor/max31790/CMakeLists.txt create mode 100644 drivers/sensor/max31790/Kconfig create mode 100644 drivers/sensor/max31790/max31790_fan_fault.c create mode 100644 drivers/sensor/max31790/max31790_fan_fault.h create mode 100644 drivers/sensor/max31790/max31790_fan_speed.c create mode 100644 drivers/sensor/max31790/max31790_fan_speed.h create mode 100644 dts/bindings/sensor/maxim,max31790-fan-fault.yaml create mode 100644 dts/bindings/sensor/maxim,max31790-fan-speed.yaml create mode 100644 include/zephyr/drivers/sensor/max31790.h diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 86f65c04ee4..d553ecd4625 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -96,6 +96,7 @@ add_subdirectory_ifdef(CONFIG_LTR_F216A ltrf216a) add_subdirectory_ifdef(CONFIG_MAX17055 max17055) add_subdirectory_ifdef(CONFIG_MAX17262 max17262) add_subdirectory_ifdef(CONFIG_MAX30101 max30101) +add_subdirectory_ifdef(CONFIG_MAX31790_SENSOR max31790) add_subdirectory_ifdef(CONFIG_MAX31855 max31855) add_subdirectory_ifdef(CONFIG_MAX31865 max31865) add_subdirectory_ifdef(CONFIG_MAX31875 max31875) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index f939950d01c..fa956332534 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -176,6 +176,7 @@ source "drivers/sensor/ltrf216a/Kconfig" source "drivers/sensor/max17055/Kconfig" source "drivers/sensor/max17262/Kconfig" source "drivers/sensor/max30101/Kconfig" +source "drivers/sensor/max31790/Kconfig" source "drivers/sensor/max31855/Kconfig" source "drivers/sensor/max31865/Kconfig" source "drivers/sensor/max31875/Kconfig" diff --git a/drivers/sensor/max31790/CMakeLists.txt b/drivers/sensor/max31790/CMakeLists.txt new file mode 100644 index 00000000000..8dfdccb564d --- /dev/null +++ b/drivers/sensor/max31790/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources_ifdef(CONFIG_MAX31790_FAN_SPEED max31790_fan_speed.c) +zephyr_library_sources_ifdef(CONFIG_MAX31790_FAN_FAULT max31790_fan_fault.c) diff --git a/drivers/sensor/max31790/Kconfig b/drivers/sensor/max31790/Kconfig new file mode 100644 index 00000000000..ef703e4a69c --- /dev/null +++ b/drivers/sensor/max31790/Kconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +config MAX31790_SENSOR + bool "MAX31790 sensors" + default y + depends on MAX31790_FAN_SPEED || MAX31790_FAN_FAULT + help + Enable sensors for the MAX31790 PWM controller. + +config MAX31790_FAN_SPEED + bool "MAX31790 fan speed sensor" + default y + depends on DT_HAS_MAXIM_MAX31790_FAN_SPEED_ENABLED + select MFD + help + Enable driver for the MAX31790 fan speed sensor. + +config MAX31790_FAN_FAULT + bool "MAX31790 fan fault sensor" + default y + depends on DT_HAS_MAXIM_MAX31790_FAN_FAULT_ENABLED + select MFD + help + Enable driver for the MAX31790 fan fault sensor. diff --git a/drivers/sensor/max31790/max31790_fan_fault.c b/drivers/sensor/max31790/max31790_fan_fault.c new file mode 100644 index 00000000000..ec25000a761 --- /dev/null +++ b/drivers/sensor/max31790/max31790_fan_fault.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT maxim_max31790_fan_fault + +#include +#include +#include +#include + +#include "max31790_fan_fault.h" + +LOG_MODULE_REGISTER(MAX31790_FAN_FAULT, CONFIG_SENSOR_LOG_LEVEL); + +static int max31790_fan_fault_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + const struct max31790_fan_fault_config *config = dev->config; + struct max31790_fan_fault_data *data = dev->data; + int result; + uint8_t value; + + __ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL); + + result = i2c_reg_read_byte_dt(&config->i2c, MAX37190_REGISTER_FANFAULTSTATUS1, &value); + if (result != 0) { + return result; + } + + data->value = value & 0x3F; + + return 0; +} + +static int max31790_fan_fault_channel_get(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + struct max31790_fan_fault_data *data = dev->data; + + if ((enum sensor_channel_max31790)chan != SENSOR_CHAN_MAX31790_FAN_FAULT) { + LOG_ERR("%s: requesting unsupported channel %i", dev->name, chan); + return -ENOTSUP; + } + + val->val1 = data->value; + val->val2 = 0; + return 0; +} + +static const struct sensor_driver_api max31790_fan_fault_api = { + .sample_fetch = max31790_fan_fault_sample_fetch, + .channel_get = max31790_fan_fault_channel_get, +}; + +static int max31790_fan_fault_init(const struct device *dev) +{ + const struct max31790_fan_fault_config *config = dev->config; + + if (!i2c_is_ready_dt(&config->i2c)) { + LOG_ERR("I2C device not ready"); + return -ENODEV; + } + + return 0; +} + +#define MAX31790_FAN_FAULT_INIT(inst) \ + static const struct max31790_fan_fault_config max31790_fan_fault_##inst##_config = { \ + .i2c = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \ + }; \ + \ + static struct max31790_fan_fault_data max31790_fan_fault_##inst##_data; \ + \ + SENSOR_DEVICE_DT_INST_DEFINE(inst, max31790_fan_fault_init, NULL, \ + &max31790_fan_fault_##inst##_data, \ + &max31790_fan_fault_##inst##_config, POST_KERNEL, \ + CONFIG_SENSOR_INIT_PRIORITY, &max31790_fan_fault_api); + +DT_INST_FOREACH_STATUS_OKAY(MAX31790_FAN_FAULT_INIT); diff --git a/drivers/sensor/max31790/max31790_fan_fault.h b/drivers/sensor/max31790/max31790_fan_fault.h new file mode 100644 index 00000000000..6045652a549 --- /dev/null +++ b/drivers/sensor/max31790/max31790_fan_fault.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_MAX31790_MAX31790_FAN_FAULT_H_ +#define ZEPHYR_DRIVERS_SENSOR_MAX31790_MAX31790_FAN_FAULT_H_ + +#include + +struct max31790_fan_fault_config { + struct i2c_dt_spec i2c; +}; + +struct max31790_fan_fault_data { + uint16_t value; +}; + +#endif /* ZEPHYR_DRIVERS_SENSOR_MAX31790_MAX31790_FAN_FAULT_H_ */ diff --git a/drivers/sensor/max31790/max31790_fan_speed.c b/drivers/sensor/max31790/max31790_fan_speed.c new file mode 100644 index 00000000000..b0db008d8dc --- /dev/null +++ b/drivers/sensor/max31790/max31790_fan_speed.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT maxim_max31790_fan_speed + +#include +#include +#include +#include + +#include "max31790_fan_speed.h" + +#define FACTOR_RPM_TO_HZ 60 +#define TACH_COUNT_FREQUENCY (MAX31790_OSCILLATOR_FREQUENCY_IN_HZ / 4) +#define TACH_COUNTS_PER_REVOLUTION 2 + +LOG_MODULE_REGISTER(MAX31790_FAN_SPEED, CONFIG_SENSOR_LOG_LEVEL); + +static int max31790_fan_speed_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + const struct max31790_fan_speed_config *config = dev->config; + struct max31790_fan_speed_data *data = dev->data; + uint16_t tach_count; + uint8_t fan_dynamics; + uint8_t number_tach_periods_counted; + uint8_t speed_range; + uint8_t register_address; + int result; + + __ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL); + + register_address = MAX37190_REGISTER_TACHCOUNTMSB(config->channel_id); + result = i2c_write_read_dt(&config->i2c, ®ister_address, sizeof(register_address), + &tach_count, sizeof(tach_count)); + tach_count = sys_be16_to_cpu(tach_count); + if (result != 0) { + return result; + } + + result = i2c_reg_read_byte_dt( + &config->i2c, MAX31790_REGISTER_FANDYNAMICS(config->channel_id), &fan_dynamics); + if (result != 0) { + return result; + } + + tach_count = tach_count >> 5; + speed_range = MAX31790_FANXDYNAMCIS_SPEED_RANGE_GET(fan_dynamics); + + switch (speed_range) { + case 0: + number_tach_periods_counted = 1; + break; + case 1: + number_tach_periods_counted = 2; + break; + case 2: + number_tach_periods_counted = 4; + break; + case 3: + number_tach_periods_counted = 8; + break; + case 4: + number_tach_periods_counted = 16; + break; + case 5: + __fallthrough; + case 6: + __fallthrough; + case 7: + number_tach_periods_counted = 32; + break; + default: + LOG_ERR("%s: invalid speed range %i", dev->name, speed_range); + return -EINVAL; + } + + if (tach_count == 0) { + LOG_WRN("%s: tach count is zero", dev->name); + data->rpm = UINT16_MAX; + } else { + LOG_DBG("%s: %i tach periods counted, %i tach count", dev->name, + number_tach_periods_counted, tach_count); + data->rpm = FACTOR_RPM_TO_HZ * TACH_COUNT_FREQUENCY * number_tach_periods_counted / + (tach_count * TACH_COUNTS_PER_REVOLUTION); + } + + return 0; +} + +static int max31790_fan_speed_channel_get(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + struct max31790_fan_speed_data *data = dev->data; + + if (chan != SENSOR_CHAN_RPM) { + LOG_ERR("%s: requesting unsupported channel %i", dev->name, chan); + return -ENOTSUP; + } + + val->val1 = data->rpm; + val->val2 = 0; + return 0; +} + +static const struct sensor_driver_api max31790_fan_speed_api = { + .sample_fetch = max31790_fan_speed_sample_fetch, + .channel_get = max31790_fan_speed_channel_get, +}; + +static int max31790_fan_speed_init(const struct device *dev) +{ + const struct max31790_fan_speed_config *config = dev->config; + + if (!i2c_is_ready_dt(&config->i2c)) { + LOG_ERR("I2C device not ready"); + return -ENODEV; + } + + return 0; +} + +#define MAX31790_FAN_SPEED_INIT(inst) \ + static const struct max31790_fan_speed_config max31790_fan_speed_##inst##_config = { \ + .i2c = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \ + .channel_id = DT_INST_PROP(inst, channel) - 1, \ + }; \ + \ + static struct max31790_fan_speed_data max31790_fan_speed_##inst##_data; \ + \ + SENSOR_DEVICE_DT_INST_DEFINE(inst, max31790_fan_speed_init, NULL, \ + &max31790_fan_speed_##inst##_data, \ + &max31790_fan_speed_##inst##_config, POST_KERNEL, \ + CONFIG_SENSOR_INIT_PRIORITY, &max31790_fan_speed_api); + +DT_INST_FOREACH_STATUS_OKAY(MAX31790_FAN_SPEED_INIT); diff --git a/drivers/sensor/max31790/max31790_fan_speed.h b/drivers/sensor/max31790/max31790_fan_speed.h new file mode 100644 index 00000000000..17d4e9c6787 --- /dev/null +++ b/drivers/sensor/max31790/max31790_fan_speed.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_MAX31790_MAX31790_FAN_SPEED_H_ +#define ZEPHYR_DRIVERS_SENSOR_MAX31790_MAX31790_FAN_SPEED_H_ + +#include + +struct max31790_fan_speed_config { + struct i2c_dt_spec i2c; + uint8_t channel_id; +}; + +struct max31790_fan_speed_data { + uint16_t rpm; +}; + +#endif /* ZEPHYR_DRIVERS_SENSOR_MAX31790_MAX31790_FAN_SPEED_H_ */ diff --git a/dts/bindings/sensor/maxim,max31790-fan-fault.yaml b/dts/bindings/sensor/maxim,max31790-fan-fault.yaml new file mode 100644 index 00000000000..529557e372f --- /dev/null +++ b/dts/bindings/sensor/maxim,max31790-fan-fault.yaml @@ -0,0 +1,10 @@ +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +description: fan fault measurement of Maxim Integrated MAX31790 PWM Controller + +compatible: "maxim,max31790-fan-fault" + +include: [sensor-device.yaml] + +on-bus: max31790 diff --git a/dts/bindings/sensor/maxim,max31790-fan-speed.yaml b/dts/bindings/sensor/maxim,max31790-fan-speed.yaml new file mode 100644 index 00000000000..709f1730a52 --- /dev/null +++ b/dts/bindings/sensor/maxim,max31790-fan-speed.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +description: fan speed measurement of Maxim Integrated MAX31790 PWM Controller + +compatible: "maxim,max31790-fan-speed" + +include: [sensor-device.yaml] + +on-bus: max31790 + +properties: + channel: + type: int + enum: + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + required: true + description: PWM channel number diff --git a/include/zephyr/drivers/sensor/max31790.h b/include/zephyr/drivers/sensor/max31790.h new file mode 100644 index 00000000000..d4f06ffc1f1 --- /dev/null +++ b/include/zephyr/drivers/sensor/max31790.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_MAX31790_H_ +#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_MAX31790_H_ + +#include + +/* MAX31790 specific channels */ +enum sensor_channel_max31790 { + SENSOR_CHAN_MAX31790_FAN_FAULT = SENSOR_CHAN_PRIV_START, +}; + +#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_MAX31790_H_ */ From 370c977b4e71f716f121da2de3feb00814b63f86 Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Wed, 14 Feb 2024 09:21:47 +0100 Subject: [PATCH 1047/2402] tests: drivers: build_all: sensor: add sensors of MAX31790 Add instances for the senors of MAX31790 to the build all tests. Signed-off-by: Benedikt Schmidt --- tests/drivers/build_all/sensor/i2c.dtsi | 47 +++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/tests/drivers/build_all/sensor/i2c.dtsi b/tests/drivers/build_all/sensor/i2c.dtsi index a949cc1b289..6b6a6a98721 100644 --- a/tests/drivers/build_all/sensor/i2c.dtsi +++ b/tests/drivers/build_all/sensor/i2c.dtsi @@ -938,3 +938,50 @@ test_i2c_tsl2591: tsl2591@84 { reg = <0x84>; int-gpios = <&test_gpio 0 0>; }; + +test_i2c_max31790: max31790@85 { + compatible = "maxim,max31790"; + status = "okay"; + reg = <0x85>; + + max31790_fan_fault: max31790_fan_fault { + compatible = "maxim,max31790-fan-fault"; + status = "okay"; + }; + + max31790_fan_speed_1: max31790_fan_speed_1 { + compatible = "maxim,max31790-fan-speed"; + status = "okay"; + channel = <1>; + }; + + max31790_fan_speed_2: max31790_fan_speed_2 { + compatible = "maxim,max31790-fan-speed"; + status = "okay"; + channel = <2>; + }; + + max31790_fan_speed_3: max31790_fan_speed_3 { + compatible = "maxim,max31790-fan-speed"; + status = "okay"; + channel = <3>; + }; + + max31790_fan_speed_4: max31790_fan_speed_4 { + compatible = "maxim,max31790-fan-speed"; + status = "okay"; + channel = <4>; + }; + + max31790_fan_speed_5: max31790_fan_speed_5 { + compatible = "maxim,max31790-fan-speed"; + status = "okay"; + channel = <5>; + }; + + max31790_fan_speed_6: max31790_fan_speed_6 { + compatible = "maxim,max31790-fan-speed"; + status = "okay"; + channel = <6>; + }; +}; From e2058a953707c93cab249575db67aecd184b3465 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Thu, 22 Feb 2024 14:02:14 -0800 Subject: [PATCH 1048/2402] pm: Fix a corner case when policy returns NULL When the policy returns NULL pm_system_suspend was assuming that the current state in z_cpus_pm_state was ACTIVE, since that is the state set after the core wakes and return to this function. The problem is that in cases where the cpu does not preserve the context, and returns to this function, z_cpus_pm_state has the value of the last state used and the cpu use it again. Fix it setting z_cpus_pm_state to ACTIVE every time the policy returns NULL. Signed-off-by: Flavio Ceolin --- subsys/pm/pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/subsys/pm/pm.c b/subsys/pm/pm.c index 2982324441e..2b17817e0bb 100644 --- a/subsys/pm/pm.c +++ b/subsys/pm/pm.c @@ -183,6 +183,8 @@ bool pm_system_suspend(int32_t ticks) info = pm_policy_next_state(id, ticks); if (info != NULL) { z_cpus_pm_state[id] = *info; + } else { + z_cpus_pm_state[id].state = PM_STATE_ACTIVE; } } k_spin_unlock(&pm_forced_state_lock, key); From 69648c17d71f62f341dc1166c05cca68a187121d Mon Sep 17 00:00:00 2001 From: Johan Lafon Date: Tue, 5 Mar 2024 13:47:47 +0100 Subject: [PATCH 1049/2402] cmake: dts: look for allowed dts overlays file presence in board/ Hardware model v2 allows the usage of _.overlay and any valid __.overlay dts overlays in the board/ directory but CMake was only looking for the most specific __.overlay overlay file. This commit allows CMake to look for the presence of any allowed overlay file to fix this issue. Tested by building the hello_world sample with the Olimex board lora_stm32wl_devkit revision C. The following line wasn't appearing before in build log and now does: "-- Found devicetree overlay: /olimex_lora_stm32wl_devkit_C.overlay" Signed-off-by: Johan Lafon --- cmake/modules/dts.cmake | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/cmake/modules/dts.cmake b/cmake/modules/dts.cmake index bf19e602f6d..4c34d9b45e6 100644 --- a/cmake/modules/dts.cmake +++ b/cmake/modules/dts.cmake @@ -133,16 +133,18 @@ if(NOT DEFINED DTS_SOURCE) endif() if(EXISTS ${DTS_SOURCE}) - # We found a devicetree. Check for a board revision overlay. - if(DEFINED BOARD_REVISION) - zephyr_build_string(dts_board_string BOARD ${BOARD} - BOARD_IDENTIFIER ${BOARD_IDENTIFIER} - BOARD_REVISION ${BOARD_REVISION} - ) - if(EXISTS ${BOARD_DIR}/${dts_board_string}.overlay) - list(APPEND DTS_SOURCE ${BOARD_DIR}/${dts_board_string}.overlay) - endif() - endif() + # We found a devicetree. Append all relevant dts overlays we can find... + zephyr_file(CONF_FILES ${BOARD_DIR} DTS DTS_SOURCE) + + zephyr_file( + CONF_FILES ${BOARD_DIR} + DTS no_rev_suffix_dts_board_overlays + BOARD ${BOARD} + BOARD_IDENTIFIER ${BOARD_IDENTIFIER} + ) + + # ...but remove the ones that do not include the revision suffix + list(REMOVE_ITEM DTS_SOURCE ${no_rev_suffix_dts_board_overlays}) else() # If we don't have a devicetree, provide an empty stub set(DTS_SOURCE ${ZEPHYR_BASE}/boards/common/stub.dts) From e0b748a6ce4ea70be1c25df533e4448c5fb9a2e8 Mon Sep 17 00:00:00 2001 From: Mateusz Michalek Date: Tue, 19 Mar 2024 09:47:50 +0100 Subject: [PATCH 1050/2402] dts: arm: nordic: nrf54l15 write block size write-block-size correction. Signed-off-by: Mateusz Michalek --- dts/arm/nordic/nrf54l_common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/arm/nordic/nrf54l_common.dtsi b/dts/arm/nordic/nrf54l_common.dtsi index 415f2471174..1c5345afc93 100644 --- a/dts/arm/nordic/nrf54l_common.dtsi +++ b/dts/arm/nordic/nrf54l_common.dtsi @@ -18,7 +18,7 @@ rram0: rram@0 { compatible = "soc-nv-flash"; erase-block-size = <4096>; - write-block-size = <1>; + write-block-size = <16>; }; }; }; From 9104afa069b70cc01145cd1ec2c4e07396ef5f34 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Mon, 18 Mar 2024 11:49:03 +0100 Subject: [PATCH 1051/2402] cmake: change check_init_priorities target into a post build command Fixes: #70359 Remove check_init_priorities target and instead create a post build command and place the post build command on native_runner_executable, if that target is the final target, else use the normal post build list for Zephyr build target. Signed-off-by: Torsten Rasmussen --- CMakeLists.txt | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 09a4ec6b55d..6c44e41c810 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1812,12 +1812,13 @@ if(NOT CMAKE_C_COMPILER_ID STREQUAL "ARMClang") ) if(CONFIG_CHECK_INIT_PRIORITIES) - add_custom_target( - check_init_priorities - ALL - COMMAND ${check_init_priorities_command} - DEPENDS ${check_init_priorities_dependencies} - ) + if(TARGET native_runner_executable) + add_custom_command(TARGET native_runner_executable POST_BUILD + COMMAND ${check_init_priorities_command} + ) + else() + list(APPEND post_build_commands COMMAND ${check_init_priorities_command}) + endif() endif() add_custom_target( From 9fe86b7dfee1b7c960c53f73b7673670465386c0 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Mon, 18 Mar 2024 10:00:08 +0200 Subject: [PATCH 1052/2402] samples: net: cellular_modem: improve nRF9160 DK configurations - Async UART would start receiving some data incorrectly without HW RX byte counting at baud rates above 115200. - Increase the UART buffer sizes to be able to receive whole UART TXs of 1500 bytes sent by SLM at once. - Remove the Kconfig items whose definition is now redundant. Signed-off-by: Tomi Fontanilles --- .../net/cellular_modem/boards/nrf9160dk_nrf52840.conf | 10 +++++----- .../cellular_modem/boards/nrf9160dk_nrf9160_ns.conf | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf b/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf index 2af3b6d2a41..161f2d7176b 100644 --- a/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf +++ b/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf @@ -1,13 +1,13 @@ CONFIG_UART_ASYNC_API=y +# Enable HW RX byte counting. This especially matters at higher baud rates. +CONFIG_UART_1_NRF_HW_ASYNC=y +CONFIG_UART_1_NRF_HW_ASYNC_TIMER=1 # Align with the Serial LTE Modem (SLM) application. CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE=1500 -CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES=1500 - -# Allow large UART TXs to go through @115200. -CONFIG_MODEM_BACKEND_UART_ASYNC_TRANSMIT_TIMEOUT_MS=200 +CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES=6000 # Print logs and printk() output on uart0. -CONFIG_LOG=y CONFIG_LOG_BACKEND_UART=y + CONFIG_MODEM_LOG_LEVEL_DBG=y diff --git a/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf b/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf index 441a5395ca1..b0866d8c86c 100644 --- a/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf +++ b/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf @@ -1,16 +1,16 @@ CONFIG_UART_ASYNC_API=y +# Enable HW RX byte counting. This especially matters at higher baud rates. +CONFIG_UART_1_NRF_HW_ASYNC=y +CONFIG_UART_1_NRF_HW_ASYNC_TIMER=1 # Align with the Serial LTE Modem (SLM) application. CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE=1500 -CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES=1500 - -# Allow large UART TXs to go through @115200. -CONFIG_MODEM_BACKEND_UART_ASYNC_TRANSMIT_TIMEOUT_MS=200 +CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES=6000 # Prevent sockets getting offloaded to the modem. CONFIG_NET_SOCKETS_OFFLOAD=n # Print logs and printk() output on uart0. -CONFIG_LOG=y CONFIG_LOG_BACKEND_UART=y + CONFIG_MODEM_LOG_LEVEL_DBG=y From f1fdf461f29465a451965687b570704a725b4b58 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Mon, 18 Mar 2024 10:03:58 +0200 Subject: [PATCH 1053/2402] samples: net: cellular_modem: set a RCVTIMEO to echoed packets So that the sample does not get stuck forever waiting for an echo packet that will never come. Signed-off-by: Tomi Fontanilles --- samples/net/cellular_modem/prj.conf | 3 +++ samples/net/cellular_modem/src/main.c | 17 +++++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/samples/net/cellular_modem/prj.conf b/samples/net/cellular_modem/prj.conf index 3bd03d662d6..c21435f3b6d 100644 --- a/samples/net/cellular_modem/prj.conf +++ b/samples/net/cellular_modem/prj.conf @@ -8,6 +8,7 @@ CONFIG_NET_L2_PPP=y CONFIG_NET_IPV4=y CONFIG_NET_UDP=y CONFIG_NET_SOCKETS=y +CONFIG_NET_CONTEXT_RCVTIMEO=y # DNS CONFIG_DNS_RESOLVER=y @@ -26,4 +27,6 @@ CONFIG_MODEM_CELLULAR=y # Logging CONFIG_LOG=y CONFIG_MODEM_MODULES_LOG_LEVEL_DBG=y +# For extra verbosity #CONFIG_MODEM_CMUX_LOG_LEVEL_DBG=y +#CONFIG_LOG_BUFFER_SIZE=65536 diff --git a/samples/net/cellular_modem/src/main.c b/samples/net/cellular_modem/src/main.c index b7e738d13e5..c951ac6bbb2 100644 --- a/samples/net/cellular_modem/src/main.c +++ b/samples/net/cellular_modem/src/main.c @@ -144,6 +144,15 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t return -1; } + { + const struct timeval tv = { .tv_sec = 10 }; + + if (zsock_setsockopt(socket_fd, SOL_SOCKET, SO_RCVTIMEO, &tv, sizeof(tv)) < 0) { + printk("Failed to set socket receive timeout (%d)\n", errno); + return -1; + } + } + printk("Socket opened\n"); *port = htons(SAMPLE_TEST_ENDPOINT_UDP_ECHO_PORT); @@ -163,7 +172,11 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t printk("Receiving echoed packet\n"); ret = zsock_recv(socket_fd, sample_recv_buffer, sizeof(sample_recv_buffer), 0); if (ret != sizeof(sample_test_packet)) { - printk("Echoed sample test packet has incorrect size\n"); + if (ret == -1) { + printk("Failed to receive echoed sample test packet (%d)\n", errno); + } else { + printk("Echoed sample test packet has incorrect size (%d)\n", ret); + } continue; } @@ -245,7 +258,7 @@ int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint packets_received = sample_recv_buffer[0]; packets_dropped = sample_recv_buffer[1]; - printk("Server received %u packets\n", packets_received); + printk("Server received %u/%u packets\n", packets_received, packets_sent); printk("Server dropped %u packets\n", packets_dropped); printk("Time elapsed sending packets %ums\n", send_end_ms - send_start_ms); printk("Throughput %u bytes/s\n", From e48fe49a70afba3b6f1b77262ace42dc55f44b8a Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 18 Mar 2024 07:57:49 -0300 Subject: [PATCH 1054/2402] soc: esp32s3: appcpu: add sram dts information Make sure SoC has defined RAM size. Signed-off-by: Sylvio Alves --- dts/xtensa/espressif/esp32s3/esp32s3_appcpu.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_appcpu.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_appcpu.dtsi index c405bfedecd..3ed7a5b6508 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_appcpu.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_appcpu.dtsi @@ -5,3 +5,8 @@ */ #include "esp32s3_common.dtsi" + +&sram0 { + reg = <0x3fc88000 DT_SIZE_K(10)>; + status = "okay"; +}; From 139a40098b01459689a3a51f60a63e63f6e21dd1 Mon Sep 17 00:00:00 2001 From: Nithin Ramesh Myliattil Date: Mon, 18 Mar 2024 10:31:59 +0100 Subject: [PATCH 1055/2402] Tests: Bluetooth: Host: update rpa expired bsim to cover more use cases rpa expired bsim is refactored so that every rpa rotation, one of the adv set belong to an adv_id returns false based on adv_index. In turn all adv sets under the same adv_Id continues with old rpa. Signed-off-by: Nithin Ramesh Myliattil --- .../privacy/peripheral/src/dut_rpa_expired.c | 84 ++++++++----------- .../peripheral/src/tester_rpa_expired.c | 32 +++++-- 2 files changed, 60 insertions(+), 56 deletions(-) diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/src/dut_rpa_expired.c b/tests/bsim/bluetooth/host/privacy/peripheral/src/dut_rpa_expired.c index 9e6b99d537d..124900fad5f 100644 --- a/tests/bsim/bluetooth/host/privacy/peripheral/src/dut_rpa_expired.c +++ b/tests/bsim/bluetooth/host/privacy/peripheral/src/dut_rpa_expired.c @@ -34,11 +34,25 @@ static struct bt_le_ext_adv *adv_set[CONFIG_BT_EXT_ADV_MAX_ADV_SET]; BT_DATA_BYTES(BT_DATA_MANUFACTURER_DATA, ADV_SET_INDEX_4), }; -bool rpa_expired_cb_returns_true(struct bt_le_ext_adv *adv) +bool rpa_expired_cb(struct bt_le_ext_adv *adv) { - /* Return true to rotate the current RPA */ - int err; - struct bt_le_ext_adv_info info; + /* Return true to rotate the current RPA. + * Return false to continue with old RPA. + */ + int err; + struct bt_le_ext_adv_info info; + static int rpa_count = -1; + static int64_t old_time; + static int64_t rpa_timeout_ms; + int64_t diff_ms; + + diff_ms = k_uptime_get() - old_time; + rpa_timeout_ms = CONFIG_BT_RPA_TIMEOUT * MSEC_PER_SEC; + + if (diff_ms >= rpa_timeout_ms) { + rpa_count++; + old_time = k_uptime_get(); + } err = bt_le_ext_adv_get_info(adv, &info); if (err) { @@ -46,33 +60,25 @@ bool rpa_expired_cb_returns_true(struct bt_le_ext_adv *adv) } printk("%s advertiser[%d] RPA %s\n", __func__, info.id, bt_addr_le_str(info.addr)); - return true; -} - -bool rpa_expired_cb_returns_false(struct bt_le_ext_adv *adv) -{ - /* Return false not to rotate the current RPA */ - int err; - struct bt_le_ext_adv_info info; - - err = bt_le_ext_adv_get_info(adv, &info); - if (err) { + /* Every rpa rotation one of the adv set returns false based on adv index */ + if (rpa_count == bt_le_ext_adv_get_index(adv)) { + printk("adv index %d returns false\n", bt_le_ext_adv_get_index(adv)); + if (rpa_count == CONFIG_BT_EXT_ADV_MAX_ADV_SET - 1) { + /* Reset RPA counter */ + rpa_count = -1; + } return false; } - printk("%s advertiser[%d] RPA %s\n", __func__, info.id, bt_addr_le_str(info.addr)); - - return false; + return true; } -static void create_adv(struct bt_le_ext_adv **adv, int id, bool expired_return) +static void create_adv(struct bt_le_ext_adv **adv, int id) { int err; struct bt_le_adv_param params; - static struct bt_le_ext_adv_cb cb_adv[] = { - {.rpa_expired = rpa_expired_cb_returns_true}, - {.rpa_expired = rpa_expired_cb_returns_false} - }; + static struct bt_le_ext_adv_cb cb_adv; + cb_adv.rpa_expired = rpa_expired_cb; memset(¶ms, 0, sizeof(struct bt_le_adv_param)); params.options |= BT_LE_ADV_OPT_EXT_ADV; @@ -81,7 +87,7 @@ static void create_adv(struct bt_le_ext_adv **adv, int id, bool expired_return) params.interval_min = BT_GAP_ADV_FAST_INT_MIN_1; params.interval_max = BT_GAP_ADV_FAST_INT_MAX_1; - err = bt_le_ext_adv_create(¶ms, expired_return ? &cb_adv[0] : &cb_adv[1], adv); + err = bt_le_ext_adv_create(¶ms, &cb_adv, adv); if (err) { FAIL("Failed to create advertiser (%d)\n", err); } @@ -130,32 +136,14 @@ void start_rpa_advertising(void) } for (int i = 0; i < CONFIG_BT_EXT_ADV_MAX_ADV_SET; i++) { - /* Create first 2 advertising sets with one id and for both sets,rpa_expied_cb - * returns true. - * Create remaining 2 sets with different id and last adv set's rpa_expired cb - * returns false. - * - * So for first two adv sets with same id new rpa's will be generated every - * rotation and for last two adv sets with same id, rpa will continue with - * only one rpa through out the rotations since one of the adv set returned - * false. + /* Create first 2 advertising sets with one id and last 2 advertising sets with + * different id. */ - switch (i) { - case ADV_SET_INDEX_1: - case ADV_SET_INDEX_2: - create_adv(&adv_set[i], ID_1, true); - break; - case ADV_SET_INDEX_3: - create_adv(&adv_set[i], ID_2, true); - break; - case ADV_SET_INDEX_4: - create_adv(&adv_set[i], ID_2, false); - break; - default: - printk("Shouldn't be here\n"); - break; + if (i < 2) { + create_adv(&adv_set[i], ID_1); + } else { + create_adv(&adv_set[i], ID_2); } - /* Set extended advertising data */ err = bt_le_ext_adv_set_data(adv_set[i], &ad_id[i], 1, NULL, 0); if (err) { diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/src/tester_rpa_expired.c b/tests/bsim/bluetooth/host/privacy/peripheral/src/tester_rpa_expired.c index aa03a25436a..85153ac8edd 100644 --- a/tests/bsim/bluetooth/host/privacy/peripheral/src/tester_rpa_expired.c +++ b/tests/bsim/bluetooth/host/privacy/peripheral/src/tester_rpa_expired.c @@ -55,24 +55,40 @@ static void test_address(bt_addr_le_t *addr) return; } - adv_set_data[adv_index].rpa_rotations++; - printk("Ad set %d Old ", adv_index); print_address(&adv_set_data[adv_index].old_addr); printk("Ad set %d New ", adv_index); print_address(addr); - /* Compare old and new address */ - if (adv_index < 2) { - if (bt_addr_le_eq(addr, &adv_set_data[adv_index].old_addr)) { - FAIL("New RPA should have been generated\n"); + /* For the first 2 rpa rotations, either of the first 2 adv sets returns false. + * Hence first 2 adv sets continue with old rpa in first 2 rpa rotations. + * For the next 2 rpa rotations, either of the last 2 adv sets returns false. + * Hence last 2 adv sets continue with old rpa in next 2 rpa rotations. + */ + if ((adv_set_data[adv_index].rpa_rotations % CONFIG_BT_EXT_ADV_MAX_ADV_SET) < 2) { + + if (adv_index < 2) { + if (!bt_addr_le_eq(addr, &adv_set_data[adv_index].old_addr)) { + FAIL("Adv sets should continue with old rpa\n"); + } + } else { + if (bt_addr_le_eq(addr, &adv_set_data[adv_index].old_addr)) { + FAIL("New RPA should have been generated\n"); + } } } else { - if (!bt_addr_le_eq(addr, &adv_set_data[adv_index].old_addr)) { - FAIL("Adv sets should continue with old rpa\n"); + if (adv_index < 2) { + if (bt_addr_le_eq(addr, &adv_set_data[adv_index].old_addr)) { + FAIL("New RPA should have been generated\n"); + } + } else { + if (!bt_addr_le_eq(addr, &adv_set_data[adv_index].old_addr)) { + FAIL("Adv sets should continue with old rpa\n"); + } } } + adv_set_data[adv_index].rpa_rotations++; if (adv_set_data[adv_index].rpa_rotations > EXPECTED_NUM_ROTATIONS) { PASS("PASS\n"); } From 31125f717732d486bac98ecec11dac7e9c64f655 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 18 Mar 2024 08:04:34 -0300 Subject: [PATCH 1056/2402] boards: esp32xx: remove minimal libc default config Let picolibc be the default for the second core as it is not mandantory to use minimal libc. Signed-off-by: Sylvio Alves --- .../esp32_devkitc_wroom_esp32_appcpu_defconfig | 1 - .../esp32_devkitc_wrover_esp32_appcpu_defconfig | 1 - .../esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig | 1 - .../esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig | 1 - .../esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig | 1 - boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig | 1 - .../heltec_wifi_lora32_v2_esp32_appcpu_defconfig | 1 - .../heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig | 1 - .../kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig | 1 - .../esp32s3_luatos_core_esp32s3_appcpu_defconfig | 1 - .../esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig | 1 - .../m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig | 1 - .../m5stack_atoms3_lite_esp32s3_appcpu_defconfig | 1 - .../m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig | 1 - .../m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig | 1 - .../m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig | 1 - .../olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig | 1 - boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu_defconfig | 1 - boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu_defconfig | 1 - 19 files changed, 19 deletions(-) diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu_defconfig b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu_defconfig index 6caadbd90ce..cc70c277960 100644 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu_defconfig +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y CONFIG_CONSOLE=n CONFIG_SERIAL=n CONFIG_UART_CONSOLE=n diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu_defconfig b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu_defconfig +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu_defconfig b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu_defconfig +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_defconfig +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu_defconfig b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu_defconfig +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig index 6caadbd90ce..cc70c277960 100644 --- a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y CONFIG_CONSOLE=n CONFIG_SERIAL=n CONFIG_UART_CONSOLE=n diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu_defconfig b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu_defconfig +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu_defconfig b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu_defconfig +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y From 6147589fbff4b4389fd98ab9a60ee60520bf4b51 Mon Sep 17 00:00:00 2001 From: Thomas PUJOLLE Date: Tue, 5 Mar 2024 17:12:18 +0100 Subject: [PATCH 1057/2402] Boards: Shell stack size for Silab's efm32xg24 Set to 4096 to prevent stack overflow while running BT Shell Signed-off-by: Thomas PUJOLLE --- boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig b/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig index a63ff0ee6a7..dbd2884e28a 100644 --- a/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig +++ b/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig @@ -37,6 +37,13 @@ choice BT_HCI_BUS_TYPE default BT_SILABS_HCI endchoice +if SHELL + +config SHELL_STACK_SIZE + default 4096 + +endif # SHELL + endif # BT endif # BOARD_EFR32XG24_DK2601B From 31e912426108fea7a42f1f1eb72010bf8368e697 Mon Sep 17 00:00:00 2001 From: Arunmani Alagarsamy Date: Wed, 13 Mar 2024 11:21:41 +0530 Subject: [PATCH 1058/2402] boards: st: b_u585i_iot02a: Add sensor child node in i2c2 Add sensor child node for iis2mdctr, ism330dhcx, lps22hh, veml6030. Signed-off-by: Arunmani Alagarsamy --- .../b_u585i_iot02a/b_u585i_iot02a-common.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi index ccbb4cea402..57fe9bded74 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi @@ -165,6 +165,30 @@ stm32_lp_tick_source: &lptim1 { status = "okay"; clock-frequency = ; + veml6030@10 { + compatible ="vishay,veml7700"; + reg = <0x10>; + status = "okay"; + }; + + iis2mdc@1e { + compatible = "st,iis2mdc"; + reg = <0x1e>; + drdy-gpios = <&gpiod 10 GPIO_ACTIVE_HIGH>; + }; + + ism330dhcx@6b { + compatible = "st,ism330dhcx"; + reg = <0x6b>; + drdy-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; + }; + + lps22hh@5d { + compatible = "st,lps22hh"; + reg = <0x5d>; + drdy-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + }; + hts221@5f { compatible = "st,hts221"; reg = <0x5f>; From e1b132771e8b69d83250b3a1598b8d65bf8ea41a Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Tue, 12 Mar 2024 12:28:45 +0100 Subject: [PATCH 1059/2402] drivers: ethernet: nxp_s32_gmac: Imply MDIO The ethernet driver will most likely require the MDIO device to be enabled. Signed-off-by: Pieter De Gendt --- drivers/ethernet/Kconfig.nxp_s32_gmac | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ethernet/Kconfig.nxp_s32_gmac b/drivers/ethernet/Kconfig.nxp_s32_gmac index a1d0f3f7c3d..40dad1b500b 100644 --- a/drivers/ethernet/Kconfig.nxp_s32_gmac +++ b/drivers/ethernet/Kconfig.nxp_s32_gmac @@ -7,6 +7,7 @@ menuconfig ETH_NXP_S32_GMAC depends on DT_HAS_NXP_S32_GMAC_ENABLED select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT select PINCTRL + imply MDIO help Enable GMAC/EMAC Ethernet driver for NXP S32 SoCs. From dcafbc2a8e3a17154620f4dc074df9740222cddf Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 11 Mar 2024 14:50:08 +0100 Subject: [PATCH 1060/2402] include: net: net_if: Re-use instance macro for NET_DEVICE_INIT Re-use a single macro for both NET_DEVICE_INIT and NET_DEVICE_INIT_INSTANCE. Signed-off-by: Pieter De Gendt --- include/zephyr/net/net_if.h | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/include/zephyr/net/net_if.h b/include/zephyr/net/net_if.h index 91f1aa63285..9d17be36d2a 100644 --- a/include/zephyr/net/net_if.h +++ b/include/zephyr/net/net_if.h @@ -2990,14 +2990,21 @@ struct net_if_api { /* Network device initialization macros */ -#define Z_NET_DEVICE_INIT(node_id, dev_id, name, init_fn, pm, data, \ - config, prio, api, l2, l2_ctx_type, mtu) \ +#define Z_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, instance, \ + init_fn, pm, data, config, prio, \ + api, l2, l2_ctx_type, mtu) \ Z_DEVICE_STATE_DEFINE(dev_id); \ Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, pm, data, \ config, POST_KERNEL, prio, api, \ &Z_DEVICE_STATE_NAME(dev_id)); \ - NET_L2_DATA_INIT(dev_id, 0, l2_ctx_type); \ - NET_IF_INIT(dev_id, 0, l2, mtu, NET_IF_MAX_CONFIGS) + NET_L2_DATA_INIT(dev_id, instance, l2_ctx_type); \ + NET_IF_INIT(dev_id, instance, l2, mtu, NET_IF_MAX_CONFIGS) + +#define Z_NET_DEVICE_INIT(node_id, dev_id, name, init_fn, pm, data, \ + config, prio, api, l2, l2_ctx_type, mtu) \ + Z_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, 0, init_fn, \ + pm, data, config, prio, api, l2, \ + l2_ctx_type, mtu) /** * @brief Create a network interface and bind it to network device. @@ -3058,16 +3065,6 @@ struct net_if_api { #define NET_DEVICE_DT_INST_DEFINE(inst, ...) \ NET_DEVICE_DT_DEFINE(DT_DRV_INST(inst), __VA_ARGS__) -#define Z_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, instance, \ - init_fn, pm, data, config, prio, \ - api, l2, l2_ctx_type, mtu) \ - Z_DEVICE_STATE_DEFINE(dev_id); \ - Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, pm, data, \ - config, POST_KERNEL, prio, api, \ - &Z_DEVICE_STATE_NAME(dev_id)); \ - NET_L2_DATA_INIT(dev_id, instance, l2_ctx_type); \ - NET_IF_INIT(dev_id, instance, l2, mtu, NET_IF_MAX_CONFIGS) - /** * @brief Create multiple network interfaces and bind them to network device. * If your network device needs more than one instance of a network interface, From 253139455c2dfa069de809017414531debcf94d6 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 11 Mar 2024 14:58:58 +0100 Subject: [PATCH 1061/2402] include: net: ethernet: Add ETH_NET_DEVICE_INIT_INSTANCE Add a macro variant for ethernet devices with instances. Signed-off-by: Pieter De Gendt --- include/zephyr/net/ethernet.h | 56 ++++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/include/zephyr/net/ethernet.h b/include/zephyr/net/ethernet.h index b1f4ebe7498..6891a96efcd 100644 --- a/include/zephyr/net/ethernet.h +++ b/include/zephyr/net/ethernet.h @@ -933,23 +933,35 @@ static inline bool net_eth_get_vlan_status(struct net_if *iface) #endif #if defined(CONFIG_NET_VLAN) -#define Z_ETH_NET_DEVICE_INIT(node_id, dev_id, name, init_fn, pm, data, \ - config, prio, api, mtu) \ + +#define Z_ETH_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, instance, \ + init_fn, pm, data, config, prio, \ + api, mtu) \ Z_DEVICE_STATE_DEFINE(dev_id); \ Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, pm, data, \ config, POST_KERNEL, prio, api, \ &Z_DEVICE_STATE_NAME(dev_id)); \ - NET_L2_DATA_INIT(dev_id, 0, NET_L2_GET_CTX_TYPE(ETHERNET_L2)); \ - NET_IF_INIT(dev_id, 0, ETHERNET_L2, mtu, NET_VLAN_MAX_COUNT) + NET_L2_DATA_INIT(dev_id, instance, \ + NET_L2_GET_CTX_TYPE(ETHERNET_L2)); \ + NET_IF_INIT(dev_id, instance, ETHERNET_L2, mtu, \ + NET_VLAN_MAX_COUNT) #else /* CONFIG_NET_VLAN */ +#define Z_ETH_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, instance, \ + init_fn, pm, data, config, prio, \ + api, mtu) \ + Z_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, instance, \ + init_fn, pm, data, config, prio, \ + api, ETHERNET_L2, \ + NET_L2_GET_CTX_TYPE(ETHERNET_L2), mtu) +#endif /* CONFIG_NET_VLAN */ + #define Z_ETH_NET_DEVICE_INIT(node_id, dev_id, name, init_fn, pm, data, \ config, prio, api, mtu) \ - Z_NET_DEVICE_INIT(node_id, dev_id, name, init_fn, pm, data, \ - config, prio, api, ETHERNET_L2, \ - NET_L2_GET_CTX_TYPE(ETHERNET_L2), mtu) -#endif /* CONFIG_NET_VLAN */ + Z_ETH_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, 0, \ + init_fn, pm, data, config, prio, \ + api, mtu) /** * @brief Create an Ethernet network interface and bind it to network device. @@ -973,6 +985,34 @@ static inline bool net_eth_get_vlan_status(struct net_if *iface) Z_ETH_NET_DEVICE_INIT(DT_INVALID_NODE, dev_id, name, init_fn, \ pm, data, config, prio, api, mtu) +/** + * @brief Create multiple Ethernet network interfaces and bind them to network + * devices. + * If your network device needs more than one instance of a network interface, + * use this macro below and provide a different instance suffix each time + * (0, 1, 2, ... or a, b, c ... whatever works for you) + * + * @param dev_id Network device id. + * @param name The name this instance of the driver exposes to + * the system. + * @param instance Instance identifier. + * @param init_fn Address to the init function of the driver. + * @param pm Reference to struct pm_device associated with the device. + * (optional). + * @param data Pointer to the device's private data. + * @param config The address to the structure containing the + * configuration information for this instance of the driver. + * @param prio The initialization level at which configuration occurs. + * @param api Provides an initial pointer to the API function struct + * used by the driver. Can be NULL. + * @param mtu Maximum transfer unit in bytes for this network interface. + */ +#define ETH_NET_DEVICE_INIT_INSTANCE(dev_id, name, instance, init_fn, \ + pm, data, config, prio, api, mtu) \ + Z_ETH_NET_DEVICE_INIT_INSTANCE(DT_INVALID_NODE, dev_id, name, \ + instance, init_fn, pm, data, \ + config, prio, api, mtu) + /** * @brief Like ETH_NET_DEVICE_INIT but taking metadata from a devicetree. * Create an Ethernet network interface and bind it to network device. From 78457c0499961b091583b09a868c0c1a64421a6b Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 11 Mar 2024 15:00:05 +0100 Subject: [PATCH 1062/2402] drivers: ethernet: adin2111: Use ethernet init macro Use the ethernet specific init macro. Signed-off-by: Pieter De Gendt --- drivers/ethernet/eth_adin2111.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index 74c533bf867..eaa1fb1ea99 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -1328,11 +1328,10 @@ static const struct ethernet_api adin2111_port_api = { .port_idx = port_n, \ .phy_addr = phy_n, \ }; \ - NET_DEVICE_INIT_INSTANCE(name##_port_##port_n, "port_" ADIN2111_XSTR(port_n), port_n, \ - NULL, NULL, &name##_port_data_##port_n, \ - &name##_port_config_##port_n, CONFIG_ETH_INIT_PRIORITY, \ - &adin2111_port_api, ETHERNET_L2, \ - NET_L2_GET_CTX_TYPE(ETHERNET_L2), NET_ETH_MTU); + ETH_NET_DEVICE_INIT_INSTANCE(name##_port_##port_n, "port_" ADIN2111_XSTR(port_n), \ + port_n, NULL, NULL, &name##_port_data_##port_n, \ + &name##_port_config_##port_n, CONFIG_ETH_INIT_PRIORITY, \ + &adin2111_port_api, NET_ETH_MTU); #define ADIN2111_SPI_OPERATION ((uint16_t)(SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8))) #define ADIN2111_MAC_INITIALIZE(inst, dev_id, ifaces, name) \ From e99b5228a1f9dd162dd3d6be1eda42b26d762da3 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 11 Mar 2024 11:18:18 +0100 Subject: [PATCH 1063/2402] drivers: ethernet: Introduce ETH_DRIVER_RAW_MODE option Add a Kconfig symbol to allow building ethernet device driver without an L2 layer. Signed-off-by: Pieter De Gendt --- drivers/ethernet/Kconfig | 15 ++++++++++++--- drivers/ethernet/phy/Kconfig | 9 ++++++--- drivers/net/Kconfig | 1 - include/zephyr/net/ethernet.h | 12 ++++++++++++ subsys/net/ip/Kconfig | 12 ++++++------ 5 files changed, 36 insertions(+), 13 deletions(-) diff --git a/drivers/ethernet/Kconfig b/drivers/ethernet/Kconfig index dcc1ac1934b..4d7facdfff0 100644 --- a/drivers/ethernet/Kconfig +++ b/drivers/ethernet/Kconfig @@ -5,12 +5,21 @@ menuconfig ETH_DRIVER bool "Ethernet drivers" - default y - depends on NET_L2_ETHERNET + depends on NETWORKING depends on !NET_TEST + default y if NET_L2_ETHERNET if ETH_DRIVER +config ETH_DRIVER_RAW_MODE + bool "Ethernet driver without the MAC stack" + select NET_RAW_MODE + depends on !NET_L2_ETHERNET + help + This option enables using the drivers in a so-called "raw" mode, + i.e. without a MAC stack (the net L2 layer for ethernet will not + be built). + module = ETHERNET module-dep = LOG module-str = Log level for Ethernet driver @@ -74,7 +83,7 @@ endif # "Ethernet Drivers" config ETH_INIT_PRIORITY int "Ethernet driver init priority" default 80 - depends on NET_L2_ETHERNET + depends on NET_L2_ETHERNET || ETH_DRIVER help Ethernet device driver initialization priority. Do not mess with it unless you know what you are doing. diff --git a/drivers/ethernet/phy/Kconfig b/drivers/ethernet/phy/Kconfig index e14a27a398d..26446974995 100644 --- a/drivers/ethernet/phy/Kconfig +++ b/drivers/ethernet/phy/Kconfig @@ -3,8 +3,11 @@ # Copyright (c) 2021 IP-Logix Inc. # SPDX-License-Identifier: Apache-2.0 -menu "Ethernet PHY Drivers" - depends on NET_L2_ETHERNET +menuconfig ETH_PHY_DRIVER + bool "Ethernet PHY drivers" + default y if NET_L2_ETHERNET || ETH_DRIVER + +if ETH_PHY_DRIVER module = PHY module-dep = LOG @@ -63,4 +66,4 @@ config PHY_MONITOR_PERIOD periodically executed to detect and report any changes in the PHY link status to the operating system. -endmenu # "Ethernet PHY Drivers" +endif # "Ethernet PHY Drivers" diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index c83f0f42a08..e0167e80ccb 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -153,7 +153,6 @@ config SLIP_STATISTICS config SLIP_TAP bool "Use TAP interface to host" default y - select NET_L2_ETHERNET help In TAP the Ethernet frames are transferred over SLIP. diff --git a/include/zephyr/net/ethernet.h b/include/zephyr/net/ethernet.h index 6891a96efcd..0fb7c43c8ef 100644 --- a/include/zephyr/net/ethernet.h +++ b/include/zephyr/net/ethernet.h @@ -932,6 +932,7 @@ static inline bool net_eth_get_vlan_status(struct net_if *iface) } #endif +#if !defined(CONFIG_ETH_DRIVER_RAW_MODE) #if defined(CONFIG_NET_VLAN) #define Z_ETH_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, instance, \ @@ -957,6 +958,17 @@ static inline bool net_eth_get_vlan_status(struct net_if *iface) NET_L2_GET_CTX_TYPE(ETHERNET_L2), mtu) #endif /* CONFIG_NET_VLAN */ +#else /* CONFIG_ETH_DRIVER_RAW_MODE */ + +#define Z_ETH_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, instance, \ + init_fn, pm, data, config, prio, \ + api, mtu) \ + Z_DEVICE_STATE_DEFINE(dev_id); \ + Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, pm, data, \ + config, POST_KERNEL, prio, api, \ + &Z_DEVICE_STATE_NAME(dev_id)); +#endif /* CONFIG_ETH_DRIVER_RAW_MODE */ + #define Z_ETH_NET_DEVICE_INIT(node_id, dev_id, name, init_fn, pm, data, \ config, prio, api, mtu) \ Z_ETH_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, 0, \ diff --git a/subsys/net/ip/Kconfig b/subsys/net/ip/Kconfig index a673c6524b0..4de15ada6d9 100644 --- a/subsys/net/ip/Kconfig +++ b/subsys/net/ip/Kconfig @@ -583,12 +583,6 @@ config NET_CONTEXT_RECV_PKTINFO This way user can get extra information about the received data in the socket. -config NET_TEST - bool "Network Testing" - help - Used for self-contained networking tests that do not require a - network device. - config NET_SLIP_TAP bool "TAP SLIP driver" depends on NET_QEMU_SLIP @@ -606,6 +600,12 @@ config NET_SLIP_TAP endif # NET_RAW_MODE +config NET_TEST + bool "Network Testing" + help + Used for self-contained networking tests that do not require a + network device. + config NET_PKT_RX_COUNT int "How many packet receives can be pending at the same time" default 14 if NET_L2_ETHERNET From 2ee4716091fbcc7364a64a3eb7cf5e4d3d978b63 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 11 Mar 2024 15:14:05 +0100 Subject: [PATCH 1064/2402] drivers: ethernet: Build ethernet drivers with ETH_DRIVER_RAW_MODE Allow building ethernet drivers without NET_L2_ETHERNET config symbol. Signed-off-by: Pieter De Gendt --- drivers/CMakeLists.txt | 2 +- drivers/ethernet/CMakeLists.txt | 5 ++++ drivers/ethernet/eth_raw.c | 48 +++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+), 1 deletion(-) create mode 100644 drivers/ethernet/eth_raw.c diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt index f0236ef653a..e1dbab7e1a2 100644 --- a/drivers/CMakeLists.txt +++ b/drivers/CMakeLists.txt @@ -35,6 +35,7 @@ add_subdirectory_ifdef(CONFIG_EDAC edac) add_subdirectory_ifdef(CONFIG_EEPROM eeprom) add_subdirectory_ifdef(CONFIG_ENTROPY_GENERATOR entropy) add_subdirectory_ifdef(CONFIG_ESPI espi) +add_subdirectory_ifdef(CONFIG_ETH_DRIVER ethernet) add_subdirectory_ifdef(CONFIG_FLASH flash) add_subdirectory_ifdef(CONFIG_FPGA fpga) add_subdirectory_ifdef(CONFIG_FUEL_GAUGE fuel_gauge) @@ -61,7 +62,6 @@ add_subdirectory_ifdef(CONFIG_MIPI_DSI mipi_dsi) add_subdirectory_ifdef(CONFIG_MM_DRV mm) add_subdirectory_ifdef(CONFIG_MODEM modem) add_subdirectory_ifdef(CONFIG_NET_DRIVERS net) -add_subdirectory_ifdef(CONFIG_NET_L2_ETHERNET ethernet) add_subdirectory_ifdef(CONFIG_PECI peci) add_subdirectory_ifdef(CONFIG_PINCTRL pinctrl) add_subdirectory_ifdef(CONFIG_PM_CPU_OPS pm_cpu_ops) diff --git a/drivers/ethernet/CMakeLists.txt b/drivers/ethernet/CMakeLists.txt index def0c5bf186..fcc43cf77f7 100644 --- a/drivers/ethernet/CMakeLists.txt +++ b/drivers/ethernet/CMakeLists.txt @@ -2,6 +2,11 @@ zephyr_library() zephyr_library_property(ALLOW_EMPTY TRUE) +zephyr_library_include_directories(${ZEPHYR_BASE}/subsys/net/l2) + +zephyr_library_sources_ifdef(CONFIG_ETH_DRIVER_RAW_MODE + eth_raw.c + ) zephyr_library_sources_ifdef(CONFIG_ETH_GECKO eth_gecko.c diff --git a/drivers/ethernet/eth_raw.c b/drivers/ethernet/eth_raw.c new file mode 100644 index 00000000000..69ab3b528f7 --- /dev/null +++ b/drivers/ethernet/eth_raw.c @@ -0,0 +1,48 @@ +/** + * @file + * @brief Ethernet Driver raw mode + * + * This file contains a collection of functions called from the ethernet drivers + * to the missing upper layer. + */ + +/* + * Copyright 2024 Basalte bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +__weak void ethernet_init(struct net_if *iface) +{ + ARG_UNUSED(iface); +} + +__weak void net_eth_carrier_on(struct net_if *iface) +{ + ARG_UNUSED(iface); +} + +__weak void net_eth_carrier_off(struct net_if *iface) +{ + ARG_UNUSED(iface); +} + +__weak int net_recv_data(struct net_if *iface, struct net_pkt *pkt) +{ + ARG_UNUSED(iface); + ARG_UNUSED(pkt); + + return -ENOTSUP; +} + +__weak void net_if_carrier_on(struct net_if *iface) +{ + ARG_UNUSED(iface); +} + +__weak void net_if_carrier_off(struct net_if *iface) +{ + ARG_UNUSED(iface); +} From 5f3a69fada1a52700d9bc00d93a2b00d81c3ab57 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 11 Mar 2024 15:31:03 +0100 Subject: [PATCH 1065/2402] tests: drivers: build_all: ethernet: Build without L2 Limit the number of files built when building ethernet device drivers. Use the ETH_DRIVER_RAW_MODE to provide weak funtions for upper layer handling. Signed-off-by: Pieter De Gendt --- tests/drivers/build_all/ethernet/prj.conf | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/tests/drivers/build_all/ethernet/prj.conf b/tests/drivers/build_all/ethernet/prj.conf index 400feb5c6fa..208ed81da3c 100644 --- a/tests/drivers/build_all/ethernet/prj.conf +++ b/tests/drivers/build_all/ethernet/prj.conf @@ -1,10 +1,21 @@ CONFIG_TEST=y CONFIG_NETWORKING=y -CONFIG_NET_L2_ETHERNET=y +CONFIG_ETH_DRIVER=y +CONFIG_ETH_DRIVER_RAW_MODE=y CONFIG_ENTROPY_GENERATOR=y CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_TEST_USERSPACE=y +# Sufficient buffer sizes +CONFIG_NET_PKT_RX_COUNT=14 +CONFIG_NET_PKT_TX_COUNT=14 +CONFIG_NET_BUF_RX_COUNT=36 +CONFIG_NET_BUF_TX_COUNT=36 +CONFIG_NET_BUF_DATA_POOL_SIZE=4096 + +# Disable L2 +CONFIG_NET_L2_ETHERNET=n + CONFIG_GPIO=y CONFIG_SPI_INIT_PRIORITY=50 From dba205a2ce04b6c3525ccb7e180e2f14afa768bc Mon Sep 17 00:00:00 2001 From: Magdalena Kasenberg Date: Tue, 12 Mar 2024 14:09:06 +0100 Subject: [PATCH 1066/2402] bluetooth: audio: broadcast source: Add missing check condition There is no need to validate stream_param->data if it is NULL. Fixes failing PTS BAP/BSRC test cases. Signed-off-by: Magdalena Kasenberg --- subsys/bluetooth/audio/bap_broadcast_source.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/subsys/bluetooth/audio/bap_broadcast_source.c b/subsys/bluetooth/audio/bap_broadcast_source.c index 45b90e56d32..0934fc0f8d0 100644 --- a/subsys/bluetooth/audio/bap_broadcast_source.c +++ b/subsys/bluetooth/audio/bap_broadcast_source.c @@ -594,7 +594,8 @@ static bool valid_broadcast_source_param(const struct bt_bap_broadcast_source_pa return false; } - CHECKIF(subgroup_param->codec_cfg->id == BT_HCI_CODING_FORMAT_LC3 && + CHECKIF(stream_param->data != NULL && + subgroup_param->codec_cfg->id == BT_HCI_CODING_FORMAT_LC3 && !bt_audio_valid_ltv(stream_param->data, stream_param->data_len)) { LOG_DBG("subgroup_params[%zu].stream_params[%zu]->data not valid " "LTV", From d737e5d8e3606b1e1879e03535cf7dcf34b83317 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 4 Mar 2024 11:10:43 +0100 Subject: [PATCH 1067/2402] manifest: optional: Update nanopb Upstream nanopb added zephyr module support. Update the revision to the latest head. Signed-off-by: Pieter De Gendt --- submanifests/optional.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/submanifests/optional.yaml b/submanifests/optional.yaml index 39faa5f3887..f0ae16d5d0d 100644 --- a/submanifests/optional.yaml +++ b/submanifests/optional.yaml @@ -22,7 +22,7 @@ manifest: groups: - optional - name: nanopb - revision: 65cbefb4695bc7af1cb733ced99618afb3586b20 + revision: 671672b4d7994a9b07a307ae654885c7202ae886 path: modules/lib/nanopb remote: upstream groups: From 280fd59547cd2c069bf4f645b2bffc71235c7fa2 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 10:22:56 +0100 Subject: [PATCH 1068/2402] boards lpcxpresso55s36: Provisionally disable in twister This board fails to build for a multitude of samples & tests which is blocking CI. Let's provisionally disable it until the matter is properly resolved. The issue was introduced with the NXP HAL update to 2.15: e4e463af812e61bb5bfb4b1087d48e1dbcd9d8d5 See https://github.com/zephyrproject-rtos/zephyr/issues/69961 for more information. Once this issue is fixed, this change should be reverted. Signed-off-by: Alberto Escolar Piedras --- boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml index 5a28b2149c5..58dbfb9df65 100644 --- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml @@ -20,3 +20,8 @@ supported: - pwm - dac vendor: nxp +env: # Provisional hack to prevent tests being run in this board, as it fails in many test & samples + - LPCXPRESSO55S36_TWISTER_ENABLE + # Twister won't run tests in this board unless LPCXPRESSO55S36_TWISTER_ENABLE is set in the + # environment, which it normally won't. + # Once https://github.com/zephyrproject-rtos/zephyr/issues/69961 is fixed this should be removed From ff35a247f1b1fc0e5b54fdc038d587d6eb25c542 Mon Sep 17 00:00:00 2001 From: Mykola Kvach Date: Tue, 9 Jan 2024 19:14:12 +0200 Subject: [PATCH 1069/2402] drivers: pinctrl: pfc_rcar: add dummy IPSR flag to pinctrl driver Add a dummy IPSR flag to the RCar PFC driver. It is necessary to ensure that the driver sets the 'peripheral' bit (the driver resets this bit during the first call of 'pfc_rcar_set_gpsr') for a pin that doesn't have a pin function defined in IPSR, but always acts as a 'peripheral', for example, the MMC pins on the Spider board. Signed-off-by: Mykola Kvach --- drivers/pinctrl/renesas/rcar/pfc_rcar.c | 5 ++++- .../zephyr/drivers/pinctrl/pinctrl_rcar_common.h | 10 +++++++++- .../pinctrl/renesas/pinctrl-r8a779f0.h | 15 +++++++++++++++ .../pinctrl/renesas/pinctrl-rcar-common.h | 12 ++++++++++++ 4 files changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/rcar/pfc_rcar.c b/drivers/pinctrl/renesas/rcar/pfc_rcar.c index ad10b03fda0..881219e41ec 100644 --- a/drivers/pinctrl/renesas/rcar/pfc_rcar.c +++ b/drivers/pinctrl/renesas/rcar/pfc_rcar.c @@ -338,7 +338,10 @@ int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) /* Select function for pin */ if ((pin->flags & RCAR_PIN_FLAGS_FUNC_SET) != 0U) { - pfc_rcar_set_ipsr(pfc_base, &pin->func); + + if ((pin->flags & RCAR_PIN_FLAGS_FUNC_DUMMY) == 0U) { + pfc_rcar_set_ipsr(pfc_base, &pin->func); + } if (RCAR_IS_GP_PIN(pin->pin)) { pfc_rcar_set_gpsr(pfc_base, pin->pin, true); diff --git a/include/zephyr/drivers/pinctrl/pinctrl_rcar_common.h b/include/zephyr/drivers/pinctrl/pinctrl_rcar_common.h index c3563e014ba..aa4e8ba6b89 100644 --- a/include/zephyr/drivers/pinctrl/pinctrl_rcar_common.h +++ b/include/zephyr/drivers/pinctrl/pinctrl_rcar_common.h @@ -27,6 +27,8 @@ struct rcar_pin_func { #define RCAR_PIN_FLAGS_PUD BIT(2) /** Alternate function for the pin is requested */ #define RCAR_PIN_FLAGS_FUNC_SET BIT(3) +/** Ignore IPSR settings for alternate function pin */ +#define RCAR_PIN_FLAGS_FUNC_DUMMY BIT(4) #define RCAR_PIN_PULL_UP (RCAR_PIN_FLAGS_PULL_SET | RCAR_PIN_FLAGS_PUEN | RCAR_PIN_FLAGS_PUD) #define RCAR_PIN_PULL_DOWN (RCAR_PIN_FLAGS_PULL_SET | RCAR_PIN_FLAGS_PUEN) @@ -52,11 +54,17 @@ typedef struct pinctrl_soc_pin { ((RCAR_IPSR(node_id) & 0xFU)) \ } +#define RCAR_PIN_IS_FUNC_DUMMY(node_id) \ + ((((RCAR_IPSR(node_id) >> 10U) & 0x1FU) == 0x1F) && \ + (((RCAR_IPSR(node_id) >> 4U) & 0x1FU) == 0x1F) && \ + ((RCAR_IPSR(node_id) & 0xFU) == 0xF)) + #define RCAR_PIN_FLAGS(node_id) \ DT_PROP(node_id, bias_pull_up) * RCAR_PIN_PULL_UP | \ DT_PROP(node_id, bias_pull_down) * RCAR_PIN_PULL_DOWN | \ DT_PROP(node_id, bias_disable) * RCAR_PIN_PULL_DISABLE | \ - RCAR_HAS_IPSR(node_id) * RCAR_PIN_FLAGS_FUNC_SET + RCAR_HAS_IPSR(node_id) * RCAR_PIN_FLAGS_FUNC_SET | \ + RCAR_PIN_IS_FUNC_DUMMY(node_id) * RCAR_PIN_FLAGS_FUNC_DUMMY #define RCAR_DT_PIN(node_id) \ { \ diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h index 50e8a358007..7fbceb40673 100644 --- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h @@ -275,6 +275,21 @@ #define FUNC_TCLK1 IP0SR1(0, 1) #define FUNC_HSCK2 IP0SR1(0, 2) #define FUNC_GP1_01 IP0SR1(4, 0) + +#define FUNC_MMC_SD_CLK IPSR_DUMMY +#define FUNC_MMC_SD_D0 IPSR_DUMMY +#define FUNC_MMC_SD_D1 IPSR_DUMMY +#define FUNC_MMC_SD_D2 IPSR_DUMMY +#define FUNC_MMC_SD_D3 IPSR_DUMMY +#define FUNC_MMC_D4 IPSR_DUMMY +#define FUNC_MMC_D5 IPSR_DUMMY +#define FUNC_MMC_D6 IPSR_DUMMY +#define FUNC_MMC_D7 IPSR_DUMMY +#define FUNC_MMC_DS IPSR_DUMMY +#define FUNC_MMC_SD_CMD IPSR_DUMMY +#define FUNC_SD_CD IPSR_DUMMY +#define FUNC_SD_WP IPSR_DUMMY + #define FUNC_TCLK4 IP0SR1(4, 1) #define FUNC_HRX2 IP0SR1(4, 2) #define FUNC_GP1_02 IP0SR1(8, 0) diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h index 30a2afe1db1..44669cc4644 100644 --- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h @@ -82,6 +82,18 @@ #define IP2SR7(shift, func) IPnSR(2, 7, shift, func) #define IP3SR7(shift, func) IPnSR(3, 7, shift, func) +/** + * @brief Macro to define a dummy IPSR flag for a pin + * + * This macro is used to define a dummy IPSR flag for a pin in the R-Car PFC + * driver. It is intended for pins that do not have a specific function + * defined in IPSR but always act as a peripheral. The dummy IPSR flag ensures + * that the driver sets the 'peripheral' bit for such pins. + * + * @see RCAR_PIN_FLAGS_FUNC_DUMMY + */ +#define IPSR_DUMMY IPnSR(0x1f, 7, 0x1f, 0xf) + #define PIN_VOLTAGE_NONE 0 #define PIN_VOLTAGE_1P8V 1 #define PIN_VOLTAGE_3P3V 2 From 64ba1b221091c343f7cca79a7970981eb1ff3a35 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Mon, 11 Mar 2024 15:23:15 +0200 Subject: [PATCH 1070/2402] dts: nxp: imx93: add nodes for SAI3 and EDMA4 Add DTS nodes for 93's SAI3 and EDMA4. Signed-off-by: Laurentiu Mihalcea --- dts/arm64/nxp/nxp_mimx93_a55.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/dts/arm64/nxp/nxp_mimx93_a55.dtsi b/dts/arm64/nxp/nxp_mimx93_a55.dtsi index 4592209c902..3bf2071cc78 100644 --- a/dts/arm64/nxp/nxp_mimx93_a55.dtsi +++ b/dts/arm64/nxp/nxp_mimx93_a55.dtsi @@ -320,6 +320,32 @@ #address-cells = <1>; #size-cells = <0>; }; + + edma4: dma@42000000 { + compatible = "nxp,edma"; + reg = <0x42000000 (DT_SIZE_K(64) * 32)>; + valid-channels = <0>, <1>; + interrupt-parent = <&gic>; + interrupts = , + ; + #dma-cells = <2>; + hal-cfg-index = <1>; + status = "disabled"; + }; + + sai3: dai@42660000 { + compatible = "nxp,dai-sai"; + reg = <0x42660000 DT_SIZE_K(64)>; + mclk-is-output; + clocks = <&ccm IMX_CCM_SAI3_CLK 0x0 0x0>; + clock-names = "mclk1"; + interrupt-parent = <&gic>; + interrupts = ; + dai-index = <3>; + dmas = <&edma4 0 60>, <&edma4 1 61>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; &gpio1{ From 7b8664c3f910331fbeacfc26c809f8e3c456c90e Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 13:34:48 +0100 Subject: [PATCH 1071/2402] arch posix: Clarify some references to native_posix Some old references to native_posix are better refering to the native targets in general, or being clarified as only applying to the old native_posix like targets. Signed-off-by: Alberto Escolar Piedras --- arch/posix/CMakeLists.txt | 2 +- arch/posix/include/posix_cheats.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/posix/CMakeLists.txt b/arch/posix/CMakeLists.txt index 2ec433ad5cb..478e29cac1e 100644 --- a/arch/posix/CMakeLists.txt +++ b/arch/posix/CMakeLists.txt @@ -197,7 +197,7 @@ endif() # This is due to some tests using _Static_assert which is a 2011 feature, but # otherwise relying on compilers supporting it also when set to C99. # This was in general ok, but with some host compilers and C library versions -# it led to problems. So we override it to 2011 for native_posix. +# it led to problems. So we override it to 2011 for the native targets. set_property(GLOBAL PROPERTY CSTD c11) add_subdirectory(core) diff --git a/arch/posix/include/posix_cheats.h b/arch/posix/include/posix_cheats.h index 770dab9aac6..d8307df0ef8 100644 --- a/arch/posix/include/posix_cheats.h +++ b/arch/posix/include/posix_cheats.h @@ -16,7 +16,7 @@ * If you do see a link error telling you that zap_something is undefined, it is * likely that you forgot to select the corresponding Zephyr POSIX API. * - * This header is included automatically when targeting POSIX ARCH boards + * This header is included automatically when targeting some POSIX ARCH boards * (for ex. native_posix). * It will be included in _all_ Zephyr and application source files * (it is passed with the option "-include" to the compiler call) From 996377340a36a17fe95a7cd2e875ea55d5f34957 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 14:08:11 +0100 Subject: [PATCH 1072/2402] cmake clang/compiler_flags.cmake: Clarify comment for native targets Correct the comment for native targets. Signed-off-by: Alberto Escolar Piedras --- cmake/compiler/clang/compiler_flags.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake/compiler/clang/compiler_flags.cmake b/cmake/compiler/clang/compiler_flags.cmake index e0448d0720e..acc9b629171 100644 --- a/cmake/compiler/clang/compiler_flags.cmake +++ b/cmake/compiler/clang/compiler_flags.cmake @@ -10,8 +10,8 @@ set_compiler_property(PROPERTY security_fortify_run_time) # No printf-return-value optimizations in clang set_compiler_property(PROPERTY no_printf_return_value) -# No property flag, this is used by the native_posix, clang has problems -# compiling the native_posix with -fno-freestanding. +# No property flag, this is used by the POSIX arch based targets when building with the host libC, +# But clang has problems compiling these with -fno-freestanding. check_set_compiler_property(PROPERTY hosted) # clang flags for coverage generation From bd68ec956868b144e3a381814715b380bc8ea863 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 14:10:53 +0100 Subject: [PATCH 1073/2402] doc/develop/application: Replace native_posix w native_sim As we are replacing native_posix with native_sim, let's use native_sim instead of native_posix as example platform. Signed-off-by: Alberto Escolar Piedras --- doc/develop/application/index.rst | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/doc/develop/application/index.rst b/doc/develop/application/index.rst index 83d7dbb3fdd..9866a12ba4c 100644 --- a/doc/develop/application/index.rst +++ b/doc/develop/application/index.rst @@ -706,20 +706,20 @@ Given the following example project layout: ├── prj.conf ├── prj_mouse.conf ├── boards - │ ├── native_posix.overlay + │ ├── native_sim.overlay │ └── qemu_cortex_m3_mouse.overlay └── src └── main.c -* If this is built normally without ``FILE_SUFFIX`` being defined for ``native_posix`` then - ``prj.conf`` and ``boards/native_posix.overlay`` will be used. +* If this is built normally without ``FILE_SUFFIX`` being defined for ``native_sim`` then + ``prj.conf`` and ``boards/native_sim.overlay`` will be used. * If this is build normally without ``FILE_SUFFIX`` being defined for ``qemu_cortex_m3`` then ``prj.conf`` will be used, no application devicetree overlay will be used. -* If this is built with ``FILE_SUFFIX`` set to ``mouse`` for ``native_posix`` then - ``prj_mouse.conf`` and ``boards/native_posix.overlay`` will be used (there is no - ``native_posix_mouse.overlay`` file so it falls back to ``native_posix.overlay``). +* If this is built with ``FILE_SUFFIX`` set to ``mouse`` for ``native_sim`` then + ``prj_mouse.conf`` and ``boards/native_sim.overlay`` will be used (there is no + ``native_sim_mouse.overlay`` file so it falls back to ``native_sim.overlay``). * If this is build with ``FILE_SUFFIX`` set to ``mouse`` for ``qemu_cortex_m3`` then ``prj_mouse.conf`` will be used and ``boards/qemu_cortex_m3_mouse.overlay`` will be used. From 11530015ad102232ae6865353fc4ef6aec00a94c Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 14:13:06 +0100 Subject: [PATCH 1074/2402] drivers/gpio emul: Fix reference to example overlay That file does not exist anymore, let's refer to its new name. Signed-off-by: Alberto Escolar Piedras --- drivers/gpio/Kconfig.emul | 2 +- include/zephyr/drivers/gpio/gpio_emul.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/Kconfig.emul b/drivers/gpio/Kconfig.emul index ca64e231284..4db2429ed16 100644 --- a/drivers/gpio/Kconfig.emul +++ b/drivers/gpio/Kconfig.emul @@ -15,5 +15,5 @@ config GPIO_EMUL available in drivers/gpio/gpio_emul.h . Configuration for each GPIO instance is accomplished using device tree and an example of such a configuration is in - tests/drivers/gpio/gpio_basic_api/boards/native_posix_64.overlay + tests/drivers/gpio/gpio_basic_api/boards/native_sim.overlay If unsure, say N. diff --git a/include/zephyr/drivers/gpio/gpio_emul.h b/include/zephyr/drivers/gpio/gpio_emul.h index 02e13e15104..5eecf98da43 100644 --- a/include/zephyr/drivers/gpio/gpio_emul.h +++ b/include/zephyr/drivers/gpio/gpio_emul.h @@ -36,7 +36,7 @@ extern "C" { * @ref gpio_emul_input_set_masked in order to emulate GPIO events * * An example of an appropriate Device Tree overlay file is in - * tests/drivers/gpio/gpio_basic_api/boards/native_posix_64.overlay. + * tests/drivers/gpio/gpio_basic_api/boards/native_sim.overlay. * * An example of registering a callback to emulate "wiring" as well as * an example of calling @ref gpio_emul_input_set is in the file From 46193f48f6be4a8b550bccb81c2fc436534c6730 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 14:20:36 +0100 Subject: [PATCH 1075/2402] drivers/sensor/bma4xx/Kconfig: Change native_posix reference to native_sim As we are replacing native_posix with native_sim, let's use native_sim instead of native_posix as example platform. Signed-off-by: Alberto Escolar Piedras --- drivers/sensor/bma4xx/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/sensor/bma4xx/Kconfig b/drivers/sensor/bma4xx/Kconfig index 01a09ccdfd5..eaffa556086 100644 --- a/drivers/sensor/bma4xx/Kconfig +++ b/drivers/sensor/bma4xx/Kconfig @@ -28,4 +28,4 @@ config EMUL_BMA4XX depends on EMUL help Enable the hardware emulator for the BMA4XX. Doing so allows exercising - sensor APIs for this sensor in native_posix and qemu. + sensor APIs for this sensor in native_sim and qemu. From f532937e921d3a2053bd0be408488d335e63d662 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 14:37:21 +0100 Subject: [PATCH 1076/2402] tests|scripts/net: Change native_posix references to native_sim * As we are replacing native_posix with native_sim, let's refer to native_sim instead of native_posix in the comments of why we have 1 extra interface. * scripts/net/run-sample-tests.sh builds for native_sim now, not native_posix => let's fix it Signed-off-by: Alberto Escolar Piedras --- scripts/net/README.txt | 2 +- tests/net/checksum_offload/src/main.c | 2 +- tests/net/iface/src/main.c | 2 +- tests/net/promiscuous/src/main.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/scripts/net/README.txt b/scripts/net/README.txt index 2d184ce1d38..7a4dee569a7 100644 --- a/scripts/net/README.txt +++ b/scripts/net/README.txt @@ -46,7 +46,7 @@ User can see what samples are supported like this: $ZEPHYR_BASE/scripts/net/run-sample-tests.sh --scan The Docker container and a corresponding 'net-tools0' Docker network is started -by the script, as well as Zephyr using native_posix board. IP addresses are +by the script, as well as Zephyr using native_sim board. IP addresses are assigned to the Docker network, which is a Linux network bridge interface. The default IP addresses are: diff --git a/tests/net/checksum_offload/src/main.c b/tests/net/checksum_offload/src/main.c index da65d69f4f9..978488ad298 100644 --- a/tests/net/checksum_offload/src/main.c +++ b/tests/net/checksum_offload/src/main.c @@ -72,7 +72,7 @@ static struct in_addr in4addr_dst = { { { 192, 0, 2, 2 } } }; static struct in_addr in4addr_my2 = { { { 192, 0, 42, 1 } } }; static struct in_addr in4addr_dst2 = { { { 192, 0, 42, 2 } } }; -/* Keep track of all ethernet interfaces. For native_posix board, we need +/* Keep track of all ethernet interfaces. For native_sim board, we need * to increase the count as it has one extra network interface defined in * eth_native_posix driver. */ diff --git a/tests/net/iface/src/main.c b/tests/net/iface/src/main.c index d5cada6fc46..54125c34ea6 100644 --- a/tests/net/iface/src/main.c +++ b/tests/net/iface/src/main.c @@ -297,7 +297,7 @@ static void iface_cb(struct net_if *iface, void *user_data) const struct ethernet_api *api = net_if_get_device(iface)->api; - /* As native_posix board will introduce another ethernet + /* As native_sim board will introduce another ethernet * interface, make sure that we only use our own in this test. */ if (api->get_capabilities == diff --git a/tests/net/promiscuous/src/main.c b/tests/net/promiscuous/src/main.c index 9bedd9773b9..364917b7de3 100644 --- a/tests/net/promiscuous/src/main.c +++ b/tests/net/promiscuous/src/main.c @@ -178,7 +178,7 @@ static void iface_cb(struct net_if *iface, void *user_data) const struct ethernet_api *api = net_if_get_device(iface)->api; - /* As native_posix board will introduce another ethernet + /* As native_sim board will introduce another ethernet * interface, make sure that we only use our own in this test. */ if (api->get_capabilities == From 50542682df94f213ad31e8b17f75c77c8e14ff7e Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 14:39:20 +0100 Subject: [PATCH 1077/2402] subsys/testsuite/ztest: Replace native_posix in one comment As we are replacing native_posix with native_sim, let's refer to native_sim instead of native_posix in the comments. Signed-off-by: Alberto Escolar Piedras --- subsys/testsuite/ztest/src/ztest_posix.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/testsuite/ztest/src/ztest_posix.c b/subsys/testsuite/ztest/src/ztest_posix.c index fe6280c552f..438e11a56db 100644 --- a/subsys/testsuite/ztest/src/ztest_posix.c +++ b/subsys/testsuite/ztest/src/ztest_posix.c @@ -9,7 +9,7 @@ #include #include -#include "cmdline.h" /* native_posix command line options header */ +#include "cmdline.h" /* native_sim command line options header */ #include "soc.h" #include #include From 64fd289b2f20e877581668df884fc7198a7fa34c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jakob=20Gen=C3=9Fler?= Date: Fri, 15 Mar 2024 17:54:13 +0100 Subject: [PATCH 1078/2402] sd: sdmmc: initialize cmd retries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sets the retries in cmd struct to their Kconfig value. This fixes an issue in imx_usdhc.c where retries would be used uninitialized. That leads to a loop not being entered and subsequently no data being read from the controller. Tested on mimxrt1170_evk. Signed-off-by: Jakob Genßler --- subsys/sd/sdmmc.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/subsys/sd/sdmmc.c b/subsys/sd/sdmmc.c index 3fea5751a32..b2cbd59fdc7 100644 --- a/subsys/sd/sdmmc.c +++ b/subsys/sd/sdmmc.c @@ -75,6 +75,8 @@ static int sdmmc_spi_send_ocr(struct sd_card *card, uint32_t arg) cmd.opcode = SD_SPI_READ_OCR; cmd.arg = arg; cmd.response_type = SD_SPI_RSP_TYPE_R3; + cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT; + cmd.retries = CONFIG_SD_CMD_RETRIES; ret = sdhc_request(card->sdhc, &cmd, NULL); @@ -103,6 +105,8 @@ static int sdmmc_send_ocr(struct sd_card *card, int ocr) cmd.arg = ocr; cmd.response_type = (SD_RSP_TYPE_R3 | SD_SPI_RSP_TYPE_R1); cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT; + cmd.retries = CONFIG_SD_CMD_RETRIES; + /* Send initialization ACMD41 */ for (retries = 0; retries < CONFIG_SD_OCR_RETRY_COUNT; retries++) { ret = sdmmc_app_command(card, 0U); @@ -171,6 +175,7 @@ static int sdmmc_read_scr(struct sd_card *card) cmd.arg = 0; cmd.response_type = (SD_RSP_TYPE_R1 | SD_SPI_RSP_TYPE_R1); cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT; + cmd.retries = CONFIG_SD_CMD_RETRIES; data.block_size = 8U; data.blocks = 1U; @@ -209,8 +214,9 @@ static int sdmmc_set_blocklen(struct sd_card *card, uint32_t block_len) cmd.opcode = SD_SET_BLOCK_SIZE; cmd.arg = block_len; - cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT; cmd.response_type = (SD_RSP_TYPE_R1 | SD_SPI_RSP_TYPE_R1); + cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT; + cmd.retries = CONFIG_SD_CMD_RETRIES; return sdhc_request(card->sdhc, &cmd, NULL); } @@ -234,9 +240,12 @@ static int sdmmc_set_bus_width(struct sd_card *card, enum sdhc_bus_width width) LOG_DBG("SD app command failed for ACMD6"); return ret; } + cmd.opcode = SD_APP_SET_BUS_WIDTH; cmd.response_type = SD_RSP_TYPE_R1; cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT; + cmd.retries = CONFIG_SD_CMD_RETRIES; + switch (width) { case SDHC_BUS_WIDTH1BIT: cmd.arg = 0U; @@ -286,6 +295,7 @@ static int sdmmc_switch(struct sd_card *card, enum sd_switch_arg mode, cmd.arg |= (value & 0xF) << (group * 4); cmd.response_type = (SD_RSP_TYPE_R1 | SD_SPI_RSP_TYPE_R1); cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT; + cmd.retries = CONFIG_SD_CMD_RETRIES; data.block_size = 64U; data.blocks = 1; From 3d1a4039eabe1e72163088baefec960076aec686 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jakob=20Gen=C3=9Fler?= Date: Fri, 15 Mar 2024 17:55:09 +0100 Subject: [PATCH 1079/2402] sd: sdmmc: fix formatting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Formats according to latest .clang-format rules. Signed-off-by: Jakob Genßler --- subsys/sd/sdmmc.c | 84 +++++++++++++++++++++-------------------------- 1 file changed, 37 insertions(+), 47 deletions(-) diff --git a/subsys/sd/sdmmc.c b/subsys/sd/sdmmc.c index b2cbd59fdc7..5b9854cc95b 100644 --- a/subsys/sd/sdmmc.c +++ b/subsys/sd/sdmmc.c @@ -18,8 +18,7 @@ LOG_MODULE_DECLARE(sd, CONFIG_SD_LOG_LEVEL); -static inline void sdmmc_decode_scr(struct sd_scr *scr, - uint32_t *raw_scr, uint8_t *version) +static inline void sdmmc_decode_scr(struct sd_scr *scr, uint32_t *raw_scr, uint8_t *version) { uint32_t tmp_version = 0; @@ -173,7 +172,7 @@ static int sdmmc_read_scr(struct sd_card *card) cmd.opcode = SD_APP_SEND_SCR; cmd.arg = 0; - cmd.response_type = (SD_RSP_TYPE_R1 | SD_SPI_RSP_TYPE_R1); + cmd.response_type = (SD_RSP_TYPE_R1 | SD_SPI_RSP_TYPE_R1); cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT; cmd.retries = CONFIG_SD_CMD_RETRIES; @@ -214,7 +213,7 @@ static int sdmmc_set_blocklen(struct sd_card *card, uint32_t block_len) cmd.opcode = SD_SET_BLOCK_SIZE; cmd.arg = block_len; - cmd.response_type = (SD_RSP_TYPE_R1 | SD_SPI_RSP_TYPE_R1); + cmd.response_type = (SD_RSP_TYPE_R1 | SD_SPI_RSP_TYPE_R1); cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT; cmd.retries = CONFIG_SD_CMD_RETRIES; @@ -283,8 +282,8 @@ static int sdmmc_set_bus_width(struct sd_card *card, enum sdhc_bus_width width) * argument corresponding to that function to "value", and all other 4 bit * blocks should be left as 0xF (no effect on current function) */ -static int sdmmc_switch(struct sd_card *card, enum sd_switch_arg mode, - enum sd_group_num group, uint8_t value, uint8_t *response) +static int sdmmc_switch(struct sd_card *card, enum sd_switch_arg mode, enum sd_group_num group, + uint8_t value, uint8_t *response) { struct sdhc_command cmd = {0}; struct sdhc_data data = {0}; @@ -351,20 +350,20 @@ static inline void sdmmc_select_bus_speed(struct sd_card *card) * selection is defined using values 0x0-0xF. */ if (card->host_props.host_caps.sdr104_support && - (card->switch_caps.bus_speed & UHS_SDR104_BUS_SPEED) && - (card->host_props.f_max >= SD_CLOCK_208MHZ)) { + (card->switch_caps.bus_speed & UHS_SDR104_BUS_SPEED) && + (card->host_props.f_max >= SD_CLOCK_208MHZ)) { card->card_speed = SD_TIMING_SDR104; } else if (card->host_props.host_caps.ddr50_support && - (card->switch_caps.bus_speed & UHS_DDR50_BUS_SPEED) && - (card->host_props.f_max >= SD_CLOCK_50MHZ)) { + (card->switch_caps.bus_speed & UHS_DDR50_BUS_SPEED) && + (card->host_props.f_max >= SD_CLOCK_50MHZ)) { card->card_speed = SD_TIMING_DDR50; } else if (card->host_props.host_caps.sdr50_support && - (card->switch_caps.bus_speed & UHS_SDR50_BUS_SPEED) && - (card->host_props.f_max >= SD_CLOCK_100MHZ)) { + (card->switch_caps.bus_speed & UHS_SDR50_BUS_SPEED) && + (card->host_props.f_max >= SD_CLOCK_100MHZ)) { card->card_speed = SD_TIMING_SDR50; } else if (card->host_props.host_caps.high_spd_support && - (card->switch_caps.bus_speed & UHS_SDR12_BUS_SPEED) && - (card->host_props.f_max >= SD_CLOCK_25MHZ)) { + (card->switch_caps.bus_speed & UHS_SDR12_BUS_SPEED) && + (card->host_props.f_max >= SD_CLOCK_25MHZ)) { card->card_speed = SD_TIMING_SDR12; } } @@ -380,12 +379,11 @@ static int sdmmc_select_driver_type(struct sd_card *card) * since it should result in lower current consumption if supported. */ if (card->host_props.host_caps.drv_type_c_support && - (card->switch_caps.sd_drv_type & SD_DRIVER_TYPE_C)) { + (card->switch_caps.sd_drv_type & SD_DRIVER_TYPE_C)) { card->bus_io.driver_type = SD_DRIVER_TYPE_C; /* Change drive strength */ - ret = sdmmc_switch(card, SD_SWITCH_SET, - SD_GRP_DRIVER_STRENGTH_MODE, - (find_msb_set(SD_DRIVER_TYPE_C) - 1), status); + ret = sdmmc_switch(card, SD_SWITCH_SET, SD_GRP_DRIVER_STRENGTH_MODE, + (find_msb_set(SD_DRIVER_TYPE_C) - 1), status); } return ret; } @@ -397,28 +395,27 @@ static int sdmmc_set_current_limit(struct sd_card *card) int max_current = -1; uint8_t *status = card->card_buffer; - if ((card->card_speed != SD_TIMING_SDR50) && - (card->card_speed != SD_TIMING_SDR104) && - (card->card_speed != SD_TIMING_DDR50)) { + if ((card->card_speed != SD_TIMING_SDR50) && (card->card_speed != SD_TIMING_SDR104) && + (card->card_speed != SD_TIMING_DDR50)) { return 0; /* Cannot set current limit */ } else if (card->host_props.max_current_180 >= 800 && - (card->switch_caps.sd_current_limit & SD_MAX_CURRENT_800MA)) { + (card->switch_caps.sd_current_limit & SD_MAX_CURRENT_800MA)) { max_current = SD_SET_CURRENT_800MA; } else if (card->host_props.max_current_180 >= 600 && - (card->switch_caps.sd_current_limit & SD_MAX_CURRENT_600MA)) { + (card->switch_caps.sd_current_limit & SD_MAX_CURRENT_600MA)) { max_current = SD_SET_CURRENT_600MA; } else if (card->host_props.max_current_180 >= 400 && - (card->switch_caps.sd_current_limit & SD_MAX_CURRENT_400MA)) { + (card->switch_caps.sd_current_limit & SD_MAX_CURRENT_400MA)) { max_current = SD_SET_CURRENT_400MA; } else if (card->host_props.max_current_180 >= 200 && - (card->switch_caps.sd_current_limit & SD_MAX_CURRENT_200MA)) { + (card->switch_caps.sd_current_limit & SD_MAX_CURRENT_200MA)) { max_current = SD_SET_CURRENT_200MA; } if (max_current != -1) { LOG_DBG("Changing SD current limit: %d", max_current); /* Switch SD current */ - ret = sdmmc_switch(card, SD_SWITCH_SET, SD_GRP_CURRENT_LIMIT_MODE, - max_current, status); + ret = sdmmc_switch(card, SD_SWITCH_SET, SD_GRP_CURRENT_LIMIT_MODE, max_current, + status); if (ret) { LOG_DBG("Failed to set SD current limit"); return ret; @@ -466,8 +463,7 @@ static int sdmmc_set_bus_speed(struct sd_card *card) } /* Switch bus speed */ - ret = sdmmc_switch(card, SD_SWITCH_SET, SD_GRP_TIMING_MODE, - card->card_speed, status); + ret = sdmmc_switch(card, SD_SWITCH_SET, SD_GRP_TIMING_MODE, card->card_speed, status); if (ret) { LOG_DBG("Failed to switch SD card speed"); return ret; @@ -521,9 +517,8 @@ static int sdmmc_init_uhs(struct sd_card *card) LOG_DBG("Failed to set card bus speed"); return ret; } - if (card->card_speed == SD_TIMING_SDR50 || - card->card_speed == SD_TIMING_SDR104 || - card->card_speed == SD_TIMING_DDR50) { + if (card->card_speed == SD_TIMING_SDR50 || card->card_speed == SD_TIMING_SDR104 || + card->card_speed == SD_TIMING_DDR50) { /* SDR104, SDR50, and DDR50 mode need tuning */ ret = sdhc_execute_tuning(card->sdhc); if (ret) { @@ -538,9 +533,8 @@ static int sdmmc_init_hs(struct sd_card *card) { int ret; - if ((!card->host_props.host_caps.high_spd_support) || - (card->sd_version < SD_SPEC_VER1_1) || - (card->switch_caps.hs_max_dtr == 0)) { + if ((!card->host_props.host_caps.high_spd_support) || (card->sd_version < SD_SPEC_VER1_1) || + (card->switch_caps.hs_max_dtr == 0)) { /* No high speed support. Leave card untouched */ return 0; } @@ -638,10 +632,8 @@ int sdmmc_card_init(struct sd_card *card) * switch to new signal voltage using "signal voltage switch procedure" * described in SD specification */ - if ((card->flags & SD_1800MV_FLAG) && - (card->host_props.host_caps.vol_180_support) && - (!card->host_props.is_spi) && - IS_ENABLED(CONFIG_SD_UHS_PROTOCOL)) { + if ((card->flags & SD_1800MV_FLAG) && (card->host_props.host_caps.vol_180_support) && + (!card->host_props.is_spi) && IS_ENABLED(CONFIG_SD_UHS_PROTOCOL)) { ret = sdmmc_switch_voltage(card); if (ret) { /* Disable host support for 1.8 V */ @@ -713,10 +705,8 @@ int sdmmc_card_init(struct sd_card *card) return ret; } } - if ((card->flags & SD_1800MV_FLAG) && - sdmmc_host_uhs(&card->host_props) && - !(card->host_props.is_spi) && - IS_ENABLED(CONFIG_SD_UHS_PROTOCOL)) { + if ((card->flags & SD_1800MV_FLAG) && sdmmc_host_uhs(&card->host_props) && + !(card->host_props.is_spi) && IS_ENABLED(CONFIG_SD_UHS_PROTOCOL)) { ret = sdmmc_init_uhs(card); if (ret) { LOG_ERR("UHS card init failed"); @@ -745,14 +735,14 @@ int sdmmc_ioctl(struct sd_card *card, uint8_t cmd, void *buf) return card_ioctl(card, cmd, buf); } -int sdmmc_read_blocks(struct sd_card *card, uint8_t *rbuf, - uint32_t start_block, uint32_t num_blocks) +int sdmmc_read_blocks(struct sd_card *card, uint8_t *rbuf, uint32_t start_block, + uint32_t num_blocks) { return card_read_blocks(card, rbuf, start_block, num_blocks); } -int sdmmc_write_blocks(struct sd_card *card, const uint8_t *wbuf, - uint32_t start_block, uint32_t num_blocks) +int sdmmc_write_blocks(struct sd_card *card, const uint8_t *wbuf, uint32_t start_block, + uint32_t num_blocks) { return card_write_blocks(card, wbuf, start_block, num_blocks); } From e336c644beea3dc21cf1f02e2c8a62ff49f87d52 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 14 Mar 2024 16:23:58 -0500 Subject: [PATCH 1080/2402] drivers: wdt_mcux_wwdt: Support RW Support RW soc series in wwdt driver Signed-off-by: Declan Snyder --- drivers/watchdog/wdt_mcux_wwdt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/watchdog/wdt_mcux_wwdt.c b/drivers/watchdog/wdt_mcux_wwdt.c index 0181b3d406f..55faafed874 100644 --- a/drivers/watchdog/wdt_mcux_wwdt.c +++ b/drivers/watchdog/wdt_mcux_wwdt.c @@ -84,6 +84,8 @@ static int mcux_wwdt_install_timeout(const struct device *dev, #if defined(CONFIG_SOC_MIMXRT685S_CM33) || defined(CONFIG_SOC_MIMXRT595S_CM33) clock_freq = CLOCK_GetWdtClkFreq(0); +#elif defined(CONFIG_SOC_SERIES_RW6XX) + clock_freq = CLOCK_GetWdtClkFreq(); #else const struct mcux_wwdt_config *config = dev->config; From 2cb4550dc727ec4c1ad05be1bad36a35b0e7b072 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 14 Mar 2024 16:24:30 -0500 Subject: [PATCH 1081/2402] soc: rw: Support WWDT Add DT entry and SOC code for watchdog Signed-off-by: Declan Snyder --- dts/arm/nxp/nxp_rw6xx_common.dtsi | 8 ++++++++ soc/nxp/rw/soc.c | 12 ++++++++++++ 2 files changed, 20 insertions(+) diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index 0490fc9ee82..17b9cfb2ba6 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -76,6 +76,14 @@ interrupts = <123 0>; }; + wwdt: watchdog@e000 { + compatible = "nxp,lpc-wwdt"; + reg = <0xe000 0x1000>; + interrupts = <0 0>; + status = "disabled"; + clk-divider = <1>; + }; + hsgpio0: hsgpio@0 { compatible = "nxp,lpc-gpio"; reg = <0x100000 0x4000>; diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c index 01c1d22c764..236c524d642 100644 --- a/soc/nxp/rw/soc.c +++ b/soc/nxp/rw/soc.c @@ -137,6 +137,15 @@ __ramfunc void clock_init(void) /* Call function set_flexspi_clock() to set flexspi clock source to aux0_pll_clk in XIP. */ set_flexspi_clock(FLEXSPI, 2U, 2U); +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt), nxp_lpc_wwdt, okay)) + CLOCK_AttachClk(kLPOSC_to_WDT0_CLK); +#else + /* Allowed to select none if not being used for watchdog to + * reduce power + */ + CLOCK_AttachClk(kNONE_to_WDT0_CLK); +#endif + /* Any flexcomm can be USART */ #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay)) && CONFIG_SERIAL CLOCK_SetFRGClock(&(const clock_frg_clk_config_t){0, kCLOCK_FrgPllDiv, 255, 0}); @@ -212,6 +221,9 @@ __ramfunc void clock_init(void) static int nxp_rw600_init(void) { +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt), nxp_lpc_wwdt, okay)) + POWER_EnableResetSource(kPOWER_ResetSourceWdt); +#endif /* Initialize clock */ clock_init(); From 1680223003355673decdf18e7fd98efd9fbd2502 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 14 Mar 2024 16:24:56 -0500 Subject: [PATCH 1082/2402] boards: rd_rw612_bga: Enable WWDT Enable watchdog on RD_RW612_BGA board. Signed-off-by: Declan Snyder --- boards/nxp/rd_rw612_bga/doc/index.rst | 2 ++ boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 5 +++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml | 1 + 3 files changed, 8 insertions(+) diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index 59ec7f265bb..c78764f5852 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -47,6 +47,8 @@ Supported Features +-----------+------------+-----------------------------------+ | TRNG | on-chip | entropy | +-----------+------------+-----------------------------------+ +| WWDT | on-chip | watchdog | ++-----------+------------+-----------------------------------+ The default configuration can be found in the defconfig file: diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index f1c16e09962..1a1143a47bb 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -12,6 +12,7 @@ led0 = &green_led; sw0 = &sw_4; i2c-0 = &flexcomm2; + watchdog0 = &wwdt; }; chosen { @@ -40,6 +41,10 @@ }; }; +&wwdt { + status = "okay"; +}; + arduino_spi: &flexcomm0 { compatible = "nxp,lpc-spi"; pinctrl-0 = <&pinmux_flexcomm0_spi>; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml index fb876b54fa1..1f3832c88d0 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -20,3 +20,4 @@ supported: - spi - i2c - entropy + - watchdog From 67bb6db3f8e5329516f005f1335bb7a23a95b3eb Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Fri, 15 Mar 2024 14:51:39 -0700 Subject: [PATCH 1083/2402] syscall: Export all emitted syscalls, enabling them for extensions Linkable loadable extensions can only use syscalls if they are exported via EXPORT_SYSCALL (or EXPORT_SYMBOL). Instead of enabling used syscalls one by one, this patch exports all of them automatically via `gen_syscalls.py`. If CONFIG_LLEXT=n, the section where the exported symbols live is discarded, so it should be a non-op when llext is not enabled. This patch also removes the now redundant EXPORT_SYSCALL macro. Note that EXPORT_SYMBOL is still useful on different situations (and is indeed used by the code generated by `gen_syscalls.py`). Signed-off-by: Ederson de Souza --- include/zephyr/llext/symbol.h | 10 ---------- kernel/mutex.c | 2 -- scripts/build/gen_syscalls.py | 10 +++++++++- subsys/logging/log_msg.c | 1 - 4 files changed, 9 insertions(+), 14 deletions(-) diff --git a/include/zephyr/llext/symbol.h b/include/zephyr/llext/symbol.h index 993e2c4a519..8691301ac09 100644 --- a/include/zephyr/llext/symbol.h +++ b/include/zephyr/llext/symbol.h @@ -83,16 +83,6 @@ struct llext_symtable { struct llext_symbol Z_GENERIC_SECTION(".exported_sym") __used \ symbol_##x = {STRINGIFY(x), (void *)&x} -/** - * @brief Export a system call to a table of symbols - * - * Takes a system call name and uses @a EXPORT_SYMBOL() to export the respective - * function. - * - * @param x System call to export - */ -#define EXPORT_SYSCALL(x) EXPORT_SYMBOL(z_impl_ ## x) - /** * @} */ diff --git a/kernel/mutex.c b/kernel/mutex.c index 808e06eda46..328a75ca9d4 100644 --- a/kernel/mutex.c +++ b/kernel/mutex.c @@ -196,7 +196,6 @@ int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout) return -EAGAIN; } -EXPORT_SYSCALL(k_mutex_lock); #ifdef CONFIG_USERSPACE static inline int z_vrfy_k_mutex_lock(struct k_mutex *mutex, @@ -282,7 +281,6 @@ int z_impl_k_mutex_unlock(struct k_mutex *mutex) return 0; } -EXPORT_SYSCALL(k_mutex_unlock); #ifdef CONFIG_USERSPACE static inline int z_vrfy_k_mutex_unlock(struct k_mutex *mutex) diff --git a/scripts/build/gen_syscalls.py b/scripts/build/gen_syscalls.py index 68d0f15f48b..3741707f803 100755 --- a/scripts/build/gen_syscalls.py +++ b/scripts/build/gen_syscalls.py @@ -52,6 +52,8 @@ table_template = """/* auto-generated by gen_syscalls.py, don't edit */ +#include + /* Weak handler functions that get replaced by the real ones unless a system * call is not implemented due to kernel configuration. */ @@ -60,6 +62,8 @@ const _k_syscall_handler_t _k_syscall_table[K_SYSCALL_LIMIT] = { \t%s }; +/* Export syscalls for extensions */ +%s """ list_template = """/* auto-generated by gen_syscalls.py, don't edit */ @@ -460,8 +464,12 @@ def main(): weak_defines += "\n".join(["extern uintptr_t %s(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, uintptr_t arg4, uintptr_t arg5, uintptr_t arg6, void *ssf);" % s for s in noweak]) + # Export symbols for emitted syscalls + exported_symbols = "\n".join("EXPORT_SYMBOL(%s);" % e for e in emit_list) + fp.write(table_template % (weak_defines, - ",\n\t".join(table_entries))) + ",\n\t".join(table_entries), + exported_symbols)) # Listing header emitted to stdout ids_emit.sort() diff --git a/subsys/logging/log_msg.c b/subsys/logging/log_msg.c index ef9b777eb69..6c1cc3c5783 100644 --- a/subsys/logging/log_msg.c +++ b/subsys/logging/log_msg.c @@ -329,7 +329,6 @@ void z_impl_z_log_msg_static_create(const void *source, z_log_msg_finalize(msg, source, out_desc, data); } -EXPORT_SYSCALL(z_log_msg_static_create); #ifdef CONFIG_USERSPACE static inline void z_vrfy_z_log_msg_static_create(const void *source, From 9e0d7f0264d2897f384753b193c630ac6b7692f0 Mon Sep 17 00:00:00 2001 From: Mateusz Kapala Date: Mon, 18 Mar 2024 16:35:07 +0100 Subject: [PATCH 1084/2402] mgmt: mcumgr: Add Kconfig option to manage SMP service registration Added the CONFIG_MCUMGR_TRANSPORT_BT_DYNAMIC_SVC_REGISTRATION Kconfig option to manage how the SMP service should be registered. By default the SMP service must be registered at runtime. If this Kconfig option is disabled, the SMP service is statically defined and registered. This change allows to opt out of using the CONFIG_BT_GATT_DYNAMIC_DB Kconfig option and as a result, lower the memory usage. Signed-off-by: Mateusz Kapala --- .../mgmt/mcumgr/transport/Kconfig.bluetooth | 10 +++- subsys/mgmt/mcumgr/transport/src/smp_bt.c | 48 +++++++++---------- 2 files changed, 33 insertions(+), 25 deletions(-) diff --git a/subsys/mgmt/mcumgr/transport/Kconfig.bluetooth b/subsys/mgmt/mcumgr/transport/Kconfig.bluetooth index 301940a47e4..bb442d01985 100644 --- a/subsys/mgmt/mcumgr/transport/Kconfig.bluetooth +++ b/subsys/mgmt/mcumgr/transport/Kconfig.bluetooth @@ -12,7 +12,6 @@ menuconfig MCUMGR_TRANSPORT_BT bool "Bluetooth mcumgr SMP transport" depends on BT_PERIPHERAL - select BT_GATT_DYNAMIC_DB help Enables handling of SMP commands received over Bluetooth. @@ -92,4 +91,13 @@ config MCUMGR_TRANSPORT_BT_CONN_PARAM_CONTROL_RETRY_TIME endif # MCUMGR_TRASNPORT_BT_CONN_PARAM_CONTROL +config MCUMGR_TRANSPORT_BT_DYNAMIC_SVC_REGISTRATION + bool "Register SMP service at runtime" + select BT_GATT_DYNAMIC_DB + default y + help + When enabled, the SMP service will be automatically registered at boot time + and can then be dynamically registered/unregistered using a dedicated API. + Otherwise, the SMP service will be statically defined and registered. + endif # MCUMGR_TRANSPORT_BT diff --git a/subsys/mgmt/mcumgr/transport/src/smp_bt.c b/subsys/mgmt/mcumgr/transport/src/smp_bt.c index e646c80b35b..79fbb45ebcf 100644 --- a/subsys/mgmt/mcumgr/transport/src/smp_bt.c +++ b/subsys/mgmt/mcumgr/transport/src/smp_bt.c @@ -353,33 +353,31 @@ static void smp_bt_ccc_changed(const struct bt_gatt_attr *attr, uint16_t value) #endif } -static struct bt_gatt_attr smp_bt_attrs[] = { - /* SMP Primary Service Declaration */ - BT_GATT_PRIMARY_SERVICE(&smp_bt_svc_uuid), - - BT_GATT_CHARACTERISTIC(&smp_bt_chr_uuid.uuid, - BT_GATT_CHRC_WRITE_WITHOUT_RESP | - BT_GATT_CHRC_NOTIFY, -#ifdef CONFIG_MCUMGR_TRANSPORT_BT_AUTHEN - BT_GATT_PERM_WRITE_AUTHEN, +#define SMP_BT_ATTRS \ + BT_GATT_PRIMARY_SERVICE(&smp_bt_svc_uuid), \ + BT_GATT_CHARACTERISTIC(&smp_bt_chr_uuid.uuid, \ + BT_GATT_CHRC_WRITE_WITHOUT_RESP | \ + BT_GATT_CHRC_NOTIFY, \ + COND_CODE_1(CONFIG_MCUMGR_TRANSPORT_BT_AUTHEN, \ + (BT_GATT_PERM_WRITE_AUTHEN), \ + (BT_GATT_PERM_WRITE)), \ + NULL, smp_bt_chr_write, NULL), \ + BT_GATT_CCC(smp_bt_ccc_changed, \ + COND_CODE_1(CONFIG_MCUMGR_TRANSPORT_BT_AUTHEN, \ + (BT_GATT_PERM_READ_AUTHEN | BT_GATT_PERM_WRITE_AUTHEN), \ + (BT_GATT_PERM_READ | BT_GATT_PERM_WRITE))), + + +#ifdef CONFIG_MCUMGR_TRANSPORT_BT_DYNAMIC_SVC_REGISTRATION +static struct bt_gatt_attr attr_smp_bt_svc[] = {SMP_BT_ATTRS}; +static struct bt_gatt_service smp_bt_svc = BT_GATT_SERVICE(attr_smp_bt_svc); #else - BT_GATT_PERM_WRITE, +BT_GATT_SERVICE_DEFINE(smp_bt_svc, SMP_BT_ATTRS); #endif - NULL, smp_bt_chr_write, NULL), - BT_GATT_CCC(smp_bt_ccc_changed, -#ifdef CONFIG_MCUMGR_TRANSPORT_BT_AUTHEN - BT_GATT_PERM_READ_AUTHEN | - BT_GATT_PERM_WRITE_AUTHEN), -#else - BT_GATT_PERM_READ | BT_GATT_PERM_WRITE), -#endif -}; - -static struct bt_gatt_service smp_bt_svc = BT_GATT_SERVICE(smp_bt_attrs); int smp_bt_notify(struct bt_conn *conn, const void *data, uint16_t len) { - return bt_gatt_notify(conn, smp_bt_attrs + 2, data, len); + return bt_gatt_notify(conn, attr_smp_bt_svc + 2, data, len); } /** @@ -449,7 +447,7 @@ static int smp_bt_tx_pkt(struct net_buf *nb) uint16_t off = 0; uint16_t mtu_size; struct bt_gatt_notify_params notify_param = { - .attr = smp_bt_attrs + 2, + .attr = attr_smp_bt_svc + 2, .func = smp_notify_finished, .data = nb->data, }; @@ -564,6 +562,7 @@ static int smp_bt_tx_pkt(struct net_buf *nb) return rc; } +#ifdef CONFIG_MCUMGR_TRANSPORT_BT_DYNAMIC_SVC_REGISTRATION int smp_bt_register(void) { return bt_gatt_service_register(&smp_bt_svc); @@ -573,6 +572,7 @@ int smp_bt_unregister(void) { return bt_gatt_service_unregister(&smp_bt_svc); } +#endif /* BT connected callback. */ static void connected(struct bt_conn *conn, uint8_t err) @@ -667,7 +667,7 @@ static void smp_bt_setup(void) rc = smp_transport_init(&smp_bt_transport); - if (rc == 0) { + if (IS_ENABLED(CONFIG_MCUMGR_TRANSPORT_BT_DYNAMIC_SVC_REGISTRATION) && rc == 0) { rc = smp_bt_register(); } From 5ff8249d198135492d0080efc9be47802004618e Mon Sep 17 00:00:00 2001 From: Mateusz Kapala Date: Tue, 19 Mar 2024 11:24:30 +0100 Subject: [PATCH 1085/2402] samples: subsys: mgmt: mcumgr: smp_svr: Add BT static svc registration Added build configuration for the CONFIG_MCUBOOT_BOOTLOADER_MODE_DIRECT_XIP_WITH_REVERT=n (non-default option) to test building the smp_svr sample with statically defined and registered SMP service. Signed-off-by: Mateusz Kapala --- samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml index 007179b2f80..6a3669b2438 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml +++ b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml @@ -15,6 +15,16 @@ tests: integration_platforms: - nrf52dk/nrf52832 - nrf52840dk/nrf52840 + sample.mcumgr.smp_svr.bt_static_svc: + extra_args: OVERLAY_CONFIG="overlay-bt.conf" + extra_configs: + - CONFIG_MCUMGR_TRANSPORT_BT_DYNAMIC_SVC_REGISTRATION=n + platform_allow: + - nrf52840dk/nrf52840 + - pinnacle_100_dvk + - mg100 + integration_platforms: + - nrf52840dk/nrf52840 sample.mcumgr.smp_svr.udp: extra_args: OVERLAY_CONFIG="overlay-udp.conf" platform_allow: frdm_k64f From 02b84fbb0e787202d72b9a1aac8b4796b59bca6b Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Wed, 20 Mar 2024 12:17:16 +0100 Subject: [PATCH 1086/2402] boards: nxp: mr_canhubk3: CAN requires 120 ohm termination at both ends CAN requires 120 ohm termination at both ends of the bus, resulting in a bus impedance of 60 ohm. Fix the board documentation to reflect this. Signed-off-by: Henrik Brix Andersen --- boards/nxp/mr_canhubk3/doc/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/nxp/mr_canhubk3/doc/index.rst b/boards/nxp/mr_canhubk3/doc/index.rst index 2fe3780236a..8ae701e3d30 100644 --- a/boards/nxp/mr_canhubk3/doc/index.rst +++ b/boards/nxp/mr_canhubk3/doc/index.rst @@ -195,7 +195,7 @@ flexcan5 | 8 bytes | 32 MBs | 32 MBs =============== ========== ================ ================ .. note:: - A CAN bus usually requires 60 Ohm termination at both ends of the bus. This may be + A CAN bus usually requires 120 Ohm termination at both ends of the bus. This may be accomplished using one of the included CAN termination boards. For more details, refer to the section ``6.3 CAN Connectors`` in the Hardware User Manual of `NXP MR-CANHUBK3`_. From c3b96ffbabd2d24fc059538ebdc0122e757e868f Mon Sep 17 00:00:00 2001 From: Piotr Kosycarz Date: Wed, 20 Mar 2024 13:44:06 +0100 Subject: [PATCH 1087/2402] scripts: twister: handlers: pass dev-id for nrfutil Needed to distinguish boards. Signed-off-by: Piotr Kosycarz --- scripts/pylib/twister/twisterlib/handlers.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py index d156fa6b3d2..a2cd97d8079 100755 --- a/scripts/pylib/twister/twisterlib/handlers.py +++ b/scripts/pylib/twister/twisterlib/handlers.py @@ -500,7 +500,7 @@ def _create_command(self, runner, hardware): board_id = hardware.probe_id or hardware.id product = hardware.product if board_id is not None: - if runner in ("pyocd", "nrfjprog"): + if runner in ("pyocd", "nrfjprog", "nrfutil"): command_extra_args.append("--dev-id") command_extra_args.append(board_id) elif runner == "openocd" and product == "STM32 STLink": From 4c8ed7dd9a108b505d646e3077d735bc807f6863 Mon Sep 17 00:00:00 2001 From: Dominik Ermel Date: Mon, 18 Mar 2024 16:28:57 +0000 Subject: [PATCH 1088/2402] devicetree.h: Rework DT_ANY_INST_HAS_PROP_STATUS_OKAY The macro is searching for all instances of specific device that contain specific property and evaluates to true (1) if any device does. The macro used to do that by generating, using DT_ANY_INST_HAS_PROP_STATUS_OKAY, a logical expression like (0 || 1 || 0), where each digit represented existence of property (1) or lack of it (0). Unfortunately other util macros, like IS_ENABLED, were not able to evaluate such expression, as they often simply expect something they can evaluate to 0 or 1. The commit here changes DT_ANY_INST_HAS_PROP_STATUS_OKAY to generate a list of tokens (1) where token is added to list only for instance of a device that has the property; then such list is processed using IS_EMPTY() macro and in the end 0 or 1 is generated, depending on whether any enabled instance of a device has the property or not. This change allows result of DT_ANY_INST_HAS_PROP_STATUS_OKAY to be used with macros like IS_ENABLED, IF_ENABLED or COND_CODE_x. Signed-off-by: Dominik Ermel --- include/zephyr/devicetree.h | 30 ++++++++++++++++++++++++++++- tests/lib/devicetree/api/src/main.c | 19 ++++++++++++++++++ 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/include/zephyr/devicetree.h b/include/zephyr/devicetree.h index 8ea39bf31c1..b6a8756c9ca 100644 --- a/include/zephyr/devicetree.h +++ b/include/zephyr/devicetree.h @@ -4192,7 +4192,7 @@ * @endcode */ #define DT_ANY_INST_HAS_PROP_STATUS_OKAY(prop) \ - (DT_INST_FOREACH_STATUS_OKAY_VARGS(DT_INST_NODE_HAS_PROP_AND_OR, prop) 0) + COND_CODE_1(IS_EMPTY(DT_ANY_INST_HAS_PROP_STATUS_OKAY_(prop)), (0), (1)) /** * @brief Call @p fn on all nodes with compatible `DT_DRV_COMPAT` @@ -4427,6 +4427,34 @@ /** @cond INTERNAL_HIDDEN */ +/** @brief Helper for DT_ANY_INST_HAS_PROP_STATUS_OKAY_ + * + * This macro generates token "1," for instance of a device, + * identified by index @p idx, if instance has property @p prop. + * + * @param idx instance number + * @param prop property to check for + * + * @return Macro evaluates to `1,` if instance has the property, + * otherwise it evaluates to literal nothing. + */ +#define DT_ANY_INST_HAS_PROP_STATUS_OKAY__(idx, prop) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, prop), (1,), ()) +/** @brief Helper for DT_ANY_INST_HAS_PROP_STATUS_OKAY + * + * This macro uses DT_ANY_INST_HAS_PROP_STATUS_OKAY_ with + * DT_INST_FOREACH_STATUS_OKAY_VARG to generate comma separated list of 1, + * where each 1 on the list represents instance that has a property + * @p prop; the list may be empty, and the upper bound on number of + * list elements is number of device instances. + * + * @param prop property to check + * + * @return Evaluates to list of 1s (e.g: 1,1,1,) or nothing. + */ +#define DT_ANY_INST_HAS_PROP_STATUS_OKAY_(prop) \ + DT_INST_FOREACH_STATUS_OKAY_VARGS(DT_ANY_INST_HAS_PROP_STATUS_OKAY__, prop) + #define DT_PATH_INTERNAL(...) \ UTIL_CAT(DT_ROOT, MACRO_MAP_CAT(DT_S_PREFIX, __VA_ARGS__)) /** @brief DT_PATH_INTERNAL() helper: prepends _S_ to a node name diff --git a/tests/lib/devicetree/api/src/main.c b/tests/lib/devicetree/api/src/main.c index 52197bcfb74..5c0937dbc28 100644 --- a/tests/lib/devicetree/api/src/main.c +++ b/tests/lib/devicetree/api/src/main.c @@ -190,6 +190,25 @@ ZTEST(devicetree_api, test_any_inst_prop) zassert_equal(DT_ANY_INST_HAS_PROP_STATUS_OKAY(bar), 1, ""); zassert_equal(DT_ANY_INST_HAS_PROP_STATUS_OKAY(baz), 0, ""); zassert_equal(DT_ANY_INST_HAS_PROP_STATUS_OKAY(does_not_exist), 0, ""); + + zassert_equal(COND_CODE_1(DT_ANY_INST_HAS_PROP_STATUS_OKAY(foo), + (5), (6)), + 5, ""); + zassert_equal(COND_CODE_0(DT_ANY_INST_HAS_PROP_STATUS_OKAY(foo), + (5), (6)), + 6, ""); + zassert_equal(COND_CODE_1(DT_ANY_INST_HAS_PROP_STATUS_OKAY(baz), + (5), (6)), + 6, ""); + zassert_equal(COND_CODE_0(DT_ANY_INST_HAS_PROP_STATUS_OKAY(baz), + (5), (6)), + 5, ""); + zassert_true(IS_ENABLED(DT_ANY_INST_HAS_PROP_STATUS_OKAY(foo)), ""); + zassert_true(!IS_ENABLED(DT_ANY_INST_HAS_PROP_STATUS_OKAY(baz)), ""); + zassert_equal(IF_ENABLED(DT_ANY_INST_HAS_PROP_STATUS_OKAY(foo), (1)) + 1, + 2, ""); + zassert_equal(IF_ENABLED(DT_ANY_INST_HAS_PROP_STATUS_OKAY(baz), (1)) + 1, + 1, ""); } ZTEST(devicetree_api, test_default_prop_access) From 9021ce82fcba3590e08ca27a8a2cbb6f7f1a12a4 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 15:26:38 -0500 Subject: [PATCH 1089/2402] soc: nxp: rw: add support for reclocking flexspi Add support for reclocking FlexSPI peripheral via flexspi_clock_set_freq function Signed-off-by: Daniel DeGrasse --- soc/nxp/rw/flexspi_clock_setup.c | 44 ++++++++++++++++++++++++++++++++ soc/nxp/rw/soc.h | 2 +- 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/soc/nxp/rw/flexspi_clock_setup.c b/soc/nxp/rw/flexspi_clock_setup.c index 18c74954bd3..3876e1adbf4 100644 --- a/soc/nxp/rw/flexspi_clock_setup.c +++ b/soc/nxp/rw/flexspi_clock_setup.c @@ -10,6 +10,50 @@ #include #endif +#ifdef CONFIG_MEMC +/** + * @brief Set flexspi clock to given frequency + * + * This function differs from the above function in that it will not configure + * the FlexSPI with a new MUX source, only change the divider. This function + * is used by the clock control framework to set the clock frequency of + * the FlexSPI + */ +int __ramfunc flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate) +{ + uint32_t root_rate; + uint32_t divider; + + (void)clock_name; /* Not used by this function */ + + /* Get the root clock rate: FlexSPI clock * divisor */ + root_rate = ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) + 1) * + CLOCK_GetFlexspiClkFreq(); + + /* Select a divider based on root frequency. + * if we can't get an exact divider, round down + */ + divider = ((root_rate + (rate - 1)) / rate) - 1; + /* Cap divider to max value */ + divider = MIN(divider, CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK); + + while (FLEXSPI_GetBusIdleStatus(FLEXSPI) == false) { + /* Spin */ + } + FLEXSPI_Enable(FLEXSPI, false); + + set_flexspi_clock(FLEXSPI, (CLKCTL0->FLEXSPIFCLKSEL & + CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK), (divider + 1)); + + + FLEXSPI_Enable(FLEXSPI, true); + + FLEXSPI_SoftwareReset(FLEXSPI); + + return 0; +} +#endif + /** * @brief Set flexspi clock */ diff --git a/soc/nxp/rw/soc.h b/soc/nxp/rw/soc.h index 66a2cf836b5..a9a28b3ab6e 100644 --- a/soc/nxp/rw/soc.h +++ b/soc/nxp/rw/soc.h @@ -17,7 +17,7 @@ #ifdef CONFIG_MEMC -uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); +int flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); #endif From 90a8ef11fe033befdd7d253b51a5e3a1eac65484 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 15:28:51 -0500 Subject: [PATCH 1090/2402] soc: nxp: rw: define Kconfigs for MEMC_MCUX_FLEXSPI code relocation MEMC_MCUX_FLEXSPI depends on code relocation being enabled on parts that XIP from the FlexSPI by default and requires a string describing the RAM region to relocate code into. Add these Kconfigs to the RW SOC port. Signed-off-by: Daniel DeGrasse --- soc/nxp/rw/Kconfig | 9 +++++++-- soc/nxp/rw/Kconfig.defconfig | 4 ++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/soc/nxp/rw/Kconfig b/soc/nxp/rw/Kconfig index 563b9671dba..5951cf59ab2 100644 --- a/soc/nxp/rw/Kconfig +++ b/soc/nxp/rw/Kconfig @@ -25,7 +25,7 @@ config INIT_SYS_PLL menuconfig NXP_RW6XX_BOOT_HEADER bool "Create boot header" - default y + default y if !BOOTLOADER_MCUBOOT help Create data structures required by the boot ROM to boot the application from an external flash device. @@ -57,6 +57,8 @@ config IMAGE_VECTOR_TABLE_OFFSET the application entry point and device configuration data. The boot ROM requires a fixed IVT offset for each type of boot device. +endif # NXP_RW6XX_BOOT_HEADER + # Used for default value in FLASH_MCUX_FLEXSPI_XIP DT_CHOSEN_Z_FLASH := zephyr,flash DT_COMPAT_FLEXSPI := nxp,imx-flexspi @@ -82,6 +84,9 @@ config NXP_RW_ROM_RAMLOADER FlexSPI boot device into RAM region. The image will be loaded from FLEXSPI into the region specified by `zephyr,flash` node. -endif # NXP_RW6XX_BOOT_HEADER +config FLASH_MCUX_FLEXSPI_XIP_MEM + string + default "RAM" + depends on MEMC_MCUX_FLEXSPI endif # SOC_SERIES_RW6XX diff --git a/soc/nxp/rw/Kconfig.defconfig b/soc/nxp/rw/Kconfig.defconfig index e17dffe663d..85f6cd5e825 100644 --- a/soc/nxp/rw/Kconfig.defconfig +++ b/soc/nxp/rw/Kconfig.defconfig @@ -63,6 +63,10 @@ choice MEMC_LOG_LEVEL_CHOICE default MEMC_LOG_LEVEL_OFF endchoice +# Code relocation is needed when MEMC driver is enabled +config CODE_DATA_RELOCATION_SRAM + default y if MEMC + endif # FLASH_MCUX_FLEXSPI_XIP endif # SOC_SERIES_RW6XX From adfe4b83596a695ae3bc01d91a88ffd912e1a383 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 15:31:49 -0500 Subject: [PATCH 1091/2402] drivers: clock_control: clock_control_mcux_syscon: allow FlexSPI reclock Enable support for setting and querying the FlexSPI clock rate to the clock_control_mcux_syscon driver, as this is required by the flash_flexspi_nor_driver Signed-off-by: Daniel DeGrasse --- .../clock_control/clock_control_mcux_syscon.c | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index 43148b40ed8..9eef978b0ed 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -249,15 +249,77 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( *rate = CLOCK_GetDmicClkFreq(); break; #endif +#if defined(CONFIG_MEMC_MCUX_FLEXSPI) + case MCUX_FLEXSPI_CLK: +#if (FSL_FEATURE_SOC_FLEXSPI_COUNT == 1) + *rate = CLOCK_GetFlexspiClkFreq(); +#else + *rate = CLOCK_GetFlexspiClkFreq(0); +#endif + break; +#if (FSL_FEATURE_SOC_FLEXSPI_COUNT == 2) + case MCUX_FLEXSPI2_CLK: + *rate = CLOCK_GetFlexspiClkFreq(1); + break; +#endif +#endif /* CONFIG_MEMC_MCUX_FLEXSPI */ } return 0; } +#if defined(CONFIG_MEMC) +/* + * Weak implemenetation of flexspi_clock_set_freq- SOC implementations are + * expected to override this + */ +__weak int flexspi_clock_set_freq(uint32_t clock_name, uint32_t freq) +{ + ARG_UNUSED(clock_name); + ARG_UNUSED(freq); + return -ENOTSUP; +} +#endif + +/* + * Since this function is used to reclock the FlexSPI when running in + * XIP, it must be located in RAM when MEMC driver is enabled. + */ +#ifdef CONFIG_MEMC +#define SYSCON_SET_FUNC_ATTR __ramfunc +#else +#define SYSCON_SET_FUNC_ATTR +#endif + +static int SYSCON_SET_FUNC_ATTR + mcux_lpc_syscon_clock_control_set_subsys_rate(const struct device *dev, + clock_control_subsys_t subsys, + clock_control_subsys_rate_t rate) +{ + uint32_t clock_name = (uintptr_t)subsys; + uint32_t clock_rate = (uintptr_t)rate; + + switch (clock_name) { + case MCUX_FLEXSPI_CLK: +#if defined(CONFIG_MEMC) + /* The SOC is using the FlexSPI for XIP. Therefore, + * the FlexSPI itself must be managed within the function, + * which is SOC specific. + */ + return flexspi_clock_set_freq(clock_name, clock_rate); +#endif + default: + /* Silence unused variable warning */ + ARG_UNUSED(clock_rate); + return -ENOTSUP; + } +} + static const struct clock_control_driver_api mcux_lpc_syscon_api = { .on = mcux_lpc_syscon_clock_control_on, .off = mcux_lpc_syscon_clock_control_off, .get_rate = mcux_lpc_syscon_clock_control_get_subsys_rate, + .set_rate = mcux_lpc_syscon_clock_control_set_subsys_rate, }; #define LPC_CLOCK_INIT(n) \ From 414b3b7efd3e927a7e68813217285b30a160d4b2 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 15:32:54 -0500 Subject: [PATCH 1092/2402] boards: nxp: rd_rw612_bga: enable support for flash Enable support for the mx25u51245g flash chip present on the RD RW612 BGA. Support has been verified with the following samples: - samples/drivers/flash_shell - tests/drivers/flash/common Signed-off-by: Daniel DeGrasse --- boards/nxp/rd_rw612_bga/doc/index.rst | 2 ++ .../nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi | 18 ++++++++++++++++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 10 +++++++++- 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index c78764f5852..7f32a8c6fb5 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -45,6 +45,8 @@ Supported Features +-----------+------------+-----------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-----------------------------------+ +| FLEXSPI | on-chip | flash | ++-----------+------------+-----------------------------------+ | TRNG | on-chip | entropy | +-----------+------------+-----------------------------------+ | WWDT | on-chip | watchdog | diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi index 9b2a44a7c76..d55a83fff70 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi @@ -31,4 +31,22 @@ bias-pull-up; }; }; + + pinmux_flexspi: pinmux_flexspi { + group0 { + pinmux = ; + slew-rate = "ultra"; + }; + + group1 { + pinmux = ; + slew-rate = "ultra"; + bias-pull-down; + }; + }; }; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index 1a1143a47bb..3b008e8d32b 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -77,6 +77,14 @@ arduino_i2c: &flexcomm2 { }; &flexspi { + status = "okay"; + ahb-bufferable; + ahb-prefetch; + ahb-cacheable; + ahb-read-addr-opt; + rx-clock-source = <1>; + pinctrl-0 = <&pinmux_flexspi>; + pinctrl-names = "default"; status = "okay"; mx25u51245g: mx25u51245g@0 { compatible = "nxp,imx-flexspi-nor"; @@ -84,7 +92,7 @@ arduino_i2c: &flexcomm2 { reg = <0>; /* MX25UM51245G is 64MB, 512MBit flash part */ size = ; - status = "disabled"; + status = "okay"; jedec-id = [c2 25 3a]; erase-block-size = <4096>; write-block-size = <1>; From c74d60dba0096ab75e7dde574d3e2d856c322820 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Wed, 20 Mar 2024 21:23:13 +0100 Subject: [PATCH 1093/2402] Revert "manifest: optional: Update nanopb" Upstream repo has made changes to the cmake module, which breaks native_sim builds. This reverts commit d737e5d8e3606b1e1879e03535cf7dcf34b83317. Signed-off-by: Pieter De Gendt --- submanifests/optional.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/submanifests/optional.yaml b/submanifests/optional.yaml index f0ae16d5d0d..39faa5f3887 100644 --- a/submanifests/optional.yaml +++ b/submanifests/optional.yaml @@ -22,7 +22,7 @@ manifest: groups: - optional - name: nanopb - revision: 671672b4d7994a9b07a307ae654885c7202ae886 + revision: 65cbefb4695bc7af1cb733ced99618afb3586b20 path: modules/lib/nanopb remote: upstream groups: From 5ebce33c42b4dfbe1b1a91d60c1c4c4fcaaaee1e Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Wed, 20 Mar 2024 14:21:48 +0200 Subject: [PATCH 1094/2402] MAINTAINERS: Update paths for NXP Platforms (MPU) Files around dts/arm64/nxp should belong to NXP Platforms (MPU) group. Signed-off-by: Daniel Baluta --- MAINTAINERS.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index fddbfb902d5..3072c088da1 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3383,6 +3383,7 @@ NXP Platforms (MPU): - decsny - yvanderv files: + - dts/arm64/nxp/ - soc/nxp/imx/ - soc/nxp/layerscape/ files-regex: From 94351ce2ad4d1a9d05e691effeda237d432e547b Mon Sep 17 00:00:00 2001 From: Johan Carlsson Date: Wed, 20 Mar 2024 14:27:26 +0100 Subject: [PATCH 1095/2402] drivers: uart_mcux_flexcomm: fix invalid use of status bits. uart flexcomm driver incorrectly used kStatus enum as mask when checking for errors and enabling the error interrupts. Signed-off-by: Johan Carlsson --- drivers/serial/uart_mcux_flexcomm.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/serial/uart_mcux_flexcomm.c b/drivers/serial/uart_mcux_flexcomm.c index a15ba82873a..f180c18c952 100644 --- a/drivers/serial/uart_mcux_flexcomm.c +++ b/drivers/serial/uart_mcux_flexcomm.c @@ -120,22 +120,22 @@ static int mcux_flexcomm_err_check(const struct device *dev) uint32_t flags = USART_GetStatusFlags(config->base); int err = 0; - if (flags & kStatus_USART_RxRingBufferOverrun) { + if (flags & kUSART_RxError) { err |= UART_ERROR_OVERRUN; } - if (flags & kStatus_USART_ParityError) { + if (flags & kUSART_ParityErrorFlag) { err |= UART_ERROR_PARITY; } - if (flags & kStatus_USART_FramingError) { + if (flags & kUSART_FramingErrorFlag) { err |= UART_ERROR_FRAMING; } USART_ClearStatusFlags(config->base, - kStatus_USART_RxRingBufferOverrun | - kStatus_USART_ParityError | - kStatus_USART_FramingError); + kUSART_RxError | + kUSART_ParityErrorFlag | + kUSART_FramingErrorFlag); return err; } @@ -243,9 +243,9 @@ static int mcux_flexcomm_irq_rx_pending(const struct device *dev) static void mcux_flexcomm_irq_err_enable(const struct device *dev) { const struct mcux_flexcomm_config *config = dev->config; - uint32_t mask = kStatus_USART_NoiseError | - kStatus_USART_FramingError | - kStatus_USART_ParityError; + uint32_t mask = kUSART_NoiseErrorInterruptEnable | + kUSART_FramingErrorInterruptEnable | + kUSART_ParityErrorInterruptEnable; USART_EnableInterrupts(config->base, mask); } @@ -253,9 +253,9 @@ static void mcux_flexcomm_irq_err_enable(const struct device *dev) static void mcux_flexcomm_irq_err_disable(const struct device *dev) { const struct mcux_flexcomm_config *config = dev->config; - uint32_t mask = kStatus_USART_NoiseError | - kStatus_USART_FramingError | - kStatus_USART_ParityError; + uint32_t mask = kUSART_NoiseErrorInterruptEnable | + kUSART_FramingErrorInterruptEnable | + kUSART_ParityErrorInterruptEnable; USART_DisableInterrupts(config->base, mask); } From 7d99de6dfa814b3dcc12f0e84eb86cecd68a9509 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Sat, 9 Mar 2024 21:50:36 +0900 Subject: [PATCH 1096/2402] drivers: led_strip: ws2812: Remove WS2812_STRIP and WS2812_STRIP_DRIVER Removing `choice WS2812_STRIP_DRIVER` to enable the use of multiple types of WS2812 drivers. Also, `menuconfig WS2812_STRIP` will be deleted as it does not correspond to the appropriate settings. Signed-off-by: TOKITA Hiroshi --- .../adafruit_neopixel_grid_bff_display.conf | 1 - drivers/led_strip/Kconfig.apa102 | 2 +- drivers/led_strip/Kconfig.lpd880x | 3 ++- drivers/led_strip/Kconfig.ws2812 | 17 ++--------------- samples/drivers/led_apa102/prj.conf | 1 - samples/drivers/led_lpd8806/prj.conf | 2 -- samples/drivers/led_ws2812/Kconfig | 5 ----- .../boards/actinius_icarus_som_dk_nrf9160.conf | 1 + .../actinius_icarus_som_dk_nrf9160_ns.conf | 1 + .../drivers/led_ws2812/boards/bbc_microbit.conf | 1 - .../led_ws2812/boards/esp32c3_devkitm.conf | 1 - .../led_ws2812/boards/esp32s2_saola.conf | 1 - .../boards/esp32s3_devkitm_esp32s3_procpu.conf | 1 - samples/drivers/led_ws2812/boards/legend.conf | 1 + .../m5stack_atoms3_lite_esp32s3_procpu.conf | 1 + .../boards/m5stack_stamps3_esp32s3_procpu.conf | 1 + .../led_ws2812/boards/mimxrt1050_evk.conf | 1 - .../led_ws2812/boards/mimxrt1050_evk_qspi.conf | 1 - .../led_ws2812/boards/nrf51dk_nrf51822.conf | 1 - .../led_ws2812/boards/nrf52dk_nrf52832.conf | 2 -- .../boards/nrf5340dk_nrf5340_cpuapp.conf | 4 ---- .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 4 ++-- .../led_ws2812/boards/nucleo_f070rb.conf | 1 - .../led_ws2812/boards/nucleo_g071rb.conf | 1 + .../led_ws2812/boards/nucleo_h743zi.conf | 1 - .../led_ws2812/boards/nucleo_l476rg.conf | 1 - .../led_ws2812/boards/thingy52_nrf52832.conf | 4 ---- .../led_ws2812/boards/thingy52_nrf52832.overlay | 4 ++-- .../boards/yd_esp32_esp32_procpu.conf | 1 + samples/drivers/led_ws2812/prj.conf | 1 - 30 files changed, 16 insertions(+), 51 deletions(-) create mode 100644 samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160.conf create mode 100644 samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160_ns.conf create mode 100644 samples/drivers/led_ws2812/boards/legend.conf create mode 100644 samples/drivers/led_ws2812/boards/m5stack_atoms3_lite_esp32s3_procpu.conf create mode 100644 samples/drivers/led_ws2812/boards/m5stack_stamps3_esp32s3_procpu.conf create mode 100644 samples/drivers/led_ws2812/boards/nucleo_g071rb.conf create mode 100644 samples/drivers/led_ws2812/boards/yd_esp32_esp32_procpu.conf diff --git a/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.conf b/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.conf index 889bdb81881..a3fd88e552b 100644 --- a/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.conf +++ b/boards/shields/adafruit_neopixel_grid_bff/adafruit_neopixel_grid_bff_display.conf @@ -1,2 +1 @@ CONFIG_LED_STRIP=y -CONFIG_WS2812_STRIP=y diff --git a/drivers/led_strip/Kconfig.apa102 b/drivers/led_strip/Kconfig.apa102 index 113d75005e6..17e76021b33 100644 --- a/drivers/led_strip/Kconfig.apa102 +++ b/drivers/led_strip/Kconfig.apa102 @@ -6,7 +6,7 @@ config APA102_STRIP bool "APA102 SPI LED strip driver" - depends on SPI + select SPI if $(dt_compat_on_bus,$(DT_COMPAT_APA_APA102),spi) select LED_STRIP_RGB_SCRATCH help Enable the LED strip driver for a chain of APA102 RGB LEDs. diff --git a/drivers/led_strip/Kconfig.lpd880x b/drivers/led_strip/Kconfig.lpd880x index dfcc4a88f24..db066194436 100644 --- a/drivers/led_strip/Kconfig.lpd880x +++ b/drivers/led_strip/Kconfig.lpd880x @@ -3,7 +3,8 @@ config LPD880X_STRIP bool "LPD880x SPI LED strip driver" - depends on SPI + select SPI if $(dt_compat_on_bus,$(DT_COMPAT_GREELED_LPD8803),spi) \ + || $(dt_compat_on_bus,$(DT_COMPAT_GREELED_LPD8806),spi) help Enable LED strip driver for daisy chains of LPD880x (LPD8803, LPD8806, or compatible) devices. diff --git a/drivers/led_strip/Kconfig.ws2812 b/drivers/led_strip/Kconfig.ws2812 index 469b6d3f915..791923f135d 100644 --- a/drivers/led_strip/Kconfig.ws2812 +++ b/drivers/led_strip/Kconfig.ws2812 @@ -7,27 +7,16 @@ # # https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/ -menuconfig WS2812_STRIP - bool "WS2812 (and compatible) LED strip driver" - help - Enable LED strip driver for daisy chains of WS2812-ish (or WS2812B, - WS2813, SK6812, Everlight B1414, or compatible) devices. - -choice WS2812_STRIP_DRIVER - prompt "Driver backend" - default WS2812_STRIP_SPI - depends on WS2812_STRIP - config WS2812_STRIP_SPI bool "SPI driver" - depends on SPI + select SPI if $(dt_compat_on_bus,$(DT_COMPAT_WORLDSEMI_WS2812_SPI),spi) help The SPI driver is portable, but requires significantly more memory (1 byte of overhead per bit of pixel data). config WS2812_STRIP_I2S bool "I2S driver" - depends on I2S + select I2S if $(dt_compat_on_bus,$(DT_COMPAT_WORLDSEMI_WS2812_I2S),i2s) help Uses the I2S peripheral, memory usage is 4 bytes per color, times the number of pixels. A few more for the start and end @@ -52,5 +41,3 @@ config WS2812_STRIP_RPI_PICO_PIO select PICOSDK_USE_PIO help Use the PIO feature available on RaspberryPi Pico devices. - -endchoice diff --git a/samples/drivers/led_apa102/prj.conf b/samples/drivers/led_apa102/prj.conf index ee66750c17f..bf12bcb81dc 100644 --- a/samples/drivers/led_apa102/prj.conf +++ b/samples/drivers/led_apa102/prj.conf @@ -2,6 +2,5 @@ CONFIG_LOG=y CONFIG_LED_STRIP=y -CONFIG_SPI=y CONFIG_APA102_STRIP=y CONFIG_POLL=y diff --git a/samples/drivers/led_lpd8806/prj.conf b/samples/drivers/led_lpd8806/prj.conf index 08909b52d20..38a88bf206f 100644 --- a/samples/drivers/led_lpd8806/prj.conf +++ b/samples/drivers/led_lpd8806/prj.conf @@ -4,7 +4,5 @@ CONFIG_LOG=y CONFIG_BOOT_BANNER=y CONFIG_POLL=y -CONFIG_SPI=y - CONFIG_LED_STRIP=y CONFIG_LPD880X_STRIP=y diff --git a/samples/drivers/led_ws2812/Kconfig b/samples/drivers/led_ws2812/Kconfig index 2b60e294b7a..fdf12abde24 100644 --- a/samples/drivers/led_ws2812/Kconfig +++ b/samples/drivers/led_ws2812/Kconfig @@ -1,11 +1,6 @@ # Copyright (c) 2019 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -# Use the SPI driver by default, unless the GPIO driver is -# specifically configured in. -config SPI - default y - menu "WS2812 Sample Configuration" config SAMPLE_LED_UPDATE_DELAY diff --git a/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160.conf b/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160.conf new file mode 100644 index 00000000000..0c82ac5d228 --- /dev/null +++ b/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160.conf @@ -0,0 +1 @@ +CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160_ns.conf b/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160_ns.conf new file mode 100644 index 00000000000..0c82ac5d228 --- /dev/null +++ b/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160_ns.conf @@ -0,0 +1 @@ +CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/bbc_microbit.conf b/samples/drivers/led_ws2812/boards/bbc_microbit.conf index 3f0afed7d43..0f98dd85562 100644 --- a/samples/drivers/led_ws2812/boards/bbc_microbit.conf +++ b/samples/drivers/led_ws2812/boards/bbc_microbit.conf @@ -1,2 +1 @@ -CONFIG_SPI=n CONFIG_WS2812_STRIP_GPIO=y diff --git a/samples/drivers/led_ws2812/boards/esp32c3_devkitm.conf b/samples/drivers/led_ws2812/boards/esp32c3_devkitm.conf index 319a42ce981..0c82ac5d228 100644 --- a/samples/drivers/led_ws2812/boards/esp32c3_devkitm.conf +++ b/samples/drivers/led_ws2812/boards/esp32c3_devkitm.conf @@ -1,2 +1 @@ CONFIG_WS2812_STRIP_SPI=y -CONFIG_SPI=y diff --git a/samples/drivers/led_ws2812/boards/esp32s2_saola.conf b/samples/drivers/led_ws2812/boards/esp32s2_saola.conf index 319a42ce981..0c82ac5d228 100644 --- a/samples/drivers/led_ws2812/boards/esp32s2_saola.conf +++ b/samples/drivers/led_ws2812/boards/esp32s2_saola.conf @@ -1,2 +1 @@ CONFIG_WS2812_STRIP_SPI=y -CONFIG_SPI=y diff --git a/samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.conf b/samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.conf index 319a42ce981..0c82ac5d228 100644 --- a/samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.conf +++ b/samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.conf @@ -1,2 +1 @@ CONFIG_WS2812_STRIP_SPI=y -CONFIG_SPI=y diff --git a/samples/drivers/led_ws2812/boards/legend.conf b/samples/drivers/led_ws2812/boards/legend.conf new file mode 100644 index 00000000000..0c82ac5d228 --- /dev/null +++ b/samples/drivers/led_ws2812/boards/legend.conf @@ -0,0 +1 @@ +CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/m5stack_atoms3_lite_esp32s3_procpu.conf b/samples/drivers/led_ws2812/boards/m5stack_atoms3_lite_esp32s3_procpu.conf new file mode 100644 index 00000000000..0c82ac5d228 --- /dev/null +++ b/samples/drivers/led_ws2812/boards/m5stack_atoms3_lite_esp32s3_procpu.conf @@ -0,0 +1 @@ +CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/m5stack_stamps3_esp32s3_procpu.conf b/samples/drivers/led_ws2812/boards/m5stack_stamps3_esp32s3_procpu.conf new file mode 100644 index 00000000000..0c82ac5d228 --- /dev/null +++ b/samples/drivers/led_ws2812/boards/m5stack_stamps3_esp32s3_procpu.conf @@ -0,0 +1 @@ +CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/mimxrt1050_evk.conf b/samples/drivers/led_ws2812/boards/mimxrt1050_evk.conf index 319a42ce981..0c82ac5d228 100644 --- a/samples/drivers/led_ws2812/boards/mimxrt1050_evk.conf +++ b/samples/drivers/led_ws2812/boards/mimxrt1050_evk.conf @@ -1,2 +1 @@ CONFIG_WS2812_STRIP_SPI=y -CONFIG_SPI=y diff --git a/samples/drivers/led_ws2812/boards/mimxrt1050_evk_qspi.conf b/samples/drivers/led_ws2812/boards/mimxrt1050_evk_qspi.conf index 319a42ce981..0c82ac5d228 100644 --- a/samples/drivers/led_ws2812/boards/mimxrt1050_evk_qspi.conf +++ b/samples/drivers/led_ws2812/boards/mimxrt1050_evk_qspi.conf @@ -1,2 +1 @@ CONFIG_WS2812_STRIP_SPI=y -CONFIG_SPI=y diff --git a/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf b/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf index 3f0afed7d43..0f98dd85562 100644 --- a/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf +++ b/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf @@ -1,2 +1 @@ -CONFIG_SPI=n CONFIG_WS2812_STRIP_GPIO=y diff --git a/samples/drivers/led_ws2812/boards/nrf52dk_nrf52832.conf b/samples/drivers/led_ws2812/boards/nrf52dk_nrf52832.conf index 6594d1bbb25..b20eefa4dea 100644 --- a/samples/drivers/led_ws2812/boards/nrf52dk_nrf52832.conf +++ b/samples/drivers/led_ws2812/boards/nrf52dk_nrf52832.conf @@ -1,5 +1,3 @@ -CONFIG_SPI=y - # This driver only uses spi_write() with the SPIM instance it allocates, # so PAN 58 doesn't matter, because the RX length is always 0. CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58=y diff --git a/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.conf index f5d64aaf5da..d43d48dc8c1 100644 --- a/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.conf +++ b/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.conf @@ -1,5 +1 @@ -CONFIG_SPI=n - -CONFIG_I2S=y -CONFIG_WS2812_STRIP=y CONFIG_WS2812_STRIP_I2S=y diff --git a/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.overlay index 738e7911532..b5d6772e2e1 100644 --- a/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -16,9 +16,7 @@ i2s_led: &i2s0 { status = "okay"; pinctrl-0 = <&i2s0_default_alt>; pinctrl-names = "default"; -}; -/ { led_strip: ws2812 { compatible = "worldsemi,ws2812-i2s"; @@ -29,7 +27,9 @@ i2s_led: &i2s0 { LED_COLOR_ID_BLUE>; reset-delay = <500>; }; +}; +/ { aliases { led-strip = &led_strip; }; diff --git a/samples/drivers/led_ws2812/boards/nucleo_f070rb.conf b/samples/drivers/led_ws2812/boards/nucleo_f070rb.conf index 36185d53ec6..e6c76d8ab9b 100644 --- a/samples/drivers/led_ws2812/boards/nucleo_f070rb.conf +++ b/samples/drivers/led_ws2812/boards/nucleo_f070rb.conf @@ -1,2 +1 @@ -CONFIG_SPI=y CONFIG_SPI_STM32_DMA=y diff --git a/samples/drivers/led_ws2812/boards/nucleo_g071rb.conf b/samples/drivers/led_ws2812/boards/nucleo_g071rb.conf new file mode 100644 index 00000000000..0c82ac5d228 --- /dev/null +++ b/samples/drivers/led_ws2812/boards/nucleo_g071rb.conf @@ -0,0 +1 @@ +CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/nucleo_h743zi.conf b/samples/drivers/led_ws2812/boards/nucleo_h743zi.conf index 319a42ce981..0c82ac5d228 100644 --- a/samples/drivers/led_ws2812/boards/nucleo_h743zi.conf +++ b/samples/drivers/led_ws2812/boards/nucleo_h743zi.conf @@ -1,2 +1 @@ CONFIG_WS2812_STRIP_SPI=y -CONFIG_SPI=y diff --git a/samples/drivers/led_ws2812/boards/nucleo_l476rg.conf b/samples/drivers/led_ws2812/boards/nucleo_l476rg.conf index 319a42ce981..0c82ac5d228 100644 --- a/samples/drivers/led_ws2812/boards/nucleo_l476rg.conf +++ b/samples/drivers/led_ws2812/boards/nucleo_l476rg.conf @@ -1,2 +1 @@ CONFIG_WS2812_STRIP_SPI=y -CONFIG_SPI=y diff --git a/samples/drivers/led_ws2812/boards/thingy52_nrf52832.conf b/samples/drivers/led_ws2812/boards/thingy52_nrf52832.conf index f5d64aaf5da..d43d48dc8c1 100644 --- a/samples/drivers/led_ws2812/boards/thingy52_nrf52832.conf +++ b/samples/drivers/led_ws2812/boards/thingy52_nrf52832.conf @@ -1,5 +1 @@ -CONFIG_SPI=n - -CONFIG_I2S=y -CONFIG_WS2812_STRIP=y CONFIG_WS2812_STRIP_I2S=y diff --git a/samples/drivers/led_ws2812/boards/thingy52_nrf52832.overlay b/samples/drivers/led_ws2812/boards/thingy52_nrf52832.overlay index c7696bd764f..2be7408069d 100644 --- a/samples/drivers/led_ws2812/boards/thingy52_nrf52832.overlay +++ b/samples/drivers/led_ws2812/boards/thingy52_nrf52832.overlay @@ -21,9 +21,7 @@ i2s_led: &i2s0 { status = "okay"; pinctrl-0 = <&i2s0_default_alt>; pinctrl-names = "default"; -}; -/ { led_strip: ws2812 { compatible = "worldsemi,ws2812-i2s"; @@ -35,7 +33,9 @@ i2s_led: &i2s0 { out-active-low; reset-delay = <120>; }; +}; +/ { aliases { led-strip = &led_strip; }; diff --git a/samples/drivers/led_ws2812/boards/yd_esp32_esp32_procpu.conf b/samples/drivers/led_ws2812/boards/yd_esp32_esp32_procpu.conf new file mode 100644 index 00000000000..0c82ac5d228 --- /dev/null +++ b/samples/drivers/led_ws2812/boards/yd_esp32_esp32_procpu.conf @@ -0,0 +1 @@ +CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/prj.conf b/samples/drivers/led_ws2812/prj.conf index 4319cb1f793..ae59400fd6c 100644 --- a/samples/drivers/led_ws2812/prj.conf +++ b/samples/drivers/led_ws2812/prj.conf @@ -1,4 +1,3 @@ CONFIG_LOG=y CONFIG_LED_STRIP=y CONFIG_LED_STRIP_LOG_LEVEL_DBG=y -CONFIG_WS2812_STRIP=y From 7b61d1c43c15c15c01c8f299883d05f85a7091f4 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Tue, 12 Mar 2024 09:37:33 +0900 Subject: [PATCH 1097/2402] drivers: led_strip: Enabling config with DT_HAS_.. Applying the modern way which is adding `default y` and `depends on DT_HAS_...` to enable configs. Signed-off-by: TOKITA Hiroshi --- drivers/led_strip/Kconfig.apa102 | 2 ++ drivers/led_strip/Kconfig.lpd880x | 2 ++ drivers/led_strip/Kconfig.ws2812 | 21 ++++++++++++++----- samples/drivers/led_apa102/prj.conf | 1 - samples/drivers/led_lpd8806/prj.conf | 1 - .../actinius_icarus_som_dk_nrf9160.conf | 1 - .../actinius_icarus_som_dk_nrf9160_ns.conf | 1 - .../led_ws2812/boards/adafruit_kb2040.conf | 1 - .../boards/adafruit_qt_py_rp2040.conf | 1 - .../led_ws2812/boards/bbc_microbit.conf | 1 - .../led_ws2812/boards/esp32c3_devkitm.conf | 1 - .../led_ws2812/boards/esp32s2_saola.conf | 1 - .../esp32s3_devkitm_esp32s3_procpu.conf | 1 - samples/drivers/led_ws2812/boards/legend.conf | 1 - .../m5stack_atoms3_lite_esp32s3_procpu.conf | 1 - .../m5stack_stamps3_esp32s3_procpu.conf | 1 - .../led_ws2812/boards/mimxrt1050_evk.conf | 1 - .../boards/mimxrt1050_evk_qspi.conf | 1 - .../led_ws2812/boards/nrf51dk_nrf51822.conf | 1 - .../boards/nrf5340dk_nrf5340_cpuapp.conf | 1 - .../led_ws2812/boards/nucleo_g071rb.conf | 1 - .../led_ws2812/boards/nucleo_h743zi.conf | 1 - .../led_ws2812/boards/nucleo_l476rg.conf | 1 - .../led_ws2812/boards/thingy52_nrf52832.conf | 1 - .../boards/yd_esp32_esp32_procpu.conf | 1 - 25 files changed, 20 insertions(+), 27 deletions(-) delete mode 100644 samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160.conf delete mode 100644 samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160_ns.conf delete mode 100644 samples/drivers/led_ws2812/boards/adafruit_kb2040.conf delete mode 100644 samples/drivers/led_ws2812/boards/bbc_microbit.conf delete mode 100644 samples/drivers/led_ws2812/boards/esp32c3_devkitm.conf delete mode 100644 samples/drivers/led_ws2812/boards/esp32s2_saola.conf delete mode 100644 samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.conf delete mode 100644 samples/drivers/led_ws2812/boards/legend.conf delete mode 100644 samples/drivers/led_ws2812/boards/m5stack_atoms3_lite_esp32s3_procpu.conf delete mode 100644 samples/drivers/led_ws2812/boards/m5stack_stamps3_esp32s3_procpu.conf delete mode 100644 samples/drivers/led_ws2812/boards/mimxrt1050_evk.conf delete mode 100644 samples/drivers/led_ws2812/boards/mimxrt1050_evk_qspi.conf delete mode 100644 samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf delete mode 100644 samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.conf delete mode 100644 samples/drivers/led_ws2812/boards/nucleo_g071rb.conf delete mode 100644 samples/drivers/led_ws2812/boards/nucleo_h743zi.conf delete mode 100644 samples/drivers/led_ws2812/boards/nucleo_l476rg.conf delete mode 100644 samples/drivers/led_ws2812/boards/thingy52_nrf52832.conf delete mode 100644 samples/drivers/led_ws2812/boards/yd_esp32_esp32_procpu.conf diff --git a/drivers/led_strip/Kconfig.apa102 b/drivers/led_strip/Kconfig.apa102 index 17e76021b33..27ac4b23391 100644 --- a/drivers/led_strip/Kconfig.apa102 +++ b/drivers/led_strip/Kconfig.apa102 @@ -6,6 +6,8 @@ config APA102_STRIP bool "APA102 SPI LED strip driver" + default y + depends on DT_HAS_APA_APA102_ENABLED select SPI if $(dt_compat_on_bus,$(DT_COMPAT_APA_APA102),spi) select LED_STRIP_RGB_SCRATCH help diff --git a/drivers/led_strip/Kconfig.lpd880x b/drivers/led_strip/Kconfig.lpd880x index db066194436..eaf79924361 100644 --- a/drivers/led_strip/Kconfig.lpd880x +++ b/drivers/led_strip/Kconfig.lpd880x @@ -3,6 +3,8 @@ config LPD880X_STRIP bool "LPD880x SPI LED strip driver" + default y + depends on DT_HAS_GREELED_LPD8803_ENABLED || DT_HAS_GREELED_LPD8806_ENABLED select SPI if $(dt_compat_on_bus,$(DT_COMPAT_GREELED_LPD8803),spi) \ || $(dt_compat_on_bus,$(DT_COMPAT_GREELED_LPD8806),spi) help diff --git a/drivers/led_strip/Kconfig.ws2812 b/drivers/led_strip/Kconfig.ws2812 index 791923f135d..5040515e8bc 100644 --- a/drivers/led_strip/Kconfig.ws2812 +++ b/drivers/led_strip/Kconfig.ws2812 @@ -8,27 +8,36 @@ # https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/ config WS2812_STRIP_SPI - bool "SPI driver" + bool "WS2812 LED strip SPI driver" + default y + depends on DT_HAS_WORLDSEMI_WS2812_SPI_ENABLED select SPI if $(dt_compat_on_bus,$(DT_COMPAT_WORLDSEMI_WS2812_SPI),spi) help + Enable driver for WS2812 (and compatibles) LED strip using SPI. The SPI driver is portable, but requires significantly more memory (1 byte of overhead per bit of pixel data). config WS2812_STRIP_I2S - bool "I2S driver" + bool "WS2812 LED strip I2S driver" + default y + depends on DT_HAS_WORLDSEMI_WS2812_I2S_ENABLED select I2S if $(dt_compat_on_bus,$(DT_COMPAT_WORLDSEMI_WS2812_I2S),i2s) help + Enable driver for WS2812 (and compatibles) LED strip using I2S. Uses the I2S peripheral, memory usage is 4 bytes per color, times the number of pixels. A few more for the start and end delay. The reset delay has a coarse resolution of ~20us. config WS2812_STRIP_GPIO - bool "GPIO driver" + bool "WS2812 LED strip GPIO driver" # Only an Cortex-M0 inline assembly implementation for the nRF51 # is supported currently. + default y + depends on DT_HAS_WORLDSEMI_WS2812_GPIO_ENABLED depends on SOC_SERIES_NRF51X select LED_STRIP_RGB_SCRATCH help + Enable driver for WS2812 (and compatibles) LED strip directly controlling with GPIO. The GPIO driver does bit-banging with inline assembly, and is not available on all SoCs. @@ -36,8 +45,10 @@ config WS2812_STRIP_GPIO controller. config WS2812_STRIP_RPI_PICO_PIO - bool "Raspberry Pi Pico PIO" + bool "WS2812 LED strip Raspberry Pi Pico PIO driver" + default y depends on DT_HAS_WORLDSEMI_WS2812_RPI_PICO_PIO_ENABLED select PICOSDK_USE_PIO help - Use the PIO feature available on RaspberryPi Pico devices. + Enable driver for WS2812 (and compatibles) LED strip using + the RaspberryPi Pico's PIO. diff --git a/samples/drivers/led_apa102/prj.conf b/samples/drivers/led_apa102/prj.conf index bf12bcb81dc..70d3f24081d 100644 --- a/samples/drivers/led_apa102/prj.conf +++ b/samples/drivers/led_apa102/prj.conf @@ -2,5 +2,4 @@ CONFIG_LOG=y CONFIG_LED_STRIP=y -CONFIG_APA102_STRIP=y CONFIG_POLL=y diff --git a/samples/drivers/led_lpd8806/prj.conf b/samples/drivers/led_lpd8806/prj.conf index 38a88bf206f..704a6a00049 100644 --- a/samples/drivers/led_lpd8806/prj.conf +++ b/samples/drivers/led_lpd8806/prj.conf @@ -5,4 +5,3 @@ CONFIG_BOOT_BANNER=y CONFIG_POLL=y CONFIG_LED_STRIP=y -CONFIG_LPD880X_STRIP=y diff --git a/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160.conf b/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160_ns.conf b/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160_ns.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/actinius_icarus_som_dk_nrf9160_ns.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/adafruit_kb2040.conf b/samples/drivers/led_ws2812/boards/adafruit_kb2040.conf deleted file mode 100644 index 9ccb06fb7bc..00000000000 --- a/samples/drivers/led_ws2812/boards/adafruit_kb2040.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_RPI_PICO_PIO=y diff --git a/samples/drivers/led_ws2812/boards/adafruit_qt_py_rp2040.conf b/samples/drivers/led_ws2812/boards/adafruit_qt_py_rp2040.conf index 6805516207c..8230eb9896b 100644 --- a/samples/drivers/led_ws2812/boards/adafruit_qt_py_rp2040.conf +++ b/samples/drivers/led_ws2812/boards/adafruit_qt_py_rp2040.conf @@ -1,3 +1,2 @@ -CONFIG_WS2812_STRIP_RPI_PICO_PIO=y CONFIG_GPIO=y CONFIG_GPIO_HOGS=y diff --git a/samples/drivers/led_ws2812/boards/bbc_microbit.conf b/samples/drivers/led_ws2812/boards/bbc_microbit.conf deleted file mode 100644 index 0f98dd85562..00000000000 --- a/samples/drivers/led_ws2812/boards/bbc_microbit.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_GPIO=y diff --git a/samples/drivers/led_ws2812/boards/esp32c3_devkitm.conf b/samples/drivers/led_ws2812/boards/esp32c3_devkitm.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/esp32c3_devkitm.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/esp32s2_saola.conf b/samples/drivers/led_ws2812/boards/esp32s2_saola.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/esp32s2_saola.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.conf b/samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/legend.conf b/samples/drivers/led_ws2812/boards/legend.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/legend.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/m5stack_atoms3_lite_esp32s3_procpu.conf b/samples/drivers/led_ws2812/boards/m5stack_atoms3_lite_esp32s3_procpu.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/m5stack_atoms3_lite_esp32s3_procpu.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/m5stack_stamps3_esp32s3_procpu.conf b/samples/drivers/led_ws2812/boards/m5stack_stamps3_esp32s3_procpu.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/m5stack_stamps3_esp32s3_procpu.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/mimxrt1050_evk.conf b/samples/drivers/led_ws2812/boards/mimxrt1050_evk.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/mimxrt1050_evk.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/mimxrt1050_evk_qspi.conf b/samples/drivers/led_ws2812/boards/mimxrt1050_evk_qspi.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/mimxrt1050_evk_qspi.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf b/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf deleted file mode 100644 index 0f98dd85562..00000000000 --- a/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_GPIO=y diff --git a/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.conf deleted file mode 100644 index d43d48dc8c1..00000000000 --- a/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_I2S=y diff --git a/samples/drivers/led_ws2812/boards/nucleo_g071rb.conf b/samples/drivers/led_ws2812/boards/nucleo_g071rb.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/nucleo_g071rb.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/nucleo_h743zi.conf b/samples/drivers/led_ws2812/boards/nucleo_h743zi.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/nucleo_h743zi.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/nucleo_l476rg.conf b/samples/drivers/led_ws2812/boards/nucleo_l476rg.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/nucleo_l476rg.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y diff --git a/samples/drivers/led_ws2812/boards/thingy52_nrf52832.conf b/samples/drivers/led_ws2812/boards/thingy52_nrf52832.conf deleted file mode 100644 index d43d48dc8c1..00000000000 --- a/samples/drivers/led_ws2812/boards/thingy52_nrf52832.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_I2S=y diff --git a/samples/drivers/led_ws2812/boards/yd_esp32_esp32_procpu.conf b/samples/drivers/led_ws2812/boards/yd_esp32_esp32_procpu.conf deleted file mode 100644 index 0c82ac5d228..00000000000 --- a/samples/drivers/led_ws2812/boards/yd_esp32_esp32_procpu.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_WS2812_STRIP_SPI=y From 0929a8db3781b74452dc82fd1ceb433d9597f5dd Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Sat, 9 Mar 2024 16:06:25 +0900 Subject: [PATCH 1098/2402] samples: drivers: Rename `led_ws2812` to `led_strip` Rename it so that it can be used as a sample of various LED strips. Signed-off-by: TOKITA Hiroshi --- .../shields/adafruit_neopixel_grid_bff/doc/index.rst | 2 +- boards/vcc-gnd/yd_esp32/doc/index.rst | 4 ++-- .../drivers/{led_ws2812 => led_strip}/CMakeLists.txt | 2 +- samples/drivers/{led_ws2812 => led_strip}/Kconfig | 0 samples/drivers/{led_ws2812 => led_strip}/README.rst | 12 ++++++------ .../boards/adafruit_qt_py_rp2040.conf | 0 .../boards/bbc_microbit.overlay | 0 .../boards/esp32c3_devkitm.overlay | 0 .../boards/esp32s2_saola.overlay | 0 .../boards/esp32s3_devkitm_esp32s3_procpu.overlay | 0 .../boards/mimxrt1050_evk.overlay | 0 .../boards/mimxrt1050_evk_qspi.overlay | 0 .../boards/nrf51dk_nrf51822.overlay | 0 .../boards/nrf52dk_nrf52832.conf | 0 .../boards/nrf52dk_nrf52832.overlay | 0 .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 0 .../boards/nucleo_f070rb.conf | 0 .../boards/nucleo_f070rb.overlay | 0 .../boards/nucleo_g071rb.overlay | 0 .../boards/nucleo_h743zi.overlay | 0 .../boards/nucleo_l476rg.overlay | 0 .../boards/thingy52_nrf52832.overlay | 0 .../{led_ws2812 => led_strip}/f070rb-bindings.h | 0 .../{led_ws2812 => led_strip}/nrf52-bindings.h | 0 samples/drivers/{led_ws2812 => led_strip}/prj.conf | 0 samples/drivers/led_strip/sample.yaml | 11 +++++++++++ samples/drivers/{led_ws2812 => led_strip}/src/main.c | 0 samples/drivers/led_ws2812/sample.yaml | 11 ----------- 28 files changed, 21 insertions(+), 21 deletions(-) rename samples/drivers/{led_ws2812 => led_strip}/CMakeLists.txt (91%) rename samples/drivers/{led_ws2812 => led_strip}/Kconfig (100%) rename samples/drivers/{led_ws2812 => led_strip}/README.rst (94%) rename samples/drivers/{led_ws2812 => led_strip}/boards/adafruit_qt_py_rp2040.conf (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/bbc_microbit.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/esp32c3_devkitm.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/esp32s2_saola.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/esp32s3_devkitm_esp32s3_procpu.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/mimxrt1050_evk.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/mimxrt1050_evk_qspi.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/nrf51dk_nrf51822.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/nrf52dk_nrf52832.conf (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/nrf52dk_nrf52832.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/nrf5340dk_nrf5340_cpuapp.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/nucleo_f070rb.conf (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/nucleo_f070rb.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/nucleo_g071rb.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/nucleo_h743zi.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/nucleo_l476rg.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/boards/thingy52_nrf52832.overlay (100%) rename samples/drivers/{led_ws2812 => led_strip}/f070rb-bindings.h (100%) rename samples/drivers/{led_ws2812 => led_strip}/nrf52-bindings.h (100%) rename samples/drivers/{led_ws2812 => led_strip}/prj.conf (100%) create mode 100644 samples/drivers/led_strip/sample.yaml rename samples/drivers/{led_ws2812 => led_strip}/src/main.c (100%) delete mode 100644 samples/drivers/led_ws2812/sample.yaml diff --git a/boards/shields/adafruit_neopixel_grid_bff/doc/index.rst b/boards/shields/adafruit_neopixel_grid_bff/doc/index.rst index f4648e9b02f..24e6762e1d6 100644 --- a/boards/shields/adafruit_neopixel_grid_bff/doc/index.rst +++ b/boards/shields/adafruit_neopixel_grid_bff/doc/index.rst @@ -39,7 +39,7 @@ LED Strip Example Set ``-DSHIELD=adafruit_neopixel_grid_bff`` when you invoke ``west build``. For example: .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_ws2812 + :zephyr-app: samples/drivers/led_strip :board: adafruit_qt_py_rp2040 :shield: adafruit_neopixel_grid_bff :goals: build diff --git a/boards/vcc-gnd/yd_esp32/doc/index.rst b/boards/vcc-gnd/yd_esp32/doc/index.rst index e69f7d07704..890c3de6855 100644 --- a/boards/vcc-gnd/yd_esp32/doc/index.rst +++ b/boards/vcc-gnd/yd_esp32/doc/index.rst @@ -233,10 +233,10 @@ RGB LED ======= The board contains an addressable RGB LED (`XL-5050RGBC-WS2812B`_), driven by GPIO16. -Here is an example of how to test it using the :zephyr:code-sample:`led-ws2812` application. +Here is an example of how to test it using the :zephyr:code-sample:`led-strip` application. .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_ws2812 + :zephyr-app: samples/drivers/led_strip :board: yd_esp32/esp32/procpu :goals: flash diff --git a/samples/drivers/led_ws2812/CMakeLists.txt b/samples/drivers/led_strip/CMakeLists.txt similarity index 91% rename from samples/drivers/led_ws2812/CMakeLists.txt rename to samples/drivers/led_strip/CMakeLists.txt index 6a2883198d3..ad3393e0c2a 100644 --- a/samples/drivers/led_ws2812/CMakeLists.txt +++ b/samples/drivers/led_strip/CMakeLists.txt @@ -3,7 +3,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(led_ws2812) +project(led_strip) FILE(GLOB app_sources src/*.c) target_sources(app PRIVATE ${app_sources}) diff --git a/samples/drivers/led_ws2812/Kconfig b/samples/drivers/led_strip/Kconfig similarity index 100% rename from samples/drivers/led_ws2812/Kconfig rename to samples/drivers/led_strip/Kconfig diff --git a/samples/drivers/led_ws2812/README.rst b/samples/drivers/led_strip/README.rst similarity index 94% rename from samples/drivers/led_ws2812/README.rst rename to samples/drivers/led_strip/README.rst index d41bad1e207..c99cf0ee383 100644 --- a/samples/drivers/led_ws2812/README.rst +++ b/samples/drivers/led_strip/README.rst @@ -1,5 +1,5 @@ -.. zephyr:code-sample:: led-ws2812 - :name: WS2812 LED strip +.. zephyr:code-sample:: led-strip + :name: LED strip sample :relevant-api: led_strip_interface Control an LED strip using a WS2812 (or compatible) driver chip. @@ -41,14 +41,14 @@ Wiring on a thingy52 The thingy52 has integrated NMOS transistors, that can be used instead of a level shifter. The I2S driver supports inverting the output to suit this scheme, using the ``out-active-low`` dts property. See the overlay file -:zephyr_file:`samples/drivers/led_ws2812/boards/thingy52_nrf52832.overlay` for more detail. +:zephyr_file:`samples/drivers/led_strip/boards/thingy52_nrf52832.overlay` for more detail. Building and Running -********************* +******************** .. _blog post on WS2812 timing: https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/ -This sample's source directory is :zephyr_file:`samples/drivers/led_ws2812/`. +This sample's source directory is :zephyr_file:`samples/drivers/led_strip/`. To make sure the sample is set up properly for building, you must: @@ -80,7 +80,7 @@ modified by changing the :kconfig:option:`CONFIG_SAMPLE_LED_UPDATE_DELAY`. Then build and flash the application: .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_ws2812 + :zephyr-app: samples/drivers/led_strip :board: :goals: flash :compact: diff --git a/samples/drivers/led_ws2812/boards/adafruit_qt_py_rp2040.conf b/samples/drivers/led_strip/boards/adafruit_qt_py_rp2040.conf similarity index 100% rename from samples/drivers/led_ws2812/boards/adafruit_qt_py_rp2040.conf rename to samples/drivers/led_strip/boards/adafruit_qt_py_rp2040.conf diff --git a/samples/drivers/led_ws2812/boards/bbc_microbit.overlay b/samples/drivers/led_strip/boards/bbc_microbit.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/bbc_microbit.overlay rename to samples/drivers/led_strip/boards/bbc_microbit.overlay diff --git a/samples/drivers/led_ws2812/boards/esp32c3_devkitm.overlay b/samples/drivers/led_strip/boards/esp32c3_devkitm.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/esp32c3_devkitm.overlay rename to samples/drivers/led_strip/boards/esp32c3_devkitm.overlay diff --git a/samples/drivers/led_ws2812/boards/esp32s2_saola.overlay b/samples/drivers/led_strip/boards/esp32s2_saola.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/esp32s2_saola.overlay rename to samples/drivers/led_strip/boards/esp32s2_saola.overlay diff --git a/samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.overlay b/samples/drivers/led_strip/boards/esp32s3_devkitm_esp32s3_procpu.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/esp32s3_devkitm_esp32s3_procpu.overlay rename to samples/drivers/led_strip/boards/esp32s3_devkitm_esp32s3_procpu.overlay diff --git a/samples/drivers/led_ws2812/boards/mimxrt1050_evk.overlay b/samples/drivers/led_strip/boards/mimxrt1050_evk.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/mimxrt1050_evk.overlay rename to samples/drivers/led_strip/boards/mimxrt1050_evk.overlay diff --git a/samples/drivers/led_ws2812/boards/mimxrt1050_evk_qspi.overlay b/samples/drivers/led_strip/boards/mimxrt1050_evk_qspi.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/mimxrt1050_evk_qspi.overlay rename to samples/drivers/led_strip/boards/mimxrt1050_evk_qspi.overlay diff --git a/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay b/samples/drivers/led_strip/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay rename to samples/drivers/led_strip/boards/nrf51dk_nrf51822.overlay diff --git a/samples/drivers/led_ws2812/boards/nrf52dk_nrf52832.conf b/samples/drivers/led_strip/boards/nrf52dk_nrf52832.conf similarity index 100% rename from samples/drivers/led_ws2812/boards/nrf52dk_nrf52832.conf rename to samples/drivers/led_strip/boards/nrf52dk_nrf52832.conf diff --git a/samples/drivers/led_ws2812/boards/nrf52dk_nrf52832.overlay b/samples/drivers/led_strip/boards/nrf52dk_nrf52832.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/nrf52dk_nrf52832.overlay rename to samples/drivers/led_strip/boards/nrf52dk_nrf52832.overlay diff --git a/samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/drivers/led_strip/boards/nrf5340dk_nrf5340_cpuapp.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/nrf5340dk_nrf5340_cpuapp.overlay rename to samples/drivers/led_strip/boards/nrf5340dk_nrf5340_cpuapp.overlay diff --git a/samples/drivers/led_ws2812/boards/nucleo_f070rb.conf b/samples/drivers/led_strip/boards/nucleo_f070rb.conf similarity index 100% rename from samples/drivers/led_ws2812/boards/nucleo_f070rb.conf rename to samples/drivers/led_strip/boards/nucleo_f070rb.conf diff --git a/samples/drivers/led_ws2812/boards/nucleo_f070rb.overlay b/samples/drivers/led_strip/boards/nucleo_f070rb.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/nucleo_f070rb.overlay rename to samples/drivers/led_strip/boards/nucleo_f070rb.overlay diff --git a/samples/drivers/led_ws2812/boards/nucleo_g071rb.overlay b/samples/drivers/led_strip/boards/nucleo_g071rb.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/nucleo_g071rb.overlay rename to samples/drivers/led_strip/boards/nucleo_g071rb.overlay diff --git a/samples/drivers/led_ws2812/boards/nucleo_h743zi.overlay b/samples/drivers/led_strip/boards/nucleo_h743zi.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/nucleo_h743zi.overlay rename to samples/drivers/led_strip/boards/nucleo_h743zi.overlay diff --git a/samples/drivers/led_ws2812/boards/nucleo_l476rg.overlay b/samples/drivers/led_strip/boards/nucleo_l476rg.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/nucleo_l476rg.overlay rename to samples/drivers/led_strip/boards/nucleo_l476rg.overlay diff --git a/samples/drivers/led_ws2812/boards/thingy52_nrf52832.overlay b/samples/drivers/led_strip/boards/thingy52_nrf52832.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/thingy52_nrf52832.overlay rename to samples/drivers/led_strip/boards/thingy52_nrf52832.overlay diff --git a/samples/drivers/led_ws2812/f070rb-bindings.h b/samples/drivers/led_strip/f070rb-bindings.h similarity index 100% rename from samples/drivers/led_ws2812/f070rb-bindings.h rename to samples/drivers/led_strip/f070rb-bindings.h diff --git a/samples/drivers/led_ws2812/nrf52-bindings.h b/samples/drivers/led_strip/nrf52-bindings.h similarity index 100% rename from samples/drivers/led_ws2812/nrf52-bindings.h rename to samples/drivers/led_strip/nrf52-bindings.h diff --git a/samples/drivers/led_ws2812/prj.conf b/samples/drivers/led_strip/prj.conf similarity index 100% rename from samples/drivers/led_ws2812/prj.conf rename to samples/drivers/led_strip/prj.conf diff --git a/samples/drivers/led_strip/sample.yaml b/samples/drivers/led_strip/sample.yaml new file mode 100644 index 00000000000..4bc7135af81 --- /dev/null +++ b/samples/drivers/led_strip/sample.yaml @@ -0,0 +1,11 @@ +sample: + description: Demonstration of the LED strip driver + name: LED strip sample +tests: + sample.drivers.led_strip: + tags: LED + filter: dt_alias_exists("led-strip") + harness_config: + fixture: fixture_led_strip + integration_platforms: + - mimxrt1050_evk diff --git a/samples/drivers/led_ws2812/src/main.c b/samples/drivers/led_strip/src/main.c similarity index 100% rename from samples/drivers/led_ws2812/src/main.c rename to samples/drivers/led_strip/src/main.c diff --git a/samples/drivers/led_ws2812/sample.yaml b/samples/drivers/led_ws2812/sample.yaml deleted file mode 100644 index 3add7297b33..00000000000 --- a/samples/drivers/led_ws2812/sample.yaml +++ /dev/null @@ -1,11 +0,0 @@ -sample: - description: Demonstration of the WS2812 LED driver - name: WS2812 sample -tests: - sample.drivers.led.ws2812: - tags: LED - filter: dt_compat_enabled("worldsemi,ws2812-spi") - harness_config: - fixture: fixture_led_ws2812 - integration_platforms: - - mimxrt1050_evk From ba9f49d7a0d148aa89dc41eb1cb07cb89806d495 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Sat, 9 Mar 2024 21:50:39 +0900 Subject: [PATCH 1099/2402] samples: drivers: led_strip: Unify `led_apa102` and `led_lpd8806` samples Unify `led_apa102` and `led_lpd8806` samples into `led_strip` and remove these. Signed-off-by: TOKITA Hiroshi --- .../itsybitsy/adafruit_itsybitsy_nrf52840.dts | 1 + boards/adafruit/itsybitsy/doc/index.rst | 2 +- .../trinket_m0/adafruit_trinket_m0.dts | 1 + .../blueclover_plt_demo_v2_nrf52832.dts | 3 +- boards/blue_clover/plt_demo_v2/doc/index.rst | 2 +- samples/drivers/led_apa102/CMakeLists.txt | 9 -- samples/drivers/led_apa102/README.rst | 90 -------------- samples/drivers/led_apa102/prj.conf | 5 - samples/drivers/led_apa102/sample.yaml | 8 -- samples/drivers/led_apa102/src/main.c | 88 ------------- samples/drivers/led_lpd8806/CMakeLists.txt | 9 -- samples/drivers/led_lpd8806/README.rst | 89 -------------- .../boards/96b_carbon_stm32f401xe.conf | 1 - samples/drivers/led_lpd8806/prj.conf | 7 -- samples/drivers/led_lpd8806/sample.yaml | 7 -- samples/drivers/led_lpd8806/src/main.c | 84 ------------- samples/drivers/led_strip/Kconfig | 8 ++ samples/drivers/led_strip/README.rst | 116 +++++++----------- .../boards/96b_carbon_stm32f401xe.conf | 3 + .../boards/96b_carbon_stm32f401xe.overlay | 8 +- .../led_strip/boards/adafruit_itsybitsy.conf | 1 + .../led_strip/boards/adafruit_trinket_m0.conf | 1 + .../blueclover_plt_demo_v2_nrf52832.conf | 1 + .../blueclover_plt_demo_v2_nrf52832.overlay | 0 .../led_strip/boards/nucleo_l432kc.conf | 1 + .../boards/nucleo_l432kc.overlay | 8 +- samples/drivers/led_strip/src/main.c | 10 +- 27 files changed, 89 insertions(+), 474 deletions(-) delete mode 100644 samples/drivers/led_apa102/CMakeLists.txt delete mode 100644 samples/drivers/led_apa102/README.rst delete mode 100644 samples/drivers/led_apa102/prj.conf delete mode 100644 samples/drivers/led_apa102/sample.yaml delete mode 100644 samples/drivers/led_apa102/src/main.c delete mode 100644 samples/drivers/led_lpd8806/CMakeLists.txt delete mode 100644 samples/drivers/led_lpd8806/README.rst delete mode 100644 samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.conf delete mode 100644 samples/drivers/led_lpd8806/prj.conf delete mode 100644 samples/drivers/led_lpd8806/sample.yaml delete mode 100644 samples/drivers/led_lpd8806/src/main.c create mode 100644 samples/drivers/led_strip/boards/96b_carbon_stm32f401xe.conf rename samples/drivers/{led_lpd8806 => led_strip}/boards/96b_carbon_stm32f401xe.overlay (72%) create mode 100644 samples/drivers/led_strip/boards/adafruit_itsybitsy.conf create mode 100644 samples/drivers/led_strip/boards/adafruit_trinket_m0.conf rename samples/drivers/{led_apa102 => led_strip}/boards/blueclover_plt_demo_v2_nrf52832.conf (57%) rename samples/drivers/{led_apa102 => led_strip}/boards/blueclover_plt_demo_v2_nrf52832.overlay (100%) create mode 100644 samples/drivers/led_strip/boards/nucleo_l432kc.conf rename samples/drivers/{led_apa102 => led_strip}/boards/nucleo_l432kc.overlay (74%) diff --git a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts index 103e18d8328..56a31b13106 100644 --- a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts +++ b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts @@ -48,6 +48,7 @@ sw0 = &button0; watchdog0 = &wdt0; spi-flash0 = &gd25q16; + led-strip = &apa102; }; }; diff --git a/boards/adafruit/itsybitsy/doc/index.rst b/boards/adafruit/itsybitsy/doc/index.rst index f4d6259ff41..c2e4330c04d 100644 --- a/boards/adafruit/itsybitsy/doc/index.rst +++ b/boards/adafruit/itsybitsy/doc/index.rst @@ -123,7 +123,7 @@ The :zephyr:code-sample:`button` sample lets you test the buttons (switches) and The :zephyr:code-sample:`blinky` sample lets you test the red LED. The DotStar LED has been implemented as a SPI device and can be tested -with the :zephyr:code-sample:`led-apa102` sample application. +with the :zephyr:code-sample:`led-strip` sample application. You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in diff --git a/boards/adafruit/trinket_m0/adafruit_trinket_m0.dts b/boards/adafruit/trinket_m0/adafruit_trinket_m0.dts index dd227354dc0..b94b0e1ed73 100644 --- a/boards/adafruit/trinket_m0/adafruit_trinket_m0.dts +++ b/boards/adafruit/trinket_m0/adafruit_trinket_m0.dts @@ -25,6 +25,7 @@ aliases { led0 = &led0; pwm-led0 = &pwm_led0; + led-strip = &led1; }; leds { diff --git a/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts index 4c49979bb0a..48bcacff102 100644 --- a/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts +++ b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts @@ -45,6 +45,7 @@ pwm-buzzer = &pwm0; watchdog0 = &wdt0; accel0 = &bmi270; + led-strip = &apa102; }; }; @@ -102,7 +103,7 @@ pinctrl-0 = <&spi1_default>; pinctrl-1 = <&spi1_sleep>; pinctrl-names = "default", "sleep"; - apa102@0 { + apa102: apa102@0 { compatible = "apa,apa102"; reg = <0>; spi-max-frequency = <5250000>; diff --git a/boards/blue_clover/plt_demo_v2/doc/index.rst b/boards/blue_clover/plt_demo_v2/doc/index.rst index ae3b5c158f7..8dfc2c9527b 100644 --- a/boards/blue_clover/plt_demo_v2/doc/index.rst +++ b/boards/blue_clover/plt_demo_v2/doc/index.rst @@ -122,7 +122,7 @@ Flashing Flashing Zephyr onto the ``blueclover_plt_demo_v2/nrf52832`` board requires an external programmer. The programmer is attached to the SWD header. -Build the Zephyr kernel and the :zephyr:code-sample:`led-apa102` sample application. +Build the Zephyr kernel and the :zephyr:code-sample:`led-strip` sample application. .. zephyr-app-commands:: :zephyr-app: samples/drivers/led_apa102 diff --git a/samples/drivers/led_apa102/CMakeLists.txt b/samples/drivers/led_apa102/CMakeLists.txt deleted file mode 100644 index d270ab00800..00000000000 --- a/samples/drivers/led_apa102/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(led_apa102) - -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) diff --git a/samples/drivers/led_apa102/README.rst b/samples/drivers/led_apa102/README.rst deleted file mode 100644 index 2ea03328238..00000000000 --- a/samples/drivers/led_apa102/README.rst +++ /dev/null @@ -1,90 +0,0 @@ -.. zephyr:code-sample:: led-apa102 - :name: APA102 LED strip - :relevant-api: led_strip_interface - - Control an LED strip using an APA102, Adafruit DotStar, or compatible driver chip. - -Overview -******** - -This sample application demonstrates basic usage of the APA102 LED -strip driver, for controlling LED strips using APA102, Adafruit DotStar, -and compatible driver chips. - -Requirements -************ - -.. _Dotstar product from AdaFruit: https://www.adafruit.com/category/885 -.. _74AHCT125: https://cdn-shop.adafruit.com/datasheets/74AHC125.pdf - -- LED strip using APA102 or compatible, such as the any `Dotstar product - from AdaFruit`_. - -- Zephyr board with SPI master driver. SPI communications must use 5V - signaling, which may require a level translator, such as the - `74AHCT125`_. - -- 5V power supply. - -Wiring -****** - -#. Ensure your Zephyr board, the 5V power supply, and the LED strip - share a common ground. -#. Connect the MOSI pin of your board's SPI master to the data input - pin of the first APA102 IC in the strip. -#. Connect the SCLK pin of your board's SPI master to the clock input - pin of the first APA102 IC in the strip. -#. Connect the 5V power supply pin to the 5V input of the LED strip. - -Building and Running -******************** - -The sample application is located at ``samples/drivers/led_apa102/`` -in the Zephyr source tree. - -Configure For Your Board -======================== - -Now check if your board is already supported, by looking for a file -named ``boards/YOUR_BOARD_NAME.conf`` in the application directory. - -If your board isn't supported yet, you'll need to configure the -application as follows. - -#. Configure your board's SPI master in a configuration file under - ``boards/`` in the sample directory. - - To provide additional configuration for some particular board, - create a ``boards/YOUR_BOARD_NAME.conf`` file in the application - directory. It will be merged into the application configuration. - - In this file, you must ensure that the SPI peripheral you want to - use for this demo is enabled. See ``boards/nucleo_l432kc.conf`` for - an example. - - #. Configure your board's dts overlay. See ``nucleo_l432kc.overlay`` - for an example. - -#. Set the number of LEDs in your strip in the application sources. - This is determined by the macro ``STRIP_NUM_LEDS`` in the file - ``src/main.c``. - -Then build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_apa102 - :board: - :goals: flash - :compact: - -Refer to your :ref:`board's documentation ` for alternative -flash instructions if your board doesn't support the ``flash`` target. - -When you connect to your board's serial console, you should see the -following output: - -.. code-block:: none - - ***** BOOTING ZEPHYR OS zephyr-v1.13.XX ***** - [general] [INF] main: Found LED strip device APA102 diff --git a/samples/drivers/led_apa102/prj.conf b/samples/drivers/led_apa102/prj.conf deleted file mode 100644 index 70d3f24081d..00000000000 --- a/samples/drivers/led_apa102/prj.conf +++ /dev/null @@ -1,5 +0,0 @@ -# This file expresses generic requirements ONLY; see README.rst. - -CONFIG_LOG=y -CONFIG_LED_STRIP=y -CONFIG_POLL=y diff --git a/samples/drivers/led_apa102/sample.yaml b/samples/drivers/led_apa102/sample.yaml deleted file mode 100644 index a11bad0efff..00000000000 --- a/samples/drivers/led_apa102/sample.yaml +++ /dev/null @@ -1,8 +0,0 @@ -sample: - description: Demonstration of the APA102 LED strip driver - name: APA102 sample -tests: - sample.drivers.led.apa102: - platform_allow: nucleo_l432kc - tags: LED - depends_on: spi diff --git a/samples/drivers/led_apa102/src/main.c b/samples/drivers/led_apa102/src/main.c deleted file mode 100644 index b1368016318..00000000000 --- a/samples/drivers/led_apa102/src/main.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2017 Linaro Limited - * Copyright (c) 2018 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#define LOG_LEVEL 4 -#include -LOG_MODULE_REGISTER(main); - -#include -#include -#include -#include -#include - -/* - * Number of RGB LEDs in the LED strip, adjust as needed. - */ -#define STRIP_NUM_LEDS 20 - -#define DELAY_TIME K_MSEC(40) - -static const struct led_rgb colors[] = { - { .r = 0xff, .g = 0x00, .b = 0x00, }, /* red */ - { .r = 0x00, .g = 0xff, .b = 0x00, }, /* green */ - { .r = 0x00, .g = 0x00, .b = 0xff, }, /* blue */ -}; - -static const struct led_rgb black = { - .r = 0x00, - .g = 0x00, - .b = 0x00, -}; - -struct led_rgb strip_colors[STRIP_NUM_LEDS]; - -const struct led_rgb *color_at(size_t time, size_t i) -{ - size_t rgb_start = time % STRIP_NUM_LEDS; - - if (rgb_start <= i && i < rgb_start + ARRAY_SIZE(colors)) { - return &colors[i - rgb_start]; - } else { - return &black; - } -} - -#define DELAY_TIME K_MSEC(40) -int main(void) -{ - const struct device *strip; - size_t i, time; - - strip = DEVICE_DT_GET_ANY(apa_apa102); - if (!strip) { - LOG_ERR("LED strip device not found"); - return 0; - } else if (!device_is_ready(strip)) { - LOG_ERR("LED strip device %s is not ready", strip->name); - return 0; - } else { - LOG_INF("Found LED strip device %s", strip->name); - } - - /* - * Display a pattern that "walks" the three primary colors - * down the strip until it reaches the end, then starts at the - * beginning. This has the effect of moving it around in a - * circle in the case of rings of pixels. - */ - LOG_INF("Displaying pattern on strip"); - time = 0; - while (1) { - for (i = 0; i < STRIP_NUM_LEDS; i++) { - memcpy(&strip_colors[i], color_at(time, i), - sizeof(strip_colors[i])); - } - led_strip_update_rgb(strip, strip_colors, STRIP_NUM_LEDS); - k_sleep(DELAY_TIME); - time++; - } - return 0; -} diff --git a/samples/drivers/led_lpd8806/CMakeLists.txt b/samples/drivers/led_lpd8806/CMakeLists.txt deleted file mode 100644 index 6220933b5f9..00000000000 --- a/samples/drivers/led_lpd8806/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(led_lpd8806) - -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) diff --git a/samples/drivers/led_lpd8806/README.rst b/samples/drivers/led_lpd8806/README.rst deleted file mode 100644 index 570f6498fc7..00000000000 --- a/samples/drivers/led_lpd8806/README.rst +++ /dev/null @@ -1,89 +0,0 @@ -.. zephyr:code-sample:: led-lpd8806 - :name: LPD880x LED strip - :relevant-api: led_strip_interface - - Control an LED strip using an LPD880x-compatible driver chip. - -Overview -******** - -This sample application demonstrates basic usage of the lpd880x LED -strip driver, for controlling LED strips using LPD8803, LPD8806, and -compatible driver chips. - -Requirements -************ - -.. _these strips from AdaFruit: https://www.adafruit.com/product/306 -.. _74AHCT125: https://cdn-shop.adafruit.com/datasheets/74AHC125.pdf - -- LED strip using LPD8806 or compatible, such as `these strips from AdaFruit`_. - -- Zephyr board with SPI master driver. SPI communications must use 5V - signaling, which may require a level translator, such as the - `74AHCT125`_. - -- 5V power supply. - -Wiring -****** - -#. Ensure your Zephyr board, the 5V power supply, and the LED strip - share a common ground. -#. Connect the MOSI pin of your board's SPI master to the data input - pin of the first LPD8806 IC in the strip. -#. Connect the SCLK pin of your board's SPI master to the clock input - pin of the first LPD8806 IC in the strip. -#. Connect the 5V power supply pin to the 5V input of the LED strip. - -Building and Running -******************** - -The sample application is located at ``samples/drivers/led_lpd8806/`` -in the Zephyr source tree. - -Before running the application, configure it as follows. - -#. Configure your board's SPI master in a configuration file under - ``boards/`` in the sample directory. - - To provide additional configuration for some particular board, - create a ``boards/YOUR_BOARD_NAME.conf`` file in the application - directory. It will be merged into the application configuration. - - In this file, you must ensure that the SPI peripheral you want to - use for this demo is enabled, and that its name is "lpd8806_spi". - See ``boards/96b_carbon.conf`` for an example, and refer to your - board's configuration options to set up your desired SPI master. - -#. Set the number of LEDs in your strip in the application sources. - This is determined by the macro ``STRIP_NUM_LEDS`` in the file - ``src/main.c``. The value in the file was chosen to work with one - meter of the AdaFruit strip. - -Then build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_lpd8806 - :board: - :goals: flash - :compact: - -Refer to your :ref:`board's documentation ` for alternative -flash instructions if your board doesn't support the ``flash`` target. - -When you connect to your board's serial console, you should see the -following output: - -.. code-block:: none - - ***** BOOTING ZEPHYR OS v1.9.99 ***** - [general] [INF] main: Found SPI device lpd8806_spi - [general] [INF] main: Found LED strip device lpd880x_strip - [general] [INF] main: Displaying pattern on strip - -References -********** - -- `LPD8806 datasheet `_ -- `74AHCT125 datasheet `_ diff --git a/samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.conf b/samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.conf deleted file mode 100644 index 0232f7d97c3..00000000000 --- a/samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SPI_STM32_INTERRUPT=y diff --git a/samples/drivers/led_lpd8806/prj.conf b/samples/drivers/led_lpd8806/prj.conf deleted file mode 100644 index 704a6a00049..00000000000 --- a/samples/drivers/led_lpd8806/prj.conf +++ /dev/null @@ -1,7 +0,0 @@ -# This file expresses generic requirements ONLY; see README.rst. - -CONFIG_LOG=y -CONFIG_BOOT_BANNER=y -CONFIG_POLL=y - -CONFIG_LED_STRIP=y diff --git a/samples/drivers/led_lpd8806/sample.yaml b/samples/drivers/led_lpd8806/sample.yaml deleted file mode 100644 index 7d0e66d79ba..00000000000 --- a/samples/drivers/led_lpd8806/sample.yaml +++ /dev/null @@ -1,7 +0,0 @@ -sample: - description: Demonstration of the lpd880x LED driver - name: LPD880x sample -tests: - sample.drivers.led.lpd8806: - platform_allow: 96b_carbon/stm32f401xe - tags: LED diff --git a/samples/drivers/led_lpd8806/src/main.c b/samples/drivers/led_lpd8806/src/main.c deleted file mode 100644 index 2c23230835c..00000000000 --- a/samples/drivers/led_lpd8806/src/main.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2017 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL -#include -LOG_MODULE_REGISTER(main); - -#include -#include -#include -#include -#include - -/* - * Number of RGB LEDs in the LED strip, adjust as needed. - */ -#define STRIP_NUM_LEDS 32 - -#define DELAY_TIME K_MSEC(40) - -static const struct led_rgb colors[] = { - { .r = 0xff, .g = 0x00, .b = 0x00, }, /* red */ - { .r = 0x00, .g = 0xff, .b = 0x00, }, /* green */ - { .r = 0x00, .g = 0x00, .b = 0xff, }, /* blue */ -}; - -static const struct led_rgb black = { - .r = 0x00, - .g = 0x00, - .b = 0x00, -}; - -struct led_rgb strip_colors[STRIP_NUM_LEDS]; - -static const struct device *const strip = DEVICE_DT_GET_ANY(greeled_lpd8806); - -const struct led_rgb *color_at(size_t time, size_t i) -{ - size_t rgb_start = time % STRIP_NUM_LEDS; - - if (rgb_start <= i && i < rgb_start + ARRAY_SIZE(colors)) { - return &colors[i - rgb_start]; - } else { - return &black; - } -} - -int main(void) -{ - size_t i, time; - - if (!strip) { - LOG_ERR("LED strip device not found"); - return 0; - } else if (!device_is_ready(strip)) { - LOG_INF("LED strip device %s is not ready", strip->name); - return 0; - } - LOG_INF("Found LED strip device %s", strip->name); - - /* - * Display a pattern that "walks" the three primary colors - * down the strip until it reaches the end, then starts at the - * beginning. - */ - LOG_INF("Displaying pattern on strip"); - time = 0; - while (1) { - for (i = 0; i < STRIP_NUM_LEDS; i++) { - memcpy(&strip_colors[i], color_at(time, i), - sizeof(strip_colors[i])); - } - led_strip_update_rgb(strip, strip_colors, STRIP_NUM_LEDS); - k_sleep(DELAY_TIME); - time++; - } - return 0; -} diff --git a/samples/drivers/led_strip/Kconfig b/samples/drivers/led_strip/Kconfig index fdf12abde24..2931d4cc929 100644 --- a/samples/drivers/led_strip/Kconfig +++ b/samples/drivers/led_strip/Kconfig @@ -9,6 +9,14 @@ config SAMPLE_LED_UPDATE_DELAY help Delay between LED updates in ms. +config SAMPLE_LED_STRIP_LENGTH + int "LED strip length" + default 0 + help + Number of LEDs in the strip. + If the value is zero, use the 'chain-length' property in + devicetree instead to determine LED numbers. + endmenu source "Kconfig.zephyr" diff --git a/samples/drivers/led_strip/README.rst b/samples/drivers/led_strip/README.rst index c99cf0ee383..7efadc1b85c 100644 --- a/samples/drivers/led_strip/README.rst +++ b/samples/drivers/led_strip/README.rst @@ -2,41 +2,57 @@ :name: LED strip sample :relevant-api: led_strip_interface - Control an LED strip using a WS2812 (or compatible) driver chip. + Control an LED strip example. Overview ******** -This sample application demonstrates basic usage of the WS2812 LED -strip driver, for controlling LED strips using WS2812, WS2812b, -SK6812, Everlight B1414 and compatible driver chips. +This sample application demonstrates basic usage of the LED strip. Requirements ************ -.. _NeoPixel Ring 12 from AdaFruit: https://www.adafruit.com/product/1643 -.. _74AHCT125: https://cdn-shop.adafruit.com/datasheets/74AHC125.pdf +Zephyr supports various LED strip chips. For example, -- LED strip using WS2812 or compatible, such as the `NeoPixel Ring 12 - from AdaFruit`_. +- WS2812, such as the `NeoPixel(WS2812 compatible) LED Strip from AdaFruit`_. +- APA102, such as the `Dotstar(APA102 compatible) LED Strip from AdaFruit`_. +- LPD8806, such as the `LPD8806 LED Strip from AdaFruit`_. -- Note that 5V communications may require a level translator, such as the - `74AHCT125`_. +- Power supply. These LED strips usually require a 5V supply. -- LED power strip supply. It's fine to power the LED strip off of your board's - IO voltage level even if that's below 5V; the LEDs will simply be dimmer in - this case. +- If the LED strip connects to the SPI bus, SPI communications usually use 5V + signaling, which may require a level translator, such as the + `74AHCT125 datasheet`_. + +.. _NeoPixel(WS2812 compatible) LED Strip from AdaFruit: https://www.adafruit.com/product/3919 +.. _Dotstar(APA102 compatible) LED Strip from AdaFruit: https://www.adafruit.com/product/2242 +.. _LPD8806 LED Strip from AdaFruit: https://www.adafruit.com/product/1948 +.. _74AHCT125 datasheet: https://cdn-shop.adafruit.com/datasheets/74AHC125.pdf Wiring ****** +APA020 and LPD880x +================== + +#. Ensure your Zephyr board, the 5V power supply, and the LED strip + share a common ground. +#. Connect the MOSI pin of your board's SPI master to the data input + pin of the first IC in the strip. +#. Connect the SCLK pin of your board's SPI master to the clock input + pin of the first IC in the strip. +#. Connect the 5V power supply pin to the 5V input of the LED strip. + +WS2812 +====== + #. Ensure your Zephyr board, and the LED strip share a common ground. #. Connect the LED strip control pin (either I2S SDOUT, SPI MOSI or GPIO) from your board to the data input pin of the first WS2812 IC in the strip. #. Power the LED strip at an I/O level compatible with the control pin signals. -Wiring on a thingy52 -******************** +Note about thingy52 +------------------- The thingy52 has integrated NMOS transistors, that can be used instead of a level shifter. The I2S driver supports inverting the output to suit this scheme, using the ``out-active-low`` dts @@ -46,37 +62,12 @@ property. See the overlay file Building and Running ******************** -.. _blog post on WS2812 timing: https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/ - -This sample's source directory is :zephyr_file:`samples/drivers/led_strip/`. - -To make sure the sample is set up properly for building, you must: - -- select the correct WS2812 driver backend for your SoC. This currently should - be :kconfig:option:`CONFIG_WS2812_STRIP_SPI` unless you are using an nRF51 SoC, in - which case it will be :kconfig:option:`CONFIG_WS2812_STRIP_GPIO`. - For the nRF52832, the SPI peripheral might output some garbage at the end of - transmissions, and that might confuse older WS2812 strips. Use the I2S driver - in those cases. - -- create a ``led-strip`` :ref:`devicetree alias `, which refers - to a node in your :ref:`devicetree ` with a - ``worldsemi,ws2812-i2s``, ``worldsemi,ws2812-spi`` or - ``worldsemi,ws2812-gpio`` compatible. The node must be properly configured for - the driver backend (I2S, SPI or GPIO) and daisy chain length (number of WS2812 - chips). - -For example devicetree configurations for each compatible, see -:zephyr_file:`samples/drivers/led_ws2812/boards/thingy52_nrf52832.overlay`, -:zephyr_file:`samples/drivers/led_ws2812/boards/nrf52dk_nrf52832.overlay` and -:zephyr_file:`samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay`. - -Some boards are already supported out of the box; see the :file:`boards` -directory for this sample for details. - The sample updates the LED strip periodically. The update frequency can be modified by changing the :kconfig:option:`CONFIG_SAMPLE_LED_UPDATE_DELAY`. +If there is no chain-length property in the devicetree node, you need to set +the number of LEDs in the :kconfig:option:`CONFIG_SAMPLE_LED_STRIP_LENGTH` option. + Then build and flash the application: .. zephyr-app-commands:: @@ -94,35 +85,18 @@ following output: [00:00:00.005,920] main: Found LED strip device WS2812 [00:00:00.005,950] main: Displaying pattern on strip -Supported drivers -***************** - -This sample uses different drivers depending on the selected board: - -I2S driver: - -- thingy52/nrf52832 -- nrf5340dk/nrf5340 (3.3V logic level, a logic level shifter may be required) - - should work for other boards featuring an nRF5340 host processor - -SPI driver: - -- mimxrt1050_evk -- nrf52dk/nrf52832 -- nucleo_f070rb -- nucleo_g071rb -- nucleo_h743zi -- nucleo_l476rg - -GPIO driver (cortex-M0 only): - -- bbc_microbit -- nrf51dk/nrf51822 - References ********** -- `RGB LED strips: an overview `_ -- `74AHCT125 datasheet - `_ +- `WS2812 datasheet`_ +- `LPD8806 datasheet`_ +- `APA102C datasheet`_ +- `74AHCT125 datasheet`_ +- `RGB LED strips: an overview`_ - An excellent `blog post on WS2812 timing`_. + +.. _WS2812 datasheet: https://cdn-shop.adafruit.com/datasheets/WS2812.pdf +.. _LPD8806 datasheet: https://cdn-shop.adafruit.com/datasheets/lpd8806+english.pdf +.. _APA102C datasheet: https://cdn-shop.adafruit.com/product-files/2477/APA102C-iPixelLED.pdf +.. _blog post on WS2812 timing: https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/ +.. _RGB LED strips\: an overview: http://nut-bolt.nl/2012/rgb-led-strips/ diff --git a/samples/drivers/led_strip/boards/96b_carbon_stm32f401xe.conf b/samples/drivers/led_strip/boards/96b_carbon_stm32f401xe.conf new file mode 100644 index 00000000000..49fc84a0a95 --- /dev/null +++ b/samples/drivers/led_strip/boards/96b_carbon_stm32f401xe.conf @@ -0,0 +1,3 @@ +CONFIG_SPI_STM32_INTERRUPT=y + +CONFIG_SAMPLE_LED_STRIP_LENGTH=1 diff --git a/samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.overlay b/samples/drivers/led_strip/boards/96b_carbon_stm32f401xe.overlay similarity index 72% rename from samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.overlay rename to samples/drivers/led_strip/boards/96b_carbon_stm32f401xe.overlay index 55bbb72a003..b4be11a83a9 100644 --- a/samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.overlay +++ b/samples/drivers/led_strip/boards/96b_carbon_stm32f401xe.overlay @@ -6,9 +6,15 @@ &spi2 { - led_strip@0 { + lpd8806: lpd8806@0 { compatible = "greeled,lpd8806"; reg = <0>; spi-max-frequency = <2000000>; }; }; + +/ { + aliases { + led-strip = &lpd8806; + }; +}; diff --git a/samples/drivers/led_strip/boards/adafruit_itsybitsy.conf b/samples/drivers/led_strip/boards/adafruit_itsybitsy.conf new file mode 100644 index 00000000000..9c347a35588 --- /dev/null +++ b/samples/drivers/led_strip/boards/adafruit_itsybitsy.conf @@ -0,0 +1 @@ +CONFIG_SAMPLE_LED_STRIP_LENGTH=4 diff --git a/samples/drivers/led_strip/boards/adafruit_trinket_m0.conf b/samples/drivers/led_strip/boards/adafruit_trinket_m0.conf new file mode 100644 index 00000000000..af9d53eddc0 --- /dev/null +++ b/samples/drivers/led_strip/boards/adafruit_trinket_m0.conf @@ -0,0 +1 @@ +CONFIG_SAMPLE_LED_STRIP_LENGTH=1 diff --git a/samples/drivers/led_apa102/boards/blueclover_plt_demo_v2_nrf52832.conf b/samples/drivers/led_strip/boards/blueclover_plt_demo_v2_nrf52832.conf similarity index 57% rename from samples/drivers/led_apa102/boards/blueclover_plt_demo_v2_nrf52832.conf rename to samples/drivers/led_strip/boards/blueclover_plt_demo_v2_nrf52832.conf index a97acd9ffab..e4aff43aee8 100644 --- a/samples/drivers/led_apa102/boards/blueclover_plt_demo_v2_nrf52832.conf +++ b/samples/drivers/led_strip/boards/blueclover_plt_demo_v2_nrf52832.conf @@ -1,2 +1,3 @@ # Enable LED 5V Regulator CONFIG_REGULATOR=y +CONFIG_SAMPLE_LED_STRIP_LENGTH=4 diff --git a/samples/drivers/led_apa102/boards/blueclover_plt_demo_v2_nrf52832.overlay b/samples/drivers/led_strip/boards/blueclover_plt_demo_v2_nrf52832.overlay similarity index 100% rename from samples/drivers/led_apa102/boards/blueclover_plt_demo_v2_nrf52832.overlay rename to samples/drivers/led_strip/boards/blueclover_plt_demo_v2_nrf52832.overlay diff --git a/samples/drivers/led_strip/boards/nucleo_l432kc.conf b/samples/drivers/led_strip/boards/nucleo_l432kc.conf new file mode 100644 index 00000000000..af9d53eddc0 --- /dev/null +++ b/samples/drivers/led_strip/boards/nucleo_l432kc.conf @@ -0,0 +1 @@ +CONFIG_SAMPLE_LED_STRIP_LENGTH=1 diff --git a/samples/drivers/led_apa102/boards/nucleo_l432kc.overlay b/samples/drivers/led_strip/boards/nucleo_l432kc.overlay similarity index 74% rename from samples/drivers/led_apa102/boards/nucleo_l432kc.overlay rename to samples/drivers/led_strip/boards/nucleo_l432kc.overlay index 793579f959e..0a7fce2fe75 100644 --- a/samples/drivers/led_apa102/boards/nucleo_l432kc.overlay +++ b/samples/drivers/led_strip/boards/nucleo_l432kc.overlay @@ -6,9 +6,15 @@ &spi1 { - apa102@0 { + apa102: apa102@0 { compatible = "apa,apa102"; reg = <0>; spi-max-frequency = <5250000>; }; }; + +/ { + aliases { + led-strip = &apa102; + }; +}; diff --git a/samples/drivers/led_strip/src/main.c b/samples/drivers/led_strip/src/main.c index d26fe6a7e91..77c80e70969 100644 --- a/samples/drivers/led_strip/src/main.c +++ b/samples/drivers/led_strip/src/main.c @@ -1,6 +1,7 @@ /* * Copyright (c) 2017 Linaro Limited * Copyright (c) 2018 Intel Corporation + * Copyright (c) 2024 TOKITA Hiroshi * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,7 +20,14 @@ LOG_MODULE_REGISTER(main); #include #define STRIP_NODE DT_ALIAS(led_strip) + +#if CONFIG_SAMPLE_LED_STRIP_LENGTH != 0 +#define STRIP_NUM_PIXELS CONFIG_SAMPLE_LED_STRIP_LENGTH +#elif DT_NODE_HAS_PROP(DT_ALIAS(led_strip), chain_length) #define STRIP_NUM_PIXELS DT_PROP(DT_ALIAS(led_strip), chain_length) +#else +#error Unable to determine length of LED strip +#endif #define DELAY_TIME K_MSEC(CONFIG_SAMPLE_LED_UPDATE_DELAY) @@ -31,7 +39,7 @@ static const struct led_rgb colors[] = { RGB(0x00, 0x00, 0x0f), /* blue */ }; -struct led_rgb pixels[STRIP_NUM_PIXELS]; +static struct led_rgb pixels[STRIP_NUM_PIXELS]; static const struct device *const strip = DEVICE_DT_GET(STRIP_NODE); From f90c2b1122ead7c8dcb4c9cbf98abf2544b77ee0 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 14 Mar 2024 10:02:15 +0900 Subject: [PATCH 1100/2402] boards: seagate: legend: Cleanup `led-strip` alias The led-strip alias can be determined in the base dts file. Remove from overlay files and aggregate to the base dts file. Signed-off-by: TOKITA Hiroshi --- boards/seagate/legend/legend.dts | 1 + .../legend/legend_stm32f070xb_25hdd.overlay | 1 - .../legend/legend_stm32f070xb_25ssd.overlay | 4 --- .../legend/legend_stm32f070xb_35.overlay | 1 - samples/drivers/led_strip/src/main.c | 26 ++++++++----------- 5 files changed, 12 insertions(+), 21 deletions(-) diff --git a/boards/seagate/legend/legend.dts b/boards/seagate/legend/legend.dts index 521b85e092c..245d2c8de7d 100644 --- a/boards/seagate/legend/legend.dts +++ b/boards/seagate/legend/legend.dts @@ -22,6 +22,7 @@ aliases { watchdog0 = &iwdg; spi-flash0 = &spi_nor; + led-strip = &led_strip_spi; }; board_id: brd-id { diff --git a/boards/seagate/legend/legend_stm32f070xb_25hdd.overlay b/boards/seagate/legend/legend_stm32f070xb_25hdd.overlay index f4ab4af03e6..48a6616e853 100644 --- a/boards/seagate/legend/legend_stm32f070xb_25hdd.overlay +++ b/boards/seagate/legend/legend_stm32f070xb_25hdd.overlay @@ -10,7 +10,6 @@ aliases { pwm-led0 = &pwm_led0; - led-strip = &led_strip_spi; }; led_pwm: pwmleds { diff --git a/boards/seagate/legend/legend_stm32f070xb_25ssd.overlay b/boards/seagate/legend/legend_stm32f070xb_25ssd.overlay index 2f0f4d19baf..e8c26ef09bd 100644 --- a/boards/seagate/legend/legend_stm32f070xb_25ssd.overlay +++ b/boards/seagate/legend/legend_stm32f070xb_25ssd.overlay @@ -7,10 +7,6 @@ / { model = "Seagate Legend 2.5 SSD board"; compatible = "legend25_ssd", "seagate,legend25_ssd"; - - aliases { - led-strip = &led_strip_spi; - }; }; &clk_hse { diff --git a/boards/seagate/legend/legend_stm32f070xb_35.overlay b/boards/seagate/legend/legend_stm32f070xb_35.overlay index 3568bf7c31d..c3af3d922ee 100644 --- a/boards/seagate/legend/legend_stm32f070xb_35.overlay +++ b/boards/seagate/legend/legend_stm32f070xb_35.overlay @@ -10,7 +10,6 @@ aliases { pwm-led0 = &pwm_led0; - led-strip = &led_strip_spi; }; led_pwm: pwmleds { diff --git a/samples/drivers/led_strip/src/main.c b/samples/drivers/led_strip/src/main.c index 77c80e70969..d6dafcd68ea 100644 --- a/samples/drivers/led_strip/src/main.c +++ b/samples/drivers/led_strip/src/main.c @@ -45,7 +45,7 @@ static const struct device *const strip = DEVICE_DT_GET(STRIP_NODE); int main(void) { - size_t cursor = 0, color = 0; + size_t color = 0; int rc; if (device_is_ready(strip)) { @@ -57,24 +57,20 @@ int main(void) LOG_INF("Displaying pattern on strip"); while (1) { - memset(&pixels, 0x00, sizeof(pixels)); - memcpy(&pixels[cursor], &colors[color], sizeof(struct led_rgb)); - rc = led_strip_update_rgb(strip, pixels, STRIP_NUM_PIXELS); + for (size_t cursor = 0; cursor < ARRAY_SIZE(pixels); cursor++) { + memset(&pixels, 0x00, sizeof(pixels)); + memcpy(&pixels[cursor], &colors[color], sizeof(struct led_rgb)); - if (rc) { - LOG_ERR("couldn't update strip: %d", rc); - } - - cursor++; - if (cursor >= STRIP_NUM_PIXELS) { - cursor = 0; - color++; - if (color == ARRAY_SIZE(colors)) { - color = 0; + rc = led_strip_update_rgb(strip, pixels, STRIP_NUM_PIXELS); + if (rc) { + LOG_ERR("couldn't update strip: %d", rc); } + + k_sleep(DELAY_TIME); } - k_sleep(DELAY_TIME); + color = (color + 1) % ARRAY_SIZE(colors); } + return 0; } From 241d41596bbe90491e542037bb377b106d6cfb8e Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 14 Mar 2024 14:33:49 -0500 Subject: [PATCH 1101/2402] soc: nxp: rw: Support CTIMER Add DT entries and clocking for CTIMER peripherals on RW61x. Signed-off-by: Declan Snyder --- dts/arm/nxp/nxp_rw6xx_common.dtsi | 48 +++++++++++++++++++++++++++++++ soc/nxp/rw/soc.c | 15 ++++++++++ 2 files changed, 63 insertions(+) diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index 17b9cfb2ba6..39545c0d19d 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -174,6 +174,54 @@ #dma-cells = <1>; dma-channels = <33>; }; + + ctimer0: ctimer@28000 { + compatible = "nxp,lpc-ctimer"; + reg = <0x28000 0x1000>; + interrupts = <10 0>; + status = "disabled"; + clk-source = <1>; + clocks = <&clkctl1 MCUX_CTIMER0_CLK>; + mode = <0>; + input = <0>; + prescale = <0>; + }; + + ctimer1: ctimer@29000 { + compatible = "nxp,lpc-ctimer"; + reg = <0x29000 0x1000>; + interrupts = <11 0>; + status = "disabled"; + clk-source = <1>; + clocks = <&clkctl1 MCUX_CTIMER1_CLK>; + mode = <0>; + input = <0>; + prescale = <0>; + }; + + ctimer2: ctimer@2a000 { + compatible = "nxp,lpc-ctimer"; + reg = <0x2a000 0x1000>; + interrupts = <39 0>; + status = "disabled"; + clk-source = <1>; + clocks = <&clkctl1 MCUX_CTIMER2_CLK>; + mode = <0>; + input = <0>; + prescale = <0>; + }; + + ctimer3: ctimer@2b000 { + compatible = "nxp,lpc-ctimer"; + reg = <0x2b000 0x1000>; + interrupts = <13 0>; + status = "disabled"; + clk-source = <1>; + clocks = <&clkctl1 MCUX_CTIMER3_CLK>; + mode = <0>; + input = <0>; + prescale = <0>; + }; }; &flexspi { diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c index 236c524d642..0b3da776f82 100644 --- a/soc/nxp/rw/soc.c +++ b/soc/nxp/rw/soc.c @@ -207,6 +207,21 @@ __ramfunc void clock_init(void) CLOCK_AttachClk(kSFRO_to_FLEXCOMM14); #endif #endif /* CONFIG_SPI */ + +#ifdef CONFIG_COUNTER_MCUX_CTIMER +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ctimer0), nxp_lpc_ctimer, okay)) + CLOCK_AttachClk(kSFRO_to_CTIMER0); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ctimer1), nxp_lpc_ctimer, okay)) + CLOCK_AttachClk(kSFRO_to_CTIMER1); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ctimer2), nxp_lpc_ctimer, okay)) + CLOCK_AttachClk(kSFRO_to_CTIMER2); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ctimer3), nxp_lpc_ctimer, okay)) + CLOCK_AttachClk(kSFRO_to_CTIMER3); +#endif +#endif /* CONFIG_COUNTER_MCUX_CTIMER */ } /** From d3e2052a690b79b0b70aa3e3d1b1963e70d5c820 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 14 Mar 2024 14:36:23 -0500 Subject: [PATCH 1102/2402] drivers: clock_control: Support RW MRT Support RW MRT in clock control syscon driver Signed-off-by: Declan Snyder --- .../clock_control/clock_control_mcux_syscon.c | 19 +++++++++++++++---- .../dt-bindings/clock/mcux_lpc_syscon_clock.h | 1 + 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index 9eef978b0ed..26917f98624 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -25,12 +25,17 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev, #endif /* defined(CONFIG_CAN_MCUX_MCAN) */ #if defined(CONFIG_COUNTER_NXP_MRT) if ((uint32_t)sub_system == MCUX_MRT_CLK) { -#if defined(CONFIG_SOC_FAMILY_LPC) +#if defined(CONFIG_SOC_FAMILY_LPC) || defined(CONFIG_SOC_SERIES_RW6XX) CLOCK_EnableClock(kCLOCK_Mrt); #elif defined(CONFIG_SOC_FAMILY_NXP_IMXRT) CLOCK_EnableClock(kCLOCK_Mrt0); #endif } +#if defined(CONFIG_SOC_SERIES_RW6XX) + if ((uint32_t)sub_system == MCUX_FREEMRT_CLK) { + CLOCK_EnableClock(kCLOCK_FreeMrt); + } +#endif #endif /* defined(CONFIG_COUNTER_NXP_MRT) */ #if defined(CONFIG_PINCTRL_NXP_KINETIS) @@ -216,12 +221,18 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( #if defined(CONFIG_COUNTER_NXP_MRT) case MCUX_MRT_CLK: -#endif +#if defined(CONFIG_SOC_SERIES_RW6XX) + case MCUX_FREEMRT_CLK: +#endif /* RW */ +#endif /* MRT */ #if defined(CONFIG_PWM_MCUX_SCTIMER) case MCUX_SCTIMER_CLK: #endif - -#ifndef CONFIG_SOC_SERIES_RW6XX +#ifdef CONFIG_SOC_SERIES_RW6XX + /* RW6XX uses core clock for SCTimer, not bus clock */ + *rate = CLOCK_GetCoreSysClkFreq(); + break; +#else case MCUX_BUS_CLK: *rate = CLOCK_GetFreq(kCLOCK_BusClk); break; diff --git a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h index 9b7eccb8a4f..99c99431f13 100644 --- a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -65,6 +65,7 @@ #define MCUX_FLEXSPI2_CLK MCUX_LPC_CLK_ID(0x0A, 0x01) #define MCUX_MRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x00) +#define MCUX_FREEMRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x01) #define MCUX_PORT0_CLK MCUX_LPC_CLK_ID(0x0C, 0x00) #define MCUX_PORT1_CLK MCUX_LPC_CLK_ID(0x0C, 0x01) From a65ae89b9e05f8199b6624b93c8e05fab73a7c70 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 14 Mar 2024 14:35:24 -0500 Subject: [PATCH 1103/2402] soc: nxp: rw: Support MRT counter Add DT entries and peripheral reset for MRT on RW. Signed-off-by: Declan Snyder --- dts/arm/nxp/nxp_rw6xx_common.dtsi | 65 +++++++++++++++++++++++++++++++ soc/nxp/rw/soc.c | 6 +++ 2 files changed, 71 insertions(+) diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index 39545c0d19d..513264df879 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -222,6 +222,71 @@ input = <0>; prescale = <0>; }; + + mrt0: mrt@2d000 { + compatible = "nxp,mrt"; + reg = <0x2d000 0x100>; + interrupts = <9 0>; + num-channels = <4>; + num-bits = <24>; + clocks = <&clkctl1 MCUX_MRT_CLK>; + #address-cells = <1>; + #size-cells = <0>; + + mrt0_channel0: mrt0_channel@0 { + compatible = "nxp,mrt-channel"; + reg = <0>; + status = "disabled"; + }; + mrt0_channel1: mrt0_channel@1 { + compatible = "nxp,mrt-channel"; + reg = <1>; + status = "disabled"; + }; + mrt0_channel2: mrt0_channel@2 { + compatible = "nxp,mrt-channel"; + reg = <2>; + status = "disabled"; + }; + mrt0_channel3: mrt0_channel@3 { + compatible = "nxp,mrt-channel"; + reg = <3>; + status = "disabled"; + }; + }; + + mrt1: mrt@3f000 { + compatible = "nxp,mrt"; + reg = <0x3f000 0x100>; + interrupts = <23 0>; + num-channels = <4>; + num-bits = <24>; + clocks = <&clkctl1 MCUX_FREEMRT_CLK>; + #address-cells = <1>; + #size-cells = <0>; + + mrt1_channel0: mrt1_channel@0 { + compatible = "nxp,mrt-channel"; + reg = <0>; + status = "disabled"; + }; + mrt1_channel1: mrt1_channel@1 { + compatible = "nxp,mrt-channel"; + reg = <1>; + status = "disabled"; + }; + mrt1_channel2: mrt1_channel@2 { + compatible = "nxp,mrt-channel"; + reg = <2>; + status = "disabled"; + }; + mrt1_channel3: mrt1_channel@3 { + compatible = "nxp,mrt-channel"; + reg = <3>; + status = "disabled"; + }; + }; + }; &flexspi { diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c index 0b3da776f82..3da03e8409f 100644 --- a/soc/nxp/rw/soc.c +++ b/soc/nxp/rw/soc.c @@ -222,6 +222,12 @@ __ramfunc void clock_init(void) CLOCK_AttachClk(kSFRO_to_CTIMER3); #endif #endif /* CONFIG_COUNTER_MCUX_CTIMER */ + +#ifdef CONFIG_COUNTER_NXP_MRT + RESET_PeripheralReset(kMRT_RST_SHIFT_RSTn); + RESET_PeripheralReset(kFREEMRT_RST_SHIFT_RSTn); +#endif + } /** From 557e5969f33e1208a7e47a564b4ef370966ea62b Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 14 Mar 2024 14:37:44 -0500 Subject: [PATCH 1104/2402] boards: rd_rw612_bga: Enable counters Enable CTimer0 and MRT0 channel 0 by default on the board, and add more of the device instances in the counter api test overlay. Signed-off-by: Declan Snyder --- boards/nxp/rd_rw612_bga/doc/index.rst | 4 +++ boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 8 +++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml | 1 + .../boards/rd_rw612_bga.overlay | 33 +++++++++++++++++++ 4 files changed, 46 insertions(+) create mode 100644 tests/drivers/counter/counter_basic_api/boards/rd_rw612_bga.overlay diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index 7f32a8c6fb5..3797d1bdb9f 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -51,6 +51,10 @@ Supported Features +-----------+------------+-----------------------------------+ | WWDT | on-chip | watchdog | +-----------+------------+-----------------------------------+ +| CTIMER | on-chip | counter | ++-----------+------------+-----------------------------------+ +| MRT | on-chip | counter | ++-----------+------------+-----------------------------------+ The default configuration can be found in the defconfig file: diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index 3b008e8d32b..3ef537e7695 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -128,3 +128,11 @@ arduino_i2c: &flexcomm2 { &dma0 { status = "okay"; }; + +&mrt0_channel0 { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml index 1f3832c88d0..6990f314240 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -21,3 +21,4 @@ supported: - i2c - entropy - watchdog + - counter diff --git a/tests/drivers/counter/counter_basic_api/boards/rd_rw612_bga.overlay b/tests/drivers/counter/counter_basic_api/boards/rd_rw612_bga.overlay new file mode 100644 index 00000000000..b47bf1bde7e --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/rd_rw612_bga.overlay @@ -0,0 +1,33 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&ctimer1 { + status = "okay"; +}; + +&ctimer2 { + status = "okay"; +}; + +&ctimer3 { + status = "okay"; +}; + +&mrt0_channel1 { + status = "okay"; +}; + +&mrt0_channel3 { + status = "okay"; +}; + +&mrt1_channel2 { + status = "okay"; +}; + +&mrt1_channel3 { + status = "okay"; +}; From 4c25482ef69c699fb5fc0b6e409f921462273eba Mon Sep 17 00:00:00 2001 From: Ledion Daja Date: Thu, 1 Feb 2024 12:39:15 +0100 Subject: [PATCH 1105/2402] modules: hal_ethos_u: update module revision Updated revision for hal_ethos_u module, and adapted ethosu_semaphore_take function prototype accordingly in order to align with changes in the NPU driver Signed-off-by: Ledion Daja --- drivers/misc/ethos_u/ethos_u.c | 60 ++++++++++++++++++++-------------- west.yml | 2 +- 2 files changed, 37 insertions(+), 25 deletions(-) diff --git a/drivers/misc/ethos_u/ethos_u.c b/drivers/misc/ethos_u/ethos_u.c index bae2b50c27a..308e689fe0f 100644 --- a/drivers/misc/ethos_u/ethos_u.c +++ b/drivers/misc/ethos_u/ethos_u.c @@ -1,9 +1,10 @@ /* - * Copyright 2021-2022 Arm Limited and/or its affiliates - * + * SPDX-FileCopyrightText: Copyright 2021-2022, 2024 Arm Limited and/or its + * affiliates * SPDX-License-Identifier: Apache-2.0 */ +#include "zephyr/sys_clock.h" #include #include #include @@ -72,13 +73,26 @@ void *ethosu_semaphore_create(void) return (void *)sem; } -int ethosu_semaphore_take(void *sem) +int ethosu_semaphore_take(void *sem, uint64_t timeout) { int status; - status = k_sem_take((struct k_sem *)sem, K_FOREVER); + status = k_sem_take((struct k_sem *)sem, (timeout == ETHOSU_SEMAPHORE_WAIT_FOREVER) + ? K_FOREVER + : Z_TIMEOUT_TICKS(timeout)); + if (status != 0) { - LOG_ERR("Failed to take semaphore with error - %d", status); + /* The Ethos-U driver expects the semaphore implementation to never fail except for + * when a timeout occurs, and the current ethosu_semaphore_take implementation makes + * no distinction, in terms of return codes, between a timeout and other semaphore + * take failures. Also, note that a timeout is virtually indistinguishable from + * other failures if the driver logging is disabled. Handling errors other than a + * timeout is therefore not covered here and is deferred to the application + * developer if necessary. + */ + if (status != -EAGAIN) { + LOG_ERR("Failed to take semaphore with error - %d", status); + } return -1; } @@ -136,25 +150,23 @@ static int ethosu_zephyr_init(const struct device *dev) return 0; } -#define ETHOSU_DEVICE_INIT(n) \ - static struct ethosu_data ethosu_data_##n; \ - \ - static void ethosu_zephyr_irq_config_##n(void) \ - { \ - IRQ_CONNECT(DT_INST_IRQN(n), \ - DT_INST_IRQ(n, priority), \ - ethosu_zephyr_irq_handler, \ - DEVICE_DT_INST_GET(n), 0); \ - irq_enable(DT_INST_IRQN(n)); \ - } \ - \ - static const struct ethosu_dts_info ethosu_dts_info_##n = { \ - .base_addr = (void *)DT_INST_REG_ADDR(n), \ - .secure_enable = DT_INST_PROP(n, secure_enable), \ - .privilege_enable = DT_INST_PROP(n, privilege_enable), \ - .irq_config = ðosu_zephyr_irq_config_##n, \ - }; \ - \ +#define ETHOSU_DEVICE_INIT(n) \ + static struct ethosu_data ethosu_data_##n; \ + \ + static void ethosu_zephyr_irq_config_##n(void) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), ethosu_zephyr_irq_handler, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + } \ + \ + static const struct ethosu_dts_info ethosu_dts_info_##n = { \ + .base_addr = (void *)DT_INST_REG_ADDR(n), \ + .secure_enable = DT_INST_PROP(n, secure_enable), \ + .privilege_enable = DT_INST_PROP(n, privilege_enable), \ + .irq_config = ðosu_zephyr_irq_config_##n, \ + }; \ + \ DEVICE_DT_INST_DEFINE(n, ethosu_zephyr_init, NULL, ðosu_data_##n, ðosu_dts_info_##n, \ POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, NULL); diff --git a/west.yml b/west.yml index 6d9f3fa1481..a1dddf9308d 100644 --- a/west.yml +++ b/west.yml @@ -158,7 +158,7 @@ manifest: groups: - hal - name: hal_ethos_u - revision: 90ada2ea5681b2a2722a10d2898eac34c2510791 + revision: 8e2cf756b474eff9a32a9bdf1775d9620f1eadcf path: modules/hal/ethos_u groups: - hal From 2fff293cc7d32e2eb9fbf742b8d4ec284083ecc5 Mon Sep 17 00:00:00 2001 From: Ledion Daja Date: Wed, 31 Jan 2024 16:53:44 +0100 Subject: [PATCH 1106/2402] modules: hal_ethos_u: fix log configuration in CMake file The core driver ETHOSU_LOG_SEVERITY CMake variable is a cache variable, and thus will not be configured by the ETHOSU_LOG_SEVERITY CMake variable of the hal_ethos_u module with local scope. Change ETHOSU_LOG_SEVERITY local variable to be a cache var. In addition, change condition test from LESS_EQUAL to LESS in order to prevent an out-of-range index when accessing list variable. Signed-off-by: Ledion Daja --- modules/hal_ethos_u/CMakeLists.txt | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/modules/hal_ethos_u/CMakeLists.txt b/modules/hal_ethos_u/CMakeLists.txt index 5933ccd73b4..56455a21076 100644 --- a/modules/hal_ethos_u/CMakeLists.txt +++ b/modules/hal_ethos_u/CMakeLists.txt @@ -1,5 +1,5 @@ -# Copyright 2022 Arm Limited and/or its affiliates -# +# SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its +# affiliates # SPDX-License-Identifier: Apache-2.0 if(CONFIG_ARM_ETHOS_U AND CONFIG_MULTITHREADING) @@ -10,10 +10,11 @@ if(CONFIG_ARM_ETHOS_U AND CONFIG_MULTITHREADING) set(ETHOSU_LOG_SEVERITY_MAP err err warning info debug) list(LENGTH ETHOSU_LOG_SEVERITY_MAP ETHOSU_LOG_SEVERITY_MAP_LENGTH) - if ("${CONFIG_ARM_ETHOS_U_LOG_LEVEL}" LESS_EQUAL "${ETHOSU_LOG_SEVERITY_MAP_LENGTH}") + if (${CONFIG_ARM_ETHOS_U_LOG_LEVEL} LESS "${ETHOSU_LOG_SEVERITY_MAP_LENGTH}") list(GET ETHOSU_LOG_SEVERITY_MAP ${CONFIG_ARM_ETHOS_U_LOG_LEVEL} ETHOSU_LOG_SEVERITY) + set(ETHOSU_LOG_SEVERITY ${ETHOSU_LOG_SEVERITY} CACHE STRING "") else() - set(ETHOSU_LOG_SEVERITY debug) + set(ETHOSU_LOG_SEVERITY debug CACHE STRING "") endif() add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR} ethos-u-core-driver) From 93af8754ecc0d0b19b55b3b2f7cb0f5e61e57284 Mon Sep 17 00:00:00 2001 From: Ledion Daja Date: Thu, 1 Feb 2024 08:32:04 +0100 Subject: [PATCH 1107/2402] modules: hal_ethos_u: add support for log level NONE Add support for log level NONE by disabling Ethos-U driver logging. Signed-off-by: Ledion Daja --- modules/hal_ethos_u/CMakeLists.txt | 5 ++++- modules/hal_ethos_u/Kconfig | 8 ++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/modules/hal_ethos_u/CMakeLists.txt b/modules/hal_ethos_u/CMakeLists.txt index 56455a21076..9de47e4457b 100644 --- a/modules/hal_ethos_u/CMakeLists.txt +++ b/modules/hal_ethos_u/CMakeLists.txt @@ -10,7 +10,10 @@ if(CONFIG_ARM_ETHOS_U AND CONFIG_MULTITHREADING) set(ETHOSU_LOG_SEVERITY_MAP err err warning info debug) list(LENGTH ETHOSU_LOG_SEVERITY_MAP ETHOSU_LOG_SEVERITY_MAP_LENGTH) - if (${CONFIG_ARM_ETHOS_U_LOG_LEVEL} LESS "${ETHOSU_LOG_SEVERITY_MAP_LENGTH}") + if (${CONFIG_ARM_ETHOS_U_LOG_LEVEL} EQUAL 0) + # The Ethos-U driver does not have a corresponding "none" log level. Disable logging instead. + set(ETHOSU_LOG_ENABLE OFF CACHE BOOL "") + elseif (${CONFIG_ARM_ETHOS_U_LOG_LEVEL} LESS "${ETHOSU_LOG_SEVERITY_MAP_LENGTH}") list(GET ETHOSU_LOG_SEVERITY_MAP ${CONFIG_ARM_ETHOS_U_LOG_LEVEL} ETHOSU_LOG_SEVERITY) set(ETHOSU_LOG_SEVERITY ${ETHOSU_LOG_SEVERITY} CACHE STRING "") else() diff --git a/modules/hal_ethos_u/Kconfig b/modules/hal_ethos_u/Kconfig index ddb2d0a8ed6..2c442de51a6 100644 --- a/modules/hal_ethos_u/Kconfig +++ b/modules/hal_ethos_u/Kconfig @@ -1,5 +1,5 @@ -# Copyright 2021-2022 Arm Limited and/or its affiliates -# +# SPDX-FileCopyrightText: Copyright 2021-2022, 2024 Arm Limited and/or its +# affiliates # SPDX-License-Identifier: Apache-2.0 config ARM_ETHOS_U @@ -45,6 +45,9 @@ choice "ARM_ETHOS_U_LOG_LEVEL_CHOICE" default ARM_ETHOS_U_LOG_LEVEL_WRN depends on STDOUT_CONSOLE +config ARM_ETHOS_U_LOG_LEVEL_NONE + bool "None" + config ARM_ETHOS_U_LOG_LEVEL_ERR bool "Error" @@ -65,6 +68,7 @@ endchoice config ARM_ETHOS_U_LOG_LEVEL int depends on STDOUT_CONSOLE + default 0 if ARM_ETHOS_U_LOG_LEVEL_NONE default 1 if ARM_ETHOS_U_LOG_LEVEL_ERR default 2 if ARM_ETHOS_U_LOG_LEVEL_WRN default 3 if ARM_ETHOS_U_LOG_LEVEL_INF From 6608ff810be95294114352d848dbefb9a234f4dd Mon Sep 17 00:00:00 2001 From: Piotr Pryga Date: Thu, 7 Mar 2024 14:47:23 +0100 Subject: [PATCH 1108/2402] boards: nordic: Add to GRTC missing child-owned-channels allocation The child-owned-channels property of GRTC is used by nrfx_grtc driver to exclude channels for common pool of channels allowed for dynamic allocation. That is sort-of workaround for missing property that allowes to remove some channels from the pool. There are also not aligned GRTC IRQs for nRF54H20 and nRF54L15. Only one of avaialbe IRQs was added to GRTC in DTS whereas there should be two. That allows to find second IRQ by other drivers that use GRTC peripehral. Signed-off-by: Piotr Pryga --- boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts | 2 -- dts/arm/nordic/nrf54h20_cpurad.dtsi | 3 ++- dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi | 4 +++- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index 1998f4fc131..fd65d2d495a 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -61,8 +61,6 @@ &grtc { status = "okay"; child-owned-channels = <8 9 10 11 12>; - interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>, - <108 NRF_DEFAULT_IRQ_PRIORITY>; nonsecure-channels = <8 9 10 11 12>; owned-channels = <7 8 9 10 11 12 13 14>; }; diff --git a/dts/arm/nordic/nrf54h20_cpurad.dtsi b/dts/arm/nordic/nrf54h20_cpurad.dtsi index 2f463f2d427..7b7f236de0c 100644 --- a/dts/arm/nordic/nrf54h20_cpurad.dtsi +++ b/dts/arm/nordic/nrf54h20_cpurad.dtsi @@ -47,5 +47,6 @@ cpuppr_vevif: &cpuppr_vevif_remote {}; }; &grtc { - interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>; + interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>, + <108 NRF_DEFAULT_IRQ_PRIORITY>; }; diff --git a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi index 485d85829a4..25f94241336 100644 --- a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi +++ b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi @@ -330,7 +330,9 @@ grtc: grtc@e2000 { reg = <0xe2000 0x1000>; cc-num = <12>; owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; - interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>; + child-owned-channels = <7 8 9 10 11>; + interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>, + <229 NRF_DEFAULT_IRQ_PRIORITY>; status = "disabled"; }; From 4afd33570ec2f3d4b03a3d4f3112c6cfa39433a7 Mon Sep 17 00:00:00 2001 From: Jordan Yates Date: Fri, 15 Mar 2024 20:45:58 +1000 Subject: [PATCH 1109/2402] logging: log: add `LOG_WRN_ONCE` Add an equivalent to the linux `WARN_ONCE` macro. This is intended for use when the developer should be notified of an event, but may occur a multitude of times in quick succession. Using `LOG_WRN` could result in either cluttered logs or recursive logging (i.e. in serial drivers). Signed-off-by: Jordan Yates --- include/zephyr/logging/log.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/zephyr/logging/log.h b/include/zephyr/logging/log.h index 3baba971dc6..c31d0667ef3 100644 --- a/include/zephyr/logging/log.h +++ b/include/zephyr/logging/log.h @@ -74,6 +74,24 @@ extern "C" { */ #define LOG_DBG(...) Z_LOG(LOG_LEVEL_DBG, __VA_ARGS__) +/** + * @brief Writes a WARNING level message to the log on the first execution only. + * + * @details It's meant for situations that warrant investigation but could clutter + * the logs if output on every execution. + * + * @param ... A string optionally containing printk valid conversion specifier, + * followed by as many values as specifiers. + */ +#define LOG_WRN_ONCE(...) \ + do { \ + static uint8_t __warned; \ + if (unlikely(__warned == 0)) { \ + Z_LOG(LOG_LEVEL_WRN, __VA_ARGS__); \ + __warned = 1; \ + } \ + } while (0) + /** * @brief Unconditionally print raw log message. * From 61ee9f4fbf59ff79914ee1c13a7b35566a8dd6b4 Mon Sep 17 00:00:00 2001 From: Jordan Yates Date: Fri, 15 Mar 2024 20:53:13 +1000 Subject: [PATCH 1110/2402] tests: logging: log_api: test `LOG_WRN_ONCE` Add a test for the `LOG_WRN_ONCE` wrapper around `LOG_WRN`. Signed-off-by: Jordan Yates --- tests/subsys/logging/log_api/src/main.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/tests/subsys/logging/log_api/src/main.c b/tests/subsys/logging/log_api/src/main.c index 1de5180f239..5c0a9930054 100644 --- a/tests/subsys/logging/log_api/src/main.c +++ b/tests/subsys/logging/log_api/src/main.c @@ -797,6 +797,29 @@ ZTEST(test_log_api, test_log_arg_evaluation) #undef TEST_MSG_0_PREFIX } +static void log_wrn_once_run(int i) +{ + LOG_WRN_ONCE("once %d", i); +} + +ZTEST(test_log_api, test_log_wrn_once) +{ + log_timestamp_t exp_timestamp = TIMESTAMP_INIT_VAL; + + log_setup(false); + + mock_log_frontend_record(LOG_CURRENT_MODULE_ID(), LOG_LEVEL_WRN, "once 0"); + mock_log_backend_record(&backend1, LOG_CURRENT_MODULE_ID(), + Z_LOG_LOCAL_DOMAIN_ID, LOG_LEVEL_WRN, + exp_timestamp++, "once 0"); + + log_wrn_once_run(0); + log_wrn_once_run(1); + log_wrn_once_run(2); + + process_and_validate(false, false); +} + ZTEST(test_log_api, test_log_override_level) { log_timestamp_t exp_timestamp = TIMESTAMP_INIT_VAL; From ca36feeca8e6c9414a8dd88e1c8121929f7e946d Mon Sep 17 00:00:00 2001 From: Jordan Yates Date: Fri, 15 Mar 2024 20:58:08 +1000 Subject: [PATCH 1111/2402] doc: logging: document `LOG_WRN_ONCE` Document the existence of `LOG_WRN_ONCE`. Signed-off-by: Jordan Yates --- doc/services/logging/index.rst | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/doc/services/logging/index.rst b/doc/services/logging/index.rst index 8d8448abf6b..9e54f8d4da8 100644 --- a/doc/services/logging/index.rst +++ b/doc/services/logging/index.rst @@ -46,7 +46,7 @@ There are four severity levels available in the system: error, warning, info and debug. For each severity level the logging API (:zephyr_file:`include/zephyr/logging/log.h`) has set of dedicated macros. Logger API also has macros for logging data. -For each level following set of macros are available: +For each level the following set of macros are available: - ``LOG_X`` for standard printf-like messages, e.g. :c:macro:`LOG_ERR`. - ``LOG_HEXDUMP_X`` for dumping data, e.g. :c:macro:`LOG_HEXDUMP_WRN`. @@ -55,6 +55,10 @@ For each level following set of macros are available: - ``LOG_INST_HEXDUMP_X`` for dumping data associated with the particular instance, e.g. :c:macro:`LOG_HEXDUMP_INST_DBG` +The warning level also exposes the following additional macro: + +- :c:macro:`LOG_WRN_ONCE` for warnings where only the first occurrence is of interest. + There are two configuration categories: configurations per module and global configuration. When logging is enabled globally, it works for modules. However, modules can disable logging locally. Every module can specify its own logging From adedf14c42594d167cb8f12855f7ae6097e285f1 Mon Sep 17 00:00:00 2001 From: Mehdi Zemzem Date: Tue, 19 Mar 2024 09:55:28 +0100 Subject: [PATCH 1112/2402] drivers: flash: spi nor: Add MultInstance support Modify the SPI Nor driver to be able to have multiple instances at the same time. This patch is heavily inspired by the at45 driver. It was tested on the nRF5340 DK by using the external spi memory two times. Macros were improved by de-nordic Signed-off-by: Mehdi Zemzem --- drivers/flash/spi_nor.c | 607 +++++++++++++++++++++++----------------- drivers/flash/spi_nor.h | 2 + 2 files changed, 356 insertions(+), 253 deletions(-) diff --git a/drivers/flash/spi_nor.c b/drivers/flash/spi_nor.c index 065795d4924..b30dd171b9b 100644 --- a/drivers/flash/spi_nor.c +++ b/drivers/flash/spi_nor.c @@ -48,36 +48,43 @@ LOG_MODULE_REGISTER(spi_nor, CONFIG_FLASH_LOG_LEVEL); #define SPI_NOR_MAX_ADDR_WIDTH 4 -#if DT_INST_NODE_HAS_PROP(0, t_enter_dpd) -#define T_DP_MS DIV_ROUND_UP(DT_INST_PROP(0, t_enter_dpd), NSEC_PER_MSEC) -#else /* T_ENTER_DPD */ -#define T_DP_MS 0 -#endif /* T_ENTER_DPD */ -#if DT_INST_NODE_HAS_PROP(0, t_exit_dpd) -#define T_RES1_MS DIV_ROUND_UP(DT_INST_PROP(0, t_exit_dpd), NSEC_PER_MSEC) -#endif /* T_EXIT_DPD */ -#if DT_INST_NODE_HAS_PROP(0, dpd_wakeup_sequence) -#define T_DPDD_MS DIV_ROUND_UP(DT_INST_PROP_BY_IDX(0, dpd_wakeup_sequence, 0), NSEC_PER_MSEC) -#define T_CRDP_MS DIV_ROUND_UP(DT_INST_PROP_BY_IDX(0, dpd_wakeup_sequence, 1), NSEC_PER_MSEC) -#define T_RDP_MS DIV_ROUND_UP(DT_INST_PROP_BY_IDX(0, dpd_wakeup_sequence, 2), NSEC_PER_MSEC) -#else /* DPD_WAKEUP_SEQUENCE */ -#define T_DPDD_MS 0 -#endif /* DPD_WAKEUP_SEQUENCE */ -#define _INST_HAS_WP_OR(inst) DT_INST_NODE_HAS_PROP(inst, wp_gpios) || -#define ANY_INST_HAS_WP_GPIOS DT_INST_FOREACH_STATUS_OKAY(_INST_HAS_WP_OR) 0 +#define ANY_INST_HAS_TRUE_(idx, bool_prop) \ + COND_CODE_1(DT_INST_PROP(idx, bool_prop), (1,), ()) + +#define ANY_INST_HAS_TRUE(bool_prop) \ + COND_CODE_1(IS_EMPTY(DT_INST_FOREACH_STATUS_OKAY_VARGS(ANY_INST_HAS_TRUE_, bool_prop)), \ + (0), (1)) + +#define ANY_INST_HAS_PROP_(idx, prop_name) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, prop_name), (1,), ()) +#define ANY_INST_HAS_PROP(prop_name) \ + COND_CODE_1(IS_EMPTY(DT_INST_FOREACH_STATUS_OKAY_VARGS(ANY_INST_HAS_PROP_, prop_name)), \ + (0), (1)) -#define _INST_HAS_HOLD_OR(inst) DT_INST_NODE_HAS_PROP(inst, hold_gpios) || -#define ANY_INST_HAS_HOLD_GPIOS DT_INST_FOREACH_STATUS_OKAY(_INST_HAS_HOLD_OR) 0 +#define ANY_INST_HAS_MXICY_MX25R_POWER_MODE ANY_INST_HAS_PROP(mxicy_mx25r_power_mode) +#define ANY_INST_HAS_DPD ANY_INST_HAS_TRUE(has_dpd) +#define ANY_INST_HAS_T_EXIT_DPD ANY_INST_HAS_PROP(t_exit_dpd) +#define ANY_INST_HAS_DPD_WAKEUP_SEQUENCE ANY_INST_HAS_PROP(dpd_wakeup_sequence) +#define ANY_INST_HAS_RESET_GPIOS ANY_INST_HAS_PROP(reset_gpios) +#define ANY_INST_HAS_WP_GPIOS ANY_INST_HAS_PROP(wp_gpios) +#define ANY_INST_HAS_HOLD_GPIOS ANY_INST_HAS_PROP(hold_gpios) #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config) +/* MXICY Related defines*/ +/* MXICY Low-power/high perf mode is second bit in configuration register 2 */ +#define LH_SWITCH_BIT 9 + +#define JEDEC_MACRONIX_ID 0xc2 +#define JEDEC_MX25R_TYPE_ID 0x28 + /* Build-time data associated with the device. */ struct spi_nor_config { /* Devicetree SPI configuration */ struct spi_dt_spec spi; -#if DT_INST_NODE_HAS_PROP(0, reset_gpios) +#if ANY_INST_HAS_RESET_GPIOS const struct gpio_dt_spec reset; #endif @@ -119,12 +126,40 @@ struct spi_nor_config { #if ANY_INST_HAS_WP_GPIOS /* The write-protect GPIO (wp-gpios) */ - const struct gpio_dt_spec *wp; + const struct gpio_dt_spec wp; #endif + #if ANY_INST_HAS_HOLD_GPIOS /* The hold GPIO (hold-gpios) */ - const struct gpio_dt_spec *hold; + const struct gpio_dt_spec hold; +#endif + +#if ANY_INST_HAS_DPD + uint16_t t_enter_dpd; /* in microseconds */ + uint16_t t_dpdd_ms; /* in microseconds */ +#if ANY_INST_HAS_T_EXIT_DPD + uint16_t t_exit_dpd; /* in microseconds */ +#endif +#endif + +#if ANY_INST_HAS_DPD_WAKEUP_SEQUENCE + uint16_t t_crdp_ms; /* in microseconds */ + uint16_t t_rdp_ms; /* in microseconds */ #endif + +#if ANY_INST_HAS_MXICY_MX25R_POWER_MODE + bool mxicy_mx25r_power_mode; +#endif + + /* exist flags for dts opt-ins */ + bool dpd_exist:1; + bool dpd_wakeup_sequence_exist:1; + bool mxicy_mx25r_power_mode_exist:1; + bool enter_4byte_addr_exist:1; + bool reset_gpios_exist:1; + bool requires_ulbpr_exist:1; + bool wp_gpios_exist:1; + bool hold_gpios_exist:1; }; /** @@ -133,7 +168,7 @@ struct spi_nor_config { */ struct spi_nor_data { struct k_sem sem; -#if DT_INST_NODE_HAS_PROP(0, has_dpd) +#if ANY_INST_HAS_DPD /* Low 32-bits of uptime counter at which device last entered * deep power-down. */ @@ -249,10 +284,16 @@ static const struct flash_parameters flash_nor_parameters = { /* Capture the time at which the device entered deep power-down. */ static inline void record_entered_dpd(const struct device *const dev) { -#if DT_INST_NODE_HAS_PROP(0, has_dpd) - struct spi_nor_data *const driver_data = dev->data; +#if ANY_INST_HAS_DPD + const struct spi_nor_config *const driver_config = dev->config; - driver_data->ts_enter_dpd = k_uptime_get_32(); + if (driver_config->dpd_exist) { + struct spi_nor_data *const driver_data = dev->data; + + driver_data->ts_enter_dpd = k_uptime_get_32(); + } +#else + ARG_UNUSED(dev); #endif } @@ -261,31 +302,37 @@ static inline void record_entered_dpd(const struct device *const dev) */ static inline void delay_until_exit_dpd_ok(const struct device *const dev) { -#if DT_INST_NODE_HAS_PROP(0, has_dpd) - struct spi_nor_data *const driver_data = dev->data; - int32_t since = (int32_t)(k_uptime_get_32() - driver_data->ts_enter_dpd); - - /* If the time is negative the 32-bit counter has wrapped, - * which is certainly long enough no further delay is - * required. Otherwise we have to check whether it's been - * long enough taking into account necessary delays for - * entering and exiting DPD. - */ - if (since >= 0) { - /* Subtract time required for DPD to be reached */ - since -= T_DP_MS; +#if ANY_INST_HAS_DPD + const struct spi_nor_config *const driver_config = dev->config; - /* Subtract time required in DPD before exit */ - since -= T_DPDD_MS; + if (driver_config->dpd_exist) { + struct spi_nor_data *const driver_data = dev->data; + int32_t since = (int32_t)(k_uptime_get_32() - driver_data->ts_enter_dpd); - /* If the adjusted time is negative we have to wait - * until it reaches zero before we can proceed. + /* If the time is negative the 32-bit counter has wrapped, + * which is certainly long enough no further delay is + * required. Otherwise we have to check whether it's been + * long enough taking into account necessary delays for + * entering and exiting DPD. */ - if (since < 0) { - k_sleep(K_MSEC((uint32_t)-since)); + if (since >= 0) { + /* Subtract time required for DPD to be reached */ + since -= driver_config->t_enter_dpd; + + /* Subtract time required in DPD before exit */ + since -= driver_config->t_dpdd_ms; + + /* If the adjusted time is negative we have to wait + * until it reaches zero before we can proceed. + */ + if (since < 0) { + k_sleep(K_MSEC((uint32_t)-since)); + } } } -#endif /* DT_INST_NODE_HAS_PROP(0, has_dpd) */ +#else + ARG_UNUSED(dev); +#endif /* ANY_INST_HAS_DPD */ } /* Indicates that an access command includes bytes for the address. @@ -455,8 +502,10 @@ static int read_sfdp(const struct device *const dev, static int enter_dpd(const struct device *const dev) { int ret = 0; + const struct spi_nor_config *cfg = dev->config; - if (IS_ENABLED(DT_INST_PROP(0, has_dpd))) { + ARG_UNUSED(cfg); + if (cfg->dpd_exist) { ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_DPD); if (ret == 0) { record_entered_dpd(dev); @@ -468,29 +517,34 @@ static int enter_dpd(const struct device *const dev) static int exit_dpd(const struct device *const dev) { int ret = 0; + const struct spi_nor_config *cfg = dev->config; - if (IS_ENABLED(DT_INST_PROP(0, has_dpd))) { + if (cfg->dpd_exist) { delay_until_exit_dpd_ok(dev); -#if DT_INST_NODE_HAS_PROP(0, dpd_wakeup_sequence) - /* Assert CSn and wait for tCRDP. - * - * Unfortunately the SPI API doesn't allow us to - * control CSn so fake it by writing a known-supported - * single-byte command, hoping that'll hold the assert - * long enough. This is highly likely, since the - * duration is usually less than two SPI clock cycles. - */ - ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_RDID); +#if ANY_INST_HAS_DPD_WAKEUP_SEQUENCE + if (cfg->dpd_wakeup_sequence_exist) { + /* Assert CSn and wait for tCRDP. + * + * Unfortunately the SPI API doesn't allow us to + * control CSn so fake it by writing a known-supported + * single-byte command, hoping that'll hold the assert + * long enough. This is highly likely, since the + * duration is usually less than two SPI clock cycles. + */ + ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_RDID); - /* Deassert CSn and wait for tRDP */ - k_sleep(K_MSEC(T_RDP_MS)); -#else /* DPD_WAKEUP_SEQUENCE */ - ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_RDPD); + /* Deassert CSn and wait for tRDP */ + k_sleep(K_MSEC(cfg->t_rdp_ms)); + } else { + ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_RDPD); - if (ret == 0) { -#if DT_INST_NODE_HAS_PROP(0, t_exit_dpd) - k_sleep(K_MSEC(T_RES1_MS)); +#if ANY_INST_HAS_T_EXIT_DPD + if (ret == 0) { + if (cfg->dpd_exist) { + k_sleep(K_MSEC(cfg->t_exit_dpd)); + } + } #endif /* T_EXIT_DPD */ } #endif /* DPD_WAKEUP_SEQUENCE */ @@ -581,7 +635,7 @@ static int spi_nor_wrsr(const struct device *dev, return ret; } -#if DT_INST_NODE_HAS_PROP(0, mxicy_mx25r_power_mode) +#if ANY_INST_HAS_MXICY_MX25R_POWER_MODE /** * @brief Read the configuration register. @@ -595,12 +649,15 @@ static int spi_nor_wrsr(const struct device *dev, */ static int mxicy_rdcr(const struct device *dev) { - uint16_t cr; - enum { CMD_RDCR = 0x15 }; - int ret = spi_nor_cmd_read(dev, CMD_RDCR, &cr, sizeof(cr)); + const struct spi_nor_config *cfg = dev->config; + uint16_t cr = -ENOSYS; + + if (cfg->mxicy_mx25r_power_mode_exist) { + int ret = spi_nor_cmd_read(dev, CMD_RDCR, &cr, sizeof(cr)); - if (ret < 0) { - return ret; + if (ret < 0) { + return ret; + } } return cr; @@ -620,30 +677,35 @@ static int mxicy_rdcr(const struct device *dev) static int mxicy_wrcr(const struct device *dev, uint16_t cr) { + const struct spi_nor_config *cfg = dev->config; + int ret = -ENOSYS; /* The configuration register bytes on the Macronix MX25R devices are * written using the Write Status Register command where the configuration * register bytes are written as two extra bytes after the status register. * First read out the current status register to preserve the value. */ - int sr = spi_nor_rdsr(dev); - if (sr < 0) { - LOG_ERR("Read status register failed: %d", sr); - return sr; - } + if (cfg->mxicy_mx25r_power_mode_exist) { + int sr = spi_nor_rdsr(dev); - int ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_WREN); + if (sr < 0) { + LOG_ERR("Read status register failed: %d", sr); + return sr; + } - if (ret == 0) { - uint8_t data[] = { - sr, - cr & 0xFF, /* Configuration register 1 */ - cr >> 8 /* Configuration register 2 */ - }; + ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_WREN); - ret = spi_nor_access(dev, SPI_NOR_CMD_WRSR, NOR_ACCESS_WRITE, 0, data, - sizeof(data)); - spi_nor_wait_until_ready(dev, WAIT_READY_REGISTER); + if (ret == 0) { + uint8_t data[] = { + sr, + cr & 0xFF, /* Configuration register 1 */ + cr >> 8 /* Configuration register 2 */ + }; + + ret = spi_nor_access(dev, SPI_NOR_CMD_WRSR, NOR_ACCESS_WRITE, 0, + data, sizeof(data)); + spi_nor_wait_until_ready(dev, WAIT_READY_REGISTER); + } } return ret; @@ -651,55 +713,57 @@ static int mxicy_wrcr(const struct device *dev, static int mxicy_configure(const struct device *dev, const uint8_t *jedec_id) { - /* Low-power/high perf mode is second bit in configuration register 2 */ - enum { LH_SWITCH_BIT = 9 }; - const uint8_t JEDEC_MACRONIX_ID = 0xc2; - const uint8_t JEDEC_MX25R_TYPE_ID = 0x28; - int current_cr, new_cr, ret; - /* lh_switch enum index: - * 0: Ultra low power - * 1: High performance mode - */ - const bool use_high_perf = DT_INST_ENUM_IDX(0, mxicy_mx25r_power_mode); + const struct spi_nor_config *cfg = dev->config; + int ret = -ENOSYS; + + if (cfg->mxicy_mx25r_power_mode_exist) { + /* Low-power/high perf mode is second bit in configuration register 2 */ + int current_cr, new_cr; + /* lh_switch enum index: + * 0: Ultra low power + * 1: High performance mode + */ + const bool use_high_perf = cfg->mxicy_mx25r_power_mode; + + /* Only supported on Macronix MX25R Ultra Low Power series. */ + if (jedec_id[0] != JEDEC_MACRONIX_ID || jedec_id[1] != JEDEC_MX25R_TYPE_ID) { + LOG_WRN("L/H switch not supported for device id: %02x %02x %02x", + jedec_id[0], jedec_id[1], jedec_id[2]); + /* Do not return an error here because the flash still functions */ + return 0; + } - /* Only supported on Macronix MX25R Ultra Low Power series. */ - if (jedec_id[0] != JEDEC_MACRONIX_ID || jedec_id[1] != JEDEC_MX25R_TYPE_ID) { - LOG_WRN("L/H switch not supported for device id: %02x %02x %02x", jedec_id[0], - jedec_id[1], jedec_id[2]); - /* Do not return an error here because the flash still functions */ - return 0; - } + acquire_device(dev); - acquire_device(dev); + /* Read current configuration register */ + + ret = mxicy_rdcr(dev); + if (ret < 0) { + release_device(dev); + return ret; + } + current_cr = ret; - /* Read current configuration register */ + LOG_DBG("Use high performance mode? %d", use_high_perf); + new_cr = current_cr; + WRITE_BIT(new_cr, LH_SWITCH_BIT, use_high_perf); + if (new_cr != current_cr) { + ret = mxicy_wrcr(dev, new_cr); + } else { + ret = 0; + } - ret = mxicy_rdcr(dev); - if (ret < 0) { - release_device(dev); - return ret; - } - current_cr = ret; - - LOG_DBG("Use high performance mode? %d", use_high_perf); - new_cr = current_cr; - WRITE_BIT(new_cr, LH_SWITCH_BIT, use_high_perf); - if (new_cr != current_cr) { - ret = mxicy_wrcr(dev, new_cr); - } else { - ret = 0; - } + if (ret < 0) { + LOG_ERR("Enable high performace mode failed: %d", ret); + } - if (ret < 0) { - LOG_ERR("Enable high performace mode failed: %d", ret); + release_device(dev); } - release_device(dev); - return ret; } -#endif /* DT_INST_NODE_HAS_PROP(0, mxicy_mx25r_power_mode) */ +#endif /* ANY_INST_HAS_MXICY_MX25R_POWER_MODE */ static int spi_nor_read(const struct device *dev, off_t addr, void *dest, size_t size) @@ -892,25 +956,27 @@ static int spi_nor_write_protection_set(const struct device *dev, bool write_protect) { int ret; + const struct spi_nor_config *cfg = dev->config; #if ANY_INST_HAS_WP_GPIOS - if (DEV_CFG(dev)->wp && write_protect == false) { - gpio_pin_set_dt(DEV_CFG(dev)->wp, 0); + if (DEV_CFG(dev)->wp_gpios_exist && write_protect == false) { + gpio_pin_set_dt(&(DEV_CFG(dev)->wp), 0); } #endif + ARG_UNUSED(cfg); ret = spi_nor_cmd_write(dev, (write_protect) ? SPI_NOR_CMD_WRDI : SPI_NOR_CMD_WREN); - if (IS_ENABLED(DT_INST_PROP(0, requires_ulbpr)) + if (cfg->requires_ulbpr_exist && (ret == 0) && !write_protect) { ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_ULBPR); } #if ANY_INST_HAS_WP_GPIOS - if (DEV_CFG(dev)->wp && write_protect == true) { - gpio_pin_set_dt(DEV_CFG(dev)->wp, 1); + if (DEV_CFG(dev)->wp_gpios_exist && write_protect == true) { + gpio_pin_set_dt(&(DEV_CFG(dev)->wp), 1); } #endif @@ -970,8 +1036,10 @@ static int spi_nor_read_jedec_id(const struct device *dev, static int spi_nor_set_address_mode(const struct device *dev, uint8_t enter_4byte_addr) { - int ret = 0; + const struct spi_nor_config *cfg = dev->config; + int ret = -ENOSYS; + if (cfg->enter_4byte_addr_exist) { /* Do nothing if not provided (either no bits or all bits * set). */ @@ -1006,6 +1074,7 @@ static int spi_nor_set_address_mode(const struct device *dev, } release_device(dev); + } return ret; } @@ -1226,18 +1295,21 @@ static int spi_nor_configure(const struct device *dev) return -ENODEV; } -#if DT_INST_NODE_HAS_PROP(0, reset_gpios) - if (!gpio_is_ready_dt(&cfg->reset)) { - LOG_ERR("Reset pin not ready"); - return -ENODEV; - } - if (gpio_pin_configure_dt(&cfg->reset, GPIO_OUTPUT_ACTIVE)) { - LOG_ERR("Couldn't configure reset pin"); - return -ENODEV; - } - rc = gpio_pin_set_dt(&cfg->reset, 0); - if (rc) { - return rc; +#if ANY_INST_HAS_RESET_GPIOS + + if (cfg->reset_gpios_exist) { + if (!gpio_is_ready_dt(&cfg->reset)) { + LOG_ERR("Reset pin not ready"); + return -ENODEV; + } + if (gpio_pin_configure_dt(&cfg->reset, GPIO_OUTPUT_ACTIVE)) { + LOG_ERR("Couldn't configure reset pin"); + return -ENODEV; + } + rc = gpio_pin_set_dt(&cfg->reset, 0); + if (rc) { + return rc; + } } #endif @@ -1339,10 +1411,12 @@ static int spi_nor_configure(const struct device *dev) #endif /* CONFIG_FLASH_PAGE_LAYOUT */ #endif /* CONFIG_SPI_NOR_SFDP_MINIMAL */ -#if DT_INST_NODE_HAS_PROP(0, mxicy_mx25r_power_mode) +#if ANY_INST_HAS_MXICY_MX25R_POWER_MODE + if (cfg->mxicy_mx25r_power_mode_exist) { /* Do not fail init if setting configuration register fails */ - (void) mxicy_configure(dev, jedec_id); -#endif /* DT_INST_NODE_HAS_PROP(0, mxicy_mx25r_power_mode) */ + (void)mxicy_configure(dev, jedec_id); + } +#endif /* ANY_INST_HAS_MXICY_MX25R_POWER_MODE */ if (IS_ENABLED(CONFIG_SPI_NOR_IDLE_IN_DPD) && (enter_dpd(dev) != 0)) { @@ -1415,24 +1489,24 @@ static int spi_nor_init(const struct device *dev) } #if ANY_INST_HAS_WP_GPIOS - if (DEV_CFG(dev)->wp) { - if (!device_is_ready(DEV_CFG(dev)->wp->port)) { + if (DEV_CFG(dev)->wp_gpios_exist) { + if (!device_is_ready(DEV_CFG(dev)->wp.port)) { LOG_ERR("Write-protect pin not ready"); return -ENODEV; } - if (gpio_pin_configure_dt(DEV_CFG(dev)->wp, GPIO_OUTPUT_ACTIVE)) { + if (gpio_pin_configure_dt(&(DEV_CFG(dev)->wp), GPIO_OUTPUT_ACTIVE)) { LOG_ERR("Write-protect pin failed to set active"); return -ENODEV; } } #endif /* ANY_INST_HAS_WP_GPIOS */ #if ANY_INST_HAS_HOLD_GPIOS - if (DEV_CFG(dev)->hold) { - if (!device_is_ready(DEV_CFG(dev)->hold->port)) { + if (DEV_CFG(dev)->hold_gpios_exist) { + if (!device_is_ready(DEV_CFG(dev)->hold.port)) { LOG_ERR("Hold pin not ready"); return -ENODEV; } - if (gpio_pin_configure_dt(DEV_CFG(dev)->hold, GPIO_OUTPUT_INACTIVE)) { + if (gpio_pin_configure_dt(&(DEV_CFG(dev)->hold), GPIO_OUTPUT_INACTIVE)) { LOG_ERR("Hold pin failed to set inactive"); return -ENODEV; } @@ -1489,117 +1563,144 @@ static const struct flash_driver_api spi_nor_api = { #endif }; -#ifndef CONFIG_SPI_NOR_SFDP_RUNTIME -/* We need to know the size and ID of the configuration data we're - * using so we can disable the device we see at runtime if it isn't - * compatible with what we're taking from devicetree or minimal. - */ -BUILD_ASSERT(DT_INST_NODE_HAS_PROP(0, jedec_id), - "jedec,spi-nor jedec-id required for non-runtime SFDP"); - -#if defined(CONFIG_FLASH_PAGE_LAYOUT) - -/* For devicetree or minimal page layout we need to know the size of - * the device. We can't extract it from the raw BFP data, so require - * it to be present in devicetree. - */ -BUILD_ASSERT(DT_INST_NODE_HAS_PROP(0, size), - "jedec,spi-nor size required for non-runtime SFDP page layout"); - -/* instance 0 size in bytes */ -#define INST_0_BYTES (DT_INST_PROP(0, size) / 8) - -BUILD_ASSERT(SPI_NOR_IS_SECTOR_ALIGNED(CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE), - "SPI_NOR_FLASH_LAYOUT_PAGE_SIZE must be multiple of 4096"); - -/* instance 0 page count */ -#define LAYOUT_PAGES_COUNT (INST_0_BYTES / CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE) - -BUILD_ASSERT((CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE * LAYOUT_PAGES_COUNT) - == INST_0_BYTES, +#define PAGE_LAYOUT_GEN(idx) \ + BUILD_ASSERT(DT_INST_NODE_HAS_PROP(idx, size), \ + "jedec,spi-nor size required for non-runtime SFDP page layout"); \ + enum { \ + INST_##idx##_BYTES = (DT_INST_PROP(idx, size) / 8) \ + }; \ + BUILD_ASSERT(SPI_NOR_IS_SECTOR_ALIGNED(CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE), \ + "SPI_NOR_FLASH_LAYOUT_PAGE_SIZE must be multiple of 4096"); \ + enum { \ + LAYOUT_PAGES_##idx##_COUNT = \ + (INST_##idx##_BYTES / CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE) \ + }; \ + BUILD_ASSERT((CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE * LAYOUT_PAGES_##idx##_COUNT) == \ + INST_##idx##_BYTES, \ "SPI_NOR_FLASH_LAYOUT_PAGE_SIZE incompatible with flash size"); -#endif /* CONFIG_FLASH_PAGE_LAYOUT */ +#define SFDP_BFP_ATTR_GEN(idx) \ + BUILD_ASSERT(DT_INST_NODE_HAS_PROP(idx, sfdp_bfp), \ + "jedec,spi-nor sfdp-bfp required for devicetree SFDP"); \ + static const __aligned(4) uint8_t bfp_##idx##_data[] = DT_INST_PROP(idx, sfdp_bfp); -#ifdef CONFIG_SPI_NOR_SFDP_DEVICETREE -BUILD_ASSERT(DT_INST_NODE_HAS_PROP(0, sfdp_bfp), - "jedec,spi-nor sfdp-bfp required for devicetree SFDP"); +#define INST_ATTR_GEN(idx) \ + BUILD_ASSERT(DT_INST_NODE_HAS_PROP(idx, jedec_id), \ + "jedec,spi-nor jedec-id required for non-runtime SFDP"); \ + IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT, (PAGE_LAYOUT_GEN(idx))) \ + IF_ENABLED(CONFIG_SPI_NOR_SFDP_DEVICETREE, (SFDP_BFP_ATTR_GEN(idx))) -static const __aligned(4) uint8_t bfp_data_0[] = DT_INST_PROP(0, sfdp_bfp); -#endif /* CONFIG_SPI_NOR_SFDP_DEVICETREE */ +#define ATTRIBUTES_DEFINE(idx) COND_CODE_1(CONFIG_SPI_NOR_SFDP_RUNTIME, EMPTY(), \ + (INST_ATTR_GEN(idx))) -#endif /* CONFIG_SPI_NOR_SFDP_RUNTIME */ +#define DEFINE_PAGE_LAYOUT(idx) \ + IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT, \ + (.layout = { \ + .pages_count = LAYOUT_PAGES_##idx##_COUNT, \ + .pages_size = CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE, \ + },)) -#if DT_INST_NODE_HAS_PROP(0, has_lock) -/* Currently we only know of devices where the BP bits are present in - * the first byte of the status register. Complain if that changes. - */ -BUILD_ASSERT(DT_INST_PROP(0, has_lock) == (DT_INST_PROP(0, has_lock) & 0xFF), - "Need support for lock clear beyond SR1"); -#endif +#define INST_HAS_LOCK(idx) DT_INST_NODE_HAS_PROP(idx, has_lock) #define INST_HAS_WP_GPIO(idx) DT_INST_NODE_HAS_PROP(idx, wp_gpios) -#define INST_WP_GPIO_SPEC(idx) \ - IF_ENABLED(INST_HAS_WP_GPIO(idx), (static const struct gpio_dt_spec wp_##idx = \ - GPIO_DT_SPEC_INST_GET(idx, wp_gpios);)) - #define INST_HAS_HOLD_GPIO(idx) DT_INST_NODE_HAS_PROP(idx, hold_gpios) -#define INST_HOLD_GPIO_SPEC(idx) \ - IF_ENABLED(INST_HAS_HOLD_GPIO(idx), (static const struct gpio_dt_spec hold_##idx = \ - GPIO_DT_SPEC_INST_GET(idx, hold_gpios);)) - -INST_WP_GPIO_SPEC(0) -INST_HOLD_GPIO_SPEC(0) - -static const struct spi_nor_config spi_nor_config_0 = { - .spi = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8), - CONFIG_SPI_NOR_CS_WAIT_DELAY), -#if DT_INST_NODE_HAS_PROP(0, reset_gpios) - .reset = GPIO_DT_SPEC_INST_GET(0, reset_gpios), +#define LOCK_DEFINE(idx) \ + IF_ENABLED(INST_HAS_LOCK(idx), (BUILD_ASSERT(DT_INST_PROP(idx, has_lock) == \ + (DT_INST_PROP(idx, has_lock) & 0xFF), \ + "Need support for lock clear beyond SR1");)) + +#define INST_HAS_ENTER_4BYTE_ADDR(idx) DT_INST_NODE_HAS_PROP(idx, enter_4byte_addr) + +#define CONFIGURE_4BYTE_ADDR(idx) \ + IF_ENABLED(INST_HAS_ENTER_4BYTE_ADDR(idx), \ + (.enter_4byte_addr = DT_INST_PROP(idx, enter_4byte_addr),)) + +#define INIT_T_ENTER_DPD(idx) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, t_enter_dpd), \ + (.t_enter_dpd = \ + DIV_ROUND_UP(DT_INST_PROP(idx, t_enter_dpd), NSEC_PER_MSEC)),\ + (.t_enter_dpd = 0)) + +#if ANY_INST_HAS_T_EXIT_DPD +#define INIT_T_EXIT_DPD(idx) \ + COND_CODE_1( \ + DT_INST_NODE_HAS_PROP(idx, t_exit_dpd), \ + (.t_exit_dpd = DIV_ROUND_UP(DT_INST_PROP(idx, t_exit_dpd), NSEC_PER_MSEC)),\ + (.t_exit_dpd = 0)) #endif -#if !defined(CONFIG_SPI_NOR_SFDP_RUNTIME) - -#if defined(CONFIG_FLASH_PAGE_LAYOUT) - .layout = { - .pages_count = LAYOUT_PAGES_COUNT, - .pages_size = CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE, - }, -#undef LAYOUT_PAGES_COUNT -#endif /* CONFIG_FLASH_PAGE_LAYOUT */ - - .flash_size = DT_INST_PROP(0, size) / 8, - .jedec_id = DT_INST_PROP(0, jedec_id), - -#if DT_INST_NODE_HAS_PROP(0, has_lock) - .has_lock = DT_INST_PROP(0, has_lock), -#endif -#if defined(CONFIG_SPI_NOR_SFDP_MINIMAL) \ - && DT_INST_NODE_HAS_PROP(0, enter_4byte_addr) - .enter_4byte_addr = DT_INST_PROP(0, enter_4byte_addr), -#endif -#ifdef CONFIG_SPI_NOR_SFDP_DEVICETREE - .bfp_len = sizeof(bfp_data_0) / 4, - .bfp = (const struct jesd216_bfp *)bfp_data_0, -#endif /* CONFIG_SPI_NOR_SFDP_DEVICETREE */ - -#endif /* CONFIG_SPI_NOR_SFDP_RUNTIME */ - -#if DT_INST_NODE_HAS_PROP(0, wp_gpios) - .wp = &wp_0, -#endif - -#if DT_INST_NODE_HAS_PROP(0, hold_gpios) - .hold = &hold_0, -#endif -}; - -static struct spi_nor_data spi_nor_data_0; - -PM_DEVICE_DT_INST_DEFINE(0, spi_nor_pm_control); -DEVICE_DT_INST_DEFINE(0, &spi_nor_init, PM_DEVICE_DT_INST_GET(0), - &spi_nor_data_0, &spi_nor_config_0, - POST_KERNEL, CONFIG_SPI_NOR_INIT_PRIORITY, - &spi_nor_api); +#define INIT_WP_GPIOS(idx) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, wp_gpios), \ + (.wp = GPIO_DT_SPEC_INST_GET(idx, wp_gpios)), \ + (.wp = {0})) + +#define INIT_HOLD_GPIOS(idx) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, hold_gpios), \ + (.hold = GPIO_DT_SPEC_INST_GET(idx, hold_gpios)), \ + (.hold = {0},)) + +#define INIT_WAKEUP_SEQ_PARAMS(idx) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, dpd_wakeup_sequence), \ + (.t_dpdd_ms = DIV_ROUND_UP( \ + DT_INST_PROP_BY_IDX(idx, dpd_wakeup_sequence, 0), NSEC_PER_MSEC),\ + .t_crdp_ms = DIV_ROUND_UP( \ + DT_INST_PROP_BY_IDX(idx, dpd_wakeup_sequence, 1), NSEC_PER_MSEC),\ + .t_rdp_ms = DIV_ROUND_UP( \ + DT_INST_PROP_BY_IDX(idx, dpd_wakeup_sequence, 2), NSEC_PER_MSEC)),\ + (.t_dpdd_ms = 0, .t_crdp_ms = 0, .t_rdp_ms = 0)) + +#define INIT_MXICY_MX25R_POWER_MODE(idx) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, mxicy_mx25r_power_mode), \ + (.mxicy_mx25r_power_mode = DT_INST_ENUM_IDX(idx, mxicy_mx25r_power_mode)),\ + (.mxicy_mx25r_power_mode = 0)) + +#define INIT_RESET_GPIOS(idx) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, reset_gpios), \ + (.reset = GPIO_DT_SPEC_INST_GET(idx, reset_gpios)), \ + (.reset = {0})) + +#define INST_CONFIG_STRUCT_GEN(idx) \ + DEFINE_PAGE_LAYOUT(idx) \ + .flash_size = DT_INST_PROP(idx, size) / 8, \ + .jedec_id = DT_INST_PROP(idx, jedec_id), \ + .dpd_exist = DT_INST_PROP(idx, has_dpd), \ + .dpd_wakeup_sequence_exist = DT_INST_NODE_HAS_PROP(idx, dpd_wakeup_sequence), \ + .mxicy_mx25r_power_mode_exist = DT_INST_NODE_HAS_PROP(idx, mxicy_mx25r_power_mode), \ + .enter_4byte_addr_exist = DT_INST_NODE_HAS_PROP(idx, enter_4byte_addr), \ + .reset_gpios_exist = DT_INST_NODE_HAS_PROP(idx, reset_gpios), \ + .requires_ulbpr_exist = DT_INST_PROP(idx, requires_ulbpr), \ + .wp_gpios_exist = DT_INST_NODE_HAS_PROP(idx, wp_gpios), \ + .hold_gpios_exist = DT_INST_NODE_HAS_PROP(idx, hold_gpios), \ + IF_ENABLED(INST_HAS_LOCK(idx), (.has_lock = DT_INST_PROP(idx, has_lock),)) \ + IF_ENABLED(CONFIG_SPI_NOR_SFDP_MINIMAL, (CONFIGURE_4BYTE_ADDR(idx))) \ + IF_ENABLED(CONFIG_SPI_NOR_SFDP_DEVICETREE, \ + (.bfp_len = sizeof(bfp_##idx##_data) / 4, \ + .bfp = (const struct jesd216_bfp *)bfp_##idx##_data,)) \ + IF_ENABLED(ANY_INST_HAS_DPD, (INIT_T_ENTER_DPD(idx),)) \ + IF_ENABLED(UTIL_AND(ANY_INST_HAS_DPD, ANY_INST_HAS_T_EXIT_DPD), (INIT_T_EXIT_DPD(idx),))\ + IF_ENABLED(ANY_INST_HAS_DPD_WAKEUP_SEQUENCE, (INIT_WAKEUP_SEQ_PARAMS(idx),)) \ + IF_ENABLED(ANY_INST_HAS_MXICY_MX25R_POWER_MODE, (INIT_MXICY_MX25R_POWER_MODE(idx),)) \ + IF_ENABLED(ANY_INST_HAS_RESET_GPIOS, (INIT_RESET_GPIOS(idx),)) \ + IF_ENABLED(ANY_INST_HAS_WP_GPIOS, (INIT_WP_GPIOS(idx),)) + +#define GENERATE_CONFIG_STRUCT(idx) \ + static const struct spi_nor_config spi_nor_##idx##_config = { \ + .spi = SPI_DT_SPEC_INST_GET(idx, SPI_WORD_SET(8), CONFIG_SPI_NOR_CS_WAIT_DELAY),\ + COND_CODE_1(CONFIG_SPI_NOR_SFDP_RUNTIME, EMPTY(), (INST_CONFIG_STRUCT_GEN(idx)))}; + +#define ASSIGN_PM(idx) \ + PM_DEVICE_DT_INST_DEFINE(idx, spi_nor_pm_control); + +#define SPI_NOR_INST(idx) \ + ASSIGN_PM(idx) \ + ATTRIBUTES_DEFINE(idx) \ + LOCK_DEFINE(idx) \ + GENERATE_CONFIG_STRUCT(idx) \ + static struct spi_nor_data spi_nor_##idx##_data; \ + DEVICE_DT_INST_DEFINE(idx, &spi_nor_init, PM_DEVICE_DT_INST_GET(idx), \ + &spi_nor_##idx##_data, &spi_nor_##idx##_config, \ + POST_KERNEL, CONFIG_SPI_NOR_INIT_PRIORITY, &spi_nor_api); + +DT_INST_FOREACH_STATUS_OKAY(SPI_NOR_INST) diff --git a/drivers/flash/spi_nor.h b/drivers/flash/spi_nor.h index 8d54cc61508..5f38c98289f 100644 --- a/drivers/flash/spi_nor.h +++ b/drivers/flash/spi_nor.h @@ -113,4 +113,6 @@ #define SPI_NOR_IS_32K_ALIGNED(_ofs) SPI_NOR_IS_ALIGNED(_ofs, 15) #define SPI_NOR_IS_64K_ALIGNED(_ofs) SPI_NOR_IS_ALIGNED(_ofs, 16) +#define CMD_RDCR 0x15 /* Read the configuration register. */ + #endif /*__SPI_NOR_H__*/ From 1e2b889bbb6929fe34ea6a81a05fcf29bb8a792b Mon Sep 17 00:00:00 2001 From: Aleksander Wasaznik Date: Fri, 15 Mar 2024 23:24:40 +0100 Subject: [PATCH 1113/2402] Bluetooth: tests: use global testlib in read_fill_buf This deduplicates a copy of testlib from before testlib was a globally available cmake library. Signed-off-by: Aleksander Wasaznik --- .../read_fill_buf/{testlib => }/bs_macro.h | 0 .../att/read_fill_buf/{testlib => }/bs_main.c | 0 .../att/read_fill_buf/client/CMakeLists.txt | 9 +- .../host/att/read_fill_buf/client/main.c | 20 +-- .../att/read_fill_buf/server/CMakeLists.txt | 6 +- .../host/att/read_fill_buf/server/main.c | 4 +- .../host/att/read_fill_buf/testlib/adv.c | 83 ------------ .../host/att/read_fill_buf/testlib/adv.h | 7 - .../host/att/read_fill_buf/testlib/att_read.c | 126 ------------------ .../host/att/read_fill_buf/testlib/att_read.h | 15 --- .../host/att/read_fill_buf/testlib/connect.c | 71 ---------- .../host/att/read_fill_buf/testlib/connect.h | 7 - .../host/att/read_fill_buf/testlib/scan.c | 87 ------------ .../host/att/read_fill_buf/testlib/scan.h | 7 - .../host/att/read_fill_buf/testlib/security.c | 103 -------------- .../host/att/read_fill_buf/testlib/security.h | 7 - 16 files changed, 20 insertions(+), 532 deletions(-) rename tests/bsim/bluetooth/host/att/read_fill_buf/{testlib => }/bs_macro.h (100%) rename tests/bsim/bluetooth/host/att/read_fill_buf/{testlib => }/bs_main.c (100%) delete mode 100644 tests/bsim/bluetooth/host/att/read_fill_buf/testlib/adv.c delete mode 100644 tests/bsim/bluetooth/host/att/read_fill_buf/testlib/adv.h delete mode 100644 tests/bsim/bluetooth/host/att/read_fill_buf/testlib/att_read.c delete mode 100644 tests/bsim/bluetooth/host/att/read_fill_buf/testlib/att_read.h delete mode 100644 tests/bsim/bluetooth/host/att/read_fill_buf/testlib/connect.c delete mode 100644 tests/bsim/bluetooth/host/att/read_fill_buf/testlib/connect.h delete mode 100644 tests/bsim/bluetooth/host/att/read_fill_buf/testlib/scan.c delete mode 100644 tests/bsim/bluetooth/host/att/read_fill_buf/testlib/scan.h delete mode 100644 tests/bsim/bluetooth/host/att/read_fill_buf/testlib/security.c delete mode 100644 tests/bsim/bluetooth/host/att/read_fill_buf/testlib/security.h diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/bs_macro.h b/tests/bsim/bluetooth/host/att/read_fill_buf/bs_macro.h similarity index 100% rename from tests/bsim/bluetooth/host/att/read_fill_buf/testlib/bs_macro.h rename to tests/bsim/bluetooth/host/att/read_fill_buf/bs_macro.h diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/bs_main.c b/tests/bsim/bluetooth/host/att/read_fill_buf/bs_main.c similarity index 100% rename from tests/bsim/bluetooth/host/att/read_fill_buf/testlib/bs_main.c rename to tests/bsim/bluetooth/host/att/read_fill_buf/bs_main.c diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/client/CMakeLists.txt b/tests/bsim/bluetooth/host/att/read_fill_buf/client/CMakeLists.txt index 9c4968f0a09..a384dcbed86 100644 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/client/CMakeLists.txt +++ b/tests/bsim/bluetooth/host/att/read_fill_buf/client/CMakeLists.txt @@ -6,11 +6,7 @@ find_package(Zephyr HINTS $ENV{ZEPHYR_BASE}) project(app) target_sources(app PRIVATE - ../testlib/bs_main.c - ../testlib/scan.c - ../testlib/connect.c - ../testlib/security.c - ../testlib/att_read.c + ../bs_main.c main.c ) @@ -18,3 +14,6 @@ zephyr_include_directories( ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/ ${BSIM_COMPONENTS_PATH}/libUtilv1/src/ ) + +add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/common/testlib testlib) +target_link_libraries(app PRIVATE testlib) diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/client/main.c b/tests/bsim/bluetooth/host/att/read_fill_buf/client/main.c index 0c9906226f1..159ce5cb27d 100644 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/client/main.c +++ b/tests/bsim/bluetooth/host/att/read_fill_buf/client/main.c @@ -10,19 +10,19 @@ #include #include -#include "../common_defs.h" +#include +#include +#include +#include -#include "../testlib/att_read.h" -#include "../testlib/bs_macro.h" -#include "../testlib/connect.h" -#include "../testlib/scan.h" -#include "../testlib/security.h" +#include "../bs_macro.h" +#include "../common_defs.h" LOG_MODULE_REGISTER(client, LOG_LEVEL_DBG); #define BT_LOCAL_ATT_MTU_EATT MIN(BT_L2CAP_SDU_RX_MTU, BT_L2CAP_SDU_TX_MTU) #define BT_LOCAL_ATT_MTU_UATT MIN(BT_L2CAP_RX_MTU, BT_L2CAP_TX_MTU) -#define BT_ATT_BUF_SIZE MAX(BT_LOCAL_ATT_MTU_UATT, BT_LOCAL_ATT_MTU_EATT) +#define BT_ATT_BUF_SIZE MAX(BT_LOCAL_ATT_MTU_UATT, BT_LOCAL_ATT_MTU_EATT) void test_long_read(struct bt_conn *conn, enum bt_att_chan_opt bearer) { @@ -43,20 +43,20 @@ void test_long_read(struct bt_conn *conn, enum bt_att_chan_opt bearer) LOG_INF("ATT_READ_BY_TYPE"); /* Aka. "read by uuid". */ err = bt_testlib_att_read_by_type_sync(&attr_value, &actual_read_len, - &handle, conn, bearer, + &handle, NULL, conn, bearer, MTU_VALIDATION_CHRC, 1, 0xffff); break; case 1: LOG_INF("ATT_READ"); /* Arg `offset == 0`: the stack should choose ATT_READ PDU. */ err = bt_testlib_att_read_by_handle_sync(&attr_value, &actual_read_len, - conn, bearer, handle, 0); + NULL, conn, bearer, handle, 0); break; case 2: LOG_INF("ATT_READ_BLOB"); /* Arg `offset != 0`: the stack should choose ATT_READ_BLOB PDU. */ err = bt_testlib_att_read_by_handle_sync(&attr_value, &actual_read_len, - conn, bearer, handle, 1); + NULL, conn, bearer, handle, 1); break; } diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/server/CMakeLists.txt b/tests/bsim/bluetooth/host/att/read_fill_buf/server/CMakeLists.txt index 663ac0cca51..a384dcbed86 100644 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/server/CMakeLists.txt +++ b/tests/bsim/bluetooth/host/att/read_fill_buf/server/CMakeLists.txt @@ -6,8 +6,7 @@ find_package(Zephyr HINTS $ENV{ZEPHYR_BASE}) project(app) target_sources(app PRIVATE - ../testlib/bs_main.c - ../testlib/adv.c + ../bs_main.c main.c ) @@ -15,3 +14,6 @@ zephyr_include_directories( ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/ ${BSIM_COMPONENTS_PATH}/libUtilv1/src/ ) + +add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/common/testlib testlib) +target_link_libraries(app PRIVATE testlib) diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/server/main.c b/tests/bsim/bluetooth/host/att/read_fill_buf/server/main.c index 9f353b74759..22904c33db5 100644 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/server/main.c +++ b/tests/bsim/bluetooth/host/att/read_fill_buf/server/main.c @@ -8,9 +8,9 @@ #include #include -#include "../testlib/bs_macro.h" -#include "../testlib/adv.h" +#include +#include "../bs_macro.h" #include "../common_defs.h" LOG_MODULE_REGISTER(server, LOG_LEVEL_DBG); diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/adv.c b/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/adv.c deleted file mode 100644 index e67d3bb6fe8..00000000000 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/adv.c +++ /dev/null @@ -1,83 +0,0 @@ -/* Copyright (c) 2023 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct bt_testlib_adv_ctx { - struct bt_conn **result; - struct k_condvar done; -}; - -/* Context pool (with capacity of one). */ -static K_SEM_DEFINE(g_ctx_free, 1, 1); -static K_MUTEX_DEFINE(g_ctx_lock); -static struct bt_testlib_adv_ctx *g_ctx; - -static void connected_cb(struct bt_le_ext_adv *adv, struct bt_le_ext_adv_connected_info *info) -{ - k_mutex_lock(&g_ctx_lock, K_FOREVER); - - if (g_ctx->result) { - *g_ctx->result = bt_conn_ref(info->conn); - } - k_condvar_signal(&g_ctx->done); - - k_mutex_unlock(&g_ctx_lock); -} - -int bt_testlib_adv_conn(struct bt_conn **conn, int id, uint32_t adv_options) -{ - int api_err; - struct bt_le_ext_adv *adv = NULL; - struct bt_le_adv_param param = {}; - struct bt_testlib_adv_ctx ctx = { - .result = conn, - }; - static const struct bt_le_ext_adv_cb cb = { - .connected = connected_cb, - }; - - param.id = id; - param.interval_min = BT_GAP_ADV_FAST_INT_MIN_1; - param.interval_max = BT_GAP_ADV_FAST_INT_MAX_1; - param.options |= BT_LE_ADV_OPT_CONNECTABLE; - param.options |= adv_options; - - k_condvar_init(&ctx.done); - - k_sem_take(&g_ctx_free, K_FOREVER); - k_mutex_lock(&g_ctx_lock, K_FOREVER); - g_ctx = &ctx; - - api_err = bt_le_ext_adv_create(¶m, &cb, &adv); - if (!api_err) { - api_err = bt_le_ext_adv_start(adv, BT_LE_EXT_ADV_START_DEFAULT); - } - - if (!api_err) { - k_condvar_wait(&ctx.done, &g_ctx_lock, K_FOREVER); - } - - /* Delete adv before giving semaphore so that it's potentially available - * for the next taker of the semaphore. - */ - if (adv) { - bt_le_ext_adv_delete(adv); - } - - g_ctx = NULL; - k_mutex_unlock(&g_ctx_lock); - k_sem_give(&g_ctx_free); - - return api_err; -} diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/adv.h b/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/adv.h deleted file mode 100644 index a9d429d5ad2..00000000000 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/adv.h +++ /dev/null @@ -1,7 +0,0 @@ -/* Copyright (c) 2023 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -int bt_testlib_adv_conn(struct bt_conn **conn, int id, uint32_t adv_options); diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/att_read.c b/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/att_read.c deleted file mode 100644 index 2b95ca044f2..00000000000 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/att_read.c +++ /dev/null @@ -1,126 +0,0 @@ -/* Copyright (c) 2023 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "att_read.h" - -struct bt_testlib_att_read_closure { - uint8_t att_err; - struct bt_conn *conn; - struct bt_gatt_read_params params; - uint16_t *result_size; - uint16_t *result_handle; - struct net_buf_simple *result_data; - struct k_mutex lock; - struct k_condvar done; -}; - -static inline uint8_t att_read_cb(struct bt_conn *conn, uint8_t att_err, - struct bt_gatt_read_params *params, const void *read_data, - uint16_t read_len) -{ - struct bt_testlib_att_read_closure *ctx = - CONTAINER_OF(params, struct bt_testlib_att_read_closure, params); - - k_mutex_lock(&ctx->lock, K_FOREVER); - - ctx->att_err = att_err; - - if (!att_err && ctx->result_handle) { - *ctx->result_handle = params->by_uuid.start_handle; - } - - if (!att_err && ctx->result_size) { - *ctx->result_size = read_len; - } - - if (!att_err && ctx->result_data) { - uint16_t result_data_size = - MIN(read_len, net_buf_simple_tailroom(ctx->result_data)); - net_buf_simple_add_mem(ctx->result_data, read_data, result_data_size); - } - - k_condvar_signal(&ctx->done); - k_mutex_unlock(&ctx->lock); - return BT_GATT_ITER_STOP; -} - -static inline int bt_testlib_sync_bt_gatt_read(struct bt_testlib_att_read_closure *ctx) -{ - int api_err; - - ctx->params.func = att_read_cb; - - k_mutex_init(&ctx->lock); - k_condvar_init(&ctx->done); - - k_mutex_lock(&ctx->lock, K_FOREVER); - - api_err = bt_gatt_read(ctx->conn, &ctx->params); - - if (!api_err) { - k_condvar_wait(&ctx->done, &ctx->lock, K_FOREVER); - } - - k_mutex_unlock(&ctx->lock); - - if (api_err) { - __ASSERT_NO_MSG(api_err < 0); - return api_err; - } - - __ASSERT_NO_MSG(ctx->att_err >= 0); - return ctx->att_err; -} - -int bt_testlib_att_read_by_type_sync(struct net_buf_simple *result_data, uint16_t *result_size, - uint16_t *result_handle, struct bt_conn *conn, - enum bt_att_chan_opt bearer, const struct bt_uuid *type, - uint16_t start_handle, uint16_t end_handle) -{ - struct bt_testlib_att_read_closure ctx = { - .result_handle = result_handle, - .result_size = result_size, - .conn = conn, - .result_data = result_data, - .params = {.by_uuid = {.uuid = type, - .start_handle = start_handle, - .end_handle = end_handle}, - IF_ENABLED(CONFIG_BT_EATT, (.chan_opt = bearer))}, - }; - - if (bearer == BT_ATT_CHAN_OPT_ENHANCED_ONLY) { - __ASSERT(IS_ENABLED(CONFIG_BT_EATT), "EATT not complied in"); - } - - return bt_testlib_sync_bt_gatt_read(&ctx); -} - -int bt_testlib_att_read_by_handle_sync(struct net_buf_simple *result_data, uint16_t *result_size, - struct bt_conn *conn, enum bt_att_chan_opt bearer, - uint16_t handle, uint16_t offset) -{ - struct bt_testlib_att_read_closure ctx = { - .result_size = result_size, - .conn = conn, - .result_data = result_data, - .params = {.handle_count = 1, - .single = {.handle = handle, .offset = offset}, - IF_ENABLED(CONFIG_BT_EATT, (.chan_opt = bearer))}, - }; - - if (bearer == BT_ATT_CHAN_OPT_ENHANCED_ONLY) { - __ASSERT(IS_ENABLED(CONFIG_BT_EATT), "EATT not complied in"); - } - - return bt_testlib_sync_bt_gatt_read(&ctx); -} diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/att_read.h b/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/att_read.h deleted file mode 100644 index 0e16a496bf4..00000000000 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/att_read.h +++ /dev/null @@ -1,15 +0,0 @@ -/* Copyright (c) 2023 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -int bt_testlib_att_read_by_type_sync(struct net_buf_simple *result_data, uint16_t *result_size, - uint16_t *result_handle, struct bt_conn *conn, - enum bt_att_chan_opt bearer, const struct bt_uuid *type, - uint16_t start_handle, uint16_t end_handle); - -int bt_testlib_att_read_by_handle_sync(struct net_buf_simple *result_data, uint16_t *result_size, - struct bt_conn *conn, enum bt_att_chan_opt bearer, - uint16_t handle, uint16_t offset); diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/connect.c b/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/connect.c deleted file mode 100644 index f0c764c12f3..00000000000 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/connect.c +++ /dev/null @@ -1,71 +0,0 @@ -/* Copyright (c) 2023 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include "connect.h" - -struct bt_testlib_connect_closure { - uint8_t conn_err; - struct bt_conn **conn; - struct k_mutex lock; - struct k_condvar done; -}; - -/* Context pool (with capacity of one). */ -static K_SEM_DEFINE(g_ctx_free, 1, 1); -static K_MUTEX_DEFINE(g_ctx_lock); -static struct bt_testlib_connect_closure *g_ctx; - -static void connected_cb(struct bt_conn *conn, uint8_t conn_err) -{ - /* Loop over each (allocated) item in pool. */ - - k_mutex_lock(&g_ctx_lock, K_FOREVER); - - if (g_ctx && conn == *g_ctx->conn) { - g_ctx->conn_err = conn_err; - k_condvar_signal(&g_ctx->done); - } - - k_mutex_unlock(&g_ctx_lock); -} - -BT_CONN_CB_DEFINE(conn_callbacks) = { - .connected = connected_cb, -}; - -int bt_testlib_connect(const bt_addr_le_t *peer, struct bt_conn **conn) -{ - int api_err; - struct bt_testlib_connect_closure ctx = { - .conn = conn, - }; - - k_condvar_init(&ctx.done); - - k_sem_take(&g_ctx_free, K_FOREVER); - k_mutex_lock(&g_ctx_lock, K_FOREVER); - g_ctx = &ctx; - - api_err = bt_conn_le_create(peer, BT_CONN_LE_CREATE_CONN, BT_LE_CONN_PARAM_DEFAULT, conn); - - if (!api_err) { - k_condvar_wait(&ctx.done, &g_ctx_lock, K_FOREVER); - } - - g_ctx = NULL; - k_mutex_unlock(&g_ctx_lock); - k_sem_give(&g_ctx_free); - - if (api_err) { - __ASSERT_NO_MSG(api_err < 0); - return api_err; - } - - __ASSERT_NO_MSG(ctx.conn_err >= 0); - return ctx.conn_err; -} diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/connect.h b/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/connect.h deleted file mode 100644 index e8da223849a..00000000000 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/connect.h +++ /dev/null @@ -1,7 +0,0 @@ -/* Copyright (c) 2023 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -int bt_testlib_connect(const bt_addr_le_t *peer, struct bt_conn **conn); diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/scan.c b/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/scan.c deleted file mode 100644 index daac4802ce6..00000000000 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/scan.c +++ /dev/null @@ -1,87 +0,0 @@ -/* Copyright (c) 2023 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#include "scan.h" - -struct bt_scan_find_name_closure { - char *wanted_name; - bt_addr_le_t *result; - struct k_condvar done; -}; - -/* Context pool (with capacity of one). */ -static K_SEM_DEFINE(g_ctx_free, 1, 1); -static K_MUTEX_DEFINE(g_ctx_lock); -static struct bt_scan_find_name_closure *g_ctx; - -static bool bt_scan_find_name_cb_data_cb(struct bt_data *data, void *user_data) -{ - char **wanted = user_data; - - if (data->type == BT_DATA_NAME_COMPLETE) { - if (data->data_len == strlen(*wanted) && - !memcmp(*wanted, data->data, data->data_len)) { - *wanted = NULL; - /* Stop bt_data_parse. */ - return false; - } - } - - /* Continue with next ad data. */ - return true; -} - -static void bt_scan_find_name_cb(const bt_addr_le_t *addr, int8_t rssi, uint8_t adv_type, - struct net_buf_simple *buf) -{ - char *wanted; - - k_mutex_lock(&g_ctx_lock, K_FOREVER); - - __ASSERT_NO_MSG(g_ctx); - __ASSERT_NO_MSG(g_ctx->wanted_name); - - wanted = g_ctx->wanted_name; - - bt_data_parse(buf, bt_scan_find_name_cb_data_cb, &wanted); - - if (!wanted) { - (void)bt_le_scan_stop(); - *g_ctx->result = *addr; - k_condvar_signal(&g_ctx->done); - } - - k_mutex_unlock(&g_ctx_lock); -} - -int bt_testlib_scan_find_name(bt_addr_le_t *result, char name[]) -{ - int api_err; - struct bt_scan_find_name_closure ctx = { - .wanted_name = name, - .result = result, - }; - - k_condvar_init(&ctx.done); - - k_sem_take(&g_ctx_free, K_FOREVER); - k_mutex_lock(&g_ctx_lock, K_FOREVER); - g_ctx = &ctx; - - api_err = bt_le_scan_start(BT_LE_SCAN_PASSIVE, bt_scan_find_name_cb); - if (!api_err) { - k_condvar_wait(&ctx.done, &g_ctx_lock, K_FOREVER); - } - - g_ctx = NULL; - k_mutex_unlock(&g_ctx_lock); - k_sem_give(&g_ctx_free); - - return api_err; -} diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/scan.h b/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/scan.h deleted file mode 100644 index 58c887c21c9..00000000000 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/scan.h +++ /dev/null @@ -1,7 +0,0 @@ -/* Copyright (c) 2023 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -int bt_testlib_scan_find_name(bt_addr_le_t *result, char name[]); diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/security.c b/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/security.c deleted file mode 100644 index b6fb67bbc68..00000000000 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/security.c +++ /dev/null @@ -1,103 +0,0 @@ -/* Copyright (c) 2023 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -struct testlib_security_ctx { - enum bt_security_err result; - struct bt_conn *conn; - bt_security_t new_minimum; - struct k_condvar done; -}; - -/* Context pool (with capacity of one). */ -static K_SEM_DEFINE(g_ctx_free, 1, 1); -static K_MUTEX_DEFINE(g_ctx_lock); -static struct testlib_security_ctx *g_ctx; - -static void security_changed(struct bt_conn *conn, bt_security_t level, enum bt_security_err err) -{ - /* Mutex operations establish a happens-before relationship. This - * ensures variables have the expected values despite non-atomic - * accesses. - */ - k_mutex_lock(&g_ctx_lock, K_FOREVER); - - if (g_ctx && (g_ctx->conn == conn)) { - g_ctx->result = err; - /* Assumption: A security error means there will be further - * security changes for this connection. - */ - if (err || level >= g_ctx->new_minimum) { - k_condvar_signal(&g_ctx->done); - } - } - - k_mutex_unlock(&g_ctx_lock); -} - -BT_CONN_CB_DEFINE(conn_callbacks) = { - .security_changed = security_changed, -}; - -int bt_testlib_secure(struct bt_conn *conn, bt_security_t new_minimum) -{ - int api_err = 0; - struct testlib_security_ctx ctx = { - .conn = conn, - .new_minimum = new_minimum, - }; - - k_condvar_init(&ctx.done); - - /* The semaphore allocates `g_ctx` to this invocation of - * `bt_testlib_secure`, in case this function is called from multiple - * threads in parallel. - */ - k_sem_take(&g_ctx_free, K_FOREVER); - /* The mutex synchronizes this function with `security_changed()`. */ - k_mutex_lock(&g_ctx_lock, K_FOREVER); - - /* Do the thing. */ - api_err = bt_conn_set_security(conn, new_minimum); - - /* Holding the mutex will pause any thread entering - * `security_changed_cb`, delaying it until `k_condvar_wait`. This - * ensures that the condition variable is signaled while this thread is - * in `k_condvar_wait`, even if the event happens before, e.g. between - * `bt_conn_get_security` and `k_condvar_wait`. - * - * If the security level is already satisfied, there is no point in - * waiting, and it would deadlock if security was already satisfied - * before the mutex was taken, `bt_conn_set_security` will result in no - * operation. - */ - if (!api_err && bt_conn_get_security(conn) < new_minimum) { - /* Waiting on a condvar releases the mutex and waits for a - * signal on the condvar, atomically, without a gap between the - * release and wait. The mutex is locked again before returning. - */ - g_ctx = &ctx; - k_condvar_wait(&ctx.done, &g_ctx_lock, K_FOREVER); - g_ctx = NULL; - } - - k_mutex_unlock(&g_ctx_lock); - k_sem_give(&g_ctx_free); - - if (api_err) { - __ASSERT_NO_MSG(api_err < 0); - return api_err; - } - - __ASSERT_NO_MSG(ctx.result >= 0); - return ctx.result; -} diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/security.h b/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/security.h deleted file mode 100644 index 8b7dd46423c..00000000000 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/testlib/security.h +++ /dev/null @@ -1,7 +0,0 @@ -/* Copyright (c) 2023 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -int bt_testlib_secure(struct bt_conn *conn, bt_security_t new_minimum); From 13e43ca5c85abf18c4f86496e429b8ff8eb9ba0a Mon Sep 17 00:00:00 2001 From: Andy Sinclair Date: Mon, 4 Mar 2024 15:58:54 +0000 Subject: [PATCH 1114/2402] drivers: gpio: npm1300: Event configuration based on active state Configuration of GPIO as input now sets rising/falling event orientation based on ACTIVE_HIGH/LOW setting. Signed-off-by: Andy Sinclair --- drivers/gpio/gpio_npm1300.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio_npm1300.c b/drivers/gpio/gpio_npm1300.c index 65c3cdd6fda..0018530207d 100644 --- a/drivers/gpio/gpio_npm1300.c +++ b/drivers/gpio/gpio_npm1300.c @@ -118,8 +118,15 @@ static inline int gpio_npm1300_configure(const struct device *dev, gpio_pin_t pi /* Configure mode */ if ((flags & GPIO_INPUT) != 0U) { - ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_MODE + pin, - NPM1300_GPIO_GPIINPUT); + if (flags & GPIO_ACTIVE_LOW) { + ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, + NPM_GPIO_OFFSET_MODE + pin, + NPM1300_GPIO_GPIEVENTFALL); + } else { + ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, + NPM_GPIO_OFFSET_MODE + pin, + NPM1300_GPIO_GPIEVENTRISE); + } } else if ((flags & NPM1300_GPIO_WDT_RESET_ON) != 0U) { ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_MODE + pin, NPM1300_GPIO_GPORESET); From 9813221ea610c686a4ef0024808d8bf309ebd0c8 Mon Sep 17 00:00:00 2001 From: Andy Sinclair Date: Mon, 4 Mar 2024 16:13:44 +0000 Subject: [PATCH 1115/2402] drivers: mfd: npm1300: Added GPIO events Added GPIO input edge events Signed-off-by: Andy Sinclair --- drivers/mfd/mfd_npm1300.c | 8 +++++++- include/zephyr/drivers/mfd/npm1300.h | 5 +++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/mfd_npm1300.c b/drivers/mfd/mfd_npm1300.c index ef06b6da7f0..3100e2e813a 100644 --- a/drivers/mfd/mfd_npm1300.c +++ b/drivers/mfd/mfd_npm1300.c @@ -67,7 +67,13 @@ static const struct event_reg_t event_reg[NPM1300_EVENT_MAX] = { [NPM1300_EVENT_SHIPHOLD_RELEASE] = {0x12U, 0x02U}, [NPM1300_EVENT_WATCHDOG_WARN] = {0x12U, 0x08U}, [NPM1300_EVENT_VBUS_DETECTED] = {0x16U, 0x01U}, - [NPM1300_EVENT_VBUS_REMOVED] = {0x16U, 0x02U}}; + [NPM1300_EVENT_VBUS_REMOVED] = {0x16U, 0x02U}, + [NPM1300_EVENT_GPIO0_EDGE] = {0x22U, 0x01U}, + [NPM1300_EVENT_GPIO1_EDGE] = {0x22U, 0x02U}, + [NPM1300_EVENT_GPIO2_EDGE] = {0x22U, 0x04U}, + [NPM1300_EVENT_GPIO3_EDGE] = {0x22U, 0x08U}, + [NPM1300_EVENT_GPIO4_EDGE] = {0x22U, 0x10U}, +}; static void gpio_callback(const struct device *dev, struct gpio_callback *cb, uint32_t pins) { diff --git a/include/zephyr/drivers/mfd/npm1300.h b/include/zephyr/drivers/mfd/npm1300.h index b86f2f31c8f..4dd03fa2ec3 100644 --- a/include/zephyr/drivers/mfd/npm1300.h +++ b/include/zephyr/drivers/mfd/npm1300.h @@ -32,6 +32,11 @@ enum mfd_npm1300_event_t { NPM1300_EVENT_WATCHDOG_WARN, NPM1300_EVENT_VBUS_DETECTED, NPM1300_EVENT_VBUS_REMOVED, + NPM1300_EVENT_GPIO0_EDGE, + NPM1300_EVENT_GPIO1_EDGE, + NPM1300_EVENT_GPIO2_EDGE, + NPM1300_EVENT_GPIO3_EDGE, + NPM1300_EVENT_GPIO4_EDGE, NPM1300_EVENT_MAX }; From 62665eabf7d29bbdf3309e197d3d01d67b669b21 Mon Sep 17 00:00:00 2001 From: cyliang tw Date: Thu, 21 Mar 2024 16:06:47 +0800 Subject: [PATCH 1116/2402] boards: nuvoton: add support for numaker m2l31ki Add new development board numaker_m2l31ki for m2l31x series. Signed-off-by: cyliang tw --- boards/nuvoton/numaker_m2l31ki/Kconfig | 8 ++ .../numaker_m2l31ki/Kconfig.numaker_m2l31ki | 8 ++ boards/nuvoton/numaker_m2l31ki/board.cmake | 6 ++ boards/nuvoton/numaker_m2l31ki/board.yml | 5 + boards/nuvoton/numaker_m2l31ki/doc/index.rst | 95 ++++++++++++++++++ .../nuvoton/numaker_m2l31ki/doc/m2l31ki.webp | Bin 0 -> 69466 bytes .../numaker_m2l31ki-pinctrl.dtsi | 27 +++++ .../numaker_m2l31ki/numaker_m2l31ki.dts | 82 +++++++++++++++ .../numaker_m2l31ki/numaker_m2l31ki.yaml | 16 +++ .../numaker_m2l31ki/numaker_m2l31ki_defconfig | 23 +++++ .../numaker_m2l31ki/support/openocd.cfg | 2 + 11 files changed, 272 insertions(+) create mode 100644 boards/nuvoton/numaker_m2l31ki/Kconfig create mode 100644 boards/nuvoton/numaker_m2l31ki/Kconfig.numaker_m2l31ki create mode 100644 boards/nuvoton/numaker_m2l31ki/board.cmake create mode 100644 boards/nuvoton/numaker_m2l31ki/board.yml create mode 100644 boards/nuvoton/numaker_m2l31ki/doc/index.rst create mode 100644 boards/nuvoton/numaker_m2l31ki/doc/m2l31ki.webp create mode 100644 boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki-pinctrl.dtsi create mode 100644 boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.dts create mode 100644 boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml create mode 100644 boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki_defconfig create mode 100644 boards/nuvoton/numaker_m2l31ki/support/openocd.cfg diff --git a/boards/nuvoton/numaker_m2l31ki/Kconfig b/boards/nuvoton/numaker_m2l31ki/Kconfig new file mode 100644 index 00000000000..7680fcb0e39 --- /dev/null +++ b/boards/nuvoton/numaker_m2l31ki/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton NuMaker M2L31KI board configuration +# +# Copyright (c) 2024 Nuvoton Technology Corporation. + +config BOARD_NUMAKER_M2L31KI + select SOC_FLASH_NUMAKER_RMC diff --git a/boards/nuvoton/numaker_m2l31ki/Kconfig.numaker_m2l31ki b/boards/nuvoton/numaker_m2l31ki/Kconfig.numaker_m2l31ki new file mode 100644 index 00000000000..4aecdc8750c --- /dev/null +++ b/boards/nuvoton/numaker_m2l31ki/Kconfig.numaker_m2l31ki @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton NuMaker M2L31KI board configuration +# +# Copyright (c) 2024 Nuvoton Technology Corporation. + +config BOARD_NUMAKER_M2L31KI + select SOC_M2L31XXX diff --git a/boards/nuvoton/numaker_m2l31ki/board.cmake b/boards/nuvoton/numaker_m2l31ki/board.cmake new file mode 100644 index 00000000000..ae766b1afe7 --- /dev/null +++ b/boards/nuvoton/numaker_m2l31ki/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(pyocd "--target=m2l31kidae") + +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/nuvoton/numaker_m2l31ki/board.yml b/boards/nuvoton/numaker_m2l31ki/board.yml new file mode 100644 index 00000000000..f01805447fa --- /dev/null +++ b/boards/nuvoton/numaker_m2l31ki/board.yml @@ -0,0 +1,5 @@ +board: + name: numaker_m2l31ki + vendor: nuvoton + socs: + - name: m2l31xxx diff --git a/boards/nuvoton/numaker_m2l31ki/doc/index.rst b/boards/nuvoton/numaker_m2l31ki/doc/index.rst new file mode 100644 index 00000000000..3e2c8b9550b --- /dev/null +++ b/boards/nuvoton/numaker_m2l31ki/doc/index.rst @@ -0,0 +1,95 @@ +.. _nuvoton_m2l31ki: + +NUVOTON NUMAKER M2L31KI +######################## + +Overview +******** + +The NuMaker M2L31KI is an Internet of Things (IoT) application focused platform +specially developed by Nuvoton. The NuMaker-M2L31KI is based on the NuMicro® M2L31 +series MCU with ARM® -Cortex®-M23 core. + +.. image:: ./m2l31ki.webp + :align: center + :alt: M2L31KI + +Features: +========= +- 32-bit Arm Cortex®-M23 M2L31KIDAE MCU +- Core clock up to 72 MHz +- 512 KB embedded Dual Bank Flash and 168 KB SRAM +- USB 2.0 Full-Speed OTG / Device +- USB 1.1 Host +- Arduino UNO compatible interface +- One push-button is for reset +- Two LEDs: one is for power indication and the other is for user-defined +- On-board NU-Link2 ICE debugger/programmer with SWD connector + +More information about the board can be found at the `NuMaker M2L31KI User Manual`_. + +Supported Features +================== + +* The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 72MHz. + +The development board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port | ++-----------+------------+-----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-----------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +More details about the supported peripherals are available in `M2L31 TRM`_ +Other hardware features are not currently supported by the Zephyr kernel. + +Building and Flashing +********************* +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +On board debugger Nu-link2 can emulate UART0 as a virtual COM port over usb, +To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. +Connect the NuMaker-M2L31KI to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: numaker_m2l31ki + :goals: flash + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: numaker_m2l31ki + :goals: debug + +Step through the application in your debugger. + +References +********** + +.. _NuMaker M2L31KI User Manual: + https://www.nuvoton.com/products/microcontrollers/arm-cortex-m23-mcus/m2l31-series/ +.. _M2L31 TRM: + https://www.nuvoton.com/products/microcontrollers/arm-cortex-m23-mcus/m2l31-series/ diff --git a/boards/nuvoton/numaker_m2l31ki/doc/m2l31ki.webp b/boards/nuvoton/numaker_m2l31ki/doc/m2l31ki.webp new file mode 100644 index 0000000000000000000000000000000000000000..6a8fcc28765acb6217b6109e54316438ef718be9 GIT binary patch literal 69466 zcmV(rK<>X%Nk&Fe4*>vIMM6+kP&gn)4*>vhg94oaD#8Lr0X~g1lSnJ4rX@AIt=OOu ziDYgA5Is-#Du{hX=R>8q|Nh@lX0`t>)K}>*OL-rouansB`FZ)xm#%Ac;+Pg-=l@#& zeS)RycR%=i@VSS@&$|96*311pwtOG`|1xi5@00&$*01$XQUB|{g}p|3yZzqvQ}b%{ zfa=cllIgVm_mB_tKO;Xx>re8Zq5miS=lu8l@9*C*Uv7WX{u9EtQUB}zS?VwIzrugD z{{Q}C_FLx%@_+OH!hfLsw)9WqSNNag|Iz-@e1v{g{Wtxe_m9dChhL}v!Tz`Y4}I3T z{#X9j`497c;U2{ONB$4^PxN25zX#tn|7ZNSsh_R?fd8HTKmA|sAJ`A`U+jPKf5CfI z{}cb0`M)RMzJIp;s`vx`h5h6I5BWd#pSvGTAKd@#|5yIo_iNlA)SvqQ)c?Nu3jTrp z>;D(|FZEvhAOC;e{44#||Ns8);k)+-|L6OcY&ln``jCk?FVIls8W&aYlY8(d^meME zHoSh%&x3QQ8+et$h>E(5+qE-028rQoZj0sxByei7YWGS3$W)tH`v^9XNeOCa5LX=| z35Z_Vi$s$0ubMHpsmU`cP-6RPeotbBC7YcCx(WY-cOWar9WU5s3Twffksbqg}T%GLj>1P1aS{tG{RvT)-w&i0TyqC>* z)9;y9;GpPAtufrr%QB#FTVQniYt%eNdelh42@^%^3FYp3rw2#laeGS)pv-?0b&`(}?BEBbUTom|`GFwC;IrZ#f&SS{5}=5#(3f4kXdzxy z43q2|56+b9o^_PFdqNtt6xC{7K^m?fa;)}L~o(9@@_?I8t@Ev=wS+P zpi$OZf<#;a%FhyxpJ1R~zD|~KGZ7wa@j+&)gDlC$5@+5d=XpxRN_?tJqQZ6)t#rPGBYt5dRO~U_J^E< zU6%aa%axFp{0emsWZX?|kfGWvlZnZ5I}HAup8!$Cf` zd3$hJ_uD?`4{Q`eL;NKl!b&PD?#Jqmwr@ehI_@P42PjG6z3!n`QDS#zC1&1h6labd z18w8zHNKoDHZmW5I6#}ka>wlH6q_=wLasqR!sToizqUSZ&D%hdssw~H*V7x9!hV06 zMoNOXgHLf9Bk%KBS8BpS4tr>3^*X`I&7Al{E9>8PQYr7z9J2?HpTt>$Kf2yk)K(}5 z&SBJJk>lZufvlEY$!~(|gZv%@AgU8QIfA}t|48`8Pu9msqkoqIW2QZYGoj7C3jifblU`}%A9-Y zvy9ViP|afYqf8*j1oNAO#z?raHoqfBm<^W=sr)uBSUB_=OvYK=YA3dA?mw}gRqD`40au`UPz#}> z%%E8}tF;yF9Z4Xd?G0!KZ;JOL6iGWvJZAU6am8Mc&gs%aL!`1CRrS0LuxwoTt2dViiRl`++}+gSl3 z-vUyLT_smkwR_!nh5)EY{`hF^S)1jL0>qw#>?Azl4VM0(8r7(=4)^v;9RgcFwvJ+J z<8|tFGnuZ>Yu_l@yrP@68k{OVhU^A5(C@Jt-1Rq{RV;p*X?>N!@Fi>ileZ$AXGbGA z2ddkFHF+ip83Sgq%Z0F1N^1|;lWb>78XzIr_2pL7l~+I|Qj`;h_3ETdv%e1tQ{aNx z_(Jm4tkjCseH88LZQ4~}^_h1D-m3|sAtfgdYcXu~TQaur#lYBZ=KF8@j5%0b;Oz-~ zoMTAs#J&=u=w;3$7Z}g)dnzL;OH` zWV{JhAr^7F#V2oAyQG4}x;AEm-sx9*$<7UPt?x(o5hF}BSX}1b3$bOKhvE+w^C+!; z1)=>_am$M?X-X6obF7OnnaUBlCp;yOr9_;F*e0WZ*6I`p>wMmyQlj> zfl&qxx*Ut6q=lXgt2J2nc<0FI-tYj;8SnpMYE12VvG&svB>(TofaJFL2{K-f=Wu~) zh31N`kW;`N)4rdPa&(=)lVR9NGQ&%W=guMLPLOQkW=3azj;+C7${1pP>6Ool?~W{D zH;u10wz9!-RNnnET*r+trrj54*nyFubIoVZ8B^@epR-e974(dpH2IPoDbt6yZu&cQ@|BPxyG(oHEO z11rH;vu{>U+kFT&He=dt;&*;EZ2PlBnSp?vO(m+E#UL+Ha+iVX>umgzRNHBc7eIah zL8u?|UPTp=?#=fMARg;ic-`NBF#<03qcVBWxnYrsSZ#e3VElo~L z^KD2yA!%;_7g7=T?j%9@cACdAwss`X{Lckr-fj~&iOFq79%(^G%wlY120XxPB5yn@ zo=!;C5}>DIt*V-y*vaw!LsdF^CfD$Dj8=Z$CmoSl_Gf1Q+UUj?>t{v1|g@i485{9 zG!y?-BDq#`t9+a^gVbYA@&NwTiO71&^+bDxEh5XlzGFs98M++e>VAJ5BbW}qK;@

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    \t\t" "\t\t\n"); for (chan_idx = 0; chan_idx < regd.num_channels; chan_idx++) { - PR(" %d\t\t\t\%d\t\t\t\%s\t\t\t%d\t\t\t%s\t\t\t\t%s\n", + PR(" %d\t\t\t%d\t\t\t%s\t\t\t%d\t\t\t%s\t\t\t\t%s\n", wifi_freq_to_channel(chan_info[chan_idx].center_frequency), chan_info[chan_idx].center_frequency, chan_info[chan_idx].supported ? "y" : "n", @@ -1417,7 +1416,7 @@ static int cmd_wifi_listen_interval(const struct shell *sh, size_t argc, char *a { struct net_if *iface = net_if_get_first_wifi(); struct wifi_ps_params params = { 0 }; - long interval = 0; + long interval; context.sh = sh; From a6865c419140cfea70b6b301750002d099f3e7e0 Mon Sep 17 00:00:00 2001 From: Pisit Sawangvonganan Date: Fri, 2 Feb 2024 23:46:12 +0700 Subject: [PATCH 1510/2402] net: wifi: shell: apply `struct option` as `static const` This change marks each instance of the `struct option` as `static const`. The rationale is that `struct option` is a read-only variable. By using `static const`, we ensure immutability, leading to usage of only the `.rodata` section and a reduction in the `.data` area. Signed-off-by: Pisit Sawangvonganan --- subsys/net/l2/wifi/wifi_shell.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 7f4489e0de3..7b5f5dbe1e3 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -641,7 +641,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, { struct getopt_state *state; int opt; - static struct option long_options[] = {{"type", required_argument, 0, 't'}, + static const struct option long_options[] = {{"type", required_argument, 0, 't'}, {"bands", required_argument, 0, 'b'}, {"dwell_time_active", required_argument, 0, 'a'}, {"dwell_time_passive", required_argument, 0, 'p'}, @@ -1485,7 +1485,7 @@ void parse_mode_args_to_params(const struct shell *sh, int argc, int opt; int option_index = 0; - static struct option long_options[] = {{"if-index", optional_argument, 0, 'i'}, + static const struct option long_options[] = {{"if-index", optional_argument, 0, 'i'}, {"sta", no_argument, 0, 's'}, {"monitor", no_argument, 0, 'm'}, {"ap", no_argument, 0, 'a'}, @@ -1584,7 +1584,7 @@ void parse_channel_args_to_params(const struct shell *sh, int argc, int opt; int option_index = 0; - static struct option long_options[] = {{"if-index", optional_argument, 0, 'i'}, + static const struct option long_options[] = {{"if-index", optional_argument, 0, 'i'}, {"channel", required_argument, 0, 'c'}, {"get", no_argument, 0, 'g'}, {"help", no_argument, 0, 'h'}, @@ -1679,7 +1679,7 @@ void parse_filter_args_to_params(const struct shell *sh, int argc, int opt; int option_index = 0; - static struct option long_options[] = {{"if-index", optional_argument, 0, 'i'}, + static const struct option long_options[] = {{"if-index", optional_argument, 0, 'i'}, {"capture-len", optional_argument, 0, 'b'}, {"all", no_argument, 0, 'a'}, {"mgmt", no_argument, 0, 'm'}, From e145eb9201e8233ecd8ba2f912d795dbbd788e14 Mon Sep 17 00:00:00 2001 From: Pisit Sawangvonganan Date: Sat, 3 Feb 2024 00:07:05 +0700 Subject: [PATCH 1511/2402] net: wifi: shell: adopt `getopt_state` for safer `optarg` access By using `getopt_state` to access `optarg`, offering a better alternative to direct global `optarg` access. This approach mitigates the risks associated with concurrent access to the global variable. Signed-off-by: Pisit Sawangvonganan --- subsys/net/l2/wifi/wifi_shell.c | 34 +++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 7b5f5dbe1e3..ba1fcce502b 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -660,19 +660,19 @@ static int wifi_scan_args_to_params(const struct shell *sh, state = getopt_state_get(); switch (opt) { case 't': - if (!strncasecmp(optarg, "passive", 7)) { + if (!strncasecmp(state->optarg, "passive", 7)) { params->scan_type = WIFI_SCAN_TYPE_PASSIVE; - } else if (!strncasecmp(optarg, "active", 6)) { + } else if (!strncasecmp(state->optarg, "active", 6)) { params->scan_type = WIFI_SCAN_TYPE_ACTIVE; } else { - PR_ERROR("Invalid scan type %s\n", optarg); + PR_ERROR("Invalid scan type %s\n", state->optarg); return -ENOEXEC; } opt_num++; break; case 'b': - if (wifi_utils_parse_scan_bands(optarg, ¶ms->bands)) { + if (wifi_utils_parse_scan_bands(state->optarg, ¶ms->bands)) { PR_ERROR("Invalid band value(s)\n"); return -ENOEXEC; } @@ -680,7 +680,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, opt_num++; break; case 'a': - val = atoi(optarg); + val = atoi(state->optarg); if ((val < 5) || (val > 1000)) { PR_ERROR("Invalid dwell_time_active val\n"); @@ -691,7 +691,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, opt_num++; break; case 'p': - val = atoi(optarg); + val = atoi(state->optarg); if ((val < 10) || (val > 1000)) { PR_ERROR("Invalid dwell_time_passive val\n"); @@ -702,7 +702,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, opt_num++; break; case 's': - if (wifi_utils_parse_scan_ssids(optarg, + if (wifi_utils_parse_scan_ssids(state->optarg, params->ssids, ARRAY_SIZE(params->ssids))) { PR_ERROR("Invalid SSID(s)\n"); @@ -712,7 +712,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, opt_num++; break; case 'm': - val = atoi(optarg); + val = atoi(state->optarg); if ((val < 0) || (val > 65535)) { PR_ERROR("Invalid max_bss val\n"); @@ -723,7 +723,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, opt_num++; break; case 'c': - if (wifi_utils_parse_scan_chan(optarg, + if (wifi_utils_parse_scan_chan(state->optarg, params->band_chan, ARRAY_SIZE(params->band_chan))) { PR_ERROR("Invalid band or channel value(s)\n"); @@ -1484,6 +1484,7 @@ void parse_mode_args_to_params(const struct shell *sh, int argc, { int opt; int option_index = 0; + struct getopt_state *state; static const struct option long_options[] = {{"if-index", optional_argument, 0, 'i'}, {"sta", no_argument, 0, 's'}, @@ -1495,6 +1496,7 @@ void parse_mode_args_to_params(const struct shell *sh, int argc, {0, 0, 0, 0}}; while ((opt = getopt_long(argc, argv, "i:smtpakgh", long_options, &option_index)) != -1) { + state = getopt_state_get(); switch (opt) { case 's': mode->mode |= WIFI_STA_MODE; @@ -1512,7 +1514,7 @@ void parse_mode_args_to_params(const struct shell *sh, int argc, mode->oper = WIFI_MGMT_GET; break; case 'i': - mode->if_index = (uint8_t)atoi(optarg); + mode->if_index = (uint8_t)atoi(state->optarg); break; case 'h': shell_help(sh); @@ -1583,6 +1585,7 @@ void parse_channel_args_to_params(const struct shell *sh, int argc, { int opt; int option_index = 0; + struct getopt_state *state; static const struct option long_options[] = {{"if-index", optional_argument, 0, 'i'}, {"channel", required_argument, 0, 'c'}, @@ -1591,12 +1594,13 @@ void parse_channel_args_to_params(const struct shell *sh, int argc, {0, 0, 0, 0}}; while ((opt = getopt_long(argc, argv, "i:c:gh", long_options, &option_index)) != -1) { + state = getopt_state_get(); switch (opt) { case 'c': - channel->channel = (uint16_t)atoi(optarg); + channel->channel = (uint16_t)atoi(state->optarg); break; case 'i': - channel->if_index = (uint8_t)atoi(optarg); + channel->if_index = (uint8_t)atoi(state->optarg); break; case 'g': channel->oper = WIFI_MGMT_GET; @@ -1678,6 +1682,7 @@ void parse_filter_args_to_params(const struct shell *sh, int argc, { int opt; int option_index = 0; + struct getopt_state *state; static const struct option long_options[] = {{"if-index", optional_argument, 0, 'i'}, {"capture-len", optional_argument, 0, 'b'}, @@ -1690,6 +1695,7 @@ void parse_filter_args_to_params(const struct shell *sh, int argc, {0, 0, 0, 0}}; while ((opt = getopt_long(argc, argv, "i:b:amcdgh", long_options, &option_index)) != -1) { + state = getopt_state_get(); switch (opt) { case 'a': filter->filter |= WIFI_PACKET_FILTER_ALL; @@ -1704,10 +1710,10 @@ void parse_filter_args_to_params(const struct shell *sh, int argc, filter->filter |= WIFI_PACKET_FILTER_CTRL; break; case 'i': - filter->if_index = (uint8_t)atoi(optarg); + filter->if_index = (uint8_t)atoi(state->optarg); break; case 'b': - filter->buffer_size = (uint16_t)atoi(optarg); + filter->buffer_size = (uint16_t)atoi(state->optarg); break; case 'h': shell_help(sh); From da7ce2f3334690707f3ad54c2aa126e3929fe1d3 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Tue, 26 Mar 2024 08:22:53 +0100 Subject: [PATCH 1512/2402] doc: bsim: Add paragraph about runner conventions Alberto had a bad time. Signed-off-by: Jonathan Rico --- doc/develop/test/bsim.rst | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/doc/develop/test/bsim.rst b/doc/develop/test/bsim.rst index a7a97cef3a1..10ba5b60fae 100644 --- a/doc/develop/test/bsim.rst +++ b/doc/develop/test/bsim.rst @@ -150,8 +150,25 @@ required, and some Zephyr users do not use or have west, but still use the build Test scripts ------------ -- Each test is defined by a shell script with the extension ``.sh``. -- Scripts starting with an underscore (``_``) are ignored. +Please follow the existing conventions and do not design one-off bespoke runners (e.g. a python +script, or another shell abstraction). + +The rationale is that it is easier and faster for the maintainers to perform tree-wide updates for +build system or compatibility changes if the tests are run in the same manner, with the same +variables, etc.. + +If you have a good idea for improving your test script, please make a PR changing *all* the test +scripts in order to benefit everyone and conserve homogeneity. You can of course discuss it first in +an RFC issue or on the babblesim discord channel. + +Scripts starting with an underscore (``_``) are not automatically discovered and run. They can serve +as either helper functions for the main script, or can be used for local development utilities, e.g. +building and running tests locally, debugging, etc.. + +Here are the conventions: + +- Each test is defined by a shell script with the extension ``.sh``, in a subfolder called + ``test_scripts/``. - Test scripts expect that the binaries they require are already built, and will spawn the processes for the simulated devices and physical layer simulation with the necessary command line options. - Tests must return 0 to the invoking shell if the test passes, and not 0 if the test fails. From 97d47204c51c54d76d4745a6838166b003ff7590 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Tue, 26 Mar 2024 08:37:39 +0100 Subject: [PATCH 1513/2402] doc: bsim: Reword test script conventions Try to make it more terse, and remove duplicate lines. Signed-off-by: Jonathan Rico --- doc/develop/test/bsim.rst | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/doc/develop/test/bsim.rst b/doc/develop/test/bsim.rst index 10ba5b60fae..4fe8bbe8095 100644 --- a/doc/develop/test/bsim.rst +++ b/doc/develop/test/bsim.rst @@ -169,21 +169,16 @@ Here are the conventions: - Each test is defined by a shell script with the extension ``.sh``, in a subfolder called ``test_scripts/``. -- Test scripts expect that the binaries they require are already built, and will spawn the processes - for the simulated devices and physical layer simulation with the necessary command line options. -- Tests must return 0 to the invoking shell if the test passes, and not 0 if the test fails. -- It is recommended to have a single test for each test script. +- It is recommended to run a single test per script file. It allows for better parallelization of + the runs in CI. +- Scripts expect that the binaries they require are already built. They should not compile binaries. +- Scripts will spawn the processes for every simulated device and the physical layer simulation. +- Scripts must return 0 to the invoking shell if the test passes, and not 0 if the test fails. - Each test must have a unique simulation id, to enable running different tests in parallel. -- The test scripts should not compile the images on their own. - Neither the scripts nor the images should modify the workstation filesystem content beyond the ``${BSIM_OUT_PATH}/results//`` or ``/tmp/`` folders. That is, they should not leave stray files behind. -- If the test scripts or the test binaries create temporary files, they should preferably do so by - placing them in the ``${BSIM_OUT_PATH}/results//`` folder. - Otherwise they should be named as to avoid conflicts with other test scripts which may be running - in parallel. -- When running tests that require several consecutive simulations, for ex. if simulating a device - pairing, powering off, and powering up after as a new simulation, - they should strive for using separate simulation ids for each simulation part, - in that way ensuring that the simulation radio activity of each segment can be inspected a +- Tests that require several consecutive simulations (e.g, if simulating a device pairing, powering + off, and powering up after as a new simulation) should use separate simulation ids for each + simulation segment, ensuring that the radio activity of each segment can be inspected a posteriori. From d73b6e50b9e74f6044e92f1f9f45b69f879121d1 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Wed, 27 Mar 2024 09:03:53 +0100 Subject: [PATCH 1514/2402] doc: bsim: Add three more rules On the request of the maintainer. Background: We have recently had issues with tests timing out because of the difference of speed between CI runners and a standard developer machine. In that case, the logs are printed, and some tests (by yours truly) are a bit on the chatty side. Github's UI chokes (for a good minute or more lol) on more than a few hundred lines, so it's a bad experience for contributors. Signed-off-by: Jonathan Rico --- doc/develop/test/bsim.rst | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/doc/develop/test/bsim.rst b/doc/develop/test/bsim.rst index 4fe8bbe8095..596d2911fdf 100644 --- a/doc/develop/test/bsim.rst +++ b/doc/develop/test/bsim.rst @@ -182,3 +182,10 @@ Here are the conventions: off, and powering up after as a new simulation) should use separate simulation ids for each simulation segment, ensuring that the radio activity of each segment can be inspected a posteriori. +- Avoid overly long tests. If the test takes over 20 seconds of runtime, consider if it is possible + to split it in several separate tests. +- If the test takes over 5 seconds, set ``EXECUTE_TIMEOUT`` to a value that is at least 5 times + bigger than the measured run-time. +- Do not set ``EXECUTE_TIMEOUT`` to a value lower than the default. +- Tests should not be overly verbose: less than a hundred lines are expected on the outputs. Do make + use of ``LOG_DBG()`` extensively, but don't enable the ``DBG`` log level by default. From 0fe8ddd75e151d3d779011df4e3914c97add74c0 Mon Sep 17 00:00:00 2001 From: Fredrik Danebjer Date: Mon, 4 Mar 2024 10:34:29 +0100 Subject: [PATCH 1515/2402] Bluetooth: Audio: Scan Delegator: Guard for duplication in add_source Added a check for duplication of add source operation in the Scan Delagator. BAP 6.5.4 states that an assistant may not perform add source operation if it results in a duplication of a source. While this is not mentioned for the Scan Delegator, the spirit of the spec. must be that no duplications can exists in the recv_state, which is what this commit fixes. Signed-off-by: Fredrik Danebjer --- subsys/bluetooth/audio/bap_scan_delegator.c | 43 +++++++++++++++++---- 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/subsys/bluetooth/audio/bap_scan_delegator.c b/subsys/bluetooth/audio/bap_scan_delegator.c index 1f9f073f89b..0f5be7ce44a 100644 --- a/subsys/bluetooth/audio/bap_scan_delegator.c +++ b/subsys/bluetooth/audio/bap_scan_delegator.c @@ -279,7 +279,7 @@ static void scan_delegator_security_changed(struct bt_conn *conn, } /* Notify all receive states after a bonded device reconnects */ - for (int i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { + for (size_t i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { struct bass_recv_state_internal *internal_state = &scan_delegator.recv_states[i]; int gatt_err; @@ -318,7 +318,7 @@ static struct broadcast_assistant *get_bap_broadcast_assistant(struct bt_conn *c { struct broadcast_assistant *new = NULL; - for (int i = 0; i < ARRAY_SIZE(scan_delegator.assistant_configs); i++) { + for (size_t i = 0; i < ARRAY_SIZE(scan_delegator.assistant_configs); i++) { if (scan_delegator.assistant_configs[i].conn == conn) { return &scan_delegator.assistant_configs[i]; } else if (new == NULL && @@ -344,7 +344,7 @@ static uint8_t next_src_id(void) while (!unique) { next_src_id = scan_delegator.next_src_id++; unique = true; - for (int i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { + for (size_t i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { if (scan_delegator.recv_states[i].active && scan_delegator.recv_states[i].state.src_id == next_src_id) { unique = false; @@ -358,7 +358,7 @@ static uint8_t next_src_id(void) static struct bass_recv_state_internal *bass_lookup_src_id(uint8_t src_id) { - for (int i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { + for (size_t i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { if (scan_delegator.recv_states[i].active && scan_delegator.recv_states[i].state.src_id == src_id) { return &scan_delegator.recv_states[i]; @@ -370,7 +370,7 @@ static struct bass_recv_state_internal *bass_lookup_src_id(uint8_t src_id) static struct bass_recv_state_internal *bass_lookup_pa_sync(struct bt_le_per_adv_sync *sync) { - for (int i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { + for (size_t i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { if (scan_delegator.recv_states[i].pa_sync == sync) { return &scan_delegator.recv_states[i]; } @@ -381,7 +381,7 @@ static struct bass_recv_state_internal *bass_lookup_pa_sync(struct bt_le_per_adv static struct bass_recv_state_internal *bass_lookup_addr(const bt_addr_le_t *addr) { - for (int i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { + for (size_t i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { if (bt_addr_le_eq(&scan_delegator.recv_states[i].state.addr, addr)) { return &scan_delegator.recv_states[i]; @@ -493,6 +493,24 @@ static int pa_sync_term_request(struct bt_conn *conn, return err; } +static bool bass_source_is_duplicate(uint32_t broadcast_id, uint8_t adv_sid, bt_addr_le_t addr) +{ + struct bass_recv_state_internal *state; + + for (size_t i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { + state = &scan_delegator.recv_states[i]; + + if (state != NULL && state->state.broadcast_id == broadcast_id + && state->state.adv_sid == adv_sid && state->state.addr.type == addr.type) { + LOG_DBG("recv_state already exists at src_id=0x%02X", state->state.src_id); + + return true; + } + } + + return false; +} + static int scan_delegator_add_source(struct bt_conn *conn, struct net_buf_simple *buf) { @@ -502,6 +520,7 @@ static int scan_delegator_add_source(struct bt_conn *conn, uint8_t pa_sync; uint16_t pa_interval; uint32_t aggregated_bis_syncs = 0; + uint32_t broadcast_id; bool bis_sync_requested; /* subtract 1 as the opcode has already been pulled */ @@ -535,7 +554,17 @@ static int scan_delegator_add_source(struct bt_conn *conn, return BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED); } - state->broadcast_id = net_buf_simple_pull_le24(buf); + broadcast_id = net_buf_simple_pull_le24(buf); + + if (bass_source_is_duplicate(broadcast_id, state->adv_sid, state->addr)) { + LOG_DBG("Adding broadcast_id=0x%06X, adv_sid=0x%02X, and addr.type=0x%02X would " + "result in duplication", state->broadcast_id, state->adv_sid, + state->addr.type); + + return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED); + } + + state->broadcast_id = broadcast_id; pa_sync = net_buf_simple_pull_u8(buf); if (pa_sync > BT_BAP_BASS_PA_REQ_SYNC) { From a1893c58905cbfc3e75de6ea3f26c8635b9aa822 Mon Sep 17 00:00:00 2001 From: Nithin Ramesh Myliattil Date: Wed, 27 Mar 2024 12:23:58 +0100 Subject: [PATCH 1516/2402] Bluetooth: Audio: Scan Delegator: update bass_source_is_duplicate fn Address type is passed as an argument instead of the entire address. Signed-off-by: Nithin Ramesh Myliattil --- subsys/bluetooth/audio/bap_scan_delegator.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/subsys/bluetooth/audio/bap_scan_delegator.c b/subsys/bluetooth/audio/bap_scan_delegator.c index 0f5be7ce44a..2e25d983f56 100644 --- a/subsys/bluetooth/audio/bap_scan_delegator.c +++ b/subsys/bluetooth/audio/bap_scan_delegator.c @@ -493,15 +493,20 @@ static int pa_sync_term_request(struct bt_conn *conn, return err; } -static bool bass_source_is_duplicate(uint32_t broadcast_id, uint8_t adv_sid, bt_addr_le_t addr) +/* BAP 6.5.4 states that the Broadcast Assistant shall not initiate the Add Source operation + * if the operation would result in duplicate values for the combined Source_Address_Type, + * Source_Adv_SID, and Broadcast_ID fields of any Broadcast Receive State characteristic exposed + * by the Scan Delegator. + */ +static bool bass_source_is_duplicate(uint32_t broadcast_id, uint8_t adv_sid, uint8_t addr_type) { struct bass_recv_state_internal *state; for (size_t i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) { state = &scan_delegator.recv_states[i]; - if (state != NULL && state->state.broadcast_id == broadcast_id - && state->state.adv_sid == adv_sid && state->state.addr.type == addr.type) { + if (state != NULL && state->state.broadcast_id == broadcast_id && + state->state.adv_sid == adv_sid && state->state.addr.type == addr_type) { LOG_DBG("recv_state already exists at src_id=0x%02X", state->state.src_id); return true; @@ -556,7 +561,7 @@ static int scan_delegator_add_source(struct bt_conn *conn, broadcast_id = net_buf_simple_pull_le24(buf); - if (bass_source_is_duplicate(broadcast_id, state->adv_sid, state->addr)) { + if (bass_source_is_duplicate(broadcast_id, state->adv_sid, state->addr.type)) { LOG_DBG("Adding broadcast_id=0x%06X, adv_sid=0x%02X, and addr.type=0x%02X would " "result in duplication", state->broadcast_id, state->adv_sid, state->addr.type); @@ -664,6 +669,7 @@ static int scan_delegator_add_source(struct bt_conn *conn, if (pa_sync != BT_BAP_BASS_PA_REQ_NO_SYNC) { int err; + err = pa_sync_request(conn, state, pa_sync, pa_interval); if (err != 0) { @@ -1137,11 +1143,10 @@ static ssize_t read_recv_state(struct bt_conn *conn, k_sem_give(&read_buf_sem); return ret_val; - } else { - LOG_DBG("Index %u: Not active", idx); - - return bt_gatt_attr_read(conn, attr, buf, len, offset, NULL, 0); } + LOG_DBG("Index %u: Not active", idx); + return bt_gatt_attr_read(conn, attr, buf, len, offset, NULL, 0); + } #define RECEIVE_STATE_CHARACTERISTIC(idx) \ From 24c03bfacbbbd87588358ce9c6b9b9c9768c925c Mon Sep 17 00:00:00 2001 From: Fabian Kainka Date: Thu, 14 Mar 2024 15:36:32 +0100 Subject: [PATCH 1517/2402] serial: uart_native_tty: Polling thread fix Addresses an issue where attempts to transmit data fail. The identified cause of this failure is the handling of the `rx_irq_enable` and `tx_irq_enable` flags. The `else if` handling the `tx_irq_enable` was replaced by an `if` so both flags can be true, and both functions can be called. This fix was tested with the `cellular_modem` example successfully. Signed-off-by: Fabian Kainka --- drivers/serial/uart_native_tty.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/serial/uart_native_tty.c b/drivers/serial/uart_native_tty.c index dc19f2a10da..8eb51bff5b8 100644 --- a/drivers/serial/uart_native_tty.c +++ b/drivers/serial/uart_native_tty.c @@ -289,9 +289,11 @@ void native_tty_uart_irq_function(void *arg1, void *arg2, void *arg3) } else { k_sleep(K_MSEC(1)); } - } else if (data->tx_irq_enabled) { + } + if (data->tx_irq_enabled) { native_tty_uart_irq_handler(dev); - } else { + } + if (data->tx_irq_enabled == false && data->rx_irq_enabled == false) { k_sleep(K_MSEC(10)); } } From 5c8f357f61c3b57929a8fe48f2164553f2966d21 Mon Sep 17 00:00:00 2001 From: Jordan Yates Date: Fri, 15 Mar 2024 15:14:07 +1000 Subject: [PATCH 1518/2402] west_commands: sign: suppress imgtool prints If `args.quiet` is set, suppress the useless `print` statements output by `imgtool` (mcuboot script) by capturing `stdout`. Old output: ``` [44/44] Linking C executable zephyr/zephyr.elf Memory region Used Size Region Size %age Used FLASH: 415192 B 824 KB 49.21% RAM: 163124 B 256 KB 62.23% IDT_LIST: 0 GB 2 KB 0.00% image.py: sign the payload image.py: sign the payload ``` New output: ``` [44/44] Linking C executable zephyr/zephyr.elf Memory region Used Size Region Size %age Used FLASH: 415192 B 824 KB 49.21% RAM: 163124 B 256 KB 62.23% IDT_LIST: 0 GB 2 KB 0.00% ``` Signed-off-by: Jordan Yates --- scripts/west_commands/sign.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/west_commands/sign.py b/scripts/west_commands/sign.py index fb1de570974..8e9321e46cf 100644 --- a/scripts/west_commands/sign.py +++ b/scripts/west_commands/sign.py @@ -299,7 +299,7 @@ def sign(self, command, build_dir, build_conf, formats): log.inf(f'unsigned bin: {in_bin}') log.inf(f'signed bin: {out_bin}') log.dbg(quote_sh_list(sign_bin)) - subprocess.check_call(sign_bin) + subprocess.check_call(sign_bin, stdout=subprocess.PIPE if args.quiet else None) if in_hex: out_hex = args.shex or str(b / 'zephyr' / 'zephyr.signed.hex') sign_hex = sign_base + [in_hex, out_hex] @@ -307,7 +307,7 @@ def sign(self, command, build_dir, build_conf, formats): log.inf(f'unsigned hex: {in_hex}') log.inf(f'signed hex: {out_hex}') log.dbg(quote_sh_list(sign_hex)) - subprocess.check_call(sign_hex) + subprocess.check_call(sign_hex, stdout=subprocess.PIPE if args.quiet else None) @staticmethod def find_imgtool(command, args): From b17712364cbc6753cb2c3796b7d581a21c06e04f Mon Sep 17 00:00:00 2001 From: Raffael Rostagno Date: Thu, 14 Mar 2024 16:45:57 -0300 Subject: [PATCH 1519/2402] drivers: systimer: Removed mention to ESP32C3 Removed mention to C3 SoC, so files are not SoC specific. Ready for C6 integration. Signed-off-by: Raffael Rostagno --- CODEOWNERS | 2 +- drivers/timer/CMakeLists.txt | 2 +- drivers/timer/Kconfig | 2 +- drivers/timer/{Kconfig.esp32c3_sys => Kconfig.esp32} | 6 +++--- drivers/timer/{esp32c3_sys_timer.c => esp32_sys_timer.c} | 0 soc/espressif/esp32c3/default.ld | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) rename drivers/timer/{Kconfig.esp32c3_sys => Kconfig.esp32} (83%) rename drivers/timer/{esp32c3_sys_timer.c => esp32_sys_timer.c} (100%) diff --git a/CODEOWNERS b/CODEOWNERS index 045a393f7db..0a30b6f34c1 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -380,7 +380,7 @@ /drivers/timer/*leon_gptimer* @julius-barendt /drivers/timer/*mips_cp0* @frantony /drivers/timer/*rcar_cmt* @aaillet -/drivers/timer/*esp32c3_sys* @uLipe +/drivers/timer/*esp32_sys* @uLipe /drivers/timer/*sam0_rtc* @bendiscz /drivers/timer/*arcv2* @ruuddw /drivers/timer/*xtensa* @dcpleung diff --git a/drivers/timer/CMakeLists.txt b/drivers/timer/CMakeLists.txt index 36534e4716f..10edb91416f 100644 --- a/drivers/timer/CMakeLists.txt +++ b/drivers/timer/CMakeLists.txt @@ -11,7 +11,7 @@ zephyr_library_sources_ifdef(CONFIG_ARM_ARCH_TIMER arm_arch_timer.c) zephyr_library_sources_ifdef(CONFIG_INTEL_ADSP_TIMER intel_adsp_timer.c) zephyr_library_sources_ifdef(CONFIG_CC13XX_CC26XX_RTC_TIMER cc13xx_cc26xx_rtc_timer.c) zephyr_library_sources_ifdef(CONFIG_CORTEX_M_SYSTICK cortex_m_systick.c) -zephyr_library_sources_ifdef(CONFIG_ESP32C3_SYS_TIMER esp32c3_sys_timer.c) +zephyr_library_sources_ifdef(CONFIG_ESP32_SYS_TIMER esp32_sys_timer.c) zephyr_library_sources_ifdef(CONFIG_GECKO_BURTC_TIMER gecko_burtc_timer.c) zephyr_library_sources_ifdef(CONFIG_HPET_TIMER hpet.c) zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_TIMER ite_it8xxx2_timer.c) diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index f20442dd2c5..317efd71d8c 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -71,7 +71,7 @@ source "drivers/timer/Kconfig.arm_arch" source "drivers/timer/Kconfig.cavs" source "drivers/timer/Kconfig.cc13xx_cc26xx_rtc" source "drivers/timer/Kconfig.cortex_m_systick" -source "drivers/timer/Kconfig.esp32c3_sys" +source "drivers/timer/Kconfig.esp32" source "drivers/timer/Kconfig.gecko" source "drivers/timer/Kconfig.ite_it8xxx2" source "drivers/timer/Kconfig.leon_gptimer" diff --git a/drivers/timer/Kconfig.esp32c3_sys b/drivers/timer/Kconfig.esp32 similarity index 83% rename from drivers/timer/Kconfig.esp32c3_sys rename to drivers/timer/Kconfig.esp32 index 366cfcd8526..0d45987c726 100644 --- a/drivers/timer/Kconfig.esp32c3_sys +++ b/drivers/timer/Kconfig.esp32 @@ -3,12 +3,12 @@ # Copyright (c) 2019 Intel Corp. # SPDX-License-Identifier: Apache-2.0 -config ESP32C3_SYS_TIMER - bool "ESP32C3 sys-timer support" +config ESP32_SYS_TIMER + bool "ESP32 sys-timer support (ESP32Cx series)" depends on SOC_SERIES_ESP32C3 default y select TICKLESS_CAPABLE select TIMER_HAS_64BIT_CYCLE_COUNTER help - This option enables the system timer driver for the Espressif ESP32C3 + This option enables the system timer driver for the Espressif ESP32Cx and provides the standard "system clock driver" interface. diff --git a/drivers/timer/esp32c3_sys_timer.c b/drivers/timer/esp32_sys_timer.c similarity index 100% rename from drivers/timer/esp32c3_sys_timer.c rename to drivers/timer/esp32_sys_timer.c diff --git a/soc/espressif/esp32c3/default.ld b/soc/espressif/esp32c3/default.ld index 65984b4fd7b..4de4bd310d4 100644 --- a/soc/espressif/esp32c3/default.ld +++ b/soc/espressif/esp32c3/default.ld @@ -238,7 +238,7 @@ SECTIONS *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) - *libdrivers__timer.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:esp32_sys_timer.*(.literal .text .literal.* .text.*) *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) From 353c6a66cb9eef9696ba54154631cca5caee1a56 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Tue, 19 Mar 2024 17:26:23 -0500 Subject: [PATCH 1520/2402] dts: bindings: ethernet: Remove fixed link Remove ethernet-fixed-link binding as it is redundant with the phy bindings. Clearly, ethernet does not work without the L1 layer, which is a phy device, or an integrated mac/phy device, and all of these things should be described properly in DT. The schema did not even come with a compatible, meaning nodelabels were hardcoded into the drivers, which is unacceptable. - Remove the binding file for ethernet-fixed-link.yaml. - Remove fixed link functionality from the nxp s32 gmac driver. Since this functionality is already covered by the phy support, it is redundant. - Remove fixed link include from the s32 gmac binding. - Remove fixed link include from the nuvoton numaker binding. As far as I can tell the corresonding driver does not even use it anyways, and I did not find any board with this device that describes a "fixed link". - Move the definition into the nxp,kinetis-ethernet binding as the eth_mcux driver, which is already being deprecated, does use this, contain the debt to the legacy driver. Signed-off-by: Declan Snyder --- drivers/ethernet/eth_nxp_s32_gmac.c | 32 +++---------------- .../ethernet/ethernet,fixed-link.yaml | 17 ---------- .../ethernet/nuvoton,numaker-ethernet.yaml | 1 - dts/bindings/ethernet/nxp,enet-mac.yaml | 2 +- .../ethernet/nxp,kinetis-ethernet.yaml | 16 +++++++++- dts/bindings/ethernet/nxp,s32-gmac.yaml | 2 +- 6 files changed, 21 insertions(+), 49 deletions(-) delete mode 100644 dts/bindings/ethernet/ethernet,fixed-link.yaml diff --git a/drivers/ethernet/eth_nxp_s32_gmac.c b/drivers/ethernet/eth_nxp_s32_gmac.c index 6a7af367ae2..a64d6c380b4 100644 --- a/drivers/ethernet/eth_nxp_s32_gmac.c +++ b/drivers/ethernet/eth_nxp_s32_gmac.c @@ -649,29 +649,6 @@ BUILD_ASSERT((CONFIG_ETH_NXP_S32_RX_RING_BUF_SIZE % FEATURE_GMAC_DATA_BUS_WIDTH_ BUILD_ASSERT((CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZE % FEATURE_GMAC_DATA_BUS_WIDTH_BYTES) == 0, "CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZE must be multiple of the data bus width"); -#define ETH_NXP_S32_FIXED_LINK_NODE(n) \ - DT_INST_CHILD(n, fixed_link) - -#define ETH_NXP_S32_IS_FIXED_LINK(n) \ - DT_NODE_EXISTS(ETH_NXP_S32_FIXED_LINK_NODE(n)) - -#define ETH_NXP_S32_FIXED_LINK_SPEED(n) \ - DT_PROP(ETH_NXP_S32_FIXED_LINK_NODE(n), speed) - -#define ETH_NXP_S32_FIXED_LINK_FULL_DUPLEX(n) \ - DT_PROP(ETH_NXP_S32_FIXED_LINK_NODE(n), full_duplex) - -#define ETH_NXP_S32_MAC_SPEED(n) \ - COND_CODE_1(ETH_NXP_S32_IS_FIXED_LINK(n), \ - (_CONCAT(_CONCAT(GMAC_SPEED_, ETH_NXP_S32_FIXED_LINK_SPEED(n)), M)), \ - (GMAC_SPEED_100M)) - -#define ETH_NXP_S32_MAC_DUPLEX(n) \ - COND_CODE_1(ETH_NXP_S32_IS_FIXED_LINK(n), \ - (COND_CODE_1(ETH_NXP_S32_FIXED_LINK_FULL_DUPLEX(n), \ - (GMAC_FULL_DUPLEX), (GMAC_HALF_DUPLEX))), \ - (GMAC_FULL_DUPLEX)) - #define ETH_NXP_S32_MAC_MII(n) \ _CONCAT(_CONCAT(GMAC_, DT_INST_STRING_UPPER_TOKEN(n, phy_connection_type)), _MODE) @@ -803,8 +780,8 @@ BUILD_ASSERT((CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZE % FEATURE_GMAC_DATA_BUS_WIDTH_ .Callback = NULL, \ .TxSchedAlgo = GMAC_SCHED_ALGO_SP, \ .MiiMode = ETH_NXP_S32_MAC_MII(n), \ - .Speed = ETH_NXP_S32_MAC_SPEED(n), \ - .Duplex = ETH_NXP_S32_MAC_DUPLEX(n), \ + .Speed = GMAC_SPEED_100M, \ + .Duplex = GMAC_FULL_DUPLEX, \ .MacConfig = ETH_NXP_S32_MAC_CONF(n), \ .MacPktFilterConfig = ETH_NXP_S32_MAC_PKT_FILTER(n), \ .EnableCtrl = false, \ @@ -837,9 +814,8 @@ BUILD_ASSERT((CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZE % FEATURE_GMAC_DATA_BUS_WIDTH_ ETH_NXP_S32_HW_INSTANCE_CHECK, (|), n) #define ETH_NXP_S32_PHY_DEV(n) \ - COND_CODE_1(ETH_NXP_S32_IS_FIXED_LINK(n), NULL, \ - (COND_CODE_1(DT_INST_NODE_HAS_PROP(n, phy_handle), \ - (DEVICE_DT_GET(DT_INST_PHANDLE(n, phy_handle))), NULL))) + (COND_CODE_1(DT_INST_NODE_HAS_PROP(n, phy_handle), \ + (DEVICE_DT_GET(DT_INST_PHANDLE(n, phy_handle))), NULL)) #define ETH_NXP_S32_DEVICE(n) \ ETH_NXP_S32_TX_CALLBACK(n) \ diff --git a/dts/bindings/ethernet/ethernet,fixed-link.yaml b/dts/bindings/ethernet/ethernet,fixed-link.yaml deleted file mode 100644 index 27c5147acfd..00000000000 --- a/dts/bindings/ethernet/ethernet,fixed-link.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2020, DENX Software Engineering GmbH -# Lukasz Majewski -# SPDX-License-Identifier: Apache-2.0 - -child-binding: - description: Fixed link ethernet node - properties: - speed: - type: int - required: true - description: The speed of fixed link - enum: - - 100 - - 10 - full-duplex: - type: boolean - description: The fixed link operates in full duplex mode diff --git a/dts/bindings/ethernet/nuvoton,numaker-ethernet.yaml b/dts/bindings/ethernet/nuvoton,numaker-ethernet.yaml index 4cdf35c4f60..18d19a45b83 100644 --- a/dts/bindings/ethernet/nuvoton,numaker-ethernet.yaml +++ b/dts/bindings/ethernet/nuvoton,numaker-ethernet.yaml @@ -7,7 +7,6 @@ compatible: "nuvoton,numaker-ethernet" include: - ethernet-controller.yaml - - ethernet,fixed-link.yaml - reset-device.yaml - pinctrl-device.yaml diff --git a/dts/bindings/ethernet/nxp,enet-mac.yaml b/dts/bindings/ethernet/nxp,enet-mac.yaml index 8ca42e769f3..bbcc2b49362 100644 --- a/dts/bindings/ethernet/nxp,enet-mac.yaml +++ b/dts/bindings/ethernet/nxp,enet-mac.yaml @@ -5,7 +5,7 @@ description: NXP ENET MAC/L2 Device compatible: "nxp,enet-mac" -include: ["ethernet-controller.yaml", "ethernet,fixed-link.yaml", "pinctrl-device.yaml"] +include: ["ethernet-controller.yaml", "pinctrl-device.yaml"] properties: interrupts: diff --git a/dts/bindings/ethernet/nxp,kinetis-ethernet.yaml b/dts/bindings/ethernet/nxp,kinetis-ethernet.yaml index 84e0e009f7a..d6b1d71b1aa 100644 --- a/dts/bindings/ethernet/nxp,kinetis-ethernet.yaml +++ b/dts/bindings/ethernet/nxp,kinetis-ethernet.yaml @@ -5,7 +5,7 @@ description: NXP Kinetis Ethernet compatible: "nxp,kinetis-ethernet" -include: ["ethernet-controller.yaml", "ethernet,fixed-link.yaml", "pinctrl-device.yaml"] +include: ["ethernet-controller.yaml", "pinctrl-device.yaml"] properties: reg: @@ -23,3 +23,17 @@ properties: type: phandle-array description: interrupt GPIO for PHY. Will be pulled high before reset is asserted. + +child-binding: + description: Fixed link ethernet node + properties: + speed: + type: int + required: true + description: The speed of fixed link + enum: + - 100 + - 10 + full-duplex: + type: boolean + description: The fixed link operates in full duplex mode diff --git a/dts/bindings/ethernet/nxp,s32-gmac.yaml b/dts/bindings/ethernet/nxp,s32-gmac.yaml index 7767a755f39..c17a5331bdc 100644 --- a/dts/bindings/ethernet/nxp,s32-gmac.yaml +++ b/dts/bindings/ethernet/nxp,s32-gmac.yaml @@ -5,7 +5,7 @@ description: NXP S32 GMAC/EMAC driver compatible: "nxp,s32-gmac" -include: [ethernet-controller.yaml, "ethernet,fixed-link.yaml", pinctrl-device.yaml] +include: [ethernet-controller.yaml, pinctrl-device.yaml] properties: reg: From f419ea7990998ee13476d5c206a6bdb83a4a0567 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Wed, 20 Mar 2024 18:42:32 +0800 Subject: [PATCH 1521/2402] runner: linkerserver : remove the probe ID hardcode linkserver is hardcoded to probe ID, now with #70343 merged the probe ID restriction can be removed. Signed-off-by: Hake Huang --- scripts/west_commands/runners/linkserver.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/scripts/west_commands/runners/linkserver.py b/scripts/west_commands/runners/linkserver.py index a4ae5c622d4..c1631d391af 100644 --- a/scripts/west_commands/runners/linkserver.py +++ b/scripts/west_commands/runners/linkserver.py @@ -25,7 +25,7 @@ class LinkServerBinaryRunner(ZephyrBinaryRunner): def __init__(self, cfg, device, core, linkserver=DEFAULT_LINKSERVER_EXE, dt_flash=True, erase=True, - probe=1, + probe='#1', gdb_host='', gdb_port=DEFAULT_LINKSERVER_GDB_PORT, semihost_port=DEFAULT_LINKSERVER_SEMIHOST_PORT, @@ -71,8 +71,8 @@ def do_add_parser(cls, parser): parser.add_argument('--core', required=False, help='core of the device') - parser.add_argument('--probe', default=1, - help='interface to use (index, no serial number), default is 1') + parser.add_argument('--probe', default='#1', + help='interface to use (index, or serial number, default is #1') parser.add_argument('--tui', default=False, action='store_true', help='if given, GDB uses -tui') @@ -169,7 +169,7 @@ def do_erase(self, **kwargs): else: _cmd_core = "" - linkserver_cmd = ([self.linkserver, "flash"] + ["--probe", "#"+str(self.probe)] + + linkserver_cmd = ([self.linkserver, "flash"] + ["--probe", str(self.probe)] + [self.device+_cmd_core] + ["erase"]) self.logger.debug("flash erase command = " + str(linkserver_cmd)) self.check_call(linkserver_cmd) @@ -191,7 +191,7 @@ def flash(self, **kwargs): else: _cmd_core = "" - linkserver_cmd = ([self.linkserver, "flash"] + ["--probe", "#"+str(self.probe)] + self.override_cli + [self.device+_cmd_core]) + linkserver_cmd = ([self.linkserver, "flash"] + ["--probe", str(self.probe)] + self.override_cli + [self.device+_cmd_core]) self.logger.debug(f'LinkServer cmd: + {linkserver_cmd}') if self.erase: From 3eeb0f0c7fac4546b5592608dc84ffb723cd44b5 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 7 Mar 2024 17:09:39 +0200 Subject: [PATCH 1522/2402] net: sockets: Deprecate CONFIG_NET_SOCKETS_POSIX_NAMES The CONFIG_NET_SOCKETS_POSIX_NAMES option is marked as deprecated in favor of using normal POSIX socket API includes found under the include/zephyr/posix directory. If you want to use BSD socket API calls, you need to select POSIX_API and use the socket headers found in the POSIX subsystem. If you do not want to or cannot enable POSIX_API, then you must use zsock_ prefix when working with BSD socket calls. Signed-off-by: Jukka Rissanen --- subsys/net/lib/sockets/Kconfig | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/subsys/net/lib/sockets/Kconfig b/subsys/net/lib/sockets/Kconfig index 36b42a3b4ad..8f7996a93bd 100644 --- a/subsys/net/lib/sockets/Kconfig +++ b/subsys/net/lib/sockets/Kconfig @@ -22,10 +22,15 @@ config NET_SOCKETS_PRIORITY_DEFAULT socket creation over the native one, or vice versa. config NET_SOCKETS_POSIX_NAMES - bool "POSIX names for Sockets API (without full POSIX API)" - default y if !POSIX_API + bool "[DEPRECATED] POSIX names for Sockets API (without full POSIX API)" depends on !POSIX_API + select DEPRECATED help + This option is marked as deprecated in favor of using normal + POSIX socket API includes found under the include/zephyr/posix + directory. If you want to use BSD socket API calls, you need + to select POSIX_API and use the socket headers in POSIX subsystem. + With this option, Socket API functions are available under the standard POSIX names like socket(), recv(), and close(), etc., even if full POSIX API (CONFIG_POSIX_API) is not enabled. (Note From dc203f0d75e679d88215aab289e1ccd25fd05a57 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 7 Mar 2024 17:43:30 +0200 Subject: [PATCH 1523/2402] net: socket: Rework the zephyr/net/socket.h header Avoid circular inclusion of socket related header files. This way applications can still continue to include zephyr/net/socket.h and not need to separately include POSIX socket headers. Signed-off-by: Jukka Rissanen --- include/zephyr/net/socket.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/include/zephyr/net/socket.h b/include/zephyr/net/socket.h index bdbbd3b19e5..ad217e425b9 100644 --- a/include/zephyr/net/socket.h +++ b/include/zephyr/net/socket.h @@ -1361,4 +1361,27 @@ struct net_socket_register { * @} */ +/* Avoid circular loops with POSIX socket headers. + * We have these includes here so that we do not need + * to change the applications that were only including + * zephyr/net/socket.h header file. + */ +#if defined(CONFIG_POSIX_API) +#if !defined(ZEPHYR_INCLUDE_POSIX_ARPA_INET_H_) +#include +#endif +#if !defined(ZEPHYR_INCLUDE_POSIX_NETDB_H_) +#include +#endif +#if !defined(ZEPHYR_INCLUDE_POSIX_UNISTD_H_) +#include +#endif +#if !defined(ZEPHYR_INCLUDE_POSIX_POLL_H_) +#include +#endif +#if !defined(ZEPHYR_INCLUDE_POSIX_SYS_SOCKET_H_) +#include +#endif +#endif /* CONFIG_POSIX_API */ + #endif /* ZEPHYR_INCLUDE_NET_SOCKET_H_ */ From e6e6bb4242999cd9bc26255b17d51ded13364592 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 7 Mar 2024 19:16:19 +0200 Subject: [PATCH 1524/2402] net: socket: Create zsock_fcntl and fsock_ioctl functions Have special wrappers for zsock_fcntl and zsock_ioctl functions so that gcc warning can be avoided. Signed-off-by: Jukka Rissanen --- include/zephyr/net/socket.h | 67 ++++++++++++++++---------------- subsys/net/lib/sockets/sockets.c | 16 ++++---- 2 files changed, 41 insertions(+), 42 deletions(-) diff --git a/include/zephyr/net/socket.h b/include/zephyr/net/socket.h index ad217e425b9..7fbe7c740e5 100644 --- a/include/zephyr/net/socket.h +++ b/include/zephyr/net/socket.h @@ -559,7 +559,24 @@ static inline ssize_t zsock_recv(int sock, void *buf, size_t max_len, * it may conflict with generic POSIX ``fcntl()`` function). * @endrst */ -__syscall int zsock_fcntl(int sock, int cmd, int flags); +__syscall int zsock_fcntl_impl(int sock, int cmd, int flags); + +/* + * Need this wrapper because newer GCC versions got too smart and "typecheck" + * even macros. + */ +static inline int zsock_fcntl_wrapper(int sock, int cmd, ...) +{ + va_list args; + int flags; + + va_start(args, cmd); + flags = va_arg(args, int); + va_end(args); + return zsock_fcntl_impl(sock, cmd, flags); +} + +#define zsock_fcntl zsock_fcntl_wrapper /** * @brief Control underlying socket parameters @@ -578,7 +595,21 @@ __syscall int zsock_fcntl(int sock, int cmd, int flags); * it may conflict with generic POSIX ``ioctl()`` function). * @endrst */ -__syscall int zsock_ioctl(int sock, unsigned long request, va_list ap); +__syscall int zsock_ioctl_impl(int sock, unsigned long request, va_list ap); + +static inline int zsock_ioctl_wrapper(int sock, unsigned long request, ...) +{ + int ret; + va_list args; + + va_start(args, request); + ret = zsock_ioctl_impl(sock, request, args); + va_end(args); + + return ret; +} + +#define zsock_ioctl zsock_ioctl_wrapper /** * @brief Efficiently poll multiple sockets for events @@ -890,38 +921,6 @@ static inline ssize_t recv(int sock, void *buf, size_t max_len, int flags) return zsock_recv(sock, buf, max_len, flags); } -/** @cond INTERNAL_HIDDEN */ -/* - * Need this wrapper because newer GCC versions got too smart and "typecheck" - * even macros, so '#define fcntl zsock_fcntl' leads to error. - */ -static inline int zsock_fcntl_wrapper(int sock, int cmd, ...) -{ - va_list args; - int flags; - - va_start(args, cmd); - flags = va_arg(args, int); - va_end(args); - return zsock_fcntl(sock, cmd, flags); -} - -#define fcntl zsock_fcntl_wrapper -/** @endcond */ - -/** POSIX wrapper for @ref zsock_ioctl */ -static inline int ioctl(int sock, unsigned long request, ...) -{ - int ret; - va_list args; - - va_start(args, request); - ret = zsock_ioctl(sock, request, args); - va_end(args); - - return ret; -} - /** POSIX wrapper for @ref zsock_sendto */ static inline ssize_t sendto(int sock, const void *buf, size_t len, int flags, const struct sockaddr *dest_addr, diff --git a/subsys/net/lib/sockets/sockets.c b/subsys/net/lib/sockets/sockets.c index 8fb5b4c6427..8bd0f63c903 100644 --- a/subsys/net/lib/sockets/sockets.c +++ b/subsys/net/lib/sockets/sockets.c @@ -2027,7 +2027,7 @@ ssize_t z_vrfy_zsock_recvmsg(int sock, struct msghdr *msg, int flags) /* As this is limited function, we don't follow POSIX signature, with * "..." instead of last arg. */ -int z_impl_zsock_fcntl(int sock, int cmd, int flags) +int z_impl_zsock_fcntl_impl(int sock, int cmd, int flags) { const struct socket_op_vtable *vtable; struct k_mutex *lock; @@ -2051,14 +2051,14 @@ int z_impl_zsock_fcntl(int sock, int cmd, int flags) } #ifdef CONFIG_USERSPACE -static inline int z_vrfy_zsock_fcntl(int sock, int cmd, int flags) +static inline int z_vrfy_zsock_fcntl_impl(int sock, int cmd, int flags) { - return z_impl_zsock_fcntl(sock, cmd, flags); + return z_impl_zsock_fcntl_impl(sock, cmd, flags); } -#include +#include #endif -int z_impl_zsock_ioctl(int sock, unsigned long request, va_list args) +int z_impl_zsock_ioctl_impl(int sock, unsigned long request, va_list args) { const struct socket_op_vtable *vtable; struct k_mutex *lock; @@ -2084,7 +2084,7 @@ int z_impl_zsock_ioctl(int sock, unsigned long request, va_list args) } #ifdef CONFIG_USERSPACE -static inline int z_vrfy_zsock_ioctl(int sock, unsigned long request, va_list args) +static inline int z_vrfy_zsock_ioctl_impl(int sock, unsigned long request, va_list args) { switch (request) { case ZFD_IOCTL_FIONBIO: @@ -2104,9 +2104,9 @@ static inline int z_vrfy_zsock_ioctl(int sock, unsigned long request, va_list ar return -1; } - return z_impl_zsock_ioctl(sock, request, args); + return z_impl_zsock_ioctl_impl(sock, request, args); } -#include +#include #endif static int zsock_poll_prepare_ctx(struct net_context *ctx, From 4a128c0d2ae317d691696fe2184bc702cc47daba Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 7 Mar 2024 18:22:13 +0200 Subject: [PATCH 1525/2402] net: sockets: Fix the documentation to use POSIX_API Fix the documentation and promote POSIX_API instead of NET_SOCKET_POSIX_NAMES Signed-off-by: Jukka Rissanen --- include/zephyr/net/socket.h | 56 +++++++++++++++--------------- include/zephyr/net/socket_select.h | 10 +++--- 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/include/zephyr/net/socket.h b/include/zephyr/net/socket.h index 7fbe7c740e5..1800533a250 100644 --- a/include/zephyr/net/socket.h +++ b/include/zephyr/net/socket.h @@ -340,7 +340,7 @@ __syscall void *zsock_get_context_object(int sock); * `__ * for normative description. * This function is also exposed as ``socket()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst * * If CONFIG_USERSPACE is enabled, the caller will be granted access to the @@ -359,7 +359,7 @@ __syscall int zsock_socket(int family, int type, int proto); * `__ * for normative description. * This function is also exposed as ``socketpair()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_socketpair(int family, int type, int proto, int *sv); @@ -371,7 +371,7 @@ __syscall int zsock_socketpair(int family, int type, int proto, int *sv); * @rst * Close a network socket. * This function is also exposed as ``close()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined (in which case it + * if :kconfig:option:`CONFIG_POSIX_API` is defined (in which case it * may conflict with generic POSIX ``close()`` function). * @endrst */ @@ -387,7 +387,7 @@ __syscall int zsock_close(int sock); * for normative description, but currently this function has no effect in * Zephyr and provided solely for compatibility with existing code. * This function is also exposed as ``shutdown()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_shutdown(int sock, int how); @@ -401,7 +401,7 @@ __syscall int zsock_shutdown(int sock, int how); * `__ * for normative description. * This function is also exposed as ``bind()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_bind(int sock, const struct sockaddr *addr, @@ -416,7 +416,7 @@ __syscall int zsock_bind(int sock, const struct sockaddr *addr, * `__ * for normative description. * This function is also exposed as ``connect()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_connect(int sock, const struct sockaddr *addr, @@ -431,7 +431,7 @@ __syscall int zsock_connect(int sock, const struct sockaddr *addr, * `__ * for normative description. * This function is also exposed as ``listen()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_listen(int sock, int backlog); @@ -445,7 +445,7 @@ __syscall int zsock_listen(int sock, int backlog); * `__ * for normative description. * This function is also exposed as ``accept()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_accept(int sock, struct sockaddr *addr, socklen_t *addrlen); @@ -459,7 +459,7 @@ __syscall int zsock_accept(int sock, struct sockaddr *addr, socklen_t *addrlen); * `__ * for normative description. * This function is also exposed as ``sendto()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall ssize_t zsock_sendto(int sock, const void *buf, size_t len, @@ -475,7 +475,7 @@ __syscall ssize_t zsock_sendto(int sock, const void *buf, size_t len, * `__ * for normative description. * This function is also exposed as ``send()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ static inline ssize_t zsock_send(int sock, const void *buf, size_t len, @@ -493,7 +493,7 @@ static inline ssize_t zsock_send(int sock, const void *buf, size_t len, * `__ * for normative description. * This function is also exposed as ``sendmsg()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall ssize_t zsock_sendmsg(int sock, const struct msghdr *msg, @@ -508,7 +508,7 @@ __syscall ssize_t zsock_sendmsg(int sock, const struct msghdr *msg, * `__ * for normative description. * This function is also exposed as ``recvfrom()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall ssize_t zsock_recvfrom(int sock, void *buf, size_t max_len, @@ -524,7 +524,7 @@ __syscall ssize_t zsock_recvfrom(int sock, void *buf, size_t max_len, * `__ * for normative description. * This function is also exposed as ``recvmsg()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall ssize_t zsock_recvmsg(int sock, struct msghdr *msg, int flags); @@ -538,7 +538,7 @@ __syscall ssize_t zsock_recvmsg(int sock, struct msghdr *msg, int flags); * `__ * for normative description. * This function is also exposed as ``recv()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ static inline ssize_t zsock_recv(int sock, void *buf, size_t max_len, @@ -555,7 +555,7 @@ static inline ssize_t zsock_recv(int sock, void *buf, size_t max_len, * This functions allow to (only) configure a socket for blocking or * non-blocking operation (O_NONBLOCK). * This function is also exposed as ``fcntl()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined (in which case + * if :kconfig:option:`CONFIG_POSIX_API` is defined (in which case * it may conflict with generic POSIX ``fcntl()`` function). * @endrst */ @@ -591,7 +591,7 @@ static inline int zsock_fcntl_wrapper(int sock, int cmd, ...) * ``ZFD_IOCTL_FIONREAD``, to set non-blocking mode, and query the number of * bytes available to read, respectively. * This function is also exposed as ``ioctl()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined (in which case + * if :kconfig:option:`CONFIG_POSIX_API` is defined (in which case * it may conflict with generic POSIX ``ioctl()`` function). * @endrst */ @@ -620,7 +620,7 @@ static inline int zsock_ioctl_wrapper(int sock, unsigned long request, ...) * `__ * for normative description. * This function is also exposed as ``poll()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined (in which case + * if :kconfig:option:`CONFIG_POSIX_API` is defined (in which case * it may conflict with generic POSIX ``poll()`` function). * @endrst */ @@ -638,7 +638,7 @@ __syscall int zsock_poll(struct zsock_pollfd *fds, int nfds, int timeout); * available in Linux (some options are dummy and provided to ease porting * of existing code). * This function is also exposed as ``getsockopt()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_getsockopt(int sock, int level, int optname, @@ -656,7 +656,7 @@ __syscall int zsock_getsockopt(int sock, int level, int optname, * available in Linux (some options are dummy and provided to ease porting * of existing code). * This function is also exposed as ``setsockopt()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_setsockopt(int sock, int level, int optname, @@ -671,7 +671,7 @@ __syscall int zsock_setsockopt(int sock, int level, int optname, * `__ * for normative description. * This function is also exposed as ``getpeername()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_getpeername(int sock, struct sockaddr *addr, @@ -686,7 +686,7 @@ __syscall int zsock_getpeername(int sock, struct sockaddr *addr, * `__ * for normative description. * This function is also exposed as ``getsockname()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_getsockname(int sock, struct sockaddr *addr, @@ -701,7 +701,7 @@ __syscall int zsock_getsockname(int sock, struct sockaddr *addr, * `__ * for normative description. * This function is also exposed as ``gethostname()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_gethostname(char *buf, size_t len); @@ -715,7 +715,7 @@ __syscall int zsock_gethostname(char *buf, size_t len); * `__ * for normative description. * This function is also exposed as ``inet_ntop()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ static inline char *zsock_inet_ntop(sa_family_t family, const void *src, @@ -733,7 +733,7 @@ static inline char *zsock_inet_ntop(sa_family_t family, const void *src, * `__ * for normative description. * This function is also exposed as ``inet_pton()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ __syscall int zsock_inet_pton(sa_family_t family, const char *src, void *dst); @@ -776,7 +776,7 @@ __syscall int z_zsock_getaddrinfo_internal(const char *host, * `__ * for normative description. * This function is also exposed as ``getaddrinfo()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ int zsock_getaddrinfo(const char *host, const char *service, @@ -792,7 +792,7 @@ int zsock_getaddrinfo(const char *host, const char *service, * `__ * for normative description. * This function is also exposed as ``freeaddrinfo()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ void zsock_freeaddrinfo(struct zsock_addrinfo *ai); @@ -806,7 +806,7 @@ void zsock_freeaddrinfo(struct zsock_addrinfo *ai); * `__ * for normative description. * This function is also exposed as ``gai_strerror()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ const char *zsock_gai_strerror(int errcode); @@ -843,7 +843,7 @@ const char *zsock_gai_strerror(int errcode); * `__ * for normative description. * This function is also exposed as ``getnameinfo()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ int zsock_getnameinfo(const struct sockaddr *addr, socklen_t addrlen, diff --git a/include/zephyr/net/socket_select.h b/include/zephyr/net/socket_select.h index f9469a7c7fe..1e7507711a1 100644 --- a/include/zephyr/net/socket_select.h +++ b/include/zephyr/net/socket_select.h @@ -38,7 +38,7 @@ typedef struct zsock_fd_set { * use zsock_poll() instead. In Zephyr this function works only with * sockets, not arbitrary file descriptors. * This function is also exposed as ``select()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined (in which case + * if :kconfig:option:`CONFIG_POSIX_API` is defined (in which case * it may conflict with generic POSIX ``select()`` function). * @endrst */ @@ -59,7 +59,7 @@ __syscall int zsock_select(int nfds, zsock_fd_set *readfds, * `__ * for normative description. * This function is also exposed as ``FD_ZERO()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ void ZSOCK_FD_ZERO(zsock_fd_set *set); @@ -73,7 +73,7 @@ void ZSOCK_FD_ZERO(zsock_fd_set *set); * `__ * for normative description. * This function is also exposed as ``FD_ISSET()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ int ZSOCK_FD_ISSET(int fd, zsock_fd_set *set); @@ -87,7 +87,7 @@ int ZSOCK_FD_ISSET(int fd, zsock_fd_set *set); * `__ * for normative description. * This function is also exposed as ``FD_CLR()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ void ZSOCK_FD_CLR(int fd, zsock_fd_set *set); @@ -101,7 +101,7 @@ void ZSOCK_FD_CLR(int fd, zsock_fd_set *set); * `__ * for normative description. * This function is also exposed as ``FD_SET()`` - * if :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined. + * if :kconfig:option:`CONFIG_POSIX_API` is defined. * @endrst */ void ZSOCK_FD_SET(int fd, zsock_fd_set *set); From 79585d5355a35e2a1827f1e5c8ff03694ff98ba1 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 7 Mar 2024 17:58:41 +0200 Subject: [PATCH 1526/2402] net: tftp: Use zsock_ API functions The library should be using internal socket API functions so that we do not need to depend on POSIX_API inside the network stack. Signed-off-by: Jukka Rissanen --- subsys/net/lib/tftp/Kconfig | 1 - subsys/net/lib/tftp/tftp_client.c | 40 +++++++++++++++---------------- 2 files changed, 20 insertions(+), 21 deletions(-) diff --git a/subsys/net/lib/tftp/Kconfig b/subsys/net/lib/tftp/Kconfig index aeb518c0f12..4a5957bccd7 100644 --- a/subsys/net/lib/tftp/Kconfig +++ b/subsys/net/lib/tftp/Kconfig @@ -6,7 +6,6 @@ config TFTP_LIB bool "Socket TFTP Library Support [EXPERIMENTAL]" select NET_SOCKETS - select NET_SOCKETS_POSIX_NAMES select EXPERIMENTAL help Enable the Zephyr TFTP Library diff --git a/subsys/net/lib/tftp/tftp_client.c b/subsys/net/lib/tftp/tftp_client.c index c6f9a371d6b..d26172f0e3f 100644 --- a/subsys/net/lib/tftp/tftp_client.c +++ b/subsys/net/lib/tftp/tftp_client.c @@ -55,7 +55,7 @@ static int send_data(int sock, struct tftpc *client, uint32_t block_no, const ui { int ret; int send_count = 0, ack_count = 0; - struct pollfd fds = { + struct zsock_pollfd fds = { .fd = sock, .events = ZSOCK_POLLIN, }; @@ -73,7 +73,7 @@ static int send_data(int sock, struct tftpc *client, uint32_t block_no, const ui sys_put_be16(block_no, client->tftp_buf + 2); memcpy(client->tftp_buf + TFTP_HEADER_SIZE, data_buffer, data_size); - ret = send(sock, client->tftp_buf, data_size + TFTP_HEADER_SIZE, 0); + ret = zsock_send(sock, client->tftp_buf, data_size + TFTP_HEADER_SIZE, 0); if (ret < 0) { LOG_ERR("send() error: %d", -errno); return -errno; @@ -85,7 +85,7 @@ static int send_data(int sock, struct tftpc *client, uint32_t block_no, const ui break; } - ret = poll(&fds, 1, CONFIG_TFTPC_REQUEST_TIMEOUT); + ret = zsock_poll(&fds, 1, CONFIG_TFTPC_REQUEST_TIMEOUT); if (ret < 0) { LOG_ERR("recv() error: %d", -errno); return -errno; /* IO error */ @@ -93,7 +93,7 @@ static int send_data(int sock, struct tftpc *client, uint32_t block_no, const ui break; /* no response, re-send data */ } - ret = recv(sock, client->tftp_buf, TFTPC_MAX_BUF_SIZE, 0); + ret = zsock_recv(sock, client->tftp_buf, TFTPC_MAX_BUF_SIZE, 0); if (ret < 0) { LOG_ERR("recv() error: %d", -errno); return -errno; @@ -166,7 +166,7 @@ static inline int send_err(int sock, struct tftpc *client, int err_code, char *e } /* Send Error to server. */ - return send(sock, client->tftp_buf, req_size, 0); + return zsock_send(sock, client->tftp_buf, req_size, 0); } /* @@ -176,7 +176,7 @@ static inline int send_ack(int sock, struct tftphdr_ack *ackhdr) { LOG_DBG("Client acking block number: %d", ntohs(ackhdr->block)); - return send(sock, ackhdr, sizeof(struct tftphdr_ack), 0); + return zsock_send(sock, ackhdr, sizeof(struct tftphdr_ack), 0); } static int send_request(int sock, struct tftpc *client, @@ -196,19 +196,19 @@ static int send_request(int sock, struct tftpc *client, remote_file); /* Send the request to the server */ - ret = sendto(sock, client->tftp_buf, req_size, 0, &client->server, - ADDRLEN(client->server)); + ret = zsock_sendto(sock, client->tftp_buf, req_size, 0, &client->server, + ADDRLEN(client->server)); if (ret < 0) { break; } /* Poll for the response */ - struct pollfd fds = { + struct zsock_pollfd fds = { .fd = sock, .events = ZSOCK_POLLIN, }; - ret = poll(&fds, 1, CONFIG_TFTPC_REQUEST_TIMEOUT); + ret = zsock_poll(&fds, 1, CONFIG_TFTPC_REQUEST_TIMEOUT); if (ret <= 0) { LOG_DBG("Failed to get data from the TFTP Server" ", req. no. %d", tx_count); @@ -219,8 +219,8 @@ static int send_request(int sock, struct tftpc *client, struct sockaddr from_addr; socklen_t from_addr_len = sizeof(from_addr); - ret = recvfrom(sock, client->tftp_buf, TFTPC_MAX_BUF_SIZE, 0, - &from_addr, &from_addr_len); + ret = zsock_recvfrom(sock, client->tftp_buf, TFTPC_MAX_BUF_SIZE, 0, + &from_addr, &from_addr_len); if (ret < TFTP_HEADER_SIZE) { req_size = make_request(client->tftp_buf, request, remote_file, mode); @@ -228,7 +228,7 @@ static int send_request(int sock, struct tftpc *client, } /* Limit communication to the specific address:port */ - if (connect(sock, &from_addr, from_addr_len) < 0) { + if (zsock_connect(sock, &from_addr, from_addr_len) < 0) { ret = -errno; LOG_ERR("connect failed, err %d", ret); break; @@ -258,7 +258,7 @@ int tftp_get(struct tftpc *client, const char *remote_file, const char *mode) return -EINVAL; } - sock = socket(client->server.sa_family, SOCK_DGRAM, IPPROTO_UDP); + sock = zsock_socket(client->server.sa_family, SOCK_DGRAM, IPPROTO_UDP); if (sock < 0) { LOG_ERR("Failed to create UDP socket: %d", errno); return -errno; @@ -338,7 +338,7 @@ int tftp_get(struct tftpc *client, const char *remote_file, const char *mode) } /* Poll for the response */ - struct pollfd fds = { + struct zsock_pollfd fds = { .fd = sock, .events = ZSOCK_POLLIN, }; @@ -353,10 +353,10 @@ int tftp_get(struct tftpc *client, const char *remote_file, const char *mode) /* Send ACK to the TFTP Server */ (void)send_ack(sock, &ackhdr); tx_count++; - } while (poll(&fds, 1, CONFIG_TFTPC_REQUEST_TIMEOUT) <= 0); + } while (zsock_poll(&fds, 1, CONFIG_TFTPC_REQUEST_TIMEOUT) <= 0); /* Receive data from the TFTP Server. */ - ret = recv(sock, client->tftp_buf, TFTPC_MAX_BUF_SIZE, 0); + ret = zsock_recv(sock, client->tftp_buf, TFTPC_MAX_BUF_SIZE, 0); rcv_size = ret; } @@ -365,7 +365,7 @@ int tftp_get(struct tftpc *client, const char *remote_file, const char *mode) } get_end: - close(sock); + zsock_close(sock); return ret; } @@ -383,7 +383,7 @@ int tftp_put(struct tftpc *client, const char *remote_file, const char *mode, return -EINVAL; } - sock = socket(client->server.sa_family, SOCK_DGRAM, IPPROTO_UDP); + sock = zsock_socket(client->server.sa_family, SOCK_DGRAM, IPPROTO_UDP); if (sock < 0) { LOG_ERR("Failed to create UDP socket: %d", errno); return -errno; @@ -449,6 +449,6 @@ int tftp_put(struct tftpc *client, const char *remote_file, const char *mode, } while (true); put_end: - close(sock); + zsock_close(sock); return ret; } From de52f8924fdb1e88aa44fbcfc9d7a7bf0c7a8ad6 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 7 Mar 2024 18:06:38 +0200 Subject: [PATCH 1527/2402] net: socks: Remove socket selection Currently the socks library does not use sockets so there is no need to select socket symbols. Signed-off-by: Jukka Rissanen --- subsys/net/lib/socks/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/subsys/net/lib/socks/Kconfig b/subsys/net/lib/socks/Kconfig index b30e2ca2704..22c5dec0610 100644 --- a/subsys/net/lib/socks/Kconfig +++ b/subsys/net/lib/socks/Kconfig @@ -3,8 +3,6 @@ menuconfig SOCKS bool "SOCKS5 proxy" - select NET_SOCKETS - select NET_SOCKETS_POSIX_NAMES help Enable SOCKS5 proxy support From 1b07425eadc63296fae21ea4350704236ad42449 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 07:59:21 +0200 Subject: [PATCH 1528/2402] net: websocket: Use zsock_ API calls Use zsock_ API calls so that we do not need to enable POSIX_API. Signed-off-by: Jukka Rissanen --- subsys/net/lib/websocket/websocket.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/subsys/net/lib/websocket/websocket.c b/subsys/net/lib/websocket/websocket.c index 811f89c5b28..8f463285c25 100644 --- a/subsys/net/lib/websocket/websocket.c +++ b/subsys/net/lib/websocket/websocket.c @@ -397,7 +397,7 @@ int websocket_connect(int sock, struct websocket_request *wreq, out: if (fd >= 0) { - (void)close(fd); + (void)zsock_close(fd); } websocket_context_unref(ctx); @@ -406,7 +406,7 @@ int websocket_connect(int sock, struct websocket_request *wreq, int websocket_disconnect(int ws_sock) { - return close(ws_sock); + return zsock_close(ws_sock); } static int websocket_interal_disconnect(struct websocket_context *ctx) @@ -963,8 +963,8 @@ int websocket_recv_msg(int ws_sock, uint8_t *buf, size_t buf_len, ret = wait_rx(ctx->real_sock, timeout_to_ms(&tout)); if (ret == 0) { - ret = recv(ctx->real_sock, ctx->recv_buf.buf, - ctx->recv_buf.size, MSG_DONTWAIT); + ret = zsock_recv(ctx->real_sock, ctx->recv_buf.buf, + ctx->recv_buf.size, MSG_DONTWAIT); if (ret < 0) { ret = -errno; } From d67fb8321c91c5e3583fc4fb1c489199331a03e8 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 07:23:47 +0200 Subject: [PATCH 1529/2402] tests: net: socket: tls_ext: Use POSIX_API The test expects to use various POSIX APIs so enable the config. Enabling POSIX_API requires also increase of max file descriptors. Signed-off-by: Jukka Rissanen --- tests/net/socket/tls_ext/prj.conf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/net/socket/tls_ext/prj.conf b/tests/net/socket/tls_ext/prj.conf index b2e360bb4db..c8a18c17f76 100644 --- a/tests/net/socket/tls_ext/prj.conf +++ b/tests/net/socket/tls_ext/prj.conf @@ -1,6 +1,7 @@ # General config CONFIG_SMP=n CONFIG_ZTEST=y +CONFIG_POSIX_API=y # Networking config CONFIG_TEST_RANDOM_GENERATOR=y @@ -11,7 +12,6 @@ CONFIG_NET_LOOPBACK=y CONFIG_NET_IPV4=y CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y # Logging / Debugging options CONFIG_NET_LOG=y @@ -29,7 +29,7 @@ CONFIG_NET_BUF_TX_COUNT=64 CONFIG_NET_PKT_TX_COUNT=64 CONFIG_NET_BUF_RX_COUNT=64 CONFIG_NET_PKT_RX_COUNT=64 -CONFIG_POSIX_MAX_FDS=8 +CONFIG_POSIX_MAX_FDS=10 # Stack sizes CONFIG_MAIN_STACK_SIZE=2048 From 0512e7ffaead7eeb2d3599cc71e439180e221e4a Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 07:25:16 +0200 Subject: [PATCH 1530/2402] tests: net: sockets: Remove use of NET_SOCKETS_POSIX_NAMES The setting is deprecated so change the code to either use the native zsock_* API or enable POSIX_API to use the BSD socket API. Signed-off-by: Jukka Rissanen --- tests/bsim/net/sockets/echo_test/prj.conf | 3 +- tests/net/all/prj.conf | 2 +- tests/net/ieee802154/l2/src/ieee802154_test.c | 48 +- tests/net/pm/prj.conf | 1 - tests/net/pm/src/main.c | 18 +- tests/net/socket/af_packet/prj.conf | 1 - tests/net/socket/af_packet/src/main.c | 102 ++-- .../net/socket/af_packet_ipproto_raw/prj.conf | 1 - .../socket/af_packet_ipproto_raw/src/main.c | 12 +- tests/net/socket/getaddrinfo/prj.conf | 1 - tests/net/socket/getaddrinfo/src/main.c | 38 +- tests/net/socket/getnameinfo/prj.conf | 1 - tests/net/socket/getnameinfo/src/main.c | 16 +- tests/net/socket/misc/prj.conf | 1 - tests/net/socket/misc/src/main.c | 288 +++++----- tests/net/socket/net_mgmt/prj.conf | 1 - tests/net/socket/net_mgmt/src/main.c | 40 +- tests/net/socket/poll/prj.conf | 1 - tests/net/socket/poll/src/main.c | 108 ++-- tests/net/socket/register/prj.conf | 1 - tests/net/socket/register/src/main.c | 8 +- tests/net/socket/reuseaddr_reuseport/prj.conf | 1 - .../net/socket/reuseaddr_reuseport/src/main.c | 82 +-- tests/net/socket/select/prj.conf | 1 - tests/net/socket/select/src/main.c | 78 +-- tests/net/socket/socket_helpers.h | 12 +- tests/net/socket/socketpair/prj.conf | 1 - tests/net/socket/socketpair/src/_main.c | 4 +- tests/net/socket/socketpair/src/_main.h | 2 +- tests/net/socket/socketpair/src/block.c | 10 +- tests/net/socket/socketpair/src/closed_ends.c | 20 +- .../socket/socketpair/src/expected_failures.c | 16 +- tests/net/socket/socketpair/src/fcntl.c | 6 +- tests/net/socket/socketpair/src/fionread.c | 6 +- tests/net/socket/socketpair/src/happy_path.c | 14 +- tests/net/socket/socketpair/src/nonblock.c | 14 +- tests/net/socket/socketpair/src/poll.c | 138 ++--- .../socket/socketpair/src/unsupported_calls.c | 8 +- tests/net/socket/tcp/prj.conf | 1 - tests/net/socket/tcp/src/main.c | 353 ++++++------ tests/net/socket/tls/prj.conf | 1 - tests/net/socket/tls/src/main.c | 298 +++++----- tests/net/socket/udp/prj.conf | 1 - tests/net/socket/udp/src/main.c | 530 +++++++++--------- tests/net/socket/websocket/prj.conf | 1 - 45 files changed, 1135 insertions(+), 1155 deletions(-) diff --git a/tests/bsim/net/sockets/echo_test/prj.conf b/tests/bsim/net/sockets/echo_test/prj.conf index e0bb985c985..259caa0deb5 100644 --- a/tests/bsim/net/sockets/echo_test/prj.conf +++ b/tests/bsim/net/sockets/echo_test/prj.conf @@ -7,10 +7,11 @@ CONFIG_NET_TCP=y CONFIG_NET_IPV6=y CONFIG_NET_IPV4=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_POLL_MAX=4 CONFIG_NET_CONNECTION_MANAGER=y +CONFIG_POSIX_API=y + # Kernel options CONFIG_MAIN_STACK_SIZE=2048 CONFIG_ENTROPY_GENERATOR=y diff --git a/tests/net/all/prj.conf b/tests/net/all/prj.conf index ac890cd2a07..8a82138c529 100644 --- a/tests/net/all/prj.conf +++ b/tests/net/all/prj.conf @@ -9,6 +9,7 @@ CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_ZTEST=y CONFIG_LOG_DEFAULT_LEVEL=4 CONFIG_MAX_THREAD_BYTES=4 +CONFIG_POSIX_API=y # TLS configuration CONFIG_MBEDTLS=y @@ -362,7 +363,6 @@ CONFIG_NET_SOCKETS_LOG_LEVEL_DBG=y CONFIG_NET_SOCKETS_OFFLOAD=y CONFIG_NET_SOCKETS_PACKET=y CONFIG_NET_SOCKETS_POLL_MAX=50 -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS=y CONFIG_NET_SOCKETS_SOCKOPT_TLS=y CONFIG_NET_SOCKETS_TLS_MAX_CIPHERSUITES=10 diff --git a/tests/net/ieee802154/l2/src/ieee802154_test.c b/tests/net/ieee802154/l2/src/ieee802154_test.c index 4d93e2398b0..c3163957673 100644 --- a/tests/net/ieee802154/l2/src/ieee802154_test.c +++ b/tests/net/ieee802154/l2/src/ieee802154_test.c @@ -405,18 +405,18 @@ static int set_up_recv_socket(enum net_sock_type socket_type) }; int fd; - fd = socket(AF_PACKET, socket_type, ETH_P_IEEE802154); + fd = zsock_socket(AF_PACKET, socket_type, ETH_P_IEEE802154); if (fd < 0) { NET_ERR("*** Failed to create recv socket : %d", errno); return fd; } - if (bind(fd, (const struct sockaddr *)&socket_sll, sizeof(struct sockaddr_ll))) { + if (zsock_bind(fd, (const struct sockaddr *)&socket_sll, sizeof(struct sockaddr_ll))) { NET_ERR("*** Failed to bind packet socket : %d", errno); goto release_fd; } - if (setsockopt(fd, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, sizeof(timeo_optval))) { + if (zsock_setsockopt(fd, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, sizeof(timeo_optval))) { NET_ERR("*** Failed to set reception timeout on packet socket : %d", errno); goto release_fd; } @@ -424,7 +424,7 @@ static int set_up_recv_socket(enum net_sock_type socket_type) return fd; release_fd: - close(fd); + zsock_close(fd); return -EFAULT; } #endif /* CONFIG_NET_SOCKETS */ @@ -697,7 +697,7 @@ static bool test_dgram_packet_sending(void *dst_sll, uint8_t dst_sll_halen, uint } NET_INFO("- Sending DGRAM packet via AF_PACKET socket"); - fd = socket(AF_PACKET, SOCK_DGRAM, ETH_P_IEEE802154); + fd = zsock_socket(AF_PACKET, SOCK_DGRAM, ETH_P_IEEE802154); if (fd < 0) { NET_ERR("*** Failed to create DGRAM socket : %d", errno); goto reset_security; @@ -715,13 +715,13 @@ static bool test_dgram_packet_sending(void *dst_sll, uint8_t dst_sll_halen, uint goto release_fd; } - if (bind(fd, (const struct sockaddr *)&socket_sll, sizeof(struct sockaddr_ll))) { + if (zsock_bind(fd, (const struct sockaddr *)&socket_sll, sizeof(struct sockaddr_ll))) { NET_ERR("*** Failed to bind packet socket : %d", errno); goto release_fd; } - if (sendto(fd, payload, sizeof(payload), 0, (const struct sockaddr *)&pkt_dst_sll, - sizeof(struct sockaddr_ll)) != sizeof(payload)) { + if (zsock_sendto(fd, payload, sizeof(payload), 0, (const struct sockaddr *)&pkt_dst_sll, + sizeof(struct sockaddr_ll)) != sizeof(payload)) { NET_ERR("*** Failed to send, errno %d", errno); goto release_fd; } @@ -762,7 +762,7 @@ static bool test_dgram_packet_sending(void *dst_sll, uint8_t dst_sll_halen, uint current_pkt->frags = NULL; release_fd: tear_down_short_addr(net_iface, ctx); - close(fd); + zsock_close(fd); reset_security: tear_down_security(); out: @@ -877,8 +877,8 @@ static bool test_dgram_packet_reception(void *src_ll_addr, uint8_t src_ll_addr_l } recv_src_sll_len = sizeof(recv_src_sll); - received_len = recvfrom(fd, received_payload, sizeof(received_payload), 0, - (struct sockaddr *)&recv_src_sll, &recv_src_sll_len); + received_len = zsock_recvfrom(fd, received_payload, sizeof(received_payload), 0, + (struct sockaddr *)&recv_src_sll, &recv_src_sll_len); if (received_len < 0) { NET_ERR("*** Failed to receive packet, errno %d", errno); goto release_pkt; @@ -905,7 +905,7 @@ static bool test_dgram_packet_reception(void *src_ll_addr, uint8_t src_ll_addr_l release_pkt: net_pkt_unref(pkt); release_fd: - close(fd); + zsock_close(fd); reset_security: tear_down_security(); out: @@ -924,7 +924,7 @@ static bool test_raw_packet_sending(void) NET_INFO("- Sending RAW packet via AF_PACKET socket"); - fd = socket(AF_PACKET, SOCK_RAW, ETH_P_IEEE802154); + fd = zsock_socket(AF_PACKET, SOCK_RAW, ETH_P_IEEE802154); if (fd < 0) { NET_ERR("*** Failed to create RAW socket : %d", errno); goto out; @@ -934,7 +934,7 @@ static bool test_raw_packet_sending(void) socket_sll.sll_family = AF_PACKET; socket_sll.sll_protocol = ETH_P_IEEE802154; - if (bind(fd, (const struct sockaddr *)&socket_sll, sizeof(struct sockaddr_ll))) { + if (zsock_bind(fd, (const struct sockaddr *)&socket_sll, sizeof(struct sockaddr_ll))) { NET_ERR("*** Failed to bind packet socket : %d", errno); goto release_fd; } @@ -944,7 +944,7 @@ static bool test_raw_packet_sending(void) msg.msg_iov = &io_vector; msg.msg_iovlen = 1; - if (sendmsg(fd, &msg, 0) != sizeof(raw_payload)) { + if (zsock_sendmsg(fd, &msg, 0) != sizeof(raw_payload)) { NET_ERR("*** Failed to send, errno %d", errno); goto release_fd; } @@ -977,7 +977,7 @@ static bool test_raw_packet_sending(void) net_pkt_frag_unref(current_pkt->frags); current_pkt->frags = NULL; release_fd: - close(fd); + zsock_close(fd); out: return result; } @@ -1031,7 +1031,7 @@ static bool test_raw_packet_reception(void) * extracted. We'll only be able to do so when Zephyr provides hooks to * call out to L2 from raw socket contexts. */ - received_len = recv(fd, received_payload, sizeof(received_payload), 0); + received_len = zsock_recv(fd, received_payload, sizeof(received_payload), 0); if (received_len < 0) { NET_ERR("*** Failed to receive packet, errno %d", errno); goto release_pkt; @@ -1058,7 +1058,7 @@ static bool test_raw_packet_reception(void) release_pkt: net_pkt_unref(pkt); release_fd: - close(fd); + zsock_close(fd); out: return result; } @@ -1108,18 +1108,18 @@ static bool test_recv_and_send_ack_reply(struct ieee802154_pkt_test *t) NET_INFO("- Sending ACK reply to a data packet"); - fd = socket(AF_PACKET, SOCK_DGRAM, ETH_P_IEEE802154); + fd = zsock_socket(AF_PACKET, SOCK_DGRAM, ETH_P_IEEE802154); if (fd < 0) { NET_ERR("*** Failed to create DGRAM socket : %d", errno); goto out; } - if (bind(fd, (const struct sockaddr *)&socket_sll, sizeof(struct sockaddr_ll))) { + if (zsock_bind(fd, (const struct sockaddr *)&socket_sll, sizeof(struct sockaddr_ll))) { NET_ERR("*** Failed to bind packet socket : %d", errno); goto release_fd; } - if (setsockopt(fd, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, sizeof(timeo_optval))) { + if (zsock_setsockopt(fd, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, sizeof(timeo_optval))) { NET_ERR("*** Failed to set reception timeout on packet socket : %d", errno); goto release_fd; } @@ -1139,8 +1139,8 @@ static bool test_recv_and_send_ack_reply(struct ieee802154_pkt_test *t) } recv_src_sll_len = sizeof(recv_src_sll); - received_len = recvfrom(fd, received_payload, sizeof(received_payload), 0, - (struct sockaddr *)&recv_src_sll, &recv_src_sll_len); + received_len = zsock_recvfrom(fd, received_payload, sizeof(received_payload), 0, + (struct sockaddr *)&recv_src_sll, &recv_src_sll_len); if (received_len < 0) { NET_ERR("*** Failed to receive packet, errno %d", errno); goto release_rx_pkt; @@ -1202,7 +1202,7 @@ static bool test_recv_and_send_ack_reply(struct ieee802154_pkt_test *t) reset_short_addr: tear_down_short_addr(net_iface, ctx); release_fd: - close(fd); + zsock_close(fd); out: return result; } diff --git a/tests/net/pm/prj.conf b/tests/net/pm/prj.conf index 5650693d56c..60080821868 100644 --- a/tests/net/pm/prj.conf +++ b/tests/net/pm/prj.conf @@ -7,7 +7,6 @@ CONFIG_NET_L2_ETHERNET=n CONFIG_NET_UDP=y CONFIG_NET_IPV4=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_POSIX_MAX_FDS=2 CONFIG_ZTEST_STACK_SIZE=2048 CONFIG_MAIN_STACK_SIZE=2048 diff --git a/tests/net/pm/src/main.c b/tests/net/pm/src/main.c index 4aa7bffff7d..02faa1c502c 100644 --- a/tests/net/pm/src/main.c +++ b/tests/net/pm/src/main.c @@ -128,16 +128,16 @@ ZTEST(test_net_pm_test_suite, test_pm) addr4.sin_family = AF_INET; addr4.sin_port = htons(12345); - inet_pton(AF_INET, "192.168.0.1", &addr4.sin_addr); + zsock_inet_pton(AF_INET, "192.168.0.1", &addr4.sin_addr); - sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + sock = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); zassert_true(sock >= 0, "Could not open socket"); zassert_false(net_if_is_suspended(iface), "net iface is not suspended"); /* Let's send some data, it should go through */ - ret = sendto(sock, data, ARRAY_SIZE(data), 0, - (struct sockaddr *)&addr4, sizeof(struct sockaddr_in)); + ret = zsock_sendto(sock, data, ARRAY_SIZE(data), 0, + (struct sockaddr *)&addr4, sizeof(struct sockaddr_in)); zassert_true(ret > 0, "Could not send data"); /* Let's make sure net stack's thread gets ran, or setting PM state @@ -157,8 +157,8 @@ ZTEST(test_net_pm_test_suite, test_pm) zassert_true(net_if_is_suspended(iface), "net iface is not suspended"); /* Let's send some data, it should fail relevantly */ - ret = sendto(sock, data, ARRAY_SIZE(data), 0, - (struct sockaddr *)&addr4, sizeof(struct sockaddr_in)); + ret = zsock_sendto(sock, data, ARRAY_SIZE(data), 0, + (struct sockaddr *)&addr4, sizeof(struct sockaddr_in)); zassert_true(ret < 0, "Could send data"); ret = pm_device_action_run(dev, PM_DEVICE_ACTION_RESUME); @@ -170,11 +170,11 @@ ZTEST(test_net_pm_test_suite, test_pm) zassert_true(ret == -EALREADY, "Could change state"); /* Let's send some data, it should go through */ - ret = sendto(sock, data, ARRAY_SIZE(data), 0, - (struct sockaddr *)&addr4, sizeof(struct sockaddr_in)); + ret = zsock_sendto(sock, data, ARRAY_SIZE(data), 0, + (struct sockaddr *)&addr4, sizeof(struct sockaddr_in)); zassert_true(ret > 0, "Could not send data"); - close(sock); + zsock_close(sock); } ZTEST_SUITE(test_net_pm_test_suite, NULL, test_setup, NULL, NULL, NULL); diff --git a/tests/net/socket/af_packet/prj.conf b/tests/net/socket/af_packet/prj.conf index c73bd698d18..a0fd507497d 100644 --- a/tests/net/socket/af_packet/prj.conf +++ b/tests/net/socket/af_packet/prj.conf @@ -5,7 +5,6 @@ CONFIG_NET_IPV6=n CONFIG_NET_UDP=y CONFIG_NET_TCP=n CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_PACKET=y CONFIG_POSIX_MAX_FDS=8 CONFIG_NET_IPV6_DAD=n diff --git a/tests/net/socket/af_packet/src/main.c b/tests/net/socket/af_packet/src/main.c index 3390fb27706..e82af239e26 100644 --- a/tests/net/socket/af_packet/src/main.c +++ b/tests/net/socket/af_packet/src/main.c @@ -11,7 +11,7 @@ LOG_MODULE_REGISTER(net_test, CONFIG_NET_SOCKETS_LOG_LEVEL); #include #include -#include +#include #include #include @@ -107,7 +107,7 @@ static int setup_socket(struct net_if *iface, int type, int proto) { int sock; - sock = socket(AF_PACKET, type, proto); + sock = zsock_socket(AF_PACKET, type, proto); zassert_true(sock >= 0, "Cannot create packet socket (%d)", -errno); return sock; @@ -122,7 +122,7 @@ static int bind_socket(int sock, struct net_if *iface) addr.sll_ifindex = net_if_get_by_iface(iface); addr.sll_family = AF_PACKET; - return bind(sock, (struct sockaddr *)&addr, sizeof(addr)); + return zsock_bind(sock, (struct sockaddr *)&addr, sizeof(addr)); } struct user_data { @@ -157,7 +157,7 @@ static void setblocking(int fd, bool val) { int fl, res; - fl = fcntl(fd, F_GETFL, 0); + fl = zsock_fcntl(fd, F_GETFL, 0); zassert_not_equal(fl, -1, "Fail to set fcntl"); if (val) { @@ -166,7 +166,7 @@ static void setblocking(int fd, bool val) fl |= O_NONBLOCK; } - res = fcntl(fd, F_SETFL, fl); + res = zsock_fcntl(fd, F_SETFL, fl); zassert_not_equal(res, -1, "Fail to set fcntl"); } @@ -176,16 +176,16 @@ static int prepare_udp_socket(struct sockaddr_in *sockaddr, uint16_t local_port) { int sock, ret; - sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + sock = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); zassert_true(sock >= 0, "Cannot create DGRAM (UDP) socket (%d)", sock); sockaddr->sin_family = AF_INET; sockaddr->sin_port = htons(local_port); - ret = inet_pton(AF_INET, IPV4_ADDR, &sockaddr->sin_addr); + ret = zsock_inet_pton(AF_INET, IPV4_ADDR, &sockaddr->sin_addr); zassert_equal(ret, 1, "inet_pton failed"); /* Bind UDP socket to local port */ - ret = bind(sock, (struct sockaddr *) sockaddr, sizeof(*sockaddr)); + ret = zsock_bind(sock, (struct sockaddr *) sockaddr, sizeof(*sockaddr)); zassert_equal(ret, 0, "Cannot bind DGRAM (UDP) socket (%d)", -errno); return sock; @@ -241,8 +241,8 @@ ZTEST(socket_packet, test_raw_packet_sockets) * Send UDP datagram to us - as check_ip_addr() in net_send_data() * returns 1 - the packet is processed immediately in the net stack */ - sent = sendto(sock4, data_to_send, sizeof(data_to_send), - 0, (struct sockaddr *)&sockaddr, sizeof(sockaddr)); + sent = zsock_sendto(sock4, data_to_send, sizeof(data_to_send), + 0, (struct sockaddr *)&sockaddr, sizeof(sockaddr)); zassert_equal(sent, sizeof(data_to_send), "sendto failed"); k_msleep(10); /* Let the packet enter the system */ @@ -253,8 +253,8 @@ ZTEST(socket_packet, test_raw_packet_sockets) /* Check if UDP packets can be read after being sent */ addrlen = sizeof(sockaddr); - ret = recvfrom(sock3, data_to_receive, sizeof(data_to_receive), - 0, (struct sockaddr *)&sockaddr, &addrlen); + ret = zsock_recvfrom(sock3, data_to_receive, sizeof(data_to_receive), + 0, (struct sockaddr *)&sockaddr, &addrlen); zassert_equal(ret, sizeof(data_to_send), "Cannot receive all data (%d)", -errno); zassert_mem_equal(data_to_receive, data_to_send, sizeof(data_to_send), @@ -271,8 +271,8 @@ ZTEST(socket_packet, test_raw_packet_sockets) * IP (20B) and UDP (8) headers. After those we can expect payload, * which have been sent. */ - ret = recvfrom(sock1, data_to_receive, sizeof(data_to_receive), 0, - (struct sockaddr *)&src, &addrlen); + ret = zsock_recvfrom(sock1, data_to_receive, sizeof(data_to_receive), 0, + (struct sockaddr *)&src, &addrlen); zassert_equal(ret, sizeof(data_to_send) + HDR_SIZE, "Cannot receive all data (%d vs %zd) (%d)", ret, sizeof(data_to_send), -errno); @@ -280,10 +280,10 @@ ZTEST(socket_packet, test_raw_packet_sockets) sizeof(data_to_send), "Sent and received buffers do not match"); - close(sock1); - close(sock2); - close(sock3); - close(sock4); + zsock_close(sock1); + zsock_close(sock2); + zsock_close(sock3); + zsock_close(sock4); } ZTEST(socket_packet, test_packet_sockets) @@ -292,8 +292,8 @@ ZTEST(socket_packet, test_packet_sockets) __test_packet_sockets(&sock1, &sock2); - close(sock1); - close(sock2); + zsock_close(sock1); + zsock_close(sock2); } ZTEST(socket_packet, test_packet_sockets_dgram) @@ -331,8 +331,8 @@ ZTEST(socket_packet, test_packet_sockets_dgram) dst.sll_protocol = htons(ETH_P_IP); memcpy(dst.sll_addr, lladdr1, sizeof(lladdr1)); - ret = sendto(sock2, data_to_send, sizeof(data_to_send), 0, - (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); + ret = zsock_sendto(sock2, data_to_send, sizeof(data_to_send), 0, + (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); zassert_equal(ret, sizeof(data_to_send), "Cannot send all data (%d)", -errno); @@ -342,8 +342,8 @@ ZTEST(socket_packet, test_packet_sockets_dgram) errno = 0; iter = 0; do { - ret = recvfrom(sock1, data_to_receive, sizeof(data_to_receive), - 0, (struct sockaddr *)&src, &addrlen); + ret = zsock_recvfrom(sock1, data_to_receive, sizeof(data_to_receive), + 0, (struct sockaddr *)&src, &addrlen); k_msleep(10); iter++; } while (ret < 0 && errno == EAGAIN && iter < max_iter); @@ -360,16 +360,16 @@ ZTEST(socket_packet, test_packet_sockets_dgram) /* Send to socket 2 but read from socket 1. There should not be any * data in socket 1 */ - ret = sendto(sock2, data_to_send, sizeof(data_to_send), 0, - (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); + ret = zsock_sendto(sock2, data_to_send, sizeof(data_to_send), 0, + (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); zassert_equal(ret, sizeof(data_to_send), "Cannot send all data (%d)", -errno); k_msleep(10); memset(&src, 0, sizeof(src)); - ret = recvfrom(sock1, data_to_receive, sizeof(data_to_receive), 0, - (struct sockaddr *)&src, &addrlen); + ret = zsock_recvfrom(sock1, data_to_receive, sizeof(data_to_receive), 0, + (struct sockaddr *)&src, &addrlen); zassert_equal(ret, -1, "Received something (%d)", ret); zassert_equal(errno, EAGAIN, "Wrong errno (%d)", errno); @@ -378,8 +378,8 @@ ZTEST(socket_packet, test_packet_sockets_dgram) errno = 0; iter = 0; do { - ret = recvfrom(sock2, data_to_receive, sizeof(data_to_receive), - 0, (struct sockaddr *)&src, &addrlen); + ret = zsock_recvfrom(sock2, data_to_receive, sizeof(data_to_receive), + 0, (struct sockaddr *)&src, &addrlen); k_msleep(10); iter++; } while (ret < 0 && errno == EAGAIN && iter < max_iter); @@ -389,8 +389,8 @@ ZTEST(socket_packet, test_packet_sockets_dgram) zassert_mem_equal(data_to_send, data_to_receive, sizeof(data_to_send), "Data mismatch"); - close(sock1); - close(sock2); + zsock_close(sock1); + zsock_close(sock2); } ZTEST(socket_packet, test_raw_and_dgram_socket_exchange) @@ -443,8 +443,8 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_exchange) /* SOCK_DGRAM to SOCK_RAW */ - ret = sendto(sock1, data_to_send, sizeof(data_to_send), 0, - (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); + ret = zsock_sendto(sock1, data_to_send, sizeof(data_to_send), 0, + (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); zassert_equal(ret, sizeof(data_to_send), "Cannot send all data (%d)", -errno); @@ -454,8 +454,8 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_exchange) errno = 0; iter = 0; do { - ret = recvfrom(sock2, data_to_receive, sizeof(data_to_receive), - 0, (struct sockaddr *)&src, &addrlen); + ret = zsock_recvfrom(sock2, data_to_receive, sizeof(data_to_receive), + 0, (struct sockaddr *)&src, &addrlen); k_msleep(10); iter++; } while (ret < 0 && errno == EAGAIN && iter < max_iter); @@ -473,8 +473,8 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_exchange) /* SOCK_RAW to SOCK_DGRAM */ - ret = sendto(sock2, send_payload_raw, sizeof(send_payload_raw), 0, - (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); + ret = zsock_sendto(sock2, send_payload_raw, sizeof(send_payload_raw), 0, + (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); zassert_equal(ret, sizeof(send_payload_raw), "Cannot send all data (%d)", -errno); @@ -484,8 +484,8 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_exchange) errno = 0; iter = 0; do { - ret = recvfrom(sock1, data_to_receive, sizeof(data_to_receive), - 0, (struct sockaddr *)&src, &addrlen); + ret = zsock_recvfrom(sock1, data_to_receive, sizeof(data_to_receive), + 0, (struct sockaddr *)&src, &addrlen); k_msleep(10); iter++; } while (ret < 0 && errno == EAGAIN && iter < max_iter); @@ -495,8 +495,8 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_exchange) zassert_mem_equal(data_to_send, data_to_receive, sizeof(data_to_send), "Data mismatch"); - close(sock1); - close(sock2); + zsock_close(sock1); + zsock_close(sock2); } ZTEST(socket_packet, test_raw_and_dgram_socket_recv) @@ -547,8 +547,8 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_recv) dst.sll_protocol = htons(ETH_P_IP); memcpy(dst.sll_addr, lladdr2, sizeof(lladdr1)); - ret = sendto(sock1, data_to_send, sizeof(data_to_send), 0, - (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); + ret = zsock_sendto(sock1, data_to_send, sizeof(data_to_send), 0, + (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); zassert_equal(ret, sizeof(data_to_send), "Cannot send all data (%d)", -errno); @@ -560,8 +560,8 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_recv) errno = 0; iter = 0; do { - ret = recvfrom(sock2, data_to_receive, sizeof(data_to_receive), - 0, (struct sockaddr *)&src, &addrlen); + ret = zsock_recvfrom(sock2, data_to_receive, sizeof(data_to_receive), + 0, (struct sockaddr *)&src, &addrlen); k_msleep(10); iter++; } while (ret < 0 && errno == EAGAIN && iter < max_iter); @@ -578,8 +578,8 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_recv) errno = 0; iter = 0; do { - ret = recvfrom(sock3, data_to_receive, sizeof(data_to_receive), - 0, (struct sockaddr *)&src, &addrlen); + ret = zsock_recvfrom(sock3, data_to_receive, sizeof(data_to_receive), + 0, (struct sockaddr *)&src, &addrlen); k_msleep(10); iter++; } while (ret < 0 && errno == EAGAIN && iter < max_iter); @@ -589,9 +589,9 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_recv) zassert_mem_equal(expected_payload_raw, data_to_receive, sizeof(expected_payload_raw), "Data mismatch"); - close(sock1); - close(sock2); - close(sock3); + zsock_close(sock1); + zsock_close(sock2); + zsock_close(sock3); } ZTEST_SUITE(socket_packet, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/net/socket/af_packet_ipproto_raw/prj.conf b/tests/net/socket/af_packet_ipproto_raw/prj.conf index 57c66491ea1..9edcaa6be84 100644 --- a/tests/net/socket/af_packet_ipproto_raw/prj.conf +++ b/tests/net/socket/af_packet_ipproto_raw/prj.conf @@ -5,7 +5,6 @@ CONFIG_NET_IPV6=n CONFIG_NET_UDP=n CONFIG_NET_TCP=n CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_PACKET=y CONFIG_POSIX_MAX_FDS=8 CONFIG_NET_SOCKETS_LOG_LEVEL_DBG=y diff --git a/tests/net/socket/af_packet_ipproto_raw/src/main.c b/tests/net/socket/af_packet_ipproto_raw/src/main.c index 95852262df7..907b28df7e5 100644 --- a/tests/net/socket/af_packet_ipproto_raw/src/main.c +++ b/tests/net/socket/af_packet_ipproto_raw/src/main.c @@ -120,27 +120,27 @@ ZTEST(net_sckt_packet_raw_ip, test_sckt_raw_packet_raw_ip) char receive_buffer[128]; int sock; - sock = socket(AF_PACKET, SOCK_RAW, IPPROTO_RAW); + sock = zsock_socket(AF_PACKET, SOCK_RAW, IPPROTO_RAW); zassert_true(sock >= 0, "Could not create a socket"); dst.sll_ifindex = net_if_get_by_iface(iface); dst.sll_family = AF_PACKET; - ret = bind(sock, (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); + ret = zsock_bind(sock, (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); zassert_true(ret >= 0, "Could not bind the socket"); /* Let's send some data: */ - ret = sendto(sock, testing_data, ARRAY_SIZE(testing_data), 0, (const struct sockaddr *)&dst, - sizeof(struct sockaddr_ll)); + ret = zsock_sendto(sock, testing_data, ARRAY_SIZE(testing_data), 0, + (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll)); zassert_true(ret > 0, "Could not send data"); /* Receive the same data back: */ - recv_data_len = recv(sock, receive_buffer, sizeof(receive_buffer), 0); + recv_data_len = zsock_recv(sock, receive_buffer, sizeof(receive_buffer), 0); zassert_true(recv_data_len == ARRAY_SIZE(testing_data), "Expected data not received"); NET_DBG("Received successfully data %s", receive_buffer); - close(sock); + zsock_close(sock); } ZTEST_SUITE(net_sckt_packet_raw_ip, NULL, test_setup, NULL, NULL, NULL); diff --git a/tests/net/socket/getaddrinfo/prj.conf b/tests/net/socket/getaddrinfo/prj.conf index e0430061b1e..7b98922798d 100644 --- a/tests/net/socket/getaddrinfo/prj.conf +++ b/tests/net/socket/getaddrinfo/prj.conf @@ -9,7 +9,6 @@ CONFIG_NET_LOOPBACK=y CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_L2_ETHERNET=n # Network driver config diff --git a/tests/net/socket/getaddrinfo/src/main.c b/tests/net/socket/getaddrinfo/src/main.c index 39999a84caf..37d960cb4b7 100644 --- a/tests/net/socket/getaddrinfo/src/main.c +++ b/tests/net/socket/getaddrinfo/src/main.c @@ -110,7 +110,7 @@ static bool check_dns_query(uint8_t *buf, int buf_len) static int process_dns(void) { - struct pollfd pollfds[2]; + struct zsock_pollfd pollfds[2]; struct sockaddr *addr; socklen_t addr_len; int ret, idx; @@ -123,19 +123,19 @@ static int process_dns(void) while (true) { memset(pollfds, 0, sizeof(pollfds)); pollfds[0].fd = sock_v4; - pollfds[0].events = POLLIN; + pollfds[0].events = ZSOCK_POLLIN; pollfds[1].fd = sock_v6; - pollfds[1].events = POLLIN; + pollfds[1].events = ZSOCK_POLLIN; NET_DBG("Polling..."); - ret = poll(pollfds, ARRAY_SIZE(pollfds), -1); + ret = zsock_poll(pollfds, ARRAY_SIZE(pollfds), -1); if (ret <= 0) { continue; } for (idx = 0; idx < ARRAY_SIZE(pollfds); idx++) { - if (pollfds[idx].revents & POLLIN) { + if (pollfds[idx].revents & ZSOCK_POLLIN) { if (pollfds[idx].fd == sock_v4) { addr_len = sizeof(addr_v4); addr = (struct sockaddr *)&addr_v4; @@ -144,9 +144,9 @@ static int process_dns(void) addr = (struct sockaddr *)&addr_v6; } - ret = recvfrom(pollfds[idx].fd, - recv_buf, sizeof(recv_buf), 0, - addr, &addr_len); + ret = zsock_recvfrom(pollfds[idx].fd, + recv_buf, sizeof(recv_buf), 0, + addr, &addr_len); if (ret < 0) { /* Socket error */ NET_ERR("DNS: Connection error (%d)", @@ -200,13 +200,13 @@ static void *test_getaddrinfo_setup(void) memcpy(&addr_v6, net_sin6(&addr), sizeof(struct sockaddr_in6)); } - addr_str = inet_ntop(AF_INET, &addr_v4.sin_addr, str, sizeof(str)); + addr_str = zsock_inet_ntop(AF_INET, &addr_v4.sin_addr, str, sizeof(str)); NET_DBG("v4: [%s]:%d", addr_str, ntohs(addr_v4.sin_port)); sock_v4 = prepare_listen_sock_udp_v4(&addr_v4); zassert_true(sock_v4 >= 0, "Invalid IPv4 socket"); - addr_str = inet_ntop(AF_INET6, &addr_v6.sin6_addr, str, sizeof(str)); + addr_str = zsock_inet_ntop(AF_INET6, &addr_v6.sin6_addr, str, sizeof(str)); NET_DBG("v6: [%s]:%d", addr_str, ntohs(addr_v6.sin6_port)); sock_v6 = prepare_listen_sock_udp_v6(&addr_v6); @@ -225,7 +225,7 @@ static void *test_getaddrinfo_setup(void) ZTEST(net_socket_getaddrinfo, test_getaddrinfo_ok) { - struct addrinfo *res = NULL; + struct zsock_addrinfo *res = NULL; queries_received = 0; @@ -235,7 +235,7 @@ ZTEST(net_socket_getaddrinfo, test_getaddrinfo_ok) * that the query triggered a function call to process_dns() function * and that it could parse the DNS query. */ - (void)getaddrinfo(QUERY_HOST, NULL, NULL, &res); + (void)zsock_getaddrinfo(QUERY_HOST, NULL, NULL, &res); (void)sys_sem_take(&wait_data, K_NO_WAIT); (void)sys_sem_take(&wait_data, K_NO_WAIT); @@ -244,15 +244,15 @@ ZTEST(net_socket_getaddrinfo, test_getaddrinfo_ok) "Did not receive both IPv4 and IPv6 query (got %d, expected %d)", queries_received, expected_query_count); - freeaddrinfo(res); + zsock_freeaddrinfo(res); } ZTEST(net_socket_getaddrinfo, test_getaddrinfo_cancelled) { - struct addrinfo *res = NULL; + struct zsock_addrinfo *res = NULL; int ret; - ret = getaddrinfo(QUERY_HOST, NULL, NULL, &res); + ret = zsock_getaddrinfo(QUERY_HOST, NULL, NULL, &res); (void)sys_sem_take(&wait_data, K_NO_WAIT); (void)sys_sem_take(&wait_data, K_NO_WAIT); @@ -264,21 +264,21 @@ ZTEST(net_socket_getaddrinfo, test_getaddrinfo_cancelled) /* Without a local DNS server this request will be canceled. */ zassert_equal(ret, DNS_EAI_CANCELED, "Invalid result"); - freeaddrinfo(res); + zsock_freeaddrinfo(res); } ZTEST(net_socket_getaddrinfo, test_getaddrinfo_no_host) { - struct addrinfo *res = NULL; + struct zsock_addrinfo *res = NULL; int ret; - ret = getaddrinfo(NULL, NULL, NULL, &res); + ret = zsock_getaddrinfo(NULL, NULL, NULL, &res); zassert_equal(ret, DNS_EAI_SYSTEM, "Invalid result"); zassert_equal(errno, EINVAL, "Invalid errno"); zassert_is_null(res, "ai_addr is not NULL"); - freeaddrinfo(res); + zsock_freeaddrinfo(res); } ZTEST(net_socket_getaddrinfo, test_getaddrinfo_num_ipv4) diff --git a/tests/net/socket/getnameinfo/prj.conf b/tests/net/socket/getnameinfo/prj.conf index adc83076810..e42ae62561b 100644 --- a/tests/net/socket/getnameinfo/prj.conf +++ b/tests/net/socket/getnameinfo/prj.conf @@ -9,7 +9,6 @@ CONFIG_NET_LOOPBACK=y CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y # Network driver config CONFIG_TEST_RANDOM_GENERATOR=y diff --git a/tests/net/socket/getnameinfo/src/main.c b/tests/net/socket/getnameinfo/src/main.c index ad9aaa59d3c..4c5e4c54789 100644 --- a/tests/net/socket/getnameinfo/src/main.c +++ b/tests/net/socket/getnameinfo/src/main.c @@ -22,8 +22,8 @@ ZTEST_USER(net_socket_getnameinfo, test_getnameinfo_ipv4) memset(&saddr, 0, sizeof(saddr)); saddr.sin_family = AF_INET; - ret = getnameinfo((struct sockaddr *)&saddr, sizeof(saddr), - host, sizeof(host), serv, sizeof(serv), 0); + ret = zsock_getnameinfo((struct sockaddr *)&saddr, sizeof(saddr), + host, sizeof(host), serv, sizeof(serv), 0); zassert_equal(ret, 0, ""); printk("%s %s\n", host, serv); @@ -33,8 +33,8 @@ ZTEST_USER(net_socket_getnameinfo, test_getnameinfo_ipv4) saddr.sin_port = htons(1234); saddr.sin_addr.s_addr = htonl(0x7f000001); - ret = getnameinfo((struct sockaddr *)&saddr, sizeof(saddr), - host, sizeof(host), serv, sizeof(serv), 0); + ret = zsock_getnameinfo((struct sockaddr *)&saddr, sizeof(saddr), + host, sizeof(host), serv, sizeof(serv), 0); zassert_equal(ret, 0, ""); printk("%s %s\n", host, serv); @@ -52,8 +52,8 @@ ZTEST_USER(net_socket_getnameinfo, test_getnameinfo_ipv6) memset(&saddr, 0, sizeof(saddr)); saddr.sin6_family = AF_INET6; - ret = getnameinfo((struct sockaddr *)&saddr, sizeof(saddr), - host, sizeof(host), serv, sizeof(serv), 0); + ret = zsock_getnameinfo((struct sockaddr *)&saddr, sizeof(saddr), + host, sizeof(host), serv, sizeof(serv), 0); zassert_equal(ret, 0, ""); printk("%s %s\n", host, serv); @@ -65,8 +65,8 @@ ZTEST_USER(net_socket_getnameinfo, test_getnameinfo_ipv6) saddr.sin6_addr.s6_addr[1] = 0x55; saddr.sin6_addr.s6_addr[15] = 0x11; - ret = getnameinfo((struct sockaddr *)&saddr, sizeof(saddr), - host, sizeof(host), serv, sizeof(serv), 0); + ret = zsock_getnameinfo((struct sockaddr *)&saddr, sizeof(saddr), + host, sizeof(host), serv, sizeof(serv), 0); zassert_equal(ret, 0, ""); printk("%s %s\n", host, serv); diff --git a/tests/net/socket/misc/prj.conf b/tests/net/socket/misc/prj.conf index 8e7bd8459cd..4b5b18129c4 100644 --- a/tests/net/socket/misc/prj.conf +++ b/tests/net/socket/misc/prj.conf @@ -11,7 +11,6 @@ CONFIG_NET_IPV6=y CONFIG_NET_UDP=y CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_L2_DUMMY=y CONFIG_NET_IPV6_DAD=n CONFIG_NET_IPV6_MLD=n diff --git a/tests/net/socket/misc/src/main.c b/tests/net/socket/misc/src/main.c index 3ddf482f5d6..1ddc872ce3b 100644 --- a/tests/net/socket/misc/src/main.c +++ b/tests/net/socket/misc/src/main.c @@ -23,7 +23,7 @@ ZTEST_USER(socket_misc_test_suite, test_gethostname) static ZTEST_BMEM char buf[80]; int res; - res = gethostname(buf, sizeof(buf)); + res = zsock_gethostname(buf, sizeof(buf)); zassert_equal(res, 0, ""); printk("%s\n", buf); zassert_equal(strcmp(buf, "ztest_hostname"), 0, ""); @@ -34,22 +34,22 @@ ZTEST_USER(socket_misc_test_suite, test_inet_pton) int res; uint8_t buf[32]; - res = inet_pton(AF_INET, "127.0.0.1", buf); + res = zsock_inet_pton(AF_INET, "127.0.0.1", buf); zassert_equal(res, 1, ""); - res = inet_pton(AF_INET, "127.0.0.1a", buf); + res = zsock_inet_pton(AF_INET, "127.0.0.1a", buf); zassert_equal(res, 0, ""); - res = inet_pton(AF_INET6, "a:b:c:d:0:1:2:3", buf); + res = zsock_inet_pton(AF_INET6, "a:b:c:d:0:1:2:3", buf); zassert_equal(res, 1, ""); - res = inet_pton(AF_INET6, "::1", buf); + res = zsock_inet_pton(AF_INET6, "::1", buf); zassert_equal(res, 1, ""); - res = inet_pton(AF_INET6, "1::", buf); + res = zsock_inet_pton(AF_INET6, "1::", buf); zassert_equal(res, 1, ""); - res = inet_pton(AF_INET6, "a:b:c:d:0:1:2:3z", buf); + res = zsock_inet_pton(AF_INET6, "a:b:c:d:0:1:2:3z", buf); zassert_equal(res, 0, ""); } @@ -181,14 +181,14 @@ void test_so_bindtodevice(int sock_c, int sock_s, struct sockaddr *peer_addr, uint8_t send_buf[32]; uint8_t recv_buf[sizeof(send_buf)] = { 0 }; - ret = bind(sock_s, bind_addr, bind_addrlen); + ret = zsock_bind(sock_s, bind_addr, bind_addrlen); zassert_equal(ret, 0, "bind failed, %d", errno); /* Bind server socket with interface 2. */ strcpy(ifreq.ifr_name, DEV2_NAME); - ret = setsockopt(sock_s, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, - sizeof(ifreq)); + ret = zsock_setsockopt(sock_s, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, + sizeof(ifreq)); zassert_equal(ret, 0, "SO_BINDTODEVICE failed, %d", errno); /* Bind client socket with interface 1 and send a packet. */ @@ -198,12 +198,12 @@ void test_so_bindtodevice(int sock_c, int sock_s, struct sockaddr *peer_addr, strcpy(ifreq.ifr_name, DEV1_NAME); strcpy(send_buf, DEV1_NAME); - ret = setsockopt(sock_c, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, - sizeof(ifreq)); + ret = zsock_setsockopt(sock_c, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, + sizeof(ifreq)); zassert_equal(ret, 0, "SO_BINDTODEVICE failed, %d", errno); - ret = sendto(sock_c, send_buf, strlen(send_buf) + 1, 0, - peer_addr, peer_addrlen); + ret = zsock_sendto(sock_c, send_buf, strlen(send_buf) + 1, 0, + peer_addr, peer_addrlen); zassert_equal(ret, strlen(send_buf) + 1, "sendto failed, %d", errno); ret = sys_sem_take(&send_sem, K_MSEC(100)); @@ -223,12 +223,12 @@ void test_so_bindtodevice(int sock_c, int sock_s, struct sockaddr *peer_addr, strcpy(ifreq.ifr_name, DEV2_NAME); strcpy(send_buf, DEV2_NAME); - ret = setsockopt(sock_c, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, - sizeof(ifreq)); + ret = zsock_setsockopt(sock_c, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, + sizeof(ifreq)); zassert_equal(ret, 0, "SO_BINDTODEVICE failed, %d", errno); - ret = sendto(sock_c, send_buf, strlen(send_buf) + 1, 0, - peer_addr, peer_addrlen); + ret = zsock_sendto(sock_c, send_buf, strlen(send_buf) + 1, 0, + peer_addr, peer_addrlen); zassert_equal(ret, strlen(send_buf) + 1, "sendto failed, %d", errno); ret = sys_sem_take(&send_sem, K_MSEC(100)); @@ -243,7 +243,7 @@ void test_so_bindtodevice(int sock_c, int sock_s, struct sockaddr *peer_addr, k_msleep(10); - ret = recv(sock_s, recv_buf, sizeof(recv_buf), MSG_DONTWAIT); + ret = zsock_recv(sock_s, recv_buf, sizeof(recv_buf), ZSOCK_MSG_DONTWAIT); zassert_true(ret > 0, "recv failed, %d", errno); zassert_mem_equal(recv_buf, DEV2_NAME, strlen(DEV2_NAME), "received datagram from invalid interface"); @@ -251,8 +251,8 @@ void test_so_bindtodevice(int sock_c, int sock_s, struct sockaddr *peer_addr, /* Remove the binding from the server socket. */ strcpy(ifreq.ifr_name, ""); - ret = setsockopt(sock_s, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, - sizeof(ifreq)); + ret = zsock_setsockopt(sock_s, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, + sizeof(ifreq)); zassert_equal(ret, 0, "SO_BINDTODEVICE failed, %d", errno); /* Bind client socket with interface 1 again. */ @@ -261,12 +261,12 @@ void test_so_bindtodevice(int sock_c, int sock_s, struct sockaddr *peer_addr, strcpy(ifreq.ifr_name, DEV1_NAME); strcpy(send_buf, DEV1_NAME); - ret = setsockopt(sock_c, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, - sizeof(ifreq)); + ret = zsock_setsockopt(sock_c, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, + sizeof(ifreq)); zassert_equal(ret, 0, "SO_BINDTODEVICE failed, %d", errno); - ret = sendto(sock_c, send_buf, strlen(send_buf) + 1, 0, - peer_addr, peer_addrlen); + ret = zsock_sendto(sock_c, send_buf, strlen(send_buf) + 1, 0, + peer_addr, peer_addrlen); zassert_equal(ret, strlen(send_buf) + 1, "sendto failed, %d", errno); ret = sys_sem_take(&send_sem, K_MSEC(100)); @@ -280,14 +280,14 @@ void test_so_bindtodevice(int sock_c, int sock_s, struct sockaddr *peer_addr, k_msleep(10); - ret = recv(sock_s, recv_buf, sizeof(recv_buf), MSG_DONTWAIT); + ret = zsock_recv(sock_s, recv_buf, sizeof(recv_buf), ZSOCK_MSG_DONTWAIT); zassert_true(ret > 0, "recv failed, %d", errno); zassert_mem_equal(recv_buf, DEV1_NAME, strlen(DEV1_NAME), "received datagram from invalid interface"); - ret = close(sock_c); + ret = zsock_close(sock_c); zassert_equal(ret, 0, "close failed, %d", errno); - ret = close(sock_s); + ret = zsock_close(sock_s); zassert_equal(ret, 0, "close failed, %d", errno); k_sleep(K_MSEC(CONFIG_NET_TCP_TIME_WAIT_DELAY)); @@ -305,15 +305,15 @@ void test_ipv4_so_bindtodevice(void) .sin_addr = INADDR_ANY_INIT, }; - sock_c = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + sock_c = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); zassert_true(sock_c >= 0, "socket open failed"); - sock_s = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + sock_s = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); zassert_true(sock_s >= 0, "socket open failed"); peer_addr.sin_family = AF_INET; peer_addr.sin_port = htons(DST_PORT); - ret = inet_pton(AF_INET, TEST_PEER_IPV4_ADDR, - &peer_addr.sin_addr); + ret = zsock_inet_pton(AF_INET, TEST_PEER_IPV4_ADDR, + &peer_addr.sin_addr); zassert_equal(ret, 1, "inet_pton failed"); test_so_bindtodevice(sock_c, sock_s, (struct sockaddr *)&peer_addr, @@ -333,15 +333,15 @@ void test_ipv6_so_bindtodevice(void) .sin6_addr = IN6ADDR_ANY_INIT, }; - sock_c = socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP); + sock_c = zsock_socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP); zassert_true(sock_c >= 0, "socket open failed"); - sock_s = socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP); + sock_s = zsock_socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP); zassert_true(sock_s >= 0, "socket open failed"); peer_addr.sin6_family = AF_INET6; peer_addr.sin6_port = htons(DST_PORT); - ret = inet_pton(AF_INET6, TEST_PEER_IPV6_ADDR, - &peer_addr.sin6_addr); + ret = zsock_inet_pton(AF_INET6, TEST_PEER_IPV6_ADDR, + &peer_addr.sin6_addr); zassert_equal(ret, 1, "inet_pton failed"); test_so_bindtodevice(sock_c, sock_s, (struct sockaddr *)&peer_addr, @@ -365,67 +365,67 @@ void test_getpeername(int family) srv_addr.sa_family = family; if (family == AF_INET) { net_sin(&srv_addr)->sin_port = htons(DST_PORT); - ret = inet_pton(AF_INET, TEST_MY_IPV4_ADDR, - &net_sin(&srv_addr)->sin_addr); + ret = zsock_inet_pton(AF_INET, TEST_MY_IPV4_ADDR, + &net_sin(&srv_addr)->sin_addr); } else { net_sin6(&srv_addr)->sin6_port = htons(DST_PORT); - ret = inet_pton(AF_INET6, TEST_MY_IPV6_ADDR, - &net_sin6(&srv_addr)->sin6_addr); + ret = zsock_inet_pton(AF_INET6, TEST_MY_IPV6_ADDR, + &net_sin6(&srv_addr)->sin6_addr); } zassert_equal(ret, 1, "inet_pton failed"); /* UDP socket */ - sock_c = socket(family, SOCK_DGRAM, IPPROTO_UDP); + sock_c = zsock_socket(family, SOCK_DGRAM, IPPROTO_UDP); zassert_true(sock_c >= 0, "socket open failed"); peer_addr_len = ADDR_SIZE(family); - ret = getpeername(sock_c, &peer_addr, &peer_addr_len); + ret = zsock_getpeername(sock_c, &peer_addr, &peer_addr_len); zassert_equal(ret, -1, "getpeername shouldn've failed"); zassert_equal(errno, ENOTCONN, "getpeername returned invalid error"); - ret = connect(sock_c, &srv_addr, ADDR_SIZE(family)); + ret = zsock_connect(sock_c, &srv_addr, ADDR_SIZE(family)); zassert_equal(ret, 0, "connect failed"); memset(&peer_addr, 0, sizeof(peer_addr)); peer_addr_len = ADDR_SIZE(family); - ret = getpeername(sock_c, &peer_addr, &peer_addr_len); + ret = zsock_getpeername(sock_c, &peer_addr, &peer_addr_len); zassert_equal(ret, 0, "getpeername failed"); zassert_mem_equal(&peer_addr, &srv_addr, ADDR_SIZE(family), "obtained wrong address"); - ret = close(sock_c); + ret = zsock_close(sock_c); zassert_equal(ret, 0, "close failed, %d", errno); /* TCP socket */ - sock_c = socket(family, SOCK_STREAM, IPPROTO_TCP); + sock_c = zsock_socket(family, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_c >= 0, "socket open failed"); - sock_s = socket(family, SOCK_STREAM, IPPROTO_TCP); + sock_s = zsock_socket(family, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_s >= 0, "socket open failed"); - ret = bind(sock_s, &srv_addr, ADDR_SIZE(family)); + ret = zsock_bind(sock_s, &srv_addr, ADDR_SIZE(family)); zassert_equal(ret, 0, "bind failed, %d", errno); - ret = listen(sock_s, 1); + ret = zsock_listen(sock_s, 1); zassert_equal(ret, 0, "listen failed, %d", errno); peer_addr_len = ADDR_SIZE(family); - ret = getpeername(sock_c, &peer_addr, &peer_addr_len); + ret = zsock_getpeername(sock_c, &peer_addr, &peer_addr_len); zassert_equal(ret, -1, "getpeername shouldn've failed"); zassert_equal(errno, ENOTCONN, "getpeername returned invalid error"); - ret = connect(sock_c, &srv_addr, ADDR_SIZE(family)); + ret = zsock_connect(sock_c, &srv_addr, ADDR_SIZE(family)); zassert_equal(ret, 0, "connect failed"); memset(&peer_addr, 0, sizeof(peer_addr)); peer_addr_len = ADDR_SIZE(family); - ret = getpeername(sock_c, &peer_addr, &peer_addr_len); + ret = zsock_getpeername(sock_c, &peer_addr, &peer_addr_len); zassert_equal(ret, 0, "getpeername failed"); zassert_mem_equal(&peer_addr, &srv_addr, ADDR_SIZE(family), "obtained wrong address"); - ret = close(sock_c); + ret = zsock_close(sock_c); zassert_equal(ret, 0, "close failed, %d", errno); - ret = close(sock_s); + ret = zsock_close(sock_s); zassert_equal(ret, 0, "close failed, %d", errno); k_sleep(K_MSEC(2 * CONFIG_NET_TCP_TIME_WAIT_DELAY)); @@ -454,58 +454,58 @@ void test_getsockname_tcp(int family) srv_addr.sa_family = family; if (family == AF_INET) { net_sin(&srv_addr)->sin_port = htons(DST_PORT); - ret = inet_pton(AF_INET, TEST_MY_IPV4_ADDR, - &net_sin(&srv_addr)->sin_addr); + ret = zsock_inet_pton(AF_INET, TEST_MY_IPV4_ADDR, + &net_sin(&srv_addr)->sin_addr); } else { net_sin6(&srv_addr)->sin6_port = htons(DST_PORT); - ret = inet_pton(AF_INET6, TEST_MY_IPV6_ADDR, - &net_sin6(&srv_addr)->sin6_addr); + ret = zsock_inet_pton(AF_INET6, TEST_MY_IPV6_ADDR, + &net_sin6(&srv_addr)->sin6_addr); } zassert_equal(ret, 1, "inet_pton failed"); - sock_c = socket(family, SOCK_STREAM, IPPROTO_TCP); + sock_c = zsock_socket(family, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_c >= 0, "socket open failed"); - sock_s = socket(family, SOCK_STREAM, IPPROTO_TCP); + sock_s = zsock_socket(family, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_s >= 0, "socket open failed"); /* Verify that unbound/unconnected socket has no local address set */ - ret = getsockname(sock_c, &local_addr, &local_addr_len); + ret = zsock_getsockname(sock_c, &local_addr, &local_addr_len); zassert_equal(ret, -1, "getsockname shouldn've failed"); zassert_equal(errno, EINVAL, "getsockname returned invalid error"); - ret = getsockname(sock_s, &local_addr, &local_addr_len); + ret = zsock_getsockname(sock_s, &local_addr, &local_addr_len); zassert_equal(ret, -1, "getsockname shouldn've failed"); zassert_equal(errno, EINVAL, "getsockname returned invalid error"); /* Verify that getsockname() can read local address of a bound socket */ - ret = bind(sock_s, &srv_addr, ADDR_SIZE(family)); + ret = zsock_bind(sock_s, &srv_addr, ADDR_SIZE(family)); zassert_equal(ret, 0, "bind failed, %d", errno); memset(&local_addr, 0, sizeof(local_addr)); local_addr_len = ADDR_SIZE(family); - ret = getsockname(sock_s, &local_addr, &local_addr_len); + ret = zsock_getsockname(sock_s, &local_addr, &local_addr_len); zassert_equal(ret, 0, "getsockname failed"); zassert_mem_equal(&local_addr, &srv_addr, ADDR_SIZE(family), "obtained wrong address"); - ret = listen(sock_s, 1); + ret = zsock_listen(sock_s, 1); zassert_equal(ret, 0, "listen failed, %d", errno); /* Verify that getsockname() can read local address of a connected socket */ - ret = connect(sock_c, &srv_addr, ADDR_SIZE(family)); + ret = zsock_connect(sock_c, &srv_addr, ADDR_SIZE(family)); zassert_equal(ret, 0, "connect failed"); memset(&local_addr, 0, sizeof(local_addr)); local_addr_len = ADDR_SIZE(family); - ret = getsockname(sock_c, &local_addr, &local_addr_len); + ret = zsock_getsockname(sock_c, &local_addr, &local_addr_len); zassert_equal(ret, 0, "getsockname failed"); zassert_equal(local_addr.sa_family, family, "wrong family"); /* Can't verify address/port of client socket here reliably as they're * chosen by net stack */ - ret = close(sock_c); + ret = zsock_close(sock_c); zassert_equal(ret, 0, "close failed, %d", errno); - ret = close(sock_s); + ret = zsock_close(sock_s); zassert_equal(ret, 0, "close failed, %d", errno); k_sleep(K_MSEC(CONFIG_NET_TCP_TIME_WAIT_DELAY)); @@ -523,55 +523,55 @@ void test_getsockname_udp(int family) srv_addr.sa_family = family; if (family == AF_INET) { net_sin(&srv_addr)->sin_port = htons(DST_PORT); - ret = inet_pton(AF_INET, TEST_MY_IPV4_ADDR, - &net_sin(&srv_addr)->sin_addr); + ret = zsock_inet_pton(AF_INET, TEST_MY_IPV4_ADDR, + &net_sin(&srv_addr)->sin_addr); } else { net_sin6(&srv_addr)->sin6_port = htons(DST_PORT); - ret = inet_pton(AF_INET6, TEST_MY_IPV6_ADDR, - &net_sin6(&srv_addr)->sin6_addr); + ret = zsock_inet_pton(AF_INET6, TEST_MY_IPV6_ADDR, + &net_sin6(&srv_addr)->sin6_addr); } zassert_equal(ret, 1, "inet_pton failed"); - sock_c = socket(family, SOCK_DGRAM, IPPROTO_UDP); + sock_c = zsock_socket(family, SOCK_DGRAM, IPPROTO_UDP); zassert_true(sock_c >= 0, "socket open failed"); - sock_s = socket(family, SOCK_DGRAM, IPPROTO_UDP); + sock_s = zsock_socket(family, SOCK_DGRAM, IPPROTO_UDP); zassert_true(sock_s >= 0, "socket open failed"); /* Verify that unbound/unconnected socket has no local address set */ - ret = getsockname(sock_c, &local_addr, &local_addr_len); + ret = zsock_getsockname(sock_c, &local_addr, &local_addr_len); zassert_equal(ret, -1, "getsockname shouldn've failed"); zassert_equal(errno, EINVAL, "getsockname returned invalid error"); - ret = getsockname(sock_s, &local_addr, &local_addr_len); + ret = zsock_getsockname(sock_s, &local_addr, &local_addr_len); zassert_equal(ret, -1, "getsockname shouldn've failed"); zassert_equal(errno, EINVAL, "getsockname returned invalid error"); /* Verify that getsockname() can read local address of a bound socket */ - ret = bind(sock_s, &srv_addr, ADDR_SIZE(family)); + ret = zsock_bind(sock_s, &srv_addr, ADDR_SIZE(family)); zassert_equal(ret, 0, "bind failed, %d", errno); memset(&local_addr, 0, sizeof(local_addr)); local_addr_len = ADDR_SIZE(family); - ret = getsockname(sock_s, &local_addr, &local_addr_len); + ret = zsock_getsockname(sock_s, &local_addr, &local_addr_len); zassert_equal(ret, 0, "getsockname failed"); zassert_mem_equal(&local_addr, &srv_addr, ADDR_SIZE(family), "obtained wrong address"); /* Verify that getsockname() can read local address of a connected socket */ - ret = connect(sock_c, &srv_addr, ADDR_SIZE(family)); + ret = zsock_connect(sock_c, &srv_addr, ADDR_SIZE(family)); zassert_equal(ret, 0, "connect failed"); memset(&local_addr, 0, sizeof(local_addr)); local_addr_len = ADDR_SIZE(family); - ret = getsockname(sock_c, &local_addr, &local_addr_len); + ret = zsock_getsockname(sock_c, &local_addr, &local_addr_len); zassert_equal(ret, 0, "getsockname failed"); zassert_equal(local_addr.sa_family, family, "wrong family"); /* Can't verify address/port of client socket here reliably as they're * chosen by net stack */ - ret = close(sock_c); + ret = zsock_close(sock_c); zassert_equal(ret, 0, "close failed, %d", errno); - ret = close(sock_s); + ret = zsock_close(sock_s); zassert_equal(ret, 0, "close failed, %d", errno); } @@ -590,34 +590,34 @@ void test_ipv4_mapped_to_ipv6_disabled(void) srv_addr4.sa_family = AF_INET; net_sin(&srv_addr4)->sin_port = htons(MAPPING_PORT); - ret = inet_pton(AF_INET, TEST_MY_IPV4_ADDR, - &net_sin(&srv_addr4)->sin_addr); + ret = zsock_inet_pton(AF_INET, TEST_MY_IPV4_ADDR, + &net_sin(&srv_addr4)->sin_addr); zassert_equal(ret, 1, "inet_pton failed"); srv_addr6.sa_family = AF_INET6; net_sin6(&srv_addr6)->sin6_port = htons(MAPPING_PORT); - ret = inet_pton(AF_INET6, TEST_MY_IPV6_ADDR, - &net_sin6(&srv_addr6)->sin6_addr); + ret = zsock_inet_pton(AF_INET6, TEST_MY_IPV6_ADDR, + &net_sin6(&srv_addr6)->sin6_addr); zassert_equal(ret, 1, "inet_pton failed"); - sock_s4 = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); + sock_s4 = zsock_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_s4 >= 0, "socket open failed"); - ret = bind(sock_s4, &srv_addr4, ADDR_SIZE(AF_INET)); + ret = zsock_bind(sock_s4, &srv_addr4, ADDR_SIZE(AF_INET)); zassert_equal(ret, 0, "bind failed, %d", errno); - ret = listen(sock_s4, 1); + ret = zsock_listen(sock_s4, 1); zassert_equal(ret, 0, "listen failed, %d", errno); - sock_s6 = socket(AF_INET6, SOCK_STREAM, IPPROTO_TCP); + sock_s6 = zsock_socket(AF_INET6, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_s6 >= 0, "socket open failed"); - ret = bind(sock_s6, &srv_addr6, ADDR_SIZE(AF_INET6)); + ret = zsock_bind(sock_s6, &srv_addr6, ADDR_SIZE(AF_INET6)); zassert_equal(ret, 0, "bind failed, %d", errno); - ret = close(sock_s4); + ret = zsock_close(sock_s4); zassert_equal(ret, 0, "close failed, %d", errno); - ret = close(sock_s6); + ret = zsock_close(sock_s6); zassert_equal(ret, 0, "close failed, %d", errno); } @@ -639,58 +639,58 @@ void test_ipv4_mapped_to_ipv6_enabled(void) */ srv_addr4.sa_family = AF_INET; net_sin(&srv_addr4)->sin_port = htons(MAPPING_PORT); - ret = inet_pton(AF_INET, "0.0.0.0", - &net_sin(&srv_addr4)->sin_addr); + ret = zsock_inet_pton(AF_INET, "0.0.0.0", + &net_sin(&srv_addr4)->sin_addr); zassert_equal(ret, 1, "inet_pton failed"); srv_addr6.sa_family = AF_INET6; net_sin6(&srv_addr6)->sin6_port = htons(MAPPING_PORT); - ret = inet_pton(AF_INET6, "::", - &net_sin6(&srv_addr6)->sin6_addr); + ret = zsock_inet_pton(AF_INET6, "::", + &net_sin6(&srv_addr6)->sin6_addr); zassert_equal(ret, 1, "inet_pton failed"); /* First create IPv6 socket */ - sock_s6 = socket(AF_INET6, SOCK_STREAM, IPPROTO_TCP); + sock_s6 = zsock_socket(AF_INET6, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_s6 >= 0, "socket open failed"); - ret = bind(sock_s6, &srv_addr6, ADDR_SIZE(AF_INET6)); + ret = zsock_bind(sock_s6, &srv_addr6, ADDR_SIZE(AF_INET6)); zassert_equal(ret, 0, "bind failed, %d", errno); - ret = listen(sock_s6, 1); + ret = zsock_listen(sock_s6, 1); zassert_equal(ret, 0, "listen failed, %d", errno); /* Then try to create IPv4 socket to the same port */ - sock_s4 = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); + sock_s4 = zsock_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_s4 >= 0, "socket open failed"); /* Initially the IPV6_V6ONLY is set so the next bind is ok */ - ret = bind(sock_s4, &srv_addr4, ADDR_SIZE(AF_INET)); + ret = zsock_bind(sock_s4, &srv_addr4, ADDR_SIZE(AF_INET)); zassert_equal(ret, 0, "bind failed, %d", errno); - ret = close(sock_s4); + ret = zsock_close(sock_s4); zassert_equal(ret, 0, "close failed, %d", errno); /* Then we turn off IPV6_V6ONLY which means that IPv4 and IPv6 * will have same port space and the next bind should fail. */ - ret = setsockopt(sock_s6, IPPROTO_IPV6, IPV6_V6ONLY, &off, sizeof(off)); + ret = zsock_setsockopt(sock_s6, IPPROTO_IPV6, IPV6_V6ONLY, &off, sizeof(off)); zassert_equal(ret, 0, "setsockopt failed, %d", errno); - ret = getsockopt(sock_s6, IPPROTO_IPV6, IPV6_V6ONLY, &off, &optlen); + ret = zsock_getsockopt(sock_s6, IPPROTO_IPV6, IPV6_V6ONLY, &off, &optlen); zassert_equal(ret, 0, "getsockopt failed, %d", errno); zassert_equal(off, 0, "IPV6_V6ONLY option setting failed"); - sock_s4 = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); + sock_s4 = zsock_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_s4 >= 0, "socket open failed"); /* Now v4 bind should fail */ - ret = bind(sock_s4, &srv_addr4, ADDR_SIZE(AF_INET)); + ret = zsock_bind(sock_s4, &srv_addr4, ADDR_SIZE(AF_INET)); zassert_equal(ret, -1, "bind failed, %d", errno); zassert_equal(errno, EADDRINUSE, "bind failed"); - ret = close(sock_s4); + ret = zsock_close(sock_s4); zassert_equal(ret, 0, "close failed, %d", errno); - ret = close(sock_s6); + ret = zsock_close(sock_s6); zassert_equal(ret, 0, "close failed, %d", errno); } @@ -723,14 +723,14 @@ void test_ipv4_mapped_to_ipv6_server(void) */ srv_addr.sa_family = AF_INET; net_sin(&srv_addr)->sin_port = htons(MAPPING_PORT); - ret = inet_pton(AF_INET, "192.0.2.1", - &net_sin(&srv_addr)->sin_addr); + ret = zsock_inet_pton(AF_INET, "192.0.2.1", + &net_sin(&srv_addr)->sin_addr); zassert_equal(ret, 1, "inet_pton failed"); connect_addr6.sa_family = AF_INET6; net_sin6(&connect_addr6)->sin6_port = htons(MAPPING_PORT); - ret = inet_pton(AF_INET6, TEST_PEER_IPV6_ADDR, - &net_sin6(&connect_addr6)->sin6_addr); + ret = zsock_inet_pton(AF_INET6, TEST_PEER_IPV6_ADDR, + &net_sin6(&connect_addr6)->sin6_addr); zassert_equal(ret, 1, "inet_pton failed"); net_ipv6_addr_create_v4_mapped(&net_sin(&srv_addr)->sin_addr, @@ -741,16 +741,16 @@ void test_ipv4_mapped_to_ipv6_server(void) */ srv_addr6.sa_family = AF_INET6; net_sin6(&srv_addr6)->sin6_port = htons(MAPPING_PORT); - ret = inet_pton(AF_INET6, "::", - &net_sin6(&srv_addr6)->sin6_addr); + ret = zsock_inet_pton(AF_INET6, "::", + &net_sin6(&srv_addr6)->sin6_addr); zassert_equal(ret, 1, "inet_pton failed"); /* First create IPv6 socket */ - sock_s6 = socket(AF_INET6, SOCK_STREAM, IPPROTO_TCP); + sock_s6 = zsock_socket(AF_INET6, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_s6 >= 0, "socket open failed"); /* Verify that by default the IPV6_V6ONLY option is set */ - ret = getsockopt(sock_s6, IPPROTO_IPV6, IPV6_V6ONLY, &off, &optlen); + ret = zsock_getsockopt(sock_s6, IPPROTO_IPV6, IPV6_V6ONLY, &off, &optlen); zassert_equal(ret, 0, "getsockopt failed, %d", errno); zassert_not_equal(off, 0, "IPV6_V6ONLY option setting failed"); @@ -758,27 +758,27 @@ void test_ipv4_mapped_to_ipv6_server(void) * will have same port space. */ off = 0; - ret = setsockopt(sock_s6, IPPROTO_IPV6, IPV6_V6ONLY, &off, sizeof(off)); + ret = zsock_setsockopt(sock_s6, IPPROTO_IPV6, IPV6_V6ONLY, &off, sizeof(off)); zassert_equal(ret, 0, "setsockopt failed, %d", errno); - ret = getsockopt(sock_s6, IPPROTO_IPV6, IPV6_V6ONLY, &off, &optlen); + ret = zsock_getsockopt(sock_s6, IPPROTO_IPV6, IPV6_V6ONLY, &off, &optlen); zassert_equal(ret, 0, "getsockopt failed, %d", errno); zassert_equal(off, 0, "IPV6_V6ONLY option setting failed, %d", off); - ret = bind(sock_s6, &srv_addr6, ADDR_SIZE(AF_INET6)); + ret = zsock_bind(sock_s6, &srv_addr6, ADDR_SIZE(AF_INET6)); zassert_equal(ret, 0, "bind failed, %d", errno); - ret = listen(sock_s6, 1); + ret = zsock_listen(sock_s6, 1); zassert_equal(ret, 0, "listen failed, %d", errno); /* Then create IPv4 socket and connect to the IPv6 port */ - sock_c4 = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); + sock_c4 = zsock_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_c4 >= 0, "socket open failed"); - ret = connect(sock_c4, &srv_addr, ADDR_SIZE(AF_INET)); + ret = zsock_connect(sock_c4, &srv_addr, ADDR_SIZE(AF_INET)); zassert_equal(ret, 0, "connect failed"); - new_sock = accept(sock_s6, &addr, &addrlen); + new_sock = zsock_accept(sock_s6, &addr, &addrlen); zassert_true(new_sock >= 0, "accept failed, %d", errno); /* Note that we should get IPv6 address here (mapped from IPv4) */ @@ -793,44 +793,44 @@ void test_ipv4_mapped_to_ipv6_server(void) net_sprint_ipv6_addr(&net_sin6(&addr)->sin6_addr)); /* Send data back to IPv4 client from IPv6 socket */ - ret = send(new_sock, "foobar", len, 0); + ret = zsock_send(new_sock, "foobar", len, 0); zassert_equal(ret, len, "cannot send (%d vs %d), errno %d", ret, len, errno); addrlen = sizeof(struct sockaddr_in); - ret = recv(sock_c4, buf, sizeof(buf), 0); + ret = zsock_recv(sock_c4, buf, sizeof(buf), 0); zassert_equal(ret, strlen("foobar"), "cannot recv"); - ret = close(sock_c4); + ret = zsock_close(sock_c4); zassert_equal(ret, 0, "close failed, %d", errno); - (void)close(new_sock); + (void)zsock_close(new_sock); /* Let the system stabilize and cleanup itself */ k_sleep(K_MSEC(200)); /* Then create IPv6 socket and make sure it works ok too */ - sock_c6 = socket(AF_INET6, SOCK_STREAM, IPPROTO_TCP); + sock_c6 = zsock_socket(AF_INET6, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_c6 >= 0, "socket open failed"); - ret = connect(sock_c6, &connect_addr6, ADDR_SIZE(AF_INET6)); + ret = zsock_connect(sock_c6, &connect_addr6, ADDR_SIZE(AF_INET6)); zassert_equal(ret, 0, "connect failed, %d", errno); - new_sock = accept(sock_s6, &addr, &addrlen); + new_sock = zsock_accept(sock_s6, &addr, &addrlen); zassert_true(new_sock >= 0, "accept failed, %d", errno); - ret = send(new_sock, "foobar", len, 0); + ret = zsock_send(new_sock, "foobar", len, 0); zassert_equal(ret, len, "cannot send (%d vs %d), errno %d", ret, len, errno); addrlen = sizeof(struct sockaddr_in); - ret = recv(sock_c6, buf, sizeof(buf), 0); + ret = zsock_recv(sock_c6, buf, sizeof(buf), 0); zassert_equal(ret, strlen("foobar"), "cannot recv"); - ret = close(sock_c6); + ret = zsock_close(sock_c6); zassert_equal(ret, 0, "close failed, %d", errno); - ret = close(sock_s6); + ret = zsock_close(sock_s6); zassert_equal(ret, 0, "close failed, %d", errno); - ret = close(new_sock); + ret = zsock_close(new_sock); zassert_equal(ret, 0, "close failed, %d", errno); } @@ -895,30 +895,30 @@ ZTEST(socket_misc_test_suite, test_so_domain_socket_option) socklen_t optlen = sizeof(int); int domain; - sock_t = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); + sock_t = zsock_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); zassert_true(sock_t >= 0, "TCP socket open failed"); - sock_u = socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP); + sock_u = zsock_socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP); zassert_true(sock_u >= 0, "UDP socket open failed"); - ret = getsockopt(sock_t, SOL_SOCKET, SO_DOMAIN, &domain, &optlen); + ret = zsock_getsockopt(sock_t, SOL_SOCKET, SO_DOMAIN, &domain, &optlen); zassert_equal(ret, 0, "getsockopt failed, %d", -errno); zassert_equal(domain, AF_INET, "Mismatch domain value %d vs %d", AF_INET, domain); - ret = getsockopt(sock_u, SOL_SOCKET, SO_DOMAIN, &domain, &optlen); + ret = zsock_getsockopt(sock_u, SOL_SOCKET, SO_DOMAIN, &domain, &optlen); zassert_equal(ret, 0, "getsockopt failed, %d", -errno); zassert_equal(domain, AF_INET6, "Mismatch domain value %d vs %d", AF_INET6, domain); /* setsockopt() is not supported for this option */ domain = AF_INET; - ret = setsockopt(sock_u, SOL_SOCKET, SO_DOMAIN, &domain, optlen); + ret = zsock_setsockopt(sock_u, SOL_SOCKET, SO_DOMAIN, &domain, optlen); zassert_equal(ret, -1, "setsockopt succeed"); zassert_equal(errno, ENOPROTOOPT, "Invalid errno %d", errno); - ret = close(sock_t); + ret = zsock_close(sock_t); zassert_equal(ret, 0, "close failed, %d", -errno); - ret = close(sock_u); + ret = zsock_close(sock_u); zassert_equal(ret, 0, "close failed, %d", -errno); } diff --git a/tests/net/socket/net_mgmt/prj.conf b/tests/net/socket/net_mgmt/prj.conf index d5c337242aa..44039b530d5 100644 --- a/tests/net/socket/net_mgmt/prj.conf +++ b/tests/net/socket/net_mgmt/prj.conf @@ -8,7 +8,6 @@ CONFIG_NET_TEST=y CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_NET_MGMT=y CONFIG_NET_MGMT=y CONFIG_NET_MGMT_EVENT=y diff --git a/tests/net/socket/net_mgmt/src/main.c b/tests/net/socket/net_mgmt/src/main.c index 0f5bec63462..455ae3e0d04 100644 --- a/tests/net/socket/net_mgmt/src/main.c +++ b/tests/net/socket/net_mgmt/src/main.c @@ -363,7 +363,7 @@ static void test_net_mgmt_setup(void) net_if_foreach(iface_cb, &default_iface); zassert_not_null(default_iface, "Cannot find test interface"); - fd = socket(AF_NET_MGMT, SOCK_DGRAM, NET_MGMT_EVENT_PROTO); + fd = zsock_socket(AF_NET_MGMT, SOCK_DGRAM, NET_MGMT_EVENT_PROTO); zassert_false(fd < 0, "Cannot create net_mgmt socket (%d)", errno); #ifdef CONFIG_USERSPACE @@ -385,7 +385,7 @@ static void test_net_mgmt_setup(void) NET_EVENT_IPV6_ADDR_ADD | NET_EVENT_IPV6_ADDR_DEL; - ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr)); + ret = zsock_bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr)); zassert_false(ret < 0, "Cannot bind net_mgmt socket (%d)", errno); k_thread_start(trigger_events_thread_id); @@ -406,9 +406,9 @@ static void test_net_mgmt_catch_events(void) memset(buf, 0, sizeof(buf)); event_addr_len = sizeof(event_addr); - ret = recvfrom(fd, buf, sizeof(buf), 0, - (struct sockaddr *)&event_addr, - &event_addr_len); + ret = zsock_recvfrom(fd, buf, sizeof(buf), 0, + (struct sockaddr *)&event_addr, + &event_addr_len); if (ret < 0) { continue; } @@ -468,9 +468,9 @@ static void test_net_mgmt_catch_events_failure(void) memset(buf, 0, sizeof(buf)); event_addr_len = sizeof(event_addr); - ret = recvfrom(fd, buf, sizeof(buf), 0, - (struct sockaddr *)&event_addr, - &event_addr_len); + ret = zsock_recvfrom(fd, buf, sizeof(buf), 0, + (struct sockaddr *)&event_addr, + &event_addr_len); zassert_equal(ret, -1, "Msg check failed, %d", errno); zassert_equal(errno, EMSGSIZE, "Msg check failed, errno %d", errno); } @@ -501,9 +501,9 @@ static void test_ethernet_set_qav(void) params.qav_param.type = ETHERNET_QAV_PARAM_TYPE_STATUS; params.qav_param.enabled = true; - ret = setsockopt(fd, SOL_NET_MGMT_RAW, - NET_REQUEST_ETHERNET_SET_QAV_PARAM, - ¶ms, sizeof(params)); + ret = zsock_setsockopt(fd, SOL_NET_MGMT_RAW, + NET_REQUEST_ETHERNET_SET_QAV_PARAM, + ¶ms, sizeof(params)); zassert_equal(ret, 0, "Cannot set Qav parameters"); } @@ -528,9 +528,9 @@ static void test_ethernet_get_qav(void) params.qav_param.queue_id = 1; params.qav_param.type = ETHERNET_QAV_PARAM_TYPE_STATUS; - ret = getsockopt(fd, SOL_NET_MGMT_RAW, - NET_REQUEST_ETHERNET_GET_QAV_PARAM, - ¶ms, &optlen); + ret = zsock_getsockopt(fd, SOL_NET_MGMT_RAW, + NET_REQUEST_ETHERNET_GET_QAV_PARAM, + ¶ms, &optlen); zassert_equal(ret, 0, "Cannot get Qav parameters (%d)", ret); zassert_equal(optlen, sizeof(params), "Invalid optlen (%d)", optlen); @@ -555,9 +555,9 @@ static void test_ethernet_get_unknown_option(void) memset(¶ms, 0, sizeof(params)); - ret = getsockopt(fd, SOL_NET_MGMT_RAW, - NET_REQUEST_ETHERNET_GET_PRIORITY_QUEUES_NUM, - ¶ms, &optlen); + ret = zsock_getsockopt(fd, SOL_NET_MGMT_RAW, + NET_REQUEST_ETHERNET_GET_PRIORITY_QUEUES_NUM, + ¶ms, &optlen); zassert_equal(ret, -1, "Could get prio queue parameters (%d)", errno); zassert_equal(errno, EINVAL, "prio queue get parameters"); } @@ -580,9 +580,9 @@ static void test_ethernet_set_unknown_option(void) memset(¶ms, 0, sizeof(params)); - ret = setsockopt(fd, SOL_NET_MGMT_RAW, - NET_REQUEST_ETHERNET_SET_MAC_ADDRESS, - ¶ms, optlen); + ret = zsock_setsockopt(fd, SOL_NET_MGMT_RAW, + NET_REQUEST_ETHERNET_SET_MAC_ADDRESS, + ¶ms, optlen); zassert_equal(ret, -1, "Could set promisc_mode parameters (%d)", errno); zassert_equal(errno, EINVAL, "promisc_mode set parameters"); } diff --git a/tests/net/socket/poll/prj.conf b/tests/net/socket/poll/prj.conf index fb9b598e32c..b708020ef43 100644 --- a/tests/net/socket/poll/prj.conf +++ b/tests/net/socket/poll/prj.conf @@ -5,7 +5,6 @@ CONFIG_NET_IPV6=y CONFIG_NET_UDP=y CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_POSIX_MAX_FDS=10 CONFIG_NET_PKT_TX_COUNT=8 CONFIG_NET_PKT_RX_COUNT=8 diff --git a/tests/net/socket/poll/src/main.c b/tests/net/socket/poll/src/main.c index 4668c1ea787..7b5eac449d5 100644 --- a/tests/net/socket/poll/src/main.c +++ b/tests/net/socket/poll/src/main.c @@ -40,8 +40,8 @@ ZTEST(net_socket_poll, test_poll) int s_sock_tcp; struct sockaddr_in6 c_addr; struct sockaddr_in6 s_addr; - struct pollfd pollfds[2]; - struct pollfd pollout[1]; + struct zsock_pollfd pollfds[2]; + struct zsock_pollfd pollout[1]; uint32_t tstamp; ssize_t len; char buf[10]; @@ -51,35 +51,35 @@ ZTEST(net_socket_poll, test_poll) prepare_sock_tcp_v6(MY_IPV6_ADDR, CLIENT_PORT, &c_sock_tcp, &c_addr); prepare_sock_tcp_v6(MY_IPV6_ADDR, SERVER_PORT, &s_sock_tcp, &s_addr); - res = bind(s_sock, (struct sockaddr *)&s_addr, sizeof(s_addr)); + res = zsock_bind(s_sock, (struct sockaddr *)&s_addr, sizeof(s_addr)); zassert_equal(res, 0, "bind failed"); - res = connect(c_sock, (struct sockaddr *)&s_addr, sizeof(s_addr)); + res = zsock_connect(c_sock, (struct sockaddr *)&s_addr, sizeof(s_addr)); zassert_equal(res, 0, "connect failed"); memset(pollfds, 0, sizeof(pollfds)); pollfds[0].fd = c_sock; - pollfds[0].events = POLLIN; + pollfds[0].events = ZSOCK_POLLIN; pollfds[1].fd = s_sock; - pollfds[1].events = POLLIN; + pollfds[1].events = ZSOCK_POLLIN; /* Poll non-ready fd's with timeout of 0 */ tstamp = k_uptime_get_32(); - res = poll(pollfds, ARRAY_SIZE(pollfds), 0); + res = zsock_poll(pollfds, ARRAY_SIZE(pollfds), 0); zassert_true(k_uptime_get_32() - tstamp <= FUZZ, ""); zassert_equal(res, 0, ""); zassert_equal(pollfds[0].fd, c_sock, ""); - zassert_equal(pollfds[0].events, POLLIN, ""); + zassert_equal(pollfds[0].events, ZSOCK_POLLIN, ""); zassert_equal(pollfds[0].revents, 0, ""); zassert_equal(pollfds[1].fd, s_sock, ""); - zassert_equal(pollfds[1].events, POLLIN, ""); + zassert_equal(pollfds[1].events, ZSOCK_POLLIN, ""); zassert_equal(pollfds[1].revents, 0, ""); /* Poll non-ready fd's with timeout of 30 */ tstamp = k_uptime_get_32(); - res = poll(pollfds, ARRAY_SIZE(pollfds), 30); + res = zsock_poll(pollfds, ARRAY_SIZE(pollfds), 30); tstamp = k_uptime_get_32() - tstamp; zassert_true(tstamp >= 30U && tstamp <= 30 + FUZZ * 2, "tstamp %d", tstamp); @@ -87,29 +87,29 @@ ZTEST(net_socket_poll, test_poll) /* Send pkt for s_sock and poll with timeout of 10 */ - len = send(c_sock, BUF_AND_SIZE(TEST_STR_SMALL), 0); + len = zsock_send(c_sock, BUF_AND_SIZE(TEST_STR_SMALL), 0); zassert_equal(len, STRLEN(TEST_STR_SMALL), "invalid send len"); tstamp = k_uptime_get_32(); - res = poll(pollfds, ARRAY_SIZE(pollfds), 30); + res = zsock_poll(pollfds, ARRAY_SIZE(pollfds), 30); tstamp = k_uptime_get_32() - tstamp; zassert_true(tstamp <= FUZZ, ""); zassert_equal(res, 1, ""); zassert_equal(pollfds[0].fd, c_sock, ""); - zassert_equal(pollfds[0].events, POLLIN, ""); + zassert_equal(pollfds[0].events, ZSOCK_POLLIN, ""); zassert_equal(pollfds[0].revents, 0, ""); zassert_equal(pollfds[1].fd, s_sock, ""); - zassert_equal(pollfds[1].events, POLLIN, ""); - zassert_equal(pollfds[1].revents, POLLIN, ""); + zassert_equal(pollfds[1].events, ZSOCK_POLLIN, ""); + zassert_equal(pollfds[1].revents, ZSOCK_POLLIN, ""); /* Recv pkt from s_sock and ensure no poll events happen */ - len = recv(s_sock, BUF_AND_SIZE(buf), 0); + len = zsock_recv(s_sock, BUF_AND_SIZE(buf), 0); zassert_equal(len, STRLEN(TEST_STR_SMALL), "invalid recv len"); tstamp = k_uptime_get_32(); - res = poll(pollfds, ARRAY_SIZE(pollfds), 0); + res = zsock_poll(pollfds, ARRAY_SIZE(pollfds), 0); zassert_true(k_uptime_get_32() - tstamp <= FUZZ, ""); zassert_equal(res, 0, ""); zassert_equal(pollfds[1].revents, 0, ""); @@ -117,61 +117,61 @@ ZTEST(net_socket_poll, test_poll) /* Make sure that POLLOUT does not wait if not really needed */ memset(pollout, 0, sizeof(pollout)); pollout[0].fd = c_sock; - pollout[0].events = POLLOUT; + pollout[0].events = ZSOCK_POLLOUT; - res = connect(c_sock, (const struct sockaddr *)&s_addr, - sizeof(s_addr)); + res = zsock_connect(c_sock, (const struct sockaddr *)&s_addr, + sizeof(s_addr)); zassert_equal(res, 0, ""); tstamp = k_uptime_get_32(); - res = poll(pollout, ARRAY_SIZE(pollout), 200); + res = zsock_poll(pollout, ARRAY_SIZE(pollout), 200); zassert_true(k_uptime_get_32() - tstamp < 100, ""); zassert_equal(res, 1, ""); - zassert_equal(pollout[0].revents, POLLOUT, ""); + zassert_equal(pollout[0].revents, ZSOCK_POLLOUT, ""); /* First test that TCP POLLOUT will not wait if there is enough * room in TCP window */ memset(pollout, 0, sizeof(pollout)); pollout[0].fd = c_sock_tcp; - pollout[0].events = POLLOUT; + pollout[0].events = ZSOCK_POLLOUT; - res = bind(s_sock_tcp, (struct sockaddr *)&s_addr, sizeof(s_addr)); + res = zsock_bind(s_sock_tcp, (struct sockaddr *)&s_addr, sizeof(s_addr)); zassert_equal(res, 0, ""); - res = listen(s_sock_tcp, 0); + res = zsock_listen(s_sock_tcp, 0); zassert_equal(res, 0, ""); - res = connect(c_sock_tcp, (const struct sockaddr *)&s_addr, - sizeof(s_addr)); + res = zsock_connect(c_sock_tcp, (const struct sockaddr *)&s_addr, + sizeof(s_addr)); zassert_equal(res, 0, ""); tstamp = k_uptime_get_32(); - res = poll(pollout, ARRAY_SIZE(pollout), 200); + res = zsock_poll(pollout, ARRAY_SIZE(pollout), 200); zassert_true(k_uptime_get_32() - tstamp < 100, ""); zassert_equal(res, 1, ""); - zassert_equal(pollout[0].revents, POLLOUT, ""); + zassert_equal(pollout[0].revents, ZSOCK_POLLOUT, ""); /* Let the network stack run */ k_msleep(10); - res = close(c_sock_tcp); + res = zsock_close(c_sock_tcp); zassert_equal(res, 0, "close failed"); - res = close(s_sock_tcp); + res = zsock_close(s_sock_tcp); zassert_equal(res, 0, "close failed"); /* Close one socket and ensure POLLNVAL happens */ - res = close(c_sock); + res = zsock_close(c_sock); zassert_equal(res, 0, "close failed"); tstamp = k_uptime_get_32(); - res = poll(pollfds, ARRAY_SIZE(pollfds), 0); + res = zsock_poll(pollfds, ARRAY_SIZE(pollfds), 0); zassert_true(k_uptime_get_32() - tstamp <= FUZZ, ""); zassert_equal(res, 1, ""); - zassert_equal(pollfds[0].revents, POLLNVAL, ""); + zassert_equal(pollfds[0].revents, ZSOCK_POLLNVAL, ""); zassert_equal(pollfds[1].revents, 0, ""); - res = close(s_sock); + res = zsock_close(s_sock); zassert_equal(res, 0, "close failed"); k_sleep(TCP_TEARDOWN_TIMEOUT); @@ -187,20 +187,20 @@ ZTEST(net_socket_poll, test_pollout_tcp) int new_sock; struct sockaddr_in6 c_addr; struct sockaddr_in6 s_addr; - struct pollfd pollout[1]; + struct zsock_pollfd pollout[1]; char buf[TEST_SNDBUF_SIZE] = { }; prepare_sock_tcp_v6(MY_IPV6_ADDR, CLIENT_PORT, &c_sock, &c_addr); prepare_sock_tcp_v6(MY_IPV6_ADDR, SERVER_PORT, &s_sock, &s_addr); - res = bind(s_sock, (struct sockaddr *)&s_addr, sizeof(s_addr)); + res = zsock_bind(s_sock, (struct sockaddr *)&s_addr, sizeof(s_addr)); zassert_equal(res, 0, ""); - res = listen(s_sock, 0); + res = zsock_listen(s_sock, 0); zassert_equal(res, 0, ""); - res = connect(c_sock, (const struct sockaddr *)&s_addr, - sizeof(s_addr)); + res = zsock_connect(c_sock, (const struct sockaddr *)&s_addr, + sizeof(s_addr)); zassert_equal(res, 0, ""); - new_sock = accept(s_sock, NULL, NULL); + new_sock = zsock_accept(s_sock, NULL, NULL); zassert_true(new_sock >= 0, ""); k_msleep(10); @@ -208,47 +208,47 @@ ZTEST(net_socket_poll, test_pollout_tcp) /* POLLOUT should be reported after connecting */ memset(pollout, 0, sizeof(pollout)); pollout[0].fd = c_sock; - pollout[0].events = POLLOUT; + pollout[0].events = ZSOCK_POLLOUT; - res = poll(pollout, ARRAY_SIZE(pollout), 10); + res = zsock_poll(pollout, ARRAY_SIZE(pollout), 10); zassert_equal(res, 1, ""); - zassert_equal(pollout[0].revents, POLLOUT, ""); + zassert_equal(pollout[0].revents, ZSOCK_POLLOUT, ""); /* POLLOUT should not be reported after filling the window */ - res = send(c_sock, buf, sizeof(buf), 0); + res = zsock_send(c_sock, buf, sizeof(buf), 0); zassert_equal(res, sizeof(buf), ""); memset(pollout, 0, sizeof(pollout)); pollout[0].fd = c_sock; - pollout[0].events = POLLOUT; + pollout[0].events = ZSOCK_POLLOUT; - res = poll(pollout, ARRAY_SIZE(pollout), 10); + res = zsock_poll(pollout, ARRAY_SIZE(pollout), 10); zassert_equal(res, 0, "%d", pollout[0].revents); zassert_equal(pollout[0].revents, 0, ""); /* POLLOUT should be reported again after consuming the data server * side. */ - res = recv(new_sock, buf, sizeof(buf), 0); + res = zsock_recv(new_sock, buf, sizeof(buf), 0); zassert_equal(res, sizeof(buf), ""); memset(pollout, 0, sizeof(pollout)); pollout[0].fd = c_sock; - pollout[0].events = POLLOUT; + pollout[0].events = ZSOCK_POLLOUT; /* Wait longer this time to give TCP stack a chance to send ZWP. */ - res = poll(pollout, ARRAY_SIZE(pollout), 500); + res = zsock_poll(pollout, ARRAY_SIZE(pollout), 500); zassert_equal(res, 1, ""); - zassert_equal(pollout[0].revents, POLLOUT, ""); + zassert_equal(pollout[0].revents, ZSOCK_POLLOUT, ""); k_msleep(10); /* Finalize the test */ - res = close(c_sock); + res = zsock_close(c_sock); zassert_equal(res, 0, "close failed"); - res = close(s_sock); + res = zsock_close(s_sock); zassert_equal(res, 0, "close failed"); - res = close(new_sock); + res = zsock_close(new_sock); zassert_equal(res, 0, "close failed"); } diff --git a/tests/net/socket/register/prj.conf b/tests/net/socket/register/prj.conf index d2b3e01b6c0..071de538d68 100644 --- a/tests/net/socket/register/prj.conf +++ b/tests/net/socket/register/prj.conf @@ -12,6 +12,5 @@ CONFIG_NET_IPV6_NBR_CACHE=n CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_NET_MAX_CONTEXTS=10 diff --git a/tests/net/socket/register/src/main.c b/tests/net/socket/register/src/main.c index d329d533fd6..2bc8d515bc1 100644 --- a/tests/net/socket/register/src/main.c +++ b/tests/net/socket/register/src/main.c @@ -245,9 +245,9 @@ ZTEST(net_socket_register, test_create_sockets) for (i = 0; i < ARRAY_SIZE(expected_result); i++, current_test++) { errno = 0; - fd = socket(expected_result[i].test_case.family, - expected_result[i].test_case.type, - expected_result[i].test_case.proto); + fd = zsock_socket(expected_result[i].test_case.family, + expected_result[i].test_case.type, + expected_result[i].test_case.proto); if (errno == EPROTONOSUPPORT) { func_called--; @@ -271,7 +271,7 @@ ZTEST(net_socket_register, test_create_sockets) } if (fd >= 0) { - close(fd); + zsock_close(fd); } } diff --git a/tests/net/socket/reuseaddr_reuseport/prj.conf b/tests/net/socket/reuseaddr_reuseport/prj.conf index f78a1bea312..1501ff0c1d8 100644 --- a/tests/net/socket/reuseaddr_reuseport/prj.conf +++ b/tests/net/socket/reuseaddr_reuseport/prj.conf @@ -11,7 +11,6 @@ CONFIG_NET_IPV6=y CONFIG_NET_UDP=y CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_L2_DUMMY=y CONFIG_NET_IPV6_DAD=n CONFIG_NET_IPV6_MLD=n diff --git a/tests/net/socket/reuseaddr_reuseport/src/main.c b/tests/net/socket/reuseaddr_reuseport/src/main.c index 1ab9be96e9a..c5e6cb4633f 100644 --- a/tests/net/socket/reuseaddr_reuseport/src/main.c +++ b/tests/net/socket/reuseaddr_reuseport/src/main.c @@ -102,14 +102,14 @@ static inline void prepare_sock_udp(sa_family_t family, const char *ip, uint16_t static void test_getsocketopt_reuseaddr(int sock, void *optval, socklen_t *optlen) { - zassert_equal(getsockopt(sock, SOL_SOCKET, SO_REUSEADDR, optval, optlen), + zassert_equal(zsock_getsockopt(sock, SOL_SOCKET, SO_REUSEADDR, optval, optlen), 0, "getsocketopt() failed with error %d", errno); } static void test_setsocketopt_reuseaddr(int sock, void *optval, socklen_t optlen) { - zassert_equal(setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, optval, optlen), + zassert_equal(zsock_setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, optval, optlen), 0, "setsocketopt() failed with error %d", errno); } @@ -123,14 +123,14 @@ static void test_enable_reuseaddr(int sock) static void test_getsocketopt_reuseport(int sock, void *optval, socklen_t *optlen) { - zassert_equal(getsockopt(sock, SOL_SOCKET, SO_REUSEPORT, optval, optlen), + zassert_equal(zsock_getsockopt(sock, SOL_SOCKET, SO_REUSEPORT, optval, optlen), 0, "getsocketopt() failed with error %d", errno); } static void test_setsocketopt_reuseport(int sock, void *optval, socklen_t optlen) { - zassert_equal(setsockopt(sock, SOL_SOCKET, SO_REUSEPORT, optval, optlen), + zassert_equal(zsock_setsockopt(sock, SOL_SOCKET, SO_REUSEPORT, optval, optlen), 0, "setsocketopt() failed with error %d", errno); } @@ -144,14 +144,14 @@ static void test_enable_reuseport(int sock) static void test_bind_success(int sock, const struct sockaddr *addr, socklen_t addrlen) { - zassert_equal(bind(sock, addr, addrlen), + zassert_equal(zsock_bind(sock, addr, addrlen), 0, "bind() failed with error %d", errno); } static void test_bind_fail(int sock, const struct sockaddr *addr, socklen_t addrlen) { - zassert_equal(bind(sock, addr, addrlen), + zassert_equal(zsock_bind(sock, addr, addrlen), -1, "bind() succeeded incorrectly"); @@ -160,14 +160,14 @@ static void test_bind_fail(int sock, const struct sockaddr *addr, socklen_t addr static void test_listen(int sock) { - zassert_equal(listen(sock, 0), + zassert_equal(zsock_listen(sock, 0), 0, "listen() failed with error %d", errno); } static void test_connect_success(int sock, const struct sockaddr *addr, socklen_t addrlen) { - zassert_equal(connect(sock, addr, addrlen), + zassert_equal(zsock_connect(sock, addr, addrlen), 0, "connect() failed with error %d", errno); @@ -179,7 +179,7 @@ static void test_connect_success(int sock, const struct sockaddr *addr, socklen_ static void test_connect_fail(int sock, const struct sockaddr *addr, socklen_t addrlen) { - zassert_equal(connect(sock, addr, addrlen), + zassert_equal(zsock_connect(sock, addr, addrlen), -1, "connect() succeeded incorrectly"); @@ -188,7 +188,7 @@ static void test_connect_fail(int sock, const struct sockaddr *addr, socklen_t a static int test_accept(int sock, struct sockaddr *addr, socklen_t *addrlen) { - int new_sock = accept(sock, addr, addrlen); + int new_sock = zsock_accept(sock, addr, addrlen); zassert_not_equal(new_sock, -1, "accept() failed with error %d", errno); @@ -198,7 +198,7 @@ static int test_accept(int sock, struct sockaddr *addr, socklen_t *addrlen) static void test_sendto(int sock, const void *buf, size_t len, int flags, const struct sockaddr *dest_addr, socklen_t addrlen) { - zassert_equal(sendto(sock, buf, len, flags, dest_addr, addrlen), + zassert_equal(zsock_sendto(sock, buf, len, flags, dest_addr, addrlen), len, "sendto failed with error %d", errno); } @@ -206,7 +206,7 @@ static void test_sendto(int sock, const void *buf, size_t len, int flags, static void test_recvfrom_success(int sock, void *buf, size_t max_len, int flags, struct sockaddr *src_addr, socklen_t *addrlen) { - zassert_equal(recvfrom(sock, buf, max_len, flags, src_addr, addrlen), + zassert_equal(zsock_recvfrom(sock, buf, max_len, flags, src_addr, addrlen), max_len, "recvfrom failed with error %d", errno); } @@ -214,7 +214,7 @@ static void test_recvfrom_success(int sock, void *buf, size_t max_len, int flags static void test_recvfrom_fail(int sock, void *buf, size_t max_len, int flags, struct sockaddr *src_addr, socklen_t *addrlen) { - zassert_equal(recvfrom(sock, buf, max_len, flags, src_addr, addrlen), + zassert_equal(zsock_recvfrom(sock, buf, max_len, flags, src_addr, addrlen), -1, "recvfrom succeeded incorrectly"); @@ -223,18 +223,18 @@ static void test_recvfrom_fail(int sock, void *buf, size_t max_len, int flags, static void test_recv_success(int sock, void *buf, size_t max_len, int flags) { - zassert_equal(recv(sock, buf, max_len, flags), + zassert_equal(zsock_recv(sock, buf, max_len, flags), max_len, "recv failed with error %d", errno); } static void test_recv_fail(int sock, void *buf, size_t max_len, int flags) { - zassert_equal(recv(sock, buf, max_len, flags), + zassert_equal(zsock_recv(sock, buf, max_len, flags), -1, "recvfrom succeeded incorrectly"); - zassert_equal(errno, EAGAIN, "recvfrom() returned unexpected errno (%d)", errno); + zassert_equal(errno, EAGAIN, "recv() returned unexpected errno (%d)", errno); } ZTEST_USER(socket_reuseaddr_test_suite, test_enable_disable) @@ -275,7 +275,7 @@ ZTEST_USER(socket_reuseaddr_test_suite, test_enable_disable) test_getsocketopt_reuseaddr(server_sock, (void *)&value, &value_size); zassert_equal(value, (int) true, "SO_REUSEADDR not correctly set, returned %d", value); - close(server_sock); + zsock_close(server_sock); } @@ -310,8 +310,8 @@ static void test_reuseaddr_unspecified_specified_common(sa_family_t family, test_bind_fail(server_sock2, &bind_addr2, sizeof(bind_addr2)); } - close(server_sock1); - close(server_sock2); + zsock_close(server_sock1); + zsock_close(server_sock2); } ZTEST_USER(socket_reuseaddr_test_suite, test_ipv4_first_unspecified) @@ -389,8 +389,8 @@ static void test_reuseaddr_tcp_listening_common(sa_family_t family, /* Try to bind the second socket, should fail */ test_bind_fail(server_sock2, (struct sockaddr *) &bind_addr2, sizeof(bind_addr2)); - close(server_sock1); - close(server_sock2); + zsock_close(server_sock1); + zsock_close(server_sock2); } ZTEST_USER(socket_reuseaddr_test_suite, test_ipv4_tcp_unspecified_listening) @@ -452,10 +452,10 @@ static void test_reuseaddr_tcp_tcp_time_wait_common(sa_family_t family, accept_sock = test_accept(server_sock, &accept_addr, &accept_addrlen); /* Close the server socket */ - close(server_sock); + zsock_close(server_sock); /* Close the accepted socket */ - close(accept_sock); + zsock_close(accept_sock); /* Wait a short time for the accept socket to enter TIME_WAIT state*/ k_msleep(50); @@ -472,8 +472,8 @@ static void test_reuseaddr_tcp_tcp_time_wait_common(sa_family_t family, /* Try to bind the new server socket again, should work now */ test_bind_success(server_sock, (struct sockaddr *) &bind_addr, sizeof(bind_addr)); - close(client_sock); - close(server_sock); + zsock_close(client_sock); + zsock_close(server_sock); /* Connection is in TIME_WAIT state, context will be released * after K_MSEC(CONFIG_NET_TCP_TIME_WAIT_DELAY), so wait for it. @@ -552,7 +552,7 @@ ZTEST_USER(socket_reuseport_test_suite, test_enable_disable) test_getsocketopt_reuseport(server_sock, (void *)&value, &value_size); zassert_equal(value, (int) true, "SO_REUSEPORT not correctly set, returned %d", value); - close(server_sock); + zsock_close(server_sock); } @@ -592,8 +592,8 @@ static void test_reuseport_unspecified_specified_common(sa_family_t family, test_bind_fail(server_sock2, &bind_addr2, sizeof(bind_addr2)); } - close(server_sock1); - close(server_sock2); + zsock_close(server_sock1); + zsock_close(server_sock2); } ZTEST_USER(socket_reuseport_test_suite, test_ipv4_both_unspecified_bad) @@ -772,12 +772,12 @@ static void test_reuseport_udp_server_client_common(sa_family_t family, /* Receive data from the client */ rx_buf = 0; - test_recvfrom_success(server_sock, &rx_buf, sizeof(rx_buf), MSG_DONTWAIT, + test_recvfrom_success(server_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT, &accept_addr, &accept_addr_len); zassert_equal(rx_buf, tx_buf, "wrong data"); /* Create a more specific socket to have a direct connection to the new client */ - accept_sock = socket(family, SOCK_DGRAM, IPPROTO_UDP); + accept_sock = zsock_socket(family, SOCK_DGRAM, IPPROTO_UDP); zassert_true(accept_sock >= 0, "socket open failed"); /* Make sure we can bind to the address:port */ @@ -809,24 +809,24 @@ static void test_reuseport_udp_server_client_common(sa_family_t family, if (setup == BOTH_SET) { /* We should receive data on the new specific socket, not on the general one */ rx_buf = 0; - test_recvfrom_fail(server_sock, &rx_buf, sizeof(rx_buf), MSG_DONTWAIT, + test_recvfrom_fail(server_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT, &accept_addr, &accept_addr_len); rx_buf = 0; - test_recv_success(accept_sock, &rx_buf, sizeof(rx_buf), MSG_DONTWAIT); + test_recv_success(accept_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); } else { /* We should receive data on the general server socket */ rx_buf = 0; - test_recvfrom_success(server_sock, &rx_buf, sizeof(rx_buf), MSG_DONTWAIT, + test_recvfrom_success(server_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT, &accept_addr, &accept_addr_len); rx_buf = 0; - test_recv_fail(accept_sock, &rx_buf, sizeof(rx_buf), MSG_DONTWAIT); + test_recv_fail(accept_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); } - close(accept_sock); - close(client_sock); - close(server_sock); + zsock_close(accept_sock); + zsock_close(client_sock); + zsock_close(server_sock); } ZTEST_USER(socket_reuseport_test_suite, test_ipv4_udp_bad_both_not_set) @@ -931,10 +931,10 @@ static void test_reuseport_tcp_identical_clients_common(sa_family_t family, /* Connect the second client, should fail */ test_connect_fail(client_sock2, (struct sockaddr *)&connect_addr, sizeof(connect_addr)); - close(accept_sock); - close(client_sock1); - close(client_sock2); - close(server_sock); + zsock_close(accept_sock); + zsock_close(client_sock1); + zsock_close(client_sock2); + zsock_close(server_sock); /* Connection is in TIME_WAIT state, context will be released * after K_MSEC(CONFIG_NET_TCP_TIME_WAIT_DELAY), so wait for it. diff --git a/tests/net/socket/select/prj.conf b/tests/net/socket/select/prj.conf index cd642566971..89918315d11 100644 --- a/tests/net/socket/select/prj.conf +++ b/tests/net/socket/select/prj.conf @@ -9,7 +9,6 @@ CONFIG_NET_LOOPBACK=y CONFIG_NET_IPV4=n CONFIG_NET_IPV6=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y # Defines fd_set size CONFIG_POSIX_MAX_FDS=33 diff --git a/tests/net/socket/select/src/main.c b/tests/net/socket/select/src/main.c index 1648cfca5a6..aab52167c31 100644 --- a/tests/net/socket/select/src/main.c +++ b/tests/net/socket/select/src/main.c @@ -32,35 +32,35 @@ LOG_MODULE_REGISTER(net_test, CONFIG_NET_SOCKETS_LOG_LEVEL); ZTEST_USER(net_socket_select, test_fd_set) { - fd_set set; + zsock_fd_set set; /* Relies on specific value of CONFIG_POSIX_MAX_FDS in prj.conf */ zassert_equal(sizeof(set.bitset), sizeof(uint32_t) * 2, ""); - FD_ZERO(&set); + ZSOCK_FD_ZERO(&set); zassert_equal(set.bitset[0], 0, ""); zassert_equal(set.bitset[1], 0, ""); - zassert_false(FD_ISSET(0, &set), ""); + zassert_false(ZSOCK_FD_ISSET(0, &set), ""); - FD_SET(0, &set); - zassert_true(FD_ISSET(0, &set), ""); + ZSOCK_FD_SET(0, &set); + zassert_true(ZSOCK_FD_ISSET(0, &set), ""); - FD_CLR(0, &set); - zassert_false(FD_ISSET(0, &set), ""); + ZSOCK_FD_CLR(0, &set); + zassert_false(ZSOCK_FD_ISSET(0, &set), ""); - FD_SET(0, &set); + ZSOCK_FD_SET(0, &set); zassert_equal(set.bitset[0], 0x00000001, ""); zassert_equal(set.bitset[1], 0, ""); - FD_SET(31, &set); + ZSOCK_FD_SET(31, &set); zassert_equal(set.bitset[0], 0x80000001, ""); zassert_equal(set.bitset[1], 0, ""); - FD_SET(33, &set); + ZSOCK_FD_SET(33, &set); zassert_equal(set.bitset[0], 0x80000001, ""); zassert_equal(set.bitset[1], 0x00000002, ""); - FD_ZERO(&set); + ZSOCK_FD_ZERO(&set); zassert_equal(set.bitset[0], 0, ""); zassert_equal(set.bitset[1], 0, ""); } @@ -72,7 +72,7 @@ ZTEST_USER(net_socket_select, test_select) int s_sock; struct sockaddr_in6 c_addr; struct sockaddr_in6 s_addr; - fd_set readfds; + zsock_fd_set readfds; uint32_t tstamp; ssize_t len; char buf[10]; @@ -81,20 +81,20 @@ ZTEST_USER(net_socket_select, test_select) prepare_sock_udp_v6(MY_IPV6_ADDR, CLIENT_PORT, &c_sock, &c_addr); prepare_sock_udp_v6(MY_IPV6_ADDR, SERVER_PORT, &s_sock, &s_addr); - res = bind(s_sock, (struct sockaddr *)&s_addr, sizeof(s_addr)); + res = zsock_bind(s_sock, (struct sockaddr *)&s_addr, sizeof(s_addr)); zassert_equal(res, 0, "bind failed"); - res = connect(c_sock, (struct sockaddr *)&s_addr, sizeof(s_addr)); + res = zsock_connect(c_sock, (struct sockaddr *)&s_addr, sizeof(s_addr)); zassert_equal(res, 0, "connect failed"); - FD_ZERO(&readfds); - FD_SET(c_sock, &readfds); - FD_SET(s_sock, &readfds); + ZSOCK_FD_ZERO(&readfds); + ZSOCK_FD_SET(c_sock, &readfds); + ZSOCK_FD_SET(s_sock, &readfds); /* Poll non-ready fd's with timeout of 0 */ tval.tv_sec = tval.tv_usec = 0; tstamp = k_uptime_get_32(); - res = select(s_sock + 1, &readfds, NULL, NULL, &tval); + res = zsock_select(s_sock + 1, &readfds, NULL, NULL, &tval); tstamp = k_uptime_get_32() - tstamp; /* Even though we expect select to be non-blocking, scheduler may * preempt the thread. That's why we add FUZZ to the expected @@ -103,67 +103,67 @@ ZTEST_USER(net_socket_select, test_select) zassert_true(tstamp <= FUZZ, ""); zassert_equal(res, 0, ""); - zassert_false(FD_ISSET(c_sock, &readfds), ""); - zassert_false(FD_ISSET(s_sock, &readfds), ""); + zassert_false(ZSOCK_FD_ISSET(c_sock, &readfds), ""); + zassert_false(ZSOCK_FD_ISSET(s_sock, &readfds), ""); /* Poll non-ready fd's with timeout of 10ms */ - FD_SET(c_sock, &readfds); - FD_SET(s_sock, &readfds); + ZSOCK_FD_SET(c_sock, &readfds); + ZSOCK_FD_SET(s_sock, &readfds); tval.tv_sec = 0; tval.tv_usec = TIMEOUT_MS * 1000; tstamp = k_uptime_get_32(); - res = select(s_sock + 1, &readfds, NULL, NULL, &tval); + res = zsock_select(s_sock + 1, &readfds, NULL, NULL, &tval); tstamp = k_uptime_get_32() - tstamp; zassert_true(tstamp >= TIMEOUT_MS && tstamp <= TIMEOUT_MS + FUZZ, ""); zassert_equal(res, 0, ""); /* Send pkt for s_sock and poll with timeout of 10ms */ - len = send(c_sock, BUF_AND_SIZE(TEST_STR_SMALL), 0); + len = zsock_send(c_sock, BUF_AND_SIZE(TEST_STR_SMALL), 0); zassert_equal(len, STRLEN(TEST_STR_SMALL), "invalid send len"); - FD_SET(c_sock, &readfds); - FD_SET(s_sock, &readfds); + ZSOCK_FD_SET(c_sock, &readfds); + ZSOCK_FD_SET(s_sock, &readfds); tval.tv_sec = 0; tval.tv_usec = TIMEOUT_MS * 1000; tstamp = k_uptime_get_32(); - res = select(s_sock + 1, &readfds, NULL, NULL, &tval); + res = zsock_select(s_sock + 1, &readfds, NULL, NULL, &tval); tstamp = k_uptime_get_32() - tstamp; zassert_true(tstamp <= FUZZ, ""); zassert_equal(res, 1, ""); - zassert_false(FD_ISSET(c_sock, &readfds), ""); - zassert_true(FD_ISSET(s_sock, &readfds), ""); + zassert_false(ZSOCK_FD_ISSET(c_sock, &readfds), ""); + zassert_true(ZSOCK_FD_ISSET(s_sock, &readfds), ""); /* Recv pkt from s_sock and ensure no poll events happen */ - len = recv(s_sock, BUF_AND_SIZE(buf), 0); + len = zsock_recv(s_sock, BUF_AND_SIZE(buf), 0); zassert_equal(len, STRLEN(TEST_STR_SMALL), "invalid recv len"); - FD_SET(c_sock, &readfds); - FD_SET(s_sock, &readfds); + ZSOCK_FD_SET(c_sock, &readfds); + ZSOCK_FD_SET(s_sock, &readfds); tval.tv_sec = tval.tv_usec = 0; tstamp = k_uptime_get_32(); - res = select(s_sock + 1, &readfds, NULL, NULL, &tval); + res = zsock_select(s_sock + 1, &readfds, NULL, NULL, &tval); zassert_true(k_uptime_get_32() - tstamp <= FUZZ, ""); zassert_equal(res, 0, ""); - zassert_false(FD_ISSET(s_sock, &readfds), ""); + zassert_false(ZSOCK_FD_ISSET(s_sock, &readfds), ""); /* Close one socket and ensure POLLNVAL happens */ - res = close(c_sock); + res = zsock_close(c_sock); zassert_equal(res, 0, "close failed"); - FD_SET(c_sock, &readfds); - FD_SET(s_sock, &readfds); + ZSOCK_FD_SET(c_sock, &readfds); + ZSOCK_FD_SET(s_sock, &readfds); tval.tv_sec = tval.tv_usec = 0; tstamp = k_uptime_get_32(); - res = select(s_sock + 1, &readfds, NULL, NULL, &tval); + res = zsock_select(s_sock + 1, &readfds, NULL, NULL, &tval); zassert_true(k_uptime_get_32() - tstamp <= FUZZ, ""); zassert_true(res < 0, ""); zassert_equal(errno, EBADF, ""); - res = close(s_sock); + res = zsock_close(s_sock); zassert_equal(res, 0, "close failed"); } diff --git a/tests/net/socket/socket_helpers.h b/tests/net/socket/socket_helpers.h index 9cecccc20b6..7ac4e0f8edd 100644 --- a/tests/net/socket/socket_helpers.h +++ b/tests/net/socket/socket_helpers.h @@ -22,14 +22,14 @@ static inline int prepare_listen_sock_udp_v4(struct sockaddr_in *addr) zassert_not_null(addr, "null sockaddr"); - ret = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + ret = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); zassert_true(ret >= 0, "socket open failed"); sock = ret; zassert_equal(addr->sin_family, AF_INET, "Invalid family"); - ret = bind(sock, (struct sockaddr *)addr, sizeof(*addr)); + ret = zsock_bind(sock, (struct sockaddr *)addr, sizeof(*addr)); zassert_equal(ret, 0, "bind failed (%d/%d)", ret, errno); return sock; @@ -41,14 +41,14 @@ static inline int prepare_listen_sock_udp_v6(struct sockaddr_in6 *addr) zassert_not_null(addr, "null sockaddr"); - ret = socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP); + ret = zsock_socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP); zassert_true(ret >= 0, "socket open failed"); sock = ret; zassert_equal(addr->sin6_family, AF_INET6, "Invalid family"); - ret = bind(sock, (struct sockaddr *)addr, sizeof(*addr)); + ret = zsock_bind(sock, (struct sockaddr *)addr, sizeof(*addr)); zassert_equal(ret, 0, "bind failed (%d/%d)", ret, errno); return sock; @@ -63,12 +63,12 @@ static inline void prepare_sock_udp_v4(const char *addr, uint16_t port, zassert_not_null(sock, "null sock"); zassert_not_null(sockaddr, "null sockaddr"); - *sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + *sock = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); zassert_true(*sock >= 0, "socket open failed"); sockaddr->sin_family = AF_INET; sockaddr->sin_port = htons(port); - rv = inet_pton(AF_INET, addr, &sockaddr->sin_addr); + rv = zsock_inet_pton(AF_INET, addr, &sockaddr->sin_addr); zassert_equal(rv, 1, "inet_pton failed"); } diff --git a/tests/net/socket/socketpair/prj.conf b/tests/net/socket/socketpair/prj.conf index 9789809556c..177d9c991c4 100644 --- a/tests/net/socket/socketpair/prj.conf +++ b/tests/net/socket/socketpair/prj.conf @@ -7,7 +7,6 @@ CONFIG_NET_IPV4=y CONFIG_NET_SOCKETS=y CONFIG_NET_SOCKETPAIR=y CONFIG_NET_SOCKETPAIR_BUFFER_SIZE=64 -CONFIG_NET_SOCKETS_POSIX_NAMES=y # Network driver config CONFIG_TEST_RANDOM_GENERATOR=y diff --git a/tests/net/socket/socketpair/src/_main.c b/tests/net/socket/socketpair/src/_main.c index 64c68fb348e..ff8027b0982 100644 --- a/tests/net/socket/socketpair/src/_main.c +++ b/tests/net/socket/socketpair/src/_main.c @@ -27,7 +27,7 @@ static void before(void *arg) fixture->sv[i] = -1; } } - zassert_ok(socketpair(AF_UNIX, SOCK_STREAM, 0, fixture->sv)); + zassert_ok(zsock_socketpair(AF_UNIX, SOCK_STREAM, 0, fixture->sv)); } static void after(void *arg) @@ -36,7 +36,7 @@ static void after(void *arg) for (int i = 0; i < 2; ++i) { if (fixture->sv[i] >= 0) { - zassert_ok(close(fixture->sv[i])); + zassert_ok(zsock_close(fixture->sv[i])); fixture->sv[i] = -1; } } diff --git a/tests/net/socket/socketpair/src/_main.h b/tests/net/socket/socketpair/src/_main.h index 2c77a0fb87e..f6df1a267f9 100644 --- a/tests/net/socket/socketpair/src/_main.h +++ b/tests/net/socket/socketpair/src/_main.h @@ -11,8 +11,8 @@ #include #include -#include #include +#include #include #include diff --git a/tests/net/socket/socketpair/src/block.c b/tests/net/socket/socketpair/src/block.c index d75cf0a9dad..b8f4a61dcfe 100644 --- a/tests/net/socket/socketpair/src/block.c +++ b/tests/net/socket/socketpair/src/block.c @@ -45,9 +45,9 @@ static void work_handler(struct k_work *w) LOG_DBG("%sing 1 byte %s fd %d", ctx.write ? "read" : "writ", ctx.write ? "from" : "to", ctx.fd); if (ctx.write) { - res = recv(ctx.fd, &c, 1, 0); + res = zsock_recv(ctx.fd, &c, 1, 0); } else { - res = send(ctx.fd, "x", 1, 0); + res = zsock_send(ctx.fd, "x", 1, 0); } if (-1 == res || 1 != res) { LOG_DBG("%s() failed: %d", ctx.write ? "recv" : "send", errno); @@ -77,7 +77,7 @@ ZTEST_F(net_socketpair, test_write_block) for (ctx.m = 0; atomic_get(&ctx.m) < CONFIG_NET_SOCKETPAIR_BUFFER_SIZE;) { - res = send(fixture->sv[i], "x", 1, 0); + res = zsock_send(fixture->sv[i], "x", 1, 0); zassert_not_equal(res, -1, "send() failed: %d", errno); zassert_equal(res, 1, "wrote %d bytes instead of 1", res); @@ -88,7 +88,7 @@ ZTEST_F(net_socketpair, test_write_block) /* try to write one more byte */ LOG_DBG("writing to fd %d", fixture->sv[i]); - res = send(fixture->sv[i], "x", 1, 0); + res = zsock_send(fixture->sv[i], "x", 1, 0); zassert_not_equal(res, -1, "send() failed: %d", errno); zassert_equal(res, 1, "wrote %d bytes instead of 1", res); @@ -117,7 +117,7 @@ ZTEST_F(net_socketpair, test_read_block) /* try to read one byte */ LOG_DBG("reading from fd %d", fixture->sv[i]); x = '\0'; - res = recv(fixture->sv[i], &x, 1, 0); + res = zsock_recv(fixture->sv[i], &x, 1, 0); zassert_not_equal(res, -1, "recv() failed: %d", errno); zassert_equal(res, 1, "read %d bytes instead of 1", res); diff --git a/tests/net/socket/socketpair/src/closed_ends.c b/tests/net/socket/socketpair/src/closed_ends.c index 33727b56dd9..8c4241f0f23 100644 --- a/tests/net/socket/socketpair/src/closed_ends.c +++ b/tests/net/socket/socketpair/src/closed_ends.c @@ -10,20 +10,20 @@ ZTEST_USER_F(net_socketpair, test_close_one_end_and_write_to_the_other) int res; for (size_t i = 0; i < 2; ++i) { - res = close(fixture->sv[i]); + res = zsock_close(fixture->sv[i]); zassert_equal(res, 0, "close(fixture->sv[%u]) failed: %d", i, errno); fixture->sv[i] = -1; - res = send(fixture->sv[(!i) & 1], "x", 1, 0); + res = zsock_send(fixture->sv[(!i) & 1], "x", 1, 0); zassert_equal(res, -1, "expected send() to fail"); zassert_equal(res, -1, "errno: expected: EPIPE actual: %d", errno); - res = close(fixture->sv[(!i) & 1]); + res = zsock_close(fixture->sv[(!i) & 1]); zassert_equal(res, 0, "close(fixture->sv[%u]) failed: %d", i, errno); fixture->sv[(!i) & 1] = -1; - res = socketpair(AF_UNIX, SOCK_STREAM, 0, fixture->sv); + res = zsock_socketpair(AF_UNIX, SOCK_STREAM, 0, fixture->sv); zassert_equal(res, 0, "socketpair() failed: %d", errno); } } @@ -39,28 +39,28 @@ ZTEST_USER_F(net_socketpair, test_close_one_end_and_read_from_the_other) * reading is possible from the other end still and that data * is not lost. */ - res = send(fixture->sv[i], "xx", 2, 0); + res = zsock_send(fixture->sv[i], "xx", 2, 0); zassert_not_equal(res, -1, "send() failed: %d", errno); zassert_equal(res, 2, "write() failed to write 2 bytes"); - res = close(fixture->sv[i]); + res = zsock_close(fixture->sv[i]); zassert_equal(res, 0, "close(fixture->sv[%u]) failed: %d", i, errno); fixture->sv[i] = -1; memset(xx, 0, sizeof(xx)); - res = recv(fixture->sv[(!i) & 1], xx, sizeof(xx), 0); + res = zsock_recv(fixture->sv[(!i) & 1], xx, sizeof(xx), 0); zassert_not_equal(res, -1, "read() failed: %d", errno); zassert_equal(res, 2, "expected to read 2 bytes but read %d", res); - res = recv(fixture->sv[(!i) & 1], xx, sizeof(xx), 0); + res = zsock_recv(fixture->sv[(!i) & 1], xx, sizeof(xx), 0); zassert_equal(res, 0, "expected read() to succeed but read 0 bytes"); - res = close(fixture->sv[(!i) & 1]); + res = zsock_close(fixture->sv[(!i) & 1]); zassert_equal(res, 0, "close(fixture->sv[%u]) failed: %d", i, errno); fixture->sv[(!i) & 1] = -1; - res = socketpair(AF_UNIX, SOCK_STREAM, 0, fixture->sv); + res = zsock_socketpair(AF_UNIX, SOCK_STREAM, 0, fixture->sv); zassert_equal(res, 0, "socketpair() failed: %d", errno); } } diff --git a/tests/net/socket/socketpair/src/expected_failures.c b/tests/net/socket/socketpair/src/expected_failures.c index 6483a259126..d5f722e45bc 100644 --- a/tests/net/socket/socketpair/src/expected_failures.c +++ b/tests/net/socket/socketpair/src/expected_failures.c @@ -12,10 +12,10 @@ ZTEST_USER_F(net_socketpair, test_expected_failures) /* Use invalid values in fields starting from left to right */ - res = socketpair(AF_INET, SOCK_STREAM, 0, fixture->sv); + res = zsock_socketpair(AF_INET, SOCK_STREAM, 0, fixture->sv); if (res != -1) { for (int i = 0; i < 2; ++i) { - zassert_ok(close(fixture->sv[i])); + zassert_ok(zsock_close(fixture->sv[i])); fixture->sv[i] = -1; } } @@ -23,10 +23,10 @@ ZTEST_USER_F(net_socketpair, test_expected_failures) zassert_equal(errno, EAFNOSUPPORT, "errno should be EAFNOSUPPORT with bad address family"); - res = socketpair(AF_UNIX, 42, 0, fixture->sv); + res = zsock_socketpair(AF_UNIX, 42, 0, fixture->sv); if (res != -1) { for (int i = 0; i < 2; ++i) { - zassert_ok(close(fixture->sv[i])); + zassert_ok(zsock_close(fixture->sv[i])); fixture->sv[i] = -1; } } @@ -35,10 +35,10 @@ ZTEST_USER_F(net_socketpair, test_expected_failures) zassert_equal(errno, EPROTOTYPE, "errno should be EPROTOTYPE with bad socket type"); - res = socketpair(AF_UNIX, SOCK_STREAM, IPPROTO_TLS_1_0, fixture->sv); + res = zsock_socketpair(AF_UNIX, SOCK_STREAM, IPPROTO_TLS_1_0, fixture->sv); if (res != -1) { for (int i = 0; i < 2; ++i) { - zassert_ok(close(fixture->sv[i])); + zassert_ok(zsock_close(fixture->sv[i])); fixture->sv[i] = -1; } } @@ -48,10 +48,10 @@ ZTEST_USER_F(net_socketpair, test_expected_failures) "errno should be EPROTONOSUPPORT with bad protocol"); /* This is not a POSIX requirement, but should be safe */ - res = socketpair(AF_UNIX, SOCK_STREAM, 0, NULL); + res = zsock_socketpair(AF_UNIX, SOCK_STREAM, 0, NULL); if (res != -1) { for (int i = 0; i < 2; ++i) { - zassert_ok(close(fixture->sv[i])); + zassert_ok(zsock_close(fixture->sv[i])); fixture->sv[i] = -1; } } diff --git a/tests/net/socket/socketpair/src/fcntl.c b/tests/net/socket/socketpair/src/fcntl.c index d87f18e046a..55d36282700 100644 --- a/tests/net/socket/socketpair/src/fcntl.c +++ b/tests/net/socket/socketpair/src/fcntl.c @@ -11,7 +11,7 @@ ZTEST_USER_F(net_socketpair, test_fcntl) int res; int flags; - res = fcntl(fixture->sv[0], F_GETFL, 0); + res = zsock_fcntl(fixture->sv[0], F_GETFL, 0); zassert_not_equal(res, -1, "fcntl(fixture->sv[0], F_GETFL) failed. errno: %d", errno); @@ -19,11 +19,11 @@ ZTEST_USER_F(net_socketpair, test_fcntl) zassert_equal(res & O_NONBLOCK, 0, "socketpair should block by default"); - res = fcntl(fixture->sv[0], F_SETFL, flags | O_NONBLOCK); + res = zsock_fcntl(fixture->sv[0], F_SETFL, flags | O_NONBLOCK); zassert_not_equal(res, -1, "fcntl(fixture->sv[0], F_SETFL, flags | O_NONBLOCK) failed. errno: %d", errno); - res = fcntl(fixture->sv[0], F_GETFL, 0); + res = zsock_fcntl(fixture->sv[0], F_GETFL, 0); zassert_equal(res ^ flags, O_NONBLOCK, "expected O_NONBLOCK set"); } diff --git a/tests/net/socket/socketpair/src/fionread.c b/tests/net/socket/socketpair/src/fionread.c index 33e8907b498..c3e7e168cd8 100644 --- a/tests/net/socket/socketpair/src/fionread.c +++ b/tests/net/socket/socketpair/src/fionread.c @@ -20,7 +20,7 @@ ZTEST_F(net_socketpair, test_ioctl_fionread) /* both ends should have zero bytes available after being newly created */ for (int i = 0; i < 2; ++i) { avail = 42; - zassert_ok(ioctl(fixture->sv[i], ZFD_IOCTL_FIONREAD, &avail)); + zassert_ok(zsock_ioctl(fixture->sv[i], ZFD_IOCTL_FIONREAD, &avail)); zassert_equal(avail, 0); } @@ -29,14 +29,14 @@ ZTEST_F(net_socketpair, test_ioctl_fionread) int j = (i + 1) % 2; zassert_equal(1, write(fixture->sv[i], "\x42", 1)); - zassert_ok(ioctl(fixture->sv[j], ZFD_IOCTL_FIONREAD, &avail)); + zassert_ok(zsock_ioctl(fixture->sv[j], ZFD_IOCTL_FIONREAD, &avail)); zassert_equal(avail, 1); } /* read the other end, ensure availability is zero again */ for (int i = 0; i < 2; ++i) { zassert_equal(1, read(fixture->sv[i], &byte, 1)); - zassert_ok(ioctl(fixture->sv[i], ZFD_IOCTL_FIONREAD, &avail)); + zassert_ok(zsock_ioctl(fixture->sv[i], ZFD_IOCTL_FIONREAD, &avail)); zassert_equal(avail, 0); } } diff --git a/tests/net/socket/socketpair/src/happy_path.c b/tests/net/socket/socketpair/src/happy_path.c index 6e84c358b3b..ebecff04b2b 100644 --- a/tests/net/socket/socketpair/src/happy_path.c +++ b/tests/net/socket/socketpair/src/happy_path.c @@ -30,7 +30,7 @@ static void happy_path( * Test with send() / recv() */ - res = send(fixture->sv[i], expected_msg, expected_msg_len, 0); + res = zsock_send(fixture->sv[i], expected_msg, expected_msg_len, 0); zassert_not_equal(res, -1, "send() failed: %d", errno); actual_msg_len = res; @@ -39,7 +39,7 @@ static void happy_path( memset(actual_msg, 0, sizeof(actual_msg)); - res = recv(fixture->sv[(!i) & 1], actual_msg, sizeof(actual_msg), 0); + res = zsock_recv(fixture->sv[(!i) & 1], actual_msg, sizeof(actual_msg), 0); zassert_not_equal(res, -1, "recv() failed: %d", errno); actual_msg_len = res; @@ -54,7 +54,7 @@ static void happy_path( * Test with sendto(2) / recvfrom(2) */ - res = sendto(fixture->sv[i], expected_msg, expected_msg_len, 0, NULL, 0); + res = zsock_sendto(fixture->sv[i], expected_msg, expected_msg_len, 0, NULL, 0); zassert_not_equal(res, -1, "sendto() failed: %d", errno); actual_msg_len = res; @@ -64,8 +64,8 @@ static void happy_path( memset(actual_msg, 0, sizeof(actual_msg)); len = 0; - res = recvfrom(fixture->sv[(!i) & 1], actual_msg, sizeof(actual_msg), 0, - NULL, &len); + res = zsock_recvfrom(fixture->sv[(!i) & 1], actual_msg, sizeof(actual_msg), 0, + NULL, &len); zassert_true(res >= 0, "recvfrom() failed: %d", errno); actual_msg_len = res; zassert_equal(actual_msg_len, expected_msg_len, @@ -85,14 +85,14 @@ static void happy_path( iovec.iov_base = (void *)expected_msg; iovec.iov_len = expected_msg_len; - res = sendmsg(fixture->sv[i], &msghdr, 0); + res = zsock_sendmsg(fixture->sv[i], &msghdr, 0); zassert_not_equal(res, -1, "sendmsg() failed: %d", errno); actual_msg_len = res; zassert_equal(actual_msg_len, expected_msg_len, "did not sendmsg entire message"); - res = recv(fixture->sv[(!i) & 1], actual_msg, sizeof(actual_msg), 0); + res = zsock_recv(fixture->sv[(!i) & 1], actual_msg, sizeof(actual_msg), 0); zassert_not_equal(res, -1, "recv() failed: %d", errno); actual_msg_len = res; diff --git a/tests/net/socket/socketpair/src/nonblock.c b/tests/net/socket/socketpair/src/nonblock.c index 11aeb6d8f66..2544855f72b 100644 --- a/tests/net/socket/socketpair/src/nonblock.c +++ b/tests/net/socket/socketpair/src/nonblock.c @@ -14,19 +14,19 @@ ZTEST_USER_F(net_socketpair, test_write_nonblock) /* first, fill up the buffer */ for (size_t k = 0; k < CONFIG_NET_SOCKETPAIR_BUFFER_SIZE; ++k) { - res = send(fixture->sv[i], "x", 1, 0); + res = zsock_send(fixture->sv[i], "x", 1, 0); zassert_equal(res, 1, "send() failed: %d", errno); } /* then set the O_NONBLOCK flag */ - res = fcntl(fixture->sv[i], F_GETFL, 0); + res = zsock_fcntl(fixture->sv[i], F_GETFL, 0); zassert_not_equal(res, -1, "fcntl() failed: %d", i, errno); - res = fcntl(fixture->sv[i], F_SETFL, res | O_NONBLOCK); + res = zsock_fcntl(fixture->sv[i], F_SETFL, res | O_NONBLOCK); zassert_not_equal(res, -1, "fcntl() failed: %d", i, errno); /* then, try to write one more byte */ - res = send(fixture->sv[i], "x", 1, 0); + res = zsock_send(fixture->sv[i], "x", 1, 0); zassert_equal(res, -1, "expected send to fail"); zassert_equal(errno, EAGAIN, "errno: expected: EAGAIN " "actual: %d", errno); @@ -40,14 +40,14 @@ ZTEST_USER_F(net_socketpair, test_read_nonblock) for (size_t i = 0; i < 2; ++i) { /* set the O_NONBLOCK flag */ - res = fcntl(fixture->sv[i], F_GETFL, 0); + res = zsock_fcntl(fixture->sv[i], F_GETFL, 0); zassert_not_equal(res, -1, "fcntl() failed: %d", i, errno); - res = fcntl(fixture->sv[i], F_SETFL, res | O_NONBLOCK); + res = zsock_fcntl(fixture->sv[i], F_SETFL, res | O_NONBLOCK); zassert_not_equal(res, -1, "fcntl() failed: %d", i, errno); /* then, try to read one byte */ - res = recv(fixture->sv[i], &c, 1, 0); + res = zsock_recv(fixture->sv[i], &c, 1, 0); zassert_equal(res, -1, "expected recv() to fail"); zassert_equal(errno, EAGAIN, "errno: expected: EAGAIN " "actual: %d", errno); diff --git a/tests/net/socket/socketpair/src/poll.c b/tests/net/socket/socketpair/src/poll.c index ed6c837a742..169063f742a 100644 --- a/tests/net/socket/socketpair/src/poll.c +++ b/tests/net/socket/socketpair/src/poll.c @@ -24,23 +24,23 @@ static ZTEST_BMEM struct k_work work; static void test_socketpair_poll_timeout_common(struct net_socketpair_fixture *fixture) { int res; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[0]; - fds[0].events |= POLLIN; - res = poll(fds, 1, 1); + fds[0].events |= ZSOCK_POLLIN; + res = zsock_poll(fds, 1, 1); zassert_equal(res, 0, "poll: expected: 0 actual: %d", res); for (size_t i = 0; i < CONFIG_NET_SOCKETPAIR_BUFFER_SIZE; ++i) { - res = send(fixture->sv[0], "x", 1, 0); + res = zsock_send(fixture->sv[0], "x", 1, 0); zassert_equal(res, 1, "send() failed: %d", res); } memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[0]; - fds[0].events |= POLLOUT; - res = poll(fds, 1, 1); + fds[0].events |= ZSOCK_POLLOUT; + res = zsock_poll(fds, 1, 1); zassert_equal(res, 0, "poll: expected: 0 actual: %d", res); } @@ -54,15 +54,15 @@ ZTEST_USER_F(net_socketpair, test_poll_timeout_nonblocking) { int res; - res = fcntl(fixture->sv[0], F_GETFL, 0); + res = zsock_fcntl(fixture->sv[0], F_GETFL, 0); zassert_not_equal(res, -1, "fcntl failed: %d", errno); int flags = res; - res = fcntl(fixture->sv[0], F_SETFL, O_NONBLOCK | flags); + res = zsock_fcntl(fixture->sv[0], F_SETFL, O_NONBLOCK | flags); zassert_not_equal(res, -1, "fcntl failed: %d", errno); - res = fcntl(fixture->sv[1], F_SETFL, O_NONBLOCK | flags); + res = zsock_fcntl(fixture->sv[1], F_SETFL, O_NONBLOCK | flags); zassert_not_equal(res, -1, "fcntl failed: %d", errno); test_socketpair_poll_timeout_common(fixture); @@ -78,7 +78,7 @@ static void close_fun(struct k_work *w) } LOG_DBG("about to close fd %d", *ctx.fd); - close(*ctx.fd); + zsock_close(*ctx.fd); *ctx.fd = -1; } @@ -93,7 +93,7 @@ ZTEST_F(net_socketpair, test_poll_close_remote_end_POLLIN) { int res; char c; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; /* * poll until there are bytes to read. @@ -102,7 +102,7 @@ ZTEST_F(net_socketpair, test_poll_close_remote_end_POLLIN) memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[0]; - fds[0].events |= POLLIN; + fds[0].events |= ZSOCK_POLLIN; memset(&ctx, 0, sizeof(ctx)); ctx.fd = &fixture->sv[1]; @@ -112,35 +112,35 @@ ZTEST_F(net_socketpair, test_poll_close_remote_end_POLLIN) k_work_init(&work, close_fun); k_work_submit(&work); - res = poll(fds, 1, -1); + res = zsock_poll(fds, 1, -1); zassert_equal(res, 1, "poll() failed: %d", res); - zassert_equal(fds[0].revents & POLLIN, POLLIN, "POLLIN not set"); + zassert_equal(fds[0].revents & ZSOCK_POLLIN, ZSOCK_POLLIN, "POLLIN not set"); - res = recv(fixture->sv[0], &c, 1, 0); + res = zsock_recv(fixture->sv[0], &c, 1, 0); zassert_equal(res, 0, "read did not return EOF"); } ZTEST_F(net_socketpair, test_poll_close_remote_end_POLLOUT) { int res; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; /* * Fill up the remote q and then poll until write space is available. * But rather than reading, close the other end of the channel */ - res = socketpair(AF_UNIX, SOCK_STREAM, 0, fixture->sv); + res = zsock_socketpair(AF_UNIX, SOCK_STREAM, 0, fixture->sv); zassert_not_equal(res, -1, "socketpair() failed: %d", errno); for (size_t i = 0; i < CONFIG_NET_SOCKETPAIR_BUFFER_SIZE; ++i) { - res = send(fixture->sv[0], "x", 1, 0); + res = zsock_send(fixture->sv[0], "x", 1, 0); zassert_equal(res, 1, "send failed: %d", res); } memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[0]; - fds[0].events |= POLLOUT; + fds[0].events |= ZSOCK_POLLOUT; memset(&ctx, 0, sizeof(ctx)); ctx.fd = &fixture->sv[1]; @@ -150,11 +150,11 @@ ZTEST_F(net_socketpair, test_poll_close_remote_end_POLLOUT) k_work_init(&work, close_fun); k_work_submit(&work); - res = poll(fds, 1, -1); + res = zsock_poll(fds, 1, -1); zassert_equal(res, 1, "poll() failed: %d", res); - zassert_equal(fds[0].revents & POLLHUP, POLLHUP, "POLLHUP not set"); + zassert_equal(fds[0].revents & ZSOCK_POLLHUP, ZSOCK_POLLHUP, "POLLHUP not set"); - res = send(fixture->sv[0], "x", 1, 0); + res = zsock_send(fixture->sv[0], "x", 1, 0); zassert_equal(res, -1, "send(): expected: -1 actual: %d", res); zassert_equal(errno, EPIPE, "errno: expected: EPIPE actual: %d", errno); } @@ -169,38 +169,38 @@ ZTEST_F(net_socketpair, test_poll_close_remote_end_POLLOUT) ZTEST_USER_F(net_socketpair, test_poll_immediate_data) { int res; - struct pollfd fds[2]; + struct zsock_pollfd fds[2]; memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[0]; - fds[0].events |= POLLOUT; - res = poll(fds, 1, 0); + fds[0].events |= ZSOCK_POLLOUT; + res = zsock_poll(fds, 1, 0); zassert_not_equal(res, -1, "poll() failed: %d", errno); zassert_equal(res, 1, "poll(): expected: 1 actual: %d", res); - zassert_not_equal(fds[0].revents & POLLOUT, 0, "POLLOUT not set"); + zassert_not_equal(fds[0].revents & ZSOCK_POLLOUT, 0, "POLLOUT not set"); - res = send(fixture->sv[0], "x", 1, 0); + res = zsock_send(fixture->sv[0], "x", 1, 0); zassert_not_equal(res, -1, "send() failed: %d", errno); zassert_equal(res, 1, "write(): expected: 1 actual: %d", res); memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[1]; - fds[0].events |= POLLIN; - res = poll(fds, 1, 0); + fds[0].events |= ZSOCK_POLLIN; + res = zsock_poll(fds, 1, 0); zassert_not_equal(res, -1, "poll() failed: %d", errno); zassert_equal(res, 1, "poll(): expected: 1 actual: %d", res); - zassert_not_equal(fds[0].revents & POLLIN, 0, "POLLIN not set"); + zassert_not_equal(fds[0].revents & ZSOCK_POLLIN, 0, "POLLIN not set"); memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[0]; - fds[0].events |= POLLOUT; + fds[0].events |= ZSOCK_POLLOUT; fds[1].fd = fixture->sv[1]; - fds[1].events |= POLLIN; - res = poll(fds, 2, 0); + fds[1].events |= ZSOCK_POLLIN; + res = zsock_poll(fds, 2, 0); zassert_not_equal(res, -1, "poll() failed: %d", errno); zassert_equal(res, 2, "poll(): expected: 1 actual: %d", res); - zassert_not_equal(fds[0].revents & POLLOUT, 0, "POLLOUT not set"); - zassert_not_equal(fds[1].revents & POLLIN, 0, "POLLIN not set"); + zassert_not_equal(fds[0].revents & ZSOCK_POLLOUT, 0, "POLLOUT not set"); + zassert_not_equal(fds[1].revents & ZSOCK_POLLIN, 0, "POLLIN not set"); } static void rw_fun(struct k_work *w) @@ -217,7 +217,7 @@ static void rw_fun(struct k_work *w) if (ctx.should_write) { LOG_DBG("about to write 1 byte"); - res = send(*ctx.fd, "x", 1, 0); + res = zsock_send(*ctx.fd, "x", 1, 0); if (-1 == res) { LOG_DBG("send() failed: %d", errno); } else { @@ -225,7 +225,7 @@ static void rw_fun(struct k_work *w) } } else { LOG_DBG("about to read 1 byte"); - res = recv(*ctx.fd, &c, 1, 0); + res = zsock_recv(*ctx.fd, &c, 1, 0); if (-1 == res) { LOG_DBG("recv() failed: %d", errno); } else { @@ -242,11 +242,11 @@ static void rw_fun(struct k_work *w) ZTEST_F(net_socketpair, test_poll_delayed_data) { int res; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[0]; - fds[0].events |= POLLIN; + fds[0].events |= ZSOCK_POLLIN; memset(&ctx, 0, sizeof(ctx)); ctx.fd = &fixture->sv[1]; @@ -257,19 +257,19 @@ ZTEST_F(net_socketpair, test_poll_delayed_data) k_work_init(&work, rw_fun); k_work_submit(&work); - res = poll(fds, 1, 5000); + res = zsock_poll(fds, 1, 5000); zassert_not_equal(res, -1, "poll() failed: %d", errno); zassert_equal(res, 1, "poll(): expected: 1 actual: %d", res); - zassert_not_equal(fds[0].revents & POLLIN, 0, "POLLIN not set"); + zassert_not_equal(fds[0].revents & ZSOCK_POLLIN, 0, "POLLIN not set"); for (size_t i = 0; i < CONFIG_NET_SOCKETPAIR_BUFFER_SIZE; ++i) { - res = send(fixture->sv[0], "x", 1, 0); + res = zsock_send(fixture->sv[0], "x", 1, 0); zassert_equal(res, 1, "send() failed: %d", res); } memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[0]; - fds[0].events |= POLLOUT; + fds[0].events |= ZSOCK_POLLOUT; memset(&ctx, 0, sizeof(ctx)); ctx.fd = &fixture->sv[1]; @@ -280,10 +280,10 @@ ZTEST_F(net_socketpair, test_poll_delayed_data) k_work_init(&work, rw_fun); k_work_submit(&work); - res = poll(fds, 1, 5000); + res = zsock_poll(fds, 1, 5000); zassert_not_equal(res, -1, "poll() failed: %d", errno); zassert_equal(res, 1, "poll(): expected: 1 actual: %d", res); - zassert_not_equal(fds[0].revents & POLLOUT, 0, "POLLOUT was not set"); + zassert_not_equal(fds[0].revents & ZSOCK_POLLOUT, 0, "POLLOUT was not set"); } /* @@ -298,42 +298,42 @@ ZTEST_USER_F(net_socketpair, test_poll_signalling_POLLIN) int res; char c; int64_t timestamp, delta; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[1]; - fds[0].events |= POLLIN; - res = poll(fds, 1, 0); + fds[0].events |= ZSOCK_POLLIN; + res = zsock_poll(fds, 1, 0); zassert_not_equal(res, -1, "poll failed: %d", errno); zassert_equal(res, 0, "poll: expected: 0 actual: %d", res); - zassert_not_equal(fds[0].revents & POLLIN, POLLIN, "POLLIN set"); + zassert_not_equal(fds[0].revents & ZSOCK_POLLIN, ZSOCK_POLLIN, "POLLIN set"); - res = send(fixture->sv[0], "x", 1, 0); + res = zsock_send(fixture->sv[0], "x", 1, 0); zassert_equal(res, 1, "send failed: %d", res); timestamp = k_uptime_get(); memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[1]; - fds[0].events |= POLLIN; - res = poll(fds, 1, 1000); + fds[0].events |= ZSOCK_POLLIN; + res = zsock_poll(fds, 1, 1000); zassert_not_equal(res, -1, "poll failed: %d", errno); zassert_equal(res, 1, "poll: expected: 1 actual: %d", res); - zassert_not_equal(fds[0].revents & POLLIN, 0, "POLLIN not set"); + zassert_not_equal(fds[0].revents & ZSOCK_POLLIN, 0, "POLLIN not set"); delta = k_uptime_delta(×tamp); zassert_true(delta < 100, "poll did not exit immediately"); - res = recv(fixture->sv[1], &c, 1, 0); + res = zsock_recv(fixture->sv[1], &c, 1, 0); zassert_equal(res, 1, "recv failed: %d", res); memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[1]; - fds[0].events |= POLLIN; - res = poll(fds, 1, 0); + fds[0].events |= ZSOCK_POLLIN; + res = zsock_poll(fds, 1, 0); zassert_not_equal(res, -1, "poll failed: %d", errno); zassert_equal(res, 0, "poll: expected: 0 actual: %d", res); - zassert_not_equal(fds[0].revents & POLLIN, POLLIN, "POLLIN set"); + zassert_not_equal(fds[0].revents & ZSOCK_POLLIN, ZSOCK_POLLIN, "POLLIN set"); } /* @@ -348,47 +348,47 @@ ZTEST_USER_F(net_socketpair, test_poll_signalling_POLLOUT) int res; char c; int64_t timestamp, delta; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; timestamp = k_uptime_get(); memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[0]; - fds[0].events |= POLLOUT; - res = poll(fds, 1, 1000); + fds[0].events |= ZSOCK_POLLOUT; + res = zsock_poll(fds, 1, 1000); zassert_not_equal(res, -1, "poll failed: %d", errno); zassert_equal(res, 1, "poll: expected: 1 actual: %d", res); - zassert_not_equal(fds[0].revents & POLLOUT, 0, "POLLOUT not set"); + zassert_not_equal(fds[0].revents & ZSOCK_POLLOUT, 0, "POLLOUT not set"); delta = k_uptime_delta(×tamp); zassert_true(delta < 100, "poll did not exit immediately"); /* Fill up the remote buffer */ for (size_t i = 0; i < CONFIG_NET_SOCKETPAIR_BUFFER_SIZE; ++i) { - res = send(fixture->sv[0], "x", 1, 0); + res = zsock_send(fixture->sv[0], "x", 1, 0); zassert_equal(res, 1, "send() failed: %d", res); } memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[0]; - fds[0].events |= POLLOUT; - res = poll(fds, 1, 0); + fds[0].events |= ZSOCK_POLLOUT; + res = zsock_poll(fds, 1, 0); zassert_not_equal(res, -1, "poll failed: %d", errno); zassert_equal(res, 0, "poll: expected: 0 actual: %d", res); - zassert_not_equal(fds[0].revents & POLLOUT, POLLOUT, "POLLOUT is set"); + zassert_not_equal(fds[0].revents & ZSOCK_POLLOUT, ZSOCK_POLLOUT, "POLLOUT is set"); - res = recv(fixture->sv[1], &c, 1, 0); + res = zsock_recv(fixture->sv[1], &c, 1, 0); zassert_equal(res, 1, "recv() failed: %d", res); timestamp = k_uptime_get(); memset(fds, 0, sizeof(fds)); fds[0].fd = fixture->sv[0]; - fds[0].events |= POLLOUT; - res = poll(fds, 1, 1000); + fds[0].events |= ZSOCK_POLLOUT; + res = zsock_poll(fds, 1, 1000); zassert_not_equal(res, -1, "poll failed: %d", errno); zassert_equal(res, 1, "poll: expected: 1 actual: %d", res); - zassert_not_equal(fds[0].revents & POLLOUT, 0, "POLLOUT not set"); + zassert_not_equal(fds[0].revents & ZSOCK_POLLOUT, 0, "POLLOUT not set"); delta = k_uptime_delta(×tamp); zassert_true(delta < 100, "poll did not exit immediately"); diff --git a/tests/net/socket/socketpair/src/unsupported_calls.c b/tests/net/socket/socketpair/src/unsupported_calls.c index 9cb6804f62c..7c80338daba 100644 --- a/tests/net/socket/socketpair/src/unsupported_calls.c +++ b/tests/net/socket/socketpair/src/unsupported_calls.c @@ -16,25 +16,25 @@ ZTEST_USER_F(net_socketpair, test_unsupported_calls) for (size_t i = 0; i < 2; ++i) { - res = bind(fixture->sv[i], (struct sockaddr *)&addr, len); + res = zsock_bind(fixture->sv[i], (struct sockaddr *)&addr, len); zassert_equal(res, -1, "bind should fail on a socketpair endpoint"); zassert_equal(errno, EISCONN, "bind should set errno to EISCONN"); - res = connect(fixture->sv[i], (struct sockaddr *)&addr, len); + res = zsock_connect(fixture->sv[i], (struct sockaddr *)&addr, len); zassert_equal(res, -1, "connect should fail on a socketpair endpoint"); zassert_equal(errno, EISCONN, "connect should set errno to EISCONN"); - res = listen(fixture->sv[i], 1); + res = zsock_listen(fixture->sv[i], 1); zassert_equal(res, -1, "listen should fail on a socketpair endpoint"); zassert_equal(errno, EINVAL, "listen should set errno to EINVAL"); - res = accept(fixture->sv[i], (struct sockaddr *)&addr, &len); + res = zsock_accept(fixture->sv[i], (struct sockaddr *)&addr, &len); zassert_equal(res, -1, "accept should fail on a socketpair endpoint"); zassert_equal(errno, EOPNOTSUPP, diff --git a/tests/net/socket/tcp/prj.conf b/tests/net/socket/tcp/prj.conf index 846cfa90749..ca331d3e20c 100644 --- a/tests/net/socket/tcp/prj.conf +++ b/tests/net/socket/tcp/prj.conf @@ -11,7 +11,6 @@ CONFIG_NET_IPV6=y CONFIG_NET_IPV6_ND=n CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_POSIX_MAX_FDS=10 # Network driver config diff --git a/tests/net/socket/tcp/src/main.c b/tests/net/socket/tcp/src/main.c index c7a8357f661..1186a3a0a8d 100644 --- a/tests/net/socket/tcp/src/main.c +++ b/tests/net/socket/tcp/src/main.c @@ -36,21 +36,21 @@ LOG_MODULE_REGISTER(net_test, CONFIG_NET_SOCKETS_LOG_LEVEL); static void test_bind(int sock, struct sockaddr *addr, socklen_t addrlen) { - zassert_equal(bind(sock, addr, addrlen), + zassert_equal(zsock_bind(sock, addr, addrlen), 0, "bind failed with error %d", errno); } static void test_listen(int sock) { - zassert_equal(listen(sock, MAX_CONNS), + zassert_equal(zsock_listen(sock, MAX_CONNS), 0, "listen failed with error %d", errno); } static void test_connect(int sock, struct sockaddr *addr, socklen_t addrlen) { - zassert_equal(connect(sock, addr, addrlen), + zassert_equal(zsock_connect(sock, addr, addrlen), 0, "connect failed with error %d", errno); @@ -62,7 +62,7 @@ static void test_connect(int sock, struct sockaddr *addr, socklen_t addrlen) static void test_send(int sock, const void *buf, size_t len, int flags) { - zassert_equal(send(sock, buf, len, flags), + zassert_equal(zsock_send(sock, buf, len, flags), len, "send failed"); } @@ -70,7 +70,7 @@ static void test_send(int sock, const void *buf, size_t len, int flags) static void test_sendto(int sock, const void *buf, size_t len, int flags, const struct sockaddr *addr, socklen_t addrlen) { - zassert_equal(sendto(sock, buf, len, flags, addr, addrlen), + zassert_equal(zsock_sendto(sock, buf, len, flags, addr, addrlen), len, "send failed"); } @@ -80,7 +80,7 @@ static void test_accept(int sock, int *new_sock, struct sockaddr *addr, { zassert_not_null(new_sock, "null newsock"); - *new_sock = accept(sock, addr, addrlen); + *new_sock = zsock_accept(sock, addr, addrlen); zassert_true(*new_sock >= 0, "accept failed"); } @@ -89,14 +89,14 @@ static void test_accept_timeout(int sock, int *new_sock, struct sockaddr *addr, { zassert_not_null(new_sock, "null newsock"); - *new_sock = accept(sock, addr, addrlen); + *new_sock = zsock_accept(sock, addr, addrlen); zassert_equal(*new_sock, -1, "accept succeed"); zassert_equal(errno, EAGAIN, ""); } static void test_fcntl(int sock, int cmd, int val) { - zassert_equal(fcntl(sock, cmd, val), 0, "fcntl failed"); + zassert_equal(zsock_fcntl(sock, cmd, val), 0, "fcntl failed"); } static void test_recv(int sock, int flags) @@ -104,7 +104,7 @@ static void test_recv(int sock, int flags) ssize_t recved = 0; char rx_buf[30] = {0}; - recved = recv(sock, rx_buf, sizeof(rx_buf), flags); + recved = zsock_recv(sock, rx_buf, sizeof(rx_buf), flags); zassert_equal(recved, strlen(TEST_STR_SMALL), "unexpected received bytes"); @@ -121,12 +121,7 @@ static void test_recvfrom(int sock, ssize_t recved = 0; char rx_buf[30] = {0}; - recved = recvfrom(sock, - rx_buf, - sizeof(rx_buf), - flags, - addr, - addrlen); + recved = zsock_recvfrom(sock, rx_buf, sizeof(rx_buf), flags, addr, addrlen); zassert_equal(recved, strlen(TEST_STR_SMALL), "unexpected received bytes"); @@ -143,7 +138,7 @@ static void test_recvmsg(int sock, { ssize_t recved; - recved = recvmsg(sock, msg, flags); + recved = zsock_recvmsg(sock, msg, flags); zassert_equal(recved, expected, "line %d, unexpected received bytes (%d vs %d)", @@ -152,14 +147,14 @@ static void test_recvmsg(int sock, static void test_shutdown(int sock, int how) { - zassert_equal(shutdown(sock, how), + zassert_equal(zsock_shutdown(sock, how), 0, "shutdown failed"); } static void test_close(int sock) { - zassert_equal(close(sock), + zassert_equal(zsock_close(sock), 0, "close failed"); } @@ -173,16 +168,16 @@ static void test_eof(int sock) ssize_t recved; /* Test that EOF properly detected. */ - recved = recv(sock, rx_buf, sizeof(rx_buf), 0); + recved = zsock_recv(sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(recved, 0, ""); /* Calling again should be OK. */ - recved = recv(sock, rx_buf, sizeof(rx_buf), 0); + recved = zsock_recv(sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(recved, 0, ""); /* Calling when TCP connection is fully torn down should be still OK. */ k_sleep(TCP_TEARDOWN_TIMEOUT); - recved = recv(sock, rx_buf, sizeof(rx_buf), 0); + recved = zsock_recv(sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(recved, 0, ""); } @@ -254,7 +249,7 @@ ZTEST_USER(net_socket_tcp, test_v4_send_recv) test_accept(s_sock, &new_sock, &addr, &addrlen); zassert_equal(addrlen, sizeof(struct sockaddr_in), "wrong addrlen"); - test_recv(new_sock, MSG_PEEK); + test_recv(new_sock, ZSOCK_MSG_PEEK); test_recv(new_sock, 0); test_close(c_sock); @@ -289,7 +284,7 @@ ZTEST_USER(net_socket_tcp, test_v6_send_recv) test_accept(s_sock, &new_sock, &addr, &addrlen); zassert_equal(addrlen, sizeof(struct sockaddr_in6), "wrong addrlen"); - test_recv(new_sock, MSG_PEEK); + test_recv(new_sock, ZSOCK_MSG_PEEK); test_recv(new_sock, 0); test_close(c_sock); @@ -337,7 +332,7 @@ void tcp_server_block_thread(void *vps_sock, void *unused2, void *unused3) chunk_size = remain; } - recved = recv(new_sock, buffer, chunk_size, 0); + recved = zsock_recv(new_sock, buffer, chunk_size, 0); zassert(recved > 0, "received bigger then 0", "Error receiving bytes %i bytes, got %i on top of %i in iteration %i, errno %i", @@ -399,7 +394,7 @@ void test_send_recv_large_common(int tcp_nodelay, int family) test_connect(c_sock, s_saddr, addrlen); - rv = setsockopt(c_sock, IPPROTO_TCP, TCP_NODELAY, (char *) &tcp_nodelay, sizeof(int)); + rv = zsock_setsockopt(c_sock, IPPROTO_TCP, TCP_NODELAY, (char *) &tcp_nodelay, sizeof(int)); zassert_equal(rv, 0, "setsockopt failed (%d)", rv); /* send piece by piece */ @@ -422,7 +417,7 @@ void test_send_recv_large_common(int tcp_nodelay, int family) chunk_size = remain; } - int send_bytes = send(c_sock, buffer, chunk_size, 0); + int send_bytes = zsock_send(c_sock, buffer, chunk_size, 0); zassert(send_bytes > 0, "send_bytes bigger then 0", "Error sending %i bytes on top of %i, got %i in iteration %i, errno %i", @@ -531,11 +526,11 @@ ZTEST(net_socket_tcp, test_v4_broken_link) test_accept(s_sock, &new_sock, &addr, &addrlen); zassert_equal(addrlen, sizeof(struct sockaddr_in), "wrong addrlen"); - rv = setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, - sizeof(optval)); + rv = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); - test_recv(new_sock, MSG_PEEK); + test_recv(new_sock, ZSOCK_MSG_PEEK); test_recv(new_sock, 0); /* At this point break the interface */ @@ -548,7 +543,7 @@ ZTEST(net_socket_tcp, test_v4_broken_link) start_time = k_uptime_get_32(); /* Test the loopback packet loss: message should never arrive */ - recved = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + recved = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); time_diff = k_uptime_get_32() - start_time; zassert_equal(recved, -1, "Unexpected return code"); @@ -557,7 +552,7 @@ ZTEST(net_socket_tcp, test_v4_broken_link) "was %dms", time_diff); /* Reading from client should indicate the socket has been closed */ - recved = recv(c_sock, rx_buf, sizeof(rx_buf), 0); + recved = zsock_recv(c_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(recved, -1, "Unexpected return code"); zassert_equal(errno, ETIMEDOUT, "Unexpected errno value: %d", errno); @@ -603,7 +598,7 @@ ZTEST_USER(net_socket_tcp, test_v4_sendto_recvfrom) test_accept(s_sock, &new_sock, &addr, &addrlen); zassert_equal(addrlen, sizeof(struct sockaddr_in), "wrong addrlen"); - test_recvfrom(new_sock, MSG_PEEK, &addr, &addrlen); + test_recvfrom(new_sock, ZSOCK_MSG_PEEK, &addr, &addrlen); zassert_equal(addrlen, sizeof(struct sockaddr_in), "wrong addrlen"); test_recvfrom(new_sock, 0, &addr, &addrlen); @@ -640,7 +635,7 @@ ZTEST_USER(net_socket_tcp, test_v6_sendto_recvfrom) test_accept(s_sock, &new_sock, &addr, &addrlen); zassert_equal(addrlen, sizeof(struct sockaddr_in6), "wrong addrlen"); - test_recvfrom(new_sock, MSG_PEEK, &addr, &addrlen); + test_recvfrom(new_sock, ZSOCK_MSG_PEEK, &addr, &addrlen); zassert_equal(addrlen, sizeof(struct sockaddr_in6), "wrong addrlen"); test_recvfrom(new_sock, 0, &addr, &addrlen); @@ -760,7 +755,7 @@ ZTEST_USER(net_socket_tcp, test_v4_sendto_recvmsg) msg.msg_name = &addr; msg.msg_namelen = addrlen; - test_recvmsg(new_sock, &msg, MSG_PEEK, strlen(TEST_STR_SMALL), + test_recvmsg(new_sock, &msg, ZSOCK_MSG_PEEK, strlen(TEST_STR_SMALL), __LINE__); zassert_mem_equal(buf, TEST_STR_SMALL, strlen(TEST_STR_SMALL), "wrong data (%s)", buf); @@ -832,13 +827,13 @@ void _test_recv_enotconn(int c_sock, int s_sock) test_listen(s_sock); /* Check "client" socket, just created. */ - res = recv(c_sock, rx_buf, sizeof(rx_buf), 0); + res = zsock_recv(c_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(res, -1, "recv() on not connected sock didn't fail"); zassert_equal(errno, ENOTCONN, "recv() on not connected sock didn't " "lead to ENOTCONN"); /* Check "server" socket, bound and listen()ed . */ - res = recv(s_sock, rx_buf, sizeof(rx_buf), 0); + res = zsock_recv(s_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(res, -1, "recv() on not connected sock didn't fail"); zassert_equal(errno, ENOTCONN, "recv() on not connected sock didn't " "lead to ENOTCONN"); @@ -928,7 +923,7 @@ static void shutdown_work(struct k_work *work) struct shutdown_data *data = CONTAINER_OF(dwork, struct shutdown_data, work); - shutdown(data->fd, data->how); + zsock_shutdown(data->fd, data->how); } ZTEST(net_socket_tcp, test_shutdown_rd_while_recv) @@ -1000,8 +995,8 @@ ZTEST(net_socket_tcp, test_open_close_immediately) */ s_saddr.sin_port = htons(SERVER_PORT + 1); - zassert_not_equal(connect(c_sock, (struct sockaddr *)&s_saddr, - sizeof(s_saddr)), + zassert_not_equal(zsock_connect(c_sock, (struct sockaddr *)&s_saddr, + sizeof(s_saddr)), 0, "connect succeed"); test_close(c_sock); @@ -1051,9 +1046,9 @@ ZTEST(net_socket_tcp, test_connect_timeout) loopback_set_packet_drop_ratio(1.0f); - zassert_equal(connect(c_sock, (struct sockaddr *)&s_saddr, - sizeof(s_saddr)), - -1, "connect succeed"); + zassert_equal(zsock_connect(c_sock, (struct sockaddr *)&s_saddr, + sizeof(s_saddr)), + -1, "connect succeed"); zassert_equal(errno, ETIMEDOUT, "connect should be timed out, got %i", errno); @@ -1087,7 +1082,7 @@ ZTEST(net_socket_tcp, test_async_connect_timeout) struct sockaddr_in s_saddr; int c_sock; int rv; - struct pollfd poll_fds[POLL_FDS_NUM]; + struct zsock_pollfd poll_fds[POLL_FDS_NUM]; loopback_set_packet_drop_ratio(1.0f); @@ -1098,18 +1093,18 @@ ZTEST(net_socket_tcp, test_async_connect_timeout) rv = zsock_inet_pton(AF_INET, MY_IPV4_ADDR, &s_saddr.sin_addr); zassert_equal(rv, 1, "inet_pton failed"); - rv = connect(c_sock, (struct sockaddr *)&s_saddr, - sizeof(s_saddr)); + rv = zsock_connect(c_sock, (struct sockaddr *)&s_saddr, + sizeof(s_saddr)); zassert_equal(rv, -1, "connect should not succeed"); zassert_equal(errno, EINPROGRESS, "connect should be in progress, got %i", errno); poll_fds[0].fd = c_sock; - poll_fds[0].events = POLLOUT; - int poll_rc = poll(poll_fds, POLL_FDS_NUM, ASYNC_POLL_TIMEOUT); + poll_fds[0].events = ZSOCK_POLLOUT; + int poll_rc = zsock_poll(poll_fds, POLL_FDS_NUM, ASYNC_POLL_TIMEOUT); zassert_equal(poll_rc, 1, "poll should return 1, got %i", poll_rc); - zassert_equal(poll_fds[0].revents, POLLERR, + zassert_equal(poll_fds[0].revents, ZSOCK_POLLERR, "poll should set error event"); test_close(c_sock); @@ -1128,7 +1123,7 @@ ZTEST(net_socket_tcp, test_async_connect) struct sockaddr_in s_saddr; struct sockaddr addr; socklen_t addrlen = sizeof(addr); - struct pollfd poll_fds[1]; + struct zsock_pollfd poll_fds[1]; int poll_rc; prepare_sock_tcp_v4(MY_IPV4_ADDR, ANY_PORT, &c_sock, &c_saddr); @@ -1138,7 +1133,7 @@ ZTEST(net_socket_tcp, test_async_connect) test_bind(s_sock, (struct sockaddr *)&s_saddr, sizeof(s_saddr)); test_listen(s_sock); - zassert_equal(connect(c_sock, (struct sockaddr *)&s_saddr, sizeof(s_saddr)), + zassert_equal(zsock_connect(c_sock, (struct sockaddr *)&s_saddr, sizeof(s_saddr)), -1, "connect shouldn't complete right away"); @@ -1146,10 +1141,10 @@ ZTEST(net_socket_tcp, test_async_connect) "connect should be in progress, got %i", errno); poll_fds[0].fd = c_sock; - poll_fds[0].events = POLLOUT; - poll_rc = poll(poll_fds, 1, ASYNC_POLL_TIMEOUT); + poll_fds[0].events = ZSOCK_POLLOUT; + poll_rc = zsock_poll(poll_fds, 1, ASYNC_POLL_TIMEOUT); zassert_equal(poll_rc, 1, "poll should return 1, got %i", poll_rc); - zassert_equal(poll_fds[0].revents, POLLOUT, + zassert_equal(poll_fds[0].revents, ZSOCK_POLLOUT, "poll should set POLLOUT"); test_accept(s_sock, &new_sock, &addr, &addrlen); @@ -1188,9 +1183,9 @@ ZTEST(net_socket_tcp, test_z_close_obstructed) test_bind(s_sock, (struct sockaddr *)&s_saddr, sizeof(s_saddr)); test_listen(s_sock); - zassert_equal(connect(c_sock, (struct sockaddr *)&s_saddr, - sizeof(s_saddr)), - 0, "connect not succeed"); + zassert_equal(zsock_connect(c_sock, (struct sockaddr *)&s_saddr, + sizeof(s_saddr)), + 0, "connect not succeed"); test_accept(s_sock, &new_sock, &addr, &addrlen); /* We should have two contexts open now */ @@ -1277,12 +1272,12 @@ ZTEST(net_socket_tcp, test_so_type) prepare_sock_tcp_v4(MY_IPV4_ADDR, ANY_PORT, &sock1, &bind_addr4); prepare_sock_tcp_v6(MY_IPV6_ADDR, ANY_PORT, &sock2, &bind_addr6); - rv = getsockopt(sock1, SOL_SOCKET, SO_TYPE, &optval, &optlen); + rv = zsock_getsockopt(sock1, SOL_SOCKET, SO_TYPE, &optval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, SOCK_STREAM, "getsockopt got invalid type"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); - rv = getsockopt(sock2, SOL_SOCKET, SO_TYPE, &optval, &optlen); + rv = zsock_getsockopt(sock2, SOL_SOCKET, SO_TYPE, &optval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, SOCK_STREAM, "getsockopt got invalid type"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); @@ -1306,12 +1301,12 @@ ZTEST(net_socket_tcp, test_so_protocol) prepare_sock_tcp_v4(MY_IPV4_ADDR, ANY_PORT, &sock1, &bind_addr4); prepare_sock_tcp_v6(MY_IPV6_ADDR, ANY_PORT, &sock2, &bind_addr6); - rv = getsockopt(sock1, SOL_SOCKET, SO_PROTOCOL, &optval, &optlen); + rv = zsock_getsockopt(sock1, SOL_SOCKET, SO_PROTOCOL, &optval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, IPPROTO_TCP, "getsockopt got invalid protocol"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); - rv = getsockopt(sock2, SOL_SOCKET, SO_PROTOCOL, &optval, &optlen); + rv = zsock_getsockopt(sock2, SOL_SOCKET, SO_PROTOCOL, &optval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, IPPROTO_TCP, "getsockopt got invalid protocol"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); @@ -1334,26 +1329,26 @@ ZTEST(net_socket_tcp, test_so_rcvbuf) prepare_sock_tcp_v4(MY_IPV4_ADDR, ANY_PORT, &sock1, &bind_addr4); prepare_sock_tcp_v6(MY_IPV6_ADDR, ANY_PORT, &sock2, &bind_addr6); - rv = setsockopt(sock1, SOL_SOCKET, SO_RCVBUF, &optval, sizeof(optval)); + rv = zsock_setsockopt(sock1, SOL_SOCKET, SO_RCVBUF, &optval, sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", rv); - rv = getsockopt(sock1, SOL_SOCKET, SO_RCVBUF, &retval, &optlen); + rv = zsock_getsockopt(sock1, SOL_SOCKET, SO_RCVBUF, &retval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", rv); zassert_equal(retval, optval, "getsockopt got invalid rcvbuf"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); - rv = setsockopt(sock2, SOL_SOCKET, SO_RCVBUF, &optval, sizeof(optval)); + rv = zsock_setsockopt(sock2, SOL_SOCKET, SO_RCVBUF, &optval, sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", rv); - rv = getsockopt(sock2, SOL_SOCKET, SO_RCVBUF, &retval, &optlen); + rv = zsock_getsockopt(sock2, SOL_SOCKET, SO_RCVBUF, &retval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", rv); zassert_equal(retval, optval, "getsockopt got invalid rcvbuf"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); optval = -1; - rv = setsockopt(sock2, SOL_SOCKET, SO_RCVBUF, &optval, sizeof(optval)); + rv = zsock_setsockopt(sock2, SOL_SOCKET, SO_RCVBUF, &optval, sizeof(optval)); zassert_equal(rv, -1, "setsockopt failed (%d)", rv); optval = UINT16_MAX + 1; - rv = setsockopt(sock2, SOL_SOCKET, SO_RCVBUF, &optval, sizeof(optval)); + rv = zsock_setsockopt(sock2, SOL_SOCKET, SO_RCVBUF, &optval, sizeof(optval)); zassert_equal(rv, -1, "setsockopt failed (%d)", rv); test_close(sock1); @@ -1387,11 +1382,11 @@ ZTEST(net_socket_tcp, test_so_rcvbuf_win_size) zassert_equal(addrlen, sizeof(struct sockaddr_in), "wrong addrlen"); /* Lower server-side RX window size. */ - rv = setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, - sizeof(buf_optval)); + rv = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, + sizeof(buf_optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); - rv = send(c_sock, tx_buf, sizeof(tx_buf), MSG_DONTWAIT); + rv = zsock_send(c_sock, tx_buf, sizeof(tx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(rv, sizeof(tx_buf), "Unexpected return code %d", rv); /* Window should've dropped to 0, so the ACK will be delayed - wait for @@ -1400,7 +1395,7 @@ ZTEST(net_socket_tcp, test_so_rcvbuf_win_size) k_msleep(150); /* Client should not be able to send now (RX window full). */ - rv = send(c_sock, tx_buf, 1, MSG_DONTWAIT); + rv = zsock_send(c_sock, tx_buf, 1, ZSOCK_MSG_DONTWAIT); zassert_equal(rv, -1, "Unexpected return code %d", rv); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); @@ -1423,26 +1418,26 @@ ZTEST(net_socket_tcp, test_so_sndbuf) prepare_sock_tcp_v4(MY_IPV4_ADDR, ANY_PORT, &sock1, &bind_addr4); prepare_sock_tcp_v6(MY_IPV6_ADDR, ANY_PORT, &sock2, &bind_addr6); - rv = setsockopt(sock1, SOL_SOCKET, SO_SNDBUF, &optval, sizeof(optval)); + rv = zsock_setsockopt(sock1, SOL_SOCKET, SO_SNDBUF, &optval, sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", rv); - rv = getsockopt(sock1, SOL_SOCKET, SO_SNDBUF, &retval, &optlen); + rv = zsock_getsockopt(sock1, SOL_SOCKET, SO_SNDBUF, &retval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", rv); zassert_equal(retval, optval, "getsockopt got invalid rcvbuf"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); - rv = setsockopt(sock2, SOL_SOCKET, SO_SNDBUF, &optval, sizeof(optval)); + rv = zsock_setsockopt(sock2, SOL_SOCKET, SO_SNDBUF, &optval, sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", rv); - rv = getsockopt(sock2, SOL_SOCKET, SO_SNDBUF, &retval, &optlen); + rv = zsock_getsockopt(sock2, SOL_SOCKET, SO_SNDBUF, &retval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", rv); zassert_equal(retval, optval, "getsockopt got invalid rcvbuf"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); optval = -1; - rv = setsockopt(sock2, SOL_SOCKET, SO_SNDBUF, &optval, sizeof(optval)); + rv = zsock_setsockopt(sock2, SOL_SOCKET, SO_SNDBUF, &optval, sizeof(optval)); zassert_equal(rv, -1, "setsockopt failed (%d)", rv); optval = UINT16_MAX + 1; - rv = setsockopt(sock2, SOL_SOCKET, SO_RCVBUF, &optval, sizeof(optval)); + rv = zsock_setsockopt(sock2, SOL_SOCKET, SO_RCVBUF, &optval, sizeof(optval)); zassert_equal(rv, -1, "setsockopt failed (%d)", rv); test_close(sock1); @@ -1468,8 +1463,8 @@ ZTEST(net_socket_tcp, test_so_sndbuf_win_size) prepare_sock_tcp_v4(MY_IPV4_ADDR, SERVER_PORT, &s_sock, &s_saddr); /* Lower client-side TX window size. */ - rv = setsockopt(c_sock, SOL_SOCKET, SO_SNDBUF, &buf_optval, - sizeof(buf_optval)); + rv = zsock_setsockopt(c_sock, SOL_SOCKET, SO_SNDBUF, &buf_optval, + sizeof(buf_optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); test_bind(s_sock, (struct sockaddr *)&s_saddr, sizeof(s_saddr)); @@ -1483,11 +1478,11 @@ ZTEST(net_socket_tcp, test_so_sndbuf_win_size) /* Make sure the ACK from the server does not arrive. */ loopback_set_packet_drop_ratio(1.0f); - rv = send(c_sock, tx_buf, sizeof(tx_buf), MSG_DONTWAIT); + rv = zsock_send(c_sock, tx_buf, sizeof(tx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(rv, sizeof(tx_buf), "Unexpected return code %d", rv); /* Client should not be able to send now (TX window full). */ - rv = send(c_sock, tx_buf, 1, MSG_DONTWAIT); + rv = zsock_send(c_sock, tx_buf, 1, ZSOCK_MSG_DONTWAIT); zassert_equal(rv, -1, "Unexpected return code %d", rv); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); @@ -1531,17 +1526,17 @@ ZTEST(net_socket_tcp, test_v4_so_rcvtimeo) test_accept(s_sock, &new_sock, &addr, &addrlen); zassert_equal(addrlen, sizeof(struct sockaddr_in), "wrong addrlen"); - rv = setsockopt(c_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, - sizeof(optval)); + rv = zsock_setsockopt(c_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); optval.tv_usec = 0; - rv = setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, - sizeof(optval)); + rv = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); start_time = k_uptime_get_32(); - recved = recv(c_sock, rx_buf, sizeof(rx_buf), 0); + recved = zsock_recv(c_sock, rx_buf, sizeof(rx_buf), 0); time_diff = k_uptime_get_32() - start_time; zassert_equal(recved, -1, "Unexpected return code"); @@ -1550,7 +1545,7 @@ ZTEST(net_socket_tcp, test_v4_so_rcvtimeo) "was %dms", time_diff); start_time = k_uptime_get_32(); - recved = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + recved = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); time_diff = k_uptime_get_32() - start_time; zassert_equal(recved, -1, "Unexpected return code"); @@ -1598,17 +1593,17 @@ ZTEST(net_socket_tcp, test_v6_so_rcvtimeo) test_accept(s_sock, &new_sock, &addr, &addrlen); zassert_equal(addrlen, sizeof(struct sockaddr_in6), "wrong addrlen"); - rv = setsockopt(c_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, - sizeof(optval)); + rv = zsock_setsockopt(c_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); optval.tv_usec = 0; - rv = setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, - sizeof(optval)); + rv = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); start_time = k_uptime_get_32(); - recved = recv(c_sock, rx_buf, sizeof(rx_buf), 0); + recved = zsock_recv(c_sock, rx_buf, sizeof(rx_buf), 0); time_diff = k_uptime_get_32() - start_time; zassert_equal(recved, -1, "Unexpected return code"); @@ -1617,7 +1612,7 @@ ZTEST(net_socket_tcp, test_v6_so_rcvtimeo) "was %dms", time_diff); start_time = k_uptime_get_32(); - recved = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + recved = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); time_diff = k_uptime_get_32() - start_time; zassert_equal(recved, -1, "Unexpected return code"); @@ -1663,16 +1658,16 @@ ZTEST(net_socket_tcp, test_v4_so_sndtimeo) test_accept(s_sock, &new_sock, &addr, &addrlen); zassert_equal(addrlen, sizeof(struct sockaddr_in), "wrong addrlen"); - rv = setsockopt(c_sock, SOL_SOCKET, SO_SNDTIMEO, &timeo_optval, - sizeof(timeo_optval)); + rv = zsock_setsockopt(c_sock, SOL_SOCKET, SO_SNDTIMEO, &timeo_optval, + sizeof(timeo_optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); /* Simulate window full scenario with SO_RCVBUF option. */ - rv = setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, - sizeof(buf_optval)); + rv = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, + sizeof(buf_optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); - rv = send(c_sock, tx_buf, sizeof(tx_buf), MSG_DONTWAIT); + rv = zsock_send(c_sock, tx_buf, sizeof(tx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(rv, sizeof(tx_buf), "Unexpected return code %d", rv); /* Wait for ACK (empty window). */ @@ -1680,7 +1675,7 @@ ZTEST(net_socket_tcp, test_v4_so_sndtimeo) /* Client should not be able to send now and time out after SO_SNDTIMEO */ start_time = k_uptime_get_32(); - rv = send(c_sock, tx_buf, 1, 0); + rv = zsock_send(c_sock, tx_buf, 1, 0); time_diff = k_uptime_get_32() - start_time; zassert_equal(rv, -1, "Unexpected return code %d", rv); @@ -1724,16 +1719,16 @@ ZTEST(net_socket_tcp, test_v6_so_sndtimeo) test_accept(s_sock, &new_sock, &addr, &addrlen); zassert_equal(addrlen, sizeof(struct sockaddr_in6), "wrong addrlen"); - rv = setsockopt(c_sock, SOL_SOCKET, SO_SNDTIMEO, &timeo_optval, - sizeof(timeo_optval)); + rv = zsock_setsockopt(c_sock, SOL_SOCKET, SO_SNDTIMEO, &timeo_optval, + sizeof(timeo_optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); /* Simulate window full scenario with SO_RCVBUF option. */ - rv = setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, - sizeof(buf_optval)); + rv = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, + sizeof(buf_optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); - rv = send(c_sock, tx_buf, sizeof(tx_buf), MSG_DONTWAIT); + rv = zsock_send(c_sock, tx_buf, sizeof(tx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(rv, sizeof(tx_buf), "Unexpected return code %d", rv); /* Wait for ACK (empty window). */ @@ -1741,7 +1736,7 @@ ZTEST(net_socket_tcp, test_v6_so_sndtimeo) /* Client should not be able to send now and time out after SO_SNDTIMEO */ start_time = k_uptime_get_32(); - rv = send(c_sock, tx_buf, 1, 0); + rv = zsock_send(c_sock, tx_buf, 1, 0); time_diff = k_uptime_get_32() - start_time; zassert_equal(rv, -1, "Unexpected return code %d", rv); @@ -1819,7 +1814,7 @@ ZTEST(net_socket_tcp, test_v4_msg_waitall) test_msg_waitall_tx_work_handler); k_work_reschedule(&test_data.tx_work, K_MSEC(10)); - ret = recv(new_sock, rx_buf, sizeof(rx_buf), MSG_WAITALL); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_WAITALL); zassert_equal(ret, sizeof(rx_buf), "Invalid length received"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, sizeof(rx_buf), "Invalid data received"); @@ -1828,8 +1823,8 @@ ZTEST(net_socket_tcp, test_v4_msg_waitall) /* MSG_WAITALL + SO_RCVTIMEO - make sure recv returns the amount of data * received so far */ - ret = setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, - sizeof(timeo_optval)); + ret = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, + sizeof(timeo_optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); memset(rx_buf, 0, sizeof(rx_buf)); @@ -1840,7 +1835,7 @@ ZTEST(net_socket_tcp, test_v4_msg_waitall) test_msg_waitall_tx_work_handler); k_work_reschedule(&test_data.tx_work, K_MSEC(10)); - ret = recv(new_sock, rx_buf, sizeof(rx_buf) - 1, MSG_WAITALL); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf) - 1, ZSOCK_MSG_WAITALL); if (ret < 0) { LOG_ERR("receive return val %i", ret); } @@ -1896,7 +1891,7 @@ ZTEST(net_socket_tcp, test_v6_msg_waitall) test_msg_waitall_tx_work_handler); k_work_reschedule(&test_data.tx_work, K_MSEC(10)); - ret = recv(new_sock, rx_buf, sizeof(rx_buf), MSG_WAITALL); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_WAITALL); zassert_equal(ret, sizeof(rx_buf), "Invalid length received"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, sizeof(rx_buf), "Invalid data received"); @@ -1905,8 +1900,8 @@ ZTEST(net_socket_tcp, test_v6_msg_waitall) /* MSG_WAITALL + SO_RCVTIMEO - make sure recv returns the amount of data * received so far */ - ret = setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, - sizeof(timeo_optval)); + ret = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, + sizeof(timeo_optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); memset(rx_buf, 0, sizeof(rx_buf)); @@ -1917,7 +1912,7 @@ ZTEST(net_socket_tcp, test_v6_msg_waitall) test_msg_waitall_tx_work_handler); k_work_reschedule(&test_data.tx_work, K_MSEC(10)); - ret = recv(new_sock, rx_buf, sizeof(rx_buf) - 1, MSG_WAITALL); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf) - 1, ZSOCK_MSG_WAITALL); zassert_equal(ret, sizeof(rx_buf) - 1, "Invalid length received"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, sizeof(rx_buf) - 1, "Invalid data received"); @@ -1940,7 +1935,7 @@ static void child_entry(void *p1, void *p2, void *p3) { int sock = POINTER_TO_INT(p1); - result = close(sock); + result = zsock_close(sock); } static void spawn_child(int sock) @@ -2016,7 +2011,7 @@ static void close_work(struct k_work *work) struct k_work_delayable *dwork = k_work_delayable_from_work(work); struct close_data *data = CONTAINER_OF(dwork, struct close_data, work); - close(data->fd); + zsock_close(data->fd); } ZTEST(net_socket_tcp, test_close_while_recv) @@ -2053,7 +2048,7 @@ ZTEST(net_socket_tcp, test_close_while_recv) /* Start blocking recv(), which should be unblocked by close() from * another thread and return an error. */ - ret = recv(c_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(c_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, -1, "recv did not return error"); zassert_equal(errno, EINTR, "Unexpected errno value: %d", errno); @@ -2088,7 +2083,7 @@ ZTEST(net_socket_tcp, test_close_while_accept) /* Start blocking accept(), which should be unblocked by close() from * another thread and return an error. */ - new_sock = accept(s_sock, &addr, &addrlen); + new_sock = zsock_accept(s_sock, &addr, &addrlen); zassert_equal(new_sock, -1, "accept did not return error"); zassert_equal(errno, EINTR, "Unexpected errno value: %d", errno); @@ -2164,7 +2159,7 @@ static void test_ioctl_fionread_common(int af) /* both ends should have zero bytes available after being newly created */ for (enum fde i = SERVER; i <= CLIENT; ++i) { avail = 42; - zassert_ok(ioctl(fd[i], ZFD_IOCTL_FIONREAD, &avail)); + zassert_ok(zsock_ioctl(fd[i], ZFD_IOCTL_FIONREAD, &avail)); zassert_equal(0, avail, "exp: %d: act: %d", 0, avail); } @@ -2175,7 +2170,7 @@ static void test_ioctl_fionread_common(int af) zassert_equal(1, write(fd[i], "\x42", 1)); zassert_equal(1, write(fd[i], "\x73", 1)); k_msleep(100); - zassert_ok(ioctl(fd[j], ZFD_IOCTL_FIONREAD, &avail)); + zassert_ok(zsock_ioctl(fd[j], ZFD_IOCTL_FIONREAD, &avail)); zassert_equal(ARRAY_SIZE(bytes), avail, "exp: %d: act: %d", ARRAY_SIZE(bytes), avail); } @@ -2186,13 +2181,13 @@ static void test_ioctl_fionread_common(int af) int act = read(fd[i], bytes, ARRAY_SIZE(bytes)); zassert_equal(ex, act, "read() failed: errno: %d exp: %d act: %d", errno, ex, act); - zassert_ok(ioctl(fd[i], ZFD_IOCTL_FIONREAD, &avail)); + zassert_ok(zsock_ioctl(fd[i], ZFD_IOCTL_FIONREAD, &avail)); zassert_equal(0, avail, "exp: %d: act: %d", 0, avail); } - close(fd[SERVER]); - close(fd[CLIENT]); - close(fd[ACCEPT]); + zsock_close(fd[SERVER]); + zsock_close(fd[CLIENT]); + zsock_close(fd[ACCEPT]); test_context_cleanup(); } @@ -2217,12 +2212,12 @@ ZTEST(net_socket_tcp, test_connect_and_wait_for_v4_select) int fd, flags, ret, optval; socklen_t optlen = sizeof(optval); - fd = socket(AF_INET, SOCK_STREAM, 0); + fd = zsock_socket(AF_INET, SOCK_STREAM, 0); - flags = fcntl(fd, F_GETFL, 0); - fcntl(fd, F_SETFL, flags | O_NONBLOCK); + flags = zsock_fcntl(fd, F_GETFL, 0); + zsock_fcntl(fd, F_SETFL, flags | O_NONBLOCK); - inet_pton(AF_INET, "127.0.0.1", (void *)&v4addr); + zsock_inet_pton(AF_INET, "127.0.0.1", (void *)&v4addr); addr.sin_family = AF_INET; net_ipaddr_copy(&addr.sin_addr, &v4addr); @@ -2230,29 +2225,29 @@ ZTEST(net_socket_tcp, test_connect_and_wait_for_v4_select) /* There should be nobody serving this port */ addr.sin_port = htons(8088); - ret = connect(fd, (const struct sockaddr *)&addr, sizeof(addr)); + ret = zsock_connect(fd, (const struct sockaddr *)&addr, sizeof(addr)); zassert_equal(ret, -1, "connect succeed, %d", errno); zassert_equal(errno, EINPROGRESS, "connect succeed, %d", errno); /* Wait for the connection (this should fail eventually) */ while (1) { - fd_set wfds; + zsock_fd_set wfds; struct timeval tv = { .tv_sec = 1, .tv_usec = 0 }; - FD_ZERO(&wfds); - FD_SET(fd, &wfds); + ZSOCK_FD_ZERO(&wfds); + ZSOCK_FD_SET(fd, &wfds); /* Check if the connection is there, this should timeout */ - ret = select(fd + 1, NULL, &wfds, NULL, &tv); + ret = zsock_select(fd + 1, NULL, &wfds, NULL, &tv); if (ret < 0) { break; } if (ret > 0) { - if (FD_ISSET(fd, &wfds)) { + if (ZSOCK_FD_ISSET(fd, &wfds)) { break; } } @@ -2261,7 +2256,7 @@ ZTEST(net_socket_tcp, test_connect_and_wait_for_v4_select) zassert_true(ret > 0, "select failed, %d", errno); /* Get the reason for the connect */ - ret = getsockopt(fd, SOL_SOCKET, SO_ERROR, &optval, &optlen); + ret = zsock_getsockopt(fd, SOL_SOCKET, SO_ERROR, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed, %d", errno); /* If SO_ERROR is 0, then it means that connect succeed. Any @@ -2269,7 +2264,7 @@ ZTEST(net_socket_tcp, test_connect_and_wait_for_v4_select) */ zassert_equal(optval, ECONNREFUSED, "unexpected connect status, %d", optval); - ret = close(fd); + ret = zsock_close(fd); zassert_equal(ret, 0, "close failed, %d", errno); } @@ -2280,18 +2275,18 @@ ZTEST(net_socket_tcp, test_connect_and_wait_for_v4_select) ZTEST(net_socket_tcp, test_connect_and_wait_for_v4_poll) { struct sockaddr_in addr = { 0 }; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; struct in_addr v4addr; int fd, flags, ret, optval; bool closed = false; socklen_t optlen = sizeof(optval); - fd = socket(AF_INET, SOCK_STREAM, 0); + fd = zsock_socket(AF_INET, SOCK_STREAM, 0); - flags = fcntl(fd, F_GETFL, 0); - fcntl(fd, F_SETFL, flags | O_NONBLOCK); + flags = zsock_fcntl(fd, F_GETFL, 0); + zsock_fcntl(fd, F_SETFL, flags | O_NONBLOCK); - inet_pton(AF_INET, "127.0.0.1", (void *)&v4addr); + zsock_inet_pton(AF_INET, "127.0.0.1", (void *)&v4addr); addr.sin_family = AF_INET; net_ipaddr_copy(&addr.sin_addr, &v4addr); @@ -2299,7 +2294,7 @@ ZTEST(net_socket_tcp, test_connect_and_wait_for_v4_poll) /* There should be nobody serving this port */ addr.sin_port = htons(8088); - ret = connect(fd, (const struct sockaddr *)&addr, sizeof(addr)); + ret = zsock_connect(fd, (const struct sockaddr *)&addr, sizeof(addr)); zassert_equal(ret, -1, "connect succeed, %d", errno); zassert_equal(errno, EINPROGRESS, "connect succeed, %d", errno); @@ -2307,16 +2302,16 @@ ZTEST(net_socket_tcp, test_connect_and_wait_for_v4_poll) while (1) { memset(fds, 0, sizeof(fds)); fds[0].fd = fd; - fds[0].events = POLLOUT; + fds[0].events = ZSOCK_POLLOUT; /* Check if the connection is there, this should timeout */ - ret = poll(fds, 1, 10); + ret = zsock_poll(fds, 1, 10); if (ret < 0) { break; } if (fds[0].revents > 0) { - if (fds[0].revents & POLLERR) { + if (fds[0].revents & ZSOCK_POLLERR) { closed = true; break; } @@ -2326,7 +2321,7 @@ ZTEST(net_socket_tcp, test_connect_and_wait_for_v4_poll) zassert_true(closed, "poll failed, %d", errno); /* Get the reason for the connect */ - ret = getsockopt(fd, SOL_SOCKET, SO_ERROR, &optval, &optlen); + ret = zsock_getsockopt(fd, SOL_SOCKET, SO_ERROR, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed, %d", errno); /* If SO_ERROR is 0, then it means that connect succeed. Any @@ -2334,7 +2329,7 @@ ZTEST(net_socket_tcp, test_connect_and_wait_for_v4_poll) */ zassert_equal(optval, ECONNREFUSED, "unexpected connect status, %d", optval); - ret = close(fd); + ret = zsock_close(fd); zassert_equal(ret, 0, "close failed, %d", errno); } @@ -2348,36 +2343,36 @@ ZTEST(net_socket_tcp, test_so_keepalive) prepare_sock_tcp_v4(MY_IPV4_ADDR, ANY_PORT, &sock, &bind_addr4); /* Keep-alive should be disabled by default. */ - ret = getsockopt(sock, SOL_SOCKET, SO_KEEPALIVE, &optval, &optlen); + ret = zsock_getsockopt(sock, SOL_SOCKET, SO_KEEPALIVE, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, 0, "getsockopt got invalid value"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); /* Enable keep-alive. */ optval = 1; - ret = setsockopt(sock, SOL_SOCKET, SO_KEEPALIVE, - &optval, sizeof(optval)); + ret = zsock_setsockopt(sock, SOL_SOCKET, SO_KEEPALIVE, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); - ret = getsockopt(sock, SOL_SOCKET, SO_KEEPALIVE, &optval, &optlen); + ret = zsock_getsockopt(sock, SOL_SOCKET, SO_KEEPALIVE, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, 1, "getsockopt got invalid value"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); /* Check keep-alive parameters defaults. */ - ret = getsockopt(sock, IPPROTO_TCP, TCP_KEEPIDLE, &optval, &optlen); + ret = zsock_getsockopt(sock, IPPROTO_TCP, TCP_KEEPIDLE, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, CONFIG_NET_TCP_KEEPIDLE_DEFAULT, "getsockopt got invalid value"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); - ret = getsockopt(sock, IPPROTO_TCP, TCP_KEEPINTVL, &optval, &optlen); + ret = zsock_getsockopt(sock, IPPROTO_TCP, TCP_KEEPINTVL, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, CONFIG_NET_TCP_KEEPINTVL_DEFAULT, "getsockopt got invalid value"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); - ret = getsockopt(sock, IPPROTO_TCP, TCP_KEEPCNT, &optval, &optlen); + ret = zsock_getsockopt(sock, IPPROTO_TCP, TCP_KEEPCNT, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, CONFIG_NET_TCP_KEEPCNT_DEFAULT, "getsockopt got invalid value"); @@ -2385,31 +2380,31 @@ ZTEST(net_socket_tcp, test_so_keepalive) /* Check keep-alive parameters update. */ optval = 123; - ret = setsockopt(sock, IPPROTO_TCP, TCP_KEEPIDLE, - &optval, sizeof(optval)); + ret = zsock_setsockopt(sock, IPPROTO_TCP, TCP_KEEPIDLE, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); optval = 10; - ret = setsockopt(sock, IPPROTO_TCP, TCP_KEEPINTVL, - &optval, sizeof(optval)); + ret = zsock_setsockopt(sock, IPPROTO_TCP, TCP_KEEPINTVL, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); optval = 2; - ret = setsockopt(sock, IPPROTO_TCP, TCP_KEEPCNT, - &optval, sizeof(optval)); + ret = zsock_setsockopt(sock, IPPROTO_TCP, TCP_KEEPCNT, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); - ret = getsockopt(sock, IPPROTO_TCP, TCP_KEEPIDLE, &optval, &optlen); + ret = zsock_getsockopt(sock, IPPROTO_TCP, TCP_KEEPIDLE, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, 123, "getsockopt got invalid value"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); - ret = getsockopt(sock, IPPROTO_TCP, TCP_KEEPINTVL, &optval, &optlen); + ret = zsock_getsockopt(sock, IPPROTO_TCP, TCP_KEEPINTVL, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, 10, "getsockopt got invalid value"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); - ret = getsockopt(sock, IPPROTO_TCP, TCP_KEEPCNT, &optval, &optlen); + ret = zsock_getsockopt(sock, IPPROTO_TCP, TCP_KEEPCNT, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, 2, "getsockopt got invalid value"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); @@ -2432,35 +2427,35 @@ ZTEST(net_socket_tcp, test_keepalive_timeout) /* Enable keep-alive on both ends and set timeouts/retries to minimum */ optval = 1; - ret = setsockopt(c_sock, SOL_SOCKET, SO_KEEPALIVE, - &optval, sizeof(optval)); + ret = zsock_setsockopt(c_sock, SOL_SOCKET, SO_KEEPALIVE, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); - ret = setsockopt(s_sock, SOL_SOCKET, SO_KEEPALIVE, - &optval, sizeof(optval)); + ret = zsock_setsockopt(s_sock, SOL_SOCKET, SO_KEEPALIVE, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); optval = 1; - ret = setsockopt(c_sock, IPPROTO_TCP, TCP_KEEPIDLE, - &optval, sizeof(optval)); + ret = zsock_setsockopt(c_sock, IPPROTO_TCP, TCP_KEEPIDLE, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); - ret = setsockopt(s_sock, IPPROTO_TCP, TCP_KEEPIDLE, - &optval, sizeof(optval)); + ret = zsock_setsockopt(s_sock, IPPROTO_TCP, TCP_KEEPIDLE, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); optval = 1; - ret = setsockopt(c_sock, IPPROTO_TCP, TCP_KEEPINTVL, - &optval, sizeof(optval)); + ret = zsock_setsockopt(c_sock, IPPROTO_TCP, TCP_KEEPINTVL, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); - ret = setsockopt(s_sock, IPPROTO_TCP, TCP_KEEPINTVL, - &optval, sizeof(optval)); + ret = zsock_setsockopt(s_sock, IPPROTO_TCP, TCP_KEEPINTVL, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); optval = 1; - ret = setsockopt(c_sock, IPPROTO_TCP, TCP_KEEPCNT, - &optval, sizeof(optval)); + ret = zsock_setsockopt(c_sock, IPPROTO_TCP, TCP_KEEPCNT, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); - ret = setsockopt(s_sock, IPPROTO_TCP, TCP_KEEPCNT, - &optval, sizeof(optval)); + ret = zsock_setsockopt(s_sock, IPPROTO_TCP, TCP_KEEPCNT, + &optval, sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); /* Establish connection */ @@ -2474,12 +2469,12 @@ ZTEST(net_socket_tcp, test_keepalive_timeout) */ loopback_set_packet_drop_ratio(1.0f); - ret = recv(c_sock, &rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(c_sock, &rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, -1, "recv() should've failed"); zassert_equal(errno, ETIMEDOUT, "wrong errno value, %d", errno); /* Same on the other end. */ - ret = recv(new_sock, &rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, &rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, -1, "recv() should've failed"); zassert_equal(errno, ETIMEDOUT, "wrong errno value, %d", errno); diff --git a/tests/net/socket/tls/prj.conf b/tests/net/socket/tls/prj.conf index 51e4f7a9032..1b0c9485aee 100644 --- a/tests/net/socket/tls/prj.conf +++ b/tests/net/socket/tls/prj.conf @@ -12,7 +12,6 @@ CONFIG_NET_IPV6=y CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_SOCKOPT_TLS=y CONFIG_NET_SOCKETS_ENABLE_DTLS=y CONFIG_NET_SOCKETS_DTLS_SENDMSG_BUF_SIZE=128 diff --git a/tests/net/socket/tls/src/main.c b/tests/net/socket/tls/src/main.c index 3dd9f30db0c..03520c575ce 100644 --- a/tests/net/socket/tls/src/main.c +++ b/tests/net/socket/tls/src/main.c @@ -73,13 +73,13 @@ static void test_config_psk(int s_sock, int c_sock) 0, "Failed to register PSK ID"); if (s_sock >= 0) { - zassert_equal(setsockopt(s_sock, SOL_TLS, TLS_SEC_TAG_LIST, + zassert_equal(zsock_setsockopt(s_sock, SOL_TLS, TLS_SEC_TAG_LIST, sec_tag_list, sizeof(sec_tag_list)), 0, "Failed to set PSK on server socket"); } if (c_sock >= 0) { - zassert_equal(setsockopt(c_sock, SOL_TLS, TLS_SEC_TAG_LIST, + zassert_equal(zsock_setsockopt(c_sock, SOL_TLS, TLS_SEC_TAG_LIST, sec_tag_list, sizeof(sec_tag_list)), 0, "Failed to set PSK on client socket"); } @@ -87,19 +87,19 @@ static void test_config_psk(int s_sock, int c_sock) static void test_fcntl(int sock, int cmd, int val) { - zassert_equal(fcntl(sock, cmd, val), 0, "fcntl failed"); + zassert_equal(zsock_fcntl(sock, cmd, val), 0, "fcntl failed"); } static void test_bind(int sock, struct sockaddr *addr, socklen_t addrlen) { - zassert_equal(bind(sock, addr, addrlen), + zassert_equal(zsock_bind(sock, addr, addrlen), 0, "bind failed"); } static void test_listen(int sock) { - zassert_equal(listen(sock, MAX_CONNS), + zassert_equal(zsock_listen(sock, MAX_CONNS), 0, "listen failed"); } @@ -108,7 +108,7 @@ static void test_connect(int sock, struct sockaddr *addr, socklen_t addrlen) { k_yield(); - zassert_equal(connect(sock, addr, addrlen), + zassert_equal(zsock_connect(sock, addr, addrlen), 0, "connect failed"); @@ -120,7 +120,7 @@ static void test_connect(int sock, struct sockaddr *addr, socklen_t addrlen) static void test_send(int sock, const void *buf, size_t len, int flags) { - zassert_equal(send(sock, buf, len, flags), + zassert_equal(zsock_send(sock, buf, len, flags), len, "send failed"); } @@ -135,7 +135,7 @@ static void test_sendmsg(int sock, const struct msghdr *msg, int flags) total_len += vec->iov_len; } - zassert_equal(sendmsg(sock, msg, flags), + zassert_equal(zsock_sendmsg(sock, msg, flags), total_len, "sendmsg failed"); } @@ -145,20 +145,20 @@ static void test_accept(int sock, int *new_sock, struct sockaddr *addr, { zassert_not_null(new_sock, "null newsock"); - *new_sock = accept(sock, addr, addrlen); + *new_sock = zsock_accept(sock, addr, addrlen); zassert_true(*new_sock >= 0, "accept failed"); } static void test_shutdown(int sock, int how) { - zassert_equal(shutdown(sock, how), + zassert_equal(zsock_shutdown(sock, how), 0, "shutdown failed"); } static void test_close(int sock) { - zassert_equal(close(sock), + zassert_equal(zsock_close(sock), 0, "close failed"); } @@ -187,16 +187,16 @@ static void test_eof(int sock) ssize_t recved; /* Test that EOF properly detected. */ - recved = recv(sock, rx_buf, sizeof(rx_buf), 0); + recved = zsock_recv(sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(recved, 0, ""); /* Calling again should be OK. */ - recved = recv(sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + recved = zsock_recv(sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(recved, 0, ""); /* Calling when TCP connection is fully torn down should be still OK. */ k_sleep(TCP_TEARDOWN_TIMEOUT); - recved = recv(sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + recved = zsock_recv(sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(recved, 0, ""); } @@ -211,12 +211,12 @@ ZTEST(net_socket_tls, test_so_type) prepare_sock_tls_v4(MY_IPV4_ADDR, ANY_PORT, &sock1, &bind_addr4, IPPROTO_TLS_1_2); prepare_sock_tls_v6(MY_IPV6_ADDR, ANY_PORT, &sock2, &bind_addr6, IPPROTO_TLS_1_2); - rv = getsockopt(sock1, SOL_SOCKET, SO_TYPE, &optval, &optlen); + rv = zsock_getsockopt(sock1, SOL_SOCKET, SO_TYPE, &optval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, SOCK_STREAM, "getsockopt got invalid type"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); - rv = getsockopt(sock2, SOL_SOCKET, SO_TYPE, &optval, &optlen); + rv = zsock_getsockopt(sock2, SOL_SOCKET, SO_TYPE, &optval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, SOCK_STREAM, "getsockopt got invalid type"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); @@ -236,13 +236,13 @@ ZTEST(net_socket_tls, test_so_protocol) prepare_sock_tls_v4(MY_IPV4_ADDR, ANY_PORT, &sock1, &bind_addr4, IPPROTO_TLS_1_2); prepare_sock_tls_v6(MY_IPV6_ADDR, ANY_PORT, &sock2, &bind_addr6, IPPROTO_TLS_1_1); - rv = getsockopt(sock1, SOL_SOCKET, SO_PROTOCOL, &optval, &optlen); + rv = zsock_getsockopt(sock1, SOL_SOCKET, SO_PROTOCOL, &optval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, IPPROTO_TLS_1_2, "getsockopt got invalid protocol"); zassert_equal(optlen, sizeof(optval), "getsockopt got invalid size"); - rv = getsockopt(sock2, SOL_SOCKET, SO_PROTOCOL, &optval, &optlen); + rv = zsock_getsockopt(sock2, SOL_SOCKET, SO_PROTOCOL, &optval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, IPPROTO_TLS_1_1, "getsockopt got invalid protocol"); @@ -357,7 +357,7 @@ static void test_prepare_dtls_connection(sa_family_t family) sizeof(struct sockaddr_in); struct connect_data test_data; int role = TLS_DTLS_ROLE_SERVER; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; uint8_t rx_buf; int ret; @@ -380,7 +380,7 @@ static void test_prepare_dtls_connection(sa_family_t family) test_config_psk(s_sock, c_sock); - zassert_equal(setsockopt(s_sock, SOL_TLS, TLS_DTLS_ROLE, + zassert_equal(zsock_setsockopt(s_sock, SOL_TLS, TLS_DTLS_ROLE, &role, sizeof(role)), 0, "setsockopt() failed"); @@ -396,12 +396,12 @@ static void test_prepare_dtls_connection(sa_family_t family) * unblock poll(). */ fds[0].fd = s_sock; - fds[0].events = POLLIN; - ret = poll(fds, 1, 1000); + fds[0].events = ZSOCK_POLLIN; + ret = zsock_poll(fds, 1, 1000); zassert_equal(ret, 1, "poll() did not report data ready"); /* Flush the dummy byte. */ - ret = recv(s_sock, &rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(s_sock, &rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, sizeof(rx_buf), "recv() failed"); test_work_wait(&test_data.work); @@ -431,7 +431,7 @@ ZTEST(net_socket_tls, test_v4_msg_waitall) test_msg_waitall_tx_work_handler); test_work_reschedule(&test_data.tx_work, K_MSEC(10)); - ret = recv(new_sock, rx_buf, sizeof(rx_buf), MSG_WAITALL); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_WAITALL); zassert_equal(ret, sizeof(rx_buf), "Invalid length received"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, sizeof(rx_buf), "Invalid data received"); @@ -440,8 +440,8 @@ ZTEST(net_socket_tls, test_v4_msg_waitall) /* MSG_WAITALL + SO_RCVTIMEO - make sure recv returns the amount of data * received so far */ - ret = setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, - sizeof(timeo_optval)); + ret = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, + sizeof(timeo_optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); memset(rx_buf, 0, sizeof(rx_buf)); @@ -452,7 +452,7 @@ ZTEST(net_socket_tls, test_v4_msg_waitall) test_msg_waitall_tx_work_handler); test_work_reschedule(&test_data.tx_work, K_MSEC(10)); - ret = recv(new_sock, rx_buf, sizeof(rx_buf) - 1, MSG_WAITALL); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf) - 1, ZSOCK_MSG_WAITALL); zassert_equal(ret, sizeof(rx_buf) - 1, "Invalid length received"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, sizeof(rx_buf) - 1, "Invalid data received"); @@ -487,7 +487,7 @@ ZTEST(net_socket_tls, test_v6_msg_waitall) test_msg_waitall_tx_work_handler); test_work_reschedule(&test_data.tx_work, K_MSEC(10)); - ret = recv(new_sock, rx_buf, sizeof(rx_buf), MSG_WAITALL); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_WAITALL); zassert_equal(ret, sizeof(rx_buf), "Invalid length received"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, sizeof(rx_buf), "Invalid data received"); @@ -496,8 +496,8 @@ ZTEST(net_socket_tls, test_v6_msg_waitall) /* MSG_WAITALL + SO_RCVTIMEO - make sure recv returns the amount of data * received so far */ - ret = setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, - sizeof(timeo_optval)); + ret = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVTIMEO, &timeo_optval, + sizeof(timeo_optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); memset(rx_buf, 0, sizeof(rx_buf)); @@ -508,7 +508,7 @@ ZTEST(net_socket_tls, test_v6_msg_waitall) test_msg_waitall_tx_work_handler); test_work_reschedule(&test_data.tx_work, K_MSEC(10)); - ret = recv(new_sock, rx_buf, sizeof(rx_buf) - 1, MSG_WAITALL); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf) - 1, ZSOCK_MSG_WAITALL); zassert_equal(ret, sizeof(rx_buf) - 1, "Invalid length received"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, sizeof(rx_buf) - 1, "Invalid data received"); @@ -553,13 +553,13 @@ void test_msg_trunc(sa_family_t family) test_work_reschedule(&test_data.tx_work, K_MSEC(10)); memset(rx_buf, 0, sizeof(rx_buf)); - rv = recv(s_sock, rx_buf, 2, ZSOCK_MSG_TRUNC); + rv = zsock_recv(s_sock, rx_buf, 2, ZSOCK_MSG_TRUNC); zassert_equal(rv, sizeof(TEST_STR_SMALL) - 1, "MSG_TRUNC flag failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, 2, "invalid rx data"); zassert_equal(rx_buf[2], 0, "received more than requested"); /* The remaining data should've been discarded */ - rv = recv(s_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + rv = zsock_recv(s_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(rv, -1, "consecutive recv should've failed"); zassert_equal(errno, EAGAIN, "incorrect errno value"); @@ -628,7 +628,7 @@ static void test_dtls_sendmsg_no_buf(sa_family_t family) test_work_reschedule(&test_data.tx_work, K_MSEC(10)); memset(rx_buf, 0, sizeof(rx_buf)); - rv = recv(s_sock, rx_buf, sizeof(rx_buf), 0); + rv = zsock_recv(s_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(rv, sizeof(TEST_STR_SMALL) - 1, "recv failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, sizeof(TEST_STR_SMALL) - 1, "invalid rx data"); @@ -642,7 +642,7 @@ static void test_dtls_sendmsg_no_buf(sa_family_t family) test_work_reschedule(&test_data.tx_work, K_MSEC(10)); memset(rx_buf, 0, sizeof(rx_buf)); - rv = recv(s_sock, rx_buf, sizeof(rx_buf), 0); + rv = zsock_recv(s_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(rv, sizeof(TEST_STR_SMALL) - 1, "recv failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, sizeof(TEST_STR_SMALL) - 1, "invalid rx data"); @@ -653,7 +653,7 @@ static void test_dtls_sendmsg_no_buf(sa_family_t family) iov[0].iov_base = TEST_STR_SMALL; iov[0].iov_len = sizeof(TEST_STR_SMALL) - 1; - rv = sendmsg(c_sock, &msg, 0); + rv = zsock_sendmsg(c_sock, &msg, 0); zassert_equal(rv, -1, "sendmsg succeeded"); zassert_equal(errno, EMSGSIZE, "incorrect errno value"); @@ -716,7 +716,7 @@ static void test_dtls_sendmsg(sa_family_t family) test_work_reschedule(&test_data.tx_work, K_NO_WAIT); memset(buf, 0, sizeof(buf)); - rv = recv(s_sock, buf, sizeof(buf), 0); + rv = zsock_recv(s_sock, buf, sizeof(buf), 0); zassert_equal(rv, sizeof(expected_str) - 1, "recv failed"); zassert_mem_equal(buf, expected_str, sizeof(expected_str) - 1, "invalid rx data"); @@ -734,7 +734,7 @@ static void test_dtls_sendmsg(sa_family_t family) test_work_reschedule(&test_data.tx_work, K_NO_WAIT); memset(buf, 0, sizeof(buf)); - rv = recv(s_sock, buf, sizeof(buf), 0); + rv = zsock_recv(s_sock, buf, sizeof(buf), 0); zassert_equal(rv, sizeof(expected_str) - 1, "recv failed"); zassert_mem_equal(buf, expected_str, sizeof(expected_str) - 1, "invalid rx data"); @@ -756,7 +756,7 @@ static void test_dtls_sendmsg(sa_family_t family) k_msleep(10); memset(buf, 0, sizeof(buf)); - rv = recv(s_sock, buf, sizeof(buf), 0); + rv = zsock_recv(s_sock, buf, sizeof(buf), 0); zassert_equal(rv, sizeof(buf), "recv failed"); for (int i = 0; i < sizeof(buf); i++) { zassert_equal(buf[i], 'a', "invalid rx data"); @@ -773,7 +773,7 @@ static void test_dtls_sendmsg(sa_family_t family) msg.msg_iov = iov; msg.msg_iovlen = 2; - rv = sendmsg(c_sock, &msg, 0); + rv = zsock_sendmsg(c_sock, &msg, 0); zassert_equal(rv, -1, "sendmsg succeeded"); zassert_equal(errno, EMSGSIZE, "incorrect errno value"); @@ -811,7 +811,7 @@ static void close_work(struct k_work *work) struct k_work_delayable *dwork = k_work_delayable_from_work(work); struct close_data *data = CONTAINER_OF(dwork, struct close_data, work); - close(*data->fd); + zsock_close(*data->fd); *data->fd = -1; } @@ -837,7 +837,7 @@ ZTEST(net_socket_tls, test_close_while_accept) /* Start blocking accept(), which should be unblocked by close() from * another thread and return an error. */ - new_sock = accept(s_sock, &addr, &addrlen); + new_sock = zsock_accept(s_sock, &addr, &addrlen); zassert_equal(new_sock, -1, "accept did not return error"); zassert_equal(errno, EINTR, "Unexpected errno value: %d", errno); @@ -857,7 +857,7 @@ ZTEST(net_socket_tls, test_close_while_recv) close_work_data.fd = &new_sock; test_work_reschedule(&close_work_data.work, K_MSEC(10)); - ret = recv(new_sock, &rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, &rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, -1, "recv did not return error"); zassert_equal(errno, EINTR, "Unexpected errno value: %d", errno); @@ -885,8 +885,8 @@ ZTEST(net_socket_tls, test_connect_timeout) loopback_set_packet_drop_ratio(1.0f); - zassert_equal(connect(c_sock, (struct sockaddr *)&s_saddr, - sizeof(s_saddr)), + zassert_equal(zsock_connect(c_sock, (struct sockaddr *)&s_saddr, + sizeof(s_saddr)), -1, "connect succeed"); zassert_equal(errno, ETIMEDOUT, "connect should be timed out, got %d", errno); @@ -912,8 +912,8 @@ ZTEST(net_socket_tls, test_connect_closed_port) ret = zsock_inet_pton(AF_INET6, MY_IPV6_ADDR, &s_saddr.sin6_addr); zassert_equal(ret, 1, "inet_pton failed"); - zassert_equal(connect(c_sock, (struct sockaddr *)&s_saddr, - sizeof(s_saddr)), + zassert_equal(zsock_connect(c_sock, (struct sockaddr *)&s_saddr, + sizeof(s_saddr)), -1, "connect succeed"); zassert_equal(errno, ETIMEDOUT, "connect should fail, got %d", errno); @@ -948,12 +948,12 @@ static void fake_tcp_server_work(struct k_work *work) int ret; char rx_buf[32]; - ret = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); if (ret <= 0) { break; } - (void)send(new_sock, TEST_STR_SMALL, sizeof(TEST_STR_SMALL), 0); + (void)zsock_send(new_sock, TEST_STR_SMALL, sizeof(TEST_STR_SMALL), 0); } out: @@ -998,8 +998,8 @@ ZTEST(net_socket_tls, test_connect_invalid_handshake_data) test_prepare_fake_tcp_server(&server_data, AF_INET6, &s_sock, (struct sockaddr *)&s_saddr, true); - zassert_equal(connect(c_sock, (struct sockaddr *)&s_saddr, - sizeof(s_saddr)), + zassert_equal(zsock_connect(c_sock, (struct sockaddr *)&s_saddr, + sizeof(s_saddr)), -1, "connect succeed"); zassert_equal(errno, ECONNABORTED, "connect should fail, got %d", errno); @@ -1025,8 +1025,8 @@ ZTEST(net_socket_tls, test_connect_no_handshake_data) test_prepare_fake_tcp_server(&server_data, AF_INET6, &s_sock, (struct sockaddr *)&s_saddr, false); - zassert_equal(connect(c_sock, (struct sockaddr *)&s_saddr, - sizeof(s_saddr)), + zassert_equal(zsock_connect(c_sock, (struct sockaddr *)&s_saddr, + sizeof(s_saddr)), -1, "connect succeed"); zassert_equal(errno, ECONNABORTED, "connect should fail, got %d", errno); @@ -1051,7 +1051,7 @@ ZTEST(net_socket_tls, test_accept_non_block) test_listen(s_sock); timestamp = k_uptime_get_32(); - new_sock = accept(s_sock, NULL, NULL); + new_sock = zsock_accept(s_sock, NULL, NULL); zassert_true(k_uptime_get_32() - timestamp <= 100, ""); zassert_equal(new_sock, -1, "accept did not return error"); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); @@ -1076,7 +1076,7 @@ ZTEST(net_socket_tls, test_accept_invalid_handshake_data) test_connect(c_sock, (struct sockaddr *)&s_saddr, sizeof(s_saddr)); test_send(c_sock, TEST_STR_SMALL, sizeof(TEST_STR_SMALL), 0); - new_sock = accept(s_sock, NULL, NULL); + new_sock = zsock_accept(s_sock, NULL, NULL); zassert_equal(new_sock, -1, "accept did not return error"); zassert_equal(errno, ECONNABORTED, "Unexpected errno value: %d", errno); @@ -1091,29 +1091,29 @@ ZTEST(net_socket_tls, test_recv_non_block) test_prepare_tls_connection(AF_INET6); /* Verify ZSOCK_MSG_DONTWAIT flag first */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(ret, -1, "recv()) should've failed"); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); /* Verify fcntl and O_NONBLOCK */ test_fcntl(new_sock, F_SETFL, O_NONBLOCK); - ret = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, -1, "recv() should've failed"); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); - ret = send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "send() failed"); /* Let the data got through. */ k_sleep(K_MSEC(10)); /* Should get data now */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "recv() failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, ret, "Invalid data received"); /* And EAGAIN on consecutive read */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, -1, "recv() should've failed"); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); @@ -1138,7 +1138,7 @@ ZTEST(net_socket_tls, test_recv_block) test_work_reschedule(&test_data.tx_work, K_MSEC(10)); /* recv() shall block until send work sends the data. */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, sizeof(TEST_STR_SMALL) - 1, "recv() failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, ret, "Invalid data received"); @@ -1173,12 +1173,12 @@ ZTEST(net_socket_tls, test_send_non_block) test_prepare_tls_connection(AF_INET6); /* Simulate window full scenario with SO_RCVBUF option. */ - ret = setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, - sizeof(buf_optval)); + ret = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, + sizeof(buf_optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); /* Fill out the window */ - ret = send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "send() failed"); /* Wait for ACK (empty window, min. 100 ms due to silly window @@ -1187,18 +1187,18 @@ ZTEST(net_socket_tls, test_send_non_block) k_sleep(K_MSEC(150)); /* Verify ZSOCK_MSG_DONTWAIT flag first */ - ret = send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), - ZSOCK_MSG_DONTWAIT); + ret = zsock_send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), + ZSOCK_MSG_DONTWAIT); zassert_equal(ret, -1, "send() should've failed"); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); /* Verify fcntl and O_NONBLOCK */ test_fcntl(c_sock, F_SETFL, O_NONBLOCK); - ret = send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); zassert_equal(ret, -1, "send() should've failed"); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); - ret = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "recv() failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, ret, "Invalid data received"); @@ -1206,16 +1206,16 @@ ZTEST(net_socket_tls, test_send_non_block) k_sleep(K_MSEC(10)); /* Should succeed now. */ - ret = send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "send() failed"); /* Flush the data */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "recv() failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, ret, "Invalid data received"); /* And make sure there's no more data left. */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(ret, -1, "recv() should've failed"); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); @@ -1242,7 +1242,7 @@ static void recv_work_handler(struct k_work *work) while (off < test_data->datalen) { size_t recvlen = MIN(sizeof(rx_buf), test_data->datalen - off); - ret = recv(test_data->sock, rx_buf, recvlen, 0); + ret = zsock_recv(test_data->sock, rx_buf, recvlen, 0); zassert_true(ret > 0, "recv() error"); zassert_mem_equal(rx_buf, test_data->data + off, ret, "unexpected data"); @@ -1266,12 +1266,12 @@ ZTEST(net_socket_tls, test_send_block) test_prepare_tls_connection(AF_INET6); /* Simulate window full scenario with SO_RCVBUF option. */ - ret = setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, - sizeof(buf_optval)); + ret = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, + sizeof(buf_optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); /* Fill out the window */ - ret = send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "send() failed"); /* Wait for ACK (empty window, min. 100 ms due to silly window @@ -1284,16 +1284,16 @@ ZTEST(net_socket_tls, test_send_block) test_work_reschedule(&test_data.work, K_MSEC(10)); /* Should block and succeed. */ - ret = send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "send() failed"); /* Flush the data */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "recv() failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, ret, "Invalid data received"); /* And make sure there's no more data left. */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(ret, -1, "recv() should've failed"); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); @@ -1316,13 +1316,13 @@ ZTEST(net_socket_tls, test_send_on_close) k_msleep(10); /* Verify send() reports an error after connection is closed. */ - ret = send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); zassert_equal(ret, -1, "send() should've failed"); zassert_equal(errno, ECONNABORTED, "Unexpected errno value: %d", errno); - /* send() on closed connection marked error on a socket. */ - ret = recv(c_sock, rx_buf, sizeof(rx_buf), 0); - zassert_equal(ret, -1, "send() should've failed"); + /* recv() on closed connection marked error on a socket. */ + ret = zsock_recv(c_sock, rx_buf, sizeof(rx_buf), 0); + zassert_equal(ret, -1, "recv() should've failed"); zassert_equal(errno, ECONNABORTED, "Unexpected errno value: %d", errno); test_sockets_close(); @@ -1338,11 +1338,11 @@ ZTEST(net_socket_tls, test_send_on_close) k_msleep(10); /* Graceful connection close should be reported first. */ - ret = recv(c_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(c_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, 0, "recv() should've reported connection close"); /* And consecutive send() should fail. */ - ret = send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); zassert_equal(ret, -1, "send() should've failed"); zassert_equal(errno, ECONNABORTED, "Unexpected errno value: %d", errno); @@ -1367,12 +1367,12 @@ ZTEST(net_socket_tls, test_so_rcvtimeo) test_prepare_tls_connection(AF_INET6); - ret = setsockopt(c_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, - sizeof(optval)); + ret = zsock_setsockopt(c_sock, SOL_SOCKET, SO_RCVTIMEO, &optval, + sizeof(optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); start_time = k_uptime_get_32(); - ret = recv(c_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(c_sock, rx_buf, sizeof(rx_buf), 0); time_diff = k_uptime_get_32() - start_time; zassert_equal(ret, -1, "recv() should've failed"); @@ -1385,7 +1385,7 @@ ZTEST(net_socket_tls, test_so_rcvtimeo) test_work_reschedule(&test_data.tx_work, K_MSEC(10)); /* recv() shall return as soon as it gets data, regardless of timeout. */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, sizeof(TEST_STR_SMALL) - 1, "recv() failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, ret, "Invalid data received"); @@ -1410,16 +1410,16 @@ ZTEST(net_socket_tls, test_so_sndtimeo) test_prepare_tls_connection(AF_INET6); - ret = setsockopt(c_sock, SOL_SOCKET, SO_SNDTIMEO, &timeo_optval, - sizeof(timeo_optval)); + ret = zsock_setsockopt(c_sock, SOL_SOCKET, SO_SNDTIMEO, &timeo_optval, + sizeof(timeo_optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); /* Simulate window full scenario with SO_RCVBUF option. */ - ret = setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, - sizeof(buf_optval)); + ret = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, + sizeof(buf_optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); - ret = send(c_sock, TEST_STR_SMALL, sizeof(TEST_STR_SMALL) - 1, 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, sizeof(TEST_STR_SMALL) - 1, 0); zassert_equal(ret, sizeof(TEST_STR_SMALL) - 1, "send() failed"); /* Wait for ACK (empty window). */ @@ -1427,7 +1427,7 @@ ZTEST(net_socket_tls, test_so_sndtimeo) /* Client should not be able to send now and time out after SO_SNDTIMEO */ start_time = k_uptime_get_32(); - ret = send(c_sock, TEST_STR_SMALL, sizeof(TEST_STR_SMALL) - 1, 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, sizeof(TEST_STR_SMALL) - 1, 0); time_diff = k_uptime_get_32() - start_time; zassert_equal(ret, -1, "send() should've failed"); @@ -1440,7 +1440,7 @@ ZTEST(net_socket_tls, test_so_sndtimeo) test_work_reschedule(&test_data.work, K_MSEC(10)); /* Should block and succeed. */ - ret = send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "send() failed"); test_sockets_close(); @@ -1475,7 +1475,7 @@ static void shutdown_work(struct k_work *work) struct shutdown_data *data = CONTAINER_OF(dwork, struct shutdown_data, work); - shutdown(data->sock, data->how); + zsock_shutdown(data->sock, data->how); } ZTEST(net_socket_tls, test_shutdown_rd_while_recv) @@ -1525,12 +1525,12 @@ ZTEST(net_socket_tls, test_send_while_recv) /* recv() shall block until the second work is executed. The second work * will execute only if the first one won't block. */ - ret = recv(c_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(c_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, sizeof(TEST_STR_SMALL) - 1, "recv() failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, ret, "Invalid data received"); /* Check if the server sock got its data. */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), 0); zassert_equal(ret, sizeof(TEST_STR_SMALL) - 1, "recv() failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, ret, "Invalid data received"); @@ -1543,25 +1543,25 @@ ZTEST(net_socket_tls, test_poll_tls_pollin) { uint8_t rx_buf[sizeof(TEST_STR_SMALL) - 1]; int ret; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; test_prepare_tls_connection(AF_INET6); fds[0].fd = new_sock; - fds[0].events = POLLIN; + fds[0].events = ZSOCK_POLLIN; - ret = poll(fds, 1, 0); + ret = zsock_poll(fds, 1, 0); zassert_equal(ret, 0, "Unexpected poll() event"); - ret = send(c_sock, TEST_STR_SMALL, sizeof(TEST_STR_SMALL) - 1, 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, sizeof(TEST_STR_SMALL) - 1, 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "send() failed"); - ret = poll(fds, 1, 100); + ret = zsock_poll(fds, 1, 100); zassert_equal(ret, 1, "poll() should've report event"); - zassert_equal(fds[0].revents, POLLIN, "No POLLIN event"); + zassert_equal(fds[0].revents, ZSOCK_POLLIN, "No POLLIN event"); /* Check that data is really available */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(ret, sizeof(TEST_STR_SMALL) - 1, "recv() failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, ret, "Invalid data received"); @@ -1578,26 +1578,26 @@ ZTEST(net_socket_tls, test_poll_dtls_pollin) .datalen = sizeof(TEST_STR_SMALL) - 1 }; int ret; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; test_prepare_dtls_connection(AF_INET6); fds[0].fd = s_sock; - fds[0].events = POLLIN; + fds[0].events = ZSOCK_POLLIN; - ret = poll(fds, 1, 0); + ret = zsock_poll(fds, 1, 0); zassert_equal(ret, 0, "Unexpected poll() event"); test_data.sock = c_sock; k_work_init_delayable(&test_data.tx_work, send_work_handler); test_work_reschedule(&test_data.tx_work, K_NO_WAIT); - ret = poll(fds, 1, 100); + ret = zsock_poll(fds, 1, 100); zassert_equal(ret, 1, "poll() should've report event"); - zassert_equal(fds[0].revents, POLLIN, "No POLLIN event"); + zassert_equal(fds[0].revents, ZSOCK_POLLIN, "No POLLIN event"); /* Check that data is really available */ - ret = recv(s_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + ret = zsock_recv(s_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(ret, sizeof(TEST_STR_SMALL) - 1, "recv() failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, ret, "Invalid data received"); @@ -1612,24 +1612,24 @@ ZTEST(net_socket_tls, test_poll_tls_pollout) int buf_optval = TLS_RECORD_OVERHEAD + sizeof(TEST_STR_SMALL) - 1; uint8_t rx_buf[sizeof(TEST_STR_SMALL) - 1]; int ret; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; test_prepare_tls_connection(AF_INET6); fds[0].fd = c_sock; - fds[0].events = POLLOUT; + fds[0].events = ZSOCK_POLLOUT; - ret = poll(fds, 1, 0); + ret = zsock_poll(fds, 1, 0); zassert_equal(ret, 1, "poll() should've report event"); - zassert_equal(fds[0].revents, POLLOUT, "No POLLOUT event"); + zassert_equal(fds[0].revents, ZSOCK_POLLOUT, "No POLLOUT event"); /* Simulate window full scenario with SO_RCVBUF option. */ - ret = setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, - sizeof(buf_optval)); + ret = zsock_setsockopt(new_sock, SOL_SOCKET, SO_RCVBUF, &buf_optval, + sizeof(buf_optval)); zassert_equal(ret, 0, "setsockopt failed (%d)", errno); /* Fill out the window */ - ret = send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); + ret = zsock_send(c_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), 0); zassert_equal(ret, strlen(TEST_STR_SMALL), "send() failed"); /* Wait for ACK (empty window, min. 100 ms due to silly window @@ -1638,17 +1638,17 @@ ZTEST(net_socket_tls, test_poll_tls_pollout) k_sleep(K_MSEC(150)); /* poll() shouldn't report POLLOUT now */ - ret = poll(fds, 1, 0); + ret = zsock_poll(fds, 1, 0); zassert_equal(ret, 0, "Unexpected poll() event"); /* Consume the data, and check if the client sock is writeable again */ - ret = recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + ret = zsock_recv(new_sock, rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(ret, sizeof(TEST_STR_SMALL) - 1, "recv() failed"); zassert_mem_equal(rx_buf, TEST_STR_SMALL, ret, "Invalid data received"); - ret = poll(fds, 1, 100); + ret = zsock_poll(fds, 1, 100); zassert_equal(ret, 1, "poll() should've report event"); - zassert_equal(fds[0].revents, POLLOUT, "No POLLOUT event"); + zassert_equal(fds[0].revents, ZSOCK_POLLOUT, "No POLLOUT event"); test_sockets_close(); @@ -1657,18 +1657,18 @@ ZTEST(net_socket_tls, test_poll_tls_pollout) ZTEST(net_socket_tls, test_poll_dtls_pollout) { - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; int ret; test_prepare_dtls_connection(AF_INET6); fds[0].fd = c_sock; - fds[0].events = POLLOUT; + fds[0].events = ZSOCK_POLLOUT; /* DTLS socket should always be writeable. */ - ret = poll(fds, 1, 0); + ret = zsock_poll(fds, 1, 0); zassert_equal(ret, 1, "poll() should've report event"); - zassert_equal(fds[0].revents, POLLOUT, "No POLLOUT event"); + zassert_equal(fds[0].revents, ZSOCK_POLLOUT, "No POLLOUT event"); test_sockets_close(); @@ -1678,25 +1678,25 @@ ZTEST(net_socket_tls, test_poll_dtls_pollout) ZTEST(net_socket_tls, test_poll_tls_pollhup) { - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; uint8_t rx_buf; int ret; test_prepare_tls_connection(AF_INET6); fds[0].fd = new_sock; - fds[0].events = POLLIN; + fds[0].events = ZSOCK_POLLIN; test_close(c_sock); c_sock = -1; - ret = poll(fds, 1, 100); + ret = zsock_poll(fds, 1, 100); zassert_equal(ret, 1, "poll() should've report event"); - zassert_true(fds[0].revents & POLLIN, "No POLLIN event"); - zassert_true(fds[0].revents & POLLHUP, "No POLLHUP event"); + zassert_true(fds[0].revents & ZSOCK_POLLIN, "No POLLIN event"); + zassert_true(fds[0].revents & ZSOCK_POLLHUP, "No POLLHUP event"); /* Check that connection was indeed closed */ - ret = recv(new_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + ret = zsock_recv(new_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(ret, 0, "recv() did not report connection close"); test_sockets_close(); @@ -1706,24 +1706,24 @@ ZTEST(net_socket_tls, test_poll_tls_pollhup) ZTEST(net_socket_tls, test_poll_dtls_pollhup) { - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; uint8_t rx_buf; int ret; test_prepare_dtls_connection(AF_INET6); fds[0].fd = s_sock; - fds[0].events = POLLIN; + fds[0].events = ZSOCK_POLLIN; test_close(c_sock); c_sock = -1; - ret = poll(fds, 1, 100); + ret = zsock_poll(fds, 1, 100); zassert_equal(ret, 1, "poll() should've report event"); - zassert_equal(fds[0].revents, POLLHUP, "No POLLHUP event"); + zassert_equal(fds[0].revents, ZSOCK_POLLHUP, "No POLLHUP event"); /* Check that connection was indeed closed */ - ret = recv(s_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + ret = zsock_recv(s_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(ret, -1, "recv() should report EAGAIN"); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); @@ -1739,7 +1739,7 @@ ZTEST(net_socket_tls, test_poll_tls_pollerr) { uint8_t rx_buf; int ret; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; int optval; socklen_t optlen = sizeof(optval); mbedtls_ssl_context *ssl_ctx; @@ -1747,23 +1747,23 @@ ZTEST(net_socket_tls, test_poll_tls_pollerr) test_prepare_tls_connection(AF_INET6); fds[0].fd = new_sock; - fds[0].events = POLLIN; + fds[0].events = ZSOCK_POLLIN; /* Get access to the underlying ssl context, and send alert. */ ssl_ctx = ztls_get_mbedtls_ssl_context(c_sock); mbedtls_ssl_send_alert_message(ssl_ctx, MBEDTLS_SSL_ALERT_LEVEL_FATAL, MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR); - ret = poll(fds, 1, 100); + ret = zsock_poll(fds, 1, 100); zassert_equal(ret, 1, "poll() should've report event"); - zassert_true(fds[0].revents & POLLERR, "No POLLERR event"); + zassert_true(fds[0].revents & ZSOCK_POLLERR, "No POLLERR event"); - ret = getsockopt(new_sock, SOL_SOCKET, SO_ERROR, &optval, &optlen); + ret = zsock_getsockopt(new_sock, SOL_SOCKET, SO_ERROR, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, ECONNABORTED, "getsockopt got invalid error %d", optval); - ret = recv(new_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + ret = zsock_recv(new_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(ret, -1, "recv() did not report error"); zassert_equal(errno, ECONNABORTED, "Unexpected errno value: %d", errno); @@ -1776,7 +1776,7 @@ ZTEST(net_socket_tls, test_poll_dtls_pollerr) { uint8_t rx_buf; int ret; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; int optval; socklen_t optlen = sizeof(optval); mbedtls_ssl_context *ssl_ctx; @@ -1784,24 +1784,24 @@ ZTEST(net_socket_tls, test_poll_dtls_pollerr) test_prepare_dtls_connection(AF_INET6); fds[0].fd = s_sock; - fds[0].events = POLLIN; + fds[0].events = ZSOCK_POLLIN; /* Get access to the underlying ssl context, and send alert. */ ssl_ctx = ztls_get_mbedtls_ssl_context(c_sock); mbedtls_ssl_send_alert_message(ssl_ctx, MBEDTLS_SSL_ALERT_LEVEL_FATAL, MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR); - ret = poll(fds, 1, 100); + ret = zsock_poll(fds, 1, 100); zassert_equal(ret, 1, "poll() should've report event"); - zassert_true(fds[0].revents & POLLERR, "No POLLERR event"); + zassert_true(fds[0].revents & ZSOCK_POLLERR, "No POLLERR event"); - ret = getsockopt(s_sock, SOL_SOCKET, SO_ERROR, &optval, &optlen); + ret = zsock_getsockopt(s_sock, SOL_SOCKET, SO_ERROR, &optval, &optlen); zassert_equal(ret, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, ECONNABORTED, "getsockopt got invalid error %d", optval); /* DTLS server socket should recover and be ready to accept new session. */ - ret = recv(s_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); + ret = zsock_recv(s_sock, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(ret, -1, "recv() did not report error"); zassert_equal(errno, EAGAIN, "Unexpected errno value: %d", errno); diff --git a/tests/net/socket/udp/prj.conf b/tests/net/socket/udp/prj.conf index 1a376bb84d2..aed6c930882 100644 --- a/tests/net/socket/udp/prj.conf +++ b/tests/net/socket/udp/prj.conf @@ -7,7 +7,6 @@ CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y CONFIG_NET_UDP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_POSIX_MAX_FDS=10 CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=3 CONFIG_NET_IPV6_DAD=n diff --git a/tests/net/socket/udp/src/main.c b/tests/net/socket/udp/src/main.c index 566ed3934f5..3046630906d 100644 --- a/tests/net/socket/udp/src/main.c +++ b/tests/net/socket/udp/src/main.c @@ -78,21 +78,21 @@ static void comm_sendto_recvfrom(int client_sock, * Test client -> server sending */ - sent = sendto(client_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), - 0, server_addr, server_addrlen); + sent = zsock_sendto(client_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), + 0, server_addr, server_addrlen); zassert_equal(sent, strlen(TEST_STR_SMALL), "sendto failed"); k_msleep(100); avail = 42; - zassert_ok(ioctl(server_sock, ZFD_IOCTL_FIONREAD, &avail)); + zassert_ok(zsock_ioctl(server_sock, ZFD_IOCTL_FIONREAD, &avail)); zassert_equal(avail, strlen(TEST_STR_SMALL)); /* Test recvfrom(MSG_PEEK) */ addrlen = sizeof(addr); clear_buf(rx_buf); - recved = recvfrom(server_sock, rx_buf, sizeof(rx_buf), - MSG_PEEK, &addr, &addrlen); + recved = zsock_recvfrom(server_sock, rx_buf, sizeof(rx_buf), + ZSOCK_MSG_PEEK, &addr, &addrlen); zassert_true(recved >= 0, "recvfrom fail"); zassert_equal(recved, strlen(TEST_STR_SMALL), "unexpected received bytes"); @@ -102,8 +102,8 @@ static void comm_sendto_recvfrom(int client_sock, /* Test normal recvfrom() */ addrlen = sizeof(addr); clear_buf(rx_buf); - recved = recvfrom(server_sock, rx_buf, sizeof(rx_buf), - 0, &addr, &addrlen); + recved = zsock_recvfrom(server_sock, rx_buf, sizeof(rx_buf), + 0, &addr, &addrlen); zassert_true(recved >= 0, "recvfrom fail"); zassert_equal(recved, strlen(TEST_STR_SMALL), "unexpected received bytes"); @@ -121,15 +121,15 @@ static void comm_sendto_recvfrom(int client_sock, * Test server -> client sending */ - sent = sendto(server_sock, BUF_AND_SIZE(TEST_STR2), - 0, &addr, addrlen); + sent = zsock_sendto(server_sock, BUF_AND_SIZE(TEST_STR2), + 0, &addr, addrlen); zassert_equal(sent, STRLEN(TEST_STR2), "sendto failed"); /* Test normal recvfrom() */ addrlen2 = sizeof(addr); clear_buf(rx_buf); - recved = recvfrom(client_sock, rx_buf, sizeof(rx_buf), - 0, &addr2, &addrlen2); + recved = zsock_recvfrom(client_sock, rx_buf, sizeof(rx_buf), + 0, &addr2, &addrlen2); zassert_true(recved >= 0, "recvfrom fail"); zassert_equal(recved, STRLEN(TEST_STR2), "unexpected received bytes"); @@ -144,24 +144,24 @@ static void comm_sendto_recvfrom(int client_sock, /* Test that unleft leftover data from datagram is discarded. */ /* Send 2 datagrams */ - sent = sendto(server_sock, BUF_AND_SIZE(TEST_STR2), - 0, &addr, addrlen); + sent = zsock_sendto(server_sock, BUF_AND_SIZE(TEST_STR2), + 0, &addr, addrlen); zassert_equal(sent, STRLEN(TEST_STR2), "sendto failed"); - sent = sendto(server_sock, BUF_AND_SIZE(TEST_STR_SMALL), - 0, &addr, addrlen); + sent = zsock_sendto(server_sock, BUF_AND_SIZE(TEST_STR_SMALL), + 0, &addr, addrlen); zassert_equal(sent, STRLEN(TEST_STR_SMALL), "sendto failed"); /* Receive just beginning of 1st datagram */ addrlen2 = sizeof(addr); clear_buf(rx_buf); - recved = recvfrom(client_sock, rx_buf, 16, 0, &addr2, &addrlen2); + recved = zsock_recvfrom(client_sock, rx_buf, 16, 0, &addr2, &addrlen2); zassert_true(recved == 16, "recvfrom fail"); zassert_mem_equal(rx_buf, TEST_STR2, 16, "wrong data"); /* Make sure that now we receive 2nd datagram */ addrlen2 = sizeof(addr); clear_buf(rx_buf); - recved = recvfrom(client_sock, rx_buf, 16, 0, &addr2, &addrlen2); + recved = zsock_recvfrom(client_sock, rx_buf, 16, 0, &addr2, &addrlen2); zassert_true(recved == STRLEN(TEST_STR_SMALL), "recvfrom fail"); zassert_mem_equal(rx_buf, BUF_AND_SIZE(TEST_STR_SMALL), "wrong data"); } @@ -177,9 +177,9 @@ ZTEST(net_socket_udp, test_02_v4_sendto_recvfrom) prepare_sock_udp_v4(MY_IPV4_ADDR, ANY_PORT, &client_sock, &client_addr); prepare_sock_udp_v4(MY_IPV4_ADDR, SERVER_PORT, &server_sock, &server_addr); - rv = bind(server_sock, - (struct sockaddr *)&server_addr, - sizeof(server_addr)); + rv = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, + sizeof(server_addr)); zassert_equal(rv, 0, "bind failed"); comm_sendto_recvfrom(client_sock, @@ -189,9 +189,9 @@ ZTEST(net_socket_udp, test_02_v4_sendto_recvfrom) (struct sockaddr *)&server_addr, sizeof(server_addr)); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } @@ -206,8 +206,8 @@ ZTEST(net_socket_udp, test_03_v6_sendto_recvfrom) prepare_sock_udp_v6(MY_IPV6_ADDR, ANY_PORT, &client_sock, &client_addr); prepare_sock_udp_v6(MY_IPV6_ADDR, SERVER_PORT, &server_sock, &server_addr); - rv = bind(server_sock, - (struct sockaddr *)&server_addr, sizeof(server_addr)); + rv = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, sizeof(server_addr)); zassert_equal(rv, 0, "bind failed"); comm_sendto_recvfrom(client_sock, @@ -217,9 +217,9 @@ ZTEST(net_socket_udp, test_03_v6_sendto_recvfrom) (struct sockaddr *)&server_addr, sizeof(server_addr)); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } @@ -234,12 +234,12 @@ ZTEST(net_socket_udp, test_04_v4_bind_sendto) prepare_sock_udp_v4(MY_IPV4_ADDR, CLIENT_PORT, &client_sock, &client_addr); prepare_sock_udp_v4(MY_IPV4_ADDR, SERVER_PORT, &server_sock, &server_addr); - rv = bind(client_sock, - (struct sockaddr *)&client_addr, sizeof(client_addr)); + rv = zsock_bind(client_sock, + (struct sockaddr *)&client_addr, sizeof(client_addr)); zassert_equal(rv, 0, "bind failed"); - rv = bind(server_sock, - (struct sockaddr *)&server_addr, sizeof(server_addr)); + rv = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, sizeof(server_addr)); zassert_equal(rv, 0, "bind failed"); comm_sendto_recvfrom(client_sock, @@ -249,9 +249,9 @@ ZTEST(net_socket_udp, test_04_v4_bind_sendto) (struct sockaddr *)&server_addr, sizeof(server_addr)); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } @@ -266,12 +266,12 @@ ZTEST(net_socket_udp, test_05_v6_bind_sendto) prepare_sock_udp_v6(MY_IPV6_ADDR, CLIENT_PORT, &client_sock, &client_addr); prepare_sock_udp_v6(MY_IPV6_ADDR, SERVER_PORT, &server_sock, &server_addr); - rv = bind(client_sock, - (struct sockaddr *)&client_addr, sizeof(client_addr)); + rv = zsock_bind(client_sock, + (struct sockaddr *)&client_addr, sizeof(client_addr)); zassert_equal(rv, 0, "bind failed"); - rv = bind(server_sock, - (struct sockaddr *)&server_addr, sizeof(server_addr)); + rv = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, sizeof(server_addr)); zassert_equal(rv, 0, "bind failed"); comm_sendto_recvfrom(client_sock, @@ -281,9 +281,9 @@ ZTEST(net_socket_udp, test_05_v6_bind_sendto) (struct sockaddr *)&server_addr, sizeof(server_addr)); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } @@ -297,28 +297,28 @@ ZTEST(net_socket_udp, test_01_send_recv_2_sock) prepare_sock_udp_v4(MY_IPV4_ADDR, 55555, &sock1, &bind_addr); prepare_sock_udp_v4(MY_IPV4_ADDR, 55555, &sock2, &conn_addr); - rv = bind(sock1, (struct sockaddr *)&bind_addr, sizeof(bind_addr)); + rv = zsock_bind(sock1, (struct sockaddr *)&bind_addr, sizeof(bind_addr)); zassert_equal(rv, 0, "bind failed"); - rv = connect(sock2, (struct sockaddr *)&conn_addr, sizeof(conn_addr)); + rv = zsock_connect(sock2, (struct sockaddr *)&conn_addr, sizeof(conn_addr)); zassert_equal(rv, 0, "connect failed"); - len = send(sock2, BUF_AND_SIZE(TEST_STR_SMALL), 0); + len = zsock_send(sock2, BUF_AND_SIZE(TEST_STR_SMALL), 0); zassert_equal(len, STRLEN(TEST_STR_SMALL), "invalid send len"); clear_buf(buf); - len = recv(sock1, buf, sizeof(buf), MSG_PEEK); + len = zsock_recv(sock1, buf, sizeof(buf), ZSOCK_MSG_PEEK); zassert_equal(len, STRLEN(TEST_STR_SMALL), "Invalid recv len"); zassert_mem_equal(buf, BUF_AND_SIZE(TEST_STR_SMALL), "Wrong data"); clear_buf(buf); - len = recv(sock1, buf, sizeof(buf), 0); + len = zsock_recv(sock1, buf, sizeof(buf), 0); zassert_equal(len, STRLEN(TEST_STR_SMALL), "Invalid recv len"); zassert_mem_equal(buf, BUF_AND_SIZE(TEST_STR_SMALL), "Wrong data"); - rv = close(sock1); + rv = zsock_close(sock1); zassert_equal(rv, 0, "close failed"); - rv = close(sock2); + rv = zsock_close(sock2); zassert_equal(rv, 0, "close failed"); } @@ -332,25 +332,25 @@ ZTEST(net_socket_udp, test_07_so_priority) prepare_sock_udp_v4(MY_IPV4_ADDR, 55555, &sock1, &bind_addr4); prepare_sock_udp_v6(MY_IPV6_ADDR, 55555, &sock2, &bind_addr6); - rv = bind(sock1, (struct sockaddr *)&bind_addr4, sizeof(bind_addr4)); + rv = zsock_bind(sock1, (struct sockaddr *)&bind_addr4, sizeof(bind_addr4)); zassert_equal(rv, 0, "bind failed"); - rv = bind(sock2, (struct sockaddr *)&bind_addr6, sizeof(bind_addr6)); + rv = zsock_bind(sock2, (struct sockaddr *)&bind_addr6, sizeof(bind_addr6)); zassert_equal(rv, 0, "bind failed"); optval = 2; - rv = setsockopt(sock1, SOL_SOCKET, SO_PRIORITY, &optval, - sizeof(optval)); + rv = zsock_setsockopt(sock1, SOL_SOCKET, SO_PRIORITY, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); optval = 8; - rv = setsockopt(sock2, SOL_SOCKET, SO_PRIORITY, &optval, - sizeof(optval)); + rv = zsock_setsockopt(sock2, SOL_SOCKET, SO_PRIORITY, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed"); - rv = close(sock1); + rv = zsock_close(sock1); zassert_equal(rv, 0, "close failed"); - rv = close(sock2); + rv = zsock_close(sock2); zassert_equal(rv, 0, "close failed"); } @@ -375,7 +375,7 @@ static void comm_sendmsg_recvfrom(int client_sock, * Test client -> server sending */ - sent = sendmsg(client_sock, client_msg, 0); + sent = zsock_sendmsg(client_sock, client_msg, 0); zassert_true(sent > 0, "sendmsg failed (%d)", -errno); for (i = 0, len = 0; i < client_msg->msg_iovlen; i++) { @@ -387,8 +387,8 @@ static void comm_sendmsg_recvfrom(int client_sock, /* Test recvfrom(MSG_PEEK) */ addrlen = sizeof(addr); clear_buf(rx_buf); - recved = recvfrom(server_sock, rx_buf, sizeof(rx_buf), - MSG_PEEK, &addr, &addrlen); + recved = zsock_recvfrom(server_sock, rx_buf, sizeof(rx_buf), + ZSOCK_MSG_PEEK, &addr, &addrlen); zassert_true(recved >= 0, "recvfrom fail"); zassert_equal(recved, strlen(TEST_STR_SMALL), "unexpected received bytes"); @@ -402,7 +402,7 @@ static void comm_sendmsg_recvfrom(int client_sock, /* Test normal recvfrom() */ addrlen = sizeof(addr); clear_buf(rx_buf); - recved = recvfrom(server_sock, rx_buf, sizeof(rx_buf), + recved = zsock_recvfrom(server_sock, rx_buf, sizeof(rx_buf), 0, &addr, &addrlen); zassert_true(recved >= 0, "recvfrom fail"); zassert_equal(recved, strlen(TEST_STR_SMALL), @@ -436,14 +436,14 @@ ZTEST_USER(net_socket_udp, test_12_v4_sendmsg_recvfrom) prepare_sock_udp_v4(MY_IPV4_ADDR, ANY_PORT, &client_sock, &client_addr); prepare_sock_udp_v4(MY_IPV4_ADDR, SERVER_PORT, &server_sock, &server_addr); - rv = bind(server_sock, - (struct sockaddr *)&server_addr, - sizeof(server_addr)); + rv = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, + sizeof(server_addr)); zassert_equal(rv, 0, "server bind failed"); - rv = bind(client_sock, - (struct sockaddr *)&client_addr, - sizeof(client_addr)); + rv = zsock_bind(client_sock, + (struct sockaddr *)&client_addr, + sizeof(client_addr)); zassert_equal(rv, 0, "client bind failed"); io_vector[0].iov_base = TEST_STR_SMALL; @@ -471,9 +471,9 @@ ZTEST_USER(net_socket_udp, test_12_v4_sendmsg_recvfrom) (struct sockaddr *)&server_addr, sizeof(server_addr)); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } @@ -490,14 +490,14 @@ ZTEST_USER(net_socket_udp, test_13_v4_sendmsg_recvfrom_no_aux_data) prepare_sock_udp_v4(MY_IPV4_ADDR, ANY_PORT, &client_sock, &client_addr); prepare_sock_udp_v4(MY_IPV4_ADDR, SERVER_PORT, &server_sock, &server_addr); - rv = bind(server_sock, - (struct sockaddr *)&server_addr, - sizeof(server_addr)); + rv = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, + sizeof(server_addr)); zassert_equal(rv, 0, "server bind failed"); - rv = bind(client_sock, - (struct sockaddr *)&client_addr, - sizeof(client_addr)); + rv = zsock_bind(client_sock, + (struct sockaddr *)&client_addr, + sizeof(client_addr)); zassert_equal(rv, 0, "client bind failed"); io_vector[0].iov_base = TEST_STR_SMALL; @@ -517,9 +517,9 @@ ZTEST_USER(net_socket_udp, test_13_v4_sendmsg_recvfrom_no_aux_data) (struct sockaddr *)&server_addr, sizeof(server_addr)); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } @@ -541,13 +541,13 @@ ZTEST_USER(net_socket_udp, test_14_v6_sendmsg_recvfrom) prepare_sock_udp_v6(MY_IPV6_ADDR, ANY_PORT, &client_sock, &client_addr); prepare_sock_udp_v6(MY_IPV6_ADDR, SERVER_PORT, &server_sock, &server_addr); - rv = bind(server_sock, - (struct sockaddr *)&server_addr, sizeof(server_addr)); + rv = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, sizeof(server_addr)); zassert_equal(rv, 0, "server bind failed"); - rv = bind(client_sock, - (struct sockaddr *)&client_addr, - sizeof(client_addr)); + rv = zsock_bind(client_sock, + (struct sockaddr *)&client_addr, + sizeof(client_addr)); zassert_equal(rv, 0, "client bind failed"); io_vector[0].iov_base = TEST_STR_SMALL; @@ -575,9 +575,9 @@ ZTEST_USER(net_socket_udp, test_14_v6_sendmsg_recvfrom) (struct sockaddr *)&server_addr, sizeof(server_addr)); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } @@ -599,18 +599,18 @@ ZTEST_USER(net_socket_udp, test_15_v4_sendmsg_recvfrom_connected) prepare_sock_udp_v4(MY_IPV4_ADDR, ANY_PORT, &client_sock, &client_addr); prepare_sock_udp_v4(MY_IPV4_ADDR, SERVER_PORT, &server_sock, &server_addr); - rv = bind(server_sock, - (struct sockaddr *)&server_addr, - sizeof(server_addr)); + rv = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, + sizeof(server_addr)); zassert_equal(rv, 0, "server bind failed"); - rv = bind(client_sock, - (struct sockaddr *)&client_addr, - sizeof(client_addr)); + rv = zsock_bind(client_sock, + (struct sockaddr *)&client_addr, + sizeof(client_addr)); zassert_equal(rv, 0, "client bind failed"); - rv = connect(client_sock, (struct sockaddr *)&server_addr, - sizeof(server_addr)); + rv = zsock_connect(client_sock, (struct sockaddr *)&server_addr, + sizeof(server_addr)); zassert_equal(rv, 0, "connect failed"); io_vector[0].iov_base = TEST_STR_SMALL; @@ -636,9 +636,9 @@ ZTEST_USER(net_socket_udp, test_15_v4_sendmsg_recvfrom_connected) (struct sockaddr *)&server_addr, sizeof(server_addr)); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } @@ -660,17 +660,17 @@ ZTEST_USER(net_socket_udp, test_06_v6_sendmsg_recvfrom_connected) prepare_sock_udp_v6(MY_IPV6_ADDR, ANY_PORT, &client_sock, &client_addr); prepare_sock_udp_v6(MY_IPV6_ADDR, SERVER_PORT, &server_sock, &server_addr); - rv = bind(server_sock, - (struct sockaddr *)&server_addr, sizeof(server_addr)); + rv = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, sizeof(server_addr)); zassert_equal(rv, 0, "server bind failed"); - rv = bind(client_sock, - (struct sockaddr *)&client_addr, - sizeof(client_addr)); + rv = zsock_bind(client_sock, + (struct sockaddr *)&client_addr, + sizeof(client_addr)); zassert_equal(rv, 0, "client bind failed"); - rv = connect(client_sock, (struct sockaddr *)&server_addr, - sizeof(server_addr)); + rv = zsock_connect(client_sock, (struct sockaddr *)&server_addr, + sizeof(server_addr)); zassert_equal(rv, 0, "connect failed"); io_vector[0].iov_base = TEST_STR_SMALL; @@ -696,9 +696,9 @@ ZTEST_USER(net_socket_udp, test_06_v6_sendmsg_recvfrom_connected) (struct sockaddr *)&server_addr, sizeof(server_addr)); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } @@ -713,19 +713,19 @@ ZTEST(net_socket_udp, test_06_so_type) prepare_sock_udp_v4(MY_IPV4_ADDR, 55555, &sock1, &bind_addr4); prepare_sock_udp_v6(MY_IPV6_ADDR, 55555, &sock2, &bind_addr6); - rv = getsockopt(sock1, SOL_SOCKET, SO_TYPE, &optval, &optsize); + rv = zsock_getsockopt(sock1, SOL_SOCKET, SO_TYPE, &optval, &optsize); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, SOCK_DGRAM, "getsockopt got invalid type"); zassert_equal(optsize, sizeof(optval), "getsockopt got invalid size"); - rv = getsockopt(sock2, SOL_SOCKET, SO_TYPE, &optval, &optsize); + rv = zsock_getsockopt(sock2, SOL_SOCKET, SO_TYPE, &optval, &optsize); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, SOCK_DGRAM, "getsockopt got invalid type"); zassert_equal(optsize, sizeof(optval), "getsockopt got invalid size"); - rv = close(sock1); + rv = zsock_close(sock1); zassert_equal(rv, 0, "close failed"); - rv = close(sock2); + rv = zsock_close(sock2); zassert_equal(rv, 0, "close failed"); } @@ -740,39 +740,39 @@ ZTEST(net_socket_udp, test_08_so_txtime) prepare_sock_udp_v4(MY_IPV4_ADDR, 55555, &sock1, &bind_addr4); prepare_sock_udp_v6(MY_IPV6_ADDR, 55555, &sock2, &bind_addr6); - rv = bind(sock1, (struct sockaddr *)&bind_addr4, sizeof(bind_addr4)); + rv = zsock_bind(sock1, (struct sockaddr *)&bind_addr4, sizeof(bind_addr4)); zassert_equal(rv, 0, "bind failed"); - rv = bind(sock2, (struct sockaddr *)&bind_addr6, sizeof(bind_addr6)); + rv = zsock_bind(sock2, (struct sockaddr *)&bind_addr6, sizeof(bind_addr6)); zassert_equal(rv, 0, "bind failed"); optval = true; - rv = setsockopt(sock1, SOL_SOCKET, SO_TXTIME, &optval, - sizeof(optval)); + rv = zsock_setsockopt(sock1, SOL_SOCKET, SO_TXTIME, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); optval = false; - rv = setsockopt(sock2, SOL_SOCKET, SO_TXTIME, &optval, - sizeof(optval)); + rv = zsock_setsockopt(sock2, SOL_SOCKET, SO_TXTIME, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed"); optlen = sizeof(optval); - rv = getsockopt(sock1, SOL_SOCKET, SO_TXTIME, &optval, &optlen); + rv = zsock_getsockopt(sock1, SOL_SOCKET, SO_TXTIME, &optval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optlen, sizeof(optval), "invalid optlen %d vs %d", optlen, sizeof(optval)); zassert_equal(optval, true, "getsockopt txtime"); optlen = sizeof(optval); - rv = getsockopt(sock2, SOL_SOCKET, SO_TXTIME, &optval, &optlen); + rv = zsock_getsockopt(sock2, SOL_SOCKET, SO_TXTIME, &optval, &optlen); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optlen, sizeof(optval), "invalid optlen %d vs %d", optlen, sizeof(optval)); zassert_equal(optval, false, "getsockopt txtime"); - rv = close(sock1); + rv = zsock_close(sock1); zassert_equal(rv, 0, "close failed"); - rv = close(sock2); + rv = zsock_close(sock2); zassert_equal(rv, 0, "close failed"); } @@ -794,26 +794,26 @@ ZTEST(net_socket_udp, test_09_so_rcvtimeo) prepare_sock_udp_v4(MY_IPV4_ADDR, 55555, &sock1, &bind_addr4); prepare_sock_udp_v6(MY_IPV6_ADDR, 55555, &sock2, &bind_addr6); - rv = bind(sock1, (struct sockaddr *)&bind_addr4, sizeof(bind_addr4)); + rv = zsock_bind(sock1, (struct sockaddr *)&bind_addr4, sizeof(bind_addr4)); zassert_equal(rv, 0, "bind failed"); - rv = bind(sock2, (struct sockaddr *)&bind_addr6, sizeof(bind_addr6)); + rv = zsock_bind(sock2, (struct sockaddr *)&bind_addr6, sizeof(bind_addr6)); zassert_equal(rv, 0, "bind failed"); - rv = setsockopt(sock1, SOL_SOCKET, SO_RCVTIMEO, &optval, - sizeof(optval)); + rv = zsock_setsockopt(sock1, SOL_SOCKET, SO_RCVTIMEO, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); optval.tv_usec = 400000; - rv = setsockopt(sock2, SOL_SOCKET, SO_RCVTIMEO, &optval, - sizeof(optval)); + rv = zsock_setsockopt(sock2, SOL_SOCKET, SO_RCVTIMEO, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); addrlen = sizeof(addr); clear_buf(rx_buf); start_time = k_uptime_get_32(); - recved = recvfrom(sock1, rx_buf, sizeof(rx_buf), - 0, &addr, &addrlen); + recved = zsock_recvfrom(sock1, rx_buf, sizeof(rx_buf), + 0, &addr, &addrlen); time_diff = k_uptime_get_32() - start_time; zassert_equal(recved, -1, "Unexpected return code"); @@ -822,8 +822,8 @@ ZTEST(net_socket_udp, test_09_so_rcvtimeo) "was %dms", time_diff); start_time = k_uptime_get_32(); - recved = recvfrom(sock2, rx_buf, sizeof(rx_buf), - 0, &addr, &addrlen); + recved = zsock_recvfrom(sock2, rx_buf, sizeof(rx_buf), + 0, &addr, &addrlen); time_diff = k_uptime_get_32() - start_time; zassert_equal(recved, -1, "Unexpected return code"); @@ -831,9 +831,9 @@ ZTEST(net_socket_udp, test_09_so_rcvtimeo) zassert_true(time_diff >= 400, "Expected timeout after 400ms but " "was %dms", time_diff); - rv = close(sock1); + rv = zsock_close(sock1); zassert_equal(rv, 0, "close failed"); - rv = close(sock2); + rv = zsock_close(sock2); zassert_equal(rv, 0, "close failed"); } @@ -851,24 +851,24 @@ ZTEST(net_socket_udp, test_10_so_sndtimeo) prepare_sock_udp_v4(MY_IPV4_ADDR, 55555, &sock1, &bind_addr4); prepare_sock_udp_v6(MY_IPV6_ADDR, 55555, &sock2, &bind_addr6); - rv = bind(sock1, (struct sockaddr *)&bind_addr4, sizeof(bind_addr4)); + rv = zsock_bind(sock1, (struct sockaddr *)&bind_addr4, sizeof(bind_addr4)); zassert_equal(rv, 0, "bind failed"); - rv = bind(sock2, (struct sockaddr *)&bind_addr6, sizeof(bind_addr6)); + rv = zsock_bind(sock2, (struct sockaddr *)&bind_addr6, sizeof(bind_addr6)); zassert_equal(rv, 0, "bind failed"); - rv = setsockopt(sock1, SOL_SOCKET, SO_SNDTIMEO, &optval, - sizeof(optval)); + rv = zsock_setsockopt(sock1, SOL_SOCKET, SO_SNDTIMEO, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed (%d)", errno); optval.tv_usec = 0; - rv = setsockopt(sock2, SOL_SOCKET, SO_SNDTIMEO, &optval, - sizeof(optval)); + rv = zsock_setsockopt(sock2, SOL_SOCKET, SO_SNDTIMEO, &optval, + sizeof(optval)); zassert_equal(rv, 0, "setsockopt failed"); - rv = close(sock1); + rv = zsock_close(sock1); zassert_equal(rv, 0, "close failed"); - rv = close(sock2); + rv = zsock_close(sock2); zassert_equal(rv, 0, "close failed"); } @@ -883,19 +883,19 @@ ZTEST(net_socket_udp, test_11_so_protocol) prepare_sock_udp_v4(MY_IPV4_ADDR, 55555, &sock1, &bind_addr4); prepare_sock_udp_v6(MY_IPV6_ADDR, 55555, &sock2, &bind_addr6); - rv = getsockopt(sock1, SOL_SOCKET, SO_PROTOCOL, &optval, &optsize); + rv = zsock_getsockopt(sock1, SOL_SOCKET, SO_PROTOCOL, &optval, &optsize); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, IPPROTO_UDP, "getsockopt got invalid protocol"); zassert_equal(optsize, sizeof(optval), "getsockopt got invalid size"); - rv = getsockopt(sock2, SOL_SOCKET, SO_PROTOCOL, &optval, &optsize); + rv = zsock_getsockopt(sock2, SOL_SOCKET, SO_PROTOCOL, &optval, &optsize); zassert_equal(rv, 0, "getsockopt failed (%d)", errno); zassert_equal(optval, IPPROTO_UDP, "getsockopt got invalid protocol"); zassert_equal(optsize, sizeof(optval), "getsockopt got invalid size"); - rv = close(sock1); + rv = zsock_close(sock1); zassert_equal(rv, 0, "close failed"); - rv = close(sock2); + rv = zsock_close(sock2); zassert_equal(rv, 0, "close failed"); } @@ -913,7 +913,7 @@ static void comm_sendmsg_with_txtime(int client_sock, * Test client -> server sending */ - sent = sendmsg(client_sock, client_msg, 0); + sent = zsock_sendmsg(client_sock, client_msg, 0); zassert_true(sent > 0, "sendmsg failed (%d)", -errno); for (i = 0, len = 0; i < client_msg->msg_iovlen; i++) { @@ -1037,7 +1037,7 @@ ZTEST(net_socket_udp, test_17_setup_eth_for_ipv6) (void)memset(&udp_server_addr, 0, sizeof(udp_server_addr)); udp_server_addr.sin6_family = AF_INET6; udp_server_addr.sin6_port = htons(1234); - ret = inet_pton(AF_INET6, PEER_IPV6_ADDR_ETH, &udp_server_addr.sin6_addr); + ret = zsock_inet_pton(AF_INET6, PEER_IPV6_ADDR_ETH, &udp_server_addr.sin6_addr); zassert_equal(ret, 1, "inet_pton failed"); /* In order to avoid neighbor discovery, populate neighbor cache */ @@ -1062,9 +1062,9 @@ ZTEST_USER(net_socket_udp, test_18_v6_sendmsg_with_txtime) prepare_sock_udp_v6(MY_IPV6_ADDR_ETH, ANY_PORT, &client_sock, &client_addr); - rv = bind(client_sock, - (struct sockaddr *)&client_addr, - sizeof(client_addr)); + rv = zsock_bind(client_sock, + (struct sockaddr *)&client_addr, + sizeof(client_addr)); zassert_equal(rv, 0, "client bind failed"); io_vector[0].iov_base = TEST_STR_SMALL; @@ -1087,8 +1087,8 @@ ZTEST_USER(net_socket_udp, test_18_v6_sendmsg_with_txtime) *(net_time_t *)CMSG_DATA(cmsg) = txtime; optval = true; - rv = setsockopt(client_sock, SOL_SOCKET, SO_TXTIME, &optval, - sizeof(optval)); + rv = zsock_setsockopt(client_sock, SOL_SOCKET, SO_TXTIME, &optval, + sizeof(optval)); test_started = true; @@ -1097,7 +1097,7 @@ ZTEST_USER(net_socket_udp, test_18_v6_sendmsg_with_txtime) sizeof(client_addr), &msg); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); if (sys_mutex_lock(&wait_data, WAIT_TIME)) { @@ -1116,50 +1116,50 @@ void test_msg_trunc(int sock_c, int sock_s, struct sockaddr *addr_c, int rv; uint8_t str_buf[sizeof(TEST_STR_SMALL) - 1]; - rv = bind(sock_s, addr_s, addrlen_s); + rv = zsock_bind(sock_s, addr_s, addrlen_s); zassert_equal(rv, 0, "server bind failed"); - rv = bind(sock_c, addr_c, addrlen_c); + rv = zsock_bind(sock_c, addr_c, addrlen_c); zassert_equal(rv, 0, "client bind failed"); - rv = connect(sock_c, addr_s, addrlen_s); + rv = zsock_connect(sock_c, addr_s, addrlen_s); zassert_equal(rv, 0, "connect failed"); /* MSG_TRUNC */ - rv = send(sock_c, BUF_AND_SIZE(TEST_STR_SMALL), 0); + rv = zsock_send(sock_c, BUF_AND_SIZE(TEST_STR_SMALL), 0); zassert_equal(rv, sizeof(TEST_STR_SMALL) - 1, "send failed"); memset(str_buf, 0, sizeof(str_buf)); - rv = recv(sock_s, str_buf, 2, ZSOCK_MSG_TRUNC); + rv = zsock_recv(sock_s, str_buf, 2, ZSOCK_MSG_TRUNC); zassert_equal(rv, sizeof(TEST_STR_SMALL) - 1, "MSG_TRUNC flag failed"); zassert_mem_equal(str_buf, TEST_STR_SMALL, 2, "invalid rx data"); zassert_equal(str_buf[2], 0, "received more than requested"); /* The remaining data should've been discarded */ - rv = recv(sock_s, str_buf, sizeof(str_buf), ZSOCK_MSG_DONTWAIT); + rv = zsock_recv(sock_s, str_buf, sizeof(str_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(rv, -1, "consecutive recv should've failed"); zassert_equal(errno, EAGAIN, "incorrect errno value"); /* MSG_TRUNC & MSG_PEEK combo */ - rv = send(sock_c, BUF_AND_SIZE(TEST_STR_SMALL), 0); + rv = zsock_send(sock_c, BUF_AND_SIZE(TEST_STR_SMALL), 0); zassert_equal(rv, sizeof(TEST_STR_SMALL) - 1, "send failed"); memset(str_buf, 0, sizeof(str_buf)); - rv = recv(sock_s, str_buf, 2, ZSOCK_MSG_TRUNC | ZSOCK_MSG_PEEK); + rv = zsock_recv(sock_s, str_buf, 2, ZSOCK_MSG_TRUNC | ZSOCK_MSG_PEEK); zassert_equal(rv, sizeof(TEST_STR_SMALL) - 1, "MSG_TRUNC flag failed"); /* The packet should still be available due to MSG_PEEK */ - rv = recv(sock_s, str_buf, sizeof(str_buf), ZSOCK_MSG_TRUNC); + rv = zsock_recv(sock_s, str_buf, sizeof(str_buf), ZSOCK_MSG_TRUNC); zassert_equal(rv, sizeof(TEST_STR_SMALL) - 1, "recv after MSG_PEEK failed"); zassert_mem_equal(str_buf, BUF_AND_SIZE(TEST_STR_SMALL), "invalid rx data"); - rv = close(sock_c); + rv = zsock_close(sock_c); zassert_equal(rv, 0, "close failed"); - rv = close(sock_s); + rv = zsock_close(sock_s); zassert_equal(rv, 0, "close failed"); } @@ -1200,22 +1200,22 @@ static void test_dgram_overflow(int sock_c, int sock_s, { int rv; - rv = bind(sock_s, addr_s, addrlen_s); + rv = zsock_bind(sock_s, addr_s, addrlen_s); zassert_equal(rv, 0, "server bind failed"); - rv = bind(sock_c, addr_c, addrlen_c); + rv = zsock_bind(sock_c, addr_c, addrlen_c); zassert_equal(rv, 0, "client bind failed"); - rv = connect(sock_c, addr_s, addrlen_s); + rv = zsock_connect(sock_c, addr_s, addrlen_s); zassert_equal(rv, 0, "connect failed"); - rv = send(sock_c, buf, buf_size, 0); + rv = zsock_send(sock_c, buf, buf_size, 0); zassert_equal(rv, -1, "send succeeded"); zassert_equal(errno, ENOMEM, "incorrect errno value"); - rv = close(sock_c); + rv = zsock_close(sock_c); zassert_equal(rv, 0, "close failed"); - rv = close(sock_s); + rv = zsock_close(sock_s); zassert_equal(rv, 0, "close failed"); } @@ -1226,26 +1226,26 @@ static void test_dgram_fragmented(int sock_c, int sock_s, { int rv; - rv = bind(sock_s, addr_s, addrlen_s); + rv = zsock_bind(sock_s, addr_s, addrlen_s); zassert_equal(rv, 0, "server bind failed"); - rv = bind(sock_c, addr_c, addrlen_c); + rv = zsock_bind(sock_c, addr_c, addrlen_c); zassert_equal(rv, 0, "client bind failed"); - rv = connect(sock_c, addr_s, addrlen_s); + rv = zsock_connect(sock_c, addr_s, addrlen_s); zassert_equal(rv, 0, "connect failed"); - rv = send(sock_c, buf, buf_size, 0); + rv = zsock_send(sock_c, buf, buf_size, 0); zassert_equal(rv, buf_size, "send failed"); memset(rx_buf, 0, sizeof(rx_buf)); - rv = recv(sock_s, rx_buf, sizeof(rx_buf), 0); + rv = zsock_recv(sock_s, rx_buf, sizeof(rx_buf), 0); zassert_equal(rv, buf_size, "recv failed"); zassert_mem_equal(rx_buf, buf, buf_size, "wrong data"); - rv = close(sock_c); + rv = zsock_close(sock_c); zassert_equal(rv, 0, "close failed"); - rv = close(sock_s); + rv = zsock_close(sock_s); zassert_equal(rv, 0, "close failed"); } @@ -1313,46 +1313,46 @@ static void test_dgram_connected(int sock_c, int sock_s1, int sock_s2, uint8_t rx_buf; int rv; - rv = bind(sock_c, addr_c, addrlen_c); + rv = zsock_bind(sock_c, addr_c, addrlen_c); zassert_equal(rv, 0, "client bind failed"); - rv = bind(sock_s1, addr_s1, addrlen_s1); + rv = zsock_bind(sock_s1, addr_s1, addrlen_s1); zassert_equal(rv, 0, "server bind failed"); - rv = bind(sock_s2, addr_s2, addrlen_s2); + rv = zsock_bind(sock_s2, addr_s2, addrlen_s2); zassert_equal(rv, 0, "server bind failed"); - rv = connect(sock_c, addr_s1, addrlen_s1); + rv = zsock_connect(sock_c, addr_s1, addrlen_s1); zassert_equal(rv, 0, "connect failed"); /* Verify that a datagram can be received from the connected address */ - rv = sendto(sock_s1, &tx_buf, sizeof(tx_buf), 0, addr_c, addrlen_c); + rv = zsock_sendto(sock_s1, &tx_buf, sizeof(tx_buf), 0, addr_c, addrlen_c); zassert_equal(rv, sizeof(tx_buf), "send failed %d", errno); /* Give the packet a chance to go through the net stack */ k_msleep(10); rx_buf = 0; - rv = recv(sock_c, &rx_buf, sizeof(rx_buf), MSG_DONTWAIT); + rv = zsock_recv(sock_c, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(rv, sizeof(rx_buf), "recv failed"); zassert_equal(rx_buf, tx_buf, "wrong data"); /* Verify that a datagram is not received from other address */ - rv = sendto(sock_s2, &tx_buf, sizeof(tx_buf), 0, addr_c, addrlen_c); + rv = zsock_sendto(sock_s2, &tx_buf, sizeof(tx_buf), 0, addr_c, addrlen_c); zassert_equal(rv, sizeof(tx_buf), "send failed"); /* Give the packet a chance to go through the net stack */ k_msleep(10); - rv = recv(sock_c, &rx_buf, sizeof(rx_buf), MSG_DONTWAIT); + rv = zsock_recv(sock_c, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); zassert_equal(rv, -1, "recv should've failed"); zassert_equal(errno, EAGAIN, "incorrect errno"); - rv = close(sock_c); + rv = zsock_close(sock_c); zassert_equal(rv, 0, "close failed"); - rv = close(sock_s1); + rv = zsock_close(sock_s1); zassert_equal(rv, 0, "close failed"); - rv = close(sock_s2); + rv = zsock_close(sock_s2); zassert_equal(rv, 0, "close failed"); } @@ -1412,19 +1412,19 @@ ZTEST_USER(net_socket_udp, test_26_recvmsg_invalid) io_vector[0].iov_base = TEST_STR_SMALL; io_vector[0].iov_len = strlen(TEST_STR_SMALL); - ret = recvmsg(0, NULL, 0); + ret = zsock_recvmsg(0, NULL, 0); zassert_true(ret < 0 && errno == EINVAL, "Wrong errno (%d)", errno); /* Set various pointers to NULL or invalid value which should cause failure */ memset(&msg, 0, sizeof(msg)); msg.msg_controllen = sizeof(cmsgbuf.buf); - ret = recvmsg(0, &msg, 0); + ret = zsock_recvmsg(0, &msg, 0); zassert_true(ret < 0, "recvmsg() succeed"); msg.msg_control = &cmsgbuf.buf; - ret = recvmsg(0, &msg, 0); + ret = zsock_recvmsg(0, &msg, 0); zassert_true(ret < 0 && errno == ENOMEM, "Wrong errno (%d)", errno); msg.msg_iov = io_vector; @@ -1438,7 +1438,7 @@ ZTEST_USER(net_socket_udp, test_26_recvmsg_invalid) cmsg->cmsg_type = 1122; *(int *)CMSG_DATA(cmsg) = 42; - ret = recvmsg(0, &msg, 0); + ret = zsock_recvmsg(0, &msg, 0); zassert_true(ret < 0, "recvmsg() succeed"); } @@ -1471,12 +1471,12 @@ static void comm_sendmsg_recvmsg(int client_sock, * Test client -> server sending */ - sent = sendmsg(client_sock, client_msg, 0); + sent = zsock_sendmsg(client_sock, client_msg, 0); zassert_true(sent > 0, "sendmsg failed, %s (%d)", strerror(errno), -errno); /* One negative test with invalid msg_iov */ memset(msg, 0, sizeof(*msg)); - recved = recvmsg(server_sock, msg, 0); + recved = zsock_recvmsg(server_sock, msg, 0); zassert_true(recved < 0 && errno == ENOMEM, "Wrong errno (%d)", errno); for (i = 0, len = 0; i < client_msg->msg_iovlen; i++) { @@ -1498,7 +1498,7 @@ static void comm_sendmsg_recvmsg(int client_sock, msg->msg_namelen = addrlen; /* Test recvmsg(MSG_PEEK) */ - recved = recvmsg(server_sock, msg, MSG_PEEK); + recved = zsock_recvmsg(server_sock, msg, ZSOCK_MSG_PEEK); zassert_true(recved > 0, "recvmsg fail, %s (%d)", strerror(errno), -errno); zassert_equal(recved, strlen(TEST_STR_SMALL), "unexpected received bytes (%d vs %d)", @@ -1512,7 +1512,7 @@ static void comm_sendmsg_recvmsg(int client_sock, /* Test normal recvmsg() */ clear_buf(rx_buf); - recved = recvmsg(server_sock, msg, 0); + recved = zsock_recvmsg(server_sock, msg, 0); zassert_true(recved > 0, "recvfrom fail"); zassert_equal(recved, strlen(TEST_STR_SMALL), "unexpected received bytes"); @@ -1547,7 +1547,7 @@ static void comm_sendmsg_recvmsg(int client_sock, /* Then send the message again and verify that we could receive * the full message in smaller chunks too. */ - sent = sendmsg(client_sock, client_msg, 0); + sent = zsock_sendmsg(client_sock, client_msg, 0); zassert_true(sent > 0, "sendmsg failed (%d)", -errno); for (i = 0, len = 0; i < client_msg->msg_iovlen; i++) { @@ -1571,7 +1571,7 @@ static void comm_sendmsg_recvmsg(int client_sock, msg->msg_namelen = addrlen; /* Test recvmsg(MSG_PEEK) */ - recved = recvmsg(server_sock, msg, MSG_PEEK); + recved = zsock_recvmsg(server_sock, msg, ZSOCK_MSG_PEEK); zassert_true(recved >= 0, "recvfrom fail (errno %d)", errno); zassert_equal(recved, strlen(TEST_STR_SMALL), "unexpected received bytes (%d vs %d)", recved, strlen(TEST_STR_SMALL)); @@ -1586,7 +1586,7 @@ static void comm_sendmsg_recvmsg(int client_sock, zassert_equal(addrlen, client_addrlen, "unexpected addrlen"); /* Test normal recvfrom() */ - recved = recvmsg(server_sock, msg, MSG_PEEK); + recved = zsock_recvmsg(server_sock, msg, ZSOCK_MSG_PEEK); zassert_true(recved >= 0, "recvfrom fail (errno %d)", errno); zassert_equal(recved, strlen(TEST_STR_SMALL), "unexpected received bytes (%d vs %d)", recved, strlen(TEST_STR_SMALL)); @@ -1608,7 +1608,7 @@ static void comm_sendmsg_recvmsg(int client_sock, } /* Then check that the trucation flag is set correctly */ - sent = sendmsg(client_sock, client_msg, 0); + sent = zsock_sendmsg(client_sock, client_msg, 0); zassert_true(sent > 0, "sendmsg failed (%d)", -errno); for (i = 0, len = 0; i < client_msg->msg_iovlen; i++) { @@ -1630,12 +1630,12 @@ static void comm_sendmsg_recvmsg(int client_sock, msg->msg_namelen = addrlen; /* Test recvmsg */ - recved = recvmsg(server_sock, msg, 0); + recved = zsock_recvmsg(server_sock, msg, 0); zassert_true(recved > 0, "recvmsg fail, %s (%d)", strerror(errno), errno); zassert_equal(recved, sizeof(buf2), "unexpected received bytes (%d vs %d)", recved, sizeof(buf2)); - zassert_true(msg->msg_flags & MSG_TRUNC, "Message not truncated"); + zassert_true(msg->msg_flags & ZSOCK_MSG_TRUNC, "Message not truncated"); zassert_mem_equal(buf2, TEST_STR_SMALL, sizeof(buf2), "wrong data (%s)", buf2); @@ -1662,14 +1662,14 @@ ZTEST_USER(net_socket_udp, test_27_recvmsg_user) prepare_sock_udp_v4(MY_IPV4_ADDR, ANY_PORT, &client_sock, &client_addr); prepare_sock_udp_v4(MY_IPV4_ADDR, SERVER_PORT, &server_sock, &server_addr); - rv = bind(server_sock, - (struct sockaddr *)&server_addr, - sizeof(server_addr)); + rv = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, + sizeof(server_addr)); zassert_equal(rv, 0, "server bind failed"); - rv = bind(client_sock, - (struct sockaddr *)&client_addr, - sizeof(client_addr)); + rv = zsock_bind(client_sock, + (struct sockaddr *)&client_addr, + sizeof(client_addr)); zassert_equal(rv, 0, "client bind failed"); io_vector[0].iov_base = TEST_STR_SMALL; @@ -1690,9 +1690,9 @@ ZTEST_USER(net_socket_udp, test_27_recvmsg_user) sizeof(server_addr), &server_msg, NULL, 0, false); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } @@ -1722,10 +1722,10 @@ static void run_ancillary_recvmsg_test(int client_sock, Z_TEST_SKIP_IFNDEF(CONFIG_NET_CONTEXT_RECV_PKTINFO); - rv = bind(server_sock, server_addr, server_addr_len); + rv = zsock_bind(server_sock, server_addr, server_addr_len); zassert_equal(rv, 0, "server bind failed"); - rv = bind(client_sock, client_addr, client_addr_len); + rv = zsock_bind(client_sock, client_addr, client_addr_len); zassert_equal(rv, 0, "client bind failed"); io_vector[0].iov_base = TEST_STR_SMALL; @@ -1776,7 +1776,7 @@ static void run_ancillary_recvmsg_test(int client_sock, opt = 1; optlen = sizeof(opt); - rv = setsockopt(server_sock, IPPROTO_IP, IP_PKTINFO, &opt, optlen); + rv = zsock_setsockopt(server_sock, IPPROTO_IP, IP_PKTINFO, &opt, optlen); zassert_equal(rv, 0, "setsockopt failed (%d)", -errno); memset(&cmsgbuf, 0, sizeof(cmsgbuf)); @@ -1837,8 +1837,8 @@ static void run_ancillary_recvmsg_test(int client_sock, } /* Make sure that the recvmsg() fails if control area is too small */ - rv = sendto(client_sock, BUF_AND_SIZE(TEST_STR_SMALL), 0, - server_addr, server_addr_len); + rv = zsock_sendto(client_sock, BUF_AND_SIZE(TEST_STR_SMALL), 0, + server_addr, server_addr_len); zassert_equal(rv, STRLEN(TEST_STR_SMALL), "sendto failed (%d)", -errno); io_vector[0].iov_base = buf; @@ -1850,14 +1850,14 @@ static void run_ancillary_recvmsg_test(int client_sock, msg.msg_iov = io_vector; msg.msg_iovlen = 1; - rv = recvmsg(server_sock, &msg, 0); + rv = zsock_recvmsg(server_sock, &msg, 0); zassert_true(rv, "recvmsg succeed (%d)", rv); - zassert_true(msg.msg_flags & MSG_CTRUNC, "Control message not truncated"); + zassert_true(msg.msg_flags & ZSOCK_MSG_CTRUNC, "Control message not truncated"); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } @@ -1926,7 +1926,7 @@ static int bind_socket(int sock, struct net_if *iface) addr.sll_ifindex = net_if_get_by_iface(iface); addr.sll_family = AF_PACKET; - return bind(sock, (struct sockaddr *)&addr, sizeof(addr)); + return zsock_bind(sock, (struct sockaddr *)&addr, sizeof(addr)); } static void test_check_ttl(int sock_c, int sock_s, int sock_p, @@ -1961,37 +1961,37 @@ static void test_check_ttl(int sock_c, int sock_s, int sock_p, Z_TEST_SKIP_IFNDEF(CONFIG_NET_INTERFACE_NAME); - ret = bind(sock_c, addr_c, addrlen_c); + ret = zsock_bind(sock_c, addr_c, addrlen_c); zassert_equal(ret, 0, "client bind failed"); ret = net_if_get_name(lo0, ifname, sizeof(ifname)); zassert_true(ret > 0, "cannot get interface name (%d)", ret); strncpy(ifreq.ifr_name, ifname, sizeof(ifreq.ifr_name)); - ret = setsockopt(sock_c, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, - sizeof(ifreq)); + ret = zsock_setsockopt(sock_c, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, + sizeof(ifreq)); zassert_equal(ret, 0, "SO_BINDTODEVICE failed, %d", -errno); - ret = connect(sock_c, addr_s, addrlen_s); + ret = zsock_connect(sock_c, addr_s, addrlen_s); zassert_equal(ret, 0, "connect failed"); - ret = setsockopt(sock_s, SOL_SOCKET, SO_RCVTIMEO, - &timeo_optval, sizeof(timeo_optval)); + ret = zsock_setsockopt(sock_s, SOL_SOCKET, SO_RCVTIMEO, + &timeo_optval, sizeof(timeo_optval)); zassert_equal(ret, 0, "Cannot set receive timeout (%d)", -errno); while (count > 0) { - ret = sendto(sock_c, &tx_buf, sizeof(tx_buf), 0, - addr_sendto, addrlen_sendto); + ret = zsock_sendto(sock_c, &tx_buf, sizeof(tx_buf), 0, + addr_sendto, addrlen_sendto); zassert_equal(ret, sizeof(tx_buf), "send failed (%d)", -errno); - ret = recv(sock_s, &rx_buf, sizeof(rx_buf), MSG_DONTWAIT); + ret = zsock_recv(sock_s, &rx_buf, sizeof(rx_buf), ZSOCK_MSG_DONTWAIT); if (ret > 0) { zassert_equal(ret, sizeof(rx_buf), "recv failed (%d)", ret); zassert_equal(rx_buf, tx_buf, "wrong data"); } - ret = recvfrom(sock_p, data_to_receive, sizeof(data_to_receive), 0, - (struct sockaddr *)&src, &addrlen); + ret = zsock_recvfrom(sock_p, data_to_receive, sizeof(data_to_receive), 0, + (struct sockaddr *)&src, &addrlen); if (ret > 0) { int hdr_size = family == AF_INET ? V4_HDR_SIZE : V6_HDR_SIZE; @@ -2054,7 +2054,7 @@ static void test_check_ttl(int sock_c, int sock_s, int sock_p, } opt = 0; - ret = setsockopt(sock_c, IPPROTO_IP, option, &opt, sizeof(opt)); + ret = zsock_setsockopt(sock_c, IPPROTO_IP, option, &opt, sizeof(opt)); zassert_equal(ret, 0, "Cannot set %s TTL (%d)", option == IP_TTL ? "unicast" : "multicast", -errno); @@ -2066,8 +2066,8 @@ static void test_check_ttl(int sock_c, int sock_s, int sock_p, net_mgmt(NET_REQUEST_STATS_GET_IPV4, lo0, &ipv4_stats_before, sizeof(ipv4_stats_before)); #endif - ret = sendto(sock_c, &tx_buf, sizeof(tx_buf), 0, - addr_sendto, addrlen_sendto); + ret = zsock_sendto(sock_c, &tx_buf, sizeof(tx_buf), 0, + addr_sendto, addrlen_sendto); zassert_equal(ret, sizeof(tx_buf), "send failed (%d)", -errno); #if defined(CONFIG_NET_STATISTICS) @@ -2080,7 +2080,7 @@ static void test_check_ttl(int sock_c, int sock_s, int sock_p, ipv4_stats_before.drop + 1, ipv4_stats_after.drop); #endif - ret = recv(sock_s, &rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(sock_s, &rx_buf, sizeof(rx_buf), 0); zassert_true(ret < 0 && errno == EAGAIN, "recv succeed (%d)", -errno); } @@ -2097,8 +2097,8 @@ static void test_check_ttl(int sock_c, int sock_s, int sock_p, } opt = 0; - ret = setsockopt(sock_c, IPPROTO_IPV6, option, - &opt, sizeof(opt)); + ret = zsock_setsockopt(sock_c, IPPROTO_IPV6, option, + &opt, sizeof(opt)); zassert_equal(ret, 0, "Cannot set %s hops (%d)", option == IPV6_UNICAST_HOPS ? "unicast" : "multicast", -errno); @@ -2110,8 +2110,8 @@ static void test_check_ttl(int sock_c, int sock_s, int sock_p, net_mgmt(NET_REQUEST_STATS_GET_IPV6, lo0, &ipv6_stats_before, sizeof(ipv6_stats_before)); #endif - ret = sendto(sock_c, &tx_buf, sizeof(tx_buf), 0, - addr_sendto, addrlen_sendto); + ret = zsock_sendto(sock_c, &tx_buf, sizeof(tx_buf), 0, + addr_sendto, addrlen_sendto); zassert_equal(ret, sizeof(tx_buf), "send failed (%d)", -errno); #if defined(CONFIG_NET_STATISTICS) @@ -2124,16 +2124,16 @@ static void test_check_ttl(int sock_c, int sock_s, int sock_p, ipv6_stats_before.drop + 1, ipv6_stats_after.drop); #endif - ret = recv(sock_s, &rx_buf, sizeof(rx_buf), 0); + ret = zsock_recv(sock_s, &rx_buf, sizeof(rx_buf), 0); zassert_true(ret < 0 && errno == EAGAIN, "recv succeed (%d)", -errno); } - ret = close(sock_c); + ret = zsock_close(sock_c); zassert_equal(ret, 0, "close failed"); - ret = close(sock_s); + ret = zsock_close(sock_s); zassert_equal(ret, 0, "close failed"); - ret = close(sock_p); + ret = zsock_close(sock_p); zassert_equal(ret, 0, "close failed"); } @@ -2153,7 +2153,7 @@ ZTEST(net_socket_udp, test_31_v4_ttl) prepare_sock_udp_v4(MY_IPV4_ADDR, CLIENT_PORT, &client_sock, &client_addr); prepare_sock_udp_v4(MY_IPV4_ADDR, SERVER_PORT, &server_sock, &server_addr); - packet_sock = socket(AF_PACKET, SOCK_RAW, ETH_P_ALL); + packet_sock = zsock_socket(AF_PACKET, SOCK_RAW, ETH_P_ALL); zassert_true(packet_sock >= 0, "Cannot create packet socket (%d)", -errno); ret = bind_socket(packet_sock, lo0); @@ -2169,11 +2169,11 @@ ZTEST(net_socket_udp, test_31_v4_ttl) zassert_equal(verify, ttl, "Different TTLs (%d vs %d)", ttl, verify); ttl = 128; - ret = setsockopt(client_sock, IPPROTO_IP, IP_TTL, &ttl, sizeof(ttl)); + ret = zsock_setsockopt(client_sock, IPPROTO_IP, IP_TTL, &ttl, sizeof(ttl)); zassert_equal(ret, 0, "Cannot set unicast TTL (%d)", -errno); optlen = sizeof(verify); - ret = getsockopt(client_sock, IPPROTO_IP, IP_TTL, &verify, &optlen); + ret = zsock_getsockopt(client_sock, IPPROTO_IP, IP_TTL, &verify, &optlen); zassert_equal(ret, 0, "Cannot get unicast TTL (%d)", -errno); zassert_equal(verify, ttl, "Different unicast TTL (%d vs %d)", ttl, verify); @@ -2202,7 +2202,7 @@ ZTEST(net_socket_udp, test_32_v4_mcast_ttl) prepare_sock_udp_v4(MY_IPV4_ADDR, CLIENT_PORT, &client_sock, &client_addr); prepare_sock_udp_v4(MY_IPV4_ADDR, SERVER_PORT, &server_sock, &server_addr); - packet_sock = socket(AF_PACKET, SOCK_RAW, ETH_P_ALL); + packet_sock = zsock_socket(AF_PACKET, SOCK_RAW, ETH_P_ALL); zassert_true(packet_sock >= 0, "Cannot create packet socket (%d)", -errno); ret = bind_socket(packet_sock, lo0); @@ -2213,13 +2213,13 @@ ZTEST(net_socket_udp, test_32_v4_mcast_ttl) net_if_get_by_iface(lo0), lo0); mcast_ttl = 8; - ret = setsockopt(client_sock, IPPROTO_IP, IP_MULTICAST_TTL, &mcast_ttl, - sizeof(mcast_ttl)); + ret = zsock_setsockopt(client_sock, IPPROTO_IP, IP_MULTICAST_TTL, &mcast_ttl, + sizeof(mcast_ttl)); zassert_equal(ret, 0, "Cannot set multicast ttl (%d)", -errno); optlen = sizeof(verify); - ret = getsockopt(client_sock, IPPROTO_IP, IP_MULTICAST_TTL, &verify, - &optlen); + ret = zsock_getsockopt(client_sock, IPPROTO_IP, IP_MULTICAST_TTL, &verify, + &optlen); zassert_equal(ret, 0, "Cannot get multicast ttl (%d)", -errno); zassert_equal(verify, mcast_ttl, "Different multicast TTLs (%d vs %d)", mcast_ttl, verify); @@ -2252,7 +2252,7 @@ ZTEST(net_socket_udp, test_33_v6_mcast_hops) prepare_sock_udp_v6(MY_IPV6_ADDR, CLIENT_PORT, &client_sock, &client_addr); prepare_sock_udp_v6(MY_IPV6_ADDR, SERVER_PORT, &server_sock, &server_addr); - packet_sock = socket(AF_PACKET, SOCK_RAW, ETH_P_ALL); + packet_sock = zsock_socket(AF_PACKET, SOCK_RAW, ETH_P_ALL); zassert_true(packet_sock >= 0, "Cannot create packet socket (%d)", -errno); ret = bind_socket(packet_sock, lo0); @@ -2268,26 +2268,26 @@ ZTEST(net_socket_udp, test_33_v6_mcast_hops) if_mcast_hops = net_if_ipv6_get_mcast_hop_limit(lo0); opt = -1; - ret = setsockopt(client_sock, IPPROTO_IPV6, IPV6_MULTICAST_HOPS, &opt, - sizeof(opt)); + ret = zsock_setsockopt(client_sock, IPPROTO_IPV6, IPV6_MULTICAST_HOPS, &opt, + sizeof(opt)); zassert_equal(ret, 0, "Cannot set multicast hop limit (%d)", -errno); optlen = sizeof(verify); - ret = getsockopt(client_sock, IPPROTO_IPV6, IPV6_MULTICAST_HOPS, &verify, - &optlen); + ret = zsock_getsockopt(client_sock, IPPROTO_IPV6, IPV6_MULTICAST_HOPS, &verify, + &optlen); zassert_equal(ret, 0, "Cannot get multicast hop limit (%d)", -errno); zassert_equal(verify, if_mcast_hops, "Different multicast hop limit (%d vs %d)", if_mcast_hops, verify); /* Then test the normal case where we set the value */ mcast_hops = 8; - ret = setsockopt(client_sock, IPPROTO_IPV6, IPV6_MULTICAST_HOPS, &mcast_hops, - sizeof(mcast_hops)); + ret = zsock_setsockopt(client_sock, IPPROTO_IPV6, IPV6_MULTICAST_HOPS, &mcast_hops, + sizeof(mcast_hops)); zassert_equal(ret, 0, "Cannot set multicast hop limit (%d)", -errno); optlen = sizeof(verify); - ret = getsockopt(client_sock, IPPROTO_IPV6, IPV6_MULTICAST_HOPS, &verify, - &optlen); + ret = zsock_getsockopt(client_sock, IPPROTO_IPV6, IPV6_MULTICAST_HOPS, &verify, + &optlen); zassert_equal(ret, 0, "Cannot get multicast hop limit (%d)", -errno); zassert_equal(verify, mcast_hops, "Different multicast hop limit (%d vs %d)", mcast_hops, verify); @@ -2318,7 +2318,7 @@ ZTEST(net_socket_udp, test_34_v6_hops) prepare_sock_udp_v6(MY_IPV6_ADDR, CLIENT_PORT, &client_sock, &client_addr); prepare_sock_udp_v6(MY_IPV6_ADDR, SERVER_PORT, &server_sock, &server_addr); - packet_sock = socket(AF_PACKET, SOCK_RAW, ETH_P_ALL); + packet_sock = zsock_socket(AF_PACKET, SOCK_RAW, ETH_P_ALL); zassert_true(packet_sock >= 0, "Cannot create packet socket (%d)", -errno); ret = bind_socket(packet_sock, lo0); @@ -2334,13 +2334,13 @@ ZTEST(net_socket_udp, test_34_v6_hops) zassert_equal(verify, hops, "Different hop limit (%d vs %d)", hops, verify); hops = 8; - ret = setsockopt(client_sock, IPPROTO_IPV6, IPV6_UNICAST_HOPS, &hops, - sizeof(hops)); + ret = zsock_setsockopt(client_sock, IPPROTO_IPV6, IPV6_UNICAST_HOPS, &hops, + sizeof(hops)); zassert_equal(ret, 0, "Cannot set unicast hops (%d)", -errno); optlen = sizeof(verify); - ret = getsockopt(client_sock, IPPROTO_IPV6, IPV6_UNICAST_HOPS, &verify, - &optlen); + ret = zsock_getsockopt(client_sock, IPPROTO_IPV6, IPV6_UNICAST_HOPS, &verify, + &optlen); zassert_equal(ret, 0, "Cannot get unicast hops (%d)", -errno); zassert_equal(verify, hops, "Different unicast hops (%d vs %d)", hops, verify); @@ -2369,14 +2369,14 @@ ZTEST_USER(net_socket_udp, test_35_recvmsg_msg_controllen_update) prepare_sock_udp_v4(MY_IPV4_ADDR, ANY_PORT, &client_sock, &client_addr); prepare_sock_udp_v4(MY_IPV4_ADDR, SERVER_PORT, &server_sock, &server_addr); - rv = bind(server_sock, - (struct sockaddr *)&server_addr, - sizeof(server_addr)); + rv = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, + sizeof(server_addr)); zassert_equal(rv, 0, "server bind failed"); - rv = bind(client_sock, - (struct sockaddr *)&client_addr, - sizeof(client_addr)); + rv = zsock_bind(client_sock, + (struct sockaddr *)&client_addr, + sizeof(client_addr)); zassert_equal(rv, 0, "client bind failed"); memset(&cmsgbuf, 0, sizeof(cmsgbuf)); @@ -2402,9 +2402,9 @@ ZTEST_USER(net_socket_udp, test_35_recvmsg_msg_controllen_update) sizeof(cmsgbuf.buf), false); - rv = close(client_sock); + rv = zsock_close(client_sock); zassert_equal(rv, 0, "close failed"); - rv = close(server_sock); + rv = zsock_close(server_sock); zassert_equal(rv, 0, "close failed"); } diff --git a/tests/net/socket/websocket/prj.conf b/tests/net/socket/websocket/prj.conf index edf128a7df0..19c1ea582c8 100644 --- a/tests/net/socket/websocket/prj.conf +++ b/tests/net/socket/websocket/prj.conf @@ -10,7 +10,6 @@ CONFIG_NET_LOOPBACK=y # Sockets CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y # Network driver config CONFIG_TEST_RANDOM_GENERATOR=y From 5c3fa85bc829e1a90df80e0052453baa881d1309 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 07:55:29 +0200 Subject: [PATCH 1531/2402] samples: net: Change to use CONFIG_POSIX_API Change the sample applications that use network socket API to use the POSIX_API config because the NET_SOCKETS_POSIX_NAMES is deprecated. Convert also the zsock_ API calls to plain BSD socket API calls when applicable. Signed-off-by: Jukka Rissanen --- samples/net/cellular_modem/prj.conf | 2 ++ samples/net/cellular_modem/src/main.c | 20 ++++++++--------- samples/net/cloud/aws_iot_mqtt/prj.conf | 1 + samples/net/cloud/aws_iot_mqtt/src/main.c | 22 +++++++++---------- samples/net/cloud/mqtt_azure/prj.conf | 1 + samples/net/cloud/mqtt_azure/src/main.c | 18 +++++++-------- samples/net/cloud/tagoio_http_post/prj.conf | 3 ++- samples/net/dsa/prj.conf | 2 +- samples/net/mdns_responder/prj.conf | 2 +- samples/net/mqtt_publisher/prj.conf | 1 + samples/net/mqtt_publisher/src/main.c | 14 ++++++------ samples/net/mqtt_sn_publisher/prj.conf | 2 +- samples/net/mqtt_sn_publisher/src/udp.c | 4 ++-- .../net/sockets/big_http_download/prj.conf | 2 +- .../net/sockets/big_http_download/sample.yaml | 5 ----- samples/net/sockets/can/prj.conf | 2 +- samples/net/sockets/coap_client/prj.conf | 2 +- samples/net/sockets/coap_server/prj.conf | 2 +- samples/net/sockets/dumb_http_server/prj.conf | 2 +- .../net/sockets/dumb_http_server/sample.yaml | 5 ----- .../net/sockets/dumb_http_server_mt/prj.conf | 2 +- .../sockets/dumb_http_server_mt/sample.yaml | 2 +- samples/net/sockets/echo/prj.conf | 2 +- samples/net/sockets/echo_async/prj.conf | 3 ++- samples/net/sockets/echo_async/sample.yaml | 5 ----- .../net/sockets/echo_async_select/prj.conf | 1 - .../net/sockets/echo_async_select/sample.yaml | 4 ---- .../src/socket_echo_select.c | 1 + samples/net/sockets/echo_client/prj.conf | 3 ++- samples/net/sockets/echo_server/prj.conf | 2 +- samples/net/sockets/echo_service/prj.conf | 1 - samples/net/sockets/http_client/prj.conf | 2 +- samples/net/sockets/http_get/prj.conf | 3 ++- samples/net/sockets/http_get/sample.yaml | 7 ------ samples/net/sockets/http_get/src/http_get.c | 2 +- samples/net/sockets/net_mgmt/prj.conf | 2 +- samples/net/sockets/packet/prj.conf | 2 +- samples/net/sockets/sntp_client/prj.conf | 1 + samples/net/sockets/sntp_client/sample.yaml | 18 --------------- samples/net/sockets/sntp_client/src/main.c | 6 ++--- samples/net/sockets/tcp/prj.conf | 2 +- samples/net/sockets/txtime/prj.conf | 2 +- samples/net/sockets/websocket_client/prj.conf | 2 +- samples/net/tftp_client/prj.conf | 1 + samples/net/tftp_client/src/tftp-client.c | 6 ++--- samples/net/zperf/prj.conf | 2 +- .../mgmt/mcumgr/smp_svr/overlay-udp.conf | 2 +- samples/subsys/mgmt/updatehub/prj.conf | 2 +- samples/subsys/modbus/tcp_gateway/prj.conf | 2 +- samples/subsys/modbus/tcp_server/prj.conf | 2 +- samples/subsys/video/tcpserversink/prj.conf | 2 +- 51 files changed, 85 insertions(+), 121 deletions(-) diff --git a/samples/net/cellular_modem/prj.conf b/samples/net/cellular_modem/prj.conf index c21435f3b6d..345d49bf463 100644 --- a/samples/net/cellular_modem/prj.conf +++ b/samples/net/cellular_modem/prj.conf @@ -1,6 +1,8 @@ # Copyright (c) 2023 Bjarki Arge Andreasen # SPDX-License-Identifier: Apache-2.0 +CONFIG_POSIX_API=y + # Networking CONFIG_NETWORKING=y CONFIG_NET_NATIVE=y diff --git a/samples/net/cellular_modem/src/main.c b/samples/net/cellular_modem/src/main.c index e02f5d7ead1..5fcfa40c64a 100644 --- a/samples/net/cellular_modem/src/main.c +++ b/samples/net/cellular_modem/src/main.c @@ -138,7 +138,7 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t printk("Opening UDP socket\n"); - socket_fd = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + socket_fd = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); if (socket_fd < 0) { printk("Failed to open socket (%d)\n", errno); return -1; @@ -161,8 +161,8 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t printk("Sending echo packet\n"); send_start_ms = k_uptime_get_32(); - ret = zsock_sendto(socket_fd, sample_test_packet, sizeof(sample_test_packet), 0, - ai_addr, ai_addrlen); + ret = sendto(socket_fd, sample_test_packet, sizeof(sample_test_packet), 0, + ai_addr, ai_addrlen); if (ret < sizeof(sample_test_packet)) { printk("Failed to send sample test packet\n"); @@ -170,7 +170,7 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t } printk("Receiving echoed packet\n"); - ret = zsock_recv(socket_fd, sample_recv_buffer, sizeof(sample_recv_buffer), 0); + ret = recv(socket_fd, sample_recv_buffer, sizeof(sample_recv_buffer), 0); if (ret != sizeof(sample_test_packet)) { if (ret == -1) { printk("Failed to receive echoed sample test packet (%d)\n", errno); @@ -202,7 +202,7 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t printk("Close UDP socket\n"); - ret = zsock_close(socket_fd); + ret = close(socket_fd); if (ret < 0) { printk("Failed to close socket\n"); return -1; @@ -224,7 +224,7 @@ int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint printk("Opening UDP socket\n"); - socket_fd = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + socket_fd = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); if (socket_fd < 0) { printk("Failed to open socket\n"); return -1; @@ -237,8 +237,8 @@ int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint printk("Sending %u packets\n", SAMPLE_TEST_TRANSMIT_PACKETS); send_start_ms = k_uptime_get_32(); for (uint32_t i = 0; i < SAMPLE_TEST_TRANSMIT_PACKETS; i++) { - ret = zsock_sendto(socket_fd, sample_test_packet, sizeof(sample_test_packet), 0, - ai_addr, ai_addrlen); + ret = sendto(socket_fd, sample_test_packet, sizeof(sample_test_packet), 0, + ai_addr, ai_addrlen); if (ret < sizeof(sample_test_packet)) { printk("Failed to send sample test packet\n"); @@ -250,7 +250,7 @@ int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint send_end_ms = k_uptime_get_32(); printk("Awaiting response from server\n"); - ret = zsock_recv(socket_fd, sample_recv_buffer, sizeof(sample_recv_buffer), 0); + ret = recv(socket_fd, sample_recv_buffer, sizeof(sample_recv_buffer), 0); if (ret != 2) { printk("Invalid response\n"); return -1; @@ -266,7 +266,7 @@ int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint (send_end_ms - send_start_ms)); printk("Close UDP socket\n"); - ret = zsock_close(socket_fd); + ret = close(socket_fd); if (ret < 0) { printk("Failed to close socket\n"); return -1; diff --git a/samples/net/cloud/aws_iot_mqtt/prj.conf b/samples/net/cloud/aws_iot_mqtt/prj.conf index b7f1d1f9857..30277ffb18c 100644 --- a/samples/net/cloud/aws_iot_mqtt/prj.conf +++ b/samples/net/cloud/aws_iot_mqtt/prj.conf @@ -14,6 +14,7 @@ CONFIG_REQUIRES_FULL_LIBC=y CONFIG_SNTP=y CONFIG_JSON_LIBRARY=y CONFIG_POSIX_CLOCK=y +CONFIG_POSIX_API=y # DNS CONFIG_DNS_RESOLVER=y diff --git a/samples/net/cloud/aws_iot_mqtt/src/main.c b/samples/net/cloud/aws_iot_mqtt/src/main.c index f1f56ffa27c..f911f429f2f 100644 --- a/samples/net/cloud/aws_iot_mqtt/src/main.c +++ b/samples/net/cloud/aws_iot_mqtt/src/main.c @@ -364,7 +364,7 @@ void aws_client_loop(void) { int rc; int timeout; - struct zsock_pollfd fds; + struct pollfd fds; aws_client_setup(); @@ -374,13 +374,13 @@ void aws_client_loop(void) } fds.fd = client_ctx.transport.tcp.sock; - fds.events = ZSOCK_POLLIN; + fds.events = POLLIN; for (;;) { timeout = mqtt_keepalive_time_left(&client_ctx); - rc = zsock_poll(&fds, 1u, timeout); + rc = poll(&fds, 1u, timeout); if (rc >= 0) { - if (fds.revents & ZSOCK_POLLIN) { + if (fds.revents & POLLIN) { rc = mqtt_input(&client_ctx); if (rc != 0) { LOG_ERR("Failed to read MQTT input: %d", rc); @@ -388,7 +388,7 @@ void aws_client_loop(void) } } - if (fds.revents & (ZSOCK_POLLHUP | ZSOCK_POLLERR)) { + if (fds.revents & (POLLHUP | POLLERR)) { LOG_ERR("Socket closed/error"); break; } @@ -417,7 +417,7 @@ void aws_client_loop(void) cleanup: mqtt_disconnect(&client_ctx); - zsock_close(fds.fd); + close(fds.fd); fds.fd = -1; } @@ -444,9 +444,9 @@ int sntp_sync_time(void) static int resolve_broker_addr(struct sockaddr_in *broker) { int ret; - struct zsock_addrinfo *ai = NULL; + struct addrinfo *ai = NULL; - const struct zsock_addrinfo hints = { + const struct addrinfo hints = { .ai_family = AF_INET, .ai_socktype = SOCK_STREAM, .ai_protocol = 0, @@ -454,19 +454,19 @@ static int resolve_broker_addr(struct sockaddr_in *broker) char port_string[6] = {0}; sprintf(port_string, "%d", AWS_BROKER_PORT); - ret = zsock_getaddrinfo(CONFIG_AWS_ENDPOINT, port_string, &hints, &ai); + ret = getaddrinfo(CONFIG_AWS_ENDPOINT, port_string, &hints, &ai); if (ret == 0) { char addr_str[INET_ADDRSTRLEN]; memcpy(broker, ai->ai_addr, MIN(ai->ai_addrlen, sizeof(struct sockaddr_storage))); - zsock_inet_ntop(AF_INET, &broker->sin_addr, addr_str, sizeof(addr_str)); + inet_ntop(AF_INET, &broker->sin_addr, addr_str, sizeof(addr_str)); LOG_INF("Resolved: %s:%u", addr_str, htons(broker->sin_port)); } else { LOG_ERR("failed to resolve hostname err = %d (errno = %d)", ret, errno); } - zsock_freeaddrinfo(ai); + freeaddrinfo(ai); return ret; } diff --git a/samples/net/cloud/mqtt_azure/prj.conf b/samples/net/cloud/mqtt_azure/prj.conf index 27b703bf585..2a88f746f5f 100644 --- a/samples/net/cloud/mqtt_azure/prj.conf +++ b/samples/net/cloud/mqtt_azure/prj.conf @@ -1,4 +1,5 @@ CONFIG_NETWORKING=y +CONFIG_POSIX_API=y # Disable IPv6 support CONFIG_NET_IPV6=n diff --git a/samples/net/cloud/mqtt_azure/src/main.c b/samples/net/cloud/mqtt_azure/src/main.c index 420750e416c..75590b5065d 100644 --- a/samples/net/cloud/mqtt_azure/src/main.c +++ b/samples/net/cloud/mqtt_azure/src/main.c @@ -34,7 +34,7 @@ static struct sockaddr socks5_proxy; #endif /* Socket Poll */ -static struct zsock_pollfd fds[1]; +static struct pollfd fds[1]; static int nfds; static bool mqtt_connected; @@ -50,8 +50,8 @@ static struct net_mgmt_event_callback l4_mgmt_cb; #endif #if defined(CONFIG_DNS_RESOLVER) -static struct zsock_addrinfo hints; -static struct zsock_addrinfo *haddr; +static struct addrinfo hints; +static struct addrinfo *haddr; #endif static K_SEM_DEFINE(mqtt_start, 0, 1); @@ -91,7 +91,7 @@ static void prepare_fds(struct mqtt_client *client) fds[0].fd = client->transport.tls.sock; } - fds[0].events = ZSOCK_POLLIN; + fds[0].events = POLLIN; nfds = 1; } @@ -108,7 +108,7 @@ static int wait(int timeout) return rc; } - rc = zsock_poll(fds, nfds, timeout); + rc = poll(fds, nfds, timeout); if (rc < 0) { LOG_ERR("poll error: %d", errno); return -errno; @@ -128,7 +128,7 @@ static void broker_init(void) net_ipaddr_copy(&broker4->sin_addr, &net_sin(haddr->ai_addr)->sin_addr); #else - zsock_inet_pton(AF_INET, SERVER_ADDR, &broker4->sin_addr); + inet_pton(AF_INET, SERVER_ADDR, &broker4->sin_addr); #endif #if defined(CONFIG_SOCKS) @@ -136,7 +136,7 @@ static void broker_init(void) proxy4->sin_family = AF_INET; proxy4->sin_port = htons(SOCKS5_PROXY_PORT); - zsock_inet_pton(AF_INET, SOCKS5_PROXY_ADDR, &proxy4->sin_addr); + inet_pton(AF_INET, SOCKS5_PROXY_ADDR, &proxy4->sin_addr); #endif } @@ -398,8 +398,8 @@ static int get_mqtt_broker_addrinfo(void) hints.ai_socktype = SOCK_STREAM; hints.ai_protocol = 0; - rc = zsock_getaddrinfo(CONFIG_SAMPLE_CLOUD_AZURE_HOSTNAME, "8883", - &hints, &haddr); + rc = getaddrinfo(CONFIG_SAMPLE_CLOUD_AZURE_HOSTNAME, "8883", + &hints, &haddr); if (rc == 0) { LOG_INF("DNS resolved for %s:%d", CONFIG_SAMPLE_CLOUD_AZURE_HOSTNAME, diff --git a/samples/net/cloud/tagoio_http_post/prj.conf b/samples/net/cloud/tagoio_http_post/prj.conf index cffd6feb142..9746de5e077 100644 --- a/samples/net/cloud/tagoio_http_post/prj.conf +++ b/samples/net/cloud/tagoio_http_post/prj.conf @@ -6,6 +6,8 @@ CONFIG_MAIN_STACK_SIZE=4096 # HEAP size (512 bytes) are enough to run DNS. CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=4096 +CONFIG_POSIX_API=y + # Networking config CONFIG_NETWORKING=y CONFIG_NET_IPV4=y @@ -15,7 +17,6 @@ CONFIG_NET_SHELL=y # Sockets CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_POLL_MAX=4 # Network driver config diff --git a/samples/net/dsa/prj.conf b/samples/net/dsa/prj.conf index 6309976db06..153ae38526b 100644 --- a/samples/net/dsa/prj.conf +++ b/samples/net/dsa/prj.conf @@ -42,7 +42,7 @@ CONFIG_NET_DSA_LOG_LEVEL_INF=y # Support for lan1..3 as RAW_SOCKETS CONFIG_NET_SOCKETS=y CONFIG_NET_SOCKETS_PACKET=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y # How many traffic classes to enable CONFIG_NET_TC_TX_COUNT=6 diff --git a/samples/net/mdns_responder/prj.conf b/samples/net/mdns_responder/prj.conf index cb77ffadffd..3db06cbb2ac 100644 --- a/samples/net/mdns_responder/prj.conf +++ b/samples/net/mdns_responder/prj.conf @@ -40,4 +40,4 @@ CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2" CONFIG_NET_CONFIG_MY_IPV4_GW="192.0.2.2" CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y diff --git a/samples/net/mqtt_publisher/prj.conf b/samples/net/mqtt_publisher/prj.conf index 9743597039e..f5ea4e3f11e 100644 --- a/samples/net/mqtt_publisher/prj.conf +++ b/samples/net/mqtt_publisher/prj.conf @@ -9,6 +9,7 @@ CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT=2 CONFIG_PRINTK=y CONFIG_STDOUT_CONSOLE=y +CONFIG_POSIX_API=y # Enable IPv6 support CONFIG_NET_IPV6=n diff --git a/samples/net/mqtt_publisher/src/main.c b/samples/net/mqtt_publisher/src/main.c index 8ff34f271c2..2d8408d1191 100644 --- a/samples/net/mqtt_publisher/src/main.c +++ b/samples/net/mqtt_publisher/src/main.c @@ -50,7 +50,7 @@ static APP_BMEM struct sockaddr_storage broker; static APP_BMEM struct sockaddr socks5_proxy; #endif -static APP_BMEM struct zsock_pollfd fds[1]; +static APP_BMEM struct pollfd fds[1]; static APP_BMEM int nfds; static APP_BMEM bool connected; @@ -116,7 +116,7 @@ static void prepare_fds(struct mqtt_client *client) } #endif - fds[0].events = ZSOCK_POLLIN; + fds[0].events = POLLIN; nfds = 1; } @@ -130,7 +130,7 @@ static int wait(int timeout) int ret = 0; if (nfds > 0) { - ret = zsock_poll(fds, nfds, timeout); + ret = poll(fds, nfds, timeout); if (ret < 0) { LOG_ERR("poll error: %d", errno); } @@ -269,27 +269,27 @@ static void broker_init(void) broker6->sin6_family = AF_INET6; broker6->sin6_port = htons(SERVER_PORT); - zsock_inet_pton(AF_INET6, SERVER_ADDR, &broker6->sin6_addr); + inet_pton(AF_INET6, SERVER_ADDR, &broker6->sin6_addr); #if defined(CONFIG_SOCKS) struct sockaddr_in6 *proxy6 = (struct sockaddr_in6 *)&socks5_proxy; proxy6->sin6_family = AF_INET6; proxy6->sin6_port = htons(SOCKS5_PROXY_PORT); - zsock_inet_pton(AF_INET6, SOCKS5_PROXY_ADDR, &proxy6->sin6_addr); + inet_pton(AF_INET6, SOCKS5_PROXY_ADDR, &proxy6->sin6_addr); #endif #else struct sockaddr_in *broker4 = (struct sockaddr_in *)&broker; broker4->sin_family = AF_INET; broker4->sin_port = htons(SERVER_PORT); - zsock_inet_pton(AF_INET, SERVER_ADDR, &broker4->sin_addr); + inet_pton(AF_INET, SERVER_ADDR, &broker4->sin_addr); #if defined(CONFIG_SOCKS) struct sockaddr_in *proxy4 = (struct sockaddr_in *)&socks5_proxy; proxy4->sin_family = AF_INET; proxy4->sin_port = htons(SOCKS5_PROXY_PORT); - zsock_inet_pton(AF_INET, SOCKS5_PROXY_ADDR, &proxy4->sin_addr); + inet_pton(AF_INET, SOCKS5_PROXY_ADDR, &proxy4->sin_addr); #endif #endif } diff --git a/samples/net/mqtt_sn_publisher/prj.conf b/samples/net/mqtt_sn_publisher/prj.conf index f38d4ea6ec3..367ba8082f4 100644 --- a/samples/net/mqtt_sn_publisher/prj.conf +++ b/samples/net/mqtt_sn_publisher/prj.conf @@ -4,7 +4,7 @@ CONFIG_NET_UDP=y CONFIG_NET_IPV4=y CONFIG_NET_IPV6=n CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y CONFIG_POSIX_MAX_FDS=6 CONFIG_NET_CONNECTION_MANAGER=y diff --git a/samples/net/mqtt_sn_publisher/src/udp.c b/samples/net/mqtt_sn_publisher/src/udp.c index 70a09bdb89d..045a676dbd1 100644 --- a/samples/net/mqtt_sn_publisher/src/udp.c +++ b/samples/net/mqtt_sn_publisher/src/udp.c @@ -115,8 +115,8 @@ static void process_thread(void) LOG_DBG("Parsing MQTT host IP " CONFIG_NET_SAMPLE_MQTT_SN_GATEWAY_IP); gateway.sin_family = AF_INET; gateway.sin_port = htons(CONFIG_NET_SAMPLE_MQTT_SN_GATEWAY_PORT); - err = zsock_inet_pton(AF_INET, CONFIG_NET_SAMPLE_MQTT_SN_GATEWAY_IP, &gateway.sin_addr); - __ASSERT(err == 1, "zsock_inet_pton() failed %d", err); + err = inet_pton(AF_INET, CONFIG_NET_SAMPLE_MQTT_SN_GATEWAY_IP, &gateway.sin_addr); + __ASSERT(err == 1, "inet_pton() failed %d", err); LOG_INF("Waiting for connection..."); LOG_HEXDUMP_DBG(&gateway, sizeof(gateway), "gateway"); diff --git a/samples/net/sockets/big_http_download/prj.conf b/samples/net/sockets/big_http_download/prj.conf index 324eb765af2..988a81908bd 100644 --- a/samples/net/sockets/big_http_download/prj.conf +++ b/samples/net/sockets/big_http_download/prj.conf @@ -10,7 +10,7 @@ CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y CONFIG_NET_CONTEXT_RCVTIMEO=y CONFIG_NET_CONTEXT_SNDTIMEO=y diff --git a/samples/net/sockets/big_http_download/sample.yaml b/samples/net/sockets/big_http_download/sample.yaml index 313d0a135c7..b8777a4e871 100644 --- a/samples/net/sockets/big_http_download/sample.yaml +++ b/samples/net/sockets/big_http_download/sample.yaml @@ -12,11 +12,6 @@ common: tests: sample.net.sockets.big_http_download: extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=y - sample.net.sockets.big_http_download.posix: - filter: not CONFIG_NET_SOCKETS_OFFLOAD - extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=n - CONFIG_POSIX_API=y sample.net.sockets.big_http_download.ci: extra_args: OVERLAY_CONFIG=overlay-ci.conf diff --git a/samples/net/sockets/can/prj.conf b/samples/net/sockets/can/prj.conf index 20afb8c1518..04ea69917ed 100644 --- a/samples/net/sockets/can/prj.conf +++ b/samples/net/sockets/can/prj.conf @@ -7,7 +7,7 @@ CONFIG_NET_DRIVERS=y CONFIG_NET_CANBUS=y CONFIG_NET_SOCKETS=y CONFIG_NET_SOCKETS_CAN=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y CONFIG_NET_IPV6=n CONFIG_NET_IPV4=n diff --git a/samples/net/sockets/coap_client/prj.conf b/samples/net/sockets/coap_client/prj.conf index b0df3759b22..1e9daa2e44c 100644 --- a/samples/net/sockets/coap_client/prj.conf +++ b/samples/net/sockets/coap_client/prj.conf @@ -5,8 +5,8 @@ CONFIG_NET_IPV6=y CONFIG_NET_UDP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_POLL_MAX=4 +CONFIG_POSIX_API=y CONFIG_COAP=y diff --git a/samples/net/sockets/coap_server/prj.conf b/samples/net/sockets/coap_server/prj.conf index 59d444db456..470caa6b448 100644 --- a/samples/net/sockets/coap_server/prj.conf +++ b/samples/net/sockets/coap_server/prj.conf @@ -5,7 +5,7 @@ CONFIG_NET_UDP=y # Socket CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y CONFIG_NET_SOCKETS_POLL_MAX=4 # CoAP diff --git a/samples/net/sockets/dumb_http_server/prj.conf b/samples/net/sockets/dumb_http_server/prj.conf index 1c826c38f9d..a1e6b9efa8d 100644 --- a/samples/net/sockets/dumb_http_server/prj.conf +++ b/samples/net/sockets/dumb_http_server/prj.conf @@ -7,7 +7,7 @@ CONFIG_NET_IPV4=y CONFIG_NET_IPV6=n CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y # Network driver config CONFIG_TEST_RANDOM_GENERATOR=y diff --git a/samples/net/sockets/dumb_http_server/sample.yaml b/samples/net/sockets/dumb_http_server/sample.yaml index 23eee0b0d48..55a8d9a9673 100644 --- a/samples/net/sockets/dumb_http_server/sample.yaml +++ b/samples/net/sockets/dumb_http_server/sample.yaml @@ -13,11 +13,6 @@ common: tests: sample.net.sockets.dumb_http_server: extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=y - sample.net.sockets.dumb_http_server.posix: - filter: not CONFIG_NET_SOCKETS_OFFLOAD - extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=n - CONFIG_POSIX_API=y sample.net.sockets.dumb_http_server.netusb: depends_on: usb_device diff --git a/samples/net/sockets/dumb_http_server_mt/prj.conf b/samples/net/sockets/dumb_http_server_mt/prj.conf index 4464f0590df..af851a0406e 100644 --- a/samples/net/sockets/dumb_http_server_mt/prj.conf +++ b/samples/net/sockets/dumb_http_server_mt/prj.conf @@ -3,6 +3,7 @@ CONFIG_TEST_RANDOM_GENERATOR=y # POSIX options CONFIG_POSIX_MAX_FDS=20 +CONFIG_POSIX_API=y # Networking config CONFIG_NETWORKING=y @@ -11,7 +12,6 @@ CONFIG_NET_IPV6=y CONFIG_NET_TCP=y CONFIG_NET_UDP=n CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_MAX_CONN=20 CONFIG_NET_MAX_CONTEXTS=20 CONFIG_NET_STATISTICS=y diff --git a/samples/net/sockets/dumb_http_server_mt/sample.yaml b/samples/net/sockets/dumb_http_server_mt/sample.yaml index 090b8bde12f..fa69fea8c97 100644 --- a/samples/net/sockets/dumb_http_server_mt/sample.yaml +++ b/samples/net/sockets/dumb_http_server_mt/sample.yaml @@ -12,5 +12,5 @@ common: tests: sample.net.sockets.dumb_http_server_mt: extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=y + - CONFIG_POSIX_API=y platform_exclude: esp32s2_saola diff --git a/samples/net/sockets/echo/prj.conf b/samples/net/sockets/echo/prj.conf index 3d25caa2924..33729784d8e 100644 --- a/samples/net/sockets/echo/prj.conf +++ b/samples/net/sockets/echo/prj.conf @@ -1,5 +1,6 @@ # General config CONFIG_MAIN_STACK_SIZE=1200 +CONFIG_POSIX_API=y # Networking config CONFIG_NETWORKING=y @@ -7,7 +8,6 @@ CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_IPV4_MAPPING_TO_IPV6=y # Network driver config diff --git a/samples/net/sockets/echo_async/prj.conf b/samples/net/sockets/echo_async/prj.conf index 21291009557..2b0e18a3d9d 100644 --- a/samples/net/sockets/echo_async/prj.conf +++ b/samples/net/sockets/echo_async/prj.conf @@ -8,9 +8,10 @@ CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_POLL_MAX=5 +CONFIG_POSIX_API=y + # Network driver config CONFIG_TEST_RANDOM_GENERATOR=y diff --git a/samples/net/sockets/echo_async/sample.yaml b/samples/net/sockets/echo_async/sample.yaml index 9c88a2d5ea5..39b33bd3165 100644 --- a/samples/net/sockets/echo_async/sample.yaml +++ b/samples/net/sockets/echo_async/sample.yaml @@ -11,9 +11,4 @@ common: tests: sample.net.sockets.echo_async: extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=y - sample.net.sockets.echo_async.posix: - filter: not CONFIG_NET_SOCKETS_OFFLOAD - extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=n - CONFIG_POSIX_API=y diff --git a/samples/net/sockets/echo_async_select/prj.conf b/samples/net/sockets/echo_async_select/prj.conf index 377b2eef8af..278ef31e818 100644 --- a/samples/net/sockets/echo_async_select/prj.conf +++ b/samples/net/sockets/echo_async_select/prj.conf @@ -9,7 +9,6 @@ CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_POLL_MAX=5 # Network driver config diff --git a/samples/net/sockets/echo_async_select/sample.yaml b/samples/net/sockets/echo_async_select/sample.yaml index 3353773ec0b..4a9d84172d0 100644 --- a/samples/net/sockets/echo_async_select/sample.yaml +++ b/samples/net/sockets/echo_async_select/sample.yaml @@ -11,8 +11,4 @@ common: tests: sample.net.sockets.echo_async_select: extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=y - sample.net.sockets.echo_async_select.posix: - extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=n - CONFIG_POSIX_API=y diff --git a/samples/net/sockets/echo_async_select/src/socket_echo_select.c b/samples/net/sockets/echo_async_select/src/socket_echo_select.c index ae949b1df30..b26bef9e404 100644 --- a/samples/net/sockets/echo_async_select/src/socket_echo_select.c +++ b/samples/net/sockets/echo_async_select/src/socket_echo_select.c @@ -25,6 +25,7 @@ #else #include +#include #include #include diff --git a/samples/net/sockets/echo_client/prj.conf b/samples/net/sockets/echo_client/prj.conf index a6cace9c179..dc75a907f41 100644 --- a/samples/net/sockets/echo_client/prj.conf +++ b/samples/net/sockets/echo_client/prj.conf @@ -5,10 +5,11 @@ CONFIG_NET_TCP=y CONFIG_NET_IPV6=y CONFIG_NET_IPV4=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_POLL_MAX=4 CONFIG_NET_CONNECTION_MANAGER=y +CONFIG_POSIX_API=y + # Kernel options CONFIG_MAIN_STACK_SIZE=2048 CONFIG_ENTROPY_GENERATOR=y diff --git a/samples/net/sockets/echo_server/prj.conf b/samples/net/sockets/echo_server/prj.conf index 8fcb936b08f..e88c98eda39 100644 --- a/samples/net/sockets/echo_server/prj.conf +++ b/samples/net/sockets/echo_server/prj.conf @@ -5,7 +5,7 @@ CONFIG_NET_TCP=y CONFIG_NET_IPV6=y CONFIG_NET_IPV4=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y CONFIG_POSIX_MAX_FDS=6 CONFIG_NET_CONNECTION_MANAGER=y diff --git a/samples/net/sockets/echo_service/prj.conf b/samples/net/sockets/echo_service/prj.conf index c39159ea7e4..d7ffe738352 100644 --- a/samples/net/sockets/echo_service/prj.conf +++ b/samples/net/sockets/echo_service/prj.conf @@ -9,7 +9,6 @@ CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_IPV4_MAPPING_TO_IPV6=y CONFIG_POSIX_MAX_FDS=10 CONFIG_NET_MAX_CONN=5 diff --git a/samples/net/sockets/http_client/prj.conf b/samples/net/sockets/http_client/prj.conf index dda4d34b883..f83fd882f95 100644 --- a/samples/net/sockets/http_client/prj.conf +++ b/samples/net/sockets/http_client/prj.conf @@ -7,8 +7,8 @@ CONFIG_NET_SHELL=y # Sockets CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_POLL_MAX=4 +CONFIG_POSIX_API=y # Network driver config CONFIG_TEST_RANDOM_GENERATOR=y diff --git a/samples/net/sockets/http_get/prj.conf b/samples/net/sockets/http_get/prj.conf index 57d4d4c55c0..a4f5e966a94 100644 --- a/samples/net/sockets/http_get/prj.conf +++ b/samples/net/sockets/http_get/prj.conf @@ -8,7 +8,8 @@ CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y + +CONFIG_POSIX_API=y CONFIG_DNS_RESOLVER=y CONFIG_DNS_SERVER_IP_ADDRESSES=y diff --git a/samples/net/sockets/http_get/sample.yaml b/samples/net/sockets/http_get/sample.yaml index 4bdb915f2e5..4e454da50a7 100644 --- a/samples/net/sockets/http_get/sample.yaml +++ b/samples/net/sockets/http_get/sample.yaml @@ -10,19 +10,12 @@ common: - socket tests: sample.net.sockets.http_get: - harness: net - extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=y - # Forcibly defines CONFIG_POSIX_API, which is incompatible with - # CONFIG_NET_SOCKETS_POSIX_NAMES. - sample.net.sockets.http_get.posix: filter: not CONFIG_NET_SOCKETS_OFFLOAD and not CONFIG_NATIVE_LIBC harness: net platform_exclude: - cc3220sf_launchxl - cc3235sf_launchxl extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=n - CONFIG_POSIX_API=y sample.net.sockets.http_get.offload.simplelink: platform_allow: cc3220sf_launchxl diff --git a/samples/net/sockets/http_get/src/http_get.c b/samples/net/sockets/http_get/src/http_get.c index 7f654ecc82e..c6d16b53461 100644 --- a/samples/net/sockets/http_get/src/http_get.c +++ b/samples/net/sockets/http_get/src/http_get.c @@ -7,7 +7,7 @@ #include #include -#if !defined(__ZEPHYR__) || defined(CONFIG_POSIX_API) +#if !defined(__ZEPHYR__) #include #include diff --git a/samples/net/sockets/net_mgmt/prj.conf b/samples/net/sockets/net_mgmt/prj.conf index 4c9720313c8..243cce21735 100644 --- a/samples/net/sockets/net_mgmt/prj.conf +++ b/samples/net/sockets/net_mgmt/prj.conf @@ -5,7 +5,7 @@ CONFIG_NET_TCP=y CONFIG_NET_IPV6=y CONFIG_NET_IPV4=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y CONFIG_POSIX_MAX_FDS=6 CONFIG_NET_SOCKETS_NET_MGMT=y CONFIG_NET_MGMT_EVENT=y diff --git a/samples/net/sockets/packet/prj.conf b/samples/net/sockets/packet/prj.conf index 9e8503fcc43..d01c89254e1 100644 --- a/samples/net/sockets/packet/prj.conf +++ b/samples/net/sockets/packet/prj.conf @@ -6,7 +6,7 @@ CONFIG_NET_IPV6=n CONFIG_NET_IPV4=n CONFIG_NET_MAX_CONTEXTS=10 CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y CONFIG_POSIX_MAX_FDS=6 CONFIG_NET_CONTEXT_RCVTIMEO=y CONFIG_NET_MGMT=y diff --git a/samples/net/sockets/sntp_client/prj.conf b/samples/net/sockets/sntp_client/prj.conf index bfcd3092ac6..56c9982fc59 100644 --- a/samples/net/sockets/sntp_client/prj.conf +++ b/samples/net/sockets/sntp_client/prj.conf @@ -1,5 +1,6 @@ # General config CONFIG_REQUIRES_FULL_LIBC=y +CONFIG_POSIX_API=y # Networking config CONFIG_NETWORKING=y diff --git a/samples/net/sockets/sntp_client/sample.yaml b/samples/net/sockets/sntp_client/sample.yaml index 65d4f2f3b2c..aba249df18a 100644 --- a/samples/net/sockets/sntp_client/sample.yaml +++ b/samples/net/sockets/sntp_client/sample.yaml @@ -9,21 +9,3 @@ tests: platform_allow: - qemu_x86 - native_sim - sample.net.sockets.sntp_client.posix_names: - platform_allow: - - qemu_x86 - - native_sim - extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=y - sample.net.sockets.sntp_client.posix: - platform_allow: - - qemu_x86 - - native_sim - extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=n - - CONFIG_POSIX_API=y - sample.net.sockets.sntp_client.native_posix: - platform_allow: native_posix - extra_configs: - - CONFIG_NET_SOCKETS_POSIX_NAMES=n - - CONFIG_POSIX_API=n diff --git a/samples/net/sockets/sntp_client/src/main.c b/samples/net/sockets/sntp_client/src/main.c index 7f17287d04f..585ce1d1b43 100644 --- a/samples/net/sockets/sntp_client/src/main.c +++ b/samples/net/sockets/sntp_client/src/main.c @@ -9,9 +9,7 @@ LOG_MODULE_REGISTER(net_sntp_client_sample, LOG_LEVEL_DBG); #include -#ifdef CONFIG_POSIX_API #include -#endif #include "config.h" @@ -31,7 +29,7 @@ int main(void) memset(&addr, 0, sizeof(addr)); addr.sin_family = AF_INET; addr.sin_port = htons(SNTP_PORT); - zsock_inet_pton(AF_INET, SERVER_ADDR, &addr.sin_addr); + inet_pton(AF_INET, SERVER_ADDR, &addr.sin_addr); rv = sntp_init(&ctx, (struct sockaddr *) &addr, sizeof(struct sockaddr_in)); @@ -58,7 +56,7 @@ int main(void) memset(&addr6, 0, sizeof(addr6)); addr6.sin6_family = AF_INET6; addr6.sin6_port = htons(SNTP_PORT); - zsock_inet_pton(AF_INET6, SERVER_ADDR6, &addr6.sin6_addr); + inet_pton(AF_INET6, SERVER_ADDR6, &addr6.sin6_addr); rv = sntp_init(&ctx, (struct sockaddr *) &addr6, sizeof(struct sockaddr_in6)); diff --git a/samples/net/sockets/tcp/prj.conf b/samples/net/sockets/tcp/prj.conf index a442918f337..f3660f4ac56 100644 --- a/samples/net/sockets/tcp/prj.conf +++ b/samples/net/sockets/tcp/prj.conf @@ -3,7 +3,7 @@ CONFIG_REQUIRES_FULL_LIBC=y CONFIG_NETWORKING=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y diff --git a/samples/net/sockets/txtime/prj.conf b/samples/net/sockets/txtime/prj.conf index bccf8e18528..39b909fddd8 100644 --- a/samples/net/sockets/txtime/prj.conf +++ b/samples/net/sockets/txtime/prj.conf @@ -5,7 +5,7 @@ CONFIG_NET_TCP=n CONFIG_NET_IPV6=y CONFIG_NET_IPV4=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y +CONFIG_POSIX_API=y CONFIG_NET_CONTEXT_PRIORITY=y CONFIG_NET_CONTEXT_TXTIME=y CONFIG_NET_TC_TX_COUNT=7 diff --git a/samples/net/sockets/websocket_client/prj.conf b/samples/net/sockets/websocket_client/prj.conf index f625062a0f8..7b8a237fb68 100644 --- a/samples/net/sockets/websocket_client/prj.conf +++ b/samples/net/sockets/websocket_client/prj.conf @@ -8,7 +8,6 @@ CONFIG_NET_STATISTICS=y # Sockets CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_POLL_MAX=4 # Network driver config @@ -42,3 +41,4 @@ CONFIG_NET_LOG=y CONFIG_MAIN_STACK_SIZE=2048 CONFIG_HEAP_MEM_POOL_SIZE=1500 +CONFIG_POSIX_API=y diff --git a/samples/net/tftp_client/prj.conf b/samples/net/tftp_client/prj.conf index 9a6ce71ca06..38d97c45086 100644 --- a/samples/net/tftp_client/prj.conf +++ b/samples/net/tftp_client/prj.conf @@ -18,3 +18,4 @@ CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1" CONFIG_DNS_RESOLVER=n CONFIG_TFTP_LIB=y +CONFIG_POSIX_API=y diff --git a/samples/net/tftp_client/src/tftp-client.c b/samples/net/tftp_client/src/tftp-client.c index 018858a281f..be65dadd5ea 100644 --- a/samples/net/tftp_client/src/tftp-client.c +++ b/samples/net/tftp_client/src/tftp-client.c @@ -37,13 +37,13 @@ static void tftp_event_callback(const struct tftp_evt *evt) static int tftp_init(const char *hostname) { struct sockaddr remote_addr; - struct zsock_addrinfo *res, hints = {0}; + struct addrinfo *res, hints = {0}; int ret; /* Setup TFTP server address */ hints.ai_socktype = SOCK_DGRAM; - ret = zsock_getaddrinfo(hostname, CONFIG_TFTP_APP_PORT, &hints, &res); + ret = getaddrinfo(hostname, CONFIG_TFTP_APP_PORT, &hints, &res); if (ret != 0) { LOG_ERR("Unable to resolve address"); /* DNS error codes don't align with normal errors */ @@ -51,7 +51,7 @@ static int tftp_init(const char *hostname) } memcpy(&remote_addr, res->ai_addr, sizeof(remote_addr)); - zsock_freeaddrinfo(res); + freeaddrinfo(res); /* Save sockaddr into TFTP client handler */ memcpy(&client.server, &remote_addr, sizeof(client.server)); diff --git a/samples/net/zperf/prj.conf b/samples/net/zperf/prj.conf index 230e0462333..e355986210b 100644 --- a/samples/net/zperf/prj.conf +++ b/samples/net/zperf/prj.conf @@ -19,9 +19,9 @@ CONFIG_NET_IF_UNICAST_IPV4_ADDR_COUNT=1 CONFIG_NET_MAX_CONTEXTS=5 CONFIG_NET_TC_TX_COUNT=1 CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_SOCKETS_POLL_MAX=9 CONFIG_POSIX_MAX_FDS=8 +CONFIG_POSIX_API=y CONFIG_INIT_STACKS=y CONFIG_TEST_RANDOM_GENERATOR=y diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/overlay-udp.conf b/samples/subsys/mgmt/mcumgr/smp_svr/overlay-udp.conf index 632d0790d9d..99f80bbe5cb 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/overlay-udp.conf +++ b/samples/subsys/mgmt/mcumgr/smp_svr/overlay-udp.conf @@ -9,8 +9,8 @@ CONFIG_NET_UDP=y CONFIG_NET_IPV4=y CONFIG_NET_IPV6=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_NET_CONNECTION_MANAGER=y CONFIG_NET_CONFIG_SETTINGS=y CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.168.1.1" CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8::1" +CONFIG_POSIX_API=y diff --git a/samples/subsys/mgmt/updatehub/prj.conf b/samples/subsys/mgmt/updatehub/prj.conf index 2a84998f366..0ea9be14f7a 100644 --- a/samples/subsys/mgmt/updatehub/prj.conf +++ b/samples/subsys/mgmt/updatehub/prj.conf @@ -12,11 +12,11 @@ CONFIG_MPU_ALLOW_FLASH_WRITE=y CONFIG_NETWORKING=y CONFIG_NET_UDP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_COAP=y CONFIG_DNS_RESOLVER=y CONFIG_JSON_LIBRARY=y CONFIG_HWINFO=y +CONFIG_POSIX_API=y # Turn on the updatehub CONFIG_UPDATEHUB=y diff --git a/samples/subsys/modbus/tcp_gateway/prj.conf b/samples/subsys/modbus/tcp_gateway/prj.conf index ac72c3d468d..1129c8ac1ae 100644 --- a/samples/subsys/modbus/tcp_gateway/prj.conf +++ b/samples/subsys/modbus/tcp_gateway/prj.conf @@ -1,5 +1,6 @@ CONFIG_LOG=y CONFIG_MAIN_STACK_SIZE=1200 +CONFIG_POSIX_API=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y @@ -16,7 +17,6 @@ CONFIG_NET_IPV4=y CONFIG_NET_IPV6=n CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y # Network address config CONFIG_NET_CONFIG_SETTINGS=y diff --git a/samples/subsys/modbus/tcp_server/prj.conf b/samples/subsys/modbus/tcp_server/prj.conf index 0bfb27042fc..210952bfb4f 100644 --- a/samples/subsys/modbus/tcp_server/prj.conf +++ b/samples/subsys/modbus/tcp_server/prj.conf @@ -1,6 +1,7 @@ CONFIG_LOG=y CONFIG_GPIO=y CONFIG_MAIN_STACK_SIZE=1200 +CONFIG_POSIX_API=y CONFIG_MODBUS=y CONFIG_MODBUS_ROLE_SERVER=y @@ -14,7 +15,6 @@ CONFIG_NET_IPV4=y CONFIG_NET_IPV6=n CONFIG_NET_TCP=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y # Network address config CONFIG_NET_CONFIG_SETTINGS=y diff --git a/samples/subsys/video/tcpserversink/prj.conf b/samples/subsys/video/tcpserversink/prj.conf index 6b04ec2493b..43ddea77f51 100644 --- a/samples/subsys/video/tcpserversink/prj.conf +++ b/samples/subsys/video/tcpserversink/prj.conf @@ -3,8 +3,8 @@ CONFIG_NETWORKING=y CONFIG_NET_TCP=y CONFIG_NET_IPV4=y CONFIG_NET_SOCKETS=y -CONFIG_NET_SOCKETS_POSIX_NAMES=y CONFIG_POSIX_MAX_FDS=6 +CONFIG_POSIX_API=y # Kernel options CONFIG_MAIN_STACK_SIZE=2048 From f27a26f9ec8aeb491cb9aac6c9281d8834c22fe6 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 7 Mar 2024 18:17:02 +0200 Subject: [PATCH 1532/2402] mgmt: updatehub: Use zsock_ API functions The library should be using internal socket API functions so that we do not need to depend on POSIX_API. Signed-off-by: Jukka Rissanen --- subsys/mgmt/updatehub/Kconfig | 1 - subsys/mgmt/updatehub/updatehub.c | 32 +++++++++++++++---------------- 2 files changed, 16 insertions(+), 17 deletions(-) diff --git a/subsys/mgmt/updatehub/Kconfig b/subsys/mgmt/updatehub/Kconfig index 517f9236737..bc1c4fb1d1c 100644 --- a/subsys/mgmt/updatehub/Kconfig +++ b/subsys/mgmt/updatehub/Kconfig @@ -10,7 +10,6 @@ menuconfig UPDATEHUB depends on NETWORKING depends on NET_UDP depends on NET_SOCKETS - depends on NET_SOCKETS_POSIX_NAMES depends on COAP depends on DNS_RESOLVER depends on JSON_LIBRARY diff --git a/subsys/mgmt/updatehub/updatehub.c b/subsys/mgmt/updatehub/updatehub.c index 0bc14f3b886..886f10634bc 100644 --- a/subsys/mgmt/updatehub/updatehub.c +++ b/subsys/mgmt/updatehub/updatehub.c @@ -67,7 +67,7 @@ static struct updatehub_context { uint8_t uri_path[MAX_PATH_SIZE]; uint8_t payload[MAX_PAYLOAD_SIZE]; int downloaded_size; - struct pollfd fds[1]; + struct zsock_pollfd fds[1]; int sock; int nfds; } ctx; @@ -99,7 +99,7 @@ static int bin2hex_str(uint8_t *bin, size_t bin_len, char *str, size_t str_buf_l static void wait_fds(void) { - if (poll(ctx.fds, ctx.nfds, NETWORK_TIMEOUT) < 0) { + if (zsock_poll(ctx.fds, ctx.nfds, NETWORK_TIMEOUT) < 0) { LOG_ERR("Error in poll"); } } @@ -107,7 +107,7 @@ static void wait_fds(void) static void prepare_fds(void) { ctx.fds[ctx.nfds].fd = ctx.sock; - ctx.fds[ctx.nfds].events = POLLIN; + ctx.fds[ctx.nfds].events = ZSOCK_POLLIN; ctx.nfds++; } @@ -153,7 +153,7 @@ static void cleanup_connection(void) { int i; - if (close(ctx.sock) < 0) { + if (zsock_close(ctx.sock) < 0) { LOG_ERR("Could not close the socket"); } @@ -167,8 +167,8 @@ static void cleanup_connection(void) static bool start_coap_client(void) { - struct addrinfo *addr; - struct addrinfo hints; + struct zsock_addrinfo *addr; + struct zsock_addrinfo hints; int resolve_attempts = 10; int ret = -1; @@ -193,7 +193,7 @@ static bool start_coap_client(void) #endif while (resolve_attempts--) { - ret = getaddrinfo(UPDATEHUB_SERVER, port, &hints, &addr); + ret = zsock_getaddrinfo(UPDATEHUB_SERVER, port, &hints, &addr); if (ret == 0) { break; } @@ -206,7 +206,7 @@ static bool start_coap_client(void) ret = 1; - ctx.sock = socket(addr->ai_family, SOCK_DGRAM, protocol); + ctx.sock = zsock_socket(addr->ai_family, SOCK_DGRAM, protocol); if (ctx.sock < 0) { LOG_ERR("Failed to create UDP socket"); goto error; @@ -215,19 +215,19 @@ static bool start_coap_client(void) ret = -1; #if defined(CONFIG_UPDATEHUB_DTLS) - if (setsockopt(ctx.sock, SOL_TLS, TLS_SEC_TAG_LIST, - sec_list, sizeof(sec_list)) < 0) { + if (zsock_setsockopt(ctx.sock, SOL_TLS, TLS_SEC_TAG_LIST, + sec_list, sizeof(sec_list)) < 0) { LOG_ERR("Failed to set TLS_TAG option"); goto error; } - if (setsockopt(ctx.sock, SOL_TLS, TLS_PEER_VERIFY, &verify, sizeof(int)) < 0) { + if (zsock_setsockopt(ctx.sock, SOL_TLS, TLS_PEER_VERIFY, &verify, sizeof(int)) < 0) { LOG_ERR("Failed to set TLS_PEER_VERIFY option"); goto error; } #endif - if (connect(ctx.sock, addr->ai_addr, addr->ai_addrlen) < 0) { + if (zsock_connect(ctx.sock, addr->ai_addr, addr->ai_addrlen) < 0) { LOG_ERR("Cannot connect to UDP remote"); goto error; } @@ -236,7 +236,7 @@ static bool start_coap_client(void) ret = 0; error: - freeaddrinfo(addr); + zsock_freeaddrinfo(addr); if (ret > 0) { cleanup_connection(); @@ -345,7 +345,7 @@ static int send_request(enum coap_msgtype msgtype, enum coap_method method, goto error; } - ret = send(ctx.sock, request_packet.data, request_packet.offset, 0); + ret = zsock_send(ctx.sock, request_packet.data, request_packet.offset, 0); if (ret < 0) { LOG_ERR("Could not send request"); goto error; @@ -425,7 +425,7 @@ static void install_update_cb(void) wait_fds(); - rcvd = recv(ctx.sock, data, MAX_DOWNLOAD_DATA, MSG_DONTWAIT); + rcvd = zsock_recv(ctx.sock, data, MAX_DOWNLOAD_DATA, ZSOCK_MSG_DONTWAIT); if (rcvd <= 0) { ctx.code_status = UPDATEHUB_NETWORKING_ERROR; LOG_ERR("Could not receive data"); @@ -693,7 +693,7 @@ static void probe_cb(char *metadata, size_t metadata_size) wait_fds(); - rcvd = recv(ctx.sock, tmp, MAX_DOWNLOAD_DATA, MSG_DONTWAIT); + rcvd = zsock_recv(ctx.sock, tmp, MAX_DOWNLOAD_DATA, ZSOCK_MSG_DONTWAIT); if (rcvd <= 0) { LOG_ERR("Could not receive data"); ctx.code_status = UPDATEHUB_NETWORKING_ERROR; From 515f5473480d89404b308a076363c06914d07a03 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 08:00:19 +0200 Subject: [PATCH 1533/2402] mgmt: mcumgr: transport: udp: Select POSIX_API The NET_SOCKET_POSIX_NAMES is deprecated so enable POSIX_API to use the socket API. Signed-off-by: Jukka Rissanen --- subsys/mgmt/mcumgr/transport/Kconfig.udp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/mgmt/mcumgr/transport/Kconfig.udp b/subsys/mgmt/mcumgr/transport/Kconfig.udp index ad0e26277f9..5eb78e2288e 100644 --- a/subsys/mgmt/mcumgr/transport/Kconfig.udp +++ b/subsys/mgmt/mcumgr/transport/Kconfig.udp @@ -13,8 +13,8 @@ menuconfig MCUMGR_TRANSPORT_UDP bool "UDP mcumgr SMP transport" depends on NET_UDP depends on NET_SOCKETS - select NET_SOCKETS_POSIX_NAMES if !POSIX_API select NET_CONNECTION_MANAGER + select POSIX_API help Enables handling of SMP commands received over UDP. Will start a thread for listening on the configured UDP port. From 9dad97ae95d1adbe72d17b1cc1ebffb623081b01 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 08:03:01 +0200 Subject: [PATCH 1534/2402] doc: net: Remove the mention of NET_SOCKETS_POSIX_NAMES The option is deprecated so remove it from documentation. Signed-off-by: Jukka Rissanen --- doc/connectivity/networking/api/sockets.rst | 4 ++-- doc/services/portability/posix/kconfig/index.rst | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/doc/connectivity/networking/api/sockets.rst b/doc/connectivity/networking/api/sockets.rst index 5ea4429cf13..c212da86754 100644 --- a/doc/connectivity/networking/api/sockets.rst +++ b/doc/connectivity/networking/api/sockets.rst @@ -22,7 +22,7 @@ compatible API implementation for Zephyr: * Is namespaced by default, to avoid name conflicts with well-known names like ``close()``, which may be part of libc or other POSIX compatibility libraries. - If enabled by :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES`, it will also + If enabled by :kconfig:option:`CONFIG_POSIX_API`, it will also expose native POSIX names. BSD Sockets compatible API is enabled using :kconfig:option:`CONFIG_NET_SOCKETS` @@ -35,7 +35,7 @@ config option and implements the following operations: ``socket()``, ``close()`` Based on the namespacing requirements above, these operations are by default exposed as functions with ``zsock_`` prefix, e.g. :c:func:`zsock_socket` and :c:func:`zsock_close`. If the config option -:kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` is defined, all the functions +:kconfig:option:`CONFIG_POSIX_API` is defined, all the functions will be also exposed as aliases without the prefix. This includes the functions like ``close()`` and ``fcntl()`` (which may conflict with functions in libc or other libraries, for example, with the filesystem diff --git a/doc/services/portability/posix/kconfig/index.rst b/doc/services/portability/posix/kconfig/index.rst index 0ce0e5bb4b4..059c0c1affe 100644 --- a/doc/services/portability/posix/kconfig/index.rst +++ b/doc/services/portability/posix/kconfig/index.rst @@ -24,7 +24,6 @@ implementation of the POSIX API. * :kconfig:option:`CONFIG_NET_SOCKETPAIR` * :kconfig:option:`CONFIG_NET_SOCKETS` * :kconfig:option:`CONFIG_NET_SOCKETS_POLL_MAX` -* :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` * :kconfig:option:`CONFIG_POSIX_API` * :kconfig:option:`CONFIG_POSIX_CLOCK` * :kconfig:option:`CONFIG_POSIX_FS` From b4bf23220d54937b1eba2b4d40e1ab6ff967a2bf Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 15:00:31 +0200 Subject: [PATCH 1535/2402] doc: migration-guide-3.7: Add NET_SOCKETS_POSIX_NAMES info Add CONFIG_NET_SOCKETS_POSIX_NAMES deprecation information. Signed-off-by: Jukka Rissanen --- doc/releases/migration-guide-3.7.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index b5d3d74908f..0de2ccec2ce 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -178,6 +178,18 @@ Bluetooth Classic Networking ********** +* Deprecate the :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` option. It is a legacy option + and was used to allow user to call BSD socket API while not enabling POSIX API. + This could cause complications when building applications that wanted to enable the + :kconfig:option:`CONFIG_POSIX_API` option. This means that if the application wants to use + normal BSD socket interface, then it needs to enable :kconfig:option:`CONFIG_POSIX_API`. + If the application does not want or is not able to enable that option, then the socket API + calls need to be prefixed by a ``zsock_`` string. + All the sample applications that use BSD socket interface are changed to enable + :kconfig:option:`CONFIG_POSIX_API`. Internally the network stack will not enable POSIX API + option which means that various network libraries that use sockets, are converted to + use the ``zsock_*`` API calls. (:github:`69950`) + * The zperf zperf_results struct is changed to support 64 bits transferred bytes (total_len) and test duration (time_in_us and client_time_in_us), instead of 32 bits. This will make the long-duration zperf test show with correct throughput result. From e158c1729aa5ec3286c165267dfa26ebbc679d30 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 15:27:18 +0200 Subject: [PATCH 1536/2402] shell: mqtt: Avoid using POSIX function names This commit fixes this error seen in CI so that things work even if CONFIG_POSIX_API is enabled. subsys/shell/backends/shell_mqtt.c:727:12: error: conflicting types for 'write'; have 'int(const struct shell_transport *, const void *, size_t, size_t *)' 727 | static int write(const struct shell_transport *transport, const void *data, size_t length) include/zephyr/posix/unistd.h:230:9: note: previous declaration of 'write' with type 'ssize_t(int, const void *, size_t)' 230 | ssize_t write(int file, const void *buffer, size_t count); subsys/shell/backends/shell_mqtt.c:787:12: error: conflicting types for 'read'; have 'int(const struct shell_transport *, void *, size_t, size_t *)' 787 | static int read(const struct shell_transport *transport, void *data, size_t length, size_t *cnt) include/zephyr/posix/unistd.h:231:9: note: previous declaration of 'read' with type 'ssize_t(int, void *, size_t)' 231 | ssize_t read(int file, void *buffer, size_t count); Signed-off-by: Jukka Rissanen --- subsys/shell/backends/shell_mqtt.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/subsys/shell/backends/shell_mqtt.c b/subsys/shell/backends/shell_mqtt.c index bb25296f8e0..9b474436fd4 100644 --- a/subsys/shell/backends/shell_mqtt.c +++ b/subsys/shell/backends/shell_mqtt.c @@ -724,8 +724,8 @@ static int enable(const struct shell_transport *transport, bool blocking) return 0; } -static int write(const struct shell_transport *transport, const void *data, size_t length, - size_t *cnt) +static int write_data(const struct shell_transport *transport, const void *data, size_t length, + size_t *cnt) { ARG_UNUSED(transport); int rc = 0; @@ -784,7 +784,8 @@ static int write(const struct shell_transport *transport, const void *data, size return rc; } -static int read(const struct shell_transport *transport, void *data, size_t length, size_t *cnt) +static int read_data(const struct shell_transport *transport, void *data, size_t length, + size_t *cnt) { ARG_UNUSED(transport); @@ -812,8 +813,8 @@ static int read(const struct shell_transport *transport, void *data, size_t leng const struct shell_transport_api shell_mqtt_transport_api = { .init = init, .uninit = uninit, .enable = enable, - .write = write, - .read = read }; + .write = write_data, + .read = read_data }; static int enable_shell_mqtt(void) { From c4216dd65c193fc40f6f3477fb0a4c504f87ba15 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 16:41:38 +0200 Subject: [PATCH 1537/2402] samples: net: echo-server: Adjust CONFIG_MAX_THREAD_BYTES This fixes this error printed by CI: Too many thread objects (21) Increase CONFIG_MAX_THREAD_BYTES to 3 Signed-off-by: Jukka Rissanen --- samples/net/sockets/echo_server/sample.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/samples/net/sockets/echo_server/sample.yaml b/samples/net/sockets/echo_server/sample.yaml index 93bdb943623..b3b99011922 100644 --- a/samples/net/sockets/echo_server/sample.yaml +++ b/samples/net/sockets/echo_server/sample.yaml @@ -128,6 +128,7 @@ tests: extra_args: - CONFIG_USERSPACE=y - OVERLAY_CONFIG="overlay-e1000.conf" + - CONFIG_MAX_THREAD_BYTES=3 platform_allow: - qemu_x86 - qemu_x86_64 From 66bc15d89d5449a0dedd44892d636d3130f3c425 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 8 Mar 2024 16:47:08 +0200 Subject: [PATCH 1538/2402] tests: net: lwm2m: Fix zsock_fcntl impl name The syscall name has _impl postfix so adjusting the stub name. zephyr-sdk-0.16.5-1/x86_64-zephyr-elf/bin/../lib/gcc/ x86_64-zephyr-elf/12.2.0/../../../../x86_64-zephyr-elf/bin/ld.bfd: app/libapp.a(lwm2m_engine.c.obj): in function `zsock_fcntl_impl': .../syscalls/socket.h:363: undefined reference to `z_impl_zsock_fcntl_impl' Signed-off-by: Jukka Rissanen --- tests/net/lib/lwm2m/lwm2m_engine/src/stubs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.c b/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.c index 0958d75a54a..55573eda168 100644 --- a/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.c +++ b/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.c @@ -129,7 +129,7 @@ int z_impl_zsock_poll(struct zsock_pollfd *fds, int nfds, int poll_timeout) return 0; } -int z_impl_zsock_fcntl(int sock, int cmd, int flags) +int z_impl_zsock_fcntl_impl(int sock, int cmd, int flags) { return 0; } From c0fcd8c9b5bbf2efab73f5e8bdec97cad3e3747b Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 10 Mar 2024 10:40:10 +0200 Subject: [PATCH 1539/2402] samples: net: sockets: can: Fix the test termination criteria If enabling CONFIG_POSIX_API, we get three file descriptors open before any socket descriptors. The sample exit criteria checks socket 0 and 1 which is no longer a valid one, so change the check to be either 0 or 3, and 1 or 4 so that the test can be run in both when POSIX API is enabled or disabled. Also disable color printing for the test run so that it is easier to read the output log. Signed-off-by: Jukka Rissanen --- samples/net/sockets/can/sample.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/samples/net/sockets/can/sample.yaml b/samples/net/sockets/can/sample.yaml index 982b15b6a74..4e1d9d1c9fa 100644 --- a/samples/net/sockets/can/sample.yaml +++ b/samples/net/sockets/can/sample.yaml @@ -12,20 +12,22 @@ tests: sample.net.sockets.can.one_socket: extra_configs: - CONFIG_NET_SOCKETS_CAN_RECEIVERS=1 + - CONFIG_LOG_BACKEND_SHOW_COLOR=n harness_config: type: multi_line ordered: true regex: - - "(.*)\\[0\\] CAN frame: IDE 0x0 RTR 0x0 ID 0x1 DLC 0x8" + - "(.*)\\[0|3\\] CAN frame: IDE 0x0 RTR 0x0 ID 0x1 DLC 0x8" - "(.*)f0 f1 f2 f3 f4 f5 f6 f7" sample.net.sockets.can.two_sockets: extra_configs: - CONFIG_NET_SOCKETS_CAN_RECEIVERS=2 + - CONFIG_LOG_BACKEND_SHOW_COLOR=n harness_config: type: multi_line ordered: true regex: - - "(.*)\\[0\\] CAN frame: IDE 0x0 RTR 0x0 ID 0x1 DLC 0x8" + - "(.*)\\[0|3\\] CAN frame: IDE 0x0 RTR 0x0 ID 0x1 DLC 0x8" - "(.*)f0 f1 f2 f3 f4 f5 f6 f7" - - "(.*)\\[1\\] CAN frame: IDE 0x0 RTR 0x0 ID 0x1 DLC 0x8" + - "(.*)\\[1|4\\] CAN frame: IDE 0x0 RTR 0x0 ID 0x1 DLC 0x8" - "(.*)f0 f1 f2 f3 f4 f5 f6 f7" From 873af2ee98852f495ab418038938c784cef0438f Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 10 Mar 2024 12:44:39 +0200 Subject: [PATCH 1540/2402] net: sockets: Use only Zephyr POSIX headers Use only Zephyr specific POSIX header files so that the whole system is getting values from the same files. There was an issue with native_sim run of tests/net/socket/af_packet which had O_BLOCKING set to 0x4000 from include/zephyr/posix/fcntl.h, but then the file subsys/net/lib/socket/sockets.c was having O_BLOCKING set to 0x0800 because different header files were used. Signed-off-by: Jukka Rissanen --- subsys/net/lib/sockets/sockets.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/subsys/net/lib/sockets/sockets.c b/subsys/net/lib/sockets/sockets.c index 8bd0f63c903..e153cd173bb 100644 --- a/subsys/net/lib/sockets/sockets.c +++ b/subsys/net/lib/sockets/sockets.c @@ -15,11 +15,7 @@ LOG_MODULE_REGISTER(net_sock, CONFIG_NET_SOCKETS_LOG_LEVEL); #include #include #include -#ifdef CONFIG_ARCH_POSIX -#include -#else #include -#endif #include #include #include From d7c9d67a9c3c9f641f58e894a8df4587df0cc8ef Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 10 Mar 2024 12:56:50 +0200 Subject: [PATCH 1541/2402] net: Use always zephyr/posix/fcntl.h Changing remaining users of fcntl.h to use the include from our own POSIX file so that the values in there are consistent in all parts of the sources. Signed-off-by: Jukka Rissanen --- samples/net/sockets/echo_async/src/socket_echo.c | 4 ++-- .../net/sockets/echo_async_select/src/socket_echo_select.c | 4 ++-- subsys/net/lib/coap/coap_server.c | 4 ---- subsys/net/lib/lwm2m/lwm2m_engine.c | 4 ---- subsys/net/lib/mqtt_sn/mqtt_sn_transport_udp.c | 4 ---- subsys/net/lib/sockets/sockets_can.c | 4 ---- subsys/net/lib/sockets/sockets_net_mgmt.c | 4 ---- subsys/net/lib/sockets/sockets_packet.c | 4 ---- subsys/net/lib/sockets/sockets_tls.c | 4 ---- tests/net/ipv4_fragment/src/main.c | 2 +- tests/net/socket/af_packet_ipproto_raw/src/main.c | 2 +- tests/net/socket/offload_dispatcher/src/main.c | 2 +- tests/net/socket/tcp/src/main.c | 2 +- tests/net/socket/tls/src/main.c | 2 +- 14 files changed, 9 insertions(+), 37 deletions(-) diff --git a/samples/net/sockets/echo_async/src/socket_echo.c b/samples/net/sockets/echo_async/src/socket_echo.c index 633a1febaa5..33dadfbf9e7 100644 --- a/samples/net/sockets/echo_async/src/socket_echo.c +++ b/samples/net/sockets/echo_async/src/socket_echo.c @@ -9,7 +9,7 @@ #include #include -#if !defined(__ZEPHYR__) || defined(CONFIG_POSIX_API) +#if !defined(__ZEPHYR__) #include #include @@ -22,7 +22,7 @@ #else -#include +#include #include #include diff --git a/samples/net/sockets/echo_async_select/src/socket_echo_select.c b/samples/net/sockets/echo_async_select/src/socket_echo_select.c index b26bef9e404..9ae3511579b 100644 --- a/samples/net/sockets/echo_async_select/src/socket_echo_select.c +++ b/samples/net/sockets/echo_async_select/src/socket_echo_select.c @@ -9,7 +9,7 @@ #include #include -#if !defined(__ZEPHYR__) || defined(CONFIG_POSIX_API) +#if !defined(__ZEPHYR__) #include #include @@ -24,7 +24,7 @@ #else -#include +#include #include #include #include diff --git a/subsys/net/lib/coap/coap_server.c b/subsys/net/lib/coap/coap_server.c index 6453043dbd9..f7cc92e2994 100644 --- a/subsys/net/lib/coap/coap_server.c +++ b/subsys/net/lib/coap/coap_server.c @@ -16,11 +16,7 @@ LOG_MODULE_DECLARE(net_coap, CONFIG_COAP_LOG_LEVEL); #include #include #include -#ifdef CONFIG_ARCH_POSIX -#include -#else #include -#endif #if defined(CONFIG_NET_TC_THREAD_COOPERATIVE) /* Lowest priority cooperative thread */ diff --git a/subsys/net/lib/lwm2m/lwm2m_engine.c b/subsys/net/lib/lwm2m/lwm2m_engine.c index 061a3d42346..df9689dc094 100644 --- a/subsys/net/lib/lwm2m/lwm2m_engine.c +++ b/subsys/net/lib/lwm2m/lwm2m_engine.c @@ -32,11 +32,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME); #include #include #include -#ifdef CONFIG_ARCH_POSIX -#include -#else #include -#endif #if defined(CONFIG_LWM2M_DTLS_SUPPORT) #include diff --git a/subsys/net/lib/mqtt_sn/mqtt_sn_transport_udp.c b/subsys/net/lib/mqtt_sn/mqtt_sn_transport_udp.c index c94f90b69c2..2104e8b0ac9 100644 --- a/subsys/net/lib/mqtt_sn/mqtt_sn_transport_udp.c +++ b/subsys/net/lib/mqtt_sn/mqtt_sn_transport_udp.c @@ -15,11 +15,7 @@ #include #include -#ifdef CONFIG_ARCH_POSIX -#include -#else #include -#endif #include LOG_MODULE_DECLARE(net_mqtt_sn, CONFIG_MQTT_SN_LOG_LEVEL); diff --git a/subsys/net/lib/sockets/sockets_can.c b/subsys/net/lib/sockets/sockets_can.c index d4856a7a4be..69dae977ad6 100644 --- a/subsys/net/lib/sockets/sockets_can.c +++ b/subsys/net/lib/sockets/sockets_can.c @@ -6,11 +6,7 @@ */ #include -#ifdef CONFIG_ARCH_POSIX -#include -#else #include -#endif #include LOG_MODULE_REGISTER(net_sock_can, CONFIG_NET_SOCKETS_LOG_LEVEL); diff --git a/subsys/net/lib/sockets/sockets_net_mgmt.c b/subsys/net/lib/sockets/sockets_net_mgmt.c index c0fec104de0..0404cc6f4ac 100644 --- a/subsys/net/lib/sockets/sockets_net_mgmt.c +++ b/subsys/net/lib/sockets/sockets_net_mgmt.c @@ -5,11 +5,7 @@ */ #include -#ifdef CONFIG_ARCH_POSIX -#include -#else #include -#endif #include LOG_MODULE_REGISTER(net_sock_mgmt, CONFIG_NET_SOCKETS_LOG_LEVEL); diff --git a/subsys/net/lib/sockets/sockets_packet.c b/subsys/net/lib/sockets/sockets_packet.c index ce4f83190c4..ec8e77c43ad 100644 --- a/subsys/net/lib/sockets/sockets_packet.c +++ b/subsys/net/lib/sockets/sockets_packet.c @@ -6,11 +6,7 @@ */ #include -#ifdef CONFIG_ARCH_POSIX -#include -#else #include -#endif #include LOG_MODULE_REGISTER(net_sock_packet, CONFIG_NET_SOCKETS_LOG_LEVEL); diff --git a/subsys/net/lib/sockets/sockets_tls.c b/subsys/net/lib/sockets/sockets_tls.c index ae64464f46c..4d7fadce47b 100644 --- a/subsys/net/lib/sockets/sockets_tls.c +++ b/subsys/net/lib/sockets/sockets_tls.c @@ -6,11 +6,7 @@ */ #include -#ifdef CONFIG_ARCH_POSIX -#include -#else #include -#endif #include LOG_MODULE_REGISTER(net_sock_tls, CONFIG_NET_SOCKETS_LOG_LEVEL); diff --git a/tests/net/ipv4_fragment/src/main.c b/tests/net/ipv4_fragment/src/main.c index 7375aab17aa..2846e324a4d 100644 --- a/tests/net/ipv4_fragment/src/main.c +++ b/tests/net/ipv4_fragment/src/main.c @@ -20,7 +20,7 @@ LOG_MODULE_REGISTER(net_ipv4_test, CONFIG_NET_IPV4_LOG_LEVEL); #include #include #include -#include +#include #include #include #include diff --git a/tests/net/socket/af_packet_ipproto_raw/src/main.c b/tests/net/socket/af_packet_ipproto_raw/src/main.c index 907b28df7e5..15d2a047d41 100644 --- a/tests/net/socket/af_packet_ipproto_raw/src/main.c +++ b/tests/net/socket/af_packet_ipproto_raw/src/main.c @@ -12,7 +12,7 @@ LOG_MODULE_REGISTER(net_test, CONFIG_NET_SOCKETS_LOG_LEVEL); #include #include -#include +#include #include #include diff --git a/tests/net/socket/offload_dispatcher/src/main.c b/tests/net/socket/offload_dispatcher/src/main.c index 9a7a5b5de37..258b186b0dc 100644 --- a/tests/net/socket/offload_dispatcher/src/main.c +++ b/tests/net/socket/offload_dispatcher/src/main.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include diff --git a/tests/net/socket/tcp/src/main.c b/tests/net/socket/tcp/src/main.c index 1186a3a0a8d..a4295b74f1d 100644 --- a/tests/net/socket/tcp/src/main.c +++ b/tests/net/socket/tcp/src/main.c @@ -8,7 +8,7 @@ LOG_MODULE_REGISTER(net_test, CONFIG_NET_SOCKETS_LOG_LEVEL); #include -#include +#include #include #include diff --git a/tests/net/socket/tls/src/main.c b/tests/net/socket/tls/src/main.c index 03520c575ce..59bad541f1c 100644 --- a/tests/net/socket/tls/src/main.c +++ b/tests/net/socket/tls/src/main.c @@ -8,7 +8,7 @@ LOG_MODULE_REGISTER(net_test, CONFIG_NET_SOCKETS_LOG_LEVEL); #include -#include +#include #include #include #include From a613e2427a30e07da1683369726b9292f7ccd9d6 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 27 Mar 2024 11:10:48 +0200 Subject: [PATCH 1542/2402] samples: net: Disable native_sim net USB driver in samples The native_sim USB driver gives this error currently if one enables CONFIG_POSIX_API. drivers/usb/device/usb_dc_native_posix_adapt.c:22:10: \ fatal error: sys/un.h: No such file or directory 22 | #include | ^~~~~~~~~~ compilation terminated. Disable the netusb support from networking shells for native_sim board for now so that CI can pass. Signed-off-by: Jukka Rissanen --- samples/net/sockets/dumb_http_server/sample.yaml | 8 ++++++++ samples/net/sockets/echo_server/sample.yaml | 4 ++++ samples/net/zperf/sample.yaml | 12 ++++++++++++ 3 files changed, 24 insertions(+) diff --git a/samples/net/sockets/dumb_http_server/sample.yaml b/samples/net/sockets/dumb_http_server/sample.yaml index 55a8d9a9673..1751f811693 100644 --- a/samples/net/sockets/dumb_http_server/sample.yaml +++ b/samples/net/sockets/dumb_http_server/sample.yaml @@ -19,8 +19,16 @@ tests: harness: net extra_args: OVERLAY_CONFIG="overlay-netusb.conf" tags: usb + # native_sim usb driver does not work with CONFIG_POSIX_API + platform_exclude: + - native_sim + - native_sim/native/64 sample.net.sockets.dumb_http_server.netusb_zeroconf: depends_on: usb_device harness: net extra_args: OVERLAY_CONFIG="overlay-netusb.conf;overlay-zeroconf.conf" tags: usb + # native_sim usb driver does not work with CONFIG_POSIX_API + platform_exclude: + - native_sim + - native_sim/native/64 diff --git a/samples/net/sockets/echo_server/sample.yaml b/samples/net/sockets/echo_server/sample.yaml index b3b99011922..a127175471f 100644 --- a/samples/net/sockets/echo_server/sample.yaml +++ b/samples/net/sockets/echo_server/sample.yaml @@ -86,6 +86,10 @@ tests: tags: - net - usb + # native_sim usb driver does not work with CONFIG_POSIX_API + platform_exclude: + - native_sim + - native_sim/native/64 sample.net.sockets.echo_server.nrf_openthread: extra_args: OVERLAY_CONFIG="overlay-ot.conf" slow: true diff --git a/samples/net/zperf/sample.yaml b/samples/net/zperf/sample.yaml index ece4f52cafb..5fb33f67348 100644 --- a/samples/net/zperf/sample.yaml +++ b/samples/net/zperf/sample.yaml @@ -40,6 +40,10 @@ tests: - net - zperf depends_on: usb_device + # native_sim usb driver does not work with CONFIG_POSIX_API + platform_exclude: + - native_sim + - native_sim/native/64 sample.net.zperf.device_next_ecm: harness: net extra_args: OVERLAY_CONFIG="overlay-usbd_next_ecm.conf" @@ -58,6 +62,10 @@ tests: - net - zperf depends_on: usb_device + # native_sim usb driver does not work with CONFIG_POSIX_API + platform_exclude: + - native_sim + - native_sim/native/64 sample.net.zperf.netusb_rndis: harness: net extra_args: OVERLAY_CONFIG="overlay-netusb.conf" @@ -69,6 +77,10 @@ tests: - net - zperf depends_on: usb_device + # native_sim usb driver does not work with CONFIG_POSIX_API + platform_exclude: + - native_sim + - native_sim/native/64 sample.net.zperf.shield: harness: net platform_allow: reel_board From 42356b6d5cbafc76e61519a6e4692cc6db512078 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 27 Mar 2024 16:06:36 +0200 Subject: [PATCH 1543/2402] net: wifi: shell: Avoid declaring variables after case statement Some compilers have trouble parsing variables directly after a case statement. Fixes: #70792 Signed-off-by: Jukka Rissanen --- subsys/net/l2/wifi/wifi_shell.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index ba1fcce502b..759eebc19f6 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -469,6 +469,7 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv bool found = false; char bands_str[MAX_BANDS_STR_LEN] = {0}; size_t offset = 0; + long channel; /* Defaults */ params->band = WIFI_FREQ_BAND_UNKNOWN; @@ -503,7 +504,7 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv } break; case 'c': - long channel = strtol(optarg, &endptr, 10); + channel = strtol(optarg, &endptr, 10); for (band = 0; band < ARRAY_SIZE(all_bands); band++) { offset += snprintf(bands_str + offset, sizeof(bands_str) - offset, From f05111dea048814ef312eb664aaa87e9eda3844c Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 22 Mar 2024 12:45:31 -0700 Subject: [PATCH 1544/2402] kernel: rename Z_KERNEL_STACK_LEN to K_KERNEL_STACK_LEN Since there is a K_THREAD_STACK_LEN, its kernel counterpart should also be prefixed with K_ for consistency. Signed-off-by: Daniel Leung --- include/zephyr/arch/arc/arch.h | 2 +- include/zephyr/kernel/thread_stack.h | 10 +++++----- scripts/build/gen_kobject_list.py | 2 +- tests/kernel/threads/thread_stack/src/main.c | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/zephyr/arch/arc/arch.h b/include/zephyr/arch/arc/arch.h index 1144faa6ebc..b3751c6041c 100644 --- a/include/zephyr/arch/arc/arch.h +++ b/include/zephyr/arch/arc/arch.h @@ -188,7 +188,7 @@ BUILD_ASSERT(CONFIG_PRIVILEGED_STACK_SIZE % Z_ARC_MPU_ALIGN == 0, * in another area of memory generated at build time by gen_kobject_list.py * * +------------+ <- thread.arch.priv_stack_start - * | Priv Stack | } Z_KERNEL_STACK_LEN(CONFIG_PRIVILEGED_STACK_SIZE) + * | Priv Stack | } K_KERNEL_STACK_LEN(CONFIG_PRIVILEGED_STACK_SIZE) * +------------+ * * +------------+ <- thread.stack_obj = thread.stack_info.start diff --git a/include/zephyr/kernel/thread_stack.h b/include/zephyr/kernel/thread_stack.h index 1cfab4b1c15..67aa35abad5 100644 --- a/include/zephyr/kernel/thread_stack.h +++ b/include/zephyr/kernel/thread_stack.h @@ -104,7 +104,7 @@ static inline char *z_stack_ptr_align(char *ptr) #define Z_KERNEL_STACK_OBJ_ALIGN ARCH_STACK_PTR_ALIGN #endif /* ARCH_KERNEL_STACK_OBJ_ALIGN */ -#define Z_KERNEL_STACK_LEN(size) \ +#define K_KERNEL_STACK_LEN(size) \ ROUND_UP(Z_KERNEL_STACK_SIZE_ADJUST(size), Z_KERNEL_STACK_OBJ_ALIGN) /** @@ -137,7 +137,7 @@ static inline char *z_stack_ptr_align(char *ptr) */ #define K_KERNEL_STACK_ARRAY_DECLARE(sym, nmemb, size) \ extern struct z_thread_stack_element \ - sym[nmemb][Z_KERNEL_STACK_LEN(size)] + sym[nmemb][K_KERNEL_STACK_LEN(size)] /** * @brief Declare a reference to a pinned thread stack array @@ -151,7 +151,7 @@ static inline char *z_stack_ptr_align(char *ptr) */ #define K_KERNEL_PINNED_STACK_ARRAY_DECLARE(sym, nmemb, size) \ extern struct z_thread_stack_element \ - sym[nmemb][Z_KERNEL_STACK_LEN(size)] + sym[nmemb][K_KERNEL_STACK_LEN(size)] /** * @brief Define a toplevel kernel stack memory region in specified section @@ -188,7 +188,7 @@ static inline char *z_stack_ptr_align(char *ptr) #define Z_KERNEL_STACK_ARRAY_DEFINE_IN(sym, nmemb, size, lsect) \ struct z_thread_stack_element lsect \ __aligned(Z_KERNEL_STACK_OBJ_ALIGN) \ - sym[nmemb][Z_KERNEL_STACK_LEN(size)] + sym[nmemb][K_KERNEL_STACK_LEN(size)] /** * @brief Define a toplevel kernel stack memory region @@ -290,7 +290,7 @@ static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) #ifndef CONFIG_USERSPACE #define K_THREAD_STACK_RESERVED K_KERNEL_STACK_RESERVED #define K_THREAD_STACK_SIZEOF K_KERNEL_STACK_SIZEOF -#define K_THREAD_STACK_LEN Z_KERNEL_STACK_LEN +#define K_THREAD_STACK_LEN K_KERNEL_STACK_LEN #define K_THREAD_STACK_DEFINE K_KERNEL_STACK_DEFINE #define K_THREAD_STACK_ARRAY_DEFINE K_KERNEL_STACK_ARRAY_DEFINE #define K_THREAD_STACK_MEMBER K_KERNEL_STACK_MEMBER diff --git a/scripts/build/gen_kobject_list.py b/scripts/build/gen_kobject_list.py index 6e41adb797d..6e07fd00957 100755 --- a/scripts/build/gen_kobject_list.py +++ b/scripts/build/gen_kobject_list.py @@ -794,7 +794,7 @@ def write_gperf_table(fp, syms, objs, little_endian, static_begin, static_end): # memory section. fp.write("static uint8_t Z_GENERIC_SECTION(.priv_stacks.noinit) " " __aligned(Z_KERNEL_STACK_OBJ_ALIGN)" - " priv_stacks[%d][Z_KERNEL_STACK_LEN(CONFIG_PRIVILEGED_STACK_SIZE)];\n" + " priv_stacks[%d][K_KERNEL_STACK_LEN(CONFIG_PRIVILEGED_STACK_SIZE)];\n" % stack_counter) fp.write("static const struct z_stack_data stack_data[%d] = {\n" diff --git a/tests/kernel/threads/thread_stack/src/main.c b/tests/kernel/threads/thread_stack/src/main.c index a2ea5e95753..73730d54d09 100644 --- a/tests/kernel/threads/thread_stack/src/main.c +++ b/tests/kernel/threads/thread_stack/src/main.c @@ -271,7 +271,7 @@ void stack_buffer_scenarios(void) if (scenario_data.is_user) { adjusted = K_THREAD_STACK_LEN(scenario_data.declared_size); } else { - adjusted = Z_KERNEL_STACK_LEN(scenario_data.declared_size); + adjusted = K_KERNEL_STACK_LEN(scenario_data.declared_size); } adjusted -= reserved; From b69d2486fee67e932c59ccb81ebd191972e77d0b Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 22 Mar 2024 12:56:12 -0700 Subject: [PATCH 1545/2402] kernel: rename Z_KERNEL_STACK_BUFFER to K_KERNEL_STACK_BUFFER Simple rename to align the kernel naming scheme. This is being used throughout the tree, especially in the architecture code. As this is not a private API internal to kernel, prefix it appropriately with K_. Signed-off-by: Daniel Leung --- arch/arc/core/irq_manage.c | 4 ++-- arch/arc/core/smp.c | 2 +- arch/arc/core/thread.c | 2 +- arch/arm/core/cortex_a_r/smp.c | 12 ++++++------ arch/arm/core/cortex_a_r/stacks.c | 2 +- arch/arm/include/cortex_m/stack.h | 2 +- arch/arm64/core/fatal.c | 2 +- arch/arm64/core/smp.c | 2 +- arch/riscv/core/smp.c | 2 +- arch/riscv/core/thread.c | 2 +- arch/x86/core/fatal.c | 2 +- arch/x86/core/ia32/fatal.c | 2 +- arch/x86/core/intel64/cpu.c | 2 +- arch/xtensa/include/kernel_arch_func.h | 2 +- include/zephyr/kernel/thread_stack.h | 4 ++-- kernel/init.c | 2 +- kernel/thread.c | 2 +- soc/espressif/esp32/esp32-mp.c | 4 ++-- soc/intel/intel_adsp/common/multiprocessing.c | 2 +- subsys/debug/thread_analyzer.c | 2 +- subsys/shell/modules/kernel_service.c | 2 +- tests/kernel/threads/thread_stack/src/main.c | 2 +- 22 files changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arc/core/irq_manage.c b/arch/arc/core/irq_manage.c index 73c8007f708..f6573f5e1bd 100644 --- a/arch/arc/core/irq_manage.c +++ b/arch/arc/core/irq_manage.c @@ -44,11 +44,11 @@ K_KERNEL_STACK_DEFINE(_firq_interrupt_stack, CONFIG_ARC_FIRQ_STACK_SIZE); void z_arc_firq_stack_set(void) { #ifdef CONFIG_SMP - char *firq_sp = Z_KERNEL_STACK_BUFFER( + char *firq_sp = K_KERNEL_STACK_BUFFER( _firq_interrupt_stack[z_arc_v2_core_id()]) + CONFIG_ARC_FIRQ_STACK_SIZE; #else - char *firq_sp = Z_KERNEL_STACK_BUFFER(_firq_interrupt_stack) + + char *firq_sp = K_KERNEL_STACK_BUFFER(_firq_interrupt_stack) + CONFIG_ARC_FIRQ_STACK_SIZE; #endif diff --git a/arch/arc/core/smp.c b/arch/arc/core/smp.c index 767c463180d..9f8ee38a4a1 100644 --- a/arch/arc/core/smp.c +++ b/arch/arc/core/smp.c @@ -50,7 +50,7 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, * arc_cpu_wake_flag will protect arc_cpu_sp that * only one slave cpu can read it per time */ - arc_cpu_sp = Z_KERNEL_STACK_BUFFER(stack) + sz; + arc_cpu_sp = K_KERNEL_STACK_BUFFER(stack) + sz; arc_cpu_wake_flag = cpu_num; diff --git a/arch/arc/core/thread.c b/arch/arc/core/thread.c index 56340120143..fd3f86c07e7 100644 --- a/arch/arc/core/thread.c +++ b/arch/arc/core/thread.c @@ -283,7 +283,7 @@ FUNC_NORETURN void z_arc_switch_to_main_no_multithreading(k_thread_entry_t main_ void *p1, void *p2, void *p3) { _kernel.cpus[0].id = 0; - _kernel.cpus[0].irq_stack = (Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]) + + _kernel.cpus[0].irq_stack = (K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]) + K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0])); void *main_stack = (Z_THREAD_STACK_BUFFER(z_main_stack) + diff --git a/arch/arm/core/cortex_a_r/smp.c b/arch/arm/core/cortex_a_r/smp.c index 85a8650d02f..9e06730f913 100644 --- a/arch/arm/core/cortex_a_r/smp.c +++ b/arch/arm/core/cortex_a_r/smp.c @@ -120,16 +120,16 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_ } /* Pass stack address to secondary core */ - arm_cpu_boot_params.irq_sp = Z_KERNEL_STACK_BUFFER(stack) + sz; - arm_cpu_boot_params.fiq_sp = Z_KERNEL_STACK_BUFFER(z_arm_fiq_stack[cpu_num]) + arm_cpu_boot_params.irq_sp = K_KERNEL_STACK_BUFFER(stack) + sz; + arm_cpu_boot_params.fiq_sp = K_KERNEL_STACK_BUFFER(z_arm_fiq_stack[cpu_num]) + CONFIG_ARMV7_FIQ_STACK_SIZE; - arm_cpu_boot_params.abt_sp = Z_KERNEL_STACK_BUFFER(z_arm_abort_stack[cpu_num]) + arm_cpu_boot_params.abt_sp = K_KERNEL_STACK_BUFFER(z_arm_abort_stack[cpu_num]) + CONFIG_ARMV7_EXCEPTION_STACK_SIZE; - arm_cpu_boot_params.udf_sp = Z_KERNEL_STACK_BUFFER(z_arm_undef_stack[cpu_num]) + arm_cpu_boot_params.udf_sp = K_KERNEL_STACK_BUFFER(z_arm_undef_stack[cpu_num]) + CONFIG_ARMV7_EXCEPTION_STACK_SIZE; - arm_cpu_boot_params.svc_sp = Z_KERNEL_STACK_BUFFER(z_arm_svc_stack[cpu_num]) + arm_cpu_boot_params.svc_sp = K_KERNEL_STACK_BUFFER(z_arm_svc_stack[cpu_num]) + CONFIG_ARMV7_SVC_STACK_SIZE; - arm_cpu_boot_params.sys_sp = Z_KERNEL_STACK_BUFFER(z_arm_sys_stack[cpu_num]) + arm_cpu_boot_params.sys_sp = K_KERNEL_STACK_BUFFER(z_arm_sys_stack[cpu_num]) + CONFIG_ARMV7_SYS_STACK_SIZE; arm_cpu_boot_params.fn = fn; diff --git a/arch/arm/core/cortex_a_r/stacks.c b/arch/arm/core/cortex_a_r/stacks.c index 0691595c359..fecc190b1ad 100644 --- a/arch/arm/core/cortex_a_r/stacks.c +++ b/arch/arm/core/cortex_a_r/stacks.c @@ -28,7 +28,7 @@ void z_arm_init_stacks(void) memset(z_arm_svc_stack, 0xAA, CONFIG_ARMV7_SVC_STACK_SIZE); memset(z_arm_abort_stack, 0xAA, CONFIG_ARMV7_EXCEPTION_STACK_SIZE); memset(z_arm_undef_stack, 0xAA, CONFIG_ARMV7_EXCEPTION_STACK_SIZE); - memset(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]), 0xAA, + memset(K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]), 0xAA, K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0])); } #endif diff --git a/arch/arm/include/cortex_m/stack.h b/arch/arm/include/cortex_m/stack.h index f5c4de5902a..feeaf719a88 100644 --- a/arch/arm/include/cortex_m/stack.h +++ b/arch/arm/include/cortex_m/stack.h @@ -40,7 +40,7 @@ K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void) { uint32_t msp = - (uint32_t)(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) + + (uint32_t)(K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) + K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]); __set_MSP(msp); diff --git a/arch/arm64/core/fatal.c b/arch/arm64/core/fatal.c index dbf0c4cdae1..5d475e4c655 100644 --- a/arch/arm64/core/fatal.c +++ b/arch/arm64/core/fatal.c @@ -33,7 +33,7 @@ void z_arm64_safe_exception_stack_init(void) char *safe_exc_sp; cpu_id = arch_curr_cpu()->id; - safe_exc_sp = Z_KERNEL_STACK_BUFFER(z_arm64_safe_exception_stacks[cpu_id]) + + safe_exc_sp = K_KERNEL_STACK_BUFFER(z_arm64_safe_exception_stacks[cpu_id]) + CONFIG_ARM64_SAFE_EXCEPTION_STACK_SIZE; arch_curr_cpu()->arch.safe_exception_stack = (uint64_t)safe_exc_sp; write_sp_el0((uint64_t)safe_exc_sp); diff --git a/arch/arm64/core/smp.c b/arch/arm64/core/smp.c index 3413a578025..8777c400766 100644 --- a/arch/arm64/core/smp.c +++ b/arch/arm64/core/smp.c @@ -84,7 +84,7 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, "The count of CPU Cores nodes in dts is not equal to CONFIG_MP_MAX_NUM_CPUS\n"); #endif - arm64_cpu_boot_params.sp = Z_KERNEL_STACK_BUFFER(stack) + sz; + arm64_cpu_boot_params.sp = K_KERNEL_STACK_BUFFER(stack) + sz; arm64_cpu_boot_params.fn = fn; arm64_cpu_boot_params.arg = arg; arm64_cpu_boot_params.cpu_num = cpu_num; diff --git a/arch/riscv/core/smp.c b/arch/riscv/core/smp.c index fe9f349f6bc..68147f8880a 100644 --- a/arch/riscv/core/smp.c +++ b/arch/riscv/core/smp.c @@ -33,7 +33,7 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, riscv_cpu_init[cpu_num].fn = fn; riscv_cpu_init[cpu_num].arg = arg; - riscv_cpu_sp = Z_KERNEL_STACK_BUFFER(stack) + sz; + riscv_cpu_sp = K_KERNEL_STACK_BUFFER(stack) + sz; riscv_cpu_boot_flag = 0U; #ifdef CONFIG_PM_CPU_OPS diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c index 124f2042860..20ef9f419b1 100644 --- a/arch/riscv/core/thread.c +++ b/arch/riscv/core/thread.c @@ -206,7 +206,7 @@ FUNC_NORETURN void z_riscv_switch_to_main_no_multithreading(k_thread_entry_t mai ARG_UNUSED(p3); _kernel.cpus[0].id = 0; - _kernel.cpus[0].irq_stack = (Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]) + + _kernel.cpus[0].irq_stack = (K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]) + K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0])); main_stack = (Z_THREAD_STACK_BUFFER(z_main_stack) + diff --git a/arch/x86/core/fatal.c b/arch/x86/core/fatal.c index 1203f390dde..517d2efa290 100644 --- a/arch/x86/core/fatal.c +++ b/arch/x86/core/fatal.c @@ -59,7 +59,7 @@ bool z_x86_check_stack_bounds(uintptr_t addr, size_t size, uint16_t cs) #else cpu_id = 0; #endif - start = (uintptr_t)Z_KERNEL_STACK_BUFFER( + start = (uintptr_t)K_KERNEL_STACK_BUFFER( z_interrupt_stacks[cpu_id]); end = start + CONFIG_ISR_STACK_SIZE; #ifdef CONFIG_USERSPACE diff --git a/arch/x86/core/ia32/fatal.c b/arch/x86/core/ia32/fatal.c index 38cf180e0bc..597f21a01ad 100644 --- a/arch/x86/core/ia32/fatal.c +++ b/arch/x86/core/ia32/fatal.c @@ -206,7 +206,7 @@ static FUNC_NORETURN __used void df_handler_top(void) _df_esf.eflags = _main_tss.eflags; /* Restore the main IA task to a runnable state */ - _main_tss.esp = (uint32_t)(Z_KERNEL_STACK_BUFFER( + _main_tss.esp = (uint32_t)(K_KERNEL_STACK_BUFFER( z_interrupt_stacks[0]) + CONFIG_ISR_STACK_SIZE); _main_tss.cs = CODE_SEG; _main_tss.ds = DATA_SEG; diff --git a/arch/x86/core/intel64/cpu.c b/arch/x86/core/intel64/cpu.c index f5b3af53fad..3c17e2de593 100644 --- a/arch/x86/core/intel64/cpu.c +++ b/arch/x86/core/intel64/cpu.c @@ -156,7 +156,7 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, apic_id = x86_cpu_loapics[cpu_num]; - x86_cpuboot[cpu_num].sp = (uint64_t) Z_KERNEL_STACK_BUFFER(stack) + sz; + x86_cpuboot[cpu_num].sp = (uint64_t) K_KERNEL_STACK_BUFFER(stack) + sz; x86_cpuboot[cpu_num].stack_size = sz; x86_cpuboot[cpu_num].fn = fn; x86_cpuboot[cpu_num].arg = arg; diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h index 8dfa53f7a7e..48599f0e769 100644 --- a/arch/xtensa/include/kernel_arch_func.h +++ b/arch/xtensa/include/kernel_arch_func.h @@ -51,7 +51,7 @@ static ALWAYS_INLINE void arch_kernel_init(void) XTENSA_WSR(ZSR_CPU_STR, cpu0); #ifdef CONFIG_INIT_STACKS - char *stack_start = Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]); + char *stack_start = K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]); size_t stack_sz = K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]); char *stack_end = stack_start + stack_sz; diff --git a/include/zephyr/kernel/thread_stack.h b/include/zephyr/kernel/thread_stack.h index 67aa35abad5..941df220dc6 100644 --- a/include/zephyr/kernel/thread_stack.h +++ b/include/zephyr/kernel/thread_stack.h @@ -283,7 +283,7 @@ static inline char *z_stack_ptr_align(char *ptr) /** @} */ -static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) +static inline char *K_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) { return (char *)sym + K_KERNEL_STACK_RESERVED; } @@ -294,7 +294,7 @@ static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) #define K_THREAD_STACK_DEFINE K_KERNEL_STACK_DEFINE #define K_THREAD_STACK_ARRAY_DEFINE K_KERNEL_STACK_ARRAY_DEFINE #define K_THREAD_STACK_MEMBER K_KERNEL_STACK_MEMBER -#define Z_THREAD_STACK_BUFFER Z_KERNEL_STACK_BUFFER +#define Z_THREAD_STACK_BUFFER K_KERNEL_STACK_BUFFER #define K_THREAD_STACK_DECLARE K_KERNEL_STACK_DECLARE #define K_THREAD_STACK_ARRAY_DECLARE K_KERNEL_STACK_ARRAY_DECLARE #define K_THREAD_PINNED_STACK_DEFINE K_KERNEL_PINNED_STACK_DEFINE diff --git a/kernel/init.c b/kernel/init.c index 506e3efbc55..fe6c176a072 100644 --- a/kernel/init.c +++ b/kernel/init.c @@ -469,7 +469,7 @@ void z_init_cpu(int id) _kernel.cpus[id].idle_thread = &z_idle_threads[id]; _kernel.cpus[id].id = id; _kernel.cpus[id].irq_stack = - (Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) + + (K_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) + K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[id])); #ifdef CONFIG_SCHED_THREAD_USAGE_ALL _kernel.cpus[id].usage = &_kernel.usage[id]; diff --git a/kernel/thread.c b/kernel/thread.c index 729be274b09..ac76e44a5e1 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -392,7 +392,7 @@ static char *setup_thread_stack(struct k_thread *new_thread, { /* Object cannot host a user mode thread */ stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size); - stack_buf_start = Z_KERNEL_STACK_BUFFER(stack); + stack_buf_start = K_KERNEL_STACK_BUFFER(stack); stack_buf_size = stack_obj_size - K_KERNEL_STACK_RESERVED; /* Zephyr treats stack overflow as an app bug. But diff --git a/soc/espressif/esp32/esp32-mp.c b/soc/espressif/esp32/esp32-mp.c index c5ec588ea09..baaae7020d6 100644 --- a/soc/espressif/esp32/esp32-mp.c +++ b/soc/espressif/esp32/esp32-mp.c @@ -258,12 +258,12 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, sr.cpu = cpu_num; sr.fn = fn; - sr.stack_top = Z_KERNEL_STACK_BUFFER(stack) + sz; + sr.stack_top = K_KERNEL_STACK_BUFFER(stack) + sz; sr.arg = arg; sr.vecbase = vb; sr.alive = &alive_flag; - appcpu_top = Z_KERNEL_STACK_BUFFER(stack) + sz; + appcpu_top = K_KERNEL_STACK_BUFFER(stack) + sz; start_rec = &sr; diff --git a/soc/intel/intel_adsp/common/multiprocessing.c b/soc/intel/intel_adsp/common/multiprocessing.c index ff49b61188d..dfd7bd2106e 100644 --- a/soc/intel/intel_adsp/common/multiprocessing.c +++ b/soc/intel/intel_adsp/common/multiprocessing.c @@ -129,7 +129,7 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, start_rec.fn = fn; start_rec.arg = arg; - z_mp_stack_top = Z_KERNEL_STACK_BUFFER(stack) + sz; + z_mp_stack_top = K_KERNEL_STACK_BUFFER(stack) + sz; soc_start_core(cpu_num); } diff --git a/subsys/debug/thread_analyzer.c b/subsys/debug/thread_analyzer.c index 39a9bcf6aae..e7f4bb78e2b 100644 --- a/subsys/debug/thread_analyzer.c +++ b/subsys/debug/thread_analyzer.c @@ -134,7 +134,7 @@ static void isr_stacks(void) unsigned int num_cpus = arch_num_cpus(); for (int i = 0; i < num_cpus; i++) { - const uint8_t *buf = Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[i]); + const uint8_t *buf = K_KERNEL_STACK_BUFFER(z_interrupt_stacks[i]); size_t size = K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[i]); size_t unused; int err; diff --git a/subsys/shell/modules/kernel_service.c b/subsys/shell/modules/kernel_service.c index ff8079fabec..3d940ba5ee3 100644 --- a/subsys/shell/modules/kernel_service.c +++ b/subsys/shell/modules/kernel_service.c @@ -257,7 +257,7 @@ static int cmd_kernel_stacks(const struct shell *sh, for (int i = 0; i < num_cpus; i++) { size_t unused; - const uint8_t *buf = Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[i]); + const uint8_t *buf = K_KERNEL_STACK_BUFFER(z_interrupt_stacks[i]); size_t size = K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[i]); int err = z_stack_space_get(buf, size, &unused); diff --git a/tests/kernel/threads/thread_stack/src/main.c b/tests/kernel/threads/thread_stack/src/main.c index 73730d54d09..272cad329a6 100644 --- a/tests/kernel/threads/thread_stack/src/main.c +++ b/tests/kernel/threads/thread_stack/src/main.c @@ -121,7 +121,7 @@ void stack_buffer_scenarios(void) #endif { reserved = K_KERNEL_STACK_RESERVED; - stack_buf = Z_KERNEL_STACK_BUFFER(stack_obj); + stack_buf = K_KERNEL_STACK_BUFFER(stack_obj); alignment = Z_KERNEL_STACK_OBJ_ALIGN; } From efe30749de24b0778cdcf0fcb2b9a313aa43f5e1 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 22 Mar 2024 13:27:56 -0700 Subject: [PATCH 1546/2402] kernel: rename Z_THREAD_STACK_BUFFER to K_THREAD_STACK_BUFFER Simple rename to align the kernel naming scheme. This is being used throughout the tree, especially in the architecture code. As this is not a private API internal to kernel, prefix it appropriately with K_. Signed-off-by: Daniel Leung --- arch/arc/core/thread.c | 2 +- arch/arm/core/cortex_a_r/thread.c | 2 +- arch/arm/core/cortex_m/thread.c | 6 +++--- arch/riscv/core/thread.c | 2 +- include/zephyr/kernel/thread_stack.h | 4 ++-- kernel/thread.c | 2 +- tests/arch/arm/arm_no_multithreading/src/main.c | 4 ++-- tests/kernel/threads/thread_stack/src/main.c | 2 +- 8 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arc/core/thread.c b/arch/arc/core/thread.c index fd3f86c07e7..1c85a416ca6 100644 --- a/arch/arc/core/thread.c +++ b/arch/arc/core/thread.c @@ -286,7 +286,7 @@ FUNC_NORETURN void z_arc_switch_to_main_no_multithreading(k_thread_entry_t main_ _kernel.cpus[0].irq_stack = (K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]) + K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0])); - void *main_stack = (Z_THREAD_STACK_BUFFER(z_main_stack) + + void *main_stack = (K_THREAD_STACK_BUFFER(z_main_stack) + K_THREAD_STACK_SIZEOF(z_main_stack)); arch_irq_unlock(_ARC_V2_INIT_IRQ_LOCK_KEY); diff --git a/arch/arm/core/cortex_a_r/thread.c b/arch/arm/core/cortex_a_r/thread.c index e134fa76053..d5ccab76877 100644 --- a/arch/arm/core/cortex_a_r/thread.c +++ b/arch/arm/core/cortex_a_r/thread.c @@ -361,7 +361,7 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp guard_len, fault_addr, psp)) { /* Thread stack corruption */ - return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack); + return (uint32_t)K_THREAD_STACK_BUFFER(z_main_stack); } #endif #endif /* CONFIG_USERSPACE */ diff --git a/arch/arm/core/cortex_m/thread.c b/arch/arm/core/cortex_m/thread.c index 1eb8df924b7..980f35566c5 100644 --- a/arch/arm/core/cortex_m/thread.c +++ b/arch/arm/core/cortex_m/thread.c @@ -439,7 +439,7 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp guard_len, fault_addr, psp)) { /* Thread stack corruption */ - return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack); + return (uint32_t)K_THREAD_STACK_BUFFER(z_main_stack); } #endif #endif /* CONFIG_USERSPACE */ @@ -595,11 +595,11 @@ FUNC_NORETURN void z_arm_switch_to_main_no_multithreading( z_arm_prepare_switch_to_main(); /* Set PSP to the highest address of the main stack. */ - char *psp = Z_THREAD_STACK_BUFFER(z_main_stack) + + char *psp = K_THREAD_STACK_BUFFER(z_main_stack) + K_THREAD_STACK_SIZEOF(z_main_stack); #if defined(CONFIG_BUILTIN_STACK_GUARD) - char *psplim = (Z_THREAD_STACK_BUFFER(z_main_stack)); + char *psplim = (K_THREAD_STACK_BUFFER(z_main_stack)); /* Clear PSPLIM before setting it to guard the main stack area. */ __set_PSPLIM(0); #endif diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c index 20ef9f419b1..38d5dbde092 100644 --- a/arch/riscv/core/thread.c +++ b/arch/riscv/core/thread.c @@ -209,7 +209,7 @@ FUNC_NORETURN void z_riscv_switch_to_main_no_multithreading(k_thread_entry_t mai _kernel.cpus[0].irq_stack = (K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]) + K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0])); - main_stack = (Z_THREAD_STACK_BUFFER(z_main_stack) + + main_stack = (K_THREAD_STACK_BUFFER(z_main_stack) + K_THREAD_STACK_SIZEOF(z_main_stack)); __asm__ volatile ( diff --git a/include/zephyr/kernel/thread_stack.h b/include/zephyr/kernel/thread_stack.h index 941df220dc6..7f0ec60c464 100644 --- a/include/zephyr/kernel/thread_stack.h +++ b/include/zephyr/kernel/thread_stack.h @@ -294,7 +294,7 @@ static inline char *K_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) #define K_THREAD_STACK_DEFINE K_KERNEL_STACK_DEFINE #define K_THREAD_STACK_ARRAY_DEFINE K_KERNEL_STACK_ARRAY_DEFINE #define K_THREAD_STACK_MEMBER K_KERNEL_STACK_MEMBER -#define Z_THREAD_STACK_BUFFER K_KERNEL_STACK_BUFFER +#define K_THREAD_STACK_BUFFER K_KERNEL_STACK_BUFFER #define K_THREAD_STACK_DECLARE K_KERNEL_STACK_DECLARE #define K_THREAD_STACK_ARRAY_DECLARE K_KERNEL_STACK_ARRAY_DECLARE #define K_THREAD_PINNED_STACK_DEFINE K_KERNEL_PINNED_STACK_DEFINE @@ -650,7 +650,7 @@ static inline char *K_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) * @param sym defined stack symbol name * @return The buffer itself, a char * */ -static inline char *Z_THREAD_STACK_BUFFER(k_thread_stack_t *sym) +static inline char *K_THREAD_STACK_BUFFER(k_thread_stack_t *sym) { return (char *)sym + K_THREAD_STACK_RESERVED; } diff --git a/kernel/thread.c b/kernel/thread.c index ac76e44a5e1..8e3739e25c0 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -385,7 +385,7 @@ static char *setup_thread_stack(struct k_thread *new_thread, #ifdef CONFIG_USERSPACE if (z_stack_is_user_capable(stack)) { stack_obj_size = Z_THREAD_STACK_SIZE_ADJUST(stack_size); - stack_buf_start = Z_THREAD_STACK_BUFFER(stack); + stack_buf_start = K_THREAD_STACK_BUFFER(stack); stack_buf_size = stack_obj_size - K_THREAD_STACK_RESERVED; } else #endif /* CONFIG_USERSPACE */ diff --git a/tests/arch/arm/arm_no_multithreading/src/main.c b/tests/arch/arm/arm_no_multithreading/src/main.c index d525470edec..a1b5c67a28f 100644 --- a/tests/arch/arm/arm_no_multithreading/src/main.c +++ b/tests/arch/arm/arm_no_multithreading/src/main.c @@ -59,8 +59,8 @@ void test_main(void) printk("ARM no-multithreading test\n"); uint32_t psp = (uint32_t)__get_PSP(); - uint32_t main_stack_base = (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack); - uint32_t main_stack_top = (uint32_t)(Z_THREAD_STACK_BUFFER(z_main_stack) + + uint32_t main_stack_base = (uint32_t)K_THREAD_STACK_BUFFER(z_main_stack); + uint32_t main_stack_top = (uint32_t)(K_THREAD_STACK_BUFFER(z_main_stack) + K_THREAD_STACK_SIZEOF(z_main_stack)); __ASSERT( diff --git a/tests/kernel/threads/thread_stack/src/main.c b/tests/kernel/threads/thread_stack/src/main.c index 272cad329a6..64651dacee7 100644 --- a/tests/kernel/threads/thread_stack/src/main.c +++ b/tests/kernel/threads/thread_stack/src/main.c @@ -114,7 +114,7 @@ void stack_buffer_scenarios(void) #ifdef CONFIG_USERSPACE if (scenario_data.is_user) { reserved = K_THREAD_STACK_RESERVED; - stack_buf = Z_THREAD_STACK_BUFFER(stack_obj); + stack_buf = K_THREAD_STACK_BUFFER(stack_obj); /* always use the original size here */ alignment = Z_THREAD_STACK_OBJ_ALIGN(STEST_STACKSIZE); } else From afb41a1e403fe9f80a99a80af037b4fadc25fb7c Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 22 Mar 2024 13:35:55 -0700 Subject: [PATCH 1547/2402] kernel: correct thread_stack.h include guard The include guard for thread_stack.h was using the scheme when it was under include/sys. Since it has been moved to include/zephyr/kernel, name the guard accordingly. Signed-off-by: Daniel Leung --- include/zephyr/kernel/thread_stack.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/zephyr/kernel/thread_stack.h b/include/zephyr/kernel/thread_stack.h index 7f0ec60c464..a4bad55b9da 100644 --- a/include/zephyr/kernel/thread_stack.h +++ b/include/zephyr/kernel/thread_stack.h @@ -18,8 +18,8 @@ * @} */ -#ifndef ZEPHYR_INCLUDE_SYS_THREAD_STACK_H -#define ZEPHYR_INCLUDE_SYS_THREAD_STACK_H +#ifndef ZEPHYR_INCLUDE_KERNEL_THREAD_STACK_H +#define ZEPHYR_INCLUDE_KERNEL_THREAD_STACK_H #if !defined(_ASMLANGUAGE) #include @@ -662,4 +662,4 @@ static inline char *K_THREAD_STACK_BUFFER(k_thread_stack_t *sym) #endif #endif /* _ASMLANGUAGE */ -#endif /* ZEPHYR_INCLUDE_SYS_THREAD_STACK_H */ +#endif /* ZEPHYR_INCLUDE_KERNEL_THREAD_STACK_H */ From b9f66b26f8beb0c98ef716078aa6fc2a202e61cd Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Mon, 25 Mar 2024 10:22:18 -0700 Subject: [PATCH 1548/2402] tests: debug/coredump_backends: more space for qemu_x86 The reserved flash space for coredump is 4KB. However, the dump_stack itself is larger than 4KB due to kernel stack size adjustment. So enlarge the space for another page. Signed-off-by: Daniel Leung --- tests/subsys/debug/coredump_backends/boards/qemu_x86.overlay | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/subsys/debug/coredump_backends/boards/qemu_x86.overlay b/tests/subsys/debug/coredump_backends/boards/qemu_x86.overlay index ab232eb6fa3..6ceffda8610 100644 --- a/tests/subsys/debug/coredump_backends/boards/qemu_x86.overlay +++ b/tests/subsys/debug/coredump_backends/boards/qemu_x86.overlay @@ -16,7 +16,7 @@ coredump_partition: partition@31000 { label = "coredump-partition"; - reg = <0x31000 DT_SIZE_K(4)>; + reg = <0x31000 DT_SIZE_K(8)>; }; }; From 6cd7936f575e511f23bf75288f0dae25bad2fa51 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 22 Mar 2024 14:03:37 -0700 Subject: [PATCH 1549/2402] kernel: align kernel stack size declaration When kernel stack is defined as an array, K_KERNEL_STACK_LEN() is used to calculate the size for each stack in the array. However, standalone kernel stack has its size calculated by Z_KERNEL_STACK_SIZE_ADJUST() instead. Depending on the arch alignment requirement, they may not be the same... which could cause some confusions. So align them both to use K_KERNEL_STACK_LEN(). Signed-off-by: Daniel Leung --- arch/x86/core/intel64/cpu.c | 4 ++-- include/zephyr/kernel/thread_stack.h | 4 ++-- include/zephyr/posix/pthread.h | 2 +- kernel/dynamic.c | 2 +- kernel/thread.c | 2 +- .../source/COMPONENT_ZEPHYR/cyabs_rtos_zephyr.c | 2 +- tests/kernel/threads/dynamic_thread_stack/src/main.c | 2 +- tests/kernel/threads/thread_stack/src/main.c | 4 ++-- 8 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/core/intel64/cpu.c b/arch/x86/core/intel64/cpu.c index 3c17e2de593..d1aedcd4dec 100644 --- a/arch/x86/core/intel64/cpu.c +++ b/arch/x86/core/intel64/cpu.c @@ -107,9 +107,9 @@ struct x86_cpuboot x86_cpuboot[] = { .tr = X86_KERNEL_CPU0_TR, .gs_base = &tss0, .sp = (uint64_t) z_interrupt_stacks[0] + - Z_KERNEL_STACK_SIZE_ADJUST(CONFIG_ISR_STACK_SIZE), + K_KERNEL_STACK_LEN(CONFIG_ISR_STACK_SIZE), .stack_size = - Z_KERNEL_STACK_SIZE_ADJUST(CONFIG_ISR_STACK_SIZE), + K_KERNEL_STACK_LEN(CONFIG_ISR_STACK_SIZE), .fn = z_prep_c, .arg = &x86_cpu_boot_arg, }, diff --git a/include/zephyr/kernel/thread_stack.h b/include/zephyr/kernel/thread_stack.h index a4bad55b9da..3598742a249 100644 --- a/include/zephyr/kernel/thread_stack.h +++ b/include/zephyr/kernel/thread_stack.h @@ -123,7 +123,7 @@ static inline char *z_stack_ptr_align(char *ptr) */ #define K_KERNEL_STACK_DECLARE(sym, size) \ extern struct z_thread_stack_element \ - sym[Z_KERNEL_STACK_SIZE_ADJUST(size)] + sym[K_KERNEL_STACK_LEN(size)] /** * @brief Declare a reference to a thread stack array @@ -175,7 +175,7 @@ static inline char *z_stack_ptr_align(char *ptr) #define Z_KERNEL_STACK_DEFINE_IN(sym, size, lsect) \ struct z_thread_stack_element lsect \ __aligned(Z_KERNEL_STACK_OBJ_ALIGN) \ - sym[Z_KERNEL_STACK_SIZE_ADJUST(size)] + sym[K_KERNEL_STACK_LEN(size)] /** * @brief Define a toplevel array of kernel stack memory regions in specified section diff --git a/include/zephyr/posix/pthread.h b/include/zephyr/posix/pthread.h index eb786f80e19..d950c9ea7fd 100644 --- a/include/zephyr/posix/pthread.h +++ b/include/zephyr/posix/pthread.h @@ -49,7 +49,7 @@ extern "C" { #define PTHREAD_ONCE_INIT {0} /* The minimum allowable stack size */ -#define PTHREAD_STACK_MIN Z_KERNEL_STACK_SIZE_ADJUST(0) +#define PTHREAD_STACK_MIN K_KERNEL_STACK_LEN(0) /** * @brief Declare a condition variable as initialized diff --git a/kernel/dynamic.c b/kernel/dynamic.c index 66cd99853c0..d03e3669346 100644 --- a/kernel/dynamic.c +++ b/kernel/dynamic.c @@ -75,7 +75,7 @@ static k_thread_stack_t *stack_alloc_dyn(size_t size, int flags) } return z_thread_stack_alloc_dyn(Z_KERNEL_STACK_OBJ_ALIGN, - Z_KERNEL_STACK_SIZE_ADJUST(size)); + K_KERNEL_STACK_LEN(size)); } k_thread_stack_t *z_impl_k_thread_stack_alloc(size_t size, int flags) diff --git a/kernel/thread.c b/kernel/thread.c index 8e3739e25c0..5d705e114b1 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -391,7 +391,7 @@ static char *setup_thread_stack(struct k_thread *new_thread, #endif /* CONFIG_USERSPACE */ { /* Object cannot host a user mode thread */ - stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size); + stack_obj_size = K_KERNEL_STACK_LEN(stack_size); stack_buf_start = K_KERNEL_STACK_BUFFER(stack); stack_buf_size = stack_obj_size - K_KERNEL_STACK_RESERVED; diff --git a/modules/hal_infineon/abstraction-rtos/source/COMPONENT_ZEPHYR/cyabs_rtos_zephyr.c b/modules/hal_infineon/abstraction-rtos/source/COMPONENT_ZEPHYR/cyabs_rtos_zephyr.c index 7c7197fafbd..3e1acbbc17b 100644 --- a/modules/hal_infineon/abstraction-rtos/source/COMPONENT_ZEPHYR/cyabs_rtos_zephyr.c +++ b/modules/hal_infineon/abstraction-rtos/source/COMPONENT_ZEPHYR/cyabs_rtos_zephyr.c @@ -122,7 +122,7 @@ cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_ /* Allocate stack if NULL was passed */ if ((uint32_t *)stack == NULL) { stack_alloc = k_aligned_alloc(Z_KERNEL_STACK_OBJ_ALIGN, - Z_KERNEL_STACK_SIZE_ADJUST(stack_size)); + K_KERNEL_STACK_LEN(stack_size)); /* Store pointer to allocated stack, * NULL if not allocated by cy_rtos_thread_create (passed by application). diff --git a/tests/kernel/threads/dynamic_thread_stack/src/main.c b/tests/kernel/threads/dynamic_thread_stack/src/main.c index 1e93beb3c66..c2446e04d68 100644 --- a/tests/kernel/threads/dynamic_thread_stack/src/main.c +++ b/tests/kernel/threads/dynamic_thread_stack/src/main.c @@ -14,7 +14,7 @@ #ifdef CONFIG_USERSPACE #define STACK_OBJ_SIZE Z_THREAD_STACK_SIZE_ADJUST(CONFIG_DYNAMIC_THREAD_STACK_SIZE) #else -#define STACK_OBJ_SIZE Z_KERNEL_STACK_SIZE_ADJUST(CONFIG_DYNAMIC_THREAD_STACK_SIZE) +#define STACK_OBJ_SIZE K_KERNEL_STACK_LEN(CONFIG_DYNAMIC_THREAD_STACK_SIZE) #endif #define MAX_HEAP_STACKS (POOL_SIZE / STACK_OBJ_SIZE) diff --git a/tests/kernel/threads/thread_stack/src/main.c b/tests/kernel/threads/thread_stack/src/main.c index 64651dacee7..df68c060323 100644 --- a/tests/kernel/threads/thread_stack/src/main.c +++ b/tests/kernel/threads/thread_stack/src/main.c @@ -235,7 +235,7 @@ void stack_buffer_scenarios(void) * K_THREAD_STACK_SIZEOF(my_stack) * * K_KERNEL_STACK_DEFINE(my_kern_stack, Y): - * Z_KERNEL_STACK_SIZE_ADJUST(Y) - K_KERNEL_STACK_RESERVED == + * K_KERNEL_STACK_LEN(Y) - K_KERNEL_STACK_RESERVED == * K_KERNEL_STACK_SIZEOF(my_stack) */ #ifdef CONFIG_USERSPACE @@ -245,7 +245,7 @@ void stack_buffer_scenarios(void) } else #endif { - adjusted = Z_KERNEL_STACK_SIZE_ADJUST(scenario_data.declared_size); + adjusted = K_KERNEL_STACK_LEN(scenario_data.declared_size); } adjusted -= reserved; From d34351d9945435fd29ff5b2ecdf4805cf784f779 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 22 Mar 2024 14:11:49 -0700 Subject: [PATCH 1550/2402] kernel: align thread stack size declaration When thread stack is defined as an array, K_THREAD_STACK_LEN() is used to calculate the size for each stack in the array. However, standalone thread stack has its size calculated by Z_THREAD_STACK_SIZE_ADJUST() instead. Depending on the arch alignment requirement, they may not be the same... which could cause some confusions. So align them both to use K_THREAD_STACK_LEN(). Signed-off-by: Daniel Leung --- arch/x86/core/userspace.c | 2 +- include/zephyr/kernel/thread_stack.h | 4 ++-- kernel/thread.c | 2 +- kernel/userspace.c | 6 +++--- tests/kernel/fatal/exception/src/main.c | 4 ++-- tests/kernel/threads/dynamic_thread_stack/src/main.c | 2 +- tests/kernel/threads/thread_stack/src/main.c | 4 ++-- 7 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/x86/core/userspace.c b/arch/x86/core/userspace.c index 750c9775943..09e7945303d 100644 --- a/arch/x86/core/userspace.c +++ b/arch/x86/core/userspace.c @@ -132,7 +132,7 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, size_t stack_aligned_size; stack_start = POINTER_TO_UINT(_current->stack_obj); - stack_size = Z_THREAD_STACK_SIZE_ADJUST(_current->stack_info.size); + stack_size = K_THREAD_STACK_LEN(_current->stack_info.size); #if defined(CONFIG_HW_STACK_PROTECTION) /* With hardware stack protection, the first page of stack diff --git a/include/zephyr/kernel/thread_stack.h b/include/zephyr/kernel/thread_stack.h index 3598742a249..a8151cce9d1 100644 --- a/include/zephyr/kernel/thread_stack.h +++ b/include/zephyr/kernel/thread_stack.h @@ -404,7 +404,7 @@ static inline char *K_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) */ #define K_THREAD_STACK_DECLARE(sym, size) \ extern struct z_thread_stack_element \ - sym[Z_THREAD_STACK_SIZE_ADJUST(size)] + sym[K_THREAD_STACK_LEN(size)] /** * @brief Declare a reference to a thread stack array @@ -467,7 +467,7 @@ static inline char *K_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) #define Z_THREAD_STACK_DEFINE_IN(sym, size, lsect) \ struct z_thread_stack_element lsect \ __aligned(Z_THREAD_STACK_OBJ_ALIGN(size)) \ - sym[Z_THREAD_STACK_SIZE_ADJUST(size)] + sym[K_THREAD_STACK_LEN(size)] /** * @brief Define a toplevel array of thread stack memory regions in specified region diff --git a/kernel/thread.c b/kernel/thread.c index 5d705e114b1..115bf34a3b6 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -384,7 +384,7 @@ static char *setup_thread_stack(struct k_thread *new_thread, #ifdef CONFIG_USERSPACE if (z_stack_is_user_capable(stack)) { - stack_obj_size = Z_THREAD_STACK_SIZE_ADJUST(stack_size); + stack_obj_size = K_THREAD_STACK_LEN(stack_size); stack_buf_start = K_THREAD_STACK_BUFFER(stack); stack_buf_size = stack_obj_size - K_THREAD_STACK_RESERVED; } else diff --git a/kernel/userspace.c b/kernel/userspace.c index c87421d0725..0d9a437570a 100644 --- a/kernel/userspace.c +++ b/kernel/userspace.c @@ -59,13 +59,13 @@ static struct k_spinlock objfree_lock; /* k_object_free */ #if defined(CONFIG_ARM_MPU) || defined(CONFIG_ARC_MPU) #define STACK_ELEMENT_DATA_SIZE(size) \ (sizeof(struct z_stack_data) + CONFIG_PRIVILEGED_STACK_SIZE + \ - Z_THREAD_STACK_OBJ_ALIGN(size) + Z_THREAD_STACK_SIZE_ADJUST(size)) + Z_THREAD_STACK_OBJ_ALIGN(size) + K_THREAD_STACK_LEN(size)) #else #define STACK_ELEMENT_DATA_SIZE(size) (sizeof(struct z_stack_data) + \ - Z_THREAD_STACK_SIZE_ADJUST(size)) + K_THREAD_STACK_LEN(size)) #endif /* CONFIG_ARM_MPU || CONFIG_ARC_MPU */ #else -#define STACK_ELEMENT_DATA_SIZE(size) Z_THREAD_STACK_SIZE_ADJUST(size) +#define STACK_ELEMENT_DATA_SIZE(size) K_THREAD_STACK_LEN(size) #endif /* CONFIG_GEN_PRIV_STACKS */ #endif /* CONFIG_DYNAMIC_OBJECTS */ diff --git a/tests/kernel/fatal/exception/src/main.c b/tests/kernel/fatal/exception/src/main.c index 5a44b215b42..30050d3ca36 100644 --- a/tests/kernel/fatal/exception/src/main.c +++ b/tests/kernel/fatal/exception/src/main.c @@ -465,7 +465,7 @@ static void *fatal_setup(void) obj_size = K_THREAD_STACK_SIZEOF(overflow_stack); #if defined(CONFIG_USERSPACE) - obj_size = Z_THREAD_STACK_SIZE_ADJUST(obj_size); + obj_size = K_THREAD_STACK_LEN(obj_size); #endif k_mem_region_align(&pin_addr, &pin_size, @@ -477,7 +477,7 @@ static void *fatal_setup(void) obj_size = K_THREAD_STACK_SIZEOF(alt_stack); #if defined(CONFIG_USERSPACE) - obj_size = Z_THREAD_STACK_SIZE_ADJUST(obj_size); + obj_size = K_THREAD_STACK_LEN(obj_size); #endif k_mem_region_align(&pin_addr, &pin_size, diff --git a/tests/kernel/threads/dynamic_thread_stack/src/main.c b/tests/kernel/threads/dynamic_thread_stack/src/main.c index c2446e04d68..bb15d824d81 100644 --- a/tests/kernel/threads/dynamic_thread_stack/src/main.c +++ b/tests/kernel/threads/dynamic_thread_stack/src/main.c @@ -12,7 +12,7 @@ #define POOL_SIZE 20480 #ifdef CONFIG_USERSPACE -#define STACK_OBJ_SIZE Z_THREAD_STACK_SIZE_ADJUST(CONFIG_DYNAMIC_THREAD_STACK_SIZE) +#define STACK_OBJ_SIZE K_THREAD_STACK_LEN(CONFIG_DYNAMIC_THREAD_STACK_SIZE) #else #define STACK_OBJ_SIZE K_KERNEL_STACK_LEN(CONFIG_DYNAMIC_THREAD_STACK_SIZE) #endif diff --git a/tests/kernel/threads/thread_stack/src/main.c b/tests/kernel/threads/thread_stack/src/main.c index df68c060323..cf9b5d8c3a5 100644 --- a/tests/kernel/threads/thread_stack/src/main.c +++ b/tests/kernel/threads/thread_stack/src/main.c @@ -231,7 +231,7 @@ void stack_buffer_scenarios(void) * For some stack declared with: * * K_THREAD_STACK_DEFINE(my_stack, X); - * Z_THREAD_STACK_SIZE_ADJUST(X) - K_THREAD_STACK_RESERVED == + * K_THREAD_STACK_LEN(X) - K_THREAD_STACK_RESERVED == * K_THREAD_STACK_SIZEOF(my_stack) * * K_KERNEL_STACK_DEFINE(my_kern_stack, Y): @@ -241,7 +241,7 @@ void stack_buffer_scenarios(void) #ifdef CONFIG_USERSPACE /* Not defined if user mode disabled, all stacks are kernel stacks */ if (scenario_data.is_user) { - adjusted = Z_THREAD_STACK_SIZE_ADJUST(scenario_data.declared_size); + adjusted = K_THREAD_STACK_LEN(scenario_data.declared_size); } else #endif { From 2abce42f80fa108ad05d1450fd62a05c2a25c95c Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Wed, 27 Mar 2024 18:42:59 -0400 Subject: [PATCH 1551/2402] posix: create a typedef for in_addr_t A recent change made it so that in_addr_t was no longer defined. Define in_addr_t in arpa/inet.h Signed-off-by: Chris Friedt --- include/zephyr/posix/arpa/inet.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/zephyr/posix/arpa/inet.h b/include/zephyr/posix/arpa/inet.h index e4e69340204..4e651d0a79f 100644 --- a/include/zephyr/posix/arpa/inet.h +++ b/include/zephyr/posix/arpa/inet.h @@ -32,6 +32,8 @@ static inline int inet_pton(sa_family_t family, const char *src, void *dst) #endif /* CONFIG_NET_SOCKETS_POSIX_NAMES */ +typedef uint32_t in_addr_t; + in_addr_t inet_addr(const char *cp); char *inet_ntoa(struct in_addr in); From bec115fbcfe778cd1653161a7920b05a5e01ea8d Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Wed, 27 Mar 2024 18:54:53 -0400 Subject: [PATCH 1552/2402] samples: thrift: add dependencies for c11 threads The thrift hello/client sample did not have the required kconfig options for some reason. Adding these seemed to fix the issue. CONFIG_COMMON_LIBC_THRD=y CONFIG_DYNAMIC_THREAD=y CONFIG_THREAD_STACK_INFO=y Signed-off-by: Chris Friedt --- samples/modules/thrift/hello/client/prj.conf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/samples/modules/thrift/hello/client/prj.conf b/samples/modules/thrift/hello/client/prj.conf index 9ca8b3be538..a83715ddfc7 100644 --- a/samples/modules/thrift/hello/client/prj.conf +++ b/samples/modules/thrift/hello/client/prj.conf @@ -6,6 +6,9 @@ CONFIG_CPP=y CONFIG_STD_CPP17=y CONFIG_CPP_EXCEPTIONS=y CONFIG_POSIX_API=y +CONFIG_COMMON_LIBC_THRD=y +CONFIG_DYNAMIC_THREAD=y +CONFIG_THREAD_STACK_INFO=y CONFIG_NETWORKING=y CONFIG_NET_SOCKETS=y CONFIG_NET_SOCKETPAIR=y From 43ef605be56387fe6668673aed9779cc70f6c5a0 Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Sun, 24 Mar 2024 10:58:35 +0900 Subject: [PATCH 1553/2402] ci: Switch to CI image v0.26.11 This commit updates the CI workflows to use the CI image v0.26.11, which includes bsim 2.2 and nrf-regtool 5.1.0. Signed-off-by: Stephanos Ioannidis --- .github/workflows/bsim-tests.yaml | 2 +- .github/workflows/clang.yaml | 2 +- .github/workflows/codecov.yaml | 2 +- .github/workflows/errno.yml | 2 +- .github/workflows/footprint-tracking.yml | 2 +- .github/workflows/twister.yaml | 4 ++-- .github/workflows/twister_tests_blackbox.yml | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 9de3f36458c..0574134f830 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -34,7 +34,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 options: '--entrypoint /bin/bash' env: ZEPHYR_TOOLCHAIN_VARIANT: zephyr diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index edba96022e7..77a36a0c931 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -12,7 +12,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 options: '--entrypoint /bin/bash' strategy: fail-fast: false diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 158489d5ba1..1c5ded582f0 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -14,7 +14,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 options: '--entrypoint /bin/bash' strategy: fail-fast: false diff --git a/.github/workflows/errno.yml b/.github/workflows/errno.yml index 9e5589aeb0a..593fe916deb 100644 --- a/.github/workflows/errno.yml +++ b/.github/workflows/errno.yml @@ -10,7 +10,7 @@ jobs: check-errno: runs-on: ubuntu-22.04 container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.9 + image: ghcr.io/zephyrproject-rtos/ci:v0.26.11 steps: - name: Apply container owner mismatch workaround diff --git a/.github/workflows/footprint-tracking.yml b/.github/workflows/footprint-tracking.yml index be7969eb05e..5f355e944fb 100644 --- a/.github/workflows/footprint-tracking.yml +++ b/.github/workflows/footprint-tracking.yml @@ -26,7 +26,7 @@ jobs: group: zephyr-runner-v2-linux-x64-4xlarge if: github.repository_owner == 'zephyrproject-rtos' container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 options: '--entrypoint /bin/bash' strategy: fail-fast: false diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index 0ac79809a3e..40f9fe04c2d 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -25,7 +25,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 options: '--entrypoint /bin/bash' outputs: subset: ${{ steps.output-services.outputs.subset }} @@ -129,7 +129,7 @@ jobs: needs: twister-build-prep if: needs.twister-build-prep.outputs.size != 0 container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.9.20240223 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.11.20240324 options: '--entrypoint /bin/bash' strategy: fail-fast: false diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index 131d773478a..7b0e1893225 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -24,7 +24,7 @@ jobs: python-version: [3.8, 3.9, '3.10', '3.11', '3.12'] os: [ubuntu-22.04] container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.9 + image: ghcr.io/zephyrproject-rtos/ci:v0.26.11 steps: - name: Apply Container Owner Mismatch Workaround From b8214b6739705eceaa10bc4b18de41d1c88c45ab Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Mon, 12 Feb 2024 15:07:50 +0200 Subject: [PATCH 1554/2402] dts: xtensa: nxp_imx8: add SAI1 node Add node for NXP's i.MX8QM/i.MX8QXP AUDIO SAI1 IP. Signed-off-by: Laurentiu Mihalcea --- dts/xtensa/nxp/nxp_imx8.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/dts/xtensa/nxp/nxp_imx8.dtsi b/dts/xtensa/nxp/nxp_imx8.dtsi index 80b715a7f16..ec97e8d1816 100644 --- a/dts/xtensa/nxp/nxp_imx8.dtsi +++ b/dts/xtensa/nxp/nxp_imx8.dtsi @@ -124,6 +124,17 @@ status = "disabled"; }; + sai1: dai@59050000 { + compatible = "nxp,dai-sai"; + reg = <0x59050000 DT_SIZE_K(64)>; + interrupt-parent = <&master5>; + interrupts = <28>; + dai-index = <1>; + dmas = <&edma0 15 0>, <&edma0 14 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + /* LSIO MU2, used to interact with the SCFW */ scu_mu: mailbox@5d1d0000 { reg = <0x5d1d0000 DT_SIZE_K(64)>; From 951763939034bd14df26dc6cfdfbcc3a6afedb03 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Tue, 12 Mar 2024 17:26:41 +0200 Subject: [PATCH 1555/2402] nxp: imx8ulp: change SOC name to MIMX8UD7 The SOC name `imx8ulp` has been just a placeholder until support for the SOC's ADSP (since this is the only core that's supported in Zephyr) could be added to the NXP HAL. Now that the support has been added, to make use of it, the SOC name `imx8ulp` has to be changed to `mimx8ud7`. As such, this commit does the following: 1) Introduces SOC part number configuration - needed by some HAL headers. 2) Replaces all occurrences of `imx8ulp` (as the SOC name) with `mimx8ud7`. 3) Enables `CONFIG_HAS_MCUX`. 4) Aligns all `CONFIG_SOC_` configurations with the new SOC name. 5) Updates SOF hash. This is needed to fix build issues caused by this name change. This is not done in a separate commit to preserve bisectability. Signed-off-by: Laurentiu Mihalcea --- boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk | 3 ++- boards/nxp/imx8ulp_evk/board.cmake | 2 +- boards/nxp/imx8ulp_evk/board.yml | 2 +- ...lp_adsp.dts => imx8ulp_evk_mimx8ud7_adsp.dts} | 0 ..._adsp.yaml => imx8ulp_evk_mimx8ud7_adsp.yaml} | 2 +- ...onfig => imx8ulp_evk_mimx8ud7_adsp_defconfig} | 0 soc/nxp/imx/imx8ulp/CMakeLists.txt | 2 +- soc/nxp/imx/imx8ulp/Kconfig | 9 ++++++++- soc/nxp/imx/imx8ulp/Kconfig.defconfig | 4 ++-- soc/nxp/imx/imx8ulp/Kconfig.soc | 16 +++++++++++----- soc/nxp/imx/soc.yml | 2 +- submanifests/optional.yaml | 2 +- 12 files changed, 29 insertions(+), 15 deletions(-) rename boards/nxp/imx8ulp_evk/{imx8ulp_evk_imx8ulp_adsp.dts => imx8ulp_evk_mimx8ud7_adsp.dts} (100%) rename boards/nxp/imx8ulp_evk/{imx8ulp_evk_imx8ulp_adsp.yaml => imx8ulp_evk_mimx8ud7_adsp.yaml} (75%) rename boards/nxp/imx8ulp_evk/{imx8ulp_evk_imx8ulp_adsp_defconfig => imx8ulp_evk_mimx8ud7_adsp_defconfig} (100%) diff --git a/boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk b/boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk index dbf611081ab..77d81829dc3 100644 --- a/boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk +++ b/boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk @@ -4,4 +4,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_IMX8ULP_EVK - select SOC_MIMX8ULP_ADSP if BOARD_IMX8ULP_EVK_IMX8ULP_ADSP + select SOC_MIMX8UD7_ADSP if BOARD_IMX8ULP_EVK_MIMX8UD7_ADSP + select SOC_PART_NUMBER_MIMX8UD7DVK08 diff --git a/boards/nxp/imx8ulp_evk/board.cmake b/boards/nxp/imx8ulp_evk/board.cmake index 97e0a80ba04..572983699e4 100644 --- a/boards/nxp/imx8ulp_evk/board.cmake +++ b/boards/nxp/imx8ulp_evk/board.cmake @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -if(CONFIG_SOC_MIMX8ULP_ADSP) +if(CONFIG_SOC_MIMX8UD7_ADSP) board_set_flasher_ifnset(misc-flasher) board_finalize_runner_args(misc-flasher) diff --git a/boards/nxp/imx8ulp_evk/board.yml b/boards/nxp/imx8ulp_evk/board.yml index b401615d7d7..bd5e16dc93d 100644 --- a/boards/nxp/imx8ulp_evk/board.yml +++ b/boards/nxp/imx8ulp_evk/board.yml @@ -2,4 +2,4 @@ board: name: imx8ulp_evk vendor: nxp socs: - - name: imx8ulp + - name: mimx8ud7 diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.dts b/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.dts similarity index 100% rename from boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.dts rename to boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.dts diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.yaml b/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.yaml similarity index 75% rename from boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.yaml rename to boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.yaml index 437d112ee58..037b2ef9095 100644 --- a/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.yaml +++ b/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.yaml @@ -1,4 +1,4 @@ -identifier: imx8ulp_evk/imx8ulp/adsp +identifier: imx8ulp_evk/mimx8ud7/adsp name: NXP i.MX 8ULP Audio DSP type: mcu arch: xtensa diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp_defconfig b/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp_defconfig similarity index 100% rename from boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp_defconfig rename to boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp_defconfig diff --git a/soc/nxp/imx/imx8ulp/CMakeLists.txt b/soc/nxp/imx/imx8ulp/CMakeLists.txt index 55a73218273..ec3ef98ebec 100644 --- a/soc/nxp/imx/imx8ulp/CMakeLists.txt +++ b/soc/nxp/imx/imx8ulp/CMakeLists.txt @@ -1,7 +1,7 @@ # Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_MIMX8ULP_ADSP) +if(CONFIG_SOC_MIMX8UD7_ADSP) zephyr_include_directories(adsp) add_subdirectory(adsp) diff --git a/soc/nxp/imx/imx8ulp/Kconfig b/soc/nxp/imx/imx8ulp/Kconfig index d0f92357c2d..66da731ca94 100644 --- a/soc/nxp/imx/imx8ulp/Kconfig +++ b/soc/nxp/imx/imx8ulp/Kconfig @@ -1,7 +1,7 @@ # Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 -config SOC_MIMX8ULP_ADSP +config SOC_MIMX8UD7_ADSP select XTENSA select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") select XTENSA_RESET_VECTOR @@ -10,3 +10,10 @@ config SOC_MIMX8ULP_ADSP select GEN_ISR_TABLES select XTENSA_SMALL_VECTOR_TABLE_ENTRY select CPU_HAS_DCACHE + select HAS_MCUX + +# note: the NXP HAL refers to the HIFI4 DSP as +# `dsp1` and the Fusion DSP as `dsp0`, thus the +# suffix(es) below +config MCUX_CORE_SUFFIX + default "_dsp1" if SOC_MIMX8UD7_ADSP diff --git a/soc/nxp/imx/imx8ulp/Kconfig.defconfig b/soc/nxp/imx/imx8ulp/Kconfig.defconfig index f29f1c7d56e..55a8e61ea62 100644 --- a/soc/nxp/imx/imx8ulp/Kconfig.defconfig +++ b/soc/nxp/imx/imx8ulp/Kconfig.defconfig @@ -3,7 +3,7 @@ if SOC_SERIES_IMX8ULP -if SOC_MIMX8ULP_ADSP +if SOC_MIMX8UD7_ADSP config SYS_CLOCK_HW_CYCLES_PER_SEC default 475200000 @@ -40,6 +40,6 @@ config TEST_LOGGING_DEFAULTS default n depends on TEST -endif # SOC_MIMX8ULP_ADSP +endif # SOC_MIMX8UD7_ADSP endif # SOC_SERIES_IMX8ULP diff --git a/soc/nxp/imx/imx8ulp/Kconfig.soc b/soc/nxp/imx/imx8ulp/Kconfig.soc index b7d4cadef7c..49f0bc6dfd0 100644 --- a/soc/nxp/imx/imx8ulp/Kconfig.soc +++ b/soc/nxp/imx/imx8ulp/Kconfig.soc @@ -8,19 +8,25 @@ config SOC_SERIES_IMX8ULP config SOC_SERIES default "imx8ulp" if SOC_SERIES_IMX8ULP -config SOC_MIMX8ULP +config SOC_MIMX8UD7 bool select SOC_SERIES_IMX8ULP config SOC - default "imx8ulp" if SOC_MIMX8ULP + default "mimx8ud7" if SOC_MIMX8UD7 -config SOC_MIMX8ULP_ADSP +config SOC_MIMX8UD7_ADSP bool - select SOC_MIMX8ULP + select SOC_MIMX8UD7 help Enable support for NXP i.MX 8ULP Audio DSP config SOC_TOOLCHAIN_NAME string - default "nxp_imx8ulp_adsp" if SOC_MIMX8ULP_ADSP + default "nxp_imx8ulp_adsp" if SOC_MIMX8UD7_ADSP + +config SOC_PART_NUMBER_MIMX8UD7DVK08 + bool + +config SOC_PART_NUMBER + default "MIMX8UD7DVK08" if SOC_PART_NUMBER_MIMX8UD7DVK08 diff --git a/soc/nxp/imx/soc.yml b/soc/nxp/imx/soc.yml index c1a4c16b37b..307b7d8c5da 100644 --- a/soc/nxp/imx/soc.yml +++ b/soc/nxp/imx/soc.yml @@ -18,7 +18,7 @@ family: - name: m4 - name: imx8ulp socs: - - name: imx8ulp + - name: mimx8ud7 cpuclusters: - name: adsp - name: f1_dsp diff --git a/submanifests/optional.yaml b/submanifests/optional.yaml index 39faa5f3887..79015e632fd 100644 --- a/submanifests/optional.yaml +++ b/submanifests/optional.yaml @@ -34,7 +34,7 @@ manifest: groups: - optional - name: sof - revision: 3e70d036a2df94b854add51742681b64ea0df729 + revision: 1c1dd3d83d85c3bd2bfd16f6d5bb101e764cb698 path: modules/audio/sof remote: upstream groups: From 24471f5000e34d5cc169c40ea31b59055378b0b2 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Tue, 12 Mar 2024 17:31:22 +0200 Subject: [PATCH 1556/2402] boards: deprecated: change SOC name for imx8ulp_evk board The SOC name for the `imx8ulp_evk` board has been changed to `mimx8ud7`. As such, update `deprecated.cmake` to reflect this change. Signed-off-by: Laurentiu Mihalcea --- boards/deprecated.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 89fe2515d02..8887b1b2749 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -588,7 +588,7 @@ set(nxp_adsp_imx8m_DEPRECATED imx8mp_evk/mimx8ml8/adsp ) set(nxp_adsp_imx8ulp_DEPRECATED - imx8ulp_evk/imx8ulp/adsp + imx8ulp_evk/mimx8ud7/adsp ) set(nxp_adsp_imx8x_DEPRECATED imx8qxp_mek/mimx8qx6/adsp From 2058d8f139e9b7755fdf6b4fac59e10f1edea960 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 17 Mar 2024 15:32:29 +0200 Subject: [PATCH 1557/2402] net: ethernet: VLAN overhaul and refactoring Re-implement the VLAN support inside the network stack. All the user facing APIs stay as is but internally the VLANs are implemented using the L2 virtual interfaces. Signed-off-by: Jukka Rissanen --- include/zephyr/net/ethernet.h | 94 ++-- include/zephyr/net/virtual.h | 3 + subsys/net/l2/ethernet/CMakeLists.txt | 1 + subsys/net/l2/ethernet/Kconfig | 10 +- subsys/net/l2/ethernet/arp.c | 10 +- subsys/net/l2/ethernet/ethernet.c | 467 +++---------------- subsys/net/l2/ethernet/vlan.c | 640 ++++++++++++++++++++++++++ 7 files changed, 764 insertions(+), 461 deletions(-) create mode 100644 subsys/net/l2/ethernet/vlan.c diff --git a/include/zephyr/net/ethernet.h b/include/zephyr/net/ethernet.h index 024eb108df2..8fc6881eed1 100644 --- a/include/zephyr/net/ethernet.h +++ b/include/zephyr/net/ethernet.h @@ -594,17 +594,6 @@ struct ethernet_context { */ atomic_t flags; -#if defined(CONFIG_NET_VLAN) - struct ethernet_vlan vlan[NET_VLAN_MAX_COUNT]; - - /** Array that will help when checking if VLAN is enabled for - * some specific network interface. Requires that VLAN count - * NET_VLAN_MAX_COUNT is not smaller than the actual number - * of network interfaces. - */ - ATOMIC_DEFINE(interfaces, NET_VLAN_MAX_COUNT); -#endif - #if defined(CONFIG_NET_ETHERNET_BRIDGE) struct eth_bridge_iface_context bridge; #endif @@ -653,14 +642,6 @@ struct ethernet_context { dsa_send_t dsa_send; #endif -#if defined(CONFIG_NET_VLAN) - /** Flag that tells whether how many VLAN tags are enabled for this - * context. The same information can be dug from the vlan array but - * this saves some time in RX path. - */ - int8_t vlan_enabled; -#endif - /** Is network carrier up */ bool is_net_carrier_up : 1; @@ -841,6 +822,9 @@ int net_eth_vlan_enable(struct net_if *iface, uint16_t tag); #else static inline int net_eth_vlan_enable(struct net_if *iface, uint16_t tag) { + ARG_UNUSED(iface); + ARG_UNUSED(tag); + return -EINVAL; } #endif @@ -858,14 +842,20 @@ int net_eth_vlan_disable(struct net_if *iface, uint16_t tag); #else static inline int net_eth_vlan_disable(struct net_if *iface, uint16_t tag) { + ARG_UNUSED(iface); + ARG_UNUSED(tag); + return -EINVAL; } #endif /** - * @brief Return VLAN tag specified to network interface + * @brief Return VLAN tag specified to network interface. + * + * Note that the interface parameter must be the VLAN interface, + * and not the Ethernet one. * - * @param iface Network interface. + * @param iface VLAN network interface. * * @return VLAN tag for this interface or NET_VLAN_TAG_UNSPEC if VLAN * is not configured for that interface. @@ -875,6 +865,8 @@ uint16_t net_eth_get_vlan_tag(struct net_if *iface); #else static inline uint16_t net_eth_get_vlan_tag(struct net_if *iface) { + ARG_UNUSED(iface); + return NET_VLAN_TAG_UNSPEC; } #endif @@ -882,8 +874,7 @@ static inline uint16_t net_eth_get_vlan_tag(struct net_if *iface) /** * @brief Return network interface related to this VLAN tag * - * @param iface Master network interface. This is used to get the - * pointer to ethernet L2 context + * @param iface Main network interface (not the VLAN one). * @param tag VLAN tag * * @return Network interface related to this tag or NULL if no such interface @@ -895,17 +886,46 @@ struct net_if *net_eth_get_vlan_iface(struct net_if *iface, uint16_t tag); static inline struct net_if *net_eth_get_vlan_iface(struct net_if *iface, uint16_t tag) { + ARG_UNUSED(iface); + ARG_UNUSED(tag); + + return NULL; +} +#endif + +/** + * @brief Return main network interface that is attached to this VLAN tag. + * + * @param iface VLAN network interface. This is used to get the + * pointer to ethernet L2 context + * + * @return Network interface related to this tag or NULL if no such interface + * exists. + */ +#if defined(CONFIG_NET_VLAN) +struct net_if *net_eth_get_vlan_main(struct net_if *iface); +#else +static inline +struct net_if *net_eth_get_vlan_main(struct net_if *iface) +{ + ARG_UNUSED(iface); + return NULL; } #endif /** - * @brief Check if VLAN is enabled for a specific network interface. + * @brief Check if there are any VLAN interfaces enabled to this specific + * Ethernet network interface. + * + * Note that the iface must be the actual Ethernet interface and not the + * virtual VLAN interface. * * @param ctx Ethernet context - * @param iface Network interface + * @param iface Ethernet network interface * - * @return True if VLAN is enabled for this network interface, false if not. + * @return True if there are enabled VLANs for this network interface, + * false if not. */ #if defined(CONFIG_NET_VLAN) bool net_eth_is_vlan_enabled(struct ethernet_context *ctx, @@ -914,6 +934,9 @@ bool net_eth_is_vlan_enabled(struct ethernet_context *ctx, static inline bool net_eth_is_vlan_enabled(struct ethernet_context *ctx, struct net_if *iface) { + ARG_UNUSED(ctx); + ARG_UNUSED(iface); + return false; } #endif @@ -930,26 +953,13 @@ bool net_eth_get_vlan_status(struct net_if *iface); #else static inline bool net_eth_get_vlan_status(struct net_if *iface) { + ARG_UNUSED(iface); + return false; } #endif #if !defined(CONFIG_ETH_DRIVER_RAW_MODE) -#if defined(CONFIG_NET_VLAN) - -#define Z_ETH_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, instance, \ - init_fn, pm, data, config, prio, \ - api, mtu) \ - Z_DEVICE_STATE_DEFINE(dev_id); \ - Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, pm, data, \ - config, POST_KERNEL, prio, api, \ - &Z_DEVICE_STATE_NAME(dev_id)); \ - NET_L2_DATA_INIT(dev_id, instance, \ - NET_L2_GET_CTX_TYPE(ETHERNET_L2)); \ - NET_IF_INIT(dev_id, instance, ETHERNET_L2, mtu, \ - NET_VLAN_MAX_COUNT) - -#else /* CONFIG_NET_VLAN */ #define Z_ETH_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, instance, \ init_fn, pm, data, config, prio, \ @@ -958,7 +968,6 @@ static inline bool net_eth_get_vlan_status(struct net_if *iface) init_fn, pm, data, config, prio, \ api, ETHERNET_L2, \ NET_L2_GET_CTX_TYPE(ETHERNET_L2), mtu) -#endif /* CONFIG_NET_VLAN */ #else /* CONFIG_ETH_DRIVER_RAW_MODE */ @@ -969,6 +978,7 @@ static inline bool net_eth_get_vlan_status(struct net_if *iface) Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, pm, data, \ config, POST_KERNEL, prio, api, \ &Z_DEVICE_STATE_NAME(dev_id)); + #endif /* CONFIG_ETH_DRIVER_RAW_MODE */ #define Z_ETH_NET_DEVICE_INIT(node_id, dev_id, name, init_fn, pm, data, \ diff --git a/include/zephyr/net/virtual.h b/include/zephyr/net/virtual.h index cbcf0dbe7d0..71fbd28c797 100644 --- a/include/zephyr/net/virtual.h +++ b/include/zephyr/net/virtual.h @@ -38,6 +38,9 @@ enum virtual_interface_caps { /** IPIP tunnel */ VIRTUAL_INTERFACE_IPIP = BIT(1), + /** Virtual LAN interface (VLAN) */ + VIRTUAL_INTERFACE_VLAN = BIT(2), + /** @cond INTERNAL_HIDDEN */ /* Marker for capabilities - must be at the end of the enum. * It is here because the capability list cannot be empty. diff --git a/subsys/net/l2/ethernet/CMakeLists.txt b/subsys/net/l2/ethernet/CMakeLists.txt index aa23df860f6..2330d18dfd3 100644 --- a/subsys/net/l2/ethernet/CMakeLists.txt +++ b/subsys/net/l2/ethernet/CMakeLists.txt @@ -17,6 +17,7 @@ zephyr_library_sources_ifdef(CONFIG_NET_L2_ETHERNET_MGMT ethernet_mgmt.c) if(CONFIG_NET_NATIVE) zephyr_library_sources_ifdef(CONFIG_NET_ARP arp.c) +zephyr_library_sources_ifdef(CONFIG_NET_VLAN vlan.c) zephyr_library_sources_ifdef(CONFIG_NET_STATISTICS_ETHERNET ethernet_stats.c) zephyr_library_sources_ifdef(CONFIG_NET_ETHERNET_BRIDGE bridge.c) zephyr_library_sources_ifdef(CONFIG_NET_ETHERNET_BRIDGE_SHELL bridge_shell.c) diff --git a/subsys/net/l2/ethernet/Kconfig b/subsys/net/l2/ethernet/Kconfig index 8f3afa553c0..17588b17fd1 100644 --- a/subsys/net/l2/ethernet/Kconfig +++ b/subsys/net/l2/ethernet/Kconfig @@ -25,7 +25,8 @@ config NET_L2_ETHERNET_MGMT configure at run-time Ethernet drivers and L2 settings. config NET_VLAN - bool "Virtual lan support" + bool "Virtual LAN support" + select NET_L2_VIRTUAL help Enables virtual lan (VLAN) support for Ethernet. @@ -37,6 +38,13 @@ config NET_VLAN_COUNT help How many VLAN tags can be configured. +config NET_VLAN_TXRX_DEBUG + bool "Debug received and sent packets in VLAN" + depends on NET_L2_ETHERNET_LOG_LEVEL_DBG && NET_VLAN + help + Enables printing of received and sent network packets. + This can produce lot of output so it is disabled by default. + config NET_ARP bool "ARP" default y diff --git a/subsys/net/l2/ethernet/arp.c b/subsys/net/l2/ethernet/arp.c index 27e27b50f25..fbedbaf1df9 100644 --- a/subsys/net/l2/ethernet/arp.c +++ b/subsys/net/l2/ethernet/arp.c @@ -266,9 +266,11 @@ static inline struct net_pkt *arp_prepare(struct net_if *iface, if (IS_ENABLED(CONFIG_NET_CAPTURE) && pending) { net_pkt_set_captured(pkt, net_pkt_is_captured(pending)); } - } - net_pkt_set_vlan_tag(pkt, net_eth_get_vlan_tag(iface)); + if (IS_ENABLED(CONFIG_NET_VLAN) && pending) { + net_pkt_set_vlan_tag(pkt, net_pkt_vlan_tag(pending)); + } + } net_buf_add(pkt->buffer, sizeof(struct net_arp_hdr)); @@ -570,7 +572,9 @@ static inline struct net_pkt *arp_prepare_reply(struct net_if *iface, hdr = NET_ARP_HDR(pkt); query = NET_ARP_HDR(req); - net_pkt_set_vlan_tag(pkt, net_pkt_vlan_tag(req)); + if (IS_ENABLED(CONFIG_NET_VLAN)) { + net_pkt_set_vlan_tag(pkt, net_pkt_vlan_tag(req)); + } hdr->hwtype = htons(NET_ARP_HTYPE_ETH); hdr->protocol = htons(NET_ETH_PTYPE_IP); diff --git a/subsys/net/l2/ethernet/ethernet.c b/subsys/net/l2/ethernet/ethernet.c index 972ad0812cc..1f2ce0514e6 100644 --- a/subsys/net/l2/ethernet/ethernet.c +++ b/subsys/net/l2/ethernet/ethernet.c @@ -239,7 +239,8 @@ static enum net_verdict ethernet_recv(struct net_if *iface, uint8_t hdr_len = sizeof(struct net_eth_hdr); uint16_t type; struct net_linkaddr *lladdr; - sa_family_t family; + sa_family_t family = AF_UNSPEC; + bool is_vlan_pkt = false; /* This expects that the Ethernet header is in the first net_buf * fragment. This is a safe expectation here as it would not make @@ -265,15 +266,33 @@ static enum net_verdict ethernet_recv(struct net_if *iface, type = ntohs(hdr->type); - if (net_eth_is_vlan_enabled(ctx, iface) && - type == NET_ETH_PTYPE_VLAN && - !eth_is_vlan_tag_stripped(iface)) { - struct net_eth_vlan_hdr *hdr_vlan = - (struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt); - - net_pkt_set_vlan_tci(pkt, ntohs(hdr_vlan->vlan.tci)); - type = ntohs(hdr_vlan->type); - hdr_len = sizeof(struct net_eth_vlan_hdr); + if (IS_ENABLED(CONFIG_NET_VLAN) && type == NET_ETH_PTYPE_VLAN) { + if (net_eth_is_vlan_enabled(ctx, iface) && + !eth_is_vlan_tag_stripped(iface)) { + struct net_eth_vlan_hdr *hdr_vlan = + (struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt); + enum net_verdict verdict; + + net_pkt_set_vlan_tci(pkt, ntohs(hdr_vlan->vlan.tci)); + type = ntohs(hdr_vlan->type); + hdr_len = sizeof(struct net_eth_vlan_hdr); + is_vlan_pkt = true; + + net_pkt_set_iface(pkt, + net_eth_get_vlan_iface(iface, + net_pkt_vlan_tag(pkt))); + + /* We could call VLAN interface directly but then the + * interface statistics would not get updated so route + * the call via Virtual L2 layer. + */ + if (net_if_l2(net_pkt_iface(pkt))->recv != NULL) { + verdict = net_if_l2(net_pkt_iface(pkt))->recv(iface, pkt); + if (verdict == NET_DROP) { + goto drop; + } + } + } } switch (type) { @@ -326,20 +345,12 @@ static enum net_verdict ethernet_recv(struct net_if *iface, net_pkt_set_ll_proto_type(pkt, type); - if (net_eth_is_vlan_enabled(ctx, iface)) { - if (type == NET_ETH_PTYPE_VLAN || - (eth_is_vlan_tag_stripped(iface) && - net_pkt_vlan_tci(pkt))) { - print_vlan_ll_addrs(pkt, type, net_pkt_vlan_tci(pkt), - net_pkt_get_len(pkt), - net_pkt_lladdr_src(pkt), - net_pkt_lladdr_dst(pkt), - eth_is_vlan_tag_stripped(iface)); - } else { - print_ll_addrs(pkt, type, net_pkt_get_len(pkt), - net_pkt_lladdr_src(pkt), - net_pkt_lladdr_dst(pkt)); - } + if (is_vlan_pkt) { + print_vlan_ll_addrs(pkt, type, net_pkt_vlan_tci(pkt), + net_pkt_get_len(pkt), + net_pkt_lladdr_src(pkt), + net_pkt_lladdr_dst(pkt), + eth_is_vlan_tag_stripped(iface)); } else { print_ll_addrs(pkt, type, net_pkt_get_len(pkt), net_pkt_lladdr_src(pkt), @@ -426,6 +437,16 @@ static bool ethernet_fill_in_dst_on_ipv4_mcast(struct net_pkt *pkt, static struct net_pkt *ethernet_ll_prepare_on_ipv4(struct net_if *iface, struct net_pkt *pkt) { + struct ethernet_context *ctx = net_if_l2_data(iface); + + if (IS_ENABLED(CONFIG_NET_VLAN) && + net_pkt_vlan_tag(pkt) != NET_VLAN_TAG_UNSPEC && + net_eth_is_vlan_enabled(ctx, net_pkt_iface(pkt))) { + iface = net_eth_get_vlan_iface(iface, + net_pkt_vlan_tag(pkt)); + net_pkt_set_iface(pkt, iface); + } + if (ethernet_ipv4_dst_is_broadcast_or_mcast(pkt)) { return pkt; } @@ -478,79 +499,8 @@ static bool ethernet_fill_in_dst_on_ipv6_mcast(struct net_pkt *pkt, #define ethernet_fill_in_dst_on_ipv6_mcast(...) false #endif /* CONFIG_NET_IPV6 */ -#if defined(CONFIG_NET_VLAN) -static enum net_verdict set_vlan_tag(struct ethernet_context *ctx, - struct net_if *iface, - struct net_pkt *pkt) -{ - int i; - - if (net_pkt_vlan_tag(pkt) != NET_VLAN_TAG_UNSPEC) { - return NET_OK; - } - -#if defined(CONFIG_NET_IPV6) - if (net_pkt_family(pkt) == AF_INET6) { - struct net_if *target; - - if (net_if_ipv6_addr_lookup((struct in6_addr *)NET_IPV6_HDR(pkt)->src, - &target)) { - if (target != iface) { - NET_DBG("Iface %p should be %p", iface, - target); - - iface = target; - } - } - } -#endif - -#if defined(CONFIG_NET_IPV4) - if (net_pkt_family(pkt) == AF_INET) { - struct net_if *target; - - if (net_if_ipv4_addr_lookup((struct in_addr *)NET_IPV4_HDR(pkt)->src, - &target)) { - if (target != iface) { - NET_DBG("Iface %p should be %p", iface, - target); - iface = target; - } - } - } -#endif - - for (i = 0; i < CONFIG_NET_VLAN_COUNT; i++) { - if (ctx->vlan[i].tag == NET_VLAN_TAG_UNSPEC || - ctx->vlan[i].iface != iface) { - continue; - } - - /* Depending on source address, use the proper network - * interface when sending. - */ - net_pkt_set_vlan_tag(pkt, ctx->vlan[i].tag); - - return NET_OK; - } - - return NET_DROP; -} - -static void set_vlan_priority(struct ethernet_context *ctx, - struct net_pkt *pkt) -{ - uint8_t vlan_priority; - - vlan_priority = net_priority2vlan(net_pkt_priority(pkt)); - net_pkt_set_vlan_priority(pkt, vlan_priority); -} -#else -#define set_vlan_tag(...) NET_DROP -#define set_vlan_priority(...) -#endif /* CONFIG_NET_VLAN */ - static struct net_buf *ethernet_fill_header(struct ethernet_context *ctx, + struct net_if *iface, struct net_pkt *pkt, uint32_t ptype) { @@ -566,7 +516,8 @@ static struct net_buf *ethernet_fill_header(struct ethernet_context *ctx, } if (IS_ENABLED(CONFIG_NET_VLAN) && - net_eth_is_vlan_enabled(ctx, net_pkt_iface(pkt)) && + net_eth_is_vlan_enabled(ctx, iface) && + net_pkt_vlan_tag(pkt) != NET_VLAN_TAG_UNSPEC && (IS_ENABLED(CONFIG_NET_GPTP_VLAN) || ptype != htons(NET_ETH_PTYPE_PTP))) { struct net_eth_vlan_hdr *hdr_vlan; @@ -743,20 +694,11 @@ static int ethernet_send(struct net_if *iface, struct net_pkt *pkt) net_pkt_lladdr_dst(pkt)->len = sizeof(struct net_eth_addr); } - if (IS_ENABLED(CONFIG_NET_VLAN) && - net_eth_is_vlan_enabled(ctx, iface) && - (IS_ENABLED(CONFIG_NET_GPTP_VLAN) || ptype != htons(NET_ETH_PTYPE_PTP))) { - if (set_vlan_tag(ctx, iface, pkt) == NET_DROP) { - ret = -EINVAL; - goto arp_error; - } - - set_vlan_priority(ctx, pkt); - } - - /* Then set the ethernet header. + /* Then set the ethernet header. Note that the iface parameter tells + * where we are actually sending the packet. The interface in net_pkt + * is used to determine if the VLAN header is added to Ethernet frame. */ - if (!ethernet_fill_header(ctx, pkt, ptype)) { + if (!ethernet_fill_header(ctx, iface, pkt, ptype)) { ret = -ENOMEM; goto arp_error; } @@ -830,287 +772,6 @@ enum net_l2_flags ethernet_flags(struct net_if *iface) return ctx->ethernet_l2_flags; } -#if defined(CONFIG_NET_VLAN) -struct net_if *net_eth_get_vlan_iface(struct net_if *iface, uint16_t tag) -{ - struct ethernet_context *ctx = net_if_l2_data(iface); - struct net_if *first_non_vlan_iface = NULL; - int i; - - for (i = 0; i < CONFIG_NET_VLAN_COUNT; i++) { - if (ctx->vlan[i].tag == NET_VLAN_TAG_UNSPEC) { - if (!first_non_vlan_iface) { - first_non_vlan_iface = ctx->vlan[i].iface; - } - - continue; - } - - if (ctx->vlan[i].tag != tag) { - continue; - } - - NET_DBG("[%d] vlan tag %d -> iface %p", i, tag, - ctx->vlan[i].iface); - - return ctx->vlan[i].iface; - } - - return first_non_vlan_iface; -} - -static bool enable_vlan_iface(struct ethernet_context *ctx, - struct net_if *iface) -{ - int iface_idx = net_if_get_by_iface(iface); - - if (iface_idx < 0) { - return false; - } - - atomic_set_bit(ctx->interfaces, iface_idx); - - return true; -} - -static bool disable_vlan_iface(struct ethernet_context *ctx, - struct net_if *iface) -{ - int iface_idx = net_if_get_by_iface(iface); - - if (iface_idx < 0) { - return false; - } - - atomic_clear_bit(ctx->interfaces, iface_idx); - - return true; -} - -static bool is_vlan_enabled_for_iface(struct ethernet_context *ctx, - struct net_if *iface) -{ - int iface_idx = net_if_get_by_iface(iface); - - if (iface_idx < 0) { - return false; - } - - return !!atomic_test_bit(ctx->interfaces, iface_idx); -} - -bool net_eth_is_vlan_enabled(struct ethernet_context *ctx, - struct net_if *iface) -{ - if (ctx->vlan_enabled) { - if (ctx->vlan_enabled == NET_VLAN_MAX_COUNT) { - /* All network interface are using VLAN, no need - * to check further. - */ - return true; - } - - if (is_vlan_enabled_for_iface(ctx, iface)) { - return true; - } - } - - return false; -} - -uint16_t net_eth_get_vlan_tag(struct net_if *iface) -{ - struct ethernet_context *ctx = net_if_l2_data(iface); - int i; - - for (i = 0; i < CONFIG_NET_VLAN_COUNT; i++) { - if (ctx->vlan[i].iface == iface) { - return ctx->vlan[i].tag; - } - } - - return NET_VLAN_TAG_UNSPEC; -} - -bool net_eth_get_vlan_status(struct net_if *iface) -{ - struct ethernet_context *ctx = net_if_l2_data(iface); - - if (ctx->vlan_enabled && - net_eth_get_vlan_tag(iface) != NET_VLAN_TAG_UNSPEC) { - return true; - } - - return false; -} - -static struct ethernet_vlan *get_vlan(struct ethernet_context *ctx, - struct net_if *iface, - uint16_t vlan_tag) -{ - int i; - - for (i = 0; i < CONFIG_NET_VLAN_COUNT; i++) { - if (ctx->vlan[i].iface == iface && - ctx->vlan[i].tag == vlan_tag) { - return &ctx->vlan[i]; - } - } - - return NULL; -} - -static void setup_ipv6_link_local_addr(struct net_if *iface) -{ - struct net_linkaddr link_addr; - struct net_if_addr *ifaddr; - struct in6_addr addr; - uint32_t entropy; - uint8_t mac_addr[6]; - - entropy = sys_rand32_get(); - mac_addr[0] = entropy >> 0; - mac_addr[1] = entropy >> 8; - mac_addr[2] = entropy >> 16; - - entropy = sys_rand32_get(); - mac_addr[3] = entropy >> 0; - mac_addr[4] = entropy >> 8; - mac_addr[5] = entropy >> 16; - - mac_addr[0] |= 0x02; /* force LAA bit */ - - link_addr.len = sizeof(mac_addr); - link_addr.type = NET_LINK_ETHERNET; - link_addr.addr = mac_addr; - - net_ipv6_addr_create_iid(&addr, &link_addr); - - ifaddr = net_if_ipv6_addr_add(iface, &addr, NET_ADDR_AUTOCONF, 0); - if (!ifaddr) { - NET_DBG("Cannot add %s address to VLAN interface %p", - net_sprint_ipv6_addr(&addr), iface); - } -} - -int net_eth_vlan_enable(struct net_if *iface, uint16_t tag) -{ - struct ethernet_context *ctx = net_if_l2_data(iface); - const struct ethernet_api *eth = - net_if_get_device(iface)->api; - struct ethernet_vlan *vlan; - int i; - - if (!eth) { - return -ENOENT; - } - - if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { - return -EINVAL; - } - - if (!ctx->is_init) { - return -EPERM; - } - - if (tag >= NET_VLAN_TAG_UNSPEC) { - return -EBADF; - } - - vlan = get_vlan(ctx, iface, tag); - if (vlan) { - return -EALREADY; - } - - for (i = 0; i < CONFIG_NET_VLAN_COUNT; i++) { - if (ctx->vlan[i].iface != iface) { - continue; - } - - if (ctx->vlan[i].tag != NET_VLAN_TAG_UNSPEC) { - continue; - } - - NET_DBG("[%d] Adding vlan tag %d to iface %p", i, tag, iface); - - ctx->vlan[i].tag = tag; - - /* Add a link local IPv6 address to VLAN interface here. - * Each network interface needs LL address, but as there is - * only one link (MAC) address defined for all the master and - * slave interfaces, the VLAN interface might be left without - * a LL address. In order to solve this issue, we create a - * random LL address and set it to the VLAN network interface. - */ - if (IS_ENABLED(CONFIG_NET_IPV6)) { - setup_ipv6_link_local_addr(iface); - } - - enable_vlan_iface(ctx, iface); - - if (eth->vlan_setup) { - eth->vlan_setup(net_if_get_device(iface), - iface, tag, true); - } - - ctx->vlan_enabled++; - if (ctx->vlan_enabled > NET_VLAN_MAX_COUNT) { - ctx->vlan_enabled = NET_VLAN_MAX_COUNT; - } - - ethernet_mgmt_raise_vlan_enabled_event(iface, tag); - - return 0; - } - - return -ENOSPC; -} - -int net_eth_vlan_disable(struct net_if *iface, uint16_t tag) -{ - struct ethernet_context *ctx = net_if_l2_data(iface); - const struct ethernet_api *eth = - net_if_get_device(iface)->api; - struct ethernet_vlan *vlan; - - if (!eth) { - return -ENOENT; - } - - if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { - return -EINVAL; - } - - if (tag == NET_VLAN_TAG_UNSPEC) { - return -EBADF; - } - - vlan = get_vlan(ctx, iface, tag); - if (!vlan) { - return -ESRCH; - } - - NET_DBG("Removing vlan tag %d from iface %p", vlan->tag, vlan->iface); - - vlan->tag = NET_VLAN_TAG_UNSPEC; - - disable_vlan_iface(ctx, iface); - - if (eth->vlan_setup) { - eth->vlan_setup(net_if_get_device(iface), iface, tag, false); - } - - ethernet_mgmt_raise_vlan_disabled_event(iface, tag); - - ctx->vlan_enabled--; - if (ctx->vlan_enabled < 0) { - ctx->vlan_enabled = 0; - } - - return 0; -} -#endif /* CONFIG_NET_VLAN */ - NET_L2_INIT(ETHERNET_L2, ethernet_recv, ethernet_send, ethernet_enable, ethernet_flags); @@ -1293,10 +954,6 @@ void ethernet_init(struct net_if *iface) { struct ethernet_context *ctx = net_if_l2_data(iface); -#if defined(CONFIG_NET_VLAN) - int i; -#endif - NET_DBG("Initializing Ethernet L2 %p for iface %p", ctx, iface); ctx->ethernet_l2_flags = NET_L2_MULTICAST; @@ -1313,26 +970,6 @@ void ethernet_init(struct net_if *iface) } #endif -#if defined(CONFIG_NET_VLAN) - if (!(net_eth_get_hw_capabilities(iface) & ETHERNET_HW_VLAN)) { - return; - } - - for (i = 0; i < CONFIG_NET_VLAN_COUNT; i++) { - if (!ctx->vlan[i].iface) { - NET_DBG("[%d] alloc ctx %p iface %p", i, ctx, iface); - ctx->vlan[i].tag = NET_VLAN_TAG_UNSPEC; - ctx->vlan[i].iface = iface; - - if (!ctx->is_init) { - atomic_clear(ctx->interfaces); - } - - break; - } - } -#endif - net_arp_init(); ctx->is_init = true; diff --git a/subsys/net/l2/ethernet/vlan.c b/subsys/net/l2/ethernet/vlan.c new file mode 100644 index 00000000000..844a6bbd2ef --- /dev/null +++ b/subsys/net/l2/ethernet/vlan.c @@ -0,0 +1,640 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +LOG_MODULE_REGISTER(net_ethernet_vlan, CONFIG_NET_L2_ETHERNET_LOG_LEVEL); + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "net_private.h" + +#if defined(CONFIG_NET_VLAN_TXRX_DEBUG) +#define DEBUG_TX 1 +#define DEBUG_RX 1 +#else +#define DEBUG_TX 0 +#define DEBUG_RX 0 +#endif + +#define MAX_VLAN_NAME_LEN MIN(sizeof("VLAN-<#####>"), \ + CONFIG_NET_INTERFACE_NAME_LEN) +#define MAX_VIRT_NAME_LEN MIN(sizeof(""), \ + CONFIG_NET_L2_VIRTUAL_MAX_NAME_LEN) + +static void vlan_iface_init(struct net_if *iface); +static int vlan_interface_attach(struct net_if *vlan_iface, + struct net_if *iface); +static enum net_verdict vlan_interface_recv(struct net_if *iface, + struct net_pkt *pkt); +static int vlan_interface_send(struct net_if *iface, struct net_pkt *pkt); +static int vlan_interface_stop(const struct device *dev); +static enum virtual_interface_caps vlan_get_capabilities(struct net_if *iface); +static int vlan_interface_start(const struct device *dev); +static int virt_dev_init(const struct device *dev); + +static K_MUTEX_DEFINE(lock); + +struct vlan_context { + struct net_if *iface; + struct net_if *attached_to; + uint16_t tag; + bool status : 1; /* Is the interface enabled or not */ + bool is_used : 1; /* Is there active config on this context */ + bool init_done : 1; /* Is interface init called for this context */ +}; + +static const struct virtual_interface_api vlan_iface_api = { + .iface_api.init = vlan_iface_init, + + .get_capabilities = vlan_get_capabilities, + .start = vlan_interface_start, + .stop = vlan_interface_stop, + .send = vlan_interface_send, + .recv = vlan_interface_recv, + .attach = vlan_interface_attach, +}; + +#define ETH_DEFINE_VLAN(x, _) \ + static struct vlan_context vlan_context_data_##x = { \ + .tag = NET_VLAN_TAG_UNSPEC, \ + }; \ + NET_VIRTUAL_INTERFACE_INIT_INSTANCE(vlan_##x, \ + "VLAN_" #x, \ + x, \ + virt_dev_init, \ + NULL, \ + &vlan_context_data_##x, \ + NULL, /* config */ \ + CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \ + &vlan_iface_api, \ + NET_ETH_MTU) + +LISTIFY(CONFIG_NET_VLAN_COUNT, ETH_DEFINE_VLAN, (;), _); + +#define INIT_VLAN_CONTEXT_PTR(x, _) \ + [x] = &vlan_context_data_##x \ + +static struct vlan_context *vlan_ctx[] = { + LISTIFY(CONFIG_NET_VLAN_COUNT, INIT_VLAN_CONTEXT_PTR, (,), _) +}; + +#define INIT_VLAN_CONTEXT_IFACE(x, _) \ + vlan_context_data_##x.iface = NET_IF_GET(vlan_##x, x) + +static void init_context_iface(void) +{ + static bool init_done; + + if (init_done) { + return; + } + + init_done = true; + + LISTIFY(CONFIG_NET_VLAN_COUNT, INIT_VLAN_CONTEXT_IFACE, (;), _); +} + +static int virt_dev_init(const struct device *dev) +{ + ARG_UNUSED(dev); + + init_context_iface(); + + return 0; +} + +static struct vlan_context *get_vlan_ctx(struct net_if *main_iface, + uint16_t vlan_tag, + bool any_tag) +{ + struct virtual_interface_context *vctx, *tmp; + sys_slist_t *interfaces; + struct vlan_context *ctx; + + interfaces = &main_iface->config.virtual_interfaces; + + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(interfaces, vctx, tmp, node) { + enum virtual_interface_caps caps; + + if (vctx->virtual_iface == NULL) { + continue; + } + + caps = net_virtual_get_iface_capabilities(vctx->virtual_iface); + if (!(caps & VIRTUAL_INTERFACE_VLAN)) { + continue; + } + + ctx = net_if_get_device(vctx->virtual_iface)->data; + NET_ASSERT(vctx != NULL); + + if (any_tag) { + if (ctx->tag != NET_VLAN_TAG_UNSPEC) { + return ctx; + } + } else { + if ((vlan_tag == NET_VLAN_TAG_UNSPEC || + vlan_tag == ctx->tag)) { + return ctx; + } + } + } + + return NULL; +} + +static struct vlan_context *get_vlan(struct net_if *iface, + uint16_t vlan_tag) +{ + struct vlan_context *ctx = NULL; + + k_mutex_lock(&lock, K_FOREVER); + + /* If the interface is NULL, then get the VLAN that has the tag */ + if (iface == NULL) { + ARRAY_FOR_EACH(vlan_ctx, i) { + if (vlan_ctx[i] == NULL || !vlan_ctx[i]->is_used) { + continue; + } + + if (vlan_tag == vlan_ctx[i]->tag) { + ctx = vlan_ctx[i]; + break; + } + } + + goto out; + } + + /* If the interface is the main Ethernet one, then we only need + * to go through its attached virtual interfaces. + */ + if (net_if_l2(iface) == &NET_L2_GET_NAME(ETHERNET)) { + + ctx = get_vlan_ctx(iface, vlan_tag, false); + goto out; + + } + + if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) { + goto out; + } + + /* If the interface is virtual, then it should be be the VLAN one. + * Just get the Ethernet interface it points to to get the context. + */ + ctx = get_vlan_ctx(net_virtual_get_iface(iface), vlan_tag, false); + +out: + k_mutex_unlock(&lock); + + return ctx; +} + +static void set_priority(struct net_pkt *pkt) +{ + uint8_t vlan_priority; + + vlan_priority = net_priority2vlan(net_pkt_priority(pkt)); + net_pkt_set_vlan_priority(pkt, vlan_priority); +} + +struct net_if *net_eth_get_vlan_iface(struct net_if *iface, uint16_t tag) +{ + struct vlan_context *ctx; + + ctx = get_vlan(iface, tag); + if (ctx == NULL) { + return NULL; + } + + return ctx->iface; +} + +struct net_if *net_eth_get_vlan_main(struct net_if *iface) +{ + struct vlan_context *ctx; + + ctx = get_vlan(iface, NET_VLAN_TAG_UNSPEC); + if (ctx == NULL) { + return NULL; + } + + return ctx->attached_to; +} + +static bool enable_vlan_iface(struct vlan_context *ctx, + struct net_if *iface) +{ + int iface_idx = net_if_get_by_iface(iface); + char name[MAX(MAX_VLAN_NAME_LEN, MAX_VIRT_NAME_LEN)]; + int ret; + + if (iface_idx < 0) { + return false; + } + + ret = net_virtual_interface_attach(ctx->iface, iface); + if (ret < 0) { + NET_DBG("Cannot attach iface %d to %d", + net_if_get_by_iface(ctx->iface), + net_if_get_by_iface(ctx->attached_to)); + return false; + } + + ctx->is_used = true; + + snprintk(name, sizeof(name), "VLAN-%d", ctx->tag); + net_if_set_name(ctx->iface, name); + + snprintk(name, sizeof(name), "VLAN to %d", + net_if_get_by_iface(ctx->attached_to)); + net_virtual_set_name(ctx->iface, name); + + return true; +} + +static bool disable_vlan_iface(struct vlan_context *ctx, + struct net_if *iface) +{ + int iface_idx = net_if_get_by_iface(iface); + char name[MAX(MAX_VLAN_NAME_LEN, MAX_VIRT_NAME_LEN)]; + + if (iface_idx < 0) { + return false; + } + + (void)net_virtual_interface_attach(iface, NULL); + ctx->is_used = false; + + snprintk(name, sizeof(name), "VLAN-"); + net_if_set_name(iface, name); + + snprintk(name, sizeof(name), ""); + net_virtual_set_name(iface, name); + + return true; +} + +static bool is_vlan_enabled_for_iface(struct net_if *iface) +{ + int iface_idx = net_if_get_by_iface(iface); + struct vlan_context *ctx; + bool ret = false; + + if (iface_idx < 0) { + return false; + } + + k_mutex_lock(&lock, K_FOREVER); + + ctx = get_vlan_ctx(iface, NET_VLAN_TAG_UNSPEC, true); + ret = (ctx != NULL); + + k_mutex_unlock(&lock); + + return ret; +} + +bool net_eth_is_vlan_enabled(struct ethernet_context *ctx, + struct net_if *iface) +{ + ARG_UNUSED(ctx); + + return is_vlan_enabled_for_iface(iface); +} + +uint16_t net_eth_get_vlan_tag(struct net_if *iface) +{ + uint16_t tag = NET_VLAN_TAG_UNSPEC; + struct vlan_context *ctx; + + k_mutex_lock(&lock, K_FOREVER); + + ctx = get_vlan_ctx(iface, tag, true); + if (ctx != NULL) { + /* The Ethernet interface does not have a tag so if user + * tried to use the main interface, then do not return + * the tag. + */ + if (ctx->attached_to != iface) { + tag = ctx->tag; + } + } + + k_mutex_unlock(&lock); + + return tag; +} + +bool net_eth_get_vlan_status(struct net_if *iface) +{ + bool status = false; + struct vlan_context *ctx; + + k_mutex_lock(&lock, K_FOREVER); + + ctx = get_vlan_ctx(iface, NET_VLAN_TAG_UNSPEC, true); + if (ctx != NULL) { + status = ctx->status; + } + + k_mutex_unlock(&lock); + + return status; +} + +static void setup_link_address(struct vlan_context *ctx) +{ + struct net_linkaddr *ll_addr; + + ll_addr = net_if_get_link_addr(ctx->attached_to); + + (void)net_if_set_link_addr(ctx->iface, + ll_addr->addr, + ll_addr->len, + ll_addr->type); +} + +int net_eth_vlan_enable(struct net_if *iface, uint16_t tag) +{ + struct ethernet_context *ctx = net_if_l2_data(iface); + const struct ethernet_api *eth = net_if_get_device(iface)->api; + struct vlan_context *vlan; + int ret; + + if (!eth) { + return -ENOENT; + } + + if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { + return -EINVAL; + } + + if (!(net_eth_get_hw_capabilities(iface) & ETHERNET_HW_VLAN)) { + NET_DBG("Interface %d does not support VLAN", + net_if_get_by_iface(iface)); + return -ENOTSUP; + } + + if (!ctx->is_init) { + return -EPERM; + } + + if (tag >= NET_VLAN_TAG_UNSPEC) { + return -EBADF; + } + + vlan = get_vlan(iface, tag); + if (vlan != NULL) { + return -EALREADY; + } + + /* This will make sure that the tag is not yet in use by some + * other interface. + */ + vlan = get_vlan(NULL, tag); + if (vlan != NULL) { + return -EALREADY; + } + + ret = -ENOSPC; + + k_mutex_lock(&lock, K_FOREVER); + + ARRAY_FOR_EACH(vlan_ctx, i) { + if (vlan_ctx[i] == NULL || vlan_ctx[i]->is_used) { + continue; + } + + vlan = vlan_ctx[i]; + vlan->tag = tag; + + if (!enable_vlan_iface(vlan, iface)) { + continue; + } + + NET_DBG("[%d] Adding vlan tag %d to iface %d (%p) attached to %d (%p)", + i, vlan->tag, net_if_get_by_iface(vlan->iface), vlan->iface, + net_if_get_by_iface(iface), iface); + + /* Use MAC address of the attached Ethernet interface so that + * packet reception works without any tweaks. + */ + setup_link_address(vlan); + + if (eth->vlan_setup) { + eth->vlan_setup(net_if_get_device(iface), + iface, vlan->tag, true); + } + + ethernet_mgmt_raise_vlan_enabled_event(vlan->iface, vlan->tag); + + ret = 0; + break; + } + + k_mutex_unlock(&lock); + + return ret; +} + +int net_eth_vlan_disable(struct net_if *iface, uint16_t tag) +{ + const struct ethernet_api *eth; + struct vlan_context *vlan; + + if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET) && + net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) { + return -EINVAL; + } + + if (tag == NET_VLAN_TAG_UNSPEC) { + return -EBADF; + } + + vlan = get_vlan(iface, tag); + if (!vlan) { + return -ESRCH; + } + + eth = net_if_get_device(vlan->attached_to)->api; + + k_mutex_lock(&lock, K_FOREVER); + + NET_DBG("Removing vlan tag %d from VLAN iface %d (%p) attached to %d (%p)", + vlan->tag, net_if_get_by_iface(vlan->iface), vlan->iface, + net_if_get_by_iface(vlan->attached_to), vlan->attached_to); + + vlan->tag = NET_VLAN_TAG_UNSPEC; + + if (eth->vlan_setup) { + eth->vlan_setup(net_if_get_device(vlan->attached_to), + vlan->attached_to, tag, false); + } + + ethernet_mgmt_raise_vlan_disabled_event(vlan->iface, tag); + + (void)disable_vlan_iface(vlan, vlan->iface); + + k_mutex_unlock(&lock); + + return 0; +} + +static enum virtual_interface_caps vlan_get_capabilities(struct net_if *iface) +{ + ARG_UNUSED(iface); + + return VIRTUAL_INTERFACE_VLAN; +} + +static int vlan_interface_start(const struct device *dev) +{ + struct vlan_context *ctx = dev->data; + + if (!ctx->is_used) { + NET_DBG("VLAN interface %d not configured yet.", + net_if_get_by_iface(ctx->iface)); + return -ENOENT; + } + + if (ctx->status) { + return -EALREADY; + } + + ctx->status = true; + + NET_DBG("Starting iface %d", net_if_get_by_iface(ctx->iface)); + + /* You can implement here any special action that is needed + * when the network interface is coming up. + */ + + return 0; +} + +static int vlan_interface_stop(const struct device *dev) +{ + struct vlan_context *ctx = dev->data; + + if (!ctx->is_used) { + NET_DBG("VLAN interface %d not configured yet.", + net_if_get_by_iface(ctx->iface)); + return -ENOENT; + } + + if (!ctx->status) { + return -EALREADY; + } + + ctx->status = false; + + NET_DBG("Stopping iface %d", net_if_get_by_iface(ctx->iface)); + + /* You can implement here any special action that is needed + * when the network interface is going down. + */ + + return 0; +} + +static int vlan_interface_send(struct net_if *iface, struct net_pkt *pkt) +{ + struct vlan_context *ctx = net_if_get_device(iface)->data; + + if (ctx->attached_to == NULL) { + return -ENOENT; + } + + net_pkt_set_vlan_tag(pkt, ctx->tag); + net_pkt_set_iface(pkt, ctx->attached_to); + set_priority(pkt); + + if (DEBUG_TX) { + char str[sizeof("TX iface xx (tag xxxx)")]; + + snprintk(str, sizeof(str), "TX iface %d (tag %d)", + net_if_get_by_iface(net_pkt_iface(pkt)), + ctx->tag); + + net_pkt_hexdump(pkt, str); + } + + return net_send_data(pkt); +} + +static enum net_verdict vlan_interface_recv(struct net_if *iface, + struct net_pkt *pkt) +{ + struct vlan_context *ctx = net_if_get_device(iface)->data; + + if (net_pkt_vlan_tag(pkt) != ctx->tag) { + return NET_CONTINUE; + } + + if (DEBUG_RX) { + char str[sizeof("RX iface xx (tag xxxx)")]; + + snprintk(str, sizeof(str), "RX iface %d (tag %d)", + net_pkt_vlan_tag(pkt), + net_if_get_by_iface(iface)); + + net_pkt_hexdump(pkt, str); + } + + return NET_OK; +} + +static int vlan_interface_attach(struct net_if *vlan_iface, + struct net_if *iface) +{ + struct vlan_context *ctx = net_if_get_device(vlan_iface)->data; + + if (iface == NULL) { + NET_DBG("VLAN interface %d (%p) detached from %d (%p)", + net_if_get_by_iface(vlan_iface), vlan_iface, + net_if_get_by_iface(ctx->attached_to), ctx->attached_to); + } else { + NET_DBG("VLAN interface %d (%p) attached to %d (%p)", + net_if_get_by_iface(vlan_iface), vlan_iface, + net_if_get_by_iface(iface), iface); + } + + ctx->attached_to = iface; + + return 0; +} + +static void vlan_iface_init(struct net_if *iface) +{ + struct vlan_context *ctx = net_if_get_device(iface)->data; + char name[MAX(MAX_VLAN_NAME_LEN, MAX_VIRT_NAME_LEN)]; + + if (ctx->init_done) { + return; + } + + ctx->iface = iface; + net_if_flag_set(iface, NET_IF_NO_AUTO_START); + + snprintk(name, sizeof(name), "VLAN-"); + net_if_set_name(iface, name); + + snprintk(name, sizeof(name), "not attached"); + net_virtual_set_name(iface, name); + + (void)net_virtual_set_flags(ctx->iface, NET_L2_MULTICAST); + + ctx->init_done = true; +} From c28ca1ce1fa1f00ce0626f6c6b1eddc0e5f11371 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 15:29:52 +0200 Subject: [PATCH 1558/2402] tests: net: vlan: Update because of VLAN changes Update the tests because of the VLAN overhaul. Signed-off-by: Jukka Rissanen --- tests/net/vlan/prj.conf | 9 +- tests/net/vlan/src/main.c | 395 +++++++++++++++++++++----------------- 2 files changed, 225 insertions(+), 179 deletions(-) diff --git a/tests/net/vlan/prj.conf b/tests/net/vlan/prj.conf index 48fa390cded..a36eb23780c 100644 --- a/tests/net/vlan/prj.conf +++ b/tests/net/vlan/prj.conf @@ -16,16 +16,17 @@ CONFIG_NET_PKT_TX_COUNT=15 CONFIG_NET_PKT_RX_COUNT=15 CONFIG_NET_BUF_RX_COUNT=15 CONFIG_NET_BUF_TX_COUNT=15 -CONFIG_NET_IF_MAX_IPV6_COUNT=6 +CONFIG_NET_IF_MAX_IPV6_COUNT=8 CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=6 CONFIG_NET_IPV6_ND=n CONFIG_NET_VLAN=y CONFIG_NET_VLAN_COUNT=4 CONFIG_NET_CONTEXT_PRIORITY=y +CONFIG_NET_SOCKETS=y CONFIG_ZTEST=y CONFIG_NET_CONFIG_SETTINGS=n CONFIG_NET_SHELL=n -# Disable internal ethernet drivers as the test is self contained -# and does not need the on board driver to function. -CONFIG_ETH_DRIVER=n +# The address check must be disabled so that packet +# is properly routed via Ethernet L2. +CONFIG_NET_IP_ADDR_CHECK=n diff --git a/tests/net/vlan/src/main.c b/tests/net/vlan/src/main.c index cfcab203193..5d53bfd4779 100644 --- a/tests/net/vlan/src/main.c +++ b/tests/net/vlan/src/main.c @@ -22,6 +22,7 @@ LOG_MODULE_REGISTER(net_test, NET_LOG_LEVEL); #include +#include #include #include #include @@ -30,6 +31,7 @@ LOG_MODULE_REGISTER(net_test, NET_LOG_LEVEL); #include #include "ipv6.h" +#include "../../socket/socket_helpers.h" #define NET_LOG_ENABLED 1 #include "net_private.h" @@ -40,7 +42,9 @@ LOG_MODULE_REGISTER(net_test, NET_LOG_LEVEL); #define DBG(fmt, ...) #endif -#define TEST_PORT 9999 +#define ANY_PORT 0 +#define SERVER_PORT 4242 +#define CLIENT_PORT 9898 #define VLAN_TAG_1 100 #define VLAN_TAG_2 200 @@ -48,7 +52,10 @@ LOG_MODULE_REGISTER(net_test, NET_LOG_LEVEL); #define VLAN_TAG_4 400 #define VLAN_TAG_5 500 -static char *test_data = "Test data to be sent"; +#define NET_ETH_MAX_COUNT 2 + +#define MY_IPV6_ADDR "2001:db8:200::2" +#define MY_IPV6_ADDR_SRV "2001:db8:200::1" /* Interface 1 addresses */ static struct in6_addr my_addr1 = { { { 0x20, 0x01, 0x0d, 0xb8, 1, 0, 0, 0, @@ -58,32 +65,39 @@ static struct in6_addr my_addr1 = { { { 0x20, 0x01, 0x0d, 0xb8, 1, 0, 0, 0, static struct in6_addr my_addr2 = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x1 } } }; -/* Interface 3 addresses */ +/* VLAN Interface 3 addresses */ static struct in6_addr my_addr3 = { { { 0x20, 0x01, 0x0d, 0xb8, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x1 } } }; -/* Destination address for test packets */ -static struct in6_addr dst_addr = { { { 0x20, 0x01, 0x0d, 0xb8, 9, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0x1 } } }; - /* Extra address is assigned to ll_addr */ static struct in6_addr ll_addr = { { { 0xfe, 0x80, 0x43, 0xb8, 0, 0, 0, 0, 0, 0, 0, 0xf2, 0xaa, 0x29, 0x02, 0x04 } } }; /* Keep track of all ethernet interfaces */ -static struct net_if *eth_interfaces[NET_VLAN_MAX_COUNT + 1]; +static struct net_if *eth_interfaces[NET_ETH_MAX_COUNT]; +static struct net_if *vlan_interfaces[NET_VLAN_MAX_COUNT]; static struct net_if *dummy_interfaces[2]; -static struct net_if *extra_eth; - -static struct net_context *udp_v6_ctx; static bool test_failed; static bool test_started; static K_SEM_DEFINE(wait_data, 0, UINT_MAX); -#define WAIT_TIME K_SECONDS(1) +#define BUF_AND_SIZE(buf) buf, sizeof(buf) - 1 +#define STRLEN(buf) (sizeof(buf) - 1) + +#define TEST_STR_SMALL "test" + +/* More than 256 bytes, to use >1 net_buf. */ +#define TEST_STR2 \ + "The Zephyr Project, a Linux Foundation hosted Collaboration " \ + "Project, is an open source collaborative effort uniting leaders " \ + "from across the industry to build a best-in-breed small, scalable, " \ + "real-time operating system (RTOS) optimized for resource-" \ + "constrained devices, across multiple architectures." + +#define WAIT_TIME K_MSEC(500) struct eth_context { struct net_if *iface; @@ -109,6 +123,7 @@ static void eth_vlan_iface_init(struct net_if *iface) static int eth_tx(const struct device *dev, struct net_pkt *pkt) { struct eth_context *context = dev->data; + int ret; zassert_equal_ptr(ð_vlan_context, context, "Context pointers do not match (%p vs %p)", @@ -125,7 +140,7 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt) zassert_equal(context->expecting_tag, net_pkt_vlan_tag(pkt), - "Invalid VLAN tag (%d vs %d) in TX pkt\n", + "Invalid VLAN tag (%d vs %d) in TX pkt", net_pkt_vlan_tag(pkt), context->expecting_tag); @@ -133,10 +148,15 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt) net_eth_vlan_get_vid(ntohs(hdr->vlan.tci)), "Invalid VLAN tag in ethernet header"); + k_sleep(K_MSEC(10)); k_sem_give(&wait_data); } - return 0; + ret = net_recv_data(net_pkt_iface(pkt), + net_pkt_clone(pkt, K_NO_WAIT)); + zassert_false(ret < 0, "Cannot receive data (%d)", ret); + + return ret; } static enum ethernet_hw_caps eth_capabilities(const struct device *dev) @@ -185,14 +205,9 @@ static int eth_init(const struct device *dev) return 0; } -/* Create one ethernet interface that does not have VLAN support. This - * is quite unlikely that this would be done in real life but for testing - * purposes create it here. - */ -NET_DEVICE_INIT(eth_test, "eth_test", eth_init, NULL, - ð_vlan_context, NULL, CONFIG_ETH_INIT_PRIORITY, - &api_funcs, ETHERNET_L2, NET_L2_GET_CTX_TYPE(ETHERNET_L2), - NET_ETH_MTU); +ETH_NET_DEVICE_INIT(eth_test, "eth_test", eth_init, NULL, + ð_vlan_context, NULL, CONFIG_ETH_INIT_PRIORITY, + &api_funcs, NET_ETH_MTU); struct net_if_test { uint8_t idx; /* not used for anything, just a dummy value */ @@ -204,15 +219,13 @@ static uint8_t *net_iface_get_mac(const struct device *dev) { struct net_if_test *data = dev->data; - if (data->mac_addr[2] == 0x00) { - /* 00-00-5E-00-53-xx Documentation RFC 7042 */ - data->mac_addr[0] = 0x00; - data->mac_addr[1] = 0x00; - data->mac_addr[2] = 0x5E; - data->mac_addr[3] = 0x00; - data->mac_addr[4] = 0x53; - data->mac_addr[5] = sys_rand32_get(); - } + /* 00-00-5E-00-53-xx Documentation RFC 7042 */ + data->mac_addr[0] = 0x00; + data->mac_addr[1] = 0x00; + data->mac_addr[2] = 0x5E; + data->mac_addr[3] = 0x00; + data->mac_addr[4] = 0x53; + data->mac_addr[5] = sys_rand32_get(); data->ll_addr.addr = data->mac_addr; data->ll_addr.len = 6U; @@ -272,6 +285,7 @@ NET_DEVICE_INIT_INSTANCE(net_iface2_test, struct user_data { int eth_if_count; + int vlan_if_count; int dummy_if_count; int total_if_count; }; @@ -303,14 +317,14 @@ static void iface_cb(struct net_if *iface, void *user_data) net_if_get_by_iface(iface)); if (net_if_l2(iface) == &NET_L2_GET_NAME(ETHERNET)) { - if (PART_OF_ARRAY(NET_IF_GET_NAME(eth_test, 0), iface)) { - if (!extra_eth) { - /* Just use the first interface */ - extra_eth = iface; - } - } else { - eth_interfaces[ud->eth_if_count++] = iface; - } + eth_interfaces[ud->eth_if_count++] = iface; + } + + if (net_if_l2(iface) == &NET_L2_GET_NAME(VIRTUAL)) { + vlan_interfaces[ud->vlan_if_count++] = iface; + + zassert_true(ud->vlan_if_count <= NET_VLAN_MAX_COUNT, + "Too many VLAN interfaces"); } if (net_if_l2(iface) == &NET_L2_GET_NAME(DUMMY)) { @@ -329,25 +343,22 @@ static void iface_cb(struct net_if *iface, void *user_data) static void test_vlan_setup(void) { struct user_data ud = { 0 }; + int remaining; /* Make sure we have enough virtual interfaces */ net_if_foreach(iface_cb, &ud); /* One extra eth interface without vlan support */ - zassert_equal(ud.eth_if_count, NET_VLAN_MAX_COUNT, - "Invalid number of VLANs %d vs %d\n", - ud.eth_if_count, NET_VLAN_MAX_COUNT); - - zassert_equal(ud.total_if_count, NET_VLAN_MAX_COUNT + 1 + 2, - "Invalid number of interfaces"); - - /* Put the extra non-vlan ethernet interface to last */ - eth_interfaces[4] = extra_eth; - zassert_not_null(extra_eth, "Extra interface missing"); - zassert_equal_ptr(net_if_l2(extra_eth), &NET_L2_GET_NAME(ETHERNET), - "Invalid L2 type %p for iface %p (should be %p)\n", - net_if_l2(extra_eth), extra_eth, - &NET_L2_GET_NAME(ETHERNET)); + zassert_equal(ud.vlan_if_count, NET_VLAN_MAX_COUNT, + "Invalid number of VLANs %d vs %d", + ud.vlan_if_count, NET_VLAN_MAX_COUNT); + + remaining = ud.total_if_count - NET_VLAN_MAX_COUNT - + ud.eth_if_count - ud.dummy_if_count; + zassert_equal(remaining, 0, + "Invalid number of interfaces expecting %d got %d+%d+%d", + ud.total_if_count, NET_VLAN_MAX_COUNT, + ud.eth_if_count, ud.dummy_if_count); } static void test_address_setup(void) @@ -357,7 +368,7 @@ static void test_address_setup(void) iface1 = eth_interfaces[1]; /* This has VLAN enabled */ iface2 = eth_interfaces[0]; /* and this one not */ - iface3 = eth_interfaces[3]; /* and this one has VLAN enabled */ + iface3 = vlan_interfaces[0]; /* and this is the virtual VLAN interface */ zassert_not_null(iface1, "Interface 1"); zassert_not_null(iface2, "Interface 2"); @@ -402,9 +413,10 @@ static void test_address_setup(void) zassert_not_null(ifaddr, "addr3"); } + ifaddr->addr_state = NET_ADDR_PREFERRED; + net_if_up(iface1); net_if_up(iface2); - net_if_up(iface3); /* The interface might receive data which might fail the checks * in the iface sending function, so we need to reset the failure @@ -517,43 +529,51 @@ static void test_vlan_enable(void) struct net_if *iface; int ret; - ret = net_eth_vlan_enable(eth_interfaces[1], VLAN_TAG_1); - zassert_equal(ret, 0, "Cannot enable %d (%d)\n", VLAN_TAG_1, ret); - ret = net_eth_vlan_enable(eth_interfaces[3], VLAN_TAG_2); - zassert_equal(ret, 0, "Cannot enable %d (%d)\n", VLAN_TAG_2, ret); + ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_1); + zassert_equal(ret, 0, "Cannot enable %d (%d)", VLAN_TAG_1, ret); + ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_2); + zassert_equal(ret, 0, "Cannot enable %d (%d)", VLAN_TAG_2, ret); + ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_3); + zassert_equal(ret, 0, "Cannot enable %d (%d)", VLAN_TAG_3, ret); + ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_4); + zassert_equal(ret, 0, "Cannot enable %d (%d)", VLAN_TAG_4, ret); eth_ctx = net_if_l2_data(eth_interfaces[0]); iface = net_eth_get_vlan_iface(eth_interfaces[0], VLAN_TAG_1); - zassert_equal_ptr(iface, eth_interfaces[1], - "Invalid interface for tag %d (%p vs %p)\n", - VLAN_TAG_1, iface, eth_interfaces[1]); + zassert_equal_ptr(iface, vlan_interfaces[0], + "Invalid interface for tag %d (%p vs %p)", + VLAN_TAG_1, iface, vlan_interfaces[0]); iface = net_eth_get_vlan_iface(eth_interfaces[0], VLAN_TAG_2); - zassert_equal_ptr(iface, eth_interfaces[3], - "Invalid interface for tag %d (%p vs %p)\n", - VLAN_TAG_2, iface, eth_interfaces[3]); + zassert_equal_ptr(iface, vlan_interfaces[1], + "Invalid interface for tag %d (%p vs %p)", + VLAN_TAG_2, iface, vlan_interfaces[1]); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[0]); - zassert_equal(ret, false, "VLAN enabled for interface 0"); + iface = net_eth_get_vlan_iface(eth_interfaces[0], VLAN_TAG_3); + zassert_equal_ptr(iface, vlan_interfaces[2], + "Invalid interface for tag %d (%p vs %p)", + VLAN_TAG_3, iface, vlan_interfaces[2]); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[1]); - zassert_equal(ret, true, "VLAN disabled for interface 1"); + iface = net_eth_get_vlan_iface(eth_interfaces[0], VLAN_TAG_4); + zassert_equal_ptr(iface, vlan_interfaces[3], + "Invalid interface for tag %d (%p vs %p)", + VLAN_TAG_4, iface, vlan_interfaces[3]); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[2]); - zassert_equal(ret, false, "VLAN enabled for interface 2"); + ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[0]); + zassert_equal(ret, true, "VLAN enabled for interface 0"); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[3]); - zassert_equal(ret, true, "VLAN disabled for interface 3"); + ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[1]); + zassert_equal(ret, false, "VLAN enabled for interface 1"); iface = eth_interfaces[0]; ret = net_eth_vlan_enable(iface, NET_VLAN_TAG_UNSPEC); - zassert_equal(ret, -EBADF, "Invalid VLAN tag value %d\n", ret); + zassert_equal(ret, -EBADF, "Invalid VLAN tag value %d", ret); iface = eth_interfaces[1]; ret = net_eth_vlan_enable(iface, VLAN_TAG_1); - zassert_equal(ret, -EALREADY, "VLAN tag %d enabled for iface 1\n", - VLAN_TAG_1); + zassert_equal(ret, -EALREADY, "VLAN tag %d enabled for iface 1 (%d)", + VLAN_TAG_1, ret); } static void test_vlan_disable(void) @@ -563,21 +583,27 @@ static void test_vlan_disable(void) int ret; ret = net_eth_vlan_disable(eth_interfaces[1], VLAN_TAG_1); - zassert_equal(ret, 0, "Cannot disable %d (%d)\n", VLAN_TAG_1, ret); - ret = net_eth_vlan_disable(eth_interfaces[3], VLAN_TAG_2); - zassert_equal(ret, 0, "Cannot disable %d (%d)\n", VLAN_TAG_2, ret); + zassert_not_equal(ret, 0, "Could disable %d (%d)", VLAN_TAG_1, ret); + + ret = net_eth_vlan_disable(eth_interfaces[0], VLAN_TAG_1); + zassert_equal(ret, 0, "Cannot disable %d (%d)", VLAN_TAG_1, ret); + + ret = net_eth_vlan_disable(eth_interfaces[0], VLAN_TAG_2); + zassert_equal(ret, 0, "Cannot disable %d (%d)", VLAN_TAG_2, ret); + + ret = net_eth_vlan_disable(eth_interfaces[0], VLAN_TAG_3); + zassert_equal(ret, 0, "Cannot disable %d (%d)", VLAN_TAG_2, ret); + + ret = net_eth_vlan_disable(vlan_interfaces[3], VLAN_TAG_4); + zassert_equal(ret, 0, "Cannot disable %d (%d)", VLAN_TAG_2, ret); eth_ctx = net_if_l2_data(eth_interfaces[0]); iface = net_eth_get_vlan_iface(eth_interfaces[0], VLAN_TAG_1); - zassert_equal_ptr(iface, eth_interfaces[0], - "Invalid interface for tag %d (%p vs %p)\n", - VLAN_TAG_1, iface, eth_interfaces[0]); + zassert_equal_ptr(iface, NULL, "Valid interface for tag %d", VLAN_TAG_1); iface = net_eth_get_vlan_iface(eth_interfaces[0], VLAN_TAG_2); - zassert_equal_ptr(iface, eth_interfaces[0], - "Invalid interface for tag %d (%p vs %p)\n", - VLAN_TAG_2, iface, eth_interfaces[0]); + zassert_equal_ptr(iface, NULL, "Valid interface for tag %d", VLAN_TAG_2); ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[0]); zassert_equal(ret, false, "VLAN enabled for interface 0"); @@ -585,19 +611,13 @@ static void test_vlan_disable(void) ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[1]); zassert_equal(ret, false, "VLAN enabled for interface 1"); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[2]); - zassert_equal(ret, false, "VLAN enabled for interface 2"); - - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[3]); - zassert_equal(ret, false, "VLAN enabled for interface 3"); - iface = eth_interfaces[0]; ret = net_eth_vlan_disable(iface, NET_VLAN_TAG_UNSPEC); - zassert_equal(ret, -EBADF, "Invalid VLAN tag value %d\n", ret); + zassert_equal(ret, -EBADF, "Invalid VLAN tag value %d", ret); iface = eth_interfaces[1]; ret = net_eth_vlan_disable(iface, VLAN_TAG_1); - zassert_equal(ret, -ESRCH, "VLAN tag %d disabled for iface 1\n", + zassert_equal(ret, -ESRCH, "VLAN tag %d disabled for iface 1", VLAN_TAG_1); } @@ -608,27 +628,27 @@ static void test_vlan_enable_all(void) int ret; ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_1); - zassert_equal(ret, 0, "Cannot enable %d\n", VLAN_TAG_1); - ret = net_eth_vlan_enable(eth_interfaces[1], VLAN_TAG_2); - zassert_equal(ret, 0, "Cannot enable %d\n", VLAN_TAG_2); - ret = net_eth_vlan_enable(eth_interfaces[2], VLAN_TAG_3); - zassert_equal(ret, 0, "Cannot enable %d\n", VLAN_TAG_3); - ret = net_eth_vlan_enable(eth_interfaces[3], VLAN_TAG_4); - zassert_equal(ret, 0, "Cannot enable %d\n", VLAN_TAG_4); + zassert_equal(ret, 0, "Cannot enable %d", VLAN_TAG_1); + ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_2); + zassert_equal(ret, 0, "Cannot enable %d", VLAN_TAG_2); + ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_3); + zassert_equal(ret, 0, "Cannot enable %d", VLAN_TAG_3); + ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_4); + zassert_equal(ret, 0, "Cannot enable %d", VLAN_TAG_4); eth_ctx = net_if_l2_data(eth_interfaces[0]); ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[0]); zassert_equal(ret, true, "VLAN disabled for interface 0"); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[1]); - zassert_equal(ret, true, "VLAN disabled for interface 1"); + ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[0]); + zassert_equal(ret, true, "VLAN disabled for interface 0"); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[2]); - zassert_equal(ret, true, "VLAN disabled for interface 2"); + ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[0]); + zassert_equal(ret, true, "VLAN disabled for interface 0"); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[3]); - zassert_equal(ret, true, "VLAN disabled for interface 3"); + ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[0]); + zassert_equal(ret, true, "VLAN disabled for interface 0"); iface = net_if_get_first_by_type(&NET_L2_GET_NAME(DUMMY)); zassert_not_null(iface, "No dummy iface found"); @@ -637,7 +657,7 @@ static void test_vlan_enable_all(void) "Not a dummy interface"); ret = net_eth_vlan_enable(iface, VLAN_TAG_5); - zassert_equal(ret, -EINVAL, "Wrong iface type (%d)\n", ret); + zassert_equal(ret, -EINVAL, "Wrong iface type (%d)", ret); } static void test_vlan_disable_all(void) @@ -647,26 +667,26 @@ static void test_vlan_disable_all(void) int ret; ret = net_eth_vlan_disable(eth_interfaces[0], VLAN_TAG_1); - zassert_equal(ret, 0, "Cannot disable %d\n", VLAN_TAG_1); - ret = net_eth_vlan_disable(eth_interfaces[1], VLAN_TAG_2); - zassert_equal(ret, 0, "Cannot disable %d\n", VLAN_TAG_2); - ret = net_eth_vlan_disable(eth_interfaces[2], VLAN_TAG_3); - zassert_equal(ret, 0, "Cannot disable %d\n", VLAN_TAG_3); - ret = net_eth_vlan_disable(eth_interfaces[3], VLAN_TAG_4); - zassert_equal(ret, 0, "Cannot disable %d\n", VLAN_TAG_4); + zassert_equal(ret, 0, "Cannot disable %d", VLAN_TAG_1); + ret = net_eth_vlan_disable(eth_interfaces[0], VLAN_TAG_2); + zassert_equal(ret, 0, "Cannot disable %d", VLAN_TAG_2); + ret = net_eth_vlan_disable(eth_interfaces[0], VLAN_TAG_3); + zassert_equal(ret, 0, "Cannot disable %d", VLAN_TAG_3); + ret = net_eth_vlan_disable(eth_interfaces[0], VLAN_TAG_4); + zassert_equal(ret, 0, "Cannot disable %d", VLAN_TAG_4); eth_ctx = net_if_l2_data(eth_interfaces[0]); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[0]); + ret = net_eth_is_vlan_enabled(eth_ctx, vlan_interfaces[0]); zassert_equal(ret, false, "VLAN enabled for interface 0"); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[1]); + ret = net_eth_is_vlan_enabled(eth_ctx, vlan_interfaces[1]); zassert_equal(ret, false, "VLAN enabled for interface 1"); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[2]); + ret = net_eth_is_vlan_enabled(eth_ctx, vlan_interfaces[2]); zassert_equal(ret, false, "VLAN enabled for interface 2"); - ret = net_eth_is_vlan_enabled(eth_ctx, eth_interfaces[3]); + ret = net_eth_is_vlan_enabled(eth_ctx, vlan_interfaces[3]); zassert_equal(ret, false, "VLAN enabled for interface 3"); iface = net_if_get_first_by_type(&NET_L2_GET_NAME(DUMMY)); @@ -676,27 +696,17 @@ static void test_vlan_disable_all(void) "Not a dummy interface"); ret = net_eth_vlan_disable(iface, VLAN_TAG_5); - zassert_equal(ret, -EINVAL, "Wrong iface type (%d)\n", ret); + zassert_equal(ret, -EINVAL, "Wrong iface type (%d)", ret); } static bool add_neighbor(struct net_if *iface, struct in6_addr *addr) { - struct net_linkaddr_storage llstorage; - struct net_linkaddr lladdr; + struct net_linkaddr *ll_addr; struct net_nbr *nbr; - llstorage.addr[0] = 0x01; - llstorage.addr[1] = 0x02; - llstorage.addr[2] = 0x33; - llstorage.addr[3] = 0x44; - llstorage.addr[4] = 0x05; - llstorage.addr[5] = 0x06; - - lladdr.len = 6U; - lladdr.addr = llstorage.addr; - lladdr.type = NET_LINK_ETHERNET; + ll_addr = net_if_get_link_addr(iface); - nbr = net_ipv6_nbr_add(iface, addr, &lladdr, false, + nbr = net_ipv6_nbr_add(iface, addr, ll_addr, false, NET_IPV6_NBR_STATE_REACHABLE); if (!nbr) { DBG("Cannot add dst %s to neighbor cache\n", @@ -704,69 +714,104 @@ static bool add_neighbor(struct net_if *iface, struct in6_addr *addr) return false; } + DBG("Adding dst %s as [%s] to nbr cache\n", + net_sprint_ipv6_addr(addr), + net_sprint_ll_addr(ll_addr->addr, 6)); + return true; } -ZTEST(net_vlan, test_vlan_send_data) +static void comm_sendto_recvfrom(int client_sock, + struct sockaddr *client_addr, + socklen_t client_addrlen, + int server_sock, + struct sockaddr *server_addr, + socklen_t server_addrlen) +{ + ssize_t sent = 0; + + ARG_UNUSED(server_sock); + ARG_UNUSED(client_addr); + ARG_UNUSED(client_addrlen); + + zassert_not_null(client_addr, "null client addr"); + zassert_not_null(server_addr, "null server addr"); + + /* + * Test client -> server sending + */ + + sent = zsock_sendto(client_sock, TEST_STR_SMALL, strlen(TEST_STR_SMALL), + 0, server_addr, server_addrlen); + zassert_equal(sent, strlen(TEST_STR_SMALL), "sendto failed (%d vs %d)", + sent, strlen(TEST_STR_SMALL)); + + if (k_sem_take(&wait_data, WAIT_TIME)) { + DBG("Timeout while waiting interface data\n"); + zassert_false(true, "Timeout"); + } + + /* The data verification cannot be done easily because we are in the + * same link and our send/recv MAC addresses are the same and the + * packet is dropped by core stack. + * We cannot use loopback as then VLAN would not be used. + * One option would be to make a fully functional network but that is + * out of scope for this test application (at least for now). + * So do not try to verify data, just check the received tag value. + */ +} + +ZTEST(net_vlan, test_vlan_ipv6_sendto_recvfrom) { - struct ethernet_context *eth_ctx; /* This is L2 context */ - struct eth_context *ctx; /* This is interface context */ struct net_if *iface; int ret; - struct sockaddr_in6 dst_addr6 = { - .sin6_family = AF_INET6, - .sin6_port = htons(TEST_PORT), - }; - struct sockaddr_in6 src_addr6 = { - .sin6_family = AF_INET6, - .sin6_port = 0, - }; + int client_sock; + int server_sock; + struct sockaddr_in6 client_addr; + struct sockaddr_in6 server_addr; + struct eth_context *ctx; /* Setup the interfaces */ test_vlan_enable(); + test_vlan_disable_all(); - ret = net_context_get(AF_INET6, SOCK_DGRAM, IPPROTO_UDP, - &udp_v6_ctx); - zassert_equal(ret, 0, "Create IPv6 UDP context failed"); - - memcpy(&src_addr6.sin6_addr, &my_addr1, sizeof(struct in6_addr)); - memcpy(&dst_addr6.sin6_addr, &dst_addr, sizeof(struct in6_addr)); - - ret = net_context_bind(udp_v6_ctx, (struct sockaddr *)&src_addr6, - sizeof(struct sockaddr_in6)); - zassert_equal(ret, 0, "Context bind failure test failed"); + ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_1); + zassert_equal(ret, 0, "Could not enable %d (%d)", VLAN_TAG_1, ret); - iface = eth_interfaces[1]; /* This is the VLAN interface */ - ctx = net_if_get_device(iface)->data; - eth_ctx = net_if_l2_data(iface); - ret = net_eth_is_vlan_enabled(eth_ctx, iface); - zassert_equal(ret, true, "VLAN disabled for interface 1"); + iface = net_eth_get_vlan_iface(eth_interfaces[0], VLAN_TAG_1); + ret = net_eth_is_vlan_enabled(NULL, eth_interfaces[0]); + zassert_equal(ret, true, "VLAN not enabled for interface 1"); + ctx = net_if_get_device(eth_interfaces[0])->data; ctx->expecting_tag = VLAN_TAG_1; - iface = eth_interfaces[3]; /* This is also VLAN interface */ - ctx = net_if_get_device(iface)->data; - eth_ctx = net_if_l2_data(iface); - ret = net_eth_is_vlan_enabled(eth_ctx, iface); - zassert_equal(ret, true, "VLAN disabled for interface 1"); + net_if_up(eth_interfaces[0]); + net_if_up(vlan_interfaces[0]); - test_started = true; + prepare_sock_udp_v6(MY_IPV6_ADDR, ANY_PORT, &client_sock, &client_addr); + prepare_sock_udp_v6(MY_IPV6_ADDR_SRV, SERVER_PORT, &server_sock, &server_addr); - ret = add_neighbor(iface, &dst_addr); + ret = add_neighbor(iface, &server_addr.sin6_addr); zassert_true(ret, "Cannot add neighbor"); - ret = net_context_sendto(udp_v6_ctx, test_data, strlen(test_data), - (struct sockaddr *)&dst_addr6, - sizeof(struct sockaddr_in6), - NULL, K_NO_WAIT, NULL); - zassert_true(ret > 0, "Send UDP pkt failed"); + ret = bind(server_sock, + (struct sockaddr *)&server_addr, + sizeof(server_addr)); + zassert_equal(ret, 0, "bind failed"); - if (k_sem_take(&wait_data, WAIT_TIME)) { - DBG("Timeout while waiting interface data\n"); - zassert_false(true, "Timeout"); - } + test_started = true; - net_context_unref(udp_v6_ctx); + comm_sendto_recvfrom(client_sock, + (struct sockaddr *)&client_addr, + sizeof(client_addr), + server_sock, + (struct sockaddr *)&server_addr, + sizeof(server_addr)); + + ret = close(client_sock); + zassert_equal(ret, 0, "close failed"); + ret = close(server_sock); + zassert_equal(ret, 0, "close failed"); } static void *setup(void) From ff01324c9b9eabfcb72563e7820d70181c14cef3 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 17 Mar 2024 18:22:33 +0200 Subject: [PATCH 1559/2402] net: if: Remove VLAN count checks No need to do the checks any more because user has specified the VLAN count and so many VLAN virtual interface are already created. Signed-off-by: Jukka Rissanen --- subsys/net/ip/net_if.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 82e077f0d18..97a5f275703 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -5302,25 +5302,6 @@ void net_if_init(void) k_thread_name_set(&tx_thread_ts, "tx_tstamp"); #endif /* CONFIG_NET_PKT_TIMESTAMP_THREAD */ -#if defined(CONFIG_NET_VLAN) - /* Make sure that we do not have too many network interfaces - * compared to the number of VLAN interfaces. - */ - if_count = 0; - - STRUCT_SECTION_FOREACH(net_if, iface) { - if (net_if_l2(iface) == &NET_L2_GET_NAME(ETHERNET)) { - if_count++; - } - } - - if (if_count > CONFIG_NET_VLAN_COUNT) { - NET_WARN("You have configured only %d VLAN interfaces" - " but you have %d network interfaces.", - CONFIG_NET_VLAN_COUNT, if_count); - } -#endif - out: k_mutex_unlock(&lock); } From b5bdc1fa6bb9f6c7a97b438411aa2411ff45a289 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 18 Mar 2024 16:22:57 +0200 Subject: [PATCH 1560/2402] net: if: Enhance debug prints when adding IP address to iface Instead of printing just a network interface pointer, print also the interface index so debugging is a bit faster as no lookup from interface listing is needed. Signed-off-by: Jukka Rissanen --- subsys/net/ip/net_if.c | 49 +++++++++++++++++++++++++----------------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 97a5f275703..83ca7f6745e 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -123,10 +123,10 @@ static sys_slist_t timestamp_callbacks; #define debug_check_packet(pkt) \ do { \ NET_DBG("Processing (pkt %p, prio %d) network packet " \ - "iface %p/%d", \ + "iface %d (%p)", \ pkt, net_pkt_priority(pkt), \ - net_pkt_iface(pkt), \ - net_if_get_by_iface(net_pkt_iface(pkt))); \ + net_if_get_by_iface(net_pkt_iface(pkt)), \ + net_pkt_iface(pkt)); \ \ NET_ASSERT(pkt->frags); \ } while (0) @@ -1775,8 +1775,9 @@ struct net_if_addr *net_if_ipv6_addr_add(struct net_if *iface, net_if_addr_init(&ipv6->unicast[i], addr, addr_type, vlifetime); - NET_DBG("[%zu] interface %p address %s type %s added", i, - iface, net_sprint_ipv6_addr(addr), + NET_DBG("[%zu] interface %d (%p) address %s type %s added", i, + net_if_get_by_iface(iface), iface, + net_sprint_ipv6_addr(addr), net_addr_type2str(addr_type)); if (!(l2_flags_get(iface) & NET_L2_POINT_TO_POINT) && @@ -1896,8 +1897,9 @@ bool net_if_ipv6_addr_rm(struct net_if *iface, const struct in6_addr *addr) net_if_ipv6_maddr_rm(iface, &maddr); } - NET_DBG("[%d] interface %p address %s type %s removed", - found, iface, net_sprint_ipv6_addr(addr), + NET_DBG("[%d] interface %d (%p) address %s type %s removed", + found, net_if_get_by_iface(iface), iface, + net_sprint_ipv6_addr(addr), net_addr_type2str(ipv6->unicast[found].addr_type)); /* Using the IPv6 address pointer here can give false @@ -2057,7 +2059,8 @@ struct net_if_mcast_addr *net_if_ipv6_maddr_add(struct net_if *iface, ipv6->mcast[i].address.family = AF_INET6; memcpy(&ipv6->mcast[i].address.in6_addr, addr, 16); - NET_DBG("[%zu] interface %p address %s added", i, iface, + NET_DBG("[%zu] interface %d (%p) address %s added", i, + net_if_get_by_iface(iface), iface, net_sprint_ipv6_addr(addr)); net_mgmt_event_notify_with_info( @@ -2099,8 +2102,9 @@ bool net_if_ipv6_maddr_rm(struct net_if *iface, const struct in6_addr *addr) ipv6->mcast[i].is_used = false; - NET_DBG("[%zu] interface %p address %s removed", - i, iface, net_sprint_ipv6_addr(addr)); + NET_DBG("[%zu] interface %d (%p) address %s removed", + i, net_if_get_by_iface(iface), iface, + net_sprint_ipv6_addr(addr)); net_mgmt_event_notify_with_info( NET_EVENT_IPV6_MADDR_DEL, iface, @@ -4047,8 +4051,9 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface, */ ifaddr->addr_state = NET_ADDR_PREFERRED; - NET_DBG("[%d] interface %p address %s type %s added", - idx, iface, net_sprint_ipv4_addr(addr), + NET_DBG("[%d] interface %d (%p) address %s type %s added", + idx, net_if_get_by_iface(iface), iface, + net_sprint_ipv4_addr(addr), net_addr_type2str(addr_type)); net_mgmt_event_notify_with_info(NET_EVENT_IPV4_ADDR_ADD, iface, @@ -4087,8 +4092,9 @@ bool net_if_ipv4_addr_rm(struct net_if *iface, const struct in_addr *addr) ipv4->unicast[i].ipv4.is_used = false; - NET_DBG("[%zu] interface %p address %s removed", - i, iface, net_sprint_ipv4_addr(addr)); + NET_DBG("[%zu] interface %d (%p) address %s removed", + i, net_if_get_by_iface(iface), iface, + net_sprint_ipv4_addr(addr)); net_mgmt_event_notify_with_info( NET_EVENT_IPV4_ADDR_DEL, iface, @@ -4261,7 +4267,8 @@ struct net_if_mcast_addr *net_if_ipv4_maddr_add(struct net_if *iface, maddr->address.family = AF_INET; maddr->address.in_addr.s4_addr32[0] = addr->s4_addr32[0]; - NET_DBG("interface %p address %s added", iface, + NET_DBG("interface %d (%p) address %s added", + net_if_get_by_iface(iface), iface, net_sprint_ipv4_addr(addr)); net_mgmt_event_notify_with_info( @@ -4287,8 +4294,9 @@ bool net_if_ipv4_maddr_rm(struct net_if *iface, const struct in_addr *addr) if (maddr) { maddr->is_used = false; - NET_DBG("interface %p address %s removed", - iface, net_sprint_ipv4_addr(addr)); + NET_DBG("interface %d (%p) address %s removed", + net_if_get_by_iface(iface), iface, + net_sprint_ipv4_addr(addr)); net_mgmt_event_notify_with_info( NET_EVENT_IPV4_MADDR_DEL, iface, @@ -4689,8 +4697,9 @@ static void update_operational_state(struct net_if *iface) return; } - NET_DBG("iface %p, oper state %s admin %s carrier %s dormant %s", - iface, net_if_oper_state2str(net_if_oper_state(iface)), + NET_DBG("iface %d (%p), oper state %s admin %s carrier %s dormant %s", + net_if_get_by_iface(iface), iface, + net_if_oper_state2str(net_if_oper_state(iface)), net_if_is_admin_up(iface) ? "UP" : "DOWN", net_if_is_carrier_ok(iface) ? "ON" : "OFF", net_if_is_dormant(iface) ? "ON" : "OFF"); @@ -4725,7 +4734,7 @@ int net_if_up(struct net_if *iface) { int status = 0; - NET_DBG("iface %p", iface); + NET_DBG("iface %d (%p)", net_if_get_by_iface(iface), iface); net_if_lock(iface); From a96a2f8d09a2dd90468db33cd46d070ebf09fc14 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 18 Mar 2024 17:05:09 +0200 Subject: [PATCH 1561/2402] net: if: Start IPv6 DAD when interface comes up Start any pending IPv6 DAD timers when interface comes up. If IPv6 addresses have been added to the network interface when it was down, the addresses would never work properly if the DAD is not done. Signed-off-by: Jukka Rissanen --- include/zephyr/net/net_if.h | 2 ++ subsys/net/ip/net_if.c | 36 ++++++++++++++++++------------------ 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/include/zephyr/net/net_if.h b/include/zephyr/net/net_if.h index 98baae409a8..03a936626d1 100644 --- a/include/zephyr/net/net_if.h +++ b/include/zephyr/net/net_if.h @@ -71,6 +71,8 @@ struct net_if_addr { #if defined(CONFIG_NET_IPV6_DAD) && defined(CONFIG_NET_NATIVE_IPV6) /** How many times we have done DAD */ uint8_t dad_count; + /* What interface the DAD is running */ + uint8_t ifindex; #endif /** Is the IP address valid forever */ diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 83ca7f6745e..644238f8b5c 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -1209,28 +1209,22 @@ static void dad_timeout(struct k_work *work) struct net_if_addr *tmp; struct net_if *iface; - NET_DBG("DAD succeeded for %s", - net_sprint_ipv6_addr(&ifaddr->address.in6_addr)); + NET_DBG("DAD succeeded for %s at interface %d", + net_sprint_ipv6_addr(&ifaddr->address.in6_addr), + ifaddr->ifindex); ifaddr->addr_state = NET_ADDR_PREFERRED; + iface = net_if_get_by_index(ifaddr->ifindex); - /* Because we do not know the interface at this point, - * we need to lookup for it. - */ - iface = NULL; - tmp = net_if_ipv6_addr_lookup(&ifaddr->address.in6_addr, - &iface); - if (tmp == ifaddr) { - net_mgmt_event_notify_with_info( - NET_EVENT_IPV6_DAD_SUCCEED, - iface, &ifaddr->address.in6_addr, - sizeof(struct in6_addr)); + net_mgmt_event_notify_with_info(NET_EVENT_IPV6_DAD_SUCCEED, + iface, + &ifaddr->address.in6_addr, + sizeof(struct in6_addr)); - /* The address gets added to neighbor cache which is not - * needed in this case as the address is our own one. - */ - net_ipv6_nbr_rm(iface, &ifaddr->address.in6_addr); - } + /* The address gets added to neighbor cache which is not + * needed in this case as the address is our own one. + */ + net_ipv6_nbr_rm(iface, &ifaddr->address.in6_addr); } } @@ -1251,8 +1245,11 @@ static void net_if_ipv6_start_dad(struct net_if *iface, if (!net_ipv6_start_dad(iface, ifaddr)) { ifaddr->dad_start = k_uptime_get_32(); + ifaddr->ifindex = net_if_get_by_iface(iface); k_mutex_lock(&lock, K_FOREVER); + sys_slist_find_and_remove(&active_dad_timers, + &ifaddr->dad_node); sys_slist_append(&active_dad_timers, &ifaddr->dad_node); k_mutex_unlock(&lock); @@ -4782,6 +4779,9 @@ int net_if_up(struct net_if *iface) net_mgmt_event_notify(NET_EVENT_IF_ADMIN_UP, iface); update_operational_state(iface); + /* Make sure that we update the IPv6 addresses */ + net_if_start_dad(iface); + out: net_if_unlock(iface); From 493c1c1f01cb25bbc97f5bc2d425e15609e7dc2b Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 18 Mar 2024 17:08:47 +0200 Subject: [PATCH 1562/2402] net: if: Add debug print when interface is taken up Add debug information to print when the network L2 enable callback is called and fails. Useful to see this information as at that point the interface goes down. Signed-off-by: Jukka Rissanen --- subsys/net/ip/net_if.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 644238f8b5c..0fd44d5ec48 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -4766,9 +4766,14 @@ int net_if_up(struct net_if *iface) } } - /* Notify L2 to enable the interface */ + /* Notify L2 to enable the interface. Note that the interface is still down + * at this point from network interface point of view i.e., the NET_IF_UP + * flag has not been set yet. + */ status = net_if_l2(iface)->enable(iface, true); if (status < 0) { + NET_DBG("Cannot take interface %d up (%d)", + net_if_get_by_iface(iface), status); goto out; } From e3f1271fb97a02c27acefc1ffd88cc678386c1a8 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 18 Mar 2024 18:03:47 +0200 Subject: [PATCH 1563/2402] net: if: Join all unjoined solicited node multicast groups If an IPv6 address was added to the interface while the interface was down, its solicited node multicast address is not joined properly and IPv6 communication will to other hosts will fail. So make sure to rejoin all the solicited node multicast groups that were joined already when the network inteface is going up. Signed-off-by: Jukka Rissanen --- subsys/net/ip/net_if.c | 73 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 67 insertions(+), 6 deletions(-) diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 0fd44d5ec48..e45b8f2110c 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -1105,8 +1105,9 @@ static void join_mcast_allnodes(struct net_if *iface) ret = net_ipv6_mld_join(iface, &addr); if (ret < 0 && ret != -EALREADY) { - NET_ERR("Cannot join all nodes address %s (%d)", - net_sprint_ipv6_addr(&addr), ret); + NET_ERR("Cannot join all nodes address %s for %d (%d)", + net_sprint_ipv6_addr(&addr), + net_if_get_by_iface(iface), ret); } } @@ -1121,8 +1122,13 @@ static void join_mcast_solicit_node(struct net_if *iface, ret = net_ipv6_mld_join(iface, &addr); if (ret < 0 && ret != -EALREADY) { - NET_ERR("Cannot join solicit node address %s (%d)", - net_sprint_ipv6_addr(&addr), ret); + NET_ERR("Cannot join solicit node address %s for %d (%d)", + net_sprint_ipv6_addr(&addr), + net_if_get_by_iface(iface), ret); + } else { + NET_DBG("Join solicit node address %s (ifindex %d)", + net_sprint_ipv6_addr(&addr), + net_if_get_by_iface(iface)); } } @@ -1206,7 +1212,6 @@ static void dad_timeout(struct k_work *work) k_mutex_unlock(&lock); SYS_SLIST_FOR_EACH_CONTAINER(&expired_list, ifaddr, dad_node) { - struct net_if_addr *tmp; struct net_if *iface; NET_DBG("DAD succeeded for %s at interface %d", @@ -1616,6 +1621,52 @@ static inline int z_vrfy_net_if_ipv6_addr_lookup_by_index( #include #endif +/* To be called when interface comes up so that all the non-joined multicast + * groups are joined. + */ +static void rejoin_ipv6_mcast_groups(struct net_if *iface) +{ + struct net_if_ipv6 *ipv6; + + net_if_lock(iface); + + if (net_if_config_ipv6_get(iface, &ipv6) < 0) { + goto out; + } + + ARRAY_FOR_EACH(ipv6->unicast, i) { + struct net_if_mcast_addr *maddr; + struct in6_addr addr; + int ret; + + if (!ipv6->unicast[i].is_used) { + continue; + } + + net_ipv6_addr_create_solicited_node( + &ipv6->unicast[i].address.in6_addr, + &addr); + + maddr = net_if_ipv6_maddr_lookup(&addr, &iface); + if (!maddr) { + continue; + } + + if (net_if_ipv4_maddr_is_joined(maddr)) { + continue; + } + + ret = net_ipv6_mld_join(iface, &addr); + if (ret < 0 && ret != EALREADY) { + NET_DBG("Cannot rejoin multicast group %s (%d)", + net_sprint_ipv6_addr(&addr), ret); + } + } + +out: + net_if_unlock(iface); +} + static void address_expired(struct net_if_addr *ifaddr) { NET_DBG("IPv6 address %s is deprecated", @@ -4727,6 +4778,13 @@ static void init_igmp(struct net_if *iface) #endif } +static void rejoin_multicast_groups(struct net_if *iface) +{ +#if defined(CONFIG_NET_NATIVE_IPV6) + rejoin_ipv6_mcast_groups(iface); +#endif +} + int net_if_up(struct net_if *iface) { int status = 0; @@ -4784,7 +4842,10 @@ int net_if_up(struct net_if *iface) net_mgmt_event_notify(NET_EVENT_IF_ADMIN_UP, iface); update_operational_state(iface); - /* Make sure that we update the IPv6 addresses */ + /* Make sure that we update the IPv6 addresses and join the + * multicast groups. + */ + rejoin_multicast_groups(iface); net_if_start_dad(iface); out: From 63081bd7da94154c158826660c8529c06f2c8879 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 17:59:05 +0200 Subject: [PATCH 1564/2402] net: if: We can only rejoin mcast groups for native IP stack No point trying to join multicast groups if the network interface is offloaded one. Signed-off-by: Jukka Rissanen --- subsys/net/ip/net_if.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index e45b8f2110c..8b3d90aa284 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -4842,11 +4842,13 @@ int net_if_up(struct net_if *iface) net_mgmt_event_notify(NET_EVENT_IF_ADMIN_UP, iface); update_operational_state(iface); - /* Make sure that we update the IPv6 addresses and join the - * multicast groups. - */ - rejoin_multicast_groups(iface); - net_if_start_dad(iface); + if (!net_if_is_offloaded(iface)) { + /* Make sure that we update the IPv6 addresses and join the + * multicast groups. + */ + rejoin_multicast_groups(iface); + net_if_start_dad(iface); + } out: net_if_unlock(iface); From e9994c8af83bc1a51cc8ca8aaccf679366e3b6e0 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 18 Mar 2024 12:01:10 +0200 Subject: [PATCH 1565/2402] net: virtual: Force LAA bit for link address Make sure LAA (locally administred address) bit is set for the generated link address. Signed-off-by: Jukka Rissanen --- subsys/net/l2/virtual/virtual.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/subsys/net/l2/virtual/virtual.c b/subsys/net/l2/virtual/virtual.c index 4e0fa0311b0..b93bc2f7245 100644 --- a/subsys/net/l2/virtual/virtual.c +++ b/subsys/net/l2/virtual/virtual.c @@ -168,6 +168,8 @@ static void random_linkaddr(uint8_t *linkaddr, size_t len) for (i = 0; i < len; i++) { linkaddr[i] = sys_rand32_get(); } + + linkaddr[0] |= 0x02; /* force LAA bit */ } int net_virtual_interface_attach(struct net_if *virtual_iface, From 092f7f76661038029c47ec738fc6162c362610dc Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 27 Mar 2024 10:04:47 +0200 Subject: [PATCH 1566/2402] net: virtual: Do not try to send data if interface is down Make sure the interface is up before trying to send data to lower level interface. Signed-off-by: Jukka Rissanen --- subsys/net/l2/virtual/virtual.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/subsys/net/l2/virtual/virtual.c b/subsys/net/l2/virtual/virtual.c index b93bc2f7245..7044665ae8e 100644 --- a/subsys/net/l2/virtual/virtual.c +++ b/subsys/net/l2/virtual/virtual.c @@ -84,6 +84,12 @@ static int virtual_send(struct net_if *iface, struct net_pkt *pkt) return -ENOENT; } + if (!net_if_is_up(iface)) { + NET_DBG("Interface %d is down.", + net_if_get_by_iface(iface)); + return -ENETDOWN; + } + if (IS_ENABLED(CONFIG_NET_STATISTICS)) { pkt_len = net_pkt_get_len(pkt); } From eb11a8af1ceb40e332203e9ebaafdd3e88ed13a9 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 17 Mar 2024 18:23:44 +0200 Subject: [PATCH 1567/2402] net: shell: Refactor VLAN configuration prints Rework the way VLAN configuration is printed out. Signed-off-by: Jukka Rissanen --- subsys/net/lib/shell/iface.c | 28 +++++++++------------------- subsys/net/lib/shell/vlan.c | 32 ++++++++++---------------------- 2 files changed, 19 insertions(+), 41 deletions(-) diff --git a/subsys/net/lib/shell/iface.c b/subsys/net/lib/shell/iface.c index f5e8ab5ae6c..4cbfb166115 100644 --- a/subsys/net/lib/shell/iface.c +++ b/subsys/net/lib/shell/iface.c @@ -136,9 +136,6 @@ static void iface_cb(struct net_if *iface, void *user_data) #if defined(CONFIG_NET_IPV4) struct net_if_ipv4 *ipv4; #endif -#if defined(CONFIG_NET_VLAN) - struct ethernet_context *eth_ctx; -#endif #if defined(CONFIG_NET_IP) struct net_if_addr *unicast; struct net_if_mcast_addr *mcast; @@ -285,23 +282,16 @@ static void iface_cb(struct net_if *iface, void *user_data) #endif #if defined(CONFIG_NET_VLAN) - if (net_if_l2(iface) == &NET_L2_GET_NAME(ETHERNET)) { - eth_ctx = net_if_l2_data(iface); - - if (eth_ctx->vlan_enabled) { - for (int i = 0; i < CONFIG_NET_VLAN_COUNT; i++) { - if (eth_ctx->vlan[i].iface != iface || - eth_ctx->vlan[i].tag == - NET_VLAN_TAG_UNSPEC) { - continue; - } - - PR("VLAN tag : %d (0x%x)\n", - eth_ctx->vlan[i].tag, - eth_ctx->vlan[i].tag); + if (net_if_l2(iface) == &NET_L2_GET_NAME(VIRTUAL)) { + if (net_virtual_get_iface_capabilities(iface) & VIRTUAL_INTERFACE_VLAN) { + uint16_t tag; + + tag = net_eth_get_vlan_tag(iface); + if (tag == NET_VLAN_TAG_UNSPEC) { + PR("VLAN not configured\n"); + } else { + PR("VLAN tag : %d (0x%03x)\n", tag, tag); } - } else { - PR("VLAN not enabled\n"); } } #endif diff --git a/subsys/net/lib/shell/vlan.c b/subsys/net/lib/shell/vlan.c index ea7103ef1c9..c29aeeb5068 100644 --- a/subsys/net/lib/shell/vlan.c +++ b/subsys/net/lib/shell/vlan.c @@ -44,40 +44,26 @@ static void iface_vlan_del_cb(struct net_if *iface, void *user_data) static void iface_vlan_cb(struct net_if *iface, void *user_data) { - struct ethernet_context *ctx = net_if_l2_data(iface); struct net_shell_user_data *data = user_data; const struct shell *sh = data->sh; int *count = data->user_data; - int i; - if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { + if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) { return; } - if (*count == 0) { - PR(" Interface Type Tag\n"); - } - - if (!ctx->vlan_enabled) { - PR_WARNING("VLAN tag(s) not set\n"); + if (!(net_virtual_get_iface_capabilities(iface) & VIRTUAL_INTERFACE_VLAN)) { return; } - for (i = 0; i < NET_VLAN_MAX_COUNT; i++) { - if (!ctx->vlan[i].iface || ctx->vlan[i].iface != iface) { - continue; - } - - if (ctx->vlan[i].tag == NET_VLAN_TAG_UNSPEC) { - continue; - } - - PR("[%d] %p %s %d\n", net_if_get_by_iface(iface), iface, - iface2str(iface, NULL), ctx->vlan[i].tag); - - break; + if (*count == 0) { + PR(" Interface Type\tTag\tAttached\n"); } + PR("[%d] %p %8s\t%d\t%d\n", net_if_get_by_iface(iface), iface, + iface2str(iface, NULL), net_eth_get_vlan_tag(iface), + net_if_get_by_iface(net_eth_get_vlan_main(iface))); + (*count)++; } #endif /* CONFIG_NET_VLAN */ @@ -156,6 +142,8 @@ static int cmd_net_vlan_add(const struct shell *sh, size_t argc, char *argv[]) return -ENOEXEC; } + iface = net_eth_get_vlan_iface(iface, tag); + PR("VLAN tag %d set to interface %d (%p)\n", tag, net_if_get_by_iface(iface), iface); From 999c169d9db1a749c6867030b816747693e29fea Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 18 Mar 2024 16:24:20 +0200 Subject: [PATCH 1568/2402] net: shell: Print VLAN name instead of interface type As the interface type is always Virtual, no need to print it. Print instead the name of the network interface as it is more useful to the user. Signed-off-by: Jukka Rissanen --- subsys/net/lib/shell/vlan.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/subsys/net/lib/shell/vlan.c b/subsys/net/lib/shell/vlan.c index c29aeeb5068..824832f4054 100644 --- a/subsys/net/lib/shell/vlan.c +++ b/subsys/net/lib/shell/vlan.c @@ -13,6 +13,7 @@ LOG_MODULE_DECLARE(net_shell); #endif #include +#include #include #include "net_shell_private.h" @@ -47,6 +48,7 @@ static void iface_vlan_cb(struct net_if *iface, void *user_data) struct net_shell_user_data *data = user_data; const struct shell *sh = data->sh; int *count = data->user_data; + char name[IFNAMSIZ]; if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) { return; @@ -57,11 +59,13 @@ static void iface_vlan_cb(struct net_if *iface, void *user_data) } if (*count == 0) { - PR(" Interface Type\tTag\tAttached\n"); + PR(" Interface Name \tTag\tAttached\n"); } - PR("[%d] %p %8s\t%d\t%d\n", net_if_get_by_iface(iface), iface, - iface2str(iface, NULL), net_eth_get_vlan_tag(iface), + (void)net_if_get_name(iface, name, sizeof(name)); + + PR("[%d] %p %-12s\t%d\t%d\n", net_if_get_by_iface(iface), iface, + name, net_eth_get_vlan_tag(iface), net_if_get_by_iface(net_eth_get_vlan_main(iface))); (*count)++; From 0de1a75f9172a932f61edddb10b525646c8e1274 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 18 Mar 2024 17:28:28 +0200 Subject: [PATCH 1569/2402] net: shell: Print multicast join status for iface cmd Print information whether a multicast address is properly joined to a multicast group when print addresses using "net iface" command. Signed-off-by: Jukka Rissanen --- subsys/net/lib/shell/iface.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/subsys/net/lib/shell/iface.c b/subsys/net/lib/shell/iface.c index 4cbfb166115..ac3980c6213 100644 --- a/subsys/net/lib/shell/iface.c +++ b/subsys/net/lib/shell/iface.c @@ -344,7 +344,8 @@ static void iface_cb(struct net_if *iface, void *user_data) continue; } - PR("\t%s\n", net_sprint_ipv6_addr(&mcast->address.in6_addr)); + PR("\t%s%s\n", net_sprint_ipv6_addr(&mcast->address.in6_addr), + net_if_ipv6_maddr_is_joined(mcast) ? "" : " "); count++; } @@ -455,7 +456,8 @@ static void iface_cb(struct net_if *iface, void *user_data) continue; } - PR("\t%s\n", net_sprint_ipv4_addr(&mcast->address.in_addr)); + PR("\t%s%s\n", net_sprint_ipv4_addr(&mcast->address.in_addr), + net_if_ipv4_maddr_is_joined(mcast) ? "" : " "); count++; } From 0e6341cc2278f1c49c9f8427da0ecfd80ed2fe0c Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 18 Mar 2024 18:18:36 +0200 Subject: [PATCH 1570/2402] net: ethernet: Enhance debug prints by printing ifindex Network interface index number is useful to see in debug messages so print it. Signed-off-by: Jukka Rissanen --- subsys/net/l2/ethernet/ethernet.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/subsys/net/l2/ethernet/ethernet.c b/subsys/net/l2/ethernet/ethernet.c index 1f2ce0514e6..2dd8121c206 100644 --- a/subsys/net/l2/ethernet/ethernet.c +++ b/subsys/net/l2/ethernet/ethernet.c @@ -87,10 +87,11 @@ void net_eth_ipv6_mcast_to_mac_addr(const struct in6_addr *ipv6_addr, net_sprint_ll_addr((src)->addr, \ sizeof(struct net_eth_addr))); \ \ - NET_DBG("iface %p src %s dst %s type 0x%x len %zu", \ - net_pkt_iface(pkt), out, \ - net_sprint_ll_addr((dst)->addr, \ - sizeof(struct net_eth_addr)), \ + NET_DBG("iface %d (%p) src %s dst %s type 0x%x len %zu", \ + net_if_get_by_iface(net_pkt_iface(pkt)), \ + net_pkt_iface(pkt), out, \ + net_sprint_ll_addr((dst)->addr, \ + sizeof(struct net_eth_addr)), \ type, (size_t)len); \ } @@ -103,10 +104,11 @@ void net_eth_ipv6_mcast_to_mac_addr(const struct in6_addr *ipv6_addr, net_sprint_ll_addr((src)->addr, \ sizeof(struct net_eth_addr))); \ \ - NET_DBG("iface %p src %s dst %s type 0x%x " \ + NET_DBG("iface %d (%p) src %s dst %s type 0x%x " \ "tag %d %spri %d len %zu", \ - net_pkt_iface(pkt), out, \ - net_sprint_ll_addr((dst)->addr, \ + net_if_get_by_iface(net_pkt_iface(pkt)), \ + net_pkt_iface(pkt), out, \ + net_sprint_ll_addr((dst)->addr, \ sizeof(struct net_eth_addr)), \ type, net_eth_vlan_get_vid(tci), \ tagstrip ? "(stripped) " : "", \ @@ -327,7 +329,8 @@ static enum net_verdict ethernet_recv(struct net_if *iface, break; } - NET_DBG("Unknown hdr type 0x%04x iface %p", type, iface); + NET_DBG("Unknown hdr type 0x%04x iface %d (%p)", type, + net_if_get_by_iface(iface), iface); eth_stats_update_unknown_protocol(iface); return NET_DROP; } @@ -460,14 +463,14 @@ static struct net_pkt *ethernet_ll_prepare_on_ipv4(struct net_if *iface, } if (pkt != arp_pkt) { - NET_DBG("Sending arp pkt %p (orig %p) to iface %p", - arp_pkt, pkt, iface); + NET_DBG("Sending arp pkt %p (orig %p) to iface %d (%p)", + arp_pkt, pkt, net_if_get_by_iface(iface), iface); net_pkt_unref(pkt); return arp_pkt; } - NET_DBG("Found ARP entry, sending pkt %p to iface %p", - pkt, iface); + NET_DBG("Found ARP entry, sending pkt %p to iface %d (%p)", + pkt, net_if_get_by_iface(iface), iface); } return pkt; @@ -954,7 +957,8 @@ void ethernet_init(struct net_if *iface) { struct ethernet_context *ctx = net_if_l2_data(iface); - NET_DBG("Initializing Ethernet L2 %p for iface %p", ctx, iface); + NET_DBG("Initializing Ethernet L2 %p for iface %d (%p)", ctx, + net_if_get_by_iface(iface), iface); ctx->ethernet_l2_flags = NET_L2_MULTICAST; ctx->iface = iface; From 3a67c6d8f5f7fb4a3380f84d5fadcaca79e78bd2 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 11:02:07 +0200 Subject: [PATCH 1571/2402] net: arp: Enhance debug prints by printing interface index Print also network interface index together with the pointer value in order to get more useful information what is going on in the system. Signed-off-by: Jukka Rissanen --- subsys/net/l2/ethernet/arp.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/subsys/net/l2/ethernet/arp.c b/subsys/net/l2/ethernet/arp.c index fbedbaf1df9..7c0a2ba74f2 100644 --- a/subsys/net/l2/ethernet/arp.c +++ b/subsys/net/l2/ethernet/arp.c @@ -36,7 +36,7 @@ static struct k_mutex arp_mutex; static void arp_entry_cleanup(struct arp_entry *entry, bool pending) { - NET_DBG("%p", entry); + NET_DBG("entry %p", entry); if (pending) { struct net_pkt *pkt; @@ -64,8 +64,9 @@ static struct arp_entry *arp_entry_find(sys_slist_t *list, struct arp_entry *entry; SYS_SLIST_FOR_EACH_CONTAINER(list, entry, node) { - NET_DBG("iface %p dst %s", - iface, net_sprint_ipv4_addr(&entry->ip)); + NET_DBG("iface %d (%p) dst %s", + net_if_get_by_iface(iface), iface, + net_sprint_ipv4_addr(&entry->ip)); if (entry->iface == iface && net_ipv4_addr_cmp(&entry->ip, dst)) { @@ -474,7 +475,8 @@ void net_arp_update(struct net_if *iface, struct arp_entry *entry; struct net_pkt *pkt; - NET_DBG("src %s", net_sprint_ipv4_addr(src)); + NET_DBG("iface %d (%p) src %s", net_if_get_by_iface(iface), iface, + net_sprint_ipv4_addr(src)); net_if_tx_lock(iface); k_mutex_lock(&arp_mutex, K_FOREVER); @@ -532,7 +534,8 @@ void net_arp_update(struct net_if *iface, net_pkt_lladdr_dst(pkt)->addr = (uint8_t *) &NET_ETH_HDR(pkt)->dst.addr; - NET_DBG("dst %s pending %p frag %p", + NET_DBG("iface %d (%p) dst %s pending %p frag %p", + net_if_get_by_iface(iface), iface, net_sprint_ipv4_addr(&entry->ip), pkt, pkt->frags); @@ -694,10 +697,11 @@ enum net_verdict net_arp_input(struct net_pkt *pkt, * and the target IP address is our address. */ if (net_eth_is_addr_unspecified(&arp_hdr->dst_hwaddr)) { - NET_DBG("Updating ARP cache for %s [%s]", + NET_DBG("Updating ARP cache for %s [%s] iface %d", net_sprint_ipv4_addr(&arp_hdr->src_ipaddr), net_sprint_ll_addr((uint8_t *)&arp_hdr->src_hwaddr, - arp_hdr->hwlen)); + arp_hdr->hwlen), + net_if_get_by_iface(net_pkt_iface(pkt))); net_arp_update(net_pkt_iface(pkt), (struct in_addr *)arp_hdr->src_ipaddr, From aca5f43eccb22f87eab2fcecbdba6fe08e3d4200 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 18 Mar 2024 18:43:57 +0200 Subject: [PATCH 1572/2402] drivers: eth: native_sim: Remove VLAN handling Virtual LAN logic is now done in Ethernet L2 so no need to manipulate VLAN packets in the driver. Signed-off-by: Jukka Rissanen --- drivers/ethernet/eth_native_posix.c | 151 +++------------------------- 1 file changed, 13 insertions(+), 138 deletions(-) diff --git a/drivers/ethernet/eth_native_posix.c b/drivers/ethernet/eth_native_posix.c index 9f1b7b2bcda..e938b2a794d 100644 --- a/drivers/ethernet/eth_native_posix.c +++ b/drivers/ethernet/eth_native_posix.c @@ -95,31 +95,15 @@ static struct gptp_hdr *check_gptp_msg(struct net_if *iface, uint8_t *msg_start = net_pkt_data(pkt); struct gptp_hdr *gptp_hdr; int eth_hlen; + struct net_eth_hdr *hdr; -#if defined(CONFIG_NET_VLAN) - if (net_eth_get_vlan_status(iface)) { - struct net_eth_vlan_hdr *hdr_vlan; - - hdr_vlan = (struct net_eth_vlan_hdr *)msg_start; - if (ntohs(hdr_vlan->type) != NET_ETH_PTYPE_PTP) { - return NULL; - } - - eth_hlen = sizeof(struct net_eth_vlan_hdr); - } else -#endif - { - struct net_eth_hdr *hdr; - - hdr = (struct net_eth_hdr *)msg_start; - if (ntohs(hdr->type) != NET_ETH_PTYPE_PTP) { - return NULL; - } - - - eth_hlen = sizeof(struct net_eth_hdr); + hdr = (struct net_eth_hdr *)msg_start; + if (ntohs(hdr->type) != NET_ETH_PTYPE_PTP) { + return NULL; } + eth_hlen = sizeof(struct net_eth_hdr); + /* In TX, the first net_buf contains the Ethernet header * and the actual gPTP header is in the second net_buf. * In RX, the Ethernet header + other headers are in the @@ -210,87 +194,8 @@ static struct net_linkaddr *eth_get_mac(struct eth_context *ctx) return &ctx->ll_addr; } -static inline struct net_if *get_iface(struct eth_context *ctx, - uint16_t vlan_tag) -{ -#if defined(CONFIG_NET_VLAN) - struct net_if *iface; - - iface = net_eth_get_vlan_iface(ctx->iface, vlan_tag); - if (!iface) { - return ctx->iface; - } - - return iface; -#else - ARG_UNUSED(vlan_tag); - - return ctx->iface; -#endif -} - -#if defined(CONFIG_NET_VLAN) -static struct net_pkt *prepare_vlan_pkt(struct eth_context *ctx, - int count, uint16_t *vlan_tag, int *status) -{ - struct net_eth_vlan_hdr *hdr = (struct net_eth_vlan_hdr *)ctx->recv; - struct net_pkt *pkt; - uint8_t pos; - - if (IS_ENABLED(CONFIG_ETH_NATIVE_POSIX_VLAN_TAG_STRIP)) { - count -= NET_ETH_VLAN_HDR_SIZE; - } - - pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, count, - AF_UNSPEC, 0, NET_BUF_TIMEOUT); - if (!pkt) { - *status = -ENOMEM; - return NULL; - } - - net_pkt_set_vlan_tci(pkt, ntohs(hdr->vlan.tci)); - *vlan_tag = net_pkt_vlan_tag(pkt); - - pos = 0; - - if (IS_ENABLED(CONFIG_ETH_NATIVE_POSIX_VLAN_TAG_STRIP)) { - if (net_pkt_write(pkt, ctx->recv, - 2 * sizeof(struct net_eth_addr))) { - goto error; - } - - pos = (2 * sizeof(struct net_eth_addr)) + NET_ETH_VLAN_HDR_SIZE; - count -= (2 * sizeof(struct net_eth_addr)); - } - - if (net_pkt_write(pkt, ctx->recv + pos, count)) { - goto error; - } - -#if CONFIG_NET_TC_RX_COUNT > 1 - { - enum net_priority prio; - - prio = net_vlan2priority(net_pkt_vlan_priority(pkt)); - net_pkt_set_priority(pkt, prio); - } -#endif - - *status = 0; - - LOG_DBG("Recv pkt %p len %d", pkt, count); - - return pkt; - -error: - net_pkt_unref(pkt); - *status = -ENOBUFS; - return NULL; -} -#endif - -static struct net_pkt *prepare_non_vlan_pkt(struct eth_context *ctx, - int count, int *status) +static struct net_pkt *prepare_pkt(struct eth_context *ctx, + int count, int *status) { struct net_pkt *pkt; @@ -316,8 +221,7 @@ static struct net_pkt *prepare_non_vlan_pkt(struct eth_context *ctx, static int read_data(struct eth_context *ctx, int fd) { - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; - struct net_if *iface; + struct net_if *iface = ctx->iface; struct net_pkt *pkt = NULL; int status; int count; @@ -327,34 +231,10 @@ static int read_data(struct eth_context *ctx, int fd) return 0; } -#if defined(CONFIG_NET_VLAN) - { - struct net_eth_hdr *hdr = (struct net_eth_hdr *)(ctx->recv); - - if (ntohs(hdr->type) == NET_ETH_PTYPE_VLAN) { - pkt = prepare_vlan_pkt(ctx, count, &vlan_tag, &status); - if (!pkt) { - return status; - } - } else { - pkt = prepare_non_vlan_pkt(ctx, count, &status); - if (!pkt) { - return status; - } - - net_pkt_set_vlan_tci(pkt, 0); - } - } -#else - { - pkt = prepare_non_vlan_pkt(ctx, count, &status); - if (!pkt) { - return status; - } + pkt = prepare_pkt(ctx, count, &status); + if (!pkt) { + return status; } -#endif - - iface = get_iface(ctx, vlan_tag); update_gptp(iface, pkt, false); @@ -414,12 +294,7 @@ static void eth_iface_init(struct net_if *iface) struct eth_context *ctx = net_if_get_device(iface)->data; struct net_linkaddr *ll_addr = eth_get_mac(ctx); - /* The iface pointer in context should contain the main interface - * if the VLANs are enabled. - */ - if (ctx->iface == NULL) { - ctx->iface = iface; - } + ctx->iface = iface; ethernet_init(iface); From f9b8608d2b682ebdb51eb19bd8b8de72db8eb7a6 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 22:26:18 +0200 Subject: [PATCH 1573/2402] drivers: ethernet: stm32: Remove VLAN code as it is no longer needed The VLAN packets are prepared in Ethernet L2 so no need to have special handling in the driver. Signed-off-by: Jukka Rissanen --- drivers/ethernet/eth_stm32_hal.c | 80 +++++--------------------------- 1 file changed, 11 insertions(+), 69 deletions(-) diff --git a/drivers/ethernet/eth_stm32_hal.c b/drivers/ethernet/eth_stm32_hal.c index fcea86e4049..10391a5458e 100644 --- a/drivers/ethernet/eth_stm32_hal.c +++ b/drivers/ethernet/eth_stm32_hal.c @@ -271,23 +271,8 @@ static inline void setup_mac_filter(ETH_HandleTypeDef *heth) #if defined(CONFIG_PTP_CLOCK_STM32_HAL) static bool eth_is_ptp_pkt(struct net_if *iface, struct net_pkt *pkt) { -#if defined(CONFIG_NET_VLAN) - struct net_eth_vlan_hdr *hdr_vlan; - struct ethernet_context *eth_ctx; - - eth_ctx = net_if_l2_data(iface); - if (net_eth_is_vlan_enabled(eth_ctx, iface)) { - hdr_vlan = (struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt); - - if (ntohs(hdr_vlan->type) != NET_ETH_PTYPE_PTP) { - return false; - } - } else -#endif - { - if (ntohs(NET_ETH_HDR(pkt)->type) != NET_ETH_PTYPE_PTP) { - return false; - } + if (ntohs(NET_ETH_HDR(pkt)->type) != NET_ETH_PTYPE_PTP) { + return false; } net_pkt_set_priority(pkt, NET_PRIORITY_CA); @@ -590,26 +575,12 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt) return res; } -static struct net_if *get_iface(struct eth_stm32_hal_dev_data *ctx, - uint16_t vlan_tag) +static struct net_if *get_iface(struct eth_stm32_hal_dev_data *ctx) { -#if defined(CONFIG_NET_VLAN) - struct net_if *iface; - - iface = net_eth_get_vlan_iface(ctx->iface, vlan_tag); - if (!iface) { - return ctx->iface; - } - - return iface; -#else - ARG_UNUSED(vlan_tag); - return ctx->iface; -#endif } -static struct net_pkt *eth_rx(const struct device *dev, uint16_t *vlan_tag) +static struct net_pkt *eth_rx(const struct device *dev) { struct eth_stm32_hal_dev_data *dev_data; ETH_HandleTypeDef *heth; @@ -740,7 +711,7 @@ static struct net_pkt *eth_rx(const struct device *dev, uint16_t *vlan_tag) #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */ #endif /* CONFIG_PTP_CLOCK_STM32_HAL */ - pkt = net_pkt_rx_alloc_with_buffer(get_iface(dev_data, *vlan_tag), + pkt = net_pkt_rx_alloc_with_buffer(get_iface(dev_data), total_len, AF_UNSPEC, 0, K_MSEC(100)); if (!pkt) { LOG_ERR("Failed to obtain RX buffer"); @@ -810,29 +781,8 @@ static struct net_pkt *eth_rx(const struct device *dev, uint16_t *vlan_tag) goto out; } -#if defined(CONFIG_NET_VLAN) - struct net_eth_hdr *hdr = NET_ETH_HDR(pkt); - - if (ntohs(hdr->type) == NET_ETH_PTYPE_VLAN) { - struct net_eth_vlan_hdr *hdr_vlan = - (struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt); - - net_pkt_set_vlan_tci(pkt, ntohs(hdr_vlan->vlan.tci)); - *vlan_tag = net_pkt_vlan_tag(pkt); - -#if CONFIG_NET_TC_RX_COUNT > 1 - enum net_priority prio; - - prio = net_vlan2priority(net_pkt_vlan_priority(pkt)); - net_pkt_set_priority(pkt, prio); -#endif - } else { - net_pkt_set_iface(pkt, dev_data->iface); - } -#endif /* CONFIG_NET_VLAN */ - #if defined(CONFIG_PTP_CLOCK_STM32_HAL) - if (eth_is_ptp_pkt(get_iface(dev_data, *vlan_tag), pkt)) { + if (eth_is_ptp_pkt(get_iface(dev_data), pkt)) { pkt->timestamp.second = timestamp.second; pkt->timestamp.nanosecond = timestamp.nanosecond; } else { @@ -844,7 +794,7 @@ static struct net_pkt *eth_rx(const struct device *dev, uint16_t *vlan_tag) out: if (!pkt) { - eth_stats_update_errors_rx(get_iface(dev_data, *vlan_tag)); + eth_stats_update_errors_rx(get_iface(dev_data)); } return pkt; @@ -852,7 +802,6 @@ static struct net_pkt *eth_rx(const struct device *dev, uint16_t *vlan_tag) static void rx_thread(void *arg1, void *unused1, void *unused2) { - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; const struct device *dev; struct eth_stm32_hal_dev_data *dev_data; struct net_if *iface; @@ -877,10 +826,9 @@ static void rx_thread(void *arg1, void *unused1, void *unused2) /* semaphore taken, update link status and receive packets */ if (dev_data->link_up != true) { dev_data->link_up = true; - net_eth_carrier_on(get_iface(dev_data, - vlan_tag)); + net_eth_carrier_on(get_iface(dev_data)); } - while ((pkt = eth_rx(dev, &vlan_tag)) != NULL) { + while ((pkt = eth_rx(dev)) != NULL) { iface = net_pkt_iface(pkt); #if defined(CONFIG_NET_DSA) iface = dsa_net_recv(iface, &pkt); @@ -903,15 +851,13 @@ static void rx_thread(void *arg1, void *unused1, void *unused2) if (dev_data->link_up != true) { dev_data->link_up = true; net_eth_carrier_on( - get_iface(dev_data, - vlan_tag)); + get_iface(dev_data)); } } else { if (dev_data->link_up != false) { dev_data->link_up = false; net_eth_carrier_off( - get_iface(dev_data, - vlan_tag)); + get_iface(dev_data)); } } } @@ -1366,10 +1312,6 @@ static void eth_iface_init(struct net_if *iface) dev_data = dev->data; __ASSERT_NO_MSG(dev_data != NULL); - /* For VLAN, this value is only used to get the correct L2 driver. - * The iface pointer in context should contain the main interface - * if the VLANs are enabled. - */ if (dev_data->iface == NULL) { dev_data->iface = iface; is_first_init = true; From 898a0d8ab82d12fe47d46201b7a49194f829f09c Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 22:32:07 +0200 Subject: [PATCH 1574/2402] drivers: ethernet: sam_gmac: Remove VLAN code as it is no longer needed The VLAN packets are prepared in Ethernet L2 so no need to have special handling in the driver. Signed-off-by: Jukka Rissanen --- drivers/ethernet/eth_sam_gmac.c | 115 +++++--------------------------- 1 file changed, 16 insertions(+), 99 deletions(-) diff --git a/drivers/ethernet/eth_sam_gmac.c b/drivers/ethernet/eth_sam_gmac.c index 1b559a9e0dc..11db700b591 100644 --- a/drivers/ethernet/eth_sam_gmac.c +++ b/drivers/ethernet/eth_sam_gmac.c @@ -541,36 +541,17 @@ static struct gptp_hdr *check_gptp_msg(struct net_if *iface, bool is_tx) { uint8_t *msg_start = net_pkt_data(pkt); - struct ethernet_context *eth_ctx; struct gptp_hdr *gptp_hdr; int eth_hlen; + struct net_eth_hdr *hdr; -#if defined(CONFIG_NET_VLAN) - eth_ctx = net_if_l2_data(iface); - if (net_eth_is_vlan_enabled(eth_ctx, iface)) { - struct net_eth_vlan_hdr *hdr_vlan; - - hdr_vlan = (struct net_eth_vlan_hdr *)msg_start; - if (ntohs(hdr_vlan->type) != NET_ETH_PTYPE_PTP) { - return NULL; - } - - eth_hlen = sizeof(struct net_eth_vlan_hdr); - } else -#else - ARG_UNUSED(eth_ctx); -#endif - { - struct net_eth_hdr *hdr; - - hdr = (struct net_eth_hdr *)msg_start; - if (ntohs(hdr->type) != NET_ETH_PTYPE_PTP) { - return NULL; - } - - eth_hlen = sizeof(struct net_eth_hdr); + hdr = (struct net_eth_hdr *)msg_start; + if (ntohs(hdr->type) != NET_ETH_PTYPE_PTP) { + return NULL; } + eth_hlen = sizeof(struct net_eth_hdr); + /* In TX, the first net_buf contains the Ethernet header * and the actual gPTP header is in the second net_buf. * In RX, the Ethernet header + other headers are in the @@ -706,23 +687,9 @@ static inline void timestamp_rx_pkt(Gmac *gmac, struct gptp_hdr *hdr, #endif -static inline struct net_if *get_iface(struct eth_sam_dev_data *ctx, - uint16_t vlan_tag) +static inline struct net_if *get_iface(struct eth_sam_dev_data *ctx) { -#if defined(CONFIG_NET_VLAN) - struct net_if *iface; - - iface = net_eth_get_vlan_iface(ctx->iface, vlan_tag); - if (!iface) { - return ctx->iface; - } - - return iface; -#else - ARG_UNUSED(vlan_tag); - return ctx->iface; -#endif } /* @@ -738,7 +705,6 @@ static void tx_completed(Gmac *gmac, struct gmac_queue *queue) struct net_buf *frag; #if defined(CONFIG_NET_GPTP) struct net_pkt *pkt; - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; struct gptp_hdr *hdr; struct eth_sam_dev_data *dev_data = CONTAINER_OF(queue, struct eth_sam_dev_data, @@ -763,15 +729,9 @@ static void tx_completed(Gmac *gmac, struct gmac_queue *queue) #if defined(CONFIG_PTP_CLOCK_SAM_GMAC) /* Release net packet to the packet pool */ pkt = UINT_TO_POINTER(ring_buf_get(&queue->tx_frames)); -#if defined(CONFIG_NET_VLAN) - struct net_eth_hdr *eth_hdr = NET_ETH_HDR(pkt); - if (ntohs(eth_hdr->type) == NET_ETH_PTYPE_VLAN) { - vlan_tag = net_pkt_vlan_tag(pkt); - } -#endif #if defined(CONFIG_NET_GPTP) - hdr = check_gptp_msg(get_iface(dev_data, vlan_tag), + hdr = check_gptp_msg(get_iface(dev_data), pkt, true); timestamp_tx_pkt(gmac, hdr, pkt); @@ -1375,7 +1335,6 @@ static void eth_rx(struct gmac_queue *queue) struct eth_sam_dev_data *dev_data = CONTAINER_OF(queue, struct eth_sam_dev_data, queue_list[queue->que_idx]); - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; struct net_pkt *rx_frame; #if defined(CONFIG_NET_GPTP) const struct device *const dev = net_if_get_device(dev_data->iface); @@ -1391,37 +1350,8 @@ static void eth_rx(struct gmac_queue *queue) while (rx_frame) { LOG_DBG("ETH rx"); -#if defined(CONFIG_NET_VLAN) - /* FIXME: Instead of this, use the GMAC register to get - * the used VLAN tag. - */ - { - struct net_eth_hdr *p_hdr = NET_ETH_HDR(rx_frame); - - if (ntohs(p_hdr->type) == NET_ETH_PTYPE_VLAN) { - struct net_eth_vlan_hdr *hdr_vlan = - (struct net_eth_vlan_hdr *) - NET_ETH_HDR(rx_frame); - - net_pkt_set_vlan_tci(rx_frame, - ntohs(hdr_vlan->vlan.tci)); - vlan_tag = net_pkt_vlan_tag(rx_frame); - -#if CONFIG_NET_TC_RX_COUNT > 1 - { - enum net_priority prio; - - prio = net_vlan2priority( - net_pkt_vlan_priority(rx_frame)); - net_pkt_set_priority(rx_frame, prio); - } -#endif - } - } -#endif #if defined(CONFIG_NET_GPTP) - hdr = check_gptp_msg(get_iface(dev_data, vlan_tag), rx_frame, - false); + hdr = check_gptp_msg(get_iface(dev_data), rx_frame, false); timestamp_rx_pkt(gmac, hdr, rx_frame); @@ -1430,10 +1360,8 @@ static void eth_rx(struct gmac_queue *queue) } #endif /* CONFIG_NET_GPTP */ - if (net_recv_data(get_iface(dev_data, vlan_tag), - rx_frame) < 0) { - eth_stats_update_errors_rx(get_iface(dev_data, - vlan_tag)); + if (net_recv_data(get_iface(dev_data), rx_frame) < 0) { + eth_stats_update_errors_rx(get_iface(dev_data)); net_pkt_unref(rx_frame); } @@ -1490,11 +1418,7 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt) uint8_t pkt_prio; #if GMAC_MULTIPLE_TX_PACKETS == 0 #if defined(CONFIG_NET_GPTP) - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; struct gptp_hdr *hdr; -#if defined(CONFIG_NET_VLAN) - struct net_eth_hdr *eth_hdr; -#endif #endif #endif @@ -1635,14 +1559,8 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt) return -EIO; } #if defined(CONFIG_NET_GPTP) -#if defined(CONFIG_NET_VLAN) - eth_hdr = NET_ETH_HDR(pkt); - if (ntohs(eth_hdr->type) == NET_ETH_PTYPE_VLAN) { - vlan_tag = net_pkt_vlan_tag(pkt); - } -#endif #if defined(CONFIG_NET_GPTP) - hdr = check_gptp_msg(get_iface(dev_data, vlan_tag), pkt, true); + hdr = check_gptp_msg(get_iface(dev_data), pkt, true); timestamp_tx_pkt(gmac, hdr, pkt); if (hdr && need_timestamping(hdr)) { net_if_add_tx_timestamp(pkt); @@ -1884,10 +1802,6 @@ static void eth0_iface_init(struct net_if *iface) int result; int i; - /* For VLAN, this value is only used to get the correct L2 driver. - * The iface pointer in context should contain the main interface - * if the VLANs are enabled. - */ if (dev_data->iface == NULL) { dev_data->iface = iface; } @@ -1999,7 +1913,10 @@ static enum ethernet_hw_caps eth_sam_gmac_get_capabilities(const struct device * { ARG_UNUSED(dev); - return ETHERNET_HW_VLAN | ETHERNET_LINK_10BASE_T | + return ETHERNET_LINK_10BASE_T | +#if defined(CONFIG_NET_VLAN) + ETHERNET_HW_VLAN | +#endif #if defined(CONFIG_PTP_CLOCK_SAM_GMAC) ETHERNET_PTP | #endif From e45a8c9104e6f970bc19135391198e3ceee02e63 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 22:35:20 +0200 Subject: [PATCH 1575/2402] drivers: ethernet: enc28j60: Remove VLAN code as it is no longer needed The VLAN packets are prepared in Ethernet L2 so no need to have special handling in the driver. Signed-off-by: Jukka Rissanen --- drivers/ethernet/eth_enc28j60.c | 55 +++++---------------------------- 1 file changed, 7 insertions(+), 48 deletions(-) diff --git a/drivers/ethernet/eth_enc28j60.c b/drivers/ethernet/eth_enc28j60.c index d4b4f08fbc1..979910f759a 100644 --- a/drivers/ethernet/eth_enc28j60.c +++ b/drivers/ethernet/eth_enc28j60.c @@ -457,23 +457,9 @@ static void eth_enc28j60_init_phy(const struct device *dev) } } -static struct net_if *get_iface(struct eth_enc28j60_runtime *ctx, - uint16_t vlan_tag) +static struct net_if *get_iface(struct eth_enc28j60_runtime *ctx) { -#if defined(CONFIG_NET_VLAN) - struct net_if *iface; - - iface = net_eth_get_vlan_iface(ctx->iface, vlan_tag); - if (!iface) { - return ctx->iface; - } - - return iface; -#else - ARG_UNUSED(vlan_tag); - return ctx->iface; -#endif } static int eth_enc28j60_tx(const struct device *dev, struct net_pkt *pkt) @@ -549,8 +535,7 @@ static int eth_enc28j60_tx(const struct device *dev, struct net_pkt *pkt) return 0; } -static void enc28j60_read_packet(const struct device *dev, uint16_t *vlan_tag, - uint16_t frm_len) +static void enc28j60_read_packet(const struct device *dev, uint16_t frm_len) { const struct eth_enc28j60_config *config = dev->config; struct eth_enc28j60_runtime *context = dev->data; @@ -560,11 +545,11 @@ static void enc28j60_read_packet(const struct device *dev, uint16_t *vlan_tag, uint8_t dummy[4]; /* Get the frame from the buffer */ - pkt = net_pkt_rx_alloc_with_buffer(get_iface(context, *vlan_tag), frm_len, + pkt = net_pkt_rx_alloc_with_buffer(get_iface(context), frm_len, AF_UNSPEC, 0, K_MSEC(config->timeout)); if (!pkt) { LOG_ERR("%s: Could not allocate rx buffer", dev->name); - eth_stats_update_errors_rx(get_iface(context, *vlan_tag)); + eth_stats_update_errors_rx(get_iface(context)); return; } @@ -606,28 +591,7 @@ static void enc28j60_read_packet(const struct device *dev, uint16_t *vlan_tag, eth_enc28j60_read_mem(dev, dummy, 1); } -#if defined(CONFIG_NET_VLAN) - struct net_eth_hdr *hdr = NET_ETH_HDR(pkt); - - if (ntohs(hdr->type) == NET_ETH_PTYPE_VLAN) { - struct net_eth_vlan_hdr *hdr_vlan = - (struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt); - - net_pkt_set_vlan_tci(pkt, ntohs(hdr_vlan->vlan.tci)); - *vlan_tag = net_pkt_vlan_tag(pkt); - -#if CONFIG_NET_TC_RX_COUNT > 1 - enum net_priority prio; - - prio = net_vlan2priority(net_pkt_vlan_priority(pkt)); - net_pkt_set_priority(pkt, prio); -#endif - } else { - net_pkt_set_iface(pkt, context->iface); - } -#else /* CONFIG_NET_VLAN */ net_pkt_set_iface(pkt, context->iface); -#endif /* CONFIG_NET_VLAN */ /* Feed buffer frame to IP stack */ LOG_DBG("%s: Received packet of length %u", dev->name, lengthfr); @@ -636,7 +600,7 @@ static void enc28j60_read_packet(const struct device *dev, uint16_t *vlan_tag, } } -static int eth_enc28j60_rx(const struct device *dev, uint16_t *vlan_tag) +static int eth_enc28j60_rx(const struct device *dev) { struct eth_enc28j60_runtime *context = dev->data; uint8_t counter; @@ -688,7 +652,7 @@ static int eth_enc28j60_rx(const struct device *dev, uint16_t *vlan_tag) */ frm_len = sys_get_le16(info) - 4; - enc28j60_read_packet(dev, vlan_tag, frm_len); + enc28j60_read_packet(dev, frm_len); /* Free buffer memory and decrement rx counter */ eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXRDPTL); @@ -716,7 +680,6 @@ static void eth_enc28j60_rx_thread(void *p1, void *p2, void *p3) const struct device *dev = p1; struct eth_enc28j60_runtime *context = dev->data; - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; uint8_t int_stat; while (true) { @@ -724,7 +687,7 @@ static void eth_enc28j60_rx_thread(void *p1, void *p2, void *p3) eth_enc28j60_read_reg(dev, ENC28J60_REG_EIR, &int_stat); if (int_stat & ENC28J60_BIT_EIR_PKTIF) { - eth_enc28j60_rx(dev, &vlan_tag); + eth_enc28j60_rx(dev); /* Clear rx interruption flag */ eth_enc28j60_clear_eth_reg(dev, ENC28J60_REG_EIR, ENC28J60_BIT_EIR_PKTIF @@ -769,10 +732,6 @@ static void eth_enc28j60_iface_init(struct net_if *iface) sizeof(context->mac_address), NET_LINK_ETHERNET); - /* For VLAN, this value is only used to get the correct L2 driver. - * The iface pointer in context should contain the main interface - * if the VLANs are enabled. - */ if (context->iface == NULL) { context->iface = iface; } From 4e7565dceb7c4f29da71d40a1bd25d7379ea80aa Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 22:38:08 +0200 Subject: [PATCH 1576/2402] drivers: ethernet: mcux: Remove VLAN code as it is no longer needed The VLAN packets are prepared in Ethernet L2 so no need to have special handling in the driver. Signed-off-by: Jukka Rissanen --- drivers/ethernet/eth_mcux.c | 86 ++++++------------------------------- 1 file changed, 12 insertions(+), 74 deletions(-) diff --git a/drivers/ethernet/eth_mcux.c b/drivers/ethernet/eth_mcux.c index 9751ab2e44c..441c7bcdfc4 100644 --- a/drivers/ethernet/eth_mcux.c +++ b/drivers/ethernet/eth_mcux.c @@ -161,10 +161,6 @@ static const char *eth_name(ENET_Type *base) struct eth_context { ENET_Type *base; void (*config_func)(void); - /* If VLAN is enabled, there can be multiple VLAN interfaces related to - * this physical device. In that case, this pointer value is not really - * used for anything. - */ struct net_if *iface; #if defined(CONFIG_NET_POWER_MANAGEMENT) clock_ip_name_t clock; @@ -336,22 +332,9 @@ static void eth_mcux_decode_duplex_and_speed(uint32_t status, } #endif /* ETH_MCUX_FIXED_LINK */ -static inline struct net_if *get_iface(struct eth_context *ctx, uint16_t vlan_tag) +static inline struct net_if *get_iface(struct eth_context *ctx) { -#if defined(CONFIG_NET_VLAN) - struct net_if *iface; - - iface = net_eth_get_vlan_iface(ctx->iface, vlan_tag); - if (!iface) { - return ctx->iface; - } - - return iface; -#else - ARG_UNUSED(vlan_tag); - return ctx->iface; -#endif } static void eth_mcux_phy_enter_reset(struct eth_context *context) @@ -672,31 +655,12 @@ static bool eth_get_ptp_data(struct net_if *iface, struct net_pkt *pkt) { int eth_hlen; -#if defined(CONFIG_NET_VLAN) - struct net_eth_vlan_hdr *hdr_vlan; - struct ethernet_context *eth_ctx; - bool vlan_enabled = false; - - eth_ctx = net_if_l2_data(iface); - if (net_eth_is_vlan_enabled(eth_ctx, iface)) { - hdr_vlan = (struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt); - vlan_enabled = true; - - if (ntohs(hdr_vlan->type) != NET_ETH_PTYPE_PTP) { - return false; - } - - eth_hlen = sizeof(struct net_eth_vlan_hdr); - } else -#endif - { - if (ntohs(NET_ETH_HDR(pkt)->type) != NET_ETH_PTYPE_PTP) { - return false; - } - - eth_hlen = sizeof(struct net_eth_hdr); + if (ntohs(NET_ETH_HDR(pkt)->type) != NET_ETH_PTYPE_PTP) { + return false; } + eth_hlen = sizeof(struct net_eth_hdr); + net_pkt_set_priority(pkt, NET_PRIORITY_CA); return true; @@ -762,7 +726,6 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt) static int eth_rx(struct eth_context *context) { - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; uint32_t frame_length = 0U; struct net_if *iface; struct net_pkt *pkt; @@ -823,36 +786,12 @@ static int eth_rx(struct eth_context *context) k_mutex_unlock(&context->rx_frame_buf_mutex); -#if defined(CONFIG_NET_VLAN) - { - struct net_eth_hdr *hdr = NET_ETH_HDR(pkt); - - if (ntohs(hdr->type) == NET_ETH_PTYPE_VLAN) { - struct net_eth_vlan_hdr *hdr_vlan = - (struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt); - - net_pkt_set_vlan_tci(pkt, ntohs(hdr_vlan->vlan.tci)); - vlan_tag = net_pkt_vlan_tag(pkt); - -#if CONFIG_NET_TC_RX_COUNT > 1 - { - enum net_priority prio; - - prio = net_vlan2priority( - net_pkt_vlan_priority(pkt)); - net_pkt_set_priority(pkt, prio); - } -#endif - } - } -#endif /* CONFIG_NET_VLAN */ - /* * Use MAC timestamp */ #if defined(CONFIG_PTP_CLOCK_MCUX) k_mutex_lock(&context->ptp_mutex, K_FOREVER); - if (eth_get_ptp_data(get_iface(context, vlan_tag), pkt)) { + if (eth_get_ptp_data(get_iface(context), pkt)) { ENET_Ptp1588GetTimer(context->base, &context->enet_handle, &ptpTimeData); /* If latest timestamp reloads after getting from Rx BD, @@ -873,7 +812,7 @@ static int eth_rx(struct eth_context *context) k_mutex_unlock(&context->ptp_mutex); #endif /* CONFIG_PTP_CLOCK_MCUX */ - iface = get_iface(context, vlan_tag); + iface = get_iface(context); #if defined(CONFIG_NET_DSA) iface = dsa_net_recv(iface, &pkt); #endif @@ -892,7 +831,7 @@ static int eth_rx(struct eth_context *context) 0, RING_ID, NULL); __ASSERT_NO_MSG(status == kStatus_Success); error: - eth_stats_update_errors_rx(get_iface(context, vlan_tag)); + eth_stats_update_errors_rx(get_iface(context)); return -EIO; } @@ -1174,10 +1113,6 @@ static void eth_iface_init(struct net_if *iface) sizeof(context->mac_addr), NET_LINK_ETHERNET); - /* For VLAN, this value is only used to get the correct L2 driver. - * The iface pointer in context should contain the main interface - * if the VLANs are enabled. - */ if (context->iface == NULL) { context->iface = iface; } @@ -1195,8 +1130,11 @@ static enum ethernet_hw_caps eth_mcux_get_capabilities(const struct device *dev) { ARG_UNUSED(dev); - return ETHERNET_HW_VLAN | ETHERNET_LINK_10BASE_T | + return ETHERNET_LINK_10BASE_T | ETHERNET_HW_FILTERING | +#if defined(CONFIG_NET_VLAN) + ETHERNET_HW_VLAN | +#endif #if defined(CONFIG_PTP_CLOCK_MCUX) ETHERNET_PTP | #endif From 813af655c5122ced73aafccc3f147909a7f0fe4e Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 22:40:10 +0200 Subject: [PATCH 1577/2402] drivers: ethernet: nxp_s32_gmac: Remove VLAN code as it is no longer needed The VLAN packets are prepared in Ethernet L2 so no need to have special handling in the driver. Signed-off-by: Jukka Rissanen --- drivers/ethernet/eth_nxp_s32_gmac.c | 52 ++++------------------------- 1 file changed, 6 insertions(+), 46 deletions(-) diff --git a/drivers/ethernet/eth_nxp_s32_gmac.c b/drivers/ethernet/eth_nxp_s32_gmac.c index a64d6c380b4..8579992fc3d 100644 --- a/drivers/ethernet/eth_nxp_s32_gmac.c +++ b/drivers/ethernet/eth_nxp_s32_gmac.c @@ -63,22 +63,9 @@ struct eth_nxp_s32_data { static void eth_nxp_s32_rx_thread(void *arg1, void *unused1, void *unused2); -static inline struct net_if *get_iface(struct eth_nxp_s32_data *ctx, uint16_t vlan_tag) +static inline struct net_if *get_iface(struct eth_nxp_s32_data *ctx) { -#if defined(CONFIG_NET_VLAN) - struct net_if *iface; - - iface = net_eth_get_vlan_iface(ctx->iface, vlan_tag); - if (!iface) { - return ctx->iface; - } - - return iface; -#else - ARG_UNUSED(vlan_tag); - return ctx->iface; -#endif } static void convert_phy_to_mac_config(Gmac_Ip_ConfigType *gmac_cfg, enum phy_link_speed phy_speed) @@ -302,10 +289,6 @@ static void eth_nxp_s32_iface_init(struct net_if *iface) const struct eth_nxp_s32_config *cfg = dev->config; struct eth_nxp_s32_data *ctx = dev->data; - /* For VLAN, this value is only used to get the correct L2 driver. - * The iface pointer in context should contain the main interface - * if the VLANs are enabled. - */ if (ctx->iface == NULL) { ctx->iface = iface; } @@ -416,19 +399,11 @@ static int eth_nxp_s32_tx(const struct device *dev, struct net_pkt *pkt) static struct net_pkt *eth_nxp_s32_get_pkt(const struct device *dev, Gmac_Ip_BufferType *buf, - Gmac_Ip_RxInfoType *rx_info, - uint16_t *vlan_tag) + Gmac_Ip_RxInfoType *rx_info) { struct eth_nxp_s32_data *ctx = dev->data; struct net_pkt *pkt = NULL; int res = 0; -#if defined(CONFIG_NET_VLAN) - struct net_eth_hdr *hdr; - struct net_eth_vlan_hdr *hdr_vlan; -#if CONFIG_NET_TC_RX_COUNT > 1 - enum net_priority prio; -#endif /* CONFIG_NET_TC_RX_COUNT > 1 */ -#endif /* CONFIG_NET_VLAN */ /* Using root iface, it will be updated in net_recv_data() */ pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, rx_info->PktLen, @@ -446,23 +421,9 @@ static struct net_pkt *eth_nxp_s32_get_pkt(const struct device *dev, goto exit; } -#if defined(CONFIG_NET_VLAN) - hdr = NET_ETH_HDR(pkt); - if (ntohs(hdr->type) == NET_ETH_PTYPE_VLAN) { - hdr_vlan = (struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt); - net_pkt_set_vlan_tci(pkt, ntohs(hdr_vlan->vlan.tci)); - *vlan_tag = net_pkt_vlan_tag(pkt); - -#if CONFIG_NET_TC_RX_COUNT > 1 - prio = net_vlan2priority(net_pkt_vlan_priority(pkt)); - net_pkt_set_priority(pkt, prio); -#endif /* CONFIG_NET_TC_RX_COUNT > 1 */ - } -#endif /* CONFIG_NET_VLAN */ - exit: if (!pkt) { - eth_stats_update_errors_rx(get_iface(ctx, *vlan_tag)); + eth_stats_update_errors_rx(get_iface(ctx)); } return pkt; @@ -472,7 +433,6 @@ static void eth_nxp_s32_rx(const struct device *dev) { struct eth_nxp_s32_data *ctx = dev->data; const struct eth_nxp_s32_config *cfg = dev->config; - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; struct net_pkt *pkt; int res = 0; Gmac_Ip_RxInfoType rx_info = {0}; @@ -484,12 +444,12 @@ static void eth_nxp_s32_rx(const struct device *dev) Gmac_Ip_ProvideRxBuff(cfg->instance, cfg->rx_ring_idx, &buf); LOG_ERR("Rx frame has errors (error mask 0x%X)", rx_info.ErrMask); } else if (status == GMAC_STATUS_SUCCESS) { - pkt = eth_nxp_s32_get_pkt(dev, &buf, &rx_info, &vlan_tag); + pkt = eth_nxp_s32_get_pkt(dev, &buf, &rx_info); Gmac_Ip_ProvideRxBuff(cfg->instance, cfg->rx_ring_idx, &buf); if (pkt != NULL) { - res = net_recv_data(get_iface(ctx, vlan_tag), pkt); + res = net_recv_data(get_iface(ctx), pkt); if (res < 0) { - eth_stats_update_errors_rx(get_iface(ctx, vlan_tag)); + eth_stats_update_errors_rx(get_iface(ctx)); net_pkt_unref(pkt); LOG_ERR("Failed to enqueue frame into rx queue (%d)", res); } From bcb34705bbc12933b6dde76e148db3ad5e8485cb Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 22:44:05 +0200 Subject: [PATCH 1578/2402] drivers: ethernet: nxp_enet: Remove VLAN code as it is no longer needed The VLAN packets are prepared in Ethernet L2 so no need to have special handling in the driver. Signed-off-by: Jukka Rissanen --- drivers/ethernet/eth_nxp_enet.c | 35 +++++++++------------------------ 1 file changed, 9 insertions(+), 26 deletions(-) diff --git a/drivers/ethernet/eth_nxp_enet.c b/drivers/ethernet/eth_nxp_enet.c index 0679e377467..6659c4f92a5 100644 --- a/drivers/ethernet/eth_nxp_enet.c +++ b/drivers/ethernet/eth_nxp_enet.c @@ -117,11 +117,9 @@ struct nxp_enet_mac_data { ******************** */ -static inline struct net_if *get_iface(struct nxp_enet_mac_data *data, uint16_t vlan_tag) +static inline struct net_if *get_iface(struct nxp_enet_mac_data *data) { - struct net_if *iface = net_eth_get_vlan_iface(data->iface, vlan_tag); - - return iface ? iface : data->iface; + return data->iface; } #if defined(CONFIG_PTP_CLOCK_NXP_ENET) @@ -248,10 +246,6 @@ static void eth_nxp_enet_iface_init(struct net_if *iface) sizeof(data->mac_addr), NET_LINK_ETHERNET); - /* For VLAN, this value is only used to get the correct L2 driver. - * The iface pointer in context should contain the main interface - * if the VLANs are enabled. - */ if (data->iface == NULL) { data->iface = iface; } @@ -270,8 +264,11 @@ static enum ethernet_hw_caps eth_nxp_enet_get_capabilities(const struct device * { ARG_UNUSED(dev); - return ETHERNET_HW_VLAN | ETHERNET_LINK_10BASE_T | + return ETHERNET_LINK_10BASE_T | ETHERNET_HW_FILTERING | +#if defined(CONFIG_NET_VLAN) + ETHERNET_HW_VLAN | +#endif #if defined(CONFIG_PTP_CLOCK_NXP_ENET) ETHERNET_PTP | #endif @@ -334,7 +331,6 @@ static int eth_nxp_enet_rx(const struct device *dev) { const struct nxp_enet_mac_config *config = dev->config; struct nxp_enet_mac_data *data = dev->data; - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; uint32_t frame_length = 0U; struct net_if *iface; struct net_pkt *pkt = NULL; @@ -382,19 +378,6 @@ static int eth_nxp_enet_rx(const struct device *dev) goto error; } - if (IS_ENABLED(CONFIG_NET_VLAN) && ntohs(NET_ETH_HDR(pkt)->type) == NET_ETH_PTYPE_VLAN) { - struct net_eth_vlan_hdr *hdr_vlan = (struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt); - - net_pkt_set_vlan_tci(pkt, ntohs(hdr_vlan->vlan.tci)); - vlan_tag = net_pkt_vlan_tag(pkt); - -#if CONFIG_NET_TC_RX_COUNT > 1 - enum net_priority prio = net_vlan2priority(net_pkt_vlan_priority(pkt)); - - net_pkt_set_priority(pkt, prio); -#endif /* CONFIG_NET_TC_RX_COUNT > 1 */ - } - #if defined(CONFIG_PTP_CLOCK_NXP_ENET) k_mutex_lock(data->ptp_mutex, K_FOREVER); @@ -403,7 +386,7 @@ static int eth_nxp_enet_rx(const struct device *dev) pkt->timestamp.second = UINT64_MAX; /* Timestamp the packet using PTP clock */ - if (eth_get_ptp_data(get_iface(data, vlan_tag), pkt)) { + if (eth_get_ptp_data(get_iface(data), pkt)) { struct net_ptp_time ptp_time; ptp_clock_get(config->ptp_clock, &ptp_time); @@ -421,7 +404,7 @@ static int eth_nxp_enet_rx(const struct device *dev) k_mutex_unlock(data->ptp_mutex); #endif /* CONFIG_PTP_CLOCK_NXP_ENET */ - iface = get_iface(data, vlan_tag); + iface = get_iface(data); #if defined(CONFIG_NET_DSA) iface = dsa_net_recv(iface, &pkt); #endif @@ -442,7 +425,7 @@ static int eth_nxp_enet_rx(const struct device *dev) if (pkt) { net_pkt_unref(pkt); } - eth_stats_update_errors_rx(get_iface(data, vlan_tag)); + eth_stats_update_errors_rx(get_iface(data)); return -EIO; } From c5dc6542fdc5fa1de45bcbb15aef99001e1ecb34 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 22:46:13 +0200 Subject: [PATCH 1579/2402] drivers: ethernet: xmc4xxx: Remove VLAN code as it is no longer needed The VLAN packets are prepared in Ethernet L2 so no need to have special handling in the driver. Signed-off-by: Jukka Rissanen --- drivers/ethernet/eth_xmc4xxx.c | 37 +++------------------------------- 1 file changed, 3 insertions(+), 34 deletions(-) diff --git a/drivers/ethernet/eth_xmc4xxx.c b/drivers/ethernet/eth_xmc4xxx.c index ad2cee470f2..21a1752c316 100644 --- a/drivers/ethernet/eth_xmc4xxx.c +++ b/drivers/ethernet/eth_xmc4xxx.c @@ -129,22 +129,9 @@ K_MEM_SLAB_DEFINE_STATIC(tx_frame_slab, sizeof(struct eth_xmc4xxx_tx_frame), static XMC_ETH_MAC_DMA_DESC_t __aligned(4) tx_dma_desc[NUM_TX_DMA_DESCRIPTORS]; static XMC_ETH_MAC_DMA_DESC_t __aligned(4) rx_dma_desc[NUM_RX_DMA_DESCRIPTORS]; -static inline struct net_if *get_iface(struct eth_xmc4xxx_data *ctx, uint16_t vlan_tag) +static inline struct net_if *get_iface(struct eth_xmc4xxx_data *ctx) { -#if defined(CONFIG_NET_VLAN) - struct net_if *iface; - - iface = net_eth_get_vlan_iface(ctx->iface, vlan_tag); - if (!iface) { - return ctx->iface; - } - - return iface; -#else - ARG_UNUSED(vlan_tag); - return ctx->iface; -#endif } static void eth_xmc4xxx_tx_dma_descriptors_init(const struct device *dev) @@ -494,31 +481,13 @@ static void eth_xmc4xxx_handle_rx(const struct device *dev) struct net_pkt *pkt = NULL; for (;;) { - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; - pkt = eth_xmc4xxx_rx_pkt(dev); if (!pkt) { return; } -#if defined(CONFIG_NET_VLAN) - struct net_eth_hdr *hdr = NET_ETH_HDR(pkt); - - if (ntohs(hdr->type) == NET_ETH_PTYPE_VLAN) { - struct net_eth_vlan_hdr *hdr_vlan = (struct net_eth_vlan_hdr *)hdr; - - net_pkt_set_vlan_tci(pkt, ntohs(hdr_vlan->vlan.tci)); - vlan_tag = net_pkt_vlan_tag(pkt); -#if CONFIG_NET_TC_RX_COUNT > 1 - enum net_priority prio; - - prio = net_vlan2priority(net_pkt_vlan_priority(pkt)); - net_pkt_set_priority(pkt, prio); -#endif - } -#endif /* CONFIG_NET_VLAN */ - if (net_recv_data(get_iface(dev_data, vlan_tag), pkt) < 0) { - eth_stats_update_errors_rx(get_iface(dev_data, vlan_tag)); + if (net_recv_data(get_iface(dev_data), pkt) < 0) { + eth_stats_update_errors_rx(get_iface(dev_data)); net_pkt_unref(pkt); } } From 7825ce24189a31ca69babd53973a7540f305567e Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 22:47:48 +0200 Subject: [PATCH 1580/2402] drivers: ethernet: e1000: Remove VLAN code as it is no longer needed The VLAN packets are prepared in Ethernet L2 so no need to have special handling in the driver. Signed-off-by: Jukka Rissanen --- drivers/ethernet/eth_e1000.c | 46 +++--------------------------------- 1 file changed, 3 insertions(+), 43 deletions(-) diff --git a/drivers/ethernet/eth_e1000.c b/drivers/ethernet/eth_e1000.c index 4699a6261b0..766ed79dec4 100644 --- a/drivers/ethernet/eth_e1000.c +++ b/drivers/ethernet/eth_e1000.c @@ -68,22 +68,9 @@ static const char *e1000_reg_to_string(enum e1000_reg_t r) return NULL; } -static struct net_if *get_iface(struct e1000_dev *ctx, uint16_t vlan_tag) +static struct net_if *get_iface(struct e1000_dev *ctx) { -#if defined(CONFIG_NET_VLAN) - struct net_if *iface; - - iface = net_eth_get_vlan_iface(ctx->iface, vlan_tag); - if (!iface) { - return ctx->iface; - } - - return iface; -#else - ARG_UNUSED(vlan_tag); - return ctx->iface; -#endif } static enum ethernet_hw_caps e1000_caps(const struct device *dev) @@ -187,7 +174,6 @@ static void e1000_isr(const struct device *ddev) { struct e1000_dev *dev = ddev->data; uint32_t icr = ior32(dev, ICR); /* Cleared upon read */ - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; icr &= ~(ICR_TXDW | ICR_TXQE); @@ -197,31 +183,9 @@ static void e1000_isr(const struct device *ddev) icr &= ~ICR_RXO; if (pkt) { -#if defined(CONFIG_NET_VLAN) - struct net_eth_hdr *hdr = NET_ETH_HDR(pkt); - - if (ntohs(hdr->type) == NET_ETH_PTYPE_VLAN) { - struct net_eth_vlan_hdr *hdr_vlan = - (struct net_eth_vlan_hdr *) - NET_ETH_HDR(pkt); - - net_pkt_set_vlan_tci( - pkt, ntohs(hdr_vlan->vlan.tci)); - vlan_tag = net_pkt_vlan_tag(pkt); - -#if CONFIG_NET_TC_RX_COUNT > 1 - enum net_priority prio; - - prio = net_vlan2priority( - net_pkt_vlan_priority(pkt)); - net_pkt_set_priority(pkt, prio); -#endif - } -#endif /* CONFIG_NET_VLAN */ - - net_recv_data(get_iface(dev, vlan_tag), pkt); + net_recv_data(get_iface(dev), pkt); } else { - eth_stats_update_errors_rx(get_iface(dev, vlan_tag)); + eth_stats_update_errors_rx(get_iface(dev)); } } @@ -291,10 +255,6 @@ static void e1000_iface_init(struct net_if *iface) struct e1000_dev *dev = net_if_get_device(iface)->data; const struct e1000_config *config = net_if_get_device(iface)->config; - /* For VLAN, this value is only used to get the correct L2 driver. - * The iface pointer in device context should contain the main - * interface if the VLANs are enabled. - */ if (dev->iface == NULL) { dev->iface = iface; From c4a4506b4abea90bd368481d1697d9303c7e1e56 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 19 Mar 2024 22:49:29 +0200 Subject: [PATCH 1581/2402] drivers: ethernet: nxp_s32_netc: Remove VLAN code as it is no longer needed The VLAN packets are prepared in Ethernet L2 so no need to have special handling in the driver. Signed-off-by: Jukka Rissanen --- drivers/ethernet/eth_nxp_s32_netc.c | 48 ++++------------------------- 1 file changed, 6 insertions(+), 42 deletions(-) diff --git a/drivers/ethernet/eth_nxp_s32_netc.c b/drivers/ethernet/eth_nxp_s32_netc.c index 81090646c60..852d37b4343 100644 --- a/drivers/ethernet/eth_nxp_s32_netc.c +++ b/drivers/ethernet/eth_nxp_s32_netc.c @@ -43,22 +43,9 @@ static void nxp_s32_eth_msix_wrapper(const struct device *dev, uint32_t channel, msix->handler(channel, NULL, 0); } -static inline struct net_if *get_iface(struct nxp_s32_eth_data *ctx, uint16_t vlan_tag) +static inline struct net_if *get_iface(struct nxp_s32_eth_data *ctx) { -#if defined(CONFIG_NET_VLAN) - struct net_if *iface; - - iface = net_eth_get_vlan_iface(ctx->iface, vlan_tag); - if (!iface) { - return ctx->iface; - } - - return iface; -#else - ARG_UNUSED(vlan_tag); - return ctx->iface; -#endif } int nxp_s32_eth_initialize_common(const struct device *dev) @@ -185,19 +172,11 @@ int nxp_s32_eth_tx(const struct device *dev, struct net_pkt *pkt) } static struct net_pkt *nxp_s32_eth_get_pkt(const struct device *dev, - Netc_Eth_Ip_BufferType *buf, - uint16_t *vlan_tag) + Netc_Eth_Ip_BufferType *buf) { struct nxp_s32_eth_data *ctx = dev->data; struct net_pkt *pkt = NULL; int res = 0; -#if defined(CONFIG_NET_VLAN) - struct net_eth_hdr *hdr; - struct net_eth_vlan_hdr *hdr_vlan; -#if CONFIG_NET_TC_RX_COUNT > 1 - enum net_priority prio; -#endif -#endif /* CONFIG_NET_VLAN */ /* Use root iface, it will be updated later in net_recv_data() */ pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, buf->length, @@ -213,23 +192,9 @@ static struct net_pkt *nxp_s32_eth_get_pkt(const struct device *dev, goto exit; } -#if defined(CONFIG_NET_VLAN) - hdr = NET_ETH_HDR(pkt); - if (ntohs(hdr->type) == NET_ETH_PTYPE_VLAN) { - hdr_vlan = (struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt); - net_pkt_set_vlan_tci(pkt, ntohs(hdr_vlan->vlan.tci)); - *vlan_tag = net_pkt_vlan_tag(pkt); - -#if CONFIG_NET_TC_RX_COUNT > 1 - prio = net_vlan2priority(net_pkt_vlan_priority(pkt)); - net_pkt_set_priority(pkt, prio); -#endif - } -#endif /* CONFIG_NET_VLAN */ - exit: if (!pkt) { - eth_stats_update_errors_rx(get_iface(ctx, *vlan_tag)); + eth_stats_update_errors_rx(get_iface(ctx)); } return pkt; @@ -242,7 +207,6 @@ static int nxp_s32_eth_rx(const struct device *dev) Netc_Eth_Ip_BufferType buf; Netc_Eth_Ip_RxInfoType info; Netc_Eth_Ip_StatusType status; - uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC; struct net_pkt *pkt; int key; int res = 0; @@ -255,13 +219,13 @@ static int nxp_s32_eth_rx(const struct device *dev) LOG_ERR("Error on received frame: %d (0x%X)", status, info.rxStatus); res = -EIO; } else { - pkt = nxp_s32_eth_get_pkt(dev, &buf, &vlan_tag); + pkt = nxp_s32_eth_get_pkt(dev, &buf); Netc_Eth_Ip_ProvideRxBuff(cfg->si_idx, cfg->rx_ring_idx, &buf); if (pkt != NULL) { - res = net_recv_data(get_iface(ctx, vlan_tag), pkt); + res = net_recv_data(get_iface(ctx), pkt); if (res < 0) { - eth_stats_update_errors_rx(get_iface(ctx, vlan_tag)); + eth_stats_update_errors_rx(get_iface(ctx)); net_pkt_unref(pkt); LOG_ERR("Failed to enqueue frame into rx queue: %d", res); } From 55cbe530dfee336467e52f819ad7c006b03655e6 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 17 Mar 2024 18:40:13 +0200 Subject: [PATCH 1582/2402] samples: net: echo_server: Rework the VLAN support Rework the code to support VLAN properly. Signed-off-by: Jukka Rissanen --- .../net/sockets/echo_server/overlay-vlan.conf | 9 +++-- samples/net/sockets/echo_server/src/vlan.c | 36 +++++++++---------- 2 files changed, 25 insertions(+), 20 deletions(-) diff --git a/samples/net/sockets/echo_server/overlay-vlan.conf b/samples/net/sockets/echo_server/overlay-vlan.conf index 13eaf5373f3..8467c436e27 100644 --- a/samples/net/sockets/echo_server/overlay-vlan.conf +++ b/samples/net/sockets/echo_server/overlay-vlan.conf @@ -1,9 +1,14 @@ CONFIG_NET_VLAN=y +# Allow useful interface assigned to VLAN interface +CONFIG_NET_INTERFACE_NAME_LEN=15 + # We have one non-vlan interface and two VLAN interfaces -CONFIG_NET_VLAN_COUNT=3 +CONFIG_NET_VLAN_COUNT=2 -# There will be three network interfaces. +# There will be three network interfaces so allocate enough IPv4 and IPv6 configs. +CONFIG_NET_IF_MAX_IPV4_COUNT=3 +CONFIG_NET_IF_MAX_IPV6_COUNT=3 # First ethernet interface will use these settings CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8::1" diff --git a/samples/net/sockets/echo_server/src/vlan.c b/samples/net/sockets/echo_server/src/vlan.c index 2115a5f3ae5..b9a28d222c4 100644 --- a/samples/net/sockets/echo_server/src/vlan.c +++ b/samples/net/sockets/echo_server/src/vlan.c @@ -15,14 +15,19 @@ LOG_MODULE_DECLARE(net_echo_server_sample, LOG_LEVEL_DBG); struct ud { struct net_if *first; struct net_if *second; - struct net_if *third; + struct net_if *eth; }; static void iface_cb(struct net_if *iface, void *user_data) { struct ud *ud = user_data; - if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { + if (net_if_l2(iface) == &NET_L2_GET_NAME(ETHERNET) && ud->eth == NULL) { + ud->eth = iface; + return; + } + + if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) { return; } @@ -35,16 +40,11 @@ static void iface_cb(struct net_if *iface, void *user_data) ud->second = iface; return; } - - if (!ud->third) { - ud->third = iface; - return; - } } -static int setup_iface(struct net_if *iface, const char *ipv6_addr, - const char *ipv4_addr, const char *netmask, - uint16_t vlan_tag) +static int setup_iface(struct net_if *iface, struct net_if *vlan, + const char *ipv6_addr, const char *ipv4_addr, + const char *netmask, uint16_t vlan_tag) { struct net_if_addr *ifaddr; struct in_addr addr4; @@ -62,11 +62,11 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, return -EINVAL; } - ifaddr = net_if_ipv6_addr_add(iface, &addr6, + ifaddr = net_if_ipv6_addr_add(vlan, &addr6, NET_ADDR_MANUAL, 0); if (!ifaddr) { LOG_ERR("Cannot add %s to interface %p", - ipv6_addr, iface); + ipv6_addr, vlan); return -EINVAL; } } @@ -77,11 +77,11 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, return -EINVAL; } - ifaddr = net_if_ipv4_addr_add(iface, &addr4, + ifaddr = net_if_ipv4_addr_add(vlan, &addr4, NET_ADDR_MANUAL, 0); if (!ifaddr) { LOG_ERR("Cannot add %s to interface %p", - ipv4_addr, iface); + ipv4_addr, vlan); return -EINVAL; } @@ -93,11 +93,11 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, return -EINVAL; } - net_if_ipv4_set_netmask_by_addr(iface, &addr4, &nm); + net_if_ipv4_set_netmask_by_addr(vlan, &addr4, &nm); } } - LOG_DBG("Interface %p VLAN tag %d setup done.", iface, vlan_tag); + LOG_DBG("Interface %p VLAN tag %d setup done.", vlan, vlan_tag); return 0; } @@ -115,7 +115,7 @@ int init_vlan(void) * create IP address for this test. But first the VLAN needs to be * added to the interface so that IPv6 DAD can work properly. */ - ret = setup_iface(ud.second, + ret = setup_iface(ud.eth, ud.first, CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR, CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR, CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_NETMASK, @@ -124,7 +124,7 @@ int init_vlan(void) return ret; } - ret = setup_iface(ud.third, + ret = setup_iface(ud.eth, ud.second, CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR, CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR, CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_NETMASK, From b5eec907d127b899b3d76e150d92fb4f714af645 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 26 Mar 2024 17:43:32 +0200 Subject: [PATCH 1583/2402] samples: net: vlan: Use proper VLAN interface The VLAN interfaces are now Virtual type so we need to collect only the Virtual interfaces and not Ethernet ones. Signed-off-by: Jukka Rissanen --- samples/net/vlan/prj.conf | 16 ++++++++-------- samples/net/vlan/src/main.c | 31 +++++++------------------------ 2 files changed, 15 insertions(+), 32 deletions(-) diff --git a/samples/net/vlan/prj.conf b/samples/net/vlan/prj.conf index 30cbbd7b4e0..0fb5b752dfd 100644 --- a/samples/net/vlan/prj.conf +++ b/samples/net/vlan/prj.conf @@ -18,6 +18,9 @@ CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT=5 CONFIG_NET_IF_UNICAST_IPV4_ADDR_COUNT=1 CONFIG_NET_MAX_CONTEXTS=10 +CONFIG_NET_IF_MAX_IPV6_COUNT=3 +CONFIG_NET_IF_MAX_IPV6_COUNT=3 + CONFIG_INIT_STACKS=y CONFIG_PRINTK=y CONFIG_NET_SHELL=y @@ -30,11 +33,11 @@ CONFIG_NET_CONFIG_NEED_IPV4=y CONFIG_NET_CONFIG_SETTINGS=y # First ethernet interface will use these settings -CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8:100::1" -CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8:100::2" -# TEST-NET-2 from RFC 5737 -CONFIG_NET_CONFIG_MY_IPV4_ADDR="198.51.100.1" -CONFIG_NET_CONFIG_PEER_IPV4_ADDR="198.51.100.2" +CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8::1" +CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2" +CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1" +CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2" + # VLAN tag for the first interface CONFIG_SAMPLE_VLAN_TAG=100 @@ -51,6 +54,3 @@ CONFIG_LOG=y # and that is enforced by Kconfig file. CONFIG_NET_VLAN=y CONFIG_NET_VLAN_COUNT=2 - -# Settings for native_posix ethernet driver (if compiled for that board) -CONFIG_ETH_NATIVE_POSIX=y diff --git a/samples/net/vlan/src/main.c b/samples/net/vlan/src/main.c index 3b075cf435c..4f7483c1d25 100644 --- a/samples/net/vlan/src/main.c +++ b/samples/net/vlan/src/main.c @@ -15,43 +15,35 @@ LOG_MODULE_REGISTER(net_vlan_sample, LOG_LEVEL_DBG); #include #include -#if CONFIG_NET_VLAN_COUNT > 1 -#define CREATE_MULTIPLE_TAGS -#endif - struct ud { struct net_if *first; struct net_if *second; }; -#if defined(CREATE_MULTIPLE_TAGS) static void iface_cb(struct net_if *iface, void *user_data) { struct ud *ud = user_data; - if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { + if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) { return; } - if (iface == ud->first) { + if (ud->first == NULL) { + ud->first = iface; return; } ud->second = iface; } -#endif static int init_app(void) { struct net_if *iface; - int ret; - -#if defined(CREATE_MULTIPLE_TAGS) struct net_if_addr *ifaddr; struct in_addr addr4; struct in6_addr addr6; struct ud ud; -#endif + int ret; iface = net_if_get_first_by_type(&NET_L2_GET_NAME(ETHERNET)); if (!iface) { @@ -59,23 +51,15 @@ static int init_app(void) return -ENOENT; } + net_if_foreach(iface_cb, &ud); + ret = net_eth_vlan_enable(iface, CONFIG_SAMPLE_VLAN_TAG); if (ret < 0) { LOG_ERR("Cannot enable VLAN for tag %d (%d)", CONFIG_SAMPLE_VLAN_TAG, ret); } -#if defined(CREATE_MULTIPLE_TAGS) - ud.first = iface; - ud.second = NULL; - - net_if_foreach(iface_cb, &ud); - - /* This sample has two VLANs. For the second one we need to manually - * create IP address for this test. But first the VLAN needs to be - * added to the interface so that IPv6 DAD can work properly. - */ - ret = net_eth_vlan_enable(ud.second, CONFIG_SAMPLE_VLAN_TAG_2); + ret = net_eth_vlan_enable(iface, CONFIG_SAMPLE_VLAN_TAG_2); if (ret < 0) { LOG_ERR("Cannot enable VLAN for tag %d (%d)", CONFIG_SAMPLE_VLAN_TAG_2, ret); @@ -104,7 +88,6 @@ static int init_app(void) CONFIG_SAMPLE_IPV4_ADDR_2, ud.second); return -EINVAL; } -#endif return ret; } From 9fcf1a4c3790dc0a277d6829537214a1724576af Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 26 Mar 2024 18:21:41 +0200 Subject: [PATCH 1584/2402] samples: net: echo-client: Fix the VLAN support The echo-client VLAN code needed updating so that correct interfaces are in use. Signed-off-by: Jukka Rissanen --- .../net/sockets/echo_client/overlay-vlan.conf | 2 +- samples/net/sockets/echo_client/prj.conf | 2 ++ samples/net/sockets/echo_client/src/vlan.c | 36 ++++++++++--------- 3 files changed, 23 insertions(+), 17 deletions(-) diff --git a/samples/net/sockets/echo_client/overlay-vlan.conf b/samples/net/sockets/echo_client/overlay-vlan.conf index 40304ff02d8..73d1fc9cb6e 100644 --- a/samples/net/sockets/echo_client/overlay-vlan.conf +++ b/samples/net/sockets/echo_client/overlay-vlan.conf @@ -1,7 +1,7 @@ CONFIG_NET_VLAN=y # We have one non-vlan interface and two VLAN interfaces -CONFIG_NET_VLAN_COUNT=3 +CONFIG_NET_VLAN_COUNT=2 # There will be three network interfaces. Note that the addresses are # selected so that our address ends to .1 and the peer one to .2 diff --git a/samples/net/sockets/echo_client/prj.conf b/samples/net/sockets/echo_client/prj.conf index dc75a907f41..016911f5917 100644 --- a/samples/net/sockets/echo_client/prj.conf +++ b/samples/net/sockets/echo_client/prj.conf @@ -33,6 +33,8 @@ CONFIG_NET_CONTEXT_NET_PKT_POOL=y CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=3 CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT=4 CONFIG_NET_MAX_CONTEXTS=10 +CONFIG_NET_IF_MAX_IPV6_COUNT=3 +CONFIG_NET_IF_MAX_IPV4_COUNT=3 # Network shell CONFIG_NET_SHELL=y diff --git a/samples/net/sockets/echo_client/src/vlan.c b/samples/net/sockets/echo_client/src/vlan.c index 482fbefb421..f7b96c9863f 100644 --- a/samples/net/sockets/echo_client/src/vlan.c +++ b/samples/net/sockets/echo_client/src/vlan.c @@ -15,14 +15,13 @@ LOG_MODULE_DECLARE(net_echo_client_sample, LOG_LEVEL_DBG); struct ud { struct net_if *first; struct net_if *second; - struct net_if *third; }; static void iface_cb(struct net_if *iface, void *user_data) { struct ud *ud = user_data; - if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { + if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) { return; } @@ -35,22 +34,20 @@ static void iface_cb(struct net_if *iface, void *user_data) ud->second = iface; return; } - - if (!ud->third) { - ud->third = iface; - return; - } } -static int setup_iface(struct net_if *iface, const char *ipv6_addr, - const char *ipv4_addr, uint16_t vlan_tag) +static int setup_iface(struct net_if *eth_iface, + struct net_if *iface, + const char *ipv6_addr, + const char *ipv4_addr, + uint16_t vlan_tag) { struct net_if_addr *ifaddr; struct in_addr addr4; struct in6_addr addr6; int ret; - ret = net_eth_vlan_enable(iface, vlan_tag); + ret = net_eth_vlan_enable(eth_iface, vlan_tag); if (ret < 0) { LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret); } @@ -84,18 +81,21 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, int init_vlan(void) { + struct net_if *iface; struct ud ud; int ret; + iface = net_if_get_first_by_type(&NET_L2_GET_NAME(ETHERNET)); + if (!iface) { + LOG_ERR("No ethernet interfaces found."); + return -ENOENT; + } + memset(&ud, 0, sizeof(ud)); net_if_foreach(iface_cb, &ud); - /* This sample has two VLANs. For the second one we need to manually - * create IP address for this test. But first the VLAN needs to be - * added to the interface so that IPv6 DAD can work properly. - */ - ret = setup_iface(ud.second, + ret = setup_iface(iface, ud.first, CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR, CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR, CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG); @@ -103,7 +103,7 @@ int init_vlan(void) return ret; } - ret = setup_iface(ud.third, + ret = setup_iface(iface, ud.second, CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR, CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR, CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG); @@ -111,5 +111,9 @@ int init_vlan(void) return ret; } + /* Bring up the VLAN interface automatically */ + net_if_up(ud.first); + net_if_up(ud.second); + return 0; } From b1e31f9f7f099a0ccc4244982b372bb6ca243bf0 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 26 Mar 2024 18:31:24 +0200 Subject: [PATCH 1585/2402] samples: net: txtime: Fix the VLAN support The txtime VLAN code needed updating so that correct interfaces are in use. Signed-off-by: Jukka Rissanen --- samples/net/sockets/txtime/overlay-vlan.conf | 2 +- samples/net/sockets/txtime/prj.conf | 2 + samples/net/sockets/txtime/src/vlan.c | 40 +++++++++++--------- 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/samples/net/sockets/txtime/overlay-vlan.conf b/samples/net/sockets/txtime/overlay-vlan.conf index 014523b7fd5..78b6e1f3831 100644 --- a/samples/net/sockets/txtime/overlay-vlan.conf +++ b/samples/net/sockets/txtime/overlay-vlan.conf @@ -1,7 +1,7 @@ CONFIG_NET_VLAN=y # We have one non-vlan interface and two VLAN interfaces -CONFIG_NET_VLAN_COUNT=3 +CONFIG_NET_VLAN_COUNT=2 # There will be three network interfaces. diff --git a/samples/net/sockets/txtime/prj.conf b/samples/net/sockets/txtime/prj.conf index 39b909fddd8..13520274bf0 100644 --- a/samples/net/sockets/txtime/prj.conf +++ b/samples/net/sockets/txtime/prj.conf @@ -21,6 +21,8 @@ CONFIG_NET_CONNECTION_MANAGER=y CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=3 CONFIG_NET_L2_ETHERNET_MGMT=y CONFIG_NET_L2_ETHERNET=y +CONFIG_NET_IF_MAX_IPV6_COUNT=3 +CONFIG_NET_IF_MAX_IPV4_COUNT=3 # If you want to have VLAN support, use VLAN overlay file diff --git a/samples/net/sockets/txtime/src/vlan.c b/samples/net/sockets/txtime/src/vlan.c index b8cee26c593..8eee42161de 100644 --- a/samples/net/sockets/txtime/src/vlan.c +++ b/samples/net/sockets/txtime/src/vlan.c @@ -15,14 +15,13 @@ LOG_MODULE_DECLARE(net_txtime_sample, LOG_LEVEL_DBG); struct ud { struct net_if *first; struct net_if *second; - struct net_if *third; }; static void iface_cb(struct net_if *iface, void *user_data) { struct ud *ud = user_data; - if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { + if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) { return; } @@ -35,15 +34,13 @@ static void iface_cb(struct net_if *iface, void *user_data) ud->second = iface; return; } - - if (!ud->third) { - ud->third = iface; - return; - } } -static int setup_iface(struct net_if *iface, const char *ipv6_addr, - const char *ipv4_addr, uint16_t vlan_tag) +static int setup_iface(struct net_if *eth_iface, + struct net_if *iface, + const char *ipv6_addr, + const char *ipv4_addr, + uint16_t vlan_tag) { struct net_if_addr *ifaddr; struct in_addr addr4; @@ -55,7 +52,7 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, return -ENOENT; } - ret = net_eth_vlan_enable(iface, vlan_tag); + ret = net_eth_vlan_enable(eth_iface, vlan_tag); if (ret < 0) { LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret); } @@ -97,25 +94,28 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, int init_vlan(void) { + struct net_if *iface; enum ethernet_hw_caps caps; struct ud ud; int ret; + iface = net_if_get_first_by_type(&NET_L2_GET_NAME(ETHERNET)); + if (!iface) { + LOG_ERR("No ethernet interfaces found."); + return -ENOENT; + } + memset(&ud, 0, sizeof(ud)); net_if_foreach(iface_cb, &ud); - caps = net_eth_get_hw_capabilities(ud.first); + caps = net_eth_get_hw_capabilities(iface); if (!(caps & ETHERNET_HW_VLAN)) { - LOG_DBG("Interface %p does not support %s", ud.first, "VLAN"); + LOG_DBG("Interface %p does not support %s", iface, "VLAN"); return -ENOENT; } - /* This sample has two VLANs. For the second one we need to manually - * create IP address for this test. But first the VLAN needs to be - * added to the interface so that IPv6 DAD can work properly. - */ - ret = setup_iface(ud.second, + ret = setup_iface(iface, ud.first, CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR, CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR, CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG); @@ -123,7 +123,7 @@ int init_vlan(void) return ret; } - ret = setup_iface(ud.third, + ret = setup_iface(iface, ud.second, CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR, CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR, CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG); @@ -131,5 +131,9 @@ int init_vlan(void) return ret; } + /* Bring up the VLAN interface automatically */ + net_if_up(ud.first); + net_if_up(ud.second); + return 0; } From 793cd566789d6d608fa435425c15d6ddc998d40f Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 26 Mar 2024 19:06:58 +0200 Subject: [PATCH 1586/2402] samples: net: mdns_responder: Fix the VLAN support The mdns-responder VLAN code needed updating so that correct interfaces are in use. Signed-off-by: Jukka Rissanen --- samples/net/mdns_responder/overlay-vlan.conf | 2 +- samples/net/mdns_responder/prj.conf | 3 ++ samples/net/mdns_responder/src/vlan.c | 32 ++++++++++++-------- 3 files changed, 24 insertions(+), 13 deletions(-) diff --git a/samples/net/mdns_responder/overlay-vlan.conf b/samples/net/mdns_responder/overlay-vlan.conf index 5dfe0f9b8f7..83d84cbf3fb 100644 --- a/samples/net/mdns_responder/overlay-vlan.conf +++ b/samples/net/mdns_responder/overlay-vlan.conf @@ -1,7 +1,7 @@ CONFIG_NET_VLAN=y # We have one non-vlan interface and two VLAN interfaces -CONFIG_NET_VLAN_COUNT=3 +CONFIG_NET_VLAN_COUNT=2 # There will be three network interfaces. diff --git a/samples/net/mdns_responder/prj.conf b/samples/net/mdns_responder/prj.conf index 3db06cbb2ac..db58992f3f8 100644 --- a/samples/net/mdns_responder/prj.conf +++ b/samples/net/mdns_responder/prj.conf @@ -5,6 +5,9 @@ CONFIG_NET_IPV6=y CONFIG_NET_IPV4=y #CONFIG_NET_DHCPV4=y +CONFIG_NET_IF_MAX_IPV6_COUNT=3 +CONFIG_NET_IF_MAX_IPV4_COUNT=3 + CONFIG_NET_HOSTNAME_ENABLE=y CONFIG_NET_HOSTNAME_UNIQUE=n CONFIG_NET_HOSTNAME="zephyr" diff --git a/samples/net/mdns_responder/src/vlan.c b/samples/net/mdns_responder/src/vlan.c index 7458343eaee..832b172f367 100644 --- a/samples/net/mdns_responder/src/vlan.c +++ b/samples/net/mdns_responder/src/vlan.c @@ -15,14 +15,13 @@ LOG_MODULE_DECLARE(net_mdns_responder_sample, LOG_LEVEL_DBG); struct ud { struct net_if *first; struct net_if *second; - struct net_if *third; }; static void iface_cb(struct net_if *iface, void *user_data_param) { struct ud *user_data = user_data_param; - if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { + if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) { return; } @@ -35,15 +34,13 @@ static void iface_cb(struct net_if *iface, void *user_data_param) user_data->second = iface; return; } - - if (!user_data->third) { - user_data->third = iface; - return; - } } -static int setup_iface(struct net_if *iface, const char *ipv6_addr, - const char *ipv4_addr, const char *netmask, +static int setup_iface(struct net_if *eth_iface, + struct net_if *iface, + const char *ipv6_addr, + const char *ipv4_addr, + const char *netmask, uint16_t vlan_tag) { struct net_if_addr *ifaddr; @@ -51,7 +48,7 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, struct in6_addr addr6; int ret; - ret = net_eth_vlan_enable(iface, vlan_tag); + ret = net_eth_vlan_enable(eth_iface, vlan_tag); if (ret < 0) { LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret); } @@ -104,9 +101,16 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, int init_vlan(void) { + struct net_if *iface; struct ud user_data; int ret; + iface = net_if_get_first_by_type(&NET_L2_GET_NAME(ETHERNET)); + if (!iface) { + LOG_ERR("No ethernet interfaces found."); + return -ENOENT; + } + memset(&user_data, 0, sizeof(user_data)); net_if_foreach(iface_cb, &user_data); @@ -115,7 +119,7 @@ int init_vlan(void) * create IP address for this test. But first the VLAN needs to be * added to the interface so that IPv6 DAD can work properly. */ - ret = setup_iface(user_data.second, + ret = setup_iface(iface, user_data.first, CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR, CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR, CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_NETMASK, @@ -124,7 +128,7 @@ int init_vlan(void) return ret; } - ret = setup_iface(user_data.third, + ret = setup_iface(iface, user_data.second, CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR, CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR, CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_NETMASK, @@ -133,5 +137,9 @@ int init_vlan(void) return ret; } + /* Bring up the VLAN interface automatically */ + net_if_up(user_data.first); + net_if_up(user_data.second); + return 0; } From d47386110b11bbfda707c5c0801a2c1fbc9a9ca2 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 27 Mar 2024 10:47:13 +0200 Subject: [PATCH 1587/2402] samples: net: lldp: Fix the VLAN support The lldp sample VLAN code needed updating so that correct interfaces are in use. Signed-off-by: Jukka Rissanen --- samples/net/lldp/prj.conf | 8 +++--- samples/net/lldp/src/main.c | 52 ++++++++++++++++++++----------------- 2 files changed, 32 insertions(+), 28 deletions(-) diff --git a/samples/net/lldp/prj.conf b/samples/net/lldp/prj.conf index 07b5c1b6016..ca4c6835e33 100644 --- a/samples/net/lldp/prj.conf +++ b/samples/net/lldp/prj.conf @@ -18,6 +18,8 @@ CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=5 CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT=5 CONFIG_NET_IF_UNICAST_IPV4_ADDR_COUNT=1 CONFIG_NET_MAX_CONTEXTS=2 +CONFIG_NET_IF_MAX_IPV6_COUNT=3 +CONFIG_NET_IF_MAX_IPV4_COUNT=3 CONFIG_INIT_STACKS=y CONFIG_PRINTK=y @@ -56,11 +58,9 @@ CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG=200 # Logging CONFIG_LOG=y -# VLAN settings. We will have three VLANs in this sample. -# The CONFIG_NET_VLAN_COUNT will also determine how many ethernet network -# interfaces there will be in the system. +# VLAN settings. We will have two VLANs in this sample. CONFIG_NET_VLAN=y -CONFIG_NET_VLAN_COUNT=3 +CONFIG_NET_VLAN_COUNT=2 # LLDP settings CONFIG_NET_LLDP=y diff --git a/samples/net/lldp/src/main.c b/samples/net/lldp/src/main.c index f63ab2edad2..d4d90f2e439 100644 --- a/samples/net/lldp/src/main.c +++ b/samples/net/lldp/src/main.c @@ -36,14 +36,13 @@ static void set_optional_tlv(struct net_if *iface) struct ud { struct net_if *first; struct net_if *second; - struct net_if *third; }; static void iface_cb(struct net_if *iface, void *user_data) { struct ud *ud = user_data; - if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { + if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) { return; } @@ -56,22 +55,20 @@ static void iface_cb(struct net_if *iface, void *user_data) ud->second = iface; return; } - - if (!ud->third) { - ud->third = iface; - return; - } } -static int setup_iface(struct net_if *iface, const char *ipv6_addr, - const char *ipv4_addr, uint16_t vlan_tag) +static int setup_iface(struct net_if *eth_iface, + struct net_if *iface, + const char *ipv6_addr, + const char *ipv4_addr, + uint16_t vlan_tag) { struct net_if_addr *ifaddr; struct in_addr addr4; struct in6_addr addr6; int ret; - ret = net_eth_vlan_enable(iface, vlan_tag); + ret = net_eth_vlan_enable(eth_iface, vlan_tag); if (ret < 0) { LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret); } @@ -105,7 +102,7 @@ static int setup_iface(struct net_if *iface, const char *ipv6_addr, static struct ud ud; -static int init_vlan(void) +static int init_vlan(struct net_if *iface) { enum ethernet_hw_caps caps; int ret; @@ -114,17 +111,13 @@ static int init_vlan(void) net_if_foreach(iface_cb, &ud); - caps = net_eth_get_hw_capabilities(ud.first); + caps = net_eth_get_hw_capabilities(iface); if (!(caps & ETHERNET_HW_VLAN)) { - LOG_DBG("Interface %p does not support %s", ud.first, "VLAN"); + LOG_DBG("Interface %p does not support %s", iface, "VLAN"); return -ENOENT; } - /* This sample has two VLANs. For the second one we need to manually - * create IP address for this test. But first the VLAN needs to be - * added to the interface so that IPv6 DAD can work properly. - */ - ret = setup_iface(ud.second, + ret = setup_iface(iface, ud.first, CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR, CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR, CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG); @@ -132,7 +125,7 @@ static int init_vlan(void) return ret; } - ret = setup_iface(ud.third, + ret = setup_iface(iface, ud.second, CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR, CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR, CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG); @@ -140,6 +133,10 @@ static int init_vlan(void) return ret; } + /* Bring up the VLAN interface automatically */ + net_if_up(ud.first); + net_if_up(ud.second); + return 0; } @@ -194,22 +191,29 @@ static enum net_verdict parse_lldp(struct net_if *iface, struct net_pkt *pkt) static int init_app(void) { enum ethernet_hw_caps caps; + struct net_if *iface; int ret; - ret = init_vlan(); + iface = net_if_get_first_by_type(&NET_L2_GET_NAME(ETHERNET)); + if (!iface) { + LOG_ERR("No ethernet interfaces found."); + return -ENOENT; + } + + ret = init_vlan(iface); if (ret < 0) { LOG_WRN("Cannot setup VLAN (%d)", ret); } - caps = net_eth_get_hw_capabilities(ud.first); + caps = net_eth_get_hw_capabilities(iface); if (!(caps & ETHERNET_LLDP)) { - LOG_ERR("Interface %p does not support %s", ud.first, "LLDP"); + LOG_ERR("Interface %p does not support %s", iface, "LLDP"); LOG_ERR("Cannot continue!"); return -ENOENT; } - set_optional_tlv(ud.first); - net_lldp_register_callback(ud.first, parse_lldp); + set_optional_tlv(iface); + net_lldp_register_callback(iface, parse_lldp); return 0; } From def4a7ec1299c5b1e844858aa865555bf33f905e Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 26 Mar 2024 18:58:08 +0200 Subject: [PATCH 1588/2402] net: gptp: Remove VLAN support The gPTP is not suppose to be run on top of VLAN and the earlier support was just for testing purposes. Remove VLAN support now after the VLAN overhaul. Signed-off-by: Jukka Rissanen --- samples/net/gptp/overlay-vlan.conf | 22 ----- samples/net/gptp/src/main.c | 111 ----------------------- subsys/net/l2/ethernet/ethernet.c | 3 +- subsys/net/l2/ethernet/gptp/Kconfig | 25 ------ subsys/net/l2/ethernet/gptp/gptp.c | 132 ---------------------------- tests/net/all/prj.conf | 2 - 6 files changed, 1 insertion(+), 294 deletions(-) delete mode 100644 samples/net/gptp/overlay-vlan.conf diff --git a/samples/net/gptp/overlay-vlan.conf b/samples/net/gptp/overlay-vlan.conf deleted file mode 100644 index afa9a52d482..00000000000 --- a/samples/net/gptp/overlay-vlan.conf +++ /dev/null @@ -1,22 +0,0 @@ -# Second ethernet interface will have these settings -CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR="2001:db8:100::1" -# TEST-NET-2 from RFC 5737 -CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR="198.51.100.1" -# VLAN tag for the second interface -CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG=100 - -# Settings for the third network interface -CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR="2001:db8:200::1" -# TEST-NET-3 from RFC 5737 -CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR="203.0.113.1" -# VLAN tag for the second interface -CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG=200 - -# VLAN settings. We will have three VLANs, but the one running gPTP protocol -# will not have any tags (see IEEE 802.11AS chapter 11.3.3 for details) -CONFIG_NET_VLAN=y -CONFIG_NET_VLAN_COUNT=3 - -# Enable these if you want to run gPTP over a VLAN link -CONFIG_NET_GPTP_VLAN=y -CONFIG_NET_GPTP_VLAN_TAG=100 diff --git a/samples/net/gptp/src/main.c b/samples/net/gptp/src/main.c index 004a3c2884f..570e31ea598 100644 --- a/samples/net/gptp/src/main.c +++ b/samples/net/gptp/src/main.c @@ -20,111 +20,6 @@ extern void init_testing(void); static struct gptp_phase_dis_cb phase_dis; -#if defined(CONFIG_NET_GPTP_VLAN) -/* User data for the interface callback */ -struct ud { - struct net_if *first; - struct net_if *second; - struct net_if *third; -}; - -static void iface_cb(struct net_if *iface, void *user_data) -{ - struct ud *ud = user_data; - - if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) { - return; - } - - if (!ud->first) { - ud->first = iface; - return; - } - - if (!ud->second) { - ud->second = iface; - return; - } - - if (!ud->third) { - ud->third = iface; - return; - } -} - -static int setup_iface(struct net_if *iface, const char *ipv6_addr, - const char *ipv4_addr, uint16_t vlan_tag) -{ - struct net_if_addr *ifaddr; - struct in_addr addr4; - struct in6_addr addr6; - int ret; - - ret = net_eth_vlan_enable(iface, vlan_tag); - if (ret < 0) { - LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret); - } - - if (net_addr_pton(AF_INET6, ipv6_addr, &addr6)) { - LOG_ERR("Invalid address: %s", ipv6_addr); - return -EINVAL; - } - - ifaddr = net_if_ipv6_addr_add(iface, &addr6, NET_ADDR_MANUAL, 0); - if (!ifaddr) { - LOG_ERR("Cannot add %s to interface %p", ipv6_addr, iface); - return -EINVAL; - } - - if (net_addr_pton(AF_INET, ipv4_addr, &addr4)) { - LOG_ERR("Invalid address: %s", ipv4_addr); - return -EINVAL; - } - - ifaddr = net_if_ipv4_addr_add(iface, &addr4, NET_ADDR_MANUAL, 0); - if (!ifaddr) { - LOG_ERR("Cannot add %s to interface %p", ipv4_addr, iface); - return -EINVAL; - } - - LOG_DBG("Interface %p VLAN tag %d setup done.", iface, vlan_tag); - - return 0; -} - -static int init_vlan(void) -{ - struct ud ud; - int ret; - - (void)memset(&ud, 0, sizeof(ud)); - - net_if_foreach(iface_cb, &ud); - - /* This sample has two VLANs. For the second one we need to manually - * create IP address for this test. But first the VLAN needs to be - * added to the interface so that IPv6 DAD can work properly. - */ - ret = setup_iface(ud.second, - CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR, - CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR, - CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG); - if (ret < 0) { - return ret; - } - - ret = setup_iface(ud.third, - CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR, - CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR, - CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG); - if (ret < 0) { - return ret; - } - - return 0; -} -#endif /* CONFIG_NET_GPTP_VLAN */ - static void gptp_phase_dis_cb(uint8_t *gm_identity, uint16_t *time_base, struct gptp_scaled_ns *last_gm_ph_change, @@ -145,12 +40,6 @@ static void gptp_phase_dis_cb(uint8_t *gm_identity, static int init_app(void) { -#if defined(CONFIG_NET_GPTP_VLAN) - if (init_vlan() < 0) { - LOG_ERR("Cannot setup VLAN"); - } -#endif - gptp_register_phase_dis_cb(&phase_dis, gptp_phase_dis_cb); return 0; diff --git a/subsys/net/l2/ethernet/ethernet.c b/subsys/net/l2/ethernet/ethernet.c index 2dd8121c206..1f448d454ef 100644 --- a/subsys/net/l2/ethernet/ethernet.c +++ b/subsys/net/l2/ethernet/ethernet.c @@ -520,8 +520,7 @@ static struct net_buf *ethernet_fill_header(struct ethernet_context *ctx, if (IS_ENABLED(CONFIG_NET_VLAN) && net_eth_is_vlan_enabled(ctx, iface) && - net_pkt_vlan_tag(pkt) != NET_VLAN_TAG_UNSPEC && - (IS_ENABLED(CONFIG_NET_GPTP_VLAN) || ptype != htons(NET_ETH_PTYPE_PTP))) { + net_pkt_vlan_tag(pkt) != NET_VLAN_TAG_UNSPEC) { struct net_eth_vlan_hdr *hdr_vlan; hdr_vlan = (struct net_eth_vlan_hdr *)(hdr_frag->data); diff --git a/subsys/net/l2/ethernet/gptp/Kconfig b/subsys/net/l2/ethernet/gptp/Kconfig index 59dcbae2327..0ca1e1f93e8 100644 --- a/subsys/net/l2/ethernet/gptp/Kconfig +++ b/subsys/net/l2/ethernet/gptp/Kconfig @@ -117,31 +117,6 @@ config NET_GPTP_NUM_PORTS Configures the gPTP stack to work with the given number of ports. The port concept is the same thing as network interface. -config NET_GPTP_VLAN - bool "Run gPTP over VLAN link" - depends on NET_VLAN - select NET_L2_ETHERNET_MGMT - select NET_MGMT_EVENT - select NET_MGMT_EVENT_INFO - help - The standard requires gPTP packets to not be VLAN-tagged (see IEEE - 802.1AS chapter 11.3.3). - This setting is for testing purposes. It allows to deviate from the - standard by running gPTP over a VLAN link. Currently only one port can - have VLAN tag set. Note that CONFIG_NET_GPTP_VLAN_TAG setting must - have a proper tag value set, otherwise the gPTP over VLAN will not - work. - -config NET_GPTP_VLAN_TAG - int "VLAN tag to use" - default 4095 - depends on NET_GPTP_VLAN - help - The VLAN tag to use when sending and receiving gPTP messages. - The default value 4095 (0x0fff) means unspecified tag which is - not a valid value. This means that you need to set the tag to - a valid value. - config NET_GPTP_NEIGHBOR_PROP_DELAY_THR int "Set neighbor propagation delay threshold (ns)" default 100000 diff --git a/subsys/net/l2/ethernet/gptp/gptp.c b/subsys/net/l2/ethernet/gptp/gptp.c index 2cb128d26c2..1b45166b5e9 100644 --- a/subsys/net/l2/ethernet/gptp/gptp.c +++ b/subsys/net/l2/ethernet/gptp/gptp.c @@ -581,19 +581,6 @@ static void gptp_add_port(struct net_if *iface, void *user_data) return; } -#if defined(CONFIG_NET_GPTP_VLAN) - if (CONFIG_NET_GPTP_VLAN_TAG >= 0 && - CONFIG_NET_GPTP_VLAN_TAG < NET_VLAN_TAG_UNSPEC) { - struct net_if *vlan_iface; - - vlan_iface = net_eth_get_vlan_iface(iface, - CONFIG_NET_GPTP_VLAN_TAG); - if (vlan_iface != iface) { - return; - } - } -#endif /* CONFIG_NET_GPTP_VLAN */ - /* Check if interface has a PTP clock. */ clk = net_eth_get_ptp_clock(iface); if (clk) { @@ -926,128 +913,9 @@ static void init_ports(void) k_thread_name_set(&gptp_thread_data, "gptp"); } -#if defined(CONFIG_NET_GPTP_VLAN) -static struct net_mgmt_event_callback vlan_cb; - -struct vlan_work { - struct k_work work; - struct net_if *iface; -} vlan; - -static void disable_port(int port) -{ - GPTP_GLOBAL_DS()->selected_role[port] = GPTP_PORT_DISABLED; - - gptp_state_machine(); -} - -static void vlan_enabled(struct k_work *work) -{ - struct vlan_work *one_vlan = CONTAINER_OF(work, - struct vlan_work, - work); - if (tid) { - int port; - - port = gptp_get_port_number(one_vlan->iface); - if (port < 0) { - NET_DBG("No port found for iface %p", one_vlan->iface); - return; - } - - GPTP_GLOBAL_DS()->selected_role[port] = GPTP_PORT_SLAVE; - - gptp_state_machine(); - } else { - init_ports(); - } -} - -static void vlan_disabled(struct k_work *work) -{ - struct vlan_work *one_vlan = CONTAINER_OF(work, - struct vlan_work, - work); - int port; - - port = gptp_get_port_number(one_vlan->iface); - if (port < 0) { - NET_DBG("No port found for iface %p", one_vlan->iface); - return; - } - - disable_port(port); -} - -static void vlan_event_handler(struct net_mgmt_event_callback *cb, - uint32_t mgmt_event, - struct net_if *iface) -{ - uint16_t tag; - - if (mgmt_event != NET_EVENT_ETHERNET_VLAN_TAG_ENABLED && - mgmt_event != NET_EVENT_ETHERNET_VLAN_TAG_DISABLED) { - return; - } - -#if defined(CONFIG_NET_MGMT_EVENT_INFO) - if (!cb->info) { - return; - } - - tag = *((uint16_t *)cb->info); - if (tag != CONFIG_NET_GPTP_VLAN_TAG) { - return; - } - - vlan.iface = iface; - - if (mgmt_event == NET_EVENT_ETHERNET_VLAN_TAG_ENABLED) { - /* We found the right tag, now start gPTP for this interface */ - k_work_init(&vlan.work, vlan_enabled); - - NET_DBG("VLAN tag %d %s for iface %p", tag, "enabled", iface); - } else { - k_work_init(&vlan.work, vlan_disabled); - - NET_DBG("VLAN tag %d %s for iface %p", tag, "disabled", iface); - } - - k_work_submit(&vlan.work); -#else - NET_WARN("VLAN event but tag info missing!"); - - ARG_UNUSED(tag); -#endif -} - -static void setup_vlan_events_listener(void) -{ - net_mgmt_init_event_callback(&vlan_cb, vlan_event_handler, - NET_EVENT_ETHERNET_VLAN_TAG_ENABLED | - NET_EVENT_ETHERNET_VLAN_TAG_DISABLED); - net_mgmt_add_event_callback(&vlan_cb); -} -#endif /* CONFIG_NET_GPTP_VLAN */ - void net_gptp_init(void) { gptp_domain.default_ds.nb_ports = 0U; -#if defined(CONFIG_NET_GPTP_VLAN) - /* If user has enabled gPTP over VLAN support, then we start gPTP - * support after we have received correct "VLAN tag enabled" event. - */ - if (CONFIG_NET_GPTP_VLAN_TAG >= 0 && - CONFIG_NET_GPTP_VLAN_TAG < NET_VLAN_TAG_UNSPEC) { - setup_vlan_events_listener(); - } else { - NET_WARN("VLAN tag %d set but the value is not valid.", - CONFIG_NET_GPTP_VLAN_TAG); - - init_ports(); - } -#else init_ports(); -#endif } diff --git a/tests/net/all/prj.conf b/tests/net/all/prj.conf index 8a82138c529..8eb3c445c79 100644 --- a/tests/net/all/prj.conf +++ b/tests/net/all/prj.conf @@ -324,8 +324,6 @@ CONFIG_NET_GPTP_PATH_TRACE_ELEMENTS=2 CONFIG_NET_GPTP_PROBE_CLOCK_SOURCE_ON_DEMAND=y CONFIG_NET_GPTP_SYNC_RECEIPT_TIMEOUT=10 CONFIG_NET_GPTP_USE_DEFAULT_CLOCK_UPDATE=y -CONFIG_NET_GPTP_VLAN=y -CONFIG_NET_GPTP_VLAN_TAG=100 # LLDP CONFIG_NET_LLDP_CHASSIS_ID_MAC0=0x01 From 47f6048490d4f6ed09963172ced267fbabe00f7a Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 27 Mar 2024 10:15:54 +0200 Subject: [PATCH 1589/2402] doc: migration-guide-3.7: Add Virtual LAN (VLAN) information The Virtual LAN is changed to use the virtual network interfaces. Add information what changes might be needed because of this. Signed-off-by: Jukka Rissanen --- doc/releases/migration-guide-3.7.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index 0de2ccec2ce..be9a9ef489f 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -206,6 +206,12 @@ Networking used to read the inner IPv4/IPv6 packets in an IP tunnel. This incoming tunnel read is now implemented in `recv` callback. (:github:`70549`) +* Virtual LAN (VLAN) implementation is changed to use the Virtual network interfaces. + There are no API changes, but the type of a VLAN network interface is changed from `ETHERNET` + to `VIRTUAL`. This could require changes to the code that sets the VLAN tags to a network + interface. For example in the `net_eth_is_vlan_enabled()` API, the 2nd interface parameter + must point to the main Ethernet interface, and not to the VLAN interface. (:github:`70345`) + * Modified the ``wifi connect`` command to use key-value format for the arguments. In the previous implementation, we were identifying an option using its position in the argument string. This made it difficult to deal with optional arguments or extending the support From ec75dc2232d32a475654cc9098896f48c176bc7b Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Sun, 10 Mar 2024 18:07:26 +0100 Subject: [PATCH 1590/2402] drivers: can: mcan: remove broken transmitter delay compensation support Remove broken support for Transmitter Delay Compensation from the Bosch M_CAN backend driver. Even if this was enabled via Kconfig, the TDC bit in the DBTP register set during driver initialization is overwritten in can_mcan_set_timing_data(), turning TDC off. Signed-off-by: Henrik Brix Andersen --- drivers/can/Kconfig.mcan | 17 ++--------------- drivers/can/can_mcan.c | 26 -------------------------- include/zephyr/drivers/can/can_mcan.h | 4 ---- 3 files changed, 2 insertions(+), 45 deletions(-) diff --git a/drivers/can/Kconfig.mcan b/drivers/can/Kconfig.mcan index 83cf6ffaba0..db09fc800c1 100644 --- a/drivers/can/Kconfig.mcan +++ b/drivers/can/Kconfig.mcan @@ -1,4 +1,4 @@ -# Bosch m_can configuration options +# Bosch M_CAN configuration options # Copyright (c) 2020 Alexander Wachter # SPDX-License-Identifier: Apache-2.0 @@ -6,17 +6,4 @@ config CAN_MCAN bool help - Enable Bosch m_can driver. - This driver supports the Bosch m_can IP. This IP is built into the - STM32G4, STM32G0, STM32H7, and the Microchip SAM controllers with - CAN FD. - -if CAN_MCAN - -config CAN_DELAY_COMP - bool "Transceiver delay compensation" - default y - help - Enable the automatic transceiver delay compensation. - -endif #CAN_MCAN + Enable the Bosch M_CAN CAN IP module driver backend. diff --git a/drivers/can/can_mcan.c b/drivers/can/can_mcan.c index 2e33bda2d61..5bfaffa6c12 100644 --- a/drivers/can/can_mcan.c +++ b/drivers/can/can_mcan.c @@ -1427,32 +1427,6 @@ int can_mcan_init(const struct device *dev) return err; } -#if defined(CONFIG_CAN_DELAY_COMP) && defined(CONFIG_CAN_FD_MODE) - err = can_mcan_read_reg(dev, CAN_MCAN_DBTP, ®); - if (err != 0) { - return err; - } - - reg |= CAN_MCAN_DBTP_TDC; - - err = can_mcan_write_reg(dev, CAN_MCAN_DBTP, reg); - if (err != 0) { - return err; - } - - err = can_mcan_read_reg(dev, CAN_MCAN_TDCR, ®); - if (err != 0) { - return err; - } - - reg |= FIELD_PREP(CAN_MCAN_TDCR_TDCO, config->tx_delay_comp_offset); - - err = can_mcan_write_reg(dev, CAN_MCAN_TDCR, reg); - if (err != 0) { - return err; - } -#endif /* defined(CONFIG_CAN_DELAY_COMP) && defined(CONFIG_CAN_FD_MODE) */ - err = can_mcan_read_reg(dev, CAN_MCAN_GFC, ®); if (err != 0) { return err; diff --git a/include/zephyr/drivers/can/can_mcan.h b/include/zephyr/drivers/can/can_mcan.h index 8a4241aa760..25eeb437efb 100644 --- a/include/zephyr/drivers/can/can_mcan.h +++ b/include/zephyr/drivers/can/can_mcan.h @@ -1237,9 +1237,6 @@ struct can_mcan_config { uint16_t mram_elements[CAN_MCAN_MRAM_CFG_NUM_CELLS]; uint16_t mram_offsets[CAN_MCAN_MRAM_CFG_NUM_CELLS]; size_t mram_size; -#ifdef CONFIG_CAN_FD_MODE - uint8_t tx_delay_comp_offset; -#endif const void *custom; }; @@ -1300,7 +1297,6 @@ struct can_mcan_config { .mram_elements = CAN_MCAN_DT_MRAM_ELEMENTS_GET(node_id), \ .mram_offsets = CAN_MCAN_DT_MRAM_OFFSETS_GET(node_id), \ .mram_size = CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(node_id), \ - .tx_delay_comp_offset = DT_PROP(node_id, tx_delay_comp_offset), \ .custom = _custom, \ } #else /* CONFIG_CAN_FD_MODE */ From 744f20d005ebe0ad3f4ed2b4f8ed4e2a79dfe652 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Sun, 10 Mar 2024 18:12:18 +0100 Subject: [PATCH 1591/2402] dts: bindings: can: can-fd-controller: remove tx-delay-comp-offset prop Remove the unused "tx-delay-comp-offset" property from the base CAN FD controller devicetree binding. Having a static Transmitter Delay Compensation (TDC) offset is useless. The offset needs to match the data phase timing parameters in order to properly configure the second sample point when transmitting CAN FD frames with BRS enabled. Signed-off-by: Henrik Brix Andersen --- dts/bindings/can/can-fd-controller.yaml | 3 --- 1 file changed, 3 deletions(-) diff --git a/dts/bindings/can/can-fd-controller.yaml b/dts/bindings/can/can-fd-controller.yaml index a29749d93ba..46fab559d2a 100644 --- a/dts/bindings/can/can-fd-controller.yaml +++ b/dts/bindings/can/can-fd-controller.yaml @@ -16,6 +16,3 @@ properties: If this is unset (or if it is set to 0), the initial sample point will default to 75.0% for bitrates over 800 kbit/s, 80.0% for bitrates over 500 kbit/s, and 87.5% for all other bitrates. - tx-delay-comp-offset: - type: int - default: 0 From a3631264d187925029752da36abae3bc42ccfe0b Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Sun, 10 Mar 2024 18:26:50 +0100 Subject: [PATCH 1592/2402] drivers: can: add utility macro for calculating TDC offset Add a utility macro for calculating the Transmitter Delay Compensation (TDC) Offset using the sample point and CAN core clock prescaler specified by a set of data phase timing parameters. Signed-off-by: Henrik Brix Andersen --- include/zephyr/drivers/can.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index dabdde2c94a..4396fa62ad6 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -322,6 +322,23 @@ typedef void (*can_state_change_callback_t)(const struct device *dev, * For internal driver use only, skip these in public documentation. */ +/** + * @brief Calculate Transmitter Delay Compensation Offset from data phase timing parameters. + * + * Calculates the TDC Offset in minimum time quanta (mtq) using the sample point and CAN core clock + * prescaler specified by a set of data phase timing parameters. + * + * The result is clamped to the minimum/maximum supported TDC Offset values provided. + * + * @param _timing_data Pointer to data phase timing parameters. + * @param _tdco_min Minimum supported TDC Offset value in mtq. + * @param _tdco_max Maximum supported TDC Offset value in mtq. + * @return Calculated TDC Offset value in mtq. + */ +#define CAN_CALC_TDCO(_timing_data, _tdco_min, _tdco_max) \ + CLAMP((1U + _timing_data->prop_seg + _timing_data->phase_seg1) * _timing_data->prescaler, \ + _tdco_min, _tdco_max) + /** * @brief Common CAN controller driver configuration. * From bfad7bc00e734010d059d5ba7eb4cd2187eb1c8d Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Sun, 10 Mar 2024 18:28:18 +0100 Subject: [PATCH 1593/2402] drivers: can: mcan: enable transmitter delay compensation when possible Enable Transmitter Delay Compensation whenever the data phase timing parameters allow it. Fixes: #70447 Signed-off-by: Henrik Brix Andersen --- drivers/can/can_mcan.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/can/can_mcan.c b/drivers/can/can_mcan.c index 5bfaffa6c12..4a83017196b 100644 --- a/drivers/can/can_mcan.c +++ b/drivers/can/can_mcan.c @@ -225,8 +225,10 @@ int can_mcan_set_timing(const struct device *dev, const struct can_timing *timin #ifdef CONFIG_CAN_FD_MODE int can_mcan_set_timing_data(const struct device *dev, const struct can_timing *timing_data) { + const uint8_t tdco_max = FIELD_GET(CAN_MCAN_TDCR_TDCO, CAN_MCAN_TDCR_TDCO); struct can_mcan_data *data = dev->data; uint32_t dbtp = 0U; + uint8_t tdco; int err; if (data->common.started) { @@ -240,6 +242,23 @@ int can_mcan_set_timing_data(const struct device *dev, const struct can_timing * FIELD_PREP(CAN_MCAN_DBTP_DTSEG2, timing_data->phase_seg2 - 1UL) | FIELD_PREP(CAN_MCAN_DBTP_DBRP, timing_data->prescaler - 1UL); + if (timing_data->prescaler == 1U || timing_data->prescaler == 2U) { + /* TDC can only be enabled if DBRP = { 0, 1 } */ + dbtp |= CAN_MCAN_DBTP_TDC; + + /* Set TDC offset for correct location of the Secondary Sample Point (SSP) */ + tdco = CAN_CALC_TDCO(timing_data, 0U, tdco_max); + LOG_DBG("TDC enabled, using TDCO %u", tdco); + + err = can_mcan_write_reg(dev, CAN_MCAN_TDCR, FIELD_PREP(CAN_MCAN_TDCR_TDCO, tdco)); + if (err != 0) { + goto unlock; + } + } else { + LOG_DBG("TDC cannot be enabled, prescaler value %u too high", + timing_data->prescaler); + } + err = can_mcan_write_reg(dev, CAN_MCAN_DBTP, dbtp); if (err != 0) { goto unlock; From 12c69562cff8cc542819c156380b6c116c2ca46e Mon Sep 17 00:00:00 2001 From: IBEN EL HADJ MESSAOUD Marwa Date: Thu, 21 Mar 2024 14:56:22 +0100 Subject: [PATCH 1594/2402] tests: drivers: i2c: i2c_target_api: add stm32h573i_dk Add necessary overlay and stm32h573i_dk in i2c_target_api test case to enable the board. Signed-off-by: IBEN EL HADJ MESSAOUD Marwa --- boards/st/stm32h573i_dk/stm32h573i_dk.dts | 7 +++++ .../i2c_target_api/boards/stm32h573i_dk.conf | 2 ++ .../boards/stm32h573i_dk.overlay | 30 +++++++++++++++++++ .../drivers/i2c/i2c_target_api/testcase.yaml | 1 + 4 files changed, 40 insertions(+) create mode 100644 tests/drivers/i2c/i2c_target_api/boards/stm32h573i_dk.conf create mode 100644 tests/drivers/i2c/i2c_target_api/boards/stm32h573i_dk.overlay diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts index 78a687cfd13..a4d0b5b17f8 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts @@ -103,6 +103,13 @@ status = "okay"; }; +&i2c2 { + pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; pinctrl-names = "default"; diff --git a/tests/drivers/i2c/i2c_target_api/boards/stm32h573i_dk.conf b/tests/drivers/i2c/i2c_target_api/boards/stm32h573i_dk.conf new file mode 100644 index 00000000000..34b2571d125 --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/stm32h573i_dk.conf @@ -0,0 +1,2 @@ +CONFIG_I2C_STM32_INTERRUPT=y +CONFIG_I2C_VIRTUAL=n diff --git a/tests/drivers/i2c/i2c_target_api/boards/stm32h573i_dk.overlay b/tests/drivers/i2c/i2c_target_api/boards/stm32h573i_dk.overlay new file mode 100644 index 00000000000..804f97c1a73 --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/stm32h573i_dk.overlay @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +/* I2C bus pins are exposed on the ST morpho header. + * + * Bus SDA SCL + * Pin Hdr Pin Hdr + * i2c1 PB7 CN13:9 PB6 CN13:10 + * i2c2 PB11 CN15:1 PB10 CN15:2 + * + * Short Pin PB7 to PB11, and PB6 to PB10, for the test to pass. + */ + +&i2c1 { + eeprom0: eeprom@54 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x54>; + size = <1024>; + }; +}; + +&i2c2 { + eeprom1: eeprom@56 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x56>; + size = <1024>; + }; +}; diff --git a/tests/drivers/i2c/i2c_target_api/testcase.yaml b/tests/drivers/i2c/i2c_target_api/testcase.yaml index 0f14bff2b5c..f3883c0459c 100644 --- a/tests/drivers/i2c/i2c_target_api/testcase.yaml +++ b/tests/drivers/i2c/i2c_target_api/testcase.yaml @@ -16,6 +16,7 @@ tests: - nucleo_f091rc - stm32f072b_disco - stm32f3_disco + - stm32h573i_dk - nucleo_g071rb - nucleo_f207zg - nucleo_f401re From 70f541107420503841825c6fac72f6cdbfbb3424 Mon Sep 17 00:00:00 2001 From: IBEN EL HADJ MESSAOUD Marwa Date: Mon, 25 Mar 2024 10:52:51 +0100 Subject: [PATCH 1595/2402] boards: stm32h573i_dk: Fix CAN core clock Set the PLL1_Q divider to 6 give a can core clock of 80MHz to resolve fdcan_clk reception problem because M_CAN requires that the host clock "APB1" should be higher or equal to the CAN core clock "PLL1_Q". Signed-off-by: IBEN EL HADJ MESSAOUD Marwa --- boards/st/stm32h573i_dk/stm32h573i_dk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts index a4d0b5b17f8..30401d7493a 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts @@ -81,7 +81,7 @@ div-m = <5>; mul-n = <96>; div-p = <2>; - div-q = <2>; + div-q = <6>; div-r = <2>; clocks = <&clk_hse>; status = "okay"; From 296b732e634caa32109cc6d13997ab99a45a1761 Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Sun, 24 Mar 2024 16:13:59 +0800 Subject: [PATCH 1596/2402] dts: mcxn947: Add dac node Add the dac node Signed-off-by: Zhaoxiang Jin --- dts/arm/nxp/nxp_mcxn94x_common.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi index 371a0876cf2..ba8de4d940c 100644 --- a/dts/arm/nxp/nxp_mcxn94x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi @@ -567,6 +567,24 @@ interrupts = <57 0>; status = "disabled"; }; + + dac0: dac@10f000 { + compatible = "nxp,lpdac"; + reg = < 0x10f000 0x1000>; + interrupts = <106 0>; + status = "disabled"; + voltage-reference = <0>; + #io-channel-cells = <1>; + }; + + dac1: dac@112000 { + compatible = "nxp,lpdac"; + reg = < 0x112000 0x1000>; + interrupts = <107 0>; + status = "disabled"; + voltage-reference = <0>; + #io-channel-cells = <1>; + }; }; &systick { From e3937e99fcc4020e466551611765838ab270179a Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Tue, 26 Mar 2024 08:45:39 +0800 Subject: [PATCH 1597/2402] boards: frdm_mcxn947: Add support for dac Add support for dac Signed-off-by: Zhaoxiang Jin --- boards/nxp/frdm_mcxn947/board.c | 16 ++++++++++++++++ boards/nxp/frdm_mcxn947/doc/index.rst | 2 ++ .../nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi | 8 ++++++++ boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 5 +++++ .../frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts | 4 ++++ .../frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml | 1 + 6 files changed, 36 insertions(+) diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index ca9405803e9..6f55c216d85 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -132,6 +132,22 @@ static int frdm_mcxn947_init(void) CLOCK_EnableClock(kCLOCK_Gpio5); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(dac0), okay) + SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac0); + CLOCK_SetClkDiv(kCLOCK_DivDac0Clk, 1u); + CLOCK_AttachClk(kFRO_HF_to_DAC0); + + CLOCK_EnableClock(kCLOCK_Dac0); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(dac1), okay) + SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac1); + CLOCK_SetClkDiv(kCLOCK_DivDac1Clk, 1u); + CLOCK_AttachClk(kFRO_HF_to_DAC1); + + CLOCK_EnableClock(kCLOCK_Dac1); +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index 06356a4f24e..a11686cd61d 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -69,6 +69,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | FLEXSPI | on-chip | flash programming | +-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ Targets available ================== diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi index 55b8bfef585..4caf1845392 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi @@ -49,4 +49,12 @@ bias-pull-up; }; }; + + pinmux_dac0: pinmux_dac0 { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; }; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 326da06db0a..16dcd41276d 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -131,3 +131,8 @@ }; }; }; + +&dac0 { + pinctrl-0 = <&pinmux_dac0>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts index 271fe4ba475..cdb52c62f5c 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts @@ -92,3 +92,7 @@ &w25q64jvssiq { status = "okay"; }; + +&dac0 { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml index 372b46ec98b..2222a8c275b 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -18,4 +18,5 @@ supported: - dma - gpio - spi + - dac vendor: nxp From bd9cad3a59a8e118e273a78fd5caa7c55993d2d6 Mon Sep 17 00:00:00 2001 From: Zhaoxiang Jin Date: Sun, 24 Mar 2024 16:16:01 +0800 Subject: [PATCH 1598/2402] samples: drivers: dac: support frdm_mcxn947 dac example add support frdm_mcxn947 dac example Signed-off-by: Zhaoxiang Jin --- samples/drivers/dac/boards/frdm_mcxn947.overlay | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 samples/drivers/dac/boards/frdm_mcxn947.overlay diff --git a/samples/drivers/dac/boards/frdm_mcxn947.overlay b/samples/drivers/dac/boards/frdm_mcxn947.overlay new file mode 100644 index 00000000000..183cad3f018 --- /dev/null +++ b/samples/drivers/dac/boards/frdm_mcxn947.overlay @@ -0,0 +1,17 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + + /* + * Please note on the FRDM-MCXN947 board, DAC0 output signal port is J1-4. + */ + zephyr,user { + dac = <&dac0>; + dac-channel-id = <0>; + dac-resolution = <12>; + }; +}; From ddf31820b02ac4e7a848bf68c5949040fa37945a Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Mon, 25 Mar 2024 20:28:02 +0900 Subject: [PATCH 1599/2402] doc: scripts: redirects: fix redirect for led_strip samples Since I have integrated some samples into samples/drivers/led_strip, seting up redirection from the deleted apa102, lpd8806, and ws2812. Signed-off-by: TOKITA Hiroshi --- doc/_scripts/redirects.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/_scripts/redirects.py b/doc/_scripts/redirects.py index 87fc9eebc23..8cb81cdae05 100644 --- a/doc/_scripts/redirects.py +++ b/doc/_scripts/redirects.py @@ -172,6 +172,9 @@ ('reference/usermode/syscalls', 'kernel/usermode/syscalls'), ('reference/util/index', 'kernel/util/index'), ('samples/drivers/kscan_touch', 'samples/subsys/input/input'), + ('samples/drivers/led_apa102/README', 'samples/drivers/led_strip/README'), + ('samples/drivers/led_lpd8806/README', 'samples/drivers/led_strip/README'), + ('samples/drivers/led_ws2812/README', 'samples/drivers/led_strip/README'), ('samples/net/cloud/google_iot_mqtt/README', 'samples/net/cloud/cloud'), ('samples/sensor/wsen_hids/README', 'samples/sensor/sensor'), ('samples/sensor/wsen_itds/README', 'samples/sensor/sensor'), From ba932f60af94be23e40e776d0ad95323c79a0539 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Mon, 25 Mar 2024 16:40:45 +0100 Subject: [PATCH 1600/2402] mgmt: hawkbit: remove hb_context.url_buffer_size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit remove hb_context.url_buffer_size and replace it with sizeof(hb_context.url_buffer) Signed-off-by: Fin Maaß --- subsys/mgmt/hawkbit/hawkbit.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c index e3ea6592b64..305f5b47921 100644 --- a/subsys/mgmt/hawkbit/hawkbit.c +++ b/subsys/mgmt/hawkbit/hawkbit.c @@ -80,7 +80,6 @@ static struct hawkbit_context { int32_t action_id; uint8_t *response_data; int32_t json_action_id; - size_t url_buffer_size; struct hawkbit_download dl; struct http_request http_req; struct flash_img_context flash_ctx; @@ -1012,8 +1011,7 @@ enum hawkbit_response hawkbit_probe(void) memset(hb_context.url_buffer, 0, sizeof(hb_context.url_buffer)); hb_context.dl.http_content_size = 0; hb_context.dl.downloaded_size = 0; - hb_context.url_buffer_size = URL_BUFFER_SIZE; - snprintk(hb_context.url_buffer, hb_context.url_buffer_size, "%s/%s-%s", + snprintk(hb_context.url_buffer, sizeof(hb_context.url_buffer), "%s/%s-%s", HAWKBIT_JSON_URL, CONFIG_BOARD, device_id); memset(&hawkbit_results.base, 0, sizeof(hawkbit_results.base)); @@ -1040,9 +1038,9 @@ enum hawkbit_response hawkbit_probe(void) ret = hawkbit_find_cancelAction_base(&hawkbit_results.base, cancel_base); memset(hb_context.url_buffer, 0, sizeof(hb_context.url_buffer)); hb_context.dl.http_content_size = 0; - hb_context.url_buffer_size = URL_BUFFER_SIZE; - snprintk(hb_context.url_buffer, hb_context.url_buffer_size, "%s/%s-%s/%s/feedback", - HAWKBIT_JSON_URL, CONFIG_BOARD, device_id, cancel_base); + snprintk(hb_context.url_buffer, sizeof(hb_context.url_buffer), + "%s/%s-%s/%s/feedback", HAWKBIT_JSON_URL, CONFIG_BOARD, device_id, + cancel_base); memset(&hawkbit_results.cancel, 0, sizeof(hawkbit_results.cancel)); if (!send_request(HTTP_POST, HAWKBIT_CLOSE, HAWKBIT_STATUS_FINISHED_SUCCESS, @@ -1061,8 +1059,7 @@ enum hawkbit_response hawkbit_probe(void) hawkbit_results.base._links.configData.href); memset(hb_context.url_buffer, 0, sizeof(hb_context.url_buffer)); hb_context.dl.http_content_size = 0; - hb_context.url_buffer_size = URL_BUFFER_SIZE; - snprintk(hb_context.url_buffer, hb_context.url_buffer_size, "%s/%s-%s/%s", + snprintk(hb_context.url_buffer, sizeof(hb_context.url_buffer), "%s/%s-%s/%s", HAWKBIT_JSON_URL, CONFIG_BOARD, device_id, "configData"); if (!send_request(HTTP_PUT, HAWKBIT_CONFIG_DEVICE, HAWKBIT_STATUS_FINISHED_SUCCESS, @@ -1088,9 +1085,8 @@ enum hawkbit_response hawkbit_probe(void) memset(hb_context.url_buffer, 0, sizeof(hb_context.url_buffer)); hb_context.dl.http_content_size = 0; hb_context.dl.downloaded_size = 0; - hb_context.url_buffer_size = URL_BUFFER_SIZE; - snprintk(hb_context.url_buffer, hb_context.url_buffer_size, "%s/%s-%s/%s", HAWKBIT_JSON_URL, - CONFIG_BOARD, device_id, deployment_base); + snprintk(hb_context.url_buffer, sizeof(hb_context.url_buffer), "%s/%s-%s/%s", + HAWKBIT_JSON_URL, CONFIG_BOARD, device_id, deployment_base); memset(&hawkbit_results.dep, 0, sizeof(hawkbit_results.dep)); memset(hb_context.response_data, 0, RESPONSE_BUFFER_SIZE); @@ -1121,8 +1117,7 @@ enum hawkbit_response hawkbit_probe(void) LOG_INF("Preventing repeated attempt to install %d", hb_context.json_action_id); hb_context.dl.http_content_size = 0; memset(hb_context.url_buffer, 0, sizeof(hb_context.url_buffer)); - hb_context.url_buffer_size = URL_BUFFER_SIZE; - snprintk(hb_context.url_buffer, hb_context.url_buffer_size, + snprintk(hb_context.url_buffer, sizeof(hb_context.url_buffer), "%s/%s-%s/%s/%d/feedback", HAWKBIT_JSON_URL, CONFIG_BOARD, device_id, "deploymentBase", hb_context.json_action_id); @@ -1141,9 +1136,7 @@ enum hawkbit_response hawkbit_probe(void) hb_context.dl.http_content_size = 0; memset(hb_context.url_buffer, 0, sizeof(hb_context.url_buffer)); - hb_context.url_buffer_size = URL_BUFFER_SIZE; - - snprintk(hb_context.url_buffer, hb_context.url_buffer_size, "%s", download_http); + snprintk(hb_context.url_buffer, sizeof(hb_context.url_buffer), "%s", download_http); flash_img_init(&hb_context.flash_ctx); From 625f0285902fa54de53ae59862a1d8bbe40299b8 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 22 Mar 2024 20:24:37 +0000 Subject: [PATCH 1601/2402] dts: arm: nxp: rw6xx: add DMIC to devicetree Add DMIC to devicetree for RW61x SOC Signed-off-by: Daniel DeGrasse --- dts/arm/nxp/nxp_rw6xx_common.dtsi | 38 +++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index d6cc8643a8b..d91976e600c 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -303,6 +303,44 @@ }; }; + dmic0: dmic@121000 { + #address-cells=<1>; + #size-cells=<0>; + compatible = "nxp,dmic"; + reg = <0x121000 0x1000>; + interrupts = <25 0>; + status = "disabled"; + clocks = <&clkctl1 MCUX_DMIC_CLK>; + + pdmc0: dmic-channel@0 { + reg = <0>; + compatible = "nxp,dmic-channel"; + dmas = <&dma0 16>; + status = "disabled"; + }; + + pdmc1: dmic-channel@1 { + reg = <1>; + compatible = "nxp,dmic-channel"; + dmas = <&dma0 17>; + status = "disabled"; + }; + + pdmc2: dmic-channel@2 { + reg = <2>; + compatible = "nxp,dmic-channel"; + dmas = <&dma0 18>; + status = "disabled"; + }; + + pdmc3: dmic-channel@3 { + reg = <3>; + compatible = "nxp,dmic-channel"; + dmas = <&dma0 19>; + status = "disabled"; + }; + }; + }; &flexspi { From 5e241970f584de935451ee50ff33e3ff9f82b17e Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 22 Mar 2024 20:25:19 +0000 Subject: [PATCH 1602/2402] soc: nxp: rw: enable DMIC clock at boot Enable DMIC clock at boot, so that RW DMIC IP will be useable by driver Signed-off-by: Daniel DeGrasse --- soc/nxp/rw/soc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c index 350b019a2cd..fc42797a09c 100644 --- a/soc/nxp/rw/soc.c +++ b/soc/nxp/rw/soc.c @@ -209,6 +209,15 @@ __ramfunc void clock_init(void) #endif #endif /* CONFIG_SPI */ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(dmic0), okay) && CONFIG_AUDIO_DMIC_MCUX + /* Clock DMIC from Audio PLL. PLL output is sourced from AVPLL + * channel 1, which is clocked at 12.288 MHz. We can divide this + * by 4 to achieve the desired DMIC bit clk of 3.072 MHz + */ + CLOCK_AttachClk(kAUDIO_PLL_to_DMIC_CLK); + CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 4); +#endif + #ifdef CONFIG_COUNTER_MCUX_CTIMER #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ctimer0), nxp_lpc_ctimer, okay)) CLOCK_AttachClk(kSFRO_to_CTIMER0); From d5eb3285445f6e4487fc409e0b8cc6822abd0c1d Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 22 Mar 2024 20:26:15 +0000 Subject: [PATCH 1603/2402] boards: nxp: rd_rw612_bga: enable DMIC Enable DMIC on RW612 BGA board. The DMIC is enabled for both onboard MEMS microphones for this board, and the board is enabled with the DMIC sample and test Signed-off-by: Daniel DeGrasse --- boards/nxp/rd_rw612_bga/doc/index.rst | 2 + .../rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi | 10 +++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 42 +++++++++++++++++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml | 1 + .../audio/dmic/boards/rd_rw612_bga.overlay | 3 ++ .../dmic_api/boards/rd_rw612_bga.overlay | 39 +++++++++++++++++ 6 files changed, 97 insertions(+) create mode 100644 samples/drivers/audio/dmic/boards/rd_rw612_bga.overlay create mode 100644 tests/drivers/audio/dmic_api/boards/rd_rw612_bga.overlay diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index 3797d1bdb9f..9f115e4445a 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -49,6 +49,8 @@ Supported Features +-----------+------------+-----------------------------------+ | TRNG | on-chip | entropy | +-----------+------------+-----------------------------------+ +| DMIC | on-chip | dmic | ++-----------+------------+-----------------------------------+ | WWDT | on-chip | watchdog | +-----------+------------+-----------------------------------+ | CTIMER | on-chip | counter | diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi index d55a83fff70..f7b131a6285 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi @@ -32,6 +32,16 @@ }; }; + pinmux_dmic0: pinmux_dmic0 { + group0 { + pinmux = ; + slew-rate = "fast"; + }; + }; + pinmux_flexspi: pinmux_flexspi { group0 { pinmux = ; + pinctrl-names = "default"; + use2fs; + status = "okay"; +}; + +/* Configure pdm channels 0-3 with gain, and cutoff settings + * appropriate for the attached MEMS microphones. + * Note that PDMC0/PDMC1 and PDMC2/PDMC3 are each connected to the same + * microphone. For best results, read from PDM HW channel 0 as left channel, + * and PDM HW channel 1 as right channel. + */ +&pdmc0 { + status = "okay"; + gainshift = <3>; + dc-cutoff = "155hz"; + dc-gain = <1>; +}; + +&pdmc1 { + status = "okay"; + gainshift = <3>; + dc-cutoff = "155hz"; + dc-gain = <1>; +}; + +&pdmc2 { + status = "okay"; + gainshift = <3>; + dc-cutoff = "155hz"; + dc-gain = <1>; +}; + +&pdmc3 { + status = "okay"; + gainshift = <3>; + dc-cutoff = "155hz"; + dc-gain = <1>; +}; + &dma0 { status = "okay"; }; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml index 61d73f05f95..0457f38a79c 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -16,6 +16,7 @@ ram: 960 flash: 65536 supported: - dma + - dmic - gpio - spi - i2c diff --git a/samples/drivers/audio/dmic/boards/rd_rw612_bga.overlay b/samples/drivers/audio/dmic/boards/rd_rw612_bga.overlay new file mode 100644 index 00000000000..ce71fa65f01 --- /dev/null +++ b/samples/drivers/audio/dmic/boards/rd_rw612_bga.overlay @@ -0,0 +1,3 @@ +dmic_dev: &dmic0 { + status = "okay"; +}; diff --git a/tests/drivers/audio/dmic_api/boards/rd_rw612_bga.overlay b/tests/drivers/audio/dmic_api/boards/rd_rw612_bga.overlay new file mode 100644 index 00000000000..49018187e3e --- /dev/null +++ b/tests/drivers/audio/dmic_api/boards/rd_rw612_bga.overlay @@ -0,0 +1,39 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright 2023 NXP + */ + +/* Enable PDM channels 0-3, + * Gain settings are configured for testing with a PDM generator, + * using a -20dbFS sine wave. + */ +&dmic0 { + dmic-channel@0 { + status = "okay"; + gainshift = <2>; + dc-cutoff = "155hz"; + dc-gain = <1>; + }; + + dmic-channel@1 { + status = "okay"; + gainshift = <2>; + dc-cutoff = "155hz"; + dc-gain = <1>; + }; + + dmic-channel@2 { + status = "okay"; + gainshift = <2>; + dc-cutoff = "155hz"; + dc-gain = <1>; + }; + + dmic-channel@3 { + status = "okay"; + gainshift = <2>; + dc-cutoff = "155hz"; + dc-gain = <1>; + }; +}; From d68db182b908982711ef86cb5d490100d2cdeaca Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Mon, 25 Mar 2024 11:49:05 -0700 Subject: [PATCH 1604/2402] random: Remove duplicated code All implementations of random number generator where duplicating logic for sys_rand32_get. Since this subsystem already has a logic to generate random values of arbitrary size, we can generically implement sys_rand32_get on top of that. Signed-off-by: Flavio Ceolin --- include/zephyr/random/random.h | 29 ++++++++++++++++++--------- subsys/random/rand32_entropy_device.c | 25 ----------------------- subsys/random/rand32_handlers.c | 6 ------ subsys/random/rand32_timer.c | 4 ++-- subsys/random/rand32_xoshiro128.c | 9 --------- 5 files changed, 21 insertions(+), 52 deletions(-) diff --git a/include/zephyr/random/random.h b/include/zephyr/random/random.h index e9c2e2968f5..bbfdd98c421 100644 --- a/include/zephyr/random/random.h +++ b/include/zephyr/random/random.h @@ -38,16 +38,6 @@ extern "C" { #endif -/** - * @brief Return a 32-bit random value that should pass general - * randomness tests. - * - * @note The random value returned is not a cryptographically secure - * random number value. - * - * @return 32-bit random value. - */ -__syscall uint32_t sys_rand32_get(void); /** * @brief Fill the destination buffer with random data values that should @@ -77,6 +67,25 @@ __syscall void sys_rand_get(void *dst, size_t len); */ __syscall int sys_csrand_get(void *dst, size_t len); +/** + * @brief Return a 32-bit random value that should pass general + * randomness tests. + * + * @note The random value returned is not a cryptographically secure + * random number value. + * + * @return 32-bit random value. + */ +static inline uint32_t sys_rand32_get(void) +{ + uint32_t ret; + + sys_rand_get(&ret, sizeof(ret)); + + return ret; +} + + #ifdef __cplusplus } #endif diff --git a/subsys/random/rand32_entropy_device.c b/subsys/random/rand32_entropy_device.c index 92ce441911e..2ffc569b690 100644 --- a/subsys/random/rand32_entropy_device.c +++ b/subsys/random/rand32_entropy_device.c @@ -12,31 +12,6 @@ static const struct device *const entropy_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_entropy)); -#if defined(CONFIG_ENTROPY_DEVICE_RANDOM_GENERATOR) -uint32_t z_impl_sys_rand32_get(void) -{ - uint32_t random_num; - int ret; - - __ASSERT(device_is_ready(entropy_dev), "Entropy device %s not ready", - entropy_dev->name); - - ret = entropy_get_entropy(entropy_dev, (uint8_t *)&random_num, - sizeof(random_num)); - if (unlikely(ret < 0)) { - /* Use system timer in case the entropy device couldn't deliver - * 32-bit of data. There's not much that can be done in this - * situation. An __ASSERT() isn't used here as the HWRNG might - * still be gathering entropy during early boot situations. - */ - - random_num = k_cycle_get_32(); - } - - return random_num; -} -#endif /* CONFIG_ENTROPY_DEVICE_RANDOM_GENERATOR */ - static int rand_get(uint8_t *dst, size_t outlen, bool csrand) { uint32_t random_num; diff --git a/subsys/random/rand32_handlers.c b/subsys/random/rand32_handlers.c index 38344a00190..77bf068ed0d 100644 --- a/subsys/random/rand32_handlers.c +++ b/subsys/random/rand32_handlers.c @@ -7,12 +7,6 @@ #include #include -static inline uint32_t z_vrfy_sys_rand32_get(void) -{ - return z_impl_sys_rand32_get(); -} -#include - static inline void z_vrfy_sys_rand_get(void *dst, size_t len) { K_OOPS(K_SYSCALL_MEMORY_WRITE(dst, len)); diff --git a/subsys/random/rand32_timer.c b/subsys/random/rand32_timer.c index 4232dccfbc8..9d2f5cefbf0 100644 --- a/subsys/random/rand32_timer.c +++ b/subsys/random/rand32_timer.c @@ -33,7 +33,7 @@ static struct k_spinlock rand32_lock; * * @return a 32-bit number */ -uint32_t z_impl_sys_rand32_get(void) +static inline uint32_t rand32_get(void) { /* initial seed value */ static uint64_t state = (uint64_t)CONFIG_TIMER_RANDOM_INITIAL_STATE; @@ -64,7 +64,7 @@ void z_impl_sys_rand_get(void *dst, size_t outlen) uint32_t ret; while (outlen) { - ret = sys_rand32_get(); + ret = rand32_get(); blocksize = MIN(outlen, sizeof(ret)); (void)memcpy((void *)udst, &ret, blocksize); udst += blocksize; diff --git a/subsys/random/rand32_xoshiro128.c b/subsys/random/rand32_xoshiro128.c index 2a68f5515a8..4264c78a612 100644 --- a/subsys/random/rand32_xoshiro128.c +++ b/subsys/random/rand32_xoshiro128.c @@ -91,15 +91,6 @@ static uint32_t xoshiro128_next(void) return result; } -uint32_t z_impl_sys_rand32_get(void) -{ - if (unlikely(!initialized)) { - xoshiro128_init_state(); - } - - return xoshiro128_next(); -} - void z_impl_sys_rand_get(void *dst, size_t outlen) { size_t blocks = outlen / sizeof(uint32_t); From 85a7b27f97713cb917258ac0a276c851a614c5a6 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Mon, 25 Mar 2024 12:40:44 -0700 Subject: [PATCH 1605/2402] random: Rename source files s/rand32/random. Signed-off-by: Flavio Ceolin --- subsys/random/CMakeLists.txt | 10 +++++----- subsys/random/{rand32_ctr_drbg.c => random_ctr_drbg.c} | 0 ...rand32_entropy_device.c => random_entropy_device.c} | 0 subsys/random/{rand32_handlers.c => random_handlers.c} | 0 subsys/random/{rand32_timer.c => random_timer.c} | 0 .../{rand32_xoshiro128.c => random_xoshiro128.c} | 0 6 files changed, 5 insertions(+), 5 deletions(-) rename subsys/random/{rand32_ctr_drbg.c => random_ctr_drbg.c} (100%) rename subsys/random/{rand32_entropy_device.c => random_entropy_device.c} (100%) rename subsys/random/{rand32_handlers.c => random_handlers.c} (100%) rename subsys/random/{rand32_timer.c => random_timer.c} (100%) rename subsys/random/{rand32_xoshiro128.c => random_xoshiro128.c} (100%) diff --git a/subsys/random/CMakeLists.txt b/subsys/random/CMakeLists.txt index cde2431ae2e..bdda2f42571 100644 --- a/subsys/random/CMakeLists.txt +++ b/subsys/random/CMakeLists.txt @@ -5,7 +5,7 @@ if (CONFIG_ENTROPY_DEVICE_RANDOM_GENERATOR OR CONFIG_XOSHIRO_RANDOM_GENERATOR) zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/random/random.h) zephyr_library() -zephyr_library_sources_ifdef(CONFIG_USERSPACE rand32_handlers.c) +zephyr_library_sources_ifdef(CONFIG_USERSPACE random_handlers.c) endif() if (CONFIG_TIMER_RANDOM_GENERATOR) @@ -15,12 +15,12 @@ if (CONFIG_TIMER_RANDOM_GENERATOR) Use it carefully.") endif() -zephyr_library_sources_ifdef(CONFIG_TIMER_RANDOM_GENERATOR rand32_timer.c) -zephyr_library_sources_ifdef(CONFIG_XOSHIRO_RANDOM_GENERATOR rand32_xoshiro128.c) -zephyr_library_sources_ifdef(CONFIG_CTR_DRBG_CSPRNG_GENERATOR rand32_ctr_drbg.c) +zephyr_library_sources_ifdef(CONFIG_TIMER_RANDOM_GENERATOR random_timer.c) +zephyr_library_sources_ifdef(CONFIG_XOSHIRO_RANDOM_GENERATOR random_xoshiro128.c) +zephyr_library_sources_ifdef(CONFIG_CTR_DRBG_CSPRNG_GENERATOR random_ctr_drbg.c) if (CONFIG_ENTROPY_DEVICE_RANDOM_GENERATOR OR CONFIG_HARDWARE_DEVICE_CS_GENERATOR) -zephyr_library_sources(rand32_entropy_device.c) +zephyr_library_sources(random_entropy_device.c) endif() if (CONFIG_CTR_DRBG_CSPRNG_GENERATOR) diff --git a/subsys/random/rand32_ctr_drbg.c b/subsys/random/random_ctr_drbg.c similarity index 100% rename from subsys/random/rand32_ctr_drbg.c rename to subsys/random/random_ctr_drbg.c diff --git a/subsys/random/rand32_entropy_device.c b/subsys/random/random_entropy_device.c similarity index 100% rename from subsys/random/rand32_entropy_device.c rename to subsys/random/random_entropy_device.c diff --git a/subsys/random/rand32_handlers.c b/subsys/random/random_handlers.c similarity index 100% rename from subsys/random/rand32_handlers.c rename to subsys/random/random_handlers.c diff --git a/subsys/random/rand32_timer.c b/subsys/random/random_timer.c similarity index 100% rename from subsys/random/rand32_timer.c rename to subsys/random/random_timer.c diff --git a/subsys/random/rand32_xoshiro128.c b/subsys/random/random_xoshiro128.c similarity index 100% rename from subsys/random/rand32_xoshiro128.c rename to subsys/random/random_xoshiro128.c From dab93222dac6e4c7344dbfc44e0abe21f34d0eba Mon Sep 17 00:00:00 2001 From: Patryk Duda Date: Wed, 27 Mar 2024 18:22:47 +0100 Subject: [PATCH 1606/2402] boards: google: dragonclaw: Fix SoC model Google Dragonclaw board uses STM32F412CGU6 MCU, so fix include in DTS and board.yml Signed-off-by: Patryk Duda --- boards/google/dragonclaw/board.yml | 2 +- boards/google/dragonclaw/google_dragonclaw.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/google/dragonclaw/board.yml b/boards/google/dragonclaw/board.yml index 28e8b84ab4f..18e233f99b6 100644 --- a/boards/google/dragonclaw/board.yml +++ b/boards/google/dragonclaw/board.yml @@ -2,4 +2,4 @@ board: name: google_dragonclaw vendor: google socs: - - name: stm32f412zx + - name: stm32f412cx diff --git a/boards/google/dragonclaw/google_dragonclaw.dts b/boards/google/dragonclaw/google_dragonclaw.dts index 579adf4026f..a0f7932d8ae 100644 --- a/boards/google/dragonclaw/google_dragonclaw.dts +++ b/boards/google/dragonclaw/google_dragonclaw.dts @@ -7,7 +7,7 @@ /dts-v1/; #include -#include +#include / { model = "Google Dragonclaw development board"; From 36ad49bd650012df674213a2e681755cb0b9ffab Mon Sep 17 00:00:00 2001 From: Tristan Honscheid Date: Wed, 30 Aug 2023 16:23:56 -0600 Subject: [PATCH 1607/2402] twister: Remove ANSI sequences before writing to handler.log ANSI color is great for viewing output in a terminal, but currently it also gets written out to the `handler.log` file. Text editors usually don't render these, resulting in a hard-to-read file with a lot of gibberish interspered. This commit strips ANSI sequences from lines before writing them to the handler log file. This change does not affect what is printed in Twister's console output, so one would still see the colors there. Signed-off-by: Tristan Honscheid --- scripts/pylib/twister/twisterlib/environment.py | 6 ++++-- scripts/pylib/twister/twisterlib/handlers.py | 8 ++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/environment.py b/scripts/pylib/twister/twisterlib/environment.py index adf31a4e499..e8bc0d9f54b 100644 --- a/scripts/pylib/twister/twisterlib/environment.py +++ b/scripts/pylib/twister/twisterlib/environment.py @@ -863,6 +863,9 @@ def parse_arguments(parser, args, options = None): return options +def strip_ansi_sequences(s: str) -> str: + """Remove ANSI escape sequences from a string.""" + return re.sub(r'\x1B(?:[@-Z\\-_]|\[[0-?]*[ -/]*[@-~])', "", s) class TwisterEnv: @@ -967,8 +970,7 @@ def run_cmake_script(args=[]): # for instance if twister is executed from inside a makefile. In such a # scenario it is then necessary to remove them, as otherwise the JSON decoding # will fail. - ansi_escape = re.compile(r'\x1B(?:[@-Z\\-_]|\[[0-?]*[ -/]*[@-~])') - out = ansi_escape.sub('', out.decode()) + out = strip_ansi_sequences(out.decode()) if p.returncode == 0: msg = "Finished running %s" % (args[0]) diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py index ed0ee9003b1..ae283c1722e 100755 --- a/scripts/pylib/twister/twisterlib/handlers.py +++ b/scripts/pylib/twister/twisterlib/handlers.py @@ -20,7 +20,7 @@ import time from queue import Queue, Empty -from twisterlib.environment import ZEPHYR_BASE +from twisterlib.environment import ZEPHYR_BASE, strip_ansi_sequences from twisterlib.error import TwisterException sys.path.insert(0, os.path.join(ZEPHYR_BASE, "scripts/pylib/build_helpers")) from domains import Domains @@ -216,7 +216,7 @@ def _output_handler(self, proc, harness): else: stripped_line = line_decoded.rstrip() logger.debug("OUTPUT: %s", stripped_line) - log_out_fp.write(line_decoded) + log_out_fp.write(strip_ansi_sequences(line_decoded)) log_out_fp.flush() harness.handle(stripped_line) if harness.state: @@ -426,7 +426,7 @@ def monitor_serial(self, ser, halt_event, harness): sl = serial_line.decode('utf-8', 'ignore').lstrip() logger.debug("DEVICE: {0}".format(sl.rstrip())) - log_out_fp.write(sl.encode('utf-8')) + log_out_fp.write(strip_ansi_sequences(sl).encode('utf-8')) log_out_fp.flush() harness.handle(sl.rstrip()) @@ -921,7 +921,7 @@ def _thread(handler, timeout, outdir, logfile, fifo_fn, pid_fn, results, continue # line contains a full line of data output from QEMU - log_out_fp.write(line) + log_out_fp.write(strip_ansi_sequences(line)) log_out_fp.flush() line = line.rstrip() logger.debug(f"QEMU ({pid}): {line}") From b06602c3f3027ec5965bc4b61cba39fa2a077a91 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 28 Mar 2024 12:47:17 +0200 Subject: [PATCH 1608/2402] tests: net: vlan: Fix the socket API usage The tests should use zsock_ APIs after the commit 0512e7ffaead7eeb2d3599cc71e439180e221e4a Signed-off-by: Jukka Rissanen --- tests/net/vlan/src/main.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/net/vlan/src/main.c b/tests/net/vlan/src/main.c index 5d53bfd4779..b9eada2a627 100644 --- a/tests/net/vlan/src/main.c +++ b/tests/net/vlan/src/main.c @@ -794,9 +794,9 @@ ZTEST(net_vlan, test_vlan_ipv6_sendto_recvfrom) ret = add_neighbor(iface, &server_addr.sin6_addr); zassert_true(ret, "Cannot add neighbor"); - ret = bind(server_sock, - (struct sockaddr *)&server_addr, - sizeof(server_addr)); + ret = zsock_bind(server_sock, + (struct sockaddr *)&server_addr, + sizeof(server_addr)); zassert_equal(ret, 0, "bind failed"); test_started = true; @@ -808,9 +808,9 @@ ZTEST(net_vlan, test_vlan_ipv6_sendto_recvfrom) (struct sockaddr *)&server_addr, sizeof(server_addr)); - ret = close(client_sock); + ret = zsock_close(client_sock); zassert_equal(ret, 0, "close failed"); - ret = close(server_sock); + ret = zsock_close(server_sock); zassert_equal(ret, 0, "close failed"); } From dfe34ca03a16c21cdfe5ff196372df25a37cded8 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 28 Mar 2024 11:47:58 +0100 Subject: [PATCH 1609/2402] tests/bsim/run_parallel: Create folder for results xml if missing Create the folder for the results if it does not exist. Fixes these warnings in CI: ``` touch: cannot touch '/__w/zephyr/zephyr/./bsim_bt/ 53_bsim_results.xml': No such file or directory realpath: /__w/zephyr/zephyr/./bsim_bt/ 53_bsim_results.xml: No such file or directory ``` Signed-off-by: Alberto Escolar Piedras --- tests/bsim/run_parallel.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/bsim/run_parallel.sh b/tests/bsim/run_parallel.sh index 80e74512ef3..cb9a3d4ed80 100755 --- a/tests/bsim/run_parallel.sh +++ b/tests/bsim/run_parallel.sh @@ -63,6 +63,8 @@ tmp_res_file=tmp.xml all_cases_a=( $all_cases ) n_cases=$((${#all_cases_a[@]})) + +mkdir -p $(dirname ${RESULTS_FILE}) touch ${RESULTS_FILE} echo "Attempting to run ${n_cases} cases (logging to \ `realpath ${RESULTS_FILE}`)" From 04a74ce107e5576d7c114cfba4066e7b854bcde6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 13 Feb 2024 16:12:14 +0100 Subject: [PATCH 1610/2402] shell: rtt: Add detection of host presence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If host is not reading RTT data (because there is no PC connection or RTT reading application is not running on the host), thread will stuck continuously trying to write to RTT. All threads with equal or lower priority are blocked then. Adding detection of that case and if host is not reading data for configurable period then data is dropped until host accepts new data. Similar solution is using in RTT logging backend. Signed-off-by: Krzysztof Chruściński --- subsys/shell/backends/Kconfig.backends | 18 ++++++ subsys/shell/backends/shell_rtt.c | 79 ++++++++++++++++++++++---- 2 files changed, 87 insertions(+), 10 deletions(-) diff --git a/subsys/shell/backends/Kconfig.backends b/subsys/shell/backends/Kconfig.backends index 0baf7772a77..a78c9247365 100644 --- a/subsys/shell/backends/Kconfig.backends +++ b/subsys/shell/backends/Kconfig.backends @@ -185,6 +185,7 @@ config SHELL_BACKEND_RTT bool "RTT backend" select CONSOLE select RTT_CONSOLE + select SEGGER_RTT_CUSTOM_LOCKING depends on USE_SEGGER_RTT help Enable RTT backend. @@ -206,6 +207,23 @@ config SHELL_BACKEND_RTT_BUFFER Select index of up-buffer used for shell output, by default it uses terminal up-buffer and its settings. +config SHELL_BACKEND_RTT_RETRY_CNT + int "Number of retries" + default 4 + help + Number of TX retries before dropping the data and assuming that + RTT session is inactive. + +config SHELL_BACKEND_RTT_RETRY_DELAY_MS + int "Delay between TX retries in milliseconds" + default 5 + help + Sleep period between TX retry attempts. During RTT session, host pulls + data periodically. Period starts from 1-2 milliseconds and can be + increased if traffic on RTT increases (also from host to device). In + case of heavy traffic data can be lost and it may be necessary to + increase delay or number of retries. + config SHELL_RTT_RX_POLL_PERIOD int "RX polling period (in milliseconds)" default 10 diff --git a/subsys/shell/backends/shell_rtt.c b/subsys/shell/backends/shell_rtt.c index 6490975893a..4a874ba9ce8 100644 --- a/subsys/shell/backends/shell_rtt.c +++ b/subsys/shell/backends/shell_rtt.c @@ -9,6 +9,12 @@ #include #include +#define RTT_LOCK() \ + COND_CODE_0(CONFIG_SHELL_BACKEND_RTT_BUFFER, (SEGGER_RTT_LOCK()), ()) + +#define RTT_UNLOCK() \ + COND_CODE_0(CONFIG_SHELL_BACKEND_RTT_BUFFER, (SEGGER_RTT_UNLOCK()), ()) + #if IS_ENABLED(CONFIG_LOG_BACKEND_RTT) BUILD_ASSERT(!(CONFIG_SHELL_BACKEND_RTT_BUFFER == CONFIG_LOG_BACKEND_RTT_BUFFER), "Conflicting log RTT backend enabled on the same channel"); @@ -25,7 +31,8 @@ SHELL_DEFINE(shell_rtt, CONFIG_SHELL_PROMPT_RTT, &shell_transport_rtt, LOG_MODULE_REGISTER(shell_rtt, CONFIG_SHELL_RTT_LOG_LEVEL); -static bool rtt_blocking; +static bool panic_mode; +static bool host_present; static void timer_handler(struct k_timer *timer) { @@ -78,29 +85,81 @@ static int enable(const struct shell_transport *transport, bool blocking) struct shell_rtt *sh_rtt = (struct shell_rtt *)transport->ctx; if (blocking) { - rtt_blocking = true; k_timer_stop(&sh_rtt->timer); } return 0; } +static inline bool is_panic_mode(void) +{ + return panic_mode; +} + +static inline bool is_sync_mode(void) +{ + return (IS_ENABLED(CONFIG_LOG_MODE_IMMEDIATE) && IS_ENABLED(CONFIG_SHELL_LOG_BACKEND)) || + is_panic_mode(); +} + +static void on_failed_write(int retry_cnt) +{ + if (retry_cnt == 0) { + host_present = false; + } else if (is_sync_mode()) { + k_busy_wait(USEC_PER_MSEC * + CONFIG_SHELL_BACKEND_RTT_RETRY_DELAY_MS); + } else { + k_msleep(CONFIG_SHELL_BACKEND_RTT_RETRY_DELAY_MS); + } +} + +static void on_write(int retry_cnt) +{ + host_present = true; + if (is_panic_mode()) { + /* In panic mode block on each write until host reads it. This + * way it is ensured that if system resets all messages are read + * by the host. While pending on data being read by the host we + * must also detect situation where host is disconnected. + */ + while (SEGGER_RTT_HasDataUp(CONFIG_SHELL_BACKEND_RTT_BUFFER) && + host_present) { + on_failed_write(retry_cnt--); + } + } + +} + static int write(const struct shell_transport *transport, const void *data, size_t length, size_t *cnt) { struct shell_rtt *sh_rtt = (struct shell_rtt *)transport->ctx; - const uint8_t *data8 = (const uint8_t *)data; + int ret = 0; + int retry_cnt = CONFIG_SHELL_BACKEND_RTT_RETRY_CNT; + + do { + if (!is_sync_mode()) { + RTT_LOCK(); + ret = SEGGER_RTT_WriteSkipNoLock(CONFIG_SHELL_BACKEND_RTT_BUFFER, + data, length); + RTT_UNLOCK(); + } else { + ret = SEGGER_RTT_WriteSkipNoLock(CONFIG_SHELL_BACKEND_RTT_BUFFER, + data, length); + } - if (rtt_blocking) { - *cnt = SEGGER_RTT_WriteNoLock(CONFIG_SHELL_BACKEND_RTT_BUFFER, data8, length); - while (SEGGER_RTT_HasDataUp(CONFIG_SHELL_BACKEND_RTT_BUFFER)) { - /* empty */ + if (ret) { + on_write(retry_cnt); + } else if (host_present) { + retry_cnt--; + on_failed_write(retry_cnt); + } else { } - } else { - *cnt = SEGGER_RTT_Write(CONFIG_SHELL_BACKEND_RTT_BUFFER, data8, length); - } + } while ((ret == 0) && host_present); sh_rtt->handler(SHELL_TRANSPORT_EVT_TX_RDY, sh_rtt->context); + *cnt = length; return 0; } From 1de13cc96a42cd61117278a7a88577344883ea30 Mon Sep 17 00:00:00 2001 From: Marcin Szymczyk Date: Mon, 25 Mar 2024 14:30:12 +0100 Subject: [PATCH 1611/2402] soc: nordic: vpr: finish pending transactions before calling `wfi` To minimize time the CPU spends when preparing for sleep, make sure the pending transactions are finished before calling `wfi`. Signed-off-by: Marcin Szymczyk --- soc/nordic/common/vpr/soc_idle.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/soc/nordic/common/vpr/soc_idle.c b/soc/nordic/common/vpr/soc_idle.c index f5f77120e1a..a5c7378fee9 100644 --- a/soc/nordic/common/vpr/soc_idle.c +++ b/soc/nordic/common/vpr/soc_idle.c @@ -4,6 +4,7 @@ */ #include +#include #include /* @@ -13,6 +14,7 @@ void arch_cpu_idle(void) { sys_trace_idle(); + barrier_dsync_fence_full(); irq_unlock(MSTATUS_IEN); __asm__ volatile("wfi"); } @@ -20,6 +22,7 @@ void arch_cpu_idle(void) void arch_cpu_atomic_idle(unsigned int key) { sys_trace_idle(); + barrier_dsync_fence_full(); irq_unlock(MSTATUS_IEN); __asm__ volatile("wfi"); From 159617c8f6196bf9f69f2f6d47d31303c5a1c464 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 27 Mar 2024 00:55:21 +0530 Subject: [PATCH 1612/2402] net: wifi: Fix the Wi-Fi state check Once Wi-Fi is associated few parameters like listen interval and power-save mode cannot be changed. The state for association is "ASSOCIATED" and not completed. Even after state transitions to COMPLETE, it can still go back to other states, e.g., PTK/GTK renewal. Fix the state check. Signed-off-by: Chaitanya Tata --- subsys/net/l2/wifi/wifi_mgmt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/l2/wifi/wifi_mgmt.c b/subsys/net/l2/wifi/wifi_mgmt.c index bc844016fa5..5ef047e6c72 100644 --- a/subsys/net/l2/wifi/wifi_mgmt.c +++ b/subsys/net/l2/wifi/wifi_mgmt.c @@ -504,7 +504,7 @@ static int wifi_set_power_save(uint32_t mgmt_request, struct net_if *iface, return -EIO; } - if (info.state == WIFI_STATE_COMPLETED) { + if (info.state >= WIFI_STATE_ASSOCIATED) { ps_params->fail_reason = WIFI_PS_PARAM_FAIL_DEVICE_CONNECTED; return -ENOTSUP; From cb331c2371144f3c391856eec4417ce65cbf0957 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 27 Mar 2024 18:00:33 +0530 Subject: [PATCH 1613/2402] net: wifi: Add an build assert for checking states order This helps us sanity check the enumerations order isn't changed. Signed-off-by: Chaitanya Tata --- include/zephyr/net/wifi.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/zephyr/net/wifi.h b/include/zephyr/net/wifi.h index 0f19d7c4c18..a0840a2319a 100644 --- a/include/zephyr/net/wifi.h +++ b/include/zephyr/net/wifi.h @@ -138,6 +138,18 @@ enum wifi_iface_state { WIFI_STATE_UNKNOWN }; +/* We rely on the strict order of the enum values, so, let's check it */ +BUILD_ASSERT(WIFI_STATE_DISCONNECTED < WIFI_STATE_INTERFACE_DISABLED && + WIFI_STATE_INTERFACE_DISABLED < WIFI_STATE_INACTIVE && + WIFI_STATE_INACTIVE < WIFI_STATE_SCANNING && + WIFI_STATE_SCANNING < WIFI_STATE_AUTHENTICATING && + WIFI_STATE_AUTHENTICATING < WIFI_STATE_ASSOCIATING && + WIFI_STATE_ASSOCIATING < WIFI_STATE_ASSOCIATED && + WIFI_STATE_ASSOCIATED < WIFI_STATE_4WAY_HANDSHAKE && + WIFI_STATE_4WAY_HANDSHAKE < WIFI_STATE_GROUP_HANDSHAKE && + WIFI_STATE_GROUP_HANDSHAKE < WIFI_STATE_COMPLETED); + + /** Helper function to get user-friendly interface state name. */ const char *wifi_state_txt(enum wifi_iface_state state); From 9d18a7cf90d00bda636d6fd01d84156c9d11cd0d Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Thu, 28 Mar 2024 11:32:58 -0700 Subject: [PATCH 1614/2402] boards: qemu_x86_tiny: Fix linker script s/rand32_timer_*/random_timer_*/. It solves a problem introduced in 85a7b27f97713cb917258ac0a276c851a614c5a6 Signed-off-by: Flavio Ceolin --- boards/qemu/x86/qemu_x86_tiny.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/qemu/x86/qemu_x86_tiny.ld b/boards/qemu/x86/qemu_x86_tiny.ld index 44e8ff85358..623a11fb416 100644 --- a/boards/qemu/x86/qemu_x86_tiny.ld +++ b/boards/qemu/x86/qemu_x86_tiny.ld @@ -165,8 +165,8 @@ MEMORY *intc_loapic.c.obj(.##lsect##.*) \ *intc_system_apic.c.obj(.##lsect) \ *intc_system_apic.c.obj(.##lsect##.*) \ - *rand32_timer.c.obj(.##lsect) \ - *rand32_timer.c.obj(.##lsect##.*) \ + *random_timer.c.obj(.##lsect) \ + *random_timer.c.obj(.##lsect##.*) \ *uart_console.c.obj(.##lsect) \ *uart_console.c.obj(.##lsect##.*) From 6f01329e9d575126d74319650d0c4c48877c5bf4 Mon Sep 17 00:00:00 2001 From: Benedikt Streicher Date: Wed, 20 Mar 2024 16:23:41 +0100 Subject: [PATCH 1615/2402] cmake: sca: codechecker: search for 'CodeChecker' and 'codechecker' Let find_program in codechecker/sca.cmake search for both 'CodeChecker' and 'codechecker'. Before this change, I wasn't able to run CodeChecker because cmake couldn't find it. (Ubuntu 23.10, CodeChecker 6.21.0 installed via snap) Signed-off-by: Benedikt Streicher --- cmake/sca/codechecker/sca.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/sca/codechecker/sca.cmake b/cmake/sca/codechecker/sca.cmake index fd7d18ecea0..eeea1933716 100644 --- a/cmake/sca/codechecker/sca.cmake +++ b/cmake/sca/codechecker/sca.cmake @@ -2,7 +2,7 @@ # # Copyright (c) 2023, Basalte bv -find_program(CODECHECKER_EXE CodeChecker REQUIRED) +find_program(CODECHECKER_EXE NAMES CodeChecker codechecker REQUIRED) message(STATUS "Found SCA: CodeChecker (${CODECHECKER_EXE})") # CodeChecker uses the compile_commands.json as input From 5cbc16ac2cf1072e754336c10026fc2f0e7abc5b Mon Sep 17 00:00:00 2001 From: Zak Portnoy Date: Sun, 17 Mar 2024 10:22:57 +0200 Subject: [PATCH 1616/2402] boards: Update Xiao_BLE Sense DTS for pdm microphone Create regulator on GPIO for microphone supply Set pdm data and clk pins in pinctrl Add xiao_ble_sense overlay for dmic sample support Signed-off-by: Zak Portnoy --- boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi | 15 +++++++++++++++ boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts | 13 +++++++++++++ .../dmic/boards/xiao_ble_nrf52840_sense.overlay | 12 ++++++++++++ 3 files changed, 40 insertions(+) create mode 100644 samples/drivers/audio/dmic/boards/xiao_ble_nrf52840_sense.overlay diff --git a/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi b/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi index 7abfb3568d5..ea8cd0ed513 100644 --- a/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi +++ b/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi @@ -52,6 +52,21 @@ }; }; + pdm0_default: pdm0_default { + group1 { + psels = , + ; + }; + }; + + pdm0_sleep: pdm0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + pwm0_default: pwm0_default { group1 { psels = ; diff --git a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts index 343454806c6..b2f1769745f 100644 --- a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts +++ b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts @@ -13,6 +13,12 @@ model = "Seeed XIAO BLE Sense"; compatible = "seeed,xiao-ble", "seeed,xiao-ble-sense"; + msm261d3526hicpm-c-en { + compatible = "regulator-fixed"; + enable-gpios = <&gpio1 10 (NRF_GPIO_DRIVE_S0H1 | GPIO_ACTIVE_HIGH)>; + regulator-name = "MSM261D3526HICPM-C-EN"; + }; + lsm6ds3tr-c-en { compatible = "regulator-fixed-sync", "regulator-fixed"; enable-gpios = <&gpio1 8 (NRF_GPIO_DRIVE_S0H1 | GPIO_ACTIVE_HIGH)>; @@ -38,3 +44,10 @@ status = "okay"; }; }; + +&pdm0 { + pinctrl-0 = <&pdm0_default>; + pinctrl-1 = <&pdm0_sleep>; + pinctrl-names = "default", "sleep"; + clock-source = "PCLK32M"; +}; diff --git a/samples/drivers/audio/dmic/boards/xiao_ble_nrf52840_sense.overlay b/samples/drivers/audio/dmic/boards/xiao_ble_nrf52840_sense.overlay new file mode 100644 index 00000000000..a3919aa0d70 --- /dev/null +++ b/samples/drivers/audio/dmic/boards/xiao_ble_nrf52840_sense.overlay @@ -0,0 +1,12 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ +/ { + msm261d3526hicpm-c-en { + regulator-boot-on; + }; +}; + +dmic_dev: &pdm0 { + status = "okay"; +}; From d81162e0ccced1a19ea40d2672705f070d0baf4a Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Sun, 21 Jan 2024 20:27:19 +0800 Subject: [PATCH 1617/2402] dts: bindings: add device tree binding for i.MX RDC Add device tree binding file for the Resource Domain Controller (RDC) on i.MX SoCs. Signed-off-by: Hou Zhiqiang --- dts/bindings/misc/nxp,rdc.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 dts/bindings/misc/nxp,rdc.yaml diff --git a/dts/bindings/misc/nxp,rdc.yaml b/dts/bindings/misc/nxp,rdc.yaml new file mode 100644 index 00000000000..08431f94bfc --- /dev/null +++ b/dts/bindings/misc/nxp,rdc.yaml @@ -0,0 +1,16 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: | + NXP i.MX Resource Domain Controller (RDC) node. + The RDC provides robust support for the isolation of destination + memory mapped locations such as peripherals and memory to a single + core, a bus master, or set of cores and bus masters. + +compatible: "nxp,rdc" + +include: [base.yaml] + +properties: + reg: + required: true From 64dd04f775f7dff6fd0f5457681e82166c8df8d9 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Sun, 21 Jan 2024 23:17:39 +0800 Subject: [PATCH 1618/2402] dts: imx8m: add device node for RDC Add RDC device tree node for i.MX8M SoCs Cortex-A core dtsi. Signed-off-by: Hou Zhiqiang --- dts/arm64/nxp/nxp_mimx8mm_a53.dtsi | 7 ++++++- dts/arm64/nxp/nxp_mimx8mn_a53.dtsi | 7 ++++++- dts/arm64/nxp/nxp_mimx8mp_a53.dtsi | 7 ++++++- 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi index b7d80992d8e..94e0751010f 100644 --- a/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2020-2022 NXP + * Copyright 2020-2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -111,4 +111,9 @@ clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; status = "disabled"; }; + + rdc: rdc@303d0000 { + compatible = "nxp,rdc"; + reg = <0x303d0000 DT_SIZE_K(64)>; + }; }; diff --git a/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi index 8902380f46a..7d4796a6f72 100644 --- a/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -111,4 +111,9 @@ clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; status = "disabled"; }; + + rdc: rdc@303d0000 { + compatible = "nxp,rdc"; + reg = <0x303d0000 DT_SIZE_K(64)>; + }; }; diff --git a/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi index 6ca0b3159d3..efe3257b1e8 100644 --- a/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2020-2022 NXP + * Copyright 2020-2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -106,5 +106,10 @@ compatible = "nxp,imx8mp-pinctrl"; }; }; + + rdc: rdc@303d0000 { + compatible = "nxp,rdc"; + reg = <0x303d0000 DT_SIZE_K(64)>; + }; }; }; From 0aaab73780e6b5f0a007742d6d3eaeb2f447b4e7 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Sun, 21 Jan 2024 21:12:24 +0800 Subject: [PATCH 1619/2402] dts: bindings: add a new 'rdc' property to the i.MX IUART bindings The new property is used to set the access permission for the IUART device. Signed-off-by: Hou Zhiqiang --- dts/bindings/serial/nxp,imx-iuart.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/dts/bindings/serial/nxp,imx-iuart.yaml b/dts/bindings/serial/nxp,imx-iuart.yaml index 6abfb13b668..d5c6996845d 100644 --- a/dts/bindings/serial/nxp,imx-iuart.yaml +++ b/dts/bindings/serial/nxp,imx-iuart.yaml @@ -17,3 +17,7 @@ properties: pinctrl-names: required: true + + rdc: + type: int + description: Set the RDC permission for this peripheral From cd8029bf94ae2369a9dc55ba09fc8f65b3e65008 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Sun, 21 Jan 2024 21:09:14 +0800 Subject: [PATCH 1620/2402] dts: imx8mm: add 'rdc' property for UART nodes Assign the UART devices to both the Cortex-A and Cortex-M cores. Signed-off-by: Hou Zhiqiang --- dts/arm64/nxp/nxp_mimx8mm_a53.dtsi | 5 +++++ dts/arm64/nxp/nxp_mimx8mn_a53.dtsi | 5 +++++ dts/arm64/nxp/nxp_mimx8mp_a53.dtsi | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi index 94e0751010f..03d710396be 100644 --- a/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -99,6 +100,8 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ + RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -109,6 +112,8 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ + RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; diff --git a/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi index 7d4796a6f72..0492b850f3e 100644 --- a/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -99,6 +100,8 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ + RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -109,6 +112,8 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ + RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; diff --git a/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi index efe3257b1e8..65933c366e0 100644 --- a/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -84,6 +85,8 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ + RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -94,6 +97,8 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ + RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; From 04e8183165596906c97bd181bca890f16be17e95 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Sun, 21 Jan 2024 20:40:00 +0800 Subject: [PATCH 1621/2402] imx-rdc: add domain ID for Cortex-A53 core Add domain ID definition for Cortex-A53 core on i.MX8M SoCs. Signed-off-by: Hou Zhiqiang --- include/zephyr/dt-bindings/rdc/imx_rdc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/zephyr/dt-bindings/rdc/imx_rdc.h b/include/zephyr/dt-bindings/rdc/imx_rdc.h index 6133101418f..06103062cb9 100644 --- a/include/zephyr/dt-bindings/rdc/imx_rdc.h +++ b/include/zephyr/dt-bindings/rdc/imx_rdc.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2018, Diego Sueiro + * Copyright 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +10,7 @@ #define A7_DOMAIN_ID 0 #define A9_DOMAIN_ID 0 +#define A53_DOMAIN_ID 0 #define M4_DOMAIN_ID 1 #define M7_DOMAIN_ID 1 From 657e7edd9641279b059527d2af53aa2c39f8f7e8 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Sun, 21 Jan 2024 21:30:49 +0800 Subject: [PATCH 1622/2402] soc: mimx8m: add MMU mapping for RDC MMIO Add MMU mapping for RDC MMIO on i.MX8M SoCs. Signed-off-by: Hou Zhiqiang --- soc/nxp/imx/imx8m/a53/mmu_regions.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/soc/nxp/imx/imx8m/a53/mmu_regions.c b/soc/nxp/imx/imx8m/a53/mmu_regions.c index e6dd90ecc28..bc6be54f2be 100644 --- a/soc/nxp/imx/imx8m/a53/mmu_regions.c +++ b/soc/nxp/imx/imx8m/a53/mmu_regions.c @@ -1,5 +1,5 @@ /* - * Copyright 2020-2022 NXP + * Copyright 2020-2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -35,6 +35,11 @@ static const struct arm_mmu_region mmu_regions[] = { DT_REG_SIZE(DT_NODELABEL(iomuxc)), MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + MMU_REGION_FLAT_ENTRY("RDC", + DT_REG_ADDR(DT_NODELABEL(rdc)), + DT_REG_SIZE(DT_NODELABEL(rdc)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_imx_iuart, (MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS)) }; From 5062c51c496c7cfeeebf268ad2c14635f4c86731 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Sun, 21 Jan 2024 21:58:31 +0800 Subject: [PATCH 1623/2402] soc: mimx8m: set the UART devices RDC permission Add SoC initialization to set the UART RDC permission in the early phase, so that the it can be used by Zephyr on Cortex-A cores. Signed-off-by: Hou Zhiqiang --- soc/nxp/imx/imx8m/CMakeLists.txt | 1 + soc/nxp/imx/imx8m/Kconfig | 3 +++ soc/nxp/imx/imx8m/a53/soc.c | 46 ++++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) create mode 100644 soc/nxp/imx/imx8m/a53/soc.c diff --git a/soc/nxp/imx/imx8m/CMakeLists.txt b/soc/nxp/imx/imx8m/CMakeLists.txt index 8f319c6827a..8fdeaa518fa 100644 --- a/soc/nxp/imx/imx8m/CMakeLists.txt +++ b/soc/nxp/imx/imx8m/CMakeLists.txt @@ -32,6 +32,7 @@ if(CONFIG_SOC_MIMX8ML8_A53 OR CONFIG_SOC_MIMX8MM6_A53 OR CONFIG_SOC_MIMX8MN6_A53 zephyr_sources( a53/pinctrl_soc.h + a53/soc.c ) zephyr_sources_ifdef(CONFIG_ARM_MMU a53/mmu_regions.c) diff --git a/soc/nxp/imx/imx8m/Kconfig b/soc/nxp/imx/imx8m/Kconfig index 41b6dc6abd7..4020862a92c 100644 --- a/soc/nxp/imx/imx8m/Kconfig +++ b/soc/nxp/imx/imx8m/Kconfig @@ -8,6 +8,7 @@ config SOC_MIMX8MM6_A53 select HAS_MCUX if CLOCK_CONTROL select HAS_MCUX_CCM if CLOCK_CONTROL select HAS_MCUX_IOMUXC if PINCTRL + select HAS_MCUX_RDC config SOC_MIMX8MM6_M4 select ARM @@ -27,6 +28,7 @@ config SOC_MIMX8ML8_A53 select HAS_MCUX if CLOCK_CONTROL select HAS_MCUX_CCM if CLOCK_CONTROL select HAS_MCUX_IOMUXC if PINCTRL + select HAS_MCUX_RDC config SOC_MIMX8MN6_A53 select ARM64 @@ -35,6 +37,7 @@ config SOC_MIMX8MN6_A53 select HAS_MCUX if CLOCK_CONTROL select HAS_MCUX_CCM if CLOCK_CONTROL select HAS_MCUX_IOMUXC if PINCTRL + select HAS_MCUX_RDC config SOC_MIMX8MP_ADSP select XTENSA diff --git a/soc/nxp/imx/imx8m/a53/soc.c b/soc/nxp/imx/imx8m/a53/soc.c new file mode 100644 index 00000000000..412880e4023 --- /dev/null +++ b/soc/nxp/imx/imx8m/a53/soc.c @@ -0,0 +1,46 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +/* set RDC permission for peripherals */ +static void soc_rdc_init(void) +{ + rdc_domain_assignment_t assignment = {0}; + rdc_periph_access_config_t periphConfig; + + RDC_Init(RDC); + assignment.domainId = A53_DOMAIN_ID; + RDC_SetMasterDomainAssignment(RDC, kRDC_Master_A53, &assignment); + + RDC_GetDefaultPeriphAccessConfig(&periphConfig); + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) && DT_NODE_HAS_PROP(DT_NODELABEL(uart2), rdc) + periphConfig.periph = kRDC_Periph_UART2; + periphConfig.policy = RDC_DT_VAL(uart2); + RDC_SetPeriphAccessConfig(RDC, &periphConfig); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay) && DT_NODE_HAS_PROP(DT_NODELABEL(uart4), rdc) + periphConfig.periph = kRDC_Periph_UART4; + periphConfig.policy = RDC_DT_VAL(uart4); + RDC_SetPeriphAccessConfig(RDC, &periphConfig); +#endif +} + +static int soc_init(void) +{ + soc_rdc_init(); + return 0; +} + +SYS_INIT(soc_init, EARLY, 1); From 795044ec6dcbb12bbd5a8ef7da0f299926389509 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 22 Jan 2024 10:22:54 +0800 Subject: [PATCH 1624/2402] boards: nxp: imx8m: remove the UART RDC setup from guide As the RDC setup has been added in SoC initialization code. Signed-off-by: Hou Zhiqiang --- boards/nxp/imx8mm_evk/doc/index.rst | 4 ++-- boards/nxp/imx8mn_evk/doc/index.rst | 4 ++-- boards/nxp/imx8mp_evk/doc/index.rst | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/boards/nxp/imx8mm_evk/doc/index.rst b/boards/nxp/imx8mm_evk/doc/index.rst index 6483febdcba..9c29ba4cb67 100644 --- a/boards/nxp/imx8mm_evk/doc/index.rst +++ b/boards/nxp/imx8mm_evk/doc/index.rst @@ -112,13 +112,13 @@ Use U-Boot to load and kick zephyr.bin: .. code-block:: console - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 + fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 Or kick SMP zephyr.bin: .. code-block:: console - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 + fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 Use this configuration to run basic Zephyr applications and kernel tests, diff --git a/boards/nxp/imx8mn_evk/doc/index.rst b/boards/nxp/imx8mn_evk/doc/index.rst index 3e27bb233ba..923967133bf 100644 --- a/boards/nxp/imx8mn_evk/doc/index.rst +++ b/boards/nxp/imx8mn_evk/doc/index.rst @@ -82,13 +82,13 @@ Use U-Boot to load and kick zephyr.bin: .. code-block:: console - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 + fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 Or kick SMP zephyr.bin: .. code-block:: console - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 + fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 Use this configuration to run basic Zephyr applications and kernel tests, diff --git a/boards/nxp/imx8mp_evk/doc/index.rst b/boards/nxp/imx8mp_evk/doc/index.rst index 9952c7c90b5..6d6e1b7b556 100644 --- a/boards/nxp/imx8mp_evk/doc/index.rst +++ b/boards/nxp/imx8mp_evk/doc/index.rst @@ -102,13 +102,13 @@ Use U-Boot to load and kick non-smp zephyr.bin: .. code-block:: console - mw 303d0518 f 1; fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xc0000000 + fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xc0000000 Or kick SMP zephyr.bin: .. code-block:: console - mw 303d0518 f 1; fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0xc0000000 + fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0xc0000000 Use this configuration to run basic Zephyr applications and kernel tests, for example, with the :zephyr:code-sample:`synchronization` sample: From b0339136c1813f616e766ff04f88d08d7cabf418 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 26 Mar 2024 10:05:25 +0100 Subject: [PATCH 1625/2402] tests bsim: run_parallel: Print how long tests take To give an idea of which tests are taking too long either on CI or locally. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/run_parallel.sh | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/tests/bsim/run_parallel.sh b/tests/bsim/run_parallel.sh index cb9a3d4ed80..99416529034 100755 --- a/tests/bsim/run_parallel.sh +++ b/tests/bsim/run_parallel.sh @@ -77,9 +77,12 @@ echo -n "" > $tmp_res_file if [ `command -v parallel` ]; then parallel ' echo "" + start=$(date +%s%N) {} $@ &> {#}.log + dur=$(($(date +%s%N) - $start)) + dur_s=$(awk -vdur=$dur "BEGIN { printf(\"%0.3f\", dur/1000000000)}") if [ $? -ne 0 ]; then - (>&2 echo -e "\e[91m{} FAILED\e[39m") + (>&2 echo -e "\e[91m{} FAILED\e[39m ($dur_s s)") (>&2 cat {#}.log) echo "" cat {#}.log | eval $CLEAN_XML @@ -88,7 +91,7 @@ if [ `command -v parallel` ]; then echo "" exit 1 else - (>&2 echo -e "{} PASSED") + (>&2 echo -e "{} PASSED ($dur_s s)") rm {#}.log echo "" fi From c62dd778cd574ea74c5f280d76130266bd958b78 Mon Sep 17 00:00:00 2001 From: Seppo Takalo Date: Tue, 26 Mar 2024 14:15:22 +0200 Subject: [PATCH 1626/2402] net: lwm2m: Fix socket hints for block transfer Outgoing block-transfers now set the socket hint to ONGOING as long as the BLOCK1/BLOCK2 header has MORE flag set to true. This means as only the last packet in the block-transfer set the socket hint to LAST or ONE_RESPONSE. Signed-off-by: Seppo Takalo --- include/zephyr/net/coap.h | 9 +++++++++ subsys/net/lib/coap/coap.c | 16 ++++++++++++++++ subsys/net/lib/lwm2m/lwm2m_engine.c | 4 +++- tests/net/lib/lwm2m/lwm2m_engine/src/stubs.c | 1 + tests/net/lib/lwm2m/lwm2m_engine/src/stubs.h | 2 ++ 5 files changed, 31 insertions(+), 1 deletion(-) diff --git a/include/zephyr/net/coap.h b/include/zephyr/net/coap.h index 43073a5b20b..7f69cc4e9a7 100644 --- a/include/zephyr/net/coap.h +++ b/include/zephyr/net/coap.h @@ -757,6 +757,15 @@ bool coap_has_descriptive_block_option(struct coap_packet *cpkt); */ int coap_remove_descriptive_block_option(struct coap_packet *cpkt); +/** + * @brief Check if BLOCK1 or BLOCK2 option has more flag set + * + * @param cpkt Packet to be checked. + * @return true If more flag is set in BLOCK1 or BLOCK2 + * @return false If MORE flag is not set or BLOCK header not found. + */ +bool coap_block_has_more(struct coap_packet *cpkt); + /** * @brief Append BLOCK1 option to the packet. * diff --git a/subsys/net/lib/coap/coap.c b/subsys/net/lib/coap/coap.c index ac434680740..543e6c14704 100644 --- a/subsys/net/lib/coap/coap.c +++ b/subsys/net/lib/coap/coap.c @@ -1257,6 +1257,22 @@ int coap_remove_descriptive_block_option(struct coap_packet *cpkt) } } +bool coap_block_has_more(struct coap_packet *cpkt) +{ + bool more = false; + int opt; + + if (coap_packet_is_request(cpkt)) { + opt = coap_get_option_int(cpkt, COAP_OPTION_BLOCK1); + } else { + opt = coap_get_option_int(cpkt, COAP_OPTION_BLOCK2); + } + if (opt >= 0) { + more = GET_MORE(opt); + } + return more; +} + int coap_append_block1_option(struct coap_packet *cpkt, struct coap_block_context *ctx) { diff --git a/subsys/net/lib/lwm2m/lwm2m_engine.c b/subsys/net/lib/lwm2m/lwm2m_engine.c index df9689dc094..db7906da4cf 100644 --- a/subsys/net/lib/lwm2m/lwm2m_engine.c +++ b/subsys/net/lib/lwm2m/lwm2m_engine.c @@ -659,7 +659,9 @@ static void hint_socket_state(struct lwm2m_ctx *ctx, struct lwm2m_message *ongoi empty = false; } - if (!empty) { + bool ongoing_block_tx = coap_block_has_more(&ongoing_tx->cpkt); + + if (!empty || ongoing_block_tx) { ctx->set_socket_state(ctx->sock_fd, LWM2M_SOCKET_STATE_ONGOING); } else if (ongoing_tx->type == COAP_TYPE_CON) { ctx->set_socket_state(ctx->sock_fd, LWM2M_SOCKET_STATE_ONE_RESPONSE); diff --git a/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.c b/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.c index 55573eda168..13b0e38e8e6 100644 --- a/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.c +++ b/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.c @@ -43,6 +43,7 @@ DEFINE_FAKE_VOID_FUNC(lwm2m_clear_block_contexts); DEFINE_FAKE_VALUE_FUNC(int, lwm2m_security_mode, struct lwm2m_ctx *); DEFINE_FAKE_VALUE_FUNC(int, z_impl_zsock_setsockopt, int, int, int, const void *, socklen_t); DEFINE_FAKE_VOID_FUNC(engine_update_tx_time); +DEFINE_FAKE_VALUE_FUNC(bool, coap_block_has_more, struct coap_packet *); static sys_slist_t obs_obj_path_list = SYS_SLIST_STATIC_INIT(&obs_obj_path_list); sys_slist_t *lwm2m_obs_obj_path_list(void) diff --git a/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.h b/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.h index 67c4cde883d..74685bbcb31 100644 --- a/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.h +++ b/tests/net/lib/lwm2m/lwm2m_engine/src/stubs.h @@ -58,6 +58,7 @@ DECLARE_FAKE_VALUE_FUNC(int, z_impl_zsock_connect, int, const struct sockaddr *, DECLARE_FAKE_VALUE_FUNC(int, lwm2m_security_mode, struct lwm2m_ctx *); DECLARE_FAKE_VALUE_FUNC(int, z_impl_zsock_setsockopt, int, int, int, const void *, socklen_t); DECLARE_FAKE_VOID_FUNC(engine_update_tx_time); +DECLARE_FAKE_VALUE_FUNC(bool, coap_block_has_more, struct coap_packet *); #define DO_FOREACH_FAKE(FUNC) \ do { \ @@ -89,6 +90,7 @@ DECLARE_FAKE_VOID_FUNC(engine_update_tx_time); FUNC(lwm2m_security_mode) \ FUNC(z_impl_zsock_setsockopt) \ FUNC(engine_update_tx_time) \ + FUNC(coap_block_has_more) \ } while (0) #endif /* STUBS_H */ From eef91d40780f96b272fbe9842d62aa8e7e55def4 Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Mon, 25 Mar 2024 19:24:26 +0100 Subject: [PATCH 1627/2402] llext: rework LL_EXTENSION_SYMBOL to generate const structs The LL_EXTENSION_SYMBOL macro is used to export symbols defined in extensions to the base image. This patch reworks the macro to use `static const struct llext_const_symbol`, since: - the associated values are semantically not modifiable; - this exported symbol table is parsed by llext like section iterables, ignoring associated symbol information. This is mostly a cosmetic change because, unlike the base image, these symbols cannot be placed (and left) in ROM as they will most certainly require runtime relocation. However, it makes this macro more consistent with EXPORT_SYMBOL, which is the base image equivalent. Also clarify some comments in the same header file. Signed-off-by: Luca Burelli --- include/zephyr/llext/symbol.h | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/include/zephyr/llext/symbol.h b/include/zephyr/llext/symbol.h index 8691301ac09..e42dc37c9ef 100644 --- a/include/zephyr/llext/symbol.h +++ b/include/zephyr/llext/symbol.h @@ -67,21 +67,34 @@ struct llext_symtable { /** - * @brief Export a constant symbol to a table of symbols + * @brief Export a constant symbol to extensions * * Takes a symbol (function or object) by symbolic name and adds the name - * and address of the symbol to a table of symbols that may be used for linking. + * and address of the symbol to a table of symbols that may be referenced + * by extensions. * - * @param x Symbol to export + * @param x Symbol to export to extensions */ #define EXPORT_SYMBOL(x) \ static const STRUCT_SECTION_ITERABLE(llext_const_symbol, x ## _sym) = { \ .name = STRINGIFY(x), .addr = (const void *)&x, \ } +/** + * @brief Exports a symbol from an extension to the base image + * + * This macro can be used in extensions to add a symbol (function or object) + * to the extension's exported symbol table, so that it may be referenced by + * the base image. + * + * @param x Extension symbol to export to the base image + */ #define LL_EXTENSION_SYMBOL(x) \ - struct llext_symbol Z_GENERIC_SECTION(".exported_sym") __used \ - symbol_##x = {STRINGIFY(x), (void *)&x} + static const struct llext_const_symbol \ + Z_GENERIC_SECTION(".exported_sym") __used \ + x ## _sym = { \ + .name = STRINGIFY(x), .addr = (const void *)&x, \ + } /** * @} From 903bbefef3773328368d7a6c9d3837ec7e2a77f8 Mon Sep 17 00:00:00 2001 From: Vit Stanicek Date: Tue, 26 Mar 2024 11:14:21 +0100 Subject: [PATCH 1628/2402] drivers: dma_mcux_lpc: Fix omitted interrupt config Add the invocation of an interrupt config function (config->irq_config_func). Absence of this call results in the DMA driver not being able to service interrupts raised by the DMA peripheral. This case was observed on the i.MX RT685's HiFi 4 DSP domain, where DMA was not functional because of this. Signed-off-by: Vit Stanicek --- drivers/dma/dma_mcux_lpc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dma/dma_mcux_lpc.c b/drivers/dma/dma_mcux_lpc.c index 449ca0de97f..3ef75ac1176 100644 --- a/drivers/dma/dma_mcux_lpc.c +++ b/drivers/dma/dma_mcux_lpc.c @@ -849,6 +849,8 @@ static int dma_mcux_lpc_init(const struct device *dev) DMA_Init(DEV_BASE(dev)); INPUTMUX_Init(INPUTMUX); + config->irq_config_func(dev); + return 0; } From 379ac5e394a9fa92f38651f2718bd5b752c24d3b Mon Sep 17 00:00:00 2001 From: Dave Lacerte Date: Tue, 26 Mar 2024 14:49:19 -0400 Subject: [PATCH 1629/2402] modules: openthread: platform: radio: Time Sync OT Feature support Add missing otRadioIeInfo structure and add plaform time to transmit frame Signed-off-by: Dave Lacerte --- modules/openthread/Kconfig.features | 3 ++- modules/openthread/platform/radio.c | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/modules/openthread/Kconfig.features b/modules/openthread/Kconfig.features index cc29a53c650..7fd9ed50802 100644 --- a/modules/openthread/Kconfig.features +++ b/modules/openthread/Kconfig.features @@ -341,7 +341,8 @@ config OPENTHREAD_SRP_SERVER select OPENTHREAD_ECDSA config OPENTHREAD_TIME_SYNC - bool "The time synchronization service feature" + bool "The time synchronization service feature [EXPERIMENTAL]" + select EXPERIMENTAL config OPENTHREAD_TREL bool "TREL radio link for Thread over Infrastructure feature" diff --git a/modules/openthread/platform/radio.c b/modules/openthread/platform/radio.c index 64effaef337..b320d0f476b 100644 --- a/modules/openthread/platform/radio.c +++ b/modules/openthread/platform/radio.c @@ -85,6 +85,10 @@ static otRadioFrame sTransmitFrame; static otRadioFrame ack_frame; static uint8_t ack_psdu[ACK_PKT_LENGTH]; +#if defined(CONFIG_OPENTHREAD_TIME_SYNC) +static otRadioIeInfo tx_ie_info; +#endif + static struct net_pkt *tx_pkt; static struct net_buf *tx_payload; @@ -334,6 +338,10 @@ static void dataInit(void) for (size_t i = 0; i < CHANNEL_COUNT; i++) { max_tx_power_table[i] = OT_RADIO_POWER_INVALID; } + +#if defined(CONFIG_OPENTHREAD_TIME_SYNC) + sTransmitFrame.mInfo.mTxInfo.mIeInfo = &tx_ie_info; +#endif } void platformRadioInit(void) @@ -385,6 +393,18 @@ void transmit_message(struct k_work *tx_job) radio_api->set_channel(radio_dev, channel); radio_api->set_txpower(radio_dev, get_transmit_power_for_channel(channel)); +#if defined(CONFIG_OPENTHREAD_TIME_SYNC) + if (sTransmitFrame.mInfo.mTxInfo.mIeInfo->mTimeIeOffset != 0) { + uint8_t *time_ie = + sTransmitFrame.mPsdu + sTransmitFrame.mInfo.mTxInfo.mIeInfo->mTimeIeOffset; + uint64_t offset_plat_time = + otPlatTimeGet() + sTransmitFrame.mInfo.mTxInfo.mIeInfo->mNetworkTimeOffset; + + *(time_ie++) = sTransmitFrame.mInfo.mTxInfo.mIeInfo->mTimeSyncSeq; + sys_put_le64(offset_plat_time, time_ie); + } +#endif + net_pkt_set_ieee802154_frame_secured(tx_pkt, sTransmitFrame.mInfo.mTxInfo.mIsSecurityProcessed); net_pkt_set_ieee802154_mac_hdr_rdy(tx_pkt, sTransmitFrame.mInfo.mTxInfo.mIsHeaderUpdated); From 693ae8635a6478734673280e76d040904ea232c6 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 26 Mar 2024 14:59:21 +0100 Subject: [PATCH 1630/2402] tests bsim edtt: Kill stuck processes in the same way as other tests This test keeps its own partial way of running tests. Let's have it kill stuck processes in the same way as the rest (sending another kill 5 seconds after, and printing a message about what happened) Signed-off-by: Alberto Escolar Piedras --- .../bluetooth/ll/edtt/tests_scripts/_controller_tests_inner.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/bsim/bluetooth/ll/edtt/tests_scripts/_controller_tests_inner.sh b/tests/bsim/bluetooth/ll/edtt/tests_scripts/_controller_tests_inner.sh index 52f04e2e6e3..318dc6c66dd 100755 --- a/tests/bsim/bluetooth/ll/edtt/tests_scripts/_controller_tests_inner.sh +++ b/tests/bsim/bluetooth/ll/edtt/tests_scripts/_controller_tests_inner.sh @@ -58,7 +58,7 @@ function _Execute(){ rr="rr record -o ${out}" fi check_program_exists $1 - run_in_background timeout 300 ${rr} $@ + run_in_background timeout --kill-after=5 -v 800 ${rr} $@ } From 7d7188e792b2a81301ed1b55f975e3907e5a1300 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 26 Mar 2024 15:33:26 +0100 Subject: [PATCH 1631/2402] tests bsim: Increase runtime timeouts Let's increase the timeout for a few tests whose timeout is less than 3x a typical execution time in CI. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio.sh | 2 +- .../audio/test_scripts/bap_broadcast_audio_assistant.sh | 2 +- tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio.sh | 1 - .../audio/test_scripts/bap_unicast_audio_acl_disconnect.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/cap_broadcast.sh | 1 - .../bsim/bluetooth/audio/test_scripts/cap_capture_and_render.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/cap_unicast.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/cap_unicast_timeout.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/csip.sh | 2 +- tests/bsim/bluetooth/audio/test_scripts/csip_encrypted_sirk.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/csip_forced_release.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/csip_new_sirk.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/csip_no_lock.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/csip_no_rank.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/csip_no_size.sh | 2 +- tests/bsim/bluetooth/audio/test_scripts/has_offline.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/media_controller.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/pbp.sh | 2 +- tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh | 2 +- tests/bsim/bluetooth/host/misc/hfc/test_scripts/run.sh | 2 +- .../bluetooth/host/privacy/central/test_scripts/run_test.sh | 1 + .../bluetooth/host/privacy/peripheral/test_scripts/run_test.sh | 1 + .../privacy/peripheral/test_scripts/run_test_rpa_expired.sh | 1 + .../privacy/peripheral/test_scripts/run_test_rpa_sharing.sh | 1 + tests/bsim/bluetooth/ll/multiple_id/tests_scripts/multiple.sh | 2 +- tests/bsim/bluetooth/mesh/_mesh_test.sh | 2 +- 27 files changed, 13 insertions(+), 23 deletions(-) diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio.sh index 0a2be7c26d9..f2330a85dd1 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio.sh @@ -5,7 +5,7 @@ # SPDX-License-Identifier: Apache-2.0 VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=50 +EXECUTE_TIMEOUT=100 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_assistant.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_assistant.sh index 4c5bf1dc6f3..b1fe4f580fe 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_assistant.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_assistant.sh @@ -6,7 +6,7 @@ SIMULATION_ID="bap_broadcast_audio_assistant" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=50 +EXECUTE_TIMEOUT=100 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio.sh index 7430b835c23..edf19425e85 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio.sh @@ -6,7 +6,6 @@ SIMULATION_ID="unicast_audio" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh index 8976fe7330a..6a3f997179f 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh @@ -6,7 +6,6 @@ SIMULATION_ID="unicast_audio_acl_disconnect" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast.sh index 4eb4d4f5d04..7688058450e 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast.sh @@ -6,7 +6,6 @@ SIMULATION_ID="cap_broadcast" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_capture_and_render.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_capture_and_render.sh index a6c6445feef..b089c0ac63e 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_capture_and_render.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_capture_and_render.sh @@ -6,7 +6,6 @@ SIMULATION_ID="cap_capture_and_render" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast.sh index c65aa58ce5d..2f90027905b 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast.sh @@ -6,7 +6,6 @@ SIMULATION_ID="cap_unicast" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh index 4ed5224e52f..1facc09e6be 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh @@ -6,7 +6,6 @@ SIMULATION_ID="cap_unicast_inval" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_timeout.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_timeout.sh index aac22facc1b..223328fab7b 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_timeout.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_timeout.sh @@ -6,7 +6,6 @@ SIMULATION_ID="cap_unicast_timeout" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip.sh b/tests/bsim/bluetooth/audio/test_scripts/csip.sh index 5263c927a78..8d2c4380dc5 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip.sh @@ -10,7 +10,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=30 +EXECUTE_TIMEOUT=100 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_encrypted_sirk.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_encrypted_sirk.sh index 388551c5d0c..a33113e381a 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_encrypted_sirk.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_encrypted_sirk.sh @@ -9,7 +9,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_forced_release.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_forced_release.sh index 32c84dfbaea..380278f2bdd 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_forced_release.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_forced_release.sh @@ -9,7 +9,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_new_sirk.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_new_sirk.sh index debdca99b12..74d88e4848f 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_new_sirk.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_new_sirk.sh @@ -10,7 +10,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_no_lock.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_no_lock.sh index 8f8d72fed6f..4ee30c09010 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_no_lock.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_no_lock.sh @@ -9,7 +9,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_no_rank.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_no_rank.sh index ad73a00fcd1..8666d5fb5d4 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_no_rank.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_no_rank.sh @@ -9,7 +9,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_no_size.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_no_size.sh index f76d350b29d..a566cec1f21 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_no_size.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_no_size.sh @@ -9,7 +9,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=30 +EXECUTE_TIMEOUT=60 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/has_offline.sh b/tests/bsim/bluetooth/audio/test_scripts/has_offline.sh index c6844d4f1b3..b75a7ba7311 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/has_offline.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/has_offline.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source SIMULATION_ID="has_offline_behavior" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/media_controller.sh b/tests/bsim/bluetooth/audio/test_scripts/media_controller.sh index ca53b2b0be7..29c41801ae5 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/media_controller.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/media_controller.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source SIMULATION_ID="media_controller" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/pbp.sh b/tests/bsim/bluetooth/audio/test_scripts/pbp.sh index 416203c0f15..fb1ecbdd14b 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/pbp.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/pbp.sh @@ -5,7 +5,7 @@ # SPDX-License-Identifier: Apache-2.0 VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=50 +EXECUTE_TIMEOUT=100 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh b/tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh index b247a5be0be..c18d5e0a9a5 100755 --- a/tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh +++ b/tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh @@ -10,7 +10,7 @@ test_path=$(guess_test_long_name) dev_exe="bs_${BOARD_TS}_${test_path}_prj_conf" simulation_id="${test_path}" -EXECUTE_TIMEOUT=60 +EXECUTE_TIMEOUT=120 cd "${BSIM_OUT_PATH}/bin" diff --git a/tests/bsim/bluetooth/host/misc/hfc/test_scripts/run.sh b/tests/bsim/bluetooth/host/misc/hfc/test_scripts/run.sh index fd1a534e5dc..cc5eef568b2 100755 --- a/tests/bsim/bluetooth/host/misc/hfc/test_scripts/run.sh +++ b/tests/bsim/bluetooth/host/misc/hfc/test_scripts/run.sh @@ -6,7 +6,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="misc_hfc" verbosity_level=2 -EXECUTE_TIMEOUT=120 +EXECUTE_TIMEOUT=240 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh index 766df63d256..52a41097883 100755 --- a/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh @@ -5,6 +5,7 @@ set -eu source ${ZEPHYR_BASE}/tests/bsim/sh_common.source +EXECUTE_TIMEOUT=100 verbosity_level=2 simulation_id="$(guess_test_long_name)" diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh index 6564e615e0e..d63d3da3eb8 100755 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh @@ -7,6 +7,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id="host_privacy_peripheral" +EXECUTE_TIMEOUT=100 central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" peripheral_exe="${central_exe}" diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh index adbbf293250..0560dd562b1 100755 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh @@ -7,6 +7,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id="rpa_expired" +EXECUTE_TIMEOUT=100 central_exe_rpa_expired="\ ${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_rpa_expired_conf" diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh index 97389f1e129..2f08758dc34 100755 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh @@ -7,6 +7,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id="$(guess_test_long_name)_rpa_sharing" +EXECUTE_TIMEOUT=60 central_exe_rpa_sharing="\ ${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_rpa_sharing_conf" diff --git a/tests/bsim/bluetooth/ll/multiple_id/tests_scripts/multiple.sh b/tests/bsim/bluetooth/ll/multiple_id/tests_scripts/multiple.sh index 91b93f0c8d1..2d9eaece5ef 100755 --- a/tests/bsim/bluetooth/ll/multiple_id/tests_scripts/multiple.sh +++ b/tests/bsim/bluetooth/ll/multiple_id/tests_scripts/multiple.sh @@ -7,7 +7,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # Multiple connection between two devices with multiple peripheral identity simulation_id="multiple" verbosity_level=2 -EXECUTE_TIMEOUT=1800 +EXECUTE_TIMEOUT=2200 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/mesh/_mesh_test.sh b/tests/bsim/bluetooth/mesh/_mesh_test.sh index fac62d335be..308be41eb0b 100755 --- a/tests/bsim/bluetooth/mesh/_mesh_test.sh +++ b/tests/bsim/bluetooth/mesh/_mesh_test.sh @@ -3,7 +3,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -EXECUTE_TIMEOUT=600 +EXECUTE_TIMEOUT=800 function Skip(){ for i in "${SKIP[@]}" ; do From 082f2832718568604688fe845999e3ea41c458af Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 26 Mar 2024 15:38:19 +0100 Subject: [PATCH 1632/2402] tests/bsim: Remove too small timeouts Remove explicit timeouts which are either the same as the default one or smaller. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/bluetooth/audio/test_scripts/_csip_notify.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/has.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/ias.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/micp.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/tbs.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/tmap.sh | 1 - tests/bsim/bluetooth/audio/test_scripts/vcp.sh | 1 - .../hci_uart/tests_scripts/basic_conn_split_hci_uart.sh | 1 - .../hci_uart/tests_scripts/basic_conn_split_hci_uart_async.sh | 1 - tests/bsim/bluetooth/host/att/eatt/tests_scripts/lowres.sh | 1 - tests/bsim/bluetooth/host/gatt/notify/test_scripts/_run_test.sh | 1 - .../bluetooth/host/gatt/sc_indicate/test_scripts/sc_indicate.sh | 1 - tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh | 1 - .../ll/bis/tests_scripts/broadcast_iso_ticker_expire_info.sh | 1 - tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh | 1 - .../ll/conn/tests_scripts/basic_conn_encrypted_split.sh | 1 - .../ll/conn/tests_scripts/basic_conn_encrypted_split_privacy.sh | 1 - .../tests_scripts/basic_conn_encrypted_split_single_timer.sh | 1 - tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split.sh | 1 - .../bluetooth/ll/conn/tests_scripts/basic_conn_split_low_lat.sh | 1 - 21 files changed, 21 deletions(-) diff --git a/tests/bsim/bluetooth/audio/test_scripts/_csip_notify.sh b/tests/bsim/bluetooth/audio/test_scripts/_csip_notify.sh index 617a6b56766..a4f93794e60 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/_csip_notify.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/_csip_notify.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source SIMULATION_ID="csip_notify" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh index fb2f5d329cb..e7d4b9c3dff 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh @@ -6,7 +6,6 @@ SIMULATION_ID="bass_client_sync" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/audio/test_scripts/has.sh b/tests/bsim/bluetooth/audio/test_scripts/has.sh index 54fa56ae460..33dbabd51b6 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/has.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/has.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source SIMULATION_ID="has" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/ias.sh b/tests/bsim/bluetooth/audio/test_scripts/ias.sh index 6655f9f23f0..6728bdfb237 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/ias.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/ias.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source SIMULATION_ID="ias" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/micp.sh b/tests/bsim/bluetooth/audio/test_scripts/micp.sh index a943107ad7d..268e487c1eb 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/micp.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/micp.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source SIMULATION_ID="micp" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/tbs.sh b/tests/bsim/bluetooth/audio/test_scripts/tbs.sh index 02d044bf622..0a4282f89e2 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/tbs.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/tbs.sh @@ -9,7 +9,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source SIMULATION_ID="tbs_ccp" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/tmap.sh b/tests/bsim/bluetooth/audio/test_scripts/tmap.sh index 7bf4dc2ba7c..ec1a2fc5b29 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/tmap.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/tmap.sh @@ -6,7 +6,6 @@ SIMULATION_ID="tmap" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=30 source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/audio/test_scripts/vcp.sh b/tests/bsim/bluetooth/audio/test_scripts/vcp.sh index b90d0deba26..47dbba3e2b1 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/vcp.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/vcp.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source SIMULATION_ID="vcp" VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=20 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart.sh b/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart.sh index 7f5907763d6..d8152d80733 100755 --- a/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart.sh +++ b/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart.sh @@ -10,7 +10,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # connected over UART. The controller is the HCI UART sample. simulation_id="basic_conn_split_hci_uart" verbosity_level=2 -EXECUTE_TIMEOUT=20 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart_async.sh b/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart_async.sh index a1dc0e1a482..fef3e1c45ef 100755 --- a/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart_async.sh +++ b/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart_async.sh @@ -10,7 +10,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # connected over UART. The controller is the HCI UART async sample. simulation_id="basic_conn_split_hci_uart_async" verbosity_level=2 -EXECUTE_TIMEOUT=20 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/lowres.sh b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/lowres.sh index 92abc234ed1..36ff66d8ade 100755 --- a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/lowres.sh +++ b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/lowres.sh @@ -6,7 +6,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="lowres" verbosity_level=2 -EXECUTE_TIMEOUT=20 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/gatt/notify/test_scripts/_run_test.sh b/tests/bsim/bluetooth/host/gatt/notify/test_scripts/_run_test.sh index ae652cf94ac..0ed274c7b5d 100755 --- a/tests/bsim/bluetooth/host/gatt/notify/test_scripts/_run_test.sh +++ b/tests/bsim/bluetooth/host/gatt/notify/test_scripts/_run_test.sh @@ -6,7 +6,6 @@ set -eu source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/sc_indicate.sh b/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/sc_indicate.sh index 3018a5c8771..4bd2dabdc5a 100755 --- a/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/sc_indicate.sh +++ b/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/sc_indicate.sh @@ -8,7 +8,6 @@ test_name='sc_indicate' test_exe="bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_${test_name}_prj_conf" simulation_id="${test_name}" verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh index 762648523a7..b9177ed5817 100755 --- a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh +++ b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # to the BIS. simulation_id="broadcast_iso" verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_ticker_expire_info.sh b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_ticker_expire_info.sh index 463676cde89..8c9daf10bb9 100755 --- a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_ticker_expire_info.sh +++ b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_ticker_expire_info.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # to the BIS. simulation_id="broadcast_iso_ticker_expire_info" verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh index b575efeed6c..e0c4ab5e1b3 100755 --- a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh +++ b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # to the BIS, and recevied SDUs are emitted via vendor data path implementation. simulation_id="broadcast_iso_vs_dp" verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split.sh index 7d4e5946441..6dbc9795363 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # notification simulation_id="basic_conn_encr_split" verbosity_level=2 -EXECUTE_TIMEOUT=5 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_privacy.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_privacy.sh index f3a898e1739..a95021ca9df 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_privacy.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_privacy.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # notification simulation_id="basic_conn_encr_split_privacy" verbosity_level=2 -EXECUTE_TIMEOUT=5 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_single_timer.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_single_timer.sh index 683aad85b6d..5d61e45a20a 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_single_timer.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_single_timer.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # notification simulation_id="basic_conn_encr_split_single_timer" verbosity_level=2 -EXECUTE_TIMEOUT=5 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split.sh index 1946b388afb..e54f40e5542 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # notification, using the split controller (ULL LLL) simulation_id="basic_conn_split" verbosity_level=2 -EXECUTE_TIMEOUT=5 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split_low_lat.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split_low_lat.sh index 9c21fc4d922..c7a2f0aaaf2 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split_low_lat.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split_low_lat.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # notification, using the split controller (ULL LLL) in Low Latency Variant simulation_id="basic_conn_split_low_lat" verbosity_level=2 -EXECUTE_TIMEOUT=5 cd ${BSIM_OUT_PATH}/bin From ff13cb5adc0b4abeb3aeb8a94de59b509d4988a3 Mon Sep 17 00:00:00 2001 From: Thomas Stranger Date: Sun, 17 Mar 2024 09:51:04 +0100 Subject: [PATCH 1633/2402] boards: nxp: frdm_mcxn947: doc fixes - fix schematic link pointing to different board - fix link to the board_defconfig file - remove the "Debug Firmware" link that was not referenced anywhere - add a link to the board user manual - minor additions to the debug with J-Link section Signed-off-by: Thomas Stranger --- boards/nxp/frdm_mcxn947/doc/index.rst | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index a11686cd61d..58903baccb7 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -38,6 +38,7 @@ For more information about the MCX-N947 SoC and FRDM-MCXN947 board, see: - `MCX-N947 Reference Manual`_ - `FRDM-MCXN947 Website`_ - `FRDM-MCXN947 User Guide`_ +- `FRDM-MCXN947 Board User Manual`_ - `FRDM-MCXN947 Schematics`_ Supported Features @@ -135,11 +136,12 @@ Using J-Link There are two options. The onboard debug circuit can be updated with Segger J-Link firmware by following the instructions in :ref:`mcu-link-jlink-onboard-debug-probe`. -To put the board in ``DFU mode`` to program the firmware, short jumper J21. -The second option is to attach :ref:`jlink-external-debug-probe` to the -board. - -Use the ``-r jlink`` option with west to use the jlink runner. +To be able to program the firmware, you need to put the board in ``DFU mode`` +by shortening the jumper J21. +The second option is to attach a :ref:`jlink-external-debug-probe` to the +10-pin SWD connector (J23) of the board. Additionally, the jumper J19 must +be shortened. +For both options use the ``-r jlink`` option with west to use the jlink runner. .. code-block:: console @@ -207,8 +209,8 @@ should see the following message in the terminal: .. _FRDM-MCXN947 User Guide: https://www.nxp.com/document/guide/getting-started-with-frdm-mcxn947:GS-FRDM-MCXNXX -.. _FRDM-MCXN947 Debug Firmware: - https://www.nxp.com/docs/en/application-note/AN13206.pdf +.. _FRDM-MCXN947 Board User Manual: + https://www.nxp.com/webapp/Download?colCode=UM12018 .. _FRDM-MCXN947 Schematics: - https://www.nxp.com/webapp/Download?colCode=LPC55S69-SCH + https://www.nxp.com/webapp/Download?colCode=90818-MCXN947SH From 5f3d584a2f870e0616c9a3fb394e2b3caa1599e6 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Thu, 28 Mar 2024 11:02:26 -0500 Subject: [PATCH 1634/2402] boards: nxp: frdm_mcxn947: use core argument to target CPU0 In future versions of Linkserver, specifying the core argument within the device string will not be supported. Therefore, move the FRDM MCXN947 board to specify the core directly instead of using the device string. Signed-off-by: Daniel DeGrasse --- boards/nxp/frdm_mcxn947/board.cmake | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/boards/nxp/frdm_mcxn947/board.cmake b/boards/nxp/frdm_mcxn947/board.cmake index ed9c7e01ee3..86cdff853d9 100644 --- a/boards/nxp/frdm_mcxn947/board.cmake +++ b/boards/nxp/frdm_mcxn947/board.cmake @@ -6,7 +6,8 @@ if(CONFIG_SOC_MCXN947_CPU0) board_runner_args(jlink "--device=MCXN947_M33_0" "--reset-after-load") - board_runner_args(linkserver "--device=MCXN947:FRDM-MCXN947:cm33_core0") + board_runner_args(linkserver "--device=MCXN947:FRDM-MCXN947") + board_runner_args(linkserver "--core=cm33_core0") board_runner_args(linkserver "--override=/device/memory/1/flash-driver=MCXN9xx_S.cfx") board_runner_args(linkserver "--override=/device/memory/1/location=0x10000000") # Linkserver v1.4.85 and earlier do not include the secure regions in the From 370343a28f0f3a3977e8db9c80d9bde33b2fa1a6 Mon Sep 17 00:00:00 2001 From: Jakub Michalski Date: Fri, 19 Jan 2024 10:02:32 +0100 Subject: [PATCH 1635/2402] dts: bindings: update renesas rzt2m gpio bindings to handle interrupts Add irqs to rzt2m gpio bindings in order to add interrupt support to rzt2m gpio driver and adds common gpio node to store interrupt config (irqs are shared between ports) Signed-off-by: Jakub Michalski --- dts/bindings/gpio/renesas,rzt2m-gpio-common.yaml | 11 +++++++++++ dts/bindings/gpio/renesas,rzt2m-gpio.yaml | 4 ++++ 2 files changed, 15 insertions(+) create mode 100644 dts/bindings/gpio/renesas,rzt2m-gpio-common.yaml diff --git a/dts/bindings/gpio/renesas,rzt2m-gpio-common.yaml b/dts/bindings/gpio/renesas,rzt2m-gpio-common.yaml new file mode 100644 index 00000000000..18ec2ed9fbe --- /dev/null +++ b/dts/bindings/gpio/renesas,rzt2m-gpio-common.yaml @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 +description: Renesas RZT2M GPIO common + +compatible: "renesas,rzt2m-gpio-common" + +include: base.yaml + +properties: + interrupts: + required: true diff --git a/dts/bindings/gpio/renesas,rzt2m-gpio.yaml b/dts/bindings/gpio/renesas,rzt2m-gpio.yaml index e099c81753e..ea8c61ad8d2 100644 --- a/dts/bindings/gpio/renesas,rzt2m-gpio.yaml +++ b/dts/bindings/gpio/renesas,rzt2m-gpio.yaml @@ -13,6 +13,10 @@ properties: "#gpio-cells": const: 2 + irqs: + type: array + description: pin-irq pairs + gpio-cells: - pin - flags From 311aa332c86bd0787954ac57081c1888e2f4d894 Mon Sep 17 00:00:00 2001 From: Jakub Michalski Date: Fri, 19 Jan 2024 10:07:58 +0100 Subject: [PATCH 1636/2402] dts: arm: add nodes to support gpio interrupts in renesas rzt2m Add common gpio node to pinctrl node (interrupts are shared between ports) and syscon for interrupt edge detection register in order to support interrupts in rzt2m gpio Signed-off-by: Jakub Michalski --- dts/arm/renesas/rz/rzt2m.dtsi | 92 ++++++++++++++++++++++++++--------- 1 file changed, 69 insertions(+), 23 deletions(-) diff --git a/dts/arm/renesas/rz/rzt2m.dtsi b/dts/arm/renesas/rz/rzt2m.dtsi index d4138994372..c1a72f37563 100644 --- a/dts/arm/renesas/rz/rzt2m.dtsi +++ b/dts/arm/renesas/rz/rzt2m.dtsi @@ -103,6 +103,13 @@ reg-io-width = <4>; }; + ns_portnf_md: ns_portnf_md@8009000c { + /* Interrupt edge detection setting */ + compatible = "syscon"; + reg = <0x8009000c 0x4>; + reg-io-width = <4>; + }; + uart0: serial@80001000 { compatible = "renesas,rzt2m-uart"; reg = <0x80001000 0x1000>; @@ -131,31 +138,70 @@ compatible = "renesas,rzt2m-pinctrl"; reg = <0x800a0000 0x1000 0x81030c00 0x1000>; reg-names = "port_nsr", "ptadr"; - #address-cells = <1>; - #size-cells = <0>; - - gpio19: gpio@13 { - compatible = "renesas,rzt2m-gpio"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0x13>; - }; - gpio20: gpio@14 { - compatible = "renesas,rzt2m-gpio"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0x14>; - }; + gpio_common: gpio_common { + compatible = "renesas,rzt2m-gpio-common"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #address-cells = <1>; + #size-cells = <0>; + + gpio10: gpio@a { + compatible = "renesas,rzt2m-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0xa>; + irqs = <4 11>, <5 2>; + }; + + gpio16: gpio@10 { + compatible = "renesas,rzt2m-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x10>; + irqs = <3 7>, <6 8>; + }; + + gpio19: gpio@13 { + compatible = "renesas,rzt2m-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x13>; + irqs = <2 3>; + }; + + gpio20: gpio@14 { + compatible = "renesas,rzt2m-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x14>; + }; + + gpio23: gpio@17 { + compatible = "renesas,rzt2m-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + reg = <0x17>; + irqs = <0 5>, <2 8>; + }; - gpio23: gpio@17 { - compatible = "renesas,rzt2m-gpio"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - reg = <0x17>; }; }; }; From e92c04cbebf7d4af50016eb63f7bc02088590240 Mon Sep 17 00:00:00 2001 From: Jakub Michalski Date: Fri, 19 Jan 2024 10:18:36 +0100 Subject: [PATCH 1637/2402] drivers: gpio: add interrupt support to renesas rzt2m gpio Add interrupt support to renesas rzt2m gpio driver Signed-off-by: Jakub Michalski --- drivers/gpio/gpio_rzt2m.c | 240 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 232 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio_rzt2m.c b/drivers/gpio/gpio_rzt2m.c index c2bfd1a4acd..51aa2cfea03 100644 --- a/drivers/gpio/gpio_rzt2m.c +++ b/drivers/gpio/gpio_rzt2m.c @@ -9,15 +9,27 @@ #include #include #include +#include #include #include #include #include +#include +#include + +static const struct device *const ns_portnf_md_dev = DEVICE_DT_GET(DT_NODELABEL(ns_portnf_md)); #define PMm_OFFSET 0x200 +#define PMCm_OFFSET 0x400 +#define PFCm_OFFSET 0x600 #define PINm_OFFSET 0x800 #define DRCTLm_OFFSET 0xa00 +#define PMm_SIZE 0x2 +#define DRCTLm_SIZE 0x8 +#define PFCm_SIZE 0x4 + +/* config defines in include/zephyr/dt-bindings/gpio/renesas-rzt2m-gpio.h */ #define DRIVE_SHIFT 0 #define SCHMITT_TRIGGER_SHIFT 4 #define SLEW_RATE_SHIFT 5 @@ -27,8 +39,21 @@ #define PULL_UP (1 << PULL_SHIFT) #define PULL_DOWN (2 << PULL_SHIFT) +#define INT_INVERT 0 +#define INT_FALLING_EDGE 1 +#define INT_RISING_EDGE 2 +#define INT_BOTH_EDGE 3 + +#define IRQ_COUNT 16 +#define NS_IRQ_COUNT 14 + +#define MAX_PORT_SIZE 8 + +#define RZT2M_GPIO_VALUE_IDENTITY(i, _) i + struct rzt2m_gpio_config { struct gpio_driver_config common; + uint8_t pin_irqs[MAX_PORT_SIZE]; uint8_t *port_nsr; uint8_t *ptadr; uint8_t port; @@ -36,17 +61,29 @@ struct rzt2m_gpio_config { struct rzt2m_gpio_data { struct gpio_driver_data common; + sys_slist_t cb; +}; + +struct rzt2m_gpio_irq_slot { + const struct device *dev; + uint8_t pin; +}; + +struct rzt2m_gpio_common_data { + struct rzt2m_gpio_irq_slot irq_registered_ports[IRQ_COUNT]; }; +static struct rzt2m_gpio_common_data rzt2m_gpio_common_data_inst; + static void rzt2m_gpio_unlock(void) { - rzt2m_unlock_prcrn(PRCRN_PRC1); + rzt2m_unlock_prcrn(PRCRN_PRC1 | PRCRN_PRC2); rzt2m_unlock_prcrs(PRCRS_GPIO); } static void rzt2m_gpio_lock(void) { - rzt2m_lock_prcrn(PRCRN_PRC1); + rzt2m_lock_prcrn(PRCRN_PRC1 | PRCRN_PRC2); rzt2m_lock_prcrs(PRCRS_GPIO); } @@ -71,7 +108,7 @@ static volatile uint16_t *rzt2m_gpio_get_pm_reg(const struct device *dev) { const struct rzt2m_gpio_config *config = dev->config; - return (volatile uint16_t *)(config->port_nsr + PMm_OFFSET + 0x2 * config->port); + return (volatile uint16_t *)(config->port_nsr + PMm_OFFSET + PMm_SIZE * config->port); } /* IO Buffer m function switching register */ @@ -79,7 +116,7 @@ static volatile uint64_t *rzt2m_gpio_get_drctl_reg(const struct device *dev) { const struct rzt2m_gpio_config *config = dev->config; - return (volatile uint64_t *)(config->port_nsr + DRCTLm_OFFSET + 0x8 * config->port); + return (volatile uint64_t *)(config->port_nsr + DRCTLm_OFFSET + DRCTLm_SIZE * config->port); } /* Port m region select register */ @@ -90,6 +127,22 @@ static volatile uint8_t *rzt2m_gpio_get_rselp_reg(const struct device *dev) return (volatile uint8_t *)(config->ptadr + config->port); } +/* Port m mode control register */ +static volatile uint8_t *rzt2m_gpio_get_pmc_reg(const struct device *dev, uint8_t port) +{ + const struct rzt2m_gpio_config *config = dev->config; + + return (volatile uint8_t *)(config->port_nsr + PMCm_OFFSET + port); +} + +/* Port m function control register */ +static volatile uint32_t *rzt2m_gpio_get_pfc_reg(const struct device *dev, uint8_t port) +{ + const struct rzt2m_gpio_config *config = dev->config; + + return (volatile uint32_t *)(config->port_nsr + PFCm_OFFSET + PFCm_SIZE * port); +} + static int rzt2m_gpio_init(const struct device *dev) { rzt2m_gpio_unlock(); @@ -211,22 +264,193 @@ static int rzt2m_gpio_configure(const struct device *dev, gpio_pin_t pin, gpio_f return 0; } +static int rzt2m_gpio_get_pin_irq(const struct device *dev, gpio_pin_t pin) +{ + const struct rzt2m_gpio_config *config = dev->config; + + if (pin >= MAX_PORT_SIZE) { + return -1; + } + return config->pin_irqs[pin] - 1; +} + +static bool rzt2m_gpio_is_irq_used_by_other_pin(const struct device *dev, gpio_pin_t pin, + uint8_t irq) +{ + if (irq >= IRQ_COUNT) { + return false; + } + if (rzt2m_gpio_common_data_inst.irq_registered_ports[irq].dev == NULL) { + return false; + } + if (rzt2m_gpio_common_data_inst.irq_registered_ports[irq].dev != dev) { + return true; + } + return rzt2m_gpio_common_data_inst.irq_registered_ports[irq].pin != pin; +} + +static void rzt2m_gpio_isr(uint8_t *irq_n) +{ + const struct device *dev = rzt2m_gpio_common_data_inst.irq_registered_ports[*irq_n].dev; + + if (dev) { + struct rzt2m_gpio_data *data = dev->data; + int irq_pin = rzt2m_gpio_common_data_inst.irq_registered_ports[*irq_n].pin; + + if (irq_pin >= 0) { + gpio_fire_callbacks(&data->cb, dev, 1 << irq_pin); + } + } +} + +static int rzt2m_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, + enum gpio_int_mode mode, enum gpio_int_trig trig) +{ + const struct rzt2m_gpio_config *config = dev->config; + volatile uint8_t *pmc_reg = rzt2m_gpio_get_pmc_reg(dev, config->port); + volatile uint32_t *pfc_reg = rzt2m_gpio_get_pfc_reg(dev, config->port); + uint32_t ns_portnf_md_val = 0; + + syscon_read_reg(ns_portnf_md_dev, 0, &ns_portnf_md_val); + + /* level interrupts are not supported */ + if (mode == GPIO_INT_MODE_LEVEL) { + return -ENOTSUP; + } + + uint8_t irq = rzt2m_gpio_get_pin_irq(dev, pin); + bool irq_used_by_other = rzt2m_gpio_is_irq_used_by_other_pin(dev, pin, irq); + + if (irq < 0) { + return -ENOTSUP; + } + + /* secure range - currently not supported*/ + if (irq >= NS_IRQ_COUNT) { + return -ENOSYS; + } + + if (mode == GPIO_INT_MODE_DISABLED) { + rzt2m_gpio_unlock(); + WRITE_BIT(*pmc_reg, pin, 0); + + /* check if selected pin is using irq line to avoid unregistering other pin irq + * handler + */ + if (!irq_used_by_other) { + rzt2m_gpio_common_data_inst.irq_registered_ports[irq].dev = NULL; + } + rzt2m_gpio_lock(); + return 0; + } + + /* the irq line is used by another pin */ + if (irq_used_by_other) { + return -EBUSY; + } + + uint8_t md_mode = 0x0; + + switch (trig) { + case GPIO_INT_TRIG_LOW: + md_mode = INT_FALLING_EDGE; + break; + case GPIO_INT_TRIG_HIGH: + md_mode = INT_RISING_EDGE; + break; + case GPIO_INT_TRIG_BOTH: + md_mode = INT_BOTH_EDGE; + } + + rzt2m_gpio_unlock(); + + uint32_t mdx_mask = + ~((uint32_t)0b11 << irq); /* description of interrupt type has length of 2 bits */ + ns_portnf_md_val = (ns_portnf_md_val & mdx_mask) | (md_mode << irq); + syscon_write_reg(ns_portnf_md_dev, 0, ns_portnf_md_val); /* set interrupt type */ + + WRITE_BIT(*pmc_reg, pin, 1); /* enable special function on selected pin */ + + /* in case of every pin on every port irq function number is 0 */ + *pfc_reg &= ~((uint32_t)0b1111 << pin * 4); + + /* register handling interrupt in isr for selected port and pin */ + rzt2m_gpio_common_data_inst.irq_registered_ports[irq].dev = dev; + rzt2m_gpio_common_data_inst.irq_registered_ports[irq].pin = pin; + + rzt2m_gpio_lock(); + + return 0; +} + +static int rzt2m_gpio_manage_callback(const struct device *dev, struct gpio_callback *cb, bool set) +{ + struct rzt2m_gpio_data *data = dev->data; + + return gpio_manage_callback(&data->cb, cb, set); +} + static const struct gpio_driver_api rzt2m_gpio_driver_api = { .pin_configure = rzt2m_gpio_configure, .port_get_raw = rzt2m_gpio_get_raw, .port_set_masked_raw = rzt2m_port_set_masked_raw, .port_set_bits_raw = rzt2m_port_set_bits_raw, .port_clear_bits_raw = rzt2m_port_clear_bits_raw, - .port_toggle_bits = rzt2m_gpio_toggle}; + .port_toggle_bits = rzt2m_gpio_toggle, + .pin_interrupt_configure = rzt2m_gpio_pin_interrupt_configure, + .manage_callback = rzt2m_gpio_manage_callback}; + +#define RZT2M_INIT_IRQ(irq_n) \ + IRQ_CONNECT(DT_IRQ_BY_IDX(DT_INST(0, renesas_rzt2m_gpio_common), irq_n, irq), \ + DT_IRQ_BY_IDX(DT_INST(0, renesas_rzt2m_gpio_common), irq_n, priority), \ + rzt2m_gpio_isr, &n[irq_n], \ + DT_IRQ_BY_IDX(DT_INST(0, renesas_rzt2m_gpio_common), irq_n, flags)) \ + irq_enable(DT_IRQ_BY_IDX(DT_INST(0, renesas_rzt2m_gpio_common), irq_n, irq)); + +static int rzt2m_gpio_common_init(const struct device *dev) +{ + struct rzt2m_gpio_common_data *data = dev->data; + + static uint8_t n[IRQ_COUNT]; + + for (int i = 0; i < ARRAY_SIZE(n); i++) { + n[i] = i; + data->irq_registered_ports[i].dev = NULL; + } + + FOR_EACH(RZT2M_INIT_IRQ, (), LISTIFY(NS_IRQ_COUNT, RZT2M_GPIO_VALUE_IDENTITY, (,))) + + return 0; +} + +DEVICE_DT_DEFINE(DT_INST(0, renesas_rzt2m_gpio_common), + rzt2m_gpio_common_init, + NULL, + &rzt2m_gpio_common_data_inst, NULL, + PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, + NULL); + +#define VALUE_2X(i, _) UTIL_X2(i) + +#define PIN_IRQ_INITIALIZER(idx, inst) \ + COND_CODE_1(DT_INST_PROP_HAS_IDX(inst, irqs, idx), \ + ([DT_INST_PROP_BY_IDX(inst, irqs, idx)] = \ + DT_INST_PROP_BY_IDX(inst, irqs, UTIL_INC(idx)) + 1,), \ + ()) + +#define PORT_IRQS_INITIALIZER(inst) \ + FOR_EACH_FIXED_ARG(PIN_IRQ_INITIALIZER, (), inst, \ + LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,))) #define RZT2M_GPIO_DEFINE(inst) \ static struct rzt2m_gpio_data rzt2m_gpio_data##inst; \ static struct rzt2m_gpio_config rzt2m_gpio_config##inst = { \ - .port_nsr = (uint8_t *)DT_REG_ADDR_BY_NAME(DT_INST_PARENT(inst), port_nsr), \ - .ptadr = (uint8_t *)DT_REG_ADDR_BY_NAME(DT_INST_PARENT(inst), ptadr), \ + .port_nsr = (uint8_t *)DT_REG_ADDR_BY_NAME(DT_INST_GPARENT(inst), port_nsr), \ + .ptadr = (uint8_t *)DT_REG_ADDR_BY_NAME(DT_INST_GPARENT(inst), ptadr), \ .port = DT_INST_REG_ADDR(inst), \ + .pin_irqs = {PORT_IRQS_INITIALIZER(inst)}, \ .common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst)}}; \ - DEVICE_DT_INST_DEFINE(inst, rzt2m_gpio_init, NULL, &rzt2m_gpio_data##inst, \ + DEVICE_DT_INST_DEFINE(inst, rzt2m_gpio_init, NULL, &rzt2m_gpio_data##inst, \ &rzt2m_gpio_config##inst, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \ &rzt2m_gpio_driver_api); From fa314941a3f7e96ca26fe1e935e51dabc998a39e Mon Sep 17 00:00:00 2001 From: Jakub Michalski Date: Fri, 19 Jan 2024 10:20:06 +0100 Subject: [PATCH 1638/2402] boards: add switch nodes to rzt2m starter kit Add onboard switch nodes to rzt2m starter kit Signed-off-by: Jakub Michalski --- .../rzt2m_starter_kit_renesas_rzt2m.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts index 6b87455aafe..a34558ec014 100644 --- a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts +++ b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts @@ -20,6 +20,7 @@ aliases { led0 = &led0; + sw0 = &sw1; }; leds { @@ -41,6 +42,18 @@ label = "led3"; }; }; + + gpio_keys { + compatible = "gpio-keys"; + sw1: sw1 { + label = "sw1"; + gpios = <&gpio10 5 0>; + }; + sw2: sw2 { + label = "sw2"; + gpios = <&gpio16 3 0>; + }; + }; }; From d70e96ea96c9a5a7fe3081a263176522adfc50d5 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Wed, 27 Mar 2024 11:45:47 +0100 Subject: [PATCH 1639/2402] soc: st: stm32 mcus setting the lptim clock source Select the LPTIM clock source STM32_LPTIM_CLOCK to be LSE or LSI depending on the DTS clocks property of the stm32_lp_tick_source node. This will also affect the SYS_CLOCK_TICKS_PER_SEC depending on the lptim prescaler Signed-off-by: Francois Ramu --- soc/st/stm32/Kconfig.defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/soc/st/stm32/Kconfig.defconfig b/soc/st/stm32/Kconfig.defconfig index 9b06788796f..d90ce9b7da8 100644 --- a/soc/st/stm32/Kconfig.defconfig +++ b/soc/st/stm32/Kconfig.defconfig @@ -44,6 +44,11 @@ config SYS_CLOCK_TICKS_PER_SEC default 250 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128 depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSI +choice STM32_LPTIM_CLOCK + default STM32_LPTIM_CLOCK_LSE if "$(dt_node_ph_array_prop_int,$(DT_STM32_LPTIM_PATH),clocks,1,bus)" = 2 + default STM32_LPTIM_CLOCK_LSI if "$(dt_node_ph_array_prop_int,$(DT_STM32_LPTIM_PATH),clocks,1,bus)" = 3 +endchoice + config CLOCK_CONTROL_STM32_CUBE default y depends on CLOCK_CONTROL From fe5313fa6197fdd1822da890e95a65a5d81adae1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 28 Mar 2024 12:44:01 +0100 Subject: [PATCH 1640/2402] doc: releases: release-notes: 3.7: add informations on dhcpv4 options MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add documentation for new use of dhcpv4 options. Signed-off-by: Fin Maaß --- doc/releases/release-notes-3.7.rst | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index 2deafcffded..a0e21d27f63 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -178,6 +178,20 @@ Drivers and Sensors Networking ********** +* DHCPv4: + + * Added support for encapsulated vendor specific options. By enabling + :kconfig:option:`CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC` callbacks can be + registered with :c:func:`net_dhcpv4_add_option_vendor_callback` to handle these options after + being initialised with :c:func:`net_dhcpv4_init_option_vendor_callback`. + + * Added support for the "Vendor class identifier" option. Use the + :kconfig:option:`CONFIG_NET_DHCPV4_VENDOR_CLASS_IDENTIFIER` to enable it and + :kconfig:option:`CONFIG_NET_DHCPV4_VENDOR_CLASS_IDENTIFIER_STRING` to set it. + + * The NTP server from the DHCPv4 option can now be used to set the system time. This is done by + default, if :kconfig:option:`CONFIG_NET_CONFIG_CLOCK_SNTP_INIT` is enabled. + * LwM2M: * Added new API function: @@ -197,6 +211,9 @@ Libraries / Subsystems * Logging + * By enabling :kconfig:option:`CONFIG_LOG_BACKEND_NET_USE_DHCPV4_OPTION`, the IP address of the + syslog server for the networking backend is set by the DHCPv4 Log Server Option (7). + * Modem modules * Picolibc From dbfc1aaec697b78573c18d83fd40ba66ff63c0b3 Mon Sep 17 00:00:00 2001 From: Javan lacerda Date: Wed, 27 Mar 2024 14:01:44 +0000 Subject: [PATCH 1641/2402] scripts: dts: update pyyaml version The currently used PyYaml version has some vulnerabilies as described on the pull request description. It updates to version 6.0, removing these supply chain vulnerabily. The OSSF Scorecard was the tool used for discovering these vulnerabilties. Signed-off-by: Javan lacerda --- doc/requirements.txt | 2 +- scripts/dts/python-devicetree/setup.py | 2 +- scripts/requirements-base.txt | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/requirements.txt b/doc/requirements.txt index a1055014861..9655cc6b43a 100644 --- a/doc/requirements.txt +++ b/doc/requirements.txt @@ -11,7 +11,7 @@ sphinx-copybutton sphinx-togglebutton # YAML validation. Used by zephyr_module. -PyYAML>=5.1 +PyYAML>=6.0 pykwalify # Used by pytest-twister-harness plugin diff --git a/scripts/dts/python-devicetree/setup.py b/scripts/dts/python-devicetree/setup.py index 21315ed2b0e..acafb4ad91a 100644 --- a/scripts/dts/python-devicetree/setup.py +++ b/scripts/dts/python-devicetree/setup.py @@ -36,7 +36,7 @@ 'Operating System :: Microsoft :: Windows', ], install_requires=[ - 'PyYAML>=5.1', + 'PyYAML>=6.0', ], python_requires='>=3.6', ) diff --git a/scripts/requirements-base.txt b/scripts/requirements-base.txt index 929a4de67d4..813aabf312d 100644 --- a/scripts/requirements-base.txt +++ b/scripts/requirements-base.txt @@ -8,7 +8,7 @@ pyelftools>=0.27 # used by dts generation to parse binding YAMLs, also used by # twister to parse YAMLs, by west, zephyr_module,... -PyYAML>=5.1 +PyYAML>=6.0 # YAML validation. Used by zephyr_module. pykwalify From b49116c7eb4484d1e864cebd20c976b6ec946f49 Mon Sep 17 00:00:00 2001 From: Armin Brauns Date: Mon, 11 Mar 2024 09:21:23 +0000 Subject: [PATCH 1642/2402] drivers: iis2dlpc: fix typo in log message Probably copy-pasted from another line. Signed-off-by: Armin Brauns --- drivers/sensor/iis2dlpc/iis2dlpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/sensor/iis2dlpc/iis2dlpc.c b/drivers/sensor/iis2dlpc/iis2dlpc.c index 8cdca66f3bc..3d9dc5775a4 100644 --- a/drivers/sensor/iis2dlpc/iis2dlpc.c +++ b/drivers/sensor/iis2dlpc/iis2dlpc.c @@ -148,7 +148,7 @@ static int ii2sdlpc_set_slope_th(const struct device *dev, uint16_t th) err = iis2dlpc_wkup_threshold_set(ctx, th & 0x3F); if (err) { LOG_ERR("Could not set WK_THS to 0x%02X, error %d", - th & 0x03, err); + th & 0x3F, err); return err; } return 0; From 808d897ca867fb00d292c6287c25f0bf74f8f16a Mon Sep 17 00:00:00 2001 From: Armin Brauns Date: Tue, 12 Mar 2024 14:35:39 +0000 Subject: [PATCH 1643/2402] drivers: iis2dlpc: fix typo in function name iis2dlpc, not ii2sdlpc. Signed-off-by: Armin Brauns --- drivers/sensor/iis2dlpc/iis2dlpc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/sensor/iis2dlpc/iis2dlpc.c b/drivers/sensor/iis2dlpc/iis2dlpc.c index 3d9dc5775a4..4d266b9577d 100644 --- a/drivers/sensor/iis2dlpc/iis2dlpc.c +++ b/drivers/sensor/iis2dlpc/iis2dlpc.c @@ -139,7 +139,7 @@ static int iis2dlpc_channel_get(const struct device *dev, } #ifdef CONFIG_IIS2DLPC_ACTIVITY -static int ii2sdlpc_set_slope_th(const struct device *dev, uint16_t th) +static int iis2dlpc_set_slope_th(const struct device *dev, uint16_t th) { int err; const struct iis2dlpc_config *cfg = dev->config; @@ -153,7 +153,7 @@ static int ii2sdlpc_set_slope_th(const struct device *dev, uint16_t th) } return 0; } -static int ii2sdlpc_set_slope_dur(const struct device *dev, uint16_t dur) +static int iis2dlpc_set_slope_dur(const struct device *dev, uint16_t dur) { int err; const struct iis2dlpc_config *cfg = dev->config; @@ -191,9 +191,9 @@ static int iis2dlpc_dev_config(const struct device *dev, return iis2dlpc_set_odr(dev, val->val1); #ifdef CONFIG_IIS2DLPC_ACTIVITY case SENSOR_ATTR_SLOPE_TH: - return ii2sdlpc_set_slope_th(dev, val->val1); + return iis2dlpc_set_slope_th(dev, val->val1); case SENSOR_ATTR_SLOPE_DUR: - return ii2sdlpc_set_slope_dur(dev, val->val1); + return iis2dlpc_set_slope_dur(dev, val->val1); #endif /* CONFIG_IIS2DLPC_ACTIVITY */ default: LOG_DBG("Acc attribute not supported"); From f4c596ae28a16328b6dd55cd16206ab07ef5cf26 Mon Sep 17 00:00:00 2001 From: Armin Brauns Date: Thu, 7 Mar 2024 15:50:06 +0000 Subject: [PATCH 1644/2402] drivers: add iis328dq stmemsc driver Based on the iis2dlpc driver, with some significant differences in interrupt handling. Signed-off-by: Armin Brauns --- drivers/sensor/CMakeLists.txt | 1 + drivers/sensor/Kconfig | 1 + drivers/sensor/iis328dq/CMakeLists.txt | 13 + drivers/sensor/iis328dq/Kconfig | 35 ++ drivers/sensor/iis328dq/iis328dq.c | 460 ++++++++++++++++++++ drivers/sensor/iis328dq/iis328dq.h | 93 ++++ drivers/sensor/iis328dq/iis328dq_trigger.c | 332 ++++++++++++++ dts/bindings/sensor/st,iis328dq-common.yaml | 61 +++ dts/bindings/sensor/st,iis328dq-i2c.yaml | 10 + dts/bindings/sensor/st,iis328dq-spi.yaml | 10 + tests/drivers/build_all/sensor/app.overlay | 15 +- tests/drivers/build_all/sensor/i2c.dtsi | 8 + tests/drivers/build_all/sensor/spi.dtsi | 9 + 13 files changed, 1041 insertions(+), 7 deletions(-) create mode 100644 drivers/sensor/iis328dq/CMakeLists.txt create mode 100644 drivers/sensor/iis328dq/Kconfig create mode 100644 drivers/sensor/iis328dq/iis328dq.c create mode 100644 drivers/sensor/iis328dq/iis328dq.h create mode 100644 drivers/sensor/iis328dq/iis328dq_trigger.c create mode 100644 dts/bindings/sensor/st,iis328dq-common.yaml create mode 100644 dts/bindings/sensor/st,iis328dq-i2c.yaml create mode 100644 dts/bindings/sensor/st,iis328dq-spi.yaml diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 52962a0b2fd..21da3166be6 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -66,6 +66,7 @@ add_subdirectory_ifdef(CONFIG_IIS2DLPC iis2dlpc) add_subdirectory_ifdef(CONFIG_IIS2ICLX iis2iclx) add_subdirectory_ifdef(CONFIG_IIS2MDC iis2mdc) add_subdirectory_ifdef(CONFIG_IIS3DHHC iis3dhhc) +add_subdirectory_ifdef(CONFIG_IIS328DQ iis328dq) add_subdirectory_ifdef(CONFIG_INA219 ina219) add_subdirectory_ifdef(CONFIG_INA23X ina23x) add_subdirectory_ifdef(CONFIG_INA3221 ina3221) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 27d6c165197..64ce47dbe32 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -145,6 +145,7 @@ source "drivers/sensor/iis2dlpc/Kconfig" source "drivers/sensor/iis2iclx/Kconfig" source "drivers/sensor/iis2mdc/Kconfig" source "drivers/sensor/iis3dhhc/Kconfig" +source "drivers/sensor/iis328dq/Kconfig" source "drivers/sensor/ina219/Kconfig" source "drivers/sensor/ina23x/Kconfig" source "drivers/sensor/ina3221/Kconfig" diff --git a/drivers/sensor/iis328dq/CMakeLists.txt b/drivers/sensor/iis328dq/CMakeLists.txt new file mode 100644 index 00000000000..e7611971ab3 --- /dev/null +++ b/drivers/sensor/iis328dq/CMakeLists.txt @@ -0,0 +1,13 @@ +# ST Microelectronics IIS328DQ 3-axis accelerometer driver +# +# Copyright (c) 2020 STMicroelectronics +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# +zephyr_library() + +zephyr_library_sources(iis328dq.c) +zephyr_library_sources_ifdef(CONFIG_IIS328DQ_TRIGGER iis328dq_trigger.c) + +zephyr_library_include_directories(../stmemsc) diff --git a/drivers/sensor/iis328dq/Kconfig b/drivers/sensor/iis328dq/Kconfig new file mode 100644 index 00000000000..670e7101910 --- /dev/null +++ b/drivers/sensor/iis328dq/Kconfig @@ -0,0 +1,35 @@ +# ST Microelectronics IIS328DQ 3-axis accelerometer driver + +# Copyright (c) 2020 STMicroelectronics +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +menuconfig IIS328DQ + bool "IIS328DQ I2C/SPI accelerometer sensor driver" + default y + depends on DT_HAS_ST_IIS328DQ_ENABLED + depends on ZEPHYR_HAL_ST_MODULE + select I2C if $(dt_compat_on_bus,$(DT_COMPAT_ST_IIS328DQ),i2c) + select SPI if $(dt_compat_on_bus,$(DT_COMPAT_ST_IIS328DQ),spi) + select HAS_STMEMSC + select USE_STDC_IIS328DQ + help + Enable driver for IIS328DQ accelerometer sensor driver + +if IIS328DQ + +module = IIS328DQ +thread_priority = 10 +thread_stack_size = 1024 +source "drivers/sensor/Kconfig.trigger_template" + +if IIS328DQ_TRIGGER + +config IIS328DQ_THRESHOLD + bool "Threshold detection" + help + Enable threshold interrupts + +endif # IIS328DQ_TRIGGER + +endif # IIS328DQ diff --git a/drivers/sensor/iis328dq/iis328dq.c b/drivers/sensor/iis328dq/iis328dq.c new file mode 100644 index 00000000000..99140e072f3 --- /dev/null +++ b/drivers/sensor/iis328dq/iis328dq.c @@ -0,0 +1,460 @@ +/* ST Microelectronics IIS328DQ 3-axis accelerometer driver + * + * Copyright (c) 2020 STMicroelectronics + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + * + * Datasheet: + * https://www.st.com/resource/en/datasheet/iis328dq.pdf + */ + +#define DT_DRV_COMPAT st_iis328dq + +#include +#include +#include +#include +#include +#include + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#include +#elif DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#include +#endif + +#include "iis328dq.h" + +LOG_MODULE_REGISTER(IIS328DQ, CONFIG_SENSOR_LOG_LEVEL); + +/** + * iis328dq_set_odr - set new Full Scale (in ±g) + */ +static int iis328dq_set_range(const struct device *dev, uint8_t fs) +{ + int err; + struct iis328dq_data *iis328dq = dev->data; + const struct iis328dq_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + iis328dq_fs_t fs_reg; + uint8_t gain; + + if (fs <= 2) { + fs_reg = IIS328DQ_2g; + gain = 1; + } else if (fs <= 4) { + fs_reg = IIS328DQ_4g; + gain = 2; + } else if (fs <= 8) { + fs_reg = IIS328DQ_8g; + gain = 4; + } else { + LOG_ERR("FS too high"); + return -ENOTSUP; + } + err = iis328dq_full_scale_set(ctx, fs_reg); + + if (!err) { + iis328dq->gain = gain; + } + + return err; +} + +/** + * iis328dq_set_odr - set new Output Data Rate/sampling frequency (in Hz) + */ +static int iis328dq_set_odr(const struct device *dev, uint16_t odr) +{ + const struct iis328dq_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + + iis328dq_dr_t odr_reg; + + if (odr == 0U) { + odr_reg = IIS328DQ_ODR_OFF; + } else if (odr <= 1) { + odr_reg = IIS328DQ_ODR_1Hz; + } else if (odr <= 2) { + /* not sure what "5Hz2" is about, datasheet says PM=0b100 is 2Hz + * https://github.com/STMicroelectronics/STMems_Standard_C_drivers/issues/162 + */ + odr_reg = IIS328DQ_ODR_5Hz2; + } else if (odr <= 5) { + odr_reg = IIS328DQ_ODR_5Hz; + } else if (odr <= 10) { + odr_reg = IIS328DQ_ODR_10Hz; + } else if (odr <= 50) { + odr_reg = IIS328DQ_ODR_50Hz; + } else if (odr <= 100) { + odr_reg = IIS328DQ_ODR_100Hz; + } else if (odr <= 400) { + odr_reg = IIS328DQ_ODR_400Hz; + } else if (odr <= 1000) { + odr_reg = IIS328DQ_ODR_1kHz; + } else { + LOG_ERR("ODR too high"); + return -ENOTSUP; + } + + if (iis328dq_data_rate_set(ctx, odr_reg) != 0) { + LOG_ERR("Failed to set ODR"); + return -EIO; + } + + return 0; +} + +static inline void iis328dq_convert(struct sensor_value *val, int raw_val, uint8_t gain) +{ + int64_t dval; + + /* Gain is in mg/LSB */ + /* Convert to μm/s^2 */ + dval = ((int64_t)raw_val * gain * SENSOR_G) / 1000LL; + val->val1 = dval / 1000000LL; + val->val2 = dval % 1000000LL; +} + +static inline void iis328dq_channel_get_acc(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + int i; + uint8_t ofs_start, ofs_stop; + struct iis328dq_data *iis328dq = dev->data; + struct sensor_value *pval = val; + + switch (chan) { + case SENSOR_CHAN_ACCEL_X: + ofs_start = ofs_stop = 0U; + break; + case SENSOR_CHAN_ACCEL_Y: + ofs_start = ofs_stop = 1U; + break; + case SENSOR_CHAN_ACCEL_Z: + ofs_start = ofs_stop = 2U; + break; + default: + ofs_start = 0U; + ofs_stop = 2U; + break; + } + + for (i = ofs_start; i <= ofs_stop; i++) { + iis328dq_convert(pval++, iis328dq->acc[i], iis328dq->gain); + } +} + +static int iis328dq_channel_get(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + switch (chan) { + case SENSOR_CHAN_ACCEL_X: + case SENSOR_CHAN_ACCEL_Y: + case SENSOR_CHAN_ACCEL_Z: + case SENSOR_CHAN_ACCEL_XYZ: + iis328dq_channel_get_acc(dev, chan, val); + return 0; + default: + LOG_DBG("Channel not supported"); + break; + } + + return -ENOTSUP; +} + +#ifdef CONFIG_IIS328DQ_THRESHOLD +static int iis328dq_set_threshold(const struct device *dev, bool is_lower, + const struct sensor_value *val) +{ + int err; + const struct iis328dq_config *cfg = dev->config; + struct iis328dq_data *iis328dq = dev->data; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + + if (val->val1 < 0 || val->val2 < 0) { + /* thresholds are absolute */ + return -EINVAL; + } + int64_t micro_ms2 = (val->val1 * INT64_C(1000000)) + val->val2; + /* factor guessed from similar-looking LIS2DH12 datasheet */ + uint8_t mg_per_digit = iis328dq->gain * 16; + + int16_t val_raw = (micro_ms2 * 1000LL) / SENSOR_G / mg_per_digit; + + if (is_lower) { + /* internal INT1 handles lower threshold */ + err = iis328dq_int1_treshold_set(ctx, val_raw); + if (err) { + LOG_ERR("Could not set INT1_THS to 0x%02X, error %d", val_raw, err); + return err; + } + } else { + /* internal INT2 handles lower threshold */ + err = iis328dq_int2_treshold_set(ctx, val_raw); + if (err) { + LOG_ERR("Could not set INT2_THS to 0x%02X, error %d", val_raw, err); + return err; + } + } + return 0; +} + +static int iis328dq_set_duration(const struct device *dev, uint16_t dur) +{ + int err; + const struct iis328dq_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + + if (dur > 0x7F) { + LOG_WRN("Duration value %u too large", dur); + return -EINVAL; + } + + err = iis328dq_int1_dur_set(ctx, dur); + if (err) { + LOG_ERR("Could not set INT1_DUR to 0x%02X, error %d", dur, err); + return err; + } + err = iis328dq_int2_dur_set(ctx, dur); + if (err) { + LOG_ERR("Could not set INT2_DUR to 0x%02X, error %d", dur, err); + return err; + } + return 0; +} +#endif /* CONFIG_IIS328DQ_THRESHOLD */ +#define IIS328DQ_ATTR_DURATION SENSOR_ATTR_PRIV_START + +static int iis328dq_dev_config(const struct device *dev, enum sensor_channel chan, + enum sensor_attribute attr, const struct sensor_value *val) +{ + switch (attr) { + case SENSOR_ATTR_FULL_SCALE: + return iis328dq_set_range(dev, sensor_ms2_to_g(val)); + case SENSOR_ATTR_SAMPLING_FREQUENCY: + return iis328dq_set_odr(dev, val->val1); +#ifdef CONFIG_IIS328DQ_THRESHOLD + case SENSOR_ATTR_LOWER_THRESH: + case SENSOR_ATTR_UPPER_THRESH: + if (chan != SENSOR_CHAN_ACCEL_XYZ) { + LOG_ERR("Threshold cannot be set per-channel"); + return -ENOTSUP; + } + return iis328dq_set_threshold(dev, attr == SENSOR_ATTR_LOWER_THRESH, val); + case IIS328DQ_ATTR_DURATION: + if (chan != SENSOR_CHAN_ACCEL_XYZ) { + LOG_ERR("Duration cannot be set per-channel"); + return -ENOTSUP; + } + return iis328dq_set_duration(dev, val->val1); +#endif /* CONFIG_IIS328DQ_THRESHOLD */ + default: + LOG_DBG("Acc attribute not supported"); + break; + } + + return -ENOTSUP; +} + +static int iis328dq_attr_set(const struct device *dev, enum sensor_channel chan, + enum sensor_attribute attr, const struct sensor_value *val) +{ + switch (chan) { + case SENSOR_CHAN_ACCEL_X: + case SENSOR_CHAN_ACCEL_Y: + case SENSOR_CHAN_ACCEL_Z: + case SENSOR_CHAN_ACCEL_XYZ: + case SENSOR_CHAN_ALL: + return iis328dq_dev_config(dev, chan, attr, val); + default: + LOG_DBG("Attr not supported on %d channel", chan); + break; + } + + return -ENOTSUP; +} + +static int iis328dq_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + struct iis328dq_data *iis328dq = dev->data; + const struct iis328dq_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + int16_t buf[3]; + + /* fetch raw data sample */ + if (iis328dq_acceleration_raw_get(ctx, buf) < 0) { + LOG_DBG("Failed to fetch raw data sample"); + return -EIO; + } + + iis328dq->acc[0] = buf[0] >> 4; + iis328dq->acc[1] = buf[1] >> 4; + iis328dq->acc[2] = buf[2] >> 4; + + return 0; +} + +static const struct sensor_driver_api iis328dq_driver_api = { + .attr_set = iis328dq_attr_set, +#if CONFIG_IIS328DQ_TRIGGER + .trigger_set = iis328dq_trigger_set, +#endif /* CONFIG_IIS328DQ_TRIGGER */ + .sample_fetch = iis328dq_sample_fetch, + .channel_get = iis328dq_channel_get, +}; + +static int iis328dq_init(const struct device *dev) +{ + struct iis328dq_data *iis328dq = dev->data; + const struct iis328dq_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + uint8_t reg_value; + + iis328dq->dev = dev; + + /* check chip ID */ + if (iis328dq_device_id_get(ctx, ®_value) < 0) { + return -EIO; + } + + if (reg_value != IIS328DQ_ID) { + LOG_ERR("Invalid chip ID"); + return -EINVAL; + } + + /* reset device */ + if (iis328dq_boot_set(ctx, PROPERTY_ENABLE) < 0) { + return -EIO; + } + + k_sleep(K_MSEC(100)); + + if (iis328dq_boot_get(ctx, ®_value) < 0) { + return -EIO; + } + if (reg_value != PROPERTY_DISABLE) { + LOG_ERR("BOOT did not deassert"); + return -EIO; + } + + if (iis328dq_block_data_update_set(ctx, PROPERTY_ENABLE) < 0) { + return -EIO; + } + + /* set default odr to 12.5Hz acc */ + if (iis328dq_set_odr(dev, 12) < 0) { + LOG_ERR("odr init error (12.5 Hz)"); + return -EIO; + } + + if (iis328dq_set_range(dev, cfg->range) < 0) { + LOG_ERR("range init error %d", cfg->range); + return -EIO; + } + +#ifdef CONFIG_IIS328DQ_TRIGGER + if (iis328dq_init_interrupt(dev) < 0) { + LOG_ERR("Failed to initialize interrupts"); + return -EIO; + } +#endif /* CONFIG_IIS328DQ_TRIGGER */ + + return 0; +} + +/* + * Device creation macro, shared by IIS328DQ_DEFINE_SPI() and + * IIS328DQ_DEFINE_I2C(). + */ + +#define IIS328DQ_DEVICE_INIT(inst) \ + SENSOR_DEVICE_DT_INST_DEFINE(inst, iis328dq_init, NULL, &iis328dq_data_##inst, \ + &iis328dq_config_##inst, POST_KERNEL, \ + CONFIG_SENSOR_INIT_PRIORITY, &iis328dq_driver_api); + +#ifdef CONFIG_IIS328DQ_TRIGGER +#ifdef CONFIG_IIS328DQ_THRESHOLD +#define IIS328DQ_CFG_IRQ_THRESHOLD(inst) \ + .threshold_pad = DT_INST_PROP_OR(inst, threshold_int_pad, -1), +#else +#define IIS328DQ_CFG_IRQ_THRESHOLD(inst) +#endif /* CONFIG_IIS328DQ_THRESHOLD */ + +#define IIS328DQ_CFG_IRQ(inst) \ + .gpio_int1 = GPIO_DT_SPEC_INST_GET_OR(inst, int1_gpios, {0}), \ + .gpio_int2 = GPIO_DT_SPEC_INST_GET_OR(inst, int2_gpios, {0}), \ + .drdy_pad = DT_INST_PROP_OR(inst, drdy_int_pad, -1), IIS328DQ_CFG_IRQ_THRESHOLD(inst) +#else +#define IIS328DQ_CFG_IRQ(inst) +#endif /* CONFIG_IIS328DQ_TRIGGER */ + +#define IIS328DQ_CONFIG_COMMON(inst) \ + .range = DT_INST_PROP(inst, range), \ + IF_ENABLED(UTIL_OR(DT_INST_NODE_HAS_PROP(inst, int1_gpios), \ + DT_INST_NODE_HAS_PROP(inst, int2_gpios)), \ + (IIS328DQ_CFG_IRQ(inst))) + +/* + * Instantiation macros used when a device is on a SPI bus. + */ + +#define IIS328DQ_SPI_OPERATION \ + (SPI_WORD_SET(8) | SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA) + +#define IIS328DQ_CONFIG_SPI(inst) \ + { \ + STMEMSC_CTX_SPI_INCR(&iis328dq_config_##inst.stmemsc_cfg), \ + .stmemsc_cfg = \ + { \ + .spi = SPI_DT_SPEC_INST_GET(inst, IIS328DQ_SPI_OPERATION, \ + 0), \ + }, \ + IIS328DQ_CONFIG_COMMON(inst) \ + } + +/* + * Instantiation macros used when a device is on an I2C bus. + */ + +#define IIS328DQ_CONFIG_I2C(inst) \ + { \ + STMEMSC_CTX_I2C_INCR(&iis328dq_config_##inst.stmemsc_cfg), \ + .stmemsc_cfg = \ + { \ + .i2c = I2C_DT_SPEC_INST_GET(inst), \ + }, \ + IIS328DQ_CONFIG_COMMON(inst) \ + } + +/* + * Main instantiation macro. Use of COND_CODE_1() selects the right + * bus-specific macro at preprocessor time. + */ + +#define IIS328DQ_DEFINE(inst) \ + static struct iis328dq_data iis328dq_data_##inst; \ + static const struct iis328dq_config iis328dq_config_##inst = \ + COND_CODE_1(DT_INST_ON_BUS(inst, spi), (IIS328DQ_CONFIG_SPI(inst)), \ + (IIS328DQ_CONFIG_I2C(inst))); \ + IIS328DQ_DEVICE_INIT(inst) \ + IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, drdy_int_pad), \ + (BUILD_ASSERT( \ + DT_INST_NODE_HAS_PROP( \ + inst, CONCAT(int, DT_INST_PROP(inst, drdy_int_pad), _gpios)), \ + "No GPIO pin defined for IIS328DQ DRDY interrupt");)) \ + IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, threshold_int_pad), \ + (BUILD_ASSERT(DT_INST_NODE_HAS_PROP( \ + inst, CONCAT(int, DT_INST_PROP(inst, threshold_int_pad), \ + _gpios)), \ + "No GPIO pin defined for IIS328DQ threshold interrupt");)) \ + IF_ENABLED( \ + UTIL_AND(DT_INST_NODE_HAS_PROP(inst, drdy_int_pad), \ + DT_INST_NODE_HAS_PROP(inst, threshold_int_pad)), \ + (BUILD_ASSERT( \ + DT_INST_PROP(inst, drdy_int_pad) != \ + DT_INST_PROP(inst, threshold_int_pad), \ + "IIS328DQ DRDY interrupt and threshold interrupt cannot share a pin");)) + +DT_INST_FOREACH_STATUS_OKAY(IIS328DQ_DEFINE) diff --git a/drivers/sensor/iis328dq/iis328dq.h b/drivers/sensor/iis328dq/iis328dq.h new file mode 100644 index 00000000000..8b9975c82bb --- /dev/null +++ b/drivers/sensor/iis328dq/iis328dq.h @@ -0,0 +1,93 @@ +/* ST Microelectronics IIS328DQ 3-axis accelerometer driver + * + * Copyright (c) 2020 STMicroelectronics + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + * + * Datasheet: + * https://www.st.com/resource/en/datasheet/iis328dq.pdf + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_IIS328DQ_IIS328DQ_H_ +#define ZEPHYR_DRIVERS_SENSOR_IIS328DQ_IIS328DQ_H_ + +#include +#include +#include +#include +#include "iis328dq_reg.h" + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ + +/** + * struct iis328dq_dev_config - iis328dq hw configuration + * @bus_name: Pointer to bus master identifier. + * @pm: Power mode (lis2dh_powermode). + * @irq_dev_name: Pointer to GPIO PORT identifier. + * @irq_pin: GPIO pin number connected to sensor int pin. + * @drdy_int: Sensor drdy int (int1/int2). + */ +struct iis328dq_config { + stmdev_ctx_t ctx; + union { +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) + const struct i2c_dt_spec i2c; +#endif +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) + const struct spi_dt_spec spi; +#endif + } stmemsc_cfg; + uint8_t range; +#ifdef CONFIG_IIS328DQ_TRIGGER + const struct gpio_dt_spec gpio_int1; + const struct gpio_dt_spec gpio_int2; + /* interrupt pad to be used for DRDY interrupts, or -1 if not configured */ + int8_t drdy_pad; +#ifdef CONFIG_IIS328DQ_THRESHOLD + /* interrupt pad to be used for threshold interrupts, or -1 if not configured */ + int8_t threshold_pad; +#endif /* CONFIG_IIS328DQ_THRESHOLD */ +#endif /* CONFIG_IIS328DQ_TRIGGER */ +}; + +/* sensor data */ +struct iis328dq_data { + const struct device *dev; + int16_t acc[3]; + + /* sensitivity in mg/LSB */ + uint8_t gain; + +#ifdef CONFIG_IIS328DQ_TRIGGER + struct gpio_callback int1_cb; + struct gpio_callback int2_cb; + sensor_trigger_handler_t drdy_handler; + const struct sensor_trigger *drdy_trig; +#ifdef CONFIG_IIS328DQ_THRESHOLD + sensor_trigger_handler_t threshold_handler; + const struct sensor_trigger *threshold_trig; +#endif /* CONFIG_IIS328DQ_THRESHOLD */ +#if defined(CONFIG_IIS328DQ_TRIGGER_OWN_THREAD) + K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_IIS328DQ_THREAD_STACK_SIZE); + struct k_thread thread; + struct k_sem gpio_sem; +#elif defined(CONFIG_IIS328DQ_TRIGGER_GLOBAL_THREAD) + struct k_work work; +#endif /* CONFIG_IIS328DQ_TRIGGER_GLOBAL_THREAD */ +#endif /* CONFIG_IIS328DQ_TRIGGER */ +}; + +#ifdef CONFIG_IIS328DQ_TRIGGER +int iis328dq_init_interrupt(const struct device *dev); +int iis328dq_trigger_set(const struct device *dev, const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); +#endif /* CONFIG_IIS328DQ_TRIGGER */ + +#endif /* ZEPHYR_DRIVERS_SENSOR_IIS328DQ_IIS328DQ_H_ */ diff --git a/drivers/sensor/iis328dq/iis328dq_trigger.c b/drivers/sensor/iis328dq/iis328dq_trigger.c new file mode 100644 index 00000000000..06b9892ea96 --- /dev/null +++ b/drivers/sensor/iis328dq/iis328dq_trigger.c @@ -0,0 +1,332 @@ +/* ST Microelectronics IIS328DQ 3-axis accelerometer driver + * + * Copyright (c) 2020 STMicroelectronics + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + * + * Datasheet: + * https://www.st.com/resource/en/datasheet/iis328dq.pdf + */ + +#define DT_DRV_COMPAT st_iis328dq + +#include +#include +#include +#include + +#include "iis328dq.h" + +LOG_MODULE_DECLARE(IIS328DQ, CONFIG_SENSOR_LOG_LEVEL); + +static int iis328dq_set_int_pad_state(const struct device *dev, uint8_t pad, bool enable) +{ + const struct iis328dq_config *cfg = dev->config; + + int state = enable ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE; + + if (pad == 1) { + return gpio_pin_interrupt_configure_dt(&cfg->gpio_int1, state); + } else if (pad == 2) { + return gpio_pin_interrupt_configure_dt(&cfg->gpio_int2, state); + } else { + return -EINVAL; + } +} + +/** + * iis328dq_enable_int - enable selected int pin to generate interrupt + */ +static int iis328dq_enable_int(const struct device *dev, const struct sensor_trigger *trig, + int enable) +{ + const struct iis328dq_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + + switch (trig->type) { + case SENSOR_TRIG_DATA_READY: + if (cfg->drdy_pad == 1) { + /* route DRDY to PAD1 */ + if (iis328dq_pin_int1_route_set(ctx, IIS328DQ_PAD1_DRDY) != 0) { + return -EIO; + } + } else if (cfg->drdy_pad == 2) { + /* route DRDY to PAD2 */ + if (iis328dq_pin_int2_route_set(ctx, IIS328DQ_PAD2_DRDY) != 0) { + return -EIO; + } + } else { + LOG_ERR("No interrupt pin configured for DRDY in devicetree"); + return -ENOTSUP; + } + return iis328dq_set_int_pad_state(dev, cfg->drdy_pad, enable); +#ifdef CONFIG_IIS328DQ_THRESHOLD + case SENSOR_TRIG_THRESHOLD: { + /* set up internal INT1 for lower thresholds */ + int1_on_th_conf_t int1_conf = {0}; + + switch (trig->chan) { + case SENSOR_CHAN_ACCEL_X: + int1_conf.int1_xlie = 1; + break; + case SENSOR_CHAN_ACCEL_Y: + int1_conf.int1_ylie = 1; + break; + case SENSOR_CHAN_ACCEL_Z: + int1_conf.int1_zlie = 1; + break; + case SENSOR_CHAN_ACCEL_XYZ: + int1_conf.int1_xlie = 1; + int1_conf.int1_ylie = 1; + int1_conf.int1_zlie = 1; + break; + default: + LOG_ERR("Invalid sensor channel %d", trig->chan); + return -EINVAL; + } + + if (iis328dq_int1_on_threshold_conf_set(ctx, int1_conf) != 0) { + return -EIO; + } + + /* set up internal INT2 for uppper thresholds */ + int2_on_th_conf_t int2_conf = {0}; + + int2_conf.int2_xhie = int1_conf.int1_xlie; + int2_conf.int2_yhie = int1_conf.int1_ylie; + int2_conf.int2_zhie = int1_conf.int1_zlie; + if (iis328dq_int2_on_threshold_conf_set(ctx, int2_conf) != 0) { + return -EIO; + } + + if (cfg->threshold_pad == 1) { + /* route both internal interrupts to PAD1 */ + if (iis328dq_pin_int1_route_set(ctx, IIS328DQ_PAD1_INT1_OR_INT2_SRC) != 0) { + return -EIO; + } + } else if (cfg->threshold_pad == 2) { + /* route both internal interrupts to PAD2 */ + if (iis328dq_pin_int2_route_set(ctx, IIS328DQ_PAD2_INT1_OR_INT2_SRC) != 0) { + return -EIO; + } + } else { + LOG_ERR("No interrupt pin configured for DRDY in devicetree"); + return -ENOTSUP; + } + return iis328dq_set_int_pad_state(dev, cfg->threshold_pad, enable); + } +#endif /* CONFIG_IIS328DQ_THRESHOLD */ + default: + LOG_ERR("Unsupported trigger interrupt route %d", trig->type); + return -ENOTSUP; + } + + return 0; +} + +/** + * iis328dq_trigger_set - link external trigger to event data ready + */ +int iis328dq_trigger_set(const struct device *dev, const struct sensor_trigger *trig, + sensor_trigger_handler_t handler) +{ + const struct iis328dq_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + struct iis328dq_data *iis328dq = dev->data; + int16_t raw[3]; + int state = (handler != NULL) ? PROPERTY_ENABLE : PROPERTY_DISABLE; + + if (!cfg->gpio_int1.port && !cfg->gpio_int2.port) { + /* no interrupts configured */ + return -ENOTSUP; + } + + switch (trig->type) { + case SENSOR_TRIG_DATA_READY: + iis328dq->drdy_handler = handler; + iis328dq->drdy_trig = trig; + if (state) { + /* dummy read: re-trigger interrupt */ + iis328dq_acceleration_raw_get(ctx, raw); + } + break; +#ifdef CONFIG_IIS328DQ_THRESHOLD + case SENSOR_TRIG_THRESHOLD: + iis328dq->threshold_handler = handler; + iis328dq->threshold_trig = trig; + break; +#endif /* CONFIG_IIS328DQ_THRESHOLD */ + default: + LOG_ERR("Unsupported sensor trigger"); + return -ENOTSUP; + } + + return iis328dq_enable_int(dev, trig, state); +} + +/** + * iis328dq_handle_interrupt - handle the drdy event + * read data and call handler if registered any + */ +static void iis328dq_handle_interrupt(const struct device *dev) +{ + const struct iis328dq_config *cfg = dev->config; + struct iis328dq_data *data = dev->data; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + iis328dq_status_reg_t status; + iis328dq_int1_src_t sources1; + iis328dq_int2_src_t sources2; + + iis328dq_status_reg_get(ctx, &status); + + if (status.zyxda) { + if (data->drdy_handler) { + data->drdy_handler(dev, data->drdy_trig); + } + + iis328dq_set_int_pad_state(dev, cfg->drdy_pad, true); + } +#ifdef CONFIG_IIS328DQ_THRESHOLD + iis328dq_int1_src_get(ctx, &sources1); + iis328dq_int2_src_get(ctx, &sources2); + if (sources1.ia || sources2.ia) { + if (data->threshold_handler) { + data->threshold_handler(dev, data->threshold_trig); + } + + iis328dq_set_int_pad_state(dev, cfg->threshold_pad, true); + } +#endif /* CONFIG_IIS328DQ_THRESHOLD */ +} + +static void iis328dq_int1_gpio_callback(const struct device *dev, struct gpio_callback *cb, + uint32_t pins) +{ + struct iis328dq_data *iis328dq = CONTAINER_OF(cb, struct iis328dq_data, int1_cb); + + ARG_UNUSED(pins); + + iis328dq_set_int_pad_state(iis328dq->dev, 1, true); + +#if defined(CONFIG_IIS328DQ_TRIGGER_OWN_THREAD) + k_sem_give(&iis328dq->gpio_sem); +#elif defined(CONFIG_IIS328DQ_TRIGGER_GLOBAL_THREAD) + k_work_submit(&iis328dq->work); +#endif /* CONFIG_IIS328DQ_TRIGGER_OWN_THREAD */ +} + +static void iis328dq_int2_gpio_callback(const struct device *dev, struct gpio_callback *cb, + uint32_t pins) +{ + struct iis328dq_data *iis328dq = CONTAINER_OF(cb, struct iis328dq_data, int2_cb); + + ARG_UNUSED(pins); + + iis328dq_set_int_pad_state(iis328dq->dev, 2, true); + +#if defined(CONFIG_IIS328DQ_TRIGGER_OWN_THREAD) + k_sem_give(&iis328dq->gpio_sem); +#elif defined(CONFIG_IIS328DQ_TRIGGER_GLOBAL_THREAD) + k_work_submit(&iis328dq->work); +#endif /* CONFIG_IIS328DQ_TRIGGER_OWN_THREAD */ +} + +#ifdef CONFIG_IIS328DQ_TRIGGER_OWN_THREAD +static void iis328dq_thread(void *p1, void *p2, void *p3) +{ + ARG_UNUSED(p2); + ARG_UNUSED(p3); + + struct iis328dq_data *iis328dq = p1; + + while (1) { + k_sem_take(&iis328dq->gpio_sem, K_FOREVER); + iis328dq_handle_interrupt(iis328dq->dev); + } +} +#endif /* CONFIG_IIS328DQ_TRIGGER_OWN_THREAD */ + +#ifdef CONFIG_IIS328DQ_TRIGGER_GLOBAL_THREAD +static void iis328dq_work_cb(struct k_work *work) +{ + struct iis328dq_data *iis328dq = CONTAINER_OF(work, struct iis328dq_data, work); + + iis328dq_handle_interrupt(iis328dq->dev); +} +#endif /* CONFIG_IIS328DQ_TRIGGER_GLOBAL_THREAD */ + +int iis328dq_init_interrupt(const struct device *dev) +{ + struct iis328dq_data *iis328dq = dev->data; + const struct iis328dq_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + int ret; + + if (!cfg->gpio_int1.port && !cfg->gpio_int2.port) { + /* no interrupts configured, nothing to do */ + return 0; + } + + /* setup data ready gpio interrupt (INT1 and INT2) */ + if (cfg->gpio_int1.port) { + if (!gpio_is_ready_dt(&cfg->gpio_int1)) { + LOG_ERR("INT_1 pin is not ready"); + return -EINVAL; + } + } + if (cfg->gpio_int2.port) { + if (!gpio_is_ready_dt(&cfg->gpio_int2)) { + LOG_ERR("INT_2 pin is not ready"); + return -EINVAL; + } + } + +#if defined(CONFIG_IIS328DQ_TRIGGER_OWN_THREAD) + k_sem_init(&iis328dq->gpio_sem, 0, K_SEM_MAX_LIMIT); + + k_thread_create(&iis328dq->thread, iis328dq->thread_stack, + CONFIG_IIS328DQ_THREAD_STACK_SIZE, iis328dq_thread, iis328dq, NULL, NULL, + K_PRIO_COOP(CONFIG_IIS328DQ_THREAD_PRIORITY), 0, K_NO_WAIT); +#elif defined(CONFIG_IIS328DQ_TRIGGER_GLOBAL_THREAD) + iis328dq->work.handler = iis328dq_work_cb; +#endif /* CONFIG_IIS328DQ_TRIGGER_OWN_THREAD */ + + if (cfg->gpio_int1.port) { + ret = gpio_pin_configure_dt(&cfg->gpio_int1, GPIO_INPUT); + if (ret < 0) { + LOG_ERR("Could not configure INT_1 gpio"); + return ret; + } + gpio_init_callback(&iis328dq->int1_cb, iis328dq_int1_gpio_callback, + BIT(cfg->gpio_int1.pin)); + if (gpio_add_callback(cfg->gpio_int1.port, &iis328dq->int1_cb) < 0) { + LOG_ERR("Could not set INT1 callback"); + return -EIO; + } + } + + if (cfg->gpio_int2.port) { + ret = gpio_pin_configure_dt(&cfg->gpio_int2, GPIO_INPUT); + if (ret < 0) { + LOG_ERR("Could not configure INT_2 gpio"); + return ret; + } + gpio_init_callback(&iis328dq->int2_cb, iis328dq_int2_gpio_callback, + BIT(cfg->gpio_int2.pin)); + if (gpio_add_callback(cfg->gpio_int2.port, &iis328dq->int2_cb) < 0) { + LOG_ERR("Could not set INT2 callback"); + return -EIO; + } + } + + if (iis328dq_int1_notification_set(ctx, IIS328DQ_INT1_PULSED) != 0) { + return -EIO; + } + + if (iis328dq_int2_notification_set(ctx, IIS328DQ_INT2_PULSED) != 0) { + return -EIO; + } + + return 0; +} diff --git a/dts/bindings/sensor/st,iis328dq-common.yaml b/dts/bindings/sensor/st,iis328dq-common.yaml new file mode 100644 index 00000000000..1be30c406f4 --- /dev/null +++ b/dts/bindings/sensor/st,iis328dq-common.yaml @@ -0,0 +1,61 @@ +# Copyright (c) 2018 STMicroelectronics +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +include: sensor-device.yaml + +properties: + int1-gpios: + type: phandle-array + description: | + INT_1 pin + + This pin defaults to active high when produced by the sensor. The property value should ensure + the flags properly describe the signal that is presented to the driver. + + int2-gpios: + type: phandle-array + description: | + INT_2 pin + + This pin defaults to active high when produced by the sensor. The property value should ensure + the flags properly describe the signal that is presented to the driver. + + drdy-int-pad: + type: int + enum: [1, 2] + description: | + Select DRDY pin number (1 or 2). + + This number represents which of the two interrupt pins (INT_1 or INT_2), if any, the DRDY + interrupt should be generated from. If this property is not specified, no data ready + interrupts can be registered. + + - 1 # drdy is generated on INT1 + - 2 # drdy is generated on INT2 + + threshold-int-pad: + type: int + enum: [1, 2] + description: | + Select threshold interrupt pin number (1 or 2). + + This number represents which of the two interrupt pins (INT_1 or INT_2), if any, the threshold + interrupt should be generated from. If this property is not specified, no threshold interrupts + can be registered. + + - 1 # threshold interrupt is generated on INT1 + - 2 # threshold interrupt is generated on INT2 + + range: + type: int + default: 2 + description: | + Range in g. Default is power-up configuration. + + - 16 # 16g (1.952 mg/LSB) + - 8 # 8g (0.976 mg/LSB) + - 4 # 4g (0.488 mg/LSB) + - 2 # 2g (0.244 mg/LSB) + + enum: [16, 8, 4, 2] diff --git a/dts/bindings/sensor/st,iis328dq-i2c.yaml b/dts/bindings/sensor/st,iis328dq-i2c.yaml new file mode 100644 index 00000000000..abb9ea8705e --- /dev/null +++ b/dts/bindings/sensor/st,iis328dq-i2c.yaml @@ -0,0 +1,10 @@ +# Copyright (c) 2018 STMicroelectronics +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +description: | + STMicroelectronics IIS328DQ accelerometer accessed through I2C bus + +compatible: "st,iis328dq" + +include: ["i2c-device.yaml", "st,iis328dq-common.yaml"] diff --git a/dts/bindings/sensor/st,iis328dq-spi.yaml b/dts/bindings/sensor/st,iis328dq-spi.yaml new file mode 100644 index 00000000000..34ba86236c0 --- /dev/null +++ b/dts/bindings/sensor/st,iis328dq-spi.yaml @@ -0,0 +1,10 @@ +# Copyright (c) 2019 STMicroelectronics +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +description: | + STMicroelectronics IIS328DQ accelerometer accessed through SPI bus + +compatible: "st,iis328dq" + +include: ["spi-device.yaml", "st,iis328dq-common.yaml"] diff --git a/tests/drivers/build_all/sensor/app.overlay b/tests/drivers/build_all/sensor/app.overlay index 898ae96ec0d..c9582338fba 100644 --- a/tests/drivers/build_all/sensor/app.overlay +++ b/tests/drivers/build_all/sensor/app.overlay @@ -120,13 +120,14 @@ <&test_gpio 0 0>, <&test_gpio 0 0>, <&test_gpio 0 0>, - <&test_gpio 0 0>, /* 0x25 */ - <&test_gpio 0 0>, /* 0x26 */ - <&test_gpio 0 0>, /* 0x27 */ - <&test_gpio 0 0>, /* 0x28 */ - <&test_gpio 0 0>, /* 0x29 */ - <&test_gpio 0 0>, /* 0x2A */ - <&test_gpio 0 0>; /* 0x2B */ + <&test_gpio 0 0>, + <&test_gpio 0 0>, + <&test_gpio 0 0>, + <&test_gpio 0 0>, + <&test_gpio 0 0>, + <&test_gpio 0 0>, + <&test_gpio 0 0>, + <&test_gpio 0 0>; /* 0x2C */ #include "spi.dtsi" }; diff --git a/tests/drivers/build_all/sensor/i2c.dtsi b/tests/drivers/build_all/sensor/i2c.dtsi index a51a525fd6f..e25e649df78 100644 --- a/tests/drivers/build_all/sensor/i2c.dtsi +++ b/tests/drivers/build_all/sensor/i2c.dtsi @@ -1011,3 +1011,11 @@ test_i2c_am2301b: am2301b@89 { reg = <0x89>; status = "okay"; }; + +test_i2c_iis328dq: iis328dq@8a { + compatible = "st,iis328dq"; + status = "okay"; + reg = <0x8a>; + int2-gpios = <&test_gpio 0 0>; + threshold-int-pad = <2>; +}; diff --git a/tests/drivers/build_all/sensor/spi.dtsi b/tests/drivers/build_all/sensor/spi.dtsi index c7edf356893..b8fd5e56b0b 100644 --- a/tests/drivers/build_all/sensor/spi.dtsi +++ b/tests/drivers/build_all/sensor/spi.dtsi @@ -352,3 +352,12 @@ test_spi_bd8lb600fs: bd8lb600fs@2b { #sensor-cells = <0>; }; }; + +test_spi_iis328dq: iis328dq@2c { + compatible = "st,iis328dq"; + status = "okay"; + reg = <0x2c>; + spi-max-frequency = <0>; + int1-gpios = <&test_gpio 0 0>; + drdy-int-pad = <1>; +}; From 9c3e24283b51a2054aa4f14a79c531349cd24a09 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 29 Mar 2024 10:56:50 +0100 Subject: [PATCH 1645/2402] boards: st: nucleo_wb55rg: Add led1 alias This board is missing the led1 alias, which prevents to use some samples such as basic/threads. Signed-off-by: Erwan Gouriou --- boards/st/nucleo_wb55rg/nucleo_wb55rg.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts index 21806ca24af..bdc61c71ad9 100644 --- a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts +++ b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts @@ -61,6 +61,7 @@ aliases { led0 = &green_led_2; + led1 = &blue_led_1; sw0 = &user_button_1; sw1 = &user_button_2; sw2 = &user_button_3; From d076962f73d34958afec98ac2a0ba5932b3ed111 Mon Sep 17 00:00:00 2001 From: Maciej Dubiel Date: Tue, 12 Dec 2023 10:13:57 +0100 Subject: [PATCH 1646/2402] twister: ut for config_parser.py initial commit Signed-off-by: Maciej Dubiel --- scripts/tests/twister/test_config_parser.py | 195 ++++++++++++++++++++ 1 file changed, 195 insertions(+) create mode 100644 scripts/tests/twister/test_config_parser.py diff --git a/scripts/tests/twister/test_config_parser.py b/scripts/tests/twister/test_config_parser.py new file mode 100644 index 00000000000..75189588373 --- /dev/null +++ b/scripts/tests/twister/test_config_parser.py @@ -0,0 +1,195 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Tests for config_parser.py +""" + +import os +import pytest +import mock +import scl + +from twisterlib.config_parser import TwisterConfigParser, extract_fields_from_arg_list, ConfigurationError +from contextlib import nullcontext + +def test_extract_single_field_from_string_argument(): + target_fields = {"FIELD1"} + arg_list = "FIELD1=value1 FIELD2=value2 FIELD3=value3" + extracted_fields, other_fields = extract_fields_from_arg_list( + target_fields, arg_list) + + assert extracted_fields == {"FIELD1": ["value1"]} + assert other_fields == "FIELD2=value2 FIELD3=value3" + + +def test_no_fields_to_extract(): + target_fields = set() + arg_list = "arg1 arg2 arg3" + + extracted_fields, other_fields = extract_fields_from_arg_list( + target_fields, arg_list) + + assert extracted_fields == {} + assert other_fields == "arg1 arg2 arg3" + + +def test_missing_fields(): + target_fields = {"CONF_FILE", "OVERLAY_CONFIG", "DTC_OVERLAY_FILE"} + arg_list = "arg1 arg2 arg3" + extracted_fields, other_fields = extract_fields_from_arg_list( + target_fields, arg_list) + + assert extracted_fields == {"CONF_FILE": [], "OVERLAY_CONFIG": [], "DTC_OVERLAY_FILE": []} + assert other_fields == "arg1 arg2 arg3" + +def test_load_yaml_with_extra_args_and_retrieve_scenario_data(zephyr_base): + filename = "test_data.yaml" + + yaml_data = ''' + tests: + scenario1: + tags: ['tag1', 'tag2'] + extra_args: '--CONF_FILE=file1.conf --OVERLAY_CONFIG=config1.conf' + filter: 'filter1' + common: + filter: 'filter2' + ''' + + loaded_schema = scl.yaml_load( + os.path.join(zephyr_base, 'scripts', 'schemas','twister', 'testsuite-schema.yaml') + ) + + with mock.patch('builtins.open', mock.mock_open(read_data=yaml_data)): + parser = TwisterConfigParser(filename, loaded_schema) + parser.load() + + scenario_data = parser.get_scenario('scenario1') + scenario_common = parser.common + + assert scenario_data['tags'] == {'tag1', 'tag2'} + assert scenario_data['extra_args'] == ['--CONF_FILE=file1.conf', '--OVERLAY_CONFIG=config1.conf'] + assert scenario_common == {'filter': 'filter2'} + + +def test_default_values(zephyr_base): + filename = "test_data.yaml" + + yaml_data = ''' + tests: + scenario1: + tags: 'tag1' + extra_args: '' + ''' + + loaded_schema = scl.yaml_load( + os.path.join(zephyr_base, 'scripts', 'schemas', 'twister','testsuite-schema.yaml') + ) + + with mock.patch('builtins.open', mock.mock_open(read_data=yaml_data)): + parser = TwisterConfigParser(filename, loaded_schema) + parser.load() + + expected_scenario_data = { 'type': 'integration', + 'extra_args': [], + 'extra_configs': [], + 'extra_conf_files': [], + 'extra_overlay_confs': [], + 'extra_dtc_overlay_files': [], + 'required_snippets': [], + 'build_only': False, + 'build_on_all': False, + 'skip': False, 'slow': False, + 'timeout': 60, + 'min_ram': 8, + 'modules': [], + 'depends_on': set(), + 'min_flash': 32, + 'arch_allow': set(), + 'arch_exclude': set(), + 'extra_sections': [], + 'integration_platforms': [], + 'ignore_faults': False, + 'ignore_qemu_crash': False, + 'testcases': [], + 'platform_type': [], + 'platform_exclude': set(), + 'platform_allow': set(), + 'platform_key': [], + 'toolchain_exclude': set(), + 'toolchain_allow': set(), + 'filter': '', + 'levels': [], + 'harness': 'test', + 'harness_config': {}, + 'seed': 0, 'sysbuild': False + } + + assert expected_scenario_data.items() <= expected_scenario_data.items() + +@pytest.mark.parametrize( + 'value, typestr, expected', + [ + (' hello ', 'str', 'hello'), + ('3.14', 'float', 3.14), + ('10', 'int', 10), + ('True', 'bool', 'True'), # do-nothing cast + ('key: val', 'map', 'key: val'), # do-nothing cast + ('test', 'int', ValueError), + ('test', 'unknown', ConfigurationError), + ('1 2 2 3', 'list', ['1', '2', '2','3']), + ('1 2 2 3', 'set', {'1', '2', '3'}) + ], + ids=['str to str', 'str to float', 'str to int', 'str to bool', 'str to map', + 'invalid', 'to unknown', "to list", "to set"] +) + +def test_cast_value(zephyr_base, value, typestr, expected): + loaded_schema = scl.yaml_load( + os.path.join(zephyr_base, 'scripts', 'schemas', 'twister','testsuite-schema.yaml') + ) + + parser = TwisterConfigParser("config.yaml", loaded_schema) + with pytest.raises(expected) if \ + isinstance(expected, type) and issubclass(expected, Exception) else nullcontext(): + result = parser._cast_value(value, typestr) + assert result == expected + +def test_load_invalid_test_config_yaml(zephyr_base): + filename = "test_data.yaml" + + yaml_data = ''' + gibberish data + ''' + + loaded_schema = scl.yaml_load( + os.path.join(zephyr_base, 'scripts', 'schemas','twister', 'test-config-schema.yaml') + ) + + with mock.patch('builtins.open', mock.mock_open(read_data=yaml_data)): + parser = TwisterConfigParser(filename, loaded_schema) + with pytest.raises(Exception): + parser.load() + + +def test_load_yaml_with_no_scenario_data(zephyr_base): + filename = "test_data.yaml" + + yaml_data = ''' + tests: + common: + extra_args: '--CONF_FILE=file2.conf --OVERLAY_CONFIG=config2.conf' + ''' + + loaded_schema = scl.yaml_load( + os.path.join(zephyr_base, 'scripts', 'schemas','twister', 'testsuite-schema.yaml') + ) + + with mock.patch('builtins.open', mock.mock_open(read_data=yaml_data)): + parser = TwisterConfigParser(filename, loaded_schema) + parser.load() + + with pytest.raises(KeyError): + scenario_data = parser.get_scenario('scenario1') + assert scenario_data is None From 6d8132c445e848d2f516d4196c5d853be7bcf675 Mon Sep 17 00:00:00 2001 From: Artur Wilczak Date: Fri, 23 Feb 2024 14:14:12 +0100 Subject: [PATCH 1647/2402] scripts: tests: Blackbox test expension - disable Add test related to disable-suite-name-check flag This flag disabling extended test suite name verification at the beginning of Ztest test. This option could be useful for tests or platforms, which from some reasons cannot print early logs. Add test related disable-warnings-as-errors Do not treat warning conditions as errors. Signed-off-by: Artur Wilczak --- .../tests/always_warning/dummy/CMakeLists.txt | 8 ++ .../tests/always_warning/dummy/prj.conf | 7 + .../tests/always_warning/dummy/src/main.c | 26 ++++ .../tests/always_warning/dummy/test_data.yaml | 10 ++ .../tests/twister_blackbox/test_disable.py | 128 ++++++++++++++++++ 5 files changed, 179 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/test_data.yaml create mode 100644 scripts/tests/twister_blackbox/test_disable.py diff --git a/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/CMakeLists.txt new file mode 100644 index 00000000000..635c696edf9 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(integration) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/prj.conf new file mode 100644 index 00000000000..e26a1dfa9ec --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/prj.conf @@ -0,0 +1,7 @@ +CONFIG_ZTEST=y +CONFIG_TEST_LOGGING_DEFAULTS=y +CONFIG_LOG=y +CONFIG_LOG_OUTPUT=y +CONFIG_LOG_BACKEND_UART=y +CONFIG_LOG_MODE_IMMEDIATE=y +CONFIG_MAIN_STACK_SIZE=4096 diff --git a/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/src/main.c new file mode 100644 index 00000000000..20d99ce340d --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/src/main.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#define LOG_MODULE_NAME log_test +LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL_INF); + +ZTEST_SUITE(a1_1_tests, NULL, NULL, NULL, NULL, NULL); + +/** + * @brief Test Asserts + * + * This test verifies various assert macros provided by ztest. + * + */ +ZTEST(a1_1_tests, test_assert) +{ + TC_PRINT("Create log message before rise warning\n"); + LOG_WRN("log warning to custom warning"); + #warning ("Custom warning"); +} diff --git a/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/test_data.yaml new file mode 100644 index 00000000000..ae60a909160 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/always_warning/dummy/test_data.yaml @@ -0,0 +1,10 @@ +common: + timeout: 10 +tests: + always_warning.dummy: + platform_allow: + - native_posix + - qemu_x86 + - qemu_x86_64 + integration_platforms: + - native_posix diff --git a/scripts/tests/twister_blackbox/test_disable.py b/scripts/tests/twister_blackbox/test_disable.py new file mode 100644 index 00000000000..448c6f0eabf --- /dev/null +++ b/scripts/tests/twister_blackbox/test_disable.py @@ -0,0 +1,128 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions related to disable features. +""" + +import importlib +import pytest +import mock +import os +import sys +import re + +from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +class TestDisable: + TESTDATA_1 = [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), + ['qemu_x86'], + '--disable-suite-name-check', + [r"Expected suite names:\[['\w+'\[,\s]*\]", r"Detected suite names:\[['\w+'\[,\s]*\]"], + True + ), + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), + ['qemu_x86'], + '-v', + [r"Expected suite names:\[['(\w+)'[, ]*]+", r"Detected suite names:\[['(\w+)'[, ]*]+"], + False + ), + ] + TESTDATA_2 = [ + ( + os.path.join(TEST_DATA, 'tests', 'always_warning'), + ['qemu_x86'], + '--disable-warnings-as-errors', + '0' + ), + ( + os.path.join(TEST_DATA, 'tests', 'always_warning'), + ['qemu_x86'], + '-v', + '1' + ), + ] + + + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + + @classmethod + def teardown_class(cls): + pass + + + @pytest.mark.parametrize( + 'test_path, test_platforms, flag, expected, expected_none', + TESTDATA_1, + ids=[ + 'disable-suite-name-check', + 'suite-name-check' + ], + ) + + def test_disable_suite_name_check(self, capfd, out_path, test_path, test_platforms, flag, expected, expected_none): + args = ['-i', '--outdir', out_path, '-T', test_path] + \ + [flag] + \ + ['-vv'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == '0' + if expected_none: + assert re.search(expected[0], err) is None, f"Not expected string in log: {expected[0]}" + assert re.search(expected[1], err) is None, f"Not expected: {expected[1]}" + else: + assert re.search(expected[0], err) is not None, f"Expected string in log: {expected[0]}" + assert re.search(expected[1], err) is not None, f"Expected string in log: {expected[1]}" + + + @pytest.mark.parametrize( + 'test_path, test_platforms, flag, expected_exit_code', + TESTDATA_2, + ids=[ + 'disable-warnings-as-errors', + 'warnings-as-errors' + ], + ) + + def test_disable_warnings_as_errors(self, capfd, out_path, test_path, test_platforms, flag, expected_exit_code): + args = ['-i', '--outdir', out_path, '-T', test_path] + \ + [flag] + \ + ['-vv'] + \ + ['--build-only'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == expected_exit_code, \ + f"Twister return not expected ({expected_exit_code}) exit code: ({sys_exit.value})" From 717fccaa0920be2b7938095a1793bd08d5bcfbc2 Mon Sep 17 00:00:00 2001 From: Kamil Paszkiet Date: Tue, 26 Mar 2024 11:52:14 +0100 Subject: [PATCH 1648/2402] scripts: tests: Blackbox test expansion - device Adds tests related to device flags: --seed Signed-off-by: Kamil Paszkiet --- .../seed_native_posix/dummy/CMakeLists.txt | 8 ++ .../tests/seed_native_posix/dummy/Kconfig | 7 ++ .../tests/seed_native_posix/dummy/prj.conf | 1 + .../tests/seed_native_posix/dummy/src/main.c | 22 ++++++ .../seed_native_posix/dummy/test_data.yaml | 6 ++ scripts/tests/twister_blackbox/test_device.py | 75 +++++++++++++++++++ 6 files changed, 119 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/Kconfig create mode 100644 scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/test_data.yaml create mode 100644 scripts/tests/twister_blackbox/test_device.py diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/CMakeLists.txt new file mode 100644 index 00000000000..635c696edf9 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(integration) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/Kconfig b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/Kconfig new file mode 100644 index 00000000000..db9be4ed558 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/Kconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 Intel Corporation + +config FAKE_ENTROPY_NATIVE_POSIX + default y + +source "Kconfig.zephyr" diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/prj.conf new file mode 100644 index 00000000000..9467c292689 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/src/main.c new file mode 100644 index 00000000000..f2ee6dc18c2 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/src/main.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + + +ZTEST_SUITE(a1_1_tests, NULL, NULL, NULL, NULL, NULL); + +/** + * @brief Test Asserts + * + * This test verifies various assert macros provided by ztest. + * + */ +ZTEST(a1_1_tests, test_assert) +{ + zassert_true(0, "1 was false"); + zassert_false(1, "0 was true"); +} diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/test_data.yaml new file mode 100644 index 00000000000..a1d75183716 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/seed_native_posix/dummy/test_data.yaml @@ -0,0 +1,6 @@ +tests: + seed_native_posix.dummy: + platform_allow: + - native_posix + integration_platforms: + - native_posix diff --git a/scripts/tests/twister_blackbox/test_device.py b/scripts/tests/twister_blackbox/test_device.py new file mode 100644 index 00000000000..f84dd76a572 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_device.py @@ -0,0 +1,75 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions related to test filtering. +""" + +import importlib +import mock +import os +import pytest +import sys +import re + +from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +class TestDevice: + TESTDATA_1 = [ + ( + 1234, + ), + ( + 4321, + ), + ( + 1324, + ) + ] + + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @pytest.mark.parametrize( + 'seed', + TESTDATA_1, + ids=[ + 'seed 1234', + 'seed 4321', + 'seed 1324' + ], + ) + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_seed(self, capfd, out_path, seed): + test_platforms = ['native_posix'] + path = os.path.join(TEST_DATA, 'tests', 'seed_native_posix') + args = ['--outdir', out_path, '-i', '-T', path, '-vv',] + \ + ['--seed', f'{seed[0]}'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == '1' + + expected_line = r'seed_native_posix.dummy FAILED Failed \(native (\d+\.\d+)s/seed: {}\)'.format(seed[0]) + assert re.search(expected_line, err) From 6a0e6e4737df541502176f410baeb714fd23331d Mon Sep 17 00:00:00 2001 From: Kapil Bhatt Date: Wed, 27 Mar 2024 16:58:18 +0530 Subject: [PATCH 1649/2402] net: wifi: Replace numeric values with defines There should be a particular defines which clarify the use of that number. So, replacing numbers with defines in wifi shell. Signed-off-by: Kapil Bhatt --- include/zephyr/net/wifi_mgmt.h | 7 +++++++ subsys/net/l2/wifi/wifi_shell.c | 13 +++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h index 065852507d7..8b5854fb932 100644 --- a/include/zephyr/net/wifi_mgmt.h +++ b/include/zephyr/net/wifi_mgmt.h @@ -48,6 +48,13 @@ extern "C" { #endif /* CONFIG_WIFI_MGMT_SCAN_CHAN_MAX_MANUAL */ #define WIFI_MGMT_BAND_STR_SIZE_MAX 8 +#define WIFI_MGMT_SCAN_MIN_DWELL_TIME_ACTIVE 5 +#define WIFI_MGMT_SCAN_MAX_DWELL_TIME_ACTIVE 1000 +#define WIFI_MGMT_SCAN_MIN_DWELL_TIME_PASSIVE 10 +#define WIFI_MGMT_SCAN_MAX_DWELL_TIME_PASSIVE 1000 +#define WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_ACTIVE 50 +#define WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_PASSIVE 130 +#define WIFI_MGMT_SCAN_MAX_BSS_CNT 65535 /** Wi-Fi management commands */ enum net_request_wifi_cmd { diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 759eebc19f6..d985d810ed0 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -683,7 +683,8 @@ static int wifi_scan_args_to_params(const struct shell *sh, case 'a': val = atoi(state->optarg); - if ((val < 5) || (val > 1000)) { + if ((val < WIFI_MGMT_SCAN_MIN_DWELL_TIME_ACTIVE) || + (val > WIFI_MGMT_SCAN_MAX_DWELL_TIME_ACTIVE)) { PR_ERROR("Invalid dwell_time_active val\n"); return -ENOEXEC; } @@ -694,7 +695,8 @@ static int wifi_scan_args_to_params(const struct shell *sh, case 'p': val = atoi(state->optarg); - if ((val < 10) || (val > 1000)) { + if ((val < WIFI_MGMT_SCAN_MIN_DWELL_TIME_PASSIVE) || + (val > WIFI_MGMT_SCAN_MAX_DWELL_TIME_PASSIVE)) { PR_ERROR("Invalid dwell_time_passive val\n"); return -ENOEXEC; } @@ -715,7 +717,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, case 'm': val = atoi(state->optarg); - if ((val < 0) || (val > 65535)) { + if ((val < 0) || (val > WIFI_MGMT_SCAN_MAX_BSS_CNT)) { PR_ERROR("Invalid max_bss val\n"); return -ENOEXEC; } @@ -752,7 +754,10 @@ static int wifi_scan_args_to_params(const struct shell *sh, static int cmd_wifi_scan(const struct shell *sh, size_t argc, char *argv[]) { struct net_if *iface = net_if_get_first_wifi(); - struct wifi_scan_params params = { .dwell_time_active = 50, .dwell_time_passive = 130, }; + struct wifi_scan_params params = { .dwell_time_active = + WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_ACTIVE, + .dwell_time_passive = + WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_PASSIVE, }; bool do_scan = true; int opt_num; From 10d9099356728b5c7680efceafe022e9e8f968dd Mon Sep 17 00:00:00 2001 From: Kapil Bhatt Date: Thu, 28 Mar 2024 12:17:11 +0530 Subject: [PATCH 1650/2402] net: wifi: Add reasons for 4 way handshake failure When there is 4 way handshake timeout, it can be because of incorrect credential or some times when AP's signal strength is weak. It can cause 4 way handshake fail. Adding comment where WIFI_STATUS_CONN_WRONG_PASSWORD is defined. Signed-off-by: Kapil Bhatt --- include/zephyr/net/wifi_mgmt.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h index 8b5854fb932..7a812c4fa7e 100644 --- a/include/zephyr/net/wifi_mgmt.h +++ b/include/zephyr/net/wifi_mgmt.h @@ -380,7 +380,14 @@ enum wifi_conn_status { WIFI_STATUS_CONN_SUCCESS = 0, /** Connection failed - generic failure */ WIFI_STATUS_CONN_FAIL, - /** Connection failed - wrong password */ + /** Connection failed - wrong password + * Few possible reasons for 4-way handshake failure that we can guess are as follows: + * 1) Incorrect key + * 2) EAPoL frames lost causing timeout + * + * #1 is the likely cause, so, we convey to the user that it is due to + * Wrong passphrase/password. + */ WIFI_STATUS_CONN_WRONG_PASSWORD, /** Connection timed out */ WIFI_STATUS_CONN_TIMEOUT, From 3102fdc8c12465a576838b6c25fe232156efda17 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Wed, 27 Mar 2024 13:31:33 +0100 Subject: [PATCH 1651/2402] bindesc: Update build time without re-running cmake entirely With CONFIG_BINDESC_BUILD_TIME_ALWAYS_REBUILD a re-run was called for the entire project. This can result in issues with the zephyr linker mechanism. Signed-off-by: Pieter De Gendt --- subsys/bindesc/CMakeLists.txt | 72 +++++++------------ subsys/bindesc/Kconfig.build_time | 3 - subsys/bindesc/bindesc_build_time.c | 3 + subsys/bindesc/bindesc_build_time.h.in | 18 +++++ subsys/bindesc/gen_bindesc_build_time_h.cmake | 39 ++++++++++ 5 files changed, 86 insertions(+), 49 deletions(-) create mode 100644 subsys/bindesc/bindesc_build_time.h.in create mode 100644 subsys/bindesc/gen_bindesc_build_time_h.cmake diff --git a/subsys/bindesc/CMakeLists.txt b/subsys/bindesc/CMakeLists.txt index 9dcb467208d..c597eddd3de 100644 --- a/subsys/bindesc/CMakeLists.txt +++ b/subsys/bindesc/CMakeLists.txt @@ -9,32 +9,6 @@ else() zephyr_linker_sources(ROM_START SORT_KEY 0x1bindesc bindesc.ld) endif() -# Wrapper macro around string(TIMESTAMP ...), that returns the time -# in either local time or UTC, depending on CONFIG_BINDESC_BUILD_TIME_USE_LOCAL_TIME. -macro(get_time out_var format) - if(CONFIG_BINDESC_BUILD_TIME_USE_LOCAL_TIME) - string(TIMESTAMP ${out_var} ${format}) - else() - string(TIMESTAMP ${out_var} ${format} UTC) - endif() -endmacro() - -macro(gen_build_time_int_definition def_name format) - if(CONFIG_BINDESC_${def_name}) - get_time(${def_name} ${format}) - # remove leading zeros so that the output will not be interpreted as octal - math(EXPR ${def_name} ${${def_name}}) - zephyr_library_compile_definitions(${def_name}=${${def_name}}) - endif() -endmacro() - -macro(gen_build_time_str_definition def_name format) - if(CONFIG_BINDESC_${def_name}) - get_time(${def_name} ${${format}}) - zephyr_library_compile_definitions(${def_name}="${${def_name}}") - endif() -endmacro() - macro(gen_str_definition def_name value) if(CONFIG_BINDESC_${def_name}) zephyr_library_compile_definitions(${def_name}="${value}") @@ -43,31 +17,37 @@ endmacro() if(CONFIG_BINDESC_DEFINE_BUILD_TIME) zephyr_library_sources(bindesc_build_time.c) - gen_build_time_int_definition(BUILD_TIME_YEAR "%Y") - gen_build_time_int_definition(BUILD_TIME_MONTH "%m") - gen_build_time_int_definition(BUILD_TIME_DAY "%d") - gen_build_time_int_definition(BUILD_TIME_HOUR "%H") - gen_build_time_int_definition(BUILD_TIME_MINUTE "%M") - gen_build_time_int_definition(BUILD_TIME_SECOND "%S") - gen_build_time_int_definition(BUILD_TIME_UNIX "%s") - gen_build_time_str_definition(BUILD_DATE_TIME_STRING - CONFIG_BINDESC_BUILD_DATE_TIME_STRING_FORMAT) - gen_build_time_str_definition(BUILD_DATE_STRING - CONFIG_BINDESC_BUILD_DATE_STRING_FORMAT) - gen_build_time_str_definition(BUILD_TIME_STRING - CONFIG_BINDESC_BUILD_TIME_STRING_FORMAT) + set(gen_header ${PROJECT_BINARY_DIR}/include/generated/bindesc_build_time.h) + + if(CONFIG_BINDESC_BUILD_TIME_USE_LOCAL_TIME) + set(BUILD_TIME "LOCAL") + else() + set(BUILD_TIME "UTC") + endif() + + set(GEN_COMMAND ${CMAKE_COMMAND} + -DIN_FILE=${CMAKE_CURRENT_LIST_DIR}/bindesc_build_time.h.in + -DOUT_FILE=${gen_header} + -DBUILD_TIME_TYPE="${BUILD_TIME}" + -DBUILD_DATE_TIME_STRING_FORMAT="${CONFIG_BINDESC_BUILD_DATE_TIME_STRING_FORMAT}" + -DBUILD_DATE_STRING_FORMAT="${CONFIG_BINDESC_BUILD_DATE_STRING_FORMAT}" + -DBUILD_TIME_STRING_FORMAT="${CONFIG_BINDESC_BUILD_TIME_STRING_FORMAT}" + -P ${CMAKE_CURRENT_LIST_DIR}/gen_bindesc_build_time_h.cmake) if(CONFIG_BINDESC_BUILD_TIME_ALWAYS_REBUILD) - # By adding a custom target that invokes cmake, - # CMake is forced to rebuild this target on every build. This is - # done to ensure that the timestamp is always up to date. - add_custom_target( - bindesc_time_force_rebuild - COMMAND ${CMAKE_COMMAND} ${CMAKE_BINARY_DIR} + add_custom_target(gen_bindesc_build_time + COMMAND ${GEN_COMMAND} + BYPRODUCTS ${gen_header} ) - zephyr_library_add_dependencies(bindesc_time_force_rebuild) + else() + add_custom_command(OUTPUT ${gen_header} + COMMAND ${GEN_COMMAND} + ) + add_custom_target(gen_bindesc_build_time DEPENDS ${gen_header}) endif() + + zephyr_library_add_dependencies(gen_bindesc_build_time) endif() if(CONFIG_BINDESC_DEFINE_VERSION) diff --git a/subsys/bindesc/Kconfig.build_time b/subsys/bindesc/Kconfig.build_time index f9917008852..f315c92f4c9 100644 --- a/subsys/bindesc/Kconfig.build_time +++ b/subsys/bindesc/Kconfig.build_time @@ -74,7 +74,6 @@ config BINDESC_BUILD_TIME_STRING The time of compilation as a string, such as "T17:43:14+0000" config BINDESC_BUILD_DATE_TIME_STRING_FORMAT - depends on BINDESC_BUILD_DATE_TIME_STRING string "Date-Time format" default "%Y-%m-%dT%H:%M:%S%z" help @@ -89,7 +88,6 @@ config BINDESC_BUILD_DATE_TIME_STRING_FORMAT Note: the default format complies with ISO-8601. config BINDESC_BUILD_DATE_STRING_FORMAT - depends on BINDESC_BUILD_DATE_STRING string "Date format" default "%Y-%m-%d" help @@ -102,7 +100,6 @@ config BINDESC_BUILD_DATE_STRING_FORMAT Note: the default format complies with ISO-8601. config BINDESC_BUILD_TIME_STRING_FORMAT - depends on BINDESC_BUILD_TIME_STRING string "Time format" default "T%H:%M:%S%z" help diff --git a/subsys/bindesc/bindesc_build_time.c b/subsys/bindesc/bindesc_build_time.c index c741ce0ffd8..fde98c0f005 100644 --- a/subsys/bindesc/bindesc_build_time.c +++ b/subsys/bindesc/bindesc_build_time.c @@ -7,6 +7,9 @@ #include #include +/* Include generated header */ +#include + #if IS_ENABLED(CONFIG_BINDESC_BUILD_TIME_YEAR) BINDESC_UINT_DEFINE(build_time_year, BINDESC_ID_BUILD_TIME_YEAR, BUILD_TIME_YEAR); #endif /* IS_ENABLED(CONFIG_BINDESC_BUILD_TIME_YEAR) */ diff --git a/subsys/bindesc/bindesc_build_time.h.in b/subsys/bindesc/bindesc_build_time.h.in new file mode 100644 index 00000000000..5ae2ad2e170 --- /dev/null +++ b/subsys/bindesc/bindesc_build_time.h.in @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#ifndef _BINDESC_BUILD_TIME_H_ +#define _BINDESC_BUILD_TIME_H_ + +#define BUILD_TIME_YEAR @BUILD_TIME_YEAR@ +#define BUILD_TIME_MONTH @BUILD_TIME_MONTH@ +#define BUILD_TIME_DAY @BUILD_TIME_DAY@ +#define BUILD_TIME_HOUR @BUILD_TIME_HOUR@ +#define BUILD_TIME_MINUTE @BUILD_TIME_MINUTE@ +#define BUILD_TIME_SECOND @BUILD_TIME_SECOND@ +#define BUILD_TIME_UNIX @BUILD_TIME_UNIX@ + +#define BUILD_DATE_TIME_STRING "@BUILD_DATE_TIME_STRING@" +#define BUILD_DATE_STRING "@BUILD_DATE_STRING@" +#define BUILD_TIME_STRING "@BUILD_TIME_STRING@" + +#endif /* _BINDESC_BUILD_TIME_H_ */ diff --git a/subsys/bindesc/gen_bindesc_build_time_h.cmake b/subsys/bindesc/gen_bindesc_build_time_h.cmake new file mode 100644 index 00000000000..7d1b0db0e28 --- /dev/null +++ b/subsys/bindesc/gen_bindesc_build_time_h.cmake @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +# Wrapper macro around string(TIMESTAMP ...), that returns the time +# in either local time or UTC, depending on CONFIG_BINDESC_BUILD_TIME_USE_LOCAL_TIME. +macro(get_time out_var format) + if(BUILD_TIME_TYPE STREQUAL LOCAL) + string(TIMESTAMP ${out_var} ${format}) + else() + string(TIMESTAMP ${out_var} ${format} UTC) + endif() +endmacro() + +macro(gen_build_time_int_definition def_name format) + get_time(${def_name} ${format}) + # remove leading zeros so that the output will not be interpreted as octal + math(EXPR ${def_name} ${${def_name}}) +endmacro() + +macro(gen_build_time_str_definition def_name format) + get_time(${def_name} ${${format}}) +endmacro() + +gen_build_time_int_definition(BUILD_TIME_YEAR "%Y") +gen_build_time_int_definition(BUILD_TIME_MONTH "%m") +gen_build_time_int_definition(BUILD_TIME_DAY "%d") +gen_build_time_int_definition(BUILD_TIME_HOUR "%H") +gen_build_time_int_definition(BUILD_TIME_MINUTE "%M") +gen_build_time_int_definition(BUILD_TIME_SECOND "%S") +gen_build_time_int_definition(BUILD_TIME_UNIX "%s") + +gen_build_time_str_definition(BUILD_DATE_TIME_STRING BUILD_DATE_TIME_STRING_FORMAT) +gen_build_time_str_definition(BUILD_DATE_STRING BUILD_DATE_STRING_FORMAT) +gen_build_time_str_definition(BUILD_TIME_STRING BUILD_TIME_STRING_FORMAT) + +file(READ ${IN_FILE} content) +string(CONFIGURE "${content}" content) +file(WRITE ${OUT_FILE} "${content}") From d83c63eccebdfcc1dae856102ebb125110d3c010 Mon Sep 17 00:00:00 2001 From: Marco Widmer Date: Wed, 27 Mar 2024 15:19:39 +0100 Subject: [PATCH 1652/2402] pm: runtime: fix race when waiting for suspended event To wait for the asynchronous suspending work item to complete, a combination of semaphores and events is used. First, the semaphore is released, then the events are cleared (through the boolean argument to k_event_wait), then events are awaited. However, if the event flag happens to be set by the work handler in the short time between k_sem_give and k_event_wait, it is then cleared by k_event_wait and k_event_wait blocks forever waiting for the event. Make sure that we clear the event flag before releasing the semaphore. Signed-off-by: Marco Widmer --- subsys/pm/device_runtime.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/subsys/pm/device_runtime.c b/subsys/pm/device_runtime.c index 8ad738cd2dc..8a35e24ca94 100644 --- a/subsys/pm/device_runtime.c +++ b/subsys/pm/device_runtime.c @@ -242,9 +242,10 @@ int pm_device_runtime_get(const struct device *dev) * nothing else we can do but wait until it finishes. */ while (pm->base.state == PM_DEVICE_STATE_SUSPENDING) { + k_event_clear(&pm->event, EVENT_MASK); k_sem_give(&pm->lock); - k_event_wait(&pm->event, EVENT_MASK, true, K_FOREVER); + k_event_wait(&pm->event, EVENT_MASK, false, K_FOREVER); (void)k_sem_take(&pm->lock, K_FOREVER); } @@ -520,9 +521,10 @@ int pm_device_runtime_disable(const struct device *dev) /* wait until possible async suspend is completed */ while (pm->base.state == PM_DEVICE_STATE_SUSPENDING) { + k_event_clear(&pm->event, EVENT_MASK); k_sem_give(&pm->lock); - k_event_wait(&pm->event, EVENT_MASK, true, K_FOREVER); + k_event_wait(&pm->event, EVENT_MASK, false, K_FOREVER); (void)k_sem_take(&pm->lock, K_FOREVER); } From f87143d9198a326da5d6cbc58290d24cd4546fec Mon Sep 17 00:00:00 2001 From: Boris Mulder Date: Thu, 1 Feb 2024 14:47:18 +0100 Subject: [PATCH 1653/2402] drivers: sensor: tmp108: Handle negative values correctly Negative temperatures were converted to the sensor_value struct incorrectly. This fixes the causes: signed/unsigned mixups and integer overflows. Also clarified temperature calculation using multiplier/divisor config values. Fixes #68240 Signed-off-by: Boris Mulder --- drivers/sensor/tmp108/tmp108.c | 10 +++++----- drivers/sensor/tmp108/tmp108.h | 12 ++++++++---- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/sensor/tmp108/tmp108.c b/drivers/sensor/tmp108/tmp108.c index 79f31a305ab..70dc1e8b5bd 100644 --- a/drivers/sensor/tmp108/tmp108.c +++ b/drivers/sensor/tmp108/tmp108.c @@ -152,9 +152,9 @@ static int tmp108_channel_get(const struct device *dev, return -ENOTSUP; } - uval = ((int32_t)(drv_data->sample) * TMP108_TEMP_MULTIPLIER(dev)) >> 4U; - val->val1 = uval / 1000000U; - val->val2 = uval % 1000000U; + uval = ((int32_t)drv_data->sample * TMP108_TEMP_MULTIPLIER(dev)) / TMP108_TEMP_DIVISOR(dev); + val->val1 = uval / 1000000; + val->val2 = uval % 1000000; return 0; } @@ -237,7 +237,7 @@ static int tmp108_attr_set(const struct device *dev, case SENSOR_ATTR_LOWER_THRESH: uval = val->val1 * 1000000 + val->val2; - reg_value = (uval << 4U) / TMP108_TEMP_MULTIPLIER(dev); + reg_value = (uval * TMP108_TEMP_DIVISOR(dev)) / TMP108_TEMP_MULTIPLIER(dev); result = tmp108_reg_write(dev, TI_TMP108_REG_LOW_LIMIT, reg_value); @@ -245,7 +245,7 @@ static int tmp108_attr_set(const struct device *dev, case SENSOR_ATTR_UPPER_THRESH: uval = val->val1 * 1000000 + val->val2; - reg_value = (uval << 4U) / TMP108_TEMP_MULTIPLIER(dev); + reg_value = (uval * TMP108_TEMP_DIVISOR(dev)) / TMP108_TEMP_MULTIPLIER(dev); result = tmp108_reg_write(dev, TI_TMP108_REG_HIGH_LIMIT, reg_value); diff --git a/drivers/sensor/tmp108/tmp108.h b/drivers/sensor/tmp108/tmp108.h index cb4137a01d1..44dc2d11936 100644 --- a/drivers/sensor/tmp108/tmp108.h +++ b/drivers/sensor/tmp108/tmp108.h @@ -29,7 +29,8 @@ .CONF_POL = 0x0400, \ .CONF_M0 = 0x8000, \ .CONF_RST = 0x0080, \ - .TEMP_MULT = 125000, \ + .TEMP_MULT = 15625, \ + .TEMP_DIV = 2, \ .WAKEUP_TIME_IN_MS = 120 } #define TI_TMP108_CONF {.CONF_HYS0 = 0x0010, \ @@ -41,7 +42,8 @@ .CONF_CR0 = 0x2000, \ .CONF_CR1 = 0x4000, \ .CONF_RST = 0x0022, \ - .TEMP_MULT = 62500, \ + .TEMP_MULT = 15625, \ + .TEMP_DIV = 4, \ .WAKEUP_TIME_IN_MS = 30 } #define TI_TMP108_MODE_SHUTDOWN(x) 0 @@ -77,6 +79,7 @@ #define TI_TMP108_CONF_M0(x) TI_TMP108_GET_CONF(x, CONF_M0) #define TMP108_TEMP_MULTIPLIER(x) TI_TMP108_GET_CONF(x, TEMP_MULT) +#define TMP108_TEMP_DIVISOR(x) TI_TMP108_GET_CONF(x, TEMP_DIV) #define TMP108_WAKEUP_TIME_IN_MS(x) TI_TMP108_GET_CONF(x, WAKEUP_TIME_IN_MS) #define TMP108_CONF_RST(x) TI_TMP108_GET_CONF(x, CONF_RST) @@ -91,7 +94,8 @@ struct tmp_108_reg_def { uint16_t CONF_TM; /** Thermostat mode setting bit */ uint16_t CONF_HYS1; /** Temperature hysteresis config 1 bit */ uint16_t CONF_HYS0; /** Temperature hysteresis config 2 bit */ - uint32_t TEMP_MULT; /** Temperature multiplier */ + int32_t TEMP_MULT; /** Temperature multiplier */ + int32_t TEMP_DIV; /** Temperature divisor */ uint16_t WAKEUP_TIME_IN_MS; /** Wake up and conversion time from one shot */ uint16_t CONF_RST; /** default reset values on init */ }; @@ -107,7 +111,7 @@ struct tmp108_config { struct tmp108_data { const struct device *tmp108_dev; - uint16_t sample; + int16_t sample; bool one_shot_mode; From 566b4900cef441c91da10b0490cca808ba3dcf6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Fri, 29 Mar 2024 14:38:05 +0100 Subject: [PATCH 1654/2402] doc: api: fix broken links to API overview MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix incorrectly formatted sphinx links Signed-off-by: Benjamin Cabé --- doc/develop/api/api_lifecycle.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/doc/develop/api/api_lifecycle.rst b/doc/develop/api/api_lifecycle.rst index 9b17163caca..112c9d3722e 100644 --- a/doc/develop/api/api_lifecycle.rst +++ b/doc/develop/api/api_lifecycle.rst @@ -41,7 +41,7 @@ The following requirements apply to all new APIs: When introducing a new and experimental API, mark the API version in the headers where the API is defined. An experimental API shall have a version where the minor -version is up to one (0.1.z). (see `api overview `) +version is up to one (0.1.z). (see :ref:`api_overview`) Peripheral APIs (Hardware Related) ================================== @@ -64,7 +64,7 @@ be used on different hardware platforms. When the API changes status to unstable API, mark the API version in the headers where the API is defined. Unstable APIs shall have a version where the minor -version is larger than one (0.y.z | y > 1 ). (see `api overview `) +version is larger than one (0.y.z | y > 1 ). (see :ref:`api_overview`) .. note:: @@ -112,7 +112,7 @@ In order to declare an API ``stable``, the following steps need to be followed: When the API changes status to stable API, mark the API version in the headers where the API is defined. Stable APIs shall have a version where the major -version is one or larger (x.y.z | x >= 1 ). (see `api overview `) +version is one or larger (x.y.z | x >= 1 ). (see :ref:`api_overview`) .. _breaking_api_changes: @@ -200,7 +200,7 @@ If the Pull Request is merged then an email must be sent to the ``devel`` and The API version shall be changed to signal backward incompatible changes. This is achieved by incrementing the major version (X.y.z | X > 1). It MAY also include minor and patch level changes. Patch and minor versions MUST be reset to -0 when major version is incremented. (see `api overview `) +0 when major version is incremented. (see :ref:`api_overview`) .. note:: From f2d1851c2b5ecadf8fde4ba02e8cb1364e6a9fe8 Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 29 Mar 2024 09:08:28 -0400 Subject: [PATCH 1655/2402] tests: thrift: build_only until c++11 threads are in sdk There was a make-shift mutex implementation added to thrift while waiting for C++11 thread support in the SDK. This was fairly racey and would cause issues in CI regularly. Make the tests build-only for now until C++11 thread, mutex, etc support is stabilized. Signed-off-by: Chris Friedt --- tests/modules/thrift/ThriftTest/testcase.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/modules/thrift/ThriftTest/testcase.yaml b/tests/modules/thrift/ThriftTest/testcase.yaml index 760b2a6fae6..9933f2e3a38 100644 --- a/tests/modules/thrift/ThriftTest/testcase.yaml +++ b/tests/modules/thrift/ThriftTest/testcase.yaml @@ -1,4 +1,5 @@ common: + build_only: true tags: - thrift - cpp From 8e2722e1cae6d7a2c65d26d4393e1bcf6550cd40 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Wed, 27 Mar 2024 16:15:13 +0100 Subject: [PATCH 1656/2402] net: Provide separate configs for TX/RX memory pool for variable bufs Instead of having a single config specifying the memory pool size for variable-sized net buffers, have a separate one for TX and RX for better configuration granularity when optimizing memory usage of the application. Deprecate the old configuration but use its value as a default (for now) for the new configs. This will need to change when the config is deleted. Signed-off-by: Robert Lubos --- .../networking/net_config_guide.rst | 4 ++-- subsys/net/ip/Kconfig | 20 +++++++++++++++++-- subsys/net/ip/net_pkt.c | 4 ++-- subsys/net/ip/tcp.c | 4 ++-- subsys/net/lib/capture/capture.c | 4 +++- subsys/net/lib/shell/mem.c | 3 ++- tests/drivers/build_all/ethernet/prj.conf | 3 ++- tests/net/6lo/testcase.yaml | 3 ++- tests/net/all/prj.conf | 3 ++- tests/net/ipv6/testcase.yaml | 3 ++- tests/net/tcp/testcase.yaml | 3 ++- 11 files changed, 39 insertions(+), 15 deletions(-) diff --git a/doc/connectivity/networking/net_config_guide.rst b/doc/connectivity/networking/net_config_guide.rst index b8341744979..177ff434e8a 100644 --- a/doc/connectivity/networking/net_config_guide.rst +++ b/doc/connectivity/networking/net_config_guide.rst @@ -35,8 +35,8 @@ are able to either send or receive at the same time. When data is received from the network, it is placed into net_buf data portion. Depending on device resources and desired network usage, user can tweak the size of the fixed buffer by setting :kconfig:option:`CONFIG_NET_BUF_DATA_SIZE`, and - the size of the data pool size by setting :kconfig:option:`CONFIG_NET_BUF_DATA_POOL_SIZE` - if variable size buffers are used. + the size of the data pool size by setting :kconfig:option:`CONFIG_NET_PKT_BUF_RX_DATA_POOL_SIZE` + and :kconfig:option:`CONFIG_NET_PKT_BUF_TX_DATA_POOL_SIZE` if variable size buffers are used. When using the fixed size data buffers, the memory consumption of network buffers can be tweaked by selecting the size of the data part according to what kind of network diff --git a/subsys/net/ip/Kconfig b/subsys/net/ip/Kconfig index 4de15ada6d9..bc5442d44ba 100644 --- a/subsys/net/ip/Kconfig +++ b/subsys/net/ip/Kconfig @@ -668,12 +668,28 @@ config NET_BUF_DATA_SIZE This value tells what is the fixed size of each network buffer. config NET_BUF_DATA_POOL_SIZE - int "Size of the memory pool where buffers are allocated from" + int "[DEPRECATED] Size of the memory pool where buffers are allocated from" default 4096 if NET_L2_ETHERNET default 2048 depends on NET_BUF_VARIABLE_DATA_SIZE help - This value tell what is the size of the memory pool where each + This config is deprecated, use NET_PKT_BUF_RX_DATA_POOL_SIZE and + NET_PKT_BUF_TX_DATA_POOL_SIZE instead. + +config NET_PKT_BUF_RX_DATA_POOL_SIZE + int "Size of the RX memory pool where buffers are allocated from" + default NET_BUF_DATA_POOL_SIZE + depends on NET_BUF_VARIABLE_DATA_SIZE + help + This value tell what is the size of the RX memory pool where each + network buffer is allocated from. + +config NET_PKT_BUF_TX_DATA_POOL_SIZE + int "Size of the TX memory pool where buffers are allocated from" + default NET_BUF_DATA_POOL_SIZE + depends on NET_BUF_VARIABLE_DATA_SIZE + help + This value tell what is the size of the TX memory pool where each network buffer is allocated from. config NET_PKT_BUF_USER_DATA_SIZE diff --git a/subsys/net/ip/net_pkt.c b/subsys/net/ip/net_pkt.c index d7556a5023d..81d9d35b736 100644 --- a/subsys/net/ip/net_pkt.c +++ b/subsys/net/ip/net_pkt.c @@ -129,9 +129,9 @@ NET_BUF_POOL_FIXED_DEFINE(tx_bufs, CONFIG_NET_BUF_TX_COUNT, CONFIG_NET_BUF_DATA_ #else /* !CONFIG_NET_BUF_FIXED_DATA_SIZE */ -NET_BUF_POOL_VAR_DEFINE(rx_bufs, CONFIG_NET_BUF_RX_COUNT, CONFIG_NET_BUF_DATA_POOL_SIZE, +NET_BUF_POOL_VAR_DEFINE(rx_bufs, CONFIG_NET_BUF_RX_COUNT, CONFIG_NET_PKT_BUF_RX_DATA_POOL_SIZE, CONFIG_NET_PKT_BUF_USER_DATA_SIZE, NULL); -NET_BUF_POOL_VAR_DEFINE(tx_bufs, CONFIG_NET_BUF_TX_COUNT, CONFIG_NET_BUF_DATA_POOL_SIZE, +NET_BUF_POOL_VAR_DEFINE(tx_bufs, CONFIG_NET_BUF_TX_COUNT, CONFIG_NET_PKT_BUF_TX_DATA_POOL_SIZE, CONFIG_NET_PKT_BUF_USER_DATA_SIZE, NULL); #endif /* CONFIG_NET_BUF_FIXED_DATA_SIZE */ diff --git a/subsys/net/ip/tcp.c b/subsys/net/ip/tcp.c index 6636b3d3032..49ad112b527 100644 --- a/subsys/net/ip/tcp.c +++ b/subsys/net/ip/tcp.c @@ -45,7 +45,7 @@ static int tcp_rx_window = #if defined(CONFIG_NET_BUF_FIXED_DATA_SIZE) (CONFIG_NET_BUF_RX_COUNT * CONFIG_NET_BUF_DATA_SIZE) / 3; #else - CONFIG_NET_BUF_DATA_POOL_SIZE / 3; + CONFIG_NET_PKT_BUF_RX_DATA_POOL_SIZE / 3; #endif /* CONFIG_NET_BUF_FIXED_DATA_SIZE */ #endif static int tcp_tx_window = @@ -55,7 +55,7 @@ static int tcp_tx_window = #if defined(CONFIG_NET_BUF_FIXED_DATA_SIZE) (CONFIG_NET_BUF_TX_COUNT * CONFIG_NET_BUF_DATA_SIZE) / 3; #else - CONFIG_NET_BUF_DATA_POOL_SIZE / 3; + CONFIG_NET_PKT_BUF_TX_DATA_POOL_SIZE / 3; #endif /* CONFIG_NET_BUF_FIXED_DATA_SIZE */ #endif #ifdef CONFIG_NET_TCP_RANDOMIZED_RTO diff --git a/subsys/net/lib/capture/capture.c b/subsys/net/lib/capture/capture.c index 27114ca7e67..fcd7bb06773 100644 --- a/subsys/net/lib/capture/capture.c +++ b/subsys/net/lib/capture/capture.c @@ -41,8 +41,10 @@ NET_PKT_SLAB_DEFINE(capture_pkts, CONFIG_NET_CAPTURE_PKT_COUNT); NET_BUF_POOL_FIXED_DEFINE(capture_bufs, CONFIG_NET_CAPTURE_BUF_COUNT, CONFIG_NET_BUF_DATA_SIZE, 4, NULL); #else +#define DATA_POOL_SIZE MAX(NET_PKT_BUF_RX_DATA_POOL_SIZE, NET_PKT_BUF_TX_DATA_POOL_SIZE) + NET_BUF_POOL_VAR_DEFINE(capture_bufs, CONFIG_NET_CAPTURE_BUF_COUNT, - CONFIG_NET_BUF_DATA_POOL_SIZE, 4, NULL); + DATA_POOL_SIZE, 4, NULL); #endif static sys_slist_t net_capture_devlist; diff --git a/subsys/net/lib/shell/mem.c b/subsys/net/lib/shell/mem.c index 47058f92767..7bbe0b5e214 100644 --- a/subsys/net/lib/shell/mem.c +++ b/subsys/net/lib/shell/mem.c @@ -107,7 +107,8 @@ static int cmd_net_mem(const struct shell *sh, size_t argc, char *argv[]) #if defined(CONFIG_NET_BUF_FIXED_DATA_SIZE) PR("Fragment length %d bytes\n", CONFIG_NET_BUF_DATA_SIZE); #else - PR("Fragment data pool size %d bytes\n", CONFIG_NET_BUF_DATA_POOL_SIZE); + PR("Fragment RX data pool size %d bytes\n", CONFIG_NET_PKT_BUF_RX_DATA_POOL_SIZE); + PR("Fragment TX data pool size %d bytes\n", CONFIG_NET_PKT_BUF_TX_DATA_POOL_SIZE); #endif /* CONFIG_NET_BUF_FIXED_DATA_SIZE */ PR("Network buffer pools:\n"); diff --git a/tests/drivers/build_all/ethernet/prj.conf b/tests/drivers/build_all/ethernet/prj.conf index 208ed81da3c..938aa284a43 100644 --- a/tests/drivers/build_all/ethernet/prj.conf +++ b/tests/drivers/build_all/ethernet/prj.conf @@ -11,7 +11,8 @@ CONFIG_NET_PKT_RX_COUNT=14 CONFIG_NET_PKT_TX_COUNT=14 CONFIG_NET_BUF_RX_COUNT=36 CONFIG_NET_BUF_TX_COUNT=36 -CONFIG_NET_BUF_DATA_POOL_SIZE=4096 +CONFIG_NET_PKT_BUF_RX_DATA_POOL_SIZE=4096 +CONFIG_NET_PKT_BUF_TX_DATA_POOL_SIZE=4096 # Disable L2 CONFIG_NET_L2_ETHERNET=n diff --git a/tests/net/6lo/testcase.yaml b/tests/net/6lo/testcase.yaml index 5d3b13b945d..a6a1294f6d9 100644 --- a/tests/net/6lo/testcase.yaml +++ b/tests/net/6lo/testcase.yaml @@ -14,4 +14,5 @@ tests: net.6lo.variable_buf_size: extra_configs: - CONFIG_NET_BUF_VARIABLE_DATA_SIZE=y - - CONFIG_NET_BUF_DATA_POOL_SIZE=4096 + - CONFIG_NET_PKT_BUF_RX_DATA_POOL_SIZE=4096 + - CONFIG_NET_PKT_BUF_TX_DATA_POOL_SIZE=4096 diff --git a/tests/net/all/prj.conf b/tests/net/all/prj.conf index 8eb3c445c79..dfdb46eeaf6 100644 --- a/tests/net/all/prj.conf +++ b/tests/net/all/prj.conf @@ -25,7 +25,8 @@ CONFIG_NET_BUF_LOG_LEVEL_DBG=y CONFIG_NET_BUF_WARN_ALLOC_INTERVAL=2 CONFIG_NET_BUF_SIMPLE_LOG=y CONFIG_NET_BUF_POOL_USAGE=y -#CONFIG_NET_BUF_DATA_POOL_SIZE=4096 +#CONFIG_NET_PKT_BUF_RX_DATA_POOL_SIZE=4096 +#CONFIG_NET_PKT_BUF_TX_DATA_POOL_SIZE=4096 CONFIG_NET_BUF_FIXED_DATA_SIZE=y CONFIG_NET_BUF_VARIABLE_DATA_SIZE=n CONFIG_NET_PKT_RX_COUNT=10 diff --git a/tests/net/ipv6/testcase.yaml b/tests/net/ipv6/testcase.yaml index 48abbd37ab0..1fbe64f067a 100644 --- a/tests/net/ipv6/testcase.yaml +++ b/tests/net/ipv6/testcase.yaml @@ -10,4 +10,5 @@ tests: net.ipv6.variable_buf_size: extra_configs: - CONFIG_NET_BUF_VARIABLE_DATA_SIZE=y - - CONFIG_NET_BUF_DATA_POOL_SIZE=4096 + - CONFIG_NET_PKT_BUF_RX_DATA_POOL_SIZE=4096 + - CONFIG_NET_PKT_BUF_TX_DATA_POOL_SIZE=4096 diff --git a/tests/net/tcp/testcase.yaml b/tests/net/tcp/testcase.yaml index a60128f049c..7f4a509553a 100644 --- a/tests/net/tcp/testcase.yaml +++ b/tests/net/tcp/testcase.yaml @@ -13,4 +13,5 @@ tests: net.tcp.variable_buf_size: extra_configs: - CONFIG_NET_BUF_VARIABLE_DATA_SIZE=y - - CONFIG_NET_BUF_DATA_POOL_SIZE=4096 + - CONFIG_NET_PKT_BUF_RX_DATA_POOL_SIZE=4096 + - CONFIG_NET_PKT_BUF_TX_DATA_POOL_SIZE=4096 From e8d4a68f8e6e3452a94d1ea016f8d6d50ff54b47 Mon Sep 17 00:00:00 2001 From: Piotr Narajowski Date: Wed, 27 Mar 2024 11:39:36 +0100 Subject: [PATCH 1657/2402] bluetooth: tester: Add CSIS btp command This commit adds CSIS command to change type of SIRK. This is needed for CSIS/SR/SP/BV-05-C test case. Signed-off-by: Piotr Narajowski --- tests/bluetooth/tester/overlay-le-audio.conf | 1 + tests/bluetooth/tester/src/btp/btp_csis.h | 5 +++ tests/bluetooth/tester/src/btp_csis.c | 41 +++++++++++++++++++- 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/tests/bluetooth/tester/overlay-le-audio.conf b/tests/bluetooth/tester/overlay-le-audio.conf index 12a237a720f..ba1b6a4e55e 100644 --- a/tests/bluetooth/tester/overlay-le-audio.conf +++ b/tests/bluetooth/tester/overlay-le-audio.conf @@ -100,6 +100,7 @@ CONFIG_BT_HAS_CLIENT=y # CSIS CONFIG_BT_CSIP_SET_MEMBER=y +CONFIG_BT_CSIP_SET_MEMBER_ENC_SIRK_SUPPORT=y # CSIP CONFIG_BT_CSIP_SET_COORDINATOR=y diff --git a/tests/bluetooth/tester/src/btp/btp_csis.h b/tests/bluetooth/tester/src/btp/btp_csis.h index 3c155acb6d5..1a9d34221a3 100644 --- a/tests/bluetooth/tester/src/btp/btp_csis.h +++ b/tests/bluetooth/tester/src/btp/btp_csis.h @@ -28,3 +28,8 @@ struct btp_csis_get_member_rsi_cmd { struct btp_csis_get_member_rsi_rp { uint8_t rsi[BT_CSIP_RSI_SIZE]; } __packed; + +#define BTP_CSIS_ENC_SIRK_TYPE 0x04 +struct btp_csis_set_sirk_type_cmd { + uint8_t encrypted; +} __packed; diff --git a/tests/bluetooth/tester/src/btp_csis.c b/tests/bluetooth/tester/src/btp_csis.c index 08e9b05723f..f0d14f114f5 100644 --- a/tests/bluetooth/tester/src/btp_csis.c +++ b/tests/bluetooth/tester/src/btp_csis.c @@ -17,6 +17,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL); #define BTP_STATUS_VAL(err) (err) ? BTP_STATUS_FAILED : BTP_STATUS_SUCCESS static struct bt_csip_set_member_svc_inst *csis_svc_inst; +static bool enc_sirk; static uint8_t csis_supported_commands(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) @@ -27,6 +28,7 @@ static uint8_t csis_supported_commands(const void *cmd, uint16_t cmd_len, tester_set_bit(rp->data, BTP_CSIS_READ_SUPPORTED_COMMANDS); tester_set_bit(rp->data, BTP_CSIS_SET_MEMBER_LOCK); tester_set_bit(rp->data, BTP_CSIS_GET_MEMBER_RSI); + tester_set_bit(rp->data, BTP_CSIS_ENC_SIRK_TYPE); *rsp_len = sizeof(*rp) + 1; @@ -61,6 +63,18 @@ static uint8_t csis_get_member_rsi(const void *cmd, uint16_t cmd_len, return BTP_STATUS_VAL(err); } +static uint8_t csis_set_sirk_type(const void *cmd, uint16_t cmd_len, void *rsp, + uint16_t *rsp_len) +{ + const struct btp_csis_set_sirk_type_cmd *cp = cmd; + + enc_sirk = cp->encrypted != 0U; + + LOG_DBG("Set SIRK type: %s", enc_sirk ? "encrypted" : "plain text"); + + return BTP_STATUS_SUCCESS; +} + static const struct btp_handler csis_handlers[] = { { .opcode = BTP_CSIS_READ_SUPPORTED_COMMANDS, @@ -77,7 +91,32 @@ static const struct btp_handler csis_handlers[] = { .opcode = BTP_CSIS_GET_MEMBER_RSI, .expect_len = sizeof(struct btp_csis_get_member_rsi_cmd), .func = csis_get_member_rsi + }, + { + .opcode = BTP_CSIS_ENC_SIRK_TYPE, + .expect_len = sizeof(struct btp_csis_set_sirk_type_cmd), + .func = csis_set_sirk_type, + }, +}; + +static void lock_changed_cb(struct bt_conn *conn, struct bt_csip_set_member_svc_inst *svc_inst, + bool locked) +{ + LOG_DBG("%s", locked ? "locked" : "unlocked"); +} + +static uint8_t sirk_read_cb(struct bt_conn *conn, struct bt_csip_set_member_svc_inst *svc_inst) +{ + if (enc_sirk) { + return BT_CSIP_READ_SIRK_REQ_RSP_ACCEPT_ENC; + } else { + return BT_CSIP_READ_SIRK_REQ_RSP_ACCEPT; } +} + +static struct bt_csip_set_member_cb csis_cb = { + .lock_changed = lock_changed_cb, + .sirk_read_req = sirk_read_cb, }; uint8_t tester_init_csis(void) @@ -88,7 +127,7 @@ uint8_t tester_init_csis(void) 0x5A, 0x41, 0xF1, 0x53, 0x05, 0x68, 0x8E, 0x83 }, .lockable = true, .rank = 1, - .cb = NULL + .cb = &csis_cb, }; int err = bt_csip_set_member_register(®ister_params, &csis_svc_inst); From 2759a35a1811b10079cd3dc6f20ea9e9c9dab916 Mon Sep 17 00:00:00 2001 From: Ryan Chu Date: Mon, 25 Mar 2024 15:00:42 +0100 Subject: [PATCH 1658/2402] Samples: Bluetooth: Fix PAwR sample failed to set subevent data Be respectful of PAwR subevents while scheduling scan activities. The radio will be swtiched from scan to PAwR when it is closed to the next subevent interval. Signed-off-by: Ryan Chu --- samples/bluetooth/periodic_adv_rsp/src/main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/samples/bluetooth/periodic_adv_rsp/src/main.c b/samples/bluetooth/periodic_adv_rsp/src/main.c index 0b0db776692..6764b023a5a 100644 --- a/samples/bluetooth/periodic_adv_rsp/src/main.c +++ b/samples/bluetooth/periodic_adv_rsp/src/main.c @@ -295,7 +295,8 @@ int main(void) } while (num_synced < MAX_SYNCS) { - err = bt_le_scan_start(BT_LE_SCAN_PASSIVE, device_found); + /* Enable continuous scanning */ + err = bt_le_scan_start(BT_LE_SCAN_PASSIVE_CONTINUOUS, device_found); if (err) { printk("Scanning failed to start (err %d)\n", err); return 0; From da676d2e011bd88b46e1de65dab46022c8d737df Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Wed, 20 Mar 2024 22:16:18 +0100 Subject: [PATCH 1659/2402] net: buf: Include user data when cloning net_buf_user_data() is supposed to copy any data, which includes the user data. Signed-off-by: Reto Schneider --- include/zephyr/net/buf.h | 2 +- subsys/net/buf.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/zephyr/net/buf.h b/include/zephyr/net/buf.h index 464dfc6ccd7..cf7e1279662 100644 --- a/include/zephyr/net/buf.h +++ b/include/zephyr/net/buf.h @@ -1536,7 +1536,7 @@ struct net_buf * __must_check net_buf_ref(struct net_buf *buf); /** * @brief Clone buffer * - * Duplicate given buffer including any data and headers currently stored. + * Duplicate given buffer including any (user) data and headers currently stored. * * @param buf A valid pointer on a buffer * @param timeout Affects the action taken should the pool be empty. diff --git a/subsys/net/buf.c b/subsys/net/buf.c index 9b04e243642..8f65c402806 100644 --- a/subsys/net/buf.c +++ b/subsys/net/buf.c @@ -539,6 +539,11 @@ struct net_buf *net_buf_clone(struct net_buf *buf, k_timeout_t timeout) net_buf_add_mem(clone, buf->data, buf->len); } + /* user_data_size should be the same for buffers from the same pool */ + __ASSERT(buf->user_data_size == clone->user_data_size, "Unexpected user data size"); + + memcpy(clone->user_data, buf->user_data, clone->user_data_size); + return clone; } From 3aba7d5bc627eddfd64fc3a15f1a4b45969d553a Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Mon, 25 Mar 2024 13:49:17 +0100 Subject: [PATCH 1660/2402] tests: net: buf: Better clone coverage This commit ensures that user data get copied when cloning a buffer. Signed-off-by: Reto Schneider --- tests/net/buf/src/main.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/tests/net/buf/src/main.c b/tests/net/buf/src/main.c index f211000dd12..1b010026062 100644 --- a/tests/net/buf/src/main.c +++ b/tests/net/buf/src/main.c @@ -464,6 +464,25 @@ ZTEST(net_buf_tests, test_net_buf_clone_reference_counted_zero_sized_buffer) zassert_not_null(clone, "Failed to clone zero sized buffer"); net_buf_unref(buf); +} + +ZTEST(net_buf_tests, test_net_buf_clone_user_data) +{ + struct net_buf *original, *clone; + uint32_t *buf_user_data, *clone_user_data; + + /* Requesting size 1 because all we are interested in are the user data */ + original = net_buf_alloc_len(&bufs_pool, 1, K_NO_WAIT); + zassert_not_null(original, "Failed to get buffer"); + buf_user_data = net_buf_user_data(original); + *buf_user_data = 0xAABBCCDD; + + clone = net_buf_clone(original, K_NO_WAIT); + zassert_not_null(clone, "Failed to get clone buffer"); + clone_user_data = net_buf_user_data(clone); + zexpect_equal(*clone_user_data, 0xAABBCCDD, "User data copy is invalid"); + + net_buf_unref(original); net_buf_unref(clone); } From 688fbb53aeb25c6160b1d6030d1b1403d3b2e81a Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Wed, 27 Mar 2024 14:29:46 -0700 Subject: [PATCH 1661/2402] intel_adsp: ace: Fix sparse error Fixes the following errors when sparse (SCA) is enabled: soc/intel/intel_adsp/ace/power.c:46:12: warning: cast removes address space '__cache' of expression /soc/intel/intel_adsp/ace/power.c:48:9: warning: incorrect type in argument 1 (different address spaces) Fixes #70725 Signed-off-by: Flavio Ceolin --- soc/intel/intel_adsp/ace/power.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/soc/intel/intel_adsp/ace/power.c b/soc/intel/intel_adsp/ace/power.c index e94e1b0f17c..ef11a66c6ea 100644 --- a/soc/intel/intel_adsp/ace/power.c +++ b/soc/intel/intel_adsp/ace/power.c @@ -43,9 +43,10 @@ __imr void power_init(void) #endif /* CONFIG_ADSP_IDLE_CLOCK_GATING */ #if CONFIG_SOC_INTEL_ACE15_MTPM - *((uint32_t *)sys_cache_cached_ptr_get(&adsp_pending_buffer)) = + *((__sparse_force uint32_t *)sys_cache_cached_ptr_get(&adsp_pending_buffer)) = INTEL_ADSP_ACE15_MAGIC_KEY; - cache_data_flush_range(sys_cache_cached_ptr_get(&adsp_pending_buffer), + cache_data_flush_range((__sparse_force void *) + sys_cache_cached_ptr_get(&adsp_pending_buffer), sizeof(adsp_pending_buffer)); #endif /* CONFIG_SOC_INTEL_ACE15_MTPM */ } From 27cb75edb8f73f4ed5e8d917089c28a03e28c7b4 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 11 Mar 2024 10:46:44 -0500 Subject: [PATCH 1662/2402] samples: ipc: openamp_rsc_table: Check for endpoint create failure Check if creating the RPMSG endpoint fails and exit the task if so. This prevents a later null pointer dereference if we try to continue. Signed-off-by: Andrew Davis --- samples/subsys/ipc/openamp_rsc_table/src/main_remote.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c b/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c index 14a89f06e90..1614a6d273c 100644 --- a/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c +++ b/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c @@ -291,6 +291,10 @@ void app_rpmsg_client_sample(void *arg1, void *arg2, void *arg3) ret = rpmsg_create_ept(&sc_ept, rpdev, "rpmsg-client-sample", RPMSG_ADDR_ANY, RPMSG_ADDR_ANY, rpmsg_recv_cs_callback, NULL); + if (ret) { + LOG_ERR("[Linux sample client] Could not create endpoint: %d\n", ret); + goto task_end; + } while (msg_cnt < 100) { k_sem_take(&data_sc_sem, K_FOREVER); @@ -301,6 +305,7 @@ void app_rpmsg_client_sample(void *arg1, void *arg2, void *arg3) } rpmsg_destroy_ept(&sc_ept); +task_end: printk("OpenAMP Linux sample client responder ended\n"); } @@ -321,6 +326,10 @@ void app_rpmsg_tty(void *arg1, void *arg2, void *arg3) ret = rpmsg_create_ept(&tty_ept, rpdev, "rpmsg-tty", RPMSG_ADDR_ANY, RPMSG_ADDR_ANY, rpmsg_recv_tty_callback, NULL); + if (ret) { + LOG_ERR("[Linux TTY] Could not create endpoint: %d\n", ret); + goto task_end; + } while (tty_ept.addr != RPMSG_ADDR_ANY) { k_sem_take(&data_tty_sem, K_FOREVER); @@ -336,6 +345,7 @@ void app_rpmsg_tty(void *arg1, void *arg2, void *arg3) } rpmsg_destroy_ept(&tty_ept); +task_end: printk("OpenAMP Linux TTY responder ended\n"); } From 21275868eef528b12e24d6cfd9966d3ddc91f3d0 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 11 Mar 2024 10:56:50 -0500 Subject: [PATCH 1663/2402] samples: ipc: openamp_rsc_table: Normalize printed output Currently a mix of printk() and LOG_*() are used, switch to using the LOG functions in all cases. The code also has mixed line-ending types, as the LOG functions add newlines remove these. Also some messages that are failures are printed with debug log level, use ERR level here. Signed-off-by: Andrew Davis --- .../ipc/openamp_rsc_table/src/main_remote.c | 57 ++++++++++--------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c b/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c index 1614a6d273c..abd5977a638 100644 --- a/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c +++ b/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c @@ -93,7 +93,7 @@ static K_SEM_DEFINE(data_tty_sem, 0, 1); static void platform_ipm_callback(const struct device *dev, void *context, uint32_t id, volatile void *data) { - LOG_DBG("%s: msg received from mb %d\n", __func__, id); + LOG_DBG("%s: msg received from mb %d", __func__, id); k_sem_give(&data_sem); } @@ -132,7 +132,7 @@ static void receive_message(unsigned char **msg, unsigned int *len) static void new_service_cb(struct rpmsg_device *rdev, const char *name, uint32_t src) { - LOG_ERR("%s: unexpected ns service receive for name %s\n", + LOG_ERR("%s: unexpected ns service receive for name %s", __func__, name); } @@ -140,7 +140,7 @@ int mailbox_notify(void *priv, uint32_t id) { ARG_UNUSED(priv); - LOG_DBG("%s: msg received\n", __func__); + LOG_DBG("%s: msg received", __func__); ipm_send(ipm_handle, 0, id, NULL, 0); return 0; @@ -156,19 +156,19 @@ int platform_init(void) status = metal_init(&metal_params); if (status) { - LOG_DBG("metal_init: failed: %d\n", status); + LOG_ERR("metal_init: failed: %d", status); return -1; } status = metal_register_generic_device(&shm_device); if (status) { - LOG_DBG("Couldn't register shared memory: %d\n", status); + LOG_ERR("Couldn't register shared memory: %d\n", status); return -1; } status = metal_device_open("generic", SHM_DEVICE_NAME, &device); if (status) { - LOG_DBG("metal_device_open failed: %d\n", status); + LOG_ERR("metal_device_open failed: %d\n", status); return -1; } @@ -178,7 +178,7 @@ int platform_init(void) shm_io = metal_device_io_region(device, 0); if (!shm_io) { - LOG_DBG("Failed to get shm_io region\n"); + LOG_ERR("Failed to get shm_io region\n"); return -1; } @@ -191,13 +191,13 @@ int platform_init(void) rsc_io = metal_device_io_region(device, 1); if (!rsc_io) { - LOG_DBG("Failed to get rsc_io region\n"); + LOG_ERR("Failed to get rsc_io region\n"); return -1; } /* setup IPM */ if (!device_is_ready(ipm_handle)) { - LOG_DBG("IPM device is not ready\n"); + LOG_ERR("IPM device is not ready"); return -1; } @@ -205,7 +205,7 @@ int platform_init(void) status = ipm_set_enabled(ipm_handle, 1); if (status) { - LOG_DBG("ipm_set_enabled failed\n"); + LOG_ERR("ipm_set_enabled failed"); return -1; } @@ -234,7 +234,7 @@ platform_create_rpmsg_vdev(unsigned int vdev_index, rsc_io, NULL, mailbox_notify, NULL); if (!vdev) { - LOG_DBG("failed to create vdev\r\n"); + LOG_ERR("failed to create vdev"); return NULL; } @@ -246,7 +246,7 @@ platform_create_rpmsg_vdev(unsigned int vdev_index, (void *)vring_rsc->da, rsc_io, vring_rsc->num, vring_rsc->align); if (ret) { - LOG_DBG("failed to init vring 0\r\n"); + LOG_ERR("failed to init vring 0"); goto failed; } @@ -255,7 +255,7 @@ platform_create_rpmsg_vdev(unsigned int vdev_index, (void *)vring_rsc->da, rsc_io, vring_rsc->num, vring_rsc->align); if (ret) { - LOG_DBG("failed to init vring 1\r\n"); + LOG_ERR("failed to init vring 1"); goto failed; } @@ -263,7 +263,7 @@ platform_create_rpmsg_vdev(unsigned int vdev_index, ret = rpmsg_init_vdev(&rvdev, vdev, ns_cb, shm_io, &shpool); if (ret) { - LOG_DBG("failed rpmsg_init_vdev\r\n"); + LOG_ERR("failed rpmsg_init_vdev"); goto failed; } @@ -286,27 +286,27 @@ void app_rpmsg_client_sample(void *arg1, void *arg2, void *arg3) k_sem_take(&data_sc_sem, K_FOREVER); - printk("\r\nOpenAMP[remote] Linux sample client responder started\r\n"); + LOG_INF("OpenAMP[remote] Linux sample client responder started"); ret = rpmsg_create_ept(&sc_ept, rpdev, "rpmsg-client-sample", RPMSG_ADDR_ANY, RPMSG_ADDR_ANY, rpmsg_recv_cs_callback, NULL); if (ret) { - LOG_ERR("[Linux sample client] Could not create endpoint: %d\n", ret); + LOG_ERR("[Linux sample client] Could not create endpoint: %d", ret); goto task_end; } while (msg_cnt < 100) { k_sem_take(&data_sc_sem, K_FOREVER); msg_cnt++; - printk("[Linux sample client] incoming msg %d: %.*s\n", msg_cnt, sc_msg.len, - (char *)sc_msg.data); + LOG_INF("[Linux sample client] incoming msg %d: %.*s", msg_cnt, sc_msg.len, + (char *)sc_msg.data); rpmsg_send(&sc_ept, sc_msg.data, sc_msg.len); } rpmsg_destroy_ept(&sc_ept); task_end: - printk("OpenAMP Linux sample client responder ended\n"); + LOG_INF("OpenAMP Linux sample client responder ended"); } void app_rpmsg_tty(void *arg1, void *arg2, void *arg3) @@ -320,21 +320,22 @@ void app_rpmsg_tty(void *arg1, void *arg2, void *arg3) k_sem_take(&data_tty_sem, K_FOREVER); - printk("\r\nOpenAMP[remote] Linux TTY responder started\r\n"); + LOG_INF("OpenAMP[remote] Linux TTY responder started"); tty_ept.priv = &tty_msg; ret = rpmsg_create_ept(&tty_ept, rpdev, "rpmsg-tty", RPMSG_ADDR_ANY, RPMSG_ADDR_ANY, rpmsg_recv_tty_callback, NULL); if (ret) { - LOG_ERR("[Linux TTY] Could not create endpoint: %d\n", ret); + LOG_ERR("[Linux TTY] Could not create endpoint: %d", ret); goto task_end; } while (tty_ept.addr != RPMSG_ADDR_ANY) { k_sem_take(&data_tty_sem, K_FOREVER); if (tty_msg.len) { - printk("[Linux TTY] incoming msg: %.*s", tty_msg.len, (char *)tty_msg.data); + LOG_INF("[Linux TTY] incoming msg: %.*s", + tty_msg.len, (char *)tty_msg.data); snprintf(tx_buff, 13, "TTY 0x%04x: ", tty_ept.addr); memcpy(&tx_buff[12], tty_msg.data, tty_msg.len); rpmsg_send(&tty_ept, tx_buff, tty_msg.len + 12); @@ -346,7 +347,7 @@ void app_rpmsg_tty(void *arg1, void *arg2, void *arg3) rpmsg_destroy_ept(&tty_ept); task_end: - printk("OpenAMP Linux TTY responder ended\n"); + LOG_INF("OpenAMP Linux TTY responder ended"); } void rpmsg_mng_task(void *arg1, void *arg2, void *arg3) @@ -359,12 +360,12 @@ void rpmsg_mng_task(void *arg1, void *arg2, void *arg3) unsigned int len; int ret = 0; - printk("\r\nOpenAMP[remote] Linux responder demo started\r\n"); + LOG_INF("OpenAMP[remote] Linux responder demo started"); /* Initialize platform */ ret = platform_init(); if (ret) { - LOG_ERR("Failed to initialize platform\n"); + LOG_ERR("Failed to initialize platform"); ret = -1; goto task_end; } @@ -372,7 +373,7 @@ void rpmsg_mng_task(void *arg1, void *arg2, void *arg3) rpdev = platform_create_rpmsg_vdev(0, VIRTIO_DEV_DEVICE, NULL, new_service_cb); if (!rpdev) { - LOG_ERR("Failed to create rpmsg virtio device\n"); + LOG_ERR("Failed to create rpmsg virtio device"); ret = -1; goto task_end; } @@ -392,12 +393,12 @@ void rpmsg_mng_task(void *arg1, void *arg2, void *arg3) task_end: cleanup_system(); - printk("OpenAMP demo ended\n"); + LOG_INF("OpenAMP demo ended"); } int main(void) { - printk("Starting application threads!\n"); + LOG_INF("Starting application threads!"); k_thread_create(&thread_mng_data, thread_mng_stack, APP_TASK_STACK_SIZE, rpmsg_mng_task, NULL, NULL, NULL, K_PRIO_COOP(8), 0, K_NO_WAIT); From 993f97801dae7d580d7bbc1c2bfa0e1c257ae615 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 11 Mar 2024 11:09:21 -0500 Subject: [PATCH 1664/2402] samples: ipc: openamp_rsc_table: Do not create null shared memory pool We are always the remote client in this example. The shared pool is only used for allocating ring descriptors when we are the host. Do not create a shared pool with a NULL base address, simply do no pass in a pool. Signed-off-by: Andrew Davis --- samples/subsys/ipc/openamp_rsc_table/src/main_remote.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c b/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c index abd5977a638..6cc906c6a20 100644 --- a/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c +++ b/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c @@ -71,7 +71,6 @@ struct rpmsg_rcv_msg { }; static struct metal_io_region *shm_io; -static struct rpmsg_virtio_shm_pool shpool; static struct metal_io_region *rsc_io; static struct rpmsg_virtio_device rvdev; @@ -259,9 +258,7 @@ platform_create_rpmsg_vdev(unsigned int vdev_index, goto failed; } - rpmsg_virtio_init_shm_pool(&shpool, NULL, SHM_SIZE); - ret = rpmsg_init_vdev(&rvdev, vdev, ns_cb, shm_io, &shpool); - + ret = rpmsg_init_vdev(&rvdev, vdev, ns_cb, shm_io, NULL); if (ret) { LOG_ERR("failed rpmsg_init_vdev"); goto failed; From 0714052c74bfe4e74ae6fca705da4d7d66c92681 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 20 Mar 2024 14:48:31 -0500 Subject: [PATCH 1665/2402] samples: ipc: openamp_rsc_table: Remove virtual shared memory device A virtual metal_device is created and then the needed IO regions created and added to this device. Immediately we extract these regions back out and make use of them. There is no reason to do this, instead simply use the created IO regions. This also removes the need to have struct metal_device defined to have more than one IO region (METAL_MAX_DEVICE_REGIONS), which is not default. If the libmetal library was built with a different value, then updating this header would not fix the underlying implementation leading to runtime failures. Signed-off-by: Andrew Davis --- .../ipc/openamp_rsc_table/CMakeLists.txt | 6 --- .../ipc/openamp_rsc_table/src/main_remote.c | 49 +++---------------- 2 files changed, 8 insertions(+), 47 deletions(-) diff --git a/samples/subsys/ipc/openamp_rsc_table/CMakeLists.txt b/samples/subsys/ipc/openamp_rsc_table/CMakeLists.txt index 57640da8418..dd89bf77549 100644 --- a/samples/subsys/ipc/openamp_rsc_table/CMakeLists.txt +++ b/samples/subsys/ipc/openamp_rsc_table/CMakeLists.txt @@ -8,12 +8,6 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) project(openamp_rsc_table_remote) -# METAL_MAX_DEVICE_REGIONS is used to give the number of memory regions shared -# between processors. By default only one region is defined for the vrings -# and rpmsg buffers. The METAL_MAX_DEVICE_REGIONS has to be redefined to add a -# second region for the resource table. -zephyr_compile_definitions(METAL_MAX_DEVICE_REGIONS=2) - target_include_directories(app PRIVATE ${LIBMETAL_INCLUDE_DIR} ${OPENAMP_INCLUDE_DIR} ${PLATFORM_DIR}) target_sources(app PRIVATE src/main_remote.c) diff --git a/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c b/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c index 6cc906c6a20..8bc1a475d08 100644 --- a/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c +++ b/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c @@ -14,7 +14,8 @@ #include #include -#include +#include +#include #include #ifdef CONFIG_SHELL_BACKEND_RPMSG @@ -53,26 +54,17 @@ static const struct device *const ipm_handle = static metal_phys_addr_t shm_physmap = SHM_START_ADDR; -struct metal_device shm_device = { - .name = SHM_DEVICE_NAME, - .num_regions = 2, - .regions = { - {.virt = NULL}, /* shared memory */ - {.virt = NULL}, /* rsc_table memory */ - }, - .node = { NULL }, - .irq_num = 0, - .irq_info = NULL -}; +static struct metal_io_region shm_io_data; /* shared memory */ +static struct metal_io_region rsc_io_data; /* rsc_table memory */ struct rpmsg_rcv_msg { void *data; size_t len; }; -static struct metal_io_region *shm_io; +static struct metal_io_region *shm_io = &shm_io_data; -static struct metal_io_region *rsc_io; +static struct metal_io_region *rsc_io = &rsc_io_data; static struct rpmsg_virtio_device rvdev; static void *rsc_table; @@ -149,7 +141,6 @@ int platform_init(void) { void *rsc_tab_addr; int rsc_size; - struct metal_device *device; struct metal_init_params metal_params = METAL_INIT_DEFAULTS; int status; @@ -159,41 +150,17 @@ int platform_init(void) return -1; } - status = metal_register_generic_device(&shm_device); - if (status) { - LOG_ERR("Couldn't register shared memory: %d\n", status); - return -1; - } - - status = metal_device_open("generic", SHM_DEVICE_NAME, &device); - if (status) { - LOG_ERR("metal_device_open failed: %d\n", status); - return -1; - } - /* declare shared memory region */ - metal_io_init(&device->regions[0], (void *)SHM_START_ADDR, &shm_physmap, + metal_io_init(shm_io, (void *)SHM_START_ADDR, &shm_physmap, SHM_SIZE, -1, 0, NULL); - shm_io = metal_device_io_region(device, 0); - if (!shm_io) { - LOG_ERR("Failed to get shm_io region\n"); - return -1; - } - /* declare resource table region */ rsc_table_get(&rsc_tab_addr, &rsc_size); rsc_table = (struct st_resource_table *)rsc_tab_addr; - metal_io_init(&device->regions[1], rsc_table, + metal_io_init(rsc_io, rsc_table, (metal_phys_addr_t *)rsc_table, rsc_size, -1, 0, NULL); - rsc_io = metal_device_io_region(device, 1); - if (!rsc_io) { - LOG_ERR("Failed to get rsc_io region\n"); - return -1; - } - /* setup IPM */ if (!device_is_ready(ipm_handle)) { LOG_ERR("IPM device is not ready"); From 2f97795360f99842894ea8af10de7ae521917f09 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Thu, 8 Feb 2024 15:24:56 +0000 Subject: [PATCH 1666/2402] scripts: tests: Blackbox test expansion - platform Adds tests related to the Twister's platform selection: * -A, --board-root * -K, --force-platform * -p, --platform Signed-off-by: Lukasz Mrugala --- .../boards/others/dummy_board/board.yml | 5 + .../boards/others/dummy_board/dummy.yaml | 4 + .../tests/twister_blackbox/test_platform.py | 109 ++++++++++++++++++ subsys/testsuite/soc/unit/dummy_board/soc.yml | 2 + 4 files changed, 120 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_data/boards/others/dummy_board/board.yml create mode 100644 scripts/tests/twister_blackbox/test_data/boards/others/dummy_board/dummy.yaml create mode 100644 scripts/tests/twister_blackbox/test_platform.py create mode 100644 subsys/testsuite/soc/unit/dummy_board/soc.yml diff --git a/scripts/tests/twister_blackbox/test_data/boards/others/dummy_board/board.yml b/scripts/tests/twister_blackbox/test_data/boards/others/dummy_board/board.yml new file mode 100644 index 00000000000..fb3335ab0d5 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/boards/others/dummy_board/board.yml @@ -0,0 +1,5 @@ +board: + name: dummy + vendor: others + socs: + - name: dummy_soc diff --git a/scripts/tests/twister_blackbox/test_data/boards/others/dummy_board/dummy.yaml b/scripts/tests/twister_blackbox/test_data/boards/others/dummy_board/dummy.yaml new file mode 100644 index 00000000000..2138eac2743 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/boards/others/dummy_board/dummy.yaml @@ -0,0 +1,4 @@ +name: dummy_board +vendor: others +arch: unit +identifier: dummy_board/dummy_soc diff --git a/scripts/tests/twister_blackbox/test_platform.py b/scripts/tests/twister_blackbox/test_platform.py new file mode 100644 index 00000000000..8303aebb3b0 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_platform.py @@ -0,0 +1,109 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions related to Zephyr platforms. +""" + +import importlib +import re +import mock +import os +import pytest +import sys +import json + +from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +class TestPlatform: + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @pytest.mark.parametrize( + 'board_root, expected_returncode', + [(True, '0'), (False, '2')], + ids=['dummy in additional board root', 'no additional board root, crash'] + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_board_root(self, out_path, board_root, expected_returncode): + test_platforms = ['qemu_x86', 'dummy_board/dummy_soc'] + board_root_path = os.path.join(TEST_DATA, 'boards') + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + (['--board-root', board_root_path] if board_root else []) + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + # Checking twister.log increases coupling, + # but we need to differentiate crashes. + with open(os.path.join(out_path, 'twister.log')) as f: + log = f.read() + error_regex = r'ERROR.*platform_filter\s+-\s+unrecognized\s+platform\s+-\s+dummy_board/dummy_soc$' + board_error = re.search(error_regex, log) + assert board_error if not board_root else not board_error + + assert str(sys_exit.value) == expected_returncode + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_force_platform(self, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + ['--force-platform'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert str(sys_exit.value) == '0' + + assert len(filtered_j) == 12 + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_platform(self, out_path): + path = os.path.join(TEST_DATA, 'tests', 'dummy') + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + ['--platform', 'qemu_x86'] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert str(sys_exit.value) == '0' + + assert all([platform == 'qemu_x86' for platform, _, _ in filtered_j]) diff --git a/subsys/testsuite/soc/unit/dummy_board/soc.yml b/subsys/testsuite/soc/unit/dummy_board/soc.yml new file mode 100644 index 00000000000..4cf614ebd09 --- /dev/null +++ b/subsys/testsuite/soc/unit/dummy_board/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: dummy_soc From 2302e5f76621bf68a28d0483ab52d15299fbb383 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Thu, 8 Feb 2024 15:58:10 +0000 Subject: [PATCH 1667/2402] scripts: tests: Move bbox platform tests to a single file Blackbox tests related to platform choice now moved to test_platform.py: * test_emulation_only * test_exclude_platform Signed-off-by: Lukasz Mrugala --- .../tests/twister_blackbox/test_platform.py | 229 ++++++++++++++- scripts/tests/twister_blackbox/test_runner.py | 267 ++---------------- 2 files changed, 248 insertions(+), 248 deletions(-) diff --git a/scripts/tests/twister_blackbox/test_platform.py b/scripts/tests/twister_blackbox/test_platform.py index 8303aebb3b0..9dd05aa7ff4 100644 --- a/scripts/tests/twister_blackbox/test_platform.py +++ b/scripts/tests/twister_blackbox/test_platform.py @@ -18,7 +18,49 @@ from twisterlib.testplan import TestPlan +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) class TestPlatform: + TESTDATA_1 = [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), + ['qemu_x86', 'qemu_x86_64', 'frdm_k64f'], + { + 'selected_test_scenarios': 3, + 'selected_test_instances': 9, + 'skipped_configurations': 3, + 'skipped_by_static_filter': 3, + 'skipped_at_runtime': 0, + 'passed_configurations': 6, + 'failed_configurations': 0, + 'errored_configurations': 0, + 'executed_test_cases': 10, + 'skipped_test_cases': 5, + 'platform_count': 3, + 'executed_on_platform': 4, + 'only_built': 2 + } + ), + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'device'), + ['qemu_x86', 'qemu_x86_64', 'frdm_k64f'], + { + 'selected_test_scenarios': 1, + 'selected_test_instances': 3, + 'skipped_configurations': 3, + 'skipped_by_static_filter': 3, + 'skipped_at_runtime': 0, + 'passed_configurations': 0, + 'failed_configurations': 0, + 'errored_configurations': 0, + 'executed_test_cases': 0, + 'skipped_test_cases': 3, + 'platform_count': 3, + 'executed_on_platform': 0, + 'only_built': 0 + } + ), + ] + @classmethod def setup_class(cls): apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') @@ -35,7 +77,6 @@ def teardown_class(cls): [(True, '0'), (False, '2')], ids=['dummy in additional board root', 'no additional board root, crash'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) def test_board_root(self, out_path, board_root, expected_returncode): test_platforms = ['qemu_x86', 'dummy_board/dummy_soc'] board_root_path = os.path.join(TEST_DATA, 'boards') @@ -60,7 +101,6 @@ def test_board_root(self, out_path, board_root, expected_returncode): assert str(sys_exit.value) == expected_returncode - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) def test_force_platform(self, out_path): test_platforms = ['qemu_x86', 'frdm_k64f'] path = os.path.join(TEST_DATA, 'tests', 'dummy') @@ -86,7 +126,6 @@ def test_force_platform(self, out_path): assert len(filtered_j) == 12 - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) def test_platform(self, out_path): path = os.path.join(TEST_DATA, 'tests', 'dummy') args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ @@ -107,3 +146,187 @@ def test_platform(self, out_path): assert str(sys_exit.value) == '0' assert all([platform == 'qemu_x86' for platform, _, _ in filtered_j]) + + @pytest.mark.parametrize( + 'test_path, test_platforms', + [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), + ['qemu_x86'], + ), + ], + ids=[ + 'any_platform', + ], + ) + @pytest.mark.parametrize( + 'flag', + ['-l', '--all'] + ) + def test_any_platform(self, capfd, out_path, test_path, test_platforms, flag): + args = ['--outdir', out_path, '-T', test_path, '-y'] + \ + [flag] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == '0' + + @pytest.mark.parametrize( + 'test_path, test_platforms, expected', + [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), + ['qemu_x86', 'qemu_x86_64'], + { + 'passed_configurations': 3, + 'selected_test_instances': 6, + 'executed_on_platform': 2, + 'only_built': 1, + } + ), + ], + ids=[ + 'exclude_platform', + ], + ) + def test_exclude_platform(self, capfd, out_path, test_path, test_platforms, expected): + args = ['--outdir', out_path, '-T', test_path] + \ + ['--exclude-platform', "qemu_x86"] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + pass_regex = r'^INFO - (?P[0-9]+) of' \ + r' (?P[0-9]+) test configurations passed' + + built_regex = r'^INFO - (?P[0-9]+)' \ + r' test configurations executed on platforms, (?P[0-9]+)' \ + r' test configurations were only built.$' + + pass_search = re.search(pass_regex, err, re.MULTILINE) + + assert pass_search + assert int(pass_search.group('passed_configurations')) == \ + expected['passed_configurations'] + assert int(pass_search.group('test_instances')) == \ + expected['selected_test_instances'] + + built_search = re.search(built_regex, err, re.MULTILINE) + + assert built_search + assert int(built_search.group('executed_on_platform')) == \ + expected['executed_on_platform'] + assert int(built_search.group('only_built')) == \ + expected['only_built'] + + assert str(sys_exit.value) == '0' + + @pytest.mark.parametrize( + 'test_path, test_platforms, expected', + TESTDATA_1, + ids=[ + 'emulation_only tests/dummy/agnostic', + 'emulation_only tests/dummy/device', + ] + ) + def test_emulation_only(self, capfd, out_path, test_path, test_platforms, expected): + args = ['-i', '--outdir', out_path, '-T', test_path] + \ + ['--emulation-only'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + select_regex = r'^INFO - (?P[0-9]+) test scenarios' \ + r' \((?P[0-9]+) test instances\) selected,' \ + r' (?P[0-9]+) configurations skipped' \ + r' \((?P[0-9]+) by static filter,' \ + r' (?P[0-9]+) at runtime\)\.$' + + pass_regex = r'^INFO - (?P[0-9]+) of' \ + r' (?P[0-9]+) test configurations passed' \ + r' \([0-9]+\.[0-9]+%\), (?P[0-9]+) failed,' \ + r' (?P[0-9]+) errored,' \ + r' (?P[0-9]+) skipped with' \ + r' [0-9]+ warnings in [0-9]+\.[0-9]+ seconds$' + + case_regex = r'^INFO - In total (?P[0-9]+)' \ + r' test cases were executed, (?P[0-9]+) skipped' \ + r' on (?P[0-9]+) out of total [0-9]+ platforms' \ + r' \([0-9]+\.[0-9]+%\)$' + + built_regex = r'^INFO - (?P[0-9]+)' \ + r' test configurations executed on platforms, (?P[0-9]+)' \ + r' test configurations were only built.$' + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + select_search = re.search(select_regex, err, re.MULTILINE) + + assert select_search + assert int(select_search.group('test_scenarios')) == \ + expected['selected_test_scenarios'] + assert int(select_search.group('test_instances')) == \ + expected['selected_test_instances'] + assert int(select_search.group('skipped_configurations')) == \ + expected['skipped_configurations'] + assert int(select_search.group('skipped_by_static_filter')) == \ + expected['skipped_by_static_filter'] + assert int(select_search.group('skipped_at_runtime')) == \ + expected['skipped_at_runtime'] + + pass_search = re.search(pass_regex, err, re.MULTILINE) + + assert pass_search + assert int(pass_search.group('passed_configurations')) == \ + expected['passed_configurations'] + assert int(pass_search.group('test_instances')) == \ + expected['selected_test_instances'] + assert int(pass_search.group('failed_configurations')) == \ + expected['failed_configurations'] + assert int(pass_search.group('errored_configurations')) == \ + expected['errored_configurations'] + assert int(pass_search.group('skipped_configurations')) == \ + expected['skipped_configurations'] + + case_search = re.search(case_regex, err, re.MULTILINE) + + assert case_search + assert int(case_search.group('executed_test_cases')) == \ + expected['executed_test_cases'] + assert int(case_search.group('skipped_test_cases')) == \ + expected['skipped_test_cases'] + assert int(case_search.group('platform_count')) == \ + expected['platform_count'] + + built_search = re.search(built_regex, err, re.MULTILINE) + + assert built_search + assert int(built_search.group('executed_on_platform')) == \ + expected['executed_on_platform'] + assert int(built_search.group('only_built')) == \ + expected['only_built'] + + assert str(sys_exit.value) == '0' diff --git a/scripts/tests/twister_blackbox/test_runner.py b/scripts/tests/twister_blackbox/test_runner.py index 80025ae7b9d..97e36d8b8a6 100644 --- a/scripts/tests/twister_blackbox/test_runner.py +++ b/scripts/tests/twister_blackbox/test_runner.py @@ -5,6 +5,7 @@ """ Blackbox tests for twister's command line functions """ +# pylint: disable=duplicate-code import importlib import mock @@ -21,46 +22,6 @@ @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) class TestRunner: TESTDATA_1 = [ - ( - os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64', 'frdm_k64f'], - { - 'selected_test_scenarios': 3, - 'selected_test_instances': 9, - 'skipped_configurations': 3, - 'skipped_by_static_filter': 3, - 'skipped_at_runtime': 0, - 'passed_configurations': 6, - 'failed_configurations': 0, - 'errored_configurations': 0, - 'executed_test_cases': 10, - 'skipped_test_cases': 5, - 'platform_count': 3, - 'executed_on_platform': 4, - 'only_built': 2 - } - ), - ( - os.path.join(TEST_DATA, 'tests', 'dummy', 'device'), - ['qemu_x86', 'qemu_x86_64', 'frdm_k64f'], - { - 'selected_test_scenarios': 1, - 'selected_test_instances': 3, - 'skipped_configurations': 3, - 'skipped_by_static_filter': 3, - 'skipped_at_runtime': 0, - 'passed_configurations': 0, - 'failed_configurations': 0, - 'errored_configurations': 0, - 'executed_test_cases': 0, - 'skipped_test_cases': 3, - 'platform_count': 3, - 'executed_on_platform': 0, - 'only_built': 0 - } - ), - ] - TESTDATA_2 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), ['qemu_x86', 'qemu_x86_64', 'frdm_k64f'], @@ -78,7 +39,7 @@ class TestRunner: } ), ] - TESTDATA_3 = [ + TESTDATA_2 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), ['qemu_x86', 'qemu_x86_64', 'frdm_k64f'], @@ -99,13 +60,13 @@ class TestRunner: } ) ] - TESTDATA_4 = [ + TESTDATA_3 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), ['qemu_x86'], ), ] - TESTDATA_5 = [ + TESTDATA_4 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), ['qemu_x86', 'qemu_x86_64'], @@ -117,26 +78,14 @@ class TestRunner: } ), ] - TESTDATA_6 = [ + TESTDATA_5 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), ['qemu_x86'], os.path.join(TEST_DATA, "pre_script.sh") ), ] - TESTDATA_7 = [ - ( - os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64'], - { - 'passed_configurations': 3, - 'selected_test_instances': 6, - 'executed_on_platform': 2, - 'only_built': 1, - } - ), - ] - TESTDATA_8 = [ + TESTDATA_6 = [ ( os.path.join(TEST_DATA, 'tests', 'always_fail', 'dummy'), ['qemu_x86_64'], @@ -148,7 +97,7 @@ class TestRunner: '2', ), ] - TESTDATA_9 = [ + TESTDATA_7 = [ ( os.path.join(TEST_DATA, 'tests', 'always_fail', 'dummy'), ['qemu_x86'], @@ -160,7 +109,7 @@ class TestRunner: '30', ), ] - TESTDATA_10 = [ + TESTDATA_8 = [ ( os.path.join(TEST_DATA, 'tests', 'always_timeout', 'dummy'), ['qemu_x86'], @@ -172,7 +121,7 @@ class TestRunner: '0.5', ), ] - TESTDATA_11 = [ + TESTDATA_9 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy'), ['qemu_x86'], @@ -198,7 +147,7 @@ class TestRunner: [r'3 of 4 test configurations passed \(100.00%\), 0 failed, 0 errored, 1 skipped'] ), ] - TESTDATA_12 = [ + TESTDATA_10 = [ ( os.path.join(TEST_DATA, 'tests', 'one_fail_one_pass'), ['qemu_x86'], @@ -211,7 +160,7 @@ class TestRunner: } ) ] - TESTDATA_13 = [ + TESTDATA_11 = [ ( os.path.join(TEST_DATA, 'tests', 'always_build_error'), ['qemu_x86_64'], @@ -238,98 +187,6 @@ def teardown_class(cls): @pytest.mark.parametrize( 'test_path, test_platforms, expected', TESTDATA_1, - ids=[ - 'emulation_only tests/dummy/agnostic', - 'emulation_only tests/dummy/device', - ] - ) - def test_emulation_only(self, capfd, out_path, test_path, test_platforms, expected): - args = ['-i', '--outdir', out_path, '-T', test_path, '--emulation-only'] + \ - [val for pair in zip( - ['-p'] * len(test_platforms), test_platforms - ) for val in pair] - - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) - - select_regex = r'^INFO - (?P[0-9]+) test scenarios' \ - r' \((?P[0-9]+) test instances\) selected,' \ - r' (?P[0-9]+) configurations skipped' \ - r' \((?P[0-9]+) by static filter,' \ - r' (?P[0-9]+) at runtime\)\.$' - - pass_regex = r'^INFO - (?P[0-9]+) of' \ - r' (?P[0-9]+) test configurations passed' \ - r' \([0-9]+\.[0-9]+%\), (?P[0-9]+) failed,' \ - r' (?P[0-9]+) errored,' \ - r' (?P[0-9]+) skipped with' \ - r' [0-9]+ warnings in [0-9]+\.[0-9]+ seconds$' - - case_regex = r'^INFO - In total (?P[0-9]+)' \ - r' test cases were executed, (?P[0-9]+) skipped' \ - r' on (?P[0-9]+) out of total [0-9]+ platforms' \ - r' \([0-9]+\.[0-9]+%\)$' - - built_regex = r'^INFO - (?P[0-9]+)' \ - r' test configurations executed on platforms, (?P[0-9]+)' \ - r' test configurations were only built.$' - - out, err = capfd.readouterr() - sys.stdout.write(out) - sys.stderr.write(err) - - select_search = re.search(select_regex, err, re.MULTILINE) - - assert select_search - assert int(select_search.group('test_scenarios')) == \ - expected['selected_test_scenarios'] - assert int(select_search.group('test_instances')) == \ - expected['selected_test_instances'] - assert int(select_search.group('skipped_configurations')) == \ - expected['skipped_configurations'] - assert int(select_search.group('skipped_by_static_filter')) == \ - expected['skipped_by_static_filter'] - assert int(select_search.group('skipped_at_runtime')) == \ - expected['skipped_at_runtime'] - - pass_search = re.search(pass_regex, err, re.MULTILINE) - - assert pass_search - assert int(pass_search.group('passed_configurations')) == \ - expected['passed_configurations'] - assert int(pass_search.group('test_instances')) == \ - expected['selected_test_instances'] - assert int(pass_search.group('failed_configurations')) == \ - expected['failed_configurations'] - assert int(pass_search.group('errored_configurations')) == \ - expected['errored_configurations'] - assert int(pass_search.group('skipped_configurations')) == \ - expected['skipped_configurations'] - - case_search = re.search(case_regex, err, re.MULTILINE) - - assert case_search - assert int(case_search.group('executed_test_cases')) == \ - expected['executed_test_cases'] - assert int(case_search.group('skipped_test_cases')) == \ - expected['skipped_test_cases'] - assert int(case_search.group('platform_count')) == \ - expected['platform_count'] - - built_search = re.search(built_regex, err, re.MULTILINE) - - assert built_search - assert int(built_search.group('executed_on_platform')) == \ - expected['executed_on_platform'] - assert int(built_search.group('only_built')) == \ - expected['only_built'] - - assert str(sys_exit.value) == '0' - - @pytest.mark.parametrize( - 'test_path, test_platforms, expected', - TESTDATA_2, ids=[ 'build_only tests/dummy/agnostic', 'build_only tests/dummy/device', @@ -369,7 +226,7 @@ def test_build_only(self, capfd, out_path, test_path, test_platforms, expected, @pytest.mark.parametrize( 'test_path, test_platforms, expected', - TESTDATA_3, + TESTDATA_2, ids=[ 'test_only' ], @@ -424,11 +281,6 @@ def test_runtest_only(self, capfd, out_path, test_path, test_platforms, expected sys.stdout.write(out) sys.stderr.write(err) - path = os.path.join(out_path, 'twister.log') - with open(path, "r") as log_file: - text_content = log_file.read() - print(text_content) - select_search = re.search(select_regex, err, re.MULTILINE) assert select_search @@ -479,7 +331,7 @@ def test_runtest_only(self, capfd, out_path, test_path, test_platforms, expected @pytest.mark.parametrize( 'test_path, test_platforms', - TESTDATA_4, + TESTDATA_3, ids=[ 'dry_run', ], @@ -504,36 +356,9 @@ def test_dry_run(self, capfd, out_path, test_path, test_platforms, flag): assert str(sys_exit.value) == '0' - @pytest.mark.parametrize( - 'test_path, test_platforms', - TESTDATA_4, - ids=[ - 'any_platform', - ], - ) - @pytest.mark.parametrize( - 'flag', - ['-l', '--all'] - ) - def test_any_platform(self, capfd, out_path, test_path, test_platforms, flag): - args = ['--outdir', out_path, '-T', test_path, flag] + \ - [val for pair in zip( - ['-p'] * len(test_platforms), test_platforms - ) for val in pair] - - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) - - out, err = capfd.readouterr() - sys.stdout.write(out) - sys.stderr.write(err) - - assert str(sys_exit.value) == '0' - @pytest.mark.parametrize( 'test_path, test_platforms, expected', - TESTDATA_5, + TESTDATA_4, ids=[ 'cmake_only', ], @@ -579,7 +404,7 @@ def test_cmake_only(self, capfd, out_path, test_path, test_platforms, expected): @pytest.mark.parametrize( 'test_path, test_platforms, file_name', - TESTDATA_6, + TESTDATA_5, ids=[ 'pre_script', ], @@ -600,55 +425,9 @@ def test_pre_script(self, capfd, out_path, test_path, test_platforms, file_name) assert str(sys_exit.value) == '0' - @pytest.mark.parametrize( - 'test_path, test_platforms, expected', - TESTDATA_7, - ids=[ - 'exclude_platform', - ], - ) - def test_exclude_platform(self, capfd, out_path, test_path, test_platforms, expected): - args = ['--outdir', out_path, '-T', test_path, '--exclude-platform', "qemu_x86"] + \ - [val for pair in zip( - ['-p'] * len(test_platforms), test_platforms - ) for val in pair] - - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) - - out, err = capfd.readouterr() - sys.stdout.write(out) - sys.stderr.write(err) - - pass_regex = r'^INFO - (?P[0-9]+) of' \ - r' (?P[0-9]+) test configurations passed' - - built_regex = r'^INFO - (?P[0-9]+)' \ - r' test configurations executed on platforms, (?P[0-9]+)' \ - r' test configurations were only built.$' - - pass_search = re.search(pass_regex, err, re.MULTILINE) - - assert pass_search - assert int(pass_search.group('passed_configurations')) == \ - expected['passed_configurations'] - assert int(pass_search.group('test_instances')) == \ - expected['selected_test_instances'] - - built_search = re.search(built_regex, err, re.MULTILINE) - - assert built_search - assert int(built_search.group('executed_on_platform')) == \ - expected['executed_on_platform'] - assert int(built_search.group('only_built')) == \ - expected['only_built'] - - assert str(sys_exit.value) == '0' - @pytest.mark.parametrize( 'test_path, test_platforms', - TESTDATA_4, + TESTDATA_3, ids=[ 'device_flash_timeout', ], @@ -671,7 +450,7 @@ def test_device_flash_timeout(self, capfd, out_path, test_path, test_platforms): @pytest.mark.parametrize( 'test_path, test_platforms, iterations', - TESTDATA_8, + TESTDATA_6, ids=[ 'retry 2', 'retry 3' @@ -707,7 +486,7 @@ def test_retry(self, capfd, out_path, test_path, test_platforms, iterations): @pytest.mark.parametrize( 'test_path, test_platforms, interval', - TESTDATA_9, + TESTDATA_7, ids=[ 'retry interval 15', 'retry interval 30' @@ -731,7 +510,6 @@ def test_retry_interval(self, capfd, out_path, test_path, test_platforms, interv end_time = time.time() elapsed_time = end_time - start_time - print(f"Time elapsed: {elapsed_time:.2f} seconds") if elapsed_time < int(interval): assert 'interval was too short' @@ -739,7 +517,7 @@ def test_retry_interval(self, capfd, out_path, test_path, test_platforms, interv @pytest.mark.parametrize( 'test_path, test_platforms, timeout', - TESTDATA_10, + TESTDATA_8, ids=[ 'timeout-multiplier 2 - 20s', 'timeout-multiplier 0.5 - 5s' @@ -770,7 +548,7 @@ def test_timeout_multiplier(self, capfd, out_path, test_path, test_platforms, ti @pytest.mark.parametrize( 'test_path, test_platforms, tags, expected', - TESTDATA_11, + TESTDATA_9, ids=[ 'tags device', 'tags subgruped', @@ -795,14 +573,13 @@ def test_tag(self, capfd, out_path, test_path, test_platforms, tags, expected): sys.stderr.write(err) for line in expected: - print(line) assert re.search(line, err) assert str(sys_exit.value) == '0' @pytest.mark.parametrize( 'test_path, test_platforms, expected', - TESTDATA_12, + TESTDATA_10, ids=[ 'only_failed' ], @@ -865,7 +642,7 @@ def test_only_failed(self, capfd, out_path, test_path, test_platforms, expected) @pytest.mark.parametrize( 'test_path, test_platforms, iterations', - TESTDATA_13, + TESTDATA_11, ids=[ 'retry 2', 'retry 3' From f7f5c4470a3b074039a9e4fa4a1e36960d90d3e5 Mon Sep 17 00:00:00 2001 From: Nikola Trifunovic Date: Sat, 27 Jan 2024 22:18:38 +0100 Subject: [PATCH 1668/2402] boards: xtensa: m5stack_atom_lite: initial support Source code of board/m5stack/m5stickc_plus and board/m5stack/m5stack_atoms3_lite were adapted for an inital support of the M5Stack ATOM Lite board. Signed-off-by: Nikola Trifunovic --- .../m5stack_atom_lite/Kconfig.defconfig | 26 +++ .../Kconfig.m5stack_atom_lite | 10 + boards/m5stack/m5stack_atom_lite/board.cmake | 12 ++ boards/m5stack/m5stack_atom_lite/board.yaml | 5 + .../doc/img/m5stack_atom_lite.webp | Bin 0 -> 8572 bytes .../m5stack/m5stack_atom_lite/doc/index.rst | 134 ++++++++++++ .../m5stack_atom_lite/grove_connectors.dtsi | 18 ++ .../m5stack_atom_lite-pinctrl.dtsi | 65 ++++++ .../m5stack_atom_lite_esp32_appcpu.dts | 74 +++++++ .../m5stack_atom_lite_esp32_appcpu.yaml | 27 +++ .../m5stack_atom_lite_esp32_appcpu_defconfig | 4 + .../m5stack_atom_lite_esp32_procpu.dts | 190 ++++++++++++++++++ .../m5stack_atom_lite_esp32_procpu.yaml | 19 ++ .../m5stack_atom_lite_esp32_procpu_defconfig | 9 + 14 files changed, 593 insertions(+) create mode 100644 boards/m5stack/m5stack_atom_lite/Kconfig.defconfig create mode 100644 boards/m5stack/m5stack_atom_lite/Kconfig.m5stack_atom_lite create mode 100644 boards/m5stack/m5stack_atom_lite/board.cmake create mode 100644 boards/m5stack/m5stack_atom_lite/board.yaml create mode 100644 boards/m5stack/m5stack_atom_lite/doc/img/m5stack_atom_lite.webp create mode 100644 boards/m5stack/m5stack_atom_lite/doc/index.rst create mode 100644 boards/m5stack/m5stack_atom_lite/grove_connectors.dtsi create mode 100644 boards/m5stack/m5stack_atom_lite/m5stack_atom_lite-pinctrl.dtsi create mode 100644 boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu.dts create mode 100644 boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu.yaml create mode 100644 boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu_defconfig create mode 100644 boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu.dts create mode 100644 boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu.yaml create mode 100644 boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu_defconfig diff --git a/boards/m5stack/m5stack_atom_lite/Kconfig.defconfig b/boards/m5stack/m5stack_atom_lite/Kconfig.defconfig new file mode 100644 index 00000000000..d56d34b22d7 --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/Kconfig.defconfig @@ -0,0 +1,26 @@ +# M5Stack ATOM Lite board configuration +# Copyright (c) 2023 Benjamin Cabé +# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_ATOM_LITE_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_M5STACK_ATOM_LITE_ESP32_PROCPU + +if BOARD_M5STACK_ATOM_LITE_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_M5STACK_ATOM_LITE_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_atom_lite/Kconfig.m5stack_atom_lite b/boards/m5stack/m5stack_atom_lite/Kconfig.m5stack_atom_lite new file mode 100644 index 00000000000..2150b48e32f --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/Kconfig.m5stack_atom_lite @@ -0,0 +1,10 @@ +# M5Stack Atom Lite board configuration + +# Copyright (c) 2024 Nikola Trifunovic +# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_ATOM_LITE + select SOC_ESP32_PICO_D4 + select SOC_ESP32_PROCPU if BOARD_M5STACK_ATOM_LITE_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_M5STACK_ATOM_LITE_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_atom_lite/board.cmake b/boards/m5stack/m5stack_atom_lite/board.cmake new file mode 100644 index 00000000000..91b3caa2c75 --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +# the default ESP32 baud rate is not supported +board_runner_args(esp32 "--esp-baud-rate=1500000") diff --git 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***** + Hello World! m5stack_atom_lite + +Debugging +--------- + +M5Stack ATOM Lite debugging is not supported due to pinout limitations. + +Related Documents +***************** +- `M5Stack ATOM Lite docs `_ +- `M5Stack ATOM Lite schematic `_ +- `ESP32-PICO-D4 Datasheet `_ (PDF) diff --git a/boards/m5stack/m5stack_atom_lite/grove_connectors.dtsi b/boards/m5stack/m5stack_atom_lite/grove_connectors.dtsi new file mode 100644 index 00000000000..a2926d68eb2 --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/grove_connectors.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 Nikola Trifunovic + * Copyright (c) 2023 Benjamin Cabé + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + grove_header: grove_header { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 26 0>, + <1 0 &gpio1 0 0>; + }; +}; + +grove_i2c1: &i2c1 {}; diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite-pinctrl.dtsi b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite-pinctrl.dtsi new file mode 100644 index 00000000000..8db8fd6cd35 --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite-pinctrl.dtsi @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024 Nikola Trifunovic + * Copyright (c) 2023 Benjamin Cabé + * Copyright (c) 2023 Martin Kiepfer + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + + }; + + /* used for SK6812 */ + spim3_ws2812_led: spim3_ws2812_led { + group1 { + pinmux = ; + output-low; + }; + }; +}; diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu.dts b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu.dts new file mode 100644 index 00000000000..59a908a3fef --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "M5Stack Atom Lite APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu.yaml b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu.yaml new file mode 100644 index 00000000000..0880b2f7981 --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stack_atom_lite/esp32/appcpu +name: M5Stack ATOM Lite +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu_defconfig b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu_defconfig new file mode 100644 index 00000000000..9abf2ff0430 --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu.dts b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu.dts new file mode 100644 index 00000000000..53f6175e4d1 --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu.dts @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2024 Nikola Trifunovic + * Copyright (c) 2023 Benjamin Cabé + * Copyright (c) 2023 Martin Kiepfer + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stack_atom_lite-pinctrl.dtsi" +#include "grove_connectors.dtsi" +#include +#include +#include + +/ { + model = "M5Stack ATOM Lite PROCPU"; + compatible = "m5stack,m5stack-atom-lite"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + sw0 = &user_button_0; + watchdog0 = &wdt0; + i2c-0 = &i2c0; + led-strip = &status_rgb_led; + }; + + leds { + compatible = "gpio-leds"; + + ir_led: led_0 { + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + label = "Infrared LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button_0: button_0 { + label = "User button 0"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; // G39 + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + sda-gpios = <&gpio0 25 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + sda-gpios = <&gpio0 26 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio1 0 GPIO_OPEN_DRAIN>; +}; + + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +/* used for SK6812 */ +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + line-idle-low; + pinctrl-0 = <&spim3_ws2812_led>; + pinctrl-names = "default"; + + status_rgb_led: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + reg = <0>; + spi-max-frequency = ; + + chain-length = <1>; + color-mapping = , + , + ; + spi-one-frame = ; + spi-zero-frame = ; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu.yaml b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu.yaml new file mode 100644 index 00000000000..14462ac58f8 --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu.yaml @@ -0,0 +1,19 @@ +identifier: m5stack_atom_lite/esp32/procpu +name: M5Stack ATOM Lite +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - pinmux + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: m5stack diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu_defconfig b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu_defconfig new file mode 100644 index 00000000000..0ec9d053667 --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_esp32_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_GPIO=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y From d61a7b2777fc46669b93f4f756638f16e051a8da Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Fri, 9 Feb 2024 14:49:37 +0900 Subject: [PATCH 1669/2402] posix: Implement set and get inheritsched APIs for pthread attr Implement `pthread_attr_setinheritsched()` and `pthread_attr_getinheritsched()`are required as part of _POSIX_THREAD_PRIORITY_SCHEDULING Option Group. signed-off-by: Gaetan Perrot --- include/zephyr/posix/pthread.h | 8 +++++ lib/posix/options/posix_internal.h | 1 + lib/posix/options/pthread.c | 50 +++++++++++++++++++++++++++++- 3 files changed, 58 insertions(+), 1 deletion(-) diff --git a/include/zephyr/posix/pthread.h b/include/zephyr/posix/pthread.h index d950c9ea7fd..7d272fda5e1 100644 --- a/include/zephyr/posix/pthread.h +++ b/include/zephyr/posix/pthread.h @@ -45,6 +45,12 @@ extern "C" { #undef PTHREAD_SCOPE_SYSTEM #define PTHREAD_SCOPE_SYSTEM 0 +/* Pthread inherit scheduler */ +#undef PTHREAD_INHERIT_SCHED +#define PTHREAD_INHERIT_SCHED 0 +#undef PTHREAD_EXPLICIT_SCHED +#define PTHREAD_EXPLICIT_SCHED 1 + /* Passed to pthread_once */ #define PTHREAD_ONCE_INIT {0} @@ -423,6 +429,8 @@ int pthread_attr_setstack(pthread_attr_t *attr, void *stackaddr, size_t stacksize); int pthread_attr_getscope(const pthread_attr_t *attr, int *contentionscope); int pthread_attr_setscope(pthread_attr_t *attr, int contentionscope); +int pthread_attr_getinheritsched(const pthread_attr_t *attr, int *inheritsched); +int pthread_attr_setinheritsched(pthread_attr_t *attr, int inheritsched); #ifdef CONFIG_PTHREAD_IPC int pthread_once(pthread_once_t *once, void (*initFunc)(void)); #endif diff --git a/lib/posix/options/posix_internal.h b/lib/posix/options/posix_internal.h index a723da17f92..06cc8d05a1f 100644 --- a/lib/posix/options/posix_internal.h +++ b/lib/posix/options/posix_internal.h @@ -30,6 +30,7 @@ struct posix_thread_attr { int8_t priority; uint8_t schedpolicy: 2; bool contentionscope: 1; + bool inheritsched: 1; union { bool caller_destroys: 1; bool initialized: 1; diff --git a/lib/posix/options/pthread.c b/lib/posix/options/pthread.c index 086d6a940ad..e7fe47fb030 100644 --- a/lib/posix/options/pthread.c +++ b/lib/posix/options/pthread.c @@ -414,7 +414,7 @@ int pthread_attr_setscope(pthread_attr_t *_attr, int contentionscope) return EINVAL; } if (!(contentionscope == PTHREAD_SCOPE_PROCESS || - contentionscope == PTHREAD_SCOPE_SYSTEM)) { + contentionscope == PTHREAD_SCOPE_SYSTEM)) { LOG_DBG("%s contentionscope %d", "Invalid", contentionscope); return EINVAL; } @@ -427,6 +427,45 @@ int pthread_attr_setscope(pthread_attr_t *_attr, int contentionscope) return 0; } +/** + * @brief Get inherit scheduler attributes in thread attributes object. + * + * See IEEE 1003.1 + */ +int pthread_attr_getinheritsched(const pthread_attr_t *_attr, int *inheritsched) +{ + struct posix_thread_attr *attr = (struct posix_thread_attr *)_attr; + + if (!__attr_is_initialized(attr) || inheritsched == NULL) { + return EINVAL; + } + *inheritsched = attr->inheritsched; + return 0; +} + +/** + * @brief Set inherit scheduler attributes in thread attributes object. + * + * See IEEE 1003.1 + */ +int pthread_attr_setinheritsched(pthread_attr_t *_attr, int inheritsched) +{ + struct posix_thread_attr *attr = (struct posix_thread_attr *)_attr; + + if (!__attr_is_initialized(attr)) { + LOG_DBG("attr %p is not initialized", attr); + return EINVAL; + } + + if (inheritsched != PTHREAD_INHERIT_SCHED && inheritsched != PTHREAD_EXPLICIT_SCHED) { + LOG_DBG("Invalid inheritsched %d", inheritsched); + return EINVAL; + } + + attr->inheritsched = inheritsched; + return 0; +} + static void posix_thread_recycle_work_handler(struct k_work *work) { ARG_UNUSED(work); @@ -599,6 +638,14 @@ int pthread_create(pthread_t *th, const pthread_attr_t *_attr, void *(*threadrou t->attr = *(struct posix_thread_attr *)_attr; } + if (t->attr.inheritsched == PTHREAD_INHERIT_SCHED) { + int pol; + + t->attr.priority = + zephyr_to_posix_priority(k_thread_priority_get(k_current_get()), &pol); + t->attr.schedpolicy = pol; + } + /* spawn the thread */ k_thread_create( &t->thread, t->attr.stack, __get_attr_stacksize(&t->attr) + t->attr.guardsize, @@ -841,6 +888,7 @@ int pthread_attr_init(pthread_attr_t *_attr) *attr = (struct posix_thread_attr){0}; attr->guardsize = CONFIG_POSIX_PTHREAD_ATTR_GUARDSIZE_DEFAULT; attr->contentionscope = PTHREAD_SCOPE_SYSTEM; + attr->inheritsched = PTHREAD_INHERIT_SCHED; if (DYNAMIC_STACK_SIZE > 0) { attr->stack = k_thread_stack_alloc(DYNAMIC_STACK_SIZE + attr->guardsize, From 97f8745eec0576086837999eedc07d823da98d4a Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Fri, 2 Feb 2024 22:11:26 +0900 Subject: [PATCH 1670/2402] doc: posix: mark set and get inheritsched as supported `pthread_attr_getinheritsched()` and `pthread_attr_setinheritsched()` are now implemented, mark it so. signed-off-by: Gaetan Perrot --- doc/services/portability/posix/option_groups/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst index 0c1267ed69e..afb3c184448 100644 --- a/doc/services/portability/posix/option_groups/index.rst +++ b/doc/services/portability/posix/option_groups/index.rst @@ -502,10 +502,10 @@ _POSIX_THREAD_PRIORITY_SCHEDULING :header: API, Supported :widths: 50,10 - pthread_attr_getinheritsched(), + pthread_attr_getinheritsched(),yes pthread_attr_getschedpolicy(),yes pthread_attr_getscope(),yes - pthread_attr_setinheritsched(), + pthread_attr_setinheritsched(),yes pthread_attr_setschedpolicy(),yes pthread_attr_setscope(),yes pthread_getschedparam(),yes From c877cd903d8f5c7260f71ee998e0ce5ebc7637ca Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Fri, 2 Feb 2024 22:25:42 +0900 Subject: [PATCH 1671/2402] posix: Implement tests for set and get inheritsched APIs for pthread attr Add tests for `pthread_attr_setinheritsched()` and `pthread_attr_getinheritsched()` signed-off-by: Gaetan Perrot --- tests/posix/common/src/pthread_attr.c | 130 +++++++++++++++++++++++++- tests/posix/headers/src/pthread_h.c | 8 +- 2 files changed, 130 insertions(+), 8 deletions(-) diff --git a/tests/posix/common/src/pthread_attr.c b/tests/posix/common/src/pthread_attr.c index d6ff3a5ee8d..6d48acb7f7b 100644 --- a/tests/posix/common/src/pthread_attr.c +++ b/tests/posix/common/src/pthread_attr.c @@ -33,7 +33,8 @@ static void *thread_entry(void *arg) return NULL; } -static void create_thread_common(const pthread_attr_t *attrp, bool expect_success, bool joinable) +static void create_thread_common_entry(const pthread_attr_t *attrp, bool expect_success, + bool joinable, void *(*entry)(void *arg), void *arg) { pthread_t th; @@ -42,9 +43,9 @@ static void create_thread_common(const pthread_attr_t *attrp, bool expect_succes } if (expect_success) { - zassert_ok(pthread_create(&th, attrp, thread_entry, UINT_TO_POINTER(joinable))); + zassert_ok(pthread_create(&th, attrp, entry, arg)); } else { - zassert_not_ok(pthread_create(&th, attrp, thread_entry, UINT_TO_POINTER(joinable))); + zassert_not_ok(pthread_create(&th, attrp, entry, arg)); return; } @@ -66,6 +67,12 @@ static void create_thread_common(const pthread_attr_t *attrp, bool expect_succes zassert_true(detached_thread_has_finished, "detached thread did not seem to finish"); } +static void create_thread_common(const pthread_attr_t *attrp, bool expect_success, bool joinable) +{ + create_thread_common_entry(attrp, expect_success, joinable, thread_entry, + UINT_TO_POINTER(joinable)); +} + static inline void can_create_thread(const pthread_attr_t *attrp) { create_thread_common(attrp, true, true); @@ -470,7 +477,8 @@ ZTEST(pthread_attr, test_pthread_attr_setscope) zassert_equal(pthread_attr_setscope(NULL, PTHREAD_SCOPE_SYSTEM), EINVAL); zassert_equal(pthread_attr_setscope(NULL, contentionscope), EINVAL); zassert_equal(pthread_attr_setscope((pthread_attr_t *)&uninit_attr, - contentionscope), EINVAL); + contentionscope), + EINVAL); } zassert_equal(pthread_attr_setscope(&attr, 3), EINVAL); } @@ -481,6 +489,120 @@ ZTEST(pthread_attr, test_pthread_attr_setscope) zassert_equal(contentionscope, PTHREAD_SCOPE_SYSTEM); } +ZTEST(pthread_attr, test_pthread_attr_getinheritsched) +{ + int inheritsched = BIOS_FOOD; + + /* degenerate cases */ + { + if (false) { + /* undefined behaviour */ + zassert_equal(pthread_attr_getinheritsched(NULL, NULL), EINVAL); + zassert_equal(pthread_attr_getinheritsched(NULL, &inheritsched), EINVAL); + zassert_equal(pthread_attr_getinheritsched(&uninit_attr, &inheritsched), + EINVAL); + } + zassert_equal(pthread_attr_getinheritsched(&attr, NULL), EINVAL); + } + + zassert_ok(pthread_attr_getinheritsched(&attr, &inheritsched)); + zassert_equal(inheritsched, PTHREAD_INHERIT_SCHED); +} + +static void *inheritsched_entry(void *arg) +{ + int prio; + int inheritsched; + int pprio = POINTER_TO_INT(arg); + + zassert_ok(pthread_attr_getinheritsched(&attr, &inheritsched)); + + prio = k_thread_priority_get(k_current_get()); + + if (inheritsched == PTHREAD_INHERIT_SCHED) { + /* + * There will be numerical overlap between posix priorities in different scheduler + * policies so only check the Zephyr priority here. The posix policy and posix + * priority are derived from the Zephyr priority in any case. + */ + zassert_equal(prio, pprio, "actual priority: %d, expected priority: %d", prio, + pprio); + return NULL; + } + + /* inheritsched == PTHREAD_EXPLICIT_SCHED */ + int act_prio; + int exp_prio; + int act_policy; + int exp_policy; + struct sched_param param; + + /* get the actual policy, param, etc */ + zassert_ok(pthread_getschedparam(pthread_self(), &act_policy, ¶m)); + act_prio = param.sched_priority; + + /* get the expected policy, param, etc */ + zassert_ok(pthread_attr_getschedpolicy(&attr, &exp_policy)); + zassert_ok(pthread_attr_getschedparam(&attr, ¶m)); + exp_prio = param.sched_priority; + + /* compare actual vs expected */ + zassert_equal(act_policy, exp_policy, "actual policy: %d, expected policy: %d", act_policy, + exp_policy); + zassert_equal(act_prio, exp_prio, "actual priority: %d, expected priority: %d", act_prio, + exp_prio); + + return NULL; +} + +static void test_pthread_attr_setinheritsched_common(bool inheritsched) +{ + int prio; + int policy; + struct sched_param param; + + extern int zephyr_to_posix_priority(int priority, int *policy); + + prio = k_thread_priority_get(k_current_get()); + zassert_not_equal(prio, K_LOWEST_APPLICATION_THREAD_PRIO); + + /* + * values affected by inheritsched are policy / priority / contentionscope + * + * we only support PTHREAD_SCOPE_SYSTEM, so no need to set contentionscope + */ + prio = K_LOWEST_APPLICATION_THREAD_PRIO; + param.sched_priority = zephyr_to_posix_priority(prio, &policy); + + zassert_ok(pthread_attr_setschedpolicy(&attr, policy)); + zassert_ok(pthread_attr_setschedparam(&attr, ¶m)); + zassert_ok(pthread_attr_setinheritsched(&attr, inheritsched)); + create_thread_common_entry(&attr, true, true, inheritsched_entry, + UINT_TO_POINTER(k_thread_priority_get(k_current_get()))); +} + +ZTEST(pthread_attr, test_pthread_attr_setinheritsched) +{ + /* degenerate cases */ + { + if (false) { + /* undefined behaviour */ + zassert_equal(pthread_attr_setinheritsched(NULL, PTHREAD_EXPLICIT_SCHED), + EINVAL); + zassert_equal(pthread_attr_setinheritsched(NULL, PTHREAD_INHERIT_SCHED), + EINVAL); + zassert_equal(pthread_attr_setinheritsched((pthread_attr_t *)&uninit_attr, + PTHREAD_INHERIT_SCHED), + EINVAL); + } + zassert_equal(pthread_attr_setinheritsched(&attr, 3), EINVAL); + } + + /* valid cases */ + test_pthread_attr_setinheritsched_common(PTHREAD_INHERIT_SCHED); + test_pthread_attr_setinheritsched_common(PTHREAD_EXPLICIT_SCHED); +} + ZTEST(pthread_attr, test_pthread_attr_large_stacksize) { size_t actual_size; diff --git a/tests/posix/headers/src/pthread_h.c b/tests/posix/headers/src/pthread_h.c index 17b7768f879..2f6a7942092 100644 --- a/tests/posix/headers/src/pthread_h.c +++ b/tests/posix/headers/src/pthread_h.c @@ -34,8 +34,8 @@ ZTEST(posix_headers, test_pthread_h) zassert_not_equal(-1, PTHREAD_CREATE_DETACHED); zassert_not_equal(-1, PTHREAD_CREATE_JOINABLE); - /* zassert_not_equal(-1, PTHREAD_EXPLICIT_SCHED); */ /* not implemented */ - /* zassert_not_equal(-1, PTHREAD_INHERIT_SCHED); */ /* not implemented */ + zassert_not_equal(-1, PTHREAD_EXPLICIT_SCHED); + zassert_not_equal(-1, PTHREAD_INHERIT_SCHED); zassert_not_equal(-1, PTHREAD_MUTEX_DEFAULT); zassert_not_equal(-1, PTHREAD_MUTEX_ERRORCHECK); @@ -65,7 +65,7 @@ ZTEST(posix_headers, test_pthread_h) zassert_not_null(pthread_attr_destroy); zassert_not_null(pthread_attr_getdetachstate); zassert_not_null(pthread_attr_getguardsize); - /* zassert_not_null(pthread_attr_getinheritsched); */ /* not implemented */ + zassert_not_null(pthread_attr_getinheritsched); zassert_not_null(pthread_attr_getschedparam); zassert_not_null(pthread_attr_getschedpolicy); zassert_not_null(pthread_attr_getscope); @@ -74,7 +74,7 @@ ZTEST(posix_headers, test_pthread_h) zassert_not_null(pthread_attr_init); zassert_not_null(pthread_attr_setdetachstate); zassert_not_null(pthread_attr_setguardsize); - /* zassert_not_null(pthread_attr_setinheritsched); */ /* not implemented */ + zassert_not_null(pthread_attr_setinheritsched); zassert_not_null(pthread_attr_setschedparam); zassert_not_null(pthread_attr_setschedpolicy); zassert_not_null(pthread_attr_setscope); From 63f713a170a33275a8c4ac7fc982066ea9076653 Mon Sep 17 00:00:00 2001 From: Armin Brauns Date: Tue, 6 Feb 2024 12:33:48 +0000 Subject: [PATCH 1672/2402] fs: allow fs_mkfs() for FATFS without auto-format on mounting Users should be able to call fs_mkfs() manually even if FS_FATFS_MOUNT_MKFS is disabled. Signed-off-by: Armin Brauns --- subsys/fs/Kconfig.fatfs | 7 ++++--- subsys/fs/fat_fs.c | 6 +++--- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/subsys/fs/Kconfig.fatfs b/subsys/fs/Kconfig.fatfs index e44ca1c781d..9af43481405 100644 --- a/subsys/fs/Kconfig.fatfs +++ b/subsys/fs/Kconfig.fatfs @@ -25,7 +25,8 @@ config FS_FATFS_READ_ONLY ELM FAT module. config FS_FATFS_MKFS - bool + bool "mkfs support for FAT FS" + default y if FILE_SYSTEM_MKFS help Adds code for creating disks with FAT file system. This option affects FF_USE_MKFS defined in ffconf.h, inside @@ -48,7 +49,7 @@ config FS_FATFS_MOUNT_MKFS prior to connecting to a device, otherwise it will not be mountable. -if FS_FATFS_MOUNT_MKFS +if FS_FATFS_MKFS config FS_FATFS_MAX_ROOT_ENTRIES int "Max number of entries in FAT FS root directory" @@ -59,7 +60,7 @@ config FS_FATFS_MAX_ROOT_ENTRIES formatting new FAT system to a device. Note that this should be multiply of FS_FATFS_MAX_SS / 32. -endif # FS_FATFS_MOUNT_MKFS +endif # FS_FATFS_MKFS config FS_FATFS_EXFAT bool "ExFAT support" diff --git a/subsys/fs/fat_fs.c b/subsys/fs/fat_fs.c index 4f79a97ec9e..a9e5c7f93cd 100644 --- a/subsys/fs/fat_fs.c +++ b/subsys/fs/fat_fs.c @@ -469,7 +469,7 @@ static int fatfs_unmount(struct fs_mount_t *mountp) return translate_error(res); } -#if defined(CONFIG_FILE_SYSTEM_MKFS) +#if defined(CONFIG_FILE_SYSTEM_MKFS) && defined(CONFIG_FS_FATFS_MKFS) static MKFS_PARM def_cfg = { .fmt = FM_ANY | FM_SFD, /* Any suitable FAT */ @@ -494,7 +494,7 @@ static int fatfs_mkfs(uintptr_t dev_id, void *cfg, int flags) return translate_error(res); } -#endif /* CONFIG_FILE_SYSTEM_MKFS */ +#endif /* CONFIG_FILE_SYSTEM_MKFS && FS_FATFS_MKFS */ /* File system interface */ static const struct fs_file_system_t fatfs_fs = { @@ -516,7 +516,7 @@ static const struct fs_file_system_t fatfs_fs = { .mkdir = fatfs_mkdir, .stat = fatfs_stat, .statvfs = fatfs_statvfs, -#if defined(CONFIG_FILE_SYSTEM_MKFS) +#if defined(CONFIG_FILE_SYSTEM_MKFS) && defined(CONFIG_FS_FATFS_MKFS) .mkfs = fatfs_mkfs, #endif }; From 95227b6fd51a924eb384dd213da81757b1fd25af Mon Sep 17 00:00:00 2001 From: Armin Brauns Date: Fri, 15 Mar 2024 09:03:36 +0000 Subject: [PATCH 1673/2402] doc: relnotes: mention new FAT FS Kconfig option See #69791. Signed-off-by: Armin Brauns --- doc/releases/release-notes-3.7.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index a0e21d27f63..6b454318a0b 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -228,6 +228,11 @@ Libraries / Subsystems * Storage + * FAT FS: It is now possible to expose file system formatting functionality for FAT without also + enabling automatic formatting on mount failure by setting the + :kconfig:option:`CONFIG_FS_FATFS_MKFS` Kconfig option. This option is enabled by default if + :kconfig:option:`CONFIG_FILE_SYSTEM_MKFS` is set. + * POSIX API * LoRa/LoRaWAN From fa6eca312fefe4285ce5d8f38c7913ad405d6f77 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Sun, 31 Mar 2024 18:42:34 +0100 Subject: [PATCH 1674/2402] input: utils: rename the input dump callback Change the input callback function name to make it easier to identify what it belongs to. This clears some ambiguity when observing the symbol names corresponding to the function pointers in the callback section. Signed-off-by: Fabio Baltieri --- subsys/input/input_utils.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/subsys/input/input_utils.c b/subsys/input/input_utils.c index 45281b6d5d7..9e093b27b46 100644 --- a/subsys/input/input_utils.c +++ b/subsys/input/input_utils.c @@ -51,7 +51,7 @@ static bool input_dump_enabled(void) } #endif /* CONFIG_INPUT_SHELL */ -static void input_cb(struct input_event *evt) +static void input_dump_cb(struct input_event *evt) { if (!input_dump_enabled()) { return; @@ -64,7 +64,7 @@ static void input_cb(struct input_event *evt) evt->code, evt->value); } -INPUT_CALLBACK_DEFINE(NULL, input_cb); +INPUT_CALLBACK_DEFINE(NULL, input_dump_cb); #endif /* CONFIG_INPUT_EVENT_DUMP */ #ifdef CONFIG_INPUT_SHELL From 7291450151ef585c7b612f16752dad4ff7df9bf1 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Thu, 28 Mar 2024 09:48:36 +0100 Subject: [PATCH 1675/2402] soc: st: stm32 devices: SW JTAG port pins config with hw model V2 During the migration to Hw model V2 the PR #63495 was not fully reported. This change is adding the support Serial Wire / JTAG port pins Signed-off-by: Francois Ramu --- soc/st/stm32/Kconfig | 8 ++++++ soc/st/stm32/common/CMakeLists.txt | 4 +++ soc/st/stm32/common/pm_debug_swj.c | 40 ++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100644 soc/st/stm32/common/pm_debug_swj.c diff --git a/soc/st/stm32/Kconfig b/soc/st/stm32/Kconfig index 363f772f74d..773e62a0dc7 100644 --- a/soc/st/stm32/Kconfig +++ b/soc/st/stm32/Kconfig @@ -39,6 +39,14 @@ config STM32_ENABLE_DEBUG_SLEEP_STOP effectivly destroys the use-case of `west attach`. Also SEGGER RTT and similar technologies need this. +config SWJ_ANALOG_PRIORITY + int "SWJ DP port to analog routine initialization priority" + default 49 + help + Initialization priority of the routine within the PRE_KERNEL1 level. + This priority must be greater than GPIO_INIT_PRIORITY and lower than + UART_INIT_PRIORITY. + choice POWER_SUPPLY_CHOICE prompt "STM32 power supply configuration" default POWER_SUPPLY_LDO diff --git a/soc/st/stm32/common/CMakeLists.txt b/soc/st/stm32/common/CMakeLists.txt index abc9793b2c5..0df733452e2 100644 --- a/soc/st/stm32/common/CMakeLists.txt +++ b/soc/st/stm32/common/CMakeLists.txt @@ -11,3 +11,7 @@ zephyr_linker_sources_ifdef(CONFIG_STM32_CCM SECTIONS ccm.ld) zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c) zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld) + +if (NOT CONFIG_DEBUG AND CONFIG_PM) + zephyr_sources_ifdef(CONFIG_DT_HAS_SWJ_CONNECTOR_ENABLED pm_debug_swj.c) +endif() diff --git a/soc/st/stm32/common/pm_debug_swj.c b/soc/st/stm32/common/pm_debug_swj.c new file mode 100644 index 00000000000..5897670e5f6 --- /dev/null +++ b/soc/st/stm32/common/pm_debug_swj.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2023 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#define SWJ_NODE DT_NODELABEL(swj_port) + +PINCTRL_DT_DEFINE(SWJ_NODE); + +const struct pinctrl_dev_config *swj_pcfg = PINCTRL_DT_DEV_CONFIG_GET(SWJ_NODE); + +/* + * Serial Wire / JTAG port pins are enabled as part of SoC default configuration. + * When debug access is not needed and in case power consumption performance is + * expected, configure matching pins to analog in order to save power. + */ + +static int swj_to_analog(void) +{ + int err; + + /* Set Serial Wire / JTAG port pins to analog mode */ + err = pinctrl_apply_state(swj_pcfg, PINCTRL_STATE_SLEEP); + if (err < 0) { + __ASSERT(0, "SWJ pinctrl setup failed"); + return err; + } + + return 0; +} + +/* Run this routine as the earliest pin configuration in the target, + * to avoid potential conflicts with devices accessing SWJ-DG pins for + * their own needs. + */ +SYS_INIT(swj_to_analog, PRE_KERNEL_1, CONFIG_SWJ_ANALOG_PRIORITY); From 90a58099f563af9977e5eceb31416f5b8b5613f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 28 Mar 2024 16:03:53 +0100 Subject: [PATCH 1676/2402] net: dhcpv4: remove conditions in header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove conditional compile function declarations Signed-off-by: Fin Maaß --- include/zephyr/net/dhcpv4.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/zephyr/net/dhcpv4.h b/include/zephyr/net/dhcpv4.h index 884c4dea5ce..b06a7cb0320 100644 --- a/include/zephyr/net/dhcpv4.h +++ b/include/zephyr/net/dhcpv4.h @@ -64,8 +64,6 @@ enum net_dhcpv4_msg_type { NET_DHCPV4_MSG_TYPE_INFORM = 8, }; -#ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS - struct net_dhcpv4_option_callback; /** @@ -161,10 +159,6 @@ int net_dhcpv4_add_option_callback(struct net_dhcpv4_option_callback *cb); */ int net_dhcpv4_remove_option_callback(struct net_dhcpv4_option_callback *cb); -#endif /* CONFIG_NET_DHCPV4_OPTION_CALLBACKS */ - -#ifdef CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC - /** * @brief Helper to initialize a struct net_dhcpv4_option_callback for encapsulated vendor-specific * options properly @@ -203,8 +197,6 @@ int net_dhcpv4_add_option_vendor_callback(struct net_dhcpv4_option_callback *cb) */ int net_dhcpv4_remove_option_vendor_callback(struct net_dhcpv4_option_callback *cb); -#endif /* CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC */ - /** * @brief Start DHCPv4 client on an iface * From a8135bbdd5e4a5903d6f86918ae4f851a1e94c77 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 28 Mar 2024 13:52:29 +0200 Subject: [PATCH 1677/2402] samples: net: vlan: Support all three network interfaces The VLAN sample application only had configuration support for the Ethernet interface and one VLAN interface, and left the one VLAN interface unconfigured. Fix this by adding config support for all three network interfaces created by the sample. Signed-off-by: Jukka Rissanen --- samples/net/vlan/Kconfig | 47 +++++++++++----- samples/net/vlan/prj.conf | 24 +++++--- samples/net/vlan/src/main.c | 107 +++++++++++++++++++++++++----------- 3 files changed, 125 insertions(+), 53 deletions(-) diff --git a/samples/net/vlan/Kconfig b/samples/net/vlan/Kconfig index 92ef899d276..22ef6b07f8b 100644 --- a/samples/net/vlan/Kconfig +++ b/samples/net/vlan/Kconfig @@ -5,31 +5,52 @@ mainmenu "Networking VLAN sample application" -config SAMPLE_VLAN_TAG - int "Virtual lan tag used in VLAN sample app" +config NET_SAMPLE_IFACE2_MY_IPV6_ADDR + string "My IPv6 address for second interface" + help + The value depends on your network setup. + +config NET_SAMPLE_IFACE2_MY_IPV4_ADDR + string "My IPv4 address for second interface" + help + The value depends on your network setup. + +config NET_SAMPLE_IFACE2_MY_IPV4_NETMASK + string "My IPv4 netmask for second interface" + help + The value depends on your network setup. + +config NET_SAMPLE_IFACE2_VLAN_TAG + int "VLAN tag for second interface" default 100 range 0 4094 depends on NET_VLAN help - Set virtual lan tag (id) that is used in VLAN sample application. + Set VLAN (virtual LAN) tag (id) that is used in the sample + application. -config SAMPLE_VLAN_TAG_2 - int "Second VLAN tag used in VLAN sample app" - default 200 - range 0 4094 - depends on NET_VLAN +config NET_SAMPLE_IFACE3_MY_IPV6_ADDR + string "My IPv6 address for third interface" help - Set virtual lan tag (id) that is used in VLAN sample application. + The value depends on your network setup. -config SAMPLE_IPV6_ADDR_2 - string "My IPv6 address for second interface" +config NET_SAMPLE_IFACE3_MY_IPV4_ADDR + string "My IPv4 address for third interface" help The value depends on your network setup. -config SAMPLE_IPV4_ADDR_2 - string "My IPv4 address for second interface" +config NET_SAMPLE_IFACE3_MY_IPV4_NETMASK + string "My IPv4 netmask for third interface" help The value depends on your network setup. +config NET_SAMPLE_IFACE3_VLAN_TAG + int "VLAN tag for third interface" + default 200 + range 0 4094 + depends on NET_VLAN + help + Set VLAN (virtual LAN) tag (id) that is used in the sample + application. source "Kconfig.zephyr" diff --git a/samples/net/vlan/prj.conf b/samples/net/vlan/prj.conf index 0fb5b752dfd..ffce904005f 100644 --- a/samples/net/vlan/prj.conf +++ b/samples/net/vlan/prj.conf @@ -19,7 +19,7 @@ CONFIG_NET_IF_UNICAST_IPV4_ADDR_COUNT=1 CONFIG_NET_MAX_CONTEXTS=10 CONFIG_NET_IF_MAX_IPV6_COUNT=3 -CONFIG_NET_IF_MAX_IPV6_COUNT=3 +CONFIG_NET_IF_MAX_IPV4_COUNT=3 CONFIG_INIT_STACKS=y CONFIG_PRINTK=y @@ -38,19 +38,25 @@ CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2" CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1" CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2" -# VLAN tag for the first interface -CONFIG_SAMPLE_VLAN_TAG=100 +# Second VLAN supported network interface will have these settings +CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR="2001:db8:100::1" +# TEST-NET-2 from RFC 5737 +CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR="198.51.100.1" +CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_NETMASK="255.255.255.0" +# VLAN tag for the second interface +CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG=100 -# Settings for the second network interface -CONFIG_SAMPLE_IPV6_ADDR_2="2001:db8:200::1" -CONFIG_SAMPLE_VLAN_TAG_2=200 +# Settings for the third VLAN supported network interface +CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR="2001:db8:200::1" # TEST-NET-3 from RFC 5737 -CONFIG_SAMPLE_IPV4_ADDR_2="203.0.113.1" +CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR="203.0.113.1" +CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_NETMASK="255.255.255.0" +# VLAN tag for the second interface +CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG=200 # Logging CONFIG_LOG=y -# VLAN settings. Note that currently SLIP only supports one VLAN tag, -# and that is enforced by Kconfig file. +# VLAN settings. CONFIG_NET_VLAN=y CONFIG_NET_VLAN_COUNT=2 diff --git a/samples/net/vlan/src/main.c b/samples/net/vlan/src/main.c index 4f7483c1d25..7b7736f71a2 100644 --- a/samples/net/vlan/src/main.c +++ b/samples/net/vlan/src/main.c @@ -36,12 +36,69 @@ static void iface_cb(struct net_if *iface, void *user_data) ud->second = iface; } -static int init_app(void) +static int setup_iface(struct net_if *iface, struct net_if *vlan, + const char *ipv6_addr, const char *ipv4_addr, + const char *netmask, uint16_t vlan_tag) { - struct net_if *iface; struct net_if_addr *ifaddr; struct in_addr addr4; struct in6_addr addr6; + int ret; + + ret = net_eth_vlan_enable(iface, vlan_tag); + if (ret < 0) { + LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret); + } + + if (IS_ENABLED(CONFIG_NET_IPV6)) { + if (net_addr_pton(AF_INET6, ipv6_addr, &addr6)) { + LOG_ERR("Invalid address: %s", ipv6_addr); + return -EINVAL; + } + + ifaddr = net_if_ipv6_addr_add(vlan, &addr6, + NET_ADDR_MANUAL, 0); + if (!ifaddr) { + LOG_ERR("Cannot add %s to interface %p", + ipv6_addr, vlan); + return -EINVAL; + } + } + + if (IS_ENABLED(CONFIG_NET_IPV4)) { + if (net_addr_pton(AF_INET, ipv4_addr, &addr4)) { + LOG_ERR("Invalid address: %s", ipv4_addr); + return -EINVAL; + } + + ifaddr = net_if_ipv4_addr_add(vlan, &addr4, + NET_ADDR_MANUAL, 0); + if (!ifaddr) { + LOG_ERR("Cannot add %s to interface %p", + ipv4_addr, vlan); + return -EINVAL; + } + + if (netmask && netmask[0]) { + struct in_addr nm; + + if (net_addr_pton(AF_INET, netmask, &nm)) { + LOG_ERR("Invalid netmask: %s", ipv4_addr); + return -EINVAL; + } + + net_if_ipv4_set_netmask_by_addr(vlan, &addr4, &nm); + } + } + + LOG_DBG("Interface %p VLAN tag %d setup done.", vlan, vlan_tag); + + return 0; +} + +static int init_app(void) +{ + struct net_if *iface; struct ud ud; int ret; @@ -51,43 +108,31 @@ static int init_app(void) return -ENOENT; } + memset(&ud, 0, sizeof(ud)); + net_if_foreach(iface_cb, &ud); - ret = net_eth_vlan_enable(iface, CONFIG_SAMPLE_VLAN_TAG); + ret = setup_iface(iface, ud.first, + CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR, + CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR, + CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_NETMASK, + CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG); if (ret < 0) { - LOG_ERR("Cannot enable VLAN for tag %d (%d)", - CONFIG_SAMPLE_VLAN_TAG, ret); + return ret; } - ret = net_eth_vlan_enable(iface, CONFIG_SAMPLE_VLAN_TAG_2); + ret = setup_iface(iface, ud.second, + CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR, + CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR, + CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_NETMASK, + CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG); if (ret < 0) { - LOG_ERR("Cannot enable VLAN for tag %d (%d)", - CONFIG_SAMPLE_VLAN_TAG_2, ret); + return ret; } - if (net_addr_pton(AF_INET6, CONFIG_SAMPLE_IPV6_ADDR_2, &addr6)) { - LOG_ERR("Invalid address: %s", CONFIG_SAMPLE_IPV6_ADDR_2); - return -EINVAL; - } - - ifaddr = net_if_ipv6_addr_add(ud.second, &addr6, NET_ADDR_MANUAL, 0); - if (!ifaddr) { - LOG_ERR("Cannot add %s to interface %p", - CONFIG_SAMPLE_IPV6_ADDR_2, ud.second); - return -EINVAL; - } - - if (net_addr_pton(AF_INET, CONFIG_SAMPLE_IPV4_ADDR_2, &addr4)) { - LOG_ERR("Invalid address: %s", CONFIG_SAMPLE_IPV4_ADDR_2); - return -EINVAL; - } - - ifaddr = net_if_ipv4_addr_add(ud.second, &addr4, NET_ADDR_MANUAL, 0); - if (!ifaddr) { - LOG_ERR("Cannot add %s to interface %p", - CONFIG_SAMPLE_IPV4_ADDR_2, ud.second); - return -EINVAL; - } + /* Bring up the VLAN interface automatically */ + net_if_up(ud.first); + net_if_up(ud.second); return ret; } From 06a4d4b02fd2fedb3f43dc186a33993757ac663a Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Thu, 14 Mar 2024 11:11:38 +0100 Subject: [PATCH 1678/2402] drivers: sensor: qdec_stm32: clang-format qdec_stm32.c Run clang-format on qdec_stm32.c. This moves '\' in macros to line index 100, which ensures '\' still aligns if a macro is edited with a new line that is longer than the previous longest line. Signed-off-by: Jeppe Odgaard --- drivers/sensor/qdec_stm32/qdec_stm32.c | 41 ++++++++++++-------------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/drivers/sensor/qdec_stm32/qdec_stm32.c b/drivers/sensor/qdec_stm32/qdec_stm32.c index ebb1f65e921..de382476c56 100644 --- a/drivers/sensor/qdec_stm32/qdec_stm32.c +++ b/drivers/sensor/qdec_stm32/qdec_stm32.c @@ -61,7 +61,7 @@ static int qdec_stm32_fetch(const struct device *dev, enum sensor_channel chan) } static int qdec_stm32_get(const struct device *dev, enum sensor_channel chan, - struct sensor_value *val) + struct sensor_value *val) { struct qdec_stm32_dev_data *const dev_data = dev->data; @@ -93,7 +93,7 @@ static int qdec_stm32_initialize(const struct device *dev) } retval = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t)&dev_cfg->pclken); + (clock_control_subsys_t)&dev_cfg->pclken); if (retval < 0) { LOG_ERR("Could not initialize clock"); return retval; @@ -138,25 +138,22 @@ static const struct sensor_driver_api qdec_stm32_driver_api = { .channel_get = qdec_stm32_get, }; -#define QDEC_STM32_INIT(n) \ - PINCTRL_DT_INST_DEFINE(n); \ - static const struct qdec_stm32_dev_cfg qdec##n##_stm32_config = { \ - .pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ - .timer_inst = ((TIM_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(n))), \ - .pclken = { \ - .bus = DT_CLOCKS_CELL(DT_INST_PARENT(n), bus), \ - .enr = DT_CLOCKS_CELL(DT_INST_PARENT(n), bits) \ - }, \ - .is_input_polarity_inverted = DT_INST_PROP(n, st_input_polarity_inverted), \ - .input_filtering_level = DT_INST_PROP(n, st_input_filter_level), \ - .counts_per_revolution = DT_INST_PROP(n, st_counts_per_revolution), \ - }; \ - \ - static struct qdec_stm32_dev_data qdec##n##_stm32_data; \ - \ - SENSOR_DEVICE_DT_INST_DEFINE(n, qdec_stm32_initialize, NULL, \ - &qdec##n##_stm32_data, &qdec##n##_stm32_config, \ - POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, \ - &qdec_stm32_driver_api); +#define QDEC_STM32_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + static const struct qdec_stm32_dev_cfg qdec##n##_stm32_config = { \ + .pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .timer_inst = ((TIM_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(n))), \ + .pclken = {.bus = DT_CLOCKS_CELL(DT_INST_PARENT(n), bus), \ + .enr = DT_CLOCKS_CELL(DT_INST_PARENT(n), bits)}, \ + .is_input_polarity_inverted = DT_INST_PROP(n, st_input_polarity_inverted), \ + .input_filtering_level = DT_INST_PROP(n, st_input_filter_level), \ + .counts_per_revolution = DT_INST_PROP(n, st_counts_per_revolution), \ + }; \ + \ + static struct qdec_stm32_dev_data qdec##n##_stm32_data; \ + \ + SENSOR_DEVICE_DT_INST_DEFINE(n, qdec_stm32_initialize, NULL, &qdec##n##_stm32_data, \ + &qdec##n##_stm32_config, POST_KERNEL, \ + CONFIG_SENSOR_INIT_PRIORITY, &qdec_stm32_driver_api); DT_INST_FOREACH_STATUS_OKAY(QDEC_STM32_INIT) From 2a5dc2a0df8748b8672e922d49e0ef9787755014 Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Wed, 13 Mar 2024 20:30:53 +0100 Subject: [PATCH 1679/2402] drivers: sensor: qdec_stm32: add optional encoder mode Add support for setting encoder mode in dts. Signed-off-by: Jeppe Odgaard --- drivers/sensor/qdec_stm32/qdec_stm32.c | 7 +++++++ dts/bindings/sensor/st,stm32-qdec.yaml | 28 ++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/sensor/qdec_stm32/qdec_stm32.c b/drivers/sensor/qdec_stm32/qdec_stm32.c index de382476c56..b60c242684f 100644 --- a/drivers/sensor/qdec_stm32/qdec_stm32.c +++ b/drivers/sensor/qdec_stm32/qdec_stm32.c @@ -30,6 +30,7 @@ struct qdec_stm32_dev_cfg { const struct pinctrl_dev_config *pin_config; struct stm32_pclken pclken; TIM_TypeDef *timer_inst; + uint32_t encoder_mode; bool is_input_polarity_inverted; uint8_t input_filtering_level; uint32_t counts_per_revolution; @@ -107,6 +108,8 @@ static int qdec_stm32_initialize(const struct device *dev) LL_TIM_ENCODER_StructInit(&init_props); + init_props.EncoderMode = dev_cfg->encoder_mode; + if (dev_cfg->is_input_polarity_inverted) { init_props.IC1Polarity = LL_TIM_IC_POLARITY_FALLING; init_props.IC2Polarity = LL_TIM_IC_POLARITY_FALLING; @@ -139,12 +142,16 @@ static const struct sensor_driver_api qdec_stm32_driver_api = { }; #define QDEC_STM32_INIT(n) \ + BUILD_ASSERT(!(DT_INST_PROP(n, st_encoder_mode) & ~TIM_SMCR_SMS), \ + "Encoder mode is not supported by this MCU"); \ + \ PINCTRL_DT_INST_DEFINE(n); \ static const struct qdec_stm32_dev_cfg qdec##n##_stm32_config = { \ .pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ .timer_inst = ((TIM_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(n))), \ .pclken = {.bus = DT_CLOCKS_CELL(DT_INST_PARENT(n), bus), \ .enr = DT_CLOCKS_CELL(DT_INST_PARENT(n), bits)}, \ + .encoder_mode = DT_INST_PROP(n, st_encoder_mode), \ .is_input_polarity_inverted = DT_INST_PROP(n, st_input_polarity_inverted), \ .input_filtering_level = DT_INST_PROP(n, st_input_filter_level), \ .counts_per_revolution = DT_INST_PROP(n, st_counts_per_revolution), \ diff --git a/dts/bindings/sensor/st,stm32-qdec.yaml b/dts/bindings/sensor/st,stm32-qdec.yaml index 9efae737e7f..c8deae1bb91 100644 --- a/dts/bindings/sensor/st,stm32-qdec.yaml +++ b/dts/bindings/sensor/st,stm32-qdec.yaml @@ -16,6 +16,34 @@ properties: pinctrl-names: required: true + st,encoder-mode: + type: int + description: | + Set encoder mode. + The following modes are supported: + 0x1: Encoder mode 1 (Default) + 0x2: Encoder mode 2 + 0x3: Encoder mode 3 + Some MCUs supports additional modes: + 0x10002: Encoder mode: Clock plus direction, x2 mode + 0x10003: Encoder mode: Clock plus direction, x1 mode + 0x10004: Encoder mode: Directional Clock, x2 mode + 0x10005: Encoder mode: Directional Clock, x1 mode + 0x10006: Quadrature encoder mode: x1 mode, counting on tim_ti1fp1 + 0x10007: Quadrature encoder mode: x1 mode, counting on tim_ti2fp2 + Default value complies with stm32 low level timer encoder init value. + default: 0x1 + enum: + - 0x1 + - 0x2 + - 0x3 + - 0x10002 + - 0x10003 + - 0x10004 + - 0x10005 + - 0x10006 + - 0x10007 + st,input-polarity-inverted: type: boolean description: Encoder is triggered by a falling edge on the input pin From 17b1912bc3512eadc25c19c1d95606a17173e154 Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Wed, 24 Jan 2024 09:05:09 +0100 Subject: [PATCH 1680/2402] drivers: ad559x: add i2c bus support Rename ad5592 files in dts, driver and include to ad559x and add support for I2C bus which is required for AD5593. Signed-off-by: Jeppe Odgaard --- CODEOWNERS | 8 +- drivers/adc/CMakeLists.txt | 2 +- drivers/adc/Kconfig | 2 +- .../adc/{Kconfig.ad5592 => Kconfig.ad559x} | 16 +- drivers/adc/adc_ad5592.c | 255 ---------------- drivers/adc/adc_ad559x.c | 273 ++++++++++++++++++ drivers/adc/adc_shell.c | 2 +- drivers/dac/CMakeLists.txt | 2 +- drivers/dac/Kconfig | 2 +- drivers/dac/Kconfig.ad5592 | 10 - drivers/dac/Kconfig.ad559x | 10 + drivers/dac/dac_ad5592.c | 107 ------- drivers/dac/dac_ad559x.c | 110 +++++++ drivers/gpio/CMakeLists.txt | 2 +- drivers/gpio/Kconfig | 2 +- drivers/gpio/Kconfig.ad5592 | 10 - drivers/gpio/Kconfig.ad559x | 10 + drivers/gpio/gpio_ad5592.c | 227 --------------- drivers/gpio/gpio_ad559x.c | 236 +++++++++++++++ drivers/mfd/CMakeLists.txt | 4 +- drivers/mfd/Kconfig | 2 +- drivers/mfd/Kconfig.ad5592 | 10 - drivers/mfd/Kconfig.ad559x | 25 ++ drivers/mfd/mfd_ad5592.c | 182 ------------ drivers/mfd/mfd_ad559x.c | 110 +++++++ drivers/mfd/mfd_ad559x.h | 65 +++++ drivers/mfd/mfd_ad559x_i2c.c | 79 +++++ drivers/mfd/mfd_ad559x_spi.c | 114 ++++++++ ...di,ad5592-adc.yaml => adi,ad559x-adc.yaml} | 4 +- ...di,ad5592-dac.yaml => adi,ad559x-dac.yaml} | 4 +- ...,ad5592-gpio.yaml => adi,ad559x-gpio.yaml} | 4 +- ...adi,ad5592.yaml => adi,ad559x-common.yaml} | 6 +- dts/bindings/mfd/adi,ad559x-i2c.yaml | 8 + dts/bindings/mfd/adi,ad559x-spi.yaml | 8 + include/zephyr/drivers/mfd/ad5592.h | 91 ------ include/zephyr/drivers/mfd/ad559x.h | 136 +++++++++ .../build_all/adc/boards/native_sim.overlay | 8 +- tests/drivers/build_all/dac/app.overlay | 8 +- tests/drivers/build_all/gpio/app.overlay | 8 +- 39 files changed, 1226 insertions(+), 936 deletions(-) rename drivers/adc/{Kconfig.ad5592 => Kconfig.ad559x} (59%) delete mode 100644 drivers/adc/adc_ad5592.c create mode 100644 drivers/adc/adc_ad559x.c delete mode 100644 drivers/dac/Kconfig.ad5592 create mode 100644 drivers/dac/Kconfig.ad559x delete mode 100644 drivers/dac/dac_ad5592.c create mode 100644 drivers/dac/dac_ad559x.c delete mode 100644 drivers/gpio/Kconfig.ad5592 create mode 100644 drivers/gpio/Kconfig.ad559x delete mode 100644 drivers/gpio/gpio_ad5592.c create mode 100644 drivers/gpio/gpio_ad559x.c delete mode 100644 drivers/mfd/Kconfig.ad5592 create mode 100644 drivers/mfd/Kconfig.ad559x delete mode 100644 drivers/mfd/mfd_ad5592.c create mode 100644 drivers/mfd/mfd_ad559x.c create mode 100644 drivers/mfd/mfd_ad559x.h create mode 100644 drivers/mfd/mfd_ad559x_i2c.c create mode 100644 drivers/mfd/mfd_ad559x_spi.c rename dts/bindings/adc/{adi,ad5592-adc.yaml => adi,ad559x-adc.yaml} (73%) rename dts/bindings/dac/{adi,ad5592-dac.yaml => adi,ad559x-dac.yaml} (73%) rename dts/bindings/gpio/{adi,ad5592-gpio.yaml => adi,ad559x-gpio.yaml} (66%) rename dts/bindings/mfd/{adi,ad5592.yaml => adi,ad559x-common.yaml} (59%) create mode 100644 dts/bindings/mfd/adi,ad559x-i2c.yaml create mode 100644 dts/bindings/mfd/adi,ad559x-spi.yaml delete mode 100644 include/zephyr/drivers/mfd/ad5592.h create mode 100644 include/zephyr/drivers/mfd/ad559x.h diff --git a/CODEOWNERS b/CODEOWNERS index 0a30b6f34c1..60ce1a2533a 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -167,7 +167,7 @@ /drivers/adc/*ads114s0x* @benediktibk /drivers/adc/*max11102_17* @benediktibk /drivers/adc/*kb1200* @ene-steven -/drivers/adc/adc_ad5592.c @bbilas +/drivers/adc/adc_ad559x.c @bbilas /drivers/audio/*nrfx* @anangl /drivers/auxdisplay/*pt6314* @xingrz /drivers/auxdisplay/* @thedjnK @@ -192,7 +192,7 @@ /drivers/display/*rm68200* @mmahadevan108 /drivers/display/display_ili9342c.* @extremegtx /drivers/dac/*ad56xx* @benediktibk -/drivers/dac/dac_ad5592.c @bbilas +/drivers/dac/dac_ad559x.c @bbilas /drivers/dai/ @kv2019i @marcinszkudlinski @abonislawski /drivers/dai/intel/ @kv2019i @marcinszkudlinski @abonislawski /drivers/dai/intel/ssp/ @kv2019i @marcinszkudlinski @abonislawski @@ -244,7 +244,7 @@ /drivers/gpio/*pcal64xxa* @benediktibk /drivers/gpio/*kb1200* @ene-steven /drivers/gpio/gpio_altera_pio.c @shilinte -/drivers/gpio/gpio_ad5592.c @bbilas +/drivers/gpio/gpio_ad559x.c @bbilas /drivers/i2c/i2c_common.c @sjg20 /drivers/i2c/i2c_emul.c @sjg20 /drivers/i2c/i2c_ite_enhance.c @GTLin08 @@ -284,7 +284,7 @@ /drivers/kscan/*ft5336* @MaureenHelm /drivers/kscan/*ht16k33* @henrikbrixandersen /drivers/led_strip/ @mbolivar-ampere -/drivers/mfd/mfd_ad5592.c @bbilas +/drivers/mfd/mfd_ad559x.c @bbilas /drivers/mfd/mfd_max20335.c @bbilas /drivers/misc/ft8xx/ @hubertmis /drivers/modem/hl7800.c @rerickson1 diff --git a/drivers/adc/CMakeLists.txt b/drivers/adc/CMakeLists.txt index edc1baf898a..ae0ebcb5b54 100644 --- a/drivers/adc/CMakeLists.txt +++ b/drivers/adc/CMakeLists.txt @@ -46,7 +46,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC_TLA2021 adc_tla2021.c) zephyr_library_sources_ifdef(CONFIG_ADC_NXP_S32_ADC_SAR adc_nxp_s32_adc_sar.c) zephyr_library_sources_ifdef(CONFIG_ADC_MAX1125X adc_max1125x.c) zephyr_library_sources_ifdef(CONFIG_ADC_MAX11102_17 adc_max11102_17.c) -zephyr_library_sources_ifdef(CONFIG_ADC_AD5592 adc_ad5592.c) +zephyr_library_sources_ifdef(CONFIG_ADC_AD559X adc_ad559x.c) zephyr_library_sources_ifdef(CONFIG_ADC_LTC2451 adc_ltc2451.c) zephyr_library_sources_ifdef(CONFIG_ADC_NUMAKER adc_numaker.c) zephyr_library_sources_ifdef(CONFIG_ADC_ENE_KB1200 adc_ene_kb1200.c) diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index fb4aa3681b3..1f13203c487 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -120,7 +120,7 @@ source "drivers/adc/Kconfig.max1125x" source "drivers/adc/Kconfig.max11102_17" -source "drivers/adc/Kconfig.ad5592" +source "drivers/adc/Kconfig.ad559x" source "drivers/adc/Kconfig.ltc2451" diff --git a/drivers/adc/Kconfig.ad5592 b/drivers/adc/Kconfig.ad559x similarity index 59% rename from drivers/adc/Kconfig.ad5592 rename to drivers/adc/Kconfig.ad559x index 92b80f34217..7c5f65bb745 100644 --- a/drivers/adc/Kconfig.ad5592 +++ b/drivers/adc/Kconfig.ad559x @@ -1,25 +1,25 @@ # Copyright (c) 2023 Grinn # SPDX -License-Identifier: Apache-2.0 -config ADC_AD5592 - bool "AD5592 ADC driver" +config ADC_AD559X + bool "AD559x ADC driver" default y - depends on DT_HAS_ADI_AD5592_ADC_ENABLED + depends on DT_HAS_ADI_AD559X_ADC_ENABLED select MFD help - Enable the AD5592 ADC driver. + Enable the AD559x ADC driver. -config ADC_AD5592_ACQUISITION_THREAD_STACK_SIZE +config ADC_AD559X_ACQUISITION_THREAD_STACK_SIZE int "Stack size for the ADC data acquisition thread" - depends on ADC_AD5592 + depends on ADC_AD559X default 384 help Size of the stack used for the internal data acquisition thread. -config ADC_AD5592_ACQUISITION_THREAD_PRIO +config ADC_AD559X_ACQUISITION_THREAD_PRIO int "Priority for the ADC data acquisition thread" - depends on ADC_AD5592 + depends on ADC_AD559X default 0 help Priority level for the internal ADC data acquisition thread. diff --git a/drivers/adc/adc_ad5592.c b/drivers/adc/adc_ad5592.c deleted file mode 100644 index b804e62e9ad..00000000000 --- a/drivers/adc/adc_ad5592.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2023 Grinn - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT adi_ad5592_adc - -#include -#include -#include - -#include - -#define ADC_CONTEXT_USES_KERNEL_TIMER -#include "adc_context.h" - -#include -LOG_MODULE_REGISTER(adc_ad5592, CONFIG_ADC_LOG_LEVEL); - -#define AD5592_ADC_RESOLUTION 12U -#define AD5592_ADC_MAX_VAL 4096 - -struct adc_ad5592_config { - const struct device *mfd_dev; -}; - -struct adc_ad5592_data { - struct adc_context ctx; - const struct device *dev; - uint8_t adc_conf; - uint16_t *buffer; - uint16_t *repeat_buffer; - uint8_t channels; - struct k_thread thread; - struct k_sem sem; - - K_KERNEL_STACK_MEMBER(stack, CONFIG_ADC_AD5592_ACQUISITION_THREAD_STACK_SIZE); -}; - -static int adc_ad5592_channel_setup(const struct device *dev, - const struct adc_channel_cfg *channel_cfg) -{ - const struct adc_ad5592_config *config = dev->config; - struct adc_ad5592_data *data = dev->data; - - if (channel_cfg->channel_id >= AD5592_PIN_MAX) { - LOG_ERR("invalid channel id %d", channel_cfg->channel_id); - return -EINVAL; - } - - data->adc_conf |= BIT(channel_cfg->channel_id); - - return mfd_ad5592_write_reg(config->mfd_dev, AD5592_REG_ADC_CONFIG, data->adc_conf); -} - -static int adc_ad5592_validate_buffer_size(const struct device *dev, - const struct adc_sequence *sequence) -{ - uint8_t channels; - size_t needed; - - channels = POPCOUNT(sequence->channels); - needed = channels * sizeof(uint16_t); - - if (sequence->buffer_size < needed) { - return -ENOMEM; - } - - return 0; -} - -static int adc_ad5592_start_read(const struct device *dev, const struct adc_sequence *sequence) -{ - struct adc_ad5592_data *data = dev->data; - int ret; - - if (sequence->resolution != AD5592_ADC_RESOLUTION) { - LOG_ERR("invalid resolution %d", sequence->resolution); - return -EINVAL; - } - - if (find_msb_set(sequence->channels) > AD5592_PIN_MAX) { - LOG_ERR("invalid channels in mask: 0x%08x", sequence->channels); - return -EINVAL; - } - - ret = adc_ad5592_validate_buffer_size(dev, sequence); - if (ret < 0) { - LOG_ERR("insufficient buffer size"); - return ret; - } - - data->buffer = sequence->buffer; - adc_context_start_read(&data->ctx, sequence); - - return adc_context_wait_for_completion(&data->ctx); -} - -static int adc_ad5592_read_channel(const struct device *dev, uint8_t channel, uint16_t *result) -{ - const struct adc_ad5592_config *config = dev->config; - uint16_t val; - int ret; - - ret = mfd_ad5592_write_reg(config->mfd_dev, AD5592_REG_SEQ_ADC, BIT(channel)); - if (ret < 0) { - return ret; - } - - /* - * Invalid data: - * See Figure 46. Single-Channel ADC Conversion Sequence. - * The first conversion result always returns invalid data. - */ - (void) mfd_ad5592_read_raw(config->mfd_dev, &val); - - ret = mfd_ad5592_read_raw(config->mfd_dev, &val); - if (ret < 0) { - return ret; - } - - val = sys_be16_to_cpu(val); - if (channel >= 1) { - val -= channel * AD5592_ADC_MAX_VAL; - } - - *result = val; - - return 0; -} - -static void adc_context_start_sampling(struct adc_context *ctx) -{ - struct adc_ad5592_data *data = CONTAINER_OF(ctx, struct adc_ad5592_data, ctx); - - data->channels = ctx->sequence.channels; - data->repeat_buffer = data->buffer; - - k_sem_give(&data->sem); -} - -static void adc_context_update_buffer_pointer(struct adc_context *ctx, - bool repeat_sampling) -{ - struct adc_ad5592_data *data = CONTAINER_OF(ctx, struct adc_ad5592_data, ctx); - - if (repeat_sampling) { - data->buffer = data->repeat_buffer; - } -} - -static void adc_ad5592_acquisition_thread(struct adc_ad5592_data *data) -{ - uint16_t result; - uint8_t channel; - int ret; - - while (true) { - k_sem_take(&data->sem, K_FOREVER); - - while (data->channels != 0) { - channel = find_lsb_set(data->channels) - 1; - - ret = adc_ad5592_read_channel(data->dev, channel, &result); - if (ret < 0) { - LOG_ERR("failed to read channel %d (ret %d)", channel, ret); - adc_context_complete(&data->ctx, ret); - break; - } - - *data->buffer++ = result; - WRITE_BIT(data->channels, channel, 0); - } - - adc_context_on_sampling_done(&data->ctx, data->dev); - } -} - -static int adc_ad5592_read_async(const struct device *dev, - const struct adc_sequence *sequence, - struct k_poll_signal *async) -{ - struct adc_ad5592_data *data = dev->data; - int ret; - - adc_context_lock(&data->ctx, async ? true : false, async); - ret = adc_ad5592_start_read(dev, sequence); - adc_context_release(&data->ctx, ret); - - return ret; -} - -static int adc_ad5592_read(const struct device *dev, - const struct adc_sequence *sequence) -{ - return adc_ad5592_read_async(dev, sequence, NULL); -} - -static int adc_ad5592_init(const struct device *dev) -{ - const struct adc_ad5592_config *config = dev->config; - struct adc_ad5592_data *data = dev->data; - k_tid_t tid; - int ret; - - if (!device_is_ready(config->mfd_dev)) { - return -ENODEV; - } - - ret = mfd_ad5592_write_reg(config->mfd_dev, AD5592_REG_PD_REF_CTRL, AD5592_EN_REF); - if (ret < 0) { - return ret; - } - - data->dev = dev; - - k_sem_init(&data->sem, 0, 1); - adc_context_init(&data->ctx); - - tid = k_thread_create(&data->thread, data->stack, - K_KERNEL_STACK_SIZEOF(data->stack), - (k_thread_entry_t)adc_ad5592_acquisition_thread, data, NULL, NULL, - CONFIG_ADC_AD5592_ACQUISITION_THREAD_PRIO, 0, K_NO_WAIT); - - ret = k_thread_name_set(tid, "adc_ad5592"); - if (ret < 0) { - return ret; - } - - adc_context_unlock_unconditionally(&data->ctx); - - return 0; -} - -static const struct adc_driver_api adc_ad5592_api = { - .channel_setup = adc_ad5592_channel_setup, - .read = adc_ad5592_read, -#ifdef CONFIG_ADC_ASYNC - .read_async = adc_ad5592_read_async, -#endif -}; - -#define ADC_AD5592_DEFINE(inst) \ - static const struct adc_ad5592_config adc_ad5592_config##inst = { \ - .mfd_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \ - }; \ - \ - static struct adc_ad5592_data adc_ad5592_data##inst; \ - \ - DEVICE_DT_INST_DEFINE(inst, adc_ad5592_init, NULL, \ - &adc_ad5592_data##inst, &adc_ad5592_config##inst, \ - POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \ - &adc_ad5592_api); - -DT_INST_FOREACH_STATUS_OKAY(ADC_AD5592_DEFINE) diff --git a/drivers/adc/adc_ad559x.c b/drivers/adc/adc_ad559x.c new file mode 100644 index 00000000000..43db99ac408 --- /dev/null +++ b/drivers/adc/adc_ad559x.c @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2023 Grinn + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT adi_ad559x_adc + +#include +#include +#include + +#include + +#define ADC_CONTEXT_USES_KERNEL_TIMER +#include "adc_context.h" + +#include +LOG_MODULE_REGISTER(adc_ad559x, CONFIG_ADC_LOG_LEVEL); + +#define AD559X_ADC_RD_POINTER_SIZE 1 +#define AD559X_ADC_RD_POINTER 0x40 + +#define AD559X_ADC_RESOLUTION 12U + +struct adc_ad559x_config { + const struct device *mfd_dev; +}; + +struct adc_ad559x_data { + struct adc_context ctx; + const struct device *dev; + uint8_t adc_conf; + uint16_t *buffer; + uint16_t *repeat_buffer; + uint8_t channels; + struct k_thread thread; + struct k_sem sem; + + K_KERNEL_STACK_MEMBER(stack, CONFIG_ADC_AD559X_ACQUISITION_THREAD_STACK_SIZE); +}; + +static int adc_ad559x_channel_setup(const struct device *dev, + const struct adc_channel_cfg *channel_cfg) +{ + const struct adc_ad559x_config *config = dev->config; + struct adc_ad559x_data *data = dev->data; + + if (channel_cfg->channel_id >= AD559X_PIN_MAX) { + LOG_ERR("invalid channel id %d", channel_cfg->channel_id); + return -EINVAL; + } + + data->adc_conf |= BIT(channel_cfg->channel_id); + + return mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_ADC_CONFIG, data->adc_conf); +} + +static int adc_ad559x_validate_buffer_size(const struct device *dev, + const struct adc_sequence *sequence) +{ + uint8_t channels; + size_t needed; + + channels = POPCOUNT(sequence->channels); + needed = channels * sizeof(uint16_t); + + if (sequence->buffer_size < needed) { + return -ENOMEM; + } + + return 0; +} + +static int adc_ad559x_start_read(const struct device *dev, const struct adc_sequence *sequence) +{ + struct adc_ad559x_data *data = dev->data; + int ret; + + if (sequence->resolution != AD559X_ADC_RESOLUTION) { + LOG_ERR("invalid resolution %d", sequence->resolution); + return -EINVAL; + } + + if (find_msb_set(sequence->channels) > AD559X_PIN_MAX) { + LOG_ERR("invalid channels in mask: 0x%08x", sequence->channels); + return -EINVAL; + } + + ret = adc_ad559x_validate_buffer_size(dev, sequence); + if (ret < 0) { + LOG_ERR("insufficient buffer size"); + return ret; + } + + data->buffer = sequence->buffer; + adc_context_start_read(&data->ctx, sequence); + + return adc_context_wait_for_completion(&data->ctx); +} + +static int adc_ad559x_read_channel(const struct device *dev, uint8_t channel, uint16_t *result) +{ + const struct adc_ad559x_config *config = dev->config; + uint16_t val; + int ret; + + /* Select channel */ + ret = mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_SEQ_ADC, BIT(channel)); + if (ret < 0) { + return ret; + } + + if (mfd_ad559x_has_pointer_byte_map(config->mfd_dev)) { + /* Start readback */ + val = AD559X_ADC_RD_POINTER; + ret = mfd_ad559x_write_raw(config->mfd_dev, (uint8_t *)&val, + AD559X_ADC_RD_POINTER_SIZE); + if (ret < 0) { + return ret; + } + + /* Read channel */ + ret = mfd_ad559x_read_raw(config->mfd_dev, (uint8_t *)&val, sizeof(val)); + if (ret < 0) { + return ret; + } + + *result = sys_get_be16((uint8_t *)&val); + + } else { + /* + * Invalid data: + * See Figure 46. Single-Channel ADC Conversion Sequence. + * The first conversion result always returns invalid data. + */ + (void)mfd_ad559x_read_raw(config->mfd_dev, (uint8_t *)&val, sizeof(val)); + + ret = mfd_ad559x_read_raw(config->mfd_dev, (uint8_t *)&val, sizeof(val)); + if (ret < 0) { + return ret; + } + + val = sys_be16_to_cpu(val); + if (channel >= 1) { + val -= channel * BIT(AD559X_ADC_RESOLUTION); + } + + *result = val; + } + + return 0; +} + +static void adc_context_start_sampling(struct adc_context *ctx) +{ + struct adc_ad559x_data *data = CONTAINER_OF(ctx, struct adc_ad559x_data, ctx); + + data->channels = ctx->sequence.channels; + data->repeat_buffer = data->buffer; + + k_sem_give(&data->sem); +} + +static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling) +{ + struct adc_ad559x_data *data = CONTAINER_OF(ctx, struct adc_ad559x_data, ctx); + + if (repeat_sampling) { + data->buffer = data->repeat_buffer; + } +} + +static void adc_ad559x_acquisition_thread(struct adc_ad559x_data *data) +{ + uint16_t result; + uint8_t channel; + int ret; + + while (true) { + k_sem_take(&data->sem, K_FOREVER); + + while (data->channels != 0) { + channel = find_lsb_set(data->channels) - 1; + + ret = adc_ad559x_read_channel(data->dev, channel, &result); + if (ret < 0) { + LOG_ERR("failed to read channel %d (ret %d)", channel, ret); + adc_context_complete(&data->ctx, ret); + break; + } + + *data->buffer++ = result; + WRITE_BIT(data->channels, channel, 0); + } + + adc_context_on_sampling_done(&data->ctx, data->dev); + } +} + +static int adc_ad559x_read_async(const struct device *dev, const struct adc_sequence *sequence, + struct k_poll_signal *async) +{ + struct adc_ad559x_data *data = dev->data; + int ret; + + adc_context_lock(&data->ctx, async ? true : false, async); + ret = adc_ad559x_start_read(dev, sequence); + adc_context_release(&data->ctx, ret); + + return ret; +} + +static int adc_ad559x_read(const struct device *dev, const struct adc_sequence *sequence) +{ + return adc_ad559x_read_async(dev, sequence, NULL); +} + +static int adc_ad559x_init(const struct device *dev) +{ + const struct adc_ad559x_config *config = dev->config; + struct adc_ad559x_data *data = dev->data; + k_tid_t tid; + int ret; + + if (!device_is_ready(config->mfd_dev)) { + return -ENODEV; + } + + ret = mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_PD_REF_CTRL, AD559X_EN_REF); + if (ret < 0) { + return ret; + } + + data->dev = dev; + + k_sem_init(&data->sem, 0, 1); + adc_context_init(&data->ctx); + + tid = k_thread_create(&data->thread, data->stack, + K_KERNEL_STACK_SIZEOF(data->stack), + (k_thread_entry_t)adc_ad559x_acquisition_thread, data, NULL, NULL, + CONFIG_ADC_AD559X_ACQUISITION_THREAD_PRIO, 0, K_NO_WAIT); + + ret = k_thread_name_set(tid, "adc_ad559x"); + if (ret < 0) { + return ret; + } + + adc_context_unlock_unconditionally(&data->ctx); + + return 0; +} + +static const struct adc_driver_api adc_ad559x_api = { + .channel_setup = adc_ad559x_channel_setup, + .read = adc_ad559x_read, +#ifdef CONFIG_ADC_ASYNC + .read_async = adc_ad559x_read_async, +#endif +}; + +#define ADC_AD559X_DEFINE(inst) \ + static const struct adc_ad559x_config adc_ad559x_config##inst = { \ + .mfd_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \ + }; \ + \ + static struct adc_ad559x_data adc_ad559x_data##inst; \ + \ + DEVICE_DT_INST_DEFINE(inst, adc_ad559x_init, NULL, &adc_ad559x_data##inst, \ + &adc_ad559x_config##inst, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \ + &adc_ad559x_api); + +DT_INST_FOREACH_STATUS_OKAY(ADC_AD559X_DEFINE) diff --git a/drivers/adc/adc_shell.c b/drivers/adc/adc_shell.c index bc002d76972..0b6951d9900 100644 --- a/drivers/adc/adc_shell.c +++ b/drivers/adc/adc_shell.c @@ -75,7 +75,7 @@ static struct adc_hdl { uint8_t resolution; } adc_list[] = { /* zephyr-keep-sorted-start */ - DT_FOREACH_STATUS_OKAY(adi_ad5592_adc, ADC_HDL_LIST_ENTRY) + DT_FOREACH_STATUS_OKAY(adi_ad559x_adc, ADC_HDL_LIST_ENTRY) DT_FOREACH_STATUS_OKAY(atmel_sam0_adc, ADC_HDL_LIST_ENTRY) DT_FOREACH_STATUS_OKAY(atmel_sam_adc, ADC_HDL_LIST_ENTRY) DT_FOREACH_STATUS_OKAY(atmel_sam_afec, ADC_HDL_LIST_ENTRY) diff --git a/drivers/dac/CMakeLists.txt b/drivers/dac/CMakeLists.txt index c84b0d9d78e..4e1f72bb71d 100644 --- a/drivers/dac/CMakeLists.txt +++ b/drivers/dac/CMakeLists.txt @@ -18,6 +18,6 @@ zephyr_library_sources_ifdef(CONFIG_DAC_MCP4725 dac_mcp4725.c) zephyr_library_sources_ifdef(CONFIG_DAC_MCP4728 dac_mcp4728.c) zephyr_library_sources_ifdef(CONFIG_DAC_GD32 dac_gd32.c) zephyr_library_sources_ifdef(CONFIG_DAC_ESP32 dac_esp32.c) -zephyr_library_sources_ifdef(CONFIG_DAC_AD5592 dac_ad5592.c) +zephyr_library_sources_ifdef(CONFIG_DAC_AD559X dac_ad559x.c) zephyr_library_sources_ifdef(CONFIG_DAC_AD56XX dac_ad56xx.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE dac_handlers.c) diff --git a/drivers/dac/Kconfig b/drivers/dac/Kconfig index 3735a11aa2a..97edb2c0bcf 100644 --- a/drivers/dac/Kconfig +++ b/drivers/dac/Kconfig @@ -53,6 +53,6 @@ source "drivers/dac/Kconfig.esp32" source "drivers/dac/Kconfig.ad56xx" -source "drivers/dac/Kconfig.ad5592" +source "drivers/dac/Kconfig.ad559x" endif # DAC diff --git a/drivers/dac/Kconfig.ad5592 b/drivers/dac/Kconfig.ad5592 deleted file mode 100644 index 1010992fb7f..00000000000 --- a/drivers/dac/Kconfig.ad5592 +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Grinn -# SPDX -License-Identifier: Apache-2.0 - -config DAC_AD5592 - bool "AD5592 DAC driver" - default y - depends on DT_HAS_ADI_AD5592_DAC_ENABLED - select MFD - help - Enable the AD5592 DAC driver. diff --git a/drivers/dac/Kconfig.ad559x b/drivers/dac/Kconfig.ad559x new file mode 100644 index 00000000000..5266680199f --- /dev/null +++ b/drivers/dac/Kconfig.ad559x @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Grinn +# SPDX -License-Identifier: Apache-2.0 + +config DAC_AD559X + bool "AD559x DAC driver" + default y + depends on DT_HAS_ADI_AD559X_DAC_ENABLED + select MFD + help + Enable the AD559x DAC driver. diff --git a/drivers/dac/dac_ad5592.c b/drivers/dac/dac_ad5592.c deleted file mode 100644 index 653df85dd56..00000000000 --- a/drivers/dac/dac_ad5592.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2023 Grinn - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT adi_ad5592_dac - -#include -#include -#include - -#include - -#include -LOG_MODULE_REGISTER(dac_ad5592, CONFIG_DAC_LOG_LEVEL); - -#define AD5592_DAC_RESOLUTION 12 -#define AD5592_DAC_WR_MSB_BIT BIT(15) -#define AD5592_DAC_CHANNEL_SHIFT_VAL 12 - -struct dac_ad5592_config { - const struct device *mfd_dev; -}; - -struct dac_ad5592_data { - uint8_t dac_conf; -}; - -static int dac_ad5592_channel_setup(const struct device *dev, - const struct dac_channel_cfg *channel_cfg) -{ - const struct dac_ad5592_config *config = dev->config; - struct dac_ad5592_data *data = dev->data; - - if (channel_cfg->channel_id >= AD5592_PIN_MAX) { - LOG_ERR("Invalid channel number %d", channel_cfg->channel_id); - return -EINVAL; - } - - if (channel_cfg->resolution != AD5592_DAC_RESOLUTION) { - LOG_ERR("Invalid resolution %d", channel_cfg->resolution); - return -EINVAL; - } - - data->dac_conf |= BIT(channel_cfg->channel_id); - - return mfd_ad5592_write_reg(config->mfd_dev, AD5592_REG_LDAC_EN, data->dac_conf); -} - -static int dac_ad5592_write_value(const struct device *dev, uint8_t channel, - uint32_t value) -{ - const struct dac_ad5592_config *config = dev->config; - uint16_t msg; - - if (channel >= AD5592_PIN_MAX) { - LOG_ERR("Invalid channel number %d", channel); - return -EINVAL; - } - - if (value >= (1 << AD5592_DAC_RESOLUTION)) { - LOG_ERR("Value %d out of range", value); - return -EINVAL; - } - - msg = sys_cpu_to_be16(AD5592_DAC_WR_MSB_BIT | - channel << AD5592_DAC_CHANNEL_SHIFT_VAL | - value); - - return mfd_ad5592_write_raw(config->mfd_dev, msg); -} - -static const struct dac_driver_api dac_ad5592_api = { - .channel_setup = dac_ad5592_channel_setup, - .write_value = dac_ad5592_write_value, -}; - -static int dac_ad5592_init(const struct device *dev) -{ - const struct dac_ad5592_config *config = dev->config; - int ret; - - if (!device_is_ready(config->mfd_dev)) { - return -ENODEV; - } - - ret = mfd_ad5592_write_reg(config->mfd_dev, AD5592_REG_PD_REF_CTRL, AD5592_EN_REF); - if (ret < 0) { - return ret; - } - - return 0; -} - -#define DAC_AD5592_DEFINE(inst) \ - static const struct dac_ad5592_config dac_ad5592_config##inst = { \ - .mfd_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \ - }; \ - \ - struct dac_ad5592_data dac_ad5592_data##inst; \ - \ - DEVICE_DT_INST_DEFINE(inst, dac_ad5592_init, NULL, \ - &dac_ad5592_data##inst, &dac_ad5592_config##inst, \ - POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \ - &dac_ad5592_api); - -DT_INST_FOREACH_STATUS_OKAY(DAC_AD5592_DEFINE) diff --git a/drivers/dac/dac_ad559x.c b/drivers/dac/dac_ad559x.c new file mode 100644 index 00000000000..0dc1c3caa23 --- /dev/null +++ b/drivers/dac/dac_ad559x.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2023 Grinn + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT adi_ad559x_dac + +#include +#include +#include + +#include + +#include +LOG_MODULE_REGISTER(dac_ad559x, CONFIG_DAC_LOG_LEVEL); + +#define AD559X_DAC_RESOLUTION 12 +#define AD559X_DAC_WR_POINTER 0x10 +#define AD559X_DAC_WR_MSB_BIT BIT(15) +#define AD559X_DAC_CHANNEL_SHIFT_VAL 12 + +struct dac_ad559x_config { + const struct device *mfd_dev; +}; + +struct dac_ad559x_data { + uint8_t dac_conf; +}; + +static int dac_ad559x_channel_setup(const struct device *dev, + const struct dac_channel_cfg *channel_cfg) +{ + const struct dac_ad559x_config *config = dev->config; + struct dac_ad559x_data *data = dev->data; + + if (channel_cfg->channel_id >= AD559X_PIN_MAX) { + LOG_ERR("Invalid channel number %d", channel_cfg->channel_id); + return -EINVAL; + } + + if (channel_cfg->resolution != AD559X_DAC_RESOLUTION) { + LOG_ERR("Invalid resolution %d", channel_cfg->resolution); + return -EINVAL; + } + + data->dac_conf |= BIT(channel_cfg->channel_id); + + return mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_LDAC_EN, data->dac_conf); +} + +static int dac_ad559x_write_value(const struct device *dev, uint8_t channel, uint32_t value) +{ + const struct dac_ad559x_config *config = dev->config; + uint16_t msg; + + if (channel >= AD559X_PIN_MAX) { + LOG_ERR("Invalid channel number %d", channel); + return -EINVAL; + } + + if (value >= (1 << AD559X_DAC_RESOLUTION)) { + LOG_ERR("Value %d out of range", value); + return -EINVAL; + } + + if (mfd_ad559x_has_pointer_byte_map(config->mfd_dev)) { + return mfd_ad559x_write_reg(config->mfd_dev, AD559X_DAC_WR_POINTER | channel, + value); + } else { + msg = sys_cpu_to_be16(AD559X_DAC_WR_MSB_BIT | + channel << AD559X_DAC_CHANNEL_SHIFT_VAL | value); + + return mfd_ad559x_write_raw(config->mfd_dev, (uint8_t *)&msg, sizeof(msg)); + } +} + +static const struct dac_driver_api dac_ad559x_api = { + .channel_setup = dac_ad559x_channel_setup, + .write_value = dac_ad559x_write_value, +}; + +static int dac_ad559x_init(const struct device *dev) +{ + const struct dac_ad559x_config *config = dev->config; + int ret; + + if (!device_is_ready(config->mfd_dev)) { + return -ENODEV; + } + + ret = mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_PD_REF_CTRL, AD559X_EN_REF); + if (ret < 0) { + return ret; + } + + return 0; +} + +#define DAC_AD559X_DEFINE(inst) \ + static const struct dac_ad559x_config dac_ad559x_config##inst = { \ + .mfd_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \ + }; \ + \ + struct dac_ad559x_data dac_ad559x_data##inst; \ + \ + DEVICE_DT_INST_DEFINE(inst, dac_ad559x_init, NULL, &dac_ad559x_data##inst, \ + &dac_ad559x_config##inst, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \ + &dac_ad559x_api); + +DT_INST_FOREACH_STATUS_OKAY(DAC_AD559X_DEFINE) diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 8d019f91ab1..2143d019cb7 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -4,7 +4,7 @@ zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/gpio.h) zephyr_library() -zephyr_library_sources_ifdef(CONFIG_GPIO_AD5592 gpio_ad5592.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_AD559X gpio_ad559x.c) zephyr_library_sources_ifdef(CONFIG_GPIO_AXP192 gpio_axp192.c) zephyr_library_sources_ifdef(CONFIG_GPIO_TELINK_B91 gpio_b91.c) zephyr_library_sources_ifdef(CONFIG_GPIO_INFINEON_CAT1 gpio_ifx_cat1.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index fb481cb229d..2ca6da678c3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -87,7 +87,7 @@ config GPIO_ENABLE_DISABLE_INTERRUPT pending register, etc. The driver must implement it to work. -source "drivers/gpio/Kconfig.ad5592" +source "drivers/gpio/Kconfig.ad559x" source "drivers/gpio/Kconfig.axp192" diff --git a/drivers/gpio/Kconfig.ad5592 b/drivers/gpio/Kconfig.ad5592 deleted file mode 100644 index c2654d1857b..00000000000 --- a/drivers/gpio/Kconfig.ad5592 +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Grinn -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_AD5592 - bool "AD5592 GPIO driver" - default y - depends on DT_HAS_ADI_AD5592_GPIO_ENABLED - select MFD - help - Enable the AD5592 GPIO driver. diff --git a/drivers/gpio/Kconfig.ad559x b/drivers/gpio/Kconfig.ad559x new file mode 100644 index 00000000000..68879b4884d --- /dev/null +++ b/drivers/gpio/Kconfig.ad559x @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Grinn +# SPDX-License-Identifier: Apache-2.0 + +config GPIO_AD559X + bool "AD559x GPIO driver" + default y + depends on DT_HAS_ADI_AD559X_GPIO_ENABLED + select MFD + help + Enable the AD559x GPIO driver. diff --git a/drivers/gpio/gpio_ad5592.c b/drivers/gpio/gpio_ad5592.c deleted file mode 100644 index a8b30ddcee4..00000000000 --- a/drivers/gpio/gpio_ad5592.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2023 Grinn - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT adi_ad5592_gpio - -#include -#include -#include -#include - -#include - -struct gpio_ad5592_config { - /* gpio_driver_config needs to be first */ - struct gpio_driver_config common; - const struct device *mfd_dev; -}; - -struct gpio_ad5592_data { - /* gpio_driver_data needs to be first */ - struct gpio_driver_data common; - uint8_t gpio_val; - uint8_t gpio_out; - uint8_t gpio_in; - uint8_t gpio_pull_down; -}; - -static int gpio_ad5592_port_get_raw(const struct device *dev, uint32_t *value) -{ - const struct gpio_ad5592_config *config = dev->config; - struct gpio_ad5592_data *drv_data = dev->data; - uint16_t data; - int ret; - - if (k_is_in_isr()) { - return -EWOULDBLOCK; - } - - ret = mfd_ad5592_read_reg(config->mfd_dev, - AD5592_REG_GPIO_INPUT_EN, drv_data->gpio_in, &data); - if (ret < 0) { - return ret; - } - - *value = (uint32_t)data; - - return 0; -} - -static int gpio_ad5592_port_set_bits_raw(const struct device *dev, - gpio_port_pins_t pins) -{ - struct gpio_ad5592_data *data = dev->data; - const struct gpio_ad5592_config *config = dev->config; - - if (k_is_in_isr()) { - return -EWOULDBLOCK; - } - - data->gpio_val |= (uint8_t)pins; - - return mfd_ad5592_write_reg(config->mfd_dev, AD5592_REG_GPIO_SET, data->gpio_val); -} - -static int gpio_ad5592_port_clear_bits_raw(const struct device *dev, - gpio_port_pins_t pins) -{ - struct gpio_ad5592_data *data = dev->data; - const struct gpio_ad5592_config *config = dev->config; - - if (k_is_in_isr()) { - return -EWOULDBLOCK; - } - - data->gpio_val &= ~(uint8_t)pins; - - return mfd_ad5592_write_reg(config->mfd_dev, AD5592_REG_GPIO_SET, data->gpio_val); -} - -static inline int gpio_ad5592_configure(const struct device *dev, - gpio_pin_t pin, gpio_flags_t flags) -{ - struct gpio_ad5592_data *data = dev->data; - const struct gpio_ad5592_config *config = dev->config; - uint8_t val; - int ret; - - if (k_is_in_isr()) { - return -EWOULDBLOCK; - } - - if (pin >= AD5592_PIN_MAX) { - return -EINVAL; - } - - val = BIT(pin); - if ((flags & GPIO_OUTPUT) != 0U) { - data->gpio_in &= ~val; - data->gpio_out |= val; - - if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) { - ret = gpio_ad5592_port_set_bits_raw( - dev, (gpio_port_pins_t)BIT(pin)); - if (ret < 0) { - return ret; - } - } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) { - ret = gpio_ad5592_port_clear_bits_raw( - dev, (gpio_port_pins_t)BIT(pin)); - if (ret < 0) { - return ret; - } - } - - ret = mfd_ad5592_write_reg(config->mfd_dev, - AD5592_REG_GPIO_OUTPUT_EN, data->gpio_out); - if (ret < 0) { - return ret; - } - - ret = mfd_ad5592_write_reg(config->mfd_dev, - AD5592_REG_GPIO_INPUT_EN, data->gpio_in); - } else if ((flags & GPIO_INPUT) != 0U) { - data->gpio_in |= val; - data->gpio_out &= ~val; - - if ((flags & GPIO_PULL_DOWN) != 0U) { - data->gpio_pull_down |= val; - - ret = mfd_ad5592_write_reg(config->mfd_dev, - AD5592_REG_GPIO_PULLDOWN, - data->gpio_pull_down); - if (ret < 0) { - return ret; - } - } else if ((flags & GPIO_PULL_UP) != 0U) { - return -ENOTSUP; - } - - ret = mfd_ad5592_write_reg(config->mfd_dev, - AD5592_REG_GPIO_OUTPUT_EN, data->gpio_out); - if (ret < 0) { - return ret; - } - - ret = mfd_ad5592_write_reg(config->mfd_dev, - AD5592_REG_GPIO_INPUT_EN, data->gpio_in); - } else { - return -ENOTSUP; - } - - return ret; -} - -static int gpio_ad5592_port_set_masked_raw(const struct device *dev, - gpio_port_pins_t mask, - gpio_port_value_t value) -{ - ARG_UNUSED(dev); - ARG_UNUSED(mask); - ARG_UNUSED(value); - - return -ENOTSUP; -} - -static int gpio_ad5592_port_toggle_bits(const struct device *dev, - gpio_port_pins_t pins) -{ - ARG_UNUSED(dev); - ARG_UNUSED(pins); - - return -ENOTSUP; -} - -static int gpio_ad5592_pin_interrupt_configure(const struct device *dev, - gpio_pin_t pin, - enum gpio_int_mode mode, - enum gpio_int_trig trig) -{ - ARG_UNUSED(dev); - ARG_UNUSED(pin); - ARG_UNUSED(mode); - ARG_UNUSED(trig); - - return -ENOTSUP; -} - -static const struct gpio_driver_api gpio_ad5592_api = { - .pin_configure = gpio_ad5592_configure, - .port_get_raw = gpio_ad5592_port_get_raw, - .port_set_masked_raw = gpio_ad5592_port_set_masked_raw, - .port_set_bits_raw = gpio_ad5592_port_set_bits_raw, - .port_clear_bits_raw = gpio_ad5592_port_clear_bits_raw, - .port_toggle_bits = gpio_ad5592_port_toggle_bits, - .pin_interrupt_configure = gpio_ad5592_pin_interrupt_configure, -}; - -static int gpio_ad5592_init(const struct device *dev) -{ - const struct gpio_ad5592_config *config = dev->config; - - if (!device_is_ready(config->mfd_dev)) { - return -ENODEV; - } - - return 0; -} - -#define GPIO_AD5592_DEFINE(inst) \ - static const struct gpio_ad5592_config gpio_ad5592_config##inst = { \ - .common = { \ - .port_pin_mask = \ - GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \ - }, \ - .mfd_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \ - }; \ - \ - static struct gpio_ad5592_data gpio_ad5592_data##inst; \ - \ - DEVICE_DT_INST_DEFINE(inst, gpio_ad5592_init, NULL, \ - &gpio_ad5592_data##inst, &gpio_ad5592_config##inst, \ - POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \ - &gpio_ad5592_api); - -DT_INST_FOREACH_STATUS_OKAY(GPIO_AD5592_DEFINE) diff --git a/drivers/gpio/gpio_ad559x.c b/drivers/gpio/gpio_ad559x.c new file mode 100644 index 00000000000..afa3d1be10c --- /dev/null +++ b/drivers/gpio/gpio_ad559x.c @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2023 Grinn + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT adi_ad559x_gpio + +#include +#include +#include +#include + +#include + +#define AD559X_GPIO_RD_POINTER 0x60 + +struct gpio_ad559x_config { + /* gpio_driver_config needs to be first */ + struct gpio_driver_config common; + const struct device *mfd_dev; +}; + +struct gpio_ad559x_data { + /* gpio_driver_data needs to be first */ + struct gpio_driver_data common; + uint8_t gpio_val; + uint8_t gpio_out; + uint8_t gpio_in; + uint8_t gpio_pull_down; +}; + +static int gpio_ad559x_port_get_raw(const struct device *dev, uint32_t *value) +{ + const struct gpio_ad559x_config *config = dev->config; + struct gpio_ad559x_data *drv_data = dev->data; + uint16_t data; + int ret; + + if (k_is_in_isr()) { + return -EWOULDBLOCK; + } + + if (mfd_ad559x_has_pointer_byte_map(config->mfd_dev)) { + ret = mfd_ad559x_read_reg(config->mfd_dev, AD559X_GPIO_RD_POINTER, 0, &data); + /* LSB contains port information. Clear the MSB. */ + data &= BIT_MASK(AD559X_PIN_MAX); + } else { + ret = mfd_ad559x_read_reg(config->mfd_dev, AD559X_REG_GPIO_INPUT_EN, + drv_data->gpio_in, &data); + } + + if (ret < 0) { + return ret; + } + + *value = (uint32_t)data; + + return 0; +} + +static int gpio_ad559x_port_set_bits_raw(const struct device *dev, + gpio_port_pins_t pins) +{ + struct gpio_ad559x_data *data = dev->data; + const struct gpio_ad559x_config *config = dev->config; + + if (k_is_in_isr()) { + return -EWOULDBLOCK; + } + + data->gpio_val |= (uint8_t)pins; + + return mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_GPIO_SET, data->gpio_val); +} + +static int gpio_ad559x_port_clear_bits_raw(const struct device *dev, + gpio_port_pins_t pins) +{ + struct gpio_ad559x_data *data = dev->data; + const struct gpio_ad559x_config *config = dev->config; + + if (k_is_in_isr()) { + return -EWOULDBLOCK; + } + + data->gpio_val &= ~(uint8_t)pins; + + return mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_GPIO_SET, data->gpio_val); +} + +static inline int gpio_ad559x_configure(const struct device *dev, + gpio_pin_t pin, gpio_flags_t flags) +{ + struct gpio_ad559x_data *data = dev->data; + const struct gpio_ad559x_config *config = dev->config; + uint8_t val; + int ret; + + if (k_is_in_isr()) { + return -EWOULDBLOCK; + } + + if (pin >= AD559X_PIN_MAX) { + return -EINVAL; + } + + val = BIT(pin); + if ((flags & GPIO_OUTPUT) != 0U) { + data->gpio_in &= ~val; + data->gpio_out |= val; + + if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) { + ret = gpio_ad559x_port_set_bits_raw( + dev, (gpio_port_pins_t)BIT(pin)); + if (ret < 0) { + return ret; + } + } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) { + ret = gpio_ad559x_port_clear_bits_raw( + dev, (gpio_port_pins_t)BIT(pin)); + if (ret < 0) { + return ret; + } + } + + ret = mfd_ad559x_write_reg(config->mfd_dev, + AD559X_REG_GPIO_OUTPUT_EN, data->gpio_out); + if (ret < 0) { + return ret; + } + + ret = mfd_ad559x_write_reg(config->mfd_dev, + AD559X_REG_GPIO_INPUT_EN, data->gpio_in); + } else if ((flags & GPIO_INPUT) != 0U) { + data->gpio_in |= val; + data->gpio_out &= ~val; + + if ((flags & GPIO_PULL_DOWN) != 0U) { + data->gpio_pull_down |= val; + + ret = mfd_ad559x_write_reg(config->mfd_dev, + AD559X_REG_GPIO_PULLDOWN, + data->gpio_pull_down); + if (ret < 0) { + return ret; + } + } else if ((flags & GPIO_PULL_UP) != 0U) { + return -ENOTSUP; + } + + ret = mfd_ad559x_write_reg(config->mfd_dev, + AD559X_REG_GPIO_OUTPUT_EN, data->gpio_out); + if (ret < 0) { + return ret; + } + + ret = mfd_ad559x_write_reg(config->mfd_dev, + AD559X_REG_GPIO_INPUT_EN, data->gpio_in); + } else { + return -ENOTSUP; + } + + return ret; +} + +static int gpio_ad559x_port_set_masked_raw(const struct device *dev, + gpio_port_pins_t mask, + gpio_port_value_t value) +{ + ARG_UNUSED(dev); + ARG_UNUSED(mask); + ARG_UNUSED(value); + + return -ENOTSUP; +} + +static int gpio_ad559x_port_toggle_bits(const struct device *dev, + gpio_port_pins_t pins) +{ + ARG_UNUSED(dev); + ARG_UNUSED(pins); + + return -ENOTSUP; +} + +static int gpio_ad559x_pin_interrupt_configure(const struct device *dev, + gpio_pin_t pin, + enum gpio_int_mode mode, + enum gpio_int_trig trig) +{ + ARG_UNUSED(dev); + ARG_UNUSED(pin); + ARG_UNUSED(mode); + ARG_UNUSED(trig); + + return -ENOTSUP; +} + +static const struct gpio_driver_api gpio_ad559x_api = { + .pin_configure = gpio_ad559x_configure, + .port_get_raw = gpio_ad559x_port_get_raw, + .port_set_masked_raw = gpio_ad559x_port_set_masked_raw, + .port_set_bits_raw = gpio_ad559x_port_set_bits_raw, + .port_clear_bits_raw = gpio_ad559x_port_clear_bits_raw, + .port_toggle_bits = gpio_ad559x_port_toggle_bits, + .pin_interrupt_configure = gpio_ad559x_pin_interrupt_configure, +}; + +static int gpio_ad559x_init(const struct device *dev) +{ + const struct gpio_ad559x_config *config = dev->config; + + if (!device_is_ready(config->mfd_dev)) { + return -ENODEV; + } + + return 0; +} + +#define GPIO_AD559X_DEFINE(inst) \ + static const struct gpio_ad559x_config gpio_ad559x_config##inst = { \ + .common = { \ + .port_pin_mask = \ + GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \ + }, \ + .mfd_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \ + }; \ + \ + static struct gpio_ad559x_data gpio_ad559x_data##inst; \ + \ + DEVICE_DT_INST_DEFINE(inst, gpio_ad559x_init, NULL, \ + &gpio_ad559x_data##inst, &gpio_ad559x_config##inst, \ + POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \ + &gpio_ad559x_api); + +DT_INST_FOREACH_STATUS_OKAY(GPIO_AD559X_DEFINE) diff --git a/drivers/mfd/CMakeLists.txt b/drivers/mfd/CMakeLists.txt index 135643a14a3..486d37f611d 100644 --- a/drivers/mfd/CMakeLists.txt +++ b/drivers/mfd/CMakeLists.txt @@ -8,7 +8,9 @@ zephyr_library_sources_ifdef(CONFIG_MFD_NCT38XX mfd_nct38xx.c) zephyr_library_sources_ifdef(CONFIG_MFD_NPM1300 mfd_npm1300.c) zephyr_library_sources_ifdef(CONFIG_MFD_NPM6001 mfd_npm6001.c) zephyr_library_sources_ifdef(CONFIG_MFD_AXP192 mfd_axp192.c) -zephyr_library_sources_ifdef(CONFIG_MFD_AD5592 mfd_ad5592.c) +zephyr_library_sources_ifdef(CONFIG_MFD_AD559X mfd_ad559x.c) +zephyr_library_sources_ifdef(CONFIG_MFD_AD559X_BUS_I2C mfd_ad559x_i2c.c) +zephyr_library_sources_ifdef(CONFIG_MFD_AD559X_BUS_SPI mfd_ad559x_spi.c) zephyr_library_sources_ifdef(CONFIG_MFD_MAX31790 mfd_max31790.c) zephyr_library_sources_ifdef(CONFIG_NXP_LP_FLEXCOMM mfd_nxp_lp_flexcomm.c) zephyr_library_sources_ifdef(CONFIG_MFD_BD8LB600FS mfd_bd8lb600fs.c) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 724359a8bc8..f24d9378dcd 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -18,7 +18,7 @@ config MFD_INIT_PRIORITY help Multi-function devices initialization priority. -source "drivers/mfd/Kconfig.ad5592" +source "drivers/mfd/Kconfig.ad559x" source "drivers/mfd/Kconfig.axp192" source "drivers/mfd/Kconfig.bd8lb600fs" source "drivers/mfd/Kconfig.max20335" diff --git a/drivers/mfd/Kconfig.ad5592 b/drivers/mfd/Kconfig.ad5592 deleted file mode 100644 index 8b94f5517cb..00000000000 --- a/drivers/mfd/Kconfig.ad5592 +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Grinn -# SPDX -License-Identifier: Apache-2.0 - -config MFD_AD5592 - bool "Analog AD5592 SPI configurable ADC/DAC/GPIO chip" - default y - depends on DT_HAS_ADI_AD5592_ENABLED - depends on SPI - help - Enable driver for Analog AD5592. diff --git a/drivers/mfd/Kconfig.ad559x b/drivers/mfd/Kconfig.ad559x new file mode 100644 index 00000000000..1597f60e3b2 --- /dev/null +++ b/drivers/mfd/Kconfig.ad559x @@ -0,0 +1,25 @@ +# Copyright (c) 2023 Grinn +# SPDX -License-Identifier: Apache-2.0 + +menuconfig MFD_AD559X + bool "Analog AD559x I2C/SPI configurable ADC/DAC/GPIO chip" + default y + depends on DT_HAS_ADI_AD559X_ENABLED + help + Enable driver for Analog AD5592 or Analog AD5593. + +if MFD_AD559X + +config MFD_AD559X_BUS_I2C + bool "Analog AD559x I2C bus support" + default y + depends on $(dt_compat_on_bus,$(DT_COMPAT_ADI_AD559X),i2c) + depends on I2C + +config MFD_AD559X_BUS_SPI + bool "Analog AD559x SPI bus support" + default y + depends on $(dt_compat_on_bus,$(DT_COMPAT_ADI_AD559X),spi) + depends on SPI + +endif # MFD_AD559X diff --git a/drivers/mfd/mfd_ad5592.c b/drivers/mfd/mfd_ad5592.c deleted file mode 100644 index 2c320fa549e..00000000000 --- a/drivers/mfd/mfd_ad5592.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2023 Grinn - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT adi_ad5592 - -#include -#include -#include -#include - -#include - -#define AD5592_GPIO_READBACK_EN BIT(10) -#define AD5592_LDAC_READBACK_EN BIT(6) -#define AD5592_REG_SOFTWARE_RESET 0x0FU -#define AD5592_SOFTWARE_RESET_MAGIC_VAL 0x5AC -#define AD5592_REG_VAL_MASK 0x3FF -#define AD5592_REG_RESET_VAL_MASK 0x7FF -#define AD5592_REG_SHIFT_VAL 11 -#define AD5592_REG_READBACK_SHIFT_VAL 2 - -#define AD5592_SPI_SPEC_CONF (SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \ - SPI_OP_MODE_MASTER | SPI_MODE_CPOL) - -struct mfd_ad5592_config { - struct gpio_dt_spec reset_gpio; - struct spi_dt_spec bus; -}; - -int mfd_ad5592_read_raw(const struct device *dev, uint16_t *val) -{ - const struct mfd_ad5592_config *config = dev->config; - uint16_t nop_msg = 0; - - struct spi_buf tx_buf[] = { - { - .buf = &nop_msg, - .len = sizeof(nop_msg) - } - }; - - const struct spi_buf_set tx = { - .buffers = tx_buf, - .count = 1 - }; - - struct spi_buf rx_buf[] = { - { - .buf = val, - .len = sizeof(uint16_t) - } - }; - - const struct spi_buf_set rx = { - .buffers = rx_buf, - .count = 1 - }; - - return spi_transceive_dt(&config->bus, &tx, &rx); -} - -int mfd_ad5592_write_raw(const struct device *dev, uint16_t val) -{ - const struct mfd_ad5592_config *config = dev->config; - - struct spi_buf tx_buf[] = { - { - .buf = &val, - .len = sizeof(val) - } - }; - - const struct spi_buf_set tx = { - .buffers = tx_buf, - .count = 1 - }; - - return spi_write_dt(&config->bus, &tx); -} - -int mfd_ad5592_read_reg(const struct device *dev, uint8_t reg, uint8_t reg_data, uint16_t *val) -{ - uint16_t data; - uint16_t msg; - int ret; - - switch (reg) { - case AD5592_REG_GPIO_INPUT_EN: - msg = sys_cpu_to_be16(AD5592_GPIO_READBACK_EN | - (AD5592_REG_GPIO_INPUT_EN << AD5592_REG_SHIFT_VAL) | - reg_data); - break; - default: - msg = sys_cpu_to_be16(AD5592_LDAC_READBACK_EN | - (AD5592_REG_READ_AND_LDAC << AD5592_REG_SHIFT_VAL) | - reg << AD5592_REG_READBACK_SHIFT_VAL); - break; - } - - ret = mfd_ad5592_write_raw(dev, msg); - if (ret < 0) { - return ret; - } - - ret = mfd_ad5592_read_raw(dev, &data); - if (ret < 0) { - return ret; - } - - *val = sys_be16_to_cpu(data); - - return 0; -} - -int mfd_ad5592_write_reg(const struct device *dev, uint8_t reg, uint16_t val) -{ - uint16_t write_mask; - uint16_t msg; - - switch (reg) { - case AD5592_REG_SOFTWARE_RESET: - write_mask = AD5592_REG_RESET_VAL_MASK; - break; - default: - write_mask = AD5592_REG_VAL_MASK; - break; - } - - msg = sys_cpu_to_be16((reg << AD5592_REG_SHIFT_VAL) | (val & write_mask)); - - return mfd_ad5592_write_raw(dev, msg); -} - -static int mfd_add592_software_reset(const struct device *dev) -{ - return mfd_ad5592_write_reg(dev, - AD5592_REG_SOFTWARE_RESET, - AD5592_SOFTWARE_RESET_MAGIC_VAL); -} - -static int mfd_ad5592_init(const struct device *dev) -{ - const struct mfd_ad5592_config *config = dev->config; - int ret; - - if (!spi_is_ready_dt(&config->bus)) { - return -ENODEV; - } - - if (!gpio_is_ready_dt(&config->reset_gpio)) { - return -ENODEV; - } - - ret = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_INACTIVE); - if (ret < 0) { - return ret; - } - - ret = mfd_add592_software_reset(dev); - if (ret < 0) { - return ret; - } - - return 0; -} - -#define MFD_AD5592_DEFINE(inst) \ - static const struct mfd_ad5592_config mfd_ad5592_config_##inst = { \ - .reset_gpio = GPIO_DT_SPEC_INST_GET(inst, reset_gpios), \ - .bus = SPI_DT_SPEC_INST_GET(inst, AD5592_SPI_SPEC_CONF, 0), \ - }; \ - \ - DEVICE_DT_INST_DEFINE(inst, mfd_ad5592_init, NULL, \ - NULL, \ - &mfd_ad5592_config_##inst, \ - POST_KERNEL, \ - CONFIG_MFD_INIT_PRIORITY, \ - NULL); - -DT_INST_FOREACH_STATUS_OKAY(MFD_AD5592_DEFINE); diff --git a/drivers/mfd/mfd_ad559x.c b/drivers/mfd/mfd_ad559x.c new file mode 100644 index 00000000000..1d298e8edae --- /dev/null +++ b/drivers/mfd/mfd_ad559x.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2023 Grinn + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT adi_ad559x + +#include +#include +#include + +#include + +#include "mfd_ad559x.h" + +bool mfd_ad559x_has_pointer_byte_map(const struct device *dev) +{ + const struct mfd_ad559x_config *config = dev->config; + + return config->has_pointer_byte_map; +} + +int mfd_ad559x_read_raw(const struct device *dev, uint8_t *val, size_t len) +{ + struct mfd_ad559x_data *data = dev->data; + + return data->transfer_function->read_raw(dev, val, len); +} + +int mfd_ad559x_write_raw(const struct device *dev, uint8_t *val, size_t len) +{ + struct mfd_ad559x_data *data = dev->data; + + return data->transfer_function->write_raw(dev, val, len); +} + +int mfd_ad559x_read_reg(const struct device *dev, uint8_t reg, uint8_t reg_data, uint16_t *val) +{ + struct mfd_ad559x_data *data = dev->data; + + return data->transfer_function->read_reg(dev, reg, reg_data, val); +} + +int mfd_ad559x_write_reg(const struct device *dev, uint8_t reg, uint16_t val) +{ + struct mfd_ad559x_data *data = dev->data; + + return data->transfer_function->write_reg(dev, reg, val); +} + +static int mfd_add559x_software_reset(const struct device *dev) +{ + return mfd_ad559x_write_reg(dev, AD559X_REG_SOFTWARE_RESET, + AD559X_SOFTWARE_RESET_MAGIC_VAL); +} + +static int mfd_ad559x_init(const struct device *dev) +{ + const struct mfd_ad559x_config *config = dev->config; + int ret; + + ret = config->bus_init(dev); + if (ret < 0) { + return ret; + } + + if (!gpio_is_ready_dt(&config->reset_gpio)) { + return -ENODEV; + } + + ret = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_INACTIVE); + if (ret < 0) { + return ret; + } + + ret = mfd_add559x_software_reset(dev); + if (ret < 0) { + return ret; + } + + return 0; +} + +#define MDF_AD559X_DEFINE_I2C_BUS(inst) \ + .i2c = I2C_DT_SPEC_INST_GET(inst), .bus_init = mfd_ad559x_i2c_init, \ + .has_pointer_byte_map = true + +#define MDF_AD559X_DEFINE_SPI_BUS_FLAGS \ + (SPI_WORD_SET(8) | SPI_TRANSFER_MSB | SPI_OP_MODE_MASTER | SPI_MODE_CPOL) + +#define MDF_AD559X_DEFINE_SPI_BUS(inst) \ + .spi = SPI_DT_SPEC_INST_GET(inst, MDF_AD559X_DEFINE_SPI_BUS_FLAGS, 0), \ + .bus_init = mfd_ad559x_spi_init, .has_pointer_byte_map = false + +#define MFD_AD559X_DEFINE_BUS(inst) \ + COND_CODE_1(DT_INST_ON_BUS(inst, i2c), (MDF_AD559X_DEFINE_I2C_BUS(inst)), \ + (MDF_AD559X_DEFINE_SPI_BUS(inst))) + +#define MFD_AD559X_DEFINE(inst) \ + static struct mfd_ad559x_data mfd_ad559x_data_##inst; \ + static const struct mfd_ad559x_config mfd_ad559x_config_##inst = { \ + .reset_gpio = GPIO_DT_SPEC_INST_GET(inst, reset_gpios), \ + MFD_AD559X_DEFINE_BUS(inst), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(inst, mfd_ad559x_init, NULL, &mfd_ad559x_data_##inst, \ + &mfd_ad559x_config_##inst, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \ + NULL); + +DT_INST_FOREACH_STATUS_OKAY(MFD_AD559X_DEFINE); diff --git a/drivers/mfd/mfd_ad559x.h b/drivers/mfd/mfd_ad559x.h new file mode 100644 index 00000000000..feea3db0708 --- /dev/null +++ b/drivers/mfd/mfd_ad559x.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024 Vitrolife A/S + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_MFD_AD559X_H_ +#define ZEPHYR_DRIVERS_MFD_AD559X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define DT_DRV_COMPAT adi_ad559x + +#include +#include + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ + +#define AD559X_GPIO_READBACK_EN BIT(10) +#define AD559X_LDAC_READBACK_EN BIT(6) +#define AD559X_REG_SOFTWARE_RESET 0x0FU +#define AD559X_SOFTWARE_RESET_MAGIC_VAL 0x5AC +#define AD559X_REG_VAL_MASK 0x3FF +#define AD559X_REG_RESET_VAL_MASK 0x7FF +#define AD559X_REG_SHIFT_VAL 11 +#define AD559X_REG_READBACK_SHIFT_VAL 2 + +struct mfd_ad559x_transfer_function { + int (*read_raw)(const struct device *dev, uint8_t *val, size_t len); + int (*write_raw)(const struct device *dev, uint8_t *val, size_t len); + int (*read_reg)(const struct device *dev, uint8_t reg, uint8_t reg_data, uint16_t *val); + int (*write_reg)(const struct device *dev, uint8_t reg, uint16_t val); +}; + +struct mfd_ad559x_config { + struct gpio_dt_spec reset_gpio; +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) + struct i2c_dt_spec i2c; +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) + struct spi_dt_spec spi; +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ + int (*bus_init)(const struct device *dev); + bool has_pointer_byte_map; +}; + +struct mfd_ad559x_data { + const struct mfd_ad559x_transfer_function *transfer_function; +}; + +int mfd_ad559x_i2c_init(const struct device *dev); +int mfd_ad559x_spi_init(const struct device *dev); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_DRIVERS_MFD_AD559X_H_*/ diff --git a/drivers/mfd/mfd_ad559x_i2c.c b/drivers/mfd/mfd_ad559x_i2c.c new file mode 100644 index 00000000000..a18ecbc1423 --- /dev/null +++ b/drivers/mfd/mfd_ad559x_i2c.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2024, Vitrolife A/S + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include +#include + +#include "mfd_ad559x.h" + +static int mfd_ad559x_i2c_read_raw(const struct device *dev, uint8_t *val, size_t len) +{ + const struct mfd_ad559x_config *config = dev->config; + + return i2c_read_dt(&config->i2c, val, len); +} + +static int mfd_ad559x_i2c_write_raw(const struct device *dev, uint8_t *val, size_t len) +{ + const struct mfd_ad559x_config *config = dev->config; + + return i2c_write_dt(&config->i2c, val, len); +} + +static int mfd_ad559x_i2c_read_reg(const struct device *dev, uint8_t reg, uint8_t reg_data, + uint16_t *val) +{ + const struct mfd_ad559x_config *config = dev->config; + uint8_t buf[sizeof(*val)]; + int ret; + + ARG_UNUSED(reg_data); + + __ASSERT((reg & 0xf0) == 0, "reg bits [7:4] should be 0: 0x%x", reg); + + ret = i2c_write_read_dt(&config->i2c, ®, sizeof(reg), buf, sizeof(buf)); + if (ret < 0) { + return ret; + } + + *val = sys_get_be16(buf); + + return 0; +} + +static int mfd_ad559x_i2c_write_reg(const struct device *dev, uint8_t reg, uint16_t val) +{ + uint8_t buf[sizeof(reg) + sizeof(val)]; + + buf[0] = reg; + sys_put_be16(val, &buf[1]); + + return mfd_ad559x_i2c_write_raw(dev, buf, sizeof(buf)); +} + +static const struct mfd_ad559x_transfer_function mfd_ad559x_i2c_transfer_function = { + .read_raw = mfd_ad559x_i2c_read_raw, + .write_raw = mfd_ad559x_i2c_write_raw, + .read_reg = mfd_ad559x_i2c_read_reg, + .write_reg = mfd_ad559x_i2c_write_reg, +}; + +int mfd_ad559x_i2c_init(const struct device *dev) +{ + const struct mfd_ad559x_config *config = dev->config; + struct mfd_ad559x_data *data = dev->data; + + data->transfer_function = &mfd_ad559x_i2c_transfer_function; + + if (!i2c_is_ready_dt(&config->i2c)) { + return -ENODEV; + } + + return 0; +} diff --git a/drivers/mfd/mfd_ad559x_spi.c b/drivers/mfd/mfd_ad559x_spi.c new file mode 100644 index 00000000000..60b0b58fc61 --- /dev/null +++ b/drivers/mfd/mfd_ad559x_spi.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2023 Grinn + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include + +#include "mfd_ad559x.h" + +static int mfd_ad559x_spi_read_raw(const struct device *dev, uint8_t *val, size_t len) +{ + const struct mfd_ad559x_config *config = dev->config; + uint16_t nop_msg = 0; + + struct spi_buf tx_buf[] = {{.buf = &nop_msg, .len = sizeof(nop_msg)}}; + + const struct spi_buf_set tx = {.buffers = tx_buf, .count = 1}; + + struct spi_buf rx_buf[] = {{.buf = val, .len = len}}; + + const struct spi_buf_set rx = {.buffers = rx_buf, .count = 1}; + + return spi_transceive_dt(&config->spi, &tx, &rx); +} + +static int mfd_ad559x_spi_write_raw(const struct device *dev, uint8_t *val, size_t len) +{ + const struct mfd_ad559x_config *config = dev->config; + + struct spi_buf tx_buf[] = {{.buf = val, .len = len}}; + + const struct spi_buf_set tx = {.buffers = tx_buf, .count = 1}; + + return spi_write_dt(&config->spi, &tx); +} + +static int mfd_ad559x_spi_read_reg(const struct device *dev, uint8_t reg, uint8_t reg_data, + uint16_t *val) +{ + uint16_t data; + uint16_t msg; + int ret; + + switch (reg) { + case AD559X_REG_GPIO_INPUT_EN: + msg = sys_cpu_to_be16(AD559X_GPIO_READBACK_EN | + (AD559X_REG_GPIO_INPUT_EN << AD559X_REG_SHIFT_VAL) | + reg_data); + break; + default: + msg = sys_cpu_to_be16(AD559X_LDAC_READBACK_EN | + (AD559X_REG_READ_AND_LDAC << AD559X_REG_SHIFT_VAL) | + reg << AD559X_REG_READBACK_SHIFT_VAL); + break; + } + + ret = mfd_ad559x_spi_write_raw(dev, (uint8_t *)&msg, sizeof(msg)); + if (ret < 0) { + return ret; + } + + ret = mfd_ad559x_spi_read_raw(dev, (uint8_t *)&data, sizeof(data)); + if (ret < 0) { + return ret; + } + + *val = sys_be16_to_cpu(data); + + return 0; +} + +static int mfd_ad559x_spi_write_reg(const struct device *dev, uint8_t reg, uint16_t val) +{ + uint16_t write_mask; + uint16_t msg; + + switch (reg) { + case AD559X_REG_SOFTWARE_RESET: + write_mask = AD559X_REG_RESET_VAL_MASK; + break; + default: + write_mask = AD559X_REG_VAL_MASK; + break; + } + + msg = sys_cpu_to_be16((reg << AD559X_REG_SHIFT_VAL) | (val & write_mask)); + + return mfd_ad559x_spi_write_raw(dev, (uint8_t *)&msg, sizeof(msg)); +} + +static const struct mfd_ad559x_transfer_function mfd_ad559x_spi_transfer_function = { + .read_raw = mfd_ad559x_spi_read_raw, + .write_raw = mfd_ad559x_spi_write_raw, + .read_reg = mfd_ad559x_spi_read_reg, + .write_reg = mfd_ad559x_spi_write_reg, +}; + +int mfd_ad559x_spi_init(const struct device *dev) +{ + const struct mfd_ad559x_config *config = dev->config; + struct mfd_ad559x_data *data = dev->data; + + data->transfer_function = &mfd_ad559x_spi_transfer_function; + + if (!spi_is_ready_dt(&config->spi)) { + return -ENODEV; + } + + return 0; +} diff --git a/dts/bindings/adc/adi,ad5592-adc.yaml b/dts/bindings/adc/adi,ad559x-adc.yaml similarity index 73% rename from dts/bindings/adc/adi,ad5592-adc.yaml rename to dts/bindings/adc/adi,ad559x-adc.yaml index 2432b55d25a..6dc71d8598f 100644 --- a/dts/bindings/adc/adi,ad5592-adc.yaml +++ b/dts/bindings/adc/adi,ad559x-adc.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2023 Grinn # SPDX-License-Identifier: Apache-2.0 -description: AD5592 ADC Controller +description: AD559x ADC Controller -compatible: "adi,ad5592-adc" +compatible: "adi,ad559x-adc" include: adc-controller.yaml diff --git a/dts/bindings/dac/adi,ad5592-dac.yaml b/dts/bindings/dac/adi,ad559x-dac.yaml similarity index 73% rename from dts/bindings/dac/adi,ad5592-dac.yaml rename to dts/bindings/dac/adi,ad559x-dac.yaml index 3ac8087b91d..43cb0aed29d 100644 --- a/dts/bindings/dac/adi,ad5592-dac.yaml +++ b/dts/bindings/dac/adi,ad559x-dac.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2023 Grinn # SPDX-License-Identifier: Apache-2.0 -description: AD5592 DAC Controller +description: AD559x DAC Controller -compatible: "adi,ad5592-dac" +compatible: "adi,ad559x-dac" include: dac-controller.yaml diff --git a/dts/bindings/gpio/adi,ad5592-gpio.yaml b/dts/bindings/gpio/adi,ad559x-gpio.yaml similarity index 66% rename from dts/bindings/gpio/adi,ad5592-gpio.yaml rename to dts/bindings/gpio/adi,ad559x-gpio.yaml index b815f557c51..1588a587bf5 100644 --- a/dts/bindings/gpio/adi,ad5592-gpio.yaml +++ b/dts/bindings/gpio/adi,ad559x-gpio.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2023 Grinn # SPDX-License-Identifier: Apache-2.0 -description: AD5592 GPIO Controller +description: AD559x GPIO Controller -compatible: "adi,ad5592-gpio" +compatible: "adi,ad559x-gpio" include: gpio-controller.yaml diff --git a/dts/bindings/mfd/adi,ad5592.yaml b/dts/bindings/mfd/adi,ad559x-common.yaml similarity index 59% rename from dts/bindings/mfd/adi,ad5592.yaml rename to dts/bindings/mfd/adi,ad559x-common.yaml index d3e404ec143..0d41a6fefb5 100644 --- a/dts/bindings/mfd/adi,ad5592.yaml +++ b/dts/bindings/mfd/adi,ad559x-common.yaml @@ -1,11 +1,7 @@ # Copyright (C) 2023 Grinn # SPDX-License-Identifier: Apache-2.0 -description: Analog AD5592 ADC/DAC/GPIO chip - -compatible: "adi,ad5592" - -include: spi-device.yaml +description: Analog AD559x ADC/DAC/GPIO chip common properties properties: reset-gpios: diff --git a/dts/bindings/mfd/adi,ad559x-i2c.yaml b/dts/bindings/mfd/adi,ad559x-i2c.yaml new file mode 100644 index 00000000000..0a43eac86b5 --- /dev/null +++ b/dts/bindings/mfd/adi,ad559x-i2c.yaml @@ -0,0 +1,8 @@ +# Copyright (C) 2024, Vitrolife A/S +# SPDX-License-Identifier: Apache-2.0 + +description: Analog AD559X ADC/DAC/GPIO chip via I2C bus + +compatible: "adi,ad559x" + +include: [i2c-device.yaml, "adi,ad559x-common.yaml"] diff --git a/dts/bindings/mfd/adi,ad559x-spi.yaml b/dts/bindings/mfd/adi,ad559x-spi.yaml new file mode 100644 index 00000000000..bc6ee3cec95 --- /dev/null +++ b/dts/bindings/mfd/adi,ad559x-spi.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2024, Vitrolife A/S +# SPDX-License-Identifier: Apache-2.0 + +description: Analog AD559X ADC/DAC/GPIO chip via SPI bus + +compatible: "adi,ad559x" + +include: [spi-device.yaml, "adi,ad559x-common.yaml"] diff --git a/include/zephyr/drivers/mfd/ad5592.h b/include/zephyr/drivers/mfd/ad5592.h deleted file mode 100644 index 014ccdd02ba..00000000000 --- a/include/zephyr/drivers/mfd/ad5592.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2023 Grinn - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_AD5592_H_ -#define ZEPHYR_INCLUDE_DRIVERS_MFD_AD5592_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define AD5592_REG_SEQ_ADC 0x02U -#define AD5592_REG_ADC_CONFIG 0x04U -#define AD5592_REG_LDAC_EN 0x05U -#define AD5592_REG_GPIO_PULLDOWN 0x06U -#define AD5592_REG_READ_AND_LDAC 0x07U -#define AD5592_REG_GPIO_OUTPUT_EN 0x08U -#define AD5592_REG_GPIO_SET 0x09U -#define AD5592_REG_GPIO_INPUT_EN 0x0AU -#define AD5592_REG_PD_REF_CTRL 0x0BU - -#define AD5592_EN_REF BIT(9) - -#define AD5592_PIN_MAX 8U - -/** - * @defgroup mdf_interface_ad5592 MFD AD5592 interface - * @ingroup mfd_interfaces - * @{ - */ - -/** - * @brief Read raw data from the chip - * - * @param[in] dev Pointer to MFD device - * @param[in] val Pointer to data buffer - * - * @retval 0 if success - * @retval negative errno if failure - */ -int mfd_ad5592_read_raw(const struct device *dev, uint16_t *val); - -/** - * @brief Write raw data to chip - * - * @param[in] dev Pointer to MFD device - * @param[in] val Data to be written - * - * - * @retval 0 if success - * @retval negative errno if failure - */ -int mfd_ad5592_write_raw(const struct device *dev, uint16_t val); - -/** - * @brief Read data from provided register - * - * @param[in] dev Pointer to MFD device - * @param[in] reg Register to be read - * @param[in] reg_data Additional data passed to selected register - * @param[in] val Pointer to data buffer - * - * @retval 0 if success - * @retval negative errno if failure - */ -int mfd_ad5592_read_reg(const struct device *dev, uint8_t reg, uint8_t reg_data, uint16_t *val); - -/** - * @brief Write data to provided register - * - * @param[in] dev Pointer to MFD device - * @param[in] reg Register to be written - * @param[in] val Data to be written - * - * @retval 0 if success - * @retval negative errno if failure - */ -int mfd_ad5592_write_reg(const struct device *dev, uint8_t reg, uint16_t val); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_AD5952_H_ */ diff --git a/include/zephyr/drivers/mfd/ad559x.h b/include/zephyr/drivers/mfd/ad559x.h new file mode 100644 index 00000000000..095cdd3e622 --- /dev/null +++ b/include/zephyr/drivers/mfd/ad559x.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2023 Grinn + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_AD559X_H_ +#define ZEPHYR_INCLUDE_DRIVERS_MFD_AD559X_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define AD559X_REG_SEQ_ADC 0x02U +#define AD559X_REG_ADC_CONFIG 0x04U +#define AD559X_REG_LDAC_EN 0x05U +#define AD559X_REG_GPIO_PULLDOWN 0x06U +#define AD559X_REG_READ_AND_LDAC 0x07U +#define AD559X_REG_GPIO_OUTPUT_EN 0x08U +#define AD559X_REG_GPIO_SET 0x09U +#define AD559X_REG_GPIO_INPUT_EN 0x0AU +#define AD559X_REG_PD_REF_CTRL 0x0BU + +#define AD559X_EN_REF BIT(9) + +#define AD559X_PIN_MAX 8U + +/** + * @defgroup mdf_interface_ad559x MFD AD559X interface + * @ingroup mfd_interfaces + * @{ + */ + +/** + * @brief Check if the chip has a pointer byte map + * + * @param[in] dev Pointer to MFD device + * + * @retval true if chip has a pointer byte map, false if it has normal register map + */ +bool mfd_ad559x_has_pointer_byte_map(const struct device *dev); + +/** + * @brief Read raw data from the chip + * + * @param[in] dev Pointer to MFD device + * @param[in] val Pointer to data buffer + * @param[in] len Number of bytes to be read + * + * @retval 0 if success + * @retval negative errno if failure + */ +int mfd_ad559x_read_raw(const struct device *dev, uint8_t *val, size_t len); + +/** + * @brief Write raw data to chip + * + * @param[in] dev Pointer to MFD device + * @param[in] val Data to be written + * @param[in] len Number of bytes to be written + * + * @retval 0 if success + * @retval negative errno if failure + */ +int mfd_ad559x_write_raw(const struct device *dev, uint8_t *val, size_t len); + +/** + * @brief Read data from provided register + * + * @param[in] dev Pointer to MFD device + * @param[in] reg Register to be read + * @param[in] reg_data Additional data passed to selected register + * @param[in] val Pointer to data buffer + * + * @retval 0 if success + * @retval negative errno if failure + */ +int mfd_ad559x_read_reg(const struct device *dev, uint8_t reg, uint8_t reg_data, uint16_t *val); + +/** + * @brief Write data to provided register + * + * @param[in] dev Pointer to MFD device + * @param[in] reg Register to be written + * @param[in] val Data to be written + * + * @retval 0 if success + * @retval negative errno if failure + */ +int mfd_ad559x_write_reg(const struct device *dev, uint8_t reg, uint16_t val); + +/** + * @brief Read ADC channel data from the chip + * + * @param[in] dev Pointer to MFD device + * @param[in] channel Channel to read + * @param[out] result ADC channel value read + * + * @retval 0 if success + * @retval negative errno if failure + */ +int mfd_ad559x_read_adc_chan(const struct device *dev, uint8_t channel, uint16_t *result); + +/** + * @brief Write ADC channel data to the chip + * + * @param[in] dev Pointer to MFD device + * @param[in] channel Channel to write to + * @param[in] value DAC channel value + * + * @retval 0 if success + * @retval negative errno if failure + */ +int mfd_ad559x_write_dac_chan(const struct device *dev, uint8_t channel, uint16_t value); + +/** + * @brief Read GPIO port from the chip + * + * @param[in] dev Pointer to MFD device + * @param[in] gpio GPIO to read + * @param[in] value DAC channel value + * + * @retval 0 if success + * @retval negative errno if failure + */ +int mfd_ad559x_gpio_port_get_raw(const struct device *dev, uint8_t gpio, uint16_t *value); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_AD559X_H_ */ diff --git a/tests/drivers/build_all/adc/boards/native_sim.overlay b/tests/drivers/build_all/adc/boards/native_sim.overlay index ff4f0702b68..e06e9504860 100644 --- a/tests/drivers/build_all/adc/boards/native_sim.overlay +++ b/tests/drivers/build_all/adc/boards/native_sim.overlay @@ -315,15 +315,15 @@ #io-channel-cells = <1>; }; - test_spi_ad5592: ad5592@16 { - compatible = "adi,ad5592"; + test_spi_ad559x: ad559x@16 { + compatible = "adi,ad559x"; status = "okay"; reg = <0x16>; spi-max-frequency = <0>; reset-gpios = <&test_gpio 0 0>; - ad5592_adc: adc-controller { - compatible = "adi,ad5592-adc"; + ad559x_adc: adc-controller { + compatible = "adi,ad559x-adc"; #io-channel-cells = <1>; }; }; diff --git a/tests/drivers/build_all/dac/app.overlay b/tests/drivers/build_all/dac/app.overlay index 9767e3b9616..df5cf7a40ad 100644 --- a/tests/drivers/build_all/dac/app.overlay +++ b/tests/drivers/build_all/dac/app.overlay @@ -235,15 +235,15 @@ reset-gpios = <&test_gpio 0 0>; }; - test_spi_ad5592: ad5592@10 { - compatible = "adi,ad5592"; + test_spi_ad559x: ad559x@10 { + compatible = "adi,ad559x"; status = "okay"; reg = <0x10>; spi-max-frequency = <0>; reset-gpios = <&test_gpio 0 0>; - ad5592_dac: dac-controller { - compatible = "adi,ad5592-dac"; + ad559x_dac: dac-controller { + compatible = "adi,ad559x-dac"; #io-channel-cells = <1>; }; }; diff --git a/tests/drivers/build_all/gpio/app.overlay b/tests/drivers/build_all/gpio/app.overlay index b594214586a..73689fb6c91 100644 --- a/tests/drivers/build_all/gpio/app.overlay +++ b/tests/drivers/build_all/gpio/app.overlay @@ -268,15 +268,15 @@ }; }; - test_spi_ad5592: ad5592@3 { - compatible = "adi,ad5592"; + test_spi_ad559x: ad559x@3 { + compatible = "adi,ad559x"; status = "okay"; reg = <0x03>; spi-max-frequency = <0>; reset-gpios = <&test_gpio 0 0>; - ad5592_gpio: gpio-controller { - compatible = "adi,ad5592-gpio"; + ad559x_gpio: gpio-controller { + compatible = "adi,ad559x-gpio"; gpio-controller; #gpio-cells = <2>; ngpios = <8>; From 128e8059d29221b0efecc8d6e224e6576dbe0acf Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Fri, 26 Jan 2024 13:22:18 +0100 Subject: [PATCH 1681/2402] tests: drivers: build_all: add build test for ad559x i2c driver Add build-only test of the ad559x I2C based ADC, DAC and GPIO driver. Signed-off-by: Jeppe Odgaard --- .../build_all/adc/boards/native_sim.overlay | 15 ++++++++++++++- tests/drivers/build_all/dac/app.overlay | 14 +++++++++++++- tests/drivers/build_all/gpio/app.overlay | 16 +++++++++++++++- 3 files changed, 42 insertions(+), 3 deletions(-) diff --git a/tests/drivers/build_all/adc/boards/native_sim.overlay b/tests/drivers/build_all/adc/boards/native_sim.overlay index e06e9504860..b53924d0c8a 100644 --- a/tests/drivers/build_all/adc/boards/native_sim.overlay +++ b/tests/drivers/build_all/adc/boards/native_sim.overlay @@ -94,6 +94,19 @@ conversion-speed = <60>; #io-channel-cells = <1>; }; + + test_i2c_ad559x: ad559x@9 { + compatible = "adi,ad559x"; + status = "okay"; + reg = <0x9>; + #io-channel-cells = <1>; + reset-gpios = <&test_gpio 0 0>; + + test_i2c_ad559x_adc: adc-controller { + compatible = "adi,ad559x-adc"; + #io-channel-cells = <1>; + }; + }; }; test_spi: spi@33334444 { @@ -322,7 +335,7 @@ spi-max-frequency = <0>; reset-gpios = <&test_gpio 0 0>; - ad559x_adc: adc-controller { + test_spi_ad559x_adc: adc-controller { compatible = "adi,ad559x-adc"; #io-channel-cells = <1>; }; diff --git a/tests/drivers/build_all/dac/app.overlay b/tests/drivers/build_all/dac/app.overlay index df5cf7a40ad..8f7c91819ac 100644 --- a/tests/drivers/build_all/dac/app.overlay +++ b/tests/drivers/build_all/dac/app.overlay @@ -43,6 +43,18 @@ #io-channel-cells = <1>; }; + test_i2c_ad559x: ad559x@3 { + compatible = "adi,ad559x"; + status = "okay"; + reg = <0x3>; + reset-gpios = <&test_gpio 0 0>; + + test_i2c_ad559x_dac: dac-controller { + compatible = "adi,ad559x-dac"; + #io-channel-cells = <1>; + }; + }; + test_i2c_mcp4725: mcp4725@60 { compatible = "microchip,mcp4725"; reg = <0x60>; @@ -242,7 +254,7 @@ spi-max-frequency = <0>; reset-gpios = <&test_gpio 0 0>; - ad559x_dac: dac-controller { + test_spi_ad559x_dac: dac-controller { compatible = "adi,ad559x-dac"; #io-channel-cells = <1>; }; diff --git a/tests/drivers/build_all/gpio/app.overlay b/tests/drivers/build_all/gpio/app.overlay index 73689fb6c91..ce6b91e5027 100644 --- a/tests/drivers/build_all/gpio/app.overlay +++ b/tests/drivers/build_all/gpio/app.overlay @@ -210,6 +210,20 @@ ngpios = <6>; }; }; + + test_i2c_ad559x: ad559x@e { + compatible = "adi,ad559x"; + status = "okay"; + reg = <0x0e>; + reset-gpios = <&test_gpio 0 0>; + + test_i2c_ad559x_gpio: gpio-controller { + compatible = "adi,ad559x-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; }; nct3807_alert_1 { @@ -275,7 +289,7 @@ spi-max-frequency = <0>; reset-gpios = <&test_gpio 0 0>; - ad559x_gpio: gpio-controller { + test_spi_ad559x_gpio: gpio-controller { compatible = "adi,ad559x-gpio"; gpio-controller; #gpio-cells = <2>; From b95e29abd8c4cbaead092833e8aa784ede90b79b Mon Sep 17 00:00:00 2001 From: cyliang tw Date: Mon, 1 Apr 2024 14:36:48 +0800 Subject: [PATCH 1682/2402] soc: nuvoton: numaker: disable DWT in Kconfig Timing function need Cycle Count Register CYCCNT of DWT, but Arm-Cortex-M23 only support DWT_CTRL, DWT_PCSR and DWT_COMP & DWT_FUNCTION registers. It can't meet the requirement of timing function, so to remove CPU_CORTEX_M_HAS_DWT. Signed-off-by: cyliang tw --- soc/nuvoton/numaker/m2l31x/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/soc/nuvoton/numaker/m2l31x/Kconfig b/soc/nuvoton/numaker/m2l31x/Kconfig index 04b7eba5765..58d30415e12 100644 --- a/soc/nuvoton/numaker/m2l31x/Kconfig +++ b/soc/nuvoton/numaker/m2l31x/Kconfig @@ -6,7 +6,6 @@ config SOC_SERIES_M2L31X select ARM select CPU_CORTEX_M23 select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_VTOR select CPU_HAS_ARM_MPU From 11ddb268e0388c9764846436029a4f394a216cb4 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Mon, 25 Mar 2024 16:26:52 -0500 Subject: [PATCH 1683/2402] boards: adi: Add temp sensor devicetree alias to adi_eval_adin1110ebz Adds a devicetree alias to the ambient temperature sensor on adi_eval_adin1110ebz to support the thermometer sensor sample application. Signed-off-by: Maureen Helm --- boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts index 5aa554d3748..00f00777a23 100644 --- a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts +++ b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts @@ -55,6 +55,7 @@ led0 = &green_led; watchdog0 = &iwdg; spi-flash0 = &mx25r6435f; + ambient-temp0 = &adt7420; }; soc { @@ -181,7 +182,7 @@ status = "okay"; clock-frequency = ; - adt7420@48 { + adt7420: adt7420@48 { compatible = "adi,adt7420"; reg = <0x48>; }; From 3f218c6cdae07a64e2069010cb2493d1bcbdb784 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Mon, 25 Mar 2024 16:42:04 -0500 Subject: [PATCH 1684/2402] samples: sensor: Relax twister constraints on thermometer sample The thermometer sensor sample application can support any board that defines the `ambient-temp0` devicetree alias, but the restrictive `platform_allow` list prevented twister from running on all but two selected boards. Use a more flexible `dt_alias_exists` filter instead to allow running this sample on additional boards. Signed-off-by: Maureen Helm --- samples/sensor/thermometer/sample.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/samples/sensor/thermometer/sample.yaml b/samples/sensor/thermometer/sample.yaml index 8acb9f72576..168c8ffc74b 100644 --- a/samples/sensor/thermometer/sample.yaml +++ b/samples/sensor/thermometer/sample.yaml @@ -4,6 +4,9 @@ tests: sample.sensor.thermometer: tags: sensors harness: sensor + filter: dt_alias_exists("ambient-temp0") integration_platforms: - - nrf52840dk/nrf52840 - platform_allow: nrf52840dk/nrf52840 frdm_k22f + - nrf52840dk/nrf52840 # mcp9700a + - frdm_k22f # tcn75a + - robokit1 # ntc_thermistor + - adi_eval_adin1110ebz # adt7420 From 49be50c8ddc07574fe846906f24858a2a90b03f3 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 28 Mar 2024 07:45:46 +0900 Subject: [PATCH 1685/2402] samples: drivers: led_strip: Correcting document title to 'LED strip' Other samples do not include 'sample' in the page title, so following that. Signed-off-by: TOKITA Hiroshi --- samples/drivers/led_strip/README.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/samples/drivers/led_strip/README.rst b/samples/drivers/led_strip/README.rst index 7efadc1b85c..a6b00327926 100644 --- a/samples/drivers/led_strip/README.rst +++ b/samples/drivers/led_strip/README.rst @@ -1,5 +1,5 @@ .. zephyr:code-sample:: led-strip - :name: LED strip sample + :name: LED strip :relevant-api: led_strip_interface Control an LED strip example. From ebb503ff7b44431c7de88cda7ca17936959aec5e Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 7 Mar 2024 18:00:45 -0500 Subject: [PATCH 1686/2402] kernel: move thread related helper function kthread.h Move some helper functions to inernal kthread.h, to offload crowded sched.c Signed-off-by: Anas Nashif --- kernel/include/ksched.h | 124 +----------- kernel/include/kthread.h | 190 ++++++++++++++++++ kernel/mailbox.c | 1 + kernel/mutex.c | 1 + kernel/sched.c | 62 ------ tests/kernel/threads/thread_apis/src/main.c | 3 + .../thread_apis/src/test_essential_thread.c | 1 + 7 files changed, 198 insertions(+), 184 deletions(-) diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index 74e4bc9f119..253d588aff6 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -52,7 +53,7 @@ void z_unpend_thread(struct k_thread *thread); int z_unpend_all(_wait_q_t *wait_q); bool z_thread_prio_set(struct k_thread *thread, int prio); void *z_get_next_switch_handle(void *interrupted); -void idle(void *unused1, void *unused2, void *unused3); + void z_time_slice(void); void z_reset_time_slice(struct k_thread *curr); void z_sched_abort(struct k_thread *thread); @@ -68,127 +69,6 @@ static inline void z_reschedule_unlocked(void) (void) z_reschedule_irqlock(arch_irq_lock()); } -static inline bool z_is_idle_thread_entry(void *entry_point) -{ - return entry_point == idle; -} - -static inline bool z_is_idle_thread_object(struct k_thread *thread) -{ -#ifdef CONFIG_MULTITHREADING -#ifdef CONFIG_SMP - return thread->base.is_idle; -#else - return thread == &z_idle_threads[0]; -#endif /* CONFIG_SMP */ -#else - return false; -#endif /* CONFIG_MULTITHREADING */ -} - -static inline bool z_is_thread_suspended(struct k_thread *thread) -{ - return (thread->base.thread_state & _THREAD_SUSPENDED) != 0U; -} - -static inline bool z_is_thread_pending(struct k_thread *thread) -{ - return (thread->base.thread_state & _THREAD_PENDING) != 0U; -} - -static inline bool z_is_thread_prevented_from_running(struct k_thread *thread) -{ - uint8_t state = thread->base.thread_state; - - return (state & (_THREAD_PENDING | _THREAD_PRESTART | _THREAD_DEAD | - _THREAD_DUMMY | _THREAD_SUSPENDED)) != 0U; - -} - -static inline bool z_is_thread_timeout_active(struct k_thread *thread) -{ - return !z_is_inactive_timeout(&thread->base.timeout); -} - -static inline bool z_is_thread_ready(struct k_thread *thread) -{ - return !((z_is_thread_prevented_from_running(thread)) != 0U || - z_is_thread_timeout_active(thread)); -} - -static inline bool z_has_thread_started(struct k_thread *thread) -{ - return (thread->base.thread_state & _THREAD_PRESTART) == 0U; -} - -static inline bool z_is_thread_state_set(struct k_thread *thread, uint32_t state) -{ - return (thread->base.thread_state & state) != 0U; -} - -static inline bool z_is_thread_queued(struct k_thread *thread) -{ - return z_is_thread_state_set(thread, _THREAD_QUEUED); -} - -static inline void z_mark_thread_as_suspended(struct k_thread *thread) -{ - thread->base.thread_state |= _THREAD_SUSPENDED; - - SYS_PORT_TRACING_FUNC(k_thread, sched_suspend, thread); -} - -static inline void z_mark_thread_as_not_suspended(struct k_thread *thread) -{ - thread->base.thread_state &= ~_THREAD_SUSPENDED; - - SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread); -} - -static inline void z_mark_thread_as_started(struct k_thread *thread) -{ - thread->base.thread_state &= ~_THREAD_PRESTART; -} - -static inline void z_mark_thread_as_pending(struct k_thread *thread) -{ - thread->base.thread_state |= _THREAD_PENDING; -} - -static inline void z_mark_thread_as_not_pending(struct k_thread *thread) -{ - thread->base.thread_state &= ~_THREAD_PENDING; -} - -/* - * This function tags the current thread as essential to system operation. - * Exceptions raised by this thread will be treated as a fatal system error. - */ -static inline void z_thread_essential_set(struct k_thread *thread) -{ - thread->base.user_options |= K_ESSENTIAL; -} - -/* - * This function tags the current thread as not essential to system operation. - * Exceptions raised by this thread may be recoverable. - * (This is the default tag for a thread.) - */ -static inline void z_thread_essential_clear(struct k_thread *thread) -{ - thread->base.user_options &= ~K_ESSENTIAL; -} - -/* - * This routine indicates if the current thread is an essential system thread. - * - * Returns true if current thread is essential, false if it is not. - */ -static inline bool z_is_thread_essential(struct k_thread *thread) -{ - return (thread->base.user_options & K_ESSENTIAL) == K_ESSENTIAL; -} - static inline bool z_is_under_prio_ceiling(int prio) { return prio >= CONFIG_PRIORITY_CEILING; diff --git a/kernel/include/kthread.h b/kernel/include/kthread.h index 423e6989fd4..57192cfd905 100644 --- a/kernel/include/kthread.h +++ b/kernel/include/kthread.h @@ -9,6 +9,7 @@ #define ZEPHYR_KERNEL_INCLUDE_THREAD_H_ #include +#include #include #ifdef CONFIG_THREAD_MONITOR @@ -19,6 +20,8 @@ extern struct k_spinlock z_thread_monitor_lock; #endif /* CONFIG_THREAD_MONITOR */ +void idle(void *unused1, void *unused2, void *unused3); + /* clean up when a thread is aborted */ #if defined(CONFIG_THREAD_MONITOR) @@ -46,4 +49,191 @@ static inline void thread_schedule_new(struct k_thread *thread, k_timeout_t dela } #endif /* CONFIG_MULTITHREADING */ +static inline int is_preempt(struct k_thread *thread) +{ + /* explanation in kernel_struct.h */ + return thread->base.preempt <= _PREEMPT_THRESHOLD; +} + + +static inline int is_metairq(struct k_thread *thread) +{ +#if CONFIG_NUM_METAIRQ_PRIORITIES > 0 + return (thread->base.prio - K_HIGHEST_THREAD_PRIO) + < CONFIG_NUM_METAIRQ_PRIORITIES; +#else + ARG_UNUSED(thread); + return 0; +#endif /* CONFIG_NUM_METAIRQ_PRIORITIES */ +} + +#if CONFIG_ASSERT +static inline bool is_thread_dummy(struct k_thread *thread) +{ + return (thread->base.thread_state & _THREAD_DUMMY) != 0U; +} +#endif /* CONFIG_ASSERT */ + + +static inline bool z_is_thread_suspended(struct k_thread *thread) +{ + return (thread->base.thread_state & _THREAD_SUSPENDED) != 0U; +} + +static inline bool z_is_thread_pending(struct k_thread *thread) +{ + return (thread->base.thread_state & _THREAD_PENDING) != 0U; +} + +static inline bool z_is_thread_prevented_from_running(struct k_thread *thread) +{ + uint8_t state = thread->base.thread_state; + + return (state & (_THREAD_PENDING | _THREAD_PRESTART | _THREAD_DEAD | + _THREAD_DUMMY | _THREAD_SUSPENDED)) != 0U; + +} + +static inline bool z_is_thread_timeout_active(struct k_thread *thread) +{ + return !z_is_inactive_timeout(&thread->base.timeout); +} + +static inline bool z_is_thread_ready(struct k_thread *thread) +{ + return !((z_is_thread_prevented_from_running(thread)) != 0U || + z_is_thread_timeout_active(thread)); +} + +static inline bool z_has_thread_started(struct k_thread *thread) +{ + return (thread->base.thread_state & _THREAD_PRESTART) == 0U; +} + +static inline bool z_is_thread_state_set(struct k_thread *thread, uint32_t state) +{ + return (thread->base.thread_state & state) != 0U; +} + +static inline bool z_is_thread_queued(struct k_thread *thread) +{ + return z_is_thread_state_set(thread, _THREAD_QUEUED); +} + +static inline void z_mark_thread_as_suspended(struct k_thread *thread) +{ + thread->base.thread_state |= _THREAD_SUSPENDED; + + SYS_PORT_TRACING_FUNC(k_thread, sched_suspend, thread); +} + +static inline void z_mark_thread_as_not_suspended(struct k_thread *thread) +{ + thread->base.thread_state &= ~_THREAD_SUSPENDED; + + SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread); +} + +static inline void z_mark_thread_as_started(struct k_thread *thread) +{ + thread->base.thread_state &= ~_THREAD_PRESTART; +} + +static inline void z_mark_thread_as_pending(struct k_thread *thread) +{ + thread->base.thread_state |= _THREAD_PENDING; +} + +static inline void z_mark_thread_as_not_pending(struct k_thread *thread) +{ + thread->base.thread_state &= ~_THREAD_PENDING; +} + +/* + * This function tags the current thread as essential to system operation. + * Exceptions raised by this thread will be treated as a fatal system error. + */ +static inline void z_thread_essential_set(struct k_thread *thread) +{ + thread->base.user_options |= K_ESSENTIAL; +} + +/* + * This function tags the current thread as not essential to system operation. + * Exceptions raised by this thread may be recoverable. + * (This is the default tag for a thread.) + */ +static inline void z_thread_essential_clear(struct k_thread *thread) +{ + thread->base.user_options &= ~K_ESSENTIAL; +} + +/* + * This routine indicates if the current thread is an essential system thread. + * + * Returns true if current thread is essential, false if it is not. + */ +static inline bool z_is_thread_essential(struct k_thread *thread) +{ + return (thread->base.user_options & K_ESSENTIAL) == K_ESSENTIAL; +} + + +static ALWAYS_INLINE bool should_preempt(struct k_thread *thread, + int preempt_ok) +{ + /* Preemption is OK if it's being explicitly allowed by + * software state (e.g. the thread called k_yield()) + */ + if (preempt_ok != 0) { + return true; + } + + __ASSERT(_current != NULL, ""); + + /* Or if we're pended/suspended/dummy (duh) */ + if (z_is_thread_prevented_from_running(_current)) { + return true; + } + + /* Edge case on ARM where a thread can be pended out of an + * interrupt handler before the "synchronous" swap starts + * context switching. Platforms with atomic swap can never + * hit this. + */ + if (IS_ENABLED(CONFIG_SWAP_NONATOMIC) + && z_is_thread_timeout_active(thread)) { + return true; + } + + /* Otherwise we have to be running a preemptible thread or + * switching to a metairq + */ + if (is_preempt(_current) || is_metairq(thread)) { + return true; + } + + return false; +} + + +static inline bool z_is_idle_thread_entry(void *entry_point) +{ + return entry_point == idle; +} + +static inline bool z_is_idle_thread_object(struct k_thread *thread) +{ +#ifdef CONFIG_MULTITHREADING +#ifdef CONFIG_SMP + return thread->base.is_idle; +#else + return thread == &z_idle_threads[0]; +#endif /* CONFIG_SMP */ +#else + return false; +#endif /* CONFIG_MULTITHREADING */ +} + + #endif /* ZEPHYR_KERNEL_INCLUDE_THREAD_H_ */ diff --git a/kernel/mailbox.c b/kernel/mailbox.c index 0d690768c21..84c79b19931 100644 --- a/kernel/mailbox.c +++ b/kernel/mailbox.c @@ -18,6 +18,7 @@ #include /* private kernel APIs */ #include +#include #include #ifdef CONFIG_OBJ_CORE_MAILBOX diff --git a/kernel/mutex.c b/kernel/mutex.c index e5ead48b9c9..3635e7624ca 100644 --- a/kernel/mutex.c +++ b/kernel/mutex.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include diff --git a/kernel/sched.c b/kernel/sched.c index bcc80d63bba..4aa2251a7b6 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -30,36 +30,11 @@ static void halt_thread(struct k_thread *thread, uint8_t new_state); static void add_to_waitq_locked(struct k_thread *thread, _wait_q_t *wait_q); - -static inline int is_preempt(struct k_thread *thread) -{ - /* explanation in kernel_struct.h */ - return thread->base.preempt <= _PREEMPT_THRESHOLD; -} - BUILD_ASSERT(CONFIG_NUM_COOP_PRIORITIES >= CONFIG_NUM_METAIRQ_PRIORITIES, "You need to provide at least as many CONFIG_NUM_COOP_PRIORITIES as " "CONFIG_NUM_METAIRQ_PRIORITIES as Meta IRQs are just a special class of cooperative " "threads."); -static inline int is_metairq(struct k_thread *thread) -{ -#if CONFIG_NUM_METAIRQ_PRIORITIES > 0 - return (thread->base.prio - K_HIGHEST_THREAD_PRIO) - < CONFIG_NUM_METAIRQ_PRIORITIES; -#else - ARG_UNUSED(thread); - return 0; -#endif /* CONFIG_NUM_METAIRQ_PRIORITIES */ -} - -#if CONFIG_ASSERT -static inline bool is_thread_dummy(struct k_thread *thread) -{ - return (thread->base.thread_state & _THREAD_DUMMY) != 0U; -} -#endif /* CONFIG_ASSERT */ - /* * Return value same as e.g. memcmp * > 0 -> thread 1 priority > thread 2 priority @@ -102,43 +77,6 @@ int32_t z_sched_prio_cmp(struct k_thread *thread_1, return 0; } -static ALWAYS_INLINE bool should_preempt(struct k_thread *thread, - int preempt_ok) -{ - /* Preemption is OK if it's being explicitly allowed by - * software state (e.g. the thread called k_yield()) - */ - if (preempt_ok != 0) { - return true; - } - - __ASSERT(_current != NULL, ""); - - /* Or if we're pended/suspended/dummy (duh) */ - if (z_is_thread_prevented_from_running(_current)) { - return true; - } - - /* Edge case on ARM where a thread can be pended out of an - * interrupt handler before the "synchronous" swap starts - * context switching. Platforms with atomic swap can never - * hit this. - */ - if (IS_ENABLED(CONFIG_SWAP_NONATOMIC) - && z_is_thread_timeout_active(thread)) { - return true; - } - - /* Otherwise we have to be running a preemptible thread or - * switching to a metairq - */ - if (is_preempt(_current) || is_metairq(thread)) { - return true; - } - - return false; -} - #ifdef CONFIG_SCHED_CPU_MASK static ALWAYS_INLINE struct k_thread *_priq_dumb_mask_best(sys_dlist_t *pq) { diff --git a/tests/kernel/threads/thread_apis/src/main.c b/tests/kernel/threads/thread_apis/src/main.c index 95a970d5792..28e1bc29d0d 100644 --- a/tests/kernel/threads/thread_apis/src/main.c +++ b/tests/kernel/threads/thread_apis/src/main.c @@ -18,7 +18,10 @@ #include #include #include + +/* internal kernel APIs */ #include +#include #include LOG_MODULE_REGISTER(test); diff --git a/tests/kernel/threads/thread_apis/src/test_essential_thread.c b/tests/kernel/threads/thread_apis/src/test_essential_thread.c index 0d2829b2b36..18143469323 100644 --- a/tests/kernel/threads/thread_apis/src/test_essential_thread.c +++ b/tests/kernel/threads/thread_apis/src/test_essential_thread.c @@ -10,6 +10,7 @@ /* Internal APIs */ #include #include +#include struct k_thread kthread_thread; struct k_thread kthread_thread1; From 31bc210bbcedb97e924822f7af940a6e2a434ca1 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 7 Mar 2024 18:18:36 -0500 Subject: [PATCH 1687/2402] kernel: sched: remove unused prototype: z_is_thread_time_slicing A prototype not used anywhere. Signed-off-by: Anas Nashif --- kernel/include/ksched.h | 1 - 1 file changed, 1 deletion(-) diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index 253d588aff6..eb968fdc1dc 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -39,7 +39,6 @@ BUILD_ASSERT(K_LOWEST_APPLICATION_THREAD_PRIO void z_sched_init(void); void z_move_thread_to_end_of_prio_q(struct k_thread *thread); -int z_is_thread_time_slicing(struct k_thread *thread); void z_unpend_thread_no_timeout(struct k_thread *thread); struct k_thread *z_unpend1_no_timeout(_wait_q_t *wait_q); int z_pend_curr(struct k_spinlock *lock, k_spinlock_key_t key, From 37df48546364510262c8faa3edceb840c8811c52 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Fri, 8 Mar 2024 07:51:01 -0500 Subject: [PATCH 1688/2402] kernel: split timeslicing/ipi code out of sched.c Move both timeslicing and IPI code to own files. Signed-off-by: Anas Nashif --- kernel/CMakeLists.txt | 9 +- kernel/include/ipi.h | 19 +++++ kernel/include/ksched.h | 2 + kernel/ipi.c | 59 +++++++++++++ kernel/sched.c | 182 ++-------------------------------------- kernel/timeslicing.c | 131 +++++++++++++++++++++++++++++ 6 files changed, 225 insertions(+), 177 deletions(-) create mode 100644 kernel/include/ipi.h create mode 100644 kernel/ipi.c create mode 100644 kernel/timeslicing.c diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt index 1883b45a138..3d7c4de6d65 100644 --- a/kernel/CMakeLists.txt +++ b/kernel/CMakeLists.txt @@ -86,11 +86,18 @@ list(APPEND kernel_files if(CONFIG_SMP) list(APPEND kernel_files - smp.c) + smp.c + ipi.c) endif() endif() + +if(CONFIG_TIMESLICING) +list(APPEND kernel_files + timeslicing.c) +endif() + if(CONFIG_SPIN_VALIDATE) list(APPEND kernel_files spinlock_validate.c) diff --git a/kernel/include/ipi.h b/kernel/include/ipi.h new file mode 100644 index 00000000000..77105cac168 --- /dev/null +++ b/kernel/include/ipi.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + + +#ifndef ZEPHYR_KERNEL_INCLUDE_IPI_H_ +#define ZEPHYR_KERNEL_INCLUDE_IPI_H_ + +/* defined in ipi.c when CONFIG_SMP=y */ +#ifdef CONFIG_SMP +void flag_ipi(void); +void signal_pending_ipi(void); +#else +#define flag_ipi() do { } while (false) +#define signal_pending_ipi() do { } while (false) +#endif /* CONFIG_SMP */ + +#endif /* ZEPHYR_KERNEL_INCLUDE_IPI_H_ */ diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index eb968fdc1dc..1340a17b4e7 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -62,6 +62,8 @@ void z_ready_thread(struct k_thread *thread); void z_requeue_current(struct k_thread *curr); struct k_thread *z_swap_next_thread(void); void z_thread_abort(struct k_thread *thread); +void move_thread_to_end_of_prio_q(struct k_thread *thread); +bool thread_is_sliceable(struct k_thread *thread); static inline void z_reschedule_unlocked(void) { diff --git a/kernel/ipi.c b/kernel/ipi.c new file mode 100644 index 00000000000..677d30f8d24 --- /dev/null +++ b/kernel/ipi.c @@ -0,0 +1,59 @@ +/** + * Copyright (c) 2024 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#ifdef CONFIG_TRACE_SCHED_IPI +extern void z_trace_sched_ipi(void); +#endif + + +void flag_ipi(void) +{ +#if defined(CONFIG_SCHED_IPI_SUPPORTED) + if (arch_num_cpus() > 1) { + _kernel.pending_ipi = true; + } +#endif /* CONFIG_SCHED_IPI_SUPPORTED */ +} + + +void signal_pending_ipi(void) +{ + /* Synchronization note: you might think we need to lock these + * two steps, but an IPI is idempotent. It's OK if we do it + * twice. All we require is that if a CPU sees the flag true, + * it is guaranteed to send the IPI, and if a core sets + * pending_ipi, the IPI will be sent the next time through + * this code. + */ +#if defined(CONFIG_SCHED_IPI_SUPPORTED) + if (arch_num_cpus() > 1) { + if (_kernel.pending_ipi) { + _kernel.pending_ipi = false; + arch_sched_ipi(); + } + } +#endif /* CONFIG_SCHED_IPI_SUPPORTED */ +} + +void z_sched_ipi(void) +{ + /* NOTE: When adding code to this, make sure this is called + * at appropriate location when !CONFIG_SCHED_IPI_SUPPORTED. + */ +#ifdef CONFIG_TRACE_SCHED_IPI + z_trace_sched_ipi(); +#endif /* CONFIG_TRACE_SCHED_IPI */ + +#ifdef CONFIG_TIMESLICING + if (sliceable(_current)) { + z_time_slice(); + } +#endif /* CONFIG_TIMESLICING */ +} diff --git a/kernel/sched.c b/kernel/sched.c index 4aa2251a7b6..609ec4b1245 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,10 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); +#if defined(CONFIG_SWAP_NONATOMIC) && defined(CONFIG_TIMESLICING) +extern struct k_thread *pending_current; +#endif + struct k_spinlock _sched_spinlock; static void update_cache(int preempt_ok); @@ -188,25 +193,6 @@ static ALWAYS_INLINE void dequeue_thread(struct k_thread *thread) } } -static void signal_pending_ipi(void) -{ - /* Synchronization note: you might think we need to lock these - * two steps, but an IPI is idempotent. It's OK if we do it - * twice. All we require is that if a CPU sees the flag true, - * it is guaranteed to send the IPI, and if a core sets - * pending_ipi, the IPI will be sent the next time through - * this code. - */ -#if defined(CONFIG_SMP) && defined(CONFIG_SCHED_IPI_SUPPORTED) - if (arch_num_cpus() > 1) { - if (_kernel.pending_ipi) { - _kernel.pending_ipi = false; - arch_sched_ipi(); - } - } -#endif /* CONFIG_SMP && CONFIG_SCHED_IPI_SUPPORTED */ -} - #ifdef CONFIG_SMP /* Called out of z_swap() when CONFIG_SMP. The current thread can * never live in the run queue until we are inexorably on the context @@ -330,7 +316,7 @@ static ALWAYS_INLINE struct k_thread *next_up(void) #endif /* CONFIG_SMP */ } -static void move_thread_to_end_of_prio_q(struct k_thread *thread) +void move_thread_to_end_of_prio_q(struct k_thread *thread) { if (z_is_thread_queued(thread)) { dequeue_thread(thread); @@ -339,140 +325,6 @@ static void move_thread_to_end_of_prio_q(struct k_thread *thread) update_cache(thread == _current); } -static void flag_ipi(void) -{ -#if defined(CONFIG_SMP) && defined(CONFIG_SCHED_IPI_SUPPORTED) - if (arch_num_cpus() > 1) { - _kernel.pending_ipi = true; - } -#endif /* CONFIG_SMP && CONFIG_SCHED_IPI_SUPPORTED */ -} - -#ifdef CONFIG_TIMESLICING - -static int slice_ticks = DIV_ROUND_UP(CONFIG_TIMESLICE_SIZE * Z_HZ_ticks, Z_HZ_ms); -static int slice_max_prio = CONFIG_TIMESLICE_PRIORITY; -static struct _timeout slice_timeouts[CONFIG_MP_MAX_NUM_CPUS]; -static bool slice_expired[CONFIG_MP_MAX_NUM_CPUS]; - -#ifdef CONFIG_SWAP_NONATOMIC -/* If z_swap() isn't atomic, then it's possible for a timer interrupt - * to try to timeslice away _current after it has already pended - * itself but before the corresponding context switch. Treat that as - * a noop condition in z_time_slice(). - */ -static struct k_thread *pending_current; -#endif /* CONFIG_SWAP_NONATOMIC */ - -static inline int slice_time(struct k_thread *thread) -{ - int ret = slice_ticks; - -#ifdef CONFIG_TIMESLICE_PER_THREAD - if (thread->base.slice_ticks != 0) { - ret = thread->base.slice_ticks; - } -#else - ARG_UNUSED(thread); -#endif /* CONFIG_TIMESLICE_PER_THREAD */ - return ret; -} - -static inline bool sliceable(struct k_thread *thread) -{ - bool ret = is_preempt(thread) - && slice_time(thread) != 0 - && !z_is_prio_higher(thread->base.prio, slice_max_prio) - && !z_is_thread_prevented_from_running(thread) - && !z_is_idle_thread_object(thread); - -#ifdef CONFIG_TIMESLICE_PER_THREAD - ret |= thread->base.slice_ticks != 0; -#endif /* CONFIG_TIMESLICE_PER_THREAD */ - - return ret; -} - -static void slice_timeout(struct _timeout *timeout) -{ - int cpu = ARRAY_INDEX(slice_timeouts, timeout); - - slice_expired[cpu] = true; - - /* We need an IPI if we just handled a timeslice expiration - * for a different CPU. Ideally this would be able to target - * the specific core, but that's not part of the API yet. - */ - if (IS_ENABLED(CONFIG_SMP) && cpu != _current_cpu->id) { - flag_ipi(); - } -} - -void z_reset_time_slice(struct k_thread *thread) -{ - int cpu = _current_cpu->id; - - z_abort_timeout(&slice_timeouts[cpu]); - slice_expired[cpu] = false; - if (sliceable(thread)) { - z_add_timeout(&slice_timeouts[cpu], slice_timeout, - K_TICKS(slice_time(thread) - 1)); - } -} - -void k_sched_time_slice_set(int32_t slice, int prio) -{ - K_SPINLOCK(&_sched_spinlock) { - slice_ticks = k_ms_to_ticks_ceil32(slice); - slice_max_prio = prio; - z_reset_time_slice(_current); - } -} - -#ifdef CONFIG_TIMESLICE_PER_THREAD -void k_thread_time_slice_set(struct k_thread *thread, int32_t thread_slice_ticks, - k_thread_timeslice_fn_t expired, void *data) -{ - K_SPINLOCK(&_sched_spinlock) { - thread->base.slice_ticks = thread_slice_ticks; - thread->base.slice_expired = expired; - thread->base.slice_data = data; - } -} -#endif /* CONFIG_TIMESLICE_PER_THREAD */ - -/* Called out of each timer interrupt */ -void z_time_slice(void) -{ - k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); - struct k_thread *curr = _current; - -#ifdef CONFIG_SWAP_NONATOMIC - if (pending_current == curr) { - z_reset_time_slice(curr); - k_spin_unlock(&_sched_spinlock, key); - return; - } - pending_current = NULL; -#endif /* CONFIG_SWAP_NONATOMIC */ - - if (slice_expired[_current_cpu->id] && sliceable(curr)) { -#ifdef CONFIG_TIMESLICE_PER_THREAD - if (curr->base.slice_expired) { - k_spin_unlock(&_sched_spinlock, key); - curr->base.slice_expired(curr, curr->base.slice_data); - key = k_spin_lock(&_sched_spinlock); - } -#endif /* CONFIG_TIMESLICE_PER_THREAD */ - if (!z_is_thread_prevented_from_running(curr)) { - move_thread_to_end_of_prio_q(curr); - } - z_reset_time_slice(curr); - } - k_spin_unlock(&_sched_spinlock, key); -} -#endif /* CONFIG_TIMESLICING */ - /* Track cooperative threads preempted by metairqs so we can return to * them specifically. Called at the moment a new thread has been * selected to run. @@ -1433,28 +1285,6 @@ void z_impl_k_wakeup(k_tid_t thread) } } -#ifdef CONFIG_TRACE_SCHED_IPI -extern void z_trace_sched_ipi(void); -#endif /* CONFIG_TRACE_SCHED_IPI */ - -#ifdef CONFIG_SMP -void z_sched_ipi(void) -{ - /* NOTE: When adding code to this, make sure this is called - * at appropriate location when !CONFIG_SCHED_IPI_SUPPORTED. - */ -#ifdef CONFIG_TRACE_SCHED_IPI - z_trace_sched_ipi(); -#endif /* CONFIG_TRACE_SCHED_IPI */ - -#ifdef CONFIG_TIMESLICING - if (sliceable(_current)) { - z_time_slice(); - } -#endif /* CONFIG_TIMESLICING */ -} -#endif /* CONFIG_SMP */ - #ifdef CONFIG_USERSPACE static inline void z_vrfy_k_wakeup(k_tid_t thread) { diff --git a/kernel/timeslicing.c b/kernel/timeslicing.c new file mode 100644 index 00000000000..a7b9d341348 --- /dev/null +++ b/kernel/timeslicing.c @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2018, 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include + +static int slice_ticks = DIV_ROUND_UP(CONFIG_TIMESLICE_SIZE * Z_HZ_ticks, Z_HZ_ms); +static int slice_max_prio = CONFIG_TIMESLICE_PRIORITY; +static struct _timeout slice_timeouts[CONFIG_MP_MAX_NUM_CPUS]; +static bool slice_expired[CONFIG_MP_MAX_NUM_CPUS]; + +#ifdef CONFIG_SWAP_NONATOMIC +/* If z_swap() isn't atomic, then it's possible for a timer interrupt + * to try to timeslice away _current after it has already pended + * itself but before the corresponding context switch. Treat that as + * a noop condition in z_time_slice(). + */ +struct k_thread *pending_current; +#endif + +static inline int slice_time(struct k_thread *thread) +{ + int ret = slice_ticks; + +#ifdef CONFIG_TIMESLICE_PER_THREAD + if (thread->base.slice_ticks != 0) { + ret = thread->base.slice_ticks; + } +#else + ARG_UNUSED(thread); +#endif + return ret; +} + +bool sliceable(struct k_thread *thread) +{ + bool ret = is_preempt(thread) + && slice_time(thread) != 0 + && !z_is_prio_higher(thread->base.prio, slice_max_prio) + && !z_is_thread_prevented_from_running(thread) + && !z_is_idle_thread_object(thread); + +#ifdef CONFIG_TIMESLICE_PER_THREAD + ret |= thread->base.slice_ticks != 0; +#endif + + return ret; +} + +static void slice_timeout(struct _timeout *timeout) +{ + int cpu = ARRAY_INDEX(slice_timeouts, timeout); + + slice_expired[cpu] = true; + + /* We need an IPI if we just handled a timeslice expiration + * for a different CPU. Ideally this would be able to target + * the specific core, but that's not part of the API yet. + */ + if (IS_ENABLED(CONFIG_SMP) && cpu != _current_cpu->id) { + flag_ipi(); + } +} + +void z_reset_time_slice(struct k_thread *thread) +{ + int cpu = _current_cpu->id; + + z_abort_timeout(&slice_timeouts[cpu]); + slice_expired[cpu] = false; + if (sliceable(thread)) { + z_add_timeout(&slice_timeouts[cpu], slice_timeout, + K_TICKS(slice_time(thread) - 1)); + } +} + +void k_sched_time_slice_set(int32_t slice, int prio) +{ + K_SPINLOCK(&_sched_spinlock) { + slice_ticks = k_ms_to_ticks_ceil32(slice); + slice_max_prio = prio; + z_reset_time_slice(_current); + } +} + +#ifdef CONFIG_TIMESLICE_PER_THREAD +void k_thread_time_slice_set(struct k_thread *thread, int32_t thread_slice_ticks, + k_thread_timeslice_fn_t expired, void *data) +{ + K_SPINLOCK(&_sched_spinlock) { + thread->base.slice_ticks = thread_slice_ticks; + thread->base.slice_expired = expired; + thread->base.slice_data = data; + } +} +#endif + +/* Called out of each timer interrupt */ +void z_time_slice(void) +{ + k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); + struct k_thread *curr = _current; + +#ifdef CONFIG_SWAP_NONATOMIC + if (pending_current == curr) { + z_reset_time_slice(curr); + k_spin_unlock(&_sched_spinlock, key); + return; + } + pending_current = NULL; +#endif + + if (slice_expired[_current_cpu->id] && sliceable(curr)) { +#ifdef CONFIG_TIMESLICE_PER_THREAD + if (curr->base.slice_expired) { + k_spin_unlock(&_sched_spinlock, key); + curr->base.slice_expired(curr, curr->base.slice_data); + key = k_spin_lock(&_sched_spinlock); + } +#endif + if (!z_is_thread_prevented_from_running(curr)) { + move_thread_to_end_of_prio_q(curr); + } + z_reset_time_slice(curr); + } + k_spin_unlock(&_sched_spinlock, key); +} From 0b473ce925fe829a5c9a9edeb11bcca9649c907e Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Wed, 27 Mar 2024 07:13:45 -0400 Subject: [PATCH 1689/2402] kernel: rename sliceable -> thread_is_sliceable Trivial rename of sliceable function. Signed-off-by: Anas Nashif --- kernel/ipi.c | 2 +- kernel/timeslicing.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/kernel/ipi.c b/kernel/ipi.c index 677d30f8d24..99693c0ecbf 100644 --- a/kernel/ipi.c +++ b/kernel/ipi.c @@ -52,7 +52,7 @@ void z_sched_ipi(void) #endif /* CONFIG_TRACE_SCHED_IPI */ #ifdef CONFIG_TIMESLICING - if (sliceable(_current)) { + if (thread_is_sliceable(_current)) { z_time_slice(); } #endif /* CONFIG_TIMESLICING */ diff --git a/kernel/timeslicing.c b/kernel/timeslicing.c index a7b9d341348..3ed83e1ed81 100644 --- a/kernel/timeslicing.c +++ b/kernel/timeslicing.c @@ -36,7 +36,7 @@ static inline int slice_time(struct k_thread *thread) return ret; } -bool sliceable(struct k_thread *thread) +bool thread_is_sliceable(struct k_thread *thread) { bool ret = is_preempt(thread) && slice_time(thread) != 0 @@ -72,7 +72,7 @@ void z_reset_time_slice(struct k_thread *thread) z_abort_timeout(&slice_timeouts[cpu]); slice_expired[cpu] = false; - if (sliceable(thread)) { + if (thread_is_sliceable(thread)) { z_add_timeout(&slice_timeouts[cpu], slice_timeout, K_TICKS(slice_time(thread) - 1)); } @@ -114,7 +114,7 @@ void z_time_slice(void) pending_current = NULL; #endif - if (slice_expired[_current_cpu->id] && sliceable(curr)) { + if (slice_expired[_current_cpu->id] && thread_is_sliceable(curr)) { #ifdef CONFIG_TIMESLICE_PER_THREAD if (curr->base.slice_expired) { k_spin_unlock(&_sched_spinlock, key); From 17c874f4fc78a183dff1b6ca1883cab26692cc1c Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 28 Mar 2024 07:15:04 -0400 Subject: [PATCH 1690/2402] kernel: thread: rename is_metairq Trivial rename of is_metairq to thread_is_metairq. Signed-off-by: Anas Nashif --- kernel/include/kthread.h | 4 ++-- kernel/sched.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/kernel/include/kthread.h b/kernel/include/kthread.h index 57192cfd905..3ec6cf88836 100644 --- a/kernel/include/kthread.h +++ b/kernel/include/kthread.h @@ -56,7 +56,7 @@ static inline int is_preempt(struct k_thread *thread) } -static inline int is_metairq(struct k_thread *thread) +static inline int thread_is_metairq(struct k_thread *thread) { #if CONFIG_NUM_METAIRQ_PRIORITIES > 0 return (thread->base.prio - K_HIGHEST_THREAD_PRIO) @@ -209,7 +209,7 @@ static ALWAYS_INLINE bool should_preempt(struct k_thread *thread, /* Otherwise we have to be running a preemptible thread or * switching to a metairq */ - if (is_preempt(_current) || is_metairq(thread)) { + if (is_preempt(_current) || thread_is_metairq(thread)) { return true; } diff --git a/kernel/sched.c b/kernel/sched.c index 609ec4b1245..6357b867b35 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -248,7 +248,7 @@ static ALWAYS_INLINE struct k_thread *next_up(void) */ struct k_thread *mirqp = _current_cpu->metairq_preempted; - if (mirqp != NULL && (thread == NULL || !is_metairq(thread))) { + if (mirqp != NULL && (thread == NULL || !thread_is_metairq(thread))) { if (!z_is_thread_prevented_from_running(mirqp)) { thread = mirqp; } else { @@ -333,11 +333,11 @@ static void update_metairq_preempt(struct k_thread *thread) { #if (CONFIG_NUM_METAIRQ_PRIORITIES > 0) && \ (CONFIG_NUM_COOP_PRIORITIES > CONFIG_NUM_METAIRQ_PRIORITIES) - if (is_metairq(thread) && !is_metairq(_current) && + if (thread_is_metairq(thread) && !thread_is_metairq(_current) && !is_preempt(_current)) { /* Record new preemption */ _current_cpu->metairq_preempted = _current; - } else if (!is_metairq(thread) && !z_is_idle_thread_object(thread)) { + } else if (!thread_is_metairq(thread) && !z_is_idle_thread_object(thread)) { /* Returning from existing preemption */ _current_cpu->metairq_preempted = NULL; } From 6754cbd1b5e46d8ae8902d20ad9feaf7386b2426 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 28 Mar 2024 07:19:20 -0400 Subject: [PATCH 1691/2402] kernel: thread: move k_is_preempt_thread to thread.c This belongs in thread.c Signed-off-by: Anas Nashif --- kernel/sched.c | 13 ------------- kernel/thread.c | 13 +++++++++++++ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/kernel/sched.c b/kernel/sched.c index 6357b867b35..5f38740c3ea 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -1320,19 +1320,6 @@ static inline k_tid_t z_vrfy_k_sched_current_thread_query(void) #include #endif /* CONFIG_USERSPACE */ -int z_impl_k_is_preempt_thread(void) -{ - return !arch_is_in_isr() && is_preempt(_current); -} - -#ifdef CONFIG_USERSPACE -static inline int z_vrfy_k_is_preempt_thread(void) -{ - return z_impl_k_is_preempt_thread(); -} -#include -#endif /* CONFIG_USERSPACE */ - static inline void unpend_all(_wait_q_t *wait_q) { struct k_thread *thread; diff --git a/kernel/thread.c b/kernel/thread.c index 115bf34a3b6..83f2ee2e725 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -108,6 +108,19 @@ static inline void *z_vrfy_k_thread_custom_data_get(void) #endif /* CONFIG_USERSPACE */ #endif /* CONFIG_THREAD_CUSTOM_DATA */ +int z_impl_k_is_preempt_thread(void) +{ + return !arch_is_in_isr() && is_preempt(_current); +} + +#ifdef CONFIG_USERSPACE +static inline int z_vrfy_k_is_preempt_thread(void) +{ + return z_impl_k_is_preempt_thread(); +} +#include +#endif /* CONFIG_USERSPACE */ + int z_impl_k_thread_name_set(struct k_thread *thread, const char *value) { #ifdef CONFIG_THREAD_NAME From 5c170c704640b8da31aca6a447f47fed27055d84 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 28 Mar 2024 07:20:51 -0400 Subject: [PATCH 1692/2402] kernel: thread: rename is_preempt Trivila rename to thread_is_preempt. Signed-off-by: Anas Nashif --- kernel/include/kthread.h | 4 ++-- kernel/sched.c | 2 +- kernel/thread.c | 2 +- kernel/timeslicing.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/kernel/include/kthread.h b/kernel/include/kthread.h index 3ec6cf88836..9fd5c9e4d98 100644 --- a/kernel/include/kthread.h +++ b/kernel/include/kthread.h @@ -49,7 +49,7 @@ static inline void thread_schedule_new(struct k_thread *thread, k_timeout_t dela } #endif /* CONFIG_MULTITHREADING */ -static inline int is_preempt(struct k_thread *thread) +static inline int thread_is_preemptible(struct k_thread *thread) { /* explanation in kernel_struct.h */ return thread->base.preempt <= _PREEMPT_THRESHOLD; @@ -209,7 +209,7 @@ static ALWAYS_INLINE bool should_preempt(struct k_thread *thread, /* Otherwise we have to be running a preemptible thread or * switching to a metairq */ - if (is_preempt(_current) || thread_is_metairq(thread)) { + if (thread_is_preemptible(_current) || thread_is_metairq(thread)) { return true; } diff --git a/kernel/sched.c b/kernel/sched.c index 5f38740c3ea..2ea7531f582 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -334,7 +334,7 @@ static void update_metairq_preempt(struct k_thread *thread) #if (CONFIG_NUM_METAIRQ_PRIORITIES > 0) && \ (CONFIG_NUM_COOP_PRIORITIES > CONFIG_NUM_METAIRQ_PRIORITIES) if (thread_is_metairq(thread) && !thread_is_metairq(_current) && - !is_preempt(_current)) { + !thread_is_preemptible(_current)) { /* Record new preemption */ _current_cpu->metairq_preempted = _current; } else if (!thread_is_metairq(thread) && !z_is_idle_thread_object(thread)) { diff --git a/kernel/thread.c b/kernel/thread.c index 83f2ee2e725..23deffff42a 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -110,7 +110,7 @@ static inline void *z_vrfy_k_thread_custom_data_get(void) int z_impl_k_is_preempt_thread(void) { - return !arch_is_in_isr() && is_preempt(_current); + return !arch_is_in_isr() && thread_is_preemptible(_current); } #ifdef CONFIG_USERSPACE diff --git a/kernel/timeslicing.c b/kernel/timeslicing.c index 3ed83e1ed81..401bcea0c7c 100644 --- a/kernel/timeslicing.c +++ b/kernel/timeslicing.c @@ -38,7 +38,7 @@ static inline int slice_time(struct k_thread *thread) bool thread_is_sliceable(struct k_thread *thread) { - bool ret = is_preempt(thread) + bool ret = thread_is_preemptible(thread) && slice_time(thread) != 0 && !z_is_prio_higher(thread->base.prio, slice_max_prio) && !z_is_thread_prevented_from_running(thread) From f5435b3df7a8cdcbb1809ae952967b985c7baaf3 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 28 Mar 2024 07:23:25 -0400 Subject: [PATCH 1693/2402] kernel: thread: move k_thread_priority_get Move to thread.c alongside all other thread calls. Signed-off-by: Anas Nashif --- kernel/sched.c | 14 -------------- kernel/thread.c | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/kernel/sched.c b/kernel/sched.c index 2ea7531f582..c7bfbd1ddcb 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -1025,20 +1025,6 @@ void z_sched_init(void) #endif /* CONFIG_SCHED_CPU_MASK_PIN_ONLY */ } -int z_impl_k_thread_priority_get(k_tid_t thread) -{ - return thread->base.prio; -} - -#ifdef CONFIG_USERSPACE -static inline int z_vrfy_k_thread_priority_get(k_tid_t thread) -{ - K_OOPS(K_SYSCALL_OBJ(thread, K_OBJ_THREAD)); - return z_impl_k_thread_priority_get(thread); -} -#include -#endif /* CONFIG_USERSPACE */ - void z_impl_k_thread_priority_set(k_tid_t thread, int prio) { /* diff --git a/kernel/thread.c b/kernel/thread.c index 23deffff42a..f87744ebed8 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -121,6 +121,20 @@ static inline int z_vrfy_k_is_preempt_thread(void) #include #endif /* CONFIG_USERSPACE */ +int z_impl_k_thread_priority_get(k_tid_t thread) +{ + return thread->base.prio; +} + +#ifdef CONFIG_USERSPACE +static inline int z_vrfy_k_thread_priority_get(k_tid_t thread) +{ + K_OOPS(K_SYSCALL_OBJ(thread, K_OBJ_THREAD)); + return z_impl_k_thread_priority_get(thread); +} +#include +#endif /* CONFIG_USERSPACE */ + int z_impl_k_thread_name_set(struct k_thread *thread, const char *value) { #ifdef CONFIG_THREAD_NAME From 8a88cd4805b0a1352e822cb707a1a0f453a8d9d7 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 28 Mar 2024 08:40:54 -0400 Subject: [PATCH 1694/2402] kernel: thread: move thread states to header Move state string defines into thread header. Signed-off-by: Anas Nashif --- kernel/include/kthread.h | 10 ++++++++++ kernel/thread.c | 9 --------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/kernel/include/kthread.h b/kernel/include/kthread.h index 9fd5c9e4d98..8438a37de15 100644 --- a/kernel/include/kthread.h +++ b/kernel/include/kthread.h @@ -12,6 +12,16 @@ #include #include + +#define Z_STATE_STR_DUMMY "dummy" +#define Z_STATE_STR_PENDING "pending" +#define Z_STATE_STR_PRESTART "prestart" +#define Z_STATE_STR_DEAD "dead" +#define Z_STATE_STR_SUSPENDED "suspended" +#define Z_STATE_STR_ABORTING "aborting" +#define Z_STATE_STR_SUSPENDING "suspending" +#define Z_STATE_STR_QUEUED "queued" + #ifdef CONFIG_THREAD_MONITOR /* This lock protects the linked list of active threads; i.e. the * initial _kernel.threads pointer and the linked list made up of diff --git a/kernel/thread.c b/kernel/thread.c index f87744ebed8..762432c4b1e 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -219,15 +219,6 @@ static size_t copy_bytes(char *dest, size_t dest_size, const char *src, size_t s return bytes_to_copy; } -#define Z_STATE_STR_DUMMY "dummy" -#define Z_STATE_STR_PENDING "pending" -#define Z_STATE_STR_PRESTART "prestart" -#define Z_STATE_STR_DEAD "dead" -#define Z_STATE_STR_SUSPENDED "suspended" -#define Z_STATE_STR_ABORTING "aborting" -#define Z_STATE_STR_SUSPENDING "suspending" -#define Z_STATE_STR_QUEUED "queued" - const char *k_thread_state_str(k_tid_t thread_id, char *buf, size_t buf_size) { size_t off = 0; From 92e0d0bbfc76ba41c3844b7362bcccf488895087 Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Mon, 25 Mar 2024 16:08:36 -0400 Subject: [PATCH 1695/2402] bluetooth: nus: Change Kconfigs prefix to BT_ZEPHYR_NUS To prevent future conflicts with NCS's NUS implementation, whose Kconfig's are prefixed with BT_NUS. Signed-off-by: Luis Ubieda --- doc/releases/release-notes-3.7.rst | 4 ++-- drivers/serial/Kconfig.bt | 2 +- include/zephyr/linker/common-ram.ld | 2 +- samples/bluetooth/peripheral_nus/prj.conf | 2 +- samples/subsys/logging/logger/overlay-bt.conf | 4 ++-- samples/subsys/shell/shell_module/overlay-bt.conf | 4 ++-- snippets/nus-console/README.rst | 2 +- snippets/nus-console/nus-console.conf | 4 ++-- subsys/bluetooth/services/CMakeLists.txt | 2 +- subsys/bluetooth/services/nus/CMakeLists.txt | 2 +- subsys/bluetooth/services/nus/Kconfig.nus | 10 +++++----- subsys/bluetooth/services/nus/nus.c | 4 ++-- subsys/bluetooth/services/nus/nus_inst.c | 2 +- 13 files changed, 22 insertions(+), 22 deletions(-) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index 6b454318a0b..2e046f084b1 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -37,7 +37,7 @@ Architectures Bluetooth ********* - * Added Nordic UART Service (NUS), enabled by the :kconfig:option:`CONFIG_BT_NUS`. + * Added Nordic UART Service (NUS), enabled by the :kconfig:option:`CONFIG_BT_ZEPHYR_NUS`. This Service exposes the ability to declare multiple instances of the GATT service, allowing multiple serial endpoints to be used for different purposes. @@ -257,6 +257,6 @@ Tests and Samples ***************** * Added snippet for easily enabling UART over Bluetooth LE by passing ``-S nus-console`` during - ``west build``. This snippet sets the :kconfig:option:`CONFIG_BT_NUS_AUTO_START_BLUETOOTH` + ``west build``. This snippet sets the :kconfig:option:`CONFIG_BT_ZEPHYR_NUS_AUTO_START_BLUETOOTH` which allows non-Bluetooth samples that use the UART APIs to run without modifications (e.g: Console and Logging examples). diff --git a/drivers/serial/Kconfig.bt b/drivers/serial/Kconfig.bt index a650615f219..500613d6208 100644 --- a/drivers/serial/Kconfig.bt +++ b/drivers/serial/Kconfig.bt @@ -3,7 +3,7 @@ config UART_BT bool "UART over NUS Bluetooth LE" - depends on BT_NUS + depends on BT_ZEPHYR_NUS depends on DT_HAS_ZEPHYR_NUS_UART_ENABLED select UART_INTERRUPT_DRIVEN select RING_BUFFER diff --git a/include/zephyr/linker/common-ram.ld b/include/zephyr/linker/common-ram.ld index 847c8373548..538b3465b01 100644 --- a/include/zephyr/linker/common-ram.ld +++ b/include/zephyr/linker/common-ram.ld @@ -140,7 +140,7 @@ ITERABLE_SECTION_RAM(device_mutable, 4) #endif -#if defined(CONFIG_BT_NUS) +#if defined(CONFIG_BT_ZEPHYR_NUS) ITERABLE_SECTION_RAM(bt_nus_inst, 4) #endif diff --git a/samples/bluetooth/peripheral_nus/prj.conf b/samples/bluetooth/peripheral_nus/prj.conf index 8eafb75f19c..0db8cecc209 100644 --- a/samples/bluetooth/peripheral_nus/prj.conf +++ b/samples/bluetooth/peripheral_nus/prj.conf @@ -1,3 +1,3 @@ CONFIG_BT=y CONFIG_BT_PERIPHERAL=y -CONFIG_BT_NUS=y +CONFIG_BT_ZEPHYR_NUS=y diff --git a/samples/subsys/logging/logger/overlay-bt.conf b/samples/subsys/logging/logger/overlay-bt.conf index bae817ce562..6691d1c36e7 100644 --- a/samples/subsys/logging/logger/overlay-bt.conf +++ b/samples/subsys/logging/logger/overlay-bt.conf @@ -4,9 +4,9 @@ CONFIG_UART_CONSOLE=y CONFIG_BT=y CONFIG_BT_PERIPHERAL=y -CONFIG_BT_NUS=y +CONFIG_BT_ZEPHYR_NUS=y CONFIG_UART_BT=y -CONFIG_BT_NUS_AUTO_START_BLUETOOTH=y +CONFIG_BT_ZEPHYR_NUS_AUTO_START_BLUETOOTH=y # Bluetooth optimizations to allow larger data packets. CONFIG_BT_RX_STACK_SIZE=2048 diff --git a/samples/subsys/shell/shell_module/overlay-bt.conf b/samples/subsys/shell/shell_module/overlay-bt.conf index bae817ce562..6691d1c36e7 100644 --- a/samples/subsys/shell/shell_module/overlay-bt.conf +++ b/samples/subsys/shell/shell_module/overlay-bt.conf @@ -4,9 +4,9 @@ CONFIG_UART_CONSOLE=y CONFIG_BT=y CONFIG_BT_PERIPHERAL=y -CONFIG_BT_NUS=y +CONFIG_BT_ZEPHYR_NUS=y CONFIG_UART_BT=y -CONFIG_BT_NUS_AUTO_START_BLUETOOTH=y +CONFIG_BT_ZEPHYR_NUS_AUTO_START_BLUETOOTH=y # Bluetooth optimizations to allow larger data packets. CONFIG_BT_RX_STACK_SIZE=2048 diff --git a/snippets/nus-console/README.rst b/snippets/nus-console/README.rst index 5d84343094b..10962681151 100644 --- a/snippets/nus-console/README.rst +++ b/snippets/nus-console/README.rst @@ -20,7 +20,7 @@ Hardware support for: - :kconfig:option:`CONFIG_BT` - :kconfig:option:`CONFIG_BT_PERIPHERAL` -- :kconfig:option:`CONFIG_BT_NUS` +- :kconfig:option:`CONFIG_BT_ZEPHYR_NUS` - :kconfig:option:`CONFIG_SERIAL` - :kconfig:option:`CONFIG_CONSOLE` - :kconfig:option:`CONFIG_UART_CONSOLE` diff --git a/snippets/nus-console/nus-console.conf b/snippets/nus-console/nus-console.conf index bae817ce562..6691d1c36e7 100644 --- a/snippets/nus-console/nus-console.conf +++ b/snippets/nus-console/nus-console.conf @@ -4,9 +4,9 @@ CONFIG_UART_CONSOLE=y CONFIG_BT=y CONFIG_BT_PERIPHERAL=y -CONFIG_BT_NUS=y +CONFIG_BT_ZEPHYR_NUS=y CONFIG_UART_BT=y -CONFIG_BT_NUS_AUTO_START_BLUETOOTH=y +CONFIG_BT_ZEPHYR_NUS_AUTO_START_BLUETOOTH=y # Bluetooth optimizations to allow larger data packets. CONFIG_BT_RX_STACK_SIZE=2048 diff --git a/subsys/bluetooth/services/CMakeLists.txt b/subsys/bluetooth/services/CMakeLists.txt index bb219891f0f..0955f202dae 100644 --- a/subsys/bluetooth/services/CMakeLists.txt +++ b/subsys/bluetooth/services/CMakeLists.txt @@ -17,6 +17,6 @@ if(CONFIG_BT_IAS OR CONFIG_BT_IAS_CLIENT) add_subdirectory(ias) endif() -if(CONFIG_BT_NUS) +if(CONFIG_BT_ZEPHYR_NUS) add_subdirectory(nus) endif() diff --git a/subsys/bluetooth/services/nus/CMakeLists.txt b/subsys/bluetooth/services/nus/CMakeLists.txt index a15271cba3c..347456d1831 100644 --- a/subsys/bluetooth/services/nus/CMakeLists.txt +++ b/subsys/bluetooth/services/nus/CMakeLists.txt @@ -9,6 +9,6 @@ zephyr_library_sources( nus_inst.c ) -zephyr_library_sources_ifdef(CONFIG_BT_NUS_AUTO_START_BLUETOOTH +zephyr_library_sources_ifdef(CONFIG_BT_ZEPHYR_NUS_AUTO_START_BLUETOOTH bt_nus_auto_start_bt.c ) diff --git a/subsys/bluetooth/services/nus/Kconfig.nus b/subsys/bluetooth/services/nus/Kconfig.nus index 1841226d7c7..9091dd91d88 100644 --- a/subsys/bluetooth/services/nus/Kconfig.nus +++ b/subsys/bluetooth/services/nus/Kconfig.nus @@ -1,12 +1,12 @@ # Copyright (c) 2024 Croxel, Inc. # SPDX-License-Identifier: Apache-2.0 -menuconfig BT_NUS +menuconfig BT_ZEPHYR_NUS bool "GATT Nordic UART Service" -if BT_NUS +if BT_ZEPHYR_NUS -config BT_NUS_DEFAULT_INSTANCE +config BT_ZEPHYR_NUS_DEFAULT_INSTANCE bool "Use default NUS Service instance" default y if !UART_BT help @@ -16,11 +16,11 @@ config BT_NUS_DEFAULT_INSTANCE BT_NUS_INST_DEFINE(), it may not be beneficial having an internal instance as well. -config BT_NUS_AUTO_START_BLUETOOTH +config BT_ZEPHYR_NUS_AUTO_START_BLUETOOTH bool "Auto-enable Bluetooth stack and start LE advertisements" help Auto-Enable the Bluetooth stack and start advertising with the NUS UUID. Useful to run applications that inherently do not deal with Bluetooth (e.g: Non-Bluetooth samples using UART over Bluetooth LE). -endif # BT_NUS +endif # BT_ZEPHYR_NUS diff --git a/subsys/bluetooth/services/nus/nus.c b/subsys/bluetooth/services/nus/nus.c index 3dc2fbe6ca1..1f6eec8c25f 100644 --- a/subsys/bluetooth/services/nus/nus.c +++ b/subsys/bluetooth/services/nus/nus.c @@ -49,7 +49,7 @@ int bt_nus_inst_cb_register(struct bt_nus_inst *instance, struct bt_nus_cb *cb, } if (!instance) { - if (IS_ENABLED(CONFIG_BT_NUS_DEFAULT_INSTANCE)) { + if (IS_ENABLED(CONFIG_BT_ZEPHYR_NUS_DEFAULT_INSTANCE)) { instance = bt_nus_inst_default(); } else { return -ENOTSUP; @@ -72,7 +72,7 @@ int bt_nus_inst_send(struct bt_conn *conn, } if (!instance) { - if (IS_ENABLED(CONFIG_BT_NUS_DEFAULT_INSTANCE)) { + if (IS_ENABLED(CONFIG_BT_ZEPHYR_NUS_DEFAULT_INSTANCE)) { instance = bt_nus_inst_default(); } else { return -ENOTSUP; diff --git a/subsys/bluetooth/services/nus/nus_inst.c b/subsys/bluetooth/services/nus/nus_inst.c index 0f88bb8dda8..bd3690f8a7d 100644 --- a/subsys/bluetooth/services/nus/nus_inst.c +++ b/subsys/bluetooth/services/nus/nus_inst.c @@ -6,7 +6,7 @@ #include "nus_internal.h" -#if defined(CONFIG_BT_NUS_DEFAULT_INSTANCE) +#if defined(CONFIG_BT_ZEPHYR_NUS_DEFAULT_INSTANCE) BT_NUS_INST_DEFINE(nus_def); struct bt_nus_inst *bt_nus_inst_default(void) { From 0b53f7a9fd8e8332b349e290dfa98989edff7372 Mon Sep 17 00:00:00 2001 From: Richard Wheatley Date: Thu, 28 Mar 2024 09:28:55 -0500 Subject: [PATCH 1696/2402] tests: drivers: counter: counter_basic_api Enable reliable_cancel_capable feature for Ambiq counter Signed-off-by: Richard Wheatley --- tests/drivers/counter/counter_basic_api/src/test_counter.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/drivers/counter/counter_basic_api/src/test_counter.c b/tests/drivers/counter/counter_basic_api/src/test_counter.c index defa820ffde..34f94e2fbd8 100644 --- a/tests/drivers/counter/counter_basic_api/src/test_counter.c +++ b/tests/drivers/counter/counter_basic_api/src/test_counter.c @@ -959,6 +959,11 @@ static bool reliable_cancel_capable(const struct device *dev) return true; } #endif +#ifdef CONFIG_COUNTER_AMBIQ + if (dev == DEVICE_DT_GET(DT_NODELABEL(counter0))) { + return true; + } +#endif #ifdef CONFIG_COUNTER_NXP_S32_SYS_TIMER if (single_channel_alarm_capable(dev)) { return true; From 2d8337181836f8a6eb15dc6a1273b811e64cb834 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Wed, 27 Mar 2024 14:43:47 -0500 Subject: [PATCH 1697/2402] soc: nxp: lpc55xxx: Remove duplicate INIT_PLL1 Remove duplicate definition of the INIT_PLL1 kconfig Signed-off-by: Declan Snyder --- soc/nxp/lpc/lpc55xxx/Kconfig.defconfig | 8 -------- 1 file changed, 8 deletions(-) diff --git a/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig b/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig index ed43f5041ed..80f20ada986 100644 --- a/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig +++ b/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig @@ -7,14 +7,6 @@ config NUM_IRQS # must be >= the highest interrupt number used default 60 -# In the LPC55XXX Family, this is currently being used to set the -# core clock value at it's highest frequency which clocks at 150MHz. -# Note that flash programming operations are limited to 100MHz, and -# this PLL should not be used as the core clock in those cases. -config INIT_PLL1 - default "y" - depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM) - config SYS_CLOCK_HW_CYCLES_PER_SEC default 144000000 if INIT_PLL1 default 96000000 From a7988f2986117a79eaf08beb3a301ef5cb0ee3d1 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 28 Mar 2024 10:46:28 -0500 Subject: [PATCH 1698/2402] soc: nxp: lpc55s69: Enable Sleep Mode Enable sleep mode on LPC55S69 (corresponding to zephyr's runtime idle mode). Add DT description and power api implementations. Signed-off-by: Declan Snyder --- dts/arm/nxp/nxp_lpc55S6x_common.dtsi | 10 ++++++++++ soc/nxp/lpc/lpc55xxx/CMakeLists.txt | 4 ++++ soc/nxp/lpc/lpc55xxx/Kconfig | 1 + soc/nxp/lpc/lpc55xxx/power.c | 28 ++++++++++++++++++++++++++++ 4 files changed, 43 insertions(+) create mode 100644 soc/nxp/lpc/lpc55xxx/power.c diff --git a/dts/arm/nxp/nxp_lpc55S6x_common.dtsi b/dts/arm/nxp/nxp_lpc55S6x_common.dtsi index 00cbb8fa0a5..107855d88d2 100644 --- a/dts/arm/nxp/nxp_lpc55S6x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S6x_common.dtsi @@ -31,6 +31,7 @@ reg = <0>; #address-cells = <1>; #size-cells = <1>; + cpu-power-states = <&sleep>; mpu: mpu@e000ed90 { compatible = "arm,armv8m-mpu"; @@ -41,6 +42,15 @@ compatible = "arm,cortex-m33"; reg = <1>; }; + + power-states { + sleep: sleep { + compatible = "zephyr,power-state"; + power-state-name = "runtime-idle"; + min-residency-us = <4>; + exit-latency-us = <4>; + }; + }; }; }; diff --git a/soc/nxp/lpc/lpc55xxx/CMakeLists.txt b/soc/nxp/lpc/lpc55xxx/CMakeLists.txt index 5f66a3eb9d8..429e41722f7 100644 --- a/soc/nxp/lpc/lpc55xxx/CMakeLists.txt +++ b/soc/nxp/lpc/lpc55xxx/CMakeLists.txt @@ -24,6 +24,10 @@ if(NOT DEFINED CONFIG_LPC55XXX_SRAM_CLOCKS) zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1) endif() +if (CONFIG_SOC_LPC55S69_CPU0) + zephyr_sources_ifdef(CONFIG_PM power.c) +endif() + zephyr_include_directories(.) set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/lpc/lpc55xxx/Kconfig b/soc/nxp/lpc/lpc55xxx/Kconfig index 2fcc3e4ee66..cc643ed97fd 100644 --- a/soc/nxp/lpc/lpc55xxx/Kconfig +++ b/soc/nxp/lpc/lpc55xxx/Kconfig @@ -68,6 +68,7 @@ config SOC_LPC55S69_CPU0 select HAS_MCUX_CTIMER select HAS_MCUX_SCTIMER select HAS_MCUX_RNG + select HAS_PM if SOC_SERIES_LPC55XXX diff --git a/soc/nxp/lpc/lpc55xxx/power.c b/soc/nxp/lpc/lpc55xxx/power.c new file mode 100644 index 00000000000..8a195ef7f0d --- /dev/null +++ b/soc/nxp/lpc/lpc55xxx/power.c @@ -0,0 +1,28 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +void pm_state_set(enum pm_state state, uint8_t id) +{ + ARG_UNUSED(id); + + switch (state) { + case PM_STATE_RUNTIME_IDLE: + k_cpu_idle(); + break; + default: + + break; + } +} + +void pm_state_exit_post_ops(enum pm_state state, uint8_t id) +{ + ARG_UNUSED(state); + ARG_UNUSED(id); +} From 1f55be8b42dfd54308038d1e422d8d4e0e7f39ab Mon Sep 17 00:00:00 2001 From: Iuliana Prodan Date: Tue, 26 Mar 2024 20:00:39 +0200 Subject: [PATCH 1699/2402] nxp: imx8: change CONFIG_SOC_ to match the value Change, for audio DSP and M7 cores, SOC_ to match the exact soc name. Update the board files accordingly. These configs are used in SOF and NXP_HAL, so change sha for these modules. Signed-off-by: Iuliana Prodan --- boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk | 4 ++-- boards/nxp/imx8mp_evk/board.cmake | 4 ++-- boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek | 2 +- boards/nxp/imx8qm_mek/board.cmake | 2 +- boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek | 2 +- boards/nxp/imx8qxp_mek/board.cmake | 2 +- .../Kconfig.mimx8mp_phyboard_pollux | 2 +- .../verdin_imx8mp/Kconfig.verdin_imx8mp | 2 +- .../clock_control/clock_control_mcux_ccm.c | 20 +++++++++---------- soc/nxp/imx/imx8/CMakeLists.txt | 2 +- soc/nxp/imx/imx8/Kconfig | 4 ++-- soc/nxp/imx/imx8/Kconfig.defconfig | 4 ++-- soc/nxp/imx/imx8/Kconfig.soc | 10 +++++----- soc/nxp/imx/imx8m/CMakeLists.txt | 4 ++-- soc/nxp/imx/imx8m/Kconfig | 10 +++++----- .../imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 | 4 ++-- .../imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp | 4 ++-- soc/nxp/imx/imx8m/Kconfig.soc | 16 +++++++-------- soc/nxp/imx/imx8x/CMakeLists.txt | 2 +- soc/nxp/imx/imx8x/Kconfig | 4 ++-- soc/nxp/imx/imx8x/Kconfig.defconfig | 4 ++-- soc/nxp/imx/imx8x/Kconfig.soc | 10 +++++----- submanifests/optional.yaml | 2 +- west.yml | 2 +- 24 files changed, 61 insertions(+), 61 deletions(-) diff --git a/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk b/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk index fbda0ccc10d..c967d6c81c1 100644 --- a/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk +++ b/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk @@ -3,6 +3,6 @@ config BOARD_IMX8MP_EVK select SOC_MIMX8ML8_A53 if BOARD_IMX8MP_EVK_MIMX8ML8_A53 || BOARD_IMX8MP_EVK_MIMX8ML8_A53_SMP - select SOC_MIMX8MP_ADSP if BOARD_IMX8MP_EVK_MIMX8ML8_ADSP - select SOC_MIMX8MP_M7 if BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR + select SOC_MIMX8ML8_ADSP if BOARD_IMX8MP_EVK_MIMX8ML8_ADSP + select SOC_MIMX8ML8_M7 if BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/nxp/imx8mp_evk/board.cmake b/boards/nxp/imx8mp_evk/board.cmake index 55a52a15b19..5a232f11d56 100644 --- a/boards/nxp/imx8mp_evk/board.cmake +++ b/boards/nxp/imx8mp_evk/board.cmake @@ -4,14 +4,14 @@ # SPDX-License-Identifier: Apache-2.0 # -if(CONFIG_SOC_MIMX8MP_ADSP) +if(CONFIG_SOC_MIMX8ML8_ADSP) board_set_flasher_ifnset(misc-flasher) board_finalize_runner_args(misc-flasher) board_set_rimage_target(imx8m) endif() -if(CONFIG_SOC_MIMX8MP_M7) +if(CONFIG_SOC_MIMX8ML8_M7) board_set_debugger_ifnset(jlink) board_set_flasher_ifnset(jlink) diff --git a/boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek b/boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek index f70580b800c..c8e271b78b1 100644 --- a/boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek +++ b/boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek @@ -4,5 +4,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_IMX8QM_MEK - select SOC_MIMX8QM_ADSP if BOARD_IMX8QM_MEK_MIMX8QM6_ADSP + select SOC_MIMX8QM6_ADSP if BOARD_IMX8QM_MEK_MIMX8QM6_ADSP select SOC_PART_NUMBER_MIMX8QM6AVUFF diff --git a/boards/nxp/imx8qm_mek/board.cmake b/boards/nxp/imx8qm_mek/board.cmake index ad24e2b6c35..ecb8129e6a0 100644 --- a/boards/nxp/imx8qm_mek/board.cmake +++ b/boards/nxp/imx8qm_mek/board.cmake @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -if(CONFIG_SOC_MIMX8QM_ADSP) +if(CONFIG_SOC_MIMX8QM6_ADSP) board_set_flasher_ifnset(misc-flasher) board_finalize_runner_args(misc-flasher) diff --git a/boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek b/boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek index fbd35d46b2f..f16d2393691 100644 --- a/boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek +++ b/boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek @@ -4,5 +4,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_IMX8QXP_MEK - select SOC_MIMX8QXP_ADSP if BOARD_IMX8QXP_MEK_MIMX8QX6_ADSP + select SOC_MIMX8QX6_ADSP if BOARD_IMX8QXP_MEK_MIMX8QX6_ADSP select SOC_PART_NUMBER_MIMX8QX6AVLFZ diff --git a/boards/nxp/imx8qxp_mek/board.cmake b/boards/nxp/imx8qxp_mek/board.cmake index 50123811d4d..94a724cc7a4 100644 --- a/boards/nxp/imx8qxp_mek/board.cmake +++ b/boards/nxp/imx8qxp_mek/board.cmake @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -if(CONFIG_SOC_MIMX8QXP_ADSP) +if(CONFIG_SOC_MIMX8QX6_ADSP) board_set_flasher_ifnset(misc-flasher) board_finalize_runner_args(misc-flasher) diff --git a/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux index 75165bf5a29..d0f63578fe2 100644 --- a/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux +++ b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux @@ -2,5 +2,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_MIMX8MP_PHYBOARD_POLLUX - select SOC_MIMX8MP_M7 if BOARD_MIMX8MP_PHYBOARD_POLLUX_MIMX8ML8_M7 + select SOC_MIMX8ML8_M7 if BOARD_MIMX8MP_PHYBOARD_POLLUX_MIMX8ML8_M7 select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp b/boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp index 41c84eb3690..018013dadf2 100644 --- a/boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp +++ b/boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp @@ -5,5 +5,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_VERDIN_IMX8MP - select SOC_MIMX8MP_M7 if BOARD_VERDIN_IMX8MP_MIMX8ML8_M7 || BOARD_VERDIN_IMX8MP_MIMX8ML8_M7_DDR + select SOC_MIMX8ML8_M7 if BOARD_VERDIN_IMX8MP_MIMX8ML8_M7 || BOARD_VERDIN_IMX8MP_MIMX8ML8_M7_DDR select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/drivers/clock_control/clock_control_mcux_ccm.c b/drivers/clock_control/clock_control_mcux_ccm.c index f3574f00532..371adf15bdc 100644 --- a/drivers/clock_control/clock_control_mcux_ccm.c +++ b/drivers/clock_control/clock_control_mcux_ccm.c @@ -12,7 +12,7 @@ #include #include -#if defined(CONFIG_SOC_MIMX8QM_ADSP) || defined(CONFIG_SOC_MIMX8QXP_ADSP) +#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP) #include
    #endif @@ -46,7 +46,7 @@ static const clock_ip_name_t uart_clocks[] = { #ifdef CONFIG_UART_MCUX_LPUART -#ifdef CONFIG_SOC_MIMX8QM_ADSP +#ifdef CONFIG_SOC_MIMX8QM6_ADSP static const clock_ip_name_t lpuart_clocks[] = { kCLOCK_DMA_Lpuart0, kCLOCK_DMA_Lpuart1, @@ -56,9 +56,9 @@ static const clock_ip_name_t lpuart_clocks[] = { }; static const uint32_t lpuart_rate = MHZ(80); -#endif /* CONFIG_SOC_MIMX8QM_ADSP */ +#endif /* CONFIG_SOC_MIMX8QM6_ADSP */ -#ifdef CONFIG_SOC_MIMX8QXP_ADSP +#ifdef CONFIG_SOC_MIMX8QX6_ADSP static const clock_ip_name_t lpuart_clocks[] = { kCLOCK_DMA_Lpuart0, kCLOCK_DMA_Lpuart1, @@ -67,7 +67,7 @@ static const clock_ip_name_t lpuart_clocks[] = { }; static const uint32_t lpuart_rate = MHZ(80); -#endif /* CONFIG_SOC_MIMX8QXP_ADSP */ +#endif /* CONFIG_SOC_MIMX8QX6_ADSP */ #endif /* CONFIG_UART_MCUX_LPUART */ @@ -88,7 +88,7 @@ static int mcux_ccm_on(const struct device *dev, return 0; #endif -#if defined(CONFIG_UART_MCUX_LPUART) && defined(CONFIG_SOC_MIMX8QM_ADSP) +#if defined(CONFIG_UART_MCUX_LPUART) && defined(CONFIG_SOC_MIMX8QM6_ADSP) case IMX_CCM_LPUART1_CLK: case IMX_CCM_LPUART2_CLK: case IMX_CCM_LPUART3_CLK: @@ -98,7 +98,7 @@ static int mcux_ccm_on(const struct device *dev, return 0; #endif -#if defined(CONFIG_UART_MCUX_LPUART) && defined(CONFIG_SOC_MIMX8QXP_ADSP) +#if defined(CONFIG_UART_MCUX_LPUART) && defined(CONFIG_SOC_MIMX8QX6_ADSP) case IMX_CCM_LPUART1_CLK: case IMX_CCM_LPUART2_CLK: case IMX_CCM_LPUART3_CLK: @@ -174,7 +174,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, #ifdef CONFIG_UART_MCUX_LPUART -#if defined(CONFIG_SOC_MIMX8QM_ADSP) +#if defined(CONFIG_SOC_MIMX8QM6_ADSP) case IMX_CCM_LPUART1_CLK: case IMX_CCM_LPUART2_CLK: case IMX_CCM_LPUART3_CLK: @@ -186,7 +186,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, *rate = CLOCK_GetIpFreq(lpuart_clocks[instance]); break; -#elif defined(CONFIG_SOC_MIMX8QXP_ADSP) +#elif defined(CONFIG_SOC_MIMX8QX6_ADSP) case IMX_CCM_LPUART1_CLK: case IMX_CCM_LPUART2_CLK: case IMX_CCM_LPUART3_CLK: @@ -428,7 +428,7 @@ static const struct clock_control_driver_api mcux_ccm_driver_api = { static int mcux_ccm_init(const struct device *dev) { -#if defined(CONFIG_SOC_MIMX8QM_ADSP) || defined(CONFIG_SOC_MIMX8QXP_ADSP) +#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP) sc_ipc_t ipc_handle; int ret; diff --git a/soc/nxp/imx/imx8/CMakeLists.txt b/soc/nxp/imx/imx8/CMakeLists.txt index 209de9c95ad..4fc32f81246 100644 --- a/soc/nxp/imx/imx8/CMakeLists.txt +++ b/soc/nxp/imx/imx8/CMakeLists.txt @@ -1,7 +1,7 @@ # Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_MIMX8QM_ADSP) +if(CONFIG_SOC_MIMX8QM6_ADSP) zephyr_include_directories(adsp) add_subdirectory(adsp) diff --git a/soc/nxp/imx/imx8/Kconfig b/soc/nxp/imx/imx8/Kconfig index 00615852d01..3783996db94 100644 --- a/soc/nxp/imx/imx8/Kconfig +++ b/soc/nxp/imx/imx8/Kconfig @@ -1,7 +1,7 @@ # Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 -config SOC_MIMX8QM_ADSP +config SOC_MIMX8QM6_ADSP select XTENSA select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") select XTENSA_RESET_VECTOR @@ -13,4 +13,4 @@ config SOC_MIMX8QM_ADSP select CPU_HAS_DCACHE config MCUX_CORE_SUFFIX - default "_dsp" if SOC_MIMX8QM_ADSP + default "_dsp" if SOC_MIMX8QM6_ADSP diff --git a/soc/nxp/imx/imx8/Kconfig.defconfig b/soc/nxp/imx/imx8/Kconfig.defconfig index 203c43b1214..74c0d582da3 100644 --- a/soc/nxp/imx/imx8/Kconfig.defconfig +++ b/soc/nxp/imx/imx8/Kconfig.defconfig @@ -3,7 +3,7 @@ if SOC_SERIES_IMX8 -if SOC_MIMX8QM_ADSP +if SOC_MIMX8QM6_ADSP config SYS_CLOCK_HW_CYCLES_PER_SEC default 666000000 @@ -40,6 +40,6 @@ config TEST_LOGGING_DEFAULTS default n depends on TEST -endif # SOC_MIMX8QM_ADSP +endif # SOC_MIMX8QM6_ADSP endif # SOC_SERIES_IMX8 diff --git a/soc/nxp/imx/imx8/Kconfig.soc b/soc/nxp/imx/imx8/Kconfig.soc index 46903a8437d..0a2acb08e4d 100644 --- a/soc/nxp/imx/imx8/Kconfig.soc +++ b/soc/nxp/imx/imx8/Kconfig.soc @@ -8,22 +8,22 @@ config SOC_SERIES_IMX8 config SOC_SERIES default "imx8" if SOC_SERIES_IMX8 -config SOC_MIMX8QM +config SOC_MIMX8QM6 bool select SOC_SERIES_IMX8 config SOC - default "mimx8qm6" if SOC_MIMX8QM + default "mimx8qm6" if SOC_MIMX8QM6 -config SOC_MIMX8QM_ADSP +config SOC_MIMX8QM6_ADSP bool - select SOC_MIMX8QM + select SOC_MIMX8QM6 help Enable support for NXP i.MX 8QM Audio DSP config SOC_TOOLCHAIN_NAME string - default "nxp_imx_adsp" if SOC_MIMX8QM_ADSP + default "nxp_imx_adsp" if SOC_MIMX8QM6_ADSP config SOC_PART_NUMBER_MIMX8QM6AVUFF bool diff --git a/soc/nxp/imx/imx8m/CMakeLists.txt b/soc/nxp/imx/imx8m/CMakeLists.txt index 8fdeaa518fa..38a08b77d87 100644 --- a/soc/nxp/imx/imx8m/CMakeLists.txt +++ b/soc/nxp/imx/imx8m/CMakeLists.txt @@ -1,7 +1,7 @@ # Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_MIMX8MP_ADSP) +if(CONFIG_SOC_MIMX8ML8_ADSP) zephyr_include_directories(adsp) add_subdirectory(adsp) @@ -48,6 +48,6 @@ if(CONFIG_SOC_MIMX8MQ6_M4) add_subdirectory(m4_quad) endif() -if(CONFIG_SOC_MIMX8MP_M7) +if(CONFIG_SOC_MIMX8ML8_M7) add_subdirectory(m7) endif() diff --git a/soc/nxp/imx/imx8m/Kconfig b/soc/nxp/imx/imx8m/Kconfig index 4020862a92c..562290ddfc8 100644 --- a/soc/nxp/imx/imx8m/Kconfig +++ b/soc/nxp/imx/imx8m/Kconfig @@ -39,7 +39,7 @@ config SOC_MIMX8MN6_A53 select HAS_MCUX_IOMUXC if PINCTRL select HAS_MCUX_RDC -config SOC_MIMX8MP_ADSP +config SOC_MIMX8ML8_ADSP select XTENSA select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") select XTENSA_RESET_VECTOR @@ -53,7 +53,7 @@ config SOC_MIMX8MP_ADSP select PINCTRL_IMX if HAS_MCUX_IOMUXC select CPU_HAS_DCACHE -config SOC_MIMX8MP_M7 +config SOC_MIMX8ML8_M7 select ARM select CPU_CORTEX_M7 select CPU_HAS_FPU @@ -81,9 +81,9 @@ config SOC_MIMX8MQ6_M4 config MCUX_CORE_SUFFIX default "_ca53" if SOC_MIMX8MM6_A53 || SOC_MIMX8MN6_A53 || SOC_MIMX8ML8_A53 - default "_dsp" if SOC_MIMX8MP_ADSP + default "_dsp" if SOC_MIMX8ML8_ADSP -if SOC_MIMX8MP_M7 +if SOC_MIMX8ML8_M7 choice CODE_LOCATION prompt "Code location selection" @@ -99,4 +99,4 @@ endchoice config INIT_VIDEO_PLL bool "Initialize Video PLL" -endif # SOC_MIMX8MP_M7 +endif # SOC_MIMX8ML8_M7 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 index acd7d02761d..dec2384897c 100644 --- a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 @@ -4,7 +4,7 @@ # Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 -if SOC_MIMX8MP_M7 +if SOC_MIMX8ML8_M7 config SOC string @@ -50,4 +50,4 @@ config PINCTRL_IMX default y if HAS_MCUX_IOMUXC depends on PINCTRL -endif # SOC_MIMX8MP_M7 +endif # SOC_MIMX8ML8_M7 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp index 6c29a2975f7..7687c561c3c 100644 --- a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp @@ -3,7 +3,7 @@ if SOC_SERIES_IMX8M -if SOC_MIMX8MP_ADSP +if SOC_MIMX8ML8_ADSP config SYS_CLOCK_HW_CYCLES_PER_SEC default 800000000 @@ -43,6 +43,6 @@ config TEST_LOGGING_DEFAULTS default n depends on TEST -endif # SOC_MIMX8MP_ADSP +endif # SOC_MIMX8ML8_ADSP endif # SOC_SERIES_IMX8M diff --git a/soc/nxp/imx/imx8m/Kconfig.soc b/soc/nxp/imx/imx8m/Kconfig.soc index ca93c3fcdeb..420de8b1776 100644 --- a/soc/nxp/imx/imx8m/Kconfig.soc +++ b/soc/nxp/imx/imx8m/Kconfig.soc @@ -24,25 +24,25 @@ config SOC_MIMX8MM6_M4 help NXP i.MX8MM M4 -config SOC_MIMX8MP +config SOC_MIMX8ML8 bool select SOC_SERIES_IMX8M config SOC_MIMX8ML8_A53 bool - select SOC_MIMX8MP + select SOC_MIMX8ML8 help NXP i.MX8MP A53 -config SOC_MIMX8MP_ADSP +config SOC_MIMX8ML8_ADSP bool - select SOC_MIMX8MP + select SOC_MIMX8ML8 help Enable support for NXP i.MX 8MPLUS Audio DSP -config SOC_MIMX8MP_M7 +config SOC_MIMX8ML8_M7 bool - select SOC_MIMX8MP + select SOC_MIMX8ML8 help Enable support for NXP i.MX 8MPLUS M7 MCU @@ -58,7 +58,7 @@ config SOC_MIMX8MQ6_M4 config SOC_TOOLCHAIN_NAME string - default "nxp_imx8m_adsp" if SOC_MIMX8MP_ADSP + default "nxp_imx8m_adsp" if SOC_MIMX8ML8_ADSP config SOC_MIMX8MN6 bool @@ -73,7 +73,7 @@ config SOC_MIMX8MN6_A53 config SOC default "mimx8mm6" if SOC_MIMX8MM6 default "mimx8mn6" if SOC_MIMX8MN6 - default "mimx8ml8" if SOC_MIMX8MP + default "mimx8ml8" if SOC_MIMX8ML8 default "mimx8mq6" if SOC_MIMX8MQ6 config SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/soc/nxp/imx/imx8x/CMakeLists.txt b/soc/nxp/imx/imx8x/CMakeLists.txt index af445cb9e57..ce3fc3ef4a7 100644 --- a/soc/nxp/imx/imx8x/CMakeLists.txt +++ b/soc/nxp/imx/imx8x/CMakeLists.txt @@ -1,7 +1,7 @@ # Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_MIMX8QXP_ADSP) +if(CONFIG_SOC_MIMX8QX6_ADSP) zephyr_include_directories(adsp) add_subdirectory(adsp) diff --git a/soc/nxp/imx/imx8x/Kconfig b/soc/nxp/imx/imx8x/Kconfig index 43e1bcfc98c..6c52f936c92 100644 --- a/soc/nxp/imx/imx8x/Kconfig +++ b/soc/nxp/imx/imx8x/Kconfig @@ -1,7 +1,7 @@ # Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 -config SOC_MIMX8QXP_ADSP +config SOC_MIMX8QX6_ADSP select XTENSA select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") select XTENSA_RESET_VECTOR @@ -13,4 +13,4 @@ config SOC_MIMX8QXP_ADSP select CPU_HAS_DCACHE config MCUX_CORE_SUFFIX - default "_dsp" if SOC_MIMX8QXP_ADSP + default "_dsp" if SOC_MIMX8QX6_ADSP diff --git a/soc/nxp/imx/imx8x/Kconfig.defconfig b/soc/nxp/imx/imx8x/Kconfig.defconfig index 2e3699d9532..e5b2de59a9c 100644 --- a/soc/nxp/imx/imx8x/Kconfig.defconfig +++ b/soc/nxp/imx/imx8x/Kconfig.defconfig @@ -3,7 +3,7 @@ if SOC_SERIES_IMX8X -if SOC_MIMX8QXP_ADSP +if SOC_MIMX8QX6_ADSP config SYS_CLOCK_HW_CYCLES_PER_SEC default 640000000 @@ -40,6 +40,6 @@ config TEST_LOGGING_DEFAULTS default n depends on TEST -endif # SOC_MIMX8QXP_ADSP +endif # SOC_MIMX8QX6_ADSP endif # SOC_SERIES_IMX8X diff --git a/soc/nxp/imx/imx8x/Kconfig.soc b/soc/nxp/imx/imx8x/Kconfig.soc index dc3c3de187f..5edd44dcd83 100644 --- a/soc/nxp/imx/imx8x/Kconfig.soc +++ b/soc/nxp/imx/imx8x/Kconfig.soc @@ -8,22 +8,22 @@ config SOC_SERIES_IMX8X config SOC_SERIES default "imx8x" if SOC_SERIES_IMX8X -config SOC_MIMX8QXP +config SOC_MIMX8QX6 bool select SOC_SERIES_IMX8X config SOC - default "mimx8qx6" if SOC_MIMX8QXP + default "mimx8qx6" if SOC_MIMX8QX6 -config SOC_MIMX8QXP_ADSP +config SOC_MIMX8QX6_ADSP bool - select SOC_MIMX8QXP + select SOC_MIMX8QX6 help Enable support for NXP i.MX 8QXP Audio DSP config SOC_TOOLCHAIN_NAME string - default "nxp_imx_adsp" if SOC_MIMX8QXP_ADSP + default "nxp_imx_adsp" if SOC_MIMX8QX6_ADSP config SOC_PART_NUMBER_MIMX8QX6AVLFZ bool diff --git a/submanifests/optional.yaml b/submanifests/optional.yaml index 79015e632fd..0f314ffd2c3 100644 --- a/submanifests/optional.yaml +++ b/submanifests/optional.yaml @@ -34,7 +34,7 @@ manifest: groups: - optional - name: sof - revision: 1c1dd3d83d85c3bd2bfd16f6d5bb101e764cb698 + revision: c11a3185afbc8e1b2a79916de3dfefaf326d9ad1 path: modules/audio/sof remote: upstream groups: diff --git a/west.yml b/west.yml index 574a96c792c..c940814ad42 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 384bb4f17245a7e6b2d83149309134597f1b8a69 + revision: 9d32c7382b6383a30ae6095e02f17f9acfa63e7a path: modules/hal/nxp groups: - hal From f3c93e0302b3d29d57a803df2fc227caa8bba554 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Th=C3=A9o=20Battrel?= Date: Mon, 18 Sep 2023 19:10:05 +0200 Subject: [PATCH 1700/2402] Documentation: Update shell completion doc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Remove OS specific instructions, instructions depend on the shell and are the same across OS; - Add fish shell to the documentation. Signed-off-by: Théo Battrel --- doc/develop/west/install.rst | 65 ++++++++++++++++++-------------- doc/develop/west/zephyr-cmds.rst | 1 + 2 files changed, 38 insertions(+), 28 deletions(-) diff --git a/doc/develop/west/install.rst b/doc/develop/west/install.rst index e9f877cbe3f..5ac0f6efaa4 100644 --- a/doc/develop/west/install.rst +++ b/doc/develop/west/install.rst @@ -48,50 +48,59 @@ APIs directly. See :ref:`west-apis` for details. Enabling shell completion ************************* -West currently supports shell completion in the following combinations of -platform and shell: +West currently supports shell completion in the following shells: -* Linux: bash -* macOS: bash -* Windows: not available +* bash +* zsh +* fish In order to enable shell completion, you will need to obtain the corresponding -completion script and have it sourced every time you enter a new shell session. +completion script and have it sourced. +Using the completion scripts: -To obtain the completion script you can use the ``west completion`` command:: +.. tabs:: - cd /path/to/zephyr/ - west completion bash > ~/west-completion.bash + .. group-tab:: bash -.. note:: + *One-time setup*: + + .. code-block:: bash + + source <(west completion bash) + + *Permanent setup*: + + .. code-block:: bash + + west completion bash > ~/west-completion.bash; echo "source ~/west-completion.bash" >> ~/.bashrc + + .. group-tab:: zsh + + *One-time setup*: + + .. code-block:: zsh + + source <(west completion zsh) - Remember to update your local copy of the completion script using ``west - completion`` when you update Zephyr. + *Permanent setup*: -Next, you need to import :file:`west-completion.bash` into your bash shell. + .. code-block:: zsh -On Linux, you have the following options: + west completion zsh > "${fpath[1]}/_west" -* Copy :file:`west-completion.bash` to :file:`/etc/bash_completion.d/`. -* Copy :file:`west-completion.bash` to - :file:`/usr/share/bash-completion/completions/`. -* Copy :file:`west-completion.bash` to a local folder and source it from your - :file:`~/.bashrc`. + .. group-tab:: fish -On macOS, you have the following options: + *One-time setup*: -* Copy :file:`west-completion.bash` to a local folder and source it from your - :file:`~/.bash_profile` -* Install the ``bash-completion`` package with ``brew``:: + .. code-block:: fish - brew install bash-completion + west completion fish | source - then source the main bash completion script in your :file:`~/.bash_profile`:: + *Permanent setup*: - source /usr/local/etc/profile.d/bash_completion.sh + .. code-block:: fish - and finally copy :file:`west-completion.bash` to - :file:`/usr/local/etc/bash_completion.d/`. + west completion fish > $HOME/.config/fish/completions/west.fish .. _PyPI: https://pypi.org/project/west/ diff --git a/doc/develop/west/zephyr-cmds.rst b/doc/develop/west/zephyr-cmds.rst index f6b2322e6a4..6037cb422b2 100644 --- a/doc/develop/west/zephyr-cmds.rst +++ b/doc/develop/west/zephyr-cmds.rst @@ -39,6 +39,7 @@ It currently supports the following shells: - bash - zsh +- fish Additional instructions are available in the command's help:: From da7b65735e56b477a6e2d8f42698d9d8fd6d3157 Mon Sep 17 00:00:00 2001 From: Renato Soma Date: Wed, 14 Feb 2024 14:31:00 -0300 Subject: [PATCH 1701/2402] drivers: sensors: Add driver for LM35 Add a driver implementation for the LM35 ADC temperature sensor Signed-off-by: Renato Soma --- drivers/sensor/CMakeLists.txt | 1 + drivers/sensor/Kconfig | 1 + drivers/sensor/lm35/CMakeLists.txt | 4 ++ drivers/sensor/lm35/Kconfig | 12 ++++ drivers/sensor/lm35/lm35.c | 109 +++++++++++++++++++++++++++++ dts/bindings/sensor/lm35.yaml | 20 ++++++ 6 files changed, 147 insertions(+) create mode 100644 drivers/sensor/lm35/CMakeLists.txt create mode 100644 drivers/sensor/lm35/Kconfig create mode 100644 drivers/sensor/lm35/lm35.c create mode 100644 dts/bindings/sensor/lm35.yaml diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 21da3166be6..bc7baade23b 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -81,6 +81,7 @@ add_subdirectory_ifdef(CONFIG_LIS2DU12 lis2du12) add_subdirectory_ifdef(CONFIG_LIS2DW12 lis2dw12) add_subdirectory_ifdef(CONFIG_LIS2MDL lis2mdl) add_subdirectory_ifdef(CONFIG_LIS3MDL lis3mdl) +add_subdirectory_ifdef(CONFIG_LM35 lm35) add_subdirectory_ifdef(CONFIG_LM75 lm75) add_subdirectory_ifdef(CONFIG_LM77 lm77) add_subdirectory_ifdef(CONFIG_LPS2XDF lps2xdf) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 64ce47dbe32..e9d1264abf8 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -161,6 +161,7 @@ source "drivers/sensor/lis2du12/Kconfig" source "drivers/sensor/lis2dw12/Kconfig" source "drivers/sensor/lis2mdl/Kconfig" source "drivers/sensor/lis3mdl/Kconfig" +source "drivers/sensor/lm35/Kconfig" source "drivers/sensor/lm75/Kconfig" source "drivers/sensor/lm77/Kconfig" source "drivers/sensor/lps2xdf/Kconfig" diff --git a/drivers/sensor/lm35/CMakeLists.txt b/drivers/sensor/lm35/CMakeLists.txt new file mode 100644 index 00000000000..f0227e8fb43 --- /dev/null +++ b/drivers/sensor/lm35/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(lm35.c) diff --git a/drivers/sensor/lm35/Kconfig b/drivers/sensor/lm35/Kconfig new file mode 100644 index 00000000000..a034f48fef2 --- /dev/null +++ b/drivers/sensor/lm35/Kconfig @@ -0,0 +1,12 @@ +# LM35 temperature sensor config + +# Copyright (c) 2024 Renato Soma +# SPDX-License-Identifier: Apache-2.0 + +config LM35 + bool "LM35 Temperature Sensor" + default y + depends on DT_HAS_LM35_ENABLED + select ADC + help + Enable the driver for the LM35 digital temperature Sensor diff --git a/drivers/sensor/lm35/lm35.c b/drivers/sensor/lm35/lm35.c new file mode 100644 index 00000000000..576741f937b --- /dev/null +++ b/drivers/sensor/lm35/lm35.c @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2024 Renato Soma + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT lm35 + +#include +#include +#include +#include +#include +#include + +#define LM35_GAIN ADC_GAIN_1 +#define LM35_REF ADC_REF_INTERNAL + +LOG_MODULE_REGISTER(LM35, CONFIG_SENSOR_LOG_LEVEL); + +struct lm35_data { + uint16_t raw; +}; + +struct lm35_config { + const struct device *adc; + uint8_t adc_channel; + struct adc_sequence adc_seq; + struct adc_channel_cfg ch_cfg; +}; + +static int lm35_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_AMBIENT_TEMP) { + return -ENOTSUP; + } + + const struct lm35_config *cfg = dev->config; + + return adc_read(cfg->adc, &cfg->adc_seq); +} + +static int lm35_channel_get(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_AMBIENT_TEMP) { + return -ENOTSUP; + } + + int err; + struct lm35_data *data = dev->data; + const struct lm35_config *cfg = dev->config; + int32_t mv = data->raw; + + err = adc_raw_to_millivolts(adc_ref_internal(cfg->adc), cfg->ch_cfg.gain, + cfg->adc_seq.resolution, &mv); + if (err) { + return err; + } + + /* LM35 computes linearly 10mV per 1 degree C */ + val->val1 = mv / 10; + val->val2 = (mv % 10) * 100000; + + return 0; +} + +static const struct sensor_driver_api lm35_driver_api = { + .sample_fetch = lm35_sample_fetch, + .channel_get = lm35_channel_get, +}; + +static int lm35_init(const struct device *dev) +{ + const struct lm35_config *cfg = dev->config; + + if (!device_is_ready(cfg->adc)) { + LOG_ERR("ADC device is not ready."); + return -EINVAL; + } + + adc_channel_setup(cfg->adc, &cfg->ch_cfg); + return 0; +} + +#define LM35_INST(inst) \ + static struct lm35_data lm35_data_##inst; \ + \ + static const struct lm35_config lm35_cfg_##inst = { \ + .adc = DEVICE_DT_GET(DT_INST_IO_CHANNELS_CTLR(inst)), \ + .adc_channel = DT_INST_IO_CHANNELS_INPUT(inst), \ + .adc_seq = \ + { \ + .channels = BIT(DT_INST_IO_CHANNELS_INPUT(inst)), \ + .buffer = &lm35_data_##inst.raw, \ + .buffer_size = sizeof(lm35_data_##inst.raw), \ + .resolution = DT_INST_PROP(inst, resolution), \ + }, \ + .ch_cfg = { \ + .gain = LM35_GAIN, \ + .reference = LM35_REF, \ + .acquisition_time = ADC_ACQ_TIME_DEFAULT, \ + .channel_id = DT_INST_IO_CHANNELS_INPUT(inst), \ + }}; \ + \ + SENSOR_DEVICE_DT_INST_DEFINE(inst, lm35_init, NULL, &lm35_data_##inst, &lm35_cfg_##inst, \ + POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &lm35_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(LM35_INST) diff --git a/dts/bindings/sensor/lm35.yaml b/dts/bindings/sensor/lm35.yaml new file mode 100644 index 00000000000..feb0306639c --- /dev/null +++ b/dts/bindings/sensor/lm35.yaml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +description: LM35 Digital Temperature Sensor + +compatible: "lm35" + +include: sensor-device.yaml + +properties: + io-channels: + required: true + description: | + ADC channel that will perform measurement + + resolution: + type: int + default: 12 + description: | + ADC resolution to be used for the channel. Defaults to 12 bits + as it's the most common for adc based drivers. From 50fb272f94ba373527d99e027308f91a2e79d05c Mon Sep 17 00:00:00 2001 From: Renato Soma Date: Wed, 14 Feb 2024 14:42:20 -0300 Subject: [PATCH 1702/2402] tests: drivers: add LM35 to build_all Add LM35 driver to build_all test Signed-off-by: Renato Soma --- tests/drivers/build_all/sensor/adc.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/drivers/build_all/sensor/adc.dtsi b/tests/drivers/build_all/sensor/adc.dtsi index 3ee9c2b8d42..b853ab0cad7 100644 --- a/tests/drivers/build_all/sensor/adc.dtsi +++ b/tests/drivers/build_all/sensor/adc.dtsi @@ -79,3 +79,9 @@ test_tdk_ntcg163jf103ft1: tdk-ntcg163jf103ft1 { pulldown-ohm = <10000>; connected-positive; }; + +test_lm35: lm35 { + compatible = "lm35"; + io-channels = <&adc0 0>; + status = "okay"; +}; From 14015db4abdd60c140c889fa84fb59a3385347fa Mon Sep 17 00:00:00 2001 From: Charles Dias Date: Sun, 18 Feb 2024 14:17:16 -0300 Subject: [PATCH 1703/2402] boards: arm: Add support for WeAct Studio MiniSTM32H743 Core board Adds the device trees, Kconfig, and documentation files. The following features have been confirmed working on hardware: * LED * Button * ST7735 TFT-LCD * External QuadSPI NOR Flash memory * External SPI NOR Flash memory * USB CDC ACM * microSD card Signed-off-by: Charles Dias --- boards/weact/mini_stm32h743/Kconfig.defconfig | 35 +++ .../mini_stm32h743/Kconfig.mini_stm32h743 | 5 + boards/weact/mini_stm32h743/board.cmake | 7 + boards/weact/mini_stm32h743/board.yml | 5 + .../mini_stm32h743/doc/img/stm32h7xx.webp | Bin 0 -> 26310 bytes boards/weact/mini_stm32h743/doc/index.rst | 242 ++++++++++++++++++ .../weact/mini_stm32h743/mini_stm32h743.dts | 210 +++++++++++++++ .../weact/mini_stm32h743/mini_stm32h743.yaml | 20 ++ .../mini_stm32h743/mini_stm32h743_defconfig | 29 +++ .../display/lvgl/boards/mini_stm32h743.conf | 5 + 10 files changed, 558 insertions(+) create mode 100644 boards/weact/mini_stm32h743/Kconfig.defconfig create mode 100644 boards/weact/mini_stm32h743/Kconfig.mini_stm32h743 create mode 100644 boards/weact/mini_stm32h743/board.cmake create mode 100644 boards/weact/mini_stm32h743/board.yml create mode 100644 boards/weact/mini_stm32h743/doc/img/stm32h7xx.webp create mode 100644 boards/weact/mini_stm32h743/doc/index.rst create mode 100644 boards/weact/mini_stm32h743/mini_stm32h743.dts create mode 100644 boards/weact/mini_stm32h743/mini_stm32h743.yaml create mode 100644 boards/weact/mini_stm32h743/mini_stm32h743_defconfig create mode 100644 samples/subsys/display/lvgl/boards/mini_stm32h743.conf diff --git a/boards/weact/mini_stm32h743/Kconfig.defconfig b/boards/weact/mini_stm32h743/Kconfig.defconfig new file mode 100644 index 00000000000..6817cc3f5f7 --- /dev/null +++ b/boards/weact/mini_stm32h743/Kconfig.defconfig @@ -0,0 +1,35 @@ +# WeAct Studio MiniSTM32H7 board configuration + +# Copyright (c) Charles Dias +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MINI_STM32H743 + +if DISPLAY + +config INPUT + default y + +if LVGL + +config LV_COLOR_16_SWAP + default y + +config LV_Z_BITS_PER_PIXEL + default 16 + +endif # LVGL + +endif # DISPLAY + +if USB_DEVICE_STACK + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y + +endif # USB_DEVICE_STACK + +endif # BOARD_MINI_STM32H743 diff --git a/boards/weact/mini_stm32h743/Kconfig.mini_stm32h743 b/boards/weact/mini_stm32h743/Kconfig.mini_stm32h743 new file mode 100644 index 00000000000..d61f0a580e9 --- /dev/null +++ b/boards/weact/mini_stm32h743/Kconfig.mini_stm32h743 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Charles Dias +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MINI_STM32H743 + select SOC_STM32H743XX diff --git a/boards/weact/mini_stm32h743/board.cmake b/boards/weact/mini_stm32h743/board.cmake new file mode 100644 index 00000000000..27c8f8c89fa --- /dev/null +++ b/boards/weact/mini_stm32h743/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32H743VI" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/weact/mini_stm32h743/board.yml b/boards/weact/mini_stm32h743/board.yml new file mode 100644 index 00000000000..0789b364dfa --- /dev/null +++ b/boards/weact/mini_stm32h743/board.yml @@ -0,0 +1,5 @@ +board: + name: mini_stm32h743 + vendor: weact + socs: + - name: stm32h743xx diff --git a/boards/weact/mini_stm32h743/doc/img/stm32h7xx.webp b/boards/weact/mini_stm32h743/doc/img/stm32h7xx.webp new file mode 100644 index 0000000000000000000000000000000000000000..7f92df0963b61e6eaebd78aa3be0d00a2a0d589e GIT binary patch literal 26310 zcmV(#K;*wtNk&G#W&i+JMM6+kP&gp6W&i*X5&@k7Du4li0X{Jpi9@0xp%YwHG#~>6 zv$tx0FG!K?A8oLNOhx*k=5@=N{#%;gX8Rp6-}5?#_}}<`QXbX(ALu`BAN0Lpe`)mz z{d)A*{|EN>-xv1(^Pia?1pi}yWj))!?SAL`zy8Vo_t<0lpZX75FII2e?_q!2k6B;* zAG&`IU*v!2{@Z)Y|GEF~*}2jW#ScfnLH&pOU-hrsAKfoj{~q~o=>OV(Uw^fK<^MbP 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zFo7Lj21K!GB+5nEZuy96_CF=ux7_!=|4vM%)F=#A;w3(YH(9Hpni7V`@>HI>a}uq9 zKdFKi0P2(1*bsP`0IWzWiIq`MJ$fD2Jjs=168utRmAYwd+>^wiW4vy%%b7tfbH5xl zI%_Wr!`MIqgB`cJ<70!{E z!E=lbfHD>Q4lAO;kR0RPSmQ26WqhicMjvp47QL^_S!*&Q1RpIVYA@XMGasYxeO_5l N4vJ}>n8&~X0044e7!Cjc literal 0 HcmV?d00001 diff --git a/boards/weact/mini_stm32h743/doc/index.rst b/boards/weact/mini_stm32h743/doc/index.rst new file mode 100644 index 00000000000..4a96538ac1b --- /dev/null +++ b/boards/weact/mini_stm32h743/doc/index.rst @@ -0,0 +1,242 @@ +.. mini_stm32h743: + +WeAct Studio MiniSTM32H743 Core Board +##################################### + +Overview +******** + +The MiniSTM32H743 Core board is a compact development board equipped with +an STM32H743VIT6 microcontroller. It features a variety of peripherals, +including a user LED and button, a display, and external SPI and QuadSPI +NOR flash memory. + +Key Features + +- STM32 microcontroller in LQFP100 package +- USB OTG or full-speed device +- 1 user LED +- User, boot, and reset push-buttons +- 32.768 kHz and 25MHz HSE crystal oscillators +- External NOR Flash memories: 64-Mbit Quad-SPI and 64-Mbit SPI +- Board connectors: + - Camera (8 bit) connector + - ST7735 TFT-LCD 160 x 80 pixels (RGB565 3-SPI) + - microSD |trade| card + - USB Type-C Connector + - SWD header for external debugger + - 2x 40-pin GPIO connector + +.. figure:: img/stm32h7xx.webp + :align: center + :alt: MiniSTM32H743 Core Board + + MiniSTM32H743 Core Board (Credit: WeAct Studio) + +More information about the board can be found on the `Mini_STM32H743 website`_. + +Hardware +******** + +The MiniSTM32H743 Core board provides the following hardware components: + +- STM32H743VIT6 in LQFP100 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 480 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 2 MB Flash +- ~1 MB SRAM +- High-resolution timer (2.1 ns) +- 32-bit timers(2) +- 16-bit timers(10) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN FD(2) +- SAI(4) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 82) with external interrupt capability +- 16-bit ADC(3) with 16 channels +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +More information about STM32H743 can be found here: + +- `STM32H743VI on www.st.com`_ +- `STM32H743/753 reference manual`_ +- `STM32H743VI datasheet`_ + +Supported Features +================== + +The mini_stm32h743 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | display | ++-----------+------------+-------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration per core can be found in the defconfig file: +``boards/weact/mini_stm32h743/mini_stm32h743_defconfig`` + +Pin Mapping +=========== + +MiniSTM32H743 Core board has 5 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `Mini_STM32H743 website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The MiniSTM32H743 Core board is configured as follows + +- USER_LED : PE3 +- USER_PB : PC13 +- SPI1 SCK/MISO/MOSI/NSS : PB3/PB4/PD7/PD6 (NOR Flash memory) +- SPI4 SCK/MOSI/NSS : PE12/PE14/PE11 (LCD) +- QuadSPI CLK/NCS/IO0/IO1/IO2/IO3 : PB2/PB6/PD11/PD12/PE2/PD13 (NOR Flash memory) +- SDMMC1 CLK/DCMD/CD/D0/D1/D2/D3 : PC12/PD2/PD4/PC8/PC9/PC10/PC11 (microSD card) +- USB DM/DP : PA11/PA12 (USB CDC ACM) + +System Clock +============ + +The STM32H743VI System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven +by the PLL clock at 240MHz. PLL clock is fed by a 25MHz high speed external clock. + +Serial Port (USB CDC ACM) +========================= + +The Zephyr console output is assigned to the USB CDC ACM virtual serial port. +Virtual COM port interface. Default communication settings are 115200 8N1. + +Programming and Debugging +************************* + +The MiniSTM32H743 Core board facilitates firmware flashing via the USB DFU +bootloader. This method simplifies the process of updating images, although +it doesn't provide debugging capabilities. However, the board provides header +pins for the Serial Wire Debug (SWD) interface, which can be used to connect +an external debugger, such as ST-Link. + +Flashing +======== + +To activate the bootloader, follow these steps: + +1. Press and hold the BOOT0 key. +2. While still holding the BOOT0 key, press and release the RESET key. +3. Wait for 0.5 seconds, then release the BOOT0 key. + +Upon successful execution of these steps, the device will transition into +bootloader mode and present itself as a USB DFU Mode device. You can program +the device using the west tool or the STM32CubeProgrammer. + +Flashing an application to MiniSTM32H743 +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +First, put the board in bootloader mode as described above. Then build and flash +the application in the usual way. Just add ``CONFIG_BOOT_DELAY=5000`` to the +configuration, so that USB CDC ACM is initialized before any text is printed, +as below: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mini_stm32h743 + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D -b 115200 + +Then, press the RESET button, you should see the following message after few seconds: + +.. code-block:: console + + Hello World! mini_stm32h743 + +Replace :code:`` with the port where the board XIAO BLE +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Debugging +--------- + +This current Zephyr port does not support debugging. + +Testing the LEDs in the MiniSTM32H743 +************************************* + +There is a sample that allows to test that LED on the board are working +properly with Zephyr: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: mini_stm32h743 + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The LED definitions can be found in +:zephyr_file:`boards/weact/mini_stm32h743/mini_stm32h743.dts`. + +Testing shell over USB in the MiniSTM32H743 +******************************************* + +There is a sample that allows to test shell interface over USB CDC ACM interface +with Zephyr: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/shell/shell_module + :board: mini_stm32h743 + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + +.. _Mini_STM32H743 website: + https://github.com/WeActStudio/MiniSTM32H7xx + +.. _STM32H743VI on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h743vi.html#overview + +.. _STM32H743/753 reference manual: + https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32H743VI datasheet: + https://www.st.com/resource/en/datasheet/stm32h743vi.pdf diff --git a/boards/weact/mini_stm32h743/mini_stm32h743.dts b/boards/weact/mini_stm32h743/mini_stm32h743.dts new file mode 100644 index 00000000000..0f604ea3985 --- /dev/null +++ b/boards/weact/mini_stm32h743/mini_stm32h743.dts @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2024 Charles Dias + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "WeAct Studio MiniSTM32H743 Core Board"; + compatible = "weact,mini-stm32h743"; + + chosen { + zephyr,console = &usb_cdc_acm_uart; + zephyr,shell-uart = &usb_cdc_acm_uart; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,display = &st7735r_tft; + }; + + leds { + compatible = "gpio-leds"; + user_led: led { + gpios = <&gpioe 3 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User PB"; + gpios = <&gpioc 13 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &user_led; + sw0 = &user_button; + spi-flash0 = &w25q64_spi; + watchdog0 = &iwdg; + sdhc0 = &sdmmc1; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hsi48 { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <5>; + mul-n = <96>; + div-p = <2>; + div-q = <10>; + div-r = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + d1cpre = <1>; + hpre = <2>; + d1ppre = <1>; + d2ppre1 = <1>; + d2ppre2 = <1>; + d3ppre = <1>; +}; + +&sdmmc1 { + pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 + &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 + &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; + pinctrl-names = "default"; + cd-gpios = <&gpiod 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; +}; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; + + usb_cdc_acm_uart: cdc_acm_uart { + compatible = "zephyr,cdc-acm-uart"; + }; +}; + +&quadspi { + pinctrl-names = "default"; + pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pb6 + &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pd12 + &quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pd13>; + flash-id = <1>; + status = "okay"; + + w25q64_qspi: qspi-nor-flash@90000000 { + compatible = "st,stm32-qspi-nor"; + reg = <0x90000000 DT_SIZE_M(64)>; /* 64 Mbits */ + qspi-max-frequency = <40000000>; + status = "okay"; + spi-bus-width = <4>; + writeoc = "PP_1_1_4"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + slot0_partition: partition@0 { + reg = <0x00000000 DT_SIZE_M(64)>; + }; + }; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_sck_pb3 &spi1_miso_pb4 &spi1_mosi_pd7>; + cs-gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + status = "okay"; + w25q64_spi: spi-nor-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + size = ; /* 64 Mbits */ + status = "okay"; + jedec-id = [ef 40 17]; + has-dpd; + t-enter-dpd = <3500>; + t-exit-dpd = <3500>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + storage_partition: partition@0 { + label = "storage"; + reg = <0x00000000 DT_SIZE_M(64)>; + }; + }; + }; +}; + +&spi4 { + pinctrl-0 = <&spi4_sck_pe12 &spi4_mosi_pe14>; + cs-gpios = <&gpioe 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + status = "okay"; + + st7735r_tft: st7735r@0 { + compatible = "sitronix,st7735r"; + spi-max-frequency = <20000000>; + reg = <0>; + cmd-data-gpios = <&gpioe 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioe 10 GPIO_ACTIVE_HIGH>; + width = <160>; + height = <80>; + inversion-on; + rgb-is-inverted; + x-offset = <1>; + y-offset = <26>; + pwctr1 = [A2 02 84]; + pwctr2 = [C5]; + pwctr3 = [0A 00]; + pwctr4 = [8A 2A]; + pwctr5 = [8A EE]; + invctr = <7>; + frmctr1 = [01 2C 2D]; + frmctr2 = [01 2C 2D]; + frmctr3 = [01 2C 2D 01 2C 2D]; + vmctr1 = <14>; + gamctrp1 = [02 1C 07 12 37 32 29 2D 29 25 2B 39 00 01 03 10]; + gamctrn1 = [03 1D 07 06 2E 2C 29 2D 2E 2E 37 3F 00 00 02 10]; + colmod = <5>; + /* Set D3 (RGB) bit to 1. LV_COLOR_16_SWAP is enabled by default in Kconfig */ + madctl = <120>; /* Set to <184> to rotate the image 180 degrees. */ + caset = [00 01 00 a0]; + raset = [00 1a 00 69]; + }; +}; + +&rng { + status = "okay"; +}; + +&backup_sram { + status = "okay"; +}; + +&iwdg1 { + status = "okay"; +}; diff --git a/boards/weact/mini_stm32h743/mini_stm32h743.yaml b/boards/weact/mini_stm32h743/mini_stm32h743.yaml new file mode 100644 index 00000000000..0ce1024b6d0 --- /dev/null +++ b/boards/weact/mini_stm32h743/mini_stm32h743.yaml @@ -0,0 +1,20 @@ +identifier: mini_stm32h743 +name: WeAct Studio MiniSTM32H743 Core Board +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 2048 +supported: + - gpio + - counter + - spi + - backup_sram + - watchdog + - usb + - sdhc + - qspi +vendor: weact diff --git a/boards/weact/mini_stm32h743/mini_stm32h743_defconfig b/boards/weact/mini_stm32h743/mini_stm32h743_defconfig new file mode 100644 index 00000000000..39e63d879a2 --- /dev/null +++ b/boards/weact/mini_stm32h743/mini_stm32h743_defconfig @@ -0,0 +1,29 @@ +# Copyright (c) Charles Dias +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable clocks +CONFIG_CLOCK_CONTROL=y + +# Enable pin controller +CONFIG_PINCTRL=y + +# Logger cannot use itself to log +CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y + +# Enable USB +CONFIG_USB_DEVICE_STACK=y diff --git a/samples/subsys/display/lvgl/boards/mini_stm32h743.conf b/samples/subsys/display/lvgl/boards/mini_stm32h743.conf new file mode 100644 index 00000000000..bbd8108f31c --- /dev/null +++ b/samples/subsys/display/lvgl/boards/mini_stm32h743.conf @@ -0,0 +1,5 @@ +# Copyright (c) Charles Dias +# SPDX-License-Identifier: Apache-2.0 + +# Enable SPI driver for ST7735R +CONFIG_ST7735R=y From 9afd8c905421321a0d8fe50f55d36c7d7ddb83c2 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 20 Mar 2024 16:39:58 +0200 Subject: [PATCH 1704/2402] drivers: clock: clock_control_mcux_pcc: rework clock ID computation In the case of some SOCs simply using the PCC base and clock offset to build the clock ID passed to the HAL is not sufficient since the clock ID may also contain some flags (e.g: see the case of i.MX8ULP). For such SOCs, we change the semantic of the value passed from the DTS (which is simply called "name", thus allowing us to interpret it differently from SOC to SOC) to an index in a LUT used to fetch the clock ID that can be safely passed to the HAL. For compatibility reasons, we also keep the old way and use it for SOCs which don't define such a LUT. The driver will decide which method to use based on the LUT size (i.e: if 0, use the old way, if != 0 use the new way). Signed-off-by: Laurentiu Mihalcea --- .../clock_control/clock_control_mcux_pcc.c | 71 ++++++++++++++++--- 1 file changed, 63 insertions(+), 8 deletions(-) diff --git a/drivers/clock_control/clock_control_mcux_pcc.c b/drivers/clock_control/clock_control_mcux_pcc.c index affb3f52cc3..4824b37068b 100644 --- a/drivers/clock_control/clock_control_mcux_pcc.c +++ b/drivers/clock_control/clock_control_mcux_pcc.c @@ -20,6 +20,8 @@ LOG_MODULE_REGISTER(clock_control_mcux_pcc); struct mcux_pcc_config { uint32_t base_address; + uint32_t *clocks; + uint32_t clock_num; }; #define DEV_BASE(dev) (((struct mcux_pcc_config *)(dev->config))->base_address) @@ -27,25 +29,60 @@ struct mcux_pcc_config { #define MAKE_PCC_REGADDR(base, offset) ((base) + (offset)) #endif -static inline clock_ip_name_t clock_ip(const struct device *dev, - clock_control_subsys_t sub_system) +static inline int get_clock_encoding(const struct device *dev, + clock_control_subsys_t sub_system, + uint32_t *clock_encoding) { - uint32_t offset = POINTER_TO_UINT(sub_system); + const struct mcux_pcc_config *cfg; + uint32_t clock_name; - return MAKE_PCC_REGADDR(DEV_BASE(dev), offset); + cfg = dev->config; + clock_name = POINTER_TO_UINT(sub_system); + + if (!cfg->clock_num) { + *clock_encoding = MAKE_PCC_REGADDR(DEV_BASE(dev), clock_name); + return 0; + } + + /* sanity check */ + if (clock_name >= cfg->clock_num) { + return -EINVAL; + } + + *clock_encoding = cfg->clocks[clock_name]; + + return 0; } static int mcux_pcc_on(const struct device *dev, clock_control_subsys_t sub_system) { - CLOCK_EnableClock(clock_ip(dev, sub_system)); + uint32_t clock_encoding; + int ret; + + ret = get_clock_encoding(dev, sub_system, &clock_encoding); + if (ret < 0) { + return ret; + } + + CLOCK_EnableClock(clock_encoding); + return 0; } static int mcux_pcc_off(const struct device *dev, clock_control_subsys_t sub_system) { - CLOCK_DisableClock(clock_ip(dev, sub_system)); + uint32_t clock_encoding; + int ret; + + ret = get_clock_encoding(dev, sub_system, &clock_encoding); + if (ret < 0) { + return ret; + } + + CLOCK_DisableClock(clock_encoding); + return 0; } @@ -53,7 +90,16 @@ static int mcux_pcc_get_rate(const struct device *dev, clock_control_subsys_t sub_system, uint32_t *rate) { - *rate = CLOCK_GetIpFreq(clock_ip(dev, sub_system)); + uint32_t clock_encoding; + int ret; + + ret = get_clock_encoding(dev, sub_system, &clock_encoding); + if (ret < 0) { + return ret; + } + + *rate = CLOCK_GetIpFreq(clock_encoding); + return 0; } @@ -63,9 +109,18 @@ static const struct clock_control_driver_api mcux_pcc_api = { .get_rate = mcux_pcc_get_rate, }; +/* this is empty for SOCs which don't need a translation from + * the clock ID passed through the DTS and the clock ID encoding + * from the HAL. For these SOCs, the clock ID will be built based + * on the value passed from the DTS and the PCC base. + */ +static uint32_t clocks[] = {}; + #define MCUX_PCC_INIT(inst) \ static const struct mcux_pcc_config mcux_pcc##inst##_config = { \ - .base_address = DT_INST_REG_ADDR(inst) \ + .base_address = DT_INST_REG_ADDR(inst), \ + .clocks = clocks, \ + .clock_num = ARRAY_SIZE(clocks), \ }; \ \ DEVICE_DT_INST_DEFINE(inst, \ From 139fcfa5f732de2c7e938f333e4d81b837302764 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 20 Mar 2024 16:47:20 +0200 Subject: [PATCH 1705/2402] drivers: clock: clock_control_mcux_pcc: add support for 8ULP This patch add supports for performing clock-related operations on i.MX8ULP. This consists of: 1) Adding a LUT. 2) Adding an initialization function meant to tell the HAL which rate the XTALs on the boards (EVK and EVK9) run at. This is used by the functions that compute the rate of an IP clock. Signed-off-by: Laurentiu Mihalcea --- .../clock_control/clock_control_mcux_pcc.c | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/clock_control/clock_control_mcux_pcc.c b/drivers/clock_control/clock_control_mcux_pcc.c index 4824b37068b..287bd6df1ec 100644 --- a/drivers/clock_control/clock_control_mcux_pcc.c +++ b/drivers/clock_control/clock_control_mcux_pcc.c @@ -109,12 +109,31 @@ static const struct clock_control_driver_api mcux_pcc_api = { .get_rate = mcux_pcc_get_rate, }; +static int mcux_pcc_init(const struct device *dev) +{ +#ifdef CONFIG_SOC_MIMX8UD7 + /* 8ULP's XTAL is set to 24MHz on EVK9. We keep + * this as SOC level because this should also be + * the case for the EVK board. + */ + CLOCK_SetXtal0Freq(24000000); +#endif /* CONFIG_SOC_MIMX8UD7 */ + return 0; +} + +#ifdef CONFIG_SOC_MIMX8UD7 +static uint32_t clocks[] = { + /* clocks managed through PCC4 */ + kCLOCK_Lpuart7, +}; +#else /* this is empty for SOCs which don't need a translation from * the clock ID passed through the DTS and the clock ID encoding * from the HAL. For these SOCs, the clock ID will be built based * on the value passed from the DTS and the PCC base. */ static uint32_t clocks[] = {}; +#endif /* CONFIG_SOC_MIMX8UD7 */ #define MCUX_PCC_INIT(inst) \ static const struct mcux_pcc_config mcux_pcc##inst##_config = { \ @@ -124,7 +143,7 @@ static uint32_t clocks[] = {}; }; \ \ DEVICE_DT_INST_DEFINE(inst, \ - NULL, \ + &mcux_pcc_init, \ NULL, \ NULL, &mcux_pcc##inst##_config, \ PRE_KERNEL_1, \ From 02f18bc5f53cfa483ac48354c4427f2207e66066 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 20 Mar 2024 16:53:42 +0200 Subject: [PATCH 1706/2402] nxp: imx8ulp: enable clock control Enable clock control for i.MX8ULP. This consists of: 1) Adding a PCC node in the DTS 2) Adding a header file containing the definitions of the clocks used by the peripherals to be enabled. Signed-off-by: Laurentiu Mihalcea --- .../imx8ulp_evk_mimx8ud7_adsp_defconfig | 2 ++ dts/xtensa/nxp/nxp_imx8ulp.dtsi | 7 +++++++ .../zephyr/dt-bindings/clock/imx8ulp_clock.h | 18 ++++++++++++++++++ 3 files changed, 27 insertions(+) create mode 100644 include/zephyr/dt-bindings/clock/imx8ulp_clock.h diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp_defconfig b/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp_defconfig index e8d594b3070..5c0df6aa56f 100644 --- a/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp_defconfig +++ b/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp_defconfig @@ -5,3 +5,5 @@ CONFIG_BUILD_OUTPUT_BIN=n CONFIG_DYNAMIC_INTERRUPTS=y CONFIG_LOG=y + +CONFIG_CLOCK_CONTROL=y diff --git a/dts/xtensa/nxp/nxp_imx8ulp.dtsi b/dts/xtensa/nxp/nxp_imx8ulp.dtsi index 71f3de1958b..f0e308f2c77 100644 --- a/dts/xtensa/nxp/nxp_imx8ulp.dtsi +++ b/dts/xtensa/nxp/nxp_imx8ulp.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { cpus { @@ -30,4 +31,10 @@ compatible = "mmio-sram"; reg = <0x8e800000 DT_SIZE_K(512)>; }; + + pcc4: clock-controller@29800000 { + compatible = "nxp,kinetis-pcc"; + reg = <0x29800000 DT_SIZE_K(64)>; + #clock-cells = <2>; + }; }; diff --git a/include/zephyr/dt-bindings/clock/imx8ulp_clock.h b/include/zephyr/dt-bindings/clock/imx8ulp_clock.h new file mode 100644 index 00000000000..3de43dc3e96 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/imx8ulp_clock.h @@ -0,0 +1,18 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_ +#define _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_ + +/* IMPORTANT: the indexes used by these macros need to + * match the indexes in the PCC driver LUT at which the + * corresponding clock ID encoding can be found. + */ + +/* clocks managed by PCC4 */ +#define IMX8ULP_CLOCK_LPUART7 0 + +#endif /* _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_ */ From f4f3ab7df2a00ab821f1564d4d6fd50bdd701ce6 Mon Sep 17 00:00:00 2001 From: Trung Hieu Le Date: Mon, 25 Mar 2024 17:15:05 +0100 Subject: [PATCH 1707/2402] boards: shields: rk055hdmipi4ma0: fix pixelclk-active issue On the RT1170-EVKB, the framebuffer displays incorrectly (shifted by about 1/4 of the screen width). This is because pixelclk-active was set to 1 (which corresponds to kELCDIF_DriveDataOnRisingClkEdge). According to the HX8394 datasheet, the DSI transfert begins at the uprising pixel clock and stop at the falling pixel clock. So, pixelclk-active needs to be set to 0 (which corresponds to kELCDIF_DriveDataOnFallingClkEdge). Signed-off-by: Trung Hieu Le --- boards/shields/rk055hdmipi4ma0/rk055hdmipi4ma0.overlay | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/shields/rk055hdmipi4ma0/rk055hdmipi4ma0.overlay b/boards/shields/rk055hdmipi4ma0/rk055hdmipi4ma0.overlay index 0f4e0c9ce45..7df9f53b6a3 100644 --- a/boards/shields/rk055hdmipi4ma0/rk055hdmipi4ma0.overlay +++ b/boards/shields/rk055hdmipi4ma0/rk055hdmipi4ma0.overlay @@ -49,7 +49,7 @@ hsync-active = <0>; vsync-active = <0>; de-active = <1>; - pixelclk-active = <1>; + pixelclk-active = <0>; /* * Pixel clock is given by the following formula: * (height + vsync-len + vfront-porch + vback-porch) * From 9a133aedcc9c32755c379f5867c73ab8b0f1ad7e Mon Sep 17 00:00:00 2001 From: Trung Hieu Le Date: Mon, 25 Mar 2024 17:17:42 +0100 Subject: [PATCH 1708/2402] boards: shields: rk055hdmipi4m: fix pixelclk-active issue On the RT1170-EVKB, the framebuffer displays incorrectly (shifted by about 1/4 of the screen width). This is because pixelclk-active was set to 1 (which corresponds to kELCDIF_DriveDataOnRisingClkEdge). According to the RM68200 datasheet, the DSI transfert begins at the uprising pixel clock and stop at the falling pixel clock. So, pixelclk-active needs to be set to 0 (which corresponds to kELCDIF_DriveDataOnFallingClkEdge). Signed-off-by: Trung Hieu Le --- boards/shields/rk055hdmipi4m/rk055hdmipi4m.overlay | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/shields/rk055hdmipi4m/rk055hdmipi4m.overlay b/boards/shields/rk055hdmipi4m/rk055hdmipi4m.overlay index 4740ee664f1..58e610fc59e 100644 --- a/boards/shields/rk055hdmipi4m/rk055hdmipi4m.overlay +++ b/boards/shields/rk055hdmipi4m/rk055hdmipi4m.overlay @@ -49,7 +49,7 @@ hsync-active = <0>; vsync-active = <0>; de-active = <1>; - pixelclk-active = <1>; + pixelclk-active = <0>; /* * Pixel clock is given by the following formula: * (height + vsync-len + vfront-porch + vback-porch) * From 0967f13c3f11366097b4716bfc4dd2a86ed95168 Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Thu, 21 Mar 2024 16:30:38 +0800 Subject: [PATCH 1709/2402] ITE: drivers/i2c: Add a property selecting to drive I2C recovery mode Add a property to select the push-pull GPIO output type to drive the I2C recovery. The default is open-drain. Signed-off-by: Tim Lin --- drivers/i2c/i2c_ite_enhance.c | 8 ++++++-- drivers/i2c/i2c_ite_it8xxx2.c | 8 ++++++-- dts/bindings/i2c/ite,common-i2c.yaml | 6 ++++++ 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/i2c_ite_enhance.c b/drivers/i2c/i2c_ite_enhance.c index bea5ddefdb9..c97a1b5655b 100644 --- a/drivers/i2c/i2c_ite_enhance.c +++ b/drivers/i2c/i2c_ite_enhance.c @@ -75,6 +75,7 @@ struct i2c_enhance_config { uint32_t clock_gate_offset; bool target_enable; bool target_pio_mode; + bool push_pull_recovery; }; enum i2c_pin_fun { @@ -1267,10 +1268,12 @@ static int i2c_enhance_recover_bus(const struct device *dev) const struct i2c_enhance_config *config = dev->config; int i, status; + /* Output type selection */ + gpio_flags_t flags = GPIO_OUTPUT | (config->push_pull_recovery ? 0 : GPIO_OPEN_DRAIN); /* Set SCL of I2C as GPIO pin */ - gpio_pin_configure_dt(&config->scl_gpios, GPIO_OUTPUT | GPIO_OPEN_DRAIN); + gpio_pin_configure_dt(&config->scl_gpios, flags); /* Set SDA of I2C as GPIO pin */ - gpio_pin_configure_dt(&config->sda_gpios, GPIO_OUTPUT | GPIO_OPEN_DRAIN); + gpio_pin_configure_dt(&config->sda_gpios, flags); /* * In I2C recovery bus, 1ms sleep interval for bitbanging i2c @@ -1492,6 +1495,7 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_I2C_TARGET_BUFFER_MODE), .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ .target_enable = DT_INST_PROP(inst, target_enable), \ .target_pio_mode = DT_INST_PROP(inst, target_pio_mode), \ + .push_pull_recovery = DT_INST_PROP(inst, push_pull_recovery), \ }; \ \ static struct i2c_enhance_data i2c_enhance_data_##inst; \ diff --git a/drivers/i2c/i2c_ite_it8xxx2.c b/drivers/i2c/i2c_ite_it8xxx2.c index 4f130e3aaa2..b639d4e5377 100644 --- a/drivers/i2c/i2c_ite_it8xxx2.c +++ b/drivers/i2c/i2c_ite_it8xxx2.c @@ -53,6 +53,7 @@ struct i2c_it8xxx2_config { const struct pinctrl_dev_config *pcfg; uint32_t clock_gate_offset; bool fifo_enable; + bool push_pull_recovery; }; enum i2c_pin_fun { @@ -1190,10 +1191,12 @@ static int i2c_it8xxx2_recover_bus(const struct device *dev) const struct i2c_it8xxx2_config *config = dev->config; int i, status; + /* Output type selection */ + gpio_flags_t flags = GPIO_OUTPUT | (config->push_pull_recovery ? 0 : GPIO_OPEN_DRAIN); /* Set SCL of I2C as GPIO pin */ - gpio_pin_configure_dt(&config->scl_gpios, GPIO_OUTPUT | GPIO_OPEN_DRAIN); + gpio_pin_configure_dt(&config->scl_gpios, flags); /* Set SDA of I2C as GPIO pin */ - gpio_pin_configure_dt(&config->sda_gpios, GPIO_OUTPUT | GPIO_OPEN_DRAIN); + gpio_pin_configure_dt(&config->sda_gpios, flags); /* * In I2C recovery bus, 1ms sleep interval for bitbanging i2c @@ -1302,6 +1305,7 @@ DT_INST_FOREACH_STATUS_OKAY(I2C_IT8XXX2_CHECK_SUPPORTED_CLOCK) .clock_gate_offset = DT_INST_PROP(inst, clock_gate_offset), \ .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ .fifo_enable = DT_INST_PROP(inst, fifo_enable), \ + .push_pull_recovery = DT_INST_PROP(inst, push_pull_recovery), \ }; \ \ static struct i2c_it8xxx2_data i2c_it8xxx2_data_##inst; \ diff --git a/dts/bindings/i2c/ite,common-i2c.yaml b/dts/bindings/i2c/ite,common-i2c.yaml index 1e4e90793da..1245c0cd78d 100644 --- a/dts/bindings/i2c/ite,common-i2c.yaml +++ b/dts/bindings/i2c/ite,common-i2c.yaml @@ -102,3 +102,9 @@ properties: pinctrl-names: required: true + + push-pull-recovery: + type: boolean + description: | + This property is enabled when selecting the push-pull GPIO output + type to drive the I2C recovery. The default is open-drain. From 820a70242f443126b1dad2f94f6c89924321dcb4 Mon Sep 17 00:00:00 2001 From: cyliang tw Date: Wed, 27 Mar 2024 12:09:55 +0800 Subject: [PATCH 1710/2402] drivers: spi: support for Nuvoton numaker m2l31x Update m2l31x.dtsi for spi support and update spi_numaker.c for dummy TX data. Signed-off-by: cyliang tw --- drivers/spi/spi_numaker.c | 10 +++++++++ dts/arm/nuvoton/m2l31x.dtsi | 44 +++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/drivers/spi/spi_numaker.c b/drivers/spi/spi_numaker.c index eda34014ebb..104439e9a56 100644 --- a/drivers/spi/spi_numaker.c +++ b/drivers/spi/spi_numaker.c @@ -186,6 +186,16 @@ static int spi_numaker_txrx(const struct device *dev) } LOG_DBG("%s --> TX [0x%x] done", __func__, tx_frame); + } else { + /* Write dummy data to TX register */ + SPI_WRITE_TX(dev_cfg->spi, 0x00U); + time_out_cnt = SystemCoreClock; /* 1 second time-out */ + while (SPI_IS_BUSY(dev_cfg->spi)) { + if (--time_out_cnt == 0) { + LOG_ERR("Wait for SPI time-out"); + return -EIO; + } + } } /* Read received data */ diff --git a/dts/arm/nuvoton/m2l31x.dtsi b/dts/arm/nuvoton/m2l31x.dtsi index 00af64b124c..51d38c3ee62 100644 --- a/dts/arm/nuvoton/m2l31x.dtsi +++ b/dts/arm/nuvoton/m2l31x.dtsi @@ -213,6 +213,50 @@ status = "disabled"; interrupts = <21 2>; }; + + spi0: spi@40061000 { + compatible = "nuvoton,numaker-spi"; + reg = <0x40061000 0x6c>; + interrupts = <23 0>; + resets = <&rst NUMAKER_SPI0_RST>; + clocks = <&pcc NUMAKER_SPI0_MODULE NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@40062000 { + compatible = "nuvoton,numaker-spi"; + reg = <0x40062000 0x6c>; + interrupts = <51 0>; + resets = <&rst NUMAKER_SPI1_RST>; + clocks = <&pcc NUMAKER_SPI1_MODULE NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@40063000 { + compatible = "nuvoton,numaker-spi"; + reg = <0x40063000 0x6c>; + interrupts = <52 0>; + resets = <&rst NUMAKER_SPI2_RST>; + clocks = <&pcc NUMAKER_SPI2_MODULE NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@40064000 { + compatible = "nuvoton,numaker-spi"; + reg = <0x40064000 0x6c>; + interrupts = <62 0>; + resets = <&rst NUMAKER_SPI3_RST>; + clocks = <&pcc NUMAKER_SPI3_MODULE NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; From fc69f25202a27b3d0b80f191d524f8a4b4f20232 Mon Sep 17 00:00:00 2001 From: cyliang tw Date: Wed, 27 Mar 2024 12:13:35 +0800 Subject: [PATCH 1711/2402] tests: drivers: spi: spi_loopback: support numaker_m2l31ki Add support for Nuvoton numaker board numaker_m2l31ki. Signed-off-by: cyliang tw --- .../spi_loopback/boards/numaker_m2l31ki.conf | 1 + .../boards/numaker_m2l31ki.overlay | 33 +++++++++++++++++++ west.yml | 2 +- 3 files changed, 35 insertions(+), 1 deletion(-) create mode 100644 tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.conf create mode 100644 tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.conf b/tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.conf new file mode 100644 index 00000000000..3d2da209abc --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.conf @@ -0,0 +1 @@ +CONFIG_SPI_ASYNC=n diff --git a/tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.overlay b/tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.overlay new file mode 100644 index 00000000000..a910f60637e --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.overlay @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +&pinctrl { +/* EVB's NU5: SS/CLK/MISO/MOSI */ + spi0_default: spi0_default { + group0 { + pinmux = , + , + , + ; + }; + }; +}; + +&gpioa { + status = "okay"; +}; + +&spi0 { + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <500000>; + }; + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = <16000000>; + }; + status = "okay"; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; +}; diff --git a/west.yml b/west.yml index c940814ad42..4c382cc4fbc 100644 --- a/west.yml +++ b/west.yml @@ -188,7 +188,7 @@ manifest: groups: - hal - name: hal_nuvoton - revision: cf24f9ebd893b349cec439ef7eaac6554a6b6d6f + revision: 34efb92e37bd07043a2cab7fff847d8443d930f9 path: modules/hal/nuvoton groups: - hal From f4c73105e55a08ba1f463c3050771c37e15f05e7 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Thu, 28 Mar 2024 17:44:10 +0200 Subject: [PATCH 1712/2402] drivers: dai: sai: add pinctrl support Add support for performing pinctrl operations. For now, the only supported operation is applying the pinctrl default state. Pinctrl is left optional to allow for scenarios in which this is not required (e.g: AMP system in which another OS configures the pinctrl). Signed-off-by: Laurentiu Mihalcea --- drivers/dai/nxp/sai/Kconfig.sai | 1 + drivers/dai/nxp/sai/sai.c | 11 +++++++++++ drivers/dai/nxp/sai/sai.h | 2 ++ dts/bindings/dai/nxp,dai-sai.yaml | 2 +- 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/dai/nxp/sai/Kconfig.sai b/drivers/dai/nxp/sai/Kconfig.sai index 04c1ff7a430..9fc5bb052fd 100644 --- a/drivers/dai/nxp/sai/Kconfig.sai +++ b/drivers/dai/nxp/sai/Kconfig.sai @@ -5,6 +5,7 @@ config DAI_NXP_SAI bool "NXP Synchronous Audio Interface (SAI) driver" default y depends on DT_HAS_NXP_DAI_SAI_ENABLED + select PINCTRL help Select this to enable NXP SAI driver. diff --git a/drivers/dai/nxp/sai/sai.c b/drivers/dai/nxp/sai/sai.c index 9af53287eb5..c61e6115a80 100644 --- a/drivers/dai/nxp/sai/sai.c +++ b/drivers/dai/nxp/sai/sai.c @@ -831,6 +831,14 @@ static int sai_init(const struct device *dev) LOG_DBG("clock %s has been ungated", cfg->clk_data.clock_names[i]); } + /* note: optional operation so -ENOENT is allowed (i.e: we + * allow the default state to not be defined) + */ + ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT); + if (ret < 0 && ret != -ENOENT) { + return ret; + } + /* set TX/RX default states */ data->tx_state = DAI_STATE_NOT_READY; data->rx_state = DAI_STATE_NOT_READY; @@ -843,6 +851,8 @@ static int sai_init(const struct device *dev) #define SAI_INIT(inst) \ \ +PINCTRL_DT_INST_DEFINE(inst); \ + \ BUILD_ASSERT(SAI_FIFO_DEPTH(inst) > 0 && \ SAI_FIFO_DEPTH(inst) <= _SAI_FIFO_DEPTH(inst), \ "invalid FIFO depth"); \ @@ -910,6 +920,7 @@ static struct sai_config sai_config_##inst = { \ .rx_sync_mode = SAI_RX_SYNC_MODE(inst), \ .tx_dline = SAI_TX_DLINE_INDEX(inst), \ .rx_dline = SAI_RX_DLINE_INDEX(inst), \ + .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ }; \ \ static struct sai_data sai_data_##inst = { \ diff --git a/drivers/dai/nxp/sai/sai.h b/drivers/dai/nxp/sai/sai.h index 10296717e83..2fa890e9811 100644 --- a/drivers/dai/nxp/sai/sai.h +++ b/drivers/dai/nxp/sai/sai.h @@ -7,6 +7,7 @@ #define ZEPHYR_DRIVERS_DAI_NXP_SAI_H_ #include +#include #include #include @@ -271,6 +272,7 @@ struct sai_config { void (*irq_config)(void); uint32_t tx_dline; uint32_t rx_dline; + const struct pinctrl_dev_config *pincfg; }; /* this needs to perfectly match SOF's struct sof_ipc_dai_sai_params */ diff --git a/dts/bindings/dai/nxp,dai-sai.yaml b/dts/bindings/dai/nxp,dai-sai.yaml index ec2bc88c392..2d9f7e34997 100644 --- a/dts/bindings/dai/nxp,dai-sai.yaml +++ b/dts/bindings/dai/nxp,dai-sai.yaml @@ -5,7 +5,7 @@ description: NXP Synchronous Audio Interface (SAI) node compatible: "nxp,dai-sai" -include: base.yaml +include: [base.yaml, pinctrl-device.yaml] properties: reg: From 34410d536654aa67c9b57352ec3a349d5f6f0cfd Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Fri, 29 Mar 2024 11:49:08 +0200 Subject: [PATCH 1713/2402] boards: nxp: imx8qxp_mek: add pinctrl for SAI1 node Add pinctrl for SAI1 node. This means: 1) Adding definitions for the pads used by SAI1. 2) Creating a pin group and referencing it in the SAI1 node via the `pinctrl-0` property. Signed-off-by: Laurentiu Mihalcea --- .../imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi | 25 +++++++++++++++++++ .../imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts | 5 ++++ .../dt-bindings/pinctrl/imx8qxp-pinctrl.h | 8 ++++++ 3 files changed, 38 insertions(+) diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi index 18cfb473257..33ba2c5446c 100644 --- a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi @@ -14,6 +14,22 @@ iomuxc_uart2_tx_uart2_tx: IOMUXC_UART2_TX_UART2_TX { pinmux = ; }; + + iomuxc_adma_sai1_txfs_sai1_rxfs: IOMUXC_ADMA_SAI1_TXFS_SAI1_RXFS { + pinmux = ; + }; + + iomuxc_adma_sai1_rxd_sai1_rxd: IOMUXC_ADMA_SAI1_RXD_SAI1_RXD { + pinmux = ; + }; + + iomuxc_adma_sai1_txc_sai1_rxc: IOMUXC_ADMA_SAI1_TXC_SAI1_RXC { + pinmux = ; + }; + + iomuxc_adma_sai1_txd_spi0_cs1: IOMUXC_ADMA_SAI1_TXD_SPI0_CS1 { + pinmux = ; + }; }; &pinctrl { @@ -23,4 +39,13 @@ <&iomuxc_uart2_tx_uart2_tx>; }; }; + + sai1_default: sai1_default { + group0 { + pinmux = <&iomuxc_adma_sai1_txfs_sai1_rxfs>, + <&iomuxc_adma_sai1_rxd_sai1_rxd>, + <&iomuxc_adma_sai1_txc_sai1_rxc>, + <&iomuxc_adma_sai1_txd_spi0_cs1>; + }; + }; }; diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts index 38974c7ca39..f7b1d061d1a 100644 --- a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts @@ -27,6 +27,11 @@ pinctrl-names = "default"; }; +&sai1 { + pinctrl-0 = <&sai1_default>; + pinctrl-names = "default"; +}; + &irqsteer { reg = <0x51080000 DT_SIZE_K(64)>; }; diff --git a/include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h index 0143540f6bf..da5f76b9da3 100644 --- a/include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h @@ -8,11 +8,19 @@ #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_ /* values for pad field */ +#define SC_P_SAI1_RXD 86 +#define SC_P_SAI1_RXC 87 +#define SC_P_SAI1_RXFS 88 +#define SC_P_SPI0_CS1 96 #define SC_P_UART2_TX 113 #define SC_P_UART2_RX 114 /* mux values */ #define IMX8QXP_DMA_LPUART2_RX_UART2_RX 0 /* UART2_RX ---> DMA_LPUART2_RX */ #define IMX8QXP_DMA_LPUART2_TX_UART2_TX 0 /* DMA_LPUART2_TX ---> UART2_TX */ +#define IMX8QXP_ADMA_SAI1_TXFS_SAI1_RXFS 1 /* ADMA_SAI1_TXFS <---> SAI1_RXFS */ +#define IMX8QXP_ADMA_SAI1_RXD_SAI1_RXD 0 /* ADMA_SAI1_RXD <--- SAI1_RXD */ +#define IMX8QXP_ADMA_SAI1_TXC_SAI1_RXC 1 /* ADMA_SAI1_TXC <---> SAI1_RXC */ +#define IMX8QXP_ADMA_SAI1_TXD_SPI0_CS1 2 /* ADMA_SAI1_TXD ---> SPI0_CS1 */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_ */ From 01a6fd5f4a5120f6ed71102051832d48ab291515 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Fri, 29 Mar 2024 12:18:51 +0200 Subject: [PATCH 1714/2402] boards: nxp: imx8qm_mek: add pinctrl for SAI1 node Add pinctrl for SAI1 node. This means: 1) Adding definitions for the pads used by SAI1. 2) Creating a pin group and referencing it in the SAI1 node via the `pinctrl-0` property. Signed-off-by: Laurentiu Mihalcea --- .../imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi | 25 +++++++++++++++++++ .../imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts | 5 ++++ .../dt-bindings/pinctrl/imx8qm-pinctrl.h | 8 ++++++ 3 files changed, 38 insertions(+) diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi index a6291a5d4b8..d6dbcdcfa95 100644 --- a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi @@ -14,6 +14,22 @@ iomuxc_uart2_tx_uart0_cts_b: IOMUXC_UART2_TX_UART0_CTS_B { pinmux = ; }; + + iomuxc_aud_sai1_rxd_sai1_rxd: IOMUXC_AUD_SAI1_RXD_SAI1_RXD { + pinmux = ; + }; + + iomuxc_aud_sai1_txc_sai1_txc: IOMUXC_AUD_SAI1_TXC_SAI1_TXC { + pinmux = ; + }; + + iomuxc_aud_sai1_txd_sai1_txd: IOMUXC_AUD_SAI1_TXD_SAI1_TXD { + pinmux = ; + }; + + iomuxc_aud_sai1_txfs_sai1_txfs: IOMUXC_AUD_SAI1_TXFS_SAI1_TXFS { + pinmux = ; + }; }; &pinctrl { @@ -23,4 +39,13 @@ <&iomuxc_uart2_tx_uart0_cts_b>; }; }; + + sai1_default: sai1_default { + group0 { + pinmux = <&iomuxc_aud_sai1_rxd_sai1_rxd>, + <&iomuxc_aud_sai1_txc_sai1_txc>, + <&iomuxc_aud_sai1_txd_sai1_txd>, + <&iomuxc_aud_sai1_txfs_sai1_txfs>; + }; + }; }; diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts index 325e293851f..9eddb9385b0 100644 --- a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts @@ -26,3 +26,8 @@ pinctrl-0 = <&lpuart2_default>; pinctrl-names = "default"; }; + +&sai1 { + pinctrl-0 = <&sai1_default>; + pinctrl-names = "default"; +}; diff --git a/include/zephyr/dt-bindings/pinctrl/imx8qm-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/imx8qm-pinctrl.h index 9748a2ce4aa..46278d5c8e8 100644 --- a/include/zephyr/dt-bindings/pinctrl/imx8qm-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/imx8qm-pinctrl.h @@ -10,9 +10,17 @@ /* values for pad field */ #define SC_P_UART0_RTS_B 23 #define SC_P_UART0_CTS_B 24 +#define SC_P_SAI1_RXD 128 +#define SC_P_SAI1_TXC 130 +#define SC_P_SAI1_TXD 131 +#define SC_P_SAI1_TXFS 132 /* mux values */ #define IMX8QM_DMA_LPUART2_RX_UART0_RTS_B 2 /* UART0_RTS_B ---> DMA_LPUART2_RX */ #define IMX8QM_DMA_LPUART2_TX_UART0_CTS_B 2 /* DMA_LPUART2_TX ---> UART0_CTS_B */ +#define IMX8QM_AUD_SAI1_RXD_SAI1_RXD 0 /* AUD_SAI1_RXD <--- SAI1_RXD */ +#define IMX8QM_AUD_SAI1_TXC_SAI1_TXC 0 /* AUD_SAI1_TXC <---> SAI1_TXC */ +#define IMX8QM_AUD_SAI1_TXD_SAI1_TXD 0 /* AUD_SAI1_TXD ---> SAI1_TXD */ +#define IMX8QM_AUD_SAI1_TXFS_SAI1_TXFS 0 /* AUD_SAI1_TXFS <---> SAI1_TXFS */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_ */ From f65715cb63a78c7c3a5df9fb29e73deaefdf1524 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Fri, 29 Mar 2024 08:52:01 +0100 Subject: [PATCH 1715/2402] mgmt: mcumgr: Remove POSIX_API dependency for UDP transport Zephyr subsystems should use non-posix socket API. Signed-off-by: Pieter De Gendt --- subsys/mgmt/mcumgr/transport/Kconfig.udp | 1 - subsys/mgmt/mcumgr/transport/src/smp_udp.c | 24 ++++++++-------------- 2 files changed, 9 insertions(+), 16 deletions(-) diff --git a/subsys/mgmt/mcumgr/transport/Kconfig.udp b/subsys/mgmt/mcumgr/transport/Kconfig.udp index 5eb78e2288e..0560ddb6dc1 100644 --- a/subsys/mgmt/mcumgr/transport/Kconfig.udp +++ b/subsys/mgmt/mcumgr/transport/Kconfig.udp @@ -14,7 +14,6 @@ menuconfig MCUMGR_TRANSPORT_UDP depends on NET_UDP depends on NET_SOCKETS select NET_CONNECTION_MANAGER - select POSIX_API help Enables handling of SMP commands received over UDP. Will start a thread for listening on the configured UDP port. diff --git a/subsys/mgmt/mcumgr/transport/src/smp_udp.c b/subsys/mgmt/mcumgr/transport/src/smp_udp.c index 5975d9b6b40..7daedb861c3 100644 --- a/subsys/mgmt/mcumgr/transport/src/smp_udp.c +++ b/subsys/mgmt/mcumgr/transport/src/smp_udp.c @@ -13,12 +13,7 @@ #include #include #include -#if defined(CONFIG_POSIX_API) -#include -#include -#else #include -#endif #include #include #include @@ -108,7 +103,7 @@ static int smp_udp4_tx(struct net_buf *nb) int ret; struct sockaddr *addr = net_buf_user_data(nb); - ret = sendto(smp_udp_configs.ipv4.sock, nb->data, nb->len, 0, addr, sizeof(*addr)); + ret = zsock_sendto(smp_udp_configs.ipv4.sock, nb->data, nb->len, 0, addr, sizeof(*addr)); if (ret < 0) { if (errno == ENOMEM) { @@ -132,7 +127,7 @@ static int smp_udp6_tx(struct net_buf *nb) int ret; struct sockaddr *addr = net_buf_user_data(nb); - ret = sendto(smp_udp_configs.ipv6.sock, nb->data, nb->len, 0, addr, sizeof(*addr)); + ret = zsock_sendto(smp_udp_configs.ipv6.sock, nb->data, nb->len, 0, addr, sizeof(*addr)); if (ret < 0) { if (errno == ENOMEM) { @@ -201,7 +196,7 @@ static int create_socket(enum proto_type proto, int *sock) } #endif - tmp_sock = socket(addr->sa_family, SOCK_DGRAM, IPPROTO_UDP); + tmp_sock = zsock_socket(addr->sa_family, SOCK_DGRAM, IPPROTO_UDP); err = errno; if (tmp_sock < 0) { @@ -211,12 +206,12 @@ static int create_socket(enum proto_type proto, int *sock) return -err; } - if (bind(tmp_sock, addr, sizeof(*addr)) < 0) { + if (zsock_bind(tmp_sock, addr, sizeof(*addr)) < 0) { err = errno; LOG_ERR("Could not bind to receive socket (%s), err: %i", smp_udp_proto_to_name(proto), err); - close(tmp_sock); + zsock_close(tmp_sock); return -err; } @@ -247,9 +242,8 @@ static void smp_udp_receive_thread(void *p1, void *p2, void *p3) struct sockaddr addr; socklen_t addr_len = sizeof(addr); - int len = recvfrom(conf->sock, conf->recv_buffer, - CONFIG_MCUMGR_TRANSPORT_UDP_MTU, - 0, &addr, &addr_len); + int len = zsock_recvfrom(conf->sock, conf->recv_buffer, + CONFIG_MCUMGR_TRANSPORT_UDP_MTU, 0, &addr, &addr_len); if (len > 0) { struct sockaddr *ud; @@ -355,7 +349,7 @@ int smp_udp_close(void) k_thread_abort(&(smp_udp_configs.ipv4.thread)); if (smp_udp_configs.ipv4.sock >= 0) { - close(smp_udp_configs.ipv4.sock); + zsock_close(smp_udp_configs.ipv4.sock); smp_udp_configs.ipv4.sock = -1; } } else { @@ -368,7 +362,7 @@ int smp_udp_close(void) k_thread_abort(&(smp_udp_configs.ipv6.thread)); if (smp_udp_configs.ipv6.sock >= 0) { - close(smp_udp_configs.ipv6.sock); + zsock_close(smp_udp_configs.ipv6.sock); smp_udp_configs.ipv6.sock = -1; } } else { From a221b44d9c31c41af08507d6724baa3fd7a46dcd Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Fri, 29 Mar 2024 08:53:21 +0100 Subject: [PATCH 1716/2402] samples: subsys: mgmt: mcumgr: smp_svr: Remove POSIX_API config The POSIX_API config should not be required to build the UDP mcumgr transport. Signed-off-by: Pieter De Gendt --- samples/subsys/mgmt/mcumgr/smp_svr/overlay-udp.conf | 1 - 1 file changed, 1 deletion(-) diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/overlay-udp.conf b/samples/subsys/mgmt/mcumgr/smp_svr/overlay-udp.conf index 99f80bbe5cb..20ef2fedb58 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/overlay-udp.conf +++ b/samples/subsys/mgmt/mcumgr/smp_svr/overlay-udp.conf @@ -13,4 +13,3 @@ CONFIG_NET_CONNECTION_MANAGER=y CONFIG_NET_CONFIG_SETTINGS=y CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.168.1.1" CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8::1" -CONFIG_POSIX_API=y From 1029800a6476e0ee0723ca329e4f82b50ff32c83 Mon Sep 17 00:00:00 2001 From: Piotr Narajowski Date: Thu, 28 Mar 2024 16:19:42 +0100 Subject: [PATCH 1717/2402] bluetooth: tester: add missing config Set CONFIG_BT_MAX_PAIRED with same value as in host. This is needed for CSIP tests with three lower testers: CSIP/CL/SP/BV-07-C, CSIP/CL/SP/BV-03-C, CSIP/CL/SP/BV-04-C, CSIP/CL/SPE/BI-01-C Signed-off-by: Piotr Narajowski --- tests/bluetooth/tester/nrf5340_hci_ipc.conf | 1 + tests/bluetooth/tester/nrf5340_hci_ipc_cpunet.conf | 1 + 2 files changed, 2 insertions(+) diff --git a/tests/bluetooth/tester/nrf5340_hci_ipc.conf b/tests/bluetooth/tester/nrf5340_hci_ipc.conf index 0e8de753e78..2b46473ffe5 100644 --- a/tests/bluetooth/tester/nrf5340_hci_ipc.conf +++ b/tests/bluetooth/tester/nrf5340_hci_ipc.conf @@ -1,5 +1,6 @@ # Apply this overlay at tester build, not hci_ipc build CONFIG_BT_MAX_CONN=3 +CONFIG_BT_MAX_PAIRED=3 # Those have to be the same as in the controller (hci_ipc) CONFIG_BT_BUF_EVT_RX_COUNT=16 CONFIG_BT_BUF_EVT_RX_SIZE=255 diff --git a/tests/bluetooth/tester/nrf5340_hci_ipc_cpunet.conf b/tests/bluetooth/tester/nrf5340_hci_ipc_cpunet.conf index ccb06345d81..d0242ec36d5 100644 --- a/tests/bluetooth/tester/nrf5340_hci_ipc_cpunet.conf +++ b/tests/bluetooth/tester/nrf5340_hci_ipc_cpunet.conf @@ -5,3 +5,4 @@ CONFIG_BT_BUF_ACL_RX_SIZE=100 CONFIG_BT_CTLR_PERIPHERAL_ISO_EARLY_CIG_START=y CONFIG_BT_CTLR_ISOAL_PSN_IGNORE=y CONFIG_BT_MAX_CONN=3 +CONFIG_BT_MAX_PAIRED=3 From 190375688867a77f8fb76d633cc25cedb770ab46 Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Fri, 29 Mar 2024 11:11:08 +0100 Subject: [PATCH 1718/2402] tests/lib/cbprintf_fp: add hifive1.conf This commit sets `CONFIG_NEWLIB_LIBC_MIN_REQUIRED_HEAP_SIZE=2048` for the SiFive HiFive1 board. Otherwise, the test fails on the following assert from Newlib: memory space available for newlib heap is less than the minimum required size specified by CONFIG_NEWLIB_LIBC_MIN_REQUIRED_HEAP_SIZE Signed-off-by: Filip Kokosinski --- tests/lib/cbprintf_fp/boards/hifive1.conf | 1 + 1 file changed, 1 insertion(+) create mode 100644 tests/lib/cbprintf_fp/boards/hifive1.conf diff --git a/tests/lib/cbprintf_fp/boards/hifive1.conf b/tests/lib/cbprintf_fp/boards/hifive1.conf new file mode 100644 index 00000000000..5b4a7d3fc15 --- /dev/null +++ b/tests/lib/cbprintf_fp/boards/hifive1.conf @@ -0,0 +1 @@ +CONFIG_NEWLIB_LIBC_MIN_REQUIRED_HEAP_SIZE=2048 From 11a30924d2e7cb79834349e6362de3470e7431cc Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Fri, 29 Mar 2024 11:13:06 +0100 Subject: [PATCH 1719/2402] tests/posix/getopt: add hifive1.conf This commit sets `CONFIG_NEWLIB_LIBC_MIN_REQUIRED_HEAP_SIZE=2048` for the SiFive HiFive1 board. Otherwise, the test fails on the following assert from Newlib: memory space available for newlib heap is less than the minimum required size specified by CONFIG_NEWLIB_LIBC_MIN_REQUIRED_HEAP_SIZE Signed-off-by: Filip Kokosinski --- tests/posix/getopt/boards/hifive1.conf | 1 + 1 file changed, 1 insertion(+) create mode 100644 tests/posix/getopt/boards/hifive1.conf diff --git a/tests/posix/getopt/boards/hifive1.conf b/tests/posix/getopt/boards/hifive1.conf new file mode 100644 index 00000000000..5b4a7d3fc15 --- /dev/null +++ b/tests/posix/getopt/boards/hifive1.conf @@ -0,0 +1 @@ +CONFIG_NEWLIB_LIBC_MIN_REQUIRED_HEAP_SIZE=2048 From 643c033a7f8d05803174ac7ce8a1dd2b1e630447 Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Fri, 29 Mar 2024 11:14:03 +0100 Subject: [PATCH 1720/2402] boards/sifive/hifive1: enable PMP on the default revision This commit enables PMP on the default revision of the SiFive HiFive1 board. PMP was already enabled on the Rev B of this board. Signed-off-by: Filip Kokosinski --- boards/sifive/hifive1/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/sifive/hifive1/Kconfig b/boards/sifive/hifive1/Kconfig index 304048665a7..34402f96d73 100644 --- a/boards/sifive/hifive1/Kconfig +++ b/boards/sifive/hifive1/Kconfig @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_HIFIVE1 - select RISCV_CORE_E31 if "$(BOARD_REVISION)" = "B" + select RISCV_CORE_E31 From d5b1a7d929e62a69d0d79c8603fbf92c4928bbf6 Mon Sep 17 00:00:00 2001 From: Jason Yu Date: Mon, 11 Mar 2024 13:08:54 +0900 Subject: [PATCH 1721/2402] driver: input: gt911: Support case that no dedicated reset pin On some boards, there is not dedicated reset pin for GT911, it might be the same pin with display IC, or might be tighted to a high level voltage. This patch makes the rst_gpio can be empty. Signed-off-by: Jason Yu --- drivers/input/input_gt911.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/input/input_gt911.c b/drivers/input/input_gt911.c index 01699c06377..23950cc4c7d 100644 --- a/drivers/input/input_gt911.c +++ b/drivers/input/input_gt911.c @@ -225,15 +225,17 @@ static int gt911_init(const struct device *dev) return -ENODEV; } - if (!gpio_is_ready_dt(&config->rst_gpio)) { - LOG_ERR("Reset GPIO controller device not ready"); - return -ENODEV; - } + if (config->rst_gpio.port != NULL) { + if (!gpio_is_ready_dt(&config->rst_gpio)) { + LOG_ERR("Reset GPIO controller device not ready"); + return -ENODEV; + } - r = gpio_pin_configure_dt(&config->rst_gpio, GPIO_OUTPUT_ACTIVE); - if (r < 0) { - LOG_ERR("Could not configure reset GPIO pin"); - return r; + r = gpio_pin_configure_dt(&config->rst_gpio, GPIO_OUTPUT_ACTIVE); + if (r < 0) { + LOG_ERR("Could not configure reset GPIO pin"); + return r; + } } if (config->alt_addr == 0x0) { @@ -252,13 +254,15 @@ static int gt911_init(const struct device *dev) } /* Delay at least 10 ms after power on before we configure gt911 */ k_sleep(K_MSEC(20)); - /* reset the device and confgiure the addr mode0 */ - gpio_pin_set_dt(&config->rst_gpio, 1); - /* hold down at least 1us, 1ms here */ - k_sleep(K_MSEC(1)); - gpio_pin_set_dt(&config->rst_gpio, 0); - /* hold down at least 5ms. This is the point the INT pin must be low. */ - k_sleep(K_MSEC(5)); + if (config->rst_gpio.port != NULL) { + /* reset the device and confgiure the addr mode0 */ + gpio_pin_set_dt(&config->rst_gpio, 1); + /* hold down at least 1us, 1ms here */ + k_sleep(K_MSEC(1)); + gpio_pin_set_dt(&config->rst_gpio, 0); + /* hold down at least 5ms. This is the point the INT pin must be low. */ + k_sleep(K_MSEC(5)); + } /* hold down 50ms to make sure the address available */ k_sleep(K_MSEC(50)); @@ -359,7 +363,7 @@ static int gt911_init(const struct device *dev) #define GT911_INIT(index) \ static const struct gt911_config gt911_config_##index = { \ .bus = I2C_DT_SPEC_INST_GET(index), \ - .rst_gpio = GPIO_DT_SPEC_INST_GET(index, reset_gpios), \ + .rst_gpio = GPIO_DT_SPEC_INST_GET_OR(index, reset_gpios, {0}), \ .int_gpio = GPIO_DT_SPEC_INST_GET(index, irq_gpios), \ .alt_addr = DT_INST_PROP_OR(index, alt_addr, 0), \ }; \ From 8f9c28282b1998e9014ce6b13b9c0f7befdb88c8 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Tue, 2 Apr 2024 12:50:38 +0200 Subject: [PATCH 1722/2402] twister: pytest: escape expected command regex When sending commands containing something like "AT+CFUN" the expected regex was not escaped and as a result such regex never matched what has been echoed over serial. Escape all commands with re.escape() so that echoed shell commands are always matched, even when they contain special characters (like '+' in the example above). Signed-off-by: Marcin Niestroj --- .../pytest-twister-harness/src/twister_harness/helpers/shell.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/shell.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/shell.py index bf8b70cea91..7782617538c 100644 --- a/scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/shell.py +++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/shell.py @@ -58,7 +58,7 @@ def exec_command(self, command: str, timeout: float | None = None, print_output: timeout = timeout or self.base_timeout command_ext = f'{command}\n\n' regex_prompt = re.escape(self.prompt) - regex_command = f'.*{command}' + regex_command = f'.*{re.escape(command)}' self._device.clear_buffer() self._device.write(command_ext.encode()) lines: list[str] = [] From a9fea59281953bc5f9acc1c6ddefcb5af4909ef7 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Mon, 1 Apr 2024 10:09:30 -0500 Subject: [PATCH 1723/2402] soc: nxp: Select the MFD Kconfig when LPFlexcomm is enabled LPFlexcomm is a MFD device hence select this Kconfig whenever it is enabled. Remove the selection from the individual driver Kconfig files. Signed-off-by: Mahesh Mahadevan --- drivers/serial/Kconfig.mcux_lpuart | 1 - drivers/spi/Kconfig.mcux_lpspi | 1 - soc/nxp/mcx/Kconfig | 4 ++++ 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/serial/Kconfig.mcux_lpuart b/drivers/serial/Kconfig.mcux_lpuart index 71c0a41663b..5833c49268e 100644 --- a/drivers/serial/Kconfig.mcux_lpuart +++ b/drivers/serial/Kconfig.mcux_lpuart @@ -13,7 +13,6 @@ config UART_MCUX_LPUART select SERIAL_SUPPORT_ASYNC select DMA if UART_ASYNC_API select PINCTRL - select MFD if DT_HAS_NXP_LP_FLEXCOMM_ENABLED help Enable the MCUX LPUART driver. diff --git a/drivers/spi/Kconfig.mcux_lpspi b/drivers/spi/Kconfig.mcux_lpspi index 8f2e79d2807..bad4191fbdc 100644 --- a/drivers/spi/Kconfig.mcux_lpspi +++ b/drivers/spi/Kconfig.mcux_lpspi @@ -9,7 +9,6 @@ config SPI_MCUX_LPSPI depends on DT_HAS_NXP_IMX_LPSPI_ENABLED depends on CLOCK_CONTROL select PINCTRL - select MFD if DT_HAS_NXP_LP_FLEXCOMM_ENABLED help Enable support for mcux spi driver. diff --git a/soc/nxp/mcx/Kconfig b/soc/nxp/mcx/Kconfig index b2a5c5ab8e7..1f310d9fa56 100644 --- a/soc/nxp/mcx/Kconfig +++ b/soc/nxp/mcx/Kconfig @@ -35,4 +35,8 @@ config FLASH_MCUX_FLEXSPI_XIP_MEM endif # FLASH_MCUX_FLEXSPI_XIP +config MFD + default y + depends on DT_HAS_NXP_LP_FLEXCOMM_ENABLED + endif # SOC_FAMILY_NXP_MCX From 930ea28798ec8ffbfcb7491166141b384709293d Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 26 Mar 2024 14:15:24 -0500 Subject: [PATCH 1724/2402] gwest.yml: Get the NXP SDK I2C support on MCX947 Get the NXP SDK driver for I2C support on MCXN947 Signed-off-by: Mahesh Mahadevan --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 4c382cc4fbc..1e82f4512c0 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 9d32c7382b6383a30ae6095e02f17f9acfa63e7a + revision: 874ed3b297ba1f21bc6422aed85c3fdba3219de2 path: modules/hal/nxp groups: - hal From 6199bd9c6192e1da0f1b8473b8ce76f3602a5762 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Wed, 3 May 2023 16:32:24 -0500 Subject: [PATCH 1725/2402] drivers: i2c: MCUX SDK LPI2C driver sometimes uses instance number Update the driver to account for variations in the SDK driver when it uses the instance number instead of the base address. Signed-off-by: Mahesh Mahadevan --- drivers/i2c/i2c_mcux_lpi2c.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/i2c_mcux_lpi2c.c b/drivers/i2c/i2c_mcux_lpi2c.c index 16660359312..ae79f0c43b3 100644 --- a/drivers/i2c/i2c_mcux_lpi2c.c +++ b/drivers/i2c/i2c_mcux_lpi2c.c @@ -479,8 +479,11 @@ static void mcux_lpi2c_isr(const struct device *dev) mcux_lpi2c_slave_irq_handler(dev); } #endif /* CONFIG_I2C_TARGET */ - +#if CONFIG_HAS_MCUX_FLEXCOMM + LPI2C_MasterTransferHandleIRQ(LPI2C_GetInstance(base), &data->handle); +#else LPI2C_MasterTransferHandleIRQ(base, &data->handle); +#endif } static int mcux_lpi2c_init(const struct device *dev) From 678e65093b6bd53e956e89522e598a8fb5c2def8 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Thu, 27 Jul 2023 16:16:59 -0500 Subject: [PATCH 1726/2402] dts: nxp_lpi2c: Interrupts is no longer a required property Some NXP SoC's have a FlexComm interface that manages the interrupts. Signed-off-by: Mahesh Mahadevan --- drivers/i2c/i2c_mcux_lpi2c.c | 20 ++++++++++++++------ dts/bindings/i2c/nxp,imx-lpi2c.yaml | 3 --- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/i2c/i2c_mcux_lpi2c.c b/drivers/i2c/i2c_mcux_lpi2c.c index ae79f0c43b3..b87ee948239 100644 --- a/drivers/i2c/i2c_mcux_lpi2c.c +++ b/drivers/i2c/i2c_mcux_lpi2c.c @@ -556,6 +556,19 @@ static const struct i2c_driver_api mcux_lpi2c_driver_api = { #define I2C_MCUX_LPI2C_SDA_INIT(n) #endif /* CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY */ +#define I2C_MCUX_LPI2C_MODULE_IRQ_CONNECT(n) \ + do { \ + IRQ_CONNECT(DT_INST_IRQN(n), \ + DT_INST_IRQ(n, priority), \ + mcux_lpi2c_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + } while (false) + +#define I2C_MCUX_LPI2C_MODULE_IRQ(n) \ + IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \ + (I2C_MCUX_LPI2C_MODULE_IRQ_CONNECT(n))) + #define I2C_MCUX_LPI2C_INIT(n) \ PINCTRL_DT_INST_DEFINE(n); \ \ @@ -586,12 +599,7 @@ static const struct i2c_driver_api mcux_lpi2c_driver_api = { \ static void mcux_lpi2c_config_func_##n(const struct device *dev) \ { \ - IRQ_CONNECT(DT_INST_IRQN(n), \ - DT_INST_IRQ(n, priority), \ - mcux_lpi2c_isr, \ - DEVICE_DT_INST_GET(n), 0); \ - \ - irq_enable(DT_INST_IRQN(n)); \ + I2C_MCUX_LPI2C_MODULE_IRQ(n); \ } DT_INST_FOREACH_STATUS_OKAY(I2C_MCUX_LPI2C_INIT) diff --git a/dts/bindings/i2c/nxp,imx-lpi2c.yaml b/dts/bindings/i2c/nxp,imx-lpi2c.yaml index 50437430918..91d2f96aaf4 100644 --- a/dts/bindings/i2c/nxp,imx-lpi2c.yaml +++ b/dts/bindings/i2c/nxp,imx-lpi2c.yaml @@ -11,9 +11,6 @@ properties: reg: required: true - interrupts: - required: true - bus-idle-timeout: type: int description: Bus idle timeout in nanoseconds From cbbe33996e1f141401e417270b44e5752ac21b8c Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Mon, 25 Mar 2024 12:26:32 -0500 Subject: [PATCH 1727/2402] drivers: i2c: Use the NXP Flexcomm driver for interrupt handling The Low Power Flexcomm driver manages the interrupt handling and provides an API to register interrupt callbacks. Register the NXP LPI2C interrupt handler. Signed-off-by: Mahesh Mahadevan --- drivers/i2c/i2c_mcux_lpi2c.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/i2c_mcux_lpi2c.c b/drivers/i2c/i2c_mcux_lpi2c.c index b87ee948239..0bb7e2d402f 100644 --- a/drivers/i2c/i2c_mcux_lpi2c.c +++ b/drivers/i2c/i2c_mcux_lpi2c.c @@ -14,6 +14,9 @@ #include #include #include +#if CONFIG_NXP_LP_FLEXCOMM +#include +#endif #include @@ -39,6 +42,9 @@ LOG_MODULE_REGISTER(mcux_lpi2c); struct mcux_lpi2c_config { DEVICE_MMIO_NAMED_ROM(reg_base); +#ifdef CONFIG_NXP_LP_FLEXCOMM + const struct device *parent_dev; +#endif const struct device *clock_dev; clock_control_subsys_t clock_subsys; void (*irq_config_func)(const struct device *dev); @@ -530,8 +536,16 @@ static int mcux_lpi2c_init(const struct device *dev) if (error) { return error; } - +#if CONFIG_NXP_LP_FLEXCOMM + /* When using LP Flexcomm driver, register the interrupt handler + * so we receive notification from the LP Flexcomm interrupt handler. + */ + nxp_lp_flexcomm_setirqhandler(config->parent_dev, dev, + LP_FLEXCOMM_PERIPH_LPI2C, mcux_lpi2c_isr); +#else + /* Interrupt is managed by this driver */ config->irq_config_func(dev); +#endif return 0; } @@ -560,7 +574,7 @@ static const struct i2c_driver_api mcux_lpi2c_driver_api = { do { \ IRQ_CONNECT(DT_INST_IRQN(n), \ DT_INST_IRQ(n, priority), \ - mcux_lpi2c_isr, \ + mcux_lpi2c_isr, \ DEVICE_DT_INST_GET(n), 0); \ irq_enable(DT_INST_IRQN(n)); \ } while (false) @@ -569,13 +583,21 @@ static const struct i2c_driver_api mcux_lpi2c_driver_api = { IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \ (I2C_MCUX_LPI2C_MODULE_IRQ_CONNECT(n))) +#ifdef CONFIG_NXP_LP_FLEXCOMM +#define PARENT_DEV(n) \ + .parent_dev = DEVICE_DT_GET(DT_INST_PARENT(n)), +#else +#define PARENT_DEV(n) +#endif /* CONFIG_NXP_LP_FLEXCOMM */ + #define I2C_MCUX_LPI2C_INIT(n) \ PINCTRL_DT_INST_DEFINE(n); \ \ static void mcux_lpi2c_config_func_##n(const struct device *dev); \ \ static const struct mcux_lpi2c_config mcux_lpi2c_config_##n = { \ - DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \ + DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \ + PARENT_DEV(n) \ .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ .clock_subsys = \ (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\ From 0a0b902b71279e9eded3ca81c04cce162bda6d7b Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 26 Mar 2024 11:39:59 -0500 Subject: [PATCH 1728/2402] boards: frdm_mcxn947: Add support for I2C Add support for I2C Signed-off-by: Mahesh Mahadevan --- boards/nxp/frdm_mcxn947/board.c | 5 +++++ boards/nxp/frdm_mcxn947/doc/index.rst | 2 ++ boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi | 12 ++++++++++++ boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 7 +++++++ .../nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts | 8 ++++++++ .../nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml | 1 + 6 files changed, 35 insertions(+) diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index 6f55c216d85..8016c4bc13a 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -99,6 +99,11 @@ static int frdm_mcxn947_init(void) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay) + CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 1u); + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2); +#endif + #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay) CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u); CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index 58903baccb7..04acb21ec3a 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -64,6 +64,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | DMA | on-chip | dma | +-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ | CLOCK | on-chip | clock_control | +-----------+------------+-------------------------------------+ | FLASH | on-chip | soc flash | diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi index 4caf1845392..c827d12a8ae 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi @@ -19,6 +19,18 @@ }; }; + pinmux_flexcomm2_lpi2c: pinmux_flexcomm2_lpi2c { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart { group0 { pinmux = , diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 16dcd41276d..f14bd8bdb24 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -5,6 +5,7 @@ */ #include "frdm_mcxn947-pinctrl.dtsi" +#include / { aliases{ @@ -54,6 +55,12 @@ pinctrl-names = "default"; }; +&flexcomm2_lpi2c2 { + pinctrl-0 = <&pinmux_flexcomm2_lpi2c>; + pinctrl-names = "default"; + clock-frequency = ; +}; + &flexcomm4_lpuart4 { current-speed = <115200>; pinctrl-0 = <&pinmux_flexcomm4_lpuart>; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts index cdb52c62f5c..ff31063f694 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts @@ -77,6 +77,14 @@ status = "okay"; }; +&flexcomm2 { + status = "okay"; +}; + +&flexcomm2_lpi2c2 { + status = "okay"; +}; + &flexcomm4 { status = "okay"; }; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml index 2222a8c275b..156451f0a10 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -19,4 +19,5 @@ supported: - gpio - spi - dac + - i2c vendor: nxp From 8ea68cc0b43aa078e14f466347f82b77491301a1 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 26 Mar 2024 11:40:52 -0500 Subject: [PATCH 1729/2402] tests: i2c: Add support for NXP MCXN947 Add support for NXP MCXN947 Signed-off-by: Mahesh Mahadevan --- .../boards/frdm_mcxn947_mcxn947_cpu0.conf | 1 + .../boards/frdm_mcxn947_mcxn947_cpu0.overlay | 51 +++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.conf create mode 100644 tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.conf b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.conf new file mode 100644 index 00000000000..70e009fae68 --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.conf @@ -0,0 +1 @@ +CONFIG_I2C_VIRTUAL=n diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay new file mode 100644 index 00000000000..d0dc5661db8 --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay @@ -0,0 +1,51 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ +&pinctrl { + pinmux_flexcomm1_lpi2c: pinmux_flexcomm1_lpi2c { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; +}; + +&flexcomm1 { + status = "okay"; +}; + +/* We cannot enable SPI and I2C on the same flexcomm */ +&flexcomm1_lpspi1 { + status = "disabled"; +}; + +/* To test this sample, connect + * LPI2C1 SCL(J2-12, P1_25/FC1_P1) --> LPI2C2 SCL(J2-20, P4_1/FC2_P1) + * LPI2C1 SDA(J2-8, P1_24/FC1_P0) --> LPI2C2 SDA(J2-18, P4_0/FC2_P0) + */ +&flexcomm1_lpi2c1 { + pinctrl-0 = <&pinmux_flexcomm1_lpi2c>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; + eeprom0: eeprom@54 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x54>; + size = <1024>; + }; +}; + +&flexcomm2_lpi2c2 { + eeprom1: eeprom@56 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x56>; + size = <1024>; + }; +}; From 5591d2305e892dfdc0f14b18cf87acb275180344 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Sat, 30 Mar 2024 19:20:52 +0000 Subject: [PATCH 1730/2402] Bluetooth: host: tweak up the bluetooth thread names Change the receive workque name to "BT RX WQ" to distinguish it from the receive thread, and the long workque one to "BT LW WQ" to make the format consistent with the other Bluetooth threads. On an nRF52 now "kernel stacks" looks like: 0x200016c8 BT RX (real size 448): unused 280 ) 0x20001780 BT RX pri (real size 448): unused 224 ) 0x200012c0 BT RX WQ (real size 2240): unused 1360 ) 0x20001208 BT TX (real size 768): unused 408 ) 0x20001130 BT LW WQ (real size 1344): unused 408 ) Signed-off-by: Fabio Baltieri --- subsys/bluetooth/host/hci_core.c | 2 +- subsys/bluetooth/host/long_wq.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c index 0118b5efdaa..35ba75701b4 100644 --- a/subsys/bluetooth/host/hci_core.c +++ b/subsys/bluetooth/host/hci_core.c @@ -4128,7 +4128,7 @@ int bt_enable(bt_ready_cb_t cb) k_work_queue_start(&bt_workq, rx_thread_stack, CONFIG_BT_RX_STACK_SIZE, K_PRIO_COOP(CONFIG_BT_RX_PRIO), NULL); - k_thread_name_set(&bt_workq.thread, "BT RX"); + k_thread_name_set(&bt_workq.thread, "BT RX WQ"); #endif err = bt_dev.drv->open(); diff --git a/subsys/bluetooth/host/long_wq.c b/subsys/bluetooth/host/long_wq.c index 2136739c243..b7b6e3dc03b 100644 --- a/subsys/bluetooth/host/long_wq.c +++ b/subsys/bluetooth/host/long_wq.c @@ -29,7 +29,7 @@ int bt_long_wq_submit(struct k_work *work) static int long_wq_init(void) { - const struct k_work_queue_config cfg = {.name = "BT_LW_WQ"}; + const struct k_work_queue_config cfg = {.name = "BT LW WQ"}; k_work_queue_init(&bt_long_wq); From f010f40c8cc7cc407590d831334eae0fdb917e40 Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Sat, 30 Mar 2024 10:18:09 -0400 Subject: [PATCH 1731/2402] posix: sys: socket: move defines outside of extern C preprocessor symbols do not need to be externed. Signed-off-by: Chris Friedt --- include/zephyr/posix/sys/socket.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/include/zephyr/posix/sys/socket.h b/include/zephyr/posix/sys/socket.h index ea3a177d88a..9ce76006f09 100644 --- a/include/zephyr/posix/sys/socket.h +++ b/include/zephyr/posix/sys/socket.h @@ -9,6 +9,17 @@ #include #include +#ifndef CONFIG_NET_SOCKETS_POSIX_NAMES + +#define SHUT_RD ZSOCK_SHUT_RD +#define SHUT_WR ZSOCK_SHUT_WR +#define SHUT_RDWR ZSOCK_SHUT_RDWR + +#define MSG_PEEK ZSOCK_MSG_PEEK +#define MSG_TRUNC ZSOCK_MSG_TRUNC +#define MSG_DONTWAIT ZSOCK_MSG_DONTWAIT +#define MSG_WAITALL ZSOCK_MSG_WAITALL + #ifdef __cplusplus extern "C" { #endif @@ -18,8 +29,6 @@ struct linger { int l_linger; }; -#ifndef CONFIG_NET_SOCKETS_POSIX_NAMES - static inline int socket(int family, int type, int proto) { return zsock_socket(family, type, proto); @@ -30,15 +39,6 @@ static inline int socketpair(int family, int type, int proto, int sv[2]) return zsock_socketpair(family, type, proto, sv); } -#define SHUT_RD ZSOCK_SHUT_RD -#define SHUT_WR ZSOCK_SHUT_WR -#define SHUT_RDWR ZSOCK_SHUT_RDWR - -#define MSG_PEEK ZSOCK_MSG_PEEK -#define MSG_TRUNC ZSOCK_MSG_TRUNC -#define MSG_DONTWAIT ZSOCK_MSG_DONTWAIT -#define MSG_WAITALL ZSOCK_MSG_WAITALL - static inline int shutdown(int sock, int how) { return zsock_shutdown(sock, how); From 5ab984a834a923094c6830a77e74c1832abfcb6e Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Sat, 30 Mar 2024 10:58:26 -0400 Subject: [PATCH 1732/2402] posix: convert static inline functions to library functions With CONFIG_NET_POSIX_NAMES being deprecated, convert static inlines in headers to prototypes, and move implementations to lib/posix/options/net.c . Since select and poll should technically also operate on non-socket file descriptors, these may be relocated in the future. Below are some reasons for this change. 1. So posix calls are regular symbols and not directly inlined as syscalls. This is also the most portable linkage type. 2. Many posix calls are cancellation points and additional checks are necessary within the implementation. 3. The more we add to an inline call, the less sense it makes for that call to be inline. 4. When the implementation of a posix function changes, the interface for it should still remain consistent. Note: the same principles have been applied in Zephyr's posix implementation already, e.g. clock_gettime(), so this is nothing new. Signed-off-by: Chris Friedt --- include/zephyr/posix/arpa/inet.h | 17 +--- include/zephyr/posix/netdb.h | 35 ++------ include/zephyr/posix/poll.h | 9 +- include/zephyr/posix/sys/select.h | 12 +-- include/zephyr/posix/sys/socket.h | 117 ++++--------------------- lib/posix/options/net.c | 141 ++++++++++++++++++++++++++++++ 6 files changed, 170 insertions(+), 161 deletions(-) diff --git a/include/zephyr/posix/arpa/inet.h b/include/zephyr/posix/arpa/inet.h index 4e651d0a79f..39b6cf6232e 100644 --- a/include/zephyr/posix/arpa/inet.h +++ b/include/zephyr/posix/arpa/inet.h @@ -17,25 +17,12 @@ extern "C" { #endif -#ifndef CONFIG_NET_SOCKETS_POSIX_NAMES - -static inline char *inet_ntop(sa_family_t family, const void *src, char *dst, - size_t size) -{ - return zsock_inet_ntop(family, src, dst, size); -} - -static inline int inet_pton(sa_family_t family, const char *src, void *dst) -{ - return zsock_inet_pton(family, src, dst); -} - -#endif /* CONFIG_NET_SOCKETS_POSIX_NAMES */ - typedef uint32_t in_addr_t; in_addr_t inet_addr(const char *cp); char *inet_ntoa(struct in_addr in); +char *inet_ntop(sa_family_t family, const void *src, char *dst, size_t size); +int inet_pton(sa_family_t family, const char *src, void *dst); #ifdef __cplusplus } diff --git a/include/zephyr/posix/netdb.h b/include/zephyr/posix/netdb.h index 0e1b71cc243..5a094428e22 100644 --- a/include/zephyr/posix/netdb.h +++ b/include/zephyr/posix/netdb.h @@ -57,42 +57,19 @@ struct servent { char *s_proto; }; -#ifndef CONFIG_NET_SOCKETS_POSIX_NAMES - #define addrinfo zsock_addrinfo -static inline int getaddrinfo(const char *host, const char *service, - const struct zsock_addrinfo *hints, - struct zsock_addrinfo **res) -{ - return zsock_getaddrinfo(host, service, hints, res); -} - -static inline void freeaddrinfo(struct zsock_addrinfo *ai) -{ - zsock_freeaddrinfo(ai); -} - -static inline const char *gai_strerror(int errcode) -{ - return zsock_gai_strerror(errcode); -} - -static inline int getnameinfo(const struct sockaddr *addr, socklen_t addrlen, - char *host, socklen_t hostlen, - char *serv, socklen_t servlen, int flags) -{ - return zsock_getnameinfo(addr, addrlen, host, hostlen, - serv, servlen, flags); -} - -#endif /* CONFIG_NET_SOCKETS_POSIX_NAMES */ - void endhostent(void); void endnetent(void); void endprotoent(void); void endservent(void); +void freeaddrinfo(struct zsock_addrinfo *ai); +const char *gai_strerror(int errcode); +int getaddrinfo(const char *host, const char *service, const struct zsock_addrinfo *hints, + struct zsock_addrinfo **res); struct hostent *gethostent(void); +int getnameinfo(const struct sockaddr *addr, socklen_t addrlen, char *host, socklen_t hostlen, + char *serv, socklen_t servlen, int flags); struct netent *getnetbyaddr(uint32_t net, int type); struct netent *getnetbyname(const char *name); struct netent *getnetent(void); diff --git a/include/zephyr/posix/poll.h b/include/zephyr/posix/poll.h index a1f90333c42..4aeebeed176 100644 --- a/include/zephyr/posix/poll.h +++ b/include/zephyr/posix/poll.h @@ -12,8 +12,6 @@ extern "C" { #endif -#ifndef CONFIG_NET_SOCKETS_POSIX_NAMES - #define pollfd zsock_pollfd #define POLLIN ZSOCK_POLLIN @@ -22,12 +20,7 @@ extern "C" { #define POLLHUP ZSOCK_POLLHUP #define POLLNVAL ZSOCK_POLLNVAL -static inline int poll(struct pollfd *fds, int nfds, int timeout) -{ - return zsock_poll(fds, nfds, timeout); -} - -#endif /* CONFIG_NET_SOCKETS_POSIX_NAMES */ +int poll(struct pollfd *fds, int nfds, int timeout); #ifdef __cplusplus } diff --git a/include/zephyr/posix/sys/select.h b/include/zephyr/posix/sys/select.h index 4420b69eaba..fc61c018e24 100644 --- a/include/zephyr/posix/sys/select.h +++ b/include/zephyr/posix/sys/select.h @@ -13,8 +13,6 @@ extern "C" { #endif -#ifndef CONFIG_NET_SOCKETS_POSIX_NAMES - #define fd_set zsock_fd_set #define FD_SETSIZE ZSOCK_FD_SETSIZE #define FD_ZERO ZSOCK_FD_ZERO @@ -24,15 +22,7 @@ extern "C" { struct timeval; -static inline int select(int nfds, fd_set *readfds, - fd_set *writefds, fd_set *exceptfds, - struct timeval *timeout) -{ - return zsock_select(nfds, readfds, writefds, exceptfds, - (struct zsock_timeval *)timeout); -} - -#endif /* CONFIG_NET_SOCKETS_POSIX_NAMES */ +int select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, struct timeval *timeout); #ifdef __cplusplus } diff --git a/include/zephyr/posix/sys/socket.h b/include/zephyr/posix/sys/socket.h index 9ce76006f09..669434f8fd0 100644 --- a/include/zephyr/posix/sys/socket.h +++ b/include/zephyr/posix/sys/socket.h @@ -9,8 +9,6 @@ #include #include -#ifndef CONFIG_NET_SOCKETS_POSIX_NAMES - #define SHUT_RD ZSOCK_SHUT_RD #define SHUT_WR ZSOCK_SHUT_WR #define SHUT_RDWR ZSOCK_SHUT_RDWR @@ -29,103 +27,26 @@ struct linger { int l_linger; }; -static inline int socket(int family, int type, int proto) -{ - return zsock_socket(family, type, proto); -} - -static inline int socketpair(int family, int type, int proto, int sv[2]) -{ - return zsock_socketpair(family, type, proto, sv); -} - -static inline int shutdown(int sock, int how) -{ - return zsock_shutdown(sock, how); -} - -static inline int bind(int sock, const struct sockaddr *addr, socklen_t addrlen) -{ - return zsock_bind(sock, addr, addrlen); -} - -static inline int connect(int sock, const struct sockaddr *addr, - socklen_t addrlen) -{ - return zsock_connect(sock, addr, addrlen); -} - -static inline int listen(int sock, int backlog) -{ - return zsock_listen(sock, backlog); -} - -static inline int accept(int sock, struct sockaddr *addr, socklen_t *addrlen) -{ - return zsock_accept(sock, addr, addrlen); -} - -static inline ssize_t send(int sock, const void *buf, size_t len, int flags) -{ - return zsock_send(sock, buf, len, flags); -} - -static inline ssize_t recv(int sock, void *buf, size_t max_len, int flags) -{ - return zsock_recv(sock, buf, max_len, flags); -} - -static inline ssize_t sendto(int sock, const void *buf, size_t len, int flags, - const struct sockaddr *dest_addr, - socklen_t addrlen) -{ - return zsock_sendto(sock, buf, len, flags, dest_addr, addrlen); -} - -static inline ssize_t sendmsg(int sock, const struct msghdr *message, - int flags) -{ - return zsock_sendmsg(sock, message, flags); -} - -static inline ssize_t recvmsg(int sock, struct msghdr *msg, int flags) -{ - return zsock_recvmsg(sock, msg, flags); -} - -static inline ssize_t recvfrom(int sock, void *buf, size_t max_len, int flags, - struct sockaddr *src_addr, socklen_t *addrlen) -{ - return zsock_recvfrom(sock, buf, max_len, flags, src_addr, addrlen); -} - -static inline int getsockopt(int sock, int level, int optname, - void *optval, socklen_t *optlen) -{ - return zsock_getsockopt(sock, level, optname, optval, optlen); -} - -static inline int setsockopt(int sock, int level, int optname, - const void *optval, socklen_t optlen) -{ - return zsock_setsockopt(sock, level, optname, optval, optlen); -} - -static inline int getpeername(int sock, struct sockaddr *addr, - socklen_t *addrlen) -{ - return zsock_getpeername(sock, addr, addrlen); -} - -static inline int getsockname(int sock, struct sockaddr *addr, - socklen_t *addrlen) -{ - return zsock_getsockname(sock, addr, addrlen); -} - -#endif /* CONFIG_NET_SOCKETS_POSIX_NAMES */ - +int accept(int sock, struct sockaddr *addr, socklen_t *addrlen); +int bind(int sock, const struct sockaddr *addr, socklen_t addrlen); +int connect(int sock, const struct sockaddr *addr, socklen_t addrlen); +int getpeername(int sock, struct sockaddr *addr, socklen_t *addrlen); +int getsockname(int sock, struct sockaddr *addr, socklen_t *addrlen); +int getsockopt(int sock, int level, int optname, void *optval, socklen_t *optlen); +int listen(int sock, int backlog); +ssize_t recv(int sock, void *buf, size_t max_len, int flags); +ssize_t recvfrom(int sock, void *buf, size_t max_len, int flags, struct sockaddr *src_addr, + socklen_t *addrlen); +ssize_t recvmsg(int sock, struct msghdr *msg, int flags); +ssize_t send(int sock, const void *buf, size_t len, int flags); +ssize_t sendmsg(int sock, const struct msghdr *message, int flags); +ssize_t sendto(int sock, const void *buf, size_t len, int flags, const struct sockaddr *dest_addr, + socklen_t addrlen); +int setsockopt(int sock, int level, int optname, const void *optval, socklen_t optlen); +int shutdown(int sock, int how); int sockatmark(int s); +int socket(int family, int type, int proto); +int socketpair(int family, int type, int proto, int sv[2]); #ifdef __cplusplus } diff --git a/lib/posix/options/net.c b/lib/posix/options/net.c index 695eff784e0..5fcfdca464c 100644 --- a/lib/posix/options/net.c +++ b/lib/posix/options/net.c @@ -1,4 +1,5 @@ /* + * Copyright (c) 2019 Linaro Limited * Copyright (c) 2024, Friedt Professional Engineering Services, Inc * * SPDX-License-Identifier: Apache-2.0 @@ -12,6 +13,11 @@ #include #include #include +#include +#include +#include + +/* From arpa/inet.h */ in_addr_t inet_addr(const char *cp) { @@ -80,6 +86,18 @@ char *inet_ntoa(struct in_addr in) return buf; } +char *inet_ntop(sa_family_t family, const void *src, char *dst, size_t size) +{ + return zsock_inet_ntop(family, src, dst, size); +} + +int inet_pton(sa_family_t family, const char *src, void *dst) +{ + return zsock_inet_pton(family, src, dst); +} + +/* From net/if.h */ + char *if_indextoname(unsigned int ifindex, char *ifname) { int ret; @@ -175,6 +193,8 @@ unsigned int if_nametoindex(const char *ifname) return ret; } +/* From netdb.h */ + void endhostent(void) { } @@ -191,11 +211,33 @@ void endservent(void) { } +void freeaddrinfo(struct zsock_addrinfo *ai) +{ + zsock_freeaddrinfo(ai); +} + +const char *gai_strerror(int errcode) +{ + return zsock_gai_strerror(errcode); +} + +int getaddrinfo(const char *host, const char *service, const struct zsock_addrinfo *hints, + struct zsock_addrinfo **res) +{ + return zsock_getaddrinfo(host, service, hints, res); +} + struct hostent *gethostent(void) { return NULL; } +int getnameinfo(const struct sockaddr *addr, socklen_t addrlen, char *host, socklen_t hostlen, + char *serv, socklen_t servlen, int flags) +{ + return zsock_getnameinfo(addr, addrlen, host, hostlen, serv, servlen, flags); +} + struct netent *getnetbyaddr(uint32_t net, int type) { ARG_UNUSED(net); @@ -216,6 +258,11 @@ struct netent *getnetent(void) return NULL; } +int getpeername(int sock, struct sockaddr *addr, socklen_t *addrlen) +{ + return zsock_getpeername(sock, addr, addrlen); +} + struct protoent *getprotobyname(const char *name) { ARG_UNUSED(name); @@ -276,6 +323,90 @@ void setservent(int stayopen) ARG_UNUSED(stayopen); } +/* From sys/socket.h */ + +int accept(int sock, struct sockaddr *addr, socklen_t *addrlen) +{ + return zsock_accept(sock, addr, addrlen); +} + +int bind(int sock, const struct sockaddr *addr, socklen_t addrlen) +{ + return zsock_bind(sock, addr, addrlen); +} + +int connect(int sock, const struct sockaddr *addr, socklen_t addrlen) +{ + return zsock_connect(sock, addr, addrlen); +} + +int getsockname(int sock, struct sockaddr *addr, socklen_t *addrlen) +{ + return zsock_getsockname(sock, addr, addrlen); +} + +int getsockopt(int sock, int level, int optname, void *optval, socklen_t *optlen) +{ + return zsock_getsockopt(sock, level, optname, optval, optlen); +} + +int listen(int sock, int backlog) +{ + return zsock_listen(sock, backlog); +} + +int poll(struct pollfd *fds, int nfds, int timeout) +{ + return zsock_poll(fds, nfds, timeout); +} + +ssize_t recv(int sock, void *buf, size_t max_len, int flags) +{ + return zsock_recv(sock, buf, max_len, flags); +} + +ssize_t recvfrom(int sock, void *buf, size_t max_len, int flags, struct sockaddr *src_addr, + socklen_t *addrlen) +{ + return zsock_recvfrom(sock, buf, max_len, flags, src_addr, addrlen); +} + +ssize_t recvmsg(int sock, struct msghdr *msg, int flags) +{ + return zsock_recvmsg(sock, msg, flags); +} + +int select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, struct timeval *timeout) +{ + return zsock_select(nfds, readfds, writefds, exceptfds, (struct zsock_timeval *)timeout); +} + +ssize_t send(int sock, const void *buf, size_t len, int flags) +{ + return zsock_send(sock, buf, len, flags); +} + +ssize_t sendmsg(int sock, const struct msghdr *message, int flags) +{ + return zsock_sendmsg(sock, message, flags); +} + +ssize_t sendto(int sock, const void *buf, size_t len, int flags, const struct sockaddr *dest_addr, + socklen_t addrlen) +{ + return zsock_sendto(sock, buf, len, flags, dest_addr, addrlen); +} + +int setsockopt(int sock, int level, int optname, const void *optval, socklen_t optlen) +{ + return zsock_setsockopt(sock, level, optname, optval, optlen); +} + +int shutdown(int sock, int how) +{ + return zsock_shutdown(sock, how); +} + int sockatmark(int s) { ARG_UNUSED(s); @@ -283,3 +414,13 @@ int sockatmark(int s) errno = ENOSYS; return -1; } + +int socket(int family, int type, int proto) +{ + return zsock_socket(family, type, proto); +} + +int socketpair(int family, int type, int proto, int sv[2]) +{ + return zsock_socketpair(family, type, proto, sv); +} From 1254092831affebd5f197906cdab5b2d4234464e Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Thu, 28 Mar 2024 10:48:04 -0500 Subject: [PATCH 1733/2402] scripts: west_commands: linkserver: fix probe serial number support With commit f419ea79909 (runner: linkerserver : remove the probe ID hardcode), support was added to use serial numbers with the linkserver --probe argument. However, one invocation of the argument was missed, and still used the "probe index" syntax. Resolve this issue. Signed-off-by: Daniel DeGrasse --- scripts/west_commands/runners/linkserver.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/west_commands/runners/linkserver.py b/scripts/west_commands/runners/linkserver.py index c1631d391af..b87c594c4ae 100644 --- a/scripts/west_commands/runners/linkserver.py +++ b/scripts/west_commands/runners/linkserver.py @@ -130,7 +130,7 @@ def do_run(self, command, **kwargs): linkserver_cmd = ([self.linkserver] + ["gdbserver"] + - ["--probe", "#"+str(self.probe) ] + + ["--probe", str(self.probe) ] + ["--gdb-port", str(self.gdb_port )] + ["--semihost-port", str(self.semihost_port) ] + _cmd_core + From db8a0b4b0c2408c1f949a0a690e75f83bd864970 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Sat, 23 Mar 2024 00:11:57 -0500 Subject: [PATCH 1734/2402] net: ethernet: Include ethernet API in eth_stats.h eth_stats.h is using ethernet api but not including the header, it must be working by luck in files that include it after something else that includes ethernet.h, fix by just including it. Signed-off-by: Declan Snyder --- subsys/net/l2/ethernet/eth_stats.h | 1 + 1 file changed, 1 insertion(+) diff --git a/subsys/net/l2/ethernet/eth_stats.h b/subsys/net/l2/ethernet/eth_stats.h index 05962e44701..b9860938f57 100644 --- a/subsys/net/l2/ethernet/eth_stats.h +++ b/subsys/net/l2/ethernet/eth_stats.h @@ -12,6 +12,7 @@ #include #include #include +#include static inline void eth_stats_update_bytes_rx(struct net_if *iface, uint32_t bytes) From a7c39a2cc2712c680b1e6730f59c859089057ba7 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Fri, 1 Mar 2024 14:30:19 -0600 Subject: [PATCH 1735/2402] dts: bindings: Add NXP ENET QOS Bindings Add compatibles for NXP ENET QOS drivers Signed-off-by: Declan Snyder --- dts/bindings/ethernet/nxp,enet-qos-mac.yaml | 15 +++++++++++++++ dts/bindings/ethernet/nxp,enet-qos.yaml | 18 ++++++++++++++++++ dts/bindings/mdio/nxp,enet-qos-mdio.yaml | 8 ++++++++ 3 files changed, 41 insertions(+) create mode 100644 dts/bindings/ethernet/nxp,enet-qos-mac.yaml create mode 100644 dts/bindings/ethernet/nxp,enet-qos.yaml create mode 100644 dts/bindings/mdio/nxp,enet-qos-mdio.yaml diff --git a/dts/bindings/ethernet/nxp,enet-qos-mac.yaml b/dts/bindings/ethernet/nxp,enet-qos-mac.yaml new file mode 100644 index 00000000000..5e43070fa5f --- /dev/null +++ b/dts/bindings/ethernet/nxp,enet-qos-mac.yaml @@ -0,0 +1,15 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP ENET QOS MAC + +compatible: "nxp,enet-qos-mac" + +include: ethernet-controller.yaml + +properties: + interrupts: + required: true + + interrupt-names: + required: true diff --git a/dts/bindings/ethernet/nxp,enet-qos.yaml b/dts/bindings/ethernet/nxp,enet-qos.yaml new file mode 100644 index 00000000000..2004c62c881 --- /dev/null +++ b/dts/bindings/ethernet/nxp,enet-qos.yaml @@ -0,0 +1,18 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP ENET QOS IP Module + +compatible: "nxp,enet-qos" + +include: [base.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + clocks: + required: true + pinctrl-0: + required: true + pinctrl-names: + required: true diff --git a/dts/bindings/mdio/nxp,enet-qos-mdio.yaml b/dts/bindings/mdio/nxp,enet-qos-mdio.yaml new file mode 100644 index 00000000000..8271c7760c2 --- /dev/null +++ b/dts/bindings/mdio/nxp,enet-qos-mdio.yaml @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP ENET QOS MDIO Controller + +compatible: "nxp,enet-qos-mdio" + +include: [mdio-controller.yaml] From 8fdacb5e454556e67cd8577c346c55e5e04fa71f Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Fri, 1 Mar 2024 14:31:40 -0600 Subject: [PATCH 1736/2402] drivers: clock_control_mcux_syscon: Add ENET QOS Add code for ENET QOS clocking in clock control driver Signed-off-by: Declan Snyder --- drivers/clock_control/clock_control_mcux_syscon.c | 13 +++++++++++++ .../dt-bindings/clock/mcux_lpc_syscon_clock.h | 2 ++ 2 files changed, 15 insertions(+) diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index 26917f98624..2570600c204 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -60,6 +60,12 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev, } #endif /* defined(CONFIG_PINCTRL_NXP_KINETIS) */ +#ifdef CONFIG_ETH_NXP_ENET_QOS + if ((uint32_t)sub_system == MCUX_ENET_QOS_CLK) { + CLOCK_EnableClock(kCLOCK_Enet); + } +#endif + return 0; } @@ -274,6 +280,13 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( break; #endif #endif /* CONFIG_MEMC_MCUX_FLEXSPI */ + +#ifdef CONFIG_ETH_NXP_ENET_QOS + case MCUX_ENET_QOS_CLK: + *rate = CLOCK_GetFreq(kCLOCK_BusClk); + break; +#endif + } return 0; diff --git a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h index 99c99431f13..5416564ed1d 100644 --- a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -74,4 +74,6 @@ #define MCUX_PORT4_CLK MCUX_LPC_CLK_ID(0x0C, 0x04) #define MCUX_PORT5_CLK MCUX_LPC_CLK_ID(0x0C, 0x05) +#define MCUX_ENET_QOS_CLK MCUX_LPC_CLK_ID(0x0D, 0x00) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */ From ecfc38ff6fe71ab621abd93bd54ff37f4a057b28 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Fri, 1 Mar 2024 14:32:46 -0600 Subject: [PATCH 1737/2402] include: Add NXP ENET QOS header Add header for NXP ENET QOS drivers Signed-off-by: Declan Snyder --- .../drivers/ethernet/eth_nxp_enet_qos.h | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h diff --git a/include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h b/include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h new file mode 100644 index 00000000000..1ec5adaf887 --- /dev/null +++ b/include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h @@ -0,0 +1,54 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_ETH_NXP_ENET_QOS_H__ +#define ZEPHYR_INCLUDE_DRIVERS_ETH_NXP_ENET_QOS_H__ + +#include +#include + +/* Different platforms named the peripheral different in the register definitions */ +#ifdef CONFIG_SOC_FAMILY_NXP_MCX +#undef ENET +#define ENET_QOS_NAME ENET +#define ENET_QOS_ALIGNMENT 4 +typedef ENET_Type enet_qos_t; +#else +#error "ENET_QOS not enabled on this SOC series" +#endif + +#define _PREFIX_UNDERLINE(x) _##x +#define _ENET_QOS_REG_FIELD(reg, field) MACRO_MAP_CAT(_PREFIX_UNDERLINE, reg, field, MASK) +#define _ENET_QOS_REG_MASK(reg, field) CONCAT(ENET_QOS_NAME, _ENET_QOS_REG_FIELD(reg, field)) + +/* Deciphers value of a field from a read value of an enet qos register + * + * reg: name of the register + * field: name of the bit field within the register + * val: value that had been read from the register + */ +#define ENET_QOS_REG_GET(reg, field, val) FIELD_GET(_ENET_QOS_REG_MASK(reg, field), val) + +/* Prepares value of a field for a write to an enet qos register + * + * reg: name of the register + * field: name of the bit field within the register + * val: value to put into the field + */ +#define ENET_QOS_REG_PREP(reg, field, val) FIELD_PREP(_ENET_QOS_REG_MASK(reg, field), val) + + +#define ENET_QOS_ALIGN_ADDR_SHIFT(x) (x >> (ENET_QOS_ALIGNMENT >> 1)) + +struct nxp_enet_qos_config { + const struct pinctrl_dev_config *pincfg; + const struct device *clock_dev; + clock_control_subsys_t clock_subsys; + enet_qos_t *base; +}; +#define ENET_QOS_MODULE_CFG(module_dev) ((struct nxp_enet_qos_config *) module_dev->config) + +#endif /* ZEPHYR_INCLUDE_DRIVERS_ETH_NXP_ENET_H__ */ From e90fa0399be3ef91638be09f2dca5253cc8a2e9a Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Fri, 1 Mar 2024 14:33:15 -0600 Subject: [PATCH 1738/2402] drivers: mdio: Add NXP ENET QOS MDIO Driver Add driver for NXP ENET QOS MDIO Signed-off-by: Declan Snyder --- drivers/mdio/CMakeLists.txt | 1 + drivers/mdio/Kconfig | 1 + drivers/mdio/Kconfig.nxp_enet_qos | 31 +++++ drivers/mdio/mdio_nxp_enet_qos.c | 217 ++++++++++++++++++++++++++++++ drivers/mdio/mdio_shell.c | 2 + 5 files changed, 252 insertions(+) create mode 100644 drivers/mdio/Kconfig.nxp_enet_qos create mode 100644 drivers/mdio/mdio_nxp_enet_qos.c diff --git a/drivers/mdio/CMakeLists.txt b/drivers/mdio/CMakeLists.txt index 30c6b9f8306..ad63d34f4ad 100644 --- a/drivers/mdio/CMakeLists.txt +++ b/drivers/mdio/CMakeLists.txt @@ -11,3 +11,4 @@ zephyr_library_sources_ifdef(CONFIG_MDIO_ADIN2111 mdio_adin2111.c) zephyr_library_sources_ifdef(CONFIG_MDIO_GPIO mdio_gpio.c) zephyr_library_sources_ifdef(CONFIG_MDIO_NXP_ENET mdio_nxp_enet.c) zephyr_library_sources_ifdef(CONFIG_MDIO_INFINEON_XMC4XXX mdio_xmc4xxx.c) +zephyr_library_sources_ifdef(CONFIG_MDIO_NXP_ENET_QOS mdio_nxp_enet_qos.c) diff --git a/drivers/mdio/Kconfig b/drivers/mdio/Kconfig index 2ff20df0b24..4af6827e8b7 100644 --- a/drivers/mdio/Kconfig +++ b/drivers/mdio/Kconfig @@ -32,6 +32,7 @@ source "drivers/mdio/Kconfig.adin2111" source "drivers/mdio/Kconfig.gpio" source "drivers/mdio/Kconfig.nxp_enet" source "drivers/mdio/Kconfig.xmc4xxx" +source "drivers/mdio/Kconfig.nxp_enet_qos" config MDIO_INIT_PRIORITY int "Init priority" diff --git a/drivers/mdio/Kconfig.nxp_enet_qos b/drivers/mdio/Kconfig.nxp_enet_qos new file mode 100644 index 00000000000..0274ba4c250 --- /dev/null +++ b/drivers/mdio/Kconfig.nxp_enet_qos @@ -0,0 +1,31 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +config MDIO_NXP_ENET_QOS + bool "NXP ENET QoS MDIO driver" + default y + depends on DT_HAS_NXP_ENET_QOS_MDIO_ENABLED + help + Enable NXP ENET QOS (Quality of Service) MDIO driver. + +if MDIO_NXP_ENET_QOS + +config MDIO_NXP_ENET_QOS_RECHECK_COUNT + int "Number of times to recheck MDIO transaction status" + default 3 + help + Number of times that the driver should recheck the status + of an MDIO bus transaction before timing out + Timeout time is: + CONFIG_MDIO_NXP_ENET_QOS_RECHECK_TIME * CONFIG_MDIO_NXP_ENET_QOS_RECHECK_COUNT + +config MDIO_NXP_ENET_QOS_RECHECK_TIME + int "Time between rechecks of transaction status (us)" + default 100 + help + The amount of time in microseconds that the driver should + busy wait between checks of the MDIO transaction status. + Timeout time is: + CONFIG_MDIO_NXP_ENET_QOS_RECHECK_TIME * CONFIG_MDIO_NXP_ENET_QOS_RECHECK_COUNT + +endif diff --git a/drivers/mdio/mdio_nxp_enet_qos.c b/drivers/mdio/mdio_nxp_enet_qos.c new file mode 100644 index 00000000000..e853d16b15f --- /dev/null +++ b/drivers/mdio/mdio_nxp_enet_qos.c @@ -0,0 +1,217 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_enet_qos_mdio + +#include +#include +#include +#include +#include +#include + +#include +LOG_MODULE_REGISTER(mdio_nxp_enet_qos, CONFIG_MDIO_LOG_LEVEL); + +struct nxp_enet_qos_mdio_config { + const struct device *enet_dev; +}; + +struct nxp_enet_qos_mdio_data { + struct k_mutex mdio_mutex; +}; + +struct mdio_transaction { + enum mdio_opcode op; + union { + uint16_t write_data; + uint16_t *read_data; + }; + uint8_t portaddr; + uint8_t regaddr; + enet_qos_t *base; + struct k_mutex *mdio_bus_mutex; +}; + +static bool check_busy(enet_qos_t *base) +{ + uint32_t val = base->MAC_MDIO_ADDRESS; + + /* Return the busy bit */ + return ENET_QOS_REG_GET(MAC_MDIO_ADDRESS, GB, val); +} + +static int do_transaction(struct mdio_transaction *mdio) +{ + enet_qos_t *base = mdio->base; + uint8_t goc_1_code; + int ret; + + k_mutex_lock(mdio->mdio_bus_mutex, K_FOREVER); + + if (mdio->op == MDIO_OP_C22_WRITE) { + base->MAC_MDIO_DATA = + /* Prepare the data to be written */ + ENET_QOS_REG_PREP(MAC_MDIO_DATA, GD, mdio->write_data); + goc_1_code = 0b0; + } else if (mdio->op == MDIO_OP_C22_READ) { + goc_1_code = 0b1; + } else { + ret = -EINVAL; + goto done; + } + + base->MAC_MDIO_ADDRESS = + /* OP command */ + ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, GOC_1, goc_1_code) | + ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, GOC_0, 0b1) | + /* PHY address */ + ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, PA, mdio->portaddr) | + /* Register address */ + ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, RDA, mdio->regaddr); + + base->MAC_MDIO_ADDRESS = + /* Start the transaction */ + ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, GB, 0b1); + + + ret = -ETIMEDOUT; + for (int i = CONFIG_MDIO_NXP_ENET_QOS_RECHECK_COUNT; i > 0; i--) { + if (!check_busy(base)) { + ret = 0; + break; + } + k_busy_wait(CONFIG_MDIO_NXP_ENET_QOS_RECHECK_TIME); + } + + if (ret) { + LOG_ERR("MDIO transaction timed out"); + goto done; + } + + if (mdio->op == MDIO_OP_C22_READ) { + uint32_t val = mdio->base->MAC_MDIO_DATA; + + *mdio->read_data = + /* Decipher the read data */ + ENET_QOS_REG_GET(MAC_MDIO_DATA, GD, val); + } + +done: + k_mutex_unlock(mdio->mdio_bus_mutex); + + return ret; +} + +static int nxp_enet_qos_mdio_read(const struct device *dev, + uint8_t portaddr, uint8_t regaddr, + uint16_t *read_data) +{ + const struct nxp_enet_qos_mdio_config *config = dev->config; + struct nxp_enet_qos_mdio_data *data = dev->data; + enet_qos_t *base = ENET_QOS_MODULE_CFG(config->enet_dev)->base; + struct mdio_transaction mdio_read = { + .op = MDIO_OP_C22_READ, + .read_data = read_data, + .portaddr = portaddr, + .regaddr = regaddr, + .base = base, + .mdio_bus_mutex = &data->mdio_mutex, + }; + + return do_transaction(&mdio_read); +} + +static int nxp_enet_qos_mdio_write(const struct device *dev, + uint8_t portaddr, uint8_t regaddr, + uint16_t write_data) +{ + const struct nxp_enet_qos_mdio_config *config = dev->config; + struct nxp_enet_qos_mdio_data *data = dev->data; + enet_qos_t *base = ENET_QOS_MODULE_CFG(config->enet_dev)->base; + struct mdio_transaction mdio_write = { + .op = MDIO_OP_C22_WRITE, + .write_data = write_data, + .portaddr = portaddr, + .regaddr = regaddr, + .base = base, + .mdio_bus_mutex = &data->mdio_mutex, + }; + + return do_transaction(&mdio_write); +} + +static void nxp_enet_qos_mdio_bus_fn(const struct device *dev) +{ + /* Intentionally empty. IP does not support this functionality. */ + ARG_UNUSED(dev); +} + +static const struct mdio_driver_api nxp_enet_qos_mdio_api = { + .read = nxp_enet_qos_mdio_read, + .write = nxp_enet_qos_mdio_write, + .bus_enable = nxp_enet_qos_mdio_bus_fn, + .bus_disable = nxp_enet_qos_mdio_bus_fn, +}; + +static int nxp_enet_qos_mdio_init(const struct device *dev) +{ + const struct nxp_enet_qos_mdio_config *mdio_config = dev->config; + struct nxp_enet_qos_mdio_data *data = dev->data; + const struct nxp_enet_qos_config *config = ENET_QOS_MODULE_CFG(mdio_config->enet_dev); + uint32_t enet_module_clk_rate; + int ret, divider; + + ret = k_mutex_init(&data->mdio_mutex); + if (ret) { + return ret; + } + + ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, + &enet_module_clk_rate); + if (ret) { + return ret; + } + + enet_module_clk_rate /= 1000000; + if (enet_module_clk_rate >= 20 && enet_module_clk_rate < 35) { + divider = 2; + } else if (enet_module_clk_rate < 60) { + divider = 3; + } else if (enet_module_clk_rate < 100) { + divider = 0; + } else if (enet_module_clk_rate < 150) { + divider = 1; + } else if (enet_module_clk_rate < 250) { + divider = 4; + } else { + LOG_ERR("ENET QOS clk rate does not allow MDIO"); + return -ENOTSUP; + } + + config->base->MAC_MDIO_ADDRESS = + /* Configure the MDIO clock range / divider */ + ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, CR, divider); + + return 0; +} + +#define NXP_ENET_QOS_MDIO_INIT(inst) \ + \ + static const struct nxp_enet_qos_mdio_config \ + nxp_enet_qos_mdio_cfg_##inst = { \ + .enet_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \ + }; \ + \ + static struct nxp_enet_qos_mdio_data nxp_enet_qos_mdio_data_##inst; \ + \ + DEVICE_DT_INST_DEFINE(inst, &nxp_enet_qos_mdio_init, NULL, \ + &nxp_enet_qos_mdio_data_##inst, \ + &nxp_enet_qos_mdio_cfg_##inst, \ + POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, \ + &nxp_enet_qos_mdio_api); \ + +DT_INST_FOREACH_STATUS_OKAY(NXP_ENET_QOS_MDIO_INIT) diff --git a/drivers/mdio/mdio_shell.c b/drivers/mdio/mdio_shell.c index 376e95244fa..371582e5757 100644 --- a/drivers/mdio/mdio_shell.c +++ b/drivers/mdio/mdio_shell.c @@ -33,6 +33,8 @@ LOG_MODULE_REGISTER(mdio_shell, CONFIG_LOG_DEFAULT_LEVEL); #define DT_DRV_COMPAT nxp_enet_mdio #elif DT_HAS_COMPAT_STATUS_OKAY(infineon_xmc4xxx_mdio) #define DT_DRV_COMPAT infineon_xmc4xxx_mdio +#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_enet_qos_mdio) +#define DT_DRV_COMPAT nxp_enet_qos_mdio #else #error "No known devicetree compatible match for MDIO shell" #endif From 62b56bb3135f3b746ea363b4006e7bb731cec333 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Fri, 1 Mar 2024 14:33:38 -0600 Subject: [PATCH 1739/2402] drivers: ethernet: Add NXP ENET QOS Driver Add driver for NXP ENET QOS Ethernet Signed-off-by: Declan Snyder --- drivers/ethernet/CMakeLists.txt | 1 + drivers/ethernet/Kconfig | 2 + .../ethernet/eth_nxp_enet_qos/CMakeLists.txt | 5 + drivers/ethernet/eth_nxp_enet_qos/Kconfig | 60 ++ .../eth_nxp_enet_qos/eth_nxp_enet_qos.c | 44 ++ .../eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c | 622 ++++++++++++++++++ .../eth_nxp_enet_qos/nxp_enet_qos_priv.h | 116 ++++ 7 files changed, 850 insertions(+) create mode 100644 drivers/ethernet/eth_nxp_enet_qos/CMakeLists.txt create mode 100644 drivers/ethernet/eth_nxp_enet_qos/Kconfig create mode 100644 drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos.c create mode 100644 drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c create mode 100644 drivers/ethernet/eth_nxp_enet_qos/nxp_enet_qos_priv.h diff --git a/drivers/ethernet/CMakeLists.txt b/drivers/ethernet/CMakeLists.txt index fcc43cf77f7..f8c2ee04df5 100644 --- a/drivers/ethernet/CMakeLists.txt +++ b/drivers/ethernet/CMakeLists.txt @@ -67,3 +67,4 @@ if(CONFIG_ETH_NATIVE_POSIX) endif() add_subdirectory(phy) +add_subdirectory(eth_nxp_enet_qos) diff --git a/drivers/ethernet/Kconfig b/drivers/ethernet/Kconfig index 4d7facdfff0..12283d39012 100644 --- a/drivers/ethernet/Kconfig +++ b/drivers/ethernet/Kconfig @@ -76,6 +76,8 @@ source "drivers/ethernet/Kconfig.lan865x" source "drivers/ethernet/Kconfig.nxp_enet" source "drivers/ethernet/Kconfig.xmc4xxx" +source "drivers/ethernet/eth_nxp_enet_qos/Kconfig" + source "drivers/ethernet/phy/Kconfig" endif # "Ethernet Drivers" diff --git a/drivers/ethernet/eth_nxp_enet_qos/CMakeLists.txt b/drivers/ethernet/eth_nxp_enet_qos/CMakeLists.txt new file mode 100644 index 00000000000..7035eb59059 --- /dev/null +++ b/drivers/ethernet/eth_nxp_enet_qos/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources_ifdef(CONFIG_ETH_NXP_ENET_QOS eth_nxp_enet_qos.c) +zephyr_library_sources_ifdef(CONFIG_ETH_NXP_ENET_QOS_MAC eth_nxp_enet_qos_mac.c) diff --git a/drivers/ethernet/eth_nxp_enet_qos/Kconfig b/drivers/ethernet/eth_nxp_enet_qos/Kconfig new file mode 100644 index 00000000000..062a9ecee18 --- /dev/null +++ b/drivers/ethernet/eth_nxp_enet_qos/Kconfig @@ -0,0 +1,60 @@ +# Copyright 2024 +# SPDX-License-Identifier: Apache-2.0 + +menuconfig ETH_NXP_ENET_QOS + bool "NXP ENET QOS Ethernet Module Driver" + default y + depends on DT_HAS_NXP_ENET_QOS_ENABLED + select MDIO if DT_HAS_NXP_ENET_QOS_MDIO_ENABLED + help + Enable NXP ENET Ethernet Module Driver. This driver + handles IP module level tasks. + +if ETH_NXP_ENET_QOS + +config ETH_NXP_ENET_QOS_MAC + bool "NXP ENET QOS Ethernet MAC Driver" + default y + depends on DT_HAS_NXP_ENET_QOS_MAC_ENABLED + depends on NET_BUF_FIXED_DATA_SIZE + help + Enable NXP ENET QOS Ethernet MAC Driver. + +if ETH_NXP_ENET_QOS_MAC + +config ETH_NXP_ENET_QOS_TX_BUFFER_DESCRIPTORS + int "Number of tx buffer descriptors" + default 4 + range 4 1024 + help + Number of TX buffer descriptors. + +config ETH_NXP_ENET_QOS_RX_BUFFER_DESCRIPTORS + int "Number of rx buffer descriptors" + default 4 + range 4 1024 + help + Number of RX buffer descriptors. + +config ETH_NXP_ENET_QOS_DMA_RESET_WAIT_TIME + int "Time in microseconds to wait for software reset" + default 10 + range 0 1000 + help + Time in us microseconds allow for software reset. + Value of 0 will allow the driver to wait unlimited time. + +config ETH_NXP_ENET_QOS_RX_THREAD_STACK_SIZE + int "Size of ENET QOS RX thread stack" + default 1024 + help + Size in bytes of the ENET QOS RX thread stack. + +config ETH_NXP_ENET_QOS_RX_THREAD_PRIORITY + int "Cooperative priority of the ENET QOS RX thread" + default 3 + help + Cooperative priority of the ENET QOS RX thread + +endif # ETH_NXP_ENET_QOS_MAC +endif # ETH_NXP_ENET_QOS diff --git a/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos.c b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos.c new file mode 100644 index 00000000000..aa89232a560 --- /dev/null +++ b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos.c @@ -0,0 +1,44 @@ +/* NXP ENET QOS Ethernet MAC Driver + * + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_enet_qos + +#include +#include + +int nxp_enet_qos_init(const struct device *dev) +{ + const struct nxp_enet_qos_config *config = dev->config; + int ret; + + /* TODO: once NXP reset drivers are created, use that to reset + * until then, make sure reset is done in platform init + */ + + ret = clock_control_on(config->clock_dev, config->clock_subsys); + if (ret) { + return ret; + } + + return pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); +} + +#define NXP_ENET_QOS_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + \ + static const struct nxp_enet_qos_config enet_qos_##n##_config = { \ + .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clock_subsys = (void *)DT_INST_CLOCKS_CELL_BY_IDX(n, 0, name), \ + .base = (enet_qos_t *)DT_INST_REG_ADDR(n), \ + }; \ + \ + /* Init the module before any enet device inits so priority 0 */ \ + DEVICE_DT_INST_DEFINE(n, nxp_enet_qos_init, NULL, NULL, \ + &enet_qos_##n##_config, POST_KERNEL, 0, NULL); + +DT_INST_FOREACH_STATUS_OKAY(NXP_ENET_QOS_INIT) diff --git a/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c new file mode 100644 index 00000000000..bba9d1df7e1 --- /dev/null +++ b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c @@ -0,0 +1,622 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_enet_qos_mac + +#include +LOG_MODULE_REGISTER(eth_nxp_enet_qos_mac, CONFIG_ETHERNET_LOG_LEVEL); + +#include +#include +#include +#include +#include "../eth.h" +#include "nxp_enet_qos_priv.h" + +static const uint32_t rx_desc_refresh_flags = + OWN_FLAG | RX_INTERRUPT_ON_COMPLETE_FLAG | BUF1_ADDR_VALID_FLAG; + +K_THREAD_STACK_DEFINE(enet_qos_rx_stack, CONFIG_ETH_NXP_ENET_QOS_RX_THREAD_STACK_SIZE); +static struct k_work_q rx_work_queue; + +static int rx_queue_init(void) +{ + struct k_work_queue_config cfg = {.name = "ENETQOS_RX"}; + + k_work_queue_init(&rx_work_queue); + k_work_queue_start(&rx_work_queue, enet_qos_rx_stack, + K_THREAD_STACK_SIZEOF(enet_qos_rx_stack), + K_PRIO_COOP(CONFIG_ETH_NXP_ENET_QOS_RX_THREAD_PRIORITY), + &cfg); + + return 0; +} + +SYS_INIT(rx_queue_init, POST_KERNEL, 0); + +static void eth_nxp_enet_qos_iface_init(struct net_if *iface) +{ + const struct device *dev = net_if_get_device(iface); + struct nxp_enet_qos_mac_data *data = dev->data; + + net_if_set_link_addr(iface, data->mac_addr.addr, + sizeof(((struct net_eth_addr *)NULL)->addr), NET_LINK_ETHERNET); + + if (data->iface == NULL) { + data->iface = iface; + } + + ethernet_init(iface); +} + +static int eth_nxp_enet_qos_tx(const struct device *dev, struct net_pkt *pkt) +{ + const struct nxp_enet_qos_mac_config *config = dev->config; + struct nxp_enet_qos_mac_data *data = dev->data; + enet_qos_t *base = config->base; + + volatile union nxp_enet_qos_tx_desc *tx_desc_ptr = data->tx.descriptors; + volatile union nxp_enet_qos_tx_desc *last_desc_ptr; + + struct net_buf *fragment = pkt->frags; + int frags_count = 0, total_bytes = 0; + + /* Only allow send of the maximum normal packet size */ + while (fragment != NULL) { + frags_count++; + total_bytes += fragment->len; + fragment = fragment->frags; + } + + if (total_bytes > config->hw_info.max_frame_len || + frags_count > NUM_TX_BUFDESC) { + LOG_ERR("TX packet too large"); + return -E2BIG; + } + + /* One TX at a time in the current implementation */ + k_sem_take(&data->tx.tx_sem, K_FOREVER); + + net_pkt_ref(pkt); + + data->tx.pkt = pkt; + /* Need to save the header because the ethernet stack + * otherwise discards it from the packet after this call + */ + data->tx.tx_header = pkt->frags; + + LOG_DBG("Setting up TX descriptors for packet %p", pkt); + + /* Reset the descriptors */ + memset((void *)data->tx.descriptors, 0, sizeof(union nxp_enet_qos_tx_desc) * frags_count); + + /* Setting up the descriptors */ + fragment = pkt->frags; + tx_desc_ptr->read.control2 |= FIRST_TX_DESCRIPTOR_FLAG; + for (int i = 0; i < frags_count; i++) { + net_pkt_frag_ref(fragment); + + tx_desc_ptr->read.buf1_addr = (uint32_t)fragment->data; + tx_desc_ptr->read.control1 = FIELD_PREP(0x3FFF, fragment->len); + tx_desc_ptr->read.control2 |= FIELD_PREP(0x7FFF, total_bytes); + + fragment = fragment->frags; + tx_desc_ptr++; + } + last_desc_ptr = tx_desc_ptr - 1; + last_desc_ptr->read.control2 |= LAST_TX_DESCRIPTOR_FLAG; + last_desc_ptr->read.control1 |= TX_INTERRUPT_ON_COMPLETE_FLAG; + + LOG_DBG("Starting TX DMA on packet %p", pkt); + + /* Set the DMA ownership of all the used descriptors */ + for (int i = 0; i < frags_count; i++) { + data->tx.descriptors[i].read.control2 |= OWN_FLAG; + } + + /* This implementation is clearly naive and basic, it just changes the + * ring length for every TX send, there is room for optimization + */ + base->DMA_CH[0].DMA_CHX_TXDESC_RING_LENGTH = frags_count - 1; + base->DMA_CH[0].DMA_CHX_TXDESC_TAIL_PTR = + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_TXDESC_TAIL_PTR, TDTP, + ENET_QOS_ALIGN_ADDR_SHIFT((uint32_t) tx_desc_ptr)); + + return 0; +} + +static void tx_dma_done(struct k_work *work) +{ + struct nxp_enet_qos_tx_data *tx_data = + CONTAINER_OF(work, struct nxp_enet_qos_tx_data, tx_done_work); + struct nxp_enet_qos_mac_data *data = + CONTAINER_OF(tx_data, struct nxp_enet_qos_mac_data, tx); + struct net_pkt *pkt = tx_data->pkt; + struct net_buf *fragment = pkt->frags; + + LOG_DBG("TX DMA completed on packet %p", pkt); + + /* Returning the buffers and packet to the pool */ + while (fragment != NULL) { + net_pkt_frag_unref(fragment); + fragment = fragment->frags; + } + + net_pkt_frag_unref(tx_data->tx_header); + net_pkt_unref(pkt); + + eth_stats_update_pkts_tx(data->iface); + + /* Allows another send */ + k_sem_give(&tx_data->tx_sem); +} + +static enum ethernet_hw_caps eth_nxp_enet_qos_get_capabilities(const struct device *dev) +{ + return ETHERNET_LINK_100BASE_T | ETHERNET_LINK_10BASE_T; +} + +static void eth_nxp_enet_qos_rx(struct k_work *work) +{ + struct nxp_enet_qos_rx_data *rx_data = + CONTAINER_OF(work, struct nxp_enet_qos_rx_data, rx_work); + struct nxp_enet_qos_mac_data *data = + CONTAINER_OF(rx_data, struct nxp_enet_qos_mac_data, rx); + volatile union nxp_enet_qos_rx_desc *desc_arr = rx_data->descriptors; + volatile union nxp_enet_qos_rx_desc *desc; + struct net_pkt *pkt; + struct net_buf *new_buf; + struct net_buf *buf; + size_t pkt_len; + + /* We are going to find all of the descriptors we own and update them */ + for (int i = 0; i < NUM_RX_BUFDESC; i++) { + desc = &desc_arr[i]; + + if (desc->write.control3 & OWN_FLAG) { + /* The DMA owns the descriptor, we cannot touch it */ + continue; + } + + /* Otherwise, we found a packet that we need to process */ + pkt = net_pkt_rx_alloc(K_NO_WAIT); + + if (!pkt) { + LOG_ERR("Could not alloc RX pkt"); + goto error; + } + + LOG_DBG("Created RX pkt %p", pkt); + + /* We need to know if we can replace the reserved fragment in advance. + * At no point can we allow the driver to have less the amount of reserved + * buffers it needs to function, so we will not give up our previous buffer + * unless we know we can get a new one. + */ + new_buf = net_pkt_get_frag(pkt, CONFIG_NET_BUF_DATA_SIZE, K_NO_WAIT); + if (new_buf == NULL) { + /* We have no choice but to lose the previous packet, + * as the buffer is more important. If we recv this packet, + * we don't know what the upper layer will do to our poor buffer. + */ + LOG_ERR("No RX buf available"); + goto error; + } + + buf = rx_data->reserved_bufs[i]; + pkt_len = desc->write.control3 & DESC_RX_PKT_LEN; + + LOG_DBG("Receiving RX packet"); + + /* Finally, we have decided that it is time to wrap the buffer nicely + * up within a packet, and try to send it. It's only one buffer, + * thanks to ENET QOS hardware handing the fragmentation, + * so the construction of the packet is very simple. + */ + net_buf_add(buf, pkt_len); + net_pkt_frag_insert(pkt, buf); + if (net_recv_data(data->iface, pkt)) { + LOG_ERR("RECV failed"); + /* Quite a shame. */ + goto error; + } + + LOG_DBG("Recycling RX buf"); + + /* Fresh meat */ + rx_data->reserved_bufs[i] = new_buf; + desc->read.buf1_addr = (uint32_t)new_buf->data; + desc->read.control |= rx_desc_refresh_flags; + + /* Record our glorious victory */ + eth_stats_update_pkts_rx(data->iface); + } + + return; + +error: + net_pkt_unref(pkt); + eth_stats_update_errors_rx(data->iface); +} + +static void eth_nxp_enet_qos_mac_isr(const struct device *dev) +{ + const struct nxp_enet_qos_mac_config *config = dev->config; + struct nxp_enet_qos_mac_data *data = dev->data; + enet_qos_t *base = config->base; + + /* cleared on read */ + volatile uint32_t mac_interrupts = base->MAC_INTERRUPT_STATUS; + volatile uint32_t mac_rx_tx_status = base->MAC_RX_TX_STATUS; + volatile uint32_t dma_interrupts = base->DMA_INTERRUPT_STATUS; + volatile uint32_t dma_ch0_interrupts = base->DMA_CH[0].DMA_CHX_STAT; + + mac_interrupts; mac_rx_tx_status; + + base->DMA_CH[0].DMA_CHX_STAT = 0xFFFFFFFF; + + if (ENET_QOS_REG_GET(DMA_INTERRUPT_STATUS, DC0IS, dma_interrupts)) { + if (ENET_QOS_REG_GET(DMA_CH_DMA_CHX_STAT, TI, dma_ch0_interrupts)) { + k_work_submit(&data->tx.tx_done_work); + } + if (ENET_QOS_REG_GET(DMA_CH_DMA_CHX_STAT, RI, dma_ch0_interrupts)) { + k_work_submit_to_queue(&rx_work_queue, &data->rx.rx_work); + } + } +} + +static void eth_nxp_enet_qos_phy_cb(const struct device *phy, + struct phy_link_state *state, void *eth_dev) +{ + const struct device *dev = eth_dev; + struct nxp_enet_qos_mac_data *data = dev->data; + + if (!data->iface) { + return; + } + + if (state->is_up) { + net_eth_carrier_on(data->iface); + } else { + net_eth_carrier_off(data->iface); + } + + LOG_INF("Link is %s", state->is_up ? "up" : "down"); +} + +static inline int enet_qos_dma_reset(enet_qos_t *base) +{ + /* Set the software reset of the DMA */ + base->DMA_MODE |= ENET_QOS_REG_PREP(DMA_MODE, SWR, 0b1); + + if (CONFIG_ETH_NXP_ENET_QOS_DMA_RESET_WAIT_TIME == 0) { + /* spin and wait forever for the reset flag to clear */ + while (ENET_QOS_REG_GET(DMA_MODE, SWR, base->DMA_MODE)) + ; + goto done; + } + + int wait_chunk = DIV_ROUND_UP(CONFIG_ETH_NXP_ENET_QOS_DMA_RESET_WAIT_TIME, + NUM_SWR_WAIT_CHUNKS); + + for (int time_elapsed = 0; + time_elapsed < CONFIG_ETH_NXP_ENET_QOS_DMA_RESET_WAIT_TIME; + time_elapsed += wait_chunk) { + + k_busy_wait(wait_chunk); + + if (!ENET_QOS_REG_GET(DMA_MODE, SWR, base->DMA_MODE)) { + /* DMA cleared the bit */ + goto done; + } + } + + /* all ENET QOS domain clocks must resolve to clear software reset, + * if getting this error, try checking phy clock connection + */ + LOG_ERR("Can't clear SWR"); + return -EIO; + +done: + return 0; +} + +static inline void enet_qos_dma_config_init(enet_qos_t *base) +{ + base->DMA_CH[0].DMA_CHX_TX_CTRL |= + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_TX_CTRL, TxPBL, 0b1); + base->DMA_CH[0].DMA_CHX_RX_CTRL |= + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_RX_CTRL, RxPBL, 0b1); +} + +static inline void enet_qos_mtl_config_init(enet_qos_t *base) +{ + base->MTL_QUEUE[0].MTL_TXQX_OP_MODE |= + /* Flush the queue */ + ENET_QOS_REG_PREP(MTL_QUEUE_MTL_TXQX_OP_MODE, FTQ, 0b1); + + /* Wait for flush to finish */ + while (ENET_QOS_REG_GET(MTL_QUEUE_MTL_TXQX_OP_MODE, FTQ, + base->MTL_QUEUE[0].MTL_TXQX_OP_MODE)) + ; + + /* Enable only Transmit Queue 0 (optimization/configuration pending) with maximum size */ + base->MTL_QUEUE[0].MTL_TXQX_OP_MODE = + /* Sets the size */ + ENET_QOS_REG_PREP(MTL_QUEUE_MTL_TXQX_OP_MODE, TQS, 0b111) | + /* Sets it to on */ + ENET_QOS_REG_PREP(MTL_QUEUE_MTL_TXQX_OP_MODE, TXQEN, 0b10); + + /* Enable only Receive Queue 0 (optimization/configuration pending) with maximum size */ + base->MTL_QUEUE[0].MTL_RXQX_OP_MODE |= + /* Sets the size */ + ENET_QOS_REG_PREP(MTL_QUEUE_MTL_RXQX_OP_MODE, RQS, 0b111) | + /* Keep small packets */ + ENET_QOS_REG_PREP(MTL_QUEUE_MTL_RXQX_OP_MODE, FUP, 0b1); +} + +static inline void enet_qos_mac_config_init(enet_qos_t *base, + struct nxp_enet_qos_mac_data *data, uint32_t clk_rate) +{ + /* Set MAC address */ + base->MAC_ADDRESS0_HIGH = + ENET_QOS_REG_PREP(MAC_ADDRESS0_HIGH, ADDRHI, + data->mac_addr.addr[5] << 8 | + data->mac_addr.addr[4]); + base->MAC_ADDRESS0_LOW = + ENET_QOS_REG_PREP(MAC_ADDRESS0_LOW, ADDRLO, + data->mac_addr.addr[3] << 24 | + data->mac_addr.addr[2] << 16 | + data->mac_addr.addr[1] << 8 | + data->mac_addr.addr[0]); + + /* Set the reference for 1 microsecond of ENET QOS CSR clock cycles */ + base->MAC_ONEUS_TIC_COUNTER = + ENET_QOS_REG_PREP(MAC_ONEUS_TIC_COUNTER, TIC_1US_CNTR, + (clk_rate / USEC_PER_SEC) - 1); + + base->MAC_CONFIGURATION |= + /* For 10/100 Mbps operation */ + ENET_QOS_REG_PREP(MAC_CONFIGURATION, PS, 0b1) | + /* Full duplex mode */ + ENET_QOS_REG_PREP(MAC_CONFIGURATION, DM, 0b1) | + /* 100 Mbps mode */ + ENET_QOS_REG_PREP(MAC_CONFIGURATION, FES, 0b1) | + /* Don't talk unless no one else is talking */ + ENET_QOS_REG_PREP(MAC_CONFIGURATION, ECRSFD, 0b1); + + /* Enable the MAC RX channel 0 */ + base->MAC_RXQ_CTRL[0] |= + ENET_QOS_REG_PREP(MAC_RXQ_CTRL, RXQ0EN, 0b1); +} + +static inline void enet_qos_start(enet_qos_t *base) +{ + /* Set start bits of the RX and TX DMAs */ + base->DMA_CH[0].DMA_CHX_RX_CTRL |= + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_RX_CTRL, SR, 0b1); + base->DMA_CH[0].DMA_CHX_TX_CTRL |= + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_TX_CTRL, ST, 0b1); + + /* Enable interrupts */ + base->DMA_CH[0].DMA_CHX_INT_EN = + /* Normal interrupts (includes tx, rx) */ + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_INT_EN, NIE, 0b1) | + /* Transmit interrupt */ + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_INT_EN, TIE, 0b1) | + /* Receive interrupt */ + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_INT_EN, RIE, 0b1); + base->MAC_INTERRUPT_ENABLE = + /* Receive and Transmit IRQs */ + ENET_QOS_REG_PREP(MAC_INTERRUPT_ENABLE, TXSTSIE, 0b1) | + ENET_QOS_REG_PREP(MAC_INTERRUPT_ENABLE, RXSTSIE, 0b1); + + /* Start the TX and RX on the MAC */ + base->MAC_CONFIGURATION |= + ENET_QOS_REG_PREP(MAC_CONFIGURATION, TE, 0b1) | + ENET_QOS_REG_PREP(MAC_CONFIGURATION, RE, 0b1); +} + +static inline void enet_qos_tx_desc_init(enet_qos_t *base, struct nxp_enet_qos_tx_data *tx) +{ + memset((void *)tx->descriptors, 0, sizeof(union nxp_enet_qos_tx_desc) * NUM_TX_BUFDESC); + + base->DMA_CH[0].DMA_CHX_TXDESC_LIST_ADDR = + /* Start of tx descriptors buffer */ + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_TXDESC_LIST_ADDR, TDESLA, + ENET_QOS_ALIGN_ADDR_SHIFT((uint32_t)tx->descriptors)); + base->DMA_CH[0].DMA_CHX_TXDESC_TAIL_PTR = + /* Do not move the tail pointer past the start until send is requested */ + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_TXDESC_TAIL_PTR, TDTP, + ENET_QOS_ALIGN_ADDR_SHIFT((uint32_t)tx->descriptors)); + base->DMA_CH[0].DMA_CHX_TXDESC_RING_LENGTH = + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_TXDESC_RING_LENGTH, TDRL, NUM_TX_BUFDESC); +} + +static inline int enet_qos_rx_desc_init(enet_qos_t *base, struct nxp_enet_qos_rx_data *rx) +{ + struct net_buf *buf; + + memset((void *)rx->descriptors, 0, sizeof(union nxp_enet_qos_rx_desc) * NUM_RX_BUFDESC); + + /* Here we reserve an RX buffer for each of the DMA descriptors. */ + for (int i = 0; i < NUM_RX_BUFDESC; i++) { + buf = net_pkt_get_reserve_rx_data(CONFIG_NET_BUF_DATA_SIZE, K_NO_WAIT); + if (buf == NULL) { + LOG_ERR("Missing a buf"); + return -ENOMEM; + } + rx->reserved_bufs[i] = buf; + rx->descriptors[i].read.buf1_addr = (uint32_t)buf->data; + rx->descriptors[i].read.control |= rx_desc_refresh_flags; + } + + /* Set up RX descriptors on channel 0 */ + base->DMA_CH[0].DMA_CHX_RXDESC_LIST_ADDR = + /* Start of tx descriptors buffer */ + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_RXDESC_LIST_ADDR, RDESLA, + ENET_QOS_ALIGN_ADDR_SHIFT((uint32_t)&rx->descriptors[0])); + base->DMA_CH[0].DMA_CHX_RXDESC_TAIL_PTR = + /* When the DMA reaches the tail pointer, it suspends. Set to last descriptor */ + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_RXDESC_TAIL_PTR, RDTP, + ENET_QOS_ALIGN_ADDR_SHIFT((uint32_t)&rx->descriptors[NUM_RX_BUFDESC])); + base->DMA_CH[0].DMA_CHX_RX_CONTROL2 = + /* Ring length == Buffer size. Register is this value minus one. */ + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_RX_CONTROL2, RDRL, NUM_RX_BUFDESC - 1); + base->DMA_CH[0].DMA_CHX_RX_CTRL |= + /* Set DMA receive buffer size. The low 2 bits are not entered to this field. */ + ENET_QOS_REG_PREP(DMA_CH_DMA_CHX_RX_CTRL, RBSZ_13_Y, NET_ETH_MAX_FRAME_SIZE >> 2); + + return 0; +} + +static int eth_nxp_enet_qos_mac_init(const struct device *dev) +{ + const struct nxp_enet_qos_mac_config *config = dev->config; + struct nxp_enet_qos_mac_data *data = dev->data; + struct nxp_enet_qos_config *module_cfg = ENET_QOS_MODULE_CFG(config->enet_dev); + enet_qos_t *base = module_cfg->base; + uint32_t clk_rate; + int ret; + + /* Used to configure timings of the MAC */ + ret = clock_control_get_rate(module_cfg->clock_dev, module_cfg->clock_subsys, &clk_rate); + if (ret) { + return ret; + } + + /* For reporting the status of the link connection */ + ret = phy_link_callback_set(config->phy_dev, eth_nxp_enet_qos_phy_cb, (void *)dev); + if (ret) { + return ret; + } + + /* Random mac therefore overrides local mac that may have been initialized */ + if (config->random_mac) { + gen_random_mac(data->mac_addr.addr, + NXP_OUI_BYTE_0, NXP_OUI_BYTE_1, NXP_OUI_BYTE_2); + } + + /* This driver cannot work without interrupts. */ + if (config->irq_config_func) { + config->irq_config_func(); + } else { + return -ENOSYS; + } + + /* Effectively reset of the peripheral */ + ret = enet_qos_dma_reset(base); + if (ret) { + return ret; + } + + /* DMA is the interface presented to software for interaction by the ENET module */ + enet_qos_dma_config_init(base); + + /* + * MTL = MAC Translation Layer. + * MTL is an asynchronous circuit needed because the MAC transmitter/receiver + * and the DMA interface are on different clock domains, MTL compromises the two. + */ + enet_qos_mtl_config_init(base); + + /* Configuration of the actual MAC hardware */ + enet_qos_mac_config_init(base, data, clk_rate); + + /* Current use of TX descriptor in the driver is such that + * one packet is sent at a time, and each descriptor is used + * to collect the fragments of it from the networking stack, + * and send them with a zero copy implementation. + */ + enet_qos_tx_desc_init(base, &data->tx); + + /* Current use of RX descriptor in the driver is such that + * each RX descriptor corresponds to a reserved fragment, that will + * hold the entirety of the contents of a packet. And these fragments + * are recycled in and out of the RX pkt buf pool to achieve a zero copy implementation. + */ + ret = enet_qos_rx_desc_init(base, &data->rx); + if (ret) { + return ret; + } + + /* Clearly, start the cogs to motion. */ + enet_qos_start(base); + + /* The tx sem is taken during ethernet send function, + * and given when DMA transmission is finished. Ie, send calls will be blocked + * until the DMA is available again. This is therefore a simple but naive implementation. + */ + k_sem_init(&data->tx.tx_sem, 1, 1); + + /* Work upon a reception of a packet to a buffer */ + k_work_init(&data->rx.rx_work, eth_nxp_enet_qos_rx); + + /* Work upon a complete transmission by a channel's TX DMA */ + k_work_init(&data->tx.tx_done_work, tx_dma_done); + + return ret; +} + +static const struct ethernet_api api_funcs = { + .iface_api.init = eth_nxp_enet_qos_iface_init, + .send = eth_nxp_enet_qos_tx, + .get_capabilities = eth_nxp_enet_qos_get_capabilities, +}; + +#define NXP_ENET_QOS_NODE_HAS_MAC_ADDR_CHECK(n) \ + BUILD_ASSERT(NODE_HAS_VALID_MAC_ADDR(DT_DRV_INST(n)) || \ + DT_INST_NODE_HAS_PROP(n, zephyr_random_mac_address), \ + "MAC address not specified on ENET QOS DT node"); + +#define NXP_ENET_QOS_CONNECT_IRQS(node_id, prop, idx) \ + do { \ + IRQ_CONNECT(DT_IRQN_BY_IDX(node_id, idx), \ + DT_IRQ_BY_IDX(node_id, idx, priority), \ + eth_nxp_enet_qos_mac_isr, \ + DEVICE_DT_GET(node_id), \ + 0); \ + irq_enable(DT_IRQN_BY_IDX(node_id, idx)); \ + } while (false); + +#define NXP_ENET_QOS_IRQ_CONFIG_FUNC(n) \ + static void nxp_enet_qos_##n##_irq_config_func(void) \ + { \ + DT_FOREACH_PROP_ELEM(DT_DRV_INST(n), \ + interrupt_names, \ + NXP_ENET_QOS_CONNECT_IRQS) \ + } + +#define NXP_ENET_QOS_DRIVER_STRUCTS_INIT(n) \ + static const struct nxp_enet_qos_mac_config enet_qos_##n##_mac_config = { \ + .enet_dev = DEVICE_DT_GET(DT_INST_PARENT(n)), \ + .phy_dev = DEVICE_DT_GET(DT_INST_PHANDLE(n, phy_handle)), \ + .base = (enet_qos_t *)DT_REG_ADDR(DT_INST_PARENT(n)), \ + .hw_info = { \ + .max_frame_len = ENET_QOS_MAX_NORMAL_FRAME_LEN, \ + }, \ + .irq_config_func = nxp_enet_qos_##n##_irq_config_func, \ + .random_mac = DT_INST_PROP(n, zephyr_random_mac_address), \ + }; \ + \ + static struct nxp_enet_qos_mac_data enet_qos_##n##_mac_data = \ + { \ + .mac_addr.addr = DT_INST_PROP_OR(n, local_mac_address, {0}), \ + }; + +#define NXP_ENET_QOS_DRIVER_INIT(n) \ + NXP_ENET_QOS_NODE_HAS_MAC_ADDR_CHECK(n) \ + NXP_ENET_QOS_IRQ_CONFIG_FUNC(n) \ + NXP_ENET_QOS_DRIVER_STRUCTS_INIT(n) + +DT_INST_FOREACH_STATUS_OKAY(NXP_ENET_QOS_DRIVER_INIT) + +#define NXP_ENET_QOS_MAC_DEVICE_DEFINE(n) \ + ETH_NET_DEVICE_DT_INST_DEFINE(n, eth_nxp_enet_qos_mac_init, NULL, \ + &enet_qos_##n##_mac_data, &enet_qos_##n##_mac_config, \ + CONFIG_ETH_INIT_PRIORITY, &api_funcs, NET_ETH_MTU); + +DT_INST_FOREACH_STATUS_OKAY(NXP_ENET_QOS_MAC_DEVICE_DEFINE) diff --git a/drivers/ethernet/eth_nxp_enet_qos/nxp_enet_qos_priv.h b/drivers/ethernet/eth_nxp_enet_qos/nxp_enet_qos_priv.h new file mode 100644 index 00000000000..e1dcadc6fec --- /dev/null +++ b/drivers/ethernet/eth_nxp_enet_qos/nxp_enet_qos_priv.h @@ -0,0 +1,116 @@ +/* NXP ENET QOS Header + * + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/* shorthands */ +#define NUM_TX_BUFDESC CONFIG_ETH_NXP_ENET_QOS_TX_BUFFER_DESCRIPTORS +#define NUM_RX_BUFDESC CONFIG_ETH_NXP_ENET_QOS_RX_BUFFER_DESCRIPTORS +#define LAST_TX_DESC_INDEX NUM_TX_BUFDESC - 1 +#define LAST_RX_DESC_INDEX NUM_RX_BUFDESC - 1 + +/* NXP Organizational Unique Identifier */ +#define NXP_OUI_BYTE_0 0xAC +#define NXP_OUI_BYTE_1 0x9A +#define NXP_OUI_BYTE_2 0x22 + +#define FIRST_TX_DESCRIPTOR_FLAG BIT(29) +#define LAST_TX_DESCRIPTOR_FLAG BIT(28) +#define OWN_FLAG BIT(31) +#define RX_INTERRUPT_ON_COMPLETE_FLAG BIT(30) +#define TX_INTERRUPT_ON_COMPLETE_FLAG BIT(31) +#define BUF1_ADDR_VALID_FLAG BIT(24) +#define DESC_RX_PKT_LEN GENMASK(14, 0) + +#define ENET_QOS_MAX_NORMAL_FRAME_LEN 1518 + +#define NUM_SWR_WAIT_CHUNKS 5 + +struct nxp_enet_qos_tx_read_desc { + union { + uint32_t buf1_addr; + uint32_t head_addr; + }; + union { + uint32_t buf2_addr; + uint32_t buf1_addr_alt; + }; + uint32_t control1; + uint32_t control2; +}; + +struct nxp_enet_qos_tx_write_desc { + uint32_t timestamp_low; + uint32_t timestamp_high; + uint32_t reserved; + uint32_t status; +}; + +union nxp_enet_qos_tx_desc { + struct nxp_enet_qos_tx_read_desc read; + struct nxp_enet_qos_tx_write_desc write; +}; + +struct nxp_enet_qos_rx_read_desc { + union { + uint32_t buf1_addr; + uint32_t head_addr; + }; + uint32_t reserved; + uint32_t buf2_addr; + uint32_t control; +}; + +struct nxp_enet_qos_rx_write_desc { + uint32_t vlan_tag; + uint32_t control1; + uint32_t control2; + uint32_t control3; +}; + +union nxp_enet_qos_rx_desc { + struct nxp_enet_qos_rx_read_desc read; + struct nxp_enet_qos_rx_write_desc write; +}; + +struct nxp_enet_qos_hw_info { + uint16_t max_frame_len; +}; + +struct nxp_enet_qos_mac_config { + const struct device *enet_dev; + const struct device *phy_dev; + enet_qos_t *base; + struct nxp_enet_qos_hw_info hw_info; + void (*irq_config_func)(void); + bool random_mac; +}; + +struct nxp_enet_qos_tx_data { + struct k_sem tx_sem; + struct net_pkt *pkt; + struct k_work tx_done_work; + struct net_buf *tx_header; + volatile union nxp_enet_qos_tx_desc descriptors[NUM_TX_BUFDESC]; +}; + +struct nxp_enet_qos_rx_data { + struct k_work rx_work; + volatile union nxp_enet_qos_rx_desc descriptors[NUM_RX_BUFDESC]; + struct net_buf *reserved_bufs[NUM_RX_BUFDESC]; +}; + +struct nxp_enet_qos_mac_data { + struct net_if *iface; + struct net_eth_addr mac_addr; + struct nxp_enet_qos_tx_data tx; + struct nxp_enet_qos_rx_data rx; +}; From 7079ea506a63225f900d25c66148ba3ca60b2e35 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Fri, 1 Mar 2024 14:35:08 -0600 Subject: [PATCH 1740/2402] dts: nxp_mcxn94x: Add ENET QOS Add ENET QOS nodes to MCX DTS Signed-off-by: Declan Snyder --- dts/arm/nxp/nxp_mcxn94x_common.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi index ba8de4d940c..3f84bde4f2b 100644 --- a/dts/arm/nxp/nxp_mcxn94x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi @@ -585,6 +585,24 @@ voltage-reference = <0>; #io-channel-cells = <1>; }; + + enet: ethernet@40100000 { + compatible = "nxp,enet-qos"; + reg = <0x40100000 0x1200>; + clocks = <&syscon MCUX_ENET_QOS_CLK>; + enet_mac: ethernet { + compatible = "nxp,enet-qos-mac"; + status = "disabled"; + interrupts = <139 0>, <140 0>, <141 0>; + interrupt-names = "mac", "power", "lpi"; + }; + enet_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,enet-qos-mdio"; + status = "disabled"; + }; + }; }; &systick { From 293cf9150c2e3d299a41379f2856d53feeabe2c4 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Fri, 1 Mar 2024 14:36:26 -0600 Subject: [PATCH 1741/2402] boards: frdm_mcxn947: Enable ENET QOS Enable ENET QOS on FRDM MCXN947 board Signed-off-by: Declan Snyder --- boards/nxp/frdm_mcxn947/Kconfig.defconfig | 9 ++++++++ boards/nxp/frdm_mcxn947/board.c | 9 ++++++++ boards/nxp/frdm_mcxn947/doc/index.rst | 2 ++ .../frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi | 22 +++++++++++++++++++ boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 19 ++++++++++++++++ .../frdm_mcxn947_mcxn947_cpu0.dts | 12 ++++++++++ 6 files changed, 73 insertions(+) create mode 100644 boards/nxp/frdm_mcxn947/Kconfig.defconfig diff --git a/boards/nxp/frdm_mcxn947/Kconfig.defconfig b/boards/nxp/frdm_mcxn947/Kconfig.defconfig new file mode 100644 index 00000000000..72cc76170b9 --- /dev/null +++ b/boards/nxp/frdm_mcxn947/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_MCXN947 + +config NET_L2_ETHERNET + default y if NETWORKING + +endif diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index 8016c4bc13a..5e798a39758 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -153,6 +153,15 @@ static int frdm_mcxn947_init(void) CLOCK_EnableClock(kCLOCK_Dac1); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) + CLOCK_AttachClk(kNONE_to_ENETRMII); + CLOCK_EnableClock(kCLOCK_Enet); + SYSCON0->PRESETCTRL2 = SYSCON_PRESETCTRL2_ENET_RST_MASK; + SYSCON0->PRESETCTRL2 &= ~SYSCON_PRESETCTRL2_ENET_RST_MASK; + /* rmii selection for this board */ + SYSCON->ENET_PHY_INTF_SEL = SYSCON_ENET_PHY_INTF_SEL_PHY_SEL(1); +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index 04acb21ec3a..ee65714f14e 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -74,6 +74,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | DAC | on-chip | dac | +-----------+------------+-------------------------------------+ +| ENET QOS | on-chip | ethernet | ++-----------+------------+-------------------------------------+ Targets available ================== diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi index c827d12a8ae..3bd948c668c 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi @@ -69,4 +69,26 @@ slew-rate = "fast"; }; }; + + pinmux_enet_qos: pinmux_enet_qos { + mdio_group { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + mac_group { + pinmux = , + , + , + , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; }; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index f14bd8bdb24..3b95bc74351 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -143,3 +143,22 @@ pinctrl-0 = <&pinmux_dac0>; pinctrl-names = "default"; }; + +&enet { + pinctrl-0 = <&pinmux_enet_qos>; + pinctrl-names = "default"; +}; + +&enet_mac { + phy-connection-type = "rmii"; + zephyr,random-mac-address; + phy-handle = <&phy>; +}; + +&enet_mdio { + phy: ethernet-phy@0 { + compatible = "ethernet-phy"; + reg = <0>; + status = "okay"; + }; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts index ff31063f694..ba08325ae0a 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts @@ -104,3 +104,15 @@ &dac0 { status = "okay"; }; + +&enet { + status = "okay"; +}; + +&enet_mac { + status = "okay"; +}; + +&enet_mdio { + status = "okay"; +}; From 36e2b40e388598b7f927b877b044ca5274b4b19f Mon Sep 17 00:00:00 2001 From: Erik Andersson Date: Sat, 16 Mar 2024 07:35:03 +0100 Subject: [PATCH 1742/2402] drivers: dsi: stm32: add additional dt options To support the NT35510 display, some additional options needs to be configurable in the STM32 DSI peripheral Signed-off-by: Erik Andersson --- drivers/mipi_dsi/dsi_stm32.c | 13 +++++++------ dts/bindings/mipi-dsi/st,stm32-mipi-dsi.yaml | 17 +++++++++++++++++ 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/mipi_dsi/dsi_stm32.c b/drivers/mipi_dsi/dsi_stm32.c index cb8a0177003..827d7f9e33f 100644 --- a/drivers/mipi_dsi/dsi_stm32.c +++ b/drivers/mipi_dsi/dsi_stm32.c @@ -245,7 +245,6 @@ static int mipi_dsi_stm32_attach(const struct device *dev, uint8_t channel, vcfg->VirtualChannelID = channel; vcfg->ColorCoding = STM32_DSI_INIT_PIXEL_FORMAT; - vcfg->LooselyPacked = DSI_LOOSELY_PACKED_DISABLE; if (mdev->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { vcfg->Mode = DSI_VID_MODE_BURST; @@ -277,16 +276,12 @@ static int mipi_dsi_stm32_attach(const struct device *dev, uint8_t channel, vcfg->LPCommandEnable = DSI_LP_COMMAND_DISABLE; } - vcfg->LPLargestPacketSize = 4; - vcfg->LPVACTLargestPacketSize = 4; - vcfg->LPHorizontalFrontPorchEnable = DSI_LP_HFP_ENABLE; vcfg->LPHorizontalBackPorchEnable = DSI_LP_HBP_ENABLE; vcfg->LPVerticalActiveEnable = DSI_LP_VACT_ENABLE; vcfg->LPVerticalFrontPorchEnable = DSI_LP_VFP_ENABLE; vcfg->LPVerticalBackPorchEnable = DSI_LP_VBP_ENABLE; vcfg->LPVerticalSyncActiveEnable = DSI_LP_VSYNC_ENABLE; - vcfg->FrameBTAAcknowledgeEnable = DSI_FBTAA_ENABLE; ret = HAL_DSI_ConfigVideoMode(&data->hdsi, vcfg); if (ret != HAL_OK) { @@ -496,7 +491,13 @@ static int mipi_dsi_stm32_init(const struct device *dev) .VSPolarity = DT_INST_PROP(inst, vs_active_high) ? \ DSI_VSYNC_ACTIVE_HIGH : DSI_VSYNC_ACTIVE_LOW, \ .DEPolarity = DT_INST_PROP(inst, de_active_high) ? \ - DSI_DATA_ENABLE_ACTIVE_HIGH : DSI_DATA_ENABLE_ACTIVE_LOW, \ + DSI_DATA_ENABLE_ACTIVE_HIGH : DSI_DATA_ENABLE_ACTIVE_LOW, \ + .LooselyPacked = DT_INST_PROP(inst, loosely_packed) ? \ + DSI_LOOSELY_PACKED_ENABLE : DSI_LOOSELY_PACKED_DISABLE, \ + .LPLargestPacketSize = DT_INST_PROP_OR(inst, largest_packet_size, 4), \ + .LPVACTLargestPacketSize = DT_INST_PROP_OR(inst, largest_packet_size, 4), \ + .FrameBTAAcknowledgeEnable = DT_INST_PROP(inst, bta_ack_disable) ? \ + DSI_FBTAA_DISABLE : DSI_FBTAA_ENABLE, \ }, \ .pll_init = { \ .PLLNDIV = DT_INST_PROP(inst, pll_ndiv), \ diff --git a/dts/bindings/mipi-dsi/st,stm32-mipi-dsi.yaml b/dts/bindings/mipi-dsi/st,stm32-mipi-dsi.yaml index 7ddfa40b120..3dc064842d0 100644 --- a/dts/bindings/mipi-dsi/st,stm32-mipi-dsi.yaml +++ b/dts/bindings/mipi-dsi/st,stm32-mipi-dsi.yaml @@ -40,6 +40,23 @@ properties: description: | DSI host data enable is active high. + loosely-packed: + type: boolean + description: | + Enable or disable loosely packed stream + (needed only when using 18-bit configuration). + + largest-packet-size: + type: int + description: | + The size, in bytes, of the low power largest packet that + can fit in a line during VSA, VBP, VFP and VACT regions + + bta-ack-disable: + type: boolean + description: | + Disable frame bus-turn-around acknowledge enable + non-continuous: type: boolean description: | From 72503ab3868d18fb20ceb60a6db32eed4989fa15 Mon Sep 17 00:00:00 2001 From: Erik Andersson Date: Sat, 16 Mar 2024 11:59:18 +0100 Subject: [PATCH 1743/2402] drivers: display: add driver for frida,nt35510 For now DSI settings are hard-coded for the specific LCD module used on the STM32H747I Discovery board Signed-off-by: Erik Andersson --- drivers/display/CMakeLists.txt | 1 + drivers/display/Kconfig | 1 + drivers/display/Kconfig.nt35510 | 20 ++ drivers/display/display_nt35510.c | 439 ++++++++++++++++++++++++ drivers/display/display_nt35510.h | 100 ++++++ dts/bindings/display/frida,nt35510.yaml | 33 ++ 6 files changed, 594 insertions(+) create mode 100644 drivers/display/Kconfig.nt35510 create mode 100644 drivers/display/display_nt35510.c create mode 100644 drivers/display/display_nt35510.h create mode 100644 dts/bindings/display/frida,nt35510.yaml diff --git a/drivers/display/CMakeLists.txt b/drivers/display/CMakeLists.txt index f6138ff99f2..b9b866ccff4 100644 --- a/drivers/display/CMakeLists.txt +++ b/drivers/display/CMakeLists.txt @@ -26,6 +26,7 @@ zephyr_library_sources_ifdef(CONFIG_HX8394 display_hx8394.c) zephyr_library_sources_ifdef(CONFIG_GC9X01X display_gc9x01x.c) zephyr_library_sources_ifdef(CONFIG_LED_STRIP_MATRIX display_led_strip_matrix.c) zephyr_library_sources_ifdef(CONFIG_DISPLAY_RENESAS_LCDC display_renesas_lcdc.c) +zephyr_library_sources_ifdef(CONFIG_NT35510 display_nt35510.c) zephyr_library_sources_ifdef(CONFIG_MICROBIT_DISPLAY mb_display.c diff --git a/drivers/display/Kconfig b/drivers/display/Kconfig index 6a355da7aeb..3270faf028d 100644 --- a/drivers/display/Kconfig +++ b/drivers/display/Kconfig @@ -43,5 +43,6 @@ source "drivers/display/Kconfig.hx8394" source "drivers/display/Kconfig.gc9x01x" source "drivers/display/Kconfig.led_strip_matrix" source "drivers/display/Kconfig.renesas_lcdc" +source "drivers/display/Kconfig.nt35510" endif # DISPLAY diff --git a/drivers/display/Kconfig.nt35510 b/drivers/display/Kconfig.nt35510 new file mode 100644 index 00000000000..d34e4a1e081 --- /dev/null +++ b/drivers/display/Kconfig.nt35510 @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Erik Andersson +# SPDX-License-Identifier: Apache-2.0 + +config NT35510 + bool "NT35510 display driver" + default y + depends on DT_HAS_FRIDA_NT35510_ENABLED + select MIPI_DSI + help + Enable driver for NT35510 display driver. + +if NT35510 + +config DISPLAY_NT35510_INIT_PRIORITY + int "Initialization priority" + default DISPLAY_INIT_PRIORITY + help + NT35510 display driver initialization priority. + +endif diff --git a/drivers/display/display_nt35510.c b/drivers/display/display_nt35510.c new file mode 100644 index 00000000000..6d0bb85fecb --- /dev/null +++ b/drivers/display/display_nt35510.c @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2024 Erik Andersson + * + * SPDX-License-Identifier: Apache-2.0 + * + * Based on the NT35510 driver provided by STMicroelectronics at + * https://github.com/STMicroelectronics/stm32-nt35510/blob/main/nt35510.c + */ + +#define DT_DRV_COMPAT frida_nt35510 + +#include +#include +#include +#include +#include +#include +#include +#include +#include "display_nt35510.h" + +LOG_MODULE_REGISTER(nt35510, CONFIG_DISPLAY_LOG_LEVEL); + +/** + * @brief Possible values of COLMOD parameter corresponding to used pixel formats + */ +#define NT35510_COLMOD_RGB565 0x55 +#define NT35510_COLMOD_RGB888 0x77 + +/** + * @brief NT35510_480X800 Timing parameters for Portrait orientation mode + */ +#define NT35510_480X800_HSYNC ((uint16_t)2) /* Horizontal synchronization */ +#define NT35510_480X800_HBP ((uint16_t)34) /* Horizontal back porch */ +#define NT35510_480X800_HFP ((uint16_t)34) /* Horizontal front porch */ + +#define NT35510_480X800_VSYNC ((uint16_t)120) /* Vertical synchronization */ +#define NT35510_480X800_VBP ((uint16_t)150) /* Vertical back porch */ +#define NT35510_480X800_VFP ((uint16_t)150) /* Vertical front porch */ + +/** + * @brief NT35510_800X480 Timing parameters for Landscape orientation mode + * Same values as for Portrait mode in fact. + */ +#define NT35510_800X480_HSYNC NT35510_480X800_VSYNC /* Horizontal synchronization */ +#define NT35510_800X480_HBP NT35510_480X800_VBP /* Horizontal back porch */ +#define NT35510_800X480_HFP NT35510_480X800_VFP /* Horizontal front porch */ +#define NT35510_800X480_VSYNC NT35510_480X800_HSYNC /* Vertical synchronization */ +#define NT35510_800X480_VBP NT35510_480X800_HBP /* Vertical back porch */ +#define NT35510_800X480_VFP NT35510_480X800_HFP /* Vertical front porch */ + +struct nt35510_config { + const struct device *mipi_dsi; + const struct gpio_dt_spec reset; + const struct gpio_dt_spec backlight; + uint8_t data_lanes; + uint16_t width; + uint16_t height; + uint8_t channel; + uint16_t rotation; +}; + +struct nt35510_data { + enum display_pixel_format pixel_format; + enum display_orientation orientation; + uint16_t xres; + uint16_t yres; +}; + +struct nt35510_init_cmd { + uint8_t reg; + uint8_t cmd_len; + uint8_t cmd[5]; +} __packed; + +static const struct nt35510_init_cmd init_cmds[] = { + /* LV2: Page 1 enable */ + {.reg = 0xf0, .cmd_len = 5, .cmd = {0x55, 0xaa, 0x52, 0x08, 0x01}}, + /* AVDD: 5.2V */ + {.reg = 0xb0, .cmd_len = 3, .cmd = {0x03, 0x03, 0x03}}, + /* AVDD: Ratio */ + {.reg = 0xb6, .cmd_len = 3, .cmd = {0x46, 0x46, 0x46}}, + /* AVEE: -5.2V */ + {.reg = 0xb1, .cmd_len = 3, .cmd = {0x03, 0x03, 0x03}}, + /* AVEE: Ratio */ + {.reg = 0xb7, .cmd_len = 3, .cmd = {0x36, 0x36, 0x36}}, + /* VCL: -2.5V */ + {.reg = 0xb2, .cmd_len = 3, .cmd = {0x00, 0x00, 0x02}}, + /* VCL: Ratio */ + {.reg = 0xb8, .cmd_len = 3, .cmd = {0x26, 0x26, 0x26}}, + /* VGH: 15V (Free Pump) */ + {.reg = 0xbf, .cmd_len = 1, .cmd = {0x01}}, + /* Frida LCD MFR specific */ + {.reg = 0xb3, .cmd_len = 3, .cmd = {0x09, 0x09, 0x09}}, + /* VGH: Ratio */ + {.reg = 0xb9, .cmd_len = 3, .cmd = {0x36, 0x36, 0x36}}, + /* VGL_REG: -10V */ + {.reg = 0xb5, .cmd_len = 3, .cmd = {0x08, 0x08, 0x08}}, + /* VGLX: Ratio */ + {.reg = 0xba, .cmd_len = 3, .cmd = {0x26, 0x26, 0x26}}, + /* VGMP/VGSP: 4.5V/0V */ + {.reg = 0xbc, .cmd_len = 3, .cmd = {0x00, 0x80, 0x00}}, + /* VGMN/VGSN:-4.5V/0V */ + {.reg = 0xbd, .cmd_len = 3, .cmd = {0x00, 0x80, 0x00}}, + /* VCOM: -1.325V */ + {.reg = 0xbe, .cmd_len = 2, .cmd = {0x00, 0x50}}, + + /* LV2: Page 0 enable */ + {.reg = 0xf0, .cmd_len = 5, .cmd = {0x55, 0xaa, 0x52, 0x08, 0x00}}, + /* Display optional control */ + {.reg = 0xb1, .cmd_len = 2, .cmd = {0xfc, 0x00}}, + /* Set source output data hold time */ + {.reg = 0xb6, .cmd_len = 1, .cmd = {0x03}}, + /* Display resolution control */ + {.reg = 0xb5, .cmd_len = 1, .cmd = {0x51}}, + /* Gate EQ control */ + {.reg = 0xb7, .cmd_len = 2, .cmd = {0x00, 0x00}}, + /* Src EQ control(Mode2) */ + {.reg = 0xb8, .cmd_len = 4, .cmd = {0x01, 0x02, 0x02, 0x02}}, + /* Frida LCD MFR specific */ + {.reg = 0xbc, .cmd_len = 3, .cmd = {0x00, 0x00, 0x00}}, + /* Frida LCD MFR specific */ + {.reg = 0xcc, .cmd_len = 3, .cmd = {0x03, 0x00, 0x00}}, + /* Frida LCD MFR specific */ + {.reg = 0xba, .cmd_len = 1, .cmd = {0x01}}}; + +static const struct nt35510_init_cmd portrait_cmds[] = { + {.reg = NT35510_CMD_MADCTL, .cmd_len = 1, .cmd = {0x00}}, + {.reg = NT35510_CMD_CASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x01, 0xdf}}, + {.reg = NT35510_CMD_RASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x03, 0x1f}}}; + +static const struct nt35510_init_cmd landscape_cmds[] = { + {.reg = NT35510_CMD_MADCTL, .cmd_len = 1, .cmd = {0x60}}, + {.reg = NT35510_CMD_CASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x03, 0x1f}}, + {.reg = NT35510_CMD_RASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x01, 0xdf}}}; + +static const struct nt35510_init_cmd turn_on_cmds[] = { + /* Content Adaptive Backlight Control section start */ + {.reg = NT35510_CMD_WRDISBV, .cmd_len = 1, .cmd = {0x7f}}, + /* Brightness Control Block, Display Dimming & BackLight on */ + {.reg = NT35510_CMD_WRCTRLD, .cmd_len = 1, .cmd = {0x2c}}, + /* Image Content based Adaptive Brightness [Still Picture] */ + {.reg = NT35510_CMD_WRCABC, .cmd_len = 1, .cmd = {0x02}}, + /* Brightness, use maximum as default */ + {.reg = NT35510_CMD_WRCABCMB, .cmd_len = 1, .cmd = {0xff}}, + /* Turn on display */ + {.reg = MIPI_DCS_SET_DISPLAY_ON, .cmd_len = 0, .cmd = {}}, + /* Send Command GRAM memory write (no parameters) + * this initiates frame write via other DSI commands sent by + * DSI host from LTDC incoming pixels in video mode + */ + {.reg = NT35510_CMD_RAMWR, .cmd_len = 0, .cmd = {}}, +}; + +/* Write data buffer to LCD register */ +static int nt35510_write_reg(const struct device *dev, uint8_t reg, const uint8_t *buf, size_t len) +{ + int ret; + const struct nt35510_config *cfg = dev->config; + + ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, reg, buf, len); + if (ret < 0) { + LOG_ERR("Failed writing reg: 0x%x result: (%d)", reg, ret); + return ret; + } + return 0; +} + +/* Write an 8-bit value to a register */ +static int nt35510_write_reg_val(const struct device *dev, uint8_t reg, uint8_t value) +{ + return nt35510_write_reg(dev, reg, &value, 1); +} + +/* Write a list of commands to registers */ +static int nt35510_write_sequence(const struct device *dev, const struct nt35510_init_cmd *cmd, + uint8_t nr_cmds) +{ + int ret = 0; + + /* Loop trough all commands as long as writes are successful*/ + for (int i = 0; i < nr_cmds && ret == 0; i++) { + ret = nt35510_write_reg(dev, cmd->reg, cmd->cmd, cmd->cmd_len); + cmd++; + } + return ret; +} + +/* Initialization, configuration turn on sequence */ +static int nt35510_config(const struct device *dev) +{ + struct nt35510_data *data = dev->data; + int ret; + + ret = nt35510_write_sequence(dev, init_cmds, ARRAY_SIZE(init_cmds)); + if (ret < 0) { + return ret; + } + /* Add a delay, otherwise MADCTL not taken */ + k_msleep(200); + + /* Configure orientation */ + if (data->orientation == DISPLAY_ORIENTATION_NORMAL) { + ret = nt35510_write_sequence(dev, portrait_cmds, ARRAY_SIZE(portrait_cmds)); + } else { + ret = nt35510_write_sequence(dev, landscape_cmds, ARRAY_SIZE(landscape_cmds)); + } + if (ret < 0) { + return ret; + } + /* Exit sleep mode */ + ret = nt35510_write_reg(dev, NT35510_CMD_SLPOUT, NULL, 0); + if (ret < 0) { + return ret; + } + + /* Wait for sleep out exit */ + k_msleep(20); + + /* Set color mode */ + ret = nt35510_write_reg_val(dev, NT35510_CMD_COLMOD, + data->pixel_format == PIXEL_FORMAT_RGB_565 + ? NT35510_COLMOD_RGB565 + : NT35510_COLMOD_RGB888); + if (ret < 0) { + return ret; + } + + /* Adjust brightness and turn on display */ + ret = nt35510_write_sequence(dev, turn_on_cmds, ARRAY_SIZE(turn_on_cmds)); + return ret; +} + +static int nt35510_blanking_on(const struct device *dev) +{ + const struct nt35510_config *cfg = dev->config; + int ret; + + if (cfg->backlight.port != NULL) { + ret = gpio_pin_set_dt(&cfg->backlight, 0); + if (ret) { + LOG_ERR("Disable backlight failed! (%d)", ret); + return ret; + } + } + return nt35510_write_reg(dev, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0); +} + +static int nt35510_blanking_off(const struct device *dev) +{ + const struct nt35510_config *cfg = dev->config; + int ret; + + if (cfg->backlight.port != NULL) { + ret = gpio_pin_set_dt(&cfg->backlight, 1); + if (ret) { + LOG_ERR("Enable backlight failed! (%d)", ret); + return ret; + } + } + return nt35510_write_reg(dev, MIPI_DCS_SET_DISPLAY_ON, NULL, 0); +} + +static int nt35510_set_brightness(const struct device *dev, const uint8_t brightness) +{ + return nt35510_write_reg(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, &brightness, 1); +} + +static void nt35510_get_capabilities(const struct device *dev, + struct display_capabilities *capabilities) +{ + const struct nt35510_config *cfg = dev->config; + struct nt35510_data *data = dev->data; + + memset(capabilities, 0, sizeof(struct display_capabilities)); + capabilities->x_resolution = cfg->width; + capabilities->y_resolution = cfg->height; + capabilities->supported_pixel_formats = PIXEL_FORMAT_RGB_565 | PIXEL_FORMAT_RGB_888; + capabilities->current_pixel_format = data->pixel_format; + capabilities->current_orientation = data->orientation; +} + +static int nt35510_set_pixel_format(const struct device *dev, + const enum display_pixel_format pixel_format) +{ + struct nt35510_data *data = dev->data; + + if (pixel_format == PIXEL_FORMAT_RGB_565 || pixel_format == PIXEL_FORMAT_RGB_888) { + data->pixel_format = pixel_format; + return 0; + } + LOG_ERR("Pixel format not supported"); + return -ENOTSUP; +} + +static int nt35510_check_id(const struct device *dev) +{ + const struct nt35510_config *cfg = dev->config; + uint8_t id = 0; + int ret; + + ret = mipi_dsi_dcs_read(cfg->mipi_dsi, cfg->channel, NT35510_CMD_RDID2, &id, 1); + if (ret != sizeof(id)) { + LOG_ERR("Failed reading ID (%d)", ret); + return -EIO; + } + + if (id != NT35510_ID) { + LOG_ERR("ID 0x%x, expected: 0x%x)", id, NT35510_ID); + return -EINVAL; + } + return 0; +} + +static int nt35510_init(const struct device *dev) +{ + const struct nt35510_config *cfg = dev->config; + struct nt35510_data *data = dev->data; + struct mipi_dsi_device mdev; + int ret; + + if (cfg->reset.port) { + if (!gpio_is_ready_dt(&cfg->reset)) { + LOG_ERR("Reset GPIO device is not ready!"); + return -ENODEV; + } + ret = gpio_pin_configure_dt(&cfg->reset, GPIO_OUTPUT_INACTIVE); + if (ret < 0) { + LOG_ERR("Reset display failed! (%d)", ret); + return ret; + } + k_msleep(20); + ret = gpio_pin_set_dt(&cfg->reset, 1); + if (ret < 0) { + LOG_ERR("Enable display failed! (%d)", ret); + return ret; + } + k_msleep(200); + } + + /* Store x/y resolution & rotation */ + if (cfg->rotation == 0) { + data->xres = cfg->width; + data->yres = cfg->height; + data->orientation = DISPLAY_ORIENTATION_NORMAL; + } else if (cfg->rotation == 90) { + data->xres = cfg->height; + data->yres = cfg->width; + data->orientation = DISPLAY_ORIENTATION_ROTATED_90; + } else if (cfg->rotation == 180) { + data->xres = cfg->width; + data->yres = cfg->height; + data->orientation = DISPLAY_ORIENTATION_ROTATED_180; + } else if (cfg->rotation == 270) { + data->xres = cfg->height; + data->yres = cfg->width; + data->orientation = DISPLAY_ORIENTATION_ROTATED_270; + } + + /* Attach to MIPI-DSI host */ + mdev.data_lanes = cfg->data_lanes; + mdev.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM; + + if (data->pixel_format == PIXEL_FORMAT_RGB_565) { + mdev.pixfmt = MIPI_DSI_PIXFMT_RGB565; + } else { + mdev.pixfmt = MIPI_DSI_PIXFMT_RGB888; + } + + mdev.timings.hactive = data->xres; + mdev.timings.hbp = NT35510_480X800_HBP; + mdev.timings.hfp = NT35510_480X800_HFP; + mdev.timings.hsync = NT35510_480X800_HSYNC; + mdev.timings.vactive = data->yres; + mdev.timings.vbp = NT35510_480X800_VBP; + mdev.timings.vfp = NT35510_480X800_VFP; + mdev.timings.vsync = NT35510_480X800_VSYNC; + + ret = mipi_dsi_attach(cfg->mipi_dsi, cfg->channel, &mdev); + if (ret < 0) { + LOG_ERR("MIPI-DSI attach failed! (%d)", ret); + return ret; + } + + ret = nt35510_check_id(dev); + if (ret) { + LOG_ERR("Panel ID check failed! (%d)", ret); + return ret; + } + + ret = gpio_pin_configure_dt(&cfg->backlight, GPIO_OUTPUT_ACTIVE); + if (ret < 0) { + LOG_ERR("Backlight pin init fail (%d)", ret); + return ret; + } + + ret = nt35510_config(dev); + if (ret) { + LOG_ERR("DSI init sequence failed! (%d)", ret); + return ret; + } + + ret = nt35510_blanking_off(dev); + if (ret) { + LOG_ERR("Display blanking off failed! (%d)", ret); + return ret; + } + + LOG_INF("Init complete(%d)", ret); + return 0; +} + +static const struct display_driver_api nt35510_api = { + .blanking_on = nt35510_blanking_on, + .blanking_off = nt35510_blanking_off, + .set_brightness = nt35510_set_brightness, + .get_capabilities = nt35510_get_capabilities, + .set_pixel_format = nt35510_set_pixel_format, +}; + +#define NT35510_DEFINE(n) \ + static const struct nt35510_config nt35510_config_##n = { \ + .mipi_dsi = DEVICE_DT_GET(DT_INST_BUS(n)), \ + .reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}), \ + .backlight = GPIO_DT_SPEC_INST_GET_OR(n, bl_gpios, {0}), \ + .data_lanes = DT_INST_PROP_BY_IDX(n, data_lanes, 0), \ + .width = DT_INST_PROP(n, width), \ + .height = DT_INST_PROP(n, height), \ + .channel = DT_INST_REG_ADDR(n), \ + .rotation = DT_INST_PROP(n, rotation), \ + }; \ + \ + static struct nt35510_data nt35510_data_##n = { \ + .pixel_format = DT_INST_PROP(n, pixel_format), \ + }; \ + DEVICE_DT_INST_DEFINE(n, &nt35510_init, NULL, &nt35510_data_##n, &nt35510_config_##n, \ + POST_KERNEL, CONFIG_DISPLAY_NT35510_INIT_PRIORITY, &nt35510_api); + +DT_INST_FOREACH_STATUS_OKAY(NT35510_DEFINE) diff --git a/drivers/display/display_nt35510.h b/drivers/display/display_nt35510.h new file mode 100644 index 00000000000..134c43079f3 --- /dev/null +++ b/drivers/display/display_nt35510.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2024 Erik Andersson + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_NT35510_H_ +#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_NT35510_H_ + +/** + * @name Controller registers + * @{ + */ + +/* NT35510 ID */ +#define NT35510_ID 0x80U + +#define NT35510_CMD_NOP 0x00 /* NOP */ +#define NT35510_CMD_SWRESET 0x01 /* SW reset */ +#define NT35510_CMD_RDDID 0x04 /* Read display ID */ +#define NT35510_CMD_RDNUMED 0x05 /* Read number of errors on DSI */ +#define NT35510_CMD_RDDPM 0x0A /* Read display power mode */ +#define NT35510_CMD_RDDMADCTL 0x0B /* Read display MADCTL */ +#define NT35510_CMD_RDDCOLMOD 0x0C /* Read display pixel format */ +#define NT35510_CMD_RDDIM 0x0D /* Read display image mode */ +#define NT35510_CMD_RDDSM 0x0E /* Read display signal mode */ +#define NT35510_CMD_RDDSDR 0x0F /* Read display self-diagnostics result */ +#define NT35510_CMD_SLPIN 0x10 /* Sleep in */ +#define NT35510_CMD_SLPOUT 0x11 /* Sleep out */ +#define NT35510_CMD_PTLON 0x12 /* Partial mode on */ +#define NT35510_CMD_NORON 0x13 /* Normal display mode on */ +#define NT35510_CMD_INVOFF 0x20 /* Display inversion off */ +#define NT35510_CMD_INVON 0x21 /* Display inversion on */ +#define NT35510_CMD_ALLPOFF 0x22 /* All pixel off */ +#define NT35510_CMD_ALLPON 0x23 /* All pixel on */ +#define NT35510_CMD_GAMSET 0x26 /* Gamma set */ +#define NT35510_CMD_DISPOFF 0x28 /* Display off */ +#define NT35510_CMD_DISPON 0x29 /* Display on */ +#define NT35510_CMD_CASET 0x2A /* Column address set */ +#define NT35510_CMD_RASET 0x2B /* Row address set */ +#define NT35510_CMD_RAMWR 0x2C /* Memory write */ +#define NT35510_CMD_RAMRD 0x2E /* Memory read */ +#define NT35510_CMD_PLTAR 0x30 /* Partial area */ +#define NT35510_CMD_TOPC 0x32 /* Turn On Peripheral Command */ +#define NT35510_CMD_TEOFF 0x34 /* Tearing effect line off */ +#define NT35510_CMD_TEEON 0x35 /* Tearing effect line on */ +#define NT35510_CMD_MADCTL 0x36 /* Memory data access control */ +#define NT35510_CMD_IDMOFF 0x38 /* Idle mode off */ +#define NT35510_CMD_IDMON 0x39 /* Idle mode on */ +#define NT35510_CMD_COLMOD 0x3A /* Interface pixel format */ +#define NT35510_CMD_RAMWRC 0x3C /* Memory write continue */ +#define NT35510_CMD_RAMRDC 0x3E /* Memory read continue */ +#define NT35510_CMD_STESL 0x44 /* Set tearing effect scan line */ +#define NT35510_CMD_GSL 0x45 /* Get scan line */ + +#define NT35510_CMD_DSTBON 0x4F /* Deep standby mode on */ +#define NT35510_CMD_WRPFD 0x50 /* Write profile value for display */ +#define NT35510_CMD_WRDISBV 0x51 /* Write display brightness */ +#define NT35510_CMD_RDDISBV 0x52 /* Read display brightness */ +#define NT35510_CMD_WRCTRLD 0x53 /* Write CTRL display */ +#define NT35510_CMD_RDCTRLD 0x54 /* Read CTRL display value */ +#define NT35510_CMD_WRCABC 0x55 /* Write content adaptative brightness control */ +#define NT35510_CMD_RDCABC 0x56 /* Read content adaptive brightness control */ +#define NT35510_CMD_WRHYSTE 0x57 /* Write hysteresis */ +#define NT35510_CMD_WRGAMMSET 0x58 /* Write gamme setting */ +#define NT35510_CMD_RDFSVM 0x5A /* Read FS value MSBs */ +#define NT35510_CMD_RDFSVL 0x5B /* Read FS value LSBs */ +#define NT35510_CMD_RDMFFSVM 0x5C /* Read median filter FS value MSBs */ +#define NT35510_CMD_RDMFFSVL 0x5D /* Read median filter FS value LSBs */ +#define NT35510_CMD_WRCABCMB 0x5E /* Write CABC minimum brightness */ +#define NT35510_CMD_RDCABCMB 0x5F /* Read CABC minimum brightness */ +#define NT35510_CMD_WRLSCC 0x65 /* Write light sensor compensation coefficient value */ +#define NT35510_CMD_RDLSCCM 0x66 /* Read light sensor compensation coefficient value MSBs */ +#define NT35510_CMD_RDLSCCL 0x67 /* Read light sensor compensation coefficient value LSBs */ +#define NT35510_CMD_RDBWLB 0x70 /* Read black/white low bits */ +#define NT35510_CMD_RDBKX 0x71 /* Read Bkx */ +#define NT35510_CMD_RDBKY 0x72 /* Read Bky */ +#define NT35510_CMD_RDWX 0x73 /* Read Wx */ +#define NT35510_CMD_RDWY 0x74 /* Read Wy */ +#define NT35510_CMD_RDRGLB 0x75 /* Read red/green low bits */ +#define NT35510_CMD_RDRX 0x76 /* Read Rx */ +#define NT35510_CMD_RDRY 0x77 /* Read Ry */ +#define NT35510_CMD_RDGX 0x78 /* Read Gx */ +#define NT35510_CMD_RDGY 0x79 /* Read Gy */ +#define NT35510_CMD_RDBALB 0x7A /* Read blue/acolor low bits */ +#define NT35510_CMD_RDBX 0x7B /* Read Bx */ +#define NT35510_CMD_RDBY 0x7C /* Read By */ +#define NT35510_CMD_RDAX 0x7D /* Read Ax */ +#define NT35510_CMD_RDAY 0x7E /* Read Ay */ +#define NT35510_CMD_RDDDBS 0xA1 /* Read DDB start */ +#define NT35510_CMD_RDDDBC 0xA8 /* Read DDB continue */ +#define NT35510_CMD_RDDCS 0xAA /* Read first checksum */ +#define NT35510_CMD_RDCCS 0xAF /* Read continue checksum */ +#define NT35510_CMD_RDID1 0xDA /* Read ID1 value */ +#define NT35510_CMD_RDID2 0xDB /* Read ID2 value */ +#define NT35510_CMD_RDID3 0xDC /* Read ID3 value */ + +/** @} */ + +#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_NT35510_H_ */ diff --git a/dts/bindings/display/frida,nt35510.yaml b/dts/bindings/display/frida,nt35510.yaml new file mode 100644 index 00000000000..0ae39ae4535 --- /dev/null +++ b/dts/bindings/display/frida,nt35510.yaml @@ -0,0 +1,33 @@ +# Copyright (c) 2024 Erik Andersson +# SPDX-License-Identifier: Apache-2.0 + +description: Frida Techshine Panel + +compatible: "frida,nt35510" + +include: [mipi-dsi-device.yaml, display-controller.yaml] + +properties: + reset-gpios: + type: phandle-array + description: | + Hardware based reset gpio pin + Setting a low level will hold NT35510 in reset + + bl-gpios: + type: phandle-array + description: | + The BLn pin is asserted to turn on the backlight of the panel. + Note that some boards may use software control instead + and don't have this pin connected + + rotation: + type: int + default: 0 + enum: + - 0 + - 90 + - 180 + - 270 + description: | + Display rotation clockwise in degrees. Defaults to 0, display default. From 8dd3aff158c97c91ff69973538ccb2ad4446a7be Mon Sep 17 00:00:00 2001 From: Erik Andersson Date: Sun, 17 Mar 2024 21:07:53 +0100 Subject: [PATCH 1744/2402] board: shield: st_b_lcd40_dsi1_mb1166 A09 support Add support for the A09 version of MB1166 which have a NT35510 panel controller instead of an OTM8009a as in prior versions Fixes #60888 Signed-off-by: Erik Andersson --- .../st_b_lcd40_dsi1_mb1166/Kconfig.defconfig | 5 ++-- .../st_b_lcd40_dsi1_mb1166/Kconfig.shield | 5 ++++ .../stm32h747i_disco_stm32h747xx_m7.conf | 6 ++++ .../stm32h747i_disco_stm32h747xx_m7.overlay | 21 +++++++++++++ .../stm32h747i_disco_stm32h747xx_m7.conf | 5 ++++ .../stm32h747i_disco_stm32h747xx_m7.overlay | 30 +++++++++++++++++++ .../stm32h747i_disco_stm32h747xx_m7.conf | 2 -- .../stm32h747i_disco_stm32h747xx_m7.overlay | 22 -------------- .../st_b_lcd40_dsi1_mb1166/doc/index.rst | 10 +++++-- .../st_b_lcd40_dsi1_mb1166.overlay | 3 ++ .../st_b_lcd40_dsi1_mb1166_a09.overlay | 20 +++++++++++++ 11 files changed, 100 insertions(+), 29 deletions(-) create mode 100644 boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h747i_disco_stm32h747xx_m7.conf create mode 100644 boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h747i_disco_stm32h747xx_m7.overlay create mode 100644 boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.conf create mode 100644 boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.overlay create mode 100644 boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.defconfig b/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.defconfig index b192ce223f0..2fe69bcea06 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.defconfig +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.defconfig @@ -1,7 +1,8 @@ # Copyright (c) 2023 BrainCo Inc. +# Copyright (c) 2024 Erik Andersson # SPDX-License-Identifier: Apache-2.0 -if SHIELD_ST_B_LCD40_DSI1_MB1166 +if SHIELD_ST_B_LCD40_DSI1_MB1166 || SHIELD_ST_B_LCD40_DSI1_MB1166_A09 # Double frame buffer maintained by lvgl. if LVGL @@ -39,4 +40,4 @@ endchoice endif # LVGL -endif # SHIELD_ST_B_LCD40_DSI1_MB1166 +endif # SHIELD_ST_B_LCD40_DSI1_MB1166 || SHIELD_ST_B_LCD40_DSI1_MB1166_A09 diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.shield b/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.shield index c46fa19b33c..4cf58d14923 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.shield +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.shield @@ -1,5 +1,10 @@ # Copyright (c) 2023 bytes at work AG +# Copyright (c) 2024 Erik Andersson + # SPDX-License-Identifier: Apache-2.0 config SHIELD_ST_B_LCD40_DSI1_MB1166 def_bool $(shields_list_contains,st_b_lcd40_dsi1_mb1166) + +config SHIELD_ST_B_LCD40_DSI1_MB1166_A09 + def_bool $(shields_list_contains,st_b_lcd40_dsi1_mb1166_a09) diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h747i_disco_stm32h747xx_m7.conf b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h747i_disco_stm32h747xx_m7.conf new file mode 100644 index 00000000000..b8b9c9b7ee3 --- /dev/null +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h747i_disco_stm32h747xx_m7.conf @@ -0,0 +1,6 @@ +# Copyright (c) 2023 bytes at work AG +# Copyright (c) 2024 Erik Andersson +# SPDX-License-Identifier: Apache-2.0 + +# Initialize after LTDC and MIPI-DSI +CONFIG_DISPLAY_OTM8009A_INIT_PRIORITY=87 diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h747i_disco_stm32h747xx_m7.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h747i_disco_stm32h747xx_m7.overlay new file mode 100644 index 00000000000..554e9777f1c --- /dev/null +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h747i_disco_stm32h747xx_m7.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2023 bytes at work AG + * + * SPDX-License-Identifier: Apache-2.0 + */ +<dc { + /* orisetech, otm8009a */ + display-timings { + compatible = "zephyr,panel-timing"; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + hsync-len = <2>; + vsync-len = <1>; + hback-porch = <34>; + vback-porch = <15>; + hfront-porch = <34>; + vfront-porch = <16>; + }; +}; diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.conf b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.conf new file mode 100644 index 00000000000..8a9071c9579 --- /dev/null +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.conf @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Erik Andersson +# SPDX-License-Identifier: Apache-2.0 + +# Initialize after LTDC and MIPI-DSI +CONFIG_DISPLAY_NT35510_INIT_PRIORITY=87 diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.overlay new file mode 100644 index 00000000000..90ddb549d7a --- /dev/null +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.overlay @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 Erik Andersson + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&mipi_dsi { + loosely-packed; + largest-packet-size = <64>; + bta-ack-disable; +}; + +<dc { + /* frida, nt35510 */ + display-timings { + compatible = "zephyr,panel-timing"; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + hsync-len = <2>; + vsync-len = <120>; + hback-porch = <34>; + vback-porch = <150>; + hfront-porch = <34>; + vfront-porch = <150>; + }; +}; diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf index d3881d7e2ed..6b946eca8f1 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf @@ -4,5 +4,3 @@ CONFIG_MEMC=y CONFIG_STM32_LTDC_RGB888=y CONFIG_HEAP_MEM_POOL_SIZE=65536 -# Initialize after LTDC and MIPI-DSI -CONFIG_DISPLAY_OTM8009A_INIT_PRIORITY=87 diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay index bbaba0718b9..7a80559b8c9 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay @@ -26,24 +26,8 @@ <dc { status = "okay"; ext-sdram = <&sdram2>; - - /* orisetech, otm8009a */ width = <800>; height = <480>; - display-timings { - compatible = "zephyr,panel-timing"; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - hsync-len = <2>; - vsync-len = <1>; - hback-porch = <34>; - vback-porch = <15>; - hfront-porch = <34>; - vfront-porch = <16>; - }; - def-back-color-red = <0>; def-back-color-green = <0>; def-back-color-blue = <0>; @@ -78,12 +62,6 @@ de-active-high; }; -&otm8009a { - data-lanes = <2>; - pixel-format = ; - rotation = <90>; -}; - &i2c4 { pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>; pinctrl-names = "default"; diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst b/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst index 4e71b025ee3..4bc150e0c0f 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst @@ -10,8 +10,11 @@ The B-LCD40-DSI1 shield provides a 4-inch WVGA TFT LCD with MIPI DSI interface and capacitive touch screen. .. note:: - Currently only the older version MB1166-A03 is supported by Zephyr. - The newer version MB1166-A09 does not get initialized correctly (see :github:`60888`). + The shield comes in different hardware revisions, the MB1166-A09 + is utilizing a NT35510 panel controller and shall specifically + use ``st_b_lcd40_dsi1_mb1166_a09`` as SHIELD when building + Prior versions are utilizing an OTM8009a controller and shall + use shield name without postfix, that is: ``st_b_lcd40_dsi1_mb1166`` .. figure:: image.jpg :alt: B-LCD40-DSI1 MB1166 Image @@ -101,7 +104,8 @@ Usage ***** The shield can be used in any application by setting ``SHIELD`` to -``st_b_lcd40_dsi1_mb1166`` and adding the necessary device tree properties. +``st_b_lcd40_dsi1_mb1166`` or ``st_b_lcd40_dsi1_mb1166_a09`` and adding +the necessary device tree properties. Set ``-DSHIELD="st_b_lcd40_dsi1_mb1166"`` when you invoke ``west build``. For example: diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay index 96469ab58de..f351cae9cdb 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay @@ -13,5 +13,8 @@ width = <480>; reset-gpios = <&dsi_lcd_qsh_030 57 GPIO_ACTIVE_HIGH>; bl-gpios = <&dsi_lcd_qsh_030 53 GPIO_ACTIVE_HIGH>; + data-lanes = <2>; + pixel-format = ; + rotation = <90>; }; }; diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay new file mode 100644 index 00000000000..0201678d4d0 --- /dev/null +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2024 Erik Andersson + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&mipi_dsi { + nt35510: nt35510@0 { + status = "okay"; + compatible = "frida,nt35510"; + reg = <0x0>; + height = <800>; + width = <480>; + reset-gpios = <&dsi_lcd_qsh_030 57 GPIO_ACTIVE_HIGH>; + bl-gpios = <&dsi_lcd_qsh_030 53 GPIO_ACTIVE_HIGH>; + data-lanes = <2>; + pixel-format = ; + rotation = <90>; + }; +}; From 7282508f65b5adf0a5cbca7929f70c21edcb3dc1 Mon Sep 17 00:00:00 2001 From: Erik Andersson Date: Fri, 22 Mar 2024 15:18:58 +0100 Subject: [PATCH 1745/2402] samples: ci: add st_b_lcd40_dsi1_mb1166_a09 shield Add tests for shield st_b_lcd40_dsi1_mb1166_a09 in: samples/drivers/display samples/modules/lvgl/demos samples/subsys/display/lvgl Signed-off-by: Erik Andersson --- samples/drivers/display/sample.yaml | 11 +++++++++++ samples/modules/lvgl/demos/sample.yaml | 18 ++++++++++++++++++ samples/subsys/display/lvgl/sample.yaml | 16 ++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/samples/drivers/display/sample.yaml b/samples/drivers/display/sample.yaml index c6188d37d14..50038edf939 100644 --- a/samples/drivers/display/sample.yaml +++ b/samples/drivers/display/sample.yaml @@ -137,6 +137,7 @@ tests: harness_config: fixture: fixture_display sample.display.st_b_lcd40_dsi1_mb1166: + filter: dt_compat_enabled("orisetech,otm8009a") platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: SHIELD=st_b_lcd40_dsi1_mb1166 tags: @@ -164,3 +165,13 @@ tests: harness_config: fixture: fixture_display tags: display + sample.display.st_b_lcd40_dsi1_mb1166_a09: + filter: dt_compat_enabled("frida,nt35510") + platform_allow: stm32h747i_disco/stm32h747xx/m7 + extra_args: SHIELD=st_b_lcd40_dsi1_mb1166_a09 + tags: + - display + - shield + harness: console + harness_config: + fixture: fixture_display diff --git a/samples/modules/lvgl/demos/sample.yaml b/samples/modules/lvgl/demos/sample.yaml index 4184f7df1af..5a9d668d02d 100644 --- a/samples/modules/lvgl/demos/sample.yaml +++ b/samples/modules/lvgl/demos/sample.yaml @@ -25,6 +25,7 @@ tests: extra_configs: - CONFIG_LV_Z_DEMO_WIDGETS=y sample.modules.lvgl.demos.st_b_lcd40_dsi1_mb1166: + filter: dt_compat_enabled("orisetech,otm8009a") platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: SHIELD=st_b_lcd40_dsi1_mb1166 harness: console @@ -40,3 +41,20 @@ tests: - shield - lvgl - gui + sample.modules.lvgl.demos.st_b_lcd40_dsi1_mb1166_a09: + filter: dt_compat_enabled("frida,nt35510") + platform_allow: stm32h747i_disco/stm32h747xx/m7 + extra_args: SHIELD=st_b_lcd40_dsi1_mb1166_a09 + harness: console + harness_config: + fixture: fixture_display + extra_configs: + - CONFIG_LV_Z_DEMO_BENCHMARK=y + modules: + - lvgl + tags: + - samples + - display + - shield + - lvgl + - gui diff --git a/samples/subsys/display/lvgl/sample.yaml b/samples/subsys/display/lvgl/sample.yaml index c0ab07d48e8..d8bfb5de9b5 100644 --- a/samples/subsys/display/lvgl/sample.yaml +++ b/samples/subsys/display/lvgl/sample.yaml @@ -41,6 +41,7 @@ tests: integration_platforms: - mimxrt1170_evk/mimxrt1176/cm7 sample.subsys.display.lvgl.st_b_lcd40_dsi1_mb1166: + filter: dt_compat_enabled("orisetech,otm8009a") platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: SHIELD=st_b_lcd40_dsi1_mb1166 harness: console @@ -54,3 +55,18 @@ tests: - shield - lvgl - gui + sample.subsys.display.lvgl.st_b_lcd40_dsi1_mb1166_a09: + filter: dt_compat_enabled("frida,nt35510") + platform_allow: stm32h747i_disco/stm32h747xx/m7 + extra_args: SHIELD=st_b_lcd40_dsi1_mb1166_a09 + harness: console + harness_config: + fixture: fixture_display + modules: + - lvgl + tags: + - samples + - display + - shield + - lvgl + - gui From 7d9fa5fab261a18c6ed57509e322140ebca187b2 Mon Sep 17 00:00:00 2001 From: Erik Andersson Date: Mon, 25 Mar 2024 19:31:52 +0100 Subject: [PATCH 1746/2402] doc: boards: update stm32h747i_disco documentation Explain the different versions of the MB1166 shield and remove note about that version A09 is not supported Signed-off-by: Erik Andersson --- boards/st/stm32h747i_disco/doc/index.rst | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/boards/st/stm32h747i_disco/doc/index.rst b/boards/st/stm32h747i_disco/doc/index.rst index 1f6846d6815..06b8c88e1ac 100644 --- a/boards/st/stm32h747i_disco/doc/index.rst +++ b/boards/st/stm32h747i_disco/doc/index.rst @@ -163,8 +163,8 @@ Display The STM32H747I Discovery kit has a dedicated DSI LCD connector **CN15**, where the MB1166 (B-LCD40-DSI1) display extension board can be mounted. Enable display -support in Zephyr by adding the shield ``st_b_lcd40_dsi1_mb1166`` to your build -command, for example: +support in Zephyr by adding the shield ``st_b_lcd40_dsi1_mb1166`` or +``st_b_lcd40_dsi1_mb1166_a09`` to your build command, for example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/display @@ -173,8 +173,13 @@ command, for example: :goals: build flash .. note:: - Currently only the older version MB1166-A03 is supported by Zephyr. - The newer version MB1166-A09 does not get initialized correctly (see :github:`60888`). + The shield comes in different hardware revisions, the MB1166-A09 + is utilizing a NT35510 panel controller and shall specifically + use ``st_b_lcd40_dsi1_mb1166_a09`` as SHIELD when building + Prior versions are utilizing an OTM8009a controller and shall + use shield name without postfix, that is: ``st_b_lcd40_dsi1_mb1166`` + Shield version is printed on a sticker placed below the two bottom + mounting holes and has the format: MB1166-Axx Resources sharing ================= From fcc729f2400aa02e43457fe65b0252aa5c1d3c02 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Tue, 20 Feb 2024 09:33:37 +0100 Subject: [PATCH 1747/2402] drivers: spi: Support NXP i.MX ECSPI Add a driver implementation for NXP's Enhanced Configurable SPI. Signed-off-by: Pieter De Gendt --- .../clock_control/clock_control_mcux_ccm.c | 18 + drivers/spi/CMakeLists.txt | 1 + drivers/spi/Kconfig | 2 + drivers/spi/Kconfig.mcux_ecspi | 11 + drivers/spi/spi_mcux_ecspi.c | 343 ++++++++++++++++++ dts/bindings/spi/nxp,imx-ecspi.yaml | 18 + include/zephyr/dt-bindings/clock/imx_ccm.h | 4 + 7 files changed, 397 insertions(+) create mode 100644 drivers/spi/Kconfig.mcux_ecspi create mode 100644 drivers/spi/spi_mcux_ecspi.c create mode 100644 dts/bindings/spi/nxp,imx-ecspi.yaml diff --git a/drivers/clock_control/clock_control_mcux_ccm.c b/drivers/clock_control/clock_control_mcux_ccm.c index 371adf15bdc..0b389819c46 100644 --- a/drivers/clock_control/clock_control_mcux_ccm.c +++ b/drivers/clock_control/clock_control_mcux_ccm.c @@ -377,6 +377,24 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, / (CLOCK_GetDiv(kCLOCK_Flexio2Div) + 1); } break; #endif + +#ifdef CONFIG_SPI_MCUX_ECSPI + case IMX_CCM_ECSPI1_CLK: + *rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / + (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi1)) / + (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi1)); + break; + case IMX_CCM_ECSPI2_CLK: + *rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / + (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi2)) / + (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi2)); + break; + case IMX_CCM_ECSPI3_CLK: + *rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / + (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi3)) / + (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi3)); + break; +#endif /* CONFIG_SPI_MCUX_ECSPI */ } return 0; diff --git a/drivers/spi/CMakeLists.txt b/drivers/spi/CMakeLists.txt index d5abf88f407..8bbae49d1c2 100644 --- a/drivers/spi/CMakeLists.txt +++ b/drivers/spi/CMakeLists.txt @@ -10,6 +10,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_DW spi_dw.c) zephyr_library_sources_ifdef(CONFIG_SPI_EMUL spi_emul.c) zephyr_library_sources_ifdef(CONFIG_SPI_STM32 spi_ll_stm32.c) zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_DSPI spi_mcux_dspi.c) +zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_ECSPI spi_mcux_ecspi.c) zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_FLEXCOMM spi_mcux_flexcomm.c) zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_FLEXIO spi_mcux_flexio.c) zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI spi_mcux_lpspi.c) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index acb37b3c43a..c7e40016b4e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -73,6 +73,8 @@ source "drivers/spi/Kconfig.dw" source "drivers/spi/Kconfig.mcux_dspi" +source "drivers/spi/Kconfig.mcux_ecspi" + source "drivers/spi/Kconfig.mcux_flexcomm" source "drivers/spi/Kconfig.mcux_flexio" diff --git a/drivers/spi/Kconfig.mcux_ecspi b/drivers/spi/Kconfig.mcux_ecspi new file mode 100644 index 00000000000..bec0b03899d --- /dev/null +++ b/drivers/spi/Kconfig.mcux_ecspi @@ -0,0 +1,11 @@ +# Copyright (c) 2024, Basalte bv +# SPDX-License-Identifier: Apache-2.0 + +config SPI_MCUX_ECSPI + bool "MCUX ECSPI driver" + default y + depends on DT_HAS_NXP_IMX_ECSPI_ENABLED + depends on CLOCK_CONTROL + select PINCTRL + help + Enable support for NXP's mcux ecspi driver. diff --git a/drivers/spi/spi_mcux_ecspi.c b/drivers/spi/spi_mcux_ecspi.c new file mode 100644 index 00000000000..dd1d4998126 --- /dev/null +++ b/drivers/spi/spi_mcux_ecspi.c @@ -0,0 +1,343 @@ +/* + * Copyright (c) 2024, Basalte bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_imx_ecspi + +#include +LOG_MODULE_REGISTER(spi_mcux_ecspi, CONFIG_SPI_LOG_LEVEL); + +#include +#include +#include +#include +#include + +#include "spi_context.h" + +#define SPI_MCUX_ECSPI_MAX_BURST 4096 + +struct spi_mcux_config { + ECSPI_Type *base; + const struct pinctrl_dev_config *pincfg; + const struct device *clock_dev; + clock_control_subsys_t clock_subsys; + void (*irq_config_func)(const struct device *dev); +}; + +struct spi_mcux_data { + ecspi_master_handle_t handle; + struct spi_context ctx; + + uint16_t dfs; + uint16_t word_size; + + uint32_t rx_data; + uint32_t tx_data; +}; + +static inline uint16_t bytes_per_word(uint16_t bits_per_word) +{ + if (bits_per_word <= 8U) { + return 1U; + } + if (bits_per_word <= 16U) { + return 2U; + } + + return 4U; +} + +static void spi_mcux_transfer_next_packet(const struct device *dev) +{ + const struct spi_mcux_config *config = dev->config; + struct spi_mcux_data *data = dev->data; + ECSPI_Type *base = config->base; + struct spi_context *ctx = &data->ctx; + ecspi_transfer_t transfer; + status_t status; + + if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) { + /* nothing left to rx or tx, we're done! */ + spi_context_cs_control(&data->ctx, false); + spi_context_complete(&data->ctx, dev, 0); + return; + } + + transfer.channel = ctx->config->slave; + + if (spi_context_rx_buf_on(ctx)) { + transfer.rxData = &data->rx_data; + } else { + transfer.rxData = NULL; + } + + if (spi_context_tx_buf_on(ctx)) { + switch (data->dfs) { + case 1U: + data->tx_data = UNALIGNED_GET((uint8_t *)ctx->tx_buf); + break; + case 2U: + data->tx_data = UNALIGNED_GET((uint16_t *)ctx->tx_buf); + break; + case 4U: + data->tx_data = UNALIGNED_GET((uint32_t *)ctx->tx_buf); + break; + } + + transfer.txData = &data->tx_data; + } else { + transfer.txData = NULL; + } + + transfer.dataSize = data->dfs; + + status = ECSPI_MasterTransferNonBlocking(base, &data->handle, &transfer); + if (status != kStatus_Success) { + LOG_ERR("Transfer could not start"); + spi_context_cs_control(&data->ctx, false); + spi_context_complete(&data->ctx, dev, -EIO); + } +} + +static void spi_mcux_isr(const struct device *dev) +{ + const struct spi_mcux_config *config = dev->config; + struct spi_mcux_data *data = dev->data; + ECSPI_Type *base = config->base; + + ECSPI_MasterTransferHandleIRQ(base, &data->handle); +} + +static void spi_mcux_master_transfer_callback(ECSPI_Type *base, ecspi_master_handle_t *handle, + status_t status, void *user_data) +{ + const struct device *dev = (const struct device *)user_data; + struct spi_mcux_data *data = dev->data; + + if (spi_context_rx_buf_on(&data->ctx)) { + switch (data->dfs) { + case 1: + UNALIGNED_PUT(data->rx_data, (uint8_t *)data->ctx.rx_buf); + break; + case 2: + UNALIGNED_PUT(data->rx_data, (uint16_t *)data->ctx.rx_buf); + break; + case 4: + UNALIGNED_PUT(data->rx_data, (uint32_t *)data->ctx.rx_buf); + break; + } + } + + spi_context_update_tx(&data->ctx, data->dfs, 1); + spi_context_update_rx(&data->ctx, data->dfs, 1); + + spi_mcux_transfer_next_packet(dev); +} + +static int spi_mcux_configure(const struct device *dev, + const struct spi_config *spi_cfg) +{ + const struct spi_mcux_config *config = dev->config; + struct spi_mcux_data *data = dev->data; + ECSPI_Type *base = config->base; + ecspi_master_config_t master_config; + uint32_t clock_freq; + uint16_t word_size; + + if (spi_context_configured(&data->ctx, spi_cfg)) { + /* This configuration is already in use */ + return 0; + } + + if (spi_cfg->operation & SPI_HALF_DUPLEX) { + LOG_ERR("Half-duplex not supported"); + return -ENOTSUP; + } + + if (spi_cfg->operation & SPI_TRANSFER_LSB) { + LOG_ERR("HW byte re-ordering not supported"); + return -ENOTSUP; + } + + if (spi_cfg->slave > kECSPI_Channel3) { + LOG_ERR("Slave %d is greater than %d", spi_cfg->slave, kECSPI_Channel3); + return -EINVAL; + } + + if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq)) { + LOG_ERR("Failed to get clock rate"); + return -EINVAL; + } + + word_size = SPI_WORD_SIZE_GET(spi_cfg->operation); + if (0 == word_size || word_size > 32) { + LOG_ERR("Invalid word size (0 < %d <= 32)", word_size); + return -EINVAL; + } + + ECSPI_MasterGetDefaultConfig(&master_config); + + master_config.channel = (ecspi_channel_source_t)spi_cfg->slave; + master_config.channelConfig.polarity = + (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL) + ? kECSPI_PolarityActiveLow + : kECSPI_PolarityActiveHigh; + master_config.channelConfig.phase = + (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA) + ? kECSPI_ClockPhaseSecondEdge + : kECSPI_ClockPhaseFirstEdge; + master_config.baudRate_Bps = spi_cfg->frequency; + master_config.burstLength = word_size; + + master_config.enableLoopback = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_LOOP); + + if (!spi_cs_is_gpio(spi_cfg)) { + uint32_t clock_cycles = + DIV_ROUND_UP(spi_cfg->cs.delay * USEC_PER_SEC, spi_cfg->frequency); + + if (clock_cycles > 63U) { + LOG_ERR("CS delay is greater than 63 clock cycles (%u)", clock_cycles); + return -EINVAL; + } + master_config.chipSelectDelay = (uint8_t)clock_cycles; + } + + ECSPI_MasterInit(base, &master_config, clock_freq); + ECSPI_MasterTransferCreateHandle(base, &data->handle, + spi_mcux_master_transfer_callback, + (void *)dev); + + data->word_size = word_size; + data->dfs = bytes_per_word(word_size); + data->ctx.config = spi_cfg; + + return 0; +} + +static int transceive(const struct device *dev, + const struct spi_config *spi_cfg, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs, + bool asynchronous, + spi_callback_t cb, + void *userdata) +{ + struct spi_mcux_data *data = dev->data; + int ret; + + spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg); + + ret = spi_mcux_configure(dev, spi_cfg); + if (ret) { + goto out; + } + + spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, data->dfs); + spi_context_cs_control(&data->ctx, true); + + spi_mcux_transfer_next_packet(dev); + ret = spi_context_wait_for_completion(&data->ctx); + +out: + spi_context_release(&data->ctx, ret); + + return ret; +} + +static int spi_mcux_transceive(const struct device *dev, + const struct spi_config *spi_cfg, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs) +{ + return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL); +} + +#ifdef CONFIG_SPI_ASYNC +static int spi_mcux_transceive_async(const struct device *dev, + const struct spi_config *spi_cfg, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs, + spi_callback_t cb, + void *userdata) +{ + return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata); +} +#endif /* CONFIG_SPI_ASYNC */ + +static int spi_mcux_release(const struct device *dev, const struct spi_config *spi_cfg) +{ + struct spi_mcux_data *data = dev->data; + + ARG_UNUSED(spi_cfg); + + spi_context_unlock_unconditionally(&data->ctx); + + return 0; +} + +static int spi_mcux_init(const struct device *dev) +{ + int ret; + const struct spi_mcux_config *config = dev->config; + struct spi_mcux_data *data = dev->data; + + config->irq_config_func(dev); + + ret = spi_context_cs_configure_all(&data->ctx); + if (ret < 0) { + return ret; + } + + ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } + + spi_context_unlock_unconditionally(&data->ctx); + + return 0; +} + +static const struct spi_driver_api spi_mcux_driver_api = { + .transceive = spi_mcux_transceive, +#ifdef CONFIG_SPI_ASYNC + .transceive_async = spi_mcux_transceive_async, +#endif + .release = spi_mcux_release, +}; + +#define SPI_MCUX_ECSPI_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + static void spi_mcux_config_func_##n(const struct device *dev); \ + \ + static const struct spi_mcux_config spi_mcux_config_##n = { \ + .base = (ECSPI_Type *) DT_INST_REG_ADDR(n), \ + .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \ + .irq_config_func = spi_mcux_config_func_##n, \ + }; \ + \ + static struct spi_mcux_data spi_mcux_data_##n = { \ + SPI_CONTEXT_INIT_LOCK(spi_mcux_data_##n, ctx), \ + SPI_CONTEXT_INIT_SYNC(spi_mcux_data_##n, ctx), \ + SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, &spi_mcux_init, NULL, \ + &spi_mcux_data_##n, &spi_mcux_config_##n, \ + POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \ + &spi_mcux_driver_api); \ + \ + static void spi_mcux_config_func_##n(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ + spi_mcux_isr, DEVICE_DT_INST_GET(n), 0); \ + \ + irq_enable(DT_INST_IRQN(n)); \ + } + +DT_INST_FOREACH_STATUS_OKAY(SPI_MCUX_ECSPI_INIT) diff --git a/dts/bindings/spi/nxp,imx-ecspi.yaml b/dts/bindings/spi/nxp,imx-ecspi.yaml new file mode 100644 index 00000000000..5e63138471b --- /dev/null +++ b/dts/bindings/spi/nxp,imx-ecspi.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Basalte bv +# SPDX-License-Identifier: Apache-2.0 + +description: NXP i.MX ECSPI controller + +compatible: "nxp,imx-ecspi" + +include: ["spi-controller.yaml", "pinctrl-device.yaml"] + +properties: + reg: + required: true + + interrupts: + required: true + + clocks: + required: true diff --git a/include/zephyr/dt-bindings/clock/imx_ccm.h b/include/zephyr/dt-bindings/clock/imx_ccm.h index 49bc7db9246..b57ca4aedca 100644 --- a/include/zephyr/dt-bindings/clock/imx_ccm.h +++ b/include/zephyr/dt-bindings/clock/imx_ccm.h @@ -66,4 +66,8 @@ #define IMX_CCM_FLEXIO1_CLK 0x1100UL #define IMX_CCM_FLEXIO2_3_CLK 0x1101UL +#define IMX_CCM_ECSPI1_CLK 0x1200UL +#define IMX_CCM_ECSPI2_CLK 0x1201UL +#define IMX_CCM_ECSPI3_CLK 0x1202UL + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */ From 5944fb38bf58ee388ba76ee6589c5017aef1ee4c Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Tue, 20 Feb 2024 09:37:17 +0100 Subject: [PATCH 1748/2402] dts: arm: nxp: nxp_imx8ml_m7: Add ECSPI instances Add device tree instances for ECSPI peripherals and update SoC code to enable clocks. Signed-off-by: Pieter De Gendt --- dts/arm/nxp/nxp_imx8ml_m7.dtsi | 29 +++++++++++++++++++++++++++++ soc/nxp/imx/imx8m/m7/soc.c | 23 +++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/dts/arm/nxp/nxp_imx8ml_m7.dtsi b/dts/arm/nxp/nxp_imx8ml_m7.dtsi index df4636bc72a..80c62a22cf1 100644 --- a/dts/arm/nxp/nxp_imx8ml_m7.dtsi +++ b/dts/arm/nxp/nxp_imx8ml_m7.dtsi @@ -181,6 +181,35 @@ status = "disabled"; }; + ecspi1: spi@30820000 { + compatible = "nxp,imx-ecspi"; + reg = <0x30820000 DT_SIZE_K(64)>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <31 3>; + clocks = <&ccm IMX_CCM_ECSPI1_CLK 0 0>; + status = "disabled"; + }; + + ecspi2: spi@30830000 { + compatible = "nxp,imx-ecspi"; + reg = <0x30830000 DT_SIZE_K(64)>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32 3>; + clocks = <&ccm IMX_CCM_ECSPI2_CLK 0 0>; + status = "disabled"; + }; + + ecspi3: spi@30840000 { + compatible = "nxp,imx-ecspi"; + reg = <0x30840000 DT_SIZE_K(64)>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <33 3>; + clocks = <&ccm IMX_CCM_ECSPI3_CLK 0 0>; + status = "disabled"; + }; }; }; diff --git a/soc/nxp/imx/imx8m/m7/soc.c b/soc/nxp/imx/imx8m/m7/soc.c index 950212b26a4..724368eac37 100644 --- a/soc/nxp/imx/imx8m/m7/soc.c +++ b/soc/nxp/imx/imx8m/m7/soc.c @@ -131,6 +131,29 @@ static void SOC_ClockInit(void) /* Set root clock to 80MHZ/ 1= 80MHZ */ CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U); #endif +#endif + +#if defined(CONFIG_SPI_MCUX_ECSPI) +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ecspi1), okay) + /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */ + CLOCK_SetRootMux(kCLOCK_RootEcspi1, kCLOCK_EcspiRootmuxSysPll1); + /* Set root clock to 800MHZ / 10 = 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ecspi2), okay) + /* Set ECSPI2 source to SYSTEM PLL1 800MHZ */ + CLOCK_SetRootMux(kCLOCK_RootEcspi2, kCLOCK_EcspiRootmuxSysPll1); + /* Set root clock to 800MHZ / 10 = 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootEcspi2, 2U, 5U); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ecspi3), okay) + /* Set ECSPI3 source to SYSTEM PLL1 800MHZ */ + CLOCK_SetRootMux(kCLOCK_RootEcspi3, kCLOCK_EcspiRootmuxSysPll1); + /* Set root clock to 800MHZ / 10 = 80MHZ */ + CLOCK_SetRootDivider(kCLOCK_RootEcspi3, 2U, 5U); +#endif #endif CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */ From c093ff4260a50547c05d6282cbc201c80ec4f52c Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Tue, 20 Feb 2024 14:37:07 +0100 Subject: [PATCH 1749/2402] tests: drivers: spi: spi_loopback: Add mimx8mp_evk board Add a config and overlay for NXP mimx8mp_evk board. Signed-off-by: Pieter De Gendt --- .../boards/imx8mp_evk_mimx8ml8_m7.conf | 6 +++ .../boards/imx8mp_evk_mimx8ml8_m7.overlay | 42 +++++++++++++++++++ .../boards/imx8mp_evk_mimx8ml8_m7_ddr.conf | 6 +++ .../boards/imx8mp_evk_mimx8ml8_m7_ddr.overlay | 42 +++++++++++++++++++ 4 files changed, 96 insertions(+) create mode 100644 tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7.conf create mode 100644 tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7.overlay create mode 100644 tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7_ddr.conf create mode 100644 tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7_ddr.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7.conf b/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7.conf new file mode 100644 index 00000000000..3286a714d0f --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7.conf @@ -0,0 +1,6 @@ +# +# Copyright (c) 2024 Basalte bv +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI_LOOPBACK_MODE_LOOP=y diff --git a/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7.overlay b/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7.overlay new file mode 100644 index 00000000000..5bb6043b803 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7.overlay @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 Basalte bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + ecspi1_default: ecspi1_default { + group1 { + pinmux = <&iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso>, + <&iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi>, + <&iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + group2 { + pinmux = <&iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0>; + slew-rate = "fast"; + drive-strength = "x6"; + bias-pull-up; + }; + }; +}; + +&ecspi1 { + status = "okay"; + pinctrl-0 = <&ecspi1_default>; + pinctrl-names = "default"; + + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <500000>; + }; + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = <16000000>; + }; +}; diff --git a/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7_ddr.conf b/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7_ddr.conf new file mode 100644 index 00000000000..3286a714d0f --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7_ddr.conf @@ -0,0 +1,6 @@ +# +# Copyright (c) 2024 Basalte bv +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI_LOOPBACK_MODE_LOOP=y diff --git a/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7_ddr.overlay b/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7_ddr.overlay new file mode 100644 index 00000000000..5bb6043b803 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/imx8mp_evk_mimx8ml8_m7_ddr.overlay @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 Basalte bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + ecspi1_default: ecspi1_default { + group1 { + pinmux = <&iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso>, + <&iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi>, + <&iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + group2 { + pinmux = <&iomuxc_ecspi1_ss0_ecspi_ss_ecspi1_ss0>; + slew-rate = "fast"; + drive-strength = "x6"; + bias-pull-up; + }; + }; +}; + +&ecspi1 { + status = "okay"; + pinctrl-0 = <&ecspi1_default>; + pinctrl-names = "default"; + + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <500000>; + }; + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = <16000000>; + }; +}; From b9e4850aa2f1120328574d450fbdcfa4ad877b5b Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Tue, 20 Feb 2024 15:19:50 +0100 Subject: [PATCH 1750/2402] boards: arm: mimx8mp_evk: Enable spi support Set spi as supported to allow loopback testing. Signed-off-by: Pieter De Gendt --- boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml | 1 + boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml index 6ab73e3386a..799c88b4fb3 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml @@ -19,5 +19,6 @@ testing: - net - bluetooth supported: + - spi - uart vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml index e5ed32a1d38..f76568a30d7 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml @@ -19,5 +19,6 @@ testing: - net - bluetooth supported: + - spi - uart vendor: nxp From abffe27edb35d235c9d07687548d319a44cc0a37 Mon Sep 17 00:00:00 2001 From: Jimmy Zheng Date: Mon, 29 Jan 2024 14:44:06 +0800 Subject: [PATCH 1751/2402] soc: andestech: pma.c: include soc_v5.h Add include header for CSR definition. Signed-off-by: Jimmy Zheng --- soc/andestech/ae350/pma.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/soc/andestech/ae350/pma.c b/soc/andestech/ae350/pma.c index 46807bf0739..9847ba622eb 100644 --- a/soc/andestech/ae350/pma.c +++ b/soc/andestech/ae350/pma.c @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include "soc_v5.h" + #include #include #include From ed021551dce0967c5e81b709cc9cb93ac35869a1 Mon Sep 17 00:00:00 2001 From: Jimmy Zheng Date: Tue, 30 Jan 2024 09:16:34 +0800 Subject: [PATCH 1752/2402] soc: andestech: linker.ld: fixed ROM padding issue Updated ROM region padding to utilize LMA instead of location counter, because the location counter has been assigned to 'RAM_BASE'. Signed-off-by: Jimmy Zheng --- soc/andestech/ae350/linker.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/andestech/ae350/linker.ld b/soc/andestech/ae350/linker.ld index 041d0aad530..f47a5d5f040 100644 --- a/soc/andestech/ae350/linker.ld +++ b/soc/andestech/ae350/linker.ld @@ -423,8 +423,8 @@ __rom_region_end = LOADADDR(.last_section) + SIZEOF(.last_section); SECTION_PROLOGUE(rom_mpu_padding,(NOLOAD),) { MPU_ALIGN(__rom_region_size); - __rom_region_end = .; } GROUP_LINK_IN(ROMABLE_REGION) +__rom_region_end = LOADADDR(rom_mpu_padding) + SIZEOF(rom_mpu_padding); #endif /* !CONFIG_RISCV_PMP */ __rom_region_size = __rom_region_end - __rom_region_start; #endif From f80377bd4e589c2f9f23a48eb5dd56deb8767edf Mon Sep 17 00:00:00 2001 From: Jimmy Zheng Date: Wed, 20 Mar 2024 16:52:25 +0800 Subject: [PATCH 1753/2402] soc: andestech: linker.ld: clarify usage of __rom_region_end/size Clarify usage of __rom_region_end/size in XIP system. When PMP is enabled, __rom_region_end should be padded to meet the requirement of PMP entry, and the actual ROM region usage ends at .last_section instead of __rom_region_end. Signed-off-by: Jimmy Zheng --- soc/andestech/ae350/linker.ld | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/soc/andestech/ae350/linker.ld b/soc/andestech/ae350/linker.ld index f47a5d5f040..9098aa2072f 100644 --- a/soc/andestech/ae350/linker.ld +++ b/soc/andestech/ae350/linker.ld @@ -400,10 +400,6 @@ GROUP_END(DTCM) /* Sections generated from 'zephyr,memory-region' nodes */ LINKER_DT_SECTIONS() -/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid - * to set __rom_region_end symbol at the end of linker script and - * doesn't mistakenly contain the RAMABLE_REGION in it. - */ #ifdef CONFIG_XIP /* Must be last in romable region */ SECTION_PROLOGUE(.last_section,,) @@ -415,17 +411,27 @@ SECTION_PROLOGUE(.last_section,,) #endif } GROUP_LINK_IN(ROMABLE_REGION) +/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid + * to set __rom_region_end symbol at the end of linker script and + * doesn't mistakenly contain the RAMABLE_REGION in it. + */ #ifndef CONFIG_RISCV_PMP -/* To provide the image size as a const expression, - * calculate this value here. */ __rom_region_end = LOADADDR(.last_section) + SIZEOF(.last_section); #else +/* Padding __rom_region_end to matches the requirement of the MPU region. + * __rom_region_size is used to configure the MPU region, but the actual rom + * region data usage is ends at .last_section. + */ SECTION_PROLOGUE(rom_mpu_padding,(NOLOAD),) { MPU_ALIGN(__rom_region_size); } GROUP_LINK_IN(ROMABLE_REGION) __rom_region_end = LOADADDR(rom_mpu_padding) + SIZEOF(rom_mpu_padding); #endif /* !CONFIG_RISCV_PMP */ + +/* To provide the rom region size as a const expression, + * calculate this value here. + */ __rom_region_size = __rom_region_end - __rom_region_start; #endif From 6ab94f04298613c35a9799001c580dd9bf01d2fc Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 15 Mar 2024 01:26:53 +0100 Subject: [PATCH 1754/2402] tests: drivers: pwm: Add lpcxpresso55s69 board name This adds a board name that got missed in commit 8dc3f856229ce083c956aa301c31a23e65bd8cd8 (hwmv2: Introduce Hardware model version 2 and convert devices) Signed-off-by: Reto Schneider --- tests/drivers/pwm/pwm_api/src/test_pwm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/drivers/pwm/pwm_api/src/test_pwm.c b/tests/drivers/pwm/pwm_api/src/test_pwm.c index c04bca4568a..904cf90964e 100644 --- a/tests/drivers/pwm/pwm_api/src/test_pwm.c +++ b/tests/drivers/pwm/pwm_api/src/test_pwm.c @@ -81,7 +81,8 @@ #define DEFAULT_PWM_PORT 2 /* TCC1/WO[2] on PA18 (D7) */ #elif defined CONFIG_BOARD_MIMXRT685_EVK #define DEFAULT_PWM_PORT 7 /* D3 on Arduino connector J27 */ -#elif defined CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 +#elif defined(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS) || \ + defined(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0) #define DEFAULT_PWM_PORT 2 /* D2 on Arduino connector P18 */ #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_pwm) /* Default port should be adapted per board to fit the channel From b0f9391aee393a9d1d28b0a603c8364560b75f99 Mon Sep 17 00:00:00 2001 From: Piotr Pryga Date: Fri, 22 Mar 2024 10:27:38 +0100 Subject: [PATCH 1755/2402] board: nrf54h20dk: Add missing default BT related configs There are default configs that are provided by default for e.g. nRF5340dk to enable HCI IPC communication type for application domain and enable BT controller for radio domain. These configs were missing for nRF54h20 DK. Signed-off-by: Piotr Pryga --- boards/nordic/nrf54h20dk/Kconfig.defconfig | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 boards/nordic/nrf54h20dk/Kconfig.defconfig diff --git a/boards/nordic/nrf54h20dk/Kconfig.defconfig b/boards/nordic/nrf54h20dk/Kconfig.defconfig new file mode 100644 index 00000000000..74fe93905ac --- /dev/null +++ b/boards/nordic/nrf54h20dk/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54H20DK_NRF54H20_CPUAPP + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP + +if BOARD_NRF54H20DK_NRF54H20_CPURAD + +config BT_CTLR + default y if BT + +endif # BOARD_NRF54H20DK_NRF54H20_CPURAD From 6f07cecc9529d44fac0b0adfe5313379719d7681 Mon Sep 17 00:00:00 2001 From: Piotr Pryga Date: Fri, 22 Mar 2024 10:12:13 +0100 Subject: [PATCH 1756/2402] boards: nrf54h20: Fix storage partitions for setting subsytem There was missing storage partition that is required for setting subsytem. Add missing entries to board files. Signed-off-by: Piotr Pryga --- .../nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi | 14 ++++++++++++++ .../nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi index 6b6402eb90f..68c0d5cd990 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi @@ -181,4 +181,18 @@ reg = <0x126000 DT_SIZE_K(64)>; }; }; + + cpuapp_rw_partitions: cpuapp-rw-partitions { + compatible = "nordic,owned-partitions", "fixed-partitions"; + status = "disabled"; + perm-read; + perm-write; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@136000 { + reg = <0x136000 DT_SIZE_K(24)>; + }; + }; }; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index a8ea9fe730f..8c6512861e8 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -130,6 +130,10 @@ status = "okay"; }; +&cpuapp_rw_partitions { + status = "okay"; +}; + &cpuppr_vpr { execution-memory = <&cpuppr_code_data>; source-memory = <&cpuppr_code_partition>; From 73bdf622f14e847068b3db776dd5a373654e2f6a Mon Sep 17 00:00:00 2001 From: Piotr Pryga Date: Mon, 25 Mar 2024 09:50:59 +0100 Subject: [PATCH 1757/2402] samples: bluetooth: hci_ipc: Add nrf54h20 DK board overlay There are required DTS entries to nable peripherals required for IPC communication between Radio and APP CPUs. Signed-off-by: Piotr Pryga --- .../boards/nrf54h20dk_nrf54h20_cpurad.overlay | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay diff --git a/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay new file mode 100644 index 00000000000..02db7c39272 --- /dev/null +++ b/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay @@ -0,0 +1,27 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,bt-hci-ipc = &ipc0; + }; +}; + +ipc0: &cpuapp_cpurad_ipc { + status = "okay"; +}; + +&cpuapp_cpurad_ram0x_region { + status = "okay"; +}; + +&cpurad_bellboard { + status = "okay"; +}; + +&cpuapp_bellboard { + status = "okay"; +}; From 45ff5afbb74759f97d403ca42628c19a64487f6c Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Thu, 29 Feb 2024 15:57:45 +0800 Subject: [PATCH 1758/2402] Bluetooth: Host: Check conn/channel status of L2CAP BR For BR/EDR L2CAP, if the function bt_l2cap_br_chan_send_cb instead of bt_l2cap_chan_send is called, the ACL conn and L2CAP chennel status will not be checked. Check conn/channel status before sending data in function bt_l2cap_br_chan_send_cb. Signed-off-by: Lyle Zhu --- subsys/bluetooth/host/classic/l2cap_br.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/subsys/bluetooth/host/classic/l2cap_br.c b/subsys/bluetooth/host/classic/l2cap_br.c index f1765105e08..f4f45db481f 100644 --- a/subsys/bluetooth/host/classic/l2cap_br.c +++ b/subsys/bluetooth/host/classic/l2cap_br.c @@ -1469,7 +1469,23 @@ static void l2cap_br_conn_rsp(struct bt_l2cap_br *l2cap, uint8_t ident, int bt_l2cap_br_chan_send_cb(struct bt_l2cap_chan *chan, struct net_buf *buf, bt_conn_tx_cb_t cb, void *user_data) { - struct bt_l2cap_br_chan *br_chan = BR_CHAN(chan); + struct bt_l2cap_br_chan *br_chan; + + if (!buf || !chan) { + return -EINVAL; + } + + br_chan = BR_CHAN(chan); + + LOG_DBG("chan %p buf %p len %zu", chan, buf, net_buf_frags_len(buf)); + + if (!chan->conn || chan->conn->state != BT_CONN_CONNECTED) { + return -ENOTCONN; + } + + if (atomic_test_bit(chan->status, BT_L2CAP_STATUS_SHUTDOWN)) { + return -ESHUTDOWN; + } if (buf->len > br_chan->tx.mtu) { return -EMSGSIZE; From 9c0b8181f3fd66cdff5354409c8acdae3206d1a0 Mon Sep 17 00:00:00 2001 From: Marcin Gasiorek Date: Thu, 28 Mar 2024 22:58:07 +0100 Subject: [PATCH 1759/2402] net: dhcpv6: Add configurable DUID buffer length According to the `RFC8415` the length of the DUID is at least 1 octet up to 128 octets. Now a user can choose buffer length without the need for source code modification. Signed-off-by: Marcin Gasiorek --- include/zephyr/net/dhcpv6.h | 7 +++++-- subsys/net/lib/dhcpv6/Kconfig | 7 +++++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/include/zephyr/net/dhcpv6.h b/include/zephyr/net/dhcpv6.h index 95b59f530b5..715b8cae858 100644 --- a/include/zephyr/net/dhcpv6.h +++ b/include/zephyr/net/dhcpv6.h @@ -38,11 +38,14 @@ enum net_dhcpv6_state { } __packed; #define DHCPV6_TID_SIZE 3 -#define DHCPV6_DUID_MAX_SIZE 20 + +#ifndef CONFIG_NET_DHCPV6_DUID_MAX_LEN +#define CONFIG_NET_DHCPV6_DUID_MAX_LEN 22 +#endif struct net_dhcpv6_duid_raw { uint16_t type; - uint8_t buf[DHCPV6_DUID_MAX_SIZE]; + uint8_t buf[CONFIG_NET_DHCPV6_DUID_MAX_LEN]; } __packed; struct net_dhcpv6_duid_storage { diff --git a/subsys/net/lib/dhcpv6/Kconfig b/subsys/net/lib/dhcpv6/Kconfig index a406f4022a8..24443c9b36c 100644 --- a/subsys/net/lib/dhcpv6/Kconfig +++ b/subsys/net/lib/dhcpv6/Kconfig @@ -15,6 +15,13 @@ config NET_DHCPV6 select NET_MGMT_EVENT depends on NET_IPV6 && NET_UDP +config NET_DHCPV6_DUID_MAX_LEN + int "The maximum DUID length (not including a type code)" + range 1 128 + default 22 + help + This will set the available number of bytes for the DUID. + if NET_DHCPV6 module = NET_DHCPV6 module-dep = NET_LOG From aad1f6e47bda64223bc90c8ec642e837e6890c74 Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Mon, 1 Apr 2024 16:21:08 +0900 Subject: [PATCH 1760/2402] test: posix: headers: check for pthread_rwlockattr_getpshared() Check for the existence of pthread_rwlockattr_getpshared() and pthread_rwlockattr_setpshared(). Signed-off-by: Gaetan Perrot --- tests/posix/headers/src/pthread_h.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/posix/headers/src/pthread_h.c b/tests/posix/headers/src/pthread_h.c index 2f6a7942092..9d5f0336e40 100644 --- a/tests/posix/headers/src/pthread_h.c +++ b/tests/posix/headers/src/pthread_h.c @@ -143,9 +143,9 @@ ZTEST(posix_headers, test_pthread_h) zassert_not_null(pthread_rwlock_unlock); zassert_not_null(pthread_rwlock_wrlock); zassert_not_null(pthread_rwlockattr_destroy); - /* zassert_not_null(pthread_rwlockattr_getpshared); */ /* not implemented */ + zassert_not_null(pthread_rwlockattr_getpshared); zassert_not_null(pthread_rwlockattr_init); - /* zassert_not_null(pthread_rwlockattr_setpshared); */ /* not implemented */ + zassert_not_null(pthread_rwlockattr_setpshared); zassert_not_null(pthread_self); zassert_not_null(pthread_setcancelstate); zassert_not_null(pthread_setcanceltype); From c032c6305dccaa74c6095fc27f382aaa7ce2730f Mon Sep 17 00:00:00 2001 From: Benjamin Perseghetti Date: Tue, 2 Apr 2024 20:26:46 +0200 Subject: [PATCH 1761/2402] boards: nxp: vmu_rt1170: Fix dts binding issues Fixs USDHC by setting PWR and CD gpio's correctly. Adds missing button from the GPS module. Co-authored-by: Peter van der Perk Signed-off-by: Benjamin Perseghetti --- boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi | 13 +++++++++++-- boards/nxp/vmu_rt1170/vmu_rt1170.dts | 17 ++++++++++------- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi index d25bffa04c5..ac50cfa8b76 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi +++ b/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi @@ -128,6 +128,11 @@ }; }; + pinmux_user: pinmux_user { + group0 { + pinmux = <&iomuxc_gpio_emc_b1_24_gpio_mux1_io24>; + }; + }; pinmux_flexspi1: pinmux_flexspi1 { group0 { @@ -346,11 +351,15 @@ input-enable; }; group1 { - pinmux = <&iomuxc_gpio_sd_b1_01_usdhc1_clk>, - <&iomuxc_gpio_ad_32_usdhc1_cd_b>; + pinmux = <&iomuxc_gpio_sd_b1_01_usdhc1_clk>; drive-strength = "high"; slew-rate = "fast"; }; + group2 { + pinmux = <&iomuxc_gpio_ad_32_usdhc1_cd_b>; + bias-pull-down; + input-enable; + }; }; }; diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170.dts b/boards/nxp/vmu_rt1170/vmu_rt1170.dts index 265fedef389..dc60deb2e18 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170.dts +++ b/boards/nxp/vmu_rt1170/vmu_rt1170.dts @@ -19,6 +19,7 @@ led1 = &red_led; watchdog0 = &wdog1; sdhc0 = &usdhc1; + sw0 = &arming_button; }; chosen { @@ -34,13 +35,13 @@ zephyr,code-partition = &slot0_partition; }; - /* This regulator controls VDD_3V3_SD_CARD onboard supply */ - reg-3v3-sdcard { - compatible = "regulator-fixed"; - regulator-name = "reg-3v3-sdcard"; - enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - regulator-always-on; - status = "okay"; + /* This is the Button on the included GPS module for 10 pin JST-GH */ + buttons { + compatible = "gpio-keys"; + arming_button: button_0 { + label = "Arming Switch"; + gpios = <&gpio1 24 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + }; }; /* This regulator controls VDD_5V_PERIPH onboard supply */ @@ -397,6 +398,8 @@ &usdhc1 { status = "okay"; + no-1-8-v; + pwr-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; sdmmc { compatible = "zephyr,sdmmc-disk"; status = "okay"; From 019b813a710910875990525e1eec0185725cf849 Mon Sep 17 00:00:00 2001 From: Iuliana Prodan Date: Thu, 7 Mar 2024 17:43:28 +0200 Subject: [PATCH 1762/2402] linker: nxp: add orphan linker section Add missing linker section to avoid warning about orphans when building with host compiler. Signed-off-by: Iuliana Prodan --- soc/nxp/imx/imx8m/adsp/linker.ld | 1 + 1 file changed, 1 insertion(+) diff --git a/soc/nxp/imx/imx8m/adsp/linker.ld b/soc/nxp/imx/imx8m/adsp/linker.ld index 9687b604d6c..97d969d476f 100644 --- a/soc/nxp/imx/imx8m/adsp/linker.ld +++ b/soc/nxp/imx/imx8m/adsp/linker.ld @@ -529,4 +529,5 @@ SECTIONS } >fw_metadata_seg :metadata_entries_phdr #include + /DISCARD/ : { *(.note.GNU-stack) } } From 5230b64cf01419cabe116a99b774a40118abbd5c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Mon, 25 Mar 2024 23:10:01 +0100 Subject: [PATCH 1763/2402] random: add sys_rand8/16/64_get() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add sys_rand8_get(), sys_rand16_get() and sys_rand64_get() Signed-off-by: Fin Maaß --- include/zephyr/random/random.h | 53 ++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/include/zephyr/random/random.h b/include/zephyr/random/random.h index bbfdd98c421..bb7f502a3d1 100644 --- a/include/zephyr/random/random.h +++ b/include/zephyr/random/random.h @@ -67,6 +67,42 @@ __syscall void sys_rand_get(void *dst, size_t len); */ __syscall int sys_csrand_get(void *dst, size_t len); +/** + * @brief Return a 8-bit random value that should pass general + * randomness tests. + * + * @note The random value returned is not a cryptographically secure + * random number value. + * + * @return 8-bit random value. + */ +static inline uint8_t sys_rand8_get(void) +{ + uint8_t ret; + + sys_rand_get(&ret, sizeof(ret)); + + return ret; +} + +/** + * @brief Return a 16-bit random value that should pass general + * randomness tests. + * + * @note The random value returned is not a cryptographically secure + * random number value. + * + * @return 16-bit random value. + */ +static inline uint16_t sys_rand16_get(void) +{ + uint16_t ret; + + sys_rand_get(&ret, sizeof(ret)); + + return ret; +} + /** * @brief Return a 32-bit random value that should pass general * randomness tests. @@ -85,6 +121,23 @@ static inline uint32_t sys_rand32_get(void) return ret; } +/** + * @brief Return a 64-bit random value that should pass general + * randomness tests. + * + * @note The random value returned is not a cryptographically secure + * random number value. + * + * @return 64-bit random value. + */ +static inline uint64_t sys_rand64_get(void) +{ + uint64_t ret; + + sys_rand_get(&ret, sizeof(ret)); + + return ret; +} #ifdef __cplusplus } From d8b368a1609534a2ccb6e22cfd8b6607d1e500b2 Mon Sep 17 00:00:00 2001 From: Patryk Kuniecki Date: Tue, 19 Mar 2024 12:25:03 +0100 Subject: [PATCH 1764/2402] scripts: tests: twister_blackbox: Add test_ignore_platform_key Add new tests to test_filter.py in blackbox twister testing Signed-off-by: Patryk Kuniecki --- .../tests/platform_key/dummy/CMakeLists.txt | 8 +++++ .../tests/platform_key/dummy/prj.conf | 1 + .../tests/platform_key/dummy/src/main.c | 26 ++++++++++++++ .../tests/platform_key/dummy/test_data.yaml | 7 ++++ scripts/tests/twister_blackbox/test_filter.py | 34 +++++++++++++++++++ 5 files changed, 76 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/test_data.yaml diff --git a/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/CMakeLists.txt new file mode 100644 index 00000000000..635c696edf9 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(integration) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/prj.conf new file mode 100644 index 00000000000..9467c292689 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/src/main.c new file mode 100644 index 00000000000..3c250486af6 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/src/main.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + + +ZTEST_SUITE(a1_1_tests, NULL, NULL, NULL, NULL, NULL); + +/** + * @brief Test Asserts + * + * This test verifies various assert macros provided by ztest. + * + */ +ZTEST(a1_1_tests, test_assert) +{ + zassert_true(1, "1 was false"); + zassert_false(0, "0 was true"); + zassert_is_null(NULL, "NULL was not NULL"); + zassert_not_null("foo", "\"foo\" was NULL"); + zassert_equal(1, 1, "1 was not equal to 1"); + zassert_equal_ptr(NULL, NULL, "NULL was not equal to NULL"); +} diff --git a/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/test_data.yaml new file mode 100644 index 00000000000..9da823b395c --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/platform_key/dummy/test_data.yaml @@ -0,0 +1,7 @@ +tests: + platform_key.dummy: + platform_allow: + - qemu_x86 + - qemu_x86_64 + platform_key: + - simulation diff --git a/scripts/tests/twister_blackbox/test_filter.py b/scripts/tests/twister_blackbox/test_filter.py index ad6c8ee6a67..c622bb7b0ca 100644 --- a/scripts/tests/twister_blackbox/test_filter.py +++ b/scripts/tests/twister_blackbox/test_filter.py @@ -248,3 +248,37 @@ def test_vendor(self, capfd, out_path, vendor, expected): assert re.search(line, err) assert str(sys_exit.value) == '0' + + @pytest.mark.parametrize( + 'flag, expected_test_count', + [ + (['--ignore-platform-key'], 2), + ([], 1) + ], + ids=['ignore_platform_key', 'without ignore_platform_key'] + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_ignore_platform_key(self, out_path, flag, expected_test_count): + test_platforms = ['qemu_x86', 'qemu_x86_64'] + path = os.path.join(TEST_DATA, 'tests', 'platform_key') + args = ['-i', '--outdir', out_path, '-T', path] + \ + flag + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert str(sys_exit.value) == '0' + + assert len(filtered_j) == expected_test_count From 8f17c830edd7a584ec0f9336b22cec4488f92ce4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Mon, 26 Feb 2024 11:59:57 +0100 Subject: [PATCH 1765/2402] doc: generate sitemap.xml MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Generate a sitemap.xml for the documentation. This aims at helping search engines react faster to the addition/removal of new pages. Signed-off-by: Benjamin Cabé --- doc/conf.py | 5 +++++ doc/requirements.txt | 1 + 2 files changed, 6 insertions(+) diff --git a/doc/conf.py b/doc/conf.py index 5af6ce51fce..ff54dd2cc49 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -86,6 +86,7 @@ "zephyr.dtcompatible-role", "zephyr.link-roles", "sphinx_tabs.tabs", + "sphinx_sitemap", "zephyr.warnings_filter", "zephyr.doxyrunner", "zephyr.gh_utils", @@ -351,6 +352,10 @@ copybutton_prompt_text = r"\$ |uart:~\$ " copybutton_prompt_is_regexp = True +# -- Options for sphinx-sitemap ---------------------------------------- + +sitemap_url_scheme = "{link}" + # -- Linkcheck options ---------------------------------------------------- linkcheck_ignore = [ diff --git a/doc/requirements.txt b/doc/requirements.txt index 9655cc6b43a..983a29d2f18 100644 --- a/doc/requirements.txt +++ b/doc/requirements.txt @@ -9,6 +9,7 @@ pygments>=2.9 sphinx-notfound-page sphinx-copybutton sphinx-togglebutton +sphinx-sitemap # YAML validation. Used by zephyr_module. PyYAML>=6.0 From 1ceceabad5012647dac5b9500cef2aadcfee6a5f Mon Sep 17 00:00:00 2001 From: Steve Boylan Date: Mon, 1 Apr 2024 12:11:31 -0400 Subject: [PATCH 1766/2402] dts: bindings: i2c: Correct the I2C reset bit It was RPI_PICO_RESETS_RESET_I2C0, but should be RPI_PICO_RESETS_RESET_I2C1. Fixes: #70959 Signed-off-by: Steve Boylan --- dts/arm/rpi_pico/rp2040.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/arm/rpi_pico/rp2040.dtsi b/dts/arm/rpi_pico/rp2040.dtsi index e04af802277..db7b12ce40b 100644 --- a/dts/arm/rpi_pico/rp2040.dtsi +++ b/dts/arm/rpi_pico/rp2040.dtsi @@ -311,7 +311,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40048000 DT_SIZE_K(4)>; - resets = <&reset RPI_PICO_RESETS_RESET_I2C0>; + resets = <&reset RPI_PICO_RESETS_RESET_I2C1>; clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; interrupts = <24 RPI_PICO_DEFAULT_IRQ_PRIORITY>; interrupt-names = "i2c1"; From 42d928ee931aca1ea41b590195b083924c870777 Mon Sep 17 00:00:00 2001 From: Damian Krolik Date: Fri, 29 Mar 2024 09:55:37 +0100 Subject: [PATCH 1767/2402] drivers: ieee802154: fix configuring CSL IE in ACK The code was assigning a pointer to a scoped buffer to an object outside that scope. This would cause the driver would receive garbage instead of a well-formatted IE and would likely reject the IE. This in turn caused CSL IE not being included in enhanced ACKs (verified with wireshark). Signed-off-by: Damian Krolik --- modules/openthread/platform/radio.c | 27 ++++++++------------------- 1 file changed, 8 insertions(+), 19 deletions(-) diff --git a/modules/openthread/platform/radio.c b/modules/openthread/platform/radio.c index b320d0f476b..0ed9aea4120 100644 --- a/modules/openthread/platform/radio.c +++ b/modules/openthread/platform/radio.c @@ -1277,7 +1277,10 @@ void otPlatRadioSetMacFrameCounterIfLarger(otInstance *aInstance, uint32_t aMacF otError otPlatRadioEnableCsl(otInstance *aInstance, uint32_t aCslPeriod, otShortAddress aShortAddr, const otExtAddress *aExtAddr) { - struct ieee802154_config config = { 0 }; + struct ieee802154_config config; + /* CSL phase will be injected on-the-fly by the driver. */ + struct ieee802154_header_ie header_ie = + IEEE802154_DEFINE_HEADER_IE_CSL_REDUCED(/* phase */ 0, aCslPeriod); int result; ARG_UNUSED(aInstance); @@ -1290,26 +1293,12 @@ otError otPlatRadioEnableCsl(otInstance *aInstance, uint32_t aCslPeriod, otShort if (result) { return OT_ERROR_FAILED; } - config.ack_ie.short_addr = aShortAddr; - config.ack_ie.ext_addr = aExtAddr != NULL ? aExtAddr->m8 : NULL; /* Configure the CSL IE. */ - if (aCslPeriod > 0) { - uint8_t header_ie_buf[OT_IE_HEADER_SIZE + OT_CSL_IE_SIZE] = { - CSL_IE_HEADER_BYTES_LO, - CSL_IE_HEADER_BYTES_HI, - }; - struct ieee802154_header_ie *header_ie = - (struct ieee802154_header_ie *)header_ie_buf; - - /* Write CSL period and leave CSL phase empty as it will be - * injected on-the-fly by the driver. - */ - header_ie->content.csl.reduced.csl_period = sys_cpu_to_le16(aCslPeriod); - config.ack_ie.header_ie = header_ie; - } else { - config.ack_ie.header_ie = NULL; - } + config.ack_ie.header_ie = aCslPeriod > 0 ? &header_ie : NULL; + config.ack_ie.short_addr = aShortAddr; + config.ack_ie.ext_addr = aExtAddr != NULL ? aExtAddr->m8 : NULL; + config.ack_ie.purge_ie = false; result = radio_api->configure(radio_dev, IEEE802154_CONFIG_ENH_ACK_HEADER_IE, &config); From 3c42daee9c1b1898bbbdbaab1f32087339f5fd8c Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Wed, 3 Apr 2024 04:12:59 -0400 Subject: [PATCH 1768/2402] tests: posix: headers: fix undefined ref to zsock_socketpair Update prj.conf so that subsys/net/lib/sockets/socketpair.c is pulled into the build and zsock_socketpair() is properly defined. Signed-off-by: Chris Friedt --- tests/posix/headers/prj.conf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/posix/headers/prj.conf b/tests/posix/headers/prj.conf index e64b889585a..950a7d510ef 100644 --- a/tests/posix/headers/prj.conf +++ b/tests/posix/headers/prj.conf @@ -10,6 +10,9 @@ CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_NET_SOCKETS=y CONFIG_NETWORKING=y +# for socketpair to work +CONFIG_NET_SOCKETPAIR=y + # for when CONFIG_POSIX_API is not selected CONFIG_PTHREAD_IPC=y CONFIG_POSIX_FS=y From 930e03fdfd706d93fbeb9cb4fd059647916c7adc Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Tue, 12 Mar 2024 16:40:34 +0100 Subject: [PATCH 1769/2402] drivers: clock_control: stm32wba: Fix chain loaded applications case In case of chain loaded application with PLL set as the sysclk source, directly exit the init function. This also applies to exit from stop mode and was tested successfully. Signed-off-by: Erwan Gouriou --- drivers/clock_control/clock_stm32_ll_wba.c | 26 +++++++++------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_wba.c b/drivers/clock_control/clock_stm32_ll_wba.c index c11aec07146..9fa5cae9e0f 100644 --- a/drivers/clock_control/clock_stm32_ll_wba.c +++ b/drivers/clock_control/clock_stm32_ll_wba.c @@ -355,19 +355,6 @@ static int set_up_plls(void) int r; uint32_t vco_input_range; - /* - * Case of chain-loaded applications: - * Switch to HSI and disable the PLL before configuration. - * (Switching to HSI makes sure we have a SYSCLK source in - * case we're currently running from the PLL we're about to - * turn off and reconfigure.) - * - */ - if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R) { - LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); - stm32_clock_switch_to_hsi(); - } - LL_RCC_PLL1_Disable(); /* Configure PLL source */ @@ -511,11 +498,20 @@ int stm32_clock_control_init(const struct device *dev) ARG_UNUSED(dev); + if (IS_ENABLED(STM32_SYSCLK_SRC_PLL) && + (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R)) { + /* In case of chainloaded application, it may happen that PLL + * was already configured as sysclk src by bootloader. + * Don't test other cases as there are multiple options but + * they will be handled smoothly by the function. + */ + SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; + return 0; + } + old_flash_freq = RCC_CALC_FLASH_FREQ(HAL_RCC_GetSysClockFreq(), GET_CURRENT_FLASH_PRESCALER()); - - /* Set up individual enabled clocks */ set_up_fixed_clock_sources(); From fa4ab81f4020773703344a4999c3be6e974e4ada Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Wed, 13 Mar 2024 17:22:51 +0100 Subject: [PATCH 1770/2402] drivers: clocks_control: stm32wba: Fix erratum 2.2.4 Cf Errata sheet, 2.2.4: With HSE active, switching the system clock source from any other source to HSI, spuriously deactivates HSE. Signed-off-by: Erwan Gouriou --- drivers/clock_control/clock_stm32_ll_wba.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clock_control/clock_stm32_ll_wba.c b/drivers/clock_control/clock_stm32_ll_wba.c index 9fa5cae9e0f..17857c0e7ca 100644 --- a/drivers/clock_control/clock_stm32_ll_wba.c +++ b/drivers/clock_control/clock_stm32_ll_wba.c @@ -346,6 +346,22 @@ static void stm32_clock_switch_to_hsi(void) LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI); while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) { } + + /* Erratum 2.2.4: Spurious deactivation of HSE when HSI is selected as + * system clock source + * Re-enable HSE clock if required after switch source to HSI + */ + if (IS_ENABLED(STM32_HSE_ENABLED)) { + if (IS_ENABLED(STM32_HSE_DIV2)) { + LL_RCC_HSE_EnablePrescaler(); + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1) { + /* Wait for HSE ready */ + } + } } __unused From e410e2b7400484f0d667912d58ee65697e4938af Mon Sep 17 00:00:00 2001 From: Robert Zieba Date: Tue, 19 Mar 2024 14:17:13 -0600 Subject: [PATCH 1771/2402] gdbstub: Make loop enum public Make the current gdb loop enum public under the name `gdb_loop_state`. This will allow for extending the current stub with further functionality in the future as new features will require control over the loop state. Signed-off-by: Robert Zieba --- include/zephyr/debug/gdbstub.h | 9 +++++++++ subsys/debug/gdbstub.c | 23 +++++++++-------------- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/include/zephyr/debug/gdbstub.h b/include/zephyr/debug/gdbstub.h index 7ab333b89ef..8f29b1fa736 100644 --- a/include/zephyr/debug/gdbstub.h +++ b/include/zephyr/debug/gdbstub.h @@ -41,6 +41,15 @@ struct gdb_mem_region { uint8_t alignment; }; +/** + * State of the packet processing loop + */ +enum gdb_loop_state { + GDB_LOOP_RECEIVING, + GDB_LOOP_CONTINUE, + GDB_LOOP_ERROR, +}; + /** * Memory region descriptions used for GDB memory access. * diff --git a/subsys/debug/gdbstub.c b/subsys/debug/gdbstub.c index 849d791b2c2..1999c42ef88 100644 --- a/subsys/debug/gdbstub.c +++ b/subsys/debug/gdbstub.c @@ -595,14 +595,9 @@ int z_gdb_main_loop(struct gdb_ctx *ctx) * not have enough space. */ static uint8_t buf[GDB_PACKET_SIZE]; + enum gdb_loop_state state; - enum loop_state { - RECEIVING, - CONTINUE, - ERROR, - } state; - - state = RECEIVING; + state = GDB_LOOP_RECEIVING; /* Only send exception if this is not the first * GDB break. @@ -616,7 +611,7 @@ int z_gdb_main_loop(struct gdb_ctx *ctx) #define CHECK_ERROR(condition) \ { \ if ((condition)) { \ - state = ERROR; \ + state = GDB_LOOP_ERROR; \ break; \ } \ } @@ -633,7 +628,7 @@ int z_gdb_main_loop(struct gdb_ctx *ctx) CHECK_ERROR(ptr == NULL); \ } - while (state == RECEIVING) { + while (state == GDB_LOOP_RECEIVING) { uint8_t *ptr; size_t data_len, pkt_len; uintptr_t addr; @@ -718,7 +713,7 @@ int z_gdb_main_loop(struct gdb_ctx *ctx) */ case 'c': arch_gdb_continue(); - state = CONTINUE; + state = GDB_LOOP_CONTINUE; break; /* @@ -727,7 +722,7 @@ int z_gdb_main_loop(struct gdb_ctx *ctx) */ case 's': arch_gdb_step(); - state = CONTINUE; + state = GDB_LOOP_CONTINUE; break; /* @@ -800,7 +795,7 @@ int z_gdb_main_loop(struct gdb_ctx *ctx) /* breakpoint/watchpoint not supported */ gdb_send_packet(NULL, 0); } else if (ret == -1) { - state = ERROR; + state = GDB_LOOP_ERROR; } else { gdb_send_packet("OK", 2); } @@ -826,9 +821,9 @@ int z_gdb_main_loop(struct gdb_ctx *ctx) * If this is an recoverable error, send an error message to * GDB and continue the debugging session. */ - if (state == ERROR) { + if (state == GDB_LOOP_ERROR) { gdb_send_packet(GDB_ERROR_GENERAL, 3); - state = RECEIVING; + state = GDB_LOOP_RECEIVING; } } From 43cb0572e9adb05c6985225a0742db3da0509a42 Mon Sep 17 00:00:00 2001 From: Robert Zieba Date: Thu, 7 Mar 2024 08:23:33 -0700 Subject: [PATCH 1772/2402] gdbstub: Add q-packet handling function Add `gdb_q_packet` function to handle proccessing of query packets. Also add `gdb_qsupported` function to serve as a single place to process and respond to `qSupported` packets. Signed-off-by: Robert Zieba --- subsys/debug/gdbstub.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/subsys/debug/gdbstub.c b/subsys/debug/gdbstub.c index 1999c42ef88..6ff749e1cf9 100644 --- a/subsys/debug/gdbstub.c +++ b/subsys/debug/gdbstub.c @@ -585,6 +585,28 @@ static int gdb_send_exception(uint8_t *buf, size_t len, uint8_t exception) return gdb_send_packet(buf, size); } +static bool gdb_qsupported(uint8_t *buf, size_t len, enum gdb_loop_state *next_state) +{ + size_t n = 0; + const char *c_buf = (const char *) buf; + + if (strstr(buf, "qSupported") != c_buf) { + return false; + } + + gdb_send_packet(buf, n); + return true; +} + +static void gdb_q_packet(uint8_t *buf, size_t len, enum gdb_loop_state *next_state) +{ + if (gdb_qsupported(buf, len, next_state)) { + return; + } + + gdb_send_packet(NULL, 0); +} + /** * Synchronously communicate with gdb on the host */ @@ -809,6 +831,13 @@ int z_gdb_main_loop(struct gdb_ctx *ctx) ctx->exception); break; + /* Query packets*/ + case 'q': + __fallthrough; + case 'Q': + gdb_q_packet(buf, sizeof(buf), &state); + break; + /* * Not supported action */ From d012f280c79c4bcf6ce6b5fc876092e3d3b37f06 Mon Sep 17 00:00:00 2001 From: Robert Zieba Date: Wed, 20 Mar 2024 16:29:39 -0600 Subject: [PATCH 1773/2402] gdbstub: Add v-packet handling function Add `gdb_v_packet` function as a central location to handle processing of v-packets. Signed-off-by: Robert Zieba --- subsys/debug/gdbstub.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/subsys/debug/gdbstub.c b/subsys/debug/gdbstub.c index 6ff749e1cf9..bb07d0575e5 100644 --- a/subsys/debug/gdbstub.c +++ b/subsys/debug/gdbstub.c @@ -607,6 +607,11 @@ static void gdb_q_packet(uint8_t *buf, size_t len, enum gdb_loop_state *next_sta gdb_send_packet(NULL, 0); } +static void gdb_v_packet(uint8_t *buf, size_t len, enum gdb_loop_state *next_state) +{ + gdb_send_packet(NULL, 0); +} + /** * Synchronously communicate with gdb on the host */ @@ -838,6 +843,11 @@ int z_gdb_main_loop(struct gdb_ctx *ctx) gdb_q_packet(buf, sizeof(buf), &state); break; + /* v packets */ + case 'v': + gdb_v_packet(buf, sizeof(buf), &state); + break; + /* * Not supported action */ From ccc58b8ce54505e11eee28914dac1821143b6b98 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Sun, 31 Mar 2024 04:34:16 +0200 Subject: [PATCH 1774/2402] net: lwm2m: device object: Fix coverage compatibility Starting with b1d24e425c3a30cdf1aed3c54c25a2518061accc (net: lwm2m: device object: optionally store error list in settings), it was no longer possible to build the code with coverage enabled when the settings subsystem was disabled. The build would fail with an error like this: > subsys/net/lib/lwm2m/lwm2m_obj_device.c:262: undefined reference to > `settings_name_steq' This fixes #70923. Signed-off-by: Reto Schneider --- subsys/net/lib/lwm2m/lwm2m_obj_device.c | 45 +++++++++++++------------ 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/subsys/net/lib/lwm2m/lwm2m_obj_device.c b/subsys/net/lib/lwm2m/lwm2m_obj_device.c index c4abb72d506..30b3beaca66 100644 --- a/subsys/net/lib/lwm2m/lwm2m_obj_device.c +++ b/subsys/net/lib/lwm2m/lwm2m_obj_device.c @@ -259,32 +259,35 @@ static int lwm2m_obj_device_settings_set(const char *name, size_t len, int rc; int i; - if (settings_name_steq(name, ERROR_LIST_KEY, &next) && !next) { - if (len > sizeof(error_code_list)) { - LOG_ERR("Error code list too large: %zu", len); - return -EINVAL; - } + if (IS_ENABLED(CONFIG_LWM2M_DEVICE_ERROR_CODE_SETTINGS)) { + if (settings_name_steq(name, ERROR_LIST_KEY, &next) && !next) { + if (len > sizeof(error_code_list)) { + LOG_ERR("Error code list too large: %zu", len); + return -EINVAL; + } - rc = read_cb(cb_arg, error_code_list, sizeof(error_code_list)); - if (rc == 0) { - reset_error_list(); - return 0; - } else if (rc > 0) { - for (i = 0; i < ARRAY_SIZE(error_code_list); i++) { - if (i < rc) { - error_code_ri[i].res_inst_id = i; - } else { - /* Reset remaining error code instances */ - error_code_list[i] = LWM2M_DEVICE_ERROR_NONE; - error_code_ri[i].res_inst_id = RES_INSTANCE_NOT_CREATED; + rc = read_cb(cb_arg, error_code_list, sizeof(error_code_list)); + if (rc == 0) { + reset_error_list(); + return 0; + } else if (rc > 0) { + for (i = 0; i < ARRAY_SIZE(error_code_list); i++) { + if (i < rc) { + error_code_ri[i].res_inst_id = i; + } else { + /* Reset remaining error code instances */ + error_code_list[i] = LWM2M_DEVICE_ERROR_NONE; + error_code_ri[i].res_inst_id = + RES_INSTANCE_NOT_CREATED; + } } + return 0; } - return 0; - } - LOG_ERR("Error code list read failure: %d", rc); + LOG_ERR("Error code list read failure: %d", rc); - return rc; + return rc; + } } return -ENOENT; From eff03ca071c4fcc241dce90eb35c42234f204a64 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 1 Apr 2024 09:52:23 +0300 Subject: [PATCH 1775/2402] net: shell: Add printout when hostname changes Add hostname changed printout to event monitor. As the name says, it is generated when the hostname of the device changes. Signed-off-by: Jukka Rissanen --- subsys/net/lib/shell/events.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/subsys/net/lib/shell/events.c b/subsys/net/lib/shell/events.c index 32edca8b24b..b7c1651cb17 100644 --- a/subsys/net/lib/shell/events.c +++ b/subsys/net/lib/shell/events.c @@ -252,6 +252,9 @@ static const char *get_l4_desc(uint32_t event) case NET_EVENT_DNS_SERVER_DEL: desc = "DNS server del"; break; + case NET_EVENT_HOSTNAME_CHANGED: + desc = "Hostname changed"; + break; case NET_EVENT_COAP_SERVICE_STARTED: desc = "CoAP service started"; break; From 68a7057513a4f6d8aef2ca56bc0a5d7bb2732aa6 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Sun, 31 Mar 2024 20:42:52 +0300 Subject: [PATCH 1776/2402] soc: nxp: imxrt: Prepare imxrt6xx soc for AMP support imxrt6xx are dual core devices featuring an ARM Cortex-M33 core and an Cadence Xtensa HIFI4 Audio DSP. Currently only m33 core is supported. In order to support the Cadence DSP we need first to do some code-reorganization for m33. We start by moving all cm33 related code to its own directory and introduce the cpuclusters property in soc.yml file. Signed-off-by: Daniel Baluta --- boards/deprecated.cmake | 2 +- boards/nxp/mimxrt685_evk/doc/index.rst | 4 +-- boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml | 2 +- samples/sensor/fxos8700/README.rst | 2 +- samples/sensor/fxos8700/sample.yaml | 4 +-- samples/sensor/lps22hh_i3c/README.rst | 2 +- samples/sensor/lsm6dso_i2c_on_i3c/README.rst | 2 +- samples/subsys/fs/littlefs/sample.yaml | 2 +- soc/nxp/imxrt/imxrt6xx/CMakeLists.txt | 23 +++------------- soc/nxp/imxrt/imxrt6xx/cm33/CMakeLists.txt | 26 +++++++++++++++++++ .../imxrt6xx/{ => cm33}/flash_clock_setup.c | 0 .../imxrt6xx/{ => cm33}/flash_clock_setup.h | 0 soc/nxp/imxrt/imxrt6xx/{ => cm33}/power.c | 0 soc/nxp/imxrt/imxrt6xx/{ => cm33}/soc.c | 0 soc/nxp/imxrt/imxrt6xx/{ => cm33}/soc.h | 0 soc/nxp/imxrt/soc.yml | 2 ++ tests/boot/test_mcuboot/testcase.yaml | 2 +- tests/drivers/build_all/pwm/testcase.yaml | 2 +- .../counter/counter_basic_api/testcase.yaml | 2 +- tests/drivers/i2s/i2s_api/testcase.yaml | 4 +-- tests/drivers/regulator/voltage/testcase.yaml | 2 +- 21 files changed, 47 insertions(+), 36 deletions(-) create mode 100644 soc/nxp/imxrt/imxrt6xx/cm33/CMakeLists.txt rename soc/nxp/imxrt/imxrt6xx/{ => cm33}/flash_clock_setup.c (100%) rename soc/nxp/imxrt/imxrt6xx/{ => cm33}/flash_clock_setup.h (100%) rename soc/nxp/imxrt/imxrt6xx/{ => cm33}/power.c (100%) rename soc/nxp/imxrt/imxrt6xx/{ => cm33}/soc.c (100%) rename soc/nxp/imxrt/imxrt6xx/{ => cm33}/soc.h (100%) diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 8887b1b2749..e3812e10261 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -384,7 +384,7 @@ set(mimxrt595_evk_cm33_DEPRECATED mimxrt595_evk/mimxrt595s/cm33 ) set(mimxrt685_evk_cm33_DEPRECATED - mimxrt685_evk + mimxrt685_evk/mimxrt685s/cm33 ) set(mps2_an385_DEPRECATED mps2/an385 diff --git a/boards/nxp/mimxrt685_evk/doc/index.rst b/boards/nxp/mimxrt685_evk/doc/index.rst index daed053fcb2..109dfde16e6 100644 --- a/boards/nxp/mimxrt685_evk/doc/index.rst +++ b/boards/nxp/mimxrt685_evk/doc/index.rst @@ -290,7 +290,7 @@ Here is an example for the :ref:`hello_world` application. This example uses the .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: mimxrt685_evk + :board: mimxrt685_evk/mimxrt685s/cm33 :goals: flash Open a serial terminal, reset the board (press the RESET button), and you should @@ -309,7 +309,7 @@ Here is an example for the :ref:`hello_world` application. This example uses the .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: mimxrt685_evk + :board: mimxrt685_evk/mimxrt685s/cm33 :goals: debug Open a serial terminal, step through the application in your debugger, and you diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml b/boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml index 53f260fc60e..22ab15ecfd9 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: mimxrt685_evk +identifier: mimxrt685_evk/mimxrt685s/cm33 name: NXP MIMXRT685-EVK type: mcu arch: arm diff --git a/samples/sensor/fxos8700/README.rst b/samples/sensor/fxos8700/README.rst index 0c0fa8af66a..3bd1aade447 100644 --- a/samples/sensor/fxos8700/README.rst +++ b/samples/sensor/fxos8700/README.rst @@ -117,7 +117,7 @@ Sample can be built and executed for the MIMXRT685-EVK as follows: .. zephyr-app-commands:: :zephyr-app: samples/sensor/fxos8700 - :board: mimxrt685_evk + :board: mimxrt685_evk/mimxrt685s/cm33 :goals: build flash :compact: diff --git a/samples/sensor/fxos8700/sample.yaml b/samples/sensor/fxos8700/sample.yaml index 29215833f63..dbdfe23f9d0 100644 --- a/samples/sensor/fxos8700/sample.yaml +++ b/samples/sensor/fxos8700/sample.yaml @@ -16,7 +16,7 @@ tests: - rv32m1_vega/openisa_rv32m1/ri5cy - twr_ke18f - lpcxpresso55s16 - - mimxrt685_evk + - mimxrt685_evk/mimxrt685s/cm33 - frdm_k22f - mimxrt1024_evk - mimxrt595_evk/mimxrt595s/cm33 @@ -34,7 +34,7 @@ tests: - bbc_microbit - lpcxpresso55s69/lpc55s69/cpu0 - reel_board - - mimxrt685_evk + - mimxrt685_evk/mimxrt685s/cm33 - mimxrt595_evk/mimxrt595s/cm33 integration_platforms: - bbc_microbit diff --git a/samples/sensor/lps22hh_i3c/README.rst b/samples/sensor/lps22hh_i3c/README.rst index 5e8b1d4dff5..8b96ab51fbe 100644 --- a/samples/sensor/lps22hh_i3c/README.rst +++ b/samples/sensor/lps22hh_i3c/README.rst @@ -43,7 +43,7 @@ Building on mimxrt685_evk board .. zephyr-app-commands:: :zephyr-app: samples/sensor/lps22hh_i3c :host-os: unix - :board: mimxrt685_evk + :board: mimxrt685_evk/mimxrt685s/cm33 :goals: build :compact: diff --git a/samples/sensor/lsm6dso_i2c_on_i3c/README.rst b/samples/sensor/lsm6dso_i2c_on_i3c/README.rst index 872d244364b..4764608bcba 100644 --- a/samples/sensor/lsm6dso_i2c_on_i3c/README.rst +++ b/samples/sensor/lsm6dso_i2c_on_i3c/README.rst @@ -34,7 +34,7 @@ Building on mimxrt685_evk board .. zephyr-app-commands:: :zephyr-app: samples/sensor/lsm6dso_i2c_on_i3c :host-os: unix - :board: mimxrt685_evk + :board: mimxrt685_evk/mimxrt685s/cm33 :goals: build :compact: diff --git a/samples/subsys/fs/littlefs/sample.yaml b/samples/subsys/fs/littlefs/sample.yaml index 183b582e400..b78a070f1c9 100644 --- a/samples/subsys/fs/littlefs/sample.yaml +++ b/samples/subsys/fs/littlefs/sample.yaml @@ -11,7 +11,7 @@ tests: - nrf52840dk/nrf52840 - particle_xenon - disco_l475_iot1 - - mimxrt685_evk + - mimxrt685_evk/mimxrt685s/cm33 - mimxrt1060_evk - mimxrt1064_evk - qemu_x86 diff --git a/soc/nxp/imxrt/imxrt6xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt6xx/CMakeLists.txt index 7ed2c42c708..d6d242f3c9c 100644 --- a/soc/nxp/imxrt/imxrt6xx/CMakeLists.txt +++ b/soc/nxp/imxrt/imxrt6xx/CMakeLists.txt @@ -1,26 +1,9 @@ # -# Copyright (c) 2020, NXP +# Copyright 2024 NXP # # SPDX-License-Identifier: Apache-2.0 # -zephyr_include_directories(.) - -zephyr_sources(soc.c) - -zephyr_sources_ifdef(CONFIG_PM power.c) - -zephyr_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_XIP flash_clock_setup.c) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) - -zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) - -if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) - zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM) +if(CONFIG_SOC_MIMXRT685S_CM33) + add_subdirectory(cm33) endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imxrt/imxrt6xx/cm33/CMakeLists.txt b/soc/nxp/imxrt/imxrt6xx/cm33/CMakeLists.txt new file mode 100644 index 00000000000..7ed2c42c708 --- /dev/null +++ b/soc/nxp/imxrt/imxrt6xx/cm33/CMakeLists.txt @@ -0,0 +1,26 @@ +# +# Copyright (c) 2020, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(.) + +zephyr_sources(soc.c) + +zephyr_sources_ifdef(CONFIG_PM power.c) + +zephyr_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_XIP flash_clock_setup.c) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) + +zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) + +if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) + zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM) +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imxrt/imxrt6xx/flash_clock_setup.c b/soc/nxp/imxrt/imxrt6xx/cm33/flash_clock_setup.c similarity index 100% rename from soc/nxp/imxrt/imxrt6xx/flash_clock_setup.c rename to soc/nxp/imxrt/imxrt6xx/cm33/flash_clock_setup.c diff --git a/soc/nxp/imxrt/imxrt6xx/flash_clock_setup.h b/soc/nxp/imxrt/imxrt6xx/cm33/flash_clock_setup.h similarity index 100% rename from soc/nxp/imxrt/imxrt6xx/flash_clock_setup.h rename to soc/nxp/imxrt/imxrt6xx/cm33/flash_clock_setup.h diff --git a/soc/nxp/imxrt/imxrt6xx/power.c b/soc/nxp/imxrt/imxrt6xx/cm33/power.c similarity index 100% rename from soc/nxp/imxrt/imxrt6xx/power.c rename to soc/nxp/imxrt/imxrt6xx/cm33/power.c diff --git a/soc/nxp/imxrt/imxrt6xx/soc.c b/soc/nxp/imxrt/imxrt6xx/cm33/soc.c similarity index 100% rename from soc/nxp/imxrt/imxrt6xx/soc.c rename to soc/nxp/imxrt/imxrt6xx/cm33/soc.c diff --git a/soc/nxp/imxrt/imxrt6xx/soc.h b/soc/nxp/imxrt/imxrt6xx/cm33/soc.h similarity index 100% rename from soc/nxp/imxrt/imxrt6xx/soc.h rename to soc/nxp/imxrt/imxrt6xx/cm33/soc.h diff --git a/soc/nxp/imxrt/soc.yml b/soc/nxp/imxrt/soc.yml index 319d5b947e2..82a6a35e74a 100644 --- a/soc/nxp/imxrt/soc.yml +++ b/soc/nxp/imxrt/soc.yml @@ -32,3 +32,5 @@ family: - name: imxrt6xx socs: - name: mimxrt685s + cpuclusters: + - name: cm33 diff --git a/tests/boot/test_mcuboot/testcase.yaml b/tests/boot/test_mcuboot/testcase.yaml index 6669dc5efdb..f30581262a2 100644 --- a/tests/boot/test_mcuboot/testcase.yaml +++ b/tests/boot/test_mcuboot/testcase.yaml @@ -32,7 +32,7 @@ tests: - mimxrt1160_evk/mimxrt1166/cm7 - mimxrt1170_evk/mimxrt1176/cm7 - mimxrt595_evk/mimxrt595s/cm33 - - mimxrt685_evk + - mimxrt685_evk/mimxrt685s/cm33 - nrf52840dk/nrf52840 integration_platforms: - frdm_k64f diff --git a/tests/drivers/build_all/pwm/testcase.yaml b/tests/drivers/build_all/pwm/testcase.yaml index 3bcb57b6100..6aca27aabcd 100644 --- a/tests/drivers/build_all/pwm/testcase.yaml +++ b/tests/drivers/build_all/pwm/testcase.yaml @@ -23,7 +23,7 @@ tests: drivers.pwm.mcux.build: platform_allow: mimxrt1064_evk drivers.pwm.mcux.sctimer.build: - platform_allow: mimxrt685_evk + platform_allow: mimxrt685_evk/mimxrt685s/cm33 drivers.pwm.rv32m1.tpm.build: platform_allow: rv32m1_vega/openisa_rv32m1/ri5cy drivers.pwm.sifive.build: diff --git a/tests/drivers/counter/counter_basic_api/testcase.yaml b/tests/drivers/counter/counter_basic_api/testcase.yaml index 3b9098e47e2..482fc9c54eb 100644 --- a/tests/drivers/counter/counter_basic_api/testcase.yaml +++ b/tests/drivers/counter/counter_basic_api/testcase.yaml @@ -34,7 +34,7 @@ tests: - drivers - counter depends_on: counter - platform_allow: mimxrt685_evk + platform_allow: mimxrt685_evk/mimxrt685s/cm33 timeout: 400 extra_args: DTC_OVERLAY_FILE="boards/mimxrt685_evk_rtc_1khz.overlay" diff --git a/tests/drivers/i2s/i2s_api/testcase.yaml b/tests/drivers/i2s/i2s_api/testcase.yaml index 84a1d2bede9..b039b413585 100644 --- a/tests/drivers/i2s/i2s_api/testcase.yaml +++ b/tests/drivers/i2s/i2s_api/testcase.yaml @@ -7,7 +7,7 @@ tests: filter: not CONFIG_I2S_TEST_USE_GPIO_LOOPBACK platform_exclude: - mimxrt595_evk/mimxrt595s/cm33 - - mimxrt685_evk + - mimxrt685_evk/mimxrt685s/cm33 drivers.i2s.gpio_loopback: depends_on: - i2s @@ -19,6 +19,6 @@ tests: harness: ztest platform_exclude: - mimxrt595_evk/mimxrt595s/cm33 - - mimxrt685_evk + - mimxrt685_evk/mimxrt685s/cm33 harness_config: fixture: gpio_loopback diff --git a/tests/drivers/regulator/voltage/testcase.yaml b/tests/drivers/regulator/voltage/testcase.yaml index 19dac317421..e9137c17a24 100644 --- a/tests/drivers/regulator/voltage/testcase.yaml +++ b/tests/drivers/regulator/voltage/testcase.yaml @@ -17,7 +17,7 @@ tests: fixture: npm6001_ek_to_adc drivers.regulator.voltage.nxp: platform_allow: - - mimxrt685_evk + - mimxrt685_evk/mimxrt685s/cm33 - lpcxpresso55s36 harness_config: fixture: gpio_loopback From cffea52fa8ecfd81f6c8568101170fb6827cd3d4 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Mon, 1 Apr 2024 13:49:14 +0300 Subject: [PATCH 1777/2402] boards: nxp: Rename mimxrt685_evk to mimxrt685_evk_mimxrt685s_cm33 In preparation for adding AMP support for i.MX RT6xx family we need to rename existing cm33 support files to more specific names. e.g mimxrt685_evk.dts -> mimxrt685_evk_mimxrt685s_cm33.dts This will allow us to later add support for Cadence DSP found on i.MX RT6xx series. Signed-off-by: Daniel Baluta --- boards/nxp/mimxrt685_evk/CMakeLists.txt | 4 +++- boards/nxp/mimxrt685_evk/Kconfig.defconfig | 4 ++-- boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk | 1 + ...{mimxrt685_evk.dts => mimxrt685_evk_mimxrt685s_cm33.dts} | 0 ...imxrt685_evk.yaml => mimxrt685_evk_mimxrt685s_cm33.yaml} | 0 ...vk_defconfig => mimxrt685_evk_mimxrt685s_cm33_defconfig} | 0 soc/nxp/imxrt/imxrt6xx/Kconfig | 2 +- soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig | 6 +++++- soc/nxp/imxrt/imxrt6xx/Kconfig.soc | 6 +++++- 9 files changed, 17 insertions(+), 6 deletions(-) rename boards/nxp/mimxrt685_evk/{mimxrt685_evk.dts => mimxrt685_evk_mimxrt685s_cm33.dts} (100%) rename boards/nxp/mimxrt685_evk/{mimxrt685_evk.yaml => mimxrt685_evk_mimxrt685s_cm33.yaml} (100%) rename boards/nxp/mimxrt685_evk/{mimxrt685_evk_defconfig => mimxrt685_evk_mimxrt685s_cm33_defconfig} (100%) diff --git a/boards/nxp/mimxrt685_evk/CMakeLists.txt b/boards/nxp/mimxrt685_evk/CMakeLists.txt index 39c978f14cc..c08b123bdc1 100644 --- a/boards/nxp/mimxrt685_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt685_evk/CMakeLists.txt @@ -4,11 +4,13 @@ # SPDX-License-Identifier: Apache-2.0 # +if(CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_CM33) zephyr_library() zephyr_library_sources(init.c) +endif() if(CONFIG_NXP_IMXRT_BOOT_HEADER) - if(NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK) + if(NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_CM33) message(WARNING "It appears you are using the board definition for " "the MIMXRT685-EVK, but targeting a custom board. You may need to " "update your flash configuration block data") diff --git a/boards/nxp/mimxrt685_evk/Kconfig.defconfig b/boards/nxp/mimxrt685_evk/Kconfig.defconfig index 8fbc681e052..02a69187a24 100644 --- a/boards/nxp/mimxrt685_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt685_evk/Kconfig.defconfig @@ -3,7 +3,7 @@ # Copyright 2020, 2024 NXP # SPDX-License-Identifier: Apache-2.0 -if BOARD_MIMXRT685_EVK +if BOARD_MIMXRT685_EVK_MIMXRT685S_CM33 config NXP_IMXRT_BOOT_HEADER default y if !BOOTLOADER_MCUBOOT @@ -26,4 +26,4 @@ config FXOS8700_DRDY_INT1 default y depends on FXOS8700_TRIGGER -endif # BOARD_MIMXRT685_EVK +endif # BOARD_MIMXRT685_EVK_MIMXRT685S_CM33 diff --git a/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk b/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk index d87399aebd7..a324f1157ea 100644 --- a/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk +++ b/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk @@ -3,3 +3,4 @@ config BOARD_MIMXRT685_EVK select SOC_PART_NUMBER_MIMXRT685SFVKB + select SOC_MIMXRT685S_CM33 if BOARD_MIMXRT685_EVK_MIMXRT685S_CM33 diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts similarity index 100% rename from boards/nxp/mimxrt685_evk/mimxrt685_evk.dts rename to boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml similarity index 100% rename from boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml rename to boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_defconfig b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33_defconfig similarity index 100% rename from boards/nxp/mimxrt685_evk/mimxrt685_evk_defconfig rename to boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33_defconfig diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig b/soc/nxp/imxrt/imxrt6xx/Kconfig index eeeb3ab7af4..48a8d4c2b5a 100644 --- a/soc/nxp/imxrt/imxrt6xx/Kconfig +++ b/soc/nxp/imxrt/imxrt6xx/Kconfig @@ -1,7 +1,7 @@ # Copyright 2020, 2024 NXP # SPDX-License-Identifier: Apache-2.0 -config SOC_SERIES_IMXRT6XX +config SOC_MIMXRT685S_CM33 select ARM select CPU_CORTEX_M33 select CPU_CORTEX_M_HAS_DWT diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig index 2133577418d..83d9604f2ba 100644 --- a/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig +++ b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig @@ -15,6 +15,10 @@ config SOC_SERIES_IMXRT_6XX bool default y +endif # SOC_SERIES_MIMXRT6XX + +if SOC_MIMXRT685S_CM33 + config ROM_START_OFFSET default 0x1200 if NXP_IMXRT_BOOT_HEADER @@ -110,4 +114,4 @@ choice USB_MCUX_CONTROLLER_TYPE default USB_DC_NXP_LPCIP3511 endchoice -endif # SOC_SERIES_MIMXRT6XX +endif # SOC_MIMXRT685S_CM33 diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig.soc b/soc/nxp/imxrt/imxrt6xx/Kconfig.soc index 14cb945b36e..57d2c2285bb 100644 --- a/soc/nxp/imxrt/imxrt6xx/Kconfig.soc +++ b/soc/nxp/imxrt/imxrt6xx/Kconfig.soc @@ -8,10 +8,14 @@ config SOC_SERIES_IMXRT6XX config SOC_SERIES default "imxrt6xx" if SOC_SERIES_IMXRT6XX -config SOC_MIMXRT685S_CM33 +config SOC_MIMXRT685S bool select SOC_SERIES_IMXRT6XX +config SOC_MIMXRT685S_CM33 + bool + select SOC_MIMXRT685S + config SOC default "mimxrt685s" if SOC_MIMXRT685S_CM33 From 96364d29b7fd1956fced71ace96e6e489d91967c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stine=20=C3=85kredalen?= Date: Mon, 1 Apr 2024 06:45:05 -0700 Subject: [PATCH 1778/2402] doc: Bluetooth: Mesh: Clarify AES usage in DFU metadata MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Added clarification on AES-CMAC usage in DFU metadata, emphasizing its sole role as a hashing function for the incoming composition data hash. Notably, it utilizes a fixed key and is not employed for encryption purposes. Signed-off-by: Stine Åkredalen --- doc/connectivity/bluetooth/api/mesh/dfu.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/connectivity/bluetooth/api/mesh/dfu.rst b/doc/connectivity/bluetooth/api/mesh/dfu.rst index d2bf4ced2ce..127d820ba7e 100644 --- a/doc/connectivity/bluetooth/api/mesh/dfu.rst +++ b/doc/connectivity/bluetooth/api/mesh/dfu.rst @@ -170,6 +170,12 @@ Firmware metadata | | | with a status message. | +------------------------+--------------+----------------------------------------+ + .. note:: + + The AES-CMAC algorithm serves as a hashing function with a fixed key and is not used for + encryption in Bluetooth Mesh DFU metadata. The resulting hash is not secure since the key is + known. + Firmware URI The firmware URI gives the Initiator information about where firmware updates for the image can be found. The URI points to an online resource the Initiator can interact with to get new From 0c138b7d282272e5a7159b92f6b08d8f3de7158b Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Mon, 12 Feb 2024 17:05:02 +0200 Subject: [PATCH 1779/2402] west.yml: update hal_nxp revision Update hal_nxp reivison to pull in the following patches: * mcux: hal_nxp: include HAL ESAI driver if Zephyr ESAI driver is enabled Signed-off-by: Laurentiu Mihalcea --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 1e82f4512c0..a05d5f35aee 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 874ed3b297ba1f21bc6422aed85c3fdba3219de2 + revision: 6b252c34eef7d0fdd2dee8261ab68086522c4435 path: modules/hal/nxp groups: - hal From bd9b3c67b240c6ae5d9de4eb954a01a718534ef9 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Thu, 8 Feb 2024 17:25:52 +0200 Subject: [PATCH 1780/2402] drivers: dai: add driver for NXP's ESAI This commit introduces a new DAI driver used for NXP's ESAI IP. Signed-off-by: Laurentiu Mihalcea --- drivers/dai/CMakeLists.txt | 1 + drivers/dai/Kconfig | 1 + drivers/dai/nxp/esai/CMakeLists.txt | 5 + drivers/dai/nxp/esai/Kconfig.esai | 9 + drivers/dai/nxp/esai/esai.c | 766 ++++++++++++++++++++++++++ drivers/dai/nxp/esai/esai.h | 533 ++++++++++++++++++ dts/bindings/dai/nxp,dai-esai.yaml | 75 +++ include/zephyr/dt-bindings/dai/esai.h | 54 ++ 8 files changed, 1444 insertions(+) create mode 100644 drivers/dai/nxp/esai/CMakeLists.txt create mode 100644 drivers/dai/nxp/esai/Kconfig.esai create mode 100644 drivers/dai/nxp/esai/esai.c create mode 100644 drivers/dai/nxp/esai/esai.h create mode 100644 dts/bindings/dai/nxp,dai-esai.yaml create mode 100644 include/zephyr/dt-bindings/dai/esai.h diff --git a/drivers/dai/CMakeLists.txt b/drivers/dai/CMakeLists.txt index b6bd04939d5..506c2a54335 100644 --- a/drivers/dai/CMakeLists.txt +++ b/drivers/dai/CMakeLists.txt @@ -5,3 +5,4 @@ add_subdirectory_ifdef(CONFIG_DAI_INTEL_ALH intel/alh) add_subdirectory_ifdef(CONFIG_DAI_INTEL_DMIC intel/dmic) add_subdirectory_ifdef(CONFIG_DAI_INTEL_HDA intel/hda) add_subdirectory_ifdef(CONFIG_DAI_NXP_SAI nxp/sai) +add_subdirectory_ifdef(CONFIG_DAI_NXP_ESAI nxp/esai) diff --git a/drivers/dai/Kconfig b/drivers/dai/Kconfig index da882a99fa0..05877efd88e 100644 --- a/drivers/dai/Kconfig +++ b/drivers/dai/Kconfig @@ -30,5 +30,6 @@ source "drivers/dai/intel/alh/Kconfig.alh" source "drivers/dai/intel/dmic/Kconfig.dmic" source "drivers/dai/intel/hda/Kconfig.hda" source "drivers/dai/nxp/sai/Kconfig.sai" +source "drivers/dai/nxp/esai/Kconfig.esai" endif # DAI diff --git a/drivers/dai/nxp/esai/CMakeLists.txt b/drivers/dai/nxp/esai/CMakeLists.txt new file mode 100644 index 00000000000..826c8592c18 --- /dev/null +++ b/drivers/dai/nxp/esai/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(esai.c) diff --git a/drivers/dai/nxp/esai/Kconfig.esai b/drivers/dai/nxp/esai/Kconfig.esai new file mode 100644 index 00000000000..99651e8dc9a --- /dev/null +++ b/drivers/dai/nxp/esai/Kconfig.esai @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config DAI_NXP_ESAI + bool "NXP Enhanced Serial Audio Interface (ESAI) driver" + default y + depends on DT_HAS_NXP_DAI_ESAI_ENABLED + help + Select this to enable NXP ESAI driver. diff --git a/drivers/dai/nxp/esai/esai.c b/drivers/dai/nxp/esai/esai.c new file mode 100644 index 00000000000..1d7bea6495e --- /dev/null +++ b/drivers/dai/nxp/esai/esai.c @@ -0,0 +1,766 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esai.h" + +/* TODO: + * 1) Some pin functions can be inferred from software ctx. For instance, + * if you use more than 1 data line, it's obvious you're going + * to want to keep the pins of the data lines in ESAI mode. + * + * 2) Add function for handling underrun/overrun. Preferably + * we should do the same as we did for SAI to ease the testing + * process. This approach will do for now. In the future, this + * can be handled in a more sophisticated maner. + * + * notes: + * 1) EXTAL clock is divided as follows: + * a) Initial EXTAL signal is automatically divided by 2. + * b) If prescaler is enabled the resulting EXTAL from a) + * is divided by 8. + * c) The resulting EXTAL signal from b) can be divided + * by 1 up to 256 (configured via xPM0-xPM7). The resulting + * signal is referred to as HCLK. + * d) HCLK obtained from c) can be further divided by 1 + * up to 16 (configured via xFP0-xFP3). The resulting signal is + * referred to as BCLK. + */ + +static int esai_get_clock_rate_config(uint32_t extal_rate, uint32_t hclk_rate, + uint32_t bclk_rate, bool variable_hclk, + bool allow_bclk_configuration, + struct esai_transceiver_config *cfg) +{ + uint32_t hclk_div_ratio, bclk_div_ratio; + + /* sanity checks */ + if (!cfg) { + LOG_ERR("got NULL clock configuration"); + return -EINVAL; + } + + if (!extal_rate || !hclk_rate || !bclk_rate) { + LOG_ERR("got NULL clock rate"); + return -EINVAL; + } + + if (hclk_rate > extal_rate) { + LOG_ERR("HCLK rate cannot be higher than EXTAL rate"); + return -EINVAL; + } + + if (bclk_rate > extal_rate) { + LOG_ERR("BCLK rate cannot be higher than EXTAL rate"); + return -EINVAL; + } + + if (DIV_ROUND_UP(extal_rate, bclk_rate) > 2 * 8 * 256 * 16) { + LOG_ERR("BCLK rate %u cannot be obtained from EXTAL rate %u", + bclk_rate, extal_rate); + return -EINVAL; + } + + /* TODO: add explanation */ + if (DIV_ROUND_UP(extal_rate / 2, bclk_rate) == 1) { + LOG_ERR("HCLK prescaler bypass with divider bypass is not supported"); + return -EINVAL; + } + + hclk_div_ratio = 1; + bclk_div_ratio = 1; + + /* check if HCLK is in (EXTAL_RATE / 2, EXTAL_RATE). If so, + * return an error as any rates from this interval cannot be obtained. + */ + if (hclk_rate > extal_rate / 2 && hclk_rate < extal_rate) { + LOG_ERR("HCLK rate cannot be higher than EXTAL's rate divided by 2"); + return -EINVAL; + } + + /* compute HCLK configuration - only required if HCLK pad output is used */ + if (!variable_hclk) { + if (extal_rate == hclk_rate) { + /* HCLK rate from pad is the same as EXTAL rate */ + cfg->hclk_bypass = true; + } else { + /* EXTAL is automatically divided by 2 */ + extal_rate /= 2; + + /* compute prescaler divide ratio w/ prescaler bypass */ + hclk_div_ratio = DIV_ROUND_UP(extal_rate, hclk_rate); + + if (hclk_div_ratio > 256) { + /* can't obtain HCLK w/o prescaler */ + cfg->hclk_prescaler_en = true; + + extal_rate /= 8; + + /* recompute ratio w/ prescaler */ + hclk_div_ratio = DIV_ROUND_UP(extal_rate, hclk_rate); + + if (hclk_div_ratio > 256) { + LOG_ERR("cannot obtain HCLK rate %u from EXTAL rate %u", + hclk_rate, extal_rate); + return -EINVAL; + } + } + } + } + + cfg->hclk_div_ratio = hclk_div_ratio; + + if (!allow_bclk_configuration) { + return 0; + } + + extal_rate = DIV_ROUND_UP(extal_rate, hclk_div_ratio); + + /* compute BCLK configuration */ + if (variable_hclk || cfg->hclk_bypass) { + /* attempt to find a configuration that satisfies BCLK's rate */ + extal_rate /= 2; + + hclk_div_ratio = DIV_ROUND_UP(extal_rate, bclk_rate); + + /* check if prescaler is required */ + if (hclk_div_ratio > 256 * 16) { + extal_rate /= 8; + cfg->hclk_prescaler_en = true; + hclk_div_ratio = DIV_ROUND_UP(extal_rate, bclk_rate); + } + + /* check if we really need to loop through TPM div ratios */ + if (hclk_div_ratio < 256) { + cfg->bclk_div_ratio = 1; + cfg->hclk_div_ratio = hclk_div_ratio; + return 0; + } + + for (int i = 1; i < 256; i++) { + hclk_div_ratio = DIV_ROUND_UP(extal_rate / i, bclk_rate); + bclk_div_ratio = DIV_ROUND_UP(extal_rate / hclk_div_ratio, bclk_rate); + + if (bclk_div_ratio <= 16) { + /* found valid configuration, let caller know */ + cfg->bclk_div_ratio = bclk_div_ratio; + cfg->hclk_div_ratio = hclk_div_ratio; + + return 0; + } + } + + /* no valid configuration found */ + LOG_ERR("no valid configuration for BCLK rate %u and EXTAL rate %u", + bclk_rate, extal_rate); + return -EINVAL; + } + + /* can the BCLK rate be obtained w/o modifying divided EXTAL? */ + bclk_div_ratio = DIV_ROUND_UP(extal_rate, bclk_rate); + + if (bclk_div_ratio > 16) { + LOG_ERR("cannot obtain BCLK rate %d from EXTAL rate %d", + bclk_rate, extal_rate); + return -EINVAL; + } + + /* save ratios before returning */ + cfg->bclk_div_ratio = bclk_div_ratio; + cfg->hclk_div_ratio = hclk_div_ratio; + + return 0; +} + +static int esai_get_clk_provider_config(const struct dai_config *cfg, + struct esai_transceiver_config *xceiver_cfg) +{ + switch (cfg->format & DAI_FORMAT_CLOCK_PROVIDER_MASK) { + case DAI_CBC_CFC: + /* default FSYNC and BCLK are OUTPUT */ + break; + case DAI_CBP_CFP: + xceiver_cfg->bclk_dir = kESAI_ClockInput; + xceiver_cfg->fsync_dir = kESAI_ClockInput; + break; + default: + LOG_ERR("invalid clock provider configuration: %d", + cfg->format & DAI_FORMAT_CLOCK_PROVIDER_MASK); + return -EINVAL; + } + + return 0; +} + +static int esai_get_clk_inversion_config(const struct dai_config *cfg, + struct esai_transceiver_config *xceiver_cfg) +{ + switch (cfg->format & DAI_FORMAT_CLOCK_INVERSION_MASK) { + case DAI_INVERSION_IB_IF: + ESAI_INVERT_POLARITY(xceiver_cfg->bclk_polarity); + ESAI_INVERT_POLARITY(xceiver_cfg->fsync_polarity); + break; + case DAI_INVERSION_IB_NF: + ESAI_INVERT_POLARITY(xceiver_cfg->bclk_polarity); + break; + case DAI_INVERSION_NB_IF: + ESAI_INVERT_POLARITY(xceiver_cfg->fsync_polarity); + break; + case DAI_INVERSION_NB_NF: + /* nothing to do here */ + break; + default: + LOG_ERR("invalid clock inversion configuration: %d", + cfg->format & DAI_FORMAT_CLOCK_INVERSION_MASK); + return -EINVAL; + } + + return 0; +} + +static int esai_get_proto_config(const struct dai_config *cfg, + struct esai_transceiver_config *xceiver_cfg) +{ + switch (cfg->format & DAI_FORMAT_PROTOCOL_MASK) { + case DAI_PROTO_I2S: + xceiver_cfg->bclk_polarity = kESAI_ClockActiveLow; + xceiver_cfg->fsync_polarity = kESAI_ClockActiveLow; + break; + case DAI_PROTO_DSP_A: + xceiver_cfg->bclk_polarity = kESAI_ClockActiveLow; + xceiver_cfg->fsync_is_bit_wide = true; + break; + default: + LOG_ERR("invalid DAI protocol: %d", + cfg->format & DAI_FORMAT_PROTOCOL_MASK); + return -EINVAL; + } + return 0; +} + +static int esai_get_slot_format(uint32_t slot_width, uint32_t word_width, + struct esai_transceiver_config *cfg) +{ + /* sanity check */ + if (!ESAI_SLOT_WORD_WIDTH_IS_VALID(slot_width, word_width)) { + LOG_ERR("invalid slot %d word %d width configuration", + slot_width, word_width); + return -EINVAL; + } + + cfg->slot_format = ESAI_SLOT_FORMAT(slot_width, word_width); + + return 0; +} + +static void esai_get_xceiver_default_config(struct esai_transceiver_config *cfg) +{ + memset(cfg, 0, sizeof(*cfg)); + + cfg->hclk_prescaler_en = false; + cfg->hclk_div_ratio = 1; + cfg->bclk_div_ratio = 1; + cfg->hclk_bypass = false; + + cfg->hclk_src = kESAI_HckSourceExternal; + cfg->hclk_dir = kESAI_ClockOutput; + cfg->hclk_polarity = kESAI_ClockActiveHigh; + + cfg->bclk_dir = kESAI_ClockOutput; + cfg->bclk_polarity = kESAI_ClockActiveHigh; + + cfg->fsync_dir = kESAI_ClockOutput; + cfg->fsync_polarity = kESAI_ClockActiveHigh; + + cfg->fsync_is_bit_wide = false; + cfg->zero_pad_en = true; + cfg->fsync_early = true; + + cfg->mode = kESAI_NetworkMode; + cfg->data_order = kESAI_ShifterMSB; + cfg->data_left_aligned = true; +} + +static void esai_commit_config(ESAI_Type *base, + enum dai_dir dir, + struct esai_transceiver_config *cfg) +{ + if (dir == DAI_DIR_TX) { + base->TCCR &= ~(ESAI_TCCR_THCKD_MASK | ESAI_TCCR_TFSD_MASK | + ESAI_TCCR_TCKD_MASK | ESAI_TCCR_THCKP_MASK | + ESAI_TCCR_TFSP_MASK | ESAI_TCCR_TCKP_MASK | + ESAI_TCCR_TFP_MASK | ESAI_TCCR_TDC_MASK | + ESAI_TCCR_TPSR_MASK | ESAI_TCCR_TPM_MASK); + + base->TCCR |= ESAI_TCCR_THCKD(cfg->hclk_dir) | + ESAI_TCCR_TFSD(cfg->fsync_dir) | + ESAI_TCCR_TCKD(cfg->bclk_dir) | + ESAI_TCCR_THCKP(cfg->hclk_polarity) | + ESAI_TCCR_TFSP(cfg->fsync_polarity) | + ESAI_TCCR_TCKP(cfg->bclk_polarity) | + ESAI_TCCR_TFP(cfg->bclk_div_ratio - 1) | + ESAI_TCCR_TDC(cfg->fsync_div - 1) | + ESAI_TCCR_TPSR(!cfg->hclk_prescaler_en) | + ESAI_TCCR_TPM(cfg->hclk_div_ratio - 1); + + base->TCR &= ~(ESAI_TCR_PADC_MASK | ESAI_TCR_TFSR_MASK | + ESAI_TCR_TFSL_MASK | ESAI_TCR_TMOD_MASK | + ESAI_TCR_TWA_MASK | ESAI_TCR_TSHFD_MASK); + + base->TCR |= ESAI_TCR_PADC(cfg->zero_pad_en) | + ESAI_TCR_TFSR(cfg->fsync_early) | + ESAI_TCR_TFSL(cfg->fsync_is_bit_wide) | + ESAI_TCR_TSWS(cfg->slot_format) | + ESAI_TCR_TMOD(cfg->mode) | + ESAI_TCR_TWA(!cfg->data_left_aligned) | + ESAI_TCR_TSHFD(cfg->data_order); + + base->ECR &= ~(ESAI_ECR_ETI_MASK | + ESAI_ECR_ETO_MASK); + + base->ECR |= ESAI_ECR_ETI(cfg->hclk_src) | + ESAI_ECR_ETO(cfg->hclk_bypass); + + base->TFCR &= ~(ESAI_TFCR_TFWM_MASK | ESAI_TFCR_TWA_MASK); + base->TFCR |= ESAI_TFCR_TFWM(cfg->watermark) | + ESAI_TFCR_TWA(cfg->word_alignment); + + ESAI_TxSetSlotMask(base, cfg->slot_mask); + } else { + base->RCCR &= ~(ESAI_RCCR_RHCKD_MASK | ESAI_RCCR_RFSD_MASK | + ESAI_RCCR_RCKD_MASK | ESAI_RCCR_RHCKP_MASK | + ESAI_RCCR_RFSP_MASK | ESAI_RCCR_RCKP_MASK | + ESAI_RCCR_RFP_MASK | ESAI_RCCR_RDC_MASK | + ESAI_RCCR_RPSR_MASK | ESAI_RCCR_RPM_MASK); + + base->RCCR |= ESAI_RCCR_RHCKD(cfg->hclk_dir) | + ESAI_RCCR_RFSD(cfg->fsync_dir) | + ESAI_RCCR_RCKD(cfg->bclk_dir) | + ESAI_RCCR_RHCKP(cfg->hclk_polarity) | + ESAI_RCCR_RFSP(cfg->fsync_polarity) | + ESAI_RCCR_RCKP(cfg->bclk_polarity) | + ESAI_RCCR_RFP(cfg->bclk_div_ratio - 1) | + ESAI_RCCR_RDC(cfg->fsync_div - 1) | + ESAI_RCCR_RPSR(!cfg->hclk_prescaler_en) | + ESAI_RCCR_RPM(cfg->hclk_div_ratio - 1); + + base->RCR &= ~(ESAI_RCR_RFSR_MASK | ESAI_RCR_RFSL_MASK | + ESAI_RCR_RMOD_MASK | ESAI_RCR_RWA_MASK | + ESAI_RCR_RSHFD_MASK); + + base->RCR |= ESAI_RCR_RFSR(cfg->fsync_early) | + ESAI_RCR_RFSL(cfg->fsync_is_bit_wide) | + ESAI_RCR_RSWS(cfg->slot_format) | + ESAI_RCR_RMOD(cfg->mode) | + ESAI_RCR_RWA(!cfg->data_left_aligned) | + ESAI_RCR_RSHFD(cfg->data_order); + + base->ECR &= ~(ESAI_ECR_ERI_MASK | + ESAI_ECR_ERO_MASK); + + base->ECR |= ESAI_ECR_ERI(cfg->hclk_src) | + ESAI_ECR_ERO(cfg->hclk_bypass); + + base->RFCR &= ~(ESAI_RFCR_RFWM_MASK | ESAI_RFCR_RWA_MASK); + base->RFCR |= ESAI_RFCR_RFWM(cfg->watermark) | + ESAI_RFCR_RWA(cfg->word_alignment); + + EASI_RxSetSlotMask(base, cfg->slot_mask); + } +} + +static int esai_config_set(const struct device *dev, + const struct dai_config *cfg, + const void *bespoke_data) +{ + const struct esai_bespoke_config *bespoke; + struct esai_data *data; + const struct esai_config *esai_cfg; + struct esai_transceiver_config tx_config; + struct esai_transceiver_config rx_config; + ESAI_Type *base; + int ret; + + if (!cfg || !bespoke_data) { + return -EINVAL; + } + + if (cfg->type != DAI_IMX_ESAI) { + LOG_ERR("wrong DAI type: %d", cfg->type); + return -EINVAL; + } + + data = dev->data; + esai_cfg = dev->config; + bespoke = bespoke_data; + base = UINT_TO_ESAI(data->regmap); + + /* config_set() configures both the transmitter and the receiver. + * As such, the following state transitions make sure that the + * directions are stopped. This means that they can be safely + * reset and re-configured. + */ + ret = esai_update_state(data, DAI_DIR_TX, DAI_STATE_READY); + if (ret < 0) { + LOG_ERR("failed to update TX state"); + return ret; + } + + ret = esai_update_state(data, DAI_DIR_RX, DAI_STATE_READY); + if (ret < 0) { + LOG_ERR("failed to update RX state"); + return ret; + } + + ESAI_Enable(base, true); + + /* disconnect all ESAI pins */ + base->PCRC &= ~ESAI_PCRC_PC_MASK; + base->PRRC &= ~ESAI_PRRC_PDC_MASK; + + /* go back to known configuration through reset */ + ESAI_Reset(UINT_TO_ESAI(data->regmap)); + + /* get default configuration */ + esai_get_xceiver_default_config(&tx_config); + + /* TODO: for now, only network mode is supported */ + tx_config.fsync_div = bespoke->tdm_slots; + + /* clock provider configuration */ + ret = esai_get_clk_provider_config(cfg, &tx_config); + if (ret < 0) { + return ret; + } + + /* protocol configuration */ + ret = esai_get_proto_config(cfg, &tx_config); + if (ret < 0) { + return ret; + } + + /* clock inversion configuration */ + ret = esai_get_clk_inversion_config(cfg, &tx_config); + if (ret < 0) { + return ret; + } + + ret = esai_get_slot_format(bespoke->tdm_slot_width, + esai_cfg->word_width, &tx_config); + if (ret < 0) { + return ret; + } + + tx_config.word_alignment = ESAI_WORD_ALIGNMENT(esai_cfg->word_width); + + /* duplicate TX configuration */ + memcpy(&rx_config, &tx_config, sizeof(tx_config)); + + /* parse clock configuration from DTS. This will overwrite + * directions set in bespoke data. + */ + ret = esai_parse_clock_config(esai_cfg, &tx_config, &rx_config); + if (ret < 0) { + return ret; + } + + /* compute TX clock configuration */ + ret = esai_get_clock_rate_config(bespoke->mclk_rate, bespoke->mclk_rate, + bespoke->bclk_rate, + !ESAI_PIN_IS_USED(data, ESAI_PIN_HCKT), + tx_config.bclk_dir, + &tx_config); + if (ret < 0) { + return ret; + } + + /* compute RX clock configuration */ + ret = esai_get_clock_rate_config(bespoke->mclk_rate, bespoke->mclk_rate, + bespoke->bclk_rate, + !ESAI_PIN_IS_USED(data, ESAI_PIN_HCKR), + rx_config.bclk_dir, + &rx_config); + if (ret < 0) { + return ret; + } + + + tx_config.watermark = esai_cfg->tx_fifo_watermark; + rx_config.watermark = esai_cfg->rx_fifo_watermark; + + tx_config.slot_mask = bespoke->tx_slots; + rx_config.slot_mask = bespoke->rx_slots; + + LOG_DBG("dumping TX configuration"); + esai_dump_xceiver_config(&tx_config); + + LOG_DBG("dumping RX configuration"); + esai_dump_xceiver_config(&rx_config); + + /* enable ESAI to allow committing the configurations */ + ESAI_Enable(base, true); + + esai_dump_register_data(base); + + esai_commit_config(base, DAI_DIR_TX, &tx_config); + esai_commit_config(base, DAI_DIR_RX, &rx_config); + + /* allow each TX data register to be initialized from TX FIFO */ + base->TFCR |= ESAI_TFCR_TIEN_MASK; + + /* enable FIFO usage + * + * TODO: for now, only 1 data line per direction is supported. + */ + esai_tx_rx_enable_disable_fifo_usage(base, DAI_DIR_TX, BIT(0), true); + esai_tx_rx_enable_disable_fifo_usage(base, DAI_DIR_RX, BIT(0), true); + + /* re-connect pins based on DTS pin configuration */ + base->PCRC = data->pcrc; + base->PRRC = data->prrc; + + data->cfg.rate = bespoke->fsync_rate; + data->cfg.channels = bespoke->tdm_slots; + + esai_dump_register_data(base); + + return 0; +} + +static int esai_config_get(const struct device *dev, + struct dai_config *cfg, + enum dai_dir dir) +{ + struct esai_data *data = dev->data; + + if (!cfg) { + return -EINVAL; + } + + memcpy(cfg, &data->cfg, sizeof(*cfg)); + + return 0; +} + +static int esai_trigger_start(const struct device *dev, enum dai_dir dir) +{ + struct esai_data *data; + ESAI_Type *base; + int ret, i; + + data = dev->data; + base = UINT_TO_ESAI(data->regmap); + + ret = esai_update_state(data, dir, DAI_STATE_RUNNING); + if (ret < 0) { + LOG_ERR("failed to transition to RUNNING"); + return -EINVAL; + } + + LOG_DBG("starting direction %d", dir); + + /* enable the FIFO */ + esai_tx_rx_enable_disable_fifo(base, dir, true); + + /* TODO: without this, the ESAI won't enter underrun + * but playing a song while doing pause-resume very + * fast seems to result in a degraded sound quality? + * + * TODO: for multiple channels, this needs to be changed. + */ + if (dir == DAI_DIR_TX) { + for (i = 0; i < 1; i++) { + ESAI_WriteData(base, 0x0); + } + } + + /* enable the transmitter/receiver */ + esai_tx_rx_enable_disable(base, dir, BIT(0), true); + + return 0; +} + +static int esai_trigger_stop(const struct device *dev, enum dai_dir dir) +{ + struct esai_data *data; + int ret; + ESAI_Type *base; + + data = dev->data; + base = UINT_TO_ESAI(data->regmap); + + ret = esai_update_state(data, dir, DAI_STATE_STOPPING); + if (ret < 0) { + LOG_ERR("failed to transition to STOPPING"); + return -EINVAL; + } + + LOG_DBG("stopping direction %d", dir); + + /* disable transmitter/receiver */ + esai_tx_rx_enable_disable(base, dir, BIT(0), false); + + /* disable FIFO */ + esai_tx_rx_enable_disable_fifo(base, dir, false); + + return 0; +} + +static int esai_trigger(const struct device *dev, + enum dai_dir dir, + enum dai_trigger_cmd cmd) +{ + /* TX/RX should be triggered individually */ + if (dir != DAI_DIR_RX && dir != DAI_DIR_TX) { + LOG_ERR("invalid direction: %d", dir); + return -EINVAL; + } + + switch (cmd) { + case DAI_TRIGGER_START: + return esai_trigger_start(dev, dir); + case DAI_TRIGGER_PAUSE: + case DAI_TRIGGER_STOP: + return esai_trigger_stop(dev, dir); + case DAI_TRIGGER_PRE_START: + case DAI_TRIGGER_COPY: + /* nothing to do here, return success code */ + return 0; + default: + LOG_ERR("invalid trigger command: %d", cmd); + return -EINVAL; + } + + return 0; +} + +static const struct dai_properties + *esai_get_properties(const struct device *dev, enum dai_dir dir, int stream_id) +{ + const struct esai_config *cfg = dev->config; + + switch (dir) { + case DAI_DIR_RX: + return cfg->rx_props; + case DAI_DIR_TX: + return cfg->tx_props; + default: + LOG_ERR("invalid direction: %d", dir); + return NULL; + } +} + +static int esai_probe(const struct device *dev) +{ + /* nothing to be done here but mandatory to implement */ + return 0; +} + +static int esai_remove(const struct device *dev) +{ + /* nothing to be done here but mandatory to implement */ + return 0; +} + +static const struct dai_driver_api esai_api = { + .config_set = esai_config_set, + .config_get = esai_config_get, + .trigger = esai_trigger, + .get_properties = esai_get_properties, + .probe = esai_probe, + .remove = esai_remove, +}; + +static int esai_init(const struct device *dev) +{ + const struct esai_config *cfg; + struct esai_data *data; + int ret; + + cfg = dev->config; + data = dev->data; + + device_map(&data->regmap, cfg->regmap_phys, cfg->regmap_size, K_MEM_CACHE_NONE); + + ESAI_Reset(UINT_TO_ESAI(data->regmap)); + + ret = esai_parse_pinmodes(cfg, data); + if (ret < 0) { + return ret; + } + + return 0; +} + +#define ESAI_INIT(inst) \ + \ +BUILD_ASSERT(ESAI_TX_FIFO_WATERMARK(inst) >= 1 && \ + ESAI_TX_FIFO_WATERMARK(inst) <= _ESAI_FIFO_DEPTH(inst), \ + "invalid TX watermark value"); \ + \ +BUILD_ASSERT(ESAI_RX_FIFO_WATERMARK(inst) >= 1 && \ + ESAI_RX_FIFO_WATERMARK(inst) <= _ESAI_FIFO_DEPTH(inst), \ + "invalid RX watermark value"); \ + \ +BUILD_ASSERT(ESAI_FIFO_DEPTH(inst) >= 1 && \ + ESAI_FIFO_DEPTH(inst) <= _ESAI_FIFO_DEPTH(inst), \ + "invalid FIFO depth value"); \ + \ +BUILD_ASSERT(ESAI_WORD_WIDTH(inst) == 8 || \ + ESAI_WORD_WIDTH(inst) == 12 || \ + ESAI_WORD_WIDTH(inst) == 16 || \ + ESAI_WORD_WIDTH(inst) == 20 || \ + ESAI_WORD_WIDTH(inst) == 24, \ + "invalid word width value"); \ + \ +static const struct dai_properties esai_tx_props_##inst = { \ + .fifo_address = ESAI_TX_FIFO_BASE(inst), \ + .fifo_depth = ESAI_FIFO_DEPTH(inst) * 4, \ + .dma_hs_id = ESAI_TX_RX_DMA_HANDSHAKE(inst, tx), \ +}; \ + \ +static const struct dai_properties esai_rx_props_##inst = { \ + .fifo_address = ESAI_RX_FIFO_BASE(inst), \ + .fifo_depth = ESAI_FIFO_DEPTH(inst) * 4, \ + .dma_hs_id = ESAI_TX_RX_DMA_HANDSHAKE(inst, rx), \ +}; \ + \ +static uint32_t pinmodes_##inst[] = \ + DT_INST_PROP_OR(inst, esai_pin_modes, {}); \ + \ +BUILD_ASSERT(ARRAY_SIZE(pinmodes_##inst) % 2 == 0, \ + "bad pinmask array size"); \ + \ +static uint32_t clock_cfg_##inst[] = \ + DT_INST_PROP_OR(inst, esai_clock_configuration, {}); \ + \ +BUILD_ASSERT(ARRAY_SIZE(clock_cfg_##inst) % 2 == 0, \ + "bad clock configuration array size"); \ + \ +static struct esai_config esai_config_##inst = { \ + .regmap_phys = DT_INST_REG_ADDR(inst), \ + .regmap_size = DT_INST_REG_SIZE(inst), \ + .tx_props = &esai_tx_props_##inst, \ + .rx_props = &esai_rx_props_##inst, \ + .tx_fifo_watermark = ESAI_TX_FIFO_WATERMARK(inst), \ + .rx_fifo_watermark = ESAI_RX_FIFO_WATERMARK(inst), \ + .word_width = ESAI_WORD_WIDTH(inst), \ + .pinmodes = pinmodes_##inst, \ + .pinmodes_size = ARRAY_SIZE(pinmodes_##inst), \ + .clock_cfg = clock_cfg_##inst, \ + .clock_cfg_size = ARRAY_SIZE(clock_cfg_##inst), \ +}; \ + \ +static struct esai_data esai_data_##inst = { \ + .cfg.type = DAI_IMX_ESAI, \ + .cfg.dai_index = DT_INST_PROP_OR(inst, dai_index, 0), \ +}; \ + \ +DEVICE_DT_INST_DEFINE(inst, &esai_init, NULL, \ + &esai_data_##inst, &esai_config_##inst, \ + POST_KERNEL, CONFIG_DAI_INIT_PRIORITY, \ + &esai_api); \ + +DT_INST_FOREACH_STATUS_OKAY(ESAI_INIT); diff --git a/drivers/dai/nxp/esai/esai.h b/drivers/dai/nxp/esai/esai.h new file mode 100644 index 00000000000..9b008d8a03b --- /dev/null +++ b/drivers/dai/nxp/esai/esai.h @@ -0,0 +1,533 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_DAI_NXP_ESAI_H_ +#define ZEPHYR_DRIVERS_DAI_NXP_ESAI_H_ + +#include +#include +#include +#include + +#include + +LOG_MODULE_REGISTER(nxp_dai_esai); + +/* used for binding the driver */ +#define DT_DRV_COMPAT nxp_dai_esai + +/* workaround the fact that device_map() doesn't exist for SoCs with no MMU */ +#ifndef DEVICE_MMIO_IS_IN_RAM +#define device_map(virt, phys, size, flags) *(virt) = (phys) +#endif /* DEVICE_MMIO_IS_IN_RAM */ + +/* macros used for parsing DTS data */ + +#define _ESAI_FIFO_DEPTH(inst)\ + FSL_FEATURE_ESAI_FIFO_SIZEn(UINT_TO_ESAI(DT_INST_REG_ADDR(inst))) + +/* used to fetch the depth of the FIFO. If the "fifo-depth" property is + * not specified, the FIFO depth that will be reported to the upper layers + * will be 128 * 4 (which is the maximum value, or, well, the actual FIFO + * depth) + */ +#define ESAI_FIFO_DEPTH(inst)\ + DT_INST_PROP_OR(inst, fifo_depth, _ESAI_FIFO_DEPTH(inst)) + +/* used to fetch the TX FIFO watermark value. If the "tx-fifo-watermark" + * property is not specified, this will be set to half of the FIFO depth. + */ +#define ESAI_TX_FIFO_WATERMARK(inst)\ + DT_INST_PROP_OR(inst, tx_fifo_watermark, (_ESAI_FIFO_DEPTH(inst) / 2)) + +/* used to fetch the RX FIFO watermark value. If the "rx-fifo-watermark" + * property is not specified, this will be set to half of the FIFO depth. + */ +#define ESAI_RX_FIFO_WATERMARK(inst)\ + DT_INST_PROP_OR(inst, rx_fifo_watermark, (_ESAI_FIFO_DEPTH(inst) / 2)) + +/* use to fetch the handshake value for a given direction. The handshake + * is computed as follows: + * handshake = CHANNEL_ID | (MUX_VALUE << 8) + * The channel ID and MUX value are each encoded in 8 bits. + */ +#define ESAI_TX_RX_DMA_HANDSHAKE(inst, dir)\ + ((DT_INST_DMAS_CELL_BY_NAME(inst, dir, channel) & GENMASK(7, 0)) |\ + ((DT_INST_DMAS_CELL_BY_NAME(inst, dir, mux) << 8) & GENMASK(15, 8))) + +/* used to fetch the word width. If the "word-width" property is not specified, + * this will default to 24. + */ +#define ESAI_WORD_WIDTH(inst) DT_INST_PROP_OR(inst, word_width, 24) + +/* utility macros */ + +/* convert uint to ESAI_Type * */ +#define UINT_TO_ESAI(x) ((ESAI_Type *)(uintptr_t)(x)) + +/* invert a clock's polarity. This works because a clock's polarity + * is expressed as a 0 or as a 1. + */ +#define ESAI_INVERT_POLARITY(polarity) (polarity) = !(polarity) + +#define _ESAI_SLOT_WORD_WIDTH_IS_VALID(width) (!(((width) - 8) % 4)) + +/* used to check if a slot/word width combination is valid */ +#define ESAI_SLOT_WORD_WIDTH_IS_VALID(slot_width, word_width)\ + (_ESAI_SLOT_WORD_WIDTH_IS_VALID(slot_width) && \ + _ESAI_SLOT_WORD_WIDTH_IS_VALID(word_width) && \ + ((word_width) < 32) && ((word_width) <= (slot_width))) + +/* used to convert slot/word width combination to a value that can be written + * to TCR's TSWS or RCR's RSWS. + */ +#define ESAI_SLOT_FORMAT(s, w)\ + ((w) < 24 ? ((s) - (w) + (((w) - 8) / 4)) : ((s) < 32 ? 0x1e : 0x1f)) + +/* used to compute the word alignment based on the word width value. + * This returns a value that can be written to TFCR's TWA or RFCR's + * RWA. + */ +#define ESAI_WORD_ALIGNMENT(word_width) ((32 - (word_width)) / 4) + +#define _ESAI_RX_FIFO_USAGE_EN(mask)\ + (((mask) << ESAI_RFCR_RE0_SHIFT) &\ + (ESAI_RFCR_RE0_MASK | ESAI_RFCR_RE1_MASK |\ + ESAI_RFCR_RE2_MASK | ESAI_RFCR_RE3_MASK)) + +#define _ESAI_TX_FIFO_USAGE_EN(mask)\ + (((mask) << ESAI_TFCR_TE0_SHIFT) &\ + (ESAI_TFCR_TE0_MASK | ESAI_TFCR_TE1_MASK | ESAI_TFCR_TE2_MASK |\ + ESAI_TFCR_TE3_MASK | ESAI_TFCR_TE4_MASK | ESAI_TFCR_TE5_MASK)) + +/* used to fetch the mask for setting TX/RX FIFO usage. By FIFO usage + * we mean we allow receivers/transmitters to use the "global" TX/RX + * FIFO (i.e: the FIFO that's common to all transmitters/receivers). + * More specifically, this macro returns the mask required for setting + * TFCR's TEx fields or RFCR's REx fields. + */ +#define ESAI_TX_RX_FIFO_USAGE_EN(dir, mask)\ + ((dir) == DAI_DIR_TX ? _ESAI_TX_FIFO_USAGE_EN(mask) :\ + _ESAI_RX_FIFO_USAGE_EN(mask)) + +#define _ESAI_TX_EN(mask)\ + (((mask) << ESAI_TCR_TE0_SHIFT) &\ + (ESAI_TCR_TE0_MASK | ESAI_TCR_TE1_MASK | ESAI_TCR_TE2_MASK |\ + ESAI_TCR_TE3_MASK | ESAI_TCR_TE4_MASK | ESAI_TCR_TE5_MASK)) + +#define _ESAI_RX_EN(mask)\ + (((mask) << ESAI_RCR_RE0_SHIFT) &\ + (ESAI_RCR_RE0_MASK | ESAI_RCR_RE1_MASK | ESAI_RCR_RE2_MASK |\ + ESAI_RCR_RE3_MASK)) + +/* used to fetch the mask for enabling transmitters/receivers. + * More specifically, this refers to TCR's TEx bits or RCR's REx + * bits. + */ +#define ESAI_TX_RX_EN(dir, mask)\ + ((dir) == DAI_DIR_TX ? _ESAI_TX_EN(mask) : _ESAI_RX_EN(mask)) + +/* used to fetch the base address of the TX FIFO */ +#define ESAI_TX_FIFO_BASE(inst)\ + POINTER_TO_UINT(&(UINT_TO_ESAI(DT_INST_REG_ADDR(inst))->ETDR)) + +/* used to fetch the base address of the RX FIFO */ +#define ESAI_RX_FIFO_BASE(inst)\ + POINTER_TO_UINT(&(UINT_TO_ESAI(DT_INST_REG_ADDR(inst))->ERDR)) + +/* used to check if an ESAI pin is used. An ESAI pin is considered to + * be used if PDC and PC bits for that pin are set (i.e: pin is in ESAI + * mode). + * + * The ESAI pins support 4 functionalities which can be configured + * via PCRC and PRRC: + * 1) Disconnected + * 2) GPIO input + * 3) GPIO output + * 4) ESAI + */ +#define ESAI_PIN_IS_USED(data, which)\ + (((data)->pcrc & BIT(which)) && ((data->prrc) & BIT(which))) + +struct esai_data { + mm_reg_t regmap; + struct dai_config cfg; + /* transmitter state */ + enum dai_state tx_state; + /* receiver state */ + enum dai_state rx_state; + /* value to be committed to PRRC. This is computed + * during esai_init() and committed during config_set() + * stage. + */ + uint32_t prrc; + /* value to be committed to PCRC. Computed and committed + * during the same stages as PRRC. + */ + uint32_t pcrc; +}; + +struct esai_config { + uint32_t regmap_phys; + uint32_t regmap_size; + const struct dai_properties *tx_props; + const struct dai_properties *rx_props; + uint32_t rx_fifo_watermark; + uint32_t tx_fifo_watermark; + uint32_t word_width; + uint32_t *pinmodes; + uint32_t pinmodes_size; + uint32_t *clock_cfg; + uint32_t clock_cfg_size; +}; + +/* this needs to perfectly match SOF's struct sof_ipc_dai_esai_params */ +struct esai_bespoke_config { + uint32_t reserved0; + + uint16_t reserved1; + uint16_t mclk_id; + uint32_t mclk_direction; + + /* clock-related data */ + uint32_t mclk_rate; + uint32_t fsync_rate; + uint32_t bclk_rate; + + /* TDM-related data */ + uint32_t tdm_slots; + uint32_t rx_slots; + uint32_t tx_slots; + uint16_t tdm_slot_width; + + uint16_t reserved2; +}; + +struct esai_transceiver_config { + /* enable/disable the HCLK prescaler */ + bool hclk_prescaler_en; + /* controls the divison value of HCLK (i.e: TPM0-TPM7) */ + uint32_t hclk_div_ratio; + /* controls the division value of HCLK before reaching + * BCLK consumers (i.e: TFP0-TFP3) + */ + uint32_t bclk_div_ratio; + /* should the HCLK divison be bypassed or not? + * If in bypass, HCLK pad will be the same as EXTAL + */ + bool hclk_bypass; + + /* HCLK direction - input or output */ + esai_clock_direction_t hclk_dir; + /* HCLK source - EXTAL or IPG clock */ + esai_hclk_source_t hclk_src; + /* HCLK polarity - LOW or HIGH */ + esai_clock_polarity_t hclk_polarity; + + /* BCLK direction - input or output */ + esai_clock_direction_t bclk_dir; + /* BCLK polarity - LOW or HIGH */ + esai_clock_polarity_t bclk_polarity; + + /* FSYNC direction - input or output */ + esai_clock_direction_t fsync_dir; + /* FSYNC polarity - LOW or HIGH */ + esai_clock_polarity_t fsync_polarity; + + /* should FSYNC be bit-wide or word-wide? */ + bool fsync_is_bit_wide; + /* enable/disable padding word with zeros. If + * disabled, pad will be done using last/first + * bit - see TCR's PADC bit for more info. + */ + bool zero_pad_en; + /* should FSYNC be asserted before MSB transmission + * or alongside it? + */ + bool fsync_early; + + /* FSYNC divison value - for network mode this is + * the same as the number of slots - 1. + */ + uint32_t fsync_div; + + /* slot format - see TCR's TSWS or RCR's RSWS */ + esai_slot_format_t slot_format; + /* mode - network or normal + * TODO: at the moment, only network mode is supported. + */ + esai_mode_t mode; + + /* controls whether MSB or LSB is transmitted first */ + esai_shift_direction_t data_order; + + /* controls the word alignment inside a slot. If enabled + * word is left-aligned, otherwise it will be right-aligned. + * For details, see TCR/RCR's TWA/RWA. + */ + bool data_left_aligned; + /* TX/RX watermark value */ + uint32_t watermark; + + /* concatenation of TSMA+TSMB/RSMA+RSMB. Controls which + * slots should be High-Z or data. + */ + uint32_t slot_mask; + /* controls the alignment of data written to FIFO. + * See TFCR's TWA or RFCR's RWA for more details. + */ + uint32_t word_alignment; +}; + +static int esai_parse_clock_config(const struct esai_config *cfg, + struct esai_transceiver_config *tx_cfg, + struct esai_transceiver_config *rx_cfg) +{ + int i; + uint32_t crt_clock, crt_dir; + + for (i = 0; i < cfg->clock_cfg_size; i += 2) { + crt_clock = cfg->clock_cfg[i]; + crt_dir = cfg->clock_cfg[i + 1]; + + /* sanity checks */ + if (crt_clock > ESAI_CLOCK_FST) { + LOG_ERR("invalid clock configuration ID: %d", crt_clock); + return -EINVAL; + } + + if (crt_dir > ESAI_CLOCK_OUTPUT) { + LOG_ERR("invalid clock configuration direction: %d", crt_dir); + return -EINVAL; + } + + switch (crt_clock) { + case ESAI_CLOCK_HCKT: + tx_cfg->hclk_dir = crt_dir; + break; + case ESAI_CLOCK_HCKR: + rx_cfg->hclk_dir = crt_dir; + break; + case ESAI_CLOCK_SCKT: + tx_cfg->bclk_dir = crt_dir; + break; + case ESAI_CLOCK_SCKR: + rx_cfg->bclk_dir = crt_dir; + break; + case ESAI_CLOCK_FST: + tx_cfg->fsync_dir = crt_dir; + break; + case ESAI_CLOCK_FSR: + rx_cfg->fsync_dir = crt_dir; + break; + } + } + + return 0; +} + +static int esai_parse_pinmodes(const struct esai_config *cfg, + struct esai_data *data) +{ + int i; + uint32_t pin, pin_mode; + + /* initially, the assumption is that all pins are in ESAI mode */ + data->pcrc = ESAI_PCRC_PC_MASK; + data->prrc = ESAI_PRRC_PDC_MASK; + + for (i = 0; i < cfg->pinmodes_size; i += 2) { + pin = cfg->pinmodes[i]; + pin_mode = cfg->pinmodes[i + 1]; + + if (pin > ESAI_PIN_SDO0 || pin_mode > ESAI_PIN_ESAI) { + return -EINVAL; + } + + switch (pin_mode) { + case ESAI_PIN_DISCONNECTED: + data->pcrc &= ~BIT(pin); + data->prrc &= ~BIT(pin); + break; + case ESAI_PIN_GPIO_INPUT: + data->pcrc &= ~BIT(pin); + break; + case ESAI_PIN_GPIO_OUTPUT: + data->prrc &= ~BIT(pin); + break; + case ESAI_PIN_ESAI: + /* nothing to be done here, this is the default */ + break; + } + } + + return 0; +} + +static inline uint32_t esai_get_state(struct esai_data *data, + enum dai_dir dir) +{ + if (dir == DAI_DIR_RX) { + return data->rx_state; + } else { + return data->tx_state; + } +} + +static inline int esai_update_state(struct esai_data *data, + enum dai_dir dir, enum dai_state new_state) +{ + enum dai_state old_state = esai_get_state(data, dir); + + LOG_DBG("attempting state transition from %d to %d", old_state, new_state); + + switch (new_state) { + case DAI_STATE_NOT_READY: + /* initial state, transition is not possible */ + return -EPERM; + case DAI_STATE_READY: + if (old_state != DAI_STATE_NOT_READY && + old_state != DAI_STATE_READY && + old_state != DAI_STATE_STOPPING) { + return -EPERM; + } + break; + case DAI_STATE_RUNNING: + if (old_state != DAI_STATE_STOPPING && + old_state != DAI_STATE_READY) { + return -EPERM; + } + break; + case DAI_STATE_STOPPING: + if (old_state != DAI_STATE_RUNNING) { + return -EPERM; + } + break; + default: + LOG_ERR("invalid new state: %d", new_state); + return -EINVAL; + } + + if (dir == DAI_DIR_RX) { + data->rx_state = new_state; + } else { + data->tx_state = new_state; + } + + return 0; +} + +static inline void esai_tx_rx_enable_disable_fifo(ESAI_Type *base, + enum dai_dir dir, + bool enable) +{ + if (enable) { + if (dir == DAI_DIR_RX) { + base->RFCR |= ESAI_RFCR_RFE_MASK; + } else { + base->TFCR |= ESAI_TFCR_TFE_MASK; + } + } else { + if (dir == DAI_DIR_RX) { + base->RFCR &= ~ESAI_RFCR_RFE_MASK; + } else { + base->TFCR &= ~ESAI_TFCR_TFE_MASK; + } + } +} + +static inline void esai_tx_rx_enable_disable(ESAI_Type *base, + enum dai_dir dir, + uint32_t which, bool enable) +{ + uint32_t val = ESAI_TX_RX_EN(dir, which); + + if (enable) { + if (dir == DAI_DIR_RX) { + base->RCR |= val; + } else { + base->TCR |= val; + } + } else { + if (dir == DAI_DIR_RX) { + base->RCR &= ~val; + } else { + base->TCR &= ~val; + } + } +} + +static inline void esai_tx_rx_enable_disable_fifo_usage(ESAI_Type *base, + enum dai_dir dir, + uint32_t which, bool enable) +{ + uint32_t val = ESAI_TX_RX_FIFO_USAGE_EN(dir, which); + + if (enable) { + if (dir == DAI_DIR_RX) { + base->RFCR |= val; + } else { + base->TFCR |= val; + } + } else { + if (dir == DAI_DIR_RX) { + base->RFCR &= ~val; + } else { + base->TFCR &= ~val; + } + } +} + +static inline void esai_dump_xceiver_config(struct esai_transceiver_config *cfg) +{ + LOG_DBG("HCLK prescaler enable: %d", cfg->hclk_prescaler_en); + LOG_DBG("HCLK divider ratio: %d", cfg->hclk_div_ratio); + LOG_DBG("BCLK divider ratio: %d", cfg->bclk_div_ratio); + LOG_DBG("HCLK bypass: %d", cfg->hclk_bypass); + + LOG_DBG("HCLK direction: %d", cfg->hclk_dir); + LOG_DBG("HCLK source: %d", cfg->hclk_src); + LOG_DBG("HCLK polarity: %d", cfg->hclk_polarity); + + LOG_DBG("BCLK direction: %d", cfg->bclk_dir); + LOG_DBG("BCLK polarity: %d", cfg->bclk_polarity); + + LOG_DBG("FSYNC direction: %d", cfg->fsync_dir); + LOG_DBG("FSYNC polarity: %d", cfg->fsync_polarity); + + LOG_DBG("FSYNC is bit wide: %d", cfg->fsync_is_bit_wide); + LOG_DBG("zero pad enable: %d", cfg->zero_pad_en); + LOG_DBG("FSYNC asserted early: %d", cfg->fsync_early); + + LOG_DBG("watermark: %d", cfg->watermark); + LOG_DBG("slot mask: 0x%x", cfg->slot_mask); + LOG_DBG("word alignment: 0x%x", cfg->word_alignment); +} + +static inline void esai_dump_register_data(ESAI_Type *base) +{ + LOG_DBG("ECR: 0x%x", base->ECR); + LOG_DBG("ESR: 0x%x", base->ESR); + LOG_DBG("TFCR: 0x%x", base->TFCR); + LOG_DBG("TFSR: 0x%x", base->TFSR); + LOG_DBG("RFCR: 0x%x", base->RFCR); + LOG_DBG("RFSR: 0x%x", base->RFSR); + LOG_DBG("TSR: 0x%x", base->TSR); + LOG_DBG("SAISR: 0x%x", base->SAISR); + LOG_DBG("SAICR: 0x%x", base->SAICR); + LOG_DBG("TCR: 0x%x", base->TCR); + LOG_DBG("TCCR: 0x%x", base->TCCR); + LOG_DBG("RCR: 0x%x", base->RCR); + LOG_DBG("RCCR: 0x%x", base->RCCR); + LOG_DBG("TSMA: 0x%x", base->TSMA); + LOG_DBG("TSMB: 0x%x", base->TSMB); + LOG_DBG("RSMA: 0x%x", base->RSMA); + LOG_DBG("RSMB: 0x%x", base->RSMB); + LOG_DBG("PRRC: 0x%x", base->PRRC); + LOG_DBG("PCRC: 0x%x", base->PCRC); +} + +#endif /* ZEPHYR_DRIVERS_DAI_NXP_ESAI_H_ */ diff --git a/dts/bindings/dai/nxp,dai-esai.yaml b/dts/bindings/dai/nxp,dai-esai.yaml new file mode 100644 index 00000000000..b179a8c6b9b --- /dev/null +++ b/dts/bindings/dai/nxp,dai-esai.yaml @@ -0,0 +1,75 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP Enhanced Serial Audio Interface (ESAI) node + +compatible: "nxp,dai-esai" + +include: base.yaml + +properties: + reg: + required: true + dai-index: + type: int + description: | + Use this property to specify the index of the DAI. At the + moment, this is only used by SOF to fetch the "struct device" + associated with the DAI whose index Linux passes to SOF + through an IPC. If this property is not specified, the DAI + index will be considered 0. + tx-fifo-watermark: + type: int + description: | + Use this property to specify the watermark value for the TX + FIFO. This value needs to be in FIFO words (NOT BYTES). This + value needs to be in the following interval: (0, DEFAULT_FIFO_DEPTH], + otherwise a BUILD_ASSERT() failure will be raised. If unspecified, + the TX FIFO watermark will be set to DEFAULT_FIFO_DEPTH / 2. + rx-fifo-watermark: + type: int + description: | + Use this property to specify the watermark value for the RX + FIFO. This values needs to be in FIFO words (NOT BYTES). This + value needs to be in the following interval: (0, DEFAULT_FIFO_DEPTH], + otherwise a BUILD_ASSERT() failure will be raised. If unspecified, + the RX FIFO watermark will be set to DEFAULT_FIFO_DEPTH / 2. + fifo-depth: + type: int + description: | + Use this property to set the FIFO depth that will be reported + to upper layer applications calling dai_get_properties(). This + value should be in the following interval: (0, DEFAULT_FIFO_DEPTH], + otherwise a BUILD_ASSERT() failure will be raised. By DEFAULT_FIFO_DEPTH + we mean the actual (hardware) value of the FIFO depth. This is needed + because some applications (e.g: SOF) use this value directly as the + DMA burst size in which case DEFAULT_FIFO_DEPTH cannot be used. + Generally, reporting a false FIFO depth should be avoided. Please note + that the sanity check for tx/rx-fifo-watermark uses DEFAULT_FIFO_DETPH + instead of this value so use with caution. If unsure, it's better to + not use this property at all, in which case the reported value will be + DEFAULT_FIFO_DEPTH. + word-width: + type: int + description: | + This property is used to specify the width of a word. If unspecified, + the word width used will be 24. + esai-pin-modes: + type: array + description: | + This property is used to configure the ESAI pins. Each ESAI pin + supports 4 modes: + 1) DISCONNECTED (PDC[i] = 0, PC[i] = 0) + 2) GPIO input (PDC[i] = 0, PC[i] = 1) + 3) GPIO output (PDC[i] = 1, PC[i] = 0) + 4) ESAI (PDC[i] = 1, PC[i] = 1) + If pin is not used then DISCONNECTED mode should be used for said pin. + If unsure, don't specify this property at all. By default, all pins will + be set to ESAI mode. + esai-clock-configuration: + type: array + description: | + Use this property to configure the directions of the ESAI clocks (HCLK, BCLK, FSYNC). + This provides extra flexibility since the bespoke configuration is not direction-based. + The values from this array will overwrite the values set through the bespoke + configuration. If unspecified, the values from the bespoke configuration will be used. diff --git a/include/zephyr/dt-bindings/dai/esai.h b/include/zephyr/dt-bindings/dai/esai.h new file mode 100644 index 00000000000..8dd45a91bc8 --- /dev/null +++ b/include/zephyr/dt-bindings/dai/esai.h @@ -0,0 +1,54 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_ +#define _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_ + +/* ESAI pin IDs + * the values of these macros are meant to match + * the bit position from PCRC/PRRC's PC/PDC associated + * with each of these pins. + */ +#define ESAI_PIN_SCKR 0 +#define ESAI_PIN_FSR 1 +#define ESAI_PIN_HCKR 2 +#define ESAI_PIN_SCKT 3 +#define ESAI_PIN_FST 4 +#define ESAI_PIN_HCKT 5 +#define ESAI_PIN_SDO5_SDI0 6 +#define ESAI_PIN_SDO4_SDI1 7 +#define ESAI_PIN_SDO3_SDI2 8 +#define ESAI_PIN_SDO2_SDI3 9 +#define ESAI_PIN_SDO1 10 +#define ESAI_PIN_SDO0 11 + +/* ESAI pin modes + * the values of these macros are set according to + * the following table: + * + * PDC = 0, PC = 0 => DISCONNECTED (0) + * PDC = 0, PC = 1 => GPIO INPUT (1) + * PDC = 1, PC = 0 => GPIO OUTUT (2) + * PDC = 1, PC = 1 => ESAI (3) + */ +#define ESAI_PIN_DISCONNECTED 0 +#define ESAI_PIN_GPIO_INPUT 1 +#define ESAI_PIN_GPIO_OUTPUT 2 +#define ESAI_PIN_ESAI 3 + +/* ESAI clock IDs */ +#define ESAI_CLOCK_HCKT 0 +#define ESAI_CLOCK_HCKR 1 +#define ESAI_CLOCK_SCKR 2 +#define ESAI_CLOCK_SCKT 3 +#define ESAI_CLOCK_FSR 4 +#define ESAI_CLOCK_FST 5 + +/* ESAI clock directions */ +#define ESAI_CLOCK_INPUT 0 +#define ESAI_CLOCK_OUTPUT 1 + +#endif /* _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_ */ From bba8641354bfbf83743c032c378a791b941ad7fc Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Mon, 12 Feb 2024 14:28:08 +0200 Subject: [PATCH 1781/2402] dts: xtensa: nxp_imx8: add ESAI0 node Add node for NXP's i.MX8QM/i.MX8QXP AUDIO ESAI0 IP. Signed-off-by: Laurentiu Mihalcea --- dts/xtensa/nxp/nxp_imx8.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/dts/xtensa/nxp/nxp_imx8.dtsi b/dts/xtensa/nxp/nxp_imx8.dtsi index ec97e8d1816..87713a71200 100644 --- a/dts/xtensa/nxp/nxp_imx8.dtsi +++ b/dts/xtensa/nxp/nxp_imx8.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { cpus { @@ -135,6 +136,20 @@ status = "disabled"; }; + esai0: dai@59010000 { + compatible = "nxp,dai-esai"; + reg = <0x59010000 DT_SIZE_K(64)>; + dmas = <&edma0 7 0>, <&edma0 6 0>; + dma-names = "tx", "rx"; + esai-pin-modes = , + , + , + , + , + ; + status = "disabled"; + }; + /* LSIO MU2, used to interact with the SCFW */ scu_mu: mailbox@5d1d0000 { reg = <0x5d1d0000 DT_SIZE_K(64)>; From a74747008692bb7cc87434e6a694491678e698c0 Mon Sep 17 00:00:00 2001 From: David Brown Date: Thu, 22 Feb 2024 12:30:23 -0700 Subject: [PATCH 1782/2402] boards: arm: sparkfun_pro_micro_rp2040: Support JTAG Add SWD debugger support for this board. Although there is not a debug header, the SWD pins are accessible and the adaptor is not that difficult to wire up. This will allow for debugging beyond just flashing, that the UF2 programming setup allows for. Signed-off-by: David Brown --- boards/sparkfun/pro_micro_rp2040/board.cmake | 39 +++++++++++++++++++ .../sparkfun/pro_micro_rp2040/doc/index.rst | 14 ++++--- .../pro_micro_rp2040/support/openocd.cfg | 11 ++++++ 3 files changed, 58 insertions(+), 6 deletions(-) create mode 100644 boards/sparkfun/pro_micro_rp2040/support/openocd.cfg diff --git a/boards/sparkfun/pro_micro_rp2040/board.cmake b/boards/sparkfun/pro_micro_rp2040/board.cmake index e69de29bb2d..7d557630b9b 100644 --- a/boards/sparkfun/pro_micro_rp2040/board.cmake +++ b/boards/sparkfun/pro_micro_rp2040/board.cmake @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: Apache-2.0 + +# This configuration allows selecting what debug adapter debugging to use +# for the SparkFun Pro Micro RP2040 by a command-line argument. +# It is mainly intended to support both the 'picoprobe' and 'raspberrypi-swd' +# adapter described in "Getting started with Raspberry Pi Pico". +# And any other SWD debug adapter might also be usable with this configuration. + +# Note that the Pro Micro RP2040 SWD pins are test points on the underside +# of the board. + +# Set RPI_PICO_DEBUG_ADAPTER to select debug adapter by command-line arguments. +# e.g.) west build -b rpi_pico -- -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd +# The value is treated as a part of an interface file name that +# the debugger's configuration file. +# The value must be the 'stem' part of the name of one of the files +# in the openocd interface configuration file. +# The setting is store to CMakeCache.txt. +if ("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "transport select swd") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2040.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# But if not so, set 2000 to adapter speed. +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000") + +board_runner_args(jlink "--device=RP2040_M0_0") +board_runner_args(uf2 "--board-id=RPI-RP2") +board_runner_args(pyocd "--target=rp2040") + +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/sparkfun/pro_micro_rp2040/doc/index.rst b/boards/sparkfun/pro_micro_rp2040/doc/index.rst index 3fa4fe40b71..cc8188aa3f1 100644 --- a/boards/sparkfun/pro_micro_rp2040/doc/index.rst +++ b/boards/sparkfun/pro_micro_rp2040/doc/index.rst @@ -115,12 +115,14 @@ Flashing Using UF2 --------- -Since it doesn't expose the SWD pins, you must flash the SparkFun Pro Micro -RP2040 with a UF2 file. By default, building an app for this board will -generate a `build/zephyr/zephyr.uf2` file. If the Pro Micro RP2040 is powered -on with the `BOOTSEL` button pressed, it will appear on the host as a mass -storage device. The UF2 file should be drag-and-dropped to the device, which -will flash the Pro Micro RP2040. +The Pro Micro board does make the SWD pins available on pads on the +underside of the board. You can solder to these pins, and use a JTag +debugger. You can also flash the SparkFun ProMicro RP2040 with a UF2 file. +By default, building an app for this board will generate a +`build/zephyr/zephyr.uf2` file. If the Pro Micro RP2040 is powered on with +the `BOOTSEL` button pressed, it will appear on the host as a mass storage +device. The UF2 file should be copied to the device, which will +flash the Pro Micro RP2040. .. target-notes:: diff --git a/boards/sparkfun/pro_micro_rp2040/support/openocd.cfg b/boards/sparkfun/pro_micro_rp2040/support/openocd.cfg new file mode 100644 index 00000000000..a9918980457 --- /dev/null +++ b/boards/sparkfun/pro_micro_rp2040/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set adapter speed that assigned by argument if not be seted. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} From da52c6e3b7d795df4ca53d97d2c57ea53592f3ac Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 22 Mar 2024 10:41:23 -0600 Subject: [PATCH 1783/2402] boards: Spelling and grammar fix in openocd comment This file has been copied a few times. Clean up the grammar and spelling in a comment in the file. Signed-off-by: David Brown --- boards/raspberrypi/rpi_pico/support/openocd.cfg | 2 +- boards/sparkfun/pro_micro_rp2040/support/openocd.cfg | 2 +- boards/wiznet/w5500_evb_pico/support/openocd.cfg | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/raspberrypi/rpi_pico/support/openocd.cfg b/boards/raspberrypi/rpi_pico/support/openocd.cfg index a9918980457..34ab592b186 100644 --- a/boards/raspberrypi/rpi_pico/support/openocd.cfg +++ b/boards/raspberrypi/rpi_pico/support/openocd.cfg @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 # Checking and set 'adapter speed'. -# Set adapter speed that assigned by argument if not be seted. +# Set the adaptor speed, if unset, and given as an argument. proc set_adapter_speed_if_not_set { speed } { puts "checking adapter speed..." if { [catch {adapter speed} ret] } { diff --git a/boards/sparkfun/pro_micro_rp2040/support/openocd.cfg b/boards/sparkfun/pro_micro_rp2040/support/openocd.cfg index a9918980457..34ab592b186 100644 --- a/boards/sparkfun/pro_micro_rp2040/support/openocd.cfg +++ b/boards/sparkfun/pro_micro_rp2040/support/openocd.cfg @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 # Checking and set 'adapter speed'. -# Set adapter speed that assigned by argument if not be seted. +# Set the adaptor speed, if unset, and given as an argument. proc set_adapter_speed_if_not_set { speed } { puts "checking adapter speed..." if { [catch {adapter speed} ret] } { diff --git a/boards/wiznet/w5500_evb_pico/support/openocd.cfg b/boards/wiznet/w5500_evb_pico/support/openocd.cfg index a9918980457..34ab592b186 100644 --- a/boards/wiznet/w5500_evb_pico/support/openocd.cfg +++ b/boards/wiznet/w5500_evb_pico/support/openocd.cfg @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 # Checking and set 'adapter speed'. -# Set adapter speed that assigned by argument if not be seted. +# Set the adaptor speed, if unset, and given as an argument. proc set_adapter_speed_if_not_set { speed } { puts "checking adapter speed..." if { [catch {adapter speed} ret] } { From 2c722f97b54f6479b176b2abb8b92fa8145277e9 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Tue, 2 Apr 2024 12:10:53 +0000 Subject: [PATCH 1784/2402] scripts: pylib: twister: Remove unused Twister flags Deletes 4 Twister flags that were unusable: * --enable-asserts * --disable-asserts * --no-skipped-report * --error-on-deprecations Signed-off-by: Lukasz Mrugala --- scripts/pylib/twister/twisterlib/environment.py | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/environment.py b/scripts/pylib/twister/twisterlib/environment.py index e8bc0d9f54b..2b99450ee6c 100644 --- a/scripts/pylib/twister/twisterlib/environment.py +++ b/scripts/pylib/twister/twisterlib/environment.py @@ -341,10 +341,6 @@ def add_parse_arguments(parser = None): "--device-serial-baud", action="store", default=None, help="Serial device baud rate (default 115200)") - parser.add_argument("--disable-asserts", action="store_false", - dest="enable_asserts", - help="deprecated, left for compatibility") - parser.add_argument( "--disable-unrecognized-section-test", action="store_true", default=False, @@ -489,12 +485,6 @@ def add_parse_arguments(parser = None): # Include paths in names by default. parser.set_defaults(detailed_test_id=True) - # To be removed in favor of --detailed-skipped-report - parser.add_argument( - "--no-skipped-report", action="store_true", - help="""Do not report skipped test cases in junit output. [Experimental] - """) - parser.add_argument( "--detailed-skipped-report", action="store_true", help="Generate a detailed report with all skipped test cases" @@ -555,9 +545,6 @@ def add_parse_arguments(parser = None): before device handler open serial port and invoke runner. """) - parser.add_argument("-Q", "--error-on-deprecations", action="store_false", - help="Error on deprecation warnings.") - parser.add_argument( "--quarantine-list", action="append", @@ -573,10 +560,6 @@ def add_parse_arguments(parser = None): help="Use the list of test scenarios under quarantine and run them" "to verify their current status.") - parser.add_argument("-R", "--enable-asserts", action="store_true", - default=True, - help="deprecated, left for compatibility") - parser.add_argument( "--report-name", help="""Create a report with a custom name. From 29aaaa2e60e4e493206c61f2f283a7be3907c907 Mon Sep 17 00:00:00 2001 From: Carles Cufi Date: Tue, 2 Apr 2024 19:37:01 +0200 Subject: [PATCH 1785/2402] samples: shell: shell_module: Add harness to the Bluetooth config Add a harness to avoid twister waiting for results on the UART, which won't happen unless there is a connection established to a remote Bluetooth device. Signed-off-by: Carles Cufi --- samples/subsys/shell/shell_module/sample.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/samples/subsys/shell/shell_module/sample.yaml b/samples/subsys/shell/shell_module/sample.yaml index fff5553b63d..cfd6adb80de 100644 --- a/samples/subsys/shell/shell_module/sample.yaml +++ b/samples/subsys/shell/shell_module/sample.yaml @@ -53,6 +53,7 @@ tests: - shell - bluetooth filter: CONFIG_DT_HAS_ZEPHYR_NUS_UART_ENABLED + harness: bluetooth_nus arch_exclude: - posix extra_args: From f211cd6345555086307da8c4998783ebe0ec0027 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Tue, 26 Mar 2024 11:34:29 +0100 Subject: [PATCH 1786/2402] net: tcp: Deprecate CONFIG_NET_TCP_ACK_TIMEOUT Deprecate CONFIG_NET_TCP_ACK_TIMEOUT as it is redundant with the combination of CONFIG_NET_TCP_INIT_RETRANSMISSION_TIMEOUT and CONFIG_NET_TCP_RETRY_COUNT. The total retransmission timeout (i. e. waiting for ACK) should depend on the individual retransmission timeout and retry count, having separate config is simply ambiguous and confusing for users. Moreover, the config was currently only used during TCP handshake, and for that purpose we could use the very same timeout that is used for the FIN timeout. Therefore, repurpose the fin_timeout_ms to be a generic, maximum timeout at the TCP stack. Signed-off-by: Robert Lubos --- doc/releases/migration-guide-3.7.rst | 7 +++++++ subsys/net/ip/Kconfig.tcp | 8 ++++---- subsys/net/ip/tcp.c | 22 +++++++++++----------- tests/net/all/prj.conf | 1 - 4 files changed, 22 insertions(+), 16 deletions(-) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index be9a9ef489f..6c6a600eff8 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -220,6 +220,13 @@ Networking ``wifi -h`` will give more information about the usage of connect command. (:github:`70024`) +* The Kconfig ``CONFIG_NET_TCP_ACK_TIMEOUT`` has been deprecated. Its usage was + limited to TCP handshake only, and in such case the total timeout should depend + on the total retransmission timeout (as in other cases) making the config + redundant and confusing. Use ``CONFIG_NET_TCP_INIT_RETRANSMISSION_TIMEOUT`` and + ``CONFIG_NET_TCP_RETRY_COUNT`` instead to control the total timeout at the + TCP level. (:github:`70731`) + Other Subsystems **************** diff --git a/subsys/net/ip/Kconfig.tcp b/subsys/net/ip/Kconfig.tcp index 8342acfb59a..e7d45f46c7a 100644 --- a/subsys/net/ip/Kconfig.tcp +++ b/subsys/net/ip/Kconfig.tcp @@ -66,14 +66,14 @@ config NET_TCP_TIME_WAIT_DELAY Value of 0 disables TIME_WAIT state completely. config NET_TCP_ACK_TIMEOUT - int "How long to wait for ACK (in milliseconds)" + int "[DEPRECATED] How long to wait for ACK (in milliseconds)" depends on NET_TCP default 1000 range 1 2147483647 help - This value affects the timeout when waiting ACK to arrive in - various TCP states. The value is in milliseconds. Note that - having a very low value here could prevent connectivity. + Deprecated. Use CONFIG_NET_TCP_INIT_RETRANSMISSION_TIMEOUT and + CONFIG_NET_TCP_RETRY_COUNT to control the total timeout at the TCP + level. config NET_TCP_INIT_RETRANSMISSION_TIMEOUT int "Initial value of Retransmission Timeout (RTO) (in milliseconds)" diff --git a/subsys/net/ip/tcp.c b/subsys/net/ip/tcp.c index 49ad112b527..3aee7e047ef 100644 --- a/subsys/net/ip/tcp.c +++ b/subsys/net/ip/tcp.c @@ -26,18 +26,18 @@ LOG_MODULE_REGISTER(net_tcp, CONFIG_NET_TCP_LOG_LEVEL); #include "net_private.h" #include "tcp_internal.h" -#define ACK_TIMEOUT_MS CONFIG_NET_TCP_ACK_TIMEOUT +#define ACK_TIMEOUT_MS tcp_max_timeout_ms #define ACK_TIMEOUT K_MSEC(ACK_TIMEOUT_MS) -#define LAST_ACK_TIMEOUT_MS tcp_fin_timeout_ms +#define LAST_ACK_TIMEOUT_MS tcp_max_timeout_ms #define LAST_ACK_TIMEOUT K_MSEC(LAST_ACK_TIMEOUT_MS) -#define FIN_TIMEOUT K_MSEC(tcp_fin_timeout_ms) +#define FIN_TIMEOUT K_MSEC(tcp_max_timeout_ms) #define ACK_DELAY K_MSEC(100) #define ZWP_MAX_DELAY_MS 120000 #define DUPLICATE_ACK_RETRANSMIT_TRHESHOLD 3 static int tcp_rto = CONFIG_NET_TCP_INIT_RETRANSMISSION_TIMEOUT; static int tcp_retries = CONFIG_NET_TCP_RETRY_COUNT; -static int tcp_fin_timeout_ms; +static int tcp_max_timeout_ms; static int tcp_rx_window = #if (CONFIG_NET_TCP_MAX_RECV_WINDOW_SIZE != 0) CONFIG_NET_TCP_MAX_RECV_WINDOW_SIZE; @@ -1821,7 +1821,7 @@ static void tcp_resend_data(struct k_work *work) if (conn->in_close && conn->send_data_total == 0) { NET_DBG("TCP connection in %s close, " "not disposing yet (waiting %dms)", - "active", tcp_fin_timeout_ms); + "active", tcp_max_timeout_ms); k_work_reschedule_for_queue(&tcp_work_q, &conn->fin_timer, FIN_TIMEOUT); @@ -1896,7 +1896,7 @@ static void tcp_fin_timeout(struct k_work *work) return; } - NET_DBG("Did not receive %s in %dms", "FIN", tcp_fin_timeout_ms); + NET_DBG("Did not receive %s in %dms", "FIN", tcp_max_timeout_ms); NET_DBG("conn: %p %s", conn, tcp_conn_state(conn, NULL)); (void)tcp_conn_close(conn, -ETIMEDOUT); @@ -3564,7 +3564,7 @@ int net_tcp_put(struct net_context *context) NET_DBG("TCP connection in %s close, " "not disposing yet (waiting %dms)", - "active", tcp_fin_timeout_ms); + "active", tcp_max_timeout_ms); k_work_reschedule_for_queue(&tcp_work_q, &conn->fin_timer, FIN_TIMEOUT); @@ -4445,18 +4445,18 @@ void net_tcp_init(void) NULL); /* Compute the largest possible retransmission timeout */ - tcp_fin_timeout_ms = 0; + tcp_max_timeout_ms = 0; rto = tcp_rto; for (i = 0; i < tcp_retries; i++) { - tcp_fin_timeout_ms += rto; + tcp_max_timeout_ms += rto; rto += rto >> 1; } /* At the last timeout cicle */ - tcp_fin_timeout_ms += tcp_rto; + tcp_max_timeout_ms += tcp_rto; /* When CONFIG_NET_TCP_RANDOMIZED_RTO is active in can be worse case 1.5 times larger */ if (IS_ENABLED(CONFIG_NET_TCP_RANDOMIZED_RTO)) { - tcp_fin_timeout_ms += tcp_fin_timeout_ms >> 1; + tcp_max_timeout_ms += tcp_max_timeout_ms >> 1; } k_thread_name_set(&tcp_work_q.thread, "tcp_work"); diff --git a/tests/net/all/prj.conf b/tests/net/all/prj.conf index dfdb46eeaf6..90f0d6cfcd5 100644 --- a/tests/net/all/prj.conf +++ b/tests/net/all/prj.conf @@ -126,7 +126,6 @@ CONFIG_NET_MAX_ROUTERS=3 CONFIG_NET_TCP=y CONFIG_NET_TCP_LOG_LEVEL_DBG=y CONFIG_NET_TCP_TIME_WAIT_DELAY=20000 -CONFIG_NET_TCP_ACK_TIMEOUT=30 CONFIG_NET_TCP_CHECKSUM=y CONFIG_NET_TCP_INIT_RETRANSMISSION_TIMEOUT=400 CONFIG_NET_TCP_RETRY_COUNT=10 From c50843a98c4c3668f15ed06e308014c7bb1c7b9f Mon Sep 17 00:00:00 2001 From: Jate Sujjavanich Date: Tue, 2 Jan 2024 12:07:33 -0500 Subject: [PATCH 1787/2402] boards: Add bl654_dvk pa variant Add pa variant definition to board.yml Add bl654_dvk_nrf52840_pa files dts, yaml, defconfig Update doc with information on variant and regulatory information Signed-off-by: Jate Sujjavanich --- .../lairdconnect/bl654_dvk/Kconfig.defconfig | 9 +++++++ .../bl654_dvk/bl654_dvk_nrf52840_pa.dts | 25 +++++++++++++++++++ .../bl654_dvk/bl654_dvk_nrf52840_pa.yaml | 15 +++++++++++ .../bl654_dvk/bl654_dvk_nrf52840_pa_defconfig | 23 +++++++++++++++++ boards/lairdconnect/bl654_dvk/board.yml | 2 ++ .../lairdconnect/bl654_dvk/doc/bl654_dvk.rst | 5 ++++ 6 files changed, 79 insertions(+) create mode 100644 boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.dts create mode 100644 boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.yaml create mode 100644 boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa_defconfig diff --git a/boards/lairdconnect/bl654_dvk/Kconfig.defconfig b/boards/lairdconnect/bl654_dvk/Kconfig.defconfig index facb6117693..dbd4fb812f0 100644 --- a/boards/lairdconnect/bl654_dvk/Kconfig.defconfig +++ b/boards/lairdconnect/bl654_dvk/Kconfig.defconfig @@ -16,3 +16,12 @@ config I2C endif # DAC endif # BOARD_BL654_DVK + +if BOARD_BL654_DVK_NRF52840_PA + +# Limit max power for FCC compliance with power amplifier +choice BT_CTLR_TX_PWR + default BT_CTLR_TX_PWR_MINUS_4 +endchoice + +endif # BOARD_BL654_DVK_NRF52840_PA diff --git a/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.dts b/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.dts new file mode 100644 index 00000000000..d826a466bfd --- /dev/null +++ b/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019 Laird Connectivity + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bl654_dvk.dts" + +/ { + /* Information from Nordic SDK-Based Application Development and SKY66112 datasheet */ + sky66112_fem: fem { + compatible = "generic-fem-two-ctrl-pins"; + ctx-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + crx-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + ctx-settle-time-us = <23>; + crx-settle-time-us = <5>; + tx-gain-db = <22>; + rx-gain-db = <11>; + }; +}; + +&radio { + fem = <&sky66112_fem>; +}; diff --git a/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.yaml b/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.yaml new file mode 100644 index 00000000000..d02d9386284 --- /dev/null +++ b/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa.yaml @@ -0,0 +1,15 @@ +identifier: bl654_dvk/nrf52840/pa +name: BL654_DVK_NRF52840_PA +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - usb_device + - ble + - pwm + - watchdog +vendor: lairdconnect diff --git a/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa_defconfig b/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa_defconfig new file mode 100644 index 00000000000..a108273c64c --- /dev/null +++ b/boards/lairdconnect/bl654_dvk/bl654_dvk_nrf52840_pa_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_RTT_CONSOLE=y + +# 32kHz clock source +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=y diff --git a/boards/lairdconnect/bl654_dvk/board.yml b/boards/lairdconnect/bl654_dvk/board.yml index 26fbd0e33bd..788824c7af1 100644 --- a/boards/lairdconnect/bl654_dvk/board.yml +++ b/boards/lairdconnect/bl654_dvk/board.yml @@ -3,3 +3,5 @@ board: vendor: lairdconnect socs: - name: nrf52840 + variants: + - name: pa diff --git a/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst b/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst index 79011edddf2..7ccb6294f4b 100644 --- a/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst +++ b/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst @@ -9,6 +9,11 @@ Overview The BL654 Development Kit hardware provides support for the Laird Connectivity BL654 module powered by a Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU. +It is also pin compatible with the BL654PA which adds a power amplifier. The "pa" variant provides +this compatibility. Use board ``bl654_dvk/nrf52840/pa`` to build for that target. +Bluetooth LE regulatory certifications obtained by Ezurio are not applicable to BL654PA variant. +It should not be used in commercial applications prior to re-certification being performed - please review with the Ezurio team at www.ezurio.com/contact + This development kit has the following features: * :abbr:`ADC (Analog to Digital Converter)` From bbb87ae0ae540d47b7a2486b2eea04f42df5f7b5 Mon Sep 17 00:00:00 2001 From: Fredrik Danebjer Date: Mon, 18 Mar 2024 11:44:02 +0100 Subject: [PATCH 1788/2402] Bluetooth: Audio: Broadcast Assistant: Check add_source duplication Added a check for checking duplication when adding a source in the broadcast assistant, as per requirement in BAP 6.5.4. It is not permitted to add a source such that a combination of broadcast_id, adv_sid and address type would result in same triple of values. Added a recv_state struct to cache these values when read, and moved past_avail and srd_ids into this as well. Signed-off-by: Fredrik Danebjer --- .../bluetooth/audio/bap_broadcast_assistant.c | 69 ++++++++++++++----- 1 file changed, 50 insertions(+), 19 deletions(-) diff --git a/subsys/bluetooth/audio/bap_broadcast_assistant.c b/subsys/bluetooth/audio/bap_broadcast_assistant.c index e8a335a0321..95163e8fe2e 100644 --- a/subsys/bluetooth/audio/bap_broadcast_assistant.c +++ b/subsys/bluetooth/audio/bap_broadcast_assistant.c @@ -3,6 +3,7 @@ /* * Copyright (c) 2019 Bose Corporation * Copyright (c) 2022-2023 Nordic Semiconductor ASA + * Copyright (c) 2024 Demant A/S * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,17 +35,21 @@ LOG_MODULE_REGISTER(bt_bap_broadcast_assistant, CONFIG_BT_BAP_BROADCAST_ASSISTAN #define MINIMUM_RECV_STATE_LEN 15 +struct bap_broadcast_assistant_recv_state_info { + uint8_t src_id; + bt_addr_le_t addr; + uint8_t adv_sid; + uint32_t broadcast_id; + + /** Cached PAST available */ + bool past_avail; +}; + struct bap_broadcast_assistant_instance { struct bt_conn *conn; bool scanning; uint8_t pa_sync; uint8_t recv_state_cnt; - /* Source ID cache so that we can notify application about - * which source ID was removed - */ - uint8_t src_ids[CONFIG_BT_BAP_BROADCAST_ASSISTANT_RECV_STATE_COUNT]; - /** Cached PAST available */ - bool past_avail[CONFIG_BT_BAP_BROADCAST_ASSISTANT_RECV_STATE_COUNT]; uint16_t start_handle; uint16_t end_handle; @@ -62,6 +67,9 @@ struct bap_broadcast_assistant_instance { struct k_work_delayable bap_read_work; uint16_t long_read_handle; + + struct bap_broadcast_assistant_recv_state_info recv_states + [CONFIG_BT_BAP_BROADCAST_ASSISTANT_RECV_STATE_COUNT]; }; static sys_slist_t broadcast_assistant_cbs = SYS_SLIST_STATIC_INIT(&broadcast_assistant_cbs); @@ -273,10 +281,10 @@ static uint8_t parse_and_send_recv_state(struct bt_conn *conn, uint16_t handle, return BT_GATT_ITER_STOP; } - broadcast_assistant.src_ids[index] = recv_state->src_id; - broadcast_assistant.past_avail[index] = past_available(conn, - &recv_state->addr, - recv_state->adv_sid); + broadcast_assistant.recv_states[index].src_id = recv_state->src_id; + broadcast_assistant.recv_states[index].past_avail = past_available(conn, + &recv_state->addr, + recv_state->adv_sid); bap_broadcast_assistant_recv_state_changed(conn, 0, recv_state); @@ -434,9 +442,9 @@ static uint8_t notify_handler(struct bt_conn *conn, return parse_and_send_recv_state(conn, handle, data, length, &recv_state); } } else { - broadcast_assistant.past_avail[index] = false; + broadcast_assistant.recv_states[index].past_avail = false; bap_broadcast_assistant_recv_state_removed(conn, 0, - broadcast_assistant.src_ids[index]); + broadcast_assistant.recv_states[index].src_id); } return BT_GATT_ITER_CONTINUE; @@ -471,8 +479,14 @@ static uint8_t read_recv_state_cb(struct bt_conn *conn, uint8_t err, if (cb_err != 0) { LOG_DBG("Invalid receive state"); } else { - broadcast_assistant.src_ids[index] = recv_state.src_id; - broadcast_assistant.past_avail[index] = + struct bap_broadcast_assistant_recv_state_info *stored_state = + &broadcast_assistant.recv_states[index]; + + stored_state->src_id = recv_state.src_id; + stored_state->adv_sid = recv_state.adv_sid; + stored_state->broadcast_id = recv_state.broadcast_id; + bt_addr_le_copy(&stored_state->addr, &recv_state.addr); + broadcast_assistant.recv_states[index].past_avail = past_available(conn, &recv_state.addr, recv_state.adv_sid); } @@ -782,8 +796,9 @@ static int broadcast_assistant_reset(struct bap_broadcast_assistant_instance *in (void)k_work_cancel_delayable(&inst->bap_read_work); for (int i = 0U; i < CONFIG_BT_BAP_BROADCAST_ASSISTANT_RECV_STATE_COUNT; i++) { - inst->src_ids[i] = 0U; - inst->past_avail[i] = false; + memset(&inst->recv_states[i], 0, + sizeof(struct bap_broadcast_assistant_recv_state_info)); + inst->recv_states[i].past_avail = false; inst->recv_state_handles[i] = 0U; } @@ -998,6 +1013,7 @@ int bt_bap_broadcast_assistant_add_src(struct bt_conn *conn, const struct bt_bap_broadcast_assistant_add_src_param *param) { struct bt_bap_bass_cp_add_src *cp; + struct bap_broadcast_assistant_recv_state_info *state; if (conn == NULL) { LOG_DBG("conn is NULL"); @@ -1013,6 +1029,21 @@ int bt_bap_broadcast_assistant_add_src(struct bt_conn *conn, return -EBUSY; } + /* Check if this operation would result in a duplicate before proceeding */ + for (size_t i = 0; i < ARRAY_SIZE(broadcast_assistant.recv_states); i++) { + state = &broadcast_assistant.recv_states[i]; + + if (param->addr.type == state->addr.type && param->adv_sid == state->adv_sid && + param->broadcast_id == state->broadcast_id) { + LOG_DBG("recv_state using broadcast_id=0x%06X, adv_sid=0x%02X, and " + "addr.type=0x%02X already exists with src_id=0x%02X", + param->broadcast_id, param->adv_sid, param->addr.type, + state->src_id); + + return -EINVAL; + } + } + /* Reset buffer before using */ net_buf_simple_reset(&att_buf); cp = net_buf_simple_add(&att_buf, sizeof(*cp)); @@ -1108,10 +1139,10 @@ int bt_bap_broadcast_assistant_mod_src(struct bt_conn *conn, */ known_recv_state = false; past_avail = false; - for (size_t i = 0; i < ARRAY_SIZE(broadcast_assistant.src_ids); i++) { - if (broadcast_assistant.src_ids[i] == param->src_id) { + for (size_t i = 0; i < ARRAY_SIZE(broadcast_assistant.recv_states); i++) { + if (broadcast_assistant.recv_states[i].src_id == param->src_id) { known_recv_state = true; - past_avail = broadcast_assistant.past_avail[i]; + past_avail = broadcast_assistant.recv_states[i].past_avail; break; } } From 5be02da6364e2b7a26b2385684fce044e8e3d52c Mon Sep 17 00:00:00 2001 From: Nithin Ramesh Myliattil Date: Wed, 3 Apr 2024 07:57:14 +0200 Subject: [PATCH 1789/2402] Bluetooth: Audio: Broadcast Assistant: add broadcast src duplicate function Moved the check of broadcast src duplicate to function while adding source. Signed-off-by: Nithin Ramesh Myliattil --- .../bluetooth/audio/bap_broadcast_assistant.c | 50 +++++++++++-------- 1 file changed, 30 insertions(+), 20 deletions(-) diff --git a/subsys/bluetooth/audio/bap_broadcast_assistant.c b/subsys/bluetooth/audio/bap_broadcast_assistant.c index 95163e8fe2e..aef75d072e4 100644 --- a/subsys/bluetooth/audio/bap_broadcast_assistant.c +++ b/subsys/bluetooth/audio/bap_broadcast_assistant.c @@ -37,12 +37,11 @@ LOG_MODULE_REGISTER(bt_bap_broadcast_assistant, CONFIG_BT_BAP_BROADCAST_ASSISTAN struct bap_broadcast_assistant_recv_state_info { uint8_t src_id; - bt_addr_le_t addr; - uint8_t adv_sid; - uint32_t broadcast_id; - /** Cached PAST available */ bool past_avail; + uint8_t adv_sid; + uint32_t broadcast_id; + bt_addr_le_t addr; }; struct bap_broadcast_assistant_instance { @@ -444,7 +443,7 @@ static uint8_t notify_handler(struct bt_conn *conn, } else { broadcast_assistant.recv_states[index].past_avail = false; bap_broadcast_assistant_recv_state_removed(conn, 0, - broadcast_assistant.recv_states[index].src_id); + broadcast_assistant.recv_states[index].src_id); } return BT_GATT_ITER_CONTINUE; @@ -781,6 +780,28 @@ static struct bt_le_scan_cb scan_cb = { .recv = scan_recv }; +/* BAP 6.5.4 states that the Broadcast Assistant shall not initiate the Add Source operation + * if the operation would result in duplicate values for the combined Source_Address_Type, + * Source_Adv_SID, and Broadcast_ID fields of any Broadcast Receive State characteristic exposed + * by the Scan Delegator. + */ +static bool broadcast_src_is_duplicate(uint32_t broadcast_id, uint8_t adv_sid, uint8_t addr_type) +{ + for (size_t i = 0; i < ARRAY_SIZE(broadcast_assistant.recv_states); i++) { + const struct bap_broadcast_assistant_recv_state_info *state = + &broadcast_assistant.recv_states[i]; + + if (state != NULL && state->broadcast_id == broadcast_id && + state->adv_sid == adv_sid && state->addr.type == addr_type) { + LOG_DBG("recv_state already exists at src_id=0x%02X", state->src_id); + + return true; + } + } + + return false; +} + /****************************** PUBLIC API ******************************/ static int broadcast_assistant_reset(struct bap_broadcast_assistant_instance *inst) @@ -796,8 +817,7 @@ static int broadcast_assistant_reset(struct bap_broadcast_assistant_instance *in (void)k_work_cancel_delayable(&inst->bap_read_work); for (int i = 0U; i < CONFIG_BT_BAP_BROADCAST_ASSISTANT_RECV_STATE_COUNT; i++) { - memset(&inst->recv_states[i], 0, - sizeof(struct bap_broadcast_assistant_recv_state_info)); + memset(&inst->recv_states[i], 0, sizeof(inst->recv_states[i])); inst->recv_states[i].past_avail = false; inst->recv_state_handles[i] = 0U; } @@ -1013,7 +1033,6 @@ int bt_bap_broadcast_assistant_add_src(struct bt_conn *conn, const struct bt_bap_broadcast_assistant_add_src_param *param) { struct bt_bap_bass_cp_add_src *cp; - struct bap_broadcast_assistant_recv_state_info *state; if (conn == NULL) { LOG_DBG("conn is NULL"); @@ -1030,20 +1049,11 @@ int bt_bap_broadcast_assistant_add_src(struct bt_conn *conn, } /* Check if this operation would result in a duplicate before proceeding */ - for (size_t i = 0; i < ARRAY_SIZE(broadcast_assistant.recv_states); i++) { - state = &broadcast_assistant.recv_states[i]; - - if (param->addr.type == state->addr.type && param->adv_sid == state->adv_sid && - param->broadcast_id == state->broadcast_id) { - LOG_DBG("recv_state using broadcast_id=0x%06X, adv_sid=0x%02X, and " - "addr.type=0x%02X already exists with src_id=0x%02X", - param->broadcast_id, param->adv_sid, param->addr.type, - state->src_id); + if (broadcast_src_is_duplicate(param->broadcast_id, param->adv_sid, param->addr.type)) { + LOG_DBG("Broadcast source already exists"); - return -EINVAL; - } + return -EINVAL; } - /* Reset buffer before using */ net_buf_simple_reset(&att_buf); cp = net_buf_simple_add(&att_buf, sizeof(*cp)); From e44c0987b9779b63ed9e111999a5a539efc48a0d Mon Sep 17 00:00:00 2001 From: Steven Chang Date: Sun, 31 Mar 2024 12:14:34 +0800 Subject: [PATCH 1790/2402] driver: watchdog: prevent floating point usage Prevent the use of floating point operations Signed-off-by: Steven Chang --- drivers/watchdog/wdt_ene_kb1200.c | 2 +- soc/ene/kb1200/reg/wdt.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/wdt_ene_kb1200.c b/drivers/watchdog/wdt_ene_kb1200.c index 008b4623de8..26a20c00968 100644 --- a/drivers/watchdog/wdt_ene_kb1200.c +++ b/drivers/watchdog/wdt_ene_kb1200.c @@ -82,7 +82,7 @@ static int wdt_kb1200_install_timeout(const struct device *dev, data->timeout_installed = false; return -EINVAL; } - cfg->wdt->WDTM = (config->window.max) / WDT_SAMPLE_TIME; + cfg->wdt->WDTM = (config->window.max * 1000) / WDT_TICK_TIME_US; /* (HW design) The counter match value must be >= 3 */ if (cfg->wdt->WDTM < WDT_MIN_CNT) { data->timeout_installed = false; diff --git a/soc/ene/kb1200/reg/wdt.h b/soc/ene/kb1200/reg/wdt.h index cd053327069..22997329534 100644 --- a/soc/ene/kb1200/reg/wdt.h +++ b/soc/ene/kb1200/reg/wdt.h @@ -24,7 +24,7 @@ struct wdt_regs { }; #define WDT_MIN_CNT 3U -#define WDT_SAMPLE_TIME 31.25 +#define WDT_TICK_TIME_US 31250 #define WDT_RESET_WHOLE_CHIP_WO_GPIO 0 #define WDT_RESET_WHOLE_CHIP 1 From 36f4ef70a91ab89def3619eed867031e65b08ff9 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Wed, 3 Apr 2024 15:19:48 +0200 Subject: [PATCH 1791/2402] drivers: can: transceiver: gpio: automatically select GPIO Automatically select CONFIG_GPIO when the GPIO-controlled CAN transceiver driver is enabled. Update board configurations to benefit from this. Signed-off-by: Henrik Brix Andersen --- boards/nxp/mr_canhubk3/Kconfig.defconfig | 7 ------- boards/nxp/ucans32k1sic/Kconfig.defconfig | 7 ------- drivers/can/transceiver/Kconfig | 2 +- 3 files changed, 1 insertion(+), 15 deletions(-) diff --git a/boards/nxp/mr_canhubk3/Kconfig.defconfig b/boards/nxp/mr_canhubk3/Kconfig.defconfig index 02710328d68..9d280f7cf3f 100644 --- a/boards/nxp/mr_canhubk3/Kconfig.defconfig +++ b/boards/nxp/mr_canhubk3/Kconfig.defconfig @@ -23,13 +23,6 @@ config WDT_NXP_FS26_INIT_PRIORITY endif # WDT_NXP_FS26 endif # SPI -if CAN - -config GPIO - default y - -endif # CAN - if NETWORKING config NET_L2_ETHERNET diff --git a/boards/nxp/ucans32k1sic/Kconfig.defconfig b/boards/nxp/ucans32k1sic/Kconfig.defconfig index 9c6542625ba..9b896847c27 100644 --- a/boards/nxp/ucans32k1sic/Kconfig.defconfig +++ b/boards/nxp/ucans32k1sic/Kconfig.defconfig @@ -10,11 +10,4 @@ config UART_CONSOLE endif # SERIAL -if CAN - -config GPIO - default y - -endif # CAN - endif # BOARD_UCANS32K1SIC diff --git a/drivers/can/transceiver/Kconfig b/drivers/can/transceiver/Kconfig index 91af7a17828..e6af354ff41 100644 --- a/drivers/can/transceiver/Kconfig +++ b/drivers/can/transceiver/Kconfig @@ -15,7 +15,7 @@ config CAN_TRANSCEIVER_GPIO bool "GPIO controlled CAN transceiver" default y depends on DT_HAS_CAN_TRANSCEIVER_GPIO_ENABLED - depends on GPIO + select GPIO help Enable support for GPIO controlled CAN transceivers. From 6aa4ade3ad69415594a7c7d70d985d42ba4e572a Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Tue, 2 Apr 2024 15:44:53 +0200 Subject: [PATCH 1792/2402] MAINTAINERS: STM32 Platforms: Reflect recent changes @Desvauxm-st is now retired and @ABOSTM is not working anymore on Zephyr since some time now. Remove them and add @ajarmouni-st, which has been contributing for some time now. Signed-off-by: Erwan Gouriou --- MAINTAINERS.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 9cad7645513..e5de1c6718d 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3541,10 +3541,9 @@ STM32 Platforms: maintainers: - erwango collaborators: - - ABOSTM + - ajarmouni-st - FRASTM - gautierg-st - - Desvauxm-st - GeorgeCGV files: - boards/st/ From 377756e0f9df0f98f53f4259fd7c07ebca9fdf36 Mon Sep 17 00:00:00 2001 From: Konrad Derda Date: Tue, 2 Apr 2024 12:57:46 +0200 Subject: [PATCH 1793/2402] net: ipv6: mld: fix handling of MLD queries This commit fixes an issue where due to inverted logic (static function returned 0 on success but the caller expected true/false) the MLDv2 reports were silently dropped. Signed-off-by: Konrad Derda --- subsys/net/ip/ipv6_mld.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/subsys/net/ip/ipv6_mld.c b/subsys/net/ip/ipv6_mld.c index a7c3971e8ef..2bd67a08c8e 100644 --- a/subsys/net/ip/ipv6_mld.c +++ b/subsys/net/ip/ipv6_mld.c @@ -124,16 +124,19 @@ static int mld_create_packet(struct net_pkt *pkt, uint16_t count) static int mld_send(struct net_pkt *pkt) { + int ret; + net_pkt_cursor_init(pkt); net_ipv6_finalize(pkt, IPPROTO_ICMPV6); - if (net_send_data(pkt) < 0) { + ret = net_send_data(pkt); + if (ret < 0) { net_stats_update_icmp_drop(net_pkt_iface(pkt)); net_stats_update_ipv6_mld_drop(net_pkt_iface(pkt)); net_pkt_unref(pkt); - return -1; + return ret; } net_stats_update_icmp_sent(net_pkt_iface(pkt)); @@ -251,11 +254,12 @@ int net_ipv6_mld_leave(struct net_if *iface, const struct in6_addr *addr) return ret; } -static void send_mld_report(struct net_if *iface) +static int send_mld_report(struct net_if *iface) { struct net_if_ipv6 *ipv6 = iface->config.ip.ipv6; struct net_pkt *pkt; int i, count = 0; + int ret; NET_ASSERT(ipv6); @@ -273,10 +277,11 @@ static void send_mld_report(struct net_if *iface) AF_INET6, IPPROTO_ICMPV6, PKT_WAIT_TIME); if (!pkt) { - return; + return -ENOBUFS; } - if (mld_create_packet(pkt, count)) { + ret = mld_create_packet(pkt, count); + if (ret < 0) { goto drop; } @@ -285,18 +290,22 @@ static void send_mld_report(struct net_if *iface) continue; } - if (!mld_create(pkt, &ipv6->mcast[i].address.in6_addr, - NET_IPV6_MLDv2_MODE_IS_EXCLUDE, 0)) { + ret = mld_create(pkt, &ipv6->mcast[i].address.in6_addr, + NET_IPV6_MLDv2_MODE_IS_EXCLUDE, 0); + if (ret < 0) { goto drop; } } - if (!mld_send(pkt)) { - return; + ret = mld_send(pkt); + if (ret < 0) { + return ret; } drop: net_pkt_unref(pkt); + + return ret; } #define dbg_addr(action, pkt_str, src, dst) \ @@ -361,9 +370,7 @@ static int handle_mld_query(struct net_icmp_ctx *ctx, goto drop; } - send_mld_report(net_pkt_iface(pkt)); - - return 0; + return send_mld_report(net_pkt_iface(pkt)); drop: net_stats_update_ipv6_mld_drop(net_pkt_iface(pkt)); From d4dc516119e21632124c00c8b97f334ba315d397 Mon Sep 17 00:00:00 2001 From: Konrad Derda Date: Tue, 2 Apr 2024 12:45:09 +0200 Subject: [PATCH 1794/2402] tests: net: mld: fix waiting for MLDv2 report after query This commit fixes 'test_verify_send_report()' function as it was not properly waiting for a MLDv2 report after sending a query. The asserted value was set for the previous report sent after joining a group. Signed-off-by: Konrad Derda --- tests/net/mld/prj.conf | 2 +- tests/net/mld/src/main.c | 22 ++++++++++++++++++---- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/tests/net/mld/prj.conf b/tests/net/mld/prj.conf index 3ce6478f4c8..06e5cd0d23c 100644 --- a/tests/net/mld/prj.conf +++ b/tests/net/mld/prj.conf @@ -21,5 +21,5 @@ CONFIG_NET_BUF_TX_COUNT=20 CONFIG_NET_MGMT=y CONFIG_NET_MGMT_EVENT=y CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=4 -CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT=4 +CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT=5 CONFIG_NET_SOCKETS=y diff --git a/tests/net/mld/src/main.c b/tests/net/mld/src/main.c index 171418b21a8..25d3c715a87 100644 --- a/tests/net/mld/src/main.c +++ b/tests/net/mld/src/main.c @@ -484,25 +484,39 @@ static void test_catch_query(void) static void test_verify_send_report(void) { + join_mldv2_capable_routers_group(); + is_query_received = false; is_report_sent = false; ignore_already = true; + k_sem_reset(&wait_data); + test_join_group(); + k_yield(); + + /* Did we send a report? */ + if (k_sem_take(&wait_data, K_MSEC(WAIT_TIME))) { + zassert_true(0, "Timeout while waiting for report"); + } + + k_sem_reset(&wait_data); + + is_report_sent = false; send_query(net_if_get_first_by_type(&NET_L2_GET_NAME(DUMMY))); k_yield(); /* Did we send a report? */ if (k_sem_take(&wait_data, K_MSEC(WAIT_TIME))) { - zassert_true(0, "Timeout while waiting report"); + zassert_true(0, "Timeout while waiting for report"); } - if (!is_report_sent) { - zassert_true(0, "Report not sent"); - } + zassert_true(is_report_sent, "Report not sent"); + + leave_mldv2_capable_routers_group(); } /* This value should be longer that the one in net_if.c when DAD timeouts */ From f7e64c87032493c7c75562ea627b70649c0d18df Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 22 Mar 2024 10:06:17 -0600 Subject: [PATCH 1795/2402] drivers: serial: rpi_pico: Enable uart FIFO A few lines above this change explicitly enable the UART FIFO. Then this line, goes and disables it. This seems to be from a workaround where the parity and stop bits are not coming in correctly in the config. Fixing that will be another patch. But, the FIFO should always be enabled. This is visible when trying to use bit rates that are reasonably fast. Even in IRQ mode, with a sufficient bit rate, bytes are readily dropped. Tested on a Sparkfun Promicro rp2040 board. Signed-off-by: David Brown --- drivers/serial/uart_rpi_pico.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/serial/uart_rpi_pico.c b/drivers/serial/uart_rpi_pico.c index a423c94cc9c..14c355a9913 100644 --- a/drivers/serial/uart_rpi_pico.c +++ b/drivers/serial/uart_rpi_pico.c @@ -191,7 +191,6 @@ static int uart_rpi_init(const struct device *dev) data->uart_config.parity = UART_CFG_PARITY_NONE; data->uart_config.stop_bits = UART_CFG_STOP_BITS_1; uart_rpi_set_format(dev, &data->uart_config); - hw_clear_bits(&uart_hw->lcr_h, UART_UARTLCR_H_FEN_BITS); uart_hw->dr = 0U; if (data->uart_config.flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS) { From 4844dabf3abf531855f1ea2ec948686dc4c3b39f Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Mon, 25 Mar 2024 18:58:12 +0100 Subject: [PATCH 1796/2402] Samples: Bluetooth: Add encrypted broadcast audio source Add support for supplying a broadcast code to the broadcast audio sample, which will, if non-empty, encrypt the broadcast. Signed-off-by: Emil Gydesen --- samples/bluetooth/broadcast_audio_source/Kconfig | 7 +++++++ samples/bluetooth/broadcast_audio_source/src/main.c | 12 ++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/samples/bluetooth/broadcast_audio_source/Kconfig b/samples/bluetooth/broadcast_audio_source/Kconfig index 683eeaf9dbf..0189da81b69 100644 --- a/samples/bluetooth/broadcast_audio_source/Kconfig +++ b/samples/bluetooth/broadcast_audio_source/Kconfig @@ -38,4 +38,11 @@ config USE_USB_AUDIO_INPUT select USB_DEVICE_AUDIO select RING_BUFFER +config BROADCAST_CODE + string "The broadcast code (if any) to use for encrypted broadcast" + default "" + help + Setting a non-empty string for this option will encrypt the broadcast using this + string as the broadcast code. The length of the string shall be between 1 and 16 octets. + source "Kconfig.zephyr" diff --git a/samples/bluetooth/broadcast_audio_source/src/main.c b/samples/bluetooth/broadcast_audio_source/src/main.c index 80def0ee960..c63a1337992 100644 --- a/samples/bluetooth/broadcast_audio_source/src/main.c +++ b/samples/bluetooth/broadcast_audio_source/src/main.c @@ -9,6 +9,9 @@ #include #include +BUILD_ASSERT(strlen(CONFIG_BROADCAST_CODE) <= BT_AUDIO_BROADCAST_CODE_SIZE, + "Invalid broadcast code"); + /* Zephyr Controller works best while Extended Advertising interval to be a multiple * of the ISO Interval minus 10 ms (max. advertising random delay). This is * required to place the AUX_ADV_IND PDUs in a non-overlapping interval with the @@ -384,7 +387,7 @@ static int setup_broadcast_source(struct bt_bap_broadcast_source **source) stream_params[CONFIG_BT_BAP_BROADCAST_SRC_STREAM_COUNT]; struct bt_bap_broadcast_source_subgroup_param subgroup_param[CONFIG_BT_BAP_BROADCAST_SRC_SUBGROUP_COUNT]; - struct bt_bap_broadcast_source_param create_param; + struct bt_bap_broadcast_source_param create_param = {0}; const size_t streams_per_subgroup = ARRAY_SIZE(stream_params) / ARRAY_SIZE(subgroup_param); uint8_t left[] = {BT_AUDIO_CODEC_DATA(BT_AUDIO_CODEC_CFG_CHAN_ALLOC, BT_BYTES_LIST_LE32(BT_AUDIO_LOCATION_FRONT_LEFT))}; @@ -408,9 +411,14 @@ static int setup_broadcast_source(struct bt_bap_broadcast_source **source) create_param.params_count = ARRAY_SIZE(subgroup_param); create_param.params = subgroup_param; create_param.qos = &preset_active.qos; - create_param.encryption = false; + create_param.encryption = strlen(CONFIG_BROADCAST_CODE) > 0; create_param.packing = BT_ISO_PACKING_SEQUENTIAL; + if (create_param.encryption) { + memcpy(create_param.broadcast_code, CONFIG_BROADCAST_CODE, + strlen(CONFIG_BROADCAST_CODE)); + } + printk("Creating broadcast source with %zu subgroups with %zu streams\n", ARRAY_SIZE(subgroup_param), ARRAY_SIZE(subgroup_param) * streams_per_subgroup); From 0a44403c4635659ee455299f8311b3a5165efdd0 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Wed, 9 Aug 2023 18:13:55 -0700 Subject: [PATCH 1797/2402] doc: pm: Change section in device pm s/System Power Management/System Managed Device Power Management/g System Power Management is confusing and does not tell anything about device. Change it for something more explicit. Signed-off-by: Flavio Ceolin --- doc/services/pm/device.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/services/pm/device.rst b/doc/services/pm/device.rst index 3eb936942ea..f6cce108399 100644 --- a/doc/services/pm/device.rst +++ b/doc/services/pm/device.rst @@ -13,7 +13,7 @@ advantage of the device power management subsystem. Zephyr supports two types of device power management: - :ref:`Device Runtime Power Management ` - - :ref:`System Power Management ` + - :ref:`System-Managed Device Power Management ` .. _pm-device-runtime-pm: @@ -37,8 +37,8 @@ For more information, see :ref:`pm-device-runtime`. .. _pm-device-system-pm: -System Power Management -*********************** +System-Managed Device Power Management +************************************** When using this type, device power management is mostly done inside :c:func:`pm_system_suspend()` along with entering a CPU or SOC power state. From 6c68d62e48b18274d6ac161ddb45e6a2fd544226 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Wed, 9 Aug 2023 15:16:34 -0700 Subject: [PATCH 1798/2402] doc: pm: Update device power management documentation Update information about device power management. Signed-off-by: Flavio Ceolin --- doc/services/pm/api/index.rst | 2 + doc/services/pm/device.rst | 86 ++++++++++++++++++++++++++--------- 2 files changed, 66 insertions(+), 22 deletions(-) diff --git a/doc/services/pm/api/index.rst b/doc/services/pm/api/index.rst index 05c01103202..bbf80ab61ae 100644 --- a/doc/services/pm/api/index.rst +++ b/doc/services/pm/api/index.rst @@ -28,6 +28,8 @@ Device PM APIs .. doxygengroup:: subsys_pm_device +.. _device_runtime_apis: + Device Runtime PM APIs ********************** diff --git a/doc/services/pm/device.rst b/doc/services/pm/device.rst index f6cce108399..094297eeea8 100644 --- a/doc/services/pm/device.rst +++ b/doc/services/pm/device.rst @@ -10,7 +10,7 @@ setting :kconfig:option:`CONFIG_PM_DEVICE` to ``y``. When this option is selected, device drivers implementing power management will be able to take advantage of the device power management subsystem. -Zephyr supports two types of device power management: +Zephyr supports two methods of device power management: - :ref:`Device Runtime Power Management ` - :ref:`System-Managed Device Power Management ` @@ -20,18 +20,50 @@ Zephyr supports two types of device power management: Device Runtime Power Management ******************************* -In this method, the application or any component that deals with devices directly -and has the best knowledge of their use, performs the device power management. This -saves power if some devices that are not in use can be turned off or put -in power saving mode. This method allows saving power even when the CPU is -active. The components that use the devices need to be power aware and should -be able to make decisions related to managing device power. - -When using this type of device power management, the kernel can change CPU -power states quickly when :c:func:`pm_system_suspend()` gets called. This is -because it does not need to spend time doing device power management if the -devices are already put in the appropriate power state by the application or -component managing the devices. +Device runtime power management involves coordinated interaction between +device drivers, subsystems, and applications. While device drivers +play a crucial role in directly controlling the power state of +devices, the decision to suspend or resume a device can also be +influenced by higher layers of the software stack. + +Each layer—device drivers, subsystems, and applications—can operate +independently without needing to know about the specifics of the other +layers because the subsystem uses reference count to check when it needs +to suspend or resume a device. + +- **Device drivers** are responsible for managing the + power state of devices. They interact directly with the hardware to + put devices into low-power states (suspend) when they are not in + use, and bring them back (resume) when needed. Drivers should use the + :ref:`device runtime power management APIs ` provided + by Zephyr to control the power state of devices. + +- **Subsystems**, such as sensors, file systems, + and network, can also influence device power management. + Subsystems may have better knowledge about the overall system + state and workload, allowing them to make informed decisions about + when to suspend or resume devices. For example, a networking + subsystem may decide to keep a network interface powered on if it + expects network activity in the near future. + +- **Applications** running on Zephyr can impact device + power management as well. An application may have specific + requirements regarding device usage and power consumption. For + example, an application that streams data over a network may need + to keep the network interface powered on continuously. + +Coordination between device drivers, subsystems, and applications is +key to efficient device power management. For example, a device driver +may not know that a subsystem will perform a series of sequential +operations that require a device to remain powered on. In such cases, +the subsystem can use device runtime power management to ensure that +the device remains in an active state until the operations are +complete. + +When using this Device Runtime Power Management, the System Power +Management subsystem is able to change power states quickly because it +does not need to spend time suspending and resuming devices that are +runtime enabled. For more information, see :ref:`pm-device-runtime`. @@ -40,7 +72,7 @@ For more information, see :ref:`pm-device-runtime`. System-Managed Device Power Management ************************************** -When using this type, device power management is mostly done inside +When using this method, device power management is mostly done inside :c:func:`pm_system_suspend()` along with entering a CPU or SOC power state. If a decision to enter a CPU lower power state is made, the power management @@ -56,20 +88,30 @@ suspended. As functions in this context cannot block, transitions that intend to use blocking APIs **must** check whether they can do so with :c:func:`k_can_yield`. -This type of device power management can be useful when the application is not -power aware and does not implement runtime device power management. Though, -:ref:`Device Runtime Power Management ` is the **preferred** -option for device power management. +This method of device power management can be useful in the following scenarios: + +- Systems with no device requiring any blocking operations when suspending and + resuming. This implementation is reasonably simpler than device runtime + power management. +- For devices that can not make any power management decision and have to be + always active. For example a firmware using Zephyr that is controlled by an + external entity (e.g Host CPU). In this scenario, some devices have to be + always active and should be suspended together with the SoC when requested by + this external entity. + +It is important to emphasize that this method has drawbacks (see above) and +:ref:`Device Runtime Power Management ` is the +**preferred** method for implementing device power management. .. note:: - When using this type of device power management, the CPU will only enter - a low power state only if no device is in the middle of a hardware + When using this method of device power management, the CPU will enter + a low power state only if no devices are in the middle of a hardware transaction that cannot be interrupted. .. note:: - This type of device power management is disabled when + This method of device power management is disabled when :kconfig:option:`CONFIG_PM_DEVICE_RUNTIME_EXCLUSIVE` is set to ``y`` (that is the default value when :kconfig:option:`CONFIG_PM_DEVICE_RUNTIME` is enabled) @@ -82,7 +124,7 @@ Device Power Management States ****************************** The power management subsystem defines device states in -:c:enum:`pm_device_state`. This type is used to track power states of +:c:enum:`pm_device_state`. This method is used to track power states of a particular device. It is important to emphasize that, although the state is tracked by the subsystem, it is the responsibility of each device driver to handle device actions(:c:enum:`pm_device_action`) which change device state. From 326f0801319ac89975847fd60c6e4488abaa6b3b Mon Sep 17 00:00:00 2001 From: Dominik Ermel Date: Wed, 3 Apr 2024 19:43:53 +0000 Subject: [PATCH 1799/2402] xtensa: dc233c: Fix build warning in DTS on leading zeros Leading zeros removed from unit name. Signed-off-by: Dominik Ermel --- dts/xtensa/dc233c.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/xtensa/dc233c.dtsi b/dts/xtensa/dc233c.dtsi index 81f5042c586..88518de8ebe 100644 --- a/dts/xtensa/dc233c.dtsi +++ b/dts/xtensa/dc233c.dtsi @@ -22,7 +22,7 @@ * Although RAM is of size 128MB (0x08000000), limit this to 16MB so * fewer L2 page table entries are needed when MMU is enabled. */ - sram0: memory@00000000 { + sram0: memory@0 { device_type = "memory"; compatible = "mmio-sram"; reg = <0x00000000 0x01000000>; From f643f3a6cf6bafd6338c090f4413e34eb3ed806c Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Mon, 25 Mar 2024 08:15:36 -0400 Subject: [PATCH 1800/2402] drivers: serial: bt: Make TX flush non-deferrable To prevent postponing data flush until filling fifo. Now the flush will occur at the scheduled time, regardless of subsequent poll_out reqs. Signed-off-by: Luis Ubieda --- drivers/serial/uart_bt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/uart_bt.c b/drivers/serial/uart_bt.c index bf9bf98a653..ad450eea9aa 100644 --- a/drivers/serial/uart_bt.c +++ b/drivers/serial/uart_bt.c @@ -169,7 +169,7 @@ static void uart_bt_poll_out(const struct device *dev, unsigned char c) * data, so more than one byte is transmitted (e.g: when poll_out is * called inside a for-loop). */ - k_work_reschedule(&dev_data->uart.tx_work, K_MSEC(1)); + k_work_schedule(&dev_data->uart.tx_work, K_MSEC(1)); } } From 42ded807aa7580115d56ab0f449a9cac79876aa1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 25 Mar 2024 17:25:24 +0100 Subject: [PATCH 1801/2402] samples: logging: logger: Add harness to the BT configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add harness as twister by default looks into ztest results and in bluetooth configuration they won't be find. Signed-off-by: Krzysztof Chruściński --- samples/subsys/logging/logger/sample.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/samples/subsys/logging/logger/sample.yaml b/samples/subsys/logging/logger/sample.yaml index 413be4f190d..fc3e03a69dc 100644 --- a/samples/subsys/logging/logger/sample.yaml +++ b/samples/subsys/logging/logger/sample.yaml @@ -38,6 +38,7 @@ tests: - logging - bluetooth filter: CONFIG_DT_HAS_ZEPHYR_NUS_UART_ENABLED + harness: bluetooth_nus arch_exclude: - posix extra_args: From 7fd73716d0e511a43f7afe685d7c94d5d926c499 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 2 Apr 2024 15:46:39 +0200 Subject: [PATCH 1802/2402] manifest: Update hal_nordic with fix for nrf_dma_accessible_check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix address checking function for nrf54h20. Signed-off-by: Krzysztof Chruściński --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index a05d5f35aee..3af54307b0d 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: 13ac55b5b52c905642e9c54f069109d188aa5840 + revision: 7803a3e6b606ddde8df9a10108d7251a108bd7c9 path: modules/hal/nordic groups: - hal From fd1a129a3e6330bdf44324e47ac7638dd6cdf5a5 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Wed, 3 Apr 2024 15:47:31 -0500 Subject: [PATCH 1803/2402] drivers: eth_nxp_enet_qos: Fixed unused variable Fix warning caused by unused variable when CONFIG_NET_STATISTICS_ETHERNET is disabled. Signed-off-by: Declan Snyder --- .../ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c index bba9d1df7e1..ed9a72cad4a 100644 --- a/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c +++ b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c @@ -145,13 +145,13 @@ static void tx_dma_done(struct k_work *work) fragment = fragment->frags; } - net_pkt_frag_unref(tx_data->tx_header); + net_pkt_frag_unref(data->tx.tx_header); net_pkt_unref(pkt); eth_stats_update_pkts_tx(data->iface); /* Allows another send */ - k_sem_give(&tx_data->tx_sem); + k_sem_give(&data->tx.tx_sem); } static enum ethernet_hw_caps eth_nxp_enet_qos_get_capabilities(const struct device *dev) @@ -165,7 +165,7 @@ static void eth_nxp_enet_qos_rx(struct k_work *work) CONTAINER_OF(work, struct nxp_enet_qos_rx_data, rx_work); struct nxp_enet_qos_mac_data *data = CONTAINER_OF(rx_data, struct nxp_enet_qos_mac_data, rx); - volatile union nxp_enet_qos_rx_desc *desc_arr = rx_data->descriptors; + volatile union nxp_enet_qos_rx_desc *desc_arr = data->rx.descriptors; volatile union nxp_enet_qos_rx_desc *desc; struct net_pkt *pkt; struct net_buf *new_buf; @@ -206,7 +206,7 @@ static void eth_nxp_enet_qos_rx(struct k_work *work) goto error; } - buf = rx_data->reserved_bufs[i]; + buf = data->rx.reserved_bufs[i]; pkt_len = desc->write.control3 & DESC_RX_PKT_LEN; LOG_DBG("Receiving RX packet"); @@ -227,7 +227,7 @@ static void eth_nxp_enet_qos_rx(struct k_work *work) LOG_DBG("Recycling RX buf"); /* Fresh meat */ - rx_data->reserved_bufs[i] = new_buf; + data->rx.reserved_bufs[i] = new_buf; desc->read.buf1_addr = (uint32_t)new_buf->data; desc->read.control |= rx_desc_refresh_flags; From a846b81d5834c7d5980c39ec88aeeba173a84247 Mon Sep 17 00:00:00 2001 From: Kyle Dunn Date: Wed, 15 Nov 2023 13:35:26 -0700 Subject: [PATCH 1804/2402] drivers: sensor: lis2dux12: Add lis2dux12 driver Adds support for the STMicroelectronics LIS2DUX12 3-axis accelerometer. Signed-off-by: Kyle Dunn --- drivers/sensor/CMakeLists.txt | 1 + drivers/sensor/Kconfig | 1 + drivers/sensor/lis2dux12/CMakeLists.txt | 8 + drivers/sensor/lis2dux12/Kconfig | 30 ++ drivers/sensor/lis2dux12/lis2dux12.c | 417 ++++++++++++++++++ drivers/sensor/lis2dux12/lis2dux12.h | 86 ++++ drivers/sensor/lis2dux12/lis2dux12_trigger.c | 199 +++++++++ dts/bindings/sensor/st,lis2dux12-common.yaml | 95 ++++ dts/bindings/sensor/st,lis2dux12-i2c.yaml | 8 + dts/bindings/sensor/st,lis2dux12-spi.yaml | 9 + include/zephyr/dt-bindings/sensor/lis2dux12.h | 38 ++ modules/hal_st/Kconfig | 3 + tests/drivers/build_all/sensor/app.overlay | 3 +- tests/drivers/build_all/sensor/i2c.dtsi | 11 + .../build_all/sensor/sensors_die_temp.conf | 1 + .../sensor/sensors_trigger_global.conf | 1 + .../sensor/sensors_trigger_none.conf | 1 + .../build_all/sensor/sensors_trigger_own.conf | 1 + tests/drivers/build_all/sensor/spi.dtsi | 9 + 19 files changed, 921 insertions(+), 1 deletion(-) create mode 100644 drivers/sensor/lis2dux12/CMakeLists.txt create mode 100644 drivers/sensor/lis2dux12/Kconfig create mode 100644 drivers/sensor/lis2dux12/lis2dux12.c create mode 100644 drivers/sensor/lis2dux12/lis2dux12.h create mode 100644 drivers/sensor/lis2dux12/lis2dux12_trigger.c create mode 100644 dts/bindings/sensor/st,lis2dux12-common.yaml create mode 100644 dts/bindings/sensor/st,lis2dux12-i2c.yaml create mode 100644 dts/bindings/sensor/st,lis2dux12-spi.yaml create mode 100644 include/zephyr/dt-bindings/sensor/lis2dux12.h diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index bc7baade23b..7f04c3ce8cf 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -78,6 +78,7 @@ add_subdirectory_ifdef(CONFIG_LIS2DH lis2dh) add_subdirectory_ifdef(CONFIG_LIS2DE12 lis2de12) add_subdirectory_ifdef(CONFIG_LIS2DS12 lis2ds12) add_subdirectory_ifdef(CONFIG_LIS2DU12 lis2du12) +add_subdirectory_ifdef(CONFIG_LIS2DUX12 lis2dux12) add_subdirectory_ifdef(CONFIG_LIS2DW12 lis2dw12) add_subdirectory_ifdef(CONFIG_LIS2MDL lis2mdl) add_subdirectory_ifdef(CONFIG_LIS3MDL lis3mdl) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index e9d1264abf8..708cc6fed24 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -158,6 +158,7 @@ source "drivers/sensor/lis2dh/Kconfig" source "drivers/sensor/lis2de12/Kconfig" source "drivers/sensor/lis2ds12/Kconfig" source "drivers/sensor/lis2du12/Kconfig" +source "drivers/sensor/lis2dux12/Kconfig" source "drivers/sensor/lis2dw12/Kconfig" source "drivers/sensor/lis2mdl/Kconfig" source "drivers/sensor/lis3mdl/Kconfig" diff --git a/drivers/sensor/lis2dux12/CMakeLists.txt b/drivers/sensor/lis2dux12/CMakeLists.txt new file mode 100644 index 00000000000..87f0e6b8928 --- /dev/null +++ b/drivers/sensor/lis2dux12/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(lis2dux12.c) +zephyr_library_sources_ifdef(CONFIG_LIS2DUX12_TRIGGER lis2dux12_trigger.c) + +zephyr_library_include_directories(../stmemsc) diff --git a/drivers/sensor/lis2dux12/Kconfig b/drivers/sensor/lis2dux12/Kconfig new file mode 100644 index 00000000000..d27344484a7 --- /dev/null +++ b/drivers/sensor/lis2dux12/Kconfig @@ -0,0 +1,30 @@ +# ST Microelectronics LIS2DUX12 3-axis accelerometer driver + +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +menuconfig LIS2DUX12 + bool "LIS2DUX12 I2C/SPI accelerometer sensor driver" + default y + depends on DT_HAS_ST_LIS2DUX12_ENABLED + depends on ZEPHYR_HAL_ST_MODULE + select I2C if $(dt_compat_on_bus,$(DT_COMPAT_ST_LIS2DUX12),i2c) + select SPI if $(dt_compat_on_bus,$(DT_COMPAT_ST_LIS2DUX12),spi) + select HAS_STMEMSC + select USE_STDC_LIS2DUX12 + help + Enable driver for LIS2DUX12 accelerometer sensor driver + +if LIS2DUX12 + +module = LIS2DUX12 +thread_priority = 10 +thread_stack_size = 1024 +source "drivers/sensor/Kconfig.trigger_template" + +config LIS2DUX12_ENABLE_TEMP + bool "Temperature" + help + Enable/disable temperature + +endif # LIS2DUX12 diff --git a/drivers/sensor/lis2dux12/lis2dux12.c b/drivers/sensor/lis2dux12/lis2dux12.c new file mode 100644 index 00000000000..4ef663608f2 --- /dev/null +++ b/drivers/sensor/lis2dux12/lis2dux12.c @@ -0,0 +1,417 @@ +/* ST Microelectronics LIS2DUX12 3-axis accelerometer driver + * + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + * + * Datasheet: + * https://www.st.com/resource/en/datasheet/lis2dux12.pdf + */ + +#define DT_DRV_COMPAT st_lis2dux12 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lis2dux12.h" + +LOG_MODULE_REGISTER(LIS2DUX12, CONFIG_SENSOR_LOG_LEVEL); + +static int lis2dux12_set_odr(const struct device *dev, uint8_t odr) +{ + const struct lis2dux12_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + lis2dux12_md_t mode = {.odr = odr}; + + return lis2dux12_mode_set(ctx, &mode); +} + +static int lis2dux12_set_range(const struct device *dev, uint8_t range) +{ + int err; + struct lis2dux12_data *data = dev->data; + const struct lis2dux12_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + lis2dux12_md_t val = { .odr = cfg->odr, .fs = range }; + + err = lis2dux12_mode_set(ctx, &val); + + if (err) { + return err; + } + + switch (range) { + default: + LOG_ERR("range [%d] not supported.", range); + return -EINVAL; + case LIS2DUX12_DT_FS_2G: + data->gain = lis2dux12_from_fs2g_to_mg(1); + break; + case LIS2DUX12_DT_FS_4G: + data->gain = lis2dux12_from_fs4g_to_mg(1); + break; + case LIS2DUX12_DT_FS_8G: + data->gain = lis2dux12_from_fs8g_to_mg(1); + break; + case LIS2DUX12_DT_FS_16G: + data->gain = lis2dux12_from_fs16g_to_mg(1); + break; + } + + return 0; +} + +#define FOREACH_ODR_ENUM(ODR_VAL) \ + ODR_VAL(LIS2DUX12_DT_ODR_OFF, 0.0f) \ + ODR_VAL(LIS2DUX12_DT_ODR_1Hz_ULP, 1.0f) \ + ODR_VAL(LIS2DUX12_DT_ODR_3Hz_ULP, 3.0f) \ + ODR_VAL(LIS2DUX12_DT_ODR_25Hz_ULP, 25.0f) \ + ODR_VAL(LIS2DUX12_DT_ODR_6Hz, 6.0f) \ + ODR_VAL(LIS2DUX12_DT_ODR_12Hz5, 12.50f) \ + ODR_VAL(LIS2DUX12_DT_ODR_25Hz, 25.0f) \ + ODR_VAL(LIS2DUX12_DT_ODR_50Hz, 50.0f) \ + ODR_VAL(LIS2DUX12_DT_ODR_100Hz, 100.0f) \ + ODR_VAL(LIS2DUX12_DT_ODR_200Hz, 200.0f) \ + ODR_VAL(LIS2DUX12_DT_ODR_400Hz, 400.0f) \ + ODR_VAL(LIS2DUX12_DT_ODR_800Hz, 800.0f) + +#define GENERATE_VAL(ENUM, VAL) VAL, + +static const float lis2dux12_odr_map[LIS2DUX12_DT_ODR_END] = {FOREACH_ODR_ENUM(GENERATE_VAL)}; + +static int lis2dux12_freq_to_odr_val(const struct device *dev, uint16_t freq) +{ + const struct lis2dux12_config *cfg = dev->config; + + /* constrain loop to prevent erroneous power mode/odr combinations */ + size_t i = (cfg->pm != LIS2DUX12_OPER_MODE_LOW_POWER) ? LIS2DUX12_DT_ODR_6Hz + : LIS2DUX12_DT_ODR_1Hz_ULP; + size_t len = (cfg->pm != LIS2DUX12_OPER_MODE_LOW_POWER) ? LIS2DUX12_DT_ODR_END + : LIS2DUX12_DT_ODR_6Hz; + + while (i < len) { + if (freq <= lis2dux12_odr_map[i]) { + return i; + } + ++i; + } + + return -EINVAL; +} + +static int lis2dux12_accel_config(const struct device *dev, enum sensor_channel chan, + enum sensor_attribute attr, const struct sensor_value *val) +{ + int odr_val; + + switch (attr) { + case SENSOR_ATTR_FULL_SCALE: + return lis2dux12_set_range(dev, sensor_ms2_to_g(val)); + case SENSOR_ATTR_SAMPLING_FREQUENCY: + odr_val = lis2dux12_freq_to_odr_val(dev, val->val1); + if (odr_val < 0) { + LOG_ERR("%d Hz not supported or wrong operating mode.", val->val1); + return odr_val; + } + + LOG_DBG("%s: set odr to %d Hz", dev->name, val->val1); + + return lis2dux12_set_odr(dev, odr_val); + default: + LOG_ERR("Accel attribute not supported."); + return -ENOTSUP; + } + + return 0; +} + +static int lis2dux12_attr_set(const struct device *dev, enum sensor_channel chan, + enum sensor_attribute attr, const struct sensor_value *val) +{ + switch (chan) { + case SENSOR_CHAN_ACCEL_XYZ: + return lis2dux12_accel_config(dev, chan, attr, val); + default: + LOG_ERR("attr_set() not supported on this channel."); + return -ENOTSUP; + } + + return 0; +} + +static int lis2dux12_sample_fetch_accel(const struct device *dev) +{ + struct lis2dux12_data *data = dev->data; + const struct lis2dux12_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + + /* fetch raw data sample */ + lis2dux12_md_t mode = {.fs = cfg->range}; + lis2dux12_xl_data_t xzy_data = {0}; + + if (lis2dux12_xl_data_get(ctx, &mode, &xzy_data) < 0) { + LOG_ERR("Failed to fetch raw data sample"); + return -EIO; + } + + data->sample_x = sys_le16_to_cpu(xzy_data.raw[0]); + data->sample_y = sys_le16_to_cpu(xzy_data.raw[1]); + data->sample_z = sys_le16_to_cpu(xzy_data.raw[2]); + + return 0; +} + +#ifdef CONFIG_LIS2DUX12_ENABLE_TEMP +static int lis2dux12_sample_fetch_temp(const struct device *dev) +{ + struct lis2dux12_data *data = dev->data; + const struct lis2dux12_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + + /* fetch raw data sample */ + lis2dux12_md_t mode; + lis2dux12_outt_data_t temp_data = {0}; + + if (lis2dux12_outt_data_get(ctx, &mode, &temp_data) < 0) { + LOG_ERR("Failed to fetch raw temperature data sample"); + return -EIO; + } + + data->sample_temp = sys_le16_to_cpu(temp_data.heat.raw); + + return 0; +} +#endif + +static int lis2dux12_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + switch (chan) { + case SENSOR_CHAN_ACCEL_XYZ: + lis2dux12_sample_fetch_accel(dev); + break; +#if defined(CONFIG_LIS2DUX12_ENABLE_TEMP) + case SENSOR_CHAN_DIE_TEMP: + lis2dux12_sample_fetch_temp(dev); + break; +#endif + case SENSOR_CHAN_ALL: + lis2dux12_sample_fetch_accel(dev); +#if defined(CONFIG_LIS2DUX12_ENABLE_TEMP) + lis2dux12_sample_fetch_temp(dev); +#endif + break; + default: + return -ENOTSUP; + } + + return 0; +} + +static inline void lis2dux12_convert(struct sensor_value *val, int raw_val, float gain) +{ + int64_t dval; + + /* Gain is in mg/LSB */ + /* Convert to m/s^2 */ + dval = ((int64_t)raw_val * gain * SENSOR_G) / 1000; + val->val1 = dval / 1000000LL; + val->val2 = dval % 1000000LL; +} + +static inline int lis2dux12_get_channel(enum sensor_channel chan, struct sensor_value *val, + struct lis2dux12_data *data, float gain) +{ + switch (chan) { + case SENSOR_CHAN_ACCEL_X: + lis2dux12_convert(val, data->sample_x, gain); + break; + case SENSOR_CHAN_ACCEL_Y: + lis2dux12_convert(val, data->sample_y, gain); + break; + case SENSOR_CHAN_ACCEL_Z: + lis2dux12_convert(val, data->sample_z, gain); + break; + case SENSOR_CHAN_ACCEL_XYZ: + lis2dux12_convert(val, data->sample_x, gain); + lis2dux12_convert(val + 1, data->sample_y, gain); + lis2dux12_convert(val + 2, data->sample_z, gain); + break; +#if defined(CONFIG_LIS2DUX12_ENABLE_TEMP) + case SENSOR_CHAN_DIE_TEMP: + sensor_value_from_double(val, data->sample_temp); + break; +#endif + default: + return -ENOTSUP; + } + + return 0; +} + +static int lis2dux12_channel_get(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + struct lis2dux12_data *data = dev->data; + + return lis2dux12_get_channel(chan, val, data, data->gain); +} + +static const struct sensor_driver_api lis2dux12_driver_api = { + .attr_set = lis2dux12_attr_set, +#if defined(CONFIG_LIS2DUX12_TRIGGER) + .trigger_set = lis2dux12_trigger_set, +#endif + .sample_fetch = lis2dux12_sample_fetch, + .channel_get = lis2dux12_channel_get, +}; + +static int lis2dux12_init(const struct device *dev) +{ + const struct lis2dux12_config *const cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + uint8_t chip_id; + int ret; + + lis2dux12_exit_deep_power_down(ctx); + k_busy_wait(25000); + + /* check chip ID */ + ret = lis2dux12_device_id_get(ctx, &chip_id); + if (ret < 0) { + LOG_ERR("%s: Not able to read dev id", dev->name); + return ret; + } + + if (chip_id != LIS2DUX12_ID) { + LOG_ERR("%s: Invalid chip ID 0x%02x", dev->name, chip_id); + return -EINVAL; + } + + /* reset device */ + ret = lis2dux12_init_set(ctx, LIS2DUX12_RESET); + if (ret < 0) { + return ret; + } + + k_busy_wait(100); + + LOG_INF("%s: chip id 0x%x", dev->name, chip_id); + + /* Set bdu and if_inc recommended for driver usage */ + lis2dux12_init_set(ctx, LIS2DUX12_SENSOR_ONLY_ON); + + lis2dux12_timestamp_set(ctx, PROPERTY_ENABLE); + +#ifdef CONFIG_LIS2DUX12_TRIGGER + if (cfg->trig_enabled) { + ret = lis2dux12_trigger_init(dev); + if (ret < 0) { + LOG_ERR("%s: Failed to initialize triggers", dev->name); + return ret; + } + } +#endif + + /* set sensor default pm and odr */ + LOG_DBG("%s: pm: %d, odr: %d", dev->name, cfg->pm, cfg->odr); + lis2dux12_md_t mode = { + .odr = cfg->odr, + .fs = cfg->range, + }; + ret = lis2dux12_mode_set(ctx, &mode); + if (ret < 0) { + LOG_ERR("%s: odr init error (12.5 Hz)", dev->name); + return ret; + } + + /* set sensor default scale (used to convert sample values) */ + LOG_DBG("%s: range is %d", dev->name, cfg->range); + ret = lis2dux12_set_range(dev, cfg->range); + if (ret < 0) { + LOG_ERR("%s: range init error %d", dev->name, cfg->range); + return ret; + } + + return 0; +} + +/* + * Device creation macro, shared by LIS2DUX12_DEFINE_SPI() and + * LIS2DUX12_DEFINE_I2C(). + */ + +#define LIS2DUX12_DEVICE_INIT(inst) \ + SENSOR_DEVICE_DT_INST_DEFINE(inst, lis2dux12_init, NULL, &lis2dux12_data_##inst, \ + &lis2dux12_config_##inst, POST_KERNEL, \ + CONFIG_SENSOR_INIT_PRIORITY, &lis2dux12_driver_api); + +/* + * Instantiation macros used when a device is on a SPI bus. + */ + +#ifdef CONFIG_LIS2DUX12_TRIGGER +#define LIS2DUX12_CFG_IRQ(inst) \ + .trig_enabled = true, \ + .int1_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, int1_gpios, {0}), \ + .int2_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, int2_gpios, {0}), \ + .drdy_pin = DT_INST_PROP(inst, drdy_pin), +#else +#define LIS2DUX12_CFG_IRQ(inst) +#endif /* CONFIG_LIS2DUX12_TRIGGER */ + +#define LIS2DUX12_SPI_OPERATION \ + (SPI_WORD_SET(8) | SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA) + +#define LIS2DUX12_CONFIG_SPI(inst) \ + { \ + STMEMSC_CTX_SPI(&lis2dux12_config_##inst.stmemsc_cfg), \ + .stmemsc_cfg = { \ + .spi = SPI_DT_SPEC_INST_GET(inst, LIS2DUX12_SPI_OPERATION, 0), \ + }, \ + .range = DT_INST_PROP(inst, range), \ + .pm = DT_INST_PROP(inst, power_mode), \ + .odr = DT_INST_PROP(inst, odr), \ + IF_ENABLED(UTIL_OR(DT_INST_NODE_HAS_PROP(inst, int1_gpios), \ + DT_INST_NODE_HAS_PROP(inst, int2_gpios)), \ + (LIS2DUX12_CFG_IRQ(inst))) \ + } + +/* + * Instantiation macros used when a device is on an I2C bus. + */ + +#define LIS2DUX12_CONFIG_I2C(inst) \ + { \ + STMEMSC_CTX_I2C(&lis2dux12_config_##inst.stmemsc_cfg), \ + .stmemsc_cfg = { \ + .i2c = I2C_DT_SPEC_INST_GET(inst), \ + }, \ + .range = DT_INST_PROP(inst, range), \ + .pm = DT_INST_PROP(inst, power_mode), \ + .odr = DT_INST_PROP(inst, odr), \ + IF_ENABLED(UTIL_OR(DT_INST_NODE_HAS_PROP(inst, int1_gpios), \ + DT_INST_NODE_HAS_PROP(inst, int2_gpios)), \ + (LIS2DUX12_CFG_IRQ(inst))) \ + } + +/* + * Main instantiation macro. Use of COND_CODE_1() selects the right + * bus-specific macro at preprocessor time. + */ + +#define LIS2DUX12_DEFINE(inst) \ + static struct lis2dux12_data lis2dux12_data_##inst; \ + static const struct lis2dux12_config lis2dux12_config_##inst = \ + COND_CODE_1(DT_INST_ON_BUS(inst, spi), (LIS2DUX12_CONFIG_SPI(inst)), \ + (LIS2DUX12_CONFIG_I2C(inst))); \ + LIS2DUX12_DEVICE_INIT(inst) + +DT_INST_FOREACH_STATUS_OKAY(LIS2DUX12_DEFINE) diff --git a/drivers/sensor/lis2dux12/lis2dux12.h b/drivers/sensor/lis2dux12/lis2dux12.h new file mode 100644 index 00000000000..82a2a693a43 --- /dev/null +++ b/drivers/sensor/lis2dux12/lis2dux12.h @@ -0,0 +1,86 @@ +/* ST Microelectronics LIS2DUX12 3-axis accelerometer driver + * + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + * + * Datasheet: + * https://www.st.com/resource/en/datasheet/lis2dux12.pdf + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_LIS2DUX12_LIS2DUX12_H_ +#define ZEPHYR_DRIVERS_SENSOR_LIS2DUX12_LIS2DUX12_H_ + +#include +#include +#include +#include +#include "lis2dux12_reg.h" + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ + +struct lis2dux12_config { + stmdev_ctx_t ctx; + union { +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) + const struct i2c_dt_spec i2c; +#endif +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) + const struct spi_dt_spec spi; +#endif + } stmemsc_cfg; + uint8_t range; + uint8_t pm; + uint8_t odr; +#ifdef CONFIG_LIS2DUX12_TRIGGER + const struct gpio_dt_spec int1_gpio; + const struct gpio_dt_spec int2_gpio; + uint8_t drdy_pin; + bool trig_enabled; +#endif +}; + +struct lis2dux12_data { + int sample_x; + int sample_y; + int sample_z; + float gain; + +#ifdef CONFIG_LIS2DUX12_ENABLE_TEMP + int sample_temp; +#endif + +#ifdef CONFIG_LIS2DUX12_TRIGGER + struct gpio_dt_spec *drdy_gpio; + struct gpio_callback gpio_cb; + + const struct sensor_trigger *data_ready_trigger; + sensor_trigger_handler_t data_ready_handler; + const struct device *dev; + +#if defined(CONFIG_LIS2DUX12_TRIGGER_OWN_THREAD) + K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_LIS2DUX12_THREAD_STACK_SIZE); + struct k_thread thread; + struct k_sem trig_sem; +#elif defined(CONFIG_LIS2DUX12_TRIGGER_GLOBAL_THREAD) + struct k_work work; +#endif + +#endif /* CONFIG_LIS2DUX12_TRIGGER */ +}; + +#ifdef CONFIG_LIS2DUX12_TRIGGER +int lis2dux12_trigger_set(const struct device *dev, + const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); + +int lis2dux12_trigger_init(const struct device *dev); +#endif + +#endif /* ZEPHYR_DRIVERS_SENSOR_LIS2DUX12_LIS2DUX12_H_ */ diff --git a/drivers/sensor/lis2dux12/lis2dux12_trigger.c b/drivers/sensor/lis2dux12/lis2dux12_trigger.c new file mode 100644 index 00000000000..f7fe2c0bc63 --- /dev/null +++ b/drivers/sensor/lis2dux12/lis2dux12_trigger.c @@ -0,0 +1,199 @@ +/* ST Microelectronics LIS2DUX12 3-axis accelerometer driver + * + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + * + * Datasheet: + * https://www.st.com/resource/en/datasheet/lis2dux12.pdf + */ + +#define DT_DRV_COMPAT st_lis2dux12 + +#include +#include "lis2dux12.h" + +LOG_MODULE_DECLARE(LIS2DUX12, CONFIG_SENSOR_LOG_LEVEL); + +static void lis2dux12_gpio_callback(const struct device *dev, struct gpio_callback *cb, + uint32_t pins) +{ + struct lis2dux12_data *data = CONTAINER_OF(cb, struct lis2dux12_data, gpio_cb); + int ret; + + ARG_UNUSED(pins); + + ret = gpio_pin_interrupt_configure_dt(data->drdy_gpio, GPIO_INT_DISABLE); + if (ret < 0) { + LOG_ERR("%s: Not able to configure pin_int", dev->name); + } + +#if defined(CONFIG_LIS2DUX12_TRIGGER_OWN_THREAD) + k_sem_give(&data->trig_sem); +#elif defined(CONFIG_LIS2DUX12_TRIGGER_GLOBAL_THREAD) + k_work_submit(&data->work); +#endif +} + +static void lis2dux12_handle_drdy_int(const struct device *dev) +{ + struct lis2dux12_data *data = dev->data; + + if (data->data_ready_handler != NULL) { + data->data_ready_handler(dev, data->data_ready_trigger); + } +} + +static void lis2dux12_handle_int(const struct device *dev) +{ + struct lis2dux12_data *lis2dux12 = dev->data; + const struct lis2dux12_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + lis2dux12_all_sources_t sources; + int ret; + + lis2dux12_all_sources_get(ctx, &sources); + + if (sources.drdy) { + lis2dux12_handle_drdy_int(dev); + } + + ret = gpio_pin_interrupt_configure_dt(lis2dux12->drdy_gpio, GPIO_INT_EDGE_TO_ACTIVE); + if (ret < 0) { + LOG_ERR("%s: Not able to configure pin_int", dev->name); + } +} + +#ifdef CONFIG_LIS2DUX12_TRIGGER_OWN_THREAD +static void lis2dux12_thread(struct lis2dux12_data *data) +{ + while (1) { + k_sem_take(&data->trig_sem, K_FOREVER); + lis2dux12_handle_int(data->dev); + } +} +#endif + +#ifdef CONFIG_LIS2DUX12_TRIGGER_GLOBAL_THREAD +static void lis2dux12_work_cb(struct k_work *work) +{ + struct lis2dux12_data *data = CONTAINER_OF(work, struct lis2dux12_data, work); + + lis2dux12_handle_int(data->dev); +} +#endif + +static int lis2dux12_init_interrupt(const struct device *dev) +{ + const struct lis2dux12_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + lis2dux12_pin_int_route_t route; + int err; + + /* Enable pulsed mode */ + err = lis2dux12_data_ready_mode_set(ctx, LIS2DUX12_DRDY_PULSED); + if (err < 0) { + return err; + } + + /* route data-ready interrupt on int1 */ + err = lis2dux12_pin_int1_route_get(ctx, &route); + if (err < 0) { + return err; + } + + route.drdy = 1; + + err = lis2dux12_pin_int1_route_set(ctx, &route); + if (err < 0) { + return err; + } + + return 0; +} + +int lis2dux12_trigger_init(const struct device *dev) +{ + struct lis2dux12_data *data = dev->data; + const struct lis2dux12_config *cfg = dev->config; + int ret; + + data->drdy_gpio = (cfg->drdy_pin == 1) ? (struct gpio_dt_spec *)&cfg->int1_gpio + : (struct gpio_dt_spec *)&cfg->int2_gpio; + + /* setup data ready gpio interrupt (INT1 or INT2) */ + if (!gpio_is_ready_dt(data->drdy_gpio)) { + LOG_ERR("Cannot get pointer to drdy_gpio device"); + return -ENODEV; + } + + data->dev = dev; + + ret = gpio_pin_configure_dt(data->drdy_gpio, GPIO_INPUT); + if (ret < 0) { + LOG_ERR("Could not configure gpio"); + return ret; + } + + gpio_init_callback(&data->gpio_cb, lis2dux12_gpio_callback, BIT(data->drdy_gpio->pin)); + + ret = gpio_add_callback(data->drdy_gpio->port, &data->gpio_cb); + if (ret < 0) { + LOG_ERR("Could not set gpio callback"); + return ret; + } + +#if defined(CONFIG_LIS2DUX12_TRIGGER_OWN_THREAD) + k_sem_init(&data->trig_sem, 0, K_SEM_MAX_LIMIT); + + k_thread_create(&data->thread, data->thread_stack, CONFIG_LIS2DUX12_THREAD_STACK_SIZE, + (k_thread_entry_t)lis2dux12_thread, data, NULL, NULL, + K_PRIO_COOP(CONFIG_LIS2DUX12_THREAD_PRIORITY), 0, K_NO_WAIT); + k_thread_name_set(&data->thread, dev->name); +#elif defined(CONFIG_LIS2DUX12_TRIGGER_GLOBAL_THREAD) + data->work.handler = lis2dux12_work_cb; +#endif + + return gpio_pin_interrupt_configure_dt(data->drdy_gpio, GPIO_INT_EDGE_TO_ACTIVE); +} + +int lis2dux12_trigger_set(const struct device *dev, const struct sensor_trigger *trig, + sensor_trigger_handler_t handler) +{ + struct lis2dux12_data *data = dev->data; + const struct lis2dux12_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + lis2dux12_xl_data_t xldata; + lis2dux12_md_t mode; + int ret; + + if (!cfg->trig_enabled) { + LOG_ERR("trigger_set op not supported"); + return -ENOTSUP; + } + + if (data->drdy_gpio->port == NULL) { + LOG_ERR("trigger_set is not supported"); + return -ENOTSUP; + } + + ret = gpio_pin_interrupt_configure_dt(data->drdy_gpio, GPIO_INT_DISABLE); + if (ret < 0) { + LOG_ERR("%s: Not able to configure pin_int", dev->name); + return ret; + } + + data->data_ready_handler = handler; + if (handler == NULL) { + LOG_WRN("lis2dux12: no handler"); + return 0; + } + + /* re-trigger lost interrupt */ + lis2dux12_xl_data_get(ctx, &mode, &xldata); + + data->data_ready_trigger = trig; + + lis2dux12_init_interrupt(dev); + return gpio_pin_interrupt_configure_dt(data->drdy_gpio, GPIO_INT_EDGE_TO_ACTIVE); +} diff --git a/dts/bindings/sensor/st,lis2dux12-common.yaml b/dts/bindings/sensor/st,lis2dux12-common.yaml new file mode 100644 index 00000000000..e9885dd37ae --- /dev/null +++ b/dts/bindings/sensor/st,lis2dux12-common.yaml @@ -0,0 +1,95 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +description: | + When setting the odr, power-mode, and range properties in a .dts or .dtsi file you may include + st_lis2dux12.h and use the macros defined there. + Example: + #include + lis2dux12: lis2dux12@0 { + ... + power-mode = ; + odr = ; + range = ; + }; + +include: sensor-device.yaml + +properties: + int1-gpios: + type: phandle-array + description: | + INT1 pin + + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. + int2-gpios: + type: phandle-array + description: | + INT2 pin + + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. + + drdy-pin: + type: int + default: 1 + enum: + - 1 # drdy is generated from INT1 + - 2 # drdy is generated from INT2 + description: | + Select DRDY pin number (1 or 2). + This number represents which of the two interrupt pins + (INT1 or INT2) the drdy line is attached to. This property is not + mandatory and if not present it defaults to 1 which is the + configuration at power-up. + + + range: + type: int + default: 0 + description: | + Range in g. Default is power-up configuration. + + - 3 # LIS2DUX12_DT_FS_16G + - 2 # LIS2DUX12_DT_FS_8G + - 1 # LIS2DUX12_DT_FS_4G + - 0 # LIS2DUX12_DT_FS_2G + + enum: [0, 1, 2, 3] + + power-mode: + type: int + default: 0 + description: | + Specify the sensor power mode. Default is power-down mode + + - 0 # LIS2DUX12_OPER_MODE_POWER_DOWN + - 1 # LIS2DUX12_OPER_MODE_LOW_POWER + - 2 # LIS2DUX12_OPER_MODE_HIGH_RESOLUTION + - 3 # LIS2DUX12_OPER_MODE_HIGH_FREQUENCY + + enum: [0, 1, 2, 3] + + odr: + type: int + default: 0 + description: | + Specify the default output data rate expressed in samples per second (Hz). + Default is power-down mode + - 0 # LIS2DUX12_DT_ODR_OFF + - 1 # LIS2DUX12_DT_ODR_1Hz_ULP + - 2 # LIS2DUX12_DT_ODR_3Hz_ULP + - 3 # LIS2DUX12_DT_ODR_25Hz_ULP + - 4 # LIS2DUX12_DT_ODR_6Hz + - 5 # LIS2DUX12_DT_ODR_12Hz5 + - 6 # LIS2DUX12_DT_ODR_25Hz + - 7 # LIS2DUX12_DT_ODR_50Hz + - 8 # LIS2DUX12_DT_ODR_100Hz + - 9 # LIS2DUX12_DT_ODR_200Hz + - 10 # LIS2DUX12_DT_ODR_400Hz + - 11 # LIS2DUX12_DT_ODR_800Hz + + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11] diff --git a/dts/bindings/sensor/st,lis2dux12-i2c.yaml b/dts/bindings/sensor/st,lis2dux12-i2c.yaml new file mode 100644 index 00000000000..8f6535c804d --- /dev/null +++ b/dts/bindings/sensor/st,lis2dux12-i2c.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +description: STMicroelectronics LIS2DUX12 3-axis accelerometer + +compatible: "st,lis2dux12" + +include: ["i2c-device.yaml", "st,lis2dux12-common.yaml"] diff --git a/dts/bindings/sensor/st,lis2dux12-spi.yaml b/dts/bindings/sensor/st,lis2dux12-spi.yaml new file mode 100644 index 00000000000..191a59cfb89 --- /dev/null +++ b/dts/bindings/sensor/st,lis2dux12-spi.yaml @@ -0,0 +1,9 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +description: | + STMicroelectronics LIS2DUX12 3-axis accelerometer accessed through SPI bus + +compatible: "st,lis2dux12" + +include: ["spi-device.yaml", "st,lis2dux12-common.yaml"] diff --git a/include/zephyr/dt-bindings/sensor/lis2dux12.h b/include/zephyr/dt-bindings/sensor/lis2dux12.h new file mode 100644 index 00000000000..48e8dfbdd4a --- /dev/null +++ b/include/zephyr/dt-bindings/sensor/lis2dux12.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2023 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LIS2DUX12_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_LIS2DUX12_H_ + +#include + +/* Operating Mode */ +#define LIS2DUX12_OPER_MODE_POWER_DOWN 0 +#define LIS2DUX12_OPER_MODE_LOW_POWER 1 +#define LIS2DUX12_OPER_MODE_HIGH_RESOLUTION 2 +#define LIS2DUX12_OPER_MODE_HIGH_FREQUENCY 3 + +/* Data rate */ +#define LIS2DUX12_DT_ODR_OFF 0 +#define LIS2DUX12_DT_ODR_1Hz_ULP 1 /* available in ultra-low power mode */ +#define LIS2DUX12_DT_ODR_3Hz_ULP 2 /* available in ultra-low power mode */ +#define LIS2DUX12_DT_ODR_25Hz_ULP 3 /* available in ultra-low power mode */ +#define LIS2DUX12_DT_ODR_6Hz 4 /* available in LP and HP mode */ +#define LIS2DUX12_DT_ODR_12Hz5 5 /* available in LP and HP mode */ +#define LIS2DUX12_DT_ODR_25Hz 6 /* available in LP and HP mode */ +#define LIS2DUX12_DT_ODR_50Hz 7 /* available in LP and HP mode */ +#define LIS2DUX12_DT_ODR_100Hz 8 /* available in LP and HP mode */ +#define LIS2DUX12_DT_ODR_200Hz 9 /* available in LP and HP mode */ +#define LIS2DUX12_DT_ODR_400Hz 10 /* available in LP and HP mode */ +#define LIS2DUX12_DT_ODR_800Hz 11 /* available in LP and HP mode */ +#define LIS2DUX12_DT_ODR_END 12 + +/* Accelerometer Full-scale */ +#define LIS2DUX12_DT_FS_2G 0 /* 2g (0.061 mg/LSB) */ +#define LIS2DUX12_DT_FS_4G 1 /* 4g (0.122 mg/LSB) */ +#define LIS2DUX12_DT_FS_8G 2 /* 8g (0.244 mg/LSB) */ +#define LIS2DUX12_DT_FS_16G 3 /* 16g (0.488 mg/LSB) */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_LIS2DUX12_H_ */ diff --git a/modules/hal_st/Kconfig b/modules/hal_st/Kconfig index 020dbdc5d35..579f7f7d3f8 100644 --- a/modules/hal_st/Kconfig +++ b/modules/hal_st/Kconfig @@ -93,6 +93,9 @@ config USE_STDC_LIS2DTW12 config USE_STDC_LIS2DU12 bool +config USE_STDC_LIS2DUX12 + bool + config USE_STDC_LIS2DW12 bool diff --git a/tests/drivers/build_all/sensor/app.overlay b/tests/drivers/build_all/sensor/app.overlay index c9582338fba..161949bdd7b 100644 --- a/tests/drivers/build_all/sensor/app.overlay +++ b/tests/drivers/build_all/sensor/app.overlay @@ -127,7 +127,8 @@ <&test_gpio 0 0>, <&test_gpio 0 0>, <&test_gpio 0 0>, - <&test_gpio 0 0>; /* 0x2C */ + <&test_gpio 0 0>, + <&test_gpio 0 0>; #include "spi.dtsi" }; diff --git a/tests/drivers/build_all/sensor/i2c.dtsi b/tests/drivers/build_all/sensor/i2c.dtsi index e25e649df78..57ca61a0077 100644 --- a/tests/drivers/build_all/sensor/i2c.dtsi +++ b/tests/drivers/build_all/sensor/i2c.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -1009,6 +1010,16 @@ test_i2c_aht20: aht20@88 { test_i2c_am2301b: am2301b@89 { compatible = "aosong,am2301b"; reg = <0x89>; +}; + +test_i2c_lis2dux12: lis2dux12@8a { + compatible = "st,lis2dux12"; + reg = <0x8a>; + int1-gpios = <&test_gpio 0 0>; + int2-gpios = <&test_gpio 0 0>; + range = ; + odr = ; + power-mode = ; status = "okay"; }; diff --git a/tests/drivers/build_all/sensor/sensors_die_temp.conf b/tests/drivers/build_all/sensor/sensors_die_temp.conf index f66af170c55..e2e79399043 100644 --- a/tests/drivers/build_all/sensor/sensors_die_temp.conf +++ b/tests/drivers/build_all/sensor/sensors_die_temp.conf @@ -5,5 +5,6 @@ CONFIG_LSM6DSV16X_ENABLE_TEMP=y CONFIG_LSM6DSO_ENABLE_TEMP=y CONFIG_LIS2DE12_ENABLE_TEMP=y CONFIG_LIS2DS12_ENABLE_TEMP=y +CONFIG_LIS2DUX12_ENABLE_TEMP=y CONFIG_LSM6DSO16IS_ENABLE_TEMP=y CONFIG_LSM6DSL_ENABLE_TEMP=y diff --git a/tests/drivers/build_all/sensor/sensors_trigger_global.conf b/tests/drivers/build_all/sensor/sensors_trigger_global.conf index d6cdef2021c..0f9369de321 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_global.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_global.conf @@ -36,6 +36,7 @@ CONFIG_LIS2DH_TRIGGER_GLOBAL_THREAD=y CONFIG_LIS2DE12_TRIGGER_GLOBAL_THREAD=y CONFIG_LIS2DS12_TRIGGER_GLOBAL_THREAD=y CONFIG_LIS2DU12_TRIGGER_GLOBAL_THREAD=y +CONFIG_LIS2DUX12_TRIGGER_GLOBAL_THREAD=y CONFIG_LIS2DW12_TRIGGER_GLOBAL_THREAD=y CONFIG_LIS2MDL_TRIGGER_GLOBAL_THREAD=y CONFIG_LIS3MDL_TRIGGER_GLOBAL_THREAD=y diff --git a/tests/drivers/build_all/sensor/sensors_trigger_none.conf b/tests/drivers/build_all/sensor/sensors_trigger_none.conf index 375e7d8ebe3..3782a0923a3 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_none.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_none.conf @@ -36,6 +36,7 @@ CONFIG_LIS2DH_TRIGGER_NONE=y CONFIG_LIS2DE12_TRIGGER_NONE=y CONFIG_LIS2DS12_TRIGGER_NONE=y CONFIG_LIS2DU12_TRIGGER_NONE=y +CONFIG_LIS2DUX12_TRIGGER_NONE=y CONFIG_LIS2DW12_TRIGGER_NONE=y CONFIG_LIS2MDL_TRIGGER_NONE=y CONFIG_LIS3MDL_TRIGGER_NONE=y diff --git a/tests/drivers/build_all/sensor/sensors_trigger_own.conf b/tests/drivers/build_all/sensor/sensors_trigger_own.conf index 76691a6994a..878a4ba34ab 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_own.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_own.conf @@ -34,6 +34,7 @@ CONFIG_LIS2DH_TRIGGER_OWN_THREAD=y CONFIG_LIS2DE12_TRIGGER_OWN_THREAD=y CONFIG_LIS2DS12_TRIGGER_OWN_THREAD=y CONFIG_LIS2DU12_TRIGGER_OWN_THREAD=y +CONFIG_LIS2DUX12_TRIGGER_OWN_THREAD=y CONFIG_LIS2DW12_TRIGGER_OWN_THREAD=y CONFIG_LIS2MDL_TRIGGER_OWN_THREAD=y CONFIG_LIS3MDL_TRIGGER_OWN_THREAD=y diff --git a/tests/drivers/build_all/sensor/spi.dtsi b/tests/drivers/build_all/sensor/spi.dtsi index b8fd5e56b0b..d781f170066 100644 --- a/tests/drivers/build_all/sensor/spi.dtsi +++ b/tests/drivers/build_all/sensor/spi.dtsi @@ -361,3 +361,12 @@ test_spi_iis328dq: iis328dq@2c { int1-gpios = <&test_gpio 0 0>; drdy-int-pad = <1>; }; + +test_spi_lis2dux12: lis2dux12@2d { + compatible = "st,lis2dux12"; + reg = <0x2d>; + spi-max-frequency = <0>; + int1-gpios = <&test_gpio 0 0>; + int2-gpios = <&test_gpio 0 0>; + status = "okay"; +}; From 828a0c04a18b9e1feee8a4b47d20d9bd11ace1ca Mon Sep 17 00:00:00 2001 From: Ilia Kharin Date: Sun, 25 Feb 2024 21:13:06 +0100 Subject: [PATCH 1805/2402] drivers: input: pinnacle: add driver for trackpad The initial version of an input driver for Cirque Pinnacle ASIC supports: * Setting sensitivity * Choosing between relative and absolute modes * Relative mode * Primary tap * Swapping X and Y * Absolute mode * Setting number of idle packets * Clipping coordinates outside of active range * Scaling coordinates * Inverting X and Y coordinates Signed-off-by: Ilia Kharin --- drivers/input/CMakeLists.txt | 1 + drivers/input/Kconfig | 1 + drivers/input/Kconfig.pinnacle | 14 + drivers/input/input_pinnacle.c | 909 ++++++++++++++++++ .../input/cirque,pinnacle-common.yaml | 113 +++ dts/bindings/input/cirque,pinnacle-i2c.yaml | 8 + dts/bindings/input/cirque,pinnacle-spi.yaml | 8 + dts/bindings/vendor-prefixes.txt | 1 + tests/drivers/build_all/input/app.overlay | 24 +- 9 files changed, 1078 insertions(+), 1 deletion(-) create mode 100644 drivers/input/Kconfig.pinnacle create mode 100644 drivers/input/input_pinnacle.c create mode 100644 dts/bindings/input/cirque,pinnacle-common.yaml create mode 100644 dts/bindings/input/cirque,pinnacle-i2c.yaml create mode 100644 dts/bindings/input/cirque,pinnacle-spi.yaml diff --git a/drivers/input/CMakeLists.txt b/drivers/input/CMakeLists.txt index 67311587fd5..3a5c901c449 100644 --- a/drivers/input/CMakeLists.txt +++ b/drivers/input/CMakeLists.txt @@ -20,6 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_INPUT_ITE_IT8XXX2_KBD input_ite_it8xxx2_kbd. zephyr_library_sources_ifdef(CONFIG_INPUT_KBD_MATRIX input_kbd_matrix.c) zephyr_library_sources_ifdef(CONFIG_INPUT_NPCX_KBD input_npcx_kbd.c) zephyr_library_sources_ifdef(CONFIG_INPUT_PAT912X input_pat912x.c) +zephyr_library_sources_ifdef(CONFIG_INPUT_PINNACLE input_pinnacle.c) zephyr_library_sources_ifdef(CONFIG_INPUT_PMW3610 input_pmw3610.c) zephyr_library_sources_ifdef(CONFIG_INPUT_STMPE811 input_stmpe811.c) zephyr_library_sources_ifdef(CONFIG_INPUT_XEC_KBD input_xec_kbd.c) diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 4562fda5a33..72c6625849c 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -22,6 +22,7 @@ source "drivers/input/Kconfig.it8xxx2" source "drivers/input/Kconfig.kbd_matrix" source "drivers/input/Kconfig.npcx" source "drivers/input/Kconfig.pat912x" +source "drivers/input/Kconfig.pinnacle" source "drivers/input/Kconfig.pmw3610" source "drivers/input/Kconfig.sdl" source "drivers/input/Kconfig.stmpe811" diff --git a/drivers/input/Kconfig.pinnacle b/drivers/input/Kconfig.pinnacle new file mode 100644 index 00000000000..05b9bbb0ada --- /dev/null +++ b/drivers/input/Kconfig.pinnacle @@ -0,0 +1,14 @@ +# Cirque Pinnacle 1CA027 touch controller based device configuration options +# +# Copyright (c) 2024 Ilia Kharin +# SPDX-License-Identifier: Apache-2.0 + +config INPUT_PINNACLE + bool "Cirque Pinnacle 1CA027 Touch Controller Based Device" + default y + depends on DT_HAS_CIRQUE_PINNACLE_ENABLED + select GPIO + select I2C if $(dt_compat_on_bus,$(DT_COMPAT_CIRQUE_PINNACLE),i2c) + select SPI if $(dt_compat_on_bus,$(DT_COMPAT_CIRQUE_PINNACLE),spi) + help + Enable driver for Cirque Pinnacle 1CA027 tracked input device. diff --git a/drivers/input/input_pinnacle.c b/drivers/input/input_pinnacle.c new file mode 100644 index 00000000000..bcf60be1d78 --- /dev/null +++ b/drivers/input/input_pinnacle.c @@ -0,0 +1,909 @@ +/* + * Copyright (c) 2024 Ilia Kharin + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT cirque_pinnacle + +#include +#include +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#include +#endif +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#include +#endif +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(pinnacle, CONFIG_INPUT_LOG_LEVEL); + +/* + * Register Access Protocol Standard Registers. + * Standard registers have 5-bit addresses, BIT[4:0], that range from + * 0x00 to 0x1F. For reading, a register address has to be combined with + * 0xA0 for reading and 0x80 for writing bits, BIT[7:5]. + */ +#define PINNACLE_REG_FIRMWARE_ID 0x00 /* R */ +#define PINNACLE_REG_FIRMWARE_VERSION 0x01 /* R */ +#define PINNACLE_REG_STATUS1 0x02 /* R/W */ +#define PINNACLE_REG_SYS_CONFIG1 0x03 /* R/W */ +#define PINNACLE_REG_FEED_CONFIG1 0x04 /* R/W */ +#define PINNACLE_REG_FEED_CONFIG2 0x05 /* R/W */ +#define PINNACLE_REG_FEED_CONFIG3 0x06 /* R/W */ +#define PINNACLE_REG_CAL_CONFIG1 0x07 /* R/W */ +#define PINNACLE_REG_PS2_AUX_CONTROL 0x08 /* R/W */ +#define PINNACLE_REG_SAMPLE_RATE 0x09 /* R/W */ +#define PINNACLE_REG_Z_IDLE 0x0A /* R/W */ +#define PINNACLE_REG_Z_SCALER 0x0B /* R/W */ +#define PINNACLE_REG_SLEEP_INTERVAL 0x0C /* R/W */ +#define PINNACLE_REG_SLEEP_TIMER 0x0D /* R/W */ +#define PINNACLE_REG_EMI_THRESHOLD 0x0E /* R/W */ +#define PINNACLE_REG_PACKET_BYTE0 0x12 /* R */ +#define PINNACLE_REG_PACKET_BYTE1 0x13 /* R */ +#define PINNACLE_REG_PACKET_BYTE2 0x14 /* R */ +#define PINNACLE_REG_PACKET_BYTE3 0x15 /* R */ +#define PINNACLE_REG_PACKET_BYTE4 0x16 /* R */ +#define PINNACLE_REG_PACKET_BYTE5 0x17 /* R */ +#define PINNACLE_REG_GPIO_A_CTRL 0x18 /* R/W */ +#define PINNACLE_REG_GPIO_A_DATA 0x19 /* R/W */ +#define PINNACLE_REG_GPIO_B_CTRL_DATA 0x1A /* R/W */ +/* Value of the extended register */ +#define PINNACLE_REG_ERA_VALUE 0x1B /* R/W */ +/* High byte BIT[15:8] of the 16 bit extended register */ +#define PINNACLE_REG_ERA_ADDR_HIGH 0x1C /* R/W */ +/* Low byte BIT[7:0] of the 16 bit extended register */ +#define PINNACLE_REG_ERA_ADDR_LOW 0x1D /* R/W */ +#define PINNACLE_REG_ERA_CTRL 0x1E /* R/W */ +#define PINNACLE_REG_PRODUCT_ID 0x1F /* R */ + +/* Extended Register Access */ +#define PINNACLE_ERA_REG_CONFIG 0x0187 /* R/W */ + +/* Firmware ASIC ID value */ +#define PINNACLE_FIRMWARE_ID 0x07 + +/* Status1 definition */ +#define PINNACLE_STATUS1_SW_DR BIT(2) +#define PINNACLE_STATUS1_SW_CC BIT(3) + +/* SysConfig1 definition */ +#define PINNACLE_SYS_CONFIG1_RESET BIT(0) +#define PINNACLE_SYS_CONFIG1_SHUTDOWN BIT(1) +#define PINNACLE_SYS_CONFIG1_LOW_POWER_MODE BIT(2) + +/* FeedConfig1 definition */ +#define PINNACLE_FEED_CONFIG1_FEED_ENABLE BIT(0) +#define PINNACLE_FEED_CONFIG1_DATA_MODE_ABSOLUTE BIT(1) +#define PINNACLE_FEED_CONFIG1_FILTER_DISABLE BIT(2) +#define PINNACLE_FEED_CONFIG1_X_DISABLE BIT(3) +#define PINNACLE_FEED_CONFIG1_Y_DISABLE BIT(4) +#define PINNACLE_FEED_CONFIG1_X_INVERT BIT(6) +#define PINNACLE_FEED_CONFIG1_Y_INVERT BIT(7) +/* X max to 0 */ +#define PINNACLE_FEED_CONFIG1_X_DATA_INVERT BIT(6) +/* Y max to 0 */ +#define PINNACLE_FEED_CONFIG1_Y_DATA_INVERT BIT(7) + +/* FeedConfig2 definition */ +#define PINNACLE_FEED_CONFIG2_INTELLIMOUSE_ENABLE BIT(0) +#define PINNACLE_FEED_CONFIG2_ALL_TAPS_DISABLE BIT(1) +#define PINNACLE_FEED_CONFIG2_SECONDARY_TAP_DISABLE BIT(2) +#define PINNACLE_FEED_CONFIG2_SCROLL_DISABLE BIT(3) +#define PINNACLE_FEED_CONFIG2_GLIDE_EXTEND_DISABLE BIT(4) +/* 90 degrees rotation */ +#define PINNACLE_FEED_CONFIG2_SWAP_X_AND_Y BIT(7) + +/* Relative position status in PacketByte0 */ +#define PINNACLE_PACKET_BYTE0_BTN_PRIMARY BIT(0) +#define PINNACLE_PACKET_BYTE0_BTN_SECONDRY BIT(1) + +/* Extended Register Access Control */ +#define PINNACLE_ERA_CTRL_READ BIT(0) +#define PINNACLE_ERA_CTRL_WRITE BIT(1) +#define PINNACLE_ERA_CTRL_READ_AUTO_INC BIT(2) +#define PINNACLE_ERA_CTRL_WRITE_AUTO_INC BIT(3) +/* Asserting both BIT(1) and BIT(0) means WRITE/Verify */ +#define PINNACLE_ERA_CTRL_WRITE_VERIFY (BIT(1) | BIT(0)) +#define PINNACLE_ERA_CTRL_COMPLETE 0x00 + +/* Extended Register Access Config */ +#define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X1 0x00 +#define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X2 0x40 +#define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X3 0x80 +#define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X4 0xC0 + +/* + * Delay and retry count for waiting completion of calibration with 200 ms of + * timeout. + */ +#define PINNACLE_CALIBRATION_AWAIT_DELAY_POLL_US 50000 +#define PINNACLE_CALIBRATION_AWAIT_RETRY_COUNT 4 + +/* + * Delay and retry count for waiting completion of ERA command with 50 ms of + * timeout. + */ +#define PINNACLE_ERA_AWAIT_DELAY_POLL_US 10000 +#define PINNACLE_ERA_AWAIT_RETRY_COUNT 5 + +/* Special definitions */ +#define PINNACLE_SPI_FB 0xFB /* Filler byte */ +#define PINNACLE_SPI_FC 0xFC /* Auto-increment byte */ + +/* Read and write masks */ +#define PINNACLE_READ_MSK 0xA0 +#define PINNACLE_WRITE_MSK 0x80 + +/* Read and write register addresses */ +#define PINNACLE_READ_REG(addr) (PINNACLE_READ_MSK | addr) +#define PINNACLE_WRITE_REG(addr) (PINNACLE_WRITE_MSK | addr) + +struct pinnacle_bus { + union { +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) + struct i2c_dt_spec i2c; +#endif +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) + struct spi_dt_spec spi; +#endif + }; + bool (*is_ready)(const struct pinnacle_bus *bus); + int (*write)(const struct pinnacle_bus *bus, uint8_t address, uint8_t value); + int (*seq_write)(const struct pinnacle_bus *bus, uint8_t *address, uint8_t *value, + uint8_t count); + int (*read)(const struct pinnacle_bus *bus, uint8_t address, uint8_t *value); + int (*seq_read)(const struct pinnacle_bus *bus, uint8_t address, uint8_t *data, + uint8_t count); +}; + +enum pinnacle_sensitivity { + PINNACLE_SENSITIVITY_X1, + PINNACLE_SENSITIVITY_X2, + PINNACLE_SENSITIVITY_X3, + PINNACLE_SENSITIVITY_X4, +}; + +struct pinnacle_config { + const struct pinnacle_bus bus; + struct gpio_dt_spec dr_gpio; + + enum pinnacle_sensitivity sensitivity; + bool relative_mode; + uint8_t idle_packets_count; + + bool clipping_enabled; + bool scaling_enabled; + bool invert_x; + bool invert_y; + bool primary_tap_enabled; + bool swap_xy; + + uint16_t active_range_x_min; + uint16_t active_range_x_max; + uint16_t active_range_y_min; + uint16_t active_range_y_max; + + uint16_t resolution_x; + uint16_t resolution_y; +}; + +union pinnacle_sample { + struct { + uint16_t abs_x; + uint16_t abs_y; + uint8_t abs_z; + }; + struct { + int16_t rel_x; + int16_t rel_y; + bool btn_primary; + }; +}; + +struct pinnacle_data { + union pinnacle_sample sample; + const struct device *dev; + struct gpio_callback dr_cb_data; + struct k_work work; +}; + +static inline bool pinnacle_bus_is_ready(const struct device *dev) +{ + const struct pinnacle_config *config = dev->config; + + return config->bus.is_ready(&config->bus); +} + +static inline int pinnacle_write(const struct device *dev, uint8_t address, uint8_t value) +{ + const struct pinnacle_config *config = dev->config; + + return config->bus.write(&config->bus, address, value); +} +static inline int pinnacle_seq_write(const struct device *dev, uint8_t *address, uint8_t *value, + uint8_t count) +{ + const struct pinnacle_config *config = dev->config; + + return config->bus.seq_write(&config->bus, address, value, count); +} +static inline int pinnacle_read(const struct device *dev, uint8_t address, uint8_t *value) +{ + const struct pinnacle_config *config = dev->config; + + return config->bus.read(&config->bus, address, value); +} + +static inline int pinnacle_seq_read(const struct device *dev, uint8_t address, uint8_t *data, + uint8_t count) +{ + const struct pinnacle_config *config = dev->config; + + return config->bus.seq_read(&config->bus, address, data, count); +} + +static inline int pinnacle_clear_cmd_complete(const struct device *dev) +{ + const struct pinnacle_config *config = dev->config; + + return config->bus.write(&config->bus, PINNACLE_REG_STATUS1, 0x00); +} + +static int pinnacle_era_wait_for_completion(const struct device *dev) +{ + int rc; + uint8_t value; + + rc = WAIT_FOR(!pinnacle_read(dev, PINNACLE_REG_ERA_CTRL, &value) && + value == PINNACLE_ERA_CTRL_COMPLETE, + PINNACLE_ERA_AWAIT_RETRY_COUNT * PINNACLE_ERA_AWAIT_DELAY_POLL_US, + k_sleep(K_USEC(PINNACLE_ERA_AWAIT_DELAY_POLL_US))); + if (rc < 0) { + return -EIO; + } + + return 0; +} + +static int pinnacle_era_write(const struct device *dev, uint16_t address, uint8_t value) +{ + uint8_t address_buf[] = { + PINNACLE_REG_ERA_VALUE, + PINNACLE_REG_ERA_ADDR_HIGH, + PINNACLE_REG_ERA_ADDR_LOW, + PINNACLE_REG_ERA_CTRL, + }; + uint8_t value_buf[] = { + value, + address >> 8, + address & 0xFF, + PINNACLE_ERA_CTRL_WRITE, + }; + int rc; + + rc = pinnacle_seq_write(dev, address_buf, value_buf, sizeof(address_buf)); + if (rc) { + return rc; + } + + return pinnacle_era_wait_for_completion(dev); +} + +static int pinnacle_era_read(const struct device *dev, uint16_t address, uint8_t *value) +{ + uint8_t address_buf[] = { + PINNACLE_REG_ERA_ADDR_HIGH, + PINNACLE_REG_ERA_ADDR_LOW, + PINNACLE_REG_ERA_CTRL, + }; + uint8_t value_buf[] = { + address >> 8, + address & 0xFF, + PINNACLE_ERA_CTRL_READ, + }; + int rc; + + rc = pinnacle_seq_write(dev, address_buf, value_buf, sizeof(address_buf)); + if (rc) { + return rc; + } + + rc = pinnacle_era_wait_for_completion(dev); + if (rc) { + return rc; + } + + return pinnacle_read(dev, PINNACLE_REG_ERA_VALUE, value); +} + +static int pinnacle_set_sensitivity(const struct device *dev) +{ + const struct pinnacle_config *config = dev->config; + + uint8_t value; + int rc; + + rc = pinnacle_era_read(dev, PINNACLE_ERA_REG_CONFIG, &value); + if (rc) { + return rc; + } + + /* Clear BIT(7) and BIT(6) */ + value &= 0x3F; + + switch (config->sensitivity) { + case PINNACLE_SENSITIVITY_X1: + value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X1; + break; + case PINNACLE_SENSITIVITY_X2: + value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X2; + break; + case PINNACLE_SENSITIVITY_X3: + value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X3; + break; + case PINNACLE_SENSITIVITY_X4: + value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X4; + break; + } + + rc = pinnacle_era_write(dev, PINNACLE_ERA_REG_CONFIG, value); + if (rc) { + return rc; + } + + /* Clear SW_CC after setting sensitivity */ + rc = pinnacle_clear_cmd_complete(dev); + if (rc) { + return rc; + } + + return 0; +} + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +static bool pinnacle_is_ready_i2c(const struct pinnacle_bus *bus) +{ + if (!i2c_is_ready_dt(&bus->i2c)) { + LOG_ERR("I2C bus %s is not ready", bus->i2c.bus->name); + return false; + } + + return true; +} + +static int pinnacle_write_i2c(const struct pinnacle_bus *bus, uint8_t address, uint8_t value) +{ + uint8_t buf[] = {PINNACLE_WRITE_REG(address), value}; + + return i2c_write_dt(&bus->i2c, buf, 2); +} + +static int pinnacle_seq_write_i2c(const struct pinnacle_bus *bus, uint8_t *address, uint8_t *value, + uint8_t count) +{ + uint8_t buf[count * 2]; + + for (uint8_t i = 0; i < count; ++i) { + buf[i * 2] = PINNACLE_WRITE_REG(address[i]); + buf[i * 2 + 1] = value[i]; + } + + return i2c_write_dt(&bus->i2c, buf, count * 2); +} + +static int pinnacle_read_i2c(const struct pinnacle_bus *bus, uint8_t address, uint8_t *value) +{ + uint8_t reg = PINNACLE_READ_REG(address); + + return i2c_write_read_dt(&bus->i2c, ®, 1, value, 1); +} + +static int pinnacle_seq_read_i2c(const struct pinnacle_bus *bus, uint8_t address, uint8_t *buf, + uint8_t count) +{ + uint8_t reg = PINNACLE_READ_REG(address); + + return i2c_burst_read_dt(&bus->i2c, reg, buf, count); +} +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +static bool pinnacle_is_ready_spi(const struct pinnacle_bus *bus) +{ + if (!spi_is_ready_dt(&bus->spi)) { + LOG_ERR("SPI bus %s is not ready", bus->spi.bus->name); + return false; + } + + return true; +} + +static int pinnacle_write_spi(const struct pinnacle_bus *bus, uint8_t address, uint8_t value) +{ + uint8_t tx_data[] = { + PINNACLE_WRITE_REG(address), + value, + }; + const struct spi_buf tx_buf[] = {{ + .buf = tx_data, + .len = sizeof(tx_data), + }}; + const struct spi_buf_set tx_set = { + .buffers = tx_buf, + .count = ARRAY_SIZE(tx_buf), + }; + + return spi_write_dt(&bus->spi, &tx_set); +} + +static int pinnacle_seq_write_spi(const struct pinnacle_bus *bus, uint8_t *address, uint8_t *value, + uint8_t count) +{ + uint8_t tx_data[count * 2]; + const struct spi_buf tx_buf[] = {{ + .buf = tx_data, + .len = sizeof(tx_data), + }}; + const struct spi_buf_set tx_set = { + .buffers = tx_buf, + .count = ARRAY_SIZE(tx_buf), + }; + + for (uint8_t i = 0; i < count; ++i) { + tx_data[i * 2] = PINNACLE_WRITE_REG(address[i]); + tx_data[i * 2 + 1] = value[i]; + } + + return spi_write_dt(&bus->spi, &tx_set); +} + +static int pinnacle_read_spi(const struct pinnacle_bus *bus, uint8_t address, uint8_t *value) +{ + uint8_t tx_data[] = { + PINNACLE_READ_REG(address), + PINNACLE_SPI_FB, + PINNACLE_SPI_FB, + PINNACLE_SPI_FB, + }; + const struct spi_buf tx_buf[] = {{ + .buf = tx_data, + .len = sizeof(tx_data), + }}; + const struct spi_buf_set tx_set = { + .buffers = tx_buf, + .count = ARRAY_SIZE(tx_buf), + }; + + const struct spi_buf rx_buf[] = { + { + .buf = NULL, + .len = 3, + }, + { + .buf = value, + .len = 1, + }, + }; + const struct spi_buf_set rx_set = { + .buffers = rx_buf, + .count = ARRAY_SIZE(rx_buf), + }; + + int rc; + + rc = spi_transceive_dt(&bus->spi, &tx_set, &rx_set); + if (rc) { + LOG_ERR("Failed to read from SPI %s", bus->spi.bus->name); + return rc; + } + + return 0; +} + +static int pinnacle_seq_read_spi(const struct pinnacle_bus *bus, uint8_t address, uint8_t *buf, + uint8_t count) +{ + + uint8_t size = count + 3; + uint8_t tx_data[size]; + + tx_data[0] = PINNACLE_READ_REG(address); + tx_data[1] = PINNACLE_SPI_FC; + tx_data[2] = PINNACLE_SPI_FC; + + uint8_t i = 3; + + for (; i < (count + 2); ++i) { + tx_data[i] = PINNACLE_SPI_FC; + } + + tx_data[i++] = PINNACLE_SPI_FB; + + const struct spi_buf tx_buf[] = {{ + .buf = tx_data, + .len = size, + }}; + const struct spi_buf_set tx_set = { + .buffers = tx_buf, + .count = 1, + }; + + const struct spi_buf rx_buf[] = { + { + .buf = NULL, + .len = 3, + }, + { + .buf = buf, + .len = count, + }, + }; + const struct spi_buf_set rx_set = { + .buffers = rx_buf, + .count = ARRAY_SIZE(rx_buf), + }; + + int rc; + + rc = spi_transceive_dt(&bus->spi, &tx_set, &rx_set); + if (rc) { + LOG_ERR("Failed to read from SPI %s", bus->spi.bus->name); + return rc; + } + + return 0; +} +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ + +static void pinnacle_decode_sample(const struct device *dev, uint8_t *rx, + union pinnacle_sample *sample) +{ + const struct pinnacle_config *config = dev->config; + + if (config->relative_mode) { + if (config->primary_tap_enabled) { + sample->btn_primary = (rx[0] & BIT(0)) == BIT(0); + } + sample->rel_x = ((rx[0] & BIT(4)) == BIT(4)) ? -(256 - rx[1]) : rx[1]; + sample->rel_y = ((rx[0] & BIT(5)) == BIT(5)) ? -(256 - rx[2]) : rx[2]; + } else { + sample->abs_x = ((rx[2] & 0x0F) << 8) | rx[0]; + sample->abs_y = ((rx[2] & 0xF0) << 4) | rx[1]; + sample->abs_z = rx[3] & 0x3F; + } +} + +static bool pinnacle_is_idle_sample(const union pinnacle_sample *sample) +{ + return (sample->abs_x == 0 && sample->abs_y == 0 && sample->abs_z == 0); +} + +static void pinnacle_clip_sample(const struct device *dev, union pinnacle_sample *sample) +{ + const struct pinnacle_config *config = dev->config; + + if (sample->abs_x < config->active_range_x_min) { + sample->abs_x = config->active_range_x_min; + } + if (sample->abs_x > config->active_range_x_max) { + sample->abs_x = config->active_range_x_max; + } + if (sample->abs_y < config->active_range_y_min) { + sample->abs_y = config->active_range_y_min; + } + if (sample->abs_y > config->active_range_y_max) { + sample->abs_y = config->active_range_y_max; + } +} + +static void pinnacle_scale_sample(const struct device *dev, union pinnacle_sample *sample) +{ + const struct pinnacle_config *config = dev->config; + + uint16_t range_x = config->active_range_x_max - config->active_range_x_min; + uint16_t range_y = config->active_range_y_max - config->active_range_y_min; + + sample->abs_x = (uint16_t)((uint32_t)(sample->abs_x - config->active_range_x_min) * + config->resolution_x / range_x); + sample->abs_y = (uint16_t)((uint32_t)(sample->abs_y - config->active_range_y_min) * + config->resolution_y / range_y); +} + +static int pinnacle_sample_fetch(const struct device *dev, union pinnacle_sample *sample) +{ + const struct pinnacle_config *config = dev->config; + + uint8_t rx[4]; + int rc; + + if (config->relative_mode) { + rc = pinnacle_seq_read(dev, PINNACLE_REG_PACKET_BYTE0, rx, 3); + } else { + rc = pinnacle_seq_read(dev, PINNACLE_REG_PACKET_BYTE2, rx, 4); + } + + if (rc) { + LOG_ERR("Failed to read data from SPI device"); + return rc; + } + + pinnacle_decode_sample(dev, rx, sample); + + rc = pinnacle_write(dev, PINNACLE_REG_STATUS1, 0x00); + if (rc) { + LOG_ERR("Failed to clear SW_CC and SW_DR"); + return rc; + } + + return 0; +} + +static int pinnacle_handle_interrupt(const struct device *dev) +{ + const struct pinnacle_config *config = dev->config; + struct pinnacle_data *drv_data = dev->data; + union pinnacle_sample *sample = &drv_data->sample; + + int rc; + + rc = pinnacle_sample_fetch(dev, sample); + if (rc) { + LOG_ERR("Failed to read data packets"); + return rc; + } + + if (config->relative_mode) { + input_report_rel(dev, INPUT_REL_X, sample->rel_x, false, K_FOREVER); + input_report_rel(dev, INPUT_REL_Y, sample->rel_y, !config->primary_tap_enabled, + K_FOREVER); + if (config->primary_tap_enabled) { + input_report_key(dev, INPUT_BTN_TOUCH, sample->btn_primary, true, + K_FOREVER); + } + } else { + if (config->clipping_enabled && !pinnacle_is_idle_sample(sample)) { + pinnacle_clip_sample(dev, sample); + if (config->scaling_enabled) { + pinnacle_scale_sample(dev, sample); + } + } + + input_report_abs(dev, INPUT_ABS_X, sample->abs_x, false, K_FOREVER); + input_report_abs(dev, INPUT_ABS_Y, sample->abs_y, false, K_FOREVER); + input_report_abs(dev, INPUT_ABS_Z, sample->abs_z, true, K_FOREVER); + } + + return 0; +} + +static void pinnacle_data_ready_gpio_callback(const struct device *dev, struct gpio_callback *cb, + uint32_t pins) +{ + struct pinnacle_data *drv_data = CONTAINER_OF(cb, struct pinnacle_data, dr_cb_data); + + k_work_submit(&drv_data->work); +} + +static void pinnacle_work_cb(struct k_work *work) +{ + struct pinnacle_data *drv_data = CONTAINER_OF(work, struct pinnacle_data, work); + + pinnacle_handle_interrupt(drv_data->dev); +} + +int pinnacle_init_interrupt(const struct device *dev) +{ + struct pinnacle_data *drv_data = dev->data; + const struct pinnacle_config *config = dev->config; + const struct gpio_dt_spec *gpio = &config->dr_gpio; + + int rc; + + drv_data->dev = dev; + drv_data->work.handler = pinnacle_work_cb; + + /* Configure GPIO pin for HW_DR signal */ + rc = gpio_is_ready_dt(gpio); + if (!rc) { + LOG_ERR("GPIO device %s/%d is not ready", gpio->port->name, gpio->pin); + return -ENODEV; + } + + rc = gpio_pin_configure_dt(gpio, GPIO_INPUT); + if (rc) { + LOG_ERR("Failed to configure %s/%d as input", gpio->port->name, gpio->pin); + return rc; + } + + rc = gpio_pin_interrupt_configure_dt(gpio, GPIO_INT_EDGE_TO_ACTIVE); + if (rc) { + LOG_ERR("Failed to configured interrupt for %s/%d", gpio->port->name, gpio->pin); + return rc; + } + + gpio_init_callback(&drv_data->dr_cb_data, pinnacle_data_ready_gpio_callback, + BIT(gpio->pin)); + + rc = gpio_add_callback(gpio->port, &drv_data->dr_cb_data); + if (rc) { + LOG_ERR("Failed to configured interrupt for %s/%d", gpio->port->name, gpio->pin); + return rc; + } + + return 0; +} + +static int pinnacle_init(const struct device *dev) +{ + const struct pinnacle_config *config = dev->config; + + int rc; + uint8_t value; + + if (!pinnacle_bus_is_ready(dev)) { + return -ENODEV; + } + + rc = pinnacle_read(dev, PINNACLE_REG_FIRMWARE_ID, &value); + if (rc) { + LOG_ERR("Failed to read FirmwareId"); + return rc; + } + + if (value != PINNACLE_FIRMWARE_ID) { + LOG_ERR("Incorrect Firmware ASIC ID %x", value); + return -ENODEV; + } + + /* Wait until the calibration is completed (SW_CC is asserted) */ + rc = WAIT_FOR(!pinnacle_read(dev, PINNACLE_REG_STATUS1, &value) && + (value & PINNACLE_STATUS1_SW_CC) == PINNACLE_STATUS1_SW_CC, + PINNACLE_CALIBRATION_AWAIT_RETRY_COUNT * + PINNACLE_CALIBRATION_AWAIT_DELAY_POLL_US, + k_sleep(K_USEC(PINNACLE_CALIBRATION_AWAIT_DELAY_POLL_US))); + if (rc < 0) { + LOG_ERR("Failed to wait for calibration complition"); + return -EIO; + } + + /* Clear SW_CC after Power on Reset */ + rc = pinnacle_clear_cmd_complete(dev); + if (rc) { + LOG_ERR("Failed to clear SW_CC in Status1"); + return -EIO; + } + + /* Set trackpad sensitivity */ + rc = pinnacle_set_sensitivity(dev); + if (rc) { + LOG_ERR("Failed to set sensitivity"); + return -EIO; + } + + rc = pinnacle_write(dev, PINNACLE_REG_SYS_CONFIG1, 0x00); + if (rc) { + LOG_ERR("Failed to write SysConfig1"); + return rc; + } + + /* Relative mode features */ + if (config->relative_mode) { + value = (PINNACLE_FEED_CONFIG2_GLIDE_EXTEND_DISABLE | + PINNACLE_FEED_CONFIG2_SCROLL_DISABLE | + PINNACLE_FEED_CONFIG2_SECONDARY_TAP_DISABLE); + if (config->swap_xy) { + value |= PINNACLE_FEED_CONFIG2_SWAP_X_AND_Y; + } + if (!config->primary_tap_enabled) { + value |= PINNACLE_FEED_CONFIG2_ALL_TAPS_DISABLE; + } + } else { + value = (PINNACLE_FEED_CONFIG2_GLIDE_EXTEND_DISABLE | + PINNACLE_FEED_CONFIG2_SCROLL_DISABLE | + PINNACLE_FEED_CONFIG2_SECONDARY_TAP_DISABLE | + PINNACLE_FEED_CONFIG2_ALL_TAPS_DISABLE); + } + rc = pinnacle_write(dev, PINNACLE_REG_FEED_CONFIG2, value); + if (rc) { + LOG_ERR("Failed to write FeedConfig2"); + return rc; + } + + /* Data output flags */ + value = PINNACLE_FEED_CONFIG1_FEED_ENABLE; + if (!config->relative_mode) { + value |= PINNACLE_FEED_CONFIG1_DATA_MODE_ABSOLUTE; + if (config->invert_x) { + value |= PINNACLE_FEED_CONFIG1_X_INVERT; + } + if (config->invert_y) { + value |= PINNACLE_FEED_CONFIG1_Y_INVERT; + } + } + rc = pinnacle_write(dev, PINNACLE_REG_FEED_CONFIG1, value); + if (rc) { + LOG_ERR("Failed to enable Feed in FeedConfig1"); + return rc; + } + + /* Configure count of Z-Idle packets */ + rc = pinnacle_write(dev, PINNACLE_REG_Z_IDLE, config->idle_packets_count); + if (rc) { + LOG_ERR("Failed to set count of Z-idle packets"); + return rc; + } + + rc = pinnacle_init_interrupt(dev); + if (rc) { + LOG_ERR("Failed to initialize interrupts"); + return rc; + } + + return 0; +} + +#define PINNACLE_CONFIG_BUS_I2C(inst) \ + .bus = { \ + .i2c = I2C_DT_SPEC_INST_GET(inst), \ + .is_ready = pinnacle_is_ready_i2c, \ + .write = pinnacle_write_i2c, \ + .seq_write = pinnacle_seq_write_i2c, \ + .read = pinnacle_read_i2c, \ + .seq_read = pinnacle_seq_read_i2c, \ + } + +#define PINNACLE_SPI_OP (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_MODE_CPHA | SPI_WORD_SET(8)) +#define PINNACLE_CONFIG_BUS_SPI(inst) \ + .bus = { \ + .spi = SPI_DT_SPEC_INST_GET(inst, PINNACLE_SPI_OP, 0U), \ + .is_ready = pinnacle_is_ready_spi, \ + .write = pinnacle_write_spi, \ + .seq_write = pinnacle_seq_write_spi, \ + .read = pinnacle_read_spi, \ + .seq_read = pinnacle_seq_read_spi, \ + } + +#define PINNACLE_DEFINE(inst) \ + static const struct pinnacle_config pinnacle_config_##inst = { \ + COND_CODE_1(DT_INST_ON_BUS(inst, i2c), (PINNACLE_CONFIG_BUS_I2C(inst),), ()) \ + COND_CODE_1(DT_INST_ON_BUS(inst, spi), (PINNACLE_CONFIG_BUS_SPI(inst),), ()) \ + .dr_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, data_ready_gpios, {}), \ + .relative_mode = DT_INST_ENUM_IDX(inst, data_mode), \ + .sensitivity = DT_INST_ENUM_IDX(inst, sensitivity), \ + .idle_packets_count = DT_INST_PROP(inst, idle_packets_count), \ + .clipping_enabled = DT_INST_PROP(inst, clipping_enable), \ + .active_range_x_min = DT_INST_PROP(inst, active_range_x_min), \ + .active_range_x_max = DT_INST_PROP(inst, active_range_x_max), \ + .active_range_y_min = DT_INST_PROP(inst, active_range_y_min), \ + .active_range_y_max = DT_INST_PROP(inst, active_range_y_max), \ + .scaling_enabled = DT_INST_PROP(inst, scaling_enable), \ + .resolution_x = DT_INST_PROP(inst, scaling_x_resolution), \ + .resolution_y = DT_INST_PROP(inst, scaling_y_resolution), \ + .invert_x = DT_INST_PROP(inst, invert_x), \ + .invert_y = DT_INST_PROP(inst, invert_y), \ + .primary_tap_enabled = DT_INST_PROP(inst, primary_tap_enable), \ + .swap_xy = DT_INST_PROP(inst, swap_xy), \ + }; \ + static struct pinnacle_data pinnacle_data_##inst; \ + DEVICE_DT_INST_DEFINE(inst, pinnacle_init, NULL, &pinnacle_data_##inst, \ + &pinnacle_config_##inst, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \ + NULL); \ + BUILD_ASSERT(DT_INST_PROP(inst, active_range_x_min) < \ + DT_INST_PROP(inst, active_range_x_max), \ + "active-range-x-min must be less than active-range-x-max"); \ + BUILD_ASSERT(DT_INST_PROP(inst, active_range_y_min) < \ + DT_INST_PROP(inst, active_range_y_max), \ + "active_range-y-min must be less than active_range-y-max"); \ + BUILD_ASSERT(DT_INST_PROP(inst, scaling_x_resolution) > 0, \ + "scaling-x-resolution must be positive"); \ + BUILD_ASSERT(DT_INST_PROP(inst, scaling_y_resolution) > 0, \ + "scaling-y-resolution must be positive"); \ + BUILD_ASSERT(IN_RANGE(DT_INST_PROP(inst, idle_packets_count), 0, UINT8_MAX), \ + "idle-packets-count must be in range [0:255]"); + +DT_INST_FOREACH_STATUS_OKAY(PINNACLE_DEFINE) diff --git a/dts/bindings/input/cirque,pinnacle-common.yaml b/dts/bindings/input/cirque,pinnacle-common.yaml new file mode 100644 index 00000000000..6ea3a96a7bc --- /dev/null +++ b/dts/bindings/input/cirque,pinnacle-common.yaml @@ -0,0 +1,113 @@ +# Copyright (c) 2024 Ilia Kharin +# SPDX-License-Identifier: Apache-2.0 + +description: Cirque Pinnacle 1CA027 ASIC trackpad + +properties: + data-ready-gpios: + type: phandle-array + description: | + Data Ready (DR) GPIO pin. The DR pin is connected to Pinnacle HW_DR + which is active high when SW_DR or SW_CC are asserted. If connected + directly, the MCU pin should be configured as active low. + + sensitivity: + type: string + default: "4x" + description: | + ADC attenuation, 1x is the most sensitive and 4x is the least sensitive. + enum: + - "1x" + - "2x" + - "3x" + - "4x" + + data-mode: + type: string + default: "relative" + description: | + Data output mode in which position is reported. In the relative mode + each position is reported as relative to the last position. In the + absolute mode absolute coordinates are reported. + enum: + - "absolute" + - "relative" + + idle-packets-count: + type: int + default: 0 + description: | + The number of empty packets where both X and Y are set to 0. They are + started to be sent when a finger presence is detected missing (no touch + detected) every 10 ms. They are stopped to be sent when a finger presence + it detected. An application can count these packets in order to detect + taps. When set to 0, no empty packets are sent. Supported values from 0 + to 255. + + clipping-enable: + type: boolean + description: | + In the absolute mode enable clipping of reported coordinates which are + outside of the active range. + + active-range-x-min: + type: int + default: 128 + description: | + The minimum X value which can be reported. + + active-range-x-max: + type: int + default: 1920 + description: | + The maximum X value which can be reported. + + active-range-y-min: + type: int + default: 64 + description: | + The minimum Y value which can be reported. + + active-range-y-max: + type: int + default: 1472 + description: | + The maximum Y value which can be reported. + + scaling-enable: + type: boolean + description: | + In the absolute mode enable scaling of coordinates according to + the specified resolution for X and Y axises. The scaling is applied only + when the clipping is enabled. + + scaling-x-resolution: + type: int + default: 1024 + description: Resolution for the X axis. + + scaling-y-resolution: + type: int + default: 1024 + description: Resolution for the Y axis. + + invert-x: + type: boolean + description: | + In the absolute mode invert X coordinate. + + invert-y: + type: boolean + description: | + In the absolute mode invert Y coordinate. + + primary-tap-enable: + type: boolean + description: | + In the relative mode enable the primary tap. + + swap-xy: + type: boolean + description: | + In the relative mode swap X and Y coordinates. This is equivalent for + rotating coordinates by 90 degrees. diff --git a/dts/bindings/input/cirque,pinnacle-i2c.yaml b/dts/bindings/input/cirque,pinnacle-i2c.yaml new file mode 100644 index 00000000000..3878028ea6b --- /dev/null +++ b/dts/bindings/input/cirque,pinnacle-i2c.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Ilia Kharin +# SPDX-License-Identifier: Apache-2.0 + +description: Cirque Pinnacle 1CA027 ASIC trackpad connected through I2C + +compatible: "cirque,pinnacle" + +include: ["i2c-device.yaml", "cirque,pinnacle-common.yaml"] diff --git a/dts/bindings/input/cirque,pinnacle-spi.yaml b/dts/bindings/input/cirque,pinnacle-spi.yaml new file mode 100644 index 00000000000..8a35c62a7a7 --- /dev/null +++ b/dts/bindings/input/cirque,pinnacle-spi.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Ilia Kharin +# SPDX-License-Identifier: Apache-2.0 + +description: Cirque Pinnacle 1CA027 ASIC trackpad connected through SPI + +compatible: "cirque,pinnacle" + +include: ["spi-device.yaml", "cirque,pinnacle-common.yaml"] diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index adb976f0851..fe3d98c90f0 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -134,6 +134,7 @@ chunghwa Chunghwa Picture Tubes Ltd. chuwi Chuwi Innovation Ltd. ciaa Computadora Industrial Abierta Argentina circuitdojo Circuit Dojo +cirque Cirque Corporation cirrus Cirrus Logic, Inc. cisco Cisco Systems, Inc. cloudengines Cloud Engines, Inc. diff --git a/tests/drivers/build_all/input/app.overlay b/tests/drivers/build_all/input/app.overlay index b34d781bf53..a5c3c0aff5d 100644 --- a/tests/drivers/build_all/input/app.overlay +++ b/tests/drivers/build_all/input/app.overlay @@ -218,6 +218,14 @@ int-gpios = <&test_gpio 0 0>; }; + pinnacle@2a { + compatible = "cirque,pinnacle"; + reg = <0x2a>; + data-ready-gpios = <&test_gpio 0 0>; + data-mode = "relative"; + primary-tap-enable; + swap-xy; + }; }; spi@2 { @@ -230,7 +238,8 @@ /* one entry for every devices */ cs-gpios = <&test_gpio 0 0>, - <&test_gpio 0 0>; + <&test_gpio 1 0>, + <&test_gpio 2 0>; xpt2046@0 { compatible = "xptek,xpt2046"; @@ -258,6 +267,19 @@ force-awake; smart-mode; }; + + pinnacle@2 { + compatible = "cirque,pinnacle"; + reg = <0x2>; + spi-max-frequency = <0>; + data-ready-gpios = <&test_gpio 0 0>; + data-mode = "absolute"; + idle-packets-count = <20>; + clipping-enable; + scaling-enable; + invert-x; + invert-y; + }; }; }; }; From 10592b9df4f851a476a094530f583ab0b5c90309 Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Wed, 3 Apr 2024 22:46:02 +0800 Subject: [PATCH 1806/2402] subsys/mgmt/hawkbit: change 'Hawkbit' & 'hawkbit' to 'hawkBit' Change 'Hawkbit' and 'hawkbit' to 'hawkBit' wherever makes sense, and a bit of touch ups here and there. Signed-off-by: Yong Cong Sin --- samples/subsys/mgmt/hawkbit/Kconfig | 8 ++++---- samples/subsys/mgmt/hawkbit/README.rst | 24 ++++++++++++------------ samples/subsys/mgmt/hawkbit/prj.conf | 8 ++++---- samples/subsys/mgmt/hawkbit/sample.yaml | 2 +- samples/subsys/mgmt/hawkbit/src/main.c | 12 ++++++------ subsys/mgmt/hawkbit/Kconfig | 20 ++++++++++---------- subsys/mgmt/hawkbit/hawkbit.c | 6 +++--- subsys/mgmt/hawkbit/hawkbit_priv.h | 2 +- subsys/mgmt/hawkbit/shell.c | 10 +++++----- 9 files changed, 46 insertions(+), 46 deletions(-) diff --git a/samples/subsys/mgmt/hawkbit/Kconfig b/samples/subsys/mgmt/hawkbit/Kconfig index 7c8c0e21168..6550b691fa0 100644 --- a/samples/subsys/mgmt/hawkbit/Kconfig +++ b/samples/subsys/mgmt/hawkbit/Kconfig @@ -3,22 +3,22 @@ # # SPDX-License-Identifier: Apache-2.0 # -mainmenu "Hawkbit sample configuration" +mainmenu "hawkBit sample configuration" choice - prompt "Hawkbit mode" + prompt "hawkBit mode" default HAWKBIT_POLLING depends on HAWKBIT config HAWKBIT_POLLING - bool "Hawkbit Polling mode" + bool "hawkBit Polling mode" help Polling mode runs automatically on a predefined period, probing the server for updates and installing them without requiring user intervention. config HAWKBIT_MANUAL - bool "Hawkbit manual mode" + bool "hawkBit manual mode" help Manual mode requires the user to call the server probe and then, if there is an available update, also requires the user to decide if diff --git a/samples/subsys/mgmt/hawkbit/README.rst b/samples/subsys/mgmt/hawkbit/README.rst index db96c518213..4f770ca333b 100644 --- a/samples/subsys/mgmt/hawkbit/README.rst +++ b/samples/subsys/mgmt/hawkbit/README.rst @@ -11,7 +11,7 @@ The Eclipse hawkBit update server provides REST resources which are consumed by device to retrieve software update tasks. This API is based on HTTP standards and a polling mechanism. -This sample shows how to use Hawkbit DDI API in both a polling and manual +This sample shows how to use hawkBit DDI API in both a polling and manual update mode. Polling mode run automatically on a predefined period, probing the server @@ -25,7 +25,7 @@ source code for this mode hawkbit_manual Caveats ******* -* The Zephyr port of ``Hawkbit`` is configured to run on a +* The Zephyr port of hawkBit is configured to run on a :ref:`Freedom-K64F ` MCU by default. The application should build and run for other platforms with support internet connection. Some platforms need some modification. Overlay files would be needed to support @@ -33,14 +33,14 @@ Caveats understanding that most other connectivity options would require an edge gateway of some sort (Border Router, etc). -* The MCUboot bootloader is required for ``Hawkbit`` to function properly. +* The MCUboot bootloader is required for hawkBit to function properly. More information about the Device Firmware Upgrade subsystem and MCUboot can be found in :ref:`mcuboot`. Building and Running ******************** -The below steps describe how to build and run the ``Hawkbit`` sample in +The below steps describe how to build and run the hawkBit sample in Zephyr. Where examples are given, it is assumed the sample is being build for the Freedom-K64F Development Kit (``BOARD=frdm_k64f``). @@ -60,7 +60,7 @@ be done by, west flash -Step 3: Start the Hawkbit Docker +Step 3: Start the hawkBit Docker ================================ By default, the hawkbit application is set to run on http at port:8080. @@ -75,10 +75,10 @@ This will start the hawkbit server on the host system.Opening your browser to the server URL, ``:8080``, and logging into the server using ``admin`` as the login and password by default. -Step 4: Build Hawkbit +Step 4: Build hawkBit ===================== -``Hawkbit`` can be built for the frdm_k64f as follows: +hawkBit can be built for the frdm_k64f as follows: .. zephyr-app-commands:: :zephyr-app: samples/subsys/mgmt/hawkbit @@ -102,7 +102,7 @@ From this section onwards you use a binary (``.bin``) image format. The command above creates a signed and confirmed image file called :file:`zephyr.signed.confirmed.bin` in the build directory. It's important for the first image to be confirmed as MCUboot isn't able to confirm an image that -is flashed using a hardware tool, and Hawkbit will reboot to trigger a firmware +is flashed using a hardware tool, and hawkBit will reboot to trigger a firmware swap if it isn't able to confirm the running image on init. Step 6: Flash the first image @@ -123,7 +123,7 @@ upload a firmware binary to the server, and update it using this UI. Step 7: Building and signing the test image =========================================== -The easiest way to test the functionality of Hawkbit is to repeat step 4 to +The easiest way to test the functionality of hawkBit is to repeat step 4 to build the sample again, so that the build time will be different. Then, similar to step 5, sign the image and assign it a different version number but without confirming it like so: @@ -143,7 +143,7 @@ Then upload the signed image to the server with Upload file Icon. Click on distribution icon in the left pane of UI and create a new Distribution with type Apps only (``name:frdm_k64f_update,version:1.0.1``). Assign the -``hawkbit`` software module to the created distribution. Click on Deployment +hawkBit software module to the created distribution. Click on Deployment icon in the left pane of UI and assign the ``frdm_k64f_update`` distribution to the target ``frdm_k64f``. @@ -278,13 +278,13 @@ Change authentication security from false to true. java -jar ./hawkbit-runtime/hawkbit-update-server/target/ \ hawkbit-update-server-#version#-SNAPSHOT.jar -Step 11: Build Hawkbit HTTPS +Step 11: Build hawkBit HTTPS ============================ * Convert the server.pem file to self_sign.der and place the der file in hawkbit/src directory -``Hawkbit https`` can be built for the frdm_k64f as follows: +``hawkBit https`` can be built for the frdm_k64f as follows: .. zephyr-app-commands:: :zephyr-app: samples/subsys/mgmt/hawkbit diff --git a/samples/subsys/mgmt/hawkbit/prj.conf b/samples/subsys/mgmt/hawkbit/prj.conf index e8539c7a120..9c2362964cc 100644 --- a/samples/subsys/mgmt/hawkbit/prj.conf +++ b/samples/subsys/mgmt/hawkbit/prj.conf @@ -1,4 +1,4 @@ -#Turn on the Hawkbit +#Enable hawkBit CONFIG_HAWKBIT=y CONFIG_NVS=y CONFIG_FLASH=y @@ -18,7 +18,7 @@ CONFIG_BOOTLOADER_MCUBOOT=y #Main Stack Size CONFIG_MAIN_STACK_SIZE=4096 -#Minimal Heap mem pool size for the Hawkbit working +#Minimal Heap mem pool size for hawkBit to work CONFIG_HEAP_MEM_POOL_SIZE=4096 CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096 @@ -42,10 +42,10 @@ CONFIG_HAWKBIT_SHELL=y CONFIG_KERNEL_SHELL=y CONFIG_SHELL_STACK_SIZE=4096 -#Hawkbit polling mode +#hawkBit polling mode CONFIG_HAWKBIT_POLLING=y -#Config Hawkbit Server +#Config hawkBit Server CONFIG_HAWKBIT_SERVER="192.168.1.110" #Debug helpers diff --git a/samples/subsys/mgmt/hawkbit/sample.yaml b/samples/subsys/mgmt/hawkbit/sample.yaml index 6a60360e423..5e161132099 100644 --- a/samples/subsys/mgmt/hawkbit/sample.yaml +++ b/samples/subsys/mgmt/hawkbit/sample.yaml @@ -1,7 +1,7 @@ common: filter: CONFIG_FULL_LIBC_SUPPORTED sample: - description: Hawkbit Firmware Over-the-Air (FOTA) + description: hawkBit Firmware Over-the-Air (FOTA) name: hawkbit tests: sample.net.hawkbit: diff --git a/samples/subsys/mgmt/hawkbit/src/main.c b/samples/subsys/mgmt/hawkbit/src/main.c index cceff82b87a..3e917f614a4 100644 --- a/samples/subsys/mgmt/hawkbit/src/main.c +++ b/samples/subsys/mgmt/hawkbit/src/main.c @@ -24,7 +24,7 @@ int main(void) { int ret = -1; - LOG_INF("Hawkbit sample app started"); + LOG_INF("hawkBit sample app started"); LOG_INF("Image build time: " __DATE__ " " __TIME__); app_dhcpv4_startup(); @@ -37,16 +37,16 @@ int main(void) ret = hawkbit_init(); if (ret < 0) { - LOG_ERR("Failed to init hawkbit"); + LOG_ERR("Failed to init hawkBit"); } #if defined(CONFIG_HAWKBIT_POLLING) - LOG_INF("Starting hawkbit polling mode"); + LOG_INF("Starting hawkBit polling mode"); hawkbit_autohandler(); #endif #if defined(CONFIG_HAWKBIT_MANUAL) - LOG_INF("Starting hawkbit manual mode"); + LOG_INF("Starting hawkBit manual mode"); switch (hawkbit_probe()) { case HAWKBIT_UNCONFIRMED_IMAGE: @@ -63,7 +63,7 @@ int main(void) break; case HAWKBIT_CANCEL_UPDATE: - LOG_INF("Hawkbit update cancelled from server"); + LOG_INF("hawkBit update cancelled from server"); break; case HAWKBIT_OK: @@ -75,7 +75,7 @@ int main(void) break; case HAWKBIT_PROBE_IN_PROGRESS: - LOG_INF("Hawkbit is already running"); + LOG_INF("hawkBit is already running"); break; default: diff --git a/subsys/mgmt/hawkbit/Kconfig b/subsys/mgmt/hawkbit/Kconfig index c48abdb1f9b..e2365cf3c1d 100644 --- a/subsys/mgmt/hawkbit/Kconfig +++ b/subsys/mgmt/hawkbit/Kconfig @@ -2,7 +2,7 @@ # SPDX -License-Identifier: Apache-2.0 menuconfig HAWKBIT - bool "Hawkbit Firmware Over-the-Air support" + bool "Eclipse hawkBit Firmware Over-the-Air support" depends on NVS depends on FLASH depends on REBOOT @@ -19,7 +19,7 @@ menuconfig HAWKBIT select IMG_ENABLE_IMAGE_CHECK select IMG_ERASE_PROGRESSIVELY help - Hawkbit is a domain independent back-end framework for polling out + hawkBit is a domain independent back-end framework for polling out software updates to constrained edge devices as well as more powerful controllers and gateways connected to IP based networking infrastructure. @@ -33,10 +33,10 @@ config HAWKBIT_POLL_INTERVAL This time interval is zero and 43200 minutes(30 days). config HAWKBIT_SHELL - bool "Hawkbit shell utilities" + bool "hawkBit shell utilities" depends on SHELL help - Activate shell module that provides Hawkbit commands. + Activate shell module that provides hawkBit commands. config HAWKBIT_SERVER string "User address for the hawkbit server" @@ -51,23 +51,23 @@ config HAWKBIT_PORT Configure the hawkbit port number. choice HAWKBIT_DDI_SECURITY - prompt "Hawkbit DDI API authentication modes" + prompt "hawkBit DDI API authentication modes" default HAWKBIT_DDI_NO_SECURITY config HAWKBIT_DDI_NO_SECURITY bool "No authentication security" help - No authentication security for the Hawkbit DDI API. + No authentication security for the hawkBit DDI API. config HAWKBIT_DDI_TARGET_SECURITY bool "Use target security token authentication" help - Use target security token authentication for the Hawkbit DDI API. + Use target security token authentication for the hawkBit DDI API. config HAWKBIT_DDI_GATEWAY_SECURITY bool "Use gateway security token authentication" help - Use gateway security token authentication for the Hawkbit DDI API. + Use gateway security token authentication for the hawkBit DDI API. endchoice @@ -76,12 +76,12 @@ config HAWKBIT_DDI_SECURITY_TOKEN depends on HAWKBIT_DDI_TARGET_SECURITY || HAWKBIT_DDI_GATEWAY_SECURITY default "" help - Authentication security token for the configured Hawkbit DDI + Authentication security token for the configured hawkBit DDI authentication mode. module = HAWKBIT module-str = Log Level for hawkbit -module-help = Enables logging for Hawkbit code. +module-help = Enables logging for hawkBit code. source "subsys/logging/Kconfig.template.log_config" endif diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c index 305f5b47921..26d930c51f9 100644 --- a/subsys/mgmt/hawkbit/hawkbit.c +++ b/subsys/mgmt/hawkbit/hawkbit.c @@ -348,7 +348,7 @@ static int hawkbit_device_acid_update(int32_t new_value) } /* - * Update sleep interval, based on results from hawkbit base polling + * Update sleep interval, based on results from hawkBit base polling * resource */ static void hawkbit_update_sleep(struct hawkbit_ctl_res *hawkbit_res) @@ -513,7 +513,7 @@ static int hawkbit_parse_deployment(struct hawkbit_dep_res *res, int32_t *json_a /* * Find the download-http href. We only support the DEFAULT - * tenant on the same hawkbit server. + * tenant on the same hawkBit server. */ href = artifact->_links.download_http.href; if (!href) { @@ -1004,7 +1004,7 @@ enum hawkbit_response hawkbit_probe(void) } /* - * Query the hawkbit base polling resource. + * Query the hawkBit base polling resource. */ LOG_INF("Polling target data from hawkBit"); diff --git a/subsys/mgmt/hawkbit/hawkbit_priv.h b/subsys/mgmt/hawkbit/hawkbit_priv.h index eb8c7c2fb22..aa1b97524f3 100644 --- a/subsys/mgmt/hawkbit/hawkbit_priv.h +++ b/subsys/mgmt/hawkbit/hawkbit_priv.h @@ -7,7 +7,7 @@ /** @file * * @brief This file contains structures representing JSON messages - * exchanged with a hawkbit + * exchanged with a hawkBit server */ #ifndef __HAWKBIT_PRIV_H__ diff --git a/subsys/mgmt/hawkbit/shell.c b/subsys/mgmt/hawkbit/shell.c index 3128378e9ca..efe2eccbf16 100644 --- a/subsys/mgmt/hawkbit/shell.c +++ b/subsys/mgmt/hawkbit/shell.c @@ -18,7 +18,7 @@ static void cmd_run(const struct shell *sh, size_t argc, char **argv) ARG_UNUSED(argc); ARG_UNUSED(argv); - shell_fprintf(sh, SHELL_INFO, "Starting Hawkbit run...\n"); + shell_fprintf(sh, SHELL_INFO, "Starting hawkBit run...\n"); switch (hawkbit_probe()) { case HAWKBIT_UNCONFIRMED_IMAGE: shell_fprintf( @@ -30,7 +30,7 @@ static void cmd_run(const struct shell *sh, size_t argc, char **argv) case HAWKBIT_CANCEL_UPDATE: shell_fprintf(sh, SHELL_INFO, - "Hawkbit update Cancelled from server\n"); + "hawkBit update Cancelled from server\n"); break; case HAWKBIT_NO_UPDATE: @@ -84,8 +84,8 @@ static int cmd_info(const struct shell *sh, size_t argc, char *argv) SHELL_STATIC_SUBCMD_SET_CREATE( sub_hawkbit, - SHELL_CMD(info, NULL, "Dump Hawkbit information", cmd_info), - SHELL_CMD(run, NULL, "Trigger an Hawkbit update run", cmd_run), + SHELL_CMD(info, NULL, "Dump hawkBit information", cmd_info), + SHELL_CMD(run, NULL, "Trigger an hawkBit update run", cmd_run), SHELL_SUBCMD_SET_END); -SHELL_CMD_REGISTER(hawkbit, &sub_hawkbit, "Hawkbit commands", NULL); +SHELL_CMD_REGISTER(hawkbit, &sub_hawkbit, "hawkBit commands", NULL); From 80b3f15a035ac0fdb17c056c7d07321c5dc5414a Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Thu, 4 Apr 2024 15:11:43 +0800 Subject: [PATCH 1807/2402] samples: mgmt: hawkbit: make references to "frdm_k64f" consistent The "frdm_k64f" is referred as frdm_k64f and ``frdm_k64f`` in places, update them to ":ref:`Freedom-K64F `" or ``frdm_k64f``. Signed-off-by: Yong Cong Sin --- samples/subsys/mgmt/hawkbit/README.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/samples/subsys/mgmt/hawkbit/README.rst b/samples/subsys/mgmt/hawkbit/README.rst index 4f770ca333b..b674b89a815 100644 --- a/samples/subsys/mgmt/hawkbit/README.rst +++ b/samples/subsys/mgmt/hawkbit/README.rst @@ -78,7 +78,7 @@ the server URL, ``:8080``, and logging into the server using Step 4: Build hawkBit ===================== -hawkBit can be built for the frdm_k64f as follows: +hawkBit can be built for the :ref:`Freedom-K64F ` as follows: .. zephyr-app-commands:: :zephyr-app: samples/subsys/mgmt/hawkbit @@ -117,7 +117,7 @@ of your board. Once the image is flashed and booted, the sample will print the image build time to the console. After it connects to the internet, in hawkbit server UI, -you should see the frdm_k64f show up in the Targets pane. It's time to +you should see the ``frdm_k64f`` show up in the Targets pane. It's time to upload a firmware binary to the server, and update it using this UI. Step 7: Building and signing the test image @@ -284,7 +284,7 @@ Step 11: Build hawkBit HTTPS * Convert the server.pem file to self_sign.der and place the der file in hawkbit/src directory -``hawkBit https`` can be built for the frdm_k64f as follows: +``hawkBit https`` can be built for the :ref:`Freedom-K64F ` as follows: .. zephyr-app-commands:: :zephyr-app: samples/subsys/mgmt/hawkbit From fec3cee0bbe63898062869fcf0990d2066ffc61e Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Tue, 2 Apr 2024 08:49:48 +0000 Subject: [PATCH 1808/2402] scripts: set_maintainer: add log messages for skipped collabs Refactor the skip collaborator logic to add log messages when a collaborator is skipped because they self removed of not part of the org. Signed-off-by: Fabio Baltieri --- scripts/set_assignees.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/scripts/set_assignees.py b/scripts/set_assignees.py index 17199ec52e6..d2091931585 100755 --- a/scripts/set_assignees.py +++ b/scripts/set_assignees.py @@ -191,9 +191,15 @@ def process_pr(gh, maintainer_file, number): for collaborator in collab: try: gh_user = gh.get_user(collaborator) - if pr.user != gh_user and gh_repo.has_in_collaborators(gh_user): - if gh_user not in existing_reviewers and gh_user not in self_removal: - reviewers.append(collaborator) + if pr.user == gh_user or gh_user in existing_reviewers: + continue + if not gh_repo.has_in_collaborators(gh_user): + log(f"Skip '{collaborator}': not in collaborators") + continue + if gh_user in self_removal: + log(f"Skip '{collaborator}': self removed") + continue + reviewers.append(collaborator) except UnknownObjectException as e: log(f"Can't get user '{collaborator}', account does not exist anymore? ({e})") From 228d9329675c0c3a6f8890bfb626deb9da873264 Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Wed, 3 Apr 2024 00:36:40 +0900 Subject: [PATCH 1809/2402] posix: implement pthread_setschedprio Implement posix pthread_setschedprio() Signed-off-by: Gaetan Perrot --- include/zephyr/posix/pthread.h | 1 + lib/posix/options/pthread.c | 40 ++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/include/zephyr/posix/pthread.h b/include/zephyr/posix/pthread.h index 7d272fda5e1..2cc05b6df25 100644 --- a/include/zephyr/posix/pthread.h +++ b/include/zephyr/posix/pthread.h @@ -447,6 +447,7 @@ int pthread_attr_setschedparam(pthread_attr_t *attr, const struct sched_param *schedparam); int pthread_setschedparam(pthread_t pthread, int policy, const struct sched_param *param); +int pthread_setschedprio(pthread_t thread, int prio); int pthread_rwlock_destroy(pthread_rwlock_t *rwlock); int pthread_rwlock_init(pthread_rwlock_t *rwlock, const pthread_rwlockattr_t *attr); diff --git a/lib/posix/options/pthread.c b/lib/posix/options/pthread.c index e7fe47fb030..a46cde7614c 100644 --- a/lib/posix/options/pthread.c +++ b/lib/posix/options/pthread.c @@ -869,6 +869,46 @@ int pthread_setschedparam(pthread_t pthread, int policy, const struct sched_para return ret; } +/** + * @brief Set thread scheduling priority. + * + * See IEEE 1003.1 + */ +int pthread_setschedprio(pthread_t thread, int prio) +{ + int ret; + int new_prio = K_LOWEST_APPLICATION_THREAD_PRIO; + struct posix_thread *t = NULL; + int policy; + struct sched_param param; + + ret = pthread_getschedparam(thread, &policy, ¶m); + + if (ret != 0) { + return ret; + } + + if (!is_posix_policy_prio_valid(prio, policy)) { + return EINVAL; + } + + K_SPINLOCK(&pthread_pool_lock) { + t = to_posix_thread(thread); + if (t == NULL) { + ret = ESRCH; + K_SPINLOCK_BREAK; + } + + new_prio = posix_to_zephyr_priority(prio, policy); + } + + if (ret == 0) { + k_thread_priority_set(&t->thread, new_prio); + } + + return ret; +} + /** * @brief Initialise threads attribute object * From 46f489da3a775e7849f6de091e6a0a43ab3bbe87 Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Wed, 3 Apr 2024 00:39:34 +0900 Subject: [PATCH 1810/2402] tests: posix: add tests for pthread_setschedprio() Add tests for pthread_setschedprio() Signed-off-by: Gaetan Perrot --- tests/posix/common/src/pthread.c | 26 ++++++++++++++++++++++++++ tests/posix/headers/src/pthread_h.c | 2 +- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/tests/posix/common/src/pthread.c b/tests/posix/common/src/pthread.c index f3facdf8686..109bcb4e5c8 100644 --- a/tests/posix/common/src/pthread.c +++ b/tests/posix/common/src/pthread.c @@ -539,6 +539,32 @@ ZTEST(pthread, test_pthread_testcancel) zassert_false(testcancel_failed); } +static void *test_pthread_setschedprio_fn(void *arg) +{ + int policy; + int prio = 0; + struct sched_param param; + pthread_t self = pthread_self(); + + zassert_equal(pthread_setschedprio(self, PRIO_INVALID), EINVAL, "EINVAL was expected"); + zassert_equal(pthread_setschedprio(PTHREAD_INVALID, prio), ESRCH, "ESRCH was expected"); + + zassert_ok(pthread_setschedprio(self, prio)); + param.sched_priority = ~prio; + zassert_ok(pthread_getschedparam(self, &policy, ¶m)); + zassert_equal(param.sched_priority, prio, "Priority unchanged"); + + return NULL; +} + +ZTEST(pthread, test_pthread_setschedprio) +{ + pthread_t th; + + zassert_ok(pthread_create(&th, NULL, test_pthread_setschedprio_fn, NULL)); + zassert_ok(pthread_join(th, NULL)); +} + static void before(void *arg) { ARG_UNUSED(arg); diff --git a/tests/posix/headers/src/pthread_h.c b/tests/posix/headers/src/pthread_h.c index 9d5f0336e40..fdf9b66c1ae 100644 --- a/tests/posix/headers/src/pthread_h.c +++ b/tests/posix/headers/src/pthread_h.c @@ -151,7 +151,7 @@ ZTEST(posix_headers, test_pthread_h) zassert_not_null(pthread_setcanceltype); zassert_not_null(pthread_setconcurrency); zassert_not_null(pthread_setschedparam); - /* zassert_not_null(pthread_setschedprio); */ /* not implemented */ + zassert_not_null(pthread_setschedprio); zassert_not_null(pthread_setspecific); zassert_not_null(pthread_spin_destroy); zassert_not_null(pthread_spin_init); From 226f2470064f70d1294a574fc8eca6c6486a096e Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Wed, 3 Apr 2024 14:13:32 +0200 Subject: [PATCH 1811/2402] drivers: net: nsos: fix compatibility with CONFIG_POSIX_API=n Improve code consistency and fix CONFIG_POSIX_API=n compatibility with use of ZSOCK_* and DNS_* macros. Signed-off-by: Marcin Niestroj --- drivers/net/nsos_sockets.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/nsos_sockets.c b/drivers/net/nsos_sockets.c index b70940697a9..98d6c429906 100644 --- a/drivers/net/nsos_sockets.c +++ b/drivers/net/nsos_sockets.c @@ -678,7 +678,7 @@ static int nsos_recvfrom_with_poll(struct nsos_socket *sock, void *buf, size_t l int sock_flags; bool non_blocking; - if (flags & MSG_DONTWAIT) { + if (flags & ZSOCK_MSG_DONTWAIT) { non_blocking = true; } else { sock_flags = nsos_adapt_fcntl_getfl(sock->pollfd.fd); @@ -890,7 +890,7 @@ static int nsos_getaddrinfo(const char *node, const char *service, ret = addrinfo_from_nsos_mid(res_mid, res); if (ret < 0) { errno = -ret; - return EAI_SYSTEM; + return DNS_EAI_SYSTEM; } return ret; From 70e57cdfcb7cc8cfb37d5abb96e2cf27d9ab676b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 2 Apr 2024 15:21:00 +0200 Subject: [PATCH 1812/2402] boards: nucleo_wba55cg: Update image Previous image was for nucleo_wba52cg. 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z80$A}9PMJL+P51N?y(ETyy`5Lt;)|S4wNo9=u#SJeQ$i)74G^53p5VuSYA|1HB}Z;2Mwq(G1ipX1E+pXmia zsPw8c)|z7k8!kDrg*`)dcko4Moz_lE)TP=Q#4_OpsZmb)M`5H&#^?Er2{GDcuD-Tz zSo9+M$6>Y?z1pek#p(bf#))5^ji86qbXmwKHiftPbVQN{2CXZ7XPE-}jsjkzWV;~1 zM;wDCp~W{}KJ&%{rv_51gwzY%bSFelC+rQDM3kB0d{gTcs8zs>b=c&`|Me91|M3rQ ef`OJ)Ta7eQNp$yr_VV*TeR=#3_lNt>pZ^6sK&RyZ From 6cda8b8312727c99ddddbabb0945622b41bc260d Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 2 Apr 2024 15:51:45 +0200 Subject: [PATCH 1813/2402] boards: nucleo_wba55cg: Fix Arduino header D4 stm32wb55cg does not have gpiob13. D4 is mapped on gpioa11. Signed-off-by: Frederic Pillon --- boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi b/boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi index 619cebea62a..2c82c94d31b 100644 --- a/boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi @@ -20,7 +20,7 @@ <7 0 &gpiob 5 0>, /* D1 */ <8 0 &gpiob 7 0>, /* D2 */ <9 0 &gpiob 6 0>, /* D3 */ - <10 0 &gpiob 13 0>, /* D4 */ + <10 0 &gpioa 11 0>, /* D4 */ <11 0 &gpiob 14 0>, /* D5 */ <12 0 &gpiob 0 0>, /* D6 */ <13 0 &gpiob 9 0>, /* D7 */ From 2ef6b98b98a116f34b0b9bed824060244c126c09 Mon Sep 17 00:00:00 2001 From: Dmitrii Golovanov Date: Mon, 1 Apr 2024 22:41:13 +0200 Subject: [PATCH 1814/2402] twister: footprint: Improve command-line arguments Improve Twister command line arguments for memory footprint: * group and order footprint arguments meaningfully, * clearer help descriptions, * resolve logical inconsistences for combinations of arguments, in particular: `--last-metrics` now forces `--enable-size-report`, `--show-footprint` now controls only detailed log output of footprint deltas in comparison modes. * align twister tests accordingly. Signed-off-by: Dmitrii Golovanov --- .../pylib/twister/twisterlib/environment.py | 128 ++++++++++-------- scripts/pylib/twister/twisterlib/reports.py | 22 +-- scripts/tests/twister/test_environment.py | 2 +- .../tests/twister_blackbox/test_footprint.py | 38 ++++-- 4 files changed, 112 insertions(+), 78 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/environment.py b/scripts/pylib/twister/twisterlib/environment.py index 2b99450ee6c..43c05750bf8 100644 --- a/scripts/pylib/twister/twisterlib/environment.py +++ b/scripts/pylib/twister/twisterlib/environment.py @@ -68,8 +68,6 @@ def add_parse_arguments(parser = None): __/fifo_api/testcase.yaml """) - compare_group_option = parser.add_mutually_exclusive_group() - platform_group_option = parser.add_mutually_exclusive_group() run_group_option = parser.add_mutually_exclusive_group() @@ -84,6 +82,10 @@ def add_parse_arguments(parser = None): valgrind_asan_group = parser.add_mutually_exclusive_group() + footprint_group = parser.add_argument_group( + title="Memory footprint", + description="Collect and report ROM/RAM size footprint for the test instance images built.") + case_select.add_argument( "-E", "--save-tests", @@ -124,14 +126,6 @@ def add_parse_arguments(parser = None): case_select.add_argument("--test-tree", action="store_true", help="""Output the test plan in a tree form""") - compare_group_option.add_argument("--compare-report", - help="Use this report file for size comparison") - - compare_group_option.add_argument( - "-m", "--last-metrics", action="store_true", - help="Compare with the results of the previous twister " - "invocation") - platform_group_option.add_argument( "-G", "--integration", @@ -332,20 +326,10 @@ def add_parse_arguments(parser = None): help="Test level to be used. By default, no levels are used for filtering" "and do the selection based on existing filters.") - parser.add_argument( - "-D", "--all-deltas", action="store_true", - help="Show all footprint deltas, positive or negative. Implies " - "--footprint-threshold=0") - parser.add_argument( "--device-serial-baud", action="store", default=None, help="Serial device baud rate (default 115200)") - parser.add_argument( - "--disable-unrecognized-section-test", action="store_true", - default=False, - help="Skip the 'unrecognized section' test.") - parser.add_argument( "--disable-suite-name-check", action="store_true", default=False, help="Disable extended test suite name verification at the beginning " @@ -375,14 +359,6 @@ def add_parse_arguments(parser = None): binaries such as those generated for the native_sim configuration. """) - parser.add_argument("--enable-size-report", action="store_true", - help="Enable expensive computation of RAM/ROM segment sizes.") - - parser.add_argument("--create-rom-ram-report", action="store_true", - help="Generate detailed ram/rom json reports for " - "each build, via cmake build calls with the " - "`--target footprint` argument") - parser.add_argument( "--filter", choices=['buildable', 'runnable'], default='buildable', @@ -403,12 +379,73 @@ def add_parse_arguments(parser = None): help="Path to the gcov tool to use for code coverage " "reports") + footprint_group.add_argument( + "--create-rom-ram-report", + action="store_true", + help="Generate detailed json reports with ROM/RAM symbol sizes for each test image built " + "using additional build option `--target footprint`.") + + footprint_group.add_argument( + "--enable-size-report", + action="store_true", + help="Collect and report ROM/RAM section sizes for each test image built.") + parser.add_argument( - "-H", "--footprint-threshold", type=float, default=5, - help="When checking test case footprint sizes, warn the user if " - "the new app size is greater then the specified percentage " - "from the last release. Default is 5. 0 to warn on any " - "increase on app size.") + "--disable-unrecognized-section-test", + action="store_true", + default=False, + help="Don't error on unrecognized sections in the binary images.") + + footprint_group.add_argument( + "--footprint-from-buildlog", + action = "store_true", + help="Take ROM/RAM sections footprint summary values from the 'build.log' " + "instead of 'objdump' results used otherwise." + "Requires --enable-size-report or one of the baseline comparison modes.") + + compare_group_option = footprint_group.add_mutually_exclusive_group() + + compare_group_option.add_argument( + "-m", "--last-metrics", + action="store_true", + help="Compare footprints to the previous twister invocation as a baseline " + "running in the same output directory. " + "Implies --enable-size-report option.") + + compare_group_option.add_argument( + "--compare-report", + help="Use this report file as a baseline for footprint comparison. " + "The file should be of 'twister.json' schema. " + "Implies --enable-size-report option.") + + footprint_group.add_argument( + "--show-footprint", + action="store_true", + help="With footprint comparison to a baseline, log ROM/RAM section deltas. ") + + footprint_group.add_argument( + "-H", "--footprint-threshold", + type=float, + default=5.0, + help="With footprint comparison to a baseline, " + "warn the user for any of the footprint metric change which is greater or equal " + "to the specified percentage value. " + "Default is %(default)s for %(default)s%% delta from the new footprint value. " + "Use zero to warn on any footprint metric increase.") + + footprint_group.add_argument( + "-D", "--all-deltas", + action="store_true", + help="With footprint comparison to a baseline, " + "warn on any footprint change, increase or decrease. " + "Implies --footprint-threshold=0") + + footprint_group.add_argument( + "-z", "--size", + action="append", + metavar='FILENAME', + help="Ignore all other command line options and just produce a report to " + "stdout with ROM/RAM section sizes on the specified binary images.") parser.add_argument( "-i", "--inline-logs", action="store_true", @@ -608,13 +645,6 @@ def add_parse_arguments(parser = None): "example on Windows OS. This option can be used only with " "'--ninja' argument (to use Ninja build generator).") - parser.add_argument( - "--show-footprint", - action="store_true", - required = "--footprint-from-buildlog" in sys.argv, - help="Show footprint statistics and deltas since last release." - ) - parser.add_argument( "-t", "--tag", action="append", help="Specify tags to restrict which tests to run by tag value. " @@ -695,18 +725,6 @@ def add_parse_arguments(parser = None): directory (testplan.json). """) - parser.add_argument( - "-z", "--size", action="append", - help="Don't run twister. Instead, produce a report to " - "stdout detailing RAM/ROM sizes on the specified filenames. " - "All other command line arguments ignored.") - - parser.add_argument( - "--footprint-from-buildlog", - action = "store_true", - help="Get information about memory footprint from generated build.log. " - "Requires using --show-footprint option.") - parser.add_argument("extra_test_args", nargs=argparse.REMAINDER, help="Additional args following a '--' are passed to the test binary") @@ -755,7 +773,7 @@ def parse_arguments(parser, args, options = None): options.testsuite_root = [os.path.join(ZEPHYR_BASE, "tests"), os.path.join(ZEPHYR_BASE, "samples")] - if options.show_footprint or options.compare_report: + if options.last_metrics or options.compare_report: options.enable_size_report = True if options.aggressive_no_clean: @@ -811,6 +829,10 @@ def parse_arguments(parser, args, options = None): sc.size_report() sys.exit(0) + if options.footprint_from_buildlog and not options.enable_size_report: + logger.error("--footprint-from-buildlog requires --enable-size-report") + sys.exit(1) + if len(options.extra_test_args) > 0: # extra_test_args is a list of CLI args that Twister did not recognize # and are intended to be passed through to the ztest executable. This diff --git a/scripts/pylib/twister/twisterlib/reports.py b/scripts/pylib/twister/twisterlib/reports.py index 001ee7d5092..e03d754ee8c 100644 --- a/scripts/pylib/twister/twisterlib/reports.py +++ b/scripts/pylib/twister/twisterlib/reports.py @@ -404,7 +404,7 @@ def footprint_reports(self, report, show_footprint, all_deltas, logger.debug("running footprint_reports") deltas = self.compare_metrics(report) warnings = 0 - if deltas and show_footprint: + if deltas: for i, metric, value, delta, lower_better in deltas: if not all_deltas and ((delta < 0 and lower_better) or (delta > 0 and not lower_better)): @@ -417,15 +417,19 @@ def footprint_reports(self, report, show_footprint, all_deltas, if not all_deltas and (percentage < (footprint_threshold / 100.0)): continue - logger.info("{:<25} {:<60} {}{}{}: {} {:<+4}, is now {:6} {:+.2%}".format( - i.platform.name, i.testsuite.name, Fore.YELLOW, - "INFO" if all_deltas else "WARNING", Fore.RESET, - metric, delta, value, percentage)) + if show_footprint: + logger.log( + logging.INFO if all_deltas else logging.WARNING, + "{:<25} {:<60} {} {:<+4}, is now {:6} {:+.2%}".format( + i.platform.name, i.testsuite.name, + metric, delta, value, percentage)) + warnings += 1 if warnings: - logger.warning("Deltas based on metrics from last %s" % - ("release" if not last_metrics else "run")) + logger.warning("Found {} footprint deltas to {} as a baseline.".format( + warnings, + (report if not last_metrics else "the last twister run."))) def synopsis(self): cnt = 0 @@ -456,13 +460,13 @@ def synopsis(self): f"{example_instance.testsuite.source_dir_rel} -T {example_instance.testsuite.id}") logger.info("-+" * 40) - def summary(self, results, unrecognized_sections, duration): + def summary(self, results, ignore_unrecognized_sections, duration): failed = 0 run = 0 for instance in self.instances.values(): if instance.status == "failed": failed += 1 - elif instance.metrics.get("unrecognized") and not unrecognized_sections: + elif not ignore_unrecognized_sections and instance.metrics.get("unrecognized"): logger.error("%sFAILED%s: %s has unrecognized binary sections: %s" % (Fore.RED, Fore.RESET, instance.name, str(instance.metrics.get("unrecognized", [])))) diff --git a/scripts/tests/twister/test_environment.py b/scripts/tests/twister/test_environment.py index 4623fad0bc4..d30f7fdad00 100644 --- a/scripts/tests/twister/test_environment.py +++ b/scripts/tests/twister/test_environment.py @@ -225,7 +225,7 @@ def test_parse_arguments_warnings(caplog): TESTDATA_2 = [ - (['--show-footprint']), + (['--enable-size-report']), (['--compare-report', 'dummy']), ] diff --git a/scripts/tests/twister_blackbox/test_footprint.py b/scripts/tests/twister_blackbox/test_footprint.py index 67aee1ea448..d3a3bea1f4b 100644 --- a/scripts/tests/twister_blackbox/test_footprint.py +++ b/scripts/tests/twister_blackbox/test_footprint.py @@ -12,6 +12,7 @@ import os import pytest import sys +import re from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock, clear_log_in_test from twisterlib.testplan import TestPlan @@ -24,11 +25,14 @@ class TestFootprint: # These warnings notify us that deltas were shown in log. # Coupled with the code under test. - DELTA_WARNING_RELEASE = 'Deltas based on metrics from last release' - DELTA_WARNING_RUN = 'Deltas based on metrics from last run' + DELTA_WARNING_COMPARE = re.compile( + r'Found [1-9]+[0-9]* footprint deltas to .*blackbox-out\.[0-9]+/twister.json as a baseline' + ) + DELTA_WARNING_RUN = re.compile(r'Found [1-9]+[0-9]* footprint deltas to the last twister run') # Size report key we modify to control for deltas RAM_KEY = 'used_ram' + DELTA_DETAIL = re.compile(RAM_KEY + r' \+[0-9]+, is now +[0-9]+ \+[0-9.]+%') @classmethod def setup_class(cls): @@ -103,11 +107,11 @@ def test_compare_report(self, caplog, out_path, old_ram_multiplier, expect_delta if expect_delta_log: assert self.RAM_KEY in caplog.text - assert self.DELTA_WARNING_RELEASE in caplog.text, \ + assert re.search(self.DELTA_WARNING_COMPARE, caplog.text), \ 'Expected footprint deltas not logged.' else: assert self.RAM_KEY not in caplog.text - assert self.DELTA_WARNING_RELEASE not in caplog.text, \ + assert not re.search(self.DELTA_WARNING_COMPARE, caplog.text), \ 'Unexpected footprint deltas logged.' def test_footprint_from_buildlog(self, out_path): @@ -116,7 +120,7 @@ def test_footprint_from_buildlog(self, out_path): path = os.path.join(TEST_DATA, 'tests', 'dummy', 'device', 'group') args = ['-i', '--outdir', out_path, '-T', path] + \ [] + \ - ['--show-footprint'] + \ + ['--enable-size-report'] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms ) for val in pair] @@ -141,7 +145,7 @@ def test_footprint_from_buildlog(self, out_path): path = os.path.join(TEST_DATA, 'tests', 'dummy', 'device', 'group') args = ['-i', '--outdir', out_path, '-T', path] + \ ['--footprint-from-buildlog'] + \ - ['--show-footprint'] + \ + ['--enable-size-report'] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms ) for val in pair] @@ -229,11 +233,11 @@ def test_footprint_threshold(self, caplog, out_path, old_ram_multiplier, if expect_delta_log: assert self.RAM_KEY in caplog.text - assert self.DELTA_WARNING_RELEASE in caplog.text, \ + assert re.search(self.DELTA_WARNING_COMPARE, caplog.text), \ 'Expected footprint deltas not logged.' else: assert self.RAM_KEY not in caplog.text - assert self.DELTA_WARNING_RELEASE not in caplog.text, \ + assert not re.search(self.DELTA_WARNING_COMPARE, caplog.text), \ 'Unexpected footprint deltas logged.' @pytest.mark.parametrize( @@ -298,12 +302,16 @@ def test_show_footprint(self, caplog, out_path, flags, old_ram_multiplier, expec if expect_delta_log: assert self.RAM_KEY in caplog.text - assert self.DELTA_WARNING_RELEASE in caplog.text, \ + assert re.search(self.DELTA_DETAIL, caplog.text), \ + 'Expected footprint delta not logged.' + assert re.search(self.DELTA_WARNING_COMPARE, caplog.text), \ 'Expected footprint deltas not logged.' else: assert self.RAM_KEY not in caplog.text - assert self.DELTA_WARNING_RELEASE not in caplog.text, \ - 'Unexpected footprint deltas logged.' + assert not re.search(self.DELTA_DETAIL, caplog.text), \ + 'Expected footprint delta not logged.' + assert re.search(self.DELTA_WARNING_COMPARE, caplog.text), \ + 'Expected footprint deltas logged.' @pytest.mark.parametrize( 'old_ram_multiplier, expect_delta_log', @@ -367,11 +375,11 @@ def test_last_metrics(self, caplog, out_path, old_ram_multiplier, expect_delta_l if expect_delta_log: assert self.RAM_KEY in caplog.text - assert self.DELTA_WARNING_RUN in caplog.text, \ + assert re.search(self.DELTA_WARNING_RUN, caplog.text), \ 'Expected footprint deltas not logged.' else: assert self.RAM_KEY not in caplog.text - assert self.DELTA_WARNING_RUN not in caplog.text, \ + assert not re.search(self.DELTA_WARNING_RUN, caplog.text), \ 'Unexpected footprint deltas logged.' second_logs = caplog.records @@ -464,9 +472,9 @@ def test_all_deltas(self, caplog, out_path, old_ram_multiplier, expect_delta_log if expect_delta_log: assert self.RAM_KEY in caplog.text - assert self.DELTA_WARNING_RELEASE in caplog.text, \ + assert re.search(self.DELTA_WARNING_COMPARE, caplog.text), \ 'Expected footprint deltas not logged.' else: assert self.RAM_KEY not in caplog.text - assert self.DELTA_WARNING_RELEASE not in caplog.text, \ + assert not re.search(self.DELTA_WARNING_COMPARE, caplog.text), \ 'Unexpected footprint deltas logged.' From a8eaa401a6f2c6dce7bbb73d1ff81c2f22399565 Mon Sep 17 00:00:00 2001 From: Dmitrii Golovanov Date: Tue, 2 Apr 2024 01:27:13 +0200 Subject: [PATCH 1815/2402] twister: blackbox: Fix test_output time-sensitive asserts Exclude time-sensitive log entries at `test_output` to avoid false negatives comparing build logs. Signed-off-by: Dmitrii Golovanov --- scripts/tests/twister_blackbox/test_output.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/scripts/tests/twister_blackbox/test_output.py b/scripts/tests/twister_blackbox/test_output.py index 4c5a60e5dec..a97ddf82b33 100644 --- a/scripts/tests/twister_blackbox/test_output.py +++ b/scripts/tests/twister_blackbox/test_output.py @@ -118,12 +118,16 @@ def test_inline_logs(self, out_path): r'-DTC_RUNID=[0-9a-zA-Z]+', # Remove variable order CMake flags r'-I[0-9a-zA-Z/\\]+', + # Remove duration-sensitive entries + r'-- Configuring done \([0-9.]+s\)', + r'-- Generating done \([0-9.]+s\)', # Cache location may vary between CI runs r'^.*-- Cache files will be written to:.*$' ] for pattern in removal_patterns: - inline_twister_log = re.sub(pattern, '', inline_twister_log, flags=re.MULTILINE) - build_log = re.sub(pattern, '', build_log, flags=re.MULTILINE) + c_pattern = re.compile(pattern, flags=re.MULTILINE) + inline_twister_log = re.sub(c_pattern, '', inline_twister_log) + build_log = re.sub(c_pattern, '', build_log) split_build_log = build_log.split('\n') for r in split_build_log: From 300507d43beb6ea0550dfcbce9cba56be1fbe906 Mon Sep 17 00:00:00 2001 From: Dmitrii Golovanov Date: Tue, 2 Apr 2024 11:35:15 +0200 Subject: [PATCH 1816/2402] twister: blackbox: pylint no-name-in-module warnings Ignore no-name-in-module pylint warnings. Signed-off-by: Dmitrii Golovanov --- scripts/tests/twister_blackbox/test_footprint.py | 1 + scripts/tests/twister_blackbox/test_output.py | 1 + 2 files changed, 2 insertions(+) diff --git a/scripts/tests/twister_blackbox/test_footprint.py b/scripts/tests/twister_blackbox/test_footprint.py index d3a3bea1f4b..7eb6ab33e46 100644 --- a/scripts/tests/twister_blackbox/test_footprint.py +++ b/scripts/tests/twister_blackbox/test_footprint.py @@ -14,6 +14,7 @@ import sys import re +# pylint: disable=no-name-in-module from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock, clear_log_in_test from twisterlib.testplan import TestPlan diff --git a/scripts/tests/twister_blackbox/test_output.py b/scripts/tests/twister_blackbox/test_output.py index a97ddf82b33..6e11f03544a 100644 --- a/scripts/tests/twister_blackbox/test_output.py +++ b/scripts/tests/twister_blackbox/test_output.py @@ -14,6 +14,7 @@ import sys import json +# pylint: disable=no-name-in-module from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock, clear_log_in_test from twisterlib.testplan import TestPlan From b8fc1c4c3e0b2bbf0a6403c185a60db104b900a3 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 1 Apr 2024 09:22:57 +0300 Subject: [PATCH 1817/2402] samples: net: Disable native_posix target in samples MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The native_posix compilations fail with various socket errors like this: samples/net/sockets/echo_server/src/udp.c:45:26: error: implicit \ declaration of function ‘socket’ [-Werror=implicit-function-declaration] 45 | data->udp.sock = socket(bind_addr->sa_family, SOCK_DGRAM, | IPPROTO_UDP); Disable the native_posix board from networking samples so that CI can pass. Signed-off-by: Jukka Rissanen --- samples/net/sockets/dumb_http_server/sample.yaml | 4 ++++ samples/net/sockets/echo_server/sample.yaml | 2 ++ samples/net/sockets/net_mgmt/sample.yaml | 3 +++ samples/net/zperf/sample.yaml | 6 ++++++ 4 files changed, 15 insertions(+) diff --git a/samples/net/sockets/dumb_http_server/sample.yaml b/samples/net/sockets/dumb_http_server/sample.yaml index 1751f811693..53fe319293d 100644 --- a/samples/net/sockets/dumb_http_server/sample.yaml +++ b/samples/net/sockets/dumb_http_server/sample.yaml @@ -23,6 +23,8 @@ tests: platform_exclude: - native_sim - native_sim/native/64 + - native_posix + - native_posix/native/64 sample.net.sockets.dumb_http_server.netusb_zeroconf: depends_on: usb_device harness: net @@ -32,3 +34,5 @@ tests: platform_exclude: - native_sim - native_sim/native/64 + - native_posix + - native_posix/native/64 diff --git a/samples/net/sockets/echo_server/sample.yaml b/samples/net/sockets/echo_server/sample.yaml index a127175471f..748df44b5c2 100644 --- a/samples/net/sockets/echo_server/sample.yaml +++ b/samples/net/sockets/echo_server/sample.yaml @@ -90,6 +90,8 @@ tests: platform_exclude: - native_sim - native_sim/native/64 + - native_posix + - native_posix/native/64 sample.net.sockets.echo_server.nrf_openthread: extra_args: OVERLAY_CONFIG="overlay-ot.conf" slow: true diff --git a/samples/net/sockets/net_mgmt/sample.yaml b/samples/net/sockets/net_mgmt/sample.yaml index 337e8d08a75..a9e8dff1b0b 100644 --- a/samples/net/sockets/net_mgmt/sample.yaml +++ b/samples/net/sockets/net_mgmt/sample.yaml @@ -6,6 +6,9 @@ common: - net - socket - mgmt + platform_exclude: + - native_posix + - native_posix/native/64 sample: description: Test network management socket sample name: net_mgmt socket diff --git a/samples/net/zperf/sample.yaml b/samples/net/zperf/sample.yaml index 5fb33f67348..9a2f30016e3 100644 --- a/samples/net/zperf/sample.yaml +++ b/samples/net/zperf/sample.yaml @@ -44,6 +44,8 @@ tests: platform_exclude: - native_sim - native_sim/native/64 + - native_posix + - native_posix/native/64 sample.net.zperf.device_next_ecm: harness: net extra_args: OVERLAY_CONFIG="overlay-usbd_next_ecm.conf" @@ -66,6 +68,8 @@ tests: platform_exclude: - native_sim - native_sim/native/64 + - native_posix + - native_posix/native/64 sample.net.zperf.netusb_rndis: harness: net extra_args: OVERLAY_CONFIG="overlay-netusb.conf" @@ -81,6 +85,8 @@ tests: platform_exclude: - native_sim - native_sim/native/64 + - native_posix + - native_posix/native/64 sample.net.zperf.shield: harness: net platform_allow: reel_board From 33c075d70560a6c1309e5deb41e10769ca75af7d Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 1 Apr 2024 18:15:58 +0300 Subject: [PATCH 1818/2402] samples: net: net_mgmt: Fix build failure on multiple boards The CONFIG_MAX_THREAD_BYTES=3 needs to be set for multiple boards like mr_canhubk3 and xiao_ble when running in usermode. Too many thread objects (18) Increase CONFIG_MAX_THREAD_BYTES to 3 Fixes #70955 Signed-off-by: Jukka Rissanen --- samples/net/sockets/net_mgmt/sample.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/samples/net/sockets/net_mgmt/sample.yaml b/samples/net/sockets/net_mgmt/sample.yaml index a9e8dff1b0b..e2d7a0e0ed9 100644 --- a/samples/net/sockets/net_mgmt/sample.yaml +++ b/samples/net/sockets/net_mgmt/sample.yaml @@ -20,5 +20,6 @@ tests: tags: userspace extra_configs: - CONFIG_USERSPACE=y + - CONFIG_MAX_THREAD_BYTES=3 platform_exclude: - ip_k66f From 9a9f6f3d9665b99864cd94cd25bc1964591efe1e Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 24 Mar 2024 21:03:28 +0200 Subject: [PATCH 1819/2402] net: dummy: Add support for receiving data Add a recv callback to dummy API. After this it is possible to receive data by a dummy network interface. This is only useful if one attaches a virtual interface on top of the dummy one. One such example is the cooked mode capture interface. Signed-off-by: Jukka Rissanen --- include/zephyr/net/dummy.h | 6 ++++++ subsys/net/l2/dummy/dummy.c | 19 +++++++++++-------- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/include/zephyr/net/dummy.h b/include/zephyr/net/dummy.h index 0be84c80191..bcf250a341c 100644 --- a/include/zephyr/net/dummy.h +++ b/include/zephyr/net/dummy.h @@ -32,6 +32,12 @@ struct dummy_api { /** Send a network packet */ int (*send)(const struct device *dev, struct net_pkt *pkt); + /** + * Receive a network packet (only limited use for this, for example + * receiving capturing packets and post processing them). + */ + enum net_verdict (*recv)(struct net_if *iface, struct net_pkt *pkt); + /** Start the device. Called when the bound network interface is brought up. */ int (*start)(const struct device *dev); diff --git a/subsys/net/l2/dummy/dummy.c b/subsys/net/l2/dummy/dummy.c index 0aec98c36c0..37ac492a1a1 100644 --- a/subsys/net/l2/dummy/dummy.c +++ b/subsys/net/l2/dummy/dummy.c @@ -17,14 +17,17 @@ LOG_MODULE_REGISTER(net_l2_dummy, LOG_LEVEL_NONE); static inline enum net_verdict dummy_recv(struct net_if *iface, struct net_pkt *pkt) { - net_pkt_lladdr_src(pkt)->addr = NULL; - net_pkt_lladdr_src(pkt)->len = 0U; - net_pkt_lladdr_src(pkt)->type = NET_LINK_DUMMY; - net_pkt_lladdr_dst(pkt)->addr = NULL; - net_pkt_lladdr_dst(pkt)->len = 0U; - net_pkt_lladdr_dst(pkt)->type = NET_LINK_DUMMY; - - return NET_CONTINUE; + const struct dummy_api *api = net_if_get_device(iface)->api; + + if (api == NULL) { + return NET_DROP; + } + + if (api->recv == NULL) { + return NET_CONTINUE; + } + + return api->recv(iface, pkt); } static inline int dummy_send(struct net_if *iface, struct net_pkt *pkt) From 00502a88946edce4702057b8c08425e9901aa729 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 31 Mar 2024 22:33:31 +0300 Subject: [PATCH 1820/2402] net: Add helper to print the verdict as string For debugging purposes it would be nice to see the verdict printed as a string instead of number. Signed-off-by: Jukka Rissanen --- subsys/net/ip/net_private.h | 1 + subsys/net/ip/utils.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/subsys/net/ip/net_private.h b/subsys/net/ip/net_private.h index a0500f0c862..0cd007595f6 100644 --- a/subsys/net/ip/net_private.h +++ b/subsys/net/ip/net_private.h @@ -203,6 +203,7 @@ int net_ipv6_send_fragmented_pkt(struct net_if *iface, struct net_pkt *pkt, uint16_t pkt_len); #endif +extern const char *net_verdict2str(enum net_verdict verdict); extern const char *net_proto2str(int family, int proto); extern char *net_byte_to_hex(char *ptr, uint8_t byte, char base, bool pad); extern char *net_sprint_ll_addr_buf(const uint8_t *ll, uint8_t ll_len, diff --git a/subsys/net/ip/utils.c b/subsys/net/ip/utils.c index 5b86017ffc2..623bb2b89e2 100644 --- a/subsys/net/ip/utils.c +++ b/subsys/net/ip/utils.c @@ -36,6 +36,19 @@ char *net_sprint_addr(sa_family_t af, const void *addr) return net_addr_ntop(af, addr, s, NET_IPV6_ADDR_LEN); } +const char *net_verdict2str(enum net_verdict verdict) +{ + if (verdict == NET_OK) { + return "NET_OK"; + } else if (verdict == NET_CONTINUE) { + return "NET_CONTINUE"; + } else if (verdict == NET_DROP) { + return "NET_DROP"; + } + + return ""; +} + const char *net_proto2str(int family, int proto) { if (family == AF_INET || family == AF_INET6) { From 3bd43ea86585318c01fce175f104538de240cc04 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 22 Mar 2024 16:19:10 +0200 Subject: [PATCH 1821/2402] net: Implement pseudo a.k.a "any" interface Allow user to create a kitchen sink pseudo a.k.a any network interface that one is only able to write to. This might seem unnecessary, but it is possible to attach virtual network interfaces on top of this pseudo interface. These virtual interfaces could then process the data for example for packet capture purposes. Signed-off-by: Jukka Rissanen --- subsys/net/l2/Kconfig | 4 ++ subsys/net/l2/dummy/CMakeLists.txt | 4 ++ subsys/net/l2/dummy/Kconfig | 4 ++ subsys/net/l2/dummy/any/CMakeLists.txt | 6 ++ subsys/net/l2/dummy/any/Kconfig | 23 +++++++ subsys/net/l2/dummy/any/any.c | 92 ++++++++++++++++++++++++++ 6 files changed, 133 insertions(+) create mode 100644 subsys/net/l2/dummy/Kconfig create mode 100644 subsys/net/l2/dummy/any/CMakeLists.txt create mode 100644 subsys/net/l2/dummy/any/Kconfig create mode 100644 subsys/net/l2/dummy/any/any.c diff --git a/subsys/net/l2/Kconfig b/subsys/net/l2/Kconfig index 9c274a5737a..5ac6349df12 100644 --- a/subsys/net/l2/Kconfig +++ b/subsys/net/l2/Kconfig @@ -10,6 +10,10 @@ config NET_L2_DUMMY Add a dummy L2 layer driver. This is usually only needed when simulating a network interface when running network stack inside QEMU. +if NET_L2_DUMMY +source "subsys/net/l2/dummy/Kconfig" +endif + config NET_L2_BT bool "Bluetooth support" depends on NET_IPV6 diff --git a/subsys/net/l2/dummy/CMakeLists.txt b/subsys/net/l2/dummy/CMakeLists.txt index dd59557cae4..48f5841f9a8 100644 --- a/subsys/net/l2/dummy/CMakeLists.txt +++ b/subsys/net/l2/dummy/CMakeLists.txt @@ -6,3 +6,7 @@ zephyr_library_compile_definitions_ifdef( ) zephyr_library_sources_ifdef(CONFIG_NET_L2_DUMMY dummy.c) + +if(CONFIG_NET_PSEUDO_IFACE) + add_subdirectory(any) +endif() diff --git a/subsys/net/l2/dummy/Kconfig b/subsys/net/l2/dummy/Kconfig new file mode 100644 index 00000000000..c451d2c8d89 --- /dev/null +++ b/subsys/net/l2/dummy/Kconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +source "subsys/net/l2/dummy/any/Kconfig" diff --git a/subsys/net/l2/dummy/any/CMakeLists.txt b/subsys/net/l2/dummy/any/CMakeLists.txt new file mode 100644 index 00000000000..2fe81778873 --- /dev/null +++ b/subsys/net/l2/dummy/any/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_include_directories(. ${ZEPHYR_BASE}/subsys/net/ip) + +zephyr_library_sources_ifdef(CONFIG_NET_PSEUDO_IFACE any.c) diff --git a/subsys/net/l2/dummy/any/Kconfig b/subsys/net/l2/dummy/any/Kconfig new file mode 100644 index 00000000000..b93c066fab0 --- /dev/null +++ b/subsys/net/l2/dummy/any/Kconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +menuconfig NET_PSEUDO_IFACE + bool "Pseudo network interface a.k.a any interface" + depends on NET_L2_DUMMY + select NET_L2_VIRTUAL + help + This implements a pseudo network interface that does nothing + itself. It can be used for example to hook virtual interfaces + on top of it that can act as a network packet capture handlers. + The option will create an "any" network interface which acts + as a packet sink. + +if NET_PSEUDO_IFACE + +module = NET_PSEUDO_IFACE +module-dep = NET_LOG +module-str = Log level for pseudo network interface +module-help = Enables pseudo interface to output debug messages. +source "subsys/net/Kconfig.template.log_config.net" + +endif # NET_PSEUDO_IFACE diff --git a/subsys/net/l2/dummy/any/any.c b/subsys/net/l2/dummy/any/any.c new file mode 100644 index 00000000000..33662573e50 --- /dev/null +++ b/subsys/net/l2/dummy/any/any.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +LOG_MODULE_REGISTER(net_any, CONFIG_NET_PSEUDO_IFACE_LOG_LEVEL); + +#include +#include +#include +#include + +#include "net_private.h" +#include "net_stats.h" + +struct any_context { + struct net_if *iface; +}; + +static struct any_context any_data; + +static void any_iface_init(struct net_if *iface) +{ + struct any_context *ctx = net_if_get_device(iface)->data; + int ret; + + ctx->iface = iface; + + ret = net_if_set_name(iface, "any"); + if (ret < 0) { + NET_DBG("Cannot set any interface name (%d)", ret); + } + + net_if_flag_set(iface, NET_IF_NO_AUTO_START); + net_if_flag_clear(iface, NET_IF_IPV6); + net_if_flag_clear(iface, NET_IF_IPV4); +} + +static enum net_verdict any_recv(struct net_if *iface, struct net_pkt *pkt) +{ + enum net_verdict verdict = NET_DROP; + struct virtual_interface_context *ctx; + sys_snode_t *first; + + if (!pkt->buffer) { + goto drop; + } + + first = sys_slist_peek_head(&iface->config.virtual_interfaces); + if (first == NULL) { + goto drop; + } + + ctx = CONTAINER_OF(first, struct virtual_interface_context, node); + if (ctx == NULL) { + goto drop; + } + + if (net_if_l2(ctx->virtual_iface)->recv == NULL) { + goto drop; + } + + NET_DBG("Passing pkt %p (len %zd) to virtual L2", + pkt, net_pkt_get_len(pkt)); + + verdict = net_if_l2(ctx->virtual_iface)->recv(iface, pkt); + + NET_DBG("Verdict for pkt %p is %s (%d)", pkt, net_verdict2str(verdict), + verdict); + +drop: + return verdict; +} + +static struct dummy_api any_api = { + .iface_api.init = any_iface_init, + .recv = any_recv, +}; + +NET_DEVICE_INIT(any, + "NET_ANY", + NULL, + NULL, + &any_data, + NULL, + CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, + &any_api, + DUMMY_L2, + NET_L2_GET_CTX_TYPE(DUMMY_L2), + 1024); From e52b7081787dc18917bfb959b20b4cb38e81db93 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sat, 23 Mar 2024 17:38:13 +0200 Subject: [PATCH 1822/2402] net: ethernet: Add more protocol types Add ETH_P_CAN, ETH_P_CANFD and ETH_P_HDLC protocol types so that they can be used in following commits. Signed-off-by: Jukka Rissanen --- include/zephyr/net/ethernet.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/zephyr/net/ethernet.h b/include/zephyr/net/ethernet.h index 8fc6881eed1..e39fa7d170e 100644 --- a/include/zephyr/net/ethernet.h +++ b/include/zephyr/net/ethernet.h @@ -59,6 +59,9 @@ struct net_eth_addr { #define NET_ETH_HDR(pkt) ((struct net_eth_hdr *)net_pkt_data(pkt)) +#define NET_ETH_PTYPE_CAN 0x000C /* CAN: Controller Area Network */ +#define NET_ETH_PTYPE_CANFD 0x000D /* CANFD: CAN flexible data rate*/ +#define NET_ETH_PTYPE_HDLC 0x0019 /* HDLC frames (like in PPP) */ #define NET_ETH_PTYPE_ARP 0x0806 #define NET_ETH_PTYPE_IP 0x0800 #define NET_ETH_PTYPE_TSN 0x22f0 /* TSN (IEEE 1722) packet */ @@ -95,6 +98,15 @@ struct net_eth_addr { #if !defined(ETH_P_IEEE802154) #define ETH_P_IEEE802154 NET_ETH_PTYPE_IEEE802154 #endif +#if !defined(ETH_P_CAN) +#define ETH_P_CAN NET_ETH_PTYPE_CAN +#endif +#if !defined(ETH_P_CANFD) +#define ETH_P_CANFD NET_ETH_PTYPE_CANFD +#endif +#if !defined(ETH_P_HDLC) +#define ETH_P_HDLC NET_ETH_PTYPE_HDLC +#endif #define NET_ETH_MINIMAL_FRAME_SIZE 60 #define NET_ETH_MTU 1500 From b8f794237756890670084fa69ed12e91c4cfc409 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sat, 30 Mar 2024 14:18:36 +0200 Subject: [PATCH 1823/2402] posix: net: Add ARP header types to if_arp.h Add various ARP types needed in packet capture support. Signed-off-by: Jukka Rissanen --- include/zephyr/posix/net/if_arp.h | 86 +++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 include/zephyr/posix/net/if_arp.h diff --git a/include/zephyr/posix/net/if_arp.h b/include/zephyr/posix/net/if_arp.h new file mode 100644 index 00000000000..683fcc2e138 --- /dev/null +++ b/include/zephyr/posix/net/if_arp.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_POSIX_NET_IF_ARP_H_ +#define ZEPHYR_INCLUDE_POSIX_NET_IF_ARP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* See https://www.iana.org/assignments/arp-parameters/arp-parameters.xhtml + * for the ARP hardware address type values. + */ +/* ARP protocol HARDWARE identifiers. */ +#define ARPHRD_NETROM 0 /* From KA9Q: NET/ROM pseudo. */ +#define ARPHRD_ETHER 1 /* Ethernet 10/100Mbps. */ +#define ARPHRD_EETHER 2 /* Experimental Ethernet. */ +#define ARPHRD_AX25 3 /* AX.25 Level 2. */ +#define ARPHRD_PRONET 4 /* PROnet token ring. */ +#define ARPHRD_CHAOS 5 /* Chaosnet. */ +#define ARPHRD_IEEE802 6 /* IEEE 802.2 Ethernet/TR/TB. */ +#define ARPHRD_ARCNET 7 /* ARCnet. */ +#define ARPHRD_APPLETLK 8 /* APPLEtalk. */ +#define ARPHRD_DLCI 15 /* Frame Relay DLCI. */ +#define ARPHRD_ATM 19 /* ATM. */ +#define ARPHRD_METRICOM 23 /* Metricom STRIP (new IANA id). */ +#define ARPHRD_IEEE1394 24 /* IEEE 1394 IPv4 - RFC 2734. */ +#define ARPHRD_EUI64 27 /* EUI-64. */ +#define ARPHRD_INFINIBAND 32 /* InfiniBand. */ + +/* Dummy types for non ARP hardware */ +#define ARPHRD_SLIP 256 +#define ARPHRD_CSLIP 257 +#define ARPHRD_SLIP6 258 +#define ARPHRD_CSLIP6 259 +#define ARPHRD_RSRVD 260 /* Notional KISS type. */ +#define ARPHRD_ADAPT 264 +#define ARPHRD_ROSE 270 +#define ARPHRD_X25 271 /* CCITT X.25. */ +#define ARPHRD_HWX25 272 /* Boards with X.25 in firmware. */ +#define ARPHRD_CAN 280 /* Controller Area Network. */ +#define ARPHRD_MCTP 290 +#define ARPHRD_PPP 512 +#define ARPHRD_CISCO 513 /* Cisco HDLC. */ +#define ARPHRD_HDLC ARPHRD_CISCO +#define ARPHRD_LAPB 516 /* LAPB. */ +#define ARPHRD_DDCMP 517 /* Digital's DDCMP. */ +#define ARPHRD_RAWHDLC 518 /* Raw HDLC. */ +#define ARPHRD_RAWIP 519 /* Raw IP. */ +#define ARPHRD_TUNNEL 768 /* IPIP tunnel. */ +#define ARPHRD_TUNNEL6 769 /* IPIP6 tunnel. */ +#define ARPHRD_FRAD 770 /* Frame Relay Access Device. */ +#define ARPHRD_SKIP 771 /* SKIP vif. */ +#define ARPHRD_LOOPBACK 772 /* Loopback device. */ +#define ARPHRD_LOCALTLK 773 /* Localtalk device. */ +#define ARPHRD_FDDI 774 /* Fiber Distributed Data Interface. */ +#define ARPHRD_BIF 775 /* AP1000 BIF. */ +#define ARPHRD_SIT 776 /* sit0 device - IPv6-in-IPv4. */ +#define ARPHRD_IPDDP 777 /* IP-in-DDP tunnel. */ +#define ARPHRD_IPGRE 778 /* GRE over IP. */ +#define ARPHRD_PIMREG 779 /* PIMSM register interface. */ +#define ARPHRD_HIPPI 780 /* High Performance Parallel I'face. */ +#define ARPHRD_ASH 781 /* (Nexus Electronics) Ash. */ +#define ARPHRD_ECONET 782 /* Acorn Econet. */ +#define ARPHRD_IRDA 783 /* Linux-IrDA. */ +#define ARPHRD_FCPP 784 /* Point to point fibrechanel. */ +#define ARPHRD_FCAL 785 /* Fibrechanel arbitrated loop. */ +#define ARPHRD_FCPL 786 /* Fibrechanel public loop. */ +#define ARPHRD_FCFABRIC 787 /* Fibrechanel fabric. */ +#define ARPHRD_IEEE802_TR 800 /* Magic type ident for TR. */ +#define ARPHRD_IEEE80211 801 /* IEEE 802.11. */ +#define ARPHRD_IEEE80211_PRISM 802 /* IEEE 802.11 + Prism2 header. */ +#define ARPHRD_IEEE80211_RADIOTAP 803 /* IEEE 802.11 + radiotap header. */ +#define ARPHRD_IEEE802154 804 /* IEEE 802.15.4 header. */ +#define ARPHRD_IEEE802154_PHY 805 /* IEEE 802.15.4 PHY header. */ + +#define ARPHRD_VOID 0xFFFF /* Void type, nothing is known. */ +#define ARPHRD_NONE 0xFFFE /* Zero header length. */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_POSIX_NET_IF_ARP_H_ */ From 46cb5c0bd101e0677f96328e2d134a7104859231 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 22 Mar 2024 17:22:49 +0200 Subject: [PATCH 1824/2402] net: capture: Add Linux cooked mode capture support Add support for capturing arbitrary data via the cooked mode (sll) capture API. The actual packet capture is done using net_capture_data() function, the packet capture infrastructure does not need any changes. Signed-off-by: Jukka Rissanen --- include/zephyr/net/capture.h | 84 +++++ include/zephyr/net/net_pkt.h | 30 ++ include/zephyr/net/virtual.h | 9 + include/zephyr/net/virtual_mgmt.h | 15 + subsys/net/l2/virtual/virtual_mgmt.c | 24 ++ subsys/net/lib/capture/CMakeLists.txt | 6 +- subsys/net/lib/capture/Kconfig | 48 +++ subsys/net/lib/capture/capture.c | 31 +- subsys/net/lib/capture/cooked.c | 460 ++++++++++++++++++++++++++ subsys/net/lib/capture/sll.h | 47 +++ 10 files changed, 745 insertions(+), 9 deletions(-) create mode 100644 subsys/net/lib/capture/cooked.c create mode 100644 subsys/net/lib/capture/sll.h diff --git a/include/zephyr/net/capture.h b/include/zephyr/net/capture.h index ac8ccdb905d..476f7b67292 100644 --- a/include/zephyr/net/capture.h +++ b/include/zephyr/net/capture.h @@ -211,6 +211,90 @@ static inline void net_capture_pkt(struct net_if *iface, struct net_pkt *pkt) } #endif +/** The type and direction of the captured data. */ +enum net_capture_packet_type { + NET_CAPTURE_HOST, /**< Packet was sent to us by somebody else */ + NET_CAPTURE_BROADCAST, /**< Packet was broadcast by somebody else */ + NET_CAPTURE_MULTICAST, /**< Packet was multicast, but not broadcast, by somebody else */ + NET_CAPTURE_OTHERHOST, /**< Packet was sent by somebody else to somebody else */ + NET_CAPTURE_OUTGOING, /**< Packet was sent by us */ +}; + +#define NET_CAPTURE_LL_ADDRLEN 8 /** Maximum length of a link-layer address */ + +/** The context information for cooked mode capture */ +struct net_capture_cooked { + /** Link-layer address type */ + uint16_t hatype; + /** Link-layer address length */ + uint16_t halen; + /** Link-layer address */ + uint8_t addr[NET_CAPTURE_LL_ADDRLEN]; +}; + +/** + * @brief Initialize cooked mode capture context. + * + * @param cooked Cooked context struct allocated by user. + * @param hatype Link-layer address type + * @param halen Link-layer address length (maximum is 8 bytes) + * @param addr Link-layer address + * + * @return 0 if ok, <0 if context initialization failed + */ +#if defined(CONFIG_NET_CAPTURE_COOKED_MODE) +int net_capture_cooked_setup(struct net_capture_cooked *ctx, + uint16_t hatype, + uint16_t halen, + uint8_t *addr); +#else +static inline int net_capture_cooked_setup(struct net_capture_cooked *ctx, + uint16_t hatype, + uint16_t halen, + uint8_t *addr) +{ + ARG_UNUSED(ctx); + ARG_UNUSED(hatype); + ARG_UNUSED(halen); + ARG_UNUSED(addr); + + return -ENOTSUP; +} +#endif + +/** + * @brief Capture arbitrary data from source that does not have an interface. + * This can be used if you do not have a network interface that + * you want to capture from. For example low level modem device + * below PPP containing HDLC frames, CANBUS data or Bluetooth packets etc. + * The data given to this function should only contain full link + * layer packets so that packet boundary is not lost. + * + * @param ctx Cooked mode capture context. + * @param buf Data to capture. + * @param len Length of the data. + * @param type The direction and type of the packet (did we sent it etc). + * @param ptype Protocol type id. These are the ETH_P_* types set in ethernet.h + */ +#if defined(CONFIG_NET_CAPTURE_COOKED_MODE) +void net_capture_data(struct net_capture_cooked *ctx, + const uint8_t *data, size_t len, + enum net_capture_packet_type type, + uint16_t ptype); +#else +static inline void net_capture_data(struct net_capture_cooked *ctx, + const uint8_t *data, size_t len, + enum net_capture_packet_type type, + uint16_t ptype) +{ + ARG_UNUSED(ctx); + ARG_UNUSED(data); + ARG_UNUSED(len); + ARG_UNUSED(type); + ARG_UNUSED(ptype); +} +#endif + struct net_capture_info { const struct device *capture_dev; struct net_if *capture_iface; diff --git a/include/zephyr/net/net_pkt.h b/include/zephyr/net/net_pkt.h index 559ac1faea8..7d3015588ac 100644 --- a/include/zephyr/net/net_pkt.h +++ b/include/zephyr/net/net_pkt.h @@ -306,6 +306,11 @@ struct net_pkt { }; #endif /* CONFIG_NET_OFFLOAD */ +#if defined(CONFIG_NET_CAPTURE_COOKED_MODE) + /* Tell the capture api that this is a captured packet */ + uint8_t cooked_mode_pkt : 1; +#endif /* CONFIG_NET_CAPTURE_COOKED_MODE */ + /* @endcond */ }; @@ -892,6 +897,31 @@ static inline void net_pkt_set_priority(struct net_pkt *pkt, pkt->priority = priority; } +#if defined(CONFIG_NET_CAPTURE_COOKED_MODE) +static inline bool net_pkt_is_cooked_mode(struct net_pkt *pkt) +{ + return pkt->cooked_mode_pkt; +} + +static inline void net_pkt_set_cooked_mode(struct net_pkt *pkt, bool value) +{ + pkt->cooked_mode_pkt = value; +} +#else +static inline bool net_pkt_is_cooked_mode(struct net_pkt *pkt) +{ + ARG_UNUSED(pkt); + + return false; +} + +static inline void net_pkt_set_cooked_mode(struct net_pkt *pkt, bool value) +{ + ARG_UNUSED(pkt); + ARG_UNUSED(value); +} +#endif /* CONFIG_NET_CAPTURE_COOKED_MODE */ + #if defined(CONFIG_NET_VLAN) static inline uint16_t net_pkt_vlan_tag(struct net_pkt *pkt) { diff --git a/include/zephyr/net/virtual.h b/include/zephyr/net/virtual.h index 71fbd28c797..d64bab15577 100644 --- a/include/zephyr/net/virtual.h +++ b/include/zephyr/net/virtual.h @@ -54,6 +54,14 @@ enum virtual_interface_caps { enum virtual_interface_config_type { VIRTUAL_INTERFACE_CONFIG_TYPE_PEER_ADDRESS, VIRTUAL_INTERFACE_CONFIG_TYPE_MTU, + VIRTUAL_INTERFACE_CONFIG_TYPE_LINK_TYPE, +}; + +struct virtual_interface_link_types { + int count; + uint16_t type[COND_CODE_1(CONFIG_NET_CAPTURE_COOKED_MODE, + (CONFIG_NET_CAPTURE_COOKED_MODE_MAX_LINK_TYPES), + (1))]; }; struct virtual_interface_config { @@ -62,6 +70,7 @@ struct virtual_interface_config { struct in_addr peer4addr; struct in6_addr peer6addr; int mtu; + struct virtual_interface_link_types link_types; }; }; diff --git a/include/zephyr/net/virtual_mgmt.h b/include/zephyr/net/virtual_mgmt.h index 8dd992bdc08..467a1fef146 100644 --- a/include/zephyr/net/virtual_mgmt.h +++ b/include/zephyr/net/virtual_mgmt.h @@ -43,6 +43,7 @@ struct virtual_interface_req_params { struct in_addr peer4addr; struct in6_addr peer6addr; int mtu; + struct virtual_interface_link_types link_types; }; }; @@ -51,6 +52,8 @@ enum net_request_virtual_interface_cmd { NET_REQUEST_VIRTUAL_INTERFACE_CMD_GET_PEER_ADDR, NET_REQUEST_VIRTUAL_INTERFACE_CMD_SET_MTU, NET_REQUEST_VIRTUAL_INTERFACE_CMD_GET_MTU, + NET_REQUEST_VIRTUAL_INTERFACE_CMD_SET_LINK_TYPE, + NET_REQUEST_VIRTUAL_INTERFACE_CMD_GET_LINK_TYPE, }; #define NET_REQUEST_VIRTUAL_INTERFACE_SET_PEER_ADDRESS \ @@ -65,6 +68,12 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_SET_PEER_ADDRESS); NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_SET_MTU); +#define NET_REQUEST_VIRTUAL_INTERFACE_SET_LINK_TYPE \ + (_NET_VIRTUAL_INTERFACE_BASE | \ + NET_REQUEST_VIRTUAL_INTERFACE_CMD_SET_LINK_TYPE) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_SET_LINK_TYPE); + #define NET_REQUEST_VIRTUAL_INTERFACE_GET_PEER_ADDRESS \ (_NET_VIRTUAL_INTERFACE_BASE | \ NET_REQUEST_VIRTUAL_INTERFACE_CMD_GET_PEER_ADDR) @@ -77,6 +86,12 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_PEER_ADDRESS); NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_MTU); +#define NET_REQUEST_VIRTUAL_INTERFACE_GET_LINK_TYPE \ + (_NET_VIRTUAL_INTERFACE_BASE | \ + NET_REQUEST_VIRTUAL_INTERFACE_CMD_GET_LINK_TYPE) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_LINK_TYPE); + struct net_if; /** @endcond */ diff --git a/subsys/net/l2/virtual/virtual_mgmt.c b/subsys/net/l2/virtual/virtual_mgmt.c index c8339a1fbf0..b0a8d62a04d 100644 --- a/subsys/net/l2/virtual/virtual_mgmt.c +++ b/subsys/net/l2/virtual/virtual_mgmt.c @@ -54,6 +54,13 @@ static int virtual_interface_set_config(uint32_t mgmt_request, config.family = params->family; config.mtu = params->mtu; type = VIRTUAL_INTERFACE_CONFIG_TYPE_MTU; + + } else if (mgmt_request == NET_REQUEST_VIRTUAL_INTERFACE_SET_LINK_TYPE) { + /* We can update the link types even if the interface is up */ + config.family = params->family; + memcpy(&config.link_types, ¶ms->link_types, + sizeof(config.link_types)); + type = VIRTUAL_INTERFACE_CONFIG_TYPE_LINK_TYPE; } else { return -EINVAL; } @@ -67,6 +74,9 @@ NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_SET_PEER_ADDRESS NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_SET_MTU, virtual_interface_set_config); +NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_SET_LINK_TYPE, + virtual_interface_set_config); + static int virtual_interface_get_config(uint32_t mgmt_request, struct net_if *iface, void *data, size_t len) @@ -112,6 +122,17 @@ static int virtual_interface_get_config(uint32_t mgmt_request, } params->mtu = config.mtu; + + } else if (mgmt_request == NET_REQUEST_VIRTUAL_INTERFACE_GET_LINK_TYPE) { + type = VIRTUAL_INTERFACE_CONFIG_TYPE_LINK_TYPE; + + ret = api->get_config(iface, type, &config); + if (ret) { + return ret; + } + + memcpy(¶ms->link_types, &config.link_types, + sizeof(params->link_types)); } else { return -EINVAL; } @@ -124,3 +145,6 @@ NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_PEER_ADDRESS NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_MTU, virtual_interface_get_config); + +NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_LINK_TYPE, + virtual_interface_get_config); diff --git a/subsys/net/lib/capture/CMakeLists.txt b/subsys/net/lib/capture/CMakeLists.txt index ce5483f9ea1..8e13876aa6c 100644 --- a/subsys/net/lib/capture/CMakeLists.txt +++ b/subsys/net/lib/capture/CMakeLists.txt @@ -3,4 +3,8 @@ zephyr_include_directories(.) zephyr_include_directories(${ZEPHYR_BASE}/subsys/net/ip) -zephyr_sources(capture.c) +zephyr_library_sources(capture.c) + +if(CONFIG_NET_CAPTURE_COOKED_MODE) + zephyr_library_sources(cooked.c) +endif() diff --git a/subsys/net/lib/capture/Kconfig b/subsys/net/lib/capture/Kconfig index 5cb8a04bfb4..b2a579b6bc4 100644 --- a/subsys/net/lib/capture/Kconfig +++ b/subsys/net/lib/capture/Kconfig @@ -46,6 +46,54 @@ config NET_CAPTURE_DEVICE_COUNT if one needs to send captured data to multiple different devices, then you need to increase the value. +config NET_CAPTURE_COOKED_MODE + bool "Capture non-IP packets a.k.a cooked (SLL) mode [EXPERIMENTAL]" + select NET_PSEUDO_IFACE + select NET_L2_DUMMY + select NET_L2_VIRTUAL + select EXPERIMENTAL + help + This enables application to capture packets in so called + Linux cooked mode (sll). Here a synthetic link layer header + is used instead of real network link header. + +choice NET_CAPTURE_COOKED_MODE_SLL_VERSION + prompt "SLL version to use" + depends on NET_CAPTURE_COOKED_MODE + default NET_CAPTURE_COOKED_MODE_SLLV1 + help + What SLL header version to use. + +config NET_CAPTURE_COOKED_MODE_SLLV1 + bool "SLL version 1" + depends on NET_CAPTURE_COOKED_MODE + help + Use SLL version 1 (header is 16 bytes) + +config NET_CAPTURE_COOKED_MODE_SLLV2 + bool "SLL version 2" + depends on NET_CAPTURE_COOKED_MODE + help + Use SLL version 2 (header is 20 bytes) + +endchoice + +config NET_CAPTURE_COOKED_MODE_INTERFACE_NAME + string "Name of the cooked mode network interface" + default "cooked" + depends on NET_CAPTURE_COOKED_MODE + help + This sets the name of the cooked mode capture network interface. + +config NET_CAPTURE_COOKED_MODE_MAX_LINK_TYPES + int "How many link types (ETH_P_*) to capture at the same time" + default 2 + range 1 64 + depends on NET_CAPTURE_COOKED_MODE + help + This defines how many ETH_P_* link type values can be captured + at the same time in cooked mode. + module = NET_CAPTURE module-dep = NET_LOG module-str = Log level for network capture API diff --git a/subsys/net/lib/capture/capture.c b/subsys/net/lib/capture/capture.c index fcd7bb06773..c0f5ddd0568 100644 --- a/subsys/net/lib/capture/capture.c +++ b/subsys/net/lib/capture/capture.c @@ -508,6 +508,7 @@ void net_capture_pkt(struct net_if *iface, struct net_pkt *pkt) struct k_mem_slab *orig_slab; struct net_pkt *captured; sys_snode_t *sn, *sns; + bool skip_clone = false; /* We must prevent to capture network packet that is already captured * in order to avoid recursion. @@ -528,17 +529,29 @@ void net_capture_pkt(struct net_if *iface, struct net_pkt *pkt) continue; } - orig_slab = pkt->slab; - pkt->slab = get_net_pkt(); + /* If the packet is marked as "cooked", then it means that the + * packet was directed here by "any" interface and was already + * cooked mode captured. So no need to clone it here. + */ + if (net_pkt_is_cooked_mode(pkt)) { + skip_clone = true; + } - captured = net_pkt_clone(pkt, K_NO_WAIT); + if (skip_clone) { + captured = pkt; + } else { + orig_slab = pkt->slab; + pkt->slab = get_net_pkt(); - pkt->slab = orig_slab; + captured = net_pkt_clone(pkt, K_NO_WAIT); - if (captured == NULL) { - NET_DBG("Captured pkt %s", "dropped"); - /* TODO: update capture data statistics */ - goto out; + pkt->slab = orig_slab; + + if (captured == NULL) { + NET_DBG("Captured pkt %s", "dropped"); + /* TODO: update capture data statistics */ + goto out; + } } net_pkt_set_orig_iface(captured, iface); @@ -550,6 +563,8 @@ void net_capture_pkt(struct net_if *iface, struct net_pkt *pkt) net_pkt_unref(captured); } + net_pkt_set_cooked_mode(pkt, false); + goto out; } diff --git a/subsys/net/lib/capture/cooked.c b/subsys/net/lib/capture/cooked.c new file mode 100644 index 00000000000..1f342569569 --- /dev/null +++ b/subsys/net/lib/capture/cooked.c @@ -0,0 +1,460 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +LOG_MODULE_REGISTER(net_cooked, CONFIG_NET_CAPTURE_LOG_LEVEL); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sll.h" + +#define BUF_ALLOC_TIMEOUT 100 /* ms */ + +/* Use our own slabs for temporary pkts */ +NET_PKT_SLAB_DEFINE(cooked_pkts, CONFIG_NET_CAPTURE_PKT_COUNT); + +#if defined(CONFIG_NET_BUF_FIXED_DATA_SIZE) +NET_BUF_POOL_FIXED_DEFINE(cooked_bufs, CONFIG_NET_CAPTURE_BUF_COUNT, + CONFIG_NET_BUF_DATA_SIZE, 4, NULL); +#else +NET_BUF_POOL_VAR_DEFINE(cooked_bufs, CONFIG_NET_CAPTURE_BUF_COUNT, + CONFIG_NET_BUF_DATA_POOL_SIZE, 4, NULL); +#endif + +#define COOKED_MTU 1024 +#define COOKED_DEVICE "NET_COOKED" + +struct cooked_context { + struct net_if *iface; + struct net_if *attached_to; + + /* -1 is used as a not configured link type */ + int link_types[CONFIG_NET_CAPTURE_COOKED_MODE_MAX_LINK_TYPES]; + int link_type_count; + int mtu; + bool init_done; + bool status; +}; + +static void iface_init(struct net_if *iface) +{ + struct cooked_context *ctx = net_if_get_device(iface)->data; + struct net_if *any_iface; + int ifindex; + int ret; + + ifindex = net_if_get_by_name("any"); + if (ifindex < 0) { + NET_DBG("No such interface \"any\", cannot init interface %d", + net_if_get_by_iface(iface)); + return; + } + + if (net_if_l2(net_if_get_by_index(ifindex)) != &NET_L2_GET_NAME(DUMMY)) { + NET_DBG("The \"any\" interface %d is wrong type", ifindex); + return; + } + + if (ctx->init_done) { + return; + } + + ctx->iface = iface; + any_iface = net_if_get_by_index(ifindex); + + (void)net_if_set_name(iface, + CONFIG_NET_CAPTURE_COOKED_MODE_INTERFACE_NAME); + (void)net_virtual_set_name(iface, "Cooked mode capture"); + + net_if_flag_set(iface, NET_IF_NO_AUTO_START); + net_if_flag_set(iface, NET_IF_POINTOPOINT); + net_if_flag_clear(iface, NET_IF_IPV4); + net_if_flag_clear(iface, NET_IF_IPV6); + + /* Hook into "any" interface so that we can receive the + * captured data. + */ + ret = net_virtual_interface_attach(ctx->iface, any_iface); + if (ret < 0) { + NET_DBG("Cannot hook into interface %d (%d)", + net_if_get_by_iface(any_iface), ret); + return; + } + + NET_DBG("Interface %d attached on top of %d", + net_if_get_by_iface(ctx->iface), + net_if_get_by_iface(any_iface)); + + ctx->init_done = true; +} + +static int dev_init(const struct device *dev) +{ + struct cooked_context *ctx = dev->data; + + memset(ctx->link_types, -1, sizeof(ctx->link_types)); + + return 0; +} + +static int interface_start(const struct device *dev) +{ + struct cooked_context *ctx = dev->data; + int ret = 0; + + if (ctx->status) { + return -EALREADY; + } + + ctx->status = true; + + NET_DBG("Starting iface %d", net_if_get_by_iface(ctx->iface)); + + return ret; +} + +static int interface_stop(const struct device *dev) +{ + struct cooked_context *ctx = dev->data; + + if (!ctx->status) { + return -EALREADY; + } + + ctx->status = false; + + NET_DBG("Stopping iface %d", net_if_get_by_iface(ctx->iface)); + + return 0; +} + +static enum net_verdict interface_recv(struct net_if *iface, struct net_pkt *pkt) +{ + struct cooked_context *ctx = net_if_get_device(iface)->data; + bool found = false; + uint16_t ptype; + + /* Feed the packet to capture system after verifying that we are capturing + * these types of packets. + * The packet will be freed by capture API after it has been processed. + */ + + ptype = net_pkt_ll_proto_type(pkt); + + NET_DBG("Capture pkt %p for interface %d", pkt, net_if_get_by_iface(iface)); + + for (int i = 0; i < ctx->link_type_count; i++) { + if (ctx->link_types[i] == ptype) { + found = true; + break; + } + } + + if (found) { + int ret; + + NET_DBG("Handler found for packet type 0x%04x", ptype); + + /* Normally capture API will clone the net_pkt and we would + * always need to unref it. But for cooked packets, we can avoid + * the cloning so need to unref only if there was an error with + * capturing. + */ + ret = net_capture_pkt_with_status(iface, pkt); + if (ret < 0) { + net_pkt_unref(pkt); + } + + return NET_OK; + } + + NET_DBG("No handler found for packet type 0x%04x", ptype); + + return NET_DROP; +} + +static int interface_attach(struct net_if *iface, struct net_if *lower_iface) +{ + struct cooked_context *ctx; + + if (net_if_get_by_iface(iface) < 0) { + return -ENOENT; + } + + ctx = net_if_get_device(iface)->data; + ctx->attached_to = lower_iface; + + return 0; +} + +static int interface_set_config(struct net_if *iface, + enum virtual_interface_config_type type, + const struct virtual_interface_config *config) +{ + struct cooked_context *ctx = net_if_get_device(iface)->data; + + switch (type) { + case VIRTUAL_INTERFACE_CONFIG_TYPE_LINK_TYPE: + if (config->link_types.count > ARRAY_SIZE(ctx->link_types)) { + return -ERANGE; + } + + for (int i = 0; i < config->link_types.count; i++) { + NET_DBG("Adding link type %u", config->link_types.type[i]); + + ctx->link_types[i] = (int)config->link_types.type[i]; + } + + ctx->link_type_count = config->link_types.count; + + /* Mark the rest of the types as invalid */ + for (int i = ctx->link_type_count; i < ARRAY_SIZE(ctx->link_types); i++) { + ctx->link_types[i] = -1; + } + + return 0; + + case VIRTUAL_INTERFACE_CONFIG_TYPE_MTU: + NET_DBG("Interface %d MTU set to %d", + net_if_get_by_iface(iface), config->mtu); + net_if_set_mtu(iface, config->mtu); + return 0; + + default: + break; + } + + return -ENOTSUP; +} + +static int interface_get_config(struct net_if *iface, + enum virtual_interface_config_type type, + struct virtual_interface_config *config) +{ + struct cooked_context *ctx = net_if_get_device(iface)->data; + int i; + + switch (type) { + case VIRTUAL_INTERFACE_CONFIG_TYPE_LINK_TYPE: + for (i = 0; i < ctx->link_type_count; i++) { + if (ctx->link_types[i] < 0) { + break; + } + + config->link_types.type[i] = (uint16_t)ctx->link_types[i]; + } + + config->link_types.count = i; + NET_ASSERT(config->link_types.count == ctx->link_type_count); + return 0; + + case VIRTUAL_INTERFACE_CONFIG_TYPE_MTU: + config->mtu = net_if_get_mtu(iface); + return 0; + + default: + break; + } + + return -ENOTSUP; +} + +static const struct virtual_interface_api cooked_api = { + .iface_api.init = iface_init, + + .start = interface_start, + .stop = interface_stop, + .recv = interface_recv, + .attach = interface_attach, + .set_config = interface_set_config, + .get_config = interface_get_config, +}; + +static struct cooked_context cooked_context_data; + +NET_VIRTUAL_INTERFACE_INIT(cooked, COOKED_DEVICE, dev_init, + NULL, &cooked_context_data, NULL, + CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, + &cooked_api, COOKED_MTU); + +int net_capture_cooked_setup(struct net_capture_cooked *ctx, + uint16_t hatype, + uint16_t halen, + uint8_t *addr) +{ + if (halen == 0 || halen > NET_CAPTURE_LL_ADDRLEN) { + return -EINVAL; + } + + memset(ctx, 0, sizeof(*ctx)); + + ctx->hatype = hatype; + ctx->halen = halen; + + memcpy(ctx->addr, addr, halen); + + return 0; +} + +static int create_sll_header(struct net_if *iface, + struct net_pkt *pkt, + struct net_capture_cooked *ctx, + enum net_capture_packet_type type, + uint16_t ptype) +{ + struct sll2_header hdr2; + struct sll_header hdr1; + size_t hdr_len; + uint8_t *hdr; + int ret; + + if (IS_ENABLED(CONFIG_NET_CAPTURE_COOKED_MODE_SLLV1)) { + hdr1.sll_pkttype = htons(type); + hdr1.sll_hatype = htons(ctx->hatype); + hdr1.sll_halen = htons(ctx->halen); + memcpy(hdr1.sll_addr, ctx->addr, sizeof(ctx->addr)); + hdr1.sll_protocol = htons(ptype); + + hdr = (uint8_t *)&hdr1; + hdr_len = sizeof(hdr1); + + } else { + hdr2.sll2_protocol = htons(ptype); + hdr2.sll2_reserved_mbz = 0; + hdr2.sll2_if_index = net_if_get_by_iface(iface); + hdr2.sll2_hatype = htons(ctx->hatype); + hdr2.sll2_pkttype = htons(type); + hdr2.sll2_halen = htons(ctx->halen); + memcpy(hdr2.sll2_addr, ctx->addr, sizeof(ctx->addr)); + + hdr = (uint8_t *)&hdr2; + hdr_len = sizeof(hdr2); + } + + ret = net_pkt_write(pkt, hdr, hdr_len); + if (ret < 0) { + NET_DBG("Cannot write sll%s header (%d)", + IS_ENABLED(CONFIG_NET_CAPTURE_COOKED_MODE_SLLV1) ? + "" : "2", ret); + } + + return ret; +} + +static struct k_mem_slab *get_net_pkt(void) +{ + return &cooked_pkts; +} + +static struct net_buf_pool *get_net_buf(void) +{ + return &cooked_bufs; +} + +void net_capture_data(struct net_capture_cooked *ctx, + const uint8_t *data, size_t data_len, + enum net_capture_packet_type type, + uint16_t ptype) +{ + static struct net_context context; + const struct device *dev; + struct net_if *iface; + struct net_pkt *pkt; + int ret; + + net_context_setup_pools(&context, get_net_pkt, get_net_buf); + + pkt = net_pkt_alloc_from_slab(&cooked_pkts, K_MSEC(BUF_ALLOC_TIMEOUT)); + if (pkt == NULL) { + NET_DBG("Cannot allocate %s", "net_pkt"); + return; + } + + net_pkt_set_context(pkt, &context); + + ret = net_pkt_alloc_buffer_raw(pkt, + sizeof(COND_CODE_1(CONFIG_NET_CAPTURE_COOKED_MODE_SLLV1, + (struct sll_header), + (struct sll2_header))) + data_len, + K_MSEC(BUF_ALLOC_TIMEOUT)); + if (ret < 0) { + NET_DBG("Cannot allocate %s %zd bytes (%d)", "net_buf for", + sizeof(struct sll_header) + data_len, ret); + net_pkt_unref(pkt); + return; + } + + /* Write the packet to "any" interface which will pass it to + * the virtual interface that does the actual capturing of the packet. + * The reason for this trickery is that we do not have a network + * interface in use in this API, and want to have the packet routed + * via the any interface which can then deliver it to registered + * virtual interfaces. + */ + dev = device_get_binding(COOKED_DEVICE); + if (dev == NULL) { + NET_DBG("No such device %s found, data not captured!", + COOKED_DEVICE); + net_pkt_unref(pkt); + return; + } + + /* Next we feed the data to the any interface, which + * will pass the data to the virtual interface. + * When using capture API or net-shell capture command, one + * should capture packets from the virtual interface. + */ + iface = ((struct cooked_context *)dev->data)->attached_to; + + ret = create_sll_header(iface, pkt, ctx, type, ptype); + if (ret < 0) { + NET_DBG("Cannot write %s %zd bytes (%d)", "header", + sizeof(struct sll_header), ret); + net_pkt_unref(pkt); + return; + } + + ret = net_pkt_write(pkt, data, data_len); + if (ret < 0) { + NET_DBG("Cannot write %s %zd bytes (%d)", "payload", + data_len, ret); + net_pkt_unref(pkt); + return; + } + + /* Mark that this packet came from cooked capture mode. + * This will prevent the capture API from cloning the packet, + * so that the net_pkt will be passed as is to capture interface. + */ + net_pkt_set_cooked_mode(pkt, true); + + /* The protocol type is used by virtual cooked interface to decide + * whether we capture the packet or not. + */ + net_pkt_set_ll_proto_type(pkt, ptype); + + net_pkt_lladdr_src(pkt)->addr = NULL; + net_pkt_lladdr_src(pkt)->len = 0U; + net_pkt_lladdr_src(pkt)->type = NET_LINK_DUMMY; + net_pkt_lladdr_dst(pkt)->addr = NULL; + net_pkt_lladdr_dst(pkt)->len = 0U; + net_pkt_lladdr_dst(pkt)->type = NET_LINK_DUMMY; + + ret = net_recv_data(iface, pkt); + if (ret < 0) { + net_pkt_unref(pkt); + } +} diff --git a/subsys/net/lib/capture/sll.h b/subsys/net/lib/capture/sll.h new file mode 100644 index 00000000000..15df416218e --- /dev/null +++ b/subsys/net/lib/capture/sll.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Defines for Linux cooked mode capture (SLL) */ + +#include +#include + +/* Useful information about SLL header format can be found here + * https://www.tcpdump.org/linktypes/LINKTYPE_LINUX_SLL.html + */ + +#define SLL_HDR_LEN 16 /* Total header length */ +#define SLL_ADDRLEN 8 /* Length of the address field */ + +struct sll_header { + uint16_t sll_pkttype; /* Packet type */ + uint16_t sll_hatype; /* Link-layer address type */ + uint16_t sll_halen; /* Link-layer address length */ + uint8_t sll_addr[SLL_ADDRLEN]; /* Link-layer address */ + uint16_t sll_protocol; /* Protocol */ +}; + +BUILD_ASSERT(sizeof(struct sll_header) == SLL_HDR_LEN); + +#define SLL2_HDR_LEN 20 /* Total header length */ + +struct sll2_header { + uint16_t sll2_protocol; /* Protocol */ + uint16_t sll2_reserved_mbz; /* Reserved - must be zero */ + uint32_t sll2_if_index; /* 1-based interface index */ + uint16_t sll2_hatype; /* Link-layer address type */ + uint8_t sll2_pkttype; /* Packet type */ + uint8_t sll2_halen; /* Link-layer address length */ + uint8_t sll2_addr[SLL_ADDRLEN]; /* Link-layer address */ +}; + +BUILD_ASSERT(sizeof(struct sll2_header) == SLL2_HDR_LEN); + +#define SLL_HOST 0 /* packet was sent to us by somebody else */ +#define SLL_BROADCAST 1 /* packet was broadcast by somebody else */ +#define SLL_MULTICAST 2 /* packet was multicast, but not broadcast, by somebody else */ +#define SLL_OTHERHOST 3 /* packet was sent by somebody else to somebody else */ +#define SLL_OUTGOING 4 /* packet was sent by us */ From 0516ce9311b9473bbb3d9cb29fe9ea8b7587abe5 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 25 Mar 2024 16:36:43 +0200 Subject: [PATCH 1825/2402] net: capture: Add capture function that returns a status The net_capture_pkt() does not return information what happened to the net_pkt because the packet was always cloned. With cooked capture we can avoid the cloning in which case we need to know the capture status in order to unref the packet if needed. Signed-off-by: Jukka Rissanen --- include/zephyr/net/capture.h | 25 +++++++++++++++++++++++++ subsys/net/lib/capture/capture.c | 18 ++++++++++++++---- 2 files changed, 39 insertions(+), 4 deletions(-) diff --git a/include/zephyr/net/capture.h b/include/zephyr/net/capture.h index 476f7b67292..eb3cd329735 100644 --- a/include/zephyr/net/capture.h +++ b/include/zephyr/net/capture.h @@ -211,6 +211,31 @@ static inline void net_capture_pkt(struct net_if *iface, struct net_pkt *pkt) } #endif +/** @cond INTERNAL_HIDDEN */ + +/** + * @brief Special variant for net_capture_pkt() which returns the status + * of the send message. + * + * @param iface Network interface the packet is being sent + * @param pkt The network packet that is sent + * + * @return 0 if captured packet was handled ok, <0 if the capture failed + */ +#if defined(CONFIG_NET_CAPTURE) +int net_capture_pkt_with_status(struct net_if *iface, struct net_pkt *pkt); +#else +static inline int net_capture_pkt_with_status(struct net_if *iface, struct net_pkt *pkt) +{ + ARG_UNUSED(iface); + ARG_UNUSED(pkt); + + return -ENOTSUP; +} +#endif + +/** @endcond */ + /** The type and direction of the captured data. */ enum net_capture_packet_type { NET_CAPTURE_HOST, /**< Packet was sent to us by somebody else */ diff --git a/subsys/net/lib/capture/capture.c b/subsys/net/lib/capture/capture.c index c0f5ddd0568..d786dca3365 100644 --- a/subsys/net/lib/capture/capture.c +++ b/subsys/net/lib/capture/capture.c @@ -503,18 +503,19 @@ static int capture_disable(const struct device *dev) return 0; } -void net_capture_pkt(struct net_if *iface, struct net_pkt *pkt) +int net_capture_pkt_with_status(struct net_if *iface, struct net_pkt *pkt) { struct k_mem_slab *orig_slab; struct net_pkt *captured; sys_snode_t *sn, *sns; bool skip_clone = false; + int ret = -ENOENT; /* We must prevent to capture network packet that is already captured * in order to avoid recursion. */ if (net_pkt_is_captured(pkt)) { - return; + return -EALREADY; } k_mutex_lock(&lock, K_FOREVER); @@ -522,7 +523,6 @@ void net_capture_pkt(struct net_if *iface, struct net_pkt *pkt) SYS_SLIST_FOR_EACH_NODE_SAFE(&net_capture_devlist, sn, sns) { struct net_capture *ctx = CONTAINER_OF(sn, struct net_capture, node); - int ret; if (!ctx->in_use || !ctx->is_enabled || ctx->capture_iface != iface) { @@ -550,6 +550,7 @@ void net_capture_pkt(struct net_if *iface, struct net_pkt *pkt) if (captured == NULL) { NET_DBG("Captured pkt %s", "dropped"); /* TODO: update capture data statistics */ + ret = -ENOMEM; goto out; } } @@ -560,7 +561,9 @@ void net_capture_pkt(struct net_if *iface, struct net_pkt *pkt) ret = net_capture_send(ctx->dev, ctx->tunnel_iface, captured); if (ret < 0) { - net_pkt_unref(captured); + if (!skip_clone) { + net_pkt_unref(captured); + } } net_pkt_set_cooked_mode(pkt, false); @@ -570,6 +573,13 @@ void net_capture_pkt(struct net_if *iface, struct net_pkt *pkt) out: k_mutex_unlock(&lock); + + return ret; +} + +void net_capture_pkt(struct net_if *iface, struct net_pkt *pkt) +{ + (void)net_capture_pkt_with_status(iface, pkt); } static int capture_dev_init(const struct device *dev) From dca5f481653589289b0e77d3baa8a2b930b525f1 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 31 Mar 2024 15:59:49 +0300 Subject: [PATCH 1826/2402] net: capture: Allow user to check capture status without knowing dev As user might not know the capture device name, allow net_capture_is_enabled() to be called with a NULL device name. Currently it then uses the hardcoded device name, but we could change that in the future so that the function could figure out the correct name itself. Signed-off-by: Jukka Rissanen --- include/zephyr/net/capture.h | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/include/zephyr/net/capture.h b/include/zephyr/net/capture.h index eb3cd329735..0d5a61c4911 100644 --- a/include/zephyr/net/capture.h +++ b/include/zephyr/net/capture.h @@ -14,6 +14,7 @@ #define ZEPHYR_INCLUDE_NET_CAPTURE_H_ #include +#include #ifdef __cplusplus extern "C" { @@ -127,15 +128,25 @@ static inline int net_capture_enable(const struct device *dev, struct net_if *if /** * @brief Is network packet capture enabled or disabled. * - * @param dev Network capture device + * @param dev Network capture device. If set to NULL, then the + * default capture device is used. * * @return True if enabled, False if network capture is disabled. */ static inline bool net_capture_is_enabled(const struct device *dev) { #if defined(CONFIG_NET_CAPTURE) - const struct net_capture_interface_api *api = - (const struct net_capture_interface_api *)dev->api; + const struct net_capture_interface_api *api; + + if (dev == NULL) { + /* TODO: Go through all capture devices instead of one */ + dev = device_get_binding("NET_CAPTURE0"); + if (dev == NULL) { + return false; + } + } + + api = (const struct net_capture_interface_api *)dev->api; return api->is_enabled(dev); #else From 2064306d41cc7313241dd90750c7453f6dd1b437 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 28 Mar 2024 17:08:00 +0200 Subject: [PATCH 1827/2402] net: capture: Generate events when starting / stopping capture The event NET_EVENT_CAPTURE_STARTED is generated when the capture is enabled, and NET_EVENT_CAPTURE_STOPPED when capture is disabled. Signed-off-by: Jukka Rissanen --- include/zephyr/net/net_event.h | 8 ++++++++ subsys/net/lib/capture/capture.c | 5 +++++ subsys/net/lib/shell/events.c | 6 ++++++ 3 files changed, 19 insertions(+) diff --git a/include/zephyr/net/net_event.h b/include/zephyr/net/net_event.h index 6d5abf4177f..881bb8dc276 100644 --- a/include/zephyr/net/net_event.h +++ b/include/zephyr/net/net_event.h @@ -210,6 +210,8 @@ enum net_event_l4_cmd { NET_EVENT_L4_CMD_DNS_SERVER_ADD, NET_EVENT_L4_CMD_DNS_SERVER_DEL, NET_EVENT_L4_CMD_HOSTNAME_CHANGED, + NET_EVENT_L4_CMD_CAPTURE_STARTED, + NET_EVENT_L4_CMD_CAPTURE_STOPPED, }; #define NET_EVENT_L4_CONNECTED \ @@ -227,6 +229,12 @@ enum net_event_l4_cmd { #define NET_EVENT_HOSTNAME_CHANGED \ (_NET_EVENT_L4_BASE | NET_EVENT_L4_CMD_HOSTNAME_CHANGED) +#define NET_EVENT_CAPTURE_STARTED \ + (_NET_EVENT_L4_BASE | NET_EVENT_L4_CMD_CAPTURE_STARTED) + +#define NET_EVENT_CAPTURE_STOPPED \ + (_NET_EVENT_L4_BASE | NET_EVENT_L4_CMD_CAPTURE_STOPPED) + /** @endcond */ /** diff --git a/subsys/net/lib/capture/capture.c b/subsys/net/lib/capture/capture.c index d786dca3365..f945a05e7f1 100644 --- a/subsys/net/lib/capture/capture.c +++ b/subsys/net/lib/capture/capture.c @@ -486,6 +486,8 @@ static int capture_enable(const struct device *dev, struct net_if *iface) ctx->capture_iface = iface; ctx->is_enabled = true; + net_mgmt_event_notify(NET_EVENT_CAPTURE_STARTED, iface); + net_if_up(ctx->tunnel_iface); return 0; @@ -494,12 +496,15 @@ static int capture_enable(const struct device *dev, struct net_if *iface) static int capture_disable(const struct device *dev) { struct net_capture *ctx = dev->data; + struct net_if *iface = ctx->capture_iface; ctx->capture_iface = NULL; ctx->is_enabled = false; net_if_down(ctx->tunnel_iface); + net_mgmt_event_notify(NET_EVENT_CAPTURE_STOPPED, iface); + return 0; } diff --git a/subsys/net/lib/shell/events.c b/subsys/net/lib/shell/events.c index b7c1651cb17..44037a76f3f 100644 --- a/subsys/net/lib/shell/events.c +++ b/subsys/net/lib/shell/events.c @@ -267,6 +267,12 @@ static const char *get_l4_desc(uint32_t event) case NET_EVENT_COAP_OBSERVER_REMOVED: desc = "CoAP observer removed"; break; + case NET_EVENT_CAPTURE_STARTED: + desc = "Capture started"; + break; + case NET_EVENT_CAPTURE_STOPPED: + desc = "Capture stopped"; + break; } return desc; From 78a0cfbd941c7f48ffe8eb103dbe844e7da13042 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sat, 30 Mar 2024 14:15:36 +0200 Subject: [PATCH 1828/2402] net: shell: capture: Set capture device if user did not use shell If user created the capture device using the API and not via the shell, then the device name was not set. Use the default capture device in this case. Signed-off-by: Jukka Rissanen --- subsys/net/lib/shell/capture.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/subsys/net/lib/shell/capture.c b/subsys/net/lib/shell/capture.c index 0c7347f8774..4ea9e4790f6 100644 --- a/subsys/net/lib/shell/capture.c +++ b/subsys/net/lib/shell/capture.c @@ -15,6 +15,7 @@ LOG_MODULE_DECLARE(net_shell); #include #if defined(CONFIG_NET_CAPTURE) +#define DEFAULT_DEV_NAME "NET_CAPTURE0" static const struct device *capture_dev; static void get_address_str(const struct sockaddr *addr, @@ -74,6 +75,10 @@ static int cmd_net_capture(const struct shell *sh, size_t argc, char *argv[]) #if defined(CONFIG_NET_CAPTURE) bool ret; + if (capture_dev == NULL) { + capture_dev = device_get_binding(DEFAULT_DEV_NAME); + } + if (capture_dev == NULL) { PR_INFO("Network packet capture %s\n", "not configured"); } else { From 7fdebb5a917685b88208675a31271d0bceab6f69 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 31 Mar 2024 16:03:00 +0300 Subject: [PATCH 1829/2402] drivers: net: ppp: Add packet capture support User is able to enable packet capture for low level HDLC data frames received from and sent to network. This data can sent to remote system for analysis. The captured data is encapsulated into Linux cooked mode SLL packets. Signed-off-by: Jukka Rissanen --- drivers/net/Kconfig | 18 +++++++++ drivers/net/ppp.c | 89 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 107 insertions(+) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index c9ad4e34e87..1ca8bb909fd 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -70,6 +70,24 @@ config NET_PPP_VERIFY_FCS to disable this as it takes some time to verify the received packet. +config NET_PPP_CAPTURE + bool "Capture received PPP packets" + depends on NET_CAPTURE_COOKED_MODE + help + This enables PPP packet capture. One needs to configure the + packet capturing in core network stack to send the captured packets + to outside system. This requires a non-PPP network connection + where the captured packets are sent for processing. Note that you + cannot use the PPP connection to sending packets as that would + lead recursion. + +config NET_PPP_CAPTURE_BUF_SIZE + int "Capture buffer for storing full PPP packets" + depends on NET_PPP_CAPTURE + default 1500 + help + The captured PPP frames are temporarily stored into this buffer. + config PPP_MAC_ADDR string "MAC address for the interface" help diff --git a/drivers/net/ppp.c b/drivers/net/ppp.c index 70fbe9631a5..a40efda0fbb 100644 --- a/drivers/net/ppp.c +++ b/drivers/net/ppp.c @@ -32,6 +32,9 @@ LOG_MODULE_REGISTER(net_ppp, LOG_LEVEL); #include #include #include +#include +#include +#include #include "../../subsys/net/ip/net_stats.h" #include "../../subsys/net/ip/net_private.h" @@ -50,6 +53,24 @@ enum ppp_driver_state { K_KERNEL_STACK_DEFINE(ppp_workq, PPP_WORKQ_STACK_SIZE); +#if defined(CONFIG_NET_PPP_CAPTURE) +#define MAX_CAPTURE_BUF_LEN CONFIG_NET_PPP_CAPTURE_BUF_SIZE +#else +#define MAX_CAPTURE_BUF_LEN 1 +#endif + +struct net_ppp_capture_ctx { + struct net_capture_cooked cooked; + uint8_t capture_buf[MAX_CAPTURE_BUF_LEN]; +}; + +#if defined(CONFIG_NET_PPP_CAPTURE) +static struct net_ppp_capture_ctx _ppp_capture_ctx; +static struct net_ppp_capture_ctx *ppp_capture_ctx = &_ppp_capture_ctx; +#else +static struct net_ppp_capture_ctx *ppp_capture_ctx; +#endif + struct ppp_driver_context { const struct device *dev; struct net_if *iface; @@ -378,6 +399,28 @@ static int ppp_send_flush(struct ppp_driver_context *ppp, int off) } uint8_t *buf = ppp->send_buf; + if (IS_ENABLED(CONFIG_NET_PPP_CAPTURE) && + net_capture_is_enabled(NULL) && ppp_capture_ctx) { + size_t len = off; + uint8_t *start = &buf[0]; + + /* Do not capture HDLC frame start and stop bytes (0x7e) */ + + if (buf[0] == 0x7e) { + len--; + start++; + } + + if (buf[off] == 0x7e) { + len--; + } + + net_capture_data(&ppp_capture_ctx->cooked, + start, len, + NET_CAPTURE_OUTGOING, + NET_ETH_PTYPE_HDLC); + } + /* If we're using gsm_mux, We don't want to use poll_out because sending * one byte at a time causes each byte to get wrapped in muxing headers. * But we can safely call uart_fifo_fill outside of ISR context when @@ -594,6 +637,34 @@ static void ppp_process_msg(struct ppp_driver_context *ppp) #endif net_pkt_unref(ppp->pkt); } else { + /* If PPP packet capturing is enabled, then send the + * full packet with PPP headers for processing. Currently this + * captures only valid frames. If we would need to receive also + * invalid frames, the if-block would need to be moved before + * fcs check above. + */ + if (IS_ENABLED(CONFIG_NET_PPP_CAPTURE) && + net_capture_is_enabled(NULL) && ppp_capture_ctx) { + size_t copied; + + /* Linearize the packet data. We cannot use the + * capture API that deals with net_pkt as we work + * in cooked mode and want to capture also the + * HDLC frame data. + */ + copied = net_buf_linearize(ppp_capture_ctx->capture_buf, + sizeof(ppp_capture_ctx->capture_buf), + ppp->pkt->buffer, + 0U, + net_pkt_get_len(ppp->pkt)); + + net_capture_data(&ppp_capture_ctx->cooked, + ppp_capture_ctx->capture_buf, + copied, + NET_CAPTURE_HOST, + NET_ETH_PTYPE_HDLC); + } + /* Remove the Address (0xff), Control (0x03) and * FCS fields (16-bit) as the PPP L2 layer does not need * those bytes. @@ -961,6 +1032,24 @@ static void ppp_iface_init(struct net_if *iface) net_if_set_link_addr(iface, ll_addr->addr, ll_addr->len, NET_LINK_ETHERNET); + if (IS_ENABLED(CONFIG_NET_PPP_CAPTURE)) { + static bool capture_setup_done; + + if (!capture_setup_done) { + int ret; + + ret = net_capture_cooked_setup(&ppp_capture_ctx->cooked, + ARPHRD_PPP, + sizeof(ppp->mac_addr), + ppp->mac_addr); + if (ret < 0) { + LOG_DBG("Cannot setup capture (%d)", ret); + } else { + capture_setup_done = true; + } + } + } + memset(ppp->buf, 0, sizeof(ppp->buf)); /* If we have a GSM modem with PPP support or interface autostart is disabled From 76290b052f95463ae1d6d6bc17b9e163ba724a60 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 25 Mar 2024 12:20:21 +0200 Subject: [PATCH 1830/2402] samples: net: echo-server: Make sure to attach to correct tunnel If there are multiple tunnels, then use the tunnel device name to select the correct one. Note that this tunnel is only used for network packet capture in this sample application. Signed-off-by: Jukka Rissanen --- samples/net/sockets/echo_server/src/tunnel.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/samples/net/sockets/echo_server/src/tunnel.c b/samples/net/sockets/echo_server/src/tunnel.c index 77c85a7cd93..da04f6f864a 100644 --- a/samples/net/sockets/echo_server/src/tunnel.c +++ b/samples/net/sockets/echo_server/src/tunnel.c @@ -21,7 +21,9 @@ struct ud { bool is_tunnel(struct net_if *iface) { - if (net_if_l2(iface) == &NET_L2_GET_NAME(VIRTUAL)) { + if (net_if_l2(iface) == &NET_L2_GET_NAME(VIRTUAL) && + strncmp(net_if_get_device(iface)->name, "IP_TUNNEL0", + strlen(net_if_get_device(iface)->name)) == 0) { return true; } @@ -134,6 +136,11 @@ int init_tunnel(void) net_if_foreach(iface_cb, &ud); + if (ud.tunnel == NULL) { + LOG_ERR("Tunnel interface not found."); + return -ENOENT; + } + ret = net_mgmt(NET_REQUEST_VIRTUAL_INTERFACE_SET_PEER_ADDRESS, ud.tunnel, ¶ms, sizeof(params)); if (ret < 0 && ret != -ENOTSUP) { From 4ae75194aa0b692c99268c9c2bfde27b33f79f0e Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 28 Mar 2024 17:10:08 +0200 Subject: [PATCH 1831/2402] samples: net: capture: Add a way to capture some cooked data For demonstration purposes add a way to capture some arbitrary data and send it in cooked mode for analysis. Signed-off-by: Jukka Rissanen --- samples/net/capture/Kconfig | 20 ++ samples/net/capture/overlay-tunnel.conf | 14 + samples/net/capture/prj.conf | 2 + samples/net/capture/src/main.c | 325 ++++++++++++++++++++++++ 4 files changed, 361 insertions(+) create mode 100644 samples/net/capture/Kconfig create mode 100644 samples/net/capture/overlay-tunnel.conf diff --git a/samples/net/capture/Kconfig b/samples/net/capture/Kconfig new file mode 100644 index 00000000000..6dc9168934c --- /dev/null +++ b/samples/net/capture/Kconfig @@ -0,0 +1,20 @@ +# Private config options for capture sample app + +# Copyright (c) 2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +mainmenu "Networking capture sample application" + +config NET_SAMPLE_TUNNEL_PEER_ADDR + string "Remote IP address of the tunnel interface" + depends on NET_L2_IPIP + help + Use overlay-tunnel.conf to setup the tunnel support. + +config NET_SAMPLE_TUNNEL_MY_ADDR + string "My address for tunnel interface" + depends on NET_L2_IPIP + help + The value depends on your network setup. + +source "Kconfig.zephyr" diff --git a/samples/net/capture/overlay-tunnel.conf b/samples/net/capture/overlay-tunnel.conf new file mode 100644 index 00000000000..0adfa5b9bce --- /dev/null +++ b/samples/net/capture/overlay-tunnel.conf @@ -0,0 +1,14 @@ +CONFIG_NET_L2_VIRTUAL=y +CONFIG_NET_L2_VIRTUAL_MGMT=y +CONFIG_NET_L2_IPIP=y + +CONFIG_NET_IF_MAX_IPV6_COUNT=4 +CONFIG_NET_IF_MAX_IPV4_COUNT=4 + +# Use this for IPv6 over IPv4 +CONFIG_NET_SAMPLE_TUNNEL_MY_ADDR="2001:db8:200::1" +CONFIG_NET_SAMPLE_TUNNEL_PEER_ADDR="2001:db8:200::2" + +# Use this for IPv4 over IPv4 +#CONFIG_NET_SAMPLE_TUNNEL_MY_ADDR="198.51.100.1" +#CONFIG_NET_SAMPLE_TUNNEL_PEER_ADDR="198.51.100.2" diff --git a/samples/net/capture/prj.conf b/samples/net/capture/prj.conf index 26aa1ba0cd0..0d22cd13a12 100644 --- a/samples/net/capture/prj.conf +++ b/samples/net/capture/prj.conf @@ -25,5 +25,7 @@ CONFIG_NET_CONFIG_SETTINGS=y CONFIG_NET_CONFIG_NEED_IPV6=y CONFIG_NET_CONFIG_NEED_IPV4=y CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8::1" +CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2" CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1" +CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2" CONFIG_NET_CONFIG_MY_IPV4_NETMASK="255.255.255.0" diff --git a/samples/net/capture/src/main.c b/samples/net/capture/src/main.c index e6dfd949a1d..3feafc4eb25 100644 --- a/samples/net/capture/src/main.c +++ b/samples/net/capture/src/main.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2021 Intel Corporation. + * Copyright (c) 2024 Nordic Semiconductor * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,10 +8,334 @@ #include LOG_MODULE_REGISTER(net_capture_sample, LOG_LEVEL_DBG); +#include #include +#include +#include +#include +#include + +#if defined(CONFIG_NET_CAPTURE_COOKED_MODE) +#define COOKED_MODE_INTERFACE_NAME CONFIG_NET_CAPTURE_COOKED_MODE_INTERFACE_NAME +#else +#define COOKED_MODE_INTERFACE_NAME "" +#endif + +static bool started; + +uint16_t link_types_to_monitor[] = { + NET_ETH_PTYPE_CAN, + NET_ETH_PTYPE_HDLC, +}; + +struct data_to_send { + struct net_capture_cooked *ctx; + size_t len; + const char *data; + enum net_capture_packet_type type; + uint16_t eth_p_type; +}; + +#define DATA(_ctx, _data, _type, _ptype) { \ + .ctx = _ctx, \ + .len = sizeof(_data), \ + .data = _data, \ + .type = _type, \ + .eth_p_type = _ptype \ + } + +static const char can_data[] = { + 0x01, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, +}; + +static struct net_capture_cooked ctx_can = { + .hatype = ARPHRD_CAN, + .halen = 0, + .addr = { 0 } +}; + +static const char ppp_send_lcp_conf_req_data[] = { + 0xff, 0x7d, 0x23, 0xc0, 0x21, 0x7d, 0x21, 0x7d, + 0x21, 0x7d, 0x20, 0x7d, 0x24, 0xd1, 0xb5, +}; + +static const char ppp_recv_lcp_conf_req_data[] = { + 0xff, 0x03, 0xc0, 0x21, 0x01, 0x01, 0x00, 0x16, + 0x02, 0x06, 0x00, 0x00, 0x00, 0x00, 0x03, 0x04, + 0xc0, 0x23, 0x05, 0x06, 0xe4, 0xdd, 0x30, 0x57, + 0x07, 0x02, 0x0c, 0x57, +}; + +static const char ppp_send_lcp_conf_rej_data[] = { + 0xff, 0x7d, 0x23, 0xc0, 0x21, 0x7d, 0x24, 0x7d, + 0x21, 0x7d, 0x20, 0x7d, 0x32, 0x7d, 0x22, 0x7d, + 0x26, 0x7d, 0x20, 0x7d, 0x20, 0x7d, 0x20, 0x7d, + 0x20, 0x7d, 0x25, 0x7d, 0x26, 0x7d, 0x20, 0x38, + 0xea, 0x74, 0x7d, 0x27, 0x7d, 0x22, 0x8c, 0xa3, +}; + +static struct net_capture_cooked ctx_ppp = { + .hatype = ARPHRD_PPP, + .halen = 6, + .addr = { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6 } +}; + +/* We just construct some demo packets and send them out */ +static const struct data_to_send data[] = { + DATA(&ctx_can, can_data, NET_CAPTURE_OUTGOING, NET_ETH_PTYPE_CAN), + DATA(&ctx_ppp, ppp_send_lcp_conf_req_data, NET_CAPTURE_OUTGOING, NET_ETH_PTYPE_HDLC), + DATA(&ctx_ppp, ppp_recv_lcp_conf_req_data, NET_CAPTURE_HOST, NET_ETH_PTYPE_HDLC), + DATA(&ctx_ppp, ppp_send_lcp_conf_rej_data, NET_CAPTURE_OUTGOING, NET_ETH_PTYPE_HDLC), +}; + +static int cmd_sample_send(const struct shell *sh, + size_t argc, char *argv[]) +{ + if (!IS_ENABLED(CONFIG_NET_CAPTURE_COOKED_MODE)) { + shell_fprintf(sh, SHELL_NORMAL, + "Enable %s to use the sample shell.\n", + "CONFIG_NET_CAPTURE_COOKED_MODE"); + return 0; + } + + if (!started) { + if (sh != NULL) { + shell_fprintf(sh, SHELL_WARNING, "%s", + "Capturing not enabled, cannot send data.\n"); + } + + return 0; + } + + ARRAY_FOR_EACH_PTR(data, ptr) { + net_capture_data(ptr->ctx, ptr->data, ptr->len, + ptr->type, ptr->eth_p_type); + } + + return 0; +} + +SHELL_STATIC_SUBCMD_SET_CREATE(sample_commands, + SHELL_CMD(send, NULL, + "Send example data\n", + cmd_sample_send), + SHELL_SUBCMD_SET_END +); + +SHELL_CMD_REGISTER(sample, &sample_commands, + "Sample application commands", NULL); + +static int init_app(void) +{ + /* What this sample does: + * - Create a tunnel that runs on top of the Ethernet interface + * - Start to capture data from cooked mode capture interface + * - Take the cooked mode interface up + * + * All of the above could be done manually from net-shell with + * these commands: + * + * net capture setup 192.0.2.2 2001:db8:200::1 2001:db8:200::2 + * net capture enable 2 + * net iface up 2 + * + * Explanation what those commands do: + * + * The "net capture setup" creates a tunnel. The tunnel is IPv6 + * tunnel and our inner end point address is 2001:db8:200::1 + * and the inner peer end point address is 2001:db8:200::2. In the + * tests, the tunnel can be created in Linux host with this command + * + * net-setup.sh -c zeth-tunnel.conf + * + * The net-setup.sh command is found in net-tools Zephyr project. + * In host side, the tunnel interface is called zeth-ip6ip where IPv6 + * packets are run in a IPv4 tunnel. + * + * The network interfaces in this sample application are: + * + * Interface any (0x808ab3c) (Dummy) [1] + * ================================ + * Virtual interfaces attached to this : 2 + * Device : NET_ANY (0x80849a4) + * + * Interface cooked (0x808ac94) (Virtual) [2] + * ================================== + * Virtual name : Cooked mode capture + * Attached : 1 (Dummy / 0x808ab3c) + * Device : NET_COOKED (0x808497c) + * + * Interface eth0 (0x808adec) (Ethernet) [3] + * =================================== + * Virtual interfaces attached to this : 4 + * Device : zeth0 (0x80849b8) + * IPv6 unicast addresses (max 4): + * fe80::5eff:fe00:53e6 autoconf preferred infinite + * 2001:db8::1 manual preferred infinite + * IPv4 unicast addresses (max 2): + * 192.0.2.1/255.255.255.0 overridable preferred infinite + * + * Interface net0 (0x808af44) (Virtual) [4] + * ================================== + * Virtual name : Capture tunnel + * Attached : 3 (Ethernet / 0x808adec) + * Device : IP_TUNNEL0 (0x8084990) + * IPv6 unicast addresses (max 4): + * 2001:db8:200::1 manual preferred infinite + * fe80::efed:6dff:fef2:b1df autoconf preferred infinite + * fe80::56da:1eff:fe5e:bc02 autoconf preferred infinite + * + * The 192.0.2.2 is the address of the outer end point of the host that + * terminates the tunnel. Zephyr uses this address to select the internal + * interface to use for the tunnel. In this example it is interface 3. + * + * The interface 2 is the interface that runs on top of interface 1. The + * cooked capture packets are written by the capture API to sink interface 1. + * The packets propagate to interface 2 because it is linked to first interface. + * The "net capture enable 2" command will cause the packets sent to interface 2 + * to be written to capture interface 4, which in turn capsulates the packets and + * tunnels them to peer via the Ethernet interface 3. + * + * The above IP addresses might change if you change the addresses in + * overlay-tunnel.conf file. + * + * If the cooked mode capture is enabled (CONFIG_NET_CAPTURE_COOKED_MODE=y), + * then we setup the capture automatically to the correct network interface. + * User is then able to send sample network packets in cooked mode and monitor + * the captured packets in the host zeth-ip6ip network interface. Use "sample send" + * command to do that. + * + * You can use "net-capture.py -i zeth-ip6ip -c" command to capture the cooked + * packets in host side. The net-capture.py tool is found in net-tools package. + */ + + const char remote[] = CONFIG_NET_CONFIG_PEER_IPV4_ADDR; + const char local[] = CONFIG_NET_SAMPLE_TUNNEL_MY_ADDR; + const char peer[] = CONFIG_NET_SAMPLE_TUNNEL_PEER_ADDR; + const struct device *capture_dev; + int ret; + + ret = net_capture_setup(remote, local, peer, &capture_dev); + if (ret < 0) { + LOG_ERR("Capture cannot be setup (%d)", ret); + return -ENOEXEC; + } + + if (IS_ENABLED(CONFIG_NET_CAPTURE_COOKED_MODE)) { + /* If we are running in cooked mode, start to capture the packets + * from cooked mode interface. + */ + struct virtual_interface_req_params params = { 0 }; + struct virtual_interface_link_types link_types; + int ifindex; + + ifindex = net_if_get_by_name(COOKED_MODE_INTERFACE_NAME); + if (ifindex < 0) { + LOG_ERR("Interface \"%s\" not found.", COOKED_MODE_INTERFACE_NAME); + return -ENOENT; + } + + ret = net_capture_enable(capture_dev, net_if_get_by_index(ifindex)); + if (ret < 0) { + LOG_ERR("Cannot enable capture to interface %d (%d)", + ifindex, ret); + return ret; + } + + /* Setup the cooked interface to capture these types of packets */ + memcpy(&link_types.type, &link_types_to_monitor, + MIN(sizeof(link_types.type), sizeof(link_types_to_monitor))); + link_types.count = MIN(ARRAY_SIZE(link_types.type), + ARRAY_SIZE(link_types_to_monitor)); + + params.family = AF_UNSPEC; + memcpy(¶ms.link_types, &link_types, + sizeof(struct virtual_interface_link_types)); + + ret = net_mgmt(NET_REQUEST_VIRTUAL_INTERFACE_SET_LINK_TYPE, + net_if_get_by_index(ifindex), ¶ms, + sizeof(struct virtual_interface_req_params)); + if (ret < 0 && ret != -ENOTSUP) { + LOG_ERR("Cannot set interface %d link types (%d)", + ifindex, ret); + return ret; + } + + /* Now the capture device and the tunnel interface is setup, + * we just need to bring up the actual interface we want to capture + * as it is down by default. + */ + ret = net_if_up(net_if_get_by_index(ifindex)); + if (ret < 0) { + LOG_ERR("Cannot take up interface %d (%d)", ifindex, ret); + return ret; + } + + LOG_INF("Type \"sample send\" to send dummy capture data to tunnel."); + } else { + LOG_INF("Please enable capture manually from net-shell"); + LOG_INF("Use \"net capture enable \" command to start " + "capturing desired network interface."); + } + + return 0; +} + +#define EVENT_MASK (NET_EVENT_CAPTURE_STARTED | NET_EVENT_CAPTURE_STOPPED) + +static void event_handler(struct net_mgmt_event_callback *cb, + uint32_t mgmt_event, struct net_if *iface) +{ + ARG_UNUSED(iface); + ARG_UNUSED(cb); + + if ((mgmt_event & EVENT_MASK) != mgmt_event) { + return; + } + + if (mgmt_event == NET_EVENT_CAPTURE_STARTED) { + started = true; + } + + if (mgmt_event == NET_EVENT_CAPTURE_STOPPED) { + started = false; + } +} int main(void) { + static struct net_mgmt_event_callback mgmt_cb; + struct net_if *iface; + uint32_t event; + int ret; + LOG_INF("Starting network capture sample"); + + net_mgmt_init_event_callback(&mgmt_cb, event_handler, EVENT_MASK); + net_mgmt_add_event_callback(&mgmt_cb); + + ret = init_app(); + if (ret < 0) { + LOG_ERR("Cannot start the application."); + return ret; + } + + while (1) { + ret = net_mgmt_event_wait(EVENT_MASK, + &event, + &iface, + NULL, + NULL, + K_FOREVER); + if (ret < 0) { + continue; + } + + LOG_INF("Capturing %s on interface %d", + event == NET_EVENT_CAPTURE_STARTED ? "started" : "stopped", + net_if_get_by_iface(iface)); + } + return 0; } From c6ea98eb6ffccedb29b53bc83b23aaf223bcb77f Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 31 Mar 2024 17:14:31 +0300 Subject: [PATCH 1832/2402] doc: net: Add information for cooked mode capture Add cooked mode capturing information to network documentation. Signed-off-by: Jukka Rissanen --- doc/connectivity/networking/api/capture.rst | 82 +++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/doc/connectivity/networking/api/capture.rst b/doc/connectivity/networking/api/capture.rst index ee7605624c4..c126df1766c 100644 --- a/doc/connectivity/networking/api/capture.rst +++ b/doc/connectivity/networking/api/capture.rst @@ -15,6 +15,88 @@ traffic in one of the Zephyr network interfaces and send that traffic to external system for analysis. The monitoring can be setup either manually using ``net-shell`` or automatically by using the ``net_capture`` API. +Cooked Mode Capture +******************* + +If capturing is enabled and configured, the system will automatically capture +network traffic for a given network interface. If you would like to capture +network data when there is no network interface involved, then you need to use +the cooked mode capture API. + +In cooked mode capture, arbitrary network packets can be captured and there +does not need to be network interface involved. For example low level HDLC +packets in PPP can be captured, as the HDLC L2 layer data is stripped away when +using the normal network interface based capture. Also CANBUS or Bluetooth +network data could be captured although currently there is no support in the +network stack to capture those. + +The cooked mode capture works like this: + +* An ``any`` network interface is created. It acts as a sink where the cooked + mode captured packets are written by the cooked mode capture API. +* A ``cooked`` virtual network interface is attached on top of this ``any`` + interface. +* The ``cooked`` interface must be configured to capture certain L2 packet types + using the network interface configuration API. +* When cooked mode capture API is used, the caller must specify what is the + layer 2 protocol type of the captured data. The cooked mode capture API is then + able to determine what to capture when receiving such a L2 packet. +* The network packet capturing infrastructure is then setup so that the ``cooked`` + interface is marked as captured network interface. + The packets received by the ``cooked`` interface via the ``any`` interface are + then automatically placed to the capture IP tunnel and sent to remote host + for analysis. + +For example, in the sample capture application, these network interfaces +are created: + +.. code-block:: c + + Interface any (0x808ab3c) (Dummy) [1] + ================================ + Virtual interfaces attached to this : 2 + Device : NET_ANY (0x80849a4) + + Interface cooked (0x808ac94) (Virtual) [2] + ================================== + Virtual name : Cooked mode capture + Attached : 1 (Dummy / 0x808ab3c) + Device : NET_COOKED (0x808497c) + + Interface eth0 (0x808adec) (Ethernet) [3] + =================================== + Virtual interfaces attached to this : 4 + Device : zeth0 (0x80849b8) + IPv6 unicast addresses (max 4): + fe80::5eff:fe00:53e6 autoconf preferred infinite + 2001:db8::1 manual preferred infinite + IPv4 unicast addresses (max 2): + 192.0.2.1/255.255.255.0 overridable preferred infinite + + Interface net0 (0x808af44) (Virtual) [4] + ================================== + Virtual name : Capture tunnel + Attached : 3 (Ethernet / 0x808adec) + Device : IP_TUNNEL0 (0x8084990) + IPv6 unicast addresses (max 4): + 2001:db8:200::1 manual preferred infinite + fe80::efed:6dff:fef2:b1df autoconf preferred infinite + fe80::56da:1eff:fe5e:bc02 autoconf preferred infinite + +In this example, the ``192.0.2.2`` is the address of the outer end point of the +host that terminates the tunnel. Zephyr uses this address to select the +internal interface to use for the tunnel. In this example it is interface 3. + +The interface 2 is a virtual interface that runs on top of interface 1. The +cooked capture packets are written by the capture API to sink interface 1. +The packets propagate to interface 2 because it is linked to the first interface. +The ``net capture enable 2`` net-shell command will cause the packets sent to +interface 2 to be written to capture interface 4, which in turn then capsulates +the packets and tunnels them to peer via the Ethernet interface 3. + +The above IP addresses might change if you change the addresses in the +sample :zephyr_file:`samples/net/capture/overlay-tunnel.conf` file. + Sample usage ************ From 6e4bdb75100599239f9bd40b3f55ad677f21b55f Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 31 Mar 2024 16:10:45 +0300 Subject: [PATCH 1833/2402] west.yaml: Update net-tools module The net-tools contains net-capture.py update to show information of captured SLL packets. Signed-off-by: Jukka Rissanen --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 3af54307b0d..1a55e019083 100644 --- a/west.yml +++ b/west.yml @@ -290,7 +290,7 @@ manifest: - debug revision: a819419603a2dfcb47f7f39092e1bc112e45d1ef - name: net-tools - revision: 3a677d355cc7f73e444801a6280d0ccec80a1957 + revision: cd2eb1858a1570b49241e18fc1e1cd849a450af2 path: tools/net-tools groups: - tools From 2e053e8116ea23e8b00ee848c5a17390c8e20bd4 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Thu, 28 Mar 2024 22:36:14 -0700 Subject: [PATCH 1834/2402] doc: security: CVE-2024-3077 left embargo Disclose information about CVE-2024-3077. Signed-off-by: Flavio Ceolin --- doc/security/vulnerabilities.rst | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/doc/security/vulnerabilities.rst b/doc/security/vulnerabilities.rst index 2eda89e11f3..468098fa0cc 100644 --- a/doc/security/vulnerabilities.rst +++ b/doc/security/vulnerabilities.rst @@ -1699,3 +1699,17 @@ This has been fixed in main for v3.6.0 - `PR 69170 fix for main `_ + +CVE-2024-3077 +------------- + +Bluetooth: Integer underflow in gatt_find_info_rsp. A malicious BLE +device can crash BLE victim device by sending malformed gatt packet. + +- `Zephyr project bug tracker GHSA-gmfv-4vfh-2mh8 + `_ + +This has been fixed in main for v3.7.0 + +- `PR 69396 fix for main + `_ From d832c12a28a2b051fdcd51b5b54b1941374bbaaa Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Thu, 28 Mar 2024 22:39:16 -0700 Subject: [PATCH 1835/2402] doc: release-notes-3.7: Add CVE-2024-3077 info Add CVE-2024-3077 to release notes. Signed-off-by: Flavio Ceolin --- doc/releases/release-notes-3.7.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index 2e046f084b1..d631a6b13f3 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -25,6 +25,9 @@ The following CVEs are addressed by this release: More detailed information can be found in: https://docs.zephyrproject.org/latest/security/vulnerabilities.html +* CVE-2024-3077 `Zephyr project bug tracker GHSA-gmfv-4vfh-2mh8 + `_ + Architectures ************* From 6b6adc07d0afca807ac66de6819fe99e4a88a285 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Thu, 4 Apr 2024 10:27:51 -0500 Subject: [PATCH 1836/2402] dts: arm: nxp_mcxn94x: add EDMA channels for LPUART RX and TX Add EDMA channels for LPUART RX and TX to LPFLEXCOMM 2 and 4, as these nodes are enabled with the UART driver Signed-off-by: Daniel DeGrasse --- dts/arm/nxp/nxp_mcxn94x_common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi index 3f84bde4f2b..22ca3ffd928 100644 --- a/dts/arm/nxp/nxp_mcxn94x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi @@ -256,6 +256,9 @@ compatible = "nxp,kinetis-lpuart"; reg = <0x94000 0x1000>; clocks = <&syscon MCUX_FLEXCOMM2_CLK>; + /* DMA channels 4 and 5, muxed to LPUART2 RX and TX */ + dmas = <&edma0 4 73>, <&edma0 5 74>; + dma-names = "rx", "tx"; status = "disabled"; }; flexcomm2_lpspi2: lpspi@94000 { @@ -324,6 +327,9 @@ compatible = "nxp,kinetis-lpuart"; reg = <0xb4000 0x1000>; clocks = <&syscon MCUX_FLEXCOMM4_CLK>; + /* DMA channels 2 and 3, muxed to LPUART4 RX and TX */ + dmas = <&edma0 2 77>, <&edma0 3 78>; + dma-names = "rx", "tx"; status = "disabled"; }; flexcomm4_lpspi4: lpspi@b4000 { From cbcbe7f43dfab6ca38a4ef4506af2b36dfbe550d Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Thu, 4 Apr 2024 10:28:55 -0500 Subject: [PATCH 1837/2402] boards: nxp: frdm_mcxn947: add pinctrl for LPUART2 Add pinctrl and board enablement for LPUART2, which is broken out to P4_2 and P4_3 on the FRDM board. Signed-off-by: Daniel DeGrasse --- boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi | 10 ++++++++++ boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 6 ++++++ boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts | 8 ++++++++ 3 files changed, 24 insertions(+) diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi index 3bd948c668c..13bd6950920 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi @@ -31,6 +31,16 @@ }; }; + pinmux_flexcomm2_lpuart: pinmux_flexcomm2_lpuart { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart { group0 { pinmux = , diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 3b95bc74351..22323d6422c 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -61,6 +61,12 @@ clock-frequency = ; }; +&flexcomm2_lpuart2 { + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm2_lpuart>; + pinctrl-names = "default"; +}; + &flexcomm4_lpuart4 { current-speed = <115200>; pinctrl-0 = <&pinmux_flexcomm4_lpuart>; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts index ba08325ae0a..2f587614580 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts @@ -85,6 +85,14 @@ status = "okay"; }; +/* + *LPFLEXCOMM supports UART and I2C on the same instance, enable this for + * LFLEXCOMM2 + */ +&flexcomm2_lpuart2 { + status = "okay"; +}; + &flexcomm4 { status = "okay"; }; From 2ad951ca85ddb75f229c90311e951faa80fa3a1e Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Thu, 4 Apr 2024 10:29:45 -0500 Subject: [PATCH 1838/2402] tests: drivers: uart_async_api: enable for frdm_mcxn947 Enable the UART async API test for the frdm_mcxn947 board. Signed-off-by: Daniel DeGrasse --- .../boards/frdm_mcxn947_mcxn947_cpu0.overlay | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 tests/drivers/uart/uart_async_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/tests/drivers/uart/uart_async_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay new file mode 100644 index 00000000000..910350c8c16 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay @@ -0,0 +1,9 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * To test this sample connect P4_2 to P4_3 + */ +dut: &flexcomm2_lpuart2 {}; From 5cd077029e1c94bb7744e4702085f48ce494359f Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Thu, 4 Apr 2024 09:12:22 -0300 Subject: [PATCH 1839/2402] samples: board: esp32: rename board config to meet proper cpu cluster This sample conf and overlay file regarding esp_wrover_kit should be used only for procpu. Signed-off-by: Sylvio Alves --- .../{esp_wrover_kit.conf => esp_wrover_kit_esp32_procpu.conf} | 0 ...esp_wrover_kit.overlay => esp_wrover_kit_esp32_procpu.overlay} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename samples/subsys/fs/fs_sample/boards/{esp_wrover_kit.conf => esp_wrover_kit_esp32_procpu.conf} (100%) rename samples/subsys/fs/fs_sample/boards/{esp_wrover_kit.overlay => esp_wrover_kit_esp32_procpu.overlay} (100%) diff --git a/samples/subsys/fs/fs_sample/boards/esp_wrover_kit.conf b/samples/subsys/fs/fs_sample/boards/esp_wrover_kit_esp32_procpu.conf similarity index 100% rename from samples/subsys/fs/fs_sample/boards/esp_wrover_kit.conf rename to samples/subsys/fs/fs_sample/boards/esp_wrover_kit_esp32_procpu.conf diff --git a/samples/subsys/fs/fs_sample/boards/esp_wrover_kit.overlay b/samples/subsys/fs/fs_sample/boards/esp_wrover_kit_esp32_procpu.overlay similarity index 100% rename from samples/subsys/fs/fs_sample/boards/esp_wrover_kit.overlay rename to samples/subsys/fs/fs_sample/boards/esp_wrover_kit_esp32_procpu.overlay From d3edd34df35e3fe7daa92c1464ee073b273d407a Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Tue, 26 Mar 2024 19:54:00 +0000 Subject: [PATCH 1840/2402] drivers: sensor: dht: Add lock IRQ option Adds an option that allows for locking all interrupts when reading the data from this sensor, this can be used alongside systems like Bluetooth to vastly increase chances of getting a reading from the sensor successfully, at the risk of losing Bluetooth packets. Signed-off-by: Jamie McCrae --- drivers/sensor/dht/Kconfig | 13 ++++++++++++- drivers/sensor/dht/dht.c | 12 ++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/sensor/dht/Kconfig b/drivers/sensor/dht/Kconfig index 85b7108dc7b..92827aabd05 100644 --- a/drivers/sensor/dht/Kconfig +++ b/drivers/sensor/dht/Kconfig @@ -3,10 +3,21 @@ # Copyright (c) 2016 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -config DHT +menuconfig DHT bool "DHT Temperature and Humidity Sensor" default y depends on DT_HAS_AOSONG_DHT_ENABLED depends on GPIO help Enable driver for the DHT temperature and humidity sensor family. + +if DHT + +config DHT_LOCK_IRQS + bool "Lock IRQs for sensor measurement" + help + Locks IRQs when taking sensor readings, this greatly improves the chances of getting a + reading successfully from the sensor at the cost of delayed interrupt servicing (e.g. + Bluetooth). Note that other systems might need to be adjusted to account for this. + +endif # DHT diff --git a/drivers/sensor/dht/dht.c b/drivers/sensor/dht/dht.c index 9ffe469cc34..acfa541b5fc 100644 --- a/drivers/sensor/dht/dht.c +++ b/drivers/sensor/dht/dht.c @@ -67,11 +67,19 @@ static int dht_sample_fetch(const struct device *dev, uint8_t buf[5]; unsigned int i, j; +#if defined(CONFIG_DHT_LOCK_IRQS) + int lock; +#endif + __ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL); /* assert to send start signal */ gpio_pin_set_dt(&cfg->dio_gpio, true); +#if defined(CONFIG_DHT_LOCK_IRQS) + lock = irq_lock(); +#endif + k_busy_wait(DHT_START_SIGNAL_DURATION); gpio_pin_set_dt(&cfg->dio_gpio, false); @@ -156,6 +164,10 @@ static int dht_sample_fetch(const struct device *dev, } cleanup: +#if defined(CONFIG_DHT_LOCK_IRQS) + irq_unlock(lock); +#endif + /* Switch to output inactive until next fetch. */ gpio_pin_configure_dt(&cfg->dio_gpio, GPIO_OUTPUT_INACTIVE); From 7a8d454e22d78fb3ffcc51008b4c0fbdaceaf98f Mon Sep 17 00:00:00 2001 From: Georgios Vasilakis Date: Fri, 8 Mar 2024 13:26:21 +0100 Subject: [PATCH 1841/2402] soc: nordic: Refactor soc_secure.h The soc_secure_* function are used by the non-secure application to access hardware resources which are mapped as secure. Using these functions for hardware resources mapped as non-secure is missleading. We have some soc_secure_* functions which read FICR values. In nRF91 and nRF53 platforms this made sense since FICR has hardware fixed mapping as secure. For nRF54 though the FICR has hardware fixed mapping as non-secure. This change refactors the soc_secure.h to exclude the functions which read FICR values from being included when FICR is mapped as non-secure. Also updates the hwinfo and ieee802154 drivers to adjust to this change. Signed-off-by: Georgios Vasilakis --- drivers/hwinfo/hwinfo_nrf.c | 12 +++++++- drivers/ieee802154/ieee802154_nrf5.c | 11 ++++++++ soc/nordic/common/soc_secure.h | 42 ++++++++++++++++------------ 3 files changed, 46 insertions(+), 19 deletions(-) diff --git a/drivers/hwinfo/hwinfo_nrf.c b/drivers/hwinfo/hwinfo_nrf.c index 4375cf05b2f..8b644f2f60e 100644 --- a/drivers/hwinfo/hwinfo_nrf.c +++ b/drivers/hwinfo/hwinfo_nrf.c @@ -7,12 +7,17 @@ #include #include #include -#include #include #ifndef CONFIG_BOARD_QEMU_CORTEX_M0 #include #endif + +#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && defined(NRF_FICR_S) #include +#else +#include +#endif + struct nrf_uid { uint32_t id[2]; }; @@ -22,7 +27,12 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) struct nrf_uid dev_id; uint32_t deviceid[2]; +#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && defined(NRF_FICR_S) soc_secure_read_deviceid(deviceid); +#else + deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR, 0); + deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR, 1); +#endif dev_id.id[0] = sys_cpu_to_be32(deviceid[1]); dev_id.id[1] = sys_cpu_to_be32(deviceid[0]); diff --git a/drivers/ieee802154/ieee802154_nrf5.c b/drivers/ieee802154/ieee802154_nrf5.c index d5bb4b33058..15f5398a191 100644 --- a/drivers/ieee802154/ieee802154_nrf5.c +++ b/drivers/ieee802154/ieee802154_nrf5.c @@ -25,7 +25,13 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME); #include #include + +#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && defined(NRF_FICR_S) #include +#else +#include +#endif + #include #include #include @@ -120,7 +126,12 @@ static void nrf5_get_eui64(uint8_t *mac) mac[index++] = (IEEE802154_NRF5_VENDOR_OUI >> 8) & 0xff; mac[index++] = IEEE802154_NRF5_VENDOR_OUI & 0xff; +#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && defined(NRF_FICR_S) soc_secure_read_deviceid(deviceid); +#else + deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR, 0); + deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR, 1); +#endif factoryAddress = (uint64_t)deviceid[EUI64_ADDR_HIGH] << 32; factoryAddress |= deviceid[EUI64_ADDR_LOW]; diff --git a/soc/nordic/common/soc_secure.h b/soc/nordic/common/soc_secure.h index d38d66ab488..cb7054962f2 100644 --- a/soc/nordic/common/soc_secure.h +++ b/soc/nordic/common/soc_secure.h @@ -15,6 +15,25 @@ void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_sel_t mcu) int soc_secure_mem_read(void *dst, void *src, size_t len); +#else /* defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ +#if NRF_GPIO_HAS_SEL +static inline void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_sel_t mcu) +{ + nrf_gpio_pin_control_select(pin_number, mcu); +} +#endif /* NRF_GPIO_HAS_SEL */ + +static inline int soc_secure_mem_read(void *dst, void *src, size_t len) +{ + (void)memcpy(dst, src, len); + return 0; +} + +#endif /* defined CONFIG_TRUSTED_EXECUTION_NONSECURE */ + +/* Include these soc_secure_* functions only when the FICR is mapped as secure only */ +#if defined(NRF_FICR_S) +#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) #if defined(CONFIG_SOC_HFXO_CAP_INTERNAL) static inline uint32_t soc_secure_read_xosc32mtrim(void) { @@ -41,31 +60,18 @@ static inline void soc_secure_read_deviceid(uint32_t deviceid[2]) } #else /* defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ - -static inline int soc_secure_mem_read(void *dst, void *src, size_t len) -{ - (void)memcpy(dst, src, len); - return 0; -} - -#if NRF_GPIO_HAS_SEL -static inline void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, - nrf_gpio_pin_sel_t mcu) -{ - nrf_gpio_pin_control_select(pin_number, mcu); -} -#endif /* NRF_GPIO_HAS_SEL */ - #if defined(CONFIG_SOC_HFXO_CAP_INTERNAL) static inline uint32_t soc_secure_read_xosc32mtrim(void) { - return NRF_FICR->XOSC32MTRIM; + return NRF_FICR_S->XOSC32MTRIM; } #endif /* defined(CONFIG_SOC_HFXO_CAP_INTERNAL) */ static inline void soc_secure_read_deviceid(uint32_t deviceid[2]) { - deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR, 0); - deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR, 1); + deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR_S, 0); + deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR_S, 1); } + #endif /* defined CONFIG_TRUSTED_EXECUTION_NONSECURE */ +#endif /* defined(NRF_FICR_S) */ From f8263e82935ef3d4e242eb4f38e01b643a214d01 Mon Sep 17 00:00:00 2001 From: Jakub Rzeszutko Date: Wed, 29 Nov 2023 21:02:16 +0100 Subject: [PATCH 1842/2402] shell: Add synchronization for prompt-string access in shell Resolved a data race in shell.c by copying the user-provided prompt-string into a private buffer within the shell, ensuring proper synchronization with the shell-thread. Fixes: #64972 Signed-off-by: Jakub Rzeszutko --- include/zephyr/shell/shell.h | 10 +++++++++- subsys/shell/Kconfig | 18 ++++++++++++++++++ subsys/shell/shell.c | 31 ++++++++++++++++++++++++++++--- 3 files changed, 55 insertions(+), 4 deletions(-) diff --git a/include/zephyr/shell/shell.h b/include/zephyr/shell/shell.h index 30b1654fdfd..91dd73a2d9b 100644 --- a/include/zephyr/shell/shell.h +++ b/include/zephyr/shell/shell.h @@ -26,6 +26,10 @@ extern "C" { #endif +#ifndef CONFIG_SHELL_PROMPT_BUFF_SIZE +#define CONFIG_SHELL_PROMPT_BUFF_SIZE 0 +#endif + #ifndef CONFIG_SHELL_CMD_BUFF_SIZE #define CONFIG_SHELL_CMD_BUFF_SIZE 0 #endif @@ -779,7 +783,11 @@ enum shell_signal { * @brief Shell instance context. */ struct shell_ctx { - const char *prompt; /*!< shell current prompt. */ +#if defined(CONFIG_SHELL_PROMPT_CHANGE) && CONFIG_SHELL_PROMPT_CHANGE + char prompt[CONFIG_SHELL_PROMPT_BUFF_SIZE]; /*!< shell current prompt. */ +#else + const char *prompt; +#endif enum shell_state state; /*!< Internal module state.*/ enum shell_receive_state receive_state;/*!< Escape sequence indicator.*/ diff --git a/subsys/shell/Kconfig b/subsys/shell/Kconfig index 618570af1e2..5921a56bb49 100644 --- a/subsys/shell/Kconfig +++ b/subsys/shell/Kconfig @@ -55,6 +55,24 @@ config SHELL_BACKSPACE_MODE_DELETE Some terminals send code: 0x08 (backspace) other 0x7F (delete). When this option is set shell will expect 0x7F for backspace key. +config SHELL_PROMPT_CHANGE + bool "Allow prompt change in runtime" + default y if !SHELL_MINIMAL + help + Allow for the modification of the shell prompt at runtime. + Enabling this will allocate additional RAM memory where + the string of the prompt will be stored. + +config SHELL_PROMPT_BUFF_SIZE + int "Shell prompt buffer size" + depends on SHELL_PROMPT_CHANGE + range 2 40 + default 10 if SHELL_MINIMAL + default 20 + help + Maximum prompt size in bytes. One byte is reserved for the string + terminator character. + config SHELL_CMD_BUFF_SIZE int "Shell command buffer size" default 128 if SHELL_MINIMAL diff --git a/subsys/shell/shell.c b/subsys/shell/shell.c index 9cbd8a7158a..1bd8de70d02 100644 --- a/subsys/shell/shell.c +++ b/subsys/shell/shell.c @@ -1208,7 +1208,6 @@ static int instance_init(const struct shell *sh, (sh->shell_flag == SHELL_FLAG_OLF_CRLF)); memset(sh->ctx, 0, sizeof(*sh->ctx)); - sh->ctx->prompt = sh->default_prompt; if (CONFIG_SHELL_CMD_ROOT[0]) { sh->ctx->selected_cmd = root_cmd_find(CONFIG_SHELL_CMD_ROOT); } @@ -1235,7 +1234,13 @@ static int instance_init(const struct shell *sh, CONFIG_SHELL_DEFAULT_TERMINAL_WIDTH; sh->ctx->vt100_ctx.cons.terminal_hei = CONFIG_SHELL_DEFAULT_TERMINAL_HEIGHT; + +#if defined(CONFIG_SHELL_PROMPT_CHANGE) && CONFIG_SHELL_PROMPT_CHANGE + shell_prompt_change(sh, sh->default_prompt); +#else + sh->ctx->prompt = sh->default_prompt; sh->ctx->vt100_ctx.cons.name_len = z_shell_strlen(sh->ctx->prompt); +#endif /* Configure backend according to enabled shell features and backend * specific settings. @@ -1614,15 +1619,35 @@ void shell_hexdump(const struct shell *sh, const uint8_t *data, size_t len) int shell_prompt_change(const struct shell *sh, const char *prompt) { +#if defined(CONFIG_SHELL_PROMPT_CHANGE) && CONFIG_SHELL_PROMPT_CHANGE __ASSERT_NO_MSG(sh); if (prompt == NULL) { return -EINVAL; } - sh->ctx->prompt = prompt; - sh->ctx->vt100_ctx.cons.name_len = z_shell_strlen(prompt); + + static const size_t mtx_timeout_ms = 20; + size_t prompt_length = z_shell_strlen(prompt); + + if (k_mutex_lock(&sh->ctx->wr_mtx, K_MSEC(mtx_timeout_ms))) { + return -EBUSY; + } + + if ((prompt_length + 1 > CONFIG_SHELL_PROMPT_BUFF_SIZE) || (prompt_length == 0)) { + k_mutex_unlock(&sh->ctx->wr_mtx); + return -EINVAL; + } + + strcpy(sh->ctx->prompt, prompt); + + sh->ctx->vt100_ctx.cons.name_len = prompt_length; + + k_mutex_unlock(&sh->ctx->wr_mtx); return 0; +#else + return -EPERM; +#endif } void shell_help(const struct shell *sh) From 554ed2235c52c2a9542ada3519cc0f0dcdb7a769 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Tue, 12 Mar 2024 21:26:53 +0000 Subject: [PATCH 1843/2402] drivers: sensor: mpu6050: Add support for MPU6500 Adds basic support for using this driver with a MPU6500 device Signed-off-by: Jamie McCrae --- drivers/sensor/tdk/mpu6050/mpu6050.c | 37 ++++++++++++++++++---------- drivers/sensor/tdk/mpu6050/mpu6050.h | 9 +++++++ 2 files changed, 33 insertions(+), 13 deletions(-) diff --git a/drivers/sensor/tdk/mpu6050/mpu6050.c b/drivers/sensor/tdk/mpu6050/mpu6050.c index f00ca138c78..ce8d157444f 100644 --- a/drivers/sensor/tdk/mpu6050/mpu6050.c +++ b/drivers/sensor/tdk/mpu6050/mpu6050.c @@ -40,19 +40,24 @@ static void mpu6050_convert_gyro(struct sensor_value *val, int16_t raw_val, } /* see "Temperature Measurement" section from register map description */ -static inline void mpu6050_convert_temp(struct sensor_value *val, +static inline void mpu6050_convert_temp(enum mpu6050_device_type device_type, + struct sensor_value *val, int16_t raw_val) { - val->val1 = raw_val / 340 + 36; - val->val2 = ((int64_t)(raw_val % 340) * 1000000) / 340 + 530000; - - if (val->val2 < 0) { - val->val1--; - val->val2 += 1000000; - } else if (val->val2 >= 1000000) { - val->val1++; - val->val2 -= 1000000; - } + int64_t tmp_val = (int64_t)raw_val * 1000000; + + switch (device_type) { + case DEVICE_TYPE_MPU6500: + tmp_val = (tmp_val * 1000 / 333870) + 21000000; + break; + + case DEVICE_TYPE_MPU6050: + default: + tmp_val = (tmp_val / 340) + 36000000; + }; + + val->val1 = tmp_val / 1000000; + val->val2 = tmp_val % 1000000; } static int mpu6050_channel_get(const struct device *dev, @@ -103,7 +108,7 @@ static int mpu6050_channel_get(const struct device *dev, drv_data->gyro_sensitivity_x10); break; case SENSOR_CHAN_DIE_TEMP: - mpu6050_convert_temp(val, drv_data->temp); + mpu6050_convert_temp(drv_data->device_type, val, drv_data->temp); break; default: return -ENOTSUP; @@ -161,7 +166,13 @@ int mpu6050_init(const struct device *dev) return -EIO; } - if ((id != MPU6050_CHIP_ID) && (id != MPU9250_CHIP_ID) && (id != MPU6880_CHIP_ID)) { + if (id == MPU6050_CHIP_ID || id == MPU9250_CHIP_ID || id == MPU6880_CHIP_ID) { + LOG_DBG("MPU6050/MPU9250/MPU6880 detected"); + drv_data->device_type = DEVICE_TYPE_MPU6050; + } else if (id == MPU6500_CHIP_ID) { + LOG_DBG("MPU6500 detected"); + drv_data->device_type = DEVICE_TYPE_MPU6500; + } else { LOG_ERR("Invalid chip ID."); return -EINVAL; } diff --git a/drivers/sensor/tdk/mpu6050/mpu6050.h b/drivers/sensor/tdk/mpu6050/mpu6050.h index 0bc20a5c070..9277873cd5f 100644 --- a/drivers/sensor/tdk/mpu6050/mpu6050.h +++ b/drivers/sensor/tdk/mpu6050/mpu6050.h @@ -16,6 +16,7 @@ #define MPU6050_REG_CHIP_ID 0x75 #define MPU6050_CHIP_ID 0x68 +#define MPU6500_CHIP_ID 0x70 #define MPU9250_CHIP_ID 0x71 #define MPU6880_CHIP_ID 0x19 @@ -38,6 +39,12 @@ static const uint16_t mpu6050_gyro_sensitivity_x10[] = { 1310, 655, 328, 164 }; +/* Device type, uses the correct offets for a particular device */ +enum mpu6050_device_type { + DEVICE_TYPE_MPU6050 = 0, + DEVICE_TYPE_MPU6500, +}; + struct mpu6050_data { int16_t accel_x; int16_t accel_y; @@ -51,6 +58,8 @@ struct mpu6050_data { int16_t gyro_z; uint16_t gyro_sensitivity_x10; + enum mpu6050_device_type device_type; + #ifdef CONFIG_MPU6050_TRIGGER const struct device *dev; struct gpio_callback gpio_cb; From dbd1da973be21dd261ad1befc58557683ff229db Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Tue, 26 Mar 2024 12:49:52 -0500 Subject: [PATCH 1844/2402] dts: arm: nxp: nxp_mcxn94x: Added watchdog node Added the dts node for the wdt watchdog and updated the clock frequency. Signed-off-by: Emilio Benavente --- drivers/watchdog/wdt_mcux_wwdt.c | 3 ++- dts/arm/nxp/nxp_mcxn94x_common.dtsi | 9 +++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/wdt_mcux_wwdt.c b/drivers/watchdog/wdt_mcux_wwdt.c index 55faafed874..cd24b1dc3e4 100644 --- a/drivers/watchdog/wdt_mcux_wwdt.c +++ b/drivers/watchdog/wdt_mcux_wwdt.c @@ -82,7 +82,8 @@ static int mcux_wwdt_install_timeout(const struct device *dev, return -ENOMEM; } -#if defined(CONFIG_SOC_MIMXRT685S_CM33) || defined(CONFIG_SOC_MIMXRT595S_CM33) +#if defined(CONFIG_SOC_MIMXRT685S_CM33) || defined(CONFIG_SOC_MIMXRT595S_CM33) \ + || defined(CONFIG_SOC_SERIES_MCXNX4X) clock_freq = CLOCK_GetWdtClkFreq(0); #elif defined(CONFIG_SOC_SERIES_RW6XX) clock_freq = CLOCK_GetWdtClkFreq(); diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi index 22ca3ffd928..ba9546bd961 100644 --- a/dts/arm/nxp/nxp_mcxn94x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi @@ -609,6 +609,15 @@ status = "disabled"; }; }; + + wwdt0: watchdog@16000 { + compatible = "nxp,lpc-wwdt"; + reg = <0x16000 0x1000>; + interrupts = <152 0>; + status = "disabled"; + clk-divider = <1>; + }; + }; &systick { From dc1ad210cbab968f2d828a58fa39d3b6baeb8a7b Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Tue, 26 Mar 2024 12:51:34 -0500 Subject: [PATCH 1845/2402] boards: nxp: frdm_mcxn947: Enabled Watchdog Enabled the watchdog for frdm_mcxn947 board. Signed-off-by: Emilio Benavente --- boards/nxp/frdm_mcxn947/board.c | 4 ++++ boards/nxp/frdm_mcxn947/doc/index.rst | 2 ++ boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts | 8 ++++++++ boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml | 1 + 4 files changed, 15 insertions(+) diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index 5e798a39758..484858f02dd 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -162,6 +162,10 @@ static int frdm_mcxn947_init(void) SYSCON->ENET_PHY_INTF_SEL = SYSCON_ENET_PHY_INTF_SEL_PHY_SEL(1); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(wwdt0), okay) + CLOCK_SetClkDiv(kCLOCK_DivWdt0Clk, 1u); +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index ee65714f14e..79f97f274dc 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -76,6 +76,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | ENET QOS | on-chip | ethernet | +-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ Targets available ================== diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts index 2f587614580..cbc18e92f0c 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts @@ -25,6 +25,10 @@ zephyr,console = &flexcomm4_lpuart4; zephyr,shell-uart = &flexcomm4_lpuart4; }; + + aliases{ + watchdog0 = &wwdt0; + }; }; /* @@ -124,3 +128,7 @@ &enet_mdio { status = "okay"; }; + +&wwdt0 { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml index 156451f0a10..1a4725a33ed 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -20,4 +20,5 @@ supported: - spi - dac - i2c + - watchdog vendor: nxp From e6a1337726422a9a22a60e689be9304e15b21a86 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 16:59:08 -0500 Subject: [PATCH 1846/2402] drivers: clock_control: clock_control_mcux_syscon: add LCDIC clock Add LCDIC clock support to MCUX SYSCON clock driver Signed-off-by: Daniel DeGrasse --- .../clock_control/clock_control_mcux_syscon.c | 18 ++++++++++++++++++ .../dt-bindings/clock/mcux_lpc_syscon_clock.h | 2 ++ 2 files changed, 20 insertions(+) diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index 2570600c204..45f2d9cf47f 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -37,6 +37,11 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev, } #endif #endif /* defined(CONFIG_COUNTER_NXP_MRT) */ +#if defined(CONFIG_MIPI_DBI_NXP_LCDIC) + if ((uint32_t)sub_system == MCUX_LCDIC_CLK) { + CLOCK_EnableClock(kCLOCK_Lcdic); + } +#endif #if defined(CONFIG_PINCTRL_NXP_KINETIS) switch ((uint32_t)sub_system) { @@ -287,6 +292,11 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( break; #endif +#if defined(CONFIG_MIPI_DBI_NXP_LCDIC) + case MCUX_LCDIC_CLK: + *rate = CLOCK_GetLcdClkFreq(); + break; +#endif } return 0; @@ -331,6 +341,14 @@ static int SYSCON_SET_FUNC_ATTR * which is SOC specific. */ return flexspi_clock_set_freq(clock_name, clock_rate); +#endif +#if defined(CONFIG_MIPI_DBI_NXP_LCDIC) + case MCUX_LCDIC_CLK: + /* Set LCDIC clock div */ + uint32_t root_rate = (CLOCK_GetLcdClkFreq() * + ((CLKCTL0->LCDFCLKDIV & CLKCTL0_LCDFCLKDIV_DIV_MASK) + 1)); + CLOCK_SetClkDiv(kCLOCK_DivLcdClk, (root_rate / clock_rate)); + return 0; #endif default: /* Silence unused variable warning */ diff --git a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h index 5416564ed1d..d3b974cb6d4 100644 --- a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -76,4 +76,6 @@ #define MCUX_ENET_QOS_CLK MCUX_LPC_CLK_ID(0x0D, 0x00) +#define MCUX_LCDIC_CLK MCUX_LPC_CLK_ID(0x0E, 0x00) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */ From 2ec7a8df3a15ea4befbf032bfe7e21dd83be7ae2 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 16:59:48 -0500 Subject: [PATCH 1847/2402] dts: bindings: add devicetree binding for NXP LCDIC Add devicetree binding for NXP LCDIC. This controller is capable of driving displays in 8080 or SPI 3/4 wire mode, and optionally swapping endianness of display data as it sends it. Signed-off-by: Daniel DeGrasse --- dts/bindings/mipi-dbi/nxp,lcdic.yaml | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 dts/bindings/mipi-dbi/nxp,lcdic.yaml diff --git a/dts/bindings/mipi-dbi/nxp,lcdic.yaml b/dts/bindings/mipi-dbi/nxp,lcdic.yaml new file mode 100644 index 00000000000..b8a38ba2c74 --- /dev/null +++ b/dts/bindings/mipi-dbi/nxp,lcdic.yaml @@ -0,0 +1,25 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: | + NXP LCDIC Controller. This controller implements 8080 and SPI mode MIPI-DBI + compliant transfers. Only SPI mode is currently supported. +compatible: "nxp,lcdic" + +include: ["mipi-dbi-controller.yaml", "pinctrl-device.yaml"] + +properties: + reg: + required: true + + interrupts: + required: true + + clocks: + required: true + + nxp,swap-bytes: + type: boolean + description: | + Swap bytes while transferring on LCDIC. When set, the LCDIC will send + the most significant byte first when using multibyte pixel formats. From 2206085cd8651cdc47d9c50f094dd2cf2b268783 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 17:02:09 -0500 Subject: [PATCH 1848/2402] drivers: mipi_dbi: introduce NXP LCDIC driver Introduce NXP LCDIC driver using MIPI DBI class. This peripheral supports 8080 and SPI 3/4 wire mode, although only SPI 4 wire support is currently implemented. The driver supports DMA and interrupt driven transfers. Signed-off-by: Daniel DeGrasse --- drivers/mipi_dbi/CMakeLists.txt | 2 +- drivers/mipi_dbi/Kconfig | 2 +- drivers/mipi_dbi/Kconfig.nxp_lcdic | 22 + drivers/mipi_dbi/mipi_dbi_nxp_lcdic.c | 797 ++++++++++++++++++++++++++ 4 files changed, 821 insertions(+), 2 deletions(-) create mode 100644 drivers/mipi_dbi/Kconfig.nxp_lcdic create mode 100644 drivers/mipi_dbi/mipi_dbi_nxp_lcdic.c diff --git a/drivers/mipi_dbi/CMakeLists.txt b/drivers/mipi_dbi/CMakeLists.txt index 133e24ca626..fbcdc4d177b 100644 --- a/drivers/mipi_dbi/CMakeLists.txt +++ b/drivers/mipi_dbi/CMakeLists.txt @@ -3,5 +3,5 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_sources_ifdef(CONFIG_MIPI_DBI_SPI mipi_dbi_spi.c) - zephyr_sources_ifdef(CONFIG_MIPI_DBI_SMARTBOND mipi_dbi_smartbond.c) +zephyr_sources_ifdef(CONFIG_MIPI_DBI_NXP_LCDIC mipi_dbi_nxp_lcdic.c) diff --git a/drivers/mipi_dbi/Kconfig b/drivers/mipi_dbi/Kconfig index 89eaa347b7d..16b7fc41c2d 100644 --- a/drivers/mipi_dbi/Kconfig +++ b/drivers/mipi_dbi/Kconfig @@ -22,7 +22,7 @@ config MIPI_DBI_INIT_PRIORITY MIPI-DBI Host Controllers initialization priority. source "drivers/mipi_dbi/Kconfig.spi" - source "drivers/mipi_dbi/Kconfig.smartbond" +source "drivers/mipi_dbi/Kconfig.nxp_lcdic" endif diff --git a/drivers/mipi_dbi/Kconfig.nxp_lcdic b/drivers/mipi_dbi/Kconfig.nxp_lcdic new file mode 100644 index 00000000000..b973619bfa3 --- /dev/null +++ b/drivers/mipi_dbi/Kconfig.nxp_lcdic @@ -0,0 +1,22 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +config MIPI_DBI_NXP_LCDIC + bool "NXP MIPI DBI LCDIC driver" + default y + depends on DT_HAS_NXP_LCDIC_ENABLED + depends on CLOCK_CONTROL + select PINCTRL + help + Enable support for NXP SPI LCDIC display controller driver + +if MIPI_DBI_NXP_LCDIC + +config MIPI_DBI_NXP_LCDIC_DMA + bool "Use DMA for transfers with LCDIC driver" + select DMA + help + Use DMA for transfers when sending data with the LCDIC driver. + Commands will still be sent in polling mode. + +endif # MIPI_DBI_NXP_LCDIC diff --git a/drivers/mipi_dbi/mipi_dbi_nxp_lcdic.c b/drivers/mipi_dbi/mipi_dbi_nxp_lcdic.c new file mode 100644 index 00000000000..3db7c7aef99 --- /dev/null +++ b/drivers/mipi_dbi/mipi_dbi_nxp_lcdic.c @@ -0,0 +1,797 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_lcdic + +#include +#include +#include +#include +#include +#include +#include +#include +LOG_MODULE_REGISTER(mipi_dbi_lcdic, CONFIG_MIPI_DBI_LOG_LEVEL); + +#include + +enum lcdic_data_fmt { + LCDIC_DATA_FMT_BYTE = 0, + LCDIC_DATA_FMT_HALFWORD = 1, /* 2 byte */ + LCDIC_DATA_FMT_WORD = 2, /* 4 byte */ +}; + +enum lcdic_cmd_dc { + LCDIC_COMMAND = 0, + LCDIC_DATA = 1, +}; + +enum lcdic_cmd_type { + LCDIC_RX = 0, + LCDIC_TX = 1, +}; + +/* Limit imposed by size of data length field in LCDIC command */ +#define LCDIC_MAX_XFER 0x40000 +/* Max reset width (in terms of Timer0_Period, see RST_CTRL register) */ +#define LCDIC_MAX_RST_WIDTH 0x3F + +/* Descriptor for LCDIC command */ +union lcdic_trx_cmd { + struct { + /* Data length in bytes. LCDIC transfers data_len + 1 */ + uint32_t data_len: 18; + /* Dummy SCLK cycles between TX and RX (for SPI mode) */ + uint32_t dummy_count: 3; + uint32_t rsvd: 2; + /* Use auto repeat mode */ + uint32_t auto_repeat: 1; + /* Tearing enable sync mode */ + uint32_t te_sync_mode: 2; + /* TRX command timeout mode */ + uint32_t trx_timeout_mode: 1; + /* Data format, see lcdic_data_fmt */ + uint32_t data_format: 2; + /* Enable command done interrupt */ + uint32_t cmd_done_int: 1; + /* LCD command or LCD data, see lcdic_cmd_dc */ + uint32_t cmd_data: 1; + /* TX or RX command, see lcdic_cmd_type */ + uint32_t trx: 1; + } bits; + uint32_t u32; +}; + +struct mipi_dbi_lcdic_config { + LCDIC_Type *base; + void (*irq_config_func)(const struct device *dev); + const struct pinctrl_dev_config *pincfg; + const struct device *clock_dev; + clock_control_subsys_t clock_subsys; + bool swap_bytes; +}; + +#ifdef CONFIG_MIPI_DBI_NXP_LCDIC_DMA +struct stream { + const struct device *dma_dev; + uint32_t channel; + struct dma_config dma_cfg; + struct dma_block_config blk_cfg[2]; +}; +#endif + +struct mipi_dbi_lcdic_data { + /* Tracks number of bytes remaining in command */ + uint32_t cmd_bytes; + /* Tracks number of bytes remaining in transfer */ + uint32_t xfer_bytes; + /* Tracks start of transfer buffer */ + const uint8_t *xfer_buf; + /* When sending data that does not evenly fit into 4 byte chunks, + * this is used to store the last unaligned segment of the data. + */ + uint32_t unaligned_word __aligned(4); + /* Tracks lcdic_data_fmt value we should use for pixel data */ + uint8_t pixel_fmt; + const struct mipi_dbi_config *active_cfg; + struct k_sem xfer_sem; + struct k_sem lock; +#ifdef CONFIG_MIPI_DBI_NXP_LCDIC_DMA + struct stream dma_stream; +#endif +}; + +#define LCDIC_ALL_INTERRUPTS \ + (LCDIC_ICR_RFIFO_THRES_INTR_CLR_MASK | \ + LCDIC_ICR_RFIFO_UNDERFLOW_INTR_CLR_MASK | \ + LCDIC_ICR_TFIFO_THRES_INTR_CLR_MASK | \ + LCDIC_ICR_TFIFO_OVERFLOW_INTR_CLR_MASK | \ + LCDIC_ICR_TE_TO_INTR_CLR_MASK | \ + LCDIC_ICR_CMD_TO_INTR_CLR_MASK | \ + LCDIC_ICR_CMD_DONE_INTR_CLR_MASK | \ + LCDIC_ICR_RST_DONE_INTR_CLR_MASK) + +/* RX and TX FIFO thresholds */ +#ifdef CONFIG_MIPI_DBI_NXP_LCDIC_DMA +#define LCDIC_RX_FIFO_THRESH 0x0 +#define LCDIC_TX_FIFO_THRESH 0x0 +#else +#define LCDIC_RX_FIFO_THRESH 0x0 +#define LCDIC_TX_FIFO_THRESH 0x3 +#endif + +/* Timer0 and Timer1 bases. We choose a longer timer0 base to enable + * long reset periods + */ +#define LCDIC_TIMER0_RATIO 0xF +#define LCDIC_TIMER1_RATIO 0x9 + +/* After LCDIC is enabled or disabled, there should be a wait longer than + * 5x the module clock before other registers are read + */ +static inline void mipi_dbi_lcdic_reset_delay(void) +{ + k_busy_wait(1); +} + +/* Resets state of the LCDIC TX/RX FIFO */ +static inline void mipi_dbi_lcdic_reset_state(const struct device *dev) +{ + const struct mipi_dbi_lcdic_config *config = dev->config; + LCDIC_Type *base = config->base; + + base->CTRL &= ~LCDIC_CTRL_LCDIC_EN_MASK; + mipi_dbi_lcdic_reset_delay(); + base->CTRL |= LCDIC_CTRL_LCDIC_EN_MASK; + mipi_dbi_lcdic_reset_delay(); +} + + +#ifdef CONFIG_MIPI_DBI_NXP_LCDIC_DMA + +/* Start DMA to send data using LCDIC TX FIFO */ +static int mipi_dbi_lcdic_start_dma(const struct device *dev) +{ + const struct mipi_dbi_lcdic_config *config = dev->config; + struct mipi_dbi_lcdic_data *data = dev->data; + struct stream *stream = &data->dma_stream; + uint32_t aligned_len = data->cmd_bytes & (~0x3); + uint32_t unaligned_len = data->cmd_bytes & 0x3; + int ret; + + stream->dma_cfg.head_block = &stream->blk_cfg[0]; + if (aligned_len == 0) { + /* Only unaligned data exists, send it in the first block */ + /* First DMA block configuration is used to send aligned data */ + stream->blk_cfg[0].source_address = (uint32_t)&data->unaligned_word; + stream->blk_cfg[0].dest_address = (uint32_t)&config->base->TFIFO_WDATA; + /* Block size should be the aligned portion of the transfer */ + stream->blk_cfg[0].block_size = sizeof(uint32_t); + stream->dma_cfg.block_count = 1; + stream->blk_cfg[0].next_block = NULL; + } else { + /* First DMA block configuration is used to send aligned data */ + stream->blk_cfg[0].source_address = (uint32_t)data->xfer_buf; + stream->blk_cfg[0].dest_address = (uint32_t)&config->base->TFIFO_WDATA; + /* Block size should be the aligned portion of the transfer */ + stream->blk_cfg[0].block_size = aligned_len; + /* Second DMA block configuration sends unaligned block */ + if (unaligned_len) { + stream->dma_cfg.block_count = 2; + stream->blk_cfg[0].next_block = + &stream->blk_cfg[1]; + stream->blk_cfg[1].source_address = + (uint32_t)&data->unaligned_word; + stream->blk_cfg[1].dest_address = + (uint32_t)&config->base->TFIFO_WDATA; + stream->blk_cfg[1].block_size = sizeof(uint32_t); + } else { + stream->dma_cfg.block_count = 1; + stream->blk_cfg[0].next_block = NULL; + } + } + + ret = dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg); + if (ret) { + return ret; + } + /* Enable DMA channel before we set up DMA request. This way, + * the hardware DMA trigger does not fire until the DMA + * start function has initialized the DMA. + */ + ret = dma_start(stream->dma_dev, stream->channel); + if (ret) { + return ret; + } + /* Enable DMA request */ + config->base->CTRL |= LCDIC_CTRL_DMA_EN_MASK; + return ret; +} + +/* DMA completion callback */ +static void mipi_dbi_lcdic_dma_callback(const struct device *dma_dev, + void *user_data, uint32_t channel, int status) +{ + if (status < 0) { + LOG_ERR("DMA callback with error %d", status); + } +} + +#endif /* CONFIG_MIPI_DBI_NXP_LCDIC_DMA */ + +/* Configure LCDIC */ +static int mipi_dbi_lcdic_configure(const struct device *dev, + const struct mipi_dbi_config *dbi_config) +{ + const struct mipi_dbi_lcdic_config *config = dev->config; + struct mipi_dbi_lcdic_data *data = dev->data; + const struct spi_config *spi_cfg = &dbi_config->config; + LCDIC_Type *base = config->base; + int ret; + uint32_t reg; + + if (dbi_config == data->active_cfg) { + return 0; + } + + /* Clear all interrupt flags */ + base->ICR = LCDIC_ALL_INTERRUPTS; + /* Mask all interrupts */ + base->IMR = LCDIC_ALL_INTERRUPTS; + + /* Set LCDIC clock frequency */ + ret = clock_control_set_rate(config->clock_dev, config->clock_subsys, + (clock_control_subsys_rate_t)spi_cfg->frequency); + if (ret) { + LOG_ERR("Invalid clock frequency %d", spi_cfg->frequency); + return ret; + } + if (!(spi_cfg->operation & SPI_HALF_DUPLEX)) { + LOG_ERR("LCDIC only supports half duplex operation"); + return -ENOTSUP; + } + if (spi_cfg->slave != 0) { + /* Only one slave select line */ + return -ENOTSUP; + } + if (SPI_WORD_SIZE_GET(spi_cfg->operation) > 8) { + LOG_ERR("Unsupported word size"); + return -ENOTSUP; + } + + reg = base->CTRL; + /* Disable LCD module during configuration */ + reg &= ~LCDIC_CTRL_LCDIC_EN_MASK; + /* Select SPI mode */ + reg &= ~LCDIC_CTRL_LCDIC_MD_MASK; + /* Select 3 or 4 wire mode based on config selection */ + if (dbi_config->mode == MIPI_DBI_MODE_SPI_4WIRE) { + reg |= LCDIC_CTRL_SPI_MD_MASK; + } else { + reg &= ~LCDIC_CTRL_SPI_MD_MASK; + } + /* Enable byte swapping if user requested it */ + reg = (reg & ~LCDIC_CTRL_DAT_ENDIAN_MASK) | + LCDIC_CTRL_DAT_ENDIAN(!config->swap_bytes); + /* Disable DMA */ + reg &= ~LCDIC_CTRL_DMA_EN_MASK; + base->CTRL = reg; + mipi_dbi_lcdic_reset_delay(); + + /* Setup SPI CPOL and CPHA selections */ + reg = base->SPI_CTRL; + reg = (reg & ~LCDIC_SPI_CTRL_SDAT_ENDIAN_MASK) | + LCDIC_SPI_CTRL_SDAT_ENDIAN((spi_cfg->operation & + SPI_TRANSFER_LSB) ? 1 : 0); + reg = (reg & ~LCDIC_SPI_CTRL_CPHA_MASK) | + LCDIC_SPI_CTRL_CPHA((spi_cfg->operation & SPI_MODE_CPHA) ? 1 : 0); + reg = (reg & ~LCDIC_SPI_CTRL_CPOL_MASK) | + LCDIC_SPI_CTRL_CPOL((spi_cfg->operation & SPI_MODE_CPOL) ? 1 : 0); + base->SPI_CTRL = reg; + + /* Enable the module */ + base->CTRL |= LCDIC_CTRL_LCDIC_EN_MASK; + mipi_dbi_lcdic_reset_delay(); + + data->active_cfg = dbi_config; + + return 0; +} + +/* Gets unaligned word data from array. Return value will be a 4 byte + * value containing the last unaligned section of the array data + */ +static uint32_t mipi_dbi_lcdic_get_unaligned(const uint8_t *bytes, + uint32_t buf_len) +{ + uint32_t word = 0U; + uint8_t unaligned_len = buf_len & 0x3; + uint32_t aligned_len = buf_len - unaligned_len; + + while ((unaligned_len--)) { + word <<= 8U; + word |= bytes[aligned_len + unaligned_len]; + } + return word; +} + +/* Fills the TX fifo with data. Returns number of bytes written. */ +static int mipi_dbi_lcdic_fill_tx(LCDIC_Type *base, const uint8_t *buf, + uint32_t buf_len, uint32_t last_word) +{ + uint32_t *word_buf = (uint32_t *)buf; + uint32_t bytes_written = 0U; + uint32_t write_len; + + /* TX FIFO consumes 4 bytes on each write, so we can write up + * to buf_len / 4 times before we send all data. + * Write to FIFO it overflows or we send entire buffer. + */ + while (buf_len) { + if (buf_len < 4) { + /* Send last bytes */ + base->TFIFO_WDATA = last_word; + write_len = buf_len; + } else { + /* Otherwise, write one word */ + base->TFIFO_WDATA = word_buf[bytes_written >> 2]; + write_len = 4; + } + if (base->IRSR & LCDIC_IRSR_TFIFO_OVERFLOW_RAW_INTR_MASK) { + /* TX FIFO has overflowed, last word write did not + * complete. Return current number of bytes written. + */ + base->ICR |= LCDIC_ICR_TFIFO_OVERFLOW_INTR_CLR_MASK; + return bytes_written; + } + bytes_written += write_len; + buf_len -= write_len; + } + return bytes_written; +} + +/* Writes command word */ +static void mipi_dbi_lcdic_set_cmd(LCDIC_Type *base, + enum lcdic_cmd_type dir, + enum lcdic_cmd_dc dc, + enum lcdic_data_fmt data_fmt, + uint32_t buf_len) +{ + union lcdic_trx_cmd cmd = {0}; + + + /* TX FIFO will be clear, write command word */ + cmd.bits.data_len = buf_len - 1; + cmd.bits.cmd_data = dc; + cmd.bits.trx = dir; + cmd.bits.cmd_done_int = true; + cmd.bits.data_format = data_fmt; + /* Write command */ + base->TFIFO_WDATA = cmd.u32; +} + +static int mipi_dbi_lcdic_write_display(const struct device *dev, + const struct mipi_dbi_config *dbi_config, + const uint8_t *framebuf, + struct display_buffer_descriptor *desc, + enum display_pixel_format pixfmt) +{ + const struct mipi_dbi_lcdic_config *config = dev->config; + struct mipi_dbi_lcdic_data *dev_data = dev->data; + LCDIC_Type *base = config->base; + int ret; + uint32_t interrupts = 0U; + + ret = k_sem_take(&dev_data->lock, K_FOREVER); + if (ret) { + goto out; + } + + ret = mipi_dbi_lcdic_configure(dev, dbi_config); + if (ret) { + goto out; + } + + /* State reset is required before transfer */ + mipi_dbi_lcdic_reset_state(dev); + + if (desc->buf_size != 0) { + dev_data->xfer_bytes = desc->buf_size; + /* Cap command to max transfer size */ + dev_data->cmd_bytes = MIN(desc->buf_size, LCDIC_MAX_XFER); + dev_data->xfer_buf = framebuf; + /* If the length of the transfer is not divisible by + * 4, save the unaligned portion of the transfer into + * a temporary buffer + */ + if (dev_data->cmd_bytes & 0x3) { + dev_data->unaligned_word = mipi_dbi_lcdic_get_unaligned( + dev_data->xfer_buf, + dev_data->cmd_bytes); + } + + /* Save pixel format */ + if (DISPLAY_BITS_PER_PIXEL(pixfmt) == 32) { + dev_data->pixel_fmt = LCDIC_DATA_FMT_WORD; + } else if (DISPLAY_BITS_PER_PIXEL(pixfmt) == 16) { + dev_data->pixel_fmt = LCDIC_DATA_FMT_HALFWORD; + } else if (DISPLAY_BITS_PER_PIXEL(pixfmt) == 8) { + dev_data->pixel_fmt = LCDIC_DATA_FMT_BYTE; + } else { + if (config->swap_bytes) { + LOG_WRN("Unsupported pixel format, byte swapping disabled"); + } + } + /* Use pixel format data width, so we can byte swap + * if needed + */ + mipi_dbi_lcdic_set_cmd(base, LCDIC_TX, LCDIC_DATA, + dev_data->pixel_fmt, + dev_data->cmd_bytes); +#ifdef CONFIG_MIPI_DBI_NXP_LCDIC_DMA + /* Enable command complete interrupt */ + interrupts |= LCDIC_IMR_CMD_DONE_INTR_MSK_MASK; + /* Write interrupt mask */ + base->IMR &= ~interrupts; + /* Configure DMA to send data */ + ret = mipi_dbi_lcdic_start_dma(dev); + if (ret) { + LOG_ERR("Could not start DMA (%d)", ret); + goto out; + } +#else + /* Enable TX FIFO threshold interrupt. This interrupt + * should fire once enabled, which will kick off + * the transfer + */ + interrupts |= LCDIC_IMR_TFIFO_THRES_INTR_MSK_MASK; + /* Enable command complete interrupt */ + interrupts |= LCDIC_IMR_CMD_DONE_INTR_MSK_MASK; + /* Write interrupt mask */ + base->IMR &= ~interrupts; +#endif + ret = k_sem_take(&dev_data->xfer_sem, K_FOREVER); + } +out: + k_sem_give(&dev_data->lock); + return ret; + +} + +static int mipi_dbi_lcdic_write_cmd(const struct device *dev, + const struct mipi_dbi_config *dbi_config, + uint8_t cmd, + const uint8_t *data, + size_t data_len) +{ + const struct mipi_dbi_lcdic_config *config = dev->config; + struct mipi_dbi_lcdic_data *dev_data = dev->data; + LCDIC_Type *base = config->base; + int ret; + uint32_t interrupts = 0U; + + ret = k_sem_take(&dev_data->lock, K_FOREVER); + if (ret) { + goto out; + } + + ret = mipi_dbi_lcdic_configure(dev, dbi_config); + if (ret) { + goto out; + } + + /* State reset is required before transfer */ + mipi_dbi_lcdic_reset_state(dev); + + /* Write command */ + mipi_dbi_lcdic_set_cmd(base, LCDIC_TX, LCDIC_COMMAND, + LCDIC_DATA_FMT_BYTE, 1); + /* Use standard byte writes */ + dev_data->pixel_fmt = LCDIC_DATA_FMT_BYTE; + base->TFIFO_WDATA = cmd; + /* Wait for command completion */ + while ((base->IRSR & LCDIC_IRSR_CMD_DONE_RAW_INTR_MASK) == 0) { + /* Spin */ + } + base->ICR |= LCDIC_ICR_CMD_DONE_INTR_CLR_MASK; + + if (data_len != 0) { + dev_data->xfer_bytes = data_len; + /* Cap command to max transfer size */ + dev_data->cmd_bytes = MIN(data_len, LCDIC_MAX_XFER); + dev_data->xfer_buf = data; + /* If the length of the transfer is not divisible by + * 4, save the unaligned portion of the transfer into + * a temporary buffer + */ + if (dev_data->cmd_bytes & 0x3) { + dev_data->unaligned_word = mipi_dbi_lcdic_get_unaligned( + dev_data->xfer_buf, + dev_data->cmd_bytes); + } + if (cmd == MIPI_DCS_WRITE_MEMORY_START) { + /* Use pixel format data width, so we can byte swap + * if needed + */ + mipi_dbi_lcdic_set_cmd(base, LCDIC_TX, LCDIC_DATA, + dev_data->pixel_fmt, + dev_data->cmd_bytes); + } else { + mipi_dbi_lcdic_set_cmd(base, LCDIC_TX, LCDIC_DATA, + LCDIC_DATA_FMT_BYTE, + dev_data->cmd_bytes); + } +#ifdef CONFIG_MIPI_DBI_NXP_LCDIC_DMA + if (((((uint32_t)dev_data->xfer_buf) & 0x3) == 0) || + (dev_data->cmd_bytes < 4)) { + /* Data is aligned, we can use DMA */ + /* Enable command complete interrupt */ + interrupts |= LCDIC_IMR_CMD_DONE_INTR_MSK_MASK; + /* Write interrupt mask */ + base->IMR &= ~interrupts; + /* Configure DMA to send data */ + ret = mipi_dbi_lcdic_start_dma(dev); + if (ret) { + LOG_ERR("Could not start DMA (%d)", ret); + goto out; + } + } else /* Data is not aligned */ +#endif + { + /* Enable TX FIFO threshold interrupt. This interrupt + * should fire once enabled, which will kick off + * the transfer + */ + interrupts |= LCDIC_IMR_TFIFO_THRES_INTR_MSK_MASK; + /* Enable command complete interrupt */ + interrupts |= LCDIC_IMR_CMD_DONE_INTR_MSK_MASK; + /* Write interrupt mask */ + base->IMR &= ~interrupts; + } + ret = k_sem_take(&dev_data->xfer_sem, K_FOREVER); + } +out: + k_sem_give(&dev_data->lock); + return ret; +} + +static int mipi_dbi_lcdic_reset(const struct device *dev, uint32_t delay) +{ + const struct mipi_dbi_lcdic_config *config = dev->config; + LCDIC_Type *base = config->base; + uint32_t lcdic_freq; + uint8_t rst_width, pulse_cnt; + + /* Calculate delay based off timer0 ratio. Formula given + * by RM is as follows: + * Reset pulse width = (RST_WIDTH + 1) * Timer0_Period + * Timer0_Period = 2^(TIMER_RATIO0) / LCDIC_Clock_Freq + */ + if (clock_control_get_rate(config->clock_dev, config->clock_subsys, + &lcdic_freq)) { + return -EIO; + } + rst_width = (delay * (lcdic_freq)) / + ((1 << LCDIC_TIMER0_RATIO) * MSEC_PER_SEC); + /* If rst_width is larger than max value supported by hardware, + * increase the pulse count (rounding up) + */ + pulse_cnt = ((rst_width + (LCDIC_MAX_RST_WIDTH - 1)) / LCDIC_MAX_RST_WIDTH); + rst_width = MIN(LCDIC_MAX_RST_WIDTH, rst_width); + + /* Start the reset signal */ + base->RST_CTRL = LCDIC_RST_CTRL_RST_WIDTH(rst_width - 1) | + LCDIC_RST_CTRL_RST_SEQ_NUM(pulse_cnt - 1) | + LCDIC_RST_CTRL_RST_START_MASK; + /* Wait for reset to complete */ + while ((base->IRSR & LCDIC_IRSR_RST_DONE_RAW_INTR_MASK) == 0) { + /* Spin */ + } + base->ICR |= LCDIC_ICR_RST_DONE_INTR_CLR_MASK; + return 0; +} + + + +/* Initializes LCDIC peripheral */ +static int mipi_dbi_lcdic_init(const struct device *dev) +{ + const struct mipi_dbi_lcdic_config *config = dev->config; + struct mipi_dbi_lcdic_data *data = dev->data; + LCDIC_Type *base = config->base; + int ret; + + ret = clock_control_on(config->clock_dev, config->clock_subsys); + if (ret) { + return ret; + } + + /* Set initial clock rate of 10 MHz */ + ret = clock_control_set_rate(config->clock_dev, config->clock_subsys, + (clock_control_subsys_rate_t)MHZ(10)); + if (ret) { + return ret; + } + + ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); + if (ret) { + return ret; + } + ret = k_sem_init(&data->xfer_sem, 0, 1); + if (ret) { + return ret; + } + ret = k_sem_init(&data->lock, 1, 1); + if (ret) { + return ret; + } + /* Clear all interrupt flags */ + base->ICR = LCDIC_ALL_INTERRUPTS; + /* Mask all interrupts */ + base->IMR = LCDIC_ALL_INTERRUPTS; + + /* Enable interrupts */ + config->irq_config_func(dev); + + /* Setup RX and TX fifo thresholds */ + base->FIFO_CTRL = LCDIC_FIFO_CTRL_RFIFO_THRES(LCDIC_RX_FIFO_THRESH) | + LCDIC_FIFO_CTRL_TFIFO_THRES(LCDIC_TX_FIFO_THRESH); + /* Disable command timeouts */ + base->TO_CTRL &= ~(LCDIC_TO_CTRL_CMD_LONG_TO_MASK | + LCDIC_TO_CTRL_CMD_SHORT_TO_MASK); + + /* Ensure LCDIC timer ratios are at reset values */ + base->TIMER_CTRL = LCDIC_TIMER_CTRL_TIMER_RATIO1(LCDIC_TIMER1_RATIO) | + LCDIC_TIMER_CTRL_TIMER_RATIO0(LCDIC_TIMER0_RATIO); + +#ifdef CONFIG_MIPI_DBI_NXP_LCDIC_DMA + /* Attach the LCDIC DMA request signal to the DMA channel we will + * use with hardware triggering. + */ + INPUTMUX_AttachSignal(INPUTMUX, data->dma_stream.channel, + kINPUTMUX_LcdTxRegToDmaSingleToDma0); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Dmac0InputTriggerLcdTxRegToDmaSingleEna, true); +#endif + + return 0; +} + +static struct mipi_dbi_driver_api mipi_dbi_lcdic_driver_api = { + .command_write = mipi_dbi_lcdic_write_cmd, + .write_display = mipi_dbi_lcdic_write_display, + .reset = mipi_dbi_lcdic_reset, +}; + +static void mipi_dbi_lcdic_isr(const struct device *dev) +{ + const struct mipi_dbi_lcdic_config *config = dev->config; + struct mipi_dbi_lcdic_data *data = dev->data; + LCDIC_Type *base = config->base; + uint32_t bytes_written, isr_status; + + isr_status = base->ISR; + /* Clear pending interrupts */ + base->ICR |= isr_status; + + if (isr_status & LCDIC_ISR_CMD_DONE_INTR_MASK) { + if (config->base->CTRL & LCDIC_CTRL_DMA_EN_MASK) { + /* DMA completed. Update buffer tracking data */ + data->xfer_bytes -= data->cmd_bytes; + data->xfer_buf += data->cmd_bytes; + /* Disable DMA request */ + config->base->CTRL &= ~LCDIC_CTRL_DMA_EN_MASK; + } + if (data->xfer_bytes == 0) { + /* Disable interrupts */ + base->IMR |= LCDIC_ALL_INTERRUPTS; + /* All data has been sent. */ + k_sem_give(&data->xfer_sem); + } else { + /* Command done. Queue next command */ + data->cmd_bytes = MIN(data->xfer_bytes, LCDIC_MAX_XFER); + mipi_dbi_lcdic_set_cmd(base, LCDIC_TX, LCDIC_DATA, + LCDIC_DATA_FMT_BYTE, + data->cmd_bytes); + if (data->cmd_bytes & 0x3) { + /* Save unaligned portion of transfer into + * a temporary buffer + */ + data->unaligned_word = mipi_dbi_lcdic_get_unaligned( + data->xfer_buf, + data->cmd_bytes); + } +#ifdef CONFIG_MIPI_DBI_NXP_LCDIC_DMA + if (((((uint32_t)data->xfer_buf) & 0x3) == 0) || + (data->cmd_bytes < 4)) { + /* Data is aligned. We can use DMA */ + mipi_dbi_lcdic_start_dma(dev); + } else +#endif + { + /* We must refill the FIFO here in order to continue + * the next transfer, since the TX FIFO threshold + * interrupt may have already fired. + */ + bytes_written = mipi_dbi_lcdic_fill_tx(base, data->xfer_buf, + data->cmd_bytes, + data->unaligned_word); + if (bytes_written > 0) { + data->xfer_buf += bytes_written; + data->cmd_bytes -= bytes_written; + data->xfer_bytes -= bytes_written; + } + } + } + } else if (isr_status & LCDIC_ISR_TFIFO_THRES_INTR_MASK) { + /* If command is not done, continue filling TX FIFO from + * current transfer buffer + */ + bytes_written = mipi_dbi_lcdic_fill_tx(base, data->xfer_buf, + data->cmd_bytes, + data->unaligned_word); + if (bytes_written > 0) { + data->xfer_buf += bytes_written; + data->cmd_bytes -= bytes_written; + data->xfer_bytes -= bytes_written; + } + } +} + +#ifdef CONFIG_MIPI_DBI_NXP_LCDIC_DMA +#define LCDIC_DMA_CHANNELS(n) \ + .dma_stream = { \ + .dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR(n)), \ + .channel = DT_INST_DMAS_CELL_BY_IDX(n, 0, channel), \ + .dma_cfg = { \ + .dma_slot = LPC_DMA_HWTRIG_EN | \ + LPC_DMA_TRIGPOL_HIGH_RISING | \ + LPC_DMA_TRIGBURST, \ + .channel_direction = MEMORY_TO_PERIPHERAL, \ + .dma_callback = mipi_dbi_lcdic_dma_callback, \ + .source_data_size = 4, \ + .dest_data_size = 4, \ + .user_data = (void *)DEVICE_DT_INST_GET(n), \ + }, \ + }, +#else +#define LCDIC_DMA_CHANNELS(n) +#endif + + +#define MIPI_DBI_LCDIC_INIT(n) \ + static void mipi_dbi_lcdic_config_func_##n( \ + const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ + mipi_dbi_lcdic_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + \ + irq_enable(DT_INST_IRQN(n)); \ + } \ + \ + PINCTRL_DT_INST_DEFINE(n); \ + static const struct mipi_dbi_lcdic_config \ + mipi_dbi_lcdic_config_##n = { \ + .base = (LCDIC_Type *)DT_INST_REG_ADDR(n), \ + .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clock_subsys = (clock_control_subsys_t) \ + DT_INST_CLOCKS_CELL(n, name), \ + .irq_config_func = mipi_dbi_lcdic_config_func_##n, \ + .swap_bytes = DT_INST_PROP(n, nxp_swap_bytes), \ + }; \ + static struct mipi_dbi_lcdic_data mipi_dbi_lcdic_data_##n = { \ + LCDIC_DMA_CHANNELS(n) \ + }; \ + DEVICE_DT_INST_DEFINE(n, mipi_dbi_lcdic_init, NULL, \ + &mipi_dbi_lcdic_data_##n, \ + &mipi_dbi_lcdic_config_##n, \ + POST_KERNEL, \ + CONFIG_MIPI_DBI_INIT_PRIORITY, \ + &mipi_dbi_lcdic_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(MIPI_DBI_LCDIC_INIT) From cc3de261aa485212923334f9925bc88945620a89 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 17:03:27 -0500 Subject: [PATCH 1849/2402] dts: arm: nxp_rw6xx: add LCDIC node Add LCDIC devicetree node or RW6xx SOC Signed-off-by: Daniel DeGrasse --- dts/arm/nxp/nxp_rw6xx_common.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index d91976e600c..0a1b8c53587 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -191,6 +191,17 @@ dma-channels = <33>; }; + lcdic: lcdic@128000 { + compatible = "nxp,lcdic"; + reg = <0x128000 0x52>; + interrupts = <61 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkctl1 MCUX_LCDIC_CLK>; + dmas = <&dma0 0>; + }; + ctimer0: ctimer@28000 { compatible = "nxp,lpc-ctimer"; reg = <0x28000 0x1000>; From b6477deb4a7961c2e476abb9b6d53282a101c059 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 17:42:35 -0500 Subject: [PATCH 1850/2402] soc: nxp: rw: add reset code for LCDIC Clear LCDIC reset signal at init when the LCDIC peripheral is enabled. Signed-off-by: Daniel DeGrasse --- soc/nxp/rw/soc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c index fc42797a09c..c372f32a425 100644 --- a/soc/nxp/rw/soc.c +++ b/soc/nxp/rw/soc.c @@ -218,6 +218,11 @@ __ramfunc void clock_init(void) CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 4); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lcdic), okay) && CONFIG_MIPI_DBI_NXP_LCDIC + CLOCK_AttachClk(kMAIN_CLK_to_LCD_CLK); + RESET_PeripheralReset(kLCDIC_RST_SHIFT_RSTn); +#endif + #ifdef CONFIG_COUNTER_MCUX_CTIMER #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ctimer0), nxp_lpc_ctimer, okay)) CLOCK_AttachClk(kSFRO_to_CTIMER0); From 049b2d86200537c915ba4d84c8c576b84298ee88 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 17:40:51 -0500 Subject: [PATCH 1851/2402] boards: nxp: rd_rw612_bga: add support for arduino header Add arduino header support for rd_rw612_bga, so this board can be used with arduino shields Signed-off-by: Daniel DeGrasse --- boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index 23e9d2429e7..c90f162a9dd 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -5,6 +5,8 @@ */ #include "rd_rw612_bga-pinctrl.dtsi" +#include + / { aliases { @@ -38,8 +40,38 @@ sw_4: sw_4 { label = "User SW4"; gpios = <&hsgpio0 25 0>; + zephyr,code = ; }; }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &hsgpio1 14 0>, /* A0 */ + <1 0 &hsgpio1 15 0>, /* A1 */ + <2 0 &hsgpio1 16 0>, /* A2 */ + <3 0 &hsgpio1 17 0>, /* A3 */ + <4 0 &hsgpio0 16 0>, /* A4 */ + <5 0 &hsgpio0 17 0>, /* A5 */ + <6 0 &hsgpio0 24 0>, /* D0 */ + <7 0 &hsgpio0 26 0>, /* D1 */ + <8 0 &hsgpio0 11 0>, /* D2 */ + <9 0 &hsgpio0 15 0>, /* D3 */ + <10 0 &hsgpio0 18 0>, /* D4 */ + <11 0 &hsgpio0 27 0>, /* D5 */ + <12 0 &hsgpio0 6 0>, /* D6 */ + <13 0 &hsgpio0 10 0>, /* D7 */ + <14 0 &hsgpio1 18 0>, /* D8 */ + <15 0 &hsgpio1 13 0>, /* D9 */ + <16 0 &hsgpio0 0 0>, /* D10 */ + <17 0 &hsgpio0 2 0>, /* D11 */ + <18 0 &hsgpio0 3 0>, /* D12 */ + <19 0 &hsgpio0 4 0>, /* D13 */ + <20 0 &hsgpio0 16 0>, /* D14 */ + <21 0 &hsgpio0 17 0>; /* D15 */ + }; }; &wwdt { From b530202871079db129bc4beabb11f9b47830440e Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Wed, 13 Mar 2024 17:41:28 -0500 Subject: [PATCH 1852/2402] boards: nxp: rd_rw612_bga: add support for LCDIC Enable support for LCDIC on rd_rw612_bga. This support also enables acceleration features such as DMA for LVGL, to improve performance Signed-off-by: Daniel DeGrasse --- boards/nxp/rd_rw612_bga/Kconfig.defconfig | 33 +++++++++++++++++++ boards/nxp/rd_rw612_bga/doc/index.rst | 2 ++ .../rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi | 12 +++++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 6 ++++ 4 files changed, 53 insertions(+) create mode 100644 boards/nxp/rd_rw612_bga/Kconfig.defconfig diff --git a/boards/nxp/rd_rw612_bga/Kconfig.defconfig b/boards/nxp/rd_rw612_bga/Kconfig.defconfig new file mode 100644 index 00000000000..713d8594e88 --- /dev/null +++ b/boards/nxp/rd_rw612_bga/Kconfig.defconfig @@ -0,0 +1,33 @@ +# RD_RW612_BGA board + +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RD_RW612_BGA + +if LVGL + +# Enable DMA for LCDIC +config MIPI_DBI_NXP_LCDIC_DMA + default y if MIPI_DBI + +# Increase descriptor count. LVGL will allocate a 30KB buffer, +# and the SPI driver sets up RX and TX side. Since LPC DMA has +# 1KB limit per descriptor, we need 60 +config DMA_MCUX_LPC_NUMBER_OF_DESCRIPTORS + default 60 + +# Allocate buffer that is 10% of screen size +config LV_Z_VDB_SIZE + default 10 + +# Enable double buffering and offloaded render thread to improve performance +config LV_Z_DOUBLE_VDB + default y + +config LV_Z_FLUSH_THREAD + default y + +endif # LVGL + +endif # BOARD_RD_RW612_BGA diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index 9f115e4445a..8e6202422c0 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -51,6 +51,8 @@ Supported Features +-----------+------------+-----------------------------------+ | DMIC | on-chip | dmic | +-----------+------------+-----------------------------------+ +| LCDIC | on-chip | mipi-dbi | ++-----------+------------+-----------------------------------+ | WWDT | on-chip | watchdog | +-----------+------------+-----------------------------------+ | CTIMER | on-chip | counter | diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi index f7b131a6285..04140e2a68c 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi @@ -42,6 +42,18 @@ }; }; + pinmux_lcdic: pinmux_lcdic { + group0 { + pinmux = , + , + , + , + , + ; + slew-rate = "ultra"; + }; + }; + pinmux_flexspi: pinmux_flexspi { group0 { pinmux = ; + pinctrl-names = "default"; +}; + &mrt0_channel0 { status = "okay"; }; From 20b7b6e1d46af2a5f02f9f3e1d7708f30871c0e6 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Thu, 22 Feb 2024 16:35:57 -0600 Subject: [PATCH 1853/2402] boards: shield: adafruit_2_8_tft_touch_v2: add support for RD_RW612_BGA Add support for the RD RW612 BGA board for the adafruit_2_8_tft_touch_v2 shield. This board uses a custom LCDIC MIPI DBI controller, which requires a specific board overlay to enable the shield. Signed-off-by: Daniel DeGrasse --- .../boards/rd_rw612_bga.overlay | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay b/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay new file mode 100644 index 00000000000..59136c9b45b --- /dev/null +++ b/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay @@ -0,0 +1,54 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + chosen { + zephyr,display = &ili9340; + }; + + /* + * RW612 uses LCDIC controller, which implements the MIPI DBI API + * directly and does not require the MIPI DBI SPI node + */ + /delete-node/ mipi_dbi; +}; + +&lcdic { + /* Byte swapping not supported for this display */ + /delete-property/ nxp,swap-bytes; + + /* + * Settings to connect this display: + * Populate the following resistors: + * - R125, R123, R12, R124, R15, R243, R239, R236, R233, R286, R246 + * Remove the following resistors: + * - R9, R11, R20, R19, R242, R241, R237, R235, R245 + * Short the following pins: + * - J5 1-2 + * Remove JP30 to disconnect Flexcomm SPI CS + * Display can be connected to Arduino header + */ + + ili9340: ili9340@0 { + compatible = "ilitek,ili9340"; + mipi-max-frequency = <15151515>; + duplex = ; + reg = <0>; + width = <320>; + height = <240>; + pixel-format = ; + rotation = <90>; + frmctr1 = [00 18]; + pwctrl1 = [23 00]; + vmctrl1 = [3e 28]; + vmctrl2 = [86]; + pgamctrl = [0f 31 2b 0c 0e 08 4e f1 37 07 10 03 0e 09 00]; + ngamctrl = [00 0e 14 03 11 07 31 c1 48 08 0f 0c 31 36 0f]; + }; + +}; From fbaf7dfdc1fba38c981946932b76fde81b403929 Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Tue, 2 Apr 2024 14:48:02 +0800 Subject: [PATCH 1854/2402] kernel: banner: use BUILD_VERSION only if not empty The `BUILD_VERSION` can be defined but empty when built without git, causing version to be missing from the banner: ``` *** Booting Zephyr OS build *** Hello World! qemu_riscv64 ``` Let's check if it is empty before using it, so that `KERNEL_VERSION_STRING`, which is generated independently with cmake can be used as a fallback: ``` *** Booting Zephyr OS build 3.5.0 *** Hello World! qemu_riscv64 ``` Signed-off-by: Yong Cong Sin --- kernel/banner.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/banner.c b/kernel/banner.c index 5274c3e0d6f..dc2506fb9b1 100644 --- a/kernel/banner.c +++ b/kernel/banner.c @@ -17,7 +17,7 @@ #endif /* defined(CONFIG_BOOT_DELAY) && (CONFIG_BOOT_DELAY > 0) */ #ifndef BANNER_VERSION -#ifdef BUILD_VERSION +#if defined(BUILD_VERSION) && !IS_EMPTY(BUILD_VERSION) #define BANNER_VERSION STRINGIFY(BUILD_VERSION) #else #define BANNER_VERSION KERNEL_VERSION_STRING From cd2c7874b95eed7505620534b4b216ef42b7ce2b Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Tue, 2 Apr 2024 14:56:37 +0800 Subject: [PATCH 1855/2402] posix: uname: use BUILD_VERSION only if not empty The `BUILD_VERSION` can be defined but empty when built without git, causing version to be missing from the uname version string: ``` *** Booting Zephyr OS build 3.5.0 *** Printing everything in utsname... sysname[7]: Zephyr nodename[7]: zephyr release[13]: 3.5.0 version[61]: Apr 1 2024 23:48:30 machine[8]: riscv64 uart:~$ ``` Let's check if it is empty before using it, so that `KERNEL_VERSION_STRING`, which is generated independently with cmake can be used as a fallback: ``` *** Booting Zephyr OS build 3.5.0 *** Printing everything in utsname... sysname[7]: Zephyr nodename[7]: zephyr release[13]: 3.5.0 version[61]: 3.5.0 Apr 1 2024 23:53:48 machine[8]: riscv64 uart:~$ ``` Signed-off-by: Yong Cong Sin --- lib/posix/options/uname.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/posix/options/uname.c b/lib/posix/options/uname.c index 107126f584e..eb1d9a3f463 100644 --- a/lib/posix/options/uname.c +++ b/lib/posix/options/uname.c @@ -22,7 +22,7 @@ #define UTSNAME_VERSION(_ver) _ver #endif -#ifdef BUILD_VERSION +#if defined(BUILD_VERSION) && !IS_EMPTY(BUILD_VERSION) #define VERSION_BUILD STRINGIFY(BUILD_VERSION) #else #define VERSION_BUILD KERNEL_VERSION_STRING From 97eb8bf78c9bf352b039cf6f82fb6c1d4b54d1aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 4 Apr 2024 17:04:27 +0200 Subject: [PATCH 1856/2402] mgmt: hawkbit: little cleanup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit a little cleanup in start_http_client(). Signed-off-by: Fin Maaß --- subsys/mgmt/hawkbit/hawkbit.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c index 26d930c51f9..b9357da1435 100644 --- a/subsys/mgmt/hawkbit/hawkbit.c +++ b/subsys/mgmt/hawkbit/hawkbit.c @@ -202,16 +202,9 @@ static bool start_http_client(void) { int ret = -1; struct zsock_addrinfo *addr; - struct zsock_addrinfo hints; + struct zsock_addrinfo hints = {0}; int resolve_attempts = 10; - -#if defined(CONFIG_NET_SOCKETS_SOCKOPT_TLS) - int protocol = IPPROTO_TLS_1_2; -#else - int protocol = IPPROTO_TCP; -#endif - - (void)memset(&hints, 0, sizeof(hints)); + int protocol = IS_ENABLED(CONFIG_NET_SOCKETS_SOCKOPT_TLS) ? IPPROTO_TLS_1_2 : IPPROTO_TCP; if (IS_ENABLED(CONFIG_NET_IPV6)) { hints.ai_family = AF_INET6; From 4867c56a51610519f7d9eb3bfc2f7ceff74b534b Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Wed, 3 Apr 2024 16:36:55 +0200 Subject: [PATCH 1857/2402] llext: invalidate instruction cache after loading extension In addition to flushing the dcache, to ensure that the new code is actually read by the CPU when loading an extension, the icache must be invalidated as well. Without this, some tests are failing in hardware because the CPU is executing stale code from its instruction cache. Fixes #70906 on arduino_giga_r1/stm32h747xx/m7. Signed-off-by: Luca Burelli --- subsys/llext/llext.c | 1 + 1 file changed, 1 insertion(+) diff --git a/subsys/llext/llext.c b/subsys/llext/llext.c index aaafe578f14..3a5a39ed7ee 100644 --- a/subsys/llext/llext.c +++ b/subsys/llext/llext.c @@ -801,6 +801,7 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local for (i = 0; i < LLEXT_MEM_COUNT; ++i) { if (ext->mem[i]) { sys_cache_data_flush_range(ext->mem[i], ext->mem_size[i]); + sys_cache_instr_invd_range(ext->mem[i], ext->mem_size[i]); } } #endif From e9dceed17394b417ba1d0b6c1617fd0dd34e368b Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Wed, 3 Apr 2024 08:59:04 +0000 Subject: [PATCH 1858/2402] doc: guidelines: add a note about ascii and emojis Add a note about source files encoding and emojis. Signed-off-by: Fabio Baltieri --- doc/contribute/guidelines.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/contribute/guidelines.rst b/doc/contribute/guidelines.rst index 06a70f0845d..564deb07418 100644 --- a/doc/contribute/guidelines.rst +++ b/doc/contribute/guidelines.rst @@ -459,6 +459,8 @@ exceptions: comment, ``//``, is not allowed. * Use ``/** */`` for doxygen comments that need to appear in the documentation. * Avoid using binary literals (constants starting with ``0b``). +* Avoid using non-ASCII symbols in code, unless it significantly improves + clarity, avoid emojis in any case. When there are differences between the guidelines above and the formatting generated by code formatting tools, the guidelines above take precedence. From 89c057a95a81b506cca80841b459fb71defdbf94 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 3 Apr 2024 10:05:57 +0200 Subject: [PATCH 1859/2402] mgmt: hawkbit: optimize poll_sleep MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit remove unnecessary condition for CONFIG_HAWKBIT_POLL_INTERVAL, changes poll_sleep to be in seconds, change type of sleep_time in hawkbit_update_sleep(), so the return value of hawkbit_time2sec() is interpreted correctly. Signed-off-by: Fin Maaß --- subsys/mgmt/hawkbit/hawkbit.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c index b9357da1435..69ee267023f 100644 --- a/subsys/mgmt/hawkbit/hawkbit.c +++ b/subsys/mgmt/hawkbit/hawkbit.c @@ -59,11 +59,7 @@ LOG_MODULE_REGISTER(hawkbit, CONFIG_HAWKBIT_LOG_LEVEL); #define STORAGE_DEV FIXED_PARTITION_DEVICE(STORAGE_LABEL) #define STORAGE_OFFSET FIXED_PARTITION_OFFSET(STORAGE_LABEL) -#if ((CONFIG_HAWKBIT_POLL_INTERVAL > 1) && (CONFIG_HAWKBIT_POLL_INTERVAL < 43200)) -static uint32_t poll_sleep = (CONFIG_HAWKBIT_POLL_INTERVAL * 60 * MSEC_PER_SEC); -#else -static uint32_t poll_sleep = (300 * MSEC_PER_SEC); -#endif +static uint32_t poll_sleep = (CONFIG_HAWKBIT_POLL_INTERVAL * SEC_PER_MIN); static struct nvs_fs fs; @@ -346,16 +342,16 @@ static int hawkbit_device_acid_update(int32_t new_value) */ static void hawkbit_update_sleep(struct hawkbit_ctl_res *hawkbit_res) { - uint32_t sleep_time; + int sleep_time; const char *sleep = hawkbit_res->config.polling.sleep; if (strlen(sleep) != HAWKBIT_SLEEP_LENGTH) { LOG_ERR("Invalid poll sleep: %s", sleep); } else { sleep_time = hawkbit_time2sec(sleep); - if (sleep_time > 0 && poll_sleep != (MSEC_PER_SEC * sleep_time)) { + if (sleep_time > 0 && poll_sleep != sleep_time) { LOG_DBG("New poll sleep %d seconds", sleep_time); - poll_sleep = sleep_time * MSEC_PER_SEC; + poll_sleep = (uint32_t)sleep_time; } } } @@ -1231,7 +1227,7 @@ static void autohandler(struct k_work *work) break; } - k_work_reschedule(&hawkbit_work_handle, K_MSEC(poll_sleep)); + k_work_reschedule(&hawkbit_work_handle, K_SECONDS(poll_sleep)); } void hawkbit_autohandler(void) From cc2898e6fe3085c8b188189ee6150637ccc4e5f3 Mon Sep 17 00:00:00 2001 From: Sreeram Tatapudi Date: Tue, 2 Apr 2024 15:19:22 -0700 Subject: [PATCH 1860/2402] modules: hal_infineon: wifi_host_driver: Fix blob case FIx the name of the cyw43xx_fw_bin Signed-off-by: Sreeram Tatapudi --- modules/hal_infineon/wifi-host-driver/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/modules/hal_infineon/wifi-host-driver/CMakeLists.txt b/modules/hal_infineon/wifi-host-driver/CMakeLists.txt index afdb147676d..010518f1642 100644 --- a/modules/hal_infineon/wifi-host-driver/CMakeLists.txt +++ b/modules/hal_infineon/wifi-host-driver/CMakeLists.txt @@ -113,8 +113,8 @@ if(CONFIG_CYW43439 AND NOT CONFIG_AIROC_WIFI_CUSTOM) set(cyw43xx_fw_bin ${hal_blobs_dir}/firmware/COMPONENT_43439/43439A0-mfgtest.bin) zephyr_library_sources(${hal_wifi_dir_resources}/firmware/COMPONENT_43439/43439A0-mfgtest_bin.c) else() - set(cyw43xx_fw_bin ${hal_blobs_dir}/firmware/COMPONENT_43439/43439A0.bin) - zephyr_library_sources(${hal_wifi_dir_resources}/firmware/COMPONENT_43439/43439A0_bin.c) + set(cyw43xx_fw_bin ${hal_blobs_dir}/firmware/COMPONENT_43439/43439a0.bin) + zephyr_library_sources(${hal_wifi_dir_resources}/firmware/COMPONENT_43439/43439a0_bin.c) endif() endif() From 83d879bb1a8573a152f75fc7f88916ad63736642 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 3 Apr 2024 09:47:19 +0300 Subject: [PATCH 1861/2402] net: if: No error if mcast group join fails because iface down If we fail to join all nodes or solicit node multicast groups when the interface is down, then there is no need to print an error message. The groups are automatically re-joined when the interface comes up. Signed-off-by: Jukka Rissanen --- subsys/net/ip/net_if.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 8b3d90aa284..a72470a434d 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -1104,7 +1104,7 @@ static void join_mcast_allnodes(struct net_if *iface) net_ipv6_addr_create_ll_allnodes_mcast(&addr); ret = net_ipv6_mld_join(iface, &addr); - if (ret < 0 && ret != -EALREADY) { + if (ret < 0 && ret != -EALREADY && ret != -ENETDOWN) { NET_ERR("Cannot join all nodes address %s for %d (%d)", net_sprint_ipv6_addr(&addr), net_if_get_by_iface(iface), ret); @@ -1121,10 +1121,12 @@ static void join_mcast_solicit_node(struct net_if *iface, net_ipv6_addr_create_solicited_node(my_addr, &addr); ret = net_ipv6_mld_join(iface, &addr); - if (ret < 0 && ret != -EALREADY) { - NET_ERR("Cannot join solicit node address %s for %d (%d)", - net_sprint_ipv6_addr(&addr), - net_if_get_by_iface(iface), ret); + if (ret < 0) { + if (ret != -EALREADY && ret != -ENETDOWN) { + NET_ERR("Cannot join solicit node address %s for %d (%d)", + net_sprint_ipv6_addr(&addr), + net_if_get_by_iface(iface), ret); + } } else { NET_DBG("Join solicit node address %s (ifindex %d)", net_sprint_ipv6_addr(&addr), From 83ccc8e29b2d4f2252226d5484afb2da15b18688 Mon Sep 17 00:00:00 2001 From: Lauren Murphy Date: Mon, 11 Mar 2024 13:20:41 -0700 Subject: [PATCH 1862/2402] llext: add threads and kernel object test case Tests threads and kernel objects with userspace. Includes cleanups suggested by Luca Burelli. Signed-off-by: Lauren Murphy --- tests/subsys/llext/simple/CMakeLists.txt | 2 +- .../llext/simple/src/test_llext_simple.c | 69 ++++++++++++++++--- .../simple/src/threads_kernel_objects_ext.c | 40 +++++++++++ .../simple/src/threads_kernel_objects_ext.h | 22 ++++++ 4 files changed, 123 insertions(+), 10 deletions(-) create mode 100644 tests/subsys/llext/simple/src/threads_kernel_objects_ext.c create mode 100644 tests/subsys/llext/simple/src/threads_kernel_objects_ext.h diff --git a/tests/subsys/llext/simple/CMakeLists.txt b/tests/subsys/llext/simple/CMakeLists.txt index e2618136b0a..f134a78c1f0 100644 --- a/tests/subsys/llext/simple/CMakeLists.txt +++ b/tests/subsys/llext/simple/CMakeLists.txt @@ -17,7 +17,7 @@ target_include_directories(app PRIVATE if(NOT LOADER_BUILD_ONLY) # generate extension targets foreach extension given by name -foreach(ext_name hello_world logging relative_jump object syscalls) +foreach(ext_name hello_world logging relative_jump object syscalls threads_kernel_objects) set(ext_src ${PROJECT_SOURCE_DIR}/src/${ext_name}_ext.c) set(ext_bin ${ZEPHYR_BINARY_DIR}/${ext_name}.llext) set(ext_inc ${ZEPHYR_BINARY_DIR}/include/generated/${ext_name}.inc) diff --git a/tests/subsys/llext/simple/src/test_llext_simple.c b/tests/subsys/llext/simple/src/test_llext_simple.c index 33f4b694ba9..90fadb68f12 100644 --- a/tests/subsys/llext/simple/src/test_llext_simple.c +++ b/tests/subsys/llext/simple/src/test_llext_simple.c @@ -7,11 +7,13 @@ #include #include #include +#include #include #include #include - #include "syscalls_ext.h" +#include "threads_kernel_objects_ext.h" + LOG_MODULE_REGISTER(test_llext_simple); @@ -28,8 +30,9 @@ struct llext_test { size_t buf_len; LLEXT_CONST uint8_t *buf; -}; + void (*perm_setup)(struct k_thread *llext_thread); +}; K_THREAD_STACK_DEFINE(llext_stack, 1024); @@ -45,6 +48,9 @@ void llext_entry(void *arg0, void *arg1, void *arg2) } #endif /* CONFIG_USERSPACE */ + +/* syscalls test */ + int z_impl_ext_syscall_ok(int a) { return a + 1; @@ -58,6 +64,33 @@ static inline int z_vrfy_ext_syscall_ok(int a) #include #endif /* CONFIG_USERSPACE */ + +/* threads kernel objects test */ + +/* For these to be accessible from user space, they must be top-level globals + * in the Zephyr image. Also, macros that add objects to special linker sections, + * such as K_THREAD_STACK_DEFINE, do not work properly from extensions code. + */ +K_SEM_DEFINE(my_sem, 1, 1); +EXPORT_SYMBOL(my_sem); +struct k_thread my_thread; +EXPORT_SYMBOL(my_thread); +K_THREAD_STACK_DEFINE(my_thread_stack, MY_THREAD_STACK_SIZE); +EXPORT_SYMBOL(my_thread_stack); + +#ifdef CONFIG_USERSPACE +/* Allow the user space test thread to access global objects */ +static void threads_objects_perm_setup(struct k_thread *llext_thread) +{ + k_object_access_grant(&my_sem, llext_thread); + k_object_access_grant(&my_thread, llext_thread); + k_object_access_grant(&my_thread_stack, llext_thread); +} +#else +/* No need to set up permissions for supervisor mode */ +#define threads_objects_perm_setup NULL +#endif /* CONFIG_USERSPACE */ + void load_call_unload(struct llext_test *test_case) { struct llext_buf_loader buf_loader = @@ -108,6 +141,14 @@ void load_call_unload(struct llext_test *test_case) k_mem_domain_add_thread(&domain, &llext_thread); + /* Even in supervisor mode, initialize permissions on objects used in + * the test by this thread, so that user mode descendant threads can + * inherit these permissions. + */ + if (test_case->perm_setup) { + test_case->perm_setup(&llext_thread); + } + k_thread_start(&llext_thread); k_thread_join(&llext_thread, K_FOREVER); @@ -123,11 +164,14 @@ void load_call_unload(struct llext_test *test_case) k_mem_domain_add_thread(&domain, &llext_thread); + if (test_case->perm_setup) { + test_case->perm_setup(&llext_thread); + } + k_thread_start(&llext_thread); k_thread_join(&llext_thread, K_FOREVER); } - #else /* CONFIG_USERSPACE */ zassert_ok(llext_call_fn(ext, "test_entry"), "test_entry call should succeed"); @@ -143,7 +187,7 @@ void load_call_unload(struct llext_test *test_case) * unloading each extension which may itself excercise various APIs provided by * Zephyr. */ -#define LLEXT_LOAD_UNLOAD(_name, _userspace) \ +#define LLEXT_LOAD_UNLOAD(_name, _userspace, _perm_setup) \ ZTEST(llext, test_load_unload_##_name) \ { \ struct llext_test test_case = { \ @@ -151,35 +195,42 @@ void load_call_unload(struct llext_test *test_case) .try_userspace = _userspace, \ .buf_len = ARRAY_SIZE(_name ## _ext), \ .buf = _name ## _ext, \ + .perm_setup = _perm_setup, \ }; \ load_call_unload(&test_case); \ } static LLEXT_CONST uint8_t hello_world_ext[] __aligned(4) = { #include "hello_world.inc" }; -LLEXT_LOAD_UNLOAD(hello_world, false) +LLEXT_LOAD_UNLOAD(hello_world, false, NULL) static LLEXT_CONST uint8_t logging_ext[] __aligned(4) = { #include "logging.inc" }; -LLEXT_LOAD_UNLOAD(logging, true) +LLEXT_LOAD_UNLOAD(logging, true, NULL) static LLEXT_CONST uint8_t relative_jump_ext[] __aligned(4) = { #include "relative_jump.inc" }; -LLEXT_LOAD_UNLOAD(relative_jump, true) +LLEXT_LOAD_UNLOAD(relative_jump, true, NULL) static LLEXT_CONST uint8_t object_ext[] __aligned(4) = { #include "object.inc" }; -LLEXT_LOAD_UNLOAD(object, true) +LLEXT_LOAD_UNLOAD(object, true, NULL) static LLEXT_CONST uint8_t syscalls_ext[] __aligned(4) = { #include "syscalls.inc" }; -LLEXT_LOAD_UNLOAD(syscalls, true) +LLEXT_LOAD_UNLOAD(syscalls, true, NULL) + +static LLEXT_CONST uint8_t threads_kernel_objects_ext[] __aligned(4) = { + #include "threads_kernel_objects.inc" +}; +LLEXT_LOAD_UNLOAD(threads_kernel_objects, true, threads_objects_perm_setup) #endif /* ! LOADER_BUILD_ONLY */ + /* * Ensure that EXPORT_SYMBOL does indeed provide a symbol and a valid address * to it. diff --git a/tests/subsys/llext/simple/src/threads_kernel_objects_ext.c b/tests/subsys/llext/simple/src/threads_kernel_objects_ext.c new file mode 100644 index 00000000000..21ca839efc4 --- /dev/null +++ b/tests/subsys/llext/simple/src/threads_kernel_objects_ext.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2023 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This code demonstrates the use of threads and requires object + * relocation support. + */ + +#include +#include +#include +#include "threads_kernel_objects_ext.h" + +void test_thread(void *arg0, void *arg1, void *arg2) +{ + printk("Take semaphore from test thread\n"); + k_sem_take(&my_sem, K_FOREVER); +} + +void test_entry(void) +{ + printk("Give semaphore from main thread\n"); + k_sem_give(&my_sem); + + printk("Creating thread\n"); + k_tid_t tid = k_thread_create(&my_thread, (k_thread_stack_t *) &my_thread_stack, + MY_THREAD_STACK_SIZE, &test_thread, NULL, NULL, NULL, + MY_THREAD_PRIO, MY_THREAD_OPTIONS, K_FOREVER); + + printk("Starting thread\n"); + k_thread_start(tid); + + printk("Joining thread\n"); + k_thread_join(&my_thread, K_FOREVER); + printk("Test thread joined\n"); +} +LL_EXTENSION_SYMBOL(test_entry); diff --git a/tests/subsys/llext/simple/src/threads_kernel_objects_ext.h b/tests/subsys/llext/simple/src/threads_kernel_objects_ext.h new file mode 100644 index 00000000000..d14c7cc9e9d --- /dev/null +++ b/tests/subsys/llext/simple/src/threads_kernel_objects_ext.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +extern struct k_thread my_thread; +#define MY_THREAD_STACK_SIZE 1024 +extern struct z_thread_stack_element my_thread_stack[]; + +extern struct k_sem my_sem; + +#ifdef CONFIG_USERSPACE +#define MY_THREAD_PRIO 1 +#define MY_THREAD_OPTIONS (K_USER | K_INHERIT_PERMS) +#else +#define MY_THREAD_PRIO 0 +#define MY_THREAD_OPTIONS 0 +#endif From 8590f6a469d38108432d0695600353cc1354cc9a Mon Sep 17 00:00:00 2001 From: Lauren Murphy Date: Wed, 3 Apr 2024 15:57:21 -0700 Subject: [PATCH 1863/2402] checkpatch: ignore EXPORT_SYMBOL checkpatch isn't smart enough to detect a function / variable has been declared e.g. with K_SEM_DEFINE and will incorrectly flag such cases. Signed-off-by: Lauren Murphy --- .checkpatch.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/.checkpatch.conf b/.checkpatch.conf index b68d702e453..accee08b149 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -29,3 +29,4 @@ --ignore MULTISTATEMENT_MACRO_USE_DO_WHILE --ignore ENOSYS --ignore IS_ENABLED_CONFIG +--ignore EXPORT_SYMBOL From 68c0c55419394084c4bd106a76ac9c1772b31a2d Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Wed, 27 Mar 2024 16:04:39 -0700 Subject: [PATCH 1864/2402] doc: pm: Clarify a device pm note Clarify conditions that prevent the cpu to enter low power state. Fixes #69647 Signed-off-by: Flavio Ceolin --- doc/services/pm/device.rst | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/doc/services/pm/device.rst b/doc/services/pm/device.rst index 094297eeea8..773ce0a6901 100644 --- a/doc/services/pm/device.rst +++ b/doc/services/pm/device.rst @@ -105,9 +105,14 @@ It is important to emphasize that this method has drawbacks (see above) and .. note:: - When using this method of device power management, the CPU will enter - a low power state only if no devices are in the middle of a hardware - transaction that cannot be interrupted. + When using this method of device power management, the CPU will not + enter a low-power state if a device cannot be suspended. For example, + if a device returns an error such as ``-EBUSY`` in response to the + ``PM_DEVICE_ACTION_SUSPEND`` action, indicating it is in the middle of + a transaction that cannot be interrupted. Another condition that + prevents the CPU from entering a low-power state is if the option + :kconfig:option:`CONFIG_PM_NEED_ALL_DEVICES_IDLE` is set and a device + is marked as busy. .. note:: From 3186c70e418d8ae7a5a57ac01277a75b6646e112 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Fri, 26 Jan 2024 00:38:34 +0530 Subject: [PATCH 1865/2402] hostap: Fix the disconnect wait timeout The timeout should be 5s, not 50s. Fix and rename the variables to better reflect their meaning. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index afa6c052f14..cb8bb75ecaf 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -104,11 +104,13 @@ static struct wpa_supplicant *get_wpa_s_handle(const struct device *dev) return wpa_s; } +#define WPA_SUPP_STATE_POLLING_MS 10 static int wait_for_disconnect_complete(const struct device *dev) { int ret = 0; - int timeout = 0; + int attempts = 0; struct wpa_supplicant *wpa_s = get_wpa_s_handle(dev); + unsigned int max_attempts = DISCONNECT_TIMEOUT_MS / WPA_SUPP_STATE_POLLING_MS; if (!wpa_s) { ret = -ENODEV; @@ -117,14 +119,13 @@ static int wait_for_disconnect_complete(const struct device *dev) } while (wpa_s->wpa_state != WPA_DISCONNECTED) { - if (timeout > DISCONNECT_TIMEOUT_MS) { + if (attempts++ > max_attempts) { ret = -ETIMEDOUT; wpa_printf(MSG_WARNING, "Failed to disconnect from network"); break; } - k_sleep(K_MSEC(10)); - timeout++; + k_sleep(K_MSEC(WPA_SUPP_STATE_POLLING_MS)); } out: return ret; From 2f29c1057ffe7cd48406038129cf70743eaae850 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Thu, 8 Feb 2024 23:02:54 +0530 Subject: [PATCH 1866/2402] hostap: Reserve the heap By default (-1) libc uses all the available heap, this is good to efficiently use the RAM, but for scenarios which there isn't enough RAM the build will be success, but we see runtime failures. Reserved the necessary RAM based on tests ahead to catch such scenarios, of course this would mean that we might be no using full RAM in case more is left, but that's never the case the with Wi-Fi :). And this also adds the constant evaluation and fine tuneing like we do for kernel heap and other parameters. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 472857caf12..0ce291bdc9c 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -16,11 +16,16 @@ config WIFI_NM_WPA_SUPPLICANT select NET_L2_WIFI_MGMT select WIFI_NM select EXPERIMENTAL + select COMMON_LIBC_MALLOC help WPA supplicant as a network management backend for WIFI_NM. if WIFI_NM_WPA_SUPPLICANT +config COMMON_LIBC_MALLOC_ARENA_SIZE + # 30K is mandatory, but might need more for long duration use cases + default 30000 + config WIFI_NM_WPA_SUPPLICANT_THREAD_STACK_SIZE int "Stack size for wpa_supplicant thread" default 8192 From 58efe79683985acd1b8881af1d284ccf79f4cb66 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Fri, 16 Feb 2024 01:58:48 +0530 Subject: [PATCH 1867/2402] hostap: Fix key management for SAP Key management for SAP should be retrieved from the network block rather than using the per-interface global structure. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index cb8bb75ecaf..82ed562a0f6 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -648,6 +648,7 @@ int supplicant_status(const struct device *dev, struct wifi_iface_status *status struct status_resp cli_status; bool is_ap; int proto; + int key_mgmt; if (!ssid) { wpa_printf(MSG_ERROR, "Failed to get current ssid"); @@ -657,9 +658,10 @@ int supplicant_status(const struct device *dev, struct wifi_iface_status *status is_ap = ssid->mode == WPAS_MODE_AP; /* For AP its always the configured one */ proto = is_ap ? ssid->proto : wpa_s->wpa_proto; + key_mgmt = is_ap ? ssid->key_mgmt : wpa_s->key_mgmt; os_memcpy(status->bssid, wpa_s->bssid, WIFI_MAC_ADDR_LEN); status->band = wpas_band_to_zephyr(wpas_freq_to_band(wpa_s->assoc_freq)); - status->security = wpas_key_mgmt_to_zephyr(wpa_s->key_mgmt, proto); + status->security = wpas_key_mgmt_to_zephyr(key_mgmt, proto); status->mfp = ssid->ieee80211w; /* Same mapping */ ieee80211_freq_to_chan(wpa_s->assoc_freq, &channel); status->channel = channel; From acd0aa7bb3a1c62e9ec066c910ee85a224e55037 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20B=C3=B8e?= Date: Mon, 12 Feb 2024 11:00:43 +0100 Subject: [PATCH 1868/2402] hostap: Add missing deps in WPA_SUPP_CRYPTO_ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing MBEDTLS_PK_C dependcy for legacy crypto. Signed-off-by: Sebastian Bøe Signed-off-by: Markus Swarowsky Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 0ce291bdc9c..7dc222f43de 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -114,6 +114,7 @@ config WIFI_NM_WPA_SUPPLICANT_CRYPTO select MBEDTLS_ECP_ALL_ENABLED select MBEDTLS_PKCS5_C select MBEDTLS_MAC_CMAC_ENABLED + select MBEDTLS_PK_C # select MBEDTLS_CIPHER_MODE_CBC # select MBEDTLS_CIPHER_MODE_CTR # select MBEDTLS_LEGACY_CRYPTO_C From 6f5d50fec90493baaae577510522fa5a36d7ef17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vidar=20Lilleb=C3=B8?= Date: Tue, 13 Feb 2024 12:42:12 +0100 Subject: [PATCH 1869/2402] hostap: Select MBEDTLS_PKCS5_C MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For WPA_SUPP_CRYPTO_LEGACY, MBEDTLS_PKCS5_C is needed. Signed-off-by: Vidar Lillebø Signed-off-by: Markus Swarowsky Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 7dc222f43de..086692b514d 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -115,6 +115,8 @@ config WIFI_NM_WPA_SUPPLICANT_CRYPTO select MBEDTLS_PKCS5_C select MBEDTLS_MAC_CMAC_ENABLED select MBEDTLS_PK_C + select MBEDTLS_PKCS5_C + select MBEDTLS_CIPHER_PADDING_PKCS7 # select MBEDTLS_CIPHER_MODE_CBC # select MBEDTLS_CIPHER_MODE_CTR # select MBEDTLS_LEGACY_CRYPTO_C From dbb5914f9516ec1c9b9641001500b72521094b2b Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Fri, 16 Feb 2024 02:34:43 +0530 Subject: [PATCH 1870/2402] hostap: Free the buffer for TX status Now that TX status buffer is allocated on heap by Zephyr driver, free the buffer once its processed. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 572d2b4a716..412b8824787 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -455,6 +455,8 @@ static void event_socket_handler(int sock, void *eloop_ctx, void *user_data) os_free((char *)data->auth.ies); } else if (msg.event == EVENT_RX_MGMT) { os_free((char *)data->rx_mgmt.frame); + } else if (msg.event == EVENT_TX_STATUS) { + os_free((char *)data->tx_status.data); } os_free(msg.data); From 86c3e0ade450b1e9ccd1288989c7284e3c67d446 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 19 Feb 2024 01:45:48 +0530 Subject: [PATCH 1871/2402] hostap: SAP mode needs more heap SAP mode adds more functionality that increases the heap usage, based on experiments, 40000 works well to avoid startup failures. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 086692b514d..b5d1a525854 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -23,6 +23,7 @@ config WIFI_NM_WPA_SUPPLICANT if WIFI_NM_WPA_SUPPLICANT config COMMON_LIBC_MALLOC_ARENA_SIZE + default 40000 if WIFI_NM_WPA_SUPPLICANT_AP # 30K is mandatory, but might need more for long duration use cases default 30000 From df70640f60b6aa6a5e608932570d6438f1e04eaf Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Fri, 23 Feb 2024 12:47:36 +0530 Subject: [PATCH 1872/2402] hostap: Limit only to WPA2 for SAP Due to AP-MLME being in the host and expensive computation WPA3 is not working reliably, so, for now this is being disabled. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 82ed562a0f6..20a557dc84e 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -377,6 +377,14 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, } if (params->security != WIFI_SECURITY_TYPE_NONE) { + /* SAP - only open and WPA2-PSK are supported for now */ + if (mode_ap && params->security != WIFI_SECURITY_TYPE_PSK) { + ret = -1; + wpa_printf(MSG_ERROR, "Unsupported security type: %d", + params->security); + goto rem_net; + } + /* Except for WPA-PSK, rest all are under WPA2 */ if (params->security != WIFI_SECURITY_TYPE_WPA_PSK) { if (!wpa_cli_cmd_v("set_network %d proto RSN", From d777c8654fcd0e7c5dff303efe4c32974407b106 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 27 Feb 2024 00:02:04 +0530 Subject: [PATCH 1873/2402] hostap: Add return value checks for interface removal These were missed earlier, and if event send fails, no point in waiting for the state to change. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_main.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 412b8824787..2b12fcf0b4b 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -288,7 +288,15 @@ static int del_interface(struct supplicant_context *ctx, struct net_if *iface) msg.event = EVENT_INTERFACE_STATUS; msg.data = event; - send_event(&msg); + ret = send_event(&msg); + if (ret) { + /* We failed notify WPA supplicant about interface removal. + * There is not much we can do, interface is still registered + * with WPA supplicant so we cannot unregister NM etc. + */ + wpa_printf(MSG_ERROR, "Failed to send event: %d", ret); + goto out; + } while (retry++ < count && wpa_s->wpa_state != WPA_INTERFACE_DISABLED) { k_sleep(K_MSEC(IFACE_NOTIFY_RETRY_MS)); From 26418cba142d654e0b2a8c57f8ca8f43137f02be Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 27 Feb 2024 00:18:46 +0530 Subject: [PATCH 1874/2402] hostap: Fix interface name copy in removal Using a macro here that can potentially limit the interface name compared to add can lead to issues, so, to mimic what we do in add, use the sizeof with a boundary check. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_main.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 2b12fcf0b4b..3c773648aa1 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -280,7 +280,13 @@ static int del_interface(struct supplicant_context *ctx, struct net_if *iface) supplicant_generate_state_event(ifname, NET_EVENT_SUPPLICANT_CMD_IFACE_REMOVING, 0); - os_memcpy(event->interface_status.ifname, ifname, IFNAMSIZ); + if (sizeof(event->interface_status.ifname) < strlen(ifname)) { + wpa_printf(MSG_ERROR, "Interface name too long: %s (max: %d)", + ifname, sizeof(event->interface_status.ifname)); + goto out; + } + + os_memcpy(event->interface_status.ifname, ifname, strlen(ifname)); event->interface_status.ievent = EVENT_INTERFACE_REMOVED; msg.global = true; From fa2b192df4200baa60d99881f6d49f6e4b16db22 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Sun, 25 Feb 2024 20:53:28 +0530 Subject: [PATCH 1875/2402] hostap: Free association response event deep copy Free the deep copied data of the association response event. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_main.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 3c773648aa1..69a4dd8438b 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -471,6 +471,26 @@ static void event_socket_handler(int sock, void *eloop_ctx, void *user_data) os_free((char *)data->rx_mgmt.frame); } else if (msg.event == EVENT_TX_STATUS) { os_free((char *)data->tx_status.data); + } else if (msg.event == EVENT_ASSOC) { + os_free((char *)data->assoc_info.addr); + os_free((char *)data->assoc_info.req_ies); + os_free((char *)data->assoc_info.resp_ies); + os_free((char *)data->assoc_info.resp_frame); + } else if (msg.event == EVENT_ASSOC_REJECT) { + os_free((char *)data->assoc_reject.bssid); + os_free((char *)data->assoc_reject.resp_ies); + } else if (msg.event == EVENT_DEAUTH) { + os_free((char *)data->deauth_info.addr); + os_free((char *)data->deauth_info.ie); + } else if (msg.event == EVENT_DISASSOC) { + os_free((char *)data->disassoc_info.addr); + os_free((char *)data->disassoc_info.ie); + } else if (msg.event == EVENT_UNPROT_DEAUTH) { + os_free((char *)data->unprot_deauth.sa); + os_free((char *)data->unprot_deauth.da); + } else if (msg.event == EVENT_UNPROT_DISASSOC) { + os_free((char *)data->unprot_disassoc.sa); + os_free((char *)data->unprot_disassoc.da); } os_free(msg.data); From a62f85c2eeec00316f94c20a396883644ec63b30 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 5 Mar 2024 01:51:53 +0530 Subject: [PATCH 1876/2402] hostap: Reduce WPA supplicant heap when MbedTLS heap is enabled If MbedTLS uses its own heap which is a static heap (not libc heap), then WPA supplicant heap usage will come down, so, reduce 8K (minimum MbedTLS heap for Wi-Fi) from the libc heap size. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index b5d1a525854..213ab22cfad 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -24,6 +24,8 @@ if WIFI_NM_WPA_SUPPLICANT config COMMON_LIBC_MALLOC_ARENA_SIZE default 40000 if WIFI_NM_WPA_SUPPLICANT_AP + # 8192 for MbedTLS heap + default 21808 if MBEDTLS_ENABLE_HEAP # 30K is mandatory, but might need more for long duration use cases default 30000 From 2e9b17158ae044218a1bc6998cce189f655bfdb5 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 5 Mar 2024 02:19:23 +0530 Subject: [PATCH 1877/2402] hostap: Always allow disconnect Even if the interface is not in connected state, allow disconnect to be accepted, this behaviour regressed when the mode check was introduced and if not connected then SSID will be NULL. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 20a557dc84e..40fb525ef6b 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -521,7 +521,7 @@ static int wpas_disconnect_network(const struct device *dev, int cur_mode) k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER); - if (!wpa_s->current_ssid || wpa_s->current_ssid->mode != cur_mode) { + if (wpa_s->current_ssid && wpa_s->current_ssid->mode != cur_mode) { ret = -EBUSY; wpa_printf(MSG_ERROR, "Interface %s is not in %s mode", dev->name, cur_mode == WPAS_MODE_INFRA ? "STA" : "AP"); From 688fe9afe55adcb2c504df7ac779d8f3363a5e39 Mon Sep 17 00:00:00 2001 From: Ravi Dondaputi Date: Fri, 8 Mar 2024 17:49:02 +0530 Subject: [PATCH 1878/2402] hostap: Resolve build warning with strncpy Make sure to copy LEN -1 bytes to the destination, to accommodate the terminating null byte. Signed-off-by: Ravi Dondaputi Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_events.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index 01a4512b95a..31a1e55e793 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -177,7 +177,7 @@ static int supplicant_process_status(struct supplicant_int_event_data *event_dat case SUPPLICANT_EVENT_NETWORK_ADDED: case SUPPLICANT_EVENT_NETWORK_REMOVED: strncpy(data->supplicant_event_str, event_info.event_str, - sizeof(data->supplicant_event_str)); + sizeof(data->supplicant_event_str) - 1); event_data->data_len = strlen(data->supplicant_event_str) + 1; case SUPPLICANT_EVENT_DSCP_POLICY: /* TODO */ From e2d267c92cb29ebccb965a278ed4916487c1eac9 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Tue, 19 Mar 2024 17:38:48 +0530 Subject: [PATCH 1879/2402] hostap: Fix band selection If user selects a band, then we should restrict scanning channels to that band, but using freq_list will only filter the results. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/src/supp_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 40fb525ef6b..305c27f3546 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -366,7 +366,7 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, } if (chan_list) { - if (!wpa_cli_cmd_v("set_network %d freq_list%s", resp.network_id, + if (!wpa_cli_cmd_v("set_network %d scan_freq%s", resp.network_id, chan_list)) { k_free(chan_list); goto out; From 873106faf156ddeeeb8ac2ea0d875905920d3b02 Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Wed, 20 Mar 2024 02:18:18 +0530 Subject: [PATCH 1880/2402] hostap: Add configuration options for NW selection To cater for different needs add an configuration options for WPA supplicant network selection (scan results sorting). The default is still left unchanged. Signed-off-by: Chaitanya Tata Signed-off-by: Jukka Rissanen --- modules/hostap/CMakeLists.txt | 4 ++++ modules/hostap/Kconfig | 23 +++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/modules/hostap/CMakeLists.txt b/modules/hostap/CMakeLists.txt index 19a8a67920b..b340c3882c8 100644 --- a/modules/hostap/CMakeLists.txt +++ b/modules/hostap/CMakeLists.txt @@ -406,4 +406,8 @@ zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_EAPOL zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_EAPOL CONFIG_IEEE8021X_EAPOL ) + +zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_NW_SEL_RELIABILITY + CONFIG_NW_SEL_RELIABILITY +) endif() diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index 213ab22cfad..feb78768905 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -360,4 +360,27 @@ config RRM config WMM_AC bool +config NW_SEL_RELIABILITY + bool + default y + depends on WIFI_NM_WPA_SUPPLICANT_NW_SEL_RELIABILITY + +choice WIFI_NM_WPA_SUPPLICANT_NW_SEL + prompt "WPA supplicant Network selection criterion" + default WIFI_NM_WPA_SUPPLICANT_NW_SEL_THROUGHPUT + help + Select the network selection method for the supplicant. + +config WIFI_NM_WPA_SUPPLICANT_NW_SEL_THROUGHPUT + bool "Throughput based network selection" + help + Select the network based on throughput. + +config WIFI_NM_WPA_SUPPLICANT_NW_SEL_RELIABILITY + bool "Reliability based network selection" + help + Select the network based on reliability. + +endchoice + endif # WIFI_NM_WPA_SUPPLICANT From af75192910effed549e188499cea3d58becdd692 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 4 Apr 2024 13:51:10 +0300 Subject: [PATCH 1881/2402] hostap: Comment out offeding mbedtls configs Comment out mbedtls symbols that do not have a proper Kconfig setting. Future commits will need to add relevant support in mbedtls side to provided needed symbols so that they can be used in hostap and uncomment these. Signed-off-by: Jukka Rissanen --- modules/hostap/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig index feb78768905..686c65695c2 100644 --- a/modules/hostap/Kconfig +++ b/modules/hostap/Kconfig @@ -117,9 +117,8 @@ config WIFI_NM_WPA_SUPPLICANT_CRYPTO select MBEDTLS_ECP_ALL_ENABLED select MBEDTLS_PKCS5_C select MBEDTLS_MAC_CMAC_ENABLED - select MBEDTLS_PK_C - select MBEDTLS_PKCS5_C - select MBEDTLS_CIPHER_PADDING_PKCS7 +# select MBEDTLS_PK_C +# select MBEDTLS_CIPHER_PADDING_PKCS7 # select MBEDTLS_CIPHER_MODE_CBC # select MBEDTLS_CIPHER_MODE_CTR # select MBEDTLS_LEGACY_CRYPTO_C From ef909b9aaaf051bc04ef230fb71eba99f4b5a61a Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Tue, 26 Mar 2024 17:27:52 +0200 Subject: [PATCH 1882/2402] west.yaml: Update hostap module This contains cherry-pick from Nordic downstream hostap repo as how it is today (20240326) Signed-off-by: Jukka Rissanen --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 1a55e019083..36059a132f2 100644 --- a/west.yml +++ b/west.yml @@ -256,7 +256,7 @@ manifest: - name: hostap repo-path: hostap path: modules/lib/hostap - revision: 9ad92f5249a6743f55787bb783d3398113b136c0 + revision: 81bdd8343347a2e36c67253a8aeb22ea7cb41132 - name: libmetal revision: 243eed541b9c211a2ce8841c788e62ddce84425e path: modules/hal/libmetal From 9e59a2f32f483b8178fce3b9fc09b19800440e4b Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Tue, 19 Mar 2024 15:06:58 +0100 Subject: [PATCH 1883/2402] include: zephyr: sys: util: add is_null_no_warn() utility function Some macros may need to check their arguments against NULL to support multiple use-cases, but NULL checks can generate warnings for a given use of those macros (where that particular argument can never be NULL). This can happen if: a) all macros are expanded (e.g. when using CONFIG_COMPILER_SAVE_TEMPS=y) or b) tracking of macro expansions are turned off (-ftrack-macro-expansion=0) This warning can be circumvented by passing the argument to be check to an inlined function for doing the NULL check. The compiler is still able to optimize this out at a later stage. Move the private ___is_null() helper function introduced in d51f874158038b1bc3b087604971132ebaaeb0f8 to include/zephyr/sys/utils.h and rename it to is_null_no_warn() to facilitate reuse. Signed-off-by: Henrik Brix Andersen --- include/zephyr/sys/cbprintf_internal.h | 16 +--------------- include/zephyr/sys/util.h | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 15 deletions(-) diff --git a/include/zephyr/sys/cbprintf_internal.h b/include/zephyr/sys/cbprintf_internal.h index 51b99494b96..da824fea2c4 100644 --- a/include/zephyr/sys/cbprintf_internal.h +++ b/include/zephyr/sys/cbprintf_internal.h @@ -757,20 +757,6 @@ do { \ _name##_buf32))) #endif -/* When the first argument of Z_CBPRINTF_STATIC_PACKAGE_GENERIC() is a - * static memory location, some compiler warns you if you compare the - * location against NULL. ___is_null() is used to kill this warning. - * - * The warnings would be visible when you built with -save-temps=obj, - * our standard debugging tip for macro problems. - * - * https://github.com/zephyrproject-rtos/zephyr/issues/51528 - */ -static ALWAYS_INLINE bool ___is_null(void *p) -{ - return p == NULL; -} - /** @brief Statically package a formatted string with arguments. * * @param buf buffer. If null then only length is calculated. @@ -819,7 +805,7 @@ do { \ Z_CBPRINTF_ON_STACK_ALLOC(_ros_pos_buf, _ros_cnt); \ uint8_t *_rws_buffer; \ Z_CBPRINTF_ON_STACK_ALLOC(_rws_buffer, 2 * _rws_cnt); \ - size_t _pmax = !___is_null(buf) ? _inlen : INT32_MAX; \ + size_t _pmax = !is_null_no_warn(buf) ? _inlen : INT32_MAX; \ int _pkg_len = 0; \ int _total_len = 0; \ int _pkg_offset = _align_offset; \ diff --git a/include/zephyr/sys/util.h b/include/zephyr/sys/util.h index 3a1bf3f553b..b457862bb97 100644 --- a/include/zephyr/sys/util.h +++ b/include/zephyr/sys/util.h @@ -421,6 +421,30 @@ static inline bool is_power_of_two(unsigned int x) return IS_POWER_OF_TWO(x); } +/** + * @brief Is @p p equal to ``NULL``? + * + * Some macros may need to check their arguments against NULL to support + * multiple use-cases, but NULL checks can generate warnings if such a macro + * is used in contexts where that particular argument can never be NULL. + * + * The warnings can be triggered if: + * a) all macros are expanded (e.g. when using CONFIG_COMPILER_SAVE_TEMPS=y) + * or + * b) tracking of macro expansions are turned off (-ftrack-macro-expansion=0) + * + * The warnings can be circumvented by using this inline function for doing + * the NULL check within the macro. The compiler is still able to optimize the + * NULL check out at a later stage. + * + * @param p Pointer to check + * @return true if @p p is equal to ``NULL``, false otherwise + */ +static ALWAYS_INLINE bool is_null_no_warn(void *p) +{ + return p == NULL; +} + /** * @brief Arithmetic shift right * @param value value to shift From 2f136f21a44df55f49f814124e13b6682da7685d Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Tue, 19 Mar 2024 15:23:33 +0100 Subject: [PATCH 1884/2402] drivers: can: use is_null_no_warn() check in generic macro Use is_null_no_warn() for checking the init_fn against NULL in order to avoid compiler warning when using CONFIG_COMPILER_SAVE_TEMPS=y. Fixes: #70390 Signed-off-by: Henrik Brix Andersen --- include/zephyr/drivers/can.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index 4396fa62ad6..2912ecbc577 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -734,7 +734,7 @@ struct can_device_state { stats_init(&state->stats.s_hdr, STATS_SIZE_32, 8, \ STATS_NAME_INIT_PARMS(can)); \ stats_register(dev->name, &(state->stats.s_hdr)); \ - if (init_fn != NULL) { \ + if (!is_null_no_warn(init_fn)) { \ return init_fn(dev); \ } \ \ From ef42f9d7597e8f9987da375558b1d509ae592214 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Tue, 19 Mar 2024 15:29:18 +0100 Subject: [PATCH 1885/2402] drivers: i2c: use is_null_no_warn() check in generic macro Use is_null_no_warn() for checking the init_fn against NULL in order to avoid compiler warning when using CONFIG_COMPILER_SAVE_TEMPS=y. Signed-off-by: Henrik Brix Andersen --- include/zephyr/drivers/i2c.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/drivers/i2c.h b/include/zephyr/drivers/i2c.h index 17dbb14010a..6135fbf1390 100644 --- a/include/zephyr/drivers/i2c.h +++ b/include/zephyr/drivers/i2c.h @@ -613,7 +613,7 @@ static inline void i2c_xfer_stats(const struct device *dev, struct i2c_msg *msgs stats_init(&state->stats.s_hdr, STATS_SIZE_32, 4, \ STATS_NAME_INIT_PARMS(i2c)); \ stats_register(dev->name, &(state->stats.s_hdr)); \ - if (init_fn != NULL) { \ + if (!is_null_no_warn(init_fn)) { \ return init_fn(dev); \ } \ \ From e3f182549a60ac9e1d84a4f4ce27bced6de0972b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 28 Mar 2024 11:53:49 +0100 Subject: [PATCH 1886/2402] mgmt: hawkbit: Add support for reboot after update MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for automatic reboot after successful update completion Signed-off-by: Fin Maaß --- include/zephyr/mgmt/hawkbit.h | 5 +++++ subsys/mgmt/hawkbit/hawkbit.c | 12 +++++++++--- subsys/mgmt/hawkbit/shell.c | 4 ++-- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/include/zephyr/mgmt/hawkbit.h b/include/zephyr/mgmt/hawkbit.h index d22330fc683..46a0ff34328 100644 --- a/include/zephyr/mgmt/hawkbit.h +++ b/include/zephyr/mgmt/hawkbit.h @@ -63,6 +63,11 @@ void hawkbit_autohandler(void); */ enum hawkbit_response hawkbit_probe(void); +/** + * @brief Request system to reboot. + */ +void hawkbit_reboot(void); + /** * @} */ diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c index 69ee267023f..37a98717a7a 100644 --- a/subsys/mgmt/hawkbit/hawkbit.c +++ b/subsys/mgmt/hawkbit/hawkbit.c @@ -952,6 +952,12 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type return true; } +void hawkbit_reboot(void) +{ + LOG_PANIC(); + sys_reboot(SYS_REBOOT_WARM); +} + enum hawkbit_response hawkbit_probe(void) { int ret; @@ -1186,8 +1192,7 @@ static void autohandler(struct k_work *work) LOG_ERR("Rebooting to previous confirmed image"); LOG_ERR("If this image is flashed using a hardware tool"); LOG_ERR("Make sure that it is a confirmed image"); - k_sleep(K_SECONDS(1)); - sys_reboot(SYS_REBOOT_WARM); + hawkbit_reboot(); break; case HAWKBIT_NO_UPDATE: @@ -1203,7 +1208,8 @@ static void autohandler(struct k_work *work) break; case HAWKBIT_UPDATE_INSTALLED: - LOG_INF("Update installed, please reboot"); + LOG_INF("Update installed"); + hawkbit_reboot(); break; case HAWKBIT_DOWNLOAD_ERROR: diff --git a/subsys/mgmt/hawkbit/shell.c b/subsys/mgmt/hawkbit/shell.c index efe2eccbf16..8b79eb7b223 100644 --- a/subsys/mgmt/hawkbit/shell.c +++ b/subsys/mgmt/hawkbit/shell.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include "hawkbit_firmware.h" #include "hawkbit_device.h" @@ -25,7 +24,7 @@ static void cmd_run(const struct shell *sh, size_t argc, char **argv) sh, SHELL_ERROR, "Image is unconfirmed." "Rebooting to revert back to previous confirmed image\n"); - sys_reboot(SYS_REBOOT_WARM); + hawkbit_reboot(); break; case HAWKBIT_CANCEL_UPDATE: @@ -43,6 +42,7 @@ static void cmd_run(const struct shell *sh, size_t argc, char **argv) case HAWKBIT_UPDATE_INSTALLED: shell_fprintf(sh, SHELL_INFO, "Update Installed\n"); + hawkbit_reboot(); break; case HAWKBIT_DOWNLOAD_ERROR: From 7392bf284cc63939626c5f38bdecbda9155f873f Mon Sep 17 00:00:00 2001 From: Ali Hozhabri Date: Fri, 1 Mar 2024 17:35:06 +0100 Subject: [PATCH 1887/2402] drivers: bluetooth: hci: Support ISO packets in ST HCI SPI BT driver Add support for ISO packets in ST HCI SPI BT driver. Signed-off-by: Ali Hozhabri --- drivers/bluetooth/hci/hci_spi_st.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/bluetooth/hci/hci_spi_st.c b/drivers/bluetooth/hci/hci_spi_st.c index b9e1c450447..78f051c5439 100644 --- a/drivers/bluetooth/hci/hci_spi_st.c +++ b/drivers/bluetooth/hci/hci_spi_st.c @@ -33,6 +33,7 @@ LOG_MODULE_REGISTER(bt_driver); #define HCI_ACL 0x02 #define HCI_SCO 0x03 #define HCI_EVT 0x04 +#define HCI_ISO 0x05 /* ST Proprietary extended event */ #define HCI_EXT_EVT 0x82 @@ -406,6 +407,26 @@ static struct net_buf *bt_spi_rx_buf_construct(uint8_t *msg) } net_buf_add_mem(buf, &msg[1], len); break; +#if defined(CONFIG_BT_ISO) + case HCI_ISO: + struct bt_hci_iso_hdr iso_hdr; + + buf = bt_buf_get_rx(BT_BUF_ISO_IN, timeout); + if (buf) { + memcpy(&iso_hdr, &msg[1], sizeof(iso_hdr)); + len = sizeof(iso_hdr) + bt_iso_hdr_len(sys_le16_to_cpu(iso_hdr.len)); + } else { + LOG_ERR("No available ISO buffers!"); + return NULL; + } + if (len > net_buf_tailroom(buf)) { + LOG_ERR("ISO too long: %d", len); + net_buf_unref(buf); + return NULL; + } + net_buf_add_mem(buf, &msg[1], len); + break; +#endif /* CONFIG_BT_ISO */ default: LOG_ERR("Unknown BT buf type %d", msg[0]); return NULL; @@ -488,6 +509,11 @@ static int bt_spi_send(struct net_buf *buf) case BT_BUF_CMD: net_buf_push_u8(buf, HCI_CMD); break; +#if defined(CONFIG_BT_ISO) + case BT_BUF_ISO_OUT: + net_buf_push_u8(buf, HCI_ISO); + break; +#endif /* CONFIG_BT_ISO */ default: LOG_ERR("Unsupported type"); return -EINVAL; From 0252b6ff88c6bd435954b421b217d84ead470aee Mon Sep 17 00:00:00 2001 From: Ali Hozhabri Date: Mon, 26 Feb 2024 17:16:11 +0100 Subject: [PATCH 1888/2402] drivers: bluetooth: hci: Support reading long events in ST SPI v1 Provide support for reading events longer than 127 bytes in ST SPI protocol v1 by splitting them into several SPI transactions. Signed-off-by: Ali Hozhabri --- drivers/bluetooth/hci/hci_spi_st.c | 55 ++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 15 deletions(-) diff --git a/drivers/bluetooth/hci/hci_spi_st.c b/drivers/bluetooth/hci/hci_spi_st.c index 78f051c5439..b2b252e0712 100644 --- a/drivers/bluetooth/hci/hci_spi_st.c +++ b/drivers/bluetooth/hci/hci_spi_st.c @@ -343,13 +343,29 @@ static int bt_spi_bluenrg_setup(const struct bt_hci_setup_params *params) #endif /* CONFIG_BT_BLUENRG_ACI */ -static struct net_buf *bt_spi_rx_buf_construct(uint8_t *msg) +static int bt_spi_rx_buf_construct(uint8_t *msg, struct net_buf **bufp, uint16_t size) { bool discardable = false; k_timeout_t timeout = K_FOREVER; struct bt_hci_acl_hdr acl_hdr; - struct net_buf *buf; - int len; + /* persistent variable to keep packet length in case the HCI packet is split in + * multiple SPI transactions + */ + static uint16_t len; + struct net_buf *buf = *bufp; + int ret = 0; + +#if DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) + if (buf) { + /* Buffer already allocated, waiting to complete event reception */ + net_buf_add_mem(buf, msg, MIN(size, len - buf->len)); + if (buf->len >= len) { + return 0; + } else { + return -EINPROGRESS; + } + } +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) */ switch (msg[PACKET_TYPE]) { #if DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v2) @@ -357,8 +373,8 @@ static struct net_buf *bt_spi_rx_buf_construct(uint8_t *msg) struct bt_hci_ext_evt_hdr *evt = (struct bt_hci_ext_evt_hdr *) (msg + 1); struct bt_hci_evt_hdr *evt2 = (struct bt_hci_evt_hdr *) (msg + 1); - if (evt->len > 0xff) { - return NULL; + if (sys_le16_to_cpu(evt->len) > 0xff) { + return -ENOMEM; } /* Use memmove instead of memcpy due to buffer overlapping */ memmove(msg + (1 + sizeof(*evt2)), msg + (1 + sizeof(*evt)), evt2->len); @@ -370,7 +386,7 @@ static struct net_buf *bt_spi_rx_buf_construct(uint8_t *msg) case BT_HCI_EVT_VENDOR: /* Run event through interface handler */ if (bt_spi_handle_vendor_evt(msg)) { - return NULL; + return -ECANCELED; } /* Event has not yet been handled */ __fallthrough; @@ -384,7 +400,7 @@ static struct net_buf *bt_spi_rx_buf_construct(uint8_t *msg) discardable, timeout); if (!buf) { LOG_DBG("Discard adv report due to insufficient buf"); - return NULL; + return -ENOMEM; } } @@ -392,9 +408,16 @@ static struct net_buf *bt_spi_rx_buf_construct(uint8_t *msg) if (len > net_buf_tailroom(buf)) { LOG_ERR("Event too long: %d", len); net_buf_unref(buf); - return NULL; + return -ENOMEM; } - net_buf_add_mem(buf, &msg[1], len); + /* Skip the first byte (HCI packet indicator) */ + size = size - 1; + net_buf_add_mem(buf, &msg[1], size); +#if DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) + if (size < len) { + ret = -EINPROGRESS; + } +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) */ break; case HCI_ACL: buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_FOREVER); @@ -403,7 +426,7 @@ static struct net_buf *bt_spi_rx_buf_construct(uint8_t *msg) if (len > net_buf_tailroom(buf)) { LOG_ERR("ACL too long: %d", len); net_buf_unref(buf); - return NULL; + return -ENOMEM; } net_buf_add_mem(buf, &msg[1], len); break; @@ -429,10 +452,11 @@ static struct net_buf *bt_spi_rx_buf_construct(uint8_t *msg) #endif /* CONFIG_BT_ISO */ default: LOG_ERR("Unknown BT buf type %d", msg[0]); - return NULL; + return -ENOTSUP; } - return buf; + *bufp = buf; + return ret; } static void bt_spi_rx_thread(void *p1, void *p2, void *p3) @@ -441,7 +465,7 @@ static void bt_spi_rx_thread(void *p1, void *p2, void *p3) ARG_UNUSED(p2); ARG_UNUSED(p3); - struct net_buf *buf; + struct net_buf *buf = NULL; uint16_t size = 0U; int ret; @@ -477,10 +501,11 @@ static void bt_spi_rx_thread(void *p1, void *p2, void *p3) LOG_HEXDUMP_DBG(rxmsg, size, "SPI RX"); /* Construct net_buf from SPI data */ - buf = bt_spi_rx_buf_construct(rxmsg); - if (buf) { + ret = bt_spi_rx_buf_construct(rxmsg, &buf, size); + if (!ret) { /* Handle the received HCI data */ bt_recv(buf); + buf = NULL; } } while (READ_CONDITION); } From 52f318c85e159935181fddaf276bcb5851447dc5 Mon Sep 17 00:00:00 2001 From: Abderrahmane Jarmouni Date: Mon, 19 Feb 2024 17:53:34 +0100 Subject: [PATCH 1889/2402] tests: lib: gui: lvgl: add LittleFS block device support Add support for running this test on a block device (MMC/SDMMC). Signed-off-by: Abderrahmane Jarmouni --- tests/lib/gui/lvgl/src/main.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tests/lib/gui/lvgl/src/main.c b/tests/lib/gui/lvgl/src/main.c index 5b32e97ed3c..2c2e0641bd3 100644 --- a/tests/lib/gui/lvgl/src/main.c +++ b/tests/lib/gui/lvgl/src/main.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2019 Jan Van Winkel + * Copyright (c) 2024 STMicroelectronics * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,6 +15,30 @@ #include +#ifdef CONFIG_FS_LITTLEFS_BLK_DEV + +#ifdef CONFIG_DISK_DRIVER_SDMMC +#define DISK_NAME CONFIG_SDMMC_VOLUME_NAME +#elif IS_ENABLED(CONFIG_DISK_DRIVER_MMC) +#define DISK_NAME CONFIG_MMC_VOLUME_NAME +#else +#error "No disk device defined, is your board supported?" +#endif /* CONFIG_DISK_DRIVER_SDMMC */ + +#define IMG_FILE_PATH "/"DISK_NAME":/img.bin" + +struct fs_littlefs lfsfs; + +static struct fs_mount_t mnt = { + .type = FS_LITTLEFS, + .fs_data = &lfsfs, + .storage_dev = (void *)DISK_NAME, + .mnt_point = "/"DISK_NAME":", + .flags = FS_MOUNT_FLAG_USE_DISK_ACCESS, +}; + +#else /* CONFIG_FS_LITTLEFS_BLK_DEV */ + #define IMG_FILE_PATH "/mnt/img.bin" #define LVGL_PARTITION storage_partition @@ -27,6 +52,7 @@ static struct fs_mount_t mnt = { .storage_dev = (void *)LVGL_PARTITION_ID, .mnt_point = "/mnt" }; +#endif /* CONFIG_FS_LITTLEFS_BLK_DEV */ ZTEST(lvgl_screen, test_get_default_screen) { From c0ce237d9fa07b416f6f8a7e250de7407de55aa7 Mon Sep 17 00:00:00 2001 From: Abderrahmane Jarmouni Date: Fri, 23 Feb 2024 15:29:55 +0100 Subject: [PATCH 1890/2402] tests: lib: gui: lvgl: add stm32 test cases Add test cases for stm32h747i_disco_stm32h747xx_m7. Signed-off-by: Abderrahmane Jarmouni --- .../stm32h747i_disco_stm32h747xx_m7.conf | 6 ++ .../stm32h747i_disco_stm32h747xx_m7.overlay | 46 +++++++++++++ tests/lib/gui/lvgl/prj_blk.conf | 10 +++ tests/lib/gui/lvgl/src/main.c | 6 -- tests/lib/gui/lvgl/testcase.yaml | 67 +++++++++++++++++-- 5 files changed, 122 insertions(+), 13 deletions(-) create mode 100644 tests/lib/gui/lvgl/boards/stm32h747i_disco_stm32h747xx_m7.conf create mode 100644 tests/lib/gui/lvgl/boards/stm32h747i_disco_stm32h747xx_m7.overlay create mode 100644 tests/lib/gui/lvgl/prj_blk.conf diff --git a/tests/lib/gui/lvgl/boards/stm32h747i_disco_stm32h747xx_m7.conf b/tests/lib/gui/lvgl/boards/stm32h747i_disco_stm32h747xx_m7.conf new file mode 100644 index 00000000000..3557d3cd511 --- /dev/null +++ b/tests/lib/gui/lvgl/boards/stm32h747i_disco_stm32h747xx_m7.conf @@ -0,0 +1,6 @@ +CONFIG_FS_LITTLEFS_FC_HEAP_SIZE=2048 +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_DUMMY_DISPLAY=n + +CONFIG_NOCACHE_MEMORY=y diff --git a/tests/lib/gui/lvgl/boards/stm32h747i_disco_stm32h747xx_m7.overlay b/tests/lib/gui/lvgl/boards/stm32h747i_disco_stm32h747xx_m7.overlay new file mode 100644 index 00000000000..3361cd6be94 --- /dev/null +++ b/tests/lib/gui/lvgl/boards/stm32h747i_disco_stm32h747xx_m7.overlay @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&sdmmc1 { + sdmmc { + compatible = "zephyr,sdmmc-disk"; + }; +}; + +/delete-node/ &storage_partition; + +&flash0 { + partitions { + partition@ff800 { + reg = <0x000ff800 DT_SIZE_K(2)>; + }; + }; +}; + +/ { + fstab { + compatible = "zephyr,fstab"; + lfs1: lfs1 { + compatible = "zephyr,fstab,littlefs"; + read-size = <32>; + prog-size = <32>; + cache-size = <256>; + lookahead-size = <64>; + block-cycles = <512>; + partition = <&storage_partition>; + mount-point = "/lfs1"; + }; + }; +}; + +&mt25ql512ab1 { + partitions { + storage_partition: partition@0 { + reg = <0x0 DT_SIZE_M(64)>; + label = "storage"; + }; + }; +}; diff --git a/tests/lib/gui/lvgl/prj_blk.conf b/tests/lib/gui/lvgl/prj_blk.conf new file mode 100644 index 00000000000..18dac1f386f --- /dev/null +++ b/tests/lib/gui/lvgl/prj_blk.conf @@ -0,0 +1,10 @@ +CONFIG_DISK_DRIVERS=y +CONFIG_DISK_ACCESS=y + +CONFIG_FS_LITTLEFS_BLK_DEV=y + +CONFIG_FS_LITTLEFS_FC_HEAP_SIZE=2048 +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_FLASH=n +CONFIG_FLASH_MAP=n diff --git a/tests/lib/gui/lvgl/src/main.c b/tests/lib/gui/lvgl/src/main.c index 2c2e0641bd3..6475e63ddd0 100644 --- a/tests/lib/gui/lvgl/src/main.c +++ b/tests/lib/gui/lvgl/src/main.c @@ -71,8 +71,6 @@ ZTEST(lvgl_screen, test_add_delete_screen) lv_scr_load(new_screen); - lv_task_handler(); - lv_obj_t *act_screen = lv_scr_act(); zassert_equal_ptr(act_screen, new_screen, "New screen not active"); @@ -81,8 +79,6 @@ ZTEST(lvgl_screen, test_add_delete_screen) lv_obj_del(new_screen); - lv_task_handler(); - act_screen = lv_scr_act(); zassert_equal_ptr(act_screen, default_screen, "Default screen not active"); @@ -96,8 +92,6 @@ ZTEST_USER(lvgl_fs, test_add_img) lv_img_set_src(img, IMG_FILE_PATH); lv_obj_align(img, LV_ALIGN_CENTER, 0, 0); - - lv_task_handler(); } diff --git a/tests/lib/gui/lvgl/testcase.yaml b/tests/lib/gui/lvgl/testcase.yaml index f878a4c4363..db356ec5569 100644 --- a/tests/lib/gui/lvgl/testcase.yaml +++ b/tests/lib/gui/lvgl/testcase.yaml @@ -2,35 +2,88 @@ common: tags: - display - gui - platform_allow: - - native_posix/native/64 - - native_sim/native/64 - - native_sim - integration_platforms: - - native_sim tests: - libraries.gui.lvgl: {} + libraries.gui.lvgl: + platform_allow: + - native_posix/native/64 + - native_sim/native/64 + - native_sim + integration_platforms: + - native_sim libraries.gui.lvgl.dynamic.heap.libc: filter: CONFIG_FULL_LIBC_SUPPORTED extra_configs: - CONFIG_REQUIRES_FULL_LIBC=y - CONFIG_LV_Z_BUFFER_ALLOC_DYNAMIC=y - CONFIG_LV_Z_MEM_POOL_HEAP_LIB_C=y + platform_allow: + - native_posix/native/64 + - native_sim/native/64 + - native_sim + integration_platforms: + - native_sim libraries.gui.lvgl.dynamic.pool.sys_heap: extra_configs: - CONFIG_LV_Z_BUFFER_ALLOC_DYNAMIC=y - CONFIG_LV_Z_MEM_POOL_SYS_HEAP=y - CONFIG_LV_Z_MEM_POOL_SIZE=98304 + platform_allow: + - native_posix/native/64 + - native_sim/native/64 + - native_sim + integration_platforms: + - native_sim libraries.gui.lvgl.16bit: extra_configs: - CONFIG_LV_COLOR_DEPTH_16=y + platform_allow: + - native_posix/native/64 + - native_sim/native/64 + - native_sim + integration_platforms: + - native_sim libraries.gui.lvgl.8bit: extra_configs: - CONFIG_LV_COLOR_DEPTH_8=y + platform_allow: + - native_posix/native/64 + - native_sim/native/64 + - native_sim + integration_platforms: + - native_sim libraries.gui.lvgl.mono: extra_configs: - CONFIG_LV_COLOR_DEPTH_1=y + platform_allow: + - native_posix/native/64 + - native_sim/native/64 + - native_sim + integration_platforms: + - native_sim libraries.gui.lvgl.16bit.swap: extra_configs: - CONFIG_LV_COLOR_DEPTH_16=y - CONFIG_LV_COLOR_16_SWAP=y + platform_allow: + - native_posix/native/64 + - native_sim/native/64 + - native_sim + integration_platforms: + - native_sim + libraries.gui.lvgl.stm32h747i_disco_m7: + platform_allow: stm32h747i_disco/stm32h747xx/m7 + extra_args: + - SHIELD=st_b_lcd40_dsi1_mb1166 + tags: + - shield + libraries.gui.lvgl.stm32h747i_disco_m7_blk: + platform_allow: stm32h747i_disco/stm32h747xx/m7 + extra_configs: + - CONFIG_SDMMC_STM32_HWFC=y + - CONFIG_NOCACHE_MEMORY=y + - CONFIG_DUMMY_DISPLAY=n + extra_args: + - SHIELD=st_b_lcd40_dsi1_mb1166 + - OVERLAY_CONFIG=prj_blk.conf + tags: + - shield From 5ab37692c0ca9fafd90a06d034ef60d7f9d0a684 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 22 Dec 2023 11:14:27 +0100 Subject: [PATCH 1891/2402] Bluetooth: CAP: Commander change microphone mute procedure Adds the CAP Commander Change Microphone Mute procedure. This procedure changes the microphone mute state on one or more CAP Acceptors. Signed-off-by: Emil Gydesen --- include/zephyr/bluetooth/audio/cap.h | 11 ++ subsys/bluetooth/audio/cap_commander.c | 181 ++++++++++++++++++++++++- subsys/bluetooth/audio/cap_internal.h | 5 +- 3 files changed, 192 insertions(+), 5 deletions(-) diff --git a/include/zephyr/bluetooth/audio/cap.h b/include/zephyr/bluetooth/audio/cap.h index 35a30f742ac..8119c0e2e9e 100644 --- a/include/zephyr/bluetooth/audio/cap.h +++ b/include/zephyr/bluetooth/audio/cap.h @@ -725,6 +725,17 @@ struct bt_cap_commander_cb { #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ #if defined(CONFIG_BT_MICP_MIC_CTLR) + /** + * @brief Callback for bt_cap_commander_change_microphone_mute_state(). + * + * @param conn Pointer to the connection where the error + * occurred. NULL if @p err is 0 or if cancelled by + * bt_cap_commander_cancel() + * @param err 0 on success, BT_GATT_ERR() with a + * specific ATT (BT_ATT_ERR_*) error code or -ECANCELED if cancelled + * by bt_cap_commander_cancel(). + */ + void (*microphone_mute_changed)(struct bt_conn *conn, int err); #if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) /** * @brief Callback for bt_cap_commander_change_microphone_gain_setting(). diff --git a/subsys/bluetooth/audio/cap_commander.c b/subsys/bluetooth/audio/cap_commander.c index 95e4affc848..b65eb453ce9 100644 --- a/subsys/bluetooth/audio/cap_commander.c +++ b/subsys/bluetooth/audio/cap_commander.c @@ -125,6 +125,11 @@ static void cap_commander_unicast_audio_proc_complete(void) #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ #if defined(CONFIG_BT_MICP_MIC_CTLR) + case BT_CAP_COMMON_PROC_TYPE_MICROPHONE_MUTE_CHANGE: + if (cap_cb->microphone_mute_changed != NULL) { + cap_cb->microphone_mute_changed(failed_conn, err); + } + break; #if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) case BT_CAP_COMMON_PROC_TYPE_MICROPHONE_GAIN_CHANGE: if (cap_cb->microphone_gain_changed != NULL) { @@ -441,7 +446,7 @@ static void cap_commander_vcp_vol_mute_cb(struct bt_vcp_vol_ctlr *vol_ctlr, int proc_param = &active_proc->proc_param.commander[active_proc->proc_done_cnt]; conn = proc_param->conn; active_proc->proc_initiated_cnt++; - if (proc_param->change_mute.mute) { + if (proc_param->change_vol_mute.mute) { err = bt_vcp_vol_ctlr_mute(bt_vcp_vol_ctlr_get_by_conn(conn)); } else { err = bt_vcp_vol_ctlr_unmute(bt_vcp_vol_ctlr_get_by_conn(conn)); @@ -500,14 +505,14 @@ int bt_cap_commander_change_volume_mute_state( * are kept valid */ active_proc->proc_param.commander[i].conn = member_conn; - active_proc->proc_param.commander[i].change_mute.mute = param->mute; + active_proc->proc_param.commander[i].change_vol_mute.mute = param->mute; } proc_param = &active_proc->proc_param.commander[0]; conn = proc_param->conn; active_proc->proc_initiated_cnt++; - if (proc_param->change_mute.mute) { + if (proc_param->change_vol_mute.mute) { err = bt_vcp_vol_ctlr_mute(bt_vcp_vol_ctlr_get_by_conn(conn)); } else { err = bt_vcp_vol_ctlr_unmute(bt_vcp_vol_ctlr_get_by_conn(conn)); @@ -754,16 +759,184 @@ static int cap_commander_register_micp_callbacks(void) return 0; } +static bool valid_change_microphone_mute_state_param( + const struct bt_cap_commander_change_microphone_mute_state_param *param) +{ + CHECKIF(param == NULL) { + LOG_DBG("param is NULL"); + return false; + } + + CHECKIF(param->count == 0) { + LOG_DBG("Invalid param->count: %u", param->count); + return false; + } + + CHECKIF(param->members == NULL) { + LOG_DBG("param->members is NULL"); + return false; + } + + CHECKIF(param->count > CONFIG_BT_MAX_CONN) { + LOG_DBG("param->count (%zu) is larger than CONFIG_BT_MAX_CONN (%d)", param->count, + CONFIG_BT_MAX_CONN); + return false; + } + + for (size_t i = 0U; i < param->count; i++) { + const union bt_cap_set_member *member = ¶m->members[i]; + const struct bt_cap_common_client *client = + bt_cap_common_get_client(param->type, member); + + CHECKIF(client == NULL) { + LOG_DBG("Invalid param->members[%zu]", i); + return false; + } + + CHECKIF(bt_micp_mic_ctlr_get_by_conn(client->conn) == NULL) { + LOG_DBG("Microphone control not available for param->members[%zu]", i); + return false; + } + + for (size_t j = 0U; j < i; j++) { + const union bt_cap_set_member *other = ¶m->members[j]; + + CHECKIF(other == member) { + LOG_DBG("param->members[%zu] (%p) is duplicated by " + "param->members[%zu] (%p)", + j, other, i, member); + return false; + } + } + } + + return true; +} + +static void cap_commander_micp_mic_mute_cb(struct bt_micp_mic_ctlr *mic_ctlr, int err) +{ + struct bt_cap_common_proc *active_proc = bt_cap_common_get_active_proc(); + struct bt_conn *conn; + int micp_err; + + LOG_DBG("mic_ctlr %p", (void *)mic_ctlr); + + micp_err = bt_micp_mic_ctlr_conn_get(mic_ctlr, &conn); + if (micp_err != 0) { + LOG_ERR("Failed to get conn by mic_ctlr: %d", micp_err); + return; + } + + LOG_DBG("conn %p", (void *)conn); + if (!bt_cap_common_conn_in_active_proc(conn)) { + /* State change happened outside of a procedure; ignore */ + return; + } + + if (err != 0) { + LOG_DBG("Failed to change microphone mute: %d", err); + bt_cap_common_abort_proc(conn, err); + } else { + active_proc->proc_done_cnt++; + + LOG_DBG("Conn %p mute updated (%zu/%zu streams done)", (void *)conn, + active_proc->proc_done_cnt, active_proc->proc_cnt); + } + + if (bt_cap_common_proc_is_aborted()) { + LOG_DBG("Proc is aborted"); + if (bt_cap_common_proc_all_handled()) { + LOG_DBG("All handled"); + cap_commander_unicast_audio_proc_complete(); + } + + return; + } + + if (!bt_cap_common_proc_is_done()) { + const struct bt_cap_commander_proc_param *proc_param; + + proc_param = &active_proc->proc_param.commander[active_proc->proc_done_cnt]; + conn = proc_param->conn; + active_proc->proc_initiated_cnt++; + if (proc_param->change_mic_mute.mute) { + err = bt_micp_mic_ctlr_mute(bt_micp_mic_ctlr_get_by_conn(conn)); + } else { + err = bt_micp_mic_ctlr_unmute(bt_micp_mic_ctlr_get_by_conn(conn)); + } + + if (err != 0) { + LOG_DBG("Failed to change mute for conn %p: %d", (void *)conn, err); + bt_cap_common_abort_proc(conn, err); + cap_commander_unicast_audio_proc_complete(); + } + } else { + cap_commander_unicast_audio_proc_complete(); + } +} + int bt_cap_commander_change_microphone_mute_state( const struct bt_cap_commander_change_microphone_mute_state_param *param) { + const struct bt_cap_commander_proc_param *proc_param; + struct bt_cap_common_proc *active_proc; + struct bt_conn *conn; + int err; + + if (bt_cap_common_proc_is_active()) { + LOG_DBG("A CAP procedure is already in progress"); + + return -EBUSY; + } + + if (!valid_change_microphone_mute_state_param(param)) { + return -EINVAL; + } + + bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_MICROPHONE_MUTE_CHANGE, param->count); + + mic_ctlr_cb.mute_written = cap_commander_micp_mic_mute_cb; + mic_ctlr_cb.unmute_written = cap_commander_micp_mic_mute_cb; if (!micp_callbacks_registered && cap_commander_register_micp_callbacks() != 0) { LOG_DBG("Failed to register MICP callbacks"); return -ENOEXEC; } - return -ENOSYS; + active_proc = bt_cap_common_get_active_proc(); + + for (size_t i = 0U; i < param->count; i++) { + struct bt_conn *member_conn = + bt_cap_common_get_member_conn(param->type, ¶m->members[i]); + + CHECKIF(member_conn == NULL) { + LOG_DBG("Invalid param->members[%zu]", i); + return -EINVAL; + } + + /* Store the necessary parameters as we cannot assume that the supplied parameters + * are kept valid + */ + active_proc->proc_param.commander[i].conn = member_conn; + active_proc->proc_param.commander[i].change_mic_mute.mute = param->mute; + } + + proc_param = &active_proc->proc_param.commander[0]; + conn = proc_param->conn; + active_proc->proc_initiated_cnt++; + + if (proc_param->change_mic_mute.mute) { + err = bt_micp_mic_ctlr_mute(bt_micp_mic_ctlr_get_by_conn(conn)); + } else { + err = bt_micp_mic_ctlr_unmute(bt_micp_mic_ctlr_get_by_conn(conn)); + } + + if (err != 0) { + LOG_DBG("Failed to set microphone mute state for conn %p: %d", (void *)conn, err); + return -ENOEXEC; + } + + return 0; } #if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) diff --git a/subsys/bluetooth/audio/cap_internal.h b/subsys/bluetooth/audio/cap_internal.h index 2c56ef1f742..c2dc861da3d 100644 --- a/subsys/bluetooth/audio/cap_internal.h +++ b/subsys/bluetooth/audio/cap_internal.h @@ -79,7 +79,7 @@ struct bt_cap_commander_proc_param { } change_volume; struct { bool mute; - } change_mute; + } change_vol_mute; #endif /* CONFIG_BT_VCP_VOL_CTLR */ #if defined(CONFIG_BT_VCP_VOL_CTLR_VOCS) struct { @@ -88,6 +88,9 @@ struct bt_cap_commander_proc_param { } change_offset; #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #if defined(CONFIG_BT_MICP_MIC_CTLR) + struct { + bool mute; + } change_mic_mute; #if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) struct { int8_t gain; From 50b37cb564c0059a8289950459537e1ac29a1b1e Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 22 Dec 2023 11:14:58 +0100 Subject: [PATCH 1892/2402] tests: bsim: Bluetooth: CAP Commander Change Microphone Mute Adds bsim test of the CAP Commander Change Microphone Mute procedure. Signed-off-by: Emil Gydesen --- .../bluetooth/audio/src/cap_commander_test.c | 53 ++++++++++++++++--- 1 file changed, 47 insertions(+), 6 deletions(-) diff --git a/tests/bsim/bluetooth/audio/src/cap_commander_test.c b/tests/bsim/bluetooth/audio/src/cap_commander_test.c index d25d94ce42e..1a8bb6dd7f6 100644 --- a/tests/bsim/bluetooth/audio/src/cap_commander_test.c +++ b/tests/bsim/bluetooth/audio/src/cap_commander_test.c @@ -28,6 +28,7 @@ CREATE_FLAG(flag_mtu_exchanged); CREATE_FLAG(flag_volume_changed); CREATE_FLAG(flag_volume_mute_changed); CREATE_FLAG(flag_volume_offset_changed); +CREATE_FLAG(flag_microphone_mute_changed); CREATE_FLAG(flag_microphone_gain_changed); static void cap_discovery_complete_cb(struct bt_conn *conn, int err, @@ -68,7 +69,7 @@ static void cap_volume_changed_cb(struct bt_conn *conn, int err) static void cap_volume_mute_changed_cb(struct bt_conn *conn, int err) { if (err != 0) { - FAIL("Failed to change volume for conn %p: %d\n", conn, err); + FAIL("Failed to change volume mute for conn %p: %d\n", conn, err); return; } @@ -79,7 +80,7 @@ static void cap_volume_mute_changed_cb(struct bt_conn *conn, int err) static void cap_volume_offset_changed_cb(struct bt_conn *conn, int err) { if (err != 0) { - FAIL("Failed to change volume for conn %p: %d\n", conn, err); + FAIL("Failed to change volume offset for conn %p: %d\n", conn, err); return; } @@ -89,11 +90,21 @@ static void cap_volume_offset_changed_cb(struct bt_conn *conn, int err) #endif /* CONFIG_BT_VCP_VOL_CTLR */ #if defined(CONFIG_BT_MICP_MIC_CTLR) +static void cap_microphone_mute_changed_cb(struct bt_conn *conn, int err) +{ + if (err != 0) { + FAIL("Failed to change microphone mute for conn %p: %d\n", conn, err); + return; + } + + SET_FLAG(flag_microphone_mute_changed); +} + #if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) static void cap_microphone_gain_changed_cb(struct bt_conn *conn, int err) { if (err != 0) { - FAIL("Failed to change volume for conn %p: %d\n", conn, err); + FAIL("Failed to change microphone gain for conn %p: %d\n", conn, err); return; } @@ -112,6 +123,7 @@ static struct bt_cap_commander_cb cap_cb = { #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ #if defined(CONFIG_BT_MICP_MIC_CTLR) + .microphone_mute_changed = cap_microphone_mute_changed_cb, #if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) .microphone_gain_changed = cap_microphone_gain_changed_cb, #endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ @@ -370,7 +382,7 @@ static void test_change_volume_mute(bool mute) err = bt_cap_commander_change_volume_mute_state(¶m); if (err != 0) { - FAIL("Failed to change volume: %d\n", err); + FAIL("Failed to change volume mute: %d\n", err); return; } @@ -398,7 +410,7 @@ static void test_change_volume_offset(void) err = bt_cap_commander_change_volume_offset(¶m); if (err != 0) { - FAIL("Failed to change volume: %d\n", err); + FAIL("Failed to change volume offset: %d\n", err); return; } @@ -406,6 +418,34 @@ static void test_change_volume_offset(void) printk("Volume offset changed\n"); } +static void test_change_microphone_mute(bool mute) +{ + union bt_cap_set_member members[CONFIG_BT_MAX_CONN]; + const struct bt_cap_commander_change_microphone_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = connected_conn_cnt, + .mute = mute, + }; + int err; + + printk("Changing microphone mute state to %d\n", param.mute); + UNSET_FLAG(flag_microphone_mute_changed); + + for (size_t i = 0U; i < param.count; i++) { + param.members[i].member = connected_conns[i]; + } + + err = bt_cap_commander_change_microphone_mute_state(¶m); + if (err != 0) { + FAIL("Failed to change microphone mute: %d\n", err); + return; + } + + WAIT_FOR_FLAG(flag_microphone_mute_changed); + printk("Microphone mute state changed to %d\n", param.mute); +} + static void test_change_microphone_gain(void) { struct bt_cap_commander_change_microphone_gain_setting_member_param @@ -471,7 +511,8 @@ static void test_main_cap_commander_capture_and_render(void) } if (IS_ENABLED(CONFIG_BT_MICP_MIC_CTLR)) { - /* TODO: Add test of mic mute */ + test_change_microphone_mute(true); + test_change_microphone_mute(false); if (IS_ENABLED(CONFIG_BT_MICP_MIC_CTLR_AICS)) { test_change_microphone_gain(); From f70ba925eaacc430247b5dabe33e5fe0361734ee Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 22 Dec 2023 11:15:18 +0100 Subject: [PATCH 1893/2402] tests: Bluetooth: CAP Commander Change Microphone mute unittests Adds unittests for the CAP Commander Change Microphone mute procedure. Signed-off-by: Emil Gydesen --- .../audio/cap_commander/src/test_micp.c | 216 ++++++++++++++++++ .../audio/mocks/include/cap_commander.h | 1 + .../bluetooth/audio/mocks/src/cap_commander.c | 3 + 3 files changed, 220 insertions(+) diff --git a/tests/bluetooth/audio/cap_commander/src/test_micp.c b/tests/bluetooth/audio/cap_commander/src/test_micp.c index 4d3958d0e44..e6636516206 100644 --- a/tests/bluetooth/audio/cap_commander/src/test_micp.c +++ b/tests/bluetooth/audio/cap_commander/src/test_micp.c @@ -291,3 +291,219 @@ ZTEST_F(cap_commander_test_micp, err = bt_cap_commander_change_microphone_gain_setting(¶m); zassert_equal(-EINVAL, err, "Unexpected return value %d", err); } + +ZTEST_F(cap_commander_test_micp, test_commander_change_microphone_mute_state) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_mute_state(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.microphone_mute_changed", 1, + mock_cap_commander_microphone_mute_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_micp, test_commander_change_microphone_mute_state_double) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_mute_state(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.microphone_mute_changed", 1, + mock_cap_commander_microphone_mute_changed_cb_fake.call_count); + + /* That that it still works as expected if we set the same value twice */ + err = bt_cap_commander_change_microphone_mute_state(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.microphone_mute_changed", 2, + mock_cap_commander_microphone_mute_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_micp, test_commander_change_microphone_mute_state_inval_param_null) +{ + int err; + + err = bt_cap_commander_change_microphone_mute_state(NULL); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, + test_commander_change_microphone_mute_state_inval_param_null_members) +{ + const struct bt_cap_commander_change_microphone_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = NULL, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + err = bt_cap_commander_change_microphone_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, + test_commander_change_microphone_mute_state_inval_param_null_member) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members) - 1; i++) { + members[i].member = &fixture->conns[i]; + } + members[ARRAY_SIZE(members) - 1].member = NULL; + + err = bt_cap_commander_change_microphone_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, test_commander_change_microphone_mute_state_inval_missing_cas) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ + + err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, test_commander_change_microphone_mute_state_inval_missing_vcs) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, test_commander_change_microphone_mute_state_inval_param_zero_count) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = 0U, + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_change_microphone_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, + test_commander_change_microphone_mute_state_inval_param_inval_count) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = CONFIG_BT_MAX_CONN + 1, + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_change_microphone_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} diff --git a/tests/bluetooth/audio/mocks/include/cap_commander.h b/tests/bluetooth/audio/mocks/include/cap_commander.h index 44c3b802895..1e56aca6930 100644 --- a/tests/bluetooth/audio/mocks/include/cap_commander.h +++ b/tests/bluetooth/audio/mocks/include/cap_commander.h @@ -20,6 +20,7 @@ DECLARE_FAKE_VOID_FUNC(mock_cap_commander_discovery_complete_cb, struct bt_conn DECLARE_FAKE_VOID_FUNC(mock_cap_commander_volume_changed_cb, struct bt_conn *, int); DECLARE_FAKE_VOID_FUNC(mock_cap_commander_volume_mute_changed_cb, struct bt_conn *, int); DECLARE_FAKE_VOID_FUNC(mock_cap_commander_volume_offset_changed_cb, struct bt_conn *, int); +DECLARE_FAKE_VOID_FUNC(mock_cap_commander_microphone_mute_changed_cb, struct bt_conn *, int); DECLARE_FAKE_VOID_FUNC(mock_cap_commander_microphone_gain_changed_cb, struct bt_conn *, int); #endif /* MOCKS_CAP_COMMANDER_H_ */ diff --git a/tests/bluetooth/audio/mocks/src/cap_commander.c b/tests/bluetooth/audio/mocks/src/cap_commander.c index 073615625e6..4305f8e1b8e 100644 --- a/tests/bluetooth/audio/mocks/src/cap_commander.c +++ b/tests/bluetooth/audio/mocks/src/cap_commander.c @@ -14,6 +14,7 @@ FAKE(mock_cap_commander_volume_changed_cb) \ FAKE(mock_cap_commander_volume_mute_changed_cb) \ FAKE(mock_cap_commander_volume_offset_changed_cb) \ + FAKE(mock_cap_commander_microphone_mute_changed_cb) \ FAKE(mock_cap_commander_microphone_gain_changed_cb) DEFINE_FAKE_VOID_FUNC(mock_cap_commander_discovery_complete_cb, struct bt_conn *, int, @@ -22,6 +23,7 @@ DEFINE_FAKE_VOID_FUNC(mock_cap_commander_discovery_complete_cb, struct bt_conn * DEFINE_FAKE_VOID_FUNC(mock_cap_commander_volume_changed_cb, struct bt_conn *, int); DEFINE_FAKE_VOID_FUNC(mock_cap_commander_volume_mute_changed_cb, struct bt_conn *, int); DEFINE_FAKE_VOID_FUNC(mock_cap_commander_volume_offset_changed_cb, struct bt_conn *, int); +DEFINE_FAKE_VOID_FUNC(mock_cap_commander_microphone_mute_changed_cb, struct bt_conn *, int); DEFINE_FAKE_VOID_FUNC(mock_cap_commander_microphone_gain_changed_cb, struct bt_conn *, int); const struct bt_cap_commander_cb mock_cap_commander_cb = { @@ -34,6 +36,7 @@ const struct bt_cap_commander_cb mock_cap_commander_cb = { #endif /* CONFIG_BT_VCP_VOL_CTLR */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ #if defined(CONFIG_BT_MICP_MIC_CTLR) + .microphone_mute_changed = mock_cap_commander_microphone_mute_changed_cb, #if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) .microphone_gain_changed = mock_cap_commander_microphone_gain_changed_cb, #endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ From 490fb201481dde0eaeb22fcc9d71811594beb685 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 22 Dec 2023 11:15:38 +0100 Subject: [PATCH 1894/2402] Bluetooth: Audio: Shell: CAP change microphone mute command Adds the change microphone mute command to the CAP commander shell. Signed-off-by: Emil Gydesen --- doc/connectivity/bluetooth/api/shell/cap.rst | 46 ++++++++++++-- subsys/bluetooth/audio/shell/cap_commander.c | 66 ++++++++++++++++++++ 2 files changed, 108 insertions(+), 4 deletions(-) diff --git a/doc/connectivity/bluetooth/api/shell/cap.rst b/doc/connectivity/bluetooth/api/shell/cap.rst index a21bc52a74b..54489ade793 100644 --- a/doc/connectivity/bluetooth/api/shell/cap.rst +++ b/doc/connectivity/bluetooth/api/shell/cap.rst @@ -233,10 +233,14 @@ the optionally included CSIS instance by calling (:code:`cap_commander discover` cap_commander --help cap_commander - Bluetooth CAP commander shell commands Subcommands: - discover :Discover CAS - change_volume :Change volume on all connections - change_volume_offset :Change volume offset per connection + discover :Discover CAS + change_volume :Change volume on all connections + change_volume_mute :Change volume mute state on all connections + change_volume_offset :Change volume offset per connection + change_microphone_mute :Change microphone mute state on all connections + change_microphone_gain :Change microphone gain per connection Before being able to perform any stream operation, the device must also perform the @@ -340,6 +344,40 @@ Setting the volume mute on all connected devices VCP unmute done Volume mute change completed +Setting the microphone mute on all connected devices +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. code-block:: console + + uart:~$ bt connect + Connected: + uart:~$ cap_commander discover + discovery completed with CSIS + uart:~$ micp_mic_ctlr discover + MICP discover done with 1 VOCS and 1 AICS + uart:~$ + uart:~$ bt connect + Connected: + uart:~$ cap_commander discover + discovery completed with CSIS + uart:~$ micp_mic_ctlr discover + MICP discover done with 1 VOCS and 1 AICS + uart:~$ + uart:~$ cap_commander change_microphone_mute 1 + Setting microphone mute to 1 on 2 connections + MICP microphone 100, mute 1 + MICP mute done + MICP microphone 100, mute 1 + MICP mute done + Microphone mute change completed + uart:~$ cap_commander change_microphone_mute 0 + Setting microphone mute to 0 on 2 connections + MICP microphone 100, mute 0 + MICP unmute done + MICP microphone 100, mute 0 + MICP unmute done + Microphone mute change completed + Setting the microphone gain on one or more devices ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The gains are set by connection index, so connection index 0 gets the first offset, diff --git a/subsys/bluetooth/audio/shell/cap_commander.c b/subsys/bluetooth/audio/shell/cap_commander.c index af65e2eeafc..b65ec319c45 100644 --- a/subsys/bluetooth/audio/shell/cap_commander.c +++ b/subsys/bluetooth/audio/shell/cap_commander.c @@ -63,6 +63,16 @@ static void cap_volume_offset_changed_cb(struct bt_conn *conn, int err) #endif /* CONFIG_BT_VCP_VOL_CTLR */ #if defined(CONFIG_BT_MICP_MIC_CTLR) +static void cap_microphone_mute_changed_cb(struct bt_conn *conn, int err) +{ + if (err != 0) { + shell_error(ctx_shell, "Microphone mute change failed (%d)", err); + return; + } + + shell_print(ctx_shell, "Microphone mute change completed"); +} + #if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) static void cap_microphone_gain_changed_cb(struct bt_conn *conn, int err) { @@ -86,6 +96,7 @@ static struct bt_cap_commander_cb cbs = { #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ #if defined(CONFIG_BT_MICP_MIC_CTLR) + .microphone_mute_changed = cap_microphone_mute_changed_cb, #if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) .microphone_gain_changed = cap_microphone_gain_changed_cb, #endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */ @@ -319,6 +330,58 @@ static int cmd_cap_commander_change_volume_offset(const struct shell *sh, size_t #endif /* CONFIG_BT_VCP_VOL_CTLR */ #if defined(CONFIG_BT_MICP_MIC_CTLR) +static int cmd_cap_commander_change_microphone_mute(const struct shell *sh, size_t argc, + char *argv[]) +{ + struct bt_conn *connected_conns[CONFIG_BT_MAX_CONN] = {0}; + union bt_cap_set_member members[CONFIG_BT_MAX_CONN] = {0}; + struct bt_cap_commander_change_microphone_mute_state_param param = { + .members = members, + .type = BT_CAP_SET_TYPE_AD_HOC, /* TODO: Add support for coordinated sets */ + }; + int err = 0; + + if (default_conn == NULL) { + shell_error(sh, "Not connected"); + return -ENOEXEC; + } + + param.mute = shell_strtobool(argv[1], 10, &err); + if (err != 0) { + shell_error(sh, "Failed to parse microphone mute from %s", argv[1]); + + return -ENOEXEC; + } + + /* Populate the array of connected connections */ + bt_conn_foreach(BT_CONN_TYPE_LE, populate_connected_conns, (void *)connected_conns); + + param.count = 0U; + param.members = members; + for (size_t i = 0; i < ARRAY_SIZE(connected_conns); i++) { + struct bt_conn *conn = connected_conns[i]; + + if (conn == NULL) { + break; + } + + param.members[i].member = conn; + param.count++; + } + + shell_print(sh, "Setting microphone mute to %d on %zu connections", param.mute, + param.count); + + err = bt_cap_commander_change_microphone_mute_state(¶m); + if (err != 0) { + shell_print(sh, "Failed to change microphone mute: %d", err); + + return -ENOEXEC; + } + + return 0; +} + #if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) static int cmd_cap_commander_change_microphone_gain(const struct shell *sh, size_t argc, char *argv[]) @@ -422,6 +485,9 @@ SHELL_STATIC_SUBCMD_SET_CREATE( #endif /* CONFIG_BT_VCP_VOL_CTLR_VOCS */ #endif /* CONFIG_BT_VCP_VOL_CTLR */ #if defined(CONFIG_BT_MICP_MIC_CTLR) + SHELL_CMD_ARG(change_microphone_mute, NULL, + "Change microphone mute state on all connections ", + cmd_cap_commander_change_microphone_mute, 2, 0), #if defined(CONFIG_BT_MICP_MIC_CTLR_AICS) SHELL_CMD_ARG(change_microphone_gain, NULL, "Change microphone gain per connection ", From 7bededbc291dae0f73c1a9b79bc8015d928d6d33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 6 Feb 2024 13:44:09 +0100 Subject: [PATCH 1895/2402] drivers: serial: nrfx_uarte2: Fix re-enabling the receiver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move providing of the first buffer in uart_rx_enable from that function to the callback which is called from nrfx_uarte_rx_enable context. By doing this nrfx_uarte_rx_buffer_set is called when RX configuration flags are already known to the driver. Signed-off-by: Krzysztof Chruściński --- drivers/serial/uart_nrfx_uarte2.c | 42 ++++++++++++++++++++++++------- 1 file changed, 33 insertions(+), 9 deletions(-) diff --git a/drivers/serial/uart_nrfx_uarte2.c b/drivers/serial/uart_nrfx_uarte2.c index 750c211efb0..cf109c32d8e 100644 --- a/drivers/serial/uart_nrfx_uarte2.c +++ b/drivers/serial/uart_nrfx_uarte2.c @@ -115,6 +115,9 @@ struct uarte_async_data { uart_callback_t user_callback; void *user_data; + uint8_t *en_rx_buf; + size_t en_rx_len; + struct k_timer tx_timer; struct k_timer rx_timer; @@ -288,6 +291,22 @@ static void on_rx_buf_req(const struct device *dev) struct uarte_async_data *adata = data->async; const nrfx_uarte_t *nrfx_dev = get_nrfx_dev(dev); + /* If buffer is not null it indicates that event comes from RX enabling + * function context. We need to pass provided buffer to the driver. + */ + if (adata->en_rx_buf) { + uint8_t *buf = adata->en_rx_buf; + size_t len = adata->en_rx_len; + nrfx_err_t err; + + adata->en_rx_buf = NULL; + adata->en_rx_len = 0; + + err = nrfx_uarte_rx_buffer_set(nrfx_dev, buf, len); + __ASSERT_NO_MSG(err == NRFX_SUCCESS); + return; + } + struct uart_event evt = { .type = UART_RX_BUF_REQUEST }; @@ -296,8 +315,6 @@ static void on_rx_buf_req(const struct device *dev) * reception of one buffer was terminated to restart another transfer. */ if (!K_TIMEOUT_EQ(adata->rx_timeout, K_NO_WAIT)) { - /* Read and clear any pending new data information. */ - nrfx_uarte_rx_new_data_check(nrfx_dev); nrfx_uarte_rxdrdy_enable(nrfx_dev); } data->async->user_callback(dev, &evt, data->async->user_data); @@ -469,22 +486,28 @@ static int api_rx_enable(const struct device *dev, uint8_t *buf, size_t len, int if (timeout != SYS_FOREVER_US) { adata->idle_cnt = RX_TIMEOUT_DIV + 1; adata->rx_timeout = K_USEC(timeout / RX_TIMEOUT_DIV); + nrfx_uarte_rxdrdy_enable(nrfx_dev); } else { adata->rx_timeout = K_NO_WAIT; } - err = nrfx_uarte_rx_buffer_set(nrfx_dev, buf, len); - if (err != NRFX_SUCCESS) { - return -EIO; - } + /* Store the buffer. It will be passed to the driver in the event handler. + * We do that instead of calling nrfx_uarte_rx_buffer_set here to ensure + * that nrfx_uarte_rx_buffer_set is called when RX enable configuration + * flags are already known to the driver (e.g. if flushed data shall be + * kept or not). + */ + adata->en_rx_buf = buf; + adata->en_rx_len = len; + + atomic_or(&data->flags, UARTE_DATA_FLAG_RX_ENABLED); err = nrfx_uarte_rx_enable(nrfx_dev, flags); if (err != NRFX_SUCCESS) { + atomic_and(&data->flags, ~UARTE_DATA_FLAG_RX_ENABLED); return (err == NRFX_ERROR_BUSY) ? -EBUSY : -EIO; } - atomic_or(&data->flags, UARTE_DATA_FLAG_RX_ENABLED); - return 0; } @@ -932,7 +955,8 @@ static int uarte_nrfx_pm_action(const struct device *dev, UARTE_MEMORY_SECTION(idx) __aligned(4); \ static nrfx_uarte_rx_cache_t uarte##idx##_rx_cache_scratch; \ IF_ENABLED(CONFIG_UART_##idx##_INTERRUPT_DRIVEN, \ - (static uint8_t a2i_rx_buf##idx[CONFIG_UART_##idx##_A2I_RX_SIZE];)) \ + (static uint8_t a2i_rx_buf##idx[CONFIG_UART_##idx##_A2I_RX_SIZE] \ + UARTE_MEMORY_SECTION(idx) __aligned(4);)) \ PINCTRL_DT_DEFINE(UARTE(idx)); \ static const struct uart_async_to_irq_config uarte_a2i_config_##idx = \ UART_ASYNC_TO_IRQ_API_CONFIG_INITIALIZER(&a2i_api, \ From 362389ee170115149fad78090f72eed80486f6c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 6 Feb 2024 13:59:14 +0100 Subject: [PATCH 1896/2402] tests: drivers: uart: Re-enabling some tests on nrf52_bsim MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tests which were using the new nordic UART shim where failing on the bsim targets. They are now fixed and tests can be re-enabled. Signed-off-by: Krzysztof Chruściński --- tests/drivers/uart/uart_async_api/testcase.yaml | 1 - tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml | 3 --- 2 files changed, 4 deletions(-) diff --git a/tests/drivers/uart/uart_async_api/testcase.yaml b/tests/drivers/uart/uart_async_api/testcase.yaml index 84bbd9c439b..a3665f7c570 100644 --- a/tests/drivers/uart/uart_async_api/testcase.yaml +++ b/tests/drivers/uart/uart_async_api/testcase.yaml @@ -34,7 +34,6 @@ tests: depends_on: gpio extra_configs: - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=n - tags: bsim_skip_CI drivers.uart.async_api.nrf_uart: filter: CONFIG_SERIAL_SUPPORT_ASYNC harness: ztest diff --git a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml index 4cb6c5d1308..39a55a4a62a 100644 --- a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml +++ b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml @@ -20,7 +20,6 @@ tests: - CONFIG_UART_ASYNC_API=n - CONFIG_UART_0_ENHANCED_POLL_OUT=n - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=n - tags: bsim_skip_CI drivers.uart.uart_mix_poll_fifo: extra_configs: @@ -28,7 +27,6 @@ tests: - CONFIG_UART_0_INTERRUPT_DRIVEN=y - CONFIG_UART_0_ENHANCED_POLL_OUT=n - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=n - tags: bsim_skip_CI drivers.uart.uart_mix_poll_async_api: extra_configs: @@ -37,7 +35,6 @@ tests: - CONFIG_UART_0_ASYNC=y - CONFIG_UART_0_ENHANCED_POLL_OUT=n - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=n - tags: bsim_skip_CI drivers.uart.uart_mix_poll_async_api_const: extra_args: TEST_CONST_BUFFER=1 From 9e8e21b36f87cb6ccec2a66a2f516f3fd2e02bbf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 3 Apr 2024 11:38:07 +0200 Subject: [PATCH 1897/2402] drivers: ieee802154: use sys_rand_get directly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use sys_rand_get() directly. Signed-off-by: Fin Maaß --- drivers/ieee802154/ieee802154_b91.c | 6 +----- drivers/ieee802154/ieee802154_cc1200.c | 4 +--- drivers/ieee802154/ieee802154_cc2520.c | 4 +--- drivers/ieee802154/ieee802154_dw1000.c | 5 +---- drivers/ieee802154/ieee802154_kw41z.c | 6 +----- drivers/ieee802154/ieee802154_mcr20a.c | 5 +---- drivers/ieee802154/ieee802154_rf2xx.c | 5 +---- drivers/ieee802154/ieee802154_uart_pipe.c | 3 +-- 8 files changed, 8 insertions(+), 30 deletions(-) diff --git a/drivers/ieee802154/ieee802154_b91.c b/drivers/ieee802154/ieee802154_b91.c index e44c99888dd..0a28af4715d 100644 --- a/drivers/ieee802154/ieee802154_b91.c +++ b/drivers/ieee802154/ieee802154_b91.c @@ -110,11 +110,7 @@ static inline uint8_t *b91_get_mac(const struct device *dev) struct b91_data *b91 = dev->data; #if defined(CONFIG_IEEE802154_B91_RANDOM_MAC) - uint32_t *ptr = (uint32_t *)(b91->mac_addr); - - UNALIGNED_PUT(sys_rand32_get(), ptr); - ptr = (uint32_t *)(b91->mac_addr + 4); - UNALIGNED_PUT(sys_rand32_get(), ptr); + sys_rand_get(b91->mac_addr, sizeof(b91->mac_addr)); /* * Clear bit 0 to ensure it isn't a multicast address and set diff --git a/drivers/ieee802154/ieee802154_cc1200.c b/drivers/ieee802154/ieee802154_cc1200.c index 7bc3aa3ed12..50dad26faee 100644 --- a/drivers/ieee802154/ieee802154_cc1200.c +++ b/drivers/ieee802154/ieee802154_cc1200.c @@ -129,9 +129,7 @@ static inline uint8_t *get_mac(const struct device *dev) struct cc1200_context *cc1200 = dev->data; #if defined(CONFIG_IEEE802154_CC1200_RANDOM_MAC) - uint32_t *ptr = (uint32_t *)(cc1200->mac_addr + 4); - - UNALIGNED_PUT(sys_rand32_get(), ptr); + sys_rand_get(&cc1200->mac_addr[4], 4U); cc1200->mac_addr[7] = (cc1200->mac_addr[7] & ~0x01) | 0x02; #else diff --git a/drivers/ieee802154/ieee802154_cc2520.c b/drivers/ieee802154/ieee802154_cc2520.c index 1f86d20d02f..b1c7dd699e7 100644 --- a/drivers/ieee802154/ieee802154_cc2520.c +++ b/drivers/ieee802154/ieee802154_cc2520.c @@ -279,9 +279,7 @@ static inline uint8_t *get_mac(const struct device *dev) struct cc2520_context *cc2520 = dev->data; #if defined(CONFIG_IEEE802154_CC2520_RANDOM_MAC) - uint32_t *ptr = (uint32_t *)(cc2520->mac_addr + 4); - - UNALIGNED_PUT(sys_rand32_get(), ptr); + sys_rand_get(&cc2520->mac_addr[4], 4U); cc2520->mac_addr[7] = (cc2520->mac_addr[7] & ~0x01) | 0x02; #else diff --git a/drivers/ieee802154/ieee802154_dw1000.c b/drivers/ieee802154/ieee802154_dw1000.c index 13d5e047544..b0e06488731 100644 --- a/drivers/ieee802154/ieee802154_dw1000.c +++ b/drivers/ieee802154/ieee802154_dw1000.c @@ -1633,11 +1633,8 @@ static int dw1000_init(const struct device *dev) static inline uint8_t *get_mac(const struct device *dev) { struct dwt_context *dw1000 = dev->data; - uint32_t *ptr = (uint32_t *)(dw1000->mac_addr); - UNALIGNED_PUT(sys_rand32_get(), ptr); - ptr = (uint32_t *)(dw1000->mac_addr + 4); - UNALIGNED_PUT(sys_rand32_get(), ptr); + sys_rand_get(dw1000->mac_addr, sizeof(dw1000->mac_addr)); dw1000->mac_addr[0] = (dw1000->mac_addr[0] & ~0x01) | 0x02; diff --git a/drivers/ieee802154/ieee802154_kw41z.c b/drivers/ieee802154/ieee802154_kw41z.c index 40064c6df7b..244d350b215 100644 --- a/drivers/ieee802154/ieee802154_kw41z.c +++ b/drivers/ieee802154/ieee802154_kw41z.c @@ -935,11 +935,7 @@ static inline uint8_t *get_mac(const struct device *dev) * and how to allow for a OUI portion? */ - uint32_t *ptr = (uint32_t *)(kw41z->mac_addr); - - UNALIGNED_PUT(sys_rand32_get(), ptr); - ptr = (uint32_t *)(kw41z->mac_addr + 4); - UNALIGNED_PUT(sys_rand32_get(), ptr); + sys_rand_get(kw41z->mac_addr, sizeof(kw41z->mac_addr)); /* * Clear bit 0 to ensure it isn't a multicast address and set diff --git a/drivers/ieee802154/ieee802154_mcr20a.c b/drivers/ieee802154/ieee802154_mcr20a.c index 2e6ed142861..a57de53754e 100644 --- a/drivers/ieee802154/ieee802154_mcr20a.c +++ b/drivers/ieee802154/ieee802154_mcr20a.c @@ -515,11 +515,8 @@ static inline int16_t mcr20a_get_rssi(uint8_t lqi) static inline uint8_t *get_mac(const struct device *dev) { struct mcr20a_context *mcr20a = dev->data; - uint32_t *ptr = (uint32_t *)(mcr20a->mac_addr); - UNALIGNED_PUT(sys_rand32_get(), ptr); - ptr = (uint32_t *)(mcr20a->mac_addr + 4); - UNALIGNED_PUT(sys_rand32_get(), ptr); + sys_rand_get(mcr20a->mac_addr, sizeof(mcr20a->mac_addr)); mcr20a->mac_addr[0] = (mcr20a->mac_addr[0] & ~0x01) | 0x02; diff --git a/drivers/ieee802154/ieee802154_rf2xx.c b/drivers/ieee802154/ieee802154_rf2xx.c index 4d7c188ce67..1dd00c213ba 100644 --- a/drivers/ieee802154/ieee802154_rf2xx.c +++ b/drivers/ieee802154/ieee802154_rf2xx.c @@ -347,12 +347,9 @@ static inline uint8_t *get_mac(const struct device *dev) { const struct rf2xx_config *conf = dev->config; struct rf2xx_context *ctx = dev->data; - uint32_t *ptr = (uint32_t *)(ctx->mac_addr); if (!conf->has_mac) { - UNALIGNED_PUT(sys_rand32_get(), ptr); - ptr = (uint32_t *)(ctx->mac_addr + 4); - UNALIGNED_PUT(sys_rand32_get(), ptr); + sys_rand_get(ctx->mac_addr, sizeof(ctx->mac_addr)); } /* diff --git a/drivers/ieee802154/ieee802154_uart_pipe.c b/drivers/ieee802154/ieee802154_uart_pipe.c index ff8b27f88f7..5a5333cab78 100644 --- a/drivers/ieee802154/ieee802154_uart_pipe.c +++ b/drivers/ieee802154/ieee802154_uart_pipe.c @@ -357,8 +357,7 @@ static inline uint8_t *get_mac(const struct device *dev) upipe->mac_addr[3] = 0x30; #if defined(CONFIG_IEEE802154_UPIPE_RANDOM_MAC) - UNALIGNED_PUT(sys_cpu_to_be32(sys_rand32_get()), - (uint32_t *) ((uint8_t *)upipe->mac_addr+4)); + sys_rand_get(&upipe->mac_addr[4], 4U); #else upipe->mac_addr[4] = CONFIG_IEEE802154_UPIPE_MAC4; upipe->mac_addr[5] = CONFIG_IEEE802154_UPIPE_MAC5; From 792cbb9a2431f3c47913949666db6b5ed18137dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 3 Apr 2024 11:41:06 +0200 Subject: [PATCH 1898/2402] drivers: ethernet: use sys_rand_get directly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use sys_rand_get() directly. Signed-off-by: Fin Maaß --- drivers/ethernet/eth.h | 8 +------- drivers/ethernet/eth_ivshmem.c | 5 +---- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/ethernet/eth.h b/drivers/ethernet/eth.h index ebbff29a9d9..f7e7ab79a4a 100644 --- a/drivers/ethernet/eth.h +++ b/drivers/ethernet/eth.h @@ -32,10 +32,6 @@ static inline void gen_random_mac(uint8_t *mac_addr, uint8_t b0, uint8_t b1, uint8_t b2) { - uint32_t entropy; - - entropy = sys_rand32_get(); - mac_addr[0] = b0; mac_addr[1] = b1; mac_addr[2] = b2; @@ -43,9 +39,7 @@ static inline void gen_random_mac(uint8_t *mac_addr, uint8_t b0, uint8_t b1, uin /* Set MAC address locally administered, unicast (LAA) */ mac_addr[0] |= 0x02; - mac_addr[3] = (entropy >> 16) & 0xff; - mac_addr[4] = (entropy >> 8) & 0xff; - mac_addr[5] = (entropy >> 0) & 0xff; + sys_rand_get(&mac_addr[3], 3U); } #endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_H_ */ diff --git a/drivers/ethernet/eth_ivshmem.c b/drivers/ethernet/eth_ivshmem.c index 0d2c104359a..ae8135f2e22 100644 --- a/drivers/ethernet/eth_ivshmem.c +++ b/drivers/ethernet/eth_ivshmem.c @@ -390,10 +390,7 @@ static const struct ethernet_api eth_ivshmem_api = { #define ETH_IVSHMEM_RANDOM_MAC_ADDR(inst) \ static void generate_mac_addr_##inst(uint8_t mac_addr[6]) \ { \ - uint32_t entropy = sys_rand32_get(); \ - mac_addr[0] = (entropy >> 16) & 0xff; \ - mac_addr[1] = (entropy >> 8) & 0xff; \ - mac_addr[2] = (entropy >> 0) & 0xff; \ + sys_rand_get(mac_addr, 3U); \ /* Clear multicast bit */ \ mac_addr[0] &= 0xFE; \ gen_random_mac(mac_addr, mac_addr[0], mac_addr[1], mac_addr[2]); \ From 19df6cd9b1d361d90a261548ba8bdbc194e9c067 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 3 Apr 2024 11:42:12 +0200 Subject: [PATCH 1899/2402] drivers: modem: use sys_rand_get directly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use sys_rand_get() directly. Signed-off-by: Fin Maaß --- drivers/modem/wncm14a2a.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/modem/wncm14a2a.c b/drivers/modem/wncm14a2a.c index 5b60d0aaff5..12b9b4b341a 100644 --- a/drivers/modem/wncm14a2a.c +++ b/drivers/modem/wncm14a2a.c @@ -1760,8 +1760,7 @@ static inline uint8_t *wncm14a2a_get_mac(const struct device *dev) ctx->mac_addr[0] = 0x00; ctx->mac_addr[1] = 0x10; - UNALIGNED_PUT(sys_cpu_to_be32(sys_rand32_get()), - (uint32_t *)(ctx->mac_addr + 2)); + sys_rand_get(&ctx->mac_addr[2], 4U); return ctx->mac_addr; } From 3ffad11b22848d783d23082e4ee18428a8972cea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 3 Apr 2024 11:43:23 +0200 Subject: [PATCH 1900/2402] drivers: net: use sys_rand8_get MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use sys_rand8_get() instant of sys_rand32_get(). Signed-off-by: Fin Maaß --- drivers/net/ppp.c | 2 +- drivers/net/slip.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ppp.c b/drivers/net/ppp.c index a40efda0fbb..7904612b9a4 100644 --- a/drivers/net/ppp.c +++ b/drivers/net/ppp.c @@ -1026,7 +1026,7 @@ static void ppp_iface_init(struct net_if *iface) ppp->mac_addr[2] = 0x5E; ppp->mac_addr[3] = 0x00; ppp->mac_addr[4] = 0x53; - ppp->mac_addr[5] = sys_rand32_get(); + ppp->mac_addr[5] = sys_rand8_get(); } net_if_set_link_addr(iface, ll_addr->addr, ll_addr->len, diff --git a/drivers/net/slip.c b/drivers/net/slip.c index cf1fef83041..c9f9fd7bb62 100644 --- a/drivers/net/slip.c +++ b/drivers/net/slip.c @@ -407,7 +407,7 @@ void slip_iface_init(struct net_if *iface) slip->mac_addr[2] = 0x5E; slip->mac_addr[3] = 0x00; slip->mac_addr[4] = 0x53; - slip->mac_addr[5] = sys_rand32_get(); + slip->mac_addr[5] = sys_rand8_get(); } net_if_set_link_addr(iface, ll_addr->addr, ll_addr->len, NET_LINK_ETHERNET); From 295aa36e6036d875f877028cee4ee0a993d851ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 3 Apr 2024 11:44:10 +0200 Subject: [PATCH 1901/2402] jwt: use sys_rand_get directly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use sys_rand_get() directly. Signed-off-by: Fin Maaß --- subsys/jwt/jwt.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/subsys/jwt/jwt.c b/subsys/jwt/jwt.c index 0db2426195b..a72c85ddc70 100644 --- a/subsys/jwt/jwt.c +++ b/subsys/jwt/jwt.c @@ -255,11 +255,7 @@ static int setup_prng(void) uint8_t entropy[TC_AES_KEY_SIZE + TC_AES_BLOCK_SIZE]; - for (int i = 0; i < sizeof(entropy); i += sizeof(uint32_t)) { - uint32_t rv = sys_rand32_get(); - - memcpy(entropy + i, &rv, sizeof(uint32_t)); - } + sys_rand_get(entropy, sizeof(entropy)); int res = tc_ctr_prng_init(&prng_state, (const uint8_t *) &entropy, sizeof(entropy), From a1ea9b73516cebb1591cac343277c2667e7d934b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 3 Apr 2024 11:54:52 +0200 Subject: [PATCH 1902/2402] net: use appropriate sys_randX_get() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use the appropriate sys_randX_get() instant of always sys_rand32_get(). Signed-off-by: Fin Maaß --- subsys/net/ip/icmp.c | 2 +- subsys/net/ip/ipv4_autoconf.c | 4 ++-- subsys/net/ip/ipv4_fragment.c | 2 +- subsys/net/ip/net_context.c | 2 +- subsys/net/l2/ethernet/gptp/gptp.c | 8 ++++---- subsys/net/l2/virtual/virtual.c | 6 +----- subsys/net/lib/dhcpv4/dhcpv4.c | 2 +- subsys/net/lib/dns/resolve.c | 2 +- 8 files changed, 12 insertions(+), 16 deletions(-) diff --git a/subsys/net/ip/icmp.c b/subsys/net/ip/icmp.c index 322801132df..4d81d227d80 100644 --- a/subsys/net/ip/icmp.c +++ b/subsys/net/ip/icmp.c @@ -360,7 +360,7 @@ static struct net_icmp_ping_params *get_default_params(void) { static struct net_icmp_ping_params params = { 0 }; - params.identifier = sys_rand32_get(); + params.identifier = sys_rand16_get(); return ¶ms; } diff --git a/subsys/net/ip/ipv4_autoconf.c b/subsys/net/ip/ipv4_autoconf.c index e34b51523c3..c9b21e79ac4 100644 --- a/subsys/net/ip/ipv4_autoconf.c +++ b/subsys/net/ip/ipv4_autoconf.c @@ -199,8 +199,8 @@ static void ipv4_autoconf_send(struct net_if_ipv4_autoconf *ipv4auto) (void)memset(&ipv4auto->current_ip, 0, sizeof(struct in_addr)); ipv4auto->requested_ip.s4_addr[0] = 169U; ipv4auto->requested_ip.s4_addr[1] = 254U; - ipv4auto->requested_ip.s4_addr[2] = sys_rand32_get() % 254; - ipv4auto->requested_ip.s4_addr[3] = sys_rand32_get() % 254; + ipv4auto->requested_ip.s4_addr[2] = sys_rand8_get() % 254; + ipv4auto->requested_ip.s4_addr[3] = sys_rand8_get() % 254; NET_DBG("%s: Starting probe for 169.254.%d.%d", "Init", ipv4auto->requested_ip.s4_addr[2], diff --git a/subsys/net/ip/ipv4_fragment.c b/subsys/net/ip/ipv4_fragment.c index ee6e43c83d3..56572626a94 100644 --- a/subsys/net/ip/ipv4_fragment.c +++ b/subsys/net/ip/ipv4_fragment.c @@ -538,7 +538,7 @@ int net_ipv4_send_fragmented_pkt(struct net_if *iface, struct net_pkt *pkt, } /* Generate a random ID to be used for packet identification, ensuring that it is not 0 */ - uint16_t rand_id = (uint16_t)sys_rand32_get(); + uint16_t rand_id = sys_rand16_get(); if (rand_id == 0) { rand_id = 1; diff --git a/subsys/net/ip/net_context.c b/subsys/net/ip/net_context.c index 6bf60bc0e37..5ec66ee7240 100644 --- a/subsys/net/ip/net_context.c +++ b/subsys/net/ip/net_context.c @@ -312,7 +312,7 @@ static uint16_t find_available_port(struct net_context *context, uint16_t local_port; do { - local_port = sys_rand32_get() | 0x8000; + local_port = sys_rand16_get() | 0x8000; } while (check_used_port(NULL, net_context_get_proto(context), htons(local_port), addr, false, false) == -EEXIST); diff --git a/subsys/net/l2/ethernet/gptp/gptp.c b/subsys/net/l2/ethernet/gptp/gptp.c index 1b45166b5e9..38f20fd34fd 100644 --- a/subsys/net/l2/ethernet/gptp/gptp.c +++ b/subsys/net/l2/ethernet/gptp/gptp.c @@ -490,10 +490,10 @@ static void gptp_init_port_ds(int port) port_ds->compute_neighbor_prop_delay = true; /* Random Sequence Numbers. */ - port_ds->sync_seq_id = (uint16_t)sys_rand32_get(); - port_ds->pdelay_req_seq_id = (uint16_t)sys_rand32_get(); - port_ds->announce_seq_id = (uint16_t)sys_rand32_get(); - port_ds->signaling_seq_id = (uint16_t)sys_rand32_get(); + port_ds->sync_seq_id = sys_rand16_get(); + port_ds->pdelay_req_seq_id = sys_rand16_get(); + port_ds->announce_seq_id = sys_rand16_get(); + port_ds->signaling_seq_id = sys_rand16_get(); #if defined(CONFIG_NET_GPTP_STATISTICS) /* Initialize stats data set. */ diff --git a/subsys/net/l2/virtual/virtual.c b/subsys/net/l2/virtual/virtual.c index 7044665ae8e..7a106969f01 100644 --- a/subsys/net/l2/virtual/virtual.c +++ b/subsys/net/l2/virtual/virtual.c @@ -169,11 +169,7 @@ NET_L2_INIT(VIRTUAL_L2, virtual_recv, virtual_send, virtual_enable, static void random_linkaddr(uint8_t *linkaddr, size_t len) { - int i; - - for (i = 0; i < len; i++) { - linkaddr[i] = sys_rand32_get(); - } + sys_rand_get(linkaddr, len); linkaddr[0] |= 0x02; /* force LAA bit */ } diff --git a/subsys/net/lib/dhcpv4/dhcpv4.c b/subsys/net/lib/dhcpv4/dhcpv4.c index b278d95401f..e1db51ebfcd 100644 --- a/subsys/net/lib/dhcpv4/dhcpv4.c +++ b/subsys/net/lib/dhcpv4/dhcpv4.c @@ -407,7 +407,7 @@ static uint32_t dhcpv4_update_message_timeout(struct net_if_dhcpv4 *dhcpv4) } /* +1/-1 second randomization */ - timeout += (sys_rand32_get() % 3U) - 1; + timeout += (sys_rand8_get() % 3U) - 1; dhcpv4->attempts++; dhcpv4_set_timeout(dhcpv4, timeout); diff --git a/subsys/net/lib/dns/resolve.c b/subsys/net/lib/dns/resolve.c index a1e367f5ec5..37032f4de45 100644 --- a/subsys/net/lib/dns/resolve.c +++ b/subsys/net/lib/dns/resolve.c @@ -1245,7 +1245,7 @@ int dns_resolve_name(struct dns_resolve_context *ctx, goto quit; } - ctx->queries[i].id = sys_rand32_get(); + ctx->queries[i].id = sys_rand16_get(); /* If mDNS is enabled, then send .local queries only to multicast * address. For mDNS the id should be set to 0, see RFC 6762 ch. 18.1 From 17ed60f0b52a63533a476db9c51758b53c88eaef Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Thu, 21 Mar 2024 10:17:12 +0100 Subject: [PATCH 1903/2402] dts: nordic: nrf54h20: add ccm030 Add node for CCM030 instance (AES CCM mode encryption). Signed-off-by: Gerard Marull-Paretas --- dts/common/nordic/nrf54h20.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/dts/common/nordic/nrf54h20.dtsi b/dts/common/nordic/nrf54h20.dtsi index 78e4c5b6549..a0085496456 100644 --- a/dts/common/nordic/nrf54h20.dtsi +++ b/dts/common/nordic/nrf54h20.dtsi @@ -266,6 +266,13 @@ }; }; + ccm030: ccm@3a000 { + compatible = "nordic,nrf-ccm"; + reg = <0x3a000 0x1000>; + interrupts = <58 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + ecb030: ecb@3b000 { compatible = "nordic,nrf-ecb"; reg = <0x3b000 0x1000>; From 37f9958feae607a4a2f5c69219241b0348e115c6 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Thu, 21 Mar 2024 10:18:24 +0100 Subject: [PATCH 1904/2402] soc: nordic: nrf54h: set DMASEC for CCM030 if enabled DMASEC is set to non-secure by default, which prevents CCM from accessing secure memory. Change DMASEC to secure. Signed-off-by: Gerard Marull-Paretas --- soc/nordic/nrf54h/soc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/soc/nordic/nrf54h/soc.c b/soc/nordic/nrf54h/soc.c index cf134dc99b1..1d071f96b20 100644 --- a/soc/nordic/nrf54h/soc.c +++ b/soc/nordic/nrf54h/soc.c @@ -12,6 +12,7 @@ #include #include +#include #include LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); @@ -26,6 +27,12 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); DT_REG_ADDR(DT_PHANDLE_BY_NAME(node_id, nordic_ficrs, name)) + \ DT_PHA_BY_NAME(node_id, nordic_ficrs, name, offset) +#define SPU_INSTANCE_GET(p_addr) \ + ((NRF_SPU_Type *)((p_addr) & (ADDRESS_REGION_Msk | \ + ADDRESS_SECURITY_Msk | \ + ADDRESS_DOMAIN_Msk | \ + ADDRESS_BUS_Msk))) + static void power_domain_init(void) { /* @@ -83,6 +90,16 @@ static int nordicsemi_nrf54h_init(void) trim_hsfll(); +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ccm030), okay) + /* DMASEC is set to non-secure by default, which prevents CCM from + * accessing secure memory. Change DMASEC to secure. + */ + uint32_t ccm030_addr = DT_REG_ADDR(DT_NODELABEL(ccm030)); + NRF_SPU_Type *spu = SPU_INSTANCE_GET(ccm030_addr); + + nrf_spu_periph_perm_dmasec_set(spu, nrf_address_slave_get(ccm030_addr), true); +#endif + return 0; } From fe57a12cf23845ca501e822c50edd2ba8b80e846 Mon Sep 17 00:00:00 2001 From: Lucas Tamborrino Date: Tue, 5 Mar 2024 11:19:27 -0300 Subject: [PATCH 1905/2402] drivers: esp32: update to hal_espressif v5.1 Modify necessary drivers to meet updated hal. Signed-off-by: Lucas Tamborrino Signed-off-by: Sylvio Alves --- drivers/adc/adc_esp32.c | 31 +- drivers/clock_control/clock_control_esp32.c | 70 ++--- drivers/counter/counter_esp32_tmr.c | 60 ++-- drivers/dac/dac_esp32.c | 8 +- drivers/dma/dma_esp32_gdma.c | 31 +- drivers/entropy/entropy_esp32.c | 4 +- drivers/ethernet/eth_esp32.c | 5 +- drivers/flash/flash_esp32.c | 49 +--- drivers/i2c/i2c_esp32.c | 176 ++++++----- drivers/interrupt_controller/intc_esp32.c | 126 +++++--- drivers/pwm/pwm_led_esp32.c | 10 +- drivers/pwm/pwm_mc_esp32.c | 38 +-- drivers/sensor/esp32_temp/esp32_temp.c | 2 +- drivers/serial/uart_esp32.c | 21 +- drivers/spi/spi_esp32_spim.c | 21 +- drivers/spi/spi_esp32_spim.h | 2 + drivers/timer/esp32_sys_timer.c | 23 +- drivers/wifi/esp32/Kconfig.esp32 | 125 +++++--- drivers/wifi/esp32/src/esp_wifi_drv.c | 309 ++++++++++++-------- include/zephyr/drivers/dma/dma_esp32.h | 28 +- 20 files changed, 660 insertions(+), 479 deletions(-) diff --git a/drivers/adc/adc_esp32.c b/drivers/adc/adc_esp32.c index 8e9c5aa74b9..9b47fdf6bd7 100644 --- a/drivers/adc/adc_esp32.c +++ b/drivers/adc/adc_esp32.c @@ -10,42 +10,27 @@ #include #include #include -#include +#include #include #include #include -#include "driver/periph_ctrl.h" #include LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL); -#if CONFIG_SOC_SERIES_ESP32 -#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_VREF #define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MIN_BITWIDTH #define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH +#if CONFIG_SOC_SERIES_ESP32 +#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_VREF /* Due to significant measurement discrepancy in higher voltage range, we * clip the value instead of yet another correction. The IDF implementation * for ESP32-S2 is doing it, so we copy that approach in Zephyr driver */ #define ADC_CLIP_MVOLT_11DB 2550 - -#elif CONFIG_SOC_SERIES_ESP32S2 -#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP -#define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH -#define ADC_RESOLUTION_MAX SOC_ADC_MAX_BITWIDTH - -#elif CONFIG_SOC_SERIES_ESP32C3 +#else #define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP -#define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH -#define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH - -#elif CONFIG_SOC_SERIES_ESP32S3 -#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP_FIT -#define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MIN_BITWIDTH -#define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH - #endif /* Convert resolution in bits to esp32 enum values */ @@ -64,9 +49,9 @@ struct adc_esp32_conf { }; struct adc_esp32_data { - adc_atten_t attenuation[ADC_CHANNEL_MAX]; - uint8_t resolution[ADC_CHANNEL_MAX]; - esp_adc_cal_characteristics_t chars[ADC_CHANNEL_MAX]; + adc_atten_t attenuation[SOC_ADC_MAX_CHANNEL_NUM]; + uint8_t resolution[SOC_ADC_MAX_CHANNEL_NUM]; + esp_adc_cal_characteristics_t chars[SOC_ADC_MAX_CHANNEL_NUM]; uint16_t meas_ref_internal; uint16_t *buffer; uint16_t *buffer_repeat; @@ -334,7 +319,7 @@ static const struct adc_driver_api api_esp32_driver_api = { #define ESP32_ADC_INIT(inst) \ \ static const struct adc_esp32_conf adc_esp32_conf_##inst = { \ - .unit = DT_PROP(DT_DRV_INST(inst), unit), \ + .unit = DT_PROP(DT_DRV_INST(inst), unit) - 1, \ .channel_count = DT_PROP(DT_DRV_INST(inst), channel_count), \ }; \ \ diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c index 4b8b01f521e..f38d780a42b 100644 --- a/drivers/clock_control/clock_control_esp32.c +++ b/drivers/clock_control/clock_control_esp32.c @@ -14,29 +14,29 @@ #undef CPU_RESET_REASON #define CPU_RESET_REASON SW_CPU_RESET #include -#include "esp32/rom/rtc.h" -#include "soc/dport_reg.h" +#include +#include #elif defined(CONFIG_SOC_SERIES_ESP32S2) #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 #include -#include "esp32s2/rom/rtc.h" -#include "soc/dport_reg.h" +#include +#include #elif defined(CONFIG_SOC_SERIES_ESP32S3) #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 #include -#include "esp32s3/rom/rtc.h" -#include "soc/dport_reg.h" -#include "esp32s3/clk.h" +#include +#include #elif CONFIG_SOC_SERIES_ESP32C3 #define DT_CPU_COMPAT espressif_riscv #include -#include "esp32c3/rom/rtc.h" +#include #include #include #include #endif /* CONFIG_SOC_SERIES_ESP32xx */ -#include "esp_rom_sys.h" +#include +#include #include #include #include @@ -44,8 +44,10 @@ #include #include #include -#include -#include +#include +#include +#include +#include struct esp32_clock_config { int clk_src_sel; @@ -54,21 +56,6 @@ struct esp32_clock_config { int xtal_div; }; -static uint8_t const xtal_freq[] = { -#if defined(CONFIG_SOC_SERIES_ESP32) || \ - defined(CONFIG_SOC_SERIES_ESP32S3) - [ESP32_CLK_XTAL_24M] = 24, - [ESP32_CLK_XTAL_26M] = 26, - [ESP32_CLK_XTAL_40M] = 40, - [ESP32_CLK_XTAL_AUTO] = 0 -#elif defined(CONFIG_SOC_SERIES_ESP32S2) - [ESP32_CLK_XTAL_40M] = 40, -#elif defined(CONFIG_SOC_SERIES_ESP32C3) - [ESP32_CLK_XTAL_32M] = 32, - [ESP32_CLK_XTAL_40M] = 40, -#endif -}; - static int clock_control_esp32_on(const struct device *dev, clock_control_subsys_t sys) { @@ -377,7 +364,7 @@ static void esp32_clock_perip_init(void) wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN | SYSTEM_WIFI_CLK_BT_EN_M | - SYSTEM_WIFI_CLK_UNUSED_BIT5 | + SYSTEM_WIFI_CLK_I2C_CLK_EN | SYSTEM_WIFI_CLK_UNUSED_BIT12 | SYSTEM_WIFI_CLK_SDIO_HOST_EN; } @@ -424,8 +411,14 @@ static void esp32_clock_perip_init(void) /* Enable RNG clock. */ periph_module_enable(PERIPH_RNG_MODULE); - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_set_clock_baudrate(0, UART_CLK_FREQ_ROM, 115200); + /* Enable TimerGroup 0 clock to ensure its reference counter will never + * be decremented to 0 during normal operation and preventing it from + * being disabled. + * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog + * registers (Flashboot protection included) will be reenabled, and some + * seconds later, will trigger an unintended reset. + */ + periph_module_enable(PERIPH_TIMG0_MODULE); } #endif /* CONFIG_SOC_SERIES_ESP32S3 */ @@ -472,7 +465,7 @@ static void esp32_clock_perip_init(void) wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN | SYSTEM_WIFI_CLK_BT_EN_M | - SYSTEM_WIFI_CLK_UNUSED_BIT5 | + SYSTEM_WIFI_CLK_I2C_CLK_EN | SYSTEM_WIFI_CLK_UNUSED_BIT12; } @@ -529,10 +522,10 @@ static int clock_control_esp32_init(const struct device *dev) if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) { rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT(); - clk_cfg.xtal_freq = xtal_freq[cfg->xtal_freq_sel]; + clk_cfg.xtal_freq = cfg->xtal_freq_sel; clk_cfg.cpu_freq_mhz = cfg->cpu_freq; - clk_cfg.slow_freq = rtc_clk_slow_freq_get(); - clk_cfg.fast_freq = rtc_clk_fast_freq_get(); + clk_cfg.slow_clk_src = rtc_clk_slow_freq_get(); + clk_cfg.fast_clk_src = rtc_clk_fast_freq_get(); rtc_clk_init(clk_cfg); } @@ -563,10 +556,19 @@ static int clock_control_esp32_init(const struct device *dev) rtc_clk_cpu_freq_set_config(&new_config); /* Re-calculate the ccount to make time calculation correct */ - cpu_hal_set_cycle_count((uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz); + esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz); esp32_clock_perip_init(); + uint32_t clock_hz = esp_clk_apb_freq(); +#if ESP_ROM_UART_CLK_IS_XTAL + clock_hz = esp_clk_xtal_freq(); +#endif + esp_rom_uart_tx_wait_idle(ESP_CONSOLE_UART_NUM); + +#if !defined(ESP_CONSOLE_UART_NONE) + esp_rom_uart_set_clock_baudrate(ESP_CONSOLE_UART_NUM, clock_hz, ESP_CONSOLE_UART_BAUDRATE); +#endif return 0; } diff --git a/drivers/counter/counter_esp32_tmr.c b/drivers/counter/counter_esp32_tmr.c index 77890f5e8fb..34d6b821875 100644 --- a/drivers/counter/counter_esp32_tmr.c +++ b/drivers/counter/counter_esp32_tmr.c @@ -9,10 +9,11 @@ /* Include esp-idf headers first to avoid redefining BIT() macro */ #include #include -#include +#include +#include #include -#include #include +#include #include #include #include @@ -80,22 +81,18 @@ static int counter_esp32_init(const struct device *dev) timer_hal_init(&data->hal_ctx, cfg->group, cfg->index); data->alarm_cfg.callback = NULL; - timer_hal_intr_disable(&data->hal_ctx); - timer_hal_clear_intr_status(&data->hal_ctx); - timer_hal_set_auto_reload(&data->hal_ctx, cfg->config.auto_reload); - timer_hal_set_divider(&data->hal_ctx, cfg->config.divider); - timer_hal_set_counter_increase(&data->hal_ctx, cfg->config.counter_dir); - timer_hal_set_alarm_enable(&data->hal_ctx, cfg->config.alarm_en); - if (cfg->config.intr_type == TIMER_INTR_LEVEL) { - timer_hal_set_level_int_enable(&data->hal_ctx, true); - } - timer_hal_set_counter_value(&data->hal_ctx, 0); - timer_hal_set_counter_enable(&data->hal_ctx, cfg->config.counter_en); - esp_intr_alloc(cfg->irq_source, - 0, - (ISR_HANDLER)counter_esp32_isr, - (void *)dev, - NULL); + timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id), + false); + timer_ll_clear_intr_status(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id)); + timer_ll_enable_auto_reload(data->hal_ctx.dev, data->hal_ctx.timer_id, + cfg->config.auto_reload); + timer_ll_set_clock_prescale(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.divider); + timer_ll_set_count_direction(data->hal_ctx.dev, data->hal_ctx.timer_id, + cfg->config.counter_dir); + timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.alarm_en); + timer_ll_set_reload_value(data->hal_ctx.dev, data->hal_ctx.timer_id, 0); + timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.counter_en); + esp_intr_alloc(cfg->irq_source, 0, (ISR_HANDLER)counter_esp32_isr, (void *)dev, NULL); k_spin_unlock(&lock, key); return 0; @@ -106,7 +103,7 @@ static int counter_esp32_start(const struct device *dev) struct counter_esp32_data *data = dev->data; k_spinlock_key_t key = k_spin_lock(&lock); - timer_hal_set_counter_enable(&data->hal_ctx, TIMER_START); + timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_START); k_spin_unlock(&lock, key); return 0; @@ -117,7 +114,7 @@ static int counter_esp32_stop(const struct device *dev) struct counter_esp32_data *data = dev->data; k_spinlock_key_t key = k_spin_lock(&lock); - timer_hal_set_counter_enable(&data->hal_ctx, TIMER_PAUSE); + timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_PAUSE); k_spin_unlock(&lock, key); return 0; @@ -128,7 +125,7 @@ static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks) struct counter_esp32_data *data = dev->data; k_spinlock_key_t key = k_spin_lock(&lock); - timer_hal_get_counter_value(&data->hal_ctx, (uint64_t *)ticks); + *ticks = timer_ll_get_counter_value(data->hal_ctx.dev, data->hal_ctx.timer_id); k_spin_unlock(&lock, key); return 0; @@ -146,13 +143,15 @@ static int counter_esp32_set_alarm(const struct device *dev, uint8_t chan_id, k_spinlock_key_t key = k_spin_lock(&lock); if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) { - timer_hal_set_alarm_value(&data->hal_ctx, (now + alarm_cfg->ticks)); + timer_ll_set_alarm_value(data->hal_ctx.dev, data->hal_ctx.timer_id, + (now + alarm_cfg->ticks)); } else { - timer_hal_set_alarm_value(&data->hal_ctx, alarm_cfg->ticks); + timer_ll_set_alarm_value(data->hal_ctx.dev, data->hal_ctx.timer_id, + alarm_cfg->ticks); } - timer_hal_intr_enable(&data->hal_ctx); - timer_hal_set_alarm_enable(&data->hal_ctx, TIMER_ALARM_EN); + timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id), true); + timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_ALARM_EN); data->alarm_cfg.callback = alarm_cfg->callback; data->alarm_cfg.user_data = alarm_cfg->user_data; k_spin_unlock(&lock, key); @@ -167,8 +166,9 @@ static int counter_esp32_cancel_alarm(const struct device *dev, uint8_t chan_id) k_spinlock_key_t key = k_spin_lock(&lock); - timer_hal_intr_disable(&data->hal_ctx); - timer_hal_set_alarm_enable(&data->hal_ctx, TIMER_ALARM_DIS); + timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id), + false); + timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_ALARM_DIS); k_spin_unlock(&lock, key); return 0; @@ -190,9 +190,7 @@ static uint32_t counter_esp32_get_pending_int(const struct device *dev) { struct counter_esp32_data *data = dev->data; - timer_hal_get_intr_status_reg(&data->hal_ctx); - - return 0; + return timer_ll_get_intr_status(data->hal_ctx.dev); } static uint32_t counter_esp32_get_top_value(const struct device *dev) @@ -226,7 +224,7 @@ static void counter_esp32_isr(void *arg) data->alarm_cfg.callback(dev, 0, now, data->alarm_cfg.user_data); } - timer_hal_clear_intr_status(&data->hal_ctx); + timer_ll_clear_intr_status(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id)); } #define ESP32_COUNTER_GET_CLK_DIV(idx) \ diff --git a/drivers/dac/dac_esp32.c b/drivers/dac/dac_esp32.c index 0fd6709446c..9dc16106eee 100644 --- a/drivers/dac/dac_esp32.c +++ b/drivers/dac/dac_esp32.c @@ -13,9 +13,7 @@ #include #include #include -#include -#include -#include "driver/dac_common.h" +#include "driver/dac.h" #include LOG_MODULE_REGISTER(esp32_dac, CONFIG_DAC_LOG_LEVEL); @@ -41,7 +39,7 @@ static int dac_esp32_channel_setup(const struct device *dev, { ARG_UNUSED(dev); - if (channel_cfg->channel_id > DAC_CHANNEL_MAX) { + if (channel_cfg->channel_id > SOC_DAC_CHAN_NUM) { LOG_ERR("Channel %d is not valid", channel_cfg->channel_id); return -EINVAL; } @@ -66,7 +64,7 @@ static int dac_esp32_init(const struct device *dev) } if (clock_control_on(cfg->clock_dev, - (clock_control_subsys_t) cfg->clock_subsys) != 0) { + (clock_control_subsys_t) &cfg->clock_subsys) != 0) { LOG_ERR("DAC clock setup failed (%d)", -EIO); return -EIO; } diff --git a/drivers/dma/dma_esp32_gdma.c b/drivers/dma/dma_esp32_gdma.c index 588b3fe9414..fcc1ca4b4b7 100644 --- a/drivers/dma/dma_esp32_gdma.c +++ b/drivers/dma/dma_esp32_gdma.c @@ -11,11 +11,11 @@ LOG_MODULE_REGISTER(dma_esp32_gdma, CONFIG_DMA_LOG_LEVEL); #include #include -#include +#include #include #include -#include +#include #include #include #include @@ -34,6 +34,8 @@ LOG_MODULE_REGISTER(dma_esp32_gdma, CONFIG_DMA_LOG_LEVEL); #endif #define DMA_MAX_CHANNEL SOC_GDMA_PAIRS_PER_GROUP +#define ESP_DMA_M2M_ON 0 +#define ESP_DMA_M2M_OFF 1 struct dma_esp32_data { gdma_hal_context_t hal; @@ -181,10 +183,12 @@ static int dma_esp32_config_rx(const struct device *dev, struct dma_esp32_channe gdma_ll_rx_reset_channel(data->hal.dev, dma_channel->channel_id); - if (dma_channel->periph_id != SOC_GDMA_TRIG_PERIPH_M2M0) { - gdma_ll_rx_connect_to_periph(data->hal.dev, dma_channel->channel_id, - dma_channel->periph_id); - } + gdma_ll_rx_connect_to_periph( + data->hal.dev, dma_channel->channel_id, + dma_channel->periph_id == SOC_GDMA_TRIG_PERIPH_M2M0 ? ESP_DMA_M2M_ON + : ESP_DMA_M2M_OFF, + dma_channel->periph_id == SOC_GDMA_TRIG_PERIPH_M2M0 ? ESP_DMA_M2M_ON + : dma_channel->periph_id); if (config_dma->dest_burst_length) { /* @@ -236,10 +240,12 @@ static int dma_esp32_config_tx(const struct device *dev, struct dma_esp32_channe gdma_ll_tx_reset_channel(data->hal.dev, dma_channel->channel_id); - if (dma_channel->periph_id != SOC_GDMA_TRIG_PERIPH_M2M0) { - gdma_ll_tx_connect_to_periph(data->hal.dev, dma_channel->channel_id, - dma_channel->periph_id); - } + gdma_ll_tx_connect_to_periph( + data->hal.dev, dma_channel->channel_id, + dma_channel->periph_id == SOC_GDMA_TRIG_PERIPH_M2M0 ? ESP_DMA_M2M_ON + : ESP_DMA_M2M_OFF, + dma_channel->periph_id == SOC_GDMA_TRIG_PERIPH_M2M0 ? ESP_DMA_M2M_ON + : dma_channel->periph_id); /* * TX channel can always enable burst mode, no matter data alignment @@ -288,9 +294,6 @@ static int dma_esp32_config(const struct device *dev, uint32_t channel, dma_channel->channel_id = channel / 2; - gdma_ll_enable_m2m_mode(data->hal.dev, dma_channel->channel_id, - config_dma->channel_direction == MEMORY_TO_MEMORY); - switch (config_dma->channel_direction) { case MEMORY_TO_MEMORY: /* @@ -538,7 +541,7 @@ static int dma_esp32_init(const struct device *dev) dma_channel = &config->dma_channel[i]; dma_channel->cb = NULL; dma_channel->dir = DMA_UNCONFIGURED; - dma_channel->periph_id = GDMA_TRIG_PERIPH_INVALID; + dma_channel->periph_id = ESP_GDMA_TRIG_PERIPH_INVALID; memset(&dma_channel->desc, 0, sizeof(dma_descriptor_t)); } diff --git a/drivers/entropy/entropy_esp32.c b/drivers/entropy/entropy_esp32.c index 4a15f640ce9..8be2891f959 100644 --- a/drivers/entropy/entropy_esp32.c +++ b/drivers/entropy/entropy_esp32.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include static inline uint32_t entropy_esp32_get_u32(void) @@ -33,7 +33,7 @@ static inline uint32_t entropy_esp32_get_u32(void) uint32_t ccount; do { - ccount = cpu_hal_get_cycle_count(); + ccount = esp_cpu_get_cycle_count(); } while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16); last_ccount = ccount; diff --git a/drivers/ethernet/eth_esp32.c b/drivers/ethernet/eth_esp32.c index 687b24c1e6d..689a6db7824 100644 --- a/drivers/ethernet/eth_esp32.c +++ b/drivers/ethernet/eth_esp32.c @@ -285,9 +285,12 @@ int eth_esp32_initialize(const struct device *dev) goto err; } + /* Set dma_burst_len as ETH_DMA_BURST_LEN_32 by default */ + emac_hal_dma_config_t dma_config = { .dma_burst_len = 0 }; + emac_hal_reset_desc_chain(&dev_data->hal); emac_hal_init_mac_default(&dev_data->hal); - emac_hal_init_dma_default(&dev_data->hal); + emac_hal_init_dma_default(&dev_data->hal, &dma_config); res = generate_mac_addr(dev_data->mac_addr); if (res != 0) { diff --git a/drivers/flash/flash_esp32.c b/drivers/flash/flash_esp32.c index 419daa342ff..3ce3777d829 100644 --- a/drivers/flash/flash_esp32.c +++ b/drivers/flash/flash_esp32.c @@ -14,13 +14,11 @@ * HAL includes go first to * avoid BIT macro redefinition */ -#include -#include -#include -#include +#include +#include #include -#include #include +#include #include #include @@ -30,30 +28,6 @@ #include #include -#if defined(CONFIG_SOC_SERIES_ESP32) -#include "soc/dport_reg.h" -#include "esp32/rom/cache.h" -#include "esp32/rom/spi_flash.h" -#include "esp32/spiram.h" -#elif defined(CONFIG_SOC_SERIES_ESP32S2) -#include "soc/spi_mem_reg.h" -#include "esp32s2/rom/cache.h" -#include "esp32s2/rom/spi_flash.h" -#elif defined(CONFIG_SOC_SERIES_ESP32S3) -#include "soc/spi_mem_reg.h" -#include "esp32s3/rom/cache.h" -#include "esp32s3/rom/spi_flash.h" -#elif defined(CONFIG_SOC_SERIES_ESP32C3) -#include "soc/spi_periph.h" -#include "soc/spi_mem_reg.h" -#include "soc/dport_access.h" -#include "esp32c3/dport_access.h" -#include "esp32c3/rom/cache.h" -#include "esp32c3/rom/spi_flash.h" -#endif - -#include "soc/mmu.h" - #include LOG_MODULE_REGISTER(flash_esp32, CONFIG_FLASH_LOG_LEVEL); @@ -101,9 +75,9 @@ static int flash_esp32_read(const struct device *dev, off_t address, void *buffe flash_esp32_sem_take(dev); if (!esp_flash_encryption_enabled()) { - ret = spi_flash_read(address, buffer, length); + ret = esp_flash_read(NULL, buffer, address, length); } else { - ret = spi_flash_read_encrypted(address, buffer, length); + ret = esp_flash_read_encrypted(NULL, address, buffer, length); } flash_esp32_sem_give(dev); return ret; @@ -118,9 +92,9 @@ static int flash_esp32_write(const struct device *dev, flash_esp32_sem_take(dev); if (!esp_flash_encryption_enabled()) { - ret = spi_flash_write(address, buffer, length); + ret = esp_flash_write(NULL, buffer, address, length); } else { - ret = spi_flash_write_encrypted(address, buffer, length); + ret = esp_flash_write_encrypted(NULL, address, buffer, length); } flash_esp32_sem_give(dev); return ret; @@ -129,7 +103,7 @@ static int flash_esp32_write(const struct device *dev, static int flash_esp32_erase(const struct device *dev, off_t start, size_t len) { flash_esp32_sem_take(dev); - int ret = spi_flash_erase_range(start, len); + int ret = esp_flash_erase_region(NULL, start, len); flash_esp32_sem_give(dev); return ret; } @@ -160,11 +134,16 @@ flash_esp32_get_parameters(const struct device *dev) static int flash_esp32_init(const struct device *dev) { struct flash_esp32_dev_data *const dev_data = dev->data; + uint32_t ret = 0; #ifdef CONFIG_MULTITHREADING k_sem_init(&dev_data->sem, 1, 1); #endif /* CONFIG_MULTITHREADING */ - + ret = esp_flash_init_default_chip(); + if (ret != 0) { + LOG_ERR("esp_flash_init_default_chip failed %d", ret); + return 0; + } return 0; } diff --git a/drivers/i2c/i2c_esp32.c b/drivers/i2c/i2c_esp32.c index 60af4648949..fdb78a2c6ed 100644 --- a/drivers/i2c/i2c_esp32.c +++ b/drivers/i2c/i2c_esp32.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -40,6 +41,8 @@ LOG_MODULE_REGISTER(i2c_esp32, CONFIG_I2C_LOG_LEVEL); #define I2C_CLK_LIMIT_RTC (20 * 1000 * 1000 / 20) /* Limited by RTC, no more than RTC/20 */ #define I2C_CLK_LIMIT_XTAL (40 * 1000 * 1000 / 20) /* Limited by RTC, no more than XTAL/20 */ +#define I2C_CLOCK_INVALID (-1) + enum i2c_status_t { I2C_STATUS_READ, /* read status for current master command */ I2C_STATUS_WRITE, /* write status for current master command */ @@ -93,31 +96,52 @@ struct i2c_esp32_config { const uint32_t scl_timeout; }; -/* I2C clock characteristic, The order is the same as i2c_sclk_t. */ -static uint32_t i2c_clk_alloc[I2C_SCLK_MAX] = { - 0, +static uint32_t i2c_get_src_clk_freq(i2c_clock_source_t clk_src) +{ + uint32_t periph_src_clk_hz = 0; + + switch (clk_src) { #if SOC_I2C_SUPPORT_APB - I2C_CLK_LIMIT_APB, /* I2C APB clock characteristic */ + case I2C_CLK_SRC_APB: + periph_src_clk_hz = esp_clk_apb_freq(); + break; #endif #if SOC_I2C_SUPPORT_XTAL - I2C_CLK_LIMIT_XTAL, /* I2C XTAL characteristic */ + case I2C_CLK_SRC_XTAL: + periph_src_clk_hz = esp_clk_xtal_freq(); + break; #endif #if SOC_I2C_SUPPORT_RTC - I2C_CLK_LIMIT_RTC, /* I2C 20M RTC characteristic */ + case I2C_CLK_SRC_RC_FAST: + periph_rtc_dig_clk8m_enable(); + periph_src_clk_hz = periph_rtc_dig_clk8m_get_freq(); + break; #endif #if SOC_I2C_SUPPORT_REF_TICK - I2C_CLK_LIMIT_REF_TICK, /* I2C REF_TICK characteristic */ + case RMT_CLK_SRC_REF_TICK: + periph_src_clk_hz = REF_CLK_FREQ; + break; #endif -}; + default: + LOG_ERR("clock source %d is not supported", clk_src); + break; + } + + return periph_src_clk_hz; +} -static i2c_sclk_t i2c_get_clk_src(uint32_t clk_freq) +static i2c_clock_source_t i2c_get_clk_src(uint32_t clk_freq) { - for (i2c_sclk_t clk = I2C_SCLK_DEFAULT + 1; clk < I2C_SCLK_MAX; clk++) { - if (clk_freq <= i2c_clk_alloc[clk]) { - return clk; + i2c_clock_source_t clk_srcs[] = SOC_I2C_CLKS; + + for (size_t i = 0; i < ARRAY_SIZE(clk_srcs); i++) { + /* I2C SCL clock frequency should not larger than clock source frequency/20 */ + if (clk_freq <= (i2c_get_src_clk_freq(clk_srcs[i]) / 20)) { + return clk_srcs[i]; } } - return I2C_SCLK_MAX; /* flag invalid */ + + return I2C_CLOCK_INVALID; } #ifndef SOC_I2C_SUPPORT_HW_CLR_BUS @@ -181,9 +205,9 @@ static void IRAM_ATTR i2c_master_clear_bus(const struct device *dev) gpio_pin_set_dt(&config->sda.gpio, 1); /* STOP, SDA low -> high while SCL is HIGH */ i2c_esp32_config_pin(dev); #else - i2c_hal_master_clr_bus(&data->hal); + i2c_ll_master_clr_bus(data->hal.dev); #endif - i2c_hal_update_config(&data->hal); + i2c_ll_update(data->hal.dev); } static void IRAM_ATTR i2c_hw_fsm_reset(const struct device *dev) @@ -199,32 +223,32 @@ static void IRAM_ATTR i2c_hw_fsm_reset(const struct device *dev) int timeout; uint8_t filter_cfg; - i2c_hal_get_scl_timing(&data->hal, &scl_high_period, &scl_low_period); - i2c_hal_get_start_timing(&data->hal, &scl_rstart_setup, &scl_start_hold); - i2c_hal_get_stop_timing(&data->hal, &scl_stop_setup, &scl_stop_hold); - i2c_hal_get_sda_timing(&data->hal, &sda_sample, &sda_hold); - i2c_hal_get_tout(&data->hal, &timeout); - i2c_hal_get_filter(&data->hal, &filter_cfg); + i2c_ll_get_scl_timing(data->hal.dev, &scl_high_period, &scl_low_period); + i2c_ll_get_start_timing(data->hal.dev, &scl_rstart_setup, &scl_start_hold); + i2c_ll_get_stop_timing(data->hal.dev, &scl_stop_setup, &scl_stop_hold); + i2c_ll_get_sda_timing(data->hal.dev, &sda_sample, &sda_hold); + i2c_ll_get_tout(data->hal.dev, &timeout); + i2c_ll_get_filter(data->hal.dev, &filter_cfg); /* to reset the I2C hw module, we need re-enable the hw */ clock_control_off(config->clock_dev, config->clock_subsys); i2c_master_clear_bus(dev); clock_control_on(config->clock_dev, config->clock_subsys); - i2c_hal_master_init(&data->hal, config->index); - i2c_hal_disable_intr_mask(&data->hal, I2C_LL_INTR_MASK); - i2c_hal_clr_intsts_mask(&data->hal, I2C_LL_INTR_MASK); - i2c_hal_set_scl_timing(&data->hal, scl_high_period, scl_low_period); - i2c_hal_set_start_timing(&data->hal, scl_rstart_setup, scl_start_hold); - i2c_hal_set_stop_timing(&data->hal, scl_stop_setup, scl_stop_hold); - i2c_hal_set_sda_timing(&data->hal, sda_sample, sda_hold); - i2c_hal_set_tout(&data->hal, timeout); - i2c_hal_set_filter(&data->hal, filter_cfg); + i2c_hal_master_init(&data->hal); + i2c_ll_disable_intr_mask(data->hal.dev, I2C_LL_INTR_MASK); + i2c_ll_clear_intr_mask(data->hal.dev, I2C_LL_INTR_MASK); + i2c_ll_set_scl_timing(data->hal.dev, scl_high_period, scl_low_period); + i2c_ll_set_start_timing(data->hal.dev, scl_rstart_setup, scl_start_hold); + i2c_ll_set_stop_timing(data->hal.dev, scl_stop_setup, scl_stop_hold); + i2c_ll_set_sda_timing(data->hal.dev, sda_sample, sda_hold); + i2c_ll_set_tout(data->hal.dev, timeout); + i2c_ll_set_filter(data->hal.dev, filter_cfg); #else - i2c_hal_master_fsm_rst(&data->hal); + i2c_ll_master_fsm_rst(data->hal.dev); i2c_master_clear_bus(dev); #endif - i2c_hal_update_config(&data->hal); + i2c_ll_update(data->hal.dev); } static int i2c_esp32_recover(const struct device *dev) @@ -244,22 +268,18 @@ static void IRAM_ATTR i2c_esp32_configure_timeout(const struct device *dev) struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data; if (config->scl_timeout > 0) { - i2c_sclk_t sclk = i2c_get_clk_src(config->bitrate); - uint32_t clk_freq_mhz = i2c_clk_alloc[sclk]; + i2c_clock_source_t sclk = i2c_get_clk_src(config->bitrate); + uint32_t clk_freq_mhz = i2c_get_src_clk_freq(sclk); uint32_t timeout_cycles = MIN(I2C_LL_MAX_TIMEOUT, clk_freq_mhz / MHZ(1) * config->scl_timeout); - i2c_hal_set_tout(&data->hal, timeout_cycles); + i2c_ll_set_tout(data->hal.dev, timeout_cycles); LOG_DBG("SCL timeout: %d us, value: %d", config->scl_timeout, timeout_cycles); } else { /* Disabling the timeout by clearing the I2C_TIME_OUT_EN bit does not seem to work, * at least for ESP32-C3 (tested with communication to bq76952 chip). So we set the * timeout to maximum supported value instead. */ -#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32) - i2c_hal_set_tout(&data->hal, I2C_LL_MAX_TIMEOUT); -#else - i2c_hal_set_tout_en(&data->hal, 0); -#endif + i2c_ll_set_tout(data->hal.dev, I2C_LL_MAX_TIMEOUT); } } @@ -286,19 +306,21 @@ static int i2c_esp32_configure(const struct device *dev, uint32_t dev_config) rx_mode = I2C_DATA_MODE_LSB_FIRST; } - i2c_hal_master_init(&data->hal, config->index); - i2c_hal_set_data_mode(&data->hal, tx_mode, rx_mode); - i2c_hal_set_filter(&data->hal, I2C_FILTER_CYC_NUM_DEF); - i2c_hal_update_config(&data->hal); + i2c_hal_master_init(&data->hal); + i2c_ll_set_data_mode(data->hal.dev, tx_mode, rx_mode); + i2c_ll_set_filter(data->hal.dev, I2C_FILTER_CYC_NUM_DEF); + i2c_ll_update(data->hal.dev); if (config->bitrate == 0) { LOG_ERR("Error configuring I2C speed."); return -ENOTSUP; } - i2c_hal_set_bus_timing(&data->hal, config->bitrate, i2c_get_clk_src(config->bitrate)); + i2c_clock_source_t sclk = i2c_get_clk_src(config->bitrate); + + i2c_hal_set_bus_timing(&data->hal, config->bitrate, sclk, i2c_get_src_clk_freq(sclk)); i2c_esp32_configure_timeout(dev); - i2c_hal_update_config(&data->hal); + i2c_ll_update(data->hal.dev); return 0; } @@ -308,8 +330,8 @@ static void IRAM_ATTR i2c_esp32_reset_fifo(const struct device *dev) struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data; /* reset fifo buffers */ - i2c_hal_txfifo_rst(&data->hal); - i2c_hal_rxfifo_rst(&data->hal); + i2c_ll_txfifo_rst(data->hal.dev); + i2c_ll_rxfifo_rst(data->hal.dev); } static int IRAM_ATTR i2c_esp32_transmit(const struct device *dev) @@ -318,8 +340,8 @@ static int IRAM_ATTR i2c_esp32_transmit(const struct device *dev) int ret = 0; /* Start transmission*/ - i2c_hal_update_config(&data->hal); - i2c_hal_trans_start(&data->hal); + i2c_ll_update(data->hal.dev); + i2c_ll_trans_start(data->hal.dev); data->cmd_idx = 0; ret = k_sem_take(&data->cmd_sem, K_MSEC(I2C_TRANSFER_TIMEOUT_MSEC)); @@ -345,22 +367,22 @@ static void IRAM_ATTR i2c_esp32_master_start(const struct device *dev) { struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data; - i2c_hw_cmd_t cmd = { + i2c_ll_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_RESTART }; - i2c_hal_write_cmd_reg(&data->hal, cmd, data->cmd_idx++); + i2c_ll_write_cmd_reg(data->hal.dev, cmd, data->cmd_idx++); } static void IRAM_ATTR i2c_esp32_master_stop(const struct device *dev) { struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data; - i2c_hw_cmd_t cmd = { + i2c_ll_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_STOP }; - i2c_hal_write_cmd_reg(&data->hal, cmd, data->cmd_idx++); + i2c_ll_write_cmd_reg(data->hal.dev, cmd, data->cmd_idx++); } static int IRAM_ATTR i2c_esp32_write_addr(const struct device *dev, uint16_t addr) @@ -372,26 +394,26 @@ static int IRAM_ATTR i2c_esp32_write_addr(const struct device *dev, uint16_t add data->status = I2C_STATUS_WRITE; /* write address value in tx buffer */ - i2c_hal_write_txfifo(&data->hal, &addr_byte, 1); + i2c_ll_write_txfifo(data->hal.dev, &addr_byte, 1); if (data->dev_config & I2C_ADDR_10_BITS) { addr_byte = (addr >> 8) & 0xFF; - i2c_hal_write_txfifo(&data->hal, &addr_byte, 1); + i2c_ll_write_txfifo(data->hal.dev, &addr_byte, 1); addr_len++; } - const i2c_hw_cmd_t cmd_end = { + const i2c_ll_hw_cmd_t cmd_end = { .op_code = I2C_LL_CMD_END, }; - i2c_hw_cmd_t cmd = { + i2c_ll_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_WRITE, .ack_en = true, .byte_num = addr_len, }; - i2c_hal_write_cmd_reg(&data->hal, cmd, data->cmd_idx++); - i2c_hal_write_cmd_reg(&data->hal, cmd_end, data->cmd_idx++); - i2c_hal_enable_master_tx_it(&data->hal); + i2c_ll_write_cmd_reg(data->hal.dev, cmd, data->cmd_idx++); + i2c_ll_write_cmd_reg(data->hal.dev, cmd_end, data->cmd_idx++); + i2c_ll_master_enable_tx_it(data->hal.dev); return i2c_esp32_transmit(dev); } @@ -407,10 +429,10 @@ static int IRAM_ATTR i2c_esp32_master_read(const struct device *dev, struct i2c_ data->status = I2C_STATUS_READ; - i2c_hw_cmd_t cmd = { + i2c_ll_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_READ, }; - const i2c_hw_cmd_t cmd_end = { + const i2c_ll_hw_cmd_t cmd_end = { .op_code = I2C_LL_CMD_END, }; @@ -429,15 +451,15 @@ static int IRAM_ATTR i2c_esp32_master_read(const struct device *dev, struct i2c_ } cmd.byte_num = rd_filled; - i2c_hal_write_cmd_reg(&data->hal, cmd, data->cmd_idx++); - i2c_hal_write_cmd_reg(&data->hal, cmd_end, data->cmd_idx++); - i2c_hal_enable_master_rx_it(&data->hal); + i2c_ll_write_cmd_reg(data->hal.dev, cmd, data->cmd_idx++); + i2c_ll_write_cmd_reg(data->hal.dev, cmd_end, data->cmd_idx++); + i2c_ll_master_enable_tx_it(data->hal.dev); ret = i2c_esp32_transmit(dev); if (ret < 0) { return ret; } - i2c_hal_read_rxfifo(&data->hal, msg_buf, rd_filled); + i2c_ll_read_rxfifo(data->hal.dev, msg_buf, rd_filled); msg_buf += rd_filled; msg_len -= rd_filled; } @@ -491,12 +513,12 @@ static int IRAM_ATTR i2c_esp32_master_write(const struct device *dev, struct i2c data->status = I2C_STATUS_WRITE; - i2c_hw_cmd_t cmd = { + i2c_ll_hw_cmd_t cmd = { .op_code = I2C_LL_CMD_WRITE, .ack_en = true, }; - const i2c_hw_cmd_t cmd_end = { + const i2c_ll_hw_cmd_t cmd_end = { .op_code = I2C_LL_CMD_END, }; @@ -505,10 +527,10 @@ static int IRAM_ATTR i2c_esp32_master_write(const struct device *dev, struct i2c cmd.byte_num = wr_filled; if (wr_filled > 0) { - i2c_hal_write_txfifo(&data->hal, msg_buf, wr_filled); - i2c_hal_write_cmd_reg(&data->hal, cmd, data->cmd_idx++); - i2c_hal_write_cmd_reg(&data->hal, cmd_end, data->cmd_idx++); - i2c_hal_enable_master_tx_it(&data->hal); + i2c_ll_write_txfifo(data->hal.dev, msg_buf, wr_filled); + i2c_ll_write_cmd_reg(data->hal.dev, cmd, data->cmd_idx++); + i2c_ll_write_cmd_reg(data->hal.dev, cmd_end, data->cmd_idx++); + i2c_ll_master_enable_tx_it(data->hal.dev); ret = i2c_esp32_transmit(dev); if (ret < 0) { return ret; @@ -567,7 +589,7 @@ static int IRAM_ATTR i2c_esp32_transfer(const struct device *dev, struct i2c_msg return 0; } - while (i2c_hal_is_bus_busy(&data->hal)) { + while (i2c_ll_is_bus_busy(data->hal.dev)) { k_busy_wait(1); if (timeout-- == 0) { return -EBUSY; @@ -617,7 +639,7 @@ static int IRAM_ATTR i2c_esp32_transfer(const struct device *dev, struct i2c_msg for (; num_msgs > 0; num_msgs--, msgs++) { - if (data->status == I2C_STATUS_TIMEOUT || i2c_hal_is_bus_busy(&data->hal)) { + if (data->status == I2C_STATUS_TIMEOUT || i2c_ll_is_bus_busy(data->hal.dev)) { i2c_hw_fsm_reset(dev); } @@ -626,8 +648,8 @@ static int IRAM_ATTR i2c_esp32_transfer(const struct device *dev, struct i2c_msg /* These two interrupts some times can not be cleared when the FSM gets stuck. */ /* So we disable them when these two interrupt occurs and re-enable them here. */ - i2c_hal_disable_intr_mask(&data->hal, I2C_LL_INTR_MASK); - i2c_hal_clr_intsts_mask(&data->hal, I2C_LL_INTR_MASK); + i2c_ll_disable_intr_mask(data->hal.dev, I2C_LL_INTR_MASK); + i2c_ll_clear_intr_mask(data->hal.dev, I2C_LL_INTR_MASK); if ((msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) { ret = i2c_esp32_read_msg(dev, msgs, addr); diff --git a/drivers/interrupt_controller/intc_esp32.c b/drivers/interrupt_controller/intc_esp32.c index 6e2c6f06640..23073d80edc 100644 --- a/drivers/interrupt_controller/intc_esp32.c +++ b/drivers/interrupt_controller/intc_esp32.c @@ -12,12 +12,14 @@ #include #include #include -#include "esp_attr.h" -#include -#include +#include +#include +#include +#include #include #include -#include "soc/soc.h" +#include + #include LOG_MODULE_REGISTER(esp32_intc, CONFIG_LOG_DEFAULT_LEVEL); @@ -73,9 +75,9 @@ struct intr_alloc_table_entry { }; /* Default handler for unhandled interrupts. */ -void default_intr_handler(void *arg) +void IRAM_ATTR default_intr_handler(void *arg) { - printk("Unhandled interrupt %d on cpu %d!\n", (int)arg, esp_core_id()); + esp_rom_printf("Unhandled interrupt %d on cpu %d!\n", (int)arg, esp_cpu_get_core_id()); } static struct intr_alloc_table_entry intr_alloc_table[ESP_INTC_INTS_NUM * CONFIG_MP_MAX_NUM_CPUS]; @@ -84,8 +86,7 @@ static void set_interrupt_handler(int n, intc_handler_t f, void *arg) { irq_disable(n); intr_alloc_table[n * CONFIG_MP_MAX_NUM_CPUS].handler = f; - irq_connect_dynamic(n, n, (intc_dyn_handler_t)f, arg, 0); - irq_enable(n); + irq_connect_dynamic(n, 0, (intc_dyn_handler_t)f, arg, 0); } /* Linked list of vector descriptions, sorted by cpu.intno value */ @@ -271,28 +272,33 @@ static bool is_vect_desc_usable(struct vector_desc_t *vd, int flags, int cpu, in { /* Check if interrupt is not reserved by design */ int x = vd->intno; + esp_cpu_intr_desc_t intr_desc; + + esp_cpu_intr_get_desc(cpu, x, &intr_desc); - if (interrupt_controller_hal_get_cpu_desc_flags(x, cpu) == INTDESC_RESVD) { + if (intr_desc.flags & ESP_CPU_INTR_DESC_FLAG_RESVD) { INTC_LOG("....Unusable: reserved"); return false; } - if (interrupt_controller_hal_get_cpu_desc_flags(x, cpu) == INTDESC_SPECIAL && force == -1) { + if (intr_desc.flags & ESP_CPU_INTR_DESC_FLAG_SPECIAL && force == -1) { INTC_LOG("....Unusable: special-purpose int"); return false; } - /* Check if the interrupt level is acceptable */ - if (!(flags & (1 << interrupt_controller_hal_get_level(x)))) { - INTC_LOG("....Unusable: incompatible level"); + +#ifndef SOC_CPU_HAS_FLEXIBLE_INTC + /* Check if the interrupt priority is acceptable */ + if (!(flags & (1 << intr_desc.priority))) { + INTC_LOG("....Unusable: incompatible priority"); return false; } /* check if edge/level type matches what we want */ - if (((flags & ESP_INTR_FLAG_EDGE) && - (interrupt_controller_hal_get_type(x) == INTTP_LEVEL)) || - (((!(flags & ESP_INTR_FLAG_EDGE)) && - (interrupt_controller_hal_get_type(x) == INTTP_EDGE)))) { + if (((flags & ESP_INTR_FLAG_EDGE) && (intr_desc.type == ESP_CPU_INTR_TYPE_LEVEL)) || + (((!(flags & ESP_INTR_FLAG_EDGE)) && (intr_desc.type == ESP_CPU_INTR_TYPE_EDGE)))) { INTC_LOG("....Unusable: incompatible trigger type"); return false; } +#endif + /* check if interrupt is reserved at runtime */ if (vd->flags & VECDESC_FL_RESERVED) { INTC_LOG("....Unusable: reserved at runtime."); @@ -353,7 +359,6 @@ static int get_available_int(int flags, int cpu, int force, int source) memset(&empty_vect_desc, 0, sizeof(struct vector_desc_t)); - /* Level defaults to any low/med interrupt */ if (!(flags & ESP_INTR_FLAG_LEVELMASK)) { flags |= ESP_INTR_FLAG_LOWMED; @@ -403,11 +408,14 @@ static int get_available_int(int flags, int cpu, int force, int source) vd = &empty_vect_desc; } + esp_cpu_intr_desc_t intr_desc; + + esp_cpu_intr_get_desc(cpu, x, &intr_desc); + INTC_LOG("Int %d reserved %d level %d %s hasIsr %d", - x, - interrupt_controller_hal_get_cpu_desc_flags(x, cpu) == INTDESC_RESVD, - interrupt_controller_hal_get_level(x), - interrupt_controller_hal_get_type(x) == INTTP_LEVEL ? "LEVEL" : "EDGE", + x, intr_desc.flags & ESP_CPU_INTR_DESC_FLAG_RESVD, + intr_desc.priority, + intr_desc.type == ESP_CPU_INTR_TYPE_LEVEL ? "LEVEL" : "EDGE", intr_has_handler(x, cpu)); if (!is_vect_desc_usable(vd, flags, cpu, force)) { @@ -430,15 +438,14 @@ static int get_available_int(int flags, int cpu, int force, int source) no++; svdesc = svdesc->next; } - if (no < best_shared_ct || - best_level > interrupt_controller_hal_get_level(x)) { + if (no < best_shared_ct || best_level > intr_desc.priority) { /* * Seems like this shared vector is both okay and has * the least amount of ISRs already attached to it. */ best = x; best_shared_ct = no; - best_level = interrupt_controller_hal_get_level(x); + best_level = intr_desc.priority; INTC_LOG("...int %d more usable as a shared int: " "has %d existing vectors", x, no); } else { @@ -453,9 +460,9 @@ static int get_available_int(int flags, int cpu, int force, int source) * Remember it in case we don't find any other shared * interrupt that qualifies. */ - if (best_level > interrupt_controller_hal_get_level(x)) { + if (best_level > intr_desc.priority) { best = x; - best_level = interrupt_controller_hal_get_level(x); + best_level = intr_desc.priority; INTC_LOG("...int %d usable as new shared int", x); } } else { @@ -467,9 +474,9 @@ static int get_available_int(int flags, int cpu, int force, int source) * Seems this interrupt is feasible. Select it and break out of the loop * No need to search further. */ - if (best_level > interrupt_controller_hal_get_level(x)) { + if (best_level > intr_desc.priority) { best = x; - best_level = interrupt_controller_hal_get_level(x); + best_level = intr_desc.priority; } else { INTC_LOG("...worse than int %d", best); } @@ -493,7 +500,8 @@ static void IRAM_ATTR shared_intr_isr(void *arg) esp_intr_lock(); while (sh_vec) { if (!sh_vec->disabled) { - if (!(sh_vec->statusreg) || (*sh_vec->statusreg & sh_vec->statusmask)) { + if ((sh_vec->statusreg == NULL) || + (*sh_vec->statusreg & sh_vec->statusmask)) { sh_vec->isr(sh_vec->arg); } } @@ -513,7 +521,7 @@ int esp_intr_alloc_intrstatus(int source, struct intr_handle_data_t *ret = NULL; int force = -1; - INTC_LOG("%s (cpu %d): checking args", __func__, esp_core_id()); + INTC_LOG("%s (cpu %d): checking args", __func__, esp_cpu_get_core_id()); /* Shared interrupts should be level-triggered. */ if ((flags & ESP_INTR_FLAG_SHARED) && (flags & ESP_INTR_FLAG_EDGE)) { return -EINVAL; @@ -536,9 +544,8 @@ int esp_intr_alloc_intrstatus(int source, * we need to make sure the interrupt is connected to the CPU0. * CPU1 does not have access to the RTC fast memory through this region. */ - if ((flags & ESP_INTR_FLAG_IRAM) && - (ptrdiff_t) handler >= SOC_RTC_IRAM_HIGH && - (ptrdiff_t) handler < SOC_RTC_DATA_LOW) { + if ((flags & ESP_INTR_FLAG_IRAM) && handler && !esp_ptr_in_iram(handler) && + !esp_ptr_in_rtc_iram_fast(handler)) { return -EINVAL; } @@ -554,7 +561,7 @@ int esp_intr_alloc_intrstatus(int source, } } INTC_LOG("%s (cpu %d): Args okay." - "Resulting flags 0x%X", __func__, esp_core_id(), flags); + "Resulting flags 0x%X", __func__, esp_cpu_get_core_id(), flags); /* * Check 'special' interrupt sources. These are tied to one specific @@ -590,7 +597,7 @@ int esp_intr_alloc_intrstatus(int source, } esp_intr_lock(); - int cpu = esp_core_id(); + int cpu = esp_cpu_get_core_id(); /* See if we can find an interrupt that matches the flags. */ int intr = get_available_int(flags, cpu, force, source); @@ -650,7 +657,7 @@ int esp_intr_alloc_intrstatus(int source, non_iram_int_mask[cpu] |= (1 << intr); } if (source >= 0) { - intr_matrix_set(cpu, source, intr); + esp_rom_route_intr_matrix(cpu, source, intr); } /* Fill return handle data. */ @@ -668,6 +675,19 @@ int esp_intr_alloc_intrstatus(int source, esp_intr_disable(ret); } +#ifdef SOC_CPU_HAS_FLEXIBLE_INTC + /* Extract the level from the interrupt passed flags */ + int level = esp_intr_flags_to_level(flags); + + esp_cpu_intr_set_priority(intr, level); + + if (flags & ESP_INTR_FLAG_EDGE) { + esp_cpu_intr_set_type(intr, ESP_CPU_INTR_TYPE_EDGE); + } else { + esp_cpu_intr_set_type(intr, ESP_CPU_INTR_TYPE_LEVEL); + } +#endif + esp_intr_unlock(); /* Fill return handle if needed, otherwise free handle. */ @@ -769,7 +789,9 @@ int esp_intr_free(struct intr_handle_data_t *handle) * few bytes of memory we save.(We can also not use the same exit path for empty * shared ints anymore if we delete the desc.) For now, just mark it as free. */ - handle->vector_desc->flags &= !(VECDESC_FL_NONSHARED | VECDESC_FL_RESERVED); + handle->vector_desc->flags &= ~(VECDESC_FL_NONSHARED | + VECDESC_FL_RESERVED | VECDESC_FL_SHARED); + /* Also kill non_iram mask bit. */ non_iram_int_mask[handle->vector_desc->cpu] &= ~(1 << (handle->vector_desc->intno)); } @@ -818,10 +840,12 @@ int IRAM_ATTR esp_intr_enable(struct intr_handle_data_t *handle) } if (source >= 0) { /* Disabled using int matrix; re-connect to enable */ - intr_matrix_set(handle->vector_desc->cpu, source, handle->vector_desc->intno); + esp_rom_route_intr_matrix(handle->vector_desc->cpu, + source, handle->vector_desc->intno); } else { /* Re-enable using cpu int ena reg */ - if (handle->vector_desc->cpu != esp_core_id()) { + if (handle->vector_desc->cpu != esp_cpu_get_core_id()) { + esp_intr_unlock(); return -EINVAL; /* Can only enable these ints on this cpu */ } irq_enable(handle->vector_desc->intno); @@ -860,11 +884,12 @@ int IRAM_ATTR esp_intr_disable(struct intr_handle_data_t *handle) if (source >= 0) { if (disabled) { /* Disable using int matrix */ - intr_matrix_set(handle->vector_desc->cpu, source, INT_MUX_DISABLED_INTNO); + esp_rom_route_intr_matrix(handle->vector_desc->cpu, + source, INT_MUX_DISABLED_INTNO); } } else { /* Disable using per-cpu regs */ - if (handle->vector_desc->cpu != esp_core_id()) { + if (handle->vector_desc->cpu != esp_cpu_get_core_id()) { esp_intr_unlock(); return -EINVAL; /* Can only enable these ints on this cpu */ } @@ -877,28 +902,33 @@ int IRAM_ATTR esp_intr_disable(struct intr_handle_data_t *handle) void IRAM_ATTR esp_intr_noniram_disable(void) { + esp_intr_lock(); int oldint; - int cpu = esp_core_id(); + int cpu = esp_cpu_get_core_id(); int non_iram_ints = ~non_iram_int_mask[cpu]; if (non_iram_int_disabled_flag[cpu]) { abort(); } non_iram_int_disabled_flag[cpu] = true; - oldint = interrupt_controller_hal_read_interrupt_mask(); - interrupt_controller_hal_disable_interrupts(non_iram_ints); - /* Save which ints we did disable */ + oldint = esp_cpu_intr_get_enabled_mask(); + esp_cpu_intr_disable(non_iram_ints); + rtc_isr_noniram_disable(cpu); non_iram_int_disabled[cpu] = oldint & non_iram_ints; + esp_intr_unlock(); } void IRAM_ATTR esp_intr_noniram_enable(void) { - int cpu = esp_core_id(); + esp_intr_lock(); + int cpu = esp_cpu_get_core_id(); int non_iram_ints = non_iram_int_disabled[cpu]; if (!non_iram_int_disabled_flag[cpu]) { abort(); } non_iram_int_disabled_flag[cpu] = false; - interrupt_controller_hal_enable_interrupts(non_iram_ints); + esp_cpu_intr_enable(non_iram_ints); + rtc_isr_noniram_enable(cpu); + esp_intr_unlock(); } diff --git a/drivers/pwm/pwm_led_esp32.c b/drivers/pwm/pwm_led_esp32.c index 7e53877f69e..1754d5dc36d 100644 --- a/drivers/pwm/pwm_led_esp32.c +++ b/drivers/pwm/pwm_led_esp32.c @@ -127,7 +127,7 @@ static int pwm_led_esp32_calculate_max_resolution(struct pwm_ledc_esp32_channel_ uint64_t clock_freq = channel->clock_src == LEDC_APB_CLK ? APB_CLK_FREQ : REF_CLK_FREQ; uint32_t max_precision_n = clock_freq/channel->freq; - for (uint8_t i = 0; i <= SOC_LEDC_TIMER_BIT_WIDE_NUM; i++) { + for (uint8_t i = 0; i <= SOC_LEDC_TIMER_BIT_WIDTH; i++) { max_precision_n /= 2; if (!max_precision_n) { channel->resolution = i; @@ -164,10 +164,12 @@ static int pwm_led_esp32_timer_config(struct pwm_ledc_esp32_channel_config *chan return 0; } +#if SOC_LEDC_SUPPORT_REF_TICK channel->clock_src = LEDC_REF_TICK; if (!pwm_led_esp32_calculate_max_resolution(channel)) { return 0; } +#endif /** * ESP32 - S2,S3 and C3 variants have only 14 bits counter. @@ -178,7 +180,7 @@ static int pwm_led_esp32_timer_config(struct pwm_ledc_esp32_channel_config *chan * so select the slow clock source (1MHz) with highest counter resolution. * this can be handled on the func 'pwm_led_esp32_timer_set' with 'prescaler'. */ - channel->resolution = SOC_LEDC_TIMER_BIT_WIDE_NUM; + channel->resolution = SOC_LEDC_TIMER_BIT_WIDTH; return 0; } @@ -199,9 +201,11 @@ static int pwm_led_esp32_timer_set(const struct device *dev, */ prescaler = ((uint64_t) APB_CLK_FREQ << 8) / channel->freq / precision; break; +#if SOC_LEDC_SUPPORT_REF_TICK case LEDC_REF_TICK: prescaler = ((uint64_t) REF_CLK_FREQ << 8) / channel->freq / precision; break; +#endif default: LOG_ERR("Invalid clock source (%d)", channel->clock_src); return -EINVAL; @@ -213,7 +217,7 @@ static int pwm_led_esp32_timer_set(const struct device *dev, } if (channel->speed_mode == LEDC_LOW_SPEED_MODE) { - ledc_hal_set_slow_clk(&data->hal, channel->clock_src); + ledc_hal_set_slow_clk_sel(&data->hal, channel->clock_src); } ledc_hal_set_clock_divider(&data->hal, channel->timer_num, prescaler); diff --git a/drivers/pwm/pwm_mc_esp32.c b/drivers/pwm/pwm_mc_esp32.c index 87003b86a9b..1297bb6da90 100644 --- a/drivers/pwm/pwm_mc_esp32.c +++ b/drivers/pwm/pwm_mc_esp32.c @@ -8,7 +8,7 @@ #include #include -#include "driver/mcpwm.h" +#include #include #include @@ -23,6 +23,7 @@ #include LOG_MODULE_REGISTER(mcpwm_esp32, CONFIG_PWM_LOG_LEVEL); +#define SOC_MCPWM_BASE_CLK_HZ (160000000U) #ifdef CONFIG_PWM_CAPTURE #define SKIP_IRQ_NUM 4U #define MCPWM_INTR_CAP0 BIT(0) @@ -109,7 +110,7 @@ static void mcpwm_esp32_duty_set(const struct device *dev, set_duty = mcpwm_ll_timer_get_peak(data->hal.dev, channel->timer_id, false) * channel->duty / 100; - mcpwm_ll_operator_select_timer(data->hal.dev, channel->operator_id, channel->timer_id); + mcpwm_ll_operator_connect_timer(data->hal.dev, channel->operator_id, channel->timer_id); mcpwm_ll_operator_set_compare_value(data->hal.dev, channel->operator_id, channel->generator_id, set_duty); mcpwm_ll_operator_enable_update_compare_on_tez(data->hal.dev, channel->operator_id, @@ -118,40 +119,40 @@ static void mcpwm_esp32_duty_set(const struct device *dev, if (duty_type == MCPWM_DUTY_MODE_0) { mcpwm_ll_generator_set_action_on_timer_event( data->hal.dev, channel->operator_id, channel->generator_id, - MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_GEN_ACTION_HIGH); + MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH); mcpwm_ll_generator_set_action_on_timer_event( data->hal.dev, channel->operator_id, channel->generator_id, - MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_PEAK, MCPWM_GEN_ACTION_KEEP); + MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_KEEP); mcpwm_ll_generator_set_action_on_compare_event( data->hal.dev, channel->operator_id, channel->generator_id, MCPWM_TIMER_DIRECTION_UP, channel->generator_id, MCPWM_ACTION_FORCE_LOW); } else if (duty_type == MCPWM_DUTY_MODE_1) { mcpwm_ll_generator_set_action_on_timer_event( data->hal.dev, channel->operator_id, channel->generator_id, - MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_GEN_ACTION_LOW); + MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW); mcpwm_ll_generator_set_action_on_timer_event( data->hal.dev, channel->operator_id, channel->generator_id, - MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_NO_CHANGE); + MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_NO_CHANGE); mcpwm_ll_generator_set_action_on_compare_event( data->hal.dev, channel->operator_id, channel->generator_id, MCPWM_TIMER_DIRECTION_UP, channel->generator_id, MCPWM_ACTION_FORCE_HIGH); } else if (duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_LOW) { mcpwm_ll_generator_set_action_on_timer_event( data->hal.dev, channel->operator_id, channel->generator_id, - MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_LOW); + MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_LOW); mcpwm_ll_generator_set_action_on_timer_event( data->hal.dev, channel->operator_id, channel->generator_id, - MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_LOW); + MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_LOW); mcpwm_ll_generator_set_action_on_compare_event( data->hal.dev, channel->operator_id, channel->generator_id, MCPWM_TIMER_DIRECTION_UP, channel->generator_id, MCPWM_ACTION_FORCE_LOW); } else if (duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH) { mcpwm_ll_generator_set_action_on_timer_event( data->hal.dev, channel->operator_id, channel->generator_id, - MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_ZERO, MCPWM_ACTION_FORCE_HIGH); + MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_ACTION_FORCE_HIGH); mcpwm_ll_generator_set_action_on_timer_event( data->hal.dev, channel->operator_id, channel->generator_id, - MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_PEAK, MCPWM_ACTION_FORCE_HIGH); + MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_ACTION_FORCE_HIGH); mcpwm_ll_generator_set_action_on_compare_event( data->hal.dev, channel->operator_id, channel->generator_id, MCPWM_TIMER_DIRECTION_UP, channel->generator_id, MCPWM_ACTION_FORCE_HIGH); @@ -259,8 +260,8 @@ static int mcpwm_esp32_set_cycles(const struct device *dev, uint32_t channel_idx return ret; } - mcpwm_ll_timer_set_execute_command(data->hal.dev, channel->timer_id, - MCPWM_TIMER_START_NO_STOP); + mcpwm_ll_timer_set_start_stop_command(data->hal.dev, channel->timer_id, + MCPWM_TIMER_START_NO_STOP); k_sem_give(&data->cmd_sem); @@ -326,7 +327,7 @@ static int mcpwm_esp32_disable_capture(const struct device *dev, uint32_t channe } mcpwm_ll_capture_enable_channel(data->hal.dev, capture->capture_signal, false); - mcpwm_ll_intr_enable_capture(data->hal.dev, capture->capture_signal, false); + mcpwm_ll_intr_enable(data->hal.dev, MCPWM_LL_EVENT_CAPTURE(capture->capture_signal), false); return 0; } @@ -381,7 +382,7 @@ static int mcpwm_esp32_enable_capture(const struct device *dev, uint32_t channel mcpwm_ll_capture_set_prescale(data->hal.dev, capture->capture_signal, cap_conf.cap_prescale); - mcpwm_ll_intr_enable_capture(data->hal.dev, capture->capture_signal, true); + mcpwm_ll_intr_enable(data->hal.dev, MCPWM_LL_EVENT_CAPTURE(capture->capture_signal), true); mcpwm_ll_intr_clear_capture_status(data->hal.dev, 1 << capture->capture_signal); capture->skip_irq = 0; @@ -476,7 +477,8 @@ static void IRAM_ATTR mcpwm_esp32_isr(const struct device *dev) capture->capture_data[capture->skip_irq].value = mcpwm_ll_capture_get_value(data->hal.dev, capture->capture_signal); capture->capture_data[capture->skip_irq].edge = - mcpwm_ll_capture_is_negedge(data->hal.dev, capture->capture_signal) + mcpwm_ll_capture_get_edge(data->hal.dev, capture->capture_signal) == + MCPWM_CAP_EDGE_NEG ? MCPWM_NEG_EDGE : MCPWM_POS_EDGE; capture->skip_irq++; @@ -550,7 +552,7 @@ static const struct pwm_driver_api mcpwm_esp32_api = { }, \ .init_config = \ { \ - .host_id = idx, \ + .group_id = idx, \ }, \ .cmd_sem = Z_SEM_INITIALIZER(mcpwm_esp32_data_##idx.cmd_sem, 1, 1), \ }; \ @@ -567,7 +569,7 @@ static const struct pwm_driver_api mcpwm_esp32_api = { CAPTURE_INIT(idx)}; \ \ DEVICE_DT_INST_DEFINE(idx, &mcpwm_esp32_init, NULL, &mcpwm_esp32_data_##idx, \ - &mcpwm_esp32_config_##idx, POST_KERNEL, \ - CONFIG_PWM_INIT_PRIORITY, &mcpwm_esp32_api); + &mcpwm_esp32_config_##idx, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \ + &mcpwm_esp32_api); DT_INST_FOREACH_STATUS_OKAY(ESP32_MCPWM_INIT) diff --git a/drivers/sensor/esp32_temp/esp32_temp.c b/drivers/sensor/esp32_temp/esp32_temp.c index 5deaecc3430..ab4efd985b8 100644 --- a/drivers/sensor/esp32_temp/esp32_temp.c +++ b/drivers/sensor/esp32_temp/esp32_temp.c @@ -18,7 +18,7 @@ LOG_MODULE_REGISTER(esp32_temp, CONFIG_SENSOR_LOG_LEVEL); #if CONFIG_SOC_SERIES_ESP32 #error "Temperature sensor not supported on ESP32" -#endif /* CONFIG_IDF_TARGET_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ struct esp32_temp_data { struct k_mutex mutex; diff --git a/drivers/serial/uart_esp32.c b/drivers/serial/uart_esp32.c index 4899d13d5b1..cb07de20adc 100644 --- a/drivers/serial/uart_esp32.c +++ b/drivers/serial/uart_esp32.c @@ -35,7 +35,7 @@ #include #include #include - +#include #include #include @@ -160,8 +160,13 @@ static int uart_esp32_config_get(const struct device *dev, struct uart_config *c uart_stop_bits_t stop_bit; uart_word_length_t data_bit; uart_hw_flowcontrol_t hw_flow; + uart_sclk_t src_clk; + uint32_t sclk_freq; - uart_hal_get_baudrate(&data->hal, &cfg->baudrate); + uart_hal_get_sclk(&data->hal, &src_clk); + esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk, + ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq); + uart_hal_get_baudrate(&data->hal, &cfg->baudrate, sclk_freq); uart_hal_get_parity(&data->hal, &parity); switch (parity) { @@ -235,6 +240,9 @@ static int uart_esp32_configure(const struct device *dev, const struct uart_conf { const struct uart_esp32_config *config = dev->config; struct uart_esp32_data *data = dev->data; + uart_sclk_t src_clk; + uint32_t sclk_freq; + int ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); if (ret < 0) { @@ -313,7 +321,10 @@ static int uart_esp32_configure(const struct device *dev, const struct uart_conf return -ENOTSUP; } - uart_hal_set_baudrate(&data->hal, cfg->baudrate); + uart_hal_get_sclk(&data->hal, &src_clk); + esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk, + ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq); + uart_hal_set_baudrate(&data->hal, cfg->baudrate, sclk_freq); uart_hal_set_rx_timeout(&data->hal, 0x16); @@ -709,7 +720,7 @@ static int uart_esp32_async_tx(const struct device *dev, const uint8_t *buf, siz dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL; dma_cfg.dma_callback = uart_esp32_dma_tx_done; dma_cfg.user_data = (void *)dev; - dma_cfg.dma_slot = GDMA_TRIG_PERIPH_UHCI0; + dma_cfg.dma_slot = ESP_GDMA_TRIG_PERIPH_UHCI0; dma_cfg.block_count = 1; dma_cfg.head_block = &dma_blk; dma_blk.block_size = len; @@ -770,7 +781,7 @@ static int uart_esp32_async_rx_enable(const struct device *dev, uint8_t *buf, si dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY; dma_cfg.dma_callback = uart_esp32_dma_rx_done; dma_cfg.user_data = (void *)dev; - dma_cfg.dma_slot = GDMA_TRIG_PERIPH_UHCI0; + dma_cfg.dma_slot = ESP_GDMA_TRIG_PERIPH_UHCI0; dma_cfg.block_count = 1; dma_cfg.head_block = &dma_blk; dma_blk.block_size = len; diff --git a/drivers/spi/spi_esp32_spim.c b/drivers/spi/spi_esp32_spim.c index 0bfed3fc8be..d209fd85b04 100644 --- a/drivers/spi/spi_esp32_spim.c +++ b/drivers/spi/spi_esp32_spim.c @@ -9,12 +9,13 @@ /* Include esp-idf headers first to avoid redefining BIT() macro */ #include #include +#include #include LOG_MODULE_REGISTER(esp32_spi, CONFIG_SPI_LOG_LEVEL); #include -#include +#include #include #ifndef CONFIG_SOC_SERIES_ESP32C3 #include @@ -177,8 +178,10 @@ static int spi_esp32_init_dma(const struct device *dev) gdma_ll_enable_clock(data->hal_gdma.dev, true); gdma_ll_tx_reset_channel(data->hal_gdma.dev, cfg->dma_host); gdma_ll_rx_reset_channel(data->hal_gdma.dev, cfg->dma_host); - gdma_ll_tx_connect_to_periph(data->hal_gdma.dev, cfg->dma_host, cfg->dma_host); - gdma_ll_rx_connect_to_periph(data->hal_gdma.dev, cfg->dma_host, cfg->dma_host); + gdma_ll_tx_connect_to_periph(data->hal_gdma.dev, cfg->dma_host, GDMA_TRIG_PERIPH_SPI, + cfg->dma_host); + gdma_ll_rx_connect_to_periph(data->hal_gdma.dev, cfg->dma_host, GDMA_TRIG_PERIPH_SPI, + cfg->dma_host); channel_offset = 0; #else channel_offset = 1; @@ -235,6 +238,13 @@ static int spi_esp32_init(const struct device *dev) return err; } + err = esp_clk_tree_src_get_freq_hz( + cfg->clock_source, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &data->clock_source_hz); + if (err) { + LOG_ERR("Could not get clock source frequency (%d)", err); + return err; + } + spi_context_unlock_unconditionally(&data->ctx); return 0; @@ -312,11 +322,11 @@ static int IRAM_ATTR spi_esp32_configure(const struct device *dev, spi_hal_timing_param_t timing_param = { .half_duplex = hal_dev->half_duplex, .no_compensate = hal_dev->no_compensate, - .clock_speed_hz = spi_cfg->frequency, + .expected_freq = spi_cfg->frequency, .duty_cycle = cfg->duty_cycle == 0 ? 128 : cfg->duty_cycle, .input_delay_ns = cfg->input_delay_ns, .use_gpio = !cfg->use_iomux, - + .clk_src_hz = data->clock_source_hz, }; spi_hal_cal_clock_conf(&timing_param, &freq, &hal_dev->timing_conf); @@ -520,6 +530,7 @@ static const struct spi_driver_api spi_api = { .cs_setup = DT_INST_PROP_OR(idx, cs_setup_time, 0), \ .cs_hold = DT_INST_PROP_OR(idx, cs_hold_time, 0), \ .line_idle_low = DT_INST_PROP(idx, line_idle_low), \ + .clock_source = SPI_CLK_SRC_DEFAULT, \ }; \ \ DEVICE_DT_INST_DEFINE(idx, &spi_esp32_init, \ diff --git a/drivers/spi/spi_esp32_spim.h b/drivers/spi/spi_esp32_spim.h index e60ca70c9be..b38c2aef8b3 100644 --- a/drivers/spi/spi_esp32_spim.h +++ b/drivers/spi/spi_esp32_spim.h @@ -39,6 +39,7 @@ struct spi_esp32_config { int cs_setup; int cs_hold; bool line_idle_low; + spi_clock_source_t clock_source; }; struct spi_esp32_data { @@ -55,6 +56,7 @@ struct spi_esp32_data { int irq_line; lldesc_t dma_desc_tx; lldesc_t dma_desc_rx; + uint32_t clock_source_hz; }; #endif /* ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_ */ diff --git a/drivers/timer/esp32_sys_timer.c b/drivers/timer/esp32_sys_timer.c index b54150c71ca..04080729911 100644 --- a/drivers/timer/esp32_sys_timer.c +++ b/drivers/timer/esp32_sys_timer.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -41,26 +42,26 @@ static systimer_hal_context_t systimer_hal; static void set_systimer_alarm(uint64_t time) { systimer_hal_select_alarm_mode(&systimer_hal, - SYSTIMER_LL_ALARM_OS_TICK_CORE0, SYSTIMER_ALARM_MODE_ONESHOT); + SYSTIMER_ALARM_OS_TICK_CORE0, SYSTIMER_ALARM_MODE_ONESHOT); systimer_counter_value_t alarm = {.val = time}; - systimer_ll_enable_alarm(systimer_hal.dev, SYSTIMER_LL_ALARM_OS_TICK_CORE0, false); - systimer_ll_set_alarm_target(systimer_hal.dev, SYSTIMER_LL_ALARM_OS_TICK_CORE0, alarm.val); - systimer_ll_apply_alarm_value(systimer_hal.dev, SYSTIMER_LL_ALARM_OS_TICK_CORE0); - systimer_ll_enable_alarm(systimer_hal.dev, SYSTIMER_LL_ALARM_OS_TICK_CORE0, true); - systimer_ll_enable_alarm_int(systimer_hal.dev, SYSTIMER_LL_ALARM_OS_TICK_CORE0, true); + systimer_ll_enable_alarm(systimer_hal.dev, SYSTIMER_ALARM_OS_TICK_CORE0, false); + systimer_ll_set_alarm_target(systimer_hal.dev, SYSTIMER_ALARM_OS_TICK_CORE0, alarm.val); + systimer_ll_apply_alarm_value(systimer_hal.dev, SYSTIMER_ALARM_OS_TICK_CORE0); + systimer_ll_enable_alarm(systimer_hal.dev, SYSTIMER_ALARM_OS_TICK_CORE0, true); + systimer_ll_enable_alarm_int(systimer_hal.dev, SYSTIMER_ALARM_OS_TICK_CORE0, true); } static uint64_t get_systimer_alarm(void) { - return systimer_hal_get_counter_value(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK); + return systimer_hal_get_counter_value(&systimer_hal, SYSTIMER_COUNTER_OS_TICK); } static void sys_timer_isr(const void *arg) { ARG_UNUSED(arg); - systimer_ll_clear_alarm_int(systimer_hal.dev, SYSTIMER_LL_ALARM_OS_TICK_CORE0); + systimer_ll_clear_alarm_int(systimer_hal.dev, SYSTIMER_ALARM_OS_TICK_CORE0); k_spinlock_key_t key = k_spin_lock(&lock); uint64_t now = get_systimer_alarm(); @@ -146,10 +147,10 @@ static int sys_clock_driver_init(void) systimer_hal_init(&systimer_hal); systimer_hal_connect_alarm_counter(&systimer_hal, - SYSTIMER_LL_ALARM_OS_TICK_CORE0, SYSTIMER_LL_COUNTER_OS_TICK); + SYSTIMER_ALARM_OS_TICK_CORE0, SYSTIMER_COUNTER_OS_TICK); - systimer_hal_enable_counter(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK); - systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 0, true); + systimer_hal_enable_counter(&systimer_hal, SYSTIMER_COUNTER_OS_TICK); + systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_COUNTER_OS_TICK, 0, true); last_count = get_systimer_alarm(); set_systimer_alarm(last_count + CYC_PER_TICK); return 0; diff --git a/drivers/wifi/esp32/Kconfig.esp32 b/drivers/wifi/esp32/Kconfig.esp32 index 4d92bc8f37b..2efbbba1ce5 100644 --- a/drivers/wifi/esp32/Kconfig.esp32 +++ b/drivers/wifi/esp32/Kconfig.esp32 @@ -15,6 +15,9 @@ menuconfig WIFI_ESP32 select MBEDTLS_ECDH_C select MBEDTLS_ECDSA_C select MBEDTLS_ECP_C + select THREAD_STACK_INFO + select DYNAMIC_THREAD + select DYNAMIC_THREAD_ALLOC help Enable ESP32 SoC WiFi support. Only supported in single core mode because the network stack is not aware of SMP @@ -43,28 +46,31 @@ config ESP32_WIFI_STA_RECONNECT help Set auto WiFI reconnection when disconnected. -config ESP32_WIFI_EVENT_TASK_STACK_SIZE - int "Event Task Stack Size" - default 4096 +config ESP32_WIFI_SW_COEXIST_ENABLE + bool + help + Software controls WiFi/Bluetooth coexistence. Not supported yet. -config ESP32_WIFI_EVENT_TASK_PRIO - int "Event Task Priority" - default 4 +config ESP32_WIFI_NET_ALLOC_SPIRAM + bool "Allocate memory of WiFi and NET in SPIRAM" + depends on ESP_SPIRAM + help + Allocate memory of WiFi and NET stack in SPIRAM, increasing available RAM memory space + for application stack. config ESP32_WIFI_STATIC_RX_BUFFER_NUM int "Max number of WiFi static RX buffers" range 2 25 default 10 help - Set the number of WiFi static RX buffers. Each buffer takes approximately - 1.6KB of RAM. The static rx buffers are allocated when esp_wifi_init is - called, they are not freed until esp_wifi_deinit is called. + Set the number of WiFi static RX buffers. Each buffer takes approximately 1.6KB of RAM. + The static rx buffers are allocated when esp_wifi_init is called, they are not freed + until esp_wifi_deinit is called. - WiFi hardware use these buffers to receive all 802.11 frames. A higher - number may allow higher throughput but increases memory use. - If ESP32_WIFI_AMPDU_RX_ENABLED is enabled, this value is recommended to - set equal or bigger than ESP32_WIFI_RX_BA_WIN in order to achieve better - throughput and compatibility with both stations and APs. + WiFi hardware use these buffers to receive all 802.11 frames. + A higher number may allow higher throughput but increases memory use. If ESP32_WIFI_AMPDU_RX_ENABLED + is enabled, this value is recommended to set equal or bigger than ESP32_WIFI_RX_BA_WIN in order to + achieve better throughput and compatibility with both stations and APs. config ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM int "Max number of WiFi dynamic RX buffers" @@ -133,6 +139,7 @@ config ESP32_WIFI_STATIC_TX_BUFFER_NUM config ESP32_WIFI_CACHE_TX_BUFFER_NUM int "Max number of WiFi cache TX buffers" + depends on ESP_SPIRAM range 16 128 default 32 help @@ -162,6 +169,7 @@ config ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM config ESP32_WIFI_CSI_ENABLED bool "WiFi CSI(Channel State Information)" + default n help Select this option to enable CSI(Channel State Information) feature. CSI takes about CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM KB of RAM. @@ -211,23 +219,17 @@ config ESP32_WIFI_RX_BA_WIN should be 16 to achieve better throughput and compatibility with both stations and APs. -choice ESP32_WIFI_TASK_CORE_ID - prompt "WiFi Task Core ID" - default ESP32_WIFI_TASK_PINNED_TO_CORE_0 - help - Pinned WiFi task to core 0 (core 1 not supported yet) - - config ESP32_WIFI_TASK_PINNED_TO_CORE_0 - bool "Core 0" -endchoice - -config ESP32_WIFI_SW_COEXIST_ENABLE - bool +config ESP32_WIFI_AMSDU_TX_ENABLED + bool "WiFi AMSDU TX" + depends on ESP_SPIRAM + default n help - Software controls WiFi/Bluetooth coexistence. Not supported yet. + Select this option to enable AMSDU TX feature config ESP32_WIFI_IRAM_OPT bool "WiFi IRAM speed optimization" + default n if (BT && ESP_SPIRAM && SOC_SERIES_ESP32) + default y help Select this option to place frequently called Wi-Fi library functions in IRAM. When this option is disabled, more than 10Kbytes of IRAM memory will be saved @@ -235,22 +237,79 @@ config ESP32_WIFI_IRAM_OPT config ESP32_WIFI_RX_IRAM_OPT bool "WiFi RX IRAM speed optimization" + default n if (BT && ESP_SPIRAM && SOC_SERIES_ESP32) help Select this option to place frequently called Wi-Fi library RX functions in IRAM. When this option is disabled, more than 17Kbytes of IRAM memory will be saved but Wi-Fi performance will be reduced. -config ESP32_WIFI_NET_ALLOC_SPIRAM - bool "Allocate memory of WiFi and NET in SPIRAM" - depends on ESP_SPIRAM +config ESP32_WIFI_FTM_ENABLE + bool "WiFi FTM" + default n + depends on SOC_SERIES_ESP32C3 help - Allocate memory of WiFi and NET stack in SPIRAM, increasing available RAM memory space - for application stack. + Enable feature Fine Timing Measurement for calculating WiFi Round-Trip-Time (RTT). + +config ESP32_WIFI_FTM_INITIATOR_SUPPORT + bool "FTM Initiator support" + default y + depends on ESP32_WIFI_FTM_ENABLE + +config ESP32_WIFI_FTM_RESPONDER_SUPPORT + bool "FTM Responder support" + default y + depends on ESP32_WIFI_FTM_ENABLE -config ESP_WIFI_SOFTAP_SUPPORT +config ESP32_WIFI_SOFTAP_SUPPORT bool default y help Hidden option to enable Wi-Fi SoftAP functions in WPA supplicant and RF libraries. +config ESP32_WIFI_MBEDTLS_CRYPTO + bool "Use MbedTLS crypto APIs" + default n + select MBEDTLS_ECP_C + select MBEDTLS_ECDH_C + select MBEDTLS_ECDSA_C + select MBEDTLS_PKCS5_C + select MBEDTLS_PK_WRITE_C + select MBEDTLS_CIPHER_MODE_CTR_ENABLED + select MBEDTLS_MAC_CMAC_ENABLED + select MBEDTLS_ZEPHYR_ENTROPY + help + Select this option to use MbedTLS crypto APIs which utilize hardware acceleration. + +config ESP32_WIFI_ENABLE_WPA3_SAE + bool "WPA3-Personal" + default n + select ESP32_WIFI_MBEDTLS_CRYPTO + help + Select this option to allow the device to establish a WPA3-Personal connection. + +config ESP32_WIFI_ENABLE_WPA3_OWE_STA + bool "OWE STA" + default y + depends on ESP32_WIFI_ENABLE_WPA3_SAE + help + Select this option to allow the device to establish OWE connection with eligible AP's. + +config ESP32_WIFI_ENABLE_SAE_PK + bool "SAE-PK" + default y + depends on ESP32_WIFI_ENABLE_WPA3_SAE + help + Select this option to enable SAE-PK + +config ESP32_WIFI_DEBUG_PRINT + bool "Print debug messages from WPA Supplicant" + default n + help + Select this option to print logging information from WPA supplicant, + this includes handshake information and key hex dumps depending + on the project logging level. + + Enabling this could increase the build size ~60kb + depending on the project logging level. + endif # WIFI_ESP32 diff --git a/drivers/wifi/esp32/src/esp_wifi_drv.c b/drivers/wifi/esp32/src/esp_wifi_drv.c index 2e86ef39552..5c17f1b4dd6 100644 --- a/drivers/wifi/esp32/src/esp_wifi_drv.c +++ b/drivers/wifi/esp32/src/esp_wifi_drv.c @@ -16,12 +16,13 @@ LOG_MODULE_REGISTER(esp32_wifi, CONFIG_WIFI_LOG_LEVEL); #include #include #include -#include "esp_networking_priv.h" #include "esp_private/wifi.h" #include "esp_event.h" #include "esp_timer.h" #include "esp_system.h" #include "esp_wpa.h" +#include +#include "wifi/wifi_event.h" #define DHCPV4_MASK (NET_EVENT_IPV4_DHCP_BOUND | NET_EVENT_IPV4_DHCP_STOP) @@ -58,14 +59,9 @@ struct esp32_wifi_runtime { struct esp32_wifi_status status; scan_result_cb_t scan_cb; uint8_t state; + uint8_t ap_connection_cnt; }; -static void esp_wifi_event_task(void *, void *, void *); - -K_MSGQ_DEFINE(esp_wifi_msgq, sizeof(system_event_t), 10, 4); -K_THREAD_STACK_DEFINE(esp_wifi_event_stack, CONFIG_ESP32_WIFI_EVENT_TASK_STACK_SIZE); -static struct k_thread esp_wifi_event_thread; - static struct net_mgmt_event_callback esp32_dhcp_cb; static void wifi_event_handler(struct net_mgmt_event_callback *cb, uint32_t mgmt_event, @@ -82,28 +78,6 @@ static void wifi_event_handler(struct net_mgmt_event_callback *cb, uint32_t mgmt } } -/* internal wifi library callback function */ -esp_err_t esp_event_send_internal(esp_event_base_t event_base, - int32_t event_id, - void *event_data, - size_t event_data_size, - uint32_t ticks_to_wait) -{ - system_event_t evt = { - .event_id = event_id, - }; - - if (event_data_size > sizeof(evt.event_info)) { - LOG_ERR("MSG %d wont find %d > %d", - event_id, event_data_size, sizeof(evt.event_info)); - return -EIO; - } - - memcpy(&evt.event_info, event_data, event_data_size); - k_msgq_put(&esp_wifi_msgq, &evt, K_FOREVER); - return 0; -} - static int esp32_wifi_send(const struct device *dev, struct net_pkt *pkt) { struct esp32_wifi_runtime *data = dev->data; @@ -208,9 +182,31 @@ static void scan_done_handler(void) strncpy(res.ssid, ap_list_buffer[k].ssid, ssid_len); res.rssi = ap_list_buffer[k].rssi; res.channel = ap_list_buffer[k].primary; - res.security = WIFI_SECURITY_TYPE_NONE; - if (ap_list_buffer[k].authmode > WIFI_AUTH_OPEN) { + switch (ap_list_buffer[k].authmode) { + case WIFI_AUTH_OPEN: + res.security = WIFI_SECURITY_TYPE_NONE; + break; + case WIFI_AUTH_WPA2_PSK: res.security = WIFI_SECURITY_TYPE_PSK; + break; + case WIFI_AUTH_WPA3_PSK: + res.security = WIFI_SECURITY_TYPE_SAE; + break; + case WIFI_AUTH_WAPI_PSK: + res.security = WIFI_SECURITY_TYPE_WAPI; + break; + case WIFI_AUTH_WPA2_ENTERPRISE: + res.security = WIFI_SECURITY_TYPE_EAP; + break; + case WIFI_AUTH_WEP: + res.security = WIFI_SECURITY_TYPE_WEP; + break; + case WIFI_AUTH_WPA_PSK: + res.security = WIFI_SECURITY_TYPE_WPA_PSK; + break; + default: + res.security = WIFI_SECURITY_TYPE_UNKNOWN; + break; } if (esp32_data.scan_cb) { @@ -232,8 +228,9 @@ static void scan_done_handler(void) esp32_data.scan_cb = NULL; } -static void esp_wifi_handle_connect_event(void) +static void esp_wifi_handle_sta_connect_event(void *event_data) { + ARG_UNUSED(event_data); esp32_data.state = ESP32_STA_CONNECTED; #if defined(CONFIG_ESP32_WIFI_STA_AUTO_DHCPV4) net_dhcpv4_start(esp32_wifi_iface); @@ -242,7 +239,7 @@ static void esp_wifi_handle_connect_event(void) #endif } -static void esp_wifi_handle_disconnect_event(void *event_data) +static void esp_wifi_handle_sta_disconnect_event(void *event_data) { wifi_event_sta_disconnected_t *event = (wifi_event_sta_disconnected_t *)event_data; @@ -280,56 +277,66 @@ static void esp_wifi_handle_disconnect_event(void *event_data) } } -static void esp_wifi_event_task(void *p1, void *p2, void *p3) +static void esp_wifi_handle_ap_connect_event(void *event_data) { - ARG_UNUSED(p2); - ARG_UNUSED(p3); - - system_event_t evt; - uint8_t s_con_cnt = 0; - - while (1) { - k_msgq_get(&esp_wifi_msgq, &evt, K_FOREVER); - - switch (evt.event_id) { - case ESP32_WIFI_EVENT_STA_START: - esp32_data.state = ESP32_STA_STARTED; - net_eth_carrier_on(esp32_wifi_iface); - break; - case ESP32_WIFI_EVENT_STA_STOP: - esp32_data.state = ESP32_STA_STOPPED; - net_eth_carrier_off(esp32_wifi_iface); - break; - case ESP32_WIFI_EVENT_STA_CONNECTED: - esp_wifi_handle_connect_event(); - break; - case ESP32_WIFI_EVENT_STA_DISCONNECTED: - esp_wifi_handle_disconnect_event(&evt.event_info); - break; - case ESP32_WIFI_EVENT_SCAN_DONE: - scan_done_handler(); - break; - case ESP32_WIFI_EVENT_AP_STOP: - esp32_data.state = ESP32_AP_STOPPED; - net_eth_carrier_off(esp32_wifi_iface); - break; - case ESP32_WIFI_EVENT_AP_STACONNECTED: - esp32_data.state = ESP32_AP_CONNECTED; - if (!s_con_cnt) { - esp_wifi_internal_reg_rxcb(WIFI_IF_AP, eth_esp32_rx); - } - s_con_cnt++; - break; - case ESP32_WIFI_EVENT_AP_STADISCONNECTED: - esp32_data.state = ESP32_AP_DISCONNECTED; - s_con_cnt--; - if (!s_con_cnt) { - esp_wifi_internal_reg_rxcb(WIFI_IF_AP, NULL); - } - break; - default: - break; - } + wifi_event_ap_staconnected_t *event = (wifi_event_ap_staconnected_t *) event_data; + + LOG_DBG("Station " MACSTR " join, AID=%d", MAC2STR(event->mac), event->aid); + wifi_mgmt_raise_connect_result_event(esp32_wifi_iface, 0); + + if (!(esp32_data.ap_connection_cnt++)) { + esp_wifi_internal_reg_rxcb(WIFI_IF_AP, eth_esp32_rx); + } +} + +static void esp_wifi_handle_ap_disconnect_event(void *event_data) +{ + wifi_event_ap_stadisconnected_t *event = (wifi_event_ap_stadisconnected_t *)event_data; + + LOG_DBG("station "MACSTR" leave, AID=%d", MAC2STR(event->mac), event->aid); + wifi_mgmt_raise_disconnect_result_event(esp32_wifi_iface, 0); + + if (!(--esp32_data.ap_connection_cnt)) { + esp_wifi_internal_reg_rxcb(WIFI_IF_AP, NULL); + } +} + +void esp_wifi_event_handler(const char *event_base, int32_t event_id, void *event_data, + size_t event_data_size, uint32_t ticks_to_wait) +{ + LOG_DBG("Wi-Fi event: %d", event_id); + switch (event_id) { + case WIFI_EVENT_STA_START: + esp32_data.state = ESP32_STA_STARTED; + net_eth_carrier_on(esp32_wifi_iface); + break; + case WIFI_EVENT_STA_STOP: + esp32_data.state = ESP32_STA_STOPPED; + net_eth_carrier_off(esp32_wifi_iface); + break; + case WIFI_EVENT_STA_CONNECTED: + esp_wifi_handle_sta_connect_event(event_data); + break; + case WIFI_EVENT_STA_DISCONNECTED: + esp_wifi_handle_sta_disconnect_event(event_data); + break; + case WIFI_EVENT_SCAN_DONE: + scan_done_handler(); + break; + case WIFI_EVENT_AP_STOP: + esp32_data.state = ESP32_AP_STOPPED; + net_eth_carrier_off(esp32_wifi_iface); + break; + case WIFI_EVENT_AP_STACONNECTED: + esp32_data.state = ESP32_AP_CONNECTED; + esp_wifi_handle_ap_connect_event(event_data); + break; + case WIFI_EVENT_AP_STADISCONNECTED: + esp32_data.state = ESP32_AP_DISCONNECTED; + esp_wifi_handle_ap_disconnect_event(event_data); + break; + default: + break; } } @@ -350,6 +357,7 @@ static int esp32_wifi_connect(const struct device *dev, struct wifi_connect_req_params *params) { struct esp32_wifi_runtime *data = dev->data; + wifi_mode_t mode; int ret; if (data->state == ESP32_STA_CONNECTING || data->state == ESP32_STA_CONNECTED) { @@ -357,6 +365,25 @@ static int esp32_wifi_connect(const struct device *dev, return -EALREADY; } + ret = esp_wifi_get_mode(&mode); + if (ret) { + LOG_ERR("Failed to get Wi-Fi mode (%d)", ret); + return -EAGAIN; + } + + if (mode != ESP32_WIFI_MODE_STA) { + ret = esp_wifi_set_mode(ESP32_WIFI_MODE_STA); + if (ret) { + LOG_ERR("Failed to set Wi-Fi mode (%d)", ret); + return -EAGAIN; + } + ret = esp_wifi_start(); + if (ret) { + LOG_ERR("Failed to start Wi-Fi driver (%d)", ret); + return -EAGAIN; + } + } + if (data->state != ESP32_STA_STARTED) { LOG_ERR("Wi-Fi not in station mode"); wifi_mgmt_raise_connect_result_event(esp32_wifi_iface, -1); @@ -374,16 +401,39 @@ static int esp32_wifi_connect(const struct device *dev, memcpy(wifi_config.sta.ssid, params->ssid, params->ssid_length); wifi_config.sta.ssid[params->ssid_length] = '\0'; - - if (params->security == WIFI_SECURITY_TYPE_PSK) { + switch (params->security) { + case WIFI_SECURITY_TYPE_NONE: + wifi_config.sta.threshold.authmode = WIFI_AUTH_OPEN; + data->status.security = WIFI_AUTH_OPEN; + wifi_config.sta.pmf_cfg.required = false; + break; + case WIFI_SECURITY_TYPE_PSK: memcpy(wifi_config.sta.password, params->psk, params->psk_length); wifi_config.sta.password[params->psk_length] = '\0'; wifi_config.sta.threshold.authmode = WIFI_AUTH_WPA2_PSK; + wifi_config.sta.pmf_cfg.required = false; data->status.security = WIFI_AUTH_WPA2_PSK; - } else if (params->security == WIFI_SECURITY_TYPE_NONE) { - wifi_config.sta.threshold.authmode = WIFI_AUTH_OPEN; - data->status.security = WIFI_AUTH_OPEN; - } else { + break; + case WIFI_SECURITY_TYPE_SAE: +#if defined(CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE) + if (params->sae_password) { + memcpy(wifi_config.sta.password, params->sae_password, + params->sae_password_length); + wifi_config.sta.password[params->sae_password_length] = '\0'; + } else { + memcpy(wifi_config.sta.password, params->psk, params->psk_length); + wifi_config.sta.password[params->psk_length] = '\0'; + } + data->status.security = WIFI_AUTH_WPA3_PSK; + wifi_config.sta.threshold.authmode = WIFI_AUTH_WPA3_PSK; + wifi_config.sta.sae_pwe_h2e = WPA3_SAE_PWE_BOTH; + break; +#else + LOG_ERR("WPA3 not supported for STA mode. Enable " + "CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE"); + return -EINVAL; +#endif /* CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE */ + default: LOG_ERR("Authentication method not supported"); return -EIO; } @@ -396,15 +446,15 @@ static int esp32_wifi_connect(const struct device *dev, data->status.channel = params->channel; } - wifi_config.sta.pmf_cfg.capable = true; - wifi_config.sta.pmf_cfg.required = false; - ret = esp_wifi_set_config(ESP_IF_WIFI_STA, &wifi_config); - ret |= esp_wifi_set_mode(ESP32_WIFI_MODE_STA); - ret |= esp_wifi_connect(); + if (ret) { + LOG_ERR("Failed to set Wi-Fi configuration (%d)", ret); + return -EINVAL; + } - if (ret != ESP_OK) { - LOG_ERR("Failed to connect to Wi-Fi access point"); + ret = esp_wifi_connect(); + if (ret) { + LOG_ERR("Failed to connect to Wi-Fi access point (%d)", ret); return -EAGAIN; } @@ -447,7 +497,7 @@ static int esp32_wifi_ap_enable(const struct device *dev, struct wifi_connect_req_params *params) { struct esp32_wifi_runtime *data = dev->data; - esp_err_t ret = 0; + esp_err_t err = 0; /* Build Wi-Fi configuration for AP mode */ wifi_config_t wifi_config = { @@ -462,22 +512,41 @@ static int esp32_wifi_ap_enable(const struct device *dev, data->status.ssid[params->ssid_length] = '\0'; strncpy((char *) wifi_config.ap.ssid, params->ssid, params->ssid_length); + wifi_config.ap.ssid_len = params->ssid_length; - if (params->psk_length == 0) { + switch (params->security) { + case WIFI_SECURITY_TYPE_NONE: memset(wifi_config.ap.password, 0, sizeof(wifi_config.ap.password)); wifi_config.ap.authmode = WIFI_AUTH_OPEN; data->status.security = WIFI_AUTH_OPEN; - } else { + wifi_config.ap.pmf_cfg.required = false; + break; + case WIFI_SECURITY_TYPE_PSK: strncpy((char *) wifi_config.ap.password, params->psk, params->psk_length); wifi_config.ap.authmode = WIFI_AUTH_WPA2_PSK; data->status.security = WIFI_AUTH_WPA2_PSK; + wifi_config.ap.pmf_cfg.required = false; + break; + default: + LOG_ERR("Authentication method not supported"); + return -EINVAL; } /* Start Wi-Fi in AP mode with configuration built above */ - ret = esp_wifi_set_mode(ESP32_WIFI_MODE_AP); - ret |= esp_wifi_set_config(WIFI_IF_AP, &wifi_config); - ret |= esp_wifi_start(); - if (ret != ESP_OK) { + err = esp_wifi_set_mode(ESP32_WIFI_MODE_AP); + if (err) { + LOG_ERR("Failed to set Wi-Fi mode (%d)", err); + return -EINVAL; + } + + err = esp_wifi_set_config(WIFI_IF_AP, &wifi_config); + if (err) { + LOG_ERR("Failed to set Wi-Fi configuration (%d)", err); + return -EINVAL; + } + + err = esp_wifi_start(); + if (err) { LOG_ERR("Failed to enable Wi-Fi AP mode"); return -EAGAIN; } @@ -489,11 +558,11 @@ static int esp32_wifi_ap_enable(const struct device *dev, static int esp32_wifi_ap_disable(const struct device *dev) { - esp_err_t ret = esp_wifi_set_mode(ESP32_WIFI_MODE_NULL); + int err = 0; - ret |= esp_wifi_start(); - if (ret != ESP_OK) { - LOG_ERR("Failed to disable Wi-Fi AP mode"); + err = esp_wifi_stop(); + if (err) { + LOG_ERR("Failed to disable Wi-Fi AP mode: (%d)", err); return -EAGAIN; } @@ -537,24 +606,30 @@ static int esp32_wifi_status(const struct device *dev, struct wifi_iface_status if (mode == ESP32_WIFI_MODE_STA) { esp_wifi_get_config(ESP_IF_WIFI_STA, &conf); esp_wifi_sta_get_ap_info(&ap_info); + status->iface_mode = WIFI_MODE_INFRA; status->channel = ap_info.primary; status->rssi = ap_info.rssi; memcpy(status->bssid, ap_info.bssid, WIFI_MAC_ADDR_LEN); - if (ap_info.phy_11n) { - status->link_mode = WIFI_4; - } else if (ap_info.phy_11g) { - status->link_mode |= WIFI_3; - } else if (ap_info.phy_11b) { + if (ap_info.phy_11b) { status->link_mode = WIFI_1; + } else if (ap_info.phy_11g) { + status->link_mode = WIFI_3; + } else if (ap_info.phy_11n) { + status->link_mode = WIFI_4; + } else if (ap_info.phy_11ax) { + status->link_mode = WIFI_6; } + status->beacon_interval = conf.sta.listen_interval; } else if (mode == ESP32_WIFI_MODE_AP) { esp_wifi_get_config(ESP_IF_WIFI_AP, &conf); status->iface_mode = WIFI_MODE_AP; status->link_mode = WIFI_LINK_MODE_UNKNOWN; status->channel = conf.ap.channel; + status->beacon_interval = conf.ap.beacon_interval; + } else { status->iface_mode = WIFI_MODE_UNKNOWN; status->link_mode = WIFI_LINK_MODE_UNKNOWN; @@ -569,6 +644,9 @@ static int esp32_wifi_status(const struct device *dev, struct wifi_iface_status case WIFI_AUTH_WPA2_PSK: status->security = WIFI_SECURITY_TYPE_PSK; break; + case WIFI_AUTH_WPA3_PSK: + status->security = WIFI_SECURITY_TYPE_SAE; + break; default: status->security = WIFI_SECURITY_TYPE_UNKNOWN; } @@ -596,6 +674,7 @@ static void esp32_wifi_init(struct net_if *iface) net_if_carrier_off(iface); wifi_init_config_t config = WIFI_INIT_CONFIG_DEFAULT(); + esp_err_t ret = esp_wifi_init(&config); esp_wifi_internal_reg_rxcb(ESP_IF_WIFI_STA, eth_esp32_rx); @@ -634,14 +713,6 @@ static int esp32_wifi_dev_init(const struct device *dev) { esp_timer_init(); - k_tid_t tid = k_thread_create(&esp_wifi_event_thread, esp_wifi_event_stack, - CONFIG_ESP32_WIFI_EVENT_TASK_STACK_SIZE, - esp_wifi_event_task, NULL, NULL, NULL, - CONFIG_ESP32_WIFI_EVENT_TASK_PRIO, K_INHERIT_PERMS, - K_NO_WAIT); - - k_thread_name_set(tid, "esp_event"); - if (IS_ENABLED(CONFIG_ESP32_WIFI_STA_AUTO_DHCPV4)) { net_mgmt_init_event_callback(&esp32_dhcp_cb, wifi_event_handler, DHCPV4_MASK); net_mgmt_add_event_callback(&esp32_dhcp_cb); diff --git a/include/zephyr/drivers/dma/dma_esp32.h b/include/zephyr/drivers/dma/dma_esp32.h index 56366e858d1..7be93c93f46 100644 --- a/include/zephyr/drivers/dma/dma_esp32.h +++ b/include/zephyr/drivers/dma/dma_esp32.h @@ -8,20 +8,20 @@ #define ZEPHYR_INCLUDE_DRIVERS_DMA_ESP32_H_ enum gdma_trigger_peripheral { - GDMA_TRIG_PERIPH_M2M = -1, - GDMA_TRIG_PERIPH_SPI2 = 0, - GDMA_TRIG_PERIPH_SPI3 = 1, - GDMA_TRIG_PERIPH_UHCI0 = 2, - GDMA_TRIG_PERIPH_I2S0 = 3, - GDMA_TRIG_PERIPH_I2S1 = 4, - GDMA_TRIG_PERIPH_LCD0 = 5, - GDMA_TRIG_PERIPH_CAM0 = 5, - GDMA_TRIG_PERIPH_AES = 6, - GDMA_TRIG_PERIPH_SHA = 7, - GDMA_TRIG_PERIPH_ADC0 = 8, - GDMA_TRIG_PERIPH_DAC0 = 8, - GDMA_TRIG_PERIPH_RMT = 9, - GDMA_TRIG_PERIPH_INVALID = 0x3F, + ESP_GDMA_TRIG_PERIPH_M2M = -1, + ESP_GDMA_TRIG_PERIPH_SPI2 = 0, + ESP_GDMA_TRIG_PERIPH_SPI3 = 1, + ESP_GDMA_TRIG_PERIPH_UHCI0 = 2, + ESP_GDMA_TRIG_PERIPH_I2S0 = 3, + ESP_GDMA_TRIG_PERIPH_I2S1 = 4, + ESP_GDMA_TRIG_PERIPH_LCD0 = 5, + ESP_GDMA_TRIG_PERIPH_CAM0 = 5, + ESP_GDMA_TRIG_PERIPH_AES = 6, + ESP_GDMA_TRIG_PERIPH_SHA = 7, + ESP_GDMA_TRIG_PERIPH_ADC0 = 8, + ESP_GDMA_TRIG_PERIPH_DAC0 = 8, + ESP_GDMA_TRIG_PERIPH_RMT = 9, + ESP_GDMA_TRIG_PERIPH_INVALID = 0x3F, }; #define ESP32_DT_INST_DMA_CTLR(n, name) \ From e63ddb70b349b6588a1a2d9ba03f34e46e1bdeff Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 6 Mar 2024 23:48:51 -0300 Subject: [PATCH 1906/2402] soc: espressif: common: update to hal_espressif v5.1 Modify and reorganize SoC to meet updated hal. Signed-off-by: Lucas Tamborrino Signed-off-by: Sylvio Alves --- soc/espressif/common/Kconfig | 209 +--------------------- soc/espressif/common/Kconfig.defconfig | 11 +- soc/espressif/common/Kconfig.esptool | 218 +++++++++++++++++++++++ soc/espressif/common/Kconfig.flash | 130 ++++++++++++++ soc/espressif/common/Kconfig.spiram | 235 +++++++++++++++++++++++++ soc/espressif/common/loader.c | 133 ++++++++++++++ 6 files changed, 723 insertions(+), 213 deletions(-) create mode 100644 soc/espressif/common/Kconfig.esptool create mode 100644 soc/espressif/common/Kconfig.flash create mode 100644 soc/espressif/common/Kconfig.spiram create mode 100644 soc/espressif/common/loader.c diff --git a/soc/espressif/common/Kconfig b/soc/espressif/common/Kconfig index 34d3c153c06..42d1961a611 100644 --- a/soc/espressif/common/Kconfig +++ b/soc/espressif/common/Kconfig @@ -1,215 +1,12 @@ # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -config ESPTOOLPY_FLASHFREQ_80M - bool - config FLASH_SIZE int config FLASH_BASE_ADDRESS hex -if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 - -config ESP_SPIRAM - bool "Support for external, SPI-connected RAM" - help - This enables support for an external SPI RAM chip, connected in - parallel with the main SPI flash chip. - -config ESP_HEAP_MIN_EXTRAM_THRESHOLD - int "Minimum threshold for external RAM allocation" - default 8192 - range 1024 131072 - depends on ESP_SPIRAM - help - Threshold to decide if memory will be allocated from DRAM - or SPIRAM. If value of allocation size is less than this value, - memory will be allocated from internal RAM. - -config ESP_HEAP_SEARCH_ALL_REGIONS - bool "Search for all available heap regions" - depends on ESP_SPIRAM - default y - help - This configuration enables searching all available heap - regions. If the region of desired capability is exhausted, - memory will be allocated from other available region. - -config ESP_SPIRAM_HEAP_SIZE - int "Size of SPIRAM heap" - default 262134 if SYS_HEAP_SMALL_ONLY - default 1048576 if !SYS_HEAP_SMALL_ONLY - depends on ESP_SPIRAM - help - Specify size of SPIRAM heap. - -menu "SPI RAM config" - depends on ESP_SPIRAM - -choice SPIRAM_MODE - prompt "Mode (QUAD/OCT) of SPI RAM chip in use" - default SPIRAM_MODE_QUAD - -config SPIRAM_MODE_QUAD - bool "Quad Mode PSRAM" - -endchoice # SPIRAM_MODE - -choice SPIRAM_TYPE - prompt "Type of SPI RAM chip in use" - depends on ESP_SPIRAM - default SPIRAM_TYPE_ESPPSRAM16 - -config SPIRAM_TYPE_ESPPSRAM16 - bool "ESP-PSRAM16 or APS1604" - -config SPIRAM_TYPE_ESPPSRAM32 - bool "ESP-PSRAM32 or IS25WP032" - -config SPIRAM_TYPE_ESPPSRAM64 - bool "ESP-PSRAM64 or LY68L6400" - -endchoice # SPIRAM_TYPE - -config ESP_SPIRAM_SIZE - int "Size of SPIRAM part" - default 2097152 if SPIRAM_TYPE_ESPPSRAM16 - default 4194304 if SPIRAM_TYPE_ESPPSRAM32 - default 8388608 if SPIRAM_TYPE_ESPPSRAM64 - help - Specify size of SPIRAM part. - NOTE: If SPIRAM size is greater than 4MB, only - lower 4MB can be allocated using k_malloc(). - -choice SPIRAM_SPEED - prompt "Set RAM clock speed" - default SPIRAM_SPEED_40M - help - Select the speed for the SPI RAM chip. - If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: - - 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz - 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz - 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz - - Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host - will be occupied by the system. Which SPI host to use can be selected by the config item - SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The - option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. - (ESPTOOLPY_FLASHFREQ_79M is true) - -config SPIRAM_SPEED_26M - bool "26MHz clock speed" - depends on SOC_SERIES_ESP32S2 - -config SPIRAM_SPEED_20M - bool "20MHz clock speed" - depends on SOC_SERIES_ESP32S2 - -config SPIRAM_SPEED_40M - bool "40MHz clock speed" - -config SPIRAM_SPEED_80M - depends on ESPTOOLPY_FLASHFREQ_80M - bool "80MHz clock speed" - -config SPIRAM_SPEED_120M - depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3 - bool "120MHz clock speed" - -endchoice # SPIRAM_SPEED - -menu "PSRAM clock and cs IO for ESP32-DOWD" - -config D0WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 17 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D0WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 16 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-DOWD - -menu "PSRAM clock and cs IO for ESP32-D2WD" - -config D2WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 9 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D2WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-D2WD - -menu "PSRAM clock and cs IO for ESP32-PICO" - -config PICO_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. - - For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock - IO. - For the reference hardware design, please refer to - https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf - -endmenu # PSRAM clock and cs IO for ESP32-PICO - -config SPIRAM_CUSTOM_SPIWP_SD3_PIN - bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" - default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5 - default n - help - This setting is only used if the SPI flash pins have been overridden by setting the eFuses - SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. - - When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka - ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI - mode, so a WP pin setting is necessary. - - If this config item is set to N (default), the correct WP pin will be automatically used for any - Espressif chip or module with integrated flash. If a custom setting is needed, set this config item - to Y and specify the GPIO number connected to the WP pin. - - When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin - configured in the bootloader. - -config SPIRAM_SPIWP_SD3_PIN - int "Custom SPI PSRAM WP(SD3) Pin" - range 0 33 - default 7 - help - The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored - - If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this - value to the GPIO number of the SPIRAM WP pin. - -config SPIRAM - bool - default y - -endmenu # SPI RAM config - -endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 +rsource "Kconfig.spiram" +rsource "Kconfig.esptool" +rsource "Kconfig.flash" diff --git a/soc/espressif/common/Kconfig.defconfig b/soc/espressif/common/Kconfig.defconfig index 62f930b0283..e451dfaae64 100644 --- a/soc/espressif/common/Kconfig.defconfig +++ b/soc/espressif/common/Kconfig.defconfig @@ -21,9 +21,6 @@ config ISR_STACK_SIZE config ATOMIC_OPERATIONS_C default y -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - config SYS_CLOCK_HW_CYCLES_PER_SEC default 16000000 @@ -33,7 +30,7 @@ config SYS_CLOCK_TICKS_PER_SEC config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE default n -config CLOCK_CONTROL +config SOC_FLASH_ESP32 default y if BOOTLOADER_MCUBOOT @@ -54,9 +51,6 @@ endif # BOOTLOADER_MCUBOOT endif # SOC_SERIES_ESP32C3 -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 # Xtensa default options for ESP32 family @@ -75,6 +69,9 @@ config GEN_IRQ_VECTOR_TABLE config CLOCK_CONTROL default y +config SOC_FLASH_ESP32 + default y + config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/espressif/common/Kconfig.esptool b/soc/espressif/common/Kconfig.esptool new file mode 100644 index 00000000000..f7c6e7b5c34 --- /dev/null +++ b/soc/espressif/common/Kconfig.esptool @@ -0,0 +1,218 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ESPRESSIF_ESP32 + +config ESPTOOLPY_OCT_FLASH + bool "Use Octal Flash" + depends on SOC_SERIES_ESP32S3 + default n + +config ESPTOOLPY_FLASH_MODE_AUTO_DETECT + depends on SOC_SERIES_ESP32S3 + bool "Choose flash mode automatically (please read help)" + default y + help + This config option helps decide whether flash is Quad or Octal, but please note some limitations: + + 1. If the flash chip is an Octal one, even if one of "QIO", "QOUT", "DIO", "DOUT" options is + selected in `ESPTOOLPY_FLASHMODE`, our code will automatically change the + mode to "OPI" and the sample mode will be STR. + 2. If the flash chip is a Quad one, even if "OPI" is selected in `ESPTOOLPY_FLASHMODE`, our code will + automatically change the mode to "DIO". + 3. Please do not rely on this option when you are pretty sure that you are using Octal flash, + please enable `ESPTOOLPY_OCT_FLASH` option, then you can choose `DTR` sample mode + in `ESPTOOLPY_FLASH_SAMPLE_MODE`. Otherwise, only `STR` mode is available. + 4. Enabling this feature reduces available internal RAM size (around 900 bytes). + If your IRAM space is insufficient and you're aware of your flash type, + disable this option and select corresponding flash type options. + +choice ESPTOOLPY_FLASHMODE + prompt "Flash SPI mode" + default ESPTOOLPY_FLASHMODE_DIO + default ESPTOOLPY_FLASHMODE_OPI if ESPTOOLPY_OCT_FLASH + help + Mode the flash chip is flashed in, as well as the default mode for the + binary to run in. + +config ESPTOOLPY_FLASHMODE_QIO + bool "QIO" + depends on !ESPTOOLPY_OCT_FLASH +config ESPTOOLPY_FLASHMODE_QOUT + bool "QOUT" + depends on !ESPTOOLPY_OCT_FLASH +config ESPTOOLPY_FLASHMODE_DIO + bool "DIO" + depends on !ESPTOOLPY_OCT_FLASH +config ESPTOOLPY_FLASHMODE_DOUT + bool "DOUT" + depends on !ESPTOOLPY_OCT_FLASH +config ESPTOOLPY_FLASHMODE_OPI + bool "OPI" + depends on ESPTOOLPY_OCT_FLASH + +endchoice # ESPTOOLPY_FLASHMODE + +choice ESPTOOLPY_FLASH_SAMPLE_MODE + prompt "Flash Sampling Mode" + default ESPTOOLPY_FLASH_SAMPLE_MODE_DTR if ESPTOOLPY_OCT_FLASH + default ESPTOOLPY_FLASH_SAMPLE_MODE_STR if !ESPTOOLPY_OCT_FLASH + +config ESPTOOLPY_FLASH_SAMPLE_MODE_STR + bool "STR Mode" +config ESPTOOLPY_FLASH_SAMPLE_MODE_DTR + bool "DTR Mode" + depends on ESPTOOLPY_OCT_FLASH + +endchoice # ESPTOOLPY_FLASH_SAMPLE_MODE + +config ESPTOOLPY_FLASHMODE + string + default "dio" if ESPTOOLPY_FLASHMODE_QIO + default "dio" if ESPTOOLPY_FLASHMODE_QOUT + default "dio" if ESPTOOLPY_FLASHMODE_DIO + default "dout" if ESPTOOLPY_FLASHMODE_DOUT + # The 1st and 2nd bootloader doesn't support opi mode, + # using fastrd instead. For now the ESPTOOL doesn't support + # fasted (see ESPTOOL-274), using dout instead. In ROM the flash mode + # information get from efuse, so don't care this dout choice. + default "dout" if ESPTOOLPY_FLASHMODE_OPI + +choice ESPTOOLPY_FLASHFREQ + prompt "Flash SPI speed" + default ESPTOOLPY_FLASHFREQ_40M if SOC_SERIES_ESP32 + default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT + +config ESPTOOLPY_FLASHFREQ_120M + bool "120 MHz" + select SPI_FLASH_HPM_ENABLE + depends on SOC_SERIES_ESP32S3 && ESPTOOLPY_FLASH_SAMPLE_MODE_STR + help + - Flash 120 MHz SDR mode is stable. + - Flash 120 MHz DDR mode is an experimental feature, it works when + the temperature is stable. + + Risks: + If your chip powers on at a certain temperature, then after the temperature + increases or decreases by approximately 20 Celsius degrees (depending on the + chip), the program will crash randomly. + +config ESPTOOLPY_FLASHFREQ_80M + bool "80 MHz" +config ESPTOOLPY_FLASHFREQ_40M + bool "40 MHz" +config ESPTOOLPY_FLASHFREQ_26M + bool "26 MHz" + depends on !SOC_SERIES_ESP32S3 +config ESPTOOLPY_FLASHFREQ_20M + bool "20 MHz" + +endchoice # ESPTOOLPY_FLASHFREQ + +config ESPTOOLPY_FLASHFREQ_80M_DEFAULT + bool + default y if SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 || SOC_SERIES_ESP32C3 + help + This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed. + +config ESPTOOLPY_FLASHFREQ + string + # On some of the ESP chips, max boot frequency would be equal to (or even lower than) 80m. + # We currently define this to `80m`. + default '80m' if ESPTOOLPY_FLASHFREQ_120M + default '80m' if ESPTOOLPY_FLASHFREQ_80M + default '40m' if ESPTOOLPY_FLASHFREQ_40M + default '26m' if ESPTOOLPY_FLASHFREQ_26M + default '20m' if ESPTOOLPY_FLASHFREQ_20M + default '20m' # if no clock can match in bin headers, go with minimal. + +choice ESPTOOLPY_FLASHSIZE + prompt "Flash size" + default ESPTOOLPY_FLASHSIZE_2MB + help + SPI flash size, in megabytes + + config ESPTOOLPY_FLASHSIZE_1MB + bool "1 MB" + config ESPTOOLPY_FLASHSIZE_2MB + bool "2 MB" + config ESPTOOLPY_FLASHSIZE_4MB + bool "4 MB" + config ESPTOOLPY_FLASHSIZE_8MB + bool "8 MB" + config ESPTOOLPY_FLASHSIZE_16MB + bool "16 MB" + config ESPTOOLPY_FLASHSIZE_32MB + bool "32 MB" + config ESPTOOLPY_FLASHSIZE_64MB + bool "64 MB" + config ESPTOOLPY_FLASHSIZE_128MB + bool "128 MB" +endchoice + +config ESPTOOLPY_FLASHSIZE + string + default "1MB" if ESPTOOLPY_FLASHSIZE_1MB + default "2MB" if ESPTOOLPY_FLASHSIZE_2MB + default "4MB" if ESPTOOLPY_FLASHSIZE_4MB + default "8MB" if ESPTOOLPY_FLASHSIZE_8MB + default "16MB" if ESPTOOLPY_FLASHSIZE_16MB + default "32MB" if ESPTOOLPY_FLASHSIZE_32MB + default "64MB" if ESPTOOLPY_FLASHSIZE_64MB + default "128MB" if ESPTOOLPY_FLASHSIZE_128MB + +config ESPTOOLPY_HEADER_FLASHSIZE_UPDATE + bool "Detect flash size when flashing bootloader" + default n + help + If this option is set, flashing the project will automatically detect + the flash size of the target chip and update the bootloader image + before it is flashed. + + Enabling this option turns off the image protection against corruption + by a SHA256 digest. Updating the bootloader image before flashing would + invalidate the digest. + +choice ESPTOOLPY_BEFORE + prompt "Before flashing" + default ESPTOOLPY_BEFORE_RESET + help + Configure whether esptool.py should reset the ESP32 before flashing. + + Automatic resetting depends on the RTS & DTR signals being + wired from the serial port to the ESP32. Most USB development + boards do this internally. + + config ESPTOOLPY_BEFORE_RESET + bool "Reset to bootloader" + config ESPTOOLPY_BEFORE_NORESET + bool "No reset" +endchoice # ESPTOOLPY_BEFORE + +config ESPTOOLPY_BEFORE + string + default "default_reset" if ESPTOOLPY_BEFORE_RESET + default "no_reset" if ESPTOOLPY_BEFORE_NORESET + +choice ESPTOOLPY_AFTER + prompt "After flashing" + default ESPTOOLPY_AFTER_RESET + help + Configure whether esptool.py should reset the ESP32 after flashing. + + Automatic resetting depends on the RTS & DTR signals being + wired from the serial port to the ESP32. Most USB development + boards do this internally. + + config ESPTOOLPY_AFTER_RESET + bool "Reset after flashing" + config ESPTOOLPY_AFTER_NORESET + bool "Stay in bootloader" +endchoice + +config ESPTOOLPY_AFTER + string + default "hard_reset" if ESPTOOLPY_AFTER_RESET + default "no_reset" if ESPTOOLPY_AFTER_NORESET + +endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/common/Kconfig.flash b/soc/espressif/common/Kconfig.flash new file mode 100644 index 00000000000..3dd465c6868 --- /dev/null +++ b/soc/espressif/common/Kconfig.flash @@ -0,0 +1,130 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ESPRESSIF_ESP32 + +config MMU_PAGE_SIZE + hex + default 0x10000 + +config SPI_FLASH_VENDOR_MXIC_SUPPORTED + bool + default y + +config SPI_FLASH_SUPPORT_ISSI_CHIP + bool "ISSI" + default y + help + Enable this to support auto detection of ISSI chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_SUPPORT_MXIC_CHIP + bool "MXIC" + default y + help + Enable this to support auto detection of MXIC chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_SUPPORT_GD_CHIP + bool "GigaDevice" + default y + help + Enable this to support auto detection of GD (GigaDevice) chips if chip vendor not + directly given by ``chip_drv`` member of the chip struct. If you are using Wrover + modules, please don't disable this, otherwise your flash may not work in 4-bit + mode. + + This adds support for variant chips, however will extend detecting time and image + size. Note that the default chip driver supports the GD chips with product ID + 60H. + +config SPI_FLASH_SUPPORT_WINBOND_CHIP + bool "Winbond" + default y + help + Enable this to support auto detection of Winbond chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_SUPPORT_BOYA_CHIP + bool "BOYA" + default y if !SOC_SERIES_ESP32 + help + Enable this to support auto detection of BOYA chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_SUPPORT_TH_CHIP + bool "TH" + default y if !SOC_SERIES_ESP32 + help + Enable this to support auto detection of TH chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_SUPPORT_MXIC_OPI_CHIP + bool "mxic (opi)" + depends on SOC_SERIES_ESP32S3 + default y + help + Enable this to support auto detection of Octal MXIC chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_ROM_DRIVER_PATCH + bool "SPI flash ROM driver patched functions" + default y + help + Enable this flag to use patched versions of SPI flash ROM driver functions. + This option should be enabled, if any one of the following is true: (1) need to write + to flash on ESP32-D2WD; (2) main SPI flash is connected to non-default pins; (3) main + SPI flash chip is manufactured by ISSI. + +config BOOTLOADER_FLASH_XMC_SUPPORT + bool "Support flash chips of XMC (READ HELP FIRST)" + default y + help + Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow. + XMC chips will be forbidden to be used, when this option is disabled. + + DON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING. + +choice BOOTLOADER_VDDSDIO_BOOST + bool "VDDSDIO LDO voltage" + default BOOTLOADER_VDDSDIO_BOOST_1_9V + depends on !SOC_SERIES_ESP32C3 + help + If this option is enabled, and VDDSDIO LDO is set to 1.8V (using eFuse + or MTDI bootstrapping pin), bootloader will change LDO settings to + output 1.9V instead. This helps prevent flash chip from browning out + during flash programming operations. + + This option has no effect if VDDSDIO is set to 3.3V, or if the internal + VDDSDIO regulator is disabled via eFuse. + + config BOOTLOADER_VDDSDIO_BOOST_1_8V + bool "1.8V" + depends on !ESPTOOLPY_FLASHFREQ_80M + config BOOTLOADER_VDDSDIO_BOOST_1_9V + bool "1.9V" +endchoice + +config BOOTLOADER_REGION_PROTECTION_ENABLE + bool "Protect unmapped memory regions from unintended accesses" + default y + help + Protects the unmapped memory regions of the entire address space from unintended accesses. + This will ensure that an exception will be triggered whenever the CPU performs a memory + operation on unmapped regions of the address space. + +config SPI_FLASH_HPM_ENABLE + bool + depends on SOC_SERIES_ESP32S3 + default n + help + This option is invisible, and will be selected automatically + when ``ESPTOOLPY_FLASHFREQ_120M`` is selected. + +endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/common/Kconfig.spiram b/soc/espressif/common/Kconfig.spiram new file mode 100644 index 00000000000..0daad784aa9 --- /dev/null +++ b/soc/espressif/common/Kconfig.spiram @@ -0,0 +1,235 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + +config ESP_SPIRAM + bool "Support for external, SPI-connected RAM" + default n if MCUBOOT + help + This enables support for an external SPI RAM chip, connected in + parallel with the main SPI flash chip. + +menu "SPI RAM config" + depends on ESP_SPIRAM + +config ESP_HEAP_MIN_EXTRAM_THRESHOLD + int "Minimum threshold for external RAM allocation" + default 8192 + range 1024 131072 + help + Threshold to decide if memory will be allocated from DRAM + or SPIRAM. If value of allocation size is less than this value, + memory will be allocated from internal RAM. + +config ESP_HEAP_SEARCH_ALL_REGIONS + bool "Search for all available heap regions" + default y + help + This configuration enables searching all available heap + regions. If the region of desired capability is exhausted, + memory will be allocated from other available region. + +config ESP_SPIRAM_HEAP_SIZE + int "Size of SPIRAM heap" + default 262134 if SYS_HEAP_SMALL_ONLY + default 1048576 if !SYS_HEAP_SMALL_ONLY + help + Specify size of SPIRAM heap. + +choice SPIRAM_MODE + prompt "Mode (QUAD/OCT) of SPI RAM chip in use" + default SPIRAM_MODE_QUAD + + config SPIRAM_MODE_QUAD + bool "Quad Mode PSRAM" + + config SPIRAM_MODE_OCT + bool "Octal Mode PSRAM" + depends on SOC_SERIES_ESP32S3 + +endchoice # SPIRAM_MODE + +choice SPIRAM_TYPE + prompt "Type of SPI RAM chip in use" + default SPIRAM_TYPE_ESPPSRAM16 if SPIRAM_MODE_QUAD + default SPIRAM_TYPE_ESPPSRAM64 + +config SPIRAM_TYPE_ESPPSRAM16 + bool "ESP-PSRAM16 or APS1604" + depends on SPIRAM_MODE_QUAD + +config SPIRAM_TYPE_ESPPSRAM32 + bool "ESP-PSRAM32 or IS25WP032" + depends on SPIRAM_MODE_QUAD + +config SPIRAM_TYPE_ESPPSRAM64 + bool "ESP-PSRAM64, LY68L6400 or APS6408" + +endchoice # SPIRAM_TYPE + +config ESP_SPIRAM_SIZE + int "Size of SPIRAM part" + default 2097152 if SPIRAM_TYPE_ESPPSRAM16 + default 4194304 if SPIRAM_TYPE_ESPPSRAM32 + default 8388608 if SPIRAM_TYPE_ESPPSRAM64 + help + Specify size of SPIRAM part. + NOTE: If SPIRAM size is greater than 4MB, only + lower 4MB can be allocated using k_malloc(). + +choice SPIRAM_SPEED + prompt "Set RAM clock speed" + default SPIRAM_SPEED_40M + help + Select the speed for the SPI RAM chip. + +config SPIRAM_SPEED_20M + bool "20MHz clock speed" + depends on SOC_SERIES_ESP32S2 + +config SPIRAM_SPEED_26M + bool "26MHz clock speed" + depends on SOC_SERIES_ESP32S2 + +config SPIRAM_SPEED_40M + bool "40MHz clock speed" + +config SPIRAM_SPEED_80M + bool "80MHz clock speed" + depends on ESPTOOLPY_FLASHFREQ_80M + +config SPIRAM_SPEED_120M + bool "120MHz clock speed" + depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3 + +endchoice # SPIRAM_SPEED + +config SPIRAM_SPEED + int + default 120 if SPIRAM_SPEED_120M + default 80 if SPIRAM_SPEED_80M + default 40 if SPIRAM_SPEED_40M || SPIRAM_SPEED_26M || SPIRAM_SPEED_20M + +config SPIRAM_CLK_IO + int + depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + default 30 + +config SPIRAM_CS_IO + int + depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + default 26 + +config SPIRAM_FETCH_INSTRUCTIONS + bool "Move Instructions in Flash to PSRAM" + depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + default n + help + If enabled, instructions in flash will be moved into PSRAM on startup. + If SPIRAM_RODATA is also enabled, code that requires execution during an SPI1 Flash operation + can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation + for more details). + +config SPIRAM_RODATA + bool "Move Read-Only Data in Flash to PSRAM" + depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + default n + help + If enabled, rodata in flash will be moved into PSRAM on startup. + If SPIRAM_FETCH_INSTRUCTIONS is also enabled, code that requires execution during an SPI1 Flash operation + can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation + for more details). + +if SOC_SERIES_ESP32 + +menu "PSRAM clock and cs IO for ESP32-DOWD" + +config D0WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 17 + help + The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use + 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D0WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 16 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use + 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endmenu # PSRAM clock and cs IO for ESP32-DOWD + +menu "PSRAM clock and cs IO for ESP32-D2WD" + +config D2WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 9 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D2WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endmenu # PSRAM clock and cs IO for ESP32-D2WD + +menu "PSRAM clock and cs IO for ESP32-PICO" + +config PICO_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. + + For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock + IO For the reference hardware design, please refer to + https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf + +endmenu # PSRAM clock and cs IO for ESP32-PICO + +config SPIRAM_CUSTOM_SPIWP_SD3_PIN + bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" + depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT + default n + help + This setting is only used if the SPI flash pins have been overridden by setting the eFuses + SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. + + When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka + ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI + mode, so a WP pin setting is necessary. + + If this config item is set to N (default), the correct WP pin will be automatically used for any + Espressif chip or module with integrated flash. If a custom setting is needed, set this config item + to Y and specify the GPIO number connected to the WP pin. + + When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin + configured in the bootloader. + +config SPIRAM_SPIWP_SD3_PIN + int "Custom SPI PSRAM WP(SD3) Pin" + depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN + range 0 33 + default 7 + help + The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored + + If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this + value to the GPIO number of the SPIRAM WP pin. + +endif # SOC_SERIES_ESP32 + +endmenu # ESP_SPIRAM + +endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 diff --git a/soc/espressif/common/loader.c b/soc/espressif/common/loader.c new file mode 100644 index 00000000000..6d1b7ecba0e --- /dev/null +++ b/soc/espressif/common/loader.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MMU_FLASH_MASK (~(CONFIG_MMU_PAGE_SIZE - 1)) + +#ifdef CONFIG_BOOTLOADER_MCUBOOT +#include +#include "esp_rom_uart.h" + +#define BOOT_LOG_INF(_fmt, ...) \ + ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) + +#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) + +void __start(void); + +static HDR_ATTR void (*_entry_point)(void) = &__start; + +extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; +extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ + +void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, + uint32_t app_drom_size, uint32_t app_irom_start, + uint32_t app_irom_vaddr, uint32_t app_irom_size) +{ + uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK; + + uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK; + uint32_t actual_mapped_len = 0; + +#if CONFIG_SOC_SERIES_ESP32 + Cache_Read_Disable(0); + Cache_Flush(0); +#else + cache_hal_disable(CACHE_TYPE_ALL); +#endif + + /* Clear the MMU entries that are already set up, + * so the new app only has the mappings it creates. + */ + mmu_hal_unmap_all(); + +#if CONFIG_SOC_SERIES_ESP32 + int rc = 0; + uint32_t drom_page_count = + (app_drom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; + + rc |= cache_flash_mmu_set(0, 0, app_drom_vaddr_aligned, + app_drom_start_aligned, 64, drom_page_count); + rc |= cache_flash_mmu_set(1, 0, app_drom_vaddr_aligned, + app_drom_start_aligned, 64, drom_page_count); + + uint32_t irom_page_count = + (app_irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; + + rc |= cache_flash_mmu_set(0, 0, app_irom_vaddr_aligned, + app_irom_start_aligned, 64, irom_page_count); + rc |= cache_flash_mmu_set(1, 0, app_irom_vaddr_aligned, + app_irom_start_aligned, 64, irom_page_count); + if (rc != 0) { + esp_rom_printf("Failed to setup XIP, aborting\n"); + abort(); + } +#else + mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_drom_vaddr_aligned, app_drom_start_aligned, + app_drom_size, &actual_mapped_len); + + mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_irom_vaddr_aligned, app_irom_start_aligned, + app_irom_size, &actual_mapped_len); +#endif + + /* ----------------------Enable corresponding buses---------------- */ + cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned, app_drom_size); + + cache_ll_l1_enable_bus(0, bus_mask); + bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(0, bus_mask); +#if CONFIG_MP_MAX_NUM_CPUS > 1 + bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size); + cache_ll_l1_enable_bus(1, bus_mask); + bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(1, bus_mask); +#endif + + /* ----------------------Enable Cache---------------- */ +#if CONFIG_SOC_SERIES_ESP32 + /* Application will need to do Cache_Flush(1) and Cache_Read_Enable(1) */ + Cache_Read_Enable(0); +#else + cache_hal_enable(CACHE_TYPE_ALL); +#endif +} + +void __start(void) +{ +#ifdef CONFIG_BOOTLOADER_MCUBOOT + size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition); + uint32_t _app_irom_start = (_partition_offset + (uint32_t)&_image_irom_start); + uint32_t _app_irom_size = (uint32_t)&_image_irom_size; + uint32_t _app_irom_vaddr = ((uint32_t)&_image_irom_vaddr); + + uint32_t _app_drom_start = (_partition_offset + (uint32_t)&_image_drom_start); + uint32_t _app_drom_size = (uint32_t)&_image_drom_size; + uint32_t _app_drom_vaddr = ((uint32_t)&_image_drom_vaddr); + uint32_t actual_mapped_len = 0; + + map_rom_segments(_app_drom_start, _app_drom_vaddr, _app_drom_size, + _app_irom_start, _app_irom_vaddr, _app_irom_size); + + /* Show map segments continue using same log format as during MCUboot phase */ + BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map", + _app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size); + BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n", + _app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size); + esp_rom_uart_tx_wait_idle(0); +#endif + __esp_platform_start(); +} From e58724970481ceb9b3024dc060871a6bdea920df Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 6 Mar 2024 23:47:31 -0300 Subject: [PATCH 1907/2402] soc: espressif: esp32: update to hal_espressif v5.1 Modify and reorganize SoC to meet updated hal. Signed-off-by: Sylvio Alves Signed-off-by: Lucas Tamborrino --- arch/xtensa/core/xtensa_backtrace.c | 2 +- .../zephyr/dt-bindings/clock/esp32_clock.h | 8 +- scripts/west_commands/runners/esp32.py | 6 +- soc/espressif/Kconfig | 39 ++++++ soc/espressif/esp32/CMakeLists.txt | 66 +++------ soc/espressif/esp32/Kconfig | 126 ------------------ soc/espressif/esp32/Kconfig.defconfig | 12 -- soc/espressif/esp32/Kconfig.mac | 45 +++++++ soc/espressif/esp32/Kconfig.rtc | 77 +++++++++++ soc/espressif/esp32/default.ld | 86 +++++++++++- soc/espressif/esp32/esp32-mp.c | 2 +- soc/espressif/esp32/loader.c | 108 --------------- soc/espressif/esp32/mcuboot.ld | 9 +- soc/espressif/esp32/soc.c | 126 ++++++------------ soc/espressif/esp32/soc.h | 2 +- soc/espressif/esp32/soc_appcpu.c | 83 ++---------- 16 files changed, 331 insertions(+), 466 deletions(-) create mode 100644 soc/espressif/esp32/Kconfig.mac create mode 100644 soc/espressif/esp32/Kconfig.rtc delete mode 100644 soc/espressif/esp32/loader.c diff --git a/arch/xtensa/core/xtensa_backtrace.c b/arch/xtensa/core/xtensa_backtrace.c index 5871a10c48f..8570fa5dbd6 100644 --- a/arch/xtensa/core/xtensa_backtrace.c +++ b/arch/xtensa/core/xtensa_backtrace.c @@ -8,7 +8,7 @@ #include "xtensa_backtrace.h" #include #if defined(CONFIG_SOC_SERIES_ESP32) -#include "soc/soc_memory_layout.h" +#include #elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP) #include "debug_helpers.h" #elif defined(CONFIG_SOC_XTENSA_DC233C) diff --git a/include/zephyr/dt-bindings/clock/esp32_clock.h b/include/zephyr/dt-bindings/clock/esp32_clock.h index 65ca36c3609..99ab3c7004b 100644 --- a/include/zephyr/dt-bindings/clock/esp32_clock.h +++ b/include/zephyr/dt-bindings/clock/esp32_clock.h @@ -22,10 +22,10 @@ #define ESP32_CLK_CPU_240M 240000000 /* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_24M 0U -#define ESP32_CLK_XTAL_26M 1U -#define ESP32_CLK_XTAL_40M 2U -#define ESP32_CLK_XTAL_AUTO 3U +#define ESP32_CLK_XTAL_24M 24 +#define ESP32_CLK_XTAL_26M 26 +#define ESP32_CLK_XTAL_40M 40 +#define ESP32_CLK_XTAL_AUTO 0 /* Supported RTC fast clock frequencies */ #define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U diff --git a/scripts/west_commands/runners/esp32.py b/scripts/west_commands/runners/esp32.py index 0ccf0c98d1f..b68ddd9b2f7 100644 --- a/scripts/west_commands/runners/esp32.py +++ b/scripts/west_commands/runners/esp32.py @@ -71,7 +71,7 @@ def do_add_parser(cls, parser): parser.add_argument( '--esp-tool', help='''if given, complete path to espidf. default is to search for - it in [ESP_IDF_PATH]/components/esptool_py/esptool/esptool.py''') + it in [ESP_IDF_PATH]/tools/esptool_py/esptool.py''') parser.add_argument('--esp-flash-bootloader', help='Bootloader image to flash') parser.add_argument('--esp-flash-partition_table', @@ -86,8 +86,8 @@ def do_create(cls, cfg, args): if args.esp_tool: espidf = args.esp_tool else: - espidf = path.join(args.esp_idf_path, 'components', 'esptool_py', - 'esptool', 'esptool.py') + espidf = path.join(args.esp_idf_path, 'tools', 'esptool_py', + 'esptool.py') return Esp32BinaryRunner( cfg, args.esp_device, boot_address=args.esp_boot_address, diff --git a/soc/espressif/Kconfig b/soc/espressif/Kconfig index 3c96a64bff6..1917c3b432b 100644 --- a/soc/espressif/Kconfig +++ b/soc/espressif/Kconfig @@ -5,4 +5,43 @@ if SOC_FAMILY_ESPRESSIF_ESP32 rsource "*/Kconfig" +menu "MAC Config" + +config ESP_MAC_ADDR_UNIVERSE_WIFI_STA + bool + +config ESP_MAC_ADDR_UNIVERSE_WIFI_AP + bool + +config ESP_MAC_ADDR_UNIVERSE_ETH + bool + +config ESP_MAC_ADDR_UNIVERSE_BT + bool + +config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_ONE + bool + +config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO + bool + +config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR + bool + +# Insert chip-specific MAC config +rsource "*/Kconfig.mac" + +endmenu + +menu "RTC Clock Config" + +config ESP_SYSTEM_RTC_EXT_XTAL + bool + +config ESP_SYSTEM_RTC_EXT_OSC + bool + +rsource "*/Kconfig.rtc" +endmenu + endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/esp32/CMakeLists.txt b/soc/espressif/esp32/CMakeLists.txt index 537c7c76acc..b1ad883b3e3 100644 --- a/soc/espressif/esp32/CMakeLists.txt +++ b/soc/espressif/esp32/CMakeLists.txt @@ -1,12 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_ESP32_APPCPU) +if (CONFIG_SOC_ESP32_APPCPU) zephyr_sources(soc_appcpu.c) else() zephyr_sources( soc.c - loader.c esp32-mp.c + ../common/loader.c ) endif() @@ -23,60 +23,31 @@ zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") - add_dependencies(app EspIdfBootloader EspPartitionTable) + if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") + endif() - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") + endif() + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + endif() if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py ARGS --chip esp32 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) @@ -85,10 +56,12 @@ if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) if(CONFIG_MCUBOOT) board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") endif() + endif() ## When building for APPCPU -if(CONFIG_SOC_ESP32_APPCPU) +if (CONFIG_SOC_ESP32_APPCPU) + if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py @@ -96,6 +69,7 @@ if(CONFIG_SOC_ESP32_APPCPU) -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c -a "esp32_appcpu_fw_array") endif() + else() set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) diff --git a/soc/espressif/esp32/Kconfig b/soc/espressif/esp32/Kconfig index 26305dd553f..67df8e255a5 100644 --- a/soc/espressif/esp32/Kconfig +++ b/soc/espressif/esp32/Kconfig @@ -41,12 +41,6 @@ config SOC_ENABLE_APPCPU help This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled. -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - config ESP32_BT_RESERVE_DRAM hex "Bluetooth controller reserved RAM region" default 0xdb5c if BT @@ -63,77 +57,6 @@ config ESP_HEAP_MEM_POOL_REGION_1_SIZE This configuration can be used to add memory from region 1 to heap and can be allocated using k_malloc. -choice ESP32_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - - "Internal 150kHz oscillator" option provides lowest deep sleep current - consumption, and does not require extra external components. However - frequency stability with respect to temperature is poor, so time may - drift in deep/light sleep modes. - - "External 32kHz crystal" provides better frequency stability, at the - expense of slightly higher (1uA) deep sleep current consumption. - - "External 32kHz oscillator" allows using 32kHz clock generated by an - external circuit. In this case, external clock signal must be connected - to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, - and <1V in case of square wave signal. Common mode voltage should be - 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. - Additionally, 1nF capacitor must be connected between 32K_XP pin and - ground. 32K_XP pin can not be used as a GPIO in this case. - - "Internal 8.5MHz oscillator divided by 256" option results in higher - deep sleep current (by 5uA) but has better frequency stability than - the internal 150kHz oscillator. It does not require external components. - -config ESP32_RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - -config ESP32_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XN pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" - -endchoice # ESP32_RTC_CLK_SRC - -config ESP32_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -config ESP32_RTC_XTAL_CAL_RETRY - int "Number of attempts to repeat 32k XTAL calibration" - default 1 - depends on ESP32_RTC_CLK_SRC_EXT_CRYS - help - Number of attempts to repeat 32k XTAL calibration - before giving up and switching to the internal RC. - Increase this option if the 32k crystal oscillator - does not start and switches to internal RC. - config ESP32_DEEP_SLEEP_WAKEUP_DELAY int "Extra delay in deep sleep wake stub (in us)" default 2000 @@ -152,55 +75,6 @@ config ESP32_DEEP_SLEEP_WAKEUP_DELAY If you are seeing "flash read err, 1000" message printed to the console after deep sleep reset, try increasing this value. -choice ESP32_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is four, - all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally - administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) - to the final octet of the base MAC address. If the number of universal MAC addresses is two, - only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. - These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. - The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. - These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 2 or 4 per device.) - -config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_BT - -config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - bool "Four" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - select ESP_MAC_ADDR_UNIVERSE_BT - select ESP_MAC_ADDR_UNIVERSE_ETH - -endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP_MAC_ADDR_UNIVERSE_BT - bool - -config ESP_MAC_ADDR_UNIVERSE_ETH - bool - -config ESP32_UNIVERSAL_MAC_ADDRESSES - int - default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - config ESP32_PHY_MAX_WIFI_TX_POWER int "Max WiFi/BLE TX power (dBm)" range 10 20 diff --git a/soc/espressif/esp32/Kconfig.defconfig b/soc/espressif/esp32/Kconfig.defconfig index 17bda587b97..74f7949e714 100644 --- a/soc/espressif/esp32/Kconfig.defconfig +++ b/soc/espressif/esp32/Kconfig.defconfig @@ -3,18 +3,6 @@ if SOC_SERIES_ESP32 -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config ESPTOOLPY_FLASHFREQ_80M - default y - config FLASH_SIZE default $(dt_node_reg_size_int,/soc/flash-controller@3ff42000/flash@0,0) diff --git a/soc/espressif/esp32/Kconfig.mac b/soc/espressif/esp32/Kconfig.mac new file mode 100644 index 00000000000..b149bc5e905 --- /dev/null +++ b/soc/espressif/esp32/Kconfig.mac @@ -0,0 +1,45 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32 + +choice ESP32_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or + derived from a single base MAC address. If the number of universal MAC addresses is four, + all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally + administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) + to the final octet of the base MAC address. If the number of universal MAC addresses is two, + only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. + These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. + The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. + These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. + When using the default (Espressif-assigned) base MAC address, either setting can be used. + When using a custom universal MAC address range, the correct setting will depend on the + allocation of MAC addresses in this range (either 2 or 4 per device.) + +config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_BT + +config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + bool "Four" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + select ESP_MAC_ADDR_UNIVERSE_BT + select ESP_MAC_ADDR_UNIVERSE_ETH + +endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES + +config ESP32_UNIVERSAL_MAC_ADDRESSES + int + default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + +endif # SOC_SERIES_ESP32 diff --git a/soc/espressif/esp32/Kconfig.rtc b/soc/espressif/esp32/Kconfig.rtc new file mode 100644 index 00000000000..bfbddc28ebb --- /dev/null +++ b/soc/espressif/esp32/Kconfig.rtc @@ -0,0 +1,77 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32 + +choice RTC_CLK_SRC + prompt "RTC clock source" + default RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + - "Internal 150kHz oscillator" option provides lowest deep sleep current + consumption, and does not require extra external components. However + frequency stability with respect to temperature is poor, so time may + drift in deep/light sleep modes. + - "External 32kHz crystal" provides better frequency stability, at the + expense of slightly higher (1uA) deep sleep current consumption. + - "External 32kHz oscillator" allows using 32kHz clock generated by an + external circuit. In this case, external clock signal must be connected + to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, + and <1V in case of square wave signal. Common mode voltage should be + 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. + Additionally, 1nF capacitor must be connected between 32K_XP pin and + ground. 32K_XP pin can not be used as a GPIO in this case. + - "Internal 8.5MHz oscillator divided by 256" option results in higher + deep sleep current (by 5uA) but has better frequency stability than + the internal 150kHz oscillator. It does not require external components. + +config RTC_CLK_SRC_INT_RC + bool "Internal 150kHz RC oscillator" + +config RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XN pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config RTC_CLK_SRC_INT_8MD256 + bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" + +endchoice # RTC_CLK_SRC + +config RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + default 1024 if RTC_CLK_SRC_INT_RC + range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + range 0 32766 if RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +config RTC_XTAL_CAL_RETRY + int "Number of attempts to repeat 32k XTAL calibration" + default 1 + depends on RTC_CLK_SRC_EXT_CRYS + help + Number of attempts to repeat 32k XTAL calibration + before giving up and switching to the internal RC. + Increase this option if the 32k crystal oscillator + does not start and switches to internal RC. + +endif # SOC_SERIES_ESP32 diff --git a/soc/espressif/esp32/default.ld b/soc/espressif/esp32/default.ld index a3577757dcd..a4210b3cc74 100644 --- a/soc/espressif/esp32/default.ld +++ b/soc/espressif/esp32/default.ld @@ -18,10 +18,10 @@ #include #define RAMABLE_REGION dram0_0_seg -#ifndef CONFIG_SOC_ENABLE_APPCPU -#define RAMABLE_REGION_1 dram0_1_seg -#else +#ifdef CONFIG_SOC_ENABLE_APPCPU #define RAMABLE_REGION_1 dram0_0_seg +#else +#define RAMABLE_REGION_1 dram0_1_seg #endif #define RODATA_REGION drom0_0_seg #define IRAM_REGION iram0_0_seg @@ -165,6 +165,7 @@ SECTIONS SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) { __rodata_region_start = ABSOLUTE(.); + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ . = ALIGN(4); #include @@ -224,6 +225,7 @@ SECTIONS { . = ALIGN(4); _image_rodata_end = ABSOLUTE(.); + _rodata_reserved_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) _image_dram_start = LOADADDR(.dram0.data); @@ -259,10 +261,38 @@ SECTIONS *libzephyr.a:log_core.*(.rodata .rodata.*) *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) *libzephyr.a:loader.*(.rodata .rodata.*) *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:cache_esp32.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_cache.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_err.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_slave_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:heap_caps_zephyr.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) KEEP(*(.jcr)) *(.dram1 .dram1.*) @@ -363,12 +393,54 @@ SECTIONS *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) *libzephyr.a:loader.*(.literal .text .literal.* .text.*) *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) *libc.a:*(.literal .text .literal.* .text.*) *libphy.a:( .phyiram .phyiram.*) *libgcov.a:(.literal .text .literal.* .text.*) + *libzephyr.a:cpu.*(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *libzephyr.a:cpu.*(.literal.esp_cpu_reset .text.esp_cpu_reset) + *libzephyr.a:cpu.*(.literal.esp_cpu_stall .text.esp_cpu_stall) + *libzephyr.a:cpu.*(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *libzephyr.a:cpu.*(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:periph_ctrl.*(.literal.periph_module_reset .text.periph_module_reset) + *libzephyr.a:periph_ctrl.*(.literal.wifi_module_disable .text.wifi_module_disable) + *libzephyr.a:periph_ctrl.*(.literal.wifi_module_enable .text.wifi_module_enable) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_wdt.*(.literal .literal.* .text .text.*) + *libzephyr.a:sar_periph_ctrl.*(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + *libzephyr.a:cache_esp32.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_system_chip.*(.literal.esp_system_abort .text.esp_system_abort) + *libzephyr.a:i2c_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:mmu_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_slave_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:wdt_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libzephyr.a:heap_caps_zephyr.*(.literal .literal.* .text .text.*) #if defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) @@ -445,11 +517,13 @@ SECTIONS *libsubsys__net__ip.a:(.noinit .noinit.*) *libsubsys__net.a:(.noinit .noinit.*) #endif + _ext_ram_bss_start = ABSOLUTE(.); + *(.ext_ram.bss*) + _ext_ram_bss_end = ABSOLUTE(.); + _spiram_heap_start = ABSOLUTE(.); . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; - *(.ext_ram.bss*) - _ext_ram_data_end = ABSOLUTE(.); } GROUP_LINK_IN(ext_ram_seg) #endif @@ -506,6 +580,7 @@ SECTIONS .flash.text : ALIGN(IROM_SEG_ALIGN) { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ _text_start = ABSOLUTE(.); #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) @@ -521,6 +596,7 @@ SECTIONS *(.literal .text .literal.* .text.*) . = ALIGN(4); _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ _etext = .; /* Similar to _iram_start, this symbol goes here so it is diff --git a/soc/espressif/esp32/esp32-mp.c b/soc/espressif/esp32/esp32-mp.c index baaae7020d6..c380df6c8b7 100644 --- a/soc/espressif/esp32/esp32-mp.c +++ b/soc/espressif/esp32/esp32-mp.c @@ -88,7 +88,7 @@ static void appcpu_entry2(void) * later. */ __asm__ volatile("rsr.PS %0" : "=r"(ps)); - ps &= ~(PS_EXCM_MASK | PS_INTLEVEL_MASK); + ps &= ~(XCHAL_PS_EXCM_MASK | XCHAL_PS_INTLEVEL_MASK); __asm__ volatile("wsr.PS %0" : : "r"(ps)); ie = 0; diff --git a/soc/espressif/esp32/loader.c b/soc/espressif/esp32/loader.c deleted file mode 100644 index 5b946bfba41..00000000000 --- a/soc/espressif/esp32/loader.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_BOOTLOADER_MCUBOOT - -#define BOOT_LOG_INF(_fmt, ...) \ - ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) - -#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) - -extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; -extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; - -void __start(void); - -static HDR_ATTR void (*_entry_point)(void) = &__start; - -static int map_rom_segments(void) -{ - int rc = 0; - size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition); - uint32_t _app_irom_start = _partition_offset + - (uint32_t)&_image_irom_start; - uint32_t _app_irom_size = (uint32_t)&_image_irom_size; - uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr; - - uint32_t _app_drom_start = _partition_offset + - (uint32_t)&_image_drom_start; - uint32_t _app_drom_size = (uint32_t)&_image_drom_size; - uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr; - - Cache_Read_Disable(0); - Cache_Flush(0); - /* Clear the MMU entries that are already set up, - * so the new app only has the mappings it creates. - */ - for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) { - DPORT_PRO_FLASH_MMU_TABLE[i] = - DPORT_FLASH_MMU_TABLE_INVALID_VAL; - } - - uint32_t drom_vaddr_addr_aligned = _app_drom_vaddr & MMU_FLASH_MASK; - uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, - _app_drom_vaddr); - rc = cache_flash_mmu_set(0, 0, drom_vaddr_addr_aligned, _app_drom_start - & MMU_FLASH_MASK, 64, drom_page_count); - rc |= cache_flash_mmu_set(1, 0, drom_vaddr_addr_aligned, _app_drom_start - & MMU_FLASH_MASK, 64, drom_page_count); - - uint32_t irom_vaddr_addr_aligned = _app_irom_vaddr & MMU_FLASH_MASK; - uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, - _app_irom_vaddr); - rc |= cache_flash_mmu_set(0, 0, irom_vaddr_addr_aligned, _app_irom_start - & MMU_FLASH_MASK, 64, irom_page_count); - rc |= cache_flash_mmu_set(1, 0, irom_vaddr_addr_aligned, _app_irom_start - & MMU_FLASH_MASK, 64, irom_page_count); - - DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, - (DPORT_PRO_CACHE_MASK_IRAM0) | - (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | - (DPORT_PRO_CACHE_MASK_IROM0 & 0) | - DPORT_PRO_CACHE_MASK_DROM0 | - DPORT_PRO_CACHE_MASK_DRAM1); - - DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, - (DPORT_APP_CACHE_MASK_IRAM0) | - (DPORT_APP_CACHE_MASK_IRAM1 & 0) | - (DPORT_APP_CACHE_MASK_IROM0 & 0) | - DPORT_APP_CACHE_MASK_DROM0 | - DPORT_APP_CACHE_MASK_DRAM1); - - esp_rom_Cache_Read_Enable(0); - - /* Show map segments continue using same log format as during MCUboot phase */ - BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map", - _app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size); - BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n", - _app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size); - esp_rom_uart_tx_wait_idle(0); - - return rc; -} -#endif - -void __start(void) -{ -#ifdef CONFIG_BOOTLOADER_MCUBOOT - int err = map_rom_segments(); - - if (err != 0) { - ets_printf("Failed to setup XIP, aborting\n"); - abort(); - } -#endif - __esp_platform_start(); -} diff --git a/soc/espressif/esp32/mcuboot.ld b/soc/espressif/esp32/mcuboot.ld index a3b2af762dd..d30e1e8c68d 100644 --- a/soc/espressif/esp32/mcuboot.ld +++ b/soc/espressif/esp32/mcuboot.ld @@ -38,7 +38,7 @@ MEMORY { iram_loader_seg (RWX) : org = 0x40078000, len = 0x4000 iram_seg (RWX) : org = 0x4009C000, len = 0x8000 - dram_seg (RW) : org = 0x3FFF0000, len = 0x6000 + dram_seg (RW) : org = 0x3FFF0000, len = 0x6400 #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -132,6 +132,8 @@ SECTIONS *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) KEEP(*(.jcr)) *(.dram1 .dram1.*) @@ -235,6 +237,11 @@ SECTIONS *libzephyr.a:app_cpu_start.*(.literal .text .literal.* .text.*) *esp_mcuboot.*(.literal .text .literal.* .text.*) *esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *(.fini.literal) *(.fini) *(.gnu.version) diff --git a/soc/espressif/esp32/soc.c b/soc/espressif/esp32/soc.c index 8e1a8ff737a..280b8da3a6e 100644 --- a/soc/espressif/esp32/soc.c +++ b/soc/espressif/esp32/soc.c @@ -11,6 +11,12 @@ #include #include #include +#include +#include +#if CONFIG_ESP_SPIRAM +#include +#include +#endif #include #include @@ -19,17 +25,16 @@ #include #include -#include "esp_private/system_internal.h" -#include "esp32/rom/cache.h" -#include "hal/soc_ll.h" -#include "soc/cpu.h" -#include "soc/gpio_periph.h" -#include "esp_spi_flash.h" -#include "esp_err.h" -#include "esp_timer.h" -#include "esp32/spiram.h" -#include "esp_app_format.h" -#include "hal/wdt_hal.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #ifndef CONFIG_SOC_ENABLE_APPCPU #include "esp_clk_internal.h" @@ -40,6 +45,11 @@ #endif /* CONFIG_MCUBOOT */ #include +#if CONFIG_ESP_SPIRAM +extern int _ext_ram_bss_start; +extern int _ext_ram_bss_end; +#endif + extern void z_cstart(void); extern void esp_reset_reason_init(void); @@ -115,7 +125,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) * initialization code wants a valid _current before * arch_kernel_init() is invoked. */ - __asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); + __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); esp_reset_reason_init(); @@ -135,7 +145,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) wdt_hal_disable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx); -#ifdef CONFIG_SOC_ESP32_APPCPU +#ifndef CONFIG_SOC_ENABLE_APPCPU /* Configures the CPU clock, RTC slow and fast clocks, and performs * RTC slow clock calibration. */ @@ -149,18 +159,34 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) esp_start_appcpu(); #endif + esp_mmu_map_init(); + +#ifdef CONFIG_SOC_FLASH_ESP32 + esp_mspi_pin_init(); + spi_flash_init_chip_state(); +#endif + #if CONFIG_ESP_SPIRAM - esp_err_t err = esp_spiram_init(); + esp_err_t err = esp_psram_init(); if (err != ESP_OK) { printk("Failed to Initialize SPIRAM, aborting.\n"); abort(); } - esp_spiram_init_cache(); - if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { + if (esp_psram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { printk("SPIRAM size is less than configured size, aborting.\n"); abort(); } + + if (esp_psram_is_initialized()) { + if (!esp_psram_extram_test()) { + printk("External RAM failed memory test!"); + abort(); + } + } + + memset(&_ext_ram_bss_start, 0, + (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); #endif /* Scheduler is not started at this point. Hence, guard functions @@ -196,71 +222,3 @@ void sys_arch_reboot(int type) { esp_restart_noos(); } - -void IRAM_ATTR esp_restart_noos(void) -{ - /* Disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - const uint32_t core_id = cpu_hal_get_core_id(); - const uint32_t other_core_id = (core_id == 0) ? 1 : 0; - - soc_ll_reset_core(other_core_id); - soc_ll_stall_core(other_core_id); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Read_Disable(0); - Cache_Read_Disable(1); - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, - DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | - DPORT_BT_RST | DPORT_BTMAC_RST | - DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | - DPORT_EMAC_RST | DPORT_MACPWR_RST | - DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); - DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - DPORT_SET_PERI_REG_MASK( - DPORT_PERIP_RST_EN_REG, - /* UART TX FIFO cannot be reset correctly on ESP32, */ - /* so reset the UART memory by DPORT here. */ - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | - DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); - DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); - - /* Clear entry point for APP CPU */ - DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0); - - /* Reset CPUs */ - if (core_id == 0) { - /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ - soc_ll_reset_core(1); - soc_ll_reset_core(0); - } else { - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - } - - while (true) { - ; - } -} diff --git a/soc/espressif/esp32/soc.h b/soc/espressif/esp32/soc.h index 473d6e750a3..e2ea8cc50b7 100644 --- a/soc/espressif/esp32/soc.h +++ b/soc/espressif/esp32/soc.h @@ -18,7 +18,7 @@ #include #include -#include +#include void __esp_platform_start(void); diff --git a/soc/espressif/esp32/soc_appcpu.c b/soc/espressif/esp32/soc_appcpu.c index a8ff116a58a..146a37087c8 100644 --- a/soc/espressif/esp32/soc_appcpu.c +++ b/soc/espressif/esp32/soc_appcpu.c @@ -20,13 +20,16 @@ #include #include -#include -#include -#include +#include +#include +#include +#include +#include +#include #include -#include +#include #include -#include +#include #include #include @@ -68,7 +71,7 @@ void __app_cpu_start(void) * initialization code wants a valid _current before * arch_kernel_init() is invoked. */ - __asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); + __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); esp_intr_initialize(); /* Start Zephyr */ @@ -88,71 +91,3 @@ void sys_arch_reboot(int type) { esp_restart_noos(); } - -void IRAM_ATTR esp_restart_noos(void) -{ - /* Disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - const uint32_t core_id = cpu_hal_get_core_id(); - const uint32_t other_core_id = (core_id == 0) ? 1 : 0; - - soc_ll_reset_core(other_core_id); - soc_ll_stall_core(other_core_id); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Read_Disable(0); - Cache_Read_Disable(1); - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, - DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | - DPORT_BT_RST | DPORT_BTMAC_RST | - DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | - DPORT_EMAC_RST | DPORT_MACPWR_RST | - DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); - DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - DPORT_SET_PERI_REG_MASK( - DPORT_PERIP_RST_EN_REG, - /* UART TX FIFO cannot be reset correctly on ESP32, */ - /* so reset the UART memory by DPORT here. */ - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | - DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); - DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); - - /* Clear entry point for APP CPU */ - DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0); - - /* Reset CPUs */ - if (core_id == 0) { - /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ - soc_ll_reset_core(1); - soc_ll_reset_core(0); - } else { - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - } - - while (true) { - ; - } -} From 072ea896d7319f63c30ba6ed93d3c7c723b74655 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 6 Mar 2024 23:50:05 -0300 Subject: [PATCH 1908/2402] soc: espressif: esp32s2: update to hal_espressif v5.1 Modify and reorganize SoC to meet updated hal. Signed-off-by: Lucas Tamborrino Signed-off-by: Sylvio Alves --- .../zephyr/dt-bindings/clock/esp32s2_clock.h | 2 +- soc/espressif/esp32s2/CMakeLists.txt | 65 ++----- soc/espressif/esp32s2/Kconfig | 144 +------------- soc/espressif/esp32s2/Kconfig.defconfig | 14 +- .../esp32s2/Kconfig.defconfig.series | 27 --- soc/espressif/esp32s2/Kconfig.mac | 42 +++++ soc/espressif/esp32s2/Kconfig.rtc | 76 ++++++++ soc/espressif/esp32s2/default.ld | 109 +++++++++-- soc/espressif/esp32s2/loader.c | 99 ---------- soc/espressif/esp32s2/mcuboot.ld | 11 +- soc/espressif/esp32s2/soc.c | 175 +++++++----------- soc/espressif/esp32s2/soc.h | 2 +- 12 files changed, 310 insertions(+), 456 deletions(-) delete mode 100644 soc/espressif/esp32s2/Kconfig.defconfig.series create mode 100644 soc/espressif/esp32s2/Kconfig.mac create mode 100644 soc/espressif/esp32s2/Kconfig.rtc delete mode 100644 soc/espressif/esp32s2/loader.c diff --git a/include/zephyr/dt-bindings/clock/esp32s2_clock.h b/include/zephyr/dt-bindings/clock/esp32s2_clock.h index c61c8b88801..aa9eb90de62 100644 --- a/include/zephyr/dt-bindings/clock/esp32s2_clock.h +++ b/include/zephyr/dt-bindings/clock/esp32s2_clock.h @@ -21,7 +21,7 @@ #define ESP32_CLK_CPU_240M 240000000 /* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_40M 0U +#define ESP32_CLK_XTAL_40M 40 /* Supported RTC fast clock frequencies */ #define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U diff --git a/soc/espressif/esp32s2/CMakeLists.txt b/soc/espressif/esp32s2/CMakeLists.txt index 1c840ce2289..e93e5711089 100644 --- a/soc/espressif/esp32s2/CMakeLists.txt +++ b/soc/espressif/esp32s2/CMakeLists.txt @@ -3,7 +3,7 @@ zephyr_sources( soc.c soc_cache.c - loader.c + ../common/loader.c ) zephyr_include_directories(.) @@ -25,52 +25,21 @@ dt_reg_addr(boot_off PATH ${dts_partition_path}) math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") + + if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") + endif() + + if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") + endif() + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") @@ -80,7 +49,7 @@ if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py ARGS --chip esp32s2 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) diff --git a/soc/espressif/esp32s2/Kconfig b/soc/espressif/esp32s2/Kconfig index 1c657c4e1b5..0efda60d23c 100644 --- a/soc/espressif/esp32s2/Kconfig +++ b/soc/espressif/esp32s2/Kconfig @@ -19,72 +19,6 @@ config IDF_TARGET_ESP32S2 bool "ESP32S2 as target SOC" default y -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - -choice ESP32S2_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32S2_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - - "Internal 90kHz oscillator" option provides lowest deep sleep current - consumption, and does not require extra external components. However - frequency stability with respect to temperature is poor, so time may - drift in deep/light sleep modes. - - "External 32kHz crystal" provides better frequency stability, at the - expense of slightly higher (1uA) deep sleep current consumption. - - "External 32kHz oscillator" allows using 32kHz clock generated by an - external circuit. In this case, external clock signal must be connected - to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, - and <1V in case of square wave signal. Common mode voltage should be - 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. - Additionally, 1nF capacitor must be connected between 32K_XP pin and - ground. 32K_XP pin can not be used as a GPIO in this case. - - "Internal 8MHz oscillator divided by 256" option results in higher - deep sleep current (by 5uA) but has better frequency stability than - the internal 90kHz oscillator. It does not require external components. - -config ESP32S2_RTC_CLK_SRC_INT_RC - bool "Internal 90kHz RC oscillator" - -config ESP32S2_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32S2_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XN pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32S2_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" - -endchoice - -config ESP32S2_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS || ESP32S2_RTC_CLK_SRC_EXT_OSC || ESP32S2_RTC_CLK_SRC_INT_8MD256 - default 576 if ESP32S2_RTC_CLK_SRC_INT_RC - range 0 125000 - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - menu "Cache config" choice @@ -111,19 +45,18 @@ choice endchoice -choice +choice ESP32S2_DATA_CACHE_SIZE prompt "Data cache size" - default ESP32S2_DATA_CACHE_0KB if !ESP_SPIRAM - default ESP32S2_DATA_CACHE_8KB if ESP_SPIRAM - + default ESP32S2_DATA_CACHE_8KB + help + Data cache size to be set on application startup. config ESP32S2_DATA_CACHE_0KB - bool "0KB data cache size" - + depends on !ESP_SPIRAM + bool "0KB" config ESP32S2_DATA_CACHE_8KB - bool "8KB data cache size" - + bool "8KB" config ESP32S2_DATA_CACHE_16KB - bool "16KB data cache size" + bool "16KB" endchoice @@ -152,67 +85,6 @@ config ESP32S2_DATA_CACHE_SIZE endmenu # Cache config -menu "PSRAM clock and cs IO for ESP32-S2" - depends on ESP_SPIRAM - -config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config - it based on hardware design. - -config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, user can config it - based on hardware design. - -endmenu # PSRAM clock and cs IO for ESP32S2 - -choice ESP32S2_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is two, - all interfaces (WiFi station, WiFi softap) receive a universally administered MAC - address. - They are generated sequentially by adding 0, and 1 (respectively) to the final octet of - the base MAC address. If the number of universal MAC addresses is one, only WiFi station - receives a universally administered MAC address. - The WiFi softap receives local MAC addresses. It's derived from the universal WiFi - station MAC addresses. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 1 or 2 per device). - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE - bool "One" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - -endchoice # ESP32S2_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES - int - default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE - default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - config ESP32_PHY_MAX_WIFI_TX_POWER int "Max WiFi TX power (dBm)" range 10 20 diff --git a/soc/espressif/esp32s2/Kconfig.defconfig b/soc/espressif/esp32s2/Kconfig.defconfig index 6daf53e76df..ec58addff67 100644 --- a/soc/espressif/esp32s2/Kconfig.defconfig +++ b/soc/espressif/esp32s2/Kconfig.defconfig @@ -3,22 +3,10 @@ if SOC_SERIES_ESP32S2 -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config ESPTOOLPY_FLASHFREQ_80M - default y - config FLASH_SIZE default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) config FLASH_BASE_ADDRESS default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) -endif # SOC_SERIES_ESP32S3 +endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/Kconfig.defconfig.series b/soc/espressif/esp32s2/Kconfig.defconfig.series deleted file mode 100644 index 50ddbd72704..00000000000 --- a/soc/espressif/esp32s2/Kconfig.defconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S2 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config MP_MAX_NUM_CPUS - default 1 - -config ISR_STACK_SIZE - default 2048 - -config ESPTOOLPY_FLASHFREQ_80M - default y - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) - -endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/Kconfig.mac b/soc/espressif/esp32s2/Kconfig.mac new file mode 100644 index 00000000000..97a5ff1d914 --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig.mac @@ -0,0 +1,42 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S2 + +choice ESP32S2_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or + derived from a single base MAC address. If the number of universal MAC addresses is two, + all interfaces (WiFi station, WiFi softap) receive a universally administered MAC + address. + They are generated sequentially by adding 0, and 1 (respectively) to the final octet of + the base MAC address. If the number of universal MAC addresses is one, only WiFi station + receives a universally administered MAC address. + The WiFi softap receives local MAC addresses. It's derived from the universal WiFi + station MAC addresses. + When using the default (Espressif-assigned) base MAC address, either setting can be used. + When using a custom universal MAC address range, the correct setting will depend on the + allocation of MAC addresses in this range (either 1 or 2 per device). + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE + bool "One" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_ONE + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + +endchoice # ESP32S2_UNIVERSAL_MAC_ADDRESSES + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES + int + default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE + default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + +endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/Kconfig.rtc b/soc/espressif/esp32s2/Kconfig.rtc new file mode 100644 index 00000000000..837ab8623e5 --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig.rtc @@ -0,0 +1,76 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S2 + +choice RTC_CLK_SRC + prompt "RTC clock source" + default RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + - "Internal 90kHz oscillator" option provides lowest deep sleep current + consumption, and does not require extra external components. However + frequency stability with respect to temperature is poor, so time may + drift in deep/light sleep modes. + - "External 32kHz crystal" provides better frequency stability, at the + expense of slightly higher (1uA) deep sleep current consumption. + - "External 32kHz oscillator" allows using 32kHz clock generated by an + external circuit. In this case, external clock signal must be connected + to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, + and <1V in case of square wave signal. Common mode voltage should be + 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. + Additionally, 1nF capacitor must be connected between 32K_XP pin and + ground. 32K_XP pin can not be used as a GPIO in this case. + - "Internal 8MHz oscillator divided by 256" option results in higher + deep sleep current (by 5uA) but has better frequency stability than + the internal 90kHz oscillator. It does not require external components. + +config RTC_CLK_SRC_INT_RC + bool "Internal 90kHz RC oscillator" + +config RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XN pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config RTC_CLK_SRC_INT_8MD256 + bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" + +endchoice + +config RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + default 576 if RTC_CLK_SRC_INT_RC + range 0 125000 + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +config RTC_XTAL_CAL_RETRY + int "Number of attempts to repeat 32k XTAL calibration" + default 3 + depends on RTC_CLK_SRC_EXT_CRYS + help + Number of attempts to repeat 32k XTAL calibration + before giving up and switching to the internal RC. + Increase this option if the 32k crystal oscillator + does not start and switches to internal RC. + +endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/default.ld b/soc/espressif/esp32s2/default.ld index 8a78bb89ac2..6c335aafa1d 100644 --- a/soc/espressif/esp32s2/default.ld +++ b/soc/espressif/esp32s2/default.ld @@ -71,7 +71,7 @@ MEMORY rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000 rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 #if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RW): org = 0x3f500000, len = CONFIG_ESP_SPIRAM_SIZE + ext_ram_seg(RW): org = 0x3f800000, len = CONFIG_ESP_SPIRAM_SIZE #endif #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -137,6 +137,7 @@ SECTIONS { _rodata_reserved_start = ABSOLUTE(.); __rodata_region_start = ABSOLUTE(.); + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ . = ALIGN(4); #include @@ -196,8 +197,9 @@ SECTIONS _rodata_reserved_end = ABSOLUTE(.); . = ALIGN(4); _image_rodata_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + _rodata_reserved_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) /* Send .iram0 code to iram */ .iram0.vectors : ALIGN(4) @@ -249,17 +251,11 @@ SECTIONS *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) *libesp32.a:panic.*(.literal .text .literal.* .text.*) *librtc.a:(.literal .text .literal.* .text.*) - *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*) - *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*) - *libsubsys__net__ip.a:(.literal .text .literal.* .text.*) - *libsubsys__net.a:(.literal .text .literal.* .text.*) *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) *libkernel.a:(.literal .text .literal.* .text.*) *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) - *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) @@ -271,12 +267,59 @@ SECTIONS *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) *libzephyr.a:loader.*(.literal .text .literal.* .text.*) *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) *libc.a:*(.literal .text .literal.* .text.*) *libphy.a:( .phyiram .phyiram.*) *libgcov.a:(.literal .text .literal.* .text.*) + *libzephyr.a:cpu.*(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *libzephyr.a:cpu.*(.literal.esp_cpu_reset .text.esp_cpu_reset) + *libzephyr.a:cpu.*(.literal.esp_cpu_stall .text.esp_cpu_stall) + *libzephyr.a:cpu.*(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *libzephyr.a:cpu.*(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:periph_ctrl.*(.literal.periph_module_reset .text.periph_module_reset) + *libzephyr.a:periph_ctrl.*(.literal.wifi_module_disable .text.wifi_module_disable) + *libzephyr.a:periph_ctrl.*(.literal.wifi_module_enable .text.wifi_module_enable) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_wdt.*(.literal .literal.* .text .text.*) + *libzephyr.a:sar_periph_ctrl.*(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_system_chip.*(.literal.esp_system_abort .text.esp_system_abort) + *libzephyr.a:cache_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:i2c_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:mmu_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_slave_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:systimer_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:wdt_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) #if defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) @@ -329,11 +372,18 @@ SECTIONS } GROUP_LINK_IN(RAMABLE_REGION) #if defined(CONFIG_ESP_SPIRAM) - .ext_ram.bss (NOLOAD): + /* This section holds .ext_ram.bss data, and will be put in PSRAM */ + .ext_ram.bss (NOLOAD) : { _ext_ram_data_start = ABSOLUTE(.); _ext_ram_bss_start = ABSOLUTE(.); + *(.ext_ram.bss*) + . = ALIGN(4); + _ext_ram_bss_end = ABSOLUTE(.); + } > ext_ram_seg + .ext_ram_noinit (NOLOAD) : + { #if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) *libdrivers__wifi.a:(.noinit .noinit.*) *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) @@ -344,10 +394,6 @@ SECTIONS _spiram_heap_start = ABSOLUTE(.); . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; - *(.ext_ram.bss*) - . = ALIGN(4); - _ext_ram_bss_end = ABSOLUTE(.); - _ext_ram_data_end = ABSOLUTE(.); } > ext_ram_seg #endif @@ -384,10 +430,41 @@ SECTIONS *libzephyr.a:log_core.*(.rodata .rodata.*) *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) *libzephyr.a:loader.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) - *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:systimer.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_cache.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_err.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:cache_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_slave_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) KEEP(*(.jcr)) *(.dram1 .dram1.*) @@ -436,6 +513,7 @@ SECTIONS { . = ALIGN(8); _stext = .; + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ _text_start = ABSOLUTE(.); #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) @@ -453,6 +531,7 @@ SECTIONS *(.literal .text .literal.* .text.*) . = ALIGN(8); _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); _etext = .; /* Similar to _iram_start, this symbol goes here so it is diff --git a/soc/espressif/esp32s2/loader.c b/soc/espressif/esp32s2/loader.c deleted file mode 100644 index 53eda01310b..00000000000 --- a/soc/espressif/esp32s2/loader.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -#include -#include "soc/cache_memory.h" -#include "soc/extmem_reg.h" -#include - -#ifdef CONFIG_BOOTLOADER_MCUBOOT - -#define BOOT_LOG_INF(_fmt, ...) \ - ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) - -#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) - -extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; -extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; - -void __start(void); - -static HDR_ATTR void (*_entry_point)(void) = &__start; - -static int map_rom_segments(void) -{ - int rc = 0; - - size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition); - uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start; - uint32_t _app_irom_size = (uint32_t)&_image_irom_size; - uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr; - - uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start; - uint32_t _app_drom_size = (uint32_t)&_image_drom_size; - uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr; - - uint32_t autoload = esp_rom_Cache_Suspend_ICache(); - - esp_rom_Cache_Invalidate_ICache_All(); - - /* Clear the MMU entries that are already set up, - * so the new app only has the mappings it creates. - */ - for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) { - FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL; - } - - uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr); - - rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, _app_drom_vaddr & 0xffff0000, - _app_drom_start & 0xffff0000, 64, drom_page_count, 0); - - uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr); - - if (_app_irom_vaddr + _app_irom_size > IRAM1_ADDRESS_LOW) { - rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64, 64, 1); - rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1); - REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1); - } - - rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, _app_irom_vaddr & 0xffff0000, - _app_irom_start & 0xffff0000, 64, irom_page_count, 0); - - REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, (EXTMEM_PRO_ICACHE_MASK_IRAM0) | - (EXTMEM_PRO_ICACHE_MASK_IRAM1 & 0) | EXTMEM_PRO_ICACHE_MASK_DROM0); - - esp_rom_Cache_Resume_ICache(autoload); - - /* Show map segments continue using same log format as during MCUboot phase */ - BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map", - _app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size); - BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n", - _app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size); - esp_rom_uart_tx_wait_idle(0); - - return rc; -} -#endif - -void __start(void) -{ -#ifdef CONFIG_BOOTLOADER_MCUBOOT - int err = map_rom_segments(); - - if (err != 0) { - ets_printf("Failed to setup XIP, aborting\n"); - abort(); - } -#endif - __esp_platform_start(); -} diff --git a/soc/espressif/esp32s2/mcuboot.ld b/soc/espressif/esp32s2/mcuboot.ld index 6d52100db75..17a975ee363 100644 --- a/soc/espressif/esp32s2/mcuboot.ld +++ b/soc/espressif/esp32s2/mcuboot.ld @@ -36,8 +36,8 @@ MEMORY { - iram_seg (RWX) : org = 0x40040000, len = 0x6000 - iram_loader_seg (RWX) : org = 0x40046000, len = 0x2000 + iram_seg (RWX) : org = 0x40040000, len = 0x7000 + iram_loader_seg (RWX) : org = 0x40047000, len = 0x3000 dram_seg (RW) : org = 0x3FFE6000, len = 0x6000 #ifdef CONFIG_GEN_ISR_TABLES @@ -136,7 +136,8 @@ SECTIONS *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) - + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) KEEP(*(.jcr)) *(.dram1 .dram1.*) . = ALIGN(4); @@ -237,6 +238,10 @@ SECTIONS *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) *esp_mcuboot.*(.literal .text .literal.* .text.*) *esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) *(.fini.literal) *(.fini) *(.gnu.version) diff --git a/soc/espressif/esp32s2/soc.c b/soc/espressif/esp32s2/soc.c index 5e1ec21c075..0ff49920737 100644 --- a/soc/espressif/esp32s2/soc.c +++ b/soc/espressif/esp32s2/soc.c @@ -11,6 +11,13 @@ #include #include #include +#include +#include +#include +#if CONFIG_ESP_SPIRAM +#include +#include +#endif #include #include @@ -18,18 +25,16 @@ #include #include -#include "esp_private/system_internal.h" -#include "esp32s2/rom/cache.h" -#include "soc/gpio_periph.h" -#include "esp_spi_flash.h" -#include "esp_cpu.h" -#include "hal/cpu_ll.h" -#include "hal/soc_ll.h" -#include "hal/wdt_hal.h" -#include "esp_timer.h" -#include "esp_err.h" -#include "esp32s2/spiram.h" -#include "esp_clk_internal.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include #ifdef CONFIG_MCUBOOT @@ -54,43 +59,19 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) extern uint32_t _init_start; /* Move the exception vector table to IRAM. */ - __asm__ __volatile__ ( - "wsr %0, vecbase" - : - : "r"(&_init_start)); + __asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start)); /* Zero out BSS */ z_bss_zero(); - /* - * Configure the mode of instruction cache : - * cache size, cache associated ways, cache line size. - */ - esp_config_instruction_cache_mode(); - - /* - * If we need use SPIRAM, we should use data cache, or if we want to - * access rodata, we also should use data cache. - * Configure the mode of data : cache size, cache associated ways, cache - * line size. - * Enable data cache, so if we don't use SPIRAM, it just works. - */ -#if CONFIG_ESP_SPIRAM - esp_config_data_cache_mode(); - esp_rom_Cache_Enable_DCache(0); -#endif - /* Disable normal interrupts. */ - __asm__ __volatile__ ( - "wsr %0, PS" - : - : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); + __asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); /* Initialize the architecture CPU pointer. Some of the * initialization code wants a valid _current before * arch_kernel_init() is invoked. */ - __asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); + __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); esp_reset_reason_init(); @@ -110,42 +91,67 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) wdt_hal_disable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx); - /* Configures the CPU clock, RTC slow and fast clocks, and performs - * RTC slow clock calibration. + /* + * Configure the mode of instruction cache : + * cache size, cache associated ways, cache line size. */ - esp_clk_init(); + esp_config_instruction_cache_mode(); - esp_timer_early_init(); + /* + * If we need use SPIRAM, we should use data cache, or if we want to + * access rodata, we also should use data cache. + * Configure the mode of data : cache size, cache associated ways, cache + * line size. + * Enable data cache, so if we don't use SPIRAM, it just works. + */ + esp_config_data_cache_mode(); + esp_rom_Cache_Enable_DCache(0); -#if CONFIG_ESP_SPIRAM +#ifdef CONFIG_SOC_FLASH_ESP32 + esp_mspi_pin_init(); + spi_flash_init_chip_state(); +#endif /*CONFIG_SOC_FLASH_ESP32*/ - memset(&_ext_ram_bss_start, - 0, - (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); + esp_mmu_map_init(); - esp_err_t err = esp_spiram_init(); +#if CONFIG_ESP_SPIRAM + esp_err_t err = esp_psram_init(); if (err != ESP_OK) { printk("Failed to Initialize SPIRAM, aborting.\n"); abort(); } - esp_spiram_init_cache(); - if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { + if (esp_psram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { printk("SPIRAM size is less than configured size, aborting.\n"); abort(); } + if (esp_psram_is_initialized()) { + if (!esp_psram_extram_test()) { + printk("External RAM failed memory test!"); + abort(); + } + } + + memset(&_ext_ram_bss_start, 0, + (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); + #endif /* CONFIG_ESP_SPIRAM */ -/* Scheduler is not started at this point. Hence, guard functions - * must be initialized after esp_spiram_init_cache which internally - * uses guard functions. Setting guard functions before SPIRAM - * cache initialization will result in a crash. - */ + /* Configures the CPU clock, RTC slow and fast clocks, and performs + * RTC slow clock calibration. + */ + esp_clk_init(); + esp_timer_early_init(); + + /* Scheduler is not started at this point. Hence, guard functions + * must be initialized after esp_spiram_init_cache which internally + * uses guard functions. Setting guard functions before SPIRAM + * cache initialization will result in a crash. + */ #if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM spi_flash_guard_set(&g_flash_guard_default_ops); #endif - #endif /* CONFIG_MCUBOOT */ esp_intr_initialize(); @@ -169,60 +175,3 @@ void sys_arch_reboot(int type) { esp_restart_noos(); } - -void IRAM_ATTR esp_restart_noos(void) -{ - /* Disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - /* - * Reset and stall the other CPU. - * CPU must be reset before stalling, in case it was running a s32c1i - * instruction. This would cause memory pool to be locked by arbiter - * to the stalled CPU, preventing current CPU from accessing this pool. - */ - const uint32_t core_id = cpu_ll_get_core_id(); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - /* Disable cache */ - esp_rom_Cache_Disable_ICache(); - esp_rom_Cache_Disable_DCache(); - - /* - * 2nd stage bootloader reconfigures SPI flash signals. - * Reset them to the defaults expected by ROM - */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/ethernet/sdio (bb/mac) */ - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, - DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | DPORT_BT_RST | - DPORT_BTMAC_RST | DPORT_SDIO_RST | DPORT_SDIO_RST | - DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | - DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); - DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - DPORT_SET_PERI_REG_MASK( - DPORT_PERIP_RST_EN_REG, - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | - DPORT_SPI3_RST | DPORT_SPI2_DMA_RST | DPORT_SPI3_DMA_RST | - DPORT_UART_RST); - DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); - - /* Reset CPUs */ - if (core_id == 0) { - soc_ll_reset_core(0); - } - - while (true) { - ; - } -} diff --git a/soc/espressif/esp32s2/soc.h b/soc/espressif/esp32s2/soc.h index f7246ed6a2d..2edd0d12cc9 100644 --- a/soc/espressif/esp32s2/soc.h +++ b/soc/espressif/esp32s2/soc.h @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include From 561f31bb5494dc40a7a49d7d9fb814dd1e2ea442 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 6 Mar 2024 23:50:55 -0300 Subject: [PATCH 1909/2402] soc: espressif: esp32s3: update to hal_espressif v5.1 Modify and reorganize SoC to meet updated hal. Signed-off-by: Sylvio Alves Signed-off-by: Lucas Tamborrino --- .../espressif/esp32s3/esp32s3_common.dtsi | 16 + .../zephyr/dt-bindings/clock/esp32s3_clock.h | 6 +- soc/espressif/esp32s3/CMakeLists.txt | 71 +- soc/espressif/esp32s3/Kconfig | 110 +-- soc/espressif/esp32s3/Kconfig.defconfig | 12 - soc/espressif/esp32s3/Kconfig.mac | 47 ++ soc/espressif/esp32s3/Kconfig.rtc | 46 ++ soc/espressif/esp32s3/default.ld | 725 +++++++++++------- soc/espressif/esp32s3/esp32s3-mp.c | 4 +- soc/espressif/esp32s3/loader.c | 98 --- soc/espressif/esp32s3/mcuboot.ld | 65 +- soc/espressif/esp32s3/power.c | 46 ++ soc/espressif/esp32s3/poweroff.c | 15 + soc/espressif/esp32s3/soc.c | 164 +--- soc/espressif/esp32s3/soc.h | 11 +- soc/espressif/esp32s3/soc_appcpu.c | 90 +-- soc/espressif/esp32s3/soc_cache.c | 46 +- 17 files changed, 766 insertions(+), 806 deletions(-) create mode 100644 soc/espressif/esp32s3/Kconfig.mac create mode 100644 soc/espressif/esp32s3/Kconfig.rtc delete mode 100644 soc/espressif/esp32s3/loader.c create mode 100644 soc/espressif/esp32s3/power.c create mode 100644 soc/espressif/esp32s3/poweroff.c diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi index a879187cbd4..b02d38410ad 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi @@ -32,6 +32,7 @@ device_type = "cpu"; compatible = "cdns,tensilica-xtensa-lx7"; reg = <0>; + cpu-power-states = <&light_sleep &deep_sleep>; }; cpu1: cpu@1 { @@ -40,6 +41,21 @@ reg = <1>; }; + power-states { + light_sleep: light_sleep { + compatible = "zephyr,power-state"; + power-state-name = "standby"; + min-residency-us = <200>; + exit-latency-us = <133>; + }; + + deep_sleep: deep_sleep { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + min-residency-us = <2000>; + exit-latency-us = <382>; + }; + }; }; wifi: wifi { diff --git a/include/zephyr/dt-bindings/clock/esp32s3_clock.h b/include/zephyr/dt-bindings/clock/esp32s3_clock.h index 817aee45890..68980d0c8bf 100644 --- a/include/zephyr/dt-bindings/clock/esp32s3_clock.h +++ b/include/zephyr/dt-bindings/clock/esp32s3_clock.h @@ -21,10 +21,8 @@ #define ESP32_CLK_CPU_240M 240000000 /* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_24M 0U -#define ESP32_CLK_XTAL_26M 1U -#define ESP32_CLK_XTAL_40M 2U -#define ESP32_CLK_XTAL_AUTO 3U +#define ESP32_CLK_XTAL_32M 32 +#define ESP32_CLK_XTAL_40M 40 /* Supported RTC fast clock frequencies */ #define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U diff --git a/soc/espressif/esp32s3/CMakeLists.txt b/soc/espressif/esp32s3/CMakeLists.txt index 75b9f0a3d7e..0a261dbe1e0 100644 --- a/soc/espressif/esp32s3/CMakeLists.txt +++ b/soc/espressif/esp32s3/CMakeLists.txt @@ -1,13 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_ESP32S3_APPCPU) +if (CONFIG_SOC_ESP32S3_APPCPU) zephyr_sources(soc_appcpu.c) else() zephyr_sources( soc.c soc_cache.c - loader.c esp32s3-mp.c + ../common/loader.c ) endif() @@ -15,65 +15,39 @@ zephyr_include_directories(.) zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) +# Power Management +zephyr_library_sources_ifdef(CONFIG_PM power.c) +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + # get flash size to use in esptool as string math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) + set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) + if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") + endif() - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") + endif() + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") endif() if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py ARGS --chip esp32s3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) @@ -82,10 +56,12 @@ if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) if(CONFIG_MCUBOOT) board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") endif() + endif() ## When building for APPCPU -if(CONFIG_SOC_ESP32S3_APPCPU) +if (CONFIG_SOC_ESP32S3_APPCPU) + if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py @@ -93,7 +69,9 @@ if(CONFIG_SOC_ESP32S3_APPCPU) -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c -a "esp32s3_appcpu_fw_array") endif() + else() + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) # get code-partition slot0 address @@ -107,6 +85,7 @@ else() board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + endif() if(CONFIG_MCUBOOT) diff --git a/soc/espressif/esp32s3/Kconfig b/soc/espressif/esp32s3/Kconfig index 33489ad6dc9..9862a1db0a4 100644 --- a/soc/espressif/esp32s3/Kconfig +++ b/soc/espressif/esp32s3/Kconfig @@ -10,6 +10,8 @@ config SOC_SERIES_ESP32S3 select XIP if !MCUBOOT select HAS_ESPRESSIF_HAL select CPU_HAS_FPU + select HAS_PM + select HAS_POWEROFF if SOC_SERIES_ESP32S3 @@ -38,95 +40,6 @@ config SOC_ENABLE_APPCPU help This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled. -choice ESP32S3_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32S3_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - config ESP32S3_RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - config ESP32S3_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - config ESP32S3_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XP pin" - select ESP_SYSTEM_RTC_EXT_OSC - config ESP32S3_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" -endchoice - -config ESP32S3_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32S3_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32S3_RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -choice ESP32_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is four, - all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally - administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) - to the final octet of the base MAC address. If the number of universal MAC addresses is two, - only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. - These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. - The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. - These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 2 or 4 per device.) - -config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_BT - -config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - bool "Four" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - select ESP_MAC_ADDR_UNIVERSE_BT - select ESP_MAC_ADDR_UNIVERSE_ETH - -endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP_MAC_ADDR_UNIVERSE_BT - bool - -config ESP_MAC_ADDR_UNIVERSE_ETH - bool - -config ESP32_UNIVERSAL_MAC_ADDRESSES - int - default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - config ESP32_PHY_MAX_WIFI_TX_POWER int "Max WiFi/BLE TX power (dBm)" range 10 20 @@ -281,23 +194,4 @@ config MAC_BB_PD endmenu # Cache config -menu "PSRAM Clock and CS IO for ESP32S3" - depends on ESP_SPIRAM - -config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design. - -config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, please refer to your hardware design. - -endmenu # PSRAM clock and cs IO for ESP32S3 - endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/Kconfig.defconfig b/soc/espressif/esp32s3/Kconfig.defconfig index 07f719a0bcc..2d61a5cfa4b 100644 --- a/soc/espressif/esp32s3/Kconfig.defconfig +++ b/soc/espressif/esp32s3/Kconfig.defconfig @@ -3,18 +3,6 @@ if SOC_SERIES_ESP32S3 -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config ESPTOOLPY_FLASHFREQ_80M - default y - config FLASH_SIZE default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) diff --git a/soc/espressif/esp32s3/Kconfig.mac b/soc/espressif/esp32s3/Kconfig.mac new file mode 100644 index 00000000000..5d51e8773b2 --- /dev/null +++ b/soc/espressif/esp32s3/Kconfig.mac @@ -0,0 +1,47 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S3 + +choice ESP32S3_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or derived from a + single base MAC address. + If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap, + Bluetooth and Ethernet) receive a universally administered MAC address. These are generated + sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address. + If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth) + receive a universally administered MAC address. These are generated sequentially by adding 0 + and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet) + receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC + addresses, respectively. + When using the default (Espressif-assigned) base MAC address, either setting can be used. When using + a custom universal MAC address range, the correct setting will depend on the allocation of MAC + addresses in this range (either 2 or 4 per device.)ll depend on the + allocation of MAC addresses in this range (either 1 or 2 per device). + +config ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_BT + +config ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR + bool "Four" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + select ESP_MAC_ADDR_UNIVERSE_BT + select ESP_MAC_ADDR_UNIVERSE_ETH + +endchoice # ESP32S3_UNIVERSAL_MAC_ADDRESSES + +config ESP32S3_UNIVERSAL_MAC_ADDRESSES + int + default 2 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR + +endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/Kconfig.rtc b/soc/espressif/esp32s3/Kconfig.rtc new file mode 100644 index 00000000000..526d4b909c9 --- /dev/null +++ b/soc/espressif/esp32s3/Kconfig.rtc @@ -0,0 +1,46 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S3 + +choice RTC_CLK_SRC + prompt "RTC clock source" + default RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + config RTC_CLK_SRC_INT_RC + bool "Internal 136kHz RC oscillator" + config RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + config RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XP pin" + select ESP_SYSTEM_RTC_EXT_OSC + config RTC_CLK_SRC_INT_8MD256 + bool "Internal 17.5MHz oscillator, divided by 256" +endchoice + +config RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + default 1024 if RTC_CLK_SRC_INT_RC + range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + range 0 32766 if RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/default.ld b/soc/espressif/esp32s3/default.ld index 7c8aff31767..3a9aa37794d 100644 --- a/soc/espressif/esp32s3/default.ld +++ b/soc/espressif/esp32s3/default.ld @@ -30,7 +30,6 @@ #define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) #define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) -#define DCACHE_SIZE 0x10000 #define SRAM_DRAM_ORG (SRAM_DRAM_START) #define DRAM0_0_SEG_LEN I_D_SRAM_SIZE @@ -41,8 +40,6 @@ #define RAMABLE_REGION dram0_0_seg #define ROMABLE_REGION ROM -#define EXT_RAM_ORG (0x3E000000 - CONFIG_ESP_SPIRAM_SIZE) - #ifdef CONFIG_FLASH_SIZE #define FLASH_SIZE CONFIG_FLASH_SIZE #else @@ -52,9 +49,12 @@ #ifdef CONFIG_BOOTLOADER_ESP_IDF #define IROM_SEG_ORG 0x42000020 #define IROM_SEG_LEN FLASH_SIZE-0x20 +#define IROM_SEG_ALIGN 0x10 #else #define IROM_SEG_ORG 0x42000000 #define IROM_SEG_LEN FLASH_SIZE +/* MCUBoot requires MMU page size alignment */ +#define IROM_SEG_ALIGN 0x10000 #endif #ifdef CONFIG_SOC_ENABLE_APPCPU @@ -65,8 +65,6 @@ #define APPCPU_DRAM_SIZE 0x0 #endif -#define IROM_SEG_ALIGN 0x10000 - /* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. * Executing directly from LMA is not possible. */ #undef GROUP_ROM_LINK_IN @@ -82,18 +80,18 @@ MEMORY irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - /* DROM is the first segment placed in generated binary. - * MCUboot binary for ESP32 has image header of 0x20 bytes. + /* MCUboot binary for ESP32 has image header of 0x20 bytes. * Additional load header of 0x20 bytes are appended to the image. * Hence, an offset of 0x40 is added to DROM segment origin. */ drom0_0_seg(R): org = 0x3C000040, len = FLASH_SIZE - 0x40 + /** - * `extern_ram_seg` and `drom0_0_seg` share the same bus and the address region. - * so we allocate `extern_ram_seg` at the end of the address region. + * `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region. + * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in` */ #if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RWX): org = EXT_RAM_ORG, len = CONFIG_ESP_SPIRAM_SIZE + ext_ram_seg(RWX): org = 0x3C000040, len = CONFIG_ESP_SPIRAM_SIZE - 0x40 #endif /* RTC fast memory (executable). Persists over deep sleep. @@ -113,6 +111,8 @@ MEMORY #endif } +_esp_mmu_block_size = (CONFIG_MMU_PAGE_SIZE); + /* Default entry point: */ ENTRY(CONFIG_KERNEL_ENTRY) @@ -155,112 +155,85 @@ SECTIONS #include - _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); - _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; - _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); + /* RTC fast memory holds RTC wake stub code */ + .rtc.text : + { + . = ALIGN(4); + _rtc_fast_start = ABSOLUTE(.); + _rtc_text_start = ABSOLUTE(.); + *(.rtc.literal .rtc.text) + *(.rtc.entry.text) + _rtc_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - /* NOTE: .rodata section should be the first section in the linker script and no - * other section should appear before .rodata section. This is the requirement - * to align ROM section to 64K page offset. - * Adding .rodata as first section helps to reduce size of generated binary by - * few kBs. + /* This section located in RTC FAST Memory area. + * It holds data marked with RTC_FAST_ATTR attribute. + * See the file "esp_attr.h" for more information. */ - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(0x10)) + .rtc.force_fast : { - _rodata_reserved_start = ABSOLUTE(.); - _rodata_start = ABSOLUTE(.); - - *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - - __rodata_region_start = ABSOLUTE(.); . = ALIGN(4); - #include + _rtc_force_fast_start = ABSOLUTE(.); - . = ALIGN(4); - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata) - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata.*) + *(.rtc.force_fast .rtc.force_fast.*) + . = ALIGN(4) ; + _rtc_force_fast_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; + /* RTC data section holds data marked with + * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + *(.rtc.data) + *(.rtc.rodata) + _rtc_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); - __rodata_region_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - *(.rodata_wlog) - *(.rodata_wlog*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); - #include - #include - #include - #include - #include - #include - #include - #include - #include + *(.rtc.data) + *(.rtc.rodata) - /* Create an explicit section at the end of all the data that shall be mapped into drom. - * This is used to calculate the size of the _image_drom_size variable */ - SECTION_PROLOGUE(_RODATA_SECTION_END,,ALIGN(0x10)) - { - _rodata_reserved_end = ABSOLUTE(.); - . = ALIGN(16); - _image_rodata_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + _rtc_bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(rtc_slow_seg) -#if defined(CONFIG_ESP_SPIRAM) - /* This section holds .ext_ram.bss data, and will be put in PSRAM */ - .ext_ram.bss (NOLOAD) : + /* This section holds data that should not be initialized at power up + * and will be retained during deep sleep. + * User data marked with RTC_NOINIT_ATTR will be placed + * into this section. See the file "esp_attr.h" for more information. + */ + .rtc_noinit (NOLOAD): { - _ext_ram_data_start = ABSOLUTE(.); - _ext_ram_bss_start = ABSOLUTE(.); - *(.ext_ram.bss*) . = ALIGN(4); - _ext_ram_bss_end = ABSOLUTE(.); - } > ext_ram_seg + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } GROUP_LINK_IN(rtc_slow_seg) - .ext_ram_noinit (NOLOAD) : + /* This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : { -#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) - *libdrivers__wifi.a:(.noinit .noinit.*) - *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) - *libsubsys__net__lib__config.a:(.noinit .noinit.*) - *libsubsys__net__ip.a:(.noinit .noinit.*) - *libsubsys__net.a:(.noinit .noinit.*) -#endif - _spiram_heap_start = ABSOLUTE(.); - . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - _ext_ram_data_end = ABSOLUTE(.); - } > ext_ram_seg -#endif + /* Get size of rtc slow data based on rtc_data_location alias */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + _rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start); + + ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") + ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") /* Send .iram0 code to iram */ .iram0.vectors : ALIGN(4) @@ -308,21 +281,14 @@ SECTIONS _iram_text_start = ABSOLUTE(.); *(.iram1 .iram1.*) *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - *libesp32.a:panic.*(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) *libkernel.a:(.literal .text .literal.* .text.*) - *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) - *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) - *libzephyr.a:spiram*.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_timing*.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_flash*.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_packaged.*(.literal .text .literal.* .text.*) *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) - *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) @@ -331,16 +297,107 @@ SECTIONS *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_minimal.*(.literal .literal.* .text .text.*) *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_mmu_map.*(.literal .literal.* .text .text.*) + *libdrivers__interrupt_controller.a:(.literal .literal.* .text .text.*) *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) - *libc.a:*(.literal .text .literal.* .text.*) + *liblib__libc__picolibc.a:string.*(.literal .text .literal.* .text.*) *libphy.a:(.phyiram .phyiram.*) *libgcov.a:(.literal .text .literal.* .text.*) + /* [mapping:esp_psram] */ + *libzephyr.a:mmu_psram_flash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_psram_impl_quad.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_psram_impl_octal.*(.literal .literal.* .text .text.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:i2c_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.literal .text .literal.* .text.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.literal .literal.* .text .text.*) + + /* [mapping:log] */ + *(.literal.esp_log_write .text.esp_log_write) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_log_impl_lock .text.esp_log_impl_lock) + *(.literal.esp_log_impl_lock_timeout .text.esp_log_impl_lock_timeout) + *(.literal.esp_log_impl_unlock .text.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hpm_enable.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_oct_flash_init*(.literal .literal.* .text .text.*) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *(.literal.esp_system_abort .text.esp_system_abort) + + /* [mapping:esp_hw_support] */ + *(.literal.esp_cpu_stall .text.esp_cpu_stall) + *(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *(.literal.esp_cpu_reset .text.esp_cpu_reset) + *(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *(.literal.rtc_vddsdio_get_config .text.rtc_vddsdio_get_config) + *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*) + *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + + /* [mapping:soc_pm] */ + *(.literal.GPIO_HOLD_MASK .text.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_cache_writeback_esp32s3.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) + #if defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) + *libnet80211.a:(.wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:(.wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) + *libcoexist.a:(.wifi_slp_iram .wifi_slp_iram.*) + + /* [mapping:esp_wifi] */ + *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper) + *(.literal.wifi_clock_disable_wrapper .text.wifi_clock_disable_wrapper) + + /* [mapping:esp_phy] */ + *(.literal.esp_phy_enable .text.esp_phy_enable) + *(.literal.esp_phy_disable .text.esp_phy_disable) + *(.literal.esp_wifi_bt_power_domain_off .text.esp_wifi_bt_power_domain_off) #endif #if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) @@ -352,81 +409,25 @@ SECTIONS } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - /* Marks the end of IRAM code segment */ - .iram0.text_end (NOLOAD) : - { - /* ESP32-S3 memprot requires 16B padding for possible CPU - * prefetch and 256B alignment for PMS split lines */ - . = ALIGN(16); - _iram_text_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - .iram0.data : - { - . = ALIGN(16); - *(.iram.data) - *(.iram.data*) - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram0.bss (NOLOAD) : - { - . = ALIGN(16); - *(.iram.bss) - *(.iram.bss*) - - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - - /* This section is required to skip .iram0.text area because iram0_0_seg and + /** + * This section is required to skip .iram0.text area because iram0_0_seg and * dram0_0_seg reflect the same address space on different buses. */ .dram0.dummy (NOLOAD): { - . = ALIGN (8); . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM_DIRAM_I_START) - SRAM_DIRAM_I_START; } GROUP_LINK_IN(RAMABLE_REGION) - /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); /* required by bluetooth library */ - __bss_start = ABSOLUTE(.); - - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - __bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) - - ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") - - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN(8); - *(.noinit) - *(.noinit.*) - . = ALIGN(8) ; - } GROUP_LINK_IN(RAMABLE_REGION) - .dram0.data : { . = ALIGN (8); __data_start = ABSOLUTE(.); + _image_ram_start = ABSOLUTE(.); + /* bluetooth library requires this symbol to be defined */ + _btdm_data_start = ABSOLUTE(.); + *libbtdm_app.a:(.data .data.*) + . = ALIGN (4); + _btdm_data_end = ABSOLUTE(.); *(.data) *(.data.*) @@ -438,20 +439,111 @@ SECTIONS *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) + *(.srodata) + *(.srodata.*) /* rodata for panic handler(libarch__xtensa__core.a) and all * dependent functions should be placed in DRAM to avoid issue * when flash cache is disabled */ *libarch__xtensa__core.a:(.rodata .rodata.*) *libkernel.a:fatal.*(.rodata .rodata.*) *libkernel.a:init.*(.rodata .rodata.*) - *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) - *libzephyr.a:systimer_hal.*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete.*(.rodata .rodata.*) *libzephyr.a:log_core.*(.rodata .rodata.*) *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:log_minimal.*(.rodata .rodata.*) *libzephyr.a:loader.*(.rodata .rodata.*) *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libzephyr.a:esp_mmu_map.*(.rodata .rodata.*) + *libdrivers__interrupt_controller.a:(.rodata .rodata.*) + + /* [mapping:esp_psram] */ + *libzephyr.a:mmu_psram_flash.*(.rodata .rodata.*) + *libzephyr.a:esp_psram_impl_octal.*(.rodata .rodata.*) + *libzephyr.a:esp_psram_impl_quad.*(.rodata .rodata.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:cache_hal.*(.rodata .rodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.rodata .rodata.*) + + /* [mapping:log] */ + *(.rodata.esp_log_write) + *(.rodata.esp_log_timestamp) + *(.rodata.esp_log_early_timestamp) + *(.rodata.esp_log_impl_lock) + *(.rodata.esp_log_impl_lock_timeout) + *(.rodata.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hpm_enable.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_oct_flash_init.*(.rodata .rodata.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.rodata .rodata.*) + + /* [mapping:esp_hw_support] */ + *(.rodata.esp_cpu_stall) + *(.rodata.esp_cpu_unstall) + *(.rodata.esp_cpu_reset) + *(.rodata.esp_cpu_wait_for_intr) + *(.rodata.esp_cpu_compare_and_set) + *(.rodata.esp_gpio_reserve_pins) + *(.rodata.esp_gpio_is_pin_reserved) + *(.rodata.rtc_vddsdio_get_config) + *(.rodata.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + *libzephyr.a:systimer.*(.rodata .rodata.*) + *libzephyr.a:mspi_timing_config.*(.rodata .rodata.*) + *libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.*) + *(.rodata.sar_periph_ctrl_power_enable) + + /* [mapping:soc_pm] */ + *(.rodata.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_cache_writeback_esp32s3.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_wdt.*(.rodata .rodata.*) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.rodata .rodata.*) + *(.rodata.esp_system_abort) + +#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) + /* [mapping:esp_wifi] */ + *(.rodata.wifi_clock_enable_wrapper) + *(.rodata.wifi_clock_disable_wrapper) + + /* [mapping:esp_phy] */ + *(.rodata.esp_phy_enable) + *(.rodata.esp_phy_disable) + *(.rodata.esp_wifi_bt_power_domain_off) +#endif KEEP(*(.jcr)) *(.dram1 .dram1.*) @@ -463,6 +555,7 @@ SECTIONS #include #include #include + #include /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ #pragma push_macro("GROUP_ROM_LINK_IN") @@ -474,32 +567,68 @@ SECTIONS .dram0.end : { . = ALIGN(4); - #include - . = ALIGN(4); - _end = ABSOLUTE(.); __data_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + *(.noinit.*) + . = ALIGN(4) ; + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); /* required by bluetooth library */ + __bss_start = ABSOLUTE(.); + + /* bluetooth library requires this symbol to be defined */ + _btdm_bss_start = ABSOLUTE(.); + *libbtdm_app.a:(.bss .bss.* COMMON) + . = ALIGN (4); + _btdm_bss_end = ABSOLUTE(.); + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + __bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + +#include + + ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + _image_irom_start = LOADADDR(.flash.text); _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; _image_irom_vaddr = ADDR(.flash.text); - .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN) - { - . = SIZEOF(_RODATA_SECTION_NAME); - . = ALIGN(IROM_SEG_ALIGN) + 0x20; - } GROUP_LINK_IN(FLASH_CODE_REGION) - .flash.text : ALIGN(IROM_SEG_ALIGN) { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); _text_start = ABSOLUTE(.); #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) + #endif #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) @@ -522,6 +651,7 @@ SECTIONS . += 16; _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ _etext = .; /* Similar to _iram_start, this symbol goes here so it is @@ -531,114 +661,154 @@ SECTIONS _flash_cache_start = ABSOLUTE(0); } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - /* RTC fast memory holds RTC wake stub code, - * including from any source file named rtc_wake_stub*.c + /** + * This dummy section represents the .flash.text section but in default_rodata_seg. + * Thus, it must have its alignment and (at least) its size. */ - .rtc.text : - { + .flash_rodata_dummy (NOLOAD): + { + _flash_rodata_dummy_start = ABSOLUTE(.); + /* Start at the same alignment constraint than .flash.text */ + . = ALIGN(ALIGNOF(.flash.text)); + /* Create an empty gap as big as .flash.text section */ + . = . + SIZEOF(.flash.text); + /* Prepare the alignment of the section above. Few bytes (0x20) must be + * added for the mapping header. */ + . = ALIGN(_esp_mmu_block_size) + 0x40; + } GROUP_LINK_IN(RODATA_REGION) + + _image_drom_start = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata_end) + SIZEOF(.flash.rodata_end) - _image_drom_start; + _image_drom_vaddr = ADDR(.flash.rodata); + + .flash.rodata : ALIGN(IROM_SEG_ALIGN) + { + _flash_rodata_start = ABSOLUTE(.); + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ + _rodata_start = ABSOLUTE(.); + __rodata_region_start = ABSOLUTE(.); . = ALIGN(4); - _rtc_text_start = ABSOLUTE(.); - *(.rtc.literal .rtc.text) - *(.rtc.entry.text) - *rtc_wake_stub*.*(.literal .text .literal.* .text.*) - _rtc_text_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + #include - /* This section is required to skip rtc.text area because rtc_iram_seg and - * rtc_data_seg are reflect the same address space on different buses. - */ - .rtc.dummy : - { - _rtc_dummy_start = ABSOLUTE(.); - _rtc_fast_start = ABSOLUTE(.); - . = SIZEOF(.rtc.text); - _rtc_dummy_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; - /* This section located in RTC FAST Memory area. - * It holds data marked with RTC_FAST_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_fast : - { + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) . = ALIGN(4); - _rtc_force_fast_start = ABSOLUTE(.); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + *(.rodata_wlog) + *(.rodata_wlog*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - *(.rtc.force_fast .rtc.force_fast.*) - . = ALIGN(4) ; - _rtc_force_fast_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) + #include + #include + #include + #include + #include + #include + #include + #include + #include - /* RTC data section holds RTC wake stub - * data/rodata, including from any source file - * named rtc_wake_stub*.c and the data marked with - * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + .flash.rodata_end : ALIGN(0x10) + { + . = ALIGN(4); + _rodata_reserved_end = ABSOLUTE(.); + _image_rodata_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + /** + * This section is required to skip flash rodata sections, because `ext_ram_seg` + * and `drom0_0_seg` are on the same bus */ - .rtc.data : +#if defined(CONFIG_ESP_SPIRAM) + + .ext_ram.dummy (NOLOAD): { - _rtc_data_start = ABSOLUTE(.); - *(.rtc.data) - *(.rtc.rodata) - *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) - _rtc_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + . = ORIGIN(ext_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start); + . = ALIGN (0x10000); + } GROUP_LINK_IN(ext_ram_seg) - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : + /* This section holds .ext_ram.bss data, and will be put in PSRAM */ + .ext_ram.bss (NOLOAD) : { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.*(.bss .bss.*) - *rtc_wake_stub*.*(COMMON) + _ext_ram_bss_start = ABSOLUTE(.); + *(.ext_ram.bss*) + . = ALIGN(4); - *(.rtc.data) - *(.rtc.rodata) + _spiram_heap_start = ABSOLUTE(.); + . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE - (_spiram_heap_start - _ext_ram_bss_start); + . = ALIGN(4); - _rtc_bss_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + _ext_ram_bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(ext_ram_seg) - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.*(.bss .bss.*) - *rtc_wake_stub*.*(COMMON) +#endif /* CONFIG_ESP_SPIRAM */ - _rtc_bss_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : + { + /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */ + . += 16; + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) - /* This section holds data that should not be initialized at power up - * and will be retained during deep sleep. - * User data marked with RTC_NOINIT_ATTR will be placed - * into this section. See the file "esp_attr.h" for more information. - */ - .rtc_noinit (NOLOAD): + .iram0.data : { . = ALIGN(4); - _rtc_noinit_start = ABSOLUTE(.); - *(.rtc_noinit .rtc_noinit.*) - . = ALIGN(4) ; - _rtc_noinit_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + _iram_data_start = ABSOLUTE(.); + *(.iram.data) + *(.iram.data*) + _iram_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - /* This section located in RTC SLOW Memory area. - * It holds data marked with RTC_SLOW_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : + .iram0.bss (NOLOAD) : { . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* Get size of rtc slow data based on rtc_data_location alias */ - _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); - _rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start); + _iram_bss_start = ABSOLUTE(.); + *(.iram.bss) + *(.iram.bss*) + _iram_bss_end = ABSOLUTE(.); + . = ALIGN(4); + _iram_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) - ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") - ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") + /* Marks the end of data, bss and possibly rodata */ + .dram0.heap_start (NOLOAD) : + { + . = ALIGN (8); + /* Lowest possible start address for the heap */ + _heap_start = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) #ifdef CONFIG_GEN_ISR_TABLES #include @@ -687,7 +857,10 @@ _heap_sentry = 0x3fceb910; ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), "IRAM0 segment data does not fit.") +ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), + "DRAM segment data does not fit.") + #if defined(CONFIG_ESP_SPIRAM) -ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), +ASSERT(((_ext_ram_bss_end - _ext_ram_bss_start) <= CONFIG_ESP_SPIRAM_SIZE), "External SPIRAM overflowed.") -#endif /* CONFIG_ESP_SPIRAM */ +#endif diff --git a/soc/espressif/esp32s3/esp32s3-mp.c b/soc/espressif/esp32s3/esp32s3-mp.c index 5f20b64c27a..ecd75aee27c 100644 --- a/soc/espressif/esp32s3/esp32s3-mp.c +++ b/soc/espressif/esp32s3/esp32s3-mp.c @@ -11,8 +11,6 @@ #include #include -#include -#include #include static struct k_spinlock loglock; @@ -28,7 +26,7 @@ void smp_log(const char *msg) void esp_appcpu_start(void *entry_point) { - soc_ll_unstall_core(1); + esp_cpu_unstall(1); if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) { REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); diff --git a/soc/espressif/esp32s3/loader.c b/soc/espressif/esp32s3/loader.c deleted file mode 100644 index ab6da243cd8..00000000000 --- a/soc/espressif/esp32s3/loader.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -#include -#include "esp32s3/dport_access.h" -#include "soc/cache_memory.h" -#include -#include "soc/extmem_reg.h" -#include - -#ifdef CONFIG_BOOTLOADER_MCUBOOT - -#define BOOT_LOG_INF(_fmt, ...) \ - ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) - -#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) - -extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; -extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; - -void __start(void); - -static HDR_ATTR void (*_entry_point)(void) = &__start; - -static int map_rom_segments(void) -{ - int rc = 0; - size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition); - uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start; - uint32_t _app_irom_size = (uint32_t)&_image_irom_size; - uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr; - - uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start; - uint32_t _app_drom_size = (uint32_t)&_image_drom_size; - uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr; - - uint32_t autoload = Cache_Suspend_DCache(); - - Cache_Invalidate_DCache_All(); - - /* Clear the MMU entries that are already set up, - * so the new app only has the mappings it creates. - */ - for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) { - FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL; - } - - uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr); - - rc |= esp_rom_Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, - _app_drom_vaddr & MMU_FLASH_MASK, - _app_drom_start & MMU_FLASH_MASK, - 64, drom_page_count, 0); - - uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr); - - rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, - _app_irom_vaddr & MMU_FLASH_MASK, - _app_irom_start & MMU_FLASH_MASK, - 64, irom_page_count, 0); - - REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE0_BUS); - REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS); - - Cache_Resume_DCache(autoload); - - /* Show map segments continue using same log format as during MCUboot phase */ - BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map", - _app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size); - BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n", - _app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size); - esp_rom_uart_tx_wait_idle(0); - - return rc; -} -#endif /* CONFIG_BOOTLOADER_MCUBOOT */ - -void __start(void) -{ -#ifdef CONFIG_BOOTLOADER_MCUBOOT - int err = map_rom_segments(); - - if (err != 0) { - ets_printf("Failed to setup XIP, aborting\n"); - abort(); - } -#endif - __esp_platform_start(); -} diff --git a/soc/espressif/esp32s3/mcuboot.ld b/soc/espressif/esp32s3/mcuboot.ld index 3d1049506ca..b562192a625 100644 --- a/soc/espressif/esp32s3/mcuboot.ld +++ b/soc/espressif/esp32s3/mcuboot.ld @@ -34,11 +34,41 @@ #define IROM_SEG_ALIGN 16 +/** Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32-S3 ROM static data usage is as follows: + * - 0x3fcd7e00 - 0x3fce9704: Shared buffers, used in UART/USB/SPI download mode only + * - 0x3fce9710 - 0x3fceb710: PRO CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fceb710 - 0x3fced710: APP CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fced710 - 0x3fcf0000: ROM .bss and .data (not easily reclaimable) + * + * The 2nd stage bootloader can take space up to the end of ROM shared + * buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700). + */ +/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */ +iram_dram_offset = 0x6f0000; + +bootloader_usable_dram_end = 0x3fce9700; + +bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */ +bootloader_dram_seg_len = 0x6600; +bootloader_iram_loader_seg_len = 0x3000; +bootloader_iram_seg_len = 0x9000; + +/* Start of the lower region is determined by region size and the end of the higher region */ +bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead; +/* bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len; */ +/* We move the dram start to 0x3FCA0000 */ +bootloader_dram_seg_start = 0x3FCA0000; +bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset; +bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len; + MEMORY { - iram_seg(RWX) : org = 0x403B6000, len = 0x8000 - iram_loader_seg(RWX) : org = 0x403BE000, len = 0x2000 - dram_seg(RW) : org = 0x3FCD0000, len = 0x6000 + iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len + iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len + dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -92,11 +122,6 @@ SECTIONS *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); . = ALIGN(4); - _thread_local_start = ABSOLUTE(.); - *(.tdata) - *(.tdata.*) - *(.tbss) - *(.tbss.*) *(.rodata_wlog) *(.rodata_wlog*) _thread_local_end = ABSOLUTE(.); @@ -104,7 +129,6 @@ SECTIONS . = ALIGN(4); } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - #include #include #include #include @@ -114,11 +138,6 @@ SECTIONS { __data_start = ABSOLUTE(.); - _btdm_data_start = ABSOLUTE(.); - *libbtdm_app.a:(.data .data.*) - . = ALIGN (4); - _btdm_data_end = ABSOLUTE(.); - *(.data) *(.data.*) *(.gnu.linkonce.d.*) @@ -129,6 +148,9 @@ SECTIONS *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + KEEP(*(.jcr)) *(.dram1 .dram1.*) . = ALIGN(4); @@ -200,7 +222,7 @@ SECTIONS . = ALIGN (16); _loader_text_start = ABSOLUTE(.); *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ + *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) *libzephyr.a:bootloader_flash_config_esp32s3.*(.literal .text .literal.* .text.*) *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) @@ -233,6 +255,11 @@ SECTIONS *libzephyr.a:app_cpu_start.*(.literal .text .literal.* .text.*) *esp_mcuboot.*(.literal .text .literal.* .text.*) *esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *(.fini.literal) *(.fini) *(.gnu.version) @@ -259,14 +286,6 @@ SECTIONS _bss_start = ABSOLUTE(.); /* required by bluetooth library */ __bss_start = ABSOLUTE(.); - _btdm_bss_start = ABSOLUTE(.); - *libbtdm_app.a:(.bss .bss.* COMMON) - . = ALIGN (4); - _btdm_bss_end = ABSOLUTE(.); - - /* Buffer for system heap should be placed in dram_seg */ - *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap) - *(.dynsbss) *(.sbss) *(.sbss.*) diff --git a/soc/espressif/esp32s3/power.c b/soc/espressif/esp32s3/power.c new file mode 100644 index 00000000000..f292774bc11 --- /dev/null +++ b/soc/espressif/esp32s3/power.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include +LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); + +static uint32_t intenable; + +/* Invoke Low Power/System Off specific Tasks */ +void pm_state_set(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(substate_id); + + switch (state) { + case PM_STATE_STANDBY: + intenable = XTENSA_RSR("INTENABLE"); + __asm__ volatile ("waiti 0"); + break; + default: + LOG_DBG("Unsupported power state %u", state); + break; + } +} + +/* Handle SOC specific activity after Low Power Mode Exit */ +void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(substate_id); + + switch (state) { + case PM_STATE_STANDBY: + z_xt_ints_on(intenable); + esp_light_sleep_start(); + break; + default: + LOG_DBG("Unsupported power state %u", state); + break; + } +} diff --git a/soc/espressif/esp32s3/poweroff.c b/soc/espressif/esp32s3/poweroff.c new file mode 100644 index 00000000000..d08d40dda97 --- /dev/null +++ b/soc/espressif/esp32s3/poweroff.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include + +void z_sys_poweroff(void) +{ + /* Forces RTC domain to be always on */ + esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON); + esp_deep_sleep_start(); +} diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c index d41732db14e..54af1c4d20b 100644 --- a/soc/espressif/esp32s3/soc.c +++ b/soc/espressif/esp32s3/soc.c @@ -8,9 +8,20 @@ #include #include #include +#include #include #include #include +#include +#include +#include +#include +#include + +#if CONFIG_ESP_SPIRAM +#include +#include +#endif #include #include @@ -20,21 +31,19 @@ #include #include -#include "esp_private/system_internal.h" -#include "esp32s3/rom/cache.h" -#include "esp32s3/rom/rtc.h" -#include "soc/syscon_reg.h" -#include "hal/soc_ll.h" -#include "hal/wdt_hal.h" -#include "soc/cpu.h" -#include "soc/gpio_periph.h" -#include "esp_spi_flash.h" -#include "esp_err.h" -#include "esp_timer.h" -#include "esp_app_format.h" -#include "esp_clk_internal.h" - -#include "esp32s3/spiram.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #ifdef CONFIG_MCUBOOT #include "bootloader_init.h" @@ -49,7 +58,7 @@ extern int _ext_ram_bss_end; extern void z_cstart(void); extern void esp_reset_reason_init(void); -#if CONFIG_SOC_ENABLE_APPCPU +#ifdef CONFIG_SOC_ENABLE_APPCPU extern const unsigned char esp32s3_appcpu_fw_array[]; void IRAM_ATTR esp_start_appcpu(void) @@ -86,7 +95,7 @@ void IRAM_ATTR esp_start_appcpu(void) esp_appcpu_start((void *)entry_addr); } -#endif /* CONFIG_SOC_ENABLE_APPCPU */ +#endif /* CONFIG_SOC_ENABLE_APPCPU*/ #ifndef CONFIG_MCUBOOT /* @@ -148,32 +157,40 @@ void IRAM_ATTR __esp_platform_start(void) */ esp_config_data_cache_mode(); - /* Apply SoC patches */ - esp_errata(); + esp_mspi_pin_init(); + + spi_flash_init_chip_state(); + + mspi_timing_flash_tuning(); + + esp_mmu_map_init(); #if CONFIG_ESP_SPIRAM - esp_err_t err = esp_spiram_init(); + esp_err_t err = esp_psram_init(); if (err != ESP_OK) { printk("Failed to Initialize external RAM, aborting.\n"); abort(); } - esp_spiram_init_cache(); - if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { + if (esp_psram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { printk("External RAM size is less than configured, aborting.\n"); abort(); } - if (!esp_spiram_test()) { - printk("External RAM failed memory test!\n"); - abort(); + if (esp_psram_is_initialized()) { + if (!esp_psram_extram_test()) { + printk("External RAM failed memory test!"); + abort(); + } } memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); #endif /* CONFIG_ESP_SPIRAM */ + /* Apply SoC patches */ + esp_errata(); /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence * related issues in application. Hence disable that as we are about to start @@ -223,100 +240,3 @@ void sys_arch_reboot(int type) { esp_restart_noos(); } - -void IRAM_ATTR esp_restart_noos(void) -{ - /* disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - /* enable RTC watchdog for 1 second */ - wdt_hal_context_t wdt_ctx; - uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); - - wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false); - wdt_hal_write_protect_disable(&wdt_ctx); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - - /* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */ - wdt_hal_set_flashboot_en(&wdt_ctx, true); - wdt_hal_write_protect_enable(&wdt_ctx); - - /* disable TG0/TG1 watchdogs */ - wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; - - wdt_hal_write_protect_disable(&wdt0_context); - wdt_hal_disable(&wdt0_context); - wdt_hal_write_protect_enable(&wdt0_context); - - wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; - - wdt_hal_write_protect_disable(&wdt1_context); - wdt_hal_disable(&wdt1_context); - wdt_hal_write_protect_enable(&wdt1_context); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Disable_ICache(); - Cache_Disable_DCache(); - - const uint32_t core_id = cpu_hal_get_core_id(); -#if CONFIG_SMP - const uint32_t other_core_id = (core_id == 0) ? 1 : 0; - - soc_ll_reset_core(other_core_id); - soc_ll_stall_core(other_core_id); -#endif - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, - SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST | - SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_SDIO_HOST_RST | - SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | - SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST); - REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | - SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - - /* Reset DMA */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - - SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - - rtc_clk_cpu_freq_set_xtal(); - - /* Reset CPUs */ - if (core_id == 0) { - /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ - soc_ll_reset_core(1); - soc_ll_reset_core(0); - } else { - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - } - - while (true) { - ; - } -} diff --git a/soc/espressif/esp32s3/soc.h b/soc/espressif/esp32s3/soc.h index e45b10cac2f..2cb247ca489 100644 --- a/soc/espressif/esp32s3/soc.h +++ b/soc/espressif/esp32s3/soc.h @@ -11,12 +11,11 @@ #include #include #include -#include "esp32s3/rom/cache.h" +#include #include -#include "soc/extmem_reg.h" -#include "soc/cache_memory.h" -#include "hal/cpu_hal.h" -#include "hal/cpu_types.h" +#include +#include +#include #include #include @@ -24,7 +23,7 @@ #include #include -#include +#include void __esp_platform_start(void); diff --git a/soc/espressif/esp32s3/soc_appcpu.c b/soc/espressif/esp32s3/soc_appcpu.c index 583f0b8119a..410e015e744 100644 --- a/soc/espressif/esp32s3/soc_appcpu.c +++ b/soc/espressif/esp32s3/soc_appcpu.c @@ -23,11 +23,11 @@ #include #include #include -#include +#include #include -#include +#include #include -#include +#include "esp_cpu.h" #include #include #include @@ -37,7 +37,7 @@ extern void z_cstart(void); static void core_intr_matrix_clear(void) { - uint32_t core_id = cpu_hal_get_core_id(); + uint32_t core_id = esp_cpu_get_core_id(); for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) { intr_matrix_set(core_id, i, ETS_INVALID_INUM); @@ -88,85 +88,3 @@ void sys_arch_reboot(int type) { esp_restart_noos(); } - -void IRAM_ATTR esp_restart_noos(void) -{ - /* disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - /* enable RTC watchdog for 1 second */ - wdt_hal_context_t wdt_ctx; - uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); - - wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false); - wdt_hal_write_protect_disable(&wdt_ctx); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - - /* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */ - wdt_hal_set_flashboot_en(&wdt_ctx, true); - wdt_hal_write_protect_enable(&wdt_ctx); - - /* disable TG0/TG1 watchdogs */ - wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; - - wdt_hal_write_protect_disable(&wdt0_context); - wdt_hal_disable(&wdt0_context); - wdt_hal_write_protect_enable(&wdt0_context); - - wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; - - wdt_hal_write_protect_disable(&wdt1_context); - wdt_hal_disable(&wdt1_context); - wdt_hal_write_protect_enable(&wdt1_context); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Disable_ICache(); - Cache_Disable_DCache(); - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, - SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST | - SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_SDIO_HOST_RST | - SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | - SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST); - REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | - SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - - /* Reset DMA */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - - SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - - rtc_clk_cpu_freq_set_xtal(); - - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - - while (true) { - ; - } -} diff --git a/soc/espressif/esp32s3/soc_cache.c b/soc/espressif/esp32s3/soc_cache.c index 6bb33e60c69..65330b2f939 100644 --- a/soc/espressif/esp32s3/soc_cache.c +++ b/soc/espressif/esp32s3/soc_cache.c @@ -7,52 +7,54 @@ #include "soc.h" #ifndef CONFIG_MCUBOOT +extern int _instruction_reserved_start; +extern int _instruction_reserved_end; extern int _rodata_reserved_start; extern int _rodata_reserved_end; + extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, - uint8_t cfg_cache_line_size); + uint8_t cfg_cache_line_size); extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, - uint8_t cfg_cache_line_size); -extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + uint8_t cfg_cache_line_size); extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num, - uint32_t rodata_start, uint32_t rodata_end, - int i_off, int ro_off); + uint32_t rodata_start, uint32_t rodata_end, int i_off, + int ro_off); extern void Cache_Enable_ICache(uint32_t autoload); void IRAM_ATTR esp_config_instruction_cache_mode(void) { rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, - CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, - CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE); + CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, + CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE); Cache_Suspend_DCache(); } void IRAM_ATTR esp_config_data_cache_mode(void) { - int s_instr_flash2spiram_off = 0; - int s_rodata_flash2spiram_off = 0; - rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, - CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, - CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE); + CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, + CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE); Cache_Resume_DCache(0); /* Configure the Cache MMU size for instruction and rodata in flash. */ - uint32_t rodata_reserved_start_align = - (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1); + uint32_t _instruction_size = + (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start; uint32_t cache_mmu_irom_size = - ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t); + ((_instruction_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE) * + sizeof(uint32_t); + uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start; uint32_t cache_mmu_drom_size = - (((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1) - / MMU_PAGE_SIZE) * sizeof(uint32_t); + ((_rodata_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE) * + sizeof(uint32_t); + Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); + int s_instr_flash2spiram_off = 0; + int s_rodata_flash2spiram_off = 0; Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size / sizeof(uint32_t), - cache_mmu_drom_size / sizeof(uint32_t), - (uint32_t)&_rodata_reserved_start, - (uint32_t)&_rodata_reserved_end, - s_instr_flash2spiram_off, - s_rodata_flash2spiram_off); + cache_mmu_drom_size / sizeof(uint32_t), + (uint32_t)&_rodata_reserved_start, (uint32_t)&_rodata_reserved_end, + s_instr_flash2spiram_off, s_rodata_flash2spiram_off); } #endif /* CONFIG_MCUBOOT */ From ad12a06e2e69073393af610581d713412e8beb18 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 6 Mar 2024 23:51:25 -0300 Subject: [PATCH 1910/2402] soc: espressif: esp32c3: update to hal_espressif v5.1 Modify and reorganize SoC to meet updated hal. Signed-off-by: Sylvio Alves Signed-off-by: Lucas Tamborrino --- .../zephyr/dt-bindings/clock/esp32c3_clock.h | 4 +- soc/espressif/esp32c3/CMakeLists.txt | 66 ++++--------- soc/espressif/esp32c3/Kconfig | 50 ---------- soc/espressif/esp32c3/Kconfig.defconfig | 3 - soc/espressif/esp32c3/Kconfig.mac | 48 ++++++++++ soc/espressif/esp32c3/Kconfig.rtc | 50 ++++++++++ soc/espressif/esp32c3/default.ld | 6 ++ soc/espressif/esp32c3/loader.c | 93 ------------------- soc/espressif/esp32c3/mcuboot.ld | 13 ++- soc/espressif/esp32c3/poweroff.c | 2 +- soc/espressif/esp32c3/soc.c | 76 +++++---------- soc/espressif/esp32c3/soc.h | 8 +- soc/espressif/esp32c3/soc_irq.c | 3 +- 13 files changed, 166 insertions(+), 256 deletions(-) create mode 100644 soc/espressif/esp32c3/Kconfig.mac create mode 100644 soc/espressif/esp32c3/Kconfig.rtc delete mode 100644 soc/espressif/esp32c3/loader.c diff --git a/include/zephyr/dt-bindings/clock/esp32c3_clock.h b/include/zephyr/dt-bindings/clock/esp32c3_clock.h index 4c0b6bf38b0..6b5b3de1227 100644 --- a/include/zephyr/dt-bindings/clock/esp32c3_clock.h +++ b/include/zephyr/dt-bindings/clock/esp32c3_clock.h @@ -18,8 +18,8 @@ #define ESP32_CLK_CPU_160M 160000000 /* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_32M 0U -#define ESP32_CLK_XTAL_40M 1U +#define ESP32_CLK_XTAL_32M 32 +#define ESP32_CLK_XTAL_40M 40 /* Supported RTC fast clock frequencies */ #define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U diff --git a/soc/espressif/esp32c3/CMakeLists.txt b/soc/espressif/esp32c3/CMakeLists.txt index 3ea38bd5287..a5c44685ef1 100644 --- a/soc/espressif/esp32c3/CMakeLists.txt +++ b/soc/espressif/esp32c3/CMakeLists.txt @@ -5,7 +5,7 @@ zephyr_sources( soc_irq.S soc_irq.c soc.c - loader.c + ../common/loader.c ) zephyr_include_directories(.) @@ -25,52 +25,22 @@ dt_reg_addr(boot_off PATH ${dts_partition_path}) math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") + + if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") + endif() + + if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") + endif() + + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") @@ -80,7 +50,7 @@ if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) diff --git a/soc/espressif/esp32c3/Kconfig b/soc/espressif/esp32c3/Kconfig index 6533ba0b5d6..38e2ab9ac35 100644 --- a/soc/espressif/esp32c3/Kconfig +++ b/soc/espressif/esp32c3/Kconfig @@ -22,56 +22,6 @@ config IDF_TARGET_ESP32C3 bool "ESP32C3 as target board" default y -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - -choice ESP32C3_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32C3_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - -config ESP32C3_RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - -config ESP32C3_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32C3_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XP pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32C3_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" - -endchoice # ESP32C3_RTC_CLK_SRC - -config ESP32C3_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32C3_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32C3_RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - config ESP32_PHY_MAX_WIFI_TX_POWER int "Max WiFi TX power (dBm)" range 10 20 diff --git a/soc/espressif/esp32c3/Kconfig.defconfig b/soc/espressif/esp32c3/Kconfig.defconfig index ce148c66d48..43d1d471ab6 100644 --- a/soc/espressif/esp32c3/Kconfig.defconfig +++ b/soc/espressif/esp32c3/Kconfig.defconfig @@ -6,9 +6,6 @@ if SOC_SERIES_ESP32C3 config NUM_IRQS default 62 -config ESPTOOLPY_FLASHFREQ_80M - default y - config FLASH_SIZE default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) diff --git a/soc/espressif/esp32c3/Kconfig.mac b/soc/espressif/esp32c3/Kconfig.mac new file mode 100644 index 00000000000..d16a2c5611c --- /dev/null +++ b/soc/espressif/esp32c3/Kconfig.mac @@ -0,0 +1,48 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32C3 + +choice ESP32C3_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or derived from a + single base MAC address. + If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap, + Bluetooth and Ethernet) receive a universally administered MAC address. These are generated + sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address. + If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth) + receive a universally administered MAC address. These are generated sequentially by adding 0 + and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet) + receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC + addresses, respectively. + When using the default (Espressif-assigned) base MAC address, either setting can be used. When using + a custom universal MAC address range, the correct setting will depend on the allocation of MAC + addresses in this range (either 2 or 4 per device.) + Note that ESP32-C3 has no integrated Ethernet MAC. Although it's possible to use the esp_read_mac() + API to return a MAC for Ethernet, this can only be used with an external MAC peripheral. + +config ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_BT + +config ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR + bool "Four" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + select ESP_MAC_ADDR_UNIVERSE_BT + select ESP_MAC_ADDR_UNIVERSE_ETH + +endchoice # ESP32C3_UNIVERSAL_MAC_ADDRESSES + +config ESP32C3_UNIVERSAL_MAC_ADDRESSES + int + default 2 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR + +endif # SOC_SERIES_ESP32C3 diff --git a/soc/espressif/esp32c3/Kconfig.rtc b/soc/espressif/esp32c3/Kconfig.rtc new file mode 100644 index 00000000000..fcd91f9ff5c --- /dev/null +++ b/soc/espressif/esp32c3/Kconfig.rtc @@ -0,0 +1,50 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32C3 + +choice RTC_CLK_SRC + prompt "RTC clock source" + default RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + +config RTC_CLK_SRC_INT_RC + bool "Internal 136kHz RC oscillator" + +config RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XP pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config RTC_CLK_SRC_INT_8MD256 + bool "Internal 17.5MHz oscillator, divided by 256" + +endchoice # ESP32C3_RTC_CLK_SRC + +config RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + default 1024 if RTC_CLK_SRC_INT_RC + range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + range 0 32766 if RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +endif # SOC_SERIES_ESP32C3 diff --git a/soc/espressif/esp32c3/default.ld b/soc/espressif/esp32c3/default.ld index 4de4bd310d4..39e6906c62f 100644 --- a/soc/espressif/esp32c3/default.ld +++ b/soc/espressif/esp32c3/default.ld @@ -247,6 +247,8 @@ SECTIONS *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) *libzephyr.a:loader.*(.literal .text .literal.* .text.*) *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) @@ -335,6 +337,8 @@ SECTIONS *libzephyr.a:log_core.*(.rodata .rodata.*) *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:cache_hal.*(.rodata .rodata.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) *libzephyr.a:loader.*(.rodata .rodata.*) *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) @@ -404,6 +408,7 @@ SECTIONS .flash.text : ALIGN(IROM_SEG_ALIGN) { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); _text_start = ABSOLUTE(.); #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) @@ -431,6 +436,7 @@ SECTIONS . += 16; _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); _etext = .; /** diff --git a/soc/espressif/esp32c3/loader.c b/soc/espressif/esp32c3/loader.c deleted file mode 100644 index d4740fd2354..00000000000 --- a/soc/espressif/esp32c3/loader.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "soc/cache_memory.h" -#include "soc/extmem_reg.h" -#include - -#include -#include -#include -#include -#include - -#ifdef CONFIG_BOOTLOADER_MCUBOOT - -#define BOOT_LOG_INF(_fmt, ...) \ - ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) - -#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) - -extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; -extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; - -void __start(void); - -static HDR_ATTR void (*_entry_point)(void) = &__start; - -static int map_rom_segments(void) -{ - int rc = 0; - - size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition); - uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start; - uint32_t _app_irom_size = (uint32_t)&_image_irom_size; - uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr; - - uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start; - uint32_t _app_drom_size = (uint32_t)&_image_drom_size; - uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr; - - uint32_t autoload = esp_rom_Cache_Suspend_ICache(); - - esp_rom_Cache_Invalidate_ICache_All(); - - /* Clear the MMU entries that are already set up, - * so the new app only has the mappings it creates. - */ - for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) { - FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL; - } - - uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr); - - rc |= esp_rom_Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, _app_drom_vaddr & 0xffff0000, - _app_drom_start & 0xffff0000, 64, drom_page_count, 0); - - uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr); - - rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, _app_irom_vaddr & 0xffff0000, - _app_irom_start & 0xffff0000, 64, irom_page_count, 0); - - REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); - REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); - - esp_rom_Cache_Resume_ICache(autoload); - - /* Show map segments continue using same log format as during MCUboot phase */ - BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map", - _app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size); - BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n", - _app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size); - esp_rom_uart_tx_wait_idle(0); - - return rc; -} -#endif /* CONFIG_BOOTLOADER_MCUBOOT */ - -void __start(void) -{ -#ifdef CONFIG_BOOTLOADER_MCUBOOT - int err = map_rom_segments(); - - if (err != 0) { - ets_printf("Failed to setup XIP, aborting\n"); - abort(); - } -#endif - __esp_platform_start(); -} diff --git a/soc/espressif/esp32c3/mcuboot.ld b/soc/espressif/esp32c3/mcuboot.ld index fe68368fdd1..958018168e1 100644 --- a/soc/espressif/esp32c3/mcuboot.ld +++ b/soc/espressif/esp32c3/mcuboot.ld @@ -35,9 +35,9 @@ /* Global symbols required for espressif hal build */ MEMORY { - iram_seg (RX) : org = 0x403CA000, len = 0x6000 - iram_loader_seg (RX) : org = 0x403D0000, len = 0x4000 - dram_seg (RW) : org = 0x3FCD8000, len = 0x8000 + iram_seg (RX) : org = 0x403CA000, len = 0x9000 + iram_loader_seg (RX) : org = 0x403D3000, len = 0x4000 + dram_seg (RW) : org = 0x3FCD8000, len = 0x9000 #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -134,7 +134,8 @@ SECTIONS *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) - + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) KEEP(*(.jcr)) *(.dram1 .dram1.*) . = ALIGN(4); @@ -227,6 +228,10 @@ SECTIONS *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) *esp_mcuboot.*(.literal .text .literal.* .text.*) *esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) *(.fini.literal) *(.fini) *(.gnu.version) diff --git a/soc/espressif/esp32c3/poweroff.c b/soc/espressif/esp32c3/poweroff.c index 8948e05c01b..2410366bafe 100644 --- a/soc/espressif/esp32c3/poweroff.c +++ b/soc/espressif/esp32c3/poweroff.c @@ -10,6 +10,6 @@ void z_sys_poweroff(void) { /* Forces RTC domain to be always on */ - esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON); + esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON); esp_deep_sleep_start(); } diff --git a/soc/espressif/esp32c3/soc.c b/soc/espressif/esp32c3/soc.c index c125450a4d9..c25f188da89 100644 --- a/soc/espressif/esp32c3/soc.c +++ b/soc/espressif/esp32c3/soc.c @@ -7,17 +7,21 @@ /* Include esp-idf headers first to avoid redefining BIT() macro */ #include #include +#include #include #include #include -#include -#include "hal/soc_ll.h" #include "hal/wdt_hal.h" #include "esp_cpu.h" +#include "hal/soc_hal.h" +#include "hal/cpu_hal.h" #include "esp_timer.h" -#include "esp_spi_flash.h" +#include "esp_private/system_internal.h" #include "esp_clk_internal.h" #include +#include +#include "esp_private/esp_mmu_map_private.h" + #include #include @@ -82,9 +86,9 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) extern int _rodata_reserved_start; uint32_t rodata_reserved_start_align = - (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1); + (uint32_t)&_rodata_reserved_start & ~(CONFIG_MMU_PAGE_SIZE - 1); uint32_t cache_mmu_irom_size = - ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * + ((rodata_reserved_start_align - SOC_DROM_LOW) / CONFIG_MMU_PAGE_SIZE) * sizeof(uint32_t); esp_rom_cache_set_idrom_mmu_size(cache_mmu_irom_size, @@ -96,6 +100,22 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN); SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN); +#ifdef CONFIG_SOC_FLASH_ESP32 + esp_mspi_pin_init(); + + /** + * This function initialise the Flash chip to the user-defined settings. + * + * In bootloader, we only init Flash (and MSPI) to a preliminary state, for being flexible to + * different chips. + * In this stage, we re-configure the Flash (and MSPI) to required configuration + */ + spi_flash_init_chip_state(); + + esp_mmu_map_init(); + +#endif /*CONFIG_SOC_FLASH_ESP32*/ + /* Configures the CPU clock, RTC slow and fast clocks, and performs * RTC slow clock calibration. */ @@ -128,52 +148,6 @@ int IRAM_ATTR arch_printk_char_out(int c) return 0; } -void IRAM_ATTR esp_restart_noos(void) -{ - /* Disable interrupts */ - csr_read_clear(mstatus, MSTATUS_MIE); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, - SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST | - SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_EMAC_RST | - SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | - BLE_REG_REST_BIT | BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT); - - REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); - - /* Reset uart0 core first, then reset apb side. */ - SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M); - - /* Reset timer/spi/uart */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, - SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - /* Reset dma */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - - /* Reset core */ - soc_ll_reset_core(0); - - while (true) { - ; - } -} - void sys_arch_reboot(int type) { esp_restart_noos(); diff --git a/soc/espressif/esp32c3/soc.h b/soc/espressif/esp32c3/soc.h index 68fb6fdb1ce..73e2fbfee1e 100644 --- a/soc/espressif/esp32c3/soc.h +++ b/soc/espressif/esp32c3/soc.h @@ -13,13 +13,18 @@ #include #include #include -#include "esp32c3/clk.h" +#include #endif #ifndef _ASMLANGUAGE void __esp_platform_start(void); +static inline uint32_t esp_core_id(void) +{ + return 0; +} + extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); extern void esp_rom_uart_attach(void); extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no); @@ -40,7 +45,6 @@ extern int esp_rom_Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); extern void esp_rom_Cache_Resume_ICache(uint32_t autoload); -extern spiflash_legacy_data_t esp_rom_spiflash_legacy_data; extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index, bool inverted); extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index, diff --git a/soc/espressif/esp32c3/soc_irq.c b/soc/espressif/esp32c3/soc_irq.c index 44c8161950c..6511901a0d4 100644 --- a/soc/espressif/esp32c3/soc_irq.c +++ b/soc/espressif/esp32c3/soc_irq.c @@ -6,11 +6,10 @@ #include #include +#include #include #include #include -#include -#include "hal/soc_ll.h" #include #include #include From 2bc8c77b4ece62e23160b899d95c43082012fc5a Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 6 Mar 2024 23:56:25 -0300 Subject: [PATCH 1911/2402] samples: esp32: update to hal_espressif v5.1 Modify and reorganize SoC to meet updated hal. Signed-off-by: Sylvio Alves --- samples/boards/esp32/deep_sleep/Kconfig | 4 ++-- samples/boards/esp32/flash_encryption/src/main.c | 5 +++-- samples/boards/esp32/flash_memory_mapped/src/main.c | 2 +- samples/boards/esp32/light_sleep/src/main.c | 3 ++- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/samples/boards/esp32/deep_sleep/Kconfig b/samples/boards/esp32/deep_sleep/Kconfig index 40ce68c076b..3cde5e740d6 100644 --- a/samples/boards/esp32/deep_sleep/Kconfig +++ b/samples/boards/esp32/deep_sleep/Kconfig @@ -5,7 +5,7 @@ mainmenu "Espressif Deep Sleep demo" config EXAMPLE_EXT1_WAKEUP bool "Enable wakeup from GPIO" - depends on !SOC_ESP32C3 + depends on !SOC_SERIES_ESP32C3 help This option enables wake up from deep sleep from GPIO2 and GPIO4. They should be connected to LOW to avoid floating pins. @@ -14,7 +14,7 @@ config EXAMPLE_EXT1_WAKEUP config EXAMPLE_GPIO_WAKEUP bool "Enable wakeup from GPIO" - depends on SOC_ESP32C3 + depends on SOC_SERIES_ESP32C3 help This option enables wake up from GPIO, only GPIO0~5 can be used to wake up. Be aware that when low level is used to trigger wakeup, diff --git a/samples/boards/esp32/flash_encryption/src/main.c b/samples/boards/esp32/flash_encryption/src/main.c index 414376495ca..07799dfe21a 100644 --- a/samples/boards/esp32/flash_encryption/src/main.c +++ b/samples/boards/esp32/flash_encryption/src/main.c @@ -10,7 +10,8 @@ #include #include -#include +#include +#include #include #include @@ -45,7 +46,7 @@ int main(void) /* read flash content without decrypting content */ memset(buffer, 0, sizeof(buffer)); - spi_flash_read(address, &buffer, sizeof(buffer)); + esp_flash_read(NULL, &buffer, address, sizeof(buffer)); LOG_HEXDUMP_INF(buffer, sizeof(buffer), "FLASH RAW DATA (Encrypted)"); /* read flash content and decrypt */ diff --git a/samples/boards/esp32/flash_memory_mapped/src/main.c b/samples/boards/esp32/flash_memory_mapped/src/main.c index d836bb34816..f6124107bfe 100644 --- a/samples/boards/esp32/flash_memory_mapped/src/main.c +++ b/samples/boards/esp32/flash_memory_mapped/src/main.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include #include diff --git a/samples/boards/esp32/light_sleep/src/main.c b/samples/boards/esp32/light_sleep/src/main.c index 4fee6bf6548..50cb920d159 100644 --- a/samples/boards/esp32/light_sleep/src/main.c +++ b/samples/boards/esp32/light_sleep/src/main.c @@ -8,7 +8,8 @@ #include #include #include -#include "esp_sleep.h" +#include +#include /* Most development boards have "boot" button attached to GPIO0. * You can also change this to another pin. From 46a0a72be855e34bbee8f86d79aac2c91c0ba207 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 18 Mar 2024 11:39:25 -0300 Subject: [PATCH 1912/2402] west.yml: update hal_espressif no v5.1 Update hal_espressif to version v5.1 in order to provide support to newer SoCS. Signed-off-by: Sylvio Alves --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 36059a132f2..857dbfd5f5f 100644 --- a/west.yml +++ b/west.yml @@ -152,7 +152,7 @@ manifest: groups: - hal - name: hal_espressif - revision: e705cc16c4b63b5b3cad5c395297a4c2b49651fd + revision: 742df6bfc595591603361eb703ac9462ed6384c6 path: modules/hal/espressif west-commands: west/west-commands.yml groups: From 4c45884c8c09ffac4e4d14c85bfdaca5e13ee933 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 3 Apr 2024 15:25:44 +0300 Subject: [PATCH 1913/2402] net: tcp: Give a warning to user if packet cloning fails If the packet cloning fails (can easily happen when working with loopback interface and when having low net_buf count), then print a warning to the user. Error could also be possible but as the situation might correct itself in this case, the warning should be enough. Signed-off-by: Jukka Rissanen --- subsys/net/ip/tcp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/subsys/net/ip/tcp.c b/subsys/net/ip/tcp.c index 3aee7e047ef..5c36199971c 100644 --- a/subsys/net/ip/tcp.c +++ b/subsys/net/ip/tcp.c @@ -353,6 +353,7 @@ static void tcp_send(struct net_pkt *pkt) * free the net_pkt. */ tcp_pkt_unref(pkt); + NET_WARN("net_pkt alloc failure"); goto out; } @@ -866,6 +867,8 @@ static bool tcp_send_process_no_lock(struct tcp *conn) if (clone) { tcp_send(clone); conn->send_retries--; + } else { + NET_WARN("net_pkt alloc failure"); } } else { unref = true; @@ -880,7 +883,7 @@ static bool tcp_send_process_no_lock(struct tcp *conn) struct net_pkt, next) : tcp_pkt_clone(pkt); if (!pkt) { - NET_ERR("net_pkt alloc failure"); + NET_WARN("net_pkt alloc failure"); goto out; } From ab84989a12725d0ffa774da8cb244e9ff9aaa539 Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Wed, 3 Apr 2024 11:00:17 +0200 Subject: [PATCH 1914/2402] arch/riscv: remove the `Kconfig.core` file This commit removes the `Kconfig.core` file. It's been largely unused, and the only symbol it provides (`RISCV_CORE_E31`) overlaps with the SoC-layer provided `SOC_SERIES_SIFIVE_FREEDOM_FE300`. As of date, the only SoC that uses the E31 core in Zephyr is the FE310 SoC. Signed-off-by: Filip Kokosinski --- arch/riscv/Kconfig | 1 - arch/riscv/Kconfig.core | 18 ------------------ .../riscv32_xip/qemu_riscv32_xip_defconfig | 1 - boards/sifive/hifive1/Kconfig | 5 ----- soc/sifive/sifive_freedom/fe300/Kconfig | 3 +++ 5 files changed, 3 insertions(+), 25 deletions(-) delete mode 100644 arch/riscv/Kconfig.core delete mode 100644 boards/sifive/hifive1/Kconfig diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9f2d24977a9..66c96cddda9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -374,6 +374,5 @@ config ARCH_HAS_SINGLE_THREAD_SUPPORT default y if !SMP rsource "Kconfig.isa" -rsource "Kconfig.core" endmenu diff --git a/arch/riscv/Kconfig.core b/arch/riscv/Kconfig.core deleted file mode 100644 index a036db5f04d..00000000000 --- a/arch/riscv/Kconfig.core +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2022 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -menu "RISCV core" - -config RISCV_CORE_E31 - bool "E31 core" - select RISCV_PMP - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - help - SiFive E31 Standard Core - -endmenu diff --git a/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig b/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig index f9bc269d13f..578726a799f 100644 --- a/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig +++ b/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig @@ -8,4 +8,3 @@ CONFIG_PINCTRL=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_RISCV_CORE_E31=y diff --git a/boards/sifive/hifive1/Kconfig b/boards/sifive/hifive1/Kconfig deleted file mode 100644 index 34402f96d73..00000000000 --- a/boards/sifive/hifive1/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HIFIVE1 - select RISCV_CORE_E31 diff --git a/soc/sifive/sifive_freedom/fe300/Kconfig b/soc/sifive/sifive_freedom/fe300/Kconfig index e5796d7c9dc..cde775ade0f 100644 --- a/soc/sifive/sifive_freedom/fe300/Kconfig +++ b/soc/sifive/sifive_freedom/fe300/Kconfig @@ -9,9 +9,12 @@ config SOC_SERIES_SIFIVE_FREEDOM_FE300 select RISCV select RISCV_PRIVILEGED select RISCV_HAS_PLIC + select RISCV_PMP + select RISCV_ISA_RV32I select RISCV_ISA_EXT_M select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI From 17aee174106c91e17af0d78a0d40419899f03d0f Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 29 Mar 2024 10:07:13 +0100 Subject: [PATCH 1915/2402] docs: Bluetooth: Add sections on GTBS and GMCS Since GTBS and GMCS in both spec definitions and in the Zephyr implemenation are notably different, it is worthwhile pointing these out in the documentation for content control. Signed-off-by: Emil Gydesen --- .../bluetooth/bluetooth-le-audio-arch.rst | 104 ++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst b/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst index 06603dca2e0..d2a0b6cd4c0 100644 --- a/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst +++ b/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst @@ -313,6 +313,110 @@ The MCP implementation supports the following roles The API reference for media control can be found in :ref:`Bluetooth Media Control `. +Generic TBS and Generic MCS +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Both the Telephone Bearer Service (TBS) used by CCP and the Media Control Service (MCS) used by MCP +have the concept of generic instances of the services called Generic TBS (GTBS) and +Generic MCS (GMCS). + +While these share a common name prefix, the behavior of these two may be significantly different. + +Generic TBS +^^^^^^^^^^^ + +The TBS spec defines GTBS as + + GTBS provides a single point of access and exposes a representation of its internal telephone + bearers into a single telephone bearer. + This service provides telephone status and control of the device as a single unit with a + single set of characteristics. + It is left up to the implementation to determine what telephone bearer a characteristic of + GTBS represents at any time. + There is no specified manner of representing a characteristic from each individual TBS that + resides on the device to the same characteristic of the GTBS. + + For example, if there is more than one TBS on a device and each has a unique telephone bearer + name (e.g., Name1 and Name2), + the way the GTBS represents the telephone bearer name is left up to the implementation. + GTBS is suited for clients that do not need to access or control all the + information available on specific telephone bearers. + +This means that a GTBS instance represents one or more telephone bearers. +A telephone bearer could be any application on a device that can handle (telephone) calls, +such as the default Call application on a smartphone, +but also other applications such as Signal, Discord, Teams, Slack, etc. + +GTBS may be standalone (i.e.the device only has a GTBS instance without any TBS instances), +and the behavior of the GTBS is mostly left up to the implementation. +In Zephyr the implementation of GBTS is that it contains some generic information, +such as the provider name which is defined to simply be "Generic TBS", +but the majority of the information in the GTBS instance in Zephyr has been implemented to be a +union of the data of the other bearers. +For example if you have a bearer for regular phone calls and +Teams and have an active call in both bearers, +then each of those bearers will report a single call, +but the GTBS instance will report 2 calls, +making it possible for a simple Call Control Client to control all calls from a single bearer. +Similarly the supported URIs for each bearer are also made into a union in GTBS, and when placing +a call using the GTBS the server will pick the most suited bearer depending on the URI. +For example calls with URI `tel` would go to the regular phone application, +and calls with the URI `skype` would go to the Teams application. + +In conclusion the GTBS implementation in Zephyr is a union of the non-generic telephone bearers. + +Generic MCS +^^^^^^^^^^^ + +The MCS spec defines GMCS as + + The GMCS provides status and control of media playback for the device as a single unit. + An MCS instance describes and controls the media playback for a + specific media player within the device. + A device implements MCS instances to allow clients to access the + separate internal media player entities. + +and where the behavior of GMCS is defined as + + ... the behavior of MCS and GMCS is identical, + and all the characteristics and the characteristics' behaviors are the same. + The term “MCS” is used throughout the document. + Unless otherwise specifically stated in this specification, + the same meaning applies to GMCS as well. + +This means that a GMCS instance works the same way as an MCS instance, +and it follows that GMCS + + controls the media playback for a specific media player within the device + +A media player on a device could be anything that plays media, +such as a Spotify or Youtube application on a smartphone. +Thus if a device has multiple MCS instances, +then each of these control media for that specific application, +but the GMCS also controls media playback for a specific media player. +GMCS can thus be considered a pointer to a specific MCS instance, +and control either e.g. Spotify or Youtube, but not both. + +The MCS spec does however provide an example of GMCS where a device can + + Implement a GMCS that provides status and control of media playback for the device as a whole. + +Which may indicate that an implementation may use GMCS to represent all media players with GMCS and +not a specific media player as stated above. In the case where a device does not have any MCS +instances and only GMCS, then GMCS will point to a generic instance. + +The Zephyr implementation of MCS and GMCS is incomplete, +and currently only supports instantiating a single instance that can either be an MCS or GMCS. +This means that the implementation is neither complete nor spec-compliant. + +Difference between GTBS and GMCS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The definitions and implementations of GTBS and GMCS as stated above are notably different. +GTBS works as a union between the other TBS instances (if any), +and GMCS works as a pointer to a specific MCS instance (if any). +This effectively means that a simple Call Control Client can control all calls just using GTBS, +but a Media Control Client may only be able to control a single player using GMCS. Coordinated Sets ---------------- From cd685bdce82d1d3843bcd56b67a086278e59e3e5 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Tue, 26 Mar 2024 16:15:31 -0700 Subject: [PATCH 1916/2402] doc: pm: Update system pm diagram Update system pm diagram to reflect recent changes in the subysystem. Use graphviz to create this new diagram. Signed-off-by: Flavio Ceolin --- doc/services/pm/images/system-pm.svg | 3 -- doc/services/pm/system.rst | 49 ++++++++++++++++++++++++++-- 2 files changed, 46 insertions(+), 6 deletions(-) delete mode 100644 doc/services/pm/images/system-pm.svg diff --git a/doc/services/pm/images/system-pm.svg b/doc/services/pm/images/system-pm.svg deleted file mode 100644 index 615052ae6b3..00000000000 --- a/doc/services/pm/images/system-pm.svg +++ /dev/null @@ -1,3 +0,0 @@ - - -
    Idle Thread
    Idle Thread    arch_irq_lock()pm_system_supspend (ticks)
    CONFIG_PM 
    CONFIG_PM 
    no
    no
    yes
    yes    k_cpu_idle()
    ACTIVE
    ACTIVE
    SUSPEND_TO_RAM
    or
    SUSPEND_TO_DISK
    or
    SOFT_OFF
    SUSPEND_TO_RAM...
    RUNTIME_IDLE
    or
    SUSPEND_TO_DILE
    or
    STANDBY
    RUNTIME_IDLE...
    pm_policy_next_state()
    pm_policy_next_state()
    pm_low_power_devices()
    pm_low_power_devices()
    pm_suspend_devices()
    pm_suspend_devices()
    k_schedule_lock()
    k_schedule_lock()
    pm_state_notify()
    pm_state_notify()
    CONFIG_PM_DEVICE
    CONFI...
    SoC Implementation
    SoC Implementation
    pm_state_notify()
    pm_state_notify()
    pm_power_state_set(state)
    pm_power_state_set(state)
    pm_resume_devices()
    pm_resume_devices()
    pm_state_exit_post_ops()
    pm_state_exit_post_ops()
    k_sched_unlock()
    k_sched_unlock()    Viewer does not support full SVG 1.1     \ No newline at end of file diff --git a/doc/services/pm/system.rst b/doc/services/pm/system.rst index b71b793c94d..f3e52b93d87 100644 --- a/doc/services/pm/system.rst +++ b/doc/services/pm/system.rst @@ -17,9 +17,52 @@ source. The following diagram describes system power management: -.. image:: images/system-pm.svg - :align: center - :alt: System power management +.. graphviz:: + :caption: System power management + + digraph G { + compound=true + node [height=1.2 style=rounded] + + lock [label="Lock interruptions"] + config_pm [label="CONFIG_PM" shape=diamond style="rounded,dashed"] + forced_state [label="state forced ?", shape=diamond style="rounded,dashed"] + config_system_managed_device_pm [label="CONFIG_PM_DEVICE" shape=diamond style="rounded,dashed"] + config_system_managed_device_pm2 [label="CONFIG_PM_DEVICE" shape=diamond style="rounded,dashed"] + pm_policy [label="Check policy manager\nfor a power state "] + pm_suspend_devices [label="Suspend\ndevices"] + pm_resume_devices [label="Resume\ndevices"] + pm_state_set [label="Change power state\n(SoC API)" style="rounded,bold"] + pm_system_resume [label="Finish wake-up\n(SoC API)\n(restore interruptions)" style="rounded,bold"] + k_cpu_idle [label="k_cpu_idle()"] + + subgraph cluster_0 { + style=invisible; + lock -> config_pm + } + + subgraph cluster_1 { + style=dashed + label = "pm_system_suspend()" + + forced_state -> config_system_managed_device_pm [label="yes"] + forced_state -> pm_policy [label="no"] + pm_policy -> config_system_managed_device_pm + config_system_managed_device_pm -> pm_state_set:e [label="no"] + config_system_managed_device_pm -> pm_suspend_devices [label="yes"] + pm_suspend_devices -> pm_state_set + pm_state_set -> config_system_managed_device_pm2 + config_system_managed_device_pm2 -> pm_resume_devices [label="yes"] + config_system_managed_device_pm2 -> pm_system_resume [label="no"] + pm_resume_devices -> pm_system_resume + } + + {rankdir=LR k_cpu_idle; forced_state} + pm_policy -> k_cpu_idle [label="PM_STATE_ACTIVE\n(no power state meet requirements)"] + config_pm -> k_cpu_idle [label="no"] + config_pm -> forced_state [label="yes" lhead="cluster_1"] + pm_system_resume:e -> lock:e [constraint=false lhed="cluster_0"] + } Some handful examples using different power management features: From 69e0b03ca97af2f2fd011aefcdf9a13d62212db8 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Wed, 3 Apr 2024 10:19:05 -0500 Subject: [PATCH 1917/2402] net: zperf_shell: Fix IPv6 invalid warning Fix the ipv6 invalid warning always appearing when a valid ipv4 address is provided. Signed-off-by: Declan Snyder --- subsys/net/lib/zperf/zperf_shell.c | 37 +++++++++++++++++++----------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/subsys/net/lib/zperf/zperf_shell.c b/subsys/net/lib/zperf/zperf_shell.c index d5c99da6be9..2bd37a476d1 100644 --- a/subsys/net/lib/zperf/zperf_shell.c +++ b/subsys/net/lib/zperf/zperf_shell.c @@ -163,9 +163,7 @@ static int parse_ipv6_addr(const struct shell *sh, char *host, char *port, ret = net_addr_pton(AF_INET6, host, &addr->sin6_addr); if (ret < 0) { - shell_fprintf(sh, SHELL_WARNING, - "Invalid IPv6 address %s\n", host); - return -EINVAL; + return -EDESTADDRREQ; } addr->sin6_port = htons(strtoul(port, NULL, 10)); @@ -189,9 +187,7 @@ static int parse_ipv4_addr(const struct shell *sh, char *host, char *port, ret = net_addr_pton(AF_INET, host, &addr->sin_addr); if (ret < 0) { - shell_fprintf(sh, SHELL_WARNING, - "Invalid IPv4 address %s\n", host); - return -EINVAL; + return -EDESTADDRREQ; } addr->sin_port = htons(strtoul(port, NULL, 10)); @@ -803,6 +799,7 @@ static int shell_cmd_upload(const struct shell *sh, size_t argc, bool is_udp; int start = 0; size_t opt_cnt = 0; + int ret; param.options.priority = -1; is_udp = proto == IPPROTO_UDP; @@ -907,8 +904,12 @@ static int shell_cmd_upload(const struct shell *sh, size_t argc, } if (IS_ENABLED(CONFIG_NET_IPV6) && !IS_ENABLED(CONFIG_NET_IPV4)) { - if (parse_ipv6_addr(sh, argv[start + 1], port_str, - &ipv6) < 0) { + ret = parse_ipv6_addr(sh, argv[start + 1], port_str, &ipv6); + if (ret == -EDESTADDRREQ) { + shell_fprintf(sh, SHELL_WARNING, + "Invalid IPv6 address %s\n", argv[start + 1]); + } + if (ret < 0) { shell_fprintf(sh, SHELL_WARNING, "Please specify the IP address of the " "remote server.\n"); @@ -922,8 +923,12 @@ static int shell_cmd_upload(const struct shell *sh, size_t argc, } if (IS_ENABLED(CONFIG_NET_IPV4) && !IS_ENABLED(CONFIG_NET_IPV6)) { - if (parse_ipv4_addr(sh, argv[start + 1], port_str, - &ipv4) < 0) { + ret = parse_ipv4_addr(sh, argv[start + 1], port_str, &ipv4); + if (ret == -EDESTADDRREQ) { + shell_fprintf(sh, SHELL_WARNING, + "Invalid IPv4 address %s\n", argv[start + 1]); + } + if (ret < 0) { shell_fprintf(sh, SHELL_WARNING, "Please specify the IP address of the " "remote server.\n"); @@ -937,10 +942,14 @@ static int shell_cmd_upload(const struct shell *sh, size_t argc, } if (IS_ENABLED(CONFIG_NET_IPV6) && IS_ENABLED(CONFIG_NET_IPV4)) { - if (parse_ipv6_addr(sh, argv[start + 1], port_str, - &ipv6) < 0) { - if (parse_ipv4_addr(sh, argv[start + 1], port_str, - &ipv4) < 0) { + ret = parse_ipv6_addr(sh, argv[start + 1], port_str, &ipv6); + if (ret < 0) { + ret = parse_ipv4_addr(sh, argv[start + 1], port_str, &ipv4); + if (ret == -EDESTADDRREQ) { + shell_fprintf(sh, SHELL_WARNING, + "Invalid IP address %s\n", argv[start + 1]); + } + if (ret < 0) { shell_fprintf(sh, SHELL_WARNING, "Please specify the IP address " "of the remote server.\n"); From 5f6a68a03b3b41b104b4e29efdcb7e7a1e87df44 Mon Sep 17 00:00:00 2001 From: Lukas Gehreke Date: Tue, 13 Feb 2024 17:17:18 +0100 Subject: [PATCH 1918/2402] drivers: flash: Added buffered write for addresses in flash on rp2040 It is impossible to perform flash reads during a flash write. When the data to write to flash lies in the flash itself, it is buffered in ram before writing. Signed-off-by: Lukas Gehreke --- drivers/flash/flash_rpi_pico.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/flash/flash_rpi_pico.c b/drivers/flash/flash_rpi_pico.c index e9a386b06a0..01ace5f68b5 100644 --- a/drivers/flash/flash_rpi_pico.c +++ b/drivers/flash/flash_rpi_pico.c @@ -61,6 +61,7 @@ enum outover { static ssi_hw_t *const ssi = (ssi_hw_t *)SSI_BASE_ADDRESS; static uint32_t boot2_copyout[BOOT2_SIZE_WORDS]; static bool boot2_copyout_valid; +static uint8_t flash_ram_buffer[PAGE_SIZE]; static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) { @@ -223,22 +224,25 @@ static int flash_rpi_write(const struct device *dev, off_t offset, const void *d if ((offset & (PAGE_SIZE - 1)) > 0) { bytes_to_write = MIN(PAGE_SIZE - (offset & (PAGE_SIZE - 1)), size); - flash_write_partial(offset, data_pointer, bytes_to_write); + memcpy(flash_ram_buffer, data_pointer, bytes_to_write); + flash_write_partial(offset, flash_ram_buffer, bytes_to_write); data_pointer += bytes_to_write; size -= bytes_to_write; offset += bytes_to_write; } - if (size >= PAGE_SIZE) { - bytes_to_write = size & ~(PAGE_SIZE - 1); - flash_range_program(offset, data_pointer, bytes_to_write); + while (size >= PAGE_SIZE) { + bytes_to_write = PAGE_SIZE; + memcpy(flash_ram_buffer, data_pointer, bytes_to_write); + flash_range_program(offset, flash_ram_buffer, bytes_to_write); data_pointer += bytes_to_write; size -= bytes_to_write; offset += bytes_to_write; } if (size > 0) { - flash_write_partial(offset, data_pointer, size); + memcpy(flash_ram_buffer, data_pointer, size); + flash_write_partial(offset, flash_ram_buffer, size); } irq_unlock(key); From a9afee1d12336ccdd09641c30d39efe4de05f588 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 3 Apr 2024 15:49:16 +0200 Subject: [PATCH 1919/2402] samples: use appropriate sys_randX_get() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use the appropriate sys_randX_get() instead of always sys_rand32_get(). Signed-off-by: Fin Maaß --- samples/arch/smp/pktqueue/src/main.c | 2 +- samples/bluetooth/peripheral_csc/src/main.c | 6 +++--- samples/net/cloud/mqtt_azure/src/main.c | 4 ++-- samples/net/mqtt_publisher/src/main.c | 4 ++-- samples/net/wpan_serial/src/main.c | 6 ++---- samples/subsys/usb/hid-cdc/src/main.c | 4 ++-- 6 files changed, 12 insertions(+), 14 deletions(-) diff --git a/samples/arch/smp/pktqueue/src/main.c b/samples/arch/smp/pktqueue/src/main.c index 07363a8d234..009cd2de966 100644 --- a/samples/arch/smp/pktqueue/src/main.c +++ b/samples/arch/smp/pktqueue/src/main.c @@ -45,7 +45,7 @@ void init_datagram_queue(struct phdr_desc_queue *queue, int queue_num) for (int j = 0; j < SIZE_OF_HEADER; j++) { /* leave crc field zeroed */ if (j < CRC_BYTE_1 || j > CRC_BYTE_2) { - descriptors[queue_num][i].ptr[j] = (uint8_t)sys_rand32_get(); + descriptors[queue_num][i].ptr[j] = sys_rand8_get(); } else { descriptors[queue_num][i].ptr[j] = 0; } diff --git a/samples/bluetooth/peripheral_csc/src/main.c b/samples/bluetooth/peripheral_csc/src/main.c index eba60137097..d6a2f3d01e5 100644 --- a/samples/bluetooth/peripheral_csc/src/main.c +++ b/samples/bluetooth/peripheral_csc/src/main.c @@ -304,18 +304,18 @@ static uint16_t lcet; /* Last Crank Event Time */ static void csc_simulation(void) { static uint8_t i; - uint32_t rand = sys_rand32_get(); + uint8_t rnd = sys_rand8_get(); bool nfy_crank = false, nfy_wheel = false; /* Measurements don't have to be updated every second */ if (!(i % 2)) { - lwet += 1050 + rand % 50; + lwet += 1050 + rnd % 50; c_wheel_revs += 2U; nfy_wheel = true; } if (!(i % 3)) { - lcet += 1000 + rand % 50; + lcet += 1000 + rnd % 50; ccr += 1U; nfy_crank = true; } diff --git a/samples/net/cloud/mqtt_azure/src/main.c b/samples/net/cloud/mqtt_azure/src/main.c index 75590b5065d..46ee6c66820 100644 --- a/samples/net/cloud/mqtt_azure/src/main.c +++ b/samples/net/cloud/mqtt_azure/src/main.c @@ -298,7 +298,7 @@ static int publish(struct mqtt_client *client, enum mqtt_qos qos) param.message.topic.topic.size = len; param.message.payload.data = payload; param.message.payload.len = strlen(payload); - param.message_id = sys_rand32_get(); + param.message_id = sys_rand16_get(); param.dup_flag = 0U; param.retain_flag = 0U; @@ -324,7 +324,7 @@ static void poll_mqtt(void) */ static uint8_t timeout_for_publish(void) { - return (10 + sys_rand32_get() % 5); + return (10 + sys_rand8_get() % 5); } static void publish_timeout(struct k_work *work) diff --git a/samples/net/mqtt_publisher/src/main.c b/samples/net/mqtt_publisher/src/main.c index 2d8408d1191..231c9c2b2f3 100644 --- a/samples/net/mqtt_publisher/src/main.c +++ b/samples/net/mqtt_publisher/src/main.c @@ -219,7 +219,7 @@ static char *get_mqtt_payload(enum mqtt_qos qos) static APP_BMEM char payload[30]; snprintk(payload, sizeof(payload), "{d:{temperature:%d}}", - (uint8_t)sys_rand32_get()); + sys_rand8_get()); #else static APP_DMEM char payload[] = "DOORS:OPEN_QoSx"; @@ -250,7 +250,7 @@ static int publish(struct mqtt_client *client, enum mqtt_qos qos) param.message.payload.data = get_mqtt_payload(qos); param.message.payload.len = strlen(param.message.payload.data); - param.message_id = sys_rand32_get(); + param.message_id = sys_rand16_get(); param.dup_flag = 0U; param.retain_flag = 0U; diff --git a/samples/net/wpan_serial/src/main.c b/samples/net/wpan_serial/src/main.c index 04b98a449bb..2f589aa33de 100644 --- a/samples/net/wpan_serial/src/main.c +++ b/samples/net/wpan_serial/src/main.c @@ -448,14 +448,12 @@ static void init_tx_queue(void) */ static uint8_t *get_mac(const struct device *dev) { - uint32_t *ptr = (uint32_t *)mac_addr; - mac_addr[7] = 0x00; mac_addr[6] = 0x12; mac_addr[5] = 0x4b; - mac_addr[4] = 0x00; - UNALIGNED_PUT(sys_rand32_get(), ptr); + + sys_rand_get(mac_addr, 4U); mac_addr[0] = (mac_addr[0] & ~0x01) | 0x02; diff --git a/samples/subsys/usb/hid-cdc/src/main.c b/samples/subsys/usb/hid-cdc/src/main.c index 7e06a2c5d0b..936afb76f0a 100644 --- a/samples/subsys/usb/hid-cdc/src/main.c +++ b/samples/subsys/usb/hid-cdc/src/main.c @@ -652,8 +652,8 @@ int main(void) case GPIO_BUTTON_0: { /* Move the mouse in random direction */ - uint8_t rep[] = {0x00, sys_rand32_get(), - sys_rand32_get(), 0x00}; + uint8_t rep[] = {0x00, sys_rand8_get(), + sys_rand8_get(), 0x00}; k_sem_take(&usb_sem, K_FOREVER); hid_int_ep_write(hid0_dev, rep, From e3549278952e6f0d271d50a3785a8ce40ac0fcf5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 3 Apr 2024 16:06:05 +0200 Subject: [PATCH 1920/2402] tests: use appropriate sys_randX_get() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit use the appropriate sys_randX_get() instead of always sys_rand32_get(). Signed-off-by: Fin Maaß --- subsys/testsuite/ztest/src/ztress.c | 2 +- tests/benchmarks/mbedtls/src/benchmark.c | 16 +--------------- tests/crypto/tinycrypt/src/ecc_dsa.c | 9 +-------- tests/drivers/smbus/smbus_emul/src/smbus.c | 16 ++++++---------- tests/drivers/uart/uart_mix_fifo_poll/src/main.c | 2 +- tests/lib/p4workq/src/main.c | 2 +- tests/lib/spsc_pbuf/src/main.c | 10 +++++----- tests/net/arp/src/main.c | 2 +- tests/net/checksum_offload/src/main.c | 2 +- tests/net/context/src/main.c | 2 +- tests/net/hostname/src/main.c | 4 ++-- tests/net/iface/src/main.c | 2 +- tests/net/igmp/src/main.c | 2 +- tests/net/ip-addr/src/main.c | 2 +- tests/net/ipv6/src/main.c | 4 ++-- tests/net/ipv6_fragment/src/main.c | 2 +- tests/net/lib/dns_addremove/src/main.c | 2 +- tests/net/lib/dns_resolve/src/main.c | 2 +- .../lib/mqtt_publisher/src/test_mqtt_publish.c | 2 +- tests/net/lib/mqtt_pubsub/src/test_mqtt_pubsub.c | 6 +++--- .../mqtt_subscriber/src/test_mqtt_subscribe.c | 4 ++-- tests/net/mld/src/main.c | 2 +- tests/net/net_pkt/src/main.c | 2 +- tests/net/pm/src/main.c | 2 +- tests/net/ptp/clock/src/main.c | 2 +- tests/net/route/src/main.c | 4 ++-- tests/net/route_mcast/src/main.c | 2 +- tests/net/shell/src/main.c | 2 +- .../net/socket/af_packet_ipproto_raw/src/main.c | 2 +- tests/net/traffic_class/src/main.c | 2 +- tests/net/tx_timestamp/src/main.c | 2 +- tests/net/udp/src/main.c | 2 +- tests/net/virtual/src/main.c | 8 ++++---- tests/net/vlan/src/main.c | 4 ++-- tests/net/wifi/wifi_nm/src/main.c | 2 +- tests/subsys/ipc/pbuf/src/main.c | 6 +++--- tests/subsys/logging/log_stress/src/main.c | 2 +- 37 files changed, 58 insertions(+), 83 deletions(-) diff --git a/subsys/testsuite/ztest/src/ztress.c b/subsys/testsuite/ztest/src/ztress.c index 0ca15b0fc96..ce8b31a5a2d 100644 --- a/subsys/testsuite/ztest/src/ztress.c +++ b/subsys/testsuite/ztest/src/ztress.c @@ -216,7 +216,7 @@ static k_timeout_t randomize_t(k_timeout_t t) static void microdelay(void) { static volatile int microdelay_cnt; - uint32_t repeat = sys_rand32_get() & 0xff; + uint8_t repeat = sys_rand8_get(); for (int i = 0; i < repeat; i++) { microdelay_cnt++; diff --git a/tests/benchmarks/mbedtls/src/benchmark.c b/tests/benchmarks/mbedtls/src/benchmark.c index 12bc3cdc3d5..0694eea1eee 100644 --- a/tests/benchmarks/mbedtls/src/benchmark.c +++ b/tests/benchmarks/mbedtls/src/benchmark.c @@ -244,25 +244,11 @@ do { \ static int myrand(void *rng_state, unsigned char *output, size_t len) { - size_t use_len; - int rnd; - if (rng_state != NULL) { rng_state = NULL; } - while (len > 0) { - use_len = len; - - if (use_len > sizeof(int)) { - use_len = sizeof(int); - } - - rnd = sys_rand32_get(); - memcpy(output, &rnd, use_len); - output += use_len; - len -= use_len; - } + sys_rand_get(output, len); return(0); } diff --git a/tests/crypto/tinycrypt/src/ecc_dsa.c b/tests/crypto/tinycrypt/src/ecc_dsa.c index f62f63c77dc..4423bdfa542 100644 --- a/tests/crypto/tinycrypt/src/ecc_dsa.c +++ b/tests/crypto/tinycrypt/src/ecc_dsa.c @@ -616,14 +616,7 @@ int default_CSPRNG(uint8_t *dest, unsigned int size) /* This is not a CSPRNG, but it's the only thing available in the * system at this point in time. */ - while (size) { - uint32_t len = size >= sizeof(uint32_t) ? sizeof(uint32_t) : size; - uint32_t rv = sys_rand32_get(); - - memcpy(dest, &rv, len); - dest += len; - size -= len; - } + sys_rand_get(dest, size); return 1; } diff --git a/tests/drivers/smbus/smbus_emul/src/smbus.c b/tests/drivers/smbus/smbus_emul/src/smbus.c index 9a96722684d..fee5a18b449 100644 --- a/tests/drivers/smbus/smbus_emul/src/smbus.c +++ b/tests/drivers/smbus/smbus_emul/src/smbus.c @@ -113,7 +113,7 @@ ZTEST(test_smbus_emul, test_byte) ret = smbus_quick(dev, PERIPH_ADDR, 1); zassert_ok(ret, "SMBus Quick failed"); - snd_byte = (uint8_t)sys_rand32_get(); + snd_byte = sys_rand8_get(); ret = smbus_byte_write(dev, PERIPH_ADDR, snd_byte); zassert_ok(ret, "SMBus Byte Write failed"); @@ -141,7 +141,7 @@ ZTEST(test_smbus_emul, test_word) zassert_not_null(dev, "Device not found"); - snd_word = (uint16_t)sys_rand32_get(); + snd_word = sys_rand16_get(); ret = smbus_word_data_write(dev, PERIPH_ADDR, 0, snd_word); zassert_ok(ret, "SMBus Word Data Write failed"); @@ -153,7 +153,7 @@ ZTEST(test_smbus_emul, test_word) /* Test 2 byte writes following word read */ - snd_byte = (uint8_t)sys_rand32_get(); + snd_byte = sys_rand8_get(); ret = smbus_byte_data_write(dev, PERIPH_ADDR, 0, snd_byte); zassert_ok(ret, "SMBus Byte Data Write failed"); @@ -174,7 +174,7 @@ ZTEST(test_smbus_emul, test_proc_call) zassert_not_null(dev, "Device not found"); - snd_word = (uint16_t)sys_rand32_get(); + snd_word = sys_rand16_get(); zassert_not_equal(snd_word, 0, "Random number generator misconfgured"); ret = smbus_pcall(dev, PERIPH_ADDR, 0x0, snd_word, &rcv_word); @@ -194,9 +194,7 @@ ZTEST(test_smbus_emul, test_block) zassert_not_null(dev, "Device not found"); - for (int i = 0; i < sizeof(snd_block); i++) { - snd_block[i] = (uint8_t)sys_rand32_get(); - } + sys_rand_get(snd_block, sizeof(snd_block)); snd_count = sizeof(snd_block); @@ -221,9 +219,7 @@ ZTEST(test_smbus_emul, test_block_pcall) zassert_not_null(dev, "Device not found"); - for (int i = 0; i < sizeof(snd_block); i++) { - snd_block[i] = (uint8_t)sys_rand32_get(); - } + sys_rand_get(snd_block, sizeof(snd_block)); snd_count = SMBUS_BLOCK_BYTES_MAX / 2; ret = smbus_block_pcall(dev, PERIPH_ADDR, 0, snd_count, snd_block, diff --git a/tests/drivers/uart/uart_mix_fifo_poll/src/main.c b/tests/drivers/uart/uart_mix_fifo_poll/src/main.c index 2f38354d21e..eaebe8e132e 100644 --- a/tests/drivers/uart/uart_mix_fifo_poll/src/main.c +++ b/tests/drivers/uart/uart_mix_fifo_poll/src/main.c @@ -294,7 +294,7 @@ static void poll_out_timer_handler(struct k_timer *timer) k_timer_stop(timer); k_sem_give(&data->sem); } else { - k_timer_start(timer, K_USEC(250 + (sys_rand32_get() % 800)), + k_timer_start(timer, K_USEC(250 + (sys_rand16_get() % 800)), K_NO_WAIT); } } diff --git a/tests/lib/p4workq/src/main.c b/tests/lib/p4workq/src/main.c index 9567acd5def..2e5ca14fac1 100644 --- a/tests/lib/p4workq/src/main.c +++ b/tests/lib/p4workq/src/main.c @@ -72,7 +72,7 @@ static void stress_handler(struct k_p4wq_work *item) /* Pick 0-3 random item slots and submit them if they aren't * already. Make sure we always have at least one active. */ - int num_tries = sys_rand32_get() % 4; + int num_tries = sys_rand8_get() % 4; for (int i = 0; (active_items == 0) || (i < num_tries); i++) { int ii = sys_rand32_get() % MAX_ITEMS; diff --git a/tests/lib/spsc_pbuf/src/main.c b/tests/lib/spsc_pbuf/src/main.c index 55edbc65ede..7a0a74d5137 100644 --- a/tests/lib/spsc_pbuf/src/main.c +++ b/tests/lib/spsc_pbuf/src/main.c @@ -424,7 +424,7 @@ bool stress_read(void *user_data, uint32_t cnt, bool last, int prio) struct stress_data *ctx = (struct stress_data *)user_data; char buf[128]; int len; - int rpt = (sys_rand32_get() & 3) + 1; + int rpt = (sys_rand8_get() & 3) + 1; for (int i = 0; i < rpt; i++) { len = spsc_pbuf_read(ctx->pbuf, buf, (uint16_t)sizeof(buf)); @@ -447,8 +447,8 @@ bool stress_write(void *user_data, uint32_t cnt, bool last, int prio) { struct stress_data *ctx = (struct stress_data *)user_data; char buf[128]; - uint16_t len = 1 + (sys_rand32_get() % (ctx->capacity / 4)); - int rpt = (sys_rand32_get() & 1) + 1; + uint16_t len = 1 + (sys_rand16_get() % (ctx->capacity / 4)); + int rpt = (sys_rand8_get() & 1) + 1; zassert_true(len < sizeof(buf), "len:%d %d", len, ctx->capacity); @@ -490,7 +490,7 @@ bool stress_claim_free(void *user_data, uint32_t cnt, bool last, int prio) struct stress_data *ctx = (struct stress_data *)user_data; char *buf; uint16_t len; - int rpt = sys_rand32_get() % 0x3; + int rpt = sys_rand8_get() % 0x3; for (int i = 0; i < rpt; i++) { len = spsc_pbuf_claim(ctx->pbuf, &buf); @@ -512,7 +512,7 @@ bool stress_claim_free(void *user_data, uint32_t cnt, bool last, int prio) bool stress_alloc_commit(void *user_data, uint32_t cnt, bool last, int prio) { struct stress_data *ctx = (struct stress_data *)user_data; - uint32_t rnd = sys_rand32_get(); + uint16_t rnd = sys_rand16_get(); uint16_t len = 1 + (rnd % (ctx->capacity / 4)); int rpt = rnd % 0x3; char *buf; diff --git a/tests/net/arp/src/main.c b/tests/net/arp/src/main.c index 9a94c488215..022abfb54c2 100644 --- a/tests/net/arp/src/main.c +++ b/tests/net/arp/src/main.c @@ -70,7 +70,7 @@ static uint8_t *net_arp_get_mac(const struct device *dev) context->mac_addr[2] = 0x5E; context->mac_addr[3] = 0x00; context->mac_addr[4] = 0x53; - context->mac_addr[5] = sys_rand32_get(); + context->mac_addr[5] = sys_rand8_get(); } return context->mac_addr; diff --git a/tests/net/checksum_offload/src/main.c b/tests/net/checksum_offload/src/main.c index 978488ad298..b41158f4ec3 100644 --- a/tests/net/checksum_offload/src/main.c +++ b/tests/net/checksum_offload/src/main.c @@ -446,7 +446,7 @@ static void generate_mac(uint8_t *mac_addr) mac_addr[2] = 0x5E; mac_addr[3] = 0x00; mac_addr[4] = 0x53; - mac_addr[5] = sys_rand32_get(); + mac_addr[5] = sys_rand8_get(); } static int eth_init(const struct device *dev) diff --git a/tests/net/context/src/main.c b/tests/net/context/src/main.c index e3596f236c8..793ce6022a8 100644 --- a/tests/net/context/src/main.c +++ b/tests/net/context/src/main.c @@ -983,7 +983,7 @@ static uint8_t *net_context_get_mac(const struct device *dev) context->mac_addr[2] = 0x5E; context->mac_addr[3] = 0x00; context->mac_addr[4] = 0x53; - context->mac_addr[5] = sys_rand32_get(); + context->mac_addr[5] = sys_rand8_get(); } return context->mac_addr; diff --git a/tests/net/hostname/src/main.c b/tests/net/hostname/src/main.c index 679018de7ad..1f007db4807 100644 --- a/tests/net/hostname/src/main.c +++ b/tests/net/hostname/src/main.c @@ -82,7 +82,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev) data->mac_addr[2] = 0x5E; data->mac_addr[3] = 0x00; data->mac_addr[4] = 0x53; - data->mac_addr[5] = sys_rand32_get(); + data->mac_addr[5] = sys_rand8_get(); } data->ll_addr.addr = data->mac_addr; @@ -173,7 +173,7 @@ static void eth_fake_iface_init(struct net_if *iface) ctx->mac_address[2] = 0x5E; ctx->mac_address[3] = 0x00; ctx->mac_address[4] = 0x53; - ctx->mac_address[5] = sys_rand32_get(); + ctx->mac_address[5] = sys_rand8_get(); net_if_set_link_addr(iface, ctx->mac_address, sizeof(ctx->mac_address), diff --git a/tests/net/iface/src/main.c b/tests/net/iface/src/main.c index bf9c577037c..2d1be245b87 100644 --- a/tests/net/iface/src/main.c +++ b/tests/net/iface/src/main.c @@ -88,7 +88,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev) data->mac_addr[2] = 0x5E; data->mac_addr[3] = 0x00; data->mac_addr[4] = 0x53; - data->mac_addr[5] = sys_rand32_get(); + data->mac_addr[5] = sys_rand8_get(); } data->ll_addr.addr = data->mac_addr; diff --git a/tests/net/igmp/src/main.c b/tests/net/igmp/src/main.c index d6f3ce7e7cd..703a058dbe2 100644 --- a/tests/net/igmp/src/main.c +++ b/tests/net/igmp/src/main.c @@ -84,7 +84,7 @@ static uint8_t *net_test_get_mac(const struct device *dev) context->mac_addr[2] = 0x5E; context->mac_addr[3] = 0x00; context->mac_addr[4] = 0x53; - context->mac_addr[5] = sys_rand32_get(); + context->mac_addr[5] = sys_rand8_get(); } return context->mac_addr; diff --git a/tests/net/ip-addr/src/main.c b/tests/net/ip-addr/src/main.c index 30ef20cd6c2..9d98c540515 100644 --- a/tests/net/ip-addr/src/main.c +++ b/tests/net/ip-addr/src/main.c @@ -129,7 +129,7 @@ static uint8_t *net_test_get_mac(const struct device *dev) context->mac_addr[2] = 0x5E; context->mac_addr[3] = 0x00; context->mac_addr[4] = 0x53; - context->mac_addr[5] = sys_rand32_get(); + context->mac_addr[5] = sys_rand8_get(); } return context->mac_addr; diff --git a/tests/net/ipv6/src/main.c b/tests/net/ipv6/src/main.c index f9ca6832009..06939fb47d5 100644 --- a/tests/net/ipv6/src/main.c +++ b/tests/net/ipv6/src/main.c @@ -169,7 +169,7 @@ static uint8_t *net_test_get_mac(const struct device *dev) context->mac_addr[2] = 0x5E; context->mac_addr[3] = 0x00; context->mac_addr[4] = 0x53; - context->mac_addr[5] = sys_rand32_get(); + context->mac_addr[5] = sys_rand8_get(); } return context->mac_addr; @@ -1179,7 +1179,7 @@ ZTEST(net_ipv6, test_change_ll_addr) ll_iface->addr[2] = 0x5E; ll_iface->addr[3] = 0x00; ll_iface->addr[4] = 0x53; - ll_iface->addr[5] = sys_rand32_get(); + ll_iface->addr[5] = sys_rand8_get(); } ZTEST(net_ipv6, test_dad_timeout) diff --git a/tests/net/ipv6_fragment/src/main.c b/tests/net/ipv6_fragment/src/main.c index adb8652bdc1..702723a5883 100644 --- a/tests/net/ipv6_fragment/src/main.c +++ b/tests/net/ipv6_fragment/src/main.c @@ -938,7 +938,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev) data->mac_addr[2] = 0x5E; data->mac_addr[3] = 0x00; data->mac_addr[4] = 0x53; - data->mac_addr[5] = sys_rand32_get(); + data->mac_addr[5] = sys_rand8_get(); } data->ll_addr.addr = data->mac_addr; diff --git a/tests/net/lib/dns_addremove/src/main.c b/tests/net/lib/dns_addremove/src/main.c index 6d992776800..5d8d227dff9 100644 --- a/tests/net/lib/dns_addremove/src/main.c +++ b/tests/net/lib/dns_addremove/src/main.c @@ -91,7 +91,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev) data->mac_addr[2] = 0x5E; data->mac_addr[3] = 0x00; data->mac_addr[4] = 0x53; - data->mac_addr[5] = sys_rand32_get(); + data->mac_addr[5] = sys_rand8_get(); } return data->mac_addr; diff --git a/tests/net/lib/dns_resolve/src/main.c b/tests/net/lib/dns_resolve/src/main.c index 39e7d286dfb..cc56a7821a2 100644 --- a/tests/net/lib/dns_resolve/src/main.c +++ b/tests/net/lib/dns_resolve/src/main.c @@ -89,7 +89,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev) data->mac_addr[2] = 0x5E; data->mac_addr[3] = 0x00; data->mac_addr[4] = 0x53; - data->mac_addr[5] = sys_rand32_get(); + data->mac_addr[5] = sys_rand8_get(); } data->ll_addr.addr = data->mac_addr; diff --git a/tests/net/lib/mqtt_publisher/src/test_mqtt_publish.c b/tests/net/lib/mqtt_publisher/src/test_mqtt_publish.c index 32dda35a78c..dc9a5c757ec 100644 --- a/tests/net/lib/mqtt_publisher/src/test_mqtt_publish.c +++ b/tests/net/lib/mqtt_publisher/src/test_mqtt_publish.c @@ -193,7 +193,7 @@ static int publish(enum mqtt_qos qos) param.message.payload.data = get_mqtt_payload(qos); param.message.payload.len = strlen(param.message.payload.data); - param.message_id = sys_rand32_get(); + param.message_id = sys_rand16_get(); param.dup_flag = 0U; param.retain_flag = 0U; diff --git a/tests/net/lib/mqtt_pubsub/src/test_mqtt_pubsub.c b/tests/net/lib/mqtt_pubsub/src/test_mqtt_pubsub.c index 606ab78a0ba..27c466ea4d4 100644 --- a/tests/net/lib/mqtt_pubsub/src/test_mqtt_pubsub.c +++ b/tests/net/lib/mqtt_pubsub/src/test_mqtt_pubsub.c @@ -325,7 +325,7 @@ static int test_subscribe(void) topic.qos = MQTT_QOS_1_AT_LEAST_ONCE; sub.list = &topic; sub.list_count = 1U; - sub.message_id = sys_rand32_get(); + sub.message_id = sys_rand16_get(); rc = mqtt_subscribe(&client_ctx, &sub); if (rc != 0) { @@ -354,7 +354,7 @@ static int test_publish(enum mqtt_qos qos) strlen(param.message.topic.topic.utf8); param.message.payload.data = (uint8_t *)payload; param.message.payload.len = payload_left; - param.message_id = sys_rand32_get(); + param.message_id = sys_rand16_get(); param.dup_flag = 0U; param.retain_flag = 0U; @@ -388,7 +388,7 @@ static int test_unsubscribe(void) topic.topic.size = strlen(topic.topic.utf8); unsub.list = &topic; unsub.list_count = 1U; - unsub.message_id = sys_rand32_get(); + unsub.message_id = sys_rand16_get(); rc = mqtt_unsubscribe(&client_ctx, &unsub); if (rc != 0) { diff --git a/tests/net/lib/mqtt_subscriber/src/test_mqtt_subscribe.c b/tests/net/lib/mqtt_subscriber/src/test_mqtt_subscribe.c index ad09e8ecd96..95830e1b9bb 100644 --- a/tests/net/lib/mqtt_subscriber/src/test_mqtt_subscribe.c +++ b/tests/net/lib/mqtt_subscriber/src/test_mqtt_subscribe.c @@ -251,7 +251,7 @@ static int test_subscribe(void) topic.qos = MQTT_QOS_1_AT_LEAST_ONCE; sub.list = &topic; sub.list_count = 1U; - sub.message_id = sys_rand32_get(); + sub.message_id = sys_rand16_get(); rc = mqtt_subscribe(&client_ctx, &sub); if (rc != 0) { @@ -274,7 +274,7 @@ static int test_unsubscribe(void) topic.topic.size = strlen(topic.topic.utf8); unsub.list = &topic; unsub.list_count = 1U; - unsub.message_id = sys_rand32_get(); + unsub.message_id = sys_rand16_get(); rc = mqtt_unsubscribe(&client_ctx, &unsub); if (rc != 0) { diff --git a/tests/net/mld/src/main.c b/tests/net/mld/src/main.c index 25d3c715a87..9ca53f6bf31 100644 --- a/tests/net/mld/src/main.c +++ b/tests/net/mld/src/main.c @@ -87,7 +87,7 @@ static uint8_t *net_test_get_mac(const struct device *dev) context->mac_addr[2] = 0x5E; context->mac_addr[3] = 0x00; context->mac_addr[4] = 0x53; - context->mac_addr[5] = sys_rand32_get(); + context->mac_addr[5] = sys_rand8_get(); } return context->mac_addr; diff --git a/tests/net/net_pkt/src/main.c b/tests/net/net_pkt/src/main.c index 596361842c3..73e20fba51a 100644 --- a/tests/net/net_pkt/src/main.c +++ b/tests/net/net_pkt/src/main.c @@ -35,7 +35,7 @@ static void fake_dev_iface_init(struct net_if *iface) mac_addr[2] = 0x5E; mac_addr[3] = 0x00; mac_addr[4] = 0x53; - mac_addr[5] = sys_rand32_get(); + mac_addr[5] = sys_rand8_get(); } net_if_set_link_addr(iface, mac_addr, 6, NET_LINK_ETHERNET); diff --git a/tests/net/pm/src/main.c b/tests/net/pm/src/main.c index 02faa1c502c..17078406a4d 100644 --- a/tests/net/pm/src/main.c +++ b/tests/net/pm/src/main.c @@ -66,7 +66,7 @@ static uint8_t *fake_dev_get_mac(struct fake_dev_context *ctx) ctx->mac_addr[2] = 0x5E; ctx->mac_addr[3] = 0x00; ctx->mac_addr[4] = 0x53; - ctx->mac_addr[5] = sys_rand32_get(); + ctx->mac_addr[5] = sys_rand8_get(); } return ctx->mac_addr; diff --git a/tests/net/ptp/clock/src/main.c b/tests/net/ptp/clock/src/main.c index a00f3e0c540..03a1e970b9e 100644 --- a/tests/net/ptp/clock/src/main.c +++ b/tests/net/ptp/clock/src/main.c @@ -147,7 +147,7 @@ static void generate_mac(uint8_t *mac_addr) mac_addr[2] = 0x5E; mac_addr[3] = 0x00; mac_addr[4] = 0x53; - mac_addr[5] = sys_rand32_get(); + mac_addr[5] = sys_rand8_get(); } static int eth_init(const struct device *dev) diff --git a/tests/net/route/src/main.c b/tests/net/route/src/main.c index 1a48dd2ebc3..276bdc9a248 100644 --- a/tests/net/route/src/main.c +++ b/tests/net/route/src/main.c @@ -113,7 +113,7 @@ static uint8_t *net_route_get_mac(const struct device *dev) route->mac_addr[2] = 0x5E; route->mac_addr[3] = 0x00; route->mac_addr[4] = 0x53; - route->mac_addr[5] = sys_rand32_get(); + route->mac_addr[5] = sys_rand8_get(); } route->ll_addr.addr = route->mac_addr; @@ -285,7 +285,7 @@ static void test_init(void) sizeof(struct in6_addr)); dest_addresses[i].s6_addr[14] = i + 1; - dest_addresses[i].s6_addr[15] = sys_rand32_get(); + dest_addresses[i].s6_addr[15] = sys_rand8_get(); } } diff --git a/tests/net/route_mcast/src/main.c b/tests/net/route_mcast/src/main.c index 3db8a05fc0b..7b6eaab4f5f 100644 --- a/tests/net/route_mcast/src/main.c +++ b/tests/net/route_mcast/src/main.c @@ -154,7 +154,7 @@ static uint8_t *net_route_mcast_get_mac(const struct device *dev) cfg->mac_addr[2] = 0x5E; cfg->mac_addr[3] = 0x00; cfg->mac_addr[4] = 0x53; - cfg->mac_addr[5] = sys_rand32_get(); + cfg->mac_addr[5] = sys_rand8_get(); } cfg->ll_addr.addr = cfg->mac_addr; diff --git a/tests/net/shell/src/main.c b/tests/net/shell/src/main.c index af61dfd750f..f7bb1a6437a 100644 --- a/tests/net/shell/src/main.c +++ b/tests/net/shell/src/main.c @@ -78,7 +78,7 @@ static uint8_t *net_udp_get_mac(const struct device *dev) context->mac_addr[2] = 0x5E; context->mac_addr[3] = 0x00; context->mac_addr[4] = 0x53; - context->mac_addr[5] = sys_rand32_get(); + context->mac_addr[5] = sys_rand8_get(); } return context->mac_addr; diff --git a/tests/net/socket/af_packet_ipproto_raw/src/main.c b/tests/net/socket/af_packet_ipproto_raw/src/main.c index 15d2a047d41..9eace58bf13 100644 --- a/tests/net/socket/af_packet_ipproto_raw/src/main.c +++ b/tests/net/socket/af_packet_ipproto_raw/src/main.c @@ -56,7 +56,7 @@ static uint8_t *fake_dev_get_mac(struct fake_dev_context *ctx) ctx->mac_addr[2] = 0x5E; ctx->mac_addr[3] = 0x00; ctx->mac_addr[4] = 0x53; - ctx->mac_addr[5] = sys_rand32_get(); + ctx->mac_addr[5] = sys_rand8_get(); } return ctx->mac_addr; diff --git a/tests/net/traffic_class/src/main.c b/tests/net/traffic_class/src/main.c index 6187e124401..cc07c6173f7 100644 --- a/tests/net/traffic_class/src/main.c +++ b/tests/net/traffic_class/src/main.c @@ -254,7 +254,7 @@ static void generate_mac(uint8_t *mac_addr) mac_addr[2] = 0x5E; mac_addr[3] = 0x00; mac_addr[4] = 0x53; - mac_addr[5] = sys_rand32_get(); + mac_addr[5] = sys_rand8_get(); } static int eth_init(const struct device *dev) diff --git a/tests/net/tx_timestamp/src/main.c b/tests/net/tx_timestamp/src/main.c index 13561c53730..4b072d1525a 100644 --- a/tests/net/tx_timestamp/src/main.c +++ b/tests/net/tx_timestamp/src/main.c @@ -141,7 +141,7 @@ static void generate_mac(uint8_t *mac_addr) mac_addr[2] = 0x5E; mac_addr[3] = 0x00; mac_addr[4] = 0x53; - mac_addr[5] = sys_rand32_get(); + mac_addr[5] = sys_rand8_get(); } static int eth_init(const struct device *dev) diff --git a/tests/net/udp/src/main.c b/tests/net/udp/src/main.c index 452db57ebb0..e87269d8295 100644 --- a/tests/net/udp/src/main.c +++ b/tests/net/udp/src/main.c @@ -80,7 +80,7 @@ static uint8_t *net_udp_get_mac(const struct device *dev) context->mac_addr[2] = 0x5E; context->mac_addr[3] = 0x00; context->mac_addr[4] = 0x53; - context->mac_addr[5] = sys_rand32_get(); + context->mac_addr[5] = sys_rand8_get(); } return context->mac_addr; diff --git a/tests/net/virtual/src/main.c b/tests/net/virtual/src/main.c index 11eaf6bc6ad..57b0e8becea 100644 --- a/tests/net/virtual/src/main.c +++ b/tests/net/virtual/src/main.c @@ -175,7 +175,7 @@ static void generate_mac(uint8_t *mac_addr) mac_addr[2] = 0x5E; mac_addr[3] = 0x00; mac_addr[4] = 0x53; - mac_addr[5] = sys_rand32_get(); + mac_addr[5] = sys_rand8_get(); } static int eth_init(const struct device *dev) @@ -209,7 +209,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev) data->mac_addr[2] = 0x5E; data->mac_addr[3] = 0x00; data->mac_addr[4] = 0x53; - data->mac_addr[5] = sys_rand32_get(); + data->mac_addr[5] = sys_rand8_get(); } data->ll_addr.addr = data->mac_addr; @@ -533,12 +533,12 @@ static bool add_to_arp(struct net_if *iface, struct in_addr *addr) #if defined(CONFIG_NET_ARP) struct net_eth_addr lladdr; - lladdr.addr[0] = sys_rand32_get(); + lladdr.addr[0] = sys_rand8_get(); lladdr.addr[1] = 0x08; lladdr.addr[2] = 0x09; lladdr.addr[3] = 0x10; lladdr.addr[4] = 0x11; - lladdr.addr[5] = sys_rand32_get(); + lladdr.addr[5] = sys_rand8_get(); return arp_add(iface, addr, &lladdr); #else diff --git a/tests/net/vlan/src/main.c b/tests/net/vlan/src/main.c index b9eada2a627..e739af7dd12 100644 --- a/tests/net/vlan/src/main.c +++ b/tests/net/vlan/src/main.c @@ -179,7 +179,7 @@ static void generate_mac(uint8_t *mac_addr) mac_addr[2] = 0x5E; mac_addr[3] = 0x00; mac_addr[4] = 0x53; - mac_addr[5] = sys_rand32_get(); + mac_addr[5] = sys_rand8_get(); } static int eth_vlan_init(const struct device *dev) @@ -225,7 +225,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev) data->mac_addr[2] = 0x5E; data->mac_addr[3] = 0x00; data->mac_addr[4] = 0x53; - data->mac_addr[5] = sys_rand32_get(); + data->mac_addr[5] = sys_rand8_get(); data->ll_addr.addr = data->mac_addr; data->ll_addr.len = 6U; diff --git a/tests/net/wifi/wifi_nm/src/main.c b/tests/net/wifi/wifi_nm/src/main.c index 43fcee530ec..fb67601823d 100644 --- a/tests/net/wifi/wifi_nm/src/main.c +++ b/tests/net/wifi/wifi_nm/src/main.c @@ -87,7 +87,7 @@ static void generate_mac(uint8_t *mac_addr) mac_addr[2] = 0x5E; mac_addr[3] = 0x00; mac_addr[4] = 0x53; - mac_addr[5] = sys_rand32_get(); + mac_addr[5] = sys_rand8_get(); } static int wifi_init(const struct device *dev) diff --git a/tests/subsys/ipc/pbuf/src/main.c b/tests/subsys/ipc/pbuf/src/main.c index 7a20fc9bdd6..d4bbb9db4fe 100644 --- a/tests/subsys/ipc/pbuf/src/main.c +++ b/tests/subsys/ipc/pbuf/src/main.c @@ -211,7 +211,7 @@ bool stress_read(void *user_data, uint32_t cnt, bool last, int prio) struct stress_data *ctx = (struct stress_data *)user_data; char buf[STRESS_LEN_MAX]; int len; - int rpt = (sys_rand32_get() & 3) + 1; + int rpt = (sys_rand8_get() & 3) + 1; for (int i = 0; i < rpt; i++) { len = pbuf_read(ctx->pbuf, buf, (uint16_t)sizeof(buf)); @@ -235,8 +235,8 @@ bool stress_write(void *user_data, uint32_t cnt, bool last, int prio) struct stress_data *ctx = (struct stress_data *)user_data; char buf[STRESS_LEN_MAX]; - uint16_t len = STRESS_LEN_MIN + (sys_rand32_get() % STRESS_LEN_MOD); - int rpt = (sys_rand32_get() & 1) + 1; + uint16_t len = STRESS_LEN_MIN + (sys_rand8_get() % STRESS_LEN_MOD); + int rpt = (sys_rand8_get() & 1) + 1; zassert_true(len < sizeof(buf)); diff --git a/tests/subsys/logging/log_stress/src/main.c b/tests/subsys/logging/log_stress/src/main.c index 8ca43f47b3d..4d06de584f5 100644 --- a/tests/subsys/logging/log_stress/src/main.c +++ b/tests/subsys/logging/log_stress/src/main.c @@ -116,7 +116,7 @@ static bool context_handler(void *user_data, uint32_t cnt, bool last, int prio) uint32_t i = cnt | (prio << CNT_BITS); - switch (sys_rand32_get() % 4) { + switch (sys_rand8_get() % 4) { case 0: LOG_INF("%u", i); break; From 7fc6ef28d3dacad1c1c67791fc645031529d3c64 Mon Sep 17 00:00:00 2001 From: Georges Oates_Larsen Date: Fri, 29 Mar 2024 15:01:05 -0700 Subject: [PATCH 1921/2402] net: lib: http: Correct http_client edge-case behavior Correct various small edge-case behaviors that have been accidentally introduced in the http_client. - http_client_req no longer incorrectly returns -ETIMEDOUT on NULL HTTP resonse. -ETIMEDOUT is now only returned when the underlying TLS socket times out. - http_client_req now returns -ECONRESET upon incomplete (but non-NULL) HTTP response. The request callback is no longer called in this case (as with any other error state). - http_wait_data has been refactored slightly to increase clarity. Signed-off-by: Georges Oates_Larsen --- subsys/net/lib/http/http_client.c | 105 +++++++++++++++++------------- 1 file changed, 58 insertions(+), 47 deletions(-) diff --git a/subsys/net/lib/http/http_client.c b/subsys/net/lib/http/http_client.c index 3992e5fafdd..0f73ce6e8f8 100644 --- a/subsys/net/lib/http/http_client.c +++ b/subsys/net/lib/http/http_client.c @@ -392,7 +392,11 @@ static void http_client_init_parser(struct http_parser *parser, settings->on_url = on_url; } -static void http_data_final_null_resp(struct http_request *req) +/* Report a NULL HTTP response to the caller. + * A NULL response is when the HTTP server intentionally closes the TLS socket (using FINACK) + * without sending any HTTP payload. + */ +static void http_report_null(struct http_request *req) { if (req->internal.response.cb) { NET_DBG("Calling callback for Final Data" @@ -413,6 +417,28 @@ static void http_data_final_null_resp(struct http_request *req) } } +/* Report a completed HTTP transaction (with no error) to the caller */ +static void http_report_complete(struct http_request *req) +{ + if (req->internal.response.cb) { + NET_DBG("Calling callback for %zd len data", req->internal.response.data_len); + req->internal.response.cb(&req->internal.response, HTTP_DATA_FINAL, + req->internal.user_data); + } +} + +/* Report that some data has been received, but the HTTP transaction is still ongoing. */ +static void http_report_progress(struct http_request *req) +{ + if (req->internal.response.cb) { + NET_DBG("Calling callback for partitioned %zd len data", + req->internal.response.data_len); + + req->internal.response.cb(&req->internal.response, HTTP_DATA_MORE, + req->internal.user_data); + } +} + static int http_wait_data(int sock, struct http_request *req, int32_t timeout) { int total_received = 0; @@ -438,24 +464,26 @@ static int http_wait_data(int sock, struct http_request *req, int32_t timeout) ret = zsock_poll(fds, nfds, remaining_time); if (ret == 0) { LOG_DBG("Timeout"); - goto finalize_data; + ret = -ETIMEDOUT; + goto error; } else if (ret < 0) { + ret = -errno; goto error; } if (fds[0].revents & (ZSOCK_POLLERR | ZSOCK_POLLNVAL)) { + ret = -errno; goto error; } else if (fds[0].revents & ZSOCK_POLLHUP) { /* Connection closed */ - LOG_DBG("Connection closed"); - goto finalize_data; + goto closed; } else if (fds[0].revents & ZSOCK_POLLIN) { received = zsock_recv(sock, req->internal.response.recv_buf + offset, req->internal.response.recv_buf_len - offset, 0); if (received == 0) { /* Connection closed */ - LOG_DBG("Connection closed"); - goto finalize_data; + goto closed; } else if (received < 0) { + ret = -errno; goto error; } else { req->internal.response.data_len += received; @@ -472,54 +500,41 @@ static int http_wait_data(int sock, struct http_request *req, int32_t timeout) offset = 0; } - if (req->internal.response.cb) { - bool notify = false; - enum http_final_call event; - - if (req->internal.response.message_complete) { - NET_DBG("Calling callback for %zd len data", - req->internal.response.data_len); - - notify = true; - event = HTTP_DATA_FINAL; - } else if (offset == 0) { - NET_DBG("Calling callback for partitioned %zd len data", - req->internal.response.data_len); - - notify = true; - event = HTTP_DATA_MORE; - } - - if (notify) { - req->internal.response.cb(&req->internal.response, event, - req->internal.user_data); - - /* Re-use the result buffer and start to fill it again */ - req->internal.response.data_len = 0; - req->internal.response.body_frag_start = NULL; - req->internal.response.body_frag_len = 0; - } - } - if (req->internal.response.message_complete) { - ret = total_received; + http_report_complete(req); break; + } else if (offset == 0) { + http_report_progress(req); + + /* Re-use the result buffer and start to fill it again */ + req->internal.response.data_len = 0; + req->internal.response.body_frag_start = NULL; + req->internal.response.body_frag_len = 0; } } } while (true); - return ret; + return total_received; -finalize_data: - ret = total_received; +closed: + LOG_DBG("Connection closed"); - http_data_final_null_resp(req); - return ret; + /* If connection was closed with no data sent, this is a NULL response, and is a special + * case valid response. + */ + if (total_received == 0) { + http_report_null(req); + return total_received; + } + + /* Otherwise, connection was closed mid-way through response, and this should be + * considered an error. + */ + ret = -ECONNRESET; error: - LOG_DBG("Connection error (%d)", errno); - ret = -errno; + LOG_DBG("Connection error (%d)", ret); return ret; } @@ -719,10 +734,6 @@ int http_client_req(int sock, struct http_request *req, NET_DBG("Wait data failure (%d)", total_recv); ret = total_recv; goto out; - } else if (total_recv == 0) { - NET_DBG("Timeout while waiting data"); - ret = -ETIMEDOUT; - goto out; } NET_DBG("Received %d bytes", total_recv); From 080d31dede243779b8b80ff865fe6f37c0a2501d Mon Sep 17 00:00:00 2001 From: Graham Harrison Date: Tue, 2 Apr 2024 15:55:10 -0600 Subject: [PATCH 1922/2402] boards: shields: seeed_xiao_expansion_board: fix missing include Was getting the error "parse error: expected number or parenthesized expression" when trying to compile with the -DSHIELD=seeed_xiao_expansion_board flag. It looks like INPUT_KEY_0 was missing the necessary include file so I added it in. Signed-off-by: Graham Harrison --- .../seeed_xiao_expansion_board.overlay | 2 ++ 1 file changed, 2 insertions(+) diff --git a/boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay b/boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay index cd318d5fe50..b61e2c85fc5 100644 --- a/boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay +++ b/boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay @@ -3,6 +3,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { chosen { zephyr,display = &ssd1306_128x64; From 83c031556b68f8120acedc61f47772d3543f815b Mon Sep 17 00:00:00 2001 From: Jose Alberto Meza Date: Mon, 21 Aug 2023 14:09:40 -0700 Subject: [PATCH 1923/2402] soc: arm: microchip: mec172x: Add macro to get pin mux value Add macro to read pin mux control value Signed-off-by: Jose Alberto Meza --- soc/microchip/mec/mec172x/reg/mec172x_gpio.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/soc/microchip/mec/mec172x/reg/mec172x_gpio.h b/soc/microchip/mec/mec172x/reg/mec172x_gpio.h index 39ed59d279d..f013ba69aca 100644 --- a/soc/microchip/mec/mec172x/reg/mec172x_gpio.h +++ b/soc/microchip/mec/mec172x/reg/mec172x_gpio.h @@ -92,6 +92,9 @@ #define MCHP_GPIO_CTRL_MUX_F7 SHLU32(7, MCHP_GPIO_CTRL_MUX_POS) #define MCHP_GPIO_CTRL_MUX(n) SHLU32(((n) & 0x7u), MCHP_GPIO_CTRL_MUX_POS) +#define MCHP_GPIO_CTRL_MUX_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_MUX_POS)\ + & MCHP_GPIO_CTRL_MUX_MASK0) + /* * bit[15] Disables input pad leaving output pad enabled * Useful for reducing power consumption of output only pins. From b5778f1b38f5b886cfcf0469b8c9d2791bd3a3a2 Mon Sep 17 00:00:00 2001 From: Jose Alberto Meza Date: Mon, 21 Aug 2023 14:51:56 -0700 Subject: [PATCH 1924/2402] drivers: gpio: mec172x: Add message to warn about pins not in GPIO mode Warn about potential device tree errors for cases when driver's client tries to configure a pin as GPIO but which is not in GPIO mode. Signed-off-by: Jose Alberto Meza --- drivers/gpio/gpio_mchp_xec_v2.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpio/gpio_mchp_xec_v2.c b/drivers/gpio/gpio_mchp_xec_v2.c index 3c89ed79c5b..67697b1e318 100644 --- a/drivers/gpio/gpio_mchp_xec_v2.c +++ b/drivers/gpio/gpio_mchp_xec_v2.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,8 @@ #define XEC_GPIO_EDGE_DLY_COUNT 4 +LOG_MODULE_REGISTER(gpio, CONFIG_GPIO_LOG_LEVEL); + static const uint32_t valid_ctrl_masks[NUM_MCHP_GPIO_PORTS] = { (MCHP_GPIO_PORT_A_BITMAP), (MCHP_GPIO_PORT_B_BITMAP), @@ -141,6 +144,12 @@ static int gpio_xec_configure(const struct device *dev, pcr1_addr = pin_ctrl_addr(dev, pin); pcr1 = sys_read32(pcr1_addr); + /* Check if pin is in GPIO mode */ + if (MCHP_GPIO_CTRL_MUX_GET(pcr1) != MCHP_GPIO_CTRL_MUX_F0) { + LOG_WRN("Port:%d pin:0x%x not in GPIO mode. CTRL[%x]=%x", config->port_num, pin, + (uint32_t)pcr1_addr, pcr1); + } + if (flags == GPIO_DISCONNECTED) { pcr1 = (pcr1 & ~MCHP_GPIO_CTRL_PWRG_MASK) | MCHP_GPIO_CTRL_PWRG_OFF; sys_write32(pcr1, pcr1_addr); From 4879681b7e38aaed42a252fde216484f09863824 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Fri, 5 Apr 2024 18:52:18 +0200 Subject: [PATCH 1925/2402] cmake: remove stray overlay file from target sources An overlay file was wrongly added to a target_sources call, this has now been corrected. Signed-off-by: Torsten Rasmussen --- samples/modules/tflite-micro/magic_wand/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/samples/modules/tflite-micro/magic_wand/CMakeLists.txt b/samples/modules/tflite-micro/magic_wand/CMakeLists.txt index 27f3e14c326..3108d31bbe7 100644 --- a/samples/modules/tflite-micro/magic_wand/CMakeLists.txt +++ b/samples/modules/tflite-micro/magic_wand/CMakeLists.txt @@ -10,4 +10,4 @@ set(NO_THREADSAFE_STATICS $) zephyr_compile_options($<$:${NO_THREADSAFE_STATICS}>) file(GLOB app_sources src/*) -target_sources(app PRIVATE ${app_sources} boards/litex_vexriscv.overlay) +target_sources(app PRIVATE ${app_sources}) From 2ccf775396c225f4398db1014886397a91f6d42f Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 27 Mar 2024 14:43:31 +0100 Subject: [PATCH 1926/2402] llext: add support for relocatable objects on Xtensa Some toolchains cannot create shared objects for Xtensa, with them we have to use relocatable objects. Add support for them to llext. Signed-off-by: Guennadi Liakhovetski --- arch/xtensa/core/elf.c | 31 +++++++++--- include/zephyr/llext/llext.h | 3 +- include/zephyr/llext/loader.h | 3 ++ subsys/llext/llext.c | 94 ++++++++++++++++++++++++++++------- 4 files changed, 104 insertions(+), 27 deletions(-) diff --git a/arch/xtensa/core/elf.c b/arch/xtensa/core/elf.c index 976be9f794a..46da8eb908a 100644 --- a/arch/xtensa/core/elf.c +++ b/arch/xtensa/core/elf.c @@ -27,19 +27,34 @@ LOG_MODULE_DECLARE(llext); * supporting modules must implement this. */ void arch_elf_relocate_local(struct llext_loader *ldr, struct llext *ext, - elf_rela_t *rel, size_t got_offset) + const elf_rela_t *rel, const elf_sym_t *sym, size_t got_offset) { uint8_t *text = ext->mem[LLEXT_MEM_TEXT]; int type = ELF32_R_TYPE(rel->r_info); + elf_word *got_entry = (elf_word *)(text + got_offset); + uintptr_t sh_addr; - if (type == R_XTENSA_RELATIVE) { - elf_word ptr_offset = *(elf_word *)(text + got_offset); - - LOG_DBG("relocation type %u offset %#x value %#x", - type, got_offset, ptr_offset); + if (ELF_ST_TYPE(sym->st_info) == STT_SECTION) { + elf_shdr_t *shdr = llext_peek(ldr, ldr->hdr.e_shoff + + sym->st_shndx * ldr->hdr.e_shentsize); + sh_addr = shdr->sh_addr; + } else { + sh_addr = ldr->sects[LLEXT_MEM_TEXT].sh_addr; + } + switch (type) { + case R_XTENSA_RELATIVE: /* Relocate a local symbol: Xtensa specific */ - *(elf_word *)(text + got_offset) = (elf_word)(text + ptr_offset - - ldr->sects[LLEXT_MEM_TEXT].sh_addr); + *got_entry += (uintptr_t)text - sh_addr; + break; + case R_XTENSA_32: + *got_entry += sh_addr; + break; + default: + LOG_DBG("unsupported relocation type %u", type); + + return; } + + LOG_DBG("relocation to %#x type %u at %p", *got_entry, type, (void *)got_entry); } diff --git a/include/zephyr/llext/llext.h b/include/zephyr/llext/llext.h index e09e21c14f6..754f0ea846d 100644 --- a/include/zephyr/llext/llext.h +++ b/include/zephyr/llext/llext.h @@ -222,10 +222,11 @@ ssize_t llext_find_section(struct llext_loader *loader, const char *search_name) * @param[in] loader Extension loader data and context * @param[in] ext Extension to call function in * @param[in] rel Relocation data provided by elf + * @param[in] sym Corresponding symbol table entry * @param[in] got_offset Offset within a relocation table */ void arch_elf_relocate_local(struct llext_loader *loader, struct llext *ext, - elf_rela_t *rel, size_t got_offset); + const elf_rela_t *rel, const elf_sym_t *sym, size_t got_offset); /** * @} diff --git a/include/zephyr/llext/loader.h b/include/zephyr/llext/loader.h index 7eb49d611be..b8477eb3003 100644 --- a/include/zephyr/llext/loader.h +++ b/include/zephyr/llext/loader.h @@ -68,6 +68,9 @@ struct llext_loader { */ void *(*peek)(struct llext_loader *ldr, size_t pos); + /** Total calculated .data size for relocatable extensions */ + size_t prog_data_size; + /** @cond ignore */ elf_ehdr_t hdr; elf_shdr_t sects[LLEXT_MEM_COUNT]; diff --git a/subsys/llext/llext.c b/subsys/llext/llext.c index 3a5a39ed7ee..08d3719778a 100644 --- a/subsys/llext/llext.c +++ b/subsys/llext/llext.c @@ -32,7 +32,7 @@ static sys_slist_t _llext_list = SYS_SLIST_STATIC_INIT(&_llext_list); static struct k_mutex llext_lock = Z_MUTEX_INITIALIZER(llext_lock); -ssize_t llext_find_section(struct llext_loader *ldr, const char *search_name) +static elf_shdr_t *llext_section_by_name(struct llext_loader *ldr, const char *search_name) { elf_shdr_t *shdr; unsigned int i; @@ -44,7 +44,7 @@ ssize_t llext_find_section(struct llext_loader *ldr, const char *search_name) shdr = llext_peek(ldr, pos); if (!shdr) { /* The peek() method isn't supported */ - return -EOPNOTSUPP; + return NULL; } const char *name = llext_peek(ldr, @@ -52,11 +52,18 @@ ssize_t llext_find_section(struct llext_loader *ldr, const char *search_name) shdr->sh_name); if (!strcmp(name, search_name)) { - return shdr->sh_offset; + return shdr; } } - return -ENOENT; + return NULL; +} + +ssize_t llext_find_section(struct llext_loader *ldr, const char *search_name) +{ + elf_shdr_t *shdr = llext_section_by_name(ldr, search_name); + + return shdr ? shdr->sh_offset : -ENOENT; } /* @@ -214,9 +221,12 @@ static int llext_map_sections(struct llext_loader *ldr, struct llext *ext) { int i, ret; size_t pos; - elf_shdr_t shdr; + elf_shdr_t shdr, rodata = {.sh_addr = ~0}, + high_shdr = {.sh_offset = 0}, low_shdr = {.sh_offset = ~0}; const char *name; + ldr->sects[LLEXT_MEM_RODATA].sh_size = 0; + for (i = 0, pos = ldr->hdr.e_shoff; i < ldr->hdr.e_shnum; i++, pos += ldr->hdr.e_shentsize) { @@ -230,12 +240,38 @@ static int llext_map_sections(struct llext_loader *ldr, struct llext *ext) return ret; } + /* Identify the lowest and the highest data sections */ + if (!(shdr.sh_flags & SHF_EXECINSTR) && + shdr.sh_type == SHT_PROGBITS) { + if (shdr.sh_offset > high_shdr.sh_offset) { + high_shdr = shdr; + } + if (shdr.sh_offset < low_shdr.sh_offset) { + low_shdr = shdr; + } + } + name = llext_string(ldr, ext, LLEXT_MEM_SHSTRTAB, shdr.sh_name); LOG_DBG("section %d name %s", i, name); enum llext_mem mem_idx; + /* + * .rodata section is optional. If there isn't one, use the + * first read-only data section + */ + if (shdr.sh_addr && !(shdr.sh_flags & (SHF_WRITE | SHF_EXECINSTR)) && + shdr.sh_addr < rodata.sh_addr) { + rodata = shdr; + LOG_DBG("rodata: select %#zx name %s", (size_t)shdr.sh_addr, name); + } + + /* + * Keep in mind, that when using relocatable (partially linked) + * objects, ELF segments aren't created, so ldr->sect_map[] and + * ldr->sects[] don't contain all the sections + */ if (strcmp(name, ".text") == 0) { mem_idx = LLEXT_MEM_TEXT; } else if (strcmp(name, ".data") == 0) { @@ -255,6 +291,13 @@ static int llext_map_sections(struct llext_loader *ldr, struct llext *ext) ldr->sect_map[i] = mem_idx; } + ldr->prog_data_size = high_shdr.sh_size + high_shdr.sh_offset - low_shdr.sh_offset; + + /* No verbatim .rodata, use an automatically selected one */ + if (!ldr->sects[LLEXT_MEM_RODATA].sh_size) { + ldr->sects[LLEXT_MEM_RODATA] = rodata; + } + return 0; } @@ -556,12 +599,12 @@ static size_t llext_file_offset(struct llext_loader *ldr, size_t offset) } __weak void arch_elf_relocate_local(struct llext_loader *ldr, struct llext *ext, - elf_rela_t *rel, size_t got_offset) + const elf_rela_t *rel, const elf_sym_t *sym, size_t got_offset) { } static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, - elf_shdr_t *shdr, bool do_local) + elf_shdr_t *shdr, bool do_local, elf_shdr_t *tgt) { unsigned int sh_cnt = shdr->sh_size / shdr->sh_entsize; /* @@ -613,25 +656,36 @@ static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, } uint32_t stt = ELF_ST_TYPE(sym_tbl.st_info); - uint32_t stb = ELF_ST_BIND(sym_tbl.st_info); - if (stt != STT_FUNC && (stt != STT_NOTYPE || sym_tbl.st_shndx != SHN_UNDEF)) { + if (stt != STT_FUNC && + stt != STT_SECTION && + (stt != STT_NOTYPE || sym_tbl.st_shndx != SHN_UNDEF)) { continue; } const char *name = llext_string(ldr, ext, LLEXT_MEM_STRTAB, sym_tbl.st_name); + /* * Both r_offset and sh_addr are addresses for which the extension * has been built. */ - size_t got_offset = llext_file_offset(ldr, rela.r_offset) - - ldr->sects[LLEXT_MEM_TEXT].sh_offset; + size_t got_offset; + if (tgt) { + got_offset = rela.r_offset + tgt->sh_offset - + ldr->sects[LLEXT_MEM_TEXT].sh_offset; + } else { + got_offset = llext_file_offset(ldr, rela.r_offset) - + ldr->sects[LLEXT_MEM_TEXT].sh_offset; + } + + uint32_t stb = ELF_ST_BIND(sym_tbl.st_info); const void *link_addr; switch (stb) { case STB_GLOBAL: link_addr = llext_find_sym(NULL, name); + if (!link_addr) link_addr = llext_find_sym(&ext->sym_tab, name); @@ -648,9 +702,9 @@ static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, /* Resolve the symbol */ *(const void **)(text + got_offset) = link_addr; break; - case STB_LOCAL: + case STB_LOCAL: if (do_local) { - arch_elf_relocate_local(ldr, ext, &rela, got_offset); + arch_elf_relocate_local(ldr, ext, &rela, &sym_tbl, got_offset); } } @@ -697,8 +751,7 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local name = llext_string(ldr, ext, LLEXT_MEM_SHSTRTAB, shdr.sh_name); - if (strcmp(name, ".rel.text") == 0 || - strcmp(name, ".rela.text") == 0) { + if (strcmp(name, ".rel.text") == 0) { loc = (uintptr_t)ext->mem[LLEXT_MEM_TEXT]; } else if (strcmp(name, ".rel.bss") == 0 || strcmp(name, ".rela.bss") == 0) { @@ -706,14 +759,19 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local } else if (strcmp(name, ".rel.rodata") == 0 || strcmp(name, ".rela.rodata") == 0) { loc = (uintptr_t)ext->mem[LLEXT_MEM_RODATA]; - } else if (strcmp(name, ".rel.data") == 0 || - strcmp(name, ".rela.data") == 0) { + } else if (strcmp(name, ".rel.data") == 0) { loc = (uintptr_t)ext->mem[LLEXT_MEM_DATA]; } else if (strcmp(name, ".rel.exported_sym") == 0) { loc = (uintptr_t)ext->mem[LLEXT_MEM_EXPORT]; } else if (strcmp(name, ".rela.plt") == 0 || strcmp(name, ".rela.dyn") == 0) { - llext_link_plt(ldr, ext, &shdr, do_local); + llext_link_plt(ldr, ext, &shdr, do_local, NULL); + continue; + } else if (strncmp(name, ".rela", 5) == 0 && strlen(name) > 5) { + elf_shdr_t *tgt = llext_section_by_name(ldr, name + 5); + + if (tgt) + llext_link_plt(ldr, ext, &shdr, do_local, tgt); continue; } From 20b2c98add7ee9dde5194b0a56bda05cbd985553 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 28 Mar 2024 10:09:26 -0400 Subject: [PATCH 1927/2402] kernel: move nothread support to own file Do not build threading support when CONFIG_MULTITHREADING=n is set and move needed calls to a new file with the changes needed instead of the ifdef party in sched.c Signed-off-by: Anas Nashif --- kernel/CMakeLists.txt | 15 ++++++------ kernel/include/kthread.h | 2 -- kernel/nothread.c | 52 ++++++++++++++++++++++++++++++++++++++++ kernel/sched.c | 13 +--------- kernel/thread.c | 9 +------ 5 files changed, 62 insertions(+), 29 deletions(-) create mode 100644 kernel/nothread.c diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt index 3d7c4de6d65..17e52682a25 100644 --- a/kernel/CMakeLists.txt +++ b/kernel/CMakeLists.txt @@ -58,10 +58,7 @@ list(APPEND kernel_files kheap.c mem_slab.c float.c - thread.c version.c - priority_queues.c - sched.c ) if(CONFIG_SCHED_CPU_MASK) @@ -82,16 +79,20 @@ list(APPEND kernel_files system_work_q.c work.c condvar.c + priority_queues.c + thread.c + sched.c ) - if(CONFIG_SMP) list(APPEND kernel_files smp.c ipi.c) endif() - -endif() - +else() # CONFIG_MULTITHREADING +list(APPEND kernel_files + nothread.c + ) +endif() # CONFIG_MULTITHREADING if(CONFIG_TIMESLICING) list(APPEND kernel_files diff --git a/kernel/include/kthread.h b/kernel/include/kthread.h index 8438a37de15..9311552e0f0 100644 --- a/kernel/include/kthread.h +++ b/kernel/include/kthread.h @@ -43,7 +43,6 @@ void z_thread_monitor_exit(struct k_thread *thread); #endif /* CONFIG_THREAD_MONITOR */ -#ifdef CONFIG_MULTITHREADING static inline void thread_schedule_new(struct k_thread *thread, k_timeout_t delay) { #ifdef CONFIG_SYS_CLOCK_EXISTS @@ -57,7 +56,6 @@ static inline void thread_schedule_new(struct k_thread *thread, k_timeout_t dela k_thread_start(thread); #endif /* CONFIG_SYS_CLOCK_EXISTS */ } -#endif /* CONFIG_MULTITHREADING */ static inline int thread_is_preemptible(struct k_thread *thread) { diff --git a/kernel/nothread.c b/kernel/nothread.c new file mode 100644 index 00000000000..e4d7e095a2b --- /dev/null +++ b/kernel/nothread.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2024 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* We are not building thread.c when MULTITHREADING=n, so we + * need to provide a few stubs here. + */ +bool k_is_in_isr(void) +{ + return arch_is_in_isr(); +} + +/* This is a fallback implementation of k_sleep() for when multi-threading is + * disabled. The main implementation is in sched.c. + */ +int32_t z_impl_k_sleep(k_timeout_t timeout) +{ + k_ticks_t ticks; + uint32_t expected_wakeup_ticks; + + __ASSERT(!arch_is_in_isr(), ""); + + SYS_PORT_TRACING_FUNC_ENTER(k_thread, sleep, timeout); + + /* in case of K_FOREVER, we suspend */ + if (K_TIMEOUT_EQ(timeout, K_FOREVER)) { + /* In Single Thread, just wait for an interrupt saving power */ + k_cpu_idle(); + SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER); + + return (int32_t) K_TICKS_FOREVER; + } + + ticks = timeout.ticks; + if (Z_TICK_ABS(ticks) <= 0) { + expected_wakeup_ticks = ticks + sys_clock_tick_get_32(); + } else { + expected_wakeup_ticks = Z_TICK_ABS(ticks); + } + /* busy wait to be time coherent since subsystems may depend on it */ + z_impl_k_busy_wait(k_ticks_to_us_ceil32(expected_wakeup_ticks)); + + int32_t ret = k_ticks_to_ms_ceil64(0); + + SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ret); + + return ret; +} diff --git a/kernel/sched.c b/kernel/sched.c index c7bfbd1ddcb..2fa45417ca6 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -1136,13 +1136,11 @@ static int32_t z_tick_sleep(k_ticks_t ticks) LOG_DBG("thread %p for %lu ticks", _current, (unsigned long)ticks); -#ifdef CONFIG_MULTITHREADING /* wait of 0 ms is treated as a 'yield' */ if (ticks == 0) { k_yield(); return 0; } -#endif /* CONFIG_MULTITHREADING */ if (Z_TICK_ABS(ticks) <= 0) { expected_wakeup_ticks = ticks + sys_clock_tick_get_32(); @@ -1150,7 +1148,6 @@ static int32_t z_tick_sleep(k_ticks_t ticks) expected_wakeup_ticks = Z_TICK_ABS(ticks); } -#ifdef CONFIG_MULTITHREADING k_timeout_t timeout = Z_TIMEOUT_TICKS(ticks); k_spinlock_key_t key = k_spin_lock(&_sched_spinlock); @@ -1169,10 +1166,6 @@ static int32_t z_tick_sleep(k_ticks_t ticks) if (ticks > 0) { return ticks; } -#else - /* busy wait to be time coherent since subsystems may depend on it */ - z_impl_k_busy_wait(k_ticks_to_us_ceil32(expected_wakeup_ticks)); -#endif /* CONFIG_MULTITHREADING */ return 0; } @@ -1187,12 +1180,8 @@ int32_t z_impl_k_sleep(k_timeout_t timeout) /* in case of K_FOREVER, we suspend */ if (K_TIMEOUT_EQ(timeout, K_FOREVER)) { -#ifdef CONFIG_MULTITHREADING + k_thread_suspend(_current); -#else - /* In Single Thread, just wait for an interrupt saving power */ - k_cpu_idle(); -#endif /* CONFIG_MULTITHREADING */ SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER); return (int32_t) K_TICKS_FOREVER; diff --git a/kernel/thread.c b/kernel/thread.c index 762432c4b1e..e31bed82c89 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -307,8 +307,6 @@ static inline int z_vrfy_k_thread_name_copy(k_tid_t thread, #include #endif /* CONFIG_USERSPACE */ - -#ifdef CONFIG_MULTITHREADING #ifdef CONFIG_STACK_SENTINEL /* Check that the stack sentinel is still present * @@ -357,8 +355,6 @@ static inline void z_vrfy_k_thread_start(struct k_thread *thread) } #include #endif /* CONFIG_USERSPACE */ -#endif /* CONFIG_MULTITHREADING */ - #if CONFIG_STACK_POINTER_RANDOM int z_stack_adjust_initialized; @@ -616,7 +612,7 @@ char *z_setup_new_thread(struct k_thread *new_thread, return stack_ptr; } -#ifdef CONFIG_MULTITHREADING + k_tid_t z_impl_k_thread_create(struct k_thread *new_thread, k_thread_stack_t *stack, size_t stack_size, k_thread_entry_t entry, @@ -635,7 +631,6 @@ k_tid_t z_impl_k_thread_create(struct k_thread *new_thread, return new_thread; } - #ifdef CONFIG_USERSPACE bool z_stack_is_user_capable(k_thread_stack_t *stack) { @@ -708,8 +703,6 @@ k_tid_t z_vrfy_k_thread_create(struct k_thread *new_thread, } #include #endif /* CONFIG_USERSPACE */ -#endif /* CONFIG_MULTITHREADING */ - void z_init_thread_base(struct _thread_base *thread_base, int priority, uint32_t initial_state, unsigned int options) From 8372df0a4868daa9750c8ea30a54c02802ecb5df Mon Sep 17 00:00:00 2001 From: Andriy Gelman Date: Mon, 18 Mar 2024 14:57:07 -0400 Subject: [PATCH 1928/2402] drivers: can: mcp251xfd: Add can statistics support Adds support for tracking CAN bus errors when CONFIG_CAN_STATS=y Signed-off-by: Andriy Gelman --- drivers/can/can_mcp251xfd.c | 75 ++++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/drivers/can/can_mcp251xfd.c b/drivers/can/can_mcp251xfd.c index 24f66f4eea6..d11f64d6dbb 100644 --- a/drivers/can/can_mcp251xfd.c +++ b/drivers/can/can_mcp251xfd.c @@ -958,6 +958,7 @@ static int mcp251xfd_handle_ivmif(const struct device *dev) uint32_t *reg; struct mcp251xfd_data *dev_data = dev->data; int ret; + uint32_t tmp; k_mutex_lock(&dev_data->mutex, K_FOREVER); @@ -967,9 +968,9 @@ static int mcp251xfd_handle_ivmif(const struct device *dev) goto done; } - *reg = sys_le32_to_cpu(*reg); + tmp = sys_le32_to_cpu(*reg); - if ((*reg & MCP251XFD_REG_BDIAG1_TXBOERR) != 0) { + if ((tmp & MCP251XFD_REG_BDIAG1_TXBOERR) != 0) { LOG_INF("ivmif bus-off error"); mcp251xfd_reset_tx_fifos(dev, -ENETDOWN); } @@ -978,12 +979,65 @@ static int mcp251xfd_handle_ivmif(const struct device *dev) reg = mcp251xfd_get_spi_buf_ptr(dev); reg[0] = 0; ret = mcp251xfd_write(dev, MCP251XFD_REG_BDIAG1, MCP251XFD_REG_SIZE); + if (ret < 0) { + goto done; + } + + /* There's no flag for DACKERR */ + if ((tmp & MCP251XFD_REG_BDIAG1_NACKERR) != 0) { + CAN_STATS_ACK_ERROR_INC(dev); + } + + if ((tmp & (MCP251XFD_REG_BDIAG1_NBIT0ERR | MCP251XFD_REG_BDIAG1_DBIT0ERR)) != 0) { + CAN_STATS_BIT0_ERROR_INC(dev); + } + + if ((tmp & (MCP251XFD_REG_BDIAG1_NBIT1ERR | MCP251XFD_REG_BDIAG1_DBIT1ERR)) != 0) { + CAN_STATS_BIT1_ERROR_INC(dev); + } + + if ((tmp & (MCP251XFD_REG_BDIAG1_NCRCERR | MCP251XFD_REG_BDIAG1_DCRCERR)) != 0) { + CAN_STATS_CRC_ERROR_INC(dev); + } + + if ((tmp & (MCP251XFD_REG_BDIAG1_NFORMERR | MCP251XFD_REG_BDIAG1_DFORMERR)) != 0) { + CAN_STATS_FORM_ERROR_INC(dev); + } + + if ((tmp & (MCP251XFD_REG_BDIAG1_NSTUFERR | MCP251XFD_REG_BDIAG1_DSTUFERR)) != 0) { + CAN_STATS_STUFF_ERROR_INC(dev); + } done: k_mutex_unlock(&dev_data->mutex); return ret; } +#if defined(CONFIG_CAN_STATS) +static int mcp251xfd_handle_rxovif(const struct device *dev) +{ + uint8_t *reg_byte; + struct mcp251xfd_data *dev_data = dev->data; + int ret; + + k_mutex_lock(&dev_data->mutex, K_FOREVER); + + reg_byte = mcp251xfd_get_spi_buf_ptr(dev); + *reg_byte = 0; + + ret = mcp251xfd_write(dev, MCP251XFD_REG_FIFOSTA(MCP251XFD_RX_FIFO_IDX), 1); + if (ret < 0) { + goto done; + } + + CAN_STATS_RX_OVERRUN_INC(dev); + +done: + k_mutex_unlock(&dev_data->mutex); + return ret; +} +#endif + static void mcp251xfd_handle_interrupts(const struct device *dev) { const struct mcp251xfd_config *dev_cfg = dev->config; @@ -1064,6 +1118,15 @@ static void mcp251xfd_handle_interrupts(const struct device *dev) } } +#if defined(CONFIG_CAN_STATS) + if ((reg_int & MCP251XFD_REG_INT_RXOVIF) != 0) { + ret = mcp251xfd_handle_rxovif(dev); + if (ret < 0) { + LOG_ERR("Error handling RXOVIF [%d]", ret); + } + } +#endif + /* Break from loop if INT pin is inactive */ consecutive_calls++; ret = gpio_pin_get_dt(&dev_cfg->int_gpio_dt); @@ -1156,6 +1219,8 @@ static int mcp251xfd_start(const struct device *dev) k_mutex_lock(&dev_data->mutex, K_FOREVER); + CAN_STATS_RESET(dev); + ret = mcp251xfd_set_mode_internal(dev, dev_data->next_mcp251xfd_mode); if (ret < 0) { LOG_ERR("Failed to set the mode [%d]", ret); @@ -1347,6 +1412,9 @@ static inline int mcp251xfd_init_int_reg(const struct device *dev) tmp = MCP251XFD_REG_INT_RXIE | MCP251XFD_REG_INT_MODIE | MCP251XFD_REG_INT_TEFIE | MCP251XFD_REG_INT_CERRIE; +#if defined(CONFIG_CAN_STATS) + tmp |= MCP251XFD_REG_INT_RXOVIE; +#endif *reg = sys_cpu_to_le32(tmp); @@ -1388,6 +1456,9 @@ static inline int mcp251xfd_init_rx_fifo(const struct device *dev) uint32_t tmp; tmp = MCP251XFD_REG_FIFOCON_TFNRFNIE | MCP251XFD_REG_FIFOCON_FRESET; +#if defined(CONFIG_CAN_STATS) + tmp |= MCP251XFD_REG_FIFOCON_RXOVIE; +#endif tmp |= FIELD_PREP(MCP251XFD_REG_FIFOCON_FSIZE_MASK, MCP251XFD_RX_FIFO_ITEMS - 1); tmp |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK, can_bytes_to_dlc(MCP251XFD_PAYLOAD_SIZE) - 8); From 25812289779f471143cf1a2cc34c245c603bd941 Mon Sep 17 00:00:00 2001 From: Benjamin Perseghetti Date: Fri, 5 Apr 2024 12:49:36 -0400 Subject: [PATCH 1929/2402] boards: nxp: vmu_rt1170: dts use gpio-keys Fix vmu_rt1170 board input tests by adding gpio-keys to dts. Signed-off-by: Benjamin Perseghetti --- boards/nxp/vmu_rt1170/vmu_rt1170.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170.dts b/boards/nxp/vmu_rt1170/vmu_rt1170.dts index dc60deb2e18..564164c5ae4 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170.dts +++ b/boards/nxp/vmu_rt1170/vmu_rt1170.dts @@ -9,6 +9,7 @@ #include #include #include "vmu_rt1170.dtsi" +#include / { model = "NXP VMU RT1170"; @@ -35,12 +36,13 @@ zephyr,code-partition = &slot0_partition; }; - /* This is the Button on the included GPS module for 10 pin JST-GH */ - buttons { + /* This is the Arming Button on the included GPS module for 10 pin JST-GH */ + gpio_keys { compatible = "gpio-keys"; arming_button: button_0 { label = "Arming Switch"; gpios = <&gpio1 24 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + zephyr,code = ; }; }; From c38ea288eee954c0ba9e51a79eb16390f3476e5e Mon Sep 17 00:00:00 2001 From: Daniel Irekvist Date: Fri, 8 Mar 2024 23:28:54 +0100 Subject: [PATCH 1930/2402] boards: sparkfun: Fix incorrect pro_micro gpio-map The SparkFun Pro Micro header pins are numbered D1, D0, GND, ... from top left whereas the SparkFun Pro Micro RP2040 and the Adafruit KB2040 boards are using gpio 0, 1, GND, ... , so the pro_micro: connector gpio-map of these boards should reflect that. Graphical Datasheet for SparkFun Pro Micro RP2040: https://cdn.sparkfun.com/assets/e/2/7/6/b/ProMicroRP2040_Graphical_Datasheet.pdf Graphical Datasheet for SparkFun Pro Micro: https://cdn.sparkfun.com/assets/f/d/8/0/d/ProMicro16MHzv2.pdf Pinout of the Adafruit KB2040: https://learn.adafruit.com/assets/106984 Please note that the KB2040 uses CircuitPython pin labels D0, D1 which does not seemt correspond to the Arduino labels D0 and D1 used by the Pro Micro. Signed-off-by: Daniel Irekvist --- .../kb2040/sparkfun_pro_micro_connector.dtsi | 4 +-- .../sparkfun_pro_micro_connector.dtsi | 4 +-- doc/releases/migration-guide-3.7.rst | 3 ++ .../gpio/sparkfun-pro-micro-header.yaml | 28 ++++++++++--------- 4 files changed, 22 insertions(+), 17 deletions(-) diff --git a/boards/adafruit/kb2040/sparkfun_pro_micro_connector.dtsi b/boards/adafruit/kb2040/sparkfun_pro_micro_connector.dtsi index c3ec9f3eb49..7412cb915e9 100644 --- a/boards/adafruit/kb2040/sparkfun_pro_micro_connector.dtsi +++ b/boards/adafruit/kb2040/sparkfun_pro_micro_connector.dtsi @@ -11,8 +11,8 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map - = <0 0 &gpio0 0 0> /* D0 */ - , <1 0 &gpio0 1 0> /* D1 */ + = <1 0 &gpio0 0 0> /* D1 */ + , <0 0 &gpio0 1 0> /* D0 */ , <2 0 &gpio0 2 0> /* D2 */ , <3 0 &gpio0 3 0> /* D3 */ , <4 0 &gpio0 4 0> /* D4/A6 */ diff --git a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi index 21852f64b7b..c43b52f2ead 100644 --- a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi @@ -11,8 +11,8 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map - = <0 0 &gpio0 0 0> /* D0 */ - , <1 0 &gpio0 1 0> /* D1 */ + = <1 0 &gpio0 0 0> /* D1 */ + , <0 0 &gpio0 1 0> /* D0 */ , <2 0 &gpio0 2 0> /* D2 */ , <3 0 &gpio0 3 0> /* D3 */ , <4 0 &gpio0 4 0> /* D4/A6 */ diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index 6c6a600eff8..0a45c6337cb 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -28,6 +28,9 @@ Kernel Boards ****** +* Reordered D1 and D0 in the `pro_micro` connector gpio-map for SparkFun Pro Micro RP2040 to match + original Pro Micro definition. Out-of-tree shields must be updated to reflect this change. + Modules ******* diff --git a/dts/bindings/gpio/sparkfun-pro-micro-header.yaml b/dts/bindings/gpio/sparkfun-pro-micro-header.yaml index 25e9f1611ca..99c75bcf899 100644 --- a/dts/bindings/gpio/sparkfun-pro-micro-header.yaml +++ b/dts/bindings/gpio/sparkfun-pro-micro-header.yaml @@ -16,19 +16,21 @@ description: | This binding provides a nexus mapping for 18 pins, as depicted below: - 0 TX0 RAW - - 1 RX1 GND - - - GND RST - - - GND VCC - - 2 D2 D21/A3 21 - 3 D3 D20/A2 20 - 4 A4 D19/A1 19 - 5 D5 D18/A0 18 - 6 D6 D15 15 - 7 D7 D14 14 - 8 D8 D16 16 - 9 D9 D10 10 - + 1 D1/TXO RAW - + 0 D0/RXI GND - + - GND RST - + - GND VCC - + 2 D2 D21/A3 21 + 3 D3 D20/A2 20 + 4 D4/A6 D19/A1 19 + 5 D5 D18/A0 18 + 6 D6/A7 D15 15 + 7 D7 D14 14 + 8 D8/A8 D16 16 + 9 D9/A9 D10/A10 10 + + A graphical datasheet of the headers can be seen here: + https://cdn.sparkfun.com/assets/f/d/8/0/d/ProMicro16MHzv2.pdf compatible: "sparkfun,pro-micro-gpio" From 5b5db53a6febf422e2570b65a6fdab310e2ff92a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 4 Apr 2024 08:07:42 +0200 Subject: [PATCH 1931/2402] MAINTAINERS: hawkbit: add myself as maintainer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add myself as maintainer for hawkbit and change the status of hawkbit from odd fixes to maintained Signed-off-by: Fin Maaß --- MAINTAINERS.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index e5de1c6718d..0113b786817 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2474,10 +2474,11 @@ OSDP: - sample.mgmt.osdp hawkBit: - status: odd fixes + status: maintained + maintainers: + - maass-hamburg collaborators: - ycsin - - maass-hamburg files: - subsys/mgmt/hawkbit/ - include/zephyr/mgmt/hawkbit.h From 360bc4f1ca7971141558d0963c0493f1e564725c Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Fri, 29 Mar 2024 11:01:25 +0800 Subject: [PATCH 1932/2402] drivers: i2c: numaker: support Nuvoton's M2L31 series Add i2c nodes into soc devicetree Signed-off-by: Chun-Chieh Li --- dts/arm/nuvoton/m2l31x.dtsi | 49 +++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/dts/arm/nuvoton/m2l31x.dtsi b/dts/arm/nuvoton/m2l31x.dtsi index 51d38c3ee62..2edad5732b7 100644 --- a/dts/arm/nuvoton/m2l31x.dtsi +++ b/dts/arm/nuvoton/m2l31x.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { chosen { @@ -257,6 +258,54 @@ #size-cells = <0>; status = "disabled"; }; + + i2c0: i2c@40080000 { + compatible = "nuvoton,numaker-i2c"; + clock-frequency = ; + reg = <0x40080000 0x1000>; + interrupts = <38 0>; + resets = <&rst NUMAKER_I2C0_RST>; + clocks = <&pcc NUMAKER_I2C0_MODULE 0 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@40081000 { + compatible = "nuvoton,numaker-i2c"; + clock-frequency = ; + reg = <0x40081000 0x1000>; + interrupts = <39 0>; + resets = <&rst NUMAKER_I2C1_RST>; + clocks = <&pcc NUMAKER_I2C1_MODULE 0 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@40082000 { + compatible = "nuvoton,numaker-i2c"; + clock-frequency = ; + reg = <0x40082000 0x1000>; + interrupts = <82 0>; + resets = <&rst NUMAKER_I2C2_RST>; + clocks = <&pcc NUMAKER_I2C2_MODULE 0 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@40083000 { + compatible = "nuvoton,numaker-i2c"; + clock-frequency = ; + reg = <0x40083000 0x1000>; + interrupts = <83 0>; + resets = <&rst NUMAKER_I2C3_RST>; + clocks = <&pcc NUMAKER_I2C3_MODULE 0 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; From 4a0aa603c89cc4dbd0a9fd0bbc0f555f95fc3c3c Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Fri, 29 Mar 2024 11:36:44 +0800 Subject: [PATCH 1933/2402] tests: drivers: i2c: i2c_target_api: support numaker_m2l31ki Add support for Nuvoton numaker board numaker_m2l31ki. Signed-off-by: Chun-Chieh Li --- .../boards/numaker_m2l31ki.conf | 2 + .../boards/numaker_m2l31ki.overlay | 41 +++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 tests/drivers/i2c/i2c_target_api/boards/numaker_m2l31ki.conf create mode 100644 tests/drivers/i2c/i2c_target_api/boards/numaker_m2l31ki.overlay diff --git a/tests/drivers/i2c/i2c_target_api/boards/numaker_m2l31ki.conf b/tests/drivers/i2c/i2c_target_api/boards/numaker_m2l31ki.conf new file mode 100644 index 00000000000..f3d64527b85 --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/numaker_m2l31ki.conf @@ -0,0 +1,2 @@ +CONFIG_I2C=y +CONFIG_I2C_TARGET=y diff --git a/tests/drivers/i2c/i2c_target_api/boards/numaker_m2l31ki.overlay b/tests/drivers/i2c/i2c_target_api/boards/numaker_m2l31ki.overlay new file mode 100644 index 00000000000..2b621b51a2f --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/numaker_m2l31ki.overlay @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +&pinctrl { + i2c2_default: i2c2_default { + group0 { + pinmux = , /* UNO D6 */ + ; /* UNO D7 */ + }; + }; + + i2c0_default: i2c0_default { + group0 { + pinmux = , /* UNO D14 */ + ; /* UNO D15 */ + }; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; + status = "okay"; + + eeprom0: eeprom@54 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x54>; + size = <1024>; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; + + eeprom1: eeprom@56 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x56>; + size = <1024>; + }; +}; From 58e78c4af7f21178ebdeb07a353d2aa7e3f1c664 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 8 Mar 2024 14:33:54 -0600 Subject: [PATCH 1934/2402] dts: bindings: add binding for sitronix ST7796s Add binding for sitronix ST7796s, a MIPI DBI display controller supporting up to 320x480 displays at 18 BPP Signed-off-by: Daniel DeGrasse --- dts/bindings/display/sitronix,st7796s.yaml | 106 +++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 dts/bindings/display/sitronix,st7796s.yaml diff --git a/dts/bindings/display/sitronix,st7796s.yaml b/dts/bindings/display/sitronix,st7796s.yaml new file mode 100644 index 00000000000..8f67fe81e41 --- /dev/null +++ b/dts/bindings/display/sitronix,st7796s.yaml @@ -0,0 +1,106 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: ST7796S Display controller + +compatible: "sitronix,st7796s" + +include: [mipi-dbi-spi-device.yaml, display-controller.yaml] + +properties: + frmctl1: + type: uint8-array + default: [0xA0, 0x10] + description: | + Frame rate control (partial mode / full colors). The default value should + result in a framerate of ~41 FPS. + + frmctl2: + type: uint8-array + default: [0x00, 0x10] + description: | + Frame rate control (idle mode / 8 colors). This property sets the + division ratio for internal clocks in idle mode + + frmctl3: + type: uint8-array + default: [0x00, 0x10] + description: | + Frame rate control (partial mode / full colors). This property sets the + division ratio for internal clocks in partial mode + + bpc: + type: uint8-array + default: [0x02, 0x02, 0x00, 0x04] + description: | + Blanking porch control. This sets the vertical and horizontal + front/back porch values + + dfc: + type: uint8-array + default: [0x80, 0x02, 0x3B] + description: | + Display function control. Sets display graphical ram mode, as well as + gate scan mode + + pwr1: + type: uint8-array + default: [0x80, 0x25] + description: Power control parameter 1. Sets AVDDS, AVLCS, and VGHS + + pwr2: + type: int + default: 0x13 + description: Power control parameter 2. Sets VAP + + pwr3: + type: int + default: 0xA + description: Power control parameter 3. Sets source and gamma current levels + + vcmpctl: + type: int + default: 0x1C + description: | + VCOM control setting. Value starts at 0.300V, and moves upwards in + increments of 0.025V. Maximum of 1.875V + + doca: + type: uint8-array + default: [0x40, 0x8A, 0x00, 0x00, 0x25, 0x0A, 0x38, 0x33] + description: | + Display output control adjust. Sets display timing controls + + pgc: + type: uint8-array + required: true + description: | + Positive gamma control settings. No default is provided by controller, + as this setting is panel specific. + ngc: + type: uint8-array + required: true + description: | + Negative gamma control settings. No default is provided by controller, + as this setting is panel specific. + + madctl: + type: int + default: 0x0 + description: | + Memory data access control value. This controls the panel color format, + as well as rotation settings. + + color-invert: + type: boolean + description: When present, inverts display colors + + invert-mode: + type: string + default: "1-dot" + enum: + - "column" + - "1-dot" + - "2-dot" + description: | + Display inversion control mode. From 8ffd1e2f5359d54c3eb61aa5916648231efed4c1 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 8 Mar 2024 14:27:20 -0600 Subject: [PATCH 1935/2402] drivers: display: add driver for ST7796s display Add driver for ST7796s display. This is a MIPI DBI display controller, with a frame memory of 320x480x18 pixels. Support for 4 wire SPI mode is implemented using the MIPI DBI API. Signed-off-by: Daniel DeGrasse --- drivers/display/CMakeLists.txt | 1 + drivers/display/Kconfig | 1 + drivers/display/Kconfig.st7796s | 10 + drivers/display/display_st7796s.c | 354 ++++++++++++++++++++++++++++++ drivers/display/display_st7796s.h | 40 ++++ 5 files changed, 406 insertions(+) create mode 100644 drivers/display/Kconfig.st7796s create mode 100644 drivers/display/display_st7796s.c create mode 100644 drivers/display/display_st7796s.h diff --git a/drivers/display/CMakeLists.txt b/drivers/display/CMakeLists.txt index b9b866ccff4..2122d0f236b 100644 --- a/drivers/display/CMakeLists.txt +++ b/drivers/display/CMakeLists.txt @@ -19,6 +19,7 @@ zephyr_library_sources_ifdef(CONFIG_SSD1306 ssd1306.c) zephyr_library_sources_ifdef(CONFIG_SSD16XX ssd16xx.c) zephyr_library_sources_ifdef(CONFIG_ST7789V display_st7789v.c) zephyr_library_sources_ifdef(CONFIG_ST7735R display_st7735r.c) +zephyr_library_sources_ifdef(CONFIG_ST7796S display_st7796s.c) zephyr_library_sources_ifdef(CONFIG_STM32_LTDC display_stm32_ltdc.c) zephyr_library_sources_ifdef(CONFIG_RM68200 display_rm68200.c) zephyr_library_sources_ifdef(CONFIG_RM67162 display_rm67162.c) diff --git a/drivers/display/Kconfig b/drivers/display/Kconfig index 3270faf028d..6c2cca4dcfb 100644 --- a/drivers/display/Kconfig +++ b/drivers/display/Kconfig @@ -29,6 +29,7 @@ source "drivers/display/Kconfig.ssd1306" source "drivers/display/Kconfig.ssd16xx" source "drivers/display/Kconfig.st7735r" source "drivers/display/Kconfig.st7789v" +source "drivers/display/Kconfig.st7796s" source "drivers/display/Kconfig.stm32_ltdc" source "drivers/display/Kconfig.uc81xx" source "drivers/display/Kconfig.dummy" diff --git a/drivers/display/Kconfig.st7796s b/drivers/display/Kconfig.st7796s new file mode 100644 index 00000000000..a7cd7a549ef --- /dev/null +++ b/drivers/display/Kconfig.st7796s @@ -0,0 +1,10 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +config ST7796S + bool "ST7796S display driver" + default y + depends on DT_HAS_SITRONIX_ST7796S_ENABLED + select MIPI_DBI + help + Enable driver for ST7796S display driver. diff --git a/drivers/display/display_st7796s.c b/drivers/display/display_st7796s.c new file mode 100644 index 00000000000..131928b2fc7 --- /dev/null +++ b/drivers/display/display_st7796s.c @@ -0,0 +1,354 @@ +/* + * Copyright 2023, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT sitronix_st7796s + +#include +#include +#include +#include +#include +#include + +#include +LOG_MODULE_REGISTER(display_st7796s, CONFIG_DISPLAY_LOG_LEVEL); + +#include "display_st7796s.h" + +/* Magic numbers used to lock/unlock command settings */ +#define ST7796S_UNLOCK_1 0xC3 +#define ST7796S_UNLOCK_2 0x96 + +#define ST7796S_LOCK_1 0x3C +#define ST7796S_LOCK_2 0x69 + +#define ST7796S_PIXEL_SIZE 2 /* Only 16 bit color mode supported with this driver */ + +struct st7796s_config { + const struct device *mipi_dbi; + const struct mipi_dbi_config dbi_config; + const struct gpio_dt_spec cmd_data_gpio; + const struct gpio_dt_spec reset_gpio; + uint16_t width; + uint16_t height; + bool inverted; /* Display color inversion */ + /* Display configuration parameters */ + uint8_t dic; /* Display inversion control */ + uint8_t frmctl1[2]; /* Frame rate control, normal mode */ + uint8_t frmctl2[2]; /* Frame rate control, idle mode */ + uint8_t frmctl3[2]; /* Frame rate control, partial mode */ + uint8_t bpc[4]; /* Blanking porch control */ + uint8_t dfc[4]; /* Display function control */ + uint8_t pwr1[2]; /* Power control 1 */ + uint8_t pwr2; /* Power control 2 */ + uint8_t pwr3; /* Power control 3 */ + uint8_t vcmpctl; /* VCOM control */ + uint8_t doca[8]; /* Display output ctrl */ + uint8_t pgc[14]; /* Positive gamma control */ + uint8_t ngc[14]; /* Negative gamma control */ + uint8_t madctl; /* Memory data access control */ +}; + +static int st7796s_send_cmd(const struct device *dev, + uint8_t cmd, const uint8_t *data, size_t len) +{ + const struct st7796s_config *config = dev->config; + + return mipi_dbi_command_write(config->mipi_dbi, &config->dbi_config, + cmd, data, len); +} + +static int st7796s_set_cursor(const struct device *dev, + const uint16_t x, const uint16_t y, + const uint16_t width, const uint16_t height) +{ + uint16_t addr_data[2]; + int ret; + + /* Column address */ + addr_data[0] = sys_cpu_to_be16(x); + addr_data[1] = sys_cpu_to_be16(x + width - 1); + + ret = st7796s_send_cmd(dev, ST7796S_CMD_CASET, + (uint8_t *)addr_data, sizeof(addr_data)); + if (ret < 0) { + return ret; + } + + /* Row address */ + addr_data[0] = sys_cpu_to_be16(y); + addr_data[1] = sys_cpu_to_be16(y + height - 1); + ret = st7796s_send_cmd(dev, ST7796S_CMD_RASET, + (uint8_t *)addr_data, sizeof(addr_data)); + return ret; +} + +static int st7796s_blanking_on(const struct device *dev) +{ + return st7796s_send_cmd(dev, ST7796S_CMD_DISPOFF, NULL, 0); +} + +static int st7796s_blanking_off(const struct device *dev) +{ + return st7796s_send_cmd(dev, ST7796S_CMD_DISPON, NULL, 0); +} + + +static int st7796s_write(const struct device *dev, + const uint16_t x, + const uint16_t y, + const struct display_buffer_descriptor *desc, + const void *buf) +{ + const struct st7796s_config *config = dev->config; + int ret; + struct display_buffer_descriptor mipi_desc; + enum display_pixel_format pixfmt; + + ret = st7796s_set_cursor(dev, x, y, desc->width, desc->height); + if (ret < 0) { + return ret; + } + + mipi_desc.buf_size = desc->width * desc->height * ST7796S_PIXEL_SIZE; + + ret = mipi_dbi_command_write(config->mipi_dbi, + &config->dbi_config, ST7796S_CMD_RAMWR, + NULL, 0); + if (ret < 0) { + return ret; + } + + if (config->madctl & ST7796S_MADCTL_BGR) { + /* Zephyr treats RGB565 as BGR565 */ + pixfmt = PIXEL_FORMAT_RGB_565; + } else { + pixfmt = PIXEL_FORMAT_BGR_565; + } + + return mipi_dbi_write_display(config->mipi_dbi, + &config->dbi_config, buf, + &mipi_desc, pixfmt); +} + +static void st7796s_get_capabilities(const struct device *dev, + struct display_capabilities *capabilities) +{ + const struct st7796s_config *config = dev->config; + + memset(capabilities, 0, sizeof(struct display_capabilities)); + + if (config->madctl & ST7796S_MADCTL_BGR) { + /* Zephyr treats RGB565 as BGR565 */ + capabilities->current_pixel_format = PIXEL_FORMAT_RGB_565; + } else { + capabilities->current_pixel_format = PIXEL_FORMAT_BGR_565; + } + capabilities->x_resolution = config->width; + capabilities->y_resolution = config->height; + capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL; +} + +static int st7796s_lcd_config(const struct device *dev) +{ + const struct st7796s_config *config = dev->config; + int ret; + uint8_t param; + + /* Unlock display configuration */ + param = ST7796S_UNLOCK_1; + ret = st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param)); + if (ret < 0) { + return ret; + } + + param = ST7796S_UNLOCK_2; + ret = st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_DIC, &config->dic, sizeof(config->dic)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_FRMCTR1, config->frmctl1, + sizeof(config->frmctl1)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_FRMCTR2, config->frmctl2, + sizeof(config->frmctl2)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_FRMCTR3, config->frmctl3, + sizeof(config->frmctl3)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_BPC, config->bpc, sizeof(config->bpc)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_DFC, config->dfc, sizeof(config->dfc)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_PWR1, config->pwr1, sizeof(config->pwr1)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_PWR2, &config->pwr2, sizeof(config->pwr2)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_PWR3, &config->pwr3, sizeof(config->pwr3)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_VCMPCTL, &config->vcmpctl, + sizeof(config->vcmpctl)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_DOCA, config->doca, + sizeof(config->doca)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_PGC, config->pgc, sizeof(config->pgc)); + if (ret < 0) { + return ret; + } + + ret = st7796s_send_cmd(dev, ST7796S_CMD_NGC, config->ngc, sizeof(config->ngc)); + if (ret < 0) { + return ret; + } + + /* Lock display configuration */ + param = ST7796S_LOCK_1; + ret = st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param)); + if (ret < 0) { + return ret; + } + + param = ST7796S_LOCK_2; + return st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param)); +} + +static int st7796s_init(const struct device *dev) +{ + const struct st7796s_config *config = dev->config; + int ret; + uint8_t param; + + /* Since VDDI comes up before reset pin is low, we must reset display + * state. Pulse for 100 MS, per datasheet + */ + ret = mipi_dbi_reset(config->mipi_dbi, 100); + if (ret < 0) { + return ret; + } + /* Delay an additional 100ms after reset */ + k_msleep(100); + + /* Configure controller parameters */ + ret = st7796s_lcd_config(dev); + if (ret < 0) { + LOG_ERR("Could not set LCD configuration (%d)", ret); + return ret; + } + + if (config->inverted) { + ret = st7796s_send_cmd(dev, ST7796S_CMD_INVON, NULL, 0); + } else { + ret = st7796s_send_cmd(dev, ST7796S_CMD_INVOFF, NULL, 0); + } + if (ret < 0) { + return ret; + } + + param = ST7796S_CONTROL_16BIT; + ret = st7796s_send_cmd(dev, ST7796S_CMD_COLMOD, ¶m, sizeof(param)); + if (ret < 0) { + return ret; + } + + param = config->madctl; + ret = st7796s_send_cmd(dev, ST7796S_CMD_MADCTL, ¶m, sizeof(param)); + if (ret < 0) { + return ret; + } + + /* Exit sleep */ + st7796s_send_cmd(dev, ST7796S_CMD_SLPOUT, NULL, 0); + /* Delay 5ms after sleep out command, per datasheet */ + k_msleep(5); + /* Turn on display */ + st7796s_send_cmd(dev, ST7796S_CMD_DISPON, NULL, 0); + + return 0; +} + +static const struct display_driver_api st7796s_api = { + .blanking_on = st7796s_blanking_on, + .blanking_off = st7796s_blanking_off, + .write = st7796s_write, + .get_capabilities = st7796s_get_capabilities, +}; + + +#define ST7796S_INIT(n) \ + static const struct st7796s_config st7796s_config_##n = { \ + .mipi_dbi = DEVICE_DT_GET(DT_INST_PARENT(n)), \ + .dbi_config = { \ + .config = MIPI_DBI_SPI_CONFIG_DT( \ + DT_DRV_INST(n), \ + SPI_OP_MODE_MASTER | \ + SPI_WORD_SET(8), \ + 0), \ + .mode = MIPI_DBI_MODE_SPI_4WIRE, \ + }, \ + .width = DT_INST_PROP(n, width), \ + .height = DT_INST_PROP(n, height), \ + .inverted = DT_INST_PROP(n, color_invert), \ + .dic = DT_INST_ENUM_IDX(n, invert_mode), \ + .frmctl1 = DT_INST_PROP(n, frmctl1), \ + .frmctl2 = DT_INST_PROP(n, frmctl2), \ + .frmctl3 = DT_INST_PROP(n, frmctl3), \ + .bpc = DT_INST_PROP(n, bpc), \ + .dfc = DT_INST_PROP(n, dfc), \ + .pwr1 = DT_INST_PROP(n, pwr1), \ + .pwr2 = DT_INST_PROP(n, pwr2), \ + .pwr3 = DT_INST_PROP(n, pwr3), \ + .vcmpctl = DT_INST_PROP(n, vcmpctl), \ + .doca = DT_INST_PROP(n, doca), \ + .pgc = DT_INST_PROP(n, pgc), \ + .ngc = DT_INST_PROP(n, ngc), \ + .madctl = DT_INST_PROP(n, madctl), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, st7796s_init, \ + NULL, \ + NULL, \ + &st7796s_config_##n, \ + POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, \ + &st7796s_api); + +DT_INST_FOREACH_STATUS_OKAY(ST7796S_INIT) diff --git a/drivers/display/display_st7796s.h b/drivers/display/display_st7796s.h new file mode 100644 index 00000000000..7b0be000107 --- /dev/null +++ b/drivers/display/display_st7796s.h @@ -0,0 +1,40 @@ +/* + * Copyright 2023, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DRIVERS_DISPLAY_ST7796S_H_ +#define _ZEPHYR_DRIVERS_DISPLAY_ST7796S_H_ + +#define ST7796S_CMD_SLPIN 0x10 /* Sleep in */ +#define ST7796S_CMD_SLPOUT 0x11 /* Sleep out */ +#define ST7796S_CMD_INVOFF 0x20 /* Display inversion off */ +#define ST7796S_CMD_INVON 0x21 /* Display inversion on */ +#define ST7796S_CMD_CASET 0x2A /* Column address set */ +#define ST7796S_CMD_RASET 0x2B /* Row address set */ +#define ST7796S_CMD_RAMWR 0x2C /* Memory write */ +#define ST7796S_CMD_DISPOFF 0x28 /* Display off */ +#define ST7796S_CMD_DISPON 0x29 /* Display on */ +#define ST7796S_CMD_MADCTL 0x36 /* Memory data access control */ +#define ST7796S_CMD_COLMOD 0x3A /* Interface pixel format */ +#define ST7796S_CMD_FRMCTR1 0xB1 /* Frame rate control 1 (normal mode) */ +#define ST7796S_CMD_FRMCTR2 0xB2 /* Frame rate control 2 (idle mode) */ +#define ST7796S_CMD_FRMCTR3 0xB3 /* Frame rate control 3 (partial mode) */ +#define ST7796S_CMD_DIC 0xB4 /* Display inversion control */ +#define ST7796S_CMD_BPC 0xB5 /* Blanking porch control */ +#define ST7796S_CMD_DFC 0xB6 /* Display function control */ +#define ST7796S_CMD_PWR1 0xC0 /* Power control 1 */ +#define ST7796S_CMD_PWR2 0xC1 /* Power control 1 */ +#define ST7796S_CMD_PWR3 0xC2 /* Power control 1 */ +#define ST7796S_CMD_VCMPCTL 0xC5 /* VCOM control */ +#define ST7796S_CMD_PGC 0xE0 /* Positive gamma control */ +#define ST7796S_CMD_NGC 0xE1 /* Negative gamma control */ +#define ST7796S_CMD_DOCA 0xE8 /* Display output control adjust */ +#define ST7796S_CMD_CSCON 0xF0 /* Command set control */ + +#define ST7796S_CONTROL_16BIT 0x5 /* Sets control interface to 16 bit mode */ +#define ST7796S_MADCTL_BGR BIT(3) /* Sets BGR color mode */ + + +#endif /* _ZEPHYR_DRIVERS_DISPLAY_ST7796S_H_ */ From b5b5291df2cb2d901f7d6d21dd33c1a9bb434937 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 8 Mar 2024 14:59:24 -0600 Subject: [PATCH 1936/2402] tests: drivers: build_all: add st7796s to display test Add entry for st7796s to display build_all test, so that the controller driver will be built by CI. Signed-off-by: Daniel DeGrasse --- tests/drivers/build_all/display/app.overlay | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tests/drivers/build_all/display/app.overlay b/tests/drivers/build_all/display/app.overlay index f287255274e..cd6669e4516 100644 --- a/tests/drivers/build_all/display/app.overlay +++ b/tests/drivers/build_all/display/app.overlay @@ -40,6 +40,19 @@ width = <320>; height = <240>; }; + + test_mipi_dbi_st7796s: st7796s@1 { + compatible = "sitronix,st7796s"; + reg = <1>; + mipi-max-frequency = <25000000>; + height = <320>; + width = <480>; + /* Use dummy values for PCG and NGC, + * As this won't drive a real panel + */ + pgc = [F0 06 0B 07 06 05 2E 33 47 3A 17 16 2E 31]; + ngc = [F0 09 0D 09 08 23 2E 33 46 38 13 13 2C 32]; + }; }; From f61b003b07c178ed8ae8309196f668e4cd695c07 Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Mon, 18 Mar 2024 16:01:51 +0100 Subject: [PATCH 1937/2402] cmake: conditionally enable shared library support When CONFIG_LLEXT is enabled, the Zephyr platform needs to enable dynamic library support. This is done by setting the `TARGET_SUPPORTS_SHARED_LIBS` property to `TRUE` in the global property scope. Signed-off-by: Luca Burelli --- cmake/modules/FindTargetTools.cmake | 10 +++++++--- cmake/modules/Platform/Zephyr.cmake | 13 +++++++++++++ 2 files changed, 20 insertions(+), 3 deletions(-) create mode 100644 cmake/modules/Platform/Zephyr.cmake diff --git a/cmake/modules/FindTargetTools.cmake b/cmake/modules/FindTargetTools.cmake index 82c474f91e4..f74f10f2845 100644 --- a/cmake/modules/FindTargetTools.cmake +++ b/cmake/modules/FindTargetTools.cmake @@ -31,7 +31,8 @@ endif() set(CMAKE_C_COMPILER_FORCED 1) set(CMAKE_CXX_COMPILER_FORCED 1) -# No official documentation exists for the "Generic" value, except their wiki. +# https://cmake.org/cmake/help/latest/variable/CMAKE_SYSTEM_NAME.html: +# The name of the operating system for which CMake is to build. # # https://gitlab.kitware.com/cmake/community/wikis/doc/cmake/CrossCompiling: # CMAKE_SYSTEM_NAME : this one is mandatory, it is the name of the target @@ -40,7 +41,10 @@ set(CMAKE_CXX_COMPILER_FORCED 1) # variable is used for constructing the file names of the platform files # like Linux.cmake or Windows-gcc.cmake. If your target is an embedded # system without OS set CMAKE_SYSTEM_NAME to "Generic". -set(CMAKE_SYSTEM_NAME Generic) +# +# This will force CMake to load cmake/modules/Platform/Zephyr.cmake, +# allowing Zephyr-specific embedded system features to be enabled. +set(CMAKE_SYSTEM_NAME Zephyr) # https://cmake.org/cmake/help/latest/variable/CMAKE_SYSTEM_PROCESSOR.html: # The name of the CPU CMake is building for. @@ -74,7 +78,7 @@ else() set(CMAKE_CXX_BYTE_ORDER LITTLE_ENDIAN) endif() -# We are not building dynamically loadable libraries +# Do not build dynamically loadable libraries by default set(BUILD_SHARED_LIBS OFF) # Custom targets for compiler and linker flags. diff --git a/cmake/modules/Platform/Zephyr.cmake b/cmake/modules/Platform/Zephyr.cmake new file mode 100644 index 00000000000..17b55284094 --- /dev/null +++ b/cmake/modules/Platform/Zephyr.cmake @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024, Arduino SA + +# Perform the same initialization as the Generic platform, then enable +# dynamic library support if CONFIG_LLEXT is enabled. + +include(Platform/Generic) + +# Enable dynamic library support when CONFIG_LLEXT is enabled. +if(CONFIG_LLEXT) + set_property(GLOBAL PROPERTY TARGET_SUPPORTS_SHARED_LIBS true) +endif() From 1e47c64266a53d4df0a9593b21c686045ac9e22a Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Mon, 22 Jan 2024 18:12:21 +0100 Subject: [PATCH 1938/2402] llext: use CMake shared library support on Xtensa This change reworks the Xtensa support in llext to use CMake's native shared library support, instead of manually running "gcc -shared". This change minimizes the differences in llext handling by defining appropriate CMake targets for the different architectures. Signed-off-by: Luca Burelli --- cmake/compiler/gcc/target_xtensa.cmake | 1 - cmake/modules/extensions.cmake | 107 ++++++++++++++++--------- 2 files changed, 68 insertions(+), 40 deletions(-) diff --git a/cmake/compiler/gcc/target_xtensa.cmake b/cmake/compiler/gcc/target_xtensa.cmake index 177830427db..5321204c2df 100644 --- a/cmake/compiler/gcc/target_xtensa.cmake +++ b/cmake/compiler/gcc/target_xtensa.cmake @@ -17,5 +17,4 @@ set(LLEXT_APPEND_FLAGS -fPIC -nostdlib -nodefaultlibs - -shared ) diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index 1444229047f..8a3b065821a 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -5099,6 +5099,12 @@ endmacro() # loadable extensions (llexts). # +# Usage: +# add_llext_target( +# OUTPUT +# SOURCES +# ) +# # Add a custom target that compiles a single source file to a .llext file. # # Output and source files must be specified using the OUTPUT and SOURCES @@ -5112,6 +5118,14 @@ endmacro() # The C_FLAGS argument can be used to pass additional compiler flags to the # compilation of this particular llext. # +# The following custom properties of are defined and can be +# retrieved using the get_target_property() function: +# +# - lib_target Target name for the source compilation and/or link step. +# - lib_output The binary file resulting from compilation and/or +# linking steps. +# - pkg_output The final .llext file. +# # Example usage: # add_llext_target(hello_world # OUTPUT ${PROJECT_BINARY_DIR}/hello_world.llext @@ -5131,10 +5145,8 @@ function(add_llext_target target_name) message(FATAL_ERROR "add_llext_target: CONFIG_LLEXT must be enabled") endif() - # Output file must be provided - if(NOT LLEXT_OUTPUT) - message(FATAL_ERROR "add_llext_target: OUTPUT argument must be provided") - endif() + # Source and output files must be provided + zephyr_check_arguments_required_all("add_llext_target" LLEXT OUTPUT SOURCES) # Source list length must currently be 1 list(LENGTH LLEXT_SOURCES source_count) @@ -5142,15 +5154,8 @@ function(add_llext_target target_name) message(FATAL_ERROR "add_llext_target: only one source file is supported") endif() - set(output_file ${LLEXT_OUTPUT}) + set(llext_pkg_output ${LLEXT_OUTPUT}) set(source_file ${LLEXT_SOURCES}) - get_filename_component(output_name ${output_file} NAME) - - # Add user-visible target and dependency - add_custom_target(${target_name} - COMMENT "Compiling ${output_name}" - DEPENDS ${output_file} - ) # Convert the LLEXT_REMOVE_FLAGS list to a regular expression, and use it to # filter out these flags from the Zephyr target settings @@ -5166,62 +5171,86 @@ function(add_llext_target target_name) "$" ) - # Compile the source file to an object file using current Zephyr settings - # but a different set of flags - add_library(${target_name}_lib OBJECT ${source_file}) - target_compile_definitions(${target_name}_lib PRIVATE + # Compile the source file using current Zephyr settings but a different + # set of flags. + # This is currently arch-specific since the ARM loader for .llext files + # expects object file format, while the Xtensa one uses shared libraries. + set(llext_lib_target ${target_name}_llext_lib) + if(CONFIG_ARM) + + # Create an object library to compile the source file + add_library(${llext_lib_target} OBJECT ${source_file}) + set(llext_lib_output $) + + elseif(CONFIG_XTENSA) + + # Create a shared library + add_library(${llext_lib_target} SHARED ${source_file}) + set(llext_lib_output $) + + # Add the llext flags to the linking step as well + target_link_options(${llext_lib_target} PRIVATE + ${LLEXT_APPEND_FLAGS} + ) + + endif() + + target_compile_definitions(${llext_lib_target} PRIVATE $ ) - target_compile_options(${target_name}_lib PRIVATE + target_compile_options(${llext_lib_target} PRIVATE ${zephyr_filtered_flags} ${LLEXT_APPEND_FLAGS} ${LLEXT_C_FLAGS} ) - target_include_directories(${target_name}_lib PRIVATE + target_include_directories(${llext_lib_target} PRIVATE $ ) - target_include_directories(${target_name}_lib SYSTEM PUBLIC + target_include_directories(${llext_lib_target} SYSTEM PUBLIC $ ) - add_dependencies(${target_name}_lib + add_dependencies(${llext_lib_target} zephyr_interface zephyr_generated_headers ) - # Arch-specific conversion of the object file to an llext + # Arch-specific packaging of the built binary file into an .llext file if(CONFIG_ARM) - # No conversion required, simply copy the object file + # No packaging required, simply copy the object file add_custom_command( - OUTPUT ${output_file} - COMMAND ${CMAKE_COMMAND} -E copy $ ${output_file} - DEPENDS ${target_name}_lib $ + OUTPUT ${llext_pkg_output} + COMMAND ${CMAKE_COMMAND} -E copy ${llext_lib_output} ${llext_pkg_output} + DEPENDS ${llext_lib_target} ${llext_lib_output} ) elseif(CONFIG_XTENSA) - # Generate an intermediate file name - get_filename_component(output_dir ${output_file} DIRECTORY) - get_filename_component(output_name_we ${output_file} NAME_WE) - set(pre_output_file ${output_dir}/${output_name_we}.pre.llext) - - # Need to convert the object file to a shared library, then strip some sections + # Need to strip the shared library of some sections add_custom_command( - OUTPUT ${output_file} - BYPRODUCTS ${pre_output_file} - COMMAND ${CMAKE_C_COMPILER} ${LLEXT_APPEND_FLAGS} - -o ${pre_output_file} - $ + OUTPUT ${llext_pkg_output} COMMAND $ $ $.xt.* - $${pre_output_file} - $${output_file} + $${llext_lib_output} + $${llext_pkg_output} $ - DEPENDS ${target_name}_lib $ + DEPENDS ${llext_lib_target} ${llext_lib_output} ) else() message(FATAL_ERROR "add_llext_target: unsupported architecture") endif() + + # Add user-visible target and dependency, and fill in properties + get_filename_component(output_name ${llext_pkg_output} NAME) + add_custom_target(${target_name} + COMMENT "Generating ${output_name}" + DEPENDS ${llext_pkg_output} + ) + set_target_properties(${target_name} PROPERTIES + lib_target ${llext_lib_target} + lib_output ${llext_lib_output} + pkg_output ${llext_pkg_output} + ) endfunction() From f50d476ee6bdab4cfa602af5a10d7ff76cc1830a Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Thu, 1 Feb 2024 11:40:22 +0100 Subject: [PATCH 1939/2402] llext: add llext_* configuration functions Remove the C_FLAGS argument from add_llext_target() and add a set of functions to configure the compilation and linking of an llext using the same API of the target_* functions. Signed-off-by: Luca Burelli --- cmake/modules/extensions.cmake | 43 ++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index 8a3b065821a..ff22c9e69eb 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -35,6 +35,8 @@ include(CheckCXXCompilerFlag) # 5.1. zephyr_linker* # 6 Function helper macros # 7 Linkable loadable extensions (llext) +# 7.1 llext_* configuration functions +# 7.2 add_llext_* build control functions ######################################################## # 1. Zephyr-aware extensions @@ -5099,6 +5101,38 @@ endmacro() # loadable extensions (llexts). # +# 7.1 Configuration functions +# +# The following functions simplify access to the compilation/link stage +# properties of an llext using the same API of the target_* functions. +# + +function(llext_compile_definitions target_name) + target_compile_definitions(${target_name}_llext_lib PRIVATE ${ARGN}) +endfunction() + +function(llext_compile_features target_name) + target_compile_features(${target_name}_llext_lib PRIVATE ${ARGN}) +endfunction() + +function(llext_compile_options target_name) + target_compile_options(${target_name}_llext_lib PRIVATE ${ARGN}) +endfunction() + +function(llext_include_directories target_name) + target_include_directories(${target_name}_llext_lib PRIVATE ${ARGN}) +endfunction() + +function(llext_link_options target_name) + target_link_options(${target_name}_llext_lib PRIVATE ${ARGN}) +endfunction() + +# 7.2 Build control functions +# +# The following functions add targets and subcommands to the build system +# to compile and link an llext. +# + # Usage: # add_llext_target( # OUTPUT @@ -5114,9 +5148,6 @@ endmacro() # in the Zephyr build, but with some important modifications. The list of # flags to remove and flags to append is controlled respectively by the # LLEXT_REMOVE_FLAGS and LLEXT_APPEND_FLAGS global variables. - -# The C_FLAGS argument can be used to pass additional compiler flags to the -# compilation of this particular llext. # # The following custom properties of are defined and can be # retrieved using the get_target_property() function: @@ -5130,14 +5161,13 @@ endmacro() # add_llext_target(hello_world # OUTPUT ${PROJECT_BINARY_DIR}/hello_world.llext # SOURCES ${PROJECT_SOURCE_DIR}/src/llext/hello_world.c -# C_FLAGS -Werror # ) # will compile the source file src/llext/hello_world.c to a file -# ${PROJECT_BINARY_DIR}/hello_world.llext, adding -Werror to the compilation. +# named "${PROJECT_BINARY_DIR}/hello_world.llext". # function(add_llext_target target_name) set(single_args OUTPUT) - set(multi_args SOURCES;C_FLAGS) + set(multi_args SOURCES) cmake_parse_arguments(PARSE_ARGV 1 LLEXT "${options}" "${single_args}" "${multi_args}") # Check that the llext subsystem is enabled for this build @@ -5201,7 +5231,6 @@ function(add_llext_target target_name) target_compile_options(${llext_lib_target} PRIVATE ${zephyr_filtered_flags} ${LLEXT_APPEND_FLAGS} - ${LLEXT_C_FLAGS} ) target_include_directories(${llext_lib_target} PRIVATE $ From 313c09bffbfaf4b556d217d4b2e4b069ab082324 Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Thu, 1 Feb 2024 11:40:22 +0100 Subject: [PATCH 1940/2402] llext: add support for build time custom commands This patch adds support for custom commands to be executed during the build of an llext target. The commands can be executed at different points in the build process: - PRE_BUILD: Before the llext code is linked. - POST_BUILD: After the llext code is built, but before packaging it in an .llext file. - POST_PKG: After the llext file has been created. Note that PRE_BUILD is not supported for ARM targets, as in that case object files are used directly and there is no actual linking step. The commands can be added using the new add_llext_command() function. An example usage of it, along with some target properties, is added to the hello_world test case. Signed-off-by: Luca Burelli --- cmake/modules/extensions.cmake | 113 ++++++++++++++++++++++- tests/subsys/llext/simple/CMakeLists.txt | 10 ++ 2 files changed, 119 insertions(+), 4 deletions(-) diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index ff22c9e69eb..32f7531167e 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -5155,6 +5155,7 @@ endfunction() # - lib_target Target name for the source compilation and/or link step. # - lib_output The binary file resulting from compilation and/or # linking steps. +# - pkg_input The file to be used as input for the packaging step. # - pkg_output The final .llext file. # # Example usage: @@ -5243,14 +5244,35 @@ function(add_llext_target target_name) zephyr_generated_headers ) + # Set up an intermediate processing step between compilation and packaging + # to be used to support POST_BUILD commands on targets that do not use a + # dynamic library. + set(llext_proc_target ${target_name}_llext_proc) + set(llext_pkg_input ${PROJECT_BINARY_DIR}/${target_name}.llext.pkg_input) + add_custom_target(${llext_proc_target} DEPENDS ${llext_pkg_input}) + set_property(TARGET ${llext_proc_target} PROPERTY has_post_build_cmds 0) + + # By default this target must copy the `lib_output` binary file to the + # expected `pkg_input` location. If actual POST_BUILD commands are defined, + # they will take care of this and the default copy is replaced by a no-op. + set(has_post_build_cmds "$") + set(noop_cmd ${CMAKE_COMMAND} -E true) + set(copy_cmd ${CMAKE_COMMAND} -E copy ${llext_lib_output} ${llext_pkg_input}) + add_custom_command( + OUTPUT ${llext_pkg_input} + COMMAND "$" + DEPENDS ${llext_lib_target} ${llext_lib_output} + COMMAND_EXPAND_LISTS + ) + # Arch-specific packaging of the built binary file into an .llext file if(CONFIG_ARM) # No packaging required, simply copy the object file add_custom_command( OUTPUT ${llext_pkg_output} - COMMAND ${CMAKE_COMMAND} -E copy ${llext_lib_output} ${llext_pkg_output} - DEPENDS ${llext_lib_target} ${llext_lib_output} + COMMAND ${CMAKE_COMMAND} -E copy ${llext_pkg_input} ${llext_pkg_output} + DEPENDS ${llext_proc_target} ${llext_pkg_input} ) elseif(CONFIG_XTENSA) @@ -5261,10 +5283,10 @@ function(add_llext_target target_name) COMMAND $ $ $.xt.* - $${llext_lib_output} + $${llext_pkg_input} $${llext_pkg_output} $ - DEPENDS ${llext_lib_target} ${llext_lib_output} + DEPENDS ${llext_proc_target} ${llext_pkg_input} ) else() @@ -5280,6 +5302,89 @@ function(add_llext_target target_name) set_target_properties(${target_name} PROPERTIES lib_target ${llext_lib_target} lib_output ${llext_lib_output} + pkg_input ${llext_pkg_input} pkg_output ${llext_pkg_output} ) endfunction() + +# Usage: +# add_llext_command( +# TARGET +# PRE_BUILD | POST_BUILD | POST_PKG +# COMMAND [...] +# ) +# +# Add a custom command to an llext target that will be executed during +# the build. The command will be executed at the specified build step and +# can refer to 's properties for build-specific details. +# +# The differrent build steps are: +# - PRE_BUILD: Before the llext code is linked, if the architecture uses +# dynamic libraries. This step can access `lib_target` and +# its own properties. +# - POST_BUILD: After the llext code is built, but before packaging +# it in an .llext file. This step is expected to create a +# `pkg_input` file by reading the contents of `lib_output`. +# - POST_PKG: After the .llext file has been created. This can operate on +# the final llext file `pkg_output`. +# +# Anything else after COMMAND will be passed to add_custom_command() as-is +# (including multiple commands and other options). +function(add_llext_command) + set(options PRE_BUILD POST_BUILD POST_PKG) + set(single_args TARGET) + # COMMAND and other options are passed to add_custom_command() as-is + + cmake_parse_arguments(PARSE_ARGV 0 LLEXT "${options}" "${single_args}" "${multi_args}") + zephyr_check_arguments_required_all("add_llext_command" LLEXT TARGET) + + # Check the target exists and refers to an llext target + set(target_name ${LLEXT_TARGET}) + set(llext_lib_target ${target_name}_llext_lib) + set(llext_proc_target ${target_name}_llext_proc) + if(NOT TARGET ${llext_lib_target}) + message(FATAL_ERROR "add_llext_command: not an llext target: ${target_name}") + endif() + + # ARM uses an object file representation so there is no link step. + if(CONFIG_ARM AND LLEXT_PRE_BUILD) + message(FATAL_ERROR + "add_llext_command: PRE_BUILD not supported on this arch") + endif() + + # Determine the build step and the target to attach the command to + # based on the provided options + if(LLEXT_PRE_BUILD) + # > before the object files are linked: + # - execute user command(s) before the lib target's link step. + set(cmd_target ${llext_lib_target}) + set(build_step PRE_LINK) + elseif(LLEXT_POST_BUILD) + # > after linking, but before llext packaging: + # - stop default file copy to prevent user files from being clobbered; + # - execute user command(s) after the (now empty) `llext_proc_target`. + set_property(TARGET ${llext_proc_target} PROPERTY has_post_build_cmds 1) + set(cmd_target ${llext_proc_target}) + set(build_step POST_BUILD) + elseif(LLEXT_POST_PKG) + # > after the final llext binary is ready: + # - execute user command(s) after the main target is done. + set(cmd_target ${target_name}) + set(build_step POST_BUILD) + else() + message(FATAL_ERROR "add_llext_command: build step must be provided") + endif() + + # Check that the first unparsed argument is the word COMMAND + list(GET LLEXT_UNPARSED_ARGUMENTS 0 command_str) + if(NOT command_str STREQUAL "COMMAND") + message(FATAL_ERROR "add_llext_command: COMMAND argument must be provided") + endif() + + # Add the actual command(s) to the target + add_custom_command( + TARGET ${cmd_target} ${build_step} + ${LLEXT_UNPARSED_ARGUMENTS} + COMMAND_EXPAND_LISTS + ) +endfunction() diff --git a/tests/subsys/llext/simple/CMakeLists.txt b/tests/subsys/llext/simple/CMakeLists.txt index f134a78c1f0..5eae7b846fd 100644 --- a/tests/subsys/llext/simple/CMakeLists.txt +++ b/tests/subsys/llext/simple/CMakeLists.txt @@ -27,4 +27,14 @@ foreach(ext_name hello_world logging relative_jump object syscalls threads_kerne ) generate_inc_file_for_target(app ${ext_bin} ${ext_inc}) endforeach() + +# Add a dummy custom processing command to test add_llext_command +get_target_property(proc_in_file hello_world_ext lib_output) +get_target_property(proc_out_file hello_world_ext pkg_input) +add_llext_command( + TARGET hello_world_ext + POST_BUILD + COMMAND echo "dummy patching ${proc_in_file} to create ${proc_out_file}" + COMMAND ${CMAKE_COMMAND} -E copy ${proc_in_file} ${proc_out_file} +) endif() From d1591cd363d5cc23929fbd85ddbf79c4b106a377 Mon Sep 17 00:00:00 2001 From: Marcio Ribeiro Date: Tue, 19 Sep 2023 14:57:44 -0300 Subject: [PATCH 1941/2402] boards: esp32s3_devkitc: initial board support Initial board files created to support the esp32s3_devkitc board. Signed-off-by: Marcio Ribeiro --- .../esp32s3_devkitc/Kconfig.defconfig | 26 ++ .../esp32s3_devkitc/Kconfig.esp32s3_devkitc | 7 + .../esp32s3_devkitc/Kconfig.sysbuild | 10 + boards/espressif/esp32s3_devkitc/board.cmake | 9 + boards/espressif/esp32s3_devkitc/board.yml | 5 + .../espressif/esp32s3_devkitc/doc/index.rst | 286 ++++++++++++++++++ .../esp32s3_devkitc-pinctrl.dtsi | 73 +++++ .../esp32s3_devkitc_esp32s3_appcpu.dts | 73 +++++ .../esp32s3_devkitc_esp32s3_appcpu.yaml | 27 ++ .../esp32s3_devkitc_esp32s3_appcpu_defconfig | 4 + .../esp32s3_devkitc_esp32s3_procpu.dts | 179 +++++++++++ .../esp32s3_devkitc_esp32s3_procpu.yaml | 23 ++ .../esp32s3_devkitc_esp32s3_procpu_defconfig | 9 + .../esp32s3_devkitc/support/openocd.cfg | 7 + 14 files changed, 738 insertions(+) create mode 100644 boards/espressif/esp32s3_devkitc/Kconfig.defconfig create mode 100644 boards/espressif/esp32s3_devkitc/Kconfig.esp32s3_devkitc create mode 100644 boards/espressif/esp32s3_devkitc/Kconfig.sysbuild create mode 100644 boards/espressif/esp32s3_devkitc/board.cmake create mode 100644 boards/espressif/esp32s3_devkitc/board.yml create mode 100644 boards/espressif/esp32s3_devkitc/doc/index.rst create mode 100644 boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi create mode 100644 boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu.dts create mode 100644 boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu.yaml create mode 100644 boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu_defconfig create mode 100644 boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu.dts create mode 100644 boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu.yaml create mode 100644 boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu_defconfig create mode 100644 boards/espressif/esp32s3_devkitc/support/openocd.cfg diff --git a/boards/espressif/esp32s3_devkitc/Kconfig.defconfig b/boards/espressif/esp32s3_devkitc/Kconfig.defconfig new file mode 100644 index 00000000000..9b109ab4525 --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/Kconfig.defconfig @@ -0,0 +1,26 @@ +# ESP32S3 DevKitC board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32S3_DEVKITC_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ESP32S3_DEVKITC_ESP32S3_PROCPU + +if BOARD_ESP32S3_DEVKITC_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_ESP32S3_DEVKITC_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitc/Kconfig.esp32s3_devkitc b/boards/espressif/esp32s3_devkitc/Kconfig.esp32s3_devkitc new file mode 100644 index 00000000000..fc15b1c4614 --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/Kconfig.esp32s3_devkitc @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_DEVKITC + select SOC_ESP32S3_WROOM_N8 + select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_DEVKITC_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_DEVKITC_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitc/Kconfig.sysbuild b/boards/espressif/esp32s3_devkitc/Kconfig.sysbuild new file mode 100644 index 00000000000..8d3acb9e11d --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/espressif/esp32s3_devkitc/board.cmake b/boards/espressif/esp32s3_devkitc/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/espressif/esp32s3_devkitc/board.yml b/boards/espressif/esp32s3_devkitc/board.yml new file mode 100644 index 00000000000..a949122fd57 --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s3_devkitc + vendor: espressif + socs: + - name: esp32s3 diff --git a/boards/espressif/esp32s3_devkitc/doc/index.rst b/boards/espressif/esp32s3_devkitc/doc/index.rst new file mode 100644 index 00000000000..4be477a51dd --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/doc/index.rst @@ -0,0 +1,286 @@ +.. _esp32s3_devkitc: + +ESP32S3-DevKitC +############### + +Overview +******** + +The ESP32-S3-DevKitC is an entry-level development board equipped with either ESP32-S3-WROOM-1 +or ESP32-S3-WROOM-1U, a module named for its small size. This board integrates complete Wi-Fi +and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitC`_ + +Hardware +******** + +ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi +and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor +(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, +RF module, and numerous peripherals. + +ESP32-S3 DevKitC includes the following features: + +- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz +- Additional vector instructions support for AI acceleration +- 512KB of SRAM +- 384KB of ROM +- Wi-Fi 802.11b/g/n +- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate + +Digital interfaces: + +- 45 programmable GPIOs +- 4x SPI +- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411 +- 1x DVP 8-bit ~16-bit camera interface +- 3x UART +- 2x I2C +- 2x I2S +- 1x RMT (TX/RX) +- 1x pulse counter +- LED PWM controller, up to 8 channels +- 1x full-speed USB OTG +- 1x USB Serial/JTAG controller +- 2x MCPWM +- 1x SDIO host controller with 2 slots +- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels +- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) +- Addressable RGB LED, driven by GPIO38. + +Analog interfaces: + +- 2x 12-bit SAR ADCs, up to 20 channels +- 1x temperature sensor +- 14x touch sensing IOs + +Timers: + +- 4x 54-bit general-purpose timers +- 1x 52-bit system timer +- 3x watchdog timers + +Low Power: + +- Power Management Unit with five power modes +- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM + +Security: + +- Secure boot +- Flash encryption +- 4-Kbit OTP, up to 1792 bits for users +- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) + +Asymmetric Multiprocessing (AMP) +******************************** + +ESP32S3-DevKitC allows 2 different applications to be executed in ESP32-S3 SoC. Due to its dual-core +architecture, each core can be enabled to execute customized tasks in stand-alone mode +and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. + +For more information, check the datasheet at `ESP32-S3 Datasheet`_. + +Supported Features +================== + +Current Zephyr's ESP32-S3-DevKitC board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32-S3 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32s3_devkitc/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitc/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32s3_devkitc`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitc/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s3_devkitc + +Debugging +********* + +ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32-S3`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitc/esp32s3/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitc/esp32s3/procpu + :goals: debug + +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`ESP32-S3 DevKitC`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitc-1.html + +References +********** + +.. _ESP32-S3 DevKitC User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitc-1.html +.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf +.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi new file mode 100644 index 00000000000..5f3fbe8b239 --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu.dts new file mode 100644 index 00000000000..5e5a1e2be48 --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "Espressif ESP32S3-DevkitC APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu.yaml b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu.yaml new file mode 100644 index 00000000000..d62dc5ff3fd --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32s3_devkitc/esp32s3/appcpu +name: ESP32-S3 DevKitC APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu_defconfig b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000..9abf2ff0430 --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu.dts new file mode 100644 index 00000000000..253731fc721 --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu.dts @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include "espressif/esp32s3/esp32s3_wroom_n8.dtsi" +#include "esp32s3_devkitc-pinctrl.dtsi" +#include +#include + +/ { + model = "Espressif ESP32S3-DevkitC PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + uart-0 = &uart0; + sw0 = &button0; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "disabled"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; + bus-speed = <125000>; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu.yaml b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu.yaml new file mode 100644 index 00000000000..c4f58917576 --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu.yaml @@ -0,0 +1,23 @@ +identifier: esp32s3_devkitc/esp32s3/procpu +name: ESP32-S3 DevKitC PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu_defconfig b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu_defconfig new file mode 100644 index 00000000000..d789bab1824 --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_esp32s3_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/espressif/esp32s3_devkitc/support/openocd.cfg b/boards/espressif/esp32s3_devkitc/support/openocd.cfg new file mode 100644 index 00000000000..2f740b4a36a --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] From 2b549daabc9d2cddda3e22c6ec1f5b27ea1997ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20G=C5=82=C4=85b?= Date: Fri, 5 Apr 2024 13:21:35 +0200 Subject: [PATCH 1942/2402] tests: drivers: uart: uart_mix_fifo_poll: Add nRF54L15 to platform allow MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nRF54L15 to the platform allow list. Overlay file already exists. Signed-off-by: Sebastian Głąb --- tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml index 39a55a4a62a..7736e085f34 100644 --- a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml +++ b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml @@ -8,6 +8,7 @@ common: - nrf52840dk/nrf52840 - nrf9160dk/nrf9160 - nrf5340dk/nrf5340/cpuapp + - nrf54l15pdk/nrf54l15/cpuapp - nrf52_bsim integration_platforms: - nrf52840dk/nrf52840 From 902351a2e5117cdc93061eccd359e34662846a76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Fri, 22 Mar 2024 16:32:22 +0100 Subject: [PATCH 1943/2402] modules: hal_nordic: Add missing nrfx_config entries for nRF54L15 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nrfx_grtc related entries that were introduced in nrfx 3.4.0, especially NRFX_GRTC_CONFIG_AUTOSTART that should be by default set to 1. Signed-off-by: Andrzej Głąbek --- .../nrfx_config_nrf54l15_enga_application.h | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54l15_enga_application.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54l15_enga_application.h index a694a07955d..57e469686ec 100644 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54l15_enga_application.h +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54l15_enga_application.h @@ -249,6 +249,33 @@ #define NRFX_GRTC_ENABLED 0 #endif +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 1 +#endif + /** * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS * From 4399750b293fd9930f64630d2b92b64c2b66c930 Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Wed, 8 Nov 2023 22:21:34 +0100 Subject: [PATCH 1944/2402] boards: st: nucleo_wb55rg: add mcuboot-{led0,button0} aliases This adds DT aliases for LED and button used in recovery mode of the MCUboot bootloader, on the 'nucleo_wb55rg' board. Signed-off-by: Piotr Dymacz --- boards/st/nucleo_wb55rg/nucleo_wb55rg.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts index bdc61c71ad9..08cfaf40eba 100644 --- a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts +++ b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts @@ -69,6 +69,8 @@ die-temp0 = &die_temp; volt-sensor0 = &vref; volt-sensor1 = &vbat; + mcuboot-led0 = &blue_led_1; + mcuboot-button0 = &user_button_1; }; }; From c4815254c0de92fb61f0d182ff3f5dbf8127b0f0 Mon Sep 17 00:00:00 2001 From: Armin Brauns Date: Wed, 27 Mar 2024 13:52:08 +0000 Subject: [PATCH 1945/2402] usb: stm32: fix calculation of TX FIFO sizes The RX FIFO size is in words, so needs to be subtracted from the total memory size *after* it's divided by 4. Fixes #70789. Signed-off-by: Armin Brauns --- drivers/usb/device/usb_dc_stm32.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c index 13131061610..7be05d95ee3 100644 --- a/drivers/usb/device/usb_dc_stm32.c +++ b/drivers/usb/device/usb_dc_stm32.c @@ -131,10 +131,10 @@ static const struct gpio_dt_spec ulpi_reset = #define TX_FIFO_NUM USB_NUM_BIDIR_ENDPOINTS /* We need a minimum size for RX FIFO */ -#define USB_FIFO_RX_MIN 160 +#define RX_FIFO_EP_WORDS 160 /* 4-byte words TX FIFO */ -#define TX_FIFO_WORDS ((USB_RAM_SIZE - USB_FIFO_RX_MIN - 64) / 4) +#define TX_FIFO_WORDS ((USB_RAM_SIZE - 64) / 4 - RX_FIFO_EP_WORDS) /* Allocate FIFO memory evenly between the TX FIFOs */ /* except the first TX endpoint need only 64 bytes */ @@ -446,7 +446,7 @@ static int usb_dc_stm32_init(void) #else /* USB_OTG_FS */ /* TODO: make this dynamic (depending usage) */ - HAL_PCDEx_SetRxFiFo(&usb_dc_stm32_state.pcd, USB_FIFO_RX_MIN); + HAL_PCDEx_SetRxFiFo(&usb_dc_stm32_state.pcd, RX_FIFO_EP_WORDS); for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) { if (i == 0) { /* first endpoint need only 64 byte for EP_TYPE_CTRL */ From e69ce5bb430cfe74f2efcb057e33d7b621aa1dbe Mon Sep 17 00:00:00 2001 From: Armin Brauns Date: Wed, 27 Mar 2024 13:52:42 +0000 Subject: [PATCH 1946/2402] usb: stm32: clarify calculation of FIFO sizes Magic constants throughout the code made this difficult to reason about, especially with two different units of measurement (bytes and words) at play. Signed-off-by: Armin Brauns --- drivers/usb/device/usb_dc_stm32.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c index 7be05d95ee3..75ce9442f8e 100644 --- a/drivers/usb/device/usb_dc_stm32.c +++ b/drivers/usb/device/usb_dc_stm32.c @@ -130,14 +130,14 @@ static const struct gpio_dt_spec ulpi_reset = /* We need n TX IN FIFOs */ #define TX_FIFO_NUM USB_NUM_BIDIR_ENDPOINTS -/* We need a minimum size for RX FIFO */ +/* We need a minimum size for RX FIFO - exact number seemingly determined through trial and error */ #define RX_FIFO_EP_WORDS 160 -/* 4-byte words TX FIFO */ -#define TX_FIFO_WORDS ((USB_RAM_SIZE - 64) / 4 - RX_FIFO_EP_WORDS) - /* Allocate FIFO memory evenly between the TX FIFOs */ /* except the first TX endpoint need only 64 bytes */ +#define TX_FIFO_EP_0_WORDS 16 +#define TX_FIFO_WORDS (USB_RAM_SIZE / 4 - RX_FIFO_EP_WORDS - TX_FIFO_EP_0_WORDS) +/* Number of words for each remaining TX endpoint FIFO */ #define TX_FIFO_EP_WORDS (TX_FIFO_WORDS / (TX_FIFO_NUM - 1)) #endif /* USB */ @@ -450,7 +450,8 @@ static int usb_dc_stm32_init(void) for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) { if (i == 0) { /* first endpoint need only 64 byte for EP_TYPE_CTRL */ - HAL_PCDEx_SetTxFiFo(&usb_dc_stm32_state.pcd, i, 16); + HAL_PCDEx_SetTxFiFo(&usb_dc_stm32_state.pcd, i, + TX_FIFO_EP_0_WORDS); } else { HAL_PCDEx_SetTxFiFo(&usb_dc_stm32_state.pcd, i, TX_FIFO_EP_WORDS); From 0717d4789d40a1e4f1b7a399441d4144afebb597 Mon Sep 17 00:00:00 2001 From: Adam Berlinger Date: Thu, 4 Apr 2024 13:31:49 +0200 Subject: [PATCH 1947/2402] drivers: timer: remove reset release for lptim The LL_APBx_GRPn_ReleaseReset clears reset bit in RCC, however this bit is reset by default. Code that set this bit was removed in previous commit 0856e9915500e2138772a5553ceabc2e6d78b7d0 Keepint the autonomous clocks for STM32U5 family. Signed-off-by: Adam Berlinger --- drivers/timer/stm32_lptim_timer.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/timer/stm32_lptim_timer.c b/drivers/timer/stm32_lptim_timer.c index b18d821f2aa..5dc28a4e8ea 100644 --- a/drivers/timer/stm32_lptim_timer.c +++ b/drivers/timer/stm32_lptim_timer.c @@ -401,12 +401,8 @@ static int sys_clock_driver_init(void) return -EIO; } -#if defined(LL_APB1_GRP1_PERIPH_LPTIM1) - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1); -#elif defined(LL_APB3_GRP1_PERIPH_LPTIM1) +#if defined(LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN) LL_SRDAMR_GRP1_EnableAutonomousClock(LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN); -#elif defined(LL_APB7_GRP1_PERIPH_LPTIM1) - LL_APB7_GRP1_ReleaseReset(LL_APB7_GRP1_PERIPH_LPTIM1); #endif /* Enable LPTIM clock source */ From e3c759e835f142b65f57c015a7302df46a0c2898 Mon Sep 17 00:00:00 2001 From: Adam Berlinger Date: Tue, 2 Apr 2024 18:06:26 +0200 Subject: [PATCH 1948/2402] soc: st: add PM support for STM32H5 Single STOP mode level supported on STM32H5 Signed-off-by: Adam Berlinger --- dts/arm/st/h5/stm32h5.dtsi | 10 ++++ soc/st/stm32/stm32h5x/CMakeLists.txt | 4 ++ soc/st/stm32/stm32h5x/Kconfig | 1 + soc/st/stm32/stm32h5x/power.c | 76 ++++++++++++++++++++++++++++ 4 files changed, 91 insertions(+) create mode 100644 soc/st/stm32/stm32h5x/power.c diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi index 087ca1b5653..a04baf15577 100644 --- a/dts/arm/st/h5/stm32h5.dtsi +++ b/dts/arm/st/h5/stm32h5.dtsi @@ -30,6 +30,7 @@ device_type = "cpu"; compatible = "arm,cortex-m33"; reg = <0>; + cpu-power-states = <&stop>; #address-cells = <1>; #size-cells = <1>; @@ -116,6 +117,15 @@ }; }; + power-states { + stop: state0 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <1>; + min-residency-us = <20>; + }; + }; + rcc: rcc@44020c00 { compatible = "st,stm32u5-rcc"; clocks-controller; diff --git a/soc/st/stm32/stm32h5x/CMakeLists.txt b/soc/st/stm32/stm32h5x/CMakeLists.txt index eebd281cd96..bc9a65c0049 100644 --- a/soc/st/stm32/stm32h5x/CMakeLists.txt +++ b/soc/st/stm32/stm32h5x/CMakeLists.txt @@ -5,6 +5,10 @@ zephyr_sources( soc.c ) +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + zephyr_include_directories(.) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32h5x/Kconfig b/soc/st/stm32/stm32h5x/Kconfig index 9ff02424ebd..6516a056490 100644 --- a/soc/st/stm32/stm32h5x/Kconfig +++ b/soc/st/stm32/stm32h5x/Kconfig @@ -14,3 +14,4 @@ config SOC_SERIES_STM32H5X select CPU_CORTEX_M_HAS_DWT select HAS_STM32CUBE select HAS_SWO + select HAS_PM diff --git a/soc/st/stm32/stm32h5x/power.c b/soc/st/stm32/stm32h5x/power.c new file mode 100644 index 00000000000..0dc1d30819a --- /dev/null +++ b/soc/st/stm32/stm32h5x/power.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2024 STMicroelectronics. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include + +#include +#include +#include + +#include +LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); + +/* Invoke Low Power/System Off specific Tasks */ +void pm_state_set(enum pm_state state, uint8_t substate_id) +{ + if (state != PM_STATE_SUSPEND_TO_IDLE) { + LOG_DBG("Unsupported power state %u", state); + return; + } + + switch (substate_id) { + case 1: /* this corresponds to the STOP mode: */ + /* enter STOP mode */ + LL_PWR_SetPowerMode(LL_PWR_STOP_MODE); + LL_LPM_EnableDeepSleep(); + /* enter SLEEP mode : WFE or WFI */ + k_cpu_idle(); + break; + default: + LOG_DBG("Unsupported power state substate-id %u", + substate_id); + break; + } +} + +/* Handle SOC specific activity after Low Power Mode Exit */ +void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +{ + if (state != PM_STATE_SUSPEND_TO_IDLE) { + LOG_DBG("Unsupported power substate %u", state); + } else { + switch (substate_id) { + case 1: /* STOP */ + LL_LPM_DisableSleepOnExit(); + /* Clear SLEEPDEEP bit */ + LL_LPM_EnableSleep(); + break; + default: + LOG_DBG("Unsupported power substate-id %u", + substate_id); + break; + } + /* need to restore the clock */ + stm32_clock_control_init(NULL); + } + + /* + * System is now in active mode. + * Reenable interrupts which were disabled + * when OS started idling code. + */ + irq_unlock(0); +} + +/* Initialize STM32 Power */ +static int stm32_power_init(void) +{ + return 0; +} + +SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); From 91acd6c1e0733a9a697f6d49039680aedc1835ea Mon Sep 17 00:00:00 2001 From: Adam Berlinger Date: Tue, 2 Apr 2024 18:08:06 +0200 Subject: [PATCH 1949/2402] drivers: timer: add support for LPTIM on STM32H5 Added support for LPTIM1/2 for STM32H503 and LPTIM1 to LPTIM6 for STM32H56x/STM32H57x devices Signed-off-by: Adam Berlinger --- drivers/timer/stm32_lptim_timer.c | 3 +++ dts/arm/st/h5/stm32h5.dtsi | 22 ++++++++++++++++ dts/arm/st/h5/stm32h562.dtsi | 44 +++++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/drivers/timer/stm32_lptim_timer.c b/drivers/timer/stm32_lptim_timer.c index 5dc28a4e8ea..c94be66b80e 100644 --- a/drivers/timer/stm32_lptim_timer.c +++ b/drivers/timer/stm32_lptim_timer.c @@ -478,6 +478,7 @@ static int sys_clock_driver_init(void) LL_LPTIM_SetPrescaler(LPTIM, (__CLZ(__RBIT(lptim_clock_presc)) << LPTIM_CFGR_PRESC_Pos)); #if defined(CONFIG_SOC_SERIES_STM32U5X) || \ + defined(CONFIG_SOC_SERIES_STM32H5X) || \ defined(CONFIG_SOC_SERIES_STM32WBAX) LL_LPTIM_OC_SetPolarity(LPTIM, LL_LPTIM_CHANNEL_CH1, LL_LPTIM_OUTPUT_POLARITY_REGULAR); @@ -491,6 +492,7 @@ static int sys_clock_driver_init(void) LL_LPTIM_TrigSw(LPTIM); #if defined(CONFIG_SOC_SERIES_STM32U5X) || \ + defined(CONFIG_SOC_SERIES_STM32H5X) || \ defined(CONFIG_SOC_SERIES_STM32WBAX) /* Enable the LPTIM before proceeding with configuration */ LL_LPTIM_Enable(LPTIM); @@ -516,6 +518,7 @@ static int sys_clock_driver_init(void) LL_LPTIM_ClearFlag_ARROK(LPTIM); #if !defined(CONFIG_SOC_SERIES_STM32U5X) && \ + !defined(CONFIG_SOC_SERIES_STM32H5X) && \ !defined(CONFIG_SOC_SERIES_STM32WBAX) /* Enable the LPTIM counter */ LL_LPTIM_Enable(LPTIM); diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi index a04baf15577..e154aa8d9de 100644 --- a/dts/arm/st/h5/stm32h5.dtsi +++ b/dts/arm/st/h5/stm32h5.dtsi @@ -206,6 +206,28 @@ }; }; + lptim1: timers@44004400 { + compatible = "st,stm32-lptim"; + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x800>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44004400 0x400>; + interrupts = <64 1>; + interrupt-names = "wakeup"; + status = "disabled"; + }; + + lptim2: timers@40009400 { + compatible = "st,stm32-lptim"; + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x20>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40009400 0x400>; + interrupts = <70 1>; + interrupt-names = "wakeup"; + status = "disabled"; + }; + usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; diff --git a/dts/arm/st/h5/stm32h562.dtsi b/dts/arm/st/h5/stm32h562.dtsi index a88b7b8a063..a7c5ae93ff4 100644 --- a/dts/arm/st/h5/stm32h562.dtsi +++ b/dts/arm/st/h5/stm32h562.dtsi @@ -54,6 +54,50 @@ }; }; + lptim3: timers@44004800 { + compatible = "st,stm32-lptim"; + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44004800 0x400>; + interrupts = <127 1>; + interrupt-names = "wakeup"; + status = "disabled"; + }; + + lptim4: timers@44004C00 { + compatible = "st,stm32-lptim"; + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44004C00 0x400>; + interrupts = <128 1>; + interrupt-names = "wakeup"; + status = "disabled"; + }; + + lptim5: timers@44005000 { + compatible = "st,stm32-lptim"; + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44005000 0x400>; + interrupts = <129 1>; + interrupt-names = "wakeup"; + status = "disabled"; + }; + + lptim6: timers@44005400 { + compatible = "st,stm32-lptim"; + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x8000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44005400 0x400>; + interrupts = <130 1>; + interrupt-names = "wakeup"; + status = "disabled"; + }; + uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; From e8b898f450f46a8e66e3ea46f3ed1500c536e451 Mon Sep 17 00:00:00 2001 From: Adam Berlinger Date: Tue, 2 Apr 2024 18:09:09 +0200 Subject: [PATCH 1950/2402] boards: st: add support for LPTIMER for nucleo_h563zi board LPTIM4 is selected, since it is used only for internal timing and it doesn't support output/input Signed-off-by: Adam Berlinger --- .../nucleo_h563zi/nucleo_h563zi-common.dtsi | 10 +++++++ .../boards/nucleo_h563zi.overlay | 26 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 samples/boards/stm32/power_mgmt/serial_wakeup/boards/nucleo_h563zi.overlay diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi index 35fb42aedfa..3e965035626 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi +++ b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi @@ -190,3 +190,13 @@ zephyr_udc0: &usb { &vbat { status = "okay"; }; + +&clk_lsi { + status = "okay"; +}; + +stm32_lp_tick_source: &lptim4 { + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x2000>, + <&rcc STM32_SRC_LSI LPTIM4_SEL(4)>; + status = "okay"; +}; diff --git a/samples/boards/stm32/power_mgmt/serial_wakeup/boards/nucleo_h563zi.overlay b/samples/boards/stm32/power_mgmt/serial_wakeup/boards/nucleo_h563zi.overlay new file mode 100644 index 00000000000..2a2393cfbc9 --- /dev/null +++ b/samples/boards/stm32/power_mgmt/serial_wakeup/boards/nucleo_h563zi.overlay @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&usart3 { + /* Set domain clock to HSI to allow wakeup from Stop mode */ + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>, + <&rcc STM32_SRC_HSI USART3_SEL(3)>; + + /* Configure device as wakeup source */ + wakeup-source; + + /* Configure sleep pinctrl configuration which will be used when + * device is not configured as wakeup source by the application. + * This use case is only applicable in PM_DEVICE mode. + */ + pinctrl-1 = <&analog_pd8 &analog_pd9>; + pinctrl-names = "default", "sleep"; +}; + +&clk_hsi { + /* Make sure HSI is enabled */ + status = "okay"; +}; From aaa04c6539abfd20073fc103e3e9ee714c8c0c16 Mon Sep 17 00:00:00 2001 From: Maxin John Date: Sun, 31 Mar 2024 20:37:03 +0300 Subject: [PATCH 1951/2402] boards: st: stm32l1_disco: enable eeprom and watchdog stm32l1_disco board from STMicroelectronics has eeprom and watchdog. Enable those peripherals. Tested using: 1. samples/drivers/eeprom 2. samples/drivers/watchdog Signed-off-by: Maxin John --- boards/st/stm32l1_disco/doc/index.rst | 3 +++ boards/st/stm32l1_disco/stm32l1_disco.dts | 10 ++++++++++ boards/st/stm32l1_disco/stm32l1_disco.yaml | 2 ++ 3 files changed, 15 insertions(+) diff --git a/boards/st/stm32l1_disco/doc/index.rst b/boards/st/stm32l1_disco/doc/index.rst index a3b4a30bdfa..4e64e94fa57 100644 --- a/boards/st/stm32l1_disco/doc/index.rst +++ b/boards/st/stm32l1_disco/doc/index.rst @@ -80,6 +80,9 @@ The Zephyr stm32l1_disco board configuration supports the following hardware fea * - FLASH - on-chip - flash memory + * - EEPROM + - on-chip + - eeprom * - WATCHDOG - on-chip - window watchdog diff --git a/boards/st/stm32l1_disco/stm32l1_disco.dts b/boards/st/stm32l1_disco/stm32l1_disco.dts index 4b158feaa12..2dff8c410b5 100644 --- a/boards/st/stm32l1_disco/stm32l1_disco.dts +++ b/boards/st/stm32l1_disco/stm32l1_disco.dts @@ -45,6 +45,8 @@ led0 = &green_led; led1 = &blue_led; sw0 = &user_button; + eeprom-0 = &eeprom; + watchdog0 = &iwdg; }; }; @@ -130,3 +132,11 @@ status = "okay"; }; }; + +&eeprom { + status = "okay"; +}; + +&iwdg { + status = "okay"; +}; diff --git a/boards/st/stm32l1_disco/stm32l1_disco.yaml b/boards/st/stm32l1_disco/stm32l1_disco.yaml index 75fa0045fa4..ac536ecacbb 100644 --- a/boards/st/stm32l1_disco/stm32l1_disco.yaml +++ b/boards/st/stm32l1_disco/stm32l1_disco.yaml @@ -12,4 +12,6 @@ supported: - gpio - i2c - spi + - eeprom + - watchdog vendor: st From f5c2971374b1c0358025f1f6f7616de0f8a73084 Mon Sep 17 00:00:00 2001 From: Lubos Koudelka Date: Wed, 3 Apr 2024 09:47:33 +0200 Subject: [PATCH 1952/2402] boards: st: nucleo_wb55rg: leds aliases Changing led color description and adding led alliases Signed-off-by: Lubos Koudelka --- boards/st/nucleo_wb55rg/nucleo_wb55rg.dts | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts index 08cfaf40eba..4eb19294f0f 100644 --- a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts +++ b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts @@ -34,7 +34,7 @@ gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>; label = "User LED2"; }; - green_led_3: led_2 { + red_led_3: led_2 { gpios = <&gpiob 1 GPIO_ACTIVE_HIGH>; label = "User LED3"; }; @@ -60,8 +60,9 @@ }; aliases { - led0 = &green_led_2; - led1 = &blue_led_1; + led0 = &blue_led_1; + led1 = &green_led_2; + led2 = &red_led_3; sw0 = &user_button_1; sw1 = &user_button_2; sw2 = &user_button_3; From 824e352a772fe1f16ff3cd362588457ef09487ab Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 14:55:55 +0100 Subject: [PATCH 1953/2402] Bluetooth: BAP: Shell: Fix bad err check for PAST sync If pa_sync_past returns 0 then that means we are ready to sync to past, and the BT_BAP_PA_STATE_INFO_REQ state should be set. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/shell/bap_scan_delegator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/bluetooth/audio/shell/bap_scan_delegator.c b/subsys/bluetooth/audio/shell/bap_scan_delegator.c index 6b8e703a899..79676875554 100644 --- a/subsys/bluetooth/audio/shell/bap_scan_delegator.c +++ b/subsys/bluetooth/audio/shell/bap_scan_delegator.c @@ -451,7 +451,7 @@ static int cmd_bap_scan_delegator_sync_pa(const struct shell *sh, size_t argc, shell_info(sh, "Syncing with PAST"); err = pa_sync_past(state->conn, state, state->pa_interval); - if (err != 0) { + if (err == 0) { err = bt_bap_scan_delegator_set_pa_state(src_id, BT_BAP_PA_STATE_INFO_REQ); if (err != 0) { From 6073b630daabec2276a3b59254d1ec02b40acf38 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 14:52:47 +0100 Subject: [PATCH 1954/2402] Bluetooth: Audio: Shell: Increase BAP BA recv state count Increase the supported receive state count to 4, as several on-market device have at least 2 and sometimes more. Signed-off-by: Emil Gydesen --- tests/bluetooth/shell/audio.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/bluetooth/shell/audio.conf b/tests/bluetooth/shell/audio.conf index 040a28db6b4..264d06cec20 100644 --- a/tests/bluetooth/shell/audio.conf +++ b/tests/bluetooth/shell/audio.conf @@ -141,6 +141,7 @@ CONFIG_BT_BAP_SCAN_DELEGATOR=y CONFIG_BT_BAP_BASS_MAX_SUBGROUPS=2 CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE=255 CONFIG_BT_BAP_BROADCAST_ASSISTANT=y +CONFIG_BT_BAP_BROADCAST_ASSISTANT_RECV_STATE_COUNT=4 # IAS CONFIG_BT_IAS=y From 3caa8f403a585c35ed04bdddaa1351640f00654b Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 14:48:53 +0100 Subject: [PATCH 1955/2402] Bluetooth: Audio: Shell: Fix snk_chan_cnt for AC_5 The audio configuration 5 is defined to have 2 sink channels per stream and 1 source channel per stream. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/shell/cap_initiator.c | 2 +- subsys/bluetooth/audio/shell/gmap.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/subsys/bluetooth/audio/shell/cap_initiator.c b/subsys/bluetooth/audio/shell/cap_initiator.c index d6c21003a16..6343e973178 100644 --- a/subsys/bluetooth/audio/shell/cap_initiator.c +++ b/subsys/bluetooth/audio/shell/cap_initiator.c @@ -896,7 +896,7 @@ static int cmd_cap_ac_5(const struct shell *sh, size_t argc, char **argv) .conn_cnt = 1U, .snk_cnt = {1U}, .src_cnt = {1U}, - .snk_chan_cnt = 1U, + .snk_chan_cnt = 2U, .src_chan_cnt = 1U, }; diff --git a/subsys/bluetooth/audio/shell/gmap.c b/subsys/bluetooth/audio/shell/gmap.c index 4096fb9be73..cbd91f69219 100644 --- a/subsys/bluetooth/audio/shell/gmap.c +++ b/subsys/bluetooth/audio/shell/gmap.c @@ -326,7 +326,7 @@ static int cmd_gmap_ac_5(const struct shell *sh, size_t argc, char **argv) .conn_cnt = 1U, .snk_cnt = {1U}, .src_cnt = {1U}, - .snk_chan_cnt = 1U, + .snk_chan_cnt = 2U, .src_chan_cnt = 1U, }; From ab57f2275ac0055a303b0b2a9c89467eecec6ccd Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 14:41:56 +0100 Subject: [PATCH 1956/2402] Bluetooth: BAP: Shell: Fix state lookup with PAST When a PA is synced via PAST, the receive state does not have a PA sync object, and the address and SID must be used. Signed-off-by: Emil Gydesen --- .../audio/shell/bap_scan_delegator.c | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/subsys/bluetooth/audio/shell/bap_scan_delegator.c b/subsys/bluetooth/audio/shell/bap_scan_delegator.c index 79676875554..a2067301c8d 100644 --- a/subsys/bluetooth/audio/shell/bap_scan_delegator.c +++ b/subsys/bluetooth/audio/shell/bap_scan_delegator.c @@ -77,6 +77,21 @@ static struct sync_state *sync_state_get_by_pa(struct bt_le_per_adv_sync *sync) return NULL; } +static struct sync_state * +sync_state_get_by_sync_info(const struct bt_le_per_adv_sync_synced_info *info) +{ + for (size_t i = 0U; i < ARRAY_SIZE(sync_states); i++) { + if (sync_states[i].recv_state != NULL && + bt_addr_le_eq(info->addr, &sync_states[i].recv_state->addr) && + info->sid == sync_states[i].recv_state->adv_sid) { + + return &sync_states[i]; + } + } + + return NULL; +} + static struct sync_state *sync_state_new(void) { for (size_t i = 0U; i < ARRAY_SIZE(sync_states); i++) { @@ -337,7 +352,13 @@ static void pa_synced_cb(struct bt_le_per_adv_sync *sync, shell_info(ctx_shell, "PA %p synced", sync); - state = sync_state_get_by_pa(sync); + if (info->conn == NULL) { + state = sync_state_get_by_pa(sync); + } else { + /* In case of PAST we need to use the addr instead */ + state = sync_state_get_by_sync_info(info); + } + if (state == NULL) { shell_info(ctx_shell, "Could not get sync state from PA sync %p", From 0f3b0d29dac1058d4ed762eebb2de698a23782ad Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 14:15:38 +0100 Subject: [PATCH 1957/2402] Bluetooth: BAP: Shell: Fix documentation for broadcast_code The documentation for the command bap_broadcast_assistant broadcast_code was incorrect and has been fixed. Additionally, and example of the command has been added in the shell documentation. Signed-off-by: Emil Gydesen --- .../bluetooth/api/shell/bap_broadcast_assistant.rst | 12 +++++++++++- .../bluetooth/audio/shell/bap_broadcast_assistant.c | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/doc/connectivity/bluetooth/api/shell/bap_broadcast_assistant.rst b/doc/connectivity/bluetooth/api/shell/bap_broadcast_assistant.rst index 169ee925874..01d2a9f23b6 100644 --- a/doc/connectivity/bluetooth/api/shell/bap_broadcast_assistant.rst +++ b/doc/connectivity/bluetooth/api/shell/bap_broadcast_assistant.rst @@ -41,7 +41,7 @@ subscribe to all notifications. [bis_index [bis_index [bix_index [...]]]]> mod_src : Set sync [] [] [] - broadcast_code : Send a space separated broadcast code of up to 16 bytes + broadcast_code : Send a string-based broadcast code of up to 16 bytes rem_src : Remove a source read_state : Remove a source @@ -115,3 +115,13 @@ Modifying a receive state: BASS recv state: src_id 0, addr 1E:4D:0A:AA:6E:49 (random), sid 0, sync_state 2, encrypt_state 0 [0]: BIS sync 0x0001, metadata_len 4 Metadata length 2, type 2, data: 0100 + +Supplying a broadcast code: +--------------------------- + +.. code-block:: console + + uart:~$ bap_broadcast_assistant broadcast_code 0 secretCode + Sending broadcast code: + 00000000: 73 65 63 72 65 74 43 6f 64 65 00 00 00 00 00 00 |secretCo de....| + uart:~$ BASS broadcast code successful diff --git a/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c b/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c index fad8b150e0a..f5fbde37046 100644 --- a/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c +++ b/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c @@ -1042,7 +1042,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE( "[] []", cmd_bap_broadcast_assistant_mod_src, 3, 2), SHELL_CMD_ARG(broadcast_code, NULL, - "Send a space separated broadcast code of up to 16 bytes " + "Send a string-based broadcast code of up to 16 bytes " " ", cmd_bap_broadcast_assistant_broadcast_code, 3, 0), SHELL_CMD_ARG(rem_src, NULL, "Remove a source ", From a3c0f2b1e9ca464bdc578e9e5570c31763b41131 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 14:08:07 +0100 Subject: [PATCH 1958/2402] Bluetooth: BAP: Shell: Add support for "unknown" PA interval in mod_src The bap_broadcast_assistant mod_src command can now take "unknown" as a value to supply BT_BAP_PA_INTERVAL_UNKNOWN to the scan delegator. Signed-off-by: Emil Gydesen --- .../api/shell/bap_broadcast_assistant.rst | 2 +- .../audio/shell/bap_broadcast_assistant.c | 31 ++++++++++--------- 2 files changed, 18 insertions(+), 15 deletions(-) diff --git a/doc/connectivity/bluetooth/api/shell/bap_broadcast_assistant.rst b/doc/connectivity/bluetooth/api/shell/bap_broadcast_assistant.rst index 01d2a9f23b6..5ebd7b34327 100644 --- a/doc/connectivity/bluetooth/api/shell/bap_broadcast_assistant.rst +++ b/doc/connectivity/bluetooth/api/shell/bap_broadcast_assistant.rst @@ -39,7 +39,7 @@ subscribe to all notifications. [] [] add_pa_sync : Add a PA sync as a source [bis_index [bis_index [bix_index [...]]]]> - mod_src : Set sync [] [] + mod_src : Set sync [ | "unknown"] [] [] broadcast_code : Send a string-based broadcast code of up to 16 bytes diff --git a/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c b/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c index f5fbde37046..aa0be699a7e 100644 --- a/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c +++ b/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c @@ -694,24 +694,27 @@ static int cmd_bap_broadcast_assistant_mod_src(const struct shell *sh, } if (argc > 3) { - unsigned long pa_interval; + if (strcmp(argv[3], "unknown") == 0) { + param.pa_interval = BT_BAP_PA_INTERVAL_UNKNOWN; + } else { + unsigned long pa_interval; - pa_interval = shell_strtoul(argv[3], 0, &result); - if (result) { - shell_error(sh, "Could not parse pa_interval: %d", result); + pa_interval = shell_strtoul(argv[3], 0, &result); + if (result) { + shell_error(sh, "Could not parse pa_interval: %d", result); - return -ENOEXEC; - } + return -ENOEXEC; + } - if (!IN_RANGE(pa_interval, - BT_GAP_PER_ADV_MIN_INTERVAL, - BT_GAP_PER_ADV_MAX_INTERVAL)) { - shell_error(sh, "Invalid pa_interval: %lu", pa_interval); + if (!IN_RANGE(pa_interval, BT_GAP_PER_ADV_MIN_INTERVAL, + BT_GAP_PER_ADV_MAX_INTERVAL)) { + shell_error(sh, "Invalid pa_interval: %lu", pa_interval); - return -ENOEXEC; - } + return -ENOEXEC; + } - param.pa_interval = pa_interval; + param.pa_interval = pa_interval; + } } else { param.pa_interval = BT_BAP_PA_INTERVAL_UNKNOWN; } @@ -1038,7 +1041,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE( "[bis_index [bis_index [bix_index [...]]]]>", cmd_bap_broadcast_assistant_add_pa_sync, 3, BT_ISO_MAX_GROUP_ISO_COUNT), SHELL_CMD_ARG(mod_src, NULL, - "Set sync [] " + "Set sync [ | \"unknown\"] " "[] []", cmd_bap_broadcast_assistant_mod_src, 3, 2), SHELL_CMD_ARG(broadcast_code, NULL, From 5e840c1f1e7a3de0c6ba5cd4dbbae93ba1ef2f8d Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 13:59:42 +0100 Subject: [PATCH 1959/2402] Bluetooth: BAP: Shell: add additional printing in recv_state_cb Add printing of the broadcast ID and whether an existing PA sync was found in the bap_broadcast_assistant_recv_state_cb function. Signed-off-by: Emil Gydesen --- .../audio/shell/bap_broadcast_assistant.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c b/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c index aa0be699a7e..fe28cdbb853 100644 --- a/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c +++ b/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c @@ -123,11 +123,12 @@ static void bap_broadcast_assistant_recv_state_cb( bad_code, sizeof(bad_code)); is_bad_code = state->encrypt_state == BT_BAP_BIG_ENC_STATE_BAD_CODE; - shell_print( - ctx_shell, - "BASS recv state: src_id %u, addr %s, sid %u, sync_state %u, encrypt_state %u%s%s", - state->src_id, le_addr, state->adv_sid, state->pa_sync_state, state->encrypt_state, - is_bad_code ? ", bad code" : "", is_bad_code ? bad_code : ""); + shell_print(ctx_shell, + "BASS recv state: src_id %u, addr %s, sid %u, broadcast_id 0x%06X, sync_state " + "%u, encrypt_state %u%s%s", + state->src_id, le_addr, state->adv_sid, state->broadcast_id, + state->pa_sync_state, state->encrypt_state, is_bad_code ? ", bad code" : "", + is_bad_code ? bad_code : ""); for (int i = 0; i < state->num_subgroups; i++) { const struct bt_bap_bass_subgroup *subgroup = &state->subgroups[i]; @@ -147,10 +148,11 @@ static void bap_broadcast_assistant_recv_state_cb( struct bt_le_ext_adv *ext_adv = NULL; /* Lookup matching PA sync */ - for (int i = 0; i < ARRAY_SIZE(per_adv_syncs); i++) { - if (per_adv_syncs[i] && + for (size_t i = 0U; i < ARRAY_SIZE(per_adv_syncs); i++) { + if (per_adv_syncs[i] != NULL && bt_addr_le_eq(&per_adv_syncs[i]->addr, &state->addr)) { per_adv_sync = per_adv_syncs[i]; + shell_print(ctx_shell, "Found matching PA sync [%zu]", i); break; } } From be5adb4323a4a2a0461de24904a1a65909011252 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 11:06:43 +0100 Subject: [PATCH 1960/2402] Bluetooth: BAP: Unicast Client: Replace some LOG_ERR/WRN with DBG When returning an error code directly to an application in the API, it should not log as a warning or error. The lack of PAC records is also reported directly to the application, and is not an error (in fact it is valid not to have e.g. sink or source pacs). Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/bap_unicast_client.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/subsys/bluetooth/audio/bap_unicast_client.c b/subsys/bluetooth/audio/bap_unicast_client.c index 9fcf8203d6f..b6c579d423b 100644 --- a/subsys/bluetooth/audio/bap_unicast_client.c +++ b/subsys/bluetooth/audio/bap_unicast_client.c @@ -2529,24 +2529,24 @@ static int stream_param_check(const struct bt_bap_unicast_group_stream_param *pa { CHECKIF(param->stream == NULL) { - LOG_ERR("param->stream is NULL"); + LOG_DBG("param->stream is NULL"); return -EINVAL; } CHECKIF(param->qos == NULL) { - LOG_ERR("param->qos is NULL"); + LOG_DBG("param->qos is NULL"); return -EINVAL; } if (param->stream != NULL && param->stream->group != NULL) { - LOG_WRN("stream %p already part of group %p", param->stream, param->stream->group); + LOG_DBG("stream %p already part of group %p", param->stream, param->stream->group); return -EALREADY; } CHECKIF(bt_audio_verify_qos(param->qos) != BT_BAP_ASCS_REASON_NONE) { - LOG_ERR("Invalid QoS"); + LOG_DBG("Invalid QoS"); return -EINVAL; } @@ -3998,7 +3998,7 @@ static uint8_t unicast_client_pac_discover_cb(struct bt_conn *conn, int err; if (attr == NULL) { - LOG_ERR("Unable to find %s PAC", bt_audio_dir_str(client->dir)); + LOG_DBG("Unable to find %s PAC", bt_audio_dir_str(client->dir)); discover_cb(conn, BT_ATT_ERR_ATTRIBUTE_NOT_FOUND); From 1d5acb754727926bbe9fe701924d99da3a6eb102 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 11:10:26 +0100 Subject: [PATCH 1961/2402] Bluetooth: Audio: Remove !found dbg log in codec.c It is a common occurance that a specific type is not found in the codec configuration, and the main way of knowing that is by calling the function. The debug log does not help debug anything (as it does also return a specific error code), but rather just clutters up the log if enabled. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/codec.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/subsys/bluetooth/audio/codec.c b/subsys/bluetooth/audio/codec.c index 2562ab0c1bc..86936d58a8e 100644 --- a/subsys/bluetooth/audio/codec.c +++ b/subsys/bluetooth/audio/codec.c @@ -309,7 +309,6 @@ int bt_audio_codec_cfg_get_val(const struct bt_audio_codec_cfg *codec_cfg, } if (!param.found) { - LOG_DBG("Could not find the type %u", type); return -ENODATA; } @@ -621,7 +620,6 @@ static int codec_meta_get_val(const uint8_t meta[], size_t meta_len, } if (!param.found) { - LOG_DBG("Could not find the type %u", type); return -ENODATA; } @@ -1823,7 +1821,6 @@ int bt_audio_codec_cap_get_val(const struct bt_audio_codec_cap *codec_cap, } if (!param.found) { - LOG_DBG("Could not find the type %u", type); return -ENODATA; } From d229b89a2bc3f5e4a69229dffe89b04eec237b76 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 11:58:46 +0100 Subject: [PATCH 1962/2402] Bluetooth: BAP: Shell: Add tracking of empty SDUs There are devices that will send empty SDUs instead of empty PDUs, and while that should be harmless, it is nice to know what is going on, and we may want to deal with empty SDUs and empty PDUs differently. This also modifies the state for TS and PSN to only be applied for valid ISO packets. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/shell/audio.h | 1 + subsys/bluetooth/audio/shell/bap.c | 32 ++++++++++++++++++---------- 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/subsys/bluetooth/audio/shell/audio.h b/subsys/bluetooth/audio/shell/audio.h index 3f5184aeca8..eb32b235871 100644 --- a/subsys/bluetooth/audio/shell/audio.h +++ b/subsys/bluetooth/audio/shell/audio.h @@ -85,6 +85,7 @@ struct shell_stream { #endif /* CONFIG_BT_AUDIO_TX */ #if defined(CONFIG_BT_AUDIO_RX) struct bt_iso_recv_info last_info; + size_t empty_sdu_pkts; size_t lost_pkts; size_t err_pkts; size_t dup_psn; diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index 6bf781ed65e..db5d76888ff 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -2338,12 +2338,20 @@ static void audio_recv(struct bt_bap_stream *stream, sh_stream->rx_cnt++; - if (info->ts == sh_stream->last_info.ts) { - sh_stream->dup_ts++; - } + if ((info->flags & BT_ISO_FLAGS_VALID) != 0) { + /* For valid ISO packets we check if they are invalid in other ways */ + + if (info->ts == sh_stream->last_info.ts) { + sh_stream->dup_ts++; + } - if (info->seq_num == sh_stream->last_info.seq_num) { - sh_stream->dup_psn++; + if (info->seq_num == sh_stream->last_info.seq_num) { + sh_stream->dup_psn++; + } + + if (buf->len == 0U) { + sh_stream->empty_sdu_pkts++; + } } if (info->flags & BT_ISO_FLAGS_ERROR) { @@ -2355,12 +2363,13 @@ static void audio_recv(struct bt_bap_stream *stream, } if ((sh_stream->rx_cnt % recv_stats_interval) == 0) { - shell_print(ctx_shell, - "[%zu]: Incoming audio on stream %p len %u ts %u seq_num %u flags %u " - "(dup ts %zu; dup psn %zu, err_pkts %zu, lost_pkts %zu)", - sh_stream->rx_cnt, stream, buf->len, info->ts, info->seq_num, - info->flags, sh_stream->dup_ts, sh_stream->dup_psn, sh_stream->err_pkts, - sh_stream->lost_pkts); + shell_print( + ctx_shell, + "[%zu]: Incoming audio on stream %p len %u ts %u seq_num %u flags %u " + "(dup ts %zu; dup psn %zu, err_pkts %zu, lost_pkts %zu, empty SDUs %zu)", + sh_stream->rx_cnt, stream, buf->len, info->ts, info->seq_num, info->flags, + sh_stream->dup_ts, sh_stream->dup_psn, sh_stream->err_pkts, + sh_stream->lost_pkts, sh_stream->empty_sdu_pkts); } (void)memcpy(&sh_stream->last_info, info, sizeof(sh_stream->last_info)); @@ -2421,6 +2430,7 @@ static void stream_started_cb(struct bt_bap_stream *bap_stream) printk("Stream %p started\n", bap_stream); #if defined(CONFIG_BT_AUDIO_RX) + sh_stream->empty_sdu_pkts = 0U; sh_stream->lost_pkts = 0U; sh_stream->err_pkts = 0U; sh_stream->dup_psn = 0U; From 8acada0608ee03ea803b1c16b568a17af5df3e1c Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 13:55:38 +0100 Subject: [PATCH 1963/2402] Bluetooth: Audio: Shell: clear static buffers for ad data The buffers for the PBP advertising data as well as the buffers for the BASE periodic advertising data were not cleared, so calling the functions multiple times would simply append the data rather than just setting the new data. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/shell/bap.c | 2 ++ subsys/bluetooth/audio/shell/cap_initiator.c | 2 ++ subsys/bluetooth/audio/shell/pbp.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index db5d76888ff..49cca9941c5 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -3740,6 +3740,8 @@ ssize_t audio_pa_data_add(struct bt_data *data_array, NET_BUF_SIMPLE_DEFINE_STATIC(base_buf, UINT8_MAX); int err; + net_buf_simple_reset(&base_buf); + err = bt_bap_broadcast_source_get_base(default_source.bap_source, &base_buf); if (err != 0) { printk("Unable to get BASE: %d\n", err); diff --git a/subsys/bluetooth/audio/shell/cap_initiator.c b/subsys/bluetooth/audio/shell/cap_initiator.c index 6343e973178..813bff1a041 100644 --- a/subsys/bluetooth/audio/shell/cap_initiator.c +++ b/subsys/bluetooth/audio/shell/cap_initiator.c @@ -1459,6 +1459,8 @@ ssize_t cap_initiator_pa_data_add(struct bt_data *data_array, const size_t data_ NET_BUF_SIMPLE_DEFINE_STATIC(base_buf, UINT8_MAX); int err; + net_buf_simple_reset(&base_buf); + err = bt_cap_initiator_broadcast_get_base(default_source.cap_source, &base_buf); if (err != 0) { printk("Unable to get BASE: %d\n", err); diff --git a/subsys/bluetooth/audio/shell/pbp.c b/subsys/bluetooth/audio/shell/pbp.c index 9519fd19274..1eb3e630660 100644 --- a/subsys/bluetooth/audio/shell/pbp.c +++ b/subsys/bluetooth/audio/shell/pbp.c @@ -48,6 +48,8 @@ size_t pbp_ad_data_add(struct bt_data data[], size_t data_size) { int err; + net_buf_simple_reset(&pbp_ad_buf); + err = bt_pbp_get_announcement(pba_metadata, ARRAY_SIZE(pba_metadata), pbp_features, From 8714f5318890403edfe9f24d477bc5a7f976e3cc Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Tue, 26 Mar 2024 14:57:31 -0500 Subject: [PATCH 1964/2402] drivers: sensor: adi: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- MAINTAINERS.yml | 3 +-- drivers/sensor/CMakeLists.txt | 11 ++++------- drivers/sensor/Kconfig | 11 ++++------- drivers/sensor/adi/CMakeLists.txt | 12 ++++++++++++ drivers/sensor/adi/Kconfig | 12 ++++++++++++ drivers/sensor/{ => adi}/adltc2990/CMakeLists.txt | 0 drivers/sensor/{ => adi}/adltc2990/Kconfig | 0 drivers/sensor/{ => adi}/adltc2990/adltc2990.c | 0 drivers/sensor/{ => adi}/adltc2990/adltc2990.h | 0 drivers/sensor/{ => adi}/adltc2990/adltc2990_emul.c | 0 drivers/sensor/{ => adi}/adltc2990/adltc2990_emul.h | 0 drivers/sensor/{ => adi}/adltc2990/adltc2990_reg.h | 0 drivers/sensor/{ => adi}/adt7310/CMakeLists.txt | 0 drivers/sensor/{ => adi}/adt7310/Kconfig | 0 drivers/sensor/{ => adi}/adt7310/adt7310.c | 0 drivers/sensor/{ => adi}/adt7310/adt7310.h | 0 drivers/sensor/{ => adi}/adt7310/adt7310_trigger.c | 0 drivers/sensor/{ => adi}/adt7420/CMakeLists.txt | 0 drivers/sensor/{ => adi}/adt7420/Kconfig | 0 drivers/sensor/{ => adi}/adt7420/adt7420.c | 0 drivers/sensor/{ => adi}/adt7420/adt7420.h | 0 drivers/sensor/{ => adi}/adt7420/adt7420_trigger.c | 0 drivers/sensor/{ => adi}/adxl345/CMakeLists.txt | 0 drivers/sensor/{ => adi}/adxl345/Kconfig | 0 drivers/sensor/{ => adi}/adxl345/adxl345.c | 0 drivers/sensor/{ => adi}/adxl345/adxl345.h | 0 drivers/sensor/{ => adi}/adxl362/CMakeLists.txt | 0 drivers/sensor/{ => adi}/adxl362/Kconfig | 0 drivers/sensor/{ => adi}/adxl362/adxl362.c | 0 drivers/sensor/{ => adi}/adxl362/adxl362.h | 0 drivers/sensor/{ => adi}/adxl362/adxl362_trigger.c | 0 drivers/sensor/{ => adi}/adxl367/CMakeLists.txt | 0 drivers/sensor/{ => adi}/adxl367/Kconfig | 0 drivers/sensor/{ => adi}/adxl367/adxl367.c | 0 drivers/sensor/{ => adi}/adxl367/adxl367.h | 0 drivers/sensor/{ => adi}/adxl367/adxl367_i2c.c | 0 drivers/sensor/{ => adi}/adxl367/adxl367_spi.c | 0 drivers/sensor/{ => adi}/adxl367/adxl367_trigger.c | 0 drivers/sensor/{ => adi}/adxl372/CMakeLists.txt | 0 drivers/sensor/{ => adi}/adxl372/Kconfig | 0 drivers/sensor/{ => adi}/adxl372/adxl372.c | 0 drivers/sensor/{ => adi}/adxl372/adxl372.h | 0 drivers/sensor/{ => adi}/adxl372/adxl372_i2c.c | 0 drivers/sensor/{ => adi}/adxl372/adxl372_spi.c | 0 drivers/sensor/{ => adi}/adxl372/adxl372_trigger.c | 0 45 files changed, 33 insertions(+), 16 deletions(-) create mode 100644 drivers/sensor/adi/CMakeLists.txt create mode 100644 drivers/sensor/adi/Kconfig rename drivers/sensor/{ => adi}/adltc2990/CMakeLists.txt (100%) rename drivers/sensor/{ => adi}/adltc2990/Kconfig (100%) rename drivers/sensor/{ => adi}/adltc2990/adltc2990.c (100%) rename drivers/sensor/{ => adi}/adltc2990/adltc2990.h (100%) rename drivers/sensor/{ => adi}/adltc2990/adltc2990_emul.c (100%) rename drivers/sensor/{ => adi}/adltc2990/adltc2990_emul.h (100%) rename drivers/sensor/{ => adi}/adltc2990/adltc2990_reg.h (100%) rename drivers/sensor/{ => adi}/adt7310/CMakeLists.txt (100%) rename drivers/sensor/{ => adi}/adt7310/Kconfig (100%) rename drivers/sensor/{ => adi}/adt7310/adt7310.c (100%) rename drivers/sensor/{ => adi}/adt7310/adt7310.h (100%) rename drivers/sensor/{ => adi}/adt7310/adt7310_trigger.c (100%) rename drivers/sensor/{ => adi}/adt7420/CMakeLists.txt (100%) rename drivers/sensor/{ => adi}/adt7420/Kconfig (100%) rename drivers/sensor/{ => adi}/adt7420/adt7420.c (100%) rename drivers/sensor/{ => adi}/adt7420/adt7420.h (100%) rename drivers/sensor/{ => adi}/adt7420/adt7420_trigger.c (100%) rename drivers/sensor/{ => adi}/adxl345/CMakeLists.txt (100%) rename drivers/sensor/{ => adi}/adxl345/Kconfig (100%) rename drivers/sensor/{ => adi}/adxl345/adxl345.c (100%) rename drivers/sensor/{ => adi}/adxl345/adxl345.h (100%) rename drivers/sensor/{ => adi}/adxl362/CMakeLists.txt (100%) rename drivers/sensor/{ => adi}/adxl362/Kconfig (100%) rename drivers/sensor/{ => adi}/adxl362/adxl362.c (100%) rename drivers/sensor/{ => adi}/adxl362/adxl362.h (100%) rename drivers/sensor/{ => adi}/adxl362/adxl362_trigger.c (100%) rename drivers/sensor/{ => adi}/adxl367/CMakeLists.txt (100%) rename drivers/sensor/{ => adi}/adxl367/Kconfig (100%) rename drivers/sensor/{ => adi}/adxl367/adxl367.c (100%) rename drivers/sensor/{ => adi}/adxl367/adxl367.h (100%) rename drivers/sensor/{ => adi}/adxl367/adxl367_i2c.c (100%) rename drivers/sensor/{ => adi}/adxl367/adxl367_spi.c (100%) rename drivers/sensor/{ => adi}/adxl367/adxl367_trigger.c (100%) rename drivers/sensor/{ => adi}/adxl372/CMakeLists.txt (100%) rename drivers/sensor/{ => adi}/adxl372/Kconfig (100%) rename drivers/sensor/{ => adi}/adxl372/adxl372.c (100%) rename drivers/sensor/{ => adi}/adxl372/adxl372.h (100%) rename drivers/sensor/{ => adi}/adxl372/adxl372_i2c.c (100%) rename drivers/sensor/{ => adi}/adxl372/adxl372_spi.c (100%) rename drivers/sensor/{ => adi}/adxl372/adxl372_trigger.c (100%) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 0113b786817..1378b5ec23b 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3087,8 +3087,7 @@ ADI Platforms: - drivers/ethernet/eth_adin* - drivers/mdio/mdio_adin* - drivers/regulator/regulator_adp5360* - - drivers/sensor/adt*/ - - drivers/sensor/adxl*/ + - drivers/sensor/adi/ - dts/bindings/*/adi,* - dts/bindings/*/lltc,* - dts/bindings/*/maxim,* diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 7f04c3ce8cf..7a059531f60 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -1,14 +1,11 @@ # SPDX-License-Identifier: Apache-2.0 +# zephyr-keep-sorted-start +add_subdirectory(adi) +# zephyr-keep-sorted-stop + add_subdirectory_ifdef(CONFIG_A01NYUB a01nyub) add_subdirectory_ifdef(CONFIG_ADC_CMP_NPCX nuvoton_adc_cmp_npcx) -add_subdirectory_ifdef(CONFIG_ADLTC2990 adltc2990) -add_subdirectory_ifdef(CONFIG_ADT7310 adt7310) -add_subdirectory_ifdef(CONFIG_ADT7420 adt7420) -add_subdirectory_ifdef(CONFIG_ADXL345 adxl345) -add_subdirectory_ifdef(CONFIG_ADXL362 adxl362) -add_subdirectory_ifdef(CONFIG_ADXL367 adxl367) -add_subdirectory_ifdef(CONFIG_ADXL372 adxl372) add_subdirectory_ifdef(CONFIG_AGS10 ags10) add_subdirectory_ifdef(CONFIG_AK8975 ak8975) add_subdirectory_ifdef(CONFIG_AKM09918C akm09918c) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 708cc6fed24..399e4730d69 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -81,14 +81,11 @@ config SENSOR_INFO comment "Device Drivers" +# zephyr-keep-sorted-start +source "drivers/sensor/adi/Kconfig" +# zephyr-keep-sorted-stop + source "drivers/sensor/a01nyub/Kconfig" -source "drivers/sensor/adltc2990/Kconfig" -source "drivers/sensor/adt7310/Kconfig" -source "drivers/sensor/adt7420/Kconfig" -source "drivers/sensor/adxl345/Kconfig" -source "drivers/sensor/adxl362/Kconfig" -source "drivers/sensor/adxl367/Kconfig" -source "drivers/sensor/adxl372/Kconfig" source "drivers/sensor/ags10/Kconfig" source "drivers/sensor/ak8975/Kconfig" source "drivers/sensor/akm09918c/Kconfig" diff --git a/drivers/sensor/adi/CMakeLists.txt b/drivers/sensor/adi/CMakeLists.txt new file mode 100644 index 00000000000..cf2e79c2db6 --- /dev/null +++ b/drivers/sensor/adi/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_ADLTC2990 adltc2990) +add_subdirectory_ifdef(CONFIG_ADT7310 adt7310) +add_subdirectory_ifdef(CONFIG_ADT7420 adt7420) +add_subdirectory_ifdef(CONFIG_ADXL345 adxl345) +add_subdirectory_ifdef(CONFIG_ADXL362 adxl362) +add_subdirectory_ifdef(CONFIG_ADXL367 adxl367) +add_subdirectory_ifdef(CONFIG_ADXL372 adxl372) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/adi/Kconfig b/drivers/sensor/adi/Kconfig new file mode 100644 index 00000000000..76305d1fd27 --- /dev/null +++ b/drivers/sensor/adi/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/adi/adltc2990/Kconfig" +source "drivers/sensor/adi/adt7310/Kconfig" +source "drivers/sensor/adi/adt7420/Kconfig" +source "drivers/sensor/adi/adxl345/Kconfig" +source "drivers/sensor/adi/adxl362/Kconfig" +source "drivers/sensor/adi/adxl367/Kconfig" +source "drivers/sensor/adi/adxl372/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/adltc2990/CMakeLists.txt b/drivers/sensor/adi/adltc2990/CMakeLists.txt similarity index 100% rename from drivers/sensor/adltc2990/CMakeLists.txt rename to drivers/sensor/adi/adltc2990/CMakeLists.txt diff --git a/drivers/sensor/adltc2990/Kconfig b/drivers/sensor/adi/adltc2990/Kconfig similarity index 100% rename from drivers/sensor/adltc2990/Kconfig rename to drivers/sensor/adi/adltc2990/Kconfig diff --git a/drivers/sensor/adltc2990/adltc2990.c b/drivers/sensor/adi/adltc2990/adltc2990.c similarity index 100% rename from drivers/sensor/adltc2990/adltc2990.c rename to drivers/sensor/adi/adltc2990/adltc2990.c diff --git a/drivers/sensor/adltc2990/adltc2990.h b/drivers/sensor/adi/adltc2990/adltc2990.h similarity index 100% rename from drivers/sensor/adltc2990/adltc2990.h rename to drivers/sensor/adi/adltc2990/adltc2990.h diff --git a/drivers/sensor/adltc2990/adltc2990_emul.c b/drivers/sensor/adi/adltc2990/adltc2990_emul.c similarity index 100% rename from drivers/sensor/adltc2990/adltc2990_emul.c rename to drivers/sensor/adi/adltc2990/adltc2990_emul.c diff --git a/drivers/sensor/adltc2990/adltc2990_emul.h b/drivers/sensor/adi/adltc2990/adltc2990_emul.h similarity index 100% rename from drivers/sensor/adltc2990/adltc2990_emul.h rename to drivers/sensor/adi/adltc2990/adltc2990_emul.h diff --git a/drivers/sensor/adltc2990/adltc2990_reg.h b/drivers/sensor/adi/adltc2990/adltc2990_reg.h similarity index 100% rename from drivers/sensor/adltc2990/adltc2990_reg.h rename to drivers/sensor/adi/adltc2990/adltc2990_reg.h diff --git a/drivers/sensor/adt7310/CMakeLists.txt b/drivers/sensor/adi/adt7310/CMakeLists.txt similarity index 100% rename from drivers/sensor/adt7310/CMakeLists.txt rename to drivers/sensor/adi/adt7310/CMakeLists.txt diff --git a/drivers/sensor/adt7310/Kconfig b/drivers/sensor/adi/adt7310/Kconfig similarity index 100% rename from drivers/sensor/adt7310/Kconfig rename to drivers/sensor/adi/adt7310/Kconfig diff --git a/drivers/sensor/adt7310/adt7310.c b/drivers/sensor/adi/adt7310/adt7310.c similarity index 100% rename from drivers/sensor/adt7310/adt7310.c rename to drivers/sensor/adi/adt7310/adt7310.c diff --git a/drivers/sensor/adt7310/adt7310.h b/drivers/sensor/adi/adt7310/adt7310.h similarity index 100% rename from drivers/sensor/adt7310/adt7310.h rename to drivers/sensor/adi/adt7310/adt7310.h diff --git a/drivers/sensor/adt7310/adt7310_trigger.c b/drivers/sensor/adi/adt7310/adt7310_trigger.c similarity index 100% rename from drivers/sensor/adt7310/adt7310_trigger.c rename to drivers/sensor/adi/adt7310/adt7310_trigger.c diff --git a/drivers/sensor/adt7420/CMakeLists.txt b/drivers/sensor/adi/adt7420/CMakeLists.txt similarity index 100% rename from drivers/sensor/adt7420/CMakeLists.txt rename to drivers/sensor/adi/adt7420/CMakeLists.txt diff --git a/drivers/sensor/adt7420/Kconfig b/drivers/sensor/adi/adt7420/Kconfig similarity index 100% rename from drivers/sensor/adt7420/Kconfig rename to drivers/sensor/adi/adt7420/Kconfig diff --git a/drivers/sensor/adt7420/adt7420.c b/drivers/sensor/adi/adt7420/adt7420.c similarity index 100% rename from drivers/sensor/adt7420/adt7420.c rename to drivers/sensor/adi/adt7420/adt7420.c diff --git a/drivers/sensor/adt7420/adt7420.h b/drivers/sensor/adi/adt7420/adt7420.h similarity index 100% rename from drivers/sensor/adt7420/adt7420.h rename to drivers/sensor/adi/adt7420/adt7420.h diff --git a/drivers/sensor/adt7420/adt7420_trigger.c b/drivers/sensor/adi/adt7420/adt7420_trigger.c similarity index 100% rename from drivers/sensor/adt7420/adt7420_trigger.c rename to drivers/sensor/adi/adt7420/adt7420_trigger.c diff --git a/drivers/sensor/adxl345/CMakeLists.txt b/drivers/sensor/adi/adxl345/CMakeLists.txt similarity index 100% rename from drivers/sensor/adxl345/CMakeLists.txt rename to drivers/sensor/adi/adxl345/CMakeLists.txt diff --git a/drivers/sensor/adxl345/Kconfig b/drivers/sensor/adi/adxl345/Kconfig similarity index 100% rename from drivers/sensor/adxl345/Kconfig rename to drivers/sensor/adi/adxl345/Kconfig diff --git a/drivers/sensor/adxl345/adxl345.c b/drivers/sensor/adi/adxl345/adxl345.c similarity index 100% rename from drivers/sensor/adxl345/adxl345.c rename to drivers/sensor/adi/adxl345/adxl345.c diff --git a/drivers/sensor/adxl345/adxl345.h b/drivers/sensor/adi/adxl345/adxl345.h similarity index 100% rename from drivers/sensor/adxl345/adxl345.h rename to drivers/sensor/adi/adxl345/adxl345.h diff --git a/drivers/sensor/adxl362/CMakeLists.txt b/drivers/sensor/adi/adxl362/CMakeLists.txt similarity index 100% rename from drivers/sensor/adxl362/CMakeLists.txt rename to drivers/sensor/adi/adxl362/CMakeLists.txt diff --git a/drivers/sensor/adxl362/Kconfig b/drivers/sensor/adi/adxl362/Kconfig similarity index 100% rename from drivers/sensor/adxl362/Kconfig rename to drivers/sensor/adi/adxl362/Kconfig diff --git a/drivers/sensor/adxl362/adxl362.c b/drivers/sensor/adi/adxl362/adxl362.c similarity index 100% rename from drivers/sensor/adxl362/adxl362.c rename to drivers/sensor/adi/adxl362/adxl362.c diff --git a/drivers/sensor/adxl362/adxl362.h b/drivers/sensor/adi/adxl362/adxl362.h similarity index 100% rename from drivers/sensor/adxl362/adxl362.h rename to drivers/sensor/adi/adxl362/adxl362.h diff --git a/drivers/sensor/adxl362/adxl362_trigger.c b/drivers/sensor/adi/adxl362/adxl362_trigger.c similarity index 100% rename from drivers/sensor/adxl362/adxl362_trigger.c rename to drivers/sensor/adi/adxl362/adxl362_trigger.c diff --git a/drivers/sensor/adxl367/CMakeLists.txt b/drivers/sensor/adi/adxl367/CMakeLists.txt similarity index 100% rename from drivers/sensor/adxl367/CMakeLists.txt rename to drivers/sensor/adi/adxl367/CMakeLists.txt diff --git a/drivers/sensor/adxl367/Kconfig b/drivers/sensor/adi/adxl367/Kconfig similarity index 100% rename from drivers/sensor/adxl367/Kconfig rename to drivers/sensor/adi/adxl367/Kconfig diff --git a/drivers/sensor/adxl367/adxl367.c b/drivers/sensor/adi/adxl367/adxl367.c similarity index 100% rename from drivers/sensor/adxl367/adxl367.c rename to drivers/sensor/adi/adxl367/adxl367.c diff --git a/drivers/sensor/adxl367/adxl367.h b/drivers/sensor/adi/adxl367/adxl367.h similarity index 100% rename from drivers/sensor/adxl367/adxl367.h rename to drivers/sensor/adi/adxl367/adxl367.h diff --git a/drivers/sensor/adxl367/adxl367_i2c.c b/drivers/sensor/adi/adxl367/adxl367_i2c.c similarity index 100% rename from drivers/sensor/adxl367/adxl367_i2c.c rename to drivers/sensor/adi/adxl367/adxl367_i2c.c diff --git a/drivers/sensor/adxl367/adxl367_spi.c b/drivers/sensor/adi/adxl367/adxl367_spi.c similarity index 100% rename from drivers/sensor/adxl367/adxl367_spi.c rename to drivers/sensor/adi/adxl367/adxl367_spi.c diff --git a/drivers/sensor/adxl367/adxl367_trigger.c b/drivers/sensor/adi/adxl367/adxl367_trigger.c similarity index 100% rename from drivers/sensor/adxl367/adxl367_trigger.c rename to drivers/sensor/adi/adxl367/adxl367_trigger.c diff --git a/drivers/sensor/adxl372/CMakeLists.txt b/drivers/sensor/adi/adxl372/CMakeLists.txt similarity index 100% rename from drivers/sensor/adxl372/CMakeLists.txt rename to drivers/sensor/adi/adxl372/CMakeLists.txt diff --git a/drivers/sensor/adxl372/Kconfig b/drivers/sensor/adi/adxl372/Kconfig similarity index 100% rename from drivers/sensor/adxl372/Kconfig rename to drivers/sensor/adi/adxl372/Kconfig diff --git a/drivers/sensor/adxl372/adxl372.c b/drivers/sensor/adi/adxl372/adxl372.c similarity index 100% rename from drivers/sensor/adxl372/adxl372.c rename to drivers/sensor/adi/adxl372/adxl372.c diff --git a/drivers/sensor/adxl372/adxl372.h b/drivers/sensor/adi/adxl372/adxl372.h similarity index 100% rename from drivers/sensor/adxl372/adxl372.h rename to drivers/sensor/adi/adxl372/adxl372.h diff --git a/drivers/sensor/adxl372/adxl372_i2c.c b/drivers/sensor/adi/adxl372/adxl372_i2c.c similarity index 100% rename from drivers/sensor/adxl372/adxl372_i2c.c rename to drivers/sensor/adi/adxl372/adxl372_i2c.c diff --git a/drivers/sensor/adxl372/adxl372_spi.c b/drivers/sensor/adi/adxl372/adxl372_spi.c similarity index 100% rename from drivers/sensor/adxl372/adxl372_spi.c rename to drivers/sensor/adi/adxl372/adxl372_spi.c diff --git a/drivers/sensor/adxl372/adxl372_trigger.c b/drivers/sensor/adi/adxl372/adxl372_trigger.c similarity index 100% rename from drivers/sensor/adxl372/adxl372_trigger.c rename to drivers/sensor/adi/adxl372/adxl372_trigger.c From 6320a96730dffe6c81581759a85fc55ef16d3ff0 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Tue, 26 Mar 2024 15:13:28 -0500 Subject: [PATCH 1965/2402] drivers: sensor: bosch: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 14 +------------- drivers/sensor/Kconfig | 14 +------------- drivers/sensor/bosch/CMakeLists.txt | 18 ++++++++++++++++++ drivers/sensor/bosch/Kconfig | 18 ++++++++++++++++++ .../sensor/{ => bosch}/bma280/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bma280/Kconfig | 0 drivers/sensor/{ => bosch}/bma280/bma280.c | 0 drivers/sensor/{ => bosch}/bma280/bma280.h | 0 .../sensor/{ => bosch}/bma280/bma280_trigger.c | 0 .../sensor/{ => bosch}/bma4xx/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bma4xx/Kconfig | 0 drivers/sensor/{ => bosch}/bma4xx/bma4xx.c | 0 drivers/sensor/{ => bosch}/bma4xx/bma4xx.h | 0 .../sensor/{ => bosch}/bma4xx/bma4xx_emul.c | 0 .../sensor/{ => bosch}/bma4xx/bma4xx_emul.h | 0 drivers/sensor/{ => bosch}/bma4xx/bma4xx_i2c.c | 0 drivers/sensor/{ => bosch}/bma4xx/bma4xx_spi.c | 0 .../{ => bosch}/bmc150_magn/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bmc150_magn/Kconfig | 0 .../{ => bosch}/bmc150_magn/bmc150_magn.c | 0 .../{ => bosch}/bmc150_magn/bmc150_magn.h | 0 .../bmc150_magn/bmc150_magn_trigger.c | 0 .../sensor/{ => bosch}/bme280/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bme280/Kconfig | 0 drivers/sensor/{ => bosch}/bme280/bme280.c | 0 drivers/sensor/{ => bosch}/bme280/bme280.h | 0 drivers/sensor/{ => bosch}/bme280/bme280_i2c.c | 0 drivers/sensor/{ => bosch}/bme280/bme280_spi.c | 0 .../sensor/{ => bosch}/bme680/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bme680/Kconfig | 0 drivers/sensor/{ => bosch}/bme680/bme680.c | 0 drivers/sensor/{ => bosch}/bme680/bme680.h | 0 drivers/sensor/{ => bosch}/bme680/bme680_i2c.c | 0 drivers/sensor/{ => bosch}/bme680/bme680_spi.c | 0 .../sensor/{ => bosch}/bmg160/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bmg160/Kconfig | 0 drivers/sensor/{ => bosch}/bmg160/bmg160.c | 0 drivers/sensor/{ => bosch}/bmg160/bmg160.h | 0 .../sensor/{ => bosch}/bmg160/bmg160_trigger.c | 0 .../sensor/{ => bosch}/bmi08x/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bmi08x/Kconfig | 0 drivers/sensor/{ => bosch}/bmi08x/bmi08x.c | 0 drivers/sensor/{ => bosch}/bmi08x/bmi08x.h | 0 .../sensor/{ => bosch}/bmi08x/bmi08x_accel.c | 0 .../{ => bosch}/bmi08x/bmi08x_accel_trigger.c | 0 .../{ => bosch}/bmi08x/bmi08x_config_file.h | 0 .../sensor/{ => bosch}/bmi08x/bmi08x_gyro.c | 0 .../{ => bosch}/bmi08x/bmi08x_gyro_trigger.c | 0 .../sensor/{ => bosch}/bmi160/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bmi160/Kconfig | 0 drivers/sensor/{ => bosch}/bmi160/bmi160.c | 0 drivers/sensor/{ => bosch}/bmi160/bmi160.h | 0 .../sensor/{ => bosch}/bmi160/bmi160_trigger.c | 0 .../sensor/{ => bosch}/bmi160/emul_bmi160.c | 0 .../sensor/{ => bosch}/bmi160/emul_bmi160.h | 0 .../sensor/{ => bosch}/bmi270/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bmi270/Kconfig | 0 drivers/sensor/{ => bosch}/bmi270/bmi270.c | 0 drivers/sensor/{ => bosch}/bmi270/bmi270.h | 0 .../{ => bosch}/bmi270/bmi270_config_file.h | 0 drivers/sensor/{ => bosch}/bmi270/bmi270_i2c.c | 0 drivers/sensor/{ => bosch}/bmi270/bmi270_spi.c | 0 .../sensor/{ => bosch}/bmi270/bmi270_trigger.c | 0 .../sensor/{ => bosch}/bmi323/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bmi323/Kconfig | 0 drivers/sensor/{ => bosch}/bmi323/bmi323.c | 0 drivers/sensor/{ => bosch}/bmi323/bmi323.h | 0 drivers/sensor/{ => bosch}/bmi323/bmi323_spi.c | 0 drivers/sensor/{ => bosch}/bmi323/bmi323_spi.h | 0 .../sensor/{ => bosch}/bmm150/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bmm150/Kconfig | 0 drivers/sensor/{ => bosch}/bmm150/bmm150.c | 0 drivers/sensor/{ => bosch}/bmm150/bmm150.h | 0 drivers/sensor/{ => bosch}/bmm150/bmm150_i2c.c | 0 drivers/sensor/{ => bosch}/bmm150/bmm150_spi.c | 0 .../sensor/{ => bosch}/bmm150/bmm150_trigger.c | 0 .../sensor/{ => bosch}/bmp388/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bmp388/Kconfig | 0 drivers/sensor/{ => bosch}/bmp388/bmp388.c | 0 drivers/sensor/{ => bosch}/bmp388/bmp388.h | 0 drivers/sensor/{ => bosch}/bmp388/bmp388_i2c.c | 0 drivers/sensor/{ => bosch}/bmp388/bmp388_spi.c | 0 .../sensor/{ => bosch}/bmp388/bmp388_trigger.c | 0 .../sensor/{ => bosch}/bmp581/CMakeLists.txt | 0 drivers/sensor/{ => bosch}/bmp581/Kconfig | 0 drivers/sensor/{ => bosch}/bmp581/bmp581.c | 0 drivers/sensor/{ => bosch}/bmp581/bmp581.h | 0 87 files changed, 38 insertions(+), 26 deletions(-) create mode 100644 drivers/sensor/bosch/CMakeLists.txt create mode 100644 drivers/sensor/bosch/Kconfig rename drivers/sensor/{ => bosch}/bma280/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bma280/Kconfig (100%) rename drivers/sensor/{ => bosch}/bma280/bma280.c (100%) rename drivers/sensor/{ => bosch}/bma280/bma280.h (100%) rename drivers/sensor/{ => bosch}/bma280/bma280_trigger.c (100%) rename drivers/sensor/{ => bosch}/bma4xx/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bma4xx/Kconfig (100%) rename drivers/sensor/{ => bosch}/bma4xx/bma4xx.c (100%) rename drivers/sensor/{ => bosch}/bma4xx/bma4xx.h (100%) rename drivers/sensor/{ => bosch}/bma4xx/bma4xx_emul.c (100%) rename drivers/sensor/{ => bosch}/bma4xx/bma4xx_emul.h (100%) rename drivers/sensor/{ => bosch}/bma4xx/bma4xx_i2c.c (100%) rename drivers/sensor/{ => bosch}/bma4xx/bma4xx_spi.c (100%) rename drivers/sensor/{ => bosch}/bmc150_magn/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bmc150_magn/Kconfig (100%) rename drivers/sensor/{ => bosch}/bmc150_magn/bmc150_magn.c (100%) rename drivers/sensor/{ => bosch}/bmc150_magn/bmc150_magn.h (100%) rename drivers/sensor/{ => bosch}/bmc150_magn/bmc150_magn_trigger.c (100%) rename drivers/sensor/{ => bosch}/bme280/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bme280/Kconfig (100%) rename drivers/sensor/{ => bosch}/bme280/bme280.c (100%) rename drivers/sensor/{ => bosch}/bme280/bme280.h (100%) rename drivers/sensor/{ => bosch}/bme280/bme280_i2c.c (100%) rename drivers/sensor/{ => bosch}/bme280/bme280_spi.c (100%) rename drivers/sensor/{ => bosch}/bme680/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bme680/Kconfig (100%) rename drivers/sensor/{ => bosch}/bme680/bme680.c (100%) rename drivers/sensor/{ => bosch}/bme680/bme680.h (100%) rename drivers/sensor/{ => bosch}/bme680/bme680_i2c.c (100%) rename drivers/sensor/{ => bosch}/bme680/bme680_spi.c (100%) rename drivers/sensor/{ => bosch}/bmg160/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bmg160/Kconfig (100%) rename drivers/sensor/{ => bosch}/bmg160/bmg160.c (100%) rename drivers/sensor/{ => bosch}/bmg160/bmg160.h (100%) rename drivers/sensor/{ => bosch}/bmg160/bmg160_trigger.c (100%) rename drivers/sensor/{ => bosch}/bmi08x/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bmi08x/Kconfig (100%) rename drivers/sensor/{ => bosch}/bmi08x/bmi08x.c (100%) rename drivers/sensor/{ => bosch}/bmi08x/bmi08x.h (100%) rename drivers/sensor/{ => bosch}/bmi08x/bmi08x_accel.c (100%) rename drivers/sensor/{ => bosch}/bmi08x/bmi08x_accel_trigger.c (100%) rename drivers/sensor/{ => bosch}/bmi08x/bmi08x_config_file.h (100%) rename drivers/sensor/{ => bosch}/bmi08x/bmi08x_gyro.c (100%) rename drivers/sensor/{ => bosch}/bmi08x/bmi08x_gyro_trigger.c (100%) rename drivers/sensor/{ => bosch}/bmi160/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bmi160/Kconfig (100%) rename drivers/sensor/{ => bosch}/bmi160/bmi160.c (100%) rename drivers/sensor/{ => bosch}/bmi160/bmi160.h (100%) rename drivers/sensor/{ => bosch}/bmi160/bmi160_trigger.c (100%) rename drivers/sensor/{ => bosch}/bmi160/emul_bmi160.c (100%) rename drivers/sensor/{ => bosch}/bmi160/emul_bmi160.h (100%) rename drivers/sensor/{ => bosch}/bmi270/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bmi270/Kconfig (100%) rename drivers/sensor/{ => bosch}/bmi270/bmi270.c (100%) rename drivers/sensor/{ => bosch}/bmi270/bmi270.h (100%) rename drivers/sensor/{ => bosch}/bmi270/bmi270_config_file.h (100%) rename drivers/sensor/{ => bosch}/bmi270/bmi270_i2c.c (100%) rename drivers/sensor/{ => bosch}/bmi270/bmi270_spi.c (100%) rename drivers/sensor/{ => bosch}/bmi270/bmi270_trigger.c (100%) rename drivers/sensor/{ => bosch}/bmi323/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bmi323/Kconfig (100%) rename drivers/sensor/{ => bosch}/bmi323/bmi323.c (100%) rename drivers/sensor/{ => bosch}/bmi323/bmi323.h (100%) rename drivers/sensor/{ => bosch}/bmi323/bmi323_spi.c (100%) rename drivers/sensor/{ => bosch}/bmi323/bmi323_spi.h (100%) rename drivers/sensor/{ => bosch}/bmm150/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bmm150/Kconfig (100%) rename drivers/sensor/{ => bosch}/bmm150/bmm150.c (100%) rename drivers/sensor/{ => bosch}/bmm150/bmm150.h (100%) rename drivers/sensor/{ => bosch}/bmm150/bmm150_i2c.c (100%) rename drivers/sensor/{ => bosch}/bmm150/bmm150_spi.c (100%) rename drivers/sensor/{ => bosch}/bmm150/bmm150_trigger.c (100%) rename drivers/sensor/{ => bosch}/bmp388/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bmp388/Kconfig (100%) rename drivers/sensor/{ => bosch}/bmp388/bmp388.c (100%) rename drivers/sensor/{ => bosch}/bmp388/bmp388.h (100%) rename drivers/sensor/{ => bosch}/bmp388/bmp388_i2c.c (100%) rename drivers/sensor/{ => bosch}/bmp388/bmp388_spi.c (100%) rename drivers/sensor/{ => bosch}/bmp388/bmp388_trigger.c (100%) rename drivers/sensor/{ => bosch}/bmp581/CMakeLists.txt (100%) rename drivers/sensor/{ => bosch}/bmp581/Kconfig (100%) rename drivers/sensor/{ => bosch}/bmp581/bmp581.c (100%) rename drivers/sensor/{ => bosch}/bmp581/bmp581.h (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 7a059531f60..e5dba6e5ad7 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -2,6 +2,7 @@ # zephyr-keep-sorted-start add_subdirectory(adi) +add_subdirectory(bosch) # zephyr-keep-sorted-stop add_subdirectory_ifdef(CONFIG_A01NYUB a01nyub) @@ -16,19 +17,6 @@ add_subdirectory_ifdef(CONFIG_AMS_IAQ_CORE ams_iAQcore) add_subdirectory_ifdef(CONFIG_APDS9960 apds9960) add_subdirectory_ifdef(CONFIG_BD8LB600FS_DIAGNOSTICS bd8lb600fs) add_subdirectory_ifdef(CONFIG_BH1750 bh1750) -add_subdirectory_ifdef(CONFIG_BMA280 bma280) -add_subdirectory_ifdef(CONFIG_BMA4XX bma4xx) -add_subdirectory_ifdef(CONFIG_BMC150_MAGN bmc150_magn) -add_subdirectory_ifdef(CONFIG_BME280 bme280) -add_subdirectory_ifdef(CONFIG_BME680 bme680) -add_subdirectory_ifdef(CONFIG_BMG160 bmg160) -add_subdirectory_ifdef(CONFIG_BMI08X bmi08x) -add_subdirectory_ifdef(CONFIG_BMI160 bmi160) -add_subdirectory_ifdef(CONFIG_BMI270 bmi270) -add_subdirectory_ifdef(CONFIG_BMI323 bmi323) -add_subdirectory_ifdef(CONFIG_BMM150 bmm150) -add_subdirectory_ifdef(CONFIG_BMP388 bmp388) -add_subdirectory_ifdef(CONFIG_BMP581 bmp581) add_subdirectory_ifdef(CONFIG_BQ274XX bq274xx) add_subdirectory_ifdef(CONFIG_CCS811 ccs811) add_subdirectory_ifdef(CONFIG_CURRENT_AMP current_amp) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 399e4730d69..7627a36ed0c 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -83,6 +83,7 @@ comment "Device Drivers" # zephyr-keep-sorted-start source "drivers/sensor/adi/Kconfig" +source "drivers/sensor/bosch/Kconfig" # zephyr-keep-sorted-stop source "drivers/sensor/a01nyub/Kconfig" @@ -96,19 +97,6 @@ source "drivers/sensor/ams_iAQcore/Kconfig" source "drivers/sensor/apds9960/Kconfig" source "drivers/sensor/bd8lb600fs/Kconfig" source "drivers/sensor/bh1750/Kconfig" -source "drivers/sensor/bma280/Kconfig" -source "drivers/sensor/bma4xx/Kconfig" -source "drivers/sensor/bmc150_magn/Kconfig" -source "drivers/sensor/bme280/Kconfig" -source "drivers/sensor/bme680/Kconfig" -source "drivers/sensor/bmg160/Kconfig" -source "drivers/sensor/bmi08x/Kconfig" -source "drivers/sensor/bmi160/Kconfig" -source "drivers/sensor/bmi270/Kconfig" -source "drivers/sensor/bmi323/Kconfig" -source "drivers/sensor/bmm150/Kconfig" -source "drivers/sensor/bmp388/Kconfig" -source "drivers/sensor/bmp581/Kconfig" source "drivers/sensor/bq274xx/Kconfig" source "drivers/sensor/ccs811/Kconfig" source "drivers/sensor/current_amp/Kconfig" diff --git a/drivers/sensor/bosch/CMakeLists.txt b/drivers/sensor/bosch/CMakeLists.txt new file mode 100644 index 00000000000..e7652dbf0b5 --- /dev/null +++ b/drivers/sensor/bosch/CMakeLists.txt @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_BMA280 bma280) +add_subdirectory_ifdef(CONFIG_BMA4XX bma4xx) +add_subdirectory_ifdef(CONFIG_BMC150_MAGN bmc150_magn) +add_subdirectory_ifdef(CONFIG_BME280 bme280) +add_subdirectory_ifdef(CONFIG_BME680 bme680) +add_subdirectory_ifdef(CONFIG_BMG160 bmg160) +add_subdirectory_ifdef(CONFIG_BMI08X bmi08x) +add_subdirectory_ifdef(CONFIG_BMI160 bmi160) +add_subdirectory_ifdef(CONFIG_BMI270 bmi270) +add_subdirectory_ifdef(CONFIG_BMI323 bmi323) +add_subdirectory_ifdef(CONFIG_BMM150 bmm150) +add_subdirectory_ifdef(CONFIG_BMP388 bmp388) +add_subdirectory_ifdef(CONFIG_BMP581 bmp581) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/bosch/Kconfig b/drivers/sensor/bosch/Kconfig new file mode 100644 index 00000000000..5e27c3d3f9e --- /dev/null +++ b/drivers/sensor/bosch/Kconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/bosch/bma280/Kconfig" +source "drivers/sensor/bosch/bma4xx/Kconfig" +source "drivers/sensor/bosch/bmc150_magn/Kconfig" +source "drivers/sensor/bosch/bme280/Kconfig" +source "drivers/sensor/bosch/bme680/Kconfig" +source "drivers/sensor/bosch/bmg160/Kconfig" +source "drivers/sensor/bosch/bmi08x/Kconfig" +source "drivers/sensor/bosch/bmi160/Kconfig" +source "drivers/sensor/bosch/bmi270/Kconfig" +source "drivers/sensor/bosch/bmi323/Kconfig" +source "drivers/sensor/bosch/bmm150/Kconfig" +source "drivers/sensor/bosch/bmp388/Kconfig" +source "drivers/sensor/bosch/bmp581/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/bma280/CMakeLists.txt b/drivers/sensor/bosch/bma280/CMakeLists.txt similarity index 100% rename from drivers/sensor/bma280/CMakeLists.txt rename to drivers/sensor/bosch/bma280/CMakeLists.txt diff --git a/drivers/sensor/bma280/Kconfig b/drivers/sensor/bosch/bma280/Kconfig similarity index 100% rename from drivers/sensor/bma280/Kconfig rename to drivers/sensor/bosch/bma280/Kconfig diff --git a/drivers/sensor/bma280/bma280.c b/drivers/sensor/bosch/bma280/bma280.c similarity index 100% rename from drivers/sensor/bma280/bma280.c rename to drivers/sensor/bosch/bma280/bma280.c diff --git a/drivers/sensor/bma280/bma280.h b/drivers/sensor/bosch/bma280/bma280.h similarity index 100% rename from drivers/sensor/bma280/bma280.h rename to drivers/sensor/bosch/bma280/bma280.h diff --git a/drivers/sensor/bma280/bma280_trigger.c b/drivers/sensor/bosch/bma280/bma280_trigger.c similarity index 100% rename from drivers/sensor/bma280/bma280_trigger.c rename to drivers/sensor/bosch/bma280/bma280_trigger.c diff --git a/drivers/sensor/bma4xx/CMakeLists.txt b/drivers/sensor/bosch/bma4xx/CMakeLists.txt similarity index 100% rename from drivers/sensor/bma4xx/CMakeLists.txt rename to drivers/sensor/bosch/bma4xx/CMakeLists.txt diff --git a/drivers/sensor/bma4xx/Kconfig b/drivers/sensor/bosch/bma4xx/Kconfig similarity index 100% rename from drivers/sensor/bma4xx/Kconfig rename to drivers/sensor/bosch/bma4xx/Kconfig diff --git a/drivers/sensor/bma4xx/bma4xx.c b/drivers/sensor/bosch/bma4xx/bma4xx.c similarity index 100% rename from drivers/sensor/bma4xx/bma4xx.c rename to drivers/sensor/bosch/bma4xx/bma4xx.c diff --git a/drivers/sensor/bma4xx/bma4xx.h b/drivers/sensor/bosch/bma4xx/bma4xx.h similarity index 100% rename from drivers/sensor/bma4xx/bma4xx.h rename to drivers/sensor/bosch/bma4xx/bma4xx.h diff --git a/drivers/sensor/bma4xx/bma4xx_emul.c b/drivers/sensor/bosch/bma4xx/bma4xx_emul.c similarity index 100% rename from drivers/sensor/bma4xx/bma4xx_emul.c rename to drivers/sensor/bosch/bma4xx/bma4xx_emul.c diff --git a/drivers/sensor/bma4xx/bma4xx_emul.h b/drivers/sensor/bosch/bma4xx/bma4xx_emul.h similarity index 100% rename from drivers/sensor/bma4xx/bma4xx_emul.h rename to drivers/sensor/bosch/bma4xx/bma4xx_emul.h diff --git a/drivers/sensor/bma4xx/bma4xx_i2c.c b/drivers/sensor/bosch/bma4xx/bma4xx_i2c.c similarity index 100% rename from drivers/sensor/bma4xx/bma4xx_i2c.c rename to drivers/sensor/bosch/bma4xx/bma4xx_i2c.c diff --git a/drivers/sensor/bma4xx/bma4xx_spi.c b/drivers/sensor/bosch/bma4xx/bma4xx_spi.c similarity index 100% rename from drivers/sensor/bma4xx/bma4xx_spi.c rename to drivers/sensor/bosch/bma4xx/bma4xx_spi.c diff --git a/drivers/sensor/bmc150_magn/CMakeLists.txt b/drivers/sensor/bosch/bmc150_magn/CMakeLists.txt similarity index 100% rename from drivers/sensor/bmc150_magn/CMakeLists.txt rename to drivers/sensor/bosch/bmc150_magn/CMakeLists.txt diff --git a/drivers/sensor/bmc150_magn/Kconfig b/drivers/sensor/bosch/bmc150_magn/Kconfig similarity index 100% rename from drivers/sensor/bmc150_magn/Kconfig rename to drivers/sensor/bosch/bmc150_magn/Kconfig diff --git a/drivers/sensor/bmc150_magn/bmc150_magn.c b/drivers/sensor/bosch/bmc150_magn/bmc150_magn.c similarity index 100% rename from drivers/sensor/bmc150_magn/bmc150_magn.c rename to drivers/sensor/bosch/bmc150_magn/bmc150_magn.c diff --git a/drivers/sensor/bmc150_magn/bmc150_magn.h b/drivers/sensor/bosch/bmc150_magn/bmc150_magn.h similarity index 100% rename from drivers/sensor/bmc150_magn/bmc150_magn.h rename to drivers/sensor/bosch/bmc150_magn/bmc150_magn.h diff --git a/drivers/sensor/bmc150_magn/bmc150_magn_trigger.c b/drivers/sensor/bosch/bmc150_magn/bmc150_magn_trigger.c similarity index 100% rename from drivers/sensor/bmc150_magn/bmc150_magn_trigger.c rename to drivers/sensor/bosch/bmc150_magn/bmc150_magn_trigger.c diff --git a/drivers/sensor/bme280/CMakeLists.txt b/drivers/sensor/bosch/bme280/CMakeLists.txt similarity index 100% rename from drivers/sensor/bme280/CMakeLists.txt rename to drivers/sensor/bosch/bme280/CMakeLists.txt diff --git a/drivers/sensor/bme280/Kconfig b/drivers/sensor/bosch/bme280/Kconfig similarity index 100% rename from drivers/sensor/bme280/Kconfig rename to drivers/sensor/bosch/bme280/Kconfig diff --git a/drivers/sensor/bme280/bme280.c b/drivers/sensor/bosch/bme280/bme280.c similarity index 100% rename from drivers/sensor/bme280/bme280.c rename to drivers/sensor/bosch/bme280/bme280.c diff --git a/drivers/sensor/bme280/bme280.h b/drivers/sensor/bosch/bme280/bme280.h similarity index 100% rename from drivers/sensor/bme280/bme280.h rename to drivers/sensor/bosch/bme280/bme280.h diff --git a/drivers/sensor/bme280/bme280_i2c.c b/drivers/sensor/bosch/bme280/bme280_i2c.c similarity index 100% rename from drivers/sensor/bme280/bme280_i2c.c rename to drivers/sensor/bosch/bme280/bme280_i2c.c diff --git a/drivers/sensor/bme280/bme280_spi.c b/drivers/sensor/bosch/bme280/bme280_spi.c similarity index 100% rename from drivers/sensor/bme280/bme280_spi.c rename to drivers/sensor/bosch/bme280/bme280_spi.c diff --git a/drivers/sensor/bme680/CMakeLists.txt b/drivers/sensor/bosch/bme680/CMakeLists.txt similarity index 100% rename from drivers/sensor/bme680/CMakeLists.txt rename to drivers/sensor/bosch/bme680/CMakeLists.txt diff --git a/drivers/sensor/bme680/Kconfig b/drivers/sensor/bosch/bme680/Kconfig similarity index 100% rename from drivers/sensor/bme680/Kconfig rename to drivers/sensor/bosch/bme680/Kconfig diff --git a/drivers/sensor/bme680/bme680.c b/drivers/sensor/bosch/bme680/bme680.c similarity index 100% rename from drivers/sensor/bme680/bme680.c rename to drivers/sensor/bosch/bme680/bme680.c diff --git a/drivers/sensor/bme680/bme680.h b/drivers/sensor/bosch/bme680/bme680.h similarity index 100% rename from drivers/sensor/bme680/bme680.h rename to drivers/sensor/bosch/bme680/bme680.h diff --git a/drivers/sensor/bme680/bme680_i2c.c b/drivers/sensor/bosch/bme680/bme680_i2c.c similarity index 100% rename from drivers/sensor/bme680/bme680_i2c.c rename to drivers/sensor/bosch/bme680/bme680_i2c.c diff --git a/drivers/sensor/bme680/bme680_spi.c b/drivers/sensor/bosch/bme680/bme680_spi.c similarity index 100% rename from drivers/sensor/bme680/bme680_spi.c rename to drivers/sensor/bosch/bme680/bme680_spi.c diff --git a/drivers/sensor/bmg160/CMakeLists.txt b/drivers/sensor/bosch/bmg160/CMakeLists.txt similarity index 100% rename from drivers/sensor/bmg160/CMakeLists.txt rename to drivers/sensor/bosch/bmg160/CMakeLists.txt diff --git a/drivers/sensor/bmg160/Kconfig b/drivers/sensor/bosch/bmg160/Kconfig similarity index 100% rename from drivers/sensor/bmg160/Kconfig rename to drivers/sensor/bosch/bmg160/Kconfig diff --git a/drivers/sensor/bmg160/bmg160.c b/drivers/sensor/bosch/bmg160/bmg160.c similarity index 100% rename from drivers/sensor/bmg160/bmg160.c rename to drivers/sensor/bosch/bmg160/bmg160.c diff --git a/drivers/sensor/bmg160/bmg160.h b/drivers/sensor/bosch/bmg160/bmg160.h similarity index 100% rename from drivers/sensor/bmg160/bmg160.h rename to drivers/sensor/bosch/bmg160/bmg160.h diff --git a/drivers/sensor/bmg160/bmg160_trigger.c b/drivers/sensor/bosch/bmg160/bmg160_trigger.c similarity index 100% rename from drivers/sensor/bmg160/bmg160_trigger.c rename to drivers/sensor/bosch/bmg160/bmg160_trigger.c diff --git a/drivers/sensor/bmi08x/CMakeLists.txt b/drivers/sensor/bosch/bmi08x/CMakeLists.txt similarity index 100% rename from drivers/sensor/bmi08x/CMakeLists.txt rename to drivers/sensor/bosch/bmi08x/CMakeLists.txt diff --git a/drivers/sensor/bmi08x/Kconfig b/drivers/sensor/bosch/bmi08x/Kconfig similarity index 100% rename from drivers/sensor/bmi08x/Kconfig rename to drivers/sensor/bosch/bmi08x/Kconfig diff --git a/drivers/sensor/bmi08x/bmi08x.c b/drivers/sensor/bosch/bmi08x/bmi08x.c similarity index 100% rename from drivers/sensor/bmi08x/bmi08x.c rename to drivers/sensor/bosch/bmi08x/bmi08x.c diff --git a/drivers/sensor/bmi08x/bmi08x.h b/drivers/sensor/bosch/bmi08x/bmi08x.h similarity index 100% rename from drivers/sensor/bmi08x/bmi08x.h rename to drivers/sensor/bosch/bmi08x/bmi08x.h diff --git a/drivers/sensor/bmi08x/bmi08x_accel.c b/drivers/sensor/bosch/bmi08x/bmi08x_accel.c similarity index 100% rename from drivers/sensor/bmi08x/bmi08x_accel.c rename to drivers/sensor/bosch/bmi08x/bmi08x_accel.c diff --git a/drivers/sensor/bmi08x/bmi08x_accel_trigger.c b/drivers/sensor/bosch/bmi08x/bmi08x_accel_trigger.c similarity index 100% rename from drivers/sensor/bmi08x/bmi08x_accel_trigger.c rename to drivers/sensor/bosch/bmi08x/bmi08x_accel_trigger.c diff --git a/drivers/sensor/bmi08x/bmi08x_config_file.h b/drivers/sensor/bosch/bmi08x/bmi08x_config_file.h similarity index 100% rename from drivers/sensor/bmi08x/bmi08x_config_file.h rename to drivers/sensor/bosch/bmi08x/bmi08x_config_file.h diff --git a/drivers/sensor/bmi08x/bmi08x_gyro.c b/drivers/sensor/bosch/bmi08x/bmi08x_gyro.c similarity index 100% rename from drivers/sensor/bmi08x/bmi08x_gyro.c rename to drivers/sensor/bosch/bmi08x/bmi08x_gyro.c diff --git a/drivers/sensor/bmi08x/bmi08x_gyro_trigger.c b/drivers/sensor/bosch/bmi08x/bmi08x_gyro_trigger.c similarity index 100% rename from drivers/sensor/bmi08x/bmi08x_gyro_trigger.c rename to drivers/sensor/bosch/bmi08x/bmi08x_gyro_trigger.c diff --git a/drivers/sensor/bmi160/CMakeLists.txt b/drivers/sensor/bosch/bmi160/CMakeLists.txt similarity index 100% rename from drivers/sensor/bmi160/CMakeLists.txt rename to drivers/sensor/bosch/bmi160/CMakeLists.txt diff --git a/drivers/sensor/bmi160/Kconfig b/drivers/sensor/bosch/bmi160/Kconfig similarity index 100% rename from drivers/sensor/bmi160/Kconfig rename to drivers/sensor/bosch/bmi160/Kconfig diff --git a/drivers/sensor/bmi160/bmi160.c b/drivers/sensor/bosch/bmi160/bmi160.c similarity index 100% rename from drivers/sensor/bmi160/bmi160.c rename to drivers/sensor/bosch/bmi160/bmi160.c diff --git a/drivers/sensor/bmi160/bmi160.h b/drivers/sensor/bosch/bmi160/bmi160.h similarity index 100% rename from drivers/sensor/bmi160/bmi160.h rename to drivers/sensor/bosch/bmi160/bmi160.h diff --git a/drivers/sensor/bmi160/bmi160_trigger.c b/drivers/sensor/bosch/bmi160/bmi160_trigger.c similarity index 100% rename from drivers/sensor/bmi160/bmi160_trigger.c rename to drivers/sensor/bosch/bmi160/bmi160_trigger.c diff --git a/drivers/sensor/bmi160/emul_bmi160.c b/drivers/sensor/bosch/bmi160/emul_bmi160.c similarity index 100% rename from drivers/sensor/bmi160/emul_bmi160.c rename to drivers/sensor/bosch/bmi160/emul_bmi160.c diff --git a/drivers/sensor/bmi160/emul_bmi160.h b/drivers/sensor/bosch/bmi160/emul_bmi160.h similarity index 100% rename from drivers/sensor/bmi160/emul_bmi160.h rename to drivers/sensor/bosch/bmi160/emul_bmi160.h diff --git a/drivers/sensor/bmi270/CMakeLists.txt b/drivers/sensor/bosch/bmi270/CMakeLists.txt similarity index 100% rename from drivers/sensor/bmi270/CMakeLists.txt rename to drivers/sensor/bosch/bmi270/CMakeLists.txt diff --git a/drivers/sensor/bmi270/Kconfig b/drivers/sensor/bosch/bmi270/Kconfig similarity index 100% rename from drivers/sensor/bmi270/Kconfig rename to drivers/sensor/bosch/bmi270/Kconfig diff --git a/drivers/sensor/bmi270/bmi270.c b/drivers/sensor/bosch/bmi270/bmi270.c similarity index 100% rename from drivers/sensor/bmi270/bmi270.c rename to drivers/sensor/bosch/bmi270/bmi270.c diff --git a/drivers/sensor/bmi270/bmi270.h b/drivers/sensor/bosch/bmi270/bmi270.h similarity index 100% rename from drivers/sensor/bmi270/bmi270.h rename to drivers/sensor/bosch/bmi270/bmi270.h diff --git a/drivers/sensor/bmi270/bmi270_config_file.h b/drivers/sensor/bosch/bmi270/bmi270_config_file.h similarity index 100% rename from drivers/sensor/bmi270/bmi270_config_file.h rename to drivers/sensor/bosch/bmi270/bmi270_config_file.h diff --git a/drivers/sensor/bmi270/bmi270_i2c.c b/drivers/sensor/bosch/bmi270/bmi270_i2c.c similarity index 100% rename from drivers/sensor/bmi270/bmi270_i2c.c rename to drivers/sensor/bosch/bmi270/bmi270_i2c.c diff --git a/drivers/sensor/bmi270/bmi270_spi.c b/drivers/sensor/bosch/bmi270/bmi270_spi.c similarity index 100% rename from drivers/sensor/bmi270/bmi270_spi.c rename to drivers/sensor/bosch/bmi270/bmi270_spi.c diff --git a/drivers/sensor/bmi270/bmi270_trigger.c b/drivers/sensor/bosch/bmi270/bmi270_trigger.c similarity index 100% rename from drivers/sensor/bmi270/bmi270_trigger.c rename to drivers/sensor/bosch/bmi270/bmi270_trigger.c diff --git a/drivers/sensor/bmi323/CMakeLists.txt b/drivers/sensor/bosch/bmi323/CMakeLists.txt similarity index 100% rename from drivers/sensor/bmi323/CMakeLists.txt rename to drivers/sensor/bosch/bmi323/CMakeLists.txt diff --git a/drivers/sensor/bmi323/Kconfig b/drivers/sensor/bosch/bmi323/Kconfig similarity index 100% rename from drivers/sensor/bmi323/Kconfig rename to drivers/sensor/bosch/bmi323/Kconfig diff --git a/drivers/sensor/bmi323/bmi323.c b/drivers/sensor/bosch/bmi323/bmi323.c similarity index 100% rename from drivers/sensor/bmi323/bmi323.c rename to drivers/sensor/bosch/bmi323/bmi323.c diff --git a/drivers/sensor/bmi323/bmi323.h b/drivers/sensor/bosch/bmi323/bmi323.h similarity index 100% rename from drivers/sensor/bmi323/bmi323.h rename to drivers/sensor/bosch/bmi323/bmi323.h diff --git a/drivers/sensor/bmi323/bmi323_spi.c b/drivers/sensor/bosch/bmi323/bmi323_spi.c similarity index 100% rename from drivers/sensor/bmi323/bmi323_spi.c rename to drivers/sensor/bosch/bmi323/bmi323_spi.c diff --git a/drivers/sensor/bmi323/bmi323_spi.h b/drivers/sensor/bosch/bmi323/bmi323_spi.h similarity index 100% rename from drivers/sensor/bmi323/bmi323_spi.h rename to drivers/sensor/bosch/bmi323/bmi323_spi.h diff --git a/drivers/sensor/bmm150/CMakeLists.txt b/drivers/sensor/bosch/bmm150/CMakeLists.txt similarity index 100% rename from drivers/sensor/bmm150/CMakeLists.txt rename to drivers/sensor/bosch/bmm150/CMakeLists.txt diff --git a/drivers/sensor/bmm150/Kconfig b/drivers/sensor/bosch/bmm150/Kconfig similarity index 100% rename from drivers/sensor/bmm150/Kconfig rename to drivers/sensor/bosch/bmm150/Kconfig diff --git a/drivers/sensor/bmm150/bmm150.c b/drivers/sensor/bosch/bmm150/bmm150.c similarity index 100% rename from drivers/sensor/bmm150/bmm150.c rename to drivers/sensor/bosch/bmm150/bmm150.c diff --git a/drivers/sensor/bmm150/bmm150.h b/drivers/sensor/bosch/bmm150/bmm150.h similarity index 100% rename from drivers/sensor/bmm150/bmm150.h rename to drivers/sensor/bosch/bmm150/bmm150.h diff --git a/drivers/sensor/bmm150/bmm150_i2c.c b/drivers/sensor/bosch/bmm150/bmm150_i2c.c similarity index 100% rename from drivers/sensor/bmm150/bmm150_i2c.c rename to drivers/sensor/bosch/bmm150/bmm150_i2c.c diff --git a/drivers/sensor/bmm150/bmm150_spi.c b/drivers/sensor/bosch/bmm150/bmm150_spi.c similarity index 100% rename from drivers/sensor/bmm150/bmm150_spi.c rename to drivers/sensor/bosch/bmm150/bmm150_spi.c diff --git a/drivers/sensor/bmm150/bmm150_trigger.c b/drivers/sensor/bosch/bmm150/bmm150_trigger.c similarity index 100% rename from drivers/sensor/bmm150/bmm150_trigger.c rename to drivers/sensor/bosch/bmm150/bmm150_trigger.c diff --git a/drivers/sensor/bmp388/CMakeLists.txt b/drivers/sensor/bosch/bmp388/CMakeLists.txt similarity index 100% rename from drivers/sensor/bmp388/CMakeLists.txt rename to drivers/sensor/bosch/bmp388/CMakeLists.txt diff --git a/drivers/sensor/bmp388/Kconfig b/drivers/sensor/bosch/bmp388/Kconfig similarity index 100% rename from drivers/sensor/bmp388/Kconfig rename to drivers/sensor/bosch/bmp388/Kconfig diff --git a/drivers/sensor/bmp388/bmp388.c b/drivers/sensor/bosch/bmp388/bmp388.c similarity index 100% rename from drivers/sensor/bmp388/bmp388.c rename to drivers/sensor/bosch/bmp388/bmp388.c diff --git a/drivers/sensor/bmp388/bmp388.h b/drivers/sensor/bosch/bmp388/bmp388.h similarity index 100% rename from drivers/sensor/bmp388/bmp388.h rename to drivers/sensor/bosch/bmp388/bmp388.h diff --git a/drivers/sensor/bmp388/bmp388_i2c.c b/drivers/sensor/bosch/bmp388/bmp388_i2c.c similarity index 100% rename from drivers/sensor/bmp388/bmp388_i2c.c rename to drivers/sensor/bosch/bmp388/bmp388_i2c.c diff --git a/drivers/sensor/bmp388/bmp388_spi.c b/drivers/sensor/bosch/bmp388/bmp388_spi.c similarity index 100% rename from drivers/sensor/bmp388/bmp388_spi.c rename to drivers/sensor/bosch/bmp388/bmp388_spi.c diff --git a/drivers/sensor/bmp388/bmp388_trigger.c b/drivers/sensor/bosch/bmp388/bmp388_trigger.c similarity index 100% rename from drivers/sensor/bmp388/bmp388_trigger.c rename to drivers/sensor/bosch/bmp388/bmp388_trigger.c diff --git a/drivers/sensor/bmp581/CMakeLists.txt b/drivers/sensor/bosch/bmp581/CMakeLists.txt similarity index 100% rename from drivers/sensor/bmp581/CMakeLists.txt rename to drivers/sensor/bosch/bmp581/CMakeLists.txt diff --git a/drivers/sensor/bmp581/Kconfig b/drivers/sensor/bosch/bmp581/Kconfig similarity index 100% rename from drivers/sensor/bmp581/Kconfig rename to drivers/sensor/bosch/bmp581/Kconfig diff --git a/drivers/sensor/bmp581/bmp581.c b/drivers/sensor/bosch/bmp581/bmp581.c similarity index 100% rename from drivers/sensor/bmp581/bmp581.c rename to drivers/sensor/bosch/bmp581/bmp581.c diff --git a/drivers/sensor/bmp581/bmp581.h b/drivers/sensor/bosch/bmp581/bmp581.h similarity index 100% rename from drivers/sensor/bmp581/bmp581.h rename to drivers/sensor/bosch/bmp581/bmp581.h From 5b9454f5204b72a4f15d8a344a20d544bd456663 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Tue, 26 Mar 2024 15:30:29 -0500 Subject: [PATCH 1966/2402] drivers: sensor: st: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 39 +---------------- drivers/sensor/Kconfig | 38 +--------------- drivers/sensor/st/CMakeLists.txt | 43 +++++++++++++++++++ drivers/sensor/st/Kconfig | 42 ++++++++++++++++++ drivers/sensor/{ => st}/hts221/CMakeLists.txt | 0 drivers/sensor/{ => st}/hts221/Kconfig | 0 drivers/sensor/{ => st}/hts221/hts221.c | 0 drivers/sensor/{ => st}/hts221/hts221.h | 0 .../sensor/{ => st}/hts221/hts221_trigger.c | 0 .../sensor/{ => st}/i3g4250d/CMakeLists.txt | 0 drivers/sensor/{ => st}/i3g4250d/Kconfig | 0 drivers/sensor/{ => st}/i3g4250d/i3g4250d.c | 0 drivers/sensor/{ => st}/i3g4250d/i3g4250d.h | 0 .../sensor/{ => st}/i3g4250d/i3g4250d_spi.c | 0 drivers/sensor/{ => st}/iis2dh/CMakeLists.txt | 0 drivers/sensor/{ => st}/iis2dh/Kconfig | 0 drivers/sensor/{ => st}/iis2dh/iis2dh.c | 0 drivers/sensor/{ => st}/iis2dh/iis2dh.h | 0 drivers/sensor/{ => st}/iis2dh/iis2dh_i2c.c | 0 drivers/sensor/{ => st}/iis2dh/iis2dh_spi.c | 0 .../sensor/{ => st}/iis2dh/iis2dh_trigger.c | 0 .../sensor/{ => st}/iis2dlpc/CMakeLists.txt | 0 drivers/sensor/{ => st}/iis2dlpc/Kconfig | 0 drivers/sensor/{ => st}/iis2dlpc/iis2dlpc.c | 0 drivers/sensor/{ => st}/iis2dlpc/iis2dlpc.h | 0 .../{ => st}/iis2dlpc/iis2dlpc_trigger.c | 0 .../sensor/{ => st}/iis2iclx/CMakeLists.txt | 0 drivers/sensor/{ => st}/iis2iclx/Kconfig | 0 drivers/sensor/{ => st}/iis2iclx/iis2iclx.c | 0 drivers/sensor/{ => st}/iis2iclx/iis2iclx.h | 0 .../sensor/{ => st}/iis2iclx/iis2iclx_shub.c | 0 .../{ => st}/iis2iclx/iis2iclx_trigger.c | 0 .../sensor/{ => st}/iis2mdc/CMakeLists.txt | 0 drivers/sensor/{ => st}/iis2mdc/Kconfig | 0 drivers/sensor/{ => st}/iis2mdc/iis2mdc.c | 0 drivers/sensor/{ => st}/iis2mdc/iis2mdc.h | 0 drivers/sensor/{ => st}/iis2mdc/iis2mdc_i2c.c | 0 drivers/sensor/{ => st}/iis2mdc/iis2mdc_spi.c | 0 .../sensor/{ => st}/iis2mdc/iis2mdc_trigger.c | 0 .../sensor/{ => st}/iis328dq/CMakeLists.txt | 0 drivers/sensor/{ => st}/iis328dq/Kconfig | 0 drivers/sensor/{ => st}/iis328dq/iis328dq.c | 0 drivers/sensor/{ => st}/iis328dq/iis328dq.h | 0 .../{ => st}/iis328dq/iis328dq_trigger.c | 0 .../sensor/{ => st}/iis3dhhc/CMakeLists.txt | 0 drivers/sensor/{ => st}/iis3dhhc/Kconfig | 0 drivers/sensor/{ => st}/iis3dhhc/iis3dhhc.c | 0 drivers/sensor/{ => st}/iis3dhhc/iis3dhhc.h | 0 .../sensor/{ => st}/iis3dhhc/iis3dhhc_spi.c | 0 .../{ => st}/iis3dhhc/iis3dhhc_trigger.c | 0 .../sensor/{ => st}/ism330dhcx/CMakeLists.txt | 0 drivers/sensor/{ => st}/ism330dhcx/Kconfig | 0 .../sensor/{ => st}/ism330dhcx/ism330dhcx.c | 0 .../sensor/{ => st}/ism330dhcx/ism330dhcx.h | 0 .../{ => st}/ism330dhcx/ism330dhcx_i2c.c | 0 .../{ => st}/ism330dhcx/ism330dhcx_shub.c | 0 .../{ => st}/ism330dhcx/ism330dhcx_spi.c | 0 .../{ => st}/ism330dhcx/ism330dhcx_trigger.c | 0 .../sensor/{ => st}/lis2de12/CMakeLists.txt | 0 drivers/sensor/{ => st}/lis2de12/Kconfig | 0 drivers/sensor/{ => st}/lis2de12/lis2de12.c | 0 drivers/sensor/{ => st}/lis2de12/lis2de12.h | 0 .../{ => st}/lis2de12/lis2de12_trigger.c | 0 drivers/sensor/{ => st}/lis2dh/CMakeLists.txt | 0 drivers/sensor/{ => st}/lis2dh/Kconfig | 0 drivers/sensor/{ => st}/lis2dh/lis2dh.c | 0 drivers/sensor/{ => st}/lis2dh/lis2dh.h | 0 drivers/sensor/{ => st}/lis2dh/lis2dh_i2c.c | 0 drivers/sensor/{ => st}/lis2dh/lis2dh_spi.c | 0 .../sensor/{ => st}/lis2dh/lis2dh_trigger.c | 0 .../sensor/{ => st}/lis2ds12/CMakeLists.txt | 0 drivers/sensor/{ => st}/lis2ds12/Kconfig | 0 drivers/sensor/{ => st}/lis2ds12/lis2ds12.c | 0 drivers/sensor/{ => st}/lis2ds12/lis2ds12.h | 0 .../{ => st}/lis2ds12/lis2ds12_trigger.c | 0 .../sensor/{ => st}/lis2du12/CMakeLists.txt | 0 drivers/sensor/{ => st}/lis2du12/Kconfig | 0 drivers/sensor/{ => st}/lis2du12/lis2du12.c | 0 drivers/sensor/{ => st}/lis2du12/lis2du12.h | 0 .../{ => st}/lis2du12/lis2du12_trigger.c | 0 .../sensor/{ => st}/lis2dux12/CMakeLists.txt | 0 drivers/sensor/{ => st}/lis2dux12/Kconfig | 0 drivers/sensor/{ => st}/lis2dux12/lis2dux12.c | 0 drivers/sensor/{ => st}/lis2dux12/lis2dux12.h | 0 .../{ => st}/lis2dux12/lis2dux12_trigger.c | 0 .../sensor/{ => st}/lis2dw12/CMakeLists.txt | 0 drivers/sensor/{ => st}/lis2dw12/Kconfig | 0 drivers/sensor/{ => st}/lis2dw12/lis2dw12.c | 0 drivers/sensor/{ => st}/lis2dw12/lis2dw12.h | 0 .../{ => st}/lis2dw12/lis2dw12_trigger.c | 0 .../sensor/{ => st}/lis2mdl/CMakeLists.txt | 0 drivers/sensor/{ => st}/lis2mdl/Kconfig | 0 drivers/sensor/{ => st}/lis2mdl/lis2mdl.c | 0 drivers/sensor/{ => st}/lis2mdl/lis2mdl.h | 0 .../sensor/{ => st}/lis2mdl/lis2mdl_trigger.c | 0 .../sensor/{ => st}/lis3mdl/CMakeLists.txt | 0 drivers/sensor/{ => st}/lis3mdl/Kconfig | 0 drivers/sensor/{ => st}/lis3mdl/lis3mdl.c | 0 drivers/sensor/{ => st}/lis3mdl/lis3mdl.h | 0 .../sensor/{ => st}/lis3mdl/lis3mdl_trigger.c | 0 .../sensor/{ => st}/lps22hb/CMakeLists.txt | 0 drivers/sensor/{ => st}/lps22hb/Kconfig | 0 drivers/sensor/{ => st}/lps22hb/lps22hb.c | 0 drivers/sensor/{ => st}/lps22hb/lps22hb.h | 0 .../sensor/{ => st}/lps22hh/CMakeLists.txt | 0 drivers/sensor/{ => st}/lps22hh/Kconfig | 0 drivers/sensor/{ => st}/lps22hh/lps22hh.c | 0 drivers/sensor/{ => st}/lps22hh/lps22hh.h | 0 .../sensor/{ => st}/lps22hh/lps22hh_trigger.c | 0 .../sensor/{ => st}/lps25hb/CMakeLists.txt | 0 drivers/sensor/{ => st}/lps25hb/Kconfig | 0 drivers/sensor/{ => st}/lps25hb/lps25hb.c | 0 drivers/sensor/{ => st}/lps25hb/lps25hb.h | 0 .../sensor/{ => st}/lps2xdf/CMakeLists.txt | 0 drivers/sensor/{ => st}/lps2xdf/Kconfig | 0 drivers/sensor/{ => st}/lps2xdf/lps22df.c | 0 drivers/sensor/{ => st}/lps2xdf/lps22df.h | 0 drivers/sensor/{ => st}/lps2xdf/lps28dfw.c | 0 drivers/sensor/{ => st}/lps2xdf/lps28dfw.h | 0 drivers/sensor/{ => st}/lps2xdf/lps2xdf.c | 0 drivers/sensor/{ => st}/lps2xdf/lps2xdf.h | 0 .../sensor/{ => st}/lps2xdf/lps2xdf_trigger.c | 0 .../{ => st}/lsm303dlhc_magn/CMakeLists.txt | 0 .../sensor/{ => st}/lsm303dlhc_magn/Kconfig | 0 .../lsm303dlhc_magn/lsm303dlhc_magn.c | 0 .../lsm303dlhc_magn/lsm303dlhc_magn.h | 0 .../sensor/{ => st}/lsm6ds0/CMakeLists.txt | 0 drivers/sensor/{ => st}/lsm6ds0/Kconfig | 0 drivers/sensor/{ => st}/lsm6ds0/lsm6ds0.c | 0 drivers/sensor/{ => st}/lsm6ds0/lsm6ds0.h | 0 .../sensor/{ => st}/lsm6dsl/CMakeLists.txt | 0 drivers/sensor/{ => st}/lsm6dsl/Kconfig | 0 drivers/sensor/{ => st}/lsm6dsl/lsm6dsl.c | 0 drivers/sensor/{ => st}/lsm6dsl/lsm6dsl.h | 0 drivers/sensor/{ => st}/lsm6dsl/lsm6dsl_i2c.c | 0 .../sensor/{ => st}/lsm6dsl/lsm6dsl_shub.c | 0 drivers/sensor/{ => st}/lsm6dsl/lsm6dsl_spi.c | 0 .../sensor/{ => st}/lsm6dsl/lsm6dsl_trigger.c | 0 .../sensor/{ => st}/lsm6dso/CMakeLists.txt | 0 drivers/sensor/{ => st}/lsm6dso/Kconfig | 0 drivers/sensor/{ => st}/lsm6dso/lsm6dso.c | 0 drivers/sensor/{ => st}/lsm6dso/lsm6dso.h | 0 .../sensor/{ => st}/lsm6dso/lsm6dso_shub.c | 0 .../sensor/{ => st}/lsm6dso/lsm6dso_trigger.c | 0 .../{ => st}/lsm6dso16is/CMakeLists.txt | 0 drivers/sensor/{ => st}/lsm6dso16is/Kconfig | 0 .../sensor/{ => st}/lsm6dso16is/lsm6dso16is.c | 0 .../sensor/{ => st}/lsm6dso16is/lsm6dso16is.h | 0 .../{ => st}/lsm6dso16is/lsm6dso16is_shub.c | 0 .../lsm6dso16is/lsm6dso16is_trigger.c | 0 .../sensor/{ => st}/lsm6dsv16x/CMakeLists.txt | 0 drivers/sensor/{ => st}/lsm6dsv16x/Kconfig | 0 .../sensor/{ => st}/lsm6dsv16x/lsm6dsv16x.c | 0 .../sensor/{ => st}/lsm6dsv16x/lsm6dsv16x.h | 0 .../{ => st}/lsm6dsv16x/lsm6dsv16x_shub.c | 0 .../{ => st}/lsm6dsv16x/lsm6dsv16x_trigger.c | 0 .../{ => st}/lsm9ds0_gyro/CMakeLists.txt | 0 drivers/sensor/{ => st}/lsm9ds0_gyro/Kconfig | 0 .../{ => st}/lsm9ds0_gyro/lsm9ds0_gyro.c | 0 .../{ => st}/lsm9ds0_gyro/lsm9ds0_gyro.h | 0 .../lsm9ds0_gyro/lsm9ds0_gyro_trigger.c | 0 .../{ => st}/lsm9ds0_mfd/CMakeLists.txt | 0 drivers/sensor/{ => st}/lsm9ds0_mfd/Kconfig | 0 .../sensor/{ => st}/lsm9ds0_mfd/lsm9ds0_mfd.c | 0 .../sensor/{ => st}/lsm9ds0_mfd/lsm9ds0_mfd.h | 0 .../sensor/{ => st}/qdec_stm32/CMakeLists.txt | 0 drivers/sensor/{ => st}/qdec_stm32/Kconfig | 0 .../sensor/{ => st}/qdec_stm32/qdec_stm32.c | 0 .../sensor/{ => st}/stm32_temp/CMakeLists.txt | 0 drivers/sensor/{ => st}/stm32_temp/Kconfig | 0 .../sensor/{ => st}/stm32_temp/stm32_temp.c | 0 .../sensor/{ => st}/stm32_vbat/CMakeLists.txt | 0 drivers/sensor/{ => st}/stm32_vbat/Kconfig | 0 .../sensor/{ => st}/stm32_vbat/stm32_vbat.c | 0 .../sensor/{ => st}/stm32_vref/CMakeLists.txt | 0 drivers/sensor/{ => st}/stm32_vref/Kconfig | 0 .../sensor/{ => st}/stm32_vref/stm32_vref.c | 0 .../sensor/{ => st}/stmemsc/CMakeLists.txt | 0 drivers/sensor/{ => st}/stmemsc/stmemsc.h | 0 drivers/sensor/{ => st}/stmemsc/stmemsc_i2c.c | 0 drivers/sensor/{ => st}/stmemsc/stmemsc_i3c.c | 0 .../sensor/{ => st}/stmemsc/stmemsc_mdelay.c | 0 drivers/sensor/{ => st}/stmemsc/stmemsc_spi.c | 0 .../sensor/{ => st}/stts22h/CMakeLists.txt | 0 drivers/sensor/{ => st}/stts22h/Kconfig | 0 drivers/sensor/{ => st}/stts22h/stts22h.c | 0 drivers/sensor/{ => st}/stts22h/stts22h.h | 0 .../sensor/{ => st}/stts22h/stts22h_trigger.c | 0 .../sensor/{ => st}/stts751/CMakeLists.txt | 0 drivers/sensor/{ => st}/stts751/Kconfig | 0 drivers/sensor/{ => st}/stts751/stts751.c | 0 drivers/sensor/{ => st}/stts751/stts751.h | 0 drivers/sensor/{ => st}/stts751/stts751_i2c.c | 0 .../sensor/{ => st}/stts751/stts751_trigger.c | 0 .../sensor/{ => st}/vl53l0x/CMakeLists.txt | 0 drivers/sensor/{ => st}/vl53l0x/Kconfig | 0 drivers/sensor/{ => st}/vl53l0x/vl53l0x.c | 0 .../{ => st}/vl53l0x/vl53l0x_platform.c | 0 .../{ => st}/vl53l0x/vl53l0x_platform.h | 0 .../{ => st}/vl53l0x/vl53l0x_platform_log.h | 0 .../sensor/{ => st}/vl53l0x/vl53l0x_types.h | 0 .../sensor/{ => st}/vl53l1x/CMakeLists.txt | 0 drivers/sensor/{ => st}/vl53l1x/Kconfig | 0 drivers/sensor/{ => st}/vl53l1x/vl53l1.c | 0 .../sensor/{ => st}/vl53l1x/vl53l1_platform.c | 0 .../sensor/{ => st}/vl53l1x/vl53l1_platform.h | 0 .../{ => st}/vl53l1x/vl53l1_platform_log.h | 0 .../vl53l1x/vl53l1_platform_user_config.h | 0 .../vl53l1x/vl53l1_platform_user_data.h | 0 .../vl53l1x/vl53l1_platform_user_defines.h | 0 .../sensor/{ => st}/vl53l1x/vl53l1_types.h | 0 west.yml | 2 +- 212 files changed, 88 insertions(+), 76 deletions(-) create mode 100644 drivers/sensor/st/CMakeLists.txt create mode 100644 drivers/sensor/st/Kconfig rename drivers/sensor/{ => st}/hts221/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/hts221/Kconfig (100%) rename drivers/sensor/{ => st}/hts221/hts221.c (100%) rename drivers/sensor/{ => st}/hts221/hts221.h (100%) rename drivers/sensor/{ => st}/hts221/hts221_trigger.c (100%) rename drivers/sensor/{ => st}/i3g4250d/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/i3g4250d/Kconfig (100%) rename drivers/sensor/{ => st}/i3g4250d/i3g4250d.c (100%) rename drivers/sensor/{ => st}/i3g4250d/i3g4250d.h (100%) rename drivers/sensor/{ => st}/i3g4250d/i3g4250d_spi.c (100%) rename drivers/sensor/{ => st}/iis2dh/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/iis2dh/Kconfig (100%) rename drivers/sensor/{ => st}/iis2dh/iis2dh.c (100%) rename drivers/sensor/{ => st}/iis2dh/iis2dh.h (100%) rename drivers/sensor/{ => st}/iis2dh/iis2dh_i2c.c (100%) rename drivers/sensor/{ => st}/iis2dh/iis2dh_spi.c (100%) rename drivers/sensor/{ => st}/iis2dh/iis2dh_trigger.c (100%) rename drivers/sensor/{ => st}/iis2dlpc/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/iis2dlpc/Kconfig (100%) rename drivers/sensor/{ => st}/iis2dlpc/iis2dlpc.c (100%) rename drivers/sensor/{ => st}/iis2dlpc/iis2dlpc.h (100%) rename drivers/sensor/{ => st}/iis2dlpc/iis2dlpc_trigger.c (100%) rename drivers/sensor/{ => st}/iis2iclx/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/iis2iclx/Kconfig (100%) rename drivers/sensor/{ => st}/iis2iclx/iis2iclx.c (100%) rename drivers/sensor/{ => st}/iis2iclx/iis2iclx.h (100%) rename drivers/sensor/{ => st}/iis2iclx/iis2iclx_shub.c (100%) rename drivers/sensor/{ => st}/iis2iclx/iis2iclx_trigger.c (100%) rename drivers/sensor/{ => st}/iis2mdc/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/iis2mdc/Kconfig (100%) rename drivers/sensor/{ => st}/iis2mdc/iis2mdc.c (100%) rename drivers/sensor/{ => st}/iis2mdc/iis2mdc.h (100%) rename drivers/sensor/{ => st}/iis2mdc/iis2mdc_i2c.c (100%) rename drivers/sensor/{ => st}/iis2mdc/iis2mdc_spi.c (100%) rename drivers/sensor/{ => st}/iis2mdc/iis2mdc_trigger.c (100%) rename drivers/sensor/{ => st}/iis328dq/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/iis328dq/Kconfig (100%) rename drivers/sensor/{ => st}/iis328dq/iis328dq.c (100%) rename drivers/sensor/{ => st}/iis328dq/iis328dq.h (100%) rename drivers/sensor/{ => st}/iis328dq/iis328dq_trigger.c (100%) rename drivers/sensor/{ => st}/iis3dhhc/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/iis3dhhc/Kconfig (100%) rename drivers/sensor/{ => st}/iis3dhhc/iis3dhhc.c (100%) rename drivers/sensor/{ => st}/iis3dhhc/iis3dhhc.h (100%) rename drivers/sensor/{ => st}/iis3dhhc/iis3dhhc_spi.c (100%) rename drivers/sensor/{ => st}/iis3dhhc/iis3dhhc_trigger.c (100%) rename drivers/sensor/{ => st}/ism330dhcx/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/ism330dhcx/Kconfig (100%) rename drivers/sensor/{ => st}/ism330dhcx/ism330dhcx.c (100%) rename drivers/sensor/{ => st}/ism330dhcx/ism330dhcx.h (100%) rename drivers/sensor/{ => st}/ism330dhcx/ism330dhcx_i2c.c (100%) rename drivers/sensor/{ => st}/ism330dhcx/ism330dhcx_shub.c (100%) rename drivers/sensor/{ => st}/ism330dhcx/ism330dhcx_spi.c (100%) rename drivers/sensor/{ => st}/ism330dhcx/ism330dhcx_trigger.c (100%) rename drivers/sensor/{ => st}/lis2de12/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lis2de12/Kconfig (100%) rename drivers/sensor/{ => st}/lis2de12/lis2de12.c (100%) rename drivers/sensor/{ => st}/lis2de12/lis2de12.h (100%) rename drivers/sensor/{ => st}/lis2de12/lis2de12_trigger.c (100%) rename drivers/sensor/{ => st}/lis2dh/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lis2dh/Kconfig (100%) rename drivers/sensor/{ => st}/lis2dh/lis2dh.c (100%) rename drivers/sensor/{ => st}/lis2dh/lis2dh.h (100%) rename drivers/sensor/{ => st}/lis2dh/lis2dh_i2c.c (100%) rename drivers/sensor/{ => st}/lis2dh/lis2dh_spi.c (100%) rename drivers/sensor/{ => st}/lis2dh/lis2dh_trigger.c (100%) rename drivers/sensor/{ => st}/lis2ds12/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lis2ds12/Kconfig (100%) rename drivers/sensor/{ => st}/lis2ds12/lis2ds12.c (100%) rename drivers/sensor/{ => st}/lis2ds12/lis2ds12.h (100%) rename drivers/sensor/{ => st}/lis2ds12/lis2ds12_trigger.c (100%) rename drivers/sensor/{ => st}/lis2du12/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lis2du12/Kconfig (100%) rename drivers/sensor/{ => st}/lis2du12/lis2du12.c (100%) rename drivers/sensor/{ => st}/lis2du12/lis2du12.h (100%) rename drivers/sensor/{ => st}/lis2du12/lis2du12_trigger.c (100%) rename drivers/sensor/{ => st}/lis2dux12/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lis2dux12/Kconfig (100%) rename drivers/sensor/{ => st}/lis2dux12/lis2dux12.c (100%) rename drivers/sensor/{ => st}/lis2dux12/lis2dux12.h (100%) rename drivers/sensor/{ => st}/lis2dux12/lis2dux12_trigger.c (100%) rename drivers/sensor/{ => st}/lis2dw12/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lis2dw12/Kconfig (100%) rename drivers/sensor/{ => st}/lis2dw12/lis2dw12.c (100%) rename drivers/sensor/{ => st}/lis2dw12/lis2dw12.h (100%) rename drivers/sensor/{ => st}/lis2dw12/lis2dw12_trigger.c (100%) rename drivers/sensor/{ => st}/lis2mdl/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lis2mdl/Kconfig (100%) rename drivers/sensor/{ => st}/lis2mdl/lis2mdl.c (100%) rename drivers/sensor/{ => st}/lis2mdl/lis2mdl.h (100%) rename drivers/sensor/{ => st}/lis2mdl/lis2mdl_trigger.c (100%) rename drivers/sensor/{ => st}/lis3mdl/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lis3mdl/Kconfig (100%) rename drivers/sensor/{ => st}/lis3mdl/lis3mdl.c (100%) rename drivers/sensor/{ => st}/lis3mdl/lis3mdl.h (100%) rename drivers/sensor/{ => st}/lis3mdl/lis3mdl_trigger.c (100%) rename drivers/sensor/{ => st}/lps22hb/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lps22hb/Kconfig (100%) rename drivers/sensor/{ => st}/lps22hb/lps22hb.c (100%) rename drivers/sensor/{ => st}/lps22hb/lps22hb.h (100%) rename drivers/sensor/{ => st}/lps22hh/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lps22hh/Kconfig (100%) rename drivers/sensor/{ => st}/lps22hh/lps22hh.c (100%) rename drivers/sensor/{ => st}/lps22hh/lps22hh.h (100%) rename drivers/sensor/{ => st}/lps22hh/lps22hh_trigger.c (100%) rename drivers/sensor/{ => st}/lps25hb/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lps25hb/Kconfig (100%) rename drivers/sensor/{ => st}/lps25hb/lps25hb.c (100%) rename drivers/sensor/{ => st}/lps25hb/lps25hb.h (100%) rename drivers/sensor/{ => st}/lps2xdf/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lps2xdf/Kconfig (100%) rename drivers/sensor/{ => st}/lps2xdf/lps22df.c (100%) rename drivers/sensor/{ => st}/lps2xdf/lps22df.h (100%) rename drivers/sensor/{ => st}/lps2xdf/lps28dfw.c (100%) rename drivers/sensor/{ => st}/lps2xdf/lps28dfw.h (100%) rename drivers/sensor/{ => st}/lps2xdf/lps2xdf.c (100%) rename drivers/sensor/{ => st}/lps2xdf/lps2xdf.h (100%) rename drivers/sensor/{ => st}/lps2xdf/lps2xdf_trigger.c (100%) rename drivers/sensor/{ => st}/lsm303dlhc_magn/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lsm303dlhc_magn/Kconfig (100%) rename drivers/sensor/{ => st}/lsm303dlhc_magn/lsm303dlhc_magn.c (100%) rename drivers/sensor/{ => st}/lsm303dlhc_magn/lsm303dlhc_magn.h (100%) rename drivers/sensor/{ => st}/lsm6ds0/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lsm6ds0/Kconfig (100%) rename drivers/sensor/{ => st}/lsm6ds0/lsm6ds0.c (100%) rename drivers/sensor/{ => st}/lsm6ds0/lsm6ds0.h (100%) rename drivers/sensor/{ => st}/lsm6dsl/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lsm6dsl/Kconfig (100%) rename drivers/sensor/{ => st}/lsm6dsl/lsm6dsl.c (100%) rename drivers/sensor/{ => st}/lsm6dsl/lsm6dsl.h (100%) rename drivers/sensor/{ => st}/lsm6dsl/lsm6dsl_i2c.c (100%) rename drivers/sensor/{ => st}/lsm6dsl/lsm6dsl_shub.c (100%) rename drivers/sensor/{ => st}/lsm6dsl/lsm6dsl_spi.c (100%) rename drivers/sensor/{ => st}/lsm6dsl/lsm6dsl_trigger.c (100%) rename drivers/sensor/{ => st}/lsm6dso/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lsm6dso/Kconfig (100%) rename drivers/sensor/{ => st}/lsm6dso/lsm6dso.c (100%) rename drivers/sensor/{ => st}/lsm6dso/lsm6dso.h (100%) rename drivers/sensor/{ => st}/lsm6dso/lsm6dso_shub.c (100%) rename drivers/sensor/{ => st}/lsm6dso/lsm6dso_trigger.c (100%) rename drivers/sensor/{ => st}/lsm6dso16is/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lsm6dso16is/Kconfig (100%) rename drivers/sensor/{ => st}/lsm6dso16is/lsm6dso16is.c (100%) rename drivers/sensor/{ => st}/lsm6dso16is/lsm6dso16is.h (100%) rename drivers/sensor/{ => st}/lsm6dso16is/lsm6dso16is_shub.c (100%) rename drivers/sensor/{ => st}/lsm6dso16is/lsm6dso16is_trigger.c (100%) rename drivers/sensor/{ => st}/lsm6dsv16x/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lsm6dsv16x/Kconfig (100%) rename drivers/sensor/{ => st}/lsm6dsv16x/lsm6dsv16x.c (100%) rename drivers/sensor/{ => st}/lsm6dsv16x/lsm6dsv16x.h (100%) rename drivers/sensor/{ => st}/lsm6dsv16x/lsm6dsv16x_shub.c (100%) rename drivers/sensor/{ => st}/lsm6dsv16x/lsm6dsv16x_trigger.c (100%) rename drivers/sensor/{ => st}/lsm9ds0_gyro/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lsm9ds0_gyro/Kconfig (100%) rename drivers/sensor/{ => st}/lsm9ds0_gyro/lsm9ds0_gyro.c (100%) rename drivers/sensor/{ => st}/lsm9ds0_gyro/lsm9ds0_gyro.h (100%) rename drivers/sensor/{ => st}/lsm9ds0_gyro/lsm9ds0_gyro_trigger.c (100%) rename drivers/sensor/{ => st}/lsm9ds0_mfd/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/lsm9ds0_mfd/Kconfig (100%) rename drivers/sensor/{ => st}/lsm9ds0_mfd/lsm9ds0_mfd.c (100%) rename drivers/sensor/{ => st}/lsm9ds0_mfd/lsm9ds0_mfd.h (100%) rename drivers/sensor/{ => st}/qdec_stm32/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/qdec_stm32/Kconfig (100%) rename drivers/sensor/{ => st}/qdec_stm32/qdec_stm32.c (100%) rename drivers/sensor/{ => st}/stm32_temp/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/stm32_temp/Kconfig (100%) rename drivers/sensor/{ => st}/stm32_temp/stm32_temp.c (100%) rename drivers/sensor/{ => st}/stm32_vbat/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/stm32_vbat/Kconfig (100%) rename drivers/sensor/{ => st}/stm32_vbat/stm32_vbat.c (100%) rename drivers/sensor/{ => st}/stm32_vref/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/stm32_vref/Kconfig (100%) rename drivers/sensor/{ => st}/stm32_vref/stm32_vref.c (100%) rename drivers/sensor/{ => st}/stmemsc/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/stmemsc/stmemsc.h (100%) rename drivers/sensor/{ => st}/stmemsc/stmemsc_i2c.c (100%) rename drivers/sensor/{ => st}/stmemsc/stmemsc_i3c.c (100%) rename drivers/sensor/{ => st}/stmemsc/stmemsc_mdelay.c (100%) rename drivers/sensor/{ => st}/stmemsc/stmemsc_spi.c (100%) rename drivers/sensor/{ => st}/stts22h/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/stts22h/Kconfig (100%) rename drivers/sensor/{ => st}/stts22h/stts22h.c (100%) rename drivers/sensor/{ => st}/stts22h/stts22h.h (100%) rename drivers/sensor/{ => st}/stts22h/stts22h_trigger.c (100%) rename drivers/sensor/{ => st}/stts751/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/stts751/Kconfig (100%) rename drivers/sensor/{ => st}/stts751/stts751.c (100%) rename drivers/sensor/{ => st}/stts751/stts751.h (100%) rename drivers/sensor/{ => st}/stts751/stts751_i2c.c (100%) rename drivers/sensor/{ => st}/stts751/stts751_trigger.c (100%) rename drivers/sensor/{ => st}/vl53l0x/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/vl53l0x/Kconfig (100%) rename drivers/sensor/{ => st}/vl53l0x/vl53l0x.c (100%) rename drivers/sensor/{ => st}/vl53l0x/vl53l0x_platform.c (100%) rename drivers/sensor/{ => st}/vl53l0x/vl53l0x_platform.h (100%) rename drivers/sensor/{ => st}/vl53l0x/vl53l0x_platform_log.h (100%) rename drivers/sensor/{ => st}/vl53l0x/vl53l0x_types.h (100%) rename drivers/sensor/{ => st}/vl53l1x/CMakeLists.txt (100%) rename drivers/sensor/{ => st}/vl53l1x/Kconfig (100%) rename drivers/sensor/{ => st}/vl53l1x/vl53l1.c (100%) rename drivers/sensor/{ => st}/vl53l1x/vl53l1_platform.c (100%) rename drivers/sensor/{ => st}/vl53l1x/vl53l1_platform.h (100%) rename drivers/sensor/{ => st}/vl53l1x/vl53l1_platform_log.h (100%) rename drivers/sensor/{ => st}/vl53l1x/vl53l1_platform_user_config.h (100%) rename drivers/sensor/{ => st}/vl53l1x/vl53l1_platform_user_data.h (100%) rename drivers/sensor/{ => st}/vl53l1x/vl53l1_platform_user_defines.h (100%) rename drivers/sensor/{ => st}/vl53l1x/vl53l1_types.h (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index e5dba6e5ad7..4dfef2e3f88 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -3,6 +3,7 @@ # zephyr-keep-sorted-start add_subdirectory(adi) add_subdirectory(bosch) +add_subdirectory(st) # zephyr-keep-sorted-stop add_subdirectory_ifdef(CONFIG_A01NYUB a01nyub) @@ -35,53 +36,23 @@ add_subdirectory_ifdef(CONFIG_FXAS21002 fxas21002) add_subdirectory_ifdef(CONFIG_FXOS8700 fxos8700) add_subdirectory_ifdef(CONFIG_GROVE_SENSORS grove) add_subdirectory_ifdef(CONFIG_GROW_R502A grow_r502a) -add_subdirectory_ifdef(CONFIG_HAS_STMEMSC stmemsc) add_subdirectory_ifdef(CONFIG_HM330X hm330x) add_subdirectory_ifdef(CONFIG_HMC5883L hmc5883l) add_subdirectory_ifdef(CONFIG_HP206C hp206c) add_subdirectory_ifdef(CONFIG_HS300X hs300x) -add_subdirectory_ifdef(CONFIG_HTS221 hts221) -add_subdirectory_ifdef(CONFIG_I3G4250D i3g4250d) add_subdirectory_ifdef(CONFIG_ICM42605 tdk/icm42605) add_subdirectory_ifdef(CONFIG_ICM42670 tdk/icm42670) add_subdirectory_ifdef(CONFIG_ICM42688 tdk/icm42688) add_subdirectory_ifdef(CONFIG_ICP10125 tdk/icp10125) -add_subdirectory_ifdef(CONFIG_IIS2DH iis2dh) -add_subdirectory_ifdef(CONFIG_IIS2DLPC iis2dlpc) -add_subdirectory_ifdef(CONFIG_IIS2ICLX iis2iclx) -add_subdirectory_ifdef(CONFIG_IIS2MDC iis2mdc) -add_subdirectory_ifdef(CONFIG_IIS3DHHC iis3dhhc) -add_subdirectory_ifdef(CONFIG_IIS328DQ iis328dq) add_subdirectory_ifdef(CONFIG_INA219 ina219) add_subdirectory_ifdef(CONFIG_INA23X ina23x) add_subdirectory_ifdef(CONFIG_INA3221 ina3221) add_subdirectory_ifdef(CONFIG_IST8310 ist8310) add_subdirectory_ifdef(CONFIG_ISL29035 isl29035) -add_subdirectory_ifdef(CONFIG_ISM330DHCX ism330dhcx) add_subdirectory_ifdef(CONFIG_ITDS wsen_itds) -add_subdirectory_ifdef(CONFIG_LIS2DH lis2dh) -add_subdirectory_ifdef(CONFIG_LIS2DE12 lis2de12) -add_subdirectory_ifdef(CONFIG_LIS2DS12 lis2ds12) -add_subdirectory_ifdef(CONFIG_LIS2DU12 lis2du12) -add_subdirectory_ifdef(CONFIG_LIS2DUX12 lis2dux12) -add_subdirectory_ifdef(CONFIG_LIS2DW12 lis2dw12) -add_subdirectory_ifdef(CONFIG_LIS2MDL lis2mdl) -add_subdirectory_ifdef(CONFIG_LIS3MDL lis3mdl) add_subdirectory_ifdef(CONFIG_LM35 lm35) add_subdirectory_ifdef(CONFIG_LM75 lm75) add_subdirectory_ifdef(CONFIG_LM77 lm77) -add_subdirectory_ifdef(CONFIG_LPS2XDF lps2xdf) -add_subdirectory_ifdef(CONFIG_LPS22HB lps22hb) -add_subdirectory_ifdef(CONFIG_LPS22HH lps22hh) -add_subdirectory_ifdef(CONFIG_LPS25HB lps25hb) -add_subdirectory_ifdef(CONFIG_LSM303DLHC_MAGN lsm303dlhc_magn) -add_subdirectory_ifdef(CONFIG_LSM6DS0 lsm6ds0) -add_subdirectory_ifdef(CONFIG_LSM6DSL lsm6dsl) -add_subdirectory_ifdef(CONFIG_LSM6DSO lsm6dso) -add_subdirectory_ifdef(CONFIG_LSM6DSO16IS lsm6dso16is) -add_subdirectory_ifdef(CONFIG_LSM6DSV16X lsm6dsv16x) -add_subdirectory_ifdef(CONFIG_LSM9DS0_GYRO lsm9ds0_gyro) -add_subdirectory_ifdef(CONFIG_LSM9DS0_MFD lsm9ds0_mfd) add_subdirectory_ifdef(CONFIG_LTR_F216A ltrf216a) add_subdirectory_ifdef(CONFIG_MAX17055 max17055) add_subdirectory_ifdef(CONFIG_MAX17262 max17262) @@ -113,7 +84,6 @@ add_subdirectory_ifdef(CONFIG_QDEC_MCUX qdec_mcux) add_subdirectory_ifdef(CONFIG_QDEC_NXP_S32 qdec_nxp_s32) add_subdirectory_ifdef(CONFIG_QDEC_NRFX qdec_nrfx) add_subdirectory_ifdef(CONFIG_QDEC_SAM qdec_sam) -add_subdirectory_ifdef(CONFIG_QDEC_STM32 qdec_stm32) add_subdirectory_ifdef(CONFIG_RPI_PICO_TEMP rpi_pico_temp) add_subdirectory_ifdef(CONFIG_S11059 s11059) add_subdirectory_ifdef(CONFIG_SBS_GAUGE sbs_gauge) @@ -126,11 +96,6 @@ add_subdirectory_ifdef(CONFIG_SI7055 si7055) add_subdirectory_ifdef(CONFIG_SI7060 si7060) add_subdirectory_ifdef(CONFIG_SI7210 si7210) add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) -add_subdirectory_ifdef(CONFIG_STM32_TEMP stm32_temp) -add_subdirectory_ifdef(CONFIG_STM32_VBAT stm32_vbat) -add_subdirectory_ifdef(CONFIG_STM32_VREF stm32_vref) -add_subdirectory_ifdef(CONFIG_STTS22H stts22h) -add_subdirectory_ifdef(CONFIG_STTS751 stts751) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) add_subdirectory_ifdef(CONFIG_TACH_IT8XXX2 ite_tach_it8xxx2) add_subdirectory_ifdef(CONFIG_TACH_NPCX nuvoton_tach_npcx) @@ -156,8 +121,6 @@ add_subdirectory_ifdef(CONFIG_VCMP_IT8XXX2 ite_vcmp_it8xxx2) add_subdirectory_ifdef(CONFIG_VCNL4040 vcnl4040) add_subdirectory_ifdef(CONFIG_VCNL36825T vcnl36825t) add_subdirectory_ifdef(CONFIG_VEML7700 veml7700) -add_subdirectory_ifdef(CONFIG_VL53L0X vl53l0x) -add_subdirectory_ifdef(CONFIG_VL53L1X vl53l1x) add_subdirectory_ifdef(CONFIG_VOLTAGE_DIVIDER voltage_divider) add_subdirectory_ifdef(CONFIG_WSEN_HIDS wsen_hids) add_subdirectory_ifdef(CONFIG_WSEN_PADS wsen_pads) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 7627a36ed0c..6f26aafe8ff 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -84,6 +84,7 @@ comment "Device Drivers" # zephyr-keep-sorted-start source "drivers/sensor/adi/Kconfig" source "drivers/sensor/bosch/Kconfig" +source "drivers/sensor/st/Kconfig" # zephyr-keep-sorted-stop source "drivers/sensor/a01nyub/Kconfig" @@ -119,49 +120,20 @@ source "drivers/sensor/hm330x/Kconfig" source "drivers/sensor/hmc5883l/Kconfig" source "drivers/sensor/hp206c/Kconfig" source "drivers/sensor/hs300x/Kconfig" -source "drivers/sensor/hts221/Kconfig" -source "drivers/sensor/i3g4250d/Kconfig" source "drivers/sensor/tdk/icm42605/Kconfig" source "drivers/sensor/tdk/icm42670/Kconfig" source "drivers/sensor/tdk/icm42688/Kconfig" source "drivers/sensor/tdk/icp10125/Kconfig" -source "drivers/sensor/iis2dh/Kconfig" -source "drivers/sensor/iis2dlpc/Kconfig" -source "drivers/sensor/iis2iclx/Kconfig" -source "drivers/sensor/iis2mdc/Kconfig" -source "drivers/sensor/iis3dhhc/Kconfig" -source "drivers/sensor/iis328dq/Kconfig" source "drivers/sensor/ina219/Kconfig" source "drivers/sensor/ina23x/Kconfig" source "drivers/sensor/ina3221/Kconfig" source "drivers/sensor/isl29035/Kconfig" source "drivers/sensor/ist8310/Kconfig" -source "drivers/sensor/ism330dhcx/Kconfig" source "drivers/sensor/ite_tach_it8xxx2/Kconfig" source "drivers/sensor/ite_vcmp_it8xxx2/Kconfig" -source "drivers/sensor/lis2dh/Kconfig" -source "drivers/sensor/lis2de12/Kconfig" -source "drivers/sensor/lis2ds12/Kconfig" -source "drivers/sensor/lis2du12/Kconfig" -source "drivers/sensor/lis2dux12/Kconfig" -source "drivers/sensor/lis2dw12/Kconfig" -source "drivers/sensor/lis2mdl/Kconfig" -source "drivers/sensor/lis3mdl/Kconfig" source "drivers/sensor/lm35/Kconfig" source "drivers/sensor/lm75/Kconfig" source "drivers/sensor/lm77/Kconfig" -source "drivers/sensor/lps2xdf/Kconfig" -source "drivers/sensor/lps22hb/Kconfig" -source "drivers/sensor/lps22hh/Kconfig" -source "drivers/sensor/lps25hb/Kconfig" -source "drivers/sensor/lsm303dlhc_magn/Kconfig" -source "drivers/sensor/lsm6ds0/Kconfig" -source "drivers/sensor/lsm6dsl/Kconfig" -source "drivers/sensor/lsm6dso/Kconfig" -source "drivers/sensor/lsm6dso16is/Kconfig" -source "drivers/sensor/lsm6dsv16x/Kconfig" -source "drivers/sensor/lsm9ds0_gyro/Kconfig" -source "drivers/sensor/lsm9ds0_mfd/Kconfig" source "drivers/sensor/ltrf216a/Kconfig" source "drivers/sensor/max17055/Kconfig" source "drivers/sensor/max17262/Kconfig" @@ -198,7 +170,6 @@ source "drivers/sensor/qdec_mcux/Kconfig" source "drivers/sensor/qdec_nxp_s32/Kconfig" source "drivers/sensor/qdec_nrfx/Kconfig" source "drivers/sensor/qdec_sam/Kconfig" -source "drivers/sensor/qdec_stm32/Kconfig" source "drivers/sensor/rpi_pico_temp/Kconfig" source "drivers/sensor/s11059/Kconfig" source "drivers/sensor/sbs_gauge/Kconfig" @@ -211,11 +182,6 @@ source "drivers/sensor/si7055/Kconfig" source "drivers/sensor/si7060/Kconfig" source "drivers/sensor/si7210/Kconfig" source "drivers/sensor/sm351lt/Kconfig" -source "drivers/sensor/stm32_temp/Kconfig" -source "drivers/sensor/stm32_vbat/Kconfig" -source "drivers/sensor/stm32_vref/Kconfig" -source "drivers/sensor/stts22h/Kconfig" -source "drivers/sensor/stts751/Kconfig" source "drivers/sensor/sx9500/Kconfig" source "drivers/sensor/tcn75a/Kconfig" source "drivers/sensor/tcs3400/Kconfig" @@ -235,8 +201,6 @@ source "drivers/sensor/tsl2591/Kconfig" source "drivers/sensor/vcnl4040/Kconfig" source "drivers/sensor/vcnl36825t/Kconfig" source "drivers/sensor/veml7700/Kconfig" -source "drivers/sensor/vl53l0x/Kconfig" -source "drivers/sensor/vl53l1x/Kconfig" source "drivers/sensor/voltage_divider/Kconfig" source "drivers/sensor/wsen_hids/Kconfig" source "drivers/sensor/wsen_itds/Kconfig" diff --git a/drivers/sensor/st/CMakeLists.txt b/drivers/sensor/st/CMakeLists.txt new file mode 100644 index 00000000000..31b191490b5 --- /dev/null +++ b/drivers/sensor/st/CMakeLists.txt @@ -0,0 +1,43 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_HAS_STMEMSC stmemsc) +add_subdirectory_ifdef(CONFIG_HTS221 hts221) +add_subdirectory_ifdef(CONFIG_I3G4250D i3g4250d) +add_subdirectory_ifdef(CONFIG_IIS2DH iis2dh) +add_subdirectory_ifdef(CONFIG_IIS2DLPC iis2dlpc) +add_subdirectory_ifdef(CONFIG_IIS2ICLX iis2iclx) +add_subdirectory_ifdef(CONFIG_IIS2MDC iis2mdc) +add_subdirectory_ifdef(CONFIG_IIS328DQ iis328dq) +add_subdirectory_ifdef(CONFIG_IIS3DHHC iis3dhhc) +add_subdirectory_ifdef(CONFIG_ISM330DHCX ism330dhcx) +add_subdirectory_ifdef(CONFIG_LIS2DE12 lis2de12) +add_subdirectory_ifdef(CONFIG_LIS2DH lis2dh) +add_subdirectory_ifdef(CONFIG_LIS2DS12 lis2ds12) +add_subdirectory_ifdef(CONFIG_LIS2DU12 lis2du12) +add_subdirectory_ifdef(CONFIG_LIS2DUX12 lis2dux12) +add_subdirectory_ifdef(CONFIG_LIS2DW12 lis2dw12) +add_subdirectory_ifdef(CONFIG_LIS2MDL lis2mdl) +add_subdirectory_ifdef(CONFIG_LIS3MDL lis3mdl) +add_subdirectory_ifdef(CONFIG_LPS22HB lps22hb) +add_subdirectory_ifdef(CONFIG_LPS22HH lps22hh) +add_subdirectory_ifdef(CONFIG_LPS25HB lps25hb) +add_subdirectory_ifdef(CONFIG_LPS2XDF lps2xdf) +add_subdirectory_ifdef(CONFIG_LSM303DLHC_MAGN lsm303dlhc_magn) +add_subdirectory_ifdef(CONFIG_LSM6DS0 lsm6ds0) +add_subdirectory_ifdef(CONFIG_LSM6DSL lsm6dsl) +add_subdirectory_ifdef(CONFIG_LSM6DSO lsm6dso) +add_subdirectory_ifdef(CONFIG_LSM6DSO16IS lsm6dso16is) +add_subdirectory_ifdef(CONFIG_LSM6DSV16X lsm6dsv16x) +add_subdirectory_ifdef(CONFIG_LSM9DS0_GYRO lsm9ds0_gyro) +add_subdirectory_ifdef(CONFIG_LSM9DS0_MFD lsm9ds0_mfd) +add_subdirectory_ifdef(CONFIG_QDEC_STM32 qdec_stm32) +add_subdirectory_ifdef(CONFIG_STM32_TEMP stm32_temp) +add_subdirectory_ifdef(CONFIG_STM32_VBAT stm32_vbat) +add_subdirectory_ifdef(CONFIG_STM32_VREF stm32_vref) +add_subdirectory_ifdef(CONFIG_STTS22H stts22h) +add_subdirectory_ifdef(CONFIG_STTS751 stts751) +add_subdirectory_ifdef(CONFIG_VL53L0X vl53l0x) +add_subdirectory_ifdef(CONFIG_VL53L1X vl53l1x) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/st/Kconfig b/drivers/sensor/st/Kconfig new file mode 100644 index 00000000000..bb1cbd6b6a0 --- /dev/null +++ b/drivers/sensor/st/Kconfig @@ -0,0 +1,42 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/st/hts221/Kconfig" +source "drivers/sensor/st/i3g4250d/Kconfig" +source "drivers/sensor/st/iis2dh/Kconfig" +source "drivers/sensor/st/iis2dlpc/Kconfig" +source "drivers/sensor/st/iis2iclx/Kconfig" +source "drivers/sensor/st/iis2mdc/Kconfig" +source "drivers/sensor/st/iis328dq/Kconfig" +source "drivers/sensor/st/iis3dhhc/Kconfig" +source "drivers/sensor/st/ism330dhcx/Kconfig" +source "drivers/sensor/st/lis2de12/Kconfig" +source "drivers/sensor/st/lis2dh/Kconfig" +source "drivers/sensor/st/lis2ds12/Kconfig" +source "drivers/sensor/st/lis2du12/Kconfig" +source "drivers/sensor/st/lis2dux12/Kconfig" +source "drivers/sensor/st/lis2dw12/Kconfig" +source "drivers/sensor/st/lis2mdl/Kconfig" +source "drivers/sensor/st/lis3mdl/Kconfig" +source "drivers/sensor/st/lps22hb/Kconfig" +source "drivers/sensor/st/lps22hh/Kconfig" +source "drivers/sensor/st/lps25hb/Kconfig" +source "drivers/sensor/st/lps2xdf/Kconfig" +source "drivers/sensor/st/lsm303dlhc_magn/Kconfig" +source "drivers/sensor/st/lsm6ds0/Kconfig" +source "drivers/sensor/st/lsm6dsl/Kconfig" +source "drivers/sensor/st/lsm6dso/Kconfig" +source "drivers/sensor/st/lsm6dso16is/Kconfig" +source "drivers/sensor/st/lsm6dsv16x/Kconfig" +source "drivers/sensor/st/lsm9ds0_gyro/Kconfig" +source "drivers/sensor/st/lsm9ds0_mfd/Kconfig" +source "drivers/sensor/st/qdec_stm32/Kconfig" +source "drivers/sensor/st/stm32_temp/Kconfig" +source "drivers/sensor/st/stm32_vbat/Kconfig" +source "drivers/sensor/st/stm32_vref/Kconfig" +source "drivers/sensor/st/stts22h/Kconfig" +source "drivers/sensor/st/stts751/Kconfig" +source "drivers/sensor/st/vl53l0x/Kconfig" +source "drivers/sensor/st/vl53l1x/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/hts221/CMakeLists.txt b/drivers/sensor/st/hts221/CMakeLists.txt similarity index 100% rename from drivers/sensor/hts221/CMakeLists.txt rename to drivers/sensor/st/hts221/CMakeLists.txt diff --git a/drivers/sensor/hts221/Kconfig b/drivers/sensor/st/hts221/Kconfig similarity index 100% rename from drivers/sensor/hts221/Kconfig rename to drivers/sensor/st/hts221/Kconfig diff --git a/drivers/sensor/hts221/hts221.c b/drivers/sensor/st/hts221/hts221.c similarity index 100% rename from drivers/sensor/hts221/hts221.c rename to drivers/sensor/st/hts221/hts221.c diff --git a/drivers/sensor/hts221/hts221.h b/drivers/sensor/st/hts221/hts221.h similarity index 100% rename from drivers/sensor/hts221/hts221.h rename to drivers/sensor/st/hts221/hts221.h diff --git a/drivers/sensor/hts221/hts221_trigger.c b/drivers/sensor/st/hts221/hts221_trigger.c similarity index 100% rename from drivers/sensor/hts221/hts221_trigger.c rename to drivers/sensor/st/hts221/hts221_trigger.c diff --git a/drivers/sensor/i3g4250d/CMakeLists.txt b/drivers/sensor/st/i3g4250d/CMakeLists.txt similarity index 100% rename from drivers/sensor/i3g4250d/CMakeLists.txt rename to drivers/sensor/st/i3g4250d/CMakeLists.txt diff --git a/drivers/sensor/i3g4250d/Kconfig b/drivers/sensor/st/i3g4250d/Kconfig similarity index 100% rename from drivers/sensor/i3g4250d/Kconfig rename to drivers/sensor/st/i3g4250d/Kconfig diff --git a/drivers/sensor/i3g4250d/i3g4250d.c b/drivers/sensor/st/i3g4250d/i3g4250d.c similarity index 100% rename from drivers/sensor/i3g4250d/i3g4250d.c rename to drivers/sensor/st/i3g4250d/i3g4250d.c diff --git a/drivers/sensor/i3g4250d/i3g4250d.h b/drivers/sensor/st/i3g4250d/i3g4250d.h similarity index 100% rename from drivers/sensor/i3g4250d/i3g4250d.h rename to drivers/sensor/st/i3g4250d/i3g4250d.h diff --git a/drivers/sensor/i3g4250d/i3g4250d_spi.c b/drivers/sensor/st/i3g4250d/i3g4250d_spi.c similarity index 100% rename from drivers/sensor/i3g4250d/i3g4250d_spi.c rename to drivers/sensor/st/i3g4250d/i3g4250d_spi.c diff --git a/drivers/sensor/iis2dh/CMakeLists.txt b/drivers/sensor/st/iis2dh/CMakeLists.txt similarity index 100% rename from drivers/sensor/iis2dh/CMakeLists.txt rename to drivers/sensor/st/iis2dh/CMakeLists.txt diff --git a/drivers/sensor/iis2dh/Kconfig b/drivers/sensor/st/iis2dh/Kconfig similarity index 100% rename from drivers/sensor/iis2dh/Kconfig rename to drivers/sensor/st/iis2dh/Kconfig diff --git a/drivers/sensor/iis2dh/iis2dh.c b/drivers/sensor/st/iis2dh/iis2dh.c similarity index 100% rename from drivers/sensor/iis2dh/iis2dh.c rename to drivers/sensor/st/iis2dh/iis2dh.c diff --git a/drivers/sensor/iis2dh/iis2dh.h b/drivers/sensor/st/iis2dh/iis2dh.h similarity index 100% rename from drivers/sensor/iis2dh/iis2dh.h rename to drivers/sensor/st/iis2dh/iis2dh.h diff --git a/drivers/sensor/iis2dh/iis2dh_i2c.c b/drivers/sensor/st/iis2dh/iis2dh_i2c.c similarity index 100% rename from drivers/sensor/iis2dh/iis2dh_i2c.c rename to drivers/sensor/st/iis2dh/iis2dh_i2c.c diff --git a/drivers/sensor/iis2dh/iis2dh_spi.c b/drivers/sensor/st/iis2dh/iis2dh_spi.c similarity index 100% rename from drivers/sensor/iis2dh/iis2dh_spi.c rename to drivers/sensor/st/iis2dh/iis2dh_spi.c diff --git a/drivers/sensor/iis2dh/iis2dh_trigger.c b/drivers/sensor/st/iis2dh/iis2dh_trigger.c similarity index 100% rename from drivers/sensor/iis2dh/iis2dh_trigger.c rename to drivers/sensor/st/iis2dh/iis2dh_trigger.c diff --git a/drivers/sensor/iis2dlpc/CMakeLists.txt b/drivers/sensor/st/iis2dlpc/CMakeLists.txt similarity index 100% rename from drivers/sensor/iis2dlpc/CMakeLists.txt rename to drivers/sensor/st/iis2dlpc/CMakeLists.txt diff --git a/drivers/sensor/iis2dlpc/Kconfig b/drivers/sensor/st/iis2dlpc/Kconfig similarity index 100% rename from drivers/sensor/iis2dlpc/Kconfig rename to drivers/sensor/st/iis2dlpc/Kconfig diff --git a/drivers/sensor/iis2dlpc/iis2dlpc.c b/drivers/sensor/st/iis2dlpc/iis2dlpc.c similarity index 100% rename from drivers/sensor/iis2dlpc/iis2dlpc.c rename to drivers/sensor/st/iis2dlpc/iis2dlpc.c diff --git a/drivers/sensor/iis2dlpc/iis2dlpc.h b/drivers/sensor/st/iis2dlpc/iis2dlpc.h similarity index 100% rename from drivers/sensor/iis2dlpc/iis2dlpc.h rename to drivers/sensor/st/iis2dlpc/iis2dlpc.h diff --git a/drivers/sensor/iis2dlpc/iis2dlpc_trigger.c b/drivers/sensor/st/iis2dlpc/iis2dlpc_trigger.c similarity index 100% rename from drivers/sensor/iis2dlpc/iis2dlpc_trigger.c rename to drivers/sensor/st/iis2dlpc/iis2dlpc_trigger.c diff --git a/drivers/sensor/iis2iclx/CMakeLists.txt b/drivers/sensor/st/iis2iclx/CMakeLists.txt similarity index 100% rename from drivers/sensor/iis2iclx/CMakeLists.txt rename to drivers/sensor/st/iis2iclx/CMakeLists.txt diff --git a/drivers/sensor/iis2iclx/Kconfig b/drivers/sensor/st/iis2iclx/Kconfig similarity index 100% rename from drivers/sensor/iis2iclx/Kconfig rename to drivers/sensor/st/iis2iclx/Kconfig diff --git a/drivers/sensor/iis2iclx/iis2iclx.c b/drivers/sensor/st/iis2iclx/iis2iclx.c similarity index 100% rename from drivers/sensor/iis2iclx/iis2iclx.c rename to drivers/sensor/st/iis2iclx/iis2iclx.c diff --git a/drivers/sensor/iis2iclx/iis2iclx.h b/drivers/sensor/st/iis2iclx/iis2iclx.h similarity index 100% rename from drivers/sensor/iis2iclx/iis2iclx.h rename to drivers/sensor/st/iis2iclx/iis2iclx.h diff --git a/drivers/sensor/iis2iclx/iis2iclx_shub.c b/drivers/sensor/st/iis2iclx/iis2iclx_shub.c similarity index 100% rename from drivers/sensor/iis2iclx/iis2iclx_shub.c rename to drivers/sensor/st/iis2iclx/iis2iclx_shub.c diff --git a/drivers/sensor/iis2iclx/iis2iclx_trigger.c b/drivers/sensor/st/iis2iclx/iis2iclx_trigger.c similarity index 100% rename from drivers/sensor/iis2iclx/iis2iclx_trigger.c rename to drivers/sensor/st/iis2iclx/iis2iclx_trigger.c diff --git a/drivers/sensor/iis2mdc/CMakeLists.txt b/drivers/sensor/st/iis2mdc/CMakeLists.txt similarity index 100% rename from drivers/sensor/iis2mdc/CMakeLists.txt rename to drivers/sensor/st/iis2mdc/CMakeLists.txt diff --git a/drivers/sensor/iis2mdc/Kconfig b/drivers/sensor/st/iis2mdc/Kconfig similarity index 100% rename from drivers/sensor/iis2mdc/Kconfig rename to drivers/sensor/st/iis2mdc/Kconfig diff --git a/drivers/sensor/iis2mdc/iis2mdc.c b/drivers/sensor/st/iis2mdc/iis2mdc.c similarity index 100% rename from drivers/sensor/iis2mdc/iis2mdc.c rename to drivers/sensor/st/iis2mdc/iis2mdc.c diff --git a/drivers/sensor/iis2mdc/iis2mdc.h b/drivers/sensor/st/iis2mdc/iis2mdc.h similarity index 100% rename from drivers/sensor/iis2mdc/iis2mdc.h rename to drivers/sensor/st/iis2mdc/iis2mdc.h diff --git a/drivers/sensor/iis2mdc/iis2mdc_i2c.c b/drivers/sensor/st/iis2mdc/iis2mdc_i2c.c similarity index 100% rename from drivers/sensor/iis2mdc/iis2mdc_i2c.c rename to drivers/sensor/st/iis2mdc/iis2mdc_i2c.c diff --git a/drivers/sensor/iis2mdc/iis2mdc_spi.c b/drivers/sensor/st/iis2mdc/iis2mdc_spi.c similarity index 100% rename from drivers/sensor/iis2mdc/iis2mdc_spi.c rename to drivers/sensor/st/iis2mdc/iis2mdc_spi.c diff --git a/drivers/sensor/iis2mdc/iis2mdc_trigger.c b/drivers/sensor/st/iis2mdc/iis2mdc_trigger.c similarity index 100% rename from drivers/sensor/iis2mdc/iis2mdc_trigger.c rename to drivers/sensor/st/iis2mdc/iis2mdc_trigger.c diff --git a/drivers/sensor/iis328dq/CMakeLists.txt b/drivers/sensor/st/iis328dq/CMakeLists.txt similarity index 100% rename from drivers/sensor/iis328dq/CMakeLists.txt rename to drivers/sensor/st/iis328dq/CMakeLists.txt diff --git a/drivers/sensor/iis328dq/Kconfig b/drivers/sensor/st/iis328dq/Kconfig similarity index 100% rename from drivers/sensor/iis328dq/Kconfig rename to drivers/sensor/st/iis328dq/Kconfig diff --git a/drivers/sensor/iis328dq/iis328dq.c b/drivers/sensor/st/iis328dq/iis328dq.c similarity index 100% rename from drivers/sensor/iis328dq/iis328dq.c rename to drivers/sensor/st/iis328dq/iis328dq.c diff --git a/drivers/sensor/iis328dq/iis328dq.h b/drivers/sensor/st/iis328dq/iis328dq.h similarity index 100% rename from drivers/sensor/iis328dq/iis328dq.h rename to drivers/sensor/st/iis328dq/iis328dq.h diff --git a/drivers/sensor/iis328dq/iis328dq_trigger.c b/drivers/sensor/st/iis328dq/iis328dq_trigger.c similarity index 100% rename from drivers/sensor/iis328dq/iis328dq_trigger.c rename to drivers/sensor/st/iis328dq/iis328dq_trigger.c diff --git a/drivers/sensor/iis3dhhc/CMakeLists.txt b/drivers/sensor/st/iis3dhhc/CMakeLists.txt similarity index 100% rename from drivers/sensor/iis3dhhc/CMakeLists.txt rename to drivers/sensor/st/iis3dhhc/CMakeLists.txt diff --git a/drivers/sensor/iis3dhhc/Kconfig b/drivers/sensor/st/iis3dhhc/Kconfig similarity index 100% rename from drivers/sensor/iis3dhhc/Kconfig rename to drivers/sensor/st/iis3dhhc/Kconfig diff --git a/drivers/sensor/iis3dhhc/iis3dhhc.c b/drivers/sensor/st/iis3dhhc/iis3dhhc.c similarity index 100% rename from drivers/sensor/iis3dhhc/iis3dhhc.c rename to drivers/sensor/st/iis3dhhc/iis3dhhc.c diff --git a/drivers/sensor/iis3dhhc/iis3dhhc.h b/drivers/sensor/st/iis3dhhc/iis3dhhc.h similarity index 100% rename from drivers/sensor/iis3dhhc/iis3dhhc.h rename to drivers/sensor/st/iis3dhhc/iis3dhhc.h diff --git a/drivers/sensor/iis3dhhc/iis3dhhc_spi.c b/drivers/sensor/st/iis3dhhc/iis3dhhc_spi.c similarity index 100% rename from drivers/sensor/iis3dhhc/iis3dhhc_spi.c rename to drivers/sensor/st/iis3dhhc/iis3dhhc_spi.c diff --git a/drivers/sensor/iis3dhhc/iis3dhhc_trigger.c b/drivers/sensor/st/iis3dhhc/iis3dhhc_trigger.c similarity index 100% rename from drivers/sensor/iis3dhhc/iis3dhhc_trigger.c rename to drivers/sensor/st/iis3dhhc/iis3dhhc_trigger.c diff --git a/drivers/sensor/ism330dhcx/CMakeLists.txt b/drivers/sensor/st/ism330dhcx/CMakeLists.txt similarity index 100% rename from drivers/sensor/ism330dhcx/CMakeLists.txt rename to drivers/sensor/st/ism330dhcx/CMakeLists.txt diff --git a/drivers/sensor/ism330dhcx/Kconfig b/drivers/sensor/st/ism330dhcx/Kconfig similarity index 100% rename from drivers/sensor/ism330dhcx/Kconfig rename to drivers/sensor/st/ism330dhcx/Kconfig diff --git a/drivers/sensor/ism330dhcx/ism330dhcx.c b/drivers/sensor/st/ism330dhcx/ism330dhcx.c similarity index 100% rename from drivers/sensor/ism330dhcx/ism330dhcx.c rename to drivers/sensor/st/ism330dhcx/ism330dhcx.c diff --git a/drivers/sensor/ism330dhcx/ism330dhcx.h b/drivers/sensor/st/ism330dhcx/ism330dhcx.h similarity index 100% rename from drivers/sensor/ism330dhcx/ism330dhcx.h rename to drivers/sensor/st/ism330dhcx/ism330dhcx.h diff --git a/drivers/sensor/ism330dhcx/ism330dhcx_i2c.c b/drivers/sensor/st/ism330dhcx/ism330dhcx_i2c.c similarity index 100% rename from drivers/sensor/ism330dhcx/ism330dhcx_i2c.c rename to drivers/sensor/st/ism330dhcx/ism330dhcx_i2c.c diff --git a/drivers/sensor/ism330dhcx/ism330dhcx_shub.c b/drivers/sensor/st/ism330dhcx/ism330dhcx_shub.c similarity index 100% rename from drivers/sensor/ism330dhcx/ism330dhcx_shub.c rename to drivers/sensor/st/ism330dhcx/ism330dhcx_shub.c diff --git a/drivers/sensor/ism330dhcx/ism330dhcx_spi.c b/drivers/sensor/st/ism330dhcx/ism330dhcx_spi.c similarity index 100% rename from drivers/sensor/ism330dhcx/ism330dhcx_spi.c rename to drivers/sensor/st/ism330dhcx/ism330dhcx_spi.c diff --git a/drivers/sensor/ism330dhcx/ism330dhcx_trigger.c b/drivers/sensor/st/ism330dhcx/ism330dhcx_trigger.c similarity index 100% rename from drivers/sensor/ism330dhcx/ism330dhcx_trigger.c rename to drivers/sensor/st/ism330dhcx/ism330dhcx_trigger.c diff --git a/drivers/sensor/lis2de12/CMakeLists.txt b/drivers/sensor/st/lis2de12/CMakeLists.txt similarity index 100% rename from drivers/sensor/lis2de12/CMakeLists.txt rename to drivers/sensor/st/lis2de12/CMakeLists.txt diff --git a/drivers/sensor/lis2de12/Kconfig b/drivers/sensor/st/lis2de12/Kconfig similarity index 100% rename from drivers/sensor/lis2de12/Kconfig rename to drivers/sensor/st/lis2de12/Kconfig diff --git a/drivers/sensor/lis2de12/lis2de12.c b/drivers/sensor/st/lis2de12/lis2de12.c similarity index 100% rename from drivers/sensor/lis2de12/lis2de12.c rename to drivers/sensor/st/lis2de12/lis2de12.c diff --git a/drivers/sensor/lis2de12/lis2de12.h b/drivers/sensor/st/lis2de12/lis2de12.h similarity index 100% rename from drivers/sensor/lis2de12/lis2de12.h rename to drivers/sensor/st/lis2de12/lis2de12.h diff --git a/drivers/sensor/lis2de12/lis2de12_trigger.c b/drivers/sensor/st/lis2de12/lis2de12_trigger.c similarity index 100% rename from drivers/sensor/lis2de12/lis2de12_trigger.c rename to drivers/sensor/st/lis2de12/lis2de12_trigger.c diff --git a/drivers/sensor/lis2dh/CMakeLists.txt b/drivers/sensor/st/lis2dh/CMakeLists.txt similarity index 100% rename from drivers/sensor/lis2dh/CMakeLists.txt rename to drivers/sensor/st/lis2dh/CMakeLists.txt diff --git a/drivers/sensor/lis2dh/Kconfig b/drivers/sensor/st/lis2dh/Kconfig similarity index 100% rename from drivers/sensor/lis2dh/Kconfig rename to drivers/sensor/st/lis2dh/Kconfig diff --git a/drivers/sensor/lis2dh/lis2dh.c b/drivers/sensor/st/lis2dh/lis2dh.c similarity index 100% rename from drivers/sensor/lis2dh/lis2dh.c rename to drivers/sensor/st/lis2dh/lis2dh.c diff --git a/drivers/sensor/lis2dh/lis2dh.h b/drivers/sensor/st/lis2dh/lis2dh.h similarity index 100% rename from drivers/sensor/lis2dh/lis2dh.h rename to drivers/sensor/st/lis2dh/lis2dh.h diff --git a/drivers/sensor/lis2dh/lis2dh_i2c.c b/drivers/sensor/st/lis2dh/lis2dh_i2c.c similarity index 100% rename from drivers/sensor/lis2dh/lis2dh_i2c.c rename to drivers/sensor/st/lis2dh/lis2dh_i2c.c diff --git a/drivers/sensor/lis2dh/lis2dh_spi.c b/drivers/sensor/st/lis2dh/lis2dh_spi.c similarity index 100% rename from drivers/sensor/lis2dh/lis2dh_spi.c rename to drivers/sensor/st/lis2dh/lis2dh_spi.c diff --git a/drivers/sensor/lis2dh/lis2dh_trigger.c b/drivers/sensor/st/lis2dh/lis2dh_trigger.c similarity index 100% rename from drivers/sensor/lis2dh/lis2dh_trigger.c rename to drivers/sensor/st/lis2dh/lis2dh_trigger.c diff --git a/drivers/sensor/lis2ds12/CMakeLists.txt b/drivers/sensor/st/lis2ds12/CMakeLists.txt similarity index 100% rename from drivers/sensor/lis2ds12/CMakeLists.txt rename to drivers/sensor/st/lis2ds12/CMakeLists.txt diff --git a/drivers/sensor/lis2ds12/Kconfig b/drivers/sensor/st/lis2ds12/Kconfig similarity index 100% rename from drivers/sensor/lis2ds12/Kconfig rename to drivers/sensor/st/lis2ds12/Kconfig diff --git a/drivers/sensor/lis2ds12/lis2ds12.c b/drivers/sensor/st/lis2ds12/lis2ds12.c similarity index 100% rename from drivers/sensor/lis2ds12/lis2ds12.c rename to drivers/sensor/st/lis2ds12/lis2ds12.c diff --git a/drivers/sensor/lis2ds12/lis2ds12.h b/drivers/sensor/st/lis2ds12/lis2ds12.h similarity index 100% rename from drivers/sensor/lis2ds12/lis2ds12.h rename to drivers/sensor/st/lis2ds12/lis2ds12.h diff --git a/drivers/sensor/lis2ds12/lis2ds12_trigger.c b/drivers/sensor/st/lis2ds12/lis2ds12_trigger.c similarity index 100% rename from drivers/sensor/lis2ds12/lis2ds12_trigger.c rename to drivers/sensor/st/lis2ds12/lis2ds12_trigger.c diff --git a/drivers/sensor/lis2du12/CMakeLists.txt b/drivers/sensor/st/lis2du12/CMakeLists.txt similarity index 100% rename from drivers/sensor/lis2du12/CMakeLists.txt rename to drivers/sensor/st/lis2du12/CMakeLists.txt diff --git a/drivers/sensor/lis2du12/Kconfig b/drivers/sensor/st/lis2du12/Kconfig similarity index 100% rename from drivers/sensor/lis2du12/Kconfig rename to drivers/sensor/st/lis2du12/Kconfig diff --git a/drivers/sensor/lis2du12/lis2du12.c b/drivers/sensor/st/lis2du12/lis2du12.c similarity index 100% rename from drivers/sensor/lis2du12/lis2du12.c rename to drivers/sensor/st/lis2du12/lis2du12.c diff --git a/drivers/sensor/lis2du12/lis2du12.h b/drivers/sensor/st/lis2du12/lis2du12.h similarity index 100% rename from drivers/sensor/lis2du12/lis2du12.h rename to drivers/sensor/st/lis2du12/lis2du12.h diff --git a/drivers/sensor/lis2du12/lis2du12_trigger.c b/drivers/sensor/st/lis2du12/lis2du12_trigger.c similarity index 100% rename from drivers/sensor/lis2du12/lis2du12_trigger.c rename to drivers/sensor/st/lis2du12/lis2du12_trigger.c diff --git a/drivers/sensor/lis2dux12/CMakeLists.txt b/drivers/sensor/st/lis2dux12/CMakeLists.txt similarity index 100% rename from drivers/sensor/lis2dux12/CMakeLists.txt rename to drivers/sensor/st/lis2dux12/CMakeLists.txt diff --git a/drivers/sensor/lis2dux12/Kconfig b/drivers/sensor/st/lis2dux12/Kconfig similarity index 100% rename from drivers/sensor/lis2dux12/Kconfig rename to drivers/sensor/st/lis2dux12/Kconfig diff --git a/drivers/sensor/lis2dux12/lis2dux12.c b/drivers/sensor/st/lis2dux12/lis2dux12.c similarity index 100% rename from drivers/sensor/lis2dux12/lis2dux12.c rename to drivers/sensor/st/lis2dux12/lis2dux12.c diff --git a/drivers/sensor/lis2dux12/lis2dux12.h b/drivers/sensor/st/lis2dux12/lis2dux12.h similarity index 100% rename from drivers/sensor/lis2dux12/lis2dux12.h rename to drivers/sensor/st/lis2dux12/lis2dux12.h diff --git a/drivers/sensor/lis2dux12/lis2dux12_trigger.c b/drivers/sensor/st/lis2dux12/lis2dux12_trigger.c similarity index 100% rename from drivers/sensor/lis2dux12/lis2dux12_trigger.c rename to drivers/sensor/st/lis2dux12/lis2dux12_trigger.c diff --git a/drivers/sensor/lis2dw12/CMakeLists.txt b/drivers/sensor/st/lis2dw12/CMakeLists.txt similarity index 100% rename from drivers/sensor/lis2dw12/CMakeLists.txt rename to drivers/sensor/st/lis2dw12/CMakeLists.txt diff --git a/drivers/sensor/lis2dw12/Kconfig b/drivers/sensor/st/lis2dw12/Kconfig similarity index 100% rename from drivers/sensor/lis2dw12/Kconfig rename to drivers/sensor/st/lis2dw12/Kconfig diff --git a/drivers/sensor/lis2dw12/lis2dw12.c b/drivers/sensor/st/lis2dw12/lis2dw12.c similarity index 100% rename from drivers/sensor/lis2dw12/lis2dw12.c rename to drivers/sensor/st/lis2dw12/lis2dw12.c diff --git a/drivers/sensor/lis2dw12/lis2dw12.h b/drivers/sensor/st/lis2dw12/lis2dw12.h similarity index 100% rename from drivers/sensor/lis2dw12/lis2dw12.h rename to drivers/sensor/st/lis2dw12/lis2dw12.h diff --git a/drivers/sensor/lis2dw12/lis2dw12_trigger.c b/drivers/sensor/st/lis2dw12/lis2dw12_trigger.c similarity index 100% rename from drivers/sensor/lis2dw12/lis2dw12_trigger.c rename to drivers/sensor/st/lis2dw12/lis2dw12_trigger.c diff --git a/drivers/sensor/lis2mdl/CMakeLists.txt b/drivers/sensor/st/lis2mdl/CMakeLists.txt similarity index 100% rename from drivers/sensor/lis2mdl/CMakeLists.txt rename to drivers/sensor/st/lis2mdl/CMakeLists.txt diff --git a/drivers/sensor/lis2mdl/Kconfig b/drivers/sensor/st/lis2mdl/Kconfig similarity index 100% rename from drivers/sensor/lis2mdl/Kconfig rename to drivers/sensor/st/lis2mdl/Kconfig diff --git a/drivers/sensor/lis2mdl/lis2mdl.c b/drivers/sensor/st/lis2mdl/lis2mdl.c similarity index 100% rename from drivers/sensor/lis2mdl/lis2mdl.c rename to drivers/sensor/st/lis2mdl/lis2mdl.c diff --git a/drivers/sensor/lis2mdl/lis2mdl.h b/drivers/sensor/st/lis2mdl/lis2mdl.h similarity index 100% rename from drivers/sensor/lis2mdl/lis2mdl.h rename to drivers/sensor/st/lis2mdl/lis2mdl.h diff --git a/drivers/sensor/lis2mdl/lis2mdl_trigger.c b/drivers/sensor/st/lis2mdl/lis2mdl_trigger.c similarity index 100% rename from drivers/sensor/lis2mdl/lis2mdl_trigger.c rename to drivers/sensor/st/lis2mdl/lis2mdl_trigger.c diff --git a/drivers/sensor/lis3mdl/CMakeLists.txt b/drivers/sensor/st/lis3mdl/CMakeLists.txt similarity index 100% rename from drivers/sensor/lis3mdl/CMakeLists.txt rename to drivers/sensor/st/lis3mdl/CMakeLists.txt diff --git a/drivers/sensor/lis3mdl/Kconfig b/drivers/sensor/st/lis3mdl/Kconfig similarity index 100% rename from drivers/sensor/lis3mdl/Kconfig rename to drivers/sensor/st/lis3mdl/Kconfig diff --git a/drivers/sensor/lis3mdl/lis3mdl.c b/drivers/sensor/st/lis3mdl/lis3mdl.c similarity index 100% rename from drivers/sensor/lis3mdl/lis3mdl.c rename to drivers/sensor/st/lis3mdl/lis3mdl.c diff --git a/drivers/sensor/lis3mdl/lis3mdl.h b/drivers/sensor/st/lis3mdl/lis3mdl.h similarity index 100% rename from drivers/sensor/lis3mdl/lis3mdl.h rename to drivers/sensor/st/lis3mdl/lis3mdl.h diff --git a/drivers/sensor/lis3mdl/lis3mdl_trigger.c b/drivers/sensor/st/lis3mdl/lis3mdl_trigger.c similarity index 100% rename from drivers/sensor/lis3mdl/lis3mdl_trigger.c rename to drivers/sensor/st/lis3mdl/lis3mdl_trigger.c diff --git a/drivers/sensor/lps22hb/CMakeLists.txt b/drivers/sensor/st/lps22hb/CMakeLists.txt similarity index 100% rename from drivers/sensor/lps22hb/CMakeLists.txt rename to drivers/sensor/st/lps22hb/CMakeLists.txt diff --git a/drivers/sensor/lps22hb/Kconfig b/drivers/sensor/st/lps22hb/Kconfig similarity index 100% rename from drivers/sensor/lps22hb/Kconfig rename to drivers/sensor/st/lps22hb/Kconfig diff --git a/drivers/sensor/lps22hb/lps22hb.c b/drivers/sensor/st/lps22hb/lps22hb.c similarity index 100% rename from drivers/sensor/lps22hb/lps22hb.c rename to drivers/sensor/st/lps22hb/lps22hb.c diff --git a/drivers/sensor/lps22hb/lps22hb.h b/drivers/sensor/st/lps22hb/lps22hb.h similarity index 100% rename from drivers/sensor/lps22hb/lps22hb.h rename to drivers/sensor/st/lps22hb/lps22hb.h diff --git a/drivers/sensor/lps22hh/CMakeLists.txt b/drivers/sensor/st/lps22hh/CMakeLists.txt similarity index 100% rename from drivers/sensor/lps22hh/CMakeLists.txt rename to drivers/sensor/st/lps22hh/CMakeLists.txt diff --git a/drivers/sensor/lps22hh/Kconfig b/drivers/sensor/st/lps22hh/Kconfig similarity index 100% rename from drivers/sensor/lps22hh/Kconfig rename to drivers/sensor/st/lps22hh/Kconfig diff --git a/drivers/sensor/lps22hh/lps22hh.c b/drivers/sensor/st/lps22hh/lps22hh.c similarity index 100% rename from drivers/sensor/lps22hh/lps22hh.c rename to drivers/sensor/st/lps22hh/lps22hh.c diff --git a/drivers/sensor/lps22hh/lps22hh.h b/drivers/sensor/st/lps22hh/lps22hh.h similarity index 100% rename from drivers/sensor/lps22hh/lps22hh.h rename to drivers/sensor/st/lps22hh/lps22hh.h diff --git a/drivers/sensor/lps22hh/lps22hh_trigger.c b/drivers/sensor/st/lps22hh/lps22hh_trigger.c similarity index 100% rename from drivers/sensor/lps22hh/lps22hh_trigger.c rename to drivers/sensor/st/lps22hh/lps22hh_trigger.c diff --git a/drivers/sensor/lps25hb/CMakeLists.txt b/drivers/sensor/st/lps25hb/CMakeLists.txt similarity index 100% rename from drivers/sensor/lps25hb/CMakeLists.txt rename to drivers/sensor/st/lps25hb/CMakeLists.txt diff --git a/drivers/sensor/lps25hb/Kconfig b/drivers/sensor/st/lps25hb/Kconfig similarity index 100% rename from drivers/sensor/lps25hb/Kconfig rename to drivers/sensor/st/lps25hb/Kconfig diff --git a/drivers/sensor/lps25hb/lps25hb.c b/drivers/sensor/st/lps25hb/lps25hb.c similarity index 100% rename from drivers/sensor/lps25hb/lps25hb.c rename to drivers/sensor/st/lps25hb/lps25hb.c diff --git a/drivers/sensor/lps25hb/lps25hb.h b/drivers/sensor/st/lps25hb/lps25hb.h similarity index 100% rename from drivers/sensor/lps25hb/lps25hb.h rename to drivers/sensor/st/lps25hb/lps25hb.h diff --git a/drivers/sensor/lps2xdf/CMakeLists.txt b/drivers/sensor/st/lps2xdf/CMakeLists.txt similarity index 100% rename from drivers/sensor/lps2xdf/CMakeLists.txt rename to drivers/sensor/st/lps2xdf/CMakeLists.txt diff --git a/drivers/sensor/lps2xdf/Kconfig b/drivers/sensor/st/lps2xdf/Kconfig similarity index 100% rename from drivers/sensor/lps2xdf/Kconfig rename to drivers/sensor/st/lps2xdf/Kconfig diff --git a/drivers/sensor/lps2xdf/lps22df.c b/drivers/sensor/st/lps2xdf/lps22df.c similarity index 100% rename from drivers/sensor/lps2xdf/lps22df.c rename to drivers/sensor/st/lps2xdf/lps22df.c diff --git a/drivers/sensor/lps2xdf/lps22df.h b/drivers/sensor/st/lps2xdf/lps22df.h similarity index 100% rename from drivers/sensor/lps2xdf/lps22df.h rename to drivers/sensor/st/lps2xdf/lps22df.h diff --git a/drivers/sensor/lps2xdf/lps28dfw.c b/drivers/sensor/st/lps2xdf/lps28dfw.c similarity index 100% rename from drivers/sensor/lps2xdf/lps28dfw.c rename to drivers/sensor/st/lps2xdf/lps28dfw.c diff --git a/drivers/sensor/lps2xdf/lps28dfw.h b/drivers/sensor/st/lps2xdf/lps28dfw.h similarity index 100% rename from drivers/sensor/lps2xdf/lps28dfw.h rename to drivers/sensor/st/lps2xdf/lps28dfw.h diff --git a/drivers/sensor/lps2xdf/lps2xdf.c b/drivers/sensor/st/lps2xdf/lps2xdf.c similarity index 100% rename from drivers/sensor/lps2xdf/lps2xdf.c rename to drivers/sensor/st/lps2xdf/lps2xdf.c diff --git a/drivers/sensor/lps2xdf/lps2xdf.h b/drivers/sensor/st/lps2xdf/lps2xdf.h similarity index 100% rename from drivers/sensor/lps2xdf/lps2xdf.h rename to drivers/sensor/st/lps2xdf/lps2xdf.h diff --git a/drivers/sensor/lps2xdf/lps2xdf_trigger.c b/drivers/sensor/st/lps2xdf/lps2xdf_trigger.c similarity index 100% rename from drivers/sensor/lps2xdf/lps2xdf_trigger.c rename to drivers/sensor/st/lps2xdf/lps2xdf_trigger.c diff --git a/drivers/sensor/lsm303dlhc_magn/CMakeLists.txt b/drivers/sensor/st/lsm303dlhc_magn/CMakeLists.txt similarity index 100% rename from drivers/sensor/lsm303dlhc_magn/CMakeLists.txt rename to drivers/sensor/st/lsm303dlhc_magn/CMakeLists.txt diff --git a/drivers/sensor/lsm303dlhc_magn/Kconfig b/drivers/sensor/st/lsm303dlhc_magn/Kconfig similarity index 100% rename from drivers/sensor/lsm303dlhc_magn/Kconfig rename to drivers/sensor/st/lsm303dlhc_magn/Kconfig diff --git a/drivers/sensor/lsm303dlhc_magn/lsm303dlhc_magn.c b/drivers/sensor/st/lsm303dlhc_magn/lsm303dlhc_magn.c similarity index 100% rename from drivers/sensor/lsm303dlhc_magn/lsm303dlhc_magn.c rename to drivers/sensor/st/lsm303dlhc_magn/lsm303dlhc_magn.c diff --git a/drivers/sensor/lsm303dlhc_magn/lsm303dlhc_magn.h b/drivers/sensor/st/lsm303dlhc_magn/lsm303dlhc_magn.h similarity index 100% rename from drivers/sensor/lsm303dlhc_magn/lsm303dlhc_magn.h rename to drivers/sensor/st/lsm303dlhc_magn/lsm303dlhc_magn.h diff --git a/drivers/sensor/lsm6ds0/CMakeLists.txt b/drivers/sensor/st/lsm6ds0/CMakeLists.txt similarity index 100% rename from drivers/sensor/lsm6ds0/CMakeLists.txt rename to drivers/sensor/st/lsm6ds0/CMakeLists.txt diff --git a/drivers/sensor/lsm6ds0/Kconfig b/drivers/sensor/st/lsm6ds0/Kconfig similarity index 100% rename from drivers/sensor/lsm6ds0/Kconfig rename to drivers/sensor/st/lsm6ds0/Kconfig diff --git a/drivers/sensor/lsm6ds0/lsm6ds0.c b/drivers/sensor/st/lsm6ds0/lsm6ds0.c similarity index 100% rename from drivers/sensor/lsm6ds0/lsm6ds0.c rename to drivers/sensor/st/lsm6ds0/lsm6ds0.c diff --git a/drivers/sensor/lsm6ds0/lsm6ds0.h b/drivers/sensor/st/lsm6ds0/lsm6ds0.h similarity index 100% rename from drivers/sensor/lsm6ds0/lsm6ds0.h rename to drivers/sensor/st/lsm6ds0/lsm6ds0.h diff --git a/drivers/sensor/lsm6dsl/CMakeLists.txt b/drivers/sensor/st/lsm6dsl/CMakeLists.txt similarity index 100% rename from drivers/sensor/lsm6dsl/CMakeLists.txt rename to drivers/sensor/st/lsm6dsl/CMakeLists.txt diff --git a/drivers/sensor/lsm6dsl/Kconfig b/drivers/sensor/st/lsm6dsl/Kconfig similarity index 100% rename from drivers/sensor/lsm6dsl/Kconfig rename to drivers/sensor/st/lsm6dsl/Kconfig diff --git a/drivers/sensor/lsm6dsl/lsm6dsl.c b/drivers/sensor/st/lsm6dsl/lsm6dsl.c similarity index 100% rename from drivers/sensor/lsm6dsl/lsm6dsl.c rename to drivers/sensor/st/lsm6dsl/lsm6dsl.c diff --git a/drivers/sensor/lsm6dsl/lsm6dsl.h b/drivers/sensor/st/lsm6dsl/lsm6dsl.h similarity index 100% rename from drivers/sensor/lsm6dsl/lsm6dsl.h rename to drivers/sensor/st/lsm6dsl/lsm6dsl.h diff --git a/drivers/sensor/lsm6dsl/lsm6dsl_i2c.c b/drivers/sensor/st/lsm6dsl/lsm6dsl_i2c.c similarity index 100% rename from drivers/sensor/lsm6dsl/lsm6dsl_i2c.c rename to drivers/sensor/st/lsm6dsl/lsm6dsl_i2c.c diff --git a/drivers/sensor/lsm6dsl/lsm6dsl_shub.c b/drivers/sensor/st/lsm6dsl/lsm6dsl_shub.c similarity index 100% rename from drivers/sensor/lsm6dsl/lsm6dsl_shub.c rename to drivers/sensor/st/lsm6dsl/lsm6dsl_shub.c diff --git a/drivers/sensor/lsm6dsl/lsm6dsl_spi.c b/drivers/sensor/st/lsm6dsl/lsm6dsl_spi.c similarity index 100% rename from drivers/sensor/lsm6dsl/lsm6dsl_spi.c rename to drivers/sensor/st/lsm6dsl/lsm6dsl_spi.c diff --git a/drivers/sensor/lsm6dsl/lsm6dsl_trigger.c b/drivers/sensor/st/lsm6dsl/lsm6dsl_trigger.c similarity index 100% rename from drivers/sensor/lsm6dsl/lsm6dsl_trigger.c rename to drivers/sensor/st/lsm6dsl/lsm6dsl_trigger.c diff --git a/drivers/sensor/lsm6dso/CMakeLists.txt b/drivers/sensor/st/lsm6dso/CMakeLists.txt similarity index 100% rename from drivers/sensor/lsm6dso/CMakeLists.txt rename to drivers/sensor/st/lsm6dso/CMakeLists.txt diff --git a/drivers/sensor/lsm6dso/Kconfig b/drivers/sensor/st/lsm6dso/Kconfig similarity index 100% rename from drivers/sensor/lsm6dso/Kconfig rename to drivers/sensor/st/lsm6dso/Kconfig diff --git a/drivers/sensor/lsm6dso/lsm6dso.c b/drivers/sensor/st/lsm6dso/lsm6dso.c similarity index 100% rename from drivers/sensor/lsm6dso/lsm6dso.c rename to drivers/sensor/st/lsm6dso/lsm6dso.c diff --git a/drivers/sensor/lsm6dso/lsm6dso.h b/drivers/sensor/st/lsm6dso/lsm6dso.h similarity index 100% rename from drivers/sensor/lsm6dso/lsm6dso.h rename to drivers/sensor/st/lsm6dso/lsm6dso.h diff --git a/drivers/sensor/lsm6dso/lsm6dso_shub.c b/drivers/sensor/st/lsm6dso/lsm6dso_shub.c similarity index 100% rename from drivers/sensor/lsm6dso/lsm6dso_shub.c rename to drivers/sensor/st/lsm6dso/lsm6dso_shub.c diff --git a/drivers/sensor/lsm6dso/lsm6dso_trigger.c b/drivers/sensor/st/lsm6dso/lsm6dso_trigger.c similarity index 100% rename from drivers/sensor/lsm6dso/lsm6dso_trigger.c rename to drivers/sensor/st/lsm6dso/lsm6dso_trigger.c diff --git a/drivers/sensor/lsm6dso16is/CMakeLists.txt b/drivers/sensor/st/lsm6dso16is/CMakeLists.txt similarity index 100% rename from drivers/sensor/lsm6dso16is/CMakeLists.txt rename to drivers/sensor/st/lsm6dso16is/CMakeLists.txt diff --git a/drivers/sensor/lsm6dso16is/Kconfig b/drivers/sensor/st/lsm6dso16is/Kconfig similarity index 100% rename from drivers/sensor/lsm6dso16is/Kconfig rename to drivers/sensor/st/lsm6dso16is/Kconfig diff --git a/drivers/sensor/lsm6dso16is/lsm6dso16is.c b/drivers/sensor/st/lsm6dso16is/lsm6dso16is.c similarity index 100% rename from drivers/sensor/lsm6dso16is/lsm6dso16is.c rename to drivers/sensor/st/lsm6dso16is/lsm6dso16is.c diff --git a/drivers/sensor/lsm6dso16is/lsm6dso16is.h b/drivers/sensor/st/lsm6dso16is/lsm6dso16is.h similarity index 100% rename from drivers/sensor/lsm6dso16is/lsm6dso16is.h rename to drivers/sensor/st/lsm6dso16is/lsm6dso16is.h diff --git a/drivers/sensor/lsm6dso16is/lsm6dso16is_shub.c b/drivers/sensor/st/lsm6dso16is/lsm6dso16is_shub.c similarity index 100% rename from drivers/sensor/lsm6dso16is/lsm6dso16is_shub.c rename to drivers/sensor/st/lsm6dso16is/lsm6dso16is_shub.c diff --git a/drivers/sensor/lsm6dso16is/lsm6dso16is_trigger.c b/drivers/sensor/st/lsm6dso16is/lsm6dso16is_trigger.c similarity index 100% rename from drivers/sensor/lsm6dso16is/lsm6dso16is_trigger.c rename to drivers/sensor/st/lsm6dso16is/lsm6dso16is_trigger.c diff --git a/drivers/sensor/lsm6dsv16x/CMakeLists.txt b/drivers/sensor/st/lsm6dsv16x/CMakeLists.txt similarity index 100% rename from drivers/sensor/lsm6dsv16x/CMakeLists.txt rename to drivers/sensor/st/lsm6dsv16x/CMakeLists.txt diff --git a/drivers/sensor/lsm6dsv16x/Kconfig b/drivers/sensor/st/lsm6dsv16x/Kconfig similarity index 100% rename from drivers/sensor/lsm6dsv16x/Kconfig rename to drivers/sensor/st/lsm6dsv16x/Kconfig diff --git a/drivers/sensor/lsm6dsv16x/lsm6dsv16x.c b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.c similarity index 100% rename from drivers/sensor/lsm6dsv16x/lsm6dsv16x.c rename to drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.c diff --git a/drivers/sensor/lsm6dsv16x/lsm6dsv16x.h b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h similarity index 100% rename from drivers/sensor/lsm6dsv16x/lsm6dsv16x.h rename to drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h diff --git a/drivers/sensor/lsm6dsv16x/lsm6dsv16x_shub.c b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_shub.c similarity index 100% rename from drivers/sensor/lsm6dsv16x/lsm6dsv16x_shub.c rename to drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_shub.c diff --git a/drivers/sensor/lsm6dsv16x/lsm6dsv16x_trigger.c b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_trigger.c similarity index 100% rename from drivers/sensor/lsm6dsv16x/lsm6dsv16x_trigger.c rename to drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_trigger.c diff --git a/drivers/sensor/lsm9ds0_gyro/CMakeLists.txt b/drivers/sensor/st/lsm9ds0_gyro/CMakeLists.txt similarity index 100% rename from drivers/sensor/lsm9ds0_gyro/CMakeLists.txt rename to drivers/sensor/st/lsm9ds0_gyro/CMakeLists.txt diff --git a/drivers/sensor/lsm9ds0_gyro/Kconfig b/drivers/sensor/st/lsm9ds0_gyro/Kconfig similarity index 100% rename from drivers/sensor/lsm9ds0_gyro/Kconfig rename to drivers/sensor/st/lsm9ds0_gyro/Kconfig diff --git a/drivers/sensor/lsm9ds0_gyro/lsm9ds0_gyro.c b/drivers/sensor/st/lsm9ds0_gyro/lsm9ds0_gyro.c similarity index 100% rename from drivers/sensor/lsm9ds0_gyro/lsm9ds0_gyro.c rename to drivers/sensor/st/lsm9ds0_gyro/lsm9ds0_gyro.c diff --git a/drivers/sensor/lsm9ds0_gyro/lsm9ds0_gyro.h b/drivers/sensor/st/lsm9ds0_gyro/lsm9ds0_gyro.h similarity index 100% rename from drivers/sensor/lsm9ds0_gyro/lsm9ds0_gyro.h rename to drivers/sensor/st/lsm9ds0_gyro/lsm9ds0_gyro.h diff --git a/drivers/sensor/lsm9ds0_gyro/lsm9ds0_gyro_trigger.c b/drivers/sensor/st/lsm9ds0_gyro/lsm9ds0_gyro_trigger.c similarity index 100% rename from drivers/sensor/lsm9ds0_gyro/lsm9ds0_gyro_trigger.c rename to drivers/sensor/st/lsm9ds0_gyro/lsm9ds0_gyro_trigger.c diff --git a/drivers/sensor/lsm9ds0_mfd/CMakeLists.txt b/drivers/sensor/st/lsm9ds0_mfd/CMakeLists.txt similarity index 100% rename from drivers/sensor/lsm9ds0_mfd/CMakeLists.txt rename to drivers/sensor/st/lsm9ds0_mfd/CMakeLists.txt diff --git a/drivers/sensor/lsm9ds0_mfd/Kconfig b/drivers/sensor/st/lsm9ds0_mfd/Kconfig similarity index 100% rename from drivers/sensor/lsm9ds0_mfd/Kconfig rename to drivers/sensor/st/lsm9ds0_mfd/Kconfig diff --git a/drivers/sensor/lsm9ds0_mfd/lsm9ds0_mfd.c b/drivers/sensor/st/lsm9ds0_mfd/lsm9ds0_mfd.c similarity index 100% rename from drivers/sensor/lsm9ds0_mfd/lsm9ds0_mfd.c rename to drivers/sensor/st/lsm9ds0_mfd/lsm9ds0_mfd.c diff --git a/drivers/sensor/lsm9ds0_mfd/lsm9ds0_mfd.h b/drivers/sensor/st/lsm9ds0_mfd/lsm9ds0_mfd.h similarity index 100% rename from drivers/sensor/lsm9ds0_mfd/lsm9ds0_mfd.h rename to drivers/sensor/st/lsm9ds0_mfd/lsm9ds0_mfd.h diff --git a/drivers/sensor/qdec_stm32/CMakeLists.txt b/drivers/sensor/st/qdec_stm32/CMakeLists.txt similarity index 100% rename from drivers/sensor/qdec_stm32/CMakeLists.txt rename to drivers/sensor/st/qdec_stm32/CMakeLists.txt diff --git a/drivers/sensor/qdec_stm32/Kconfig b/drivers/sensor/st/qdec_stm32/Kconfig similarity index 100% rename from drivers/sensor/qdec_stm32/Kconfig rename to drivers/sensor/st/qdec_stm32/Kconfig diff --git a/drivers/sensor/qdec_stm32/qdec_stm32.c b/drivers/sensor/st/qdec_stm32/qdec_stm32.c similarity index 100% rename from drivers/sensor/qdec_stm32/qdec_stm32.c rename to drivers/sensor/st/qdec_stm32/qdec_stm32.c diff --git a/drivers/sensor/stm32_temp/CMakeLists.txt b/drivers/sensor/st/stm32_temp/CMakeLists.txt similarity index 100% rename from drivers/sensor/stm32_temp/CMakeLists.txt rename to drivers/sensor/st/stm32_temp/CMakeLists.txt diff --git a/drivers/sensor/stm32_temp/Kconfig b/drivers/sensor/st/stm32_temp/Kconfig similarity index 100% rename from drivers/sensor/stm32_temp/Kconfig rename to drivers/sensor/st/stm32_temp/Kconfig diff --git a/drivers/sensor/stm32_temp/stm32_temp.c b/drivers/sensor/st/stm32_temp/stm32_temp.c similarity index 100% rename from drivers/sensor/stm32_temp/stm32_temp.c rename to drivers/sensor/st/stm32_temp/stm32_temp.c diff --git a/drivers/sensor/stm32_vbat/CMakeLists.txt b/drivers/sensor/st/stm32_vbat/CMakeLists.txt similarity index 100% rename from drivers/sensor/stm32_vbat/CMakeLists.txt rename to drivers/sensor/st/stm32_vbat/CMakeLists.txt diff --git a/drivers/sensor/stm32_vbat/Kconfig b/drivers/sensor/st/stm32_vbat/Kconfig similarity index 100% rename from drivers/sensor/stm32_vbat/Kconfig rename to drivers/sensor/st/stm32_vbat/Kconfig diff --git a/drivers/sensor/stm32_vbat/stm32_vbat.c b/drivers/sensor/st/stm32_vbat/stm32_vbat.c similarity index 100% rename from drivers/sensor/stm32_vbat/stm32_vbat.c rename to drivers/sensor/st/stm32_vbat/stm32_vbat.c diff --git a/drivers/sensor/stm32_vref/CMakeLists.txt b/drivers/sensor/st/stm32_vref/CMakeLists.txt similarity index 100% rename from drivers/sensor/stm32_vref/CMakeLists.txt rename to drivers/sensor/st/stm32_vref/CMakeLists.txt diff --git a/drivers/sensor/stm32_vref/Kconfig b/drivers/sensor/st/stm32_vref/Kconfig similarity index 100% rename from drivers/sensor/stm32_vref/Kconfig rename to drivers/sensor/st/stm32_vref/Kconfig diff --git a/drivers/sensor/stm32_vref/stm32_vref.c b/drivers/sensor/st/stm32_vref/stm32_vref.c similarity index 100% rename from drivers/sensor/stm32_vref/stm32_vref.c rename to drivers/sensor/st/stm32_vref/stm32_vref.c diff --git a/drivers/sensor/stmemsc/CMakeLists.txt b/drivers/sensor/st/stmemsc/CMakeLists.txt similarity index 100% rename from drivers/sensor/stmemsc/CMakeLists.txt rename to drivers/sensor/st/stmemsc/CMakeLists.txt diff --git a/drivers/sensor/stmemsc/stmemsc.h b/drivers/sensor/st/stmemsc/stmemsc.h similarity index 100% rename from drivers/sensor/stmemsc/stmemsc.h rename to drivers/sensor/st/stmemsc/stmemsc.h diff --git a/drivers/sensor/stmemsc/stmemsc_i2c.c b/drivers/sensor/st/stmemsc/stmemsc_i2c.c similarity index 100% rename from drivers/sensor/stmemsc/stmemsc_i2c.c rename to drivers/sensor/st/stmemsc/stmemsc_i2c.c diff --git a/drivers/sensor/stmemsc/stmemsc_i3c.c b/drivers/sensor/st/stmemsc/stmemsc_i3c.c similarity index 100% rename from drivers/sensor/stmemsc/stmemsc_i3c.c rename to drivers/sensor/st/stmemsc/stmemsc_i3c.c diff --git a/drivers/sensor/stmemsc/stmemsc_mdelay.c b/drivers/sensor/st/stmemsc/stmemsc_mdelay.c similarity index 100% rename from drivers/sensor/stmemsc/stmemsc_mdelay.c rename to drivers/sensor/st/stmemsc/stmemsc_mdelay.c diff --git a/drivers/sensor/stmemsc/stmemsc_spi.c b/drivers/sensor/st/stmemsc/stmemsc_spi.c similarity index 100% rename from drivers/sensor/stmemsc/stmemsc_spi.c rename to drivers/sensor/st/stmemsc/stmemsc_spi.c diff --git a/drivers/sensor/stts22h/CMakeLists.txt b/drivers/sensor/st/stts22h/CMakeLists.txt similarity index 100% rename from drivers/sensor/stts22h/CMakeLists.txt rename to drivers/sensor/st/stts22h/CMakeLists.txt diff --git a/drivers/sensor/stts22h/Kconfig b/drivers/sensor/st/stts22h/Kconfig similarity index 100% rename from drivers/sensor/stts22h/Kconfig rename to drivers/sensor/st/stts22h/Kconfig diff --git a/drivers/sensor/stts22h/stts22h.c b/drivers/sensor/st/stts22h/stts22h.c similarity index 100% rename from drivers/sensor/stts22h/stts22h.c rename to drivers/sensor/st/stts22h/stts22h.c diff --git a/drivers/sensor/stts22h/stts22h.h b/drivers/sensor/st/stts22h/stts22h.h similarity index 100% rename from drivers/sensor/stts22h/stts22h.h rename to drivers/sensor/st/stts22h/stts22h.h diff --git a/drivers/sensor/stts22h/stts22h_trigger.c b/drivers/sensor/st/stts22h/stts22h_trigger.c similarity index 100% rename from drivers/sensor/stts22h/stts22h_trigger.c rename to drivers/sensor/st/stts22h/stts22h_trigger.c diff --git a/drivers/sensor/stts751/CMakeLists.txt b/drivers/sensor/st/stts751/CMakeLists.txt similarity index 100% rename from drivers/sensor/stts751/CMakeLists.txt rename to drivers/sensor/st/stts751/CMakeLists.txt diff --git a/drivers/sensor/stts751/Kconfig b/drivers/sensor/st/stts751/Kconfig similarity index 100% rename from drivers/sensor/stts751/Kconfig rename to drivers/sensor/st/stts751/Kconfig diff --git a/drivers/sensor/stts751/stts751.c b/drivers/sensor/st/stts751/stts751.c similarity index 100% rename from drivers/sensor/stts751/stts751.c rename to drivers/sensor/st/stts751/stts751.c diff --git a/drivers/sensor/stts751/stts751.h b/drivers/sensor/st/stts751/stts751.h similarity index 100% rename from drivers/sensor/stts751/stts751.h rename to drivers/sensor/st/stts751/stts751.h diff --git a/drivers/sensor/stts751/stts751_i2c.c b/drivers/sensor/st/stts751/stts751_i2c.c similarity index 100% rename from drivers/sensor/stts751/stts751_i2c.c rename to drivers/sensor/st/stts751/stts751_i2c.c diff --git a/drivers/sensor/stts751/stts751_trigger.c b/drivers/sensor/st/stts751/stts751_trigger.c similarity index 100% rename from drivers/sensor/stts751/stts751_trigger.c rename to drivers/sensor/st/stts751/stts751_trigger.c diff --git a/drivers/sensor/vl53l0x/CMakeLists.txt b/drivers/sensor/st/vl53l0x/CMakeLists.txt similarity index 100% rename from drivers/sensor/vl53l0x/CMakeLists.txt rename to drivers/sensor/st/vl53l0x/CMakeLists.txt diff --git a/drivers/sensor/vl53l0x/Kconfig b/drivers/sensor/st/vl53l0x/Kconfig similarity index 100% rename from drivers/sensor/vl53l0x/Kconfig rename to drivers/sensor/st/vl53l0x/Kconfig diff --git a/drivers/sensor/vl53l0x/vl53l0x.c b/drivers/sensor/st/vl53l0x/vl53l0x.c similarity index 100% rename from drivers/sensor/vl53l0x/vl53l0x.c rename to drivers/sensor/st/vl53l0x/vl53l0x.c diff --git a/drivers/sensor/vl53l0x/vl53l0x_platform.c b/drivers/sensor/st/vl53l0x/vl53l0x_platform.c similarity index 100% rename from drivers/sensor/vl53l0x/vl53l0x_platform.c rename to drivers/sensor/st/vl53l0x/vl53l0x_platform.c diff --git a/drivers/sensor/vl53l0x/vl53l0x_platform.h b/drivers/sensor/st/vl53l0x/vl53l0x_platform.h similarity index 100% rename from drivers/sensor/vl53l0x/vl53l0x_platform.h rename to drivers/sensor/st/vl53l0x/vl53l0x_platform.h diff --git a/drivers/sensor/vl53l0x/vl53l0x_platform_log.h b/drivers/sensor/st/vl53l0x/vl53l0x_platform_log.h similarity index 100% rename from drivers/sensor/vl53l0x/vl53l0x_platform_log.h rename to drivers/sensor/st/vl53l0x/vl53l0x_platform_log.h diff --git a/drivers/sensor/vl53l0x/vl53l0x_types.h b/drivers/sensor/st/vl53l0x/vl53l0x_types.h similarity index 100% rename from drivers/sensor/vl53l0x/vl53l0x_types.h rename to drivers/sensor/st/vl53l0x/vl53l0x_types.h diff --git a/drivers/sensor/vl53l1x/CMakeLists.txt b/drivers/sensor/st/vl53l1x/CMakeLists.txt similarity index 100% rename from drivers/sensor/vl53l1x/CMakeLists.txt rename to drivers/sensor/st/vl53l1x/CMakeLists.txt diff --git a/drivers/sensor/vl53l1x/Kconfig b/drivers/sensor/st/vl53l1x/Kconfig similarity index 100% rename from drivers/sensor/vl53l1x/Kconfig rename to drivers/sensor/st/vl53l1x/Kconfig diff --git a/drivers/sensor/vl53l1x/vl53l1.c b/drivers/sensor/st/vl53l1x/vl53l1.c similarity index 100% rename from drivers/sensor/vl53l1x/vl53l1.c rename to drivers/sensor/st/vl53l1x/vl53l1.c diff --git a/drivers/sensor/vl53l1x/vl53l1_platform.c b/drivers/sensor/st/vl53l1x/vl53l1_platform.c similarity index 100% rename from drivers/sensor/vl53l1x/vl53l1_platform.c rename to drivers/sensor/st/vl53l1x/vl53l1_platform.c diff --git a/drivers/sensor/vl53l1x/vl53l1_platform.h b/drivers/sensor/st/vl53l1x/vl53l1_platform.h similarity index 100% rename from drivers/sensor/vl53l1x/vl53l1_platform.h rename to drivers/sensor/st/vl53l1x/vl53l1_platform.h diff --git a/drivers/sensor/vl53l1x/vl53l1_platform_log.h b/drivers/sensor/st/vl53l1x/vl53l1_platform_log.h similarity index 100% rename from drivers/sensor/vl53l1x/vl53l1_platform_log.h rename to drivers/sensor/st/vl53l1x/vl53l1_platform_log.h diff --git a/drivers/sensor/vl53l1x/vl53l1_platform_user_config.h b/drivers/sensor/st/vl53l1x/vl53l1_platform_user_config.h similarity index 100% rename from drivers/sensor/vl53l1x/vl53l1_platform_user_config.h rename to drivers/sensor/st/vl53l1x/vl53l1_platform_user_config.h diff --git a/drivers/sensor/vl53l1x/vl53l1_platform_user_data.h b/drivers/sensor/st/vl53l1x/vl53l1_platform_user_data.h similarity index 100% rename from drivers/sensor/vl53l1x/vl53l1_platform_user_data.h rename to drivers/sensor/st/vl53l1x/vl53l1_platform_user_data.h diff --git a/drivers/sensor/vl53l1x/vl53l1_platform_user_defines.h b/drivers/sensor/st/vl53l1x/vl53l1_platform_user_defines.h similarity index 100% rename from drivers/sensor/vl53l1x/vl53l1_platform_user_defines.h rename to drivers/sensor/st/vl53l1x/vl53l1_platform_user_defines.h diff --git a/drivers/sensor/vl53l1x/vl53l1_types.h b/drivers/sensor/st/vl53l1x/vl53l1_types.h similarity index 100% rename from drivers/sensor/vl53l1x/vl53l1_types.h rename to drivers/sensor/st/vl53l1x/vl53l1_types.h diff --git a/west.yml b/west.yml index 857dbfd5f5f..892de42faab 100644 --- a/west.yml +++ b/west.yml @@ -224,7 +224,7 @@ manifest: groups: - hal - name: hal_st - revision: 0643d20ae85b32c658ad11036f7c964a860ddefe + revision: b77157f6bc4395e398d90ab02a7d2cbc01ab2ce7 path: modules/hal/st groups: - hal From c02e3aa47a2b0498c654a4bde1b6401b440be5fb Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Tue, 26 Mar 2024 18:21:34 -0500 Subject: [PATCH 1967/2402] drivers: sensor: maxim: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 11 +---------- drivers/sensor/Kconfig | 11 +---------- drivers/sensor/maxim/CMakeLists.txt | 15 +++++++++++++++ drivers/sensor/maxim/Kconfig | 15 +++++++++++++++ drivers/sensor/{ => maxim}/ds18b20/CMakeLists.txt | 0 drivers/sensor/{ => maxim}/ds18b20/Kconfig | 0 drivers/sensor/{ => maxim}/ds18b20/ds18b20.c | 0 drivers/sensor/{ => maxim}/ds18b20/ds18b20.h | 0 .../sensor/{ => maxim}/max17055/CMakeLists.txt | 0 drivers/sensor/{ => maxim}/max17055/Kconfig | 0 drivers/sensor/{ => maxim}/max17055/max17055.c | 0 drivers/sensor/{ => maxim}/max17055/max17055.h | 0 .../sensor/{ => maxim}/max17262/CMakeLists.txt | 0 drivers/sensor/{ => maxim}/max17262/Kconfig | 0 drivers/sensor/{ => maxim}/max17262/max17262.c | 0 drivers/sensor/{ => maxim}/max17262/max17262.h | 0 .../sensor/{ => maxim}/max30101/CMakeLists.txt | 0 drivers/sensor/{ => maxim}/max30101/Kconfig | 0 drivers/sensor/{ => maxim}/max30101/max30101.c | 0 drivers/sensor/{ => maxim}/max30101/max30101.h | 0 .../sensor/{ => maxim}/max31790/CMakeLists.txt | 0 drivers/sensor/{ => maxim}/max31790/Kconfig | 0 .../{ => maxim}/max31790/max31790_fan_fault.c | 0 .../{ => maxim}/max31790/max31790_fan_fault.h | 0 .../{ => maxim}/max31790/max31790_fan_speed.c | 0 .../{ => maxim}/max31790/max31790_fan_speed.h | 0 .../sensor/{ => maxim}/max31855/CMakeLists.txt | 0 drivers/sensor/{ => maxim}/max31855/Kconfig | 0 drivers/sensor/{ => maxim}/max31855/max31855.c | 0 .../sensor/{ => maxim}/max31865/CMakeLists.txt | 0 drivers/sensor/{ => maxim}/max31865/Kconfig | 0 drivers/sensor/{ => maxim}/max31865/max31865.c | 0 drivers/sensor/{ => maxim}/max31865/max31865.h | 0 .../sensor/{ => maxim}/max31875/CMakeLists.txt | 0 drivers/sensor/{ => maxim}/max31875/Kconfig | 0 drivers/sensor/{ => maxim}/max31875/max31875.c | 0 .../sensor/{ => maxim}/max44009/CMakeLists.txt | 0 drivers/sensor/{ => maxim}/max44009/Kconfig | 0 drivers/sensor/{ => maxim}/max44009/max44009.c | 0 drivers/sensor/{ => maxim}/max44009/max44009.h | 0 drivers/sensor/{ => maxim}/max6675/CMakeLists.txt | 0 drivers/sensor/{ => maxim}/max6675/Kconfig | 0 drivers/sensor/{ => maxim}/max6675/max6675.c | 0 43 files changed, 32 insertions(+), 20 deletions(-) create mode 100644 drivers/sensor/maxim/CMakeLists.txt create mode 100644 drivers/sensor/maxim/Kconfig rename drivers/sensor/{ => maxim}/ds18b20/CMakeLists.txt (100%) rename drivers/sensor/{ => maxim}/ds18b20/Kconfig (100%) rename drivers/sensor/{ => maxim}/ds18b20/ds18b20.c (100%) rename drivers/sensor/{ => maxim}/ds18b20/ds18b20.h (100%) rename drivers/sensor/{ => maxim}/max17055/CMakeLists.txt (100%) rename drivers/sensor/{ => maxim}/max17055/Kconfig (100%) rename drivers/sensor/{ => maxim}/max17055/max17055.c (100%) rename drivers/sensor/{ => maxim}/max17055/max17055.h (100%) rename drivers/sensor/{ => maxim}/max17262/CMakeLists.txt (100%) rename drivers/sensor/{ => maxim}/max17262/Kconfig (100%) rename drivers/sensor/{ => maxim}/max17262/max17262.c (100%) rename drivers/sensor/{ => maxim}/max17262/max17262.h (100%) rename drivers/sensor/{ => maxim}/max30101/CMakeLists.txt (100%) rename drivers/sensor/{ => maxim}/max30101/Kconfig (100%) rename drivers/sensor/{ => maxim}/max30101/max30101.c (100%) rename drivers/sensor/{ => maxim}/max30101/max30101.h (100%) rename drivers/sensor/{ => maxim}/max31790/CMakeLists.txt (100%) rename drivers/sensor/{ => maxim}/max31790/Kconfig (100%) rename drivers/sensor/{ => maxim}/max31790/max31790_fan_fault.c (100%) rename drivers/sensor/{ => maxim}/max31790/max31790_fan_fault.h (100%) rename drivers/sensor/{ => maxim}/max31790/max31790_fan_speed.c (100%) rename drivers/sensor/{ => maxim}/max31790/max31790_fan_speed.h (100%) rename drivers/sensor/{ => maxim}/max31855/CMakeLists.txt (100%) rename drivers/sensor/{ => maxim}/max31855/Kconfig (100%) rename drivers/sensor/{ => maxim}/max31855/max31855.c (100%) rename drivers/sensor/{ => maxim}/max31865/CMakeLists.txt (100%) rename drivers/sensor/{ => maxim}/max31865/Kconfig (100%) rename drivers/sensor/{ => maxim}/max31865/max31865.c (100%) rename drivers/sensor/{ => maxim}/max31865/max31865.h (100%) rename drivers/sensor/{ => maxim}/max31875/CMakeLists.txt (100%) rename drivers/sensor/{ => maxim}/max31875/Kconfig (100%) rename drivers/sensor/{ => maxim}/max31875/max31875.c (100%) rename drivers/sensor/{ => maxim}/max44009/CMakeLists.txt (100%) rename drivers/sensor/{ => maxim}/max44009/Kconfig (100%) rename drivers/sensor/{ => maxim}/max44009/max44009.c (100%) rename drivers/sensor/{ => maxim}/max44009/max44009.h (100%) rename drivers/sensor/{ => maxim}/max6675/CMakeLists.txt (100%) rename drivers/sensor/{ => maxim}/max6675/Kconfig (100%) rename drivers/sensor/{ => maxim}/max6675/max6675.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 4dfef2e3f88..285f61544e2 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -3,6 +3,7 @@ # zephyr-keep-sorted-start add_subdirectory(adi) add_subdirectory(bosch) +add_subdirectory(maxim) add_subdirectory(st) # zephyr-keep-sorted-stop @@ -24,7 +25,6 @@ add_subdirectory_ifdef(CONFIG_CURRENT_AMP current_amp) add_subdirectory_ifdef(CONFIG_DHT dht) add_subdirectory_ifdef(CONFIG_DHT20 dht20) add_subdirectory_ifdef(CONFIG_DPS310 dps310) -add_subdirectory_ifdef(CONFIG_DS18B20 ds18b20) add_subdirectory_ifdef(CONFIG_ENS160 ens160) add_subdirectory_ifdef(CONFIG_ENS210 ens210) add_subdirectory_ifdef(CONFIG_ESP32_TEMP esp32_temp) @@ -54,15 +54,6 @@ add_subdirectory_ifdef(CONFIG_LM35 lm35) add_subdirectory_ifdef(CONFIG_LM75 lm75) add_subdirectory_ifdef(CONFIG_LM77 lm77) add_subdirectory_ifdef(CONFIG_LTR_F216A ltrf216a) -add_subdirectory_ifdef(CONFIG_MAX17055 max17055) -add_subdirectory_ifdef(CONFIG_MAX17262 max17262) -add_subdirectory_ifdef(CONFIG_MAX30101 max30101) -add_subdirectory_ifdef(CONFIG_MAX31790_SENSOR max31790) -add_subdirectory_ifdef(CONFIG_MAX31855 max31855) -add_subdirectory_ifdef(CONFIG_MAX31865 max31865) -add_subdirectory_ifdef(CONFIG_MAX31875 max31875) -add_subdirectory_ifdef(CONFIG_MAX44009 max44009) -add_subdirectory_ifdef(CONFIG_MAX6675 max6675) add_subdirectory_ifdef(CONFIG_MC3419 mc3419) add_subdirectory_ifdef(CONFIG_MCP9600 mcp9600) add_subdirectory_ifdef(CONFIG_MCP970X mcp970x) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 6f26aafe8ff..5a192a9eeb2 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -84,6 +84,7 @@ comment "Device Drivers" # zephyr-keep-sorted-start source "drivers/sensor/adi/Kconfig" source "drivers/sensor/bosch/Kconfig" +source "drivers/sensor/maxim/Kconfig" source "drivers/sensor/st/Kconfig" # zephyr-keep-sorted-stop @@ -104,7 +105,6 @@ source "drivers/sensor/current_amp/Kconfig" source "drivers/sensor/dht/Kconfig" source "drivers/sensor/dht20/Kconfig" source "drivers/sensor/dps310/Kconfig" -source "drivers/sensor/ds18b20/Kconfig" source "drivers/sensor/ens160/Kconfig" source "drivers/sensor/ens210/Kconfig" source "drivers/sensor/esp32_temp/Kconfig" @@ -135,15 +135,6 @@ source "drivers/sensor/lm35/Kconfig" source "drivers/sensor/lm75/Kconfig" source "drivers/sensor/lm77/Kconfig" source "drivers/sensor/ltrf216a/Kconfig" -source "drivers/sensor/max17055/Kconfig" -source "drivers/sensor/max17262/Kconfig" -source "drivers/sensor/max30101/Kconfig" -source "drivers/sensor/max31790/Kconfig" -source "drivers/sensor/max31855/Kconfig" -source "drivers/sensor/max31865/Kconfig" -source "drivers/sensor/max31875/Kconfig" -source "drivers/sensor/max44009/Kconfig" -source "drivers/sensor/max6675/Kconfig" source "drivers/sensor/mc3419/Kconfig" source "drivers/sensor/mchp_tach_xec/Kconfig" source "drivers/sensor/mcp9600/Kconfig" diff --git a/drivers/sensor/maxim/CMakeLists.txt b/drivers/sensor/maxim/CMakeLists.txt new file mode 100644 index 00000000000..c93ffbb7ada --- /dev/null +++ b/drivers/sensor/maxim/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_DS18B20 ds18b20) +add_subdirectory_ifdef(CONFIG_MAX17055 max17055) +add_subdirectory_ifdef(CONFIG_MAX17262 max17262) +add_subdirectory_ifdef(CONFIG_MAX30101 max30101) +add_subdirectory_ifdef(CONFIG_MAX31790_SENSOR max31790) +add_subdirectory_ifdef(CONFIG_MAX31855 max31855) +add_subdirectory_ifdef(CONFIG_MAX31865 max31865) +add_subdirectory_ifdef(CONFIG_MAX31875 max31875) +add_subdirectory_ifdef(CONFIG_MAX44009 max44009) +add_subdirectory_ifdef(CONFIG_MAX6675 max6675) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/maxim/Kconfig b/drivers/sensor/maxim/Kconfig new file mode 100644 index 00000000000..ada577b05ad --- /dev/null +++ b/drivers/sensor/maxim/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/maxim/ds18b20/Kconfig" +source "drivers/sensor/maxim/max17055/Kconfig" +source "drivers/sensor/maxim/max17262/Kconfig" +source "drivers/sensor/maxim/max30101/Kconfig" +source "drivers/sensor/maxim/max31790/Kconfig" +source "drivers/sensor/maxim/max31855/Kconfig" +source "drivers/sensor/maxim/max31865/Kconfig" +source "drivers/sensor/maxim/max31875/Kconfig" +source "drivers/sensor/maxim/max44009/Kconfig" +source "drivers/sensor/maxim/max6675/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/ds18b20/CMakeLists.txt b/drivers/sensor/maxim/ds18b20/CMakeLists.txt similarity index 100% rename from drivers/sensor/ds18b20/CMakeLists.txt rename to drivers/sensor/maxim/ds18b20/CMakeLists.txt diff --git a/drivers/sensor/ds18b20/Kconfig b/drivers/sensor/maxim/ds18b20/Kconfig similarity index 100% rename from drivers/sensor/ds18b20/Kconfig rename to drivers/sensor/maxim/ds18b20/Kconfig diff --git a/drivers/sensor/ds18b20/ds18b20.c b/drivers/sensor/maxim/ds18b20/ds18b20.c similarity index 100% rename from drivers/sensor/ds18b20/ds18b20.c rename to drivers/sensor/maxim/ds18b20/ds18b20.c diff --git a/drivers/sensor/ds18b20/ds18b20.h b/drivers/sensor/maxim/ds18b20/ds18b20.h similarity index 100% rename from drivers/sensor/ds18b20/ds18b20.h rename to drivers/sensor/maxim/ds18b20/ds18b20.h diff --git a/drivers/sensor/max17055/CMakeLists.txt b/drivers/sensor/maxim/max17055/CMakeLists.txt similarity index 100% rename from drivers/sensor/max17055/CMakeLists.txt rename to drivers/sensor/maxim/max17055/CMakeLists.txt diff --git a/drivers/sensor/max17055/Kconfig b/drivers/sensor/maxim/max17055/Kconfig similarity index 100% rename from drivers/sensor/max17055/Kconfig rename to drivers/sensor/maxim/max17055/Kconfig diff --git a/drivers/sensor/max17055/max17055.c b/drivers/sensor/maxim/max17055/max17055.c similarity index 100% rename from drivers/sensor/max17055/max17055.c rename to drivers/sensor/maxim/max17055/max17055.c diff --git a/drivers/sensor/max17055/max17055.h b/drivers/sensor/maxim/max17055/max17055.h similarity index 100% rename from drivers/sensor/max17055/max17055.h rename to drivers/sensor/maxim/max17055/max17055.h diff --git a/drivers/sensor/max17262/CMakeLists.txt b/drivers/sensor/maxim/max17262/CMakeLists.txt similarity index 100% rename from drivers/sensor/max17262/CMakeLists.txt rename to drivers/sensor/maxim/max17262/CMakeLists.txt diff --git a/drivers/sensor/max17262/Kconfig b/drivers/sensor/maxim/max17262/Kconfig similarity index 100% rename from drivers/sensor/max17262/Kconfig rename to drivers/sensor/maxim/max17262/Kconfig diff --git a/drivers/sensor/max17262/max17262.c b/drivers/sensor/maxim/max17262/max17262.c similarity index 100% rename from drivers/sensor/max17262/max17262.c rename to drivers/sensor/maxim/max17262/max17262.c diff --git a/drivers/sensor/max17262/max17262.h b/drivers/sensor/maxim/max17262/max17262.h similarity index 100% rename from drivers/sensor/max17262/max17262.h rename to drivers/sensor/maxim/max17262/max17262.h diff --git a/drivers/sensor/max30101/CMakeLists.txt b/drivers/sensor/maxim/max30101/CMakeLists.txt similarity index 100% rename from drivers/sensor/max30101/CMakeLists.txt rename to drivers/sensor/maxim/max30101/CMakeLists.txt diff --git a/drivers/sensor/max30101/Kconfig b/drivers/sensor/maxim/max30101/Kconfig similarity index 100% rename from drivers/sensor/max30101/Kconfig rename to drivers/sensor/maxim/max30101/Kconfig diff --git a/drivers/sensor/max30101/max30101.c b/drivers/sensor/maxim/max30101/max30101.c similarity index 100% rename from drivers/sensor/max30101/max30101.c rename to drivers/sensor/maxim/max30101/max30101.c diff --git a/drivers/sensor/max30101/max30101.h b/drivers/sensor/maxim/max30101/max30101.h similarity index 100% rename from drivers/sensor/max30101/max30101.h rename to drivers/sensor/maxim/max30101/max30101.h diff --git a/drivers/sensor/max31790/CMakeLists.txt b/drivers/sensor/maxim/max31790/CMakeLists.txt similarity index 100% rename from drivers/sensor/max31790/CMakeLists.txt rename to drivers/sensor/maxim/max31790/CMakeLists.txt diff --git a/drivers/sensor/max31790/Kconfig b/drivers/sensor/maxim/max31790/Kconfig similarity index 100% rename from drivers/sensor/max31790/Kconfig rename to drivers/sensor/maxim/max31790/Kconfig diff --git a/drivers/sensor/max31790/max31790_fan_fault.c b/drivers/sensor/maxim/max31790/max31790_fan_fault.c similarity index 100% rename from drivers/sensor/max31790/max31790_fan_fault.c rename to drivers/sensor/maxim/max31790/max31790_fan_fault.c diff --git a/drivers/sensor/max31790/max31790_fan_fault.h b/drivers/sensor/maxim/max31790/max31790_fan_fault.h similarity index 100% rename from drivers/sensor/max31790/max31790_fan_fault.h rename to drivers/sensor/maxim/max31790/max31790_fan_fault.h diff --git a/drivers/sensor/max31790/max31790_fan_speed.c b/drivers/sensor/maxim/max31790/max31790_fan_speed.c similarity index 100% rename from drivers/sensor/max31790/max31790_fan_speed.c rename to drivers/sensor/maxim/max31790/max31790_fan_speed.c diff --git a/drivers/sensor/max31790/max31790_fan_speed.h b/drivers/sensor/maxim/max31790/max31790_fan_speed.h similarity index 100% rename from drivers/sensor/max31790/max31790_fan_speed.h rename to drivers/sensor/maxim/max31790/max31790_fan_speed.h diff --git a/drivers/sensor/max31855/CMakeLists.txt b/drivers/sensor/maxim/max31855/CMakeLists.txt similarity index 100% rename from drivers/sensor/max31855/CMakeLists.txt rename to drivers/sensor/maxim/max31855/CMakeLists.txt diff --git a/drivers/sensor/max31855/Kconfig b/drivers/sensor/maxim/max31855/Kconfig similarity index 100% rename from drivers/sensor/max31855/Kconfig rename to drivers/sensor/maxim/max31855/Kconfig diff --git a/drivers/sensor/max31855/max31855.c b/drivers/sensor/maxim/max31855/max31855.c similarity index 100% rename from drivers/sensor/max31855/max31855.c rename to drivers/sensor/maxim/max31855/max31855.c diff --git a/drivers/sensor/max31865/CMakeLists.txt b/drivers/sensor/maxim/max31865/CMakeLists.txt similarity index 100% rename from drivers/sensor/max31865/CMakeLists.txt rename to drivers/sensor/maxim/max31865/CMakeLists.txt diff --git a/drivers/sensor/max31865/Kconfig b/drivers/sensor/maxim/max31865/Kconfig similarity index 100% rename from drivers/sensor/max31865/Kconfig rename to drivers/sensor/maxim/max31865/Kconfig diff --git a/drivers/sensor/max31865/max31865.c b/drivers/sensor/maxim/max31865/max31865.c similarity index 100% rename from drivers/sensor/max31865/max31865.c rename to drivers/sensor/maxim/max31865/max31865.c diff --git a/drivers/sensor/max31865/max31865.h b/drivers/sensor/maxim/max31865/max31865.h similarity index 100% rename from drivers/sensor/max31865/max31865.h rename to drivers/sensor/maxim/max31865/max31865.h diff --git a/drivers/sensor/max31875/CMakeLists.txt b/drivers/sensor/maxim/max31875/CMakeLists.txt similarity index 100% rename from drivers/sensor/max31875/CMakeLists.txt rename to drivers/sensor/maxim/max31875/CMakeLists.txt diff --git a/drivers/sensor/max31875/Kconfig b/drivers/sensor/maxim/max31875/Kconfig similarity index 100% rename from drivers/sensor/max31875/Kconfig rename to drivers/sensor/maxim/max31875/Kconfig diff --git a/drivers/sensor/max31875/max31875.c b/drivers/sensor/maxim/max31875/max31875.c similarity index 100% rename from drivers/sensor/max31875/max31875.c rename to drivers/sensor/maxim/max31875/max31875.c diff --git a/drivers/sensor/max44009/CMakeLists.txt b/drivers/sensor/maxim/max44009/CMakeLists.txt similarity index 100% rename from drivers/sensor/max44009/CMakeLists.txt rename to drivers/sensor/maxim/max44009/CMakeLists.txt diff --git a/drivers/sensor/max44009/Kconfig b/drivers/sensor/maxim/max44009/Kconfig similarity index 100% rename from drivers/sensor/max44009/Kconfig rename to drivers/sensor/maxim/max44009/Kconfig diff --git a/drivers/sensor/max44009/max44009.c b/drivers/sensor/maxim/max44009/max44009.c similarity index 100% rename from drivers/sensor/max44009/max44009.c rename to drivers/sensor/maxim/max44009/max44009.c diff --git a/drivers/sensor/max44009/max44009.h b/drivers/sensor/maxim/max44009/max44009.h similarity index 100% rename from drivers/sensor/max44009/max44009.h rename to drivers/sensor/maxim/max44009/max44009.h diff --git a/drivers/sensor/max6675/CMakeLists.txt b/drivers/sensor/maxim/max6675/CMakeLists.txt similarity index 100% rename from drivers/sensor/max6675/CMakeLists.txt rename to drivers/sensor/maxim/max6675/CMakeLists.txt diff --git a/drivers/sensor/max6675/Kconfig b/drivers/sensor/maxim/max6675/Kconfig similarity index 100% rename from drivers/sensor/max6675/Kconfig rename to drivers/sensor/maxim/max6675/Kconfig diff --git a/drivers/sensor/max6675/max6675.c b/drivers/sensor/maxim/max6675/max6675.c similarity index 100% rename from drivers/sensor/max6675/max6675.c rename to drivers/sensor/maxim/max6675/max6675.c From e09398d5e0b79e1f8fbd2462149c2b1a232e9b19 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Tue, 26 Mar 2024 18:29:08 -0500 Subject: [PATCH 1968/2402] drivers: sensor: microchip: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 6 +----- drivers/sensor/Kconfig | 6 +----- drivers/sensor/microchip/CMakeLists.txt | 10 ++++++++++ drivers/sensor/microchip/Kconfig | 10 ++++++++++ .../{ => microchip}/mchp_tach_xec/CMakeLists.txt | 0 drivers/sensor/{ => microchip}/mchp_tach_xec/Kconfig | 0 .../{ => microchip}/mchp_tach_xec/tach_mchp_xec.c | 0 drivers/sensor/{ => microchip}/mcp9600/CMakeLists.txt | 0 drivers/sensor/{ => microchip}/mcp9600/Kconfig | 0 drivers/sensor/{ => microchip}/mcp9600/mcp9600.c | 0 drivers/sensor/{ => microchip}/mcp970x/CMakeLists.txt | 0 drivers/sensor/{ => microchip}/mcp970x/Kconfig | 0 drivers/sensor/{ => microchip}/mcp970x/mcp970x.c | 0 drivers/sensor/{ => microchip}/mcp9808/CMakeLists.txt | 0 drivers/sensor/{ => microchip}/mcp9808/Kconfig | 0 drivers/sensor/{ => microchip}/mcp9808/mcp9808.c | 0 drivers/sensor/{ => microchip}/mcp9808/mcp9808.h | 0 .../sensor/{ => microchip}/mcp9808/mcp9808_trigger.c | 0 drivers/sensor/{ => microchip}/tcn75a/CMakeLists.txt | 0 drivers/sensor/{ => microchip}/tcn75a/Kconfig | 0 drivers/sensor/{ => microchip}/tcn75a/tcn75a.c | 0 drivers/sensor/{ => microchip}/tcn75a/tcn75a.h | 0 drivers/sensor/{ => microchip}/tcn75a/tcn75a_trigger.c | 0 23 files changed, 22 insertions(+), 10 deletions(-) create mode 100644 drivers/sensor/microchip/CMakeLists.txt create mode 100644 drivers/sensor/microchip/Kconfig rename drivers/sensor/{ => microchip}/mchp_tach_xec/CMakeLists.txt (100%) rename drivers/sensor/{ => microchip}/mchp_tach_xec/Kconfig (100%) rename drivers/sensor/{ => microchip}/mchp_tach_xec/tach_mchp_xec.c (100%) rename drivers/sensor/{ => microchip}/mcp9600/CMakeLists.txt (100%) rename drivers/sensor/{ => microchip}/mcp9600/Kconfig (100%) rename drivers/sensor/{ => microchip}/mcp9600/mcp9600.c (100%) rename drivers/sensor/{ => microchip}/mcp970x/CMakeLists.txt (100%) rename drivers/sensor/{ => microchip}/mcp970x/Kconfig (100%) rename drivers/sensor/{ => microchip}/mcp970x/mcp970x.c (100%) rename drivers/sensor/{ => microchip}/mcp9808/CMakeLists.txt (100%) rename drivers/sensor/{ => microchip}/mcp9808/Kconfig (100%) rename drivers/sensor/{ => microchip}/mcp9808/mcp9808.c (100%) rename drivers/sensor/{ => microchip}/mcp9808/mcp9808.h (100%) rename drivers/sensor/{ => microchip}/mcp9808/mcp9808_trigger.c (100%) rename drivers/sensor/{ => microchip}/tcn75a/CMakeLists.txt (100%) rename drivers/sensor/{ => microchip}/tcn75a/Kconfig (100%) rename drivers/sensor/{ => microchip}/tcn75a/tcn75a.c (100%) rename drivers/sensor/{ => microchip}/tcn75a/tcn75a.h (100%) rename drivers/sensor/{ => microchip}/tcn75a/tcn75a_trigger.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 285f61544e2..0d55e479ae9 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -4,6 +4,7 @@ add_subdirectory(adi) add_subdirectory(bosch) add_subdirectory(maxim) +add_subdirectory(microchip) add_subdirectory(st) # zephyr-keep-sorted-stop @@ -55,9 +56,6 @@ add_subdirectory_ifdef(CONFIG_LM75 lm75) add_subdirectory_ifdef(CONFIG_LM77 lm77) add_subdirectory_ifdef(CONFIG_LTR_F216A ltrf216a) add_subdirectory_ifdef(CONFIG_MC3419 mc3419) -add_subdirectory_ifdef(CONFIG_MCP9600 mcp9600) -add_subdirectory_ifdef(CONFIG_MCP970X mcp970x) -add_subdirectory_ifdef(CONFIG_MCP9808 mcp9808) add_subdirectory_ifdef(CONFIG_MCUX_ACMP mcux_acmp) add_subdirectory_ifdef(CONFIG_MHZ19B mhz19b) add_subdirectory_ifdef(CONFIG_MPR mpr) @@ -90,8 +88,6 @@ add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) add_subdirectory_ifdef(CONFIG_TACH_IT8XXX2 ite_tach_it8xxx2) add_subdirectory_ifdef(CONFIG_TACH_NPCX nuvoton_tach_npcx) -add_subdirectory_ifdef(CONFIG_TACH_XEC mchp_tach_xec) -add_subdirectory_ifdef(CONFIG_TCN75A tcn75a) add_subdirectory_ifdef(CONFIG_TCS3400 tcs3400) add_subdirectory_ifdef(CONFIG_TEMP_KINETIS nxp_kinetis_temp) add_subdirectory_ifdef(CONFIG_TEMP_NRF5 nrf5) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 5a192a9eeb2..5d6aa0e710b 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -85,6 +85,7 @@ comment "Device Drivers" source "drivers/sensor/adi/Kconfig" source "drivers/sensor/bosch/Kconfig" source "drivers/sensor/maxim/Kconfig" +source "drivers/sensor/microchip/Kconfig" source "drivers/sensor/st/Kconfig" # zephyr-keep-sorted-stop @@ -136,10 +137,6 @@ source "drivers/sensor/lm75/Kconfig" source "drivers/sensor/lm77/Kconfig" source "drivers/sensor/ltrf216a/Kconfig" source "drivers/sensor/mc3419/Kconfig" -source "drivers/sensor/mchp_tach_xec/Kconfig" -source "drivers/sensor/mcp9600/Kconfig" -source "drivers/sensor/mcp970x/Kconfig" -source "drivers/sensor/mcp9808/Kconfig" source "drivers/sensor/mcux_acmp/Kconfig" source "drivers/sensor/mhz19b/Kconfig" source "drivers/sensor/mpr/Kconfig" @@ -174,7 +171,6 @@ source "drivers/sensor/si7060/Kconfig" source "drivers/sensor/si7210/Kconfig" source "drivers/sensor/sm351lt/Kconfig" source "drivers/sensor/sx9500/Kconfig" -source "drivers/sensor/tcn75a/Kconfig" source "drivers/sensor/tcs3400/Kconfig" source "drivers/sensor/th02/Kconfig" source "drivers/sensor/ti_hdc/Kconfig" diff --git a/drivers/sensor/microchip/CMakeLists.txt b/drivers/sensor/microchip/CMakeLists.txt new file mode 100644 index 00000000000..f9cb91f8dae --- /dev/null +++ b/drivers/sensor/microchip/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_MCP9600 mcp9600) +add_subdirectory_ifdef(CONFIG_MCP970X mcp970x) +add_subdirectory_ifdef(CONFIG_MCP9808 mcp9808) +add_subdirectory_ifdef(CONFIG_TACH_XEC mchp_tach_xec) +add_subdirectory_ifdef(CONFIG_TCN75A tcn75a) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/microchip/Kconfig b/drivers/sensor/microchip/Kconfig new file mode 100644 index 00000000000..7b57487dcd0 --- /dev/null +++ b/drivers/sensor/microchip/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/microchip/mchp_tach_xec/Kconfig" +source "drivers/sensor/microchip/mcp9600/Kconfig" +source "drivers/sensor/microchip/mcp970x/Kconfig" +source "drivers/sensor/microchip/mcp9808/Kconfig" +source "drivers/sensor/microchip/tcn75a/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/mchp_tach_xec/CMakeLists.txt b/drivers/sensor/microchip/mchp_tach_xec/CMakeLists.txt similarity index 100% rename from drivers/sensor/mchp_tach_xec/CMakeLists.txt rename to drivers/sensor/microchip/mchp_tach_xec/CMakeLists.txt diff --git a/drivers/sensor/mchp_tach_xec/Kconfig b/drivers/sensor/microchip/mchp_tach_xec/Kconfig similarity index 100% rename from drivers/sensor/mchp_tach_xec/Kconfig rename to drivers/sensor/microchip/mchp_tach_xec/Kconfig diff --git a/drivers/sensor/mchp_tach_xec/tach_mchp_xec.c b/drivers/sensor/microchip/mchp_tach_xec/tach_mchp_xec.c similarity index 100% rename from drivers/sensor/mchp_tach_xec/tach_mchp_xec.c rename to drivers/sensor/microchip/mchp_tach_xec/tach_mchp_xec.c diff --git a/drivers/sensor/mcp9600/CMakeLists.txt b/drivers/sensor/microchip/mcp9600/CMakeLists.txt similarity index 100% rename from drivers/sensor/mcp9600/CMakeLists.txt rename to drivers/sensor/microchip/mcp9600/CMakeLists.txt diff --git a/drivers/sensor/mcp9600/Kconfig b/drivers/sensor/microchip/mcp9600/Kconfig similarity index 100% rename from drivers/sensor/mcp9600/Kconfig rename to drivers/sensor/microchip/mcp9600/Kconfig diff --git a/drivers/sensor/mcp9600/mcp9600.c b/drivers/sensor/microchip/mcp9600/mcp9600.c similarity index 100% rename from drivers/sensor/mcp9600/mcp9600.c rename to drivers/sensor/microchip/mcp9600/mcp9600.c diff --git a/drivers/sensor/mcp970x/CMakeLists.txt b/drivers/sensor/microchip/mcp970x/CMakeLists.txt similarity index 100% rename from drivers/sensor/mcp970x/CMakeLists.txt rename to drivers/sensor/microchip/mcp970x/CMakeLists.txt diff --git a/drivers/sensor/mcp970x/Kconfig b/drivers/sensor/microchip/mcp970x/Kconfig similarity index 100% rename from drivers/sensor/mcp970x/Kconfig rename to drivers/sensor/microchip/mcp970x/Kconfig diff --git a/drivers/sensor/mcp970x/mcp970x.c b/drivers/sensor/microchip/mcp970x/mcp970x.c similarity index 100% rename from drivers/sensor/mcp970x/mcp970x.c rename to drivers/sensor/microchip/mcp970x/mcp970x.c diff --git a/drivers/sensor/mcp9808/CMakeLists.txt b/drivers/sensor/microchip/mcp9808/CMakeLists.txt similarity index 100% rename from drivers/sensor/mcp9808/CMakeLists.txt rename to drivers/sensor/microchip/mcp9808/CMakeLists.txt diff --git a/drivers/sensor/mcp9808/Kconfig b/drivers/sensor/microchip/mcp9808/Kconfig similarity index 100% rename from drivers/sensor/mcp9808/Kconfig rename to drivers/sensor/microchip/mcp9808/Kconfig diff --git a/drivers/sensor/mcp9808/mcp9808.c b/drivers/sensor/microchip/mcp9808/mcp9808.c similarity index 100% rename from drivers/sensor/mcp9808/mcp9808.c rename to drivers/sensor/microchip/mcp9808/mcp9808.c diff --git a/drivers/sensor/mcp9808/mcp9808.h b/drivers/sensor/microchip/mcp9808/mcp9808.h similarity index 100% rename from drivers/sensor/mcp9808/mcp9808.h rename to drivers/sensor/microchip/mcp9808/mcp9808.h diff --git a/drivers/sensor/mcp9808/mcp9808_trigger.c b/drivers/sensor/microchip/mcp9808/mcp9808_trigger.c similarity index 100% rename from drivers/sensor/mcp9808/mcp9808_trigger.c rename to drivers/sensor/microchip/mcp9808/mcp9808_trigger.c diff --git a/drivers/sensor/tcn75a/CMakeLists.txt b/drivers/sensor/microchip/tcn75a/CMakeLists.txt similarity index 100% rename from drivers/sensor/tcn75a/CMakeLists.txt rename to drivers/sensor/microchip/tcn75a/CMakeLists.txt diff --git a/drivers/sensor/tcn75a/Kconfig b/drivers/sensor/microchip/tcn75a/Kconfig similarity index 100% rename from drivers/sensor/tcn75a/Kconfig rename to drivers/sensor/microchip/tcn75a/Kconfig diff --git a/drivers/sensor/tcn75a/tcn75a.c b/drivers/sensor/microchip/tcn75a/tcn75a.c similarity index 100% rename from drivers/sensor/tcn75a/tcn75a.c rename to drivers/sensor/microchip/tcn75a/tcn75a.c diff --git a/drivers/sensor/tcn75a/tcn75a.h b/drivers/sensor/microchip/tcn75a/tcn75a.h similarity index 100% rename from drivers/sensor/tcn75a/tcn75a.h rename to drivers/sensor/microchip/tcn75a/tcn75a.h diff --git a/drivers/sensor/tcn75a/tcn75a_trigger.c b/drivers/sensor/microchip/tcn75a/tcn75a_trigger.c similarity index 100% rename from drivers/sensor/tcn75a/tcn75a_trigger.c rename to drivers/sensor/microchip/tcn75a/tcn75a_trigger.c From 1cfa6d918a661ad3ebaa297ce4c0feac1df357a3 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Tue, 26 Mar 2024 18:37:54 -0500 Subject: [PATCH 1969/2402] drivers: sensor: nxp: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 8 +------- drivers/sensor/Kconfig | 8 +------- drivers/sensor/nxp/CMakeLists.txt | 12 ++++++++++++ drivers/sensor/nxp/Kconfig | 12 ++++++++++++ drivers/sensor/{ => nxp}/fxas21002/CMakeLists.txt | 0 drivers/sensor/{ => nxp}/fxas21002/Kconfig | 0 drivers/sensor/{ => nxp}/fxas21002/fxas21002.c | 0 drivers/sensor/{ => nxp}/fxas21002/fxas21002.h | 0 .../sensor/{ => nxp}/fxas21002/fxas21002_trigger.c | 0 drivers/sensor/{ => nxp}/fxos8700/CMakeLists.txt | 0 drivers/sensor/{ => nxp}/fxos8700/Kconfig | 0 drivers/sensor/{ => nxp}/fxos8700/fxos8700.c | 0 drivers/sensor/{ => nxp}/fxos8700/fxos8700.h | 0 drivers/sensor/{ => nxp}/fxos8700/fxos8700_trigger.c | 0 drivers/sensor/{ => nxp}/mcux_acmp/CMakeLists.txt | 0 drivers/sensor/{ => nxp}/mcux_acmp/Kconfig | 0 drivers/sensor/{ => nxp}/mcux_acmp/mcux_acmp.c | 0 .../sensor/{ => nxp}/nxp_kinetis_temp/CMakeLists.txt | 0 drivers/sensor/{ => nxp}/nxp_kinetis_temp/Kconfig | 0 .../sensor/{ => nxp}/nxp_kinetis_temp/temp_kinetis.c | 0 drivers/sensor/{ => nxp}/nxp_tempmon/CMakeLists.txt | 0 drivers/sensor/{ => nxp}/nxp_tempmon/Kconfig | 0 drivers/sensor/{ => nxp}/nxp_tempmon/nxp_tempmon.c | 0 drivers/sensor/{ => nxp}/qdec_mcux/CMakeLists.txt | 0 drivers/sensor/{ => nxp}/qdec_mcux/Kconfig | 0 drivers/sensor/{ => nxp}/qdec_mcux/qdec_mcux.c | 0 drivers/sensor/{ => nxp}/qdec_nxp_s32/CMakeLists.txt | 0 drivers/sensor/{ => nxp}/qdec_nxp_s32/Kconfig | 0 drivers/sensor/{ => nxp}/qdec_nxp_s32/qdec_nxp_s32.c | 0 29 files changed, 26 insertions(+), 14 deletions(-) create mode 100644 drivers/sensor/nxp/CMakeLists.txt create mode 100644 drivers/sensor/nxp/Kconfig rename drivers/sensor/{ => nxp}/fxas21002/CMakeLists.txt (100%) rename drivers/sensor/{ => nxp}/fxas21002/Kconfig (100%) rename drivers/sensor/{ => nxp}/fxas21002/fxas21002.c (100%) rename drivers/sensor/{ => nxp}/fxas21002/fxas21002.h (100%) rename drivers/sensor/{ => nxp}/fxas21002/fxas21002_trigger.c (100%) rename drivers/sensor/{ => nxp}/fxos8700/CMakeLists.txt (100%) rename drivers/sensor/{ => nxp}/fxos8700/Kconfig (100%) rename drivers/sensor/{ => nxp}/fxos8700/fxos8700.c (100%) rename drivers/sensor/{ => nxp}/fxos8700/fxos8700.h (100%) rename drivers/sensor/{ => nxp}/fxos8700/fxos8700_trigger.c (100%) rename drivers/sensor/{ => nxp}/mcux_acmp/CMakeLists.txt (100%) rename drivers/sensor/{ => nxp}/mcux_acmp/Kconfig (100%) rename drivers/sensor/{ => nxp}/mcux_acmp/mcux_acmp.c (100%) rename drivers/sensor/{ => nxp}/nxp_kinetis_temp/CMakeLists.txt (100%) rename drivers/sensor/{ => nxp}/nxp_kinetis_temp/Kconfig (100%) rename drivers/sensor/{ => nxp}/nxp_kinetis_temp/temp_kinetis.c (100%) rename drivers/sensor/{ => nxp}/nxp_tempmon/CMakeLists.txt (100%) rename drivers/sensor/{ => nxp}/nxp_tempmon/Kconfig (100%) rename drivers/sensor/{ => nxp}/nxp_tempmon/nxp_tempmon.c (100%) rename drivers/sensor/{ => nxp}/qdec_mcux/CMakeLists.txt (100%) rename drivers/sensor/{ => nxp}/qdec_mcux/Kconfig (100%) rename drivers/sensor/{ => nxp}/qdec_mcux/qdec_mcux.c (100%) rename drivers/sensor/{ => nxp}/qdec_nxp_s32/CMakeLists.txt (100%) rename drivers/sensor/{ => nxp}/qdec_nxp_s32/Kconfig (100%) rename drivers/sensor/{ => nxp}/qdec_nxp_s32/qdec_nxp_s32.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 0d55e479ae9..c039735412e 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -5,6 +5,7 @@ add_subdirectory(adi) add_subdirectory(bosch) add_subdirectory(maxim) add_subdirectory(microchip) +add_subdirectory(nxp) add_subdirectory(st) # zephyr-keep-sorted-stop @@ -33,8 +34,6 @@ add_subdirectory_ifdef(CONFIG_EXPLORIR_M explorir_m) add_subdirectory_ifdef(CONFIG_F75303 f75303) add_subdirectory_ifdef(CONFIG_FCX_MLDX5 fcx_mldx5) add_subdirectory_ifdef(CONFIG_FDC2X1X fdc2x1x) -add_subdirectory_ifdef(CONFIG_FXAS21002 fxas21002) -add_subdirectory_ifdef(CONFIG_FXOS8700 fxos8700) add_subdirectory_ifdef(CONFIG_GROVE_SENSORS grove) add_subdirectory_ifdef(CONFIG_GROW_R502A grow_r502a) add_subdirectory_ifdef(CONFIG_HM330X hm330x) @@ -56,7 +55,6 @@ add_subdirectory_ifdef(CONFIG_LM75 lm75) add_subdirectory_ifdef(CONFIG_LM77 lm77) add_subdirectory_ifdef(CONFIG_LTR_F216A ltrf216a) add_subdirectory_ifdef(CONFIG_MC3419 mc3419) -add_subdirectory_ifdef(CONFIG_MCUX_ACMP mcux_acmp) add_subdirectory_ifdef(CONFIG_MHZ19B mhz19b) add_subdirectory_ifdef(CONFIG_MPR mpr) add_subdirectory_ifdef(CONFIG_MPU6050 tdk/mpu6050) @@ -65,12 +63,9 @@ add_subdirectory_ifdef(CONFIG_MS5607 ms5607) add_subdirectory_ifdef(CONFIG_MS5837 ms5837) add_subdirectory_ifdef(CONFIG_NPM1300_CHARGER npm1300_charger) add_subdirectory_ifdef(CONFIG_NTC_THERMISTOR ntc_thermistor) -add_subdirectory_ifdef(CONFIG_NXP_TEMPMON nxp_tempmon) add_subdirectory_ifdef(CONFIG_OPT3001 opt3001) add_subdirectory_ifdef(CONFIG_PCNT_ESP32 pcnt_esp32) add_subdirectory_ifdef(CONFIG_PMS7003 pms7003) -add_subdirectory_ifdef(CONFIG_QDEC_MCUX qdec_mcux) -add_subdirectory_ifdef(CONFIG_QDEC_NXP_S32 qdec_nxp_s32) add_subdirectory_ifdef(CONFIG_QDEC_NRFX qdec_nrfx) add_subdirectory_ifdef(CONFIG_QDEC_SAM qdec_sam) add_subdirectory_ifdef(CONFIG_RPI_PICO_TEMP rpi_pico_temp) @@ -89,7 +84,6 @@ add_subdirectory_ifdef(CONFIG_SX9500 sx9500) add_subdirectory_ifdef(CONFIG_TACH_IT8XXX2 ite_tach_it8xxx2) add_subdirectory_ifdef(CONFIG_TACH_NPCX nuvoton_tach_npcx) add_subdirectory_ifdef(CONFIG_TCS3400 tcs3400) -add_subdirectory_ifdef(CONFIG_TEMP_KINETIS nxp_kinetis_temp) add_subdirectory_ifdef(CONFIG_TEMP_NRF5 nrf5) add_subdirectory_ifdef(CONFIG_TH02 th02) add_subdirectory_ifdef(CONFIG_TI_HDC ti_hdc) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 5d6aa0e710b..8a5fc07d798 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -86,6 +86,7 @@ source "drivers/sensor/adi/Kconfig" source "drivers/sensor/bosch/Kconfig" source "drivers/sensor/maxim/Kconfig" source "drivers/sensor/microchip/Kconfig" +source "drivers/sensor/nxp/Kconfig" source "drivers/sensor/st/Kconfig" # zephyr-keep-sorted-stop @@ -113,8 +114,6 @@ source "drivers/sensor/explorir_m/Kconfig" source "drivers/sensor/f75303/Kconfig" source "drivers/sensor/fcx_mldx5/Kconfig" source "drivers/sensor/fdc2x1x/Kconfig" -source "drivers/sensor/fxas21002/Kconfig" -source "drivers/sensor/fxos8700/Kconfig" source "drivers/sensor/grove/Kconfig" source "drivers/sensor/grow_r502a/Kconfig" source "drivers/sensor/hm330x/Kconfig" @@ -137,7 +136,6 @@ source "drivers/sensor/lm75/Kconfig" source "drivers/sensor/lm77/Kconfig" source "drivers/sensor/ltrf216a/Kconfig" source "drivers/sensor/mc3419/Kconfig" -source "drivers/sensor/mcux_acmp/Kconfig" source "drivers/sensor/mhz19b/Kconfig" source "drivers/sensor/mpr/Kconfig" source "drivers/sensor/tdk/mpu6050/Kconfig" @@ -149,13 +147,9 @@ source "drivers/sensor/nrf5/Kconfig" source "drivers/sensor/ntc_thermistor/Kconfig" source "drivers/sensor/nuvoton_adc_cmp_npcx/Kconfig" source "drivers/sensor/nuvoton_tach_npcx/Kconfig" -source "drivers/sensor/nxp_kinetis_temp/Kconfig" -source "drivers/sensor/nxp_tempmon/Kconfig" source "drivers/sensor/opt3001/Kconfig" source "drivers/sensor/pcnt_esp32/Kconfig" source "drivers/sensor/pms7003/Kconfig" -source "drivers/sensor/qdec_mcux/Kconfig" -source "drivers/sensor/qdec_nxp_s32/Kconfig" source "drivers/sensor/qdec_nrfx/Kconfig" source "drivers/sensor/qdec_sam/Kconfig" source "drivers/sensor/rpi_pico_temp/Kconfig" diff --git a/drivers/sensor/nxp/CMakeLists.txt b/drivers/sensor/nxp/CMakeLists.txt new file mode 100644 index 00000000000..21e7825187f --- /dev/null +++ b/drivers/sensor/nxp/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_FXAS21002 fxas21002) +add_subdirectory_ifdef(CONFIG_FXOS8700 fxos8700) +add_subdirectory_ifdef(CONFIG_MCUX_ACMP mcux_acmp) +add_subdirectory_ifdef(CONFIG_NXP_TEMPMON nxp_tempmon) +add_subdirectory_ifdef(CONFIG_QDEC_MCUX qdec_mcux) +add_subdirectory_ifdef(CONFIG_QDEC_NXP_S32 qdec_nxp_s32) +add_subdirectory_ifdef(CONFIG_TEMP_KINETIS nxp_kinetis_temp) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/nxp/Kconfig b/drivers/sensor/nxp/Kconfig new file mode 100644 index 00000000000..bf1565580aa --- /dev/null +++ b/drivers/sensor/nxp/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/nxp/fxas21002/Kconfig" +source "drivers/sensor/nxp/fxos8700/Kconfig" +source "drivers/sensor/nxp/mcux_acmp/Kconfig" +source "drivers/sensor/nxp/nxp_kinetis_temp/Kconfig" +source "drivers/sensor/nxp/nxp_tempmon/Kconfig" +source "drivers/sensor/nxp/qdec_mcux/Kconfig" +source "drivers/sensor/nxp/qdec_nxp_s32/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/fxas21002/CMakeLists.txt b/drivers/sensor/nxp/fxas21002/CMakeLists.txt similarity index 100% rename from drivers/sensor/fxas21002/CMakeLists.txt rename to drivers/sensor/nxp/fxas21002/CMakeLists.txt diff --git a/drivers/sensor/fxas21002/Kconfig b/drivers/sensor/nxp/fxas21002/Kconfig similarity index 100% rename from drivers/sensor/fxas21002/Kconfig rename to drivers/sensor/nxp/fxas21002/Kconfig diff --git a/drivers/sensor/fxas21002/fxas21002.c b/drivers/sensor/nxp/fxas21002/fxas21002.c similarity index 100% rename from drivers/sensor/fxas21002/fxas21002.c rename to drivers/sensor/nxp/fxas21002/fxas21002.c diff --git a/drivers/sensor/fxas21002/fxas21002.h b/drivers/sensor/nxp/fxas21002/fxas21002.h similarity index 100% rename from drivers/sensor/fxas21002/fxas21002.h rename to drivers/sensor/nxp/fxas21002/fxas21002.h diff --git a/drivers/sensor/fxas21002/fxas21002_trigger.c b/drivers/sensor/nxp/fxas21002/fxas21002_trigger.c similarity index 100% rename from drivers/sensor/fxas21002/fxas21002_trigger.c rename to drivers/sensor/nxp/fxas21002/fxas21002_trigger.c diff --git a/drivers/sensor/fxos8700/CMakeLists.txt b/drivers/sensor/nxp/fxos8700/CMakeLists.txt similarity index 100% rename from drivers/sensor/fxos8700/CMakeLists.txt rename to drivers/sensor/nxp/fxos8700/CMakeLists.txt diff --git a/drivers/sensor/fxos8700/Kconfig b/drivers/sensor/nxp/fxos8700/Kconfig similarity index 100% rename from drivers/sensor/fxos8700/Kconfig rename to drivers/sensor/nxp/fxos8700/Kconfig diff --git a/drivers/sensor/fxos8700/fxos8700.c b/drivers/sensor/nxp/fxos8700/fxos8700.c similarity index 100% rename from drivers/sensor/fxos8700/fxos8700.c rename to drivers/sensor/nxp/fxos8700/fxos8700.c diff --git a/drivers/sensor/fxos8700/fxos8700.h b/drivers/sensor/nxp/fxos8700/fxos8700.h similarity index 100% rename from drivers/sensor/fxos8700/fxos8700.h rename to drivers/sensor/nxp/fxos8700/fxos8700.h diff --git a/drivers/sensor/fxos8700/fxos8700_trigger.c b/drivers/sensor/nxp/fxos8700/fxos8700_trigger.c similarity index 100% rename from drivers/sensor/fxos8700/fxos8700_trigger.c rename to drivers/sensor/nxp/fxos8700/fxos8700_trigger.c diff --git a/drivers/sensor/mcux_acmp/CMakeLists.txt b/drivers/sensor/nxp/mcux_acmp/CMakeLists.txt similarity index 100% rename from drivers/sensor/mcux_acmp/CMakeLists.txt rename to drivers/sensor/nxp/mcux_acmp/CMakeLists.txt diff --git a/drivers/sensor/mcux_acmp/Kconfig b/drivers/sensor/nxp/mcux_acmp/Kconfig similarity index 100% rename from drivers/sensor/mcux_acmp/Kconfig rename to drivers/sensor/nxp/mcux_acmp/Kconfig diff --git a/drivers/sensor/mcux_acmp/mcux_acmp.c b/drivers/sensor/nxp/mcux_acmp/mcux_acmp.c similarity index 100% rename from drivers/sensor/mcux_acmp/mcux_acmp.c rename to drivers/sensor/nxp/mcux_acmp/mcux_acmp.c diff --git a/drivers/sensor/nxp_kinetis_temp/CMakeLists.txt b/drivers/sensor/nxp/nxp_kinetis_temp/CMakeLists.txt similarity index 100% rename from drivers/sensor/nxp_kinetis_temp/CMakeLists.txt rename to drivers/sensor/nxp/nxp_kinetis_temp/CMakeLists.txt diff --git a/drivers/sensor/nxp_kinetis_temp/Kconfig b/drivers/sensor/nxp/nxp_kinetis_temp/Kconfig similarity index 100% rename from drivers/sensor/nxp_kinetis_temp/Kconfig rename to drivers/sensor/nxp/nxp_kinetis_temp/Kconfig diff --git a/drivers/sensor/nxp_kinetis_temp/temp_kinetis.c b/drivers/sensor/nxp/nxp_kinetis_temp/temp_kinetis.c similarity index 100% rename from drivers/sensor/nxp_kinetis_temp/temp_kinetis.c rename to drivers/sensor/nxp/nxp_kinetis_temp/temp_kinetis.c diff --git a/drivers/sensor/nxp_tempmon/CMakeLists.txt b/drivers/sensor/nxp/nxp_tempmon/CMakeLists.txt similarity index 100% rename from drivers/sensor/nxp_tempmon/CMakeLists.txt rename to drivers/sensor/nxp/nxp_tempmon/CMakeLists.txt diff --git a/drivers/sensor/nxp_tempmon/Kconfig b/drivers/sensor/nxp/nxp_tempmon/Kconfig similarity index 100% rename from drivers/sensor/nxp_tempmon/Kconfig rename to drivers/sensor/nxp/nxp_tempmon/Kconfig diff --git a/drivers/sensor/nxp_tempmon/nxp_tempmon.c b/drivers/sensor/nxp/nxp_tempmon/nxp_tempmon.c similarity index 100% rename from drivers/sensor/nxp_tempmon/nxp_tempmon.c rename to drivers/sensor/nxp/nxp_tempmon/nxp_tempmon.c diff --git a/drivers/sensor/qdec_mcux/CMakeLists.txt b/drivers/sensor/nxp/qdec_mcux/CMakeLists.txt similarity index 100% rename from drivers/sensor/qdec_mcux/CMakeLists.txt rename to drivers/sensor/nxp/qdec_mcux/CMakeLists.txt diff --git a/drivers/sensor/qdec_mcux/Kconfig b/drivers/sensor/nxp/qdec_mcux/Kconfig similarity index 100% rename from drivers/sensor/qdec_mcux/Kconfig rename to drivers/sensor/nxp/qdec_mcux/Kconfig diff --git a/drivers/sensor/qdec_mcux/qdec_mcux.c b/drivers/sensor/nxp/qdec_mcux/qdec_mcux.c similarity index 100% rename from drivers/sensor/qdec_mcux/qdec_mcux.c rename to drivers/sensor/nxp/qdec_mcux/qdec_mcux.c diff --git a/drivers/sensor/qdec_nxp_s32/CMakeLists.txt b/drivers/sensor/nxp/qdec_nxp_s32/CMakeLists.txt similarity index 100% rename from drivers/sensor/qdec_nxp_s32/CMakeLists.txt rename to drivers/sensor/nxp/qdec_nxp_s32/CMakeLists.txt diff --git a/drivers/sensor/qdec_nxp_s32/Kconfig b/drivers/sensor/nxp/qdec_nxp_s32/Kconfig similarity index 100% rename from drivers/sensor/qdec_nxp_s32/Kconfig rename to drivers/sensor/nxp/qdec_nxp_s32/Kconfig diff --git a/drivers/sensor/qdec_nxp_s32/qdec_nxp_s32.c b/drivers/sensor/nxp/qdec_nxp_s32/qdec_nxp_s32.c similarity index 100% rename from drivers/sensor/qdec_nxp_s32/qdec_nxp_s32.c rename to drivers/sensor/nxp/qdec_nxp_s32/qdec_nxp_s32.c From a2ef60e9bcd2caf7859203f73fbd5a2f5dbcba9d Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Tue, 26 Mar 2024 18:44:45 -0500 Subject: [PATCH 1970/2402] drivers: sensor: silabs: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 5 +---- drivers/sensor/Kconfig | 5 +---- drivers/sensor/silabs/CMakeLists.txt | 9 +++++++++ drivers/sensor/silabs/Kconfig | 9 +++++++++ drivers/sensor/{ => silabs}/si7006/CMakeLists.txt | 0 drivers/sensor/{ => silabs}/si7006/Kconfig | 0 drivers/sensor/{ => silabs}/si7006/si7006.c | 0 drivers/sensor/{ => silabs}/si7006/si7006.h | 0 drivers/sensor/{ => silabs}/si7055/CMakeLists.txt | 0 drivers/sensor/{ => silabs}/si7055/Kconfig | 0 drivers/sensor/{ => silabs}/si7055/si7055.c | 0 drivers/sensor/{ => silabs}/si7055/si7055.h | 0 drivers/sensor/{ => silabs}/si7060/CMakeLists.txt | 0 drivers/sensor/{ => silabs}/si7060/Kconfig | 0 drivers/sensor/{ => silabs}/si7060/si7060.c | 0 drivers/sensor/{ => silabs}/si7060/si7060.h | 0 drivers/sensor/{ => silabs}/si7210/CMakeLists.txt | 0 drivers/sensor/{ => silabs}/si7210/Kconfig | 0 drivers/sensor/{ => silabs}/si7210/si7210.c | 0 19 files changed, 20 insertions(+), 8 deletions(-) create mode 100644 drivers/sensor/silabs/CMakeLists.txt create mode 100644 drivers/sensor/silabs/Kconfig rename drivers/sensor/{ => silabs}/si7006/CMakeLists.txt (100%) rename drivers/sensor/{ => silabs}/si7006/Kconfig (100%) rename drivers/sensor/{ => silabs}/si7006/si7006.c (100%) rename drivers/sensor/{ => silabs}/si7006/si7006.h (100%) rename drivers/sensor/{ => silabs}/si7055/CMakeLists.txt (100%) rename drivers/sensor/{ => silabs}/si7055/Kconfig (100%) rename drivers/sensor/{ => silabs}/si7055/si7055.c (100%) rename drivers/sensor/{ => silabs}/si7055/si7055.h (100%) rename drivers/sensor/{ => silabs}/si7060/CMakeLists.txt (100%) rename drivers/sensor/{ => silabs}/si7060/Kconfig (100%) rename drivers/sensor/{ => silabs}/si7060/si7060.c (100%) rename drivers/sensor/{ => silabs}/si7060/si7060.h (100%) rename drivers/sensor/{ => silabs}/si7210/CMakeLists.txt (100%) rename drivers/sensor/{ => silabs}/si7210/Kconfig (100%) rename drivers/sensor/{ => silabs}/si7210/si7210.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index c039735412e..508fcc14cf0 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -6,6 +6,7 @@ add_subdirectory(bosch) add_subdirectory(maxim) add_subdirectory(microchip) add_subdirectory(nxp) +add_subdirectory(silabs) add_subdirectory(st) # zephyr-keep-sorted-stop @@ -75,10 +76,6 @@ add_subdirectory_ifdef(CONFIG_SGP40 sgp40) add_subdirectory_ifdef(CONFIG_SHT3XD sht3xd) add_subdirectory_ifdef(CONFIG_SHT4X sht4x) add_subdirectory_ifdef(CONFIG_SHTCX shtcx) -add_subdirectory_ifdef(CONFIG_SI7006 si7006) -add_subdirectory_ifdef(CONFIG_SI7055 si7055) -add_subdirectory_ifdef(CONFIG_SI7060 si7060) -add_subdirectory_ifdef(CONFIG_SI7210 si7210) add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) add_subdirectory_ifdef(CONFIG_TACH_IT8XXX2 ite_tach_it8xxx2) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 8a5fc07d798..e3fa2b9d40f 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -87,6 +87,7 @@ source "drivers/sensor/bosch/Kconfig" source "drivers/sensor/maxim/Kconfig" source "drivers/sensor/microchip/Kconfig" source "drivers/sensor/nxp/Kconfig" +source "drivers/sensor/silabs/Kconfig" source "drivers/sensor/st/Kconfig" # zephyr-keep-sorted-stop @@ -159,10 +160,6 @@ source "drivers/sensor/sgp40/Kconfig" source "drivers/sensor/sht3xd/Kconfig" source "drivers/sensor/sht4x/Kconfig" source "drivers/sensor/shtcx/Kconfig" -source "drivers/sensor/si7006/Kconfig" -source "drivers/sensor/si7055/Kconfig" -source "drivers/sensor/si7060/Kconfig" -source "drivers/sensor/si7210/Kconfig" source "drivers/sensor/sm351lt/Kconfig" source "drivers/sensor/sx9500/Kconfig" source "drivers/sensor/tcs3400/Kconfig" diff --git a/drivers/sensor/silabs/CMakeLists.txt b/drivers/sensor/silabs/CMakeLists.txt new file mode 100644 index 00000000000..5bbefbb7f1a --- /dev/null +++ b/drivers/sensor/silabs/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_SI7006 si7006) +add_subdirectory_ifdef(CONFIG_SI7055 si7055) +add_subdirectory_ifdef(CONFIG_SI7060 si7060) +add_subdirectory_ifdef(CONFIG_SI7210 si7210) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/silabs/Kconfig b/drivers/sensor/silabs/Kconfig new file mode 100644 index 00000000000..79a1d38c281 --- /dev/null +++ b/drivers/sensor/silabs/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/silabs/si7006/Kconfig" +source "drivers/sensor/silabs/si7055/Kconfig" +source "drivers/sensor/silabs/si7060/Kconfig" +source "drivers/sensor/silabs/si7210/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/si7006/CMakeLists.txt b/drivers/sensor/silabs/si7006/CMakeLists.txt similarity index 100% rename from drivers/sensor/si7006/CMakeLists.txt rename to drivers/sensor/silabs/si7006/CMakeLists.txt diff --git a/drivers/sensor/si7006/Kconfig b/drivers/sensor/silabs/si7006/Kconfig similarity index 100% rename from drivers/sensor/si7006/Kconfig rename to drivers/sensor/silabs/si7006/Kconfig diff --git a/drivers/sensor/si7006/si7006.c b/drivers/sensor/silabs/si7006/si7006.c similarity index 100% rename from drivers/sensor/si7006/si7006.c rename to drivers/sensor/silabs/si7006/si7006.c diff --git a/drivers/sensor/si7006/si7006.h b/drivers/sensor/silabs/si7006/si7006.h similarity index 100% rename from drivers/sensor/si7006/si7006.h rename to drivers/sensor/silabs/si7006/si7006.h diff --git a/drivers/sensor/si7055/CMakeLists.txt b/drivers/sensor/silabs/si7055/CMakeLists.txt similarity index 100% rename from drivers/sensor/si7055/CMakeLists.txt rename to drivers/sensor/silabs/si7055/CMakeLists.txt diff --git a/drivers/sensor/si7055/Kconfig b/drivers/sensor/silabs/si7055/Kconfig similarity index 100% rename from drivers/sensor/si7055/Kconfig rename to drivers/sensor/silabs/si7055/Kconfig diff --git a/drivers/sensor/si7055/si7055.c b/drivers/sensor/silabs/si7055/si7055.c similarity index 100% rename from drivers/sensor/si7055/si7055.c rename to drivers/sensor/silabs/si7055/si7055.c diff --git a/drivers/sensor/si7055/si7055.h b/drivers/sensor/silabs/si7055/si7055.h similarity index 100% rename from drivers/sensor/si7055/si7055.h rename to drivers/sensor/silabs/si7055/si7055.h diff --git a/drivers/sensor/si7060/CMakeLists.txt b/drivers/sensor/silabs/si7060/CMakeLists.txt similarity index 100% rename from drivers/sensor/si7060/CMakeLists.txt rename to drivers/sensor/silabs/si7060/CMakeLists.txt diff --git a/drivers/sensor/si7060/Kconfig b/drivers/sensor/silabs/si7060/Kconfig similarity index 100% rename from drivers/sensor/si7060/Kconfig rename to drivers/sensor/silabs/si7060/Kconfig diff --git a/drivers/sensor/si7060/si7060.c b/drivers/sensor/silabs/si7060/si7060.c similarity index 100% rename from drivers/sensor/si7060/si7060.c rename to drivers/sensor/silabs/si7060/si7060.c diff --git a/drivers/sensor/si7060/si7060.h b/drivers/sensor/silabs/si7060/si7060.h similarity index 100% rename from drivers/sensor/si7060/si7060.h rename to drivers/sensor/silabs/si7060/si7060.h diff --git a/drivers/sensor/si7210/CMakeLists.txt b/drivers/sensor/silabs/si7210/CMakeLists.txt similarity index 100% rename from drivers/sensor/si7210/CMakeLists.txt rename to drivers/sensor/silabs/si7210/CMakeLists.txt diff --git a/drivers/sensor/si7210/Kconfig b/drivers/sensor/silabs/si7210/Kconfig similarity index 100% rename from drivers/sensor/si7210/Kconfig rename to drivers/sensor/silabs/si7210/Kconfig diff --git a/drivers/sensor/si7210/si7210.c b/drivers/sensor/silabs/si7210/si7210.c similarity index 100% rename from drivers/sensor/si7210/si7210.c rename to drivers/sensor/silabs/si7210/si7210.c From b2b2d704f4874975f35594c65049168d7aff791c Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Tue, 26 Mar 2024 18:57:09 -0500 Subject: [PATCH 1971/2402] drivers: sensor: ti: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 15 +-------------- drivers/sensor/Kconfig | 15 +-------------- drivers/sensor/ti/CMakeLists.txt | 19 +++++++++++++++++++ drivers/sensor/ti/Kconfig | 19 +++++++++++++++++++ .../sensor/{ => ti}/bq274xx/CMakeLists.txt | 0 drivers/sensor/{ => ti}/bq274xx/Kconfig | 0 drivers/sensor/{ => ti}/bq274xx/bq274xx.c | 0 drivers/sensor/{ => ti}/bq274xx/bq274xx.h | 0 .../sensor/{ => ti}/bq274xx/bq274xx_trigger.c | 0 .../sensor/{ => ti}/fdc2x1x/CMakeLists.txt | 0 drivers/sensor/{ => ti}/fdc2x1x/Kconfig | 0 drivers/sensor/{ => ti}/fdc2x1x/fdc2x1x.c | 0 drivers/sensor/{ => ti}/fdc2x1x/fdc2x1x.h | 0 .../sensor/{ => ti}/fdc2x1x/fdc2x1x_trigger.c | 0 drivers/sensor/{ => ti}/ina219/CMakeLists.txt | 0 drivers/sensor/{ => ti}/ina219/Kconfig | 0 drivers/sensor/{ => ti}/ina219/ina219.c | 0 drivers/sensor/{ => ti}/ina219/ina219.h | 0 drivers/sensor/{ => ti}/ina23x/CMakeLists.txt | 0 drivers/sensor/{ => ti}/ina23x/Kconfig | 0 drivers/sensor/{ => ti}/ina23x/ina230.c | 0 drivers/sensor/{ => ti}/ina23x/ina230.h | 0 .../sensor/{ => ti}/ina23x/ina230_trigger.c | 0 drivers/sensor/{ => ti}/ina23x/ina237.c | 0 drivers/sensor/{ => ti}/ina23x/ina237.h | 0 .../sensor/{ => ti}/ina23x/ina23x_common.c | 0 .../sensor/{ => ti}/ina23x/ina23x_common.h | 0 .../sensor/{ => ti}/ina23x/ina23x_trigger.c | 0 .../sensor/{ => ti}/ina23x/ina23x_trigger.h | 0 .../sensor/{ => ti}/ina3221/CMakeLists.txt | 0 drivers/sensor/{ => ti}/ina3221/Kconfig | 0 drivers/sensor/{ => ti}/ina3221/ina3221.c | 0 drivers/sensor/{ => ti}/ina3221/ina3221.h | 0 .../sensor/{ => ti}/opt3001/CMakeLists.txt | 0 drivers/sensor/{ => ti}/opt3001/Kconfig | 0 drivers/sensor/{ => ti}/opt3001/opt3001.c | 0 drivers/sensor/{ => ti}/opt3001/opt3001.h | 0 drivers/sensor/{ => ti}/ti_hdc/CMakeLists.txt | 0 drivers/sensor/{ => ti}/ti_hdc/Kconfig | 0 drivers/sensor/{ => ti}/ti_hdc/ti_hdc.c | 0 drivers/sensor/{ => ti}/ti_hdc/ti_hdc.h | 0 .../sensor/{ => ti}/ti_hdc20xx/CMakeLists.txt | 0 drivers/sensor/{ => ti}/ti_hdc20xx/Kconfig | 0 .../sensor/{ => ti}/ti_hdc20xx/ti_hdc20xx.c | 0 .../sensor/{ => ti}/tmag5170/CMakeLists.txt | 0 drivers/sensor/{ => ti}/tmag5170/Kconfig | 0 drivers/sensor/{ => ti}/tmag5170/tmag5170.c | 0 drivers/sensor/{ => ti}/tmag5170/tmag5170.h | 0 .../{ => ti}/tmag5170/tmag5170_trigger.c | 0 .../sensor/{ => ti}/tmag5273/CMakeLists.txt | 0 drivers/sensor/{ => ti}/tmag5273/Kconfig | 0 drivers/sensor/{ => ti}/tmag5273/tmag5273.c | 0 drivers/sensor/{ => ti}/tmag5273/tmag5273.h | 0 drivers/sensor/{ => ti}/tmp007/CMakeLists.txt | 0 drivers/sensor/{ => ti}/tmp007/Kconfig | 0 drivers/sensor/{ => ti}/tmp007/tmp007.c | 0 drivers/sensor/{ => ti}/tmp007/tmp007.h | 0 .../sensor/{ => ti}/tmp007/tmp007_trigger.c | 0 drivers/sensor/{ => ti}/tmp108/CMakeLists.txt | 0 drivers/sensor/{ => ti}/tmp108/Kconfig | 0 drivers/sensor/{ => ti}/tmp108/tmp108.c | 0 drivers/sensor/{ => ti}/tmp108/tmp108.h | 0 .../sensor/{ => ti}/tmp108/tmp108_trigger.c | 0 drivers/sensor/{ => ti}/tmp112/CMakeLists.txt | 0 drivers/sensor/{ => ti}/tmp112/Kconfig | 0 drivers/sensor/{ => ti}/tmp112/tmp112.c | 0 drivers/sensor/{ => ti}/tmp112/tmp112.h | 0 drivers/sensor/{ => ti}/tmp116/CMakeLists.txt | 0 drivers/sensor/{ => ti}/tmp116/Kconfig | 0 drivers/sensor/{ => ti}/tmp116/tmp116.c | 0 drivers/sensor/{ => ti}/tmp116/tmp116.h | 0 tests/drivers/sensor/ina230/CMakeLists.txt | 2 +- tests/drivers/sensor/ina237/CMakeLists.txt | 2 +- 73 files changed, 42 insertions(+), 30 deletions(-) create mode 100644 drivers/sensor/ti/CMakeLists.txt create mode 100644 drivers/sensor/ti/Kconfig rename drivers/sensor/{ => ti}/bq274xx/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/bq274xx/Kconfig (100%) rename drivers/sensor/{ => ti}/bq274xx/bq274xx.c (100%) rename drivers/sensor/{ => ti}/bq274xx/bq274xx.h (100%) rename drivers/sensor/{ => ti}/bq274xx/bq274xx_trigger.c (100%) rename drivers/sensor/{ => ti}/fdc2x1x/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/fdc2x1x/Kconfig (100%) rename drivers/sensor/{ => ti}/fdc2x1x/fdc2x1x.c (100%) rename drivers/sensor/{ => ti}/fdc2x1x/fdc2x1x.h (100%) rename drivers/sensor/{ => ti}/fdc2x1x/fdc2x1x_trigger.c (100%) rename drivers/sensor/{ => ti}/ina219/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/ina219/Kconfig (100%) rename drivers/sensor/{ => ti}/ina219/ina219.c (100%) rename drivers/sensor/{ => ti}/ina219/ina219.h (100%) rename drivers/sensor/{ => ti}/ina23x/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/ina23x/Kconfig (100%) rename drivers/sensor/{ => ti}/ina23x/ina230.c (100%) rename drivers/sensor/{ => ti}/ina23x/ina230.h (100%) rename drivers/sensor/{ => ti}/ina23x/ina230_trigger.c (100%) rename drivers/sensor/{ => ti}/ina23x/ina237.c (100%) rename drivers/sensor/{ => ti}/ina23x/ina237.h (100%) rename drivers/sensor/{ => ti}/ina23x/ina23x_common.c (100%) rename drivers/sensor/{ => ti}/ina23x/ina23x_common.h (100%) rename drivers/sensor/{ => ti}/ina23x/ina23x_trigger.c (100%) rename drivers/sensor/{ => ti}/ina23x/ina23x_trigger.h (100%) rename drivers/sensor/{ => ti}/ina3221/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/ina3221/Kconfig (100%) rename drivers/sensor/{ => ti}/ina3221/ina3221.c (100%) rename drivers/sensor/{ => ti}/ina3221/ina3221.h (100%) rename drivers/sensor/{ => ti}/opt3001/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/opt3001/Kconfig (100%) rename drivers/sensor/{ => ti}/opt3001/opt3001.c (100%) rename drivers/sensor/{ => ti}/opt3001/opt3001.h (100%) rename drivers/sensor/{ => ti}/ti_hdc/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/ti_hdc/Kconfig (100%) rename drivers/sensor/{ => ti}/ti_hdc/ti_hdc.c (100%) rename drivers/sensor/{ => ti}/ti_hdc/ti_hdc.h (100%) rename drivers/sensor/{ => ti}/ti_hdc20xx/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/ti_hdc20xx/Kconfig (100%) rename drivers/sensor/{ => ti}/ti_hdc20xx/ti_hdc20xx.c (100%) rename drivers/sensor/{ => ti}/tmag5170/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/tmag5170/Kconfig (100%) rename drivers/sensor/{ => ti}/tmag5170/tmag5170.c (100%) rename drivers/sensor/{ => ti}/tmag5170/tmag5170.h (100%) rename drivers/sensor/{ => ti}/tmag5170/tmag5170_trigger.c (100%) rename drivers/sensor/{ => ti}/tmag5273/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/tmag5273/Kconfig (100%) rename drivers/sensor/{ => ti}/tmag5273/tmag5273.c (100%) rename drivers/sensor/{ => ti}/tmag5273/tmag5273.h (100%) rename drivers/sensor/{ => ti}/tmp007/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/tmp007/Kconfig (100%) rename drivers/sensor/{ => ti}/tmp007/tmp007.c (100%) rename drivers/sensor/{ => ti}/tmp007/tmp007.h (100%) rename drivers/sensor/{ => ti}/tmp007/tmp007_trigger.c (100%) rename drivers/sensor/{ => ti}/tmp108/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/tmp108/Kconfig (100%) rename drivers/sensor/{ => ti}/tmp108/tmp108.c (100%) rename drivers/sensor/{ => ti}/tmp108/tmp108.h (100%) rename drivers/sensor/{ => ti}/tmp108/tmp108_trigger.c (100%) rename drivers/sensor/{ => ti}/tmp112/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/tmp112/Kconfig (100%) rename drivers/sensor/{ => ti}/tmp112/tmp112.c (100%) rename drivers/sensor/{ => ti}/tmp112/tmp112.h (100%) rename drivers/sensor/{ => ti}/tmp116/CMakeLists.txt (100%) rename drivers/sensor/{ => ti}/tmp116/Kconfig (100%) rename drivers/sensor/{ => ti}/tmp116/tmp116.c (100%) rename drivers/sensor/{ => ti}/tmp116/tmp116.h (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 508fcc14cf0..01218c6db88 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -8,6 +8,7 @@ add_subdirectory(microchip) add_subdirectory(nxp) add_subdirectory(silabs) add_subdirectory(st) +add_subdirectory(ti) # zephyr-keep-sorted-stop add_subdirectory_ifdef(CONFIG_A01NYUB a01nyub) @@ -22,7 +23,6 @@ add_subdirectory_ifdef(CONFIG_AMS_IAQ_CORE ams_iAQcore) add_subdirectory_ifdef(CONFIG_APDS9960 apds9960) add_subdirectory_ifdef(CONFIG_BD8LB600FS_DIAGNOSTICS bd8lb600fs) add_subdirectory_ifdef(CONFIG_BH1750 bh1750) -add_subdirectory_ifdef(CONFIG_BQ274XX bq274xx) add_subdirectory_ifdef(CONFIG_CCS811 ccs811) add_subdirectory_ifdef(CONFIG_CURRENT_AMP current_amp) add_subdirectory_ifdef(CONFIG_DHT dht) @@ -34,7 +34,6 @@ add_subdirectory_ifdef(CONFIG_ESP32_TEMP esp32_temp) add_subdirectory_ifdef(CONFIG_EXPLORIR_M explorir_m) add_subdirectory_ifdef(CONFIG_F75303 f75303) add_subdirectory_ifdef(CONFIG_FCX_MLDX5 fcx_mldx5) -add_subdirectory_ifdef(CONFIG_FDC2X1X fdc2x1x) add_subdirectory_ifdef(CONFIG_GROVE_SENSORS grove) add_subdirectory_ifdef(CONFIG_GROW_R502A grow_r502a) add_subdirectory_ifdef(CONFIG_HM330X hm330x) @@ -45,9 +44,6 @@ add_subdirectory_ifdef(CONFIG_ICM42605 tdk/icm42605) add_subdirectory_ifdef(CONFIG_ICM42670 tdk/icm42670) add_subdirectory_ifdef(CONFIG_ICM42688 tdk/icm42688) add_subdirectory_ifdef(CONFIG_ICP10125 tdk/icp10125) -add_subdirectory_ifdef(CONFIG_INA219 ina219) -add_subdirectory_ifdef(CONFIG_INA23X ina23x) -add_subdirectory_ifdef(CONFIG_INA3221 ina3221) add_subdirectory_ifdef(CONFIG_IST8310 ist8310) add_subdirectory_ifdef(CONFIG_ISL29035 isl29035) add_subdirectory_ifdef(CONFIG_ITDS wsen_itds) @@ -64,7 +60,6 @@ add_subdirectory_ifdef(CONFIG_MS5607 ms5607) add_subdirectory_ifdef(CONFIG_MS5837 ms5837) add_subdirectory_ifdef(CONFIG_NPM1300_CHARGER npm1300_charger) add_subdirectory_ifdef(CONFIG_NTC_THERMISTOR ntc_thermistor) -add_subdirectory_ifdef(CONFIG_OPT3001 opt3001) add_subdirectory_ifdef(CONFIG_PCNT_ESP32 pcnt_esp32) add_subdirectory_ifdef(CONFIG_PMS7003 pms7003) add_subdirectory_ifdef(CONFIG_QDEC_NRFX qdec_nrfx) @@ -83,15 +78,7 @@ add_subdirectory_ifdef(CONFIG_TACH_NPCX nuvoton_tach_npcx) add_subdirectory_ifdef(CONFIG_TCS3400 tcs3400) add_subdirectory_ifdef(CONFIG_TEMP_NRF5 nrf5) add_subdirectory_ifdef(CONFIG_TH02 th02) -add_subdirectory_ifdef(CONFIG_TI_HDC ti_hdc) -add_subdirectory_ifdef(CONFIG_TI_HDC20XX ti_hdc20xx) -add_subdirectory_ifdef(CONFIG_TMAG5170 tmag5170) -add_subdirectory_ifdef(CONFIG_TMAG5273 tmag5273) add_subdirectory_ifdef(CONFIG_TMD2620 tmd2620) -add_subdirectory_ifdef(CONFIG_TMP007 tmp007) -add_subdirectory_ifdef(CONFIG_TMP108 tmp108) -add_subdirectory_ifdef(CONFIG_TMP112 tmp112) -add_subdirectory_ifdef(CONFIG_TMP116 tmp116) add_subdirectory_ifdef(CONFIG_TSL2540 tsl2540) add_subdirectory_ifdef(CONFIG_TSL2561 tsl2561) add_subdirectory_ifdef(CONFIG_TSL2591 tsl2591) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index e3fa2b9d40f..e5a3bbb313e 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -89,6 +89,7 @@ source "drivers/sensor/microchip/Kconfig" source "drivers/sensor/nxp/Kconfig" source "drivers/sensor/silabs/Kconfig" source "drivers/sensor/st/Kconfig" +source "drivers/sensor/ti/Kconfig" # zephyr-keep-sorted-stop source "drivers/sensor/a01nyub/Kconfig" @@ -102,7 +103,6 @@ source "drivers/sensor/ams_iAQcore/Kconfig" source "drivers/sensor/apds9960/Kconfig" source "drivers/sensor/bd8lb600fs/Kconfig" source "drivers/sensor/bh1750/Kconfig" -source "drivers/sensor/bq274xx/Kconfig" source "drivers/sensor/ccs811/Kconfig" source "drivers/sensor/current_amp/Kconfig" source "drivers/sensor/dht/Kconfig" @@ -114,7 +114,6 @@ source "drivers/sensor/esp32_temp/Kconfig" source "drivers/sensor/explorir_m/Kconfig" source "drivers/sensor/f75303/Kconfig" source "drivers/sensor/fcx_mldx5/Kconfig" -source "drivers/sensor/fdc2x1x/Kconfig" source "drivers/sensor/grove/Kconfig" source "drivers/sensor/grow_r502a/Kconfig" source "drivers/sensor/hm330x/Kconfig" @@ -125,9 +124,6 @@ source "drivers/sensor/tdk/icm42605/Kconfig" source "drivers/sensor/tdk/icm42670/Kconfig" source "drivers/sensor/tdk/icm42688/Kconfig" source "drivers/sensor/tdk/icp10125/Kconfig" -source "drivers/sensor/ina219/Kconfig" -source "drivers/sensor/ina23x/Kconfig" -source "drivers/sensor/ina3221/Kconfig" source "drivers/sensor/isl29035/Kconfig" source "drivers/sensor/ist8310/Kconfig" source "drivers/sensor/ite_tach_it8xxx2/Kconfig" @@ -148,7 +144,6 @@ source "drivers/sensor/nrf5/Kconfig" source "drivers/sensor/ntc_thermistor/Kconfig" source "drivers/sensor/nuvoton_adc_cmp_npcx/Kconfig" source "drivers/sensor/nuvoton_tach_npcx/Kconfig" -source "drivers/sensor/opt3001/Kconfig" source "drivers/sensor/pcnt_esp32/Kconfig" source "drivers/sensor/pms7003/Kconfig" source "drivers/sensor/qdec_nrfx/Kconfig" @@ -164,15 +159,7 @@ source "drivers/sensor/sm351lt/Kconfig" source "drivers/sensor/sx9500/Kconfig" source "drivers/sensor/tcs3400/Kconfig" source "drivers/sensor/th02/Kconfig" -source "drivers/sensor/ti_hdc/Kconfig" -source "drivers/sensor/ti_hdc20xx/Kconfig" -source "drivers/sensor/tmag5170/Kconfig" -source "drivers/sensor/tmag5273/Kconfig" source "drivers/sensor/tmd2620/Kconfig" -source "drivers/sensor/tmp007/Kconfig" -source "drivers/sensor/tmp108/Kconfig" -source "drivers/sensor/tmp112/Kconfig" -source "drivers/sensor/tmp116/Kconfig" source "drivers/sensor/tsl2540/Kconfig" source "drivers/sensor/tsl2561/Kconfig" source "drivers/sensor/tsl2591/Kconfig" diff --git a/drivers/sensor/ti/CMakeLists.txt b/drivers/sensor/ti/CMakeLists.txt new file mode 100644 index 00000000000..39c7af3042f --- /dev/null +++ b/drivers/sensor/ti/CMakeLists.txt @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_BQ274XX bq274xx) +add_subdirectory_ifdef(CONFIG_FDC2X1X fdc2x1x) +add_subdirectory_ifdef(CONFIG_INA219 ina219) +add_subdirectory_ifdef(CONFIG_INA23X ina23x) +add_subdirectory_ifdef(CONFIG_INA3221 ina3221) +add_subdirectory_ifdef(CONFIG_OPT3001 opt3001) +add_subdirectory_ifdef(CONFIG_TI_HDC ti_hdc) +add_subdirectory_ifdef(CONFIG_TI_HDC20XX ti_hdc20xx) +add_subdirectory_ifdef(CONFIG_TMAG5170 tmag5170) +add_subdirectory_ifdef(CONFIG_TMAG5273 tmag5273) +add_subdirectory_ifdef(CONFIG_TMP007 tmp007) +add_subdirectory_ifdef(CONFIG_TMP108 tmp108) +add_subdirectory_ifdef(CONFIG_TMP112 tmp112) +add_subdirectory_ifdef(CONFIG_TMP116 tmp116) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/ti/Kconfig b/drivers/sensor/ti/Kconfig new file mode 100644 index 00000000000..713c8f2f099 --- /dev/null +++ b/drivers/sensor/ti/Kconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/ti/bq274xx/Kconfig" +source "drivers/sensor/ti/fdc2x1x/Kconfig" +source "drivers/sensor/ti/ina219/Kconfig" +source "drivers/sensor/ti/ina23x/Kconfig" +source "drivers/sensor/ti/ina3221/Kconfig" +source "drivers/sensor/ti/opt3001/Kconfig" +source "drivers/sensor/ti/ti_hdc/Kconfig" +source "drivers/sensor/ti/ti_hdc20xx/Kconfig" +source "drivers/sensor/ti/tmag5170/Kconfig" +source "drivers/sensor/ti/tmag5273/Kconfig" +source "drivers/sensor/ti/tmp007/Kconfig" +source "drivers/sensor/ti/tmp108/Kconfig" +source "drivers/sensor/ti/tmp112/Kconfig" +source "drivers/sensor/ti/tmp116/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/bq274xx/CMakeLists.txt b/drivers/sensor/ti/bq274xx/CMakeLists.txt similarity index 100% rename from drivers/sensor/bq274xx/CMakeLists.txt rename to drivers/sensor/ti/bq274xx/CMakeLists.txt diff --git a/drivers/sensor/bq274xx/Kconfig b/drivers/sensor/ti/bq274xx/Kconfig similarity index 100% rename from drivers/sensor/bq274xx/Kconfig rename to drivers/sensor/ti/bq274xx/Kconfig diff --git a/drivers/sensor/bq274xx/bq274xx.c b/drivers/sensor/ti/bq274xx/bq274xx.c similarity index 100% rename from drivers/sensor/bq274xx/bq274xx.c rename to drivers/sensor/ti/bq274xx/bq274xx.c diff --git a/drivers/sensor/bq274xx/bq274xx.h b/drivers/sensor/ti/bq274xx/bq274xx.h similarity index 100% rename from drivers/sensor/bq274xx/bq274xx.h rename to drivers/sensor/ti/bq274xx/bq274xx.h diff --git a/drivers/sensor/bq274xx/bq274xx_trigger.c b/drivers/sensor/ti/bq274xx/bq274xx_trigger.c similarity index 100% rename from drivers/sensor/bq274xx/bq274xx_trigger.c rename to drivers/sensor/ti/bq274xx/bq274xx_trigger.c diff --git a/drivers/sensor/fdc2x1x/CMakeLists.txt b/drivers/sensor/ti/fdc2x1x/CMakeLists.txt similarity index 100% rename from drivers/sensor/fdc2x1x/CMakeLists.txt rename to drivers/sensor/ti/fdc2x1x/CMakeLists.txt diff --git a/drivers/sensor/fdc2x1x/Kconfig b/drivers/sensor/ti/fdc2x1x/Kconfig similarity index 100% rename from drivers/sensor/fdc2x1x/Kconfig rename to drivers/sensor/ti/fdc2x1x/Kconfig diff --git a/drivers/sensor/fdc2x1x/fdc2x1x.c b/drivers/sensor/ti/fdc2x1x/fdc2x1x.c similarity index 100% rename from drivers/sensor/fdc2x1x/fdc2x1x.c rename to drivers/sensor/ti/fdc2x1x/fdc2x1x.c diff --git a/drivers/sensor/fdc2x1x/fdc2x1x.h b/drivers/sensor/ti/fdc2x1x/fdc2x1x.h similarity index 100% rename from drivers/sensor/fdc2x1x/fdc2x1x.h rename to drivers/sensor/ti/fdc2x1x/fdc2x1x.h diff --git a/drivers/sensor/fdc2x1x/fdc2x1x_trigger.c b/drivers/sensor/ti/fdc2x1x/fdc2x1x_trigger.c similarity index 100% rename from drivers/sensor/fdc2x1x/fdc2x1x_trigger.c rename to drivers/sensor/ti/fdc2x1x/fdc2x1x_trigger.c diff --git a/drivers/sensor/ina219/CMakeLists.txt b/drivers/sensor/ti/ina219/CMakeLists.txt similarity index 100% rename from drivers/sensor/ina219/CMakeLists.txt rename to drivers/sensor/ti/ina219/CMakeLists.txt diff --git a/drivers/sensor/ina219/Kconfig b/drivers/sensor/ti/ina219/Kconfig similarity index 100% rename from drivers/sensor/ina219/Kconfig rename to drivers/sensor/ti/ina219/Kconfig diff --git a/drivers/sensor/ina219/ina219.c b/drivers/sensor/ti/ina219/ina219.c similarity index 100% rename from drivers/sensor/ina219/ina219.c rename to drivers/sensor/ti/ina219/ina219.c diff --git a/drivers/sensor/ina219/ina219.h b/drivers/sensor/ti/ina219/ina219.h similarity index 100% rename from drivers/sensor/ina219/ina219.h rename to drivers/sensor/ti/ina219/ina219.h diff --git a/drivers/sensor/ina23x/CMakeLists.txt b/drivers/sensor/ti/ina23x/CMakeLists.txt similarity index 100% rename from drivers/sensor/ina23x/CMakeLists.txt rename to drivers/sensor/ti/ina23x/CMakeLists.txt diff --git a/drivers/sensor/ina23x/Kconfig b/drivers/sensor/ti/ina23x/Kconfig similarity index 100% rename from drivers/sensor/ina23x/Kconfig rename to drivers/sensor/ti/ina23x/Kconfig diff --git a/drivers/sensor/ina23x/ina230.c b/drivers/sensor/ti/ina23x/ina230.c similarity index 100% rename from drivers/sensor/ina23x/ina230.c rename to drivers/sensor/ti/ina23x/ina230.c diff --git a/drivers/sensor/ina23x/ina230.h b/drivers/sensor/ti/ina23x/ina230.h similarity index 100% rename from drivers/sensor/ina23x/ina230.h rename to drivers/sensor/ti/ina23x/ina230.h diff --git a/drivers/sensor/ina23x/ina230_trigger.c b/drivers/sensor/ti/ina23x/ina230_trigger.c similarity index 100% rename from drivers/sensor/ina23x/ina230_trigger.c rename to drivers/sensor/ti/ina23x/ina230_trigger.c diff --git a/drivers/sensor/ina23x/ina237.c b/drivers/sensor/ti/ina23x/ina237.c similarity index 100% rename from drivers/sensor/ina23x/ina237.c rename to drivers/sensor/ti/ina23x/ina237.c diff --git a/drivers/sensor/ina23x/ina237.h b/drivers/sensor/ti/ina23x/ina237.h similarity index 100% rename from drivers/sensor/ina23x/ina237.h rename to drivers/sensor/ti/ina23x/ina237.h diff --git a/drivers/sensor/ina23x/ina23x_common.c b/drivers/sensor/ti/ina23x/ina23x_common.c similarity index 100% rename from drivers/sensor/ina23x/ina23x_common.c rename to drivers/sensor/ti/ina23x/ina23x_common.c diff --git a/drivers/sensor/ina23x/ina23x_common.h b/drivers/sensor/ti/ina23x/ina23x_common.h similarity index 100% rename from drivers/sensor/ina23x/ina23x_common.h rename to drivers/sensor/ti/ina23x/ina23x_common.h diff --git a/drivers/sensor/ina23x/ina23x_trigger.c b/drivers/sensor/ti/ina23x/ina23x_trigger.c similarity index 100% rename from drivers/sensor/ina23x/ina23x_trigger.c rename to drivers/sensor/ti/ina23x/ina23x_trigger.c diff --git a/drivers/sensor/ina23x/ina23x_trigger.h b/drivers/sensor/ti/ina23x/ina23x_trigger.h similarity index 100% rename from drivers/sensor/ina23x/ina23x_trigger.h rename to drivers/sensor/ti/ina23x/ina23x_trigger.h diff --git a/drivers/sensor/ina3221/CMakeLists.txt b/drivers/sensor/ti/ina3221/CMakeLists.txt similarity index 100% rename from drivers/sensor/ina3221/CMakeLists.txt rename to drivers/sensor/ti/ina3221/CMakeLists.txt diff --git a/drivers/sensor/ina3221/Kconfig b/drivers/sensor/ti/ina3221/Kconfig similarity index 100% rename from drivers/sensor/ina3221/Kconfig rename to drivers/sensor/ti/ina3221/Kconfig diff --git a/drivers/sensor/ina3221/ina3221.c b/drivers/sensor/ti/ina3221/ina3221.c similarity index 100% rename from drivers/sensor/ina3221/ina3221.c rename to drivers/sensor/ti/ina3221/ina3221.c diff --git a/drivers/sensor/ina3221/ina3221.h b/drivers/sensor/ti/ina3221/ina3221.h similarity index 100% rename from drivers/sensor/ina3221/ina3221.h rename to drivers/sensor/ti/ina3221/ina3221.h diff --git a/drivers/sensor/opt3001/CMakeLists.txt b/drivers/sensor/ti/opt3001/CMakeLists.txt similarity index 100% rename from drivers/sensor/opt3001/CMakeLists.txt rename to drivers/sensor/ti/opt3001/CMakeLists.txt diff --git a/drivers/sensor/opt3001/Kconfig b/drivers/sensor/ti/opt3001/Kconfig similarity index 100% rename from drivers/sensor/opt3001/Kconfig rename to drivers/sensor/ti/opt3001/Kconfig diff --git a/drivers/sensor/opt3001/opt3001.c b/drivers/sensor/ti/opt3001/opt3001.c similarity index 100% rename from drivers/sensor/opt3001/opt3001.c rename to drivers/sensor/ti/opt3001/opt3001.c diff --git a/drivers/sensor/opt3001/opt3001.h b/drivers/sensor/ti/opt3001/opt3001.h similarity index 100% rename from drivers/sensor/opt3001/opt3001.h rename to drivers/sensor/ti/opt3001/opt3001.h diff --git a/drivers/sensor/ti_hdc/CMakeLists.txt b/drivers/sensor/ti/ti_hdc/CMakeLists.txt similarity index 100% rename from drivers/sensor/ti_hdc/CMakeLists.txt rename to drivers/sensor/ti/ti_hdc/CMakeLists.txt diff --git a/drivers/sensor/ti_hdc/Kconfig b/drivers/sensor/ti/ti_hdc/Kconfig similarity index 100% rename from drivers/sensor/ti_hdc/Kconfig rename to drivers/sensor/ti/ti_hdc/Kconfig diff --git a/drivers/sensor/ti_hdc/ti_hdc.c b/drivers/sensor/ti/ti_hdc/ti_hdc.c similarity index 100% rename from drivers/sensor/ti_hdc/ti_hdc.c rename to drivers/sensor/ti/ti_hdc/ti_hdc.c diff --git a/drivers/sensor/ti_hdc/ti_hdc.h b/drivers/sensor/ti/ti_hdc/ti_hdc.h similarity index 100% rename from drivers/sensor/ti_hdc/ti_hdc.h rename to drivers/sensor/ti/ti_hdc/ti_hdc.h diff --git a/drivers/sensor/ti_hdc20xx/CMakeLists.txt b/drivers/sensor/ti/ti_hdc20xx/CMakeLists.txt similarity index 100% rename from drivers/sensor/ti_hdc20xx/CMakeLists.txt rename to drivers/sensor/ti/ti_hdc20xx/CMakeLists.txt diff --git a/drivers/sensor/ti_hdc20xx/Kconfig b/drivers/sensor/ti/ti_hdc20xx/Kconfig similarity index 100% rename from drivers/sensor/ti_hdc20xx/Kconfig rename to drivers/sensor/ti/ti_hdc20xx/Kconfig diff --git a/drivers/sensor/ti_hdc20xx/ti_hdc20xx.c b/drivers/sensor/ti/ti_hdc20xx/ti_hdc20xx.c similarity index 100% rename from drivers/sensor/ti_hdc20xx/ti_hdc20xx.c rename to drivers/sensor/ti/ti_hdc20xx/ti_hdc20xx.c diff --git a/drivers/sensor/tmag5170/CMakeLists.txt b/drivers/sensor/ti/tmag5170/CMakeLists.txt similarity index 100% rename from drivers/sensor/tmag5170/CMakeLists.txt rename to drivers/sensor/ti/tmag5170/CMakeLists.txt diff --git a/drivers/sensor/tmag5170/Kconfig b/drivers/sensor/ti/tmag5170/Kconfig similarity index 100% rename from drivers/sensor/tmag5170/Kconfig rename to drivers/sensor/ti/tmag5170/Kconfig diff --git a/drivers/sensor/tmag5170/tmag5170.c b/drivers/sensor/ti/tmag5170/tmag5170.c similarity index 100% rename from drivers/sensor/tmag5170/tmag5170.c rename to drivers/sensor/ti/tmag5170/tmag5170.c diff --git a/drivers/sensor/tmag5170/tmag5170.h b/drivers/sensor/ti/tmag5170/tmag5170.h similarity index 100% rename from drivers/sensor/tmag5170/tmag5170.h rename to drivers/sensor/ti/tmag5170/tmag5170.h diff --git a/drivers/sensor/tmag5170/tmag5170_trigger.c b/drivers/sensor/ti/tmag5170/tmag5170_trigger.c similarity index 100% rename from drivers/sensor/tmag5170/tmag5170_trigger.c rename to drivers/sensor/ti/tmag5170/tmag5170_trigger.c diff --git a/drivers/sensor/tmag5273/CMakeLists.txt b/drivers/sensor/ti/tmag5273/CMakeLists.txt similarity index 100% rename from drivers/sensor/tmag5273/CMakeLists.txt rename to drivers/sensor/ti/tmag5273/CMakeLists.txt diff --git a/drivers/sensor/tmag5273/Kconfig b/drivers/sensor/ti/tmag5273/Kconfig similarity index 100% rename from drivers/sensor/tmag5273/Kconfig rename to drivers/sensor/ti/tmag5273/Kconfig diff --git a/drivers/sensor/tmag5273/tmag5273.c b/drivers/sensor/ti/tmag5273/tmag5273.c similarity index 100% rename from drivers/sensor/tmag5273/tmag5273.c rename to drivers/sensor/ti/tmag5273/tmag5273.c diff --git a/drivers/sensor/tmag5273/tmag5273.h b/drivers/sensor/ti/tmag5273/tmag5273.h similarity index 100% rename from drivers/sensor/tmag5273/tmag5273.h rename to drivers/sensor/ti/tmag5273/tmag5273.h diff --git a/drivers/sensor/tmp007/CMakeLists.txt b/drivers/sensor/ti/tmp007/CMakeLists.txt similarity index 100% rename from drivers/sensor/tmp007/CMakeLists.txt rename to drivers/sensor/ti/tmp007/CMakeLists.txt diff --git a/drivers/sensor/tmp007/Kconfig b/drivers/sensor/ti/tmp007/Kconfig similarity index 100% rename from drivers/sensor/tmp007/Kconfig rename to drivers/sensor/ti/tmp007/Kconfig diff --git a/drivers/sensor/tmp007/tmp007.c b/drivers/sensor/ti/tmp007/tmp007.c similarity index 100% rename from drivers/sensor/tmp007/tmp007.c rename to drivers/sensor/ti/tmp007/tmp007.c diff --git a/drivers/sensor/tmp007/tmp007.h b/drivers/sensor/ti/tmp007/tmp007.h similarity index 100% rename from drivers/sensor/tmp007/tmp007.h rename to drivers/sensor/ti/tmp007/tmp007.h diff --git a/drivers/sensor/tmp007/tmp007_trigger.c b/drivers/sensor/ti/tmp007/tmp007_trigger.c similarity index 100% rename from drivers/sensor/tmp007/tmp007_trigger.c rename to drivers/sensor/ti/tmp007/tmp007_trigger.c diff --git a/drivers/sensor/tmp108/CMakeLists.txt b/drivers/sensor/ti/tmp108/CMakeLists.txt similarity index 100% rename from drivers/sensor/tmp108/CMakeLists.txt rename to drivers/sensor/ti/tmp108/CMakeLists.txt diff --git a/drivers/sensor/tmp108/Kconfig b/drivers/sensor/ti/tmp108/Kconfig similarity index 100% rename from drivers/sensor/tmp108/Kconfig rename to drivers/sensor/ti/tmp108/Kconfig diff --git a/drivers/sensor/tmp108/tmp108.c b/drivers/sensor/ti/tmp108/tmp108.c similarity index 100% rename from drivers/sensor/tmp108/tmp108.c rename to drivers/sensor/ti/tmp108/tmp108.c diff --git a/drivers/sensor/tmp108/tmp108.h b/drivers/sensor/ti/tmp108/tmp108.h similarity index 100% rename from drivers/sensor/tmp108/tmp108.h rename to drivers/sensor/ti/tmp108/tmp108.h diff --git a/drivers/sensor/tmp108/tmp108_trigger.c b/drivers/sensor/ti/tmp108/tmp108_trigger.c similarity index 100% rename from drivers/sensor/tmp108/tmp108_trigger.c rename to drivers/sensor/ti/tmp108/tmp108_trigger.c diff --git a/drivers/sensor/tmp112/CMakeLists.txt b/drivers/sensor/ti/tmp112/CMakeLists.txt similarity index 100% rename from drivers/sensor/tmp112/CMakeLists.txt rename to drivers/sensor/ti/tmp112/CMakeLists.txt diff --git a/drivers/sensor/tmp112/Kconfig b/drivers/sensor/ti/tmp112/Kconfig similarity index 100% rename from drivers/sensor/tmp112/Kconfig rename to drivers/sensor/ti/tmp112/Kconfig diff --git a/drivers/sensor/tmp112/tmp112.c b/drivers/sensor/ti/tmp112/tmp112.c similarity index 100% rename from drivers/sensor/tmp112/tmp112.c rename to drivers/sensor/ti/tmp112/tmp112.c diff --git a/drivers/sensor/tmp112/tmp112.h b/drivers/sensor/ti/tmp112/tmp112.h similarity index 100% rename from drivers/sensor/tmp112/tmp112.h rename to drivers/sensor/ti/tmp112/tmp112.h diff --git a/drivers/sensor/tmp116/CMakeLists.txt b/drivers/sensor/ti/tmp116/CMakeLists.txt similarity index 100% rename from drivers/sensor/tmp116/CMakeLists.txt rename to drivers/sensor/ti/tmp116/CMakeLists.txt diff --git a/drivers/sensor/tmp116/Kconfig b/drivers/sensor/ti/tmp116/Kconfig similarity index 100% rename from drivers/sensor/tmp116/Kconfig rename to drivers/sensor/ti/tmp116/Kconfig diff --git a/drivers/sensor/tmp116/tmp116.c b/drivers/sensor/ti/tmp116/tmp116.c similarity index 100% rename from drivers/sensor/tmp116/tmp116.c rename to drivers/sensor/ti/tmp116/tmp116.c diff --git a/drivers/sensor/tmp116/tmp116.h b/drivers/sensor/ti/tmp116/tmp116.h similarity index 100% rename from drivers/sensor/tmp116/tmp116.h rename to drivers/sensor/ti/tmp116/tmp116.h diff --git a/tests/drivers/sensor/ina230/CMakeLists.txt b/tests/drivers/sensor/ina230/CMakeLists.txt index 7ee7f280da3..cf8396daed4 100644 --- a/tests/drivers/sensor/ina230/CMakeLists.txt +++ b/tests/drivers/sensor/ina230/CMakeLists.txt @@ -10,4 +10,4 @@ target_sources(app PRIVATE ${app_sources}) # Include the INA23x driver path and unit-test path for private header inclusion zephyr_include_directories(./src) -zephyr_include_directories($ENV{ZEPHYR_BASE}/drivers/sensor/ina23x) +zephyr_include_directories($ENV{ZEPHYR_BASE}/drivers/sensor/ti/ina23x) diff --git a/tests/drivers/sensor/ina237/CMakeLists.txt b/tests/drivers/sensor/ina237/CMakeLists.txt index 7ee7f280da3..cf8396daed4 100644 --- a/tests/drivers/sensor/ina237/CMakeLists.txt +++ b/tests/drivers/sensor/ina237/CMakeLists.txt @@ -10,4 +10,4 @@ target_sources(app PRIVATE ${app_sources}) # Include the INA23x driver path and unit-test path for private header inclusion zephyr_include_directories(./src) -zephyr_include_directories($ENV{ZEPHYR_BASE}/drivers/sensor/ina23x) +zephyr_include_directories($ENV{ZEPHYR_BASE}/drivers/sensor/ti/ina23x) From 5df44e43d6796661ce579da2ef85eb3fb9e63503 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Tue, 26 Mar 2024 19:08:34 -0500 Subject: [PATCH 1972/2402] drivers: sensor: ams: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 10 +--------- drivers/sensor/Kconfig | 10 +--------- drivers/sensor/ams/CMakeLists.txt | 14 ++++++++++++++ drivers/sensor/ams/Kconfig | 14 ++++++++++++++ drivers/sensor/{ => ams}/ams_as5600/CMakeLists.txt | 0 drivers/sensor/{ => ams}/ams_as5600/Kconfig | 0 drivers/sensor/{ => ams}/ams_as5600/ams_as5600.c | 0 .../sensor/{ => ams}/ams_iAQcore/CMakeLists.txt | 0 drivers/sensor/{ => ams}/ams_iAQcore/Kconfig | 0 drivers/sensor/{ => ams}/ams_iAQcore/iAQcore.c | 0 drivers/sensor/{ => ams}/ams_iAQcore/iAQcore.h | 0 drivers/sensor/{ => ams}/ccs811/CMakeLists.txt | 0 drivers/sensor/{ => ams}/ccs811/Kconfig | 0 drivers/sensor/{ => ams}/ccs811/ccs811.c | 0 drivers/sensor/{ => ams}/ccs811/ccs811.h | 0 drivers/sensor/{ => ams}/ccs811/ccs811_trigger.c | 0 drivers/sensor/{ => ams}/ens210/CMakeLists.txt | 0 drivers/sensor/{ => ams}/ens210/Kconfig | 0 drivers/sensor/{ => ams}/ens210/ens210.c | 0 drivers/sensor/{ => ams}/ens210/ens210.h | 0 drivers/sensor/{ => ams}/tcs3400/CMakeLists.txt | 0 drivers/sensor/{ => ams}/tcs3400/Kconfig | 0 drivers/sensor/{ => ams}/tcs3400/tcs3400.c | 0 drivers/sensor/{ => ams}/tmd2620/CMakeLists.txt | 0 drivers/sensor/{ => ams}/tmd2620/Kconfig | 0 drivers/sensor/{ => ams}/tmd2620/tmd2620.c | 0 drivers/sensor/{ => ams}/tmd2620/tmd2620.h | 0 drivers/sensor/{ => ams}/tmd2620/tmd2620_trigger.c | 0 drivers/sensor/{ => ams}/tsl2540/CMakeLists.txt | 0 drivers/sensor/{ => ams}/tsl2540/Kconfig | 0 drivers/sensor/{ => ams}/tsl2540/tsl2540.c | 0 drivers/sensor/{ => ams}/tsl2540/tsl2540.h | 0 drivers/sensor/{ => ams}/tsl2540/tsl2540_trigger.c | 0 drivers/sensor/{ => ams}/tsl2561/CMakeLists.txt | 0 drivers/sensor/{ => ams}/tsl2561/Kconfig | 0 drivers/sensor/{ => ams}/tsl2561/tsl2561.c | 0 drivers/sensor/{ => ams}/tsl2591/CMakeLists.txt | 0 drivers/sensor/{ => ams}/tsl2591/Kconfig | 0 drivers/sensor/{ => ams}/tsl2591/tsl2591.c | 0 drivers/sensor/{ => ams}/tsl2591/tsl2591.h | 0 drivers/sensor/{ => ams}/tsl2591/tsl2591_trigger.c | 0 41 files changed, 30 insertions(+), 18 deletions(-) create mode 100644 drivers/sensor/ams/CMakeLists.txt create mode 100644 drivers/sensor/ams/Kconfig rename drivers/sensor/{ => ams}/ams_as5600/CMakeLists.txt (100%) rename drivers/sensor/{ => ams}/ams_as5600/Kconfig (100%) rename drivers/sensor/{ => ams}/ams_as5600/ams_as5600.c (100%) rename drivers/sensor/{ => ams}/ams_iAQcore/CMakeLists.txt (100%) rename drivers/sensor/{ => ams}/ams_iAQcore/Kconfig (100%) rename drivers/sensor/{ => ams}/ams_iAQcore/iAQcore.c (100%) rename drivers/sensor/{ => ams}/ams_iAQcore/iAQcore.h (100%) rename drivers/sensor/{ => ams}/ccs811/CMakeLists.txt (100%) rename drivers/sensor/{ => ams}/ccs811/Kconfig (100%) rename drivers/sensor/{ => ams}/ccs811/ccs811.c (100%) rename drivers/sensor/{ => ams}/ccs811/ccs811.h (100%) rename drivers/sensor/{ => ams}/ccs811/ccs811_trigger.c (100%) rename drivers/sensor/{ => ams}/ens210/CMakeLists.txt (100%) rename drivers/sensor/{ => ams}/ens210/Kconfig (100%) rename drivers/sensor/{ => ams}/ens210/ens210.c (100%) rename drivers/sensor/{ => ams}/ens210/ens210.h (100%) rename drivers/sensor/{ => ams}/tcs3400/CMakeLists.txt (100%) rename drivers/sensor/{ => ams}/tcs3400/Kconfig (100%) rename drivers/sensor/{ => ams}/tcs3400/tcs3400.c (100%) rename drivers/sensor/{ => ams}/tmd2620/CMakeLists.txt (100%) rename drivers/sensor/{ => ams}/tmd2620/Kconfig (100%) rename drivers/sensor/{ => ams}/tmd2620/tmd2620.c (100%) rename drivers/sensor/{ => ams}/tmd2620/tmd2620.h (100%) rename drivers/sensor/{ => ams}/tmd2620/tmd2620_trigger.c (100%) rename drivers/sensor/{ => ams}/tsl2540/CMakeLists.txt (100%) rename drivers/sensor/{ => ams}/tsl2540/Kconfig (100%) rename drivers/sensor/{ => ams}/tsl2540/tsl2540.c (100%) rename drivers/sensor/{ => ams}/tsl2540/tsl2540.h (100%) rename drivers/sensor/{ => ams}/tsl2540/tsl2540_trigger.c (100%) rename drivers/sensor/{ => ams}/tsl2561/CMakeLists.txt (100%) rename drivers/sensor/{ => ams}/tsl2561/Kconfig (100%) rename drivers/sensor/{ => ams}/tsl2561/tsl2561.c (100%) rename drivers/sensor/{ => ams}/tsl2591/CMakeLists.txt (100%) rename drivers/sensor/{ => ams}/tsl2591/Kconfig (100%) rename drivers/sensor/{ => ams}/tsl2591/tsl2591.c (100%) rename drivers/sensor/{ => ams}/tsl2591/tsl2591.h (100%) rename drivers/sensor/{ => ams}/tsl2591/tsl2591_trigger.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 01218c6db88..f0c1c1e8098 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -2,6 +2,7 @@ # zephyr-keep-sorted-start add_subdirectory(adi) +add_subdirectory(ams) add_subdirectory(bosch) add_subdirectory(maxim) add_subdirectory(microchip) @@ -18,18 +19,14 @@ add_subdirectory_ifdef(CONFIG_AK8975 ak8975) add_subdirectory_ifdef(CONFIG_AKM09918C akm09918c) add_subdirectory_ifdef(CONFIG_AMD_SB_TSI amd_sb_tsi) add_subdirectory_ifdef(CONFIG_AMG88XX amg88xx) -add_subdirectory_ifdef(CONFIG_AMS_AS5600 ams_as5600) -add_subdirectory_ifdef(CONFIG_AMS_IAQ_CORE ams_iAQcore) add_subdirectory_ifdef(CONFIG_APDS9960 apds9960) add_subdirectory_ifdef(CONFIG_BD8LB600FS_DIAGNOSTICS bd8lb600fs) add_subdirectory_ifdef(CONFIG_BH1750 bh1750) -add_subdirectory_ifdef(CONFIG_CCS811 ccs811) add_subdirectory_ifdef(CONFIG_CURRENT_AMP current_amp) add_subdirectory_ifdef(CONFIG_DHT dht) add_subdirectory_ifdef(CONFIG_DHT20 dht20) add_subdirectory_ifdef(CONFIG_DPS310 dps310) add_subdirectory_ifdef(CONFIG_ENS160 ens160) -add_subdirectory_ifdef(CONFIG_ENS210 ens210) add_subdirectory_ifdef(CONFIG_ESP32_TEMP esp32_temp) add_subdirectory_ifdef(CONFIG_EXPLORIR_M explorir_m) add_subdirectory_ifdef(CONFIG_F75303 f75303) @@ -75,13 +72,8 @@ add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) add_subdirectory_ifdef(CONFIG_TACH_IT8XXX2 ite_tach_it8xxx2) add_subdirectory_ifdef(CONFIG_TACH_NPCX nuvoton_tach_npcx) -add_subdirectory_ifdef(CONFIG_TCS3400 tcs3400) add_subdirectory_ifdef(CONFIG_TEMP_NRF5 nrf5) add_subdirectory_ifdef(CONFIG_TH02 th02) -add_subdirectory_ifdef(CONFIG_TMD2620 tmd2620) -add_subdirectory_ifdef(CONFIG_TSL2540 tsl2540) -add_subdirectory_ifdef(CONFIG_TSL2561 tsl2561) -add_subdirectory_ifdef(CONFIG_TSL2591 tsl2591) add_subdirectory_ifdef(CONFIG_VCMP_IT8XXX2 ite_vcmp_it8xxx2) add_subdirectory_ifdef(CONFIG_VCNL4040 vcnl4040) add_subdirectory_ifdef(CONFIG_VCNL36825T vcnl36825t) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index e5a3bbb313e..8fd51aa9c6a 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -83,6 +83,7 @@ comment "Device Drivers" # zephyr-keep-sorted-start source "drivers/sensor/adi/Kconfig" +source "drivers/sensor/ams/Kconfig" source "drivers/sensor/bosch/Kconfig" source "drivers/sensor/maxim/Kconfig" source "drivers/sensor/microchip/Kconfig" @@ -98,18 +99,14 @@ source "drivers/sensor/ak8975/Kconfig" source "drivers/sensor/akm09918c/Kconfig" source "drivers/sensor/amd_sb_tsi/Kconfig" source "drivers/sensor/amg88xx/Kconfig" -source "drivers/sensor/ams_as5600/Kconfig" -source "drivers/sensor/ams_iAQcore/Kconfig" source "drivers/sensor/apds9960/Kconfig" source "drivers/sensor/bd8lb600fs/Kconfig" source "drivers/sensor/bh1750/Kconfig" -source "drivers/sensor/ccs811/Kconfig" source "drivers/sensor/current_amp/Kconfig" source "drivers/sensor/dht/Kconfig" source "drivers/sensor/dht20/Kconfig" source "drivers/sensor/dps310/Kconfig" source "drivers/sensor/ens160/Kconfig" -source "drivers/sensor/ens210/Kconfig" source "drivers/sensor/esp32_temp/Kconfig" source "drivers/sensor/explorir_m/Kconfig" source "drivers/sensor/f75303/Kconfig" @@ -157,12 +154,7 @@ source "drivers/sensor/sht4x/Kconfig" source "drivers/sensor/shtcx/Kconfig" source "drivers/sensor/sm351lt/Kconfig" source "drivers/sensor/sx9500/Kconfig" -source "drivers/sensor/tcs3400/Kconfig" source "drivers/sensor/th02/Kconfig" -source "drivers/sensor/tmd2620/Kconfig" -source "drivers/sensor/tsl2540/Kconfig" -source "drivers/sensor/tsl2561/Kconfig" -source "drivers/sensor/tsl2591/Kconfig" source "drivers/sensor/vcnl4040/Kconfig" source "drivers/sensor/vcnl36825t/Kconfig" source "drivers/sensor/veml7700/Kconfig" diff --git a/drivers/sensor/ams/CMakeLists.txt b/drivers/sensor/ams/CMakeLists.txt new file mode 100644 index 00000000000..6561af6659e --- /dev/null +++ b/drivers/sensor/ams/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_AMS_AS5600 ams_as5600) +add_subdirectory_ifdef(CONFIG_AMS_IAQ_CORE ams_iAQcore) +add_subdirectory_ifdef(CONFIG_CCS811 ccs811) +add_subdirectory_ifdef(CONFIG_ENS210 ens210) +add_subdirectory_ifdef(CONFIG_TCS3400 tcs3400) +add_subdirectory_ifdef(CONFIG_TMD2620 tmd2620) +add_subdirectory_ifdef(CONFIG_TSL2540 tsl2540) +add_subdirectory_ifdef(CONFIG_TSL2561 tsl2561) +add_subdirectory_ifdef(CONFIG_TSL2591 tsl2591) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/ams/Kconfig b/drivers/sensor/ams/Kconfig new file mode 100644 index 00000000000..5aa40b944a8 --- /dev/null +++ b/drivers/sensor/ams/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/ams/ams_as5600/Kconfig" +source "drivers/sensor/ams/ams_iAQcore/Kconfig" +source "drivers/sensor/ams/ccs811/Kconfig" +source "drivers/sensor/ams/ens210/Kconfig" +source "drivers/sensor/ams/tcs3400/Kconfig" +source "drivers/sensor/ams/tmd2620/Kconfig" +source "drivers/sensor/ams/tsl2540/Kconfig" +source "drivers/sensor/ams/tsl2561/Kconfig" +source "drivers/sensor/ams/tsl2591/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/ams_as5600/CMakeLists.txt b/drivers/sensor/ams/ams_as5600/CMakeLists.txt similarity index 100% rename from drivers/sensor/ams_as5600/CMakeLists.txt rename to drivers/sensor/ams/ams_as5600/CMakeLists.txt diff --git a/drivers/sensor/ams_as5600/Kconfig b/drivers/sensor/ams/ams_as5600/Kconfig similarity index 100% rename from drivers/sensor/ams_as5600/Kconfig rename to drivers/sensor/ams/ams_as5600/Kconfig diff --git a/drivers/sensor/ams_as5600/ams_as5600.c b/drivers/sensor/ams/ams_as5600/ams_as5600.c similarity index 100% rename from drivers/sensor/ams_as5600/ams_as5600.c rename to drivers/sensor/ams/ams_as5600/ams_as5600.c diff --git a/drivers/sensor/ams_iAQcore/CMakeLists.txt b/drivers/sensor/ams/ams_iAQcore/CMakeLists.txt similarity index 100% rename from drivers/sensor/ams_iAQcore/CMakeLists.txt rename to drivers/sensor/ams/ams_iAQcore/CMakeLists.txt diff --git a/drivers/sensor/ams_iAQcore/Kconfig b/drivers/sensor/ams/ams_iAQcore/Kconfig similarity index 100% rename from drivers/sensor/ams_iAQcore/Kconfig rename to drivers/sensor/ams/ams_iAQcore/Kconfig diff --git a/drivers/sensor/ams_iAQcore/iAQcore.c b/drivers/sensor/ams/ams_iAQcore/iAQcore.c similarity index 100% rename from drivers/sensor/ams_iAQcore/iAQcore.c rename to drivers/sensor/ams/ams_iAQcore/iAQcore.c diff --git a/drivers/sensor/ams_iAQcore/iAQcore.h b/drivers/sensor/ams/ams_iAQcore/iAQcore.h similarity index 100% rename from drivers/sensor/ams_iAQcore/iAQcore.h rename to drivers/sensor/ams/ams_iAQcore/iAQcore.h diff --git a/drivers/sensor/ccs811/CMakeLists.txt b/drivers/sensor/ams/ccs811/CMakeLists.txt similarity index 100% rename from drivers/sensor/ccs811/CMakeLists.txt rename to drivers/sensor/ams/ccs811/CMakeLists.txt diff --git a/drivers/sensor/ccs811/Kconfig b/drivers/sensor/ams/ccs811/Kconfig similarity index 100% rename from drivers/sensor/ccs811/Kconfig rename to drivers/sensor/ams/ccs811/Kconfig diff --git a/drivers/sensor/ccs811/ccs811.c b/drivers/sensor/ams/ccs811/ccs811.c similarity index 100% rename from drivers/sensor/ccs811/ccs811.c rename to drivers/sensor/ams/ccs811/ccs811.c diff --git a/drivers/sensor/ccs811/ccs811.h b/drivers/sensor/ams/ccs811/ccs811.h similarity index 100% rename from drivers/sensor/ccs811/ccs811.h rename to drivers/sensor/ams/ccs811/ccs811.h diff --git a/drivers/sensor/ccs811/ccs811_trigger.c b/drivers/sensor/ams/ccs811/ccs811_trigger.c similarity index 100% rename from drivers/sensor/ccs811/ccs811_trigger.c rename to drivers/sensor/ams/ccs811/ccs811_trigger.c diff --git a/drivers/sensor/ens210/CMakeLists.txt b/drivers/sensor/ams/ens210/CMakeLists.txt similarity index 100% rename from drivers/sensor/ens210/CMakeLists.txt rename to drivers/sensor/ams/ens210/CMakeLists.txt diff --git a/drivers/sensor/ens210/Kconfig b/drivers/sensor/ams/ens210/Kconfig similarity index 100% rename from drivers/sensor/ens210/Kconfig rename to drivers/sensor/ams/ens210/Kconfig diff --git a/drivers/sensor/ens210/ens210.c b/drivers/sensor/ams/ens210/ens210.c similarity index 100% rename from drivers/sensor/ens210/ens210.c rename to drivers/sensor/ams/ens210/ens210.c diff --git a/drivers/sensor/ens210/ens210.h b/drivers/sensor/ams/ens210/ens210.h similarity index 100% rename from drivers/sensor/ens210/ens210.h rename to drivers/sensor/ams/ens210/ens210.h diff --git a/drivers/sensor/tcs3400/CMakeLists.txt b/drivers/sensor/ams/tcs3400/CMakeLists.txt similarity index 100% rename from drivers/sensor/tcs3400/CMakeLists.txt rename to drivers/sensor/ams/tcs3400/CMakeLists.txt diff --git a/drivers/sensor/tcs3400/Kconfig b/drivers/sensor/ams/tcs3400/Kconfig similarity index 100% rename from drivers/sensor/tcs3400/Kconfig rename to drivers/sensor/ams/tcs3400/Kconfig diff --git a/drivers/sensor/tcs3400/tcs3400.c b/drivers/sensor/ams/tcs3400/tcs3400.c similarity index 100% rename from drivers/sensor/tcs3400/tcs3400.c rename to drivers/sensor/ams/tcs3400/tcs3400.c diff --git a/drivers/sensor/tmd2620/CMakeLists.txt b/drivers/sensor/ams/tmd2620/CMakeLists.txt similarity index 100% rename from drivers/sensor/tmd2620/CMakeLists.txt rename to drivers/sensor/ams/tmd2620/CMakeLists.txt diff --git a/drivers/sensor/tmd2620/Kconfig b/drivers/sensor/ams/tmd2620/Kconfig similarity index 100% rename from drivers/sensor/tmd2620/Kconfig rename to drivers/sensor/ams/tmd2620/Kconfig diff --git a/drivers/sensor/tmd2620/tmd2620.c b/drivers/sensor/ams/tmd2620/tmd2620.c similarity index 100% rename from drivers/sensor/tmd2620/tmd2620.c rename to drivers/sensor/ams/tmd2620/tmd2620.c diff --git a/drivers/sensor/tmd2620/tmd2620.h b/drivers/sensor/ams/tmd2620/tmd2620.h similarity index 100% rename from drivers/sensor/tmd2620/tmd2620.h rename to drivers/sensor/ams/tmd2620/tmd2620.h diff --git a/drivers/sensor/tmd2620/tmd2620_trigger.c b/drivers/sensor/ams/tmd2620/tmd2620_trigger.c similarity index 100% rename from drivers/sensor/tmd2620/tmd2620_trigger.c rename to drivers/sensor/ams/tmd2620/tmd2620_trigger.c diff --git a/drivers/sensor/tsl2540/CMakeLists.txt b/drivers/sensor/ams/tsl2540/CMakeLists.txt similarity index 100% rename from drivers/sensor/tsl2540/CMakeLists.txt rename to drivers/sensor/ams/tsl2540/CMakeLists.txt diff --git a/drivers/sensor/tsl2540/Kconfig b/drivers/sensor/ams/tsl2540/Kconfig similarity index 100% rename from drivers/sensor/tsl2540/Kconfig rename to drivers/sensor/ams/tsl2540/Kconfig diff --git a/drivers/sensor/tsl2540/tsl2540.c b/drivers/sensor/ams/tsl2540/tsl2540.c similarity index 100% rename from drivers/sensor/tsl2540/tsl2540.c rename to drivers/sensor/ams/tsl2540/tsl2540.c diff --git a/drivers/sensor/tsl2540/tsl2540.h b/drivers/sensor/ams/tsl2540/tsl2540.h similarity index 100% rename from drivers/sensor/tsl2540/tsl2540.h rename to drivers/sensor/ams/tsl2540/tsl2540.h diff --git a/drivers/sensor/tsl2540/tsl2540_trigger.c b/drivers/sensor/ams/tsl2540/tsl2540_trigger.c similarity index 100% rename from drivers/sensor/tsl2540/tsl2540_trigger.c rename to drivers/sensor/ams/tsl2540/tsl2540_trigger.c diff --git a/drivers/sensor/tsl2561/CMakeLists.txt b/drivers/sensor/ams/tsl2561/CMakeLists.txt similarity index 100% rename from drivers/sensor/tsl2561/CMakeLists.txt rename to drivers/sensor/ams/tsl2561/CMakeLists.txt diff --git a/drivers/sensor/tsl2561/Kconfig b/drivers/sensor/ams/tsl2561/Kconfig similarity index 100% rename from drivers/sensor/tsl2561/Kconfig rename to drivers/sensor/ams/tsl2561/Kconfig diff --git a/drivers/sensor/tsl2561/tsl2561.c b/drivers/sensor/ams/tsl2561/tsl2561.c similarity index 100% rename from drivers/sensor/tsl2561/tsl2561.c rename to drivers/sensor/ams/tsl2561/tsl2561.c diff --git a/drivers/sensor/tsl2591/CMakeLists.txt b/drivers/sensor/ams/tsl2591/CMakeLists.txt similarity index 100% rename from drivers/sensor/tsl2591/CMakeLists.txt rename to drivers/sensor/ams/tsl2591/CMakeLists.txt diff --git a/drivers/sensor/tsl2591/Kconfig b/drivers/sensor/ams/tsl2591/Kconfig similarity index 100% rename from drivers/sensor/tsl2591/Kconfig rename to drivers/sensor/ams/tsl2591/Kconfig diff --git a/drivers/sensor/tsl2591/tsl2591.c b/drivers/sensor/ams/tsl2591/tsl2591.c similarity index 100% rename from drivers/sensor/tsl2591/tsl2591.c rename to drivers/sensor/ams/tsl2591/tsl2591.c diff --git a/drivers/sensor/tsl2591/tsl2591.h b/drivers/sensor/ams/tsl2591/tsl2591.h similarity index 100% rename from drivers/sensor/tsl2591/tsl2591.h rename to drivers/sensor/ams/tsl2591/tsl2591.h diff --git a/drivers/sensor/tsl2591/tsl2591_trigger.c b/drivers/sensor/ams/tsl2591/tsl2591_trigger.c similarity index 100% rename from drivers/sensor/tsl2591/tsl2591_trigger.c rename to drivers/sensor/ams/tsl2591/tsl2591_trigger.c From fab99bd64144f58f2d4f1f745e905358106afae4 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Wed, 27 Mar 2024 18:51:06 -0500 Subject: [PATCH 1973/2402] drivers: sensor: sensirion: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 5 +---- drivers/sensor/Kconfig | 5 +---- drivers/sensor/sensirion/CMakeLists.txt | 9 +++++++++ drivers/sensor/sensirion/Kconfig | 9 +++++++++ drivers/sensor/{ => sensirion}/sgp40/CMakeLists.txt | 0 drivers/sensor/{ => sensirion}/sgp40/Kconfig | 0 drivers/sensor/{ => sensirion}/sgp40/sgp40.c | 0 drivers/sensor/{ => sensirion}/sgp40/sgp40.h | 0 drivers/sensor/{ => sensirion}/sht3xd/CMakeLists.txt | 0 drivers/sensor/{ => sensirion}/sht3xd/Kconfig | 0 drivers/sensor/{ => sensirion}/sht3xd/sht3xd.c | 0 drivers/sensor/{ => sensirion}/sht3xd/sht3xd.h | 0 drivers/sensor/{ => sensirion}/sht3xd/sht3xd_trigger.c | 0 drivers/sensor/{ => sensirion}/sht4x/CMakeLists.txt | 0 drivers/sensor/{ => sensirion}/sht4x/Kconfig | 0 drivers/sensor/{ => sensirion}/sht4x/sht4x.c | 0 drivers/sensor/{ => sensirion}/sht4x/sht4x.h | 0 drivers/sensor/{ => sensirion}/shtcx/CMakeLists.txt | 0 drivers/sensor/{ => sensirion}/shtcx/Kconfig | 0 drivers/sensor/{ => sensirion}/shtcx/shtcx.c | 0 drivers/sensor/{ => sensirion}/shtcx/shtcx.h | 0 21 files changed, 20 insertions(+), 8 deletions(-) create mode 100644 drivers/sensor/sensirion/CMakeLists.txt create mode 100644 drivers/sensor/sensirion/Kconfig rename drivers/sensor/{ => sensirion}/sgp40/CMakeLists.txt (100%) rename drivers/sensor/{ => sensirion}/sgp40/Kconfig (100%) rename drivers/sensor/{ => sensirion}/sgp40/sgp40.c (100%) rename drivers/sensor/{ => sensirion}/sgp40/sgp40.h (100%) rename drivers/sensor/{ => sensirion}/sht3xd/CMakeLists.txt (100%) rename drivers/sensor/{ => sensirion}/sht3xd/Kconfig (100%) rename drivers/sensor/{ => sensirion}/sht3xd/sht3xd.c (100%) rename drivers/sensor/{ => sensirion}/sht3xd/sht3xd.h (100%) rename drivers/sensor/{ => sensirion}/sht3xd/sht3xd_trigger.c (100%) rename drivers/sensor/{ => sensirion}/sht4x/CMakeLists.txt (100%) rename drivers/sensor/{ => sensirion}/sht4x/Kconfig (100%) rename drivers/sensor/{ => sensirion}/sht4x/sht4x.c (100%) rename drivers/sensor/{ => sensirion}/sht4x/sht4x.h (100%) rename drivers/sensor/{ => sensirion}/shtcx/CMakeLists.txt (100%) rename drivers/sensor/{ => sensirion}/shtcx/Kconfig (100%) rename drivers/sensor/{ => sensirion}/shtcx/shtcx.c (100%) rename drivers/sensor/{ => sensirion}/shtcx/shtcx.h (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index f0c1c1e8098..60002978f44 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -7,6 +7,7 @@ add_subdirectory(bosch) add_subdirectory(maxim) add_subdirectory(microchip) add_subdirectory(nxp) +add_subdirectory(sensirion) add_subdirectory(silabs) add_subdirectory(st) add_subdirectory(ti) @@ -64,10 +65,6 @@ add_subdirectory_ifdef(CONFIG_QDEC_SAM qdec_sam) add_subdirectory_ifdef(CONFIG_RPI_PICO_TEMP rpi_pico_temp) add_subdirectory_ifdef(CONFIG_S11059 s11059) add_subdirectory_ifdef(CONFIG_SBS_GAUGE sbs_gauge) -add_subdirectory_ifdef(CONFIG_SGP40 sgp40) -add_subdirectory_ifdef(CONFIG_SHT3XD sht3xd) -add_subdirectory_ifdef(CONFIG_SHT4X sht4x) -add_subdirectory_ifdef(CONFIG_SHTCX shtcx) add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) add_subdirectory_ifdef(CONFIG_TACH_IT8XXX2 ite_tach_it8xxx2) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 8fd51aa9c6a..82478969bf2 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -88,6 +88,7 @@ source "drivers/sensor/bosch/Kconfig" source "drivers/sensor/maxim/Kconfig" source "drivers/sensor/microchip/Kconfig" source "drivers/sensor/nxp/Kconfig" +source "drivers/sensor/sensirion/Kconfig" source "drivers/sensor/silabs/Kconfig" source "drivers/sensor/st/Kconfig" source "drivers/sensor/ti/Kconfig" @@ -148,10 +149,6 @@ source "drivers/sensor/qdec_sam/Kconfig" source "drivers/sensor/rpi_pico_temp/Kconfig" source "drivers/sensor/s11059/Kconfig" source "drivers/sensor/sbs_gauge/Kconfig" -source "drivers/sensor/sgp40/Kconfig" -source "drivers/sensor/sht3xd/Kconfig" -source "drivers/sensor/sht4x/Kconfig" -source "drivers/sensor/shtcx/Kconfig" source "drivers/sensor/sm351lt/Kconfig" source "drivers/sensor/sx9500/Kconfig" source "drivers/sensor/th02/Kconfig" diff --git a/drivers/sensor/sensirion/CMakeLists.txt b/drivers/sensor/sensirion/CMakeLists.txt new file mode 100644 index 00000000000..68a26c2518a --- /dev/null +++ b/drivers/sensor/sensirion/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_SGP40 sgp40) +add_subdirectory_ifdef(CONFIG_SHT3XD sht3xd) +add_subdirectory_ifdef(CONFIG_SHT4X sht4x) +add_subdirectory_ifdef(CONFIG_SHTCX shtcx) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/sensirion/Kconfig b/drivers/sensor/sensirion/Kconfig new file mode 100644 index 00000000000..87409404fa8 --- /dev/null +++ b/drivers/sensor/sensirion/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/sensirion/sgp40/Kconfig" +source "drivers/sensor/sensirion/sht3xd/Kconfig" +source "drivers/sensor/sensirion/sht4x/Kconfig" +source "drivers/sensor/sensirion/shtcx/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/sgp40/CMakeLists.txt b/drivers/sensor/sensirion/sgp40/CMakeLists.txt similarity index 100% rename from drivers/sensor/sgp40/CMakeLists.txt rename to drivers/sensor/sensirion/sgp40/CMakeLists.txt diff --git a/drivers/sensor/sgp40/Kconfig b/drivers/sensor/sensirion/sgp40/Kconfig similarity index 100% rename from drivers/sensor/sgp40/Kconfig rename to drivers/sensor/sensirion/sgp40/Kconfig diff --git a/drivers/sensor/sgp40/sgp40.c b/drivers/sensor/sensirion/sgp40/sgp40.c similarity index 100% rename from drivers/sensor/sgp40/sgp40.c rename to drivers/sensor/sensirion/sgp40/sgp40.c diff --git a/drivers/sensor/sgp40/sgp40.h b/drivers/sensor/sensirion/sgp40/sgp40.h similarity index 100% rename from drivers/sensor/sgp40/sgp40.h rename to drivers/sensor/sensirion/sgp40/sgp40.h diff --git a/drivers/sensor/sht3xd/CMakeLists.txt b/drivers/sensor/sensirion/sht3xd/CMakeLists.txt similarity index 100% rename from drivers/sensor/sht3xd/CMakeLists.txt rename to drivers/sensor/sensirion/sht3xd/CMakeLists.txt diff --git a/drivers/sensor/sht3xd/Kconfig b/drivers/sensor/sensirion/sht3xd/Kconfig similarity index 100% rename from drivers/sensor/sht3xd/Kconfig rename to drivers/sensor/sensirion/sht3xd/Kconfig diff --git a/drivers/sensor/sht3xd/sht3xd.c b/drivers/sensor/sensirion/sht3xd/sht3xd.c similarity index 100% rename from drivers/sensor/sht3xd/sht3xd.c rename to drivers/sensor/sensirion/sht3xd/sht3xd.c diff --git a/drivers/sensor/sht3xd/sht3xd.h b/drivers/sensor/sensirion/sht3xd/sht3xd.h similarity index 100% rename from drivers/sensor/sht3xd/sht3xd.h rename to drivers/sensor/sensirion/sht3xd/sht3xd.h diff --git a/drivers/sensor/sht3xd/sht3xd_trigger.c b/drivers/sensor/sensirion/sht3xd/sht3xd_trigger.c similarity index 100% rename from drivers/sensor/sht3xd/sht3xd_trigger.c rename to drivers/sensor/sensirion/sht3xd/sht3xd_trigger.c diff --git a/drivers/sensor/sht4x/CMakeLists.txt b/drivers/sensor/sensirion/sht4x/CMakeLists.txt similarity index 100% rename from drivers/sensor/sht4x/CMakeLists.txt rename to drivers/sensor/sensirion/sht4x/CMakeLists.txt diff --git a/drivers/sensor/sht4x/Kconfig b/drivers/sensor/sensirion/sht4x/Kconfig similarity index 100% rename from drivers/sensor/sht4x/Kconfig rename to drivers/sensor/sensirion/sht4x/Kconfig diff --git a/drivers/sensor/sht4x/sht4x.c b/drivers/sensor/sensirion/sht4x/sht4x.c similarity index 100% rename from drivers/sensor/sht4x/sht4x.c rename to drivers/sensor/sensirion/sht4x/sht4x.c diff --git a/drivers/sensor/sht4x/sht4x.h b/drivers/sensor/sensirion/sht4x/sht4x.h similarity index 100% rename from drivers/sensor/sht4x/sht4x.h rename to drivers/sensor/sensirion/sht4x/sht4x.h diff --git a/drivers/sensor/shtcx/CMakeLists.txt b/drivers/sensor/sensirion/shtcx/CMakeLists.txt similarity index 100% rename from drivers/sensor/shtcx/CMakeLists.txt rename to drivers/sensor/sensirion/shtcx/CMakeLists.txt diff --git a/drivers/sensor/shtcx/Kconfig b/drivers/sensor/sensirion/shtcx/Kconfig similarity index 100% rename from drivers/sensor/shtcx/Kconfig rename to drivers/sensor/sensirion/shtcx/Kconfig diff --git a/drivers/sensor/shtcx/shtcx.c b/drivers/sensor/sensirion/shtcx/shtcx.c similarity index 100% rename from drivers/sensor/shtcx/shtcx.c rename to drivers/sensor/sensirion/shtcx/shtcx.c diff --git a/drivers/sensor/shtcx/shtcx.h b/drivers/sensor/sensirion/shtcx/shtcx.h similarity index 100% rename from drivers/sensor/shtcx/shtcx.h rename to drivers/sensor/sensirion/shtcx/shtcx.h From 2fc36432e6fbf9a72d268afd056b5dd4b7968bb4 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Wed, 27 Mar 2024 18:56:30 -0500 Subject: [PATCH 1974/2402] drivers: sensor: wsen: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 6 +----- drivers/sensor/Kconfig | 6 +----- drivers/sensor/wsen/CMakeLists.txt | 10 ++++++++++ drivers/sensor/wsen/Kconfig | 10 ++++++++++ drivers/sensor/{ => wsen}/wsen_hids/CMakeLists.txt | 0 drivers/sensor/{ => wsen}/wsen_hids/Kconfig | 0 drivers/sensor/{ => wsen}/wsen_hids/wsen_hids.c | 0 drivers/sensor/{ => wsen}/wsen_hids/wsen_hids.h | 0 .../sensor/{ => wsen}/wsen_hids/wsen_hids_trigger.c | 0 drivers/sensor/{ => wsen}/wsen_itds/CMakeLists.txt | 0 drivers/sensor/{ => wsen}/wsen_itds/Kconfig | 0 drivers/sensor/{ => wsen}/wsen_itds/itds.c | 0 drivers/sensor/{ => wsen}/wsen_itds/itds.h | 0 drivers/sensor/{ => wsen}/wsen_itds/itds_trigger.c | 0 drivers/sensor/{ => wsen}/wsen_pads/CMakeLists.txt | 0 drivers/sensor/{ => wsen}/wsen_pads/Kconfig | 0 drivers/sensor/{ => wsen}/wsen_pads/wsen_pads.c | 0 drivers/sensor/{ => wsen}/wsen_pads/wsen_pads.h | 0 .../sensor/{ => wsen}/wsen_pads/wsen_pads_trigger.c | 0 drivers/sensor/{ => wsen}/wsen_pdus/CMakeLists.txt | 0 drivers/sensor/{ => wsen}/wsen_pdus/Kconfig | 0 drivers/sensor/{ => wsen}/wsen_pdus/wsen_pdus.c | 0 drivers/sensor/{ => wsen}/wsen_pdus/wsen_pdus.h | 0 drivers/sensor/{ => wsen}/wsen_tids/CMakeLists.txt | 0 drivers/sensor/{ => wsen}/wsen_tids/Kconfig | 0 drivers/sensor/{ => wsen}/wsen_tids/wsen_tids.c | 0 drivers/sensor/{ => wsen}/wsen_tids/wsen_tids.h | 0 .../sensor/{ => wsen}/wsen_tids/wsen_tids_trigger.c | 0 28 files changed, 22 insertions(+), 10 deletions(-) create mode 100644 drivers/sensor/wsen/CMakeLists.txt create mode 100644 drivers/sensor/wsen/Kconfig rename drivers/sensor/{ => wsen}/wsen_hids/CMakeLists.txt (100%) rename drivers/sensor/{ => wsen}/wsen_hids/Kconfig (100%) rename drivers/sensor/{ => wsen}/wsen_hids/wsen_hids.c (100%) rename drivers/sensor/{ => wsen}/wsen_hids/wsen_hids.h (100%) rename drivers/sensor/{ => wsen}/wsen_hids/wsen_hids_trigger.c (100%) rename drivers/sensor/{ => wsen}/wsen_itds/CMakeLists.txt (100%) rename drivers/sensor/{ => wsen}/wsen_itds/Kconfig (100%) rename drivers/sensor/{ => wsen}/wsen_itds/itds.c (100%) rename drivers/sensor/{ => wsen}/wsen_itds/itds.h (100%) rename drivers/sensor/{ => wsen}/wsen_itds/itds_trigger.c (100%) rename drivers/sensor/{ => wsen}/wsen_pads/CMakeLists.txt (100%) rename drivers/sensor/{ => wsen}/wsen_pads/Kconfig (100%) rename drivers/sensor/{ => wsen}/wsen_pads/wsen_pads.c (100%) rename drivers/sensor/{ => wsen}/wsen_pads/wsen_pads.h (100%) rename drivers/sensor/{ => wsen}/wsen_pads/wsen_pads_trigger.c (100%) rename drivers/sensor/{ => wsen}/wsen_pdus/CMakeLists.txt (100%) rename drivers/sensor/{ => wsen}/wsen_pdus/Kconfig (100%) rename drivers/sensor/{ => wsen}/wsen_pdus/wsen_pdus.c (100%) rename drivers/sensor/{ => wsen}/wsen_pdus/wsen_pdus.h (100%) rename drivers/sensor/{ => wsen}/wsen_tids/CMakeLists.txt (100%) rename drivers/sensor/{ => wsen}/wsen_tids/Kconfig (100%) rename drivers/sensor/{ => wsen}/wsen_tids/wsen_tids.c (100%) rename drivers/sensor/{ => wsen}/wsen_tids/wsen_tids.h (100%) rename drivers/sensor/{ => wsen}/wsen_tids/wsen_tids_trigger.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 60002978f44..708fc2f0e83 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -11,6 +11,7 @@ add_subdirectory(sensirion) add_subdirectory(silabs) add_subdirectory(st) add_subdirectory(ti) +add_subdirectory(wsen) # zephyr-keep-sorted-stop add_subdirectory_ifdef(CONFIG_A01NYUB a01nyub) @@ -44,7 +45,6 @@ add_subdirectory_ifdef(CONFIG_ICM42688 tdk/icm42688) add_subdirectory_ifdef(CONFIG_ICP10125 tdk/icp10125) add_subdirectory_ifdef(CONFIG_IST8310 ist8310) add_subdirectory_ifdef(CONFIG_ISL29035 isl29035) -add_subdirectory_ifdef(CONFIG_ITDS wsen_itds) add_subdirectory_ifdef(CONFIG_LM35 lm35) add_subdirectory_ifdef(CONFIG_LM75 lm75) add_subdirectory_ifdef(CONFIG_LM77 lm77) @@ -76,10 +76,6 @@ add_subdirectory_ifdef(CONFIG_VCNL4040 vcnl4040) add_subdirectory_ifdef(CONFIG_VCNL36825T vcnl36825t) add_subdirectory_ifdef(CONFIG_VEML7700 veml7700) add_subdirectory_ifdef(CONFIG_VOLTAGE_DIVIDER voltage_divider) -add_subdirectory_ifdef(CONFIG_WSEN_HIDS wsen_hids) -add_subdirectory_ifdef(CONFIG_WSEN_PADS wsen_pads) -add_subdirectory_ifdef(CONFIG_WSEN_PDUS wsen_pdus) -add_subdirectory_ifdef(CONFIG_WSEN_TIDS wsen_tids) add_subdirectory_ifdef(CONFIG_XMC4XXX_TEMP xmc4xxx_temp) add_subdirectory_ifdef(CONFIG_TACH_ENE_KB1200 ene_tach_kb1200) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 82478969bf2..162e92ae275 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -92,6 +92,7 @@ source "drivers/sensor/sensirion/Kconfig" source "drivers/sensor/silabs/Kconfig" source "drivers/sensor/st/Kconfig" source "drivers/sensor/ti/Kconfig" +source "drivers/sensor/wsen/Kconfig" # zephyr-keep-sorted-stop source "drivers/sensor/a01nyub/Kconfig" @@ -156,11 +157,6 @@ source "drivers/sensor/vcnl4040/Kconfig" source "drivers/sensor/vcnl36825t/Kconfig" source "drivers/sensor/veml7700/Kconfig" source "drivers/sensor/voltage_divider/Kconfig" -source "drivers/sensor/wsen_hids/Kconfig" -source "drivers/sensor/wsen_itds/Kconfig" -source "drivers/sensor/wsen_pads/Kconfig" -source "drivers/sensor/wsen_pdus/Kconfig" -source "drivers/sensor/wsen_tids/Kconfig" source "drivers/sensor/xmc4xxx_temp/Kconfig" source "drivers/sensor/ene_tach_kb1200/Kconfig" diff --git a/drivers/sensor/wsen/CMakeLists.txt b/drivers/sensor/wsen/CMakeLists.txt new file mode 100644 index 00000000000..6be98625036 --- /dev/null +++ b/drivers/sensor/wsen/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_ITDS wsen_itds) +add_subdirectory_ifdef(CONFIG_WSEN_HIDS wsen_hids) +add_subdirectory_ifdef(CONFIG_WSEN_PADS wsen_pads) +add_subdirectory_ifdef(CONFIG_WSEN_PDUS wsen_pdus) +add_subdirectory_ifdef(CONFIG_WSEN_TIDS wsen_tids) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/wsen/Kconfig b/drivers/sensor/wsen/Kconfig new file mode 100644 index 00000000000..4e96bd52588 --- /dev/null +++ b/drivers/sensor/wsen/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/wsen/wsen_hids/Kconfig" +source "drivers/sensor/wsen/wsen_itds/Kconfig" +source "drivers/sensor/wsen/wsen_pads/Kconfig" +source "drivers/sensor/wsen/wsen_pdus/Kconfig" +source "drivers/sensor/wsen/wsen_tids/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/wsen_hids/CMakeLists.txt b/drivers/sensor/wsen/wsen_hids/CMakeLists.txt similarity index 100% rename from drivers/sensor/wsen_hids/CMakeLists.txt rename to drivers/sensor/wsen/wsen_hids/CMakeLists.txt diff --git a/drivers/sensor/wsen_hids/Kconfig b/drivers/sensor/wsen/wsen_hids/Kconfig similarity index 100% rename from drivers/sensor/wsen_hids/Kconfig rename to drivers/sensor/wsen/wsen_hids/Kconfig diff --git a/drivers/sensor/wsen_hids/wsen_hids.c b/drivers/sensor/wsen/wsen_hids/wsen_hids.c similarity index 100% rename from drivers/sensor/wsen_hids/wsen_hids.c rename to drivers/sensor/wsen/wsen_hids/wsen_hids.c diff --git a/drivers/sensor/wsen_hids/wsen_hids.h b/drivers/sensor/wsen/wsen_hids/wsen_hids.h similarity index 100% rename from drivers/sensor/wsen_hids/wsen_hids.h rename to drivers/sensor/wsen/wsen_hids/wsen_hids.h diff --git a/drivers/sensor/wsen_hids/wsen_hids_trigger.c b/drivers/sensor/wsen/wsen_hids/wsen_hids_trigger.c similarity index 100% rename from drivers/sensor/wsen_hids/wsen_hids_trigger.c rename to drivers/sensor/wsen/wsen_hids/wsen_hids_trigger.c diff --git a/drivers/sensor/wsen_itds/CMakeLists.txt b/drivers/sensor/wsen/wsen_itds/CMakeLists.txt similarity index 100% rename from drivers/sensor/wsen_itds/CMakeLists.txt rename to drivers/sensor/wsen/wsen_itds/CMakeLists.txt diff --git a/drivers/sensor/wsen_itds/Kconfig b/drivers/sensor/wsen/wsen_itds/Kconfig similarity index 100% rename from drivers/sensor/wsen_itds/Kconfig rename to drivers/sensor/wsen/wsen_itds/Kconfig diff --git a/drivers/sensor/wsen_itds/itds.c b/drivers/sensor/wsen/wsen_itds/itds.c similarity index 100% rename from drivers/sensor/wsen_itds/itds.c rename to drivers/sensor/wsen/wsen_itds/itds.c diff --git a/drivers/sensor/wsen_itds/itds.h b/drivers/sensor/wsen/wsen_itds/itds.h similarity index 100% rename from drivers/sensor/wsen_itds/itds.h rename to drivers/sensor/wsen/wsen_itds/itds.h diff --git a/drivers/sensor/wsen_itds/itds_trigger.c b/drivers/sensor/wsen/wsen_itds/itds_trigger.c similarity index 100% rename from drivers/sensor/wsen_itds/itds_trigger.c rename to drivers/sensor/wsen/wsen_itds/itds_trigger.c diff --git a/drivers/sensor/wsen_pads/CMakeLists.txt b/drivers/sensor/wsen/wsen_pads/CMakeLists.txt similarity index 100% rename from drivers/sensor/wsen_pads/CMakeLists.txt rename to drivers/sensor/wsen/wsen_pads/CMakeLists.txt diff --git a/drivers/sensor/wsen_pads/Kconfig b/drivers/sensor/wsen/wsen_pads/Kconfig similarity index 100% rename from drivers/sensor/wsen_pads/Kconfig rename to drivers/sensor/wsen/wsen_pads/Kconfig diff --git a/drivers/sensor/wsen_pads/wsen_pads.c b/drivers/sensor/wsen/wsen_pads/wsen_pads.c similarity index 100% rename from drivers/sensor/wsen_pads/wsen_pads.c rename to drivers/sensor/wsen/wsen_pads/wsen_pads.c diff --git a/drivers/sensor/wsen_pads/wsen_pads.h b/drivers/sensor/wsen/wsen_pads/wsen_pads.h similarity index 100% rename from drivers/sensor/wsen_pads/wsen_pads.h rename to drivers/sensor/wsen/wsen_pads/wsen_pads.h diff --git a/drivers/sensor/wsen_pads/wsen_pads_trigger.c b/drivers/sensor/wsen/wsen_pads/wsen_pads_trigger.c similarity index 100% rename from drivers/sensor/wsen_pads/wsen_pads_trigger.c rename to drivers/sensor/wsen/wsen_pads/wsen_pads_trigger.c diff --git a/drivers/sensor/wsen_pdus/CMakeLists.txt b/drivers/sensor/wsen/wsen_pdus/CMakeLists.txt similarity index 100% rename from drivers/sensor/wsen_pdus/CMakeLists.txt rename to drivers/sensor/wsen/wsen_pdus/CMakeLists.txt diff --git a/drivers/sensor/wsen_pdus/Kconfig b/drivers/sensor/wsen/wsen_pdus/Kconfig similarity index 100% rename from drivers/sensor/wsen_pdus/Kconfig rename to drivers/sensor/wsen/wsen_pdus/Kconfig diff --git a/drivers/sensor/wsen_pdus/wsen_pdus.c b/drivers/sensor/wsen/wsen_pdus/wsen_pdus.c similarity index 100% rename from drivers/sensor/wsen_pdus/wsen_pdus.c rename to drivers/sensor/wsen/wsen_pdus/wsen_pdus.c diff --git a/drivers/sensor/wsen_pdus/wsen_pdus.h b/drivers/sensor/wsen/wsen_pdus/wsen_pdus.h similarity index 100% rename from drivers/sensor/wsen_pdus/wsen_pdus.h rename to drivers/sensor/wsen/wsen_pdus/wsen_pdus.h diff --git a/drivers/sensor/wsen_tids/CMakeLists.txt b/drivers/sensor/wsen/wsen_tids/CMakeLists.txt similarity index 100% rename from drivers/sensor/wsen_tids/CMakeLists.txt rename to drivers/sensor/wsen/wsen_tids/CMakeLists.txt diff --git a/drivers/sensor/wsen_tids/Kconfig b/drivers/sensor/wsen/wsen_tids/Kconfig similarity index 100% rename from drivers/sensor/wsen_tids/Kconfig rename to drivers/sensor/wsen/wsen_tids/Kconfig diff --git a/drivers/sensor/wsen_tids/wsen_tids.c b/drivers/sensor/wsen/wsen_tids/wsen_tids.c similarity index 100% rename from drivers/sensor/wsen_tids/wsen_tids.c rename to drivers/sensor/wsen/wsen_tids/wsen_tids.c diff --git a/drivers/sensor/wsen_tids/wsen_tids.h b/drivers/sensor/wsen/wsen_tids/wsen_tids.h similarity index 100% rename from drivers/sensor/wsen_tids/wsen_tids.h rename to drivers/sensor/wsen/wsen_tids/wsen_tids.h diff --git a/drivers/sensor/wsen_tids/wsen_tids_trigger.c b/drivers/sensor/wsen/wsen_tids/wsen_tids_trigger.c similarity index 100% rename from drivers/sensor/wsen_tids/wsen_tids_trigger.c rename to drivers/sensor/wsen/wsen_tids/wsen_tids_trigger.c From ec105cbf67fb6310d520b0c0d230cd842cd93f00 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Wed, 27 Mar 2024 19:02:02 -0500 Subject: [PATCH 1975/2402] drivers: sensor: ite: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- MAINTAINERS.yml | 2 +- drivers/sensor/CMakeLists.txt | 3 +-- drivers/sensor/Kconfig | 3 +-- drivers/sensor/ite/CMakeLists.txt | 7 +++++++ drivers/sensor/ite/Kconfig | 7 +++++++ drivers/sensor/{ => ite}/ite_tach_it8xxx2/CMakeLists.txt | 0 drivers/sensor/{ => ite}/ite_tach_it8xxx2/Kconfig | 0 .../sensor/{ => ite}/ite_tach_it8xxx2/tach_ite_it8xxx2.c | 0 drivers/sensor/{ => ite}/ite_vcmp_it8xxx2/CMakeLists.txt | 0 drivers/sensor/{ => ite}/ite_vcmp_it8xxx2/Kconfig | 0 .../sensor/{ => ite}/ite_vcmp_it8xxx2/vcmp_ite_it8xxx2.c | 0 11 files changed, 17 insertions(+), 5 deletions(-) create mode 100644 drivers/sensor/ite/CMakeLists.txt create mode 100644 drivers/sensor/ite/Kconfig rename drivers/sensor/{ => ite}/ite_tach_it8xxx2/CMakeLists.txt (100%) rename drivers/sensor/{ => ite}/ite_tach_it8xxx2/Kconfig (100%) rename drivers/sensor/{ => ite}/ite_tach_it8xxx2/tach_ite_it8xxx2.c (100%) rename drivers/sensor/{ => ite}/ite_vcmp_it8xxx2/CMakeLists.txt (100%) rename drivers/sensor/{ => ite}/ite_vcmp_it8xxx2/Kconfig (100%) rename drivers/sensor/{ => ite}/ite_vcmp_it8xxx2/vcmp_ite_it8xxx2.c (100%) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 1378b5ec23b..466c9682c74 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3596,7 +3596,7 @@ ITE Platforms: - sjg20 files: - boards/ite/ - - drivers/*/*/*it8xxx2*.c + - drivers/sensor/ite/ - drivers/*/*it8xxx2*.c - drivers/*/*_ite_* - dts/bindings/*/*ite* diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 708fc2f0e83..92943769188 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -4,6 +4,7 @@ add_subdirectory(adi) add_subdirectory(ams) add_subdirectory(bosch) +add_subdirectory(ite) add_subdirectory(maxim) add_subdirectory(microchip) add_subdirectory(nxp) @@ -67,11 +68,9 @@ add_subdirectory_ifdef(CONFIG_S11059 s11059) add_subdirectory_ifdef(CONFIG_SBS_GAUGE sbs_gauge) add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) -add_subdirectory_ifdef(CONFIG_TACH_IT8XXX2 ite_tach_it8xxx2) add_subdirectory_ifdef(CONFIG_TACH_NPCX nuvoton_tach_npcx) add_subdirectory_ifdef(CONFIG_TEMP_NRF5 nrf5) add_subdirectory_ifdef(CONFIG_TH02 th02) -add_subdirectory_ifdef(CONFIG_VCMP_IT8XXX2 ite_vcmp_it8xxx2) add_subdirectory_ifdef(CONFIG_VCNL4040 vcnl4040) add_subdirectory_ifdef(CONFIG_VCNL36825T vcnl36825t) add_subdirectory_ifdef(CONFIG_VEML7700 veml7700) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 162e92ae275..420f3034552 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -85,6 +85,7 @@ comment "Device Drivers" source "drivers/sensor/adi/Kconfig" source "drivers/sensor/ams/Kconfig" source "drivers/sensor/bosch/Kconfig" +source "drivers/sensor/ite/Kconfig" source "drivers/sensor/maxim/Kconfig" source "drivers/sensor/microchip/Kconfig" source "drivers/sensor/nxp/Kconfig" @@ -125,8 +126,6 @@ source "drivers/sensor/tdk/icm42688/Kconfig" source "drivers/sensor/tdk/icp10125/Kconfig" source "drivers/sensor/isl29035/Kconfig" source "drivers/sensor/ist8310/Kconfig" -source "drivers/sensor/ite_tach_it8xxx2/Kconfig" -source "drivers/sensor/ite_vcmp_it8xxx2/Kconfig" source "drivers/sensor/lm35/Kconfig" source "drivers/sensor/lm75/Kconfig" source "drivers/sensor/lm77/Kconfig" diff --git a/drivers/sensor/ite/CMakeLists.txt b/drivers/sensor/ite/CMakeLists.txt new file mode 100644 index 00000000000..68883d9bc0c --- /dev/null +++ b/drivers/sensor/ite/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_TACH_IT8XXX2 ite_tach_it8xxx2) +add_subdirectory_ifdef(CONFIG_VCMP_IT8XXX2 ite_vcmp_it8xxx2) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/ite/Kconfig b/drivers/sensor/ite/Kconfig new file mode 100644 index 00000000000..8d0bf169cea --- /dev/null +++ b/drivers/sensor/ite/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/ite/ite_tach_it8xxx2/Kconfig" +source "drivers/sensor/ite/ite_vcmp_it8xxx2/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/ite_tach_it8xxx2/CMakeLists.txt b/drivers/sensor/ite/ite_tach_it8xxx2/CMakeLists.txt similarity index 100% rename from drivers/sensor/ite_tach_it8xxx2/CMakeLists.txt rename to drivers/sensor/ite/ite_tach_it8xxx2/CMakeLists.txt diff --git a/drivers/sensor/ite_tach_it8xxx2/Kconfig b/drivers/sensor/ite/ite_tach_it8xxx2/Kconfig similarity index 100% rename from drivers/sensor/ite_tach_it8xxx2/Kconfig rename to drivers/sensor/ite/ite_tach_it8xxx2/Kconfig diff --git a/drivers/sensor/ite_tach_it8xxx2/tach_ite_it8xxx2.c b/drivers/sensor/ite/ite_tach_it8xxx2/tach_ite_it8xxx2.c similarity index 100% rename from drivers/sensor/ite_tach_it8xxx2/tach_ite_it8xxx2.c rename to drivers/sensor/ite/ite_tach_it8xxx2/tach_ite_it8xxx2.c diff --git a/drivers/sensor/ite_vcmp_it8xxx2/CMakeLists.txt b/drivers/sensor/ite/ite_vcmp_it8xxx2/CMakeLists.txt similarity index 100% rename from drivers/sensor/ite_vcmp_it8xxx2/CMakeLists.txt rename to drivers/sensor/ite/ite_vcmp_it8xxx2/CMakeLists.txt diff --git a/drivers/sensor/ite_vcmp_it8xxx2/Kconfig b/drivers/sensor/ite/ite_vcmp_it8xxx2/Kconfig similarity index 100% rename from drivers/sensor/ite_vcmp_it8xxx2/Kconfig rename to drivers/sensor/ite/ite_vcmp_it8xxx2/Kconfig diff --git a/drivers/sensor/ite_vcmp_it8xxx2/vcmp_ite_it8xxx2.c b/drivers/sensor/ite/ite_vcmp_it8xxx2/vcmp_ite_it8xxx2.c similarity index 100% rename from drivers/sensor/ite_vcmp_it8xxx2/vcmp_ite_it8xxx2.c rename to drivers/sensor/ite/ite_vcmp_it8xxx2/vcmp_ite_it8xxx2.c From 51e6cbddba8e27395958f306abb949c824f0dba0 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Wed, 27 Mar 2024 19:07:21 -0500 Subject: [PATCH 1976/2402] drivers: sensor: nordic: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 4 +--- drivers/sensor/Kconfig | 4 +--- drivers/sensor/nordic/CMakeLists.txt | 8 ++++++++ drivers/sensor/nordic/Kconfig | 8 ++++++++ .../sensor/{ => nordic}/npm1300_charger/CMakeLists.txt | 0 drivers/sensor/{ => nordic}/npm1300_charger/Kconfig | 0 .../sensor/{ => nordic}/npm1300_charger/npm1300_charger.c | 0 drivers/sensor/{ => nordic}/nrf5/CMakeLists.txt | 0 drivers/sensor/{ => nordic}/nrf5/Kconfig | 0 drivers/sensor/{ => nordic}/nrf5/temp_nrf5.c | 0 drivers/sensor/{ => nordic}/qdec_nrfx/CMakeLists.txt | 0 drivers/sensor/{ => nordic}/qdec_nrfx/Kconfig | 0 drivers/sensor/{ => nordic}/qdec_nrfx/qdec_nrfx.c | 0 13 files changed, 18 insertions(+), 6 deletions(-) create mode 100644 drivers/sensor/nordic/CMakeLists.txt create mode 100644 drivers/sensor/nordic/Kconfig rename drivers/sensor/{ => nordic}/npm1300_charger/CMakeLists.txt (100%) rename drivers/sensor/{ => nordic}/npm1300_charger/Kconfig (100%) rename drivers/sensor/{ => nordic}/npm1300_charger/npm1300_charger.c (100%) rename drivers/sensor/{ => nordic}/nrf5/CMakeLists.txt (100%) rename drivers/sensor/{ => nordic}/nrf5/Kconfig (100%) rename drivers/sensor/{ => nordic}/nrf5/temp_nrf5.c (100%) rename drivers/sensor/{ => nordic}/qdec_nrfx/CMakeLists.txt (100%) rename drivers/sensor/{ => nordic}/qdec_nrfx/Kconfig (100%) rename drivers/sensor/{ => nordic}/qdec_nrfx/qdec_nrfx.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 92943769188..8de5ace679b 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -7,6 +7,7 @@ add_subdirectory(bosch) add_subdirectory(ite) add_subdirectory(maxim) add_subdirectory(microchip) +add_subdirectory(nordic) add_subdirectory(nxp) add_subdirectory(sensirion) add_subdirectory(silabs) @@ -57,11 +58,9 @@ add_subdirectory_ifdef(CONFIG_MPU6050 tdk/mpu6050) add_subdirectory_ifdef(CONFIG_MPU9250 tdk/mpu9250) add_subdirectory_ifdef(CONFIG_MS5607 ms5607) add_subdirectory_ifdef(CONFIG_MS5837 ms5837) -add_subdirectory_ifdef(CONFIG_NPM1300_CHARGER npm1300_charger) add_subdirectory_ifdef(CONFIG_NTC_THERMISTOR ntc_thermistor) add_subdirectory_ifdef(CONFIG_PCNT_ESP32 pcnt_esp32) add_subdirectory_ifdef(CONFIG_PMS7003 pms7003) -add_subdirectory_ifdef(CONFIG_QDEC_NRFX qdec_nrfx) add_subdirectory_ifdef(CONFIG_QDEC_SAM qdec_sam) add_subdirectory_ifdef(CONFIG_RPI_PICO_TEMP rpi_pico_temp) add_subdirectory_ifdef(CONFIG_S11059 s11059) @@ -69,7 +68,6 @@ add_subdirectory_ifdef(CONFIG_SBS_GAUGE sbs_gauge) add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) add_subdirectory_ifdef(CONFIG_TACH_NPCX nuvoton_tach_npcx) -add_subdirectory_ifdef(CONFIG_TEMP_NRF5 nrf5) add_subdirectory_ifdef(CONFIG_TH02 th02) add_subdirectory_ifdef(CONFIG_VCNL4040 vcnl4040) add_subdirectory_ifdef(CONFIG_VCNL36825T vcnl36825t) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 420f3034552..a68b425478a 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -88,6 +88,7 @@ source "drivers/sensor/bosch/Kconfig" source "drivers/sensor/ite/Kconfig" source "drivers/sensor/maxim/Kconfig" source "drivers/sensor/microchip/Kconfig" +source "drivers/sensor/nordic/Kconfig" source "drivers/sensor/nxp/Kconfig" source "drivers/sensor/sensirion/Kconfig" source "drivers/sensor/silabs/Kconfig" @@ -137,14 +138,11 @@ source "drivers/sensor/tdk/mpu6050/Kconfig" source "drivers/sensor/tdk/mpu9250/Kconfig" source "drivers/sensor/ms5607/Kconfig" source "drivers/sensor/ms5837/Kconfig" -source "drivers/sensor/npm1300_charger/Kconfig" -source "drivers/sensor/nrf5/Kconfig" source "drivers/sensor/ntc_thermistor/Kconfig" source "drivers/sensor/nuvoton_adc_cmp_npcx/Kconfig" source "drivers/sensor/nuvoton_tach_npcx/Kconfig" source "drivers/sensor/pcnt_esp32/Kconfig" source "drivers/sensor/pms7003/Kconfig" -source "drivers/sensor/qdec_nrfx/Kconfig" source "drivers/sensor/qdec_sam/Kconfig" source "drivers/sensor/rpi_pico_temp/Kconfig" source "drivers/sensor/s11059/Kconfig" diff --git a/drivers/sensor/nordic/CMakeLists.txt b/drivers/sensor/nordic/CMakeLists.txt new file mode 100644 index 00000000000..0169664e6aa --- /dev/null +++ b/drivers/sensor/nordic/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_NPM1300_CHARGER npm1300_charger) +add_subdirectory_ifdef(CONFIG_QDEC_NRFX qdec_nrfx) +add_subdirectory_ifdef(CONFIG_TEMP_NRF5 nrf5) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/nordic/Kconfig b/drivers/sensor/nordic/Kconfig new file mode 100644 index 00000000000..42678ed2fcc --- /dev/null +++ b/drivers/sensor/nordic/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/nordic/npm1300_charger/Kconfig" +source "drivers/sensor/nordic/nrf5/Kconfig" +source "drivers/sensor/nordic/qdec_nrfx/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/npm1300_charger/CMakeLists.txt b/drivers/sensor/nordic/npm1300_charger/CMakeLists.txt similarity index 100% rename from drivers/sensor/npm1300_charger/CMakeLists.txt rename to drivers/sensor/nordic/npm1300_charger/CMakeLists.txt diff --git a/drivers/sensor/npm1300_charger/Kconfig b/drivers/sensor/nordic/npm1300_charger/Kconfig similarity index 100% rename from drivers/sensor/npm1300_charger/Kconfig rename to drivers/sensor/nordic/npm1300_charger/Kconfig diff --git a/drivers/sensor/npm1300_charger/npm1300_charger.c b/drivers/sensor/nordic/npm1300_charger/npm1300_charger.c similarity index 100% rename from drivers/sensor/npm1300_charger/npm1300_charger.c rename to drivers/sensor/nordic/npm1300_charger/npm1300_charger.c diff --git a/drivers/sensor/nrf5/CMakeLists.txt b/drivers/sensor/nordic/nrf5/CMakeLists.txt similarity index 100% rename from drivers/sensor/nrf5/CMakeLists.txt rename to drivers/sensor/nordic/nrf5/CMakeLists.txt diff --git a/drivers/sensor/nrf5/Kconfig b/drivers/sensor/nordic/nrf5/Kconfig similarity index 100% rename from drivers/sensor/nrf5/Kconfig rename to drivers/sensor/nordic/nrf5/Kconfig diff --git a/drivers/sensor/nrf5/temp_nrf5.c b/drivers/sensor/nordic/nrf5/temp_nrf5.c similarity index 100% rename from drivers/sensor/nrf5/temp_nrf5.c rename to drivers/sensor/nordic/nrf5/temp_nrf5.c diff --git a/drivers/sensor/qdec_nrfx/CMakeLists.txt b/drivers/sensor/nordic/qdec_nrfx/CMakeLists.txt similarity index 100% rename from drivers/sensor/qdec_nrfx/CMakeLists.txt rename to drivers/sensor/nordic/qdec_nrfx/CMakeLists.txt diff --git a/drivers/sensor/qdec_nrfx/Kconfig b/drivers/sensor/nordic/qdec_nrfx/Kconfig similarity index 100% rename from drivers/sensor/qdec_nrfx/Kconfig rename to drivers/sensor/nordic/qdec_nrfx/Kconfig diff --git a/drivers/sensor/qdec_nrfx/qdec_nrfx.c b/drivers/sensor/nordic/qdec_nrfx/qdec_nrfx.c similarity index 100% rename from drivers/sensor/qdec_nrfx/qdec_nrfx.c rename to drivers/sensor/nordic/qdec_nrfx/qdec_nrfx.c From addfa22b086989de799b4e4986dafef02b23c253 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Wed, 27 Mar 2024 19:10:39 -0500 Subject: [PATCH 1977/2402] drivers: sensor: nuvoton: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 3 +-- drivers/sensor/Kconfig | 3 +-- drivers/sensor/nuvoton/CMakeLists.txt | 7 +++++++ drivers/sensor/nuvoton/Kconfig | 7 +++++++ .../{ => nuvoton}/nuvoton_adc_cmp_npcx/CMakeLists.txt | 0 drivers/sensor/{ => nuvoton}/nuvoton_adc_cmp_npcx/Kconfig | 0 .../{ => nuvoton}/nuvoton_adc_cmp_npcx/adc_cmp_npcx.c | 0 .../sensor/{ => nuvoton}/nuvoton_tach_npcx/CMakeLists.txt | 0 drivers/sensor/{ => nuvoton}/nuvoton_tach_npcx/Kconfig | 0 .../{ => nuvoton}/nuvoton_tach_npcx/tach_nuvoton_npcx.c | 0 10 files changed, 16 insertions(+), 4 deletions(-) create mode 100644 drivers/sensor/nuvoton/CMakeLists.txt create mode 100644 drivers/sensor/nuvoton/Kconfig rename drivers/sensor/{ => nuvoton}/nuvoton_adc_cmp_npcx/CMakeLists.txt (100%) rename drivers/sensor/{ => nuvoton}/nuvoton_adc_cmp_npcx/Kconfig (100%) rename drivers/sensor/{ => nuvoton}/nuvoton_adc_cmp_npcx/adc_cmp_npcx.c (100%) rename drivers/sensor/{ => nuvoton}/nuvoton_tach_npcx/CMakeLists.txt (100%) rename drivers/sensor/{ => nuvoton}/nuvoton_tach_npcx/Kconfig (100%) rename drivers/sensor/{ => nuvoton}/nuvoton_tach_npcx/tach_nuvoton_npcx.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 8de5ace679b..cfbdbb6c377 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -8,6 +8,7 @@ add_subdirectory(ite) add_subdirectory(maxim) add_subdirectory(microchip) add_subdirectory(nordic) +add_subdirectory(nuvoton) add_subdirectory(nxp) add_subdirectory(sensirion) add_subdirectory(silabs) @@ -17,7 +18,6 @@ add_subdirectory(wsen) # zephyr-keep-sorted-stop add_subdirectory_ifdef(CONFIG_A01NYUB a01nyub) -add_subdirectory_ifdef(CONFIG_ADC_CMP_NPCX nuvoton_adc_cmp_npcx) add_subdirectory_ifdef(CONFIG_AGS10 ags10) add_subdirectory_ifdef(CONFIG_AK8975 ak8975) add_subdirectory_ifdef(CONFIG_AKM09918C akm09918c) @@ -67,7 +67,6 @@ add_subdirectory_ifdef(CONFIG_S11059 s11059) add_subdirectory_ifdef(CONFIG_SBS_GAUGE sbs_gauge) add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) -add_subdirectory_ifdef(CONFIG_TACH_NPCX nuvoton_tach_npcx) add_subdirectory_ifdef(CONFIG_TH02 th02) add_subdirectory_ifdef(CONFIG_VCNL4040 vcnl4040) add_subdirectory_ifdef(CONFIG_VCNL36825T vcnl36825t) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index a68b425478a..870e2cc3428 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -89,6 +89,7 @@ source "drivers/sensor/ite/Kconfig" source "drivers/sensor/maxim/Kconfig" source "drivers/sensor/microchip/Kconfig" source "drivers/sensor/nordic/Kconfig" +source "drivers/sensor/nuvoton/Kconfig" source "drivers/sensor/nxp/Kconfig" source "drivers/sensor/sensirion/Kconfig" source "drivers/sensor/silabs/Kconfig" @@ -139,8 +140,6 @@ source "drivers/sensor/tdk/mpu9250/Kconfig" source "drivers/sensor/ms5607/Kconfig" source "drivers/sensor/ms5837/Kconfig" source "drivers/sensor/ntc_thermistor/Kconfig" -source "drivers/sensor/nuvoton_adc_cmp_npcx/Kconfig" -source "drivers/sensor/nuvoton_tach_npcx/Kconfig" source "drivers/sensor/pcnt_esp32/Kconfig" source "drivers/sensor/pms7003/Kconfig" source "drivers/sensor/qdec_sam/Kconfig" diff --git a/drivers/sensor/nuvoton/CMakeLists.txt b/drivers/sensor/nuvoton/CMakeLists.txt new file mode 100644 index 00000000000..70a8385ba6c --- /dev/null +++ b/drivers/sensor/nuvoton/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_ADC_CMP_NPCX nuvoton_adc_cmp_npcx) +add_subdirectory_ifdef(CONFIG_TACH_NPCX nuvoton_tach_npcx) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/nuvoton/Kconfig b/drivers/sensor/nuvoton/Kconfig new file mode 100644 index 00000000000..64893f2c565 --- /dev/null +++ b/drivers/sensor/nuvoton/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/nuvoton/nuvoton_adc_cmp_npcx/Kconfig" +source "drivers/sensor/nuvoton/nuvoton_tach_npcx/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/nuvoton_adc_cmp_npcx/CMakeLists.txt b/drivers/sensor/nuvoton/nuvoton_adc_cmp_npcx/CMakeLists.txt similarity index 100% rename from drivers/sensor/nuvoton_adc_cmp_npcx/CMakeLists.txt rename to drivers/sensor/nuvoton/nuvoton_adc_cmp_npcx/CMakeLists.txt diff --git a/drivers/sensor/nuvoton_adc_cmp_npcx/Kconfig b/drivers/sensor/nuvoton/nuvoton_adc_cmp_npcx/Kconfig similarity index 100% rename from drivers/sensor/nuvoton_adc_cmp_npcx/Kconfig rename to drivers/sensor/nuvoton/nuvoton_adc_cmp_npcx/Kconfig diff --git a/drivers/sensor/nuvoton_adc_cmp_npcx/adc_cmp_npcx.c b/drivers/sensor/nuvoton/nuvoton_adc_cmp_npcx/adc_cmp_npcx.c similarity index 100% rename from drivers/sensor/nuvoton_adc_cmp_npcx/adc_cmp_npcx.c rename to drivers/sensor/nuvoton/nuvoton_adc_cmp_npcx/adc_cmp_npcx.c diff --git a/drivers/sensor/nuvoton_tach_npcx/CMakeLists.txt b/drivers/sensor/nuvoton/nuvoton_tach_npcx/CMakeLists.txt similarity index 100% rename from drivers/sensor/nuvoton_tach_npcx/CMakeLists.txt rename to drivers/sensor/nuvoton/nuvoton_tach_npcx/CMakeLists.txt diff --git a/drivers/sensor/nuvoton_tach_npcx/Kconfig b/drivers/sensor/nuvoton/nuvoton_tach_npcx/Kconfig similarity index 100% rename from drivers/sensor/nuvoton_tach_npcx/Kconfig rename to drivers/sensor/nuvoton/nuvoton_tach_npcx/Kconfig diff --git a/drivers/sensor/nuvoton_tach_npcx/tach_nuvoton_npcx.c b/drivers/sensor/nuvoton/nuvoton_tach_npcx/tach_nuvoton_npcx.c similarity index 100% rename from drivers/sensor/nuvoton_tach_npcx/tach_nuvoton_npcx.c rename to drivers/sensor/nuvoton/nuvoton_tach_npcx/tach_nuvoton_npcx.c From b52d5e20a11a8222a10b181b678290368e495637 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Wed, 27 Mar 2024 19:16:07 -0500 Subject: [PATCH 1978/2402] drivers: sensor: rohm: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 3 +-- drivers/sensor/Kconfig | 3 +-- drivers/sensor/rohm/CMakeLists.txt | 7 +++++++ drivers/sensor/rohm/Kconfig | 7 +++++++ drivers/sensor/{ => rohm}/bd8lb600fs/CMakeLists.txt | 0 drivers/sensor/{ => rohm}/bd8lb600fs/Kconfig | 0 .../sensor/{ => rohm}/bd8lb600fs/bd8lb600fs_diagnostics.c | 0 .../sensor/{ => rohm}/bd8lb600fs/bd8lb600fs_diagnostics.h | 0 drivers/sensor/{ => rohm}/bh1750/CMakeLists.txt | 0 drivers/sensor/{ => rohm}/bh1750/Kconfig | 0 drivers/sensor/{ => rohm}/bh1750/bh1750.c | 0 11 files changed, 16 insertions(+), 4 deletions(-) create mode 100644 drivers/sensor/rohm/CMakeLists.txt create mode 100644 drivers/sensor/rohm/Kconfig rename drivers/sensor/{ => rohm}/bd8lb600fs/CMakeLists.txt (100%) rename drivers/sensor/{ => rohm}/bd8lb600fs/Kconfig (100%) rename drivers/sensor/{ => rohm}/bd8lb600fs/bd8lb600fs_diagnostics.c (100%) rename drivers/sensor/{ => rohm}/bd8lb600fs/bd8lb600fs_diagnostics.h (100%) rename drivers/sensor/{ => rohm}/bh1750/CMakeLists.txt (100%) rename drivers/sensor/{ => rohm}/bh1750/Kconfig (100%) rename drivers/sensor/{ => rohm}/bh1750/bh1750.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index cfbdbb6c377..db4d92216bb 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -10,6 +10,7 @@ add_subdirectory(microchip) add_subdirectory(nordic) add_subdirectory(nuvoton) add_subdirectory(nxp) +add_subdirectory(rohm) add_subdirectory(sensirion) add_subdirectory(silabs) add_subdirectory(st) @@ -24,8 +25,6 @@ add_subdirectory_ifdef(CONFIG_AKM09918C akm09918c) add_subdirectory_ifdef(CONFIG_AMD_SB_TSI amd_sb_tsi) add_subdirectory_ifdef(CONFIG_AMG88XX amg88xx) add_subdirectory_ifdef(CONFIG_APDS9960 apds9960) -add_subdirectory_ifdef(CONFIG_BD8LB600FS_DIAGNOSTICS bd8lb600fs) -add_subdirectory_ifdef(CONFIG_BH1750 bh1750) add_subdirectory_ifdef(CONFIG_CURRENT_AMP current_amp) add_subdirectory_ifdef(CONFIG_DHT dht) add_subdirectory_ifdef(CONFIG_DHT20 dht20) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 870e2cc3428..b52877b3634 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -91,6 +91,7 @@ source "drivers/sensor/microchip/Kconfig" source "drivers/sensor/nordic/Kconfig" source "drivers/sensor/nuvoton/Kconfig" source "drivers/sensor/nxp/Kconfig" +source "drivers/sensor/rohm/Kconfig" source "drivers/sensor/sensirion/Kconfig" source "drivers/sensor/silabs/Kconfig" source "drivers/sensor/st/Kconfig" @@ -105,8 +106,6 @@ source "drivers/sensor/akm09918c/Kconfig" source "drivers/sensor/amd_sb_tsi/Kconfig" source "drivers/sensor/amg88xx/Kconfig" source "drivers/sensor/apds9960/Kconfig" -source "drivers/sensor/bd8lb600fs/Kconfig" -source "drivers/sensor/bh1750/Kconfig" source "drivers/sensor/current_amp/Kconfig" source "drivers/sensor/dht/Kconfig" source "drivers/sensor/dht20/Kconfig" diff --git a/drivers/sensor/rohm/CMakeLists.txt b/drivers/sensor/rohm/CMakeLists.txt new file mode 100644 index 00000000000..629421e3272 --- /dev/null +++ b/drivers/sensor/rohm/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_BD8LB600FS_DIAGNOSTICS bd8lb600fs) +add_subdirectory_ifdef(CONFIG_BH1750 bh1750) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/rohm/Kconfig b/drivers/sensor/rohm/Kconfig new file mode 100644 index 00000000000..c03de16d89e --- /dev/null +++ b/drivers/sensor/rohm/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/rohm/bd8lb600fs/Kconfig" +source "drivers/sensor/rohm/bh1750/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/bd8lb600fs/CMakeLists.txt b/drivers/sensor/rohm/bd8lb600fs/CMakeLists.txt similarity index 100% rename from drivers/sensor/bd8lb600fs/CMakeLists.txt rename to drivers/sensor/rohm/bd8lb600fs/CMakeLists.txt diff --git a/drivers/sensor/bd8lb600fs/Kconfig b/drivers/sensor/rohm/bd8lb600fs/Kconfig similarity index 100% rename from drivers/sensor/bd8lb600fs/Kconfig rename to drivers/sensor/rohm/bd8lb600fs/Kconfig diff --git a/drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.c b/drivers/sensor/rohm/bd8lb600fs/bd8lb600fs_diagnostics.c similarity index 100% rename from drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.c rename to drivers/sensor/rohm/bd8lb600fs/bd8lb600fs_diagnostics.c diff --git a/drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.h b/drivers/sensor/rohm/bd8lb600fs/bd8lb600fs_diagnostics.h similarity index 100% rename from drivers/sensor/bd8lb600fs/bd8lb600fs_diagnostics.h rename to drivers/sensor/rohm/bd8lb600fs/bd8lb600fs_diagnostics.h diff --git a/drivers/sensor/bh1750/CMakeLists.txt b/drivers/sensor/rohm/bh1750/CMakeLists.txt similarity index 100% rename from drivers/sensor/bh1750/CMakeLists.txt rename to drivers/sensor/rohm/bh1750/CMakeLists.txt diff --git a/drivers/sensor/bh1750/Kconfig b/drivers/sensor/rohm/bh1750/Kconfig similarity index 100% rename from drivers/sensor/bh1750/Kconfig rename to drivers/sensor/rohm/bh1750/Kconfig diff --git a/drivers/sensor/bh1750/bh1750.c b/drivers/sensor/rohm/bh1750/bh1750.c similarity index 100% rename from drivers/sensor/bh1750/bh1750.c rename to drivers/sensor/rohm/bh1750/bh1750.c From 77a53a21b1bb33bb0d753256af68f72750ba3e63 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Wed, 27 Mar 2024 19:21:00 -0500 Subject: [PATCH 1979/2402] drivers: sensor: seeed: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 3 +-- drivers/sensor/Kconfig | 3 +-- drivers/sensor/seeed/CMakeLists.txt | 7 +++++++ drivers/sensor/seeed/Kconfig | 7 +++++++ drivers/sensor/{ => seeed}/grove/CMakeLists.txt | 0 drivers/sensor/{ => seeed}/grove/Kconfig | 0 drivers/sensor/{ => seeed}/grove/light_sensor.c | 0 drivers/sensor/{ => seeed}/grove/temperature_sensor.c | 0 drivers/sensor/{ => seeed}/hm330x/CMakeLists.txt | 0 drivers/sensor/{ => seeed}/hm330x/Kconfig | 0 drivers/sensor/{ => seeed}/hm330x/hm330x.c | 0 11 files changed, 16 insertions(+), 4 deletions(-) create mode 100644 drivers/sensor/seeed/CMakeLists.txt create mode 100644 drivers/sensor/seeed/Kconfig rename drivers/sensor/{ => seeed}/grove/CMakeLists.txt (100%) rename drivers/sensor/{ => seeed}/grove/Kconfig (100%) rename drivers/sensor/{ => seeed}/grove/light_sensor.c (100%) rename drivers/sensor/{ => seeed}/grove/temperature_sensor.c (100%) rename drivers/sensor/{ => seeed}/hm330x/CMakeLists.txt (100%) rename drivers/sensor/{ => seeed}/hm330x/Kconfig (100%) rename drivers/sensor/{ => seeed}/hm330x/hm330x.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index db4d92216bb..2eb781db995 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -11,6 +11,7 @@ add_subdirectory(nordic) add_subdirectory(nuvoton) add_subdirectory(nxp) add_subdirectory(rohm) +add_subdirectory(seeed) add_subdirectory(sensirion) add_subdirectory(silabs) add_subdirectory(st) @@ -34,9 +35,7 @@ add_subdirectory_ifdef(CONFIG_ESP32_TEMP esp32_temp) add_subdirectory_ifdef(CONFIG_EXPLORIR_M explorir_m) add_subdirectory_ifdef(CONFIG_F75303 f75303) add_subdirectory_ifdef(CONFIG_FCX_MLDX5 fcx_mldx5) -add_subdirectory_ifdef(CONFIG_GROVE_SENSORS grove) add_subdirectory_ifdef(CONFIG_GROW_R502A grow_r502a) -add_subdirectory_ifdef(CONFIG_HM330X hm330x) add_subdirectory_ifdef(CONFIG_HMC5883L hmc5883l) add_subdirectory_ifdef(CONFIG_HP206C hp206c) add_subdirectory_ifdef(CONFIG_HS300X hs300x) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index b52877b3634..3c9aa6e85f4 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -92,6 +92,7 @@ source "drivers/sensor/nordic/Kconfig" source "drivers/sensor/nuvoton/Kconfig" source "drivers/sensor/nxp/Kconfig" source "drivers/sensor/rohm/Kconfig" +source "drivers/sensor/seeed/Kconfig" source "drivers/sensor/sensirion/Kconfig" source "drivers/sensor/silabs/Kconfig" source "drivers/sensor/st/Kconfig" @@ -115,9 +116,7 @@ source "drivers/sensor/esp32_temp/Kconfig" source "drivers/sensor/explorir_m/Kconfig" source "drivers/sensor/f75303/Kconfig" source "drivers/sensor/fcx_mldx5/Kconfig" -source "drivers/sensor/grove/Kconfig" source "drivers/sensor/grow_r502a/Kconfig" -source "drivers/sensor/hm330x/Kconfig" source "drivers/sensor/hmc5883l/Kconfig" source "drivers/sensor/hp206c/Kconfig" source "drivers/sensor/hs300x/Kconfig" diff --git a/drivers/sensor/seeed/CMakeLists.txt b/drivers/sensor/seeed/CMakeLists.txt new file mode 100644 index 00000000000..569f83a541a --- /dev/null +++ b/drivers/sensor/seeed/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_GROVE_SENSORS grove) +add_subdirectory_ifdef(CONFIG_HM330X hm330x) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/seeed/Kconfig b/drivers/sensor/seeed/Kconfig new file mode 100644 index 00000000000..4c5156cdff8 --- /dev/null +++ b/drivers/sensor/seeed/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/seeed/grove/Kconfig" +source "drivers/sensor/seeed/hm330x/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/grove/CMakeLists.txt b/drivers/sensor/seeed/grove/CMakeLists.txt similarity index 100% rename from drivers/sensor/grove/CMakeLists.txt rename to drivers/sensor/seeed/grove/CMakeLists.txt diff --git a/drivers/sensor/grove/Kconfig b/drivers/sensor/seeed/grove/Kconfig similarity index 100% rename from drivers/sensor/grove/Kconfig rename to drivers/sensor/seeed/grove/Kconfig diff --git a/drivers/sensor/grove/light_sensor.c b/drivers/sensor/seeed/grove/light_sensor.c similarity index 100% rename from drivers/sensor/grove/light_sensor.c rename to drivers/sensor/seeed/grove/light_sensor.c diff --git a/drivers/sensor/grove/temperature_sensor.c b/drivers/sensor/seeed/grove/temperature_sensor.c similarity index 100% rename from drivers/sensor/grove/temperature_sensor.c rename to drivers/sensor/seeed/grove/temperature_sensor.c diff --git a/drivers/sensor/hm330x/CMakeLists.txt b/drivers/sensor/seeed/hm330x/CMakeLists.txt similarity index 100% rename from drivers/sensor/hm330x/CMakeLists.txt rename to drivers/sensor/seeed/hm330x/CMakeLists.txt diff --git a/drivers/sensor/hm330x/Kconfig b/drivers/sensor/seeed/hm330x/Kconfig similarity index 100% rename from drivers/sensor/hm330x/Kconfig rename to drivers/sensor/seeed/hm330x/Kconfig diff --git a/drivers/sensor/hm330x/hm330x.c b/drivers/sensor/seeed/hm330x/hm330x.c similarity index 100% rename from drivers/sensor/hm330x/hm330x.c rename to drivers/sensor/seeed/hm330x/hm330x.c From 8e46dc01ba70e0e378a97dd02dca5041673969cc Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Thu, 4 Apr 2024 18:21:18 -0500 Subject: [PATCH 1980/2402] drivers: sensor: vishay: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 4 +--- drivers/sensor/Kconfig | 4 +--- drivers/sensor/vishay/CMakeLists.txt | 8 ++++++++ drivers/sensor/vishay/Kconfig | 8 ++++++++ drivers/sensor/{ => vishay}/vcnl36825t/CMakeLists.txt | 0 drivers/sensor/{ => vishay}/vcnl36825t/Kconfig | 0 drivers/sensor/{ => vishay}/vcnl36825t/vcnl36825t.c | 0 drivers/sensor/{ => vishay}/vcnl36825t/vcnl36825t.h | 0 drivers/sensor/{ => vishay}/vcnl4040/CMakeLists.txt | 0 drivers/sensor/{ => vishay}/vcnl4040/Kconfig | 0 drivers/sensor/{ => vishay}/vcnl4040/vcnl4040.c | 0 drivers/sensor/{ => vishay}/vcnl4040/vcnl4040.h | 0 drivers/sensor/{ => vishay}/vcnl4040/vcnl4040_trigger.c | 0 drivers/sensor/{ => vishay}/veml7700/CMakeLists.txt | 0 drivers/sensor/{ => vishay}/veml7700/Kconfig | 0 drivers/sensor/{ => vishay}/veml7700/veml7700.c | 0 16 files changed, 18 insertions(+), 6 deletions(-) create mode 100644 drivers/sensor/vishay/CMakeLists.txt create mode 100644 drivers/sensor/vishay/Kconfig rename drivers/sensor/{ => vishay}/vcnl36825t/CMakeLists.txt (100%) rename drivers/sensor/{ => vishay}/vcnl36825t/Kconfig (100%) rename drivers/sensor/{ => vishay}/vcnl36825t/vcnl36825t.c (100%) rename drivers/sensor/{ => vishay}/vcnl36825t/vcnl36825t.h (100%) rename drivers/sensor/{ => vishay}/vcnl4040/CMakeLists.txt (100%) rename drivers/sensor/{ => vishay}/vcnl4040/Kconfig (100%) rename drivers/sensor/{ => vishay}/vcnl4040/vcnl4040.c (100%) rename drivers/sensor/{ => vishay}/vcnl4040/vcnl4040.h (100%) rename drivers/sensor/{ => vishay}/vcnl4040/vcnl4040_trigger.c (100%) rename drivers/sensor/{ => vishay}/veml7700/CMakeLists.txt (100%) rename drivers/sensor/{ => vishay}/veml7700/Kconfig (100%) rename drivers/sensor/{ => vishay}/veml7700/veml7700.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 2eb781db995..66d71083a03 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -16,6 +16,7 @@ add_subdirectory(sensirion) add_subdirectory(silabs) add_subdirectory(st) add_subdirectory(ti) +add_subdirectory(vishay) add_subdirectory(wsen) # zephyr-keep-sorted-stop @@ -66,9 +67,6 @@ add_subdirectory_ifdef(CONFIG_SBS_GAUGE sbs_gauge) add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) add_subdirectory_ifdef(CONFIG_TH02 th02) -add_subdirectory_ifdef(CONFIG_VCNL4040 vcnl4040) -add_subdirectory_ifdef(CONFIG_VCNL36825T vcnl36825t) -add_subdirectory_ifdef(CONFIG_VEML7700 veml7700) add_subdirectory_ifdef(CONFIG_VOLTAGE_DIVIDER voltage_divider) add_subdirectory_ifdef(CONFIG_XMC4XXX_TEMP xmc4xxx_temp) add_subdirectory_ifdef(CONFIG_TACH_ENE_KB1200 ene_tach_kb1200) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 3c9aa6e85f4..87fafefc0e5 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -97,6 +97,7 @@ source "drivers/sensor/sensirion/Kconfig" source "drivers/sensor/silabs/Kconfig" source "drivers/sensor/st/Kconfig" source "drivers/sensor/ti/Kconfig" +source "drivers/sensor/vishay/Kconfig" source "drivers/sensor/wsen/Kconfig" # zephyr-keep-sorted-stop @@ -147,9 +148,6 @@ source "drivers/sensor/sbs_gauge/Kconfig" source "drivers/sensor/sm351lt/Kconfig" source "drivers/sensor/sx9500/Kconfig" source "drivers/sensor/th02/Kconfig" -source "drivers/sensor/vcnl4040/Kconfig" -source "drivers/sensor/vcnl36825t/Kconfig" -source "drivers/sensor/veml7700/Kconfig" source "drivers/sensor/voltage_divider/Kconfig" source "drivers/sensor/xmc4xxx_temp/Kconfig" source "drivers/sensor/ene_tach_kb1200/Kconfig" diff --git a/drivers/sensor/vishay/CMakeLists.txt b/drivers/sensor/vishay/CMakeLists.txt new file mode 100644 index 00000000000..51f0b77fde7 --- /dev/null +++ b/drivers/sensor/vishay/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_VCNL36825T vcnl36825t) +add_subdirectory_ifdef(CONFIG_VCNL4040 vcnl4040) +add_subdirectory_ifdef(CONFIG_VEML7700 veml7700) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/vishay/Kconfig b/drivers/sensor/vishay/Kconfig new file mode 100644 index 00000000000..e11eb201193 --- /dev/null +++ b/drivers/sensor/vishay/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/vishay/vcnl36825t/Kconfig" +source "drivers/sensor/vishay/vcnl4040/Kconfig" +source "drivers/sensor/vishay/veml7700/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/vcnl36825t/CMakeLists.txt b/drivers/sensor/vishay/vcnl36825t/CMakeLists.txt similarity index 100% rename from drivers/sensor/vcnl36825t/CMakeLists.txt rename to drivers/sensor/vishay/vcnl36825t/CMakeLists.txt diff --git a/drivers/sensor/vcnl36825t/Kconfig b/drivers/sensor/vishay/vcnl36825t/Kconfig similarity index 100% rename from drivers/sensor/vcnl36825t/Kconfig rename to drivers/sensor/vishay/vcnl36825t/Kconfig diff --git a/drivers/sensor/vcnl36825t/vcnl36825t.c b/drivers/sensor/vishay/vcnl36825t/vcnl36825t.c similarity index 100% rename from drivers/sensor/vcnl36825t/vcnl36825t.c rename to drivers/sensor/vishay/vcnl36825t/vcnl36825t.c diff --git a/drivers/sensor/vcnl36825t/vcnl36825t.h b/drivers/sensor/vishay/vcnl36825t/vcnl36825t.h similarity index 100% rename from drivers/sensor/vcnl36825t/vcnl36825t.h rename to drivers/sensor/vishay/vcnl36825t/vcnl36825t.h diff --git a/drivers/sensor/vcnl4040/CMakeLists.txt b/drivers/sensor/vishay/vcnl4040/CMakeLists.txt similarity index 100% rename from drivers/sensor/vcnl4040/CMakeLists.txt rename to drivers/sensor/vishay/vcnl4040/CMakeLists.txt diff --git a/drivers/sensor/vcnl4040/Kconfig b/drivers/sensor/vishay/vcnl4040/Kconfig similarity index 100% rename from drivers/sensor/vcnl4040/Kconfig rename to drivers/sensor/vishay/vcnl4040/Kconfig diff --git a/drivers/sensor/vcnl4040/vcnl4040.c b/drivers/sensor/vishay/vcnl4040/vcnl4040.c similarity index 100% rename from drivers/sensor/vcnl4040/vcnl4040.c rename to drivers/sensor/vishay/vcnl4040/vcnl4040.c diff --git a/drivers/sensor/vcnl4040/vcnl4040.h b/drivers/sensor/vishay/vcnl4040/vcnl4040.h similarity index 100% rename from drivers/sensor/vcnl4040/vcnl4040.h rename to drivers/sensor/vishay/vcnl4040/vcnl4040.h diff --git a/drivers/sensor/vcnl4040/vcnl4040_trigger.c b/drivers/sensor/vishay/vcnl4040/vcnl4040_trigger.c similarity index 100% rename from drivers/sensor/vcnl4040/vcnl4040_trigger.c rename to drivers/sensor/vishay/vcnl4040/vcnl4040_trigger.c diff --git a/drivers/sensor/veml7700/CMakeLists.txt b/drivers/sensor/vishay/veml7700/CMakeLists.txt similarity index 100% rename from drivers/sensor/veml7700/CMakeLists.txt rename to drivers/sensor/vishay/veml7700/CMakeLists.txt diff --git a/drivers/sensor/veml7700/Kconfig b/drivers/sensor/vishay/veml7700/Kconfig similarity index 100% rename from drivers/sensor/veml7700/Kconfig rename to drivers/sensor/vishay/veml7700/Kconfig diff --git a/drivers/sensor/veml7700/veml7700.c b/drivers/sensor/vishay/veml7700/veml7700.c similarity index 100% rename from drivers/sensor/veml7700/veml7700.c rename to drivers/sensor/vishay/veml7700/veml7700.c From eedccf7e96f3184aaf25e18963d03ea50d71f2de Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Thu, 4 Apr 2024 18:31:04 -0500 Subject: [PATCH 1981/2402] drivers: sensor: aosong: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 4 +--- drivers/sensor/Kconfig | 4 +--- drivers/sensor/aosong/CMakeLists.txt | 8 ++++++++ drivers/sensor/aosong/Kconfig | 8 ++++++++ drivers/sensor/{ => aosong}/ags10/CMakeLists.txt | 0 drivers/sensor/{ => aosong}/ags10/Kconfig | 0 drivers/sensor/{ => aosong}/ags10/ags10.c | 0 drivers/sensor/{ => aosong}/ags10/ags10.h | 0 drivers/sensor/{ => aosong}/dht/CMakeLists.txt | 0 drivers/sensor/{ => aosong}/dht/Kconfig | 0 drivers/sensor/{ => aosong}/dht/dht.c | 0 drivers/sensor/{ => aosong}/dht/dht.h | 0 drivers/sensor/{ => aosong}/dht20/CMakeLists.txt | 0 drivers/sensor/{ => aosong}/dht20/Kconfig | 0 drivers/sensor/{ => aosong}/dht20/dht20.c | 0 15 files changed, 18 insertions(+), 6 deletions(-) create mode 100644 drivers/sensor/aosong/CMakeLists.txt create mode 100644 drivers/sensor/aosong/Kconfig rename drivers/sensor/{ => aosong}/ags10/CMakeLists.txt (100%) rename drivers/sensor/{ => aosong}/ags10/Kconfig (100%) rename drivers/sensor/{ => aosong}/ags10/ags10.c (100%) rename drivers/sensor/{ => aosong}/ags10/ags10.h (100%) rename drivers/sensor/{ => aosong}/dht/CMakeLists.txt (100%) rename drivers/sensor/{ => aosong}/dht/Kconfig (100%) rename drivers/sensor/{ => aosong}/dht/dht.c (100%) rename drivers/sensor/{ => aosong}/dht/dht.h (100%) rename drivers/sensor/{ => aosong}/dht20/CMakeLists.txt (100%) rename drivers/sensor/{ => aosong}/dht20/Kconfig (100%) rename drivers/sensor/{ => aosong}/dht20/dht20.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 66d71083a03..db680f5f72d 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -3,6 +3,7 @@ # zephyr-keep-sorted-start add_subdirectory(adi) add_subdirectory(ams) +add_subdirectory(aosong) add_subdirectory(bosch) add_subdirectory(ite) add_subdirectory(maxim) @@ -21,15 +22,12 @@ add_subdirectory(wsen) # zephyr-keep-sorted-stop add_subdirectory_ifdef(CONFIG_A01NYUB a01nyub) -add_subdirectory_ifdef(CONFIG_AGS10 ags10) add_subdirectory_ifdef(CONFIG_AK8975 ak8975) add_subdirectory_ifdef(CONFIG_AKM09918C akm09918c) add_subdirectory_ifdef(CONFIG_AMD_SB_TSI amd_sb_tsi) add_subdirectory_ifdef(CONFIG_AMG88XX amg88xx) add_subdirectory_ifdef(CONFIG_APDS9960 apds9960) add_subdirectory_ifdef(CONFIG_CURRENT_AMP current_amp) -add_subdirectory_ifdef(CONFIG_DHT dht) -add_subdirectory_ifdef(CONFIG_DHT20 dht20) add_subdirectory_ifdef(CONFIG_DPS310 dps310) add_subdirectory_ifdef(CONFIG_ENS160 ens160) add_subdirectory_ifdef(CONFIG_ESP32_TEMP esp32_temp) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 87fafefc0e5..0acbff5f0c2 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -84,6 +84,7 @@ comment "Device Drivers" # zephyr-keep-sorted-start source "drivers/sensor/adi/Kconfig" source "drivers/sensor/ams/Kconfig" +source "drivers/sensor/aosong/Kconfig" source "drivers/sensor/bosch/Kconfig" source "drivers/sensor/ite/Kconfig" source "drivers/sensor/maxim/Kconfig" @@ -102,15 +103,12 @@ source "drivers/sensor/wsen/Kconfig" # zephyr-keep-sorted-stop source "drivers/sensor/a01nyub/Kconfig" -source "drivers/sensor/ags10/Kconfig" source "drivers/sensor/ak8975/Kconfig" source "drivers/sensor/akm09918c/Kconfig" source "drivers/sensor/amd_sb_tsi/Kconfig" source "drivers/sensor/amg88xx/Kconfig" source "drivers/sensor/apds9960/Kconfig" source "drivers/sensor/current_amp/Kconfig" -source "drivers/sensor/dht/Kconfig" -source "drivers/sensor/dht20/Kconfig" source "drivers/sensor/dps310/Kconfig" source "drivers/sensor/ens160/Kconfig" source "drivers/sensor/esp32_temp/Kconfig" diff --git a/drivers/sensor/aosong/CMakeLists.txt b/drivers/sensor/aosong/CMakeLists.txt new file mode 100644 index 00000000000..a4895d6cfb3 --- /dev/null +++ b/drivers/sensor/aosong/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_AGS10 ags10) +add_subdirectory_ifdef(CONFIG_DHT dht) +add_subdirectory_ifdef(CONFIG_DHT20 dht20) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/aosong/Kconfig b/drivers/sensor/aosong/Kconfig new file mode 100644 index 00000000000..19d229d38ab --- /dev/null +++ b/drivers/sensor/aosong/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/aosong/ags10/Kconfig" +source "drivers/sensor/aosong/dht/Kconfig" +source "drivers/sensor/aosong/dht20/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/ags10/CMakeLists.txt b/drivers/sensor/aosong/ags10/CMakeLists.txt similarity index 100% rename from drivers/sensor/ags10/CMakeLists.txt rename to drivers/sensor/aosong/ags10/CMakeLists.txt diff --git a/drivers/sensor/ags10/Kconfig b/drivers/sensor/aosong/ags10/Kconfig similarity index 100% rename from drivers/sensor/ags10/Kconfig rename to drivers/sensor/aosong/ags10/Kconfig diff --git a/drivers/sensor/ags10/ags10.c b/drivers/sensor/aosong/ags10/ags10.c similarity index 100% rename from drivers/sensor/ags10/ags10.c rename to drivers/sensor/aosong/ags10/ags10.c diff --git a/drivers/sensor/ags10/ags10.h b/drivers/sensor/aosong/ags10/ags10.h similarity index 100% rename from drivers/sensor/ags10/ags10.h rename to drivers/sensor/aosong/ags10/ags10.h diff --git a/drivers/sensor/dht/CMakeLists.txt b/drivers/sensor/aosong/dht/CMakeLists.txt similarity index 100% rename from drivers/sensor/dht/CMakeLists.txt rename to drivers/sensor/aosong/dht/CMakeLists.txt diff --git a/drivers/sensor/dht/Kconfig b/drivers/sensor/aosong/dht/Kconfig similarity index 100% rename from drivers/sensor/dht/Kconfig rename to drivers/sensor/aosong/dht/Kconfig diff --git a/drivers/sensor/dht/dht.c b/drivers/sensor/aosong/dht/dht.c similarity index 100% rename from drivers/sensor/dht/dht.c rename to drivers/sensor/aosong/dht/dht.c diff --git a/drivers/sensor/dht/dht.h b/drivers/sensor/aosong/dht/dht.h similarity index 100% rename from drivers/sensor/dht/dht.h rename to drivers/sensor/aosong/dht/dht.h diff --git a/drivers/sensor/dht20/CMakeLists.txt b/drivers/sensor/aosong/dht20/CMakeLists.txt similarity index 100% rename from drivers/sensor/dht20/CMakeLists.txt rename to drivers/sensor/aosong/dht20/CMakeLists.txt diff --git a/drivers/sensor/dht20/Kconfig b/drivers/sensor/aosong/dht20/Kconfig similarity index 100% rename from drivers/sensor/dht20/Kconfig rename to drivers/sensor/aosong/dht20/Kconfig diff --git a/drivers/sensor/dht20/dht20.c b/drivers/sensor/aosong/dht20/dht20.c similarity index 100% rename from drivers/sensor/dht20/dht20.c rename to drivers/sensor/aosong/dht20/dht20.c From 5d79eced22cf200af5e7e4b491f2b2a4068e9921 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Thu, 4 Apr 2024 18:38:34 -0500 Subject: [PATCH 1982/2402] drivers: sensor: honeywell: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 4 +--- drivers/sensor/Kconfig | 4 +--- drivers/sensor/honeywell/CMakeLists.txt | 8 ++++++++ drivers/sensor/honeywell/Kconfig | 8 ++++++++ drivers/sensor/{ => honeywell}/hmc5883l/CMakeLists.txt | 0 drivers/sensor/{ => honeywell}/hmc5883l/Kconfig | 0 drivers/sensor/{ => honeywell}/hmc5883l/hmc5883l.c | 0 drivers/sensor/{ => honeywell}/hmc5883l/hmc5883l.h | 0 .../sensor/{ => honeywell}/hmc5883l/hmc5883l_trigger.c | 0 drivers/sensor/{ => honeywell}/mpr/CMakeLists.txt | 0 drivers/sensor/{ => honeywell}/mpr/Kconfig | 0 drivers/sensor/{ => honeywell}/mpr/mpr.c | 0 drivers/sensor/{ => honeywell}/mpr/mpr.h | 0 drivers/sensor/{ => honeywell}/mpr/mpr_configuration.h | 0 drivers/sensor/{ => honeywell}/sm351lt/CMakeLists.txt | 0 drivers/sensor/{ => honeywell}/sm351lt/Kconfig | 0 drivers/sensor/{ => honeywell}/sm351lt/sm351lt.c | 0 drivers/sensor/{ => honeywell}/sm351lt/sm351lt.h | 0 18 files changed, 18 insertions(+), 6 deletions(-) create mode 100644 drivers/sensor/honeywell/CMakeLists.txt create mode 100644 drivers/sensor/honeywell/Kconfig rename drivers/sensor/{ => honeywell}/hmc5883l/CMakeLists.txt (100%) rename drivers/sensor/{ => honeywell}/hmc5883l/Kconfig (100%) rename drivers/sensor/{ => honeywell}/hmc5883l/hmc5883l.c (100%) rename drivers/sensor/{ => honeywell}/hmc5883l/hmc5883l.h (100%) rename drivers/sensor/{ => honeywell}/hmc5883l/hmc5883l_trigger.c (100%) rename drivers/sensor/{ => honeywell}/mpr/CMakeLists.txt (100%) rename drivers/sensor/{ => honeywell}/mpr/Kconfig (100%) rename drivers/sensor/{ => honeywell}/mpr/mpr.c (100%) rename drivers/sensor/{ => honeywell}/mpr/mpr.h (100%) rename drivers/sensor/{ => honeywell}/mpr/mpr_configuration.h (100%) rename drivers/sensor/{ => honeywell}/sm351lt/CMakeLists.txt (100%) rename drivers/sensor/{ => honeywell}/sm351lt/Kconfig (100%) rename drivers/sensor/{ => honeywell}/sm351lt/sm351lt.c (100%) rename drivers/sensor/{ => honeywell}/sm351lt/sm351lt.h (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index db680f5f72d..ea00d33128d 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -5,6 +5,7 @@ add_subdirectory(adi) add_subdirectory(ams) add_subdirectory(aosong) add_subdirectory(bosch) +add_subdirectory(honeywell) add_subdirectory(ite) add_subdirectory(maxim) add_subdirectory(microchip) @@ -35,7 +36,6 @@ add_subdirectory_ifdef(CONFIG_EXPLORIR_M explorir_m) add_subdirectory_ifdef(CONFIG_F75303 f75303) add_subdirectory_ifdef(CONFIG_FCX_MLDX5 fcx_mldx5) add_subdirectory_ifdef(CONFIG_GROW_R502A grow_r502a) -add_subdirectory_ifdef(CONFIG_HMC5883L hmc5883l) add_subdirectory_ifdef(CONFIG_HP206C hp206c) add_subdirectory_ifdef(CONFIG_HS300X hs300x) add_subdirectory_ifdef(CONFIG_ICM42605 tdk/icm42605) @@ -50,7 +50,6 @@ add_subdirectory_ifdef(CONFIG_LM77 lm77) add_subdirectory_ifdef(CONFIG_LTR_F216A ltrf216a) add_subdirectory_ifdef(CONFIG_MC3419 mc3419) add_subdirectory_ifdef(CONFIG_MHZ19B mhz19b) -add_subdirectory_ifdef(CONFIG_MPR mpr) add_subdirectory_ifdef(CONFIG_MPU6050 tdk/mpu6050) add_subdirectory_ifdef(CONFIG_MPU9250 tdk/mpu9250) add_subdirectory_ifdef(CONFIG_MS5607 ms5607) @@ -62,7 +61,6 @@ add_subdirectory_ifdef(CONFIG_QDEC_SAM qdec_sam) add_subdirectory_ifdef(CONFIG_RPI_PICO_TEMP rpi_pico_temp) add_subdirectory_ifdef(CONFIG_S11059 s11059) add_subdirectory_ifdef(CONFIG_SBS_GAUGE sbs_gauge) -add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) add_subdirectory_ifdef(CONFIG_TH02 th02) add_subdirectory_ifdef(CONFIG_VOLTAGE_DIVIDER voltage_divider) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 0acbff5f0c2..dc97f2b0e9f 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -86,6 +86,7 @@ source "drivers/sensor/adi/Kconfig" source "drivers/sensor/ams/Kconfig" source "drivers/sensor/aosong/Kconfig" source "drivers/sensor/bosch/Kconfig" +source "drivers/sensor/honeywell/Kconfig" source "drivers/sensor/ite/Kconfig" source "drivers/sensor/maxim/Kconfig" source "drivers/sensor/microchip/Kconfig" @@ -116,7 +117,6 @@ source "drivers/sensor/explorir_m/Kconfig" source "drivers/sensor/f75303/Kconfig" source "drivers/sensor/fcx_mldx5/Kconfig" source "drivers/sensor/grow_r502a/Kconfig" -source "drivers/sensor/hmc5883l/Kconfig" source "drivers/sensor/hp206c/Kconfig" source "drivers/sensor/hs300x/Kconfig" source "drivers/sensor/tdk/icm42605/Kconfig" @@ -131,7 +131,6 @@ source "drivers/sensor/lm77/Kconfig" source "drivers/sensor/ltrf216a/Kconfig" source "drivers/sensor/mc3419/Kconfig" source "drivers/sensor/mhz19b/Kconfig" -source "drivers/sensor/mpr/Kconfig" source "drivers/sensor/tdk/mpu6050/Kconfig" source "drivers/sensor/tdk/mpu9250/Kconfig" source "drivers/sensor/ms5607/Kconfig" @@ -143,7 +142,6 @@ source "drivers/sensor/qdec_sam/Kconfig" source "drivers/sensor/rpi_pico_temp/Kconfig" source "drivers/sensor/s11059/Kconfig" source "drivers/sensor/sbs_gauge/Kconfig" -source "drivers/sensor/sm351lt/Kconfig" source "drivers/sensor/sx9500/Kconfig" source "drivers/sensor/th02/Kconfig" source "drivers/sensor/voltage_divider/Kconfig" diff --git a/drivers/sensor/honeywell/CMakeLists.txt b/drivers/sensor/honeywell/CMakeLists.txt new file mode 100644 index 00000000000..05dba3ca218 --- /dev/null +++ b/drivers/sensor/honeywell/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_HMC5883L hmc5883l) +add_subdirectory_ifdef(CONFIG_MPR mpr) +add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/honeywell/Kconfig b/drivers/sensor/honeywell/Kconfig new file mode 100644 index 00000000000..e0c2a1e6a32 --- /dev/null +++ b/drivers/sensor/honeywell/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/honeywell/hmc5883l/Kconfig" +source "drivers/sensor/honeywell/mpr/Kconfig" +source "drivers/sensor/honeywell/sm351lt/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/hmc5883l/CMakeLists.txt b/drivers/sensor/honeywell/hmc5883l/CMakeLists.txt similarity index 100% rename from drivers/sensor/hmc5883l/CMakeLists.txt rename to drivers/sensor/honeywell/hmc5883l/CMakeLists.txt diff --git a/drivers/sensor/hmc5883l/Kconfig b/drivers/sensor/honeywell/hmc5883l/Kconfig similarity index 100% rename from drivers/sensor/hmc5883l/Kconfig rename to drivers/sensor/honeywell/hmc5883l/Kconfig diff --git a/drivers/sensor/hmc5883l/hmc5883l.c b/drivers/sensor/honeywell/hmc5883l/hmc5883l.c similarity index 100% rename from drivers/sensor/hmc5883l/hmc5883l.c rename to drivers/sensor/honeywell/hmc5883l/hmc5883l.c diff --git a/drivers/sensor/hmc5883l/hmc5883l.h b/drivers/sensor/honeywell/hmc5883l/hmc5883l.h similarity index 100% rename from drivers/sensor/hmc5883l/hmc5883l.h rename to drivers/sensor/honeywell/hmc5883l/hmc5883l.h diff --git a/drivers/sensor/hmc5883l/hmc5883l_trigger.c b/drivers/sensor/honeywell/hmc5883l/hmc5883l_trigger.c similarity index 100% rename from drivers/sensor/hmc5883l/hmc5883l_trigger.c rename to drivers/sensor/honeywell/hmc5883l/hmc5883l_trigger.c diff --git a/drivers/sensor/mpr/CMakeLists.txt b/drivers/sensor/honeywell/mpr/CMakeLists.txt similarity index 100% rename from drivers/sensor/mpr/CMakeLists.txt rename to drivers/sensor/honeywell/mpr/CMakeLists.txt diff --git a/drivers/sensor/mpr/Kconfig b/drivers/sensor/honeywell/mpr/Kconfig similarity index 100% rename from drivers/sensor/mpr/Kconfig rename to drivers/sensor/honeywell/mpr/Kconfig diff --git a/drivers/sensor/mpr/mpr.c b/drivers/sensor/honeywell/mpr/mpr.c similarity index 100% rename from drivers/sensor/mpr/mpr.c rename to drivers/sensor/honeywell/mpr/mpr.c diff --git a/drivers/sensor/mpr/mpr.h b/drivers/sensor/honeywell/mpr/mpr.h similarity index 100% rename from drivers/sensor/mpr/mpr.h rename to drivers/sensor/honeywell/mpr/mpr.h diff --git a/drivers/sensor/mpr/mpr_configuration.h b/drivers/sensor/honeywell/mpr/mpr_configuration.h similarity index 100% rename from drivers/sensor/mpr/mpr_configuration.h rename to drivers/sensor/honeywell/mpr/mpr_configuration.h diff --git a/drivers/sensor/sm351lt/CMakeLists.txt b/drivers/sensor/honeywell/sm351lt/CMakeLists.txt similarity index 100% rename from drivers/sensor/sm351lt/CMakeLists.txt rename to drivers/sensor/honeywell/sm351lt/CMakeLists.txt diff --git a/drivers/sensor/sm351lt/Kconfig b/drivers/sensor/honeywell/sm351lt/Kconfig similarity index 100% rename from drivers/sensor/sm351lt/Kconfig rename to drivers/sensor/honeywell/sm351lt/Kconfig diff --git a/drivers/sensor/sm351lt/sm351lt.c b/drivers/sensor/honeywell/sm351lt/sm351lt.c similarity index 100% rename from drivers/sensor/sm351lt/sm351lt.c rename to drivers/sensor/honeywell/sm351lt/sm351lt.c diff --git a/drivers/sensor/sm351lt/sm351lt.h b/drivers/sensor/honeywell/sm351lt/sm351lt.h similarity index 100% rename from drivers/sensor/sm351lt/sm351lt.h rename to drivers/sensor/honeywell/sm351lt/sm351lt.h From 1b1954649b56d94832f1e0d7cb93182007e19f68 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Thu, 4 Apr 2024 18:45:50 -0500 Subject: [PATCH 1983/2402] drivers: sensor: infineon: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- MAINTAINERS.yml | 2 +- drivers/sensor/CMakeLists.txt | 3 +-- drivers/sensor/Kconfig | 3 +-- drivers/sensor/infineon/CMakeLists.txt | 7 +++++++ drivers/sensor/infineon/Kconfig | 7 +++++++ drivers/sensor/{ => infineon}/dps310/CMakeLists.txt | 0 drivers/sensor/{ => infineon}/dps310/Kconfig | 0 drivers/sensor/{ => infineon}/dps310/dps310.c | 0 drivers/sensor/{ => infineon}/xmc4xxx_temp/CMakeLists.txt | 0 drivers/sensor/{ => infineon}/xmc4xxx_temp/Kconfig | 0 drivers/sensor/{ => infineon}/xmc4xxx_temp/xmc4xxx_temp.c | 0 11 files changed, 17 insertions(+), 5 deletions(-) create mode 100644 drivers/sensor/infineon/CMakeLists.txt create mode 100644 drivers/sensor/infineon/Kconfig rename drivers/sensor/{ => infineon}/dps310/CMakeLists.txt (100%) rename drivers/sensor/{ => infineon}/dps310/Kconfig (100%) rename drivers/sensor/{ => infineon}/dps310/dps310.c (100%) rename drivers/sensor/{ => infineon}/xmc4xxx_temp/CMakeLists.txt (100%) rename drivers/sensor/{ => infineon}/xmc4xxx_temp/Kconfig (100%) rename drivers/sensor/{ => infineon}/xmc4xxx_temp/xmc4xxx_temp.c (100%) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 466c9682c74..4786168d8ac 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3676,7 +3676,7 @@ Infineon Platforms: - drivers/*/*ifx_cat1* - drivers/*/*xmc*/ - drivers/*/*xmc*.c - - drivers/*/*/*xmc* + - drivers/sensor/infineon/ - dts/arm/infineon/ - dts/arm/cypress/ - soc/cypress/ diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index ea00d33128d..8f671f40d21 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -6,6 +6,7 @@ add_subdirectory(ams) add_subdirectory(aosong) add_subdirectory(bosch) add_subdirectory(honeywell) +add_subdirectory(infineon) add_subdirectory(ite) add_subdirectory(maxim) add_subdirectory(microchip) @@ -29,7 +30,6 @@ add_subdirectory_ifdef(CONFIG_AMD_SB_TSI amd_sb_tsi) add_subdirectory_ifdef(CONFIG_AMG88XX amg88xx) add_subdirectory_ifdef(CONFIG_APDS9960 apds9960) add_subdirectory_ifdef(CONFIG_CURRENT_AMP current_amp) -add_subdirectory_ifdef(CONFIG_DPS310 dps310) add_subdirectory_ifdef(CONFIG_ENS160 ens160) add_subdirectory_ifdef(CONFIG_ESP32_TEMP esp32_temp) add_subdirectory_ifdef(CONFIG_EXPLORIR_M explorir_m) @@ -64,7 +64,6 @@ add_subdirectory_ifdef(CONFIG_SBS_GAUGE sbs_gauge) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) add_subdirectory_ifdef(CONFIG_TH02 th02) add_subdirectory_ifdef(CONFIG_VOLTAGE_DIVIDER voltage_divider) -add_subdirectory_ifdef(CONFIG_XMC4XXX_TEMP xmc4xxx_temp) add_subdirectory_ifdef(CONFIG_TACH_ENE_KB1200 ene_tach_kb1200) zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/sensor.h) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index dc97f2b0e9f..08d3172bb17 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -87,6 +87,7 @@ source "drivers/sensor/ams/Kconfig" source "drivers/sensor/aosong/Kconfig" source "drivers/sensor/bosch/Kconfig" source "drivers/sensor/honeywell/Kconfig" +source "drivers/sensor/infineon/Kconfig" source "drivers/sensor/ite/Kconfig" source "drivers/sensor/maxim/Kconfig" source "drivers/sensor/microchip/Kconfig" @@ -110,7 +111,6 @@ source "drivers/sensor/amd_sb_tsi/Kconfig" source "drivers/sensor/amg88xx/Kconfig" source "drivers/sensor/apds9960/Kconfig" source "drivers/sensor/current_amp/Kconfig" -source "drivers/sensor/dps310/Kconfig" source "drivers/sensor/ens160/Kconfig" source "drivers/sensor/esp32_temp/Kconfig" source "drivers/sensor/explorir_m/Kconfig" @@ -145,7 +145,6 @@ source "drivers/sensor/sbs_gauge/Kconfig" source "drivers/sensor/sx9500/Kconfig" source "drivers/sensor/th02/Kconfig" source "drivers/sensor/voltage_divider/Kconfig" -source "drivers/sensor/xmc4xxx_temp/Kconfig" source "drivers/sensor/ene_tach_kb1200/Kconfig" endif # SENSOR diff --git a/drivers/sensor/infineon/CMakeLists.txt b/drivers/sensor/infineon/CMakeLists.txt new file mode 100644 index 00000000000..5c0afd3c4e3 --- /dev/null +++ b/drivers/sensor/infineon/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_DPS310 dps310) +add_subdirectory_ifdef(CONFIG_XMC4XXX_TEMP xmc4xxx_temp) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/infineon/Kconfig b/drivers/sensor/infineon/Kconfig new file mode 100644 index 00000000000..92d95d20fbb --- /dev/null +++ b/drivers/sensor/infineon/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/infineon/dps310/Kconfig" +source "drivers/sensor/infineon/xmc4xxx_temp/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/dps310/CMakeLists.txt b/drivers/sensor/infineon/dps310/CMakeLists.txt similarity index 100% rename from drivers/sensor/dps310/CMakeLists.txt rename to drivers/sensor/infineon/dps310/CMakeLists.txt diff --git a/drivers/sensor/dps310/Kconfig b/drivers/sensor/infineon/dps310/Kconfig similarity index 100% rename from drivers/sensor/dps310/Kconfig rename to drivers/sensor/infineon/dps310/Kconfig diff --git a/drivers/sensor/dps310/dps310.c b/drivers/sensor/infineon/dps310/dps310.c similarity index 100% rename from drivers/sensor/dps310/dps310.c rename to drivers/sensor/infineon/dps310/dps310.c diff --git a/drivers/sensor/xmc4xxx_temp/CMakeLists.txt b/drivers/sensor/infineon/xmc4xxx_temp/CMakeLists.txt similarity index 100% rename from drivers/sensor/xmc4xxx_temp/CMakeLists.txt rename to drivers/sensor/infineon/xmc4xxx_temp/CMakeLists.txt diff --git a/drivers/sensor/xmc4xxx_temp/Kconfig b/drivers/sensor/infineon/xmc4xxx_temp/Kconfig similarity index 100% rename from drivers/sensor/xmc4xxx_temp/Kconfig rename to drivers/sensor/infineon/xmc4xxx_temp/Kconfig diff --git a/drivers/sensor/xmc4xxx_temp/xmc4xxx_temp.c b/drivers/sensor/infineon/xmc4xxx_temp/xmc4xxx_temp.c similarity index 100% rename from drivers/sensor/xmc4xxx_temp/xmc4xxx_temp.c rename to drivers/sensor/infineon/xmc4xxx_temp/xmc4xxx_temp.c From 3127ffb4415a90221356073b4a3aaa98e2359dd6 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Thu, 4 Apr 2024 18:50:58 -0500 Subject: [PATCH 1984/2402] drivers: sensor: espressif: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 3 +-- drivers/sensor/Kconfig | 3 +-- drivers/sensor/espressif/CMakeLists.txt | 7 +++++++ drivers/sensor/espressif/Kconfig | 7 +++++++ drivers/sensor/{ => espressif}/esp32_temp/CMakeLists.txt | 0 drivers/sensor/{ => espressif}/esp32_temp/Kconfig | 0 drivers/sensor/{ => espressif}/esp32_temp/esp32_temp.c | 0 drivers/sensor/{ => espressif}/pcnt_esp32/CMakeLists.txt | 0 drivers/sensor/{ => espressif}/pcnt_esp32/Kconfig | 0 drivers/sensor/{ => espressif}/pcnt_esp32/pcnt_esp32.c | 0 10 files changed, 16 insertions(+), 4 deletions(-) create mode 100644 drivers/sensor/espressif/CMakeLists.txt create mode 100644 drivers/sensor/espressif/Kconfig rename drivers/sensor/{ => espressif}/esp32_temp/CMakeLists.txt (100%) rename drivers/sensor/{ => espressif}/esp32_temp/Kconfig (100%) rename drivers/sensor/{ => espressif}/esp32_temp/esp32_temp.c (100%) rename drivers/sensor/{ => espressif}/pcnt_esp32/CMakeLists.txt (100%) rename drivers/sensor/{ => espressif}/pcnt_esp32/Kconfig (100%) rename drivers/sensor/{ => espressif}/pcnt_esp32/pcnt_esp32.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 8f671f40d21..6813ab7e93f 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -5,6 +5,7 @@ add_subdirectory(adi) add_subdirectory(ams) add_subdirectory(aosong) add_subdirectory(bosch) +add_subdirectory(espressif) add_subdirectory(honeywell) add_subdirectory(infineon) add_subdirectory(ite) @@ -31,7 +32,6 @@ add_subdirectory_ifdef(CONFIG_AMG88XX amg88xx) add_subdirectory_ifdef(CONFIG_APDS9960 apds9960) add_subdirectory_ifdef(CONFIG_CURRENT_AMP current_amp) add_subdirectory_ifdef(CONFIG_ENS160 ens160) -add_subdirectory_ifdef(CONFIG_ESP32_TEMP esp32_temp) add_subdirectory_ifdef(CONFIG_EXPLORIR_M explorir_m) add_subdirectory_ifdef(CONFIG_F75303 f75303) add_subdirectory_ifdef(CONFIG_FCX_MLDX5 fcx_mldx5) @@ -55,7 +55,6 @@ add_subdirectory_ifdef(CONFIG_MPU9250 tdk/mpu9250) add_subdirectory_ifdef(CONFIG_MS5607 ms5607) add_subdirectory_ifdef(CONFIG_MS5837 ms5837) add_subdirectory_ifdef(CONFIG_NTC_THERMISTOR ntc_thermistor) -add_subdirectory_ifdef(CONFIG_PCNT_ESP32 pcnt_esp32) add_subdirectory_ifdef(CONFIG_PMS7003 pms7003) add_subdirectory_ifdef(CONFIG_QDEC_SAM qdec_sam) add_subdirectory_ifdef(CONFIG_RPI_PICO_TEMP rpi_pico_temp) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 08d3172bb17..8db1b49525f 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -86,6 +86,7 @@ source "drivers/sensor/adi/Kconfig" source "drivers/sensor/ams/Kconfig" source "drivers/sensor/aosong/Kconfig" source "drivers/sensor/bosch/Kconfig" +source "drivers/sensor/espressif/Kconfig" source "drivers/sensor/honeywell/Kconfig" source "drivers/sensor/infineon/Kconfig" source "drivers/sensor/ite/Kconfig" @@ -112,7 +113,6 @@ source "drivers/sensor/amg88xx/Kconfig" source "drivers/sensor/apds9960/Kconfig" source "drivers/sensor/current_amp/Kconfig" source "drivers/sensor/ens160/Kconfig" -source "drivers/sensor/esp32_temp/Kconfig" source "drivers/sensor/explorir_m/Kconfig" source "drivers/sensor/f75303/Kconfig" source "drivers/sensor/fcx_mldx5/Kconfig" @@ -136,7 +136,6 @@ source "drivers/sensor/tdk/mpu9250/Kconfig" source "drivers/sensor/ms5607/Kconfig" source "drivers/sensor/ms5837/Kconfig" source "drivers/sensor/ntc_thermistor/Kconfig" -source "drivers/sensor/pcnt_esp32/Kconfig" source "drivers/sensor/pms7003/Kconfig" source "drivers/sensor/qdec_sam/Kconfig" source "drivers/sensor/rpi_pico_temp/Kconfig" diff --git a/drivers/sensor/espressif/CMakeLists.txt b/drivers/sensor/espressif/CMakeLists.txt new file mode 100644 index 00000000000..52ef203de9a --- /dev/null +++ b/drivers/sensor/espressif/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_ESP32_TEMP esp32_temp) +add_subdirectory_ifdef(CONFIG_PCNT_ESP32 pcnt_esp32) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/espressif/Kconfig b/drivers/sensor/espressif/Kconfig new file mode 100644 index 00000000000..ef4985a7440 --- /dev/null +++ b/drivers/sensor/espressif/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/espressif/esp32_temp/Kconfig" +source "drivers/sensor/espressif/pcnt_esp32/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/esp32_temp/CMakeLists.txt b/drivers/sensor/espressif/esp32_temp/CMakeLists.txt similarity index 100% rename from drivers/sensor/esp32_temp/CMakeLists.txt rename to drivers/sensor/espressif/esp32_temp/CMakeLists.txt diff --git a/drivers/sensor/esp32_temp/Kconfig b/drivers/sensor/espressif/esp32_temp/Kconfig similarity index 100% rename from drivers/sensor/esp32_temp/Kconfig rename to drivers/sensor/espressif/esp32_temp/Kconfig diff --git a/drivers/sensor/esp32_temp/esp32_temp.c b/drivers/sensor/espressif/esp32_temp/esp32_temp.c similarity index 100% rename from drivers/sensor/esp32_temp/esp32_temp.c rename to drivers/sensor/espressif/esp32_temp/esp32_temp.c diff --git a/drivers/sensor/pcnt_esp32/CMakeLists.txt b/drivers/sensor/espressif/pcnt_esp32/CMakeLists.txt similarity index 100% rename from drivers/sensor/pcnt_esp32/CMakeLists.txt rename to drivers/sensor/espressif/pcnt_esp32/CMakeLists.txt diff --git a/drivers/sensor/pcnt_esp32/Kconfig b/drivers/sensor/espressif/pcnt_esp32/Kconfig similarity index 100% rename from drivers/sensor/pcnt_esp32/Kconfig rename to drivers/sensor/espressif/pcnt_esp32/Kconfig diff --git a/drivers/sensor/pcnt_esp32/pcnt_esp32.c b/drivers/sensor/espressif/pcnt_esp32/pcnt_esp32.c similarity index 100% rename from drivers/sensor/pcnt_esp32/pcnt_esp32.c rename to drivers/sensor/espressif/pcnt_esp32/pcnt_esp32.c From b6fd6eafa11d60b9ce05d4bafeb2fa46e6dd2c03 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Thu, 4 Apr 2024 18:57:34 -0500 Subject: [PATCH 1985/2402] drivers: sensor: asahi_kasei: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 3 +-- drivers/sensor/Kconfig | 3 +-- drivers/sensor/asahi_kasei/CMakeLists.txt | 7 +++++++ drivers/sensor/asahi_kasei/Kconfig | 7 +++++++ drivers/sensor/{ => asahi_kasei}/ak8975/CMakeLists.txt | 0 drivers/sensor/{ => asahi_kasei}/ak8975/Kconfig | 0 drivers/sensor/{ => asahi_kasei}/ak8975/ak8975.c | 0 drivers/sensor/{ => asahi_kasei}/ak8975/ak8975.h | 0 drivers/sensor/{ => asahi_kasei}/akm09918c/CMakeLists.txt | 0 drivers/sensor/{ => asahi_kasei}/akm09918c/Kconfig | 0 drivers/sensor/{ => asahi_kasei}/akm09918c/akm09918c.c | 0 drivers/sensor/{ => asahi_kasei}/akm09918c/akm09918c.h | 0 .../sensor/{ => asahi_kasei}/akm09918c/akm09918c_async.c | 0 .../sensor/{ => asahi_kasei}/akm09918c/akm09918c_decoder.c | 0 .../sensor/{ => asahi_kasei}/akm09918c/akm09918c_emul.c | 0 .../sensor/{ => asahi_kasei}/akm09918c/akm09918c_emul.h | 0 drivers/sensor/{ => asahi_kasei}/akm09918c/akm09918c_reg.h | 0 17 files changed, 16 insertions(+), 4 deletions(-) create mode 100644 drivers/sensor/asahi_kasei/CMakeLists.txt create mode 100644 drivers/sensor/asahi_kasei/Kconfig rename drivers/sensor/{ => asahi_kasei}/ak8975/CMakeLists.txt (100%) rename drivers/sensor/{ => asahi_kasei}/ak8975/Kconfig (100%) rename drivers/sensor/{ => asahi_kasei}/ak8975/ak8975.c (100%) rename drivers/sensor/{ => asahi_kasei}/ak8975/ak8975.h (100%) rename drivers/sensor/{ => asahi_kasei}/akm09918c/CMakeLists.txt (100%) rename drivers/sensor/{ => asahi_kasei}/akm09918c/Kconfig (100%) rename drivers/sensor/{ => asahi_kasei}/akm09918c/akm09918c.c (100%) rename drivers/sensor/{ => asahi_kasei}/akm09918c/akm09918c.h (100%) rename drivers/sensor/{ => asahi_kasei}/akm09918c/akm09918c_async.c (100%) rename drivers/sensor/{ => asahi_kasei}/akm09918c/akm09918c_decoder.c (100%) rename drivers/sensor/{ => asahi_kasei}/akm09918c/akm09918c_emul.c (100%) rename drivers/sensor/{ => asahi_kasei}/akm09918c/akm09918c_emul.h (100%) rename drivers/sensor/{ => asahi_kasei}/akm09918c/akm09918c_reg.h (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 6813ab7e93f..4833fb6db64 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -4,6 +4,7 @@ add_subdirectory(adi) add_subdirectory(ams) add_subdirectory(aosong) +add_subdirectory(asahi_kasei) add_subdirectory(bosch) add_subdirectory(espressif) add_subdirectory(honeywell) @@ -25,8 +26,6 @@ add_subdirectory(wsen) # zephyr-keep-sorted-stop add_subdirectory_ifdef(CONFIG_A01NYUB a01nyub) -add_subdirectory_ifdef(CONFIG_AK8975 ak8975) -add_subdirectory_ifdef(CONFIG_AKM09918C akm09918c) add_subdirectory_ifdef(CONFIG_AMD_SB_TSI amd_sb_tsi) add_subdirectory_ifdef(CONFIG_AMG88XX amg88xx) add_subdirectory_ifdef(CONFIG_APDS9960 apds9960) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 8db1b49525f..fd4aad01adb 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -85,6 +85,7 @@ comment "Device Drivers" source "drivers/sensor/adi/Kconfig" source "drivers/sensor/ams/Kconfig" source "drivers/sensor/aosong/Kconfig" +source "drivers/sensor/asahi_kasei/Kconfig" source "drivers/sensor/bosch/Kconfig" source "drivers/sensor/espressif/Kconfig" source "drivers/sensor/honeywell/Kconfig" @@ -106,8 +107,6 @@ source "drivers/sensor/wsen/Kconfig" # zephyr-keep-sorted-stop source "drivers/sensor/a01nyub/Kconfig" -source "drivers/sensor/ak8975/Kconfig" -source "drivers/sensor/akm09918c/Kconfig" source "drivers/sensor/amd_sb_tsi/Kconfig" source "drivers/sensor/amg88xx/Kconfig" source "drivers/sensor/apds9960/Kconfig" diff --git a/drivers/sensor/asahi_kasei/CMakeLists.txt b/drivers/sensor/asahi_kasei/CMakeLists.txt new file mode 100644 index 00000000000..579b0e85738 --- /dev/null +++ b/drivers/sensor/asahi_kasei/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_AK8975 ak8975) +add_subdirectory_ifdef(CONFIG_AKM09918C akm09918c) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/asahi_kasei/Kconfig b/drivers/sensor/asahi_kasei/Kconfig new file mode 100644 index 00000000000..d89726e37e1 --- /dev/null +++ b/drivers/sensor/asahi_kasei/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/asahi_kasei/ak8975/Kconfig" +source "drivers/sensor/asahi_kasei/akm09918c/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/ak8975/CMakeLists.txt b/drivers/sensor/asahi_kasei/ak8975/CMakeLists.txt similarity index 100% rename from drivers/sensor/ak8975/CMakeLists.txt rename to drivers/sensor/asahi_kasei/ak8975/CMakeLists.txt diff --git a/drivers/sensor/ak8975/Kconfig b/drivers/sensor/asahi_kasei/ak8975/Kconfig similarity index 100% rename from drivers/sensor/ak8975/Kconfig rename to drivers/sensor/asahi_kasei/ak8975/Kconfig diff --git a/drivers/sensor/ak8975/ak8975.c b/drivers/sensor/asahi_kasei/ak8975/ak8975.c similarity index 100% rename from drivers/sensor/ak8975/ak8975.c rename to drivers/sensor/asahi_kasei/ak8975/ak8975.c diff --git a/drivers/sensor/ak8975/ak8975.h b/drivers/sensor/asahi_kasei/ak8975/ak8975.h similarity index 100% rename from drivers/sensor/ak8975/ak8975.h rename to drivers/sensor/asahi_kasei/ak8975/ak8975.h diff --git a/drivers/sensor/akm09918c/CMakeLists.txt b/drivers/sensor/asahi_kasei/akm09918c/CMakeLists.txt similarity index 100% rename from drivers/sensor/akm09918c/CMakeLists.txt rename to drivers/sensor/asahi_kasei/akm09918c/CMakeLists.txt diff --git a/drivers/sensor/akm09918c/Kconfig b/drivers/sensor/asahi_kasei/akm09918c/Kconfig similarity index 100% rename from drivers/sensor/akm09918c/Kconfig rename to drivers/sensor/asahi_kasei/akm09918c/Kconfig diff --git a/drivers/sensor/akm09918c/akm09918c.c b/drivers/sensor/asahi_kasei/akm09918c/akm09918c.c similarity index 100% rename from drivers/sensor/akm09918c/akm09918c.c rename to drivers/sensor/asahi_kasei/akm09918c/akm09918c.c diff --git a/drivers/sensor/akm09918c/akm09918c.h b/drivers/sensor/asahi_kasei/akm09918c/akm09918c.h similarity index 100% rename from drivers/sensor/akm09918c/akm09918c.h rename to drivers/sensor/asahi_kasei/akm09918c/akm09918c.h diff --git a/drivers/sensor/akm09918c/akm09918c_async.c b/drivers/sensor/asahi_kasei/akm09918c/akm09918c_async.c similarity index 100% rename from drivers/sensor/akm09918c/akm09918c_async.c rename to drivers/sensor/asahi_kasei/akm09918c/akm09918c_async.c diff --git a/drivers/sensor/akm09918c/akm09918c_decoder.c b/drivers/sensor/asahi_kasei/akm09918c/akm09918c_decoder.c similarity index 100% rename from drivers/sensor/akm09918c/akm09918c_decoder.c rename to drivers/sensor/asahi_kasei/akm09918c/akm09918c_decoder.c diff --git a/drivers/sensor/akm09918c/akm09918c_emul.c b/drivers/sensor/asahi_kasei/akm09918c/akm09918c_emul.c similarity index 100% rename from drivers/sensor/akm09918c/akm09918c_emul.c rename to drivers/sensor/asahi_kasei/akm09918c/akm09918c_emul.c diff --git a/drivers/sensor/akm09918c/akm09918c_emul.h b/drivers/sensor/asahi_kasei/akm09918c/akm09918c_emul.h similarity index 100% rename from drivers/sensor/akm09918c/akm09918c_emul.h rename to drivers/sensor/asahi_kasei/akm09918c/akm09918c_emul.h diff --git a/drivers/sensor/akm09918c/akm09918c_reg.h b/drivers/sensor/asahi_kasei/akm09918c/akm09918c_reg.h similarity index 100% rename from drivers/sensor/akm09918c/akm09918c_reg.h rename to drivers/sensor/asahi_kasei/akm09918c/akm09918c_reg.h From d2dfb8e8d7e69de774649fc012ad2adbcb6851c7 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Thu, 4 Apr 2024 19:03:07 -0500 Subject: [PATCH 1986/2402] drivers: sensor: meas: Move to vendor subdirectory Organizes sensor drivers by vendor to distribute maintainership responsibilities. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 3 +-- drivers/sensor/Kconfig | 3 +-- drivers/sensor/meas/CMakeLists.txt | 7 +++++++ drivers/sensor/meas/Kconfig | 7 +++++++ drivers/sensor/{ => meas}/ms5607/CMakeLists.txt | 0 drivers/sensor/{ => meas}/ms5607/Kconfig | 0 drivers/sensor/{ => meas}/ms5607/ms5607.c | 0 drivers/sensor/{ => meas}/ms5607/ms5607.h | 0 drivers/sensor/{ => meas}/ms5607/ms5607_i2c.c | 0 drivers/sensor/{ => meas}/ms5607/ms5607_spi.c | 0 drivers/sensor/{ => meas}/ms5837/CMakeLists.txt | 0 drivers/sensor/{ => meas}/ms5837/Kconfig | 0 drivers/sensor/{ => meas}/ms5837/ms5837.c | 0 drivers/sensor/{ => meas}/ms5837/ms5837.h | 0 14 files changed, 16 insertions(+), 4 deletions(-) create mode 100644 drivers/sensor/meas/CMakeLists.txt create mode 100644 drivers/sensor/meas/Kconfig rename drivers/sensor/{ => meas}/ms5607/CMakeLists.txt (100%) rename drivers/sensor/{ => meas}/ms5607/Kconfig (100%) rename drivers/sensor/{ => meas}/ms5607/ms5607.c (100%) rename drivers/sensor/{ => meas}/ms5607/ms5607.h (100%) rename drivers/sensor/{ => meas}/ms5607/ms5607_i2c.c (100%) rename drivers/sensor/{ => meas}/ms5607/ms5607_spi.c (100%) rename drivers/sensor/{ => meas}/ms5837/CMakeLists.txt (100%) rename drivers/sensor/{ => meas}/ms5837/Kconfig (100%) rename drivers/sensor/{ => meas}/ms5837/ms5837.c (100%) rename drivers/sensor/{ => meas}/ms5837/ms5837.h (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 4833fb6db64..78051027fce 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -11,6 +11,7 @@ add_subdirectory(honeywell) add_subdirectory(infineon) add_subdirectory(ite) add_subdirectory(maxim) +add_subdirectory(meas) add_subdirectory(microchip) add_subdirectory(nordic) add_subdirectory(nuvoton) @@ -51,8 +52,6 @@ add_subdirectory_ifdef(CONFIG_MC3419 mc3419) add_subdirectory_ifdef(CONFIG_MHZ19B mhz19b) add_subdirectory_ifdef(CONFIG_MPU6050 tdk/mpu6050) add_subdirectory_ifdef(CONFIG_MPU9250 tdk/mpu9250) -add_subdirectory_ifdef(CONFIG_MS5607 ms5607) -add_subdirectory_ifdef(CONFIG_MS5837 ms5837) add_subdirectory_ifdef(CONFIG_NTC_THERMISTOR ntc_thermistor) add_subdirectory_ifdef(CONFIG_PMS7003 pms7003) add_subdirectory_ifdef(CONFIG_QDEC_SAM qdec_sam) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index fd4aad01adb..89552e3b746 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -92,6 +92,7 @@ source "drivers/sensor/honeywell/Kconfig" source "drivers/sensor/infineon/Kconfig" source "drivers/sensor/ite/Kconfig" source "drivers/sensor/maxim/Kconfig" +source "drivers/sensor/meas/Kconfig" source "drivers/sensor/microchip/Kconfig" source "drivers/sensor/nordic/Kconfig" source "drivers/sensor/nuvoton/Kconfig" @@ -132,8 +133,6 @@ source "drivers/sensor/mc3419/Kconfig" source "drivers/sensor/mhz19b/Kconfig" source "drivers/sensor/tdk/mpu6050/Kconfig" source "drivers/sensor/tdk/mpu9250/Kconfig" -source "drivers/sensor/ms5607/Kconfig" -source "drivers/sensor/ms5837/Kconfig" source "drivers/sensor/ntc_thermistor/Kconfig" source "drivers/sensor/pms7003/Kconfig" source "drivers/sensor/qdec_sam/Kconfig" diff --git a/drivers/sensor/meas/CMakeLists.txt b/drivers/sensor/meas/CMakeLists.txt new file mode 100644 index 00000000000..a899a916590 --- /dev/null +++ b/drivers/sensor/meas/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_MS5607 ms5607) +add_subdirectory_ifdef(CONFIG_MS5837 ms5837) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/meas/Kconfig b/drivers/sensor/meas/Kconfig new file mode 100644 index 00000000000..aa3f54ca423 --- /dev/null +++ b/drivers/sensor/meas/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/meas/ms5607/Kconfig" +source "drivers/sensor/meas/ms5837/Kconfig" +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/ms5607/CMakeLists.txt b/drivers/sensor/meas/ms5607/CMakeLists.txt similarity index 100% rename from drivers/sensor/ms5607/CMakeLists.txt rename to drivers/sensor/meas/ms5607/CMakeLists.txt diff --git a/drivers/sensor/ms5607/Kconfig b/drivers/sensor/meas/ms5607/Kconfig similarity index 100% rename from drivers/sensor/ms5607/Kconfig rename to drivers/sensor/meas/ms5607/Kconfig diff --git a/drivers/sensor/ms5607/ms5607.c b/drivers/sensor/meas/ms5607/ms5607.c similarity index 100% rename from drivers/sensor/ms5607/ms5607.c rename to drivers/sensor/meas/ms5607/ms5607.c diff --git a/drivers/sensor/ms5607/ms5607.h b/drivers/sensor/meas/ms5607/ms5607.h similarity index 100% rename from drivers/sensor/ms5607/ms5607.h rename to drivers/sensor/meas/ms5607/ms5607.h diff --git a/drivers/sensor/ms5607/ms5607_i2c.c b/drivers/sensor/meas/ms5607/ms5607_i2c.c similarity index 100% rename from drivers/sensor/ms5607/ms5607_i2c.c rename to drivers/sensor/meas/ms5607/ms5607_i2c.c diff --git a/drivers/sensor/ms5607/ms5607_spi.c b/drivers/sensor/meas/ms5607/ms5607_spi.c similarity index 100% rename from drivers/sensor/ms5607/ms5607_spi.c rename to drivers/sensor/meas/ms5607/ms5607_spi.c diff --git a/drivers/sensor/ms5837/CMakeLists.txt b/drivers/sensor/meas/ms5837/CMakeLists.txt similarity index 100% rename from drivers/sensor/ms5837/CMakeLists.txt rename to drivers/sensor/meas/ms5837/CMakeLists.txt diff --git a/drivers/sensor/ms5837/Kconfig b/drivers/sensor/meas/ms5837/Kconfig similarity index 100% rename from drivers/sensor/ms5837/Kconfig rename to drivers/sensor/meas/ms5837/Kconfig diff --git a/drivers/sensor/ms5837/ms5837.c b/drivers/sensor/meas/ms5837/ms5837.c similarity index 100% rename from drivers/sensor/ms5837/ms5837.c rename to drivers/sensor/meas/ms5837/ms5837.c diff --git a/drivers/sensor/ms5837/ms5837.h b/drivers/sensor/meas/ms5837/ms5837.h similarity index 100% rename from drivers/sensor/ms5837/ms5837.h rename to drivers/sensor/meas/ms5837/ms5837.h From 9b66515ce0065467f8a65705c97775f66a9dc033 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 29 Mar 2024 11:41:03 +0100 Subject: [PATCH 1987/2402] docs: Bluetooth: Add additional notes to BAP related services Some of the services have some unique points worth knowing as both a contributor and an application developer. Signed-off-by: Emil Gydesen --- .../bluetooth/bluetooth-le-audio-arch.rst | 66 ++++++++++++++++++- 1 file changed, 64 insertions(+), 2 deletions(-) diff --git a/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst b/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst index d2a0b6cd4c0..40282361c7f 100644 --- a/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst +++ b/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst @@ -264,12 +264,74 @@ defines multiple roles: * Unicast Server * Broadcast Source * Broadcast Sink -* Scan Delegator (not yet implemented) -* Broadcast assistant (not yet implemented) +* Scan Delegator +* Broadcast Assistant Each role can be enabled individually, and it is possible to support more than one role. +Notes about the stream control services +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +There are 3 services primarily used by stream control using the Basic Audio Profile. + +Audio Stream Control Service (ASCS) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +ASCS is a service used exclusively for setting up unicast streams, +and is located on the BAP Unicast Server device. +The service exposes one or more endpoints that can either be a sink or source endpoint, +from the perspective of the Unicast Server. +That means a sink endpoint is always audio from the Unicast Client to the Unicast Server, +and a source endpoint is always from the Unicast Server to the Unicast Client. + +Unlike most other GATT services, +ASCS require that each characteristic in the service has unique data per client. +This means that if a Unicast Server is connected to multiple Unicast Clients, +the Unicast Clients are not able to see or control the endpoints configured by the other clients. +For example if a person's smartphone is streaming audio to a headset, +then the same person will not be able to see or control that stream from their smartwatch. + +Broadcast Audio Scan Service (BASS) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +BASS is a service that is exclusively used by the Scan Delegator and Broadcast Assistant. +The main purpose of the service is to offload scanning from low power peripherals to e.g. phones +and PCs. +Unlike ASCS where the data is required to be unique per client, +the data in BASS (called receive states) are (usually) shared among all connected clients. +That means it is possible for a person to tell their headphones to synchronize to a +Broadcast Source using their phone, +and then later tell their headphones to stop synchronizing using their smartwatch. + +A Broadcast Assistant can be any device, +and may only support this one role without any audio capabilities. +This allows legacy devices that do not support periodic advertisements or isochronous channels to +still provide an interface and scan offloading for peripherals. +The Bluetooth SIG have provided a guide on how to develop such legacy Broadcast Assistants that can +be found at +https://www.bluetooth.com/bluetooth-resources/developing-auracast-receivers-with-an-assistant-application-for-legacy-smartphones/. +An important note about this guide is that many operating systems (especially on phones), +do not allow generic usage of the BASS UUID, +effectively making it impossible to implement your own Broadcast Assistant, +because you cannot access the BASS. + +Published Audio Capabilities Service (PACS) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +PACS is used to expose a device's audio capabilities in Published Audio Capabilities (PAC) records. +PACS is used by nearly all roles, +where the Unicast Client and Broadcast Assistant will act as PACS clients, +and Unicast Server and Broadcast Sink will act as PACS servers. +These records contain information about the codec, and which values are supported by each codec. +The values for the LC3 codec are defined by the Bluetooth Assigned numbers +(https://www.bluetooth.com/specifications/assigned-numbers/), and the values for other codecs such +as SBC are left undefined/implementation specific for BAP. + +PACS also usually share the same data between each connected client, +but by using functions such as :c:func:`bt_pacs_conn_set_available_contexts_for_conn`, +it is possible to set specific values for specific clients. + The API reference for stream control can be found in :ref:`Bluetooth Audio `. From 0287d5387df21acc49065a9c37b251db09f9fbbf Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Fri, 29 Mar 2024 14:36:01 +0100 Subject: [PATCH 1988/2402] docs: Bluetooth: Audio: Add LE audio resources This commit adds a small overview over resources related to LE Audio, both Zephyr specific and general information from the Bluetooth SIG. Signed-off-by: Emil Gydesen --- .../bluetooth/bluetooth-le-audio-arch.rst | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst b/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst index 40282361c7f..a9a43c3891a 100644 --- a/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst +++ b/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst @@ -493,3 +493,86 @@ The CSIP implementation supports the following roles The API reference for media control can be found in :ref:`Bluetooth Coordinated Sets `. + + +LE Audio resources +################## + +This section contains some links and reference to resources that are useful for either contributors +to the LE Audio Stack in Zephyr, LE Audio application developers or both. + +The LE audio channel on Discord +******************************* + +Zephyr has a specific Discord channel for LE Audio development, which is open to all. +Find it here at https://discordapp.com/channels/720317445772017664/1207326649591271434 or simply +search for `ble-audio` from within Discord. +Since the `ble-audio` channel is open for all, +we cannot discuss any specifications that are in development in that channel. +For discussions that require a Bluetooth SIG membership we refer to the `bluetooth-sig` +Discord channel found at https://discordapp.com/channels/720317445772017664/869172014018097162. + +Zephyr weekly meetings +********************** + +Anyone who is a Bluetooth SIG member and a Zephyr member can join the weekly meetings where we +discuss and plan the development of LE Audio in Zephyr. You can find the time of the meetings by +joining the Bluetooth-sig group at https://lists.zephyrproject.org/g/Bluetooth-sig. + +Github project +************** + +LE Audio in Zephyr has its own Github project available at +https://github.com/orgs/zephyrproject-rtos/projects/26. +The project is mostly automated, +and the LE Audio contributors almost only rely on the automated workflows +to present the state of development. +Anyone is able to pick any of the open issues and work on it. +If you cannot assign the issue to youself, +please leave a comment in the issue itself or ping the Discord channel for help. + +Bluetooth SIG errata for LE Audio +********************************* + +There are many specifications for LE Audio, +and several of them are still being updated and developed. +To get an overview of the errata for the LE Audio specifications you can visit + +* Generic Audio (GA) errata https://bluetooth.atlassian.net/wiki/spaces/GA/pages/1634402349/GAWG+Errata+Lists +* Hearing Aid (HA) errata https://bluetooth.atlassian.net/wiki/spaces/HA/pages/1634140216/HA+WG+Errata+List +* Audio, Telephony and Automotive (ATA) errata https://bluetooth.atlassian.net/wiki/spaces/ATA/pages/1668481034/ATA+Errata+Lists + +Access to errata requires a Bluetooth SIG membership. + +Bluetooth SIG working groups for LE Audio +***************************************** + +There are 3 working groups in the Bluetooth SIG related to LE Audio: + +* Generic Audio (GA) https://www.bluetooth.org/groups/group.aspx?gId=665 +* Hearing Aid (HA) https://www.bluetooth.org/groups/group.aspx?gId=605 +* Audio, Telephony, and Automotive (ATA) https://www.bluetooth.org/groups/group.aspx?gId=659 + +By joining these groups you will also get emails from their respective mailing lists, +where multiple questions and discussions are handled. +The working groups also have scheduled weekly meetings, +where issues and the development of the specifications are handled. + +Access to the Bluetooth SIG working groups requires a Bluetooth SIG membership. + +The LE Audio Book +***************** + +There is a free ebook on LE Audio at https://www.bluetooth.com/bluetooth-resources/le-audio-book/. +The book was released in January 2022, +and thus before some of the specifications were finalized, +but also before some of the released updates to the specifications. +Nevertheless the book still provides a good explanation for many of the concepts and ideas, +but please refer to the individual specifications for technical information. + +Bluetooth SIG informational papers, reports and guides +****************************************************** + +The Bluetooth SIG occasionally release new informational papers, report and guides. +These can be found at https://www.bluetooth.com/bluetooth-resources/?tags=le-audio&keyword. +Here you will also find the aforementioned LE Audio book, among many other good resources. From 6de30457b80618d6dd9a63e2c21d82f9fb89542d Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Thu, 4 Apr 2024 12:19:34 +0200 Subject: [PATCH 1989/2402] doc: Bluetooth: setup redirects Setup redirects for pages renamed in #70679 . Signed-off-by: Jonathan Rico --- doc/_scripts/redirects.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/doc/_scripts/redirects.py b/doc/_scripts/redirects.py index 8cb81cdae05..49aec7ad039 100644 --- a/doc/_scripts/redirects.py +++ b/doc/_scripts/redirects.py @@ -17,6 +17,15 @@ ('application/index', 'develop/application/index'), ('boards/x86/ehl_crb/doc/index', 'boards/x86/intel_ehl/doc/index'), ('boards/x86/rpl_crb/doc/index', 'boards/x86/intel_rpl/doc/index'), + ('connectivity/bluetooth/bluetooth-audio-arch', 'connectivity/bluetooth/bluetooth-le-audio-arch'), + ('connectivity/bluetooth/dis-pics', 'connectivity/bluetooth/ics/dis'), + ('connectivity/bluetooth/gap-pics', 'connectivity/bluetooth/ics/gap'), + ('connectivity/bluetooth/gatt-pics', 'connectivity/bluetooth/ics/gatt'), + ('connectivity/bluetooth/l2cap-pics', 'connectivity/bluetooth/ics/l2cap'), + ('connectivity/bluetooth/mesh-pics', 'connectivity/bluetooth/ics/mesh'), + ('connectivity/bluetooth/overview', 'connectivity/bluetooth/features'), + ('connectivity/bluetooth/rfcomm-pics', 'connectivity/bluetooth/ics/rfcomm'), + ('connectivity/bluetooth/sm-pics', 'connectivity/bluetooth/ics/sm'), ('connectivity/networking/networking-api-usage', 'connectivity/networking/api/index'), ('development_process/code_flow', 'project/code_flow'), ('development_process/index', 'project/index'), From e69d5d83d3aec5e7fce88a1dd1181086405b392f Mon Sep 17 00:00:00 2001 From: Arunmani Alagarsamy Date: Tue, 2 Apr 2024 19:42:35 +0530 Subject: [PATCH 1990/2402] boards: st: b_u585i_iot02a: Add eeprom child node in i2c2 Added eeprom devicetree support for b_u585i_iot02a board. Signed-off-by: Arunmani Alagarsamy --- boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi index 57fe9bded74..7912aa33deb 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi @@ -38,6 +38,7 @@ die-temp0 = &die_temp; volt-sensor0 = &vref1; volt-sensor1 = &vbat4; + eeprom-0 = &eeprom0; }; }; @@ -189,6 +190,16 @@ stm32_lp_tick_source: &lptim1 { drdy-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; }; + eeprom0:eeprom@56 { + compatible = "atmel,at24"; + reg = <0x56>; + status = "okay"; + size = ; + pagesize = <64>; + address-width = <16>; + timeout = <5>; + }; + hts221@5f { compatible = "st,hts221"; reg = <0x5f>; From f0779d39d7cb1d71b3abeb9db5505c05274ce452 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Wed, 14 Feb 2024 11:24:03 +0100 Subject: [PATCH 1991/2402] manifest: update espressif hal Update hal_espressif to support the simple boot. Signed-off-by: Marek Matej --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 892de42faab..012582eec23 100644 --- a/west.yml +++ b/west.yml @@ -152,7 +152,7 @@ manifest: groups: - hal - name: hal_espressif - revision: 742df6bfc595591603361eb703ac9462ed6384c6 + revision: dddb7cf318d931c25623c34ecde20f3150d7f987 path: modules/hal/espressif west-commands: west/west-commands.yml groups: From a54f3832f5fc8fae55198045949e1991b3261450 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Wed, 31 Jan 2024 20:18:02 +0100 Subject: [PATCH 1992/2402] kconfig.zephyr: Remove ESP_IDF bootloader option Remove ESP_IDF bootloader option. Default boot method is simple boot. Signed-off-by: Marek Matej --- Kconfig.zephyr | 9 --------- 1 file changed, 9 deletions(-) diff --git a/Kconfig.zephyr b/Kconfig.zephyr index b315a0e7aad..5375245ced0 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -905,15 +905,6 @@ config BOOTLOADER_SRAM_SIZE_DEPRECATED Non-prompt symbol to indicate that the deprecated BOOTLOADER_SRAM_SIZE Kconfig has a non-0 value. Please transition to using devicetree. -config BOOTLOADER_ESP_IDF - bool "ESP-IDF bootloader support" - depends on SOC_FAMILY_ESPRESSIF_ESP32 && !BOOTLOADER_MCUBOOT && !MCUBOOT - default y - help - This option will trigger the compilation of the ESP-IDF bootloader - inside the build folder. - At flash time, the bootloader will be flashed with the zephyr image - config BOOTLOADER_BOSSA bool "BOSSA bootloader support" select USE_DT_CODE_PARTITION From 72363217434a623a070a0b1e725ead91268f77ac Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Thu, 25 Jan 2024 16:58:53 +0100 Subject: [PATCH 1993/2402] drivers: clock_control: esp32: Multiple fixes - update the console configuration defines references - add missing header file with flash capabilities - replace all console wait-until-ready calls by single one Signed-off-by: Marek Matej --- drivers/clock_control/clock_control_esp32.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c index f38d780a42b..7aec123785d 100644 --- a/drivers/clock_control/clock_control_esp32.c +++ b/drivers/clock_control/clock_control_esp32.c @@ -35,6 +35,7 @@ #include #endif /* CONFIG_SOC_SERIES_ESP32xx */ +#include #include #include #include @@ -518,6 +519,9 @@ static int clock_control_esp32_init(const struct device *dev) rtc_cpu_freq_config_t new_config; bool res; + /* wait uart output to be cleared */ + esp_rom_uart_tx_wait_idle(ESP_CONSOLE_UART_NUM); + /* reset default config to use dts config */ if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) { rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT(); @@ -541,9 +545,6 @@ static int clock_control_esp32_init(const struct device *dev) return -ENOTSUP; } - /* wait uart output to be cleared */ - esp_rom_uart_tx_wait_idle(0); - if (cfg->xtal_div >= 0) { new_config.div = cfg->xtal_div; } @@ -564,10 +565,10 @@ static int clock_control_esp32_init(const struct device *dev) #if ESP_ROM_UART_CLK_IS_XTAL clock_hz = esp_clk_xtal_freq(); #endif - esp_rom_uart_tx_wait_idle(ESP_CONSOLE_UART_NUM); #if !defined(ESP_CONSOLE_UART_NONE) - esp_rom_uart_set_clock_baudrate(ESP_CONSOLE_UART_NUM, clock_hz, ESP_CONSOLE_UART_BAUDRATE); + esp_rom_uart_set_clock_baudrate(ESP_CONSOLE_UART_NUM, + clock_hz, ESP_CONSOLE_UART_BAUDRATE); #endif return 0; } From 43e3088c2d7df553cb9bccdeb6a341d59cf54400 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Wed, 14 Feb 2024 18:45:17 +0100 Subject: [PATCH 1994/2402] soc: espressif: Simple boot support Add simplistic booting method which allows to load without 2nd stage bootloader. Update common architecture loader to support all build scenarios. - simple boot: using single binary application without bootloader - mcuboot: zephyr port of MCUboot - application: loaded by the MCUboot Signed-off-by: Marek Matej --- soc/espressif/common/Kconfig.flash | 8 ++ soc/espressif/common/loader.c | 180 +++++++++++++++++++++++------ 2 files changed, 153 insertions(+), 35 deletions(-) diff --git a/soc/espressif/common/Kconfig.flash b/soc/espressif/common/Kconfig.flash index 3dd465c6868..2ed5d3f1b65 100644 --- a/soc/espressif/common/Kconfig.flash +++ b/soc/espressif/common/Kconfig.flash @@ -127,4 +127,12 @@ config SPI_FLASH_HPM_ENABLE This option is invisible, and will be selected automatically when ``ESPTOOLPY_FLASHFREQ_120M`` is selected. +config ESP_SIMPLE_BOOT + bool "Simple Boot method" + default y if !BOOTLOADER_MCUBOOT + help + The Simple Boot is a method of booting that doesn't depend on a + 2nd stage bootloader. Please note that some of the bootloader features + are not available using simple boot, such secure boot and OTA. + endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/common/loader.c b/soc/espressif/common/loader.c index 6d1b7ecba0e..e563f6757ec 100644 --- a/soc/espressif/common/loader.c +++ b/soc/espressif/common/loader.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,29 +12,64 @@ #include #include #include +#include #define MMU_FLASH_MASK (~(CONFIG_MMU_PAGE_SIZE - 1)) -#ifdef CONFIG_BOOTLOADER_MCUBOOT +#include #include #include "esp_rom_uart.h" +#include "esp_flash.h" +#include "esp_log.h" +#include "bootloader_init.h" + +#define TAG "boot" + +#define CHECKSUM_ALIGN 16 +#define IS_PADD(addr) (addr == 0) +#define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH) +#define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH) +#define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH) +#define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH) +#define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr)) +#define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr)) +#define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \ + && !IS_IRAM(addr) && !IS_DRAM(addr) && !IS_PADD(addr)) #define BOOT_LOG_INF(_fmt, ...) \ ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) +#define BOOT_LOG_ERR(_fmt, ...) \ + ets_printf("[" CONFIG_SOC_SERIES "] [ERR] " _fmt "\n\r", ##__VA_ARGS__) #define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) void __start(void); - static HDR_ATTR void (*_entry_point)(void) = &__start; +extern esp_image_header_t bootloader_image_hdr; extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; + +static uint32_t _app_irom_start = (FIXED_PARTITION_OFFSET(slot0_partition) + + (uint32_t)&_image_irom_start); +static uint32_t _app_irom_size = (uint32_t)&_image_irom_size; +static uint32_t _app_irom_vaddr = ((uint32_t)&_image_irom_vaddr); + +static uint32_t _app_drom_start = (FIXED_PARTITION_OFFSET(slot0_partition) + + (uint32_t)&_image_drom_start); +static uint32_t _app_drom_size = (uint32_t)&_image_drom_size; +static uint32_t _app_drom_vaddr = ((uint32_t)&_image_drom_vaddr); + +#ifndef CONFIG_BOOTLOADER_MCUBOOT +static esp_err_t spi_flash_read(uint32_t address, void *buffer, size_t length) +{ + return esp_flash_read(NULL, buffer, address, length); +} #endif /* CONFIG_BOOTLOADER_MCUBOOT */ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, - uint32_t app_drom_size, uint32_t app_irom_start, - uint32_t app_irom_vaddr, uint32_t app_irom_size) + uint32_t app_drom_size, uint32_t app_irom_start, + uint32_t app_irom_vaddr, uint32_t app_irom_size) { uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK; @@ -43,12 +78,74 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK; uint32_t actual_mapped_len = 0; +#ifndef CONFIG_BOOTLOADER_MCUBOOT + esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr; + size_t offset = FIXED_PARTITION_OFFSET(boot_partition); + bool checksum = false; + unsigned int segments = 0; + unsigned int ram_segments = 0; + + /* Using already fetched bootloader image header from bootloader_init */ + offset += sizeof(esp_image_header_t); + + while (segments++ < 16) { + + if (spi_flash_read(offset, &segment_hdr, + sizeof(esp_image_segment_header_t)) != ESP_OK) { + BOOT_LOG_ERR("Failed to read segment header at %x", offset); + abort(); + } + + /* TODO: Find better end-of-segment detection */ + if (IS_NONE(segment_hdr.load_addr)) { + /* Total segment count = (segments - 1) */ + break; + } + + BOOT_LOG_INF("%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)", + IS_NONE(segment_hdr.load_addr) ? "???" : + IS_MMAP(segment_hdr.load_addr) ? + IS_IROM(segment_hdr.load_addr) ? "IMAP" : "DMAP" : + IS_PADD(segment_hdr.load_addr) ? "padd" : + IS_DRAM(segment_hdr.load_addr) ? "DRAM" : "IRAM", + offset + sizeof(esp_image_segment_header_t), + segment_hdr.load_addr, segment_hdr.data_len, segment_hdr.data_len); + + /* Fix drom and irom produced be the linker, as it could + * be invalidated by the elf2image and flash load offset + */ + if (segment_hdr.load_addr == _app_drom_vaddr) { + app_drom_start = offset + sizeof(esp_image_segment_header_t); + app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + } + if (segment_hdr.load_addr == _app_irom_vaddr) { + app_irom_start = offset + sizeof(esp_image_segment_header_t); + app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + } + if (IS_SRAM(segment_hdr.load_addr)) { + ram_segments++; + } + offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len; + + if (ram_segments == bootloader_image_hdr.segment_count && !checksum) { + offset += (CHECKSUM_ALIGN - 1) - (offset % CHECKSUM_ALIGN) + 1; + checksum = true; + } + } + if (segments == 0 || segments == 16) { + BOOT_LOG_ERR("Error parsing segments"); + abort(); + } + + BOOT_LOG_INF("Image with %d segments", segments - 1); +#endif /* !CONFIG_BOOTLOADER_MCUBOOT */ + #if CONFIG_SOC_SERIES_ESP32 Cache_Read_Disable(0); Cache_Flush(0); #else cache_hal_disable(CACHE_TYPE_ALL); -#endif +#endif /* CONFIG_SOC_SERIES_ESP32 */ /* Clear the MMU entries that are already set up, * so the new app only has the mappings it creates. @@ -58,31 +155,33 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, #if CONFIG_SOC_SERIES_ESP32 int rc = 0; uint32_t drom_page_count = - (app_drom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; + (app_drom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; rc |= cache_flash_mmu_set(0, 0, app_drom_vaddr_aligned, - app_drom_start_aligned, 64, drom_page_count); + app_drom_start_aligned, 64, drom_page_count); rc |= cache_flash_mmu_set(1, 0, app_drom_vaddr_aligned, - app_drom_start_aligned, 64, drom_page_count); + app_drom_start_aligned, 64, drom_page_count); uint32_t irom_page_count = - (app_irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; + (app_irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; rc |= cache_flash_mmu_set(0, 0, app_irom_vaddr_aligned, - app_irom_start_aligned, 64, irom_page_count); + app_irom_start_aligned, 64, irom_page_count); rc |= cache_flash_mmu_set(1, 0, app_irom_vaddr_aligned, - app_irom_start_aligned, 64, irom_page_count); + app_irom_start_aligned, 64, irom_page_count); if (rc != 0) { - esp_rom_printf("Failed to setup XIP, aborting\n"); + BOOT_LOG_ERR("Failed to setup XIP, aborting"); abort(); } #else - mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_drom_vaddr_aligned, app_drom_start_aligned, + mmu_hal_map_region(0, MMU_TARGET_FLASH0, + app_drom_vaddr_aligned, app_drom_start_aligned, app_drom_size, &actual_mapped_len); - mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_irom_vaddr_aligned, app_irom_start_aligned, + mmu_hal_map_region(0, MMU_TARGET_FLASH0, + app_irom_vaddr_aligned, app_irom_start_aligned, app_irom_size, &actual_mapped_len); -#endif +#endif /* CONFIG_SOC_SERIES_ESP32 */ /* ----------------------Enable corresponding buses---------------- */ cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned, app_drom_size); @@ -103,31 +202,42 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, Cache_Read_Enable(0); #else cache_hal_enable(CACHE_TYPE_ALL); -#endif +#endif /* CONFIG_SOC_SERIES_ESP32 */ + + /* Show map segments continue using same log format as during MCUboot phase */ + BOOT_LOG_INF("DROM segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map", + app_drom_start_aligned, app_drom_vaddr_aligned, + app_drom_size, app_drom_size); + BOOT_LOG_INF("IROM segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map\r\n", + app_irom_start_aligned, app_irom_vaddr_aligned, + app_irom_size, app_irom_size); + esp_rom_uart_tx_wait_idle(0); } void __start(void) { -#ifdef CONFIG_BOOTLOADER_MCUBOOT - size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition); - uint32_t _app_irom_start = (_partition_offset + (uint32_t)&_image_irom_start); - uint32_t _app_irom_size = (uint32_t)&_image_irom_size; - uint32_t _app_irom_vaddr = ((uint32_t)&_image_irom_vaddr); - - uint32_t _app_drom_start = (_partition_offset + (uint32_t)&_image_drom_start); - uint32_t _app_drom_size = (uint32_t)&_image_drom_size; - uint32_t _app_drom_vaddr = ((uint32_t)&_image_drom_vaddr); - uint32_t actual_mapped_len = 0; +#ifdef CONFIG_RISCV_GP + /* Configure the global pointer register + * (This should be the first thing startup does, as any other piece of code could be + * relaxed by the linker to access something relative to __global_pointer$) + */ + __asm__ __volatile__(".option push\n" + ".option norelax\n" + "la gp, __global_pointer$\n" + ".option pop"); +#endif /* CONFIG_RISCV_GP */ + +#ifndef CONFIG_BOOTLOADER_MCUBOOT + /* Init fundamental components */ + if (bootloader_init()) { + BOOT_LOG_ERR("HW init failed, aborting"); + abort(); + } +#endif +#ifndef CONFIG_MCUBOOT map_rom_segments(_app_drom_start, _app_drom_vaddr, _app_drom_size, - _app_irom_start, _app_irom_vaddr, _app_irom_size); - - /* Show map segments continue using same log format as during MCUboot phase */ - BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map", - _app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size); - BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n", - _app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size); - esp_rom_uart_tx_wait_idle(0); + _app_irom_start, _app_irom_vaddr, _app_irom_size); #endif __esp_platform_start(); } From f9008b5330c064d55d2f202d52a7ed986bafcac1 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Wed, 14 Feb 2024 11:43:29 +0100 Subject: [PATCH 1995/2402] soc: espressif: esp32c3: simple boot support Add simplistic booting method which allows to run applications without the 2nd stage bootloader. - introduce memory layout header file - update and optimize default and mcuboot linker scripts - remove building multiple binaries during the application build Signed-off-by: Marek Matej --- soc/espressif/esp32c3/CMakeLists.txt | 75 +-- soc/espressif/esp32c3/default.ld | 819 ++++++++++++++++++--------- soc/espressif/esp32c3/mcuboot.ld | 339 +++++------ soc/espressif/esp32c3/memory.h | 67 +++ soc/espressif/esp32c3/soc.c | 34 +- 5 files changed, 811 insertions(+), 523 deletions(-) create mode 100644 soc/espressif/esp32c3/memory.h diff --git a/soc/espressif/esp32c3/CMakeLists.txt b/soc/espressif/esp32c3/CMakeLists.txt index a5c44685ef1..75ee06e2a06 100644 --- a/soc/espressif/esp32c3/CMakeLists.txt +++ b/soc/espressif/esp32c3/CMakeLists.txt @@ -13,58 +13,59 @@ zephyr_include_directories(.) zephyr_library_sources_ifdef(CONFIG_PM power.c) zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) -# get code-partition slot0 address -dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") -dt_reg_addr(img_0_off PATH ${dts_partition_path}) - -# get code-partition boot address -dt_nodelabel(dts_partition_path NODELABEL "boot_partition") -dt_reg_addr(boot_off PATH ${dts_partition_path}) - # get flash size to use in esptool as string math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") -if(CONFIG_BOOTLOADER_ESP_IDF) - - set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") +if(NOT CONFIG_BOOTLOADER_MCUBOOT) - if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") - endif() - - if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") - endif() - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + if(CONFIG_BUILD_OUTPUT_BIN) + # make ESP ROM loader compatible image + message("ESP-IDF path: ${ESP_IDF_PATH}") -endif() + set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py) + message("esptool path: ${ESPTOOL_PY}") -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + set(ELF2IMAGE_ARG "") + if(NOT CONFIG_MCUBOOT) + set(ELF2IMAGE_ARG "--ram-only-header") + endif() - if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py - ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY} + ARGS --chip esp32c3 elf2image ${ELF2IMAGE_ARG} + --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) endif() - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - endif() -board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") +# get code-partition slot0 address +dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") +dt_reg_addr(img_0_off PATH ${dts_partition_path}) + +# get code-partition boot address +dt_nodelabel(dts_partition_path NODELABEL "boot_partition") +dt_reg_addr(boot_off PATH ${dts_partition_path}) + +if(CONFIG_ESP_SIMPLE_BOOT) + board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}") +else() + board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") +endif() -board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") +if(CONFIG_MCUBOOT) + # search from cross references between bootloader sections + message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py") + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py + ARGS + --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr + --elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf + find-refs --from-section=.iram0.iram_loader --to-section=.iram0.text + --exit-code) +endif() if(CONFIG_MCUBOOT) set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") diff --git a/soc/espressif/esp32c3/default.ld b/soc/espressif/esp32c3/default.ld index 39e6906c62f..120f66d852d 100644 --- a/soc/espressif/esp32c3/default.ld +++ b/soc/espressif/esp32c3/default.ld @@ -1,55 +1,42 @@ /* - * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the esp32c3 platform. - */ - #include #include #include #include -#define RAMABLE_REGION dram0_0_seg -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define FLASH_CODE_REGION irom0_0_seg - -#define ROMABLE_REGION ROM - -#define SRAM_IRAM_START 0x4037C000 -#define SRAM_DRAM_START 0x3FC7C000 -#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */ -#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) -/* SRAM_DRAM_END is equivalent 2nd stage bootloader iram_loader_seg - start address (that should not be overlapped) */ -#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET -#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) -#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE) -#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG - -#ifdef CONFIG_FLASH_SIZE -#define FLASH_SIZE CONFIG_FLASH_SIZE -#else -#define FLASH_SIZE 0x400000 -#endif +#include "memory.h" -#ifdef CONFIG_BOOTLOADER_ESP_IDF -#define IROM_SEG_ORG 0x42000020 -#define IROM_SEG_LEN (FLASH_SIZE-0x20) -#define IROM_SEG_ALIGN 0x4 +/* The "user_iram_end" represents the 2nd stage bootloader + * "iram_loader_seg" start address (that should not be overlapped). + * If no bootloader is used, we can extend it to gain more user ram. + */ +#ifdef CONFIG_ESP_SIMPLE_BOOT +user_iram_end = (DRAM_BUFFERS_START + IRAM_DRAM_OFFSET); #else -#define IROM_SEG_ORG 0x42000000 -#define IROM_SEG_LEN FLASH_SIZE -#define IROM_SEG_ALIGN 0x10000 +user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START; #endif -/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. +/* User available SRAM memory segments */ +user_iram_seg_org = SRAM1_IRAM_START; +user_dram_seg_org = SRAM1_DRAM_START; +user_dram_end = (user_iram_end - IRAM_DRAM_OFFSET); +user_idram_size = (user_dram_end - user_dram_seg_org); +user_iram_seg_len = user_idram_size; +user_dram_seg_len = user_idram_size; + +/* Aliases */ +#define FLASH_CODE_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define DRAM_REGION dram0_0_seg +#define RAMABLE_REGION dram0_0_seg +#define ROMABLE_REGION FLASH + +/* Flash segments (rodata and text) should be mapped in the virtual address spaces. * Executing directly from LMA is not possible. */ #undef GROUP_ROM_LINK_IN #define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion @@ -57,15 +44,21 @@ /* Global symbols required for espressif hal build */ MEMORY { - mcuboot_hdr (RX): org = 0x0, len = 0x20 - metadata (RX): org = 0x20, len = 0x20 - ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 +#ifdef CONFIG_BOOTLOADER_MCUBOOT + mcuboot_hdr (R): org = 0x0, len = 0x20 + metadata (R): org = 0x20, len = 0x20 + FLASH (R): org = 0x40, len = FLASH_SIZE - 0x40 +#else + /* Make safety margin in the FLASH memory size so the + * (esp_img_header + (n*esp_seg_headers)) would fit */ + FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100 +#endif - iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE - irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN + iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len + dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len - drom0_0_seg (R) : org = 0x3C000040, len = FLASH_SIZE - 0x40 - dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE + irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN + drom0_0_seg (R): org = DROM_SEG_ORG, len = DROM_SEG_LEN rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000 @@ -74,7 +67,6 @@ MEMORY #endif } - /* The line below defines location alias for .rtc.data section * As C3 only has RTC fast memory, this is not configurable like * on other targets. @@ -86,8 +78,11 @@ ENTRY(CONFIG_KERNEL_ENTRY) _rom_store_table = 0; +_iram_dram_offset = IRAM_DRAM_OFFSET; + SECTIONS { +#ifdef CONFIG_BOOTLOADER_MCUBOOT /* Reserve space for MCUboot header in the binary */ .mcuboot_header : { @@ -98,110 +93,95 @@ SECTIONS } > mcuboot_hdr .metadata : { - /* Magic byte for load header */ + /* 0. Magic byte for load header */ LONG(0xace637d3) - /* Application entry point address */ + /* 1. Application entry point address */ KEEP(*(.entry_addr)) /* IRAM metadata: - * - Destination address (VMA) for IRAM region - * - Flash offset (LMA) for start of IRAM region - * - Size of IRAM region + * 2. Destination address (VMA) for IRAM region + * 3. Flash offset (LMA) for start of IRAM region + * 4. Size of IRAM region */ LONG(ADDR(.iram0.text)) LONG(LOADADDR(.iram0.text)) - LONG(SIZEOF(.iram0.text)) + LONG(LOADADDR(.iram0.data) - LOADADDR(.iram0.text)) /* DRAM metadata: - * - Destination address (VMA) for DRAM region - * - Flash offset (LMA) for start of DRAM region - * - Size of DRAM region + * 5. Destination address (VMA) for DRAM region + * 6. Flash offset (LMA) for start of DRAM region + * 7. Size of DRAM region */ LONG(ADDR(.dram0.data)) LONG(LOADADDR(.dram0.data)) - LONG(LOADADDR(.dummy.dram.data) + SIZEOF(.dummy.dram.data) - LOADADDR(.dram0.data)) + LONG(LOADADDR(.dram0.end) - LOADADDR(.dram0.data)) } > metadata +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ -#include - _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); - _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; - _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); - - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) - { - _rodata_reserved_start = ABSOLUTE(.); - _rodata_start = ABSOLUTE(.); + iram_vma = ADDR(.iram0.text); + iram_lma = LOADADDR(.iram0.text); + iram_size_field = LOADADDR(.iram0.data) - LOADADDR(.iram0.text); - *(.rodata_desc .rodata_desc.*) - *(.rodata_custom_desc .rodata_custom_desc.*) + dram_vma = ADDR(.dram0.data); + dram_lma = LOADADDR(.dram0.data); + dram_size_field = LOADADDR(.dram0.end) - LOADADDR(.dram0.data); - __rodata_region_start = .; + #include - . = ALIGN(4); - #include + /* --- START OF RTC --- */ + .rtc.text : + { . = ALIGN(4); - *(EXCLUDE_FILE (*libarch__riscv__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata) - *(EXCLUDE_FILE (*libarch__riscv__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*) + *(.rtc.literal .rtc.text) + *rtc_wake_stub*.o(.literal .text .literal.* .text.*) + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; + /* This section is required to skip rtc.text area because the text and + * data segments reflect the same address space on different buses. + */ + .rtc.dummy (NOLOAD): + { + . = SIZEOF(.rtc.text); + } GROUP_LINK_IN(rtc_iram_seg) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - __rodata_region_end = .; - _rodata_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - *(.srodata) - *(.srodata.*) - *(.rodata) - *(.rodata.*) - *(.rodata_wlog) - *(.rodata_wlog*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + *(.rtc.data) + *(.rtc.rodata) + *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) + _rtc_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - #include - #include - #include - #include - #include - #include - #include - #include - #include + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.o(.bss .bss.*) + *rtc_wake_stub*.o(COMMON) + _rtc_bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(rtc_iram_seg) - /* Create an explicit section at the end of all the data that shall be mapped into drom. - * This is used to calculate the size of the _image_drom_size variable */ - SECTION_PROLOGUE(_RODATA_SECTION_END,,) + /* This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : { - _rodata_reserved_end = ABSOLUTE(.); . = ALIGN(4); - _image_rodata_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } > rtc_slow_seg + + /* Get size of rtc slow data */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + + /* --- END OF RTC --- */ + + /* --- START OF IRAM --- */ .iram0.text : ALIGN(4) { @@ -214,8 +194,6 @@ SECTIONS _invalid_pc_placeholder = ABSOLUTE(.); - _iram_text_start = ABSOLUTE(.); - KEEP(*(.exception.entry*)); /* contains _isr_wrapper */ *(.exception.other*) . = ALIGN(4); @@ -224,10 +202,14 @@ SECTIONS *(.init.literal) *(.init) . = ALIGN(4); + + _init_end = ABSOLUTE(.); + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - *libesp32.a:panic.*(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) + *libzephyr.a:panic.*(.literal .text .literal.* .text.*) + *libzephyr.a:loader.*(.literal .text .literal.* .text.*) *libarch__riscv__core.a:(.literal .text .literal.* .text.*) *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*) *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*) @@ -238,7 +220,7 @@ SECTIONS *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) - *libdrivers__timer.a:esp32_sys_timer.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*) *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) @@ -247,81 +229,219 @@ SECTIONS *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) - *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:loader.*(.literal .text .literal.* .text.*) - *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) - *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_*.*(.literal .text .literal.* .text.*) *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) - *libc.a:*(.literal .text .literal.* .text.*) - *libphy.a:( .phyiram .phyiram.*) + *liblib__libc__picolib.a:string.*(.literal .text .literal.* .text.*) + *libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*) *libgcov.a:(.literal .text .literal.* .text.*) + *libphy.a:( .phyiram .phyiram.*) + *libc.a:*(.literal .text .literal.* .text.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:i2c_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.literal .literal.* .text .text.*) + + /* [mapping:log] */ + *(.literal.esp_log_write .text.esp_log_write) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_log_impl_lock .text.esp_log_impl_lock) + *(.literal.esp_log_impl_lock_timeout .text.esp_log_impl_lock_timeout) + *(.literal.esp_log_impl_unlock .text.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hpm_enable.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_oct_flash_init*(.literal .literal.* .text .text.*) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *(.literal.esp_system_abort .text.esp_system_abort) + + /* [mapping:esp_hw_support] */ + *(.literal.esp_cpu_stall .text.esp_cpu_stall) + *(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *(.literal.esp_cpu_reset .text.esp_cpu_reset) + *(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *(.literal.rtc_vddsdio_get_config .text.rtc_vddsdio_get_config) + *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*) + *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + + /* [mapping:soc_pm] */ + *(.literal.GPIO_HOLD_MASK .text.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) + *libzephyr.a:cache_utils.*(.literal .text .literal.* .text.*) #if defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) -#endif + *libcoexist.a:(.wifi_slp_iram .wifi_slp_iram.*) + + /* [mapping:esp_wifi] */ + *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper) + *(.literal.wifi_clock_disable_wrapper .text.wifi_clock_disable_wrapper) + + /* [mapping:esp_phy] */ + *(.literal.esp_phy_enable .text.esp_phy_enable) + *(.literal.esp_phy_disable .text.esp_phy_disable) + *(.literal.esp_wifi_bt_power_domain_off .text.esp_wifi_bt_power_domain_off) +#endif /* CONFIG_ESP32_WIFI_IRAM_OPT */ #if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif - . = ALIGN(4); - _init_end = ABSOLUTE(.); +#endif /* CONFIG_ESP32_WIFI_RX_IRAM_OPT */ + + . = ALIGN(4) + 16; + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - .dram0.dummy (NOLOAD): +#ifdef CONFIG_ESP_SIMPLE_BOOT + .loader.text : { - /** - * This section is required to skip .iram0.text area because iram0_0_seg and - * dram0_0_seg reflect the same address space on different buses. - */ - . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; - } GROUP_LINK_IN(RAMABLE_REGION) + . = ALIGN(4); + _loader_text_start = ABSOLUTE(.); + *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_esp32c3.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_wdt.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash_config_esp32c3.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_mem.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + *libzephyr.a:bootloader_efuse.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) + + *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_ops.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_ops_esp32c3.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_flash_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_flash_spi_init.*(.literal .text .literal.* .text.*) + + *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) + + *libzephyr.a:cpu_region_protect.*(.literal .text .literal.* .text.*) + + /* ??? */ + *libzephyr.a:esp_gpio_reserve.*(.literal .text .literal.* .text.*) + + . = ALIGN(0x10) + 0x10; + _loader_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ - /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + .iram0.text_end (NOLOAD) : { - . = ALIGN (8); - __bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - __bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) + /* C3 memprot requires 512 B alignment for split lines */ + . = ALIGN (16); + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) + .iram0.data : { - . = ALIGN(4); - *(.noinit) - *(.noinit.*) - . = ALIGN(4); + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + /* --- END OF IRAM --- */ + + /* --- START OF DRAM --- */ + + .dram0.dummy (NOLOAD): + { + /* Spacer section is required to skip .iram0.text area because + * iram0_0_seg and dram0_0_seg reflect the same address space on different buses. + */ + . = ORIGIN(dram0_0_seg) + MAX(_iram_end, user_iram_seg_org) - user_iram_seg_org; + . = ALIGN(16) + 16; } GROUP_LINK_IN(RAMABLE_REGION) .dram0.data : { . = ALIGN(4); _data_start = ABSOLUTE(.); + __data_start = ABSOLUTE(.); + *(.data) *(.data.*) *(.gnu.linkonce.d.*) *(.data1) + #ifdef CONFIG_RISCV_GP + . = ALIGN(8); __global_pointer$ = . + 0x800; #endif /* CONFIG_RISCV_GP */ + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) @@ -331,27 +451,125 @@ SECTIONS /* All dependent functions should be placed in DRAM to avoid issue * when flash cache is disabled */ - *libkernel.a:fatal.*(.rodata .rodata.*) - *libkernel.a:init.*(.rodata .rodata.*) - *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) - *libzephyr.a:log_core.*(.rodata .rodata.*) - *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) - *libzephyr.a:log_output.*(.rodata .rodata.*) - *libzephyr.a:cache_hal.*(.rodata .rodata.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.*) - *libzephyr.a:loader.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) - *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) - *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) + *libkernel.a:fatal.*(.rodata .rodata.* .srodata .srodata.*) + *libkernel.a:init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:cbprintf_complete*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.* .srodata .srodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.* .srodata .srodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:periph_ctrl.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:loader.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:cache_utils.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:cache_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:log] */ + *(.rodata.esp_log_write) + *(.rodata.esp_log_timestamp) + *(.rodata.esp_log_early_timestamp) + *(.rodata.esp_log_impl_lock) + *(.rodata.esp_log_impl_lock_timeout) + *(.rodata.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hpm_enable.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_oct_flash_init.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:esp_hw_support] */ + *(.rodata.esp_cpu_stall) + *(.rodata.esp_cpu_unstall) + *(.rodata.esp_cpu_reset) + *(.rodata.esp_cpu_wait_for_intr) + *(.rodata.esp_cpu_compare_and_set) + *(.rodata.esp_gpio_reserve_pins) + *(.rodata.esp_gpio_is_pin_reserved) + *(.rodata.rtc_vddsdio_get_config) + *(.rodata.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:rtc_clk_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:systimer.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:mspi_timing_config.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.* .srodata .srodata.*) + *(.rodata.sar_periph_ctrl_power_enable) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.rodata .rodata.*) + *(.rodata.esp_system_abort) + . = ALIGN(4); + #include + . = ALIGN(4); KEEP(*(.jcr)) *(.dram1 .dram1.*) . = ALIGN(4); } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - #include - #include +#ifdef CONFIG_ESP_SIMPLE_BOOT + /* Secondary loader sections */ + .loader.data : + { + . = ALIGN(4); + _loader_data_start = ABSOLUTE(.); + *libzephyr.a:bootloader_soc.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_esp32c3.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_clock_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_wdt.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_flash.*(.srodata .srodata.* .rodata .rodata.*) + *libzephyr.a:bootloader_flash_config_esp32c3.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_clock_loader.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_common_loader.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_panic.*(.rodata .rodata.* .srodata .srodata.*) + + *libzephyr.a:cpu_region_protect.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:clk.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_clk.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_mmap.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_ops.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_ops_esp32c3.*(.rodata .rodata.* .srodata .srodata.*) + + *libzephyr.a:esp_gpio_reserve.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_flash_api.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_flash_spi_init.*(.rodata .rodata.* .srodata .srodata.*) + + . = ALIGN(16); + _loader_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ + #include #include #include @@ -364,68 +582,187 @@ SECTIONS #include #pragma pop_macro("GROUP_ROM_LINK_IN") - .dummy.dram.data : + .dram0.end : { . = ALIGN(4); - #include - _end = ABSOLUTE(.); _data_end = ABSOLUTE(.); + __data_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - .iram0.text_end (NOLOAD) : + .dram0.noinit (NOLOAD): { - /* C3 memprot requires 512 B alignment for split lines */ + . = ALIGN(4); + *(.noinit) + *(.noinit.*) + . = ALIGN(4); + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + __bss_start = ABSOLUTE(.); + _bss_start = ABSOLUTE(.); + + /* bluetooth library requires this symbol to be defined */ + _btdm_bss_start = ABSOLUTE(.); + *libbtdm_app.a:(.bss .bss.* COMMON) + . = ALIGN (4); + _btdm_bss_end = ABSOLUTE(.); + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) . = ALIGN (16); - } GROUP_LINK_IN(IRAM_REGION) + __bss_end = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) - .iram0.data : + /* Provide total SRAM usage, including IRAM and DRAM */ + _image_ram_start = _iram_start - IRAM_DRAM_OFFSET; + #include + + ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + + /* --- END OF DRAM --- */ + + /* --- START OF .rodata --- */ + + /* Align next section to 64k to allow mapping */ + .flash.rodata_dummy (NOLOAD) : { - . = ALIGN(16); - *(.iram.data) - *(.iram.data*) - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + . = ALIGN(CACHE_ALIGN); + } GROUP_LINK_IN(ROMABLE_REGION) - .iram0.bss (NOLOAD) : + /* Symbols used during the application memory mapping */ + _image_drom_start = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata_end) + SIZEOF(.flash.rodata_end) - _image_drom_start; + _image_drom_vaddr = ADDR(.flash.rodata); + + .flash.rodata : ALIGN(0x10) { - . = ALIGN(16); - *(.iram.bss) - *(.iram.bss*) + _rodata_reserved_start = ABSOLUTE(.); + _rodata_start = ABSOLUTE(.); - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) + *(.rodata_desc .rodata_desc.*) + *(.rodata_custom_desc .rodata_custom_desc.*) + + __rodata_region_start = .; + + . = ALIGN(4); + #include + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + __rodata_region_end = .; + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + *(.srodata) + *(.srodata.*) + *(.rodata) + *(.rodata.*) + *(.rodata_wlog) + *(.rodata_wlog*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + .flash.rodata_end : ALIGN(0x10) + { + . = ALIGN(4); + _rodata_reserved_end = ABSOLUTE(.); + _image_rodata_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + /* --- END OF .rodata --- */ + + /* --- START OF .flash.text --- */ + + /* Symbols used during the application memory mapping */ _image_irom_start = LOADADDR(.flash.text); _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; _image_irom_vaddr = ADDR(.flash.text); - .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN) + .flash.text_dummy (NOLOAD): { - . = SIZEOF(_RODATA_SECTION_NAME); - . = ALIGN(0x10000) + 0x20; - } GROUP_LINK_IN(FLASH_CODE_REGION) + /* Spacer in the IROM address to avoid interfering with the DROM address + * because DROM and IROM regions share the same address space */ + . += _image_rodata_end - _rodata_start; + . = ALIGN(CACHE_ALIGN); + } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - .flash.text : ALIGN(IROM_SEG_ALIGN) + .flash.text : ALIGN(CACHE_ALIGN) { _stext = .; _instruction_reserved_start = ABSOLUTE(.); _text_start = ABSOLUTE(.); + _instruction_reserved_start = ABSOLUTE(.); #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) -#endif +#endif /* CONFIG_ESP32_WIFI_IRAM_OPT */ #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif +#endif /* CONFIG_ESP32_WIFI_RX_IRAM_OPT */ *(.literal .text .literal.* .text.*) *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) *(.fini) + *(.gnu.version) /** CPU will try to prefetch up to 16 bytes of @@ -435,6 +772,7 @@ SECTIONS */ . += 16; + _instruction_reserved_end = ABSOLUTE(.); _text_end = ABSOLUTE(.); _instruction_reserved_end = ABSOLUTE(.); _etext = .; @@ -444,63 +782,16 @@ SECTIONS * resolved by addr2line in preference to the first symbol in * the flash.text segment. */ - _flash_cache_start = ABSOLUTE(0); + //_flash_cache_start = ABSOLUTE(0); } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - .rtc.text : - { - . = ALIGN(4); - *(.rtc.literal .rtc.text) - *rtc_wake_stub*.o(.literal .text .literal.* .text.*) - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - - /* This section is required to skip rtc.text area because the text and - * data segments reflect the same address space on different buses. - */ - .rtc.dummy (NOLOAD): - { - . = SIZEOF(.rtc.text); - } GROUP_LINK_IN(rtc_iram_seg) - - .rtc.data : - { - _rtc_data_start = ABSOLUTE(.); - *(.rtc.data) - *(.rtc.rodata) - *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) - _rtc_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.o(.bss .bss.*) - *rtc_wake_stub*.o(COMMON) - _rtc_bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(rtc_iram_seg) - - /** - * This section located in RTC SLOW Memory area. - * It holds data marked with RTC_SLOW_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : - { - . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } > rtc_slow_seg - - /* Get size of rtc slow data */ - _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + /* --- END OF .flash.text --- */ #ifdef CONFIG_GEN_ISR_TABLES -#include + #include #endif -#include + #include /DISCARD/ : { *(.note.GNU-stack) } SECTION_PROLOGUE(.riscv.attributes, 0,) diff --git a/soc/espressif/esp32c3/mcuboot.ld b/soc/espressif/esp32c3/mcuboot.ld index 958018168e1..8f402f566be 100644 --- a/soc/espressif/esp32c3/mcuboot.ld +++ b/soc/espressif/esp32c3/mcuboot.ld @@ -1,20 +1,15 @@ /* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the esp32c3 platform. - */ - #include #include #include #include +#include "memory.h" + #ifdef CONFIG_XIP #error "ESP32C3 bootloader cannot use XIP" #endif /* CONFIG_XIP */ @@ -24,20 +19,18 @@ #define GROUP_DATA_LINK_IN(vregion, lregion) > vregion #define RAMABLE_REGION dram_seg -#define RODATA_REGION dram_seg - -#define IRAM_REGION iram_seg -#define IRAM_LOADER_REGION iram_loader_seg - +#define RODATA_REGION dram_seg #define ROMABLE_REGION dram_seg -#define IROM_SEG_ALIGN 0x4 /* Global symbols required for espressif hal build */ MEMORY { - iram_seg (RX) : org = 0x403CA000, len = 0x9000 - iram_loader_seg (RX) : org = 0x403D3000, len = 0x4000 - dram_seg (RW) : org = 0x3FCD8000, len = 0x9000 + iram_seg (RX) : org = BOOTLOADER_IRAM_SEG_START, + len = BOOTLOADER_IRAM_SEG_LEN + iram_loader_seg (RX) : org = BOOTLOADER_IRAM_LOADER_SEG_START, + len = BOOTLOADER_IRAM_LOADER_SEG_LEN + dram_seg (RW) : org = BOOTLOADER_DRAM_SEG_START, + len = BOOTLOADER_DRAM_SEG_LEN #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -49,15 +42,135 @@ ENTRY(CONFIG_KERNEL_ENTRY) SECTIONS { - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + .iram0.loader_text : + { + . = ALIGN (16); + _loader_text_start = ABSOLUTE(.); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + + /* TODO: cross-segments calls in the libzephyr.a:device.* */ + + *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*) + + *libzephyr.a:heap.*(.literal .text .literal.* .text.*) + + *libkernel.a:kheap.*(.literal .text .literal.* .text.*) + *libkernel.a:mempool.*(.literal .text .literal.* .text.*) + + *(.literal.bootloader_mmap .text.bootloader_mmap) + *(.literal.bootloader_munmap .text.bootloader_munmap) + + *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + + *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*) + *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_system_abort .text.esp_system_abort) + + *(.fini.literal) + *(.fini) + *(.gnu.version) + _loader_text_end = ABSOLUTE(.); + _iram_end = ABSOLUTE(.); + } > iram_loader_seg + + .iram0.text : + { + /* Vectors go to IRAM */ + _iram_start = ABSOLUTE(.); + _init_start = ABSOLUTE(.); + + KEEP(*(.exception_vectors.text)); + . = ALIGN(256); + + _invalid_pc_placeholder = ABSOLUTE(.); + + _iram_text_start = ABSOLUTE(.); + + KEEP(*(.exception.entry*)); /* contains _isr_wrapper */ + *(.exception.other*) + . = ALIGN(4); + + *(.entry.text) + *(.init.literal) + *(.init) + . = ALIGN(4); + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + + /* C3 memprot requires 512 B alignment for split lines */ + . = ALIGN (16); + _init_end = ABSOLUTE(.); + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + + *(.literal .text .literal.* .text.*) + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /* CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } > iram_seg + + .dram0.data : { - _rodata_start = ABSOLUTE(.); + . = ALIGN(4); + __data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) +#ifdef CONFIG_RISCV_GP + __global_pointer$ = . + 0x800; +#endif /* CONFIG_RISCV_GP */ + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + + #include + . = ALIGN(4); *(.rodata_desc .rodata_desc.*) *(.rodata_custom_desc .rodata_custom_desc.*) - __rodata_region_start = .; - . = ALIGN(4); #include . = ALIGN(4); @@ -108,39 +221,14 @@ SECTIONS _thread_local_end = ABSOLUTE(.); /* _rodata_reserved_end = ABSOLUTE(.); */ . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + } > dram_seg #include #include #include #include - #include - .dram0.data : - { - . = ALIGN(4); - __data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) -#ifdef CONFIG_RISCV_GP - __global_pointer$ = . + 0x800; -#endif /* CONFIG_RISCV_GP */ - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.*) - *libzephyr.a:rtc_clk.*(.rodata .rodata.*) - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - #include #include #include @@ -150,17 +238,16 @@ SECTIONS #include - .dram0.end : + .noinit (NOLOAD): { . = ALIGN(4); - #include + *(.noinit) + *(.noinit.*) . = ALIGN(4); - _end = ABSOLUTE(.); - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + } > dram_seg /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + .bss (NOLOAD): { . = ALIGN (8); _bss_start = ABSOLUTE(.); @@ -182,155 +269,13 @@ SECTIONS . = ALIGN (8); __bss_end = ABSOLUTE(.); _bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) - - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN(4); - *(.noinit) - *(.noinit.*) - . = ALIGN(4); - } GROUP_LINK_IN(RAMABLE_REGION) - - .iram_loader.text : - { - . = ALIGN (16); - _loader_text_start = ABSOLUTE(.); - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ - *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_flash_config_esp32c3.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_init_common.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libzephyr.a:bootloader_efuse_esp32c3.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) - *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) - *esp_mcuboot.*(.literal .text .literal.* .text.*) - *esp_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) - *(.fini.literal) - *(.fini) - *(.gnu.version) - _loader_text_end = ABSOLUTE(.); - } > iram_loader_seg - - /* .iram0.text : ALIGN(4) */ - SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) - { - /* Vectors go to IRAM */ - _iram_start = ABSOLUTE(.); - _init_start = ABSOLUTE(.); - - KEEP(*(.exception_vectors.text)); - . = ALIGN(256); - - _invalid_pc_placeholder = ABSOLUTE(.); - - _iram_text_start = ABSOLUTE(.); - - KEEP(*(.exception.entry*)); /* contains _isr_wrapper */ - *(.exception.other*) - . = ALIGN(4); - - *(.entry.text) - *(.init.literal) - *(.init) - . = ALIGN(4); - *(.iram1 .iram1.*) - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - - . = ALIGN(4); - _init_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_LOADER_REGION, ROMABLE_REGION) - - .iram0.text_end (NOLOAD) : - { - /* C3 memprot requires 512 B alignment for split lines */ - . = ALIGN (16); - } GROUP_LINK_IN(IRAM_LOADER_REGION) - - .iram0.data : - { - . = ALIGN(16); - *(.iram.data) - *(.iram.data*) - } GROUP_DATA_LINK_IN(IRAM_LOADER_REGION, ROMABLE_REGION) - - .iram0.bss (NOLOAD) : - { - . = ALIGN(16); - *(.iram.bss) - *(.iram.bss*) - - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_LOADER_REGION) - - .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN) - { - . = SIZEOF(_RODATA_SECTION_NAME); - . = ALIGN(4) + 0x20; - _rodata_reserved_start = .; - } GROUP_LINK_IN(IRAM_REGION) - - .flash.text : ALIGN(IROM_SEG_ALIGN) - { - _stext = .; - _text_start = ABSOLUTE(.); - - *(.literal .text .literal.* .text.*) - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - - /* CPU will try to prefetch up to 16 bytes of - * of instructions. This means that any configuration (e.g. MMU, PMS) must allow - * safe access to up to 16 bytes after the last real instruction, add - * dummy bytes to ensure this - */ - . += 16; - - _text_end = ABSOLUTE(.); - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + } > dram_seg /* linker rel sections*/ #include #ifdef CONFIG_GEN_ISR_TABLES -#include + #include #endif #include diff --git a/soc/espressif/esp32c3/memory.h b/soc/espressif/esp32c3/memory.h new file mode 100644 index 00000000000..f249f8b9643 --- /dev/null +++ b/soc/espressif/esp32c3/memory.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/* SRAM0 (16kB) memory */ +#define SRAM0_IRAM_START 0x4037c000 +#define SRAM0_SIZE 0x4000 +/* SRAM1 (384kB) memory */ +#define SRAM1_DRAM_START 0x3fc80000 +#define SRAM1_IRAM_START 0x40380000 +/* ICache size is fixed to 16KB on ESP32-C3 */ +#define ICACHE_SIZE SRAM0_SIZE + +/** Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32-C3 ROM static data usage is as follows: + * - 0x3fccae00 - 0x3fcdc710: Shared buffers, used in UART/USB/SPI download mode only + * - 0x3fcdc710 - 0x3fcde710: PRO CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fcde710 - 0x3fce0000: ROM .bss and .data (not easily reclaimable) + * + * The 2nd stage bootloader can take space up to the end of ROM shared + * buffers area (0x3fcdc710). + */ + +/* The offset between Dbus and Ibus. + * Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. + */ +#define IRAM_DRAM_OFFSET 0x700000 +#define DRAM_BUFFERS_START 0x3fccae00 +#define DRAM_STACK_START 0x3fcdc710 +#define DRAM_ROM_BSS_DATA_START 0x3fcde710 + +/* Base address used for calculating memory layout + * counted from Dbus backwards and back to the Ibus + */ +#define BOOTLOADER_USABLE_DRAM_END DRAM_BUFFERS_START + +/* For safety margin between bootloader data section and startup stacks */ +#define BOOTLOADER_STACK_OVERHEAD 0x0 +/* These lengths can be adjusted, if necessary: */ +#define BOOTLOADER_DRAM_SEG_LEN 0x9000 +#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x3000 +#define BOOTLOADER_IRAM_SEG_LEN 0x8000 + +/* Start of the lower region is determined by region size and the end of the higher region */ +#define BOOTLOADER_DRAM_SEG_END (BOOTLOADER_USABLE_DRAM_END + BOOTLOADER_STACK_OVERHEAD) +#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_DRAM_SEG_END - BOOTLOADER_DRAM_SEG_LEN) +#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_DRAM_SEG_START - \ + BOOTLOADER_IRAM_LOADER_SEG_LEN + IRAM_DRAM_OFFSET) +#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN) + +/* Flash */ +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x400000 +#endif + +/* Cached memory */ +#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE +#define IROM_SEG_ORG 0x42000000 +#define IROM_SEG_LEN FLASH_SIZE +#define DROM_SEG_ORG 0x3c000000 +#define DROM_SEG_LEN FLASH_SIZE diff --git a/soc/espressif/esp32c3/soc.c b/soc/espressif/esp32c3/soc.c index c25f188da89..cb13c6205af 100644 --- a/soc/espressif/esp32c3/soc.c +++ b/soc/espressif/esp32c3/soc.c @@ -43,17 +43,6 @@ extern void esp_reset_reason_init(void); */ void __attribute__((section(".iram1"))) __esp_platform_start(void) { -#ifdef CONFIG_RISCV_GP - /* Configure the global pointer register - * (This should be the first thing startup does, as any other piece of code could be - * relaxed by the linker to access something relative to __global_pointer$) - */ - __asm__ __volatile__(".option push\n" - ".option norelax\n" - "la gp, __global_pointer$\n" - ".option pop"); -#endif /* CONFIG_RISCV_GP */ - __asm__ __volatile__("la t0, _esp32c3_vector_table\n" "csrw mtvec, t0\n"); @@ -64,12 +53,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) esp_reset_reason_init(); -#ifdef CONFIG_MCUBOOT - /* MCUboot early initialisation. - */ - bootloader_init(); - -#else +#ifndef CONFIG_MCUBOOT /* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence * related issues in application. Hence disable that as we are about to start * Zephyr environment. @@ -103,13 +87,13 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) #ifdef CONFIG_SOC_FLASH_ESP32 esp_mspi_pin_init(); - /** - * This function initialise the Flash chip to the user-defined settings. - * - * In bootloader, we only init Flash (and MSPI) to a preliminary state, for being flexible to - * different chips. - * In this stage, we re-configure the Flash (and MSPI) to required configuration - */ + /** + * This function initialise the Flash chip to the user-defined settings. + * + * In bootloader, we only init Flash (and MSPI) to a preliminary + * state, for being flexible to different chips. + * In this stage, we re-configure the Flash (and MSPI) to required configuration + */ spi_flash_init_chip_state(); esp_mmu_map_init(); @@ -127,7 +111,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) spi_flash_guard_set(&g_flash_guard_default_ops); #endif -#endif /* CONFIG_MCUBOOT */ +#endif /* !CONFIG_MCUBOOT */ /*Initialize the esp32c3 interrupt controller */ esp_intr_initialize(); From 553238704f67c20a54493b32a4879b175b118d87 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Thu, 14 Dec 2023 00:09:17 +0100 Subject: [PATCH 1996/2402] soc: espressif: esp32s3: simple boot support Add simplistic booting method which allows to run applications without the 2nd stage bootloader. - introduce memory layout header file - update and optimize default and mcuboot linker scripts - remove building multiple binaries during the application build Signed-off-by: Marek Matej --- soc/espressif/esp32s3/CMakeLists.txt | 57 ++-- soc/espressif/esp32s3/default.ld | 370 +++++++++++++++---------- soc/espressif/esp32s3/mcuboot.ld | 388 +++++++++++---------------- soc/espressif/esp32s3/memory.h | 80 ++++++ soc/espressif/esp32s3/soc.c | 10 +- 5 files changed, 485 insertions(+), 420 deletions(-) create mode 100644 soc/espressif/esp32s3/memory.h diff --git a/soc/espressif/esp32s3/CMakeLists.txt b/soc/espressif/esp32s3/CMakeLists.txt index 0a261dbe1e0..540881b45ab 100644 --- a/soc/espressif/esp32s3/CMakeLists.txt +++ b/soc/espressif/esp32s3/CMakeLists.txt @@ -19,44 +19,31 @@ zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) zephyr_library_sources_ifdef(CONFIG_PM power.c) zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) -# get flash size to use in esptool as string +# Get flash size to use in esptool as string math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") -if(CONFIG_BOOTLOADER_ESP_IDF) +# Make rom loader compatible binary file +if(NOT CONFIG_BOOTLOADER_MCUBOOT) - set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") - - if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") - endif() - - if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") - endif() - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + if(CONFIG_BUILD_OUTPUT_BIN) -endif() + set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py) + message("esptool path: ${ESPTOOL_PY}") -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + set(ELF2IMAGE_ARG "") + if(NOT CONFIG_MCUBOOT) + set(ELF2IMAGE_ARG "--ram-only-header") + endif() - if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py - ARGS --chip esp32s3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY} + ARGS --chip esp32s3 elf2image ${ELF2IMAGE_ARG} + --flash_mode dio --flash_freq 40m + --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) endif() - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - endif() ## When building for APPCPU @@ -74,17 +61,19 @@ else() set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - # get code-partition slot0 address - dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") - dt_reg_addr(img_0_off PATH ${dts_partition_path}) - - # get code-partition boot address + # Get code-partition boot address dt_nodelabel(dts_partition_path NODELABEL "boot_partition") dt_reg_addr(boot_off PATH ${dts_partition_path}) - board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") + # Get code-partition slot0 address + dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") + dt_reg_addr(img_0_off PATH ${dts_partition_path}) - board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + if(NOT CONFIG_BOOTLOADER_MCUBOOT) + board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}") + else() + board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + endif() endif() diff --git a/soc/espressif/esp32s3/default.ld b/soc/espressif/esp32s3/default.ld index 3a9aa37794d..120fb083d38 100644 --- a/soc/espressif/esp32s3/default.ld +++ b/soc/espressif/esp32s3/default.ld @@ -1,97 +1,70 @@ /* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the ESP32S3 platform. - */ - #include #include #include #include -#define SRAM_IRAM_START 0x40370000 -#define SRAM_DIRAM_I_START 0x40378000 -/* SRAM_IRAM_END is equivalent 2nd stage bootloader iram_loader_seg - start address (that should not be overlapped) */ -#define SRAM_IRAM_END 0x403BA000 -#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START) - -#define SRAM_DRAM_START 0x3FC88000 -#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET) -#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START) - -#define ICACHE_SIZE 0x8000 -#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) -#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) - -#define SRAM_DRAM_ORG (SRAM_DRAM_START) +#include "memory.h" -#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE - -#define FLASH_CODE_REGION irom0_0_seg -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define RAMABLE_REGION dram0_0_seg -#define ROMABLE_REGION ROM - -#ifdef CONFIG_FLASH_SIZE -#define FLASH_SIZE CONFIG_FLASH_SIZE -#else -#define FLASH_SIZE 0x800000 -#endif - -#ifdef CONFIG_BOOTLOADER_ESP_IDF -#define IROM_SEG_ORG 0x42000020 -#define IROM_SEG_LEN FLASH_SIZE-0x20 -#define IROM_SEG_ALIGN 0x10 -#else -#define IROM_SEG_ORG 0x42000000 -#define IROM_SEG_LEN FLASH_SIZE -/* MCUBoot requires MMU page size alignment */ -#define IROM_SEG_ALIGN 0x10000 -#endif - -#ifdef CONFIG_SOC_ENABLE_APPCPU -#define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM -#define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM +/* The "user_iram_end" represents the 2nd stage bootloader + * "iram_loader_seg" start address (that should not be overlapped). + * If no bootloader is used, we can extend it to gain more user ram. + */ +#ifdef CONFIG_ESP_SIMPLE_BOOT +user_iram_end = (DRAM_BUFFERS_START + IRAM_DRAM_OFFSET); #else -#define APPCPU_IRAM_SIZE 0x0 -#define APPCPU_DRAM_SIZE 0x0 +user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START; #endif -/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. +/* User available SRAM memory segments */ +user_dram_seg_org = SRAM1_DRAM_START; +user_iram_seg_org = (SRAM0_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE); +user_dram_end = (user_iram_end - IRAM_DRAM_OFFSET); +user_idram_size = (user_dram_end - SRAM1_DRAM_START); +sram0_iram_size = (SRAM0_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE); +user_iram_seg_len = (user_idram_size + sram0_iram_size); +user_dram_seg_len = user_idram_size; + +/* Aliases */ +#define FLASH_CODE_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define RAMABLE_REGION dram0_0_seg +#define ROMABLE_REGION FLASH + +/* Flash segments (rodata and text) should be mapped in the virtual address spaces. * Executing directly from LMA is not possible. */ #undef GROUP_ROM_LINK_IN #define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion MEMORY { - mcuboot_hdr (RX): org = 0x0, len = 0x20 - metadata (RX): org = 0x20, len = 0x20 - ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 - iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE - APPCPU_IRAM_SIZE - dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN - APPCPU_DRAM_SIZE +#ifdef CONFIG_BOOTLOADER_MCUBOOT + mcuboot_hdr (R): org = 0x0, len = 0x20 + metadata (R): org = 0x20, len = 0x20 + FLASH (R): org = 0x40, len = FLASH_SIZE - 0x40 +#else + /* Make safety margin in the FLASH memory size so the + * (esp_img_header + (n*esp_seg_headers)) would fit */ + FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100 +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ - irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN + iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len - APPCPU_IRAM_SIZE + dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len - APPCPU_DRAM_SIZE - /* MCUboot binary for ESP32 has image header of 0x20 bytes. - * Additional load header of 0x20 bytes are appended to the image. - * Hence, an offset of 0x40 is added to DROM segment origin. - */ - drom0_0_seg(R): org = 0x3C000040, len = FLASH_SIZE - 0x40 + irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN + drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN /** * `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region. * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in` */ #if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RWX): org = 0x3C000040, len = CONFIG_ESP_SPIRAM_SIZE - 0x40 + ext_ram_seg(RWX): org = DROM_SEG_ORG, len = CONFIG_ESP_SPIRAM_SIZE - 0x40 #endif /* RTC fast memory (executable). Persists over deep sleep. @@ -111,13 +84,17 @@ MEMORY #endif } -_esp_mmu_block_size = (CONFIG_MMU_PAGE_SIZE); - /* Default entry point: */ ENTRY(CONFIG_KERNEL_ENTRY) +/* Used as a pointer to the heap end */ +_heap_sentry = DRAM_BUFFERS_START; + SECTIONS { + _iram_dram_offset = IRAM_DRAM_OFFSET; + +#ifdef CONFIG_BOOTLOADER_MCUBOOT /* Reserve space for MCUboot header in the binary */ .mcuboot_header : { @@ -128,32 +105,37 @@ SECTIONS } > mcuboot_hdr .metadata : { - /* Magic byte for load header */ + /* 0. Magic byte for load header */ LONG(0xace637d3) - /* Application entry point address */ + /* 1. Application entry point address */ KEEP(*(.entry_addr)) /* IRAM metadata: - * - Destination address (VMA) for IRAM region - * - Flash offset (LMA) for start of IRAM region - * - Size of IRAM region + * 2. Destination address (VMA) for IRAM region + * 3. Flash offset (LMA) for start of IRAM region + * 4. Size of IRAM region */ LONG(ADDR(.iram0.vectors)) LONG(LOADADDR(.iram0.vectors)) LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors)) /* DRAM metadata: - * - Destination address (VMA) for DRAM region - * - Flash offset (LMA) for start of DRAM region - * - Size of DRAM region + * 5. Destination address (VMA) for DRAM region + * 6. Flash offset (LMA) for start of DRAM region + * 7. Size of DRAM region */ LONG(ADDR(.dram0.data)) LONG(LOADADDR(.dram0.data)) LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) } > metadata +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ - #include + +/* Virtual non-loadable sections */ +#include + + /* --- START OF RTC --- */ /* RTC fast memory holds RTC wake stub code */ .rtc.text : @@ -224,7 +206,7 @@ SECTIONS . = ALIGN(4); _rtc_force_slow_start = ABSOLUTE(.); *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; + . = ALIGN(4); _rtc_force_slow_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) @@ -235,6 +217,10 @@ SECTIONS ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") + /* --- END OF RTC --- */ + + /* --- START OF IRAM --- */ + /* Send .iram0 code to iram */ .iram0.vectors : ALIGN(4) { @@ -365,6 +351,7 @@ SECTIONS *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .text .literal.* .text.*) *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) @@ -377,7 +364,6 @@ SECTIONS /* [mapping:esp_rom] */ *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_rom_cache_writeback_esp32s3.*(.literal .literal.* .text .text.*) *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*) @@ -404,25 +390,109 @@ SECTIONS *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) #endif + . = ALIGN(4); + + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + +#ifdef CONFIG_ESP_SIMPLE_BOOT + .loader.text : + { + . = ALIGN(4); + _loader_text_start = ABSOLUTE(.); + *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_esp32s3.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_wdt.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash_config_esp32s3.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_mem.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + *libzephyr.a:bootloader_efuse.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) + + *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_flash_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_flash_spi_init.*(.literal .text .literal.* .text.*) + + *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) + *libzephyr.a:mpu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu_region_protect.*(.literal .text .literal.* .text.*) + + *(.fini.literal) + *(.fini) + + . = ALIGN(4); + _loader_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : + { + /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */ . = ALIGN(4) + 16; + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + .iram0.data : + { + . = ALIGN(4); + _iram_data_start = ABSOLUTE(.); + *(.iram.data) + *(.iram.data*) + _iram_data_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - /** - * This section is required to skip .iram0.text area because iram0_0_seg and - * dram0_0_seg reflect the same address space on different buses. - */ + .iram0.bss (NOLOAD) : + { + . = ALIGN(4); + _iram_bss_start = ABSOLUTE(.); + *(.iram.bss) + *(.iram.bss*) + _iram_bss_end = ABSOLUTE(.); + . = ALIGN(4); + _iram_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + /* --- END OF IRAM --- */ + + /* --- START OF DRAM --- */ + .dram0.dummy (NOLOAD): { - . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM_DIRAM_I_START) - SRAM_DIRAM_I_START; + /* Spacer section is required to skip .iram0.text area because + * iram0_0_seg and dram0_0_seg reflect the same address space on different buses. + */ + . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM1_IRAM_START) - SRAM1_IRAM_START; + . = ALIGN(4) + 16; } GROUP_LINK_IN(RAMABLE_REGION) .dram0.data : { . = ALIGN (8); + _data_start = ABSOLUTE(.); __data_start = ABSOLUTE(.); - _image_ram_start = ABSOLUTE(.); + /* bluetooth library requires this symbol to be defined */ _btdm_data_start = ABSOLUTE(.); *libbtdm_app.a:(.data .data.*) @@ -515,6 +585,7 @@ SECTIONS *(.rodata.rtc_vddsdio_set_config) *libzephyr.a:esp_memory_utils.*(.rodata .rodata.*) *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk_init.*(.rodata .rodata.*) *libzephyr.a:systimer.*(.rodata .rodata.*) *libzephyr.a:mspi_timing_config.*(.rodata .rodata.*) *libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.*) @@ -525,7 +596,6 @@ SECTIONS /* [mapping:esp_rom] */ *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*) - *libzephyr.a:esp_rom_cache_writeback_esp32s3.*(.rodata .rodata.*) *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.*) *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.*) *libzephyr.a:esp_rom_wdt.*(.rodata .rodata.*) @@ -545,12 +615,43 @@ SECTIONS *(.rodata.esp_wifi_bt_power_domain_off) #endif + . = ALIGN(4); + #include + . = ALIGN(4); + KEEP(*(.jcr)) *(.dram1 .dram1.*) . = ALIGN(4); } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - #include +#ifdef CONFIG_ESP_SIMPLE_BOOT + .loader.data : + { + . = ALIGN(4); + _loader_data_start = ABSOLUTE(.); + *libzephyr.a:bootloader_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_esp32s3.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_clock_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_wdt.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_flash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_flash_config_esp32s3.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_efuse.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:cpu_util.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:cpu_region_protect.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:spi_flash_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_flash_api.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_flash_spi_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + . = ALIGN(4); + _loader_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ + #include #include #include @@ -566,13 +667,11 @@ SECTIONS .dram0.end : { - . = ALIGN(4); - #include - . = ALIGN(4); __data_end = ABSOLUTE(.); + _data_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - .noinit (NOLOAD): + .dram0.noinit (NOLOAD): { . = ALIGN(4); *(.noinit) @@ -580,7 +679,7 @@ SECTIONS . = ALIGN(4) ; } GROUP_LINK_IN(RAMABLE_REGION) - /* Shared RAM */ + /* Shared RAM */ .dram0.bss (NOLOAD) : { . = ALIGN (8); @@ -608,18 +707,39 @@ SECTIONS *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN (8); + _bss_end = ABSOLUTE(.); __bss_end = ABSOLUTE(.); } GROUP_LINK_IN(RAMABLE_REGION) -#include + .dram0.heap_start (NOLOAD) : + { + . = ALIGN (8); + /* Lowest possible start address for the heap */ + _heap_start = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Provide total SRAM usage, including IRAM and DRAM */ + _image_ram_start = _iram_start - IRAM_DRAM_OFFSET; + #include ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + /* --- END OF DRAM --- */ + + /* --- START OF IROM --- */ + + /* Symbols used during the application memory mapping */ _image_irom_start = LOADADDR(.flash.text); _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; _image_irom_vaddr = ADDR(.flash.text); - .flash.text : ALIGN(IROM_SEG_ALIGN) + /* Align next section to 64k to allow mapping */ + .flash.text_dummy (NOLOAD) : + { + . = ALIGN(CACHE_ALIGN); + } GROUP_LINK_IN(ROMABLE_REGION) + + .flash.text : ALIGN(0x10) { _stext = .; _instruction_reserved_start = ABSOLUTE(.); @@ -628,7 +748,6 @@ SECTIONS #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) - #endif #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) @@ -658,35 +777,30 @@ SECTIONS * resolved by addr2line in preference to the first symbol in * the flash.text segment. */ - _flash_cache_start = ABSOLUTE(0); + //_flash_cache_start = ABSOLUTE(0); } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - /** - * This dummy section represents the .flash.text section but in default_rodata_seg. + /* This dummy section represents the .flash.text section but in default_rodata_seg. * Thus, it must have its alignment and (at least) its size. */ - .flash_rodata_dummy (NOLOAD): + .flash.rodata_dummy (NOLOAD): { _flash_rodata_dummy_start = ABSOLUTE(.); - /* Start at the same alignment constraint than .flash.text */ - . = ALIGN(ALIGNOF(.flash.text)); - /* Create an empty gap as big as .flash.text section */ - . = . + SIZEOF(.flash.text); - /* Prepare the alignment of the section above. Few bytes (0x20) must be - * added for the mapping header. */ - . = ALIGN(_esp_mmu_block_size) + 0x40; + . += SIZEOF(.flash.text); + . = ALIGN(CACHE_ALIGN); } GROUP_LINK_IN(RODATA_REGION) _image_drom_start = LOADADDR(.flash.rodata); _image_drom_size = LOADADDR(.flash.rodata_end) + SIZEOF(.flash.rodata_end) - _image_drom_start; _image_drom_vaddr = ADDR(.flash.rodata); - .flash.rodata : ALIGN(IROM_SEG_ALIGN) + .flash.rodata : ALIGN(CACHE_ALIGN) { _flash_rodata_start = ABSOLUTE(.); _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ _rodata_start = ABSOLUTE(.); __rodata_region_start = ABSOLUTE(.); + . = ALIGN(4); #include @@ -727,6 +841,7 @@ SECTIONS . = ALIGN(4); } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + #include #include #include #include @@ -755,7 +870,7 @@ SECTIONS .ext_ram.dummy (NOLOAD): { . = ORIGIN(ext_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start); - . = ALIGN (0x10000); + . = ALIGN (CACHE_ALIGN); } GROUP_LINK_IN(ext_ram_seg) /* This section holds .ext_ram.bss data, and will be put in PSRAM */ @@ -774,48 +889,11 @@ SECTIONS #endif /* CONFIG_ESP_SPIRAM */ - /* Marks the end of IRAM code segment */ - .iram0.text_end (NOLOAD) : - { - /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */ - . += 16; - _iram_text_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - .iram0.data : - { - . = ALIGN(4); - _iram_data_start = ABSOLUTE(.); - *(.iram.data) - *(.iram.data*) - _iram_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram0.bss (NOLOAD) : - { - . = ALIGN(4); - _iram_bss_start = ABSOLUTE(.); - *(.iram.bss) - *(.iram.bss*) - _iram_bss_end = ABSOLUTE(.); - . = ALIGN(4); - _iram_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - /* Marks the end of data, bss and possibly rodata */ - .dram0.heap_start (NOLOAD) : - { - . = ALIGN (8); - /* Lowest possible start address for the heap */ - _heap_start = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) #ifdef CONFIG_GEN_ISR_TABLES #include #endif -_heap_sentry = 0x3fceb910; - #include .xtensa.info 0 : { *(.xtensa.info) } diff --git a/soc/espressif/esp32s3/mcuboot.ld b/soc/espressif/esp32s3/mcuboot.ld index b562192a625..01ad3aded33 100644 --- a/soc/espressif/esp32s3/mcuboot.ld +++ b/soc/espressif/esp32s3/mcuboot.ld @@ -1,20 +1,15 @@ /* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - #include #include #include #include +#include "memory.h" + #ifdef CONFIG_XIP #error "Xtensa bootloader cannot use XIP" #endif /* CONFIG_XIP */ @@ -23,52 +18,19 @@ #undef GROUP_DATA_LINK_IN #define GROUP_DATA_LINK_IN(vregion, lregion) > vregion -#define RAMABLE_REGION dram_seg -#define RAMABLE_REGION_1 dram_seg - -#define RODATA_REGION dram_seg -#define ROMABLE_REGION dram_seg - -#define IRAM_REGION iram_seg -#define FLASH_CODE_REGION iram_seg - -#define IROM_SEG_ALIGN 16 - -/** Simplified memory map for the bootloader. - * Make sure the bootloader can load into main memory without overwriting itself. - * - * ESP32-S3 ROM static data usage is as follows: - * - 0x3fcd7e00 - 0x3fce9704: Shared buffers, used in UART/USB/SPI download mode only - * - 0x3fce9710 - 0x3fceb710: PRO CPU stack, can be reclaimed as heap after RTOS startup - * - 0x3fceb710 - 0x3fced710: APP CPU stack, can be reclaimed as heap after RTOS startup - * - 0x3fced710 - 0x3fcf0000: ROM .bss and .data (not easily reclaimable) - * - * The 2nd stage bootloader can take space up to the end of ROM shared - * buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700). - */ -/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */ -iram_dram_offset = 0x6f0000; +/* Aliases for zephyr scripts */ +#define RAMABLE_REGION dram_seg +#define RODATA_REGION dram_seg +#define ROMABLE_REGION dram_seg -bootloader_usable_dram_end = 0x3fce9700; - -bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */ -bootloader_dram_seg_len = 0x6600; -bootloader_iram_loader_seg_len = 0x3000; -bootloader_iram_seg_len = 0x9000; - -/* Start of the lower region is determined by region size and the end of the higher region */ -bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead; -/* bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len; */ -/* We move the dram start to 0x3FCA0000 */ -bootloader_dram_seg_start = 0x3FCA0000; -bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset; -bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len; +_bootloader_dram_seg_end = BOOTLOADER_DRAM_SEG_END; +_bootloader_iram_loader_seg_start = BOOTLOADER_IRAM_LOADER_SEG_START; MEMORY { - iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len - iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len - dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len + iram_seg (RWX) : org = BOOTLOADER_IRAM_SEG_START, len = BOOTLOADER_IRAM_SEG_LEN + iram_loader_seg (RWX) : org = BOOTLOADER_IRAM_LOADER_SEG_START, len = BOOTLOADER_IRAM_LOADER_SEG_LEN + dram_seg (RW) : org = BOOTLOADER_DRAM_SEG_START, len = BOOTLOADER_DRAM_SEG_LEN #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -80,100 +42,64 @@ ENTRY(CONFIG_KERNEL_ENTRY) SECTIONS { - - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(0x10)) + .iram0.loader_text : { - __rodata_region_start = ABSOLUTE(.); + _loader_text_start = ABSOLUTE(.); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - . = ALIGN(4); - #include + *libarch__xtensa__core.a:xtensa_asm2_util.*(.literal .text .literal.* .text.*) + *liblib__libc__common.a:abort.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libarch__common.a:dynamic_isr.*(.literal .text .literal.* .text.*) + *libarch__common.a:sw_isr_common.*(.literal .text .literal.* .text.*) - . = ALIGN(4); - *(.rodata) - *(.rodata.*) + *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*) - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; + *libzephyr.a:heap.*(.literal .text .literal.* .text.*) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); - __rodata_region_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - *(.rodata_wlog) - *(.rodata_wlog*) - _thread_local_end = ABSOLUTE(.); - /* _rodata_reserved_end = ABSOLUTE(.); */ - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + *libkernel.a:kheap.*(.literal .text .literal.* .text.*) + *libkernel.a:mempool.*(.literal .text .literal.* .text.*) + *libkernel.a:device.*(.literal .text .literal.* .text.*) + *libkernel.a:timeout.*(.literal .text .literal.* .text.*) - #include - #include - #include - #include + *(.literal.bootloader_mmap .text.bootloader_mmap) + *(.literal.bootloader_munmap .text.bootloader_munmap) - .dram0.data : - { - __data_start = ABSOLUTE(.); + *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.*) - *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*) + *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_system_abort .text.esp_system_abort) - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + *(.fini.literal) + *(.fini) + *(.gnu.version) - #include - #include - #include - #include - #include - #include + /* CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; - .dram0.end : - { - . = ALIGN(4); - #include + _text_end = ABSOLUTE(.); + _etext = .; . = ALIGN(4); - _end = ABSOLUTE(.); - _heap_sentry = .; - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + _loader_text_end = ABSOLUTE(.); + _iram_text_end = ABSOLUTE(.); + _iram_end = ABSOLUTE(.); + } > iram_loader_seg - /* Send .iram0 code to iram */ .iram0.vectors : ALIGN(4) { /* Vectors go to IRAM */ @@ -209,78 +135,117 @@ SECTIONS *(.entry.text) *(.init.literal) *(.init) + . = ALIGN (4); _init_end = ABSOLUTE(.); /* This goes here, not at top of linker script, so addr2line finds it last, * and uses it in preference to the first symbol in IRAM */ - _iram_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + _iram_start = ABSOLUTE(.); + } > iram_seg - .iram_loader.text : + .iram0.text : { - . = ALIGN (16); - _loader_text_start = ABSOLUTE(.); - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ - *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_flash_config_esp32s3.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_init_common.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libzephyr.a:bootloader_efuse_esp32s3.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) - *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) - *libzephyr.a:app_cpu_start.*(.literal .text .literal.* .text.*) - *esp_mcuboot.*(.literal .text .literal.* .text.*) - *esp_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + . = ALIGN(4); - *(.fini.literal) - *(.fini) - *(.gnu.version) - _loader_text_end = ABSOLUTE(.); - } > iram_loader_seg + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + + *(.literal .text .literal.* .text.*) + . = ALIGN(4); + + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + . = ALIGN(4); + } > iram_seg - SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) + .dram0.data : ALIGN(16) { - /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); + . = ALIGN(4); + __data_start = ABSOLUTE(.); - *(.iram1 .iram1.*) - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + #include - . = ALIGN(16); - _iram_text_end = ABSOLUTE(.); */ - _iram_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + . = ALIGN(4); + #include + . = ALIGN(4); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + *(.rodata) + *(.rodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + *(.rodata_wlog) + *(.rodata_wlog*) + _thread_local_end = ABSOLUTE(.); + . = ALIGN(4); + } > dram_seg + + #include + #include + #include + #include + + #include + #include + #include + #include + #include + #include + + .noinit (NOLOAD): + { + . = ALIGN(8); + *(.noinit) + *(.noinit.*) + . = ALIGN(8) ; + } > dram_seg /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + .bss (NOLOAD): { . = ALIGN (8); _bss_start = ABSOLUTE(.); /* required by bluetooth library */ @@ -304,49 +269,10 @@ SECTIONS __bss_end = ABSOLUTE(.); _bss_end = ABSOLUTE(.); _end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) + } > dram_seg ASSERT(((__bss_end - ORIGIN(dram_seg)) <= LENGTH(dram_seg)), "DRAM segment data does not fit.") - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN(8); - *(.noinit) - *(.noinit.*) - . = ALIGN(8) ; - } GROUP_LINK_IN(RAMABLE_REGION) - - .flash.text : - { - _stext = .; - _text_start = ABSOLUTE(.); - - *(.literal .text .literal.* .text.*) - . = ALIGN(4); - - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - - /* CPU will try to prefetch up to 16 bytes of - * of instructions. This means that any configuration (e.g. MMU, PMS) must allow - * safe access to up to 16 bytes after the last real instruction, add - * dummy bytes to ensure this - */ - . += 16; - - _text_end = ABSOLUTE(.); - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - #include .xtensa.info 0 : { *(.xtensa.info) } @@ -386,8 +312,4 @@ SECTIONS #ifdef CONFIG_GEN_ISR_TABLES #include #endif - } - -ASSERT(((_iram_end - ORIGIN(IRAM_REGION)) <= LENGTH(IRAM_REGION)), - "IRAM0 segment data does not fit.") diff --git a/soc/espressif/esp32s3/memory.h b/soc/espressif/esp32s3/memory.h new file mode 100644 index 00000000000..5675acccead --- /dev/null +++ b/soc/espressif/esp32s3/memory.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/* SRAM0 (64k), SRAM1 (416k), SRAM2 (64k) memories + * Ibus and Dbus address space + */ +#define SRAM0_IRAM_START 0x40370000 +#define SRAM0_SIZE 0x8000 +#define SRAM1_DRAM_START 0x3fc88000 +/* IRAM equivalent address where DRAM actually start */ +#define SRAM1_IRAM_START (SRAM0_IRAM_START + SRAM0_SIZE) +#define SRAM2_DRAM_START 0x3fcf0000 +#define SRAM2_SIZE 0x10000 + +/** Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32-S3 ROM static data usage is as follows: + * - 0x3fcd7e00 - 0x3fce9704: Shared buffers, used in UART/USB/SPI download mode only + * - 0x3fce9710 - 0x3fceb710: PRO CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fceb710 - 0x3fced710: APP CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fced710 - 0x3fcf0000: ROM .bss and .data (not easily reclaimable) + * + * The 2nd stage bootloader can take space up to the end of ROM shared + * buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700). + */ + +/* The offset between Dbus and Ibus. + * Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. + */ +#define IRAM_DRAM_OFFSET 0x6f0000 +#define DRAM_BUFFERS_START 0x3fcd7e00 +#define DRAM_PROCPU_STACK_START 0x3fce9710 +#define DRAM_STACK_START DRAM_PROCPU_STACK_START +#define DRAM_APPCPU_STACK_START 0x3fceb710 +#define DRAM_ROM_BSS_DATA_START 0x3fcf0000 + +/* Base address used for calculating memory layout + * counted from Dbus backwards and back to the Ibus + */ +#define BOOTLOADER_USABLE_DRAM_END DRAM_BUFFERS_START + +/* For safety margin between bootloader data section and startup stacks */ +#define BOOTLOADER_STACK_OVERHEAD 0x0 +#define BOOTLOADER_DRAM_SEG_LEN 0x6600 +#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x2c00 +#define BOOTLOADER_IRAM_SEG_LEN 0x9000 + +/* Start of the lower region is determined by region size and the end of the higher region */ +#define BOOTLOADER_DRAM_SEG_END (BOOTLOADER_USABLE_DRAM_END - BOOTLOADER_STACK_OVERHEAD) +#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_DRAM_SEG_END - BOOTLOADER_DRAM_SEG_LEN) +#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_DRAM_SEG_START - \ + BOOTLOADER_IRAM_LOADER_SEG_LEN + IRAM_DRAM_OFFSET) +#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN) + +/* Flash */ +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x800000 +#endif + +/* Cached memory */ +#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE +#define IROM_SEG_ORG 0x42000000 +#define IROM_SEG_LEN FLASH_SIZE +#define DROM_SEG_ORG 0x3c000000 +#define DROM_SEG_LEN FLASH_SIZE + +/* AMP */ +#ifdef CONFIG_SOC_ENABLE_APPCPU +#define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM +#define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM +#else +#define APPCPU_IRAM_SIZE 0 +#define APPCPU_DRAM_SIZE 0 +#endif diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c index 54af1c4d20b..c63d61474dd 100644 --- a/soc/espressif/esp32s3/soc.c +++ b/soc/espressif/esp32s3/soc.c @@ -143,12 +143,7 @@ void IRAM_ATTR __esp_platform_start(void) */ __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); -#ifdef CONFIG_MCUBOOT - /* MCUboot early initialisation. */ - if (bootloader_init()) { - abort(); - } -#else +#ifndef CONFIG_MCUBOOT /* Configure the mode of instruction cache : cache size, cache line size. */ esp_config_instruction_cache_mode(); @@ -189,6 +184,7 @@ void IRAM_ATTR __esp_platform_start(void) (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); #endif /* CONFIG_ESP_SPIRAM */ + /* Apply SoC patches */ esp_errata(); @@ -216,7 +212,7 @@ void IRAM_ATTR __esp_platform_start(void) #if CONFIG_SOC_FLASH_ESP32 spi_flash_guard_set(&g_flash_guard_default_ops); #endif -#endif /* CONFIG_MCUBOOT */ +#endif /* !CONFIG_MCUBOOT */ esp_intr_initialize(); From 323f811c7cc7719e0821389a1eb92db7e6238d78 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Wed, 31 Jan 2024 20:24:46 +0100 Subject: [PATCH 1997/2402] soc: espressif: esp32s2: simple boot support Add simplistic booting method which allows to run applications without the 2nd stage bootloader. - introduce memory layout header file - update and optimize default and mcuboot linker scripts - remove building multiple binaries during the application build Signed-off-by: Marek Matej --- soc/espressif/esp32s2/CMakeLists.txt | 75 +- soc/espressif/esp32s2/default.ld | 1033 +++++++++++++++++--------- soc/espressif/esp32s2/mcuboot.ld | 379 ++++------ soc/espressif/esp32s2/memory.h | 65 ++ soc/espressif/esp32s2/soc.c | 11 +- 5 files changed, 955 insertions(+), 608 deletions(-) create mode 100644 soc/espressif/esp32s2/memory.h diff --git a/soc/espressif/esp32s2/CMakeLists.txt b/soc/espressif/esp32s2/CMakeLists.txt index e93e5711089..77610b2fb0c 100644 --- a/soc/espressif/esp32s2/CMakeLists.txt +++ b/soc/espressif/esp32s2/CMakeLists.txt @@ -13,57 +13,60 @@ zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) zephyr_library_sources_ifdef(CONFIG_PM power.c) zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) -# get code-partition slot0 address -dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") -dt_reg_addr(img_0_off PATH ${dts_partition_path}) - -# get code-partition boot address -dt_nodelabel(dts_partition_path NODELABEL "boot_partition") -dt_reg_addr(boot_off PATH ${dts_partition_path}) - # get flash size to use in esptool as string math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") -if(CONFIG_BOOTLOADER_ESP_IDF) - - set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") +if(NOT CONFIG_BOOTLOADER_MCUBOOT) - if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") - endif() - - if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") - endif() - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + if(CONFIG_BUILD_OUTPUT_BIN) + # make ESP ROM loader compatible image + message("ESP-IDF path: ${ESP_IDF_PATH}") -endif() + set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py) + message("esptool path: ${ESPTOOL_PY}") -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + set(ELF2IMAGE_ARG "") + if(NOT CONFIG_MCUBOOT) + set(ELF2IMAGE_ARG "--ram-only-header") + endif() - if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py - ARGS --chip esp32s2 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY} + ARGS --chip esp32s2 elf2image ${ELF2IMAGE_ARG} + --flash_mode dio --flash_freq 40m + --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) endif() - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - endif() -board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") +# Get code-partition boot address +dt_nodelabel(dts_partition_path NODELABEL "boot_partition") +dt_reg_addr(boot_off PATH ${dts_partition_path}) + +# Get code-partition slot0 address +dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") +dt_reg_addr(img_0_off PATH ${dts_partition_path}) + +if(CONFIG_ESP_SIMPLE_BOOT) + board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}") +else() + board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") +endif() -board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") +if(CONFIG_MCUBOOT) + # search from cross references between bootloader sections + message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py") + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py + ARGS + --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr + --elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf + find-refs --from-section=.iram0.iram_loader --to-section=.iram0.text + --exit-code) +endif() if(CONFIG_MCUBOOT) set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") diff --git a/soc/espressif/esp32s2/default.ld b/soc/espressif/esp32s2/default.ld index 6c335aafa1d..89fb139f19c 100644 --- a/soc/espressif/esp32s2/default.ld +++ b/soc/espressif/esp32s2/default.ld @@ -1,92 +1,102 @@ /* - * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2016 Cadence Design Systems, Inc. + * Copyright (c) 2017 Intel Corporation + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the esp32s2 platform. - */ - #include #include #include #include -#define RAM_IRAM_START 0x40020000 -#define RAM_DRAM_START 0x3ffb0000 - -/* DATA_RAM_END is equivalent 2nd stage bootloader iram_loader_seg - start address (that should not be overlapped) */ -#define DATA_RAM_END 0x3FFE0000 - -#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ - + CONFIG_ESP32S2_DATA_CACHE_SIZE) - -#define DRAM_ORG (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ - + CONFIG_ESP32S2_DATA_CACHE_SIZE) - -#define I_D_RAM_SIZE DATA_RAM_END - DRAM_ORG - -#define RAMABLE_REGION dram0_0_seg -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define FLASH_CODE_REGION irom0_0_seg +#include "memory.h" -#define ROMABLE_REGION ROM - -#ifdef CONFIG_FLASH_SIZE -#define FLASH_SIZE CONFIG_FLASH_SIZE +/* The "user_iram_end" represents the 2nd stage bootloader + * "iram_loader_seg" start address (that should not be overlapped). + * If no bootloader is used, we can extend it to gain more user ram. + */ +#ifdef CONFIG_ESP_SIMPLE_BOOT +user_iram_end = (DRAM_BUFFERS_START + IRAM_DRAM_OFFSET); #else -#define FLASH_SIZE 0x400000 +user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START; #endif -#ifdef CONFIG_BOOTLOADER_ESP_IDF -#define IROM_SEG_ORG 0x40080020 -#define IROM_SEG_LEN (FLASH_SIZE-0x20) -#define IROM_SEG_ALIGN 0x4 -#else -#define IROM_SEG_ORG 0x40080000 -#define IROM_SEG_LEN FLASH_SIZE -#define IROM_SEG_ALIGN 0x10000 -#endif +/* User available SRAM memory segments */ +user_iram_seg_org = (SRAM_IRAM_START + SRAM_CACHE_SIZE); +user_dram_seg_org = (SRAM_DRAM_START + SRAM_CACHE_SIZE); +user_dram_end = (user_iram_end - IRAM_DRAM_OFFSET); +user_idram_size = (user_dram_end - user_dram_seg_org); +user_iram_seg_len = user_idram_size; +user_dram_seg_len = user_idram_size; + +/* Aliases */ +#define ROTEXT_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define RAMABLE_REGION dram0_0_seg +#define ROMABLE_REGION FLASH /* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. * Executing directly from LMA is not possible. */ #undef GROUP_ROM_LINK_IN #define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion +/* TODO */ +#define RESERVE_RTC_MEM 0 + MEMORY { - mcuboot_hdr (RX): org = 0x0, len = 0x20 - metadata (RX): org = 0x20, len = 0x20 - ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 - iram0_0_seg(RX): org = IRAM_ORG, len = I_D_RAM_SIZE +#ifdef CONFIG_BOOTLOADER_MCUBOOT + mcuboot_hdr (R): org = 0x0, len = 0x20 + metadata (R): org = 0x20, len = 0x20 + FLASH (R): org = 0x40, len = FLASH_SIZE +#else + /* Make safety margin in the FLASH memory size so the + * (esp_img_header + (n*esp_seg_headers)) would fit */ + FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100 +#endif + + iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len + dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len + irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - dram0_0_seg(RW): org = DRAM_ORG, len = I_D_RAM_SIZE - drom0_0_seg(R): org = 0x3f000040, len = FLASH_SIZE - 0x40 + drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN + + rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000 - RESERVE_RTC_MEM + rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 + /* RTC fast memory (same block as above, rtc_iram_seg), viewed from data bus */ + rtc_data_seg(RW) : org = 0x3ff9e000, len = 0x2000 - RESERVE_RTC_MEM + /* We reduced the size of rtc_data_seg and rtc_iram_seg by RESERVE_RTC_MEM value. + * It reserves the amount of RTC fast memory that we use for this memory segment. + * This segment is intended for keeping: + * - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). + * - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on). + * The aim of this is to keep data that will not be moved around and have a fixed address. + */ + rtc_reserved_seg(RW) : org = 0x3ff9e000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM +#ifdef CONFIG_ESP_SPIRAM + ext_data_ram_seg(RW): org = 0x3f800000, len = CONFIG_ESP_SPIRAM_SIZE /* OR 0x780000 */ +#endif /* CONFIG_ESP_SPIRAM */ - rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000 - rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 -#if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RW): org = 0x3f800000, len = CONFIG_ESP_SPIRAM_SIZE -#endif #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 #endif } -/* Default entry point: */ +/* Default entry point: */ ENTRY(CONFIG_KERNEL_ENTRY) _rom_store_table = 0; -_heap_sentry = 0x3fffe710; +/* Used as a pointer to the heap end */ +_heap_sentry = DRAM_BUFFERS_START; SECTIONS { + _iram_dram_offset = IRAM_DRAM_OFFSET; + +#ifdef CONFIG_BOOTLOADER_MCUBOOT /* Reserve space for MCUboot header in the binary */ .mcuboot_header : { @@ -97,109 +107,163 @@ SECTIONS } > mcuboot_hdr .metadata : { - /* Magic byte for load header */ + /* 0. Magic byte for load header */ LONG(0xace637d3) - /* Application entry point address */ + /* 1. Application entry point address */ KEEP(*(.entry_addr)) - /* IRAM metadata: - * - Destination address (VMA) for IRAM region - * - Flash offset (LMA) for start of IRAM region - * - Size of IRAM region + /* IRAM load: + * 2. Destination address (VMA) for IRAM region + * 3. Flash offset (LMA) for start of IRAM region + * 4. Size of IRAM region */ LONG(ADDR(.iram0.vectors)) LONG(LOADADDR(.iram0.vectors)) LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors)) - /* DRAM metadata: - * - Destination address (VMA) for DRAM region - * - Flash offset (LMA) for start of DRAM region - * - Size of DRAM region + /* DRAM load: + * 5. Destination address (VMA) for DRAM region + * 6. Flash offset (LMA) for start of DRAM region + * 7. Size of DRAM region */ LONG(ADDR(.dram0.data)) LONG(LOADADDR(.dram0.data)) - LONG(LOADADDR(.dummy.dram.data) + SIZEOF(.dummy.dram.data) - LOADADDR(.dram0.data)) + LONG(LOADADDR(.dram0.data_end) - LOADADDR(.dram0.data)) } > metadata +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ +/* Virtual non-loadable sections */ #include - _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); - _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; - _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); - - /* NOTE: .rodata section should be the first section in the linker script and no - * other section should appear before .rodata section. This is the requirement - * to align ROM section to 64K page offset. - * Adding .rodata as first section helps to reduce size of generated binary by - * few kBs. + + /* --- START OF RTC --- */ + + /* RTC fast memory holds RTC wake stub code, + * including from any source file named rtc_wake_stub*.c */ - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(4)) + .rtc.text : { - _rodata_reserved_start = ABSOLUTE(.); - __rodata_region_start = ABSOLUTE(.); - _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ - + _rtc_text_start = ABSOLUTE(.); . = ALIGN(4); - #include - . = ALIGN(4); - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata) - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*) + _rtc_code_start = .; - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; + /* mapping[rtc_text] */ - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); - __rodata_region_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); + *rtc_wake_stub*.*(.literal .text .literal.* .text.*) + _rtc_code_end = .; + + /* possibly align + add 16B for CPU dummy speculative instr. fetch */ + . = ((_rtc_code_end - _rtc_code_start) == 0) ? ALIGN(0) : ALIGN(4) + 16; + + _rtc_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + + /* + * This section is required to skip rtc.text area because rtc_iram_seg and + * rtc_data_seg are reflect the same address space on different buses. + */ + .rtc.dummy : + { + _rtc_dummy_start = ABSOLUTE(.); + _rtc_fast_start = ABSOLUTE(.); + . = SIZEOF(.rtc.text); + _rtc_dummy_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + + /* This section located in RTC FAST Memory area. + * It holds data marked with RTC_FAST_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_fast : + { . = ALIGN(4); - *(.rodata_wlog) - *(.rodata_wlog*) + _rtc_force_fast_start = ABSOLUTE(.); + + /* mapping[rtc_force_fast] */ + + *(.rtc.force_fast .rtc.force_fast.*) + . = ALIGN(4) ; + _rtc_force_fast_end = ABSOLUTE(.); + } > rtc_data_seg + + /* RTC data section holds RTC wake stub + * data/rodata, including from any source file + * named rtc_wake_stub*.c and the data marked with + * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + + /* mapping[rtc_data] */ + + *rtc_wake_stub*.*(.data .rodata .data.* .rodata.*) + _rtc_data_end = ABSOLUTE(.); + } > rtc_data_seg + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.*(.bss .bss.*) + *rtc_wake_stub*.*(COMMON) + + /* mapping[rtc_bss] */ + + _rtc_bss_end = ABSOLUTE(.); + } > rtc_data_seg + + /* This section holds data that should not be initialized at power up + * and will be retained during deep sleep. + * User data marked with RTC_NOINIT_ATTR will be placed + * into this section. See the file "esp_attr.h" for more information. + */ + .rtc_noinit (NOLOAD): + { . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } > rtc_data_seg - #include - #include - #include - #include - #include - #include - #include - #include + /* This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } > rtc_slow_seg - /* Create an explicit section at the end of all the data that shall be mapped into drom. - * This is used to calculate the size of the _image_drom_size variable */ - SECTION_PROLOGUE(_RODATA_SECTION_END,,ALIGN(0x10)) + /** + * This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ + .rtc_reserved (NOLOAD): { - _rodata_reserved_end = ABSOLUTE(.); . = ALIGN(4); - _image_rodata_end = ABSOLUTE(.); - _rodata_reserved_end = ABSOLUTE(.); + _rtc_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. + Because data have adhered to the end of the segment and code is relied on it. + >> put new data here << */ - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + + /* Get size of rtc slow data */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + + /* --- END OF RTC --- */ + + /* --- START OF IRAM --- */ /* Send .iram0 code to iram */ .iram0.vectors : ALIGN(4) @@ -238,92 +302,134 @@ SECTIONS *(.init.literal) *(.init) _init_end = ABSOLUTE(.); - - /* This goes here, not at top of linker script, so addr2line finds it last, - and uses it in preference to the first symbol in IRAM */ } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) .iram0.text : ALIGN(4) { - . = ALIGN(8); /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); *(.iram1 .iram1.*) *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) *libesp32.a:panic.*(.literal .text .literal.* .text.*) *librtc.a:(.literal .text .literal.* .text.*) *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) *libkernel.a:(.literal .text .literal.* .text.*) - *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) - *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_packaged.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) - *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) - *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) - *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) - *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_minimal.*(.literal .literal.* .text .text.*) *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_mmu_map.*(.literal .literal.* .text .text.*) + *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) + *libdrivers__interrupt_controller.a:(.literal .literal.* .text .text.*) *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) - *libc.a:*(.literal .text .literal.* .text.*) - *libphy.a:( .phyiram .phyiram.*) + *liblib__libc__picolibc.a:string.*(.literal .text .literal.* .text.*) + *libphy.a:(.phyiram .phyiram.*) *libgcov.a:(.literal .text .literal.* .text.*) - *libzephyr.a:cpu.*(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) - *libzephyr.a:cpu.*(.literal.esp_cpu_reset .text.esp_cpu_reset) - *libzephyr.a:cpu.*(.literal.esp_cpu_stall .text.esp_cpu_stall) - *libzephyr.a:cpu.*(.literal.esp_cpu_unstall .text.esp_cpu_unstall) - *libzephyr.a:cpu.*(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) - *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) - *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) - *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) - *libzephyr.a:periph_ctrl.*(.literal.periph_module_reset .text.periph_module_reset) - *libzephyr.a:periph_ctrl.*(.literal.wifi_module_disable .text.wifi_module_disable) - *libzephyr.a:periph_ctrl.*(.literal.wifi_module_enable .text.wifi_module_enable) - *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_wdt.*(.literal .literal.* .text .text.*) - *libzephyr.a:sar_periph_ctrl.*(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) - *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_system_chip.*(.literal.esp_system_abort .text.esp_system_abort) - *libzephyr.a:cache_hal.*(.literal .literal.* .text .text.*) - *libzephyr.a:i2c_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:ledc_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:mmu_hal.*(.literal .literal.* .text .text.*) - *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*) - *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:spi_flash_init.*(.literal .literal.* .text .text.*) - *libzephyr.a:spi_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:spi_slave_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:systimer_hal.*(.literal .literal.* .text .text.*) - *libzephyr.a:wdt_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) - *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + + /* [mapping:esp_psram] */ + *libzephyr.a:mmu_psram_flash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_psram_impl_quad.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_psram_impl_octal.*(.literal .literal.* .text .text.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:i2c_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.literal .text .literal.* .text.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.literal .literal.* .text .text.*) + + /* [mapping:log] */ + *(.literal.esp_log_write .text.esp_log_write) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_log_impl_lock .text.esp_log_impl_lock) + *(.literal.esp_log_impl_lock_timeout .text.esp_log_impl_lock_timeout) + *(.literal.esp_log_impl_unlock .text.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hpm_enable.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_oct_flash_init*(.literal .literal.* .text .text.*) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *(.literal.esp_system_abort .text.esp_system_abort) + + /* [mapping:esp_hw_support] */ + *(.literal.esp_cpu_stall .text.esp_cpu_stall) + *(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *(.literal.esp_cpu_reset .text.esp_cpu_reset) + *(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *(.literal.rtc_vddsdio_get_config .text.rtc_vddsdio_get_config) + *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*) + *libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*) + *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + + /* [mapping:soc_pm] */ + *(.literal.GPIO_HOLD_MASK .text.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) #if defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) + *libnet80211.a:(.wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:(.wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) + *libcoexist.a:(.wifi_slp_iram .wifi_slp_iram.*) + + /* [mapping:esp_wifi] */ + *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper) + *(.literal.wifi_clock_disable_wrapper .text.wifi_clock_disable_wrapper) + + /* [mapping:esp_phy] */ + *(.literal.esp_phy_enable .text.esp_phy_enable) + *(.literal.esp_phy_disable .text.esp_phy_disable) + *(.literal.esp_wifi_bt_power_domain_off .text.esp_wifi_bt_power_domain_off) #endif #if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) @@ -333,83 +439,113 @@ SECTIONS /* align + add 16B for CPU dummy speculative instr. fetch */ . = ALIGN(4) + 16; - _iram_text = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - .dram0.dummy (NOLOAD): +#ifdef CONFIG_ESP_SIMPLE_BOOT + .loader.text : { - /** - * This section is required to skip .iram0.text area because iram0_0_seg and - * dram0_0_seg reflect the same address space on different buses. - */ - . = ALIGN (8); - . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; - } GROUP_LINK_IN(RAMABLE_REGION) + . = ALIGN(4); + _loader_text_start = ABSOLUTE(.); + *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_esp32s2.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_wdt.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash_config_esp32s2.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_common.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_mem.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + *libzephyr.a:bootloader_efuse.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) + + *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_flash_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_flash_spi_init.*(.literal .text .literal.* .text.*) + + *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) + *libzephyr.a:efuse_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) + *libzephyr.a:mpu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu_region_protect.*(.literal .text .literal.* .text.*) + + *(.fini.literal) + *(.fini) + + . = ALIGN(4); + _loader_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ - /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + .iram0.text_end (NOLOAD) : { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - __bss_start = ABSOLUTE(.); + . = ALIGN(16); + _iram_text_end_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - __bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) -#if defined(CONFIG_ESP_SPIRAM) - /* This section holds .ext_ram.bss data, and will be put in PSRAM */ - .ext_ram.bss (NOLOAD) : + .iram0.bss (NOLOAD) : { - _ext_ram_data_start = ABSOLUTE(.); - _ext_ram_bss_start = ABSOLUTE(.); - *(.ext_ram.bss*) + . = ALIGN(16); + _iram_bss_start = ABSOLUTE(.); + *(.iram.bss) + *(.iram.bss.*) + _iram_bss_end = ABSOLUTE(.); + . = ALIGN(4); - _ext_ram_bss_end = ABSOLUTE(.); - } > ext_ram_seg + _iram_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) - .ext_ram_noinit (NOLOAD) : - { -#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) - *libdrivers__wifi.a:(.noinit .noinit.*) - *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) - *libsubsys__net__lib__config.a:(.noinit .noinit.*) - *libsubsys__net__ip.a:(.noinit .noinit.*) - *libsubsys__net.a:(.noinit .noinit.*) -#endif - _spiram_heap_start = ABSOLUTE(.); - . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; + /* --- END OF IRAM --- */ - _ext_ram_data_end = ABSOLUTE(.); - } > ext_ram_seg -#endif + /* --- START OF DRAM --- */ - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) + .dram0.dummy (NOLOAD): { - . = ALIGN(8); - *(.noinit) - *(.noinit.*) - . = ALIGN(8); + /* This section is required to skip .iram0.text area because iram0_0_seg and + * dram0_0_seg reflect the same address space on different buses. + */ + . = ORIGIN(dram0_0_seg) + MAX(_iram_end, user_iram_seg_org) - user_iram_seg_org; + . = ALIGN(4) + 16; } GROUP_LINK_IN(RAMABLE_REGION) .dram0.data : { . = ALIGN (8); + _data_start = ABSOLUTE(.); __data_start = ABSOLUTE(.); + + /* bluetooth library requires this symbol to be defined */ + _btdm_data_start = ABSOLUTE(.); + *libbtdm_app.a:(.data .data.*) + . = ALIGN (4); + _btdm_data_end = ABSOLUTE(.); + *(.data) *(.data.*) *(.gnu.linkonce.d.*) @@ -420,58 +556,155 @@ SECTIONS *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) + *(.srodata) + *(.srodata.*) /* rodata for panic handler(libarch__xtensa__core.a) and all * dependent functions should be placed in DRAM to avoid issue * when flash cache is disabled */ *libarch__xtensa__core.a:(.rodata .rodata.*) *libkernel.a:fatal.*(.rodata .rodata.*) *libkernel.a:init.*(.rodata .rodata.*) - *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete.*(.rodata .rodata.*) *libzephyr.a:log_core.*(.rodata .rodata.*) *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) *libzephyr.a:log_output.*(.rodata .rodata.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:log_minimal.*(.rodata .rodata.*) *libzephyr.a:loader.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) - *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) - *libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:rtc_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:systimer.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:esp_cache.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:esp_err.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:cache_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_slave_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:systimer_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libzephyr.a:esp_mmu_map.*(.rodata .rodata.*) + *libdrivers__interrupt_controller.a:(.rodata .rodata.*) + + /* [mapping:esp_psram] */ + *libzephyr.a:mmu_psram_flash.*(.rodata .rodata.*) + *libzephyr.a:esp_psram_impl_octal.*(.rodata .rodata.*) + *libzephyr.a:esp_psram_impl_quad.*(.rodata .rodata.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:cache_hal.*(.rodata .rodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.rodata .rodata.*) + + /* [mapping:log] */ + *(.rodata.esp_log_write) + *(.rodata.esp_log_timestamp) + *(.rodata.esp_log_early_timestamp) + *(.rodata.esp_log_impl_lock) + *(.rodata.esp_log_impl_lock_timeout) + *(.rodata.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hpm_enable.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_oct_flash_init.*(.rodata .rodata.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.rodata .rodata.*) + + /* [mapping:esp_hw_support] */ + *(.rodata.esp_cpu_stall) + *(.rodata.esp_cpu_unstall) + *(.rodata.esp_cpu_reset) + *(.rodata.esp_cpu_wait_for_intr) + *(.rodata.esp_cpu_compare_and_set) + *(.rodata.esp_gpio_reserve_pins) + *(.rodata.esp_gpio_is_pin_reserved) + *(.rodata.rtc_vddsdio_get_config) + *(.rodata.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk_init.*(.rodata .rodata.*) + *libzephyr.a:systimer.*(.rodata .rodata.*) + *libzephyr.a:mspi_timing_config.*(.rodata .rodata.*) + *libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.*) + *(.rodata.sar_periph_ctrl_power_enable) + *libzephyr.a:periph_ctrl.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + /* [mapping:soc_pm] */ + *(.rodata.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_wdt.*(.rodata .rodata.*) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.rodata .rodata.*) + *(.rodata.esp_system_abort) + +#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) + /* [mapping:esp_wifi] */ + *(.rodata.wifi_clock_enable_wrapper) + *(.rodata.wifi_clock_disable_wrapper) + + /* [mapping:esp_phy] */ + *(.rodata.esp_phy_enable) + *(.rodata.esp_phy_disable) + *(.rodata.esp_wifi_bt_power_domain_off) +#endif + + . = ALIGN(4); KEEP(*(.jcr)) *(.dram1 .dram1.*) + . = ALIGN(4); + #include + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - #include +#ifdef CONFIG_ESP_SIMPLE_BOOT + .loader.data : + { + . = ALIGN(4); + _loader_data_start = ABSOLUTE(.); + *libzephyr.a:bootloader_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_esp32s3.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_clock_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_wdt.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_flash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_flash_config_esp32s2.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_efuse.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_random_esp32s2.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:cpu_util.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:cpu_region_protect.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:spi_flash_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_flash_api.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_flash_spi_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:efuse_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + . = ALIGN(4); + _loader_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +#endif /* !CONFIG_BOOTLOADER_MCUBOOT */ + #include #include #include @@ -484,110 +717,218 @@ SECTIONS #include #pragma pop_macro("GROUP_ROM_LINK_IN") - .dummy.dram.data : + .dram0.data_end : { . = ALIGN(4); - #include - . = ALIGN(4); - _end = ABSOLUTE(.); - __data_end = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + _dram_data_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - .iram0.text_end (NOLOAD) : + /* .bss */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + __bss_start = ABSOLUTE(.); + _bss_start = ABSOLUTE(.); + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + __bss_end = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + +#ifdef CONFIG_ESP_SPIRAM + /* This section holds .ext_ram.bss data, and will be put in PSRAM */ + .ext_ram.bss (NOLOAD): { + _ext_ram_data_start = ABSOLUTE(.); + _ext_ram_bss_start = ABSOLUTE(.); + *(.ext_ram.bss*) . = ALIGN(4); - _iram_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) + _ext_ram_bss_end = ABSOLUTE(.); + } > ext_data_ram_seg + + .ext_ram_noinit (NOLOAD) : + { +#ifdef CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM + *libdrivers__wifi.a:(.noinit .noinit.*) + *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) + *libsubsys__net__lib__config.a:(.noinit .noinit.*) + *libsubsys__net__ip.a:(.noinit .noinit.*) + *libsubsys__net.a:(.noinit .noinit.*) +#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */ + + _spiram_heap_start = ABSOLUTE(.); + . += CONFIG_ESP_SPIRAM_HEAP_SIZE; + + _ext_ram_data_end = ABSOLUTE(.); + } > ext_data_ram_seg +#endif /* CONFIG_ESP_SPIRAM */ + + .dram0.noinit (NOLOAD) : + { + . = ALIGN(8); + *(.noinit) + *(.noinit.*) + . = ALIGN(8); + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Provide total SRAM usage, including IRAM and DRAM */ + _image_ram_start = _iram_start - IRAM_DRAM_OFFSET; + #include + + ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + + /* --- END OF DRAM --- */ + + /* --- START OF .rodata --- */ + + _image_drom_start = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata_end) + SIZEOF(.flash.rodata_end) - _image_drom_start; + _image_drom_vaddr = ADDR(.flash.rodata); + + /* Align next section to 64k to allow mapping */ + .flash.rodata_dummy (NOLOAD) : + { + . = ALIGN(CACHE_ALIGN); + } GROUP_LINK_IN(ROMABLE_REGION) + + .flash.rodata : ALIGN(16) + { + _flash_rodata_start = ABSOLUTE(.); + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ + _rodata_start = ABSOLUTE(.); + __rodata_region_start = ABSOLUTE(.); + . = ALIGN(4); + #include + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + *(.rodata_wlog) + *(.rodata_wlog*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + .flash.rodata_end : + { + . = ALIGN(CACHE_ALIGN); + _image_rodata_end = ABSOLUTE(.); + _rodata_region_end = ABSOLUTE(.); + _rodata_reserved_end = ABSOLUTE(.); + + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + /* --- END OF .rodata --- */ + + /* --- START OF .flash.text --- */ _image_irom_start = LOADADDR(.flash.text); _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; _image_irom_vaddr = ADDR(.flash.text); - .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN) + .flash.text_dummy (NOLOAD): { - . = ALIGN(4); - . = SIZEOF(_RODATA_SECTION_NAME); - } GROUP_LINK_IN(FLASH_CODE_REGION) + . = ALIGN(CACHE_ALIGN+CACHE_ALIGN); + } GROUP_LINK_IN(ROMABLE_REGION) - .flash.text : ALIGN(IROM_SEG_ALIGN) + .flash.text : ALIGN(4) { - . = ALIGN(8); _stext = .; - _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ + _instruction_reserved_start = ABSOLUTE(.); _text_start = ABSOLUTE(.); #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) + #endif - . = ALIGN(8); #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) #endif - . = ALIGN(8); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) *(.literal .text .literal.* .text.*) - . = ALIGN(8); + + /* CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + _text_end = ABSOLUTE(.); - _instruction_reserved_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ _etext = .; /* Similar to _iram_start, this symbol goes here so it is - resolved by addr2line in preference to the first symbol in - the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - - /* RTC fast memory holds RTC wake stub code, - including from any source file named rtc_wake_stub*.c - */ - .rtc.text : - { - . = ALIGN(4); - *(.rtc.literal .rtc.text) - *rtc_wake_stub*.o(.literal .text .literal.* .text.*) - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - - /* RTC slow memory holds RTC wake stub - data/rodata, including from any source file - named rtc_wake_stub*.c - */ - .rtc.data : - { - _rtc_data_start = ABSOLUTE(.); - *(.rtc.data) - *(.rtc.rodata) - *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) - _rtc_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.o(.bss .bss.*) - *rtc_wake_stub*.o(COMMON) - _rtc_bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(rtc_slow_seg) - - /* This section located in RTC SLOW Memory area. - It holds data marked with RTC_SLOW_ATTR attribute. - See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : - { - . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } > rtc_slow_seg + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(ROTEXT_REGION, ROMABLE_REGION) - /* Get size of rtc slow data */ - _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + /* --- END OF .flash.text --- */ #ifdef CONFIG_GEN_ISR_TABLES #include @@ -636,7 +977,7 @@ ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), "IRAM0 segment data does not fit.") -#if defined(CONFIG_ESP_SPIRAM) +#ifdef CONFIG_ESP_SPIRAM ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), "External SPIRAM overflowed.") #endif /* CONFIG_ESP_SPIRAM */ diff --git a/soc/espressif/esp32s2/mcuboot.ld b/soc/espressif/esp32s2/mcuboot.ld index 17a975ee363..8b2c6dc89a0 100644 --- a/soc/espressif/esp32s2/mcuboot.ld +++ b/soc/espressif/esp32s2/mcuboot.ld @@ -1,68 +1,187 @@ /* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the MCUboot on Xtensa platform. - */ - #include #include #include #include +#include "memory.h" + #ifdef CONFIG_XIP #error "Xtensa bootloader cannot use XIP" -#endif /* CONFIG_XIP */ +#endif /* Disable all romable LMA */ -#udef GROUP_DATA_LINK_IN +#undef GROUP_DATA_LINK_IN #define GROUP_DATA_LINK_IN(vregion, lregion) > vregion -#define RAMABLE_REGION dram_seg -#define RAMABLE_REGION_1 dram_seg - -#define RODATA_REGION dram_seg -#define ROMABLE_REGION dram_seg - -#define IRAM_REGION iram_seg -#define FLASH_CODE_REGION iram_seg - -#define IROM_SEG_ALIGN 16 +/* Aliases for zephyr scripts */ +#define RAMABLE_REGION dram_seg +#define RODATA_REGION dram_seg +#define ROMABLE_REGION dram_seg MEMORY { - iram_seg (RWX) : org = 0x40040000, len = 0x7000 - iram_loader_seg (RWX) : org = 0x40047000, len = 0x3000 - dram_seg (RW) : org = 0x3FFE6000, len = 0x6000 + iram_seg (RWX) : org = BOOTLOADER_IRAM_SEG_START, + len = BOOTLOADER_IRAM_SEG_LEN + iram_loader_seg (RWX) : org = BOOTLOADER_IRAM_LOADER_SEG_START, + len = BOOTLOADER_IRAM_LOADER_SEG_LEN + dram_seg (RW) : org = BOOTLOADER_DRAM_SEG_START, + len = BOOTLOADER_DRAM_SEG_LEN #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 #endif - } +/* Default entry point: */ ENTRY(CONFIG_KERNEL_ENTRY) SECTIONS { - /* NOTE: .rodata section should be the first section in the linker script and no - * other section should appear before .rodata section. This is the requirement - * to align ROM section to 64K page offset. - * Adding .rodata as first section helps to reduce size of generated binary by - * few kBs. - */ - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + .iram0.loader_text : { - __rodata_region_start = ABSOLUTE(.); + _loader_text_start = ABSOLUTE(.); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + + *libarch__xtensa__core.a:xtensa_asm2_util.*(.literal .text .literal.* .text.*) + *liblib__libc__common.a:abort.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libarch__common.a:dynamic_isr.*(.literal .text .literal.* .text.*) + *libarch__common.a:sw_isr_common.*(.literal .text .literal.* .text.*) + + *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*) + *libzephyr.a:heap.*(.literal .text .literal.* .text.*) + + *libkernel.a:kheap.*(.literal .text .literal.* .text.*) + *libkernel.a:mempool.*(.literal .text .literal.* .text.*) + *libkernel.a:device.*(.literal .text .literal.* .text.*) + *libkernel.a:timeout.*(.literal .text .literal.* .text.*) + + *(.literal.bootloader_mmap .text.bootloader_mmap) + *(.literal.bootloader_munmap .text.bootloader_munmap) + + *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + + *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*) + *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_system_abort .text.esp_system_abort) + + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /* CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; . = ALIGN(4); + _loader_text_end = ABSOLUTE(.); + _iram_text_end = ABSOLUTE(.); + _iram_end = ABSOLUTE(.); + } > iram_loader_seg + + .iram0.vectors : ALIGN(4) + { + _iram_start = ABSOLUTE(.); + /* Vectors go to IRAM */ + _init_start = ABSOLUTE(.); + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + _invalid_pc_placeholder = ABSOLUTE(.); + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + . = ALIGN (4); + _init_end = ABSOLUTE(.); + + _iram_start = ABSOLUTE(.); + } > iram_seg + + .iram0.text : + { + . = ALIGN(4); + + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + + *(.literal .text .literal.* .text.*) + . = ALIGN(4); + + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + . = ALIGN(4); + } > iram_seg + + .dram0.data : ALIGN(16) + { + . = ALIGN(4); + __data_start = ABSOLUTE(.); + #include + . = ALIGN(4); + #include + . = ALIGN(4); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) . = ALIGN(4); *(.rodata) *(.rodata.*) @@ -97,52 +216,17 @@ SECTIONS *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); . = ALIGN(4); - _thread_local_start = ABSOLUTE(.); - *(.tdata) - *(.tdata.*) - *(.tbss) - *(.tbss.*) *(.rodata_wlog) *(.rodata_wlog*) _thread_local_end = ABSOLUTE(.); . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + } > dram_seg - #include #include - #include - #include - #include #include #include #include - .dram0.data : - { - __data_start = ABSOLUTE(.); - - _btdm_data_start = ABSOLUTE(.); - *libbtdm_app.a:(.data .data.*) - . = ALIGN (4); - _btdm_data_end = ABSOLUTE(.); - - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.*) - *libzephyr.a:rtc_clk.*(.rodata .rodata.*) - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - #include #include #include @@ -150,132 +234,21 @@ SECTIONS #include #include - .dram0.end : - { - . = ALIGN(4); - #include - . = ALIGN(4); - _end = ABSOLUTE(.); - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - /* Send .iram0 code to iram */ - .iram0.vectors : ALIGN(4) + .noinit (NOLOAD): { - /* Vectors go to IRAM */ - _init_start = ABSOLUTE(.); - /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ - . = 0x0; - KEEP(*(.WindowVectors.text)); - . = 0x180; - KEEP(*(.Level2InterruptVector.text)); - . = 0x1c0; - KEEP(*(.Level3InterruptVector.text)); - . = 0x200; - KEEP(*(.Level4InterruptVector.text)); - . = 0x240; - KEEP(*(.Level5InterruptVector.text)); - . = 0x280; - KEEP(*(.DebugExceptionVector.text)); - . = 0x2c0; - KEEP(*(.NMIExceptionVector.text)); - . = 0x300; - KEEP(*(.KernelExceptionVector.text)); - . = 0x340; - KEEP(*(.UserExceptionVector.text)); - . = 0x3C0; - KEEP(*(.DoubleExceptionVector.text)); - . = 0x400; - *(.*Vector.literal) - - *(.UserEnter.literal); - *(.UserEnter.text); - . = ALIGN (16); - *(.entry.text) - *(.init.literal) - *(.init) - _init_end = ABSOLUTE(.); - - /* This goes here, not at top of linker script, so addr2line finds it last, - and uses it in preference to the first symbol in IRAM */ - _iram_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram_loader.text : - { - . = ALIGN (16); - _loader_text_start = ABSOLUTE(.); - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ - *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_flash_config_esp32s2.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_init_common.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libzephyr.a:bootloader_efuse_esp32s2.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) - *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) - *esp_mcuboot.*(.literal .text .literal.* .text.*) - *esp_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) - *(.fini.literal) - *(.fini) - *(.gnu.version) - _loader_text_end = ABSOLUTE(.); - } > iram_loader_seg - - SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) - { - /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); - - *(.iram1 .iram1.*) - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - - . = ALIGN(4); - _iram_text_end = ABSOLUTE(.); - _iram_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + . = ALIGN(8); + *(.noinit) + *(.noinit.*) + . = ALIGN(8) ; + } > dram_seg /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + .bss (NOLOAD): { . = ALIGN (8); _bss_start = ABSOLUTE(.); /* required by bluetooth library */ __bss_start = ABSOLUTE(.); - _btdm_bss_start = ABSOLUTE(.); - *libbtdm_app.a:(.bss .bss.* COMMON) - . = ALIGN (4); - _btdm_bss_end = ABSOLUTE(.); - - /* Buffer for system heap should be placed in dram_seg */ - *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap) - *(.dynsbss) *(.sbss) *(.sbss.*) @@ -294,35 +267,9 @@ SECTIONS __bss_end = ABSOLUTE(.); _bss_end = ABSOLUTE(.); _end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) + } > dram_seg - ASSERT(((__bss_end - ORIGIN(RAMABLE_REGION)) <= LENGTH(RAMABLE_REGION)), - "DRAM segment data does not fit.") - - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN (8); - *(.noinit) - *(.noinit.*) - . = ALIGN (8); - } GROUP_LINK_IN(RAMABLE_REGION_1) - - .flash.text : ALIGN(IROM_SEG_ALIGN) - { - _stext = .; - _text_start = ABSOLUTE(.); - - *(.literal .text .literal.* .text.*) - . = ALIGN(4); - _text_end = ABSOLUTE(.); - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) + ASSERT(((__bss_end - ORIGIN(dram_seg)) <= LENGTH(dram_seg)), "DRAM segment data does not fit.") #include @@ -363,8 +310,4 @@ SECTIONS #ifdef CONFIG_GEN_ISR_TABLES #include #endif - } - -ASSERT(((_iram_end - ORIGIN(IRAM_REGION)) <= LENGTH(IRAM_REGION)), - "IRAM0 segment data does not fit.") diff --git a/soc/espressif/esp32s2/memory.h b/soc/espressif/esp32s2/memory.h new file mode 100644 index 00000000000..5f7cd7fdbaf --- /dev/null +++ b/soc/espressif/esp32s2/memory.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/* SRAM0 (32k) with adjacted SRAM1 (288k) + * Ibus and Dbus address space + */ +#define SRAM_IRAM_START 0x40020000 +#define SRAM_DRAM_START 0x3ffb0000 +#define SRAM_CACHE_SIZE (CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ + + CONFIG_ESP32S2_DATA_CACHE_SIZE) + +/** Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32-S2 ROM static data usage is as follows: + * - 0x3ffeab00 - 0x3fffc410: Shared buffers, used in UART/USB/SPI download mode only + * - 0x3fffc410 - 0x3fffe710: CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fffe710 - 0x40000000: ROM .bss and .data (not easily reclaimable) + * + * The 2nd stage bootloader can take space up to the end of ROM shared + * buffers area (0x3fffc410). For alignment purpose we shall use value (0x3fce9700). + */ + +/* The offset between Dbus and Ibus. + * Used to convert between 0x4002xxxx and 0x3ffbxxxx addresses. + */ +#define IRAM_DRAM_OFFSET 0x70000 +#define DRAM_BUFFERS_START 0x3ffeab00 +#define DRAM_STACK_START 0x3fffc410 +#define DRAM_ROM_BSS_DATA_START 0x3fffe710 + +/* Base address used for calculating memory layout + * counted from Dbus backwards and back to the Ibus + */ +#define BOOTLOADER_USABLE_DRAM_END DRAM_BUFFERS_START + +/* For safety margin between bootloader data section and startup stacks */ +#define BOOTLOADER_STACK_OVERHEAD 0x0 +#define BOOTLOADER_DRAM_SEG_LEN 0x6000 +#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x2800 +#define BOOTLOADER_IRAM_SEG_LEN 0x8000 + +/* Start of the lower region is determined by region size and the end of the higher region */ +#define BOOTLOADER_DRAM_SEG_END (BOOTLOADER_USABLE_DRAM_END - BOOTLOADER_STACK_OVERHEAD) +#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_DRAM_SEG_END - BOOTLOADER_DRAM_SEG_LEN) +#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_DRAM_SEG_START - \ + BOOTLOADER_IRAM_LOADER_SEG_LEN + IRAM_DRAM_OFFSET) +#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN) + +/* Flash */ +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x400000 +#endif + +/* Cached memories */ +#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE +#define IROM_SEG_ORG 0x40080000 +#define IROM_SEG_LEN 0x780000 +#define DROM_SEG_ORG 0x3f000000 +#define DROM_SEG_LEN FLASH_SIZE diff --git a/soc/espressif/esp32s2/soc.c b/soc/espressif/esp32s2/soc.c index 0ff49920737..2df9f7f288f 100644 --- a/soc/espressif/esp32s2/soc.c +++ b/soc/espressif/esp32s2/soc.c @@ -75,12 +75,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) esp_reset_reason_init(); -#ifdef CONFIG_MCUBOOT - /* MCUboot early initialisation. */ - if (bootloader_init()) { - abort(); - } -#else +#ifndef CONFIG_MCUBOOT /* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence * related issues in application. Hence disable that as we are about to start * Zephyr environment. @@ -110,7 +105,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) #ifdef CONFIG_SOC_FLASH_ESP32 esp_mspi_pin_init(); spi_flash_init_chip_state(); -#endif /*CONFIG_SOC_FLASH_ESP32*/ +#endif /* CONFIG_SOC_FLASH_ESP32 */ esp_mmu_map_init(); @@ -152,7 +147,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) #if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM spi_flash_guard_set(&g_flash_guard_default_ops); #endif -#endif /* CONFIG_MCUBOOT */ +#endif /* !CONFIG_MCUBOOT */ esp_intr_initialize(); /* Start Zephyr */ From 2395f08d489c2e222bb9691d3985f8b6d74f2cd8 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Wed, 14 Feb 2024 11:48:14 +0100 Subject: [PATCH 1998/2402] soc: espressif: esp32: simple boot support Add simplistic booting method which allows to run applications without the 2nd stage bootloader. - introduce memory layout header file - update and optimize default and mcuboot linker scripts - remove building multiple binaries during the application build Signed-off-by: Marek Matej --- soc/espressif/esp32/CMakeLists.txt | 67 +- soc/espressif/esp32/default.ld | 999 ++++++++++++++++++----------- soc/espressif/esp32/mcuboot.ld | 373 +++++------ soc/espressif/esp32/memory.h | 83 +++ soc/espressif/esp32/soc.c | 13 +- 5 files changed, 913 insertions(+), 622 deletions(-) create mode 100644 soc/espressif/esp32/memory.h diff --git a/soc/espressif/esp32/CMakeLists.txt b/soc/espressif/esp32/CMakeLists.txt index b1ad883b3e3..f6f38056a4d 100644 --- a/soc/espressif/esp32/CMakeLists.txt +++ b/soc/espressif/esp32/CMakeLists.txt @@ -22,41 +22,28 @@ zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) # get flash size to use in esptool as string math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") -if(CONFIG_BOOTLOADER_ESP_IDF) +# This includes CONFIG_MCUBOOT and CONFIG_ESP_SIMPLE_BOOT +if(NOT CONFIG_BOOTLOADER_MCUBOOT) - set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") - - if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") - endif() - - if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") - endif() - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + if(CONFIG_BUILD_OUTPUT_BIN) -endif() + set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py) + message("esptool path: ${ESPTOOL_PY}") -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + set(ELF2IMAGE_ARG "") + if(NOT CONFIG_MCUBOOT) + set(ELF2IMAGE_ARG "--ram-only-header") + endif() - if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py - ARGS --chip esp32 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY} + ARGS --chip esp32 elf2image ${ELF2IMAGE_ARG} + --flash_mode dio --flash_freq 40m + --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) endif() - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - endif() ## When building for APPCPU @@ -71,18 +58,36 @@ if (CONFIG_SOC_ESP32_APPCPU) endif() else() + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + # get code-partition boot address + dt_nodelabel(dts_partition_path NODELABEL "boot_partition") + dt_reg_addr(boot_off PATH ${dts_partition_path}) + # get code-partition slot0 address dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") dt_reg_addr(img_0_off PATH ${dts_partition_path}) - # get code-partition boot address - dt_nodelabel(dts_partition_path NODELABEL "boot_partition") - dt_reg_addr(boot_off PATH ${dts_partition_path}) + if(CONFIG_ESP_SIMPLE_BOOT) + board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}") + else() + board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + endif() + +endif() - board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") - board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") +if(CONFIG_MCUBOOT) + # search from cross references between bootloader sections + message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py") + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py + ARGS + --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr + --elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf + find-refs --from-section=.iram0.iram_loader --to-section=.iram0.text + --exit-code) endif() if(CONFIG_MCUBOOT) diff --git a/soc/espressif/esp32/default.ld b/soc/espressif/esp32/default.ld index a4210b3cc74..4f0ac082896 100644 --- a/soc/espressif/esp32/default.ld +++ b/soc/espressif/esp32/default.ld @@ -1,50 +1,48 @@ /* * Copyright (c) 2016 Cadence Design Systems, Inc. * Copyright (c) 2017 Intel Corporation - * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - #include #include #include #include -#define RAMABLE_REGION dram0_0_seg -#ifdef CONFIG_SOC_ENABLE_APPCPU -#define RAMABLE_REGION_1 dram0_0_seg -#else -#define RAMABLE_REGION_1 dram0_1_seg -#endif -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define FLASH_CODE_REGION irom0_0_seg - -#define ROMABLE_REGION ROM +#include "memory.h" -#ifdef CONFIG_FLASH_SIZE -#define FLASH_SIZE CONFIG_FLASH_SIZE +/* The "user_iram_end" represents the 2nd stage bootloader + * "dram_seg" end address (that should not be overlapped). + * If no bootloader is used we extend it to gain more user ram. + */ +#ifdef CONFIG_ESP_SIMPLE_BOOT +user_iram_end = SRAM1_DRAM_IRAM_CALC(SRAM1_DRAM_USABLE_START); #else -#define FLASH_SIZE 0x400000 +user_iram_end = SRAM1_DRAM_IRAM_CALC(BOOTLOADER_DRAM_SEG_END); #endif -#ifdef CONFIG_BOOTLOADER_ESP_IDF -#define IROM_SEG_ORG 0x400D0020 -#define IROM_SEG_LEN FLASH_SIZE-0x20 -#define IROM_SEG_ALIGN 0x4 +/* User available SRAM memory segments */ +user_iram_seg_org = (SRAM0_IRAM_START + SRAM0_CACHE_SIZE); +user_iram_seg_len = user_iram_end - user_iram_seg_org; +user_dram_seg_org = SRAM2_DRAM_USABLE_START; +user_dram_seg_len = SRAM2_USABLE_SIZE; +user_dram_2_seg_org = SRAM1_DRAM_USABLE_START; +user_dram_2_seg_len = SRAM1_USABLE_SIZE; + +/* Aliases */ +#define FLASH_CODE_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define DRAM_REGION dram0_0_seg +#define RAMABLE_REGION dram0_0_seg +#define ROMABLE_REGION FLASH + +#ifndef CONFIG_SOC_ESP32_PROCPU +#define RAMABLE_REGION_1 dram0_1_seg #else -#define IROM_SEG_ORG 0x400D0000 -#define IROM_SEG_LEN FLASH_SIZE -#define IROM_SEG_ALIGN 0x10000 +#define RAMABLE_REGION_1 dram0_0_seg #endif -#define IRAM_SEG_LEN 0x20000 /* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. * Executing directly from LMA is not possible. */ @@ -53,57 +51,53 @@ MEMORY { - mcuboot_hdr (RX): org = 0x0, len = 0x20 - metadata (RX): org = 0x20, len = 0x20 - ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 +#ifdef CONFIG_BOOTLOADER_MCUBOOT + mcuboot_hdr (R): org = 0x0, len = 0x20 + metadata (R): org = 0x20, len = 0x20 + FLASH (R): org = 0x40, len = FLASH_SIZE - 0x40 +#else + /* Make safety margin in the FLASH memory size so the + * (esp_img_header + (n*esp_seg_headers)) would fit */ + FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100 +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ - #ifdef CONFIG_SOC_ENABLE_APPCPU - iram0_0_seg(RX): org = 0x40080000, len = 0x08000 - #else - iram0_0_seg(RX): org = 0x40080000, len = IRAM_SEG_LEN - #endif +#ifndef CONFIG_SOC_ESP32_APPCPU + iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len +#else + iram0_0_seg(RX): org = user_iram_seg_org, len = 0x8000 +#endif /* CONFIG_SOC_ESP32_APPCPU */ + + dram0_0_seg(RW): org = user_dram_seg_org + CONFIG_ESP32_BT_RESERVE_DRAM, + len = user_dram_seg_len - CONFIG_ESP32_BT_RESERVE_DRAM + +#ifdef CONFIG_SOC_ESP32_PROCPU + /* shared RAM reserved for IPM */ + dram0_shm0_seg(RW): org = 0x3ffe5230, len = 2K + /* shared data reserved for IPM data header */ + dram0_sem0_seg(RW): org = 0x3ffe5a30, len = 8 + /* for AMP builds dram0_1 is reserved for network core */ + dram0_1_seg(RW): org = 0x3ffe5a38, len = 0K +#else + /* skip data for APP CPU initialization usage */ + dram0_1_seg(RW): org = user_dram_2_seg_org, len = user_dram_2_seg_len +#endif /* CONFIG_SOC_ESP32_PROCPU */ irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - /* - * Following is DRAM memory split with reserved address ranges in ESP32: - * - * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions) - * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage) - * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU) - * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU) - * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage) - * - * FIXME: - * - Utilize available memory regions to full capacity - */ - dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM - - #ifdef CONFIG_SOC_ENABLE_APPCPU - dram0_shm0_seg(RW): org = 0x3FFE5230, len = 2K /* shared RAM reserved for IPM */ - dram0_sem0_seg(RW): org = 0x3FFE5A30, len = 8 /* shared data reserved for IPM data header */ - dram0_1_seg(RW): org = 0x3FFE5A38, len = 0K /* for AMP builds dram0_1 is reserved for network core */ - #else - dram0_1_seg(RW): org = 0x3FFE5230, len = 0x1BCB0 - 0xEE0 /* skip data for APP CPU initialization usage */ - #endif - - /* DROM is the first segment placed in generated binary. - * MCUboot binary for ESP32 has image header of 0x20 bytes. - * Additional load header of 0x20 bytes are appended to the image. - * Hence, an offset of 0x40 is added to DROM segment origin. - */ - drom0_0_seg(R): org = 0x3F400040, len = 0x400000 - 0x40 - rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000 - rtc_slow_seg(RW): org = 0x50000000, len = 0x1000 -#if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE -#endif + drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN + + rtc_iram_seg(RWX): org = 0x400c0000, len = 0x2000 + rtc_slow_seg(RW): org = 0x50000000, len = 0x1000 + +#ifdef CONFIG_ESP_SPIRAM + ext_ram_seg(RW): org = 0x3f800000, len = CONFIG_ESP_SPIRAM_SIZE +#endif /* CONFIG_ESP_SPIRAM */ + #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 -#endif +#endif /* CONFIG_GEN_ISR_TABLES */ } /* Default entry point: */ -PROVIDE ( _ResetVector = 0x40000400 ); ENTRY(CONFIG_KERNEL_ENTRY) _rom_store_table = 0; @@ -111,8 +105,15 @@ _rom_store_table = 0; PROVIDE(_memmap_vecbase_reset = 0x40000450); PROVIDE(_memmap_reset_vector = 0x40000400); +#ifdef CONFIG_BT +_heap_sentry = SRAM1_DRAM_USABLE_START; +#else +_heap_sentry = DRAM1_BT_SHM_BUFFERS_START; /* was 0x3ffe3f20; */ +#endif + SECTIONS { +#ifdef CONFIG_BOOTLOADER_MCUBOOT /* Reserve space for MCUboot header in the binary */ .mcuboot_header : { @@ -123,211 +124,91 @@ SECTIONS } > mcuboot_hdr .metadata : { - /* Magic byte for load header */ + /* 0. Magic byte for load header */ LONG(0xace637d3) - /* Application entry point address */ + /* 1. Application entry point address */ KEEP(*(.entry_addr)) - /* IRAM metadata: - * - Destination address (VMA) for IRAM region - * - Flash offset (LMA) for start of IRAM region - * - Size of IRAM region + /* IRAM load: + * 2. Destination address (VMA) for IRAM region + * 3. Flash offset (LMA) for start of IRAM region + * 4. Size of IRAM region */ - LONG(ADDR(.iram0.vectors)) LONG(LOADADDR(.iram0.vectors)) - LONG(LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - LOADADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors)) - /* DRAM metadata: - * - Destination address (VMA) for DRAM region - * - Flash offset (LMA) for start of DRAM region - * - Size of DRAM region + /* DRAM load: + * 5. Destination address (VMA) for DRAM region + * 6. Flash offset (LMA) for start of DRAM region + * 7. Size of DRAM region */ - LONG(ADDR(.dram0.data)) LONG(LOADADDR(.dram0.data)) LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) } > metadata +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ -#include + #include - _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); - _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; - _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); + /* --- RTC BEGIN --- */ - /* NOTE: .rodata section should be the first section in the linker script and no - * other section should appear before .rodata section. This is the requirement - * to align ROM section to 64K page offset. - * Adding .rodata as first section helps to reduce size of generated binary by - * few kBs. + /* RTC fast memory holds RTC wake stub code, + * including from any source file named rtc_wake_stub*.c */ - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + .rtc.text : { - __rodata_region_start = ABSOLUTE(.); - _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ - - . = ALIGN(4); - #include - - . = ALIGN(4); - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata) - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*) - - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; - - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); - __rodata_region_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - *(.rodata_wlog) - *(.rodata_wlog*) . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - #include - #include - #include - #include + *(.rtc.literal .rtc.text) + *rtc_wake_stub*.o(.literal .text .literal.* .text.*) + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - /* Create an explicit section at the end of all the data that shall be mapped into drom. - * This is used to calculate the size of the _image_drom_size variable */ - SECTION_PROLOGUE(_RODATA_SECTION_END,,) + /* RTC slow memory holds RTC wake stub + * data/rodata, including from any source file + * named rtc_wake_stub*.c + */ + .rtc.data : { - . = ALIGN(4); - _image_rodata_end = ABSOLUTE(.); - _rodata_reserved_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - - _image_dram_start = LOADADDR(.dram0.data); - _image_dram_size = LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - _image_dram_start; - _image_dram_vaddr = ADDR(.dram0.data); + _rtc_data_start = ABSOLUTE(.); + *(.rtc.data) + *(.rtc.rodata) + *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) + _rtc_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - .dram0.data : + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : { - __data_start = ABSOLUTE(.); - - _btdm_data_start = ABSOLUTE(.); - *libbtdm_app.a:(.data .data.*) - . = ALIGN (4); - _btdm_data_end = ABSOLUTE(.); - - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - /* rodata for panic handler(libarch__xtensa__core.a) and all - * dependent functions should be placed in DRAM to avoid issue - * when flash cache is disabled */ - *libarch__xtensa__core.a:(.rodata .rodata.*) - *libkernel.a:fatal.*(.rodata .rodata.*) - *libkernel.a:init.*(.rodata .rodata.*) - *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) - *libzephyr.a:log_core.*(.rodata .rodata.*) - *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) - *libzephyr.a:log_output.*(.rodata .rodata.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.*) - *libzephyr.a:loader.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) - *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) - *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) - *libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:rtc_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - - *libzephyr.a:cache_esp32.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:esp_cache.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:esp_err.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_slave_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - *libzephyr.a:heap_caps_zephyr.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.o(.bss .bss.*) + *rtc_wake_stub*.o(COMMON) + _rtc_bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(rtc_slow_seg) - KEEP(*(.jcr)) - *(.dram1 .dram1.*) + /* This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } > rtc_slow_seg - /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ - #pragma push_macro("GROUP_ROM_LINK_IN") - #undef GROUP_ROM_LINK_IN - #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN - #include - #pragma pop_macro("GROUP_ROM_LINK_IN") + /* Get size of rtc slow data */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); - .dram0.end : - { - . = ALIGN(4); - #include - . = ALIGN(4); - _end = ABSOLUTE(.); - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + /* --- RTC END --- */ - _image_iram_start = LOADADDR(.iram0.vectors); - _image_iram_size = LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - _image_iram_start; - _image_iram_vaddr = ADDR(.iram0.vectors); + /* --- IRAM BEGIN --- */ - /* Send .iram0 code to iram */ .iram0.vectors : ALIGN(4) { + _iram_start = ABSOLUTE(.); /* Vectors go to IRAM */ _init_start = ABSOLUTE(.); /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ @@ -361,175 +242,424 @@ SECTIONS *(.init.literal) *(.init) _init_end = ABSOLUTE(.); - - /* This goes here, not at top of linker script, so addr2line finds it last, - and uses it in preference to the first symbol in IRAM */ - _iram_start = ABSOLUTE(0); } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) + .iram0.text : ALIGN(4) { /* Code marked as running out of IRAM */ _iram_text_start = ABSOLUTE(.); *(.iram1 .iram1.*) *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - *libesp32.a:panic.*(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) *libkernel.a:(.literal .text .literal.* .text.*) - *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) - *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) - *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) - *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) - *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) - *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_*.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu_util.*(.literal .text .literal.* .text.*) + *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) + *liblib__libc__picolib.a:abort.*(.literal .text .literal.* .text.*) *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) *libc.a:*(.literal .text .literal.* .text.*) *libphy.a:( .phyiram .phyiram.*) *libgcov.a:(.literal .text .literal.* .text.*) - *libzephyr.a:cpu.*(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) - *libzephyr.a:cpu.*(.literal.esp_cpu_reset .text.esp_cpu_reset) - *libzephyr.a:cpu.*(.literal.esp_cpu_stall .text.esp_cpu_stall) - *libzephyr.a:cpu.*(.literal.esp_cpu_unstall .text.esp_cpu_unstall) - *libzephyr.a:cpu.*(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) - *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) - *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) - *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) - *libzephyr.a:periph_ctrl.*(.literal.periph_module_reset .text.periph_module_reset) - *libzephyr.a:periph_ctrl.*(.literal.wifi_module_disable .text.wifi_module_disable) - *libzephyr.a:periph_ctrl.*(.literal.wifi_module_enable .text.wifi_module_enable) - *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_wdt.*(.literal .literal.* .text .text.*) - *libzephyr.a:sar_periph_ctrl.*(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) - *libzephyr.a:cache_esp32.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) - *libzephyr.a:esp_system_chip.*(.literal.esp_system_abort .text.esp_system_abort) - *libzephyr.a:i2c_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:ledc_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) + + /* [mapping:esp_psram] */ + *libzephyr.a:mmu_psram_flash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_psram_impl_quad.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_psram_impl_octal.*(.literal .literal.* .text .text.*) + + /* [mapping:hal] */ *libzephyr.a:mmu_hal.*(.literal .literal.* .text .text.*) - *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*) - *libzephyr.a:spi_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:spi_slave_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:i2c_hal_iram.*(.literal .literal.* .text .text.*) *libzephyr.a:wdt_hal_iram.*(.literal .literal.* .text .text.*) - *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) - *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .literal.* .text .text.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.literal .literal.* .text .text.*) + + /* [mapping:log] */ + *(.literal.esp_log_write .text.esp_log_write) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_log_impl_lock .text.esp_log_impl_lock) + *(.literal.esp_log_impl_lock_timeout .text.esp_log_impl_lock_timeout) + *(.literal.esp_log_impl_unlock .text.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hpm_enable.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_oct_flash_init*(.literal .literal.* .text .text.*) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *(.literal.esp_system_abort .text.esp_system_abort) + + /* [mapping:esp_hw_support] */ + *(.literal.esp_cpu_stall .text.esp_cpu_stall) + *(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *(.literal.esp_cpu_reset .text.esp_cpu_reset) + *(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *(.literal.rtc_vddsdio_get_config .text.rtc_vddsdio_get_config) + *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*) + *libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*) + *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + +/* TODO: optimize SRAM usage + *libzephyr.a:periph_ctrl.*(.literal.periph_module_reset .text.periph_module_reset) + *libzephyr.a:periph_ctrl.*(.literal.wifi_module_disable .text.wifi_module_disable) + *libzephyr.a:periph_ctrl.*(.literal.wifi_module_enable .text.wifi_module_enable) + *libzephyr.a:rtc_wdt.*(.literal .literal.* .text .text.*) +*/ + *libzephyr.a:esp_system_chip.*(.literal.esp_system_abort .text.esp_system_abort) + *libzephyr.a:spi_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_slave_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) *libzephyr.a:heap_caps_zephyr.*(.literal .literal.* .text .text.*) + /* [mapping:soc_pm] */ + *(.literal.GPIO_HOLD_MASK .text.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) + *libzephyr.a:cache_esp32.*(.literal .literal.* .text .text.*) + #if defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) -#endif + + /* [mapping:esp_wifi] */ + *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper) + *(.literal.wifi_clock_disable_wrapper .text.wifi_clock_disable_wrapper) + + /* [mapping:esp_phy] */ + *(.literal.esp_phy_enable .text.esp_phy_enable) + *(.literal.esp_phy_disable .text.esp_phy_disable) + *(.literal.esp_wifi_bt_power_domain_off .text.esp_wifi_bt_power_domain_off) +#endif /* CONFIG_ESP32_WIFI_IRAM_OPT */ #if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif +#endif /* CONFIG_ESP32_WIFI_RX_IRAM_OPT */ - _iram_text_end = ABSOLUTE(.); . = ALIGN(4); - _iram_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - /* RTC fast memory holds RTC wake stub code, - including from any source file named rtc_wake_stub*.c - */ - .rtc.text : +#ifdef CONFIG_ESP_SIMPLE_BOOT + .loader.text : { - . = ALIGN(4); - *(.rtc.literal .rtc.text) - *rtc_wake_stub*.o(.literal .text .literal.* .text.*) - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + . = ALIGN(4); + *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_esp32.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_wdt.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash_config_esp32.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_common.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_mem.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + *libzephyr.a:bootloader_efuse.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) + + *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_flash_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_flash_spi_init.*(.literal .text .literal.* .text.*) + + *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) + + *libzephyr.a:efuse_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api_key_esp32.*(.literal .text .literal.* .text.*) + + *libzephyr.a:app_cpu_start.*(.literal .text .literal.* .text.*) + *libzephyr.a:mpu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu_region_protect.*(.literal .text .literal.* .text.*) + + /* to overcome the bug in esptool making Simple boot compatible image */ + . += 16; + . = ALIGN(16); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ - /* RTC slow memory holds RTC wake stub - data/rodata, including from any source file - named rtc_wake_stub*.c - */ - .rtc.data : + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : { - _rtc_data_start = ABSOLUTE(.); - *(.rtc.data) - *(.rtc.rodata) - *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) - _rtc_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + /* ESP32 memprot requires 16B padding for possible CPU + * prefetch and 256B alignment for PMS split lines */ + . += 16; + . = ALIGN(0x100); + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : + .iram0.data : { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.o(.bss .bss.*) - *rtc_wake_stub*.o(COMMON) - _rtc_bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(rtc_slow_seg) + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - /* This section located in RTC SLOW Memory area. - It holds data marked with RTC_SLOW_ATTR attribute. - See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : + .iram0.bss (NOLOAD) : { + . = ALIGN(16); + _iram_bss_start = ABSOLUTE(.); + *(.iram.bss) + *(.iram.bss.*) + _iram_bss_end = ABSOLUTE(.); + . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } > rtc_slow_seg + _iram_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) - /* Get size of rtc slow data */ - _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + /* --- IRAM END --- */ -#if defined(CONFIG_ESP_SPIRAM) - .ext_ram.bss (NOLOAD): + /* --- DRAM BEGIN --- */ + + .dram0.data : { - _ext_ram_data_start = ABSOLUTE(.); + _dram_data_start = ABSOLUTE(.); + _data_start = ABSOLUTE(.); -#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) - *libdrivers__wifi.a:(.noinit .noinit.*) - *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) - *libsubsys__net__lib__config.a:(.noinit .noinit.*) - *libsubsys__net__ip.a:(.noinit .noinit.*) - *libsubsys__net.a:(.noinit .noinit.*) -#endif - _ext_ram_bss_start = ABSOLUTE(.); - *(.ext_ram.bss*) - _ext_ram_bss_end = ABSOLUTE(.); + _btdm_data_start = ABSOLUTE(.); + *libbtdm_app.a:(.data .data.*) + . = ALIGN (4); + _btdm_data_end = ABSOLUTE(.); - _spiram_heap_start = ABSOLUTE(.); - . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + /* rodata for panic handler(libarch__xtensa__core.a) and all + * dependent functions should be placed in DRAM to avoid issue + * when flash cache is disabled */ + *libarch__xtensa__core.a:(.rodata .rodata.*) + *libkernel.a:fatal.*(.rodata .rodata.*) + *libkernel.a:init.*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:loader.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) - _ext_ram_data_end = ABSOLUTE(.); - } GROUP_LINK_IN(ext_ram_seg) -#endif + /* [mapping:esp_psram] */ + *libzephyr.a:mmu_psram_flash.*(.rodata .rodata.*) + *libzephyr.a:esp_psram_impl_octal.*(.rodata .rodata.*) + *libzephyr.a:esp_psram_impl_quad.*(.rodata .rodata.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:cache_hal.*(.rodata .rodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.rodata .rodata.*) + + /* [mapping:log] */ + *(.rodata.esp_log_write) + *(.rodata.esp_log_timestamp) + *(.rodata.esp_log_early_timestamp) + *(.rodata.esp_log_impl_lock) + *(.rodata.esp_log_impl_lock_timeout) + *(.rodata.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hpm_enable.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_oct_flash_init.*(.rodata .rodata.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.rodata .rodata.*) + + /* [mapping:esp_hw_support] */ + *(.rodata.esp_cpu_stall) + *(.rodata.esp_cpu_unstall) + *(.rodata.esp_cpu_reset) + *(.rodata.esp_cpu_wait_for_intr) + *(.rodata.esp_cpu_compare_and_set) + *(.rodata.esp_gpio_reserve_pins) + *(.rodata.esp_gpio_is_pin_reserved) + *(.rodata.rtc_vddsdio_get_config) + *(.rodata.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk_init.*(.rodata .rodata.*) + *libzephyr.a:systimer.*(.rodata .rodata.*) + *libzephyr.a:mspi_timing_config.*(.rodata .rodata.*) + *libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.*) + *(.rodata.sar_periph_ctrl_power_enable) + + *libzephyr.a:cache_esp32.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_cache.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_err.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_slave_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + /* TODO: fix other socs */ + *libzephyr.a:heap_caps_zephyr.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_wdt.*(.rodata .rodata.*) + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + + . = ALIGN(4); + #include + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + +#ifdef CONFIG_ESP_SIMPLE_BOOT + .loader.data : + { + . = ALIGN(4); + _loader_data_start = ABSOLUTE(.); + *libzephyr.a:bootloader_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_esp32.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_clock_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_wdt.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_flash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_flash_config_esp32.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_common.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_common_loader.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:bootloader_efuse.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:cpu_util.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:rtc_clk_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:rtc_time.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:efuse_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:cpu_region_protect.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:periph_ctrl.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + *libzephyr.a:esp_flash_api.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_flash_spi_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + . = ALIGN(4); + _loader_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(DRAM_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ + + #include + #include + #include + #include + #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ + #pragma push_macro("GROUP_ROM_LINK_IN") + #undef GROUP_ROM_LINK_IN + #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN + #include + #pragma pop_macro("GROUP_ROM_LINK_IN") + + .dram0.end : + { + __data_end = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + .dram0.bss (NOLOAD) : { . = ALIGN (8); _bss_start = ABSOLUTE(.); /* required by bluetooth library */ @@ -559,13 +689,13 @@ SECTIONS *(COMMON) . = ALIGN (8); __bss_end = ABSOLUTE(.); - _end = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); } GROUP_LINK_IN(RAMABLE_REGION) ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) + .dram0.noinit (NOLOAD) : { . = ALIGN (8); *(.noinit) @@ -573,40 +703,173 @@ SECTIONS . = ALIGN (8); } GROUP_LINK_IN(RAMABLE_REGION_1) + .dram0.end (NOLOAD) : + { + . = ALIGN(4); + _end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + /* TODO: Provide total SRAM usage, including IRAM and DRAM */ + /* _image_ram_start = _iram_start - IRAM_DRAM_OFFSET; */ + /* #include */ + + /* --- DRAM END --- */ + + /* --- SPIRAM BEGIN --- */ + +#ifdef CONFIG_ESP_SPIRAM + .ext_ram.bss (NOLOAD): + { + _ext_ram_data_start = ABSOLUTE(.); + +#ifdef CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM + *libdrivers__wifi.a:(.noinit .noinit.*) + *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) + *libsubsys__net__lib__config.a:(.noinit .noinit.*) + *libsubsys__net__ip.a:(.noinit .noinit.*) + *libsubsys__net.a:(.noinit .noinit.*) +#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */ + + _ext_ram_bss_start = ABSOLUTE(.); + *(.ext_ram.bss*) + _ext_ram_bss_end = ABSOLUTE(.); + _spiram_heap_start = ABSOLUTE(.); + . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; + + _ext_ram_data_end = ABSOLUTE(.); + } GROUP_LINK_IN(ext_ram_seg) +#endif /* CONFIG_ESP_SPIRAM */ + + /* --- SPIRAM END --- */ + + /* --- RODATA BEGIN --- */ + + .flash.rodata_dummy (NOLOAD) : + { + . = ALIGN(CACHE_ALIGN); + } GROUP_LINK_IN(ROMABLE_REGION) + + _image_drom_start = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata_end) - LOADADDR(.flash.rodata); + _image_drom_vaddr = ADDR(.flash.rodata); + + .flash.rodata : ALIGN(CACHE_ALIGN) + { + _rodata_start = ABSOLUTE(.); + _rodata_reserved_start = ABSOLUTE(.); + + . = ALIGN(4); + #include + . = ALIGN(4); + + *(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.* ) + + _flash_rodata_start = ABSOLUTE(.); + __rodata_region_start = ABSOLUTE(.); + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + _rodata_end = ABSOLUTE(.); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + + *(.rodata_wlog) + *(.rodata_wlog*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + .flash.rodata_end : + { + /* This is a symbol marking the flash.rodata end, this + * can be used for mmu driver to maintain virtual address + * We don't need to include the noload rodata in this section + */ + . = ALIGN(CONFIG_MMU_PAGE_SIZE); + + _rodata_end = ABSOLUTE(.); + _rodata_reserved_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + /* --- RODATA END --- */ + + /* --- FLASH TEXT BEGIN --- */ + + .flash.text_dummy (NOLOAD): + { + . = ALIGN(CACHE_ALIGN); + } GROUP_LINK_IN(ROMABLE_REGION) + _image_irom_start = LOADADDR(.flash.text); _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; _image_irom_vaddr = ADDR(.flash.text); - .flash.text : ALIGN(IROM_SEG_ALIGN) + .flash.text : ALIGN(CACHE_ALIGN) { _stext = .; _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ _text_start = ABSOLUTE(.); -#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) +#ifndef CONFIG_ESP32_WIFI_IRAM_OPT *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) #endif -#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) +#ifndef CONFIG_ESP32_WIFI_RX_IRAM_OPT *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) #endif + *(.fini.literal) + *(.fini) + *(.literal .text .literal.* .text.*) . = ALIGN(4); _text_end = ABSOLUTE(.); _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - resolved by addr2line in preference to the first symbol in - the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) -_heap_sentry = 0x3ffe3f20; + /* --- FLASH TEXT END --- */ + + /* --- XTENSA GLUE AND DEBUG BEGIN --- */ #include @@ -650,10 +913,12 @@ _heap_sentry = 0x3ffe3f20; } + /* --- XTENSA GLUE AND DEBUG END --- */ + ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), "IRAM0 segment data does not fit.") -#if defined(CONFIG_ESP_SPIRAM) +#ifdef CONFIG_ESP_SPIRAM ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), "External SPIRAM overflowed.") #endif /* CONFIG_ESP_SPIRAM */ diff --git a/soc/espressif/esp32/mcuboot.ld b/soc/espressif/esp32/mcuboot.ld index d30e1e8c68d..37d284cbcd9 100644 --- a/soc/espressif/esp32/mcuboot.ld +++ b/soc/espressif/esp32/mcuboot.ld @@ -1,20 +1,15 @@ /* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the MCUboot on Xtensa platform. - */ - #include #include #include #include +#include "memory.h" + #ifdef CONFIG_XIP #error "Xtensa bootloader cannot use XIP" #endif /* CONFIG_XIP */ @@ -23,22 +18,20 @@ #undef GROUP_DATA_LINK_IN #define GROUP_DATA_LINK_IN(vregion, lregion) > vregion -#define RAMABLE_REGION dram_seg -#define RAMABLE_REGION_1 dram_seg - -#define RODATA_REGION dram_seg -#define ROMABLE_REGION dram_seg - -#define IRAM_REGION iram_seg -#define FLASH_CODE_REGION iram_seg - -#define IROM_SEG_ALIGN 16 +/* Aliases */ +#define RAMABLE_REGION dram_seg +#define RAMABLE_REGION_1 dram_seg +#define RODATA_REGION dram_seg +#define ROMABLE_REGION dram_seg MEMORY { - iram_loader_seg (RWX) : org = 0x40078000, len = 0x4000 - iram_seg (RWX) : org = 0x4009C000, len = 0x8000 - dram_seg (RW) : org = 0x3FFF0000, len = 0x6400 + iram_loader_seg (RWX) : org = BOOTLOADER_IRAM_LOADER_SEG_START, + len = BOOTLOADER_IRAM_LOADER_SEG_LEN + iram_seg (RWX) : org = BOOTLOADER_IRAM_SEG_START, + len = BOOTLOADER_IRAM_SEG_LEN + dram_seg (RW) : org = BOOTLOADER_DRAM_SEG_START, + len = BOOTLOADER_DRAM_SEG_LEN #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -49,19 +42,145 @@ ENTRY(CONFIG_KERNEL_ENTRY) SECTIONS { - /* NOTE: .rodata section should be the first section in the linker script and no - * other section should appear before .rodata section. This is the requirement - * to align ROM section to 64K page offset. - * Adding .rodata as first section helps to reduce size of generated binary by - * few kBs. - */ - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + .iram0.loader_text : { - __rodata_region_start = ABSOLUTE(.); + _loader_text_start = ABSOLUTE(.); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + + *libarch__xtensa__core.a:xtensa_asm2_util.*(.literal .text .literal.* .text.*) + *liblib__libc__common.a:abort.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libarch__common.a:dynamic_isr.*(.literal .text .literal.* .text.*) + *libarch__common.a:sw_isr_common.*(.literal .text .literal.* .text.*) + + *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_esp32.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*) + + *libzephyr.a:heap.*(.literal .text .literal.* .text.*) + + *libkernel.a:kheap.*(.literal .text .literal.* .text.*) + *libkernel.a:mempool.*(.literal .text .literal.* .text.*) + *libkernel.a:device.*(.literal .text .literal.* .text.*) + *libkernel.a:timeout.*(.literal .text .literal.* .text.*) + + *(.literal.bootloader_mmap .text.bootloader_mmap) + *(.literal.bootloader_munmap .text.bootloader_munmap) + + *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + + *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*) + *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_system_abort .text.esp_system_abort) + + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /* CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; + . = ALIGN(4) + 16; + _loader_text_end = ABSOLUTE(.); + _iram_text_end = ABSOLUTE(.); + _iram_end = ABSOLUTE(.); + } > iram_loader_seg + .iram0.vectors : ALIGN(4) + { + /* Vectors go to IRAM */ + _init_start = ABSOLUTE(.); + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + _invalid_pc_placeholder = ABSOLUTE(.); + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + . = ALIGN (4); + _init_end = ABSOLUTE(.); + + _iram_start = ABSOLUTE(.); + } > iram_seg + + .iram0.text : + { . = ALIGN(4); + + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + + *(.literal .text .literal.* .text.*) + . = ALIGN(4); + + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + . = ALIGN(4) + 16; + } > iram_seg + + .dram0.data : ALIGN(16) + { + . = ALIGN(4); + __data_start = ABSOLUTE(.); + #include + . = ALIGN(4); + #include + . = ALIGN(4); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) . = ALIGN(4); *(.rodata) *(.rodata.*) @@ -96,50 +215,17 @@ SECTIONS *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); . = ALIGN(4); - _thread_local_start = ABSOLUTE(.); - *(.tdata) - *(.tdata.*) - *(.tbss) - *(.tbss.*) *(.rodata_wlog) *(.rodata_wlog*) _thread_local_end = ABSOLUTE(.); . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + } > dram_seg - #include #include #include #include #include - .dram0.data : - { - __data_start = ABSOLUTE(.); - - _btdm_data_start = ABSOLUTE(.); - *libbtdm_app.a:(.data .data.*) - . = ALIGN (4); - _btdm_data_end = ABSOLUTE(.); - - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.*) - *libzephyr.a:rtc_clk.*(.rodata .rodata.*) - - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - #include #include #include @@ -147,134 +233,21 @@ SECTIONS #include #include - .dram0.end : - { - . = ALIGN(4); - #include - . = ALIGN(4); - _end = ABSOLUTE(.); - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - /* Send .iram0 code to iram */ - .iram0.vectors : ALIGN(4) + .noinit (NOLOAD): { - /* Vectors go to IRAM */ - _init_start = ABSOLUTE(.); - /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ - . = 0x0; - KEEP(*(.WindowVectors.text)); - . = 0x180; - KEEP(*(.Level2InterruptVector.text)); - . = 0x1c0; - KEEP(*(.Level3InterruptVector.text)); - . = 0x200; - KEEP(*(.Level4InterruptVector.text)); - . = 0x240; - KEEP(*(.Level5InterruptVector.text)); - . = 0x280; - KEEP(*(.DebugExceptionVector.text)); - . = 0x2c0; - KEEP(*(.NMIExceptionVector.text)); - . = 0x300; - KEEP(*(.KernelExceptionVector.text)); - . = 0x340; - KEEP(*(.UserExceptionVector.text)); - . = 0x3C0; - KEEP(*(.DoubleExceptionVector.text)); - . = 0x400; - *(.*Vector.literal) - - *(.UserEnter.literal); - *(.UserEnter.text); - . = ALIGN (16); - *(.entry.text) - *(.init.literal) - *(.init) - _init_end = ABSOLUTE(.); - - /* This goes here, not at top of linker script, so addr2line finds it last, - * and uses it in preference to the first symbol in IRAM - */ - _iram_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram_loader.text : - { - . = ALIGN (16); - _loader_text_start = ABSOLUTE(.); - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ - *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_flash_config_esp32.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_init_common.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libzephyr.a:bootloader_efuse_esp32.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) - *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api_key_esp32.*(.literal .text .literal.* .text.*) - *libzephyr.a:app_cpu_start.*(.literal .text .literal.* .text.*) - *esp_mcuboot.*(.literal .text .literal.* .text.*) - *esp_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) - - *(.fini.literal) - *(.fini) - *(.gnu.version) - _loader_text_end = ABSOLUTE(.); - } > iram_loader_seg - - SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) - { - /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); - *(.iram1 .iram1.*) - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - - . = ALIGN(4); - _iram_text_end = ABSOLUTE(.); - _iram_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + . = ALIGN(8); + *(.noinit) + *(.noinit.*) + . = ALIGN(8) ; + } > dram_seg /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + .bss (NOLOAD): { . = ALIGN (8); _bss_start = ABSOLUTE(.); /* required by bluetooth library */ __bss_start = ABSOLUTE(.); - _btdm_bss_start = ABSOLUTE(.); - *libbtdm_app.a:(.bss .bss.* COMMON) - . = ALIGN (4); - _btdm_bss_end = ABSOLUTE(.); - - /* Buffer for system heap should be placed in dram_seg */ - *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap) - *(.dynsbss) *(.sbss) *(.sbss.*) @@ -293,35 +266,9 @@ SECTIONS __bss_end = ABSOLUTE(.); _bss_end = ABSOLUTE(.); _end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) + } > dram_seg - ASSERT(((__bss_end - ORIGIN(RAMABLE_REGION)) <= LENGTH(RAMABLE_REGION)), - "DRAM segment data does not fit.") - - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN (8); - *(.noinit) - *(.noinit.*) - . = ALIGN (8); - } GROUP_LINK_IN(RAMABLE_REGION_1) - - .flash.text : ALIGN(IROM_SEG_ALIGN) - { - _stext = .; - _text_start = ABSOLUTE(.); - - *(.literal .text .literal.* .text.*) - . = ALIGN(4); - _text_end = ABSOLUTE(.); - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) + ASSERT(((__bss_end - ORIGIN(dram_seg)) <= LENGTH(dram_seg)), "DRAM segment data does not fit.") #include @@ -362,8 +309,4 @@ SECTIONS #ifdef CONFIG_GEN_ISR_TABLES #include #endif - } - -ASSERT(((_iram_end - ORIGIN(IRAM_REGION)) <= LENGTH(IRAM_REGION)), - "IRAM0 segment data does not fit.") diff --git a/soc/espressif/esp32/memory.h b/soc/espressif/esp32/memory.h new file mode 100644 index 00000000000..b229132b12c --- /dev/null +++ b/soc/espressif/esp32/memory.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/* SRAM0 (64k+128k) instruction cache+memory */ +#define SRAM0_IRAM_START 0x40070000 +#define SRAM0_CACHE_SIZE 0x10000 +#define SRAM0_SIZE 0x30000 + +/* SRAM1 (128k) instruction/data memory */ +#define SRAM1_IRAM_START 0x400a0000 +#define SRAM1_DRAM_START 0x3ffe0000 +#define SRAM1_SIZE 0x20000 +#define SRAM1_DRAM_PROAPP_PRIV_SIZE 0x8000 +#define SRAM1_DRAM_USABLE_START 0x3ffe8000 /* Can be optimised - 0x3ffe5230 (?) */ +#define SRAM1_USABLE_SIZE (0x40000000 - SRAM1_DRAM_USABLE_START) + +/* SRAM2 (200k) data memory */ +#define SRAM2_DRAM_START 0x3ffae000 +#define SRAM2_SIZE 0x32000 +#define SRAM2_DRAM_SHM_PRIV_SIZE 0x2000 +#define SRAM2_DRAM_USABLE_START 0x3ffb0000 +#define SRAM2_USABLE_SIZE (SRAM1_DRAM_START - SRAM2_DRAM_USABLE_START) + +/** Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32 ROM static data usage is as follows: + * - 0x3ffae000 - 0x3ffb0000 (Reserved: data memory for ROM functions) + * - 0x3ffb0000 - 0x3ffe0000 (RAM bank 1 for application usage) + * - 0x3ffe0000 - 0x3ffe0440 (Reserved: data memory for ROM PRO CPU) + * - 0x3ffe3f20 - 0x3ffe4350 (Reserved: data memory for ROM APP CPU) + * - 0x3ffe4350 - 0x3ffe5230 (BT shm buffers) + * - 0x3ffe8000 - 0x3fffffff (RAM bank 2 for application usage) + */ + +#define DRAM1_PROCPU_RESERVED_START 0x3ffe0000 +#define DRAM1_APPCPU_RESERVED_START 0x3ffe3f20 +#define DRAM1_BT_SHM_BUFFERS_START 0x3ffe4350 +#define DRAM1_BT_SHM_BUFFERS_END 0x3ffe5230 + +/* Conversion beween IRAM and DRAM in SRAM1 memory */ +#define SRAM1_IRAM_DRAM_CALC(addr_iram) \ + (SRAM1_SIZE - ((addr_iram) - SRAM1_IRAM_START) + SRAM1_DRAM_START) +#define SRAM1_DRAM_IRAM_CALC(addr_dram) \ + (SRAM1_SIZE - ((addr_dram) - SRAM1_DRAM_START) + SRAM1_IRAM_START) + +/* For safety margin between bootloader data section and startup stacks */ +#define BOOTLOADER_DRAM_SEG_LEN 0x6400 +#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x4000 +#define BOOTLOADER_IRAM_SEG_LEN 0x9500 + +/* Start of the lower region is determined by region size and the end of the higher region */ +#define BOOTLOADER_DRAM_SEG_START 0x3fff0000 +#define BOOTLOADER_DRAM_SEG_END (BOOTLOADER_DRAM_SEG_START + BOOTLOADER_DRAM_SEG_LEN) +#define BOOTLOADER_IRAM_LOADER_SEG_START 0x40078000 +/* TODO: It should be possible to have this @ 0x40080400 + * but due a bug we need to use different memory location. + */ +#define BOOTLOADER_IRAM_SEG_START 0x400a0000 + +/* Flash */ +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x400000 +#endif + +/* Cached memories */ +#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE +#define IROM_SEG_ORG 0x400d0000 +#define IROM_SEG_LEN (FLASH_SIZE - 0x1000) +#define DROM_SEG_ORG 0x3f400000 +#define DROM_SEG_LEN (FLASH_SIZE - 0x1000) + +/* AMP: TODO utilise memory for APPCPU */ +#ifndef CONFIG_SOC_ESP32_PROCPU +#define APPCPU_IRAM_SIZE 0x20000 +#else +#define APPCPU_IRAM_SIZE 0x8000 +#endif diff --git a/soc/espressif/esp32/soc.c b/soc/espressif/esp32/soc.c index 280b8da3a6e..42b5e7bb399 100644 --- a/soc/espressif/esp32/soc.c +++ b/soc/espressif/esp32/soc.c @@ -97,7 +97,7 @@ void IRAM_ATTR esp_start_appcpu(void) * Zephyr is being booted by the Espressif bootloader. With it, the C stack * is already set up. */ -void __attribute__((section(".iram1"))) __esp_platform_start(void) +void IRAM_ATTR __esp_platform_start(void) { extern uint32_t _init_start; @@ -129,12 +129,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) esp_reset_reason_init(); -#ifdef CONFIG_MCUBOOT - /* MCUboot early initialisation. */ - if (bootloader_init()) { - abort(); - } -#else +#ifndef CONFIG_MCUBOOT /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check * on startup sequence related issues in application. Hence disable that * as we are about to start Zephyr environment. @@ -187,7 +182,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); -#endif +#endif /* CONFIG_ESP_SPIRAM */ /* Scheduler is not started at this point. Hence, guard functions * must be initialized after esp_spiram_init_cache which internally @@ -198,7 +193,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) spi_flash_guard_set(&g_flash_guard_default_ops); #endif -#endif /* CONFIG_MCUBOOT */ +#endif /* !CONFIG_MCUBOOT */ esp_intr_initialize(); From c0866030ebc9c0588eb349de34eb96af5317161e Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Tue, 19 Mar 2024 18:20:30 +0100 Subject: [PATCH 1999/2402] boards: Update ESP32 related documentation Update the note on the booting method for all ESP32 related boards. Signed-off-by: Marek Matej --- .../esp32_devkitc_wroom/doc/index.rst | 88 ++++++++++++++++++- .../esp32_devkitc_wrover/doc/index.rst | 13 +-- .../esp32_ethernet_kit/doc/index.rst | 13 +-- .../espressif/esp32c3_devkitm/doc/index.rst | 13 +-- boards/espressif/esp32s2_saola/doc/index.rst | 13 +-- .../espressif/esp32s3_devkitm/doc/index.rst | 13 +-- boards/espressif/esp_wrover_kit/doc/index.rst | 13 +-- .../esp32s2_franzininho/doc/index.rst | 13 +-- .../heltec_wifi_lora32_v2/doc/index.rst | 13 +-- .../doc/index.rst | 13 +-- .../luatos/esp32c3_luatos_core/doc/index.rst | 13 +-- .../luatos/esp32s3_luatos_core/doc/index.rst | 13 +-- boards/olimex/olimex_esp32_evb/doc/index.rst | 13 +-- boards/others/icev_wireless/doc/index.rst | 13 +-- boards/seeed/xiao_esp32c3/doc/index.rst | 13 +-- boards/seeed/xiao_esp32s3/doc/index.rst | 13 +-- boards/vcc-gnd/yd_esp32/doc/index.rst | 13 +-- 17 files changed, 214 insertions(+), 82 deletions(-) diff --git a/boards/espressif/esp32_devkitc_wroom/doc/index.rst b/boards/espressif/esp32_devkitc_wroom/doc/index.rst index 7b0d7d8964c..ec1248da38e 100644 --- a/boards/espressif/esp32_devkitc_wroom/doc/index.rst +++ b/boards/espressif/esp32_devkitc_wroom/doc/index.rst @@ -115,7 +115,91 @@ below to retrieve those files. It is recommended running the command above after :file:`west update`. Building & Flashing -------------------- +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp_wrover_kit + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -149,7 +233,7 @@ message in the monitor: Hello World! esp32_devkitc_wroom Debugging ---------- +********* ESP32-DEVKITC-WROOM support on OpenOCD is available upstream as of version 0.12.0. Download and install OpenOCD from `OpenOCD`_. diff --git a/boards/espressif/esp32_devkitc_wrover/doc/index.rst b/boards/espressif/esp32_devkitc_wrover/doc/index.rst index 26f3a82e011..1f66f3da8a9 100644 --- a/boards/espressif/esp32_devkitc_wrover/doc/index.rst +++ b/boards/espressif/esp32_devkitc_wrover/doc/index.rst @@ -117,12 +117,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/espressif/esp32_ethernet_kit/doc/index.rst b/boards/espressif/esp32_ethernet_kit/doc/index.rst index fb0bd9aa425..2f8ff821aad 100644 --- a/boards/espressif/esp32_ethernet_kit/doc/index.rst +++ b/boards/espressif/esp32_ethernet_kit/doc/index.rst @@ -438,12 +438,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/espressif/esp32c3_devkitm/doc/index.rst b/boards/espressif/esp32c3_devkitm/doc/index.rst index 379d2c31065..c2d6551170c 100644 --- a/boards/espressif/esp32c3_devkitm/doc/index.rst +++ b/boards/espressif/esp32c3_devkitm/doc/index.rst @@ -92,12 +92,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/espressif/esp32s2_saola/doc/index.rst b/boards/espressif/esp32s2_saola/doc/index.rst index b329b45f682..1e7c1627fd1 100644 --- a/boards/espressif/esp32s2_saola/doc/index.rst +++ b/boards/espressif/esp32s2_saola/doc/index.rst @@ -88,12 +88,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/espressif/esp32s3_devkitm/doc/index.rst b/boards/espressif/esp32s3_devkitm/doc/index.rst index 5405100f364..abef4294733 100644 --- a/boards/espressif/esp32s3_devkitm/doc/index.rst +++ b/boards/espressif/esp32s3_devkitm/doc/index.rst @@ -137,12 +137,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/espressif/esp_wrover_kit/doc/index.rst b/boards/espressif/esp_wrover_kit/doc/index.rst index 06203863505..521307376a0 100644 --- a/boards/espressif/esp_wrover_kit/doc/index.rst +++ b/boards/espressif/esp_wrover_kit/doc/index.rst @@ -503,12 +503,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/franzininho/esp32s2_franzininho/doc/index.rst b/boards/franzininho/esp32s2_franzininho/doc/index.rst index de0b2c8b1b7..54de95ecb40 100644 --- a/boards/franzininho/esp32s2_franzininho/doc/index.rst +++ b/boards/franzininho/esp32s2_franzininho/doc/index.rst @@ -54,12 +54,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst index 07355a6d70b..b97a9980512 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst +++ b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst @@ -42,12 +42,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst index 987eeb9f0f1..85470571981 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst +++ b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst @@ -156,12 +156,15 @@ below to retrieve those files. Programming and Debugging ************************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/luatos/esp32c3_luatos_core/doc/index.rst b/boards/luatos/esp32c3_luatos_core/doc/index.rst index beaf0d1e85b..7b6bbacf982 100644 --- a/boards/luatos/esp32c3_luatos_core/doc/index.rst +++ b/boards/luatos/esp32c3_luatos_core/doc/index.rst @@ -110,12 +110,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/luatos/esp32s3_luatos_core/doc/index.rst b/boards/luatos/esp32s3_luatos_core/doc/index.rst index 4921e11e915..94bc0f685d3 100644 --- a/boards/luatos/esp32s3_luatos_core/doc/index.rst +++ b/boards/luatos/esp32s3_luatos_core/doc/index.rst @@ -136,12 +136,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/olimex/olimex_esp32_evb/doc/index.rst b/boards/olimex/olimex_esp32_evb/doc/index.rst index b667547f859..bcfc8a3c346 100644 --- a/boards/olimex/olimex_esp32_evb/doc/index.rst +++ b/boards/olimex/olimex_esp32_evb/doc/index.rst @@ -111,12 +111,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/others/icev_wireless/doc/index.rst b/boards/others/icev_wireless/doc/index.rst index a931bb33da7..5484924e8d6 100644 --- a/boards/others/icev_wireless/doc/index.rst +++ b/boards/others/icev_wireless/doc/index.rst @@ -98,12 +98,15 @@ incredibly easy 🎉 following the steps below. Building and Flashing ********************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/seeed/xiao_esp32c3/doc/index.rst b/boards/seeed/xiao_esp32c3/doc/index.rst index 11d5109b3cf..dc86a6c20ca 100644 --- a/boards/seeed/xiao_esp32c3/doc/index.rst +++ b/boards/seeed/xiao_esp32c3/doc/index.rst @@ -80,12 +80,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/seeed/xiao_esp32s3/doc/index.rst b/boards/seeed/xiao_esp32s3/doc/index.rst index 1880e6ff9a4..bbb1bf528ae 100644 --- a/boards/seeed/xiao_esp32s3/doc/index.rst +++ b/boards/seeed/xiao_esp32s3/doc/index.rst @@ -96,12 +96,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/vcc-gnd/yd_esp32/doc/index.rst b/boards/vcc-gnd/yd_esp32/doc/index.rst index 890c3de6855..433c1ac0c30 100644 --- a/boards/vcc-gnd/yd_esp32/doc/index.rst +++ b/boards/vcc-gnd/yd_esp32/doc/index.rst @@ -117,12 +117,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== From f23d06e344ab7b6a0019ec31d2b8171b6442356a Mon Sep 17 00:00:00 2001 From: Marcio Ribeiro Date: Tue, 19 Sep 2023 14:57:44 -0300 Subject: [PATCH 2000/2402] boards: esp32s2_devkitc: initial board support Initial board files created to support the esp32s2_devkitc board. Signed-off-by: Marcio Ribeiro --- .../esp32s2_devkitc/Kconfig.defconfig | 12 + .../esp32s2_devkitc/Kconfig.esp32s2_devkitc | 5 + .../esp32s2_devkitc/Kconfig.sysbuild | 10 + boards/espressif/esp32s2_devkitc/board.cmake | 9 + boards/espressif/esp32s2_devkitc/board.yml | 5 + .../espressif/esp32s2_devkitc/doc/index.rst | 249 ++++++++++++++++++ .../esp32s2_devkitc-pinctrl.dtsi | 68 +++++ .../esp32s2_devkitc/esp32s2_devkitc.dts | 165 ++++++++++++ .../esp32s2_devkitc/esp32s2_devkitc.yaml | 26 ++ .../esp32s2_devkitc/esp32s2_devkitc_defconfig | 10 + .../esp32s2_devkitc/support/openocd.cfg | 4 + 11 files changed, 563 insertions(+) create mode 100644 boards/espressif/esp32s2_devkitc/Kconfig.defconfig create mode 100644 boards/espressif/esp32s2_devkitc/Kconfig.esp32s2_devkitc create mode 100644 boards/espressif/esp32s2_devkitc/Kconfig.sysbuild create mode 100644 boards/espressif/esp32s2_devkitc/board.cmake create mode 100644 boards/espressif/esp32s2_devkitc/board.yml create mode 100644 boards/espressif/esp32s2_devkitc/doc/index.rst create mode 100644 boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi create mode 100644 boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts create mode 100644 boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml create mode 100644 boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig create mode 100644 boards/espressif/esp32s2_devkitc/support/openocd.cfg diff --git a/boards/espressif/esp32s2_devkitc/Kconfig.defconfig b/boards/espressif/esp32s2_devkitc/Kconfig.defconfig new file mode 100644 index 00000000000..03bfd65b195 --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ESP32S2 DevKitC board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config ENTROPY_GENERATOR + default y + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 32768 if WIFI + default 4096 diff --git a/boards/espressif/esp32s2_devkitc/Kconfig.esp32s2_devkitc b/boards/espressif/esp32s2_devkitc/Kconfig.esp32s2_devkitc new file mode 100644 index 00000000000..97dca607bf0 --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/Kconfig.esp32s2_devkitc @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S2_DEVKITC + select SOC_ESP32S2_SOLO_N4R2 diff --git a/boards/espressif/esp32s2_devkitc/Kconfig.sysbuild b/boards/espressif/esp32s2_devkitc/Kconfig.sysbuild new file mode 100644 index 00000000000..8d3acb9e11d --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/espressif/esp32s2_devkitc/board.cmake b/boards/espressif/esp32s2_devkitc/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/espressif/esp32s2_devkitc/board.yml b/boards/espressif/esp32s2_devkitc/board.yml new file mode 100644 index 00000000000..b3d62e88686 --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s2_devkitc + vendor: espressif + socs: + - name: esp32s2 diff --git a/boards/espressif/esp32s2_devkitc/doc/index.rst b/boards/espressif/esp32s2_devkitc/doc/index.rst new file mode 100644 index 00000000000..a51e904fe6f --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/doc/index.rst @@ -0,0 +1,249 @@ +.. _esp32s2_devkitc: + +ESP32-S2 +######## + +Overview +******** + +ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be secure and +cost-effective, with a high performance and a rich set of IO capabilities. [1]_ + +The features include the following: + +- RSA-3072-based secure boot +- AES-XTS-256-based flash encryption +- Protected private key and device secrets from software access +- Cryptographic accelerators for enhanced performance +- Protection against physical fault injection attacks +- Various peripherals: + + - 43x programmable GPIOs + - 14x configurable capacitive touch GPIOs + - USB OTG + - LCD interface + - camera interface + - SPI + - I2S + - UART + - ADC + - DAC + - LED PWM with up to 8 channels + +Supported Features +================== + +Current Zephyr's ESP32-S2-devkitc board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32s2_devkitc + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_devkitc + :goals: build + +The usual ``flash`` target will work with the ``esp32s2_devkitc`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_devkitc + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s2_devkitc + +Debugging +********* + +ESP32-S2 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +The following table shows the pin mapping between ESP32-S2 board and JTAG interface. + ++---------------+-----------+ +| ESP32 pin | JTAG pin | ++===============+===========+ +| MTDO / GPIO40 | TDO | ++---------------+-----------+ +| MTDI / GPIO41 | TDI | ++---------------+-----------+ +| MTCK / GPIO39 | TCK | ++---------------+-----------+ +| MTMS / GPIO42 | TMS | ++---------------+-----------+ + +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S2`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_devkitc + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_devkitc + :goals: debug + +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html + + +References +********** + +.. [1] https://www.espressif.com/en/products/socs/esp32-s2 +.. _ESP32-S2 DevKitC User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-s2-devkitc-1.html +.. _ESP32S2 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf +.. _ESP32S2 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi new file mode 100644 index 00000000000..756aaf9b5b7 --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + +}; diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts new file mode 100644 index 00000000000..25b1c599c57 --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "esp32s2_devkitc-pinctrl.dtsi" +#include +#include + +/ { + model = "Espressif ESP32S2_DevKitC"; + compatible = "espressif,esp32s2"; + + aliases { + sw0 = &user_button; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: user_button { + label = "BOOT"; + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + + +&flash0 { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; + +&wdt0 { + status = "okay"; +}; diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml new file mode 100644 index 00000000000..482d8ad5ec2 --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml @@ -0,0 +1,26 @@ +identifier: esp32s2_devkitc +name: ESP32-S2 DevKitC +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - adc + - dac + - gpio + - i2c + - watchdog + - uart + - nvs + - pwm + - spi + - counter + - entropy + - input + - can + - dma +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig new file mode 100644 index 00000000000..5476839e2ba --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/espressif/esp32s2_devkitc/support/openocd.cfg b/boards/espressif/esp32s2_devkitc/support/openocd.cfg new file mode 100644 index 00000000000..f75d53b0b34 --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/support/openocd.cfg @@ -0,0 +1,4 @@ +set ESP_RTOS none + +source [find interface/ftdi/esp32s2_kaluga_v1.cfg] +source [find target/esp32s2.cfg] From f1d174e0d3a4957e7fbf29c2448374f8b567b4f9 Mon Sep 17 00:00:00 2001 From: Ping Wang Date: Mon, 19 Feb 2024 09:23:44 +0100 Subject: [PATCH 2001/2402] Bluetooth: Audio: broadcast assistant sync to PA broadcast_audio_assistant application sync to PA and obtain the correct subgroup information used by BASS. Signed-off-by: Ping Wang --- .../broadcast_audio_assistant/prj.conf | 2 + .../broadcast_audio_assistant/src/main.c | 207 ++++++++++++++++-- 2 files changed, 188 insertions(+), 21 deletions(-) diff --git a/samples/bluetooth/broadcast_audio_assistant/prj.conf b/samples/bluetooth/broadcast_audio_assistant/prj.conf index 4cd572d858f..b4ae2dc154a 100644 --- a/samples/bluetooth/broadcast_audio_assistant/prj.conf +++ b/samples/bluetooth/broadcast_audio_assistant/prj.conf @@ -11,4 +11,6 @@ CONFIG_BT_CTLR_SCAN_DATA_LEN_MAX=191 CONFIG_BT_TINYCRYPT_ECC=y CONFIG_BT_EXT_ADV=y +CONFIG_BT_BAP_BASS_MAX_SUBGROUPS=2 CONFIG_BT_BAP_BROADCAST_ASSISTANT=y +CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE=255 diff --git a/samples/bluetooth/broadcast_audio_assistant/src/main.c b/samples/bluetooth/broadcast_audio_assistant/src/main.c index 560e6d1c1fa..3c8bdf1de69 100644 --- a/samples/bluetooth/broadcast_audio_assistant/src/main.c +++ b/samples/bluetooth/broadcast_audio_assistant/src/main.c @@ -17,7 +17,8 @@ #include #define NAME_LEN 30 - +#define PA_SYNC_SKIP 5 +#define PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO 20 /* Set the timeout relative to interval */ /* Broadcast IDs are 24bit, so this is out of valid range */ #define INVALID_BROADCAST_ID 0xFFFFFFFFU @@ -39,15 +40,23 @@ static uint32_t selected_broadcast_id; static uint8_t selected_sid; static uint16_t selected_pa_interval; static bt_addr_le_t selected_addr; +static struct bt_le_per_adv_sync *pa_sync; +static uint8_t received_base[UINT8_MAX]; +static uint8_t received_base_size; +static struct bt_bap_bass_subgroup + bass_subgroups[CONFIG_BT_BAP_BASS_MAX_SUBGROUPS]; static bool scanning_for_broadcast_source; +static struct k_mutex base_store_mutex; static K_SEM_DEFINE(sem_source_discovered, 0, 1); static K_SEM_DEFINE(sem_sink_discovered, 0, 1); static K_SEM_DEFINE(sem_sink_connected, 0, 1); static K_SEM_DEFINE(sem_sink_disconnected, 0, 1); static K_SEM_DEFINE(sem_security_updated, 0, 1); static K_SEM_DEFINE(sem_bass_discovered, 0, 1); +static K_SEM_DEFINE(sem_pa_synced, 0, 1); +static K_SEM_DEFINE(sem_received_base_subgroups, 0, 1); static bool device_found(struct bt_data *data, void *user_data) { @@ -121,6 +130,88 @@ static bool device_found(struct bt_data *data, void *user_data) } } +static bool base_store(struct bt_data *data, void *user_data) +{ + const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(data); + uint8_t base_size; + int base_subgroup_count; + + /* Base is NULL if the data does not contain a valid BASE */ + if (base == NULL) { + return true; + } + + /* Can not fit all the received subgroups with the size CONFIG_BT_BAP_BASS_MAX_SUBGROUPS */ + base_subgroup_count = bt_bap_base_get_subgroup_count(base); + if (base_subgroup_count < 0 || base_subgroup_count > CONFIG_BT_BAP_BASS_MAX_SUBGROUPS) { + printk("Got invalid subgroup count: %d\n", base_subgroup_count); + return true; + } + + base_size = data->data_len - BT_UUID_SIZE_16; /* the BASE comes after the UUID */ + + /* Compare BASE and copy if different */ + k_mutex_lock(&base_store_mutex, K_FOREVER); + if (base_size != received_base_size || memcmp(base, received_base, base_size) != 0) { + (void)memcpy(received_base, base, base_size); + received_base_size = base_size; + } + k_mutex_unlock(&base_store_mutex); + + /* Stop parsing */ + k_sem_give(&sem_received_base_subgroups); + return false; +} + +static void pa_recv(struct bt_le_per_adv_sync *sync, + const struct bt_le_per_adv_sync_recv_info *info, + struct net_buf_simple *buf) +{ + bt_data_parse(buf, base_store, NULL); +} + +static bool add_pa_sync_base_subgroup_bis_cb(const struct bt_bap_base_subgroup_bis *bis, + void *user_data) +{ + struct bt_bap_bass_subgroup *subgroup_param = user_data; + + subgroup_param->bis_sync |= BIT(bis->index); + + return true; +} + +static bool add_pa_sync_base_subgroup_cb(const struct bt_bap_base_subgroup *subgroup, + void *user_data) +{ + struct bt_bap_broadcast_assistant_add_src_param *param = user_data; + struct bt_bap_bass_subgroup *subgroup_param; + uint8_t *data; + int ret; + + ret = bt_bap_base_get_subgroup_codec_meta(subgroup, &data); + if (ret < 0) { + return false; + } + + subgroup_param = param->subgroups; + + if (ret > ARRAY_SIZE(subgroup_param->metadata)) { + printk("Cannot fit %d octets into subgroup param with size %zu", ret, + ARRAY_SIZE(subgroup_param->metadata)); + return false; + } + + ret = bt_bap_base_subgroup_foreach_bis(subgroup, add_pa_sync_base_subgroup_bis_cb, + subgroup_param); + if (ret < 0) { + return false; + } + + param->num_subgroups++; + + return true; +} + static bool is_substring(const char *substr, const char *str) { const size_t str_len = strlen(str); @@ -143,6 +234,41 @@ static bool is_substring(const char *substr, const char *str) return false; } +static uint16_t interval_to_sync_timeout(uint16_t pa_interval) +{ + uint16_t pa_timeout; + + if (pa_interval == BT_BAP_PA_INTERVAL_UNKNOWN) { + /* Use maximum value to maximize chance of success */ + pa_timeout = BT_GAP_PER_ADV_MAX_TIMEOUT; + } else { + uint32_t interval_ms; + uint32_t timeout; + + /* Add retries and convert to unit in 10's of ms */ + interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(pa_interval); + timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10; + + /* Enforce restraints */ + pa_timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT); + } + + return pa_timeout; +} + +static int pa_sync_create(void) +{ + struct bt_le_per_adv_sync_param create_params = {0}; + + bt_addr_le_copy(&create_params.addr, &selected_addr); + create_params.options = BT_LE_PER_ADV_SYNC_OPT_FILTER_DUPLICATE; + create_params.sid = selected_sid; + create_params.skip = PA_SYNC_SKIP; + create_params.timeout = interval_to_sync_timeout(selected_pa_interval); + + return bt_le_per_adv_sync_create(&create_params, &pa_sync); +} + static void scan_recv_cb(const struct bt_le_scan_recv_info *info, struct net_buf_simple *ad) { @@ -168,6 +294,7 @@ static void scan_recv_cb(const struct bt_le_scan_recv_info *info, printk(" Broadcast Name: %s\n", sr_info.broadcast_name); printk(" Broadcast ID: 0x%06x\n\n", sr_info.broadcast_id); +#if defined(CONFIG_SELECT_SOURCE_NAME) if (strlen(CONFIG_SELECT_SOURCE_NAME) > 0U) { /* Compare names with CONFIG_SELECT_SOURCE_NAME */ if (is_substring(CONFIG_SELECT_SOURCE_NAME, sr_info.bt_name) || @@ -180,6 +307,7 @@ static void scan_recv_cb(const struct bt_le_scan_recv_info *info, return; } } +#endif /* CONFIG_SELECT_SOURCE_NAME */ err = bt_le_scan_stop(); if (err != 0) { @@ -199,6 +327,9 @@ static void scan_recv_cb(const struct bt_le_scan_recv_info *info, bt_addr_le_copy(&selected_addr, info->addr); k_sem_give(&sem_source_discovered); + + printk("Attempting to PA sync to the broadcaster with id 0x%06X\n", + selected_broadcast_id); } } else { /* Scan for and connect to Broadcast Sink */ @@ -369,11 +500,27 @@ static void bap_broadcast_assistant_add_src_cb(struct bt_conn *conn, int err) } } +static void pa_sync_synced_cb(struct bt_le_per_adv_sync *sync, + struct bt_le_per_adv_sync_synced_info *info) +{ + if (sync == pa_sync) { + printk("PA sync %p synced for broadcast sink with broadcast ID 0x%06X\n", sync, + selected_broadcast_id); + + k_sem_give(&sem_pa_synced); + } +} + static struct bt_bap_broadcast_assistant_cb ba_cbs = { .discover = bap_broadcast_assistant_discover_cb, .add_src = bap_broadcast_assistant_add_src_cb, }; +static struct bt_le_per_adv_sync_cb pa_synced_cb = { + .synced = pa_sync_synced_cb, + .recv = pa_recv, +}; + static void reset(void) { printk("\n\nReset...\n\n"); @@ -390,6 +537,8 @@ static void reset(void) k_sem_reset(&sem_sink_disconnected); k_sem_reset(&sem_security_updated); k_sem_reset(&sem_bass_discovered); + k_sem_reset(&sem_pa_synced); + k_sem_reset(&sem_received_base_subgroups); } BT_CONN_CB_DEFINE(conn_callbacks) = { @@ -401,7 +550,6 @@ BT_CONN_CB_DEFINE(conn_callbacks) = { int main(void) { int err; - struct bt_bap_bass_subgroup subgroup = { 0 }; struct bt_bap_broadcast_assistant_add_src_param param = { 0 }; err = bt_enable(NULL); @@ -412,8 +560,11 @@ int main(void) printk("Bluetooth initialized\n"); - bt_le_scan_cb_register(&scan_callbacks); bt_bap_broadcast_assistant_register_cb(&ba_cbs); + bt_le_per_adv_sync_cb_register(&pa_synced_cb); + bt_le_scan_cb_register(&scan_callbacks); + + k_mutex_init(&base_store_mutex); while (true) { scan_for_broadcast_sink(); @@ -467,31 +618,45 @@ int main(void) scan_for_broadcast_source(); - /* FIX NEEDED: It should be valid to assign BT_BAP_BIS_SYNC_NO_PREF - * to bis_sync, but currently (2024-01-30), the broadcast_audio_sink - * sample seems to reject it (err=19) while other sinks don't. - * - * Also, if the source contains more than one stream (e.g. stereo), - * some sinks have been observed to have issues. In this case, - * set only one bit in bis_sync, e.g. subgroup.bis_sync = BIT(1). - * - * When PA sync and BASE is parsed (see note in the scan_recv_cb function), - * the available bits can be used for proper selection. - */ - subgroup.bis_sync = BT_BAP_BIS_SYNC_NO_PREF; + printk("Scan stopped, attempting to PA sync to the broadcaster with id 0x%06X\n", + selected_broadcast_id); + err = pa_sync_create(); + if (err != 0) { + printk("Could not create Broadcast PA sync: %d, resetting\n", err); + return -ETIMEDOUT; + } + printk("Waiting for PA synced\n"); + err = k_sem_take(&sem_pa_synced, K_FOREVER); + if (err != 0) { + printk("sem_pa_synced timed out, resetting\n"); + return err; + } + + memset(bass_subgroups, 0, sizeof(bass_subgroups)); bt_addr_le_copy(¶m.addr, &selected_addr); param.adv_sid = selected_sid; param.pa_interval = selected_pa_interval; param.broadcast_id = selected_broadcast_id; param.pa_sync = true; + param.subgroups = bass_subgroups; - /* TODO: Obtain the and set the correct subgroup information. - * See above in the broadcast audio source discovery part - * of the scan_recv_cb function. - */ - param.num_subgroups = 1; - param.subgroups = &subgroup; + /* Wait to receive subgroups */ + err = k_sem_take(&sem_received_base_subgroups, K_FOREVER); + if (err != 0) { + printk("Failed to take sem_received_base_subgroups (err %d)\n", err); + return err; + } + + k_mutex_lock(&base_store_mutex, K_FOREVER); + err = bt_bap_base_foreach_subgroup((const struct bt_bap_base *)received_base, + add_pa_sync_base_subgroup_cb, ¶m); + k_mutex_unlock(&base_store_mutex); + + if (err < 0) { + printk("Could not add BASE to params %d\n", err); + continue; + } err = bt_bap_broadcast_assistant_add_src(broadcast_sink_conn, ¶m); if (err) { From ce52fafa23dbd1ee19ae238924fe6c4915e8fdae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Th=C3=A9o=20Battrel?= Date: Wed, 27 Mar 2024 10:46:00 +0100 Subject: [PATCH 2002/2402] doc: Bluetooth: Add section on L2CAP PDUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add terminology table and describe LE frame types and related Kconfig. Signed-off-by: Théo Battrel --- .../bluetooth/bluetooth-le-host.rst | 113 ++++++++++++++++++ .../bluetooth/img/l2cap_b_frame.drawio.svg | 4 + .../bluetooth/img/l2cap_k_frame.drawio.svg | 4 + .../bluetooth/img/l2cap_k_frame_1.drawio.svg | 4 + 4 files changed, 125 insertions(+) create mode 100644 doc/connectivity/bluetooth/img/l2cap_b_frame.drawio.svg create mode 100644 doc/connectivity/bluetooth/img/l2cap_k_frame.drawio.svg create mode 100644 doc/connectivity/bluetooth/img/l2cap_k_frame_1.drawio.svg diff --git a/doc/connectivity/bluetooth/bluetooth-le-host.rst b/doc/connectivity/bluetooth/bluetooth-le-host.rst index 26b21f8ca2b..3fad3425681 100644 --- a/doc/connectivity/bluetooth/bluetooth-le-host.rst +++ b/doc/connectivity/bluetooth/bluetooth-le-host.rst @@ -153,6 +153,119 @@ an application comes in direct contact with it only when using it in the so-called Connection-oriented Channels (CoC) mode. More information on this can be found in the :ref:`L2CAP API section `. +Terminology +----------- + +The definitions are from the Core Specification version 5.4, volume 3, part A +1.4. + +.. list-table:: + :header-rows: 1 + + * - Term + - Description + + * - Upper layer + - Layer above L2CAP, it exchanges data in form of SDUs. It may be an + application or a higher level protocol. + + * - Lower layer + - Layer below L2CAP, it exchanges data in form of PDUs (or fragments). It is + usually the HCI. + + * - Service Data Unit (SDU) + - Packet of data that L2CAP exchanges with the upper layer. + + This term is relevant only in Enhanced Retransmission mode, Streaming + mode, Retransmission mode and Flow Control Mode, not in Basic L2CAP mode. + + * - Protocol Data Unit (PDU) + - Packet of data containing L2CAP data. PDUs always start with Basic L2CAP + header. + + Types of PDUs for LE: :ref:`B-frames ` and + :ref:`K-frames `. + + Types of PDUs for BR/EDR: I-frames, S-frames, C-frames and G-frames. + + * - Maximum Transmission Unit (MTU) + - Maximum size of an SDU that the upper layer is capable of accepting. + + * - Maximum Payload Size (MPS) + - Maximum payload size that the L2CAP layer is capable of accepting. + + In Basic L2CAP mode, the MTU size is equal to MPS. In credit-based + channels without segmentation, the MTU is MPS minus 2. + + * - Basic L2CAP header + - Present at the beginning of each PDU. It contains two fields, the PDU + length and the Channel Identifier (CID). + +PDU Types +--------- + +.. _bluetooth_l2cap_b_frame: + +B-frame: Basic information frame +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +PDU used in Basic L2CAP mode. It contains the payload received from the upper +layer or delivered to the upper layer as its payload. + +.. image:: img/l2cap_b_frame.drawio.svg + :align: center + :width: 45% + :alt: Representation of a B-frame PDU. The PDU is split into two rectangles, + the first one being the L2CAP header, its size is 4 octets and its made + of the PDU length and the channel ID. The second rectangle represents + the information payload and its size is less or equal to MPS. + +.. _bluetooth_l2cap_k_frame: + +K-frame: Credit-based frame +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +PDU used in LE Credit Based Flow Control mode and Enhanced Credit Based Flow +Control mode. It contains a SDU segment and additional protocol information. + +.. image:: img/l2cap_k_frame_1.drawio.svg + :width: 45% + :alt: Representation of a starting K-frame PDU. The PDU is split into three + rectangles, the first one being the L2CAP header, its size is 4 octets + and its made of the PDU length and the channel ID. The second rectangle + represents the L2CAP SDU length, its size is 2 octets. The third + rectangle represents the information payload and its size is less or + equal to MPS minus 2 octets. The information payload contains the L2CAP + SDU. + +.. image:: img/l2cap_k_frame.drawio.svg + :align: right + :width: 45% + :alt: Representation of K-frames PDUs after the starting one. The PDU is split + into two rectangles, the first one being the L2CAP header, its size is 4 + octets and its made of the PDU length and the channel ID. The second + rectangle represents the information payload and its size is less or + equal to MPS. The information payload contains the L2CAP SDU. + +Relevant Kconfig +---------------- + +.. list-table:: + :header-rows: 1 + + * - Kconfig symbol + - Description + + * - :kconfig:option:`CONFIG_BT_BUF_ACL_RX_SIZE` + - Represents the MPS + + * - :kconfig:option:`CONFIG_BT_L2CAP_TX_MTU` + - Represents the L2CAP MTU + + * - :kconfig:option:`CONFIG_BT_L2CAP_DYNAMIC_CHANNEL` + - Enables LE Credit Based Flow Control and thus the stack may use + :ref:`K-frame ` PDUs + GATT ==== diff --git a/doc/connectivity/bluetooth/img/l2cap_b_frame.drawio.svg b/doc/connectivity/bluetooth/img/l2cap_b_frame.drawio.svg new file mode 100644 index 00000000000..fe1339030f2 --- /dev/null +++ b/doc/connectivity/bluetooth/img/l2cap_b_frame.drawio.svg @@ -0,0 +1,4 @@ + + + +
    L2CAP HDR
    (PDU length + channel ID)
    Information Payload
    B-frame PDU
    4 octets
    ≤ MPS
     \ No newline at end of file diff --git a/doc/connectivity/bluetooth/img/l2cap_k_frame.drawio.svg b/doc/connectivity/bluetooth/img/l2cap_k_frame.drawio.svg new file mode 100644 index 00000000000..fd94fd35c22 --- /dev/null +++ b/doc/connectivity/bluetooth/img/l2cap_k_frame.drawio.svg @@ -0,0 +1,4 @@ + + + +
    L2CAP HDR
    (PDU length + channel ID)
    Information Payload (L2CAP SDU)
    K-frame PDU (next ones)
    4 octets
    ≤ MPS
     \ No newline at end of file diff --git a/doc/connectivity/bluetooth/img/l2cap_k_frame_1.drawio.svg b/doc/connectivity/bluetooth/img/l2cap_k_frame_1.drawio.svg new file mode 100644 index 00000000000..2ff7c11d12b --- /dev/null +++ b/doc/connectivity/bluetooth/img/l2cap_k_frame_1.drawio.svg @@ -0,0 +1,4 @@ + + + +
    L2CAP HDR
    (PDU length + channel ID)
    Information Payload
    (L2CAP SDU)
    K-frame PDU (first one)
    4 octets
    ≤ MPS-2
    L2CAP SDU length
    2 octets
     \ No newline at end of file From c0700d98257b2a46001566a1cb87a622c97138ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Th=C3=A9o=20Battrel?= Date: Wed, 27 Mar 2024 10:43:58 +0100 Subject: [PATCH 2003/2402] Bluetooth: L2CAP: Reword K-frame comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The terminology was not following the Spec wording. Signed-off-by: Théo Battrel --- subsys/bluetooth/host/l2cap.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/subsys/bluetooth/host/l2cap.c b/subsys/bluetooth/host/l2cap.c index 0a736112a49..75e8bc396bd 100644 --- a/subsys/bluetooth/host/l2cap.c +++ b/subsys/bluetooth/host/l2cap.c @@ -3072,25 +3072,24 @@ static int bt_l2cap_dyn_chan_send(struct bt_l2cap_le_chan *le_chan, struct net_b return -EINVAL; } - /* Prepend SDU "header". + /* Prepend SDU length. * - * L2CAP LE CoC SDUs are segmented into PDUs and sent over so-called - * K-frames that each have their own L2CAP header (ie channel, PDU - * length). + * L2CAP LE CoC SDUs are segmented and put into K-frames PDUs which have + * their own L2CAP header (i.e. PDU length, channel id). * - * The SDU header is right before the data that will be segmented and is - * only present in the first segment/PDU. Here's an example: + * The SDU length is right before the data that will be segmented and is + * only present in the first PDU. Here's an example: * * Sent data payload of 50 bytes over channel 0x4040 with MPS of 30 bytes: - * First PDU / segment / K-frame: + * First PDU (K-frame): * | L2CAP K-frame header | K-frame payload | - * | PDU length | Channel ID | SDU header | SDU payload | - * | 30 | 0x4040 | 50 | 28 bytes of data | + * | PDU length | Channel ID | SDU length | SDU payload | + * | 0x001e | 0x4040 | 0x0032 | 28 bytes of data | * - * Second and last PDU / segment / K-frame: + * Second and last PDU (K-frame): * | L2CAP K-frame header | K-frame payload | * | PDU length | Channel ID | rest of SDU payload | - * | 22 | 0x4040 | 22 bytes of data | + * | 0x0016 | 0x4040 | 22 bytes of data | */ net_buf_push_le16(buf, sdu_len); From 2e7befe2407a07559cf589975aedd2dbaf4870a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Th=C3=A9o=20Battrel?= Date: Wed, 3 Apr 2024 13:22:03 +0200 Subject: [PATCH 2004/2402] Bluetooth: HCI: Reword `BT_BUF_ACL_*` description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some part of the descriptions were wrong. Also, the description of `BT_BUF_ACL_RX_SIZE` was too verbose and no longer needed with the updated L2CAP documentation. Signed-off-by: Théo Battrel --- subsys/bluetooth/common/Kconfig | 41 +++++++++++---------------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/subsys/bluetooth/common/Kconfig b/subsys/bluetooth/common/Kconfig index a5a21aece39..344823a88d1 100644 --- a/subsys/bluetooth/common/Kconfig +++ b/subsys/bluetooth/common/Kconfig @@ -14,13 +14,14 @@ config BT_BUF_ACL_TX_SIZE help Maximum supported ACL size of data packets sent from the Host to the Controller. This value does not include the HCI ACL header. - The Host will segment the data transmitted to the Controller so that - packets sent to the Controller will contain data up to this size. + In a combined build this value will be set in both the Host and the Controller. + In a Host-only build the Host will read the maximum ACL size supported by the Controller and use the smallest value supported by both the Host and the Controller. + The Host supports sending of larger L2CAP PDUs than the ACL size and will fragment L2CAP PDUs into ACL data packets. The Controller will return this value in the HCI LE Read Buffer @@ -60,37 +61,21 @@ config BT_BUF_ACL_RX_SIZE help Maximum support ACL size of data packets sent from the Controller to the Host. This value does not include the HCI ACL header. - In a combined Host and Controller build the buffer sizes in both the - Host and the Controller will use this value for buffer sizes, and - therefore Controller to Host flow Controller is not needed. + + In a combined Host and Controller build, both the + Host and the Controller will use this value for buffer sizes, making + Controller to Host flow control not strictly necessary. + In a Host only build with Controller to Host flow control enabled the Host will inform the Controller about the maximum ACL data size it can send by setting this value in the Host Buffer Size command. + If Controller to Host flow control is not enabled then the Controller - can assume the Host has infinite buffer size so this value should then - be set to something that is guaranteed the Controller will not exceed - or the data packets will be dropped. + can assume the Host has to receive and process ACL data faster than + the controller can produce it. + In a Controller only build this will determine the maximum ACL size that the Controller will send to the Host. - The Host supports reassembling of L2CAP PDUs from ACL data packets, - but the maximum supported L2CAP PDU size is limited by the maximum - supported ACL size. - This means the maximum L2CAP PDU MTU is restricted by the maximum ACL - size subtracting the 4 byte header of an L2CAP PDU. - When using L2CAP Connection oriented Channels without segmentation - then the L2CAP SDU MTU is also restricted by the maximum ACL size - subtracting the 4 Byte header of an L2CAP PDU plus the 2 byte header - of an L2CAP SDU. - - With Enhanced ATT enabled the minimum of 70 is needed to support the - minimum ATT_MTU of 64 octets in an L2CAP SDU without segmentation. - With SMP LE Secure Connections enabled the minimum of 69 is needed to - support the minimum SMP MTU of 65 octets (public key + opcode) in an - L2CAP PDU. - - An L2CAP PDU is also referred to as an L2CAP basic frame or B-frame. - An L2CAP SDU is also referred to as an L2CAP Credit-based frame or - K-frame. config BT_BUF_ACL_RX_COUNT int "Number of incoming ACL data buffers" @@ -102,9 +87,11 @@ config BT_BUF_ACL_RX_COUNT Host. In a combined Host and Controller build the buffers are shared and therefore Controller to Host flow control is not needed. + In a Host only build with Controller to Host flow control enabled the Host will inform the Controller about the maximum number of buffers by setting this value in the Host Buffer Size command. + When Controller to Host flow control is not enabled the Controller can assume that the Host has infinite amount of buffers. From 58030cc31c388c7983ab0d7b741b22a4674f3afa Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 14:45:36 +0100 Subject: [PATCH 2005/2402] Bluetooth: CAP: Shell: Stop all streams by default The cap_initiator unicast_stop command will now stop all streams by default, without supplying the "all" argument. Signed-off-by: Emil Gydesen --- doc/connectivity/bluetooth/api/shell/cap.rst | 2 +- subsys/bluetooth/audio/shell/cap_initiator.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/connectivity/bluetooth/api/shell/cap.rst b/doc/connectivity/bluetooth/api/shell/cap.rst index 54489ade793..aa5854442e6 100644 --- a/doc/connectivity/bluetooth/api/shell/cap.rst +++ b/doc/connectivity/bluetooth/api/shell/cap.rst @@ -86,7 +86,7 @@ The CAP initiator also supports broadcast audio as a source. (default 1)] [conns ( | all) (default 1)] unicast_list :Unicast list streams unicast_update :Unicast Update - unicast_stop :Unicast stop streams + unicast_stop :Unicast stop streams [stream [stream [stream...]]] (all by default) unicast_cancel :Unicast cancel current procedure Before being able to perform any stream operation, the device must also perform the diff --git a/subsys/bluetooth/audio/shell/cap_initiator.c b/subsys/bluetooth/audio/shell/cap_initiator.c index 813bff1a041..6da30a7fe17 100644 --- a/subsys/bluetooth/audio/shell/cap_initiator.c +++ b/subsys/bluetooth/audio/shell/cap_initiator.c @@ -453,7 +453,7 @@ static int cmd_cap_initiator_unicast_stop(const struct shell *sh, size_t argc, return -ENOEXEC; } - if (argc == 2 && strcmp(argv[1], "all") == 0) { + if (argc == 1) { for (size_t i = 0U; i < ARRAY_SIZE(unicast_streams); i++) { struct bt_cap_stream *stream = &unicast_streams[i].stream; struct bt_bap_ep_info ep_info; @@ -1332,7 +1332,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE( SHELL_CMD_ARG(unicast_update, NULL, "Unicast Update ", cmd_cap_initiator_unicast_update, 2, CAP_UNICAST_CLIENT_STREAM_COUNT), SHELL_CMD_ARG(unicast_stop, NULL, - "Unicast stop streams ", + "Unicast stop streams [stream [stream [stream...]]] (all by default)", cmd_cap_initiator_unicast_stop, 2, CAP_UNICAST_CLIENT_STREAM_COUNT), SHELL_CMD_ARG(unicast_cancel, NULL, "Unicast cancel current procedure", cmd_cap_initiator_unicast_cancel, 1, 0), From cf265631c11428c2b976f182d7a546ecc3ecd007 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Tue, 6 Feb 2024 23:16:55 +0900 Subject: [PATCH 2006/2402] boards: sheilds: Add RaspberryPi Pico to UNO FlexyPin Adapter Add "RaspberryPi Pico to UNO FlexyPin Adapter". It is a converter-PCB to Arduino UNO form-factor from Raspberry Pi Pico that is released in Open Source Hardware. Signed-off-by: TOKITA Hiroshi --- .../rpi_pico_uno_flexypin/Kconfig.shield | 5 + .../doc/img/rpi_pico_uno_flexypin.png | Bin 0 -> 100315 bytes .../rpi_pico_uno_flexypin/doc/index.rst | 94 ++++++++++++++++++ .../rpi_pico_uno_flexypin.overlay | 41 ++++++++ 4 files changed, 140 insertions(+) create mode 100644 boards/shields/rpi_pico_uno_flexypin/Kconfig.shield create mode 100644 boards/shields/rpi_pico_uno_flexypin/doc/img/rpi_pico_uno_flexypin.png create mode 100644 boards/shields/rpi_pico_uno_flexypin/doc/index.rst create mode 100644 boards/shields/rpi_pico_uno_flexypin/rpi_pico_uno_flexypin.overlay diff --git a/boards/shields/rpi_pico_uno_flexypin/Kconfig.shield b/boards/shields/rpi_pico_uno_flexypin/Kconfig.shield new file mode 100644 index 00000000000..4e385966d3f --- /dev/null +++ b/boards/shields/rpi_pico_uno_flexypin/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_RPI_PICO_UNO_FLEXYPIN + def_bool $(shields_list_contains,rpi_pico_uno_flexypin) diff --git a/boards/shields/rpi_pico_uno_flexypin/doc/img/rpi_pico_uno_flexypin.png b/boards/shields/rpi_pico_uno_flexypin/doc/img/rpi_pico_uno_flexypin.png new file mode 100644 index 0000000000000000000000000000000000000000..b146238eeb0b995a56ce1c3fc4d33c03829a5be8 GIT binary patch literal 100315 zcmeEtbx8c}1{x_E3=9kgSYBEU1_ssu_-jT%0*>&D zoLm9_2D~-ix~ds_fE=A2pjNi#AXhI(bC9{G6%+=>bJifL6g zhau#T!KbEnMSa3X9COSgcB<{I1ajP-DYC9!>KTbzi!qZkM9&~%PsYJKxj!f~o=#R8 zhF8-!J{=0Ho*GY4r1p~CY(-AiSM|pokm6yMLxzQq4 zzyx|1W+f%10+y2cM~8rJWcwuu%lE0^zke=KkkKVS0?klKxz&TZ9Ft!W_DWhYH~uto zo+aY3l2?02j<^^c5FZNj8jV zG+1D&@Q%teY@4ukzd|zDl0u+TGJR)Kk~_u%-O@3~~S( zXW7Qs&VVTHcf28onuDpt7$~@Z1oy|kOVjt?dFT9gGsBoBE0+NiFS?j5wLLurBgHdH zprVX)_k~~@!GvD+ymd~~>98R&izPEj&1@7Xh>kWP7=^@5LnSPX_?VQ5e#VvJ`WKe) z6MmbSvu4lNxpDaIe7By~zqC&1)kfOJ3Xi`)|#941v!itusPT zx_If2w4Kw_1#&$-e2z|Q)89omoso&XXXvDyX~kLd-y*C}{>VD-*<_vS-kYfQinUXl!a@?g}z7x3IDor9N%%rUqG=iBfCxLO39fQs$Oc^4`wo>fXv4 zrrtKDf@aj>VrU|sLVy7~b5~=Kr=6|6i;$-%^{fX{ypvr~iqYT{}mO8pk10+MoY zHV5&r@vw2Q%6MA2b5V<-fkd3mph9ZWvVS)Ld=sU%baizUVrTd8@L==cW^-`1VCNJR z6lCY%V&~#w1zNDWc-gxed$QWQ(EKs+HyhICE~d^_j;>Y?_MksDjZGZfTt%s=f%Bk$ zJfEE-1oBVw_AY<-0^kpJPh&@RPBsp9J3ID&y~4#+#vL&7_XqkvUg4qvEL3(ia~B6U zXH#<-cXNAJntwH6X8O5Gi=geQ-`PT;lF8`<9e{21ZzW>!2Xa#`?NjsRj{dqjFv?%qT z`wN*lm|B?${q>Pk5X!^NYi`UcV9v|S$^$hvW;GGu;bk?3@(A+ra+`8-8uR{(DX_hZ ztFgVQ`5#k&aW*T!j+neg)ei-|YR zR=}(@w*A+q`eVurFlAz5%45n4(6Mq~oB%uNprRHMe_@5&xw#Ked-~wO`SlOF7c)0w} zDGe(-b9GnaKmO$8=iuk!=jRdN7U1CF<`ejzMq1|1F2G#;W0jMGjhpAMGk*p~24OY=YD0Jw~mgNyZFTt?0Q_s+8a*)jgnTM_pE%^xCvHTah;2Dt8T z$AGO1*a_MHxfTB1Uw<~8|BpX^ABX>scK}TP_a^_5fB);Q|GMix^1y%8_`kF3zwY{v zJn$bi{_pJif95W<{{d6x_CN;Y0YD{dLECZwW+9m<%1OgK|M~scS(*eKL3NbZae;xs zb^Y@PyAGxF1P&s*f*~@$IT<|IC zhbgK{gCaCSmdf^M>K~t95xQ2}=pU9=*63?5>brU9`$*vzF$PoXV;|%o$V+->tt;O? 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z1Ar$&x}G|?vhwo42}c_(E;Wdogo1vBf1VGq&YqYoQ_AM|g6!p(8&09mUVOtjM8HDc ze|@jOYW-7|1^bV3J+j|c6setOiAwg=;f?PEjez*&q2wHu@qInm_3-7(D%|qx(M&g4 zd~L-NvN(?%q4=dQQS*Oskulg#hn7@0c-4@oCi@i_rO0%ifGjsDVS?y+nf@9-rb0Ya!E2`V-@XL!&xBh=oR#f{h zq3@pCEv4x-z2fDik!%+iZn_QDh3p07Z!1f5dJ27<=V-bWF}`ngx^E9!u72TcF7&Y_ zuvQGrDTCR$x8@4Kqc|TPo9P0vS4P-m+~C2BT7XG#+YD6xyNK+6UK1wW`G37;I#T<8 q{XPHl8f-Fz9r%0xzvr^SxO+F+BCF~BT{Y?n_>q%>O4f**g#JJ0Zv$HZ literal 0 HcmV?d00001 diff --git a/boards/shields/rpi_pico_uno_flexypin/doc/index.rst b/boards/shields/rpi_pico_uno_flexypin/doc/index.rst new file mode 100644 index 00000000000..3ac57cfaa38 --- /dev/null +++ b/boards/shields/rpi_pico_uno_flexypin/doc/index.rst @@ -0,0 +1,94 @@ +.. _rpi_pico_uno_flexypin: + +RaspberryPi Pico to UNO FlexyPin Adapter +######################################## + +Overview +******** + +Raspberry Pi Pico to Uno `FlexyPin Adapter` is a converter-PCB to Arduino UNO form-factor +from Raspberry Pi Pico that is released in Open Source Hardware. +This board design to use with `FlexyPin`. +The FlexyPin holds Pico and contacts to castellated through-hole. +With simple soldering, it can also be used as a board to convert the RapsberryPi Pico +o the Arduino UNO form factor. + +.. image:: img/rpi_pico_uno_flexypin.png + :align: center + :alt: RaspberryPi Pico to UNO FlexyPin Adapter + +Pins Assignment of the RaspberryPi Pico to UNO FlexyPin Adapter +=============================================================== + ++---------------------+------------+ +| Rpi-Pico Pin | UNO Header | ++=====================+============+ +| GP0 (UART0 TX) | D1 | ++---------------------+------------+ +| GP1 (UART0 RX) | D0 | ++---------------------+------------+ +| GP2 | D8 | ++---------------------+------------+ +| GP3 | D9 | ++---------------------+------------+ +| GP4 | D2 | ++---------------------+------------+ +| GP5 | D3 | ++---------------------+------------+ +| GP6 | D4 | ++---------------------+------------+ +| GP7 | D5 | ++---------------------+------------+ +| GP8 | D6 | ++---------------------+------------+ +| GP9 | D7 | ++---------------------+------------+ +| GP13 | A3 | ++---------------------+------------+ +| GP14 (I2C1 SDA) | A4 | ++---------------------+------------+ +| GP15 (I2C1 SCL) | A5 | ++---------------------+------------+ +| GP16 (SPI0 RX/CIPO) | D12 | ++---------------------+------------+ +| GP17 (SPI0 CS) | D10 | ++---------------------+------------+ +| GP18 (SPI0 SCK) | D13 | ++---------------------+------------+ +| GP19 (SPI0 TX/COPI) | D11 | ++---------------------+------------+ +| GP20 | D14 | ++---------------------+------------+ +| GP21 (I2C0 SCL) | D15 | ++---------------------+------------+ +| GP26 (I2C0 SDA) | A0 | ++---------------------+------------+ +| GP27 | A1 | ++---------------------+------------+ +| GP28 | A2 | ++---------------------+------------+ + +Programming +*********** + +Set ``-DSHIELD=rpi_pico_uno_flexypin`` when you invoke ``west build``. +This shield is just a converter, so it is usually used with other Arduino shield. + +For example, + +.. zephyr-app-commands:: + :zephyr-app: samples/net/wifi + :board: rpi_pico + :shield: 'rpi_pico_uno_flexypin;esp_8266_arduino' + :goals: build + +References +********** + +.. target-notes:: + +.. _FlexyPin: + https://github.com/solderparty/flexypin + +.. _FlexyPin Adapters: + https://github.com/solderparty/flexypin_adapters_hw diff --git a/boards/shields/rpi_pico_uno_flexypin/rpi_pico_uno_flexypin.overlay b/boards/shields/rpi_pico_uno_flexypin/rpi_pico_uno_flexypin.overlay new file mode 100644 index 00000000000..3ddf2872883 --- /dev/null +++ b/boards/shields/rpi_pico_uno_flexypin/rpi_pico_uno_flexypin.overlay @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = + <0 0 &pico_header 26 0>, /* A0 */ + <1 0 &pico_header 27 0>, /* A1 */ + <2 0 &pico_header 28 0>, /* A2 */ + <3 0 &pico_header 13 0>, /* A3 */ + <4 0 &pico_header 14 0>, /* A4 */ + <5 0 &pico_header 15 0>, /* A5 */ + <6 0 &pico_header 1 0>, /* D0 */ + <7 0 &pico_header 0 0>, /* D1 */ + <8 0 &pico_header 4 0>, /* D2 */ + <9 0 &pico_header 5 0>, /* D3 */ + <10 0 &pico_header 6 0>, /* D4 */ + <11 0 &pico_header 7 0>, /* D5 */ + <12 0 &pico_header 8 0>, /* D6 */ + <13 0 &pico_header 9 0>, /* D7 */ + <14 0 &pico_header 2 0>, /* D8 */ + <15 0 &pico_header 3 0>, /* D9 */ + <16 0 &pico_header 17 0>, /* D10 */ + <17 0 &pico_header 19 0>, /* D11 */ + <18 0 &pico_header 16 0>, /* D12 */ + <19 0 &pico_header 18 0>, /* D13 */ + <20 0 &pico_header 20 0>, /* D14 */ + <21 0 &pico_header 21 0>; /* D15 */ + }; +}; + +arduino_spi: &pico_spi {}; +arduino_i2c: &pico_i2c0 {}; +arduino_serial: &pico_serial {}; From d9fd292f4b9af24cb4c1f16ea73c3a857d6af42f Mon Sep 17 00:00:00 2001 From: Nicolas Goualard Date: Thu, 4 Apr 2024 00:30:00 +0200 Subject: [PATCH 2007/2402] drivers: input: CHSC6X Driver Added a driver for the CHSC6X chip used on the Seeed Studio Round Display for Xiao Signed-off-by: Nicolas Goualard --- drivers/input/CMakeLists.txt | 1 + drivers/input/Kconfig | 1 + drivers/input/Kconfig.chsc6x | 11 ++ drivers/input/input_chsc6x.c | 139 ++++++++++++++++++++++ dts/bindings/input/chipsemi,chsc6x.yaml | 13 ++ dts/bindings/vendor-prefixes.txt | 1 + tests/drivers/build_all/input/app.overlay | 6 + 7 files changed, 172 insertions(+) create mode 100644 drivers/input/Kconfig.chsc6x create mode 100644 drivers/input/input_chsc6x.c create mode 100644 dts/bindings/input/chipsemi,chsc6x.yaml diff --git a/drivers/input/CMakeLists.txt b/drivers/input/CMakeLists.txt index 3a5c901c449..4131cca963f 100644 --- a/drivers/input/CMakeLists.txt +++ b/drivers/input/CMakeLists.txt @@ -9,6 +9,7 @@ zephyr_library_sources_ifdef(CONFIG_INPUT_ANALOG_AXIS input_analog_axis.c) zephyr_library_sources_ifdef(CONFIG_INPUT_ANALOG_AXIS_SETTINGS input_analog_axis_settings.c) zephyr_library_sources_ifdef(CONFIG_INPUT_CAP1203 input_cap1203.c) zephyr_library_sources_ifdef(CONFIG_INPUT_CF1133 input_cf1133.c) +zephyr_library_sources_ifdef(CONFIG_INPUT_CHSC6X input_chsc6x.c) zephyr_library_sources_ifdef(CONFIG_INPUT_CST816S input_cst816s.c) zephyr_library_sources_ifdef(CONFIG_INPUT_ESP32_TOUCH_SENSOR input_esp32_touch_sensor.c) zephyr_library_sources_ifdef(CONFIG_INPUT_FT5336 input_ft5336.c) diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 72c6625849c..2312767cea9 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -10,6 +10,7 @@ source "drivers/input/Kconfig.adc_keys" source "drivers/input/Kconfig.analog_axis" source "drivers/input/Kconfig.cap1203" source "drivers/input/Kconfig.cf1133" +source "drivers/input/Kconfig.chsc6x" source "drivers/input/Kconfig.cst816s" source "drivers/input/Kconfig.esp32" source "drivers/input/Kconfig.evdev" diff --git a/drivers/input/Kconfig.chsc6x b/drivers/input/Kconfig.chsc6x new file mode 100644 index 00000000000..18ec25a503c --- /dev/null +++ b/drivers/input/Kconfig.chsc6x @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Nicolas Goualard +# SPDX-License-Identifier: Apache-2.0 + +config INPUT_CHSC6X + bool "Use CHSC6X capacitive touch panel driver" + default y + depends on DT_HAS_CHIPSEMI_CHSC6X_ENABLED + select GPIO + select I2C + help + Enable out of tree driver for CHSC6X touch panel. diff --git a/drivers/input/input_chsc6x.c b/drivers/input/input_chsc6x.c new file mode 100644 index 00000000000..2ef6880725b --- /dev/null +++ b/drivers/input/input_chsc6x.c @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2024 Nicolas Goualard + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT chipsemi_chsc6x + +#include +#include +#include +#include +#include + +struct chsc6x_config { + struct i2c_dt_spec i2c; + const struct gpio_dt_spec int_gpio; +}; + +struct chsc6x_data { + const struct device *dev; + struct k_work work; + struct gpio_callback int_gpio_cb; +}; + +#define CHSC6X_READ_ADDR 0 +#define CHSC6X_READ_LENGTH 5 +#define CHSC6X_OUTPUT_POINTS_PRESSED 0 +#define CHSC6X_OUTPUT_COL 2 +#define CHSC6X_OUTPUT_ROW 4 + +LOG_MODULE_REGISTER(chsc6x, CONFIG_INPUT_LOG_LEVEL); + +static int chsc6x_process(const struct device *dev) +{ + uint8_t output[CHSC6X_READ_LENGTH]; + uint8_t row, col; + bool is_pressed; + int ret; + + const struct chsc6x_config *cfg = dev->config; + + ret = i2c_burst_read_dt(&cfg->i2c, CHSC6X_READ_ADDR, output, CHSC6X_READ_LENGTH); + if (ret < 0) { + LOG_ERR("Could not read data: %i", ret); + return -ENODATA; + } + + is_pressed = output[CHSC6X_OUTPUT_POINTS_PRESSED]; + col = output[CHSC6X_OUTPUT_COL]; + row = output[CHSC6X_OUTPUT_ROW]; + + if (is_pressed) { + input_report_abs(dev, INPUT_ABS_X, col, false, K_FOREVER); + input_report_abs(dev, INPUT_ABS_Y, row, false, K_FOREVER); + input_report_key(dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER); + } else { + input_report_key(dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER); + } + + return 0; +} + +static void chsc6x_work_handler(struct k_work *work) +{ + struct chsc6x_data *data = CONTAINER_OF(work, struct chsc6x_data, work); + + chsc6x_process(data->dev); +} + +static void chsc6x_isr_handler(const struct device *dev, struct gpio_callback *cb, uint32_t mask) +{ + struct chsc6x_data *data = CONTAINER_OF(cb, struct chsc6x_data, int_gpio_cb); + + k_work_submit(&data->work); +} + +static int chsc6x_chip_init(const struct device *dev) +{ + const struct chsc6x_config *cfg = dev->config; + + if (!i2c_is_ready_dt(&cfg->i2c)) { + LOG_ERR("I2C bus %s not ready", cfg->i2c.bus->name); + return -ENODEV; + } + + return 0; +} + +static int chsc6x_init(const struct device *dev) +{ + struct chsc6x_data *data = dev->data; + int ret; + + data->dev = dev; + + k_work_init(&data->work, chsc6x_work_handler); + + const struct chsc6x_config *config = dev->config; + + if (!gpio_is_ready_dt(&config->int_gpio)) { + LOG_ERR("GPIO port %s not ready", config->int_gpio.port->name); + return -ENODEV; + } + + ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT); + if (ret < 0) { + LOG_ERR("Could not configure interrupt GPIO pin: %d", ret); + return ret; + } + + ret = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE); + if (ret < 0) { + LOG_ERR("Could not configure interrupt GPIO interrupt: %d", ret); + return ret; + } + + gpio_init_callback(&data->int_gpio_cb, chsc6x_isr_handler, BIT(config->int_gpio.pin)); + + ret = gpio_add_callback(config->int_gpio.port, &data->int_gpio_cb); + if (ret < 0) { + LOG_ERR("Could not set gpio callback: %d", ret); + return ret; + } + + return chsc6x_chip_init(dev); +}; + +#define CHSC6X_DEFINE(index) \ + static const struct chsc6x_config chsc6x_config_##index = { \ + .i2c = I2C_DT_SPEC_INST_GET(index), \ + .int_gpio = GPIO_DT_SPEC_INST_GET(index, irq_gpios), \ + }; \ + static struct chsc6x_data chsc6x_data_##index; \ + DEVICE_DT_INST_DEFINE(index, chsc6x_init, NULL, &chsc6x_data_##index, \ + &chsc6x_config_##index, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \ + NULL); + +DT_INST_FOREACH_STATUS_OKAY(CHSC6X_DEFINE) diff --git a/dts/bindings/input/chipsemi,chsc6x.yaml b/dts/bindings/input/chipsemi,chsc6x.yaml new file mode 100644 index 00000000000..9f491bd3be8 --- /dev/null +++ b/dts/bindings/input/chipsemi,chsc6x.yaml @@ -0,0 +1,13 @@ +description: CHSC6X touchscreen sensor + +compatible: "chipsemi,chsc6x" + +include: i2c-device.yaml + +properties: + irq-gpios: + type: phandle-array + required: true + description: | + Interrupt GPIO. Used by the controller to signal touch data is + available. Active low. diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index fe3d98c90f0..63e7186781b 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -127,6 +127,7 @@ checkpoint Check Point Software Technologies Ltd. chefree Chefree Technology Corp. chipidea Chipidea, Inc chipone ChipOne +chipsemi Chipsemi Corp. chipspark ChipSPARK chrontel Chrontel, Inc. chrp Common Hardware Reference Platform diff --git a/tests/drivers/build_all/input/app.overlay b/tests/drivers/build_all/input/app.overlay index a5c3c0aff5d..93e7bf1c144 100644 --- a/tests/drivers/build_all/input/app.overlay +++ b/tests/drivers/build_all/input/app.overlay @@ -218,6 +218,12 @@ int-gpios = <&test_gpio 0 0>; }; + chsc6x@7 { + compatible = "chipsemi,chsc6x"; + reg = <0x7>; + irq-gpios = <&test_gpio 0 0>; + }; + pinnacle@2a { compatible = "cirque,pinnacle"; reg = <0x2a>; From 2ae1a978ae38b8a1648951d71e95cd46873a7f33 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Mon, 8 Apr 2024 13:49:26 +0100 Subject: [PATCH 2008/2402] drivers: sensor: ite_cvmp_it8xxx2: Move init priority into if check Moves a Kconfig that appears everywhere in the wrong place so that it is enclosed if if statment check, so it only shows for device that have the driver enabled Signed-off-by: Jamie McCrae --- drivers/sensor/ite/ite_vcmp_it8xxx2/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/sensor/ite/ite_vcmp_it8xxx2/Kconfig b/drivers/sensor/ite/ite_vcmp_it8xxx2/Kconfig index a1423365f7d..c19ff1a7a6d 100644 --- a/drivers/sensor/ite/ite_vcmp_it8xxx2/Kconfig +++ b/drivers/sensor/ite/ite_vcmp_it8xxx2/Kconfig @@ -13,14 +13,14 @@ config VCMP_IT8XXX2 it8xxx2 supports six 10-bit resolution voltage comparator channels, and the input of each comparator comes from ADC pin. +if VCMP_IT8XXX2 + config VCMP_IT8XXX2_INIT_PRIORITY int "ITE it8xxx2 voltage comparator device instance init priority" default SENSOR_INIT_PRIORITY help This option sets ITE voltage comparator device instance init priority. -if VCMP_IT8XXX2 - config VCMP_IT8XXX2_WORKQUEUE bool "ITE it8xxx2 voltage comparator threshold detection uses internal work queue" help From 4d5606b55ba07a29ec022058142f65be10444511 Mon Sep 17 00:00:00 2001 From: Gaetan Perrot Date: Mon, 8 Apr 2024 18:57:39 +0900 Subject: [PATCH 2009/2402] doc: driver: input: espressif touch_sensor Typo Example code was incorrect. Signed-off-by: Gaetan Perrot --- dts/bindings/input/espressif,esp32-touch-sensor.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dts/bindings/input/espressif,esp32-touch-sensor.yaml b/dts/bindings/input/espressif,esp32-touch-sensor.yaml index 7fe6a01d0c7..5bea6081b97 100644 --- a/dts/bindings/input/espressif,esp32-touch-sensor.yaml +++ b/dts/bindings/input/espressif,esp32-touch-sensor.yaml @@ -28,8 +28,8 @@ description: | filter-smooth-level = ; touch_sensor_0 { - channel_num = <1>; - channel_sens = <20>; + channel-num = <1>; + channel-sens = <20>; zephyr,code = ; }; }; From ba08a9a49904ac78687ef10ceed28779de6e1f1f Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 4 Apr 2024 15:34:18 -0500 Subject: [PATCH 2010/2402] MAINTAINERS: Add decsny as DT collaborator Add myself as DT collaborator. Signed-off-by: Declan Snyder --- MAINTAINERS.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 4786168d8ac..1fd761b7d5a 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -762,6 +762,8 @@ Devicetree: status: maintained maintainers: - galak + collaborators: + - decsny files: - scripts/dts/ - dts/common/ @@ -779,6 +781,8 @@ Devicetree Bindings: status: maintained maintainers: - galak + collaborators: + - decsny files: - dts/bindings/ - include/zephyr/dt-bindings/ From 6d7b62452e632a5c02abe53b2b82377c77eff388 Mon Sep 17 00:00:00 2001 From: Richard Wheatley Date: Thu, 4 Apr 2024 14:05:20 -0500 Subject: [PATCH 2011/2402] tests: drivers: gpio: gpio_basic_api Update to remove failure on GPIO_INT_EDGE_BOTH when devices return -ENOTSUP Signed-off-by: Richard Wheatley --- .../gpio/gpio_basic_api/src/test_config_trigger.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/tests/drivers/gpio/gpio_basic_api/src/test_config_trigger.c b/tests/drivers/gpio/gpio_basic_api/src/test_config_trigger.c index 869e550aba4..0bbfe0f9620 100644 --- a/tests/drivers/gpio/gpio_basic_api/src/test_config_trigger.c +++ b/tests/drivers/gpio/gpio_basic_api/src/test_config_trigger.c @@ -40,7 +40,12 @@ ZTEST(after_flash_gpio_config_trigger, test_gpio_config_twice_trigger) /* 2. Enable PIN callback as both edges */ ret = gpio_pin_interrupt_configure(dev, PIN_IN, GPIO_INT_EDGE_BOTH); - zassert_ok(ret, "enable callback failed"); + if (ret == -ENOTSUP) { + TC_PRINT("Both edge GPIO interrupt not supported.\n"); + gpio_remove_callback(dev, &drv_data->gpio_cb); + } else { + zassert_ok(ret, "enable callback failed"); + } /* 3. Configure PIN_OUT as open drain, internal pull-up (may trigger * callback) @@ -87,7 +92,12 @@ ZTEST(after_flash_gpio_config_trigger, test_gpio_config_trigger) /* 2. Enable PIN callback as both edges */ ret = gpio_pin_interrupt_configure(dev, PIN_IN, GPIO_INT_EDGE_BOTH); - zassert_ok(ret, "enable callback failed"); + if (ret == -ENOTSUP) { + TC_PRINT("Both edge GPIO interrupt not supported.\n"); + gpio_remove_callback(dev, &drv_data->gpio_cb); + } else { + zassert_ok(ret, "enable callback failed"); + } /* 3. Configure PIN_OUT as open drain, internal pull-up (may trigger * callback) From 9f0cd47c784e4d2099f59899d17a6ba5f3d4be55 Mon Sep 17 00:00:00 2001 From: Richard Wheatley Date: Thu, 4 Apr 2024 14:06:18 -0500 Subject: [PATCH 2012/2402] tests: drivers: rtc: rtc_api Correct time check for get/set Previous check would always pass as it checked get/get. Signed-off-by: Richard Wheatley --- tests/drivers/rtc/rtc_api/src/test_alarm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/drivers/rtc/rtc_api/src/test_alarm.c b/tests/drivers/rtc/rtc_api/src/test_alarm.c index fcaf187dbf6..f65baf15877 100644 --- a/tests/drivers/rtc/rtc_api/src/test_alarm.c +++ b/tests/drivers/rtc/rtc_api/src/test_alarm.c @@ -116,10 +116,10 @@ ZTEST(rtc_api, test_alarm) zassert_equal(alarm_time_mask_get, alarm_time_mask_set, "Incorrect alarm time mask"); - zassert_equal(alarm_time_get.tm_min, alarm_time_get.tm_min, + zassert_equal(alarm_time_get.tm_min, alarm_time_set.tm_min, "Incorrect alarm time minute field"); - zassert_equal(alarm_time_get.tm_hour, alarm_time_get.tm_hour, + zassert_equal(alarm_time_get.tm_hour, alarm_time_set.tm_hour, "Incorrect alarm time hour field"); } From 837d09ed9ebb4c4c0e22be94707ae75b43389811 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Mon, 8 Apr 2024 11:53:08 +0200 Subject: [PATCH 2013/2402] net: connection: Log an error when running out of contexts Running out of connection contexts is most likely due to app misconfiguration, therefore it's useful to get an explicit information that context allocation failed. Signed-off-by: Robert Lubos --- subsys/net/ip/connection.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/subsys/net/ip/connection.c b/subsys/net/ip/connection.c index c5542d1238a..0d3b4f93640 100644 --- a/subsys/net/ip/connection.c +++ b/subsys/net/ip/connection.c @@ -352,6 +352,8 @@ int net_conn_register(uint16_t proto, uint8_t family, conn = conn_get_unused(); if (!conn) { + NET_ERR("Not enough connection contexts. " + "Consider increasing CONFIG_NET_MAX_CONN."); return -ENOENT; } From e2314426728b5ad8fa4d4279329dc8049aadfb44 Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Fri, 5 Apr 2024 13:36:16 +0200 Subject: [PATCH 2014/2402] boards: nucleo_h563zi: Fix APB3 bus clock 240MHz as APB3 bus clock is too fast to set I2C base bus speed. Set bus pre-scaler to 2 and reach a safe 120MHz. This commit is very similar to 456183f982923446d8b40b32d79a9a2d24d37ab8. Signed-off-by: Jeppe Odgaard --- boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi index 3e965035626..4d375016208 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi +++ b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi @@ -84,7 +84,7 @@ ahb-prescaler = <1>; apb1-prescaler = <2>; apb2-prescaler = <1>; - apb3-prescaler = <1>; + apb3-prescaler = <2>; }; &lpuart1 { From 3114ccf568a2b20d60b896c297a8a417f6733d64 Mon Sep 17 00:00:00 2001 From: Rob Newberry Date: Fri, 5 Apr 2024 11:11:40 +0530 Subject: [PATCH 2015/2402] GNSS: Increase size of hdop The valid range of hdop (horizontal diffusion of precision) goes from 0-100000, but because we are using a uint16_t, we truncate anything above UINT16_MAX. This fix changes the size of the hdop member to a uint32_t, which allows us to capture valid (but admittedly very poor) readings. Signed-off-by: Rob Newberry --- drivers/gnss/gnss_nmea0183.c | 2 +- include/zephyr/drivers/gnss.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gnss/gnss_nmea0183.c b/drivers/gnss/gnss_nmea0183.c index f69dd347a9f..9bce7a443a2 100644 --- a/drivers/gnss/gnss_nmea0183.c +++ b/drivers/gnss/gnss_nmea0183.c @@ -530,7 +530,7 @@ int gnss_nmea0183_parse_gga(const char **argv, uint16_t argc, struct gnss_data * /* Parse HDOP */ if ((gnss_parse_dec_to_milli(argv[8], &tmp64) < 0) || - (tmp64 > UINT16_MAX) || + (tmp64 > UINT32_MAX) || (tmp64 < 0)) { return -EINVAL; } diff --git a/include/zephyr/drivers/gnss.h b/include/zephyr/drivers/gnss.h index c5448cefffc..2c716a43a06 100644 --- a/include/zephyr/drivers/gnss.h +++ b/include/zephyr/drivers/gnss.h @@ -156,7 +156,7 @@ struct gnss_info { /** Number of satellites being tracked */ uint16_t satellites_cnt; /** Horizontal dilution of precision in 1/1000 */ - uint16_t hdop; + uint32_t hdop; /** The fix status */ enum gnss_fix_status fix_status; /** The fix quality */ From f9b7a2a37db9d0ce70145edafd05afd1db2a8dd5 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Wed, 3 Apr 2024 13:21:20 +0200 Subject: [PATCH 2016/2402] manifest: update hal_nordic revision to have PWM fix for nRF54 series Updated hal_nordic revision contains fix that allows the PWM on nRF54H20 and nRF54L15 devices to work. Signed-off-by: Nikodem Kastelik --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 012582eec23..c89ad043c28 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: 7803a3e6b606ddde8df9a10108d7251a108bd7c9 + revision: fc2bab706f195c64d40016c9855b8acd7c235ded path: modules/hal/nordic groups: - hal From 0401d063fa9ea3eb78542cee74e2a89f501b02f9 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Wed, 3 Apr 2024 12:33:40 +0200 Subject: [PATCH 2017/2402] dts: nordic: add PWM instances for nRF54 Series Add definitions of PWM peripheral instances so it can be utilized on nRF54H20 and nRF54L15 devices. Signed-off-by: Nikodem Kastelik --- .../nordic/nrf54l15_cpuapp_peripherals.dtsi | 24 +++++++++++ dts/common/nordic/nrf54h20.dtsi | 40 +++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi index 25f94241336..eb161844841 100644 --- a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi +++ b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi @@ -261,6 +261,30 @@ timer24: timer@ce000 { prescaler = <0>; }; +pwm20: pwm@d2000 { + compatible = "nordic,nrf-pwm"; + status = "disabled"; + reg = <0xd2000 0x1000>; + interrupts = <210 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; +}; + +pwm21: pwm@d3000 { + compatible = "nordic,nrf-pwm"; + status = "disabled"; + reg = <0xd3000 0x1000>; + interrupts = <211 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; +}; + +pwm22: pwm@d4000 { + compatible = "nordic,nrf-pwm"; + status = "disabled"; + reg = <0xd4000 0x1000>; + interrupts = <212 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; +}; + adc: adc@d5000 { compatible = "nordic,nrf-saadc"; reg = <0xd5000 0x1000>; diff --git a/dts/common/nordic/nrf54h20.dtsi b/dts/common/nordic/nrf54h20.dtsi index a0085496456..b8456d719c0 100644 --- a/dts/common/nordic/nrf54h20.dtsi +++ b/dts/common/nordic/nrf54h20.dtsi @@ -352,6 +352,14 @@ prescaler = <0>; }; + pwm120: pwm@8e4000 { + compatible = "nordic,nrf-pwm"; + reg = <0x8e4000 0x1000>; + status = "disabled"; + interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + }; + spi120: spi@8e6000 { compatible = "nordic,nrf-spim"; reg = <0x8e6000 0x1000>; @@ -609,6 +617,14 @@ prescaler = <0>; }; + pwm130: pwm@9a4000 { + compatible = "nordic,nrf-pwm"; + reg = <0x9a4000 0x1000>; + status = "disabled"; + interrupts = <420 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + }; + i2c130: i2c@9a5000 { compatible = "nordic,nrf-twim"; reg = <0x9a5000 0x1000>; @@ -691,6 +707,14 @@ prescaler = <0>; }; + pwm131: pwm@9b4000 { + compatible = "nordic,nrf-pwm"; + reg = <0x9b4000 0x1000>; + status = "disabled"; + interrupts = <436 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + }; + i2c132: i2c@9b5000 { compatible = "nordic,nrf-twim"; reg = <0x9b5000 0x1000>; @@ -773,6 +797,14 @@ prescaler = <0>; }; + pwm132: pwm@9c4000 { + compatible = "nordic,nrf-pwm"; + reg = <0x9c4000 0x1000>; + status = "disabled"; + interrupts = <452 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + }; + i2c134: i2c@9c5000 { compatible = "nordic,nrf-twim"; reg = <0x9c5000 0x1000>; @@ -855,6 +887,14 @@ prescaler = <0>; }; + pwm133: pwm@9d4000 { + compatible = "nordic,nrf-pwm"; + reg = <0x9d4000 0x1000>; + status = "disabled"; + interrupts = <468 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + }; + i2c136: i2c@9d5000 { compatible = "nordic,nrf-twim"; reg = <0x9d5000 0x1000>; From 6bce78937df09f55143ddd8fc14b064438a020e9 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Wed, 3 Apr 2024 12:37:00 +0200 Subject: [PATCH 2018/2402] soc: nordic: add nRF54 PWM HAS_HW & base addr validation Add HAS_HW symbols for PWM instances found on nRF54H20 and nRF54L15 devices. Signed-off-by: Nikodem Kastelik --- soc/nordic/common/Kconfig.peripherals | 24 ++++++++++++++++++++++++ soc/nordic/validate_base_addresses.c | 8 ++++++++ 2 files changed, 32 insertions(+) diff --git a/soc/nordic/common/Kconfig.peripherals b/soc/nordic/common/Kconfig.peripherals index 7a1c3281dec..0c8f958eb38 100644 --- a/soc/nordic/common/Kconfig.peripherals +++ b/soc/nordic/common/Kconfig.peripherals @@ -147,6 +147,30 @@ config HAS_HW_NRF_PWM2 config HAS_HW_NRF_PWM3 def_bool $(dt_nodelabel_enabled_with_compat,pwm3,$(DT_COMPAT_NORDIC_NRF_PWM)) +config HAS_HW_NRF_PWM20 + def_bool $(dt_nodelabel_enabled_with_compat,pwm20,$(DT_COMPAT_NORDIC_NRF_PWM)) + +config HAS_HW_NRF_PWM21 + def_bool $(dt_nodelabel_enabled_with_compat,pwm21,$(DT_COMPAT_NORDIC_NRF_PWM)) + +config HAS_HW_NRF_PWM22 + def_bool $(dt_nodelabel_enabled_with_compat,pwm22,$(DT_COMPAT_NORDIC_NRF_PWM)) + +config HAS_HW_NRF_PWM120 + def_bool $(dt_nodelabel_enabled_with_compat,pwm120,$(DT_COMPAT_NORDIC_NRF_PWM)) + +config HAS_HW_NRF_PWM130 + def_bool $(dt_nodelabel_enabled_with_compat,pwm130,$(DT_COMPAT_NORDIC_NRF_PWM)) + +config HAS_HW_NRF_PWM131 + def_bool $(dt_nodelabel_enabled_with_compat,pwm131,$(DT_COMPAT_NORDIC_NRF_PWM)) + +config HAS_HW_NRF_PWM132 + def_bool $(dt_nodelabel_enabled_with_compat,pwm132,$(DT_COMPAT_NORDIC_NRF_PWM)) + +config HAS_HW_NRF_PWM133 + def_bool $(dt_nodelabel_enabled_with_compat,pwm133,$(DT_COMPAT_NORDIC_NRF_PWM)) + config HAS_HW_NRF_QDEC0 def_bool $(dt_nodelabel_enabled_with_compat,qdec0,$(DT_COMPAT_NORDIC_NRF_QDEC)) diff --git a/soc/nordic/validate_base_addresses.c b/soc/nordic/validate_base_addresses.c index 1d7d5190ba5..1fa4c87c97b 100644 --- a/soc/nordic/validate_base_addresses.c +++ b/soc/nordic/validate_base_addresses.c @@ -210,6 +210,14 @@ CHECK_DT_REG(pwm0, NRF_PWM0); CHECK_DT_REG(pwm1, NRF_PWM1); CHECK_DT_REG(pwm2, NRF_PWM2); CHECK_DT_REG(pwm3, NRF_PWM3); +CHECK_DT_REG(pwm20, NRF_PWM20); +CHECK_DT_REG(pwm21, NRF_PWM21); +CHECK_DT_REG(pwm22, NRF_PWM22); +CHECK_DT_REG(pwm120, NRF_PWM120); +CHECK_DT_REG(pwm130, NRF_PWM130); +CHECK_DT_REG(pwm131, NRF_PWM131); +CHECK_DT_REG(pwm132, NRF_PWM132); +CHECK_DT_REG(pwm133, NRF_PWM133); CHECK_DT_REG(qdec, NRF_QDEC0); /* this should be the same node as qdec0 */ CHECK_DT_REG(qdec0, NRF_QDEC0); CHECK_DT_REG(qdec1, NRF_QDEC1); From 9949645dd447bce65c66c03066e4034ba86631be Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Wed, 3 Apr 2024 12:39:13 +0200 Subject: [PATCH 2019/2402] modules: hal_nordic: nrfx: add support for nRF54 PWM Add Kconfig-to-nrfx symbol redefinitions so that PWM instances found on nRF54H20 and nRF54L15 devices are supported. Signed-off-by: Nikodem Kastelik --- modules/hal_nordic/nrfx/Kconfig | 40 +++++++++++++++++++++++++++ modules/hal_nordic/nrfx/nrfx_config.h | 24 ++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/modules/hal_nordic/nrfx/Kconfig b/modules/hal_nordic/nrfx/Kconfig index a731013bd4b..541d9fac5e7 100644 --- a/modules/hal_nordic/nrfx/Kconfig +++ b/modules/hal_nordic/nrfx/Kconfig @@ -184,6 +184,46 @@ config NRFX_PWM3 depends on $(dt_nodelabel_has_compat,pwm3,$(DT_COMPAT_NORDIC_NRF_PWM)) select NRFX_PWM +config NRFX_PWM20 + bool "PWM20 driver instance" + depends on $(dt_nodelabel_has_compat,pwm20,$(DT_COMPAT_NORDIC_NRF_PWM)) + select NRFX_PWM + +config NRFX_PWM21 + bool "PWM21 driver instance" + depends on $(dt_nodelabel_has_compat,pwm21,$(DT_COMPAT_NORDIC_NRF_PWM)) + select NRFX_PWM + +config NRFX_PWM22 + bool "PWM22 driver instance" + depends on $(dt_nodelabel_has_compat,pwm22,$(DT_COMPAT_NORDIC_NRF_PWM)) + select NRFX_PWM + +config NRFX_PWM120 + bool "PWM120 driver instance" + depends on $(dt_nodelabel_has_compat,pwm120,$(DT_COMPAT_NORDIC_NRF_PWM)) + select NRFX_PWM + +config NRFX_PWM130 + bool "PWM130 driver instance" + depends on $(dt_nodelabel_has_compat,pwm130,$(DT_COMPAT_NORDIC_NRF_PWM)) + select NRFX_PWM + +config NRFX_PWM131 + bool "PWM131 driver instance" + depends on $(dt_nodelabel_has_compat,pwm131,$(DT_COMPAT_NORDIC_NRF_PWM)) + select NRFX_PWM + +config NRFX_PWM132 + bool "PWM132 driver instance" + depends on $(dt_nodelabel_has_compat,pwm132,$(DT_COMPAT_NORDIC_NRF_PWM)) + select NRFX_PWM + +config NRFX_PWM133 + bool "PWM133 driver instance" + depends on $(dt_nodelabel_has_compat,pwm133,$(DT_COMPAT_NORDIC_NRF_PWM)) + select NRFX_PWM + config NRFX_QDEC bool diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index 89c07938293..60fcd276ea4 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -248,6 +248,30 @@ #ifdef CONFIG_NRFX_PWM3 #define NRFX_PWM3_ENABLED 1 #endif +#ifdef CONFIG_NRFX_PWM20 +#define NRFX_PWM20_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_PWM21 +#define NRFX_PWM21_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_PWM22 +#define NRFX_PWM22_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_PWM120 +#define NRFX_PWM120_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_PWM130 +#define NRFX_PWM130_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_PWM131 +#define NRFX_PWM131_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_PWM132 +#define NRFX_PWM132_ENABLED 1 +#endif +#ifdef CONFIG_NRFX_PWM133 +#define NRFX_PWM133_ENABLED 1 +#endif #ifdef CONFIG_NRFX_QDEC #define NRFX_QDEC_ENABLED 1 From 835f3bef7059a97b6e0543ac449d6376c2d06e58 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Wed, 3 Apr 2024 12:40:50 +0200 Subject: [PATCH 2020/2402] drivers: pwm: add support for nRF54 devices Add PWM instances found on nRF54H20 and nRF54L15 devices, so that PWM driver can be utilized on these. Signed-off-by: Nikodem Kastelik --- drivers/pwm/Kconfig.nrfx | 8 ++++++++ drivers/pwm/pwm_nrfx.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/pwm/Kconfig.nrfx b/drivers/pwm/Kconfig.nrfx index 9a84c5fd21b..933fe7cb29c 100644 --- a/drivers/pwm/Kconfig.nrfx +++ b/drivers/pwm/Kconfig.nrfx @@ -9,6 +9,14 @@ config PWM_NRFX select NRFX_PWM1 if HAS_HW_NRF_PWM1 select NRFX_PWM2 if HAS_HW_NRF_PWM2 select NRFX_PWM3 if HAS_HW_NRF_PWM3 + select NRFX_PWM20 if HAS_HW_NRF_PWM20 + select NRFX_PWM21 if HAS_HW_NRF_PWM21 + select NRFX_PWM22 if HAS_HW_NRF_PWM22 + select NRFX_PWM120 if HAS_HW_NRF_PWM120 + select NRFX_PWM130 if HAS_HW_NRF_PWM130 + select NRFX_PWM131 if HAS_HW_NRF_PWM131 + select NRFX_PWM132 if HAS_HW_NRF_PWM132 + select NRFX_PWM133 if HAS_HW_NRF_PWM133 select PINCTRL help Enable support for nrfx Hardware PWM driver for nRF52 MCU series. diff --git a/drivers/pwm/pwm_nrfx.c b/drivers/pwm/pwm_nrfx.c index 52257dce104..9feacb2c10b 100644 --- a/drivers/pwm/pwm_nrfx.c +++ b/drivers/pwm/pwm_nrfx.c @@ -391,3 +391,35 @@ PWM_NRFX_DEVICE(2); #ifdef CONFIG_HAS_HW_NRF_PWM3 PWM_NRFX_DEVICE(3); #endif + +#ifdef CONFIG_HAS_HW_NRF_PWM20 +PWM_NRFX_DEVICE(20); +#endif + +#ifdef CONFIG_HAS_HW_NRF_PWM21 +PWM_NRFX_DEVICE(21); +#endif + +#ifdef CONFIG_HAS_HW_NRF_PWM22 +PWM_NRFX_DEVICE(22); +#endif + +#ifdef CONFIG_HAS_HW_NRF_PWM120 +PWM_NRFX_DEVICE(120); +#endif + +#ifdef CONFIG_HAS_HW_NRF_PWM130 +PWM_NRFX_DEVICE(130); +#endif + +#ifdef CONFIG_HAS_HW_NRF_PWM131 +PWM_NRFX_DEVICE(131); +#endif + +#ifdef CONFIG_HAS_HW_NRF_PWM132 +PWM_NRFX_DEVICE(132); +#endif + +#ifdef CONFIG_HAS_HW_NRF_PWM133 +PWM_NRFX_DEVICE(133); +#endif From c5d39a83dd1728aecb5c83257fb6049b645d4801 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Wed, 3 Apr 2024 15:42:40 +0200 Subject: [PATCH 2021/2402] boards: nordic: nrf54l15pdk: mark PWM as supported PWM peripheral is now supported on nRF54L15 PDK. Signed-off-by: Nikodem Kastelik --- boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml index a6cf750dcc7..95fc08d422e 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml @@ -15,6 +15,7 @@ supported: - counter - gpio - i2c + - pwm - spi - watchdog - i2s From 53a7a402a78fd53c2fed08dfd10907a86906a5b6 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Wed, 3 Apr 2024 12:42:21 +0200 Subject: [PATCH 2022/2402] tests: drivers: pwm: add support for nRF54 devices Add missing alignments and overlays so that nRF54H20 and nRF54L15 can run the test. Signed-off-by: Nikodem Kastelik --- .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 20 +++++++++++++++++++ .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 20 +++++++++++++++++++ tests/drivers/pwm/pwm_api/src/test_pwm.c | 5 ++++- tests/drivers/pwm/pwm_api/testcase.yaml | 2 +- 4 files changed, 45 insertions(+), 2 deletions(-) create mode 100644 tests/drivers/pwm/pwm_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay create mode 100644 tests/drivers/pwm/pwm_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay diff --git a/tests/drivers/pwm/pwm_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/pwm/pwm_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..c483d27f569 --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -0,0 +1,20 @@ +&pinctrl { + pwm_default: pwm_default { + group1 { + psels = ; + }; + }; + pwm_sleep: pwm_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; +}; + +&pwm130 { + status = "okay"; + pinctrl-0 = <&pwm_default>; + pinctrl-1 = <&pwm_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/tests/drivers/pwm/pwm_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/pwm/pwm_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay new file mode 100644 index 00000000000..013653617e4 --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay @@ -0,0 +1,20 @@ +&pinctrl { + pwm_default: pwm_default { + group1 { + psels = ; + }; + }; + pwm_sleep: pwm_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; +}; + +&pwm20 { + status = "okay"; + pinctrl-0 = <&pwm_default>; + pinctrl-1 = <&pwm_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/tests/drivers/pwm/pwm_api/src/test_pwm.c b/tests/drivers/pwm/pwm_api/src/test_pwm.c index 904cf90964e..a83b14ffef4 100644 --- a/tests/drivers/pwm/pwm_api/src/test_pwm.c +++ b/tests/drivers/pwm/pwm_api/src/test_pwm.c @@ -38,6 +38,9 @@ #elif DT_NODE_HAS_STATUS(DT_ALIAS(pwm_3), okay) #define PWM_DEV_NODE DT_ALIAS(pwm_3) +#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pwm) +#define PWM_DEV_NODE DT_INST(0, nordic_nrf_pwm) + #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_pwm) #define PWM_DEV_NODE DT_INST(0, st_stm32_pwm) @@ -76,7 +79,7 @@ #if defined CONFIG_BOARD_SAM_E70_XPLAINED #define DEFAULT_PWM_PORT 2 /* PWM on EXT2 connector, pin 8 */ #elif defined CONFIG_PWM_NRFX -#define DEFAULT_PWM_PORT DT_PROP(DT_ALIAS(pwm_0), ch0_pin) +#define DEFAULT_PWM_PORT 0 #elif defined CONFIG_BOARD_ADAFRUIT_ITSYBITSY_M4_EXPRESS #define DEFAULT_PWM_PORT 2 /* TCC1/WO[2] on PA18 (D7) */ #elif defined CONFIG_BOARD_MIMXRT685_EVK diff --git a/tests/drivers/pwm/pwm_api/testcase.yaml b/tests/drivers/pwm/pwm_api/testcase.yaml index 608a4d0a0e1..aca9172fc96 100644 --- a/tests/drivers/pwm/pwm_api/testcase.yaml +++ b/tests/drivers/pwm/pwm_api/testcase.yaml @@ -6,5 +6,5 @@ tests: - userspace filter: dt_alias_exists("pwm-0") or dt_alias_exists("pwm-1") or dt_alias_exists("pwm-2") or dt_alias_exists("pwm-3") or dt_compat_enabled("st,stm32-pwm") - or dt_compat_enabled("intel,blinky-pwm") + or dt_compat_enabled("intel,blinky-pwm") or dt_compat_enabled("nordic,nrf-pwm") depends_on: pwm From ebdb07a05c036da8f8d76559cd24d3a34a2679c5 Mon Sep 17 00:00:00 2001 From: Simon Hein Date: Mon, 18 Mar 2024 14:30:08 +0100 Subject: [PATCH 2023/2402] kernel: Clean up mailbox async msg configuration Remove confusing and duplicate async message configuration switches for mailboxes. Signed-off-by: Simon Hein --- kernel/mailbox.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/kernel/mailbox.c b/kernel/mailbox.c index 84c79b19931..d7da8e3c8e4 100644 --- a/kernel/mailbox.c +++ b/kernel/mailbox.c @@ -48,10 +48,6 @@ static inline void mbox_async_free(struct k_mbox_async *async) k_stack_push(&async_msg_free, (stack_data_t)async); } -#endif /* CONFIG_NUM_MBOX_ASYNC_MSGS > 0 */ - -#if (CONFIG_NUM_MBOX_ASYNC_MSGS > 0) - /* * Do run-time initialization of mailbox object subsystem. */ @@ -60,7 +56,6 @@ static int init_mbox_module(void) /* array of asynchronous message descriptors */ static struct k_mbox_async __noinit async_msg[CONFIG_NUM_MBOX_ASYNC_MSGS]; -#if (CONFIG_NUM_MBOX_ASYNC_MSGS > 0) /* * Create pool of asynchronous message descriptors. * @@ -79,7 +74,6 @@ static int init_mbox_module(void) z_init_thread_base(&async_msg[i].thread, 0, _THREAD_DUMMY, 0); k_stack_push(&async_msg_free, (stack_data_t)&async_msg[i]); } -#endif /* CONFIG_NUM_MBOX_ASYNC_MSGS > 0 */ /* Complete initialization of statically defined mailboxes. */ @@ -88,7 +82,7 @@ static int init_mbox_module(void) SYS_INIT(init_mbox_module, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif /* CONFIG_NUM_MBOX_ASYNC_MSGS */ +#endif /* CONFIG_NUM_MBOX_ASYNC_MSGS > 0 */ void k_mbox_init(struct k_mbox *mbox) { From d42dfc36d7a88ba2fdb596a1cf0d2d24aab4815d Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Thu, 21 Mar 2024 15:53:14 +0200 Subject: [PATCH 2024/2402] drivers: pinctrl: Kconfig.imx: enable PINCTRL_IMX by default Currently, when using the `pinctrl_imx.c` driver one has to manually enable `CONFIG_PINCTRL_IMX` even if the pinctrl node using the driver is enabled. This is redundant and prone to error as one would expect the driver to be enabled when the node is also enabled. This commit fixes the issue by enabling `CONFIG_PINCTRL_IMX` by default and adding a new dependency on the state of the pinctrl node (i.e: node needs to be enabled for the configuration to also be set to `y`). Signed-off-by: Laurentiu Mihalcea --- drivers/pinctrl/Kconfig.imx | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/Kconfig.imx b/drivers/pinctrl/Kconfig.imx index 506f5b30016..d12571786a0 100644 --- a/drivers/pinctrl/Kconfig.imx +++ b/drivers/pinctrl/Kconfig.imx @@ -3,7 +3,9 @@ config PINCTRL_IMX bool "Pin controller driver for iMX MCUs" + depends on DT_HAS_NXP_IMX_IOMUXC_ENABLED depends on HAS_MCUX_IOMUXC || HAS_IMX_IOMUXC + default y help Enable pin controller driver for NXP iMX series MCUs From 399c2cba652aeee320eab87fd454a71b74d289eb Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Thu, 21 Mar 2024 15:35:49 +0200 Subject: [PATCH 2025/2402] nxp: imx8ulp: enable pinctrl This commit enables pinctrl on i.MX8ULP. This includes: 1) Adding `pinctrl_soc.h` header file. 2) Adding DTS node for IOMUXC1, which is one of the IPs responsible for managing the 8ULP pads. 3) Adding .dtsi with pin definitions. For now, only the LPUART7 pads are added to this file because this is going to be the only consummer for now. 4) Modifying the `pinctrl_imx.c` driver to work for 8ULP. 5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a dependency of `CONFIG_PINCTRL_IMX`. Signed-off-by: Laurentiu Mihalcea --- .../imx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi | 23 +++++++ .../imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.dts | 1 + drivers/pinctrl/pinctrl_imx.c | 16 +++++ dts/bindings/pinctrl/nxp,imx8ulp-pinctrl.yaml | 48 +++++++++++++ dts/xtensa/nxp/nxp_imx8ulp.dtsi | 8 +++ soc/nxp/imx/imx8ulp/Kconfig | 1 + soc/nxp/imx/imx8ulp/pinctrl_soc.h | 68 +++++++++++++++++++ 7 files changed, 165 insertions(+) create mode 100644 boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi create mode 100644 dts/bindings/pinctrl/nxp,imx8ulp-pinctrl.yaml create mode 100644 soc/nxp/imx/imx8ulp/pinctrl_soc.h diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi b/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi new file mode 100644 index 00000000000..c0b80948ca2 --- /dev/null +++ b/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&iomuxc1 { + iomuxc1_ptf22_lpuart7_tx: IOMUXC_PTF22_LPUART7_TX { + pinmux = <0x298c0158 0x4 0x298c09e0 0x3 0x298c0158>; + }; + + iomuxc1_ptf23_lpuart7_rx: IOMUXC_PTF23_LPUART7_RX { + pinmux = <0x298c015c 0x4 0x298c09dc 0x3 0x298c015c>; + }; +}; + +&pinctrl { + lpuart7_default: lpuart7_default { + group0 { + pinmux = <&iomuxc1_ptf22_lpuart7_tx>, <&iomuxc1_ptf23_lpuart7_rx>; + }; + }; +}; diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.dts b/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.dts index 49ad098fb24..c9cb331a7ba 100644 --- a/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.dts +++ b/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include "imx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi" / { model = "NXP i.MX 8ULP Audio DSP"; diff --git a/drivers/pinctrl/pinctrl_imx.c b/drivers/pinctrl/pinctrl_imx.c index 2996657914c..6bc9df4e538 100644 --- a/drivers/pinctrl/pinctrl_imx.c +++ b/drivers/pinctrl/pinctrl_imx.c @@ -45,6 +45,22 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)), (mem_addr_t)config_register); } +#elif defined(CONFIG_SOC_MIMX8UD7) + if (mux_register == config_register) { + sys_write32(IOMUXC_PCR_MUX_MODE(mux_mode) | + pin_ctrl_flags, (mem_addr_t)mux_register); + } else { + sys_write32(IOMUXC_PCR_MUX_MODE(mux_mode), + (mem_addr_t)mux_register); + + if (config_register) { + sys_write32(pin_ctrl_flags, (mem_addr_t)config_register); + } + } + + if (input_register) { + sys_write32(IOMUXC_PSMI_SSS(input_daisy), (mem_addr_t)input_register); + } #else sys_write32( IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) | diff --git a/dts/bindings/pinctrl/nxp,imx8ulp-pinctrl.yaml b/dts/bindings/pinctrl/nxp,imx8ulp-pinctrl.yaml new file mode 100644 index 00000000000..29f5b0c2285 --- /dev/null +++ b/dts/bindings/pinctrl/nxp,imx8ulp-pinctrl.yaml @@ -0,0 +1,48 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: Use this compatible for the i.MX8ULP boards + +compatible: "nxp,imx8ulp-pinctrl" + +include: base.yaml + +child-binding: + description: i.MX8ULP pin controller pin group + child-binding: + description: i.MX8ULP pin controller pin configuration node + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-pull-up + - bias-pull-down + - drive-open-drain + properties: + pinmux: + required: true + type: phandles + drive-strength: + type: string + description: | + Used to configure the pad's drive strength, which, together + with the slew rate, affects the maximum frequency the pad's + output buffer can yield. If "normal" drive strength is used, + the maximum frequency will be lower as per the measurements + found in the SoC datasheet. Note that the TRM refers to the + "normal" drive strength as "standard". If unspecified, the + default will be "normal". + enum: + - "normal" + - "high" + slew-rate: + type: string + description: | + Used to configure the pad's slew rate, which affects the + maximum frequency the pad's output buffer can yield ( + "fast" slew rate -> higher pad frequency, "slow" slew rate -> + lower pad frequency). Note that the TRM refers to the "fast" + slew rate as "standard". If unspecified, the default will be + "fast". + enum: + - "fast" + - "slow" diff --git a/dts/xtensa/nxp/nxp_imx8ulp.dtsi b/dts/xtensa/nxp/nxp_imx8ulp.dtsi index f0e308f2c77..2b4460aff5a 100644 --- a/dts/xtensa/nxp/nxp_imx8ulp.dtsi +++ b/dts/xtensa/nxp/nxp_imx8ulp.dtsi @@ -37,4 +37,12 @@ reg = <0x29800000 DT_SIZE_K(64)>; #clock-cells = <2>; }; + + iomuxc1: pinctrl@298c0000 { + compatible = "nxp,imx-iomuxc"; + reg = <0x298c0000 DT_SIZE_K(64)>; + pinctrl: pinctrl { + compatible = "nxp,imx8ulp-pinctrl"; + }; + }; }; diff --git a/soc/nxp/imx/imx8ulp/Kconfig b/soc/nxp/imx/imx8ulp/Kconfig index 66da731ca94..ca41f1673ef 100644 --- a/soc/nxp/imx/imx8ulp/Kconfig +++ b/soc/nxp/imx/imx8ulp/Kconfig @@ -11,6 +11,7 @@ config SOC_MIMX8UD7_ADSP select XTENSA_SMALL_VECTOR_TABLE_ENTRY select CPU_HAS_DCACHE select HAS_MCUX + select HAS_MCUX_IOMUXC # note: the NXP HAL refers to the HIFI4 DSP as # `dsp1` and the Fusion DSP as `dsp0`, thus the diff --git a/soc/nxp/imx/imx8ulp/pinctrl_soc.h b/soc/nxp/imx/imx8ulp/pinctrl_soc.h new file mode 100644 index 00000000000..0dd48b4ca21 --- /dev/null +++ b/soc/nxp/imx/imx8ulp/pinctrl_soc.h @@ -0,0 +1,68 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_NXP_IMX_IMX8ULP_PINCTR_SOC_H_ +#define ZEPHYR_SOC_NXP_IMX_IMX8ULP_PINCTR_SOC_H_ + +#include +#include "fsl_iomuxc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct pinctrl_soc_pinmux { + uint32_t mux_register; + uint8_t mux_mode; + uint32_t input_register; + uint32_t input_daisy; + uint32_t config_register; +}; + +struct pinctrl_soc_pin { + struct pinctrl_soc_pinmux pinmux; + uint32_t pin_ctrl_flags; +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +#define _PULL_IS_ENABLED(node_id)\ + (DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) + +#define _IMX8ULP_PIN_FLAGS(node_id) \ + ((DT_ENUM_IDX_OR(node_id, drive_strength, 0) << IOMUXC_PCR_DSE_SHIFT) | \ + (DT_PROP(node_id, drive_open_drain) << IOMUXC_PCR_ODE_SHIFT) | \ + (DT_ENUM_IDX_OR(node_id, slew_rate, 0) << IOMUXC_PCR_SRE_SHIFT) | \ + (DT_PROP(node_id, bias_pull_up) << IOMUXC_PCR_PS_SHIFT) | \ + (_PULL_IS_ENABLED(node_id) << IOMUXC_PCR_PE_SHIFT)) + +#define _IMX8ULP_PINMUX(node_id) \ + { \ + .mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \ + .input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \ + .mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \ + .input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \ + } + +#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx)\ + _IMX8ULP_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) + +#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ + { \ + .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \ + .pin_ctrl_flags = _IMX8ULP_PIN_FLAGS(group_id), \ + }, + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)\ + { DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),\ + DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT) }; + +#ifdef __cplusplus +{ +#endif + +#endif /* ZEPHYR_SOC_NXP_IMX_IMX8ULP_PINCTR_SOC_H_ */ From 6a9407ede41ee698456477af125c8a2646b12cb2 Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Wed, 20 Mar 2024 10:21:32 +0800 Subject: [PATCH 2026/2402] drivers: counter: gpt: enable MMIO memory mapping Map the device memory in case of running with MMU on Cortex-A Core. Signed-off-by: Jiafei Pan --- drivers/counter/Kconfig.mcux_gpt | 1 + drivers/counter/counter_mcux_gpt.c | 63 +++++++++++++++++++----------- 2 files changed, 41 insertions(+), 23 deletions(-) diff --git a/drivers/counter/Kconfig.mcux_gpt b/drivers/counter/Kconfig.mcux_gpt index b8ac2653150..22417bf58fe 100644 --- a/drivers/counter/Kconfig.mcux_gpt +++ b/drivers/counter/Kconfig.mcux_gpt @@ -7,5 +7,6 @@ config COUNTER_MCUX_GPT bool "MCUX GPT driver" default y depends on DT_HAS_NXP_IMX_GPT_ENABLED + select KERNEL_DIRECT_MAP if MMU help Enable support for mcux General Purpose Timer (GPT) driver. diff --git a/drivers/counter/counter_mcux_gpt.c b/drivers/counter/counter_mcux_gpt.c index 79079a0f5bc..04cd1c4cbed 100644 --- a/drivers/counter/counter_mcux_gpt.c +++ b/drivers/counter/counter_mcux_gpt.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2019, Linaro Limited. + * Copyright 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,55 +16,66 @@ LOG_MODULE_REGISTER(mcux_gpt, CONFIG_COUNTER_LOG_LEVEL); +#define DEV_CFG(_dev) ((const struct mcux_gpt_config *)(_dev)->config) +#define DEV_DATA(_dev) ((struct mcux_gpt_data *)(_dev)->data) + struct mcux_gpt_config { /* info must be first element */ struct counter_config_info info; + + DEVICE_MMIO_NAMED_ROM(gpt_mmio); + const struct device *clock_dev; clock_control_subsys_t clock_subsys; - GPT_Type *base; clock_name_t clock_source; }; struct mcux_gpt_data { + DEVICE_MMIO_NAMED_RAM(gpt_mmio); counter_alarm_callback_t alarm_callback; counter_top_callback_t top_callback; void *alarm_user_data; void *top_user_data; }; +static GPT_Type *get_base(const struct device *dev) +{ + return (GPT_Type *)DEVICE_MMIO_NAMED_GET(dev, gpt_mmio); +} + static int mcux_gpt_start(const struct device *dev) { - const struct mcux_gpt_config *config = dev->config; + GPT_Type *base = get_base(dev); - GPT_StartTimer(config->base); + GPT_StartTimer(base); return 0; } static int mcux_gpt_stop(const struct device *dev) { - const struct mcux_gpt_config *config = dev->config; + GPT_Type *base = get_base(dev); - GPT_StopTimer(config->base); + GPT_StopTimer(base); return 0; } static int mcux_gpt_get_value(const struct device *dev, uint32_t *ticks) { - const struct mcux_gpt_config *config = dev->config; + GPT_Type *base = get_base(dev); - *ticks = GPT_GetCurrentTimerCount(config->base); + *ticks = GPT_GetCurrentTimerCount(base); return 0; } static int mcux_gpt_set_alarm(const struct device *dev, uint8_t chan_id, const struct counter_alarm_cfg *alarm_cfg) { - const struct mcux_gpt_config *config = dev->config; + GPT_Type *base = get_base(dev); struct mcux_gpt_data *data = dev->data; - uint32_t current = GPT_GetCurrentTimerCount(config->base); + uint32_t current = GPT_GetCurrentTimerCount(base); uint32_t ticks = alarm_cfg->ticks; if (chan_id != 0) { @@ -82,16 +94,16 @@ static int mcux_gpt_set_alarm(const struct device *dev, uint8_t chan_id, data->alarm_callback = alarm_cfg->callback; data->alarm_user_data = alarm_cfg->user_data; - GPT_SetOutputCompareValue(config->base, kGPT_OutputCompare_Channel1, + GPT_SetOutputCompareValue(base, kGPT_OutputCompare_Channel1, ticks); - GPT_EnableInterrupts(config->base, kGPT_OutputCompare1InterruptEnable); + GPT_EnableInterrupts(base, kGPT_OutputCompare1InterruptEnable); return 0; } static int mcux_gpt_cancel_alarm(const struct device *dev, uint8_t chan_id) { - const struct mcux_gpt_config *config = dev->config; + GPT_Type *base = get_base(dev); struct mcux_gpt_data *data = dev->data; if (chan_id != 0) { @@ -99,7 +111,7 @@ static int mcux_gpt_cancel_alarm(const struct device *dev, uint8_t chan_id) return -EINVAL; } - GPT_DisableInterrupts(config->base, kGPT_OutputCompare1InterruptEnable); + GPT_DisableInterrupts(base, kGPT_OutputCompare1InterruptEnable); data->alarm_callback = NULL; return 0; @@ -107,18 +119,18 @@ static int mcux_gpt_cancel_alarm(const struct device *dev, uint8_t chan_id) void mcux_gpt_isr(const struct device *dev) { - const struct mcux_gpt_config *config = dev->config; + GPT_Type *base = get_base(dev); struct mcux_gpt_data *data = dev->data; - uint32_t current = GPT_GetCurrentTimerCount(config->base); + uint32_t current = GPT_GetCurrentTimerCount(base); uint32_t status; - status = GPT_GetStatusFlags(config->base, kGPT_OutputCompare1Flag | + status = GPT_GetStatusFlags(base, kGPT_OutputCompare1Flag | kGPT_RollOverFlag); - GPT_ClearStatusFlags(config->base, status); + GPT_ClearStatusFlags(base, status); barrier_dsync_fence_full(); if ((status & kGPT_OutputCompare1Flag) && data->alarm_callback) { - GPT_DisableInterrupts(config->base, + GPT_DisableInterrupts(base, kGPT_OutputCompare1InterruptEnable); counter_alarm_callback_t alarm_cb = data->alarm_callback; data->alarm_callback = NULL; @@ -132,15 +144,16 @@ void mcux_gpt_isr(const struct device *dev) static uint32_t mcux_gpt_get_pending_int(const struct device *dev) { - const struct mcux_gpt_config *config = dev->config; + GPT_Type *base = get_base(dev); - return GPT_GetStatusFlags(config->base, kGPT_OutputCompare1Flag); + return GPT_GetStatusFlags(base, kGPT_OutputCompare1Flag); } static int mcux_gpt_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg) { const struct mcux_gpt_config *config = dev->config; + GPT_Type *base = get_base(dev); struct mcux_gpt_data *data = dev->data; if (cfg->ticks != config->info.max_top_value) { @@ -152,7 +165,7 @@ static int mcux_gpt_set_top_value(const struct device *dev, data->top_callback = cfg->callback; data->top_user_data = cfg->user_data; - GPT_EnableInterrupts(config->base, kGPT_RollOverFlagInterruptEnable); + GPT_EnableInterrupts(base, kGPT_RollOverFlagInterruptEnable); return 0; } @@ -169,6 +182,9 @@ static int mcux_gpt_init(const struct device *dev) const struct mcux_gpt_config *config = dev->config; gpt_config_t gptConfig; uint32_t clock_freq; + GPT_Type *base; + + DEVICE_MMIO_NAMED_MAP(dev, gpt_mmio, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); if (!device_is_ready(config->clock_dev)) { LOG_ERR("clock control device not ready"); @@ -191,7 +207,8 @@ static int mcux_gpt_init(const struct device *dev) gptConfig.enableFreeRun = true; /* Do not reset on compare */ gptConfig.clockSource = kGPT_ClockSource_Periph; gptConfig.divider = clock_freq / config->info.freq; - GPT_Init(config->base, &gptConfig); + base = get_base(dev); + GPT_Init(base, &gptConfig); return 0; } @@ -211,7 +228,7 @@ static const struct counter_driver_api mcux_gpt_driver_api = { static struct mcux_gpt_data mcux_gpt_data_ ## n; \ \ static const struct mcux_gpt_config mcux_gpt_config_ ## n = { \ - .base = (void *)DT_INST_REG_ADDR(n), \ + DEVICE_MMIO_NAMED_ROM_INIT(gpt_mmio, DT_DRV_INST(n)), \ .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ .clock_subsys = \ (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\ From 46ce8741bd4b6eb5585f8b4385e3a89d3b3672f0 Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Tue, 6 Jul 2021 17:52:12 +0800 Subject: [PATCH 2027/2402] clock: mcux_ccm: add gpt ipg clock GPT IPG clock is using GPTx_CLK_ROOT. Signed-off-by: Jiafei Pan --- drivers/clock_control/clock_control_mcux_ccm.c | 11 +++++++++++ include/zephyr/dt-bindings/clock/imx_ccm.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/drivers/clock_control/clock_control_mcux_ccm.c b/drivers/clock_control/clock_control_mcux_ccm.c index 0b389819c46..c9fd6229bab 100644 --- a/drivers/clock_control/clock_control_mcux_ccm.c +++ b/drivers/clock_control/clock_control_mcux_ccm.c @@ -292,6 +292,17 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, case IMX_CCM_GPT_CLK: *rate = CLOCK_GetFreq(kCLOCK_PerClk); break; +#ifdef CONFIG_SOC_SERIES_IMX8M + case IMX_CCM_GPT_IPG_CLK: + { + uint32_t mux = CLOCK_GetRootMux(kCLOCK_RootGpt1); + + if (mux == 0) + *rate = OSC24M_CLK_FREQ; + else + *rate = 0; + } break; +#endif #endif #ifdef CONFIG_COUNTER_MCUX_QTMR diff --git a/include/zephyr/dt-bindings/clock/imx_ccm.h b/include/zephyr/dt-bindings/clock/imx_ccm.h index b57ca4aedca..7a4876cc43f 100644 --- a/include/zephyr/dt-bindings/clock/imx_ccm.h +++ b/include/zephyr/dt-bindings/clock/imx_ccm.h @@ -70,4 +70,6 @@ #define IMX_CCM_ECSPI2_CLK 0x1201UL #define IMX_CCM_ECSPI3_CLK 0x1202UL +#define IMX_CCM_GPT_IPG_CLK 0x1300UL + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */ From 212af1f33d52da85872a11c6f3067f901bbd885b Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Tue, 19 Mar 2024 15:00:15 +0800 Subject: [PATCH 2028/2402] dts: mimx8mp: add gpt counter device nodes Add GPT counter device nodes. Signed-off-by: Jiafei Pan --- dts/arm64/nxp/nxp_mimx8mp_a53.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi index 65933c366e0..9fdfa1d27f3 100644 --- a/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi @@ -78,6 +78,28 @@ #clock-cells = <3>; }; + gpt1: gpt@302d0000 { + compatible = "nxp,imx-gpt"; + reg = <0x302d0000 DT_SIZE_K(64)>; + interrupt-parent = <&gic>; + interrupts = ; + gptfreq = <24000000>; + clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x6C 20>; + status = "disabled"; + }; + + gpt2: gpt@302e0000 { + compatible = "nxp,imx-gpt"; + reg = <0x302e0000 DT_SIZE_K(64)>; + interrupt-parent = <&gic>; + interrupts = ; + gptfreq = <24000000>; + clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x68 24>; + status = "disabled"; + }; + uart2: uart@30890000 { compatible = "nxp,imx-iuart"; reg = <0x30890000 DT_SIZE_K(64)>; From f81cf5b61e7abca3415e9cd214fee108856ac41a Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Wed, 20 Mar 2024 16:09:31 +0800 Subject: [PATCH 2029/2402] dts: mimx8mm: add gpt counter device nodes Add dts node for GPT. Signed-off-by: Jiafei Pan --- dts/arm64/nxp/nxp_mimx8mm_a53.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi index 03d710396be..9c6564ce269 100644 --- a/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi @@ -72,6 +72,28 @@ status = "okay"; }; + gpt1: gpt@302d0000 { + compatible = "nxp,imx-gpt"; + reg = <0x302d0000 DT_SIZE_K(64)>; + interrupt-parent = <&gic>; + interrupts = ; + gptfreq = <24000000>; + clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x6C 20>; + status = "disabled"; + }; + + gpt2: gpt@302e0000 { + compatible = "nxp,imx-gpt"; + reg = <0x302e0000 DT_SIZE_K(64)>; + interrupt-parent = <&gic>; + interrupts = ; + gptfreq = <24000000>; + clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x68 24>; + status = "disabled"; + }; + iomuxc: iomuxc@30330000 { compatible = "nxp,imx-iomuxc"; reg = <0x30330000 DT_SIZE_K(64)>; From 21f0d9b3a98eeadad6d44c4a5b68c9e5237ef99f Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Wed, 20 Mar 2024 16:10:26 +0800 Subject: [PATCH 2030/2402] dts: mimx8mn: add gpt counter device nodes Add dts node for GPT counter. Signed-off-by: Jiafei Pan --- dts/arm64/nxp/nxp_mimx8mn_a53.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi index 0492b850f3e..ce7b840747b 100644 --- a/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi @@ -72,6 +72,28 @@ status = "okay"; }; + gpt1: gpt@302d0000 { + compatible = "nxp,imx-gpt"; + reg = <0x302d0000 DT_SIZE_K(64)>; + interrupt-parent = <&gic>; + interrupts = ; + gptfreq = <24000000>; + clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x6C 20>; + status = "disabled"; + }; + + gpt2: gpt@302e0000 { + compatible = "nxp,imx-gpt"; + reg = <0x302e0000 DT_SIZE_K(64)>; + interrupt-parent = <&gic>; + interrupts = ; + gptfreq = <24000000>; + clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x68 24>; + status = "disabled"; + }; + iomuxc: iomuxc@30330000 { compatible = "nxp,imx-iomuxc"; reg = <0x30330000 DT_SIZE_K(64)>; From 2e80cf4fd6b783166bf74a96ebac6d125ffaa8af Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Tue, 19 Mar 2024 17:00:54 +0800 Subject: [PATCH 2031/2402] tests: counter: add imx8mp evk support Add counter_basic_api application support on imx8mp_evk. Signed-off-by: Jiafei Pan --- .../boards/imx8mp_evk_mimx8ml8_a53.overlay | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 tests/drivers/counter/counter_basic_api/boards/imx8mp_evk_mimx8ml8_a53.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/imx8mp_evk_mimx8ml8_a53.overlay b/tests/drivers/counter/counter_basic_api/boards/imx8mp_evk_mimx8ml8_a53.overlay new file mode 100644 index 00000000000..d9820cd037c --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/imx8mp_evk_mimx8ml8_a53.overlay @@ -0,0 +1,9 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&gpt1 { + status = "okay"; +}; From a1000b514fe5f53ae3d2e8d7a0c57b5f77179169 Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Wed, 20 Mar 2024 16:11:27 +0800 Subject: [PATCH 2032/2402] tests: counter: add imx8mm evk support Add counter_basic_api application support on imx8mm_evk. Signed-off-by: Jiafei Pan --- .../boards/imx8mm_evk_mimx8mm6_a53.overlay | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 tests/drivers/counter/counter_basic_api/boards/imx8mm_evk_mimx8mm6_a53.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/imx8mm_evk_mimx8mm6_a53.overlay b/tests/drivers/counter/counter_basic_api/boards/imx8mm_evk_mimx8mm6_a53.overlay new file mode 100644 index 00000000000..d9820cd037c --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/imx8mm_evk_mimx8mm6_a53.overlay @@ -0,0 +1,9 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&gpt1 { + status = "okay"; +}; From f5fdc483e7ff14d29706f11fb546a5c72e0c7aa8 Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Wed, 20 Mar 2024 16:13:27 +0800 Subject: [PATCH 2033/2402] tests: counter: add imx8mn evk support Add counter_basic_api application support on imx8mn_evk. Signed-off-by: Jiafei Pan --- .../boards/imx8mn_evk_mimx8mn6_a53.overlay | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 tests/drivers/counter/counter_basic_api/boards/imx8mn_evk_mimx8mn6_a53.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/imx8mn_evk_mimx8mn6_a53.overlay b/tests/drivers/counter/counter_basic_api/boards/imx8mn_evk_mimx8mn6_a53.overlay new file mode 100644 index 00000000000..d9820cd037c --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/imx8mn_evk_mimx8mn6_a53.overlay @@ -0,0 +1,9 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&gpt1 { + status = "okay"; +}; From 11e50e750edc702f794a2fc63c3d13becd9e80fe Mon Sep 17 00:00:00 2001 From: Axel Haslam Date: Wed, 31 Jan 2024 14:29:47 +0100 Subject: [PATCH 2034/2402] drivers: usb: stm32: Dont disable ULPI clock on low power When running the cdc_acm demo on a board with an external ULPI phy, the device is unable to enumerate: usb 1-1.8.3.1: new full-speed USB device number 51 using ehci-pci usb 1-1.8.3.1: device descriptor read/64, error -32 usb 1-1.8.3.1: device descriptor read/64, error -32 the console shows: [00:00:00.001,000] cdc_acm_echo: Wait for DTR [00:00:00.007,000] usb_cdc_acm: Device suspended [00:00:00.902,000] usb_cdc_acm: Device resumed [00:00:00.902,000] usb_cdc_acm: from suspend [00:00:25.526,000] usb_cdc_acm: Device suspended By not disabling the ULPI clock in low power, the usb enumeration is working and we can run the cdc_acm demo. While touching this code, add some comments to clarify the macro nesting. Signed-off-by: Axel Haslam --- drivers/usb/device/usb_dc_stm32.c | 8 +++++--- drivers/usb/udc/udc_stm32.c | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c index 75ce9442f8e..ad9c6ac520c 100644 --- a/drivers/usb/device/usb_dc_stm32.c +++ b/drivers/usb/device/usb_dc_stm32.c @@ -276,14 +276,16 @@ static int usb_dc_stm32_clock_enable(void) */ LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI); #endif -#else +#else /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */ +#if !USB_OTG_HS_ULPI_PHY /* Disable ULPI interface (for external high-speed PHY) clock in low * power mode. It is disabled by default in run power mode, no need to * disable it. */ LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI); -#endif -#endif +#endif /* USB_OTG_HS_ULPI_PHY */ +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */ +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) */ return 0; } diff --git a/drivers/usb/udc/udc_stm32.c b/drivers/usb/udc/udc_stm32.c index e11228619b8..9b912f792c9 100644 --- a/drivers/usb/udc/udc_stm32.c +++ b/drivers/usb/udc/udc_stm32.c @@ -988,14 +988,16 @@ static int priv_clock_enable(void) */ LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI); #endif -#else +#else /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */ +#if !USB_OTG_HS_ULPI_PHY /* Disable ULPI interface (for external high-speed PHY) clock in low * power mode. It is disabled by default in run power mode, no need to * disable it. */ LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI); -#endif -#endif +#endif /* USB_OTG_HS_ULPI_PHY */ +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */ +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) */ return 0; } From 7726f27bc1a5b1c2f0287c892b4659959bed1885 Mon Sep 17 00:00:00 2001 From: Philip Molloy Date: Tue, 30 Jan 2024 12:28:26 +0100 Subject: [PATCH 2035/2402] boards: adi_sdp_k1: add usb cdc support This adds support for the usb cdc on the k1 board Tested using samples/subsys/usb/cdc_acm Co-developed-by: Axel Haslam Signed-off-by: Axel Haslam Signed-off-by: Philip Molloy --- boards/adi/sdp_k1/adi_sdp_k1.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/boards/adi/sdp_k1/adi_sdp_k1.dts b/boards/adi/sdp_k1/adi_sdp_k1.dts index 91aea8c60df..52c68f90c18 100644 --- a/boards/adi/sdp_k1/adi_sdp_k1.dts +++ b/boards/adi/sdp_k1/adi_sdp_k1.dts @@ -41,6 +41,12 @@ }; }; + otghs_ulpi_phy: otghs_ulpis_phy { + compatible = "usb-ulpi-phy"; + reset-gpios = <&gpiod 7 (GPIO_ACTIVE_LOW)>; + #phy-cells = <0>; + }; + aliases { led0 = &status_led; }; @@ -78,3 +84,25 @@ current-speed = <115200>; status = "okay"; }; + +zephyr_udc0: &usbotg_hs { + pinctrl-0 = <&usb_otg_hs_ulpi_ck_pa5 + &usb_otg_hs_ulpi_d0_pa3 + &usb_otg_hs_ulpi_d1_pb0 + &usb_otg_hs_ulpi_d2_pb1 + &usb_otg_hs_ulpi_d3_pb10 + &usb_otg_hs_ulpi_d4_pb11 + &usb_otg_hs_ulpi_d5_pb12 + &usb_otg_hs_ulpi_d6_pb13 + &usb_otg_hs_ulpi_d7_pb5 + &usb_otg_hs_ulpi_stp_pc0 + &usb_otg_hs_ulpi_dir_pc2 + &usb_otg_hs_ulpi_nxt_pc3>; + pinctrl-names = "default"; + maximum-speed = "high-speed"; + /* Enable OTGHSULPIEN rather than OTGHSEN */ + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x60000000>, + <&rcc STM32_SRC_PLL_Q NO_SEL>; + phys = <&otghs_ulpi_phy>; + status = "okay"; +}; From 197a0f39fb3a57c0164f846ccd11520fa37927ee Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Sun, 21 Jan 2024 22:44:08 +0100 Subject: [PATCH 2036/2402] teensy: add west flash teensy_loader_cli integration Adds loader, and flash target for teensy boards Signed-off-by: Peter van der Perk --- boards/common/teensy.board.cmake | 4 ++ boards/pjrc/teensy4/board.cmake | 11 ++++ scripts/west_commands/runners/__init__.py | 1 + scripts/west_commands/runners/teensy.py | 62 +++++++++++++++++++++++ 4 files changed, 78 insertions(+) create mode 100644 boards/common/teensy.board.cmake create mode 100644 boards/pjrc/teensy4/board.cmake create mode 100644 scripts/west_commands/runners/teensy.py diff --git a/boards/common/teensy.board.cmake b/boards/common/teensy.board.cmake new file mode 100644 index 00000000000..0b4d78eb35d --- /dev/null +++ b/boards/common/teensy.board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(teensy) +board_finalize_runner_args(teensy) diff --git a/boards/pjrc/teensy4/board.cmake b/boards/pjrc/teensy4/board.cmake new file mode 100644 index 00000000000..bd6ec2b59e0 --- /dev/null +++ b/boards/pjrc/teensy4/board.cmake @@ -0,0 +1,11 @@ +#SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(teensy) + +if(CONFIG_BOARD_TEENSY40) +board_runner_args(teensy "--mcu=TEENSY40") +else() +board_runner_args(teensy "--mcu=TEENSY41") +endif() + +include(${ZEPHYR_BASE}/boards/common/teensy.board.cmake) diff --git a/scripts/west_commands/runners/__init__.py b/scripts/west_commands/runners/__init__.py index 7e88d56edc4..aa5686f73b0 100644 --- a/scripts/west_commands/runners/__init__.py +++ b/scripts/west_commands/runners/__init__.py @@ -53,6 +53,7 @@ def _import_runner_module(runner_name): 'spi_burn', 'stm32cubeprogrammer', 'stm32flash', + 'teensy', 'trace32', 'uf2', 'xtensa', diff --git a/scripts/west_commands/runners/teensy.py b/scripts/west_commands/runners/teensy.py new file mode 100644 index 00000000000..a0854f619b2 --- /dev/null +++ b/scripts/west_commands/runners/teensy.py @@ -0,0 +1,62 @@ +# Copyright (c) 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +'''Runner for teensy .''' + +import os +import subprocess + +from runners.core import ZephyrBinaryRunner + +class TeensyBinaryRunner(ZephyrBinaryRunner): + '''Runner front-end for teensy.''' + + def __init__(self, cfg, mcu, teensy_loader): + super().__init__(cfg) + + self.mcu_args = ['--mcu', mcu] + self.teensy_loader = teensy_loader + self.hex_name = cfg.hex_file + + @classmethod + def name(cls): + return 'teensy' + + @classmethod + def do_add_parser(cls, parser): + parser.add_argument('--mcu', required=True, + help='Teensy mcu target') + parser.add_argument('--teensy', default='teensy_loader_cli', + help='path to teensy cli tool, default is teensy_loader_cli') + + @classmethod + def do_create(cls, cfg, args): + ret = TeensyBinaryRunner( + cfg, args.mcu, + teensy_loader=args.teensy) + return ret + + def do_run(self, command): + self.require(self.teensy_loader) + if command == 'flash': + self.flash() + + def flash(self): + if self.hex_name is not None and os.path.isfile(self.hex_name): + fname = self.hex_name + else: + raise ValueError( + 'Cannot flash; no hex ({}) file found. '.format(self.hex_name)) + + cmd = ([self.teensy_loader] + + self.mcu_args + + [fname]) + + self.logger.info('Flashing file: {}'.format(fname)) + + try: + self.check_output(cmd) + self.logger.info('Success') + except subprocess.CalledProcessError as grepexc: + self.logger.error("Failure %i" % grepexc.returncode) From 46cb2ad7c09cdfa97513779d741f93802e74dc25 Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Fri, 5 Apr 2024 14:54:17 +0200 Subject: [PATCH 2037/2402] west: add teensy loader test Adds test import for teensy_loader runner Signed-off-by: Peter van der Perk --- scripts/west_commands/tests/test_imports.py | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/west_commands/tests/test_imports.py b/scripts/west_commands/tests/test_imports.py index 89ca44c980b..b101ab42fe6 100644 --- a/scripts/west_commands/tests/test_imports.py +++ b/scripts/west_commands/tests/test_imports.py @@ -44,6 +44,7 @@ def test_runner_imports(): 'stm32cubeprogrammer', 'stm32flash', 'trace32', + 'teensy', 'uf2', 'xtensa')) assert runner_names == expected From 84a40778af81fad2d0e1a98e2919afc877a2a330 Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Thu, 15 Feb 2024 11:41:33 +0100 Subject: [PATCH 2038/2402] drivers: gpio: split up driver for TLE9104 into a MFD Split up the driver for the power train switch TLE9104 into a MFD and GPIO. Signed-off-by: Benedikt Schmidt --- drivers/gpio/Kconfig.tle9104 | 8 +- drivers/gpio/gpio_tle9104.c | 440 ++------------ drivers/mfd/CMakeLists.txt | 1 + drivers/mfd/Kconfig | 1 + drivers/mfd/Kconfig.tle9104 | 11 + drivers/mfd/mfd_tle9104.c | 570 +++++++++++++++++++ dts/bindings/gpio/infineon,tle9104-gpio.yaml | 27 + dts/bindings/gpio/infineon,tle9104.yaml | 49 -- dts/bindings/mfd/infineon,tle9104.yaml | 78 +++ include/zephyr/drivers/mfd/tle9104.h | 65 +++ tests/drivers/build_all/gpio/app.overlay | 12 +- tests/drivers/build_all/gpio/prj.conf | 3 + 12 files changed, 819 insertions(+), 446 deletions(-) create mode 100644 drivers/mfd/Kconfig.tle9104 create mode 100644 drivers/mfd/mfd_tle9104.c create mode 100644 dts/bindings/gpio/infineon,tle9104-gpio.yaml delete mode 100644 dts/bindings/gpio/infineon,tle9104.yaml create mode 100644 dts/bindings/mfd/infineon,tle9104.yaml create mode 100644 include/zephyr/drivers/mfd/tle9104.h diff --git a/drivers/gpio/Kconfig.tle9104 b/drivers/gpio/Kconfig.tle9104 index fd12710a5f5..92947976e49 100644 --- a/drivers/gpio/Kconfig.tle9104 +++ b/drivers/gpio/Kconfig.tle9104 @@ -1,15 +1,15 @@ # TLE9104 GPIO configuration options -# Copyright (c) 2023 SILA Embedded Solutions GmbH +# Copyright (c) 2024 SILA Embedded Solutions GmbH # SPDX-License-Identifier: Apache-2.0 menuconfig GPIO_TLE9104 bool "TLE9104 SPI-based powertrain switch" default y - depends on DT_HAS_INFINEON_TLE9104_ENABLED - depends on SPI + depends on DT_HAS_INFINEON_TLE9104_GPIO_ENABLED + select MFD help - Enable driver for TLE9104 SPI-based powertrain switch. + Enable GPIO driver for TLE9104 SPI-based powertrain switch. config GPIO_TLE9104_INIT_PRIORITY int "Init priority" diff --git a/drivers/gpio/gpio_tle9104.c b/drivers/gpio/gpio_tle9104.c index 47a899e1615..9108c4d916a 100644 --- a/drivers/gpio/gpio_tle9104.c +++ b/drivers/gpio/gpio_tle9104.c @@ -1,251 +1,43 @@ /* - * Copyright (c) 2023 SILA Embedded Solutions GmbH + * Copyright (c) 2024 SILA Embedded Solutions GmbH * * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT infineon_tle9104 +#define DT_DRV_COMPAT infineon_tle9104_gpio #include - #include #include #include #include #include -#include +#include #include -#include LOG_MODULE_REGISTER(gpio_tle9104, CONFIG_GPIO_LOG_LEVEL); -/* - * The values for the defines below as well as the register definitions were - * taken from the datasheet, which can be found at: - * https://www.infineon.com/dgdl/Infineon-TLE9104SH-DataSheet-v01_31-EN.pdf?fileId=5546d462766cbe86017676144d76581b - */ -#define TLE9104_RESET_DURATION_TIME_US 10 -#define TLE9104_RESET_DURATION_WAIT_TIME_SAFETY_MARGIN_US 200 -#define TLE9104_RESET_DURATION_WAIT_TIME_US 10 -#define TLE9104_GPIO_COUNT 4 -#define TLE9104_INITIALIZATION_TIMEOUT_MS 1 -#define TLE9104_ICVERSIONID 0xB1 - -#define TLE9104_FRAME_RW_POS 15 -#define TLE9104_FRAME_PARITY_POS 14 -#define TLE9104_FRAME_FAULTCOMMUNICATION_POS 13 -#define TLE9104_FRAME_FAULTGLOBAL_POS 12 -#define TLE9104_FRAME_ADDRESS_POS 8 -#define TLE9104_FRAME_DATA_POS 0 - -#define TLE9104_CFG_CWDTIME_LENGTH 2 -#define TLE9104_CFG_CWDTIME_POS 6 - -#define TLE9104_CTRL_OUT1ONS_BIT BIT(1) -#define TLE9104_CTRL_OUT1ONC_BIT BIT(0) -#define TLE9104_CFG_OUT1DD_BIT BIT(0) -#define TLE9104_GLOBALSTATUS_OUTEN_BIT BIT(7) -#define TLE9104_GLOBALSTATUS_POR_LATCH_BIT BIT(0) -#define TLE9104_SPIFRAME_FAULTCOMMUNICATION_BIT BIT(13) - -enum tle9104_register { - TLE9104REGISTER_CTRL = 0x00, - TLE9104REGISTER_CFG = 0x01, - TLE9104REGISTER_GLOBALSTATUS = 0x07, - TLE9104REGISTER_ICVID = 0x08, -}; - -struct tle9104_config { +struct tle9104_gpio_config { /* gpio_driver_config needs to be first */ struct gpio_driver_config common; - - struct spi_dt_spec bus; - const struct gpio_dt_spec gpio_reset; - const struct gpio_dt_spec gpio_enable; - const struct gpio_dt_spec gpio_control[TLE9104_GPIO_COUNT]; + /* parent MFD */ + const struct device *parent; }; -struct tle9104_data { +struct tle9104_gpio_data { /* gpio_driver_data needs to be first */ struct gpio_driver_data common; /* each bit is one output channel, bit 0 = OUT1, ... */ uint8_t state; - /* same as state, just kept for checking what has to be updated */ - uint8_t previous_state; /* each bit defines if the output channel is configured, see state */ uint8_t configured; struct k_mutex lock; - /* communication watchdog is getting ignored */ - bool cwd_ignore; }; -static void tle9104_set_cfg_cwdtime(uint8_t *destination, uint8_t value) -{ - uint8_t length = TLE9104_CFG_CWDTIME_LENGTH; - uint8_t pos = TLE9104_CFG_CWDTIME_POS; - - *destination &= ~GENMASK(pos + length - 1, pos); - *destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value); -} - -static int tle9104_calculate_parity(uint16_t value) -{ - int parity = 1 + POPCOUNT(value); - - if ((value & BIT(TLE9104_FRAME_PARITY_POS)) != 0) { - parity--; - } - - return parity % 2; -} - -static void tle9104_apply_parity(uint16_t *value) -{ - int parity = tle9104_calculate_parity(*value); - - WRITE_BIT(*value, TLE9104_FRAME_PARITY_POS, parity); -} - -static bool tle9104_check_parity(uint16_t value) -{ - int parity = tle9104_calculate_parity(value); - - return ((value & BIT(TLE9104_FRAME_PARITY_POS)) >> TLE9104_FRAME_PARITY_POS) == parity; -} - -static int tle9104_transceive_frame(const struct device *dev, bool write, - enum tle9104_register write_reg, uint8_t write_data, - enum tle9104_register *read_reg, uint8_t *read_data) -{ - const struct tle9104_config *config = dev->config; - struct tle9104_data *data = dev->data; - uint16_t write_frame; - uint16_t read_frame; - int result; - uint8_t buffer_tx[2]; - uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)]; - const struct spi_buf tx_buf[] = {{ - .buf = buffer_tx, - .len = ARRAY_SIZE(buffer_tx), - }}; - const struct spi_buf rx_buf[] = {{ - .buf = buffer_rx, - .len = ARRAY_SIZE(buffer_rx), - }}; - const struct spi_buf_set tx = { - .buffers = tx_buf, - .count = ARRAY_SIZE(tx_buf), - }; - const struct spi_buf_set rx = { - .buffers = rx_buf, - .count = ARRAY_SIZE(rx_buf), - }; - - write_frame = write_data << TLE9104_FRAME_DATA_POS; - write_frame |= write_reg << TLE9104_FRAME_ADDRESS_POS; - WRITE_BIT(write_frame, TLE9104_FRAME_RW_POS, write); - tle9104_apply_parity(&write_frame); - sys_put_be16(write_frame, buffer_tx); - LOG_DBG("writing in register 0x%02X of TLE9104 value 0x%02X, complete frame 0x%04X", - write_reg, write_data, write_frame); - - result = spi_transceive_dt(&config->bus, &tx, &rx); - if (result != 0) { - LOG_ERR("spi_write failed with error %i", result); - return result; - } - - read_frame = sys_get_be16(buffer_rx); - LOG_DBG("received complete frame 0x%04X", read_frame); - - if (!tle9104_check_parity(read_frame)) { - LOG_ERR("parity check for received frame of TLE9104 failed"); - return -EIO; - } - - if (!data->cwd_ignore) { - if ((TLE9104_SPIFRAME_FAULTCOMMUNICATION_BIT & read_frame) != 0) { - LOG_WRN("%s: communication fault reported by TLE9104", dev->name); - } - } - - *read_reg = FIELD_GET(GENMASK(TLE9104_FRAME_FAULTGLOBAL_POS - 1, TLE9104_FRAME_ADDRESS_POS), - read_frame); - *read_data = FIELD_GET(GENMASK(TLE9104_FRAME_ADDRESS_POS - 1, TLE9104_FRAME_DATA_POS), - read_frame); - - return 0; -} - -static int tle9104_write_register(const struct device *dev, enum tle9104_register reg, - uint8_t value) -{ - enum tle9104_register read_reg; - uint8_t read_data; - - return tle9104_transceive_frame(dev, true, reg, value, &read_reg, &read_data); -} - -static int tle9104_write_state(const struct device *dev) +static int tle9104_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) { - const struct tle9104_config *config = dev->config; - struct tle9104_data *data = dev->data; - bool spi_update_required = false; - uint8_t register_ctrl = 0x00; - int result; - - LOG_DBG("writing state 0x%02X to TLE9104", data->state); - - for (size_t i = 0; i < TLE9104_GPIO_COUNT; ++i) { - uint8_t mask = GENMASK(i, i); - bool current_value = (data->state & mask) != 0; - bool previous_value = (data->previous_state & mask) != 0; - - /* - * Setting the OUTx_ON bits results in a high impedance output, - * clearing them pulls the output to ground. Therefore the - * meaning here is intentionally inverted, as this will then turn - * out for a low active open drain output to be pulled to ground - * if set to off. - */ - if (current_value == 0) { - register_ctrl |= TLE9104_CTRL_OUT1ONS_BIT << (2 * i); - } else { - register_ctrl |= TLE9104_CTRL_OUT1ONC_BIT << (2 * i); - } - - if (current_value == previous_value) { - continue; - } - - if (config->gpio_control[i].port == NULL) { - spi_update_required = true; - continue; - } - - result = gpio_pin_set_dt(&config->gpio_control[i], current_value); - if (result != 0) { - LOG_ERR("unable to set control GPIO"); - return result; - } - } - - if (spi_update_required) { - result = tle9104_write_register(dev, TLE9104REGISTER_CTRL, register_ctrl); - if (result != 0) { - LOG_ERR("unable to set control register"); - return result; - } - } - - data->previous_state = data->state; - - return 0; -} - -static int tle9104_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) -{ - struct tle9104_data *data = dev->data; + const struct tle9104_gpio_config *config = dev->config; + struct tle9104_gpio_data *data = dev->data; int result; /* cannot execute a bus operation in an ISR context */ @@ -297,13 +89,13 @@ static int tle9104_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ } WRITE_BIT(data->configured, pin, 1); - result = tle9104_write_state(dev); + result = tle9104_write_state(config->parent, data->state); k_mutex_unlock(&data->lock); return result; } -static int tle9104_port_get_raw(const struct device *dev, uint32_t *value) +static int tle9104_gpio_port_get_raw(const struct device *dev, uint32_t *value) { ARG_UNUSED(dev); ARG_UNUSED(value); @@ -312,9 +104,10 @@ static int tle9104_port_get_raw(const struct device *dev, uint32_t *value) return -ENOTSUP; } -static int tle9104_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value) +static int tle9104_gpio_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value) { - struct tle9104_data *data = dev->data; + const struct tle9104_gpio_config *config = dev->config; + struct tle9104_gpio_data *data = dev->data; int result; /* cannot execute a bus operation in an ISR context */ @@ -324,25 +117,26 @@ static int tle9104_port_set_masked_raw(const struct device *dev, uint32_t mask, k_mutex_lock(&data->lock, K_FOREVER); data->state = (data->state & ~mask) | (mask & value); - result = tle9104_write_state(dev); + result = tle9104_write_state(config->parent, data->state); k_mutex_unlock(&data->lock); return result; } -static int tle9104_port_set_bits_raw(const struct device *dev, uint32_t mask) +static int tle9104_gpio_port_set_bits_raw(const struct device *dev, uint32_t mask) { - return tle9104_port_set_masked_raw(dev, mask, mask); + return tle9104_gpio_port_set_masked_raw(dev, mask, mask); } -static int tle9104_port_clear_bits_raw(const struct device *dev, uint32_t mask) +static int tle9104_gpio_port_clear_bits_raw(const struct device *dev, uint32_t mask) { - return tle9104_port_set_masked_raw(dev, mask, 0); + return tle9104_gpio_port_set_masked_raw(dev, mask, 0); } -static int tle9104_port_toggle_bits(const struct device *dev, uint32_t mask) +static int tle9104_gpio_port_toggle_bits(const struct device *dev, uint32_t mask) { - struct tle9104_data *data = dev->data; + const struct tle9104_gpio_config *config = dev->config; + struct tle9104_gpio_data *data = dev->data; int result; /* cannot execute a bus operation in an ISR context */ @@ -352,14 +146,14 @@ static int tle9104_port_toggle_bits(const struct device *dev, uint32_t mask) k_mutex_lock(&data->lock, K_FOREVER); data->state ^= mask; - result = tle9104_write_state(dev); + result = tle9104_write_state(config->parent, data->state); k_mutex_unlock(&data->lock); return result; } -static int tle9104_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, - enum gpio_int_mode mode, enum gpio_int_trig trig) +static int tle9104_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, + enum gpio_int_mode mode, enum gpio_int_trig trig) { ARG_UNUSED(dev); ARG_UNUSED(pin); @@ -369,183 +163,49 @@ static int tle9104_pin_interrupt_configure(const struct device *dev, gpio_pin_t } static const struct gpio_driver_api api_table = { - .pin_configure = tle9104_pin_configure, - .port_get_raw = tle9104_port_get_raw, - .port_set_masked_raw = tle9104_port_set_masked_raw, - .port_set_bits_raw = tle9104_port_set_bits_raw, - .port_clear_bits_raw = tle9104_port_clear_bits_raw, - .port_toggle_bits = tle9104_port_toggle_bits, - .pin_interrupt_configure = tle9104_pin_interrupt_configure, + .pin_configure = tle9104_gpio_pin_configure, + .port_get_raw = tle9104_gpio_port_get_raw, + .port_set_masked_raw = tle9104_gpio_port_set_masked_raw, + .port_set_bits_raw = tle9104_gpio_port_set_bits_raw, + .port_clear_bits_raw = tle9104_gpio_port_clear_bits_raw, + .port_toggle_bits = tle9104_gpio_port_toggle_bits, + .pin_interrupt_configure = tle9104_gpio_pin_interrupt_configure, }; -static int tle9104_init(const struct device *dev) +static int tle9104_gpio_init(const struct device *dev) { - const struct tle9104_config *config = dev->config; - struct tle9104_data *data = dev->data; - uint8_t register_cfg; - uint8_t register_globalstatus; - uint8_t register_icvid; - enum tle9104_register read_reg; - int result; - - LOG_DBG("initialize TLE9104 instance %s", dev->name); - - data->cwd_ignore = true; + const struct tle9104_gpio_config *config = dev->config; + struct tle9104_gpio_data *data = dev->data; - result = k_mutex_init(&data->lock); - if (result != 0) { - LOG_ERR("unable to initialize mutex"); - return result; - } - - if (!spi_is_ready_dt(&config->bus)) { - LOG_ERR("SPI bus %s is not ready", config->bus.bus->name); - return -ENODEV; - } + LOG_DBG("initialize TLE9104 GPIO instance %s", dev->name); - register_cfg = 0x00; - - for (int i = 0; i < TLE9104_GPIO_COUNT; ++i) { - const struct gpio_dt_spec *current = config->gpio_control + i; - - if (current->port == NULL) { - LOG_DBG("got no control port for output %i, will control it via SPI", i); - continue; - } - - register_cfg |= TLE9104_CFG_OUT1DD_BIT << i; - - if (!gpio_is_ready_dt(current)) { - LOG_ERR("%s: control GPIO is not ready", dev->name); - return -ENODEV; - } - - result = gpio_pin_configure_dt(current, GPIO_OUTPUT_INACTIVE); - if (result != 0) { - LOG_ERR("failed to initialize control GPIO %i", i); - return result; - } - } - - if (config->gpio_enable.port != NULL) { - if (!gpio_is_ready_dt(&config->gpio_enable)) { - LOG_ERR("%s: enable GPIO is not ready", dev->name); - return -ENODEV; - } - - result = gpio_pin_configure_dt(&config->gpio_enable, GPIO_OUTPUT_ACTIVE); - if (result != 0) { - LOG_ERR("failed to enable TLE9104"); - return result; - } - } - - if (config->gpio_reset.port != NULL) { - if (!gpio_is_ready_dt(&config->gpio_reset)) { - LOG_ERR("%s: reset GPIO is not yet ready", dev->name); - return -ENODEV; - } - - result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE); - if (result != 0) { - LOG_ERR("failed to initialize GPIO for reset"); - return result; - } - - k_busy_wait(TLE9104_RESET_DURATION_TIME_US); - gpio_pin_set_dt(&config->gpio_reset, 0); - k_busy_wait(TLE9104_RESET_DURATION_WAIT_TIME_US + - TLE9104_RESET_DURATION_WAIT_TIME_SAFETY_MARGIN_US); - } - - /* - * The first read value should be the ICVID, this acts also as the setup of the - * global status register address. - */ - result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_GLOBALSTATUS, 0x00, &read_reg, - ®ister_icvid); - if (result != 0) { - return result; - } - - if (read_reg != TLE9104REGISTER_ICVID) { - LOG_ERR("expected to read register ICVID, got instead 0x%02X", read_reg); - return -EIO; - } - - if (register_icvid != TLE9104_ICVERSIONID) { - LOG_ERR("got unexpected IC version id 0x%02X", register_icvid); - return -EIO; - } - - result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_GLOBALSTATUS, 0x00, &read_reg, - ®ister_globalstatus); - if (result != 0) { - return result; - } - - if (read_reg != TLE9104REGISTER_GLOBALSTATUS) { - LOG_ERR("expected to read register GLOBALSTATUS, got instead 0x%02X", read_reg); - return -EIO; - } - - if ((register_globalstatus & TLE9104_GLOBALSTATUS_POR_LATCH_BIT) == 0) { - LOG_ERR("no power on reset detected"); - return -EIO; - } - - result = tle9104_write_register(dev, TLE9104REGISTER_CFG, register_cfg); - if (result != 0) { - LOG_ERR("unable to write configuration"); - return result; + if (!device_is_ready(config->parent)) { + LOG_ERR("%s: parent MFD is not ready", dev->name); + return -EINVAL; } - register_globalstatus = 0x00; - /* disable communication watchdog */ - tle9104_set_cfg_cwdtime(®ister_cfg, 0); - /* enable outputs */ - register_globalstatus |= TLE9104_GLOBALSTATUS_OUTEN_BIT; - - result = tle9104_write_register(dev, TLE9104REGISTER_GLOBALSTATUS, register_globalstatus); + int result = k_mutex_init(&data->lock); if (result != 0) { - LOG_ERR("unable to write global status"); + LOG_ERR("unable to initialize mutex"); return result; } - data->cwd_ignore = false; - return 0; } -BUILD_ASSERT(CONFIG_GPIO_TLE9104_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY, - "TLE9104 must be initialized after SPI"); - -#define TLE9104_INIT_GPIO_FIELDS(inst, gpio) \ - COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, gpio), \ - (GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(inst), gpio, 0)), ({0})) - -#define TLE9104_INIT(inst) \ - static const struct tle9104_config tle9104_##inst##_config = { \ +#define TLE9104_GPIO_INIT(inst) \ + static const struct tle9104_gpio_config tle9104_gpio_##inst##_config = { \ .common = { \ - .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \ - }, \ - .bus = SPI_DT_SPEC_INST_GET( \ - inst, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \ - .gpio_enable = TLE9104_INIT_GPIO_FIELDS(inst, en_gpios), \ - .gpio_reset = TLE9104_INIT_GPIO_FIELDS(inst, resn_gpios), \ - .gpio_control = { \ - TLE9104_INIT_GPIO_FIELDS(inst, in1_gpios), \ - TLE9104_INIT_GPIO_FIELDS(inst, in2_gpios), \ - TLE9104_INIT_GPIO_FIELDS(inst, in3_gpios), \ - TLE9104_INIT_GPIO_FIELDS(inst, in4_gpios), \ + .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \ }, \ + .parent = DEVICE_DT_GET(DT_PARENT(DT_DRV_INST(inst))), \ }; \ \ - static struct tle9104_data tle9104_##inst##_drvdata; \ + static struct tle9104_gpio_data tle9104_gpio_##inst##_drvdata; \ \ /* This has to be initialized after the SPI peripheral. */ \ - DEVICE_DT_INST_DEFINE(inst, tle9104_init, NULL, &tle9104_##inst##_drvdata, \ - &tle9104_##inst##_config, POST_KERNEL, \ + DEVICE_DT_INST_DEFINE(inst, tle9104_gpio_init, NULL, &tle9104_gpio_##inst##_drvdata, \ + &tle9104_gpio_##inst##_config, POST_KERNEL, \ CONFIG_GPIO_TLE9104_INIT_PRIORITY, &api_table); -DT_INST_FOREACH_STATUS_OKAY(TLE9104_INIT) +DT_INST_FOREACH_STATUS_OKAY(TLE9104_GPIO_INIT) diff --git a/drivers/mfd/CMakeLists.txt b/drivers/mfd/CMakeLists.txt index 486d37f611d..bcd9b190e15 100644 --- a/drivers/mfd/CMakeLists.txt +++ b/drivers/mfd/CMakeLists.txt @@ -14,3 +14,4 @@ zephyr_library_sources_ifdef(CONFIG_MFD_AD559X_BUS_SPI mfd_ad559x_spi.c) zephyr_library_sources_ifdef(CONFIG_MFD_MAX31790 mfd_max31790.c) zephyr_library_sources_ifdef(CONFIG_NXP_LP_FLEXCOMM mfd_nxp_lp_flexcomm.c) zephyr_library_sources_ifdef(CONFIG_MFD_BD8LB600FS mfd_bd8lb600fs.c) +zephyr_library_sources_ifdef(CONFIG_MFD_TLE9104 mfd_tle9104.c) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index f24d9378dcd..b487c3556b0 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -27,5 +27,6 @@ source "drivers/mfd/Kconfig.nct38xx" source "drivers/mfd/Kconfig.npm1300" source "drivers/mfd/Kconfig.npm6001" source "drivers/mfd/Kconfig.lpflexcomm" +source "drivers/mfd/Kconfig.tle9104" endif # MFD diff --git a/drivers/mfd/Kconfig.tle9104 b/drivers/mfd/Kconfig.tle9104 new file mode 100644 index 00000000000..8432e067adb --- /dev/null +++ b/drivers/mfd/Kconfig.tle9104 @@ -0,0 +1,11 @@ +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX -License-Identifier: Apache-2.0 + +config MFD_TLE9104 + bool "Infineon TLE9104 SPI powertrain switch" + default y + depends on DT_HAS_INFINEON_TLE9104_ENABLED + # using select SPI at this point introduces a cyclic dependency + depends on SPI + help + Enable driver for TLE9104 SPI-based powertrain switch. diff --git a/drivers/mfd/mfd_tle9104.c b/drivers/mfd/mfd_tle9104.c new file mode 100644 index 00000000000..3170a97d8f7 --- /dev/null +++ b/drivers/mfd/mfd_tle9104.c @@ -0,0 +1,570 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT infineon_tle9104 + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The values for the defines below as well as the register definitions were + * taken from the datasheet, which can be found at: + * https://www.infineon.com/dgdl/Infineon-TLE9104SH-DataSheet-v01_31-EN.pdf?fileId=5546d462766cbe86017676144d76581b + */ +#define TLE9104_RESET_DURATION_TIME_US 10 +#define TLE9104_RESET_DURATION_WAIT_TIME_SAFETY_MARGIN_US 200 +#define TLE9104_RESET_DURATION_WAIT_TIME_US 10 +#define TLE9104_INITIALIZATION_TIMEOUT_MS 1 +#define TLE9104_ICVERSIONID 0xB1 + +#define TLE9104_FRAME_RW_POS 15 +#define TLE9104_FRAME_PARITY_POS 14 +#define TLE9104_FRAME_FAULTCOMMUNICATION_POS 13 +#define TLE9104_FRAME_FAULTGLOBAL_POS 12 +#define TLE9104_FRAME_ADDRESS_POS 8 +#define TLE9104_FRAME_DATA_POS 0 + +#define TLE9104_CFG_CWDTIME_LENGTH 2 +#define TLE9104_CFG_CWDTIME_POS 6 + +#define TLE9104_OFFDIAGCFG_DIAGFILTCFG_LENGTH 2 +#define TLE9104_OFFDIAGCFG_DIAGFILTCFG_POS 4 +#define TLE9104_OFFDIAGCFG_OUT4DIAGEN_BIT BIT(3) +#define TLE9104_OFFDIAGCFG_OUT3DIAGEN_BIT BIT(2) +#define TLE9104_OFFDIAGCFG_OUT2DIAGEN_BIT BIT(1) +#define TLE9104_OFFDIAGCFG_OUT1DIAGEN_BIT BIT(0) + +#define TLE9104_ONDIAGCFG_OCFILTCFG_LENGTH 3 +#define TLE9104_ONDIAGCFG_OCFILTCFG_POS 2 +#define TLE9104_ONDIAGCFG_OCTH_LENGTH 2 +#define TLE9104_ONDIAGCFG_OCTH_POS 0 + +#define TLE9104_DIAGOUT12ON_OUT2STAT_BIT BIT(7) +#define TLE9104_DIAGOUT12ON_OUT1STAT_BIT BIT(6) +#define TLE9104_DIAGOUT12ON_DIAGCH2ON_LENGTH 3 +#define TLE9104_DIAGOUT12ON_DIAGCH2ON_POS 3 +#define TLE9104_DIAGOUT12ON_DIAGCH1ON_LENGTH 3 +#define TLE9104_DIAGOUT12ON_DIAGCH1ON_POS 0 + +#define TLE9104_DIAGOUT34ON_OUT4STAT_BIT BIT(7) +#define TLE9104_DIAGOUT34ON_OUT3STAT_BIT BIT(6) +#define TLE9104_DIAGOUT34ON_DIAGCH4ON_LENGTH 3 +#define TLE9104_DIAGOUT34ON_DIAGCH4ON_POS 3 +#define TLE9104_DIAGOUT34ON_DIAGCH3ON_LENGTH 3 +#define TLE9104_DIAGOUT34ON_DIAGCH3ON_POS 0 + +#define TLE9104_DIAGOFF_DIAGCH4OFF_LENGTH 2 +#define TLE9104_DIAGOFF_DIAGCH4OFF_POS 6 +#define TLE9104_DIAGOFF_DIAGCH3OFF_LENGTH 2 +#define TLE9104_DIAGOFF_DIAGCH3OFF_POS 4 +#define TLE9104_DIAGOFF_DIAGCH2OFF_LENGTH 2 +#define TLE9104_DIAGOFF_DIAGCH2OFF_POS 2 +#define TLE9104_DIAGOFF_DIAGCH1OFF_LENGTH 2 +#define TLE9104_DIAGOFF_DIAGCH1OFF_POS 0 + +#define TLE9104_CTRL_OUT1ONS_BIT BIT(1) +#define TLE9104_CTRL_OUT1ONC_BIT BIT(0) +#define TLE9104_CFG_OUT1DD_BIT BIT(0) +#define TLE9104_GLOBALSTATUS_OUTEN_BIT BIT(7) +#define TLE9104_GLOBALSTATUS_POR_LATCH_BIT BIT(0) +#define TLE9104_SPIFRAME_FAULTCOMMUNICATION_BIT BIT(13) + +enum tle9104_register { + TLE9104REGISTER_CTRL = 0x00, + TLE9104REGISTER_CFG = 0x01, + TLE9104REGISTER_OFFDIAGCFG = 0x02, + TLE9104REGISTER_ONDIAGCFG = 0x03, + TLE9104REGISTER_DIAGOUT12ON = 0x04, + TLE9104REGISTER_DIAGOUT34ON = 0x05, + TLE9104REGISTER_DIAGOFF = 0x06, + TLE9104REGISTER_GLOBALSTATUS = 0x07, + TLE9104REGISTER_ICVID = 0x08, +}; + +LOG_MODULE_REGISTER(infineon_tle9104, CONFIG_MFD_LOG_LEVEL); + +struct tle9104_config { + struct spi_dt_spec bus; + const struct gpio_dt_spec gpio_reset; + const struct gpio_dt_spec gpio_enable; + const struct gpio_dt_spec gpio_control[TLE9104_GPIO_COUNT]; + uint16_t diagnostic_filter_time; + uint16_t overcurrent_shutdown_delay_time; + uint16_t overcurrent_shutdown_threshold; +}; + +struct tle9104_data { + /* communication watchdog is getting ignored */ + bool cwd_ignore; + /* each bit is one output channel, bit 0 = OUT1, ... */ + uint8_t previous_state; + struct k_mutex lock; +}; + +static void tle9104_set_register_bits(uint8_t *destination, uint8_t pos, uint8_t length, + uint8_t value) +{ + *destination &= ~GENMASK(pos + length - 1, pos); + *destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value); +} + +static uint8_t tle9104_get_register_bits(uint8_t value, uint8_t pos, uint8_t length) +{ + return FIELD_GET(GENMASK(pos + length - 1, pos), value); +} + +static int tle9104_calculate_parity(uint16_t value) +{ + int parity = 1 + POPCOUNT(value); + + if ((value & BIT(TLE9104_FRAME_PARITY_POS)) != 0) { + parity--; + } + + return parity % 2; +} + +static void tle9104_apply_parity(uint16_t *value) +{ + int parity = tle9104_calculate_parity(*value); + + WRITE_BIT(*value, TLE9104_FRAME_PARITY_POS, parity); +} + +static bool tle9104_check_parity(uint16_t value) +{ + int parity = tle9104_calculate_parity(value); + + return ((value & BIT(TLE9104_FRAME_PARITY_POS)) >> TLE9104_FRAME_PARITY_POS) == parity; +} + +static int tle9104_transceive_frame(const struct device *dev, bool write, + enum tle9104_register write_reg, uint8_t write_data, + enum tle9104_register *read_reg, uint8_t *read_data) +{ + const struct tle9104_config *config = dev->config; + struct tle9104_data *data = dev->data; + uint16_t write_frame; + uint16_t read_frame; + int result; + uint8_t buffer_tx[2]; + uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)]; + const struct spi_buf tx_buf[] = {{ + .buf = buffer_tx, + .len = ARRAY_SIZE(buffer_tx), + }}; + const struct spi_buf rx_buf[] = {{ + .buf = buffer_rx, + .len = ARRAY_SIZE(buffer_rx), + }}; + const struct spi_buf_set tx = { + .buffers = tx_buf, + .count = ARRAY_SIZE(tx_buf), + }; + const struct spi_buf_set rx = { + .buffers = rx_buf, + .count = ARRAY_SIZE(rx_buf), + }; + + write_frame = write_data << TLE9104_FRAME_DATA_POS; + write_frame |= write_reg << TLE9104_FRAME_ADDRESS_POS; + WRITE_BIT(write_frame, TLE9104_FRAME_RW_POS, write); + tle9104_apply_parity(&write_frame); + sys_put_be16(write_frame, buffer_tx); + LOG_DBG("writing in register 0x%02X of TLE9104 value 0x%02X, complete frame 0x%04X", + write_reg, write_data, write_frame); + + result = spi_transceive_dt(&config->bus, &tx, &rx); + if (result != 0) { + LOG_ERR("spi_write failed with error %i", result); + return result; + } + + read_frame = sys_get_be16(buffer_rx); + LOG_DBG("received complete frame 0x%04X", read_frame); + + if (!tle9104_check_parity(read_frame)) { + LOG_ERR("parity check for received frame of TLE9104 failed"); + return -EIO; + } + + if (!data->cwd_ignore) { + if ((TLE9104_SPIFRAME_FAULTCOMMUNICATION_BIT & read_frame) != 0) { + LOG_WRN("%s: communication fault reported by TLE9104", dev->name); + } + } + + *read_reg = FIELD_GET(GENMASK(TLE9104_FRAME_FAULTGLOBAL_POS - 1, TLE9104_FRAME_ADDRESS_POS), + read_frame); + *read_data = FIELD_GET(GENMASK(TLE9104_FRAME_ADDRESS_POS - 1, TLE9104_FRAME_DATA_POS), + read_frame); + + return 0; +} + +static int tle9104_write_register(const struct device *dev, enum tle9104_register reg, + uint8_t value) +{ + enum tle9104_register read_reg; + uint8_t read_data; + + return tle9104_transceive_frame(dev, true, reg, value, &read_reg, &read_data); +} + +static int tle9104_write_state_internal(const struct device *dev, uint8_t state) +{ + const struct tle9104_config *config = dev->config; + struct tle9104_data *data = dev->data; + bool spi_update_required = false; + uint8_t register_ctrl = 0x00; + int result; + + LOG_DBG("writing state 0x%02X to TLE9104", state); + + for (size_t i = 0; i < TLE9104_GPIO_COUNT; ++i) { + uint8_t mask = GENMASK(i, i); + bool current_value = (state & mask) != 0; + bool previous_value = (data->previous_state & mask) != 0; + + /* + * Setting the OUTx_ON bits results in a high impedance output, + * clearing them pulls the output to ground. Therefore the + * meaning here is intentionally inverted, as this will then turn + * out for a low active open drain output to be pulled to ground + * if set to off. + */ + if (current_value == 0) { + register_ctrl |= TLE9104_CTRL_OUT1ONS_BIT << (2 * i); + } else { + register_ctrl |= TLE9104_CTRL_OUT1ONC_BIT << (2 * i); + } + + if (current_value == previous_value) { + continue; + } + + if (config->gpio_control[i].port == NULL) { + spi_update_required = true; + continue; + } + + result = gpio_pin_set_dt(&config->gpio_control[i], current_value); + if (result != 0) { + LOG_ERR("unable to set control GPIO"); + return result; + } + } + + if (spi_update_required) { + result = tle9104_write_register(dev, TLE9104REGISTER_CTRL, register_ctrl); + if (result != 0) { + LOG_ERR("unable to set control register"); + return result; + } + } + + data->previous_state = state; + + return 0; +} + +int tle9104_write_state(const struct device *dev, uint8_t state) +{ + struct tle9104_data *data = dev->data; + int result; + + k_mutex_lock(&data->lock, K_FOREVER); + result = tle9104_write_state_internal(dev, state); + k_mutex_unlock(&data->lock); + + return result; +} + +static int +tle9104_get_diagnostics_internal(const struct device *dev, + struct gpio_tle9104_channel_diagnostics diag[TLE9104_GPIO_COUNT]) +{ + enum tle9104_register read_reg; + uint8_t diag_out12_on; + uint8_t diag_out34_on; + uint8_t diag_off; + + int result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_DIAGOUT12ON, 0x00, + &read_reg, &diag_out12_on); + if (result != 0) { + return result; + } + + result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_DIAGOUT34ON, 0x00, &read_reg, + &diag_out12_on); + if (result != 0) { + return result; + } + if (read_reg != TLE9104REGISTER_DIAGOUT12ON) { + LOG_ERR("expected to read different register"); + return -EFAULT; + } + + result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_DIAGOFF, 0x00, &read_reg, + &diag_out34_on); + if (result != 0) { + return result; + } + if (read_reg != TLE9104REGISTER_DIAGOUT34ON) { + LOG_ERR("expected to read different register"); + return -EFAULT; + } + + result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_DIAGOFF, 0x00, &read_reg, + &diag_off); + if (result != 0) { + return result; + } + if (read_reg != TLE9104REGISTER_DIAGOFF) { + LOG_ERR("expected to read different register"); + return -EFAULT; + } + + diag[0].on = tle9104_get_register_bits(diag_out12_on, TLE9104_DIAGOUT12ON_DIAGCH1ON_POS, + TLE9104_DIAGOUT12ON_DIAGCH1ON_LENGTH); + diag[1].on = tle9104_get_register_bits(diag_out12_on, TLE9104_DIAGOUT12ON_DIAGCH2ON_POS, + TLE9104_DIAGOUT12ON_DIAGCH2ON_LENGTH); + diag[2].on = tle9104_get_register_bits(diag_out34_on, TLE9104_DIAGOUT34ON_DIAGCH3ON_POS, + TLE9104_DIAGOUT34ON_DIAGCH3ON_LENGTH); + diag[3].on = tle9104_get_register_bits(diag_out34_on, TLE9104_DIAGOUT34ON_DIAGCH4ON_POS, + TLE9104_DIAGOUT34ON_DIAGCH4ON_LENGTH); + diag[0].off = tle9104_get_register_bits(diag_off, TLE9104_DIAGOFF_DIAGCH1OFF_POS, + TLE9104_DIAGOFF_DIAGCH1OFF_LENGTH); + diag[1].off = tle9104_get_register_bits(diag_off, TLE9104_DIAGOFF_DIAGCH2OFF_POS, + TLE9104_DIAGOFF_DIAGCH2OFF_LENGTH); + diag[2].off = tle9104_get_register_bits(diag_off, TLE9104_DIAGOFF_DIAGCH3OFF_POS, + TLE9104_DIAGOFF_DIAGCH3OFF_LENGTH); + diag[3].off = tle9104_get_register_bits(diag_off, TLE9104_DIAGOFF_DIAGCH4OFF_POS, + TLE9104_DIAGOFF_DIAGCH4OFF_LENGTH); + + return 0; +} + +int tle9104_get_diagnostics(const struct device *dev, + struct gpio_tle9104_channel_diagnostics diag[TLE9104_GPIO_COUNT]) +{ + struct tle9104_data *data = dev->data; + int result; + + k_mutex_lock(&data->lock, K_FOREVER); + result = tle9104_get_diagnostics_internal(dev, diag); + k_mutex_unlock(&data->lock); + + return result; +} + +static int tle9104_init(const struct device *dev) +{ + const struct tle9104_config *config = dev->config; + struct tle9104_data *data = dev->data; + uint8_t register_cfg; + uint8_t register_globalstatus; + uint8_t register_icvid; + enum tle9104_register read_reg; + int result; + + LOG_DBG("initialize TLE9104 instance %s", dev->name); + + data->cwd_ignore = true; + + result = k_mutex_init(&data->lock); + if (result != 0) { + LOG_ERR("unable to initialize mutex"); + return result; + } + + if (!spi_is_ready_dt(&config->bus)) { + LOG_ERR("SPI bus %s is not ready", config->bus.bus->name); + return -ENODEV; + } + + register_cfg = 0x00; + + for (int i = 0; i < TLE9104_GPIO_COUNT; ++i) { + const struct gpio_dt_spec *current = config->gpio_control + i; + + if (current->port == NULL) { + LOG_DBG("got no control port for output %i, will control it via SPI", i); + continue; + } + + register_cfg |= TLE9104_CFG_OUT1DD_BIT << i; + + if (!gpio_is_ready_dt(current)) { + LOG_ERR("%s: control GPIO is not ready", dev->name); + return -ENODEV; + } + + result = gpio_pin_configure_dt(current, GPIO_OUTPUT_INACTIVE); + if (result != 0) { + LOG_ERR("failed to initialize control GPIO %i", i); + return result; + } + } + + if (config->gpio_enable.port != NULL) { + if (!gpio_is_ready_dt(&config->gpio_enable)) { + LOG_ERR("%s: enable GPIO is not ready", dev->name); + return -ENODEV; + } + + result = gpio_pin_configure_dt(&config->gpio_enable, GPIO_OUTPUT_ACTIVE); + if (result != 0) { + LOG_ERR("failed to enable TLE9104"); + return result; + } + } + + if (config->gpio_reset.port != NULL) { + if (!gpio_is_ready_dt(&config->gpio_reset)) { + LOG_ERR("%s: reset GPIO is not yet ready", dev->name); + return -ENODEV; + } + + result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE); + if (result != 0) { + LOG_ERR("failed to initialize GPIO for reset"); + return result; + } + + k_busy_wait(TLE9104_RESET_DURATION_TIME_US); + gpio_pin_set_dt(&config->gpio_reset, 0); + k_busy_wait(TLE9104_RESET_DURATION_WAIT_TIME_US + + TLE9104_RESET_DURATION_WAIT_TIME_SAFETY_MARGIN_US); + } + + /* + * The first read value should be the ICVID, this acts also as the setup of the + * global status register address. + */ + result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_GLOBALSTATUS, 0x00, &read_reg, + ®ister_icvid); + if (result != 0) { + return result; + } + + if (read_reg != TLE9104REGISTER_ICVID) { + LOG_ERR("expected to read register ICVID, got instead 0x%02X", read_reg); + return -EIO; + } + + if (register_icvid != TLE9104_ICVERSIONID) { + LOG_ERR("got unexpected IC version id 0x%02X", register_icvid); + return -EIO; + } + + result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_GLOBALSTATUS, 0x00, &read_reg, + ®ister_globalstatus); + if (result != 0) { + return result; + } + + if (read_reg != TLE9104REGISTER_GLOBALSTATUS) { + LOG_ERR("expected to read register GLOBALSTATUS, got instead 0x%02X", read_reg); + return -EIO; + } + + if ((register_globalstatus & TLE9104_GLOBALSTATUS_POR_LATCH_BIT) == 0) { + LOG_ERR("no power on reset detected"); + return -EIO; + } + + /* disable communication watchdog */ + tle9104_set_register_bits(®ister_cfg, TLE9104_CFG_CWDTIME_POS, + TLE9104_CFG_CWDTIME_LENGTH, 0); + + result = tle9104_write_register(dev, TLE9104REGISTER_CFG, register_cfg); + if (result != 0) { + LOG_ERR("unable to write configuration"); + return result; + } + + register_cfg = 0x00; + tle9104_set_register_bits(®ister_cfg, TLE9104_OFFDIAGCFG_DIAGFILTCFG_POS, + TLE9104_OFFDIAGCFG_DIAGFILTCFG_LENGTH, + config->diagnostic_filter_time); + register_cfg |= TLE9104_OFFDIAGCFG_OUT4DIAGEN_BIT; + register_cfg |= TLE9104_OFFDIAGCFG_OUT3DIAGEN_BIT; + register_cfg |= TLE9104_OFFDIAGCFG_OUT2DIAGEN_BIT; + register_cfg |= TLE9104_OFFDIAGCFG_OUT1DIAGEN_BIT; + + result = tle9104_write_register(dev, TLE9104REGISTER_OFFDIAGCFG, register_cfg); + if (result != 0) { + LOG_ERR("unable to write OFF-diag configuration"); + return result; + } + + register_cfg = 0x00; + tle9104_set_register_bits(®ister_cfg, TLE9104_ONDIAGCFG_OCFILTCFG_POS, + TLE9104_ONDIAGCFG_OCFILTCFG_LENGTH, + config->overcurrent_shutdown_delay_time); + tle9104_set_register_bits(®ister_cfg, TLE9104_ONDIAGCFG_OCTH_POS, + TLE9104_ONDIAGCFG_OCTH_LENGTH, + config->overcurrent_shutdown_threshold); + + result = tle9104_write_register(dev, TLE9104REGISTER_ONDIAGCFG, register_cfg); + if (result != 0) { + LOG_ERR("unable to write ON-diag configuration"); + return result; + } + + register_globalstatus = 0x00; + /* enable outputs */ + register_globalstatus |= TLE9104_GLOBALSTATUS_OUTEN_BIT; + + result = tle9104_write_register(dev, TLE9104REGISTER_GLOBALSTATUS, register_globalstatus); + if (result != 0) { + LOG_ERR("unable to write global status"); + return result; + } + + data->cwd_ignore = false; + + return 0; +} + +#define TLE9104_INIT_GPIO_FIELDS(inst, gpio) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, gpio), \ + (GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(inst), gpio, 0)), ({0})) + +#define TLE9104_INIT(inst) \ + static const struct tle9104_config tle9104_##inst##_config = { \ + .bus = SPI_DT_SPEC_INST_GET( \ + inst, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \ + .gpio_enable = TLE9104_INIT_GPIO_FIELDS(inst, en_gpios), \ + .gpio_reset = TLE9104_INIT_GPIO_FIELDS(inst, resn_gpios), \ + .gpio_control = { \ + TLE9104_INIT_GPIO_FIELDS(inst, in1_gpios), \ + TLE9104_INIT_GPIO_FIELDS(inst, in2_gpios), \ + TLE9104_INIT_GPIO_FIELDS(inst, in3_gpios), \ + TLE9104_INIT_GPIO_FIELDS(inst, in4_gpios), \ + }, \ + .diagnostic_filter_time = DT_INST_ENUM_IDX(inst, diagnostic_filter_time), \ + .overcurrent_shutdown_delay_time = \ + DT_INST_ENUM_IDX(inst, overcurrent_shutdown_delay_time), \ + .overcurrent_shutdown_threshold = \ + DT_INST_ENUM_IDX(inst, overcurrent_shutdown_threshold), \ + }; \ + \ + static struct tle9104_data tle9104_##inst##_data; \ + \ + DEVICE_DT_INST_DEFINE(inst, tle9104_init, NULL, &tle9104_##inst##_data, \ + &tle9104_##inst##_config, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \ + NULL); + +DT_INST_FOREACH_STATUS_OKAY(TLE9104_INIT); diff --git a/dts/bindings/gpio/infineon,tle9104-gpio.yaml b/dts/bindings/gpio/infineon,tle9104-gpio.yaml new file mode 100644 index 00000000000..cd8cf933b9b --- /dev/null +++ b/dts/bindings/gpio/infineon,tle9104-gpio.yaml @@ -0,0 +1,27 @@ +# +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +description: Infineon TLE9104 4-channel powertrain switch GPIO instance + +compatible: "infineon,tle9104-gpio" + +include: gpio-controller.yaml + +on-bus: tle9104 + +properties: + "#gpio-cells": + const: 2 + + ngpios: + type: int + required: true + const: 4 + description: Number of GPIOs supported + +gpio-cells: + - pin + - flags diff --git a/dts/bindings/gpio/infineon,tle9104.yaml b/dts/bindings/gpio/infineon,tle9104.yaml deleted file mode 100644 index cb82ecbde92..00000000000 --- a/dts/bindings/gpio/infineon,tle9104.yaml +++ /dev/null @@ -1,49 +0,0 @@ -# -# Copyright (c) 2023 SILA Embedded Solutions GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -description: Infineon TLE9104 4-channel powertrain switch - -compatible: "infineon,tle9104" - -include: [gpio-controller.yaml, spi-device.yaml] - -properties: - "#gpio-cells": - const: 2 - - ngpios: - type: int - required: true - const: 4 - description: Number of GPIOs supported - - en-gpios: - type: phandle-array - description: "GPIO for enable" - - resn-gpios: - type: phandle-array - description: "GPIO for reset" - - in1-gpios: - type: phandle-array - description: "GPIO for controlling OUT1" - - in2-gpios: - type: phandle-array - description: "GPIO for controlling OUT2" - - in3-gpios: - type: phandle-array - description: "GPIO for controlling OUT3" - - in4-gpios: - type: phandle-array - description: "GPIO for controlling OUT4" - -gpio-cells: - - pin - - flags diff --git a/dts/bindings/mfd/infineon,tle9104.yaml b/dts/bindings/mfd/infineon,tle9104.yaml new file mode 100644 index 00000000000..f9a5512296e --- /dev/null +++ b/dts/bindings/mfd/infineon,tle9104.yaml @@ -0,0 +1,78 @@ +# +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +description: Infineon TLE9104 4-channel powertrain switch + +compatible: "infineon,tle9104" + +include: spi-device.yaml + +bus: tle9104 + +properties: + en-gpios: + type: phandle-array + description: "GPIO for enable" + + resn-gpios: + type: phandle-array + description: "GPIO for reset" + + in1-gpios: + type: phandle-array + description: "GPIO for controlling OUT1" + + in2-gpios: + type: phandle-array + description: "GPIO for controlling OUT2" + + in3-gpios: + type: phandle-array + description: "GPIO for controlling OUT3" + + in4-gpios: + type: phandle-array + description: "GPIO for controlling OUT4" + + diagnostic-filter-time: + type: int + default: 500 + enum: + - 200 + - 500 + - 1000 + - 2000 + description: + diagnostic filter time in us, + default matches power on reset value + + overcurrent-shutdown-delay-time: + type: int + default: 60 + enum: + - 60 + - 120 + - 500 + - 1000 + - 5000 + - 10000 + - 20000 + - 30000 + description: + overcurrent shutdown delay time in us, + default matches power on reset value + + overcurrent-shutdown-threshold: + type: int + default: 2000 + enum: + - 1000 + - 2000 + - 3000 + - 4000 + description: + overcurrent shutdown threshold in mA, + default matches power on reset value diff --git a/include/zephyr/drivers/mfd/tle9104.h b/include/zephyr/drivers/mfd/tle9104.h new file mode 100644 index 00000000000..a647f79c7e6 --- /dev/null +++ b/include/zephyr/drivers/mfd/tle9104.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_TLE9104_H_ +#define ZEPHYR_INCLUDE_DRIVERS_MFD_TLE9104_H_ + +#include +#include + +#define TLE9104_GPIO_COUNT 4 + +enum tle9104_on_state_diagnostics { + /* overtemperature */ + TLE9104_ONDIAG_OT = 5, + /* overcurrent timeout */ + TLE9104_ONDIAG_OCTIME = 4, + /* overtemperature during overcurrent */ + TLE9104_ONDIAG_OCOT = 3, + /* short to battery */ + TLE9104_ONDIAG_SCB = 2, + /* no failure */ + TLE9104_ONDIAG_NOFAIL = 1, + /* no diagnosis done */ + TLE9104_ONDIAG_UNKNOWN = 0, +}; + +enum tle9104_off_state_diagnostics { + /* short to ground */ + TLE9104_OFFDIAG_SCG = 3, + /* open load */ + TLE9104_OFFDIAG_OL = 2, + /* no failure */ + TLE9104_OFFDIAG_NOFAIL = 1, + /* no diagnosis done */ + TLE9104_OFFDIAG_UNKNOWN = 0, +}; + +struct gpio_tle9104_channel_diagnostics { + enum tle9104_on_state_diagnostics on: 3; + enum tle9104_off_state_diagnostics off: 2; +}; + +/** + * @brief get the diagnostics of the outputs + * + * @param dev instance of TLE9104 + * @param diag destination where the result is written to + * + * @retval 0 If successful. + */ +int tle9104_get_diagnostics(const struct device *dev, + struct gpio_tle9104_channel_diagnostics diag[TLE9104_GPIO_COUNT]); +/*! + * @brief write output state + * + * @param dev instance of TLE9104 + * @param state output state, each bit represents on output + * + * @retval 0 If successful. + */ +int tle9104_write_state(const struct device *dev, uint8_t state); + +#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_TLE9104_H_ */ diff --git a/tests/drivers/build_all/gpio/app.overlay b/tests/drivers/build_all/gpio/app.overlay index ce6b91e5027..6a34c45d4d5 100644 --- a/tests/drivers/build_all/gpio/app.overlay +++ b/tests/drivers/build_all/gpio/app.overlay @@ -299,13 +299,19 @@ test_spi_tle9104: tle9104@4 { compatible = "infineon,tle9104"; + status = "okay"; spi-max-frequency = <0>; reg = <0x04>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <4>; resn-gpios = <&test_gpio 0 0>; en-gpios = <&test_gpio 0 0>; + + tle9104_gpio: tle9104_gpio { + compatible = "infineon,tle9104-gpio"; + status = "okay"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <4>; + }; }; }; }; diff --git a/tests/drivers/build_all/gpio/prj.conf b/tests/drivers/build_all/gpio/prj.conf index 24c22489fbb..10602c9b8f1 100644 --- a/tests/drivers/build_all/gpio/prj.conf +++ b/tests/drivers/build_all/gpio/prj.conf @@ -4,4 +4,7 @@ CONFIG_TEST_USERSPACE=y CONFIG_I2C=y CONFIG_GPIO_PCA95XX_INTERRUPT=y CONFIG_SPI=y +CONFIG_MFD=y +CONFIG_MFD_INIT_PRIORITY=80 +CONFIG_GPIO_TLE9104_INIT_PRIORITY=81 CONFIG_GPIO_BD8LB600FS_INIT_PRIORITY=81 From 888d071fe701827c3bb1ec570e0215e32622d593 Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Thu, 15 Feb 2024 11:42:42 +0100 Subject: [PATCH 2039/2402] drivers: sensor: implement output diagnostics sensor for TLE9104 Implement a sensor for the output diagnostics of the power train switch TLE9104. Signed-off-by: Benedikt Schmidt --- drivers/mfd/mfd_tle9104.c | 39 ++++++++ drivers/sensor/infineon/CMakeLists.txt | 1 + drivers/sensor/infineon/Kconfig | 1 + .../sensor/infineon/tle9104/CMakeLists.txt | 5 + drivers/sensor/infineon/tle9104/Kconfig | 10 ++ .../infineon/tle9104/tle9104_diagnostics.c | 96 +++++++++++++++++++ .../infineon/tle9104/tle9104_diagnostics.h | 23 +++++ .../sensor/infineon,tle9104-diagnostics.yaml | 15 +++ include/zephyr/drivers/mfd/tle9104.h | 8 ++ include/zephyr/drivers/sensor/tle9104.h | 18 ++++ 10 files changed, 216 insertions(+) create mode 100644 drivers/sensor/infineon/tle9104/CMakeLists.txt create mode 100644 drivers/sensor/infineon/tle9104/Kconfig create mode 100644 drivers/sensor/infineon/tle9104/tle9104_diagnostics.c create mode 100644 drivers/sensor/infineon/tle9104/tle9104_diagnostics.h create mode 100644 dts/bindings/sensor/infineon,tle9104-diagnostics.yaml create mode 100644 include/zephyr/drivers/sensor/tle9104.h diff --git a/drivers/mfd/mfd_tle9104.c b/drivers/mfd/mfd_tle9104.c index 3170a97d8f7..313c59d5d78 100644 --- a/drivers/mfd/mfd_tle9104.c +++ b/drivers/mfd/mfd_tle9104.c @@ -368,6 +368,45 @@ int tle9104_get_diagnostics(const struct device *dev, return result; } +static int tle9104_clear_diagnostics_internal(const struct device *dev) +{ + enum tle9104_register read_reg; + uint8_t temp; + int result; + + result = tle9104_transceive_frame(dev, true, TLE9104REGISTER_DIAGOUT12ON, 0x00, &read_reg, + &temp); + if (result != 0) { + return result; + } + + result = tle9104_transceive_frame(dev, true, TLE9104REGISTER_DIAGOUT34ON, 0x00, &read_reg, + &temp); + if (result != 0) { + return result; + } + + result = tle9104_transceive_frame(dev, true, TLE9104REGISTER_DIAGOFF, 0x00, &read_reg, + &temp); + if (result != 0) { + return result; + } + + return 0; +} + +int tle9104_clear_diagnostics(const struct device *dev) +{ + struct tle9104_data *data = dev->data; + int result; + + k_mutex_lock(&data->lock, K_FOREVER); + result = tle9104_clear_diagnostics_internal(dev); + k_mutex_unlock(&data->lock); + + return result; +} + static int tle9104_init(const struct device *dev) { const struct tle9104_config *config = dev->config; diff --git a/drivers/sensor/infineon/CMakeLists.txt b/drivers/sensor/infineon/CMakeLists.txt index 5c0afd3c4e3..5ebc1254db0 100644 --- a/drivers/sensor/infineon/CMakeLists.txt +++ b/drivers/sensor/infineon/CMakeLists.txt @@ -3,5 +3,6 @@ # zephyr-keep-sorted-start add_subdirectory_ifdef(CONFIG_DPS310 dps310) +add_subdirectory_ifdef(CONFIG_TLE9104_DIAGNOSTICS tle9104) add_subdirectory_ifdef(CONFIG_XMC4XXX_TEMP xmc4xxx_temp) # zephyr-keep-sorted-stop diff --git a/drivers/sensor/infineon/Kconfig b/drivers/sensor/infineon/Kconfig index 92d95d20fbb..678fa194754 100644 --- a/drivers/sensor/infineon/Kconfig +++ b/drivers/sensor/infineon/Kconfig @@ -3,5 +3,6 @@ # zephyr-keep-sorted-start source "drivers/sensor/infineon/dps310/Kconfig" +source "drivers/sensor/infineon/tle9104/Kconfig" source "drivers/sensor/infineon/xmc4xxx_temp/Kconfig" # zephyr-keep-sorted-stop diff --git a/drivers/sensor/infineon/tle9104/CMakeLists.txt b/drivers/sensor/infineon/tle9104/CMakeLists.txt new file mode 100644 index 00000000000..38edbca3b5a --- /dev/null +++ b/drivers/sensor/infineon/tle9104/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(tle9104_diagnostics.c) diff --git a/drivers/sensor/infineon/tle9104/Kconfig b/drivers/sensor/infineon/tle9104/Kconfig new file mode 100644 index 00000000000..ec4b9e1ab03 --- /dev/null +++ b/drivers/sensor/infineon/tle9104/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +config TLE9104_DIAGNOSTICS + bool "Output diagnostics of TLE9104" + default y + depends on DT_HAS_INFINEON_TLE9104_DIAGNOSTICS_ENABLED + help + Enable driver for the output diagnostics of the power train + switch TLE9104. diff --git a/drivers/sensor/infineon/tle9104/tle9104_diagnostics.c b/drivers/sensor/infineon/tle9104/tle9104_diagnostics.c new file mode 100644 index 00000000000..d1c820ab115 --- /dev/null +++ b/drivers/sensor/infineon/tle9104/tle9104_diagnostics.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT infineon_tle9104_diagnostics + +#include +#include +#include + +#include "tle9104_diagnostics.h" + +LOG_MODULE_REGISTER(TLE9104_DIAGNOSTICS, CONFIG_SENSOR_LOG_LEVEL); + +static int tle9104_diagnostics_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + const struct tle9104_diagnostics_config *config = dev->config; + struct tle9104_diagnostics_data *data = dev->data; + int result; + + __ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL); + result = tle9104_get_diagnostics(config->parent, data->values); + if (result != 0) { + return result; + } + + result = tle9104_clear_diagnostics(config->parent); + if (result != 0) { + return result; + } + + return 0; +} + +static int tle9104_diagnostics_channel_get(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + struct tle9104_diagnostics_data *data = dev->data; + + val->val1 = 0; + val->val2 = 0; + + switch (chan) { + case SENSOR_CHAN_TLE9104_OPEN_LOAD: + for (size_t i = 0; i < ARRAY_SIZE(data->values); ++i) { + if (data->values[i].off == TLE9104_OFFDIAG_OL) { + val->val1 |= BIT(i); + } + } + return 0; + case SENSOR_CHAN_TLE9104_OVER_CURRENT: + for (size_t i = 0; i < ARRAY_SIZE(data->values); ++i) { + if (data->values[i].on == TLE9104_ONDIAG_OCTIME || + data->values[i].on == TLE9104_ONDIAG_OCOT) { + val->val1 |= BIT(i); + } + } + return 0; + default: + LOG_ERR("%s: requesting unsupported channel %i", dev->name, chan); + return -ENOTSUP; + } +} + +static const struct sensor_driver_api tle9104_diagnostics_driver_api = { + .sample_fetch = tle9104_diagnostics_sample_fetch, + .channel_get = tle9104_diagnostics_channel_get, +}; + +int tle9104_diagnostics_init(const struct device *dev) +{ + const struct tle9104_diagnostics_config *config = dev->config; + + if (!device_is_ready(config->parent)) { + LOG_ERR("%s: parent device is not ready", dev->name); + return -ENODEV; + } + + return 0; +} + +#define TLE9104_DIAGNOSTICS_DEFINE(inst) \ + static struct tle9104_diagnostics_data tle9104_diagnostics_data_##inst; \ + \ + static const struct tle9104_diagnostics_config tle9104_diagnostics_config##inst = { \ + .parent = DEVICE_DT_GET(DT_PARENT(DT_DRV_INST(inst))), \ + }; \ + \ + SENSOR_DEVICE_DT_INST_DEFINE( \ + inst, tle9104_diagnostics_init, NULL, &tle9104_diagnostics_data_##inst, \ + &tle9104_diagnostics_config##inst, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, \ + &tle9104_diagnostics_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(TLE9104_DIAGNOSTICS_DEFINE) diff --git a/drivers/sensor/infineon/tle9104/tle9104_diagnostics.h b/drivers/sensor/infineon/tle9104/tle9104_diagnostics.h new file mode 100644 index 00000000000..37f03952d7f --- /dev/null +++ b/drivers/sensor/infineon/tle9104/tle9104_diagnostics.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_INFINEON_TLE9104_TLE9104_DIAGNOSTICS_H_ +#define ZEPHYR_DRIVERS_SENSOR_INFINEON_TLE9104_TLE9104_DIAGNOSTICS_H_ + +#include +#include +#include + +struct tle9104_diagnostics_data { + struct gpio_tle9104_channel_diagnostics values[TLE9104_GPIO_COUNT]; +}; + +struct tle9104_diagnostics_config { + const struct device *parent; + uint8_t channel; +}; + +#endif /* ZEPHYR_DRIVERS_SENSOR_INFINEON_TLE9104_TLE9104_DIAGNOSTICS_H_ */ diff --git a/dts/bindings/sensor/infineon,tle9104-diagnostics.yaml b/dts/bindings/sensor/infineon,tle9104-diagnostics.yaml new file mode 100644 index 00000000000..521a2e74c99 --- /dev/null +++ b/dts/bindings/sensor/infineon,tle9104-diagnostics.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +description: Output diagnostics of the powertrain switch TLE9104 + +compatible: "infineon,tle9104-diagnostics" + +include: [sensor-device.yaml] + +on-bus: tle9104 + +properties: + "#sensor-cells": + type: int + const: 0 diff --git a/include/zephyr/drivers/mfd/tle9104.h b/include/zephyr/drivers/mfd/tle9104.h index a647f79c7e6..bb170790657 100644 --- a/include/zephyr/drivers/mfd/tle9104.h +++ b/include/zephyr/drivers/mfd/tle9104.h @@ -52,6 +52,14 @@ struct gpio_tle9104_channel_diagnostics { */ int tle9104_get_diagnostics(const struct device *dev, struct gpio_tle9104_channel_diagnostics diag[TLE9104_GPIO_COUNT]); +/** + * @brief clear the diagnostics of the outputs + * + * @param dev instance of TLE9104 + * + * @retval 0 If successful. + */ +int tle9104_clear_diagnostics(const struct device *dev); /*! * @brief write output state * diff --git a/include/zephyr/drivers/sensor/tle9104.h b/include/zephyr/drivers/sensor/tle9104.h new file mode 100644 index 00000000000..d2829d81504 --- /dev/null +++ b/include/zephyr/drivers/sensor/tle9104.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_TLE9104_H_ +#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TLE9104_H_ + +#include + +enum sensor_channel_tle9104 { + /** Open load detected, boolean with one bit per output */ + SENSOR_CHAN_TLE9104_OPEN_LOAD = SENSOR_ATTR_PRIV_START, + /** Over current detected, boolean with one bit per output */ + SENSOR_CHAN_TLE9104_OVER_CURRENT, +}; + +#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_TLE9104_H_ */ From abf32ced7451c1bc8938b631c4fd5fd6bd5a8dcf Mon Sep 17 00:00:00 2001 From: Benedikt Schmidt Date: Thu, 15 Feb 2024 11:43:51 +0100 Subject: [PATCH 2040/2402] tests: drivers: build_all: sensor: add TLE9104 Add an instance of the output diagnostics sensor for the power train switch TLE9104 to the build all tests. Signed-off-by: Benedikt Schmidt --- .../drivers/build_all/gpio/adc_ads1145s0x_gpio.conf | 5 ++++- tests/drivers/build_all/gpio/prj.conf | 2 ++ tests/drivers/build_all/sensor/app.overlay | 3 ++- tests/drivers/build_all/sensor/prj.conf | 1 + tests/drivers/build_all/sensor/spi.dtsi | 13 +++++++++++++ 5 files changed, 22 insertions(+), 2 deletions(-) diff --git a/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.conf b/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.conf index 826107aabc4..623fc79cd08 100644 --- a/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.conf +++ b/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.conf @@ -1,4 +1,7 @@ CONFIG_ADC=y CONFIG_ADC_ADS114S0X_GPIO=y -CONFIG_ADC_INIT_PRIORITY=81 +CONFIG_MFD=y +CONFIG_MFD_INIT_PRIORITY=79 +CONFIG_ADC_INIT_PRIORITY=80 +CONFIG_GPIO_TLE9104_INIT_PRIORITY=81 CONFIG_GPIO_BD8LB600FS_INIT_PRIORITY=81 diff --git a/tests/drivers/build_all/gpio/prj.conf b/tests/drivers/build_all/gpio/prj.conf index 10602c9b8f1..cd3185f6845 100644 --- a/tests/drivers/build_all/gpio/prj.conf +++ b/tests/drivers/build_all/gpio/prj.conf @@ -8,3 +8,5 @@ CONFIG_MFD=y CONFIG_MFD_INIT_PRIORITY=80 CONFIG_GPIO_TLE9104_INIT_PRIORITY=81 CONFIG_GPIO_BD8LB600FS_INIT_PRIORITY=81 +CONFIG_GPIO_AXP192_INIT_PRIORITY=81 +CONFIG_REGULATOR_FIXED_INIT_PRIORITY=82 diff --git a/tests/drivers/build_all/sensor/app.overlay b/tests/drivers/build_all/sensor/app.overlay index 161949bdd7b..aec784c2688 100644 --- a/tests/drivers/build_all/sensor/app.overlay +++ b/tests/drivers/build_all/sensor/app.overlay @@ -128,7 +128,8 @@ <&test_gpio 0 0>, <&test_gpio 0 0>, <&test_gpio 0 0>, - <&test_gpio 0 0>; + <&test_gpio 0 0>, + <&test_gpio 0 0>; /* 0x2e */ #include "spi.dtsi" }; diff --git a/tests/drivers/build_all/sensor/prj.conf b/tests/drivers/build_all/sensor/prj.conf index 67172951b7d..fe677345578 100644 --- a/tests/drivers/build_all/sensor/prj.conf +++ b/tests/drivers/build_all/sensor/prj.conf @@ -9,6 +9,7 @@ CONFIG_I2C=y CONFIG_I3C=y CONFIG_SERIAL=y CONFIG_SPI=y +CONFIG_MFD=y CONFIG_W1=y CONFIG_SENSOR=y CONFIG_ICM42605_TRIGGER_NONE=y diff --git a/tests/drivers/build_all/sensor/spi.dtsi b/tests/drivers/build_all/sensor/spi.dtsi index d781f170066..708b2f6a607 100644 --- a/tests/drivers/build_all/sensor/spi.dtsi +++ b/tests/drivers/build_all/sensor/spi.dtsi @@ -370,3 +370,16 @@ test_spi_lis2dux12: lis2dux12@2d { int2-gpios = <&test_gpio 0 0>; status = "okay"; }; + +test_spi_tle9104: tle9104@2e { + compatible = "infineon,tle9104"; + reg = <0x2e>; + spi-max-frequency = <0>; + status = "okay"; + + tle9104_diagnostics: tle9104_diagnostics { + compatible = "infineon,tle9104-diagnostics"; + status = "okay"; + #sensor-cells = <0>; + }; +}; From ca4e5d9c9872a7ff27737fb4f2125507525e75c3 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 5 Apr 2024 12:12:50 +0200 Subject: [PATCH 2041/2402] cmake: use INTERFACE_SOURCES in zephyr_syscall_header Instead of INTERFACE_INCLUDE_DIRECTORIES, because header files are used, not directories. Headers were added to both, target sources and include directories. Signed-off-by: Gerard Marull-Paretas --- CMakeLists.txt | 2 +- cmake/modules/extensions.cmake | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 2d802277a68..20ff0c9caaf 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -840,7 +840,7 @@ add_subdirectory(kernel) get_property( syscalls_file_list TARGET syscalls_interface - PROPERTY INTERFACE_INCLUDE_DIRECTORIES + PROPERTY INTERFACE_SOURCES ) file(CONFIGURE OUTPUT ${syscalls_file_list_output} CONTENT "@syscalls_file_list@" @ONLY) diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index 32f7531167e..cb878e3b813 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -1634,10 +1634,6 @@ function(zephyr_syscall_header) syscalls_interface INTERFACE ${header_file} ) - target_include_directories( - syscalls_interface INTERFACE - ${header_file} - ) add_dependencies( syscalls_interface ${header_file} From 80a6a206289537fa220e34fe485b11fccef9ac85 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 5 Apr 2024 12:21:31 +0200 Subject: [PATCH 2042/2402] cmake: extensions: introduce zephyr_syscall_include_directories Add a new CMake helper to add new include directories to be parsed by the syscall machinery. This helper complements the existing zephyr_syscall_header, which works at a header-level. Signed-off-by: Gerard Marull-Paretas --- CMakeLists.txt | 7 +++++++ cmake/modules/extensions.cmake | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 20ff0c9caaf..b4d12bb8c87 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -694,6 +694,13 @@ if(CONFIG_ZTEST) endif() +get_property( + syscalls_include_list + TARGET syscalls_interface + PROPERTY INTERFACE_INCLUDE_DIRECTORIES +) +list(APPEND SYSCALL_INCLUDE_DIRS ${syscalls_include_list}) + foreach(d ${SYSCALL_INCLUDE_DIRS}) list(APPEND parse_syscalls_include_args --include ${d} diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index cb878e3b813..8f9be83b140 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -1619,6 +1619,30 @@ function(zephyr_build_string outvar) set(${outvar} ${${outvar}} PARENT_SCOPE) endfunction() +# Function to add one or more directories to the include list passed to the syscall generator. +function(zephyr_syscall_include_directories) + foreach(one_dir ${ARGV}) + if(EXISTS ${one_dir}) + set(include_dir ${one_dir}) + elseif(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${one_dir}) + set(include_dir ${CMAKE_CURRENT_SOURCE_DIR}/${one_dir}) + else() + message(FATAL_ERROR "Syscall include directory not found: ${one_dir}") + endif() + + target_include_directories( + syscalls_interface INTERFACE + ${include_dir} + ) + add_dependencies( + syscalls_interface + ${include_dir} + ) + + unset(include_dir) + endforeach() +endfunction() + # Function to add header file(s) to the list to be passed to syscall generator. function(zephyr_syscall_header) foreach(one_file ${ARGV}) From 774dd165557e71bb2d3e67dd6c62d8229c1017be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Ciupis?= Date: Fri, 23 Feb 2024 13:13:10 +0100 Subject: [PATCH 2043/2402] drivers: ieee802154: gracefully handle invalid Ack timestamp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The nRF IEEE 802.15.4 driver might report a received Ack frame with invalid timestamp, if the timestamp could not have been taken. The upper layers are not prepared to handle such a case as they expect that for a received frame, the timestamp is always present and valid. This commit detects this situation and handles it gracefully by reporting the transmission as failed as if no Ack was received. Signed-off-by: Jędrzej Ciupis --- drivers/ieee802154/ieee802154_nrf5.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/ieee802154/ieee802154_nrf5.c b/drivers/ieee802154/ieee802154_nrf5.c index 15f5398a191..4cbdd9eb607 100644 --- a/drivers/ieee802154/ieee802154_nrf5.c +++ b/drivers/ieee802154/ieee802154_nrf5.c @@ -398,6 +398,17 @@ static int handle_ack(struct nrf5_802154_data *nrf5_radio) struct net_pkt *ack_pkt; int err = 0; +#if defined(CONFIG_NET_PKT_TIMESTAMP) + if (nrf5_radio->ack_frame.time == NRF_802154_NO_TIMESTAMP) { + /* Ack timestamp is invalid and cannot be used by the upper layer. + * Report the transmission as failed as if the Ack was not received at all. + */ + LOG_WRN("Invalid ACK timestamp."); + err = -ENOMSG; + goto free_nrf_ack; + } +#endif + if (IS_ENABLED(CONFIG_IEEE802154_NRF5_FCS_IN_LENGTH)) { ack_len = nrf5_radio->ack_frame.psdu[0]; } else { @@ -1140,8 +1151,14 @@ void nrf_802154_transmitted_raw(uint8_t *frame, nrf5_data.ack_frame.lqi = metadata->data.transmitted.lqi; #if defined(CONFIG_NET_PKT_TIMESTAMP) - nrf5_data.ack_frame.time = nrf_802154_timestamp_end_to_phr_convert( - metadata->data.transmitted.time, nrf5_data.ack_frame.psdu[0]); + if (metadata->data.transmitted.time == NRF_802154_NO_TIMESTAMP) { + /* Ack timestamp is invalid. Keep this value to detect it when handling Ack + */ + nrf5_data.ack_frame.time = NRF_802154_NO_TIMESTAMP; + } else { + nrf5_data.ack_frame.time = nrf_802154_timestamp_end_to_phr_convert( + metadata->data.transmitted.time, nrf5_data.ack_frame.psdu[0]); + } #endif } From 6b495ceda98afdf78abf575467d2892d6e1648db Mon Sep 17 00:00:00 2001 From: Daniel Maslowski Date: Fri, 8 Mar 2024 19:44:21 +0100 Subject: [PATCH 2044/2402] dts: jh7110: fix memory definitions The L2LIM is 2MB in size, see: https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/u74_memory_map.html Rename it since there are other memory blocks such as the DTIM for the S7. Signed-off-by: Daniel Maslowski --- boards/starfive/visionfive2/visionfive2.dts | 2 +- dts/riscv/starfive/jh7110-visionfive-v2.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/starfive/visionfive2/visionfive2.dts b/boards/starfive/visionfive2/visionfive2.dts index 48d7045e075..98c4b960951 100644 --- a/boards/starfive/visionfive2/visionfive2.dts +++ b/boards/starfive/visionfive2/visionfive2.dts @@ -15,7 +15,7 @@ chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &ram0; + zephyr,sram = &l2lim; }; }; diff --git a/dts/riscv/starfive/jh7110-visionfive-v2.dtsi b/dts/riscv/starfive/jh7110-visionfive-v2.dtsi index 2a42a5ebe72..c3382bca86f 100644 --- a/dts/riscv/starfive/jh7110-visionfive-v2.dtsi +++ b/dts/riscv/starfive/jh7110-visionfive-v2.dtsi @@ -133,9 +133,9 @@ }; }; - ram0: memory@8000000 { + l2lim: memory@8000000 { device_type = "memory"; - reg = <0x0 0x8000000 0x1 0x0>; + reg = <0x0 0x8000000 0x0 0x200000>; }; soc { From 50c24f17e3af4d13b1989a0fafb538b498c6a062 Mon Sep 17 00:00:00 2001 From: Daniel Maslowski Date: Wed, 20 Mar 2024 20:46:55 +0100 Subject: [PATCH 2045/2402] soc: starfive: jh71xx: select 64BIT for SOC_JH7110 We get a 32bit binary otherwise. Signed-off-by: Daniel Maslowski --- soc/starfive/jh71xx/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/soc/starfive/jh71xx/Kconfig b/soc/starfive/jh71xx/Kconfig index b98817f20c8..823ffe08e95 100644 --- a/soc/starfive/jh71xx/Kconfig +++ b/soc/starfive/jh71xx/Kconfig @@ -25,3 +25,4 @@ config SOC_JH7110 select RISCV_ISA_EXT_C select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI + select 64BIT From 16189b007f2c4930b00f56696f4ddeed96416899 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Mon, 25 Mar 2024 19:06:31 +0100 Subject: [PATCH 2046/2402] Bluetooth: BAP: Only dump active receive states The bt_debug_dump_recv_state did not care if the receive state being dumped to log was active or not, and if it was not actice, then it may just contain random data. Added a check to see if it was active. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/bap_scan_delegator.c | 43 +++++++++++---------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/subsys/bluetooth/audio/bap_scan_delegator.c b/subsys/bluetooth/audio/bap_scan_delegator.c index 2e25d983f56..09cd2327051 100644 --- a/subsys/bluetooth/audio/bap_scan_delegator.c +++ b/subsys/bluetooth/audio/bap_scan_delegator.c @@ -118,26 +118,29 @@ static bool bis_syncs_unique_or_no_pref(uint32_t requested_bis_syncs, static void bt_debug_dump_recv_state(const struct bass_recv_state_internal *recv_state) { - const struct bt_bap_scan_delegator_recv_state *state = &recv_state->state; - const bool is_bad_code = state->encrypt_state == - BT_BAP_BIG_ENC_STATE_BAD_CODE; - - LOG_DBG("Receive State[%d]: src ID %u, addr %s, adv_sid %u, " - "broadcast_id 0x%06X, pa_sync_state %u, " - "encrypt state %u%s%s, num_subgroups %u", - recv_state->index, state->src_id, bt_addr_le_str(&state->addr), state->adv_sid, - state->broadcast_id, state->pa_sync_state, state->encrypt_state, - is_bad_code ? ", bad code" : "", - is_bad_code ? bt_hex(state->bad_code, sizeof(state->bad_code)) : "", - state->num_subgroups); - - for (int i = 0; i < state->num_subgroups; i++) { - const struct bt_bap_bass_subgroup *subgroup = &state->subgroups[i]; - - LOG_DBG("\tSubgroup[%d]: BIS sync %u (requested %u), metadata_len %zu, metadata: " - "%s", - i, subgroup->bis_sync, recv_state->requested_bis_sync[i], - subgroup->metadata_len, bt_hex(subgroup->metadata, subgroup->metadata_len)); + if (recv_state->active) { + const struct bt_bap_scan_delegator_recv_state *state = &recv_state->state; + const bool is_bad_code = state->encrypt_state == BT_BAP_BIG_ENC_STATE_BAD_CODE; + + LOG_DBG("Receive State[%d]: src ID %u, addr %s, adv_sid %u, broadcast_id 0x%06X, " + "pa_sync_state %u, encrypt state %u%s%s, num_subgroups %u", + recv_state->index, state->src_id, bt_addr_le_str(&state->addr), + state->adv_sid, state->broadcast_id, state->pa_sync_state, + state->encrypt_state, is_bad_code ? ", bad code" : "", + is_bad_code ? bt_hex(state->bad_code, sizeof(state->bad_code)) : "", + state->num_subgroups); + + for (uint8_t i = 0U; i < state->num_subgroups; i++) { + const struct bt_bap_bass_subgroup *subgroup = &state->subgroups[i]; + + LOG_DBG("\tSubgroup[%u]: BIS sync %u (requested %u), metadata_len %zu, " + "metadata: %s", + i, subgroup->bis_sync, recv_state->requested_bis_sync[i], + subgroup->metadata_len, + bt_hex(subgroup->metadata, subgroup->metadata_len)); + } + } else { + LOG_DBG("Inactive receive state"); } } From 16ec531a5b913e9abc03395bf9bfc86d0619ac09 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 26 Mar 2024 14:54:12 +0100 Subject: [PATCH 2047/2402] Bluetooth: Audio: Shell: Disable EATT support EATT is not properly used by LE audio nor is the Zephyr implementation very good, so disable for now or at least until the BSIM tests are passing with it enabled. Signed-off-by: Emil Gydesen --- tests/bluetooth/shell/audio.conf | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/bluetooth/shell/audio.conf b/tests/bluetooth/shell/audio.conf index 264d06cec20..d28c311feef 100644 --- a/tests/bluetooth/shell/audio.conf +++ b/tests/bluetooth/shell/audio.conf @@ -12,7 +12,6 @@ CONFIG_BT_CENTRAL=y CONFIG_BT_PERIPHERAL=y CONFIG_BT_PRIVACY=y CONFIG_BT_L2CAP_ECRED=y -CONFIG_BT_EATT=y CONFIG_BT_SIGNING=y CONFIG_BT_FIXED_PASSKEY=y CONFIG_BT_ATT_PREPARE_COUNT=5 From a087a40ac6d01f183b192b50fa6cce11c71c42cf Mon Sep 17 00:00:00 2001 From: Kapil Bhatt Date: Fri, 5 Apr 2024 16:35:19 +0530 Subject: [PATCH 2048/2402] net: wifi: Remove constraints for dwell time There is no limitations for dwell time. Just add valid condition for positive value. So , it's better to remove those constraints. Signed-off-by: Kapil Bhatt --- include/zephyr/net/wifi_mgmt.h | 6 ------ subsys/net/l2/wifi/wifi_shell.c | 11 +++-------- 2 files changed, 3 insertions(+), 14 deletions(-) diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h index 7a812c4fa7e..ea3cbf8961c 100644 --- a/include/zephyr/net/wifi_mgmt.h +++ b/include/zephyr/net/wifi_mgmt.h @@ -48,12 +48,6 @@ extern "C" { #endif /* CONFIG_WIFI_MGMT_SCAN_CHAN_MAX_MANUAL */ #define WIFI_MGMT_BAND_STR_SIZE_MAX 8 -#define WIFI_MGMT_SCAN_MIN_DWELL_TIME_ACTIVE 5 -#define WIFI_MGMT_SCAN_MAX_DWELL_TIME_ACTIVE 1000 -#define WIFI_MGMT_SCAN_MIN_DWELL_TIME_PASSIVE 10 -#define WIFI_MGMT_SCAN_MAX_DWELL_TIME_PASSIVE 1000 -#define WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_ACTIVE 50 -#define WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_PASSIVE 130 #define WIFI_MGMT_SCAN_MAX_BSS_CNT 65535 /** Wi-Fi management commands */ diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index d985d810ed0..3eb4dac5ddd 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -683,8 +683,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, case 'a': val = atoi(state->optarg); - if ((val < WIFI_MGMT_SCAN_MIN_DWELL_TIME_ACTIVE) || - (val > WIFI_MGMT_SCAN_MAX_DWELL_TIME_ACTIVE)) { + if (val < 0) { PR_ERROR("Invalid dwell_time_active val\n"); return -ENOEXEC; } @@ -695,8 +694,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, case 'p': val = atoi(state->optarg); - if ((val < WIFI_MGMT_SCAN_MIN_DWELL_TIME_PASSIVE) || - (val > WIFI_MGMT_SCAN_MAX_DWELL_TIME_PASSIVE)) { + if (val < 0) { PR_ERROR("Invalid dwell_time_passive val\n"); return -ENOEXEC; } @@ -754,10 +752,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, static int cmd_wifi_scan(const struct shell *sh, size_t argc, char *argv[]) { struct net_if *iface = net_if_get_first_wifi(); - struct wifi_scan_params params = { .dwell_time_active = - WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_ACTIVE, - .dwell_time_passive = - WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_PASSIVE, }; + struct wifi_scan_params params = { 0 }; bool do_scan = true; int opt_num; From f2495b7d578d1e7f5be7fce1c01d543fb2f60e05 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Fri, 5 Apr 2024 12:25:37 +0000 Subject: [PATCH 2049/2402] ci: twister: Remove Blackbox artifacts Blackbox tests do not produce easily accessible artifacts. Thus, the upload steps ought to be removed. Signed-off-by: Lukasz Mrugala --- .github/workflows/twister_tests_blackbox.yml | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index 7b0e1893225..ec380f0eecd 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -75,19 +75,3 @@ jobs: echo "Run twister tests" source zephyr-env.sh PYTHONPATH="./scripts/tests" pytest ./scripts/tests/twister_blackbox - - - name: Upload Unit Test Results - if: success() || failure() - uses: actions/upload-artifact@v2 - with: - name: Black Box Test Results (Python ${{ matrix.python-version }}) - path: | - twister-out*/twister.log - twister-out*/twister.json - twister-out*/testplan.log - retention-days: 14 - - - name: Clear Workspace - if: success() || failure() - run: | - rm -rf twister-out*/ From 5f95ec76a1396328237ba8f9af96ec7ed4cafde4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 3 Apr 2024 13:22:18 +0200 Subject: [PATCH 2050/2402] doc: releases: release-notes: 3.7: add informations on random helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Release notes for random PR #70513 Signed-off-by: Fin Maaß --- doc/releases/release-notes-3.7.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index d631a6b13f3..a98211d48ac 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -225,6 +225,12 @@ Libraries / Subsystems * Crypto +* Random + + * Besides the existing :c:func:`sys_rand32_get` function, :c:func:`sys_rand8_get`, + :c:func:`sys_rand16_get` and :c:func:`sys_rand64_get` are now also available. + These functions are all implemented on top of :c:func:`sys_rand_get`. + * Retention * SD From a83d2dad8d2be9d604d6a91c4856f9f0dceb7e3a Mon Sep 17 00:00:00 2001 From: Nazar Palamar Date: Tue, 2 Apr 2024 00:20:03 +0300 Subject: [PATCH 2051/2402] wifi: airoc: remove dependency on CYHAL Removing dependency on cyhal in airoc wifi driver. It need to build airoc wifi driver with different than PSoC 6 Soc like STM32 Signed-off-by: Nazar Palamar --- drivers/wifi/infineon/airoc_whd_hal.c | 5 +++-- drivers/wifi/infineon/airoc_wifi.h | 2 +- modules/hal_infineon/CMakeLists.txt | 6 ++++++ modules/hal_infineon/Kconfig | 10 +++++----- 4 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/wifi/infineon/airoc_whd_hal.c b/drivers/wifi/infineon/airoc_whd_hal.c index 5b02d0bba49..b3a68102851 100644 --- a/drivers/wifi/infineon/airoc_whd_hal.c +++ b/drivers/wifi/infineon/airoc_whd_hal.c @@ -11,6 +11,7 @@ #include #include #include +#include #define DT_DRV_COMPAT infineon_airoc_wifi @@ -103,14 +104,14 @@ int airoc_wifi_power_on(const struct device *dev) } /* Allow CBUCK regulator to discharge */ - (void)cyhal_system_delay_ms(WLAN_CBUCK_DISCHARGE_MS); + (void)k_msleep(WLAN_CBUCK_DISCHARGE_MS); /* WIFI power on */ ret = gpio_pin_set_dt(&config->wifi_reg_on_gpio, 1); if (ret) { return ret; } - (void)cyhal_system_delay_ms(WLAN_POWER_UP_DELAY_MS); + (void)k_msleep(WLAN_POWER_UP_DELAY_MS); #endif /* DT_INST_NODE_HAS_PROP(0, reg_on_gpios) */ return 0; diff --git a/drivers/wifi/infineon/airoc_wifi.h b/drivers/wifi/infineon/airoc_wifi.h index 648423ab109..1bf688e5d72 100644 --- a/drivers/wifi/infineon/airoc_wifi.h +++ b/drivers/wifi/infineon/airoc_wifi.h @@ -10,7 +10,7 @@ #include #include #include -#include +#include struct airoc_wifi_data { struct sd_card card; diff --git a/modules/hal_infineon/CMakeLists.txt b/modules/hal_infineon/CMakeLists.txt index 27dbd71897f..99d925b1396 100644 --- a/modules/hal_infineon/CMakeLists.txt +++ b/modules/hal_infineon/CMakeLists.txt @@ -39,6 +39,12 @@ endif() ## Add Wi-Fi assets for AIROC devices if (CONFIG_WIFI_AIROC) add_subdirectory(wifi-host-driver) + + ## Add core-lib sources for CAT1 devices + add_subdirectory_ifndef(CONFIG_SOC_FAMILY_INFINEON_CAT1 core-lib) + + ## Add abstraction-rtos sources + add_subdirectory_ifndef(CONFIG_SOC_FAMILY_INFINEON_CAT1 abstraction-rtos) endif() ## Add BT assets for AIROC devices diff --git a/modules/hal_infineon/Kconfig b/modules/hal_infineon/Kconfig index af92b98b3dc..723579c5d5b 100644 --- a/modules/hal_infineon/Kconfig +++ b/modules/hal_infineon/Kconfig @@ -72,14 +72,14 @@ config USE_INFINEON_WDT Enable WATCHDOG TIMER (WDT) HAL module driver for Infineon devices -config USE_INFINEON_ABSTRACTION_RTOS - bool "Abstraction RTOS component (Zephyr support)" - help - Enable Abstraction RTOS component with Zephyr support - config USE_INFINEON_FLASH bool help Enable Flash HAL module driver for Infineon devices endif # SOC_FAMILY_PSOC6 + +config USE_INFINEON_ABSTRACTION_RTOS + bool "Abstraction RTOS component (Zephyr support)" + help + Enable Abstraction RTOS component with Zephyr support From d5897a48aaab546751a6a5bb71cf4d441c229c1c Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Mon, 4 Mar 2024 14:49:55 +0100 Subject: [PATCH 2052/2402] ipc: intel_adsp: Ensure IPC completion before runtime idle Prevent the system from entering runtime idle state during IPC transactions until the HOST acknowledgment is received. This patch modifies the IPC mechanism to: - Lock the runtime idle state immediately after sending an IPC message to the HOST, preventing the system from entering a low-power state. - Unlock the runtime idle state once the IPC transaction is acknowledged by the HOST, allowing the system to enter low-power states if conditions permit. The changes ensure that the DSP does not enter a power state that could interrupt the IPC communication process, maintaining the integrity of the IPC state machine. Signed-off-by: Tomasz Leman --- soc/intel/intel_adsp/common/ipc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/soc/intel/intel_adsp/common/ipc.c b/soc/intel/intel_adsp/common/ipc.c index a73d696a68a..bffa2e6710d 100644 --- a/soc/intel/intel_adsp/common/ipc.c +++ b/soc/intel/intel_adsp/common/ipc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include void intel_adsp_ipc_set_message_handler(const struct device *dev, @@ -73,6 +74,10 @@ void z_intel_adsp_ipc_isr(const void *devarg) external_completion = devdata->done_notify(dev, devdata->done_arg); } devdata->tx_ack_pending = false; + /* Allow the system to enter the runtime idle state after the IPC acknowledgment + * is received. + */ + pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); k_sem_give(&devdata->sem); /* IPC completion registers will be set externally */ @@ -158,6 +163,8 @@ int intel_adsp_ipc_send_message(const struct device *dev, } k_sem_init(&devdata->sem, 0, 1); + /* Prevent entering runtime idle state until IPC acknowledgment is received. */ + pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); devdata->tx_ack_pending = true; config->regs->idd = ext_data; config->regs->idr = data | INTEL_ADSP_IPC_BUSY; From a200dd88d878a74aaf036ebf22986293e7081e91 Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Thu, 21 Mar 2024 18:06:49 +0100 Subject: [PATCH 2053/2402] dts: xtensa: intel_adsp: Set soft-off state as disabled Configure the 'soft-off' power state for manual selection only in the DTS for Intel ADSP ACE 1.5 MTPM and ACE 2.0 LNL platforms. Changes include: - Setting 'min-residency-us' to 0 to indicate that the 'soft-off' state is not intended for automatic selection by the power management policy. - Adding a 'status' property set to "disabled" to prevent the power management policy from using this state during its decision process. The 'soft-off' state remains available for manual selection by calling `pm_state_force`. This change ensures that the state can still be used when explicitly requested by the system or application, providing flexibility for power management operations. Signed-off-by: Tomasz Leman --- dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi | 3 ++- dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi index 9c92387e36a..352e119b3aa 100644 --- a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi @@ -48,8 +48,9 @@ d3: off { compatible = "zephyr,power-state"; power-state-name = "soft-off"; - min-residency-us = <2147483647>; + min-residency-us = <0>; exit-latency-us = <0>; + status = "disabled"; }; }; }; diff --git a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi index 91535c92dcd..d89dcb9c7f6 100644 --- a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi @@ -62,8 +62,9 @@ d3: off { compatible = "zephyr,power-state"; power-state-name = "soft-off"; - min-residency-us = <2147483647>; + min-residency-us = <0>; exit-latency-us = <0>; + status = "disabled"; }; }; }; From aee8dd1d33bf0ca1088288a36bc1ab08f138f156 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 26 Mar 2024 16:33:06 +0100 Subject: [PATCH 2054/2402] kernel: timeout: Optimize setting next alarm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Next timeout was set unconditionally at the end of sys_clock_announce. However, if one of the current expired timeouts was setting a new timeout which is the first to execute then system clock was configured twice. Lets configure system clock only once in the isr at the and of sys_clock_announce. If timeouts are frequent this optimization can reduce CPU load. In many cases setting the new sys_clock timeout is the most time consuming operation in the sys_clock isr handler. As an example, on the target I used setting new sys_clock timeout is taking 6 uS of 9 uS spent in the isr and it takes 16 uS with the redundant call. Signed-off-by: Krzysztof Chruściński --- kernel/timeout.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/timeout.c b/kernel/timeout.c index 3d5cb51c0f0..8c727e204f9 100644 --- a/kernel/timeout.c +++ b/kernel/timeout.c @@ -135,7 +135,7 @@ void z_add_timeout(struct _timeout *to, _timeout_func_t fn, sys_dlist_append(&timeout_list, &to->node); } - if (to == first()) { + if (to == first() && announce_remaining == 0) { sys_clock_set_timeout(next_timeout(), false); } } From eeb527a5da4a384f464caa4cbf0bdb5a34274598 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Fri, 5 Apr 2024 17:04:08 +0200 Subject: [PATCH 2055/2402] net: Restore the default networking behavior on qemu platforms Commit e99b5228a1f9dd162dd3d6be1eda42b26d762da3 changed the default networking behavior on qemu platforms, as the SLIP_TAP driver no longer selected Ethernet L2. In results, qemu platforms in default configuration had no network interface to work with. Fix this, by restoring select for NET_L2_ETHERNET, but this time in NET_SLIP_TAP. The difference is that SLIP_TAP is a generic driver config, which could be enabled on any platform, so not changing the behavior here, while NET_SLIP_TAP is a config dedicated for qemu only, so it's reasonable to enable all that's needed to get SLIP to work with qemu by default. As there were circular Kconfig dependencies, move the respective qemu configs outside of NET_RAW_MODE if block (as this caused the circular dependency with ETH_DRIVER_RAW_MODE). Also, remove dependency to NET_L2_BT, as it made little sense there, and also caused dependency problems. Signed-off-by: Robert Lubos --- subsys/net/ip/Kconfig | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/subsys/net/ip/Kconfig b/subsys/net/ip/Kconfig index bc5442d44ba..29553e464c1 100644 --- a/subsys/net/ip/Kconfig +++ b/subsys/net/ip/Kconfig @@ -88,8 +88,6 @@ config NET_RAW_MODE net_pkt part. It is currently used only by IEEE 802.15.4 drivers, though any type of net drivers could use it. -if !NET_RAW_MODE - choice NET_QEMU_NETWORKING prompt "Qemu networking" default NET_QEMU_PPP if NET_PPP @@ -134,6 +132,8 @@ config NET_QEMU_USER_EXTRA_ARGS include host / guest port forwarding, device id, Network address information etc. This string is appended to the QEMU "-net user" option. +if !NET_RAW_MODE + config NET_INIT_PRIO int default 90 @@ -583,6 +583,8 @@ config NET_CONTEXT_RECV_PKTINFO This way user can get extra information about the received data in the socket. +endif # NET_RAW_MODE + config NET_SLIP_TAP bool "TAP SLIP driver" depends on NET_QEMU_SLIP @@ -591,15 +593,14 @@ config NET_SLIP_TAP select UART_PIPE select UART_INTERRUPT_DRIVEN select SLIP_TAP - default y if (QEMU_TARGET && !NET_TEST && !NET_L2_BT) + select NET_L2_ETHERNET + default y if (QEMU_TARGET && !NET_TEST) help SLIP TAP support is necessary when testing with QEMU. The host needs to have tunslip6 with TAP support running in order to communicate via the SLIP driver. See net-tools project at https://github.com/zephyrproject-rtos/net-tools for more details. -endif # NET_RAW_MODE - config NET_TEST bool "Network Testing" help From 17abc2743b6c9795f3e5a789f8345a885c844757 Mon Sep 17 00:00:00 2001 From: Nick Ward Date: Tue, 9 Apr 2024 21:01:10 +1000 Subject: [PATCH 2056/2402] net: lib: coap: set MAX_RETRANSMIT maximum to 100 Some application environments may need it. Signed-off-by: Nick Ward --- subsys/net/lib/coap/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/lib/coap/Kconfig b/subsys/net/lib/coap/Kconfig index 63396bb0518..61a5d2ab785 100644 --- a/subsys/net/lib/coap/Kconfig +++ b/subsys/net/lib/coap/Kconfig @@ -80,7 +80,7 @@ config COAP_ACK_RANDOM_PERCENT config COAP_MAX_RETRANSMIT int "Max retransmission of a CoAP packet" default 4 - range 1 10 + range 1 100 config COAP_BACKOFF_PERCENT int "Retransmission backoff factor for ACK timeout described as percentage" From 741bbaca6dd727a5d81856ae67f45dfb9a3e32b8 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Tue, 12 Mar 2024 11:11:03 -0700 Subject: [PATCH 2057/2402] soc/intel_adsp: ipc: Remove unnecessary device state lock There is no needed to lock/unlock a device state in its pm action callback. The power management subsystem should take care of serialize these calls. Signed-off-by: Flavio Ceolin --- soc/intel/intel_adsp/common/ipc.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/soc/intel/intel_adsp/common/ipc.c b/soc/intel/intel_adsp/common/ipc.c index bffa2e6710d..5a444f2d459 100644 --- a/soc/intel/intel_adsp/common/ipc.c +++ b/soc/intel/intel_adsp/common/ipc.c @@ -292,7 +292,6 @@ static int ipc_pm_action(const struct device *dev, enum pm_device_action action) switch (action) { case PM_DEVICE_ACTION_SUSPEND: - pm_device_state_lock(dev); if (api->suspend_fn) { ret = api->suspend_fn(dev, api->suspend_fn_args); if (!ret) { @@ -301,7 +300,6 @@ static int ipc_pm_action(const struct device *dev, enum pm_device_action action) } break; case PM_DEVICE_ACTION_RESUME: - pm_device_state_lock(dev); irq_enable(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE)); if (!irq_is_enabled(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE))) { ret = -EINTR; @@ -321,7 +319,6 @@ static int ipc_pm_action(const struct device *dev, enum pm_device_action action) return -ENOTSUP; } - pm_device_state_unlock(dev); return ret; } From e85226fd1a034738a4f770d6c71e68009ed72a9a Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Tue, 12 Mar 2024 12:00:44 -0700 Subject: [PATCH 2058/2402] soc/intel_adsp: ipc: Remove fragile device state check Checking if the device state is locked is not correct, device runtime put / get is no longer checking for it and the only place that was locking device's state was the pm action callback and if the idea was to protect some concurrent call, using it is not enough. Signed-off-by: Flavio Ceolin --- soc/intel/intel_adsp/common/ipc.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/soc/intel/intel_adsp/common/ipc.c b/soc/intel/intel_adsp/common/ipc.c index 5a444f2d459..987189ce1fe 100644 --- a/soc/intel/intel_adsp/common/ipc.c +++ b/soc/intel/intel_adsp/common/ipc.c @@ -148,10 +148,6 @@ int intel_adsp_ipc_send_message(const struct device *dev, } #endif - if (pm_device_state_is_locked(INTEL_ADSP_IPC_HOST_DEV)) { - return -EAGAIN; - } - pm_device_busy_set(dev); const struct intel_adsp_ipc_config *config = dev->config; struct intel_adsp_ipc_data *devdata = dev->data; From 3b895064afaf7924a80def09bd1edeefa61ebc9f Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Tue, 12 Mar 2024 12:19:06 -0700 Subject: [PATCH 2059/2402] pm: Remove state lock/unlock API This API is not widely used and it is actually broken since device runtime power management is not checking it when suspending and resuming. On top of that, this API is very close to pm_device_busy* API, close enough to consolidate in only one API. Signed-off-by: Flavio Ceolin --- include/zephyr/pm/device.h | 52 ------------------- subsys/pm/device.c | 34 ------------ subsys/pm/device_runtime.c | 5 -- subsys/pm/pm.c | 1 - tests/subsys/pm/device_runtime_api/src/main.c | 12 ----- tests/subsys/pm/power_mgmt/src/main.c | 15 ------ 6 files changed, 119 deletions(-) diff --git a/include/zephyr/pm/device.h b/include/zephyr/pm/device.h index d607fc4a042..ce0e53d7446 100644 --- a/include/zephyr/pm/device.h +++ b/include/zephyr/pm/device.h @@ -44,8 +44,6 @@ enum pm_device_flag { PM_DEVICE_FLAG_WS_ENABLED, /** Indicates if device runtime is enabled */ PM_DEVICE_FLAG_RUNTIME_ENABLED, - /** Indicates if the device pm is locked. */ - PM_DEVICE_FLAG_STATE_LOCKED, /** Indicates if the device is used as a power domain */ PM_DEVICE_FLAG_PD, /** Indicates if device runtime PM should be automatically enabled */ @@ -569,43 +567,6 @@ bool pm_device_wakeup_is_enabled(const struct device *dev); */ bool pm_device_wakeup_is_capable(const struct device *dev); -/** - * @brief Lock current device state. - * - * This function locks the current device power state. Once - * locked the device power state will not be changed by - * system power management or device runtime power - * management until unlocked. - * - * @note The given device should not have device runtime enabled. - * - * @see pm_device_state_unlock - * - * @param dev Device instance. - */ -void pm_device_state_lock(const struct device *dev); - -/** - * @brief Unlock the current device state. - * - * Unlocks a previously locked device pm. - * - * @see pm_device_state_lock - * - * @param dev Device instance. - */ -void pm_device_state_unlock(const struct device *dev); - -/** - * @brief Check if the device pm is locked. - * - * @param dev Device instance. - * - * @retval true If device is locked. - * @retval false If device is not locked. - */ -bool pm_device_state_is_locked(const struct device *dev); - /** * @brief Check if the device is on a switchable power domain. * @@ -723,19 +684,6 @@ static inline bool pm_device_wakeup_is_capable(const struct device *dev) ARG_UNUSED(dev); return false; } -static inline void pm_device_state_lock(const struct device *dev) -{ - ARG_UNUSED(dev); -} -static inline void pm_device_state_unlock(const struct device *dev) -{ - ARG_UNUSED(dev); -} -static inline bool pm_device_state_is_locked(const struct device *dev) -{ - ARG_UNUSED(dev); - return false; -} static inline bool pm_device_on_power_domain(const struct device *dev) { ARG_UNUSED(dev); diff --git a/subsys/pm/device.c b/subsys/pm/device.c index ca3816fa93b..dcc05ce125a 100644 --- a/subsys/pm/device.c +++ b/subsys/pm/device.c @@ -49,10 +49,6 @@ int pm_device_action_run(const struct device *dev, return -ENOSYS; } - if (pm_device_state_is_locked(dev)) { - return -EPERM; - } - /* Validate action against current state */ if (pm->state == action_target_state[action]) { return -EALREADY; @@ -327,36 +323,6 @@ bool pm_device_wakeup_is_capable(const struct device *dev) PM_DEVICE_FLAG_WS_CAPABLE); } -void pm_device_state_lock(const struct device *dev) -{ - struct pm_device_base *pm = dev->pm_base; - - if ((pm != NULL) && !pm_device_runtime_is_enabled(dev)) { - atomic_set_bit(&pm->flags, PM_DEVICE_FLAG_STATE_LOCKED); - } -} - -void pm_device_state_unlock(const struct device *dev) -{ - struct pm_device_base *pm = dev->pm_base; - - if (pm != NULL) { - atomic_clear_bit(&pm->flags, PM_DEVICE_FLAG_STATE_LOCKED); - } -} - -bool pm_device_state_is_locked(const struct device *dev) -{ - struct pm_device_base *pm = dev->pm_base; - - if (pm == NULL) { - return false; - } - - return atomic_test_bit(&pm->flags, - PM_DEVICE_FLAG_STATE_LOCKED); -} - bool pm_device_on_power_domain(const struct device *dev) { #ifdef CONFIG_PM_DEVICE_POWER_DOMAIN diff --git a/subsys/pm/device_runtime.c b/subsys/pm/device_runtime.c index 8a35e24ca94..533caddd503 100644 --- a/subsys/pm/device_runtime.c +++ b/subsys/pm/device_runtime.c @@ -422,11 +422,6 @@ int pm_device_runtime_enable(const struct device *dev) goto end; } - if (pm_device_state_is_locked(dev)) { - ret = -EPERM; - goto end; - } - if (atomic_test_bit(&dev->pm_base->flags, PM_DEVICE_FLAG_ISR_SAFE)) { ret = runtime_enable_sync(dev); goto end; diff --git a/subsys/pm/pm.c b/subsys/pm/pm.c index 2b17817e0bb..d81072c3a5b 100644 --- a/subsys/pm/pm.c +++ b/subsys/pm/pm.c @@ -66,7 +66,6 @@ static int pm_suspend_devices(void) * devices with runtime PM enabled. */ if (!device_is_ready(dev) || pm_device_is_busy(dev) || - pm_device_state_is_locked(dev) || pm_device_wakeup_is_enabled(dev) || pm_device_runtime_is_enabled(dev)) { continue; diff --git a/tests/subsys/pm/device_runtime_api/src/main.c b/tests/subsys/pm/device_runtime_api/src/main.c index 623aa20b612..74f46eaf755 100644 --- a/tests/subsys/pm/device_runtime_api/src/main.c +++ b/tests/subsys/pm/device_runtime_api/src/main.c @@ -250,18 +250,6 @@ ZTEST(device_runtime_api, test_api) /* Put operation should fail due the state be locked. */ ret = pm_device_runtime_disable(test_dev); zassert_equal(ret, 0); - - pm_device_state_lock(test_dev); - - /* This operation should not succeed. */ - ret = pm_device_runtime_enable(test_dev); - zassert_equal(ret, -EPERM); - - /* After unlock the state, enable runtime should work. */ - pm_device_state_unlock(test_dev); - - ret = pm_device_runtime_enable(test_dev); - zassert_equal(ret, 0); } DEVICE_DEFINE(pm_unsupported_device, "PM Unsupported", NULL, NULL, NULL, NULL, diff --git a/tests/subsys/pm/power_mgmt/src/main.c b/tests/subsys/pm/power_mgmt/src/main.c index 4cd219ed5c3..73e64020ec8 100644 --- a/tests/subsys/pm/power_mgmt/src/main.c +++ b/tests/subsys/pm/power_mgmt/src/main.c @@ -437,21 +437,6 @@ ZTEST(power_management_1cpu, test_busy) zassert_false(busy); } -ZTEST(power_management_1cpu, test_device_state_lock) -{ - pm_device_state_lock(device_a); - zassert_true(pm_device_state_is_locked(device_a)); - - testing_device_lock = true; - enter_low_power = true; - - k_sleep(SLEEP_TIMEOUT); - - pm_device_state_unlock(device_a); - - testing_device_lock = false; -} - ZTEST(power_management_1cpu, test_empty_states) { const struct pm_state_info *cpu_states; From 0be0d2175bdbb660f510a6056794569b2527d348 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Thu, 21 Mar 2024 09:56:27 +0000 Subject: [PATCH 2060/2402] cmake: modules: extensions: Revert using common board files This change reverts a change that was introduced with hwmv2 which allowed for using common board names for overlays, given the board target ``nrf9160dk@0.7.0/nrf9160/ns``. In hwmv1 this would have used: ``nrf9160dk_nrf9160_ns.conf``. ``nrf9160dk_nrf9160_ns_0_7_0.conf``. In hwmv2 this would have used: ``nrf9160dk_nrf9160_ns.conf`` ``nrf9160dk_nrf9160_ns_0_7_0.conf`` ``nrf9160dk_nrf9160.conf`` ``nrf9160dk_nrf9160_0_7_0.conf`` ``nrf9160dk.conf`` ``nrf9160dk_0_7_0.conf`` With these changes, the following are used (which restores the hwmv1 behaviour): ``nrf9160dk_nrf9160_ns.conf`` ``nrf9160dk_nrf9160_ns_0_7_0.conf`` For a board with a default SoC which is not a variant for example ``rpi_pico`` then ``rpi_pico.conf`` will also be used, this file will not be used for variants e.g. ``rpi_pico/rp2040/w`` This applies to .dts, .conf and .overlay files in the boards directory, and to .conf and .overlay files in application board overlay directories. This revert is needed to avoid issues whereby variants have incompatible configuration to the parent board target, which has been affecting samples and tests. Signed-off-by: Jamie McCrae --- cmake/modules/extensions.cmake | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index 8f9be83b140..909887e6393 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -1519,8 +1519,7 @@ endfunction() # build string as first item in the list. # The full order of build strings returned in the list will be: # - Normalized board target build string, this includes qualifiers and revision -# - Build string with board variants removed in addition -# - Build string with cpuset removed in addition +# - Normalized board target build string, without revision # - Build string with soc removed in addition # # If BUILD is supplied, then build type will be appended to each entry in the @@ -1561,7 +1560,7 @@ endfunction() # calling # zephyr_build_string(build_string BOARD alpha BOARD_REVISION 1.0.0 BOARD_QUALIFIERS /soc/bar MERGE) # will return a list of the following strings -# `alpha_soc_bar_1_0_0;alpha_soc_bar;alpha_soc_1_0_0;alpha_soc;alpha_1_0_0;alpha` in `build_string` parameter. +# `alpha_soc_bar_1_0_0;alpha_soc_bar;alpha_bar` in `build_string` parameter. # function(zephyr_build_string outvar) set(options MERGE REVERSE) @@ -1595,20 +1594,17 @@ function(zephyr_build_string outvar) string(JOIN "_" ${outvar} ${str_segment_list} ${revision_string} ${BUILD_STR_BUILD}) if(BUILD_STR_MERGE) - if(DEFINED BUILD_STR_BOARD_REVISION) - string(JOIN "_" variant_string ${str_segment_list} ${BUILD_STR_BUILD}) + string(JOIN "_" variant_string ${str_segment_list} ${BUILD_STR_BUILD}) + + if(NOT "${variant_string}" IN_LIST ${outvar}) list(APPEND ${outvar} "${variant_string}") endif() - list(POP_BACK str_segment_list) - while(NOT str_segment_list STREQUAL "") - if(DEFINED BUILD_STR_BOARD_REVISION) - string(JOIN "_" variant_string ${str_segment_list} ${revision_string} ${BUILD_STR_BUILD}) - list(APPEND ${outvar} "${variant_string}") - endif() - string(JOIN "_" variant_string ${str_segment_list} ${BUILD_STR_BUILD}) - list(APPEND ${outvar} "${variant_string}") - list(POP_BACK str_segment_list) - endwhile() + + if(BUILD_STR_BOARD_QUALIFIERS) + string(REGEX REPLACE "^/[^/]*(.*)" "\\1" qualifiers_without_soc "${BUILD_STR_BOARD_QUALIFIERS}") + string(REPLACE "/" "_" qualifiers_without_soc "${qualifiers_without_soc}") + list(APPEND ${outvar} "${BUILD_STR_BOARD}${qualifiers_without_soc}") + endif() endif() if(BUILD_STR_REVERSE) From 96b6c0c015279ac486ecc75ebc6aca4ef5c96d43 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Thu, 21 Mar 2024 10:02:13 +0000 Subject: [PATCH 2061/2402] Revert "boards: Raspberry Pi pico pwm led adjustment" This reverts commit 037a3b52a49a8e26ac3ee4bdac46c72d76bc7399. Signed-off-by: Jamie McCrae --- boards/raspberrypi/rpi_pico/rpi_pico.dts | 4 ---- samples/basic/blinky_pwm/boards/rpi_pico.overlay | 6 ------ samples/basic/blinky_pwm/sample.yaml | 1 + 3 files changed, 1 insertion(+), 10 deletions(-) diff --git a/boards/raspberrypi/rpi_pico/rpi_pico.dts b/boards/raspberrypi/rpi_pico/rpi_pico.dts index f92c55c6825..97d721024d7 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico.dts +++ b/boards/raspberrypi/rpi_pico/rpi_pico.dts @@ -8,10 +8,6 @@ #include "rpi_pico-common.dtsi" -/* Only the rpi_pico/rp2040 has a pwm. */ -/* This define can be used to avoid sourcing board overlays when the PWM is not available */ -#define HAS_DT_PWM_LED 1 - / { leds { compatible = "gpio-leds"; diff --git a/samples/basic/blinky_pwm/boards/rpi_pico.overlay b/samples/basic/blinky_pwm/boards/rpi_pico.overlay index 2487fc181f1..43e054ede94 100644 --- a/samples/basic/blinky_pwm/boards/rpi_pico.overlay +++ b/samples/basic/blinky_pwm/boards/rpi_pico.overlay @@ -1,7 +1,3 @@ -/* The rpi_pico/rp2040/w doesn't have a pwm. */ -/* Use the HAS_DT_PWM defined by the based board to identify when this overlay is valid */ -#if HAS_DT_PWM_LED - &{/pwm_leds} { status = "okay"; }; @@ -15,5 +11,3 @@ divider-frac-4 = <15>; divider-int-4 = <255>; }; - -#endif diff --git a/samples/basic/blinky_pwm/sample.yaml b/samples/basic/blinky_pwm/sample.yaml index de2cb234933..c08ec6f0adc 100644 --- a/samples/basic/blinky_pwm/sample.yaml +++ b/samples/basic/blinky_pwm/sample.yaml @@ -8,3 +8,4 @@ tests: - pwm depends_on: pwm harness: led + platform_exclude: rpi_pico/rp2040/w From 5308c4f2f12d4c9692a9b1d7144319d94a53861f Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Thu, 21 Mar 2024 10:02:18 +0000 Subject: [PATCH 2062/2402] Revert "samples: blinky_pwm: enable pwm_leds in rpi_pico overlay" This reverts commit 7277cae6fa7c3d0ad567b4f1ef9007dc12e44314. Signed-off-by: Jamie McCrae --- samples/basic/blinky_pwm/boards/rpi_pico.overlay | 4 ---- 1 file changed, 4 deletions(-) diff --git a/samples/basic/blinky_pwm/boards/rpi_pico.overlay b/samples/basic/blinky_pwm/boards/rpi_pico.overlay index 43e054ede94..c3a3f1ff5d3 100644 --- a/samples/basic/blinky_pwm/boards/rpi_pico.overlay +++ b/samples/basic/blinky_pwm/boards/rpi_pico.overlay @@ -1,7 +1,3 @@ -&{/pwm_leds} { - status = "okay"; -}; - &pwm_led0 { status = "okay"; }; From 79fe21c48c7c754e6156341a0a9ea2f3ecc9d62a Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Wed, 27 Mar 2024 10:21:29 +0000 Subject: [PATCH 2063/2402] Revert "sample: basic: blinky_pwm: Exclude rpi_pico w variant" This reverts commit c47c37d3db876f168f33bb3fa8c28ef8976093b6. Signed-off-by: Jamie McCrae --- samples/basic/blinky_pwm/sample.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/samples/basic/blinky_pwm/sample.yaml b/samples/basic/blinky_pwm/sample.yaml index c08ec6f0adc..de2cb234933 100644 --- a/samples/basic/blinky_pwm/sample.yaml +++ b/samples/basic/blinky_pwm/sample.yaml @@ -8,4 +8,3 @@ tests: - pwm depends_on: pwm harness: led - platform_exclude: rpi_pico/rp2040/w From 006ea0f6fba0ef27748c7609f6ee7d5fb3efa0b1 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Thu, 21 Mar 2024 12:31:50 +0000 Subject: [PATCH 2064/2402] boards: Split merged board file configuration up Splits configuration up that was merged as part of hwmv2 due to the merged configuration feature being reverted Signed-off-by: Jamie McCrae --- .../actinius_icarus_nrf9160_ns_defconfig | 19 ++++++++++++++ .../actinius_icarus_bee_nrf9160_ns_defconfig | 19 ++++++++++++++ .../actinius_icarus_som_nrf9160_ns_defconfig | 19 ++++++++++++++ ...ctinius_icarus_som_dk_nrf9160_ns_defconfig | 19 ++++++++++++++ ...er_aemv8r_fvp_aemv8r_aarch32_smp_defconfig | 22 ++++++++++++++++ ...er_aemv8r_fvp_aemv8r_aarch64_smp_defconfig | 19 ++++++++++++++ .../v2m_musca_b1_musca_b1_ns_defconfig | 9 +++++++ .../v2m_musca_s1_musca_s1_ns_defconfig | 9 +++++++ .../roc_rk3568_pc_rk3568_smp_defconfig | 24 +++++++++++++++--- .../adsp/intel_adsp_cavs25_tgph_defconfig | 18 ++++++++++++- .../bl5340_dvk/bl5340_dvk_nrf5340_defconfig | 1 - .../nrf5340_audio_dk_nrf5340_defconfig | 1 - boards/nordic/nrf54h20dk/nrf54h20dk_defconfig | 9 ------- .../nrf54h20dk_nrf54h20_cpuapp_defconfig | 7 ++++++ .../nrf54h20dk_nrf54h20_cpuppr_defconfig | 7 ++++++ .../nrf54h20dk_nrf54h20_cpuppr_xip_defconfig | 9 +++++++ .../nrf54h20dk_nrf54h20_cpurad_defconfig | 7 ++++++ .../nrf54l15pdk_nrf54l15_cpuapp_defconfig | 7 ++++++ .../nrf54l15pdk_nrf54l15_defconfig | 1 - .../thingy53/thingy53_nrf5340_defconfig | 1 - .../lpcxpresso55s69_lpc55s69_cpu0_defconfig | 5 ++++ ...lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig | 5 ++++ .../ls1046ardb_ls1046a_smp_4cores_defconfig | 18 +++++++++++++ .../ls1046ardb_ls1046a_smp_defconfig | 18 +++++++++++++ ...mu_riscv32_qemu_virt_riscv32_smp_defconfig | 6 +++++ ...mu_riscv64_qemu_virt_riscv64_smp_defconfig | 7 ++++++ .../x86/qemu_x86_64_atom_nokpti_defconfig | 13 ++++++++++ .../qemu/x86/qemu_x86_atom_nokpti_defconfig | 12 +++++++++ boards/qemu/x86/qemu_x86_atom_nommu_defconfig | 8 ++++++ boards/qemu/x86/qemu_x86_atom_nopae_defconfig | 12 +++++++++ boards/qemu/x86/qemu_x86_atom_virt_defconfig | 12 +++++++++ boards/qemu/x86/qemu_x86_atom_xip_defconfig | 11 ++++++++ .../raytac_mdbt53_db_40_nrf5340_defconfig | 1 - .../raytac_mdbt53v_db_40_nrf5340_defconfig | 1 - .../xiao_ble_nrf52840_sense_defconfig | 25 +++++++++++++++++++ .../em_starterkit_emsk_em7d_2_3_defconfig | 11 ++++++++ .../em_starterkit_emsk_em7d_defconfig | 11 ++++++++ .../em_starterkit_emsk_em9d_defconfig | 14 +++++++++++ boards/snps/emsdp/emsdp_emsdp_em11d_defconfig | 12 +++++++++ boards/snps/emsdp/emsdp_emsdp_em5d_defconfig | 12 +++++++++ boards/snps/emsdp/emsdp_emsdp_em6_defconfig | 12 +++++++++ boards/snps/emsdp/emsdp_emsdp_em7d_defconfig | 14 +++++++++++ .../snps/emsdp/emsdp_emsdp_em7d_esp_defconfig | 12 +++++++++ boards/snps/emsdp/emsdp_emsdp_em9d_defconfig | 12 +++++++++ .../snps/hsdk/hsdk_arc_hsdk_2cores_defconfig | 12 +++++++++ .../nsim/nsim_nsim_hs5x_smp_12cores_defconfig | 8 ++++++ boards/snps/nsim/nsim_nsim_hs5x_smp_defconfig | 8 ++++++ .../nsim/nsim_nsim_hs6x_smp_12cores_defconfig | 8 ++++++ boards/snps/nsim/nsim_nsim_hs6x_smp_defconfig | 8 ++++++ .../nsim/nsim_nsim_hs_flash_xip_defconfig | 8 ++++++ boards/snps/nsim/nsim_nsim_hs_smp_defconfig | 7 ++++++ boards/snps/nsim/nsim_nsim_hs_sram_defconfig | 8 ++++++ .../nsim_nsim_sem_mpu_stack_guard_defconfig | 9 +++++++ 53 files changed, 548 insertions(+), 19 deletions(-) delete mode 100644 boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_defconfig delete mode 100644 boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_defconfig delete mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_defconfig delete mode 100644 boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_defconfig delete mode 100644 boards/nordic/thingy53/thingy53_nrf5340_defconfig delete mode 100644 boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_defconfig delete mode 100644 boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_defconfig create mode 100644 boards/snps/em_starterkit/em_starterkit_emsk_em9d_defconfig create mode 100644 boards/snps/emsdp/emsdp_emsdp_em7d_defconfig diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_defconfig b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_defconfig index 4baa62c55ef..ec0a8605a57 100644 --- a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_defconfig +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_defconfig @@ -1,4 +1,23 @@ # SPDX-License-Identifier: Apache-2.0 +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + # This board implies building Non-Secure firmware CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns_defconfig b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns_defconfig index 4baa62c55ef..ec0a8605a57 100644 --- a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns_defconfig +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns_defconfig @@ -1,4 +1,23 @@ # SPDX-License-Identifier: Apache-2.0 +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + # This board implies building Non-Secure firmware CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns_defconfig b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns_defconfig index 4baa62c55ef..ec0a8605a57 100644 --- a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns_defconfig +++ b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns_defconfig @@ -1,4 +1,23 @@ # SPDX-License-Identifier: Apache-2.0 +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + # This board implies building Non-Secure firmware CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns_defconfig b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns_defconfig index 4baa62c55ef..ec0a8605a57 100644 --- a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns_defconfig +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns_defconfig @@ -1,4 +1,23 @@ # SPDX-License-Identifier: Apache-2.0 +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + # This board implies building Non-Secure firmware CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig index a320c3486f7..7c9e907f9c9 100644 --- a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig @@ -1,6 +1,28 @@ # Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. # SPDX-License-Identifier: Apache-2.0 +CONFIG_ARM_MPU=y + +CONFIG_ISR_STACK_SIZE=1024 +CONFIG_THREAD_STACK_INFO=y + +# Enable Timer and Sys clock +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_ARM_ARCH_TIMER=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE=n + CONFIG_USE_SWITCH=y CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=4 diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig index 286fc28d189..ae5d65df18f 100644 --- a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig @@ -1,6 +1,25 @@ # Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. # SPDX-License-Identifier: Apache-2.0 +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +CONFIG_THREAD_STACK_INFO=y + +# Enable Timer and Sys clock +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_ARM_ARCH_TIMER=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + # Enable simulated CPU power management CONFIG_SOC_FVP_AEMV8R_SIMULATE_CPU_PM=y CONFIG_PM_CPU_OPS=y diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns_defconfig b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns_defconfig index 925071fbdf4..39f48c06243 100644 --- a/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns_defconfig +++ b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns_defconfig @@ -4,4 +4,13 @@ # SPDX-License-Identifier: Apache-2.0 # +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns_defconfig b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns_defconfig index d5c8f4180ac..a06574b8f84 100644 --- a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns_defconfig +++ b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns_defconfig @@ -4,4 +4,13 @@ # SPDX-License-Identifier: Apache-2.0 # +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig index 5d5b627f549..92324fbe871 100644 --- a/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig +++ b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig @@ -2,14 +2,32 @@ # Copyright 2022 openEuler SIG-Zephyr # SPDX-License-Identifier: Apache-2.0 +# Platform Configuration +CONFIG_ARM_ARCH_TIMER=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_NS16550=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# ARMv8 NS world with cache management +CONFIG_ARMV8_A_NS=y +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE=y + +# Clock support +CONFIG_CLOCK_CONTROL=y +CONFIG_TICKLESS_KERNEL=y + # SMP support CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=4 CONFIG_MAX_THREAD_BYTES=4 -# ARMv8 NS world with cache management -CONFIG_DCACHE=y - # PSCI support CONFIG_PM_CPU_OPS=y CONFIG_PM_CPU_OPS_PSCI=y diff --git a/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig index a0b72230091..041043937bf 100644 --- a/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig +++ b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig @@ -2,7 +2,23 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_DAI_SSP_HAS_POWER_CONTROL=y +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_XTENSA_RESET_VECTOR=y + +CONFIG_XTENSA_USE_CORE_CRT1=y + +CONFIG_MULTI_LEVEL_INTERRUPTS=y +CONFIG_2ND_LEVEL_INTERRUPTS=y + +CONFIG_BUILD_OUTPUT_BIN=n CONFIG_MP_MAX_NUM_CPUS=2 CONFIG_CORE_COUNT=2 + +CONFIG_DCACHE_LINE_SIZE=64 + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_defconfig b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_defconfig deleted file mode 100644 index 9881313609a..00000000000 --- a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_defconfig +++ /dev/null @@ -1 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_defconfig b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_defconfig deleted file mode 100644 index 9881313609a..00000000000 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_defconfig +++ /dev/null @@ -1 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_defconfig deleted file mode 100644 index bad567cbd74..00000000000 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig index b014eb7b031..e1ba596d135 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig @@ -1,6 +1,13 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + CONFIG_USE_DT_CODE_PARTITION=y # Enable MPU diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig index 76aa51244f1..b6ee6107d46 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_defconfig @@ -1,6 +1,13 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + CONFIG_USE_DT_CODE_PARTITION=y # Execute from RAM diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_defconfig index d3d1bf7799f..d73f271870b 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_defconfig +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_defconfig @@ -1,4 +1,13 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_USE_DT_CODE_PARTITION=y + CONFIG_XIP=y diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_defconfig index 1a62a205502..27df01dee12 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_defconfig +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_defconfig @@ -1,6 +1,13 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + CONFIG_USE_DT_CODE_PARTITION=y # Enable MPU diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_defconfig b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_defconfig index 0352761e0ce..bb9fd0de14b 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_defconfig +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_defconfig @@ -1,6 +1,13 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_defconfig b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_defconfig deleted file mode 100644 index 9881313609a..00000000000 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_defconfig +++ /dev/null @@ -1 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/nordic/thingy53/thingy53_nrf5340_defconfig b/boards/nordic/thingy53/thingy53_nrf5340_defconfig deleted file mode 100644 index 9881313609a..00000000000 --- a/boards/nordic/thingy53/thingy53_nrf5340_defconfig +++ /dev/null @@ -1 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig index 966a0228f10..873503cfc73 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig @@ -4,6 +4,11 @@ # SPDX-License-Identifier: Apache-2.0 # +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_RUNTIME_NMI=y + CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig index 11924b6c377..98721c751a9 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig @@ -4,6 +4,11 @@ # SPDX-License-Identifier: Apache-2.0 # +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_RUNTIME_NMI=y + CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig index 2d2429f57d2..8ae910c3a70 100644 --- a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig @@ -1,4 +1,22 @@ # SPDX-License-Identifier: Apache-2.0 +# Platform Configuration +CONFIG_ARM64_VA_BITS_40=y +CONFIG_ARM64_PA_BITS_40=y +# 25 MHz system clock +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_AARCH64_IMAGE_HEADER=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + # SMP support CONFIG_MP_MAX_NUM_CPUS=4 diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig index ace2e242267..aab2de96cef 100644 --- a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig @@ -1,5 +1,23 @@ # SPDX-License-Identifier: Apache-2.0 +# Platform Configuration +CONFIG_ARM64_VA_BITS_40=y +CONFIG_ARM64_PA_BITS_40=y +# 25 MHz system clock +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_AARCH64_IMAGE_HEADER=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + # Zephyr Kernel Configuration CONFIG_MAX_THREAD_BYTES=5 CONFIG_MAX_XLAT_TABLES=10 diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig index 412b05982f3..f52d8927f0c 100644 --- a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig +++ b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig @@ -1,5 +1,11 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_STACK_SENTINEL=y +CONFIG_XIP=n +CONFIG_RISCV_PMP=y CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=2 CONFIG_IDLE_STACK_SIZE=1024 diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig index 412b05982f3..948e0bad363 100644 --- a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig +++ b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig @@ -1,5 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_PRIVILEGED_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_STACK_SENTINEL=y +CONFIG_XIP=n +CONFIG_RISCV_PMP=y CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=2 CONFIG_IDLE_STACK_SIZE=1024 diff --git a/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig b/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig index 01dd154ba5a..6b67200e544 100644 --- a/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig +++ b/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig @@ -1,4 +1,17 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2019 Intel Corp. +CONFIG_PIC_DISABLE=y +CONFIG_LOAPIC=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_DEBUG_INFO=y +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_X86_MMU=y +CONFIG_X86_VERY_EARLY_CONSOLE=y +CONFIG_QEMU_ICOUNT=n CONFIG_X86_KPTI=n diff --git a/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig b/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig index 01dd154ba5a..33cbf5de6b4 100644 --- a/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig +++ b/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig @@ -1,4 +1,16 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2019 Intel Corp. +CONFIG_PIC_DISABLE=y +CONFIG_LOAPIC=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_X86_MMU=y +CONFIG_DEBUG_INFO=y +CONFIG_SCHED_SCALABLE=y +CONFIG_WAITQ_SCALABLE=y +CONFIG_X86_VERY_EARLY_CONSOLE=y CONFIG_X86_KPTI=n diff --git a/boards/qemu/x86/qemu_x86_atom_nommu_defconfig b/boards/qemu/x86/qemu_x86_atom_nommu_defconfig index 32dbada07b4..119a6dd2c39 100644 --- a/boards/qemu/x86/qemu_x86_atom_nommu_defconfig +++ b/boards/qemu/x86/qemu_x86_atom_nommu_defconfig @@ -1,7 +1,15 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2019 Intel Corp. +CONFIG_PIC_DISABLE=y +CONFIG_LOAPIC=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 +CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_X86_MMU=n +CONFIG_DEBUG_INFO=y CONFIG_SCHED_DUMB=y CONFIG_WAITQ_DUMB=y CONFIG_X86_VERY_EARLY_CONSOLE=n diff --git a/boards/qemu/x86/qemu_x86_atom_nopae_defconfig b/boards/qemu/x86/qemu_x86_atom_nopae_defconfig index 36ec7d7d8e5..bccb2e2771e 100644 --- a/boards/qemu/x86/qemu_x86_atom_nopae_defconfig +++ b/boards/qemu/x86/qemu_x86_atom_nopae_defconfig @@ -1,4 +1,16 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2019 Intel Corp. +CONFIG_PIC_DISABLE=y +CONFIG_LOAPIC=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_X86_MMU=y +CONFIG_DEBUG_INFO=y +CONFIG_SCHED_SCALABLE=y +CONFIG_WAITQ_SCALABLE=y +CONFIG_X86_VERY_EARLY_CONSOLE=y CONFIG_X86_PAE=n diff --git a/boards/qemu/x86/qemu_x86_atom_virt_defconfig b/boards/qemu/x86/qemu_x86_atom_virt_defconfig index 6c1679d7728..c06824e6004 100644 --- a/boards/qemu/x86/qemu_x86_atom_virt_defconfig +++ b/boards/qemu/x86/qemu_x86_atom_virt_defconfig @@ -1,6 +1,18 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2019 Intel Corp. +CONFIG_PIC_DISABLE=y +CONFIG_LOAPIC=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_X86_MMU=y +CONFIG_DEBUG_INFO=y +CONFIG_SCHED_SCALABLE=y +CONFIG_WAITQ_SCALABLE=y +CONFIG_X86_VERY_EARLY_CONSOLE=y CONFIG_SRAM_OFFSET=0x100000 CONFIG_KERNEL_VM_SIZE=0x400000 CONFIG_KERNEL_VM_BASE=0x40000000 diff --git a/boards/qemu/x86/qemu_x86_atom_xip_defconfig b/boards/qemu/x86/qemu_x86_atom_xip_defconfig index c186d568275..230d6ea36d2 100644 --- a/boards/qemu/x86/qemu_x86_atom_xip_defconfig +++ b/boards/qemu/x86/qemu_x86_atom_xip_defconfig @@ -1,5 +1,16 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2019 Intel Corp. +CONFIG_PIC_DISABLE=y +CONFIG_LOAPIC=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 +CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_X86_MMU=n +CONFIG_DEBUG_INFO=y +CONFIG_SCHED_SCALABLE=y +CONFIG_WAITQ_SCALABLE=y +CONFIG_X86_VERY_EARLY_CONSOLE=y CONFIG_XIP=y diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_defconfig b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_defconfig deleted file mode 100644 index 9881313609a..00000000000 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_defconfig +++ /dev/null @@ -1 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_defconfig b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_defconfig deleted file mode 100644 index 9881313609a..00000000000 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_defconfig +++ /dev/null @@ -1 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig index ff4b012b93c..027dd93e73b 100644 --- a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig +++ b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig @@ -1,4 +1,29 @@ # SPDX-License-Identifier: Apache-2.0 +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y + +# Logger cannot use itself to log +CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y + +# Enable USB +CONFIG_USB_DEVICE_STACK=y + +# Build UF2 by default, supported by the Adafruit nRF52 Bootloader +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_USE_DT_CODE_PARTITION=y + # Required to enable LSM6DS3TR-C power CONFIG_REGULATOR=y diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig index 5ce90449df8..42963436cbc 100644 --- a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig +++ b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig @@ -1,6 +1,17 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2017 Synopsys +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y CONFIG_ARC_HAS_SECURE=y CONFIG_TRUSTED_EXECUTION_SECURE=y CONFIG_INIT_ARCH_HW_AT_BOOT=y diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_defconfig b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_defconfig index 6685d5f940d..d9fa27c036b 100644 --- a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_defconfig +++ b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_defconfig @@ -1,4 +1,15 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2017 Synopsys +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em9d_defconfig b/boards/snps/em_starterkit/em_starterkit_emsk_em9d_defconfig new file mode 100644 index 00000000000..38979ec4912 --- /dev/null +++ b/boards/snps/em_starterkit/em_starterkit_emsk_em9d_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y diff --git a/boards/snps/emsdp/emsdp_emsdp_em11d_defconfig b/boards/snps/emsdp/emsdp_emsdp_em11d_defconfig index ac2ac3efaaa..666e1cb41fb 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em11d_defconfig +++ b/boards/snps/emsdp/emsdp_emsdp_em11d_defconfig @@ -1,4 +1,16 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_GPIO=y CONFIG_SPI=y CONFIG_PINCTRL=y diff --git a/boards/snps/emsdp/emsdp_emsdp_em5d_defconfig b/boards/snps/emsdp/emsdp_emsdp_em5d_defconfig index e3abf3f96b6..03f84b13a64 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em5d_defconfig +++ b/boards/snps/emsdp/emsdp_emsdp_em5d_defconfig @@ -1,3 +1,15 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_GPIO=y CONFIG_SPI=y diff --git a/boards/snps/emsdp/emsdp_emsdp_em6_defconfig b/boards/snps/emsdp/emsdp_emsdp_em6_defconfig index e3abf3f96b6..03f84b13a64 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em6_defconfig +++ b/boards/snps/emsdp/emsdp_emsdp_em6_defconfig @@ -1,3 +1,15 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_GPIO=y CONFIG_SPI=y diff --git a/boards/snps/emsdp/emsdp_emsdp_em7d_defconfig b/boards/snps/emsdp/emsdp_emsdp_em7d_defconfig new file mode 100644 index 00000000000..d8581e40fab --- /dev/null +++ b/boards/snps/emsdp/emsdp_emsdp_em7d_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_GPIO=y diff --git a/boards/snps/emsdp/emsdp_emsdp_em7d_esp_defconfig b/boards/snps/emsdp/emsdp_emsdp_em7d_esp_defconfig index a0da795360a..d6de8dababf 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em7d_esp_defconfig +++ b/boards/snps/emsdp/emsdp_emsdp_em7d_esp_defconfig @@ -1,5 +1,17 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_GPIO=y CONFIG_ARC_HAS_SECURE=y CONFIG_TRUSTED_EXECUTION_SECURE=y CONFIG_SPI=y diff --git a/boards/snps/emsdp/emsdp_emsdp_em9d_defconfig b/boards/snps/emsdp/emsdp_emsdp_em9d_defconfig index e3abf3f96b6..03f84b13a64 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em9d_defconfig +++ b/boards/snps/emsdp/emsdp_emsdp_em9d_defconfig @@ -1,3 +1,15 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_GPIO=y CONFIG_SPI=y diff --git a/boards/snps/hsdk/hsdk_arc_hsdk_2cores_defconfig b/boards/snps/hsdk/hsdk_arc_hsdk_2cores_defconfig index af283689b38..711d759a8fd 100644 --- a/boards/snps/hsdk/hsdk_arc_hsdk_2cores_defconfig +++ b/boards/snps/hsdk/hsdk_arc_hsdk_2cores_defconfig @@ -1,3 +1,15 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_GPIO=y CONFIG_MP_MAX_NUM_CPUS=2 diff --git a/boards/snps/nsim/nsim_nsim_hs5x_smp_12cores_defconfig b/boards/snps/nsim/nsim_nsim_hs5x_smp_12cores_defconfig index cea98ef287a..6f80ab66cfb 100644 --- a/boards/snps/nsim/nsim_nsim_hs5x_smp_12cores_defconfig +++ b/boards/snps/nsim/nsim_nsim_hs5x_smp_12cores_defconfig @@ -1,3 +1,11 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_ISA_ARCV3=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y CONFIG_MP_MAX_NUM_CPUS=12 diff --git a/boards/snps/nsim/nsim_nsim_hs5x_smp_defconfig b/boards/snps/nsim/nsim_nsim_hs5x_smp_defconfig index 112ba7f1bd0..c55df123e9f 100644 --- a/boards/snps/nsim/nsim_nsim_hs5x_smp_defconfig +++ b/boards/snps/nsim/nsim_nsim_hs5x_smp_defconfig @@ -1,5 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_ISA_ARCV3=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=2 CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/snps/nsim/nsim_nsim_hs6x_smp_12cores_defconfig b/boards/snps/nsim/nsim_nsim_hs6x_smp_12cores_defconfig index cea98ef287a..6f80ab66cfb 100644 --- a/boards/snps/nsim/nsim_nsim_hs6x_smp_12cores_defconfig +++ b/boards/snps/nsim/nsim_nsim_hs6x_smp_12cores_defconfig @@ -1,3 +1,11 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_ISA_ARCV3=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y CONFIG_MP_MAX_NUM_CPUS=12 diff --git a/boards/snps/nsim/nsim_nsim_hs6x_smp_defconfig b/boards/snps/nsim/nsim_nsim_hs6x_smp_defconfig index 112ba7f1bd0..c55df123e9f 100644 --- a/boards/snps/nsim/nsim_nsim_hs6x_smp_defconfig +++ b/boards/snps/nsim/nsim_nsim_hs6x_smp_defconfig @@ -1,5 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_ISA_ARCV3=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=2 CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/snps/nsim/nsim_nsim_hs_flash_xip_defconfig b/boards/snps/nsim/nsim_nsim_hs_flash_xip_defconfig index 4c4786d7291..598d6250e35 100644 --- a/boards/snps/nsim/nsim_nsim_hs_flash_xip_defconfig +++ b/boards/snps/nsim/nsim_nsim_hs_flash_xip_defconfig @@ -1,4 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_MPU_ENABLE=y CONFIG_XIP=y CONFIG_HARVARD=n diff --git a/boards/snps/nsim/nsim_nsim_hs_smp_defconfig b/boards/snps/nsim/nsim_nsim_hs_smp_defconfig index f6818014718..351a2b9660b 100644 --- a/boards/snps/nsim/nsim_nsim_hs_smp_defconfig +++ b/boards/snps/nsim/nsim_nsim_hs_smp_defconfig @@ -1,5 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y CONFIG_ARC_MPU_ENABLE=n CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=2 diff --git a/boards/snps/nsim/nsim_nsim_hs_sram_defconfig b/boards/snps/nsim/nsim_nsim_hs_sram_defconfig index fec69adbb50..1ee8bc1dad0 100644 --- a/boards/snps/nsim/nsim_nsim_hs_sram_defconfig +++ b/boards/snps/nsim/nsim_nsim_hs_sram_defconfig @@ -1,3 +1,11 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_MPU_ENABLE=y CONFIG_HARVARD=n diff --git a/boards/snps/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig b/boards/snps/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig index 8fe546e4302..1162d5f132b 100644 --- a/boards/snps/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig +++ b/boards/snps/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig @@ -1,3 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_TRUSTED_EXECUTION_SECURE=y CONFIG_ARC_HAS_STACK_CHECKING=n From 4e3a01df418bbee1c2d9c4c14845b277a002deea Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Fri, 5 Apr 2024 15:39:37 +0200 Subject: [PATCH 2065/2402] cmake: support shortened file names for single SoC boards This allow developers to create board files without the SoC name when the board only defines a single SoC. This means that a board, such as rpi_pico, which defines only a single SoC, rp2040, and one variant, now allows the following file names: Board target: rpi_pico/rp2040 - dts: rpi_pico_rp2040.dts, short: rpi_pico.dts - defconfig: rpi_pico_rp2040_defconfig, short: rpi_pico_defconfig - overlay: rpi_pico_rp2040.overlay, short: rpi_pico.overlay - conf: rpi_pico_rp2040.conf, short: rpi_pico.conf Board target: rpi_pico/rp2040/w - dts: rpi_pico_rp2040_w.dts, short: rpi_pico_w.dts - defconfig: rpi_pico_rp2040_w_defconfig, short: rpi_pico_w_defconfig - overlay: rpi_pico_rp2040_w.overlay, short: rpi_pico_w.overlay - conf: rpi_pico_rp2040_w.conf, short: rpi_pico_w.conf A multi CPU cluster board, nrf5340dk: Board target: nrf5340dk/nrf5340/cpunet - dts: nrf5340dk_nrf5340_cpunet.dts, short: nrf5340dk_cpunet.dts - defconfig: nrf5340dk_nrf5340_cpunet_defconfig, short: nrf5340dk_cpunet_defconfig - overlay: nrf5340dk_nrf5340_cpunet.overlay, short: nrf5340dk_cpunet.overlay - conf: nrf5340dk_nrf5340_cpunet.conf, short: nrf5340dk_cpunet.conf A multi SoC board, nrf5340dk (real: nrf52840, emulated: nrf52811): Board target: nrf52840dk/nrf52840 - dts: nrf52840dk_nrf52840.dts, short: Not possible - defconfig: nrf52840dk_nrf52840_defconfig, short: Not possible - overlay: nrf52840dk_nrf52840.overlay, short: Not possible - conf: nrf52840dk_nrf52840.conf, short: Not possible If two conflicting files are found, for example both rpi_pico_rp2040.overlay and rpi_pico.overlay, then an error is raised. If short form is detected for a board target with multiple SoCs, for example nrf52840dk_nrf52840.overlay and nrf52840dk.overlay, then an error is raised. Signed-off-by: Torsten Rasmussen --- cmake/modules/boards.cmake | 12 +- cmake/modules/configuration_files.cmake | 17 ++- cmake/modules/dts.cmake | 24 +++- cmake/modules/extensions.cmake | 170 ++++++++++++++++++------ 4 files changed, 163 insertions(+), 60 deletions(-) diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index f76d89a8427..cb07262f150 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -297,10 +297,14 @@ elseif(HWMv2) if(LIST_BOARD_QUALIFIERS) # Allow users to omit the SoC when building for a board with a single SoC. list(LENGTH LIST_BOARD_SOCS socs_length) - if(NOT DEFINED BOARD_QUALIFIERS AND socs_length EQUAL 1) - set(BOARD_QUALIFIERS "/${LIST_BOARD_SOCS}") - elseif("${BOARD_QUALIFIERS}" MATCHES "^//.*" AND socs_length EQUAL 1) - string(REGEX REPLACE "^//" "/${LIST_BOARD_SOCS}/" BOARD_QUALIFIERS "${BOARD_QUALIFIERS}") + if(socs_length EQUAL 1) + set(BOARD_SINGLE_SOC TRUE) + set(BOARD_${BOARD}_SINGLE_SOC TRUE) + if(NOT DEFINED BOARD_QUALIFIERS) + set(BOARD_QUALIFIERS "/${LIST_BOARD_SOCS}") + elseif("${BOARD_QUALIFIERS}" MATCHES "^//.*") + string(REGEX REPLACE "^//" "/${LIST_BOARD_SOCS}/" BOARD_QUALIFIERS "${BOARD_QUALIFIERS}") + endif() endif() set(board_targets ${LIST_BOARD_QUALIFIERS}) diff --git a/cmake/modules/configuration_files.cmake b/cmake/modules/configuration_files.cmake index 708f0a3c98f..78e7bf2a494 100644 --- a/cmake/modules/configuration_files.cmake +++ b/cmake/modules/configuration_files.cmake @@ -83,15 +83,14 @@ endif() # If still not found, search for other overlays in the configuration directory. if(NOT DEFINED DTC_OVERLAY_FILE) - zephyr_build_string(board_overlay_strings - BOARD ${BOARD} - BOARD_QUALIFIERS ${BOARD_QUALIFIERS} - MERGE - ) - list(TRANSFORM board_overlay_strings APPEND ".overlay") - - zephyr_file(CONF_FILES ${APPLICATION_CONFIG_DIR} DTS DTC_OVERLAY_FILE - NAMES "${board_overlay_strings};app.overlay" SUFFIX ${FILE_SUFFIX}) + zephyr_file(CONF_FILES ${APPLICATION_CONFIG_DIR} DTS DTC_OVERLAY_FILE) + + if(NOT DEFINED DTC_OVERLAY_FILE) + zephyr_file(CONF_FILES ${APPLICATION_CONFIG_DIR} DTS DTC_OVERLAY_FILE + NAMES "app.overlay" SUFFIX ${FILE_SUFFIX} + ) + endif() + endif() set(DTC_OVERLAY_FILE ${DTC_OVERLAY_FILE} CACHE STRING "If desired, you can \ diff --git a/cmake/modules/dts.cmake b/cmake/modules/dts.cmake index 294471b4ad0..d1ff4df9bcd 100644 --- a/cmake/modules/dts.cmake +++ b/cmake/modules/dts.cmake @@ -123,13 +123,23 @@ set(DTS_CMAKE ${PROJECT_BINARY_DIR}/dts.cmake) set(VENDOR_PREFIXES dts/bindings/vendor-prefixes.txt) if(NOT DEFINED DTS_SOURCE) - zephyr_build_string(dts_board_string BOARD ${BOARD} BOARD_QUALIFIERS ${BOARD_QUALIFIERS} MERGE) - foreach(str ${dts_board_string}) - if(EXISTS ${BOARD_DIR}/${str}.dts) - set(DTS_SOURCE ${BOARD_DIR}/${str}.dts) - break() - endif() - endforeach() + zephyr_build_string(board_string SHORT shortened_board_string + BOARD ${BOARD} BOARD_QUALIFIERS ${BOARD_QUALIFIERS} + ) + if(EXISTS ${BOARD_DIR}/${shortened_board_string}.dts AND NOT BOARD_${BOARD}_SINGLE_SOC) + message(FATAL_ERROR "Board ${ZFILE_BOARD} defines multiple SoCs.\nShortened file name " + "(${shortened_board_string}.dts) not allowed, use '_.dts' naming" + ) + elseif(EXISTS ${BOARD_DIR}/${board_string}.dts AND EXISTS ${BOARD_DIR}/${shortened_board_string}.dts) + message(FATAL_ERROR "Conflicting file names discovered. Cannot use both " + "${board_string}.dts and ${shortened_board_string}.dts. " + "Please choose one naming style, ${board_string}.dts is recommended." + ) + elseif(EXISTS ${BOARD_DIR}/${board_string}.dts) + set(DTS_SOURCE ${BOARD_DIR}/${board_string}.dts) + elseif(EXISTS ${BOARD_DIR}/${shortened_board_string}.dts) + set(DTS_SOURCE ${BOARD_DIR}/${shortened_board_string}.dts) + endif() endif() if(EXISTS ${DTS_SOURCE}) diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index 909887e6393..4c989e808ae 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -1519,7 +1519,8 @@ endfunction() # build string as first item in the list. # The full order of build strings returned in the list will be: # - Normalized board target build string, this includes qualifiers and revision -# - Normalized board target build string, without revision +# - Build string with board variants removed in addition +# - Build string with cpuset removed in addition # - Build string with soc removed in addition # # If BUILD is supplied, then build type will be appended to each entry in the @@ -1538,6 +1539,7 @@ endfunction() # ) # # : Output variable where the build string will be returned. +# SHORT : Output variable where the shortened build string will be returned. # BOARD : Board name to use when creating the build string. # BOARD_REVISION : Board revision to use when creating the build string. # BUILD : Build type to use when creating the build string. @@ -1560,11 +1562,17 @@ endfunction() # calling # zephyr_build_string(build_string BOARD alpha BOARD_REVISION 1.0.0 BOARD_QUALIFIERS /soc/bar MERGE) # will return a list of the following strings -# `alpha_soc_bar_1_0_0;alpha_soc_bar;alpha_bar` in `build_string` parameter. +# `alpha_soc_bar_1_0_0;alpha_soc_bar` in `build_string` parameter. +# +# calling +# zephyr_build_string(build_string SHORTENED short_build_string BOARD alpha BOARD_REVISION 1.0.0 BOARD_QUALIFIERS /soc/bar MERGE) +# will return two lists of the following strings +# `alpha_soc_bar_1_0_0;alpha_soc_bar` in `build_string` parameter. +# `alpha_bar_1_0_0;alpha_bar` in `short_build_string` parameter. # function(zephyr_build_string outvar) set(options MERGE REVERSE) - set(single_args BOARD BOARD_QUALIFIERS BOARD_REVISION BUILD) + set(single_args BOARD BOARD_QUALIFIERS BOARD_REVISION BUILD SHORT) cmake_parse_arguments(BUILD_STR "${options}" "${single_args}" "" ${ARGN}) if(BUILD_STR_UNPARSED_ARGUMENTS) @@ -1588,28 +1596,44 @@ function(zephyr_build_string outvar) ) endif() - string(REPLACE "/" ";" str_segment_list "${BUILD_STR_BOARD}${BUILD_STR_BOARD_QUALIFIERS}") + string(REPLACE "/" ";" str_segment_list "${BUILD_STR_BOARD_QUALIFIERS}") string(REPLACE "." "_" revision_string "${BUILD_STR_BOARD_REVISION}") - string(JOIN "_" ${outvar} ${str_segment_list} ${revision_string} ${BUILD_STR_BUILD}) + string(JOIN "_" ${outvar} ${BUILD_STR_BOARD} ${str_segment_list} ${revision_string} ${BUILD_STR_BUILD}) if(BUILD_STR_MERGE) - string(JOIN "_" variant_string ${str_segment_list} ${BUILD_STR_BUILD}) + string(JOIN "_" variant_string ${BUILD_STR_BOARD} ${str_segment_list} ${BUILD_STR_BUILD}) if(NOT "${variant_string}" IN_LIST ${outvar}) list(APPEND ${outvar} "${variant_string}") endif() - - if(BUILD_STR_BOARD_QUALIFIERS) - string(REGEX REPLACE "^/[^/]*(.*)" "\\1" qualifiers_without_soc "${BUILD_STR_BOARD_QUALIFIERS}") - string(REPLACE "/" "_" qualifiers_without_soc "${qualifiers_without_soc}") - list(APPEND ${outvar} "${BUILD_STR_BOARD}${qualifiers_without_soc}") - endif() endif() if(BUILD_STR_REVERSE) list(REVERSE ${outvar}) endif() + list(REMOVE_DUPLICATES ${outvar}) + + if(BUILD_STR_SHORT AND BUILD_STR_BOARD_QUALIFIERS) + string(REGEX REPLACE "^/[^/]*(.*)" "\\1" shortened_qualifiers "${BOARD_QUALIFIERS}") + string(REPLACE "/" ";" str_short_segment_list "${shortened_qualifiers}") + string(JOIN "_" ${BUILD_STR_SHORT} + ${BUILD_STR_BOARD} ${str_short_segment_list} ${revision_string} ${BUILD_STR_BUILD} + ) + if(BUILD_STR_MERGE) + string(JOIN "_" variant_string ${BUILD_STR_BOARD} ${str_short_segment_list} ${BUILD_STR_BUILD}) + + if(NOT "${variant_string}" IN_LIST ${BUILD_STR_SHORT}) + list(APPEND ${BUILD_STR_SHORT} "${variant_string}") + endif() + endif() + + if(BUILD_STR_REVERSE) + list(REVERSE ${BUILD_STR_SHORT}) + endif() + list(REMOVE_DUPLICATES ${BUILD_STR_SHORT}) + set(${BUILD_STR_SHORT} ${${BUILD_STR_SHORT}} PARENT_SCOPE) + endif() # This updates the provided outvar in parent scope (callers scope) set(${outvar} ${${outvar}} PARENT_SCOPE) @@ -2522,7 +2546,6 @@ endfunction() # creating file names based on board settings. # Only the first match found in will be # returned in the -# # DTS : List to append DTS overlay files in to # KCONF : List to append Kconfig fragment files in to # DEFCONF : List to append _defconfig files in to @@ -2618,32 +2641,44 @@ Relative paths are only allowed with `-D${ARGV1}=`") set(kconf_filename_list ${ZFILE_NAMES}) else() zephyr_build_string(filename_list + SHORT shortened_filename_list BOARD ${ZFILE_BOARD} BOARD_REVISION ${ZFILE_BOARD_REVISION} BOARD_QUALIFIERS ${ZFILE_BOARD_QUALIFIERS} BUILD ${ZFILE_BUILD} MERGE REVERSE ) - list(REMOVE_DUPLICATES filename_list) + set(dts_filename_list ${filename_list}) + set(dts_shortened_filename_list ${shortened_filename_list}) list(TRANSFORM dts_filename_list APPEND ".overlay") + list(TRANSFORM dts_shortened_filename_list APPEND ".overlay") set(kconf_filename_list ${filename_list}) + set(kconf_shortened_filename_list ${shortened_filename_list}) list(TRANSFORM kconf_filename_list APPEND ".conf") + list(TRANSFORM kconf_shortened_filename_list APPEND ".conf") endif() if(ZFILE_DTS) foreach(path ${ZFILE_CONF_FILES}) - foreach(filename ${dts_filename_list}) - if(NOT IS_ABSOLUTE ${filename}) - set(test_file ${path}/${filename}) - else() - set(test_file ${filename}) - endif() - zephyr_file_suffix(test_file SUFFIX ${ZFILE_SUFFIX}) + foreach(filename IN ZIP_LISTS dts_filename_list dts_shortened_filename_list) + foreach(i RANGE 1) + if(NOT IS_ABSOLUTE filename_${i} AND DEFINED filename_${i}) + set(test_file_${i} ${path}/${filename_${i}}) + else() + set(test_file_${i} ${filename_${i}}) + endif() + zephyr_file_suffix(test_file_${i} SUFFIX ${ZFILE_SUFFIX}) - if(EXISTS ${test_file}) - list(APPEND ${ZFILE_DTS} ${test_file}) + if(NOT EXISTS ${test_file_${i}}) + set(test_file_${i}) + endif() + endforeach() + + if(test_file_0 OR test_file_1) + list(APPEND found_dts_files ${test_file_0}) + list(APPEND found_dts_files ${test_file_1}) if(DEFINED ZFILE_BUILD) set(deprecated_file_found y) @@ -2653,29 +2688,48 @@ Relative paths are only allowed with `-D${ARGV1}=`") break() endif() endif() + + if(test_file_1 AND NOT BOARD_${ZFILE_BOARD}_SINGLE_SOC) + message(FATAL_ERROR "Board ${ZFILE_BOARD} defines multiple SoCs.\nShortened file name " + "(${filename_1}) not allowed, use '_.overlay' naming" + ) + endif() + + if(test_file_0 AND test_file_1) + message(FATAL_ERROR "Conflicting file names discovered. Cannot use both ${filename_0} " + "and ${filename_1}. Please choose one naming style, " + "${filename_0} is recommended." + ) + endif() endforeach() endforeach() + list(APPEND ${ZFILE_DTS} ${found_dts_files}) + # This updates the provided list in parent scope (callers scope) set(${ZFILE_DTS} ${${ZFILE_DTS}} PARENT_SCOPE) - - if(NOT ${ZFILE_DTS}) - set(not_found ${dts_filename_list}) - endif() endif() if(ZFILE_KCONF) + set(found_conf_files) foreach(path ${ZFILE_CONF_FILES}) - foreach(filename ${kconf_filename_list}) - if(NOT IS_ABSOLUTE ${filename}) - set(test_file ${path}/${filename}) - else() - set(test_file ${filename}) - endif() - zephyr_file_suffix(test_file SUFFIX ${ZFILE_SUFFIX}) + foreach(filename IN ZIP_LISTS kconf_filename_list kconf_shortened_filename_list) + foreach(i RANGE 1) + if(NOT IS_ABSOLUTE filename_${i} AND DEFINED filename_${i}) + set(test_file_${i} ${path}/${filename_${i}}) + else() + set(test_file_${i} ${filename_${i}}) + endif() + zephyr_file_suffix(test_file_${i} SUFFIX ${ZFILE_SUFFIX}) + + if(NOT EXISTS ${test_file_${i}}) + set(test_file_${i}) + endif() + endforeach() - if(EXISTS ${test_file}) - list(APPEND ${ZFILE_KCONF} ${test_file}) + if(test_file_0 OR test_file_1) + list(APPEND found_conf_files ${test_file_0}) + list(APPEND found_conf_files ${test_file_1}) if(DEFINED ZFILE_BUILD) set(deprecated_file_found y) @@ -2685,9 +2739,24 @@ Relative paths are only allowed with `-D${ARGV1}=`") break() endif() endif() + + if(test_file_1 AND NOT BOARD_${ZFILE_BOARD}_SINGLE_SOC) + message(FATAL_ERROR "Board ${ZFILE_BOARD} defines multiple SoCs.\nShortened file name " + "(${filename_1}) not allowed, use '_.conf' naming" + ) + endif() + + if(test_file_0 AND test_file_1) + message(FATAL_ERROR "Conflicting file names discovered. Cannot use both ${filename_0} " + "and ${filename_1}. Please choose one naming style, " + "${filename_0} is recommended." + ) + endif() endforeach() endforeach() + list(APPEND ${ZFILE_KCONF} ${found_conf_files}) + # This updates the provided list in parent scope (callers scope) set(${ZFILE_KCONF} ${${ZFILE_KCONF}} PARENT_SCOPE) @@ -2709,13 +2778,34 @@ Relative paths are only allowed with `-D${ARGV1}=`") endif() if(ZFILE_DEFCONFIG) + set(found_defconf_files) foreach(path ${ZFILE_CONF_FILES}) - foreach(filename ${filename_list}) - if(EXISTS ${path}/${filename}_defconfig) - list(APPEND ${ZFILE_DEFCONFIG} ${path}/${filename}_defconfig) + foreach(filename IN ZIP_LISTS filename_list shortened_filename_list) + foreach(i RANGE 1) + set(test_file_${i} ${path}/${filename_${i}}_defconfig) + + if(EXISTS ${test_file_${i}}) + list(APPEND found_defconf_files ${test_file_${i}}) + else() + set(test_file_${i}) + endif() + endforeach() + + if(test_file_1 AND NOT BOARD_${ZFILE_BOARD}_SINGLE_SOC) + message(FATAL_ERROR "Board ${ZFILE_BOARD} defines multiple SoCs.\nShortened file name " + "(${filename_1}_defconfig) not allowed, use '__defconfig' naming" + ) + endif() + + if(test_file_0 AND test_file_1) + message(FATAL_ERROR "Conflicting file names discovered. Cannot use both " + "${filename_0}_defconfig and ${filename_1}_defconfig. Please choose one " + "naming style, ${filename_0}_defconfig is recommended." + ) endif() endforeach() endforeach() + list(APPEND ${ZFILE_DEFCONFIG} ${found_defconf_files}) # This updates the provided list in parent scope (callers scope) set(${ZFILE_DEFCONFIG} ${${ZFILE_DEFCONFIG}} PARENT_SCOPE) @@ -4377,7 +4467,7 @@ function(zephyr_linker_dts_section) if(DTS_SECTION_UNPARSED_ARGUMENTS) message(FATAL_ERROR "zephyr_linker_dts_section(${ARGV0} ...) given unknown " - "arguments: ${DTS_SECTION_UNPARSED_ARGUMENTS}" + "arguments: ${DTS_SECTION_UNPARSED_ARGUMENTS}" ) endif() From abca9170553c69603625087bfbd4df1ceff6124b Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Fri, 5 Apr 2024 18:49:47 +0200 Subject: [PATCH 2066/2402] boards: board dts and defconfig file adjustments Adjustments of dts and defconfig files to adjust for the MERGE removal. The revert of MERGE requires specific dts and defconfig files for boards which relied on the MERGE feature. Signed-off-by: Torsten Rasmussen --- boards/arm/mps2/mps2_an521_cpu0_ns_defconfig | 12 +++++++++++- ...s25_tgph.dts => intel_adsp_cavs25_tgph.dts} | 0 .../adsp/intel_adsp_cavs25_tgph_defconfig | 1 - boards/native/native_posix/native_posix_64.dts | 7 +++++++ .../native_posix/native_posix_64_defconfig | 4 ++++ boards/native/native_sim/native_sim_64.dts | 7 +++++++ .../native/native_sim/native_sim_64_defconfig | 4 ++++ .../nrf54h20dk_nrf54h20_cpuppr_xip.dts | 7 +++++++ .../lpcxpresso55s69/lpcxpresso55s69_defconfig | 12 ------------ ...t1170.dts => vmu_rt1170_mimxrt1176_cm7.dts} | 0 ...fig => vmu_rt1170_mimxrt1176_cm7_defconfig} | 0 ...rv32m1_vega_openisa_rv32m1_ri5cy_defconfig} | 0 ...m1_vega_openisa_rv32m1_zero_riscy_defconfig | 10 ++++++++++ .../qemu_riscv32_qemu_virt_riscv32_smp.dts | 17 +++++++++++++++++ .../qemu_riscv64_qemu_virt_riscv64_smp.dts | 18 ++++++++++++++++++ .../longan_nano_gd32vf103_lite_defconfig | 15 +++++++++++++++ .../snps/em_starterkit/em_starterkit_defconfig | 14 -------------- .../nsim_nsim_hs_hostlink_defconfig} | 4 ---- .../lvgl/demos/boards/native_posix_64.overlay | 11 +++++++++++ 19 files changed, 111 insertions(+), 32 deletions(-) rename boards/intel/adsp/{intel_adsp_cavs25_cavs25_tgph.dts => intel_adsp_cavs25_tgph.dts} (100%) create mode 100644 boards/native/native_posix/native_posix_64.dts create mode 100644 boards/native/native_posix/native_posix_64_defconfig create mode 100644 boards/native/native_sim/native_sim_64.dts create mode 100644 boards/native/native_sim/native_sim_64_defconfig create mode 100644 boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip.dts delete mode 100644 boards/nxp/lpcxpresso55s69/lpcxpresso55s69_defconfig rename boards/nxp/vmu_rt1170/{vmu_rt1170.dts => vmu_rt1170_mimxrt1176_cm7.dts} (100%) rename boards/nxp/vmu_rt1170/{vmu_rt1170_defconfig => vmu_rt1170_mimxrt1176_cm7_defconfig} (100%) rename boards/openisa/rv32m1_vega/{rv32m1_vega_openisa_rv32m1_defconfig => rv32m1_vega_openisa_rv32m1_ri5cy_defconfig} (100%) create mode 100644 boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy_defconfig create mode 100644 boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.dts create mode 100644 boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts create mode 100644 boards/sipeed/longan_nano/longan_nano_gd32vf103_lite_defconfig delete mode 100644 boards/snps/em_starterkit/em_starterkit_defconfig rename boards/snps/{emsdp/emsdp_defconfig => nsim/nsim_nsim_hs_hostlink_defconfig} (73%) create mode 100644 samples/modules/lvgl/demos/boards/native_posix_64.overlay diff --git a/boards/arm/mps2/mps2_an521_cpu0_ns_defconfig b/boards/arm/mps2/mps2_an521_cpu0_ns_defconfig index 7c02187aaef..bbcafede67a 100644 --- a/boards/arm/mps2/mps2_an521_cpu0_ns_defconfig +++ b/boards/arm/mps2/mps2_an521_cpu0_ns_defconfig @@ -4,8 +4,18 @@ # SPDX-License-Identifier: Apache-2.0 # +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y CONFIG_QEMU_ICOUNT_SHIFT=6 +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + # Build a non-secure firmware image -CONFIG_TRUSTED_EXECUTION_SECURE=n CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/intel/adsp/intel_adsp_cavs25_cavs25_tgph.dts b/boards/intel/adsp/intel_adsp_cavs25_tgph.dts similarity index 100% rename from boards/intel/adsp/intel_adsp_cavs25_cavs25_tgph.dts rename to boards/intel/adsp/intel_adsp_cavs25_tgph.dts diff --git a/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig index 041043937bf..7e79840a033 100644 --- a/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig +++ b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig @@ -17,7 +17,6 @@ CONFIG_2ND_LEVEL_INTERRUPTS=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_CORE_COUNT=2 CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/native/native_posix/native_posix_64.dts b/boards/native/native_posix/native_posix_64.dts new file mode 100644 index 00000000000..74a3c30049b --- /dev/null +++ b/boards/native/native_posix/native_posix_64.dts @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../native_sim/native_sim.dts" diff --git a/boards/native/native_posix/native_posix_64_defconfig b/boards/native/native_posix/native_posix_64_defconfig new file mode 100644 index 00000000000..b0033eda61f --- /dev/null +++ b/boards/native/native_posix/native_posix_64_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/native/native_sim/native_sim_64.dts b/boards/native/native_sim/native_sim_64.dts new file mode 100644 index 00000000000..4ac77d414f9 --- /dev/null +++ b/boards/native/native_sim/native_sim_64.dts @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "native_sim.dts" diff --git a/boards/native/native_sim/native_sim_64_defconfig b/boards/native/native_sim/native_sim_64_defconfig new file mode 100644 index 00000000000..b0033eda61f --- /dev/null +++ b/boards/native/native_sim/native_sim_64_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip.dts new file mode 100644 index 00000000000..020f5bf8e1f --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip.dts @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf54h20dk_nrf54h20_cpuppr.dts" diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_defconfig deleted file mode 100644 index 32700cd4833..00000000000 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2024 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# -# Common Kconfigs for all board targets -# - -CONFIG_GPIO=y -CONFIG_PINCTRL=y - -CONFIG_RUNTIME_NMI=y diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170.dts b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts similarity index 100% rename from boards/nxp/vmu_rt1170/vmu_rt1170.dts rename to boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_defconfig b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig similarity index 100% rename from boards/nxp/vmu_rt1170/vmu_rt1170_defconfig rename to boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_defconfig b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy_defconfig similarity index 100% rename from boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_defconfig rename to boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy_defconfig diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy_defconfig b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy_defconfig new file mode 100644 index 00000000000..908f07c0198 --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2018 Foundries.io Ltd + +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_MULTI_LEVEL_INTERRUPTS=y diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.dts b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.dts new file mode 100644 index 00000000000..6c820813021 --- /dev/null +++ b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.dts @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram0; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts new file mode 100644 index 00000000000..fb96f6d3d38 --- /dev/null +++ b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts @@ -0,0 +1,18 @@ +/* Copyright (c) 2019 BayLibre SAS */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram0; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite_defconfig b/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite_defconfig new file mode 100644 index 00000000000..353e533ef84 --- /dev/null +++ b/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite_defconfig @@ -0,0 +1,15 @@ +# Sipeed longan nano Development Board Configuration +# +# Copyright (c) 2021 Tokita, Hiroshi +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GD32_HXTAL_8MHZ=y + +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/snps/em_starterkit/em_starterkit_defconfig b/boards/snps/em_starterkit/em_starterkit_defconfig deleted file mode 100644 index 38979ec4912..00000000000 --- a/boards/snps/em_starterkit/em_starterkit_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2017 Synopsys - -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y diff --git a/boards/snps/emsdp/emsdp_defconfig b/boards/snps/nsim/nsim_nsim_hs_hostlink_defconfig similarity index 73% rename from boards/snps/emsdp/emsdp_defconfig rename to boards/snps/nsim/nsim_nsim_hs_hostlink_defconfig index d8581e40fab..123983e3241 100644 --- a/boards/snps/emsdp/emsdp_defconfig +++ b/boards/snps/nsim/nsim_nsim_hs_hostlink_defconfig @@ -1,14 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y diff --git a/samples/modules/lvgl/demos/boards/native_posix_64.overlay b/samples/modules/lvgl/demos/boards/native_posix_64.overlay new file mode 100644 index 00000000000..eab17f916bd --- /dev/null +++ b/samples/modules/lvgl/demos/boards/native_posix_64.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2023, Fabian Blatz + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&sdl_dc { + compatible = "zephyr,sdl-dc"; + height = <272>; + width = <480>; +}; From b9f3d68863b9f75dcc1dfac7dd7ff269b99cd118 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Fri, 5 Apr 2024 22:12:36 +0200 Subject: [PATCH 2067/2402] samples: tests: additional overlay and conf file adjustments Adjustments of overlay and conf files to adjust for the MERGE removal. The revert of MERGE requires specific overlay and conf files for boards which relied on the MERGE feature. Signed-off-by: Torsten Rasmussen --- ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ...m.conf => esp32_devkitc_wroom_procpu.conf} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ...m.conf => esp32_devkitc_wroom_procpu.conf} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ...ay => esp32_devkitc_wrover_procpu.overlay} | 0 .../adc/boards/mimxrt1160_evk_cm7.overlay | 34 ------------- ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ...ay => esp32_devkitc_wrover_procpu.overlay} | 0 ...rkit.conf => em_starterkit_emsk_em9d.conf} | 0 ...verlay => em_starterkit_emsk_em9d.overlay} | 0 .../{emsdp.conf => emsdp_emsdp_em11d.conf} | 0 ...m.conf => esp32_devkitc_wroom_procpu.conf} | 0 .../lvgl/demos/boards/native_sim_64.overlay | 6 +++ ...m.conf => esp32_devkitc_wroom_procpu.conf} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ....conf => esp32_devkitc_wrover_procpu.conf} | 0 ...ay => esp32_devkitc_wrover_procpu.overlay} | 0 .../fxos8700/boards/mimxrt1160_evk_cm4.conf | 2 - .../fxos8700/boards/mimxrt1160_evk_cm7.conf | 2 - ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ...ay => esp32_devkitc_wrover_procpu.overlay} | 0 .../openamp/boards/mimxrt1160_evk_cm7.conf | 2 - .../openamp/boards/mimxrt1160_evk_cm7.overlay | 24 --------- ..._an521.overlay => mps2_an521_cpu0.overlay} | 0 .../remote/boards/mimxrt1160_evk_cm4.overlay | 51 ------------------- ..._an521.overlay => mps2_an521_cpu0.overlay} | 0 ...m.conf => esp32_devkitc_wroom_procpu.conf} | 0 ...m.conf => esp32_devkitc_wroom_procpu.conf} | 0 ...m.conf => esp32_devkitc_wroom_procpu.conf} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ....conf => esp32_devkitc_wrover_procpu.conf} | 0 ...ay => esp32_devkitc_wrover_procpu.overlay} | 0 ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 .../adc_api/boards/native_posix_64.overlay | 7 +++ .../adc/adc_api/boards/native_sim_64.overlay | 7 +++ ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ...ay => esp32_devkitc_wrover_procpu.overlay} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ...ay => esp32_devkitc_wrover_procpu.overlay} | 0 .../boards/mimxrt1160_evk_cm4.conf | 3 -- .../boards/mimxrt1160_evk_cm4.overlay | 14 ----- .../boards/mimxrt1160_evk_cm7.conf | 3 -- .../boards/mimxrt1160_evk_cm7.overlay | 14 ----- .../boards/mimxrt1170_evk_cm4.conf | 4 -- .../boards/mimxrt1170_evk_cm4.overlay | 14 ----- ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 .../boards/mimxrt1160_evk_cm7.overlay | 7 --- .../boards/native_sim_64.overlay | 7 +++ .../boards/mimxrt1160_evk_cm4.conf | 3 -- .../boards/mimxrt1160_evk_cm4.overlay | 14 ----- .../boards/mimxrt1160_evk_cm7.conf | 3 -- .../boards/mimxrt1160_evk_cm7.overlay | 14 ----- .../boards/mimxrt1170_evk_cm4.conf | 3 -- .../boards/mimxrt1170_evk_cm4.overlay | 14 ----- ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ...verlay => em_starterkit_emsk_em9d.overlay} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ...ay => esp32_devkitc_wrover_procpu.overlay} | 0 ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ...verlay => em_starterkit_emsk_em9d.overlay} | 0 .../{emsdp.conf => emsdp_emsdp_em11d.conf} | 0 ...msdp.overlay => emsdp_emsdp_em11d.overlay} | 0 ...m.conf => esp32_devkitc_wroom_procpu.conf} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 .../boards/mimxrt1160_evk_cm4.overlay | 7 --- .../boards/mimxrt1160_evk_cm7.overlay | 13 ----- .../boards/mimxrt1170_evk_cm4.overlay | 7 --- ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ... => mimxrt685_evk_mimxrt685s_cm33.overlay} | 0 ...lay => esp32_devkitc_wroom_procpu.overlay} | 0 ...ay => esp32_devkitc_wrover_procpu.overlay} | 0 85 files changed, 27 insertions(+), 252 deletions(-) rename samples/basic/blinky_pwm/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename samples/basic/blinky_pwm/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename samples/bluetooth/hci_uart/boards/{esp32_devkitc_wroom.conf => esp32_devkitc_wroom_procpu.conf} (100%) rename samples/bluetooth/hci_uart/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename samples/boards/esp32/deep_sleep/boards/{esp32_devkitc_wroom.conf => esp32_devkitc_wroom_procpu.conf} (100%) rename samples/boards/esp32/flash_encryption/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename samples/drivers/adc/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename samples/drivers/adc/boards/{esp32_devkitc_wrover.overlay => esp32_devkitc_wrover_procpu.overlay} (100%) delete mode 100644 samples/drivers/adc/boards/mimxrt1160_evk_cm7.overlay rename samples/drivers/adc/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename samples/drivers/counter/alarm/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename samples/drivers/dac/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename samples/drivers/dac/boards/{esp32_devkitc_wrover.overlay => esp32_devkitc_wrover_procpu.overlay} (100%) rename samples/drivers/spi_flash/boards/{em_starterkit.conf => em_starterkit_emsk_em9d.conf} (100%) rename samples/drivers/spi_flash/boards/{em_starterkit.overlay => em_starterkit_emsk_em9d.overlay} (100%) rename samples/drivers/spi_flash/boards/{emsdp.conf => emsdp_emsdp_em11d.conf} (100%) rename samples/drivers/watchdog/boards/{esp32_devkitc_wroom.conf => esp32_devkitc_wroom_procpu.conf} (100%) create mode 100644 samples/modules/lvgl/demos/boards/native_sim_64.overlay rename samples/net/wifi/boards/{esp32_devkitc_wroom.conf => esp32_devkitc_wroom_procpu.conf} (100%) rename samples/net/wifi/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename samples/net/wifi/boards/{esp32_devkitc_wrover.conf => esp32_devkitc_wrover_procpu.conf} (100%) rename samples/net/wifi/boards/{esp32_devkitc_wrover.overlay => esp32_devkitc_wrover_procpu.overlay} (100%) delete mode 100644 samples/sensor/fxos8700/boards/mimxrt1160_evk_cm4.conf delete mode 100644 samples/sensor/fxos8700/boards/mimxrt1160_evk_cm7.conf rename samples/sensor/grow_r502a/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename samples/sensor/lps22hh_i3c/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename samples/sensor/lsm6dso_i2c_on_i3c/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename samples/subsys/input/input_dump/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename samples/subsys/input/input_dump/boards/{esp32_devkitc_wrover.overlay => esp32_devkitc_wrover_procpu.overlay} (100%) delete mode 100644 samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.conf delete mode 100644 samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.overlay rename samples/subsys/ipc/openamp/boards/{mps2_an521.overlay => mps2_an521_cpu0.overlay} (100%) delete mode 100644 samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_cm4.overlay rename samples/subsys/ipc/rpmsg_service/boards/{mps2_an521.overlay => mps2_an521_cpu0.overlay} (100%) rename samples/subsys/nvs/boards/{esp32_devkitc_wroom.conf => esp32_devkitc_wroom_procpu.conf} (100%) rename samples/subsys/settings/boards/{esp32_devkitc_wroom.conf => esp32_devkitc_wroom_procpu.conf} (100%) rename tests/drivers/adc/adc_api/boards/{esp32_devkitc_wroom.conf => esp32_devkitc_wroom_procpu.conf} (100%) rename tests/drivers/adc/adc_api/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{esp32_devkitc_wrover.conf => esp32_devkitc_wrover_procpu.conf} (100%) rename tests/drivers/adc/adc_api/boards/{esp32_devkitc_wrover.overlay => esp32_devkitc_wrover_procpu.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) create mode 100644 tests/drivers/adc/adc_api/boards/native_posix_64.overlay create mode 100644 tests/drivers/adc/adc_api/boards/native_sim_64.overlay rename tests/drivers/counter/counter_basic_api/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename tests/drivers/counter/counter_basic_api/boards/{esp32_devkitc_wrover.overlay => esp32_devkitc_wrover_procpu.overlay} (100%) rename tests/drivers/dac/dac_api/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename tests/drivers/dac/dac_api/boards/{esp32_devkitc_wrover.overlay => esp32_devkitc_wrover_procpu.overlay} (100%) delete mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm4.conf delete mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm4.overlay delete mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm7.conf delete mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm7.overlay delete mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm4.conf delete mode 100644 tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm4.overlay rename tests/drivers/dma/chan_blen_transfer/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) delete mode 100644 tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_cm7.overlay create mode 100644 tests/drivers/dma/chan_link_transfer/boards/native_sim_64.overlay delete mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm4.conf delete mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm4.overlay delete mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm7.conf delete mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm7.overlay delete mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm4.conf delete mode 100644 tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm4.overlay rename tests/drivers/dma/loop_transfer/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename tests/drivers/dma/scatter_gather/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{em_starterkit.overlay => em_starterkit_emsk_em9d.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename tests/drivers/i2s/i2s_api/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename tests/drivers/i2s/i2s_speed/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename tests/drivers/pwm/pwm_api/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename tests/drivers/pwm/pwm_loopback/boards/{esp32_devkitc_wrover.overlay => esp32_devkitc_wrover_procpu.overlay} (100%) rename tests/drivers/regulator/voltage/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{em_starterkit.overlay => em_starterkit_emsk_em9d.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{emsdp.conf => emsdp_emsdp_em11d.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{emsdp.overlay => emsdp_emsdp_em11d.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{esp32_devkitc_wroom.conf => esp32_devkitc_wroom_procpu.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) delete mode 100644 tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_cm4.overlay delete mode 100644 tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_cm7.overlay delete mode 100644 tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_cm4.overlay rename tests/drivers/uart/uart_async_api/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename tests/kernel/mem_protect/userspace/boards/{mimxrt685_evk.overlay => mimxrt685_evk_mimxrt685s_cm33.overlay} (100%) rename tests/subsys/debug/coredump_backends/boards/{esp32_devkitc_wroom.overlay => esp32_devkitc_wroom_procpu.overlay} (100%) rename tests/subsys/debug/coredump_backends/boards/{esp32_devkitc_wrover.overlay => esp32_devkitc_wrover_procpu.overlay} (100%) diff --git a/samples/basic/blinky_pwm/boards/esp32_devkitc_wroom.overlay b/samples/basic/blinky_pwm/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from samples/basic/blinky_pwm/boards/esp32_devkitc_wroom.overlay rename to samples/basic/blinky_pwm/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/samples/basic/blinky_pwm/boards/mimxrt685_evk.overlay b/samples/basic/blinky_pwm/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from samples/basic/blinky_pwm/boards/mimxrt685_evk.overlay rename to samples/basic/blinky_pwm/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/samples/bluetooth/hci_uart/boards/esp32_devkitc_wroom.conf b/samples/bluetooth/hci_uart/boards/esp32_devkitc_wroom_procpu.conf similarity index 100% rename from samples/bluetooth/hci_uart/boards/esp32_devkitc_wroom.conf rename to samples/bluetooth/hci_uart/boards/esp32_devkitc_wroom_procpu.conf diff --git a/samples/bluetooth/hci_uart/boards/esp32_devkitc_wroom.overlay b/samples/bluetooth/hci_uart/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from samples/bluetooth/hci_uart/boards/esp32_devkitc_wroom.overlay rename to samples/bluetooth/hci_uart/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/samples/boards/esp32/deep_sleep/boards/esp32_devkitc_wroom.conf b/samples/boards/esp32/deep_sleep/boards/esp32_devkitc_wroom_procpu.conf similarity index 100% rename from samples/boards/esp32/deep_sleep/boards/esp32_devkitc_wroom.conf rename to samples/boards/esp32/deep_sleep/boards/esp32_devkitc_wroom_procpu.conf diff --git a/samples/boards/esp32/flash_encryption/boards/esp32_devkitc_wroom.overlay b/samples/boards/esp32/flash_encryption/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from samples/boards/esp32/flash_encryption/boards/esp32_devkitc_wroom.overlay rename to samples/boards/esp32/flash_encryption/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/samples/drivers/adc/boards/esp32_devkitc_wroom.overlay b/samples/drivers/adc/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from samples/drivers/adc/boards/esp32_devkitc_wroom.overlay rename to samples/drivers/adc/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/samples/drivers/adc/boards/esp32_devkitc_wrover.overlay b/samples/drivers/adc/boards/esp32_devkitc_wrover_procpu.overlay similarity index 100% rename from samples/drivers/adc/boards/esp32_devkitc_wrover.overlay rename to samples/drivers/adc/boards/esp32_devkitc_wrover_procpu.overlay diff --git a/samples/drivers/adc/boards/mimxrt1160_evk_cm7.overlay b/samples/drivers/adc/boards/mimxrt1160_evk_cm7.overlay deleted file mode 100644 index a27042020df..00000000000 --- a/samples/drivers/adc/boards/mimxrt1160_evk_cm7.overlay +++ /dev/null @@ -1,34 +0,0 @@ -/* - * SPDX-License-Identifier: Apache-2.0 - * - * Copyright 2021,2023 NXP - */ - -#include - -/ { - zephyr,user { - /* adjust channel number according to pinmux in board.dts */ - io-channels = <&lpadc0 0>; - }; -}; - -&lpadc0 { - #address-cells = <1>; - #size-cells = <0>; - - /* - * To use this sample: - * - Connect LPADC0 CH0 signal to voltage between 0~1.8V (J9 pin 10) - */ - - channel@0 { - reg = <0>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_EXTERNAL0"; - zephyr,vref-mv = <1800>; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - zephyr,input-positive = ; - }; -}; diff --git a/samples/drivers/adc/boards/mimxrt685_evk.overlay b/samples/drivers/adc/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from samples/drivers/adc/boards/mimxrt685_evk.overlay rename to samples/drivers/adc/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/samples/drivers/counter/alarm/boards/esp32_devkitc_wroom.overlay b/samples/drivers/counter/alarm/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/esp32_devkitc_wroom.overlay rename to samples/drivers/counter/alarm/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/samples/drivers/dac/boards/esp32_devkitc_wroom.overlay b/samples/drivers/dac/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from samples/drivers/dac/boards/esp32_devkitc_wroom.overlay rename to samples/drivers/dac/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/samples/drivers/dac/boards/esp32_devkitc_wrover.overlay b/samples/drivers/dac/boards/esp32_devkitc_wrover_procpu.overlay similarity index 100% rename from samples/drivers/dac/boards/esp32_devkitc_wrover.overlay rename to samples/drivers/dac/boards/esp32_devkitc_wrover_procpu.overlay diff --git a/samples/drivers/spi_flash/boards/em_starterkit.conf b/samples/drivers/spi_flash/boards/em_starterkit_emsk_em9d.conf similarity index 100% rename from samples/drivers/spi_flash/boards/em_starterkit.conf rename to samples/drivers/spi_flash/boards/em_starterkit_emsk_em9d.conf diff --git a/samples/drivers/spi_flash/boards/em_starterkit.overlay b/samples/drivers/spi_flash/boards/em_starterkit_emsk_em9d.overlay similarity index 100% rename from samples/drivers/spi_flash/boards/em_starterkit.overlay rename to samples/drivers/spi_flash/boards/em_starterkit_emsk_em9d.overlay diff --git a/samples/drivers/spi_flash/boards/emsdp.conf b/samples/drivers/spi_flash/boards/emsdp_emsdp_em11d.conf similarity index 100% rename from samples/drivers/spi_flash/boards/emsdp.conf rename to samples/drivers/spi_flash/boards/emsdp_emsdp_em11d.conf diff --git a/samples/drivers/watchdog/boards/esp32_devkitc_wroom.conf b/samples/drivers/watchdog/boards/esp32_devkitc_wroom_procpu.conf similarity index 100% rename from samples/drivers/watchdog/boards/esp32_devkitc_wroom.conf rename to samples/drivers/watchdog/boards/esp32_devkitc_wroom_procpu.conf diff --git a/samples/modules/lvgl/demos/boards/native_sim_64.overlay b/samples/modules/lvgl/demos/boards/native_sim_64.overlay new file mode 100644 index 00000000000..ab50aa66f82 --- /dev/null +++ b/samples/modules/lvgl/demos/boards/native_sim_64.overlay @@ -0,0 +1,6 @@ +/* + * Copyright (c) 2023, Fabian Blatz + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "native_posix.overlay" diff --git a/samples/net/wifi/boards/esp32_devkitc_wroom.conf b/samples/net/wifi/boards/esp32_devkitc_wroom_procpu.conf similarity index 100% rename from samples/net/wifi/boards/esp32_devkitc_wroom.conf rename to samples/net/wifi/boards/esp32_devkitc_wroom_procpu.conf diff --git a/samples/net/wifi/boards/esp32_devkitc_wroom.overlay b/samples/net/wifi/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from samples/net/wifi/boards/esp32_devkitc_wroom.overlay rename to samples/net/wifi/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/samples/net/wifi/boards/esp32_devkitc_wrover.conf b/samples/net/wifi/boards/esp32_devkitc_wrover_procpu.conf similarity index 100% rename from samples/net/wifi/boards/esp32_devkitc_wrover.conf rename to samples/net/wifi/boards/esp32_devkitc_wrover_procpu.conf diff --git a/samples/net/wifi/boards/esp32_devkitc_wrover.overlay b/samples/net/wifi/boards/esp32_devkitc_wrover_procpu.overlay similarity index 100% rename from samples/net/wifi/boards/esp32_devkitc_wrover.overlay rename to samples/net/wifi/boards/esp32_devkitc_wrover_procpu.overlay diff --git a/samples/sensor/fxos8700/boards/mimxrt1160_evk_cm4.conf b/samples/sensor/fxos8700/boards/mimxrt1160_evk_cm4.conf deleted file mode 100644 index 16c619082c6..00000000000 --- a/samples/sensor/fxos8700/boards/mimxrt1160_evk_cm4.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_FXOS8700_TRIGGER_OWN_THREAD=n -CONFIG_FXOS8700_TRIGGER_NONE=y diff --git a/samples/sensor/fxos8700/boards/mimxrt1160_evk_cm7.conf b/samples/sensor/fxos8700/boards/mimxrt1160_evk_cm7.conf deleted file mode 100644 index 16c619082c6..00000000000 --- a/samples/sensor/fxos8700/boards/mimxrt1160_evk_cm7.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_FXOS8700_TRIGGER_OWN_THREAD=n -CONFIG_FXOS8700_TRIGGER_NONE=y diff --git a/samples/sensor/grow_r502a/boards/esp32_devkitc_wroom.overlay b/samples/sensor/grow_r502a/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from samples/sensor/grow_r502a/boards/esp32_devkitc_wroom.overlay rename to samples/sensor/grow_r502a/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/samples/sensor/lps22hh_i3c/boards/mimxrt685_evk.overlay b/samples/sensor/lps22hh_i3c/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from samples/sensor/lps22hh_i3c/boards/mimxrt685_evk.overlay rename to samples/sensor/lps22hh_i3c/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk.overlay b/samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk.overlay rename to samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/samples/subsys/input/input_dump/boards/esp32_devkitc_wroom.overlay b/samples/subsys/input/input_dump/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from samples/subsys/input/input_dump/boards/esp32_devkitc_wroom.overlay rename to samples/subsys/input/input_dump/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/samples/subsys/input/input_dump/boards/esp32_devkitc_wrover.overlay b/samples/subsys/input/input_dump/boards/esp32_devkitc_wrover_procpu.overlay similarity index 100% rename from samples/subsys/input/input_dump/boards/esp32_devkitc_wrover.overlay rename to samples/subsys/input/input_dump/boards/esp32_devkitc_wrover_procpu.overlay diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.conf b/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.conf deleted file mode 100644 index 630a1933d62..00000000000 --- a/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_INCLUDE_REMOTE_DIR=y -CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.overlay deleted file mode 100644 index 7facea692cb..00000000000 --- a/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.overlay +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -/ { - chosen { - zephyr,ipc_shm = &ocram2_overlay; - }; - - /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory. - * Define a subset of the OCRAM2 region for demo to use - * Note that shared memory must have specific MPU attributes set. - */ - ocram2_overlay: memory@202c0000{ - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x202c0000 DT_SIZE_K(16)>; - zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; - }; -}; diff --git a/samples/subsys/ipc/openamp/boards/mps2_an521.overlay b/samples/subsys/ipc/openamp/boards/mps2_an521_cpu0.overlay similarity index 100% rename from samples/subsys/ipc/openamp/boards/mps2_an521.overlay rename to samples/subsys/ipc/openamp/boards/mps2_an521_cpu0.overlay diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_cm4.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_cm4.overlay deleted file mode 100644 index 87159192cf2..00000000000 --- a/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_cm4.overlay +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2022-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -/ { - /* Switch to lpuart2, since primary core uses lpuart1 */ - chosen { - zephyr,flash = &ocram; - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - zephyr,ipc_shm = &ocram2_overlay; - }; - - soc { - /delete-node/ gpt@400f0000; - - /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { - compatible = "nxp,gpt-hw-timer"; - reg = <0x400f0000 0x4000>; - interrupts = <120 0>; - status = "okay"; - }; - }; - - /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory. - * Define a subset of the OCRAM2 region for demo to use - * Note that shared memory must have specific MPU attributes set - */ - ocram2_overlay: memory@202c0000 { - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x202c0000 DT_SIZE_K(16)>; - zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; - }; -}; - -/* Enable secondary LPUART */ -&lpuart2 { - status = "okay"; - current-speed = <115200>; -}; - -/* Disable primary GPT timer */ -&gpt_hw_timer { - status = "disabled"; -}; diff --git a/samples/subsys/ipc/rpmsg_service/boards/mps2_an521.overlay b/samples/subsys/ipc/rpmsg_service/boards/mps2_an521_cpu0.overlay similarity index 100% rename from samples/subsys/ipc/rpmsg_service/boards/mps2_an521.overlay rename to samples/subsys/ipc/rpmsg_service/boards/mps2_an521_cpu0.overlay diff --git a/samples/subsys/nvs/boards/esp32_devkitc_wroom.conf b/samples/subsys/nvs/boards/esp32_devkitc_wroom_procpu.conf similarity index 100% rename from samples/subsys/nvs/boards/esp32_devkitc_wroom.conf rename to samples/subsys/nvs/boards/esp32_devkitc_wroom_procpu.conf diff --git a/samples/subsys/settings/boards/esp32_devkitc_wroom.conf b/samples/subsys/settings/boards/esp32_devkitc_wroom_procpu.conf similarity index 100% rename from samples/subsys/settings/boards/esp32_devkitc_wroom.conf rename to samples/subsys/settings/boards/esp32_devkitc_wroom_procpu.conf diff --git a/tests/drivers/adc/adc_api/boards/esp32_devkitc_wroom.conf b/tests/drivers/adc/adc_api/boards/esp32_devkitc_wroom_procpu.conf similarity index 100% rename from tests/drivers/adc/adc_api/boards/esp32_devkitc_wroom.conf rename to tests/drivers/adc/adc_api/boards/esp32_devkitc_wroom_procpu.conf diff --git a/tests/drivers/adc/adc_api/boards/esp32_devkitc_wroom.overlay b/tests/drivers/adc/adc_api/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/esp32_devkitc_wroom.overlay rename to tests/drivers/adc/adc_api/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/tests/drivers/adc/adc_api/boards/esp32_devkitc_wrover.conf b/tests/drivers/adc/adc_api/boards/esp32_devkitc_wrover_procpu.conf similarity index 100% rename from tests/drivers/adc/adc_api/boards/esp32_devkitc_wrover.conf rename to tests/drivers/adc/adc_api/boards/esp32_devkitc_wrover_procpu.conf diff --git a/tests/drivers/adc/adc_api/boards/esp32_devkitc_wrover.overlay b/tests/drivers/adc/adc_api/boards/esp32_devkitc_wrover_procpu.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/esp32_devkitc_wrover.overlay rename to tests/drivers/adc/adc_api/boards/esp32_devkitc_wrover_procpu.overlay diff --git a/tests/drivers/adc/adc_api/boards/mimxrt685_evk.overlay b/tests/drivers/adc/adc_api/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/mimxrt685_evk.overlay rename to tests/drivers/adc/adc_api/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/tests/drivers/adc/adc_api/boards/native_posix_64.overlay b/tests/drivers/adc/adc_api/boards/native_posix_64.overlay new file mode 100644 index 00000000000..6b622000bdf --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/native_posix_64.overlay @@ -0,0 +1,7 @@ +/* + * Copyright 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "native_posix.overlay" diff --git a/tests/drivers/adc/adc_api/boards/native_sim_64.overlay b/tests/drivers/adc/adc_api/boards/native_sim_64.overlay new file mode 100644 index 00000000000..6b622000bdf --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/native_sim_64.overlay @@ -0,0 +1,7 @@ +/* + * Copyright 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "native_posix.overlay" diff --git a/tests/drivers/counter/counter_basic_api/boards/esp32_devkitc_wroom.overlay b/tests/drivers/counter/counter_basic_api/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/esp32_devkitc_wroom.overlay rename to tests/drivers/counter/counter_basic_api/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/esp32_devkitc_wrover.overlay b/tests/drivers/counter/counter_basic_api/boards/esp32_devkitc_wrover_procpu.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/esp32_devkitc_wrover.overlay rename to tests/drivers/counter/counter_basic_api/boards/esp32_devkitc_wrover_procpu.overlay diff --git a/tests/drivers/dac/dac_api/boards/esp32_devkitc_wroom.overlay b/tests/drivers/dac/dac_api/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from tests/drivers/dac/dac_api/boards/esp32_devkitc_wroom.overlay rename to tests/drivers/dac/dac_api/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/tests/drivers/dac/dac_api/boards/esp32_devkitc_wrover.overlay b/tests/drivers/dac/dac_api/boards/esp32_devkitc_wrover_procpu.overlay similarity index 100% rename from tests/drivers/dac/dac_api/boards/esp32_devkitc_wrover.overlay rename to tests/drivers/dac/dac_api/boards/esp32_devkitc_wrover_procpu.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm4.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm4.conf deleted file mode 100644 index cdc6eb7c7f1..00000000000 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm4.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_CODE_DATA_RELOCATION=y -CONFIG_MEM_ATTR_HEAP=y -CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm4.overlay deleted file mode 100644 index 5e8bafa1d9b..00000000000 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm4.overlay +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2022 Kumar Gala - * Copyright (c) 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&sram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; -}; - -tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm7.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm7.conf deleted file mode 100644 index 433a67585be..00000000000 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm7.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_CODE_DATA_RELOCATION=y -CONFIG_MEM_ATTR_HEAP=y -CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="DTCM" diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm7.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm7.overlay deleted file mode 100644 index 82f0bbe94e8..00000000000 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_cm7.overlay +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2022 Kumar Gala - * Copyright (c) 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; -}; - -tst_dma0: &edma0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm4.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm4.conf deleted file mode 100644 index f3ceb4ecbb8..00000000000 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm4.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_CODE_DATA_RELOCATION=y -CONFIG_NOCACHE_MEMORY=y -CONFIG_MEM_ATTR_HEAP=y -CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm4.overlay deleted file mode 100644 index 5e8bafa1d9b..00000000000 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm4.overlay +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2022 Kumar Gala - * Copyright (c) 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&sram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; -}; - -tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_cm7.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_cm7.overlay deleted file mode 100644 index 9d2f44e7231..00000000000 --- a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_cm7.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2022 Kumar Gala - * - * SPDX-License-Identifier: Apache-2.0 - */ - -dma0: &edma0 { }; diff --git a/tests/drivers/dma/chan_link_transfer/boards/native_sim_64.overlay b/tests/drivers/dma/chan_link_transfer/boards/native_sim_64.overlay new file mode 100644 index 00000000000..cbe84107678 --- /dev/null +++ b/tests/drivers/dma/chan_link_transfer/boards/native_sim_64.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2023 Meta + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "native_sim.overlay" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm4.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm4.conf deleted file mode 100644 index cdc6eb7c7f1..00000000000 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm4.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_CODE_DATA_RELOCATION=y -CONFIG_MEM_ATTR_HEAP=y -CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm4.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm4.overlay deleted file mode 100644 index 5e8bafa1d9b..00000000000 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm4.overlay +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2022 Kumar Gala - * Copyright (c) 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&sram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; -}; - -tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm7.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm7.conf deleted file mode 100644 index 8aa11602c69..00000000000 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm7.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_CODE_DATA_RELOCATION=y -CONFIG_MEM_ATTR_HEAP=y -CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="ITCM" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm7.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm7.overlay deleted file mode 100644 index 43b7fc37826..00000000000 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_cm7.overlay +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2022 Kumar Gala - * Copyright (c) 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&itcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; -}; - -tst_dma0: &edma0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm4.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm4.conf deleted file mode 100644 index cdc6eb7c7f1..00000000000 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm4.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_CODE_DATA_RELOCATION=y -CONFIG_MEM_ATTR_HEAP=y -CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm4.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm4.overlay deleted file mode 100644 index 5e8bafa1d9b..00000000000 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm4.overlay +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2022 Kumar Gala - * Copyright (c) 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&sram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; -}; - -tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt685_evk.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt685_evk.overlay rename to tests/drivers/dma/loop_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/tests/drivers/dma/scatter_gather/boards/mimxrt685_evk.overlay b/tests/drivers/dma/scatter_gather/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from tests/drivers/dma/scatter_gather/boards/mimxrt685_evk.overlay rename to tests/drivers/dma/scatter_gather/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/em_starterkit.overlay b/tests/drivers/gpio/gpio_basic_api/boards/em_starterkit_emsk_em9d.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/em_starterkit.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/em_starterkit_emsk_em9d.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/esp32_devkitc_wroom.overlay b/tests/drivers/gpio/gpio_basic_api/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/esp32_devkitc_wroom.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk.overlay b/tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/tests/drivers/i2s/i2s_api/boards/mimxrt685_evk.overlay b/tests/drivers/i2s/i2s_api/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from tests/drivers/i2s/i2s_api/boards/mimxrt685_evk.overlay rename to tests/drivers/i2s/i2s_api/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk.overlay b/tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk.overlay rename to tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/tests/drivers/pwm/pwm_api/boards/esp32_devkitc_wroom.overlay b/tests/drivers/pwm/pwm_api/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from tests/drivers/pwm/pwm_api/boards/esp32_devkitc_wroom.overlay rename to tests/drivers/pwm/pwm_api/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/tests/drivers/pwm/pwm_loopback/boards/esp32_devkitc_wrover.overlay b/tests/drivers/pwm/pwm_loopback/boards/esp32_devkitc_wrover_procpu.overlay similarity index 100% rename from tests/drivers/pwm/pwm_loopback/boards/esp32_devkitc_wrover.overlay rename to tests/drivers/pwm/pwm_loopback/boards/esp32_devkitc_wrover_procpu.overlay diff --git a/tests/drivers/regulator/voltage/boards/mimxrt685_evk.overlay b/tests/drivers/regulator/voltage/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from tests/drivers/regulator/voltage/boards/mimxrt685_evk.overlay rename to tests/drivers/regulator/voltage/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/em_starterkit.overlay b/tests/drivers/spi/spi_loopback/boards/em_starterkit_emsk_em9d.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/em_starterkit.overlay rename to tests/drivers/spi/spi_loopback/boards/em_starterkit_emsk_em9d.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/emsdp.conf b/tests/drivers/spi/spi_loopback/boards/emsdp_emsdp_em11d.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/emsdp.conf rename to tests/drivers/spi/spi_loopback/boards/emsdp_emsdp_em11d.conf diff --git a/tests/drivers/spi/spi_loopback/boards/emsdp.overlay b/tests/drivers/spi/spi_loopback/boards/emsdp_emsdp_em11d.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/emsdp.overlay rename to tests/drivers/spi/spi_loopback/boards/emsdp_emsdp_em11d.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/esp32_devkitc_wroom.conf b/tests/drivers/spi/spi_loopback/boards/esp32_devkitc_wroom_procpu.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/esp32_devkitc_wroom.conf rename to tests/drivers/spi/spi_loopback/boards/esp32_devkitc_wroom_procpu.conf diff --git a/tests/drivers/spi/spi_loopback/boards/esp32_devkitc_wroom.overlay b/tests/drivers/spi/spi_loopback/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/esp32_devkitc_wroom.overlay rename to tests/drivers/spi/spi_loopback/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt685_evk.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt685_evk.overlay rename to tests/drivers/spi/spi_loopback/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_cm4.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_cm4.overlay deleted file mode 100644 index 4f031193d15..00000000000 --- a/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_cm4.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -dut: &lpuart2 { - status = "okay"; - current-speed = <115200>; - nxp,loopback; -}; diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_cm7.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_cm7.overlay deleted file mode 100644 index 37f2577dc2a..00000000000 --- a/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_cm7.overlay +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/ { - chosen { - zephyr,sram = &dtcm; - }; -}; - -dut: &lpuart2 { - status = "okay"; - current-speed = <115200>; - nxp,loopback; -}; diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_cm4.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_cm4.overlay deleted file mode 100644 index 4f031193d15..00000000000 --- a/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_cm4.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -dut: &lpuart2 { - status = "okay"; - current-speed = <115200>; - nxp,loopback; -}; diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt685_evk.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/mimxrt685_evk.overlay rename to tests/drivers/uart/uart_async_api/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/tests/kernel/mem_protect/userspace/boards/mimxrt685_evk.overlay b/tests/kernel/mem_protect/userspace/boards/mimxrt685_evk_mimxrt685s_cm33.overlay similarity index 100% rename from tests/kernel/mem_protect/userspace/boards/mimxrt685_evk.overlay rename to tests/kernel/mem_protect/userspace/boards/mimxrt685_evk_mimxrt685s_cm33.overlay diff --git a/tests/subsys/debug/coredump_backends/boards/esp32_devkitc_wroom.overlay b/tests/subsys/debug/coredump_backends/boards/esp32_devkitc_wroom_procpu.overlay similarity index 100% rename from tests/subsys/debug/coredump_backends/boards/esp32_devkitc_wroom.overlay rename to tests/subsys/debug/coredump_backends/boards/esp32_devkitc_wroom_procpu.overlay diff --git a/tests/subsys/debug/coredump_backends/boards/esp32_devkitc_wrover.overlay b/tests/subsys/debug/coredump_backends/boards/esp32_devkitc_wrover_procpu.overlay similarity index 100% rename from tests/subsys/debug/coredump_backends/boards/esp32_devkitc_wrover.overlay rename to tests/subsys/debug/coredump_backends/boards/esp32_devkitc_wrover_procpu.overlay From 66af7a6881bda5622f7d8e9ee6ee9a51c70b3d28 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 4 Apr 2024 09:03:31 -0400 Subject: [PATCH 2068/2402] gitlint: do not allow treewide as an area in commit messages Treewide changes touching a single area or topic should have the area/subsystem at the start of the commit message. Treewide is very ambigous. Signed-off-by: Anas Nashif --- .gitlint | 2 +- scripts/ci/twister_ignore.txt | 1 + scripts/gitlint/zephyr_commit_rules.py | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.gitlint b/.gitlint index de5285527ce..e83edce6b6e 100644 --- a/.gitlint +++ b/.gitlint @@ -26,7 +26,7 @@ extra-path=scripts/gitlint # max-line-count=200 [title-starts-with-subsystem] -regex = ^(?!subsys:)(([^:]+):)(\s([^:]+):)*\s(.+)$ +regex = ^(?!subsys:)(?!treewide:)(([^:]+):)(\s([^:]+):)*\s(.+)$ [title-must-not-contain-word] # Comma-separated list of words that should not occur in the title. Matching is case diff --git a/scripts/ci/twister_ignore.txt b/scripts/ci/twister_ignore.txt index 8b1ac2f6c3f..8db6878be3a 100644 --- a/scripts/ci/twister_ignore.txt +++ b/scripts/ci/twister_ignore.txt @@ -45,3 +45,4 @@ scripts/checkpatch.pl scripts/ci/pylintrc scripts/footprint/* scripts/set_assignees.py +scripts/gitlint/zephyr_commit_rules.py diff --git a/scripts/gitlint/zephyr_commit_rules.py b/scripts/gitlint/zephyr_commit_rules.py index ea31c6737f3..a2c9cd3cb7f 100644 --- a/scripts/gitlint/zephyr_commit_rules.py +++ b/scripts/gitlint/zephyr_commit_rules.py @@ -95,7 +95,7 @@ class TitleStartsWithSubsystem(LineRule): def validate(self, title, _commit): regex = self.options['regex'].value pattern = re.compile(regex, re.UNICODE) - violation_message = "Commit title does not follow [subsystem]: [subject] (and should not start with literal subsys:)" + violation_message = "Commit title does not follow [subsystem]: [subject] (and should not start with literal subsys or treewide)" if not pattern.search(title): return [RuleViolation(self.id, violation_message, title)] From ca527d9f12bceb23d8ace958233edcdd63de3db7 Mon Sep 17 00:00:00 2001 From: Toon Stegen Date: Thu, 4 Apr 2024 17:32:30 +0200 Subject: [PATCH 2069/2402] doc: add openocd as a dependency for mac openocd is not part of the mac Zephyr SDK, so it should be installed through brew Signed-off-by: Toon Stegen --- doc/develop/getting_started/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/develop/getting_started/index.rst b/doc/develop/getting_started/index.rst index 5946e37d068..56fcb7e991f 100644 --- a/doc/develop/getting_started/index.rst +++ b/doc/develop/getting_started/index.rst @@ -132,7 +132,7 @@ The current minimum required version for the main dependencies are: .. code-block:: bash - brew install cmake ninja gperf python3 ccache qemu dtc libmagic wget + brew install cmake ninja gperf python3 ccache qemu dtc libmagic wget openocd #. Add the Homebrew Python folder to the path, in order to be able to execute ``python`` and ``pip`` as well ``python3`` and ``pip3``. From 7b209eee0a67b8ded574386e0844d10b85d60ddc Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Tue, 28 Mar 2023 10:50:43 -0700 Subject: [PATCH 2070/2402] tests: intel_adsp: Add vecbase lock test Add a test to check if vecbase register was properly locked. Signed-off-by: Flavio Ceolin --- tests/boards/intel_adsp/smoke/src/main.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/tests/boards/intel_adsp/smoke/src/main.c b/tests/boards/intel_adsp/smoke/src/main.c index 36436875051..c212b1e6acb 100644 --- a/tests/boards/intel_adsp/smoke/src/main.c +++ b/tests/boards/intel_adsp/smoke/src/main.c @@ -42,6 +42,30 @@ ZTEST(intel_adsp, test_clock_calibrate) zassert_true((hz / MIN(1, diff)) > 100, "clock rate wrong"); } +#if XCHAL_HAVE_VECBASE +ZTEST(intel_adsp, test_vecbase_lock) +{ + uintptr_t vecbase; + + /* Unfortunately there is not symbol to check if the target + * supports locking VECBASE. The best we can do is checking if + * the first is not set and skip the test. + */ + __asm__ volatile("rsr.vecbase %0" : "=r"(vecbase)); + if ((vecbase & 0x1) == 0) { + ztest_test_skip(); + } + + /* VECBASE register should have been locked during the cpu + * start up. Trying to change its location should fail. + */ + __asm__ volatile("wsr.vecbase %0; rsync" : : "r"(0x0)); + __asm__ volatile("rsr.vecbase %0" : "=r"(vecbase)); + + zassert_not_equal(vecbase, 0x0, "VECBASE was changed"); +} +#endif + static void *intel_adsp_setup(void) { struct intel_adsp_ipc_data *devdata = INTEL_ADSP_IPC_HOST_DEV->data; From a8fa742b186cd724465144c420fc741728464027 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Mon, 8 Apr 2024 16:13:01 +0300 Subject: [PATCH 2071/2402] soc: nxp: imx8: Fix Kconfig.defconfig.* filenames We need to use correct SOC name when naming the Kconfig.defconfig* files. So we need the following changes: - mimx8mp -> mimx8ml8 - mimx8mm -> imx8mm6 - mimx8mn -> mimx8mn6 - mimx8mq -> mimx8mq6 Then we also need to take care of qualifiers name. Standard notation uses "_" instead of "." e.g : Kconfig.defconfig.mimx8mp.a53 -> Kconfig.defconfig.mimx8ml8_a53 Signed-off-by: Daniel Baluta --- ...onfig.defconfig.mimx8mp.a53 => Kconfig.defconfig.mimx8ml8_a53} | 0 ...config.defconfig.mimx8ml8.m7 => Kconfig.defconfig.mimx8ml8_m7} | 0 ...onfig.defconfig.mimx8mm.a53 => Kconfig.defconfig.mimx8mm6_a53} | 0 ...Kconfig.defconfig.mimx8mm.m4 => Kconfig.defconfig.mimx8mm6_m4} | 0 ...onfig.defconfig.mimx8mn.a53 => Kconfig.defconfig.mimx8mn6_a53} | 0 ...Kconfig.defconfig.mimx8mq.m4 => Kconfig.defconfig.mimx8mq6_m4} | 0 6 files changed, 0 insertions(+), 0 deletions(-) rename soc/nxp/imx/imx8m/{Kconfig.defconfig.mimx8mp.a53 => Kconfig.defconfig.mimx8ml8_a53} (100%) rename soc/nxp/imx/imx8m/{Kconfig.defconfig.mimx8ml8.m7 => Kconfig.defconfig.mimx8ml8_m7} (100%) rename soc/nxp/imx/imx8m/{Kconfig.defconfig.mimx8mm.a53 => Kconfig.defconfig.mimx8mm6_a53} (100%) rename soc/nxp/imx/imx8m/{Kconfig.defconfig.mimx8mm.m4 => Kconfig.defconfig.mimx8mm6_m4} (100%) rename soc/nxp/imx/imx8m/{Kconfig.defconfig.mimx8mn.a53 => Kconfig.defconfig.mimx8mn6_a53} (100%) rename soc/nxp/imx/imx8m/{Kconfig.defconfig.mimx8mq.m4 => Kconfig.defconfig.mimx8mq6_m4} (100%) diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mp.a53 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_a53 similarity index 100% rename from soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mp.a53 rename to soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_a53 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_m7 similarity index 100% rename from soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 rename to soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_m7 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.a53 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm6_a53 similarity index 100% rename from soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.a53 rename to soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm6_a53 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.m4 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm6_m4 similarity index 100% rename from soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.m4 rename to soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm6_m4 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn.a53 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn6_a53 similarity index 100% rename from soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn.a53 rename to soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn6_a53 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq6_m4 similarity index 100% rename from soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4 rename to soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq6_m4 From 85911bcfc16f7a46b1718bb6aecdb2ea5aca4498 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sat, 6 Apr 2024 19:25:59 +0300 Subject: [PATCH 2072/2402] net: mdns_responder: Avoid joining IPv4 mcast group if iface is down Check if the interface is down before joining IPv4 mDNS multicast group. This avoids warning later when the network packet cannot be sent. Fixes #71121 Signed-off-by: Jukka Rissanen --- subsys/net/lib/dns/mdns_responder.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/subsys/net/lib/dns/mdns_responder.c b/subsys/net/lib/dns/mdns_responder.c index 15a4c276467..893a3692d37 100644 --- a/subsys/net/lib/dns/mdns_responder.c +++ b/subsys/net/lib/dns/mdns_responder.c @@ -99,8 +99,8 @@ static void mdns_iface_event_handler(struct net_mgmt_event_callback *cb, int ret = net_ipv4_igmp_join(iface, &local_addr4.sin_addr, NULL); if (ret < 0) { - NET_DBG("Cannot add IPv4 multicast address to iface %p", - iface); + NET_DBG("Cannot add IPv4 multicast address to iface %d", + net_if_get_by_iface(iface)); } #endif /* defined(CONFIG_NET_IPV4) */ } @@ -653,10 +653,25 @@ static void iface_ipv4_cb(struct net_if *iface, void *user_data) struct in_addr *addr = user_data; int ret; + if (!net_if_is_up(iface)) { + struct net_if_mcast_addr *maddr; + + NET_DBG("Interface %d is down, not joining mcast group yet", + net_if_get_by_iface(iface)); + + maddr = net_if_ipv4_maddr_add(iface, addr); + if (!maddr) { + NET_DBG("Cannot add multicast address %s", + net_sprint_ipv4_addr(addr)); + } + + return; + } + ret = net_ipv4_igmp_join(iface, addr, NULL); if (ret < 0) { - NET_DBG("Cannot add IPv4 multicast address to iface %p", - iface); + NET_DBG("Cannot add IPv4 multicast address to iface %d", + net_if_get_by_iface(iface)); } } From f7b92f1eae11abab22ba06b55fbdd438fa36f68d Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Sat, 6 Apr 2024 10:05:09 +0000 Subject: [PATCH 2073/2402] drivers: can: shell: use CAN_STD_ID_MASK/CAN_EXT_ID_MASK Use CAN_STD_ID_MASK/CAN_EXT_ID_MASK instead of CAN_MAX_STD_ID/CAN_MAX_EXT_ID. Signed-off-by: Henrik Brix Andersen --- drivers/can/can_shell.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/can/can_shell.c b/drivers/can/can_shell.c index e9573b56a4b..66cb4c127c9 100644 --- a/drivers/can/can_shell.c +++ b/drivers/can/can_shell.c @@ -679,7 +679,7 @@ static int cmd_can_send(const struct shell *sh, size_t argc, char **argv) static unsigned int frame_counter; unsigned int frame_no; struct can_frame frame; - uint32_t max_id; + uint32_t id_mask; int argidx = 2; uint32_t val; char *endptr; @@ -693,7 +693,7 @@ static int cmd_can_send(const struct shell *sh, size_t argc, char **argv) } /* Defaults */ - max_id = CAN_MAX_STD_ID; + id_mask = CAN_STD_ID_MASK; frame.flags = 0; frame.dlc = 0; @@ -704,7 +704,7 @@ static int cmd_can_send(const struct shell *sh, size_t argc, char **argv) break; } else if (strcmp(argv[argidx], "-e") == 0) { frame.flags |= CAN_FRAME_IDE; - max_id = CAN_MAX_EXT_ID; + id_mask = CAN_EXT_ID_MASK; argidx++; } else if (strcmp(argv[argidx], "-r") == 0) { frame.flags |= CAN_FRAME_RTR; @@ -735,7 +735,7 @@ static int cmd_can_send(const struct shell *sh, size_t argc, char **argv) return -EINVAL; } - if (val > max_id) { + if (val > id_mask) { shell_error(sh, "CAN ID 0x%0*x out of range", (frame.flags & CAN_FRAME_IDE) != 0 ? 8 : 3, val); @@ -798,7 +798,7 @@ static int cmd_can_filter_add(const struct shell *sh, size_t argc, char **argv) { const struct device *dev = device_get_binding(argv[1]); struct can_filter filter; - uint32_t max_id; + uint32_t id_mask; int argidx = 2; uint32_t val; char *endptr; @@ -810,7 +810,7 @@ static int cmd_can_filter_add(const struct shell *sh, size_t argc, char **argv) } /* Defaults */ - max_id = CAN_MAX_STD_ID; + id_mask = CAN_STD_ID_MASK; filter.flags = 0U; /* Parse options */ @@ -820,7 +820,7 @@ static int cmd_can_filter_add(const struct shell *sh, size_t argc, char **argv) break; } else if (strcmp(argv[argidx], "-e") == 0) { filter.flags |= CAN_FILTER_IDE; - max_id = CAN_MAX_EXT_ID; + id_mask = CAN_EXT_ID_MASK; argidx++; } else { shell_error(sh, "unsupported argument %s", argv[argidx]); @@ -842,7 +842,7 @@ static int cmd_can_filter_add(const struct shell *sh, size_t argc, char **argv) return -EINVAL; } - if (val > max_id) { + if (val > id_mask) { shell_error(sh, "CAN ID 0x%0*x out of range", (filter.flags & CAN_FILTER_IDE) != 0 ? 8 : 3, val); @@ -859,7 +859,7 @@ static int cmd_can_filter_add(const struct shell *sh, size_t argc, char **argv) return -EINVAL; } - if (val > max_id) { + if (val > id_mask) { shell_error(sh, "CAN ID mask 0x%0*x out of range", (filter.flags & CAN_FILTER_IDE) != 0 ? 8 : 3, val); @@ -867,7 +867,7 @@ static int cmd_can_filter_add(const struct shell *sh, size_t argc, char **argv) } } else { - val = max_id; + val = id_mask; } filter.mask = val; From c6e4748deb41698edf863512172a57a4c82674d0 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Sat, 6 Apr 2024 10:06:45 +0000 Subject: [PATCH 2074/2402] drivers: can: deprecate CAN_MAX_STD_ID/CAN_MAX_EXT_ID macros Deprecate CAN_MAX_STD_ID/CAN_MAX_EXT_ID macros in favor of CAN_STD_ID_MASK/CAN_EXT_ID_MASK. Signed-off-by: Henrik Brix Andersen --- include/zephyr/drivers/can.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index 2912ecbc577..d677d8a9263 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -47,16 +47,20 @@ extern "C" { #define CAN_STD_ID_MASK 0x7FFU /** * @brief Maximum value for a standard (11-bit) CAN identifier. + * + * @deprecated Use ``CAN_STD_ID_MASK`` instead. */ -#define CAN_MAX_STD_ID CAN_STD_ID_MASK +#define CAN_MAX_STD_ID CAN_STD_ID_MASK __DEPRECATED_MACRO /** * @brief Bit mask for an extended (29-bit) CAN identifier. */ #define CAN_EXT_ID_MASK 0x1FFFFFFFU /** * @brief Maximum value for an extended (29-bit) CAN identifier. + * + * @deprecated Use ``CAN_EXT_ID_MASK`` instead. */ -#define CAN_MAX_EXT_ID CAN_EXT_ID_MASK +#define CAN_MAX_EXT_ID CAN_EXT_ID_MASK __DEPRECATED_MACRO /** * @brief Maximum data length code for CAN 2.0A/2.0B. */ From 33e533386424593b8c15e8f21f3a494211a06521 Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Fri, 5 Apr 2024 18:14:14 +0000 Subject: [PATCH 2075/2402] west: updated hal_nxp for updated LPC PWM definitions Updated the west.yml file to add nxp_hal update for pwm definitions used by devices LPC5534, LPC5536 and LPC55S36. The nxp_hal changes lets the PWM driver be aware that these devices contain a WAITEN bit in their PWM register which can be used when setting up the PWM on init phase. Signed-off-by: Emilio Benavente --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index c89ad043c28..6ee89e4b0bb 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 6b252c34eef7d0fdd2dee8261ab68086522c4435 + revision: 14160a1c14c06ce5a918cd550989555d832a636f path: modules/hal/nxp groups: - hal From f8ddeed85c7c01d05a69e13d9d5c0738df338860 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20G=C5=82=C4=85b?= Date: Fri, 5 Apr 2024 09:03:40 +0200 Subject: [PATCH 2076/2402] samples: subsys: settings: Add configuration for nRF54L15 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add configuration needed to run the sample on nrf54l15pdk/nrf54l15/cpuapp. Signed-off-by: Sebastian Głąb --- samples/subsys/settings/boards/nrf54l15pdk_nrf54l15_cpuapp.conf | 2 ++ samples/subsys/settings/sample.yaml | 1 + 2 files changed, 3 insertions(+) create mode 100644 samples/subsys/settings/boards/nrf54l15pdk_nrf54l15_cpuapp.conf diff --git a/samples/subsys/settings/boards/nrf54l15pdk_nrf54l15_cpuapp.conf b/samples/subsys/settings/boards/nrf54l15pdk_nrf54l15_cpuapp.conf new file mode 100644 index 00000000000..3746c13c741 --- /dev/null +++ b/samples/subsys/settings/boards/nrf54l15pdk_nrf54l15_cpuapp.conf @@ -0,0 +1,2 @@ +CONFIG_NVS=y +CONFIG_SETTINGS_NVS=y diff --git a/samples/subsys/settings/sample.yaml b/samples/subsys/settings/sample.yaml index 101c290bb96..3ab57ee0923 100644 --- a/samples/subsys/settings/sample.yaml +++ b/samples/subsys/settings/sample.yaml @@ -12,6 +12,7 @@ tests: - native_sim - native_sim/native/64 - mr_canhubk3 + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - native_sim harness: console From 155fee5924d4d62d67fb69a9ba00853cf2e1f19f Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 4 Apr 2024 08:19:48 +0900 Subject: [PATCH 2077/2402] drivers: serial: pl011: Introduce macros to separate device-dependent code Introduce the `COMPAT_SPECIFIC_...` macros to determine the function name from the compatible name. These macros allow the isolation of device-dependent code in a generic way. For example, if the compatible name is `ambiq,uart`, The `COMPAT_SPECIFIC_DEFINE` macro is replaced by `AMBIQ_UART_DEFINE`. Signed-off-by: TOKITA Hiroshi --- drivers/serial/uart_pl011.c | 55 +++++++++++++++++++++++-------- drivers/serial/uart_pl011_ambiq.h | 10 +++--- 2 files changed, 46 insertions(+), 19 deletions(-) diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c index 3510fe29ba6..7b93e006821 100644 --- a/drivers/serial/uart_pl011.c +++ b/drivers/serial/uart_pl011.c @@ -468,6 +468,35 @@ static int pl011_init(const struct device *dev) return 0; } +#define COMPAT_SPECIFIC_FUNC_NAME(prefix, name) _CONCAT(_CONCAT(prefix, name), _) + +/* + * The first element of compatible is used to determine the type. + * When compatible defines as "ambiq,uart", "arm,pl011", + * this macro expands to pwr_on_ambiq_uart_[n]. + */ +#define COMPAT_SPECIFIC_PWR_ON_FUNC(n) \ + _CONCAT(COMPAT_SPECIFIC_FUNC_NAME(pwr_on_, DT_INST_STRING_TOKEN_BY_IDX(n, compatible, 0)), \ + n) + +/* + * The first element of compatible is used to determine the type. + * When compatible defines as "ambiq,uart", "arm,pl011", + * this macro expands to clk_enable_ambiq_uart_[n]. + */ +#define COMPAT_SPECIFIC_CLK_ENABLE_FUNC(n) \ + _CONCAT(COMPAT_SPECIFIC_FUNC_NAME(clk_enable_, \ + DT_INST_STRING_TOKEN_BY_IDX(n, compatible, 0)), n) + +/* + * The first element of compatible is used to determine the type. + * When compatible defines as "ambiq,uart", "arm,pl011", + * this macro expands to AMBIQ_UART_DEFINE(n). + */ +#define COMPAT_SPECIFIC_DEFINE(n) \ + _CONCAT(DT_INST_STRING_UPPER_TOKEN_BY_IDX(n, compatible, 0), _DEFINE)(n) + + #if defined(CONFIG_PINCTRL) #define PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n); #define PINCTRL_INIT(n) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), @@ -476,17 +505,15 @@ static int pl011_init(const struct device *dev) #define PINCTRL_INIT(n) #endif /* CONFIG_PINCTRL */ -#define PL011_GET_COMPAT_QUIRK_NONE(n) NULL - -#define PL011_GET_COMPAT_CLK_QUIRK_0(n) \ - COND_CODE_1(DT_NODE_HAS_COMPAT(DT_DRV_INST(n), ambiq_uart), \ - (clk_enable_ambiq_uart), \ - PL011_GET_COMPAT_QUIRK_NONE(n)) - -#define PL011_GET_COMPAT_PWR_QUIRK_0(n) \ - COND_CODE_1(DT_NODE_HAS_COMPAT(DT_DRV_INST(n), ambiq_uart), \ - (pwr_on_ambiq_uart_##n), \ - PL011_GET_COMPAT_QUIRK_NONE(n)) +#define ARM_PL011_DEFINE(n) \ + static inline int pwr_on_arm_pl011_##n(void) \ + { \ + return 0; \ + } \ + static inline int clk_enable_arm_pl011_##n(const struct device *dev, uint32_t clk) \ + { \ + return 0; \ + } #ifdef CONFIG_UART_INTERRUPT_DRIVEN void pl011_isr(const struct device *dev) @@ -523,8 +550,8 @@ void pl011_isr(const struct device *dev) .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \ PINCTRL_INIT(n) \ .irq_config_func = pl011_irq_config_func_##n, \ - .clk_enable_func = PL011_GET_COMPAT_CLK_QUIRK_0(n), \ - .pwr_on_func = PL011_GET_COMPAT_PWR_QUIRK_0(n), \ + .clk_enable_func = COMPAT_SPECIFIC_CLK_ENABLE_FUNC(n), \ + .pwr_on_func = COMPAT_SPECIFIC_PWR_ON_FUNC(n), \ }; #else #define PL011_CONFIG_PORT(n) \ @@ -537,7 +564,7 @@ void pl011_isr(const struct device *dev) #define PL011_INIT(n) \ PINCTRL_DEFINE(n) \ - PL011_QUIRK_AMBIQ_UART_DEFINE(n) \ + COMPAT_SPECIFIC_DEFINE(n) \ PL011_CONFIG_PORT(n) \ \ static struct pl011_data pl011_data_port_##n = { \ diff --git a/drivers/serial/uart_pl011_ambiq.h b/drivers/serial/uart_pl011_ambiq.h index 470e0e35a95..24a356571a2 100644 --- a/drivers/serial/uart_pl011_ambiq.h +++ b/drivers/serial/uart_pl011_ambiq.h @@ -55,7 +55,7 @@ static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk) * Note: busy wait is not allowed to use here due to UART is initiated before timer starts. */ -#define QUIRK_AMBIQ_UART_DEFINE(n) \ +#define AMBIQ_UART_DEFINE(n) \ static int pwr_on_ambiq_uart_##n(void) \ { \ uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \ @@ -67,10 +67,10 @@ static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk) arch_nop(); \ }; \ return 0; \ + } \ + static inline int clk_enable_ambiq_uart_##n(const struct device *dev, uint32_t clk) \ + { \ + return clk_enable_ambiq_uart(dev, clk); \ } -#define PL011_QUIRK_AMBIQ_UART_DEFINE(n) \ - COND_CODE_1(DT_NODE_HAS_COMPAT(DT_DRV_INST(n), ambiq_uart), (QUIRK_AMBIQ_UART_DEFINE(n)), \ - ()) - #endif /* ZEPHYR_DRIVERS_SERIAL_UART_PL011_AMBIQ_H_ */ From 80b8ef80b3cf4c1ac33e9715c18a6613b6cd61f4 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 4 Apr 2024 07:00:17 +0900 Subject: [PATCH 2078/2402] drivers: serial: pl011: Add capability for handling reset device Reset the device on initializing if the node inherits `reset-device.yaml`. Signed-off-by: TOKITA Hiroshi --- drivers/serial/uart_pl011.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c index 7b93e006821..cd8e24fb12f 100644 --- a/drivers/serial/uart_pl011.c +++ b/drivers/serial/uart_pl011.c @@ -21,6 +21,9 @@ #if defined(CONFIG_PINCTRL) #include #endif +#if IS_ENABLED(CONFIG_RESET) +#include +#endif #ifdef CONFIG_CPU_CORTEX_M #include @@ -35,6 +38,9 @@ struct pl011_config { #if defined(CONFIG_PINCTRL) const struct pinctrl_dev_config *pincfg; #endif +#if IS_ENABLED(CONFIG_RESET) + const struct reset_dt_spec reset; +#endif #ifdef CONFIG_UART_INTERRUPT_DRIVEN uart_irq_config_func_t irq_config_func; #endif @@ -408,6 +414,15 @@ static int pl011_init(const struct device *dev) DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); +#if IS_ENABLED(CONFIG_RESET) + if (config->reset.dev) { + ret = reset_line_toggle_dt(&config->reset); + if (ret) { + return ret; + } + } +#endif + /* * If working in SBSA mode, we assume that UART is already configured, * or does not require configuration at all (if UART is emulated by @@ -505,6 +520,13 @@ static int pl011_init(const struct device *dev) #define PINCTRL_INIT(n) #endif /* CONFIG_PINCTRL */ +#if IS_ENABLED(CONFIG_RESET) +#define RESET_INIT(n) \ + IF_ENABLED(DT_INST_NODE_HAS_PROP(0, resets), (.reset = RESET_DT_SPEC_INST_GET(n),)) +#else +#define RESET_INIT(n) +#endif + #define ARM_PL011_DEFINE(n) \ static inline int pwr_on_arm_pl011_##n(void) \ { \ From dd84e8db26dfd7c08cad381f12794679abad3d94 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 4 Apr 2024 07:10:48 +0900 Subject: [PATCH 2079/2402] drivers: serial: pl011: Use clock control to determine frequency If a clock control device is set in the `clocks` property, it is used to determine the frequency. If `fixed-clock` is set for the clocks, we use that value as is. Signed-off-by: TOKITA Hiroshi --- drivers/serial/uart_pl011.c | 40 +++++++++++++++++++++++++++++-------- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c index cd8e24fb12f..6b496923536 100644 --- a/drivers/serial/uart_pl011.c +++ b/drivers/serial/uart_pl011.c @@ -24,6 +24,9 @@ #if IS_ENABLED(CONFIG_RESET) #include #endif +#if IS_ENABLED(CONFIG_CLOCK_CONTROL) +#include +#endif #ifdef CONFIG_CPU_CORTEX_M #include @@ -34,13 +37,16 @@ struct pl011_config { DEVICE_MMIO_ROM; - uint32_t sys_clk_freq; #if defined(CONFIG_PINCTRL) const struct pinctrl_dev_config *pincfg; #endif #if IS_ENABLED(CONFIG_RESET) const struct reset_dt_spec reset; #endif +#if IS_ENABLED(CONFIG_CLOCK_CONTROL) + const struct device *clock_dev; + clock_control_subsys_t clock_id; +#endif #ifdef CONFIG_UART_INTERRUPT_DRIVEN uart_irq_config_func_t irq_config_func; #endif @@ -53,6 +59,7 @@ struct pl011_data { DEVICE_MMIO_RAM; struct uart_config uart_cfg; bool sbsa; /* SBSA mode */ + uint32_t clk_freq; #ifdef CONFIG_UART_INTERRUPT_DRIVEN volatile bool sw_call_txdrdy; uart_irq_callback_user_data_t irq_cb; @@ -150,7 +157,6 @@ static int pl011_runtime_configure_internal(const struct device *dev, const struct uart_config *cfg, bool disable) { - const struct pl011_config *config = dev->config; struct pl011_data *data = dev->data; uint32_t lcrh; int ret = -ENOTSUP; @@ -216,7 +222,7 @@ static int pl011_runtime_configure_internal(const struct device *dev, } /* Set baud rate */ - ret = pl011_set_baudrate(dev, config->sys_clk_freq, cfg->baudrate); + ret = pl011_set_baudrate(dev, data->clk_freq, cfg->baudrate); if (ret != 0) { goto enable; } @@ -423,6 +429,13 @@ static int pl011_init(const struct device *dev) } #endif +#if IS_ENABLED(CONFIG_CLOCK_CONTROL) + if (config->clock_dev) { + clock_control_on(config->clock_dev, config->clock_id); + clock_control_get_rate(config->clock_dev, config->clock_id, &data->clk_freq); + } +#endif + /* * If working in SBSA mode, we assume that UART is already configured, * or does not require configuration at all (if UART is emulated by @@ -446,7 +459,7 @@ static int pl011_init(const struct device *dev) /* Call vendor-specific function to enable clock for the peripheral */ if (config->clk_enable_func != NULL) { - ret = config->clk_enable_func(dev, config->sys_clk_freq); + ret = config->clk_enable_func(dev, data->clk_freq); if (ret) { return ret; } @@ -511,6 +524,8 @@ static int pl011_init(const struct device *dev) #define COMPAT_SPECIFIC_DEFINE(n) \ _CONCAT(DT_INST_STRING_UPPER_TOKEN_BY_IDX(n, compatible, 0), _DEFINE)(n) +#define COMPAT_SPECIFIC_CLOCK_CTLR_SUBSYS_CELL(n) \ + _CONCAT(DT_INST_STRING_UPPER_TOKEN_BY_IDX(n, compatible, 0), _CLOCK_CTLR_SUBSYS_CELL) #if defined(CONFIG_PINCTRL) #define PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n); @@ -527,6 +542,12 @@ static int pl011_init(const struct device *dev) #define RESET_INIT(n) #endif +#define CLOCK_INIT(n) \ + COND_CODE_1(DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(n), fixed_clock), (), \ + (.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clock_id = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, \ + COMPAT_SPECIFIC_CLOCK_CTLR_SUBSYS_CELL(n)),)) + #define ARM_PL011_DEFINE(n) \ static inline int pwr_on_arm_pl011_##n(void) \ { \ @@ -569,8 +590,8 @@ void pl011_isr(const struct device *dev) \ static struct pl011_config pl011_cfg_port_##n = { \ DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \ - .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \ - PINCTRL_INIT(n) \ + CLOCK_INIT(n) \ + PINCTRL_INIT(n) \ .irq_config_func = pl011_irq_config_func_##n, \ .clk_enable_func = COMPAT_SPECIFIC_CLK_ENABLE_FUNC(n), \ .pwr_on_func = COMPAT_SPECIFIC_PWR_ON_FUNC(n), \ @@ -579,8 +600,8 @@ void pl011_isr(const struct device *dev) #define PL011_CONFIG_PORT(n) \ static struct pl011_config pl011_cfg_port_##n = { \ DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \ - .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \ - PINCTRL_INIT(n) \ + CLOCK_INIT(n) \ + PINCTRL_INIT(n) \ }; #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ @@ -597,6 +618,9 @@ void pl011_isr(const struct device *dev) .data_bits = UART_CFG_DATA_BITS_8, \ .flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \ }, \ + .clk_freq = COND_CODE_1( \ + DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(n), fixed_clock), \ + (DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency)), (0)), \ }; \ \ DEVICE_DT_INST_DEFINE(n, &pl011_init, \ From e93cf224b6e8f6559f6b40a18c09f884b01f4855 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Sun, 7 Apr 2024 17:24:07 +0900 Subject: [PATCH 2080/2402] drivers: serial: pl011: Add err_check function Implementing err_check function by porting from rpi_pico implementation. Signed-off-by: TOKITA Hiroshi --- drivers/serial/uart_pl011.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c index 6b496923536..53e6e96b123 100644 --- a/drivers/serial/uart_pl011.c +++ b/drivers/serial/uart_pl011.c @@ -153,6 +153,29 @@ static void pl011_poll_out(const struct device *dev, get_uart(dev)->dr = (uint32_t)c; } +static int pl011_err_check(const struct device *dev) +{ + int errors = 0; + + if (get_uart(dev)->rsr & PL011_RSR_ECR_OE) { + errors |= UART_ERROR_OVERRUN; + } + + if (get_uart(dev)->rsr & PL011_RSR_ECR_BE) { + errors |= UART_BREAK; + } + + if (get_uart(dev)->rsr & PL011_RSR_ECR_PE) { + errors |= UART_ERROR_PARITY; + } + + if (get_uart(dev)->rsr & PL011_RSR_ECR_FE) { + errors |= UART_ERROR_FRAMING; + } + + return errors; +} + static int pl011_runtime_configure_internal(const struct device *dev, const struct uart_config *cfg, bool disable) @@ -390,6 +413,7 @@ static void pl011_irq_callback_set(const struct device *dev, static const struct uart_driver_api pl011_driver_api = { .poll_in = pl011_poll_in, .poll_out = pl011_poll_out, + .err_check = pl011_err_check, #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE .configure = pl011_runtime_configure, .config_get = pl011_runtime_config_get, From e678a6247d1a651f9bbbc48403d60510b2fbda30 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 4 Apr 2024 06:58:49 +0900 Subject: [PATCH 2081/2402] drivers: serial: rpi_pico: Migrate to pl011 driver RaspberryPi Pico's UART can be operated with the pl011 driver. Replace it with this. Signed-off-by: TOKITA Hiroshi --- drivers/serial/CMakeLists.txt | 1 - drivers/serial/Kconfig.pl011 | 1 + drivers/serial/Kconfig.rpi_pico | 9 - drivers/serial/uart_pl011.c | 1 + drivers/serial/uart_pl011_raspberrypi_pico.h | 23 + drivers/serial/uart_rpi_pico.c | 472 ------------------- dts/arm/rpi_pico/rp2040.dtsi | 4 +- 7 files changed, 27 insertions(+), 484 deletions(-) create mode 100644 drivers/serial/uart_pl011_raspberrypi_pico.h delete mode 100644 drivers/serial/uart_rpi_pico.c diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index 9f35b365021..ef0133a5ca1 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -43,7 +43,6 @@ zephyr_library_sources_ifdef(CONFIG_UART_PSOC6 uart_psoc6.c) zephyr_library_sources_ifdef(CONFIG_UART_PL011 uart_pl011.c) zephyr_library_sources_ifdef(CONFIG_UART_QUICKLOGIC_USBSERIALPORT_S3B uart_ql_usbserialport_s3b.c) zephyr_library_sources_ifdef(CONFIG_UART_RV32M1_LPUART uart_rv32m1_lpuart.c) -zephyr_library_sources_ifdef(CONFIG_UART_RPI_PICO uart_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_UART_RPI_PICO_PIO uart_rpi_pico_pio.c) zephyr_library_sources_ifdef(CONFIG_UART_LITEUART uart_liteuart.c) zephyr_library_sources_ifdef(CONFIG_UART_RTT_DRIVER uart_rtt.c) diff --git a/drivers/serial/Kconfig.pl011 b/drivers/serial/Kconfig.pl011 index 5a13b3adda9..e68771f97e9 100644 --- a/drivers/serial/Kconfig.pl011 +++ b/drivers/serial/Kconfig.pl011 @@ -9,6 +9,7 @@ menuconfig UART_PL011 select SERIAL_SUPPORT_INTERRUPT select PINCTRL if SOC_EOS_S3 select PINCTRL if DT_HAS_AMBIQ_UART_ENABLED + select PINCTRL if DT_HAS_RASPBERRYPI_PICO_UART_ENABLED help This option enables the UART driver for the PL011 diff --git a/drivers/serial/Kconfig.rpi_pico b/drivers/serial/Kconfig.rpi_pico index 0465570f704..e0549eeaff6 100644 --- a/drivers/serial/Kconfig.rpi_pico +++ b/drivers/serial/Kconfig.rpi_pico @@ -1,15 +1,6 @@ # Copyright (c) 2021 Yonatan Schachter # SPDX-License-Identifier: Apache-2.0 -config UART_RPI_PICO - bool "Raspberry Pi UART driver" - default y - depends on DT_HAS_RASPBERRYPI_PICO_UART_ENABLED - select SERIAL_HAS_DRIVER - select PICOSDK_USE_UART - select SERIAL_SUPPORT_INTERRUPT - depends on RESET - config UART_RPI_PICO_PIO bool "Raspberry Pi PIO UART driver" default y diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c index 53e6e96b123..160d6887f9d 100644 --- a/drivers/serial/uart_pl011.c +++ b/drivers/serial/uart_pl011.c @@ -34,6 +34,7 @@ #include "uart_pl011_registers.h" #include "uart_pl011_ambiq.h" +#include "uart_pl011_raspberrypi_pico.h" struct pl011_config { DEVICE_MMIO_ROM; diff --git a/drivers/serial/uart_pl011_raspberrypi_pico.h b/drivers/serial/uart_pl011_raspberrypi_pico.h new file mode 100644 index 00000000000..480d6e1d1de --- /dev/null +++ b/drivers/serial/uart_pl011_raspberrypi_pico.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SERIAL_UART_PL011_RASPBERRYPI_PICO_H_ +#define ZEPHYR_DRIVERS_SERIAL_UART_PL011_RASPBERRYPI_PICO_H_ + +#define RASPBERRYPI_PICO_UART_CLOCK_CTLR_SUBSYS_CELL clk_id + +#define RASPBERRYPI_PICO_UART_DEFINE(n) \ + static inline int pwr_on_raspberrypi_pico_uart_##n(void) \ + { \ + return 0; \ + } \ + static inline int clk_enable_raspberrypi_pico_uart_##n(const struct device *dev, \ + uint32_t clk) \ + { \ + return 0; \ + } + +#endif /* ZEPHYR_DRIVERS_SERIAL_UART_PL011_RASPBERRYPI_PICO_H_ */ diff --git a/drivers/serial/uart_rpi_pico.c b/drivers/serial/uart_rpi_pico.c deleted file mode 100644 index 14c355a9913..00000000000 --- a/drivers/serial/uart_rpi_pico.c +++ /dev/null @@ -1,472 +0,0 @@ -/* - * Copyright (c) 2021, Yonatan Schachter - * Copyright (c) 2022, Andrei-Edward Popa - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -/* pico-sdk includes */ -#include - -#define DT_DRV_COMPAT raspberrypi_pico_uart - -struct uart_rpi_config { - uart_hw_t *const uart_regs; - const struct pinctrl_dev_config *pcfg; - const struct reset_dt_spec reset; - const struct device *clk_dev; - clock_control_subsys_t clk_id; -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - uart_irq_config_func_t irq_config_func; -#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ -}; - -struct uart_rpi_data { - struct uart_config uart_config; -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - uart_irq_callback_user_data_t irq_cb; - void *irq_cb_data; -#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ -}; - -static int uart_rpi_poll_in(const struct device *dev, unsigned char *c) -{ - const struct uart_rpi_config *config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - - if (uart_hw->fr & UART_UARTFR_RXFE_BITS) { - return -1; - } - - *c = (unsigned char)uart_hw->dr; - return 0; -} - -static void uart_rpi_poll_out(const struct device *dev, unsigned char c) -{ - const struct uart_rpi_config *config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - - while (uart_hw->fr & UART_UARTFR_TXFF_BITS) { - /* Wait */ - } - - uart_hw->dr = c; -} - -static int uart_rpi_set_baudrate(const struct device *dev, uint32_t input_baudrate, - uint32_t *output_baudrate) -{ - const struct uart_rpi_config *cfg = dev->config; - uart_hw_t * const uart_hw = cfg->uart_regs; - uint32_t baudrate_frac; - uint32_t baudrate_int; - uint32_t baudrate_div; - uint32_t pclk; - int ret; - - if (input_baudrate == 0) { - return -EINVAL; - } - - ret = clock_control_get_rate(cfg->clk_dev, cfg->clk_id, &pclk); - if (ret < 0 || pclk == 0) { - return -EINVAL; - } - - baudrate_div = (8 * pclk / input_baudrate); - baudrate_int = baudrate_div >> 7; - baudrate_frac = (baudrate_int == 0) || (baudrate_int >= UINT16_MAX) ? 0 : - ((baudrate_div & 0x7f) + 1) / 2; - baudrate_int = (baudrate_int == 0) ? 1 : - (baudrate_int >= UINT16_MAX) ? UINT16_MAX : baudrate_int; - - uart_hw->ibrd = baudrate_int; - uart_hw->fbrd = baudrate_frac; - - uart_hw->lcr_h |= 0; - - *output_baudrate = (4 * pclk) / (64 * baudrate_int + baudrate_frac); - - return 0; -} - -static int uart_rpi_set_format(const struct device *dev, const struct uart_config *cfg) -{ - const struct uart_rpi_config *config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - uint32_t data_bits; - uint32_t stop_bits; - uint32_t lcr_value; - uint32_t lcr_mask; - - switch (cfg->data_bits) { - case UART_CFG_DATA_BITS_5: - data_bits = 5; - break; - case UART_CFG_DATA_BITS_6: - data_bits = 6; - break; - case UART_CFG_DATA_BITS_7: - data_bits = 7; - break; - case UART_CFG_DATA_BITS_8: - data_bits = 8; - break; - default: - return -EINVAL; - } - - switch (cfg->stop_bits) { - case UART_CFG_STOP_BITS_1: - stop_bits = 1; - break; - case UART_CFG_STOP_BITS_2: - stop_bits = 2; - break; - default: - return -EINVAL; - } - - lcr_mask = UART_UARTLCR_H_WLEN_BITS | UART_UARTLCR_H_STP2_BITS | - UART_UARTLCR_H_PEN_BITS | UART_UARTLCR_H_EPS_BITS; - - lcr_value = ((data_bits - 5) << UART_UARTLCR_H_WLEN_LSB) | - ((stop_bits - 1) << UART_UARTLCR_H_STP2_LSB) | - (!!(cfg->parity != UART_CFG_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) | - (!!(cfg->parity == UART_CFG_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB); - - uart_hw->lcr_h = (uart_hw->lcr_h & ~lcr_mask) | (lcr_value & lcr_mask); - - return 0; -} - -static int uart_rpi_init(const struct device *dev) -{ - const struct uart_rpi_config *config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - struct uart_rpi_data * const data = dev->data; - uint32_t baudrate; - int ret; - - ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); - if (ret < 0) { - return ret; - } - - ret = clock_control_on(config->clk_dev, config->clk_id); - if (ret < 0) { - return ret; - } - - ret = reset_line_toggle(config->reset.dev, config->reset.id); - if (ret < 0) { - return ret; - } - - ret = uart_rpi_set_baudrate(dev, data->uart_config.baudrate, &baudrate); - if (ret < 0) { - return ret; - } - - uart_rpi_set_format(dev, &data->uart_config); - - uart_hw->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS; - uart_hw->lcr_h |= UART_UARTLCR_H_FEN_BITS; - - uart_hw->dmacr = UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS; - - /* - * initialize uart_config with hardware reset values - * https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart page:431 - * data bits set default to 8 instead of hardware reset 5 to increase compatibility. - */ - data->uart_config.data_bits = UART_CFG_DATA_BITS_8; - data->uart_config.parity = UART_CFG_PARITY_NONE; - data->uart_config.stop_bits = UART_CFG_STOP_BITS_1; - uart_rpi_set_format(dev, &data->uart_config); - uart_hw->dr = 0U; - - if (data->uart_config.flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS) { - uart_set_hw_flow((uart_inst_t *)uart_hw, true, true); - } - -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - config->irq_config_func(dev); -#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ - - return 0; -} - -static int uart_rpi_config_get(const struct device *dev, struct uart_config *cfg) -{ - struct uart_rpi_data *data = dev->data; - - *cfg = data->uart_config; - - return 0; -} - -static int uart_rpi_configure(const struct device *dev, const struct uart_config *cfg) -{ - struct uart_rpi_data *data = dev->data; - uint32_t baudrate = 0; - int ret; - - ret = uart_rpi_set_baudrate(dev, cfg->baudrate, &baudrate); - if (ret < 0) { - return ret; - } - - ret = uart_rpi_set_format(dev, cfg); - if (ret < 0) { - return ret; - } - - data->uart_config = *cfg; - return 0; -} - -static int uart_rpi_err_check(const struct device *dev) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - uint32_t data_reg = uart_hw->dr; - int errors = 0; - - if (data_reg & UART_UARTDR_OE_BITS) { - errors |= UART_ERROR_OVERRUN; - } - - if (data_reg & UART_UARTDR_BE_BITS) { - errors |= UART_BREAK; - } - - if (data_reg & UART_UARTDR_PE_BITS) { - errors |= UART_ERROR_PARITY; - } - - if (data_reg & UART_UARTDR_FE_BITS) { - errors |= UART_ERROR_FRAMING; - } - - return errors; -} - -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - -static int uart_rpi_fifo_fill(const struct device *dev, - const uint8_t *tx_data, int len) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - int tx_len = 0; - - while (!(uart_hw->fr & UART_UARTFR_TXFF_BITS) && (len - tx_len) > 0) { - uart_hw->dr = tx_data[tx_len++]; - } - - return tx_len; -} - -static int uart_rpi_fifo_read(const struct device *dev, - uint8_t *rx_data, const int len) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - int rx_len = 0; - - while (!(uart_hw->fr & UART_UARTFR_RXFE_BITS) && (len - rx_len) > 0) { - rx_data[rx_len++] = (uint8_t)uart_hw->dr; - } - - return rx_len; -} - -static void uart_rpi_irq_tx_enable(const struct device *dev) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - - uart_hw->imsc |= UART_UARTIMSC_TXIM_BITS; - uart_hw->ifls &= ~UART_UARTIFLS_TXIFLSEL_BITS; -} - -static void uart_rpi_irq_tx_disable(const struct device *dev) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - - uart_hw->imsc &= ~UART_UARTIMSC_TXIM_BITS; -} - -static int uart_rpi_irq_tx_ready(const struct device *dev) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - - return (uart_hw->mis & UART_UARTMIS_TXMIS_BITS) == UART_UARTMIS_TXMIS_BITS; -} - -static void uart_rpi_irq_rx_enable(const struct device *dev) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - - uart_hw->imsc |= UART_UARTIMSC_RXIM_BITS; - uart_hw->ifls &= ~UART_UARTIFLS_RXIFLSEL_BITS; -} - -static void uart_rpi_irq_rx_disable(const struct device *dev) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - - uart_hw->imsc &= ~UART_UARTIMSC_RXIM_BITS; -} - -static int uart_rpi_irq_tx_complete(const struct device *dev) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - - return !!(uart_hw->fr & UART_UARTFR_TXFE_BITS) && !(uart_hw->fr & UART_UARTFR_BUSY_BITS); -} - -static int uart_rpi_irq_rx_ready(const struct device *dev) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - - return (uart_hw->mis & UART_UARTMIS_RXMIS_BITS) == UART_UARTMIS_RXMIS_BITS; -} - -static void uart_rpi_irq_err_enable(const struct device *dev) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - - uart_hw->imsc |= (UART_UARTIMSC_OEIM_BITS | - UART_UARTIMSC_BEIM_BITS | - UART_UARTIMSC_PEIM_BITS | - UART_UARTIMSC_FEIM_BITS | - UART_UARTIMSC_RTIM_BITS); -} - -static void uart_rpi_irq_err_disable(const struct device *dev) -{ - const struct uart_rpi_config * const config = dev->config; - uart_hw_t * const uart_hw = config->uart_regs; - - uart_hw->imsc &= ~(UART_UARTIMSC_OEIM_BITS | - UART_UARTIMSC_BEIM_BITS | - UART_UARTIMSC_PEIM_BITS | - UART_UARTIMSC_FEIM_BITS | - UART_UARTIMSC_RTIM_BITS); -} - -static int uart_rpi_irq_is_pending(const struct device *dev) -{ - return !!(uart_rpi_irq_rx_ready(dev) || uart_rpi_irq_tx_ready(dev)); -} - -static int uart_rpi_irq_update(const struct device *dev) -{ - return 1; -} - -static void uart_rpi_irq_callback_set(const struct device *dev, - uart_irq_callback_user_data_t cb, - void *cb_data) -{ - struct uart_rpi_data * const data = dev->data; - - data->irq_cb = cb; - data->irq_cb_data = cb_data; -} - -static void uart_rpi_isr(const struct device *dev) -{ - struct uart_rpi_data * const data = dev->data; - - if (data->irq_cb) { - data->irq_cb(dev, data->irq_cb_data); - } -} - -#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ - -static const struct uart_driver_api uart_rpi_driver_api = { - .poll_in = uart_rpi_poll_in, - .poll_out = uart_rpi_poll_out, - .err_check = uart_rpi_err_check, -#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE - .configure = uart_rpi_configure, - .config_get = uart_rpi_config_get, -#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - .fifo_fill = uart_rpi_fifo_fill, - .fifo_read = uart_rpi_fifo_read, - .irq_tx_enable = uart_rpi_irq_tx_enable, - .irq_tx_disable = uart_rpi_irq_tx_disable, - .irq_tx_ready = uart_rpi_irq_tx_ready, - .irq_rx_enable = uart_rpi_irq_rx_enable, - .irq_rx_disable = uart_rpi_irq_rx_disable, - .irq_tx_complete = uart_rpi_irq_tx_complete, - .irq_rx_ready = uart_rpi_irq_rx_ready, - .irq_err_enable = uart_rpi_irq_err_enable, - .irq_err_disable = uart_rpi_irq_err_disable, - .irq_is_pending = uart_rpi_irq_is_pending, - .irq_update = uart_rpi_irq_update, - .irq_callback_set = uart_rpi_irq_callback_set, -#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ -}; - -#ifdef CONFIG_UART_INTERRUPT_DRIVEN -#define RPI_UART_IRQ_CONFIG_INIT(idx) \ - .irq_config_func = uart##idx##_rpi_irq_config_func -#else -#define RPI_UART_IRQ_CONFIG_INIT(idx) -#endif /* CONFIG_UART_INTERRUPT_DRIVEN*/ - -#define RPI_UART_INIT(idx) \ - PINCTRL_DT_INST_DEFINE(idx); \ - \ - static void uart##idx##_rpi_irq_config_func(const struct device *port) \ - { \ - IRQ_CONNECT(DT_INST_IRQN(idx), \ - DT_INST_IRQ(idx, priority), \ - uart_rpi_isr, \ - DEVICE_DT_INST_GET(idx), 0); \ - irq_enable(DT_INST_IRQN(idx)); \ - } \ - \ - static const struct uart_rpi_config uart##idx##_rpi_config = { \ - .uart_regs = (uart_hw_t *const)DT_INST_REG_ADDR(idx), \ - .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \ - .reset = RESET_DT_SPEC_INST_GET(idx), \ - .clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \ - .clk_id = (clock_control_subsys_t)DT_INST_PHA_BY_IDX(idx, clocks, 0, clk_id), \ - RPI_UART_IRQ_CONFIG_INIT(idx), \ - }; \ - \ - static struct uart_rpi_data uart##idx##_rpi_data = { \ - .uart_config.baudrate = DT_INST_PROP(idx, current_speed), \ - .uart_config.flow_ctrl = DT_INST_PROP(idx, hw_flow_control) \ - ? UART_CFG_FLOW_CTRL_RTS_CTS \ - : UART_CFG_FLOW_CTRL_NONE, \ - }; \ - \ - DEVICE_DT_INST_DEFINE(idx, &uart_rpi_init, \ - NULL, &uart##idx##_rpi_data, \ - &uart##idx##_rpi_config, PRE_KERNEL_1, \ - CONFIG_SERIAL_INIT_PRIORITY, \ - &uart_rpi_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(RPI_UART_INIT) diff --git a/dts/arm/rpi_pico/rp2040.dtsi b/dts/arm/rpi_pico/rp2040.dtsi index db7b12ce40b..a33d1805c09 100644 --- a/dts/arm/rpi_pico/rp2040.dtsi +++ b/dts/arm/rpi_pico/rp2040.dtsi @@ -240,7 +240,7 @@ }; uart0: uart@40034000 { - compatible = "raspberrypi,pico-uart"; + compatible = "raspberrypi,pico-uart", "arm,pl011"; reg = <0x40034000 DT_SIZE_K(4)>; clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>; resets = <&reset RPI_PICO_RESETS_RESET_UART0>; @@ -250,7 +250,7 @@ }; uart1: uart@40038000 { - compatible = "raspberrypi,pico-uart"; + compatible = "raspberrypi,pico-uart", "arm,pl011"; reg = <0x40038000 DT_SIZE_K(4)>; clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>; resets = <&reset RPI_PICO_RESETS_RESET_UART1>; From 033bf60776c2c0ab2532aa764c4c6b29ccbe0bbe Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Wed, 3 Apr 2024 23:55:13 +0800 Subject: [PATCH 2082/2402] subsys/mgmt/hawkbit: use `zsock_setsockopt` instead of `setsockopt` `setsockopt` is enabled by `CONFIG_POSIX_API`, use `zsock_setsockopt` instead, otherwise there will be a compilation error if `CONFIG_NET_SOCKETS_SOCKOPT_TLS` is enabled. Signed-off-by: Yong Cong Sin --- subsys/mgmt/hawkbit/hawkbit.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c index 37a98717a7a..cbff846316d 100644 --- a/subsys/mgmt/hawkbit/hawkbit.c +++ b/subsys/mgmt/hawkbit/hawkbit.c @@ -235,14 +235,14 @@ static bool start_http_client(void) CA_CERTIFICATE_TAG, }; - if (setsockopt(hb_context.sock, SOL_TLS, TLS_SEC_TAG_LIST, sec_tag_opt, - sizeof(sec_tag_opt)) < 0) { + if (zsock_setsockopt(hb_context.sock, SOL_TLS, TLS_SEC_TAG_LIST, sec_tag_opt, + sizeof(sec_tag_opt)) < 0) { LOG_ERR("Failed to set TLS_TAG option"); goto err_sock; } - if (setsockopt(hb_context.sock, SOL_TLS, TLS_HOSTNAME, CONFIG_HAWKBIT_SERVER, - sizeof(CONFIG_HAWKBIT_SERVER)) < 0) { + if (zsock_setsockopt(hb_context.sock, SOL_TLS, TLS_HOSTNAME, CONFIG_HAWKBIT_SERVER, + sizeof(CONFIG_HAWKBIT_SERVER)) < 0) { goto err_sock; } #endif From b41db52ffec78bd17ec1be333ce7077d5eb52937 Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Wed, 3 Apr 2024 23:56:27 +0800 Subject: [PATCH 2083/2402] samples: subsys: mgmt: hawkbit: test more configurations Exercise each and every hawkBit's Kconfig switches. Signed-off-by: Yong Cong Sin --- samples/subsys/mgmt/hawkbit/sample.yaml | 34 +++++++++++++++++++------ 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/samples/subsys/mgmt/hawkbit/sample.yaml b/samples/subsys/mgmt/hawkbit/sample.yaml index 5e161132099..9644d620d52 100644 --- a/samples/subsys/mgmt/hawkbit/sample.yaml +++ b/samples/subsys/mgmt/hawkbit/sample.yaml @@ -1,14 +1,32 @@ common: filter: CONFIG_FULL_LIBC_SUPPORTED + harness: net + tags: net + depends_on: netif + build_only: true + platform_allow: frdm_k64f + integration_platforms: + - frdm_k64f sample: description: hawkBit Firmware Over-the-Air (FOTA) name: hawkbit tests: - sample.net.hawkbit: - harness: net - tags: net - depends_on: netif - build_only: true - platform_allow: frdm_k64f - integration_platforms: - - frdm_k64f + sample.net.hawkbit.default: {} + sample.net.hawkbit.manual: + extra_configs: + - CONFIG_HAWKBIT_MANUAL=y + sample.net.hawkbit.shell: + extra_configs: + - CONFIG_SHELL=y + - CONFIG_HAWKBIT_SHELL=y + sample.net.hawkbit.ddi.target: + extra_configs: + - CONFIG_HAWKBIT_DDI_TARGET_SECURITY=y + - CONFIG_HAWKBIT_DDI_SECURITY_TOKEN="abcd1234" + sample.net.hawkbit.ddi.gateway: + extra_configs: + - CONFIG_HAWKBIT_DDI_GATEWAY_SECURITY=y + - CONFIG_HAWKBIT_DDI_SECURITY_TOKEN="abcd1234" + sample.net.hawkbit.tls: + extra_configs: + - CONFIG_NET_SOCKETS_SOCKOPT_TLS=y From 37dfafe3f4b375c74582881123368def8ec47c94 Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Thu, 4 Apr 2024 00:03:02 +0800 Subject: [PATCH 2084/2402] subsys/mgmt/hawkbit: rearrange headers The order of the headers could use some cleanup. I'm rearranging them alphabetically. Signed-off-by: Yong Cong Sin --- subsys/mgmt/hawkbit/hawkbit.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c index cbff846316d..d986b05f571 100644 --- a/subsys/mgmt/hawkbit/hawkbit.c +++ b/subsys/mgmt/hawkbit/hawkbit.c @@ -8,36 +8,36 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include - -LOG_MODULE_REGISTER(hawkbit, CONFIG_HAWKBIT_LOG_LEVEL); - #include -#include -#include #include -#include +#include + #include -#include -#include -#include -#include #include -#include -#include +#include +#include +#include #include +#include +#include +#include +#include +#include +#include #include +#include -#include "hawkbit_priv.h" #include "hawkbit_device.h" -#include #include "hawkbit_firmware.h" +#include "hawkbit_priv.h" #if defined(CONFIG_NET_SOCKETS_SOCKOPT_TLS) #define CA_CERTIFICATE_TAG 1 #include #endif +LOG_MODULE_REGISTER(hawkbit, CONFIG_HAWKBIT_LOG_LEVEL); + #define ADDRESS_ID 1 #define CANCEL_BASE_SIZE 50 From 5a0ecb964186320828625b0fd2f2ddd889cc28ab Mon Sep 17 00:00:00 2001 From: Dominik Ermel Date: Wed, 3 Apr 2024 17:05:32 +0200 Subject: [PATCH 2085/2402] flash: Move dependency on FLASH_PAGE_LAYOUT where it belongs The commit adds dependency on Kconfig FLASH_PAGE_LAYOUT to subsystems that really require it: FCB, NVS, LittleFS and removes direct selection from '*.conf' files where no longer needed. Signed-off-by: Dominik Ermel --- drivers/flash/Kconfig.sam | 1 - drivers/flash/Kconfig.stm32 | 1 - drivers/flash/Kconfig.stm32_ospi | 1 - drivers/flash/Kconfig.stm32_qspi | 1 - samples/bluetooth/direct_adv/prj.conf | 1 - samples/bluetooth/mesh_demo/prj.conf | 1 - samples/bluetooth/mesh_provisioner/prj.conf | 1 - samples/bluetooth/peripheral/prj.conf | 1 - samples/bluetooth/peripheral_accept_list/prj.conf | 1 - samples/bluetooth/peripheral_hids/prj.conf | 1 - samples/boards/nrf/mesh/onoff-app/prj.conf | 1 - samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/prj.conf | 1 - samples/boards/reel_board/mesh_badge/prj.conf | 1 - samples/drivers/soc_flash_nand/prj.conf | 1 - samples/drivers/soc_flash_nrf/prj.conf | 1 - samples/subsys/fs/format/prj.conf | 1 - samples/subsys/fs/littlefs/prj.conf | 1 - samples/subsys/nvs/prj.conf | 1 - samples/subsys/settings/prj.conf | 1 - samples/subsys/shell/fs/prj.conf | 1 - samples/subsys/shell/fs/prj_flash_load.conf | 1 - samples/subsys/usb/cdc_acm/overlay-composite-cdc-dfu.conf | 1 - samples/subsys/usb/dfu/prj.conf | 1 - subsys/fs/fcb/Kconfig | 1 + subsys/fs/nvs/Kconfig | 2 ++ subsys/net/l2/openthread/Kconfig | 1 - subsys/testsuite/Kconfig | 1 - tests/bluetooth/mesh/blob_io_flash/prj.conf | 1 - tests/bluetooth/mesh_shell/prj.conf | 1 - tests/bluetooth/shell/log.conf | 1 - tests/bluetooth/shell/prj.conf | 1 - tests/bsim/bluetooth/host/att/long_read/prj.conf | 1 - tests/bsim/bluetooth/host/att/open_close/prj.conf | 1 - tests/bsim/bluetooth/host/gatt/ccc_store/prj.conf | 1 - tests/bsim/bluetooth/host/gatt/ccc_store/prj_2.conf | 1 - tests/bsim/bluetooth/host/gatt/sc_indicate/prj.conf | 1 - tests/bsim/bluetooth/host/id/settings/prj.conf | 1 - tests/bsim/bluetooth/host/privacy/peripheral/prj.conf | 1 - .../bsim/bluetooth/host/privacy/peripheral/prj_rpa_expired.conf | 1 - .../bsim/bluetooth/host/privacy/peripheral/prj_rpa_sharing.conf | 1 - tests/bsim/bluetooth/host/security/ccc_update/prj.conf | 1 - tests/bsim/bluetooth/host/security/ccc_update/prj_2.conf | 1 - .../bluetooth/host/security/security_changed_callback/prj.conf | 1 - tests/bsim/bluetooth/mesh/overlay_pst.conf | 1 - tests/subsys/fs/fcb/prj.conf | 1 - tests/subsys/fs/littlefs/prj.conf | 1 - tests/subsys/fs/multi-fs/prj.conf | 1 - tests/subsys/fs/multi-fs/prj_fs_shell.conf | 1 - tests/subsys/fs/nvs/prj.conf | 1 - tests/subsys/settings/fcb/prj.conf | 1 - tests/subsys/settings/fcb_init/prj.conf | 1 - tests/subsys/settings/file/prj.conf | 1 - tests/subsys/settings/functional/fcb/prj.conf | 1 - tests/subsys/settings/functional/file/prj.conf | 1 - tests/subsys/settings/functional/nvs/prj.conf | 1 - tests/subsys/settings/nvs/prj.conf | 1 - tests/subsys/storage/stream/stream_flash/prj.conf | 1 - 57 files changed, 3 insertions(+), 55 deletions(-) diff --git a/drivers/flash/Kconfig.sam b/drivers/flash/Kconfig.sam index 64df895bd6a..bb014d65279 100644 --- a/drivers/flash/Kconfig.sam +++ b/drivers/flash/Kconfig.sam @@ -7,7 +7,6 @@ config SOC_FLASH_SAM bool "Atmel SAM flash driver" default y depends on DT_HAS_ATMEL_SAM_FLASH_CONTROLLER_ENABLED - select FLASH_PAGE_LAYOUT select FLASH_HAS_PAGE_LAYOUT select FLASH_HAS_DRIVER_ENABLED select MPU_ALLOW_FLASH_WRITE if ARM_MPU diff --git a/drivers/flash/Kconfig.stm32 b/drivers/flash/Kconfig.stm32 index a452ab8b98d..1ba8c33a7ec 100644 --- a/drivers/flash/Kconfig.stm32 +++ b/drivers/flash/Kconfig.stm32 @@ -11,7 +11,6 @@ config SOC_FLASH_STM32 depends on DT_HAS_ST_STM32_FLASH_CONTROLLER_ENABLED select FLASH_HAS_DRIVER_ENABLED default y - select FLASH_PAGE_LAYOUT select FLASH_HAS_PAGE_LAYOUT select MPU_ALLOW_FLASH_WRITE if ARM_MPU select USE_STM32_HAL_FLASH if BT_STM32WBA diff --git a/drivers/flash/Kconfig.stm32_ospi b/drivers/flash/Kconfig.stm32_ospi index c61f29d44b0..305fcfac76d 100644 --- a/drivers/flash/Kconfig.stm32_ospi +++ b/drivers/flash/Kconfig.stm32_ospi @@ -16,7 +16,6 @@ config FLASH_STM32_OSPI select USE_STM32_HAL_MDMA if SOC_SERIES_STM32H7X select FLASH_HAS_DRIVER_ENABLED select FLASH_JESD216 - select FLASH_PAGE_LAYOUT select FLASH_HAS_PAGE_LAYOUT select DMA if $(DT_STM32_OCTOSPI_1_HAS_DMA) || $(DT_STM32_OCTOSPI_2_HAS_DMA) select USE_STM32_HAL_DMA if $(DT_STM32_OCTOSPI_1_HAS_DMA) || \ diff --git a/drivers/flash/Kconfig.stm32_qspi b/drivers/flash/Kconfig.stm32_qspi index 6ba00c81c9e..c97be5ef354 100644 --- a/drivers/flash/Kconfig.stm32_qspi +++ b/drivers/flash/Kconfig.stm32_qspi @@ -14,7 +14,6 @@ config FLASH_STM32_QSPI select USE_STM32_HAL_MDMA if SOC_SERIES_STM32H7X select FLASH_HAS_DRIVER_ENABLED select FLASH_JESD216 - select FLASH_PAGE_LAYOUT select FLASH_HAS_PAGE_LAYOUT select DMA if $(DT_STM32_QUADSPI_HAS_DMA) select USE_STM32_HAL_DMA if $(DT_STM32_QUADSPI_HAS_DMA) diff --git a/samples/bluetooth/direct_adv/prj.conf b/samples/bluetooth/direct_adv/prj.conf index 6a633da1923..2af54670b51 100644 --- a/samples/bluetooth/direct_adv/prj.conf +++ b/samples/bluetooth/direct_adv/prj.conf @@ -15,7 +15,6 @@ CONFIG_BT_DEVICE_APPEARANCE=833 CONFIG_BT_KEYS_OVERWRITE_OLDEST=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/samples/bluetooth/mesh_demo/prj.conf b/samples/bluetooth/mesh_demo/prj.conf index 1fe22df04ef..df67555b021 100644 --- a/samples/bluetooth/mesh_demo/prj.conf +++ b/samples/bluetooth/mesh_demo/prj.conf @@ -27,7 +27,6 @@ CONFIG_BT_MESH_LOOPBACK_BUFS=8 CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/samples/bluetooth/mesh_provisioner/prj.conf b/samples/bluetooth/mesh_provisioner/prj.conf index 341dd49ed2e..71cf6d6a14d 100644 --- a/samples/bluetooth/mesh_provisioner/prj.conf +++ b/samples/bluetooth/mesh_provisioner/prj.conf @@ -41,7 +41,6 @@ CONFIG_BT_MESH_CDB_APP_KEY_COUNT=3 CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/samples/bluetooth/peripheral/prj.conf b/samples/bluetooth/peripheral/prj.conf index 9946a3107bc..5d577265d6e 100644 --- a/samples/bluetooth/peripheral/prj.conf +++ b/samples/bluetooth/peripheral/prj.conf @@ -20,7 +20,6 @@ CONFIG_BT_DEVICE_NAME_MAX=65 CONFIG_BT_KEYS_OVERWRITE_OLDEST=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/samples/bluetooth/peripheral_accept_list/prj.conf b/samples/bluetooth/peripheral_accept_list/prj.conf index 3395353388a..563ee758d2e 100644 --- a/samples/bluetooth/peripheral_accept_list/prj.conf +++ b/samples/bluetooth/peripheral_accept_list/prj.conf @@ -16,7 +16,6 @@ CONFIG_BT_KEYS_OVERWRITE_OLDEST=y CONFIG_BT_SETTINGS=y CONFIG_BT_FILTER_ACCEPT_LIST=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/samples/bluetooth/peripheral_hids/prj.conf b/samples/bluetooth/peripheral_hids/prj.conf index dd21313836c..10274a865d2 100644 --- a/samples/bluetooth/peripheral_hids/prj.conf +++ b/samples/bluetooth/peripheral_hids/prj.conf @@ -12,7 +12,6 @@ CONFIG_BT_DEVICE_APPEARANCE=962 CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/samples/boards/nrf/mesh/onoff-app/prj.conf b/samples/boards/nrf/mesh/onoff-app/prj.conf index 6c3a08f44ea..0fdf19b8cfc 100644 --- a/samples/boards/nrf/mesh/onoff-app/prj.conf +++ b/samples/boards/nrf/mesh/onoff-app/prj.conf @@ -6,7 +6,6 @@ CONFIG_GPIO=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/prj.conf b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/prj.conf index e617afed89f..b5a01e39e56 100644 --- a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/prj.conf +++ b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/prj.conf @@ -4,7 +4,6 @@ CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096 CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/samples/boards/reel_board/mesh_badge/prj.conf b/samples/boards/reel_board/mesh_badge/prj.conf index 833ca55da34..cce6826abb8 100644 --- a/samples/boards/reel_board/mesh_badge/prj.conf +++ b/samples/boards/reel_board/mesh_badge/prj.conf @@ -64,7 +64,6 @@ CONFIG_CHARACTER_FRAMEBUFFER=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/samples/drivers/soc_flash_nand/prj.conf b/samples/drivers/soc_flash_nand/prj.conf index 463cd27a152..53a45c34889 100644 --- a/samples/drivers/soc_flash_nand/prj.conf +++ b/samples/drivers/soc_flash_nand/prj.conf @@ -6,5 +6,4 @@ CONFIG_HEAP_MEM_POOL_SIZE=363840 # Enable Flash CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_LOG=y diff --git a/samples/drivers/soc_flash_nrf/prj.conf b/samples/drivers/soc_flash_nrf/prj.conf index 48e64121b6a..4a6b0a51c56 100644 --- a/samples/drivers/soc_flash_nrf/prj.conf +++ b/samples/drivers/soc_flash_nrf/prj.conf @@ -1,6 +1,5 @@ CONFIG_STDOUT_CONSOLE=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_MPU_ALLOW_FLASH_WRITE=y CONFIG_SOC_FLASH_NRF_EMULATE_ONE_BYTE_WRITE_ACCESS=y CONFIG_FCB=y diff --git a/samples/subsys/fs/format/prj.conf b/samples/subsys/fs/format/prj.conf index e7dded045d5..8df386705d2 100644 --- a/samples/subsys/fs/format/prj.conf +++ b/samples/subsys/fs/format/prj.conf @@ -3,7 +3,6 @@ CONFIG_LOG_MODE_MINIMAL=y CONFIG_FLASH=y CONFIG_FLASH_MAP=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FILE_SYSTEM=y CONFIG_FILE_SYSTEM_MKFS=y diff --git a/samples/subsys/fs/littlefs/prj.conf b/samples/subsys/fs/littlefs/prj.conf index 673735fb0fd..9c0d25926bb 100644 --- a/samples/subsys/fs/littlefs/prj.conf +++ b/samples/subsys/fs/littlefs/prj.conf @@ -18,7 +18,6 @@ CONFIG_LOG_MODE_MINIMAL=y CONFIG_FLASH=y CONFIG_FLASH_MAP=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FILE_SYSTEM=y CONFIG_FILE_SYSTEM_LITTLEFS=y diff --git a/samples/subsys/nvs/prj.conf b/samples/subsys/nvs/prj.conf index b0b5e3041bd..17bcf7fb2e3 100644 --- a/samples/subsys/nvs/prj.conf +++ b/samples/subsys/nvs/prj.conf @@ -1,5 +1,4 @@ CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_NVS=y CONFIG_LOG=y diff --git a/samples/subsys/settings/prj.conf b/samples/subsys/settings/prj.conf index a37cf73ad72..25c66253846 100644 --- a/samples/subsys/settings/prj.conf +++ b/samples/subsys/settings/prj.conf @@ -1,6 +1,5 @@ CONFIG_STDOUT_CONSOLE=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_SETTINGS=y diff --git a/samples/subsys/shell/fs/prj.conf b/samples/subsys/shell/fs/prj.conf index 1f2863e0038..43bedbd85df 100644 --- a/samples/subsys/shell/fs/prj.conf +++ b/samples/subsys/shell/fs/prj.conf @@ -14,4 +14,3 @@ CONFIG_FILE_SYSTEM_SHELL=y CONFIG_FILE_SYSTEM_LITTLEFS=y CONFIG_FLASH_MAP=y -CONFIG_FLASH_PAGE_LAYOUT=y diff --git a/samples/subsys/shell/fs/prj_flash_load.conf b/samples/subsys/shell/fs/prj_flash_load.conf index ae5e4d727e1..9910dd096ec 100644 --- a/samples/subsys/shell/fs/prj_flash_load.conf +++ b/samples/subsys/shell/fs/prj_flash_load.conf @@ -14,4 +14,3 @@ CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=128 CONFIG_FILE_SYSTEM_LITTLEFS=y CONFIG_FLASH_MAP=y -CONFIG_FLASH_PAGE_LAYOUT=y diff --git a/samples/subsys/usb/cdc_acm/overlay-composite-cdc-dfu.conf b/samples/subsys/usb/cdc_acm/overlay-composite-cdc-dfu.conf index e1fc3c9a994..35eeca22f4d 100644 --- a/samples/subsys/usb/cdc_acm/overlay-composite-cdc-dfu.conf +++ b/samples/subsys/usb/cdc_acm/overlay-composite-cdc-dfu.conf @@ -9,5 +9,4 @@ CONFIG_USB_DFU_CLASS=y CONFIG_FLASH=y CONFIG_IMG_MANAGER=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_BOOTLOADER_MCUBOOT=y diff --git a/samples/subsys/usb/dfu/prj.conf b/samples/subsys/usb/dfu/prj.conf index c6a84a554bd..6bf6f1ee310 100644 --- a/samples/subsys/usb/dfu/prj.conf +++ b/samples/subsys/usb/dfu/prj.conf @@ -9,7 +9,6 @@ CONFIG_FLASH=y CONFIG_FLASH_MAP=y CONFIG_STREAM_FLASH=y CONFIG_IMG_MANAGER=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_LOG=y CONFIG_USB_DRIVER_LOG_LEVEL_ERR=y CONFIG_USB_DEVICE_LOG_LEVEL_ERR=y diff --git a/subsys/fs/fcb/Kconfig b/subsys/fs/fcb/Kconfig index 50ddb7009b2..442a649c1cb 100644 --- a/subsys/fs/fcb/Kconfig +++ b/subsys/fs/fcb/Kconfig @@ -11,6 +11,7 @@ config FCB bool "Flash Circular Buffer support" depends on FLASH_MAP select CRC + select FLASH_PAGE_LAYOUT help Enable support of Flash Circular Buffer. diff --git a/subsys/fs/nvs/Kconfig b/subsys/fs/nvs/Kconfig index de4f282ee98..209e2ad29a6 100644 --- a/subsys/fs/nvs/Kconfig +++ b/subsys/fs/nvs/Kconfig @@ -5,7 +5,9 @@ config NVS bool "Non-volatile Storage" + depends on FLASH select CRC + select FLASH_PAGE_LAYOUT help Enable support of Non-volatile Storage. diff --git a/subsys/net/l2/openthread/Kconfig b/subsys/net/l2/openthread/Kconfig index aa7e03b8204..ef71e411b4e 100644 --- a/subsys/net/l2/openthread/Kconfig +++ b/subsys/net/l2/openthread/Kconfig @@ -16,7 +16,6 @@ menuconfig NET_L2_OPENTHREAD select OPENTHREAD imply FLASH - imply FLASH_PAGE_LAYOUT imply FLASH_MAP imply MPU_ALLOW_FLASH_WRITE imply NVS diff --git a/subsys/testsuite/Kconfig b/subsys/testsuite/Kconfig index 266b8533025..2ae331eb438 100644 --- a/subsys/testsuite/Kconfig +++ b/subsys/testsuite/Kconfig @@ -164,7 +164,6 @@ config TEST_FLASH_DRIVERS bool "Test flash drivers" depends on BOARD_QEMU_X86 select FLASH_HAS_DRIVER_ENABLED - select FLASH_HAS_PAGE_LAYOUT help This option will help test the flash drivers. This should be enabled only when using qemu_x86. diff --git a/tests/bluetooth/mesh/blob_io_flash/prj.conf b/tests/bluetooth/mesh/blob_io_flash/prj.conf index 1e7864aa05d..7db7efc16cd 100644 --- a/tests/bluetooth/mesh/blob_io_flash/prj.conf +++ b/tests/bluetooth/mesh/blob_io_flash/prj.conf @@ -1,6 +1,5 @@ CONFIG_ZTEST=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_FLASH_AREA_CHECK_INTEGRITY=y CONFIG_FLASH_SIMULATOR=y diff --git a/tests/bluetooth/mesh_shell/prj.conf b/tests/bluetooth/mesh_shell/prj.conf index 6535b77c3ab..9ed15616cab 100644 --- a/tests/bluetooth/mesh_shell/prj.conf +++ b/tests/bluetooth/mesh_shell/prj.conf @@ -11,7 +11,6 @@ CONFIG_SHELL_CMD_BUFF_SIZE=128 CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/tests/bluetooth/shell/log.conf b/tests/bluetooth/shell/log.conf index 6c278246e33..69a1d5d5533 100644 --- a/tests/bluetooth/shell/log.conf +++ b/tests/bluetooth/shell/log.conf @@ -35,7 +35,6 @@ CONFIG_LOG=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/tests/bluetooth/shell/prj.conf b/tests/bluetooth/shell/prj.conf index 185167de1d1..605cbc61c19 100644 --- a/tests/bluetooth/shell/prj.conf +++ b/tests/bluetooth/shell/prj.conf @@ -33,7 +33,6 @@ CONFIG_BT_GATT_AUTO_DISCOVER_CCC=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/tests/bsim/bluetooth/host/att/long_read/prj.conf b/tests/bsim/bluetooth/host/att/long_read/prj.conf index 1e5e8dc8b41..ddcef1bc3fe 100644 --- a/tests/bsim/bluetooth/host/att/long_read/prj.conf +++ b/tests/bsim/bluetooth/host/att/long_read/prj.conf @@ -18,7 +18,6 @@ CONFIG_BT_SMP=y CONFIG_BT_TESTING=y CONFIG_BT=y CONFIG_FLASH_MAP=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH=y CONFIG_LOG_BACKEND_FORMAT_TIMESTAMP=n CONFIG_LOG_RUNTIME_FILTERING=y diff --git a/tests/bsim/bluetooth/host/att/open_close/prj.conf b/tests/bsim/bluetooth/host/att/open_close/prj.conf index f898c5238cc..bee886a30e2 100644 --- a/tests/bsim/bluetooth/host/att/open_close/prj.conf +++ b/tests/bsim/bluetooth/host/att/open_close/prj.conf @@ -18,7 +18,6 @@ CONFIG_BT_SMP=y CONFIG_BT_TESTING=y CONFIG_BT=y CONFIG_FLASH_MAP=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH=y CONFIG_LOG_BACKEND_FORMAT_TIMESTAMP=n CONFIG_LOG_RUNTIME_FILTERING=y diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/prj.conf b/tests/bsim/bluetooth/host/gatt/ccc_store/prj.conf index 1fbddd5c271..7aec13ace8e 100644 --- a/tests/bsim/bluetooth/host/gatt/ccc_store/prj.conf +++ b/tests/bsim/bluetooth/host/gatt/ccc_store/prj.conf @@ -14,7 +14,6 @@ CONFIG_BT_SMP=y CONFIG_SETTINGS=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_NVS=y CONFIG_FLASH_MAP=y CONFIG_SETTINGS_NVS=y diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/prj_2.conf b/tests/bsim/bluetooth/host/gatt/ccc_store/prj_2.conf index fffdcbcf1cc..82fa0d0c155 100644 --- a/tests/bsim/bluetooth/host/gatt/ccc_store/prj_2.conf +++ b/tests/bsim/bluetooth/host/gatt/ccc_store/prj_2.conf @@ -14,7 +14,6 @@ CONFIG_BT_SMP=y CONFIG_SETTINGS=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_NVS=y CONFIG_FLASH_MAP=y CONFIG_SETTINGS_NVS=y diff --git a/tests/bsim/bluetooth/host/gatt/sc_indicate/prj.conf b/tests/bsim/bluetooth/host/gatt/sc_indicate/prj.conf index 7edaf36d10e..f2513b92356 100644 --- a/tests/bsim/bluetooth/host/gatt/sc_indicate/prj.conf +++ b/tests/bsim/bluetooth/host/gatt/sc_indicate/prj.conf @@ -12,7 +12,6 @@ CONFIG_BT_GATT_CLIENT=y CONFIG_SETTINGS=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_NVS=y CONFIG_FLASH_MAP=y CONFIG_SETTINGS_NVS=y diff --git a/tests/bsim/bluetooth/host/id/settings/prj.conf b/tests/bsim/bluetooth/host/id/settings/prj.conf index 4559ba6f8f9..99efcbc8966 100644 --- a/tests/bsim/bluetooth/host/id/settings/prj.conf +++ b/tests/bsim/bluetooth/host/id/settings/prj.conf @@ -7,7 +7,6 @@ CONFIG_LOG=y CONFIG_BT_ID_MAX=2 CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/prj.conf b/tests/bsim/bluetooth/host/privacy/peripheral/prj.conf index 9113a44382b..d7295596ac3 100644 --- a/tests/bsim/bluetooth/host/privacy/peripheral/prj.conf +++ b/tests/bsim/bluetooth/host/privacy/peripheral/prj.conf @@ -13,7 +13,6 @@ CONFIG_BT_CTLR_ADV_DATA_BUF_MAX=3 CONFIG_BT_ID_MAX=3 CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_expired.conf b/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_expired.conf index dcab4bc5686..a357a38df39 100644 --- a/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_expired.conf +++ b/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_expired.conf @@ -13,7 +13,6 @@ CONFIG_BT_CTLR_ADV_DATA_BUF_MAX=4 CONFIG_BT_ID_MAX=3 CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_sharing.conf b/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_sharing.conf index 208efda9c7f..2c4195b169d 100644 --- a/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_sharing.conf +++ b/tests/bsim/bluetooth/host/privacy/peripheral/prj_rpa_sharing.conf @@ -13,7 +13,6 @@ CONFIG_BT_CTLR_ADV_DATA_BUF_MAX=3 CONFIG_BT_ID_MAX=3 CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y diff --git a/tests/bsim/bluetooth/host/security/ccc_update/prj.conf b/tests/bsim/bluetooth/host/security/ccc_update/prj.conf index 3d727bf31de..87cc06cde9e 100644 --- a/tests/bsim/bluetooth/host/security/ccc_update/prj.conf +++ b/tests/bsim/bluetooth/host/security/ccc_update/prj.conf @@ -16,7 +16,6 @@ CONFIG_BT_SMP=y CONFIG_SETTINGS=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_NVS=y CONFIG_FLASH_MAP=y CONFIG_SETTINGS_NVS=y diff --git a/tests/bsim/bluetooth/host/security/ccc_update/prj_2.conf b/tests/bsim/bluetooth/host/security/ccc_update/prj_2.conf index ce1300a7439..cab86865147 100644 --- a/tests/bsim/bluetooth/host/security/ccc_update/prj_2.conf +++ b/tests/bsim/bluetooth/host/security/ccc_update/prj_2.conf @@ -18,7 +18,6 @@ CONFIG_BT_SMP=y CONFIG_SETTINGS=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_NVS=y CONFIG_FLASH_MAP=y CONFIG_SETTINGS_NVS=y diff --git a/tests/bsim/bluetooth/host/security/security_changed_callback/prj.conf b/tests/bsim/bluetooth/host/security/security_changed_callback/prj.conf index abf1bd7ffb7..25422630f25 100644 --- a/tests/bsim/bluetooth/host/security/security_changed_callback/prj.conf +++ b/tests/bsim/bluetooth/host/security/security_changed_callback/prj.conf @@ -10,7 +10,6 @@ CONFIG_BT_PRIVACY=y CONFIG_SETTINGS=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_NVS=y CONFIG_FLASH_MAP=y CONFIG_SETTINGS_NVS=y diff --git a/tests/bsim/bluetooth/mesh/overlay_pst.conf b/tests/bsim/bluetooth/mesh/overlay_pst.conf index e02c0ec2b93..42c1d0d26ce 100644 --- a/tests/bsim/bluetooth/mesh/overlay_pst.conf +++ b/tests/bsim/bluetooth/mesh/overlay_pst.conf @@ -1,7 +1,6 @@ CONFIG_SETTINGS=y CONFIG_BT_SETTINGS=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y diff --git a/tests/subsys/fs/fcb/prj.conf b/tests/subsys/fs/fcb/prj.conf index c30a352a0e4..7308ffdbf9c 100644 --- a/tests/subsys/fs/fcb/prj.conf +++ b/tests/subsys/fs/fcb/prj.conf @@ -1,7 +1,6 @@ CONFIG_ZTEST=y CONFIG_STDOUT_CONSOLE=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_FCB=y CONFIG_FCB_ALLOW_FIXED_ENDMARKER=y diff --git a/tests/subsys/fs/littlefs/prj.conf b/tests/subsys/fs/littlefs/prj.conf index de33b272ae6..094bf4a9102 100644 --- a/tests/subsys/fs/littlefs/prj.conf +++ b/tests/subsys/fs/littlefs/prj.conf @@ -13,7 +13,6 @@ CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=8192 CONFIG_FLASH=y CONFIG_FLASH_MAP=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_ZTEST=y CONFIG_ZTEST_STACK_SIZE=4096 diff --git a/tests/subsys/fs/multi-fs/prj.conf b/tests/subsys/fs/multi-fs/prj.conf index 287f0363dca..9e8871e074b 100644 --- a/tests/subsys/fs/multi-fs/prj.conf +++ b/tests/subsys/fs/multi-fs/prj.conf @@ -1,6 +1,5 @@ CONFIG_FLASH=y CONFIG_FLASH_MAP=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FILE_SYSTEM=y CONFIG_FILE_SYSTEM_LITTLEFS=y CONFIG_LOG=y diff --git a/tests/subsys/fs/multi-fs/prj_fs_shell.conf b/tests/subsys/fs/multi-fs/prj_fs_shell.conf index 327e2b4f2fb..0f796e27515 100644 --- a/tests/subsys/fs/multi-fs/prj_fs_shell.conf +++ b/tests/subsys/fs/multi-fs/prj_fs_shell.conf @@ -1,6 +1,5 @@ CONFIG_FLASH=y CONFIG_FLASH_MAP=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FILE_SYSTEM=y CONFIG_FILE_SYSTEM_LITTLEFS=y CONFIG_LOG=y diff --git a/tests/subsys/fs/nvs/prj.conf b/tests/subsys/fs/nvs/prj.conf index 7d7f4aec2e9..75740e3df33 100644 --- a/tests/subsys/fs/nvs/prj.conf +++ b/tests/subsys/fs/nvs/prj.conf @@ -4,7 +4,6 @@ CONFIG_STDOUT_CONSOLE=y CONFIG_FLASH=y CONFIG_FLASH_MAP=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_NVS=y CONFIG_LOG=y diff --git a/tests/subsys/settings/fcb/prj.conf b/tests/subsys/settings/fcb/prj.conf index c0091de22ed..851107aa45f 100644 --- a/tests/subsys/settings/fcb/prj.conf +++ b/tests/subsys/settings/fcb/prj.conf @@ -2,7 +2,6 @@ CONFIG_ZTEST=y CONFIG_ZTEST_STACK_SIZE=2048 CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_FCB=y diff --git a/tests/subsys/settings/fcb_init/prj.conf b/tests/subsys/settings/fcb_init/prj.conf index 9652f2c467c..49e4e03c180 100644 --- a/tests/subsys/settings/fcb_init/prj.conf +++ b/tests/subsys/settings/fcb_init/prj.conf @@ -1,6 +1,5 @@ CONFIG_ZTEST=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_FCB=y diff --git a/tests/subsys/settings/file/prj.conf b/tests/subsys/settings/file/prj.conf index 9a61b45661d..bf36966b2f3 100644 --- a/tests/subsys/settings/file/prj.conf +++ b/tests/subsys/settings/file/prj.conf @@ -3,7 +3,6 @@ CONFIG_ZTEST=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_ZTEST_STACK_SIZE=4096 diff --git a/tests/subsys/settings/functional/fcb/prj.conf b/tests/subsys/settings/functional/fcb/prj.conf index 795a225d7fd..e67348a875a 100644 --- a/tests/subsys/settings/functional/fcb/prj.conf +++ b/tests/subsys/settings/functional/fcb/prj.conf @@ -1,6 +1,5 @@ CONFIG_ZTEST=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_FCB=y diff --git a/tests/subsys/settings/functional/file/prj.conf b/tests/subsys/settings/functional/file/prj.conf index fe506f01d99..dd6a82ce321 100644 --- a/tests/subsys/settings/functional/file/prj.conf +++ b/tests/subsys/settings/functional/file/prj.conf @@ -2,7 +2,6 @@ CONFIG_ZTEST=y CONFIG_ZTEST_STACK_SIZE=2048 CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_FILE_SYSTEM=y diff --git a/tests/subsys/settings/functional/nvs/prj.conf b/tests/subsys/settings/functional/nvs/prj.conf index 2466686f555..1ab9abd5576 100644 --- a/tests/subsys/settings/functional/nvs/prj.conf +++ b/tests/subsys/settings/functional/nvs/prj.conf @@ -1,6 +1,5 @@ CONFIG_ZTEST=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y diff --git a/tests/subsys/settings/nvs/prj.conf b/tests/subsys/settings/nvs/prj.conf index 2466686f555..1ab9abd5576 100644 --- a/tests/subsys/settings/nvs/prj.conf +++ b/tests/subsys/settings/nvs/prj.conf @@ -1,6 +1,5 @@ CONFIG_ZTEST=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y diff --git a/tests/subsys/storage/stream/stream_flash/prj.conf b/tests/subsys/storage/stream/stream_flash/prj.conf index 6e5811b8fdc..99684390afa 100644 --- a/tests/subsys/storage/stream/stream_flash/prj.conf +++ b/tests/subsys/storage/stream/stream_flash/prj.conf @@ -6,7 +6,6 @@ CONFIG_ZTEST=y CONFIG_FLASH=y -CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_NVS=y CONFIG_SETTINGS=y From 731f8d473610f04ec3d0cf53cb10dd373b467f31 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Stenberg?= Date: Thu, 8 Feb 2024 15:47:32 +0100 Subject: [PATCH 2086/2402] modbus: Respect CONFIG_UART_USE_RUNTIME_CONFIGURE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only perform runtime UART configuration if it is enabled. Signed-off-by: Björn Stenberg --- subsys/modbus/Kconfig | 2 +- subsys/modbus/modbus_serial.c | 94 ++++++++++++++++++++--------------- 2 files changed, 55 insertions(+), 41 deletions(-) diff --git a/subsys/modbus/Kconfig b/subsys/modbus/Kconfig index 38c7d761c07..4c49d6c0985 100644 --- a/subsys/modbus/Kconfig +++ b/subsys/modbus/Kconfig @@ -44,7 +44,7 @@ config MODBUS_SERIAL default y depends on SERIAL && SERIAL_HAS_DRIVER depends on DT_HAS_ZEPHYR_MODBUS_SERIAL_ENABLED - select UART_USE_RUNTIME_CONFIGURE + imply UART_USE_RUNTIME_CONFIGURE help Enable Modbus over serial line support. diff --git a/subsys/modbus/modbus_serial.c b/subsys/modbus/modbus_serial.c index a8b65291781..13d59c8154a 100644 --- a/subsys/modbus/modbus_serial.c +++ b/subsys/modbus/modbus_serial.c @@ -444,6 +444,58 @@ static int configure_gpio(struct modbus_context *ctx) return 0; } +static inline int configure_uart(struct modbus_context *ctx, + struct modbus_iface_param *param) +{ + struct modbus_serial_config *cfg = ctx->cfg; + struct uart_config uart_cfg = { + .baudrate = param->serial.baud, + .flow_ctrl = UART_CFG_FLOW_CTRL_NONE, + }; + + if (ctx->mode == MODBUS_MODE_ASCII) { + uart_cfg.data_bits = UART_CFG_DATA_BITS_7; + } else { + uart_cfg.data_bits = UART_CFG_DATA_BITS_8; + } + + switch (param->serial.parity) { + case UART_CFG_PARITY_ODD: + case UART_CFG_PARITY_EVEN: + uart_cfg.parity = param->serial.parity; + uart_cfg.stop_bits = UART_CFG_STOP_BITS_1; + break; + case UART_CFG_PARITY_NONE: + /* Use of no parity requires 2 stop bits */ + uart_cfg.parity = param->serial.parity; + uart_cfg.stop_bits = UART_CFG_STOP_BITS_2; + break; + default: + return -EINVAL; + } + + if (ctx->client) { + /* Allow custom stop bit settings only in client mode */ + switch (param->serial.stop_bits_client) { + case UART_CFG_STOP_BITS_0_5: + case UART_CFG_STOP_BITS_1: + case UART_CFG_STOP_BITS_1_5: + case UART_CFG_STOP_BITS_2: + uart_cfg.stop_bits = param->serial.stop_bits_client; + break; + default: + return -EINVAL; + } + } + + if (uart_configure(cfg->dev, &uart_cfg) != 0) { + LOG_ERR("Failed to configure UART"); + return -EINVAL; + } + + return 0; +} + void modbus_serial_rx_disable(struct modbus_context *ctx) { modbus_serial_rx_off(ctx); @@ -505,7 +557,6 @@ int modbus_serial_init(struct modbus_context *ctx, struct modbus_serial_config *cfg = ctx->cfg; const uint32_t if_delay_max = 3500000; const uint32_t numof_bits = 11; - struct uart_config uart_cfg; switch (param.mode) { case MODBUS_MODE_RTU: @@ -521,49 +572,12 @@ int modbus_serial_init(struct modbus_context *ctx, return -ENODEV; } - uart_cfg.baudrate = param.serial.baud, - uart_cfg.flow_ctrl = UART_CFG_FLOW_CTRL_NONE; - - if (ctx->mode == MODBUS_MODE_ASCII) { - uart_cfg.data_bits = UART_CFG_DATA_BITS_7; - } else { - uart_cfg.data_bits = UART_CFG_DATA_BITS_8; - } - - switch (param.serial.parity) { - case UART_CFG_PARITY_ODD: - case UART_CFG_PARITY_EVEN: - uart_cfg.parity = param.serial.parity; - uart_cfg.stop_bits = UART_CFG_STOP_BITS_1; - break; - case UART_CFG_PARITY_NONE: - /* Use of no parity requires 2 stop bits */ - uart_cfg.parity = param.serial.parity; - uart_cfg.stop_bits = UART_CFG_STOP_BITS_2; - break; - default: - return -EINVAL; - } - - if (ctx->client) { - /* Allow custom stop bit settings only in client mode */ - switch (param.serial.stop_bits_client) { - case UART_CFG_STOP_BITS_0_5: - case UART_CFG_STOP_BITS_1: - case UART_CFG_STOP_BITS_1_5: - case UART_CFG_STOP_BITS_2: - uart_cfg.stop_bits = param.serial.stop_bits_client; - break; - default: + if (IS_ENABLED(CONFIG_UART_USE_RUNTIME_CONFIGURE)) { + if (configure_uart(ctx, ¶m) != 0) { return -EINVAL; } } - if (uart_configure(cfg->dev, &uart_cfg) != 0) { - LOG_ERR("Failed to configure UART"); - return -EINVAL; - } - if (param.serial.baud <= 38400) { cfg->rtu_timeout = (numof_bits * if_delay_max) / param.serial.baud; From 9c05618c2b6b8e10ab523411067e32846cd8cd8e Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Wed, 10 Apr 2024 07:18:30 +0100 Subject: [PATCH 2087/2402] tests: Fix missed renames Fixes some missed renames for overlays with the recent change Signed-off-by: Jamie McCrae Signed-off-by: Torsten Rasmussen --- .../boards/{mps2_an521.overlay => mps2_an521_cpu0.overlay} | 0 .../boards/qemu_riscv32_qemu_virt_riscv32_smp.overlay | 6 ++++++ .../boards/{mps2_an521.overlay => mps2_an521_cpu0.overlay} | 0 3 files changed, 6 insertions(+) rename samples/subsys/tracing/boards/{mps2_an521.overlay => mps2_an521_cpu0.overlay} (100%) create mode 100644 tests/drivers/coredump/coredump_api/boards/qemu_riscv32_qemu_virt_riscv32_smp.overlay rename tests/lib/shared_multi_heap/boards/{mps2_an521.overlay => mps2_an521_cpu0.overlay} (100%) diff --git a/samples/subsys/tracing/boards/mps2_an521.overlay b/samples/subsys/tracing/boards/mps2_an521_cpu0.overlay similarity index 100% rename from samples/subsys/tracing/boards/mps2_an521.overlay rename to samples/subsys/tracing/boards/mps2_an521_cpu0.overlay diff --git a/tests/drivers/coredump/coredump_api/boards/qemu_riscv32_qemu_virt_riscv32_smp.overlay b/tests/drivers/coredump/coredump_api/boards/qemu_riscv32_qemu_virt_riscv32_smp.overlay new file mode 100644 index 00000000000..ce40ceadeb8 --- /dev/null +++ b/tests/drivers/coredump/coredump_api/boards/qemu_riscv32_qemu_virt_riscv32_smp.overlay @@ -0,0 +1,6 @@ +/* + * Copyright Meta Platforms, Inc. and its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "qemu_riscv32.overlay" diff --git a/tests/lib/shared_multi_heap/boards/mps2_an521.overlay b/tests/lib/shared_multi_heap/boards/mps2_an521_cpu0.overlay similarity index 100% rename from tests/lib/shared_multi_heap/boards/mps2_an521.overlay rename to tests/lib/shared_multi_heap/boards/mps2_an521_cpu0.overlay From 1ab6f82c7e3195dfde5a58f2ae0b94a2cc1b8b51 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Mon, 8 Apr 2024 12:35:07 +0200 Subject: [PATCH 2088/2402] lib: smf: check for NULL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit don't execute share_paren() if the target is NULL in smf_execute_ancestor_exit_actions() Signed-off-by: Fin Maaß --- lib/smf/smf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/smf/smf.c b/lib/smf/smf.c index d869de47c6e..ecc10740744 100644 --- a/lib/smf/smf.c +++ b/lib/smf/smf.c @@ -172,7 +172,8 @@ __unused static bool smf_execute_ancestor_exit_actions( for (const struct smf_state *tmp_state = ctx->current->parent; tmp_state != NULL; tmp_state = tmp_state->parent) { - if (!share_paren(target->parent, tmp_state) && tmp_state->exit) { + if ((target == NULL || !share_paren(target->parent, tmp_state)) && + tmp_state->exit) { tmp_state->exit(ctx); /* No need to continue if terminate was set */ From 768215ad963d103fe27de514f213ffd7e5669352 Mon Sep 17 00:00:00 2001 From: Nikola Trifunovic Date: Tue, 9 Apr 2024 22:41:00 +0200 Subject: [PATCH 2089/2402] boards: m5stack: m5stack_atom_lite file ending typo fixed Change board.yaml to board.yml in zephyr/boards/m5stack/m5stack_atom_lite. Fixes: #71240 Signed-off-by: Nikola Trifunovic --- boards/m5stack/m5stack_atom_lite/{board.yaml => board.yml} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename boards/m5stack/m5stack_atom_lite/{board.yaml => board.yml} (100%) diff --git a/boards/m5stack/m5stack_atom_lite/board.yaml b/boards/m5stack/m5stack_atom_lite/board.yml similarity index 100% rename from boards/m5stack/m5stack_atom_lite/board.yaml rename to boards/m5stack/m5stack_atom_lite/board.yml From 8d4743d14474fc5b65cbb8016aeee7ab3fe3090c Mon Sep 17 00:00:00 2001 From: Piotr Kosycarz Date: Mon, 8 Apr 2024 11:39:38 +0200 Subject: [PATCH 2090/2402] samples: sensor: qdec: Allow coverage calculation Sample must end to dump coverage data. Signed-off-by: Piotr Kosycarz --- samples/sensor/qdec/src/main.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/samples/sensor/qdec/src/main.c b/samples/sensor/qdec/src/main.c index 3e7e87ab021..3410d04e5ba 100644 --- a/samples/sensor/qdec/src/main.c +++ b/samples/sensor/qdec/src/main.c @@ -85,7 +85,11 @@ int main(void) qenc_emulate_init(); +#ifndef CONFIG_COVERAGE while (true) { +#else + for (int i = 0; i < 3; i++) { +#endif rc = sensor_sample_fetch(dev); if (rc != 0) { printk("Failed to fetch sample (%d)\n", rc); From f77c7a3d05d4baded8878db47d4968789d625784 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Mon, 8 Apr 2024 10:39:16 +0200 Subject: [PATCH 2091/2402] net: dhcpv4_server: Fix positive error codes returned errno values are positive, therefore they should be negated when assigned as return values for net_dhcpv4_server_start(). Signed-off-by: Robert Lubos --- subsys/net/lib/dhcpv4/dhcpv4_server.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/subsys/net/lib/dhcpv4/dhcpv4_server.c b/subsys/net/lib/dhcpv4/dhcpv4_server.c index bfdf7477953..95236d2a982 100644 --- a/subsys/net/lib/dhcpv4/dhcpv4_server.c +++ b/subsys/net/lib/dhcpv4/dhcpv4_server.c @@ -1533,7 +1533,7 @@ int net_dhcpv4_server_start(struct net_if *iface, struct in_addr *base_addr) sock = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); if (sock < 0) { - ret = errno; + ret = -errno; LOG_ERR("Failed to create DHCPv4 server socket, %d", ret); goto error; } @@ -1541,7 +1541,7 @@ int net_dhcpv4_server_start(struct net_if *iface, struct in_addr *base_addr) ret = zsock_setsockopt(sock, SOL_SOCKET, SO_BINDTODEVICE, &ifreq, sizeof(ifreq)); if (ret < 0) { - ret = errno; + ret = -errno; LOG_ERR("Failed to bind DHCPv4 server socket with interface, %d", ret); goto error; @@ -1549,7 +1549,7 @@ int net_dhcpv4_server_start(struct net_if *iface, struct in_addr *base_addr) ret = zsock_bind(sock, (struct sockaddr *)&addr, sizeof(addr)); if (ret < 0) { - ret = errno; + ret = -errno; LOG_ERR("Failed to bind DHCPv4 server socket, %d", ret); goto error; } From cb7aae6f82c5cbc953da48c46baef51b54d9614b Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 8 Apr 2024 11:40:05 +0300 Subject: [PATCH 2092/2402] net: dns-sd: Do not use sockaddr struct directly The "struct sockaddr" should only be used in casts and never as a standalone variable because it might not have enough space allocated for all the protocol specific fields. So refactor the port_in_use() function to reflect that. Signed-off-by: Jukka Rissanen --- subsys/net/lib/dns/dns_sd.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/subsys/net/lib/dns/dns_sd.c b/subsys/net/lib/dns/dns_sd.c index 31fd8f6b9dd..8e64688dd86 100644 --- a/subsys/net/lib/dns/dns_sd.c +++ b/subsys/net/lib/dns/dns_sd.c @@ -667,33 +667,40 @@ static bool port_in_use_sockaddr(uint16_t proto, uint16_t port, || net_context_port_in_use(proto, port, anyp); } -static bool port_in_use(uint16_t proto, uint16_t port, const struct in_addr *addr4, - const struct in6_addr *addr6) +static bool port_in_use(uint16_t proto, uint16_t port, + const struct in_addr *addr4, + const struct in6_addr *addr6) { - bool r; - struct sockaddr sa; + bool ret = false; if (addr4 != NULL) { - net_sin(&sa)->sin_family = AF_INET; - net_sin(&sa)->sin_addr = *addr4; + struct sockaddr_in sa = { 0 }; + + sa.sin_family = AF_INET; + sa.sin_addr = *addr4; - r = port_in_use_sockaddr(proto, port, &sa); - if (r) { - return true; + ret = port_in_use_sockaddr(proto, port, + (struct sockaddr *)&sa); + if (ret) { + goto out; } } if (addr6 != NULL) { - net_sin6(&sa)->sin6_family = AF_INET6; - net_sin6(&sa)->sin6_addr = *addr6; + struct sockaddr_in6 sa = { 0 }; + + sa.sin6_family = AF_INET6; + sa.sin6_addr = *addr6; - r = port_in_use_sockaddr(proto, port, &sa); - if (r) { - return true; + ret = port_in_use_sockaddr(proto, port, + (struct sockaddr *)&sa); + if (ret) { + goto out; } } - return false; +out: + return ret; } #else /* CONFIG_NET_TEST */ static inline bool port_in_use(uint16_t proto, uint16_t port, const struct in_addr *addr4, From 936598ddf186eec7b97f3c3a16bd5cae05c90244 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 4 Apr 2024 08:43:39 +0200 Subject: [PATCH 2093/2402] tests/bsim/common sh: Improve getting test name/relative path Improve function which guesses the test name so the calling script can be invoked from any folder, not just Zephyr's base. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/sh_common.source | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/bsim/sh_common.source b/tests/bsim/sh_common.source index 2dac776f024..6c0b5444f37 100644 --- a/tests/bsim/sh_common.source +++ b/tests/bsim/sh_common.source @@ -50,18 +50,21 @@ function Execute() { } function _guess_test_relpath(){ - local PA="$(realpath --relative-to "${ZEPHYR_BASE}" $(dirname "${BASH_SOURCE[2]}"))" + local PA="$(cd -- "$(dirname "${BASH_SOURCE[2]}")" && pwd)" + PA="$(realpath --relative-to "${ZEPHYR_BASE}" "${PA}")" echo $PA | sed -E 's/\/tests?_scripts//' } # For a caller running from a tests_script/ folder, get the path of its parent # relative to $ZEPHYR_BASE +# This must be run without/before cd'ing into another directory function guess_test_relpath(){ echo $(_guess_test_relpath) } # For a caller running from a tests_script/ folder, get the path of its parent # relative to $ZEPHYR_BASE, replacing "/" with "_" +# This must be run without/before cd'ing into another directory function guess_test_long_name(){ echo $(_guess_test_relpath) | tr / _ } From 389192a94d208b5da18d2c350007eb903e916c56 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Wed, 3 Apr 2024 14:35:36 +0200 Subject: [PATCH 2094/2402] tests: Bluetooth: Add common helpers for bsim This code can be found (kinda) duplicated all over `tests/bsim/bluetooth`. Put it in a common place. Refactoring the current tests will be done in a future commit. Signed-off-by: Jonathan Rico --- tests/bsim/babblekit/CMakeLists.txt | 19 +++ .../bsim/babblekit/include/babblekit/flags.h | 55 +++++++++ tests/bsim/babblekit/include/babblekit/sync.h | 43 +++++++ .../babblekit/include/babblekit/testcase.h | 112 ++++++++++++++++++ tests/bsim/babblekit/src/sync.c | 67 +++++++++++ 5 files changed, 296 insertions(+) create mode 100644 tests/bsim/babblekit/CMakeLists.txt create mode 100644 tests/bsim/babblekit/include/babblekit/flags.h create mode 100644 tests/bsim/babblekit/include/babblekit/sync.h create mode 100644 tests/bsim/babblekit/include/babblekit/testcase.h create mode 100644 tests/bsim/babblekit/src/sync.c diff --git a/tests/bsim/babblekit/CMakeLists.txt b/tests/bsim/babblekit/CMakeLists.txt new file mode 100644 index 00000000000..67fdbc8bd31 --- /dev/null +++ b/tests/bsim/babblekit/CMakeLists.txt @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Helpers that can be used on bsim targets but don't have other +# dependencies (e.g. on Bluetooth, etc). +add_library(babblekit) + +target_link_libraries(babblekit PUBLIC + kernel + zephyr_interface +) + +target_include_directories(babblekit PUBLIC + include +) + +target_sources(babblekit PRIVATE + src/sync.c +) diff --git a/tests/bsim/babblekit/include/babblekit/flags.h b/tests/bsim/babblekit/include/babblekit/flags.h new file mode 100644 index 00000000000..89c8b45ca3e --- /dev/null +++ b/tests/bsim/babblekit/include/babblekit/flags.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * Provides a way to set/clear and block on binary flags. + * + * These flags are often used to wait until the test has gotten in a particular + * state, e.g. a connection is established or a message has been successfully + * sent. + * + * These macros can only be called from Zephyr threads. They can't be called + * from e.g. a bs_tests callback. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* Declare a flag that has been defined in another file */ +#define DECLARE_FLAG(flag) extern atomic_t flag + +/* Define a new binary flag. + * Declare them static if defining flags with the same name in multiple files. + * + * @param flag Name of the flag + */ +#define DEFINE_FLAG(flag) atomic_t flag = (atomic_t) false + +#define SET_FLAG(flag) (void)atomic_set(&flag, (atomic_t) true) +#define UNSET_FLAG(flag) (void)atomic_set(&flag, (atomic_t) false) + +#define IS_FLAG_SET(flag) (atomic_get(&flag) != false) + +/* Block until `flag` is equal to `val` */ +#define WAIT_FOR_VAL(var, val) \ + while (atomic_get(&var) != val) { \ + (void)k_sleep(K_MSEC(1)); \ + } + +/* Block until `flag` is true */ +#define WAIT_FOR_FLAG(flag) \ + while (!(bool)atomic_get(&flag)) { \ + (void)k_sleep(K_MSEC(1)); \ + } + +/* Block until `flag` is false */ +#define WAIT_FOR_FLAG_UNSET(flag) \ + while ((bool)atomic_get(&flag)) { \ + (void)k_sleep(K_MSEC(1)); \ + } + +/* Block until `flag` is true and set it to false */ +#define TAKE_FLAG(flag) \ + while (!(bool)atomic_cas(&flag, true, false)) { \ + (void)k_sleep(K_MSEC(1)); \ + } diff --git a/tests/bsim/babblekit/include/babblekit/sync.h b/tests/bsim/babblekit/include/babblekit/sync.h new file mode 100644 index 00000000000..d57538ac4d9 --- /dev/null +++ b/tests/bsim/babblekit/include/babblekit/sync.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file provides a synchronization mechanism between devices, for the + * simple use-case when there are only two devices in the simulation. + */ + + +/* + * @brief Initialize the sync library + * + * This initializes a simple synchronization library based on bsim backchannels. + * + * Calling `bk_sync_wait()` on device A will make it block until + * `bk_sync_send()` is called on device B. + * + * @note Only works between two devices in a simulation, with IDs 0 and 1. + * + * @retval 0 Sync channel operational + * @retval -1 Failed to open sync channel + * + */ +int bk_sync_init(void); + +/* + * @brief Send a synchronization packet + * + * @note Only works between two devices in a simulation, with IDs 0 and 1. + * + */ +void bk_sync_send(void); + +/* + * @brief Wait for a synchronization packet + * + * This blocks until the other device has called `bk_sync_send()`. + * + * @note Only works between two devices in a simulation, with IDs 0 and 1. + * + */ +void bk_sync_wait(void); diff --git a/tests/bsim/babblekit/include/babblekit/testcase.h b/tests/bsim/babblekit/include/babblekit/testcase.h new file mode 100644 index 00000000000..9d13a1a0030 --- /dev/null +++ b/tests/bsim/babblekit/include/babblekit/testcase.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bs_tracing.h" +#include "bs_types.h" +#include "bstests.h" + +extern enum bst_result_t bst_result; + +/* + * @brief Mark the test as in progress + * + * Call this at the start of the test entry point. + * + * @param ... format-string and arguments to print to console + * + */ +#define TEST_START(msg, ...) \ + do { \ + bst_result = In_progress; \ + bs_trace_info_time(2, "Test start: " msg "\n", ##__VA_ARGS__); \ + } while (0) + +/* + * @brief Fail the test and exit + * + * Printf-like function that also terminates the device with an error code. + * + * @param ... format-string and arguments to print to console + * + */ +#define TEST_FAIL(msg, ...) \ + do { \ + bst_result = Failed; \ + bs_trace_error_time_line(msg "\n", ##__VA_ARGS__); \ + } while (0) + +/* + * @brief Mark the currently-running test as "Passed" + * + * Mark the test as "passed". The execution continues after that point. + * + * @note Use this if you use backchannels (testlib/bsim/sync.h). + * + * After calling this, the executable will eventually return 0 when it exits. + * Unless `TEST_FAIL` is called (e.g. in a callback). + * + * @param ... format-string and arguments to print to console + * + */ +#define TEST_PASS(msg, ...) \ + do { \ + bst_result = Passed; \ + bs_trace_info_time(2, "Test end: " msg "\n", ##__VA_ARGS__); \ + } while (0) + +/* + * @brief Mark test case as passed and end execution + * + * Mark the role / test-case as "Passed" and return 0. + * + * @note DO NOT use this if you use backchannels (testlib/bsim/sync.h). + * + * @note This macro only ends execution for the current executable, not all + * executables in a simulation. + * + * @param ... format-string and arguments to print to console + * + */ +#define TEST_PASS_AND_EXIT(msg, ...) \ + do { \ + bst_result = Passed; \ + bs_trace_info_time(2, "Test end: " msg "\n", ##__VA_ARGS__); \ + bs_trace_silent_exit(0); \ + } while (0) + +/* + * @brief Assert `expr` is true + * + * Assert that `expr` is true. If assertion is false, print a printf-like + * message to the console and fail the test. I.e. return non-zero. + * + * @note This is different than `sys/__assert.h`. + * + * @param message String to print to console + * + */ +#define TEST_ASSERT(expr, ...) \ + do { \ + if (!(expr)) { \ + TEST_FAIL(__VA_ARGS__); \ + } \ + } while (0) + +/* + * @brief Print a value. Lower-level than `printk` or `LOG_xx`. + * + * Print a message to console. + * + * This can be safely called at any time in the execution of the device. + * Use it to print when the logging subsystem is not available, e.g. early + * startup or shutdown. + * + * @param ... format-string and arguments to print to console + * + */ +#define TEST_PRINT(msg, ...) \ + bs_trace_print(BS_TRACE_INFO, __FILE__, __LINE__, 0, BS_TRACE_AUTOTIME, 0, \ + msg "\n", ##__VA_ARGS__) diff --git a/tests/bsim/babblekit/src/sync.c b/tests/bsim/babblekit/src/sync.c new file mode 100644 index 00000000000..6a212420077 --- /dev/null +++ b/tests/bsim/babblekit/src/sync.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "argparse.h" +#include "bs_types.h" +#include "bs_tracing.h" +#include "time_machine.h" +#include "bs_pc_backchannel.h" + +#include +LOG_MODULE_REGISTER(sync, CONFIG_LOG_DEFAULT_LEVEL); + +#define CHANNEL_ID 0 +#define MSG_SIZE 1 + +int bk_sync_init(void) +{ + uint device_number = get_device_nbr(); + uint peer_number = device_number ^ 1; + uint device_numbers[] = { peer_number }; + uint channel_numbers[] = { CHANNEL_ID }; + uint *ch; + + ch = bs_open_back_channel(device_number, device_numbers, channel_numbers, + ARRAY_SIZE(channel_numbers)); + if (!ch) { + return -1; + } + + LOG_DBG("Sync initialized"); + + return 0; +} + +void bk_sync_send(void) +{ + uint8_t sync_msg[MSG_SIZE] = { get_device_nbr() }; + + LOG_DBG("Sending sync"); + bs_bc_send_msg(CHANNEL_ID, sync_msg, ARRAY_SIZE(sync_msg)); +} + +void bk_sync_wait(void) +{ + uint8_t sync_msg[MSG_SIZE]; + + LOG_DBG("Waiting for sync"); + + while (true) { + if (bs_bc_is_msg_received(CHANNEL_ID) > 0) { + bs_bc_receive_msg(CHANNEL_ID, sync_msg, ARRAY_SIZE(sync_msg)); + if (sync_msg[0] != get_device_nbr()) { + /* Received a message from another device, exit */ + break; + } + } + + k_sleep(K_MSEC(1)); + } + + LOG_DBG("Sync received"); +} From f818cbd8ccc9c9a80ef9669ce183e901e3ebc6fa Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Wed, 3 Apr 2024 14:37:35 +0200 Subject: [PATCH 2095/2402] tests: Bluetooth: Add example bsim test This test is intended to teach the conventions and best practices to a potential contributor that wants to add a test, for say a new feature. It is liberally commented on purpose, so new contributors don't have to spend two weeks understanding the intricacies of the simulator, the bsim test framework, the native builds, backchannels, etc.. Signed-off-by: Jonathan Rico --- doc/develop/test/bsim.rst | 6 + tests/bsim/bluetooth/host/compile.sh | 1 + .../host/misc/sample_test/CMakeLists.txt | 49 +++++ .../bluetooth/host/misc/sample_test/Kconfig | 18 ++ .../host/misc/sample_test/README.rst | 34 +++ .../bluetooth/host/misc/sample_test/prj.conf | 56 +++++ .../host/misc/sample_test/src/data.h | 26 +++ .../bluetooth/host/misc/sample_test/src/dut.c | 172 +++++++++++++++ .../host/misc/sample_test/src/main.c | 62 ++++++ .../host/misc/sample_test/src/peer.c | 200 ++++++++++++++++++ .../misc/sample_test/test_scripts/_compile.sh | 13 ++ .../host/misc/sample_test/test_scripts/run.sh | 78 +++++++ 12 files changed, 715 insertions(+) create mode 100644 tests/bsim/bluetooth/host/misc/sample_test/CMakeLists.txt create mode 100644 tests/bsim/bluetooth/host/misc/sample_test/Kconfig create mode 100644 tests/bsim/bluetooth/host/misc/sample_test/README.rst create mode 100644 tests/bsim/bluetooth/host/misc/sample_test/prj.conf create mode 100644 tests/bsim/bluetooth/host/misc/sample_test/src/data.h create mode 100644 tests/bsim/bluetooth/host/misc/sample_test/src/dut.c create mode 100644 tests/bsim/bluetooth/host/misc/sample_test/src/main.c create mode 100644 tests/bsim/bluetooth/host/misc/sample_test/src/peer.c create mode 100755 tests/bsim/bluetooth/host/misc/sample_test/test_scripts/_compile.sh create mode 100755 tests/bsim/bluetooth/host/misc/sample_test/test_scripts/run.sh diff --git a/doc/develop/test/bsim.rst b/doc/develop/test/bsim.rst index 596d2911fdf..d2f98295dc7 100644 --- a/doc/develop/test/bsim.rst +++ b/doc/develop/test/bsim.rst @@ -132,6 +132,12 @@ and then directly run one of the tests: Conventions =========== +Test code +--------- + +See the :zephyr_file:`Bluetooth sample test ` for conventions that apply to test +code. + Build scripts ------------- diff --git a/tests/bsim/bluetooth/host/compile.sh b/tests/bsim/bluetooth/host/compile.sh index de3fd1cd940..cc0d49ea360 100755 --- a/tests/bsim/bluetooth/host/compile.sh +++ b/tests/bsim/bluetooth/host/compile.sh @@ -26,6 +26,7 @@ app=tests/bsim/bluetooth/host/misc/conn_stress/central compile app=tests/bsim/bluetooth/host/misc/conn_stress/peripheral compile app=tests/bsim/bluetooth/host/misc/hfc compile app=tests/bsim/bluetooth/host/misc/unregister_conn_cb compile +app=tests/bsim/bluetooth/host/misc/sample_test compile app=tests/bsim/bluetooth/host/privacy/central compile app=tests/bsim/bluetooth/host/privacy/peripheral compile diff --git a/tests/bsim/bluetooth/host/misc/sample_test/CMakeLists.txt b/tests/bsim/bluetooth/host/misc/sample_test/CMakeLists.txt new file mode 100644 index 00000000000..8ae3a088a42 --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/sample_test/CMakeLists.txt @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) + +# You can name the project however you like. Having a unique name is encouraged. +project(sample_test) + +# This contains a variety of helper functions that abstract away common tasks, +# like scanning, setting up a connection, querying the peer for a given +# characteristic, etc.. +add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/common/testlib testlib) +target_link_libraries(app PRIVATE testlib) + +# This contains babblesim-specific helpers, e.g. device synchronization. +add_subdirectory(${ZEPHYR_BASE}/tests/bsim/babblekit babblekit) +target_link_libraries(app PRIVATE babblekit) + +zephyr_include_directories( + ${BSIM_COMPONENTS_PATH}/libUtilv1/src/ + ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/ +) + +# List every source file in the test application. Do not use GLOB. +# +# It is a good idea to have one file per test role / entry point. +# +# Try to keep test procedures readable, that is minimizing the amount of +# boilerplate. Use the `testlib` for anything that is not the object of the test +# or that you don't need tight control over. For example, setting up a +# connection between two devices. +# +# As a general rule of thumb: All functions that use `TEST_ASSERT()` are part of +# the test and should be in the same file as the test entry point. Any other +# "helper" functions can be isolated in their own file, minimizing visual +# clutter and cognitive overhead for future readers. +# +# Common data can live in a header included by multiple roles (e.g. service or +# characteristic UUIDs, test data that should be verified by both parties, +# etc..). +# +# Ideally, main.c should only set up the test framework, and map the entry +# points to the test identifiers. +target_sources(app PRIVATE + src/main.c + src/dut.c + src/peer.c +) diff --git a/tests/bsim/bluetooth/host/misc/sample_test/Kconfig b/tests/bsim/bluetooth/host/misc/sample_test/Kconfig new file mode 100644 index 00000000000..d1289e2c121 --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/sample_test/Kconfig @@ -0,0 +1,18 @@ +# Kconfig options for the test +# +# Only used as single point for log level configuration. +# Can be extended with any new kconfig, really. +# +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +menu "Test configuration" + +module = APP +module-str = app + +source "subsys/logging/Kconfig.template.log_config" + +endmenu + +source "Kconfig.zephyr" diff --git a/tests/bsim/bluetooth/host/misc/sample_test/README.rst b/tests/bsim/bluetooth/host/misc/sample_test/README.rst new file mode 100644 index 00000000000..a14244e9a98 --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/sample_test/README.rst @@ -0,0 +1,34 @@ +.. _bluetooth_bsim_test_sample: + +Bluetooth: Example BabbleSim test +################################# + +Abstract +******** + +This test's purpose is to serve as template for implementing a new BabbleSim Bluetooth test. + +BabbleSim_ is :ref:`integrated in zephyr ` and used for testing the Bluetooth stack. +The tests are implemented in ``tests/bsim/bluetooth``. +They can only be run on Linux. + +This sample test uses the ``testlib`` (:zephyr_file:`tests/bluetooth/common/testlib/CMakeLists.txt`) +test library, in order to de-duplicate code that is not relevant to the test in question. Things +like setting up a connection, getting the GATT handle of a characteristic, etc.. + +Please don't use the ``bs_`` prefix in files or identifiers. It's meant to +namespace the babblesim simulator code. + +Reading guide +************* + +Read in order: + +1. The :ref:`Bsim test documentation `. +#. ``test_scripts/run.sh`` +#. ``CMakeLists.txt`` +#. ``src/dut.c`` and ``src/peer.c`` +#. ``src/main.c`` + +.. _BabbleSim: + https://BabbleSim.github.io diff --git a/tests/bsim/bluetooth/host/misc/sample_test/prj.conf b/tests/bsim/bluetooth/host/misc/sample_test/prj.conf new file mode 100644 index 00000000000..19d767d93ef --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/sample_test/prj.conf @@ -0,0 +1,56 @@ +# Select only the config options that are necessary for the test. +# I.e. don't just copy this config and its comments into your new test. +# +# If the test is a stress or robustness test, it is also a good idea to set the +# stack resources (e.g. number of buffers, roles) to the lowest value possible. + +CONFIG_BT=y +CONFIG_BT_DEVICE_NAME="sample-test" +CONFIG_BT_PERIPHERAL=y +CONFIG_BT_CENTRAL=y + +# Dependency of testlib/adv and testlib/scan. +CONFIG_BT_EXT_ADV=y + +CONFIG_BT_GATT_CLIENT=y +CONFIG_BT_GATT_AUTO_DISCOVER_CCC=y + +# This is the object of the test. Commenting it out should make the test fail. +CONFIG_BT_GATT_ENFORCE_SUBSCRIPTION=n + +# Always enable asserts in tests, they're virtually free on native targets. +CONFIG_ASSERT=y + +# The same applies for logs. +# Only enable the INFO level though, as a contributor that isn't familiar with +# the test will have a hard time understanding what the problem is if it's +# buried in thousands of lines of debug logs. +CONFIG_LOG=y + +# Those two options together add the thread name in every log print, very useful +# for debugging if you expect the same functions to be called from different +# threads. +CONFIG_THREAD_NAME=y +CONFIG_LOG_THREAD_ID_PREFIX=y + +# BT_TESTING provides additional hooks in the stack to inspect or modify state. +# It is not strictly necessary, leave it disabled if you don't need it. +# CONFIG_BT_TESTING=y + +# Will call `raise(SIGTRAP)` on fatal error. +# If a debugger is connected to the app, it will automatically be stopped. +# Makes retrieving an exception stacktrace very easy. +CONFIG_ARCH_POSIX_TRAP_ON_FATAL=y + +# It's OK to leave useful debug options commented out, with a short comment +# explaining why they might be useful. That way, someone trying to debug your +# test will get a headstart. +# CONFIG_APP_LOG_LEVEL_DBG=y +# CONFIG_BT_CONN_LOG_LEVEL_DBG=y +# CONFIG_BT_ATT_LOG_LEVEL_DBG=y +# CONFIG_BT_GATT_LOG_LEVEL_DBG=y + +# For this particular test, the LOG_INF printed on `bt_enable()` are just noise. +# They might matter for other tests though. They are printed by the +# "bt_hci_core" domain, and HCI_CORE doesn't use LOG_INF very much anyways. +CONFIG_BT_HCI_CORE_LOG_LEVEL_WRN=y diff --git a/tests/bsim/bluetooth/host/misc/sample_test/src/data.h b/tests/bsim/bluetooth/host/misc/sample_test/src/data.h new file mode 100644 index 00000000000..48feee06c49 --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/sample_test/src/data.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_TESTS_BSIM_BLUETOOTH_HOST_MISC_SAMPLE_TEST_SRC_DATA_H_ +#define ZEPHYR_TESTS_BSIM_BLUETOOTH_HOST_MISC_SAMPLE_TEST_SRC_DATA_H_ + +#include + +static uint8_t payload_1[] = {0xab, 0xcd}; +static uint8_t payload_2[] = {0x13, 0x37}; + +/* Both payloads are assumed to be the same size in order to simplify the test + * procedure. + */ +BUILD_ASSERT(sizeof(payload_1) == sizeof(payload_2), + "Both payloads should be of equal length"); + +#define test_service_uuid \ + BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf0debc9a, 0x7856, 0x3412, 0x7856, 0x341278563412)) +#define test_characteristic_uuid \ + BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf2debc9a, 0x7856, 0x3412, 0x7856, 0x341278563412)) + +#endif /* ZEPHYR_TESTS_BSIM_BLUETOOTH_HOST_MISC_SAMPLE_TEST_SRC_DATA_H_ */ diff --git a/tests/bsim/bluetooth/host/misc/sample_test/src/dut.c b/tests/bsim/bluetooth/host/misc/sample_test/src/dut.c new file mode 100644 index 00000000000..ea6d62f3ded --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/sample_test/src/dut.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#include "testlib/conn.h" +#include "testlib/scan.h" + +#include "babblekit/flags.h" +#include "babblekit/sync.h" +#include "babblekit/testcase.h" + +/* local includes */ +#include "data.h" + +LOG_MODULE_REGISTER(dut, CONFIG_APP_LOG_LEVEL); + +static DEFINE_FLAG(is_subscribed); + +static void ccc_changed(const struct bt_gatt_attr *attr, uint16_t value) +{ + /* assume we only get it for the `test_gatt_service` */ + if (value != 0) { + SET_FLAG(is_subscribed); + } else { + UNSET_FLAG(is_subscribed); + } +} + +BT_GATT_SERVICE_DEFINE(test_gatt_service, BT_GATT_PRIMARY_SERVICE(test_service_uuid), + BT_GATT_CHARACTERISTIC(test_characteristic_uuid, + (BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | + BT_GATT_CHRC_NOTIFY | BT_GATT_CHRC_INDICATE), + BT_GATT_PERM_READ | BT_GATT_PERM_WRITE, NULL, NULL, + NULL), + BT_GATT_CCC(ccc_changed, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE),); + +/* This is the entrypoint for the DUT. + * + * This is executed by the `bst_test` framework provided by the zephyr bsim + * boards. The framework selects which "main" function to run as entrypoint + * depending on the `-testid=` command-line parameter passed to the zephyr + * executable. + * + * In our case, the `testid` is set to "dut" and `entrypoint_dut()` is mapped to + * the "dut" ID in `entrypoints[]`. + * + * In our case we only have two entrypoints, as we only have a single test + * involving two devices (so 1x 2 entrypoints). One can define more test cases + * with different entrypoints and map them to different test ID strings in + * `entrypoints[]` + */ +void entrypoint_dut(void) +{ + /* Please leave a comment indicating what the test is supposed to test, + * and what is the pass verdict. A nice place is at the beginning of + * each test entry point. Something like the following: + */ + + /* Test purpose: + * + * Verifies that we are able to send a notification to the peer when + * `CONFIG_BT_GATT_ENFORCE_SUBSCRIPTION` is disabled and the peer has + * unsubscribed from the characteristic in question. + * + * Two devices: + * - `dut`: tries to send the notification + * - `peer`: will receive the notification + * + * Procedure: + * - [dut] establish connection to `peer` + * - [peer] discover GATT and subscribe to the test characteristic + * - [dut] send notification #1 + * - [peer] wait for notification + * - [peer] unsubscribe + * - [dut] send notification #2 + * - [peer] and [dut] pass test + * + * [verdict] + * - peer receives notifications #1 and #2 + */ + int err; + bt_addr_le_t peer = {}; + struct bt_conn *conn = NULL; + const struct bt_gatt_attr *attr; + uint8_t data[10]; + + /* Mark test as in progress. */ + TEST_START("dut"); + + /* Initialize device sync library */ + bk_sync_init(); + + /* Initialize Bluetooth */ + err = bt_enable(NULL); + TEST_ASSERT(err == 0, "Can't enable Bluetooth (err %d)", err); + + LOG_DBG("Bluetooth initialized"); + + /* Find the address of the peer. In our case, both devices are actually + * the same executable (with the same config) but executed with + * different arguments. We can then just use CONFIG_BT_DEVICE_NAME which + * contains our device name in string form. + */ + err = bt_testlib_scan_find_name(&peer, CONFIG_BT_DEVICE_NAME); + TEST_ASSERT(!err, "Failed to start scan (err %d)", err); + + /* Create a connection using that address */ + err = bt_testlib_connect(&peer, &conn); + TEST_ASSERT(!err, "Failed to initiate connection (err %d)", err); + + LOG_DBG("Connected"); + + LOG_INF("Wait until peer subscribes"); + UNSET_FLAG(is_subscribed); + WAIT_FOR_FLAG(is_subscribed); + + /* Prepare data for notifications + * attrs[0] is our service declaration + * attrs[1] is our characteristic declaration + * attrs[2] is our characteristic value + * + * We store a pointer for the characteristic value as that is the + * value we want to notify later. + * + * We could alternatively use `bt_gatt_notify_uuid()`. + */ + attr = &test_gatt_service.attrs[2]; + + LOG_INF("Send notification #1"); + LOG_HEXDUMP_DBG(data, sizeof(data), "Notification payload"); + + err = bt_gatt_notify(conn, attr, payload_1, sizeof(payload_1)); + TEST_ASSERT(!err, "Failed to send notification: err %d", err); + + LOG_INF("Wait until peer unsubscribes"); + WAIT_FOR_FLAG_UNSET(is_subscribed); + + LOG_INF("Send notification #2"); + err = bt_gatt_notify(conn, attr, payload_2, sizeof(payload_2)); + TEST_ASSERT(!err, "Failed to send notification: err %d", err); + + /* We won't be using `conn` anymore */ + bt_conn_unref(conn); + + /* Wait until the peer has received notification #2. + * + * This is not strictly necessary, but serves as an example on how to + * use the backchannel-based synchronization mechanism between devices + * in a simulation. + */ + bk_sync_wait(); + + /* Wait for the acknowledge of the DUT. If a device that uses + * backchannels exits prematurely (ie before the other side has read the + * message it sent), we are in undefined behavior territory. + * + * The simulation will continue running for its specified length. + * + * If you don't need backchannels, using `TEST_PASS_AND_EXIT()` is + * better as it will make the simulation exit prematurely, saving + * computing resources (CI compute time is not free). + */ + TEST_PASS("dut"); +} diff --git a/tests/bsim/bluetooth/host/misc/sample_test/src/main.c b/tests/bsim/bluetooth/host/misc/sample_test/src/main.c new file mode 100644 index 00000000000..278cdc2090e --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/sample_test/src/main.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "bs_tracing.h" +#include "bstests.h" +#include "babblekit/testcase.h" + +extern void entrypoint_dut(void); +extern void entrypoint_peer(void); +extern enum bst_result_t bst_result; + + +static void test_end_cb(void) +{ + /* This callback will fire right before the executable returns + * + * You can use it to print test or system state that would be of use for + * debugging why the test fails. + * Here we just print a dummy string for demonstration purposes. + * + * Can also be used to trigger a `k_oops` which will halt the image if + * running under a debugger, if `CONFIG_ARCH_POSIX_TRAP_ON_FATAL=y`. + */ + static const char demo_state[] = "My interesting state"; + + if (bst_result != Passed) { + TEST_PRINT("Test has not passed. State: %s", demo_state); + } +} + +static const struct bst_test_instance entrypoints[] = { + { + .test_id = "dut", + .test_delete_f = test_end_cb, + .test_main_f = entrypoint_dut, + }, + { + .test_id = "peer", + .test_delete_f = test_end_cb, + .test_main_f = entrypoint_peer, + }, + BSTEST_END_MARKER, +}; + +static struct bst_test_list *install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, entrypoints); +}; + +bst_test_install_t test_installers[] = {install, NULL}; + +int main(void) +{ + bst_main(); + + return 0; +} diff --git a/tests/bsim/bluetooth/host/misc/sample_test/src/peer.c b/tests/bsim/bluetooth/host/misc/sample_test/src/peer.c new file mode 100644 index 00000000000..475043c0d3a --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/sample_test/src/peer.c @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#include "testlib/adv.h" +#include "testlib/att_read.h" +#include "testlib/att_write.h" +#include "testlib/conn.h" + +#include "babblekit/flags.h" +#include "babblekit/sync.h" +#include "babblekit/testcase.h" + +/* local includes */ +#include "data.h" + +LOG_MODULE_REGISTER(peer, CONFIG_APP_LOG_LEVEL); + +static DEFINE_FLAG(is_subscribed); +static DEFINE_FLAG(got_notification_1); +static DEFINE_FLAG(got_notification_2); + +int find_characteristic(struct bt_conn *conn, + const struct bt_uuid *svc, + const struct bt_uuid *chrc, + uint16_t *chrc_value_handle) +{ + uint16_t svc_handle; + uint16_t svc_end_handle; + uint16_t chrc_end_handle; + int err; + + LOG_DBG(""); + + err = bt_testlib_gatt_discover_primary(&svc_handle, &svc_end_handle, conn, svc, + BT_ATT_FIRST_ATTRIBUTE_HANDLE, + BT_ATT_LAST_ATTRIBUTE_HANDLE); + if (err != 0) { + LOG_ERR("Failed to discover service: %d", err); + + return err; + } + + LOG_DBG("svc_handle: %u, svc_end_handle: %u", svc_handle, svc_end_handle); + + err = bt_testlib_gatt_discover_characteristic(chrc_value_handle, &chrc_end_handle, + NULL, conn, chrc, (svc_handle + 1), + svc_end_handle); + if (err != 0) { + LOG_ERR("Failed to get value handle: %d", err); + + return err; + } + + LOG_DBG("chrc_value_handle: %u, chrc_end_handle: %u", *chrc_value_handle, chrc_end_handle); + + return err; +} + +static uint8_t received_notification(struct bt_conn *conn, + struct bt_gatt_subscribe_params *params, + const void *data, + uint16_t length) +{ + if (length) { + LOG_INF("RX notification"); + LOG_HEXDUMP_DBG(data, length, "payload"); + + TEST_ASSERT(length == sizeof(payload_1), "Unexpected length: %d", length); + + if (!memcmp(payload_1, data, length)) { + SET_FLAG(got_notification_1); + } else if (!memcmp(payload_2, data, length)) { + SET_FLAG(got_notification_2); + } + } + + return BT_GATT_ITER_CONTINUE; +} + +static void sub_cb(struct bt_conn *conn, + uint8_t err, + struct bt_gatt_subscribe_params *params) +{ + TEST_ASSERT(!err, "Subscribe failed (err %d)", err); + + TEST_ASSERT(params, "params is NULL"); + TEST_ASSERT(params->value, "Host shouldn't know we have unsubscribed"); + + LOG_DBG("Subscribed to handle 0x%04x", params->value_handle); + SET_FLAG(is_subscribed); +} + +/* Subscription parameters have the same lifetime as a subscription. + * That is the backing struct should stay valid until a call to + * `bt_gatt_unsubscribe()` is made. Hence the `static`. + */ +static struct bt_gatt_subscribe_params sub_params; + +/* This is "working memory" used by the `CONFIG_BT_GATT_AUTO_DISCOVER_CCC` + * feature. It also has to stay valid until the end of the async call. + */ +static struct bt_gatt_discover_params ccc_disc_params; + +static void subscribe(struct bt_conn *conn, + uint16_t handle, + bt_gatt_notify_func_t cb) +{ + int err; + + /* Subscribe to notifications */ + sub_params.notify = cb; + sub_params.subscribe = sub_cb; + sub_params.value = BT_GATT_CCC_NOTIFY; + sub_params.value_handle = handle; + + /* Set-up auto-discovery of the CCC handle */ + sub_params.ccc_handle = 0; + sub_params.disc_params = &ccc_disc_params; + sub_params.end_handle = BT_ATT_LAST_ATTRIBUTE_HANDLE; + + err = bt_gatt_subscribe(conn, &sub_params); + TEST_ASSERT(!err, "Subscribe failed (err %d)", err); + + WAIT_FOR_FLAG(is_subscribed); +} + +static void unsubscribe_but_not_really(struct bt_conn *conn, uint16_t handle) +{ + /* Here we do something slightly different: + * + * Since we want to still be able to receive the notification, we don't + * actually want to unsubscribe. We only want to make the server *think* + * we have unsubscribed in order to test that + * CONFIG_BT_GATT_ENFORCE_SUBSCRIPTION works properly. + * + * So we just write a 0 to the CCC handle, that should do the trick. + */ + uint8_t data[1] = {0}; + + int err = bt_testlib_att_write(conn, BT_ATT_CHAN_OPT_NONE, + sub_params.ccc_handle, data, sizeof(data)); + + TEST_ASSERT(!err, "Unsubscribe failed: err %d", err); +} + +/* Read the comments on `entrypoint_dut()` first. */ +void entrypoint_peer(void) +{ + int err; + struct bt_conn *conn; + uint16_t handle; + + /* Mark test as in progress. */ + TEST_START("peer"); + + /* Initialize device sync library */ + bk_sync_init(); + + /* Initialize Bluetooth */ + err = bt_enable(NULL); + TEST_ASSERT(err == 0, "Can't enable Bluetooth (err %d)", err); + + LOG_DBG("Bluetooth initialized"); + + err = bt_testlib_adv_conn(&conn, BT_ID_DEFAULT, + (BT_LE_ADV_OPT_USE_NAME | BT_LE_ADV_OPT_FORCE_NAME_IN_AD)); + TEST_ASSERT(!err, "Failed to start connectable advertising (err %d)", err); + + LOG_DBG("Discover test characteristic"); + err = find_characteristic(conn, test_service_uuid, test_characteristic_uuid, &handle); + TEST_ASSERT(!err, "Failed to find characteristic: %d", err); + + LOG_DBG("Subscribe to test characteristic: handle 0x%04x", handle); + subscribe(conn, handle, received_notification); + + WAIT_FOR_FLAG(got_notification_1); + + LOG_DBG("Unsubscribe from test characteristic: handle 0x%04x", handle); + unsubscribe_but_not_really(conn, handle); + + WAIT_FOR_FLAG(got_notification_2); + bk_sync_send(); + + /* Disconnect and destroy connection object */ + LOG_DBG("Disconnect"); + err = bt_testlib_disconnect(&conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN); + TEST_ASSERT(!err, "Failed to disconnect (err %d)", err); + + TEST_PASS("peer"); +} diff --git a/tests/bsim/bluetooth/host/misc/sample_test/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/sample_test/test_scripts/_compile.sh new file mode 100755 index 00000000000..e717a4b2bbe --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/sample_test/test_scripts/_compile.sh @@ -0,0 +1,13 @@ +#!/usr/bin/env bash +# Copyright 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +set -eu +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +INCR_BUILD=1 + +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)" compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/misc/sample_test/test_scripts/run.sh b/tests/bsim/bluetooth/host/misc/sample_test/test_scripts/run.sh new file mode 100755 index 00000000000..431d7c2064e --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/sample_test/test_scripts/run.sh @@ -0,0 +1,78 @@ +#!/usr/bin/env bash +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +set -eu + +# Provides common functions for bsim tests. +# Mainly `Execute`, and `wait_for_background_jobs`. +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +# Helper variable. Expands to "tests_bsim_bluetooth_host_misc_sample_test". +test_name="$(guess_test_long_name)" + +# Use a unique simulation id per test script. It is a necessity as the CI runner +# will run all the test scripts in parallel. If multiple simulations share the +# same ID, they will step on each other's toes in unpredictable ways. +simulation_id=${test_name} + +# This controls the verbosity of the simulator. It goes up to 9 (not 11, sorry) +# and is useful for figuring out what is happening on the PHYsical layer (e.g. +# device 1 starts listening at T=100us) among other things. +# `2` is the default value if not specified. +verbosity_level=2 + +# This sets the watchdog timeout for the `Execute` function. +# +# Although all simulations are started with a bounded end (the `sim_length` +# option), something very wrong can still happen and this additional time-out +# will ensure all executables started by the current script are killed. +# +# It measures wall-clock time, not simulated time. E.g. a test that simulates 5 +# hours might actually complete (have a runtime of) 10 seconds. +# +# The default is set in `sh_common.source`. +# Guidelines to set this value: +# - Do not set it to a value lower or equal to the default. +# - If the test takes over 5 seconds of runtime, set `EXECUTE_TIMEOUT` to at +# least 5 times the run-time on your machine. +EXECUTE_TIMEOUT=120 + +# Set simulation length, in microseconds. The PHY will run for this amount of +# simulated time, unless both devices exit. +# +# If you are not early-exiting the devices (e.g. using `TEST_PASS_AND_EXIT()`), +# please run the test once and set the simulation time in the same ballpark. No +# need to simulate hours of runtime if the test finishes in 10 seconds. +# +SIM_LEN_US=$((2 * 1000 * 1000)) + +# This is the final path of the test executable. +# +# Some tests may have different executable images for each device in the test. +# +# In our case, both test cases are compiled in the same image, and the right one +# will be run depending on what arguments we give the executable. +test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_${test_name}_prj_conf" + +# BabbleSim will by default search for its shared libraries assuming it is +# running in the bin/ directory. Test results will also be placed in +# `${BSIM_OUT_PATH}/results` if not specified. +cd ${BSIM_OUT_PATH}/bin + +# Instantiate all devices in the simulation. +# The `testid` parameter is used to run the right role or procedure (here "dut" vs "tester"). +Execute "${test_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -rs=420 -testid=dut +Execute "${test_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -rs=69 -testid=peer + +# Start the PHY. Double-check the `-D` parameter: it has to match the number of +# devices started in the lines above. +# +# Also set a maximum simulation length. If the devices have not set a special +# variable indicating they have passed before the simulation runs out of time, +# the test will be reported as "in progress (not passed)". +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=${SIM_LEN_US} $@ + +# Wait until all executables started above have returned. +# The exit code returned will be != 0 if any of them have failed. +wait_for_background_jobs From 55533bc607bb9f17360ec744550ee7ec875fe69e Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Fri, 5 Apr 2024 11:35:09 +0200 Subject: [PATCH 2096/2402] scripts: Add `APP_LOG_LEVEL_DBG` Someone should really fix this properly.. Signed-off-by: Jonathan Rico --- scripts/ci/check_compliance.py | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index a77bd580453..55430f9cfe3 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -803,6 +803,7 @@ def check_no_undef_outside_kconfig(self, kconf): "APP_LOG_LEVEL", # Application log level is not detected correctly as # the option is defined using a template, so it can't # be grepped + "APP_LOG_LEVEL_DBG", "ARMCLANG_STD_LIBC", # The ARMCLANG_STD_LIBC is defined in the # toolchain Kconfig which is sourced based on # Zephyr toolchain variant and therefore not From d8614afd8ddab19b39da40ea8453767894dc3a26 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 15 Mar 2024 11:35:03 -0700 Subject: [PATCH 2097/2402] x86: gen_gdt: remove extra unnecessary parens Pylint complains so we fix. Signed-off-by: Daniel Leung --- arch/x86/gen_gdt.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/gen_gdt.py b/arch/x86/gen_gdt.py index 8bb99e9cfa9..a65586a56f8 100755 --- a/arch/x86/gen_gdt.py +++ b/arch/x86/gen_gdt.py @@ -137,7 +137,7 @@ def create_tss_entry(base, limit, dpl): gran = 0 flags = (gran << 7) | limit_hi - type_byte = ((present << 7) | (dpl << 5) | type_code) + type_byte = (present << 7) | (dpl << 5) | type_code return struct.pack(GDT_ENT_FMT, limit_lo, base_lo, base_mid, type_byte, flags, base_hi) From 3d3986490080940f6b8ff62fdec972e22496f32c Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 12 Mar 2024 16:23:17 -0700 Subject: [PATCH 2098/2402] x86: do not advertise demand paging support for x86_64 x86_64 does not currently support demand paging so don't advertise it. Signed-off-by: Daniel Leung --- arch/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index 4a90eb395d3..a746044362a 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -85,7 +85,7 @@ config X86 select ARCH_HAS_GDBSTUB if !X86_64 select ARCH_HAS_TIMING_FUNCTIONS select ARCH_HAS_THREAD_LOCAL_STORAGE - select ARCH_HAS_DEMAND_PAGING + select ARCH_HAS_DEMAND_PAGING if !X86_64 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD select NEED_LIBC_MEM_PARTITION if USERSPACE && TIMING_FUNCTIONS \ && !BOARD_HAS_TIMING_FUNCTIONS \ From ac5835565bc6750a5f90daf6d3795d1fea9ab992 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Thu, 7 Mar 2024 16:15:18 -0800 Subject: [PATCH 2099/2402] x86: synchronize usage of CONFIG_X86_STACK_PROTECTION Most places use CONFIG_X86_STACK_PROTECTION, but there are some places using CONFIG_HW_STACK_PROTECTION. So synchronize all to use CONFIG_X86_STACK_PROTECTION instead. Signed-off-by: Daniel Leung --- arch/x86/core/userspace.c | 2 +- arch/x86/gen_gdt.py | 2 +- arch/x86/include/x86_mmu.h | 2 +- include/zephyr/arch/x86/ia32/arch.h | 2 +- include/zephyr/arch/x86/ia32/scripts/shared_kernel_pages.ld | 2 +- include/zephyr/arch/x86/thread_stack.h | 6 +++--- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/core/userspace.c b/arch/x86/core/userspace.c index 09e7945303d..7ad77166b0f 100644 --- a/arch/x86/core/userspace.c +++ b/arch/x86/core/userspace.c @@ -134,7 +134,7 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, stack_start = POINTER_TO_UINT(_current->stack_obj); stack_size = K_THREAD_STACK_LEN(_current->stack_info.size); -#if defined(CONFIG_HW_STACK_PROTECTION) +#if defined(CONFIG_X86_STACK_PROTECTION) /* With hardware stack protection, the first page of stack * is a guard page. So need to skip it. */ diff --git a/arch/x86/gen_gdt.py b/arch/x86/gen_gdt.py index a65586a56f8..5794a965a02 100755 --- a/arch/x86/gen_gdt.py +++ b/arch/x86/gen_gdt.py @@ -185,7 +185,7 @@ def main(): # fault exception handling if "CONFIG_USERSPACE" in syms: num_entries = 7 - elif "CONFIG_HW_STACK_PROTECTION" in syms: + elif "CONFIG_X86_STACK_PROTECTION" in syms: num_entries = 5 else: num_entries = 3 diff --git a/arch/x86/include/x86_mmu.h b/arch/x86/include/x86_mmu.h index b5b319a64e4..0328e98d735 100644 --- a/arch/x86/include/x86_mmu.h +++ b/arch/x86/include/x86_mmu.h @@ -120,7 +120,7 @@ void z_x86_pentry_get(int *paging_level, pentry_t *val, pentry_t *ptables, void z_x86_dump_page_tables(pentry_t *ptables); #endif /* CONFIG_EXCEPTION_DEBUG */ -#ifdef CONFIG_HW_STACK_PROTECTION +#ifdef CONFIG_X86_STACK_PROTECTION /* Legacy function - set identity-mapped MMU stack guard page to RO in the * kernel's page tables to prevent writes and generate an exception */ diff --git a/include/zephyr/arch/x86/ia32/arch.h b/include/zephyr/arch/x86/ia32/arch.h index bd6ae1ed040..8e85ccaea11 100644 --- a/include/zephyr/arch/x86/ia32/arch.h +++ b/include/zephyr/arch/x86/ia32/arch.h @@ -45,7 +45,7 @@ */ #if defined(CONFIG_USERSPACE) #define GS_TLS_SEG (0x38 | 0x03) -#elif defined(CONFIG_HW_STACK_PROTECTION) +#elif defined(CONFIG_X86_STACK_PROTECTION) #define GS_TLS_SEG (0x28 | 0x03) #else #define GS_TLS_SEG (0x18 | 0x03) diff --git a/include/zephyr/arch/x86/ia32/scripts/shared_kernel_pages.ld b/include/zephyr/arch/x86/ia32/scripts/shared_kernel_pages.ld index 5d104e403ac..50dfb4f7abc 100644 --- a/include/zephyr/arch/x86/ia32/scripts/shared_kernel_pages.ld +++ b/include/zephyr/arch/x86/ia32/scripts/shared_kernel_pages.ld @@ -41,7 +41,7 @@ #ifdef CONFIG_USERSPACE #define GDT_NUM_ENTRIES 7 -#elif defined(CONFIG_HW_STACK_PROTECTION) +#elif defined(CONFIG_X86_STACK_PROTECTION) #define GDT_NUM_ENTRIES 5 #else #define GDT_NUM_ENTRIES 3 diff --git a/include/zephyr/arch/x86/thread_stack.h b/include/zephyr/arch/x86/thread_stack.h index a92b04846d4..6602d85784c 100644 --- a/include/zephyr/arch/x86/thread_stack.h +++ b/include/zephyr/arch/x86/thread_stack.h @@ -14,7 +14,7 @@ #define ARCH_STACK_PTR_ALIGN 4UL #endif -#if defined(CONFIG_HW_STACK_PROTECTION) || defined(CONFIG_USERSPACE) +#if defined(CONFIG_X86_STACK_PROTECTION) || defined(CONFIG_USERSPACE) #define Z_X86_STACK_BASE_ALIGN CONFIG_MMU_PAGE_SIZE #else #define Z_X86_STACK_BASE_ALIGN ARCH_STACK_PTR_ALIGN @@ -62,7 +62,7 @@ * privileged mode stack. */ struct z_x86_thread_stack_header { -#ifdef CONFIG_HW_STACK_PROTECTION +#ifdef CONFIG_X86_STACK_PROTECTION char guard_page[CONFIG_MMU_PAGE_SIZE]; #endif #ifdef CONFIG_USERSPACE @@ -78,7 +78,7 @@ struct z_x86_thread_stack_header { #define ARCH_THREAD_STACK_RESERVED \ sizeof(struct z_x86_thread_stack_header) -#ifdef CONFIG_HW_STACK_PROTECTION +#ifdef CONFIG_X86_STACK_PROTECTION #define ARCH_KERNEL_STACK_RESERVED CONFIG_MMU_PAGE_SIZE #define ARCH_KERNEL_STACK_OBJ_ALIGN CONFIG_MMU_PAGE_SIZE #else From 94997a026fc55a41c7d8ec481698f063dede40e2 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 29 Mar 2024 09:54:47 -0700 Subject: [PATCH 2100/2402] x86: correct size for stack bound check for privileged stack Previous commit changed the privileged stack size to be using kconfig CONFIG_PRIVILEGED_STACK_SIZE instead of simply CONFIG_MMU_PAGE_SIZE. However, the stack bound check function was still using the MMU page size, so fix that. Signed-off-by: Daniel Leung --- arch/x86/core/fatal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/core/fatal.c b/arch/x86/core/fatal.c index 517d2efa290..bd5e3a51d91 100644 --- a/arch/x86/core/fatal.c +++ b/arch/x86/core/fatal.c @@ -72,7 +72,7 @@ bool z_x86_check_stack_bounds(uintptr_t addr, size_t size, uint16_t cs) * If we get here, we must have been doing a syscall, check * privilege elevation stack bounds */ - start = _current->stack_info.start - CONFIG_MMU_PAGE_SIZE; + start = _current->stack_info.start - CONFIG_PRIVILEGED_STACK_SIZE; end = _current->stack_info.start; #endif /* CONFIG_USERSPACE */ } else { From 378131c266978bd56364463e9d9194b5c986622c Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 26 Mar 2024 11:54:31 -0700 Subject: [PATCH 2101/2402] kernel: add options to cleanup after aborting current thread This adds the mechanism to do cleanup after k_thread_abort() is called with the current thread. This is mainly used for cleaning up things when the thread cannot be running, e.g., cleanup the thread stack. Signed-off-by: Daniel Leung --- kernel/Kconfig | 7 +++ kernel/include/kernel_internal.h | 29 ++++++++++++ kernel/include/ksched.h | 1 + kernel/sched.c | 11 +++++ kernel/thread.c | 79 ++++++++++++++++++++++++++++++++ 5 files changed, 127 insertions(+) diff --git a/kernel/Kconfig b/kernel/Kconfig index 5668f382f0a..0db5d970668 100644 --- a/kernel/Kconfig +++ b/kernel/Kconfig @@ -197,6 +197,13 @@ config THREAD_ABORT_HOOK help Used by portability layers to modify locally managed status mask. +config THREAD_ABORT_NEED_CLEANUP + bool + help + This option enables the bits to clean up the current thread if + k_thread_abort(_current) is called, as the cleanup cannot be + running in the current thread stack. + config THREAD_CUSTOM_DATA bool "Thread custom data" help diff --git a/kernel/include/kernel_internal.h b/kernel/include/kernel_internal.h index a5e69b8935b..c598720999a 100644 --- a/kernel/include/kernel_internal.h +++ b/kernel/include/kernel_internal.h @@ -297,6 +297,35 @@ int z_kernel_stats_raw(struct k_obj_core *obj_core, void *stats); int z_kernel_stats_query(struct k_obj_core *obj_core, void *stats); #endif /* CONFIG_OBJ_CORE_STATS_SYSTEM */ +#if defined(CONFIG_THREAD_ABORT_NEED_CLEANUP) +/** + * Perform cleanup at the end of k_thread_abort(). + * + * This performs additional cleanup steps at the end of k_thread_abort() + * where these steps require that the thread is no longer running. + * If the target thread is not the current running thread, the cleanup + * steps will be performed immediately. However, if the target thread is + * the current running thread (e.g. k_thread_abort(_current)), it defers + * the cleanup steps to later when the work will be finished in another + * context. + * + * @param thread Pointer to thread to be cleaned up. + */ +void k_thread_abort_cleanup(struct k_thread *thread); + +/** + * Check if thread is the same as the one waiting for cleanup. + * + * This is used to guard against reusing the same thread object + * before the previous cleanup has finished. This will perform + * the necessary cleanups before the thread object can be + * reused. Should mainly be used during thread creation. + * + * @param thread Pointer to thread to be checked. + */ +void k_thread_abort_cleanup_check_reuse(struct k_thread *thread); +#endif /* CONFIG_THREAD_ABORT_NEED_CLEANUP */ + #ifdef __cplusplus } #endif diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index 1340a17b4e7..2943ee1e612 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -59,6 +59,7 @@ void z_sched_abort(struct k_thread *thread); void z_sched_ipi(void); void z_sched_start(struct k_thread *thread); void z_ready_thread(struct k_thread *thread); +void z_ready_thread_locked(struct k_thread *thread); void z_requeue_current(struct k_thread *curr); struct k_thread *z_swap_next_thread(void); void z_thread_abort(struct k_thread *thread); diff --git a/kernel/sched.c b/kernel/sched.c index 2fa45417ca6..10bc50cfeaa 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -417,6 +417,13 @@ static void ready_thread(struct k_thread *thread) } } +void z_ready_thread_locked(struct k_thread *thread) +{ + if (!thread_active_elsewhere(thread)) { + ready_thread(thread); + } +} + void z_ready_thread(struct k_thread *thread) { K_SPINLOCK(&_sched_spinlock) { @@ -1371,6 +1378,10 @@ static void halt_thread(struct k_thread *thread, uint8_t new_state) k_object_uninit(thread->stack_obj); k_object_uninit(thread); #endif /* CONFIG_USERSPACE */ + +#ifdef CONFIG_THREAD_ABORT_NEED_CLEANUP + k_thread_abort_cleanup(thread); +#endif /* CONFIG_THREAD_ABORT_NEED_CLEANUP */ } } diff --git a/kernel/thread.c b/kernel/thread.c index e31bed82c89..f6c65404630 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -487,6 +487,10 @@ char *z_setup_new_thread(struct k_thread *new_thread, Z_ASSERT_VALID_PRIO(prio, entry); +#ifdef CONFIG_THREAD_ABORT_NEED_CLEANUP + k_thread_abort_cleanup_check_reuse(new_thread); +#endif /* CONFIG_THREAD_ABORT_NEED_CLEANUP */ + #ifdef CONFIG_OBJ_CORE_THREAD k_obj_core_init_and_link(K_OBJ_CORE(new_thread), &obj_type_thread); #ifdef CONFIG_OBJ_CORE_STATS_THREAD @@ -950,3 +954,78 @@ int k_thread_runtime_stats_all_get(k_thread_runtime_stats_t *stats) return 0; } + +#ifdef CONFIG_THREAD_ABORT_NEED_CLEANUP +/** Pointer to thread which needs to be cleaned up. */ +static struct k_thread *thread_to_cleanup; + +/** Spinlock for thread abort cleanup. */ +static struct k_spinlock thread_cleanup_lock; + +void defer_thread_cleanup(struct k_thread *thread) +{ + /* Note when adding new deferred cleanup steps: + * - The thread object may have been overwritten by the time + * the actual cleanup is being done (e.g. thread object + * allocated on a stack). So stash any necessary data here + * that will be used in the actual cleanup steps. + */ + thread_to_cleanup = thread; +} + +void do_thread_cleanup(struct k_thread *thread) +{ + /* Note when adding new actual cleanup steps: + * - The thread object may have been overwritten when this is + * called. So avoid using any data from the thread object. + */ + ARG_UNUSED(thread); +} + +void k_thread_abort_cleanup(struct k_thread *thread) +{ + K_SPINLOCK(&thread_cleanup_lock) { + if (thread_to_cleanup != NULL) { + /* Finish the pending one first. */ + do_thread_cleanup(thread_to_cleanup); + thread_to_cleanup = NULL; + } + + if (thread == _current) { + /* Need to defer for current running thread as the cleanup + * might result in exception. Actual cleanup will be done + * at the next time k_thread_abort() is called, or at thread + * creation if the same thread object is being reused. This + * is to make sure the cleanup code no longer needs this + * thread's stack. This is not exactly ideal as the stack + * may still be memory mapped for a while. However, this is + * a simple solution without a) the need to workaround + * the schedule lock during k_thread_abort(), b) creating + * another thread to perform the cleanup, and c) does not + * require architecture code support (e.g. via exception). + */ + defer_thread_cleanup(thread); + } else { + /* Not the current running thread, so we are safe to do + * cleanups. + */ + do_thread_cleanup(thread); + } + } +} + +void k_thread_abort_cleanup_check_reuse(struct k_thread *thread) +{ + K_SPINLOCK(&thread_cleanup_lock) { + /* This is to guard reuse of the same thread object and make sure + * any pending cleanups of it needs to be finished before the thread + * object can be reused. + */ + if (thread_to_cleanup == thread) { + do_thread_cleanup(thread_to_cleanup); + thread_to_cleanup = NULL; + } + } +} + +#endif /* CONFIG_THREAD_ABORT_NEED_CLEANUP */ From 04c5632bd4ab935a07d362c3745080b20d3c4603 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 6 Mar 2024 15:58:37 -0800 Subject: [PATCH 2102/2402] kernel: mm: introduce k_mem_phys_map()/_unmap() This is similar to k_mem_map()/_unmap(). But instead of using anonymous memory, the provided physical region is mapped into virtual address instead. In addition to simple mapping physical ro virtual addresses, the mapping also adds two guard pages before and after the virtual region to catch buffer under-/over-flow. Signed-off-by: Daniel Leung --- include/zephyr/kernel/internal/mm.h | 41 +++++++++ include/zephyr/kernel/mm.h | 77 +++++++++++++++- kernel/mmu.c | 131 +++++++++++++++++----------- 3 files changed, 194 insertions(+), 55 deletions(-) diff --git a/include/zephyr/kernel/internal/mm.h b/include/zephyr/kernel/internal/mm.h index abb393e3d67..d4183753415 100644 --- a/include/zephyr/kernel/internal/mm.h +++ b/include/zephyr/kernel/internal/mm.h @@ -205,6 +205,47 @@ void z_phys_map(uint8_t **virt_ptr, uintptr_t phys, size_t size, */ void z_phys_unmap(uint8_t *virt, size_t size); +/** + * Map memory into virtual address space with guard pages. + * + * This maps memory into virtual address space with a preceding and + * a succeeding guard pages. + * + * @see k_mem_map() for additional information if called via that. + * + * @see k_mem_phys_map() for additional information if called via that. + * + * @param phys Physical address base of the memory region if not requesting + * anonymous memory. Must be page-aligned. + * @param size Size of the memory mapping. This must be page-aligned. + * @param flags K_MEM_PERM_*, K_MEM_MAP_* control flags. + * @param is_anon True is requesting mapping with anonymous memory. + * + * @return The mapped memory location, or NULL if insufficient virtual address + * space, insufficient physical memory to establish the mapping, + * or insufficient memory for paging structures. + */ +void *k_mem_map_impl(uintptr_t phys, size_t size, uint32_t flags, bool is_anon); + +/** + * Un-map mapped memory + * + * This removes the memory mappings for the provided page-aligned region, + * and the two guard pages surrounding the region. + * + * @see k_mem_unmap() for additional information if called via that. + * + * @see k_mem_phys_unmap() for additional information if called via that. + * + * @note Calling this function on a region which was not mapped to begin + * with is undefined behavior. + * + * @param addr Page-aligned memory region base virtual address + * @param size Page-aligned memory region size + * @param is_anon True if the mapped memory is from anonymous memory. + */ +void k_mem_unmap_impl(void *addr, size_t size, bool is_anon); + #ifdef __cplusplus } #endif diff --git a/include/zephyr/kernel/mm.h b/include/zephyr/kernel/mm.h index b391bdbab19..90dd7535483 100644 --- a/include/zephyr/kernel/mm.h +++ b/include/zephyr/kernel/mm.h @@ -168,7 +168,54 @@ size_t k_mem_free_get(void); * space, insufficient physical memory to establish the mapping, * or insufficient memory for paging structures. */ -void *k_mem_map(size_t size, uint32_t flags); +static inline void *k_mem_map(size_t size, uint32_t flags) +{ + return k_mem_map_impl((uintptr_t)NULL, size, flags, true); +} + +/** + * Map a physical memory region into kernel's virtual address space with guard pages. + * + * This function maps a contiguous physical memory region into kernel's + * virtual address space. Given a physical address and a size, return a + * linear address representing the base of where the physical region is mapped + * in the virtual address space for the Zephyr kernel. + * + * This function alters the active page tables in the area reserved + * for the kernel. This function will choose the virtual address + * and return it to the caller. + * + * If user thread access control needs to be managed in any way, do not enable + * K_MEM_PERM_USER flags here; instead manage the region's permissions + * with memory domain APIs after the mapping has been established. Setting + * K_MEM_PERM_USER here will allow all user threads to access this memory + * which is usually undesirable. + * + * Unless K_MEM_MAP_UNINIT is used, the returned memory will be zeroed. + * + * The returned virtual memory pointer will be page-aligned. The size + * parameter, and any base address for re-mapping purposes must be page- + * aligned. + * + * Note that the allocation includes two guard pages immediately before + * and after the requested region. The total size of the allocation will be + * the requested size plus the size of these two guard pages. + * + * Many K_MEM_MAP_* flags have been implemented to alter the behavior of this + * function, with details in the documentation for these flags. + * + * @param phys Physical address base of the memory region. + * This must be page-aligned. + * @param size Size of the memory mapping. This must be page-aligned. + * @param flags K_MEM_PERM_*, K_MEM_MAP_* control flags. + * + * @return The mapped memory location, or NULL if insufficient virtual address + * space or insufficient memory for paging structures. + */ +static inline void *k_mem_phys_map(uintptr_t phys, size_t size, uint32_t flags) +{ + return k_mem_map_impl(phys, size, flags, false); +} /** * Un-map mapped memory @@ -183,7 +230,33 @@ void *k_mem_map(size_t size, uint32_t flags); * @param addr Page-aligned memory region base virtual address * @param size Page-aligned memory region size */ -void k_mem_unmap(void *addr, size_t size); +static inline void k_mem_unmap(void *addr, size_t size) +{ + k_mem_unmap_impl(addr, size, true); +} + +/** + * Un-map memory mapped via k_mem_phys_map(). + * + * This unmaps a virtual memory region from kernel's virtual address space. + * + * This function alters the active page tables in the area reserved + * for the kernel. + * + * This removes a memory mapping for the provided page-aligned region + * and the guard pages. The kernel may re-use the associated virtual address + * region later. + * + * @note Calling this function on a region which was not mapped via + * k_mem_phys_map() to begin with is undefined behavior. + * + * @param addr Page-aligned memory region base virtual address + * @param size Page-aligned memory region size + */ +static inline void k_mem_phys_unmap(void *addr, size_t size) +{ + k_mem_unmap_impl(addr, size, false); +} /** * Given an arbitrary region, provide a aligned region that covers it diff --git a/kernel/mmu.c b/kernel/mmu.c index 6cb444f629d..4d364a1b0a6 100644 --- a/kernel/mmu.c +++ b/kernel/mmu.c @@ -513,7 +513,6 @@ static int map_anon_page(void *addr, uint32_t flags) struct z_page_frame *pf; uintptr_t phys; bool lock = (flags & K_MEM_MAP_LOCK) != 0U; - bool uninit = (flags & K_MEM_MAP_UNINIT) != 0U; pf = free_page_frame_list_get(); if (pf == NULL) { @@ -549,23 +548,17 @@ static int map_anon_page(void *addr, uint32_t flags) LOG_DBG("memory mapping anon page %p -> 0x%lx", addr, phys); - if (!uninit) { - /* If we later implement mappings to a copy-on-write - * zero page, won't need this step - */ - memset(addr, 0, CONFIG_MMU_PAGE_SIZE); - } - return 0; } -void *k_mem_map(size_t size, uint32_t flags) +void *k_mem_map_impl(uintptr_t phys, size_t size, uint32_t flags, bool is_anon) { uint8_t *dst; size_t total_size; int ret; k_spinlock_key_t key; uint8_t *pos; + bool uninit = (flags & K_MEM_MAP_UNINIT) != 0U; __ASSERT(!(((flags & K_MEM_PERM_USER) != 0U) && ((flags & K_MEM_MAP_UNINIT) != 0U)), @@ -573,7 +566,8 @@ void *k_mem_map(size_t size, uint32_t flags) __ASSERT(size % CONFIG_MMU_PAGE_SIZE == 0U, "unaligned size %zu passed to %s", size, __func__); __ASSERT(size != 0, "zero sized memory mapping"); - __ASSERT(page_frames_initialized, "%s called too early", __func__); + __ASSERT(!is_anon || (is_anon && page_frames_initialized), + "%s called too early", __func__); __ASSERT((flags & K_MEM_CACHE_MASK) == 0U, "%s does not support explicit cache settings", __func__); @@ -605,24 +599,43 @@ void *k_mem_map(size_t size, uint32_t flags) /* Skip over the "before" guard page in returned address. */ dst += CONFIG_MMU_PAGE_SIZE; - VIRT_FOREACH(dst, size, pos) { - ret = map_anon_page(pos, flags); - - if (ret != 0) { - /* TODO: call k_mem_unmap(dst, pos - dst) when - * implemented in #28990 and release any guard virtual - * page as well. - */ - dst = NULL; - goto out; + if (is_anon) { + /* Mapping from annoymous memory */ + VIRT_FOREACH(dst, size, pos) { + ret = map_anon_page(pos, flags); + + if (ret != 0) { + /* TODO: call k_mem_unmap(dst, pos - dst) when + * implemented in #28990 and release any guard virtual + * page as well. + */ + dst = NULL; + goto out; + } } + } else { + /* Mapping known physical memory. + * + * arch_mem_map() is a void function and does not return + * anything. Arch code usually uses ASSERT() to catch + * mapping errors. Assume this works correctly for now. + */ + arch_mem_map(dst, phys, size, flags); } + + if (!uninit) { + /* If we later implement mappings to a copy-on-write + * zero page, won't need this step + */ + memset(dst, 0, size); + } + out: k_spin_unlock(&z_mm_lock, key); return dst; } -void k_mem_unmap(void *addr, size_t size) +void k_mem_unmap_impl(void *addr, size_t size, bool is_anon) { uintptr_t phys; uint8_t *pos; @@ -663,43 +676,55 @@ void k_mem_unmap(void *addr, size_t size) goto out; } - VIRT_FOREACH(addr, size, pos) { - ret = arch_page_phys_get(pos, &phys); - - __ASSERT(ret == 0, - "%s: cannot unmap an unmapped address %p", - __func__, pos); - if (ret != 0) { - /* Found an address not mapped. Do not continue. */ - goto out; - } + if (is_anon) { + /* Unmapping anonymous memory */ + VIRT_FOREACH(addr, size, pos) { + ret = arch_page_phys_get(pos, &phys); + + __ASSERT(ret == 0, + "%s: cannot unmap an unmapped address %p", + __func__, pos); + if (ret != 0) { + /* Found an address not mapped. Do not continue. */ + goto out; + } - __ASSERT(z_is_page_frame(phys), - "%s: 0x%lx is not a page frame", __func__, phys); - if (!z_is_page_frame(phys)) { - /* Physical address has no corresponding page frame - * description in the page frame array. - * This should not happen. Do not continue. - */ - goto out; - } + __ASSERT(z_is_page_frame(phys), + "%s: 0x%lx is not a page frame", __func__, phys); + if (!z_is_page_frame(phys)) { + /* Physical address has no corresponding page frame + * description in the page frame array. + * This should not happen. Do not continue. + */ + goto out; + } - /* Grab the corresponding page frame from physical address */ - pf = z_phys_to_page_frame(phys); + /* Grab the corresponding page frame from physical address */ + pf = z_phys_to_page_frame(phys); - __ASSERT(z_page_frame_is_mapped(pf), - "%s: 0x%lx is not a mapped page frame", __func__, phys); - if (!z_page_frame_is_mapped(pf)) { - /* Page frame is not marked mapped. - * This should not happen. Do not continue. - */ - goto out; - } + __ASSERT(z_page_frame_is_mapped(pf), + "%s: 0x%lx is not a mapped page frame", __func__, phys); + if (!z_page_frame_is_mapped(pf)) { + /* Page frame is not marked mapped. + * This should not happen. Do not continue. + */ + goto out; + } - arch_mem_unmap(pos, CONFIG_MMU_PAGE_SIZE); + arch_mem_unmap(pos, CONFIG_MMU_PAGE_SIZE); - /* Put the page frame back into free list */ - page_frame_free_locked(pf); + /* Put the page frame back into free list */ + page_frame_free_locked(pf); + } + } else { + /* + * Unmapping previous mapped memory with specific physical address. + * + * Note that we don't have to unmap the guard pages, as they should + * have been unmapped. We just need to unmapped the in-between + * region [addr, (addr + size)). + */ + arch_mem_unmap(addr, size); } /* There are guard pages just before and after the mapped From d0a90a0b337f4d09060921e500d7ec3d66f93b8c Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Mon, 18 Mar 2024 15:58:48 -0700 Subject: [PATCH 2103/2402] kernel: add the ability to memory map thread stacks This introduces support for memory mapped thread stacks, where each thread stack is mapped into virtual memory address space with two guard pages to catch under-/over-flowing the stack. This is just on the kernel side. Additional architecture code is required to fully support this feature. Signed-off-by: Daniel Leung --- arch/Kconfig | 5 +++ include/zephyr/kernel/thread.h | 19 ++++++++- kernel/Kconfig | 10 +++++ kernel/thread.c | 77 ++++++++++++++++++++++++++++++++++ 4 files changed, 110 insertions(+), 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index a746044362a..cec29eb3c40 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -654,6 +654,11 @@ config ARCH_HAS_SUSPEND_TO_RAM config ARCH_HAS_STACK_CANARIES_TLS bool +config ARCH_SUPPORTS_MEM_MAPPED_STACKS + bool + help + Select when the architecture supports memory mapped stacks. + # # Other architecture related options # diff --git a/include/zephyr/kernel/thread.h b/include/zephyr/kernel/thread.h index 062e4a36ecb..cbbb35aa7d6 100644 --- a/include/zephyr/kernel/thread.h +++ b/include/zephyr/kernel/thread.h @@ -171,6 +171,16 @@ struct _thread_stack_info { * is the initial stack pointer for a thread. May be 0. */ size_t delta; + +#if defined(CONFIG_THREAD_STACK_MEM_MAPPED) + struct { + /** Base address of the memory mapped thread stack */ + k_thread_stack_t *addr; + + /** Size of whole mapped stack object */ + size_t sz; + } mapped; +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ }; typedef struct _thread_stack_info _thread_stack_info_t; @@ -311,8 +321,15 @@ struct k_thread { #if defined(CONFIG_USERSPACE) /** memory domain info of the thread */ struct _mem_domain_info mem_domain_info; - /** Base address of thread stack */ + + /** + * Base address of thread stack. + * + * If memory mapped stack (CONFIG_THREAD_STACK_MEM_MAPPED) + * is enabled, this is the physical address of the stack. + */ k_thread_stack_t *stack_obj; + /** current syscall frame pointer */ void *syscall_frame; #endif /* CONFIG_USERSPACE */ diff --git a/kernel/Kconfig b/kernel/Kconfig index 0db5d970668..8114a7b84dc 100644 --- a/kernel/Kconfig +++ b/kernel/Kconfig @@ -192,6 +192,16 @@ config THREAD_STACK_INFO This option allows each thread to store the thread stack info into the k_thread data structure. +config THREAD_STACK_MEM_MAPPED + bool "Stack to be memory mapped at runtime" + depends on MMU && ARCH_SUPPORTS_MEM_MAPPED_STACKS + select THREAD_STACK_INFO + select THREAD_ABORT_NEED_CLEANUP + help + This option changes behavior where the thread stack is memory + mapped with guard pages on both ends to catch undesired + accesses. + config THREAD_ABORT_HOOK bool help diff --git a/kernel/thread.c b/kernel/thread.c index f6c65404630..981a048bb0d 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -419,11 +419,47 @@ static char *setup_thread_stack(struct k_thread *new_thread, } +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + /* Map the stack into virtual memory and use that as the base to + * calculate the initial stack pointer at the high end of the stack + * object. The stack pointer may be reduced later in this function + * by TLS or random offset. + * + * K_MEM_MAP_UNINIT is used to mimic the behavior of non-mapped + * stack. If CONFIG_INIT_STACKS is enabled, the stack will be + * cleared below. + */ + void *stack_mapped = k_mem_phys_map((uintptr_t)stack, stack_obj_size, + K_MEM_PERM_RW | K_MEM_CACHE_WB | K_MEM_MAP_UNINIT); + + __ASSERT_NO_MSG((uintptr_t)stack_mapped != 0); + +#ifdef CONFIG_USERSPACE + if (z_stack_is_user_capable(stack)) { + stack_buf_start = K_THREAD_STACK_BUFFER(stack_mapped); + } else +#endif /* CONFIG_USERSPACE */ + { + stack_buf_start = K_KERNEL_STACK_BUFFER(stack_mapped); + } + + stack_ptr = (char *)stack_mapped + stack_obj_size; + + /* Need to store the info on mapped stack so we can remove the mappings + * when the thread ends. + */ + new_thread->stack_info.mapped.addr = stack_mapped; + new_thread->stack_info.mapped.sz = stack_obj_size; + +#else /* CONFIG_THREAD_STACK_MEM_MAPPED */ + /* Initial stack pointer at the high end of the stack object, may * be reduced later in this function by TLS or random offset */ stack_ptr = (char *)stack + stack_obj_size; +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ + LOG_DBG("stack %p for thread %p: obj_size=%zu buf_start=%p " " buf_size %zu stack_ptr=%p", stack, new_thread, stack_obj_size, (void *)stack_buf_start, @@ -825,6 +861,12 @@ int z_stack_space_get(const uint8_t *stack_start, size_t size, size_t *unused_pt int z_impl_k_thread_stack_space_get(const struct k_thread *thread, size_t *unused_ptr) { +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + if (thread->stack_info.mapped.addr == NULL) { + return -EINVAL; + } +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ + return z_stack_space_get((const uint8_t *)thread->stack_info.start, thread->stack_info.size, unused_ptr); } @@ -962,6 +1004,11 @@ static struct k_thread *thread_to_cleanup; /** Spinlock for thread abort cleanup. */ static struct k_spinlock thread_cleanup_lock; +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED +static void *thread_cleanup_stack_addr; +static size_t thread_cleanup_stack_sz; +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ + void defer_thread_cleanup(struct k_thread *thread) { /* Note when adding new deferred cleanup steps: @@ -971,6 +1018,27 @@ void defer_thread_cleanup(struct k_thread *thread) * that will be used in the actual cleanup steps. */ thread_to_cleanup = thread; + +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + /* Note that the permission of the stack should have been + * stripped of user thread access due to the thread having + * already exited from a memory domain. That is done via + * k_thread_abort(). + */ + + /* Stash the address and size so the region can be unmapped + * later. + */ + thread_cleanup_stack_addr = thread->stack_info.mapped.addr; + thread_cleanup_stack_sz = thread->stack_info.mapped.sz; + + /* The stack is now considered un-usable. This should prevent any functions + * from looking directly into the mapped stack if they are made to be aware + * of memory mapped stacks, e.g., z_stack_space_get(). + */ + thread->stack_info.mapped.addr = NULL; + thread->stack_info.mapped.sz = 0; +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ } void do_thread_cleanup(struct k_thread *thread) @@ -980,6 +1048,15 @@ void do_thread_cleanup(struct k_thread *thread) * called. So avoid using any data from the thread object. */ ARG_UNUSED(thread); + +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + if (thread_cleanup_stack_addr != NULL) { + k_mem_phys_unmap(thread_cleanup_stack_addr, + thread_cleanup_stack_sz); + + thread_cleanup_stack_addr = NULL; + } +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ } void k_thread_abort_cleanup(struct k_thread *thread) From 0b3a4f35d010a1a1d3703e8bcd9dcd33264c59bb Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 13 Mar 2024 13:45:31 -0700 Subject: [PATCH 2104/2402] tests: mem_protect/userspace: extend tests for mapped stack This extends the test for memory mapped stack, as the address of memory mapped stack object would be different than the actual stack object. Signed-off-by: Daniel Leung --- tests/kernel/mem_protect/userspace/src/main.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/tests/kernel/mem_protect/userspace/src/main.c b/tests/kernel/mem_protect/userspace/src/main.c index edf5e8cd687..cd66c06ab7a 100644 --- a/tests/kernel/mem_protect/userspace/src/main.c +++ b/tests/kernel/mem_protect/userspace/src/main.c @@ -1060,6 +1060,9 @@ void tls_entry(void *p1, void *p2, void *p3) ZTEST(userspace, test_tls_pointer) { #ifdef CONFIG_THREAD_USERSPACE_LOCAL_DATA + char *stack_obj_ptr; + size_t stack_obj_sz; + k_thread_create(&test_thread, test_stack, STACKSIZE, tls_entry, NULL, NULL, NULL, 1, K_USER, K_FOREVER); @@ -1071,15 +1074,23 @@ ZTEST(userspace, test_tls_pointer) (void *)(test_thread.stack_info.start + test_thread.stack_info.size)); +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + stack_obj_ptr = (char *)test_thread.stack_obj_mapped; + stack_obj_sz = test_thread.stack_obj_size; +#else + stack_obj_ptr = (char *)test_stack; + stack_obj_sz = sizeof(test_stack); +#endif + printk("stack object bounds: [%p, %p)\n", - test_stack, test_stack + sizeof(test_stack)); + stack_obj_ptr, stack_obj_ptr + stack_obj_sz); uintptr_t tls_start = (uintptr_t)test_thread.userspace_local_data; uintptr_t tls_end = tls_start + sizeof(struct _thread_userspace_local_data); - if ((tls_start < (uintptr_t)test_stack) || - (tls_end > (uintptr_t)test_stack + sizeof(test_stack))) { + if ((tls_start < (uintptr_t)stack_obj_ptr) || + (tls_end > (uintptr_t)stack_obj_ptr + stack_obj_sz)) { printk("tls area out of bounds\n"); ztest_test_fail(); } From cfbbcac3f7a48777558ec5d620323212290a6db0 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Thu, 14 Mar 2024 12:49:45 -0700 Subject: [PATCH 2105/2402] tests: threads/thread_stack: extend tests for mapped stack This extends the test for memory mapped stack, as the address of memory mapped stack object would be different than the actual stack object. Signed-off-by: Daniel Leung --- tests/kernel/threads/thread_stack/src/main.c | 40 +++++++++++++++++--- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/tests/kernel/threads/thread_stack/src/main.c b/tests/kernel/threads/thread_stack/src/main.c index cf9b5d8c3a5..ad14e92bdfb 100644 --- a/tests/kernel/threads/thread_stack/src/main.c +++ b/tests/kernel/threads/thread_stack/src/main.c @@ -66,6 +66,10 @@ static inline int z_vrfy_check_perms(void *addr, size_t size, int write) ZTEST_BMEM struct scenario_data { k_thread_stack_t *stack; +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + k_thread_stack_t *stack_mapped; +#endif + /* If this was declared with K_THREAD_STACK_DEFINE and not * K_KERNEL_STACK_DEFINE */ @@ -89,7 +93,7 @@ ZTEST_BMEM struct scenario_data { void stack_buffer_scenarios(void) { - k_thread_stack_t *stack_obj = scenario_data.stack; + k_thread_stack_t *stack_obj; size_t obj_size = scenario_data.object_size; size_t stack_size, unused, carveout, reserved, alignment, adjusted; uint8_t val = 0; @@ -97,10 +101,18 @@ void stack_buffer_scenarios(void) char *stack_buf; volatile char *pos; int ret, expected; - uintptr_t base = (uintptr_t)stack_obj; + uintptr_t base; bool is_usermode; long int end_space; +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + stack_obj = scenario_data.stack_mapped; +#else + stack_obj = scenario_data.stack; +#endif + + base = (uintptr_t)stack_obj; + #ifdef CONFIG_USERSPACE is_usermode = arch_is_user_context(); #else @@ -211,8 +223,10 @@ void stack_buffer_scenarios(void) stack_size); } #endif + carveout = stack_start - stack_buf; printk(" - Carved-out space in buffer: %zu\n", carveout); + zassert_true(carveout < stack_size, "Suspicious carve-out space reported"); /* 0 unless this is a stack array */ @@ -318,12 +332,28 @@ void stest_thread_launch(uint32_t flags, bool drop) k_thread_create(&test_thread, scenario_data.stack, STEST_STACKSIZE, stest_thread_entry, (void *)drop, NULL, NULL, - -1, flags, K_NO_WAIT); + -1, flags, K_FOREVER); + +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + scenario_data.stack_mapped = test_thread.stack_info.mapped.addr; + + printk(" - Memory mapped stack object %p\n", scenario_data.stack_mapped); +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ + + k_thread_start(&test_thread); k_thread_join(&test_thread, K_FOREVER); ret = k_thread_stack_space_get(&test_thread, &unused); - zassert_equal(ret, 0, "failed to calculate unused stack space\n"); - printk("target thread unused stack space: %zu\n", unused); + +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + if (ret == -EINVAL) { + printk("! cannot report unused stack space due to stack no longer mapped.\n"); + } else +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ + { + zassert_equal(ret, 0, "failed to calculate unused stack space\n"); + printk("target thread unused stack space: %zu\n", unused); + } } void scenario_entry(void *stack_obj, size_t obj_size, size_t reported_size, From b60e09062d4c83c2e70fefb5f26110089cb2699f Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 27 Mar 2024 15:00:27 -0700 Subject: [PATCH 2106/2402] cmsis_rtos_v1: support memory mapped stack at abort hook This extends the thread abort hook to support memory mapped stack. The calculation to find out to which instance of thread pools the outgoing thread belongs requires physical address. So find the physical address via the memory mapped stack for that. Signed-off-by: Daniel Leung --- subsys/portability/cmsis_rtos_v1/cmsis_thread.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/subsys/portability/cmsis_rtos_v1/cmsis_thread.c b/subsys/portability/cmsis_rtos_v1/cmsis_thread.c index 6ce53fe7192..41752a51795 100644 --- a/subsys/portability/cmsis_rtos_v1/cmsis_thread.c +++ b/subsys/portability/cmsis_rtos_v1/cmsis_thread.c @@ -47,7 +47,17 @@ void thread_abort_hook(struct k_thread *thread) if (thread_def != NULL) { /* get thread instance index according to stack address */ - offset = thread->stack_info.start - (uintptr_t)thread_def->stack_mem; + uintptr_t stack_start; + +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + /* The offset calculation below requires physical address. */ + extern int arch_page_phys_get(void *virt, uintptr_t *phys); + (void)arch_page_phys_get((void *)thread->stack_info.start, &stack_start); +#else + stack_start = thread->stack_info.start; +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ + + offset = stack_start - (uintptr_t)thread_def->stack_mem; instance = offset / K_THREAD_STACK_LEN(CONFIG_CMSIS_THREAD_MAX_STACK_SIZE); sys_bitarray_clear_bit((sys_bitarray_t *)(thread_def->status_mask), instance); } From e7554117b71d868d9910e02f3ba324b2c1856c4d Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Mon, 1 Apr 2024 11:51:35 -0700 Subject: [PATCH 2107/2402] tests: mem_protect/stackprot: test mapped stack This extends the mem_protect/stackprot tests to support testing with memory mapped stack. Signed-off-by: Daniel Leung --- .../mem_protect/stackprot/src/mapped_stack.c | 151 ++++++++++++++++++ 1 file changed, 151 insertions(+) create mode 100644 tests/kernel/mem_protect/stackprot/src/mapped_stack.c diff --git a/tests/kernel/mem_protect/stackprot/src/mapped_stack.c b/tests/kernel/mem_protect/stackprot/src/mapped_stack.c new file mode 100644 index 00000000000..434d0cc98eb --- /dev/null +++ b/tests/kernel/mem_protect/stackprot/src/mapped_stack.c @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + +#define STACK_SIZE (CONFIG_MMU_PAGE_SIZE + CONFIG_TEST_EXTRA_STACK_SIZE) + +K_THREAD_STACK_DEFINE(mapped_thread_stack_area, STACK_SIZE); +static struct k_thread mapped_thread_data; + +ZTEST_BMEM static char *mapped_stack_addr; +ZTEST_BMEM static size_t mapped_stack_sz; + +/** + * @brief To cause fault in guard pages. + * + * @param p1 0 if testing rear guard page, 1 if testing front guard page. + * @param p2 Unused. + * @param p3 Unused. + */ +void mapped_thread(void *p1, void *p2, void *p3) +{ + bool is_front = p1 == NULL ? false : true; + volatile char *ptr; + + ARG_UNUSED(p2); + ARG_UNUSED(p3); + + TC_PRINT("Starts %s\n", __func__); + TC_PRINT("Mapped stack %p size %zu\n", mapped_stack_addr, mapped_stack_sz); + + ptr = mapped_stack_addr; + + /* Figure out where to cause the stack fault. */ + if (is_front) { + /* Middle of front guard page. */ + ptr -= CONFIG_MMU_PAGE_SIZE / 2; + } else { + /* Middle of rear guard page. */ + ptr += mapped_stack_sz; + ptr += CONFIG_MMU_PAGE_SIZE / 2; + } + + TC_PRINT("Trying to cause stack fault at %p\n", ptr); + + *ptr = 0; + + TC_PRINT("Should have fault on guard page but not!\n"); + ztest_test_fail(); +} + +/** + * @brief To create thread to fault on guard pages. + * + * @param is_front True if testing front guard page, false if testing rear guard page. + * @param is_user True if creating a user thread, false if creating a kernel thread. + */ +void create_thread(bool is_front, bool is_user) +{ + /* Start thread */ + k_thread_create(&mapped_thread_data, mapped_thread_stack_area, STACK_SIZE, + mapped_thread, + is_front ? (void *)1 : (void *)0, + NULL, NULL, + K_PRIO_COOP(1), is_user ? K_USER : 0, K_FOREVER); + + zassert_true(mapped_thread_data.stack_info.mapped.addr != NULL); + + /* Grab the mapped stack object address and size so we can calculate + * where to cause a stack fault. + */ + mapped_stack_addr = (void *)mapped_thread_data.stack_info.mapped.addr; + mapped_stack_sz = mapped_thread_data.stack_info.mapped.sz; + + k_thread_start(&mapped_thread_data); + + /* Note that this sleep is required on SMP platforms where + * that thread will execute asynchronously! + */ + k_sleep(K_MSEC(100)); + + k_thread_join(&mapped_thread_data, K_FOREVER); +} + +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ + +/** + * @brief Test faulting on front guard page + * + * @ingroup kernel_memprotect_tests + */ +ZTEST(stackprot_mapped_stack, test_guard_page_front) +{ +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + create_thread(true, false); +#else + ztest_test_skip(); +#endif +} + +/** + * @brief Test faulting on rear guard page + * + * @ingroup kernel_memprotect_tests + */ +ZTEST(stackprot_mapped_stack, test_guard_page_rear) +{ +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + create_thread(false, false); +#else + ztest_test_skip(); +#endif +} + +/** + * @brief Test faulting on front guard page in user mode + * + * @ingroup kernel_memprotect_tests + */ +ZTEST(stackprot_mapped_stack, test_guard_page_front_user) +{ +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + create_thread(true, true); +#else + ztest_test_skip(); +#endif +} + +/** + * @brief Test faulting on rear guard page in user mode + * + * @ingroup kernel_memprotect_tests + */ +ZTEST(stackprot_mapped_stack, test_guard_page_rear_user) +{ +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + create_thread(false, true); +#else + ztest_test_skip(); +#endif +} + + +ZTEST_SUITE(stackprot_mapped_stack, NULL, NULL, NULL, NULL, NULL); From 414250d013a15651f3f945f5575cf477d99dded0 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Thu, 28 Mar 2024 12:01:43 -0700 Subject: [PATCH 2108/2402] boards: qemu_x86/atom/virt: forcibly disable memory mapped stack The current memory mapped stack code requires actual physical addresses for stacks, and cannot deal with stacks already using virtual addresses. So disable mapped stack via defconfig. Note that this is done before enabling memory mapped stacks on x86 so test won't fail when the support in the architecture code is introduced. Signed-off-by: Daniel Leung --- boards/qemu/x86/qemu_x86_atom_virt_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/boards/qemu/x86/qemu_x86_atom_virt_defconfig b/boards/qemu/x86/qemu_x86_atom_virt_defconfig index c06824e6004..f4a79e4d306 100644 --- a/boards/qemu/x86/qemu_x86_atom_virt_defconfig +++ b/boards/qemu/x86/qemu_x86_atom_virt_defconfig @@ -20,3 +20,9 @@ CONFIG_KERNEL_VM_OFFSET=0 CONFIG_LINKER_USE_BOOT_SECTION=y CONFIG_LINKER_USE_PINNED_SECTION=y + +# For now, the mapped stacks require physical addresses +# and cannot deal with mapping a stack with virtual +# address. So make sure memory mapped stack is not +# enabled. +CONFIG_THREAD_STACK_MEM_MAPPED=n From 027a1c30cd4423ab26575e6285efadecb13a00cc Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Mon, 1 Apr 2024 13:05:43 -0700 Subject: [PATCH 2109/2402] x86: add support for memory mapped stack for threads This adds the necessary bits to enable memory mapping thread stacks on both x86 and x86_64. Note that currently these do not support multi level mappings (e.g. demand paging and running in virtual address space: qemu_x86/atom/virt board) as the mapped stacks require actual physical addresses. Signed-off-by: Daniel Leung --- arch/Kconfig | 1 + arch/x86/core/Kconfig.ia32 | 1 + arch/x86/core/Kconfig.intel64 | 1 + arch/x86/core/fatal.c | 42 ++++++++++++++++++++++++++ arch/x86/core/ia32/thread.c | 5 ++- arch/x86/core/intel64/thread.c | 5 ++- arch/x86/core/userspace.c | 5 +++ include/zephyr/arch/x86/thread_stack.h | 33 +++++++++++++++++--- 8 files changed, 87 insertions(+), 6 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index cec29eb3c40..a800d220b58 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -91,6 +91,7 @@ config X86 && !BOARD_HAS_TIMING_FUNCTIONS \ && !SOC_HAS_TIMING_FUNCTIONS select ARCH_HAS_STACK_CANARIES_TLS + select ARCH_SUPPORTS_MEM_MAPPED_STACKS if X86_MMU && !DEMAND_PAGING help x86 architecture diff --git a/arch/x86/core/Kconfig.ia32 b/arch/x86/core/Kconfig.ia32 index b24981c0606..d789c87eb80 100644 --- a/arch/x86/core/Kconfig.ia32 +++ b/arch/x86/core/Kconfig.ia32 @@ -67,6 +67,7 @@ config X86_STACK_PROTECTION select SET_GDT select GDT_DYNAMIC select X86_ENABLE_TSS + imply THREAD_STACK_MEM_MAPPED if !DEMAND_PAGING help This option leverages the MMU to cause a system fatal error if the bounds of the current process stack are overflowed. This is done diff --git a/arch/x86/core/Kconfig.intel64 b/arch/x86/core/Kconfig.intel64 index 64021959034..913bb0e794d 100644 --- a/arch/x86/core/Kconfig.intel64 +++ b/arch/x86/core/Kconfig.intel64 @@ -73,6 +73,7 @@ config X86_STACK_PROTECTION bool default y if HW_STACK_PROTECTION select THREAD_STACK_INFO + imply THREAD_STACK_MEM_MAPPED help This option leverages the MMU to cause a system fatal error if the bounds of the current process stack are overflowed. This is done diff --git a/arch/x86/core/fatal.c b/arch/x86/core/fatal.c index bd5e3a51d91..370386d4af9 100644 --- a/arch/x86/core/fatal.c +++ b/arch/x86/core/fatal.c @@ -86,6 +86,40 @@ bool z_x86_check_stack_bounds(uintptr_t addr, size_t size, uint16_t cs) } #endif +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED +/** + * Check if the fault is in the guard pages. + * + * @param addr Address to be tested. + * + * @return True Address is in guard pages, false otherwise. + */ +__pinned_func +bool z_x86_check_guard_page(uintptr_t addr) +{ + struct k_thread *thread = _current; + uintptr_t start, end; + + /* Front guard size - before thread stack area */ + start = (uintptr_t)thread->stack_info.mapped.addr - CONFIG_MMU_PAGE_SIZE; + end = (uintptr_t)thread->stack_info.mapped.addr; + + if ((addr >= start) && (addr < end)) { + return true; + } + + /* Rear guard size - after thread stack area */ + start = (uintptr_t)thread->stack_info.mapped.addr + thread->stack_info.mapped.sz; + end = start + CONFIG_MMU_PAGE_SIZE; + + if ((addr >= start) && (addr < end)) { + return true; + } + + return false; +} +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ + #ifdef CONFIG_EXCEPTION_DEBUG static inline uintptr_t esf_get_code(const z_arch_esf_t *esf) @@ -441,6 +475,14 @@ void z_x86_page_fault_handler(z_arch_esf_t *esf) z_x86_fatal_error(K_ERR_STACK_CHK_FAIL, esf); } #endif +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + void *fault_addr = z_x86_cr2_get(); + + if (z_x86_check_guard_page((uintptr_t)fault_addr)) { + z_x86_fatal_error(K_ERR_STACK_CHK_FAIL, esf); + } +#endif + z_x86_fatal_error(K_ERR_CPU_EXCEPTION, esf); CODE_UNREACHABLE; } diff --git a/arch/x86/core/ia32/thread.c b/arch/x86/core/ia32/thread.c index 7830298f72e..b639bb59fdf 100644 --- a/arch/x86/core/ia32/thread.c +++ b/arch/x86/core/ia32/thread.c @@ -79,7 +79,10 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, void *swap_entry; struct _x86_initial_frame *initial_frame; -#if CONFIG_X86_STACK_PROTECTION +#if defined(CONFIG_X86_STACK_PROTECTION) && !defined(CONFIG_THREAD_STACK_MEM_MAPPED) + /* This unconditionally set the first page of stack as guard page, + * which is only needed if the stack is not memory mapped. + */ z_x86_set_stack_guard(stack); #endif diff --git a/arch/x86/core/intel64/thread.c b/arch/x86/core/intel64/thread.c index e419a92d206..f26f25ab5f1 100644 --- a/arch/x86/core/intel64/thread.c +++ b/arch/x86/core/intel64/thread.c @@ -32,7 +32,10 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, void *switch_entry; struct x86_initial_frame *iframe; -#if CONFIG_X86_STACK_PROTECTION +#if defined(CONFIG_X86_STACK_PROTECTION) && !defined(CONFIG_THREAD_STACK_MEM_MAPPED) + /* This unconditionally set the first page of stack as guard page, + * which is only needed if the stack is not memory mapped. + */ z_x86_set_stack_guard(stack); #endif #ifdef CONFIG_USERSPACE diff --git a/arch/x86/core/userspace.c b/arch/x86/core/userspace.c index 7ad77166b0f..dbe40b2bda0 100644 --- a/arch/x86/core/userspace.c +++ b/arch/x86/core/userspace.c @@ -69,8 +69,13 @@ void z_x86_swap_update_page_tables(struct k_thread *incoming) void *z_x86_userspace_prepare_thread(struct k_thread *thread) { void *initial_entry; + struct z_x86_thread_stack_header *header = +#ifdef CONFIG_THREAD_STACK_MEM_MAPPED + (struct z_x86_thread_stack_header *)thread->stack_info.mapped.addr; +#else (struct z_x86_thread_stack_header *)thread->stack_obj; +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED */ thread->arch.psp = header->privilege_stack + sizeof(header->privilege_stack); diff --git a/include/zephyr/arch/x86/thread_stack.h b/include/zephyr/arch/x86/thread_stack.h index 6602d85784c..f22bf4d6853 100644 --- a/include/zephyr/arch/x86/thread_stack.h +++ b/include/zephyr/arch/x86/thread_stack.h @@ -14,16 +14,20 @@ #define ARCH_STACK_PTR_ALIGN 4UL #endif -#if defined(CONFIG_X86_STACK_PROTECTION) || defined(CONFIG_USERSPACE) +#if defined(CONFIG_X86_STACK_PROTECTION) || defined(CONFIG_USERSPACE) \ + || defined(CONFIG_THREAD_STACK_MEM_MAPPED) #define Z_X86_STACK_BASE_ALIGN CONFIG_MMU_PAGE_SIZE #else #define Z_X86_STACK_BASE_ALIGN ARCH_STACK_PTR_ALIGN #endif -#ifdef CONFIG_USERSPACE +#if defined(CONFIG_USERSPACE) || defined(CONFIG_THREAD_STACK_MEM_MAPPED) /* If user mode enabled, expand any stack size to fill a page since that is * the access control granularity and we don't want other kernel data to * unintentionally fall in the latter part of the page + * + * This is also true when memory mapped stacks are used with since + * access control applies to one page at a time. */ #define Z_X86_STACK_SIZE_ALIGN CONFIG_MMU_PAGE_SIZE #else @@ -34,17 +38,38 @@ /* With both hardware stack protection and userspace enabled, stacks are * arranged as follows: * + * --- Without stack being memory mapped: * High memory addresses * +-----------------------------------------+ * | Thread stack (varies) | * +-----------------------------------------+ * | Privilege elevation stack | - * | (4096 bytes) | + * | (CONFIG_PRIVILEGED_STACK_SIZE) | * +-----------------------------------------+ * | Guard page (4096 bytes) | + * | - 'guard_page' in struct | + * | z_x86_thread_stack_header | + * +-----------------------------------------+ + * Low Memory addresses + * + * --- With stack being memory mapped: + * High memory addresses + * +-----------------------------------------+ + * | Guard page (empty page) | + * +-----------------------------------------+ + * | Thread stack (varies) | + * +-----------------------------------------+ + * | Privilege elevation stack | + * | (CONFIG_PRIVILEGED_STACK_SIZE) | + * +-----------------------------------------+ + * | Guard page (empty page) | * +-----------------------------------------+ * Low Memory addresses * + * Without memory mapped stacks, the guard page is actually allocated + * as part of the stack struct, which takes up physical memory during + * linking. + * * Privilege elevation stacks are fixed-size. All the pages containing the * thread stack are marked as user-accessible. The guard page is marked * read-only to catch stack overflows in supervisor mode. @@ -62,7 +87,7 @@ * privileged mode stack. */ struct z_x86_thread_stack_header { -#ifdef CONFIG_X86_STACK_PROTECTION +#if defined(CONFIG_X86_STACK_PROTECTION) && !defined(CONFIG_THREAD_STACK_MEM_MAPPED) char guard_page[CONFIG_MMU_PAGE_SIZE]; #endif #ifdef CONFIG_USERSPACE From 7d45f3c92a1c9b1dc0e63526670bcf4f16e9fa33 Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Tue, 2 Apr 2024 10:50:57 +0200 Subject: [PATCH 2110/2402] soc: nordic: Provide z_arm_platform_init at link time Nordic SoCs use this hook to execute `SystemInit` as early as possible after ARM core reset. Previously, `z_arm_platform_init` was defined as assembly code, which would simply jump to the other function. However, this extra code can be avoided by using `SystemInit` directly in place of the `z_arm_platform_init` symbol (whenever it's undefined). This is now done with a linker script containing a `PROVIDE` directive. This saves 4 bytes of ROM (0-16 depending on alignment) and also makes it possible to override `z_arm_platform_init` out of tree, if needed. Signed-off-by: Grzegorz Swiderski --- soc/nordic/CMakeLists.txt | 12 ++++------ soc/nordic/common/CMakeLists.txt | 4 ---- soc/nordic/common/soc_nrf_common.S | 34 ---------------------------- soc/nordic/common/vpr/CMakeLists.txt | 2 -- soc/nordic/linker.ld | 19 ++++++++++++++++ 5 files changed, 24 insertions(+), 47 deletions(-) delete mode 100644 soc/nordic/common/soc_nrf_common.S create mode 100644 soc/nordic/linker.ld diff --git a/soc/nordic/CMakeLists.txt b/soc/nordic/CMakeLists.txt index 9e0619772e2..6dae6e97fb2 100644 --- a/soc/nordic/CMakeLists.txt +++ b/soc/nordic/CMakeLists.txt @@ -2,14 +2,12 @@ zephyr_library() -if(CONFIG_ARM) - set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "SoC Linker script") +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "SoC Linker script") - zephyr_library_sources( - validate_base_addresses.c - validate_enabled_instances.c - ) -endif() +zephyr_library_sources( + validate_base_addresses.c + validate_enabled_instances.c + ) if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) if(CONFIG_TIMING_FUNCTIONS) diff --git a/soc/nordic/common/CMakeLists.txt b/soc/nordic/common/CMakeLists.txt index d3cb84fd451..b574cafc0c7 100644 --- a/soc/nordic/common/CMakeLists.txt +++ b/soc/nordic/common/CMakeLists.txt @@ -3,10 +3,6 @@ add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr) -if(CONFIG_ARM AND CONFIG_SOC_FAMILY_NORDIC_NRF) - zephyr_library_sources(soc_nrf_common.S) -endif() - zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) zephyr_include_directories(.) diff --git a/soc/nordic/common/soc_nrf_common.S b/soc/nordic/common/soc_nrf_common.S deleted file mode 100644 index 9067ff5a94c..00000000000 --- a/soc/nordic/common/soc_nrf_common.S +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2021 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief System/hardware module for Nordic Semiconductor nRFxx family processors - */ - -#include -#include - -_ASM_FILE_PROLOGUE - -GTEXT(SystemInit) -GTEXT(z_arm_platform_init) - -SECTION_FUNC(TEXT, z_arm_platform_init) - - /* Implement z_arm_platform_init() directly in ASM, - * and ensure no stack access is performed until - * we jump to SystemInit(). - */ -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) - ldr r0, =SystemInit - bx r0 -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - b SystemInit -#else -#error "Unsupported architecture" -#endif - /* Return occurs via SystemInit */ diff --git a/soc/nordic/common/vpr/CMakeLists.txt b/soc/nordic/common/vpr/CMakeLists.txt index d418954eebc..3849a3fdc94 100644 --- a/soc/nordic/common/vpr/CMakeLists.txt +++ b/soc/nordic/common/vpr/CMakeLists.txt @@ -4,5 +4,3 @@ zephyr_include_directories(.) zephyr_library_sources(soc_idle.c soc_irq.S soc_irq.c vector.S) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/nordic/linker.ld b/soc/nordic/linker.ld new file mode 100644 index 00000000000..c8dbb426592 --- /dev/null +++ b/soc/nordic/linker.ld @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(CONFIG_ARM) +#include + +/* Let SystemInit() be called in place of z_arm_platform_init() by default. */ +PROVIDE(z_arm_platform_init = SystemInit); + +#elif defined(CONFIG_RISCV) +#include + +#else +#error Unsupported architecture + +#endif From 01684df03a9f39199296b61e7b9074fe166591bd Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 19 Mar 2024 14:22:18 +0100 Subject: [PATCH 2111/2402] drivers: flash: stm32 ospi flash driver the correct erase instruction Use the most adapted instruction for the sector erase command It can be 0x20 or ox21 or 0x21DE in octo - DTR mode. The value is given by the SFDP table and filled in the erase_types table the during the SFDP discovery process. Signed-off-by: Francois Ramu --- drivers/flash/flash_stm32_ospi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/flash/flash_stm32_ospi.c b/drivers/flash/flash_stm32_ospi.c index 030dc8bd156..fa9df2937e7 100644 --- a/drivers/flash/flash_stm32_ospi.c +++ b/drivers/flash/flash_stm32_ospi.c @@ -1108,11 +1108,11 @@ static int flash_stm32_ospi_erase(const struct device *dev, off_t addr, ? SPI_NOR_CMD_SE_4B : SPI_NOR_CMD_SE; } - /* Avoid using wrong erase type, - * if zero entries are found in erase_types - */ - bet = NULL; } + /* Avoid using wrong erase type, + * if zero entries are found in erase_types + */ + bet = NULL; } LOG_DBG("Sector/Block Erase addr 0x%x, asize 0x%x amode 0x%x instr 0x%x", cmd_erase.Address, cmd_erase.AddressSize, From 325ae4d32a85947c5ee6cef570e8df8c2fa313b0 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Tue, 19 Mar 2024 15:42:43 +0100 Subject: [PATCH 2112/2402] samples: drivers: spi flash testcase check the erased data After erasing the sector, compare dat read with expected 0xFF pattern to decide if erasing is successful instead of relying on the returned code of the flash_erase function Signed-off-by: Francois Ramu --- samples/drivers/spi_flash/src/main.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/samples/drivers/spi_flash/src/main.c b/samples/drivers/spi_flash/src/main.c index 293a38e6b8b..2faadd309c6 100644 --- a/samples/drivers/spi_flash/src/main.c +++ b/samples/drivers/spi_flash/src/main.c @@ -30,6 +30,8 @@ #define SPI_FLASH_MULTI_SECTOR_TEST #endif +const uint8_t erased[] = { 0xff, 0xff, 0xff, 0xff }; + void single_sector_test(const struct device *flash_dev) { const uint8_t expected[] = { 0x55, 0xaa, 0x66, 0x99 }; @@ -53,9 +55,20 @@ void single_sector_test(const struct device *flash_dev) if (rc != 0) { printf("Flash erase failed! %d\n", rc); } else { + /* Check erased pattern */ + memset(buf, 0, len); + rc = flash_read(flash_dev, SPI_FLASH_TEST_REGION_OFFSET, buf, len); + if (rc != 0) { + printf("Flash read failed! %d\n", rc); + return; + } + if (memcmp(erased, buf, len) != 0) { + printf("Flash erase failed at offset 0x%x got 0x%x\n", + SPI_FLASH_TEST_REGION_OFFSET, *(uint32_t *)buf); + return; + } printf("Flash erase succeeded!\n"); } - printf("\nTest 2: Flash write\n"); printf("Attempting to write %zu bytes\n", len); @@ -98,7 +111,7 @@ void multi_sector_test(const struct device *flash_dev) uint8_t buf[sizeof(expected)]; int rc; - printf("\nPerform test on multiple consequtive sectors"); + printf("\nPerform test on multiple consecutive sectors"); /* Write protection needs to be disabled before each write or * erase, since the flash component turns on write protection @@ -125,9 +138,9 @@ void multi_sector_test(const struct device *flash_dev) printf("Flash read failed! %d\n", rc); return; } - if (buf[0] != 0xff) { + if (memcmp(erased, buf, len) != 0) { printf("Flash erase failed at offset 0x%x got 0x%x\n", - offs, buf[0]); + offs, *(uint32_t *)buf); return; } offs += SPI_FLASH_SECTOR_SIZE; From f46debf21e3f82a92f117c8478ae144342839821 Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Mon, 8 Apr 2024 13:12:24 +0200 Subject: [PATCH 2113/2402] MAINTAINERS: update SiLabs maintainers Removing ourselves from maintainers list as we currently don't have bandwith to maintain this platform family. Signed-off-by: Filip Kokosinski --- MAINTAINERS.yml | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 1fd761b7d5a..5a4f332e40e 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3200,11 +3200,7 @@ Raspberry Pi Pico Platforms: - "platform: Raspberry Pi Pico" SiLabs Platforms: - status: maintained - maintainers: - - fkokosinski - collaborators: - - tgorochowik + status: odd fixes files: - soc/silabs/ - boards/silabs/ @@ -4252,9 +4248,7 @@ West: - "platform: Raspberry Pi Pico" "West project: hal_silabs": - status: maintained - maintainers: - - fkokosinski + status: odd fixes collaborators: - sateeshkotapati - yonsch From e70273a3cdb53fb22e20ed5011cd4a8dcaddd253 Mon Sep 17 00:00:00 2001 From: "Najumon B.A" Date: Fri, 5 Apr 2024 09:44:35 +0530 Subject: [PATCH 2114/2402] MAINTAINERS: update for x86 arch and platform Update collaborators list for x86 arch and platform Signed-off-by: Najumon B.A --- MAINTAINERS.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 5a4f332e40e..91cb3cd9ff7 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3217,6 +3217,7 @@ Intel Platforms (X86): collaborators: - tbursztyka - laurenmurphyx64 + - najumon1980 files: - boards/intel/adl/ - boards/intel/ehl/ @@ -4667,6 +4668,7 @@ x86 arch: - dcpleung - ceolin - laurenmurphyx64 + - najumon1980 files: - arch/x86/ - include/zephyr/arch/x86/ From 41d70de91e026b11ea8f89be59b7865e56dc3e75 Mon Sep 17 00:00:00 2001 From: Seppo Takalo Date: Wed, 10 Apr 2024 10:08:19 +0300 Subject: [PATCH 2115/2402] drivers: eth: stellaris: Fix build error Apparently there was a typo in the last commit. Looks like it was refactored without trying to build. Signed-off-by: Seppo Takalo --- drivers/ethernet/eth_stellaris.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ethernet/eth_stellaris.c b/drivers/ethernet/eth_stellaris.c index 30de5d47ad2..dc7503e67af 100644 --- a/drivers/ethernet/eth_stellaris.c +++ b/drivers/ethernet/eth_stellaris.c @@ -249,7 +249,7 @@ static void eth_stellaris_isr(const struct device *dev) * to get how many packets are in the Ethernet. */ num_packets = sys_read32(REG_MACNP); - for (int i = 0; i < np; i++) { + for (int i = 0; i < num_packets; i++) { if (eth_stellaris_rx(dev) != 0) { break; } From 03057f33d4a3066a469006fc5cef6a5828f42f47 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Mon, 8 Apr 2024 17:26:47 +0300 Subject: [PATCH 2116/2402] soc: intel_adsp: ace: fix power_down documentation Fix the inline documentation to match implementation. As IPFL is used, the correct matching function is xthal_icache_region_lock(). Signed-off-by: Kai Vehmanen --- soc/intel/intel_adsp/ace/power_down.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/intel/intel_adsp/ace/power_down.S b/soc/intel/intel_adsp/ace/power_down.S index 488520979d2..1b9f7792ac8 100644 --- a/soc/intel/intel_adsp/ace/power_down.S +++ b/soc/intel/intel_adsp/ace/power_down.S @@ -47,7 +47,7 @@ power_down: /** * effectively executes: * xthal_dcache_region_lock(&literals, 128); - * xthal_dcache_region_lock(&powerdown, 256); + * xthal_icache_region_lock(&powerdown, 256); * xthal_dcache_region_lock(&pu32_hpsram_mask, 64); */ movi pfl_reg, power_down_literals From 7fee1bdd39757e2619bc6225e3f5fb65e624d271 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Mon, 8 Apr 2024 17:29:25 +0300 Subject: [PATCH 2117/2402] soc: intel_adsp: cavs: fix power_down documentation Fix the inline documentation to match implementation. As IPFL is used, the correct matching function is xthal_icache_region_lock(). Signed-off-by: Kai Vehmanen --- soc/intel/intel_adsp/cavs/power_down_cavs.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/intel/intel_adsp/cavs/power_down_cavs.S b/soc/intel/intel_adsp/cavs/power_down_cavs.S index 448b105ff61..4698b1f3a30 100644 --- a/soc/intel/intel_adsp/cavs/power_down_cavs.S +++ b/soc/intel/intel_adsp/cavs/power_down_cavs.S @@ -48,7 +48,7 @@ power_down_cavs: /** * effectively executes: * xthal_dcache_region_lock(&literals, 128); - * xthal_dcache_region_lock(&powerdown, 256); + * xthal_icache_region_lock(&powerdown, 256); * xthal_dcache_region_lock(&pu32_hpsram_mask, 64); */ movi pfl_reg, power_down_literals From 38738265b9422acd699512dfaa7dbb998cdb4f6d Mon Sep 17 00:00:00 2001 From: Armando Visconti Date: Mon, 8 Apr 2024 14:23:52 +0200 Subject: [PATCH 2118/2402] drivers/sensor: use sensor APIs to convert to units Make use of sensor_ug_to_ms2() and sensor_10udegrees_to_rad() APIs to convert from raw values into proper units (i.e. m/s^2 for accel and rad/s for gyro). Signed-off-by: Armando Visconti --- drivers/sensor/st/iis2iclx/iis2iclx.c | 8 +++----- drivers/sensor/st/iis2iclx/iis2iclx.h | 4 ---- drivers/sensor/st/ism330dhcx/ism330dhcx.c | 14 ++++++-------- drivers/sensor/st/ism330dhcx/ism330dhcx.h | 4 ---- drivers/sensor/st/lsm6dso/lsm6dso.c | 15 ++++++--------- drivers/sensor/st/lsm6dso/lsm6dso.h | 4 ---- drivers/sensor/st/lsm6dso16is/lsm6dso16is.c | 14 ++++++-------- drivers/sensor/st/lsm6dso16is/lsm6dso16is.h | 4 ---- drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.c | 15 ++++++--------- drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h | 4 ---- 10 files changed, 27 insertions(+), 59 deletions(-) diff --git a/drivers/sensor/st/iis2iclx/iis2iclx.c b/drivers/sensor/st/iis2iclx/iis2iclx.c index e45203da003..3cc34cd4a64 100644 --- a/drivers/sensor/st/iis2iclx/iis2iclx.c +++ b/drivers/sensor/st/iis2iclx/iis2iclx.c @@ -281,10 +281,8 @@ static inline void iis2iclx_accel_convert(struct sensor_value *val, int raw_val, /* Sensitivity is exposed in ug/LSB */ /* Convert to m/s^2 */ - dval = (int64_t)(raw_val) * sensitivity * SENSOR_G_DOUBLE; - val->val1 = (int32_t)(dval / 1000000); - val->val2 = (int32_t)(dval % 1000000); - + dval = (int64_t)(raw_val) * sensitivity; + sensor_ug_to_ms2(dval, val); } static inline int iis2iclx_accel_get_channel(enum sensor_channel chan, @@ -336,7 +334,7 @@ static inline void iis2iclx_magn_convert(struct sensor_value *val, int raw_val, { double dval; - /* Sensitivity is exposed in mgauss/LSB */ + /* Sensitivity is exposed in ugauss/LSB */ dval = (double)(raw_val * sensitivity); val->val1 = (int32_t)dval / 1000000; val->val2 = (int32_t)dval % 1000000; diff --git a/drivers/sensor/st/iis2iclx/iis2iclx.h b/drivers/sensor/st/iis2iclx/iis2iclx.h index 6605be5851c..c9d39abf0ff 100644 --- a/drivers/sensor/st/iis2iclx/iis2iclx.h +++ b/drivers/sensor/st/iis2iclx/iis2iclx.h @@ -32,10 +32,6 @@ /* Accel sensor sensitivity grain is 15 ug/LSB */ #define GAIN_UNIT_XL (15LL) -#define SENSOR_PI_DOUBLE (SENSOR_PI / 1000000.0) -#define SENSOR_DEG2RAD_DOUBLE (SENSOR_PI_DOUBLE / 180) -#define SENSOR_G_DOUBLE (SENSOR_G / 1000000.0) - struct iis2iclx_config { stmdev_ctx_t ctx; union { diff --git a/drivers/sensor/st/ism330dhcx/ism330dhcx.c b/drivers/sensor/st/ism330dhcx/ism330dhcx.c index 97d0aaa5f44..95b819b97be 100644 --- a/drivers/sensor/st/ism330dhcx/ism330dhcx.c +++ b/drivers/sensor/st/ism330dhcx/ism330dhcx.c @@ -382,9 +382,8 @@ static inline void ism330dhcx_accel_convert(struct sensor_value *val, int raw_va /* Sensitivity is exposed in ug/LSB */ /* Convert to m/s^2 */ - dval = (int64_t)(raw_val) * sensitivity * SENSOR_G_DOUBLE; - val->val1 = (int32_t)(dval / 1000000); - val->val2 = (int32_t)(dval % 1000000); + dval = (int64_t)(raw_val) * sensitivity; + sensor_ug_to_ms2(dval, val); } @@ -430,10 +429,9 @@ static inline void ism330dhcx_gyro_convert(struct sensor_value *val, int raw_val int64_t dval; /* Sensitivity is exposed in udps/LSB */ - /* Convert to rad/s */ - dval = (int64_t)(raw_val) * sensitivity * SENSOR_DEG2RAD_DOUBLE; - val->val1 = (int32_t)(dval / 1000000); - val->val2 = (int32_t)(dval % 1000000); + /* So, calculate value in 10 udps unit and then to rad/s */ + dval = (int64_t)(raw_val) * sensitivity / 10; + sensor_10udegrees_to_rad(dval, val); } static inline int ism330dhcx_gyro_get_channel(const struct device *dev, enum sensor_channel chan, @@ -490,7 +488,7 @@ static inline void ism330dhcx_magn_convert(struct sensor_value *val, int raw_val { double dval; - /* Sensitivity is exposed in mgauss/LSB */ + /* Sensitivity is exposed in ugauss/LSB */ dval = (double)(raw_val * sensitivity); val->val1 = (int32_t)dval / 1000000; val->val2 = (int32_t)dval % 1000000; diff --git a/drivers/sensor/st/ism330dhcx/ism330dhcx.h b/drivers/sensor/st/ism330dhcx/ism330dhcx.h index 6e42b9d15f3..4dd03304173 100644 --- a/drivers/sensor/st/ism330dhcx/ism330dhcx.h +++ b/drivers/sensor/st/ism330dhcx/ism330dhcx.h @@ -30,10 +30,6 @@ /* Gyro sensor sensitivity grain is 4.375 udps/LSB */ #define GAIN_UNIT_G (4375LL) -#define SENSOR_PI_DOUBLE (SENSOR_PI / 1000000.0) -#define SENSOR_DEG2RAD_DOUBLE (SENSOR_PI_DOUBLE / 180) -#define SENSOR_G_DOUBLE (SENSOR_G / 1000000.0) - struct ism330dhcx_config { int (*bus_init)(const struct device *dev); uint8_t accel_odr; diff --git a/drivers/sensor/st/lsm6dso/lsm6dso.c b/drivers/sensor/st/lsm6dso/lsm6dso.c index fe6b65edbec..974c0307ba8 100644 --- a/drivers/sensor/st/lsm6dso/lsm6dso.c +++ b/drivers/sensor/st/lsm6dso/lsm6dso.c @@ -402,10 +402,8 @@ static inline void lsm6dso_accel_convert(struct sensor_value *val, int raw_val, /* Sensitivity is exposed in ug/LSB */ /* Convert to m/s^2 */ - dval = (int64_t)(raw_val) * sensitivity * SENSOR_G_DOUBLE; - val->val1 = (int32_t)(dval / 1000000); - val->val2 = (int32_t)(dval % 1000000); - + dval = (int64_t)(raw_val) * sensitivity; + sensor_ug_to_ms2(dval, val); } static inline int lsm6dso_accel_get_channel(enum sensor_channel chan, @@ -450,10 +448,9 @@ static inline void lsm6dso_gyro_convert(struct sensor_value *val, int raw_val, int64_t dval; /* Sensitivity is exposed in udps/LSB */ - /* Convert to rad/s */ - dval = (int64_t)(raw_val) * sensitivity * SENSOR_DEG2RAD_DOUBLE; - val->val1 = (int32_t)(dval / 1000000); - val->val2 = (int32_t)(dval % 1000000); + /* So, calculate value in 10 udps unit and then to rad/s */ + dval = (int64_t)(raw_val) * sensitivity / 10; + sensor_10udegrees_to_rad(dval, val); } static inline int lsm6dso_gyro_get_channel(enum sensor_channel chan, @@ -508,7 +505,7 @@ static inline void lsm6dso_magn_convert(struct sensor_value *val, int raw_val, { double dval; - /* Sensitivity is exposed in mgauss/LSB */ + /* Sensitivity is exposed in ugauss/LSB */ dval = (double)(raw_val * sensitivity); val->val1 = (int32_t)dval / 1000000; val->val2 = (int32_t)dval % 1000000; diff --git a/drivers/sensor/st/lsm6dso/lsm6dso.h b/drivers/sensor/st/lsm6dso/lsm6dso.h index 7b01901263d..c7f7279d3ba 100644 --- a/drivers/sensor/st/lsm6dso/lsm6dso.h +++ b/drivers/sensor/st/lsm6dso/lsm6dso.h @@ -36,10 +36,6 @@ /* Gyro sensor sensitivity grain is 4.375 udps/LSB */ #define GAIN_UNIT_G (4375LL) -#define SENSOR_PI_DOUBLE (SENSOR_PI / 1000000.0) -#define SENSOR_DEG2RAD_DOUBLE (SENSOR_PI_DOUBLE / 180) -#define SENSOR_G_DOUBLE (SENSOR_G / 1000000.0) - struct lsm6dso_config { stmdev_ctx_t ctx; union { diff --git a/drivers/sensor/st/lsm6dso16is/lsm6dso16is.c b/drivers/sensor/st/lsm6dso16is/lsm6dso16is.c index cf4862df2e0..02d1fdf8be6 100644 --- a/drivers/sensor/st/lsm6dso16is/lsm6dso16is.c +++ b/drivers/sensor/st/lsm6dso16is/lsm6dso16is.c @@ -426,9 +426,8 @@ static inline void lsm6dso16is_accel_convert(struct sensor_value *val, int raw_v /* Sensitivity is exposed in ug/LSB */ /* Convert to m/s^2 */ - dval = (int64_t)(raw_val) * sensitivity * SENSOR_G_DOUBLE; - val->val1 = (int32_t)(dval / 1000000); - val->val2 = (int32_t)(dval % 1000000); + dval = (int64_t)(raw_val) * sensitivity; + sensor_ug_to_ms2(dval, val); } @@ -474,10 +473,9 @@ static inline void lsm6dso16is_gyro_convert(struct sensor_value *val, int raw_va int64_t dval; /* Sensitivity is exposed in udps/LSB */ - /* Convert to rad/s */ - dval = (int64_t)(raw_val) * sensitivity * SENSOR_DEG2RAD_DOUBLE; - val->val1 = (int32_t)(dval / 1000000); - val->val2 = (int32_t)(dval % 1000000); + /* So, calculate value in 10 udps unit and then to rad/s */ + dval = (int64_t)(raw_val) * sensitivity / 10; + sensor_10udegrees_to_rad(dval, val); } static inline int lsm6dso16is_gyro_get_channel(enum sensor_channel chan, @@ -538,7 +536,7 @@ static inline void lsm6dso16is_magn_convert(struct sensor_value *val, int raw_va { double dval; - /* Sensitivity is exposed in mgauss/LSB */ + /* Sensitivity is exposed in ugauss/LSB */ dval = (double)(raw_val * sensitivity); val->val1 = (int32_t)dval / 1000000; val->val2 = (int32_t)dval % 1000000; diff --git a/drivers/sensor/st/lsm6dso16is/lsm6dso16is.h b/drivers/sensor/st/lsm6dso16is/lsm6dso16is.h index ce2448e2c5a..62f13586cd6 100644 --- a/drivers/sensor/st/lsm6dso16is/lsm6dso16is.h +++ b/drivers/sensor/st/lsm6dso16is/lsm6dso16is.h @@ -35,10 +35,6 @@ /* Gyro sensor sensitivity grain is 4.375 udps/LSB */ #define GAIN_UNIT_G (4375LL) -#define SENSOR_PI_DOUBLE (SENSOR_PI / 1000000.0) -#define SENSOR_DEG2RAD_DOUBLE (SENSOR_PI_DOUBLE / 180) -#define SENSOR_G_DOUBLE (SENSOR_G / 1000000.0) - struct lsm6dso16is_config { stmdev_ctx_t ctx; union { diff --git a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.c b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.c index d4f9a2c850d..887302adf4d 100644 --- a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.c +++ b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.c @@ -473,10 +473,8 @@ static inline void lsm6dsv16x_accel_convert(struct sensor_value *val, int raw_va /* Sensitivity is exposed in ug/LSB */ /* Convert to m/s^2 */ - dval = (int64_t)(raw_val) * sensitivity * SENSOR_G_DOUBLE; - val->val1 = (int32_t)(dval / 1000000); - val->val2 = (int32_t)(dval % 1000000); - + dval = (int64_t)(raw_val) * sensitivity; + sensor_ug_to_ms2(dval, val); } static inline int lsm6dsv16x_accel_get_channel(enum sensor_channel chan, @@ -521,10 +519,9 @@ static inline void lsm6dsv16x_gyro_convert(struct sensor_value *val, int raw_val int64_t dval; /* Sensitivity is exposed in udps/LSB */ - /* Convert to rad/s */ - dval = (int64_t)(raw_val) * sensitivity * SENSOR_DEG2RAD_DOUBLE; - val->val1 = (int32_t)(dval / 1000000); - val->val2 = (int32_t)(dval % 1000000); + /* So, calculate value in 10 udps unit and then to rad/s */ + dval = (int64_t)(raw_val) * sensitivity / 10; + sensor_10udegrees_to_rad(dval, val); } static inline int lsm6dsv16x_gyro_get_channel(enum sensor_channel chan, @@ -585,7 +582,7 @@ static inline void lsm6dsv16x_magn_convert(struct sensor_value *val, int raw_val { double dval; - /* Sensitivity is exposed in mgauss/LSB */ + /* Sensitivity is exposed in ugauss/LSB */ dval = (double)(raw_val * sensitivity); val->val1 = (int32_t)dval / 1000000; val->val2 = (int32_t)dval % 1000000; diff --git a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h index 2b3819b306a..76132f743cc 100644 --- a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h +++ b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h @@ -35,10 +35,6 @@ /* Gyro sensor sensitivity grain is 4.375 udps/LSB */ #define GAIN_UNIT_G (4375LL) -#define SENSOR_PI_DOUBLE (SENSOR_PI / 1000000.0) -#define SENSOR_DEG2RAD_DOUBLE (SENSOR_PI_DOUBLE / 180) -#define SENSOR_G_DOUBLE (SENSOR_G / 1000000.0) - struct lsm6dsv16x_config { stmdev_ctx_t ctx; union { From 884e661cc92a699fc5bad88950c1afcea7c1217e Mon Sep 17 00:00:00 2001 From: Piotr Kosycarz Date: Mon, 8 Apr 2024 10:30:48 +0200 Subject: [PATCH 2119/2402] samples: sensor: isl29035: Align sample definition Add fixutre as external hw is required. Add regex. Signed-off-by: Piotr Kosycarz --- samples/sensor/isl29035/sample.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/samples/sensor/isl29035/sample.yaml b/samples/sensor/isl29035/sample.yaml index 086e4eec8cf..66652b64d27 100644 --- a/samples/sensor/isl29035/sample.yaml +++ b/samples/sensor/isl29035/sample.yaml @@ -7,3 +7,9 @@ tests: platform_allow: nrf52dk/nrf52832 integration_platforms: - nrf52dk/nrf52832 + harness: console + harness_config: + type: one_line + regex: + - "Ambient light sense" + fixture: fixture_isl29035 From ad33d007eaeef27869475f56f958c2442049eaa0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20G=C5=82=C4=85b?= Date: Thu, 4 Apr 2024 14:37:53 +0200 Subject: [PATCH 2120/2402] samples: sensor: qdec: Add nRF54L15 to platform allow MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nRF54L15 to platform_allow and integration_platforms in the sample.yaml. Overlay file for that target already exists in the boards directory. Signed-off-by: Sebastian Głąb --- samples/sensor/qdec/sample.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/samples/sensor/qdec/sample.yaml b/samples/sensor/qdec/sample.yaml index cbd90ba6f3e..962fee55b6e 100644 --- a/samples/sensor/qdec/sample.yaml +++ b/samples/sensor/qdec/sample.yaml @@ -20,8 +20,10 @@ tests: platform_allow: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp + - nrf54l15pdk/nrf54l15/cpuapp harness_config: fixture: gpio_loopback From 0fdfcad6759a5bab83c4708d86c7274fb749f300 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20G=C5=82=C4=85b?= Date: Thu, 4 Apr 2024 16:17:39 +0200 Subject: [PATCH 2121/2402] samples: sensor: qdec: Move console regex to each test MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It seems that harness_config defined in the 'common' section is discarded when test adds fixture to it's harness_config. Signed-off-by: Sebastian Głąb --- samples/sensor/qdec/sample.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/samples/sensor/qdec/sample.yaml b/samples/sensor/qdec/sample.yaml index 962fee55b6e..8982dfccd33 100644 --- a/samples/sensor/qdec/sample.yaml +++ b/samples/sensor/qdec/sample.yaml @@ -5,17 +5,18 @@ common: tags: sensors timeout: 5 harness: console - harness_config: - type: multi_line - ordered: true - regex: - - "Quadrature decoder sensor test" - - "Position = (.*) degrees" + tests: sample.sensor.qdec_sensor: platform_allow: nucleo_f401re harness_config: fixture: fixture_mech_encoder + type: multi_line + ordered: true + regex: + - "Quadrature decoder sensor test" + - "Position = (.*) degrees" + sample.sensor.nrf_qdec_sensor: platform_allow: - nrf52840dk/nrf52840 @@ -27,3 +28,8 @@ tests: - nrf54l15pdk/nrf54l15/cpuapp harness_config: fixture: gpio_loopback + type: multi_line + ordered: true + regex: + - "Quadrature decoder sensor test" + - "Position = (.*) degrees" From 63772ad2d86bb1f7e64ce0b90406b9f1b01dc71a Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Wed, 3 Apr 2024 18:15:06 +0900 Subject: [PATCH 2122/2402] boards: arduino: uno_r4_minima: Rename directory to `uno_r4` Rename directory to `uno_r4` for preparing to add Arduino UNO R4 Wifi. Signed-off-by: TOKITA Hiroshi --- MAINTAINERS.yml | 2 +- .../{uno_r4_minima => uno_r4}/Kconfig.arduino_uno_r4_minima | 0 .../{uno_r4_minima => uno_r4}/arduino_uno_r4_common.dtsi | 0 .../arduino_uno_r4_minima-pinctrl.dtsi | 0 .../arduino/{uno_r4_minima => uno_r4}/arduino_uno_r4_minima.dts | 0 .../{uno_r4_minima => uno_r4}/arduino_uno_r4_minima.yaml | 0 .../{uno_r4_minima => uno_r4}/arduino_uno_r4_minima_defconfig | 0 boards/arduino/{uno_r4_minima => uno_r4}/board.cmake | 0 boards/arduino/{uno_r4_minima => uno_r4}/board.yml | 0 boards/arduino/{uno_r4_minima => uno_r4}/doc/index.rst | 0 10 files changed, 1 insertion(+), 1 deletion(-) rename boards/arduino/{uno_r4_minima => uno_r4}/Kconfig.arduino_uno_r4_minima (100%) rename boards/arduino/{uno_r4_minima => uno_r4}/arduino_uno_r4_common.dtsi (100%) rename boards/arduino/{uno_r4_minima => uno_r4}/arduino_uno_r4_minima-pinctrl.dtsi (100%) rename boards/arduino/{uno_r4_minima => uno_r4}/arduino_uno_r4_minima.dts (100%) rename boards/arduino/{uno_r4_minima => uno_r4}/arduino_uno_r4_minima.yaml (100%) rename boards/arduino/{uno_r4_minima => uno_r4}/arduino_uno_r4_minima_defconfig (100%) rename boards/arduino/{uno_r4_minima => uno_r4}/board.cmake (100%) rename boards/arduino/{uno_r4_minima => uno_r4}/board.yml (100%) rename boards/arduino/{uno_r4_minima => uno_r4}/doc/index.rst (100%) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 91cb3cd9ff7..90097c74317 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3485,7 +3485,7 @@ Renesas RA Platforms: maintainers: - soburi files: - - boards/arduino/uno_r4_minima/ + - boards/arduino/uno_r4/ - drivers/*/*renesas_ra* - drivers/pinctrl/renesas/ra/ - dts/arm/renesas/ra/ diff --git a/boards/arduino/uno_r4_minima/Kconfig.arduino_uno_r4_minima b/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_minima similarity index 100% rename from boards/arduino/uno_r4_minima/Kconfig.arduino_uno_r4_minima rename to boards/arduino/uno_r4/Kconfig.arduino_uno_r4_minima diff --git a/boards/arduino/uno_r4_minima/arduino_uno_r4_common.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi similarity index 100% rename from boards/arduino/uno_r4_minima/arduino_uno_r4_common.dtsi rename to boards/arduino/uno_r4/arduino_uno_r4_common.dtsi diff --git a/boards/arduino/uno_r4_minima/arduino_uno_r4_minima-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi similarity index 100% rename from boards/arduino/uno_r4_minima/arduino_uno_r4_minima-pinctrl.dtsi rename to boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi diff --git a/boards/arduino/uno_r4_minima/arduino_uno_r4_minima.dts b/boards/arduino/uno_r4/arduino_uno_r4_minima.dts similarity index 100% rename from boards/arduino/uno_r4_minima/arduino_uno_r4_minima.dts rename to boards/arduino/uno_r4/arduino_uno_r4_minima.dts diff --git a/boards/arduino/uno_r4_minima/arduino_uno_r4_minima.yaml b/boards/arduino/uno_r4/arduino_uno_r4_minima.yaml similarity index 100% rename from boards/arduino/uno_r4_minima/arduino_uno_r4_minima.yaml rename to boards/arduino/uno_r4/arduino_uno_r4_minima.yaml diff --git a/boards/arduino/uno_r4_minima/arduino_uno_r4_minima_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig similarity index 100% rename from boards/arduino/uno_r4_minima/arduino_uno_r4_minima_defconfig rename to boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig diff --git a/boards/arduino/uno_r4_minima/board.cmake b/boards/arduino/uno_r4/board.cmake similarity index 100% rename from boards/arduino/uno_r4_minima/board.cmake rename to boards/arduino/uno_r4/board.cmake diff --git a/boards/arduino/uno_r4_minima/board.yml b/boards/arduino/uno_r4/board.yml similarity index 100% rename from boards/arduino/uno_r4_minima/board.yml rename to boards/arduino/uno_r4/board.yml diff --git a/boards/arduino/uno_r4_minima/doc/index.rst b/boards/arduino/uno_r4/doc/index.rst similarity index 100% rename from boards/arduino/uno_r4_minima/doc/index.rst rename to boards/arduino/uno_r4/doc/index.rst From 1b2560167f586159fe4751f5b00ae9f7be8e8c83 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Wed, 3 Apr 2024 18:18:19 +0900 Subject: [PATCH 2123/2402] boards: arduino: uno_r4: Add Arduino UNO R4 WiFi Add configuration for Arduino UNO R4 WiFi Signed-off-by: TOKITA Hiroshi --- .../uno_r4/Kconfig.arduino_uno_r4_wifi | 5 ++ .../arduino/uno_r4/arduino_uno_r4_common.dtsi | 62 ++++++++++++++++++ .../arduino/uno_r4/arduino_uno_r4_minima.dts | 64 ------------------- .../uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi | 15 +++++ boards/arduino/uno_r4/arduino_uno_r4_wifi.dts | 24 +++++++ .../arduino/uno_r4/arduino_uno_r4_wifi.yaml | 12 ++++ .../uno_r4/arduino_uno_r4_wifi_defconfig | 23 +++++++ boards/arduino/uno_r4/board.yml | 14 ++-- 8 files changed, 150 insertions(+), 69 deletions(-) create mode 100644 boards/arduino/uno_r4/Kconfig.arduino_uno_r4_wifi create mode 100644 boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi create mode 100644 boards/arduino/uno_r4/arduino_uno_r4_wifi.dts create mode 100644 boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml create mode 100644 boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig diff --git a/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_wifi b/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_wifi new file mode 100644 index 00000000000..840ead804a4 --- /dev/null +++ b/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_wifi @@ -0,0 +1,5 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_UNO_R4_WIFI + select SOC_R7FA4M1AB3CFM diff --git a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi index 472e1092f5f..13ec82502c2 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi +++ b/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi @@ -6,8 +6,70 @@ /dts-v1/; #include +#include / { model = "Arduino Uno R4 Board"; compatible = "renesas,r7fa4m1aB3cfm"; + + chosen { + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &code_partition; + }; +}; + +&sci2 { + status = "okay"; + pinctrl-0 = <&sci2_default>; + pinctrl-names = "default"; + uart2: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&ioport1 { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "bootloader"; + reg = <0x00000000 0x4000>; + read-only; + }; + + code_partition: partition@4000 { + label = "code"; + reg = <0x4000 0x3C000>; + read-only; + }; + }; +}; + +&fcu { + status = "okay"; +}; + +&hoco { + status = "okay"; + clock-frequency = <48000000>; +}; + +&cgc { + clock-source = <&hoco>; + iclk-div = <1>; + pclka-div = <1>; + pclkb-div = <2>; + pclkc-div = <1>; + pclkd-div = <1>; + fclk-div = <2>; }; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima.dts b/boards/arduino/uno_r4/arduino_uno_r4_minima.dts index 18b1aea120c..6984b6c5354 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_minima.dts +++ b/boards/arduino/uno_r4/arduino_uno_r4_minima.dts @@ -5,23 +5,12 @@ */ /dts-v1/; - -#include - #include "arduino_uno_r4_common.dtsi" #include "arduino_uno_r4_minima-pinctrl.dtsi" / { model = "Arduino Uno R4 Minima"; - chosen { - zephyr,console = &uart2; - zephyr,shell-uart = &uart2; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &code_partition; - }; - leds { compatible = "gpio-leds"; led: led { @@ -33,56 +22,3 @@ led0 = &led; }; }; - -&sci2 { - status = "okay"; - pinctrl-0 = <&sci2_default>; - pinctrl-names = "default"; - uart2: uart { - current-speed = <115200>; - status = "okay"; - }; -}; - -&ioport1 { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "bootloader"; - reg = <0x00000000 0x4000>; - read-only; - }; - - code_partition: partition@4000 { - label = "code"; - reg = <0x4000 0x3C000>; - read-only; - }; - }; -}; - -&fcu { - status = "okay"; -}; - -&hoco { - status = "okay"; - clock-frequency = <48000000>; -}; - -&cgc { - clock-source = <&hoco>; - iclk-div = <1>; - pclka-div = <1>; - pclkb-div = <2>; - pclkc-div = <1>; - pclkd-div = <1>; - fclk-div = <2>; -}; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi new file mode 100644 index 00000000000..093d4e4cdf9 --- /dev/null +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + sci2_default: sci2_default { + group1 { + pinmux = , ; + }; + }; +}; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi.dts b/boards/arduino/uno_r4/arduino_uno_r4_wifi.dts new file mode 100644 index 00000000000..2cba24cdf16 --- /dev/null +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi.dts @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "arduino_uno_r4_common.dtsi" +#include "arduino_uno_r4_wifi-pinctrl.dtsi" + +/ { + model = "Arduino Uno R4 WiFi"; + + leds { + compatible = "gpio-leds"; + led: led { + gpios = <&ioport1 2 GPIO_ACTIVE_HIGH>; + }; + }; + + aliases { + led0 = &led; + }; +}; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml b/boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml new file mode 100644 index 00000000000..bfe5bc8cdcd --- /dev/null +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml @@ -0,0 +1,12 @@ +identifier: arduino_uno_r4_wifi +name: Arduino Uno R4 WiFi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32 +supported: + - gpio + - uart diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig new file mode 100644 index 00000000000..76f5a5fb854 --- /dev/null +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 + +CONFIG_BUILD_OUTPUT_HEX=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_PINCTRL=y + +CONFIG_CLOCK_CONTROL=y + +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arduino/uno_r4/board.yml b/boards/arduino/uno_r4/board.yml index f4dc7b8467b..8286850b76c 100644 --- a/boards/arduino/uno_r4/board.yml +++ b/boards/arduino/uno_r4/board.yml @@ -1,5 +1,9 @@ -board: - name: arduino_uno_r4_minima - vendor: arduino - socs: - - name: r7fa4m1ab3cfm +boards: + - name: arduino_uno_r4_minima + vendor: arduino + socs: + - name: r7fa4m1ab3cfm + - name: arduino_uno_r4_wifi + vendor: arduino + socs: + - name: r7fa4m1ab3cfm From 747440c46e5670da6254ecfcc0c117d3b52c4f78 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Wed, 3 Apr 2024 19:58:45 +0900 Subject: [PATCH 2124/2402] boards: arduino: uno_r4: Update document about Arduino UNO R4 WiFi Update documents about adding Arduino UNO R4 WiFi. Adding a description that a debug adapter is required when flashing and debugging. Signed-off-by: TOKITA Hiroshi --- boards/arduino/uno_r4/doc/index.rst | 63 ++++++++++++++++++++++++++--- 1 file changed, 58 insertions(+), 5 deletions(-) diff --git a/boards/arduino/uno_r4/doc/index.rst b/boards/arduino/uno_r4/doc/index.rst index e94c4c78902..1b2b28385ba 100644 --- a/boards/arduino/uno_r4/doc/index.rst +++ b/boards/arduino/uno_r4/doc/index.rst @@ -1,21 +1,58 @@ .. _arduino_uno_r4: -Arduino UNO R4 Minima -##################### +Arduino UNO R4 +############## Overview ******** -The Arduino UNO R4 Minima is a development board featuring the Renesas RA4M1 SoC +The Arduino UNO R4 Minima/WiFi is a development board featuring the Renesas RA4M1 SoC in the Arduino form factor and is compatible with traditional Arduino. +Hardware +******** + +- Renesas RA4MA1 Processor (ARM Cortex-M4 at 48 MHz) +- 256 KiB flash memory and 32 KiB of RAM +- One user LEDs +- One reset button +- One WiFi Transceiver (Arduino UNO R4 WiFi only) +- One 12x8 LED Matrix (Arduino UNO R4 WiFi only) +- Built-in CMSIS-DAP debug adapter (Arduino UNO R4 WiFi only) + +Supported Features +================== + +The Arduino UNO R4 Minima/Wifi board configuration supports the following +hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| UART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ + Programming and debugging ************************* +Debug adapter +============= + +A debug adapter is required to flash and debug programs. +Arduino UNO R4 WiFi has a built-in debug adapter that +you can use for flashing and debugging. + +In the Arduino UNO R4 Minima case, You need to prepare +debug adapter separately. A 5V-compatible CMSIS-DAP adapter +adapts to this board. + + Building & Flashing =================== -You can build and flash an application in the usual way (See +You can build and flash with ``west flash`` command (See :ref:`build_an_application` and :ref:`application_run` for more details). @@ -26,10 +63,15 @@ Here is an example for building and flashing the :zephyr:code-sample:`blinky` ap :board: arduino_uno_r4_minima :goals: build flash +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: arduino_uno_r4_wifi + :goals: build flash + Debugging ========= -Debugging also can be done in the usual way. +Debugging can be done with ``west debug`` command. The following command is debugging the :zephyr:code-sample:`blinky` application. Also, see the instructions specific to the debug server that you use. @@ -39,6 +81,12 @@ Also, see the instructions specific to the debug server that you use. :maybe-skip-config: :goals: debug +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: arduino_uno_r4_wifi + :maybe-skip-config: + :goals: debug + Using pyOCD ----------- @@ -62,3 +110,8 @@ If you corrupt the Arduino bootloader, you can restore it with the following com wget https://raw.githubusercontent.com/arduino/ArduinoCore-renesas/main/bootloaders/UNO_R4/dfu_minima.hex pyocd flash -e sector -a 0x0 -t r7fa4m1ab dfu_minima.hex + +.. code-block:: console + + wget https://raw.githubusercontent.com/arduino/ArduinoCore-renesas/main/bootloaders/UNO_R4/dfu_wifi.hex + pyocd flash -e sector -a 0x0 -t r7fa4m1ab dfu_wifi.hex From 97fcbc905b95c45b1e47bd8e9b0b54718ac18f0f Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Fri, 29 Mar 2024 13:21:34 +0800 Subject: [PATCH 2125/2402] drivers: memc: fix FlexRAM bank cfg issue From IMXRT1170RM.pdf, iomuxc_gpr->GPR17 is used to configure FlexRAM bank 0~7. iomuxc_gpr->GPR18 is used to configure FlexRAM bank 8~15. Set low 2 bytes to iomuxc_gpr->GPR17. Set high 2 bytes to iomuxc_gpr->GPR18. Signed-off-by: Lyle Zhu --- drivers/memc/memc_nxp_flexram.h | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/memc/memc_nxp_flexram.h b/drivers/memc/memc_nxp_flexram.h index 5ea2e89d0cc..2bc0e03752e 100644 --- a/drivers/memc/memc_nxp_flexram.h +++ b/drivers/memc/memc_nxp_flexram.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,7 +7,7 @@ #include #include -#define FLEXRAM_DT_NODE DT_INST(0, nxp_flexram) +#define FLEXRAM_DT_NODE DT_INST(0, nxp_flexram) #define IOMUXC_GPR_DT_NODE DT_NODELABEL(iomuxcgpr) #if defined(CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API) || \ @@ -44,20 +44,27 @@ void memc_flexram_register_callback(flexram_callback_t callback, void *user_data * call from platform_init to set up flexram if using runtime map * must be inlined because cannot use stack */ -#define GPR17_REG_FILL(node_id, prop, idx) + (DT_PROP_BY_IDX(node_id, prop, idx) << (2*idx)) +#define GPR_FLEXRAM_REG_FILL(node_id, prop, idx) \ + (((uint32_t)DT_PROP_BY_IDX(node_id, prop, idx)) << (2 * idx)) static inline void memc_flexram_dt_partition(void) { /* iomuxc_gpr must be const (in ROM region) because used in reconfiguring ram */ static IOMUXC_GPR_Type *const iomuxc_gpr = - (IOMUXC_GPR_Type *) DT_REG_ADDR(IOMUXC_GPR_DT_NODE); + (IOMUXC_GPR_Type *)DT_REG_ADDR(IOMUXC_GPR_DT_NODE); /* do not create stack variables or use any data from ram in this function */ - iomuxc_gpr->GPR17 = DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, - flexram_bank_spec, GPR17_REG_FILL, (+)); +#if defined(CONFIG_SOC_SERIES_IMXRT11XX) + iomuxc_gpr->GPR17 = (DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, flexram_bank_spec, + GPR_FLEXRAM_REG_FILL, (+))) & 0xFFFF; + iomuxc_gpr->GPR18 = (((DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, flexram_bank_spec, + GPR_FLEXRAM_REG_FILL, (+)))) >> 16) & 0xFFFF; +#elif defined(CONFIG_SOC_SERIES_IMXRT10XX) + iomuxc_gpr->GPR17 = DT_FOREACH_PROP_ELEM_SEP(FLEXRAM_DT_NODE, flexram_bank_spec, + GPR_FLEXRAM_REG_FILL, (+)); +#endif iomuxc_gpr->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK; } #endif /* FLEXRAM_RUNTIME_BANKS_USED */ - #ifdef CONFIG_MEMC_NXP_FLEXRAM_MAGIC_ADDR_API /** @brief Sets magic address for OCRAM * From 85b86daa01adf009202499c4adaff57e143e98d6 Mon Sep 17 00:00:00 2001 From: Lluis Campos Date: Wed, 10 Apr 2024 12:48:09 +0200 Subject: [PATCH 2126/2402] doc: device_mgmt: Fix typo in link text Previously it read "there is a sample sample that..." Signed-off-by: Lluis Campos --- doc/services/device_mgmt/mcumgr.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/services/device_mgmt/mcumgr.rst b/doc/services/device_mgmt/mcumgr.rst index 6d4d575baa1..905307ab424 100644 --- a/doc/services/device_mgmt/mcumgr.rst +++ b/doc/services/device_mgmt/mcumgr.rst @@ -31,7 +31,7 @@ systems. The management subsystem is located in :zephyr_file:`subsys/mgmt/` inside of the Zephyr tree. -Additionally, there is a :zephyr:code-sample:`sample ` sample that provides +Additionally, there is a :zephyr:code-sample:`sample ` server that provides management functionality over BLE and serial. .. _mcumgr_tools_libraries: From f47b862c446746985a43018c2375f132f4b9dcb9 Mon Sep 17 00:00:00 2001 From: Fabian Blatz Date: Wed, 10 Apr 2024 11:28:48 +0200 Subject: [PATCH 2127/2402] modules: lvgl: Kconfig: Add missing stubs for DMA2D kconfig symbols Adds the missing stubs for DMA2D kconfig symbol to fix the Kconfig warning produced by checkpatch. Resolves #70859 Signed-off-by: Fabian Blatz --- modules/lvgl/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/modules/lvgl/Kconfig b/modules/lvgl/Kconfig index dba26b76d89..932df9e55d9 100644 --- a/modules/lvgl/Kconfig +++ b/modules/lvgl/Kconfig @@ -127,6 +127,15 @@ config LV_Z_AREA_Y_ALIGNMENT_WIDTH the current frame dimensions to meet display and/or LCD host controller requirements. The value must be power of 2. +config LV_USE_GPU_STM32_DMA2D + bool + +config LV_GPU_DMA2D_CMSIS_INCLUDE + string + help + Must be defined to include path of CMSIS header of target processor + e.g. "stm32f769xx.h" or "stm32f429xx.h" + rsource "Kconfig.memory" rsource "Kconfig.input" rsource "Kconfig.shell" From b29be06ec2560bff36a61a25b4a4f666144c1f98 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Mon, 8 Apr 2024 16:42:28 +0200 Subject: [PATCH 2128/2402] boards: espressif: Update documentation Update the booting information in recently added Espressif boards to include simple boot method. Signed-off-by: Marek Matej --- boards/espressif/esp32s2_devkitc/doc/index.rst | 13 ++++++++----- boards/espressif/esp32s3_devkitc/doc/index.rst | 13 ++++++++----- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/boards/espressif/esp32s2_devkitc/doc/index.rst b/boards/espressif/esp32s2_devkitc/doc/index.rst index a51e904fe6f..bfe8eb3fc7d 100644 --- a/boards/espressif/esp32s2_devkitc/doc/index.rst +++ b/boards/espressif/esp32s2_devkitc/doc/index.rst @@ -88,12 +88,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== diff --git a/boards/espressif/esp32s3_devkitc/doc/index.rst b/boards/espressif/esp32s3_devkitc/doc/index.rst index 4be477a51dd..60edc732b56 100644 --- a/boards/espressif/esp32s3_devkitc/doc/index.rst +++ b/boards/espressif/esp32s3_devkitc/doc/index.rst @@ -137,12 +137,15 @@ below to retrieve those files. Building & Flashing ******************* -ESP-IDF bootloader -================== +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. + Simple boot does not provide any security features nor OTA updates. MCUboot bootloader ================== From 7c506fad6b36208f6f8da0da30ed54a249467e45 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Mon, 8 Apr 2024 16:13:14 +0200 Subject: [PATCH 2129/2402] drivers: net: nsos: fix error message on EPOLL_CTL_DEL error Fix a copy-pasted error message to reference proper epoll_ctl() operation. Signed-off-by: Marcin Niestroj --- drivers/net/nsos_adapt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/nsos_adapt.c b/drivers/net/nsos_adapt.c index a7ecd46eeb4..9c8184bd61b 100644 --- a/drivers/net/nsos_adapt.c +++ b/drivers/net/nsos_adapt.c @@ -526,7 +526,7 @@ void nsos_adapt_poll_remove(struct nsos_mid_pollfd *pollfd) err = epoll_ctl(nsos_epoll_fd, EPOLL_CTL_DEL, pollfd->fd, NULL); if (err) { - nsi_print_error_and_exit("error in EPOLL_CTL_ADD: errno=%d\n", errno); + nsi_print_error_and_exit("error in EPOLL_CTL_DEL: errno=%d\n", errno); return; } From ea44e2715a504600cbcff4dd9cf31d6ffeaf349c Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Mon, 8 Apr 2024 16:13:19 +0200 Subject: [PATCH 2130/2402] drivers: net: nsos: update unwatched file descriptor with poll() zsock_poll_internal() iterates through all fds to call ZFD_IOCTL_POLL_UPDATE on them. In cases when -EAGAIN is returned from one of such syscalls (which happens for example for TLS sockets when in the middle of a TLS handshake) whole fds array is iterated once again. This means that ZFD_IOCTL_POLL_UPDATE can be called more than once for a single preceding ZFD_IOCTL_POLL_PREPARE operation. This resulted in error in nsos_adapt_poll_remove() call, which was not intended to be called twice. In case ZFD_IOCTL_POLL_UPDATE is called second time, update 'revents' just by calling poll() syscall on the host (Linux) side with 0 timeout. Signed-off-by: Marcin Niestroj --- drivers/net/nsos.h | 1 + drivers/net/nsos_adapt.c | 19 +++++++++++++++++++ drivers/net/nsos_sockets.c | 5 +++++ 3 files changed, 25 insertions(+) diff --git a/drivers/net/nsos.h b/drivers/net/nsos.h index 14b495177c3..e7ece3ded7e 100644 --- a/drivers/net/nsos.h +++ b/drivers/net/nsos.h @@ -113,6 +113,7 @@ int nsos_adapt_recvfrom(int fd, void *buf, size_t len, int flags, void nsos_adapt_poll_add(struct nsos_mid_pollfd *pollfd); void nsos_adapt_poll_remove(struct nsos_mid_pollfd *pollfd); +void nsos_adapt_poll_update(struct nsos_mid_pollfd *pollfd); int nsos_adapt_fcntl_getfl(int fd); int nsos_adapt_fcntl_setfl(int fd, int flags); diff --git a/drivers/net/nsos_adapt.c b/drivers/net/nsos_adapt.c index 9c8184bd61b..5f44b332f60 100644 --- a/drivers/net/nsos_adapt.c +++ b/drivers/net/nsos_adapt.c @@ -533,6 +533,25 @@ void nsos_adapt_poll_remove(struct nsos_mid_pollfd *pollfd) nsos_adapt_nfds--; } +void nsos_adapt_poll_update(struct nsos_mid_pollfd *pollfd) +{ + struct pollfd fds = { + .fd = pollfd->fd, + .events = pollfd->events, + }; + int ret; + + ret = poll(&fds, 1, 0); + if (ret < 0) { + nsi_print_error_and_exit("error in poll(): errno=%d\n", errno); + return; + } + + if (ret > 0) { + pollfd->revents = fds.revents; + } +} + struct nsos_addrinfo_wrap { struct nsos_mid_addrinfo addrinfo_mid; struct nsos_mid_sockaddr_storage addr_storage; diff --git a/drivers/net/nsos_sockets.c b/drivers/net/nsos_sockets.c index 98d6c429906..2e1ff4589d1 100644 --- a/drivers/net/nsos_sockets.c +++ b/drivers/net/nsos_sockets.c @@ -298,6 +298,11 @@ static int nsos_poll_update(struct nsos_socket *sock, struct zsock_pollfd *pfd, signaled = 0; flags = 0; + if (!sys_dnode_is_linked(&sock->node)) { + nsos_adapt_poll_update(&sock->pollfd); + return 0; + } + nsos_adapt_poll_remove(&sock->pollfd); sys_dlist_remove(&sock->node); From d2b3e3a38963c6a3954c2af18f68a07f883cdc7a Mon Sep 17 00:00:00 2001 From: Marcin Szymczyk Date: Wed, 10 Apr 2024 12:30:24 +0200 Subject: [PATCH 2131/2402] sysbuild: add SoC-specific sysbuild configuration Sysbuild now supports SoC configuration, in addition to application and board. Signed-off-by: Marcin Szymczyk --- cmake/modules/hwm_v2.cmake | 5 +++++ share/sysbuild/Kconfig | 1 + share/sysbuild/images/CMakeLists.txt | 3 ++- share/sysbuild/images/soc/CMakeLists.txt | 5 +++++ 4 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 share/sysbuild/images/soc/CMakeLists.txt diff --git a/cmake/modules/hwm_v2.cmake b/cmake/modules/hwm_v2.cmake index 38af4083fb1..45238f212b3 100644 --- a/cmake/modules/hwm_v2.cmake +++ b/cmake/modules/hwm_v2.cmake @@ -12,6 +12,7 @@ # - Kconfig.defconfig: Contains references to SoC defconfig files for Zephyr integration. # - Kconfig: Contains references to regular SoC Kconfig files for Zephyr integration. # - Kconfig.soc: Contains references to generic SoC Kconfig files. +# - Kconfig.sysbuild: Contains references to SoC sysbuild Kconfig files. # # The following file is generated in '/arch' # - Kconfig: Contains references to regular arch Kconfig files for Zephyr integration. @@ -96,19 +97,23 @@ set(arch_kconfig_file Kconfig) set(soc_defconfig_file Kconfig.defconfig) set(soc_zephyr_file Kconfig) set(soc_kconfig_file Kconfig.soc) +set(soc_sysbuild_file Kconfig.sysbuild) set(arch_kconfig_header "# Load arch Kconfig descriptions.\n") set(defconfig_header "# Load Zephyr SoC Kconfig defconfig.\n") set(soc_zephyr_header "# Load Zephyr SoC Kconfig descriptions.\n") set(soc_kconfig_header "# Load SoC Kconfig descriptions.\n") +set(soc_sysbuild_header "# Load SoC sysbuild Kconfig descriptions.\n") file(WRITE ${KCONFIG_BINARY_DIR}/arch/${arch_kconfig_file} "${arch_kconfig_header}") file(WRITE ${KCONFIG_BINARY_DIR}/soc/${soc_defconfig_file} "${defconfig_header}") file(WRITE ${KCONFIG_BINARY_DIR}/soc/${soc_zephyr_file} "${soc_zephyr_header}") file(WRITE ${KCONFIG_BINARY_DIR}/soc/${soc_kconfig_file} "${soc_kconfig_header}") +file(WRITE ${KCONFIG_BINARY_DIR}/soc/${soc_sysbuild_file} "${soc_sysbuild_header}") kconfig_gen("${KCONFIG_BINARY_DIR}/arch" "${arch_kconfig_file}" "${kconfig_arch_source_dir}") kconfig_gen("${KCONFIG_BINARY_DIR}/soc" "${soc_defconfig_file}" "${kconfig_soc_source_dir}") kconfig_gen("${KCONFIG_BINARY_DIR}/soc" "${soc_zephyr_file}" "${kconfig_soc_source_dir}") kconfig_gen("${KCONFIG_BINARY_DIR}/soc" "${soc_kconfig_file}" "${kconfig_soc_source_dir}") +kconfig_gen("${KCONFIG_BINARY_DIR}/soc" "${soc_sysbuild_file}" "${kconfig_soc_source_dir}") # Clear variables created by cmake_parse_arguments unset(SOC_V2_NAME) diff --git a/share/sysbuild/Kconfig b/share/sysbuild/Kconfig index d8a0cf25b8e..556462af310 100644 --- a/share/sysbuild/Kconfig +++ b/share/sysbuild/Kconfig @@ -7,6 +7,7 @@ rsource "Kconfig.$(HWM_SCHEME)" comment "Sysbuild image configuration" osource "$(BOARD_DIR)/Kconfig.sysbuild" +osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig.sysbuild" menu "Modules" diff --git a/share/sysbuild/images/CMakeLists.txt b/share/sysbuild/images/CMakeLists.txt index 2b553181d06..1d9e381fa5c 100644 --- a/share/sysbuild/images/CMakeLists.txt +++ b/share/sysbuild/images/CMakeLists.txt @@ -32,5 +32,6 @@ endforeach() set(SYSBUILD_CURRENT_MODULE_DIR) set(SYSBUILD_CURRENT_CMAKE_DIR) -# This allows for board specific images to be included. +# This allows for board and SoC specific images to be included. sysbuild_add_subdirectory(boards) +sysbuild_add_subdirectory(soc) diff --git a/share/sysbuild/images/soc/CMakeLists.txt b/share/sysbuild/images/soc/CMakeLists.txt new file mode 100644 index 00000000000..1e7775caa52 --- /dev/null +++ b/share/sysbuild/images/soc/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +include(${SOC_${SB_CONFIG_SOC}_DIR}/sysbuild.cmake OPTIONAL) From 79c3ba802a1a7bded2399aabb03afbee23885745 Mon Sep 17 00:00:00 2001 From: Dmytro Firsov Date: Tue, 2 Apr 2024 13:42:48 +0300 Subject: [PATCH 2132/2402] boards: xenvm: return userspace testcases for XenVM board XenVM boards were mark as unsupported for twister testcases related to userspace. After additional investigation no problems were found for builds, so there are no reason to exclude it from test runs. Signed-off-by: Dmytro Firsov --- boards/xen/xenvm/xenvm.yaml | 3 --- boards/xen/xenvm/xenvm_xenvm_gicv3.yaml | 3 --- 2 files changed, 6 deletions(-) diff --git a/boards/xen/xenvm/xenvm.yaml b/boards/xen/xenvm/xenvm.yaml index dc72d05e550..2cd38e3c399 100644 --- a/boards/xen/xenvm/xenvm.yaml +++ b/boards/xen/xenvm/xenvm.yaml @@ -7,6 +7,3 @@ toolchain: - cross-compile ram: 16384 vendor: xen -testing: - ignore_tags: - - userspace diff --git a/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml b/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml index edf816e4979..a680dd6d0cf 100644 --- a/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml +++ b/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml @@ -7,6 +7,3 @@ toolchain: - cross-compile ram: 16384 vendor: xen -testing: - ignore_tags: - - userspace From 424ea9f5e42c50b40faf7c70bf443999e47e9b68 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Mon, 8 Apr 2024 18:13:35 +0200 Subject: [PATCH 2133/2402] drivers: wifi: esp_at: do not connect socket on bind(INADDR_ANY) All connect() syscalls result in EISCONN error, since underlying _sock_connect() is attempted to be called twice. Once from net_context.c' bind_default() (with INADDR_ANY) as part of esp_bind() and second time as part of esp_connect(). Do not call _sock_connect() from esp_bind(INADDR_ANY), which happens as part of connect(). Fixes: dbf3d6e9110a ("drivers: esp_at: implement bind() and recvfrom() for UDP sockets") Signed-off-by: Marcin Niestroj --- drivers/wifi/esp_at/esp_offload.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/wifi/esp_at/esp_offload.c b/drivers/wifi/esp_at/esp_offload.c index 96e2b143a21..31c59d11fc7 100644 --- a/drivers/wifi/esp_at/esp_offload.c +++ b/drivers/wifi/esp_at/esp_offload.c @@ -110,8 +110,14 @@ static int esp_bind(struct net_context *context, const struct sockaddr *addr, } if (IS_ENABLED(CONFIG_NET_IPV4) && addr->sa_family == AF_INET) { + struct sockaddr_in *addr4 = (struct sockaddr_in *)addr; + LOG_DBG("link %d", sock->link_id); + if (addr4->sin_addr.s_addr == INADDR_ANY) { + return 0; + } + if (esp_socket_connected(sock)) { return -EISCONN; } From 00b46686b12d853663607e49cfbc997466d46920 Mon Sep 17 00:00:00 2001 From: David Leach Date: Fri, 5 Apr 2024 22:41:40 -0500 Subject: [PATCH 2134/2402] drivers: lpc55s36: Remove deprecated CSS driver CSS was deprecated from the mcu-sdk. Removing driver from lpc55s36 to clear build error. This is a temporary patch to remove the build error. Fixes #69961 Signed-off-by: David Leach --- boards/nxp/lpcxpresso55s36/doc/index.rst | 2 - .../nxp/lpcxpresso55s36/lpcxpresso55s36.yaml | 5 -- drivers/entropy/CMakeLists.txt | 1 - drivers/entropy/Kconfig.mcux | 8 --- drivers/entropy/entropy_mcux_css.c | 55 ------------------- dts/arm/nxp/nxp_lpc55S3x_common.dtsi | 10 ---- dts/bindings/rng/nxp,css-v2.yaml | 12 ---- west.yml | 2 +- 8 files changed, 1 insertion(+), 94 deletions(-) delete mode 100644 drivers/entropy/entropy_mcux_css.c delete mode 100644 dts/bindings/rng/nxp,css-v2.yaml diff --git a/boards/nxp/lpcxpresso55s36/doc/index.rst b/boards/nxp/lpcxpresso55s36/doc/index.rst index a8914f20154..bff3ef5d36a 100644 --- a/boards/nxp/lpcxpresso55s36/doc/index.rst +++ b/boards/nxp/lpcxpresso55s36/doc/index.rst @@ -77,8 +77,6 @@ already supported, which can also be re-used on this lpcxpresso55s36 board: +-----------+------------+-------------------------------------+ | PWM | on-chip | pwm | +-----------+------------+-------------------------------------+ -| CSS | on-chip | entropy | -+-----------+------------+-------------------------------------+ | USB FS | on-chip | USB Full Speed device | +-----------+------------+-------------------------------------+ | DAC | on-chip | dac | diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml index 58dbfb9df65..5a28b2149c5 100644 --- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml @@ -20,8 +20,3 @@ supported: - pwm - dac vendor: nxp -env: # Provisional hack to prevent tests being run in this board, as it fails in many test & samples - - LPCXPRESSO55S36_TWISTER_ENABLE - # Twister won't run tests in this board unless LPCXPRESSO55S36_TWISTER_ENABLE is set in the - # environment, which it normally won't. - # Once https://github.com/zephyrproject-rtos/zephyr/issues/69961 is fixed this should be removed diff --git a/drivers/entropy/CMakeLists.txt b/drivers/entropy/CMakeLists.txt index 02a32ed252a..c3d37e1461a 100644 --- a/drivers/entropy/CMakeLists.txt +++ b/drivers/entropy/CMakeLists.txt @@ -11,7 +11,6 @@ zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_RNG entropy_mcux_rng. zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_RNGA entropy_mcux_rnga.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_TRNG entropy_mcux_trng.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_CAAM entropy_mcux_caam.c) -zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_CSS entropy_mcux_css.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_NRF5_RNG entropy_nrf5.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_SAM_RNG entropy_sam.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_SMARTBOND_TRNG entropy_smartbond.c) diff --git a/drivers/entropy/Kconfig.mcux b/drivers/entropy/Kconfig.mcux index 40941a20610..af4d8dc3d67 100644 --- a/drivers/entropy/Kconfig.mcux +++ b/drivers/entropy/Kconfig.mcux @@ -40,14 +40,6 @@ config ENTROPY_MCUX_CAAM This option enables the CAAM driver based on the MCUX CAAM driver. -config ENTROPY_MCUX_CSS - bool "MCUX CSS RNG driver" - default y - depends on DT_HAS_NXP_CSS_V2_ENABLED - select ENTROPY_HAS_DRIVER - help - This option enables the driver for random number generation using - the CSS (Crypto Subsystem). # # Don't use use the MCUX TRNG as a random source as it is not designed # to supply a continuous random stream. Instead, it is used to provide diff --git a/drivers/entropy/entropy_mcux_css.c b/drivers/entropy/entropy_mcux_css.c deleted file mode 100644 index e0a5853aa25..00000000000 --- a/drivers/entropy/entropy_mcux_css.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT nxp_css_v2 - -#include "mcuxClCss_Rng.h" - -#include -#include -#include -#include - -static int entropy_mcux_css_get_entropy(const struct device *dev, uint8_t *buffer, uint16_t length) -{ - ARG_UNUSED(dev); - uint8_t status = 0; - - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_Prng_GetRandom(buffer, length)); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Prng_GetRandom) != token) || - (result != MCUXCLCSS_STATUS_OK)) { - status = -EAGAIN; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - __ASSERT_NO_MSG(!status); - - return status; -} - -static const struct entropy_driver_api entropy_mcux_css_api_funcs = { - .get_entropy = entropy_mcux_css_get_entropy -}; - -static int entropy_mcux_css_init(const struct device *dev) -{ - ARG_UNUSED(dev); - uint8_t status = 0; - - MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_Enable_Async()); - if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Enable_Async) != token) || - (result != MCUXCLCSS_STATUS_OK_WAIT)) { - status = -ENODEV; - } - MCUX_CSSL_FP_FUNCTION_CALL_END(); - - __ASSERT_NO_MSG(!status); - - return status; -} - -DEVICE_DT_INST_DEFINE(0, entropy_mcux_css_init, NULL, NULL, NULL, PRE_KERNEL_1, - CONFIG_ENTROPY_INIT_PRIORITY, &entropy_mcux_css_api_funcs); diff --git a/dts/arm/nxp/nxp_lpc55S3x_common.dtsi b/dts/arm/nxp/nxp_lpc55S3x_common.dtsi index 16b90cb7392..328633f5163 100644 --- a/dts/arm/nxp/nxp_lpc55S3x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S3x_common.dtsi @@ -13,10 +13,6 @@ #include / { - chosen { - zephyr,entropy = &css; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -270,12 +266,6 @@ #size-cells = <0>; }; - css: css@4003000 { - compatible = "nxp,css-v2"; - reg = <0x4003000 0x200>; - status = "okay"; - }; - adc0: adc@A0000 { compatible = "nxp,lpc-lpadc"; reg = <0xA0000 0x1000>; diff --git a/dts/bindings/rng/nxp,css-v2.yaml b/dts/bindings/rng/nxp,css-v2.yaml deleted file mode 100644 index 18ac4ee3d85..00000000000 --- a/dts/bindings/rng/nxp,css-v2.yaml +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -description: CSSv2 (Crypto Subsystem) - -compatible: "nxp,css-v2" - -include: base.yaml - -properties: - reg: - required: true diff --git a/west.yml b/west.yml index 6ee89e4b0bb..9fdaa6b2be8 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 14160a1c14c06ce5a918cd550989555d832a636f + revision: 4ab0e7bc9c44840cbb22a6dd74c214713f239182 path: modules/hal/nxp groups: - hal From 7b1d9d61662c00f3b5914c2fff84eb4ededa5b66 Mon Sep 17 00:00:00 2001 From: Cedric Lescop Date: Wed, 10 Apr 2024 11:05:26 +0200 Subject: [PATCH 2135/2402] llext: Full ARM ELF relocation support Adds support for all relocation type produced by GCC on ARM platform using partial linking (-r flag) or shared link (-fpic and -shared flag). Signed-off-by: Cedric Lescop --- arch/arm/core/elf.c | 352 +++++++++++++++++++++++++++++++---- include/zephyr/llext/elf.h | 24 ++- include/zephyr/llext/llext.h | 13 +- subsys/llext/llext.c | 27 ++- 4 files changed, 362 insertions(+), 54 deletions(-) diff --git a/arch/arm/core/elf.c b/arch/arm/core/elf.c index e3c137e49f2..108c72728d5 100644 --- a/arch/arm/core/elf.c +++ b/arch/arm/core/elf.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 Intel Corporation + * Copyright (c) 2024 Schneider Electric * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,42 +12,266 @@ LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL); -#define ARM_BL_BLX_UPPER_S_BIT BIT(10) -#define ARM_BL_BLX_ADDEND_OFFSET 0 -#define ARM_BL_BLX_ADDEND_SIZE 11 -#define ARM_BL_BLX_ADDEND_MASK 0x7FF -#define ARM_BL_BLX_HDR_MASK 0xF800 -#define ARM_BL_BLX_LOWER_T1T2_BIT BIT(12) +#define OPCODE2ARMMEM(x) ((uint32_t)(x)) +#define OPCODE2THM16MEM(x) ((uint16_t)(x)) +#define MEM2ARMOPCODE(x) OPCODE2ARMMEM(x) +#define MEM2THM16OPCODE(x) OPCODE2THM16MEM(x) +#define JUMP_UPPER_BOUNDARY ((int32_t)0xfe000000) +#define JUMP_LOWER_BOUNDARY ((int32_t)0x2000000) +#define PREL31_UPPER_BOUNDARY ((int32_t)0x40000000) +#define PREL31_LOWER_BOUNDARY ((int32_t)-0x40000000) +#define THM_JUMP_UPPER_BOUNDARY ((int32_t)0xff000000) +#define THM_JUMP_LOWER_BOUNDARY ((int32_t)0x01000000) +#define MASK_V4BX_RM_COND 0xf000000f +#define MASK_V4BX_NOT_RM_COND 0x01a0f000 +#define MASK_BRANCH_COND GENMASK(31, 28) +#define MASK_BRANCH_101 GENMASK(27, 25) +#define MASK_BRANCH_L BIT(24) +#define MASK_BRANCH_OFFSET GENMASK(23, 0) +#define MASK_MOV_COND GENMASK(31, 28) +#define MASK_MOV_00 GENMASK(27, 26) +#define MASK_MOV_I BIT(25) +#define MASK_MOV_OPCODE GENMASK(24, 21) +#define MASK_MOV_S BIT(20) +#define MASK_MOV_RN GENMASK(19, 16) +#define MASK_MOV_RD GENMASK(15, 12) +#define MASK_MOV_OPERAND2 GENMASK(11, 0) +#define BIT_THM_BW_S 10 +#define MASK_THM_BW_11110 GENMASK(15, 11) +#define MASK_THM_BW_S BIT(10) +#define MASK_THM_BW_IMM10 GENMASK(9, 0) +#define BIT_THM_BL_J1 13 +#define BIT_THM_BL_J2 11 +#define MASK_THM_BL_10 GENMASK(15, 14) +#define MASK_THM_BL_J1 BIT(13) +#define MASK_THM_BL_1 BIT(12) +#define MASK_THM_BL_J2 BIT(11) +#define MASK_THM_BL_IMM11 GENMASK(10, 0) +#define MASK_THM_MOV_11110 GENMASK(15, 11) +#define MASK_THM_MOV_I BIT(10) +#define MASK_THM_MOV_100100 GENMASK(9, 4) +#define MASK_THM_MOV_IMM4 GENMASK(3, 0) +#define MASK_THM_MOV_0 BIT(15) +#define MASK_THM_MOV_IMM3 GENMASK(14, 12) +#define MASK_THM_MOV_RD GENMASK(11, 8) +#define MASK_THM_MOV_IMM8 GENMASK(7, 0) +#define SHIFT_PREL31_SIGN 30 +#define SHIFT_BRANCH_OFFSET 2 +#define SHIFT_JUMPS_SIGN 25 +#define SHIFT_MOV_RD 4 +#define SHIFT_MOV_RN 4 +#define SHIFT_MOVS_SIGN 15 +#define SHIFT_THM_JUMPS_SIGN 24 +#define SHIFT_THM_BW_IMM10 12 +#define SHIFT_THM_BL_J2 22 +#define SHIFT_THM_BL_J1 23 +#define SHIFT_THM_MOVS_SIGN 15 +#define SHIFT_THM_MOV_I 1 +#define SHIFT_THM_MOV_IMM3 4 +#define SHIFT_THM_MOV_IMM4 12 -static int32_t arm_bl_blx_decode_addend(uintptr_t opaddr) +static inline int prel31_decode(elf_word reloc_type, uint32_t loc, + uint32_t sym_base_addr, const char *sym_name, int32_t *offset) { - uint16_t upper = *((uint16_t *)opaddr); - uint16_t lower = *(((uint16_t *)opaddr) + 1); + int ret; - int32_t addend = upper & ARM_BL_BLX_UPPER_S_BIT ? UINT32_MAX : 0; + *offset = sign_extend(*(int32_t *)loc, SHIFT_PREL31_SIGN); + *offset += sym_base_addr - loc; + if (*offset >= PREL31_UPPER_BOUNDARY || *offset < PREL31_LOWER_BOUNDARY) { + LOG_ERR("sym '%s': relocation out of range (%#x -> %#x)\n", + sym_name, loc, sym_base_addr); + ret = -ENOEXEC; + } else { + ret = 0; + } + + return ret; +} + +static inline void prel31_reloc(uint32_t loc, int32_t *offset) +{ + *(uint32_t *)loc &= BIT(31); + *(uint32_t *)loc |= *offset & GENMASK(30, 0); +} + +static int prel31_handler(elf_word reloc_type, uint32_t loc, + uint32_t sym_base_addr, const char *sym_name) +{ + int ret; + int32_t offset; + + ret = prel31_decode(reloc_type, loc, sym_base_addr, sym_name, &offset); + if (!ret) { + prel31_reloc(loc, &offset); + } - addend <<= ARM_BL_BLX_ADDEND_SIZE; - addend |= upper & ARM_BL_BLX_ADDEND_MASK; - addend <<= ARM_BL_BLX_ADDEND_SIZE; - addend |= lower & ARM_BL_BLX_ADDEND_MASK; + return ret; +} + +static inline int jumps_decode(elf_word reloc_type, uint32_t loc, + uint32_t sym_base_addr, const char *sym_name, int32_t *offset) +{ + int ret; + + *offset = MEM2ARMOPCODE(*(uint32_t *)loc); + *offset = (*offset & MASK_BRANCH_OFFSET) << SHIFT_BRANCH_OFFSET; + *offset = sign_extend(*offset, SHIFT_JUMPS_SIGN); + *offset += sym_base_addr - loc; + if (*offset >= JUMP_LOWER_BOUNDARY || *offset <= JUMP_UPPER_BOUNDARY) { + LOG_ERR("sym '%s': relocation out of range (%#x -> %#x)\n", + sym_name, loc, sym_base_addr); + ret = -ENOEXEC; + } else { + ret = 0; + } - return lower & ARM_BL_BLX_LOWER_T1T2_BIT ? addend << 1 : addend << 2; + return ret; } -static void arm_bl_blx_encode_addend(uintptr_t opaddr, int32_t addend) +static inline void jumps_reloc(uint32_t loc, int32_t *offset) { - uint16_t upper = *((uint16_t *)opaddr); - uint16_t lower = *(((uint16_t *)opaddr) + 1); + *offset >>= SHIFT_BRANCH_OFFSET; + *offset &= MASK_BRANCH_OFFSET; - addend = upper & ARM_BL_BLX_UPPER_S_BIT ? addend >> 1 : addend >> 2; + *(uint32_t *)loc &= OPCODE2ARMMEM(MASK_BRANCH_COND|MASK_BRANCH_101|MASK_BRANCH_L); + *(uint32_t *)loc |= OPCODE2ARMMEM(*offset); +} - upper &= ARM_BL_BLX_HDR_MASK; - lower &= ARM_BL_BLX_HDR_MASK; - upper |= (addend >> ARM_BL_BLX_ADDEND_SIZE) & ARM_BL_BLX_ADDEND_MASK; - lower |= addend & ARM_BL_BLX_ADDEND_MASK; +static int jumps_handler(elf_word reloc_type, uint32_t loc, + uint32_t sym_base_addr, const char *sym_name) +{ + int ret; + int32_t offset; - *((uint16_t *)opaddr) = upper; - *(((uint16_t *)opaddr) + 1) = lower; + ret = jumps_decode(reloc_type, loc, sym_base_addr, sym_name, &offset); + if (!ret) { + jumps_reloc(loc, &offset); + } + + return ret; +} + +static void movs_handler(elf_word reloc_type, uint32_t loc, + uint32_t sym_base_addr, const char *sym_name) +{ + int32_t offset; + uint32_t tmp; + + offset = tmp = MEM2ARMOPCODE(*(uint32_t *)loc); + offset = ((offset & MASK_MOV_RN) >> SHIFT_MOV_RN) | (offset & MASK_MOV_OPERAND2); + offset = sign_extend(offset, SHIFT_MOVS_SIGN); + + offset += sym_base_addr; + if (reloc_type == R_ARM_MOVT_PREL || reloc_type == R_ARM_MOVW_PREL_NC) { + offset -= loc; + } + if (reloc_type == R_ARM_MOVT_ABS || reloc_type == R_ARM_MOVT_PREL) { + offset >>= 16; + } + + tmp &= (MASK_MOV_COND | MASK_MOV_00 | MASK_MOV_I | MASK_MOV_OPCODE | MASK_MOV_RD); + tmp |= ((offset & MASK_MOV_RD) << SHIFT_MOV_RD) | (offset & MASK_MOV_OPERAND2); + + *(uint32_t *)loc = OPCODE2ARMMEM(tmp); +} + +static inline int thm_jumps_decode(elf_word reloc_type, uint32_t loc, + uint32_t sym_base_addr, const char *sym_name, int32_t *offset, + uint32_t *upper, uint32_t *lower) +{ + int ret; + uint32_t j_one, j_two, sign; + + *upper = MEM2THM16OPCODE(*(uint16_t *)loc); + *lower = MEM2THM16OPCODE(*(uint16_t *)(loc + 2)); + + /* sign is bit10 */ + sign = (*upper >> BIT_THM_BW_S) & 1; + j_one = (*lower >> BIT_THM_BL_J1) & 1; + j_two = (*lower >> BIT_THM_BL_J2) & 1; + *offset = (sign << SHIFT_THM_JUMPS_SIGN) | + ((~(j_one ^ sign) & 1) << SHIFT_THM_BL_J1) | + ((~(j_two ^ sign) & 1) << SHIFT_THM_BL_J2) | + ((*upper & MASK_THM_BW_IMM10) << SHIFT_THM_BW_IMM10) | + ((*lower & MASK_THM_BL_IMM11) << 1); + *offset = sign_extend(*offset, SHIFT_THM_JUMPS_SIGN); + *offset += sym_base_addr - loc; + + if (*offset >= THM_JUMP_LOWER_BOUNDARY || *offset <= THM_JUMP_UPPER_BOUNDARY) { + LOG_ERR("sym '%s': relocation out of range (%#x -> %#x)\n", + sym_name, loc, sym_base_addr); + ret = -ENOEXEC; + } else { + ret = 0; + } + + return ret; +} + +static inline void thm_jumps_reloc(uint32_t loc, int32_t *offset, + uint32_t *upper, uint32_t *lower) +{ + uint32_t j_one, j_two, sign; + + sign = (*offset >> SHIFT_THM_JUMPS_SIGN) & 1; + j_one = sign ^ (~(*offset >> SHIFT_THM_BL_J1) & 1); + j_two = sign ^ (~(*offset >> SHIFT_THM_BL_J2) & 1); + *upper = (uint16_t)((*upper & MASK_THM_BW_11110) | (sign << BIT_THM_BW_S) | + ((*offset >> SHIFT_THM_BW_IMM10) & MASK_THM_BW_IMM10)); + *lower = (uint16_t)((*lower & (MASK_THM_BL_10|MASK_THM_BL_1)) | + (j_one << BIT_THM_BL_J1) | (j_two << BIT_THM_BL_J2) | + ((*offset >> 1) & MASK_THM_BL_IMM11)); + + *(uint16_t *)loc = OPCODE2THM16MEM(*upper); + *(uint16_t *)(loc + 2) = OPCODE2THM16MEM(*lower); +} + +static int thm_jumps_handler(elf_word reloc_type, uint32_t loc, + uint32_t sym_base_addr, const char *sym_name) +{ + int ret; + int32_t offset; + uint32_t upper, lower; + + ret = thm_jumps_decode(reloc_type, loc, sym_base_addr, sym_name, &offset, &upper, &lower); + if (!ret) { + thm_jumps_reloc(loc, &offset, &upper, &lower); + } + + return ret; +} + +static void thm_movs_handler(elf_word reloc_type, uint32_t loc, + uint32_t sym_base_addr, const char *sym_name) +{ + int32_t offset; + uint32_t upper, lower; + + upper = MEM2THM16OPCODE(*(uint16_t *)loc); + lower = MEM2THM16OPCODE(*(uint16_t *)(loc + 2)); + + /* MOVT/MOVW instructions encoding in Thumb-2 */ + offset = ((upper & MASK_THM_MOV_IMM4) << SHIFT_THM_MOV_IMM4) | + ((upper & MASK_THM_MOV_I) << SHIFT_THM_MOV_I) | + ((lower & MASK_THM_MOV_IMM3) >> SHIFT_THM_MOV_IMM3) | (lower & MASK_THM_MOV_IMM8); + offset = sign_extend(offset, SHIFT_THM_MOVS_SIGN); + offset += sym_base_addr; + + if (reloc_type == R_ARM_THM_MOVT_PREL || reloc_type == R_ARM_THM_MOVW_PREL_NC) { + offset -= loc; + } + if (reloc_type == R_ARM_THM_MOVT_ABS || reloc_type == R_ARM_THM_MOVT_PREL) { + offset >>= 16; + } + + upper = (uint16_t)((upper & (MASK_THM_MOV_11110|MASK_THM_MOV_100100)) | + ((offset & (MASK_THM_MOV_IMM4<> SHIFT_THM_MOV_IMM4) | + ((offset & (MASK_THM_MOV_I<> SHIFT_THM_MOV_I)); + lower = (uint16_t)((lower & (MASK_THM_MOV_0|MASK_THM_MOV_RD)) | + ((offset & (MASK_THM_MOV_IMM3>>SHIFT_THM_MOV_IMM3)) << SHIFT_THM_MOV_IMM3) | + (offset & MASK_THM_MOV_IMM8)); + *(uint16_t *)loc = OPCODE2THM16MEM(upper); + *(uint16_t *)(loc + 2) = OPCODE2THM16MEM(lower); } /** @@ -58,32 +283,81 @@ static void arm_bl_blx_encode_addend(uintptr_t opaddr, int32_t addend) * * The relocation codes for arm are well documented * https://github.com/ARM-software/abi-aa/blob/main/aaelf32/aaelf32.rst#relocation + * + * Handler functions prefixed by '_thm_' means that they are Thumb instructions specific. + * Do NOT mix them with not 'Thumb instructions' in the below switch/case: they are not + * intended to work together. */ -void arch_elf_relocate(elf_rela_t *rel, uintptr_t opaddr, uintptr_t opval) +int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr, + const char *sym_name, uintptr_t load_bias) { + int ret = 0; elf_word reloc_type = ELF32_R_TYPE(rel->r_info); + LOG_DBG("%d %lx %lx %s", reloc_type, loc, sym_base_addr, sym_name); + switch (reloc_type) { + case R_ARM_NONE: + break; + case R_ARM_ABS32: - /* Add the addend stored at opaddr to opval */ - opval += *((uint32_t *)opaddr); + case R_ARM_TARGET1: + *(uint32_t *)loc += sym_base_addr; + break; + + case R_ARM_PC24: + case R_ARM_CALL: + case R_ARM_JUMP24: + ret = jumps_handler(reloc_type, loc, sym_base_addr, sym_name); + break; - /* Update the absolute address of a load/store instruction */ - *((uint32_t *)opaddr) = (uint32_t)opval; + case R_ARM_V4BX: + /* keep Rm and condition bits */ + *(uint32_t *)loc &= OPCODE2ARMMEM(MASK_V4BX_RM_COND); + /* remove the rest */ + *(uint32_t *)loc |= OPCODE2ARMMEM(MASK_V4BX_NOT_RM_COND); break; + + case R_ARM_PREL31: + ret = prel31_handler(reloc_type, loc, sym_base_addr, sym_name); + break; + + case R_ARM_REL32: + *(uint32_t *)loc += sym_base_addr - loc; + break; + + case R_ARM_MOVW_ABS_NC: + case R_ARM_MOVT_ABS: + case R_ARM_MOVW_PREL_NC: + case R_ARM_MOVT_PREL: + movs_handler(reloc_type, loc, sym_base_addr, sym_name); + break; + case R_ARM_THM_CALL: - /* Decode the initial addend */ - int32_t addend = arm_bl_blx_decode_addend(opaddr); + case R_ARM_THM_JUMP24: + ret = thm_jumps_handler(reloc_type, loc, sym_base_addr, sym_name); + break; - /* Calculate and add the branch offset (addend) */ - addend += ((int32_t)opval) - ((int32_t)opaddr); + case R_ARM_THM_MOVW_ABS_NC: + case R_ARM_THM_MOVT_ABS: + case R_ARM_THM_MOVW_PREL_NC: + case R_ARM_THM_MOVT_PREL: + thm_movs_handler(reloc_type, loc, sym_base_addr, sym_name); + break; - /* Encode the addend */ - arm_bl_blx_encode_addend(opaddr, addend); + case R_ARM_RELATIVE: + *(uint32_t *)loc += load_bias; break; - default: - LOG_DBG("Unsupported ARM elf relocation type %d at address %lx", - reloc_type, opaddr); + + case R_ARM_GLOB_DAT: + case R_ARM_JUMP_SLOT: + *(uint32_t *)loc = sym_base_addr; break; + + default: + LOG_ERR("unknown relocation: %u\n", reloc_type); + ret = -ENOEXEC; } + + return ret; } diff --git a/include/zephyr/llext/elf.h b/include/zephyr/llext/elf.h index 53445bfb6bd..edf83cae271 100644 --- a/include/zephyr/llext/elf.h +++ b/include/zephyr/llext/elf.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 Intel Corporation + * Copyright (c) 2024 Schneider Electric * * SPDX-License-Identifier: Apache-2.0 * @@ -370,10 +371,29 @@ struct elf64_rela { #define R_ARM_PC24 1 #define R_ARM_ABS32 2 #define R_ARM_REL32 3 -#define R_ARM_COPY 4 -#define R_ARM_THM_CALL 10 +#define R_ARM_COPY 20 +#define R_ARM_GLOB_DAT 21 +#define R_ARM_JUMP_SLOT 22 +#define R_ARM_RELATIVE 23 #define R_ARM_CALL 28 +#define R_ARM_JUMP24 29 +#define R_ARM_TARGET1 38 #define R_ARM_V4BX 40 +#define R_ARM_PREL31 42 +#define R_ARM_MOVW_ABS_NC 43 +#define R_ARM_MOVT_ABS 44 +#define R_ARM_MOVW_PREL_NC 45 +#define R_ARM_MOVT_PREL 46 +#define R_ARM_ALU_PC_G0_NC 57 +#define R_ARM_ALU_PC_G1_NC 59 +#define R_ARM_LDR_PC_G2 63 + +#define R_ARM_THM_CALL 10 +#define R_ARM_THM_JUMP24 30 +#define R_ARM_THM_MOVW_ABS_NC 47 +#define R_ARM_THM_MOVT_ABS 48 +#define R_ARM_THM_MOVW_PREL_NC 49 +#define R_ARM_THM_MOVT_PREL 50 #define R_XTENSA_NONE 0 #define R_XTENSA_32 1 diff --git a/include/zephyr/llext/llext.h b/include/zephyr/llext/llext.h index 754f0ea846d..99d780ee3b6 100644 --- a/include/zephyr/llext/llext.h +++ b/include/zephyr/llext/llext.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 Intel Corporation + * Copyright (c) 2024 Schneider Electric * * SPDX-License-Identifier: Apache-2.0 */ @@ -202,11 +203,15 @@ int llext_add_domain(struct llext *ext, struct k_mem_domain *domain); * or object. * * @param[in] rel Relocation data provided by elf - * @param[in] opaddr Address of operation to rewrite with relocation - * @param[in] opval Value of looked up symbol to relocate + * @param[in] loc Address of operation to rewrite with relocation + * @param[in] sym_base_addr Symbol address + * @param[in] sym_name Symbol name + * @param[in] load_bias .text load address + * @retval 0 success + * @retval -ENOEXEC invalid relocation */ -void arch_elf_relocate(elf_rela_t *rel, uintptr_t opaddr, uintptr_t opval); - +int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, + uintptr_t sym_base_addr, const char *sym_name, uintptr_t load_bias); /** * @brief Find an ELF section * diff --git a/subsys/llext/llext.c b/subsys/llext/llext.c index 08d3719778a..8222de55028 100644 --- a/subsys/llext/llext.c +++ b/subsys/llext/llext.c @@ -714,8 +714,10 @@ static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, } } -__weak void arch_elf_relocate(elf_rela_t *rel, uintptr_t opaddr, uintptr_t opval) +__weak int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, + uintptr_t sym_base_addr, const char *sym_name, uintptr_t load_bias) { + return -EOPNOTSUPP; } static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local) @@ -773,6 +775,9 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local if (tgt) llext_link_plt(ldr, ext, &shdr, do_local, tgt); continue; + } else if (strcmp(name, ".rel.dyn") == 0) { + /* we assume that first load segment starts at MEM_TEXT */ + loc = (uintptr_t)ext->mem[LLEXT_MEM_TEXT]; } LOG_DBG("relocation section %s (%d) linked to section %d has %zd relocations", @@ -815,8 +820,11 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local op_loc = loc + rel.r_offset; - /* If symbol is undefined, then we need to look it up */ - if (sym.st_shndx == SHN_UNDEF) { + if (ELF_R_SYM(rel.r_info) == 0) { + /* no symbol ex: R_ARM_V4BX relocation, R_ARM_RELATIVE */ + link_addr = 0; + } else if (sym.st_shndx == SHN_UNDEF) { + /* If symbol is undefined, then we need to look it up */ link_addr = (uintptr_t)llext_find_sym(NULL, name); if (link_addr == 0) { @@ -824,6 +832,8 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local "symbol table %s, offset %zd, link section %d", name, (size_t)rel.r_offset, shdr.sh_link); return -ENODATA; + } else { + LOG_INF("found symbol %s at 0x%lx", name, link_addr); } } else if (ELF_ST_TYPE(sym.st_info) == STT_SECTION || ELF_ST_TYPE(sym.st_info) == STT_FUNC || @@ -839,18 +849,17 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local continue; } - LOG_INF("relocating (linking) symbol %s type %d binding %d ndx %d offset " - "%zd link section %d", - name, ELF_ST_TYPE(sym.st_info), ELF_ST_BIND(sym.st_info), - sym.st_shndx, (size_t)rel.r_offset, shdr.sh_link); - LOG_INF("writing relocation symbol %s type %zd sym %zd at addr 0x%lx " "addr 0x%lx", name, (size_t)ELF_R_TYPE(rel.r_info), (size_t)ELF_R_SYM(rel.r_info), op_loc, link_addr); /* relocation */ - arch_elf_relocate(&rel, op_loc, link_addr); + ret = arch_elf_relocate(&rel, op_loc, link_addr, name, + (uintptr_t)ext->mem[LLEXT_MEM_TEXT]); + if (ret != 0) { + return ret; + } } } From b573f447f04f042f427fafd23fb8cd4cacfe6e30 Mon Sep 17 00:00:00 2001 From: Cedric Lescop Date: Wed, 10 Apr 2024 11:07:07 +0200 Subject: [PATCH 2136/2402] llext: add movt/movw relocation test Arch arm relocatate test covers: R_ARM_ABS32: all tests decode_thm_jumps -> relative jmp extension decode_thm_movs -> movwmovt extension Signed-off-by: Cedric Lescop --- tests/subsys/llext/simple/CMakeLists.txt | 48 ++++++++++++-------- tests/subsys/llext/simple/src/movwmovt_ext.c | 31 +++++++++++++ 2 files changed, 59 insertions(+), 20 deletions(-) create mode 100644 tests/subsys/llext/simple/src/movwmovt_ext.c diff --git a/tests/subsys/llext/simple/CMakeLists.txt b/tests/subsys/llext/simple/CMakeLists.txt index 5eae7b846fd..2bea2e9b7bf 100644 --- a/tests/subsys/llext/simple/CMakeLists.txt +++ b/tests/subsys/llext/simple/CMakeLists.txt @@ -16,25 +16,33 @@ target_include_directories(app PRIVATE ) if(NOT LOADER_BUILD_ONLY) -# generate extension targets foreach extension given by name -foreach(ext_name hello_world logging relative_jump object syscalls threads_kernel_objects) - set(ext_src ${PROJECT_SOURCE_DIR}/src/${ext_name}_ext.c) - set(ext_bin ${ZEPHYR_BINARY_DIR}/${ext_name}.llext) - set(ext_inc ${ZEPHYR_BINARY_DIR}/include/generated/${ext_name}.inc) - add_llext_target(${ext_name}_ext - OUTPUT ${ext_bin} - SOURCES ${ext_src} - ) - generate_inc_file_for_target(app ${ext_bin} ${ext_inc}) -endforeach() + set(ext_names hello_world logging relative_jump object syscalls threads_kernel_objects) -# Add a dummy custom processing command to test add_llext_command -get_target_property(proc_in_file hello_world_ext lib_output) -get_target_property(proc_out_file hello_world_ext pkg_input) -add_llext_command( - TARGET hello_world_ext - POST_BUILD - COMMAND echo "dummy patching ${proc_in_file} to create ${proc_out_file}" - COMMAND ${CMAKE_COMMAND} -E copy ${proc_in_file} ${proc_out_file} -) + if(CONFIG_ARM) + if(NOT CONFIG_CPU_CORTEX_M0 AND NOT CONFIG_CPU_CORTEX_M0PLUS AND NOT CONFIG_CPU_CORTEX_M1) + list(APPEND ext_names movwmovt) + endif() + endif() + + # generate extension targets foreach extension given by 'ext_names' + foreach(ext_name ${ext_names}) + set(ext_src ${PROJECT_SOURCE_DIR}/src/${ext_name}_ext.c) + set(ext_bin ${ZEPHYR_BINARY_DIR}/${ext_name}.llext) + set(ext_inc ${ZEPHYR_BINARY_DIR}/include/generated/${ext_name}.inc) + add_llext_target(${ext_name}_ext + OUTPUT ${ext_bin} + SOURCES ${ext_src} + ) + generate_inc_file_for_target(app ${ext_bin} ${ext_inc}) + endforeach() + + # Add a dummy custom processing command to test add_llext_command + get_target_property(proc_in_file hello_world_ext lib_output) + get_target_property(proc_out_file hello_world_ext pkg_input) + add_llext_command( + TARGET hello_world_ext + POST_BUILD + COMMAND echo "dummy patching ${proc_in_file} to create ${proc_out_file}" + COMMAND ${CMAKE_COMMAND} -E copy ${proc_in_file} ${proc_out_file} + ) endif() diff --git a/tests/subsys/llext/simple/src/movwmovt_ext.c b/tests/subsys/llext/simple/src/movwmovt_ext.c new file mode 100644 index 00000000000..5400385623a --- /dev/null +++ b/tests/subsys/llext/simple/src/movwmovt_ext.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024 Schneider Electric. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This test is designed to test MOV.W and MOV.T instructions on ARM architectures. + * (except Cortex-M0, M0+ and M1, that don't support them) + */ + +#include +#include +#include + + +static void test_func(void) +{ + printk("%s\n", __func__); +} + +void test_entry(void) +{ + test_func(); + + printk("test movwmovt\n"); + __asm volatile ("movw r0, #:lower16:test_func"); + __asm volatile ("movt r0, #:upper16:test_func"); + __asm volatile ("blx r0"); +} +LL_EXTENSION_SYMBOL(test_entry); From 8a63a0a563396092ad52d2d6c9d7d0b2edb4e742 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Wed, 10 Apr 2024 13:47:25 -0700 Subject: [PATCH 2137/2402] intel_adsp: ipc: Fix policy state lock usage IPC has inverted the usage of the state lock API. In this API semantics, the get method disallow the policy of using the given state, while the put() release this constraint. Signed-off-by: Flavio Ceolin --- soc/intel/intel_adsp/common/ipc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/soc/intel/intel_adsp/common/ipc.c b/soc/intel/intel_adsp/common/ipc.c index 987189ce1fe..a33c03ebfde 100644 --- a/soc/intel/intel_adsp/common/ipc.c +++ b/soc/intel/intel_adsp/common/ipc.c @@ -77,7 +77,7 @@ void z_intel_adsp_ipc_isr(const void *devarg) /* Allow the system to enter the runtime idle state after the IPC acknowledgment * is received. */ - pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); + pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); k_sem_give(&devdata->sem); /* IPC completion registers will be set externally */ @@ -160,7 +160,7 @@ int intel_adsp_ipc_send_message(const struct device *dev, k_sem_init(&devdata->sem, 0, 1); /* Prevent entering runtime idle state until IPC acknowledgment is received. */ - pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); + pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); devdata->tx_ack_pending = true; config->regs->idd = ext_data; config->regs->idr = data | INTEL_ADSP_IPC_BUSY; From dbc700125cfa289fbcf943ca8bc402bb6e758cca Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 10 Apr 2024 15:42:49 +0300 Subject: [PATCH 2138/2402] boards: nxp: imx8qm_mek: add `adsp` suffix to board defconfig Board name contains the `adsp` suffix and so should the defconfig. Otherwise, the build system won't be able to fetch the board configurations. Signed-off-by: Laurentiu Mihalcea --- ..._mek_mimx8qm6_defconfig => imx8qm_mek_mimx8qm6_adsp_defconfig} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename boards/nxp/imx8qm_mek/{imx8qm_mek_mimx8qm6_defconfig => imx8qm_mek_mimx8qm6_adsp_defconfig} (100%) diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp_defconfig similarity index 100% rename from boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig rename to boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp_defconfig From e13d1b47c65cf6361c7464da4813bd528a7ae465 Mon Sep 17 00:00:00 2001 From: Franciszek Pindel Date: Fri, 29 Mar 2024 13:46:53 +0100 Subject: [PATCH 2139/2402] fs: ext2: Fix calculating fs_memory in ext2_format First sector starts at CONFIG_EXT2_DISK_STARTING_SECTOR. This commit fixes calculating free space, based on that value. Signed-off-by: Franciszek Pindel --- subsys/fs/ext2/ext2_format.c | 2 ++ tests/subsys/fs/ext2/src/utils.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/subsys/fs/ext2/ext2_format.c b/subsys/fs/ext2/ext2_format.c index 9fb9792df75..f316e4d3d51 100644 --- a/subsys/fs/ext2/ext2_format.c +++ b/subsys/fs/ext2/ext2_format.c @@ -117,6 +117,8 @@ int ext2_format(struct ext2_data *fs, struct ext2_cfg *cfg) return -ENOSPC; } + /* Assume whole disk may be used minus CONFIG_EXT2_DISK_STARTING_SECTOR sectors. */ + fs_memory -= CONFIG_EXT2_DISK_STARTING_SECTOR * fs->write_size; uint32_t blocks_count = fs_memory / cfg->block_size; uint32_t blocks_per_group = cfg->block_size * 8; diff --git a/tests/subsys/fs/ext2/src/utils.c b/tests/subsys/fs/ext2/src/utils.c index 9a6afd89022..c7e6e942e29 100644 --- a/tests/subsys/fs/ext2/src/utils.c +++ b/tests/subsys/fs/ext2/src/utils.c @@ -72,5 +72,6 @@ size_t get_partition_size(uintptr_t id) sectors_info(name, §or_size, §or_count); - return sector_size * sector_count; + /* Assume that partition occupies sectors from CONFIG_EXT2_DISK_STARTING_SECTOR to last. */ + return sector_size * (sector_count - CONFIG_EXT2_DISK_STARTING_SECTOR); } From 3614d4cb88f4714c47af66d7053304092659fb43 Mon Sep 17 00:00:00 2001 From: Dmitrii Golovanov Date: Wed, 3 Apr 2024 17:58:17 +0200 Subject: [PATCH 2140/2402] gdbstub: doc: Update documentation with example Update the Zephyr `gdbstub` documentation with its 'how to use' example to align with former sample application replaced by the test. Fixes: zephyrproject-rtos#70966 Signed-off-by: Dmitrii Golovanov --- doc/services/debugging/gdbstub.rst | 201 +++++++++++++++-------------- 1 file changed, 102 insertions(+), 99 deletions(-) diff --git a/doc/services/debugging/gdbstub.rst b/doc/services/debugging/gdbstub.rst index c2062ec304d..67282749bb6 100644 --- a/doc/services/debugging/gdbstub.rst +++ b/doc/services/debugging/gdbstub.rst @@ -17,7 +17,7 @@ using GDB. The protocol supports different connection types: serial, UDP/IP and TCP/IP. Zephyr currently supports only serial device communication. -The GDB program acts as the client while Zephyr acts as the +The GDB program acts as a client while the Zephyr gdbstub acts as a server. When this feature is enabled, Zephyr stops its execution after :c:func:`gdb_init` starts gdbstub service and waits for a GDB connection. Once a connection is established it is possible to @@ -87,20 +87,39 @@ Using Serial Backend Example ******* -This is an example to demonstrate how GDB stub works. -You can also refer to ``tests/subsys/debug/gdbstub`` -for its implementation as a Twister test. +There is a test application :zephyr_file:`tests/subsys/debug/gdbstub` with one of its +test cases ``debug.gdbstub.breakpoints`` demonstrating how the Zephyr GDB stub can be used. +The test also has a case to connect to the QEMU's GDB stub implementation (at a custom +port ``tcp:1235``) as a reference to validate the test script itself. + +Run the test with the following command from your :envvar:`ZEPHYR_BASE` directory: + + .. code-block:: console + + ./scripts/twister -p qemu_x86 -T tests/subsys/debug/gdbstub + +The test should run successfully, and now let's do something similar step-by-step +to demonstrate how the Zephyr GDB stub works from the GDB user's perspective. + +In the snippets below use and expect your appropriate directories instead of +````, ````, ````. + #. Open two terminal windows. -#. On the first terminal, build and run the sample: +#. On the first terminal, build and run the test application: .. zephyr-app-commands:: - :zephyr-app: samples/subsys/debug/gdbstub + :zephyr-app: tests/subsys/debug/gdbstub :host-os: unix :board: qemu_x86 + :gen-args: '-DCONFIG_QEMU_EXTRA_FLAGS="-serial tcp:localhost:5678,server"' :goals: build run + Note how we set :kconfig:option:`CONFIG_QEMU_EXTRA_FLAGS` to direct QEMU serial + console port to the ``localhost`` TCP port ``5678`` to wait for a connection + from the GDB ``remote`` command we are going to do on the next steps. + #. On the second terminal, start GDB: .. code-block:: bash @@ -111,7 +130,7 @@ for its implementation as a Twister test. .. code-block:: text - (gdb) file /zephyr/zephyr.elf + (gdb) symbol-file /zephyr/zephyr.elf Response from GDB: @@ -119,38 +138,38 @@ for its implementation as a Twister test. Reading symbols from /zephyr/zephyr.elf... - #. Tell GDB to connect to the server: + #. Tell GDB to connect to the Zephyr gdbstub serial backend which is exposed + earlier as a server through the TCP port ``-serial`` redirection at QEMU. .. code-block:: text (gdb) target remote localhost:5678 - Note that QEMU is setup to redirect the serial used for GDB stub in - the Zephyr image to a networking port. Hence the connection to - localhost, port 5678. - Response from GDB: .. code-block:: text - Remote debugging using :5678 - arch_gdb_init () at /arch/x86/core/ia32/gdbstub.c:232 - 232 } + Remote debugging using localhost:5678 + arch_gdb_init () at /arch/x86/core/ia32/gdbstub.c:252 + 252 } GDB also shows where the code execution is stopped. In this case, - it is at :file:`arch/x86/core/ia32/gdbstub.c`, line 232. + it is at :zephyr_file:`arch/x86/core/ia32/gdbstub.c`, line 252. #. Use command ``bt`` or ``backtrace`` to show the backtrace of stack frames. .. code-block:: text (gdb) bt - #0 arch_gdb_init () at /arch/x86/core/ia32/gdbstub.c:232 - #1 0x00105068 in gdb_init (arg=0x0) at /subsys/debug/gdbstub.c:833 - #2 0x00109d6f in z_sys_init_run_level (level=0x1) at /kernel/device.c:72 - #3 0x0010a40b in z_cstart () at /kernel/init.c:423 - #4 0x00105383 in z_prep_c (arg=0x9500) at /arch/x86/core/prep_c.c:58 - #5 0x001000a9 in __csSet () at /arch/x86/core/ia32/crt0.S:273 + #0 arch_gdb_init () at /arch/x86/core/ia32/gdbstub.c:252 + #1 0x00104140 in gdb_init () at /zephyr/subsys/debug/gdbstub.c:852 + #2 0x00109c13 in z_sys_init_run_level (level=INIT_LEVEL_PRE_KERNEL_2) at /kernel/init.c:360 + #3 0x00109e73 in z_cstart () at /kernel/init.c:630 + #4 0x00104422 in z_prep_c (arg=0x1245bc ) at /arch/x86/core/prep_c.c:80 + #5 0x001000c9 in __csSet () at /arch/x86/core/ia32/crt0.S:290 + #6 0x001245bc in uart_dev () + #7 0x00134988 in z_interrupt_stacks () + #8 0x00000000 in ?? () #. Use command ``list`` to show the source code and surroundings where code execution is stopped. @@ -158,16 +177,16 @@ for its implementation as a Twister test. .. code-block:: text (gdb) list - 227 } - 228 - 229 void arch_gdb_init(void) - 230 { - 231 __asm__ volatile ("int3"); - 232 } - 233 - 234 /* Hook current IDT. */ - 235 _EXCEPTION_CONNECT_NOCODE(z_gdb_debug_isr, IV_DEBUG, 3); - 236 _EXCEPTION_CONNECT_NOCODE(z_gdb_break_isr, IV_BREAKPOINT, 3); + 247 __asm__ volatile ("int3"); + 248 + 249 #ifdef CONFIG_GDBSTUB_TRACE + 250 printk("gdbstub:%s GDB is connected\n", __func__); + 251 #endif + 252 } + 253 + 254 /* Hook current IDT. */ + 255 _EXCEPTION_CONNECT_NOCODE(z_gdb_debug_isr, IV_DEBUG, 3); + 256 _EXCEPTION_CONNECT_NOCODE(z_gdb_break_isr, IV_BREAKPOINT, 3); #. Use command ``s`` or ``step`` to step through program until it reaches a different source line. Now that it finished executing :c:func:`arch_gdb_init` @@ -176,31 +195,34 @@ for its implementation as a Twister test. .. code-block:: text (gdb) s - gdb_init (arg=0x0) at /home/dleung5/zephyr/rtos/zephyr/subsys/debug/gdbstub.c:834 - 834 return 0; + gdb_init () at /subsys/debug/gdbstub.c:857 + 857 return 0; .. code-block:: text (gdb) list - 829 LOG_ERR("Could not initialize gdbstub backend."); - 830 return -1; - 831 } - 832 - 833 arch_gdb_init(); - 834 return 0; - 835 } - 836 - 837 #ifdef CONFIG_XTENSA - 838 /* - - #. Use command ``br`` or ``break`` to setup a breakpoint. This example - sets up a breakpoint at :c:func:`main`, and let code execution continue + 852 arch_gdb_init(); + 853 + 854 #ifdef CONFIG_GDBSTUB_TRACE + 855 printk("gdbstub:%s exit\n", __func__); + 856 #endif + 857 return 0; + 858 } + 859 + 860 #ifdef CONFIG_XTENSA + 861 /* + + #. Use command ``br`` or ``break`` to setup a breakpoint. For this example + set up a breakpoint at :c:func:`main`, and let code execution continue without any intervention using command ``c`` (or ``continue``). .. code-block:: text (gdb) break main - Breakpoint 1 at 0x1005a9: file /samples/subsys/debug/gdbstub/src/main.c, line 32. + Breakpoint 1 at 0x10064d: file /tests/subsys/debug/gdbstub/src/main.c, line 27. + + .. code-block:: text + (gdb) continue Continuing. @@ -209,24 +231,24 @@ for its implementation as a Twister test. .. code-block:: text - Breakpoint 1, main () at /samples/subsys/debug/gdbstub/src/main.c:32 - 32 ret = test(); + Breakpoint 1, main () at /tests/subsys/debug/gdbstub/src/main.c:27 + 27 printk("%s():enter\n", __func__); Now GDB is waiting at the beginning of :c:func:`main`: .. code-block:: text (gdb) list - 27 - 28 int main(void) - 29 { - 30 int ret; - 31 - 32 ret = test(); - 33 printk("%d\n", ret); - 34 } - 35 - 36 K_THREAD_DEFINE(thread, STACKSIZE, thread_entry, NULL, NULL, NULL, + 22 + 23 int main(void) + 24 { + 25 int ret; + 26 + 27 printk("%s():enter\n", __func__); + 28 ret = test(); + 29 printk("ret=%d\n", ret); + 30 return 0; + 31 } #. To examine the value of ``ret``, the command ``p`` or ``print`` can be used. @@ -234,48 +256,26 @@ for its implementation as a Twister test. .. code-block:: text (gdb) p ret - $1 = 0x11318c + $1 = 1273788 - Since ``ret`` has not been assigned a value yet, what it contains is - simply a random value. + Since ``ret`` has not been initialized, it contains some random value. #. If step (``s`` or ``step``) is used here, it will continue execution - until :c:func:`printk` is reached, thus skipping the interior of - :c:func:`test`. To examine code execution inside :c:func:`test`, + skipping the interior of :c:func:`test`. + To examine code execution inside :c:func:`test`, a breakpoint can be set for :c:func:`test`, or simply using ``si`` (or ``stepi``) to execute one machine instruction, where it has - the side effect of going into the function. - - .. code-block:: text - - (gdb) si - test () at /samples/subsys/debug/gdbstub/src/main.c:13 - 13 { - (gdb) list - 8 #include - 9 - 10 #define STACKSIZE 512 - 11 - 12 static int test(void) - 13 { - 14 int a; - 15 int b; - 16 - 17 a = 10; - - #. Here, ``step`` can be used to go through all code inside :c:func:`test` - until it returns. Or the command ``finish`` can be used to continue - execution without intervention until the function returns. + the side effect of going into the function. The GDB command ``finish`` + can be used to continue execution without intervention until the function + returns. .. code-block:: text (gdb) finish - Run till exit from #0 test () at /samples/subsys/debug/gdbstub/src/main.c:13 - 0x001005ae in main () at /samples/subsys/debug/gdbstub/src/main.c:32 - 32 ret = test(); - Value returned is $2 = 0x1e - - And now, execution is back to :c:func:`main`. + Run till exit from #0 test () at /tests/subsys/debug/gdbstub/src/main.c:17 + 0x00100667 in main () at /tests/subsys/debug/gdbstub/src/main.c:28 + 28 ret = test(); + Value returned is $2 = 30 #. Examine ``ret`` again which should have the return value from :c:func:`test`. Sometimes, the assignment is not done until another @@ -287,13 +287,16 @@ for its implementation as a Twister test. .. code-block:: text (gdb) p ret - $3 = 0x11318c - (gdb) s - 33 printk("%d\n", ret); + $3 = 1273788 + (gdb) step + 29 printk("ret=%d\n", ret); (gdb) p ret - $4 = 0x1e + $4 = 30 #. If ``continue`` is issued here, code execution will continue indefinitely as there are no breakpoints to further stop execution. Breaking execution - in GDB via Ctrl-C does not currently work as the GDB stub does not - support this functionality (yet). + in GDB via :kbd:`Ctrl-C` does not currently work as the Zephyr gdbstub does + not support this functionality yet. Switch to the first console with QEMU + running the Zephyr image and stop it manually with :kbd:`Ctrl+a x`. + When the same test is executed by Twister, it automatically takes care of + stopping the QEMU instance. From 87779e73f87739afdeb2b595b397b831f5fc3518 Mon Sep 17 00:00:00 2001 From: Aleksander Wasaznik Date: Tue, 2 Apr 2024 15:06:09 +0200 Subject: [PATCH 2141/2402] toolchain: gcc: Simplify `GEN_ABSOLUTE_SYM` and `GEN_ABSOLUTE_SYM_KCONFIG` The assembler code in these macros can be expressed using target-independent language constructs. This change unifies the variants from using a target-specific dialects to a target-agnostic solution. This fixes building Zephyr for target AArch32, by using target-agnostic `STT_OBJECT`. Signed-off-by: Aleksander Wasaznik --- include/zephyr/toolchain/gcc.h | 123 ++++++++++++--------------------- 1 file changed, 45 insertions(+), 78 deletions(-) diff --git a/include/zephyr/toolchain/gcc.h b/include/zephyr/toolchain/gcc.h index 646deea04f5..767dc10f742 100644 --- a/include/zephyr/toolchain/gcc.h +++ b/include/zephyr/toolchain/gcc.h @@ -489,85 +489,52 @@ do { \ * to generate named symbol/value pairs for kconfigs. */ -#if defined(CONFIG_ARM) - -/* - * GNU/ARM backend does not have a proper operand modifier which does not - * produces prefix # followed by value, such as %0 for PowerPC, Intel, and - * MIPS. The workaround performed here is using %B0 which converts - * the value to ~(value). Thus "n"(~(value)) is set in operand constraint - * to output (value) in the ARM specific GEN_OFFSET macro. +#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_ARC) || defined(CONFIG_ARM64) || \ + defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) || defined(CONFIG_MIPS) || \ + defined(CONFIG_ARCH_POSIX) || defined(CONFIG_SPARC) + +#define GEN_ABSOLUTE_SYM(name, value) \ + do { \ + __asm__(".global " #name); \ + __asm__(".set " #name ", %c0" ::"n"(value)); \ + __asm__(".type " #name ", STT_OBJECT"); \ + } while (false) + +#define GEN_ABSOLUTE_SYM_KCONFIG(name, value) \ + do { \ + __asm__(".global " #name); \ + __asm__(".set " #name ", " #value); \ + __asm__(".type " #name ", STT_OBJECT"); \ + } while (false) + +/* The following is a workaround for the RISC-V target, which + * has a bug so it errors out on the target-agnostic '%c'. + * + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112434 + * + * > error: invalid 'asm': invalid use of '%c' + * + * According to commit cd83e85edc5d741f6b52c6b5995303c30bda443a, + * '%0' is equivalent to '%c0' for the RISC-V target. We use + * this as a workaround for now. + * + * This workaround should be removed when the above bug is fixed + * in all supported Zephyr toolchain versions. */ - -#define GEN_ABSOLUTE_SYM(name, value) \ - __asm__(".globl\t" #name "\n\t.equ\t" #name \ - ",%B0" \ - "\n\t.type\t" #name ",%%object" : : "n"(~(value))) - -#define GEN_ABSOLUTE_SYM_KCONFIG(name, value) \ - __asm__(".globl\t" #name \ - "\n\t.equ\t" #name "," #value \ - "\n\t.type\t" #name ",%object") - -#elif defined(CONFIG_X86) - -#define GEN_ABSOLUTE_SYM(name, value) \ - __asm__(".globl\t" #name "\n\t.equ\t" #name \ - ",%c0" \ - "\n\t.type\t" #name ",@object" : : "n"(value)) - -#define GEN_ABSOLUTE_SYM_KCONFIG(name, value) \ - __asm__(".globl\t" #name \ - "\n\t.equ\t" #name "," #value \ - "\n\t.type\t" #name ",@object") - -#elif defined(CONFIG_ARC) || defined(CONFIG_ARM64) - -#define GEN_ABSOLUTE_SYM(name, value) \ - __asm__(".globl\t" #name "\n\t.equ\t" #name \ - ",%c0" \ - "\n\t.type\t" #name ",@object" : : "n"(value)) - -#define GEN_ABSOLUTE_SYM_KCONFIG(name, value) \ - __asm__(".globl\t" #name \ - "\n\t.equ\t" #name "," #value \ - "\n\t.type\t" #name ",@object") - -#elif defined(CONFIG_NIOS2) || defined(CONFIG_RISCV) || \ - defined(CONFIG_XTENSA) || defined(CONFIG_MIPS) - -/* No special prefixes necessary for constants in this arch AFAICT */ -#define GEN_ABSOLUTE_SYM(name, value) \ - __asm__(".globl\t" #name "\n\t.equ\t" #name \ - ",%0" \ - "\n\t.type\t" #name ",%%object" : : "n"(value)) - -#define GEN_ABSOLUTE_SYM_KCONFIG(name, value) \ - __asm__(".globl\t" #name \ - "\n\t.equ\t" #name "," #value \ - "\n\t.type\t" #name ",%object") - -#elif defined(CONFIG_ARCH_POSIX) -#define GEN_ABSOLUTE_SYM(name, value) \ - __asm__(".globl\t" #name "\n\t.equ\t" #name \ - ",%c0" \ - "\n\t.type\t" #name ",@object" : : "n"(value)) - -#define GEN_ABSOLUTE_SYM_KCONFIG(name, value) \ - __asm__(".globl\t" #name \ - "\n\t.equ\t" #name "," #value \ - "\n\t.type\t" #name ",@object") - -#elif defined(CONFIG_SPARC) -#define GEN_ABSOLUTE_SYM(name, value) \ - __asm__(".global\t" #name "\n\t.equ\t" #name \ - ",%0" \ - "\n\t.type\t" #name ",#object" : : "n"(value)) - -#define GEN_ABSOLUTE_SYM_KCONFIG(name, value) \ - __asm__(".globl\t" #name \ - "\n\t.equ\t" #name "," #value \ - "\n\t.type\t" #name ",#object") +#elif defined(CONFIG_RISCV) +#define GEN_ABSOLUTE_SYM(name, value) \ + do { \ + __asm__(".global " #name); \ + __asm__(".set " #name ", %0" ::"n"(value)); \ + __asm__(".type " #name ", STT_OBJECT"); \ + } while (false) + +#define GEN_ABSOLUTE_SYM_KCONFIG(name, value) \ + do { \ + __asm__(".global " #name); \ + __asm__(".set " #name ", " #value); \ + __asm__(".type " #name ", STT_OBJECT"); \ + } while (false) #else #error processor architecture not supported From 503a3d78d2c5ea35dbc761bb160ad05423204d4c Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Fri, 22 Mar 2024 14:48:50 +0100 Subject: [PATCH 2142/2402] samples: subsys: nvs fix hard fault when running on stm32 targets on stm32f091 and stm32g071 nucleo boards This avoids HARD Fault when reaching the last reboot Disable the external flash memory of the b_u585i_iot02 target to end the test properly Signed-off-by: Francois Ramu --- samples/subsys/nvs/boards/b_u585i_iot02a.overlay | 9 +++++++++ samples/subsys/nvs/boards/nucleo_f091rc.conf | 1 + samples/subsys/nvs/boards/nucleo_g071rb.conf | 1 + 3 files changed, 11 insertions(+) create mode 100644 samples/subsys/nvs/boards/b_u585i_iot02a.overlay create mode 100644 samples/subsys/nvs/boards/nucleo_f091rc.conf create mode 100644 samples/subsys/nvs/boards/nucleo_g071rb.conf diff --git a/samples/subsys/nvs/boards/b_u585i_iot02a.overlay b/samples/subsys/nvs/boards/b_u585i_iot02a.overlay new file mode 100644 index 00000000000..140a387a8c6 --- /dev/null +++ b/samples/subsys/nvs/boards/b_u585i_iot02a.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&mx25lm51245 { + status = "disabled"; +}; diff --git a/samples/subsys/nvs/boards/nucleo_f091rc.conf b/samples/subsys/nvs/boards/nucleo_f091rc.conf new file mode 100644 index 00000000000..d862c64353b --- /dev/null +++ b/samples/subsys/nvs/boards/nucleo_f091rc.conf @@ -0,0 +1 @@ +CONFIG_MAIN_STACK_SIZE=2048 diff --git a/samples/subsys/nvs/boards/nucleo_g071rb.conf b/samples/subsys/nvs/boards/nucleo_g071rb.conf new file mode 100644 index 00000000000..d862c64353b --- /dev/null +++ b/samples/subsys/nvs/boards/nucleo_g071rb.conf @@ -0,0 +1 @@ +CONFIG_MAIN_STACK_SIZE=2048 From 821ae1574460791c953ca38aae62443ba76b8330 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 22 Mar 2024 17:36:19 +0000 Subject: [PATCH 2143/2402] dts: arm: nxp_rw6xx: add USBOTG devicetree node Add devicetree node for USBOTG device, the EHCI based USB controller on the RW6XX. Signed-off-by: Daniel DeGrasse --- dts/arm/nxp/nxp_rw6xx_common.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index 0a1b8c53587..d78879e107a 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -108,6 +108,15 @@ int-source = "pint"; }; + usb_otg: usbotg@145000 { + compatible = "nxp,ehci"; + reg = <0x145000 0x200>; + interrupts = <50 1>; + interrupt-names = "usb_otg"; + num-bidir-endpoints = <8>; + status = "disabled"; + }; + flexcomm0: flexcomm@106000 { compatible = "nxp,lpc-flexcomm"; reg = <0x106000 0x1000>; From 46bed8896e1b24f84bd159f1ea9b31b7ba87f28f Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 22 Mar 2024 17:37:10 +0000 Subject: [PATCH 2144/2402] soc: nxp: rw: add support for USBOTG controller Add code to clock and release reset signal for USBOTG controller on RW6xx SOC when USB is enabled, and add KConfig selection to indicate to build system which USB controller this SOC uses. Signed-off-by: Daniel DeGrasse --- soc/nxp/rw/Kconfig.defconfig | 4 ++++ soc/nxp/rw/soc.c | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/soc/nxp/rw/Kconfig.defconfig b/soc/nxp/rw/Kconfig.defconfig index 85f6cd5e825..38bb0df74b7 100644 --- a/soc/nxp/rw/Kconfig.defconfig +++ b/soc/nxp/rw/Kconfig.defconfig @@ -69,4 +69,8 @@ config CODE_DATA_RELOCATION_SRAM endif # FLASH_MCUX_FLEXSPI_XIP +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_EHCI +endchoice + endif # SOC_SERIES_RW6XX diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c index c372f32a425..f1571010bdd 100644 --- a/soc/nxp/rw/soc.c +++ b/soc/nxp/rw/soc.c @@ -243,6 +243,17 @@ __ramfunc void clock_init(void) RESET_PeripheralReset(kFREEMRT_RST_SHIFT_RSTn); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb_otg), okay) && CONFIG_USB_DC_NXP_EHCI + /* Enable system xtal from Analog */ + SYSCTL2->ANA_GRP_CTRL |= SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK; + /* reset USB */ + RESET_PeripheralReset(kUSB_RST_SHIFT_RSTn); + /* enable usb clock */ + CLOCK_EnableClock(kCLOCK_Usb); + /* enable usb phy clock */ + CLOCK_EnableUsbhsPhyClock(); +#endif + } /** From 6294f4b5415b48a83c6f95e2c4b204844bb79e82 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 22 Mar 2024 17:38:07 +0000 Subject: [PATCH 2145/2402] drivers: usb: usb_dc_mcux: add case for RW6xx SOC series Add case for RW6xx SOC series to indicate which device controller is in use. Signed-off-by: Daniel DeGrasse --- drivers/usb/device/usb_dc_mcux.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/device/usb_dc_mcux.c b/drivers/usb/device/usb_dc_mcux.c index a4e979d206b..e36eba89182 100644 --- a/drivers/usb/device/usb_dc_mcux.c +++ b/drivers/usb/device/usb_dc_mcux.c @@ -95,6 +95,8 @@ BUILD_ASSERT(NUM_INSTS <= 1, "Only one USB device supported"); #elif DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) #define CONTROLLER_ID kUSB_ControllerEhci1 #endif /* IMX RT */ +#elif defined(CONFIG_SOC_SERIES_RW6XX) +#define CONTROLLER_ID kUSB_ControllerEhci0 #else /* If SOC has EHCI or LPCIP3511 then probably just need to add controller ID to this code */ #error "USB driver does not yet support this SOC" From a70ba00fd3a481efa034d7a194c7b0fb93298026 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 22 Mar 2024 17:39:59 +0000 Subject: [PATCH 2146/2402] boards: nxp: rd_rw612_bga add support for USBOTG Add support for USBOTG on RW612 BGA board. This support was tested with the USB console sample, as well as the USB DFU sample. Signed-off-by: Daniel DeGrasse --- boards/nxp/rd_rw612_bga/doc/index.rst | 2 ++ boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 4 ++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml | 1 + 3 files changed, 7 insertions(+) diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index 8e6202422c0..c31df4ab448 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -55,6 +55,8 @@ Supported Features +-----------+------------+-----------------------------------+ | WWDT | on-chip | watchdog | +-----------+------------+-----------------------------------+ +| USBOTG | on-chip | usb | ++-----------+------------+-----------------------------------+ | CTIMER | on-chip | counter | +-----------+------------+-----------------------------------+ | MRT | on-chip | counter | diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index b82f4bb7153..a9f52c885e3 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -199,6 +199,10 @@ arduino_i2c: &flexcomm2 { dc-gain = <1>; }; +zephyr_udc0: &usb_otg { + status = "okay"; +}; + &dma0 { status = "okay"; }; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml index 0457f38a79c..db7445f1c95 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -21,6 +21,7 @@ supported: - spi - i2c - entropy + - usb_device - watchdog - counter - hwinfo From ba90f160b9865530e6b8d66bbc23d024849a7c9c Mon Sep 17 00:00:00 2001 From: Jan Kubiznak Date: Tue, 12 Mar 2024 17:29:42 +0100 Subject: [PATCH 2147/2402] drivers: adc: adc_ads1119: Fix configuration register access. The adc_ads1119 driver is unable to overwrite the configuration register, the chip therefore always works with its default settings. Register access macros are fixed by this commit. Fixes: #70091 Signed-off-by: Jan Kubiznak --- drivers/adc/adc_ads1119.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/adc/adc_ads1119.c b/drivers/adc/adc_ads1119.c index 1abdcaad720..638b83fc2b2 100644 --- a/drivers/adc/adc_ads1119.c +++ b/drivers/adc/adc_ads1119.c @@ -21,11 +21,11 @@ LOG_MODULE_REGISTER(ADS1119, CONFIG_ADC_LOG_LEVEL); -#define ADS1119_CONFIG_VREF(x) ((x) & BIT(0)) -#define ADS1119_CONFIG_CM(x) ((x) & BIT(1)) -#define ADS1119_CONFIG_DR(x) ((x) & (BIT_MASK(2) << 2)) -#define ADS1119_CONFIG_GAIN(x) ((x) & BIT(4)) -#define ADS1119_CONFIG_MUX(x) ((x) & (BIT_MASK(3) << 5)) +#define ADS1119_CONFIG_VREF(x) (FIELD_PREP(BIT(0), x)) +#define ADS1119_CONFIG_CM(x) (FIELD_PREP(BIT(1), x)) +#define ADS1119_CONFIG_DR(x) (FIELD_PREP(BIT_MASK(2) << 2, x)) +#define ADS1119_CONFIG_GAIN(x) (FIELD_PREP(BIT(4), x)) +#define ADS1119_CONFIG_MUX(x) (FIELD_PREP(BIT_MASK(3) << 5, x)) #define ADS1119_STATUS_MASK_ID BIT_MASK(7) #define ADS1119_STATUS_MASK_READY BIT(7) From 75973852bfb0328957b2bf86cfbe67e1139ee2c0 Mon Sep 17 00:00:00 2001 From: Rubin Gerritsen Date: Tue, 9 Apr 2024 08:50:11 +0200 Subject: [PATCH 2148/2402] Bluetooth: Audio: Add iso_chan to bt_bap_ep_info By exposing the underlying iso channel, the application can retrieve properties of the iso channel. This can be useful in case the application wants to use the connection handle for vendor specific HCI commands or to retrieve the particular parameters used for the given channel. Signed-off-by: Rubin Gerritsen --- include/zephyr/bluetooth/audio/bap.h | 3 +++ subsys/bluetooth/audio/bap_stream.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/include/zephyr/bluetooth/audio/bap.h b/include/zephyr/bluetooth/audio/bap.h index fa5d20f00cf..08a2a642eb0 100644 --- a/include/zephyr/bluetooth/audio/bap.h +++ b/include/zephyr/bluetooth/audio/bap.h @@ -397,6 +397,9 @@ struct bt_bap_ep_info { /** Capabilities type */ enum bt_audio_dir dir; + /** The isochronous channel associated with the endpoint. */ + struct bt_iso_chan *iso_chan; + /** @brief True if the stream associated with the endpoint is able to send data */ bool can_send; diff --git a/subsys/bluetooth/audio/bap_stream.c b/subsys/bluetooth/audio/bap_stream.c index 29e058544e9..e3f044cacb6 100644 --- a/subsys/bluetooth/audio/bap_stream.c +++ b/subsys/bluetooth/audio/bap_stream.c @@ -121,8 +121,10 @@ int bt_bap_ep_get_info(const struct bt_bap_ep *ep, struct bt_bap_ep_info *info) if (ep->iso == NULL) { info->paired_ep = NULL; + info->iso_chan = NULL; } else { info->paired_ep = bt_bap_iso_get_paired_ep(ep); + info->iso_chan = &ep->iso->chan; } info->can_send = false; From 9b17a952f6df812fad42e124e2b70eea89c77ff5 Mon Sep 17 00:00:00 2001 From: Aditya Ganesh Date: Sat, 6 Apr 2024 11:25:06 +0530 Subject: [PATCH 2149/2402] drivers: can: can_stm32_bxcan.c: Failed to exit sleep mode Fixes the issue of CAN failing to exit sleep mode inside can_stm32_init() when a software reset is done. For stm32 the CAN is first made to enter initialization mode first and then made to exit the sleep mode. Signed-off-by: Aditya Ganesh --- drivers/can/can_stm32_bxcan.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/can/can_stm32_bxcan.c b/drivers/can/can_stm32_bxcan.c index 3f8060944e9..c89e1c3724e 100644 --- a/drivers/can/can_stm32_bxcan.c +++ b/drivers/can/can_stm32_bxcan.c @@ -632,15 +632,15 @@ static int can_stm32_init(const struct device *dev) return ret; } - ret = can_stm32_leave_sleep_mode(can); + ret = can_stm32_enter_init_mode(can); if (ret) { - LOG_ERR("Failed to exit sleep mode"); + LOG_ERR("Failed to enter init mode"); return ret; } - ret = can_stm32_enter_init_mode(can); + ret = can_stm32_leave_sleep_mode(can); if (ret) { - LOG_ERR("Failed to enter init mode"); + LOG_ERR("Failed to exit sleep mode"); return ret; } From abc1ea146b74aabdd075d158caac0aed5e42593a Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:05 +0200 Subject: [PATCH 2150/2402] Revert "[nrf fromlist] boards: nordic: Add PWM support for LEDs on nRF54 DKs" This reverts commit bdda11bdb687157e55b44e3053bb0966ecf75d4f. Signed-off-by: Gerard Marull-Paretas --- .../nrf54h20dk_nrf54h20-pinctrl.dtsi | 14 -------------- .../nrf54h20dk_nrf54h20_cpuapp.dts | 15 --------------- .../nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi | 13 ------------- .../nrf54l15pdk_nrf54l15_cpuapp.dts | 15 --------------- .../nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay | 15 --------------- 5 files changed, 72 deletions(-) diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-pinctrl.dtsi b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-pinctrl.dtsi index cc6b5e90beb..6c6da3fa747 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-pinctrl.dtsi +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-pinctrl.dtsi @@ -50,18 +50,4 @@ ; }; }; - - /omit-if-no-ref/ pwm120_default: pwm120_default { - group1 { - psels = ; - }; - }; - - /omit-if-no-ref/ pwm120_sleep: pwm120_sleep { - group1 { - psels = ; - low-power-enable; - }; - }; - }; diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts index aee17df9f8f..4b04ff8dcd4 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts @@ -31,7 +31,6 @@ led1 = &led1; led2 = &led2; led3 = &led3; - pwm-led0 = &pwm_led0; sw0 = &button0; sw1 = &button1; sw2 = &button2; @@ -90,13 +89,6 @@ }; }; - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm120 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - }; - prng: prng { compatible = "nordic,entropy-prng"; status = "okay"; @@ -201,10 +193,3 @@ ipc0: &cpuapp_cpurad_ipc { pinctrl-names = "default", "sleep"; hw-flow-control; }; - -&pwm120 { - status = "okay"; - pinctrl-0 = <&pwm120_default>; - pinctrl-1 = <&pwm120_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi index ac6cd2e4357..31c2f820f3f 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi @@ -64,17 +64,4 @@ low-power-enable; }; }; - - pwm20_default: pwm20_default { - group1 { - psels = ; - }; - }; - - pwm20_sleep: pwm20_sleep { - group1 { - psels = ; - low-power-enable; - }; - }; }; diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts index e5f808de44b..f64952ba886 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -43,13 +43,6 @@ }; }; - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - }; - buttons { compatible = "gpio-keys"; button0: button_0 { @@ -79,7 +72,6 @@ led1 = &led1; led2 = &led2; led3 = &led3; - pwm-led0 = &pwm_led0; watchdog0 = &wdt30; sw0 = &button0; sw1 = &button1; @@ -213,10 +205,3 @@ &adc { status = "okay"; }; - -&pwm20 { - status = "okay"; - pinctrl-0 = <&pwm20_default>; - pinctrl-1 = <&pwm20_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay index 99ba6ff3062..d8262dde994 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay @@ -36,18 +36,3 @@ &button3 { gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; }; - -&pinctrl { - /omit-if-no-ref/ pwm20_default: pwm20_default { - group1 { - psels = ; - }; - }; - - /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { - group1 { - psels = ; - low-power-enable; - }; - }; -}; From 29db402584a4ac325a894e9c054e9da494ec1151 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:05 +0200 Subject: [PATCH 2151/2402] Revert "[nrf fromtree] mcumgr/img_mgmt: Fix zcbor logic in os_mgmt_bootloader_info" This reverts commit 99187c89524710cba572477a2cc95ab8d309b563. Signed-off-by: Gerard Marull-Paretas --- subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c index 9fc02f81661..29e222d1de9 100644 --- a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c +++ b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c @@ -469,9 +469,9 @@ os_mgmt_bootloader_info(struct smp_streamer *ctxt) ok = zcbor_tstr_put_lit(zse, "mode") && zcbor_int32_put(zse, BOOTLOADER_MODE); -#ifdef CONFIG_MCUBOOT_BOOTLOADER_NO_DOWNGRADE - ok = ok && zcbor_tstr_put_lit(zse, "no-downgrade") && - zcbor_bool_encode(zse, &(bool){true}); +#if IS_ENABLED(CONFIG_MCUBOOT_BOOTLOADER_NO_DOWNGRADE) + ok = zcbor_tstr_put_lit(zse, "no-downgrade") && + zcbor_bool_encode(zse, true); #endif } else { return OS_MGMT_ERR_QUERY_YIELDS_NO_ANSWER; From 24611ecb035155b0c05e4e0dfd895a6e535066f7 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:06 +0200 Subject: [PATCH 2152/2402] Revert "[nrf fromtree] mcumgr/img_mgmt: Fix CONFIG_MCUBOOT_BOOTLOADER_NO_DOWNGRADE" This reverts commit 8b560b37f8421c0a68dc0bf3d352ce6a7c8016c5. Signed-off-by: Gerard Marull-Paretas --- subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c index 29e222d1de9..7de448ac78d 100644 --- a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c +++ b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c @@ -469,7 +469,7 @@ os_mgmt_bootloader_info(struct smp_streamer *ctxt) ok = zcbor_tstr_put_lit(zse, "mode") && zcbor_int32_put(zse, BOOTLOADER_MODE); -#if IS_ENABLED(CONFIG_MCUBOOT_BOOTLOADER_NO_DOWNGRADE) +#if IS_ENABLED(MCUBOOT_BOOTLOADER_NO_DOWNGRADE) ok = zcbor_tstr_put_lit(zse, "no-downgrade") && zcbor_bool_encode(zse, true); #endif From fe24fc440db509ab04bb150ee0044ff3b324a422 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:06 +0200 Subject: [PATCH 2153/2402] Revert "[nrf fromtree] tests: drivers: spi: Add negative test cases" This reverts commit 6c515dd5fc7c777e0105cf5bb66c51b036f8b6dd. Signed-off-by: Gerard Marull-Paretas --- .../spi/spi_error_cases/CMakeLists.txt | 10 - .../boards/nrf52840dk_nrf52840.overlay | 72 ----- .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 78 ------ tests/drivers/spi/spi_error_cases/prj.conf | 7 - tests/drivers/spi/spi_error_cases/src/main.c | 263 ------------------ .../drivers/spi/spi_error_cases/testcase.yaml | 12 - 6 files changed, 442 deletions(-) delete mode 100644 tests/drivers/spi/spi_error_cases/CMakeLists.txt delete mode 100644 tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay delete mode 100644 tests/drivers/spi/spi_error_cases/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay delete mode 100644 tests/drivers/spi/spi_error_cases/prj.conf delete mode 100644 tests/drivers/spi/spi_error_cases/src/main.c delete mode 100644 tests/drivers/spi/spi_error_cases/testcase.yaml diff --git a/tests/drivers/spi/spi_error_cases/CMakeLists.txt b/tests/drivers/spi/spi_error_cases/CMakeLists.txt deleted file mode 100644 index 2ac4bdbef4d..00000000000 --- a/tests/drivers/spi/spi_error_cases/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(spi_error_cases) - -FILE(GLOB app_sources src/*.c) - -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay b/tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay deleted file mode 100644 index 183d6da9967..00000000000 --- a/tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - spi3_default_alt: spi3_default_alt { - group1 { - psels = , - , - ; - }; - }; - - spi3_sleep_alt: spi3_sleep_alt { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; - - spi1_default_alt: spi1_default_alt { - group1 { - psels = , - , - , - ; - }; - }; - - spi1_sleep_alt: spi1_sleep_alt { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; - -}; - -dut_spi: &spi3 { - status = "okay"; - pinctrl-0 = <&spi3_default_alt>; - pinctrl-1 = <&spi3_sleep_alt>; - pinctrl-names = "default", "sleep"; - overrun-character = <0x00>; - cs-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - dut_spi_dt: test-spi-dev@0 { - compatible = "vnd,spi-device"; - reg = <0>; - spi-max-frequency = <200000>; - }; -}; - -dut_spis: &spi1 { - compatible = "nordic,nrf-spis"; - status = "okay"; - def-char = <0x00>; - pinctrl-0 = <&spi1_default_alt>; - pinctrl-1 = <&spi1_sleep_alt>; - pinctrl-names = "default", "sleep"; - dut_spis_dt: test-spis-dev@0 { - compatible = "vnd,spi-device"; - reg = <0>; - spi-max-frequency = <200000>; - }; -}; diff --git a/tests/drivers/spi/spi_error_cases/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_error_cases/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay deleted file mode 100644 index 2a0394c3f60..00000000000 --- a/tests/drivers/spi/spi_error_cases/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - spi22_default_alt: spi22_default_alt { - group1 { - psels = , - , - ; - }; - }; - - spi22_sleep_alt: spi22_sleep_alt { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; - - spi21_default_alt: spi21_default_alt { - group1 { - psels = , - , - , - ; - }; - }; - - spi21_sleep_alt: spi21_sleep_alt { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; - -}; - -&gpio2 { - status = "okay"; -}; - -dut_spi: &spi22 { - status = "okay"; - pinctrl-0 = <&spi22_default_alt>; - pinctrl-1 = <&spi22_sleep_alt>; - pinctrl-names = "default", "sleep"; - overrun-character = <0x00>; - cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - dut_spi_dt: test-spi-dev@0 { - compatible = "vnd,spi-device"; - reg = <0>; - spi-max-frequency = <200000>; - }; -}; - -dut_spis: &spi21 { - compatible = "nordic,nrf-spis"; - status = "okay"; - def-char = <0x00>; - pinctrl-0 = <&spi21_default_alt>; - pinctrl-1 = <&spi21_sleep_alt>; - pinctrl-names = "default", "sleep"; - dut_spis_dt: test-spis-dev@0 { - compatible = "vnd,spi-device"; - reg = <0>; - spi-max-frequency = <200000>; - }; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; -}; diff --git a/tests/drivers/spi/spi_error_cases/prj.conf b/tests/drivers/spi/spi_error_cases/prj.conf deleted file mode 100644 index 1161e03f477..00000000000 --- a/tests/drivers/spi/spi_error_cases/prj.conf +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_SPI=y -CONFIG_SPI_SLAVE=y -CONFIG_GPIO=y -CONFIG_POLL=y -CONFIG_SPI_ASYNC=y -CONFIG_SPI_EXTENDED_MODES=y -CONFIG_ZTEST=y diff --git a/tests/drivers/spi/spi_error_cases/src/main.c b/tests/drivers/spi/spi_error_cases/src/main.c deleted file mode 100644 index 0b44812db84..00000000000 --- a/tests/drivers/spi/spi_error_cases/src/main.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -#define SPI_MODE (SPI_MODE_CPOL | SPI_WORD_SET(8) | SPI_LINES_SINGLE) -#define SPIM_OP (SPI_OP_MODE_MASTER | SPI_MODE) -#define SPIS_OP (SPI_OP_MODE_SLAVE | SPI_MODE) - -static struct spi_dt_spec spim = SPI_DT_SPEC_GET(DT_NODELABEL(dut_spi_dt), SPIM_OP, 0); -static struct spi_dt_spec spis = SPI_DT_SPEC_GET(DT_NODELABEL(dut_spis_dt), SPIS_OP, 0); - -#define MEMORY_SECTION(node) \ - COND_CODE_1(DT_NODE_HAS_PROP(node, memory_regions), \ - (__attribute__((__section__( \ - LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(node, memory_regions)))))), \ - ()) - -static uint8_t spim_buffer[32] MEMORY_SECTION(DT_NODELABEL(dut_spi)); -static uint8_t spis_buffer[32] MEMORY_SECTION(DT_NODELABEL(dut_spis)); - -struct test_data { - int spim_alloc_idx; - int spis_alloc_idx; - struct spi_buf_set sets[4]; - struct spi_buf_set *mtx_set; - struct spi_buf_set *mrx_set; - struct spi_buf_set *stx_set; - struct spi_buf_set *srx_set; - struct spi_buf bufs[4]; -}; - -static struct test_data tdata; - -/* Allocate buffer from spim or spis space. */ -static uint8_t *buf_alloc(size_t len, bool spim) -{ - int *idx = spim ? &tdata.spim_alloc_idx : &tdata.spis_alloc_idx; - uint8_t *buf = spim ? spim_buffer : spis_buffer; - size_t total = spim ? sizeof(spim_buffer) : sizeof(spis_buffer); - uint8_t *rv; - - if (*idx + len > total) { - zassert_false(true); - - return NULL; - } - - rv = &buf[*idx]; - *idx += len; - - return rv; -} - -ZTEST(spi_error_cases, test_SPI_HALF_DUPLEX_not_supported) -{ - int rv; - int slave_rv; - struct spi_dt_spec spim_invalid = spim; - struct spi_dt_spec spis_invalid = spis; - - spim_invalid.config.operation |= SPI_HALF_DUPLEX; - spis_invalid.config.operation |= SPI_HALF_DUPLEX; - - rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(rv, -ENOTSUP, "Got %d instead", rv); - slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -ENOTSUP, "Got %d instead", slave_rv); -} - -ZTEST(spi_error_cases, test_SPI_OP_MODE_invalid) -{ - int rv; - int slave_rv; - struct spi_dt_spec spim_invalid = spim; - struct spi_dt_spec spis_invalid = spis; - - spim_invalid.config.operation |= SPI_OP_MODE_SLAVE; - spis_invalid.config.operation &= !SPI_OP_MODE_SLAVE; - - /* Check that Operation Mode Slave on spim is not supported */ - rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(rv, -EINVAL, "Got %d instead", rv); - /* Check that Operation Mode Master on spis is not supported */ - slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); -} - -ZTEST(spi_error_cases, test_SPI_MODE_LOOP_not_supported) -{ - int rv; - int slave_rv; - struct spi_dt_spec spim_invalid = spim; - struct spi_dt_spec spis_invalid = spis; - - spim_invalid.config.operation |= SPI_MODE_LOOP; - spis_invalid.config.operation |= SPI_MODE_LOOP; - - rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(rv, -EINVAL, "Got %d instead", rv); - slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); -} - -ZTEST(spi_error_cases, test_only_SPI_LINES_SINGLE_supported) -{ - int rv; - int slave_rv; - struct spi_dt_spec spim_invalid = spim; - struct spi_dt_spec spis_invalid = spis; - - spim_invalid.config.operation |= SPI_LINES_DUAL; - spis_invalid.config.operation |= SPI_LINES_DUAL; - - rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(rv, -EINVAL, "Got %d instead", rv); - slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); - - spim_invalid = spim; - spis_invalid = spis; - spim_invalid.config.operation |= SPI_LINES_QUAD; - spis_invalid.config.operation |= SPI_LINES_QUAD; - - rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(rv, -EINVAL, "Got %d instead", rv); - slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); - - spim_invalid = spim; - spis_invalid = spis; - spim_invalid.config.operation |= SPI_LINES_OCTAL; - spis_invalid.config.operation |= SPI_LINES_OCTAL; - - rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(rv, -EINVAL, "Got %d instead", rv); - slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); -} - -ZTEST(spi_error_cases, test_only_8BIT_supported) -{ - int rv; - int slave_rv; - struct spi_dt_spec spim_invalid = spim; - struct spi_dt_spec spis_invalid = spis; - - spim_invalid.config.operation |= SPI_WORD_SET(16); - spis_invalid.config.operation |= SPI_WORD_SET(16); - - rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(rv, -EINVAL, "Got %d instead", rv); - slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); -} - -ZTEST(spi_error_cases, test_unsupported_frequency) -{ - int rv; - struct spi_dt_spec spim_invalid = spim; - - spim_invalid.config.frequency = 124999; - - rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(rv, -EINVAL, "Got %d instead", rv); -} - -ZTEST(spi_error_cases, test_CS_unsupported_on_slave) -{ - int slave_rv; - struct spi_dt_spec spis_invalid = spis; - struct gpio_dt_spec test_gpio = { DEVICE_DT_GET(DT_NODELABEL(gpio1)), 10, GPIO_ACTIVE_LOW }; - - spis_invalid.config.cs.gpio = test_gpio; - - slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); -} - -ZTEST(spi_error_cases, test_spis_scattered_tx_buf_not_supported) -{ - int slave_rv; - - tdata.sets[2].count = 2; - slave_rv = spi_transceive_dt(&spis, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -ENOTSUP, "Got %d instead", slave_rv); -} - -ZTEST(spi_error_cases, test_spis_scattered_rx_buf_not_supported) -{ - int slave_rv; - - tdata.sets[3].count = 2; - slave_rv = spi_transceive_dt(&spis, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -ENOTSUP, "Got %d instead", slave_rv); -} - -ZTEST(spi_error_cases, test_spis_tx_buf_too_big) -{ - int slave_rv; - - tdata.bufs[2].len = (size_t)65536; - slave_rv = spi_transceive_dt(&spis, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); -} - -ZTEST(spi_error_cases, test_spis_rx_buf_too_big) -{ - int slave_rv; - - tdata.bufs[3].len = (size_t)65536; - slave_rv = spi_transceive_dt(&spis, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); -} - -ZTEST(spi_error_cases, test_spis_tx_buf_not_in_ram) -{ - int slave_rv; - - tdata.bufs[2].buf = (void *)0x12345678; - slave_rv = spi_transceive_dt(&spis, tdata.stx_set, tdata.srx_set); - zassert_equal(slave_rv, -ENOTSUP, "Got %d instead", slave_rv); -} - -static void before(void *not_used) -{ - ARG_UNUSED(not_used); - size_t len = 16; - - memset(&tdata, 0, sizeof(tdata)); - for (size_t i = 0; i < sizeof(spim_buffer); i++) { - spim_buffer[i] = (uint8_t)i; - } - for (size_t i = 0; i < sizeof(spis_buffer); i++) { - spis_buffer[i] = (uint8_t)i; - } - - for (int i = 0; i < 4; i++) { - tdata.bufs[i].buf = buf_alloc(len, i < 2); - tdata.bufs[i].len = len; - tdata.sets[i].buffers = &tdata.bufs[i]; - tdata.sets[i].count = 1; - } - - tdata.mtx_set = &tdata.sets[0]; - tdata.mrx_set = &tdata.sets[1]; - tdata.stx_set = &tdata.sets[2]; - tdata.srx_set = &tdata.sets[3]; -} - -static void *suite_setup(void) -{ - return NULL; -} - -ZTEST_SUITE(spi_error_cases, NULL, suite_setup, before, NULL, NULL); diff --git a/tests/drivers/spi/spi_error_cases/testcase.yaml b/tests/drivers/spi/spi_error_cases/testcase.yaml deleted file mode 100644 index 17cee921111..00000000000 --- a/tests/drivers/spi/spi_error_cases/testcase.yaml +++ /dev/null @@ -1,12 +0,0 @@ -tests: - drivers.spi.spi_error_cases: - depends_on: spi - tags: drivers spi - harness: ztest - harness_config: - fixture: gpio_spi_loopback - platform_allow: - - nrf52840dk_nrf52840 - - nrf54l15pdk_nrf54l15_cpuapp - integration_platforms: - - nrf52840dk_nrf52840 From 754abd0e7e513310b72141f21a82fff0392f9818 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:06 +0200 Subject: [PATCH 2154/2402] Revert "[nrf fromlist] boards: Enable ADC in nRF54L15 PDK configuration" This reverts commit c045098d5a17be01227750fe27b422983ce8b59d. Signed-off-by: Gerard Marull-Paretas --- .../arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts index f64952ba886..e6ef815e783 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -201,7 +201,3 @@ t-exit-dpd = <35000>; }; }; - -&adc { - status = "okay"; -}; From d20dbb4f5d8fcc496bea2c19517d546f1144559e Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:06 +0200 Subject: [PATCH 2155/2402] Revert "[nrf fromtree] tests: boards: nrf: add i2c driver test with TWIS slave" This reverts commit ee43b9ac08c6351aeaee6089fb28c659151596d6. Signed-off-by: Gerard Marull-Paretas --- tests/boards/nrf/i2c/i2c_slave/CMakeLists.txt | 10 -- .../i2c_slave/boards/nrf52840dk_nrf52840.conf | 1 - .../boards/nrf52840dk_nrf52840.overlay | 60 -------- .../boards/nrf5340dk_nrf5340_cpuapp.conf | 1 - .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 58 ------- .../boards/nrf54h20dk_nrf54h20_cpuapp.conf | 1 - .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 63 -------- .../boards/nrf54l15pdk_nrf54l15_cpuapp.conf | 1 - .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 59 ------- tests/boards/nrf/i2c/i2c_slave/prj.conf | 2 - tests/boards/nrf/i2c/i2c_slave/src/main.c | 145 ------------------ tests/boards/nrf/i2c/i2c_slave/testcase.yaml | 12 -- 12 files changed, 413 deletions(-) delete mode 100644 tests/boards/nrf/i2c/i2c_slave/CMakeLists.txt delete mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.conf delete mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay delete mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.conf delete mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.overlay delete mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.conf delete mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay delete mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.conf delete mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay delete mode 100644 tests/boards/nrf/i2c/i2c_slave/prj.conf delete mode 100644 tests/boards/nrf/i2c/i2c_slave/src/main.c delete mode 100644 tests/boards/nrf/i2c/i2c_slave/testcase.yaml diff --git a/tests/boards/nrf/i2c/i2c_slave/CMakeLists.txt b/tests/boards/nrf/i2c/i2c_slave/CMakeLists.txt deleted file mode 100644 index 43130d6a07d..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(i2c_slave) - -FILE(GLOB app_sources src/*.c) - -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.conf b/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.conf deleted file mode 100644 index e79ad7a8126..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_NRFX_TWIS1=y diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay deleted file mode 100644 index 8628731faf4..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay +++ /dev/null @@ -1,60 +0,0 @@ -/ { - aliases { - i2c-slave = &i2c1; - }; -}; - -&pinctrl { - i2c0_default_alt: i2c0_default_alt { - group1 { - psels = , - ; - }; - }; - - i2c0_sleep_alt: i2c0_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; - - i2c1_default_alt: i2c1_default_alt { - group1 { -/* Temporary workaround as it is currently not possible - * to configure pins for TWIS with pinctrl. */ - psels = , - ; - bias-pull-up; - }; - }; - - i2c1_sleep_alt: i2c1_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; -}; - -&i2c0 { - compatible = "nordic,nrf-twim"; - status = "okay"; - pinctrl-0 = <&i2c0_default_alt>; - pinctrl-1 = <&i2c0_sleep_alt>; - pinctrl-names = "default", "sleep"; - sensor: sensor@54 { - reg = <0x54>; - }; -}; - - -&i2c1 { - compatible = "nordic,nrf-twis"; - status = "okay"; - pinctrl-0 = <&i2c1_default_alt>; - pinctrl-1 = <&i2c1_sleep_alt>; - pinctrl-names = "default", "sleep"; -}; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.conf b/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.conf deleted file mode 100644 index a7bedf1f04b..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_NRFX_TWIS2=y diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.overlay deleted file mode 100644 index d473a04f85c..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ /dev/null @@ -1,58 +0,0 @@ -/ { - aliases { - i2c-slave = &i2c2; - }; -}; - -&pinctrl { - i2c1_default_alt: i2c1_default_alt { - group1 { - psels = , - ; - }; - }; - - i2c1_sleep_alt: i2c1_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; - - i2c2_default_alt: i2c2_default_alt { - group1 { -/* Temporary workaround as it is currently not possible - * to configure pins for TWIS with pinctrl. */ - psels = , - ; - bias-pull-up; - }; - }; - - i2c2_sleep_alt: i2c2_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; -}; - -&i2c1 { - compatible = "nordic,nrf-twim"; - status = "okay"; - pinctrl-0 = <&i2c1_default_alt>; - pinctrl-1 = <&i2c1_sleep_alt>; - pinctrl-names = "default", "sleep"; - sensor: sensor@54 { - reg = <0x54>; - }; -}; - -&i2c2 { - compatible = "nordic,nrf-twis"; - pinctrl-0 = <&i2c2_default_alt>; - pinctrl-1 = <&i2c2_sleep_alt>; - pinctrl-names = "default", "sleep"; -}; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.conf b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.conf deleted file mode 100644 index 157e0a11f72..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_NRFX_TWIS131=y diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay deleted file mode 100644 index 73d1d85cf45..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ /dev/null @@ -1,63 +0,0 @@ -/ { - aliases { - i2c-slave = &i2c131; - }; -}; - -&pinctrl { - i2c130_default_alt: i2c130_default_alt { - group1 { - psels = , - ; - }; - }; - - i2c130_sleep_alt: i2c130_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; - - i2c131_default_alt: i2c131_default_alt { - group1 { -/* Temporary workaround as it is currently not possible - * to configure pins for TWIS with pinctrl. */ - psels = , - ; - bias-pull-up; - }; - }; - - i2c131_sleep_alt: i2c131_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; -}; - -&i2c130 { - compatible = "nordic,nrf-twim"; - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c130_default_alt>; - pinctrl-1 = <&i2c130_sleep_alt>; - pinctrl-names = "default", "sleep"; - memory-regions = <&cpuapp_dma_region>; - sensor: sensor@54 { - reg = <0x54>; - }; -}; - -&i2c131 { - compatible = "nordic,nrf-twis"; - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c131_default_alt>; - pinctrl-1 = <&i2c131_sleep_alt>; - pinctrl-names = "default", "sleep"; - memory-regions = <&cpuapp_dma_region>; -}; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.conf b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.conf deleted file mode 100644 index b01af3b36a7..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_NRFX_TWIS22=y diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay deleted file mode 100644 index d60e42659ee..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay +++ /dev/null @@ -1,59 +0,0 @@ -/ { - aliases { - i2c-slave = &i2c22; - }; -}; - -&pinctrl { - i2c21_default_alt: i2c21_default_alt { - group1 { - psels = , - ; - }; - }; - - i2c21_sleep_alt: i2c21_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; - - i2c22_default_alt: i2c22_default_alt { - group1 { -/* Temporary workaround as it is currently not possible - * to configure pins for TWIS with pinctrl. */ - psels = , - ; - bias-pull-up; - }; - }; - - i2c22_sleep_alt: i2c22_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; -}; - -&i2c21 { - compatible = "nordic,nrf-twim"; - status = "okay"; - pinctrl-0 = <&i2c21_default_alt>; - pinctrl-1 = <&i2c21_sleep_alt>; - pinctrl-names = "default", "sleep"; - sensor: sensor@54 { - reg = <0x54>; - }; -}; - -&i2c22 { - compatible = "nordic,nrf-twis"; - status = "okay"; - pinctrl-0 = <&i2c22_default_alt>; - pinctrl-1 = <&i2c22_sleep_alt>; - pinctrl-names = "default", "sleep"; -}; diff --git a/tests/boards/nrf/i2c/i2c_slave/prj.conf b/tests/boards/nrf/i2c/i2c_slave/prj.conf deleted file mode 100644 index 4b19609ecfb..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/prj.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_I2C=y -CONFIG_ZTEST=y diff --git a/tests/boards/nrf/i2c/i2c_slave/src/main.c b/tests/boards/nrf/i2c/i2c_slave/src/main.c deleted file mode 100644 index 1de4b16bc2c..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/src/main.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#if CONFIG_NRFX_TWIS1 -#define I2C_S_INSTANCE 1 -#elif CONFIG_NRFX_TWIS2 -#define I2C_S_INSTANCE 2 -#elif CONFIG_NRFX_TWIS22 -#define I2C_S_INSTANCE 22 -#elif CONFIG_NRFX_TWIS131 -#define I2C_S_INSTANCE 131 -#else -#error "TWIS instance not enabled or not supported" -#endif - -#define NODE_SENSOR DT_NODELABEL(sensor) -#define NODE_TWIS DT_ALIAS(i2c_slave) - -#define TWIS_MEMORY_SECTION \ - COND_CODE_1(DT_NODE_HAS_PROP(NODE_TWIS, memory_regions), \ - (__attribute__((__section__( \ - LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(NODE_TWIS, memory_regions)))))), \ - ()) - -#define TEST_DATA_SIZE 6 -static const uint8_t msg[TEST_DATA_SIZE] = "Nordic"; -static const nrfx_twis_t twis = NRFX_TWIS_INSTANCE(I2C_S_INSTANCE); - -static uint8_t i2c_slave_buffer[TEST_DATA_SIZE] TWIS_MEMORY_SECTION; -static uint8_t i2c_master_buffer[TEST_DATA_SIZE]; -struct i2c_api_twis_fixture { - const struct device *dev; - uint8_t addr; - uint8_t *const master_buffer; - uint8_t *const slave_buffer; -}; - -void i2s_slave_handler(nrfx_twis_evt_t const *p_event) -{ - switch (p_event->type) { - case NRFX_TWIS_EVT_READ_REQ: - nrfx_twis_tx_prepare(&twis, i2c_slave_buffer, TEST_DATA_SIZE); - TC_PRINT("TWIS event: read request\n"); - break; - case NRFX_TWIS_EVT_READ_DONE: - TC_PRINT("TWIS event: read done\n"); - break; - case NRFX_TWIS_EVT_WRITE_REQ: - nrfx_twis_rx_prepare(&twis, i2c_slave_buffer, TEST_DATA_SIZE); - TC_PRINT("TWIS event: write request\n"); - break; - case NRFX_TWIS_EVT_WRITE_DONE: - zassert_mem_equal(i2c_slave_buffer, msg, TEST_DATA_SIZE); - TC_PRINT("TWIS event: write done\n"); - break; - default: - TC_PRINT("TWIS event: %d\n", p_event->type); - break; - } -} - -static void *test_setup(void) -{ - static struct i2c_api_twis_fixture fixture = { - .dev = DEVICE_DT_GET(DT_BUS(NODE_SENSOR)), - .addr = DT_REG_ADDR(NODE_SENSOR), - .master_buffer = i2c_master_buffer, - .slave_buffer = i2c_slave_buffer, - }; - const nrfx_twis_config_t config = { - .addr = {fixture.addr, 0}, - .skip_gpio_cfg = true, - .skip_psel_cfg = true, - }; - int ret; - - zassert_equal(NRFX_SUCCESS, nrfx_twis_init(&twis, &config, i2s_slave_handler), - "TWIS initialization failed"); - - PINCTRL_DT_DEFINE(NODE_TWIS); - ret = pinctrl_apply_state(PINCTRL_DT_DEV_CONFIG_GET(NODE_TWIS), PINCTRL_STATE_DEFAULT); - zassert_ok(ret); - - IRQ_CONNECT(DT_IRQN(NODE_TWIS), DT_IRQ(NODE_TWIS, priority), - NRFX_TWIS_INST_HANDLER_GET(I2C_S_INSTANCE), NULL, 0); - - nrfx_twis_enable(&twis); - - return &fixture; -} - -static void cleanup_buffers(void *argc) -{ - struct i2c_api_twis_fixture *fixture = (struct i2c_api_twis_fixture *)argc; - - memset(fixture->slave_buffer, 0, TEST_DATA_SIZE); - memset(fixture->master_buffer, 0, TEST_DATA_SIZE); -} - -ZTEST_USER_F(i2c_api_twis, test_i2c_read_write) -{ - int ret = i2c_write_read(fixture->dev, fixture->addr, msg, TEST_DATA_SIZE, - fixture->master_buffer, TEST_DATA_SIZE); - - zassert_ok(ret); - zassert_mem_equal(fixture->master_buffer, msg, TEST_DATA_SIZE); -} - -ZTEST_USER_F(i2c_api_twis, test_i2c_read) -{ - /* Prepare slave data */ - strncpy(fixture->slave_buffer, msg, TEST_DATA_SIZE); - zassert_mem_equal(fixture->slave_buffer, msg, TEST_DATA_SIZE); - - int ret = i2c_read(fixture->dev, fixture->master_buffer, TEST_DATA_SIZE, fixture->addr); - - zassert_ok(ret); - zassert_mem_equal(fixture->master_buffer, msg, TEST_DATA_SIZE); -} - -ZTEST_USER_F(i2c_api_twis, test_i2c_write) -{ - int ret = i2c_write(fixture->dev, msg, TEST_DATA_SIZE, fixture->addr); - - zassert_ok(ret); - zassert_mem_equal(fixture->slave_buffer, msg, TEST_DATA_SIZE); -} - -ZTEST_SUITE(i2c_api_twis, NULL, test_setup, NULL, cleanup_buffers, NULL); diff --git a/tests/boards/nrf/i2c/i2c_slave/testcase.yaml b/tests/boards/nrf/i2c/i2c_slave/testcase.yaml deleted file mode 100644 index 06213b742ea..00000000000 --- a/tests/boards/nrf/i2c/i2c_slave/testcase.yaml +++ /dev/null @@ -1,12 +0,0 @@ -tests: - boards.nrf.i2c.i2c_slave: - depends_on: i2c - tags: drivers i2c - harness: ztest - harness_config: - fixture: i2c_loopback - platform_allow: nrf52840dk_nrf52840 nrf5340dk_nrf5340_cpuapp nrf54l15pdk_nrf54l15_cpuapp - integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf54l15pdk_nrf54l15_cpuapp From 814c4912fbe2f148159e724850e57494dd380134 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:06 +0200 Subject: [PATCH 2156/2402] Revert "[nrf fromtree] soc: nordic: add nRF54 TWIS HAS_HW symbols" This reverts commit 4a4ff2741cb753e5d5e6961f283486b0c062c8ba. Signed-off-by: Gerard Marull-Paretas --- soc/common/nordic_nrf/Kconfig.peripherals | 36 ----------------------- 1 file changed, 36 deletions(-) diff --git a/soc/common/nordic_nrf/Kconfig.peripherals b/soc/common/nordic_nrf/Kconfig.peripherals index f0adc82d44a..817002f7282 100644 --- a/soc/common/nordic_nrf/Kconfig.peripherals +++ b/soc/common/nordic_nrf/Kconfig.peripherals @@ -530,42 +530,6 @@ config HAS_HW_NRF_TWIS2 config HAS_HW_NRF_TWIS3 def_bool $(dt_nodelabel_enabled_with_compat,i2c3,$(DT_COMPAT_NORDIC_NRF_TWIS)) -config HAS_HW_NRF_TWIS20 - def_bool $(dt_nodelabel_enabled_with_compat,i2c20,$(DT_COMPAT_NORDIC_NRF_TWIS)) - -config HAS_HW_NRF_TWIS21 - def_bool $(dt_nodelabel_enabled_with_compat,i2c21,$(DT_COMPAT_NORDIC_NRF_TWIS)) - -config HAS_HW_NRF_TWIS22 - def_bool $(dt_nodelabel_enabled_with_compat,i2c22,$(DT_COMPAT_NORDIC_NRF_TWIS)) - -config HAS_HW_NRF_TWIS30 - def_bool $(dt_nodelabel_enabled_with_compat,i2c30,$(DT_COMPAT_NORDIC_NRF_TWIS)) - -config HAS_HW_NRF_TWIS130 - def_bool $(dt_nodelabel_enabled_with_compat,i2c130,$(DT_COMPAT_NORDIC_NRF_TWIS)) - -config HAS_HW_NRF_TWIS131 - def_bool $(dt_nodelabel_enabled_with_compat,i2c131,$(DT_COMPAT_NORDIC_NRF_TWIS)) - -config HAS_HW_NRF_TWIS132 - def_bool $(dt_nodelabel_enabled_with_compat,i2c132,$(DT_COMPAT_NORDIC_NRF_TWIS)) - -config HAS_HW_NRF_TWIS133 - def_bool $(dt_nodelabel_enabled_with_compat,i2c133,$(DT_COMPAT_NORDIC_NRF_TWIS)) - -config HAS_HW_NRF_TWIS134 - def_bool $(dt_nodelabel_enabled_with_compat,i2c134,$(DT_COMPAT_NORDIC_NRF_TWIS)) - -config HAS_HW_NRF_TWIS135 - def_bool $(dt_nodelabel_enabled_with_compat,i2c135,$(DT_COMPAT_NORDIC_NRF_TWIS)) - -config HAS_HW_NRF_TWIS136 - def_bool $(dt_nodelabel_enabled_with_compat,i2c136,$(DT_COMPAT_NORDIC_NRF_TWIS)) - -config HAS_HW_NRF_TWIS137 - def_bool $(dt_nodelabel_enabled_with_compat,i2c137,$(DT_COMPAT_NORDIC_NRF_TWIS)) - config HAS_HW_NRF_UART0 def_bool $(dt_nodelabel_enabled_with_compat,uart0,$(DT_COMPAT_NORDIC_NRF_UART)) From f49d5db44aeeb7c91d3c4a88f0aa036e343a20b2 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:07 +0200 Subject: [PATCH 2157/2402] Revert "[nrf fromtree] dts: bindings: regulator: Added regulator-boot-off to allowlists" This reverts commit 94a7ff975973a43864c851af331abc3ae8dfc962. Signed-off-by: Gerard Marull-Paretas --- dts/bindings/regulator/adi,adp5360-regulator.yaml | 1 - dts/bindings/regulator/nordic,npm1300-regulator.yaml | 1 - dts/bindings/regulator/nordic,npm6001-regulator.yaml | 1 - dts/bindings/regulator/x-powers,axp192-regulator.yaml | 1 - 4 files changed, 4 deletions(-) diff --git a/dts/bindings/regulator/adi,adp5360-regulator.yaml b/dts/bindings/regulator/adi,adp5360-regulator.yaml index e54a305e80f..d683bd694ef 100644 --- a/dts/bindings/regulator/adi,adp5360-regulator.yaml +++ b/dts/bindings/regulator/adi,adp5360-regulator.yaml @@ -34,7 +34,6 @@ child-binding: property-allowlist: - regulator-always-on - regulator-boot-on - - regulator-boot-off - regulator-init-microvolt - regulator-min-microvolt - regulator-max-microvolt diff --git a/dts/bindings/regulator/nordic,npm1300-regulator.yaml b/dts/bindings/regulator/nordic,npm1300-regulator.yaml index e0fc28ff8be..c5364a49fe0 100644 --- a/dts/bindings/regulator/nordic,npm1300-regulator.yaml +++ b/dts/bindings/regulator/nordic,npm1300-regulator.yaml @@ -53,7 +53,6 @@ child-binding: property-allowlist: - regulator-always-on - regulator-boot-on - - regulator-boot-off - regulator-min-microvolt - regulator-max-microvolt - regulator-init-microvolt diff --git a/dts/bindings/regulator/nordic,npm6001-regulator.yaml b/dts/bindings/regulator/nordic,npm6001-regulator.yaml index 378f6c0a8ec..34c90c78640 100644 --- a/dts/bindings/regulator/nordic,npm6001-regulator.yaml +++ b/dts/bindings/regulator/nordic,npm6001-regulator.yaml @@ -45,7 +45,6 @@ child-binding: property-allowlist: - regulator-always-on - regulator-boot-on - - regulator-boot-off - regulator-max-microamp - regulator-min-microvolt - regulator-max-microvolt diff --git a/dts/bindings/regulator/x-powers,axp192-regulator.yaml b/dts/bindings/regulator/x-powers,axp192-regulator.yaml index 9072e80727b..98599731c3b 100644 --- a/dts/bindings/regulator/x-powers,axp192-regulator.yaml +++ b/dts/bindings/regulator/x-powers,axp192-regulator.yaml @@ -51,7 +51,6 @@ child-binding: - regulator-max-microvolt - regulator-always-on - regulator-boot-on - - regulator-boot-off - regulator-initial-mode - regulator-allowed-modes From c77fbf1953e80145b3b6378c8a395335105ed02a Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:07 +0200 Subject: [PATCH 2158/2402] Revert "[nrf fromtree] tests: drivers: regulator: added regulator-boot-off tests" This reverts commit 8d3fda6b1beb831d5352017afaf3c0a218725c7c. Signed-off-by: Gerard Marull-Paretas --- tests/drivers/regulator/api/app.overlay | 9 -------- tests/drivers/regulator/api/src/main.c | 29 ------------------------- 2 files changed, 38 deletions(-) diff --git a/tests/drivers/regulator/api/app.overlay b/tests/drivers/regulator/api/app.overlay index 6dfeefed18f..25d1d8bb795 100644 --- a/tests/drivers/regulator/api/app.overlay +++ b/tests/drivers/regulator/api/app.overlay @@ -26,14 +26,5 @@ regulator-initial-mode = <1>; regulator-active-discharge = <1>; }; - - reg4: REG4 { - regulator-boot-off; - }; - - reg5: REG5 { - regulator-boot-off; - fake-is-enabled-in-hardware; - }; }; }; diff --git a/tests/drivers/regulator/api/src/main.c b/tests/drivers/regulator/api/src/main.c index 93fa7863085..648d761a8b4 100644 --- a/tests/drivers/regulator/api/src/main.c +++ b/tests/drivers/regulator/api/src/main.c @@ -19,10 +19,6 @@ static const struct device *const reg1 = DEVICE_DT_GET(DT_NODELABEL(reg1)); static const struct device *const reg2 = DEVICE_DT_GET(DT_NODELABEL(reg2)); /* REG3: regulator-max/min-microvolt/microamp, regulator-allowed-modes */ static const struct device *const reg3 = DEVICE_DT_GET(DT_NODELABEL(reg3)); -/* REG4: regulator-boot-off */ -static const struct device *const reg4 = DEVICE_DT_GET(DT_NODELABEL(reg4)); -/* REG5: regulator-boot-off and is_enabled */ -static const struct device *const reg5 = DEVICE_DT_GET(DT_NODELABEL(reg5)); ZTEST(regulator_api, test_parent_dvs_state_set_not_implemented) { @@ -133,10 +129,6 @@ ZTEST(regulator_api, test_common_config) zassert_equal(config->allowed_modes[1], 10U); zassert_equal(config->allowed_modes_cnt, 2U); zassert_equal(REGULATOR_ACTIVE_DISCHARGE_GET_BITS(config->flags), 1U); - - /* reg4: regulator-boot-off */ - config = reg4->config; - zassert_equal(config->flags & REGULATOR_BOOT_OFF, REGULATOR_BOOT_OFF); } ZTEST(regulator_api, test_common_is_init_enabled) @@ -145,8 +137,6 @@ ZTEST(regulator_api, test_common_is_init_enabled) zassert_true(regulator_common_is_init_enabled(reg1)); zassert_true(regulator_common_is_init_enabled(reg2)); zassert_false(regulator_common_is_init_enabled(reg3)); - zassert_false(regulator_common_is_init_enabled(reg4)); - zassert_false(regulator_common_is_init_enabled(reg5)); } ZTEST(regulator_api, test_enable_disable) @@ -181,16 +171,6 @@ ZTEST(regulator_api, test_enable_disable) zassert_equal(regulator_disable(reg0), 0); zassert_equal(regulator_fake_disable_fake.arg0_val, reg0); zassert_equal(regulator_fake_disable_fake.call_count, 2U); - - /* REG5: disabled at boot, can be enabled again */ - zassert_equal(regulator_enable(reg5), 0); - zassert_equal(regulator_fake_enable_fake.call_count, 3U); - - /* REG5: disable */ - zassert_equal(regulator_disable(reg5), 0); - zassert_equal(regulator_fake_disable_fake.call_count, 3U); - - } ZTEST(regulator_api, test_count_voltages_not_implemented) @@ -796,8 +776,6 @@ void *setup(void) zassert_true(device_is_ready(reg1)); zassert_true(device_is_ready(reg2)); zassert_true(device_is_ready(reg3)); - zassert_true(device_is_ready(reg4)); - zassert_true(device_is_ready(reg5)); /* REG1, REG2 initialized at init time (always-on/boot-on) */ zassert_equal(regulator_fake_enable_fake.call_count, 2U); @@ -807,13 +785,6 @@ void *setup(void) /* REG3 mode set at init time (initial-mode) */ zassert_equal(regulator_fake_set_mode_fake.call_count, 1U); - /* REG4 already disabled at init time (boot-off) */ - zassert_false(regulator_is_enabled(reg4)); - - /* REG5 explicitly disabled at init time (boot-off) */ - zassert_equal(regulator_fake_disable_fake.call_count, 1U); - zassert_false(regulator_is_enabled(reg5)); - return NULL; } From 3740446eb683a285e96b9dbacdcba5febe718e74 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:07 +0200 Subject: [PATCH 2159/2402] Revert "[nrf fromtree] drivers: regulator: fake: Added is_enabled property" This reverts commit 4698e88891b150910a5c84eb50c4e50be79fc9ad. Signed-off-by: Gerard Marull-Paretas --- drivers/regulator/regulator_fake.c | 6 +----- dts/bindings/regulator/zephyr,fake-regulator.yaml | 7 ------- 2 files changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/regulator/regulator_fake.c b/drivers/regulator/regulator_fake.c index c2c71593c61..129ef2f215e 100644 --- a/drivers/regulator/regulator_fake.c +++ b/drivers/regulator/regulator_fake.c @@ -15,7 +15,6 @@ struct regulator_fake_config { struct regulator_common_config common; - bool is_enabled; }; struct regulator_fake_data { @@ -65,11 +64,9 @@ static struct regulator_driver_api api = { static int regulator_fake_init(const struct device *dev) { - const struct regulator_fake_config *config = dev->config; - regulator_common_data_init(dev); - return regulator_common_init(dev, config->is_enabled); + return regulator_common_init(dev, false); } /* parent regulator */ @@ -93,7 +90,6 @@ static struct regulator_parent_driver_api parent_api = { \ static const struct regulator_fake_config FAKE_CONF_NAME(node_id) = { \ .common = REGULATOR_DT_COMMON_CONFIG_INIT(node_id), \ - .is_enabled = DT_PROP(node_id, fake_is_enabled_in_hardware), \ }; \ \ DEVICE_DT_DEFINE(node_id, regulator_fake_init, NULL, \ diff --git a/dts/bindings/regulator/zephyr,fake-regulator.yaml b/dts/bindings/regulator/zephyr,fake-regulator.yaml index 833dc8ca115..7a6894948b2 100644 --- a/dts/bindings/regulator/zephyr,fake-regulator.yaml +++ b/dts/bindings/regulator/zephyr,fake-regulator.yaml @@ -10,10 +10,3 @@ compatible: "zephyr,fake-regulator" child-binding: include: regulator.yaml - - properties: - fake-is-enabled-in-hardware: - type: boolean - description: | - Sets the is_enabled flag passed to regulator_common_init. - Allows test cases where the regulator is enabled in hardware. From 920d951f0df068f76fd868ccc69bbc9090f4009d Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:07 +0200 Subject: [PATCH 2160/2402] Revert "[nrf fromtree] drivers: regulator: common: Added regulator-boot-off" This reverts commit f71ddc7dcc5d89a297cd1691582318efcb12a0ed. Signed-off-by: Gerard Marull-Paretas --- drivers/regulator/regulator_common.c | 3 --- dts/bindings/regulator/regulator.yaml | 5 ----- include/zephyr/drivers/regulator.h | 7 +------ 3 files changed, 1 insertion(+), 14 deletions(-) diff --git a/drivers/regulator/regulator_common.c b/drivers/regulator/regulator_common.c index c539e1169ee..f2d9f6275e6 100644 --- a/drivers/regulator/regulator_common.c +++ b/drivers/regulator/regulator_common.c @@ -90,9 +90,6 @@ int regulator_common_init(const struct device *dev, bool is_enabled) if (is_enabled) { data->refcnt++; - if ((config->flags & REGULATOR_BOOT_OFF) != 0U) { - return regulator_disable(dev); - } } else if ((config->flags & REGULATOR_INIT_ENABLED) != 0U) { ret = api->enable(dev); if (ret < 0) { diff --git a/dts/bindings/regulator/regulator.yaml b/dts/bindings/regulator/regulator.yaml index b072ce8c920..635bfa49596 100644 --- a/dts/bindings/regulator/regulator.yaml +++ b/dts/bindings/regulator/regulator.yaml @@ -61,11 +61,6 @@ properties: This property is intended to only be used for regulators where software cannot read the state of the regulator. - regulator-boot-off: - type: boolean - description: | - Regulator should be disabled on boot. - regulator-allow-bypass: type: boolean description: allow the regulator to go into bypass mode diff --git a/include/zephyr/drivers/regulator.h b/include/zephyr/drivers/regulator.h index 46a085d9239..77e441d0dae 100644 --- a/include/zephyr/drivers/regulator.h +++ b/include/zephyr/drivers/regulator.h @@ -141,8 +141,6 @@ __subsystem struct regulator_driver_api { /** Regulator active discharge get bits */ #define REGULATOR_ACTIVE_DISCHARGE_GET_BITS(x) \ (((x) & REGULATOR_ACTIVE_DISCHARGE_MASK) >> REGULATOR_ACTIVE_DISCHARGE_POS) -/** Indicates regulator must be initialized OFF */ -#define REGULATOR_BOOT_OFF BIT(4) /** @} */ @@ -214,9 +212,7 @@ struct regulator_common_config { REGULATOR_BOOT_ON) | \ (REGULATOR_ACTIVE_DISCHARGE_SET_BITS( \ DT_PROP_OR(node_id, regulator_active_discharge, \ - REGULATOR_ACTIVE_DISCHARGE_DEFAULT))) | \ - (DT_PROP_OR(node_id, regulator_boot_off, 0U) * \ - REGULATOR_BOOT_OFF)), \ + REGULATOR_ACTIVE_DISCHARGE_DEFAULT)))), \ } /** @@ -258,7 +254,6 @@ void regulator_common_data_init(const struct device *dev); * * - Automatically enable the regulator if it is set to `regulator-boot-on` * or `regulator-always-on` and increase its usage count. - * - Automatically disable the regulator if it is set to `regulator-boot-off`. * - Configure the regulator mode if `regulator-initial-mode` is set. * - Ensure regulator voltage is set to a valid range. * From 2c7ed1e8415bcf5c34cc3d35c085a6dd74516b06 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:07 +0200 Subject: [PATCH 2161/2402] Revert "[nrf fromtree] tests: drivers: nrf_grtc_timer: add nRF54H20 target" This reverts commit 05d72f27f9494aadd6cda8b09f23c17951170091. Signed-off-by: Gerard Marull-Paretas --- tests/drivers/timer/nrf_grtc_timer/testcase.yaml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/tests/drivers/timer/nrf_grtc_timer/testcase.yaml b/tests/drivers/timer/nrf_grtc_timer/testcase.yaml index 654594cfe0a..81b320c7c9b 100644 --- a/tests/drivers/timer/nrf_grtc_timer/testcase.yaml +++ b/tests/drivers/timer/nrf_grtc_timer/testcase.yaml @@ -1,7 +1,4 @@ tests: drivers.timer.nrf_grtc_timer: tags: drivers - platform_allow: - - nrf54l15pdk_nrf54l15_cpuapp - - nrf54h20dk_nrf54h20_cpuapp - - nrf54h20dk_nrf54h20_cpurad + platform_allow: nrf54l15pdk_nrf54l15_cpuapp From ee8ac538f2db98c529fa4b5a8d7080401ebd3bd3 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:08 +0200 Subject: [PATCH 2162/2402] Revert "[nrf fromtree] tests: drivers: timer: add nrf_grtc_timer tests" This reverts commit 33a0ef8c3ab89959671c703f79d5b1b8d6faaf42. Signed-off-by: Gerard Marull-Paretas --- .../timer/nrf_grtc_timer/CMakeLists.txt | 9 ----- tests/drivers/timer/nrf_grtc_timer/prj.conf | 2 - tests/drivers/timer/nrf_grtc_timer/src/main.c | 40 ------------------- .../timer/nrf_grtc_timer/testcase.yaml | 4 -- 4 files changed, 55 deletions(-) delete mode 100644 tests/drivers/timer/nrf_grtc_timer/CMakeLists.txt delete mode 100644 tests/drivers/timer/nrf_grtc_timer/prj.conf delete mode 100644 tests/drivers/timer/nrf_grtc_timer/src/main.c delete mode 100644 tests/drivers/timer/nrf_grtc_timer/testcase.yaml diff --git a/tests/drivers/timer/nrf_grtc_timer/CMakeLists.txt b/tests/drivers/timer/nrf_grtc_timer/CMakeLists.txt deleted file mode 100644 index 6dfe69d0045..00000000000 --- a/tests/drivers/timer/nrf_grtc_timer/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(nrf_grtc_timer) - -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/timer/nrf_grtc_timer/prj.conf b/tests/drivers/timer/nrf_grtc_timer/prj.conf deleted file mode 100644 index dea03477519..00000000000 --- a/tests/drivers/timer/nrf_grtc_timer/prj.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ZTEST=y -CONFIG_NRF_GRTC_TIMER=y diff --git a/tests/drivers/timer/nrf_grtc_timer/src/main.c b/tests/drivers/timer/nrf_grtc_timer/src/main.c deleted file mode 100644 index 197270cc6a4..00000000000 --- a/tests/drivers/timer/nrf_grtc_timer/src/main.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2022, Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include -#include -#include - -#define GRTC_SLEW_TICKS 10 - -ZTEST(nrf_grtc_timer, test_get_ticks) -{ - k_timeout_t t = K_MSEC(1); - - uint64_t exp_ticks = z_nrf_grtc_timer_read() + t.ticks; - int64_t ticks; - - /* Relative 1ms from now timeout converted to GRTC */ - ticks = z_nrf_grtc_timer_get_ticks(t); - zassert_true((ticks >= exp_ticks) && (ticks <= (exp_ticks + GRTC_SLEW_TICKS)), - "Unexpected result %" PRId64 " (expected: %" PRId64 ")", ticks, exp_ticks); - - /* Absolute timeout 1ms in the past */ - t = Z_TIMEOUT_TICKS(Z_TICK_ABS(sys_clock_tick_get() - K_MSEC(1).ticks)); - - exp_ticks = z_nrf_grtc_timer_read() - K_MSEC(1).ticks; - ticks = z_nrf_grtc_timer_get_ticks(t); - zassert_true((ticks >= exp_ticks) && (ticks <= (exp_ticks + GRTC_SLEW_TICKS)), - "Unexpected result %" PRId64 " (expected: %" PRId64 ")", ticks, exp_ticks); - - /* Absolute timeout 10ms in the future */ - t = Z_TIMEOUT_TICKS(Z_TICK_ABS(sys_clock_tick_get() + K_MSEC(10).ticks)); - exp_ticks = z_nrf_grtc_timer_read() + K_MSEC(10).ticks; - ticks = z_nrf_grtc_timer_get_ticks(t); - zassert_true((ticks >= exp_ticks) && (ticks <= (exp_ticks + GRTC_SLEW_TICKS)), - "Unexpected result %" PRId64 " (expected: %" PRId64 ")", ticks, exp_ticks); -} - -ZTEST_SUITE(nrf_grtc_timer, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/drivers/timer/nrf_grtc_timer/testcase.yaml b/tests/drivers/timer/nrf_grtc_timer/testcase.yaml deleted file mode 100644 index 81b320c7c9b..00000000000 --- a/tests/drivers/timer/nrf_grtc_timer/testcase.yaml +++ /dev/null @@ -1,4 +0,0 @@ -tests: - drivers.timer.nrf_grtc_timer: - tags: drivers - platform_allow: nrf54l15pdk_nrf54l15_cpuapp From 39440c28de260fa5330b10924b99501f6135de55 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:08 +0200 Subject: [PATCH 2163/2402] Revert "[nrf noup] samples: psa_crypto: Remove support for Nordic boards" This reverts commit 74b659fb11b82a2009d3dcde331f4b01eb7dcfe4. Signed-off-by: Gerard Marull-Paretas --- samples/tfm_integration/psa_crypto/sample.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/samples/tfm_integration/psa_crypto/sample.yaml b/samples/tfm_integration/psa_crypto/sample.yaml index b368f289e8c..45c9940b021 100644 --- a/samples/tfm_integration/psa_crypto/sample.yaml +++ b/samples/tfm_integration/psa_crypto/sample.yaml @@ -12,6 +12,7 @@ tests: - csr - mcuboot platform_allow: mps2_an521_ns v2m_musca_s1_ns + nrf5340dk_nrf5340_cpuapp_ns nrf9160dk_nrf9160_ns stm32l562e_dk_ns bl5340_dvk_cpuapp_ns harness: console harness_config: From 318305e31e075cdc8e0210641c44221b20d6a8ae Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:08 +0200 Subject: [PATCH 2164/2402] Revert "[nrf fromlist] tests: drivers: spi: spi_slave: Add nrf54h20dk" This reverts commit a49a583e33618d906e0be2b1da2525fe47ece5df. Signed-off-by: Gerard Marull-Paretas --- .../boards/nrf54h20dk_nrf54h20_common.dtsi | 79 ------------------- .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 14 ---- .../boards/nrf54h20dk_nrf54h20_cpurad.overlay | 14 ---- tests/drivers/spi/spi_slave/src/main.c | 1 - tests/drivers/spi/spi_slave/testcase.yaml | 4 +- 5 files changed, 1 insertion(+), 111 deletions(-) delete mode 100644 tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_common.dtsi delete mode 100644 tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay delete mode 100644 tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpurad.overlay diff --git a/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_common.dtsi deleted file mode 100644 index 0a9425cc2f9..00000000000 --- a/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_common.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - spi130_default_alt: spi130_default_alt { - group1 { - psels = , - , - ; - }; - }; - - spi130_sleep_alt: spi130_sleep_alt { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; - - spis131_default_alt: spis131_default_alt { - group1 { - psels = , - , - , - ; - }; - }; - - spis131_sleep_alt: spis131_sleep_alt { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; - -}; - -&gpio0 { - status = "okay"; -}; - -&gpiote130 { - status = "okay"; - owned-channels = <7>; -}; - -dut_spi: &spi130 { - compatible = "nordic,nrf-spim"; - status = "okay"; - pinctrl-0 = <&spi130_default_alt>; - pinctrl-1 = <&spi130_sleep_alt>; - pinctrl-names = "default", "sleep"; - overrun-character = <0x00>; - cs-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - dut_spi_dt: test-spi-dev@0 { - compatible = "vnd,spi-device"; - reg = <0>; - spi-max-frequency = <500000>; - }; -}; - -dut_spis: &spi131 { - compatible = "nordic,nrf-spis"; - status = "okay"; - def-char = <0x00>; - pinctrl-0 = <&spis131_default_alt>; - pinctrl-1 = <&spis131_sleep_alt>; - pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; -}; diff --git a/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay deleted file mode 100644 index ff337ebdec4..00000000000 --- a/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "nrf54h20dk_nrf54h20_common.dtsi" - -&dut_spi { - memory-regions = <&cpuapp_dma_region>; -}; - -&dut_spis { - memory-regions = <&cpuapp_dma_region>; -}; diff --git a/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpurad.overlay deleted file mode 100644 index 936bd5b15d5..00000000000 --- a/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpurad.overlay +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "nrf54h20dk_nrf54h20_common.dtsi" - -&dut_spi { - memory-regions = <&cpurad_dma_region>; -}; - -&dut_spis { - memory-regions = <&cpurad_dma_region>; -}; diff --git a/tests/drivers/spi/spi_slave/src/main.c b/tests/drivers/spi/spi_slave/src/main.c index 5f441480c12..7a6ca1b7545 100644 --- a/tests/drivers/spi/spi_slave/src/main.c +++ b/tests/drivers/spi/spi_slave/src/main.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #define SPI_MODE (SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_LINES_SINGLE) diff --git a/tests/drivers/spi/spi_slave/testcase.yaml b/tests/drivers/spi/spi_slave/testcase.yaml index 2ad23f25d4f..9f04af801fd 100644 --- a/tests/drivers/spi/spi_slave/testcase.yaml +++ b/tests/drivers/spi/spi_slave/testcase.yaml @@ -5,8 +5,6 @@ tests: harness: ztest harness_config: fixture: gpio_spi_loopback - platform_allow: | - nrf52840dk_nrf52840 nrf54l15pdk_nrf54l15_cpuapp nrf54h20dk_nrf54h20_cpuapp - nrf54h20dk_nrf54h20_cpurad + platform_allow: nrf52840dk_nrf52840 nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf52840dk_nrf52840 From 52dfba36a96e2ff82baad83f02b1476bb5d71901 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:08 +0200 Subject: [PATCH 2165/2402] Revert "[nrf fromtree] tests: drivers: spi: spi_loopback_test: Add nrf54h20dk" This reverts commit cd31de02bd74e486bed493f3f78d980774717b2e. Signed-off-by: Gerard Marull-Paretas --- .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 43 ------------------- 1 file changed, 43 deletions(-) delete mode 100644 tests/drivers/spi/spi_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/spi/spi_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay deleted file mode 100644 index 5ab0e84eeaa..00000000000 --- a/tests/drivers/spi/spi_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - spi130_default: spi130_default { - group1 { - psels = , - , - ; - }; - }; - - spi130_sleep: spi130_sleep { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; -}; - -&spi130 { - status = "okay"; - pinctrl-0 = <&spi130_default>; - pinctrl-1 = <&spi130_sleep>; - pinctrl-names = "default", "sleep"; - overrun-character = <0x00>; - memory-regions = <&cpuapp_dma_region>; - slow@0 { - compatible = "test-spi-loopback-slow"; - reg = <0>; - spi-max-frequency = ; - }; - fast@0 { - compatible = "test-spi-loopback-fast"; - reg = <0>; - spi-max-frequency = ; - }; -}; From 0d4790ce9c4dd2bf97fbbfced0680d4abb63197b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:08 +0200 Subject: [PATCH 2166/2402] Revert "[nrf fromtree] dts: common: nordic: nrf54: Add rx-delay property to SPI" This reverts commit d97636ea3172f524150b152a046eb7388e6cf765. Signed-off-by: Gerard Marull-Paretas --- .../nordic/nrf54l15_cpuapp_peripherals.dtsi | 10 ---------- dts/common/nordic/nrf54h20.dtsi | 20 ------------------- 2 files changed, 30 deletions(-) diff --git a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi index 3e4d3641069..eb161844841 100644 --- a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi +++ b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi @@ -24,8 +24,6 @@ spi00: spi@4a000 { interrupts = <74 NRF_DEFAULT_IRQ_PRIORITY>; max-frequency = ; easydma-maxcnt-bits = <16>; - rx-delay-supported; - rx-delay = <1>; status = "disabled"; }; @@ -126,8 +124,6 @@ spi20: spi@c6000 { interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>; max-frequency = ; easydma-maxcnt-bits = <16>; - rx-delay-supported; - rx-delay = <1>; status = "disabled"; }; @@ -163,8 +159,6 @@ spi21: spi@c7000 { interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>; max-frequency = ; easydma-maxcnt-bits = <16>; - rx-delay-supported; - rx-delay = <1>; status = "disabled"; }; @@ -200,8 +194,6 @@ spi22: spi@c8000 { interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>; max-frequency = ; easydma-maxcnt-bits = <16>; - rx-delay-supported; - rx-delay = <1>; status = "disabled"; }; @@ -399,8 +391,6 @@ spi30: spi@104000 { interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>; max-frequency = ; easydma-maxcnt-bits = <16>; - rx-delay-supported; - rx-delay = <1>; status = "disabled"; }; diff --git a/dts/common/nordic/nrf54h20.dtsi b/dts/common/nordic/nrf54h20.dtsi index d3b6b20188f..ec5c4cca14f 100644 --- a/dts/common/nordic/nrf54h20.dtsi +++ b/dts/common/nordic/nrf54h20.dtsi @@ -362,8 +362,6 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; - rx-delay-supported; - rx-delay = <1>; }; uart120: uart@8e6000 { @@ -382,8 +380,6 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; - rx-delay-supported; - rx-delay = <1>; }; cpuppr_vpr: vpr@908000 { @@ -641,8 +637,6 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; - rx-delay-supported; - rx-delay = <1>; }; uart130: uart@9a5000 { @@ -671,8 +665,6 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; - rx-delay-supported; - rx-delay = <1>; }; uart131: uart@9a6000 { @@ -735,8 +727,6 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; - rx-delay-supported; - rx-delay = <1>; }; uart132: uart@9b5000 { @@ -765,8 +755,6 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; - rx-delay-supported; - rx-delay = <1>; }; uart133: uart@9b6000 { @@ -829,8 +817,6 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; - rx-delay-supported; - rx-delay = <1>; }; uart134: uart@9c5000 { @@ -859,8 +845,6 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; - rx-delay-supported; - rx-delay = <1>; }; uart135: uart@9c6000 { @@ -923,8 +907,6 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; - rx-delay-supported; - rx-delay = <1>; }; uart136: uart@9d5000 { @@ -953,8 +935,6 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; - rx-delay-supported; - rx-delay = <1>; }; uart137: uart@9d6000 { From a0c1c6a1a33df4dae372e76b966aabeb4e8c70e7 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:08 +0200 Subject: [PATCH 2167/2402] Revert "[nrf fromtree] tests: drivers: spi: Add test for SPI master and slave" This reverts commit 476eef81fbd379e162959f0cb32a730fba5c81fa. Signed-off-by: Gerard Marull-Paretas --- tests/drivers/spi/spi_slave/CMakeLists.txt | 10 - .../boards/nrf52840dk_nrf52840.overlay | 67 --- .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 73 --- tests/drivers/spi/spi_slave/prj.conf | 6 - tests/drivers/spi/spi_slave/src/main.c | 452 ------------------ tests/drivers/spi/spi_slave/testcase.yaml | 10 - 6 files changed, 618 deletions(-) delete mode 100644 tests/drivers/spi/spi_slave/CMakeLists.txt delete mode 100644 tests/drivers/spi/spi_slave/boards/nrf52840dk_nrf52840.overlay delete mode 100644 tests/drivers/spi/spi_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay delete mode 100644 tests/drivers/spi/spi_slave/prj.conf delete mode 100644 tests/drivers/spi/spi_slave/src/main.c delete mode 100644 tests/drivers/spi/spi_slave/testcase.yaml diff --git a/tests/drivers/spi/spi_slave/CMakeLists.txt b/tests/drivers/spi/spi_slave/CMakeLists.txt deleted file mode 100644 index f9f7a6bdae4..00000000000 --- a/tests/drivers/spi/spi_slave/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(spi_slave) - -FILE(GLOB app_sources src/*.c) - -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/spi/spi_slave/boards/nrf52840dk_nrf52840.overlay b/tests/drivers/spi/spi_slave/boards/nrf52840dk_nrf52840.overlay deleted file mode 100644 index 477917e0ca7..00000000000 --- a/tests/drivers/spi/spi_slave/boards/nrf52840dk_nrf52840.overlay +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - spi3_default_alt: spi3_default_alt { - group1 { - psels = , - , - ; - }; - }; - - spi3_sleep_alt: spi3_sleep_alt { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; - - spi1_default_alt: spi1_default_alt { - group1 { - psels = , - , - , - ; - }; - }; - - spi1_sleep_alt: spi1_sleep_alt { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; - -}; - -&spi3 { - status = "okay"; - pinctrl-0 = <&spi3_default_alt>; - pinctrl-1 = <&spi3_sleep_alt>; - pinctrl-names = "default", "sleep"; - overrun-character = <0x00>; - cs-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - dut_spi_dt: test-spi-dev@0 { - compatible = "vnd,spi-device"; - reg = <0>; - spi-max-frequency = <4000000>; - }; -}; - -dut_spis: &spi1 { - compatible = "nordic,nrf-spis"; - status = "okay"; - def-char = <0x00>; - pinctrl-0 = <&spi1_default_alt>; - pinctrl-1 = <&spi1_sleep_alt>; - pinctrl-names = "default", "sleep"; -}; diff --git a/tests/drivers/spi/spi_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay deleted file mode 100644 index d431f278337..00000000000 --- a/tests/drivers/spi/spi_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - spi22_default_alt: spi22_default_alt { - group1 { - psels = , - , - ; - }; - }; - - spi22_sleep_alt: spi22_sleep_alt { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; - - spi21_default_alt: spi21_default_alt { - group1 { - psels = , - , - , - ; - }; - }; - - spi21_sleep_alt: spi21_sleep_alt { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; - -}; - -&gpio2 { - status = "okay"; -}; - -&spi22 { - status = "okay"; - pinctrl-0 = <&spi22_default_alt>; - pinctrl-1 = <&spi22_sleep_alt>; - pinctrl-names = "default", "sleep"; - overrun-character = <0x00>; - cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - dut_spi_dt: test-spi-dev@0 { - compatible = "vnd,spi-device"; - reg = <0>; - spi-max-frequency = <4000000>; - }; -}; - -dut_spis: &spi21 { - compatible = "nordic,nrf-spis"; - status = "okay"; - def-char = <0x00>; - pinctrl-0 = <&spi21_default_alt>; - pinctrl-1 = <&spi21_sleep_alt>; - pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; -}; diff --git a/tests/drivers/spi/spi_slave/prj.conf b/tests/drivers/spi/spi_slave/prj.conf deleted file mode 100644 index 840a8f87d9a..00000000000 --- a/tests/drivers/spi/spi_slave/prj.conf +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_SPI=y -CONFIG_SPI_SLAVE=y -CONFIG_GPIO=y -CONFIG_POLL=y -CONFIG_SPI_ASYNC=y -CONFIG_ZTEST=y diff --git a/tests/drivers/spi/spi_slave/src/main.c b/tests/drivers/spi/spi_slave/src/main.c deleted file mode 100644 index 7a6ca1b7545..00000000000 --- a/tests/drivers/spi/spi_slave/src/main.c +++ /dev/null @@ -1,452 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -#define SPI_MODE (SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_LINES_SINGLE) -#define SPIM_OP (SPI_OP_MODE_MASTER | SPI_MODE) -#define SPIS_OP (SPI_OP_MODE_SLAVE | SPI_MODE) - -static struct spi_dt_spec spim = SPI_DT_SPEC_GET(DT_NODELABEL(dut_spi_dt), SPIM_OP, 0); -static const struct device *spis_dev = DEVICE_DT_GET(DT_NODELABEL(dut_spis)); -static const struct spi_config spis_config = { - .operation = SPIS_OP -}; - -static struct k_poll_signal async_sig = K_POLL_SIGNAL_INITIALIZER(async_sig); -static struct k_poll_event async_evt = - K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &async_sig); - -#define MEMORY_SECTION(node) \ - COND_CODE_1(DT_NODE_HAS_PROP(node, memory_regions), \ - (__attribute__((__section__( \ - LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(node, memory_regions)))))), \ - ()) - -static uint8_t spim_buffer[32] MEMORY_SECTION(DT_BUS(DT_NODELABEL(dut_spi_dt))); -static uint8_t spis_buffer[32] MEMORY_SECTION(DT_NODELABEL(dut_spis)); - -struct test_data { - struct k_work_delayable test_work; - struct k_sem sem; - int spim_alloc_idx; - int spis_alloc_idx; - struct spi_buf_set sets[4]; - struct spi_buf_set *mtx_set; - struct spi_buf_set *mrx_set; - struct spi_buf_set *stx_set; - struct spi_buf_set *srx_set; - struct spi_buf bufs[8]; -}; - -static struct test_data tdata; - -/* Allocate buffer from spim or spis space. */ -static uint8_t *buf_alloc(size_t len, bool spim) -{ - int *idx = spim ? &tdata.spim_alloc_idx : &tdata.spis_alloc_idx; - uint8_t *buf = spim ? spim_buffer : spis_buffer; - size_t total = spim ? sizeof(spim_buffer) : sizeof(spis_buffer); - uint8_t *rv; - - if (*idx + len > total) { - zassert_false(true); - - return NULL; - } - - rv = &buf[*idx]; - *idx += len; - - return rv; -} - -static void work_handler(struct k_work *work) -{ - struct k_work_delayable *dwork = k_work_delayable_from_work(work); - struct test_data *td = CONTAINER_OF(dwork, struct test_data, test_work); - int rv; - - rv = spi_transceive_dt(&spim, td->mtx_set, td->mrx_set); - if (rv == 0) { - k_sem_give(&td->sem); - } -} - -/** Copies data from buffers in the set to a single buffer which makes it easier - * to compare transmitted and received data. - * - * @param buf Output buffer. - * @param len Buffer length. - * @param set Set of buffers. - * - * @return Number of bytes copied. - */ -static int cpy_data(uint8_t *buf, size_t len, struct spi_buf_set *set) -{ - int idx = 0; - - for (size_t i = 0; i < set->count; i++) { - size_t l = set->buffers[i].len; - - if (len - idx >= l) { - memcpy(&buf[idx], set->buffers[i].buf, l); - idx += l; - } else { - return -1; - } - } - - return idx; -} - -/** Compare two sets. - * - * @param tx_set TX set. - * @param rx_set RX set. - * @param same_size True if it is expected to have the same amount of data in both sets. - * - * @return 0 if data is the same and other value indicate that check failed. - */ -static int check_buffers(struct spi_buf_set *tx_set, struct spi_buf_set *rx_set, bool same_size) -{ - static uint8_t tx_data[256]; - static uint8_t rx_data[256]; - int rx_len; - int tx_len; - - if (!tx_set || !rx_set) { - return 0; - } - - rx_len = cpy_data(rx_data, sizeof(rx_data), rx_set); - tx_len = cpy_data(tx_data, sizeof(tx_data), tx_set); - if (same_size && (rx_len != tx_len)) { - return -1; - } - - return memcmp(tx_data, rx_data, rx_len); -} - -/** Calculate expected number of received bytes by the slave. - * - * It is used to check if SPI API call for slave returns correct value. - * @param tx_set TX set. - * @param rx_set RX set. - * - * @return Expected amount of received bytes. - */ -static int slave_rx_len(struct spi_buf_set *tx_set, struct spi_buf_set *rx_set) -{ - size_t tx_len = 0; - size_t rx_len = 0; - - if (!tx_set || !rx_set) { - return 0; - } - - for (size_t i = 0; i < tx_set->count; i++) { - tx_len += tx_set->buffers[i].len; - } - - for (size_t i = 0; i < rx_set->count; i++) { - rx_len += rx_set->buffers[i].len; - } - - return MIN(rx_len, tx_len); -} - -/** Generic function which runs the test with sets prepared in the test data structure. */ -static void run_test(bool m_same_size, bool s_same_size, bool async) -{ - int rv; - int slave_rv; - int srx_len; - - rv = k_work_schedule(&tdata.test_work, K_MSEC(10)); - zassert_equal(rv, 1); - - if (!async) { - slave_rv = spi_transceive(spis_dev, &spis_config, tdata.stx_set, tdata.srx_set); - if (slave_rv == -ENOTSUP) { - ztest_test_skip(); - } - } else { - rv = spi_transceive_signal(spis_dev, &spis_config, tdata.stx_set, tdata.srx_set, - &async_sig); - if (rv == -ENOTSUP) { - ztest_test_skip(); - } - zassert_equal(rv, 0); - - /* Transfer not finished yet */ - rv = k_sem_take(&tdata.sem, K_NO_WAIT); - zassert_equal(rv, -EBUSY); - - rv = k_poll(&async_evt, 1, K_MSEC(200)); - zassert_false(rv, "one or more events are not ready"); - - slave_rv = async_evt.signal->result; - - /* Reinitializing for next call */ - async_evt.signal->signaled = 0U; - async_evt.state = K_POLL_STATE_NOT_READY; - } - - rv = k_sem_take(&tdata.sem, K_MSEC(100)); - zassert_equal(rv, 0); - - srx_len = slave_rx_len(tdata.mtx_set, tdata.srx_set); - - zassert_equal(slave_rv, srx_len, "Got: %d but expected:%d", slave_rv, srx_len); - - rv = check_buffers(tdata.mtx_set, tdata.srx_set, m_same_size); - zassert_equal(rv, 0); - - rv = check_buffers(tdata.stx_set, tdata.mrx_set, s_same_size); - zassert_equal(rv, 0); -} - -/** Basic test where slave and master have RX and TX sets which contains only one - * same size buffer. - */ -static void test_basic(bool async) -{ - size_t len = 16; - - for (int i = 0; i < 4; i++) { - tdata.bufs[i].buf = buf_alloc(len, i < 2); - tdata.bufs[i].len = len; - tdata.sets[i].buffers = &tdata.bufs[i]; - tdata.sets[i].count = 1; - } - - tdata.mtx_set = &tdata.sets[0]; - tdata.mrx_set = &tdata.sets[1]; - tdata.stx_set = &tdata.sets[2]; - tdata.srx_set = &tdata.sets[3]; - - run_test(true, true, async); -} - -ZTEST(spi_slave, test_basic) -{ - test_basic(false); -} - -ZTEST(spi_slave, test_basic_async) -{ - test_basic(true); -} - -/** Setup a transfer where RX buffer on master and slave are shorter than - * TX buffers. RX buffers shall contain beginning of TX data and last TX - * bytes that did not fit in the RX buffers shall be lost. - */ -static void test_short_rx(bool async) -{ - size_t len = 16; - - tdata.bufs[0].buf = buf_alloc(len, true); - tdata.bufs[0].len = len; - tdata.bufs[1].buf = buf_alloc(len, true); - tdata.bufs[1].len = len - 3; /* RX buffer */ - tdata.bufs[2].buf = buf_alloc(len, false); - tdata.bufs[2].len = len; - tdata.bufs[3].buf = buf_alloc(len, false); - tdata.bufs[3].len = len - 4; /* RX buffer */ - - for (int i = 0; i < 4; i++) { - tdata.sets[i].buffers = &tdata.bufs[i]; - tdata.sets[i].count = 1; - } - - tdata.mtx_set = &tdata.sets[0]; - tdata.mrx_set = &tdata.sets[1]; - tdata.stx_set = &tdata.sets[2]; - tdata.srx_set = &tdata.sets[3]; - - run_test(false, false, async); -} - -ZTEST(spi_slave, test_short_rx) -{ - test_short_rx(false); -} - -ZTEST(spi_slave, test_short_rx_async) -{ - test_short_rx(true); -} - -/** Test where only master transmits. */ -static void test_only_tx(bool async) -{ - size_t len = 16; - - /* MTX buffer */ - tdata.bufs[0].buf = buf_alloc(len, true); - tdata.bufs[0].len = len; - tdata.sets[0].buffers = &tdata.bufs[0]; - tdata.sets[0].count = 1; - tdata.mtx_set = &tdata.sets[0]; - tdata.mrx_set = NULL; - - /* STX buffer */ - tdata.bufs[1].buf = buf_alloc(len, false); - tdata.bufs[1].len = len; - tdata.sets[1].buffers = &tdata.bufs[1]; - tdata.sets[1].count = 1; - tdata.srx_set = &tdata.sets[1]; - tdata.stx_set = NULL; - - run_test(true, true, async); -} - -ZTEST(spi_slave, test_only_tx) -{ - test_only_tx(false); -} - -ZTEST(spi_slave, test_only_tx_async) -{ - test_only_tx(true); -} - -/** Test where only master transmits and slave receives in chunks. */ -static void test_only_tx_in_chunks(bool async) -{ - size_t len1 = 7; - size_t len2 = 8; - - /* MTX buffer */ - tdata.bufs[0].buf = buf_alloc(len1 + len2, true); - tdata.bufs[0].len = len1 + len2; - tdata.sets[0].buffers = &tdata.bufs[0]; - tdata.sets[0].count = 1; - tdata.mtx_set = &tdata.sets[0]; - tdata.mrx_set = NULL; - - /* STX buffer */ - tdata.bufs[1].buf = buf_alloc(len1, false); - tdata.bufs[1].len = len1; - tdata.bufs[2].buf = buf_alloc(len2, false); - tdata.bufs[2].len = len2; - tdata.sets[1].buffers = &tdata.bufs[1]; - tdata.sets[1].count = 2; - tdata.srx_set = &tdata.sets[1]; - tdata.stx_set = NULL; - - run_test(true, true, async); -} - -ZTEST(spi_slave, test_only_tx_in_chunks) -{ - test_only_tx_in_chunks(false); -} - -ZTEST(spi_slave, test_only_tx_in_chunks_async) -{ - test_only_tx_in_chunks(true); -} - -/** Test where only slave transmits. */ -static void test_only_rx(bool async) -{ - size_t len = 16; - - /* MTX buffer */ - tdata.bufs[0].buf = buf_alloc(len, true); - tdata.bufs[0].len = len; - tdata.sets[0].buffers = &tdata.bufs[0]; - tdata.sets[0].count = 1; - tdata.mrx_set = &tdata.sets[0]; - tdata.mtx_set = NULL; - - /* STX buffer */ - tdata.bufs[1].buf = buf_alloc(len, false); - tdata.bufs[1].len = len; - tdata.sets[1].buffers = &tdata.bufs[1]; - tdata.sets[1].count = 1; - tdata.stx_set = &tdata.sets[1]; - tdata.srx_set = NULL; - - run_test(true, true, async); -} - -ZTEST(spi_slave, test_only_rx) -{ - test_only_rx(false); -} - -ZTEST(spi_slave, test_only_rx_async) -{ - test_only_rx(true); -} - -/** Test where only slave transmits in chunks. */ -static void test_only_rx_in_chunks(bool async) -{ - size_t len1 = 7; - size_t len2 = 9; - - /* MTX buffer */ - tdata.bufs[0].buf = buf_alloc(len1 + len2, true); - tdata.bufs[0].len = len1 + len2; - tdata.sets[0].buffers = &tdata.bufs[0]; - tdata.sets[0].count = 1; - tdata.mrx_set = &tdata.sets[0]; - tdata.mtx_set = NULL; - - /* STX buffer */ - tdata.bufs[1].buf = buf_alloc(len1, false); - tdata.bufs[1].len = len1; - tdata.bufs[2].buf = buf_alloc(len2, false); - tdata.bufs[2].len = len2; - tdata.sets[1].buffers = &tdata.bufs[1]; - tdata.sets[1].count = 2; - tdata.stx_set = &tdata.sets[1]; - tdata.srx_set = NULL; - - run_test(true, true, async); -} - -ZTEST(spi_slave, test_only_rx_in_chunks) -{ - test_only_rx_in_chunks(false); -} - -ZTEST(spi_slave, test_only_rx_in_chunks_async) -{ - test_only_rx_in_chunks(true); -} - -static void before(void *not_used) -{ - ARG_UNUSED(not_used); - - memset(&tdata, 0, sizeof(tdata)); - for (size_t i = 0; i < sizeof(spim_buffer); i++) { - spim_buffer[i] = (uint8_t)i; - } - for (size_t i = 0; i < sizeof(spis_buffer); i++) { - spis_buffer[i] = (uint8_t)(i + 0x80); - } - - k_work_init_delayable(&tdata.test_work, work_handler); - k_sem_init(&tdata.sem, 0, 1); -} - -static void *suite_setup(void) -{ - return NULL; -} - -ZTEST_SUITE(spi_slave, NULL, suite_setup, before, NULL, NULL); diff --git a/tests/drivers/spi/spi_slave/testcase.yaml b/tests/drivers/spi/spi_slave/testcase.yaml deleted file mode 100644 index 9f04af801fd..00000000000 --- a/tests/drivers/spi/spi_slave/testcase.yaml +++ /dev/null @@ -1,10 +0,0 @@ -tests: - drivers.spi_slave.api: - depends_on: spi - tags: drivers spi - harness: ztest - harness_config: - fixture: gpio_spi_loopback - platform_allow: nrf52840dk_nrf52840 nrf54l15pdk_nrf54l15_cpuapp - integration_platforms: - - nrf52840dk_nrf52840 From 0a8ca5995f3333b89866bed7d1ddd9328386c3aa Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:09 +0200 Subject: [PATCH 2168/2402] Revert "[nrf fromtree] drivers: spi: nrf: Add new SPIS instances" This reverts commit 2e476d935ea60e644e221327806fd2d539734c9e. Signed-off-by: Gerard Marull-Paretas --- drivers/spi/Kconfig.nrfx | 14 ----- drivers/spi/spi_nrfx_spis.c | 19 ++++-- modules/hal_nordic/nrfx/Kconfig | 70 ----------------------- modules/hal_nordic/nrfx/nrfx_config.h | 42 -------------- soc/common/nordic_nrf/Kconfig.peripherals | 42 -------------- 5 files changed, 14 insertions(+), 173 deletions(-) diff --git a/drivers/spi/Kconfig.nrfx b/drivers/spi/Kconfig.nrfx index 870730769fa..0ee1c03065b 100644 --- a/drivers/spi/Kconfig.nrfx +++ b/drivers/spi/Kconfig.nrfx @@ -51,20 +51,6 @@ config SPI_NRFX_SPIS select NRFX_SPIS1 if HAS_HW_NRF_SPIS1 select NRFX_SPIS2 if HAS_HW_NRF_SPIS2 select NRFX_SPIS3 if HAS_HW_NRF_SPIS3 - select NRFX_SPIS00 if HAS_HW_NRF_SPIS00 - select NRFX_SPIS20 if HAS_HW_NRF_SPIS20 - select NRFX_SPIS21 if HAS_HW_NRF_SPIS21 - select NRFX_SPIS22 if HAS_HW_NRF_SPIS22 - select NRFX_SPIS30 if HAS_HW_NRF_SPIS30 - select NRFX_SPIS120 if HAS_HW_NRF_SPIS120 - select NRFX_SPIS130 if HAS_HW_NRF_SPIS130 - select NRFX_SPIS131 if HAS_HW_NRF_SPIS131 - select NRFX_SPIS132 if HAS_HW_NRF_SPIS132 - select NRFX_SPIS133 if HAS_HW_NRF_SPIS133 - select NRFX_SPIS134 if HAS_HW_NRF_SPIS134 - select NRFX_SPIS135 if HAS_HW_NRF_SPIS135 - select NRFX_SPIS136 if HAS_HW_NRF_SPIS136 - select NRFX_SPIS137 if HAS_HW_NRF_SPIS137 config SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 depends on SOC_NRF52832 diff --git a/drivers/spi/spi_nrfx_spis.c b/drivers/spi/spi_nrfx_spis.c index 78bcc9f84be..d2a61530f00 100644 --- a/drivers/spi/spi_nrfx_spis.c +++ b/drivers/spi/spi_nrfx_spis.c @@ -399,9 +399,18 @@ static int spi_nrfx_init(const struct device *dev) CONFIG_SPI_INIT_PRIORITY, \ &spi_nrfx_driver_api) -/* Macro creates device instance if it is enabled in devicetree. */ -#define SPIS_DEVICE(periph, prefix, id, _) \ - IF_ENABLED(CONFIG_HAS_HW_NRF_SPIS##prefix##id, (SPI_NRFX_SPIS_DEFINE(prefix##id);)) +#ifdef CONFIG_HAS_HW_NRF_SPIS0 +SPI_NRFX_SPIS_DEFINE(0); +#endif + +#ifdef CONFIG_HAS_HW_NRF_SPIS1 +SPI_NRFX_SPIS_DEFINE(1); +#endif -/* Macro iterates over nrfx_spis instances enabled in the nrfx_config.h. */ -NRFX_FOREACH_ENABLED(SPIS, SPIS_DEVICE, (), (), _) +#ifdef CONFIG_HAS_HW_NRF_SPIS2 +SPI_NRFX_SPIS_DEFINE(2); +#endif + +#ifdef CONFIG_HAS_HW_NRF_SPIS3 +SPI_NRFX_SPIS_DEFINE(3); +#endif diff --git a/modules/hal_nordic/nrfx/Kconfig b/modules/hal_nordic/nrfx/Kconfig index 32386d54274..22758742ef4 100644 --- a/modules/hal_nordic/nrfx/Kconfig +++ b/modules/hal_nordic/nrfx/Kconfig @@ -441,76 +441,6 @@ config NRFX_SPIS3 depends on $(dt_nodelabel_has_compat,spi3,$(DT_COMPAT_NORDIC_NRF_SPIS)) select NRFX_SPIS -config NRFX_SPIS00 - bool "SPIS00 driver instance" - depends on $(dt_nodelabel_has_compat,spi00,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS20 - bool "SPIS20 driver instance" - depends on $(dt_nodelabel_has_compat,spi20,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS21 - bool "SPIS21 driver instance" - depends on $(dt_nodelabel_has_compat,spi21,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS22 - bool "SPIS22 driver instance" - depends on $(dt_nodelabel_has_compat,spi22,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS30 - bool "SPIS30 driver instance" - depends on $(dt_nodelabel_has_compat,spi30,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS120 - bool "SPIS120 driver instance" - depends on $(dt_nodelabel_has_compat,spi120,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS130 - bool "SPIS130 driver instance" - depends on $(dt_nodelabel_has_compat,spi130,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS131 - bool "SPIS131 driver instance" - depends on $(dt_nodelabel_has_compat,spi131,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS132 - bool "SPIS132 driver instance" - depends on $(dt_nodelabel_has_compat,spi132,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS133 - bool "SPIS133 driver instance" - depends on $(dt_nodelabel_has_compat,spi133,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS134 - bool "SPIS134 driver instance" - depends on $(dt_nodelabel_has_compat,spi134,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS135 - bool "SPIS135 driver instance" - depends on $(dt_nodelabel_has_compat,spi135,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS136 - bool "SPIS136 driver instance" - depends on $(dt_nodelabel_has_compat,spi136,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - -config NRFX_SPIS137 - bool "SPIS137 driver instance" - depends on $(dt_nodelabel_has_compat,spi137,$(DT_COMPAT_NORDIC_NRF_SPIS)) - select NRFX_SPIS - config NRFX_SYSTICK bool "SYSTICK driver" depends on CPU_CORTEX_M_HAS_SYSTICK diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index e7120b54ab7..4a7ae346d84 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -451,48 +451,6 @@ #ifdef CONFIG_NRFX_SPIS3 #define NRFX_SPIS3_ENABLED 1 #endif -#ifdef CONFIG_NRFX_SPIS00 -#define NRFX_SPIS00_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS20 -#define NRFX_SPIS20_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS21 -#define NRFX_SPIS21_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS22 -#define NRFX_SPIS22_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS30 -#define NRFX_SPIS30_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS120 -#define NRFX_SPIS120_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS130 -#define NRFX_SPIS130_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS131 -#define NRFX_SPIS131_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS132 -#define NRFX_SPIS132_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS133 -#define NRFX_SPIS133_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS134 -#define NRFX_SPIS134_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS135 -#define NRFX_SPIS135_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS136 -#define NRFX_SPIS136_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_SPIS137 -#define NRFX_SPIS130_ENABLED 1 -#endif #ifdef CONFIG_NRFX_SYSTICK #define NRFX_SYSTICK_ENABLED 1 diff --git a/soc/common/nordic_nrf/Kconfig.peripherals b/soc/common/nordic_nrf/Kconfig.peripherals index 817002f7282..e10ddb42d20 100644 --- a/soc/common/nordic_nrf/Kconfig.peripherals +++ b/soc/common/nordic_nrf/Kconfig.peripherals @@ -320,48 +320,6 @@ config HAS_HW_NRF_SPIS2 config HAS_HW_NRF_SPIS3 def_bool $(dt_nodelabel_enabled_with_compat,spi3,$(DT_COMPAT_NORDIC_NRF_SPIS)) -config HAS_HW_NRF_SPIS00 - def_bool $(dt_nodelabel_enabled_with_compat,spi00,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS20 - def_bool $(dt_nodelabel_enabled_with_compat,spi20,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS21 - def_bool $(dt_nodelabel_enabled_with_compat,spi21,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS22 - def_bool $(dt_nodelabel_enabled_with_compat,spi22,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS30 - def_bool $(dt_nodelabel_enabled_with_compat,spi30,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS120 - def_bool $(dt_nodelabel_enabled_with_compat,spi120,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS130 - def_bool $(dt_nodelabel_enabled_with_compat,spi130,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS131 - def_bool $(dt_nodelabel_enabled_with_compat,spi131,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS132 - def_bool $(dt_nodelabel_enabled_with_compat,spi132,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS133 - def_bool $(dt_nodelabel_enabled_with_compat,spi133,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS134 - def_bool $(dt_nodelabel_enabled_with_compat,spi134,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS135 - def_bool $(dt_nodelabel_enabled_with_compat,spi135,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS136 - def_bool $(dt_nodelabel_enabled_with_compat,spi136,$(DT_COMPAT_NORDIC_NRF_SPIS)) - -config HAS_HW_NRF_SPIS137 - def_bool $(dt_nodelabel_enabled_with_compat,spi137,$(DT_COMPAT_NORDIC_NRF_SPIS)) - config HAS_HW_NRF_SPU def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_SPU)) From 464d3c8bbbd57245807ee5fbd3cbe0f5a21fcd2e Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:09 +0200 Subject: [PATCH 2169/2402] Revert "[nrf fromlist] tests: drivers: uart: uart_elementary: Fix mismatch case" This reverts commit 42762514e253fb37aa803294018943dfdd367a9d. Signed-off-by: Gerard Marull-Paretas --- tests/drivers/uart/uart_elementary/src/main.c | 15 +++++++-------- tests/drivers/uart/uart_elementary/testcase.yaml | 8 -------- 2 files changed, 7 insertions(+), 16 deletions(-) diff --git a/tests/drivers/uart/uart_elementary/src/main.c b/tests/drivers/uart/uart_elementary/src/main.c index df8c7b54b10..1c4df3273a7 100644 --- a/tests/drivers/uart/uart_elementary/src/main.c +++ b/tests/drivers/uart/uart_elementary/src/main.c @@ -40,7 +40,6 @@ static volatile uint8_t uart_error_counter; static const struct device *const uart_dev_aux = DEVICE_DT_GET(UART_NODE_AUX); static uint8_t test_buffer_aux[TEST_BUFFER_LEN]; static volatile uint8_t aux_uart_error; -static volatile uint8_t aux_uart_error_counter; #endif /* @@ -111,9 +110,12 @@ static void interrupt_driven_uart_callback_aux_uart(const struct device *dev, vo uart_irq_update(dev); err = uart_err_check(dev); - if (err != 0) { - aux_uart_error_counter++; - } +#if !defined(CONFIG_COVERAGE) + /* This assetion will fail with coverge enabled + * When in coverage mode it has no impact on test case execution + */ + zassert_equal(err, 0, "Unexpected UART device: %s error: %d", dev->name, err); +#endif /* CONFIG_COVERAGE */ while (uart_irq_is_pending(dev)) { if (uart_irq_rx_ready(dev)) { uart_rx_interrupt_service(dev, (uint8_t *)user_data, &rx_byte_offset_aux); @@ -288,10 +290,7 @@ ZTEST(uart_elementary, test_uart_dual_port_transmission) uart_irq_err_disable(uart_dev_aux); #if defined(CONFIG_SETUP_MISMATCH_TEST) - TC_PRINT("Mismatched configuration test\n"); - zassert_not_equal(uart_error_counter + aux_uart_error_counter, 0, - "UART configuration mismatch error not detected"); - + zassert_not_equal(uart_error_counter, 0); #else for (int index = 0; index < TEST_BUFFER_LEN; index++) { zassert_equal(test_buffer[index], test_pattern[index], diff --git a/tests/drivers/uart/uart_elementary/testcase.yaml b/tests/drivers/uart/uart_elementary/testcase.yaml index 67ac04fc1d6..9308ffbf5c2 100644 --- a/tests/drivers/uart/uart_elementary/testcase.yaml +++ b/tests/drivers/uart/uart_elementary/testcase.yaml @@ -33,11 +33,3 @@ tests: extra_args: DTC_OVERLAY_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay" extra_configs: - CONFIG_DUAL_UART_TEST=y - drivers.uart.uart_elementary_dual_setup_mismatch_nrf54l: - filter: CONFIG_SERIAL_SUPPORT_INTERRUPT - platform_allow: - - nrf54l15pdk_nrf54l15_cpuapp - extra_args: DTC_OVERLAY_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay" - extra_configs: - - CONFIG_DUAL_UART_TEST=y - - CONFIG_SETUP_MISMATCH_TEST=y From a8dc208b932ac225ccf52f6c9ad7df99bfd14c21 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:09 +0200 Subject: [PATCH 2170/2402] Revert "[nrf fromlist] tests: drivers: uart: uart_elementary: Fix RX handling" This reverts commit 1fffbd9a5fce282301542ddcfa7255c495af9bd4. Signed-off-by: Gerard Marull-Paretas --- tests/drivers/uart/uart_elementary/src/main.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/drivers/uart/uart_elementary/src/main.c b/tests/drivers/uart/uart_elementary/src/main.c index 1c4df3273a7..d7d85ee9542 100644 --- a/tests/drivers/uart/uart_elementary/src/main.c +++ b/tests/drivers/uart/uart_elementary/src/main.c @@ -66,12 +66,14 @@ static void uart_rx_interrupt_service(const struct device *dev, uint8_t *receive int *rx_byte_offset) { int rx_data_length = 0; + int bytes_received = 0; do { rx_data_length = uart_fifo_read(dev, receive_buffer_pointer + *rx_byte_offset, TEST_BUFFER_LEN); - *rx_byte_offset += rx_data_length; + bytes_received += rx_data_length; } while (rx_data_length); + *rx_byte_offset += bytes_received; } /* From 98b892bea503a36c30bf7a157fe795929df9b145 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:09 +0200 Subject: [PATCH 2171/2402] Revert "[nrf fromtree] drivers: Extend coverage for UARTE driver" This reverts commit 117bb08c370f38d02bba10e0838f588acf19a0ab. Signed-off-by: Gerard Marull-Paretas --- .../uart/uart_elementary/CMakeLists.txt | 10 - tests/drivers/uart/uart_elementary/Kconfig | 11 - tests/drivers/uart/uart_elementary/README.txt | 13 - .../boards/nrf5340dk_nrf5340_cpuapp.conf | 1 - .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 32 -- .../boards/nrf54h20dk_nrf54h20_common.dtsi | 37 -- .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 3 - ...f54h20dk_nrf54h20_cpuapp_dual_uart.overlay | 56 --- .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 31 -- ...54l15pdk_nrf54l15_cpuapp_dual_uart.overlay | 51 --- tests/drivers/uart/uart_elementary/prj.conf | 6 - tests/drivers/uart/uart_elementary/src/main.c | 322 ------------------ .../uart/uart_elementary/testcase.yaml | 35 -- 13 files changed, 608 deletions(-) delete mode 100644 tests/drivers/uart/uart_elementary/CMakeLists.txt delete mode 100644 tests/drivers/uart/uart_elementary/Kconfig delete mode 100644 tests/drivers/uart/uart_elementary/README.txt delete mode 100644 tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.conf delete mode 100644 tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.overlay delete mode 100644 tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi delete mode 100644 tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp.overlay delete mode 100644 tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay delete mode 100644 tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay delete mode 100644 tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay delete mode 100644 tests/drivers/uart/uart_elementary/prj.conf delete mode 100644 tests/drivers/uart/uart_elementary/src/main.c delete mode 100644 tests/drivers/uart/uart_elementary/testcase.yaml diff --git a/tests/drivers/uart/uart_elementary/CMakeLists.txt b/tests/drivers/uart/uart_elementary/CMakeLists.txt deleted file mode 100644 index 59b31ee68a9..00000000000 --- a/tests/drivers/uart/uart_elementary/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(uart_high_level_api) - -target_sources(app PRIVATE - src/main.c - ) diff --git a/tests/drivers/uart/uart_elementary/Kconfig b/tests/drivers/uart/uart_elementary/Kconfig deleted file mode 100644 index aed523c5832..00000000000 --- a/tests/drivers/uart/uart_elementary/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -# UART test configuration options -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config DUAL_UART_TEST - bool "Enable dual UART test" - -config SETUP_MISMATCH_TEST - bool "Enable mismatched configuration in dual UART test" - -source "Kconfig.zephyr" diff --git a/tests/drivers/uart/uart_elementary/README.txt b/tests/drivers/uart/uart_elementary/README.txt deleted file mode 100644 index 5af85beff46..00000000000 --- a/tests/drivers/uart/uart_elementary/README.txt +++ /dev/null @@ -1,13 +0,0 @@ -The purpose of this test is to validate basic UART driver functions, -that are not tested elsewhere. -UART interrupt mode is used for the tests purpose. - -Hardware setup required for these tests: -For single uart conviguration - UART0 TX connected to RX and CTS to RTS -For dual uart configuratiom - UART0 and UART1 TXs and RXs cross-connected - -These test cases cover: -- UART configuration, -- UART error check, -- UART callback setup, -- Dual UART transmission with matched and mismatched configurations diff --git a/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.conf b/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.conf deleted file mode 100644 index 064e78b6f74..00000000000 --- a/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=n diff --git a/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.overlay deleted file mode 100644 index f98f3657f13..00000000000 --- a/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -&pinctrl { - uart1_default_alt: uart1_default_alt { - group1 { - psels = , - , - , - ; - }; - }; - - uart1_sleep_alt: uart1_sleep_alt { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; -}; - -dut: &uart1 { - current-speed = <115200>; - compatible = "nordic,nrf-uarte"; - status = "okay"; - pinctrl-0 = <&uart1_default_alt>; - pinctrl-1 = <&uart1_sleep_alt>; - pinctrl-names = "default", "sleep"; - hw-flow-control; -}; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi deleted file mode 100644 index 22d8378937c..00000000000 --- a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -&cpuapp_dma_region { - status="okay"; -}; - -&pinctrl { - uart135_default_alt: uart135_default_alt { - group1 { - psels = , - , - , - ; - }; - }; - - uart135_sleep_alt: uart135_sleep_alt { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; -}; - -dut: &uart135 { - status = "okay"; - memory-regions = <&cpuapp_dma_region>; - pinctrl-0 = <&uart135_default_alt>; - pinctrl-1 = <&uart135_sleep_alt>; - pinctrl-names = "default", "sleep"; - current-speed = <115200>; - hw-flow-control; - -}; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp.overlay deleted file mode 100644 index f65b4dd3b0b..00000000000 --- a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include "nrf54h20dk_nrf54h20_common.dtsi" diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay deleted file mode 100644 index 23c36ee8974..00000000000 --- a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include "nrf54h20dk_nrf54h20_common.dtsi" - - -&pinctrl { - uart135_default_alt: uart135_default_alt { - group1 { - psels = , - ; - }; - }; - - uart135_sleep_alt: uart135_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; -}; - -dut: &uart135 { - status = "okay"; - memory-regions = <&cpuapp_dma_region>; - pinctrl-0 = <&uart135_default_alt>; - pinctrl-1 = <&uart135_sleep_alt>; - pinctrl-names = "default", "sleep"; - current-speed = <115200>; -}; - -&pinctrl { - uart137_default_alt: uart137_default_alt { - group1 { - psels = , - ; - }; - }; - - uart137_sleep_alt: uart137_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; -}; - -dut_aux: &uart137 { - status = "okay"; - memory-regions = <&cpuapp_dma_region>; - pinctrl-0 = <&uart137_default_alt>; - pinctrl-1 = <&uart137_sleep_alt>; - pinctrl-names = "default", "sleep"; - current-speed = <115200>; -}; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay deleted file mode 100644 index cf481b7a161..00000000000 --- a/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -&pinctrl { - uart21_default: uart21_default { - group1 { - psels = , - , - , - ; - }; - }; - - uart21_sleep: uart21_sleep { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; -}; - -dut: &uart21 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart21_default>; - pinctrl-1 = <&uart21_sleep>; - pinctrl-names = "default", "sleep"; - hw-flow-control; -}; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay deleted file mode 100644 index 2031f7a2444..00000000000 --- a/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -&pinctrl { - uart21_default: uart21_default { - group1 { - psels = , - ; - bias-pull-up; - }; - }; - - uart21_sleep: uart21_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - - uart22_default: uart22_default { - group1 { - psels = , - ; - bias-pull-up; - }; - }; - - uart22_sleep: uart22_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; -}; - -dut: &uart21 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart21_default>; - pinctrl-1 = <&uart21_sleep>; - pinctrl-names = "default", "sleep"; -}; - -dut_aux: &uart22 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart22_default>; - pinctrl-1 = <&uart22_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/tests/drivers/uart/uart_elementary/prj.conf b/tests/drivers/uart/uart_elementary/prj.conf deleted file mode 100644 index 26c93d320a7..00000000000 --- a/tests/drivers/uart/uart_elementary/prj.conf +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_SERIAL=y -CONFIG_ZTEST=y -CONFIG_TEST_USERSPACE=y -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_UART_USE_RUNTIME_CONFIGURE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/tests/drivers/uart/uart_elementary/src/main.c b/tests/drivers/uart/uart_elementary/src/main.c deleted file mode 100644 index d7d85ee9542..00000000000 --- a/tests/drivers/uart/uart_elementary/src/main.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @addtogroup t_driver_uart - * @{ - * @defgroup t_uart_elementary test_uart_elementary - * @} - */ - -#include -#include - -#if DT_NODE_EXISTS(DT_NODELABEL(dut)) -#define UART_NODE DT_NODELABEL(dut) -#else -#define UART_NODE DT_CHOSEN(zephyr_console) -#endif - -#if DT_NODE_EXISTS(DT_NODELABEL(dut_aux)) -#define UART_NODE_AUX DT_NODELABEL(dut_aux) -#else -#define UART_NODE_AUX DT_CHOSEN(zephyr_console) -#endif - -#define SLEEP_TIME_US 1000 -#define TEST_BUFFER_LEN 10 - -static const struct device *const uart_dev = DEVICE_DT_GET(UART_NODE); - -const uint8_t test_pattern[TEST_BUFFER_LEN] = { 0x11, 0x12, 0x13, 0x14, 0x15, - 0x16, 0x17, 0x18, 0x19, 0x20 }; -static uint8_t test_buffer[TEST_BUFFER_LEN]; -static volatile uint8_t uart_error_counter; - -#if defined(CONFIG_DUAL_UART_TEST) -static const struct device *const uart_dev_aux = DEVICE_DT_GET(UART_NODE_AUX); -static uint8_t test_buffer_aux[TEST_BUFFER_LEN]; -static volatile uint8_t aux_uart_error; -#endif - -/* - * ISR for UART TX action - */ -static void uart_tx_interrupt_service(const struct device *dev, int *tx_byte_offset) -{ - uint8_t bytes_sent = 0; - uint8_t *tx_data_pointer = (uint8_t *)(test_pattern + *tx_byte_offset); - - if (*tx_byte_offset < TEST_BUFFER_LEN) { - bytes_sent = uart_fifo_fill(dev, tx_data_pointer, 1); - *tx_byte_offset += bytes_sent; - } else { - *tx_byte_offset = 0; - uart_irq_tx_disable(dev); - } -} - -/* - * ISR for UART RX action - */ -static void uart_rx_interrupt_service(const struct device *dev, uint8_t *receive_buffer_pointer, - int *rx_byte_offset) -{ - int rx_data_length = 0; - int bytes_received = 0; - - do { - rx_data_length = uart_fifo_read(dev, receive_buffer_pointer + *rx_byte_offset, - TEST_BUFFER_LEN); - bytes_received += rx_data_length; - } while (rx_data_length); - *rx_byte_offset += bytes_received; -} - -/* - * Callback function for MAIN UART interrupt based transmission test - */ -static void interrupt_driven_uart_callback_main_uart(const struct device *dev, void *user_data) -{ - int err; - static int tx_byte_offset; - static int rx_byte_offset; - - uart_irq_update(dev); - err = uart_err_check(dev); - if (err != 0) { - uart_error_counter++; - } - while (uart_irq_is_pending(dev)) { - if (uart_irq_rx_ready(dev)) { - uart_rx_interrupt_service(dev, (uint8_t *)user_data, &rx_byte_offset); - } - if (uart_irq_tx_ready(dev)) { - uart_tx_interrupt_service(dev, &tx_byte_offset); - } - } -} - -#if defined(CONFIG_DUAL_UART_TEST) -/* - * Callback function for AUX UART interrupt based transmission test - */ -static void interrupt_driven_uart_callback_aux_uart(const struct device *dev, void *user_data) -{ - int err; - static int tx_byte_offset_aux; - static int rx_byte_offset_aux; - - uart_irq_update(dev); - err = uart_err_check(dev); -#if !defined(CONFIG_COVERAGE) - /* This assetion will fail with coverge enabled - * When in coverage mode it has no impact on test case execution - */ - zassert_equal(err, 0, "Unexpected UART device: %s error: %d", dev->name, err); -#endif /* CONFIG_COVERAGE */ - while (uart_irq_is_pending(dev)) { - if (uart_irq_rx_ready(dev)) { - uart_rx_interrupt_service(dev, (uint8_t *)user_data, &rx_byte_offset_aux); - } - if (uart_irq_tx_ready(dev)) { - uart_tx_interrupt_service(dev, &tx_byte_offset_aux); - } - } -} -#endif /* CONFIG_DUAL_UART_TEST */ - -/* - * Test UART proper configuration call - */ -ZTEST(uart_elementary, test_uart_proper_configuration) -{ - Z_TEST_SKIP_IFDEF(CONFIG_DUAL_UART_TEST); - - int err; - struct uart_config test_expected_uart_config; - struct uart_config test_uart_config = { .baudrate = 115200, - .parity = UART_CFG_PARITY_NONE, - .stop_bits = UART_CFG_STOP_BITS_1, - .data_bits = UART_CFG_DATA_BITS_8, - .flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS }; - - err = uart_configure(uart_dev, &test_uart_config); - zassert_equal(err, 0, "'uart_configure' api call - unexpected error: %d", err); - - err = uart_config_get(uart_dev, &test_expected_uart_config); - zassert_equal(err, 0, "'uart_config_get' api call - unexpected error raised : %d", err); - - zassert_equal(test_uart_config.baudrate, test_expected_uart_config.baudrate, - "Set and actual UART config baudrate mismatch: %d != %d", - test_uart_config.baudrate, test_expected_uart_config.baudrate); - - zassert_equal(test_uart_config.parity, test_expected_uart_config.parity, - "Set and actual UART config parity mismatch: %d != %d", - test_uart_config.parity, test_expected_uart_config.parity); - - zassert_equal(test_uart_config.stop_bits, test_expected_uart_config.stop_bits, - "Set and actual UART config stop_bits mismatch: %d != %d", - test_uart_config.stop_bits, test_expected_uart_config.stop_bits); - - zassert_equal(test_uart_config.data_bits, test_expected_uart_config.data_bits, - "Set and actual UART config data_bits mismatch: %d != %d", - test_uart_config.data_bits, test_expected_uart_config.data_bits); - - zassert_equal(test_uart_config.flow_ctrl, test_expected_uart_config.flow_ctrl, - "Set and actual UART config flow_ctrl mismatch: %d != %d", - test_uart_config.flow_ctrl, test_expected_uart_config.flow_ctrl); -} - -/* - * Test UART improper configuration call - */ -ZTEST(uart_elementary, test_uart_improper_configuration) -{ - Z_TEST_SKIP_IFDEF(CONFIG_DUAL_UART_TEST); - - int err; - struct uart_config test_uart_config = { .baudrate = 115200, - .parity = 7, - .stop_bits = UART_CFG_STOP_BITS_1, - .data_bits = UART_CFG_DATA_BITS_8, - .flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS }; - - err = uart_configure(uart_dev, &test_uart_config); - zassert_not_equal( - err, 0, - "'uart_configure' with incorrect configuration havent't raised an error, err=%d", - err); -} - -#if !defined(CONFIG_DUAL_UART_TEST) -/* - * Test UART basic interrupt based transmission (with loopback) - */ -ZTEST(uart_elementary, test_uart_basic_transmission) -{ - int err; - struct uart_config test_uart_config = { .baudrate = 115200, - .parity = UART_CFG_PARITY_ODD, - .stop_bits = UART_CFG_STOP_BITS_1, - .data_bits = UART_CFG_DATA_BITS_8, - .flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS }; - - err = uart_configure(uart_dev, &test_uart_config); - zassert_equal(err, 0, "Unexpected error when configuring UART0: %d", err); - - err = uart_irq_callback_set(uart_dev, interrupt_driven_uart_callback_main_uart); - zassert_equal(err, 0, "Unexpected error when setting callback %d", err); - err = uart_irq_callback_user_data_set(uart_dev, interrupt_driven_uart_callback_main_uart, - (void *)test_buffer); - zassert_equal(err, 0, "Unexpected error when setting user data for callback %d", err); - uart_irq_err_enable(uart_dev); - uart_irq_rx_enable(uart_dev); - uart_irq_tx_enable(uart_dev); - - /* wait for the tramission to finish (no polling is intentional) */ - k_sleep(K_USEC(100 * SLEEP_TIME_US)); - - uart_irq_tx_disable(uart_dev); - uart_irq_rx_disable(uart_dev); - uart_irq_err_disable(uart_dev); - for (int index = 0; index < TEST_BUFFER_LEN; index++) { - zassert_equal(test_buffer[index], test_pattern[index], - "Recieived data byte %d does not match pattern 0x%x != 0x%x", index, - test_buffer[index], test_pattern[index]); - } -} -#else -/* - * Test UART interrupt based transmission between two ports - */ -ZTEST(uart_elementary, test_uart_dual_port_transmission) -{ - int err; - struct uart_config test_uart_config = { .baudrate = 115200, - .parity = UART_CFG_PARITY_NONE, - .stop_bits = UART_CFG_STOP_BITS_1, - .data_bits = UART_CFG_DATA_BITS_8, - .flow_ctrl = UART_CFG_FLOW_CTRL_NONE }; - -#if defined(CONFIG_SETUP_MISMATCH_TEST) - struct uart_config test_uart_config_aux = { .baudrate = 9600, - .parity = UART_CFG_PARITY_NONE, - .stop_bits = UART_CFG_STOP_BITS_1, - .data_bits = UART_CFG_DATA_BITS_8, - .flow_ctrl = UART_CFG_FLOW_CTRL_NONE }; -#endif - err = uart_configure(uart_dev, &test_uart_config); - zassert_equal(err, 0, "Unexpected error when configuring UART0: %d", err); - -#if defined(CONFIG_SETUP_MISMATCH_TEST) - err = uart_configure(uart_dev_aux, &test_uart_config_aux); -#else - err = uart_configure(uart_dev_aux, &test_uart_config); -#endif - - zassert_equal(err, 0, "Unexpected error when configuring UART1: %d", err); - - err = uart_irq_callback_set(uart_dev, interrupt_driven_uart_callback_main_uart); - zassert_equal(err, 0, "Unexpected error when setting callback for UART0 %d", err); - err = uart_irq_callback_user_data_set(uart_dev, interrupt_driven_uart_callback_main_uart, - (void *)test_buffer); - zassert_equal(err, 0, "Unexpected error when setting user data for UART0 callback %d", err); - - err = uart_irq_callback_set(uart_dev_aux, interrupt_driven_uart_callback_aux_uart); - zassert_equal(err, 0, "Unexpected error when setting callback for UART1 %d", err); - err = uart_irq_callback_user_data_set(uart_dev_aux, interrupt_driven_uart_callback_aux_uart, - (void *)test_buffer_aux); - zassert_equal(err, 0, "Unexpected error when setting user data for UART1 callback %d", err); - - uart_irq_err_enable(uart_dev); - uart_irq_err_enable(uart_dev_aux); - - uart_irq_tx_enable(uart_dev); - uart_irq_tx_enable(uart_dev_aux); - - uart_irq_rx_enable(uart_dev); - uart_irq_rx_enable(uart_dev_aux); - - /* wait for the tramission to finish (no polling is intentional) */ - k_sleep(K_USEC(100 * SLEEP_TIME_US)); - - uart_irq_tx_disable(uart_dev); - uart_irq_tx_disable(uart_dev_aux); - uart_irq_rx_disable(uart_dev); - uart_irq_rx_disable(uart_dev_aux); - uart_irq_err_disable(uart_dev); - uart_irq_err_disable(uart_dev_aux); - -#if defined(CONFIG_SETUP_MISMATCH_TEST) - zassert_not_equal(uart_error_counter, 0); -#else - for (int index = 0; index < TEST_BUFFER_LEN; index++) { - zassert_equal(test_buffer[index], test_pattern[index], - "UART0 recieived data byte %d does not match pattern 0x%x != 0x%x", - index, test_buffer[index], test_pattern[index]); - zassert_equal(test_buffer_aux[index], test_pattern[index], - "UART1 recieived data byte %d does not match pattern 0x%x != 0x%x", - index, test_buffer_aux[index], test_pattern[index]); - } -#endif /* CONFIG_SETUP_MISMATCH_TEST */ -} -#endif /* CONFIG_DUAL_UART_TEST */ - -/* - * Test setup - */ -void *test_setup(void) -{ - zassert_true(device_is_ready(uart_dev), "UART0 device is not ready"); -#if defined(CONFIG_DUAL_UART_TEST) - zassert_true(device_is_ready(uart_dev_aux), "UART1 device is not ready"); -#endif - - return NULL; -} - -ZTEST_SUITE(uart_elementary, NULL, test_setup, NULL, NULL, NULL); diff --git a/tests/drivers/uart/uart_elementary/testcase.yaml b/tests/drivers/uart/uart_elementary/testcase.yaml deleted file mode 100644 index 9308ffbf5c2..00000000000 --- a/tests/drivers/uart/uart_elementary/testcase.yaml +++ /dev/null @@ -1,35 +0,0 @@ -common: - tags: drivers uart - depends_on: gpio - harness: ztest - harness_config: - fixture: gpio_loopback -tests: - drivers.uart.uart_elementary: - filter: CONFIG_SERIAL_SUPPORT_INTERRUPT - platform_allow: - - nrf54h20dk_nrf54h20_cpuapp - - nrf54l15pdk_nrf54l15_cpuapp - - nrf5340dk_nrf5340_cpuapp - drivers.uart.uart_elementary_dual_nrf54h: - filter: CONFIG_SERIAL_SUPPORT_INTERRUPT - platform_allow: - - nrf54h20dk_nrf54h20_cpuapp - extra_args: DTC_OVERLAY_FILE="boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay" - extra_configs: - - CONFIG_DUAL_UART_TEST=y - drivers.uart.uart_elementary_dual_setup_mismatch_nrf54h: - filter: CONFIG_SERIAL_SUPPORT_INTERRUPT - platform_allow: - - nrf54h20dk_nrf54h20_cpuapp - extra_args: DTC_OVERLAY_FILE="boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay" - extra_configs: - - CONFIG_DUAL_UART_TEST=y - - CONFIG_SETUP_MISMATCH_TEST=y - drivers.uart.uart_elementary_dual_nrf54l: - filter: CONFIG_SERIAL_SUPPORT_INTERRUPT - platform_allow: - - nrf54l15pdk_nrf54l15_cpuapp - extra_args: DTC_OVERLAY_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay" - extra_configs: - - CONFIG_DUAL_UART_TEST=y From 0eca162fe9ac3747f8e4cda57e5e57560c2a346c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:09 +0200 Subject: [PATCH 2172/2402] Revert "[nrf fromlist] tests: drivers: uart: async_api: Add nrf54h20 support" This reverts commit 9e79564fad08b8b32fccd5a81cea196d3cadee80. Signed-off-by: Gerard Marull-Paretas --- .../boards/nrf54h20dk_nrf54h20_common.dtsi | 25 ------------------- .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 11 -------- .../boards/nrf54h20dk_nrf54h20_cpurad.overlay | 11 -------- 3 files changed, 47 deletions(-) delete mode 100644 tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_common.dtsi delete mode 100644 tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay delete mode 100644 tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpurad.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_common.dtsi deleted file mode 100644 index 172d75904e4..00000000000 --- a/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_common.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -&pinctrl { - uart135_default_alt: uart135_default_alt { - group1 { - psels = , - ; - }; - }; - - uart135_sleep_alt: uart135_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; -}; - -dut: &uart135 { - status = "okay"; - pinctrl-0 = <&uart135_default_alt>; - pinctrl-1 = <&uart135_sleep_alt>; - pinctrl-names = "default", "sleep"; -}; diff --git a/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay deleted file mode 100644 index a8fe36d37bb..00000000000 --- a/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include "nrf54h20dk_nrf54h20_common.dtsi" - -&cpuapp_dma_region { - status = "okay"; -}; - -&dut { - memory-regions = <&cpuapp_dma_region>; -}; diff --git a/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpurad.overlay deleted file mode 100644 index 32f95625201..00000000000 --- a/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpurad.overlay +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include "nrf54h20dk_nrf54h20_common.dtsi" - -&cpurad_dma_region { - status = "okay"; -}; - -&dut { - memory-regions = <&cpurad_dma_region>; -}; From 24c8aaa4c2974bdf965b32afac27e0fa03e2b12a Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:10 +0200 Subject: [PATCH 2173/2402] Revert "[nrf fromlist] tests: drivers: uart: uart_pm: Add support for nrf54h20dk" This reverts commit 53ca2050ec1ab44c9eee3195780d0a1b0f69349c. Signed-off-by: Gerard Marull-Paretas --- .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 31 ------------------- tests/drivers/uart/uart_pm/testcase.yaml | 5 --- 2 files changed, 36 deletions(-) delete mode 100644 tests/drivers/uart/uart_pm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay diff --git a/tests/drivers/uart/uart_pm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/uart/uart_pm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay deleted file mode 100644 index d01ebce4c8a..00000000000 --- a/tests/drivers/uart/uart_pm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - uart135_default_alt: uart135_default_alt { - group1 { - psels = , - ; - }; - }; - - uart135_sleep_alt: uart135_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; -}; - -dut: &uart135 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart135_default_alt>; - pinctrl-1 = <&uart135_sleep_alt>; - pinctrl-names = "default", "sleep"; - memory-regions = <&cpuapp_dma_region>; -}; diff --git a/tests/drivers/uart/uart_pm/testcase.yaml b/tests/drivers/uart/uart_pm/testcase.yaml index 1430fd9a8c2..69e3b0e5d0d 100644 --- a/tests/drivers/uart/uart_pm/testcase.yaml +++ b/tests/drivers/uart/uart_pm/testcase.yaml @@ -6,7 +6,6 @@ common: platform_allow: - nrf52840dk_nrf52840 - nrf54l15pdk_nrf54l15_cpuapp - - nrf54h20dk_nrf54h20_cpuapp - nrf52_bsim harness_config: fixture: gpio_loopback @@ -28,7 +27,6 @@ tests: extra_args: DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840.overlay;nrf_rx_disable.overlay" platform_exclude: - nrf54l15pdk_nrf54l15_cpuapp - - nrf54h20dk_nrf54h20_cpuapp drivers.uart.pm.enhanced_poll: extra_configs: @@ -38,7 +36,6 @@ tests: - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y platform_exclude: - nrf54l15pdk_nrf54l15_cpuapp - - nrf54h20dk_nrf54h20_cpuapp drivers.uart.pm.int_driven: extra_configs: @@ -57,7 +54,6 @@ tests: - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y platform_exclude: - nrf54l15pdk_nrf54l15_cpuapp - - nrf54h20dk_nrf54h20_cpuapp drivers.uart.pm.async: extra_configs: @@ -82,4 +78,3 @@ tests: - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y platform_exclude: - nrf54l15pdk_nrf54l15_cpuapp - - nrf54h20dk_nrf54h20_cpuapp From bb21376b7e500a2809cdbe5c53f61108cd7cc546 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:10 +0200 Subject: [PATCH 2174/2402] Revert "[nrf fromlist] tests: drivers: uart: uart_pm: Limit scope for nrf54l15" This reverts commit a105c379cffad1c1454a09a37880d26050c7e54f. Signed-off-by: Gerard Marull-Paretas --- tests/drivers/uart/uart_pm/testcase.yaml | 9 --------- 1 file changed, 9 deletions(-) diff --git a/tests/drivers/uart/uart_pm/testcase.yaml b/tests/drivers/uart/uart_pm/testcase.yaml index 69e3b0e5d0d..5417be597e0 100644 --- a/tests/drivers/uart/uart_pm/testcase.yaml +++ b/tests/drivers/uart/uart_pm/testcase.yaml @@ -5,7 +5,6 @@ common: harness: ztest platform_allow: - nrf52840dk_nrf52840 - - nrf54l15pdk_nrf54l15_cpuapp - nrf52_bsim harness_config: fixture: gpio_loopback @@ -25,8 +24,6 @@ tests: - CONFIG_UART_0_ENHANCED_POLL_OUT=n - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y extra_args: DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840.overlay;nrf_rx_disable.overlay" - platform_exclude: - - nrf54l15pdk_nrf54l15_cpuapp drivers.uart.pm.enhanced_poll: extra_configs: @@ -34,8 +31,6 @@ tests: - CONFIG_UART_ASYNC_API=n - CONFIG_UART_0_ENHANCED_POLL_OUT=y - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y - platform_exclude: - - nrf54l15pdk_nrf54l15_cpuapp drivers.uart.pm.int_driven: extra_configs: @@ -52,8 +47,6 @@ tests: - CONFIG_UART_ASYNC_API=n - CONFIG_UART_0_ENHANCED_POLL_OUT=y - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y - platform_exclude: - - nrf54l15pdk_nrf54l15_cpuapp drivers.uart.pm.async: extra_configs: @@ -76,5 +69,3 @@ tests: - CONFIG_NRFX_TIMER2=y - CONFIG_UART_0_ENHANCED_POLL_OUT=y - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y - platform_exclude: - - nrf54l15pdk_nrf54l15_cpuapp From 10c36a4d513dba461db2ffc22d23afc340c713ed Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:10 +0200 Subject: [PATCH 2175/2402] Revert "[nrf fromtree] drivers: serial: uart_async_rx: Fix uart_async_rx_reset" This reverts commit eac6c474270860683c6f19afef3010d9ffb337e8. Signed-off-by: Gerard Marull-Paretas --- drivers/serial/uart_async_rx.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/serial/uart_async_rx.c b/drivers/serial/uart_async_rx.c index 709f8733849..68e17691c3e 100644 --- a/drivers/serial/uart_async_rx.c +++ b/drivers/serial/uart_async_rx.c @@ -116,9 +116,6 @@ void uart_async_rx_data_consume(struct uart_async_rx *rx_data, size_t length) void uart_async_rx_reset(struct uart_async_rx *rx_data) { rx_data->free_buf_cnt = rx_data->config->buf_cnt; - rx_data->rd_buf_idx = 0; - rx_data->drv_buf_idx = 0; - rx_data->pending_bytes = 0; for (uint8_t i = 0; i < rx_data->config->buf_cnt; i++) { buf_reset(get_buf(rx_data, i)); } From d6727f22d5433bbf0b17f651ba0ccc9d3a0aef1b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:10 +0200 Subject: [PATCH 2176/2402] Revert "[nrf fromlist] drivers: serial: nrfx_uarte2: Clean error on rx_enable" This reverts commit c080d9332c09a9a525c781cbc1283ccbd22e738b. Signed-off-by: Gerard Marull-Paretas --- drivers/serial/uart_nrfx_uarte2.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/serial/uart_nrfx_uarte2.c b/drivers/serial/uart_nrfx_uarte2.c index ebe85448cea..0b8350714eb 100644 --- a/drivers/serial/uart_nrfx_uarte2.c +++ b/drivers/serial/uart_nrfx_uarte2.c @@ -506,7 +506,6 @@ static int api_rx_enable(const struct device *dev, uint8_t *buf, size_t len, int * flags are already known to the driver (e.g. if flushed data shall be * kept or not). */ - adata->err = 0; adata->en_rx_buf = buf; adata->en_rx_len = len; From 3f2ce5a0395bd8053126067a0472a1447518aeb7 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:10 +0200 Subject: [PATCH 2177/2402] Revert "[nrf fromtree] drivers: serial: nrfx_uarte2: Fix re-enabling the RX" This reverts commit 8fd1556ae3a6730001464830139a928319889a27. Signed-off-by: Gerard Marull-Paretas --- drivers/serial/uart_nrfx_uarte2.c | 42 +++++++------------------------ 1 file changed, 9 insertions(+), 33 deletions(-) diff --git a/drivers/serial/uart_nrfx_uarte2.c b/drivers/serial/uart_nrfx_uarte2.c index 0b8350714eb..67e6adfccd5 100644 --- a/drivers/serial/uart_nrfx_uarte2.c +++ b/drivers/serial/uart_nrfx_uarte2.c @@ -115,9 +115,6 @@ struct uarte_async_data { uart_callback_t user_callback; void *user_data; - uint8_t *en_rx_buf; - size_t en_rx_len; - struct k_timer tx_timer; struct k_timer rx_timer; @@ -291,22 +288,6 @@ static void on_rx_buf_req(const struct device *dev) struct uarte_async_data *adata = data->async; const nrfx_uarte_t *nrfx_dev = get_nrfx_dev(dev); - /* If buffer is not null it indicates that event comes from RX enabling - * function context. We need to pass provided buffer to the driver. - */ - if (adata->en_rx_buf) { - uint8_t *buf = adata->en_rx_buf; - size_t len = adata->en_rx_len; - nrfx_err_t err; - - adata->en_rx_buf = NULL; - adata->en_rx_len = 0; - - err = nrfx_uarte_rx_buffer_set(nrfx_dev, buf, len); - __ASSERT_NO_MSG(err == NRFX_SUCCESS); - return; - } - struct uart_event evt = { .type = UART_RX_BUF_REQUEST }; @@ -315,6 +296,8 @@ static void on_rx_buf_req(const struct device *dev) * reception of one buffer was terminated to restart another transfer. */ if (!K_TIMEOUT_EQ(adata->rx_timeout, K_NO_WAIT)) { + /* Read and clear any pending new data information. */ + nrfx_uarte_rx_new_data_check(nrfx_dev); nrfx_uarte_rxdrdy_enable(nrfx_dev); } data->async->user_callback(dev, &evt, data->async->user_data); @@ -495,28 +478,22 @@ static int api_rx_enable(const struct device *dev, uint8_t *buf, size_t len, int if (timeout != SYS_FOREVER_US) { adata->idle_cnt = RX_TIMEOUT_DIV + 1; adata->rx_timeout = K_USEC(timeout / RX_TIMEOUT_DIV); - nrfx_uarte_rxdrdy_enable(nrfx_dev); } else { adata->rx_timeout = K_NO_WAIT; } - /* Store the buffer. It will be passed to the driver in the event handler. - * We do that instead of calling nrfx_uarte_rx_buffer_set here to ensure - * that nrfx_uarte_rx_buffer_set is called when RX enable configuration - * flags are already known to the driver (e.g. if flushed data shall be - * kept or not). - */ - adata->en_rx_buf = buf; - adata->en_rx_len = len; - - atomic_or(&data->flags, UARTE_DATA_FLAG_RX_ENABLED); + err = nrfx_uarte_rx_buffer_set(nrfx_dev, buf, len); + if (err != NRFX_SUCCESS) { + return -EIO; + } err = nrfx_uarte_rx_enable(nrfx_dev, flags); if (err != NRFX_SUCCESS) { - atomic_and(&data->flags, ~UARTE_DATA_FLAG_RX_ENABLED); return (err == NRFX_ERROR_BUSY) ? -EBUSY : -EIO; } + atomic_or(&data->flags, UARTE_DATA_FLAG_RX_ENABLED); + return 0; } @@ -973,8 +950,7 @@ static int uarte_nrfx_pm_action(const struct device *dev, UARTE_MEMORY_SECTION(idx) __aligned(4); \ static nrfx_uarte_rx_cache_t uarte##idx##_rx_cache_scratch; \ IF_ENABLED(CONFIG_UART_##idx##_INTERRUPT_DRIVEN, \ - (static uint8_t a2i_rx_buf##idx[CONFIG_UART_##idx##_A2I_RX_SIZE] \ - UARTE_MEMORY_SECTION(idx) __aligned(4);)) \ + (static uint8_t a2i_rx_buf##idx[CONFIG_UART_##idx##_A2I_RX_SIZE];)) \ PINCTRL_DT_DEFINE(UARTE(idx)); \ static const struct uart_async_to_irq_config uarte_a2i_config_##idx = \ UART_ASYNC_TO_IRQ_API_CONFIG_INITIALIZER(&a2i_api, \ From bab41529fb665db64b854405d4e6b3d3afd4f771 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:11 +0200 Subject: [PATCH 2178/2402] Revert "[nrf fromlist] manifest: Update hal_nordic fix nrfx_uarte fixes" This reverts commit 100646ff29f04b35dd2387e40cda494882a49a0b. Signed-off-by: Gerard Marull-Paretas --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 0b80a43c597..c25c87dcd32 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: f8e4d73a78316ea9ef85f09f24a3a229e40c1a80 + revision: fc2bab706f195c64d40016c9855b8acd7c235ded path: modules/hal/nordic groups: - hal From c0a42d06b7f6669a8e9c81f74a6245732beab836 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:11 +0200 Subject: [PATCH 2179/2402] Revert "[nrf fromtree] tests: drivers: counter: add nRF54L15 overlay" This reverts commit b85b85b1873a59f13e7dcee558845b623ff883b9. Signed-off-by: Gerard Marull-Paretas --- .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 34 ------------------- 1 file changed, 34 deletions(-) delete mode 100644 tests/drivers/counter/counter_basic_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/counter/counter_basic_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay deleted file mode 100644 index 54b47926164..00000000000 --- a/tests/drivers/counter/counter_basic_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay +++ /dev/null @@ -1,34 +0,0 @@ -&timer00 { - prescaler = <6>; - status = "okay"; -}; - -&timer10 { - prescaler = <4>; - status = "okay"; -}; - -&timer20 { - prescaler = <4>; - status = "okay"; -}; - -&timer21 { - prescaler = <4>; - status = "okay"; -}; - -&timer22 { - prescaler = <4>; - status = "okay"; -}; - -&timer23 { - prescaler = <4>; - status = "okay"; -}; - -&timer24 { - prescaler = <4>; - status = "okay"; -}; From f5b98a085ddf5fa8be4a853c0a069855aeaff5b8 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:11 +0200 Subject: [PATCH 2180/2402] Revert "[nrf fromlist] wifi: shell: Support WPA auto personal security mode" This reverts commit f46813ec86e56ed491ca0180f993e998e48c89ed. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/net/wifi.h | 2 -- subsys/net/l2/wifi/wifi_mgmt.c | 3 +-- subsys/net/l2/wifi/wifi_shell.c | 5 ++--- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/include/zephyr/net/wifi.h b/include/zephyr/net/wifi.h index ebfc76d2192..a0840a2319a 100644 --- a/include/zephyr/net/wifi.h +++ b/include/zephyr/net/wifi.h @@ -49,8 +49,6 @@ enum wifi_security_type { WIFI_SECURITY_TYPE_WEP, /** WPA-PSK security. */ WIFI_SECURITY_TYPE_WPA_PSK, - /** WPA/WPA2/WPA3 PSK security. */ - WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL, __WIFI_SECURITY_TYPE_AFTER_LAST, WIFI_SECURITY_TYPE_MAX = __WIFI_SECURITY_TYPE_AFTER_LAST - 1, diff --git a/subsys/net/l2/wifi/wifi_mgmt.c b/subsys/net/l2/wifi/wifi_mgmt.c index 51e76aec5fb..72552d371d7 100644 --- a/subsys/net/l2/wifi/wifi_mgmt.c +++ b/subsys/net/l2/wifi/wifi_mgmt.c @@ -275,8 +275,7 @@ static int wifi_connect(uint32_t mgmt_request, struct net_if *iface, (params->ssid_length == 0U) || ((params->security == WIFI_SECURITY_TYPE_PSK || params->security == WIFI_SECURITY_TYPE_WPA_PSK || - params->security == WIFI_SECURITY_TYPE_PSK_SHA256 || - params->security == WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL) && + params->security == WIFI_SECURITY_TYPE_PSK_SHA256) && ((params->psk_length < 8) || (params->psk_length > 64) || (params->psk_length == 0U) || !params->psk)) || ((params->security == WIFI_SECURITY_TYPE_SAE) && diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index a81af57d40f..b938a80bc4b 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -1898,9 +1898,8 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_commands, "[-c --channel]: Channel that needs to be scanned for connection. 0:any channel.\n" "[-b, --band] 0: any band (2:2.4GHz, 5:5GHz, 6:6GHz]\n" "[-p, --psk]: Passphrase (valid only for secure SSIDs)\n" - "[-k, --key-mgmt]: Key Management type (valid only for secure SSIDs)\n" - "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP," - " 7: WPA-PSK, 8: WPA-Auto-Personal\n" + "[-k, --key-mgmt]: Key Management type\n" + "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP, 7: WPA-PSK\n" "[-w, --ieee-80211w]: MFP (optional: needs security type to be specified)\n" ": 0:Disable, 1:Optional, 2:Required.\n" "[-m, --bssid]: MAC address of the AP (BSSID).\n" From 3b38ac315d5947efb63dc0e19988dae344ab59e7 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:11 +0200 Subject: [PATCH 2181/2402] Revert "[nrf noup] samples/**/smp_svr: testcase of nrf54l15pdk with ext-flash" This reverts commit 849d51f27998807371199e36cf7995652b4864a1. Signed-off-by: Gerard Marull-Paretas --- samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml index e5c30662d90..373c3acccb9 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml +++ b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml @@ -94,15 +94,3 @@ tests: - mg100 integration_platforms: - nrf52840dk_nrf52840 - sample.mcumgr.smp_svr.bt.nrf54l15pdk.ext_flash: - extra_args: - - OVERLAY_CONFIG="overlay-bt.conf" - - DTC_OVERLAY_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_ext_flash.overlay" - - mcuboot_CONF_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_ext_flash.conf" - - mcuboot_EXTRA_DTC_OVERLAY_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_ext_flash.overlay" - extra_configs: - - CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y - platform_allow: - - nrf54l15pdk_nrf54l15_cpuapp - integration_platforms: - - nrf54l15pdk_nrf54l15_cpuapp From 378d9b6eb1ba474c23d210555103e179c89abb6e Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:11 +0200 Subject: [PATCH 2182/2402] Revert "[nrf fromlist] soc/nordic/comomn: Added HAS_HW_NRF_GPIO2" This reverts commit dbea77330f5da536adb0dbe33f47c746cbb1ff73. Signed-off-by: Gerard Marull-Paretas --- soc/common/nordic_nrf/Kconfig.peripherals | 3 --- 1 file changed, 3 deletions(-) diff --git a/soc/common/nordic_nrf/Kconfig.peripherals b/soc/common/nordic_nrf/Kconfig.peripherals index e10ddb42d20..39ed2e6432f 100644 --- a/soc/common/nordic_nrf/Kconfig.peripherals +++ b/soc/common/nordic_nrf/Kconfig.peripherals @@ -74,9 +74,6 @@ config HAS_HW_NRF_GPIO0 config HAS_HW_NRF_GPIO1 def_bool $(dt_nodelabel_enabled_with_compat,gpio1,$(DT_COMPAT_NORDIC_NRF_GPIO)) -config HAS_HW_NRF_GPIO2 - def_bool $(dt_nodelabel_enabled_with_compat,gpio2,$(DT_COMPAT_NORDIC_NRF_GPIO)) - config HAS_HW_NRF_GPIOTE0 def_bool $(dt_nodelabel_enabled_with_compat,gpiote0,$(DT_COMPAT_NORDIC_NRF_GPIOTE)) From a7c4a08ef718e09a89085f7b6a25c41d2e693848 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:12 +0200 Subject: [PATCH 2183/2402] Revert "[nrf fromlist] boards/nordic/nrf54l15pdk: added mx25r64 flash DTS" This reverts commit 113f05cbc93fb7775ab5512fd56e718d908a03cf. Signed-off-by: Gerard Marull-Paretas --- .../nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi | 17 ------------ .../nrf54l15pdk_nrf54l15_cpuapp.dts | 27 ------------------- 2 files changed, 44 deletions(-) diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi index 31c2f820f3f..96c53f948fc 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi @@ -47,21 +47,4 @@ low-power-enable; }; }; - - spi0_default: spi0_default { - group1 { - psels = , - , - ; - }; - }; - - spi0_sleep: spi0_sleep { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; }; diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts index e6ef815e783..0b9e76ff083 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -77,7 +77,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - spi-flash0 = &mx25r64; }; }; @@ -175,29 +174,3 @@ &clock { status = "okay"; }; - -&spi00 { - status = "okay"; - cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&spi0_default>; - pinctrl-1 = <&spi0_sleep>; - pinctrl-names = "default", "sleep"; - - mx25r64: mx25r6435f@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - status = "disabled"; - spi-max-frequency = <8000000>; - jedec-id = [c2 28 17]; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; - size = <67108864>; - has-dpd; - t-enter-dpd = <10000>; - t-exit-dpd = <35000>; - }; -}; From 8dcf65af8e82fda3e5d1d4d972d231a86e7cce77 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:12 +0200 Subject: [PATCH 2184/2402] Revert "[nrf noup] boards: nordic: nrf54l15pdk: enable HWFC" This reverts commit c22c9c258ce776b88dac8a917ab13f46a4c7db85. Signed-off-by: Gerard Marull-Paretas --- .../nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi | 22 ++++--------------- .../nrf54l15pdk_nrf54l15_cpuapp.dts | 1 - 2 files changed, 4 insertions(+), 19 deletions(-) diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi index 96c53f948fc..02b02bc8171 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi @@ -7,21 +7,14 @@ uart20_default: uart20_default { group1 { psels = , - ; - }; - group2 { - psels = , - ; - bias-pull-up; + ; }; }; uart20_sleep: uart20_sleep { group1 { psels = , - , - , - ; + ; low-power-enable; }; }; @@ -29,21 +22,14 @@ uart30_default: uart30_default { group1 { psels = , - ; - }; - group2 { - psels = , - ; - bias-pull-up; + ; }; }; uart30_sleep: uart30_sleep { group1 { psels = , - , - , - ; + ; low-power-enable; }; }; diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts index 0b9e76ff083..c801ddc8dc5 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -96,7 +96,6 @@ pinctrl-0 = <&uart20_default>; pinctrl-1 = <&uart20_sleep>; pinctrl-names = "default", "sleep"; - hw-flow-control; }; &uart30 { From 3182ea8d971d0809585919e0bcf063263f048bba Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:12 +0200 Subject: [PATCH 2185/2402] Revert "[nrf fromlist] boards: nrf54l15pdk_nrf54l15_cpuapp: yaml for PDK 0.3.0" This reverts commit 5647467695b545e6baf127ef6e8d7d0cee0a403f. Signed-off-by: Gerard Marull-Paretas --- .../nrf54l15pdk_nrf54l15_cpuapp_0_3_0.yaml | 20 ------------------- 1 file changed, 20 deletions(-) delete mode 100644 boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.yaml diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.yaml b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.yaml deleted file mode 100644 index 8db30713e43..00000000000 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54l15pdk_nrf54l15_cpuapp@0.3.0 -name: nRF54l15-PDK-nRF54l15-Application -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 256 -flash: 1536 -supported: - - counter - - gpio - - i2c - - spi - - watchdog - - i2s From 83a3f30ebabacd7d02bb6f3301b29d50bf6d7fe5 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:12 +0200 Subject: [PATCH 2186/2402] Revert "[nrf fromlist] boards: nordic: nrf54h20dk: Add configuration for BLE" This reverts commit dd3931ad85d643528bec4494898abc6b6cbe21a0. Signed-off-by: Gerard Marull-Paretas --- .../nrf54h20dk_nrf54h20_cpuapp.dts | 13 +-------- .../nrf54h20dk_nrf54h20_cpurad.dts | 13 +-------- .../boards/nrf54h20dk_nrf54h20_cpurad.overlay | 27 +++++++++++++++++++ 3 files changed, 29 insertions(+), 24 deletions(-) create mode 100644 samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts index 4b04ff8dcd4..4eff8c7741d 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts @@ -23,7 +23,6 @@ zephyr,flash = &mram1x; zephyr,sram = &cpuapp_data; zephyr,entropy = &prng; - zephyr,bt-hci-ipc = &ipc0; }; aliases { @@ -99,34 +98,24 @@ status = "okay"; }; -&cpuapp_cpurad_ram0x_region { - status = "okay"; -}; - &shared_ram3x_region { status = "okay"; }; &cpuapp_bellboard { - status = "okay"; interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; interrupt-names = "irq0"; /* irq0: 0: cpuapp-cpusec, 13: cpuapp-cpuppr, 18: cpuapp-cpurad */ nordic,interrupt-mapping = <0x00042001 0>; }; -&cpurad_bellboard { - status = "okay"; -}; - &cpusec_cpuapp_ipc { mbox-names = "tx", "rx"; tx-region = <&cpuapp_cpusec_ipc_shm>; rx-region = <&cpusec_cpuapp_ipc_shm>; }; -ipc0: &cpuapp_cpurad_ipc { - status = "okay"; +&cpuapp_cpurad_ipc { mbox-names = "rx", "tx"; tx-region = <&cpuapp_cpurad_ipc_shm>; rx-region = <&cpurad_cpuapp_ipc_shm>; diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts index 36ac2aef20a..9e3dacbeb32 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts @@ -24,7 +24,6 @@ zephyr,flash = &mram1x; zephyr,sram = &cpurad_ram0; zephyr,entropy = &prng; - zephyr,bt-hci-ipc = &ipc0; }; prng: prng { @@ -37,30 +36,20 @@ status = "okay"; }; -&cpuapp_cpurad_ram0x_region { - status = "okay"; -}; - &cpurad_bellboard { - status = "okay"; interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; interrupt-names = "irq0"; /* irq0: 0: cpurad-cpusec, 12: cpurad-cpuapp */ nordic,interrupt-mapping = <0x00001001 0>; }; -&cpuapp_bellboard { - status = "okay"; -}; - &cpusec_cpurad_ipc { mbox-names = "tx", "rx"; tx-region = <&cpurad_cpusec_ipc_shm>; rx-region = <&cpusec_cpurad_ipc_shm>; }; -ipc0: &cpuapp_cpurad_ipc { - status = "okay"; +&cpuapp_cpurad_ipc { mbox-names = "tx", "rx"; tx-region = <&cpurad_cpuapp_ipc_shm>; rx-region = <&cpuapp_cpurad_ipc_shm>; diff --git a/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay new file mode 100644 index 00000000000..02db7c39272 --- /dev/null +++ b/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay @@ -0,0 +1,27 @@ +/* + * Copyright 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,bt-hci-ipc = &ipc0; + }; +}; + +ipc0: &cpuapp_cpurad_ipc { + status = "okay"; +}; + +&cpuapp_cpurad_ram0x_region { + status = "okay"; +}; + +&cpurad_bellboard { + status = "okay"; +}; + +&cpuapp_bellboard { + status = "okay"; +}; From ecd7d2cb0a4e9b990fae444a3e64a344cb82855f Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:12 +0200 Subject: [PATCH 2187/2402] Revert "[nrf fromlist] boards: nordic: nrf54h20dk: Change IPC default backend" This reverts commit 2f52b92ebdd60f68a8ee1be02e134b3ff4bc8cb6. Signed-off-by: Gerard Marull-Paretas --- .../arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-ipc_conf.dtsi | 1 - boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts | 3 +-- boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts | 3 +-- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-ipc_conf.dtsi b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-ipc_conf.dtsi index 539e80d149a..9c3d971b9bc 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-ipc_conf.dtsi +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-ipc_conf.dtsi @@ -21,7 +21,6 @@ }; cpuapp_cpurad_ipc: ipc-2-3 { - compatible = "zephyr,ipc-icbmsg"; status = "disabled"; mboxes = <&cpuapp_bellboard 18>, <&cpurad_bellboard 12>; diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts index 4eff8c7741d..7e5127f8b16 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts @@ -116,11 +116,10 @@ }; &cpuapp_cpurad_ipc { + compatible = "zephyr,ipc-icmsg-me-initiator"; mbox-names = "rx", "tx"; tx-region = <&cpuapp_cpurad_ipc_shm>; rx-region = <&cpurad_cpuapp_ipc_shm>; - tx-blocks = <32>; - rx-blocks = <32>; }; &cpuapp_cpuppr_ipc { diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts index 9e3dacbeb32..30fdf7286d5 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts @@ -50,11 +50,10 @@ }; &cpuapp_cpurad_ipc { + compatible = "zephyr,ipc-icmsg-me-follower"; mbox-names = "tx", "rx"; tx-region = <&cpurad_cpuapp_ipc_shm>; rx-region = <&cpuapp_cpurad_ipc_shm>; - tx-blocks = <32>; - rx-blocks = <32>; }; &cpurad_dma_region { From 51cf483500f04dc83481ae25ed9d1ebe2b42b90c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:13 +0200 Subject: [PATCH 2188/2402] Revert "[nrf fromlist] net: wifi: shell: Remove redundant break" This reverts commit 700870d10917960e4799926b864189d755d95f83. Signed-off-by: Gerard Marull-Paretas --- subsys/net/l2/wifi/wifi_shell.c | 1 + 1 file changed, 1 insertion(+) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index b938a80bc4b..5578444acc6 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -565,6 +565,7 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv break; case 'h': return -ENOEXEC; + break; default: PR_ERROR("Invalid option %c\n", opt); shell_help(sh); From f1c5f5a74c76cfad486dbb5975f023b28e365356 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:13 +0200 Subject: [PATCH 2189/2402] Revert "[nrf fromlist] net: wifi: shell: Correct help text for `connect` command" This reverts commit 57e78845ad43eac40c05550507435c7123517174. Signed-off-by: Gerard Marull-Paretas --- subsys/net/l2/wifi/wifi_shell.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 5578444acc6..995e39cbbd2 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -1899,7 +1899,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_commands, "[-c --channel]: Channel that needs to be scanned for connection. 0:any channel.\n" "[-b, --band] 0: any band (2:2.4GHz, 5:5GHz, 6:6GHz]\n" "[-p, --psk]: Passphrase (valid only for secure SSIDs)\n" - "[-k, --key-mgmt]: Key Management type\n" + "[-k, --key-mgmt]: Key Management type (valid only for secure SSIDs)\n" "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP, 7: WPA-PSK\n" "[-w, --ieee-80211w]: MFP (optional: needs security type to be specified)\n" ": 0:Disable, 1:Optional, 2:Required.\n" From d815f1dd09ac140546645d15c15a51b639b26d4b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:13 +0200 Subject: [PATCH 2190/2402] Revert "[nrf fromtree] net: wifi: shell: update wifi ap enable to use get opt parsing" This reverts commit 55541273196045fc112c4b97e46a914d0e915291. Signed-off-by: Gerard Marull-Paretas --- subsys/net/l2/wifi/wifi_shell.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 995e39cbbd2..cd4fa7b503e 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -496,8 +496,12 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv } break; case 'p': - params->psk = optarg; - params->psk_length = strlen(params->psk); + if (secure_connection) { + params->psk = optarg; + params->psk_length = strlen(params->psk); + } else { + PR_WARNING("Passphrase provided without security configuration\n"); + } break; case 'c': long channel = strtol(optarg, &endptr, 10); @@ -564,7 +568,7 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv ¶ms->bssid[4], ¶ms->bssid[5]); break; case 'h': - return -ENOEXEC; + shell_help(sh); break; default: PR_ERROR("Invalid option %c\n", opt); @@ -572,9 +576,7 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv return -EINVAL; } } - if (params->psk && !secure_connection) { - PR_WARNING("Passphrase provided without security configuration\n"); - } + return 0; } @@ -1242,7 +1244,7 @@ static int cmd_wifi_ap_enable(const struct shell *sh, size_t argc, int ret; context.sh = sh; - if (__wifi_args_to_params(sh, argc, &argv[0], &cnx_params, WIFI_MODE_AP)) { + if (__wifi_args_to_params(sh, argc - 1, &argv[1], &cnx_params, WIFI_MODE_AP)) { shell_help(sh); return -ENOEXEC; } @@ -1839,18 +1841,15 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_cmd_ap, cmd_wifi_ap_disable, 1, 0), SHELL_CMD_ARG(enable, NULL, - "-s --ssid=\n" - "-c --channel=\n" - "-p --passphrase= (valid only for secure SSIDs)\n" - "-k --key-mgmt= (valid only for secure SSIDs)\n" + "\"\"\n" + "\n" + "[PSK: valid only for secure SSIDs]\n" + "[Security type: valid only for secure SSIDs]\n" "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP, 7: WPA-PSK\n" - "-w --ieee-80211w= (optional: needs security type to be specified)\n" - "0:Disable, 1:Optional, 2:Required\n" - "-b --band= (2 -2.6GHz, 5 - 5Ghz, 6 - 6GHz)\n" - "-m --bssid=\n" - "-h --help (prints help)", + "[MFP (optional: needs security type to be specified)]\n" + ": 0:Disable, 1:Optional, 2:Required.\n", cmd_wifi_ap_enable, - 2, 13), + 3, 3), SHELL_CMD_ARG(stations, NULL, "List stations connected to the AP", cmd_wifi_ap_stations, From a2b4cdba2be687afb6d5ca3351bc0243440bcab8 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:13 +0200 Subject: [PATCH 2191/2402] Revert "[nrf fromtree] net: wifi: shell: Support BSSID configuration" This reverts commit edb5148d0ea4823860920c652511df1c78909200. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/net/wifi_mgmt.h | 2 -- subsys/net/l2/wifi/wifi_shell.c | 15 +++------------ 2 files changed, 3 insertions(+), 14 deletions(-) diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h index 70fd5978fba..f8fb7893234 100644 --- a/include/zephyr/net/wifi_mgmt.h +++ b/include/zephyr/net/wifi_mgmt.h @@ -352,8 +352,6 @@ struct wifi_connect_req_params { enum wifi_security_type security; /** MFP options */ enum wifi_mfp_options mfp; - /** BSSID */ - uint8_t bssid[WIFI_MAC_ADDR_LEN]; /** Connect timeout in seconds, SYS_FOREVER_MS for no timeout */ int timeout; }; diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index cd4fa7b503e..871680a1705 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -477,7 +477,7 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv params->security = WIFI_SECURITY_TYPE_NONE; params->mfp = WIFI_MFP_OPTIONAL; - while ((opt = getopt_long(argc, argv, "s:p:k:w:b:c:m:h", long_options, &opt_index)) != -1) { + while ((opt = getopt_long(argc, argv, "s:p:k:w:b:c:h", long_options, &opt_index)) != -1) { state = getopt_state_get(); switch (opt) { case 's': @@ -561,12 +561,6 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv } params->mfp = atoi(optarg); break; - case 'm': - sscanf(optarg, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", - ¶ms->bssid[0], ¶ms->bssid[1], - ¶ms->bssid[2], ¶ms->bssid[3], - ¶ms->bssid[4], ¶ms->bssid[5]); - break; case 'h': shell_help(sh); break; @@ -576,7 +570,6 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv return -EINVAL; } } - return 0; } @@ -1901,11 +1894,9 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_commands, "[-k, --key-mgmt]: Key Management type (valid only for secure SSIDs)\n" "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP, 7: WPA-PSK\n" "[-w, --ieee-80211w]: MFP (optional: needs security type to be specified)\n" - ": 0:Disable, 1:Optional, 2:Required.\n" - "[-m, --bssid]: MAC address of the AP (BSSID).\n" - "[-h, --help]: Print out the help for the connect command.\n", + ": 0:Disable, 1:Optional, 2:Required.\n", cmd_wifi_connect, - 2, 7), + 2, 5), SHELL_CMD_ARG(disconnect, NULL, "Disconnect from the Wi-Fi AP.\n", cmd_wifi_disconnect, 1, 0), From e898600b85345eae43611358470ecf8a613a3bea Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:13 +0200 Subject: [PATCH 2192/2402] Revert "[nrf fromtree] net: wifi: shell: Use getopt API for connect options" This reverts commit 512023e7f16a413144b20c76dffd3b492c9505e6. Signed-off-by: Gerard Marull-Paretas --- subsys/net/l2/wifi/wifi_shell.c | 204 ++++++++++++++++++-------------- 1 file changed, 114 insertions(+), 90 deletions(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 871680a1705..c512612e7ed 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -442,69 +442,73 @@ static void wifi_mgmt_event_handler(struct net_mgmt_event_callback *cb, } } -static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv[], +static int __wifi_args_to_params(size_t argc, char *argv[], struct wifi_connect_req_params *params, enum wifi_iface_mode iface_mode) { char *endptr; int idx = 1; - struct getopt_state *state; - int opt; - bool secure_connection = false; - static struct option long_options[] = {{"ssid", required_argument, 0, 's'}, - {"passphrase", required_argument, 0, 'p'}, - {"key-mgmt", required_argument, 0, 'k'}, - {"ieee-80211w", required_argument, 0, 'w'}, - {"bssid", required_argument, 0, 'm'}, - {"band", required_argument, 0, 'b'}, - {"channel", required_argument, 0, 'c'}, - {"help", no_argument, 0, 'h'}, - {0, 0, 0, 0}}; - int opt_index = 0; - uint8_t band; - const uint8_t all_bands[] = { - WIFI_FREQ_BAND_2_4_GHZ, - WIFI_FREQ_BAND_5_GHZ, - WIFI_FREQ_BAND_6_GHZ - }; - bool found = false; - char bands_str[MAX_BANDS_STR_LEN] = {0}; - size_t offset = 0; + const struct shell *sh = context.sh; /* Defaults */ params->band = WIFI_FREQ_BAND_UNKNOWN; params->channel = WIFI_CHANNEL_ANY; params->security = WIFI_SECURITY_TYPE_NONE; - params->mfp = WIFI_MFP_OPTIONAL; - while ((opt = getopt_long(argc, argv, "s:p:k:w:b:c:h", long_options, &opt_index)) != -1) { - state = getopt_state_get(); - switch (opt) { - case 's': - params->ssid = optarg; - params->ssid_length = strlen(params->ssid); - if (params->ssid_length > WIFI_SSID_MAX_LEN) { - PR_WARNING("SSID too long (max %d characters)\n", - WIFI_SSID_MAX_LEN); - return -EINVAL; - } - break; - case 'k': - params->security = atoi(optarg); - if (params->security) { - secure_connection = true; + /* SSID */ + params->ssid = argv[0]; + params->ssid_length = strlen(params->ssid); + if (params->ssid_length > WIFI_SSID_MAX_LEN) { + PR_WARNING("SSID too long (max %d characters)\n", + WIFI_SSID_MAX_LEN); + return -EINVAL; + } + + /* Channel (optional: STA, mandatory: AP) */ + if ((idx < argc) && (strlen(argv[idx]) <= 3)) { + uint8_t band; + long channel = strtol(argv[idx], &endptr, 10); + const uint8_t all_bands[] = {WIFI_FREQ_BAND_2_4_GHZ, + WIFI_FREQ_BAND_5_GHZ, + WIFI_FREQ_BAND_6_GHZ}; + bool found = false; + char bands_str[MAX_BANDS_STR_LEN] = {0}; + size_t offset = 0; + + if (*endptr != '\0') { + PR_ERROR("Failed to parse channel: %s: endp: %s, err: %s\n", + argv[idx], + endptr, + strerror(errno)); + return -EINVAL; + } + + if (iface_mode == WIFI_MODE_INFRA) { + if (channel < 0) { + /* Negative channel means band */ + switch (-channel) { + case 2: + params->band = WIFI_FREQ_BAND_2_4_GHZ; + break; + case 5: + params->band = WIFI_FREQ_BAND_5_GHZ; + break; + case 6: + params->band = WIFI_FREQ_BAND_6_GHZ; + break; + default: + PR_ERROR("Invalid band: %ld\n", channel); + return -EINVAL; + } } - break; - case 'p': - if (secure_connection) { - params->psk = optarg; - params->psk_length = strlen(params->psk); - } else { - PR_WARNING("Passphrase provided without security configuration\n"); + } else { + if (channel < 0) { + PR_ERROR("Invalid channel: %ld\n", channel); + return -EINVAL; } - break; - case 'c': - long channel = strtol(optarg, &endptr, 10); + } + + if (channel > 0) { for (band = 0; band < ARRAY_SIZE(all_bands); band++) { offset += snprintf(bands_str + offset, sizeof(bands_str) - offset, @@ -533,43 +537,63 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv } params->channel = channel; - break; - case 'b': - if (iface_mode == WIFI_MODE_INFRA) { - switch (atoi(optarg)) { - case 2: - params->band = WIFI_FREQ_BAND_2_4_GHZ; - break; - case 5: - params->band = WIFI_FREQ_BAND_5_GHZ; - break; - case 6: - params->band = WIFI_FREQ_BAND_6_GHZ; - break; - default: - PR_ERROR("Invalid band: %d\n", atoi(optarg)); + } + idx++; + } + + if ((idx == 1) && (iface_mode == WIFI_MODE_AP)) { + PR_ERROR("Invalid channel: %s\n", argv[idx]); + return -EINVAL; + } + + /* PSK (optional) */ + if (idx < argc) { + params->psk = argv[idx]; + params->psk_length = strlen(argv[idx]); + /* Defaults */ + params->security = WIFI_SECURITY_TYPE_PSK; + params->mfp = WIFI_MFP_OPTIONAL; + idx++; + + /* Security type (optional) */ + if (idx < argc) { + unsigned int security = strtol(argv[idx], &endptr, 10); + + if (security <= WIFI_SECURITY_TYPE_MAX) { + params->security = security; + } + idx++; + + /* MFP (optional) */ + if (idx < argc) { + unsigned int mfp = strtol(argv[idx], &endptr, 10); + + if (security == WIFI_SECURITY_TYPE_NONE || + security == WIFI_SECURITY_TYPE_WPA_PSK) { + PR_ERROR("MFP not supported for security type %s\n", + wifi_security_txt(security)); return -EINVAL; } + + if (mfp <= WIFI_MFP_REQUIRED) { + params->mfp = mfp; + } + idx++; } - break; - case 'w': - if (params->security == WIFI_SECURITY_TYPE_NONE || - params->security == WIFI_SECURITY_TYPE_WPA_PSK) { - PR_ERROR("MFP not supported for security type %s\n", - wifi_security_txt(params->security)); - return -EINVAL; - } - params->mfp = atoi(optarg); - break; - case 'h': - shell_help(sh); - break; - default: - PR_ERROR("Invalid option %c\n", opt); - shell_help(sh); + } + + if (params->psk_length < WIFI_PSK_MIN_LEN || + (params->security != WIFI_SECURITY_TYPE_SAE && + params->psk_length > WIFI_PSK_MAX_LEN) || + (params->security == WIFI_SECURITY_TYPE_SAE && + params->psk_length > WIFI_SAE_PSWD_MAX_LEN)) { + PR_ERROR("Invalid PSK length (%d) for security type %s\n", + params->psk_length, + wifi_security_txt(params->security)); return -EINVAL; } } + return 0; } @@ -580,7 +604,7 @@ static int cmd_wifi_connect(const struct shell *sh, size_t argc, struct wifi_connect_req_params cnx_params = { 0 }; context.sh = sh; - if (__wifi_args_to_params(sh, argc, argv, &cnx_params, WIFI_MODE_INFRA)) { + if (__wifi_args_to_params(argc - 1, &argv[1], &cnx_params, WIFI_MODE_INFRA)) { shell_help(sh); return -ENOEXEC; } @@ -1237,7 +1261,7 @@ static int cmd_wifi_ap_enable(const struct shell *sh, size_t argc, int ret; context.sh = sh; - if (__wifi_args_to_params(sh, argc - 1, &argv[1], &cnx_params, WIFI_MODE_AP)) { + if (__wifi_args_to_params(argc - 1, &argv[1], &cnx_params, WIFI_MODE_AP)) { shell_help(sh); return -ENOEXEC; } @@ -1887,16 +1911,16 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_commands, SHELL_CMD(ap, &wifi_cmd_ap, "Access Point mode commands.\n", NULL), SHELL_CMD_ARG(connect, NULL, "Connect to a Wi-Fi AP\n" - "<-s --ssid \"\">: SSID.\n" - "[-c --channel]: Channel that needs to be scanned for connection. 0:any channel.\n" - "[-b, --band] 0: any band (2:2.4GHz, 5:5GHz, 6:6GHz]\n" - "[-p, --psk]: Passphrase (valid only for secure SSIDs)\n" - "[-k, --key-mgmt]: Key Management type (valid only for secure SSIDs)\n" + "\"\"\n" + "[channel number/band: > 0:Channel, 0:any channel,\n" + "< 0:band (-2:2.4GHz, -5:5GHz, -6:6GHz]\n" + "[PSK: valid only for secure SSIDs]\n" + "[Security type: valid only for secure SSIDs]\n" "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP, 7: WPA-PSK\n" - "[-w, --ieee-80211w]: MFP (optional: needs security type to be specified)\n" + "[MFP (optional: needs security type to be specified)]\n" ": 0:Disable, 1:Optional, 2:Required.\n", cmd_wifi_connect, - 2, 5), + 2, 4), SHELL_CMD_ARG(disconnect, NULL, "Disconnect from the Wi-Fi AP.\n", cmd_wifi_disconnect, 1, 0), From add80a7f5b8ef314cadd0162e7a79ae2e60077fe Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:14 +0200 Subject: [PATCH 2193/2402] Revert "[nrf fromtree] tests: drivers: clock_control: Add nRF54L15 to platform allow" This reverts commit d4ee5b3ce2ae353412430857cba05dfe846049cd. Signed-off-by: Gerard Marull-Paretas --- .../clock_control/clock_control_api/testcase.yaml | 2 -- .../clock_control/nrf_clock_calibration/testcase.yaml | 1 - .../clock_control/nrf_lf_clock_start/testcase.yaml | 9 --------- tests/drivers/clock_control/onoff/testcase.yaml | 1 - 4 files changed, 13 deletions(-) diff --git a/tests/drivers/clock_control/clock_control_api/testcase.yaml b/tests/drivers/clock_control/clock_control_api/testcase.yaml index 42ca3013a0f..be789c8382a 100644 --- a/tests/drivers/clock_control/clock_control_api/testcase.yaml +++ b/tests/drivers/clock_control/clock_control_api/testcase.yaml @@ -7,7 +7,6 @@ tests: - nrf51dk_nrf51422 - nrf52dk_nrf52832 - nrf52840dk_nrf52840 - - nrf54l15pdk_nrf54l15_cpuapp - nrf9160dk_nrf9160 integration_platforms: - nrf51dk_nrf51422 @@ -19,7 +18,6 @@ tests: - nrf51dk_nrf51422 - nrf52dk_nrf52832 - nrf52840dk_nrf52840 - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf51dk_nrf51422 extra_args: CONF_FILE="nrf_lfclk_rc.conf" diff --git a/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml b/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml index 8b28612378d..092471d30e4 100644 --- a/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml +++ b/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml @@ -7,6 +7,5 @@ tests: - nrf51dk_nrf51422 - nrf52dk_nrf52832 - nrf52840dk_nrf52840 - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf51dk_nrf51422 diff --git a/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml b/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml index e24dcb83786..f4940d79896 100644 --- a/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml +++ b/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml @@ -13,7 +13,6 @@ tests: - nrf9160dk_nrf9160 - nrf5340dk_nrf5340_cpuapp - nrf5340dk_nrf5340_cpunet - - nrf54l15pdk_nrf54l15_cpuapp extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_STABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y @@ -28,7 +27,6 @@ tests: - nrf9160dk_nrf9160 - nrf5340dk_nrf5340_cpuapp - nrf5340dk_nrf5340_cpunet - - nrf54l15pdk_nrf54l15_cpuapp extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y @@ -43,7 +41,6 @@ tests: - nrf9160dk_nrf9160 - nrf5340dk_nrf5340_cpuapp - nrf5340dk_nrf5340_cpunet - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf51dk_nrf51422 extra_configs: @@ -57,7 +54,6 @@ tests: - nrf52840dk_nrf52840 - nrf5340dk_nrf5340_cpuapp - nrf5340dk_nrf5340_cpunet - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf51dk_nrf51422 extra_configs: @@ -71,7 +67,6 @@ tests: - nrf52840dk_nrf52840 - nrf5340dk_nrf5340_cpuapp - nrf5340dk_nrf5340_cpunet - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf51dk_nrf51422 extra_configs: @@ -85,7 +80,6 @@ tests: - nrf52840dk_nrf52840 - nrf5340dk_nrf5340_cpuapp - nrf5340dk_nrf5340_cpunet - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf51dk_nrf51422 extra_configs: @@ -99,7 +93,6 @@ tests: - nrf52840dk_nrf52840 - nrf5340dk_nrf5340_cpuapp - nrf5340dk_nrf5340_cpunet - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf51dk_nrf51422 extra_configs: @@ -113,7 +106,6 @@ tests: - nrf52840dk_nrf52840 - nrf5340dk_nrf5340_cpuapp - nrf5340dk_nrf5340_cpunet - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf51dk_nrf51422 extra_configs: @@ -127,7 +119,6 @@ tests: - nrf52840dk_nrf52840 - nrf5340dk_nrf5340_cpuapp - nrf5340dk_nrf5340_cpunet - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf51dk_nrf51422 extra_configs: diff --git a/tests/drivers/clock_control/onoff/testcase.yaml b/tests/drivers/clock_control/onoff/testcase.yaml index cf6d4b3f8cd..a6e03d9a0ec 100644 --- a/tests/drivers/clock_control/onoff/testcase.yaml +++ b/tests/drivers/clock_control/onoff/testcase.yaml @@ -7,7 +7,6 @@ tests: - nrf51dk_nrf51422 - nrf52dk_nrf52832 - nrf52840dk_nrf52840 - - nrf54l15pdk_nrf54l15_cpuapp - nrf9160dk_nrf9160 integration_platforms: - nrf51dk_nrf51422 From 4afff9798b5b891b48a2f6fdd6820b2eae3f2ee1 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:14 +0200 Subject: [PATCH 2194/2402] Revert "[nrf fromtree] Bluetooth: Audio: Add iso_chan to bt_bap_ep_info" This reverts commit 3ae75850e43503aecbe481bfec7a51872e2aa946. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/bluetooth/audio/bap.h | 3 --- subsys/bluetooth/audio/bap_stream.c | 2 -- 2 files changed, 5 deletions(-) diff --git a/include/zephyr/bluetooth/audio/bap.h b/include/zephyr/bluetooth/audio/bap.h index a0719bd939d..f61accde211 100644 --- a/include/zephyr/bluetooth/audio/bap.h +++ b/include/zephyr/bluetooth/audio/bap.h @@ -397,9 +397,6 @@ struct bt_bap_ep_info { /** Capabilities type */ enum bt_audio_dir dir; - /** The isochronous channel associated with the endpoint. */ - struct bt_iso_chan *iso_chan; - /** @brief True if the stream associated with the endpoint is able to send data */ bool can_send; diff --git a/subsys/bluetooth/audio/bap_stream.c b/subsys/bluetooth/audio/bap_stream.c index dc776c6483d..2f1cf71e8dd 100644 --- a/subsys/bluetooth/audio/bap_stream.c +++ b/subsys/bluetooth/audio/bap_stream.c @@ -107,10 +107,8 @@ int bt_bap_ep_get_info(const struct bt_bap_ep *ep, struct bt_bap_ep_info *info) if (ep->iso == NULL) { info->paired_ep = NULL; - info->iso_chan = NULL; } else { info->paired_ep = bt_bap_iso_get_paired_ep(ep); - info->iso_chan = &ep->iso->chan; } info->can_send = false; From f894e66fcf11931803dd54159f60ae1d9f11c595 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:14 +0200 Subject: [PATCH 2195/2402] Revert "[nrf fromtree] dts: arm: nordic: keep NFCT disabled by default" This reverts commit 70729fcad3c56dd6f84e82c5f2b0b62e99b4301c. Signed-off-by: Gerard Marull-Paretas --- dts/arm/nordic/nrf52832.dtsi | 2 +- dts/arm/nordic/nrf52833.dtsi | 2 +- dts/arm/nordic/nrf52840.dtsi | 2 +- dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/dts/arm/nordic/nrf52832.dtsi b/dts/arm/nordic/nrf52832.dtsi index 13ee05226b7..ed5a21b9935 100644 --- a/dts/arm/nordic/nrf52832.dtsi +++ b/dts/arm/nordic/nrf52832.dtsi @@ -177,7 +177,7 @@ compatible = "nordic,nrf-nfct"; reg = <0x40005000 0x1000>; interrupts = <5 NRF_DEFAULT_IRQ_PRIORITY>; - status = "disabled"; + status = "okay"; }; gpiote: gpiote0: gpiote@40006000 { diff --git a/dts/arm/nordic/nrf52833.dtsi b/dts/arm/nordic/nrf52833.dtsi index f22cb36bc14..5ac9cb2d2f8 100644 --- a/dts/arm/nordic/nrf52833.dtsi +++ b/dts/arm/nordic/nrf52833.dtsi @@ -184,7 +184,7 @@ compatible = "nordic,nrf-nfct"; reg = <0x40005000 0x1000>; interrupts = <5 NRF_DEFAULT_IRQ_PRIORITY>; - status = "disabled"; + status = "okay"; }; gpiote: gpiote0: gpiote@40006000 { diff --git a/dts/arm/nordic/nrf52840.dtsi b/dts/arm/nordic/nrf52840.dtsi index c105da55c76..8efe49a3c91 100644 --- a/dts/arm/nordic/nrf52840.dtsi +++ b/dts/arm/nordic/nrf52840.dtsi @@ -179,7 +179,7 @@ compatible = "nordic,nrf-nfct"; reg = <0x40005000 0x1000>; interrupts = <5 NRF_DEFAULT_IRQ_PRIORITY>; - status = "disabled"; + status = "okay"; }; gpiote: gpiote0: gpiote@40006000 { diff --git a/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi b/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi index c9f1ff2fae9..94e764ec52c 100644 --- a/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi +++ b/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi @@ -449,7 +449,7 @@ nfct: nfct@2d000 { compatible = "nordic,nrf-nfct"; reg = <0x2d000 0x1000>; interrupts = <45 NRF_DEFAULT_IRQ_PRIORITY>; - status = "disabled"; + status = "okay"; }; mutex: mutex@30000 { From 344264945c8ec2df543226229eddba870092adb8 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:14 +0200 Subject: [PATCH 2196/2402] Revert "[nrf fromtree] net: dns-sd: Do not use sockaddr struct directly" This reverts commit 2cad7ad67aa16b023968463d77e26755955bc855. Signed-off-by: Gerard Marull-Paretas --- subsys/net/lib/dns/dns_sd.c | 37 +++++++++++++++---------------------- 1 file changed, 15 insertions(+), 22 deletions(-) diff --git a/subsys/net/lib/dns/dns_sd.c b/subsys/net/lib/dns/dns_sd.c index 5d4dff10ef9..fa55a24271b 100644 --- a/subsys/net/lib/dns/dns_sd.c +++ b/subsys/net/lib/dns/dns_sd.c @@ -667,40 +667,33 @@ static bool port_in_use_sockaddr(uint16_t proto, uint16_t port, || net_context_port_in_use(proto, port, anyp); } -static bool port_in_use(uint16_t proto, uint16_t port, - const struct in_addr *addr4, - const struct in6_addr *addr6) +static bool port_in_use(uint16_t proto, uint16_t port, const struct in_addr *addr4, + const struct in6_addr *addr6) { - bool ret = false; + bool r; + struct sockaddr sa; if (addr4 != NULL) { - struct sockaddr_in sa = { 0 }; - - sa.sin_family = AF_INET; - sa.sin_addr = *addr4; + net_sin(&sa)->sin_family = AF_INET; + net_sin(&sa)->sin_addr = *addr4; - ret = port_in_use_sockaddr(proto, port, - (struct sockaddr *)&sa); - if (ret) { - goto out; + r = port_in_use_sockaddr(proto, port, &sa); + if (r) { + return true; } } if (addr6 != NULL) { - struct sockaddr_in6 sa = { 0 }; - - sa.sin6_family = AF_INET6; - sa.sin6_addr = *addr6; + net_sin6(&sa)->sin6_family = AF_INET6; + net_sin6(&sa)->sin6_addr = *addr6; - ret = port_in_use_sockaddr(proto, port, - (struct sockaddr *)&sa); - if (ret) { - goto out; + r = port_in_use_sockaddr(proto, port, &sa); + if (r) { + return true; } } -out: - return ret; + return false; } #else /* CONFIG_NET_TEST */ static inline bool port_in_use(uint16_t proto, uint16_t port, const struct in_addr *addr4, From cfdf3f7e9ac8082e10453edd4772b67b424506da Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:14 +0200 Subject: [PATCH 2197/2402] Revert "[nrf fromtree] tests: drivers: pwm: add support for nRF54 devices" This reverts commit 66fec84a3e19b7661aa0300d257d07eaf9b5a287. Signed-off-by: Gerard Marull-Paretas --- .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 20 ------------------- .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 20 ------------------- tests/drivers/pwm/pwm_api/src/test_pwm.c | 5 +---- tests/drivers/pwm/pwm_api/testcase.yaml | 2 +- 4 files changed, 2 insertions(+), 45 deletions(-) delete mode 100644 tests/drivers/pwm/pwm_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay delete mode 100644 tests/drivers/pwm/pwm_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay diff --git a/tests/drivers/pwm/pwm_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/pwm/pwm_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay deleted file mode 100644 index c483d27f569..00000000000 --- a/tests/drivers/pwm/pwm_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ /dev/null @@ -1,20 +0,0 @@ -&pinctrl { - pwm_default: pwm_default { - group1 { - psels = ; - }; - }; - pwm_sleep: pwm_sleep { - group1 { - psels = ; - low-power-enable; - }; - }; -}; - -&pwm130 { - status = "okay"; - pinctrl-0 = <&pwm_default>; - pinctrl-1 = <&pwm_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/tests/drivers/pwm/pwm_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/pwm/pwm_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay deleted file mode 100644 index 013653617e4..00000000000 --- a/tests/drivers/pwm/pwm_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay +++ /dev/null @@ -1,20 +0,0 @@ -&pinctrl { - pwm_default: pwm_default { - group1 { - psels = ; - }; - }; - pwm_sleep: pwm_sleep { - group1 { - psels = ; - low-power-enable; - }; - }; -}; - -&pwm20 { - status = "okay"; - pinctrl-0 = <&pwm_default>; - pinctrl-1 = <&pwm_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/tests/drivers/pwm/pwm_api/src/test_pwm.c b/tests/drivers/pwm/pwm_api/src/test_pwm.c index f8e71d1cb24..867025d99b1 100644 --- a/tests/drivers/pwm/pwm_api/src/test_pwm.c +++ b/tests/drivers/pwm/pwm_api/src/test_pwm.c @@ -38,9 +38,6 @@ #elif DT_NODE_HAS_STATUS(DT_ALIAS(pwm_3), okay) #define PWM_DEV_NODE DT_ALIAS(pwm_3) -#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pwm) -#define PWM_DEV_NODE DT_INST(0, nordic_nrf_pwm) - #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_pwm) #define PWM_DEV_NODE DT_INST(0, st_stm32_pwm) @@ -79,7 +76,7 @@ #if defined CONFIG_BOARD_SAM_E70_XPLAINED #define DEFAULT_PWM_PORT 2 /* PWM on EXT2 connector, pin 8 */ #elif defined CONFIG_PWM_NRFX -#define DEFAULT_PWM_PORT 0 +#define DEFAULT_PWM_PORT DT_PROP(DT_ALIAS(pwm_0), ch0_pin) #elif defined CONFIG_BOARD_ADAFRUIT_ITSYBITSY_M4_EXPRESS #define DEFAULT_PWM_PORT 2 /* TCC1/WO[2] on PA18 (D7) */ #elif defined CONFIG_BOARD_MIMXRT685_EVK diff --git a/tests/drivers/pwm/pwm_api/testcase.yaml b/tests/drivers/pwm/pwm_api/testcase.yaml index aca9172fc96..608a4d0a0e1 100644 --- a/tests/drivers/pwm/pwm_api/testcase.yaml +++ b/tests/drivers/pwm/pwm_api/testcase.yaml @@ -6,5 +6,5 @@ tests: - userspace filter: dt_alias_exists("pwm-0") or dt_alias_exists("pwm-1") or dt_alias_exists("pwm-2") or dt_alias_exists("pwm-3") or dt_compat_enabled("st,stm32-pwm") - or dt_compat_enabled("intel,blinky-pwm") or dt_compat_enabled("nordic,nrf-pwm") + or dt_compat_enabled("intel,blinky-pwm") depends_on: pwm From 94bd204845c25d08c7fa9fb61ba7e188746df6f2 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:15 +0200 Subject: [PATCH 2198/2402] Revert "[nrf fromtree] boards: nordic: nrf54l15pdk: mark PWM as supported" This reverts commit ecdf156a7c546417559d2abcdba9cfa696d89116. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml index e8e69adfc6d..de5ce29d162 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml @@ -14,7 +14,6 @@ flash: 1536 supported: - gpio - i2c - - pwm - spi - watchdog - i2s From 6b9824e0970877931df9dd369964db0f5e5cbd7c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:15 +0200 Subject: [PATCH 2199/2402] Revert "[nrf fromtree] drivers: pwm: add support for nRF54 devices" This reverts commit 3b0c038225cd86ed4fabe5fe937c61cff6bd6be2. Signed-off-by: Gerard Marull-Paretas --- drivers/pwm/Kconfig.nrfx | 8 -------- drivers/pwm/pwm_nrfx.c | 32 -------------------------------- 2 files changed, 40 deletions(-) diff --git a/drivers/pwm/Kconfig.nrfx b/drivers/pwm/Kconfig.nrfx index 933fe7cb29c..9a84c5fd21b 100644 --- a/drivers/pwm/Kconfig.nrfx +++ b/drivers/pwm/Kconfig.nrfx @@ -9,14 +9,6 @@ config PWM_NRFX select NRFX_PWM1 if HAS_HW_NRF_PWM1 select NRFX_PWM2 if HAS_HW_NRF_PWM2 select NRFX_PWM3 if HAS_HW_NRF_PWM3 - select NRFX_PWM20 if HAS_HW_NRF_PWM20 - select NRFX_PWM21 if HAS_HW_NRF_PWM21 - select NRFX_PWM22 if HAS_HW_NRF_PWM22 - select NRFX_PWM120 if HAS_HW_NRF_PWM120 - select NRFX_PWM130 if HAS_HW_NRF_PWM130 - select NRFX_PWM131 if HAS_HW_NRF_PWM131 - select NRFX_PWM132 if HAS_HW_NRF_PWM132 - select NRFX_PWM133 if HAS_HW_NRF_PWM133 select PINCTRL help Enable support for nrfx Hardware PWM driver for nRF52 MCU series. diff --git a/drivers/pwm/pwm_nrfx.c b/drivers/pwm/pwm_nrfx.c index 9feacb2c10b..52257dce104 100644 --- a/drivers/pwm/pwm_nrfx.c +++ b/drivers/pwm/pwm_nrfx.c @@ -391,35 +391,3 @@ PWM_NRFX_DEVICE(2); #ifdef CONFIG_HAS_HW_NRF_PWM3 PWM_NRFX_DEVICE(3); #endif - -#ifdef CONFIG_HAS_HW_NRF_PWM20 -PWM_NRFX_DEVICE(20); -#endif - -#ifdef CONFIG_HAS_HW_NRF_PWM21 -PWM_NRFX_DEVICE(21); -#endif - -#ifdef CONFIG_HAS_HW_NRF_PWM22 -PWM_NRFX_DEVICE(22); -#endif - -#ifdef CONFIG_HAS_HW_NRF_PWM120 -PWM_NRFX_DEVICE(120); -#endif - -#ifdef CONFIG_HAS_HW_NRF_PWM130 -PWM_NRFX_DEVICE(130); -#endif - -#ifdef CONFIG_HAS_HW_NRF_PWM131 -PWM_NRFX_DEVICE(131); -#endif - -#ifdef CONFIG_HAS_HW_NRF_PWM132 -PWM_NRFX_DEVICE(132); -#endif - -#ifdef CONFIG_HAS_HW_NRF_PWM133 -PWM_NRFX_DEVICE(133); -#endif From b81198bc6c15a7a8e3140f100a153fc055bbeed5 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:15 +0200 Subject: [PATCH 2200/2402] Revert "[nrf fromtree] modules: hal_nordic: nrfx: add support for nRF54 PWM" This reverts commit 1730143bcf32278f446e310ad6a5458a4408d191. Signed-off-by: Gerard Marull-Paretas --- modules/hal_nordic/nrfx/Kconfig | 40 --------------------------- modules/hal_nordic/nrfx/nrfx_config.h | 24 ---------------- 2 files changed, 64 deletions(-) diff --git a/modules/hal_nordic/nrfx/Kconfig b/modules/hal_nordic/nrfx/Kconfig index 22758742ef4..7d34f2f289d 100644 --- a/modules/hal_nordic/nrfx/Kconfig +++ b/modules/hal_nordic/nrfx/Kconfig @@ -184,46 +184,6 @@ config NRFX_PWM3 depends on $(dt_nodelabel_has_compat,pwm3,$(DT_COMPAT_NORDIC_NRF_PWM)) select NRFX_PWM -config NRFX_PWM20 - bool "PWM20 driver instance" - depends on $(dt_nodelabel_has_compat,pwm20,$(DT_COMPAT_NORDIC_NRF_PWM)) - select NRFX_PWM - -config NRFX_PWM21 - bool "PWM21 driver instance" - depends on $(dt_nodelabel_has_compat,pwm21,$(DT_COMPAT_NORDIC_NRF_PWM)) - select NRFX_PWM - -config NRFX_PWM22 - bool "PWM22 driver instance" - depends on $(dt_nodelabel_has_compat,pwm22,$(DT_COMPAT_NORDIC_NRF_PWM)) - select NRFX_PWM - -config NRFX_PWM120 - bool "PWM120 driver instance" - depends on $(dt_nodelabel_has_compat,pwm120,$(DT_COMPAT_NORDIC_NRF_PWM)) - select NRFX_PWM - -config NRFX_PWM130 - bool "PWM130 driver instance" - depends on $(dt_nodelabel_has_compat,pwm130,$(DT_COMPAT_NORDIC_NRF_PWM)) - select NRFX_PWM - -config NRFX_PWM131 - bool "PWM131 driver instance" - depends on $(dt_nodelabel_has_compat,pwm131,$(DT_COMPAT_NORDIC_NRF_PWM)) - select NRFX_PWM - -config NRFX_PWM132 - bool "PWM132 driver instance" - depends on $(dt_nodelabel_has_compat,pwm132,$(DT_COMPAT_NORDIC_NRF_PWM)) - select NRFX_PWM - -config NRFX_PWM133 - bool "PWM133 driver instance" - depends on $(dt_nodelabel_has_compat,pwm133,$(DT_COMPAT_NORDIC_NRF_PWM)) - select NRFX_PWM - config NRFX_QDEC bool diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index 4a7ae346d84..c4798d1906a 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -248,30 +248,6 @@ #ifdef CONFIG_NRFX_PWM3 #define NRFX_PWM3_ENABLED 1 #endif -#ifdef CONFIG_NRFX_PWM20 -#define NRFX_PWM20_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_PWM21 -#define NRFX_PWM21_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_PWM22 -#define NRFX_PWM22_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_PWM120 -#define NRFX_PWM120_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_PWM130 -#define NRFX_PWM130_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_PWM131 -#define NRFX_PWM131_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_PWM132 -#define NRFX_PWM132_ENABLED 1 -#endif -#ifdef CONFIG_NRFX_PWM133 -#define NRFX_PWM133_ENABLED 1 -#endif #ifdef CONFIG_NRFX_QDEC #define NRFX_QDEC_ENABLED 1 From 6547ac18282d8b2a8d49d1ad01041daa916891b0 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:15 +0200 Subject: [PATCH 2201/2402] Revert "[nrf fromtree] soc: nordic: add nRF54 PWM HAS_HW & base addr validation" This reverts commit 591e739e9611a28643a49ea9bc919667f65cfd07. Signed-off-by: Gerard Marull-Paretas --- soc/arm/nordic_nrf/validate_base_addresses.c | 8 ------- soc/common/nordic_nrf/Kconfig.peripherals | 24 -------------------- 2 files changed, 32 deletions(-) diff --git a/soc/arm/nordic_nrf/validate_base_addresses.c b/soc/arm/nordic_nrf/validate_base_addresses.c index f3c1b29b69a..04c7a1ae3cd 100644 --- a/soc/arm/nordic_nrf/validate_base_addresses.c +++ b/soc/arm/nordic_nrf/validate_base_addresses.c @@ -209,14 +209,6 @@ CHECK_DT_REG(pwm0, NRF_PWM0); CHECK_DT_REG(pwm1, NRF_PWM1); CHECK_DT_REG(pwm2, NRF_PWM2); CHECK_DT_REG(pwm3, NRF_PWM3); -CHECK_DT_REG(pwm20, NRF_PWM20); -CHECK_DT_REG(pwm21, NRF_PWM21); -CHECK_DT_REG(pwm22, NRF_PWM22); -CHECK_DT_REG(pwm120, NRF_PWM120); -CHECK_DT_REG(pwm130, NRF_PWM130); -CHECK_DT_REG(pwm131, NRF_PWM131); -CHECK_DT_REG(pwm132, NRF_PWM132); -CHECK_DT_REG(pwm133, NRF_PWM133); CHECK_DT_REG(qdec, NRF_QDEC0); /* this should be the same node as qdec0 */ CHECK_DT_REG(qdec0, NRF_QDEC0); CHECK_DT_REG(qdec1, NRF_QDEC1); diff --git a/soc/common/nordic_nrf/Kconfig.peripherals b/soc/common/nordic_nrf/Kconfig.peripherals index 39ed2e6432f..a6b62428626 100644 --- a/soc/common/nordic_nrf/Kconfig.peripherals +++ b/soc/common/nordic_nrf/Kconfig.peripherals @@ -149,30 +149,6 @@ config HAS_HW_NRF_PWM2 config HAS_HW_NRF_PWM3 def_bool $(dt_nodelabel_enabled_with_compat,pwm3,$(DT_COMPAT_NORDIC_NRF_PWM)) -config HAS_HW_NRF_PWM20 - def_bool $(dt_nodelabel_enabled_with_compat,pwm20,$(DT_COMPAT_NORDIC_NRF_PWM)) - -config HAS_HW_NRF_PWM21 - def_bool $(dt_nodelabel_enabled_with_compat,pwm21,$(DT_COMPAT_NORDIC_NRF_PWM)) - -config HAS_HW_NRF_PWM22 - def_bool $(dt_nodelabel_enabled_with_compat,pwm22,$(DT_COMPAT_NORDIC_NRF_PWM)) - -config HAS_HW_NRF_PWM120 - def_bool $(dt_nodelabel_enabled_with_compat,pwm120,$(DT_COMPAT_NORDIC_NRF_PWM)) - -config HAS_HW_NRF_PWM130 - def_bool $(dt_nodelabel_enabled_with_compat,pwm130,$(DT_COMPAT_NORDIC_NRF_PWM)) - -config HAS_HW_NRF_PWM131 - def_bool $(dt_nodelabel_enabled_with_compat,pwm131,$(DT_COMPAT_NORDIC_NRF_PWM)) - -config HAS_HW_NRF_PWM132 - def_bool $(dt_nodelabel_enabled_with_compat,pwm132,$(DT_COMPAT_NORDIC_NRF_PWM)) - -config HAS_HW_NRF_PWM133 - def_bool $(dt_nodelabel_enabled_with_compat,pwm133,$(DT_COMPAT_NORDIC_NRF_PWM)) - config HAS_HW_NRF_QDEC0 def_bool $(dt_nodelabel_enabled_with_compat,qdec0,$(DT_COMPAT_NORDIC_NRF_QDEC)) From d764d5807a572b44e5de81bee5ce5ecc419989c6 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:15 +0200 Subject: [PATCH 2202/2402] Revert "[nrf fromtree] dts: nordic: add PWM instances for nRF54 Series" This reverts commit 293ae3de1470640f70664dd3c4d7e006440012d5. Signed-off-by: Gerard Marull-Paretas --- .../nordic/nrf54l15_cpuapp_peripherals.dtsi | 24 ----------- dts/common/nordic/nrf54h20.dtsi | 40 ------------------- 2 files changed, 64 deletions(-) diff --git a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi index eb161844841..25f94241336 100644 --- a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi +++ b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi @@ -261,30 +261,6 @@ timer24: timer@ce000 { prescaler = <0>; }; -pwm20: pwm@d2000 { - compatible = "nordic,nrf-pwm"; - status = "disabled"; - reg = <0xd2000 0x1000>; - interrupts = <210 NRF_DEFAULT_IRQ_PRIORITY>; - #pwm-cells = <3>; -}; - -pwm21: pwm@d3000 { - compatible = "nordic,nrf-pwm"; - status = "disabled"; - reg = <0xd3000 0x1000>; - interrupts = <211 NRF_DEFAULT_IRQ_PRIORITY>; - #pwm-cells = <3>; -}; - -pwm22: pwm@d4000 { - compatible = "nordic,nrf-pwm"; - status = "disabled"; - reg = <0xd4000 0x1000>; - interrupts = <212 NRF_DEFAULT_IRQ_PRIORITY>; - #pwm-cells = <3>; -}; - adc: adc@d5000 { compatible = "nordic,nrf-saadc"; reg = <0xd5000 0x1000>; diff --git a/dts/common/nordic/nrf54h20.dtsi b/dts/common/nordic/nrf54h20.dtsi index ec5c4cca14f..78e4c5b6549 100644 --- a/dts/common/nordic/nrf54h20.dtsi +++ b/dts/common/nordic/nrf54h20.dtsi @@ -345,14 +345,6 @@ prescaler = <0>; }; - pwm120: pwm@8e4000 { - compatible = "nordic,nrf-pwm"; - reg = <0x8e4000 0x1000>; - status = "disabled"; - interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>; - #pwm-cells = <3>; - }; - spi120: spi@8e6000 { compatible = "nordic,nrf-spim"; reg = <0x8e6000 0x1000>; @@ -610,14 +602,6 @@ prescaler = <0>; }; - pwm130: pwm@9a4000 { - compatible = "nordic,nrf-pwm"; - reg = <0x9a4000 0x1000>; - status = "disabled"; - interrupts = <420 NRF_DEFAULT_IRQ_PRIORITY>; - #pwm-cells = <3>; - }; - i2c130: i2c@9a5000 { compatible = "nordic,nrf-twim"; reg = <0x9a5000 0x1000>; @@ -700,14 +684,6 @@ prescaler = <0>; }; - pwm131: pwm@9b4000 { - compatible = "nordic,nrf-pwm"; - reg = <0x9b4000 0x1000>; - status = "disabled"; - interrupts = <436 NRF_DEFAULT_IRQ_PRIORITY>; - #pwm-cells = <3>; - }; - i2c132: i2c@9b5000 { compatible = "nordic,nrf-twim"; reg = <0x9b5000 0x1000>; @@ -790,14 +766,6 @@ prescaler = <0>; }; - pwm132: pwm@9c4000 { - compatible = "nordic,nrf-pwm"; - reg = <0x9c4000 0x1000>; - status = "disabled"; - interrupts = <452 NRF_DEFAULT_IRQ_PRIORITY>; - #pwm-cells = <3>; - }; - i2c134: i2c@9c5000 { compatible = "nordic,nrf-twim"; reg = <0x9c5000 0x1000>; @@ -880,14 +848,6 @@ prescaler = <0>; }; - pwm133: pwm@9d4000 { - compatible = "nordic,nrf-pwm"; - reg = <0x9d4000 0x1000>; - status = "disabled"; - interrupts = <468 NRF_DEFAULT_IRQ_PRIORITY>; - #pwm-cells = <3>; - }; - i2c136: i2c@9d5000 { compatible = "nordic,nrf-twim"; reg = <0x9d5000 0x1000>; From 62bd97f2136bb2b10b2ae25f6e7a715f8914587c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:16 +0200 Subject: [PATCH 2203/2402] Revert "[nrf fromtree] manifest: update hal_nordic to have PWM fix for nRF54" This reverts commit 70a046e332a078778d3ef4e78e13b6108ae4a0bb. Signed-off-by: Gerard Marull-Paretas --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index c25c87dcd32..720e5d5a97b 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: fc2bab706f195c64d40016c9855b8acd7c235ded + revision: 7803a3e6b606ddde8df9a10108d7251a108bd7c9 path: modules/hal/nordic groups: - hal From 039e83e80d3563da8bb2edbaeb8c5a02af9caa2e Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:16 +0200 Subject: [PATCH 2204/2402] Revert "[nrf fromtree] samples: sensor: qdec: Move console regex to each test" This reverts commit 22e2d8781ef57c215b49539ae1b16fcd42b331cf. Signed-off-by: Gerard Marull-Paretas --- samples/sensor/qdec/sample.yaml | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/samples/sensor/qdec/sample.yaml b/samples/sensor/qdec/sample.yaml index 8d5652906a1..48654c582a6 100644 --- a/samples/sensor/qdec/sample.yaml +++ b/samples/sensor/qdec/sample.yaml @@ -5,18 +5,17 @@ common: tags: sensors timeout: 5 harness: console - + harness_config: + type: multi_line + ordered: true + regex: + - "Quadrature decoder sensor test" + - "Position = (.*) degrees" tests: sample.sensor.qdec_sensor: platform_allow: nucleo_f401re harness_config: fixture: fixture_mech_encoder - type: multi_line - ordered: true - regex: - - "Quadrature decoder sensor test" - - "Position = (.*) degrees" - sample.sensor.nrf_qdec_sensor: platform_allow: - nrf52840dk_nrf52840 @@ -28,8 +27,3 @@ tests: - nrf54l15pdk_nrf54l15_cpuapp harness_config: fixture: gpio_loopback - type: multi_line - ordered: true - regex: - - "Quadrature decoder sensor test" - - "Position = (.*) degrees" From 997c121e3ddb05e6a934bd5871f8e3fe334de453 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:16 +0200 Subject: [PATCH 2205/2402] Revert "[nrf fromtree] samples: sensor: qdec: Add nRF54L15 to platform allow" This reverts commit 35bde43cd1d7b516f79e70e434ca1954801dc309. Signed-off-by: Gerard Marull-Paretas --- samples/sensor/qdec/sample.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/samples/sensor/qdec/sample.yaml b/samples/sensor/qdec/sample.yaml index 48654c582a6..5849f3e00c7 100644 --- a/samples/sensor/qdec/sample.yaml +++ b/samples/sensor/qdec/sample.yaml @@ -20,10 +20,8 @@ tests: platform_allow: - nrf52840dk_nrf52840 - nrf5340dk_nrf5340_cpuapp - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf52840dk_nrf52840 - nrf5340dk_nrf5340_cpuapp - - nrf54l15pdk_nrf54l15_cpuapp harness_config: fixture: gpio_loopback From d643ed127aafb06460be7c0fb6857fbf47b86f34 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:16 +0200 Subject: [PATCH 2206/2402] Revert "[nrf noup] test-spec: include nrf54 boards in low-level test trigger" This reverts commit 3c68e19f4eb40c472b8be4fdff067c2519f7379f. Signed-off-by: Gerard Marull-Paretas --- .github/test-spec.yml | 2 -- 1 file changed, 2 deletions(-) diff --git a/.github/test-spec.yml b/.github/test-spec.yml index f0ac25e3f27..a4776a433f3 100644 --- a/.github/test-spec.yml +++ b/.github/test-spec.yml @@ -293,8 +293,6 @@ "CI-test-low-level": - "dts/**/*" - - "boards/arm/nrf54*/**/*" - - "boards/riscv/nrf54*/**/*" - "include/zephyr/**/*" - "tests/arch/**/*" - "arch/**/*" From 46c21dcc6c08824aa41f260520da273efd438de5 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:16 +0200 Subject: [PATCH 2207/2402] Revert "[nrf fromtree] samples: sensor: qdec: Allow coverage calculation" This reverts commit 7c48c142bd059d2bc40b3339d58af7cea054141a. Signed-off-by: Gerard Marull-Paretas --- samples/sensor/qdec/src/main.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/samples/sensor/qdec/src/main.c b/samples/sensor/qdec/src/main.c index 3410d04e5ba..3e7e87ab021 100644 --- a/samples/sensor/qdec/src/main.c +++ b/samples/sensor/qdec/src/main.c @@ -85,11 +85,7 @@ int main(void) qenc_emulate_init(); -#ifndef CONFIG_COVERAGE while (true) { -#else - for (int i = 0; i < 3; i++) { -#endif rc = sensor_sample_fetch(dev); if (rc != 0) { printk("Failed to fetch sample (%d)\n", rc); From ad41a5afcfc80d757ed2eb8e592f72aabc77f1f8 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:17 +0200 Subject: [PATCH 2208/2402] Revert "[nrf fromlist] boards: nordic: nrf54h20dk: enable HWFC" This reverts commit dd8fd47265796b558c2d2d495d6880848c50815b. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts | 1 - boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts | 1 - boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.dts | 1 - 3 files changed, 3 deletions(-) diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts index 7e5127f8b16..894685693ac 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts @@ -179,5 +179,4 @@ pinctrl-0 = <&uart136_default>; pinctrl-1 = <&uart136_sleep>; pinctrl-names = "default", "sleep"; - hw-flow-control; }; diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts index 30fdf7286d5..4ab3876abab 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts @@ -75,7 +75,6 @@ pinctrl-0 = <&uart135_default>; pinctrl-1 = <&uart135_sleep>; pinctrl-names = "default", "sleep"; - hw-flow-control; }; &uart136 { diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.dts b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.dts index 679afcdc8f9..edce1a8b275 100644 --- a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.dts +++ b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.dts @@ -46,7 +46,6 @@ pinctrl-0 = <&uart135_default>; pinctrl-1 = <&uart135_sleep>; pinctrl-names = "default", "sleep"; - hw-flow-control; }; &uart136 { From 16cf5b98560bd1fc98afb9bef173474c95067156 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:17 +0200 Subject: [PATCH 2209/2402] Revert "[nrf noup] entropy: Add fake entropy nRF PRNG driver" This reverts commit c976657eb74bfb052d93479be37594bddeff3d86. Signed-off-by: Gerard Marull-Paretas --- .../nrf54h20dk_nrf54h20_cpuapp.dts | 6 -- .../nrf54h20dk_nrf54h20_cpurad.dts | 6 -- drivers/entropy/CMakeLists.txt | 7 -- drivers/entropy/Kconfig | 1 - drivers/entropy/Kconfig.nrf_prng | 19 ---- drivers/entropy/fake_entropy_nrf_prng.c | 101 ------------------ dts/bindings/rng/nordic,nrf-prng.yaml | 8 -- 7 files changed, 148 deletions(-) delete mode 100644 drivers/entropy/Kconfig.nrf_prng delete mode 100644 drivers/entropy/fake_entropy_nrf_prng.c delete mode 100644 dts/bindings/rng/nordic,nrf-prng.yaml diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts index 894685693ac..8c6512861e8 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts @@ -22,7 +22,6 @@ zephyr,code-partition = &cpuapp_slot0_partition; zephyr,flash = &mram1x; zephyr,sram = &cpuapp_data; - zephyr,entropy = &prng; }; aliases { @@ -87,11 +86,6 @@ label = "Green LED 3"; }; }; - - prng: prng { - compatible = "nordic,entropy-prng"; - status = "okay"; - }; }; &cpuapp_ram0x_region { diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts index 4ab3876abab..3efa07f6349 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts @@ -23,12 +23,6 @@ zephyr,code-partition = &cpurad_slot0_partition; zephyr,flash = &mram1x; zephyr,sram = &cpurad_ram0; - zephyr,entropy = &prng; - }; - - prng: prng { - compatible = "nordic,entropy-prng"; - status = "okay"; }; }; diff --git a/drivers/entropy/CMakeLists.txt b/drivers/entropy/CMakeLists.txt index c3ffe1413e6..11e361517c2 100644 --- a/drivers/entropy/CMakeLists.txt +++ b/drivers/entropy/CMakeLists.txt @@ -34,13 +34,6 @@ zephyr_library_sources_ifdef(CONFIG_ENTROPY_BT_HCI entropy_bt_hci.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_SE entropy_gecko_se.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_PSA_CRYPTO_RNG entropy_psa_crypto.c) -if (CONFIG_FAKE_ENTROPY_NRF_PRNG) - zephyr_library_sources(fake_entropy_nrf_prng.c) - - message(WARNING "\nA nRF PRNG is used, which does not produce real random bits." - "This is not secure and should therefore never be used in a product.") -endif() - if (CONFIG_BUILD_WITH_TFM) target_include_directories(${ZEPHYR_CURRENT_LIBRARY} PRIVATE $/api_ns/interface/include diff --git a/drivers/entropy/Kconfig b/drivers/entropy/Kconfig index 604a28e7ac7..e932f62c6bf 100644 --- a/drivers/entropy/Kconfig +++ b/drivers/entropy/Kconfig @@ -35,7 +35,6 @@ source "drivers/entropy/Kconfig.gecko" source "drivers/entropy/Kconfig.neorv32" source "drivers/entropy/Kconfig.bt_hci" source "drivers/entropy/Kconfig.psa_crypto" -source "drivers/entropy/Kconfig.nrf_prng" config ENTROPY_HAS_DRIVER bool diff --git a/drivers/entropy/Kconfig.nrf_prng b/drivers/entropy/Kconfig.nrf_prng deleted file mode 100644 index e1b1a9ab4fe..00000000000 --- a/drivers/entropy/Kconfig.nrf_prng +++ /dev/null @@ -1,19 +0,0 @@ -# nRF fake entropy prng generator driver configuration - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if ENTROPY_GENERATOR - -config FAKE_ENTROPY_NRF_PRNG - bool "A fake nRF entropy driver" - default y - depends on DT_HAS_NORDIC_ENTROPY_PRNG_ENABLED - depends on SOC_SERIES_NRF54HX - select ENTROPY_HAS_DRIVER - help - This is a super simple PRNG driver that can be used on nRF platforms that - do not have an entropy source. - This is NOT SAFE to use for cryptographic operations! - -endif diff --git a/drivers/entropy/fake_entropy_nrf_prng.c b/drivers/entropy/fake_entropy_nrf_prng.c deleted file mode 100644 index 8624c844405..00000000000 --- a/drivers/entropy/fake_entropy_nrf_prng.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include - -#define DT_DRV_COMPAT nordic_entropy_prng - -/* This file implements a pseudo-RNG - * https://vigna.di.unimi.it/xorshift/xoshiro128plus.c - */ - -static uint32_t s[4]; - -static inline uint32_t rotl(const uint32_t x, int k) -{ - return (x << k) | (x >> (32 - k)); -} - -static uint32_t rng_next(void) -{ - const uint32_t result = rotl(s[0] + s[3], 7) + s[0]; - - const uint32_t t = s[1] << 9; - - s[2] ^= s[0]; - s[3] ^= s[1]; - s[1] ^= s[2]; - s[0] ^= s[3]; - - s[2] ^= t; - - s[3] = rotl(s[3], 11); - - return result; -} - -static int entropy_prng_get_entropy(const struct device *dev, uint8_t *buffer, uint16_t length) -{ - ARG_UNUSED(dev); - - while (length) { - /* - * Note that only 1 thread (Zephyr thread or HW models), runs at - * a time, therefore there is no need to use random_r() - */ - uint32_t value = rng_next(); - - size_t to_copy = MIN(length, sizeof(long)); - - memcpy(buffer, &value, to_copy); - buffer += to_copy; - length -= to_copy; - } - - return 0; -} - -static int entropy_prng_get_entropy_isr(const struct device *dev, uint8_t *buf, uint16_t len, - uint32_t flags) -{ - ARG_UNUSED(flags); - - int err; - - /* - * entropy_prng_get_entropy() is also safe for ISRs - * and always produces data. - */ - err = entropy_prng_get_entropy(dev, buf, len); - if (err < 0) { - return err; - } else { - return len; - } -} - -static int entropy_prng_init(const struct device *dev) -{ - ARG_UNUSED(dev); - - /* Picked some arbitrary initial seed. */ - s[0] = 0xAF568BC0; - s[1] = 0xAC34307E; - s[2] = 0x9B7F6DD1; - s[3] = 0xD84319FC; - return 0; -} - -static const struct entropy_driver_api entropy_prng_api_funcs = { - .get_entropy = entropy_prng_get_entropy, .get_entropy_isr = entropy_prng_get_entropy_isr}; - -DEVICE_DT_INST_DEFINE(0, entropy_prng_init, NULL, NULL, NULL, PRE_KERNEL_1, - CONFIG_ENTROPY_INIT_PRIORITY, &entropy_prng_api_funcs); diff --git a/dts/bindings/rng/nordic,nrf-prng.yaml b/dts/bindings/rng/nordic,nrf-prng.yaml deleted file mode 100644 index 8936393a0b6..00000000000 --- a/dts/bindings/rng/nordic,nrf-prng.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause - -description: This is a super simple PRNG - -compatible: "nordic,entropy-prng" - -include: base.yaml From 6fd64f77046bf621d3de35ca5aa7b18b4d104d92 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:17 +0200 Subject: [PATCH 2210/2402] Revert "[nrf fromtree] net: wifi: Remove constraints for dwell time" This reverts commit a76c880b8922777333549d86b991597cd7a46031. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/net/wifi_mgmt.h | 6 ++++++ subsys/net/l2/wifi/wifi_shell.c | 11 ++++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h index f8fb7893234..a5af218bf4a 100644 --- a/include/zephyr/net/wifi_mgmt.h +++ b/include/zephyr/net/wifi_mgmt.h @@ -48,6 +48,12 @@ extern "C" { #endif /* CONFIG_WIFI_MGMT_SCAN_CHAN_MAX_MANUAL */ #define WIFI_MGMT_BAND_STR_SIZE_MAX 8 +#define WIFI_MGMT_SCAN_MIN_DWELL_TIME_ACTIVE 5 +#define WIFI_MGMT_SCAN_MAX_DWELL_TIME_ACTIVE 1000 +#define WIFI_MGMT_SCAN_MIN_DWELL_TIME_PASSIVE 10 +#define WIFI_MGMT_SCAN_MAX_DWELL_TIME_PASSIVE 1000 +#define WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_ACTIVE 50 +#define WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_PASSIVE 130 #define WIFI_MGMT_SCAN_MAX_BSS_CNT 65535 /** Wi-Fi management commands */ diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index c512612e7ed..d62788ab6c8 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -700,7 +700,8 @@ static int wifi_scan_args_to_params(const struct shell *sh, case 'a': val = atoi(optarg); - if (val < 0) { + if ((val < WIFI_MGMT_SCAN_MIN_DWELL_TIME_ACTIVE) || + (val > WIFI_MGMT_SCAN_MAX_DWELL_TIME_ACTIVE)) { PR_ERROR("Invalid dwell_time_active val\n"); return -ENOEXEC; } @@ -711,7 +712,8 @@ static int wifi_scan_args_to_params(const struct shell *sh, case 'p': val = atoi(optarg); - if (val < 0) { + if ((val < WIFI_MGMT_SCAN_MIN_DWELL_TIME_PASSIVE) || + (val > WIFI_MGMT_SCAN_MAX_DWELL_TIME_PASSIVE)) { PR_ERROR("Invalid dwell_time_passive val\n"); return -ENOEXEC; } @@ -769,7 +771,10 @@ static int wifi_scan_args_to_params(const struct shell *sh, static int cmd_wifi_scan(const struct shell *sh, size_t argc, char *argv[]) { struct net_if *iface = net_if_get_first_wifi(); - struct wifi_scan_params params = { 0 }; + struct wifi_scan_params params = { .dwell_time_active = + WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_ACTIVE, + .dwell_time_passive = + WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_PASSIVE, }; bool do_scan = true; int opt_num; From 7f7bf979e7d84d84e0da7b74d4b2595d20997da0 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:17 +0200 Subject: [PATCH 2211/2402] Revert "[nrf fromtree] net: wifi: Add reasons for 4 way handshake failure" This reverts commit 98aa4243c15e646e6a82c0a34ddd7454d6d9a9a4. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/net/wifi_mgmt.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h index a5af218bf4a..414263d31e7 100644 --- a/include/zephyr/net/wifi_mgmt.h +++ b/include/zephyr/net/wifi_mgmt.h @@ -370,14 +370,7 @@ enum wifi_conn_status { WIFI_STATUS_CONN_SUCCESS = 0, /** Connection failed - generic failure */ WIFI_STATUS_CONN_FAIL, - /** Connection failed - wrong password - * Few possible reasons for 4-way handshake failure that we can guess are as follows: - * 1) Incorrect key - * 2) EAPoL frames lost causing timeout - * - * #1 is the likely cause, so, we convey to the user that it is due to - * Wrong passphrase/password. - */ + /** Connection failed - wrong password */ WIFI_STATUS_CONN_WRONG_PASSWORD, /** Connection timed out */ WIFI_STATUS_CONN_TIMEOUT, From aa7a3dd5b98c8d712f1d497ccc787ecb3b54ea2b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:17 +0200 Subject: [PATCH 2212/2402] Revert "[nrf fromtree] net: wifi: Replace numeric values with defines" This reverts commit d9a8f7e0430296e33c738d2be76406528aeed897. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/net/wifi_mgmt.h | 7 ------- subsys/net/l2/wifi/wifi_shell.c | 13 ++++--------- 2 files changed, 4 insertions(+), 16 deletions(-) diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h index 414263d31e7..25cdf0919f7 100644 --- a/include/zephyr/net/wifi_mgmt.h +++ b/include/zephyr/net/wifi_mgmt.h @@ -48,13 +48,6 @@ extern "C" { #endif /* CONFIG_WIFI_MGMT_SCAN_CHAN_MAX_MANUAL */ #define WIFI_MGMT_BAND_STR_SIZE_MAX 8 -#define WIFI_MGMT_SCAN_MIN_DWELL_TIME_ACTIVE 5 -#define WIFI_MGMT_SCAN_MAX_DWELL_TIME_ACTIVE 1000 -#define WIFI_MGMT_SCAN_MIN_DWELL_TIME_PASSIVE 10 -#define WIFI_MGMT_SCAN_MAX_DWELL_TIME_PASSIVE 1000 -#define WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_ACTIVE 50 -#define WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_PASSIVE 130 -#define WIFI_MGMT_SCAN_MAX_BSS_CNT 65535 /** Wi-Fi management commands */ enum net_request_wifi_cmd { diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index d62788ab6c8..f1a52aaf23a 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -700,8 +700,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, case 'a': val = atoi(optarg); - if ((val < WIFI_MGMT_SCAN_MIN_DWELL_TIME_ACTIVE) || - (val > WIFI_MGMT_SCAN_MAX_DWELL_TIME_ACTIVE)) { + if ((val < 5) || (val > 1000)) { PR_ERROR("Invalid dwell_time_active val\n"); return -ENOEXEC; } @@ -712,8 +711,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, case 'p': val = atoi(optarg); - if ((val < WIFI_MGMT_SCAN_MIN_DWELL_TIME_PASSIVE) || - (val > WIFI_MGMT_SCAN_MAX_DWELL_TIME_PASSIVE)) { + if ((val < 10) || (val > 1000)) { PR_ERROR("Invalid dwell_time_passive val\n"); return -ENOEXEC; } @@ -734,7 +732,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, case 'm': val = atoi(optarg); - if ((val < 0) || (val > WIFI_MGMT_SCAN_MAX_BSS_CNT)) { + if ((val < 0) || (val > 65535)) { PR_ERROR("Invalid max_bss val\n"); return -ENOEXEC; } @@ -771,10 +769,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, static int cmd_wifi_scan(const struct shell *sh, size_t argc, char *argv[]) { struct net_if *iface = net_if_get_first_wifi(); - struct wifi_scan_params params = { .dwell_time_active = - WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_ACTIVE, - .dwell_time_passive = - WIFI_MGMT_SCAN_DEFAULT_DWELL_TIME_PASSIVE, }; + struct wifi_scan_params params = { .dwell_time_active = 50, .dwell_time_passive = 130, }; bool do_scan = true; int opt_num; From 53385223f24489f0d7fa11ed367cb4f8dd1ecfcf Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:18 +0200 Subject: [PATCH 2213/2402] Revert "[nrf fromtree] net: wifi: Fix disconnect reason codes" This reverts commit b91d6d1ce593bf96cf23c5c7e76cff6479998709. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/net/wifi_mgmt.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h index 25cdf0919f7..894c25e7e8c 100644 --- a/include/zephyr/net/wifi_mgmt.h +++ b/include/zephyr/net/wifi_mgmt.h @@ -369,10 +369,6 @@ enum wifi_conn_status { WIFI_STATUS_CONN_TIMEOUT, /** Connection failed - AP not found */ WIFI_STATUS_CONN_AP_NOT_FOUND, - /** Last connection status */ - WIFI_STATUS_CONN_LAST_STATUS, - /** Connection disconnected status */ - WIFI_STATUS_DISCONN_FIRST_STATUS = WIFI_STATUS_CONN_LAST_STATUS, }; /** Wi-Fi disconnect reason codes. To be overlaid on top of \ref wifi_status @@ -380,7 +376,7 @@ enum wifi_conn_status { */ enum wifi_disconn_reason { /** Unspecified reason */ - WIFI_REASON_DISCONN_UNSPECIFIED = WIFI_STATUS_DISCONN_FIRST_STATUS, + WIFI_REASON_DISCONN_UNSPECIFIED = 0, /** Disconnected due to user request */ WIFI_REASON_DISCONN_USER_REQUEST, /** Disconnected due to AP leaving */ From c287b82d66029f05b7d2be6651e5c60e98143eb0 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:18 +0200 Subject: [PATCH 2214/2402] Revert "[nrf fromtree] net: wifi: Set default values of dwell time" This reverts commit 6886bf7441b53a8734482009130f53c8e70166e2. Signed-off-by: Gerard Marull-Paretas --- subsys/net/l2/wifi/wifi_shell.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index f1a52aaf23a..fc4c8cf0def 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -769,7 +769,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, static int cmd_wifi_scan(const struct shell *sh, size_t argc, char *argv[]) { struct net_if *iface = net_if_get_first_wifi(); - struct wifi_scan_params params = { .dwell_time_active = 50, .dwell_time_passive = 130, }; + struct wifi_scan_params params = { 0 }; bool do_scan = true; int opt_num; From bec8fac39bf6e6886113258a61445896f7813587 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:18 +0200 Subject: [PATCH 2215/2402] Revert "[nrf fromtree] net: wifi: Add channel validity check for AP mode" This reverts commit df2e0db29ed705f528e2cfb385738b8bf389544b. Signed-off-by: Gerard Marull-Paretas --- subsys/net/l2/wifi/wifi_shell.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index fc4c8cf0def..c1ecf4533b1 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -541,11 +541,6 @@ static int __wifi_args_to_params(size_t argc, char *argv[], idx++; } - if ((idx == 1) && (iface_mode == WIFI_MODE_AP)) { - PR_ERROR("Invalid channel: %s\n", argv[idx]); - return -EINVAL; - } - /* PSK (optional) */ if (idx < argc) { params->psk = argv[idx]; From a9ea6cb2e52c2aa362638e6e74beeb0348183f00 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:18 +0200 Subject: [PATCH 2216/2402] Revert "[nrf fromtree] samples: subsys: settings: Add configuration for nRF54L15" This reverts commit d06a1a7d77b564b331b24db2f3cca58076ef28e9. Signed-off-by: Gerard Marull-Paretas --- samples/subsys/settings/boards/nrf54l15pdk_nrf54l15_cpuapp.conf | 2 -- samples/subsys/settings/sample.yaml | 1 - 2 files changed, 3 deletions(-) delete mode 100644 samples/subsys/settings/boards/nrf54l15pdk_nrf54l15_cpuapp.conf diff --git a/samples/subsys/settings/boards/nrf54l15pdk_nrf54l15_cpuapp.conf b/samples/subsys/settings/boards/nrf54l15pdk_nrf54l15_cpuapp.conf deleted file mode 100644 index 3746c13c741..00000000000 --- a/samples/subsys/settings/boards/nrf54l15pdk_nrf54l15_cpuapp.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_NVS=y -CONFIG_SETTINGS_NVS=y diff --git a/samples/subsys/settings/sample.yaml b/samples/subsys/settings/sample.yaml index 1bb763eedb4..2cd51d1405d 100644 --- a/samples/subsys/settings/sample.yaml +++ b/samples/subsys/settings/sample.yaml @@ -12,7 +12,6 @@ tests: - native_sim - native_sim_64 - mr_canhubk3 - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - native_sim harness: console From 36a6df9fcff294b54f8bdab97f55f906706a4112 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:18 +0200 Subject: [PATCH 2217/2402] Revert "[nrf fromtree] scripts: snippets: Fix path output on windows" This reverts commit 92095510b5f18979b12718ebb83f3741c6e411ee. Signed-off-by: Gerard Marull-Paretas --- scripts/snippets.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/snippets.py b/scripts/snippets.py index 4050f57a973..78ab896e85b 100644 --- a/scripts/snippets.py +++ b/scripts/snippets.py @@ -56,7 +56,7 @@ def append_value(variable, value): path = pathobj.parent / value if not path.is_file(): _err(f'snippet file {pathobj}: {variable}: file not found: {path}') - return f'"{path.as_posix()}"' + return f'"{path}"' if variable in ('DTS_EXTRA_CPPFLAGS'): return f'"{value}"' _err(f'unknown append variable: {variable}') From 61aeecf41347c12130786138ccbb5dbee0d9a696 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:19 +0200 Subject: [PATCH 2218/2402] Revert "[nrf fromtree] tests: drivers: uart: uart_mix_fifo_poll: Add nRF54L15 to platform allow" This reverts commit 2a3a5c9757f1f333a638fce9808d2d352623b76c. Signed-off-by: Gerard Marull-Paretas --- tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml index 60a3501f9fd..ccfdd1aa717 100644 --- a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml +++ b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml @@ -8,7 +8,6 @@ common: - nrf52840dk_nrf52840 - nrf9160dk_nrf9160 - nrf5340dk_nrf5340_cpuapp - - nrf54l15pdk_nrf54l15_cpuapp - nrf52_bsim integration_platforms: - nrf52840dk_nrf52840 From 5e3a7b8b2fe80182bbcc9652d55c9e8e3ba3dd41 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:19 +0200 Subject: [PATCH 2219/2402] Revert "[nrf fromtree] net: lib: http: Correct http_client edge-case behavior" This reverts commit 0f0b9f3c45c6884671a8205f9526be23f9463d15. Signed-off-by: Gerard Marull-Paretas --- subsys/net/lib/http/http_client.c | 105 +++++++++++++----------------- 1 file changed, 47 insertions(+), 58 deletions(-) diff --git a/subsys/net/lib/http/http_client.c b/subsys/net/lib/http/http_client.c index 0f73ce6e8f8..3992e5fafdd 100644 --- a/subsys/net/lib/http/http_client.c +++ b/subsys/net/lib/http/http_client.c @@ -392,11 +392,7 @@ static void http_client_init_parser(struct http_parser *parser, settings->on_url = on_url; } -/* Report a NULL HTTP response to the caller. - * A NULL response is when the HTTP server intentionally closes the TLS socket (using FINACK) - * without sending any HTTP payload. - */ -static void http_report_null(struct http_request *req) +static void http_data_final_null_resp(struct http_request *req) { if (req->internal.response.cb) { NET_DBG("Calling callback for Final Data" @@ -417,28 +413,6 @@ static void http_report_null(struct http_request *req) } } -/* Report a completed HTTP transaction (with no error) to the caller */ -static void http_report_complete(struct http_request *req) -{ - if (req->internal.response.cb) { - NET_DBG("Calling callback for %zd len data", req->internal.response.data_len); - req->internal.response.cb(&req->internal.response, HTTP_DATA_FINAL, - req->internal.user_data); - } -} - -/* Report that some data has been received, but the HTTP transaction is still ongoing. */ -static void http_report_progress(struct http_request *req) -{ - if (req->internal.response.cb) { - NET_DBG("Calling callback for partitioned %zd len data", - req->internal.response.data_len); - - req->internal.response.cb(&req->internal.response, HTTP_DATA_MORE, - req->internal.user_data); - } -} - static int http_wait_data(int sock, struct http_request *req, int32_t timeout) { int total_received = 0; @@ -464,26 +438,24 @@ static int http_wait_data(int sock, struct http_request *req, int32_t timeout) ret = zsock_poll(fds, nfds, remaining_time); if (ret == 0) { LOG_DBG("Timeout"); - ret = -ETIMEDOUT; - goto error; + goto finalize_data; } else if (ret < 0) { - ret = -errno; goto error; } if (fds[0].revents & (ZSOCK_POLLERR | ZSOCK_POLLNVAL)) { - ret = -errno; goto error; } else if (fds[0].revents & ZSOCK_POLLHUP) { /* Connection closed */ - goto closed; + LOG_DBG("Connection closed"); + goto finalize_data; } else if (fds[0].revents & ZSOCK_POLLIN) { received = zsock_recv(sock, req->internal.response.recv_buf + offset, req->internal.response.recv_buf_len - offset, 0); if (received == 0) { /* Connection closed */ - goto closed; + LOG_DBG("Connection closed"); + goto finalize_data; } else if (received < 0) { - ret = -errno; goto error; } else { req->internal.response.data_len += received; @@ -500,41 +472,54 @@ static int http_wait_data(int sock, struct http_request *req, int32_t timeout) offset = 0; } + if (req->internal.response.cb) { + bool notify = false; + enum http_final_call event; + + if (req->internal.response.message_complete) { + NET_DBG("Calling callback for %zd len data", + req->internal.response.data_len); + + notify = true; + event = HTTP_DATA_FINAL; + } else if (offset == 0) { + NET_DBG("Calling callback for partitioned %zd len data", + req->internal.response.data_len); + + notify = true; + event = HTTP_DATA_MORE; + } + + if (notify) { + req->internal.response.cb(&req->internal.response, event, + req->internal.user_data); + + /* Re-use the result buffer and start to fill it again */ + req->internal.response.data_len = 0; + req->internal.response.body_frag_start = NULL; + req->internal.response.body_frag_len = 0; + } + } + if (req->internal.response.message_complete) { - http_report_complete(req); + ret = total_received; break; - } else if (offset == 0) { - http_report_progress(req); - - /* Re-use the result buffer and start to fill it again */ - req->internal.response.data_len = 0; - req->internal.response.body_frag_start = NULL; - req->internal.response.body_frag_len = 0; } } } while (true); - return total_received; + return ret; -closed: - LOG_DBG("Connection closed"); +finalize_data: + ret = total_received; - /* If connection was closed with no data sent, this is a NULL response, and is a special - * case valid response. - */ - if (total_received == 0) { - http_report_null(req); - return total_received; - } - - /* Otherwise, connection was closed mid-way through response, and this should be - * considered an error. - */ - ret = -ECONNRESET; + http_data_final_null_resp(req); + return ret; error: - LOG_DBG("Connection error (%d)", ret); + LOG_DBG("Connection error (%d)", errno); + ret = -errno; return ret; } @@ -734,6 +719,10 @@ int http_client_req(int sock, struct http_request *req, NET_DBG("Wait data failure (%d)", total_recv); ret = total_recv; goto out; + } else if (total_recv == 0) { + NET_DBG("Timeout while waiting data"); + ret = -ETIMEDOUT; + goto out; } NET_DBG("Received %d bytes", total_recv); From f47848363152e5a8943df2a20351566d3d9073b8 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:19 +0200 Subject: [PATCH 2220/2402] Revert "[nrf fromtree] net: wifi: Add an build assert for checking states order" This reverts commit 35a387057f373217b6ad64ddc2c31ca939f1e190. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/net/wifi.h | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/include/zephyr/net/wifi.h b/include/zephyr/net/wifi.h index a0840a2319a..0f19d7c4c18 100644 --- a/include/zephyr/net/wifi.h +++ b/include/zephyr/net/wifi.h @@ -138,18 +138,6 @@ enum wifi_iface_state { WIFI_STATE_UNKNOWN }; -/* We rely on the strict order of the enum values, so, let's check it */ -BUILD_ASSERT(WIFI_STATE_DISCONNECTED < WIFI_STATE_INTERFACE_DISABLED && - WIFI_STATE_INTERFACE_DISABLED < WIFI_STATE_INACTIVE && - WIFI_STATE_INACTIVE < WIFI_STATE_SCANNING && - WIFI_STATE_SCANNING < WIFI_STATE_AUTHENTICATING && - WIFI_STATE_AUTHENTICATING < WIFI_STATE_ASSOCIATING && - WIFI_STATE_ASSOCIATING < WIFI_STATE_ASSOCIATED && - WIFI_STATE_ASSOCIATED < WIFI_STATE_4WAY_HANDSHAKE && - WIFI_STATE_4WAY_HANDSHAKE < WIFI_STATE_GROUP_HANDSHAKE && - WIFI_STATE_GROUP_HANDSHAKE < WIFI_STATE_COMPLETED); - - /** Helper function to get user-friendly interface state name. */ const char *wifi_state_txt(enum wifi_iface_state state); From dfe309b1bf92ca24e507cd50b6dc430888ea2f69 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:19 +0200 Subject: [PATCH 2221/2402] Revert "[nrf fromtree] net: wifi: Fix the Wi-Fi state check" This reverts commit e658f5167cb48c29fe434f43c8171f49fecf6e48. Signed-off-by: Gerard Marull-Paretas --- subsys/net/l2/wifi/wifi_mgmt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/l2/wifi/wifi_mgmt.c b/subsys/net/l2/wifi/wifi_mgmt.c index 72552d371d7..a9c931507ed 100644 --- a/subsys/net/l2/wifi/wifi_mgmt.c +++ b/subsys/net/l2/wifi/wifi_mgmt.c @@ -504,7 +504,7 @@ static int wifi_set_power_save(uint32_t mgmt_request, struct net_if *iface, return -EIO; } - if (info.state >= WIFI_STATE_ASSOCIATED) { + if (info.state == WIFI_STATE_COMPLETED) { ps_params->fail_reason = WIFI_PS_PARAM_FAIL_DEVICE_CONNECTED; return -ENOTSUP; From 81a6b1bb12c35c3432dc8eec6e779090336e284b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:19 +0200 Subject: [PATCH 2222/2402] Revert "[nrf fromlist] boards: nrf54l15pdk_nrf54l15_cpuapp: add support for PDK 0.3.0" This reverts commit 93f8406a968cd750bbfa8ada1682a4556972ed66. Signed-off-by: Gerard Marull-Paretas --- .../nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay | 38 ------------------- .../arm/nrf54l15pdk_nrf54l15/revision.cmake | 2 +- 2 files changed, 1 insertion(+), 39 deletions(-) delete mode 100644 boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay deleted file mode 100644 index d8262dde994..00000000000 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -&led0 { - gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; -}; - -&led1 { - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; -}; - -&led2 { - gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; -}; - -&led3 { - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; -}; - -&button0 { - gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; -}; - -&button1 { - gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; -}; - -&button2 { - gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; -}; - -&button3 { - gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; -}; diff --git a/boards/arm/nrf54l15pdk_nrf54l15/revision.cmake b/boards/arm/nrf54l15pdk_nrf54l15/revision.cmake index 6057362de55..4fe5b260db3 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/revision.cmake +++ b/boards/arm/nrf54l15pdk_nrf54l15/revision.cmake @@ -5,5 +5,5 @@ # board_check_revision(FORMAT MAJOR.MINOR.PATCH - VALID_REVISIONS 0.2.0 0.3.0 + VALID_REVISIONS 0.2.0 DEFAULT_REVISION 0.2.0) From 8d79477ace858b4fc304188fa0460e39f73d82b1 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:20 +0200 Subject: [PATCH 2223/2402] Revert "[nrf fromtree] board: nrf54h20dk: Add missing default BT related configs" This reverts commit a503870a7a7f6f0b1f9a8213998c0a4ed066b194. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf54h20dk_nrf54h20/Kconfig.defconfig | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/boards/arm/nrf54h20dk_nrf54h20/Kconfig.defconfig b/boards/arm/nrf54h20dk_nrf54h20/Kconfig.defconfig index c0e83e0f6a8..1a029338775 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/Kconfig.defconfig +++ b/boards/arm/nrf54h20dk_nrf54h20/Kconfig.defconfig @@ -4,18 +4,3 @@ config BOARD default "nrf54h20dk_nrf54h20_cpuapp" if BOARD_NRF54H20DK_NRF54H20_CPUAPP default "nrf54h20dk_nrf54h20_cpurad" if BOARD_NRF54H20DK_NRF54H20_CPURAD - -if BOARD_NRF54H20DK_NRF54H20_CPUAPP - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP - -if BOARD_NRF54H20DK_NRF54H20_CPURAD - -config BT_CTLR - default y if BT - -endif # BOARD_NRF54H20DK_NRF54H20_CPURAD From b4e552754c2343ad1f477b0ea0d97540991d5bbb Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:20 +0200 Subject: [PATCH 2224/2402] Revert "[nrf fromtree] boards: nrf54h20: Fix storage partitions for setting subsytem" This reverts commit a6e3fd56ead78a1373f6af36170f48f5736d4e67. Signed-off-by: Gerard Marull-Paretas --- .../nrf54h20dk_nrf54h20-memory_map.dtsi | 14 -------------- .../nrf54h20dk_nrf54h20_cpuapp.dts | 4 ---- 2 files changed, 18 deletions(-) diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-memory_map.dtsi index 68c0d5cd990..6b6402eb90f 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-memory_map.dtsi +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-memory_map.dtsi @@ -181,18 +181,4 @@ reg = <0x126000 DT_SIZE_K(64)>; }; }; - - cpuapp_rw_partitions: cpuapp-rw-partitions { - compatible = "nordic,owned-partitions", "fixed-partitions"; - status = "disabled"; - perm-read; - perm-write; - perm-secure; - #address-cells = <1>; - #size-cells = <1>; - - storage_partition: partition@136000 { - reg = <0x136000 DT_SIZE_K(24)>; - }; - }; }; diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts index 8c6512861e8..a8ea9fe730f 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts @@ -130,10 +130,6 @@ status = "okay"; }; -&cpuapp_rw_partitions { - status = "okay"; -}; - &cpuppr_vpr { execution-memory = <&cpuppr_code_data>; source-memory = <&cpuppr_code_partition>; From 5ba69c4a7c4dd056ab6edfc763a7a902488035a8 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:20 +0200 Subject: [PATCH 2225/2402] Revert "[nrf fromtree] samples: bluetooth: hci_ipc: Add nrf54h20 DK board overlay" This reverts commit 1b8b90c4b252e40c6ccb56ce25f6b17e616627af. Signed-off-by: Gerard Marull-Paretas --- .../boards/nrf54h20dk_nrf54h20_cpurad.overlay | 27 ------------------- 1 file changed, 27 deletions(-) delete mode 100644 samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay diff --git a/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay deleted file mode 100644 index 02db7c39272..00000000000 --- a/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,bt-hci-ipc = &ipc0; - }; -}; - -ipc0: &cpuapp_cpurad_ipc { - status = "okay"; -}; - -&cpuapp_cpurad_ram0x_region { - status = "okay"; -}; - -&cpurad_bellboard { - status = "okay"; -}; - -&cpuapp_bellboard { - status = "okay"; -}; From bcc5f2fc2cb13f44b21de942ad0dba9d34b39e29 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:20 +0200 Subject: [PATCH 2226/2402] Revert "[nrf fromtree] net: dhcpv6: Add configurable DUID buffer length" This reverts commit c24df01678e8fc55ce50b322d484eb3f2b5b56a6. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/net/dhcpv6.h | 7 ++----- subsys/net/lib/dhcpv6/Kconfig | 7 ------- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/include/zephyr/net/dhcpv6.h b/include/zephyr/net/dhcpv6.h index 715b8cae858..95b59f530b5 100644 --- a/include/zephyr/net/dhcpv6.h +++ b/include/zephyr/net/dhcpv6.h @@ -38,14 +38,11 @@ enum net_dhcpv6_state { } __packed; #define DHCPV6_TID_SIZE 3 - -#ifndef CONFIG_NET_DHCPV6_DUID_MAX_LEN -#define CONFIG_NET_DHCPV6_DUID_MAX_LEN 22 -#endif +#define DHCPV6_DUID_MAX_SIZE 20 struct net_dhcpv6_duid_raw { uint16_t type; - uint8_t buf[CONFIG_NET_DHCPV6_DUID_MAX_LEN]; + uint8_t buf[DHCPV6_DUID_MAX_SIZE]; } __packed; struct net_dhcpv6_duid_storage { diff --git a/subsys/net/lib/dhcpv6/Kconfig b/subsys/net/lib/dhcpv6/Kconfig index 24443c9b36c..a406f4022a8 100644 --- a/subsys/net/lib/dhcpv6/Kconfig +++ b/subsys/net/lib/dhcpv6/Kconfig @@ -15,13 +15,6 @@ config NET_DHCPV6 select NET_MGMT_EVENT depends on NET_IPV6 && NET_UDP -config NET_DHCPV6_DUID_MAX_LEN - int "The maximum DUID length (not including a type code)" - range 1 128 - default 22 - help - This will set the available number of bytes for the DUID. - if NET_DHCPV6 module = NET_DHCPV6 module-dep = NET_LOG From 29b0d855a099e5715888a345f68eef209997734e Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:20 +0200 Subject: [PATCH 2227/2402] Revert "[nrf fromtree] net: ip: Fix for improper offset return by `net_pkt_find_offset()`" This reverts commit 78cf54bcaced3de263184c72f958ee0bf1bf9a8e. Signed-off-by: Gerard Marull-Paretas --- subsys/net/ip/net_pkt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/ip/net_pkt.c b/subsys/net/ip/net_pkt.c index d7556a5023d..38fc288d8f5 100644 --- a/subsys/net/ip/net_pkt.c +++ b/subsys/net/ip/net_pkt.c @@ -1817,7 +1817,7 @@ static int32_t net_pkt_find_offset(struct net_pkt *pkt, uint8_t *ptr) buf = pkt->buffer; while (buf) { - if (buf->data <= ptr && ptr < (buf->data + buf->len)) { + if (buf->data <= ptr && ptr <= (buf->data + buf->len)) { ret = offset + (ptr - buf->data); break; } From 863c3bf143275457be945cb01cd1612b5d722a6a Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:21 +0200 Subject: [PATCH 2228/2402] Revert "[nrf fromtree] manifest: Update hal_nordic with DMA address check fix" This reverts commit 7d7953d89e4cfe1c6f8cdf8635d89c3f40324073. Signed-off-by: Gerard Marull-Paretas --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 720e5d5a97b..9c375a568fe 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: 7803a3e6b606ddde8df9a10108d7251a108bd7c9 + revision: 13ac55b5b52c905642e9c54f069109d188aa5840 path: modules/hal/nordic groups: - hal From d80f9b1787f48b7a95fedabf64eda44bcdbaea00 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:21 +0200 Subject: [PATCH 2229/2402] Revert "[nrf fromtree] Samples: Bluetooth: Fix PAwR sample failed to set subevent data" This reverts commit e85f119dcf7f13acb3b239c99bdad69912e3b0af. Signed-off-by: Gerard Marull-Paretas --- samples/bluetooth/periodic_adv_rsp/src/main.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/samples/bluetooth/periodic_adv_rsp/src/main.c b/samples/bluetooth/periodic_adv_rsp/src/main.c index 6764b023a5a..0b0db776692 100644 --- a/samples/bluetooth/periodic_adv_rsp/src/main.c +++ b/samples/bluetooth/periodic_adv_rsp/src/main.c @@ -295,8 +295,7 @@ int main(void) } while (num_synced < MAX_SYNCS) { - /* Enable continuous scanning */ - err = bt_le_scan_start(BT_LE_SCAN_PASSIVE_CONTINUOUS, device_found); + err = bt_le_scan_start(BT_LE_SCAN_PASSIVE, device_found); if (err) { printk("Scanning failed to start (err %d)\n", err); return 0; From 5557b29d69c359ae40ea387a4521c813ff1d2ddf Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:21 +0200 Subject: [PATCH 2230/2402] Revert "[nrf fromtree] Bluetooth: Host: Add macros for contiuous scanner" This reverts commit 6ba6f31d69b697b7ac87e9e3ef6bf6190e2d613b. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/bluetooth/bluetooth.h | 25 ------------------- include/zephyr/bluetooth/gap.h | 1 - .../host/att/pipeline/dut/src/main.c | 8 +++++- tests/bsim/bluetooth/ll/cis/src/main.c | 11 +++++++- 4 files changed, 17 insertions(+), 28 deletions(-) diff --git a/include/zephyr/bluetooth/bluetooth.h b/include/zephyr/bluetooth/bluetooth.h index 99a26884371..0cfad9b1f6b 100644 --- a/include/zephyr/bluetooth/bluetooth.h +++ b/include/zephyr/bluetooth/bluetooth.h @@ -2125,18 +2125,6 @@ struct bt_le_scan_cb { BT_GAP_SCAN_FAST_INTERVAL, \ BT_GAP_SCAN_FAST_WINDOW) -/** - * @brief Helper macro to enable active scanning to discover new devices with window == interval. - * - * Continuous scanning should be used to maximize the chances of receiving advertising packets. - */ -#define BT_LE_SCAN_ACTIVE_CONTINUOUS BT_LE_SCAN_PARAM(BT_LE_SCAN_TYPE_ACTIVE, \ - BT_LE_SCAN_OPT_FILTER_DUPLICATE, \ - BT_GAP_SCAN_FAST_INTERVAL_MIN, \ - BT_GAP_SCAN_FAST_WINDOW) -BUILD_ASSERT(BT_GAP_SCAN_FAST_WINDOW == BT_GAP_SCAN_FAST_INTERVAL_MIN, - "Continuous scanning is requested by setting window and interval equal."); - /** * @brief Helper macro to enable passive scanning to discover new devices. * @@ -2148,19 +2136,6 @@ BUILD_ASSERT(BT_GAP_SCAN_FAST_WINDOW == BT_GAP_SCAN_FAST_INTERVAL_MIN, BT_GAP_SCAN_FAST_INTERVAL, \ BT_GAP_SCAN_FAST_WINDOW) -/** - * @brief Helper macro to enable passive scanning to discover new devices with window==interval. - * - * This macro should be used if information required for device identification - * (e.g., UUID) are known to be placed in Advertising Data. - */ -#define BT_LE_SCAN_PASSIVE_CONTINUOUS BT_LE_SCAN_PARAM(BT_LE_SCAN_TYPE_PASSIVE, \ - BT_LE_SCAN_OPT_FILTER_DUPLICATE, \ - BT_GAP_SCAN_FAST_INTERVAL_MIN, \ - BT_GAP_SCAN_FAST_WINDOW) -BUILD_ASSERT(BT_GAP_SCAN_FAST_WINDOW == BT_GAP_SCAN_FAST_INTERVAL_MIN, - "Continuous scanning is requested by setting window and interval equal."); - /** * @brief Helper macro to enable active scanning to discover new devices. * Include scanning on Coded PHY in addition to 1M PHY. diff --git a/include/zephyr/bluetooth/gap.h b/include/zephyr/bluetooth/gap.h index 16026d218e1..02fa8878c6b 100644 --- a/include/zephyr/bluetooth/gap.h +++ b/include/zephyr/bluetooth/gap.h @@ -708,7 +708,6 @@ extern "C" { * @name Defined GAP timers * @{ */ -#define BT_GAP_SCAN_FAST_INTERVAL_MIN 0x0030 /* 30 ms */ #define BT_GAP_SCAN_FAST_INTERVAL 0x0060 /* 60 ms */ #define BT_GAP_SCAN_FAST_WINDOW 0x0030 /* 30 ms */ #define BT_GAP_SCAN_SLOW_INTERVAL_1 0x0800 /* 1.28 s */ diff --git a/tests/bsim/bluetooth/host/att/pipeline/dut/src/main.c b/tests/bsim/bluetooth/host/att/pipeline/dut/src/main.c index 6481ce909b4..1a3c1480e1e 100644 --- a/tests/bsim/bluetooth/host/att/pipeline/dut/src/main.c +++ b/tests/bsim/bluetooth/host/att/pipeline/dut/src/main.c @@ -151,10 +151,16 @@ static struct bt_conn *connect(void) { int err; struct bt_conn *conn; + struct bt_le_scan_param scan_param = { + .type = BT_LE_SCAN_TYPE_ACTIVE, + .options = BT_LE_SCAN_OPT_NONE, + .interval = BT_GAP_SCAN_FAST_INTERVAL, + .window = BT_GAP_SCAN_FAST_WINDOW, + }; UNSET_FLAG(is_connected); - err = bt_le_scan_start(BT_LE_SCAN_ACTIVE_CONTINUOUS, device_found); + err = bt_le_scan_start(&scan_param, device_found); ASSERT(!err, "Scanning failed to start (err %d)\n", err); LOG_DBG("Central initiating connection..."); diff --git a/tests/bsim/bluetooth/ll/cis/src/main.c b/tests/bsim/bluetooth/ll/cis/src/main.c index e54b2e5224c..665c8e0daa4 100644 --- a/tests/bsim/bluetooth/ll/cis/src/main.c +++ b/tests/bsim/bluetooth/ll/cis/src/main.c @@ -45,6 +45,9 @@ static K_SEM_DEFINE(sem_iso_data, CONFIG_BT_ISO_TX_BUF_COUNT, CONFIG_BT_ISO_TX_BUF_COUNT); static bt_addr_le_t peer_addr; +#define SCAN_INTERVAL 0x0010 +#define SCAN_WINDOW 0x0010 + #define CREATE_CONN_INTERVAL 0x0010 #define CREATE_CONN_WINDOW 0x0010 @@ -66,6 +69,12 @@ static bt_addr_le_t peer_addr; #define ADV_INTERVAL_MIN 0x0020 #define ADV_INTERVAL_MAX 0x0020 +#define BT_LE_SCAN_CUSTOM \ + BT_LE_SCAN_PARAM(BT_LE_SCAN_TYPE_PASSIVE, \ + BT_LE_SCAN_OPT_NONE, \ + SCAN_INTERVAL, \ + SCAN_WINDOW) + #define BT_CONN_LE_CREATE_CONN_CUSTOM \ BT_CONN_LE_CREATE_PARAM(BT_CONN_LE_OPT_NONE, \ CREATE_CONN_INTERVAL, \ @@ -442,7 +451,7 @@ static void test_cis_central(void) int chan; printk("Start scanning (%d)...", i); - err = bt_le_scan_start(BT_LE_SCAN_PASSIVE_CONTINUOUS, NULL); + err = bt_le_scan_start(BT_LE_SCAN_CUSTOM, NULL); if (err) { FAIL("Could not start scan: %d\n", err); return; From fd46606cfdea6e25accdb98769d8c5a9c725cd96 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:21 +0200 Subject: [PATCH 2231/2402] Revert "[nrf fromlist] modules: hal_nordic: Add missing nrfx_config entries for nRF54L15" This reverts commit 272786b074227b4abcbe8f954d5bb8acf54f3dd3. Signed-off-by: Gerard Marull-Paretas --- .../nrfx_config_nrf54l15_enga_application.h | 27 ------------------- 1 file changed, 27 deletions(-) diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54l15_enga_application.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54l15_enga_application.h index 57e469686ec..a694a07955d 100644 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54l15_enga_application.h +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54l15_enga_application.h @@ -249,33 +249,6 @@ #define NRFX_GRTC_ENABLED 0 #endif -/** - * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED -#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOEN - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOEN -#define NRFX_GRTC_CONFIG_AUTOEN 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOSTART - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOSTART -#define NRFX_GRTC_CONFIG_AUTOSTART 1 -#endif - /** * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS * From 6afcc93398892e1ad79b7b649e7a50db2eb9fe3a Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:21 +0200 Subject: [PATCH 2232/2402] Revert "[nrf fromtree] dts: nrf54h20: Add missing global dppic and ipcst configs" This reverts commit 3fb1c87c354a91b6dbc62f5289b05b860534e011. Signed-off-by: Gerard Marull-Paretas --- dts/arm/nordic/nrf54h20_cpurad.dtsi | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/dts/arm/nordic/nrf54h20_cpurad.dtsi b/dts/arm/nordic/nrf54h20_cpurad.dtsi index 4bdaf76e348..f30c777dbe2 100644 --- a/dts/arm/nordic/nrf54h20_cpurad.dtsi +++ b/dts/arm/nordic/nrf54h20_cpurad.dtsi @@ -54,23 +54,3 @@ cpuppr_vevif: &cpuppr_vevif_remote {}; <109 NRF_DEFAULT_IRQ_PRIORITY>, <110 NRF_DEFAULT_IRQ_PRIORITY>; }; - -&dppic130 { - owned-channels = <0>; - sink-channels = <0>; - nonsecure-channels = <0>; - status = "okay"; -}; - -&dppic132 { - owned-channels = <0>; - source-channels = <0>; - nonsecure-channels = <0>; - status = "okay"; -}; - -&ipct130 { - owned-channels = <0>; - source-channel-links = <0 3 0>; - status = "okay"; -}; From 5da9e77535b71172a718134971018849764a16ab Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:22 +0200 Subject: [PATCH 2233/2402] Revert "[nrf fromlist] dts: nrf54h20: move GRTC channels allocation to the SOC dtsi" This reverts commit 479305b555fbe875faf0683efb73bc0bbe4e4656. Signed-off-by: Gerard Marull-Paretas --- .../arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts | 3 +++ dts/arm/nordic/nrf54h20_cpurad.dtsi | 6 +----- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts index 3efa07f6349..fd65d2d495a 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts @@ -60,6 +60,9 @@ &grtc { status = "okay"; + child-owned-channels = <8 9 10 11 12>; + nonsecure-channels = <8 9 10 11 12>; + owned-channels = <7 8 9 10 11 12 13 14>; }; &uart135 { diff --git a/dts/arm/nordic/nrf54h20_cpurad.dtsi b/dts/arm/nordic/nrf54h20_cpurad.dtsi index f30c777dbe2..7b7f236de0c 100644 --- a/dts/arm/nordic/nrf54h20_cpurad.dtsi +++ b/dts/arm/nordic/nrf54h20_cpurad.dtsi @@ -47,10 +47,6 @@ cpuppr_vevif: &cpuppr_vevif_remote {}; }; &grtc { - owned-channels = <7 8 9 10 11 12 13 14>; - child-owned-channels = <8 9 10 11 12>; - nonsecure-channels = <8 9 10 11 12>; interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>, - <109 NRF_DEFAULT_IRQ_PRIORITY>, - <110 NRF_DEFAULT_IRQ_PRIORITY>; + <108 NRF_DEFAULT_IRQ_PRIORITY>; }; From 4b8adc477f8cf4ac4eb05e2b5e86491386232f21 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:22 +0200 Subject: [PATCH 2234/2402] Revert "[nrf fromlist] boards: nordic: Add to GRTC missing child-owned-channels allocation" This reverts commit c98ea075249aba735508a2de53bbc4438ac943da. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts | 2 ++ dts/arm/nordic/nrf54h20_cpurad.dtsi | 3 +-- dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi | 4 +--- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts index fd65d2d495a..1998f4fc131 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts @@ -61,6 +61,8 @@ &grtc { status = "okay"; child-owned-channels = <8 9 10 11 12>; + interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>, + <108 NRF_DEFAULT_IRQ_PRIORITY>; nonsecure-channels = <8 9 10 11 12>; owned-channels = <7 8 9 10 11 12 13 14>; }; diff --git a/dts/arm/nordic/nrf54h20_cpurad.dtsi b/dts/arm/nordic/nrf54h20_cpurad.dtsi index 7b7f236de0c..2f463f2d427 100644 --- a/dts/arm/nordic/nrf54h20_cpurad.dtsi +++ b/dts/arm/nordic/nrf54h20_cpurad.dtsi @@ -47,6 +47,5 @@ cpuppr_vevif: &cpuppr_vevif_remote {}; }; &grtc { - interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>, - <108 NRF_DEFAULT_IRQ_PRIORITY>; + interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>; }; diff --git a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi index 25f94241336..485d85829a4 100644 --- a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi +++ b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi @@ -330,9 +330,7 @@ grtc: grtc@e2000 { reg = <0xe2000 0x1000>; cc-num = <12>; owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; - child-owned-channels = <7 8 9 10 11>; - interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>, - <229 NRF_DEFAULT_IRQ_PRIORITY>; + interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>; status = "disabled"; }; From 707103862c1ba000d5210e49785914a8261c1af4 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:22 +0200 Subject: [PATCH 2235/2402] Revert "[nrf fromtree] scripts: twister: handlers: pass dev-id for nrfutil" This reverts commit 5b8966b6c9ec3b2cae07bcec349e8e851795ab07. Signed-off-by: Gerard Marull-Paretas --- scripts/pylib/twister/twisterlib/handlers.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py index 6170fc8076e..3a13b819649 100755 --- a/scripts/pylib/twister/twisterlib/handlers.py +++ b/scripts/pylib/twister/twisterlib/handlers.py @@ -499,7 +499,7 @@ def _create_command(self, runner, hardware): board_id = hardware.probe_id or hardware.id product = hardware.product if board_id is not None: - if runner in ("pyocd", "nrfjprog", "nrfutil"): + if runner in ("pyocd", "nrfjprog"): command_extra_args.append("--dev-id") command_extra_args.append(board_id) elif runner == "openocd" and product == "STM32 STLink": From 09b1d1dfcfddc7a0891681108a1bf6f6090e6c3c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:22 +0200 Subject: [PATCH 2236/2402] Revert "[nrf fromlist] boards: nordic: nrf54h20dk: enable nrfutil" This reverts commit a316ce85304b757f5a51de20e75450fce1cc8ea6. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf54h20dk_nrf54h20/board.cmake | 2 -- boards/riscv/nrf54h20dk_nrf54h20/board.cmake | 3 --- 2 files changed, 5 deletions(-) delete mode 100644 boards/riscv/nrf54h20dk_nrf54h20/board.cmake diff --git a/boards/arm/nrf54h20dk_nrf54h20/board.cmake b/boards/arm/nrf54h20dk_nrf54h20/board.cmake index 6361f7fe7b4..32d1daac179 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/board.cmake +++ b/boards/arm/nrf54h20dk_nrf54h20/board.cmake @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) - if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD) if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD) set( diff --git a/boards/riscv/nrf54h20dk_nrf54h20/board.cmake b/boards/riscv/nrf54h20dk_nrf54h20/board.cmake deleted file mode 100644 index 86de994b4e2..00000000000 --- a/boards/riscv/nrf54h20dk_nrf54h20/board.cmake +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) From 1201d35e58895ce82885756334d618ecd3ebb467 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:22 +0200 Subject: [PATCH 2237/2402] Revert "[nrf fromtree] scripts: west_commands: runners: nrf_common: update nRF54H support" This reverts commit 79075ef37fbb80f0710262b2362fec6103da0ece. Signed-off-by: Gerard Marull-Paretas --- scripts/west_commands/runners/nrf_common.py | 62 +++++++++++---------- scripts/west_commands/runners/nrfjprog.py | 3 +- scripts/west_commands/tests/test_nrf.py | 21 +++---- 3 files changed, 42 insertions(+), 44 deletions(-) diff --git a/scripts/west_commands/runners/nrf_common.py b/scripts/west_commands/runners/nrf_common.py index 1ea09f8f595..76662c72ea9 100644 --- a/scripts/west_commands/runners/nrf_common.py +++ b/scripts/west_commands/runners/nrf_common.py @@ -29,6 +29,10 @@ 'NRFDL_DEVICE_CORE_APPLICATION': (0x00FF8000, 0x00FF8800), 'NRFDL_DEVICE_CORE_NETWORK': (0x01FF8000, 0x01FF8800), }, + 'NRF54H_FAMILY': { + 'NRFDL_DEVICE_CORE_APPLICATION': (0x0FFF8000, 0x0FFF8800), + 'NRFDL_DEVICE_CORE_NETWORK': (0x0FFFA000, 0x0FFFA800), + }, 'NRF91_FAMILY': { 'NRFDL_DEVICE_CORE_APPLICATION': (0x00FF8000, 0x00FF8800), } @@ -38,7 +42,8 @@ class NrfBinaryRunner(ZephyrBinaryRunner): '''Runner front-end base class for nrf tools.''' def __init__(self, cfg, family, softreset, dev_id, erase=False, - reset=True, tool_opt=[], force=False, recover=False): + reset=True, tool_opt=[], force=False, recover=False, + erase_all_uicrs=False): super().__init__(cfg) self.hex_ = cfg.hex_file if family and not family.endswith('_FAMILY'): @@ -50,6 +55,7 @@ def __init__(self, cfg, family, softreset, dev_id, erase=False, self.reset = bool(reset) self.force = force self.recover = bool(recover) + self.erase_all_uicrs = bool(erase_all_uicrs) self.tool_opt = [] for opts in [shlex.split(opt) for opt in tool_opt]: @@ -86,6 +92,11 @@ def do_add_parser(cls, parser): help='''erase all user available non-volatile memory and disable read back protection before flashing (erases flash for both cores on nRF53)''') + parser.add_argument('--erase-all-uicrs', required=False, + action='store_true', + help='''Erase all UICR registers before flashing + (nRF54H only). When not set, only UICR registers + present in the hex file will be erased.''') parser.set_defaults(reset=True) @@ -250,36 +261,14 @@ def program_hex(self): # Get the command use to actually program self.hex_. self.logger.info('Flashing file: {}'.format(self.hex_)) - # What type of erase/core arguments should we pass to the tool? - core = None - - if self.family == 'NRF54H_FAMILY': - erase_arg = 'ERASE_NONE' - - if self.erase: - self.exec_op('erase', core='NRFDL_DEVICE_CORE_APPLICATION') - self.exec_op('erase', core='NRFDL_DEVICE_CORE_NETWORK') - - if self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPUAPP'): - if not self.erase: - self.exec_op('erase', core='NRFDL_DEVICE_CORE_APPLICATION', - chip_erase_mode='ERASE_UICR', - qspi_erase_mode='ERASE_NONE') - core = 'NRFDL_DEVICE_CORE_APPLICATION' - elif self.build_conf.getboolean('CONFIG_SOC_NRF54H20_CPURAD'): - if not self.erase: - self.exec_op('erase', core='NRFDL_DEVICE_CORE_NETWORK', - chip_erase_mode='ERASE_UICR', - qspi_erase_mode='ERASE_NONE') - core = 'NRFDL_DEVICE_CORE_NETWORK' + # What type of erase argument should we pass to the tool? + if self.erase: + erase_arg = 'ERASE_ALL' else: - if self.erase: - erase_arg = 'ERASE_ALL' + if self.family == 'NRF52_FAMILY': + erase_arg = 'ERASE_PAGES_INCLUDING_UICR' else: - if self.family == 'NRF52_FAMILY': - erase_arg = 'ERASE_PAGES_INCLUDING_UICR' - else: - erase_arg = 'ERASE_PAGES' + erase_arg = 'ERASE_PAGES' xip_ranges = { 'NRF52_FAMILY': (0x12000000, 0x19FFFFFF), @@ -295,11 +284,24 @@ def program_hex(self): if self.family == 'NRF53_FAMILY': # nRF53 requires special treatment due to the extra coprocessor. self.program_hex_nrf53(erase_arg, qspi_erase_opt) + elif self.family == 'NRF54H_FAMILY': + self.program_hex_nrf54h() else: - self.op_program(self.hex_, erase_arg, qspi_erase_opt, defer=True, core=core) + self.op_program(self.hex_, erase_arg, qspi_erase_opt, defer=True) self.flush(force=False) + def program_hex_nrf54h(self): + if self.erase_all_uicrs: + uicrs = UICR_RANGES['NRF54H_FAMILY'] + else: + uicrs = self.hex_get_uicrs() + + for uicr_core, range in uicrs.items(): + self.exec_op('erasepage', defer=True, core=uicr_core, page=range[0]) + + self.op_program(self.hex_, 'NO_ERASE', None, defer=True) + def program_hex_nrf53(self, erase_arg, qspi_erase_opt): # program_hex() helper for nRF53. diff --git a/scripts/west_commands/runners/nrfjprog.py b/scripts/west_commands/runners/nrfjprog.py index f4bdfa74f97..cfcf43c9e78 100644 --- a/scripts/west_commands/runners/nrfjprog.py +++ b/scripts/west_commands/runners/nrfjprog.py @@ -32,7 +32,8 @@ def do_create(cls, cfg, args): args.dev_id, erase=args.erase, reset=args.reset, tool_opt=args.tool_opt, force=args.force, - recover=args.recover) + recover=args.recover, + erase_all_uicrs=args.erase_all_uicrs) def do_get_boards(self): snrs = self.check_output(['nrfjprog', '--ids']) diff --git a/scripts/west_commands/tests/test_nrf.py b/scripts/west_commands/tests/test_nrf.py index d3f429ef775..a15fe2302e5 100644 --- a/scripts/west_commands/tests/test_nrf.py +++ b/scripts/west_commands/tests/test_nrf.py @@ -5,7 +5,6 @@ import argparse import functools -import io import os from pathlib import Path import shlex @@ -524,16 +523,14 @@ def check_expected(tool, test_case, check_fn, get_snr, tmpdir, runner_config): tmpfile = nrfutil_args[nrfutil_args.index('--batch-path') + 1] cmds = (['nrfutil', '--json', 'device', 'x-execute-batch', '--batch-path', tmpfile, '--serial-number', expected[0]],) - call_args = [call(nrfutil_args)] else: cmds = expected - call_args = check_fn.call_args_list if callable(cmds): - assert (call_args == + assert (check_fn.call_args_list == [call(x) for x in cmds(tmpdir, runner_config.hex_file)]) else: - assert call_args == [call(x) for x in cmds] + assert check_fn.call_args_list == [call(x) for x in cmds] if not test_case.snr: get_snr.assert_called_once_with('*') @@ -545,11 +542,10 @@ def check_expected(tool, test_case, check_fn, get_snr, tmpdir, runner_config): @patch('runners.core.ZephyrBinaryRunner.require') @patch('runners.nrfjprog.NrfBinaryRunner.get_board_snr', side_effect=get_board_snr_patch) -@patch('runners.nrfutil.subprocess.Popen') +@patch('runners.nrfjprog.NrfBinaryRunner.check_output') @patch('runners.nrfjprog.NrfBinaryRunner.check_call') -def test_init(check_call, popen, get_snr, require, tool, test_case, +def test_init(check_call, check_output, get_snr, require, tool, test_case, runner_config, tmpdir): - popen.return_value.__enter__.return_value.stdout = io.BytesIO(b'') require.side_effect = functools.partial(require_patch, tool) runner_config = fix_up_runner_config(test_case, runner_config, tmpdir) @@ -568,7 +564,7 @@ def test_init(check_call, popen, get_snr, require, tool, test_case, runner.run('flash') assert require.called - CHECK_FN_MAP = {'nrfjprog': check_call, 'nrfutil': popen} + CHECK_FN_MAP = {'nrfjprog': check_call, 'nrfutil': check_output} check_expected(tool, test_case, CHECK_FN_MAP[tool], get_snr, tmpdir, runner_config) @@ -577,11 +573,10 @@ def test_init(check_call, popen, get_snr, require, tool, test_case, @patch('runners.core.ZephyrBinaryRunner.require') @patch('runners.nrfjprog.NrfBinaryRunner.get_board_snr', side_effect=get_board_snr_patch) -@patch('runners.nrfutil.subprocess.Popen') +@patch('runners.nrfjprog.NrfBinaryRunner.check_output') @patch('runners.nrfjprog.NrfBinaryRunner.check_call') -def test_create(check_call, popen, get_snr, require, tool, test_case, +def test_create(check_call, check_output, get_snr, require, tool, test_case, runner_config, tmpdir): - popen.return_value.__enter__.return_value.stdout = io.BytesIO(b'') require.side_effect = functools.partial(require_patch, tool) runner_config = fix_up_runner_config(test_case, runner_config, tmpdir) @@ -608,6 +603,6 @@ def test_create(check_call, popen, get_snr, require, tool, test_case, assert require.called - CHECK_FN_MAP = {'nrfjprog': check_call, 'nrfutil': popen} + CHECK_FN_MAP = {'nrfjprog': check_call, 'nrfutil': check_output} check_expected(tool, test_case, CHECK_FN_MAP[tool], get_snr, tmpdir, runner_config) From 054728fc814d030fa7532f7b18d4332d762614f2 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:23 +0200 Subject: [PATCH 2238/2402] Revert "[nrf fromtree] scripts: west_commands: runners: nrfutil: provide live feedback" This reverts commit 084cec5e437aadd93b5479a74eb2e20b6f6a0df4. Signed-off-by: Gerard Marull-Paretas --- scripts/west_commands/runners/nrfutil.py | 51 ++++++++++-------------- 1 file changed, 21 insertions(+), 30 deletions(-) diff --git a/scripts/west_commands/runners/nrfutil.py b/scripts/west_commands/runners/nrfutil.py index a7ff512bb9f..50db41abae2 100644 --- a/scripts/west_commands/runners/nrfutil.py +++ b/scripts/west_commands/runners/nrfutil.py @@ -10,10 +10,8 @@ import sys import subprocess -from runners.core import _DRY_RUN from runners.nrf_common import NrfBinaryRunner - class NrfUtilBinaryRunner(NrfBinaryRunner): '''Runner front-end for nrfutil.''' @@ -42,34 +40,27 @@ def do_create(cls, cfg, args): recover=args.recover) def _exec(self, args): - jout_all = [] - - cmd = ['nrfutil', '--json', 'device'] + args - self._log_cmd(cmd) - - if _DRY_RUN: - return {} - - with subprocess.Popen(cmd, stdout=subprocess.PIPE) as p: - for line in iter(p.stdout.readline, b''): - # https://github.com/ndjson/ndjson-spec - jout = json.loads(line.decode(sys.getdefaultencoding())) - jout_all.append(jout) - - if 'x-execute-batch' in args: - if jout['type'] == 'batch_update': - pld = jout['data']['data'] - if ( - pld['type'] == 'task_progress' and - pld['data']['progress']['progressPercentage'] == 0 - ): - self.logger.info(pld['data']['progress']['description']) - elif jout['type'] == 'batch_end' and jout['data']['error']: - raise subprocess.CalledProcessError( - jout['data']['error']['code'], cmd - ) - - return jout_all + try: + out = self.check_output(['nrfutil', '--json', 'device'] + args) + except subprocess.CalledProcessError as e: + # https://docs.python.org/3/reference/compound_stmts.html#except-clause + cpe = e + out = cpe.stdout + else: + cpe = None + finally: + # https://github.com/ndjson/ndjson-spec + out = [json.loads(s) for s in + out.decode(sys.getdefaultencoding()).split('\n') if len(s)] + self.logger.debug(f'output: {out}') + if cpe: + if 'execute-batch' in args: + for o in out: + if o['type'] == 'batch_end' and o['data']['error']: + cpe.returncode = o['data']['error']['code'] + raise cpe + + return out def do_get_boards(self): out = self._exec(['list']) From 2df4882d4464fd42d6006c3028369709f6d87b85 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:23 +0200 Subject: [PATCH 2239/2402] Revert "[nrf fromtree] scripts: west_commands: runners: nrfutil: use x-execute-batch" This reverts commit 09101e38a030f12e8ff8c6e97fc7cc4aa20a9d6b. Signed-off-by: Gerard Marull-Paretas --- scripts/west_commands/runners/nrfutil.py | 2 +- scripts/west_commands/tests/test_nrf.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/west_commands/runners/nrfutil.py b/scripts/west_commands/runners/nrfutil.py index 50db41abae2..719e432a23b 100644 --- a/scripts/west_commands/runners/nrfutil.py +++ b/scripts/west_commands/runners/nrfutil.py @@ -97,7 +97,7 @@ def _exec_batch(self): self._ops = [] self._op_id = 1 self.logger.debug(f'Executing batch in: {json_file}') - self._exec(['x-execute-batch', '--batch-path', f'{json_file}', + self._exec(['execute-batch', '--batch-path', f'{json_file}', '--serial-number', f'{self.dev_id}']) def do_exec_op(self, op, force=False): diff --git a/scripts/west_commands/tests/test_nrf.py b/scripts/west_commands/tests/test_nrf.py index a15fe2302e5..405e6ea9d6c 100644 --- a/scripts/west_commands/tests/test_nrf.py +++ b/scripts/west_commands/tests/test_nrf.py @@ -521,7 +521,7 @@ def check_expected(tool, test_case, check_fn, get_snr, tmpdir, runner_config): # Extract filename nrfutil_args = check_fn.call_args_list[0].args[0] tmpfile = nrfutil_args[nrfutil_args.index('--batch-path') + 1] - cmds = (['nrfutil', '--json', 'device', 'x-execute-batch', '--batch-path', + cmds = (['nrfutil', '--json', 'device', 'execute-batch', '--batch-path', tmpfile, '--serial-number', expected[0]],) else: cmds = expected From ac2f1a8c68f10384c4b43d13da4d16d2f7ad8bdd Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:23 +0200 Subject: [PATCH 2240/2402] Revert "[nrf fromtree] scripts: west_commands: runners: nrfjprog: drop nRF54H support" This reverts commit 6e6e417a4356f9e0c4935ae5388e971698b1ed68. Signed-off-by: Gerard Marull-Paretas --- scripts/west_commands/runners/nrfjprog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/west_commands/runners/nrfjprog.py b/scripts/west_commands/runners/nrfjprog.py index cfcf43c9e78..723080d56c3 100644 --- a/scripts/west_commands/runners/nrfjprog.py +++ b/scripts/west_commands/runners/nrfjprog.py @@ -48,7 +48,7 @@ def do_exec_op(self, op, force=False): families = {'NRF51_FAMILY': 'NRF51', 'NRF52_FAMILY': 'NRF52', 'NRF53_FAMILY': 'NRF53', 'NRF54L_FAMILY': 'NRF54L', - 'NRF91_FAMILY': 'NRF91'} + 'NRF54H_FAMILY': 'NRF54H', 'NRF91_FAMILY': 'NRF91'} cores = {'NRFDL_DEVICE_CORE_APPLICATION': 'CP_APPLICATION', 'NRFDL_DEVICE_CORE_NETWORK': 'CP_NETWORK'} From 895caa12c2d35e1b5944a50e5b3b0173ed2adb01 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:23 +0200 Subject: [PATCH 2241/2402] Revert "[nrf fromtree] scripts: test for imported ELFFile instead of setting it to None" This reverts commit 50d71e240539698b2b6a0da5f8c311cdfa22e4ed. Signed-off-by: Gerard Marull-Paretas --- scripts/west_commands/runners/intel_cyclonev.py | 16 ++++++++++++---- scripts/west_commands/runners/openocd.py | 8 +++----- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/scripts/west_commands/runners/intel_cyclonev.py b/scripts/west_commands/runners/intel_cyclonev.py index c6bfb65eeef..eb67c860800 100644 --- a/scripts/west_commands/runners/intel_cyclonev.py +++ b/scripts/west_commands/runners/intel_cyclonev.py @@ -11,6 +11,11 @@ from os import path from pathlib import Path +try: + from elftools.elf.elffile import ELFFile +except ImportError: + ELFFile = None + from runners.core import ZephyrBinaryRunner, RunnerCaps DEFAULT_OPENOCD_TCL_PORT = 6333 @@ -190,7 +195,7 @@ def to_num(self, number): def read_version(self): self.require(self.openocd_cmd[0]) - # OpenOCD prints in stderr, need redirect to get output + # OpenOCD prints in stderr, need redirect to get output out = self.check_output([self.openocd_cmd[0], '--version'], stderr=subprocess.STDOUT).decode() @@ -205,6 +210,9 @@ def supports_thread_info(self): def do_run(self, command, **kwargs): self.require(self.openocd_cmd[0]) + if ELFFile is None: + raise RuntimeError( + 'elftools missing; please "pip3 install elftools"') self.cfg_cmd = [] if self.openocd_config is not None: @@ -264,11 +272,11 @@ def do_flash_elf(self, **kwargs): self.require(gdb_cmd[0]) self.print_gdbserver_message() - cmd1 = echo + server_cmd + cmd1 = (echo + server_cmd) self.check_call(cmd1) - cmd2 = echo + gdb_cmd + cmd2 = (echo + gdb_cmd) self.check_call(cmd2) - cmd3 = echo + gdb_cmd2 + cmd3 = (echo + gdb_cmd2) self.check_call(cmd3) self.run_server_and_client(server_cmd, gdb_cmd) diff --git a/scripts/west_commands/runners/openocd.py b/scripts/west_commands/runners/openocd.py index dd7c6882a36..ff92d4f58f4 100644 --- a/scripts/west_commands/runners/openocd.py +++ b/scripts/west_commands/runners/openocd.py @@ -1,8 +1,6 @@ # Copyright (c) 2017 Linaro Limited. # # SPDX-License-Identifier: Apache-2.0 -# -# pylint: disable=duplicate-code '''Runner for openocd.''' @@ -15,7 +13,7 @@ try: from elftools.elf.elffile import ELFFile except ImportError: - pass + ELFFile = None from runners.core import ZephyrBinaryRunner @@ -191,7 +189,7 @@ def to_num(self, number): def read_version(self): self.require(self.openocd_cmd[0]) - # OpenOCD prints in stderr, need redirect to get output + # OpenOCD prints in stderr, need redirect to get output out = self.check_output([self.openocd_cmd[0], '--version'], stderr=subprocess.STDOUT).decode() @@ -206,7 +204,7 @@ def supports_thread_info(self): def do_run(self, command, **kwargs): self.require(self.openocd_cmd[0]) - if globals().get('ELFFile') is None: + if ELFFile is None: raise RuntimeError( 'elftools missing; please "pip3 install elftools"') From 86ce31a0ced7549ae57dd64355e63e788a43d7b0 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:23 +0200 Subject: [PATCH 2242/2402] Revert "[nrf fromtree] drivers: misc: nordic_vpr_launcher: Update src/exec memory size check" This reverts commit bcb46da71cd8bdd05e159de349384f12b8009994. Signed-off-by: Gerard Marull-Paretas --- .../nordic_vpr_launcher/nordic_vpr_launcher.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c b/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c index 11b75a2c0e5..64d4969081b 100644 --- a/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c +++ b/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c @@ -22,7 +22,7 @@ struct nordic_vpr_launcher_config { uintptr_t exec_addr; #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(source_memory) uintptr_t src_addr; - size_t size; + size_t src_size; #endif }; @@ -31,10 +31,10 @@ static int nordic_vpr_launcher_init(const struct device *dev) const struct nordic_vpr_launcher_config *config = dev->config; #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(source_memory) - if (config->size > 0U) { + if (config->src_size > 0U) { LOG_DBG("Loading VPR (%p) from %p to %p (%zu bytes)", config->vpr, - (void *)config->src_addr, (void *)config->exec_addr, config->size); - memcpy((void *)config->exec_addr, (void *)config->src_addr, config->size); + (void *)config->src_addr, (void *)config->exec_addr, config->src_size); + memcpy((void *)config->exec_addr, (void *)config->src_addr, config->src_size); } #endif @@ -51,17 +51,19 @@ static int nordic_vpr_launcher_init(const struct device *dev) COND_CODE_0(DT_FIXED_PARTITION_EXISTS(node_id), (0), (DT_REG_ADDR(DT_GPARENT(node_id))))) #define NORDIC_VPR_LAUNCHER_DEFINE(inst) \ - IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, source_memory), \ - (BUILD_ASSERT((DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)) <= \ - DT_REG_SIZE(DT_INST_PHANDLE(inst, source_memory))), \ - "Execution memory exceeds source memory size");)) \ + COND_CODE_1(DT_NODE_HAS_PROP(inst, source_memory), \ + (BUILD_ASSERT((DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)) == \ + DT_REG_SIZE(DT_INST_PHANDLE(inst, source_memory))), \ + "Source/execution memory sizes mismatch");), \ + ()) \ \ static const struct nordic_vpr_launcher_config config##inst = { \ .vpr = (NRF_VPR_Type *)DT_INST_REG_ADDR(inst), \ .exec_addr = VPR_ADDR(DT_INST_PHANDLE(inst, execution_memory)), \ - IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, source_memory), \ - (.src_addr = VPR_ADDR(DT_INST_PHANDLE(inst, source_memory)), \ - .size = DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)),))}; \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, source_memory), \ + (.src_addr = VPR_ADDR(DT_INST_PHANDLE(inst, source_memory)), \ + .src_size = DT_REG_SIZE(DT_INST_PHANDLE(inst, source_memory)),), \ + ())}; \ \ DEVICE_DT_INST_DEFINE(inst, nordic_vpr_launcher_init, NULL, NULL, &config##inst, \ POST_KERNEL, CONFIG_NORDIC_VPR_LAUNCHER_INIT_PRIORITY, NULL); From 02f56db5ee8ff0fd63d917e506e10dfa61237343 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:24 +0200 Subject: [PATCH 2243/2402] Revert "[nrf fromlist] snippets: Add nordic-ppr-xip" This reverts commit daa61372e121eaf4c261112434b0b90d2dab60e6. Signed-off-by: Gerard Marull-Paretas --- snippets/nordic-ppr-xip/README.rst | 12 ------------ .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 17 ----------------- snippets/nordic-ppr-xip/nordic-ppr-xip.overlay | 8 -------- snippets/nordic-ppr-xip/snippet.yml | 8 -------- 4 files changed, 45 deletions(-) delete mode 100644 snippets/nordic-ppr-xip/README.rst delete mode 100644 snippets/nordic-ppr-xip/boards/nrf54h20dk_nrf54h20_cpuapp.overlay delete mode 100644 snippets/nordic-ppr-xip/nordic-ppr-xip.overlay delete mode 100644 snippets/nordic-ppr-xip/snippet.yml diff --git a/snippets/nordic-ppr-xip/README.rst b/snippets/nordic-ppr-xip/README.rst deleted file mode 100644 index 64977da2989..00000000000 --- a/snippets/nordic-ppr-xip/README.rst +++ /dev/null @@ -1,12 +0,0 @@ -.. _nordic-ppr-xip: - -Nordic boot PPR snippet with execution in place (nordic-ppr-xip) -################################################################ - -Overview -******** - -This snippet allows users to build Zephyr with the capability to boot Nordic PPR -(Peripheral Processor) from another core. PPR code is to be executed from MRAM, -so the PPR image must be built for the ``xip`` board variant, or with -:kconfig:option:`CONFIG_XIP` enabled. diff --git a/snippets/nordic-ppr-xip/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/snippets/nordic-ppr-xip/boards/nrf54h20dk_nrf54h20_cpuapp.overlay deleted file mode 100644 index 4d02921660b..00000000000 --- a/snippets/nordic-ppr-xip/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * SPDX-License-Identifier: Apache-2.0 - */ - -&cpuppr_ram3x_region { - status = "okay"; -}; - -&cpuppr_vpr { - execution-memory = <&cpuppr_code_partition>; - /delete-property/ source-memory; -}; - -&uart135 { - status = "reserved"; -}; diff --git a/snippets/nordic-ppr-xip/nordic-ppr-xip.overlay b/snippets/nordic-ppr-xip/nordic-ppr-xip.overlay deleted file mode 100644 index e33885fc10d..00000000000 --- a/snippets/nordic-ppr-xip/nordic-ppr-xip.overlay +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * SPDX-License-Identifier: Apache-2.0 - */ - -&cpuppr_vpr { - status = "okay"; -}; diff --git a/snippets/nordic-ppr-xip/snippet.yml b/snippets/nordic-ppr-xip/snippet.yml deleted file mode 100644 index 4af89ccc2c0..00000000000 --- a/snippets/nordic-ppr-xip/snippet.yml +++ /dev/null @@ -1,8 +0,0 @@ -name: nordic-ppr-xip -append: - EXTRA_DTC_OVERLAY_FILE: nordic-ppr-xip.overlay - -boards: - nrf54h20dk_nrf54h20_cpuapp: - append: - EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay From 01f611e27a74f8e1db95d6c268de0223878eb962 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:24 +0200 Subject: [PATCH 2244/2402] Revert "[nrf fromlist] snippets: Remove nordic-ppr-ram" This reverts commit c676736bb95569ee8c2cd5d09e56ff4d5d347d31. Signed-off-by: Gerard Marull-Paretas --- snippets/nordic-ppr-ram/README.rst | 11 +++++++++++ .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 16 ++++++++++++++++ snippets/nordic-ppr-ram/nordic-ppr-ram.overlay | 15 +++++++++++++++ snippets/nordic-ppr-ram/snippet.yml | 8 ++++++++ 4 files changed, 50 insertions(+) create mode 100644 snippets/nordic-ppr-ram/README.rst create mode 100644 snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay create mode 100644 snippets/nordic-ppr-ram/nordic-ppr-ram.overlay create mode 100644 snippets/nordic-ppr-ram/snippet.yml diff --git a/snippets/nordic-ppr-ram/README.rst b/snippets/nordic-ppr-ram/README.rst new file mode 100644 index 00000000000..501e5073357 --- /dev/null +++ b/snippets/nordic-ppr-ram/README.rst @@ -0,0 +1,11 @@ +.. _nordic-ppr-ram: + +Nordic boot PPR snippet with execution from RAM (nordic-ppr-ram) +################################################################ + +Overview +******** + +This snippet allows users to build Zephyr with the capability to boot Nordic PPR +(Peripheral Processor) from another core. PPR code is executed from RAM. Note +that PPR image must be built with :kconfig:option:`CONFIG_XIP` disabled. diff --git a/snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..ea866358fc0 --- /dev/null +++ b/snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&cpuppr_code_data { + status = "okay"; +}; + +&cpuppr_vpr { + execution-memory = <&cpuppr_code_data>; +}; + +&uart135 { + status = "reserved"; +}; diff --git a/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay b/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay new file mode 100644 index 00000000000..71c45c1b9f4 --- /dev/null +++ b/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +/* code is sourced from cpuppr code partition */ +&cpuppr_vpr { + status = "okay"; + source-memory = <&cpuppr_code_partition>; +}; + +/* code partition size must match RAM size */ +&cpuppr_code_partition { + reg = <0x126000 DT_SIZE_K(62)>; +}; diff --git a/snippets/nordic-ppr-ram/snippet.yml b/snippets/nordic-ppr-ram/snippet.yml new file mode 100644 index 00000000000..022ed8d38e8 --- /dev/null +++ b/snippets/nordic-ppr-ram/snippet.yml @@ -0,0 +1,8 @@ +name: nordic-ppr-ram +append: + EXTRA_DTC_OVERLAY_FILE: nordic-ppr-ram.overlay + +boards: + nrf54h20dk_nrf54h20_cpuapp: + append: + EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay From 64ed4e0435588bac8646872c449e30a7fb67f89c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:24 +0200 Subject: [PATCH 2245/2402] Revert "[nrf fromlist] boards: nrf54h20dk: Make execution from RAM default for PPR" This reverts commit 7852ea12dddd317d8ab02874596d85a1f2f7771b. Signed-off-by: Gerard Marull-Paretas --- .../arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts | 3 +-- .../nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.yaml | 2 +- .../nrf54h20dk_nrf54h20_cpuppr_defconfig | 3 --- ...20_cpuppr_xip.dts => nrf54h20dk_nrf54h20_cpuppr_ram.dts} | 0 ..._cpuppr_xip.yaml => nrf54h20dk_nrf54h20_cpuppr_ram.yaml} | 6 +++--- ...p_defconfig => nrf54h20dk_nrf54h20_cpuppr_ram_defconfig} | 2 +- 6 files changed, 6 insertions(+), 10 deletions(-) rename boards/riscv/nrf54h20dk_nrf54h20/{nrf54h20dk_nrf54h20_cpuppr_xip.dts => nrf54h20dk_nrf54h20_cpuppr_ram.dts} (100%) rename boards/riscv/nrf54h20dk_nrf54h20/{nrf54h20dk_nrf54h20_cpuppr_xip.yaml => nrf54h20dk_nrf54h20_cpuppr_ram.yaml} (62%) rename boards/riscv/nrf54h20dk_nrf54h20/{nrf54h20dk_nrf54h20_cpuppr_xip_defconfig => nrf54h20dk_nrf54h20_cpuppr_ram_defconfig} (95%) diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts index a8ea9fe730f..3873fec457e 100644 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts @@ -131,8 +131,7 @@ }; &cpuppr_vpr { - execution-memory = <&cpuppr_code_data>; - source-memory = <&cpuppr_code_partition>; + execution-memory = <&cpuppr_code_partition>; }; &gpiote130 { diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.yaml b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.yaml index 839869d55c2..02e28651f5d 100644 --- a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.yaml +++ b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.yaml @@ -8,6 +8,6 @@ arch: riscv toolchain: - zephyr ram: 62 -flash: 62 +flash: 64 supported: - gpio diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_defconfig b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_defconfig index 1e4c72309c6..2f6ccc43892 100644 --- a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_defconfig +++ b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_defconfig @@ -12,6 +12,3 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# Execute from RAM -CONFIG_XIP=n diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_xip.dts b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.dts similarity index 100% rename from boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_xip.dts rename to boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.dts diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_xip.yaml b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.yaml similarity index 62% rename from boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_xip.yaml rename to boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.yaml index 82f2109707a..26d6ebeac9a 100644 --- a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_xip.yaml +++ b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.yaml @@ -1,13 +1,13 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: nrf54h20dk_nrf54h20_cpuppr_xip -name: nRF54H20-DK-nRF54H20-PPR (MRAM XIP) +identifier: nrf54h20dk_nrf54h20_cpuppr_ram +name: nRF54H20-DK-nRF54H20-PPR-RAM type: mcu arch: riscv toolchain: - zephyr ram: 62 -flash: 64 +flash: 62 supported: - gpio diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_xip_defconfig b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig similarity index 95% rename from boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_xip_defconfig rename to boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig index 7e4a13b811b..73056fac7ef 100644 --- a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_xip_defconfig +++ b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig @@ -13,4 +13,4 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -CONFIG_XIP=y +CONFIG_XIP=n From 86629f0efe3ba636ce9d4c6437566e118e9f8a34 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:24 +0200 Subject: [PATCH 2246/2402] Revert "[nrf fromlist] soc: nordic: Remove support for nRF54H20 EngA" This reverts commit faee8c01b85062c17441675717a73fc7ae67f925. Signed-off-by: Gerard Marull-Paretas --- .../Kconfig.defconfig.nrf54h20_enga_cpuapp | 17 +++++++++++++++++ .../Kconfig.defconfig.nrf54h20_enga_cpurad | 17 +++++++++++++++++ soc/arm/nordic_nrf/nrf54h/Kconfig.soc | 16 ++++++++++++++++ soc/arm/nordic_nrf/nrf54h/soc.c | 10 ++++++++++ .../nordic_nrf/common/vpr/Kconfig.defconfig | 6 ++++++ .../Kconfig.defconfig.nrf54h20_enga_cpuppr | 15 +++++++++++++++ soc/riscv/nordic_nrf/nrf54h/Kconfig.soc | 4 ++++ 7 files changed, 85 insertions(+) create mode 100644 soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp create mode 100644 soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad create mode 100644 soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp new file mode 100644 index 00000000000..d90f87c0b89 --- /dev/null +++ b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp @@ -0,0 +1,17 @@ +# Nordic Semiconductor nRF54H20 Application MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF54H20_ENGA_CPUAPP + +config SOC + default "nrf54h20_enga_cpuapp" + +config NUM_IRQS + default 471 + +config NRF_REGTOOL_GENERATE_UICR + default y + +endif # SOC_NRF54H20_ENGA_CPUAPP diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad new file mode 100644 index 00000000000..6aae8c3a105 --- /dev/null +++ b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad @@ -0,0 +1,17 @@ +# Nordic Semiconductor nRF54H20 Radio MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF54H20_ENGA_CPURAD + +config SOC + default "nrf54h20_enga_cpurad" + +config NUM_IRQS + default 471 + +config NRF_REGTOOL_GENERATE_UICR + default y + +endif # SOC_NRF54H20_ENGA_CPURAD diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.soc b/soc/arm/nordic_nrf/nrf54h/Kconfig.soc index be8752c8b5f..32256a809a9 100644 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.soc +++ b/soc/arm/nordic_nrf/nrf54h/Kconfig.soc @@ -28,6 +28,22 @@ config SOC_NRF54H20_CPURAD select CPU_HAS_ICACHE select CPU_HAS_FPU +config SOC_NRF54H20_ENGA_CPUAPP + bool "nRF54H20 ENGA CPUAPP" + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_FPU + +config SOC_NRF54H20_ENGA_CPURAD + bool "nRF54H20 ENGA CPURAD" + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_FPU + endchoice config NRF_ENABLE_ICACHE diff --git a/soc/arm/nordic_nrf/nrf54h/soc.c b/soc/arm/nordic_nrf/nrf54h/soc.c index cf134dc99b1..9fefd414152 100644 --- a/soc/arm/nordic_nrf/nrf54h/soc.c +++ b/soc/arm/nordic_nrf/nrf54h/soc.c @@ -44,6 +44,10 @@ static void power_domain_init(void) nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true); nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true); + +#if defined(CONFIG_SOC_NRF54H20_ENGA_CPUAPP) + nrf_lrcconf_poweron_force_set(NRF_LRCCONF000, NRF_LRCCONF_POWER_DOMAIN_0, true); +#endif } static int trim_hsfll(void) @@ -65,6 +69,12 @@ static int trim_hsfll(void) nrf_hsfll_trim_set(hsfll, &trim); nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE); +#if defined(CONFIG_SOC_NRF54H20_ENGA_CPUAPP) || defined(CONFIG_SOC_NRF54H20_ENGA_CPURAD) + /* In this HW revision, HSFLL task frequency change needs to be + * triggered additional time to take effect. + */ + nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE); +#endif LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP); LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE); diff --git a/soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig b/soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig index ccab6b62c1d..a89593170f6 100644 --- a/soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig +++ b/soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig @@ -1,6 +1,12 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +CPU_PATH := $(dt_nodelabel_path,cpu) +CPU_ID := $(dt_node_reg_addr_int,$(CPU_PATH)) + +config RV_BOOT_HART + default $(CPU_ID) if SOC_NRF54H20_ENGA_CPUPPR + config RISCV_MCAUSE_EXCEPTION_MASK default 0xFFF diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr b/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr new file mode 100644 index 00000000000..a36d24c72ae --- /dev/null +++ b/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF54H20_ENGA_CPUPPR + +config SOC + default "nrf54h20_enga_cpuppr" + +config NUM_IRQS + default 496 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +endif # SOC_NRF54H20_ENGA_CPUPPR diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc b/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc index 51d42e201f9..47138277fce 100644 --- a/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc +++ b/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc @@ -14,6 +14,10 @@ config SOC_NRF54H20_CPUPPR bool "nRF54H20 CPUPPR" select RISCV +config SOC_NRF54H20_ENGA_CPUPPR + bool "nRF54H20 ENGA CPUPPR" + depends on RISCV_CORE_NORDIC_VPR + endchoice endif # SOC_NRF54H20 From 7a6d7ab2d6732ec667d06ce1fc057890bc025385 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:25 +0200 Subject: [PATCH 2247/2402] Revert "[nrf fromtree] dts: Remove support for nRF54H20 EngA" This reverts commit 0938076a408d4ec076d8886d32ccb5016b8434d2. Signed-off-by: Gerard Marull-Paretas --- dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi | 51 + dts/arm/nordic/nrf54h20_enga_cpurad.dtsi | 51 + dts/common/nordic/nrf54h20_enga.dtsi | 941 ++++++++++++++++++ dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi | 48 + .../misc/nordic-nrf-ficr-nrf54h20-enga.h | 96 ++ 5 files changed, 1187 insertions(+) create mode 100644 dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi create mode 100644 dts/arm/nordic/nrf54h20_enga_cpurad.dtsi create mode 100644 dts/common/nordic/nrf54h20_enga.dtsi create mode 100644 dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi create mode 100644 include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20-enga.h diff --git a/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi b/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi new file mode 100644 index 00000000000..7252b3d5a04 --- /dev/null +++ b/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +cpu: &cpuapp {}; +systick: &cpuapp_systick {}; +nvic: &cpuapp_nvic {}; +cpuppr_vevif: &cpuppr_vevif_remote {}; + +/delete-node/ &cpuppr; +/delete-node/ &cpurad; +/delete-node/ &cpurad_peripherals; +/delete-node/ &cpurad_ppb; +/delete-node/ &cpurad_ram0; + +/ { + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpuapp_nvic>; + ranges; + }; +}; + +&cpuapp_ppb { + compatible = "simple-bus"; + ranges; +}; + +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-local"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&gpiote130 { + interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&grtc { + interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>; +}; diff --git a/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi b/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi new file mode 100644 index 00000000000..d2aaa790349 --- /dev/null +++ b/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +cpu: &cpurad {}; +systick: &cpurad_systick {}; +nvic: &cpurad_nvic {}; +cpuppr_vevif: &cpuppr_vevif_remote {}; + +/delete-node/ &cpuapp; +/delete-node/ &cpuapp_peripherals; +/delete-node/ &cpuapp_ppb; +/delete-node/ &cpuapp_ram0; +/delete-node/ &cpuppr; + +/ { + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpurad_nvic>; + ranges; + }; +}; + +&cpurad_ppb { + compatible = "simple-bus"; + ranges; +}; + +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-local"; +}; + +&gpiote130 { + interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&grtc { + interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>; +}; diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi new file mode 100644 index 00000000000..8552b9534eb --- /dev/null +++ b/dts/common/nordic/nrf54h20_enga.dtsi @@ -0,0 +1,941 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +/* Domain IDs. Can be used to specify channel links in IPCT nodes. */ +#define NRF_DOMAIN_ID_APPLICATION 2 +#define NRF_DOMAIN_ID_RADIOCORE 3 +#define NRF_DOMAIN_ID_GLOBALFAST 12 +#define NRF_DOMAIN_ID_GLOBALSLOW 13 + +/delete-node/ &sw_pwm; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpuapp: cpu@2 { + compatible = "arm,cortex-m33"; + reg = <2>; + device_type = "cpu"; + clock-frequency = ; + }; + + cpurad: cpu@3 { + compatible = "arm,cortex-m33"; + reg = <3>; + device_type = "cpu"; + clock-frequency = ; + }; + + cpuppr: cpu@d { + compatible = "nordic,vpr"; + reg = <13>; + device_type = "cpu"; + clock-frequency = ; + riscv,isa = "rv32emc"; + nordic,bus-width = <32>; + + cpuppr_vevif_local: mailbox { + compatible = "nordic,nrf-vevif-local"; + status = "disabled"; + interrupt-parent = <&cpuppr_clic>; + interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, + <1 NRF_DEFAULT_IRQ_PRIORITY>, + <2 NRF_DEFAULT_IRQ_PRIORITY>, + <3 NRF_DEFAULT_IRQ_PRIORITY>, + <4 NRF_DEFAULT_IRQ_PRIORITY>, + <5 NRF_DEFAULT_IRQ_PRIORITY>, + <6 NRF_DEFAULT_IRQ_PRIORITY>, + <7 NRF_DEFAULT_IRQ_PRIORITY>, + <8 NRF_DEFAULT_IRQ_PRIORITY>, + <9 NRF_DEFAULT_IRQ_PRIORITY>, + <10 NRF_DEFAULT_IRQ_PRIORITY>, + <11 NRF_DEFAULT_IRQ_PRIORITY>, + <12 NRF_DEFAULT_IRQ_PRIORITY>, + <13 NRF_DEFAULT_IRQ_PRIORITY>, + <14 NRF_DEFAULT_IRQ_PRIORITY>, + <15 NRF_DEFAULT_IRQ_PRIORITY>; + #mbox-cells = <1>; + nordic,tasks = <16>; + nordic,tasks-mask = <0xfffffff0>; + }; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + + cpurad_uicr_ext: memory@e1ff000 { + reg = <0xe1ff000 DT_SIZE_K(2)>; + }; + + cpuapp_uicr_ext: memory@e1ff800 { + reg = <0xe1ff800 DT_SIZE_K(2)>; + }; + }; + + clocks { + fll16m: fll16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + mram1x: mram@e000000 { + compatible = "nordic,mram"; + reg = <0xe000000 DT_SIZE_K(2048)>; + erase-block-size = <4096>; + write-block-size = <16>; + }; + + cpuapp_uicr: uicr@fff8000 { + compatible = "nordic,nrf-uicr-v2"; + reg = <0xfff8000 DT_SIZE_K(2)>; + domain = <2>; + ptr-ext-uicr = <&cpuapp_uicr_ext>; + }; + + cpurad_uicr: uicr@fffa000 { + compatible = "nordic,nrf-uicr-v2"; + reg = <0xfffa000 DT_SIZE_K(2)>; + domain = <3>; + ptr-ext-uicr = <&cpurad_uicr_ext>; + }; + + ficr: ficr@fffe000 { + compatible = "nordic,nrf-ficr"; + reg = <0xfffe000 DT_SIZE_K(2)>; + #nordic,ficr-cells = <1>; + }; + + cpuapp_ram0: sram@22000000 { + compatible = "mmio-sram"; + reg = <0x22000000 DT_SIZE_K(32)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000000 0x8000>; + }; + + cpurad_ram0: sram@23000000 { + compatible = "mmio-sram"; + reg = <0x23000000 DT_SIZE_K(64)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x23000000 0x10000>; + }; + + cpuapp_peripherals: peripheral@52000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x52000000 0x1000000>; + + cpuapp_hsfll: clock@d000 { + compatible = "nordic,nrf-hsfll"; + #clock-cells = <0>; + reg = <0xd000 0x1000>; + clocks = <&fll16m>; + clock-frequency = ; + nordic,ficrs = + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; + nordic,ficr-names = "vsup", "coarse", "fine"; + }; + + cpuapp_ipct: ipct@13000 { + compatible = "nordic,nrf-ipct-local"; + reg = <0x13000 0x1000>; + status = "disabled"; + channels = <4>; + interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, + <65 NRF_DEFAULT_IRQ_PRIORITY>; + }; + }; + + cpurad_peripherals: peripheral@53000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53000000 0x1000000>; + + cpurad_hsfll: clock@d000 { + compatible = "nordic,nrf-hsfll"; + #clock-cells = <0>; + reg = <0xd000 0x1000>; + clocks = <&fll16m>; + clock-frequency = ; + nordic,ficrs = + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; + nordic,ficr-names = "vsup", "coarse", "fine"; + }; + + dppic020: dppic@22000 { + compatible = "nordic,nrf-dppic-local"; + reg = <0x22000 0x1000>; + status = "disabled"; + }; + + cpurad_ipct: ipct@24000 { + compatible = "nordic,nrf-ipct-local"; + reg = <0x24000 0x1000>; + status = "disabled"; + channels = <8>; + interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, + <65 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + egu020: egu@25000 { + compatible = "nordic,nrf-egu"; + reg = <0x25000 0x1000>; + status = "disabled"; + interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + ecb020: ecb@27000 { + compatible = "nordic,nrf-ecb"; + reg = <0x27000 0x1000>; + status = "disabled"; + interrupts = <39 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + timer020: timer@28000 { + compatible = "nordic,nrf-timer"; + reg = <0x28000 0x1000>; + status = "disabled"; + cc-num = <8>; + interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer021: timer@29000 { + compatible = "nordic,nrf-timer"; + reg = <0x29000 0x1000>; + status = "disabled"; + cc-num = <8>; + interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer022: timer@2a000 { + compatible = "nordic,nrf-timer"; + reg = <0x2a000 0x1000>; + status = "disabled"; + cc-num = <8>; + interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + rtc: rtc@2b000 { + compatible = "nordic,nrf-rtc"; + reg = <0x2b000 0x1000>; + status = "disabled"; + cc-num = <4>; + clock-frequency = <32768>; + interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>; + prescaler = <1>; + }; + + radio: radio@2c000 { + compatible = "nordic,nrf-radio"; + reg = <0x2c000 0x1000>; + status = "disabled"; + ble-2mbps-supported; + ble-coded-phy-supported; + dfe-supported; + ieee802154-supported; + interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>; + + cpurad_ieee802154: ieee802154 { + compatible = "nordic,nrf-ieee802154"; + status = "disabled"; + }; + }; + + ecb030: ecb@3b000 { + compatible = "nordic,nrf-ecb"; + reg = <0x3b000 0x1000>; + interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + }; + + global_peripherals: peripheral@5f000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5f000000 0x1000000>; + + cpusec_bellboard: mailbox@99000 { + reg = <0x99000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + cpuapp_bellboard: mailbox@9a000 { + reg = <0x9a000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + cpurad_bellboard: mailbox@9b000 { + reg = <0x9b000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + ipct120: ipct@8d1000 { + compatible = "nordic,nrf-ipct-global"; + reg = <0x8d1000 0x1000>; + status = "disabled"; + channels = <8>; + global-domain-id = <12>; + }; + + dppic120: dppic@8e1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x8e1000 0x1000>; + status = "disabled"; + }; + + timer120: timer@8e2000 { + compatible = "nordic,nrf-timer"; + reg = <0x8e2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer121: timer@8e3000 { + compatible = "nordic,nrf-timer"; + reg = <0x8e3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + uart120: uart@8e5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x8e5000 0x1000>; + status = "disabled"; + interrupts = <229 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + spi120: spi@8e6000 { + compatible = "nordic,nrf-spim"; + reg = <0x8e6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi121: spi@8e7000 { + compatible = "nordic,nrf-spim"; + reg = <0x8e7000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + cpuppr_vpr: vpr@908000 { + compatible = "nordic,nrf-vpr-coprocessor"; + reg = <0x908000 0x1000>; + status = "disabled"; + cpu = <13>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x908000 0x4000>; + + cpuppr_vevif_remote: mailbox@0 { + compatible = "nordic,nrf-vevif-remote"; + reg = <0x0 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + nordic,tasks = <16>; + nordic,tasks-mask = <0xfffffff0>; + }; + + cpuppr_clic: interrupt-controller@1000 { + compatible = "nordic,nrf-clic"; + reg = <0x1000 0x3000>; + status = "disabled"; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + }; + }; + + ipct130: ipct@921000 { + compatible = "nordic,nrf-ipct-global"; + reg = <0x921000 0x1000>; + status = "disabled"; + channels = <8>; + global-domain-id = <13>; + }; + + dppic130: dppic@922000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x922000 0x1000>; + status = "disabled"; + }; + + rtc130: rtc@928000 { + compatible = "nordic,nrf-rtc"; + reg = <0x928000 0x1000>; + status = "disabled"; + cc-num = <4>; + clock-frequency = <32768>; + interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>; + prescaler = <1>; + }; + + rtc131: rtc@929000 { + compatible = "nordic,nrf-rtc"; + reg = <0x929000 0x1000>; + status = "disabled"; + cc-num = <4>; + clock-frequency = <32768>; + interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>; + prescaler = <1>; + }; + + wdt131: watchdog@92b000 { + compatible = "nordic,nrf-wdt"; + reg = <0x92b000 0x1000>; + status = "disabled"; + interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + wdt132: watchdog@92c000 { + compatible = "nordic,nrf-wdt"; + reg = <0x92c000 0x1000>; + status = "disabled"; + interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + gpiote130: gpiote@934000 { + compatible = "nordic,nrf-gpiote"; + reg = <0x934000 0x1000>; + status = "disabled"; + instance = <130>; + }; + + gpio0: gpio@938000 { + compatible = "nordic,nrf-gpio"; + reg = <0x938000 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <12>; + port = <0>; + }; + + gpio1: gpio@938200 { + compatible = "nordic,nrf-gpio"; + reg = <0x938200 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <12>; + port = <1>; + }; + + gpio2: gpio@938400 { + compatible = "nordic,nrf-gpio"; + reg = <0x938400 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <12>; + port = <2>; + }; + + gpio6: gpio@938c00 { + compatible = "nordic,nrf-gpio"; + reg = <0x938c00 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + ngpios = <14>; + port = <6>; + }; + + gpio7: gpio@938e00 { + compatible = "nordic,nrf-gpio"; + reg = <0x938e00 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + port = <7>; + }; + + gpio9: gpio@939200 { + compatible = "nordic,nrf-gpio"; + reg = <0x939200 0x200>; + status = "disabled"; + #gpio-cells = <2>; + gpio-controller; + gpiote-instance = <&gpiote130>; + ngpios = <6>; + port = <9>; + }; + + dppic131: dppic@981000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x981000 0x1000>; + status = "disabled"; + }; + + comp: comparator@983000 { + compatible = "nordic,nrf-comp"; + reg = <0x983000 0x1000>; + status = "disabled"; + interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>; + #io-channel-cells = <1>; + }; + + temp: temperature-sensor@984000 { + compatible = "nordic,nrf-temp"; + reg = <0x984000 0x1000>; + interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + nfct: nfct@985000 { + compatible = "nordic,nrf-nfct"; + reg = <0x985000 0x1000>; + status = "disabled"; + interrupts = <389 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + dppic132: dppic@991000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x991000 0x1000>; + status = "disabled"; + }; + + qdec130: qdec@994000 { + compatible = "nordic,nrf-qdec"; + reg = <0x994000 0x1000>; + status = "disabled"; + interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + qdec131: qdec@995000 { + compatible = "nordic,nrf-qdec"; + reg = <0x995000 0x1000>; + status = "disabled"; + interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + grtc: grtc@99c000 { + compatible = "nordic,nrf-grtc"; + reg = <0x99c000 0x1000>; + status = "disabled"; + cc-num = <16>; + }; + + dppic133: dppic@9a1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9a1000 0x1000>; + status = "disabled"; + }; + + timer130: timer@9a2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9a2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer131: timer@9a3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9a3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + i2c130: i2c@9a5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9a5000 0x1000>; + status = "disabled"; + interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi130: spi@9a5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9a5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart130: uart@9a5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9a5000 0x1000>; + status = "disabled"; + interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + i2c131: i2c@9a6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9a6000 0x1000>; + status = "disabled"; + interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi131: spi@9a6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9a6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart131: uart@9a6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9a6000 0x1000>; + status = "disabled"; + interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + dppic134: dppic@9b1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9b1000 0x1000>; + status = "disabled"; + }; + + timer132: timer@9b2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9b2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer133: timer@9b3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9b3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + i2c132: i2c@9b5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9b5000 0x1000>; + status = "disabled"; + interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi132: spi@9b5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9b5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart132: uart@9b5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9b5000 0x1000>; + status = "disabled"; + interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + i2c133: i2c@9b6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9b6000 0x1000>; + status = "disabled"; + interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi133: spi@9b6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9b6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart133: uart@9b6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9b6000 0x1000>; + status = "disabled"; + interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + dppic135: dppic@9c1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9c1000 0x1000>; + status = "disabled"; + }; + + timer134: timer@9c2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9c2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer135: timer@9c3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9c3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + i2c134: i2c@9c5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9c5000 0x1000>; + status = "disabled"; + interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi134: spi@9c5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9c5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart134: uart@9c5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9c5000 0x1000>; + status = "disabled"; + interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + i2c135: i2c@9c6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9c6000 0x1000>; + status = "disabled"; + interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi135: spi@9c6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9c6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart135: uart@9c6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9c6000 0x1000>; + status = "disabled"; + interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + dppic136: dppic@9d1000 { + compatible = "nordic,nrf-dppic-global"; + reg = <0x9d1000 0x1000>; + status = "disabled"; + }; + + timer136: timer@9d2000 { + compatible = "nordic,nrf-timer"; + reg = <0x9d2000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + timer137: timer@9d3000 { + compatible = "nordic,nrf-timer"; + reg = <0x9d3000 0x1000>; + status = "disabled"; + cc-num = <6>; + interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>; + max-bit-width = <32>; + prescaler = <0>; + }; + + i2c136: i2c@9d5000 { + compatible = "nordic,nrf-twim"; + reg = <0x9d5000 0x1000>; + status = "disabled"; + interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi136: spi@9d5000 { + compatible = "nordic,nrf-spim"; + reg = <0x9d5000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart136: uart@9d5000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9d5000 0x1000>; + status = "disabled"; + interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; + }; + + i2c137: i2c@9d6000 { + compatible = "nordic,nrf-twim"; + reg = <0x9d6000 0x1000>; + status = "disabled"; + interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi137: spi@9d6000 { + compatible = "nordic,nrf-spim"; + reg = <0x9d6000 0x1000>; + status = "disabled"; + easydma-maxcnt-bits = <15>; + interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart137: uart@9d6000 { + compatible = "nordic,nrf-uarte"; + reg = <0x9d6000 0x1000>; + status = "disabled"; + interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; + }; + }; + }; + + cpuapp_ppb: cpuapp-ppb-bus { + #address-cells = <1>; + #size-cells = <1>; + + cpuapp_systick: timer@e000e010 { + compatible = "arm,armv8m-systick"; + reg = <0xe000e010 0x10>; + status = "disabled"; + }; + + cpuapp_nvic: interrupt-controller@e000e100 { + compatible = "arm,v8m-nvic"; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <3>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + }; + }; + + cpurad_ppb: cpurad-ppb-bus { + #address-cells = <1>; + #size-cells = <1>; + + cpurad_systick: timer@e000e010 { + compatible = "arm,armv8m-systick"; + reg = <0xe000e010 0x10>; + status = "disabled"; + }; + + cpurad_nvic: interrupt-controller@e000e100 { + compatible = "arm,v8m-nvic"; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <3>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + }; + }; +}; diff --git a/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi b/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi new file mode 100644 index 00000000000..0af6618688f --- /dev/null +++ b/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +cpu: &cpuppr {}; +clic: &cpuppr_clic {}; +cpuppr_vevif: &cpuppr_vevif_local {}; + +/delete-node/ &cpuapp; +/delete-node/ &cpuapp_peripherals; +/delete-node/ &cpuapp_ppb; +/delete-node/ &cpuapp_ram0; +/delete-node/ &cpurad; +/delete-node/ &cpurad_peripherals; +/delete-node/ &cpurad_ppb; +/delete-node/ &cpurad_ram0; + +/ { + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpuppr_clic>; + ranges; + }; +}; + +&cpusec_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&cpurad_bellboard { + compatible = "nordic,nrf-bellboard-remote"; +}; + +&gpiote130 { + interrupts = <104 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&grtc { + interrupts = <108 NRF_DEFAULT_IRQ_PRIORITY>; +}; diff --git a/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20-enga.h b/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20-enga.h new file mode 100644 index 00000000000..60b788a3516 --- /dev/null +++ b/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20-enga.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +/* autogenerated using Nordic HAL utils/gen_offsets.py script */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_ENGA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_ENGA_H_ + +#define NRF_FICR_BLE_ADDRTYPE 0x00CU +#define NRF_FICR_BLE_ADDR_0 0x010U +#define NRF_FICR_BLE_ADDR_1 0x014U +#define NRF_FICR_BLE_ER_0 0x018U +#define NRF_FICR_BLE_ER_1 0x01CU +#define NRF_FICR_BLE_ER_2 0x020U +#define NRF_FICR_BLE_ER_3 0x024U +#define NRF_FICR_BLE_IR_0 0x028U +#define NRF_FICR_BLE_IR_1 0x02CU +#define NRF_FICR_BLE_IR_2 0x030U +#define NRF_FICR_BLE_IR_3 0x034U +#define NRF_FICR_NFC_TAGHEADER_0 0x040U +#define NRF_FICR_NFC_TAGHEADER_1 0x044U +#define NRF_FICR_NFC_TAGHEADER_2 0x048U +#define NRF_FICR_NFC_TAGHEADER_3 0x04CU +#define NRF_FICR_INFO_CONFIGID 0x050U +#define NRF_FICR_INFO_PART 0x054U +#define NRF_FICR_INFO_VARIANT 0x058U +#define NRF_FICR_INFO_PACKAGE 0x05CU +#define NRF_FICR_INFO_RAM 0x060U +#define NRF_FICR_INFO_MRAM 0x064U +#define NRF_FICR_INFO_CODEPAGESIZE 0x068U +#define NRF_FICR_INFO_CODESIZE 0x06CU +#define NRF_FICR_INFO_DEVICETYPE 0x070U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALVREF 0x384U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_0 0x388U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_1 0x38CU +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_2 0x390U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALOFFSET 0x394U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_0 0x398U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_1 0x39CU +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_2 0x3A0U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_3 0x3A4U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_4 0x3A8U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_5 0x3ACU +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALIREF 0x3B0U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALVREFTC 0x3B4U +#define NRF_FICR_TRIM_GLOBAL_NFCT_BIASCFG 0x3BCU +#define NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE 0x3C0U +#define NRF_FICR_TRIM_GLOBAL_COMP_REFTRIM 0x3D0U +#define NRF_FICR_TRIM_GLOBAL_COMP_RCALTRIM 0x3D4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP 0x3D8U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0 0x3DCU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_1 0x3E0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_2 0x3E4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_3 0x3E8U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_4 0x3ECU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_5 0x3F0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0 0x3F4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_1 0x3F8U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_2 0x3FCU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_3 0x400U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_4 0x404U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_5 0x408U +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_0_TRIM 0x40CU +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_1_TRIM 0x410U +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_2_TRIM 0x414U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP 0x418U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_0 0x41CU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1 0x420U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_2 0x424U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_3 0x428U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_4 0x42CU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_5 0x430U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_0 0x434U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1 0x438U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_2 0x43CU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_3 0x440U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_4 0x444U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_5 0x448U +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_0_TRIM 0x44CU +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_1_TRIM 0x450U +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_2_TRIM 0x454U +#define NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL0 0x458U +#define NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL1 0x45CU +#define NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL2 0x460U +#define NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_RXCTRL 0x464U +#define NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_OVRRXTRIMCODE 0x468U +#define NRF_FICR_TRIM_RADIOCORE_RADIO_RXAGC_CALIBRATION 0x46CU +#define NRF_FICR_TRIM_RADIOCORE_RADIO_PVTTOT 0x470U +#define NRF_FICR_TRIM_RADIOCORE_RADIO_KDTC 0x474U +#define NRF_FICR_TRIM_RADIOCORE_RADIO_TXHFGAIN 0x478U +#define NRF_FICR_TRIM_RADIOCORE_RADIO_PVTTOFIX 0x47CU +#define NRF_FICR_TRIM_RADIOCORE_RADIO_LOOPGAIN 0x480U + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_ENGA_H_ */ From f09da2659ea67073ccbda5ec6872ba033c071f48 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:25 +0200 Subject: [PATCH 2248/2402] Revert "[nrf fromtree] modules: hal_nordic: Remove support for nRF54H20 EngA" This reverts commit 26aa38e4115b5f87aabc242cd1590ccdfa782564. Signed-off-by: Gerard Marull-Paretas --- modules/hal_nordic/nrfx/CMakeLists.txt | 10 + modules/hal_nordic/nrfx/nrfx_config.h | 6 + .../nrfx_config_nrf54h20_enga_application.h | 1962 ++++++++++++++++ .../nrfx/nrfx_config_nrf54h20_enga_ppr.h | 1882 +++++++++++++++ .../nrfx_config_nrf54h20_enga_radiocore.h | 2043 +++++++++++++++++ 5 files changed, 5903 insertions(+) create mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h create mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h create mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index adce870fc3a..eb384046aa6 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -47,6 +47,13 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_ENGA_CPUAPP NRF_APPLICATION zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9120 NRF9120_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9160 NRF9160_XXAA) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUAPP NRF54H20_ENGA_XXAA + NRF_APPLICATION) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPURAD NRF54H20_ENGA_XXAA + NRF_RADIOCORE) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUPPR NRF54H20_ENGA_XXAA + NRF_PPR) + zephyr_compile_definitions_ifdef(CONFIG_NRF_APPROTECT_LOCK ENABLE_APPROTECT) zephyr_compile_definitions_ifdef(CONFIG_NRF_APPROTECT_USER_HANDLING @@ -203,5 +210,8 @@ mdk_svd_ifdef(CONFIG_SOC_NRF5340_CPUNET nrf5340_network.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUAPP nrf54h20_application.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUPPR nrf54h20_ppr.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPURAD nrf54h20_radiocore.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUAPP nrf54h20_enga_application.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUPPR nrf54h20_enga_ppr.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPURAD nrf54h20_enga_radiocore.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9120 nrf9120.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9160 nrf9160.svd) diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index c4798d1906a..d0f2a0555d5 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -943,6 +943,12 @@ #include #elif defined(NRF54H20_XXAA) && defined(NRF_PPR) #include +#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_APPLICATION) + #include +#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_RADIOCORE) + #include +#elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_PPR) + #include #elif (defined(NRF54L15_XXAA) || defined(NRF54L15_ENGA_XXAA)) && defined(NRF_APPLICATION) #include #elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h new file mode 100644 index 00000000000..af74d9d3dc3 --- /dev/null +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h @@ -0,0 +1,1962 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NRFX_CONFIG_NRF54H20_ENGA_APPLICATION_H__ +#define NRFX_CONFIG_NRF54H20_ENGA_APPLICATION_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + + +/** + * @brief NRFX_DEFAULT_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_DEFAULT_IRQ_PRIORITY +#define NRFX_DEFAULT_IRQ_PRIORITY 7 +#endif + +/** + * @brief NRFX_BELLBOARD_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD_ENABLED +#define NRFX_BELLBOARD_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_BELLBOARD0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD0_ENABLED +#define NRFX_BELLBOARD0_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD1_ENABLED +#define NRFX_BELLBOARD1_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD2_ENABLED +#define NRFX_BELLBOARD2_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD3_ENABLED +#define NRFX_BELLBOARD3_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED +#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL +#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0 +#endif + +/** + * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e +#endif + +/** + * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 +#endif + +/** + * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 +#endif + +/** + * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 +#endif + +/** + * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f +#endif + +/** + * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 +#endif + +/** + * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df +#endif + +/** + * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf +#endif + +/** + * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e +#endif + +/** + * @brief NRFX_GPIOTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS + * + * Integer value. Minimum: 0. Maximum: 15. + */ +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_GPIOTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE130_ENABLED +#define NRFX_GPIOTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_ENABLED +#define NRFX_GRTC_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS + * + * Integer value. + */ +#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS +#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK + */ +#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK +#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000f0 +#endif + +/** + * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED +#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL +#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_ENABLED +#define NRFX_I2S_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S130_ENABLED +#define NRFX_I2S130_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S131_ENABLED +#define NRFX_I2S131_ENABLED 0 +#endif + +/** + * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_LPCOMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_MVDMA_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA_ENABLED +#define NRFX_MVDMA_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_ENABLED +#define NRFX_NFCT_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver. + * + * Integer value. Minimum: 0. Maximum: 5. + */ +#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID +#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED +#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL +#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PDM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_BOX_0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_3_ENABLED +#define NRFX_PRS_BOX_3_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_4_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_4_ENABLED +#define NRFX_PRS_BOX_4_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_5_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_5_ENABLED +#define NRFX_PRS_BOX_5_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_6_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_6_ENABLED +#define NRFX_PRS_BOX_6_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_7_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_7_ENABLED +#define NRFX_PRS_BOX_7_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_8_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_8_ENABLED +#define NRFX_PRS_BOX_8_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_9_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_9_ENABLED +#define NRFX_PRS_BOX_9_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PWM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM120_ENABLED +#define NRFX_PWM120_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM130_ENABLED +#define NRFX_PWM130_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM131_ENABLED +#define NRFX_PWM131_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM132_ENABLED +#define NRFX_PWM132_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM133_ENABLED +#define NRFX_PWM133_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_QDEC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC130_ENABLED +#define NRFX_QDEC130_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC131_ENABLED +#define NRFX_QDEC131_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_RTC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC130_ENABLED +#define NRFX_RTC130_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC131_ENABLED +#define NRFX_RTC131_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM120_ENABLED +#define NRFX_SPIM120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM121_ENABLED +#define NRFX_SPIM121_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM130_ENABLED +#define NRFX_SPIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM131_ENABLED +#define NRFX_SPIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM132_ENABLED +#define NRFX_SPIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM133_ENABLED +#define NRFX_SPIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM134_ENABLED +#define NRFX_SPIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM135_ENABLED +#define NRFX_SPIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM136_ENABLED +#define NRFX_SPIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM137_ENABLED +#define NRFX_SPIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIS120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS120_ENABLED +#define NRFX_SPIS120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS130_ENABLED +#define NRFX_SPIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS131_ENABLED +#define NRFX_SPIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS132_ENABLED +#define NRFX_SPIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS133_ENABLED +#define NRFX_SPIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS134_ENABLED +#define NRFX_SPIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS135_ENABLED +#define NRFX_SPIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS136_ENABLED +#define NRFX_SPIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS137_ENABLED +#define NRFX_SPIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_SYSTICK_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_ENABLED +#define NRFX_TEMP_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED +#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL +#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER120_ENABLED +#define NRFX_TIMER120_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER121_ENABLED +#define NRFX_TIMER121_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER130_ENABLED +#define NRFX_TIMER130_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER131_ENABLED +#define NRFX_TIMER131_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER132_ENABLED +#define NRFX_TIMER132_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER133_ENABLED +#define NRFX_TIMER133_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER134_ENABLED +#define NRFX_TIMER134_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER135_ENABLED +#define NRFX_TIMER135_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER136_ENABLED +#define NRFX_TIMER136_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER137_ENABLED +#define NRFX_TIMER137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM130_ENABLED +#define NRFX_TWIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM131_ENABLED +#define NRFX_TWIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM132_ENABLED +#define NRFX_TWIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM133_ENABLED +#define NRFX_TWIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM134_ENABLED +#define NRFX_TWIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM135_ENABLED +#define NRFX_TWIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM136_ENABLED +#define NRFX_TWIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM137_ENABLED +#define NRFX_TWIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance + * would be initialized only once. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +/** + * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS130_ENABLED +#define NRFX_TWIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS131_ENABLED +#define NRFX_TWIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS132_ENABLED +#define NRFX_TWIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS133_ENABLED +#define NRFX_TWIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS134_ENABLED +#define NRFX_TWIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS135_ENABLED +#define NRFX_TWIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS136_ENABLED +#define NRFX_TWIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS137_ENABLED +#define NRFX_TWIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for + * configuring GPIO pins is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for + * configuring PSEL registers is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking + * of TX transfers. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_TX_LINK +#define NRFX_UARTE_CONFIG_TX_LINK 1 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED +#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 +#endif + +/** + * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_UARTE120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE120_ENABLED +#define NRFX_UARTE120_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE130_ENABLED +#define NRFX_UARTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE131_ENABLED +#define NRFX_UARTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE132_ENABLED +#define NRFX_UARTE132_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE133_ENABLED +#define NRFX_UARTE133_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE134_ENABLED +#define NRFX_UARTE134_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE135_ENABLED +#define NRFX_UARTE135_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE136_ENABLED +#define NRFX_UARTE136_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE137_ENABLED +#define NRFX_UARTE137_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_WDT010_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT010_ENABLED +#define NRFX_WDT010_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT011_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT011_ENABLED +#define NRFX_WDT011_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT131_ENABLED +#define NRFX_WDT131_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT132_ENABLED +#define NRFX_WDT132_ENABLED 0 +#endif + +#endif /* NRFX_CONFIG_NRF54H20_ENGA_APPLICATION_H__ */ diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h new file mode 100644 index 00000000000..65b3e2fa958 --- /dev/null +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h @@ -0,0 +1,1882 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NRFX_CONFIG_NRF54H20_ENGA_PPR_H__ +#define NRFX_CONFIG_NRF54H20_ENGA_PPR_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + + +/** + * @brief NRFX_DEFAULT_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_DEFAULT_IRQ_PRIORITY +#define NRFX_DEFAULT_IRQ_PRIORITY 0 +#endif + +/** + * @brief NRFX_COMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED +#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL +#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030 +#endif + +/** + * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e +#endif + +/** + * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 +#endif + +/** + * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 +#endif + +/** + * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 +#endif + +/** + * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 +#endif + +/** + * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df +#endif + +/** + * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf +#endif + +/** + * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e +#endif + +/** + * @brief NRFX_GPIOTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS + * + * Integer value. Minimum: 0. Maximum: 15. + */ +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_GPIOTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE130_ENABLED +#define NRFX_GPIOTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_ENABLED +#define NRFX_GRTC_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS + * + * Integer value. + */ +#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS +#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 2 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK + */ +#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK +#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000c0 +#endif + +/** + * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED +#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL +#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_ENABLED +#define NRFX_I2S_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S130_ENABLED +#define NRFX_I2S130_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S131_ENABLED +#define NRFX_I2S131_ENABLED 0 +#endif + +/** + * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_LPCOMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_NFCT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_ENABLED +#define NRFX_NFCT_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for + * workarounds in the driver. + * + * Integer value. Minimum: 0. Maximum: 5. + */ +#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID +#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED +#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL +#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PDM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_BOX_0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_3_ENABLED +#define NRFX_PRS_BOX_3_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_4_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_4_ENABLED +#define NRFX_PRS_BOX_4_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_5_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_5_ENABLED +#define NRFX_PRS_BOX_5_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_6_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_6_ENABLED +#define NRFX_PRS_BOX_6_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_7_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_7_ENABLED +#define NRFX_PRS_BOX_7_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_8_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_8_ENABLED +#define NRFX_PRS_BOX_8_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_9_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_9_ENABLED +#define NRFX_PRS_BOX_9_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PWM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM120_ENABLED +#define NRFX_PWM120_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM130_ENABLED +#define NRFX_PWM130_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM131_ENABLED +#define NRFX_PWM131_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM132_ENABLED +#define NRFX_PWM132_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM133_ENABLED +#define NRFX_PWM133_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_QDEC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC130_ENABLED +#define NRFX_QDEC130_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC131_ENABLED +#define NRFX_QDEC131_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_RTC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC130_ENABLED +#define NRFX_RTC130_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC131_ENABLED +#define NRFX_RTC131_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM120_ENABLED +#define NRFX_SPIM120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM121_ENABLED +#define NRFX_SPIM121_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM130_ENABLED +#define NRFX_SPIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM131_ENABLED +#define NRFX_SPIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM132_ENABLED +#define NRFX_SPIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM133_ENABLED +#define NRFX_SPIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM134_ENABLED +#define NRFX_SPIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM135_ENABLED +#define NRFX_SPIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM136_ENABLED +#define NRFX_SPIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM137_ENABLED +#define NRFX_SPIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIS120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS120_ENABLED +#define NRFX_SPIS120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS130_ENABLED +#define NRFX_SPIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS131_ENABLED +#define NRFX_SPIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS132_ENABLED +#define NRFX_SPIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS133_ENABLED +#define NRFX_SPIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS134_ENABLED +#define NRFX_SPIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS135_ENABLED +#define NRFX_SPIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS136_ENABLED +#define NRFX_SPIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS137_ENABLED +#define NRFX_SPIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_ENABLED +#define NRFX_TEMP_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED +#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL +#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER120_ENABLED +#define NRFX_TIMER120_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER121_ENABLED +#define NRFX_TIMER121_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER130_ENABLED +#define NRFX_TIMER130_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER131_ENABLED +#define NRFX_TIMER131_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER132_ENABLED +#define NRFX_TIMER132_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER133_ENABLED +#define NRFX_TIMER133_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER134_ENABLED +#define NRFX_TIMER134_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER135_ENABLED +#define NRFX_TIMER135_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER136_ENABLED +#define NRFX_TIMER136_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER137_ENABLED +#define NRFX_TIMER137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM130_ENABLED +#define NRFX_TWIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM131_ENABLED +#define NRFX_TWIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM132_ENABLED +#define NRFX_TWIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM133_ENABLED +#define NRFX_TWIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM134_ENABLED +#define NRFX_TWIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM135_ENABLED +#define NRFX_TWIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM136_ENABLED +#define NRFX_TWIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM137_ENABLED +#define NRFX_TWIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance + * would be initialized only once. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +/** + * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS130_ENABLED +#define NRFX_TWIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS131_ENABLED +#define NRFX_TWIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS132_ENABLED +#define NRFX_TWIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS133_ENABLED +#define NRFX_TWIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS134_ENABLED +#define NRFX_TWIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS135_ENABLED +#define NRFX_TWIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS136_ENABLED +#define NRFX_TWIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS137_ENABLED +#define NRFX_TWIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for + * configuring GPIO pins is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for + * configuring PSEL registers is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking of TX + * transfers. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_TX_LINK +#define NRFX_UARTE_CONFIG_TX_LINK 1 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED +#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 +#endif + +/** + * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_UARTE120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE120_ENABLED +#define NRFX_UARTE120_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE130_ENABLED +#define NRFX_UARTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE131_ENABLED +#define NRFX_UARTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE132_ENABLED +#define NRFX_UARTE132_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE133_ENABLED +#define NRFX_UARTE133_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE134_ENABLED +#define NRFX_UARTE134_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE135_ENABLED +#define NRFX_UARTE135_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE136_ENABLED +#define NRFX_UARTE136_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE137_ENABLED +#define NRFX_UARTE137_ENABLED 0 +#endif + +/** + * @brief NRFX_VEVIF_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_VEVIF_ENABLED +#define NRFX_VEVIF_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_WDT131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT131_ENABLED +#define NRFX_WDT131_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT132_ENABLED +#define NRFX_WDT132_ENABLED 0 +#endif + +#endif /* NRFX_CONFIG_NRF54H20_ENGA_PPR_H__ */ diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h new file mode 100644 index 00000000000..ca7bf3aca63 --- /dev/null +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h @@ -0,0 +1,2043 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef NRFX_CONFIG_NRF54H20_ENGA_RADIOCORE_H__ +#define NRFX_CONFIG_NRF54H20_ENGA_RADIOCORE_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + +/** + * @brief NRFX_DEFAULT_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_DEFAULT_IRQ_PRIORITY +#define NRFX_DEFAULT_IRQ_PRIORITY 7 +#endif + +/** + * @brief NRFX_BELLBOARD_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD_ENABLED +#define NRFX_BELLBOARD_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_BELLBOARD0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD0_ENABLED +#define NRFX_BELLBOARD0_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD1_ENABLED +#define NRFX_BELLBOARD1_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD2_ENABLED +#define NRFX_BELLBOARD2_ENABLED 0 +#endif + +/** + * @brief NRFX_BELLBOARD3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_BELLBOARD3_ENABLED +#define NRFX_BELLBOARD3_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_COMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_ENABLED +#define NRFX_DPPI_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED +#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_DPPI_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL +#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0 +#endif + +/** + * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e +#endif + +/** + * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 +#endif + +/** + * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 +#endif + +/** + * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 +#endif + +/** + * @brief NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f +#endif + +/** + * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff +#endif + +/** + * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 +#endif + +/** + * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df +#endif + +/** + * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf +#endif + +/** + * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e +#endif + +/** + * @brief NRFX_EGU_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +/** + * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_EGU020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_EGU020_ENABLED +#define NRFX_EGU020_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS + * + * Integer value. Minimum: 0. Maximum: 15. + */ +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS +#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_GPIOTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GPIOTE130_ENABLED +#define NRFX_GPIOTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_ENABLED +#define NRFX_GRTC_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED +#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOEN + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOEN +#define NRFX_GRTC_CONFIG_AUTOEN 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_AUTOSTART + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_AUTOSTART +#define NRFX_GRTC_CONFIG_AUTOSTART 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS + * + * Integer value. + */ +#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS +#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK + */ +#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK +#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f00 +#endif + +/** + * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED +#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_GRTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL +#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_ENABLED +#define NRFX_I2S_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_I2S130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S130_ENABLED +#define NRFX_I2S130_ENABLED 0 +#endif + +/** + * @brief NRFX_I2S131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_I2S131_ENABLED +#define NRFX_I2S131_ENABLED 0 +#endif + +/** + * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030 +#endif + +/** + * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c +#endif + +/** + * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000c0 +#endif + +/** + * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 +#endif + +/** + * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK + */ +#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK +#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 +#endif + +/** + * @brief NRFX_LPCOMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_MVDMA_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_MVDMA_ENABLED +#define NRFX_MVDMA_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_ENABLED +#define NRFX_NFCT_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver. + * + * Integer value. Minimum: 0. Maximum: 5. + */ +#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID +#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED +#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_NFCT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL +#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PDM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PDM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_BOX_0_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_1_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_2_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_3_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_3_ENABLED +#define NRFX_PRS_BOX_3_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_4_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_4_ENABLED +#define NRFX_PRS_BOX_4_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_5_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_5_ENABLED +#define NRFX_PRS_BOX_5_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_6_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_6_ENABLED +#define NRFX_PRS_BOX_6_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_7_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_7_ENABLED +#define NRFX_PRS_BOX_7_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_8_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_8_ENABLED +#define NRFX_PRS_BOX_8_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_9_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PRS_BOX_9_ENABLED +#define NRFX_PRS_BOX_9_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PWM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM120_ENABLED +#define NRFX_PWM120_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM130_ENABLED +#define NRFX_PWM130_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM131_ENABLED +#define NRFX_PWM131_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM132_ENABLED +#define NRFX_PWM132_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM133_ENABLED +#define NRFX_PWM133_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_QDEC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC130_ENABLED +#define NRFX_QDEC130_ENABLED 0 +#endif + +/** + * @brief NRFX_QDEC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_QDEC131_ENABLED +#define NRFX_QDEC131_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_RTC130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC130_ENABLED +#define NRFX_RTC130_ENABLED 0 +#endif + +/** + * @brief NRFX_RTC131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RTC131_ENABLED +#define NRFX_RTC131_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SAADC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIM120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM120_ENABLED +#define NRFX_SPIM120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM121_ENABLED +#define NRFX_SPIM121_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM130_ENABLED +#define NRFX_SPIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM131_ENABLED +#define NRFX_SPIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM132_ENABLED +#define NRFX_SPIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM133_ENABLED +#define NRFX_SPIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM134_ENABLED +#define NRFX_SPIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM135_ENABLED +#define NRFX_SPIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM136_ENABLED +#define NRFX_SPIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIM137_ENABLED +#define NRFX_SPIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_SPIS120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS120_ENABLED +#define NRFX_SPIS120_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS130_ENABLED +#define NRFX_SPIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS131_ENABLED +#define NRFX_SPIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS132_ENABLED +#define NRFX_SPIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS133_ENABLED +#define NRFX_SPIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS134_ENABLED +#define NRFX_SPIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS135_ENABLED +#define NRFX_SPIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS136_ENABLED +#define NRFX_SPIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_SPIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SPIS137_ENABLED +#define NRFX_SPIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_SYSTICK_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_ENABLED +#define NRFX_TEMP_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED +#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TEMP_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL +#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TIMER020_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER020_ENABLED +#define NRFX_TIMER020_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER021_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER021_ENABLED +#define NRFX_TIMER021_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER022_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER022_ENABLED +#define NRFX_TIMER022_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER120_ENABLED +#define NRFX_TIMER120_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER121_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER121_ENABLED +#define NRFX_TIMER121_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER130_ENABLED +#define NRFX_TIMER130_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER131_ENABLED +#define NRFX_TIMER131_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER132_ENABLED +#define NRFX_TIMER132_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER133_ENABLED +#define NRFX_TIMER133_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER134_ENABLED +#define NRFX_TIMER134_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER135_ENABLED +#define NRFX_TIMER135_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER136_ENABLED +#define NRFX_TIMER136_ENABLED 0 +#endif + +/** + * @brief NRFX_TIMER137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TIMER137_ENABLED +#define NRFX_TIMER137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIM130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM130_ENABLED +#define NRFX_TWIM130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM131_ENABLED +#define NRFX_TWIM131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM132_ENABLED +#define NRFX_TWIM132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM133_ENABLED +#define NRFX_TWIM133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM134_ENABLED +#define NRFX_TWIM134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM135_ENABLED +#define NRFX_TWIM135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM136_ENABLED +#define NRFX_TWIM136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIM137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIM137_ENABLED +#define NRFX_TWIM137_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance + * would be initialized only once. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +/** + * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +/** + * @brief NRFX_TWIS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_TWIS130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS130_ENABLED +#define NRFX_TWIS130_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS131_ENABLED +#define NRFX_TWIS131_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS132_ENABLED +#define NRFX_TWIS132_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS133_ENABLED +#define NRFX_TWIS133_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS134_ENABLED +#define NRFX_TWIS134_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS135_ENABLED +#define NRFX_TWIS135_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS136_ENABLED +#define NRFX_TWIS136_ENABLED 0 +#endif + +/** + * @brief NRFX_TWIS137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_TWIS137_ENABLED +#define NRFX_TWIS137_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for + * configuring GPIO pins is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for + * configuring PSEL registers is removed from the driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG +#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking + * of TX transfers. + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_TX_LINK +#define NRFX_UARTE_CONFIG_TX_LINK 1 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED +#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 +#endif + +/** + * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_UARTE120_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE120_ENABLED +#define NRFX_UARTE120_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE130_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE130_ENABLED +#define NRFX_UARTE130_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE131_ENABLED +#define NRFX_UARTE131_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE132_ENABLED +#define NRFX_UARTE132_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE133_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE133_ENABLED +#define NRFX_UARTE133_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE134_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE134_ENABLED +#define NRFX_UARTE134_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE135_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE135_ENABLED +#define NRFX_UARTE135_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE136_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE136_ENABLED +#define NRFX_UARTE136_ENABLED 0 +#endif + +/** + * @brief NRFX_UARTE137_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_UARTE137_ENABLED +#define NRFX_UARTE137_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_WDT010_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT010_ENABLED +#define NRFX_WDT010_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT011_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT011_ENABLED +#define NRFX_WDT011_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT131_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT131_ENABLED +#define NRFX_WDT131_ENABLED 0 +#endif + +/** + * @brief NRFX_WDT132_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_WDT132_ENABLED +#define NRFX_WDT132_ENABLED 0 +#endif + +#endif /* NRFX_CONFIG_NRF54H20_ENGA_RADIOCORE_H__ */ From 22ccbb8300c125d1db9a43bcce125475d68ffa42 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:25 +0200 Subject: [PATCH 2249/2402] Revert "[nrf fromlist] boards: nordic: Remove definition of nRF54H20 PDK" This reverts commit 1fcc5e329b6eb9dbe2f068139747c805186dba63. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board | 10 + .../nrf54h20pdk_nrf54h20/Kconfig.defconfig | 14 ++ boards/arm/nrf54h20pdk_nrf54h20/board.cmake | 3 + .../doc/img/nrf54h20pdk_nrf54h20.webp | Bin 0 -> 27232 bytes boards/arm/nrf54h20pdk_nrf54h20/doc/index.rst | 153 +++++++++++++++ .../nrf54h20pdk_nrf54h20-ipc_conf.dtsi | 36 ++++ .../nrf54h20pdk_nrf54h20-memory_map.dtsi | 177 ++++++++++++++++++ .../nrf54h20pdk_nrf54h20-pinctrl.dtsi | 53 ++++++ .../nrf54h20pdk_nrf54h20_cpuapp.dts | 171 +++++++++++++++++ .../nrf54h20pdk_nrf54h20_cpuapp.yaml | 15 ++ .../nrf54h20pdk_nrf54h20_cpuapp_defconfig | 33 ++++ .../nrf54h20pdk_nrf54h20_cpurad.dts | 84 +++++++++ .../nrf54h20pdk_nrf54h20_cpurad.yaml | 15 ++ .../nrf54h20pdk_nrf54h20_cpurad_defconfig | 30 +++ .../riscv/nrf54h20pdk_nrf54h20/Kconfig.board | 6 + .../nrf54h20pdk_nrf54h20/Kconfig.defconfig | 6 + boards/riscv/nrf54h20pdk_nrf54h20/board.cmake | 3 + .../nrf54h20pdk_nrf54h20_cpuppr.dts | 56 ++++++ .../nrf54h20pdk_nrf54h20_cpuppr.yaml | 13 ++ .../nrf54h20pdk_nrf54h20_cpuppr_defconfig | 14 ++ .../nrf54h20pdk_nrf54h20/pre_dt_board.cmake | 7 + 21 files changed, 899 insertions(+) create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/board.cmake create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/doc/img/nrf54h20pdk_nrf54h20.webp create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/doc/index.rst create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-ipc_conf.dtsi create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-pinctrl.dtsi create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.yaml create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp_defconfig create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.yaml create mode 100644 boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad_defconfig create mode 100644 boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.board create mode 100644 boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.defconfig create mode 100644 boards/riscv/nrf54h20pdk_nrf54h20/board.cmake create mode 100644 boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts create mode 100644 boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.yaml create mode 100644 boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr_defconfig create mode 100644 boards/riscv/nrf54h20pdk_nrf54h20/pre_dt_board.cmake diff --git a/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board b/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board new file mode 100644 index 00000000000..b76cfce6800 --- /dev/null +++ b/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54H20PDK_NRF54H20_CPUAPP + bool "nRF54H20 PDK nRF54H20 Application MCU" + depends on SOC_NRF54H20_ENGA_CPUAPP + +config BOARD_NRF54H20PDK_NRF54H20_CPURAD + bool "nRF54H20 PDK nRF54H20 Radio MCU" + depends on SOC_NRF54H20_ENGA_CPURAD diff --git a/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig b/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig new file mode 100644 index 00000000000..954276ec829 --- /dev/null +++ b/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + default "nrf54h20pdk_nrf54h20_cpuapp" if BOARD_NRF54H20PDK_NRF54H20_CPUAPP + default "nrf54h20pdk_nrf54h20_cpurad" if BOARD_NRF54H20PDK_NRF54H20_CPURAD + +if BOARD_NRF54H20PDK_NRF54H20_CPUAPP || BOARD_NRF54H20PDK_NRF54H20_CPURAD + +# Data cache is disabled due to a HW issue in the EngA SoC revision. +config DCACHE + default n + +endif # BOARD_NRF54H20PDK_NRF54H20_CPUAPP || BOARD_NRF54H20PDK_NRF54H20_CPURAD diff --git a/boards/arm/nrf54h20pdk_nrf54h20/board.cmake b/boards/arm/nrf54h20pdk_nrf54h20/board.cmake new file mode 100644 index 00000000000..4c63f1dd05e --- /dev/null +++ b/boards/arm/nrf54h20pdk_nrf54h20/board.cmake @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) diff --git a/boards/arm/nrf54h20pdk_nrf54h20/doc/img/nrf54h20pdk_nrf54h20.webp b/boards/arm/nrf54h20pdk_nrf54h20/doc/img/nrf54h20pdk_nrf54h20.webp new file mode 100644 index 0000000000000000000000000000000000000000..bcda6b0732b3acefe24e83332692e8ae898d47b4 GIT binary patch literal 27232 zcmV(sK<&R$Nk&FkY5)LNMM6+kP&il$000000001Q0stKW09H^qAmnKP05D|%odGIv z0v-WAkv^G7C8MIFs<#_f`^Tyu{XVb1!~f~^1^a#KxBm0?$KBueKTr?yzxRD)|MGwT|LO39{#*Y? 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zvmms3KN^>|YAzqBtn34I>ps1;)bG%?q6kd|rW79|(sShsy%G6#be=~tfjt*y4;h(2 zzR!InryGgEy#TIHS3(*pK6BEDhXB~VE?~mk46&?=5%d<3gjk6ni$f1dM^cU?A^FGP zzoY@aSAKXV-dUBh%oQ`K5967$&EybidTzApYc&qRD1A?PWeA|SM2peYR2j04$B(c? z^u1Z8D5|^%a+CM;Vahun2|cRqV1nK`5, + <&cpuapp_bellboard 0>; + }; + + cpusec_cpurad_ipc: ipc-1-3 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpusec_bellboard 18>, + <&cpurad_bellboard 0>; + }; + + cpuapp_cpurad_ipc: ipc-2-3 { + status = "disabled"; + mboxes = <&cpuapp_bellboard 18>, + <&cpurad_bellboard 12>; + }; + + cpuapp_cpuppr_ipc: ipc-2-13 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + mboxes = <&cpuapp_bellboard 13>, + <&cpuppr_vevif 12>; + }; + }; +}; diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi new file mode 100644 index 00000000000..560700b1756 --- /dev/null +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + reserved-memory { + cpuapp_ram0x_region: memory@2f000000 { + compatible = "nordic,owned-memory"; + reg = <0x2f000000 DT_SIZE_K(260)>; + status = "disabled"; + perm-read; + perm-write; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f000000 0x41000>; + + cpusec_cpuapp_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpuapp_cpusec_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + + cpuapp_data: memory@1000 { + reg = <0x1000 DT_SIZE_K(256)>; + }; + }; + + cpurad_ram0x_region: memory@2f041000 { + compatible = "nordic,owned-memory"; + reg = <0x2f041000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f041000 0x1000>; + + cpusec_cpurad_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpurad_cpusec_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + }; + + cpuapp_cpurad_ram0x_region: memory@2f0bf000 { + compatible = "nordic,owned-memory"; + reg = <0x2f0bf000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f0bf000 0x1000>; + + cpuapp_cpurad_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpurad_cpuapp_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + }; + + shared_ram20_region: memory@2f88f000 { + compatible = "nordic,owned-memory"; + reg = <0x2f88f000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f88f000 0x1000>; + + cpuapp_cpusys_ipc_shm: memory@ce0 { + reg = <0xce0 0x80>; + }; + + cpusys_cpuapp_ipc_shm: memory@d60 { + reg = <0xd60 0x80>; + }; + + cpurad_cpusys_ipc_shm: memory@e00 { + reg = <0xe00 0x80>; + }; + + cpusys_cpurad_ipc_shm: memory@e80 { + reg = <0xe80 0x80>; + }; + }; + + cpuppr_ram3x_region: memory@2fc00000 { + compatible = "nordic,owned-memory"; + reg = <0x2fc00000 DT_SIZE_K(28)>; + status = "disabled"; + perm-read; + perm-write; + perm-execute; + }; + + shared_ram3x_region: memory@2fc07000 { + compatible = "nordic,owned-memory"; + reg = <0x2fc07000 DT_SIZE_K(4)>; + status = "disabled"; + perm-read; + perm-write; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2fc07000 0x1000>; + + cpuapp_cpuppr_ipc_shm: memory@0 { + reg = <0x0 0x340>; + }; + + cpuppr_cpuapp_ipc_shm: memory@340 { + reg = <0x340 0x340>; + }; + + cpuapp_dma_region: memory@680 { + compatible = "zephyr,memory-region"; + reg = <0x680 DT_SIZE_K(2)>; + status = "disabled"; + #memory-region-cells = <0>; + zephyr,memory-region = "DMA_RAM3x_APP"; + }; + + cpurad_dma_region: memory@e80 { + compatible = "zephyr,memory-region"; + reg = <0xe80 0x80>; + status = "disabled"; + #memory-region-cells = <0>; + zephyr,memory-region = "DMA_RAM3x_RAD"; + }; + }; + }; +}; + +&mram1x { + cpurad_rx_partitions: cpurad-rx-partitions { + compatible = "nordic,owned-partitions", "fixed-partitions"; + status = "disabled"; + perm-read; + perm-execute; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + + cpurad_slot0_partition: partition@66000 { + reg = <0x66000 DT_SIZE_K(256)>; + }; + }; + + cpuapp_rx_partitions: cpuapp-rx-partitions { + compatible = "nordic,owned-partitions", "fixed-partitions"; + status = "disabled"; + perm-read; + perm-execute; + perm-secure; + #address-cells = <1>; + #size-cells = <1>; + + cpuapp_slot0_partition: partition@a6000 { + reg = <0xa6000 DT_SIZE_K(512)>; + }; + + cpuppr_code_partition: partition@126000 { + reg = <0x126000 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-pinctrl.dtsi b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-pinctrl.dtsi new file mode 100644 index 00000000000..d3b79120322 --- /dev/null +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-pinctrl.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart135_default: uart135_default { + group1 { + psels = , + ; + }; + + group2 { + bias-pull-up; + psels = , + ; + }; + }; + + /omit-if-no-ref/ uart135_sleep: uart135_sleep { + group1 { + low-power-enable; + psels = , + , + , + ; + }; + }; + + /omit-if-no-ref/ uart136_default: uart136_default { + group1 { + psels = , + ; + }; + + group2 { + bias-pull-up; + psels = , + ; + }; + }; + + /omit-if-no-ref/ uart136_sleep: uart136_sleep { + group1 { + low-power-enable; + psels = , + , + , + ; + }; + }; +}; diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts new file mode 100644 index 00000000000..b2db9e4b9b1 --- /dev/null +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf54h20pdk_nrf54h20-memory_map.dtsi" +#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" +#include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" + +/delete-node/ &cpusec_cpurad_ipc; + +/ { + compatible = "nordic,nrf54h20pdk_nrf54h20-cpuapp"; + model = "Nordic nRF54H20 PDK nRF54H20 Application MCU"; + + chosen { + zephyr,console = &uart136; + zephyr,code-partition = &cpuapp_slot0_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpuapp_data; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio0 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + + led2: led_2 { + gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + + led3: led_3 { + gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; +}; + +&cpuapp_ram0x_region { + status = "okay"; +}; + +&shared_ram3x_region { + status = "okay"; +}; + +&cpuapp_bellboard { + interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0"; + /* irq0: 0: cpuapp-cpusec, 13: cpuapp-cpuppr, 18: cpuapp-cpurad */ + nordic,interrupt-mapping = <0x00042001 0>; +}; + +&cpusec_cpuapp_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuapp_cpusec_ipc_shm>; + rx-region = <&cpusec_cpuapp_ipc_shm>; +}; + +&cpuapp_cpurad_ipc { + compatible = "zephyr,ipc-icmsg-me-initiator"; + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpurad_ipc_shm>; + rx-region = <&cpurad_cpuapp_ipc_shm>; +}; + +&cpuapp_cpuppr_ipc { + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpuppr_ipc_shm>; + rx-region = <&cpuppr_cpuapp_ipc_shm>; +}; + +&cpuapp_dma_region { + status = "okay"; +}; + +&cpuapp_rx_partitions { + status = "okay"; +}; + +&cpuppr_vpr { + execution-memory = <&cpuppr_code_partition>; +}; + +&gpiote130 { + status = "okay"; + owned-channels = <0 1 2 3 4 5 6 7>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio9 { + status = "okay"; +}; + +&grtc { + status = "okay"; + child-owned-channels = <5 6>; + nonsecure-channels = <5 6>; + owned-channels = <4 5 6>; +}; + +&uart135 { + current-speed = <115200>; + pinctrl-0 = <&uart135_default>; + pinctrl-1 = <&uart135_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart136 { + status = "okay"; + memory-regions = <&cpuapp_dma_region>; + current-speed = <115200>; + pinctrl-0 = <&uart136_default>; + pinctrl-1 = <&uart136_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.yaml b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.yaml new file mode 100644 index 00000000000..a364c2863d3 --- /dev/null +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20pdk_nrf54h20_cpuapp +name: nRF54H20-PDK-nRF54H20-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 32 +flash: 368 +supported: + - gpio diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp_defconfig b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp_defconfig new file mode 100644 index 00000000000..1f7ef38a7fc --- /dev/null +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp_defconfig @@ -0,0 +1,33 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_NRF54HX=y +CONFIG_SOC_NRF54H20=y +CONFIG_SOC_NRF54H20_ENGA_CPUAPP=y +CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPUAPP=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot be applied +# as the (0x0 - 0x400) region is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts new file mode 100644 index 00000000000..8d2629df62e --- /dev/null +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf54h20pdk_nrf54h20-memory_map.dtsi" +#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" +#include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" + +/delete-node/ &cpuapp_cpuppr_ipc; +/delete-node/ &cpusec_cpuapp_ipc; + +/ { + compatible = "nordic,nrf54h20pdk_nrf54h20-cpurad"; + model = "Nordic nRF54H20 PDK nRF54H20 Radio MCU"; + + chosen { + zephyr,console = &uart135; + zephyr,code-partition = &cpurad_slot0_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpurad_ram0; + }; +}; + +&shared_ram3x_region { + status = "okay"; +}; + +&cpurad_bellboard { + interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0"; + /* irq0: 0: cpurad-cpusec, 12: cpurad-cpuapp */ + nordic,interrupt-mapping = <0x00001001 0>; +}; + +&cpusec_cpurad_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpurad_cpusec_ipc_shm>; + rx-region = <&cpusec_cpurad_ipc_shm>; +}; + +&cpuapp_cpurad_ipc { + compatible = "zephyr,ipc-icmsg-me-follower"; + mbox-names = "tx", "rx"; + tx-region = <&cpurad_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpurad_ipc_shm>; +}; + +&cpurad_dma_region { + status = "okay"; +}; + +&cpurad_rx_partitions { + status = "okay"; +}; + +&grtc { + status = "okay"; + child-owned-channels = <8 9 10 11 12>; + interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>, + <108 NRF_DEFAULT_IRQ_PRIORITY>; + nonsecure-channels = <8 9 10 11 12>; + owned-channels = <7 8 9 10 11 12 13 14>; +}; + +&uart135 { + status = "okay"; + memory-regions = <&cpurad_dma_region>; + current-speed = <115200>; + pinctrl-0 = <&uart135_default>; + pinctrl-1 = <&uart135_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart136 { + current-speed = <115200>; + pinctrl-0 = <&uart136_default>; + pinctrl-1 = <&uart136_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.yaml b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.yaml new file mode 100644 index 00000000000..d1c8548d07d --- /dev/null +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20pdk_nrf54h20_cpurad +name: nRF54H20-PDK-nRF54H20-Radio +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 32 +flash: 368 +supported: + - gpio diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad_defconfig b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad_defconfig new file mode 100644 index 00000000000..254d8656e61 --- /dev/null +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad_defconfig @@ -0,0 +1,30 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_NRF54HX=y +CONFIG_SOC_NRF54H20=y +CONFIG_SOC_NRF54H20_ENGA_CPURAD=y +CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPURAD=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot be applied +# as the (0x0 - 0x400) region is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.board b/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.board new file mode 100644 index 00000000000..9bbbba60dd4 --- /dev/null +++ b/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54H20PDK_NRF54H20_CPUPPR + bool "nRF54H20 PDK nRF54H20 PPR MCU" + depends on SOC_NRF54H20_ENGA_CPUPPR diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.defconfig b/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.defconfig new file mode 100644 index 00000000000..256976d6519 --- /dev/null +++ b/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + default "nrf54h20pdk_nrf54h20_cpuppr" + depends on BOARD_NRF54H20PDK_NRF54H20_CPUPPR diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/board.cmake b/boards/riscv/nrf54h20pdk_nrf54h20/board.cmake new file mode 100644 index 00000000000..4c63f1dd05e --- /dev/null +++ b/boards/riscv/nrf54h20pdk_nrf54h20/board.cmake @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts b/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts new file mode 100644 index 00000000000..f98abb9e44b --- /dev/null +++ b/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "nrf54h20pdk_nrf54h20-memory_map.dtsi" +#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" +#include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" + +/delete-node/ &cpuapp_cpurad_ipc; +/delete-node/ &cpusec_cpuapp_ipc; +/delete-node/ &cpusec_cpurad_ipc; + +/ { + compatible = "nordic,nrf54h20pdk_nrf54h20-cpuppr"; + model = "Nordic nRF54H20 PDK nRF54H20 Peripheral Processor MCU"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart135; + zephyr,code-partition = &cpuppr_code_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpuppr_ram3x_region; + }; +}; + +&cpuapp_cpuppr_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuppr_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpuppr_ipc_shm>; +}; + +&grtc { + status = "okay"; + owned-channels = <5>; +}; + +&uart135 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart135_default>; + pinctrl-1 = <&uart135_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart136 { + current-speed = <115200>; + pinctrl-0 = <&uart136_default>; + pinctrl-1 = <&uart136_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.yaml b/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.yaml new file mode 100644 index 00000000000..274be865c36 --- /dev/null +++ b/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20pdk_nrf54h20_cpuppr +name: nRF54H20-PDK-nRF54H20-PPR +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 28 +flash: 28 +supported: + - gpio diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr_defconfig b/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr_defconfig new file mode 100644 index 00000000000..112140693ef --- /dev/null +++ b/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_NRF54HX=y +CONFIG_SOC_NRF54H20=y +CONFIG_SOC_NRF54H20_ENGA_CPUPPR=y +CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPUPPR=y + +CONFIG_USE_DT_CODE_PARTITION=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/pre_dt_board.cmake b/boards/riscv/nrf54h20pdk_nrf54h20/pre_dt_board.cmake new file mode 100644 index 00000000000..5e0fecebdc8 --- /dev/null +++ b/boards/riscv/nrf54h20pdk_nrf54h20/pre_dt_board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Allow common DTS files to be included from the other board directory. +# To be removed after HWMv2 (#51831), once both directories can be merged into one. +string(REGEX REPLACE "/riscv/(.*$)" "/arm/\\1" BOARD_DIR_ARM "${BOARD_DIR}") +list(APPEND DTS_EXTRA_CPPFLAGS -isystem "${BOARD_DIR_ARM}") From c2f956a18e44815f5ae693143e0f2a19013a71ae Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:25 +0200 Subject: [PATCH 2250/2402] Revert "[nrf fromlist] tests: Replace nRF54H20 PDK with nRF54H20 DK" This reverts commit b933325a93ce4d27b49a9554bb2095bc913514e2. Signed-off-by: Gerard Marull-Paretas --- ...h20_cpuapp.overlay => nrf54h20pdk_nrf54h20_cpuapp.overlay} | 0 tests/lib/cpp/cxx/testcase.yaml | 4 ++-- 2 files changed, 2 insertions(+), 2 deletions(-) rename tests/arch/common/ramfunc/boards/{nrf54h20dk_nrf54h20_cpuapp.overlay => nrf54h20pdk_nrf54h20_cpuapp.overlay} (100%) diff --git a/tests/arch/common/ramfunc/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay similarity index 100% rename from tests/arch/common/ramfunc/boards/nrf54h20dk_nrf54h20_cpuapp.overlay rename to tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay diff --git a/tests/lib/cpp/cxx/testcase.yaml b/tests/lib/cpp/cxx/testcase.yaml index 04e5cd2bf21..f06b451742b 100644 --- a/tests/lib/cpp/cxx/testcase.yaml +++ b/tests/lib/cpp/cxx/testcase.yaml @@ -37,8 +37,8 @@ tests: # Exclude nRF54L15 and nRF54H20 as Nordic HAL is not compatible with C++98. platform_exclude: - nrf54l15pdk_nrf54l15_cpuapp - - nrf54h20dk_nrf54h20_cpuapp - - nrf54h20dk_nrf54h20_cpurad + - nrf54h20pdk_nrf54h20_cpuapp + - nrf54h20pdk_nrf54h20_cpurad build_only: true extra_configs: - CONFIG_STD_CPP98=y From 9534117ef8dfa404a5637aae036ce6c72cf1512d Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:25 +0200 Subject: [PATCH 2251/2402] Revert "[nrf fromtree] tests: arch: common: ramfunc: add nrf54h20pdk cpuapp overlays" This reverts commit afe06d25554dd31a0c0054ee635e61ddb2e2b640. Signed-off-by: Gerard Marull-Paretas --- .../ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay | 8 -------- 1 file changed, 8 deletions(-) delete mode 100644 tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay diff --git a/tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay b/tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay deleted file mode 100644 index 2deb6756009..00000000000 --- a/tests/arch/common/ramfunc/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -&cpuapp_ram0x_region { - perm-execute; -}; From 4189175b688a3ef213700f8a6f6cb61d83b49cb9 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:26 +0200 Subject: [PATCH 2252/2402] Revert "[nrf fromlist] snippets: Replace nRF54H20 PDK with nRF54H20 DK" This reverts commit fb3be114abc636b794ab624f01bf4dbdd6e51bca. Signed-off-by: Gerard Marull-Paretas --- ...h20_cpuapp.overlay => nrf54h20pdk_nrf54h20_cpuapp.overlay} | 4 ++-- snippets/nordic-ppr-ram/nordic-ppr-ram.overlay | 2 +- snippets/nordic-ppr-ram/snippet.yml | 4 ++-- ...h20_cpuapp.overlay => nrf54h20pdk_nrf54h20_cpuapp.overlay} | 0 snippets/nordic-ppr/snippet.yml | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) rename snippets/nordic-ppr-ram/boards/{nrf54h20dk_nrf54h20_cpuapp.overlay => nrf54h20pdk_nrf54h20_cpuapp.overlay} (71%) rename snippets/nordic-ppr/boards/{nrf54h20dk_nrf54h20_cpuapp.overlay => nrf54h20pdk_nrf54h20_cpuapp.overlay} (100%) diff --git a/snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/snippets/nordic-ppr-ram/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay similarity index 71% rename from snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay rename to snippets/nordic-ppr-ram/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay index ea866358fc0..5597c886b85 100644 --- a/snippets/nordic-ppr-ram/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/snippets/nordic-ppr-ram/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay @@ -3,12 +3,12 @@ * SPDX-License-Identifier: Apache-2.0 */ -&cpuppr_code_data { +&cpuppr_ram3x_region { status = "okay"; }; &cpuppr_vpr { - execution-memory = <&cpuppr_code_data>; + execution-memory = <&cpuppr_ram3x_region>; }; &uart135 { diff --git a/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay b/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay index 71c45c1b9f4..e69c3a0d2bf 100644 --- a/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay +++ b/snippets/nordic-ppr-ram/nordic-ppr-ram.overlay @@ -11,5 +11,5 @@ /* code partition size must match RAM size */ &cpuppr_code_partition { - reg = <0x126000 DT_SIZE_K(62)>; + reg = <0x126000 DT_SIZE_K(28)>; }; diff --git a/snippets/nordic-ppr-ram/snippet.yml b/snippets/nordic-ppr-ram/snippet.yml index 022ed8d38e8..0d6039af2e5 100644 --- a/snippets/nordic-ppr-ram/snippet.yml +++ b/snippets/nordic-ppr-ram/snippet.yml @@ -3,6 +3,6 @@ append: EXTRA_DTC_OVERLAY_FILE: nordic-ppr-ram.overlay boards: - nrf54h20dk_nrf54h20_cpuapp: + nrf54h20pdk_nrf54h20_cpuapp: append: - EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay + EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20pdk_nrf54h20_cpuapp.overlay diff --git a/snippets/nordic-ppr/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/snippets/nordic-ppr/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay similarity index 100% rename from snippets/nordic-ppr/boards/nrf54h20dk_nrf54h20_cpuapp.overlay rename to snippets/nordic-ppr/boards/nrf54h20pdk_nrf54h20_cpuapp.overlay diff --git a/snippets/nordic-ppr/snippet.yml b/snippets/nordic-ppr/snippet.yml index d9b37963c3a..9e1f20bb757 100644 --- a/snippets/nordic-ppr/snippet.yml +++ b/snippets/nordic-ppr/snippet.yml @@ -3,6 +3,6 @@ append: EXTRA_DTC_OVERLAY_FILE: nordic-ppr.overlay boards: - nrf54h20dk_nrf54h20_cpuapp: + nrf54h20pdk_nrf54h20_cpuapp: append: - EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay + EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20pdk_nrf54h20_cpuapp.overlay From 423b85d3d3873182a94878ede3573cf0073e29e3 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:26 +0200 Subject: [PATCH 2253/2402] Revert "[nrf fromlist] samples: Replace nRF54H20 PDK with nRF54H20 DK" This reverts commit 7ead64ecf47a4ae42b29aef31182365d0d4a03a1. Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/CMakeLists.txt | 2 +- samples/drivers/mbox/Kconfig.sysbuild | 2 +- ...rf54h20pdk_nrf54h20_cpuapp_bellboard.conf} | 0 ...4h20pdk_nrf54h20_cpuapp_bellboard.overlay} | 0 ...=> nrf54h20pdk_nrf54h20_cpuapp_vevif.conf} | 0 ...nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay} | 0 samples/drivers/mbox/remote/CMakeLists.txt | 2 +- ...rf54h20pdk_nrf54h20_cpuppr_bellboard.conf} | 0 ...4h20pdk_nrf54h20_cpuppr_bellboard.overlay} | 0 ...=> nrf54h20pdk_nrf54h20_cpuppr_vevif.conf} | 0 ...nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay} | 0 samples/drivers/mbox/sample.yaml | 24 +++++++++---------- 12 files changed, 15 insertions(+), 15 deletions(-) rename samples/drivers/mbox/boards/{nrf54h20dk_nrf54h20_cpuapp_bellboard.conf => nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf} (100%) rename samples/drivers/mbox/boards/{nrf54h20dk_nrf54h20_cpuapp_bellboard.overlay => nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay} (100%) rename samples/drivers/mbox/boards/{nrf54h20dk_nrf54h20_cpuapp_vevif.conf => nrf54h20pdk_nrf54h20_cpuapp_vevif.conf} (100%) rename samples/drivers/mbox/boards/{nrf54h20dk_nrf54h20_cpuapp_vevif.overlay => nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay} (100%) rename samples/drivers/mbox/remote/boards/{nrf54h20dk_nrf54h20_cpuppr_bellboard.conf => nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf} (100%) rename samples/drivers/mbox/remote/boards/{nrf54h20dk_nrf54h20_cpuppr_bellboard.overlay => nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay} (100%) rename samples/drivers/mbox/remote/boards/{nrf54h20dk_nrf54h20_cpuppr_vevif.conf => nrf54h20pdk_nrf54h20_cpuppr_vevif.conf} (100%) rename samples/drivers/mbox/remote/boards/{nrf54h20dk_nrf54h20_cpuppr_vevif.overlay => nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay} (100%) diff --git a/samples/drivers/mbox/CMakeLists.txt b/samples/drivers/mbox/CMakeLists.txt index 5c21619a8cf..c69621c2496 100644 --- a/samples/drivers/mbox/CMakeLists.txt +++ b/samples/drivers/mbox/CMakeLists.txt @@ -18,7 +18,7 @@ if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp") OR ("${BOARD}" STREQUAL "mimxrt1170_evk_cm7") OR ("${BOARD}" STREQUAL "mimxrt1160_evk_cm7") OR ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu0") OR - ("${BOARD}" STREQUAL "nrf54h20dk_nrf54h20_cpuapp")) + ("${BOARD}" STREQUAL "nrf54h20pdk_nrf54h20_cpuapp")) message(STATUS "${BOARD} compile as Main in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/Kconfig.sysbuild b/samples/drivers/mbox/Kconfig.sysbuild index 0899d958bdb..aca48b8ead3 100644 --- a/samples/drivers/mbox/Kconfig.sysbuild +++ b/samples/drivers/mbox/Kconfig.sysbuild @@ -14,4 +14,4 @@ string default "mimxrt1170_evk_cm4" if $(BOARD) = "mimxrt1170_evk_cm7" default "mimxrt1160_evk_cm4" if $(BOARD) = "mimxrt1160_evk_cm7" default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" - default "nrf54h20dk_nrf54h20_cpuppr" if $(BOARD) = "nrf54h20dk_nrf54h20_cpuapp" + default "nrf54h20pdk_nrf54h20_cpuppr" if $(BOARD) = "nrf54h20pdk_nrf54h20_cpuapp" diff --git a/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.conf b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf similarity index 100% rename from samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.conf rename to samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf diff --git a/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.overlay b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay similarity index 100% rename from samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.overlay rename to samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay diff --git a/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_vevif.conf b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf similarity index 100% rename from samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_vevif.conf rename to samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf diff --git a/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_vevif.overlay b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay similarity index 100% rename from samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_vevif.overlay rename to samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay diff --git a/samples/drivers/mbox/remote/CMakeLists.txt b/samples/drivers/mbox/remote/CMakeLists.txt index 9ae8d377685..cb024cb6112 100644 --- a/samples/drivers/mbox/remote/CMakeLists.txt +++ b/samples/drivers/mbox/remote/CMakeLists.txt @@ -16,7 +16,7 @@ if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpunet") OR ("${BOARD}" STREQUAL "mimxrt1160_evk_cm4") OR ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu1") OR ("${BOARD}" STREQUAL "adp_xc7k_ae350") OR - ("${BOARD}" STREQUAL "nrf54h20dk_nrf54h20_cpuppr")) + ("${BOARD}" STREQUAL "nrf54h20pdk_nrf54h20_cpuppr")) message(STATUS "${BOARD} compile as remote in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.conf b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf similarity index 100% rename from samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.conf rename to samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf diff --git a/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.overlay b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay similarity index 100% rename from samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.overlay rename to samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay diff --git a/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_vevif.conf b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf similarity index 100% rename from samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_vevif.conf rename to samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf diff --git a/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_vevif.overlay b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay similarity index 100% rename from samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuppr_vevif.overlay rename to samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml index 19b6322d9bf..b386b9d2b4b 100644 --- a/samples/drivers/mbox/sample.yaml +++ b/samples/drivers/mbox/sample.yaml @@ -26,15 +26,15 @@ tests: sample.drivers.mbox.nrf54h20_vevif: platform_allow: - - nrf54h20dk_nrf54h20_cpuapp + - nrf54h20pdk_nrf54h20_cpuapp integration_platforms: - - nrf54h20dk_nrf54h20_cpuapp + - nrf54h20pdk_nrf54h20_cpuapp extra_args: mbox_SNIPPET=nordic-ppr - mbox_EXTRA_CONF_FILE=boards/nrf54h20dk_nrf54h20_cpuapp_vevif.conf - mbox_DTC_OVERLAY_FILE=boards/nrf54h20dk_nrf54h20_cpuapp_vevif.overlay - remote_EXTRA_CONF_FILE=boards/nrf54h20dk_nrf54h20_cpuppr_vevif.conf - remote_DTC_OVERLAY_FILE=boards/nrf54h20dk_nrf54h20_cpuppr_vevif.overlay + mbox_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf + mbox_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay + remote_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf + remote_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay sysbuild: true harness: console harness_config: @@ -46,15 +46,15 @@ tests: sample.drivers.mbox.nrf54h20_bellboard: platform_allow: - - nrf54h20dk_nrf54h20_cpuapp + - nrf54h20pdk_nrf54h20_cpuapp integration_platforms: - - nrf54h20dk_nrf54h20_cpuapp + - nrf54h20pdk_nrf54h20_cpuapp extra_args: mbox_SNIPPET=nordic-ppr - mbox_EXTRA_CONF_FILE=boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.conf - mbox_DTC_OVERLAY_FILE=boards/nrf54h20dk_nrf54h20_cpuapp_bellboard.overlay - remote_EXTRA_CONF_FILE=boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.conf - remote_DTC_OVERLAY_FILE=boards/nrf54h20dk_nrf54h20_cpuppr_bellboard.overlay + mbox_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf + mbox_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay + remote_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf + remote_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay sysbuild: true harness: console harness_config: From 161b554e83b2363712c13529ec98e21ef93cd715 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:26 +0200 Subject: [PATCH 2254/2402] Revert "[nrf fromlist] boards: nordic: Add support for nRF54H20 DK" This reverts commit 831cf634c93216a742c61a7ef0b5a023a4001b59. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf54h20dk_nrf54h20/Kconfig.board | 10 - .../arm/nrf54h20dk_nrf54h20/Kconfig.defconfig | 6 - boards/arm/nrf54h20dk_nrf54h20/board.cmake | 13 -- boards/arm/nrf54h20dk_nrf54h20/doc/index.rst | 154 --------------- .../nrf54h20dk_nrf54h20-ipc_conf.dtsi | 36 ---- .../nrf54h20dk_nrf54h20-memory_map.dtsi | 184 ------------------ .../nrf54h20dk_nrf54h20-pinctrl.dtsi | 53 ----- .../nrf54h20dk_nrf54h20_cpuapp.dts | 171 ---------------- .../nrf54h20dk_nrf54h20_cpuapp.yaml | 15 -- .../nrf54h20dk_nrf54h20_cpuapp_defconfig | 33 ---- .../nrf54h20dk_nrf54h20_cpurad.dts | 84 -------- .../nrf54h20dk_nrf54h20_cpurad.yaml | 15 -- .../nrf54h20dk_nrf54h20_cpurad_defconfig | 30 --- .../support/nrf54h20_cpurad.JLinkScript | 4 - .../riscv/nrf54h20dk_nrf54h20/Kconfig.board | 10 - .../nrf54h20dk_nrf54h20/Kconfig.defconfig | 6 - .../nrf54h20dk_nrf54h20_cpuppr.dts | 56 ------ .../nrf54h20dk_nrf54h20_cpuppr.yaml | 13 -- .../nrf54h20dk_nrf54h20_cpuppr_defconfig | 14 -- .../nrf54h20dk_nrf54h20_cpuppr_ram.dts | 11 -- .../nrf54h20dk_nrf54h20_cpuppr_ram.yaml | 13 -- .../nrf54h20dk_nrf54h20_cpuppr_ram_defconfig | 16 -- .../nrf54h20dk_nrf54h20/pre_dt_board.cmake | 7 - 23 files changed, 954 deletions(-) delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/Kconfig.board delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/Kconfig.defconfig delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/board.cmake delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/doc/index.rst delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-ipc_conf.dtsi delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-memory_map.dtsi delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-pinctrl.dtsi delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.yaml delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp_defconfig delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.yaml delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad_defconfig delete mode 100644 boards/arm/nrf54h20dk_nrf54h20/support/nrf54h20_cpurad.JLinkScript delete mode 100644 boards/riscv/nrf54h20dk_nrf54h20/Kconfig.board delete mode 100644 boards/riscv/nrf54h20dk_nrf54h20/Kconfig.defconfig delete mode 100644 boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.dts delete mode 100644 boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.yaml delete mode 100644 boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_defconfig delete mode 100644 boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.dts delete mode 100644 boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.yaml delete mode 100644 boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig delete mode 100644 boards/riscv/nrf54h20dk_nrf54h20/pre_dt_board.cmake diff --git a/boards/arm/nrf54h20dk_nrf54h20/Kconfig.board b/boards/arm/nrf54h20dk_nrf54h20/Kconfig.board deleted file mode 100644 index 831ddc009c2..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF54H20DK_NRF54H20_CPUAPP - bool "nRF54H20 DK nRF54H20 Application MCU" - depends on SOC_NRF54H20_CPUAPP - -config BOARD_NRF54H20DK_NRF54H20_CPURAD - bool "nRF54H20 DK nRF54H20 Radio MCU" - depends on SOC_NRF54H20_CPURAD diff --git a/boards/arm/nrf54h20dk_nrf54h20/Kconfig.defconfig b/boards/arm/nrf54h20dk_nrf54h20/Kconfig.defconfig deleted file mode 100644 index 1a029338775..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "nrf54h20dk_nrf54h20_cpuapp" if BOARD_NRF54H20DK_NRF54H20_CPUAPP - default "nrf54h20dk_nrf54h20_cpurad" if BOARD_NRF54H20DK_NRF54H20_CPURAD diff --git a/boards/arm/nrf54h20dk_nrf54h20/board.cmake b/boards/arm/nrf54h20dk_nrf54h20/board.cmake deleted file mode 100644 index 32d1daac179..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD) - if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD) - set( - JLINK_TOOL_OPT - "-jlinkscriptfile ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpurad.JLinkScript" - ) - endif() - - board_runner_args(jlink "--device=CORTEX-M33" "--speed=4000" "--tool-opt=${JLINK_TOOL_OPT}") - include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -endif() diff --git a/boards/arm/nrf54h20dk_nrf54h20/doc/index.rst b/boards/arm/nrf54h20dk_nrf54h20/doc/index.rst deleted file mode 100644 index 6b8a08f0953..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/doc/index.rst +++ /dev/null @@ -1,154 +0,0 @@ -.. _nrf54h20dk_nrf54h20: - -nRF54H20 DK -########### - -Overview -******** - -.. note:: - - All software for the nRF54H20 SoC is experimental and hardware availability - is restricted to the participants in the limited sampling program. - -The nRF54H20 DK is a single-board development kit for evaluation and development -on the Nordic nRF54H20 System-on-Chip (SoC). - -The nRF54H20 is a multicore SoC with: - -* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security - Extensions, running at up to 320 MHz, referred to as the **application core** -* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security - Extensions, running at up to 256 MHz, referred to as the **radio core**. - -The ``nrf54h20dk/nrf54h20/cpuapp`` build target provides support for -the application core on the nRF54H20 SoC. -The ``nrf54h20dk/nrf54h20/cpurad`` build target provides support for -the radio core on the nRF54H20 SoC. - -nRF54H20 SoC provides support for the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`GRTC (Global real-time counter)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* MRAM -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -Hardware -******** - -nRF54H20 DK has two crystal oscillators: - -* High-frequency 32 MHz crystal oscillator (HFXO) -* Low-frequency 32.768 kHz crystal oscillator (LFXO) - -Supported Features -================== - -The ``nrf54h20dk/nrf54h20/cpuapp`` board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GRTC | on-chip | system clock | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The ``nrf54h20dk/nrf54h20/cpurad`` board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GRTC | on-chip | system clock | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -LEDs ----- - -* LED1 (green) = P9.0 -* LED2 (green) = P9.1 -* LED3 (green) = P9.2 -* LED4 (green) = P9.3 - -Push buttons ------------- - -* BUTTON1 = P0.8 -* BUTTON2 = P0.9 -* BUTTON3 = P0.10 -* BUTTON4 = P0.11 -* RESET (SW1) - -Programming and Debugging -************************* - -Applications for both the ``nrf54h20dk/nrf54h20/cpuapp`` and -``nrf54h20dk/nrf54h20/cpurad`` targets can be built, flashed, -and debugged in the usual way. See :ref:`build_an_application` -and :ref:`application_run` for more details on building and running. - -Flashing -======== - -As an example, this section shows how to build and flash the :ref:`hello_world` -application. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. - -To build and program the sample to the nRF54H20 DK, complete the following steps: - -1. Connect the nRF54H20 DK to your computer using the IMCU USB port on the DK. -#. Build the sample by running the following command: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf54h20dk/nrf54h20/cpuapp - :goals: build flash - -Testing the LEDs and buttons in the nRF54H20 DK -*********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs -on the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts`. diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-ipc_conf.dtsi b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-ipc_conf.dtsi deleted file mode 100644 index 9c3d971b9bc..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-ipc_conf.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - ipc { - cpusec_cpuapp_ipc: ipc-1-2 { - compatible = "zephyr,ipc-icmsg"; - status = "disabled"; - mboxes = <&cpusec_bellboard 12>, - <&cpuapp_bellboard 0>; - }; - - cpusec_cpurad_ipc: ipc-1-3 { - compatible = "zephyr,ipc-icmsg"; - status = "disabled"; - mboxes = <&cpusec_bellboard 18>, - <&cpurad_bellboard 0>; - }; - - cpuapp_cpurad_ipc: ipc-2-3 { - status = "disabled"; - mboxes = <&cpuapp_bellboard 18>, - <&cpurad_bellboard 12>; - }; - - cpuapp_cpuppr_ipc: ipc-2-13 { - compatible = "zephyr,ipc-icmsg"; - status = "disabled"; - mboxes = <&cpuapp_bellboard 13>, - <&cpuppr_vevif 12>; - }; - }; -}; diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-memory_map.dtsi deleted file mode 100644 index 6b6402eb90f..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-memory_map.dtsi +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - reserved-memory { - cpuapp_ram0x_region: memory@2f000000 { - compatible = "nordic,owned-memory"; - reg = <0x2f000000 DT_SIZE_K(260)>; - status = "disabled"; - perm-read; - perm-write; - perm-secure; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f000000 0x41000>; - - cpusec_cpuapp_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; - - cpuapp_cpusec_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; - - cpuapp_data: memory@1000 { - reg = <0x1000 DT_SIZE_K(256)>; - }; - }; - - cpurad_ram0x_region: memory@2f041000 { - compatible = "nordic,owned-memory"; - reg = <0x2f041000 DT_SIZE_K(4)>; - status = "disabled"; - perm-read; - perm-write; - perm-secure; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f041000 0x1000>; - - cpusec_cpurad_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; - - cpurad_cpusec_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; - }; - - cpuapp_cpurad_ram0x_region: memory@2f0bf000 { - compatible = "nordic,owned-memory"; - reg = <0x2f0bf000 DT_SIZE_K(4)>; - status = "disabled"; - perm-read; - perm-write; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f0bf000 0x1000>; - - cpuapp_cpurad_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; - - cpurad_cpuapp_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; - }; - - shared_ram20_region: memory@2f88f000 { - compatible = "nordic,owned-memory"; - reg = <0x2f88f000 DT_SIZE_K(4)>; - status = "disabled"; - perm-read; - perm-write; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f88f000 0x1000>; - - cpuapp_cpusys_ipc_shm: memory@ce0 { - reg = <0xce0 0x80>; - }; - - cpusys_cpuapp_ipc_shm: memory@d60 { - reg = <0xd60 0x80>; - }; - - cpurad_cpusys_ipc_shm: memory@e00 { - reg = <0xe00 0x80>; - }; - - cpusys_cpurad_ipc_shm: memory@e80 { - reg = <0xe80 0x80>; - }; - }; - - cpuppr_ram3x_region: memory@2fc00000 { - compatible = "nordic,owned-memory"; - reg = <0x2fc00000 DT_SIZE_K(64)>; - status = "disabled"; - perm-read; - perm-write; - perm-execute; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2fc00000 0x10000>; - - cpuppr_code_data: memory@0 { - reg = <0x0 DT_SIZE_K(62)>; - }; - - cpuapp_cpuppr_ipc_shm: memory@f800 { - reg = <0xf800 DT_SIZE_K(1)>; - }; - - cpuppr_cpuapp_ipc_shm: memory@fc00 { - reg = <0xfc00 DT_SIZE_K(1)>; - }; - }; - - shared_ram3x_region: memory@2fc12000 { - compatible = "nordic,owned-memory"; - reg = <0x2fc12000 DT_SIZE_K(8)>; - status = "disabled"; - perm-read; - perm-write; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2fc12000 0x2000>; - - cpuapp_dma_region: memory@e80 { - compatible = "zephyr,memory-region"; - reg = <0xe80 DT_SIZE_K(4)>; - status = "disabled"; - #memory-region-cells = <0>; - zephyr,memory-region = "DMA_RAM3x_APP"; - }; - - cpurad_dma_region: memory@1e80 { - compatible = "zephyr,memory-region"; - reg = <0x1e80 0x80>; - status = "disabled"; - #memory-region-cells = <0>; - zephyr,memory-region = "DMA_RAM3x_RAD"; - }; - }; - }; -}; - -&mram1x { - cpurad_rx_partitions: cpurad-rx-partitions { - compatible = "nordic,owned-partitions", "fixed-partitions"; - status = "disabled"; - perm-read; - perm-execute; - perm-secure; - #address-cells = <1>; - #size-cells = <1>; - - cpurad_slot0_partition: partition@66000 { - reg = <0x66000 DT_SIZE_K(256)>; - }; - }; - - cpuapp_rx_partitions: cpuapp-rx-partitions { - compatible = "nordic,owned-partitions", "fixed-partitions"; - status = "disabled"; - perm-read; - perm-execute; - perm-secure; - #address-cells = <1>; - #size-cells = <1>; - - cpuapp_slot0_partition: partition@a6000 { - reg = <0xa6000 DT_SIZE_K(512)>; - }; - - cpuppr_code_partition: partition@126000 { - reg = <0x126000 DT_SIZE_K(64)>; - }; - }; -}; diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-pinctrl.dtsi b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-pinctrl.dtsi deleted file mode 100644 index 6c6da3fa747..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20-pinctrl.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - /omit-if-no-ref/ uart135_default: uart135_default { - group1 { - psels = , - ; - }; - - group2 { - bias-pull-up; - psels = , - ; - }; - }; - - /omit-if-no-ref/ uart135_sleep: uart135_sleep { - group1 { - low-power-enable; - psels = , - , - , - ; - }; - }; - - /omit-if-no-ref/ uart136_default: uart136_default { - group1 { - psels = , - ; - }; - - group2 { - bias-pull-up; - psels = , - ; - }; - }; - - /omit-if-no-ref/ uart136_sleep: uart136_sleep { - group1 { - low-power-enable; - psels = , - , - , - ; - }; - }; -}; diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts deleted file mode 100644 index 3873fec457e..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.dts +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "nrf54h20dk_nrf54h20-memory_map.dtsi" -#include "nrf54h20dk_nrf54h20-ipc_conf.dtsi" -#include "nrf54h20dk_nrf54h20-pinctrl.dtsi" - -/delete-node/ &cpusec_cpurad_ipc; - -/ { - compatible = "nordic,nrf54h20dk_nrf54h20-cpuapp"; - model = "Nordic nRF54H20 DK nRF54H20 Application MCU"; - - chosen { - zephyr,console = &uart136; - zephyr,code-partition = &cpuapp_slot0_partition; - zephyr,flash = &mram1x; - zephyr,sram = &cpuapp_data; - }; - - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - led3 = &led3; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - sw3 = &button3; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 0"; - zephyr,code = ; - }; - - button1: button_1 { - gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 1"; - zephyr,code = ; - }; - - button2: button_2 { - gpios = <&gpio0 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 2"; - zephyr,code = ; - }; - - button3: button_3 { - gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 3"; - zephyr,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0: led_0 { - gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; - label = "Green LED 0"; - }; - - led1: led_1 { - gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; - label = "Green LED 1"; - }; - - led2: led_2 { - gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; - label = "Green LED 2"; - }; - - led3: led_3 { - gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; - label = "Green LED 3"; - }; - }; -}; - -&cpuapp_ram0x_region { - status = "okay"; -}; - -&shared_ram3x_region { - status = "okay"; -}; - -&cpuapp_bellboard { - interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; - interrupt-names = "irq0"; - /* irq0: 0: cpuapp-cpusec, 13: cpuapp-cpuppr, 18: cpuapp-cpurad */ - nordic,interrupt-mapping = <0x00042001 0>; -}; - -&cpusec_cpuapp_ipc { - mbox-names = "tx", "rx"; - tx-region = <&cpuapp_cpusec_ipc_shm>; - rx-region = <&cpusec_cpuapp_ipc_shm>; -}; - -&cpuapp_cpurad_ipc { - compatible = "zephyr,ipc-icmsg-me-initiator"; - mbox-names = "rx", "tx"; - tx-region = <&cpuapp_cpurad_ipc_shm>; - rx-region = <&cpurad_cpuapp_ipc_shm>; -}; - -&cpuapp_cpuppr_ipc { - mbox-names = "rx", "tx"; - tx-region = <&cpuapp_cpuppr_ipc_shm>; - rx-region = <&cpuppr_cpuapp_ipc_shm>; -}; - -&cpuapp_dma_region { - status = "okay"; -}; - -&cpuapp_rx_partitions { - status = "okay"; -}; - -&cpuppr_vpr { - execution-memory = <&cpuppr_code_partition>; -}; - -&gpiote130 { - status = "okay"; - owned-channels = <0 1 2 3 4 5 6 7>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio9 { - status = "okay"; -}; - -&grtc { - status = "okay"; - child-owned-channels = <5 6>; - nonsecure-channels = <5 6>; - owned-channels = <4 5 6>; -}; - -&uart135 { - current-speed = <115200>; - pinctrl-0 = <&uart135_default>; - pinctrl-1 = <&uart135_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart136 { - status = "okay"; - memory-regions = <&cpuapp_dma_region>; - current-speed = <115200>; - pinctrl-0 = <&uart136_default>; - pinctrl-1 = <&uart136_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.yaml b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.yaml deleted file mode 100644 index ec2437ef84c..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54h20dk_nrf54h20_cpuapp -name: nRF54H20-DK-nRF54H20-Application -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 256 -flash: 512 -supported: - - gpio diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp_defconfig b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp_defconfig deleted file mode 100644 index d83fabfcfa0..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuapp_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF54HX=y -CONFIG_SOC_NRF54H20=y -CONFIG_SOC_NRF54H20_CPUAPP=y -CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP=y - -CONFIG_USE_DT_CODE_PARTITION=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# MPU-based null-pointer dereferencing detection cannot be applied -# as the (0x0 - 0x400) region is unmapped for this target. -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y - -# Enable cache -CONFIG_CACHE_MANAGEMENT=y -CONFIG_EXTERNAL_CACHE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts deleted file mode 100644 index 1998f4fc131..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.dts +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "nrf54h20dk_nrf54h20-memory_map.dtsi" -#include "nrf54h20dk_nrf54h20-ipc_conf.dtsi" -#include "nrf54h20dk_nrf54h20-pinctrl.dtsi" - -/delete-node/ &cpuapp_cpuppr_ipc; -/delete-node/ &cpusec_cpuapp_ipc; - -/ { - compatible = "nordic,nrf54h20dk_nrf54h20-cpurad"; - model = "Nordic nRF54H20 DK nRF54H20 Radio MCU"; - - chosen { - zephyr,console = &uart135; - zephyr,code-partition = &cpurad_slot0_partition; - zephyr,flash = &mram1x; - zephyr,sram = &cpurad_ram0; - }; -}; - -&shared_ram3x_region { - status = "okay"; -}; - -&cpurad_bellboard { - interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; - interrupt-names = "irq0"; - /* irq0: 0: cpurad-cpusec, 12: cpurad-cpuapp */ - nordic,interrupt-mapping = <0x00001001 0>; -}; - -&cpusec_cpurad_ipc { - mbox-names = "tx", "rx"; - tx-region = <&cpurad_cpusec_ipc_shm>; - rx-region = <&cpusec_cpurad_ipc_shm>; -}; - -&cpuapp_cpurad_ipc { - compatible = "zephyr,ipc-icmsg-me-follower"; - mbox-names = "tx", "rx"; - tx-region = <&cpurad_cpuapp_ipc_shm>; - rx-region = <&cpuapp_cpurad_ipc_shm>; -}; - -&cpurad_dma_region { - status = "okay"; -}; - -&cpurad_rx_partitions { - status = "okay"; -}; - -&grtc { - status = "okay"; - child-owned-channels = <8 9 10 11 12>; - interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>, - <108 NRF_DEFAULT_IRQ_PRIORITY>; - nonsecure-channels = <8 9 10 11 12>; - owned-channels = <7 8 9 10 11 12 13 14>; -}; - -&uart135 { - status = "okay"; - memory-regions = <&cpurad_dma_region>; - current-speed = <115200>; - pinctrl-0 = <&uart135_default>; - pinctrl-1 = <&uart135_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart136 { - current-speed = <115200>; - pinctrl-0 = <&uart136_default>; - pinctrl-1 = <&uart136_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.yaml b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.yaml deleted file mode 100644 index 80bd2a60ec0..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54h20dk_nrf54h20_cpurad -name: nRF54H20-DK-nRF54H20-Radio -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 192 -flash: 256 -supported: - - gpio diff --git a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad_defconfig b/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad_defconfig deleted file mode 100644 index 4d87fe6bc0e..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpurad_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF54HX=y -CONFIG_SOC_NRF54H20=y -CONFIG_SOC_NRF54H20_CPURAD=y -CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD=y - -CONFIG_USE_DT_CODE_PARTITION=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# MPU-based null-pointer dereferencing detection cannot be applied -# as the (0x0 - 0x400) region is unmapped for this target. -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y - -# Enable cache -CONFIG_CACHE_MANAGEMENT=y -CONFIG_EXTERNAL_CACHE=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf54h20dk_nrf54h20/support/nrf54h20_cpurad.JLinkScript b/boards/arm/nrf54h20dk_nrf54h20/support/nrf54h20_cpurad.JLinkScript deleted file mode 100644 index 2fb7e32302e..00000000000 --- a/boards/arm/nrf54h20dk_nrf54h20/support/nrf54h20_cpurad.JLinkScript +++ /dev/null @@ -1,4 +0,0 @@ -void ConfigTargetSettings(void) { - JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP"); - CORESIGHT_IndexAHBAPToUse = 1; -} diff --git a/boards/riscv/nrf54h20dk_nrf54h20/Kconfig.board b/boards/riscv/nrf54h20dk_nrf54h20/Kconfig.board deleted file mode 100644 index a35655ec3fd..00000000000 --- a/boards/riscv/nrf54h20dk_nrf54h20/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF54H20DK_NRF54H20_CPUPPR - bool "nRF54H20 DK nRF54H20 PPR MCU" - depends on SOC_NRF54H20_CPUPPR - -config BOARD_NRF54H20DK_NRF54H20_CPUPPR_RAM - bool "nRF54H20 DK nRF54H20 PPR MCU (executing from RAM)" - depends on SOC_NRF54H20_CPUPPR diff --git a/boards/riscv/nrf54h20dk_nrf54h20/Kconfig.defconfig b/boards/riscv/nrf54h20dk_nrf54h20/Kconfig.defconfig deleted file mode 100644 index fa67352d3c8..00000000000 --- a/boards/riscv/nrf54h20dk_nrf54h20/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "nrf54h20dk_nrf54h20_cpuppr" - depends on BOARD_NRF54H20DK_NRF54H20_CPUPPR || BOARD_NRF54H20DK_NRF54H20_CPUPPR_RAM diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.dts b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.dts deleted file mode 100644 index edce1a8b275..00000000000 --- a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.dts +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "nrf54h20dk_nrf54h20-memory_map.dtsi" -#include "nrf54h20dk_nrf54h20-ipc_conf.dtsi" -#include "nrf54h20dk_nrf54h20-pinctrl.dtsi" - -/delete-node/ &cpuapp_cpurad_ipc; -/delete-node/ &cpusec_cpuapp_ipc; -/delete-node/ &cpusec_cpurad_ipc; - -/ { - compatible = "nordic,nrf54h20dk_nrf54h20-cpuppr"; - model = "Nordic nRF54H20 DK nRF54H20 Peripheral Processor MCU"; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - zephyr,console = &uart135; - zephyr,code-partition = &cpuppr_code_partition; - zephyr,flash = &mram1x; - zephyr,sram = &cpuppr_code_data; - }; -}; - -&cpuapp_cpuppr_ipc { - mbox-names = "tx", "rx"; - tx-region = <&cpuppr_cpuapp_ipc_shm>; - rx-region = <&cpuapp_cpuppr_ipc_shm>; -}; - -&grtc { - status = "okay"; - owned-channels = <5>; -}; - -&uart135 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart135_default>; - pinctrl-1 = <&uart135_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart136 { - current-speed = <115200>; - pinctrl-0 = <&uart136_default>; - pinctrl-1 = <&uart136_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.yaml b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.yaml deleted file mode 100644 index 02e28651f5d..00000000000 --- a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54h20dk_nrf54h20_cpuppr -name: nRF54H20-DK-nRF54H20-PPR -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 62 -flash: 64 -supported: - - gpio diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_defconfig b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_defconfig deleted file mode 100644 index 2f6ccc43892..00000000000 --- a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF54HX=y -CONFIG_SOC_NRF54H20=y -CONFIG_SOC_NRF54H20_CPUPPR=y -CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR=y - -CONFIG_USE_DT_CODE_PARTITION=y - -CONFIG_SERIAL=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.dts b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.dts deleted file mode 100644 index b10cff15474..00000000000 --- a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.dts +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "nrf54h20dk_nrf54h20_cpuppr.dts" - -&cpuppr_code_partition { - reg = <0x126000 DT_SIZE_K(62)>; -}; diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.yaml b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.yaml deleted file mode 100644 index 26d6ebeac9a..00000000000 --- a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54h20dk_nrf54h20_cpuppr_ram -name: nRF54H20-DK-nRF54H20-PPR-RAM -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 62 -flash: 62 -supported: - - gpio diff --git a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig b/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig deleted file mode 100644 index 73056fac7ef..00000000000 --- a/boards/riscv/nrf54h20dk_nrf54h20/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF54HX=y -CONFIG_SOC_NRF54H20=y -CONFIG_SOC_NRF54H20_CPUPPR=y -CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR=y - -CONFIG_USE_DT_CODE_PARTITION=y - -CONFIG_SERIAL=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_XIP=n diff --git a/boards/riscv/nrf54h20dk_nrf54h20/pre_dt_board.cmake b/boards/riscv/nrf54h20dk_nrf54h20/pre_dt_board.cmake deleted file mode 100644 index 5e0fecebdc8..00000000000 --- a/boards/riscv/nrf54h20dk_nrf54h20/pre_dt_board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Allow common DTS files to be included from the other board directory. -# To be removed after HWMv2 (#51831), once both directories can be merged into one. -string(REGEX REPLACE "/riscv/(.*$)" "/arm/\\1" BOARD_DIR_ARM "${BOARD_DIR}") -list(APPEND DTS_EXTRA_CPPFLAGS -isystem "${BOARD_DIR_ARM}") From f99357f994c18c3417864e07c16c2d3aa50faf9c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:26 +0200 Subject: [PATCH 2255/2402] Revert "[nrf fromtree] modules: hal_nordic: Add nrfx configuration needed for nRF54H20" This reverts commit 26010c1110a8682c0a3afb0023c93b560d953f3b. Signed-off-by: Gerard Marull-Paretas --- modules/hal_nordic/nrfx/CMakeLists.txt | 9 - modules/hal_nordic/nrfx/nrfx_config.h | 10 +- .../nrfx/nrfx_config_nrf54h20_application.h | 1937 ---------------- .../nrfx/nrfx_config_nrf54h20_ppr.h | 1865 --------------- .../nrfx/nrfx_config_nrf54h20_radiocore.h | 2001 ----------------- 5 files changed, 2 insertions(+), 5820 deletions(-) delete mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_application.h delete mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_ppr.h delete mode 100644 modules/hal_nordic/nrfx/nrfx_config_nrf54h20_radiocore.h diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index eb384046aa6..92aa3962f61 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -36,12 +36,6 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF5340_CPUAPP NRF5340_XXAA_APP zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF5340_CPUAPP NRF5340_XXAA_APPLICATION) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF5340_CPUNET NRF5340_XXAA_NETWORK) zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF5340_CPUNET NRF5340_XXAA_NETWORK) -zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_CPUAPP NRF54H20_XXAA - NRF_APPLICATION) -zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_CPURAD NRF54H20_XXAA - NRF_RADIOCORE) -zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_CPUPPR NRF54H20_XXAA - NRF_PPR) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_ENGA NRF54L15_ENGA_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_ENGA_CPUAPP NRF_APPLICATION) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9120 NRF9120_XXAA) @@ -207,9 +201,6 @@ mdk_svd_ifdef(CONFIG_SOC_NRF52833 nrf52833.svd) mdk_svd_ifdef(CONFIG_SOC_NRF52840 nrf52840.svd) mdk_svd_ifdef(CONFIG_SOC_NRF5340_CPUAPP nrf5340_application.svd) mdk_svd_ifdef(CONFIG_SOC_NRF5340_CPUNET nrf5340_network.svd) -mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUAPP nrf54h20_application.svd) -mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUPPR nrf54h20_ppr.svd) -mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPURAD nrf54h20_radiocore.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUAPP nrf54h20_enga_application.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPUPPR nrf54h20_enga_ppr.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGA_CPURAD nrf54h20_enga_radiocore.svd) diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index d0f2a0555d5..58b9cd2aba7 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -937,22 +937,16 @@ #include #elif defined(NRF5340_XXAA_NETWORK) #include -#elif defined(NRF54H20_XXAA) && defined(NRF_APPLICATION) - #include -#elif defined(NRF54H20_XXAA) && defined(NRF_RADIOCORE) - #include -#elif defined(NRF54H20_XXAA) && defined(NRF_PPR) - #include #elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_APPLICATION) #include #elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_RADIOCORE) #include #elif defined(NRF54H20_ENGA_XXAA) && defined(NRF_PPR) #include -#elif (defined(NRF54L15_XXAA) || defined(NRF54L15_ENGA_XXAA)) && defined(NRF_APPLICATION) - #include #elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) #include +#elif (defined(NRF54L15_XXAA) || defined(NRF54L15_ENGA_XXAA)) && defined(NRF_APPLICATION) + #include #else #error "Unknown device." #endif diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_application.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_application.h deleted file mode 100644 index 5b91d921c7c..00000000000 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_application.h +++ /dev/null @@ -1,1937 +0,0 @@ -/* - * Copyright (c) 2024, Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef NRFX_CONFIG_NRF54H20_APPLICATION_H__ -#define NRFX_CONFIG_NRF54H20_APPLICATION_H__ - -#ifndef NRFX_CONFIG_H__ -#error "This file should not be included directly. Include nrfx_config.h instead." -#endif - -/** - * @brief NRFX_DEFAULT_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_DEFAULT_IRQ_PRIORITY -#define NRFX_DEFAULT_IRQ_PRIORITY 7 -#endif - -/** - * @brief NRFX_BELLBOARD_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD_ENABLED -#define NRFX_BELLBOARD_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_BELLBOARD0_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD0_ENABLED -#define NRFX_BELLBOARD0_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD1_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD1_ENABLED -#define NRFX_BELLBOARD1_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD2_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD2_ENABLED -#define NRFX_BELLBOARD2_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD3_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD3_ENABLED -#define NRFX_BELLBOARD3_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_ENABLED -#define NRFX_COMP_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_CONFIG_LOG_ENABLED -#define NRFX_COMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_COMP_CONFIG_LOG_LEVEL -#define NRFX_COMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_ENABLED -#define NRFX_DPPI_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED -#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL -#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0 -#endif - -/** - * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e -#endif - -/** - * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 -#endif - -/** - * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 -#endif - -/** - * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 -#endif - -/** - * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f -#endif - -/** - * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 -#endif - -/** - * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df -#endif - -/** - * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf -#endif - -/** - * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e -#endif - -/** - * @brief NRFX_EGU_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_EGU_ENABLED -#define NRFX_EGU_ENABLED 0 -#endif - -/** - * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_EGU130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_EGU130_ENABLED -#define NRFX_EGU130_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - * - * Integer value. Minimum: 0. Maximum: 15. - */ -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS -#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED -#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL -#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_GPIOTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE130_ENABLED -#define NRFX_GPIOTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_ENABLED -#define NRFX_GRTC_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED -#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOEN - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOEN -#define NRFX_GRTC_CONFIG_AUTOEN 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOSTART - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOSTART -#define NRFX_GRTC_CONFIG_AUTOSTART 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS - * - * Integer value. - */ -#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS -#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK - */ -#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK -#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000f0 -#endif - -/** - * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED -#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL -#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_LPCOMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_ENABLED -#define NRFX_LPCOMP_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED -#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL -#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_MVDMA_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_MVDMA_ENABLED -#define NRFX_MVDMA_ENABLED 0 -#endif - -/** - * @brief NRFX_MVDMA120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_MVDMA120_ENABLED -#define NRFX_MVDMA120_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_ENABLED -#define NRFX_NFCT_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver. - * - * Integer value. Minimum: 0. Maximum: 5. - */ -#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID -#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED -#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL -#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PDM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_ENABLED -#define NRFX_PDM_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_CONFIG_LOG_ENABLED -#define NRFX_PDM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PDM_CONFIG_LOG_LEVEL -#define NRFX_PDM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_ENABLED -#define NRFX_PRS_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_CONFIG_LOG_ENABLED -#define NRFX_PRS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PRS_CONFIG_LOG_LEVEL -#define NRFX_PRS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_BOX_0_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_0_ENABLED -#define NRFX_PRS_BOX_0_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_1_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_1_ENABLED -#define NRFX_PRS_BOX_1_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_2_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_2_ENABLED -#define NRFX_PRS_BOX_2_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_3_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_3_ENABLED -#define NRFX_PRS_BOX_3_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_4_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_4_ENABLED -#define NRFX_PRS_BOX_4_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_5_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_5_ENABLED -#define NRFX_PRS_BOX_5_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_6_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_6_ENABLED -#define NRFX_PRS_BOX_6_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_7_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_7_ENABLED -#define NRFX_PRS_BOX_7_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_8_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_8_ENABLED -#define NRFX_PRS_BOX_8_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_9_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_9_ENABLED -#define NRFX_PRS_BOX_9_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_ENABLED -#define NRFX_PWM_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_CONFIG_LOG_ENABLED -#define NRFX_PWM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PWM_CONFIG_LOG_LEVEL -#define NRFX_PWM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PWM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM120_ENABLED -#define NRFX_PWM120_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM130_ENABLED -#define NRFX_PWM130_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM131_ENABLED -#define NRFX_PWM131_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM132_ENABLED -#define NRFX_PWM132_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM133_ENABLED -#define NRFX_PWM133_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_ENABLED -#define NRFX_QDEC_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED -#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL -#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_QDEC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC130_ENABLED -#define NRFX_QDEC130_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC131_ENABLED -#define NRFX_QDEC131_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_CONFIG_LOG_ENABLED -#define NRFX_RTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_RTC_CONFIG_LOG_LEVEL -#define NRFX_RTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_RTC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC130_ENABLED -#define NRFX_RTC130_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC131_ENABLED -#define NRFX_RTC131_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_ENABLED -#define NRFX_SAADC_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED -#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL -#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED -#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL -#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM120_ENABLED -#define NRFX_SPIM120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM121_ENABLED -#define NRFX_SPIM121_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM130_ENABLED -#define NRFX_SPIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM131_ENABLED -#define NRFX_SPIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM132_ENABLED -#define NRFX_SPIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM133_ENABLED -#define NRFX_SPIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM134_ENABLED -#define NRFX_SPIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM135_ENABLED -#define NRFX_SPIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM136_ENABLED -#define NRFX_SPIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM137_ENABLED -#define NRFX_SPIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED -#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL -#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIS120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS120_ENABLED -#define NRFX_SPIS120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS130_ENABLED -#define NRFX_SPIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS131_ENABLED -#define NRFX_SPIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS132_ENABLED -#define NRFX_SPIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS133_ENABLED -#define NRFX_SPIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS134_ENABLED -#define NRFX_SPIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS135_ENABLED -#define NRFX_SPIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS136_ENABLED -#define NRFX_SPIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS137_ENABLED -#define NRFX_SPIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_SYSTICK_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SYSTICK_ENABLED -#define NRFX_SYSTICK_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_ENABLED -#define NRFX_TEMP_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED -#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL -#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED -#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL -#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER120_ENABLED -#define NRFX_TIMER120_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER121_ENABLED -#define NRFX_TIMER121_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER130_ENABLED -#define NRFX_TIMER130_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER131_ENABLED -#define NRFX_TIMER131_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER132_ENABLED -#define NRFX_TIMER132_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER133_ENABLED -#define NRFX_TIMER133_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER134_ENABLED -#define NRFX_TIMER134_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER135_ENABLED -#define NRFX_TIMER135_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER136_ENABLED -#define NRFX_TIMER136_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER137_ENABLED -#define NRFX_TIMER137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED -#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL -#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM130_ENABLED -#define NRFX_TWIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM131_ENABLED -#define NRFX_TWIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM132_ENABLED -#define NRFX_TWIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM133_ENABLED -#define NRFX_TWIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM134_ENABLED -#define NRFX_TWIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM135_ENABLED -#define NRFX_TWIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM136_ENABLED -#define NRFX_TWIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM137_ENABLED -#define NRFX_TWIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ENABLED -#define NRFX_TWIS_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED -#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance - * would be initialized only once. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -/** - * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_NO_SYNC_MODE -#define NRFX_TWIS_NO_SYNC_MODE 0 -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL -#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS130_ENABLED -#define NRFX_TWIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS131_ENABLED -#define NRFX_TWIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS132_ENABLED -#define NRFX_TWIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS133_ENABLED -#define NRFX_TWIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS134_ENABLED -#define NRFX_TWIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS135_ENABLED -#define NRFX_TWIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS136_ENABLED -#define NRFX_TWIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS137_ENABLED -#define NRFX_TWIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for - * configuring GPIO pins is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for - * configuring PSEL registers is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking - * of TX transfers. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_TX_LINK -#define NRFX_UARTE_CONFIG_TX_LINK 1 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED -#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 -#endif - -/** - * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED -#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL -#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_UARTE120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE120_ENABLED -#define NRFX_UARTE120_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE130_ENABLED -#define NRFX_UARTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE131_ENABLED -#define NRFX_UARTE131_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE132_ENABLED -#define NRFX_UARTE132_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE133_ENABLED -#define NRFX_UARTE133_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE134_ENABLED -#define NRFX_UARTE134_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE135_ENABLED -#define NRFX_UARTE135_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE136_ENABLED -#define NRFX_UARTE136_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE137_ENABLED -#define NRFX_UARTE137_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_NO_IRQ -#define NRFX_WDT_CONFIG_NO_IRQ 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_LOG_ENABLED -#define NRFX_WDT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_WDT_CONFIG_LOG_LEVEL -#define NRFX_WDT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_WDT010_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT010_ENABLED -#define NRFX_WDT010_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT011_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT011_ENABLED -#define NRFX_WDT011_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT131_ENABLED -#define NRFX_WDT131_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT132_ENABLED -#define NRFX_WDT132_ENABLED 0 -#endif - -#endif /* NRFX_CONFIG_NRF54H20_APPLICATION_H__ */ diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_ppr.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_ppr.h deleted file mode 100644 index 4a4e6c08a8a..00000000000 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_ppr.h +++ /dev/null @@ -1,1865 +0,0 @@ -/* - * Copyright (c) 2024, Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef NRFX_CONFIG_NRF54H20_PPR_H__ -#define NRFX_CONFIG_NRF54H20_PPR_H__ - -#ifndef NRFX_CONFIG_H__ -#error "This file should not be included directly. Include nrfx_config.h instead." -#endif - -/** - * @brief NRFX_DEFAULT_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_DEFAULT_IRQ_PRIORITY -#define NRFX_DEFAULT_IRQ_PRIORITY 0 -#endif - -/** - * @brief NRFX_COMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_ENABLED -#define NRFX_COMP_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_CONFIG_LOG_ENABLED -#define NRFX_COMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_COMP_CONFIG_LOG_LEVEL -#define NRFX_COMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_ENABLED -#define NRFX_DPPI_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED -#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL -#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030 -#endif - -/** - * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e -#endif - -/** - * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 -#endif - -/** - * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 -#endif - -/** - * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 -#endif - -/** - * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 -#endif - -/** - * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df -#endif - -/** - * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf -#endif - -/** - * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e -#endif - -/** - * @brief NRFX_EGU_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_EGU_ENABLED -#define NRFX_EGU_ENABLED 0 -#endif - -/** - * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_EGU130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_EGU130_ENABLED -#define NRFX_EGU130_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - * - * Integer value. Minimum: 0. Maximum: 15. - */ -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS -#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED -#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL -#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_GPIOTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE130_ENABLED -#define NRFX_GPIOTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_ENABLED -#define NRFX_GRTC_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED -#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOEN - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOEN -#define NRFX_GRTC_CONFIG_AUTOEN 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOSTART - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOSTART -#define NRFX_GRTC_CONFIG_AUTOSTART 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS - * - * Integer value. - */ -#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS -#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 2 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK - */ -#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK -#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000c0 -#endif - -/** - * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED -#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL -#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_LPCOMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_ENABLED -#define NRFX_LPCOMP_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED -#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL -#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_MVDMA_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_MVDMA_ENABLED -#define NRFX_MVDMA_ENABLED 0 -#endif - -/** - * @brief NRFX_MVDMA120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_MVDMA120_ENABLED -#define NRFX_MVDMA120_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_ENABLED -#define NRFX_NFCT_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver. - * - * Integer value. Minimum: 0. Maximum: 5. - */ -#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID -#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED -#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL -#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PDM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_ENABLED -#define NRFX_PDM_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_CONFIG_LOG_ENABLED -#define NRFX_PDM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PDM_CONFIG_LOG_LEVEL -#define NRFX_PDM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_ENABLED -#define NRFX_PRS_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_CONFIG_LOG_ENABLED -#define NRFX_PRS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PRS_CONFIG_LOG_LEVEL -#define NRFX_PRS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_BOX_0_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_0_ENABLED -#define NRFX_PRS_BOX_0_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_1_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_1_ENABLED -#define NRFX_PRS_BOX_1_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_2_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_2_ENABLED -#define NRFX_PRS_BOX_2_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_3_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_3_ENABLED -#define NRFX_PRS_BOX_3_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_4_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_4_ENABLED -#define NRFX_PRS_BOX_4_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_5_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_5_ENABLED -#define NRFX_PRS_BOX_5_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_6_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_6_ENABLED -#define NRFX_PRS_BOX_6_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_7_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_7_ENABLED -#define NRFX_PRS_BOX_7_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_8_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_8_ENABLED -#define NRFX_PRS_BOX_8_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_9_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_9_ENABLED -#define NRFX_PRS_BOX_9_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_ENABLED -#define NRFX_PWM_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_CONFIG_LOG_ENABLED -#define NRFX_PWM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PWM_CONFIG_LOG_LEVEL -#define NRFX_PWM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PWM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM120_ENABLED -#define NRFX_PWM120_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM130_ENABLED -#define NRFX_PWM130_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM131_ENABLED -#define NRFX_PWM131_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM132_ENABLED -#define NRFX_PWM132_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM133_ENABLED -#define NRFX_PWM133_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_ENABLED -#define NRFX_QDEC_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED -#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL -#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_QDEC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC130_ENABLED -#define NRFX_QDEC130_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC131_ENABLED -#define NRFX_QDEC131_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_CONFIG_LOG_ENABLED -#define NRFX_RTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_RTC_CONFIG_LOG_LEVEL -#define NRFX_RTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_RTC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC130_ENABLED -#define NRFX_RTC130_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC131_ENABLED -#define NRFX_RTC131_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_ENABLED -#define NRFX_SAADC_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED -#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL -#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED -#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL -#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM120_ENABLED -#define NRFX_SPIM120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM121_ENABLED -#define NRFX_SPIM121_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM130_ENABLED -#define NRFX_SPIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM131_ENABLED -#define NRFX_SPIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM132_ENABLED -#define NRFX_SPIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM133_ENABLED -#define NRFX_SPIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM134_ENABLED -#define NRFX_SPIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM135_ENABLED -#define NRFX_SPIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM136_ENABLED -#define NRFX_SPIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM137_ENABLED -#define NRFX_SPIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED -#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL -#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIS120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS120_ENABLED -#define NRFX_SPIS120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS130_ENABLED -#define NRFX_SPIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS131_ENABLED -#define NRFX_SPIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS132_ENABLED -#define NRFX_SPIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS133_ENABLED -#define NRFX_SPIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS134_ENABLED -#define NRFX_SPIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS135_ENABLED -#define NRFX_SPIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS136_ENABLED -#define NRFX_SPIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS137_ENABLED -#define NRFX_SPIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_ENABLED -#define NRFX_TEMP_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED -#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL -#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED -#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL -#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER120_ENABLED -#define NRFX_TIMER120_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER121_ENABLED -#define NRFX_TIMER121_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER130_ENABLED -#define NRFX_TIMER130_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER131_ENABLED -#define NRFX_TIMER131_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER132_ENABLED -#define NRFX_TIMER132_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER133_ENABLED -#define NRFX_TIMER133_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER134_ENABLED -#define NRFX_TIMER134_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER135_ENABLED -#define NRFX_TIMER135_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER136_ENABLED -#define NRFX_TIMER136_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER137_ENABLED -#define NRFX_TIMER137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED -#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL -#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM130_ENABLED -#define NRFX_TWIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM131_ENABLED -#define NRFX_TWIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM132_ENABLED -#define NRFX_TWIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM133_ENABLED -#define NRFX_TWIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM134_ENABLED -#define NRFX_TWIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM135_ENABLED -#define NRFX_TWIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM136_ENABLED -#define NRFX_TWIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM137_ENABLED -#define NRFX_TWIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ENABLED -#define NRFX_TWIS_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED -#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance - * would be initialized only once. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -/** - * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_NO_SYNC_MODE -#define NRFX_TWIS_NO_SYNC_MODE 0 -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL -#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS130_ENABLED -#define NRFX_TWIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS131_ENABLED -#define NRFX_TWIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS132_ENABLED -#define NRFX_TWIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS133_ENABLED -#define NRFX_TWIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS134_ENABLED -#define NRFX_TWIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS135_ENABLED -#define NRFX_TWIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS136_ENABLED -#define NRFX_TWIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS137_ENABLED -#define NRFX_TWIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for - * configuring GPIO pins is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for - * configuring PSEL registers is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking - * of TX transfers. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_TX_LINK -#define NRFX_UARTE_CONFIG_TX_LINK 1 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED -#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 -#endif - -/** - * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED -#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL -#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_UARTE120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE120_ENABLED -#define NRFX_UARTE120_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE130_ENABLED -#define NRFX_UARTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE131_ENABLED -#define NRFX_UARTE131_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE132_ENABLED -#define NRFX_UARTE132_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE133_ENABLED -#define NRFX_UARTE133_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE134_ENABLED -#define NRFX_UARTE134_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE135_ENABLED -#define NRFX_UARTE135_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE136_ENABLED -#define NRFX_UARTE136_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE137_ENABLED -#define NRFX_UARTE137_ENABLED 0 -#endif - -/** - * @brief NRFX_VEVIF_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_VEVIF_ENABLED -#define NRFX_VEVIF_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 3. - */ -#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_NO_IRQ -#define NRFX_WDT_CONFIG_NO_IRQ 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_LOG_ENABLED -#define NRFX_WDT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_WDT_CONFIG_LOG_LEVEL -#define NRFX_WDT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_WDT131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT131_ENABLED -#define NRFX_WDT131_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT132_ENABLED -#define NRFX_WDT132_ENABLED 0 -#endif - -#endif /* NRFX_CONFIG_NRF54H20_PPR_H__ */ diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_radiocore.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_radiocore.h deleted file mode 100644 index 274073e6a38..00000000000 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_radiocore.h +++ /dev/null @@ -1,2001 +0,0 @@ -/* - * Copyright (c) 2024, Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef NRFX_CONFIG_NRF54H20_RADIOCORE_H__ -#define NRFX_CONFIG_NRF54H20_RADIOCORE_H__ - -#ifndef NRFX_CONFIG_H__ -#error "This file should not be included directly. Include nrfx_config.h instead." -#endif - -/** - * @brief NRFX_DEFAULT_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_DEFAULT_IRQ_PRIORITY -#define NRFX_DEFAULT_IRQ_PRIORITY 7 -#endif - -/** - * @brief NRFX_BELLBOARD_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD_ENABLED -#define NRFX_BELLBOARD_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_BELLBOARD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_BELLBOARD0_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD0_ENABLED -#define NRFX_BELLBOARD0_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD1_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD1_ENABLED -#define NRFX_BELLBOARD1_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD2_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD2_ENABLED -#define NRFX_BELLBOARD2_ENABLED 0 -#endif - -/** - * @brief NRFX_BELLBOARD3_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_BELLBOARD3_ENABLED -#define NRFX_BELLBOARD3_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_ENABLED -#define NRFX_COMP_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_COMP_CONFIG_LOG_ENABLED -#define NRFX_COMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_COMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_COMP_CONFIG_LOG_LEVEL -#define NRFX_COMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_ENABLED -#define NRFX_DPPI_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED -#define NRFX_DPPI_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_DPPI_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL -#define NRFX_DPPI_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI020_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI030_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000f0 -#endif - -/** - * @brief NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000001e -#endif - -/** - * @brief NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000020 -#endif - -/** - * @brief NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000040 -#endif - -/** - * @brief NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000081 -#endif - -/** - * @brief NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI020_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI030_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000f -#endif - -/** - * @brief NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI131_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000ff -#endif - -/** - * @brief NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI132_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI133_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000e1 -#endif - -/** - * @brief NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI134_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000df -#endif - -/** - * @brief NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI135_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000bf -#endif - -/** - * @brief NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_DPPI136_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000007e -#endif - -/** - * @brief NRFX_EGU_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_EGU_ENABLED -#define NRFX_EGU_ENABLED 0 -#endif - -/** - * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_EGU020_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_EGU020_ENABLED -#define NRFX_EGU020_ENABLED 0 -#endif - -/** - * @brief NRFX_EGU130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_EGU130_ENABLED -#define NRFX_EGU130_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS - * - * Integer value. Minimum: 0. Maximum: 15. - */ -#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS -#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 1 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED -#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL -#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_GPIOTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GPIOTE130_ENABLED -#define NRFX_GPIOTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_ENABLED -#define NRFX_GRTC_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED -#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOEN - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOEN -#define NRFX_GRTC_CONFIG_AUTOEN 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOSTART - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOSTART -#define NRFX_GRTC_CONFIG_AUTOSTART 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS - * - * Integer value. - */ -#ifndef NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS -#define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS 4 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK - */ -#ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK -#define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f00 -#endif - -/** - * @brief NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GRTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_LOG_ENABLED -#define NRFX_GRTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_GRTC_CONFIG_LOG_LEVEL -#define NRFX_GRTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000030 -#endif - -/** - * @brief NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_PUB_CONFIG_ALLOWED_CHANNELS_MASK 0x0000000c -#endif - -/** - * @brief NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x000000c0 -#endif - -/** - * @brief NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT120_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0 -#endif - -/** - * @brief NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK - */ -#ifndef NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK -#define NRFX_IPCT130_SUB_CONFIG_ALLOWED_CHANNELS_MASK 0x00000003 -#endif - -/** - * @brief NRFX_LPCOMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_ENABLED -#define NRFX_LPCOMP_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED -#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL -#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_MVDMA_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_MVDMA_ENABLED -#define NRFX_MVDMA_ENABLED 0 -#endif - -/** - * @brief NRFX_MVDMA120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_MVDMA120_ENABLED -#define NRFX_MVDMA120_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_ENABLED -#define NRFX_NFCT_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver. - * - * Integer value. Minimum: 0. Maximum: 5. - */ -#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID -#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED -#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_NFCT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL -#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PDM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_ENABLED -#define NRFX_PDM_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PDM_CONFIG_LOG_ENABLED -#define NRFX_PDM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PDM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PDM_CONFIG_LOG_LEVEL -#define NRFX_PDM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_ENABLED -#define NRFX_PRS_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_CONFIG_LOG_ENABLED -#define NRFX_PRS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PRS_CONFIG_LOG_LEVEL -#define NRFX_PRS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PRS_BOX_0_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_0_ENABLED -#define NRFX_PRS_BOX_0_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_1_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_1_ENABLED -#define NRFX_PRS_BOX_1_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_2_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_2_ENABLED -#define NRFX_PRS_BOX_2_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_3_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_3_ENABLED -#define NRFX_PRS_BOX_3_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_4_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_4_ENABLED -#define NRFX_PRS_BOX_4_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_5_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_5_ENABLED -#define NRFX_PRS_BOX_5_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_6_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_6_ENABLED -#define NRFX_PRS_BOX_6_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_7_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_7_ENABLED -#define NRFX_PRS_BOX_7_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_8_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_8_ENABLED -#define NRFX_PRS_BOX_8_ENABLED 0 -#endif - -/** - * @brief NRFX_PRS_BOX_9_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PRS_BOX_9_ENABLED -#define NRFX_PRS_BOX_9_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_ENABLED -#define NRFX_PWM_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM_CONFIG_LOG_ENABLED -#define NRFX_PWM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_PWM_CONFIG_LOG_LEVEL -#define NRFX_PWM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_PWM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM120_ENABLED -#define NRFX_PWM120_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM130_ENABLED -#define NRFX_PWM130_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM131_ENABLED -#define NRFX_PWM131_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM132_ENABLED -#define NRFX_PWM132_ENABLED 0 -#endif - -/** - * @brief NRFX_PWM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_PWM133_ENABLED -#define NRFX_PWM133_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_ENABLED -#define NRFX_QDEC_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED -#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL -#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_QDEC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC130_ENABLED -#define NRFX_QDEC130_ENABLED 0 -#endif - -/** - * @brief NRFX_QDEC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_QDEC131_ENABLED -#define NRFX_QDEC131_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC_CONFIG_LOG_ENABLED -#define NRFX_RTC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_RTC_CONFIG_LOG_LEVEL -#define NRFX_RTC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_RTC130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC130_ENABLED -#define NRFX_RTC130_ENABLED 0 -#endif - -/** - * @brief NRFX_RTC131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_RTC131_ENABLED -#define NRFX_RTC131_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_ENABLED -#define NRFX_SAADC_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED -#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SAADC_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL -#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED -#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL -#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIM120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM120_ENABLED -#define NRFX_SPIM120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM121_ENABLED -#define NRFX_SPIM121_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM130_ENABLED -#define NRFX_SPIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM131_ENABLED -#define NRFX_SPIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM132_ENABLED -#define NRFX_SPIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM133_ENABLED -#define NRFX_SPIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM134_ENABLED -#define NRFX_SPIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM135_ENABLED -#define NRFX_SPIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM136_ENABLED -#define NRFX_SPIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIM137_ENABLED -#define NRFX_SPIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED -#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL -#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_SPIS120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS120_ENABLED -#define NRFX_SPIS120_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS130_ENABLED -#define NRFX_SPIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS131_ENABLED -#define NRFX_SPIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS132_ENABLED -#define NRFX_SPIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS133_ENABLED -#define NRFX_SPIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS134_ENABLED -#define NRFX_SPIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS135_ENABLED -#define NRFX_SPIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS136_ENABLED -#define NRFX_SPIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_SPIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SPIS137_ENABLED -#define NRFX_SPIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_SYSTICK_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_SYSTICK_ENABLED -#define NRFX_SYSTICK_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_ENABLED -#define NRFX_TEMP_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED -#define NRFX_TEMP_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TEMP_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL -#define NRFX_TEMP_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED -#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL -#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TIMER020_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER020_ENABLED -#define NRFX_TIMER020_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER021_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER021_ENABLED -#define NRFX_TIMER021_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER022_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER022_ENABLED -#define NRFX_TIMER022_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER120_ENABLED -#define NRFX_TIMER120_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER121_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER121_ENABLED -#define NRFX_TIMER121_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER130_ENABLED -#define NRFX_TIMER130_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER131_ENABLED -#define NRFX_TIMER131_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER132_ENABLED -#define NRFX_TIMER132_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER133_ENABLED -#define NRFX_TIMER133_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER134_ENABLED -#define NRFX_TIMER134_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER135_ENABLED -#define NRFX_TIMER135_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER136_ENABLED -#define NRFX_TIMER136_ENABLED 0 -#endif - -/** - * @brief NRFX_TIMER137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TIMER137_ENABLED -#define NRFX_TIMER137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED -#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL -#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIM130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM130_ENABLED -#define NRFX_TWIM130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM131_ENABLED -#define NRFX_TWIM131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM132_ENABLED -#define NRFX_TWIM132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM133_ENABLED -#define NRFX_TWIM133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM134_ENABLED -#define NRFX_TWIM134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM135_ENABLED -#define NRFX_TWIM135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM136_ENABLED -#define NRFX_TWIM136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIM137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIM137_ENABLED -#define NRFX_TWIM137_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ENABLED -#define NRFX_TWIS_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED -#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance - * would be initialized only once. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -/** - * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS_NO_SYNC_MODE -#define NRFX_TWIS_NO_SYNC_MODE 0 -#endif - -/** - * @brief NRFX_TWIS_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL -#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_TWIS130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS130_ENABLED -#define NRFX_TWIS130_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS131_ENABLED -#define NRFX_TWIS131_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS132_ENABLED -#define NRFX_TWIS132_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS133_ENABLED -#define NRFX_TWIS133_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS134_ENABLED -#define NRFX_TWIS134_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS135_ENABLED -#define NRFX_TWIS135_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS136_ENABLED -#define NRFX_TWIS136_ENABLED 0 -#endif - -/** - * @brief NRFX_TWIS137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_TWIS137_ENABLED -#define NRFX_TWIS137_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG - If enabled, support for - * configuring GPIO pins is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_GPIO_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG - If enabled, support for - * configuring PSEL registers is removed from the driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG -#define NRFX_UARTE_CONFIG_SKIP_PSEL_CONFIG 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_TX_LINK - If enabled, driver supports linking - * of TX transfers. - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_TX_LINK -#define NRFX_UARTE_CONFIG_TX_LINK 1 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_RX_CACHE_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_RX_CACHE_ENABLED -#define NRFX_UARTE_CONFIG_RX_CACHE_ENABLED 1 -#endif - -/** - * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED -#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL -#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_UARTE120_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE120_ENABLED -#define NRFX_UARTE120_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE130_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE130_ENABLED -#define NRFX_UARTE130_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE131_ENABLED -#define NRFX_UARTE131_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE132_ENABLED -#define NRFX_UARTE132_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE133_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE133_ENABLED -#define NRFX_UARTE133_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE134_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE134_ENABLED -#define NRFX_UARTE134_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE135_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE135_ENABLED -#define NRFX_UARTE135_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE136_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE136_ENABLED -#define NRFX_UARTE136_ENABLED 0 -#endif - -/** - * @brief NRFX_UARTE137_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_UARTE137_ENABLED -#define NRFX_UARTE137_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - * - * Integer value. Minimum: 0. Maximum: 7. - */ -#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY -#endif - -/** - * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_NO_IRQ -#define NRFX_WDT_CONFIG_NO_IRQ 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT_CONFIG_LOG_ENABLED -#define NRFX_WDT_CONFIG_LOG_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT_CONFIG_LOG_LEVEL - * - * Integer value. - * Supported values: - * - Off = 0 - * - Error = 1 - * - Warning = 2 - * - Info = 3 - * - Debug = 4 - */ -#ifndef NRFX_WDT_CONFIG_LOG_LEVEL -#define NRFX_WDT_CONFIG_LOG_LEVEL 3 -#endif - -/** - * @brief NRFX_WDT010_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT010_ENABLED -#define NRFX_WDT010_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT011_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT011_ENABLED -#define NRFX_WDT011_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT131_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT131_ENABLED -#define NRFX_WDT131_ENABLED 0 -#endif - -/** - * @brief NRFX_WDT132_ENABLED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_WDT132_ENABLED -#define NRFX_WDT132_ENABLED 0 -#endif - -#endif /* NRFX_CONFIG_NRF54H20_RADIOCORE_H__ */ From 395fa26639f6a2b74a308257747dbf51e03de600 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:26 +0200 Subject: [PATCH 2256/2402] Revert "[nrf fromtree] modules: hal_nordic: nrfx: include config for nrf54l15" This reverts commit b13898244d1e6b2d033ae9a3e355e57057339956. Signed-off-by: Gerard Marull-Paretas --- modules/hal_nordic/nrfx/nrfx_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index 58b9cd2aba7..206fa2ed5dc 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -945,7 +945,7 @@ #include #elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) #include -#elif (defined(NRF54L15_XXAA) || defined(NRF54L15_ENGA_XXAA)) && defined(NRF_APPLICATION) +#elif defined(NRF54L15_ENGA_XXAA) && defined(NRF_APPLICATION) #include #else #error "Unknown device." From b60ed7900a335e287134853d4fe4dc8298d4ea69 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:27 +0200 Subject: [PATCH 2257/2402] Revert "[nrf fromtree] dts: nordic: Add initial support for nRF54H20" This reverts commit e1ac501f97385e95f120a27508ad59585ddc9970. Signed-off-by: Gerard Marull-Paretas --- dts/arm/nordic/nrf54h20_cpuapp.dtsi | 51 - dts/arm/nordic/nrf54h20_cpurad.dtsi | 51 - dts/common/nordic/nrf54h20.dtsi | 948 ------------------ dts/riscv/nordic/nrf54h20_cpuppr.dtsi | 48 - .../misc/nordic-nrf-ficr-nrf54h20.h | 85 -- 5 files changed, 1183 deletions(-) delete mode 100644 dts/arm/nordic/nrf54h20_cpuapp.dtsi delete mode 100644 dts/arm/nordic/nrf54h20_cpurad.dtsi delete mode 100644 dts/common/nordic/nrf54h20.dtsi delete mode 100644 dts/riscv/nordic/nrf54h20_cpuppr.dtsi delete mode 100644 include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h diff --git a/dts/arm/nordic/nrf54h20_cpuapp.dtsi b/dts/arm/nordic/nrf54h20_cpuapp.dtsi deleted file mode 100644 index d82c69262c0..00000000000 --- a/dts/arm/nordic/nrf54h20_cpuapp.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -cpu: &cpuapp {}; -systick: &cpuapp_systick {}; -nvic: &cpuapp_nvic {}; -cpuppr_vevif: &cpuppr_vevif_remote {}; - -/delete-node/ &cpuppr; -/delete-node/ &cpurad; -/delete-node/ &cpurad_peripherals; -/delete-node/ &cpurad_ppb; -/delete-node/ &cpurad_ram0; - -/ { - soc { - compatible = "simple-bus"; - interrupt-parent = <&cpuapp_nvic>; - ranges; - }; -}; - -&cpuapp_ppb { - compatible = "simple-bus"; - ranges; -}; - -&cpusec_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpuapp_bellboard { - compatible = "nordic,nrf-bellboard-local"; -}; - -&cpurad_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&gpiote130 { - interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; -}; - -&grtc { - interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>; -}; diff --git a/dts/arm/nordic/nrf54h20_cpurad.dtsi b/dts/arm/nordic/nrf54h20_cpurad.dtsi deleted file mode 100644 index 2f463f2d427..00000000000 --- a/dts/arm/nordic/nrf54h20_cpurad.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -cpu: &cpurad {}; -systick: &cpurad_systick {}; -nvic: &cpurad_nvic {}; -cpuppr_vevif: &cpuppr_vevif_remote {}; - -/delete-node/ &cpuapp; -/delete-node/ &cpuapp_peripherals; -/delete-node/ &cpuapp_ppb; -/delete-node/ &cpuapp_ram0; -/delete-node/ &cpuppr; - -/ { - soc { - compatible = "simple-bus"; - interrupt-parent = <&cpurad_nvic>; - ranges; - }; -}; - -&cpurad_ppb { - compatible = "simple-bus"; - ranges; -}; - -&cpusec_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpuapp_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpurad_bellboard { - compatible = "nordic,nrf-bellboard-local"; -}; - -&gpiote130 { - interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; -}; - -&grtc { - interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>; -}; diff --git a/dts/common/nordic/nrf54h20.dtsi b/dts/common/nordic/nrf54h20.dtsi deleted file mode 100644 index 78e4c5b6549..00000000000 --- a/dts/common/nordic/nrf54h20.dtsi +++ /dev/null @@ -1,948 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#include - -/* Domain IDs. Can be used to specify channel links in IPCT nodes. */ -#define NRF_DOMAIN_ID_APPLICATION 2 -#define NRF_DOMAIN_ID_RADIOCORE 3 -#define NRF_DOMAIN_ID_GLOBALFAST 12 -#define NRF_DOMAIN_ID_GLOBALSLOW 13 - -/delete-node/ &sw_pwm; - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpuapp: cpu@2 { - compatible = "arm,cortex-m33"; - reg = <2>; - device_type = "cpu"; - clock-frequency = ; - }; - - cpurad: cpu@3 { - compatible = "arm,cortex-m33"; - reg = <3>; - device_type = "cpu"; - clock-frequency = ; - }; - - cpuppr: cpu@d { - compatible = "nordic,vpr"; - reg = <13>; - device_type = "cpu"; - clock-frequency = ; - riscv,isa = "rv32emc"; - nordic,bus-width = <32>; - - cpuppr_vevif_local: mailbox { - compatible = "nordic,nrf-vevif-local"; - status = "disabled"; - interrupt-parent = <&cpuppr_clic>; - interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, - <1 NRF_DEFAULT_IRQ_PRIORITY>, - <2 NRF_DEFAULT_IRQ_PRIORITY>, - <3 NRF_DEFAULT_IRQ_PRIORITY>, - <4 NRF_DEFAULT_IRQ_PRIORITY>, - <5 NRF_DEFAULT_IRQ_PRIORITY>, - <6 NRF_DEFAULT_IRQ_PRIORITY>, - <7 NRF_DEFAULT_IRQ_PRIORITY>, - <8 NRF_DEFAULT_IRQ_PRIORITY>, - <9 NRF_DEFAULT_IRQ_PRIORITY>, - <10 NRF_DEFAULT_IRQ_PRIORITY>, - <11 NRF_DEFAULT_IRQ_PRIORITY>, - <12 NRF_DEFAULT_IRQ_PRIORITY>, - <13 NRF_DEFAULT_IRQ_PRIORITY>, - <14 NRF_DEFAULT_IRQ_PRIORITY>, - <15 NRF_DEFAULT_IRQ_PRIORITY>; - #mbox-cells = <1>; - nordic,tasks = <16>; - nordic,tasks-mask = <0xfffffff0>; - }; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - - cpurad_uicr_ext: memory@e1ff000 { - reg = <0xe1ff000 DT_SIZE_K(2)>; - }; - - cpuapp_uicr_ext: memory@e1ff800 { - reg = <0xe1ff800 DT_SIZE_K(2)>; - }; - }; - - clocks { - fll16m: fll16m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = ; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - - mram1x: mram@e000000 { - compatible = "nordic,mram"; - reg = <0xe000000 DT_SIZE_K(2048)>; - erase-block-size = <4096>; - write-block-size = <16>; - }; - - cpuapp_uicr: uicr@fff8000 { - compatible = "nordic,nrf-uicr-v2"; - reg = <0xfff8000 DT_SIZE_K(2)>; - domain = <2>; - ptr-ext-uicr = <&cpuapp_uicr_ext>; - }; - - cpurad_uicr: uicr@fffa000 { - compatible = "nordic,nrf-uicr-v2"; - reg = <0xfffa000 DT_SIZE_K(2)>; - domain = <3>; - ptr-ext-uicr = <&cpurad_uicr_ext>; - }; - - ficr: ficr@fffe000 { - compatible = "nordic,nrf-ficr"; - reg = <0xfffe000 DT_SIZE_K(2)>; - #nordic,ficr-cells = <1>; - }; - - cpuapp_ram0: sram@22000000 { - compatible = "mmio-sram"; - reg = <0x22000000 DT_SIZE_K(32)>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000000 0x8000>; - }; - - cpurad_ram0: sram@23000000 { - compatible = "mmio-sram"; - reg = <0x23000000 DT_SIZE_K(192)>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x23000000 0x30000>; - }; - - cpuapp_peripherals: peripheral@52000000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x52000000 0x1000000>; - - cpuapp_hsfll: clock@d000 { - compatible = "nordic,nrf-hsfll"; - #clock-cells = <0>; - reg = <0xd000 0x1000>; - clocks = <&fll16m>; - clock-frequency = ; - nordic,ficrs = - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; - nordic,ficr-names = "vsup", "coarse", "fine"; - }; - - cpuapp_ipct: ipct@13000 { - compatible = "nordic,nrf-ipct-local"; - reg = <0x13000 0x1000>; - status = "disabled"; - channels = <4>; - interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, - <65 NRF_DEFAULT_IRQ_PRIORITY>; - }; - }; - - cpurad_peripherals: peripheral@53000000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53000000 0x1000000>; - - cpurad_hsfll: clock@d000 { - compatible = "nordic,nrf-hsfll"; - #clock-cells = <0>; - reg = <0xd000 0x1000>; - clocks = <&fll16m>; - clock-frequency = ; - nordic,ficrs = - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; - nordic,ficr-names = "vsup", "coarse", "fine"; - }; - - dppic020: dppic@22000 { - compatible = "nordic,nrf-dppic-local"; - reg = <0x22000 0x1000>; - status = "disabled"; - }; - - cpurad_ipct: ipct@24000 { - compatible = "nordic,nrf-ipct-local"; - reg = <0x24000 0x1000>; - status = "disabled"; - channels = <8>; - interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, - <65 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - egu020: egu@25000 { - compatible = "nordic,nrf-egu"; - reg = <0x25000 0x1000>; - status = "disabled"; - interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - timer020: timer@28000 { - compatible = "nordic,nrf-timer"; - reg = <0x28000 0x1000>; - status = "disabled"; - cc-num = <8>; - interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer021: timer@29000 { - compatible = "nordic,nrf-timer"; - reg = <0x29000 0x1000>; - status = "disabled"; - cc-num = <8>; - interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer022: timer@2a000 { - compatible = "nordic,nrf-timer"; - reg = <0x2a000 0x1000>; - status = "disabled"; - cc-num = <8>; - interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - rtc: rtc@2b000 { - compatible = "nordic,nrf-rtc"; - reg = <0x2b000 0x1000>; - status = "disabled"; - cc-num = <4>; - clock-frequency = <32768>; - interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>; - prescaler = <1>; - }; - - radio: radio@2c000 { - compatible = "nordic,nrf-radio"; - reg = <0x2c000 0x1000>; - status = "disabled"; - ble-2mbps-supported; - ble-coded-phy-supported; - dfe-supported; - ieee802154-supported; - interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>; - - cpurad_ieee802154: ieee802154 { - compatible = "nordic,nrf-ieee802154"; - status = "disabled"; - }; - }; - - ecb030: ecb@3b000 { - compatible = "nordic,nrf-ecb"; - reg = <0x3b000 0x1000>; - interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>; - status = "disabled"; - }; - - ccm031: ccm@3c000 { - compatible = "nordic,nrf-ccm"; - reg = <0x3c000 0x1000>; - interrupts = <60 NRF_DEFAULT_IRQ_PRIORITY>; - status = "disabled"; - }; - - ecb031: ecb@3d000 { - compatible = "nordic,nrf-ecb"; - reg = <0x3d000 0x1000>; - status = "disabled"; - interrupts = <61 NRF_DEFAULT_IRQ_PRIORITY>; - }; - }; - - global_peripherals: peripheral@5f000000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5f000000 0x1000000>; - - cpusec_bellboard: mailbox@99000 { - reg = <0x99000 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - }; - - cpuapp_bellboard: mailbox@9a000 { - reg = <0x9a000 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - }; - - cpurad_bellboard: mailbox@9b000 { - reg = <0x9b000 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - }; - - ipct120: ipct@8d1000 { - compatible = "nordic,nrf-ipct-global"; - reg = <0x8d1000 0x1000>; - status = "disabled"; - channels = <8>; - global-domain-id = <12>; - }; - - dppic120: dppic@8e1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x8e1000 0x1000>; - status = "disabled"; - }; - - timer120: timer@8e2000 { - compatible = "nordic,nrf-timer"; - reg = <0x8e2000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer121: timer@8e3000 { - compatible = "nordic,nrf-timer"; - reg = <0x8e3000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - spi120: spi@8e6000 { - compatible = "nordic,nrf-spim"; - reg = <0x8e6000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart120: uart@8e6000 { - compatible = "nordic,nrf-uarte"; - reg = <0x8e6000 0x1000>; - status = "disabled"; - interrupts = <229 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - spi121: spi@8e7000 { - compatible = "nordic,nrf-spim"; - reg = <0x8e7000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - cpuppr_vpr: vpr@908000 { - compatible = "nordic,nrf-vpr-coprocessor"; - reg = <0x908000 0x1000>; - status = "disabled"; - cpu = <13>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x908000 0x4000>; - - cpuppr_vevif_remote: mailbox@0 { - compatible = "nordic,nrf-vevif-remote"; - reg = <0x0 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - nordic,tasks = <16>; - nordic,tasks-mask = <0xfffffff0>; - }; - - cpuppr_clic: interrupt-controller@1000 { - compatible = "nordic,nrf-clic"; - reg = <0x1000 0x3000>; - status = "disabled"; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - }; - }; - - ipct130: ipct@921000 { - compatible = "nordic,nrf-ipct-global"; - reg = <0x921000 0x1000>; - status = "disabled"; - channels = <8>; - global-domain-id = <13>; - }; - - dppic130: dppic@922000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x922000 0x1000>; - status = "disabled"; - }; - - rtc130: rtc@928000 { - compatible = "nordic,nrf-rtc"; - reg = <0x928000 0x1000>; - status = "disabled"; - cc-num = <4>; - clock-frequency = <32768>; - interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>; - prescaler = <1>; - }; - - rtc131: rtc@929000 { - compatible = "nordic,nrf-rtc"; - reg = <0x929000 0x1000>; - status = "disabled"; - cc-num = <4>; - clock-frequency = <32768>; - interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>; - prescaler = <1>; - }; - - wdt131: watchdog@92b000 { - compatible = "nordic,nrf-wdt"; - reg = <0x92b000 0x1000>; - status = "disabled"; - interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - wdt132: watchdog@92c000 { - compatible = "nordic,nrf-wdt"; - reg = <0x92c000 0x1000>; - status = "disabled"; - interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - gpiote130: gpiote@934000 { - compatible = "nordic,nrf-gpiote"; - reg = <0x934000 0x1000>; - status = "disabled"; - instance = <130>; - }; - - gpio0: gpio@938000 { - compatible = "nordic,nrf-gpio"; - reg = <0x938000 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - gpiote-instance = <&gpiote130>; - ngpios = <12>; - port = <0>; - }; - - gpio1: gpio@938200 { - compatible = "nordic,nrf-gpio"; - reg = <0x938200 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - gpiote-instance = <&gpiote130>; - ngpios = <12>; - port = <1>; - }; - - gpio2: gpio@938400 { - compatible = "nordic,nrf-gpio"; - reg = <0x938400 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - gpiote-instance = <&gpiote130>; - ngpios = <12>; - port = <2>; - }; - - gpio6: gpio@938c00 { - compatible = "nordic,nrf-gpio"; - reg = <0x938c00 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - ngpios = <14>; - port = <6>; - }; - - gpio7: gpio@938e00 { - compatible = "nordic,nrf-gpio"; - reg = <0x938e00 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - ngpios = <8>; - port = <7>; - }; - - gpio9: gpio@939200 { - compatible = "nordic,nrf-gpio"; - reg = <0x939200 0x200>; - status = "disabled"; - #gpio-cells = <2>; - gpio-controller; - gpiote-instance = <&gpiote130>; - ngpios = <6>; - port = <9>; - }; - - dppic131: dppic@981000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x981000 0x1000>; - status = "disabled"; - }; - - comp: comparator@983000 { - compatible = "nordic,nrf-comp"; - reg = <0x983000 0x1000>; - status = "disabled"; - interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>; - #io-channel-cells = <1>; - }; - - temp: temperature-sensor@984000 { - compatible = "nordic,nrf-temp"; - reg = <0x984000 0x1000>; - interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>; - status = "disabled"; - }; - - nfct: nfct@985000 { - compatible = "nordic,nrf-nfct"; - reg = <0x985000 0x1000>; - status = "disabled"; - interrupts = <389 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - dppic132: dppic@991000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x991000 0x1000>; - status = "disabled"; - }; - - qdec130: qdec@994000 { - compatible = "nordic,nrf-qdec"; - reg = <0x994000 0x1000>; - status = "disabled"; - interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - qdec131: qdec@995000 { - compatible = "nordic,nrf-qdec"; - reg = <0x995000 0x1000>; - status = "disabled"; - interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - grtc: grtc@99c000 { - compatible = "nordic,nrf-grtc"; - reg = <0x99c000 0x1000>; - status = "disabled"; - cc-num = <16>; - }; - - dppic133: dppic@9a1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9a1000 0x1000>; - status = "disabled"; - }; - - timer130: timer@9a2000 { - compatible = "nordic,nrf-timer"; - reg = <0x9a2000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer131: timer@9a3000 { - compatible = "nordic,nrf-timer"; - reg = <0x9a3000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - i2c130: i2c@9a5000 { - compatible = "nordic,nrf-twim"; - reg = <0x9a5000 0x1000>; - status = "disabled"; - interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi130: spi@9a5000 { - compatible = "nordic,nrf-spim"; - reg = <0x9a5000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart130: uart@9a5000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9a5000 0x1000>; - status = "disabled"; - interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - i2c131: i2c@9a6000 { - compatible = "nordic,nrf-twim"; - reg = <0x9a6000 0x1000>; - status = "disabled"; - interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi131: spi@9a6000 { - compatible = "nordic,nrf-spim"; - reg = <0x9a6000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart131: uart@9a6000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9a6000 0x1000>; - status = "disabled"; - interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - dppic134: dppic@9b1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9b1000 0x1000>; - status = "disabled"; - }; - - timer132: timer@9b2000 { - compatible = "nordic,nrf-timer"; - reg = <0x9b2000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer133: timer@9b3000 { - compatible = "nordic,nrf-timer"; - reg = <0x9b3000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - i2c132: i2c@9b5000 { - compatible = "nordic,nrf-twim"; - reg = <0x9b5000 0x1000>; - status = "disabled"; - interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi132: spi@9b5000 { - compatible = "nordic,nrf-spim"; - reg = <0x9b5000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart132: uart@9b5000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9b5000 0x1000>; - status = "disabled"; - interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - i2c133: i2c@9b6000 { - compatible = "nordic,nrf-twim"; - reg = <0x9b6000 0x1000>; - status = "disabled"; - interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi133: spi@9b6000 { - compatible = "nordic,nrf-spim"; - reg = <0x9b6000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart133: uart@9b6000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9b6000 0x1000>; - status = "disabled"; - interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - dppic135: dppic@9c1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9c1000 0x1000>; - status = "disabled"; - }; - - timer134: timer@9c2000 { - compatible = "nordic,nrf-timer"; - reg = <0x9c2000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer135: timer@9c3000 { - compatible = "nordic,nrf-timer"; - reg = <0x9c3000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - i2c134: i2c@9c5000 { - compatible = "nordic,nrf-twim"; - reg = <0x9c5000 0x1000>; - status = "disabled"; - interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi134: spi@9c5000 { - compatible = "nordic,nrf-spim"; - reg = <0x9c5000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart134: uart@9c5000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9c5000 0x1000>; - status = "disabled"; - interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - i2c135: i2c@9c6000 { - compatible = "nordic,nrf-twim"; - reg = <0x9c6000 0x1000>; - status = "disabled"; - interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi135: spi@9c6000 { - compatible = "nordic,nrf-spim"; - reg = <0x9c6000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart135: uart@9c6000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9c6000 0x1000>; - status = "disabled"; - interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - dppic136: dppic@9d1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9d1000 0x1000>; - status = "disabled"; - }; - - timer136: timer@9d2000 { - compatible = "nordic,nrf-timer"; - reg = <0x9d2000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - timer137: timer@9d3000 { - compatible = "nordic,nrf-timer"; - reg = <0x9d3000 0x1000>; - status = "disabled"; - cc-num = <6>; - interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>; - max-bit-width = <32>; - prescaler = <0>; - }; - - i2c136: i2c@9d5000 { - compatible = "nordic,nrf-twim"; - reg = <0x9d5000 0x1000>; - status = "disabled"; - interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi136: spi@9d5000 { - compatible = "nordic,nrf-spim"; - reg = <0x9d5000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart136: uart@9d5000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9d5000 0x1000>; - status = "disabled"; - interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; - }; - - i2c137: i2c@9d6000 { - compatible = "nordic,nrf-twim"; - reg = <0x9d6000 0x1000>; - status = "disabled"; - interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; - easydma-maxcnt-bits = <15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi137: spi@9d6000 { - compatible = "nordic,nrf-spim"; - reg = <0x9d6000 0x1000>; - status = "disabled"; - easydma-maxcnt-bits = <15>; - interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; - max-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart137: uart@9d6000 { - compatible = "nordic,nrf-uarte"; - reg = <0x9d6000 0x1000>; - status = "disabled"; - interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; - }; - }; - }; - - cpuapp_ppb: cpuapp-ppb-bus { - #address-cells = <1>; - #size-cells = <1>; - - cpuapp_systick: timer@e000e010 { - compatible = "arm,armv8m-systick"; - reg = <0xe000e010 0x10>; - status = "disabled"; - }; - - cpuapp_nvic: interrupt-controller@e000e100 { - compatible = "arm,v8m-nvic"; - reg = <0xe000e100 0xc00>; - arm,num-irq-priority-bits = <3>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - }; - }; - - cpurad_ppb: cpurad-ppb-bus { - #address-cells = <1>; - #size-cells = <1>; - - cpurad_systick: timer@e000e010 { - compatible = "arm,armv8m-systick"; - reg = <0xe000e010 0x10>; - status = "disabled"; - }; - - cpurad_nvic: interrupt-controller@e000e100 { - compatible = "arm,v8m-nvic"; - reg = <0xe000e100 0xc00>; - arm,num-irq-priority-bits = <3>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - }; - }; -}; diff --git a/dts/riscv/nordic/nrf54h20_cpuppr.dtsi b/dts/riscv/nordic/nrf54h20_cpuppr.dtsi deleted file mode 100644 index d74147bc04b..00000000000 --- a/dts/riscv/nordic/nrf54h20_cpuppr.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -cpu: &cpuppr {}; -clic: &cpuppr_clic {}; -cpuppr_vevif: &cpuppr_vevif_local {}; - -/delete-node/ &cpuapp; -/delete-node/ &cpuapp_peripherals; -/delete-node/ &cpuapp_ppb; -/delete-node/ &cpuapp_ram0; -/delete-node/ &cpurad; -/delete-node/ &cpurad_peripherals; -/delete-node/ &cpurad_ppb; -/delete-node/ &cpurad_ram0; - -/ { - soc { - compatible = "simple-bus"; - interrupt-parent = <&cpuppr_clic>; - ranges; - }; -}; - -&cpusec_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpuapp_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpurad_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&gpiote130 { - interrupts = <104 NRF_DEFAULT_IRQ_PRIORITY>; -}; - -&grtc { - interrupts = <108 NRF_DEFAULT_IRQ_PRIORITY>; -}; diff --git a/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h b/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h deleted file mode 100644 index 4ebd8fb6614..00000000000 --- a/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -/* autogenerated using Nordic HAL utils/gen_offsets.py script */ - -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_H_ - -#define NRF_FICR_BLE_ADDRTYPE 0x00CU -#define NRF_FICR_BLE_ADDR_0 0x010U -#define NRF_FICR_BLE_ADDR_1 0x014U -#define NRF_FICR_BLE_ER_0 0x018U -#define NRF_FICR_BLE_ER_1 0x01CU -#define NRF_FICR_BLE_ER_2 0x020U -#define NRF_FICR_BLE_ER_3 0x024U -#define NRF_FICR_BLE_IR_0 0x028U -#define NRF_FICR_BLE_IR_1 0x02CU -#define NRF_FICR_BLE_IR_2 0x030U -#define NRF_FICR_BLE_IR_3 0x034U -#define NRF_FICR_NFC_TAGHEADER_0 0x040U -#define NRF_FICR_NFC_TAGHEADER_1 0x044U -#define NRF_FICR_NFC_TAGHEADER_2 0x048U -#define NRF_FICR_NFC_TAGHEADER_3 0x04CU -#define NRF_FICR_INFO_CONFIGID 0x050U -#define NRF_FICR_INFO_PART 0x054U -#define NRF_FICR_INFO_VARIANT 0x058U -#define NRF_FICR_INFO_PACKAGE 0x05CU -#define NRF_FICR_INFO_RAM 0x060U -#define NRF_FICR_INFO_MRAM 0x064U -#define NRF_FICR_INFO_CODEPAGESIZE 0x068U -#define NRF_FICR_INFO_CODESIZE 0x06CU -#define NRF_FICR_INFO_DEVICETYPE 0x070U -#define NRF_FICR_TRIM_GLOBAL_SAADC_CAL_0 0x388U -#define NRF_FICR_TRIM_GLOBAL_SAADC_CAL_1 0x38CU -#define NRF_FICR_TRIM_GLOBAL_SAADC_CAL_2 0x390U -#define NRF_FICR_TRIM_GLOBAL_SAADC_CALREF 0x394U -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_0 0x398U -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_1 0x39CU -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_2 0x3A0U -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_3 0x3A4U -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_4 0x3A8U -#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_5 0x3ACU -#define NRF_FICR_TRIM_GLOBAL_NFCT_BIASCFG 0x3B4U -#define NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE 0x3B8U -#define NRF_FICR_TRIM_GLOBAL_COMP_REFTRIM 0x3C0U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP 0x3C8U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0 0x3CCU -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_1 0x3D0U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_2 0x3D4U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_3 0x3D8U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_4 0x3DCU -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_5 0x3E0U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0 0x3E4U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_1 0x3E8U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_2 0x3ECU -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_3 0x3F0U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_4 0x3F4U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_5 0x3F8U -#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_TCOEF 0x3FCU -#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_0_TRIM 0x400U -#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_1_TRIM 0x404U -#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_2_TRIM 0x408U -#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_3_TRIM 0x40CU -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP 0x410U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_0 0x414U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1 0x418U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_2 0x41CU -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_3 0x420U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_4 0x424U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_5 0x428U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_0 0x42CU -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1 0x430U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_2 0x434U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_3 0x438U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_4 0x43CU -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_5 0x440U -#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_TCOEF 0x444U -#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_0_TRIM 0x448U -#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_1_TRIM 0x44CU -#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_2_TRIM 0x450U -#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_3_TRIM 0x454U - -#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_H_ */ From ef3a37e71d4157b33e2a476e89de27a08f49f04a Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:27 +0200 Subject: [PATCH 2258/2402] Revert "[nrf fromlist] soc: nordic: Add initial support for nRF54H20" This reverts commit 32eaa669cbd1c32af67cf81466dba899223303a5. Signed-off-by: Gerard Marull-Paretas --- .../nrf54h/Kconfig.defconfig.nrf54h20_cpuapp | 6 +++--- .../nrf54h/Kconfig.defconfig.nrf54h20_cpurad | 6 +++--- .../Kconfig.defconfig.nrf54h20_enga_cpuapp | 17 ----------------- .../Kconfig.defconfig.nrf54h20_enga_cpurad | 17 ----------------- soc/arm/nordic_nrf/nrf54h/Kconfig.soc | 16 ---------------- .../nordic_nrf/common/vpr/Kconfig.defconfig | 2 +- .../nrf54h/Kconfig.defconfig.nrf54h20_cpuppr | 15 --------------- soc/riscv/nordic_nrf/nrf54h/Kconfig.soc | 4 ---- 8 files changed, 7 insertions(+), 76 deletions(-) delete mode 100644 soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp delete mode 100644 soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad delete mode 100644 soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuppr diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp index 007035c0f48..d90f87c0b89 100644 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp +++ b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp @@ -3,10 +3,10 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -if SOC_NRF54H20_CPUAPP +if SOC_NRF54H20_ENGA_CPUAPP config SOC - default "nrf54h20_cpuapp" + default "nrf54h20_enga_cpuapp" config NUM_IRQS default 471 @@ -14,4 +14,4 @@ config NUM_IRQS config NRF_REGTOOL_GENERATE_UICR default y -endif # SOC_NRF54H20_CPUAPP +endif # SOC_NRF54H20_ENGA_CPUAPP diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpurad b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpurad index 0f9e4c7e102..6aae8c3a105 100644 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpurad +++ b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpurad @@ -3,10 +3,10 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -if SOC_NRF54H20_CPURAD +if SOC_NRF54H20_ENGA_CPURAD config SOC - default "nrf54h20_cpurad" + default "nrf54h20_enga_cpurad" config NUM_IRQS default 471 @@ -14,4 +14,4 @@ config NUM_IRQS config NRF_REGTOOL_GENERATE_UICR default y -endif # SOC_NRF54H20_CPURAD +endif # SOC_NRF54H20_ENGA_CPURAD diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp deleted file mode 100644 index d90f87c0b89..00000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF54H20 Application MCU - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF54H20_ENGA_CPUAPP - -config SOC - default "nrf54h20_enga_cpuapp" - -config NUM_IRQS - default 471 - -config NRF_REGTOOL_GENERATE_UICR - default y - -endif # SOC_NRF54H20_ENGA_CPUAPP diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad deleted file mode 100644 index 6aae8c3a105..00000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF54H20 Radio MCU - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF54H20_ENGA_CPURAD - -config SOC - default "nrf54h20_enga_cpurad" - -config NUM_IRQS - default 471 - -config NRF_REGTOOL_GENERATE_UICR - default y - -endif # SOC_NRF54H20_ENGA_CPURAD diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.soc b/soc/arm/nordic_nrf/nrf54h/Kconfig.soc index 32256a809a9..9c065e79eaf 100644 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.soc +++ b/soc/arm/nordic_nrf/nrf54h/Kconfig.soc @@ -12,22 +12,6 @@ if SOC_NRF54H20 choice prompt "nRF54H20 MCU Selection" -config SOC_NRF54H20_CPUAPP - bool "nRF54H20 CPUAPP" - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CPU_HAS_FPU - -config SOC_NRF54H20_CPURAD - bool "nRF54H20 CPURAD" - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CPU_HAS_FPU - config SOC_NRF54H20_ENGA_CPUAPP bool "nRF54H20 ENGA CPUAPP" select CPU_HAS_ARM_MPU diff --git a/soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig b/soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig index a89593170f6..f0014455b3a 100644 --- a/soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig +++ b/soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig @@ -5,7 +5,7 @@ CPU_PATH := $(dt_nodelabel_path,cpu) CPU_ID := $(dt_node_reg_addr_int,$(CPU_PATH)) config RV_BOOT_HART - default $(CPU_ID) if SOC_NRF54H20_ENGA_CPUPPR + default $(CPU_ID) config RISCV_MCAUSE_EXCEPTION_MASK default 0xFFF diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuppr b/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuppr deleted file mode 100644 index caecd6ad0eb..00000000000 --- a/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuppr +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF54H20_CPUPPR - -config SOC - default "nrf54h20_cpuppr" - -config NUM_IRQS - default 496 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -endif # SOC_NRF54H20_CPUPPR diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc b/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc index 47138277fce..760e05a0e64 100644 --- a/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc +++ b/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc @@ -10,10 +10,6 @@ if SOC_NRF54H20 choice prompt "nRF54Hx MCU Selection" -config SOC_NRF54H20_CPUPPR - bool "nRF54H20 CPUPPR" - select RISCV - config SOC_NRF54H20_ENGA_CPUPPR bool "nRF54H20 ENGA CPUPPR" depends on RISCV_CORE_NORDIC_VPR From e0199c587a78b3b095c41d7dc8b76006459143d6 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:27 +0200 Subject: [PATCH 2259/2402] Revert "[nrf fromtree] drivers: pinctrl_nrf: Set clockpin bitfield when necessary" This reverts commit bfc54995e2c166f73838411a0048ba229869ca85. Signed-off-by: Gerard Marull-Paretas --- drivers/pinctrl/pinctrl_nrf.c | 34 ---------------------------------- 1 file changed, 34 deletions(-) diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c index 0bf09e5e460..3ff28922835 100644 --- a/drivers/pinctrl/pinctrl_nrf.c +++ b/drivers/pinctrl/pinctrl_nrf.c @@ -40,19 +40,16 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = { #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uart) #define NRF_PSEL_UART(reg, line) ((NRF_UART_Type *)reg)->PSEL##line #elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uarte) -#include #define NRF_PSEL_UART(reg, line) ((NRF_UARTE_Type *)reg)->PSEL.line #endif #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spi) #define NRF_PSEL_SPIM(reg, line) ((NRF_SPI_Type *)reg)->PSEL##line #elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spim) -#include #define NRF_PSEL_SPIM(reg, line) ((NRF_SPIM_Type *)reg)->PSEL.line #endif #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spis) -#include #if defined(NRF51) #define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL##line #else @@ -67,7 +64,6 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = { #define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL.line #endif #elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twim) -#include #define NRF_PSEL_TWIM(reg, line) ((NRF_TWIM_Type *)reg)->PSEL.line #endif @@ -101,9 +97,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uint32_t write = NO_WRITE; nrf_gpio_pin_dir_t dir; nrf_gpio_pin_input_t input; -#if NRF_GPIO_HAS_CLOCKPIN - bool clockpin = false; -#endif if (drive_idx < ARRAY_SIZE(drive_modes)) { drive = drive_modes[drive_idx]; @@ -122,9 +115,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, write = 1U; dir = NRF_GPIO_PIN_DIR_OUTPUT; input = NRF_GPIO_PIN_INPUT_DISCONNECT; -#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_UARTE_CLOCKPIN_TXD_NEEDED) - clockpin = true; -#endif break; case NRF_FUN_UART_RX: NRF_PSEL_UART(reg, RXD) = psel; @@ -136,9 +126,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, write = 1U; dir = NRF_GPIO_PIN_DIR_OUTPUT; input = NRF_GPIO_PIN_INPUT_DISCONNECT; -#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_UARTE_CLOCKPIN_RTS_NEEDED) - clockpin = true; -#endif break; case NRF_FUN_UART_CTS: NRF_PSEL_UART(reg, CTS) = psel; @@ -152,18 +139,12 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, write = 0U; dir = NRF_GPIO_PIN_DIR_OUTPUT; input = NRF_GPIO_PIN_INPUT_CONNECT; -#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIM_CLOCKPIN_SCK_NEEDED) - clockpin = true; -#endif break; case NRF_FUN_SPIM_MOSI: NRF_PSEL_SPIM(reg, MOSI) = psel; write = 0U; dir = NRF_GPIO_PIN_DIR_OUTPUT; input = NRF_GPIO_PIN_INPUT_DISCONNECT; -#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIM_CLOCKPIN_MOSI_NEEDED) - clockpin = true; -#endif break; case NRF_FUN_SPIM_MISO: NRF_PSEL_SPIM(reg, MISO) = psel; @@ -176,9 +157,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, NRF_PSEL_SPIS(reg, SCK) = psel; dir = NRF_GPIO_PIN_DIR_INPUT; input = NRF_GPIO_PIN_INPUT_CONNECT; -#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIS_CLOCKPIN_SCK_NEEDED) - clockpin = true; -#endif break; case NRF_FUN_SPIS_MOSI: NRF_PSEL_SPIS(reg, MOSI) = psel; @@ -189,9 +167,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, NRF_PSEL_SPIS(reg, MISO) = psel; dir = NRF_GPIO_PIN_DIR_INPUT; input = NRF_GPIO_PIN_INPUT_DISCONNECT; -#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIS_CLOCKPIN_MISO_NEEDED) - clockpin = true; -#endif break; case NRF_FUN_SPIS_CSN: NRF_PSEL_SPIS(reg, CSN) = psel; @@ -213,9 +188,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, } dir = NRF_GPIO_PIN_DIR_INPUT; input = NRF_GPIO_PIN_INPUT_CONNECT; -#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_TWIM_CLOCKPIN_SCL_NEEDED) - clockpin = true; -#endif break; case NRF_FUN_TWIM_SDA: NRF_PSEL_TWIM(reg, SDA) = psel; @@ -224,9 +196,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, } dir = NRF_GPIO_PIN_DIR_INPUT; input = NRF_GPIO_PIN_INPUT_CONNECT; -#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_TWIM_CLOCKPIN_SDA_NEEDED) - clockpin = true; -#endif break; #endif /* defined(NRF_PSEL_TWIM) */ #if defined(NRF_PSEL_I2S) @@ -380,9 +349,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]), drive, NRF_GPIO_PIN_NOSENSE); -#if NRF_GPIO_HAS_CLOCKPIN - nrf_gpio_pin_clock_set(pin, clockpin); -#endif } } From 6157ceb6c091e559e3d82295e4c0f3b5eca8d09a Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:27 +0200 Subject: [PATCH 2260/2402] Revert "[nrf fromtree] modules: hal_nordic: Align nRF54H20 nrfx_configs with nrfx templates" This reverts commit bdde95118bce09fa620c83d9b8bff6959077a2fb. Signed-off-by: Gerard Marull-Paretas --- .../nrfx_config_nrf54h20_enga_application.h | 27 ----------------- .../nrfx/nrfx_config_nrf54h20_enga_ppr.h | 29 +------------------ .../nrfx_config_nrf54h20_enga_radiocore.h | 27 ----------------- 3 files changed, 1 insertion(+), 82 deletions(-) diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h index af74d9d3dc3..e6c79341b9a 100644 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_application.h @@ -331,33 +331,6 @@ #define NRFX_GRTC_ENABLED 0 #endif -/** - * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED -#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOEN - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOEN -#define NRFX_GRTC_CONFIG_AUTOEN 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOSTART - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOSTART -#define NRFX_GRTC_CONFIG_AUTOSTART 0 -#endif - /** * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS * diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h index 65b3e2fa958..369fe18a81f 100644 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_ppr.h @@ -18,7 +18,7 @@ * Integer value. Minimum: 0. Maximum: 3. */ #ifndef NRFX_DEFAULT_IRQ_PRIORITY -#define NRFX_DEFAULT_IRQ_PRIORITY 0 +#define NRFX_DEFAULT_IRQ_PRIORITY 3 #endif /** @@ -277,33 +277,6 @@ #define NRFX_GRTC_ENABLED 0 #endif -/** - * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED -#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOEN - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOEN -#define NRFX_GRTC_CONFIG_AUTOEN 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOSTART - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOSTART -#define NRFX_GRTC_CONFIG_AUTOSTART 0 -#endif - /** * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS * diff --git a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h index ca7bf3aca63..7b9a1c4b733 100644 --- a/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h +++ b/modules/hal_nordic/nrfx/nrfx_config_nrf54h20_enga_radiocore.h @@ -385,33 +385,6 @@ #define NRFX_GRTC_ENABLED 0 #endif -/** - * @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED -#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOEN - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOEN -#define NRFX_GRTC_CONFIG_AUTOEN 0 -#endif - -/** - * @brief NRFX_GRTC_CONFIG_AUTOSTART - * - * Boolean. Accepted values: 0 and 1. - */ -#ifndef NRFX_GRTC_CONFIG_AUTOSTART -#define NRFX_GRTC_CONFIG_AUTOSTART 0 -#endif - /** * @brief NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS * From 5d4ea06efc348e0dc59dd9508f915658b972e2ce Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:27 +0200 Subject: [PATCH 2261/2402] Revert "[nrf fromtree] drivers: nrf_qspi_nor: Handle anomaly 159 on nRF5340" This reverts commit 4580e21835ab345eff1ab258d60058e97e003b72. Signed-off-by: Gerard Marull-Paretas --- drivers/flash/nrf_qspi_nor.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/flash/nrf_qspi_nor.c b/drivers/flash/nrf_qspi_nor.c index c2ac5f3f3ba..c0e8c397d8e 100644 --- a/drivers/flash/nrf_qspi_nor.c +++ b/drivers/flash/nrf_qspi_nor.c @@ -21,7 +21,6 @@ LOG_MODULE_REGISTER(qspi_nor, CONFIG_FLASH_LOG_LEVEL); #include "spi_nor.h" #include "jesd216.h" #include "flash_priv.h" -#include #include #include #include @@ -102,11 +101,6 @@ BUILD_ASSERT(INST_0_SCK_FREQUENCY >= (NRF_QSPI_BASE_CLOCK_FREQ / 16), /* For requested SCK >= 96 MHz, use HFCLK192M / 1 / (2*1) = 96 MHz */ #define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_1 #define INST_0_SCK_CFG NRF_QSPI_FREQ_DIV1 -/* If anomaly 159 is to be prevented, only /1 divider can be used. */ -#elif NRF53_ERRATA_159_ENABLE_WORKAROUND -#define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_1 -#define INST_0_SCK_CFG (DIV_ROUND_UP(NRF_QSPI_BASE_CLOCK_FREQ, \ - INST_0_SCK_FREQUENCY) - 1) #elif (INST_0_SCK_FREQUENCY >= (NRF_QSPI_BASE_CLOCK_FREQ / 2)) /* For 96 MHz > SCK >= 48 MHz, use HFCLK192M / 2 / (2*1) = 48 MHz */ #define BASE_CLOCK_DIV NRF_CLOCK_HFCLK_DIV_2 @@ -121,13 +115,6 @@ BUILD_ASSERT(INST_0_SCK_FREQUENCY >= (NRF_QSPI_BASE_CLOCK_FREQ / 16), #define INST_0_SCK_CFG (DIV_ROUND_UP(NRF_QSPI_BASE_CLOCK_FREQ / 2, \ INST_0_SCK_FREQUENCY) - 1) #endif -/* After the base clock divider is changed, some time is needed for the new - * setting to take effect. This value specifies the delay (in microseconds) - * to be applied to ensure that the clock is ready when the QSPI operation - * starts. It was measured with a logic analyzer (unfortunately, the nRF5340 - * specification does not provide any numbers in this regard). - */ -#define BASE_CLOCK_SWITCH_DELAY_US 7 #else /* @@ -243,12 +230,6 @@ static inline int qspi_get_zephyr_ret_code(nrfx_err_t res) return -EINVAL; case NRFX_ERROR_INVALID_STATE: return -ECANCELED; -#if NRF53_ERRATA_159_ENABLE_WORKAROUND - case NRFX_ERROR_FORBIDDEN: - LOG_ERR("nRF5340 anomaly 159 conditions detected"); - LOG_ERR("Set the CPU clock to 64 MHz before starting QSPI operation"); - return -ECANCELED; -#endif case NRFX_ERROR_BUSY: case NRFX_ERROR_TIMEOUT: default: @@ -281,7 +262,6 @@ static inline void qspi_clock_div_change(void) * before a QSPI transfer is performed. */ nrf_clock_hfclk192m_div_set(NRF_CLOCK, BASE_CLOCK_DIV); - k_busy_wait(BASE_CLOCK_SWITCH_DELAY_US); #endif } From 5e80e9ec6a437ff6b48d43ccd3041b13628c7231 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:28 +0200 Subject: [PATCH 2262/2402] Revert "[nrf fromtree] manifest: hal_nordic: update revision to have nrfx 3.4.0 release" This reverts commit 3c4c757e6f0a1df5de4b0f285b1dcf4ab67429e4. Signed-off-by: Gerard Marull-Paretas --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 9c375a568fe..f9cf79db073 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: 13ac55b5b52c905642e9c54f069109d188aa5840 + revision: 5470822384781624efb2fda28cbc6a895a227677 path: modules/hal/nordic groups: - hal From d44f9d41d265acb2f73754b64af6aa794c3214ec Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:28 +0200 Subject: [PATCH 2263/2402] Revert "[nrf fromlist] soc: nordic: vpr: always select HAS_FLASH_LOAD_OFFSET" This reverts commit 5dd838f21312d6bc88c2acc51d96f8f4938abefe. Signed-off-by: Gerard Marull-Paretas --- soc/riscv/nordic_nrf/common/vpr/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/riscv/nordic_nrf/common/vpr/Kconfig b/soc/riscv/nordic_nrf/common/vpr/Kconfig index baef3432a90..70ac63e7204 100644 --- a/soc/riscv/nordic_nrf/common/vpr/Kconfig +++ b/soc/riscv/nordic_nrf/common/vpr/Kconfig @@ -14,6 +14,6 @@ config RISCV_CORE_NORDIC_VPR select RISCV_ISA_EXT_ZIFENCEI select RISCV_SOC_HAS_ISR_STACKING select RISCV_SOC_CONTEXT_SAVE - select HAS_FLASH_LOAD_OFFSET + select HAS_FLASH_LOAD_OFFSET if XIP help Enable support for the RISC-V Nordic VPR core. From d770be6302e845c4f34186a9b9d7358158205869 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:28 +0200 Subject: [PATCH 2264/2402] Revert "[nrf noup] samples: smp_svr: configuration for nrf54l15" This reverts commit a55a68f01811d66b52ce9d0e82744d78792db3c1. Signed-off-by: Gerard Marull-Paretas --- samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml index 373c3acccb9..a13270e5845 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml +++ b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml @@ -12,11 +12,9 @@ tests: - nrf52840dk_nrf52840 - pinnacle_100_dvk - mg100 - - nrf54l15pdk_nrf54l15_cpuapp integration_platforms: - nrf52dk_nrf52832 - nrf52840dk_nrf52840 - - nrf54l15pdk_nrf54l15_cpuapp sample.mcumgr.smp_svr.udp: extra_args: OVERLAY_CONFIG="overlay-udp.conf" platform_allow: frdm_k64f From 2c72c281f8f9afb8d0c2630f93d06347f92e2080 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:28 +0200 Subject: [PATCH 2265/2402] Revert "[nrf fromtree] modules: hal_nordic: nrfx: propagate new configs to nrfx" This reverts commit 55663b1e4975a97626257a4feb67a6909800826c. Signed-off-by: Gerard Marull-Paretas --- modules/hal_nordic/nrfx/CMakeLists.txt | 2 -- soc/arm/nordic_nrf/nrf54l/Kconfig.soc | 5 +++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index 92aa3962f61..285293722bb 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -168,8 +168,6 @@ if(CONFIG_SOC_NRF54L15) endif() zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG NRF_SKIP_CLOCK_CONFIGURATION) -zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_DISABLE_FICR_TRIMCNF NRF_DISABLE_FICR_TRIMCNF) -zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE NRF_SKIP_GLITCHDETECTOR_DISABLE) if(CONFIG_SOC_SERIES_NRF54LX AND CONFIG_NRFX_DPPI) zephyr_library_sources(${HELPERS_DIR}/nrfx_gppi_dppi_ppib_lumos.c) diff --git a/soc/arm/nordic_nrf/nrf54l/Kconfig.soc b/soc/arm/nordic_nrf/nrf54l/Kconfig.soc index f8eadd1388d..18c2517df92 100644 --- a/soc/arm/nordic_nrf/nrf54l/Kconfig.soc +++ b/soc/arm/nordic_nrf/nrf54l/Kconfig.soc @@ -37,11 +37,12 @@ config SOC_NRF54LX_DISABLE_FICR_TRIMCNF help Disable trimming of the device. When the device is trimmed it will copy all the trimming values from FICR into the target - addresses. + addresses. When TF-M is enabled it will trim the device before + booting this image. config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE bool "Skip disabling glitch detector" - default y if TRUSTED_EXECUTION_NONSECURE + default n help With this option, the glitch detector is not disabled during system initialization. The CPU runs with the default state of glitch detector. From 096eb373623bf5a244274e2f5cab84e0c693e60d Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:28 +0200 Subject: [PATCH 2266/2402] Revert "[nrf fromtree] soc: nordic: nrf54l: add two new Kconfig options" This reverts commit f03e194923c1403b9cb9a423d6d2b5d9cf5553f3. Signed-off-by: Gerard Marull-Paretas --- soc/arm/nordic_nrf/nrf54l/Kconfig.soc | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/soc/arm/nordic_nrf/nrf54l/Kconfig.soc b/soc/arm/nordic_nrf/nrf54l/Kconfig.soc index 18c2517df92..915b1e4b2d2 100644 --- a/soc/arm/nordic_nrf/nrf54l/Kconfig.soc +++ b/soc/arm/nordic_nrf/nrf54l/Kconfig.soc @@ -31,22 +31,6 @@ config SOC_NRF54LX_SKIP_CLOCK_CONFIG With this option, the CPU clock frequency is not set during system initialization. The CPU runs with the default, hardware-selected frequency. -config SOC_NRF54LX_DISABLE_FICR_TRIMCNF - bool "Disable trimming of the device" - default y if TRUSTED_EXECUTION_NONSECURE - help - Disable trimming of the device. When the device is trimmed it - will copy all the trimming values from FICR into the target - addresses. When TF-M is enabled it will trim the device before - booting this image. - -config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE - bool "Skip disabling glitch detector" - default n - help - With this option, the glitch detector is not disabled during system initialization. - The CPU runs with the default state of glitch detector. - config SOC_NRF_FORCE_CONSTLAT bool "Force constant-latency mode" help From f1b95e4ddd3cc87c96bc2cc76f62190c0eb9e4d0 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:29 +0200 Subject: [PATCH 2267/2402] Revert "[nrf fromlist] soc: nordic: Refactor soc_secure.h" This reverts commit a1ff51de6be0cf34387a1e6fea3811196768101d. Signed-off-by: Gerard Marull-Paretas --- drivers/hwinfo/hwinfo_nrf.c | 12 +---- drivers/ieee802154/ieee802154_nrf5.c | 11 ----- soc/arm/nordic_nrf/common/soc_secure.h | 64 +++++++++++++------------- 3 files changed, 33 insertions(+), 54 deletions(-) diff --git a/drivers/hwinfo/hwinfo_nrf.c b/drivers/hwinfo/hwinfo_nrf.c index 8b644f2f60e..4375cf05b2f 100644 --- a/drivers/hwinfo/hwinfo_nrf.c +++ b/drivers/hwinfo/hwinfo_nrf.c @@ -7,17 +7,12 @@ #include #include #include +#include #include #ifndef CONFIG_BOARD_QEMU_CORTEX_M0 #include #endif - -#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && defined(NRF_FICR_S) #include -#else -#include -#endif - struct nrf_uid { uint32_t id[2]; }; @@ -27,12 +22,7 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) struct nrf_uid dev_id; uint32_t deviceid[2]; -#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && defined(NRF_FICR_S) soc_secure_read_deviceid(deviceid); -#else - deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR, 0); - deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR, 1); -#endif dev_id.id[0] = sys_cpu_to_be32(deviceid[1]); dev_id.id[1] = sys_cpu_to_be32(deviceid[0]); diff --git a/drivers/ieee802154/ieee802154_nrf5.c b/drivers/ieee802154/ieee802154_nrf5.c index 4cbdd9eb607..67b5431e9cc 100644 --- a/drivers/ieee802154/ieee802154_nrf5.c +++ b/drivers/ieee802154/ieee802154_nrf5.c @@ -25,13 +25,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME); #include #include - -#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && defined(NRF_FICR_S) #include -#else -#include -#endif - #include #include #include @@ -126,12 +120,7 @@ static void nrf5_get_eui64(uint8_t *mac) mac[index++] = (IEEE802154_NRF5_VENDOR_OUI >> 8) & 0xff; mac[index++] = IEEE802154_NRF5_VENDOR_OUI & 0xff; -#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && defined(NRF_FICR_S) soc_secure_read_deviceid(deviceid); -#else - deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR, 0); - deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR, 1); -#endif factoryAddress = (uint64_t)deviceid[EUI64_ADDR_HIGH] << 32; factoryAddress |= deviceid[EUI64_ADDR_LOW]; diff --git a/soc/arm/nordic_nrf/common/soc_secure.h b/soc/arm/nordic_nrf/common/soc_secure.h index 28d18e9b4bb..d38d66ab488 100644 --- a/soc/arm/nordic_nrf/common/soc_secure.h +++ b/soc/arm/nordic_nrf/common/soc_secure.h @@ -9,44 +9,20 @@ #include #if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) -int soc_secure_mem_read(void *dst, void *src, size_t len); #if NRF_GPIO_HAS_SEL void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_sel_t mcu); #endif -#else /* defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ -static inline int soc_secure_mem_read(void *dst, void *src, size_t len) -{ - (void)memcpy(dst, src, len); - return 0; -} -#if NRF_GPIO_HAS_SEL -static inline void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_sel_t mcu) -{ - nrf_gpio_pin_control_select(pin_number, mcu); -} -#endif /* NRF_GPIO_HAS_SEL */ - -#endif /* defined CONFIG_TRUSTED_EXECUTION_NONSECURE */ - -/* Include these soc_secure_* functions only when the FICR is mapped as secure only */ -#if defined(NRF_FICR_S) -#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) -static inline void soc_secure_read_deviceid(uint32_t deviceid[2]) -{ - int err; +int soc_secure_mem_read(void *dst, void *src, size_t len); - err = soc_secure_mem_read(deviceid, (void *)&NRF_FICR_S->INFO.DEVICEID, - 2 * sizeof(uint32_t)); - __ASSERT(err == 0, "Secure read error (%d)", err); -} #if defined(CONFIG_SOC_HFXO_CAP_INTERNAL) static inline uint32_t soc_secure_read_xosc32mtrim(void) { uint32_t xosc32mtrim; int err; - err = soc_secure_mem_read(&xosc32mtrim, (void *)&NRF_FICR_S->XOSC32MTRIM, + err = soc_secure_mem_read(&xosc32mtrim, + (void *)&NRF_FICR_S->XOSC32MTRIM, sizeof(xosc32mtrim)); __ASSERT(err == 0, "Secure read error (%d)", err); @@ -54,18 +30,42 @@ static inline uint32_t soc_secure_read_xosc32mtrim(void) } #endif /* defined(CONFIG_SOC_HFXO_CAP_INTERNAL) */ -#else /* defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ static inline void soc_secure_read_deviceid(uint32_t deviceid[2]) { - deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR_S, 0); - deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR_S, 1); + int err; + + err = soc_secure_mem_read(deviceid, + (void *)&NRF_FICR_S->INFO.DEVICEID, + 2 * sizeof(uint32_t)); + __ASSERT(err == 0, "Secure read error (%d)", err); +} + +#else /* defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ + +static inline int soc_secure_mem_read(void *dst, void *src, size_t len) +{ + (void)memcpy(dst, src, len); + return 0; +} + +#if NRF_GPIO_HAS_SEL +static inline void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, + nrf_gpio_pin_sel_t mcu) +{ + nrf_gpio_pin_control_select(pin_number, mcu); } +#endif /* NRF_GPIO_HAS_SEL */ + #if defined(CONFIG_SOC_HFXO_CAP_INTERNAL) static inline uint32_t soc_secure_read_xosc32mtrim(void) { - return NRF_FICR_S->XOSC32MTRIM; + return NRF_FICR->XOSC32MTRIM; } #endif /* defined(CONFIG_SOC_HFXO_CAP_INTERNAL) */ +static inline void soc_secure_read_deviceid(uint32_t deviceid[2]) +{ + deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR, 0); + deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR, 1); +} #endif /* defined CONFIG_TRUSTED_EXECUTION_NONSECURE */ -#endif /* defined(NRF_FICR_S) */ From 89abb6e59ed99923ea974f1370a67dfc9ef34e3f Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:29 +0200 Subject: [PATCH 2268/2402] Revert "[nrf fromtree] soc: nordic: nrf54l: Remove redundant option" This reverts commit 3b2bdcf3c698238a40ce79fcc580c27d41b56768. Signed-off-by: Gerard Marull-Paretas --- soc/arm/nordic_nrf/nrf54l/Kconfig.soc | 6 ++++++ soc/arm/nordic_nrf/nrf54l/soc.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/soc/arm/nordic_nrf/nrf54l/Kconfig.soc b/soc/arm/nordic_nrf/nrf54l/Kconfig.soc index 915b1e4b2d2..c42c8cfc9b3 100644 --- a/soc/arm/nordic_nrf/nrf54l/Kconfig.soc +++ b/soc/arm/nordic_nrf/nrf54l/Kconfig.soc @@ -47,6 +47,12 @@ config SOC_NRF54L_VREG_MAIN_DCDC config SOC_NRF54L_NORMAL_VOLTAGE_MODE bool "NRF54L Normal Voltage Mode." +config SOC_NRF54L_GLITCHDET_WORKAROUND + bool "Workaround that disables glitch detector" + default y + help + Temporary workaround - disabling glitch detector to limit power consumption. + if NRF_GRTC_TIMER config ELV_GRTC_LFXO_ALLOWED diff --git a/soc/arm/nordic_nrf/nrf54l/soc.c b/soc/arm/nordic_nrf/nrf54l/soc.c index 6af0ff4ebcd..a7b286fa048 100644 --- a/soc/arm/nordic_nrf/nrf54l/soc.c +++ b/soc/arm/nordic_nrf/nrf54l/soc.c @@ -42,6 +42,10 @@ static int nordicsemi_nrf54l_init(void) /* Enable ICACHE */ sys_cache_instr_enable(); + if (IS_ENABLED(CONFIG_SOC_NRF54L_GLITCHDET_WORKAROUND)) { + nrf_glitchdet_enable_set(NRF_GLITCHDET, false); + } + #if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal) uint32_t xosc32ktrim = NRF_FICR->XOSC32KTRIM; From aa8ad236cadb054c4c4cdbfb6572cc079899a151 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:29 +0200 Subject: [PATCH 2269/2402] Revert "[nrf fromtree] samples: hci_uart_async: Dont try to receive 0 bytes" This reverts commit fc3886f97f63a62a7d6e5f1f8621db297ad7ce21. Signed-off-by: Gerard Marull-Paretas --- samples/bluetooth/hci_uart_async/src/hci_uart_async.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/samples/bluetooth/hci_uart_async/src/hci_uart_async.c b/samples/bluetooth/hci_uart_async/src/hci_uart_async.c index cf9cc600d5c..4d276e42378 100644 --- a/samples/bluetooth/hci_uart_async/src/hci_uart_async.c +++ b/samples/bluetooth/hci_uart_async/src/hci_uart_async.c @@ -254,9 +254,7 @@ static void h2c_h4_transport(void) LOG_DBG("h2c: payload_size %u", payload_size); - if (payload_size == 0) { - /* Done, dont rx zero bytes */ - } else if (payload_size <= net_buf_tailroom(buf)) { + if (payload_size <= net_buf_tailroom(buf)) { uint8_t *payload_dst = net_buf_add(buf, payload_size); err = uart_h2c_rx(payload_dst, payload_size); From ff850f2e1c50c0b5744443c27bff05bf678c00c2 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:29 +0200 Subject: [PATCH 2270/2402] Revert "[nrf fromtree] drivers/counter nrfx: Fix with DT instance not matching device instance" This reverts commit a8da6e408aa22c5002557d0c55f0ed2c390dfbd0. Signed-off-by: Gerard Marull-Paretas --- drivers/counter/counter_nrfx_timer.c | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/drivers/counter/counter_nrfx_timer.c b/drivers/counter/counter_nrfx_timer.c index 1fe3a98f8d7..47537b16d7d 100644 --- a/drivers/counter/counter_nrfx_timer.c +++ b/drivers/counter/counter_nrfx_timer.c @@ -28,12 +28,6 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL); #define COUNTER_OVERFLOW_SHORT NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK #define COUNTER_READ_CC NRF_TIMER_CC_CHANNEL1 -#if defined(CONFIG_SOC_SERIES_BSIM_NRFXX) -#define MAYBE_CONST_CONFIG -#else -#define MAYBE_CONST_CONFIG const -#endif - struct counter_nrfx_data { counter_top_callback_t top_cb; void *top_user_data; @@ -289,16 +283,7 @@ static uint32_t get_pending_int(const struct device *dev) static int init_timer(const struct device *dev, const struct counter_timer_config *config) { - MAYBE_CONST_CONFIG struct counter_nrfx_config *nrfx_config = - (MAYBE_CONST_CONFIG struct counter_nrfx_config *)dev->config; - -#if defined(CONFIG_SOC_SERIES_BSIM_NRFXX) - /* For simulated devices we need to convert the hardcoded DT address from the real - * peripheral into the correct one for simulation - */ - nrfx_config->timer = nhw_convert_periph_base_addr(nrfx_config->timer); -#endif - + const struct counter_nrfx_config *nrfx_config = dev->config; NRF_TIMER_Type *reg = nrfx_config->timer; nrf_timer_bit_width_set(reg, config->bit_width); @@ -445,7 +430,7 @@ static const struct counter_driver_api counter_nrfx_driver_api = { static struct counter_nrfx_ch_data \ counter##idx##_ch_data[CC_TO_ID(DT_INST_PROP(idx, cc_num))]; \ LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_COUNTER_LOG_LEVEL); \ - static MAYBE_CONST_CONFIG struct counter_nrfx_config nrfx_counter_##idx##_config = { \ + static const struct counter_nrfx_config nrfx_counter_##idx##_config = { \ .info = { \ .max_top_value = (uint32_t)BIT64_MASK(DT_INST_PROP(idx, max_bit_width)),\ .freq = TIMER_CLOCK((NRF_TIMER_Type *)DT_INST_REG_ADDR(idx)) / \ @@ -454,7 +439,7 @@ static const struct counter_driver_api counter_nrfx_driver_api = { .channels = CC_TO_ID(DT_INST_PROP(idx, cc_num)), \ }, \ .ch_data = counter##idx##_ch_data, \ - .timer = (NRF_TIMER_Type *)DT_INST_REG_ADDR(idx), \ + .timer = (NRF_TIMER_Type *)_CONCAT(NRF_TIMER, idx), \ LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx) \ }; \ DEVICE_DT_INST_DEFINE(idx, \ From debaf47db5fe1f35e0dcf0885063c262acc46c79 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:29 +0200 Subject: [PATCH 2271/2402] Revert "[nrf fromtree] manifest: Update nrf hw models to latest" This reverts commit 18b88cb8aa8a88594594723c0c323eb5f6803659. Signed-off-by: Gerard Marull-Paretas --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index f9cf79db073..f8e75062ad4 100644 --- a/west.yml +++ b/west.yml @@ -295,7 +295,7 @@ manifest: groups: - tools - name: nrf_hw_models - revision: 319e3ebd3134935c330980dfac53d05d28c0af9a + revision: 52d0b4b7b7431d8da6222cc3b17a8afdcb099baf path: modules/bsim_hw_models/nrf_hw_models - name: open-amp revision: da78aea63159771956fe0c9263f2e6985b66e9d5 From 1056520b0a3d914b4cb0591abfd27e153f4e8d54 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:30 +0200 Subject: [PATCH 2272/2402] Revert "[nrf fromtree] tests: llext: Set min_ram requirement for readonly_mpu variant" This reverts commit 41b38928f63ed79960084cf415299703b44d870f. Signed-off-by: Gerard Marull-Paretas --- tests/subsys/llext/hello_world/testcase.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/subsys/llext/hello_world/testcase.yaml b/tests/subsys/llext/hello_world/testcase.yaml index 2b324bea5ab..c977dc5f94f 100644 --- a/tests/subsys/llext/hello_world/testcase.yaml +++ b/tests/subsys/llext/hello_world/testcase.yaml @@ -13,7 +13,6 @@ tests: - arch:arm:CONFIG_ARM_MPU=n - CONFIG_LLEXT_STORAGE_WRITABLE=n llext.simple.readonly_mpu: - min_ram: 128 arch_exclude: xtensa # for now filter: CONFIG_CPU_HAS_MPU extra_configs: From 4295836cc5be98b8df2b64c1cb6deb119e61039f Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:30 +0200 Subject: [PATCH 2273/2402] Revert "[nrf fromtree] posix: socket: Add missing recvmsg()" This reverts commit c20c5afe1fd6cbd301e16e12144e0956cee0c9e6. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/posix/sys/socket.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/include/zephyr/posix/sys/socket.h b/include/zephyr/posix/sys/socket.h index 235bd76cc59..af4f48e3907 100644 --- a/include/zephyr/posix/sys/socket.h +++ b/include/zephyr/posix/sys/socket.h @@ -88,11 +88,6 @@ static inline ssize_t sendmsg(int sock, const struct msghdr *message, return zsock_sendmsg(sock, message, flags); } -static inline ssize_t recvmsg(int sock, struct msghdr *msg, int flags) -{ - return zsock_recvmsg(sock, msg, flags); -} - static inline ssize_t recvfrom(int sock, void *buf, size_t max_len, int flags, struct sockaddr *src_addr, socklen_t *addrlen) { From fe0dd8988368003c61773dac81b9feacf4bf521c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:30 +0200 Subject: [PATCH 2274/2402] Revert "[nrf fromtree] drivers: input: Fix uninitialized closest_mv variable warning" This reverts commit a74f47a3f06d47d92edf3c0c9657816daae43611. Signed-off-by: Gerard Marull-Paretas --- drivers/input/input_adc_keys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/input_adc_keys.c b/drivers/input/input_adc_keys.c index d37d79bf098..2e24ffd097d 100644 --- a/drivers/input/input_adc_keys.c +++ b/drivers/input/input_adc_keys.c @@ -70,7 +70,7 @@ static inline int32_t adc_keys_read(const struct device *dev) static inline void adc_keys_process(const struct device *dev) { const struct adc_keys_config *cfg = dev->config; - int32_t sample_mv, closest_mv = 0; + int32_t sample_mv, closest_mv; uint32_t diff, closest_diff = UINT32_MAX; const struct adc_keys_code_config *code_cfg; struct adc_keys_key_state *key_state; From a8a5ce7a3e527b846695fa0ca41ca6168b98c8e3 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:30 +0200 Subject: [PATCH 2275/2402] Revert "[nrf fromtree] sys: Include sys/util.h header in sys/atomic.h" This reverts commit e0363868fd5447ceb1fb0565380f863cd210a0d0. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/sys/atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/sys/atomic.h b/include/zephyr/sys/atomic.h index 86ba2cdf144..3982e428038 100644 --- a/include/zephyr/sys/atomic.h +++ b/include/zephyr/sys/atomic.h @@ -15,7 +15,7 @@ #include /* IWYU pragma: export */ #include -#include +#include #ifdef __cplusplus extern "C" { From b8eed899bcf186b48440586df7edcada10c07656 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:30 +0200 Subject: [PATCH 2276/2402] Revert "[nrf fromlist] dts: arm: nordic: nrf54l15 write block size" This reverts commit be32f653555d4445f4ca525cd8e0021a81fbbf31. Signed-off-by: Gerard Marull-Paretas --- dts/arm/nordic/nrf54l_common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/arm/nordic/nrf54l_common.dtsi b/dts/arm/nordic/nrf54l_common.dtsi index c537554b05b..3214daeac84 100644 --- a/dts/arm/nordic/nrf54l_common.dtsi +++ b/dts/arm/nordic/nrf54l_common.dtsi @@ -18,7 +18,7 @@ rram0: rram@0 { compatible = "soc-nv-flash"; erase-block-size = <4096>; - write-block-size = <16>; + write-block-size = <1>; }; }; }; From 80321903d62e2f2a4729f4993ac20d749575515d Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:31 +0200 Subject: [PATCH 2277/2402] Revert "[nrf fromtree] boards: nrf54l15pdk_nrf54l15_cpuapp: add temp status okay" This reverts commit d3a903aff7b36e992ec3b5ce32eeb94dea426de0. Signed-off-by: Gerard Marull-Paretas --- .../arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts index c801ddc8dc5..c009f0bd544 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -133,10 +133,6 @@ status = "okay"; }; -&temp { - status = "okay"; -}; - &rram0 { partitions { compatible = "fixed-partitions"; From f15b6f0b7443d616fcdff38eb9dfc173ab4ef386 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:31 +0200 Subject: [PATCH 2278/2402] Revert "[nrf fromtree] boards: nrf54l15pdk_nrf54l15_cpuapp: add ieee802154 status okay" This reverts commit 8a134f993662ebb63a790d9e479669bc7a171c0c. Signed-off-by: Gerard Marull-Paretas --- .../arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts index c009f0bd544..9876e3996e8 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -129,10 +129,6 @@ status = "okay"; }; -&ieee802154 { - status = "okay"; -}; - &rram0 { partitions { compatible = "fixed-partitions"; From aa345f6bf5b667e17b402408750f4cf1a5553c32 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:31 +0200 Subject: [PATCH 2279/2402] Revert "[nrf noup] boards: arm: kconfig: ROM_START_OFFSET" This reverts commit a5a8676af4c2702e5570cdb1381dceadf2d8b6c0. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig b/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig index 94b0fc7299d..3e47a0bb583 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig +++ b/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig @@ -10,7 +10,7 @@ config BT_CTLR default BT config ROM_START_OFFSET - default 0 if PARTITION_MANAGER_ENABLED + hex default 0x800 if BOOTLOADER_MCUBOOT endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP From 8adf363d08f3015be10e6f1fc610543a969e6f1e Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:31 +0200 Subject: [PATCH 2280/2402] Revert "[nrf noup] tree-wide: support NCS Partition Manager (PM) definitions" This reverts commit 39598424d22cc357cfb37365901c9a5cf733436b. Signed-off-by: Gerard Marull-Paretas --- arch/arm/core/mpu/arm_mpu_regions.c | 13 ------ cmake/modules/kernel.cmake | 4 -- drivers/flash/soc_flash_nrf.c | 11 ----- .../arch/arm/cortex_m/scripts/linker.ld | 46 ------------------- include/zephyr/storage/flash_map.h | 6 --- lib/heap/Kconfig | 2 +- lib/libc/common/source/stdlib/malloc.c | 18 +------- subsys/fs/littlefs_fs.c | 7 +-- subsys/ipc/rpmsg_service/rpmsg_backend.h | 27 ----------- 9 files changed, 4 insertions(+), 130 deletions(-) diff --git a/arch/arm/core/mpu/arm_mpu_regions.c b/arch/arm/core/mpu/arm_mpu_regions.c index cfe1230c907..6af62f84078 100644 --- a/arch/arm/core/mpu/arm_mpu_regions.c +++ b/arch/arm/core/mpu/arm_mpu_regions.c @@ -8,9 +8,6 @@ #include #include -#if USE_PARTITION_MANAGER -#include -#endif static const struct arm_mpu_region mpu_regions[] = { /* Region 0 */ @@ -24,14 +21,6 @@ static const struct arm_mpu_region mpu_regions[] = { #endif /* Region 1 */ MPU_REGION_ENTRY("SRAM_0", -#if USE_PARTITION_MANAGER - PM_SRAM_ADDRESS, -#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) - REGION_RAM_ATTR(PM_SRAM_ADDRESS, PM_SRAM_SIZE)), -#else - REGION_RAM_ATTR(REGION_SRAM_SIZE)), -#endif -#else CONFIG_SRAM_BASE_ADDRESS, #if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \ @@ -39,8 +28,6 @@ static const struct arm_mpu_region mpu_regions[] = { #else REGION_RAM_ATTR(REGION_SRAM_SIZE)), #endif - -#endif /* USE_PARTITION_MANAGER */ }; const struct arm_mpu_config mpu_config = { diff --git a/cmake/modules/kernel.cmake b/cmake/modules/kernel.cmake index 06e1642f362..a093d46691f 100644 --- a/cmake/modules/kernel.cmake +++ b/cmake/modules/kernel.cmake @@ -243,7 +243,3 @@ if("${CMAKE_EXTRA_GENERATOR}" STREQUAL "Eclipse CDT4") include(${ZEPHYR_BASE}/cmake/ide/eclipse_cdt4_generator_amendment.cmake) eclipse_cdt4_generator_amendment(1) endif() - -if(ZEPHYR_NRF_MODULE_DIR) - include(${ZEPHYR_NRF_MODULE_DIR}/cmake/partition_manager.cmake) -endif() diff --git a/drivers/flash/soc_flash_nrf.c b/drivers/flash/soc_flash_nrf.c index b5a3fefa1e5..cc840309264 100644 --- a/drivers/flash/soc_flash_nrf.c +++ b/drivers/flash/soc_flash_nrf.c @@ -37,11 +37,6 @@ LOG_MODULE_REGISTER(flash_nrf); #define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash) -#if CONFIG_TRUSTED_EXECUTION_NONSECURE && USE_PARTITION_MANAGER -#include -#include -#endif /* CONFIG_TRUSTED_EXECUTION_NONSECURE && USE_PARTITION_MANAGER */ - #ifndef CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE #define FLASH_SLOT_WRITE 7500 #if defined(CONFIG_SOC_FLASH_NRF_PARTIAL_ERASE) @@ -171,12 +166,6 @@ static int flash_nrf_read(const struct device *dev, off_t addr, } #endif -#if CONFIG_TRUSTED_EXECUTION_NONSECURE && USE_PARTITION_MANAGER && PM_APP_ADDRESS - if (addr < PM_APP_ADDRESS) { - return soc_secure_mem_read(data, (void *)addr, len); - } -#endif - nrf_nvmc_buffer_read(data, (uint32_t)addr, len); return 0; diff --git a/include/zephyr/arch/arm/cortex_m/scripts/linker.ld b/include/zephyr/arch/arm/cortex_m/scripts/linker.ld index 14eb78f3e70..d061468d2ac 100644 --- a/include/zephyr/arch/arm/cortex_m/scripts/linker.ld +++ b/include/zephyr/arch/arm/cortex_m/scripts/linker.ld @@ -26,35 +26,6 @@ #endif #define RAMABLE_REGION RAM -#if USE_PARTITION_MANAGER - -#include - -#if CONFIG_NCS_IS_VARIANT_IMAGE && defined(PM_S0_ID) -/* We are linking against S1, create symbol containing the flash ID of S0. - * This is used when writing code operating on the "other" slot. - */ -_image_1_primary_slot_id = PM_S0_ID; - -#else /* ! CONFIG_NCS_IS_VARIANT_IMAGE */ - -#ifdef PM_S1_ID -/* We are linking against S0, create symbol containing the flash ID of S1. - * This is used when writing code operating on the "other" slot. - */ -_image_1_primary_slot_id = PM_S1_ID; -#endif /* PM_S1_ID */ - -#endif /* CONFIG_NCS_IS_VARIANT_IMAGE */ - -#define ROM_ADDR PM_ADDRESS -#define ROM_SIZE PM_SIZE - -#define RAM_SIZE PM_SRAM_SIZE -#define RAM_ADDR PM_SRAM_ADDRESS - -#else /* ! USE_PARTITION_MANAGER */ - #if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0) #define ROM_ADDR RAM_ADDR #else @@ -87,23 +58,6 @@ _image_1_primary_slot_id = PM_S1_ID; #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS #endif -#endif /* USE_PARTITION_MANAGER */ - -#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay) -#define CCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ccm)) -#define CCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ccm)) -#endif - -#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay) -#define ITCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_itcm)) -#define ITCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_itcm)) -#endif - -#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay) -#define DTCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm)) -#define DTCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm)) -#endif - #if defined(CONFIG_CUSTOM_SECTION_ALIGN) _region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE; #else diff --git a/include/zephyr/storage/flash_map.h b/include/zephyr/storage/flash_map.h index ffe386d6b7a..12f4f4c34a2 100644 --- a/include/zephyr/storage/flash_map.h +++ b/include/zephyr/storage/flash_map.h @@ -271,10 +271,6 @@ const char *flash_area_label(const struct flash_area *fa); */ uint8_t flash_area_erased_val(const struct flash_area *fa); -#if USE_PARTITION_MANAGER -#include -#else - /** * Returns non-0 value if fixed-partition of given DTS node label exists. * @@ -332,8 +328,6 @@ uint8_t flash_area_erased_val(const struct flash_area *fa); #define FIXED_PARTITION_DEVICE(label) \ DEVICE_DT_GET(DT_MTD_FROM_FIXED_PARTITION(DT_NODELABEL(label))) -#endif /* USE_PARTITION_MANAGER */ - #ifdef __cplusplus } #endif diff --git a/lib/heap/Kconfig b/lib/heap/Kconfig index 68476eb735c..7f01b280b3b 100644 --- a/lib/heap/Kconfig +++ b/lib/heap/Kconfig @@ -68,7 +68,7 @@ config HEAP_LISTENER choice prompt "Supported heap sizes" depends on !64BIT - default SYS_HEAP_SMALL_ONLY if (SRAM_SIZE <= 256) && !PARTITION_MANAGER_ENABLED + default SYS_HEAP_SMALL_ONLY if (SRAM_SIZE <= 256) default SYS_HEAP_AUTO help Heaps using reduced-size chunk headers can accommodate so called diff --git a/lib/libc/common/source/stdlib/malloc.c b/lib/libc/common/source/stdlib/malloc.c index 2f469d673e4..e3a5db6f7d5 100644 --- a/lib/libc/common/source/stdlib/malloc.c +++ b/lib/libc/common/source/stdlib/malloc.c @@ -25,20 +25,6 @@ #include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); -#if USE_PARTITION_MANAGER - -#include - -#define RAM_SIZE PM_SRAM_SIZE -#define RAM_ADDR PM_SRAM_ADDRESS - -#else /* ! USE_PARTITION_MANAGER */ - -#define RAM_SIZE (KB((size_t) CONFIG_SRAM_SIZE)) -#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS - -#endif /* USE_PARTITION_MANAGER */ - #ifdef CONFIG_COMMON_LIBC_MALLOC #if (CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE != 0) @@ -120,8 +106,8 @@ static POOL_SECTION unsigned char __aligned(HEAP_ALIGN) malloc_arena[HEAP_SIZE]; extern char _heap_sentry[]; # define HEAP_SIZE ROUND_DOWN((POINTER_TO_UINT(_heap_sentry) - HEAP_BASE), HEAP_ALIGN) # else -# define HEAP_SIZE ROUND_DOWN((RAM_SIZE - \ - ((size_t) HEAP_BASE - (size_t) RAM_ADDR)), HEAP_ALIGN) +# define HEAP_SIZE ROUND_DOWN((KB((size_t) CONFIG_SRAM_SIZE) - \ + ((size_t) HEAP_BASE - (size_t) CONFIG_SRAM_BASE_ADDRESS)), HEAP_ALIGN) # endif /* else CONFIG_XTENSA */ # endif /* else CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE > 0 */ diff --git a/subsys/fs/littlefs_fs.c b/subsys/fs/littlefs_fs.c index 3fc84c2922d..b373ca92ba8 100644 --- a/subsys/fs/littlefs_fs.c +++ b/subsys/fs/littlefs_fs.c @@ -1054,12 +1054,7 @@ struct fs_mount_t FS_FSTAB_ENTRY(DT_DRV_INST(inst)) = { \ .type = FS_LITTLEFS, \ .mnt_point = DT_INST_PROP(inst, mount_point), \ .fs_data = &fs_data_##inst, \ - .storage_dev = (void *) \ - COND_CODE_1(USE_PARTITION_MANAGER, \ - (COND_CODE_1(FIXED_PARTITION_EXISTS(littlefs_storage), \ - (FIXED_PARTITION_ID(littlefs_storage)), \ - (FIXED_PARTITION_ID(storage)))), \ - (DT_FIXED_PARTITION_ID(FS_PARTITION(inst)))), \ + .storage_dev = (void *)DT_FIXED_PARTITION_ID(FS_PARTITION(inst)), \ .flags = FSTAB_ENTRY_DT_MOUNT_FLAGS(DT_DRV_INST(inst)), \ }; diff --git a/subsys/ipc/rpmsg_service/rpmsg_backend.h b/subsys/ipc/rpmsg_service/rpmsg_backend.h index 9996e1d74d9..a74e46b8520 100644 --- a/subsys/ipc/rpmsg_service/rpmsg_backend.h +++ b/subsys/ipc/rpmsg_service/rpmsg_backend.h @@ -13,35 +13,8 @@ extern "C" { #endif -#if CONFIG_PARTITION_MANAGER_ENABLED - -#include "pm_config.h" - -#if defined(PM_RPMSG_NRF53_SRAM_ADDRESS) || defined(PM__RPMSG_NRF53_SRAM_ADDRESS) - -#if defined(PM_RPMSG_NRF53_SRAM_ADDRESS) -#define VDEV_START_ADDR PM_RPMSG_NRF53_SRAM_ADDRESS -#define VDEV_SIZE PM_RPMSG_NRF53_SRAM_SIZE -#else -/* The current image is a child image in a different domain than the image - * which defined the required values. To reach the values of the parent domain - * we use the 'PM__' variant of the define. - */ -#define VDEV_START_ADDR PM__RPMSG_NRF53_SRAM_ADDRESS -#define VDEV_SIZE PM__RPMSG_NRF53_SRAM_SIZE -#endif /* defined(PM_RPMSG_NRF53_SRAM_ADDRESS) */ - -#else #define VDEV_START_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ipc_shm)) #define VDEV_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ipc_shm)) -#endif /* defined(PM_RPMSG_NRF53_SRAM_ADDRESS) || defined(PM__RPMSG_NRF53_SRAM_ADDRESS) */ - -#else - -#define VDEV_START_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ipc_shm)) -#define VDEV_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ipc_shm)) - -#endif /* CONFIG_PARTITION_MANAGER_ENABLED */ #define VDEV_STATUS_ADDR VDEV_START_ADDR #define VDEV_STATUS_SIZE 0x400 From dfba153563167d6e850227e949347caca0db2695 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:32 +0200 Subject: [PATCH 2281/2402] Revert "[nrf noup] ci: clang: parallel execution" This reverts commit 368628d23026e5c141b92816fefb801640cfb908. Signed-off-by: Gerard Marull-Paretas --- .github/workflows/clang.yaml | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index b28d3c387e4..17fbc1c72bd 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -8,7 +8,8 @@ concurrency: jobs: clang-build: - runs-on: ubuntu-latest + if: github.repository_owner == 'zephyrproject-rtos' + runs-on: zephyr-runner-linux-x64-4xlarge container: image: ghcr.io/zephyrproject-rtos/ci:v0.26.7 options: '--entrypoint /bin/bash' @@ -18,12 +19,10 @@ jobs: fail-fast: false matrix: platform: ["native_sim"] - subset: [1, 2, 3, 4, 5] env: LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16 COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} BASE_REF: ${{ github.base_ref }} - MATRIX_SIZE: 5 outputs: report_needed: ${{ steps.twister.outputs.report_needed }} steps: @@ -88,7 +87,7 @@ jobs: id: cache-ccache uses: zephyrproject-rtos/action-s3-cache@v1.2.0 with: - key: ${{ steps.ccache_cache_timestamp.outputs.repo }}-${{ github.ref_name }}-clang-${{ matrix.subset }}-ccache + key: ${{ steps.ccache_cache_timestamp.outputs.repo }}-${{ github.ref_name }}-clang-${{ matrix.platform }}-ccache path: /github/home/.cache/ccache aws-s3-bucket: ccache.zephyrproject.org aws-access-key-id: ${{ vars.AWS_CCACHE_ACCESS_KEY_ID }} @@ -101,16 +100,6 @@ jobs: test -d github/home/.cache/ccache && rm -rf /github/home/.cache/ccache && mv github/home/.cache/ccache /github/home/.cache/ccache ccache -M 10G -s - - name: Build test plan with Twister - id: twister_test_plan - run: | - export ZEPHYR_BASE=${PWD} - export ZEPHYR_TOOLCHAIN_VARIANT=llvm - - # check if we need to run a full twister or not based on files changed - python3 ./scripts/ci/test_plan.py -p native_posix -c origin/${BASE_REF}.. - - - name: Run Tests with Twister id: twister run: | @@ -124,7 +113,7 @@ jobs: if [ -s testplan.json ]; then echo "report_needed=1" >> $GITHUB_OUTPUT # Full twister but with options based on changes - ./scripts/twister --inline-logs -M -N -v --load-tests testplan.json --retry-failed 2 --subset ${{matrix.subset}}/${MATRIX_SIZE} + ./scripts/twister --force-color --inline-logs -M -N -v --load-tests testplan.json --retry-failed 2 else # if nothing is run, skip reporting step echo "report_needed=0" >> $GITHUB_OUTPUT @@ -139,7 +128,7 @@ jobs: if: always() && steps.twister.outputs.report_needed != 0 uses: actions/upload-artifact@v4 with: - name: Unit Test Results (Subset ${{ matrix.subset }}) + name: Unit Test Results (Subset ${{ matrix.platform }}) path: twister-out/twister.xml clang-build-results: From e4f8129a466a73459eddc3aef3cc390a38354c4b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:32 +0200 Subject: [PATCH 2282/2402] Revert "[nrf fromlist] modules: hal_nordic: Enable support for DPPI on nRF54H20" This reverts commit 4378c6032eefd27fd4e0216051287b160af0516b. Signed-off-by: Gerard Marull-Paretas --- drivers/timer/nrf_grtc_timer.c | 4 +- modules/hal_nordic/nrfx/CMakeLists.txt | 8 -- modules/hal_nordic/nrfx/nrfx_config.h | 121 ++----------------------- 3 files changed, 12 insertions(+), 121 deletions(-) diff --git a/drivers/timer/nrf_grtc_timer.c b/drivers/timer/nrf_grtc_timer.c index 51f00687e7e..7ac6eca80eb 100644 --- a/drivers/timer/nrf_grtc_timer.c +++ b/drivers/timer/nrf_grtc_timer.c @@ -21,8 +21,8 @@ #if !DT_NODE_HAS_PROP(GRTC_NODE, owned_channels) #error GRTC owned-channels DT property is not defined #endif -#define OWNED_CHANNELS_MASK NRFX_CONFIG_MASK_DT(GRTC_NODE, owned_channels) -#define CHILD_OWNED_CHANNELS_MASK NRFX_CONFIG_MASK_DT(GRTC_NODE, child_owned_channels) +#define OWNED_CHANNELS_MASK NRFX_CONFIG_GRTC_MASK_DT(owned_channels) +#define CHILD_OWNED_CHANNELS_MASK NRFX_CONFIG_GRTC_MASK_DT(child_owned_channels) #if ((OWNED_CHANNELS_MASK | CHILD_OWNED_CHANNELS_MASK) != OWNED_CHANNELS_MASK) #error GRTC child-owned-channels DT property must be a subset of owned-channels #endif diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index 285293722bb..29f09783f2f 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -174,14 +174,6 @@ if(CONFIG_SOC_SERIES_NRF54LX AND CONFIG_NRFX_DPPI) zephyr_library_sources(${NRFX_DIR}/soc/interconnect/dppic_ppib/nrfx_interconnect_dppic_ppib.c) endif() -if(CONFIG_SOC_SERIES_NRF54HX AND - (CONFIG_DT_HAS_NORDIC_NRF_DPPIC_LOCAL_ENABLED OR - CONFIG_DT_HAS_NORDIC_NRF_DPPIC_GLOBAL_ENABLED)) - zephyr_library_sources(${HELPERS_DIR}/nrfx_gppi_dppi_ppib.c) - zephyr_library_sources(${NRFX_DIR}/soc/interconnect/apb/nrfx_interconnect_apb.c) - zephyr_library_sources(${NRFX_DIR}/soc/interconnect/ipct/nrfx_interconnect_ipct.c) -endif() - # Get the SVD file for the current SoC macro(mdk_svd_ifdef feature_toggle filename) if(${feature_toggle}) diff --git a/modules/hal_nordic/nrfx/nrfx_config.h b/modules/hal_nordic/nrfx/nrfx_config.h index 206fa2ed5dc..0daa476cb9d 100644 --- a/modules/hal_nordic/nrfx/nrfx_config.h +++ b/modules/hal_nordic/nrfx/nrfx_config.h @@ -8,7 +8,6 @@ #define NRFX_CONFIG_H__ #include -#include /* * These are mappings of Kconfig options enabling nrfx drivers and particular @@ -795,127 +794,27 @@ #define NRF_PERIPH(P) P##_S #endif -#define NRFX_CONFIG_BIT_DT(node_id, prop, idx) BIT(DT_PROP_BY_IDX(node_id, prop, idx)) -#define NRFX_CONFIG_MASK_DT(node_id, prop) \ - (COND_CODE_1(DT_NODE_HAS_PROP(node_id, prop), \ - (DT_FOREACH_PROP_ELEM_SEP(node_id, prop, NRFX_CONFIG_BIT_DT, (|))), \ - (0))) - /* If the GRTC system timer driver is to be used, prepare definitions required * by the nrfx_grtc driver (NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK and * NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS) based on information from devicetree. */ #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_grtc) +#define NRFX_CONFIG_BIT_DT(node_id, prop, idx) \ + BIT(DT_PROP_BY_IDX(node_id, prop, idx)) +#define NRFX_CONFIG_GRTC_MASK_DT(prop) \ + (COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(0, nordic_nrf_grtc), prop), \ + (DT_FOREACH_PROP_ELEM_SEP(DT_INST(0, nordic_nrf_grtc), prop, \ + NRFX_CONFIG_BIT_DT, (|))), \ + (0))) + #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK \ - (NRFX_CONFIG_MASK_DT(DT_INST(0, nordic_nrf_grtc), owned_channels) & \ - ~NRFX_CONFIG_MASK_DT(DT_INST(0, nordic_nrf_grtc), child_owned_channels)) + (NRFX_CONFIG_GRTC_MASK_DT(owned_channels) & \ + ~NRFX_CONFIG_GRTC_MASK_DT(child_owned_channels)) #define NRFX_GRTC_CONFIG_NUM_OF_CC_CHANNELS \ (DT_PROP_LEN_OR(DT_INST(0, nordic_nrf_grtc), owned_channels, 0) - \ DT_PROP_LEN_OR(DT_INST(0, nordic_nrf_grtc), child_owned_channels, 0)) #endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_grtc) */ -/* If global of local DPPIC peripherals are used, provide the following macro - * definitions required by the interconnect/apb layer: - * - NRFX_DPPI_PUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) - * - NRFX_DPPI_SUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) - * - NRFX_DPPI_PUB_OR_SUB_MASK(inst_num) - * - NRFX_DPPI_CHANNELS_SINGLE_VAR_NAME_BY_INST_NUM(inst_num) - * - NRFX_INTERCONNECT_APB_GLOBAL_DPPI_DEFINE - * - NRFX_INTERCONNECT_APB_LOCAL_DPPI_DEFINE - * based on information from devicetree. - */ -#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_dppic_global) || \ - DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_dppic_local) -#ifndef NRFX_DPPI_ENABLED -#define NRFX_DPPI_ENABLED 1 -#endif -/* Source (publish) channels masks generation. */ -#define NRFX_DPPI_PUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) \ - NRFX_CONFIG_MASK_DT(DT_NODELABEL(_CONCAT(dppic, inst_num)), source_channels) - -/* Sink (subscribe) channels masks generation. */ -#define NRFX_DPPI_SUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) \ - NRFX_CONFIG_MASK_DT(DT_NODELABEL(_CONCAT(dppic, inst_num)), sink_channels) - -#define NRFX_DPPI_PUB_OR_SUB_MASK(inst_num) \ - UTIL_OR(DT_NODE_HAS_PROP(DT_NODELABEL(_CONCAT(dppic, inst_num)), source_channels), \ - DT_NODE_HAS_PROP(DT_NODELABEL(_CONCAT(dppic, inst_num)), sink_channels)) - -/* Variables names generation. */ -#define NRFX_CONFIG_DPPI_CHANNELS_ENTRY_NAME(node_id) _CONCAT(_CONCAT(m_, node_id), _channels) -#define NRFX_DPPI_CHANNELS_SINGLE_VAR_NAME_BY_INST_NUM(inst_num) \ - NRFX_CONFIG_DPPI_CHANNELS_ENTRY_NAME(DT_NODELABEL(_CONCAT(dppic, inst_num))) - -/* Variables entries generation. */ -#define NRFX_CONFIG_DPPI_CHANNELS_ENTRY(node_id) \ - static nrfx_atomic_t NRFX_CONFIG_DPPI_CHANNELS_ENTRY_NAME(node_id) \ - __attribute__((used)) = \ - NRFX_CONFIG_MASK_DT(node_id, source_channels) | \ - NRFX_CONFIG_MASK_DT(node_id, sink_channels); -#define NRFX_INTERCONNECT_APB_GLOBAL_DPPI_DEFINE \ - DT_FOREACH_STATUS_OKAY(nordic_nrf_dppic_global, NRFX_CONFIG_DPPI_CHANNELS_ENTRY) -#define NRFX_INTERCONNECT_APB_LOCAL_DPPI_DEFINE \ - DT_FOREACH_STATUS_OKAY(nordic_nrf_dppic_local, NRFX_CONFIG_DPPI_CHANNELS_ENTRY) -#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_dppic_global) || ... */ - -/* If local or global DPPIC peripherals are used, provide the following macro - * definitions required by the interconnect/ipct layer: - * - NRFX_IPCTx_PUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) - * - NRFX_IPCTx_SUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) - * - NRFX_IPCT_PUB_OR_SUB_MASK(inst_num) - * - NRFX_IPCTx_CHANNELS_SINGLE_VAR_NAME_BY_INST_NUM(inst_num) - * - NRFX_INTERCONNECT_IPCT_GLOBAL_DEFINE - * - NRFX_INTERCONNECT_IPCT_LOCAL_DEFINE - * based on information from devicetree. - */ -#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_ipct_global) || \ - DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_ipct_local) -/* Channels masks generation. */ -#define NRFX_CONFIG_IPCT_MASK_DT(node_id) \ - COND_CODE_1(DT_NODE_HAS_PROP(node_id, owned_channels), \ - (NRFX_CONFIG_MASK_DT(node_id, owned_channels)), \ - (COND_CODE_1(DT_NODE_HAS_COMPAT(node_id, nordic_nrf_ipct_local), \ - (BIT_MASK(DT_PROP(node_id, channels))), (0)))) - -#if defined(NRF_APPLICATION) -#define NRFX_CONFIG_IPCT_LOCAL_NODE DT_NODELABEL(cpuapp_ipct) -#elif defined(NRF_RADIOCORE) -#define NRFX_CONFIG_IPCT_LOCAL_NODE DT_NODELABEL(cpurad_ipct) -#endif -#define NRFX_CONFIG_IPCT_NODE_BY_INST_NUM(inst_num) \ - COND_CODE_1(IS_EMPTY(inst_num), \ - (NRFX_CONFIG_IPCT_LOCAL_NODE), \ - (DT_NODELABEL(_CONCAT(ipct, inst_num)))) - -#define NRFX_IPCTx_PUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) \ - NRFX_CONFIG_IPCT_MASK_DT(NRFX_CONFIG_IPCT_NODE_BY_INST_NUM(inst_num)) - -#define NRFX_IPCTx_SUB_CONFIG_ALLOWED_CHANNELS_MASK_BY_INST_NUM(inst_num) \ - NRFX_CONFIG_IPCT_MASK_DT(NRFX_CONFIG_IPCT_NODE_BY_INST_NUM(inst_num)) - -#define NRFX_IPCT_PUB_OR_SUB_MASK(inst_num) \ - COND_CODE_1(IS_EMPTY(inst_num), \ - (DT_NODE_HAS_STATUS(NRFX_CONFIG_IPCT_LOCAL_NODE, okay)), \ - (DT_NODE_HAS_PROP(DT_NODELABEL(_CONCAT(ipct, inst_num)), owned_channels))) - -/* Variables names generation. */ -#define NRFX_CONFIG_IPCT_CHANNELS_ENTRY_NAME(node_id) _CONCAT(_CONCAT(m_, node_id), _channels) -#define NRFX_IPCTx_CHANNELS_SINGLE_VAR_NAME_BY_INST_NUM(inst_num) \ - COND_CODE_1(IS_EMPTY(inst_num), \ - (NRFX_CONFIG_IPCT_CHANNELS_ENTRY_NAME(NRFX_CONFIG_IPCT_LOCAL_NODE)), \ - (NRFX_CONFIG_IPCT_CHANNELS_ENTRY_NAME(DT_NODELABEL(_CONCAT(ipct, inst_num))))) - -/* Variables entries generation. */ -#define NRFX_CONFIG_IPCT_CHANNELS_ENTRY(node_id) \ - static nrfx_atomic_t NRFX_CONFIG_IPCT_CHANNELS_ENTRY_NAME(node_id) \ - __attribute__((used)) = \ - NRFX_CONFIG_IPCT_MASK_DT(node_id); -#define NRFX_INTERCONNECT_IPCT_LOCAL_DEFINE \ - DT_FOREACH_STATUS_OKAY(nordic_nrf_ipct_local, NRFX_CONFIG_IPCT_CHANNELS_ENTRY) -#define NRFX_INTERCONNECT_IPCT_GLOBAL_DEFINE \ - DT_FOREACH_STATUS_OKAY(nordic_nrf_ipct_global, NRFX_CONFIG_IPCT_CHANNELS_ENTRY) -#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_ipct_global) || ... */ - #include #if defined(NRF51) #include From a8116f53123b5d8b6deb7b333eff6527033ba6bc Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:32 +0200 Subject: [PATCH 2283/2402] Revert "[nrf fromlist] manifest: Update hal_nordic revision" This reverts commit 70d831dfcfad758cf70b7a5712bcf442b563e067. Signed-off-by: Gerard Marull-Paretas --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index f8e75062ad4..a288009c15a 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: 5470822384781624efb2fda28cbc6a895a227677 + revision: daf875285120be6b2825969b7a0abc3f415b248d path: modules/hal/nordic groups: - hal From 89a5417274e3679df6e3210502837de69bb00630 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:32 +0200 Subject: [PATCH 2284/2402] Revert "[nrf fromlist] soc: nordic_nrf: Add address validation entries for nRF54H/L dts nodes" This reverts commit 319fb4c47550b0adcd3eed7aba804b75aedbce30. Signed-off-by: Gerard Marull-Paretas --- soc/arm/nordic_nrf/validate_base_addresses.c | 76 -------------------- 1 file changed, 76 deletions(-) diff --git a/soc/arm/nordic_nrf/validate_base_addresses.c b/soc/arm/nordic_nrf/validate_base_addresses.c index 04c7a1ae3cd..28ec231b132 100644 --- a/soc/arm/nordic_nrf/validate_base_addresses.c +++ b/soc/arm/nordic_nrf/validate_base_addresses.c @@ -133,39 +133,17 @@ CHECK_DT_REG(cryptocell, NRF_CRYPTOCELL); CHECK_DT_REG(ctrlap, NRF_CTRLAP); CHECK_DT_REG(dcnf, NRF_DCNF); CHECK_DT_REG(dppic, NRF_DPPIC); -CHECK_DT_REG(dppic00, NRF_DPPIC00); -CHECK_DT_REG(dppic10, NRF_DPPIC10); -CHECK_DT_REG(dppic20, NRF_DPPIC20); -CHECK_DT_REG(dppic30, NRF_DPPIC30); -CHECK_DT_REG(dppic020, NRF_DPPIC020); -CHECK_DT_REG(dppic120, NRF_DPPIC120); -CHECK_DT_REG(dppic130, NRF_DPPIC130); -CHECK_DT_REG(dppic131, NRF_DPPIC131); -CHECK_DT_REG(dppic132, NRF_DPPIC132); -CHECK_DT_REG(dppic133, NRF_DPPIC133); -CHECK_DT_REG(dppic134, NRF_DPPIC134); -CHECK_DT_REG(dppic135, NRF_DPPIC135); -CHECK_DT_REG(dppic136, NRF_DPPIC136); CHECK_DT_REG(ecb, NRF_ECB); -CHECK_DT_REG(ecb020, NRF_ECB020); -CHECK_DT_REG(ecb030, NRF_ECB030); CHECK_DT_REG(egu0, NRF_EGU0); CHECK_DT_REG(egu1, NRF_EGU1); CHECK_DT_REG(egu2, NRF_EGU2); CHECK_DT_REG(egu3, NRF_EGU3); CHECK_DT_REG(egu4, NRF_EGU4); CHECK_DT_REG(egu5, NRF_EGU5); -CHECK_DT_REG(egu10, NRF_EGU10); -CHECK_DT_REG(egu20, NRF_EGU20); -CHECK_DT_REG(egu020, NRF_EGU020); CHECK_DT_REG(ficr, NRF_FICR); CHECK_DT_REG(flash_controller, NRF_NVMC); CHECK_DT_REG(gpio0, NRF_P0); CHECK_DT_REG(gpio1, NRF_P1); -CHECK_DT_REG(gpio2, NRF_P2); -CHECK_DT_REG(gpio6, NRF_P6); -CHECK_DT_REG(gpio7, NRF_P7); -CHECK_DT_REG(gpio9, NRF_P9); CHECK_DT_REG(gpiote, NRF_GPIOTE); CHECK_DT_REG(gpiote0, NRF_GPIOTE0); CHECK_DT_REG(gpiote1, NRF_GPIOTE1); @@ -177,25 +155,8 @@ CHECK_I2C_REG(i2c0, 0); CHECK_I2C_REG(i2c1, 1); CHECK_DT_REG(i2c2, NRF_TWIM2); CHECK_DT_REG(i2c3, NRF_TWIM3); -CHECK_DT_REG(i2c20, NRF_TWIM20); -CHECK_DT_REG(i2c21, NRF_TWIM21); -CHECK_DT_REG(i2c22, NRF_TWIM22); -CHECK_DT_REG(i2c30, NRF_TWIM30); -CHECK_DT_REG(i2c130, NRF_TWIM130); -CHECK_DT_REG(i2c131, NRF_TWIM131); -CHECK_DT_REG(i2c132, NRF_TWIM132); -CHECK_DT_REG(i2c133, NRF_TWIM133); -CHECK_DT_REG(i2c134, NRF_TWIM134); -CHECK_DT_REG(i2c135, NRF_TWIM135); -CHECK_DT_REG(i2c136, NRF_TWIM136); -CHECK_DT_REG(i2c137, NRF_TWIM137); CHECK_DT_REG(i2s0, NRF_I2S0); -CHECK_DT_REG(i2s20, NRF_I2S20); CHECK_DT_REG(ipc, NRF_IPC); -CHECK_DT_REG(cpuapp_ipct, NRF_IPCT); -CHECK_DT_REG(cpurad_ipct, NRF_IPCT); -CHECK_DT_REG(ipct120, NRF_IPCT120); -CHECK_DT_REG(ipct130, NRF_IPCT130); CHECK_DT_REG(kmu, NRF_KMU); CHECK_DT_REG(mutex, NRF_MUTEX); CHECK_DT_REG(mwu, NRF_MWU); @@ -212,40 +173,18 @@ CHECK_DT_REG(pwm3, NRF_PWM3); CHECK_DT_REG(qdec, NRF_QDEC0); /* this should be the same node as qdec0 */ CHECK_DT_REG(qdec0, NRF_QDEC0); CHECK_DT_REG(qdec1, NRF_QDEC1); -CHECK_DT_REG(qdec20, NRF_QDEC20); -CHECK_DT_REG(qdec21, NRF_QDEC21); -CHECK_DT_REG(qdec130, NRF_QDEC130); -CHECK_DT_REG(qdec131, NRF_QDEC131); CHECK_DT_REG(radio, NRF_RADIO); CHECK_DT_REG(regulators, NRF_REGULATORS); CHECK_DT_REG(reset, NRF_RESET); CHECK_DT_REG(rng, NRF_RNG); -CHECK_DT_REG(rtc, NRF_RTC); CHECK_DT_REG(rtc0, NRF_RTC0); CHECK_DT_REG(rtc1, NRF_RTC1); CHECK_DT_REG(rtc2, NRF_RTC2); -CHECK_DT_REG(rtc130, NRF_RTC130); -CHECK_DT_REG(rtc131, NRF_RTC131); CHECK_SPI_REG(spi0, 0); CHECK_SPI_REG(spi1, 1); CHECK_SPI_REG(spi2, 2); CHECK_DT_REG(spi3, NRF_SPIM3); CHECK_DT_REG(spi4, NRF_SPIM4); -CHECK_DT_REG(spi00, NRF_SPIM00); -CHECK_DT_REG(spi20, NRF_SPIM20); -CHECK_DT_REG(spi21, NRF_SPIM21); -CHECK_DT_REG(spi22, NRF_SPIM22); -CHECK_DT_REG(spi30, NRF_SPIM30); -CHECK_DT_REG(spi120, NRF_SPIM120); -CHECK_DT_REG(spi121, NRF_SPIM121); -CHECK_DT_REG(spi130, NRF_SPIM130); -CHECK_DT_REG(spi131, NRF_SPIM131); -CHECK_DT_REG(spi132, NRF_SPIM132); -CHECK_DT_REG(spi133, NRF_SPIM133); -CHECK_DT_REG(spi134, NRF_SPIM134); -CHECK_DT_REG(spi135, NRF_SPIM135); -CHECK_DT_REG(spi136, NRF_SPIM136); -CHECK_DT_REG(spi137, NRF_SPIM137); CHECK_DT_REG(spu, NRF_SPU); CHECK_DT_REG(swi0, NRF_SWI0); CHECK_DT_REG(swi1, NRF_SWI1); @@ -266,19 +205,6 @@ CHECK_DT_REG(timer21, NRF_TIMER21); CHECK_DT_REG(timer22, NRF_TIMER22); CHECK_DT_REG(timer23, NRF_TIMER23); CHECK_DT_REG(timer24, NRF_TIMER24); -CHECK_DT_REG(timer020, NRF_TIMER020); -CHECK_DT_REG(timer021, NRF_TIMER021); -CHECK_DT_REG(timer022, NRF_TIMER022); -CHECK_DT_REG(timer120, NRF_TIMER120); -CHECK_DT_REG(timer121, NRF_TIMER121); -CHECK_DT_REG(timer130, NRF_TIMER130); -CHECK_DT_REG(timer131, NRF_TIMER131); -CHECK_DT_REG(timer132, NRF_TIMER132); -CHECK_DT_REG(timer133, NRF_TIMER133); -CHECK_DT_REG(timer134, NRF_TIMER134); -CHECK_DT_REG(timer135, NRF_TIMER135); -CHECK_DT_REG(timer136, NRF_TIMER136); -CHECK_DT_REG(timer137, NRF_TIMER137); CHECK_UART_REG(uart0, 0); CHECK_DT_REG(uart1, NRF_UARTE1); CHECK_DT_REG(uart2, NRF_UARTE2); @@ -306,8 +232,6 @@ CHECK_DT_REG(wdt0, NRF_WDT0); CHECK_DT_REG(wdt1, NRF_WDT1); CHECK_DT_REG(wdt30, NRF_WDT30); CHECK_DT_REG(wdt31, NRF_WDT31); -CHECK_DT_REG(wdt131, NRF_WDT131); -CHECK_DT_REG(wdt132, NRF_WDT132); /* nRF51/nRF52-specific addresses */ #if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X) From 762d11be686708dcf6f4f152057da0f14d08925b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:32 +0200 Subject: [PATCH 2285/2402] Revert "[nrf fromlist] dts: nordic: Add missing ECB020 node in nRF54H20 EngA" This reverts commit 8c7a4439115a0ff24f97b69309fce989d8cd8371. Signed-off-by: Gerard Marull-Paretas --- dts/common/nordic/nrf54h20_enga.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi index 8552b9534eb..47aba0df253 100644 --- a/dts/common/nordic/nrf54h20_enga.dtsi +++ b/dts/common/nordic/nrf54h20_enga.dtsi @@ -210,13 +210,6 @@ interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>; }; - ecb020: ecb@27000 { - compatible = "nordic,nrf-ecb"; - reg = <0x27000 0x1000>; - status = "disabled"; - interrupts = <39 NRF_DEFAULT_IRQ_PRIORITY>; - }; - timer020: timer@28000 { compatible = "nordic,nrf-timer"; reg = <0x28000 0x1000>; From c0660ab7e59aaf3372477f10772467eddc896e75 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:33 +0200 Subject: [PATCH 2286/2402] Revert "[nrf fromlist] dts: nordic: Add DPPIC and IPCT nodes to nRF54H20 EngA" This reverts commit 4663189d08d5c51238a60ed15996087a87b1526f. Signed-off-by: Gerard Marull-Paretas --- .../{misc => arm}/nordic,nrf-dppic.yaml | 0 .../{misc => arm}/nordic,nrf-ppi.yaml | 0 dts/bindings/ipc/nordic,nrf-ipct-common.yaml | 45 --------- dts/bindings/ipc/nordic,nrf-ipct-global.yaml | 17 ---- dts/bindings/ipc/nordic,nrf-ipct-local.yaml | 12 --- dts/bindings/{ipc => ipm}/nordic,nrf-ipc.yaml | 0 .../misc/nordic,nrf-dppic-global.yaml | 18 ---- dts/bindings/misc/nordic,nrf-dppic-links.yaml | 17 ---- dts/bindings/misc/nordic,nrf-dppic-local.yaml | 13 --- .../misc/nordic,split-channel-groups.yaml | 20 ---- dts/common/nordic/nrf54h20_enga.dtsi | 94 ------------------- 11 files changed, 236 deletions(-) rename dts/bindings/{misc => arm}/nordic,nrf-dppic.yaml (100%) rename dts/bindings/{misc => arm}/nordic,nrf-ppi.yaml (100%) delete mode 100644 dts/bindings/ipc/nordic,nrf-ipct-common.yaml delete mode 100644 dts/bindings/ipc/nordic,nrf-ipct-global.yaml delete mode 100644 dts/bindings/ipc/nordic,nrf-ipct-local.yaml rename dts/bindings/{ipc => ipm}/nordic,nrf-ipc.yaml (100%) delete mode 100644 dts/bindings/misc/nordic,nrf-dppic-global.yaml delete mode 100644 dts/bindings/misc/nordic,nrf-dppic-links.yaml delete mode 100644 dts/bindings/misc/nordic,nrf-dppic-local.yaml delete mode 100644 dts/bindings/misc/nordic,split-channel-groups.yaml diff --git a/dts/bindings/misc/nordic,nrf-dppic.yaml b/dts/bindings/arm/nordic,nrf-dppic.yaml similarity index 100% rename from dts/bindings/misc/nordic,nrf-dppic.yaml rename to dts/bindings/arm/nordic,nrf-dppic.yaml diff --git a/dts/bindings/misc/nordic,nrf-ppi.yaml b/dts/bindings/arm/nordic,nrf-ppi.yaml similarity index 100% rename from dts/bindings/misc/nordic,nrf-ppi.yaml rename to dts/bindings/arm/nordic,nrf-ppi.yaml diff --git a/dts/bindings/ipc/nordic,nrf-ipct-common.yaml b/dts/bindings/ipc/nordic,nrf-ipct-common.yaml deleted file mode 100644 index a75b63577c4..00000000000 --- a/dts/bindings/ipc/nordic,nrf-ipct-common.yaml +++ /dev/null @@ -1,45 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: Nordic IPCT (Interprocessor Communication Transceiver) - -include: base.yaml - -properties: - reg: - required: true - - channels: - type: int - required: true - description: Number of channels implemented by the IPCT instance. - - source-channel-links: - type: array - description: | - Mapping of IPCT channels that are mapped between two IPCT instances on - separate domains, in which a channel on this IPCT node is considered - the source. This array is then comprised of a 3-integer-wide "unit" - that defines one connection of the mapping. The format of this unit - is . Units are sequential - in the array, therefore requiring the length of this property to be - a factor of 3. - - For example, if channel 2 is to be mapped to Radio Core (ID: 3) IPCT - channel 4, then the array "unit" would be <2 NRF_DOMAIN_ID_RADIOCORE 4> - or <2 3 4>. - - sink-channel-links: - type: array - description: | - Mapping of IPCT channels that are mapped between two IPCT instances on - separate domains, in which a channel on this IPCT node is considered - the sink. This array is then comprised of a 3-integer-wide "unit" - that defines one connection of the mapping. The format of this unit - is . Units are sequential - in the array, therefore requiring the length of this property to be - a factor of 3. - - For example, if channel 2 is to be mapped to Radio Core (ID: 3) IPCT - channel 4, then the array "unit" would be <2 NRF_DOMAIN_ID_RADIOCORE 4> - or <2 3 4>. diff --git a/dts/bindings/ipc/nordic,nrf-ipct-global.yaml b/dts/bindings/ipc/nordic,nrf-ipct-global.yaml deleted file mode 100644 index a1f7776d464..00000000000 --- a/dts/bindings/ipc/nordic,nrf-ipct-global.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: Nordic Global IPCT (Interprocessor Communication Transceiver) - -compatible: "nordic,nrf-ipct-global" - -include: ["nordic,nrf-ipct-common.yaml", "nordic,split-channels.yaml"] - -properties: - global-domain-id: - required: true - type: int - description: | - Global IPCT instances reside on specific buses within the Global Domain, - such as fast and slow, which have different IDs that do not match the - standard Global Domain ID presented in their address. diff --git a/dts/bindings/ipc/nordic,nrf-ipct-local.yaml b/dts/bindings/ipc/nordic,nrf-ipct-local.yaml deleted file mode 100644 index 9f055eb8b79..00000000000 --- a/dts/bindings/ipc/nordic,nrf-ipct-local.yaml +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: Nordic Local IPCT (Interprocessor Communication Transceiver) - -compatible: "nordic,nrf-ipct-local" - -include: "nordic,nrf-ipct-common.yaml" - -properties: - interrupts: - required: true diff --git a/dts/bindings/ipc/nordic,nrf-ipc.yaml b/dts/bindings/ipm/nordic,nrf-ipc.yaml similarity index 100% rename from dts/bindings/ipc/nordic,nrf-ipc.yaml rename to dts/bindings/ipm/nordic,nrf-ipc.yaml diff --git a/dts/bindings/misc/nordic,nrf-dppic-global.yaml b/dts/bindings/misc/nordic,nrf-dppic-global.yaml deleted file mode 100644 index 3257c519348..00000000000 --- a/dts/bindings/misc/nordic,nrf-dppic-global.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: | - Nordic Global DPPIC - (Distributed Programmable Peripheral Interconnect Controller) - - Updated DPPIC binding set for Nordic products that have global DPPIC instances - with inter-bridge functionality. These instances also have split-ownership - of its channels and channel groups. - -compatible: "nordic,nrf-dppic-global" - -include: - - "nordic,nrf-dppic.yaml" - - "nordic,nrf-dppic-links.yaml" - - "nordic,split-channels.yaml" - - "nordic,split-channel-groups.yaml" diff --git a/dts/bindings/misc/nordic,nrf-dppic-links.yaml b/dts/bindings/misc/nordic,nrf-dppic-links.yaml deleted file mode 100644 index db12ccb72cb..00000000000 --- a/dts/bindings/misc/nordic,nrf-dppic-links.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: Nordic DPPIC Channel Linking - -properties: - source-channels: - type: array - description: | - Channels that are linked to channels of DPPIC instances on separate - bridges as publishing sources. - - sink-channels: - type: array - description: | - Channels that are linked to channels of DPPIC instances on separate - bridges as subscribing sinks. diff --git a/dts/bindings/misc/nordic,nrf-dppic-local.yaml b/dts/bindings/misc/nordic,nrf-dppic-local.yaml deleted file mode 100644 index bea53bddec8..00000000000 --- a/dts/bindings/misc/nordic,nrf-dppic-local.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause - -description: | - Nordic Local DPPIC - (Distributed Programmable Peripheral Interconnect Controller) - - Updated DPPIC binding set for Nordic products that have local DPPIC instances - with inter-bridge functionality. - -compatible: "nordic,nrf-dppic-local" - -include: ["nordic,nrf-dppic.yaml", "nordic,nrf-dppic-links.yaml"] diff --git a/dts/bindings/misc/nordic,split-channel-groups.yaml b/dts/bindings/misc/nordic,split-channel-groups.yaml deleted file mode 100644 index 868bc5fecec..00000000000 --- a/dts/bindings/misc/nordic,split-channel-groups.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: Nordic Split Channel Groups - -properties: - owned-channel-groups: - type: array - description: | - List of channel groups of a split-ownership peripheral that are to be - owned for use by the compiled domain. - - nonsecure-channel-groups: - type: array - description: | - List of channel groups in a split-ownership, split-security peripheral - that are to be configured as nonsecure. In Trustzone systems, this - property is only evaluated for secure peripherals, as nonsecure channels - are implicitly specified through the owned-channels property. This - property is ignored in non-Trustzone systems. diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi index 47aba0df253..70c994ccd06 100644 --- a/dts/common/nordic/nrf54h20_enga.dtsi +++ b/dts/common/nordic/nrf54h20_enga.dtsi @@ -9,12 +9,6 @@ #include -/* Domain IDs. Can be used to specify channel links in IPCT nodes. */ -#define NRF_DOMAIN_ID_APPLICATION 2 -#define NRF_DOMAIN_ID_RADIOCORE 3 -#define NRF_DOMAIN_ID_GLOBALFAST 12 -#define NRF_DOMAIN_ID_GLOBALSLOW 13 - /delete-node/ &sw_pwm; / { @@ -159,15 +153,6 @@ <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; nordic,ficr-names = "vsup", "coarse", "fine"; }; - - cpuapp_ipct: ipct@13000 { - compatible = "nordic,nrf-ipct-local"; - reg = <0x13000 0x1000>; - status = "disabled"; - channels = <4>; - interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, - <65 NRF_DEFAULT_IRQ_PRIORITY>; - }; }; cpurad_peripherals: peripheral@53000000 { @@ -188,21 +173,6 @@ nordic,ficr-names = "vsup", "coarse", "fine"; }; - dppic020: dppic@22000 { - compatible = "nordic,nrf-dppic-local"; - reg = <0x22000 0x1000>; - status = "disabled"; - }; - - cpurad_ipct: ipct@24000 { - compatible = "nordic,nrf-ipct-local"; - reg = <0x24000 0x1000>; - status = "disabled"; - channels = <8>; - interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, - <65 NRF_DEFAULT_IRQ_PRIORITY>; - }; - egu020: egu@25000 { compatible = "nordic,nrf-egu"; reg = <0x25000 0x1000>; @@ -297,20 +267,6 @@ #mbox-cells = <1>; }; - ipct120: ipct@8d1000 { - compatible = "nordic,nrf-ipct-global"; - reg = <0x8d1000 0x1000>; - status = "disabled"; - channels = <8>; - global-domain-id = <12>; - }; - - dppic120: dppic@8e1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x8e1000 0x1000>; - status = "disabled"; - }; - timer120: timer@8e2000 { compatible = "nordic,nrf-timer"; reg = <0x8e2000 0x1000>; @@ -388,20 +344,6 @@ }; }; - ipct130: ipct@921000 { - compatible = "nordic,nrf-ipct-global"; - reg = <0x921000 0x1000>; - status = "disabled"; - channels = <8>; - global-domain-id = <13>; - }; - - dppic130: dppic@922000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x922000 0x1000>; - status = "disabled"; - }; - rtc130: rtc@928000 { compatible = "nordic,nrf-rtc"; reg = <0x928000 0x1000>; @@ -507,12 +449,6 @@ port = <9>; }; - dppic131: dppic@981000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x981000 0x1000>; - status = "disabled"; - }; - comp: comparator@983000 { compatible = "nordic,nrf-comp"; reg = <0x983000 0x1000>; @@ -535,12 +471,6 @@ interrupts = <389 NRF_DEFAULT_IRQ_PRIORITY>; }; - dppic132: dppic@991000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x991000 0x1000>; - status = "disabled"; - }; - qdec130: qdec@994000 { compatible = "nordic,nrf-qdec"; reg = <0x994000 0x1000>; @@ -562,12 +492,6 @@ cc-num = <16>; }; - dppic133: dppic@9a1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9a1000 0x1000>; - status = "disabled"; - }; - timer130: timer@9a2000 { compatible = "nordic,nrf-timer"; reg = <0x9a2000 0x1000>; @@ -644,12 +568,6 @@ interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; }; - dppic134: dppic@9b1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9b1000 0x1000>; - status = "disabled"; - }; - timer132: timer@9b2000 { compatible = "nordic,nrf-timer"; reg = <0x9b2000 0x1000>; @@ -726,12 +644,6 @@ interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; }; - dppic135: dppic@9c1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9c1000 0x1000>; - status = "disabled"; - }; - timer134: timer@9c2000 { compatible = "nordic,nrf-timer"; reg = <0x9c2000 0x1000>; @@ -808,12 +720,6 @@ interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; }; - dppic136: dppic@9d1000 { - compatible = "nordic,nrf-dppic-global"; - reg = <0x9d1000 0x1000>; - status = "disabled"; - }; - timer136: timer@9d2000 { compatible = "nordic,nrf-timer"; reg = <0x9d2000 0x1000>; From b68b9890ad3f0d239afc53673f54ad7924ed07ad Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:33 +0200 Subject: [PATCH 2287/2402] Revert "[nrf fromtree] manifest: update hal_nordic revision" This reverts commit 20b7e5c80778c5162d8c040516b830593305d831. Signed-off-by: Gerard Marull-Paretas --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index a288009c15a..3da134e76ce 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: daf875285120be6b2825969b7a0abc3f415b248d + revision: dce8519f7da37b0a745237679fd3f88250b495ff path: modules/hal/nordic groups: - hal From f724dba59dab3ceb34ffcfd2bb5ab396e67a7d05 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:33 +0200 Subject: [PATCH 2288/2402] Revert "[nrf fromtree] dts: nordic: nrf54h20_enga: Add erase-block-size to mram1x" This reverts commit 77d21e0e54f3996c8318145912bb6e8556194917. Signed-off-by: Gerard Marull-Paretas --- dts/common/nordic/nrf54h20_enga.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi index 70c994ccd06..610fbd81587 100644 --- a/dts/common/nordic/nrf54h20_enga.dtsi +++ b/dts/common/nordic/nrf54h20_enga.dtsi @@ -96,7 +96,6 @@ mram1x: mram@e000000 { compatible = "nordic,mram"; reg = <0xe000000 DT_SIZE_K(2048)>; - erase-block-size = <4096>; write-block-size = <16>; }; From 3f7bd6c8a4b9e6a6417957917a1689e19c45cc12 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:33 +0200 Subject: [PATCH 2289/2402] Revert "[nrf fromtree] drivers: flash: Add flash driver for MRAM" This reverts commit 56e0ecf9ed3d45ec48e9c6f03f15bdb02417b432. Signed-off-by: Gerard Marull-Paretas --- drivers/flash/CMakeLists.txt | 1 - drivers/flash/Kconfig | 2 - drivers/flash/Kconfig.nrf_mram | 19 ---- drivers/flash/soc_flash_nrf_mram.c | 177 ----------------------------- 4 files changed, 199 deletions(-) delete mode 100644 drivers/flash/Kconfig.nrf_mram delete mode 100644 drivers/flash/soc_flash_nrf_mram.c diff --git a/drivers/flash/CMakeLists.txt b/drivers/flash/CMakeLists.txt index 98f24ff123c..4f21b2f65ed 100644 --- a/drivers/flash/CMakeLists.txt +++ b/drivers/flash/CMakeLists.txt @@ -129,4 +129,3 @@ zephyr_library_sources_ifdef(CONFIG_FLASH_JESD216 jesd216.c) zephyr_library_sources_ifdef(CONFIG_FLASH_INFINEON_CAT1 flash_ifx_cat1.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NUMAKER soc_flash_numaker.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_RRAM soc_flash_nrf_rram.c) -zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_MRAM soc_flash_nrf_mram.c) diff --git a/drivers/flash/Kconfig b/drivers/flash/Kconfig index 0c24890d44d..4731a628438 100644 --- a/drivers/flash/Kconfig +++ b/drivers/flash/Kconfig @@ -163,6 +163,4 @@ source "drivers/flash/Kconfig.ambiq" source "drivers/flash/Kconfig.nrf_rram" -source "drivers/flash/Kconfig.nrf_mram" - endif # FLASH diff --git a/drivers/flash/Kconfig.nrf_mram b/drivers/flash/Kconfig.nrf_mram deleted file mode 100644 index 0ef65864a62..00000000000 --- a/drivers/flash/Kconfig.nrf_mram +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2024 Nordic Semiconductor ASA -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_FLASH_NRF_MRAM - bool "Nordic Semiconductor flash driver for MRAM" - default y - depends on DT_HAS_NORDIC_MRAM_ENABLED - select FLASH_HAS_DRIVER_ENABLED - select FLASH_HAS_PAGE_LAYOUT - imply MPU_ALLOW_FLASH_WRITE if ARM_MPU - help - Enables Nordic Semiconductor flash driver for MRAM in direct write mode. - - Note that MRAM words are auto-erased when written to, but writing to a - pre-erased area is faster. Hence, the erase API is not required, but - it can be used to amortize write performance for some use cases. diff --git a/drivers/flash/soc_flash_nrf_mram.c b/drivers/flash/soc_flash_nrf_mram.c deleted file mode 100644 index 9b33ee05d6f..00000000000 --- a/drivers/flash/soc_flash_nrf_mram.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include -#include -#include - -LOG_MODULE_REGISTER(flash_nrf_mram, CONFIG_FLASH_LOG_LEVEL); - -#define DT_DRV_COMPAT nordic_mram - -#define MRAM_START DT_INST_REG_ADDR(0) -#define MRAM_SIZE DT_INST_REG_SIZE(0) - -#define MRAM_WORD_SIZE 16 -#define MRAM_WORD_MASK 0xf - -#define WRITE_BLOCK_SIZE DT_INST_PROP_OR(0, write_block_size, MRAM_WORD_SIZE) -#define ERASE_BLOCK_SIZE DT_INST_PROP_OR(0, erase_block_size, WRITE_BLOCK_SIZE) - -#define ERASE_VALUE 0xff - -BUILD_ASSERT(MRAM_START > 0, "nordic,mram: start address expected to be non-zero"); -BUILD_ASSERT((ERASE_BLOCK_SIZE % WRITE_BLOCK_SIZE) == 0, - "erase-block-size expected to be a multiple of write-block-size"); - -/** - * @param[in,out] offset Relative offset into memory, from the driver API. - * @param[in] len Number of bytes for the intended operation. - * @param[in] must_align Require MRAM word alignment, if applicable. - * - * @return Absolute address in MRAM, or NULL if @p offset or @p len are not - * within bounds or appropriately aligned. - */ -static uintptr_t validate_and_map_addr(off_t offset, size_t len, bool must_align) -{ - if (unlikely(offset < 0 || offset >= MRAM_SIZE || len > MRAM_SIZE - offset)) { - LOG_ERR("invalid offset: %ld:%zu", offset, len); - return 0; - } - - const uintptr_t addr = MRAM_START + offset; - - if (WRITE_BLOCK_SIZE > 1 && must_align && - unlikely((addr % WRITE_BLOCK_SIZE) != 0 || (len % WRITE_BLOCK_SIZE) != 0)) { - LOG_ERR("invalid alignment: %p:%zu", (void *)addr, len); - return 0; - } - - return addr; -} - -/** - * @param[in] addr_end Last modified MRAM address (not inclusive). - */ -static void commit_changes(uintptr_t addr_end) -{ - /* Barrier following our last write. */ - barrier_dmem_fence_full(); - - if ((WRITE_BLOCK_SIZE & MRAM_WORD_MASK) == 0 || (addr_end & MRAM_WORD_MASK) == 0) { - /* Our last operation was MRAM word-aligned, so we're done. - * Note: if WRITE_BLOCK_SIZE is a multiple of MRAM_WORD_SIZE, - * then this was already checked in validate_and_map_addr(). - */ - return; - } - - /* Get the most significant byte (MSB) of the last MRAM word we were modifying. - * Writing to this byte makes the MRAM controller commit other pending writes to that word. - */ - addr_end |= MRAM_WORD_MASK; - - /* Issue a dummy write, since we didn't have anything to write here. - * Doing this lets us finalize our changes before we exit the driver API. - */ - sys_write8(sys_read8(addr_end), addr_end); -} - -static int nrf_mram_read(const struct device *dev, off_t offset, void *data, size_t len) -{ - ARG_UNUSED(dev); - - const uintptr_t addr = validate_and_map_addr(offset, len, false); - - if (!addr) { - return -EINVAL; - } - - LOG_DBG("read: %p:%zu", (void *)addr, len); - - memcpy(data, (void *)addr, len); - - return 0; -} - -static int nrf_mram_write(const struct device *dev, off_t offset, const void *data, size_t len) -{ - ARG_UNUSED(dev); - - const uintptr_t addr = validate_and_map_addr(offset, len, true); - - if (!addr) { - return -EINVAL; - } - - LOG_DBG("write: %p:%zu", (void *)addr, len); - - memcpy((void *)addr, data, len); - commit_changes(addr + len); - - return 0; -} - -static int nrf_mram_erase(const struct device *dev, off_t offset, size_t size) -{ - ARG_UNUSED(dev); - - const uintptr_t addr = validate_and_map_addr(offset, size, true); - - if (!addr) { - return -EINVAL; - } - - LOG_DBG("erase: %p:%zu", (void *)addr, size); - - memset((void *)addr, ERASE_VALUE, size); - commit_changes(addr + size); - - return 0; -} - -static const struct flash_parameters *nrf_mram_get_parameters(const struct device *dev) -{ - ARG_UNUSED(dev); - - static const struct flash_parameters parameters = { - .write_block_size = WRITE_BLOCK_SIZE, - .erase_value = ERASE_VALUE, - }; - - return ¶meters; -} - -#if defined(CONFIG_FLASH_PAGE_LAYOUT) -static void nrf_mram_page_layout(const struct device *dev, const struct flash_pages_layout **layout, - size_t *layout_size) -{ - ARG_UNUSED(dev); - - static const struct flash_pages_layout pages_layout = { - .pages_count = (MRAM_SIZE) / (ERASE_BLOCK_SIZE), - .pages_size = ERASE_BLOCK_SIZE, - }; - - *layout = &pages_layout; - *layout_size = 1; -} -#endif - -static const struct flash_driver_api nrf_mram_api = { - .read = nrf_mram_read, - .write = nrf_mram_write, - .erase = nrf_mram_erase, - .get_parameters = nrf_mram_get_parameters, -#if defined(CONFIG_FLASH_PAGE_LAYOUT) - .page_layout = nrf_mram_page_layout, -#endif -}; - -DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, NULL, POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY, - &nrf_mram_api); From 150d71dcbef11c4a775e3539beeb12c866d2bdeb Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:33 +0200 Subject: [PATCH 2290/2402] Revert "[nrf fromtree] drivers: modem_cellular: allow leaving out the chat_filter parameter" This reverts commit a102df7e8a2063d226767bc7c705d5f20e9630ef. Signed-off-by: Gerard Marull-Paretas --- drivers/modem/modem_cellular.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 15f10f11a52..276c9d38f7b 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -1516,7 +1516,7 @@ static int modem_cellular_init(const struct device *dev) .delimiter = data->chat_delimiter, .delimiter_size = strlen(data->chat_delimiter), .filter = data->chat_filter, - .filter_size = data->chat_filter ? strlen(data->chat_filter) : 0, + .filter_size = strlen(data->chat_filter), .argv = data->chat_argv, .argv_size = ARRAY_SIZE(data->chat_argv), .unsol_matches = unsol_matches, From aa1f23bf290473046b564f409b0dd8890a3a5178 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:34 +0200 Subject: [PATCH 2291/2402] Revert "[nrf fromlist] buildsystem: Enable LTO also for the application" This reverts commit 3f9065356fe91353311ebec8924471071a8a4131. Signed-off-by: Gerard Marull-Paretas --- CMakeLists.txt | 2 +- lib/libc/newlib/CMakeLists.txt | 3 --- lib/libc/picolibc/CMakeLists.txt | 3 --- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index a229c06413e..f1fb89660f9 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -214,7 +214,7 @@ endif() zephyr_compile_options(${OPTIMIZATION_FLAG}) if(CONFIG_LTO) - zephyr_compile_options($) + add_compile_options($) add_link_options($) endif() diff --git a/lib/libc/newlib/CMakeLists.txt b/lib/libc/newlib/CMakeLists.txt index 35c6a9b6337..6556a3e814c 100644 --- a/lib/libc/newlib/CMakeLists.txt +++ b/lib/libc/newlib/CMakeLists.txt @@ -3,9 +3,6 @@ zephyr_library() zephyr_library_sources(libc-hooks.c) -# Do not allow LTO when compiling libc-hooks.c file -set_source_files_properties(libc-hooks.c PROPERTIES COMPILE_OPTIONS $) - # Zephyr normally uses -ffreestanding, which with current GNU toolchains # means that the flag macros used by newlib 3.x to signal # support for PRI.64 macros are not present. To make them available we diff --git a/lib/libc/picolibc/CMakeLists.txt b/lib/libc/picolibc/CMakeLists.txt index 87fb0d9d8ec..23e84231e2a 100644 --- a/lib/libc/picolibc/CMakeLists.txt +++ b/lib/libc/picolibc/CMakeLists.txt @@ -3,9 +3,6 @@ zephyr_library() zephyr_library_sources(libc-hooks.c) -# Do not allow LTO when compiling libc-hooks.c file -set_source_files_properties(libc-hooks.c PROPERTIES COMPILE_OPTIONS $) - # define __LINUX_ERRNO_EXTENSIONS__ so we get errno defines like -ESHUTDOWN # used by the network stack zephyr_compile_definitions(__LINUX_ERRNO_EXTENSIONS__) From a1012e5a26778be0207de31cb8b13bdfc938c617 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:34 +0200 Subject: [PATCH 2292/2402] Revert "[nrf fromlist] linker: Set ROM offset for MCUboot with NRF54L" This reverts commit 3701af0b87579c566c128e90c1c3e1c9302be191. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig b/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig index 3e47a0bb583..532ea07c859 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig +++ b/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig @@ -9,8 +9,4 @@ config BOARD config BT_CTLR default BT -config ROM_START_OFFSET - hex - default 0x800 if BOOTLOADER_MCUBOOT - endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP From 58122e75538220f2d639dfe7e453f8b6b36728e7 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:34 +0200 Subject: [PATCH 2293/2402] Revert "[nrf fromlist] dts: arm: add uart-mcumgr choosen for 54L15" This reverts commit ce7a9abbc9ebb852644e1fe1207a6547006de700. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts index 9876e3996e8..f2703872899 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -16,7 +16,6 @@ chosen { zephyr,console = &uart20; zephyr,shell-uart = &uart20; - zephyr,uart-mcumgr = &uart20; zephyr,sram = &sram0; zephyr,flash = &rram0; zephyr,code-partition = &slot0_partition; From 221bac446d7746fdcf5a7aa0a8f6d1c6acfdfd1b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:34 +0200 Subject: [PATCH 2294/2402] Revert "[nrf fromlist] dts: arm: nrf54l: Add nodes required by MCUboot" This reverts commit 74208ee8f77c0184758a48128afd1a45fc133cb6. Signed-off-by: Gerard Marull-Paretas --- .../nrf54l15pdk_nrf54l15_cpuapp.dts | 25 +++---------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts index f2703872899..1e0245f6cc3 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -133,30 +133,13 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 DT_SIZE_K(64)>; - }; - slot0_partition: partition@10000 { + slot0_partition: partition@0 { label = "image-0"; - reg = <0x10000 DT_SIZE_K(348)>; - }; - slot0_ns_partition: partition@67000 { - label = "image-0-nonsecure"; - reg = <0x67000 DT_SIZE_K(348)>; - }; - slot1_partition: partition@be000 { - label = "image-1"; - reg = <0xbe000 DT_SIZE_K(348)>; - }; - slot1_ns_partition: partition@115000 { - label = "image-1-nonsecure"; - reg = <0x115000 DT_SIZE_K(348)>; + reg = <0x0 DT_SIZE_K(64)>; }; - /* 32k from 0x16c000 to 0x173fff reserved for TF-M partitions */ - storage_partition: partition@174000 { + storage_partition: partition@f2000 { label = "storage"; - reg = <0x174000 DT_SIZE_K(36)>; + reg = <0xf2000 DT_SIZE_K(24)>; }; }; }; From 4213173f5c4026064093ce5dd4b90e453c183b6f Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:34 +0200 Subject: [PATCH 2295/2402] Revert "[nrf fromlist] samples: drivers: mbox: add support for nRF BELLBOARD" This reverts commit ae6525bb4e7e294fd629240de7f88f8bd52c64cd. Signed-off-by: Gerard Marull-Paretas --- ...nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf | 1 - ...54h20pdk_nrf54h20_cpuapp_bellboard.overlay | 8 -------- ...nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf | 1 - ...54h20pdk_nrf54h20_cpuppr_bellboard.overlay | 8 -------- samples/drivers/mbox/sample.yaml | 20 ------------------- 5 files changed, 38 deletions(-) delete mode 100644 samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf delete mode 100644 samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay delete mode 100644 samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf delete mode 100644 samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf deleted file mode 100644 index 0b6bc73d6bc..00000000000 --- a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_TX_ENABLED=n diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay deleted file mode 100644 index 5f0cfe2261d..00000000000 --- a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -mbox: &cpuapp_bellboard { - status = "okay"; -}; diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf deleted file mode 100644 index 4596bc3a757..00000000000 --- a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_RX_ENABLED=n diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay deleted file mode 100644 index 5f0cfe2261d..00000000000 --- a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -mbox: &cpuapp_bellboard { - status = "okay"; -}; diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml index b386b9d2b4b..8c85a8d5150 100644 --- a/samples/drivers/mbox/sample.yaml +++ b/samples/drivers/mbox/sample.yaml @@ -44,26 +44,6 @@ tests: - "Ping \\(on channel 4\\)" - "Pong \\(on channel 4\\)" - sample.drivers.mbox.nrf54h20_bellboard: - platform_allow: - - nrf54h20pdk_nrf54h20_cpuapp - integration_platforms: - - nrf54h20pdk_nrf54h20_cpuapp - extra_args: - mbox_SNIPPET=nordic-ppr - mbox_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.conf - mbox_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_bellboard.overlay - remote_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.conf - remote_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_bellboard.overlay - sysbuild: true - harness: console - harness_config: - type: multi_line - ordered: false - regex: - - "Ping \\(on channel 0\\)" - - "Pong \\(on channel 0\\)" - sample.drivers.mbox.simu: platform_allow: - nrf5340bsim_nrf5340_cpuapp From 66170b8b331740fe280721f4e96046b9ebf9752b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:35 +0200 Subject: [PATCH 2296/2402] Revert "[nrf fromlist] samples: drivers: mbox: add support for nRF VEVIF" This reverts commit 1ee5a6fb10567a1a47f749f3a2bcc4d56e9d772e. Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/CMakeLists.txt | 3 +-- samples/drivers/mbox/Kconfig.sysbuild | 1 - .../nrf54h20pdk_nrf54h20_cpuapp_vevif.conf | 2 -- .../nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay | 8 ------- samples/drivers/mbox/remote/CMakeLists.txt | 3 +-- .../nrf54h20pdk_nrf54h20_cpuppr_vevif.conf | 2 -- .../nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay | 8 ------- samples/drivers/mbox/sample.yaml | 21 ------------------- 8 files changed, 2 insertions(+), 46 deletions(-) delete mode 100644 samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf delete mode 100644 samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay delete mode 100644 samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf delete mode 100644 samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay diff --git a/samples/drivers/mbox/CMakeLists.txt b/samples/drivers/mbox/CMakeLists.txt index c69621c2496..ec79db9deed 100644 --- a/samples/drivers/mbox/CMakeLists.txt +++ b/samples/drivers/mbox/CMakeLists.txt @@ -17,8 +17,7 @@ if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp") OR ("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7") OR ("${BOARD}" STREQUAL "mimxrt1170_evk_cm7") OR ("${BOARD}" STREQUAL "mimxrt1160_evk_cm7") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu0") OR - ("${BOARD}" STREQUAL "nrf54h20pdk_nrf54h20_cpuapp")) + ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu0")) message(STATUS "${BOARD} compile as Main in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/Kconfig.sysbuild b/samples/drivers/mbox/Kconfig.sysbuild index aca48b8ead3..a17dd56ee55 100644 --- a/samples/drivers/mbox/Kconfig.sysbuild +++ b/samples/drivers/mbox/Kconfig.sysbuild @@ -14,4 +14,3 @@ string default "mimxrt1170_evk_cm4" if $(BOARD) = "mimxrt1170_evk_cm7" default "mimxrt1160_evk_cm4" if $(BOARD) = "mimxrt1160_evk_cm7" default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" - default "nrf54h20pdk_nrf54h20_cpuppr" if $(BOARD) = "nrf54h20pdk_nrf54h20_cpuapp" diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf deleted file mode 100644 index d8d66e9812d..00000000000 --- a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_RX_ENABLED=n -CONFIG_TX_CHANNEL_ID=4 diff --git a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay b/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay deleted file mode 100644 index ed631f04cc3..00000000000 --- a/samples/drivers/mbox/boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -mbox: &cpuppr_vevif { - status = "okay"; -}; diff --git a/samples/drivers/mbox/remote/CMakeLists.txt b/samples/drivers/mbox/remote/CMakeLists.txt index cb024cb6112..2c7c8fff29e 100644 --- a/samples/drivers/mbox/remote/CMakeLists.txt +++ b/samples/drivers/mbox/remote/CMakeLists.txt @@ -15,8 +15,7 @@ if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpunet") OR ("${BOARD}" STREQUAL "mimxrt1170_evk_cm4") OR ("${BOARD}" STREQUAL "mimxrt1160_evk_cm4") OR ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu1") OR - ("${BOARD}" STREQUAL "adp_xc7k_ae350") OR - ("${BOARD}" STREQUAL "nrf54h20pdk_nrf54h20_cpuppr")) + ("${BOARD}" STREQUAL "adp_xc7k_ae350")) message(STATUS "${BOARD} compile as remote in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf deleted file mode 100644 index 19e03b75c63..00000000000 --- a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_TX_ENABLED=n -CONFIG_RX_CHANNEL_ID=4 diff --git a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay b/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay deleted file mode 100644 index ed631f04cc3..00000000000 --- a/samples/drivers/mbox/remote/boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -mbox: &cpuppr_vevif { - status = "okay"; -}; diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml index 8c85a8d5150..e38deda55d3 100644 --- a/samples/drivers/mbox/sample.yaml +++ b/samples/drivers/mbox/sample.yaml @@ -23,27 +23,6 @@ tests: - "Pong \\(on channel 0\\)" - "Ping \\(on channel 1\\)" - "Pong \\(on channel 1\\)" - - sample.drivers.mbox.nrf54h20_vevif: - platform_allow: - - nrf54h20pdk_nrf54h20_cpuapp - integration_platforms: - - nrf54h20pdk_nrf54h20_cpuapp - extra_args: - mbox_SNIPPET=nordic-ppr - mbox_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.conf - mbox_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuapp_vevif.overlay - remote_EXTRA_CONF_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.conf - remote_DTC_OVERLAY_FILE=boards/nrf54h20pdk_nrf54h20_cpuppr_vevif.overlay - sysbuild: true - harness: console - harness_config: - type: multi_line - ordered: false - regex: - - "Ping \\(on channel 4\\)" - - "Pong \\(on channel 4\\)" - sample.drivers.mbox.simu: platform_allow: - nrf5340bsim_nrf5340_cpuapp From 83b4d4fd8308b56d9587d13a95a81f2332aa4635 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:35 +0200 Subject: [PATCH 2297/2402] Revert "[nrf fromlist] boards: nrf54h20pdk: Add default IPC configuration" This reverts commit b6e4ad45786e4b775409c07fcc7ffdbf9865a1f3. Signed-off-by: Gerard Marull-Paretas --- .../nrf54h20pdk_nrf54h20-ipc_conf.dtsi | 36 ------------------- .../nrf54h20pdk_nrf54h20_cpuapp.dts | 29 --------------- .../nrf54h20pdk_nrf54h20_cpurad.dts | 24 ------------- .../nrf54h20pdk_nrf54h20_cpuppr.dts | 11 ------ 4 files changed, 100 deletions(-) delete mode 100644 boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-ipc_conf.dtsi diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-ipc_conf.dtsi b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-ipc_conf.dtsi deleted file mode 100644 index 9c3d971b9bc..00000000000 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-ipc_conf.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - ipc { - cpusec_cpuapp_ipc: ipc-1-2 { - compatible = "zephyr,ipc-icmsg"; - status = "disabled"; - mboxes = <&cpusec_bellboard 12>, - <&cpuapp_bellboard 0>; - }; - - cpusec_cpurad_ipc: ipc-1-3 { - compatible = "zephyr,ipc-icmsg"; - status = "disabled"; - mboxes = <&cpusec_bellboard 18>, - <&cpurad_bellboard 0>; - }; - - cpuapp_cpurad_ipc: ipc-2-3 { - status = "disabled"; - mboxes = <&cpuapp_bellboard 18>, - <&cpurad_bellboard 12>; - }; - - cpuapp_cpuppr_ipc: ipc-2-13 { - compatible = "zephyr,ipc-icmsg"; - status = "disabled"; - mboxes = <&cpuapp_bellboard 13>, - <&cpuppr_vevif 12>; - }; - }; -}; diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts index b2db9e4b9b1..0251fbded25 100644 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts @@ -8,11 +8,8 @@ #include #include "nrf54h20pdk_nrf54h20-memory_map.dtsi" -#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" #include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" -/delete-node/ &cpusec_cpurad_ipc; - / { compatible = "nordic,nrf54h20pdk_nrf54h20-cpuapp"; model = "Nordic nRF54H20 PDK nRF54H20 Application MCU"; @@ -96,32 +93,6 @@ status = "okay"; }; -&cpuapp_bellboard { - interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; - interrupt-names = "irq0"; - /* irq0: 0: cpuapp-cpusec, 13: cpuapp-cpuppr, 18: cpuapp-cpurad */ - nordic,interrupt-mapping = <0x00042001 0>; -}; - -&cpusec_cpuapp_ipc { - mbox-names = "tx", "rx"; - tx-region = <&cpuapp_cpusec_ipc_shm>; - rx-region = <&cpusec_cpuapp_ipc_shm>; -}; - -&cpuapp_cpurad_ipc { - compatible = "zephyr,ipc-icmsg-me-initiator"; - mbox-names = "rx", "tx"; - tx-region = <&cpuapp_cpurad_ipc_shm>; - rx-region = <&cpurad_cpuapp_ipc_shm>; -}; - -&cpuapp_cpuppr_ipc { - mbox-names = "rx", "tx"; - tx-region = <&cpuapp_cpuppr_ipc_shm>; - rx-region = <&cpuppr_cpuapp_ipc_shm>; -}; - &cpuapp_dma_region { status = "okay"; }; diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts index 8d2629df62e..d639847e197 100644 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts @@ -8,12 +8,8 @@ #include #include "nrf54h20pdk_nrf54h20-memory_map.dtsi" -#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" #include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" -/delete-node/ &cpuapp_cpuppr_ipc; -/delete-node/ &cpusec_cpuapp_ipc; - / { compatible = "nordic,nrf54h20pdk_nrf54h20-cpurad"; model = "Nordic nRF54H20 PDK nRF54H20 Radio MCU"; @@ -30,26 +26,6 @@ status = "okay"; }; -&cpurad_bellboard { - interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; - interrupt-names = "irq0"; - /* irq0: 0: cpurad-cpusec, 12: cpurad-cpuapp */ - nordic,interrupt-mapping = <0x00001001 0>; -}; - -&cpusec_cpurad_ipc { - mbox-names = "tx", "rx"; - tx-region = <&cpurad_cpusec_ipc_shm>; - rx-region = <&cpusec_cpurad_ipc_shm>; -}; - -&cpuapp_cpurad_ipc { - compatible = "zephyr,ipc-icmsg-me-follower"; - mbox-names = "tx", "rx"; - tx-region = <&cpurad_cpuapp_ipc_shm>; - rx-region = <&cpuapp_cpurad_ipc_shm>; -}; - &cpurad_dma_region { status = "okay"; }; diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts b/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts index f98abb9e44b..3c74e7c88d4 100644 --- a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts +++ b/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts @@ -8,13 +8,8 @@ #include #include "nrf54h20pdk_nrf54h20-memory_map.dtsi" -#include "nrf54h20pdk_nrf54h20-ipc_conf.dtsi" #include "nrf54h20pdk_nrf54h20-pinctrl.dtsi" -/delete-node/ &cpuapp_cpurad_ipc; -/delete-node/ &cpusec_cpuapp_ipc; -/delete-node/ &cpusec_cpurad_ipc; - / { compatible = "nordic,nrf54h20pdk_nrf54h20-cpuppr"; model = "Nordic nRF54H20 PDK nRF54H20 Peripheral Processor MCU"; @@ -29,12 +24,6 @@ }; }; -&cpuapp_cpuppr_ipc { - mbox-names = "tx", "rx"; - tx-region = <&cpuppr_cpuapp_ipc_shm>; - rx-region = <&cpuapp_cpuppr_ipc_shm>; -}; - &grtc { status = "okay"; owned-channels = <5>; From c9593e9a005d02a1f3c2166f23e552373fc65975 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:35 +0200 Subject: [PATCH 2298/2402] Revert "[nrf fromlist] boards: nrf54h20pdk_nrf54h20: Update memory map" This reverts commit cfb31b2e6478d63adaf771c9a2d9ccff14428b38. Signed-off-by: Gerard Marull-Paretas --- .../nrf54h20pdk_nrf54h20-memory_map.dtsi | 100 +----------------- .../nrf54h20pdk_nrf54h20_cpuapp.dts | 8 +- .../nrf54h20pdk_nrf54h20_cpurad.dts | 2 +- 3 files changed, 4 insertions(+), 106 deletions(-) diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi index 560700b1756..cb5a4fe0b0c 100644 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi @@ -6,96 +6,6 @@ / { reserved-memory { - cpuapp_ram0x_region: memory@2f000000 { - compatible = "nordic,owned-memory"; - reg = <0x2f000000 DT_SIZE_K(260)>; - status = "disabled"; - perm-read; - perm-write; - perm-secure; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f000000 0x41000>; - - cpusec_cpuapp_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; - - cpuapp_cpusec_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; - - cpuapp_data: memory@1000 { - reg = <0x1000 DT_SIZE_K(256)>; - }; - }; - - cpurad_ram0x_region: memory@2f041000 { - compatible = "nordic,owned-memory"; - reg = <0x2f041000 DT_SIZE_K(4)>; - status = "disabled"; - perm-read; - perm-write; - perm-secure; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f041000 0x1000>; - - cpusec_cpurad_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; - - cpurad_cpusec_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; - }; - - cpuapp_cpurad_ram0x_region: memory@2f0bf000 { - compatible = "nordic,owned-memory"; - reg = <0x2f0bf000 DT_SIZE_K(4)>; - status = "disabled"; - perm-read; - perm-write; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f0bf000 0x1000>; - - cpuapp_cpurad_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; - - cpurad_cpuapp_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; - }; - - shared_ram20_region: memory@2f88f000 { - compatible = "nordic,owned-memory"; - reg = <0x2f88f000 DT_SIZE_K(4)>; - status = "disabled"; - perm-read; - perm-write; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f88f000 0x1000>; - - cpuapp_cpusys_ipc_shm: memory@ce0 { - reg = <0xce0 0x80>; - }; - - cpusys_cpuapp_ipc_shm: memory@d60 { - reg = <0xd60 0x80>; - }; - - cpurad_cpusys_ipc_shm: memory@e00 { - reg = <0xe00 0x80>; - }; - - cpusys_cpurad_ipc_shm: memory@e80 { - reg = <0xe80 0x80>; - }; - }; - cpuppr_ram3x_region: memory@2fc00000 { compatible = "nordic,owned-memory"; reg = <0x2fc00000 DT_SIZE_K(28)>; @@ -105,7 +15,7 @@ perm-execute; }; - shared_ram3x_region: memory@2fc07000 { + ram3x_dma_region: memory@2fc07000 { compatible = "nordic,owned-memory"; reg = <0x2fc07000 DT_SIZE_K(4)>; status = "disabled"; @@ -115,14 +25,6 @@ #size-cells = <1>; ranges = <0x0 0x2fc07000 0x1000>; - cpuapp_cpuppr_ipc_shm: memory@0 { - reg = <0x0 0x340>; - }; - - cpuppr_cpuapp_ipc_shm: memory@340 { - reg = <0x340 0x340>; - }; - cpuapp_dma_region: memory@680 { compatible = "zephyr,memory-region"; reg = <0x680 DT_SIZE_K(2)>; diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts index 0251fbded25..8500d22a924 100644 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts @@ -18,7 +18,7 @@ zephyr,console = &uart136; zephyr,code-partition = &cpuapp_slot0_partition; zephyr,flash = &mram1x; - zephyr,sram = &cpuapp_data; + zephyr,sram = &cpuapp_ram0; }; aliases { @@ -85,11 +85,7 @@ }; }; -&cpuapp_ram0x_region { - status = "okay"; -}; - -&shared_ram3x_region { +&ram3x_dma_region { status = "okay"; }; diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts index d639847e197..a7d142b06c4 100644 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts +++ b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts @@ -22,7 +22,7 @@ }; }; -&shared_ram3x_region { +&ram3x_dma_region { status = "okay"; }; From 9a57a2fae2c7d937cabeb4b01c4ab84fcb2b40e9 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:35 +0200 Subject: [PATCH 2299/2402] Revert "[nrf fromlist] dts: nordic: nrf54h20_enga: add PPR VEVIF nodes" This reverts commit 63bf0c42728cfc861e1ee5cc1e2615df445eff6e. Signed-off-by: Gerard Marull-Paretas --- dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi | 1 - dts/arm/nordic/nrf54h20_enga_cpurad.dtsi | 1 - dts/common/nordic/nrf54h20_enga.dtsi | 34 ---------------------- dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi | 1 - 4 files changed, 37 deletions(-) diff --git a/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi b/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi index 7252b3d5a04..25585659968 100644 --- a/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi +++ b/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi @@ -9,7 +9,6 @@ cpu: &cpuapp {}; systick: &cpuapp_systick {}; nvic: &cpuapp_nvic {}; -cpuppr_vevif: &cpuppr_vevif_remote {}; /delete-node/ &cpuppr; /delete-node/ &cpurad; diff --git a/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi b/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi index d2aaa790349..e51ce316c3f 100644 --- a/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi +++ b/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi @@ -9,7 +9,6 @@ cpu: &cpurad {}; systick: &cpurad_systick {}; nvic: &cpurad_nvic {}; -cpuppr_vevif: &cpuppr_vevif_remote {}; /delete-node/ &cpuapp; /delete-node/ &cpuapp_peripherals; diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi index 610fbd81587..3a8a5759268 100644 --- a/dts/common/nordic/nrf54h20_enga.dtsi +++ b/dts/common/nordic/nrf54h20_enga.dtsi @@ -40,31 +40,6 @@ clock-frequency = ; riscv,isa = "rv32emc"; nordic,bus-width = <32>; - - cpuppr_vevif_local: mailbox { - compatible = "nordic,nrf-vevif-local"; - status = "disabled"; - interrupt-parent = <&cpuppr_clic>; - interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, - <1 NRF_DEFAULT_IRQ_PRIORITY>, - <2 NRF_DEFAULT_IRQ_PRIORITY>, - <3 NRF_DEFAULT_IRQ_PRIORITY>, - <4 NRF_DEFAULT_IRQ_PRIORITY>, - <5 NRF_DEFAULT_IRQ_PRIORITY>, - <6 NRF_DEFAULT_IRQ_PRIORITY>, - <7 NRF_DEFAULT_IRQ_PRIORITY>, - <8 NRF_DEFAULT_IRQ_PRIORITY>, - <9 NRF_DEFAULT_IRQ_PRIORITY>, - <10 NRF_DEFAULT_IRQ_PRIORITY>, - <11 NRF_DEFAULT_IRQ_PRIORITY>, - <12 NRF_DEFAULT_IRQ_PRIORITY>, - <13 NRF_DEFAULT_IRQ_PRIORITY>, - <14 NRF_DEFAULT_IRQ_PRIORITY>, - <15 NRF_DEFAULT_IRQ_PRIORITY>; - #mbox-cells = <1>; - nordic,tasks = <16>; - nordic,tasks-mask = <0xfffffff0>; - }; }; }; @@ -324,15 +299,6 @@ #size-cells = <1>; ranges = <0x0 0x908000 0x4000>; - cpuppr_vevif_remote: mailbox@0 { - compatible = "nordic,nrf-vevif-remote"; - reg = <0x0 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - nordic,tasks = <16>; - nordic,tasks-mask = <0xfffffff0>; - }; - cpuppr_clic: interrupt-controller@1000 { compatible = "nordic,nrf-clic"; reg = <0x1000 0x3000>; diff --git a/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi b/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi index 0af6618688f..dcefe95885c 100644 --- a/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi +++ b/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi @@ -8,7 +8,6 @@ cpu: &cpuppr {}; clic: &cpuppr_clic {}; -cpuppr_vevif: &cpuppr_vevif_local {}; /delete-node/ &cpuapp; /delete-node/ &cpuapp_peripherals; From 808032d592bf98a39e2209b353d44e19038c86e7 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:35 +0200 Subject: [PATCH 2300/2402] Revert "[nrf fromlist] boards: arm: nrf9151dk: fix broken link" This reverts commit 11dad4da8b5634b4a3a040fe22416a6d3ae17880. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf9151dk_nrf9151/doc/index.rst | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/boards/arm/nrf9151dk_nrf9151/doc/index.rst b/boards/arm/nrf9151dk_nrf9151/doc/index.rst index 91e9b75ad9c..4c02e7ed372 100644 --- a/boards/arm/nrf9151dk_nrf9151/doc/index.rst +++ b/boards/arm/nrf9151dk_nrf9151/doc/index.rst @@ -26,7 +26,9 @@ Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: * :abbr:`WDT (Watchdog Timer)` * :abbr:`IDAU (Implementation Defined Attribution Unit)` -More information about the board can be found at the `nRF9151 website`_. +More information about the board can be found at the +`nRF9151 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. Hardware @@ -82,7 +84,8 @@ hardware features: .. _nrf9151dk_additional_hardware: Other hardware features have not been enabled yet for this board. -See the `nRF9151 website`_ for more information. +See `nRF9151 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF9151 DK board hardware features. Connections and IOs =================== @@ -195,6 +198,6 @@ References .. _IDAU: https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _nRF9151 website: https://www.nordicsemi.com/Products/nRF9151 +.. _nRF9151 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9151-DK .. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com .. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ From 007e8a400adfa6a7036b0c226a874afdbda6a17e Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:36 +0200 Subject: [PATCH 2301/2402] Revert "[nrf fromlist] dts: nordic: nrf54h20_enga: add BELLBOARD nodes" This reverts commit 077d1b2c473a0abccf9c7fc31cbac6eb23f60d27. Signed-off-by: Gerard Marull-Paretas --- dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi | 12 ------------ dts/arm/nordic/nrf54h20_enga_cpurad.dtsi | 12 ------------ dts/common/nordic/nrf54h20_enga.dtsi | 18 ------------------ dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi | 12 ------------ 4 files changed, 54 deletions(-) diff --git a/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi b/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi index 25585659968..f51528d5733 100644 --- a/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi +++ b/dts/arm/nordic/nrf54h20_enga_cpuapp.dtsi @@ -29,18 +29,6 @@ nvic: &cpuapp_nvic {}; ranges; }; -&cpusec_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpuapp_bellboard { - compatible = "nordic,nrf-bellboard-local"; -}; - -&cpurad_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - &gpiote130 { interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; }; diff --git a/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi b/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi index e51ce316c3f..cb2767381da 100644 --- a/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi +++ b/dts/arm/nordic/nrf54h20_enga_cpurad.dtsi @@ -29,18 +29,6 @@ nvic: &cpurad_nvic {}; ranges; }; -&cpusec_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpuapp_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpurad_bellboard { - compatible = "nordic,nrf-bellboard-local"; -}; - &gpiote130 { interrupts = <105 NRF_DEFAULT_IRQ_PRIORITY>; }; diff --git a/dts/common/nordic/nrf54h20_enga.dtsi b/dts/common/nordic/nrf54h20_enga.dtsi index 3a8a5759268..5a9af57801c 100644 --- a/dts/common/nordic/nrf54h20_enga.dtsi +++ b/dts/common/nordic/nrf54h20_enga.dtsi @@ -223,24 +223,6 @@ #size-cells = <1>; ranges = <0x0 0x5f000000 0x1000000>; - cpusec_bellboard: mailbox@99000 { - reg = <0x99000 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - }; - - cpuapp_bellboard: mailbox@9a000 { - reg = <0x9a000 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - }; - - cpurad_bellboard: mailbox@9b000 { - reg = <0x9b000 0x1000>; - status = "disabled"; - #mbox-cells = <1>; - }; - timer120: timer@8e2000 { compatible = "nordic,nrf-timer"; reg = <0x8e2000 0x1000>; diff --git a/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi b/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi index dcefe95885c..d42a815a4b2 100644 --- a/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi +++ b/dts/riscv/nordic/nrf54h20_enga_cpuppr.dtsi @@ -26,18 +26,6 @@ clic: &cpuppr_clic {}; }; }; -&cpusec_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpuapp_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - -&cpurad_bellboard { - compatible = "nordic,nrf-bellboard-remote"; -}; - &gpiote130 { interrupts = <104 NRF_DEFAULT_IRQ_PRIORITY>; }; From 44efd81cd74e15e33faeb8e4d842636ba2e9ee75 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:36 +0200 Subject: [PATCH 2302/2402] Revert "[nrf fromlist] samples: drivers: mbox: misc cleanups/enhancements" This reverts commit 737da5af682b26ce089f4043b7102f1103e8dbb1. Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/remote/src/main.c | 26 +++++++++++++------------- samples/drivers/mbox/src/main.c | 23 +++++++++++------------ 2 files changed, 24 insertions(+), 25 deletions(-) diff --git a/samples/drivers/mbox/remote/src/main.c b/samples/drivers/mbox/remote/src/main.c index 1ca832a697c..31665951172 100644 --- a/samples/drivers/mbox/remote/src/main.c +++ b/samples/drivers/mbox/remote/src/main.c @@ -4,9 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include +#include #include #include -#include #if !defined(CONFIG_RX_ENABLED) && !defined(CONFIG_TX_ENABLED) #error "At least one of CONFIG_RX_ENABLED or CONFIG_TX_ENABLED must be set" @@ -22,25 +23,24 @@ static void callback(const struct device *dev, uint32_t channel, int main(void) { - int ret; - const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); + const struct device *dev; - printk("Hello from REMOTE\n"); + printk("Hello from NET\n"); + + dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); #ifdef CONFIG_RX_ENABLED struct mbox_channel rx_channel; mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); - ret = mbox_register_callback(&rx_channel, callback, NULL); - if (ret < 0) { - printk("Could not register callback (%d)\n", ret); + if (mbox_register_callback(&rx_channel, callback, NULL)) { + printk("mbox_register_callback() error\n"); return 0; } - ret = mbox_set_enabled(&rx_channel, true); - if (ret < 0) { - printk("Could not enable RX channel %d (%d)\n", rx_channel.id, ret); + if (mbox_set_enabled(&rx_channel, 1)) { + printk("mbox_set_enable() error\n"); return 0; } #endif /* CONFIG_RX_ENABLED */ @@ -51,11 +51,11 @@ int main(void) mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); while (1) { + printk("Ping (on channel %d)\n", tx_channel.id); - ret = mbox_send(&tx_channel, NULL); - if (ret < 0) { - printk("Could not send (%d)\n", ret); + if (mbox_send(&tx_channel, NULL) < 0) { + printk("mbox_send() error\n"); return 0; } diff --git a/samples/drivers/mbox/src/main.c b/samples/drivers/mbox/src/main.c index d4dd21d342f..cea34afb29a 100644 --- a/samples/drivers/mbox/src/main.c +++ b/samples/drivers/mbox/src/main.c @@ -4,9 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include +#include #include #include -#include #ifdef CONFIG_RX_ENABLED static void callback(const struct device *dev, uint32_t channel, @@ -18,25 +19,24 @@ static void callback(const struct device *dev, uint32_t channel, int main(void) { - int ret; - const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); + const struct device *dev; printk("Hello from APP\n"); + dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); + #ifdef CONFIG_RX_ENABLED struct mbox_channel rx_channel; mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); - ret = mbox_register_callback(&rx_channel, callback, NULL); - if (ret < 0) { - printk("Could not register callback (%d)\n", ret); + if (mbox_register_callback(&rx_channel, callback, NULL)) { + printk("mbox_register_callback() error\n"); return 0; } - ret = mbox_set_enabled(&rx_channel, true); - if (ret < 0) { - printk("Could not enable RX channel %d (%d)\n", rx_channel.id, ret); + if (mbox_set_enabled(&rx_channel, 1)) { + printk("mbox_set_enable() error\n"); return 0; } #endif /* CONFIG_RX_ENABLED */ @@ -51,9 +51,8 @@ int main(void) printk("Ping (on channel %d)\n", tx_channel.id); - ret = mbox_send(&tx_channel, NULL); - if (ret < 0) { - printk("Could not send (%d)\n", ret); + if (mbox_send(&tx_channel, NULL) < 0) { + printk("mbox_send() error\n"); return 0; } } From 0f8f21e664fb2b6460173a51868c7adde8aa45d3 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:36 +0200 Subject: [PATCH 2303/2402] Revert "[nrf fromlist] samples: drivers: mbox: allow to enable RX/TX" This reverts commit 7d399d06e46cf7594bfd17c86578b3f591220a2b. Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/Kconfig | 13 ------------- samples/drivers/mbox/remote/Kconfig | 13 ------------- samples/drivers/mbox/remote/src/main.c | 20 +++----------------- samples/drivers/mbox/src/main.c | 15 +++------------ 4 files changed, 6 insertions(+), 55 deletions(-) diff --git a/samples/drivers/mbox/Kconfig b/samples/drivers/mbox/Kconfig index 3af6e740bfc..79dd2d09689 100644 --- a/samples/drivers/mbox/Kconfig +++ b/samples/drivers/mbox/Kconfig @@ -10,28 +10,15 @@ config INCLUDE_REMOTE_DIR Include remote build header files. Can be used if primary image needs to be aware of size or base address of secondary image -config TX_ENABLED - bool "TX enabled" - default y - help - Enable TX - config TX_CHANNEL_ID int "Channel ID for TX" default 1 - depends on TX_ENABLED help Channel ID for TX -config RX_ENABLED - bool "RX enabled" - default y - help - Enable RX config RX_CHANNEL_ID int "Channel ID for RX" - depends on RX_ENABLED default 0 help Channel ID for RX diff --git a/samples/drivers/mbox/remote/Kconfig b/samples/drivers/mbox/remote/Kconfig index 7edb8574359..a8897e4aab0 100644 --- a/samples/drivers/mbox/remote/Kconfig +++ b/samples/drivers/mbox/remote/Kconfig @@ -3,28 +3,15 @@ source "Kconfig.zephyr" -config TX_ENABLED - bool "TX enabled" - default y - help - Enable TX - config TX_CHANNEL_ID int "Channel ID for TX" default 0 - depends on TX_ENABLED help Channel ID for TX -config RX_ENABLED - bool "RX enabled" - default y - help - Enable RX config RX_CHANNEL_ID int "Channel ID for RX" - depends on RX_ENABLED default 1 help Channel ID for RX diff --git a/samples/drivers/mbox/remote/src/main.c b/samples/drivers/mbox/remote/src/main.c index 31665951172..a256ed21daa 100644 --- a/samples/drivers/mbox/remote/src/main.c +++ b/samples/drivers/mbox/remote/src/main.c @@ -9,29 +9,23 @@ #include #include -#if !defined(CONFIG_RX_ENABLED) && !defined(CONFIG_TX_ENABLED) -#error "At least one of CONFIG_RX_ENABLED or CONFIG_TX_ENABLED must be set" -#endif - -#ifdef CONFIG_RX_ENABLED static void callback(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data) { printk("Pong (on channel %d)\n", channel); } -#endif /* CONFIG_RX_ENABLED */ int main(void) { + struct mbox_channel tx_channel; + struct mbox_channel rx_channel; const struct device *dev; printk("Hello from NET\n"); dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); -#ifdef CONFIG_RX_ENABLED - struct mbox_channel rx_channel; - + mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); if (mbox_register_callback(&rx_channel, callback, NULL)) { @@ -43,12 +37,6 @@ int main(void) printk("mbox_set_enable() error\n"); return 0; } -#endif /* CONFIG_RX_ENABLED */ - -#ifdef CONFIG_TX_ENABLED - struct mbox_channel tx_channel; - - mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); while (1) { @@ -61,7 +49,5 @@ int main(void) k_sleep(K_MSEC(3000)); } -#endif /* CONFIG_TX_ENABLED */ - return 0; } diff --git a/samples/drivers/mbox/src/main.c b/samples/drivers/mbox/src/main.c index cea34afb29a..bfe28443f95 100644 --- a/samples/drivers/mbox/src/main.c +++ b/samples/drivers/mbox/src/main.c @@ -9,25 +9,23 @@ #include #include -#ifdef CONFIG_RX_ENABLED static void callback(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data) { printk("Pong (on channel %d)\n", channel); } -#endif int main(void) { + struct mbox_channel tx_channel; + struct mbox_channel rx_channel; const struct device *dev; printk("Hello from APP\n"); dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); -#ifdef CONFIG_RX_ENABLED - struct mbox_channel rx_channel; - + mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); if (mbox_register_callback(&rx_channel, callback, NULL)) { @@ -39,12 +37,6 @@ int main(void) printk("mbox_set_enable() error\n"); return 0; } -#endif /* CONFIG_RX_ENABLED */ - -#ifdef CONFIG_TX_ENABLED - struct mbox_channel tx_channel; - - mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); while (1) { k_sleep(K_MSEC(2000)); @@ -56,6 +48,5 @@ int main(void) return 0; } } -#endif /* CONFIG_TX_ENABLED */ return 0; } From 51ddaa890c217947b920bf49e2b031d114fcb3f0 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:36 +0200 Subject: [PATCH 2304/2402] Revert "[nrf fromlist] samples: drivers: mbox: allow to configure RX/TX channels" This reverts commit 5e63290f335d41ccc4ead98d18a6ebd689d707dd. Signed-off-by: Gerard Marull-Paretas --- samples/drivers/mbox/Kconfig | 13 ------------- samples/drivers/mbox/remote/Kconfig | 17 ----------------- samples/drivers/mbox/remote/src/main.c | 7 +++++-- samples/drivers/mbox/src/main.c | 7 +++++-- 4 files changed, 10 insertions(+), 34 deletions(-) delete mode 100644 samples/drivers/mbox/remote/Kconfig diff --git a/samples/drivers/mbox/Kconfig b/samples/drivers/mbox/Kconfig index 79dd2d09689..3837c49b6e9 100644 --- a/samples/drivers/mbox/Kconfig +++ b/samples/drivers/mbox/Kconfig @@ -9,16 +9,3 @@ config INCLUDE_REMOTE_DIR help Include remote build header files. Can be used if primary image needs to be aware of size or base address of secondary image - -config TX_CHANNEL_ID - int "Channel ID for TX" - default 1 - help - Channel ID for TX - - -config RX_CHANNEL_ID - int "Channel ID for RX" - default 0 - help - Channel ID for RX diff --git a/samples/drivers/mbox/remote/Kconfig b/samples/drivers/mbox/remote/Kconfig deleted file mode 100644 index a8897e4aab0..00000000000 --- a/samples/drivers/mbox/remote/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "Kconfig.zephyr" - -config TX_CHANNEL_ID - int "Channel ID for TX" - default 0 - help - Channel ID for TX - - -config RX_CHANNEL_ID - int "Channel ID for RX" - default 1 - help - Channel ID for RX diff --git a/samples/drivers/mbox/remote/src/main.c b/samples/drivers/mbox/remote/src/main.c index a256ed21daa..89039e3b277 100644 --- a/samples/drivers/mbox/remote/src/main.c +++ b/samples/drivers/mbox/remote/src/main.c @@ -9,6 +9,9 @@ #include #include +#define TX_ID (0) +#define RX_ID (1) + static void callback(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data) { @@ -25,8 +28,8 @@ int main(void) dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); - mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); - mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); + mbox_init_channel(&tx_channel, dev, TX_ID); + mbox_init_channel(&rx_channel, dev, RX_ID); if (mbox_register_callback(&rx_channel, callback, NULL)) { printk("mbox_register_callback() error\n"); diff --git a/samples/drivers/mbox/src/main.c b/samples/drivers/mbox/src/main.c index bfe28443f95..d6c79729b4f 100644 --- a/samples/drivers/mbox/src/main.c +++ b/samples/drivers/mbox/src/main.c @@ -9,6 +9,9 @@ #include #include +#define TX_ID (1) +#define RX_ID (0) + static void callback(const struct device *dev, uint32_t channel, void *user_data, struct mbox_msg *data) { @@ -25,8 +28,8 @@ int main(void) dev = DEVICE_DT_GET(DT_NODELABEL(mbox)); - mbox_init_channel(&tx_channel, dev, CONFIG_TX_CHANNEL_ID); - mbox_init_channel(&rx_channel, dev, CONFIG_RX_CHANNEL_ID); + mbox_init_channel(&tx_channel, dev, TX_ID); + mbox_init_channel(&rx_channel, dev, RX_ID); if (mbox_register_callback(&rx_channel, callback, NULL)) { printk("mbox_register_callback() error\n"); From e74fbce17db01a0713bff517eebb43085016b042 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:36 +0200 Subject: [PATCH 2305/2402] Revert "[nrf fromlist] drivers: misc: nordic_vpr_launcher: initialize earlier" This reverts commit a7007991bf72bcd5051dd4aff8028b271a4af4b8. Signed-off-by: Gerard Marull-Paretas --- drivers/misc/nordic_vpr_launcher/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/nordic_vpr_launcher/Kconfig b/drivers/misc/nordic_vpr_launcher/Kconfig index 6aeabcd251c..57605e505f2 100644 --- a/drivers/misc/nordic_vpr_launcher/Kconfig +++ b/drivers/misc/nordic_vpr_launcher/Kconfig @@ -17,7 +17,7 @@ source "subsys/logging/Kconfig.template.log_config" config NORDIC_VPR_LAUNCHER_INIT_PRIORITY int "Nordic VPR coprocessor launcher init priority" - default 0 + default KERNEL_INIT_PRIORITY_DEVICE help The init priority of the VPR coprocessor launcher. From 1e1fdb95f4ffb8c08bf08337dccd3af3574d2e86 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:37 +0200 Subject: [PATCH 2306/2402] Revert "[nrf fromlist] drivers: modem_cellular: fine tune nRF91's shutdown_time" This reverts commit eab783c7d645bee60606def787caad29d0d01f5f. Signed-off-by: Gerard Marull-Paretas --- drivers/modem/modem_cellular.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 276c9d38f7b..ed4e998fec3 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -2219,7 +2219,7 @@ MODEM_CHAT_SCRIPT_DEFINE(nordic_nrf91_slm_periodic_chat_script, .power_pulse_duration_ms = 100, \ .reset_pulse_duration_ms = 100, \ .startup_time_ms = 2000, \ - .shutdown_time_ms = 10000, \ + .shutdown_time_ms = 3000, \ .init_chat_script = &nordic_nrf91_slm_init_chat_script, \ .dial_chat_script = &nordic_nrf91_slm_dial_chat_script, \ .periodic_chat_script = &nordic_nrf91_slm_periodic_chat_script, \ From df58e1a30229b9e84b0e2ab83c2ae12f469851aa Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:37 +0200 Subject: [PATCH 2307/2402] Revert "[nrf fromlist] drivers: modem_cellular: add nRF91 series (w/ SLM)" This reverts commit a1f3dbbb5fd7e01c00a777076eb1de5c7d46dbf1. Signed-off-by: Gerard Marull-Paretas --- drivers/modem/Kconfig.cellular | 3 +- drivers/modem/modem_cellular.c | 67 ------------------- dts/bindings/modem/nordic,nrf91-slm.yaml | 9 --- .../boards/nrf9160dk_nrf9160_ns.conf | 16 ----- .../boards/nrf9160dk_nrf9160_ns.overlay | 34 ---------- tests/drivers/build_all/modem/uart.dtsi | 6 -- 6 files changed, 1 insertion(+), 134 deletions(-) delete mode 100644 dts/bindings/modem/nordic,nrf91-slm.yaml delete mode 100644 samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf delete mode 100644 samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.overlay diff --git a/drivers/modem/Kconfig.cellular b/drivers/modem/Kconfig.cellular index aacf4449d28..599a8a61138 100644 --- a/drivers/modem/Kconfig.cellular +++ b/drivers/modem/Kconfig.cellular @@ -15,8 +15,7 @@ config MODEM_CELLULAR depends on (DT_HAS_QUECTEL_BG95_ENABLED || DT_HAS_ZEPHYR_GSM_PPP_ENABLED || \ DT_HAS_SIMCOM_SIM7080_ENABLED || DT_HAS_U_BLOX_SARA_R4_ENABLED || \ DT_HAS_U_BLOX_SARA_R5_ENABLED || DT_HAS_SWIR_HL7800_ENABLED || \ - DT_HAS_TELIT_ME910G1_ENABLED || DT_HAS_QUECTEL_EG25_G_ENABLED || \ - DT_HAS_NORDIC_NRF91_SLM_ENABLED) + DT_HAS_TELIT_ME910G1_ENABLED || DT_HAS_QUECTEL_EG25_G_ENABLED) help This driver uses the generic 3gpp AT commands, along with the standard protocols CMUX and PPP, to configure diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index ed4e998fec3..63430d45c1a 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -1933,41 +1933,6 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, modem_cellular_chat_callback_handler, 4); #endif -#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf91_slm) -MODEM_CHAT_SCRIPT_CMDS_DEFINE(nordic_nrf91_slm_init_chat_script_cmds, - MODEM_CHAT_SCRIPT_CMD_RESP_MULT("AT", allow_match), - MODEM_CHAT_SCRIPT_CMD_RESP("AT+CMEE=1", ok_match), - MODEM_CHAT_SCRIPT_CMD_RESP("AT+CEREG=1", ok_match), - MODEM_CHAT_SCRIPT_CMD_RESP("AT+CEREG?", ok_match), - MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGSN", imei_match), - MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), - MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMM", cgmm_match), - MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), - MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMI", cgmi_match), - MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), - MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMR", cgmr_match), - MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), - MODEM_CHAT_SCRIPT_CMD_RESP("AT#XCMUX=1", ok_match)); - -MODEM_CHAT_SCRIPT_DEFINE(nordic_nrf91_slm_init_chat_script, nordic_nrf91_slm_init_chat_script_cmds, - abort_matches, modem_cellular_chat_callback_handler, 10); - -MODEM_CHAT_SCRIPT_CMDS_DEFINE(nordic_nrf91_slm_dial_chat_script_cmds, - MODEM_CHAT_SCRIPT_CMD_RESP("AT+CFUN=4", ok_match), - MODEM_CHAT_SCRIPT_CMD_RESP("AT+CFUN=1", ok_match), - MODEM_CHAT_SCRIPT_CMD_RESP("AT#XCMUX=2", ok_match)); - -MODEM_CHAT_SCRIPT_DEFINE(nordic_nrf91_slm_dial_chat_script, nordic_nrf91_slm_dial_chat_script_cmds, - dial_abort_matches, modem_cellular_chat_callback_handler, 10); - -MODEM_CHAT_SCRIPT_CMDS_DEFINE(nordic_nrf91_slm_periodic_chat_script_cmds, - MODEM_CHAT_SCRIPT_CMD_RESP("AT+CEREG?", ok_match)); - -MODEM_CHAT_SCRIPT_DEFINE(nordic_nrf91_slm_periodic_chat_script, - nordic_nrf91_slm_periodic_chat_script_cmds, abort_matches, - modem_cellular_chat_callback_handler, 4); -#endif - #define MODEM_CELLULAR_INST_NAME(name, inst) \ _CONCAT(_CONCAT(_CONCAT(name, _), DT_DRV_COMPAT), inst) @@ -2204,34 +2169,6 @@ MODEM_CHAT_SCRIPT_DEFINE(nordic_nrf91_slm_periodic_chat_script, &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \ &modem_cellular_api); -#define MODEM_CELLULAR_DEVICE_NORDIC_NRF91_SLM(inst) \ - MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 1500); \ - \ - static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = "\r\n", \ - .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ - }; \ - \ - static struct modem_cellular_config MODEM_CELLULAR_INST_NAME(config, inst) = { \ - .uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \ - .power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}), \ - .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}), \ - .power_pulse_duration_ms = 100, \ - .reset_pulse_duration_ms = 100, \ - .startup_time_ms = 2000, \ - .shutdown_time_ms = 3000, \ - .init_chat_script = &nordic_nrf91_slm_init_chat_script, \ - .dial_chat_script = &nordic_nrf91_slm_dial_chat_script, \ - .periodic_chat_script = &nordic_nrf91_slm_periodic_chat_script, \ - }; \ - \ - PM_DEVICE_DT_INST_DEFINE(inst, modem_cellular_pm_action); \ - \ - DEVICE_DT_INST_DEFINE(inst, modem_cellular_init, PM_DEVICE_DT_INST_GET(inst), \ - &MODEM_CELLULAR_INST_NAME(data, inst), \ - &MODEM_CELLULAR_INST_NAME(config, inst), POST_KERNEL, 99, \ - &modem_cellular_api); - #define DT_DRV_COMPAT quectel_bg95 DT_INST_FOREACH_STATUS_OKAY(MODEM_CELLULAR_DEVICE_QUECTEL_BG95) #undef DT_DRV_COMPAT @@ -2263,7 +2200,3 @@ DT_INST_FOREACH_STATUS_OKAY(MODEM_CELLULAR_DEVICE_SWIR_HL7800) #define DT_DRV_COMPAT telit_me910g1 DT_INST_FOREACH_STATUS_OKAY(MODEM_CELLULAR_DEVICE_TELIT_ME910G1) #undef DT_DRV_COMPAT - -#define DT_DRV_COMPAT nordic_nrf91_slm -DT_INST_FOREACH_STATUS_OKAY(MODEM_CELLULAR_DEVICE_NORDIC_NRF91_SLM) -#undef DT_DRV_COMPAT diff --git a/dts/bindings/modem/nordic,nrf91-slm.yaml b/dts/bindings/modem/nordic,nrf91-slm.yaml deleted file mode 100644 index 3f06696197d..00000000000 --- a/dts/bindings/modem/nordic,nrf91-slm.yaml +++ /dev/null @@ -1,9 +0,0 @@ -description: Nordic nRF91 series running the Serial LTE Modem application - -compatible: "nordic,nrf91-slm" - -include: uart-device.yaml - -properties: - mdm-power-gpios: - type: phandle-array diff --git a/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf b/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf deleted file mode 100644 index 441a5395ca1..00000000000 --- a/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf +++ /dev/null @@ -1,16 +0,0 @@ -CONFIG_UART_ASYNC_API=y - -# Align with the Serial LTE Modem (SLM) application. -CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE=1500 -CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES=1500 - -# Allow large UART TXs to go through @115200. -CONFIG_MODEM_BACKEND_UART_ASYNC_TRANSMIT_TIMEOUT_MS=200 - -# Prevent sockets getting offloaded to the modem. -CONFIG_NET_SOCKETS_OFFLOAD=n - -# Print logs and printk() output on uart0. -CONFIG_LOG=y -CONFIG_LOG_BACKEND_UART=y -CONFIG_MODEM_LOG_LEVEL_DBG=y diff --git a/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.overlay b/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.overlay deleted file mode 100644 index 44ce80601a1..00000000000 --- a/samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.overlay +++ /dev/null @@ -1,34 +0,0 @@ -/ { - aliases { - modem = &modem; - }; -}; - -&uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - hw-flow-control; - status = "okay"; - - pinctrl-0 = <&uart1_default_alt>; - - modem: modem { - compatible = "nordic,nrf91-slm"; - status = "okay"; - mdm-power-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - uart1_default_alt: uart1_default_alt { - group1 { - psels = ; - bias-pull-up; - }; - group2 { - psels = , - , - ; - }; - }; -}; diff --git a/tests/drivers/build_all/modem/uart.dtsi b/tests/drivers/build_all/modem/uart.dtsi index 08da2c325d3..3d649a2ff60 100644 --- a/tests/drivers/build_all/modem/uart.dtsi +++ b/tests/drivers/build_all/modem/uart.dtsi @@ -70,9 +70,3 @@ test_telit_me910g1: telit_me910g1 { test_esp_at: esp_at { compatible = "espressif,esp-at"; }; - -test_nordic_nrf91_slm: nordic_nrf91_slm { - compatible = "nordic,nrf91-slm"; - - mdm-power-gpios = <&test_gpio 0 0>; -}; From 48589d9d652de64ea7c2979789bf267999c85c6b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:37 +0200 Subject: [PATCH 2308/2402] Revert "[nrf fromlist] drivers: modem_cellular: make the buffer sizes configurable" This reverts commit e17559225295a1803af8a7c265c48b75128aae3d. Signed-off-by: Gerard Marull-Paretas --- drivers/modem/Kconfig.cellular | 14 -------------- drivers/modem/modem_cellular.c | 15 +++++++-------- 2 files changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/modem/Kconfig.cellular b/drivers/modem/Kconfig.cellular index 599a8a61138..0460cda8d96 100644 --- a/drivers/modem/Kconfig.cellular +++ b/drivers/modem/Kconfig.cellular @@ -36,18 +36,4 @@ config MODEM_CELLULAR_PERIODIC_SCRIPT_MS int "Periodic script interval in milliseconds" default 2000 -config MODEM_CELLULAR_UART_BUFFER_SIZES - int "The UART receive and transmit buffer sizes in bytes." - default 512 - -config MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE - int "The maximum CMUX frame size in bytes." - default 128 - help - This value affects the size of buffers used to receive and transmit CMUX frames. - -config MODEM_CELLULAR_CHAT_BUFFER_SIZES - int "The size of the buffers used for the chat scripts in bytes." - default 128 - endif diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 63430d45c1a..35b05602a74 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -79,24 +79,23 @@ struct modem_cellular_data { /* UART backend */ struct modem_pipe *uart_pipe; struct modem_backend_uart uart_backend; - uint8_t uart_backend_receive_buf[CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES]; - uint8_t uart_backend_transmit_buf[CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES]; + uint8_t uart_backend_receive_buf[512]; + uint8_t uart_backend_transmit_buf[512]; /* CMUX */ struct modem_cmux cmux; - uint8_t cmux_receive_buf[CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE]; - uint8_t cmux_transmit_buf[2 * CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE]; + uint8_t cmux_receive_buf[128]; + uint8_t cmux_transmit_buf[256]; struct modem_cmux_dlci dlci1; struct modem_cmux_dlci dlci2; struct modem_pipe *dlci1_pipe; struct modem_pipe *dlci2_pipe; - uint8_t dlci1_receive_buf[CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE]; - /* DLCI 2 is only used for chat scripts. */ - uint8_t dlci2_receive_buf[CONFIG_MODEM_CELLULAR_CHAT_BUFFER_SIZES]; + uint8_t dlci1_receive_buf[128]; + uint8_t dlci2_receive_buf[256]; /* Modem chat */ struct modem_chat chat; - uint8_t chat_receive_buf[CONFIG_MODEM_CELLULAR_CHAT_BUFFER_SIZES]; + uint8_t chat_receive_buf[128]; uint8_t *chat_delimiter; uint8_t *chat_filter; uint8_t *chat_argv[32]; From a0819fa974ce932b3175dee011e43a8718aa53a8 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:37 +0200 Subject: [PATCH 2309/2402] Revert "[nrf fromlist] drivers: modem_cellular: allow variable length chat delimiter and filter" This reverts commit 45209857cb06da35772e88e66e6ca38cf7a05cbe. Signed-off-by: Gerard Marull-Paretas --- drivers/modem/modem_cellular.c | 46 +++++++++++++++++----------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 35b05602a74..f5e099cd08c 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -96,8 +96,8 @@ struct modem_cellular_data { /* Modem chat */ struct modem_chat chat; uint8_t chat_receive_buf[128]; - uint8_t *chat_delimiter; - uint8_t *chat_filter; + uint8_t chat_delimiter[1]; + uint8_t chat_filter[1]; uint8_t *chat_argv[32]; /* Status */ @@ -424,9 +424,9 @@ MODEM_CHAT_MATCH_DEFINE(imei_match, "", "", modem_cellular_chat_on_imei); MODEM_CHAT_MATCH_DEFINE(cgmm_match, "", "", modem_cellular_chat_on_cgmm); MODEM_CHAT_MATCH_DEFINE(csq_match, "+CSQ: ", ",", modem_cellular_chat_on_csq); MODEM_CHAT_MATCH_DEFINE(cesq_match, "+CESQ: ", ",", modem_cellular_chat_on_cesq); -MODEM_CHAT_MATCH_DEFINE(cimi_match __maybe_unused, "", "", modem_cellular_chat_on_imsi); -MODEM_CHAT_MATCH_DEFINE(cgmi_match __maybe_unused, "", "", modem_cellular_chat_on_cgmi); -MODEM_CHAT_MATCH_DEFINE(cgmr_match __maybe_unused, "", "", modem_cellular_chat_on_cgmr); +MODEM_CHAT_MATCH_DEFINE(cimi_match, "", "", modem_cellular_chat_on_imsi); +MODEM_CHAT_MATCH_DEFINE(cgmi_match, "", "", modem_cellular_chat_on_cgmi); +MODEM_CHAT_MATCH_DEFINE(cgmr_match, "", "", modem_cellular_chat_on_cgmr); MODEM_CHAT_MATCHES_DEFINE(unsol_matches, MODEM_CHAT_MATCH("+CREG: ", ",", modem_cellular_chat_on_cxreg), @@ -1513,9 +1513,9 @@ static int modem_cellular_init(const struct device *dev) .receive_buf = data->chat_receive_buf, .receive_buf_size = ARRAY_SIZE(data->chat_receive_buf), .delimiter = data->chat_delimiter, - .delimiter_size = strlen(data->chat_delimiter), + .delimiter_size = ARRAY_SIZE(data->chat_delimiter), .filter = data->chat_filter, - .filter_size = strlen(data->chat_filter), + .filter_size = ARRAY_SIZE(data->chat_filter), .argv = data->chat_argv, .argv_size = ARRAY_SIZE(data->chat_argv), .unsol_matches = unsol_matches, @@ -1939,8 +1939,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = "\r", \ - .chat_filter = "\n", \ + .chat_delimiter = {'\r'}, \ + .chat_filter = {'\n'}, \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -1968,8 +1968,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = "\r", \ - .chat_filter = "\n", \ + .chat_delimiter = {'\r'}, \ + .chat_filter = {'\n'}, \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -1997,8 +1997,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = "\r", \ - .chat_filter = "\n", \ + .chat_delimiter = {'\r'}, \ + .chat_filter = {'\n'}, \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -2026,8 +2026,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = "\r", \ - .chat_filter = "\n", \ + .chat_delimiter = {'\r'}, \ + .chat_filter = {'\n'}, \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -2055,8 +2055,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = "\r", \ - .chat_filter = "\n", \ + .chat_delimiter = {'\r'}, \ + .chat_filter = {'\n'}, \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -2084,8 +2084,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = "\r", \ - .chat_filter = "\n", \ + .chat_delimiter = {'\r'}, \ + .chat_filter = {'\n'}, \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -2114,8 +2114,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = "\r", \ - .chat_filter = "\n", \ + .chat_delimiter = {'\r'}, \ + .chat_filter = {'\n'}, \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ @@ -2143,8 +2143,8 @@ MODEM_CHAT_SCRIPT_DEFINE(telit_me910g1_periodic_chat_script, MODEM_PPP_DEFINE(MODEM_CELLULAR_INST_NAME(ppp, inst), NULL, 98, 1500, 64); \ \ static struct modem_cellular_data MODEM_CELLULAR_INST_NAME(data, inst) = { \ - .chat_delimiter = "\r", \ - .chat_filter = "\n", \ + .chat_delimiter = {'\r'}, \ + .chat_filter = {'\n'}, \ .ppp = &MODEM_CELLULAR_INST_NAME(ppp, inst), \ }; \ \ From 423638f70c975e8f027016bc76fcc2978cd8cf99 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:38 +0200 Subject: [PATCH 2310/2402] Revert "[nrf fromtree] drivers: ieee802154_nrf5: Use Radio IRQ number from DT" This reverts commit 869cf57a5f72df5e2974d8c87e2b7d4079bdb68e. Signed-off-by: Gerard Marull-Paretas --- drivers/ieee802154/ieee802154_nrf5.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/ieee802154/ieee802154_nrf5.c b/drivers/ieee802154/ieee802154_nrf5.c index 67b5431e9cc..ecc758455d7 100644 --- a/drivers/ieee802154/ieee802154_nrf5.c +++ b/drivers/ieee802154/ieee802154_nrf5.c @@ -738,8 +738,9 @@ static void nrf5_irq_config(const struct device *dev) ARG_UNUSED(dev); #if !IS_ENABLED(CONFIG_IEEE802154_NRF5_EXT_IRQ_MGMT) - IRQ_CONNECT(DT_IRQN(DT_NODELABEL(radio)), NRF_802154_IRQ_PRIORITY, nrf5_radio_irq, NULL, 0); - irq_enable(DT_IRQN(DT_NODELABEL(radio))); + IRQ_CONNECT(RADIO_IRQn, NRF_802154_IRQ_PRIORITY, + nrf5_radio_irq, NULL, 0); + irq_enable(RADIO_IRQn); #endif } From e277f4fac82662ed3f9f44cd5f938e069065364d Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:38 +0200 Subject: [PATCH 2311/2402] Revert "[nrf fromtree] modules: hal_nordic: nrfx_glue add missing code for nrf_802154" This reverts commit e9136301ebee6633b91ac35d21662b36c027e2eb. Signed-off-by: Gerard Marull-Paretas --- modules/hal_nordic/nrfx/nrfx_glue.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/modules/hal_nordic/nrfx/nrfx_glue.h b/modules/hal_nordic/nrfx/nrfx_glue.h index 748c5eafd47..0edda440112 100644 --- a/modules/hal_nordic/nrfx/nrfx_glue.h +++ b/modules/hal_nordic/nrfx/nrfx_glue.h @@ -364,10 +364,6 @@ void nrfx_busy_wait(uint32_t usec_to_wait); #include <../src/nrf_802154_peripherals_nrf53.h> #define NRFX_PPI_CHANNELS_USED_BY_802154_DRV NRF_802154_DPPI_CHANNELS_USED_MASK #define NRFX_PPI_GROUPS_USED_BY_802154_DRV NRF_802154_DPPI_GROUPS_USED_MASK -#elif defined(NRF54L_SERIES) -#include <../src/nrf_802154_peripherals_nrf54l.h> -#define NRFX_PPI_CHANNELS_USED_BY_802154_DRV NRF_802154_DPPI_CHANNELS_USED_MASK -#define NRFX_PPI_GROUPS_USED_BY_802154_DRV NRF_802154_DPPI_GROUPS_USED_MASK #else #error Unsupported chip family #endif From 4e088be990755ad3e4fe7d13c42bab9bca8be4cb Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:38 +0200 Subject: [PATCH 2312/2402] Revert "[nrf fromtree] Bluetooth: Shell: Add support for EAD" This reverts commit aa2eeb1a34df2d9abcdb46c9b85aafbf8fbc768f. Signed-off-by: Gerard Marull-Paretas --- .../bluetooth/bluetooth-shell.rst | 84 ----- subsys/bluetooth/shell/bt.c | 340 ------------------ tests/bluetooth/shell/prj.conf | 2 - 3 files changed, 426 deletions(-) diff --git a/doc/connectivity/bluetooth/bluetooth-shell.rst b/doc/connectivity/bluetooth/bluetooth-shell.rst index 2b38f4c7b6f..f639cb0b030 100644 --- a/doc/connectivity/bluetooth/bluetooth-shell.rst +++ b/doc/connectivity/bluetooth/bluetooth-shell.rst @@ -228,90 +228,6 @@ Let's now have a look at some extended advertising features. To enable extended This will create an extended advertiser, that is connectable and non-scannable. -Encrypted Advertising Data -========================== - -Zephyr has support for the Encrypted Advertising Data feature. The :code:`bt encrypted-ad` -sub-commands allow managing the advertising data of a given advertiser. - -To encrypt the advertising data, key materials need to be provided, that can be done with :code:`bt -encrypted-ad set-keys `. The session key is 16 bytes long and the -initialisation vector is 8 bytes long. - -You can add advertising data by using :code:`bt encrypted-ad add-ad` and :code:`bt encrypted-ad -add-ead`. The former will take add one advertising data structure (as defined in the Core -Specification), when the later will read the given data, encrypt them and then add the generated -encrypted advertising data structure. It's possible to mix encrypted and non-encrypted data, when -done adding advertising data, :code:`bt encrypted-ad commit-ad` can be used to apply the change to -the data to the selected advertiser. After that the advertiser can be started as described -previously. It's possible to clear the advertising data by using :code:`bt encrypted-ad clear-ad`. - -On the Central side, it's possible to decrypt the received encrypted advertising data by setting the -correct keys material as described earlier and then enabling the decrypting of the data with -:code:`bt encrypted-ad decrypt-scan on`. - -.. note:: - - To see the advertising data in the scan report :code:`bt scan-verbose-output` need to be - enabled. - -.. note:: - - It's possible to increase the length of the advertising data by increasing the value of - :kconfig:option:`CONFIG_BT_CTLR_ADV_DATA_LEN_MAX` and - :kconfig:option:`CONFIG_BT_CTLR_SCAN_DATA_LEN_MAX`. - -Here is a simple example demonstrating the usage of EAD: - -.. tabs:: - - .. group-tab:: Peripheral - - .. code-block:: console - - uart:~$ bt init - ... - uart:~$ bt adv-create conn-nscan ext-adv - Created adv id: 0, adv: 0x81769a0 - uart:~$ bt encrypted-ad set-keys 9ba22d3824efc70feb800c80294cba38 2e83f3d4d47695b6 - session key set to: - 00000000: 9b a2 2d 38 24 ef c7 0f eb 80 0c 80 29 4c ba 38 |..-8$... ....)L.8| - initialisation vector set to: - 00000000: 2e 83 f3 d4 d4 76 95 b6 |.....v.. | - uart:~$ bt encrypted-ad add-ad 06097368656C6C - uart:~$ bt encrypted-ad add-ead 03ffdead03ffbeef - uart:~$ bt encrypted-ad commit-ad - Advertising data for Advertiser[0] 0x81769a0 updated. - uart:~$ bt adv-start - Advertiser[0] 0x81769a0 set started - - .. group-tab:: Central - - .. code-block:: console - - uart:~$ bt init - ... - uart:~$ bt scan-verbose-output on - uart:~$ bt encrypted-ad set-keys 9ba22d3824efc70feb800c80294cba38 2e83f3d4d47695b6 - session key set to: - 00000000: 9b a2 2d 38 24 ef c7 0f eb 80 0c 80 29 4c ba 38 |..-8$... ....)L.8| - initialisation vector set to: - 00000000: 2e 83 f3 d4 d4 76 95 b6 |.....v.. | - uart:~$ bt encrypted-ad decrypt-scan on - Received encrypted advertising data will now be decrypted using provided key materials. - uart:~$ bt scan on - Bluetooth active scan enabled - [DEVICE]: 68:49:30:68:49:30 (random), AD evt type 5, RSSI -59 shell C:1 S:0 D:0 SR:0 E:1 Prim: LE 1M, Secn: LE 2M, Interval: 0x0000 (0 us), SID: 0x0 - [SCAN DATA START - EXT_ADV] - Type 0x09: shell - Type 0x31: Encrypted Advertising Data: 0xe2, 0x17, 0xed, 0x04, 0xe7, 0x02, 0x1d, 0xc9, 0x40, 0x07, uart:~0x18, 0x90, 0x6c, 0x4b, 0xfe, 0x34, 0xad - [START DECRYPTED DATA] - Type 0xff: 0xde, 0xad - Type 0xff: 0xbe, 0xef - [END DECRYPTED DATA] - [SCAN DATA END] - ... - Filter Accept List ****************** diff --git a/subsys/bluetooth/shell/bt.c b/subsys/bluetooth/shell/bt.c index e8952e47526..bbe794969d7 100644 --- a/subsys/bluetooth/shell/bt.c +++ b/subsys/bluetooth/shell/bt.c @@ -32,7 +32,6 @@ #include #include #include -#include #include @@ -217,30 +216,6 @@ static struct bt_scan_filter { static const char scan_response_label[] = "[DEVICE]: "; static bool scan_verbose_output; -#if defined(CONFIG_BT_EAD) -static uint8_t bt_shell_ead_session_key[BT_EAD_KEY_SIZE] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, - 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, - 0xCC, 0xCD, 0xCE, 0xCF}; -static uint8_t bt_shell_ead_iv[BT_EAD_IV_SIZE] = {0xFB, 0x56, 0xE1, 0xDA, 0xDC, 0x7E, 0xAD, 0xF5}; - -/* this is the number of ad struct allowed */ -#define BT_SHELL_EAD_MAX_AD 10 -static size_t bt_shell_ead_ad_len; - -#if defined(CONFIG_BT_CTLR_ADV_DATA_LEN_MAX) -/* this is the maximum total size of the ad data */ -#define BT_SHELL_EAD_DATA_MAX_SIZE CONFIG_BT_CTLR_ADV_DATA_LEN_MAX -#else -#define BT_SHELL_EAD_DATA_MAX_SIZE 31 -#endif -static size_t bt_shell_ead_data_size; -static uint8_t bt_shell_ead_data[BT_SHELL_EAD_DATA_MAX_SIZE] = {0}; - -int ead_update_ad(void); -#endif - -static bool bt_shell_ead_decrypt_scan; - /** * @brief Compares two strings without case sensitivy * @@ -408,36 +383,6 @@ static bool data_verbose_cb(struct bt_data *data, void *user_data) case BT_DATA_CSIS_RSI: print_data_set(3, data->data, data->data_len); break; - case BT_DATA_ENCRYPTED_AD_DATA: - shell_fprintf(ctx_shell, SHELL_INFO, "Encrypted Advertising Data: "); - print_data_set(1, data->data, data->data_len); - - if (bt_shell_ead_decrypt_scan) { -#if defined(CONFIG_BT_EAD) - shell_fprintf(ctx_shell, SHELL_INFO, "\n%*s[START DECRYPTED DATA]\n", - strlen(scan_response_label), ""); - - int ead_err; - struct net_buf_simple decrypted_buf; - size_t decrypted_data_size = BT_EAD_DECRYPTED_PAYLOAD_SIZE(data->data_len); - uint8_t decrypted_data[decrypted_data_size]; - - ead_err = bt_ead_decrypt(bt_shell_ead_session_key, bt_shell_ead_iv, - data->data, data->data_len, decrypted_data); - if (ead_err) { - shell_error(ctx_shell, "Error during decryption (err %d)", ead_err); - } - - net_buf_simple_init_with_data(&decrypted_buf, &decrypted_data[0], - decrypted_data_size); - - bt_data_parse(&decrypted_buf, &data_verbose_cb, user_data); - - shell_fprintf(ctx_shell, SHELL_INFO, "%*s[END DECRYPTED DATA]", - strlen(scan_response_label), ""); -#endif - } - break; default: print_data_set(1, data->data, data->data_len); } @@ -636,13 +581,6 @@ static bool adv_rpa_expired(struct bt_le_ext_adv *adv) adv_index, adv, keep_rpa ? "not expired" : "expired"); -#if defined(CONFIG_BT_EAD) - /* EAD must be updated each time the RPA is updated */ - if (!keep_rpa) { - ead_update_ad(); - } -#endif - return keep_rpa; } #endif /* defined(CONFIG_BT_PRIVACY) */ @@ -4189,267 +4127,6 @@ static int cmd_auth_oob_tk(const struct shell *sh, size_t argc, char *argv[]) #endif /* !defined(CONFIG_BT_SMP_SC_PAIR_ONLY) */ #endif /* CONFIG_BT_SMP) || CONFIG_BT_BREDR */ -#if defined(CONFIG_BT_EAD) -static int cmd_encrypted_ad_set_keys(const struct shell *sh, size_t argc, char *argv[]) -{ - size_t len; - - const char *session_key = argv[1]; - const char *iv = argv[2]; - - len = hex2bin(session_key, strlen(session_key), bt_shell_ead_session_key, BT_EAD_KEY_SIZE); - if (len != BT_EAD_KEY_SIZE) { - shell_error(sh, "Failed to set session key"); - return -ENOEXEC; - } - - len = hex2bin(iv, strlen(iv), bt_shell_ead_iv, BT_EAD_IV_SIZE); - if (len != BT_EAD_IV_SIZE) { - shell_error(sh, "Failed to set initialisation vector"); - return -ENOEXEC; - } - - shell_info(sh, "session key set to:"); - shell_hexdump(sh, bt_shell_ead_session_key, BT_EAD_KEY_SIZE); - shell_info(sh, "initialisation vector set to:"); - shell_hexdump(sh, bt_shell_ead_iv, BT_EAD_IV_SIZE); - - return 0; -} - -int encrypted_ad_store_ad(const struct shell *sh, uint8_t type, const uint8_t *data, - uint8_t data_len) -{ - /* data_len is the size of the data, add two bytes for the size of the type - * and the length that will be stored with the data - */ - uint8_t new_data_size = data_len + 2; - - if (bt_shell_ead_data_size + new_data_size > BT_SHELL_EAD_DATA_MAX_SIZE) { - shell_error(sh, "Failed to add data (trying to add %d but %d already used on %d)", - new_data_size, bt_shell_ead_data_size, BT_SHELL_EAD_DATA_MAX_SIZE); - return -ENOEXEC; - } - - /* the length is the size of the data + the size of the type */ - bt_shell_ead_data[bt_shell_ead_data_size] = data_len + 1; - bt_shell_ead_data[bt_shell_ead_data_size + 1] = type; - memcpy(&bt_shell_ead_data[bt_shell_ead_data_size + 2], data, data_len); - - bt_shell_ead_data_size += new_data_size; - bt_shell_ead_ad_len += 1; - - return 0; -} - -bool is_payload_valid_ad(uint8_t *payload, size_t payload_size) -{ - size_t idx = 0; - bool is_valid = true; - - uint8_t ad_len; - - while (idx < payload_size) { - ad_len = payload[idx]; - - if (payload_size <= ad_len) { - is_valid = false; - break; - } - - idx += ad_len + 1; - } - - if (idx != payload_size) { - is_valid = false; - } - - return is_valid; -} - -static int cmd_encrypted_ad_add_ead(const struct shell *sh, size_t argc, char *argv[]) -{ - size_t len; - - char *hex_payload = argv[1]; - size_t hex_payload_size = strlen(hex_payload); - - uint8_t payload[BT_SHELL_EAD_DATA_MAX_SIZE] = {0}; - uint8_t payload_size = hex_payload_size / 2 + hex_payload_size % 2; - - uint8_t ead_size = BT_EAD_ENCRYPTED_PAYLOAD_SIZE(payload_size); - - if (ead_size > BT_SHELL_EAD_DATA_MAX_SIZE) { - shell_error(sh, - "Failed to add data. Maximum AD size is %d, passed data size after " - "encryption is %d", - BT_SHELL_EAD_DATA_MAX_SIZE, ead_size); - return -ENOEXEC; - } - - len = hex2bin(hex_payload, hex_payload_size, payload, BT_SHELL_EAD_DATA_MAX_SIZE); - if (len != payload_size) { - shell_error(sh, "Failed to add data"); - return -ENOEXEC; - } - - /* check that the given advertising data structures are valid before encrypting them */ - if (!is_payload_valid_ad(payload, payload_size)) { - shell_error(sh, "Failed to add data. Advertising structure are malformed."); - return -ENOEXEC; - } - - /* store not-yet encrypted AD but claim the expected size of encrypted AD */ - return encrypted_ad_store_ad(sh, BT_DATA_ENCRYPTED_AD_DATA, payload, ead_size); -} - -static int cmd_encrypted_ad_add_ad(const struct shell *sh, size_t argc, char *argv[]) -{ - size_t len; - uint8_t ad_len; - uint8_t ad_type; - - char *hex_payload = argv[1]; - size_t hex_payload_size = strlen(hex_payload); - - uint8_t payload[BT_SHELL_EAD_DATA_MAX_SIZE] = {0}; - uint8_t payload_size = hex_payload_size / 2 + hex_payload_size % 2; - - len = hex2bin(hex_payload, hex_payload_size, payload, BT_SHELL_EAD_DATA_MAX_SIZE); - if (len != payload_size) { - shell_error(sh, "Failed to add data"); - return -ENOEXEC; - } - - /* the length received is the length of ad data + the length of the data - * type but `bt_data` struct `data_len` field is only the size of the - * data - */ - ad_len = payload[0] - 1; - ad_type = payload[1]; - - /* if the ad data is malformed or there is more than 1 ad data passed we - * fail - */ - if (len != ad_len + 2) { - shell_error(sh, - "Failed to add data. Data need to be formated as specified in the " - "Core Spec. Only one non-encrypted AD payload can be added at a time."); - return -ENOEXEC; - } - - return encrypted_ad_store_ad(sh, ad_type, payload, payload_size); -} - -static int cmd_encrypted_ad_clear_ad(const struct shell *sh, size_t argc, char *argv[]) -{ - memset(bt_shell_ead_data, 0, BT_SHELL_EAD_DATA_MAX_SIZE); - - bt_shell_ead_ad_len = 0; - bt_shell_ead_data_size = 0; - - shell_info(sh, "Advertising data has been cleared."); - - return 0; -} - -int ead_encrypt_ad(const uint8_t *payload, uint8_t payload_size, uint8_t *encrypted_payload) -{ - int err; - - err = bt_ead_encrypt(bt_shell_ead_session_key, bt_shell_ead_iv, payload, payload_size, - encrypted_payload); - if (err != 0) { - shell_error(ctx_shell, "Failed to encrypt AD."); - return -1; - } - - return 0; -} - -int ead_update_ad(void) -{ - int err; - size_t idx = 0; - struct bt_le_ext_adv *adv = adv_sets[selected_adv]; - - struct bt_data *ad; - size_t ad_structs_idx = 0; - struct bt_data ad_structs[BT_SHELL_EAD_MAX_AD] = {0}; - - size_t encrypted_data_buf_len = 0; - uint8_t encrypted_data_buf[BT_SHELL_EAD_DATA_MAX_SIZE] = {0}; - - while (idx < bt_shell_ead_data_size && ad_structs_idx < BT_SHELL_EAD_MAX_AD) { - ad = &ad_structs[ad_structs_idx]; - - /* the data_len from bt_data struct doesn't include the size of the type */ - ad->data_len = bt_shell_ead_data[idx] - 1; - - if (ad->data_len < 0) { - /* if the len is less than 0 that mean there is not even a type field */ - shell_error(ctx_shell, "Failed to update AD due to malformed AD."); - return -ENOEXEC; - } - - ad->type = bt_shell_ead_data[idx + 1]; - - if (ad->data_len > 0) { - if (ad->type == BT_DATA_ENCRYPTED_AD_DATA) { - /* for EAD the size used to store the non-encrypted data - * is the size of those data when encrypted - */ - ead_encrypt_ad(&bt_shell_ead_data[idx + 2], - BT_EAD_DECRYPTED_PAYLOAD_SIZE(ad->data_len), - &encrypted_data_buf[encrypted_data_buf_len]); - - ad->data = &encrypted_data_buf[encrypted_data_buf_len]; - encrypted_data_buf_len += ad->data_len; - } else { - ad->data = &bt_shell_ead_data[idx + 2]; - } - } - - ad_structs_idx += 1; - idx += ad->data_len + 2; - } - - err = bt_le_ext_adv_set_data(adv, ad_structs, bt_shell_ead_ad_len, NULL, 0); - if (err != 0) { - shell_error(ctx_shell, "Failed to set advertising data (err %d)", err); - return -ENOEXEC; - } - - shell_info(ctx_shell, "Advertising data for Advertiser[%d] %p updated.", selected_adv, adv); - - return 0; -} - -static int cmd_encrypted_ad_commit_ad(const struct shell *sh, size_t argc, char *argv[]) -{ - return ead_update_ad(); -} - -static int cmd_encrypted_ad_decrypt_scan(const struct shell *sh, size_t argc, char *argv[]) -{ - const char *action = argv[1]; - - if (strcmp(action, "on") == 0) { - bt_shell_ead_decrypt_scan = true; - shell_info(sh, "Received encrypted advertising data will now be decrypted using " - "provided key materials."); - } else if (strcmp(action, "off") == 0) { - bt_shell_ead_decrypt_scan = false; - shell_info(sh, "Received encrypted advertising data will now longer be decrypted."); - } else { - shell_error(sh, "Invalid option."); - return -ENOEXEC; - } - - return 0; -} -#endif - static int cmd_default_handler(const struct shell *sh, size_t argc, char **argv) { if (argc == 1) { @@ -4497,19 +4174,6 @@ SHELL_STATIC_SUBCMD_SET_CREATE(bt_scan_filter_clear_cmds, ); #endif /* CONFIG_BT_OBSERVER */ -#if defined(CONFIG_BT_EAD) -SHELL_STATIC_SUBCMD_SET_CREATE( - bt_encrypted_ad_cmds, - SHELL_CMD_ARG(set-keys, NULL, " ", cmd_encrypted_ad_set_keys, 3, - 0), - SHELL_CMD_ARG(add-ead, NULL, "", cmd_encrypted_ad_add_ead, 2, 0), - SHELL_CMD_ARG(add-ad, NULL, "", cmd_encrypted_ad_add_ad, 2, 0), - SHELL_CMD(clear-ad, NULL, HELP_NONE, cmd_encrypted_ad_clear_ad), - SHELL_CMD(commit-ad, NULL, HELP_NONE, cmd_encrypted_ad_commit_ad), - SHELL_CMD_ARG(decrypt-scan, NULL, HELP_ONOFF, cmd_encrypted_ad_decrypt_scan, 2, 0), - SHELL_SUBCMD_SET_END); -#endif - SHELL_STATIC_SUBCMD_SET_CREATE(bt_cmds, SHELL_CMD_ARG(init, NULL, "[no-settings-load], [sync]", cmd_init, 1, 2), @@ -4598,10 +4262,6 @@ SHELL_STATIC_SUBCMD_SET_CREATE(bt_cmds, cmd_per_adv_sync_delete, 1, 1), SHELL_CMD_ARG(per-adv-sync-select, NULL, "[adv]", cmd_per_adv_sync_select, 1, 1), #endif /* defined(CONFIG_BT_PER_ADV_SYNC) */ -#if defined(CONFIG_BT_EAD) - SHELL_CMD(encrypted-ad, &bt_encrypted_ad_cmds, "Manage advertiser with encrypted data", - cmd_default_handler), -#endif /* CONFIG_BT_EAD */ #if defined(CONFIG_BT_CONN) #if defined(CONFIG_BT_PER_ADV_SYNC_TRANSFER_RECEIVER) SHELL_CMD_ARG(past-subscribe, NULL, "[conn] [skip ] " diff --git a/tests/bluetooth/shell/prj.conf b/tests/bluetooth/shell/prj.conf index 185167de1d1..168ccf62a7f 100644 --- a/tests/bluetooth/shell/prj.conf +++ b/tests/bluetooth/shell/prj.conf @@ -46,8 +46,6 @@ CONFIG_BT_PER_ADV_SYNC=y CONFIG_BT_USER_DATA_LEN_UPDATE=y CONFIG_BT_AUTO_DATA_LEN_UPDATE=y -CONFIG_BT_EAD=y - CONFIG_BT_USER_PHY_UPDATE=y CONFIG_BT_AUTO_PHY_UPDATE=y From ffbc70cdd6331edae8607e3509d44e08eeb448cb Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:38 +0200 Subject: [PATCH 2313/2402] Revert "[nrf fromtree] Bluetooth: add missing initilization of sync_info member" This reverts commit daefd697e55896e075fd75c5e8c8e79c439b87b5. Signed-off-by: Gerard Marull-Paretas --- subsys/bluetooth/host/scan.c | 1 - 1 file changed, 1 deletion(-) diff --git a/subsys/bluetooth/host/scan.c b/subsys/bluetooth/host/scan.c index ceb4fd2428e..0b61305e2c3 100644 --- a/subsys/bluetooth/host/scan.c +++ b/subsys/bluetooth/host/scan.c @@ -1246,7 +1246,6 @@ static void bt_hci_le_past_received_common(struct net_buf *buf) sync_info.addr = &per_adv_sync->addr; sync_info.sid = per_adv_sync->sid; sync_info.service_data = sys_le16_to_cpu(evt->service_data); - sync_info.recv_enabled = true; #if defined(CONFIG_BT_PER_ADV_SYNC_RSP) sync_info.num_subevents = per_adv_sync->num_subevents; From 988c412d1c90ff3d47f1b5711186f36f3aeafd81 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:38 +0200 Subject: [PATCH 2314/2402] Revert "[nrf fromtree] modules: crypto: update tinycrypt revision" This reverts commit efbf382d11bde519e7b0fb8f15ee87080271be55. Signed-off-by: Gerard Marull-Paretas --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 3da134e76ce..4d04f7fecaf 100644 --- a/west.yml +++ b/west.yml @@ -317,7 +317,7 @@ manifest: groups: - debug - name: tinycrypt - revision: 1012a3ebee18c15ede5efc8332ee2fc37817670f + revision: 3e9a49d2672ec01435ffbf0d788db6d95ef28de0 path: modules/crypto/tinycrypt groups: - crypto From ec399a0bf1798ceec9fd5d70f9f68825b2e34b82 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:39 +0200 Subject: [PATCH 2315/2402] Revert "[nrf noup] boards: arm: nrf9131ek: enable tfm" This reverts commit 9377fa01e755a19c0aad584c55d5665e327a2db5. Signed-off-by: Gerard Marull-Paretas --- boards/arm/nrf9131ek_nrf9131/Kconfig.defconfig | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/boards/arm/nrf9131ek_nrf9131/Kconfig.defconfig b/boards/arm/nrf9131ek_nrf9131/Kconfig.defconfig index 378a58fb6e3..0ece4f9a2ac 100644 --- a/boards/arm/nrf9131ek_nrf9131/Kconfig.defconfig +++ b/boards/arm/nrf9131ek_nrf9131/Kconfig.defconfig @@ -8,22 +8,6 @@ if BOARD_NRF9131EK_NRF9131 || BOARD_NRF9131EK_NRF9131_NS config BOARD default "nrf9131ek_nrf9131" - -# By default, if we build for a Non-Secure version of the board, -# enable building with TF-M as the Secure Execution Environment. -config BUILD_WITH_TFM - default y if BOARD_NRF9131EK_NRF9131_NS - -if BUILD_WITH_TFM - -# By default, if we build with TF-M, instruct build system to -# flash the combined TF-M (Secure) & Zephyr (Non Secure) image -config TFM_FLASH_MERGED_BINARY - bool - default y - -endif # BUILD_WITH_TFM - # For the secure version of the board the firmware is linked at the beginning # of the flash, or into the code-partition defined in DT if it is intended to # be loaded by MCUboot. If the secure firmware is to be combined with a non- From 1975a842591153dd6dd68c468dcbb6b29cf3ff29 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:39 +0200 Subject: [PATCH 2316/2402] Revert "[nrf noup] boards: thingy53_nrf5340: Enable MCUboot by default" This reverts commit b923938da11c598ad0c5d0b3a7eeacf3d771a166. Signed-off-by: Gerard Marull-Paretas --- boards/arm/thingy53_nrf5340/Kconfig.defconfig | 6 ------ boards/arm/thingy53_nrf5340/thingy53_nrf5340_common.dtsi | 1 - 2 files changed, 7 deletions(-) diff --git a/boards/arm/thingy53_nrf5340/Kconfig.defconfig b/boards/arm/thingy53_nrf5340/Kconfig.defconfig index 2c5dfa46d9c..0b9246e1787 100644 --- a/boards/arm/thingy53_nrf5340/Kconfig.defconfig +++ b/boards/arm/thingy53_nrf5340/Kconfig.defconfig @@ -8,12 +8,6 @@ if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS config BOARD default "thingy53_nrf5340_cpuapp" -config BOOTLOADER_MCUBOOT - default y if !MCUBOOT - -config BOARD_ENABLE_CPUNET - default y if !MCUBOOT - # Code Partition: # # For the secure version of the board the firmware is linked at the beginning diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_common.dtsi b/boards/arm/thingy53_nrf5340/thingy53_nrf5340_common.dtsi index 54efd588cf7..694a6960584 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_common.dtsi +++ b/boards/arm/thingy53_nrf5340/thingy53_nrf5340_common.dtsi @@ -16,7 +16,6 @@ zephyr,bt-hci-ipc = &ipc0; nordic,802154-spinel-ipc = &ipc0; zephyr,ieee802154 = &ieee802154; - nordic,pm-ext-flash = &mx25r64; }; buttons { From a28972bb2f81c77e987ca659ad6a743cd7d77738 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:39 +0200 Subject: [PATCH 2317/2402] Revert "[nrf noup] boards: arm: thingy53: Disable USB CDC added by MCUBoot" This reverts commit ef801f13ca0f4dd63cced39b527f6adb90c1eff0. Signed-off-by: Gerard Marull-Paretas --- boards/arm/thingy53_nrf5340/Kconfig.defconfig | 7 ------- 1 file changed, 7 deletions(-) diff --git a/boards/arm/thingy53_nrf5340/Kconfig.defconfig b/boards/arm/thingy53_nrf5340/Kconfig.defconfig index 0b9246e1787..12f1e5bbdc9 100644 --- a/boards/arm/thingy53_nrf5340/Kconfig.defconfig +++ b/boards/arm/thingy53_nrf5340/Kconfig.defconfig @@ -136,13 +136,6 @@ endif # LOG endif # BOARD_SERIAL_BACKEND_CDC_ACM -# By default, a USB CDC ACM instance is already enabled in the board's DTS. -# It is not necessary for nRF Connect SDK to add another instance if MCUBoot -# bootloader is built as a child image. -config MCUBOOT_USB_SUPPORT - bool - default n - endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS if BOARD_THINGY53_NRF5340_CPUNET From 7c14eba611f9ff7eb686ff8c12d2822384ac04d9 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:39 +0200 Subject: [PATCH 2318/2402] Revert "[nrf noup] boards: thingy53_nrf5340: Add common partition map" This reverts commit 5b9d7df92cafb0e4b97430d61e3717055b46743a. Signed-off-by: Gerard Marull-Paretas --- .../pm_static_thingy53_nrf5340_cpuapp.yml | 55 -------------- .../pm_static_thingy53_nrf5340_cpuapp_ns.yml | 73 ------------------- 2 files changed, 128 deletions(-) delete mode 100644 boards/arm/thingy53_nrf5340/pm_static_thingy53_nrf5340_cpuapp.yml delete mode 100644 boards/arm/thingy53_nrf5340/pm_static_thingy53_nrf5340_cpuapp_ns.yml diff --git a/boards/arm/thingy53_nrf5340/pm_static_thingy53_nrf5340_cpuapp.yml b/boards/arm/thingy53_nrf5340/pm_static_thingy53_nrf5340_cpuapp.yml deleted file mode 100644 index 7a48d51ec33..00000000000 --- a/boards/arm/thingy53_nrf5340/pm_static_thingy53_nrf5340_cpuapp.yml +++ /dev/null @@ -1,55 +0,0 @@ -app: - address: 0x10200 - region: flash_primary - size: 0xdfe00 -mcuboot: - address: 0x0 - region: flash_primary - size: 0x10000 -mcuboot_pad: - address: 0x10000 - region: flash_primary - size: 0x200 -mcuboot_primary: - address: 0x10000 - orig_span: &id001 - - mcuboot_pad - - app - region: flash_primary - size: 0xe0000 - span: *id001 -mcuboot_primary_app: - address: 0x10200 - orig_span: &id002 - - app - region: flash_primary - size: 0xdfe00 - span: *id002 -settings_storage: - address: 0xf0000 - region: flash_primary - size: 0x10000 -mcuboot_primary_1: - address: 0x0 - size: 0x40000 - device: flash_ctrl - region: ram_flash -mcuboot_secondary: - address: 0x00000 - size: 0xe0000 - device: MX25R64 - region: external_flash -mcuboot_secondary_1: - address: 0xe0000 - size: 0x40000 - device: MX25R64 - region: external_flash -external_flash: - address: 0x120000 - size: 0x6e0000 - device: MX25R64 - region: external_flash -pcd_sram: - address: 0x20000000 - size: 0x2000 - region: sram_primary diff --git a/boards/arm/thingy53_nrf5340/pm_static_thingy53_nrf5340_cpuapp_ns.yml b/boards/arm/thingy53_nrf5340/pm_static_thingy53_nrf5340_cpuapp_ns.yml deleted file mode 100644 index 70ffe6d9c12..00000000000 --- a/boards/arm/thingy53_nrf5340/pm_static_thingy53_nrf5340_cpuapp_ns.yml +++ /dev/null @@ -1,73 +0,0 @@ -mcuboot: - address: 0x0 - region: flash_primary - size: 0x10000 -mcuboot_pad: - address: 0x10000 - region: flash_primary - size: 0x200 -tfm_secure: - address: 0x10000 - size: 0xc000 - span: [mcuboot_pad, tfm] -tfm_nonsecure: - address: 0x1c000 - size: 0xd4000 - span: [app] -tfm: - address: 0x10200 - region: flash_primary - size: 0xbe00 -app: - address: 0x1c000 - region: flash_primary - size: 0xd4000 -mcuboot_primary: - address: 0x10000 - orig_span: &id001 - - mcuboot_pad - - tfm - - app - region: flash_primary - size: 0xe0000 - span: *id001 -mcuboot_primary_app: - address: 0x10200 - orig_span: &id002 - - tfm - - app - region: flash_primary - size: 0xdfe00 - span: *id002 -nonsecure_storage: - address: 0xf0000 - size: 0x10000 - span: [settings_storage] -settings_storage: - address: 0xf0000 - region: flash_primary - size: 0x10000 -mcuboot_primary_1: - address: 0x0 - size: 0x40000 - device: flash_ctrl - region: ram_flash -mcuboot_secondary: - address: 0x00000 - size: 0xe0000 - device: MX25R64 - region: external_flash -mcuboot_secondary_1: - address: 0xe0000 - size: 0x40000 - device: MX25R64 - region: external_flash -external_flash: - address: 0x120000 - size: 0x6e0000 - device: MX25R64 - region: external_flash -pcd_sram: - address: 0x20000000 - size: 0x2000 - region: sram_primary From be1bdd9051ad2627231f5b20cd0016718a3a7656 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:39 +0200 Subject: [PATCH 2319/2402] Revert "[nrf noup] soc: arm: nRF91: Add SPU Flash/RAM alignment" This reverts commit 95a3bde0a6269dbe41e22fc97d6259070d170d2c. Signed-off-by: Gerard Marull-Paretas --- soc/arm/nordic_nrf/nrf91/Kconfig.series | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.series b/soc/arm/nordic_nrf/nrf91/Kconfig.series index 08d36e5b48c..1be69c377e5 100644 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.series +++ b/soc/arm/nordic_nrf/nrf91/Kconfig.series @@ -27,23 +27,9 @@ config NRF_SPU_FLASH_REGION_SIZE help FLASH region size for the NRF_SPU peripheral -config NRF_SPU_FLASH_REGION_ALIGNMENT - hex - default 0x8000 - help - FLASH regions must be aligned to this value due to SPU HW - limitations. - config NRF_SPU_RAM_REGION_SIZE hex default 0x2000 help RAM region size for the NRF_SPU peripheral - -config NRF_SPU_RAM_REGION_ALIGNMENT - hex - default 0x2000 - help - RAM regions must be aligned to this value due to SPU HW - limitations. endif From e7687c1a9f96a4e95932aa5e7caca743a37dae51 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:40 +0200 Subject: [PATCH 2320/2402] Revert "[nrf noup] soc: arm: nRF53: Add SPU Flash/RAM alignment" This reverts commit 58d05502b3e1bb25e70d64f7b255cf0a387699fa. Signed-off-by: Gerard Marull-Paretas --- soc/arm/nordic_nrf/nrf53/Kconfig.soc | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.soc b/soc/arm/nordic_nrf/nrf53/Kconfig.soc index b3ca2661675..3ecf09ecd92 100644 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.soc +++ b/soc/arm/nordic_nrf/nrf53/Kconfig.soc @@ -124,26 +124,12 @@ config NRF_SPU_FLASH_REGION_SIZE help FLASH region size for the NRF_SPU peripheral -config NRF_SPU_FLASH_REGION_ALIGNMENT - hex - default 0x4000 - help - FLASH regions must be aligned to this value due to SPU HW - limitations. - config NRF_SPU_RAM_REGION_SIZE hex default 0x2000 help RAM region size for the NRF_SPU peripheral -config NRF_SPU_RAM_REGION_ALIGNMENT - hex - default 0x2000 - help - RAM regions must be aligned to this value due to SPU HW - limitations. - config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 bool depends on NRF_SOC_SECURE_SUPPORTED From 0e6eb70cf650c2d7adfbc5bd50baf85a6b761e1c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:40 +0200 Subject: [PATCH 2321/2402] Revert "[nrf noup] net: mqtt: add native TLS support" This reverts commit b09985d98a322c19c5e777bdb1c043897c733e30. Signed-off-by: Gerard Marull-Paretas --- doc/connectivity/networking/api/mqtt.rst | 3 --- include/zephyr/net/mqtt.h | 3 --- subsys/net/lib/mqtt/mqtt_transport_socket_tls.c | 7 +------ 3 files changed, 1 insertion(+), 12 deletions(-) diff --git a/doc/connectivity/networking/api/mqtt.rst b/doc/connectivity/networking/api/mqtt.rst index 79da5abe57b..b232f125333 100644 --- a/doc/connectivity/networking/api/mqtt.rst +++ b/doc/connectivity/networking/api/mqtt.rst @@ -150,7 +150,6 @@ additional configuration information: tls_config->sec_tag_list = m_sec_tags; tls_config->sec_tag_count = ARRAY_SIZE(m_sec_tags); tls_config->hostname = MQTT_BROKER_HOSTNAME; - tls_config->set_native_tls = true; In this sample code, the ``m_sec_tags`` array holds a list of tags, referencing TLS credentials that the MQTT library should use for authentication. We do not specify @@ -163,8 +162,6 @@ Note, that TLS credentials referenced by the ``m_sec_tags`` array must be registered in the system first. For more information on how to do that, refer to :ref:`secure sockets documentation `. -Finally, ``set_native_tls`` can be optionally set to enable native TLS support instead of offloading TLS operations to the modem. - An example of how to use TLS with MQTT is also present in :zephyr:code-sample:`mqtt-publisher` sample application. diff --git a/include/zephyr/net/mqtt.h b/include/zephyr/net/mqtt.h index 906cd8f6be6..83ec02a5999 100644 --- a/include/zephyr/net/mqtt.h +++ b/include/zephyr/net/mqtt.h @@ -366,9 +366,6 @@ struct mqtt_sec_config { /** Indicates the preference for copying certificates to the heap. */ int cert_nocopy; - - /** Set socket to native TLS */ - bool set_native_tls; }; /** @brief MQTT transport type. */ diff --git a/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c b/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c index 8e9cc87239a..363ff51afef 100644 --- a/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c +++ b/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c @@ -22,15 +22,10 @@ int mqtt_client_tls_connect(struct mqtt_client *client) { const struct sockaddr *broker = client->broker; struct mqtt_sec_config *tls_config = &client->transport.tls.config; - int type = SOCK_STREAM; int ret; - if (tls_config->set_native_tls) { - type |= SOCK_NATIVE_TLS; - } - client->transport.tls.sock = zsock_socket(broker->sa_family, - type, IPPROTO_TLS_1_2); + SOCK_STREAM, IPPROTO_TLS_1_2); if (client->transport.tls.sock < 0) { return -errno; } From 854bf1f2f9b4604f52e4449608a7a159f77db4c8 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:40 +0200 Subject: [PATCH 2322/2402] Revert "[nrf noup] net: mqtt: Provide option to enable TLS session caching" This reverts commit 188c2707060bfc6b054971b899c01c4408d5296a. Signed-off-by: Gerard Marull-Paretas --- include/zephyr/net/mqtt.h | 3 --- subsys/net/lib/mqtt/mqtt_transport_socket_tls.c | 10 ---------- 2 files changed, 13 deletions(-) diff --git a/include/zephyr/net/mqtt.h b/include/zephyr/net/mqtt.h index 83ec02a5999..f1071af64f2 100644 --- a/include/zephyr/net/mqtt.h +++ b/include/zephyr/net/mqtt.h @@ -356,9 +356,6 @@ struct mqtt_sec_config { /** Indicates the list of security tags to be used for the session. */ const sec_tag_t *sec_tag_list; - /** Indicates the preference for enabling TLS session caching. */ - int session_cache; - /** Peer hostname for ceritificate verification. * May be NULL to skip hostname verification. */ diff --git a/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c b/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c index 363ff51afef..c835656b6cf 100644 --- a/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c +++ b/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c @@ -78,16 +78,6 @@ int mqtt_client_tls_connect(struct mqtt_client *client) } } - if (tls_config->session_cache == TLS_SESSION_CACHE_ENABLED) { - ret = zsock_setsockopt(client->transport.tls.sock, SOL_TLS, - TLS_SESSION_CACHE, - &tls_config->session_cache, - sizeof(tls_config->session_cache)); - if (ret < 0) { - goto error; - } - } - if (tls_config->cert_nocopy != TLS_CERT_NOCOPY_NONE) { ret = zsock_setsockopt(client->transport.tls.sock, SOL_TLS, TLS_CERT_NOCOPY, &tls_config->cert_nocopy, From 3c86da18e5cd1ff6122f448d52f37f81e5db8902 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:40 +0200 Subject: [PATCH 2323/2402] Revert "[nrf noup] test: schedule_api: Use Minimal C library" This reverts commit 2f2142f031254c1c1abc858be2b55afed1ca8b8f. Signed-off-by: Gerard Marull-Paretas --- tests/kernel/sched/schedule_api/prj.conf | 1 - tests/kernel/sched/schedule_api/prj_dumb.conf | 1 - tests/kernel/sched/schedule_api/prj_multiq.conf | 1 - 3 files changed, 3 deletions(-) diff --git a/tests/kernel/sched/schedule_api/prj.conf b/tests/kernel/sched/schedule_api/prj.conf index 785e9a3987b..fe5125047e3 100644 --- a/tests/kernel/sched/schedule_api/prj.conf +++ b/tests/kernel/sched/schedule_api/prj.conf @@ -7,4 +7,3 @@ CONFIG_MAX_THREAD_BYTES=5 CONFIG_TEST_USERSPACE=y CONFIG_MP_MAX_NUM_CPUS=1 CONFIG_ZTEST_FATAL_HOOK=y -CONFIG_MINIMAL_LIBC=y diff --git a/tests/kernel/sched/schedule_api/prj_dumb.conf b/tests/kernel/sched/schedule_api/prj_dumb.conf index a1d0cf6dced..c0ddfbd7c3f 100644 --- a/tests/kernel/sched/schedule_api/prj_dumb.conf +++ b/tests/kernel/sched/schedule_api/prj_dumb.conf @@ -5,4 +5,3 @@ CONFIG_SCHED_DUMB=y CONFIG_MAX_THREAD_BYTES=5 CONFIG_MP_MAX_NUM_CPUS=1 CONFIG_ZTEST_FATAL_HOOK=y -CONFIG_MINIMAL_LIBC=y diff --git a/tests/kernel/sched/schedule_api/prj_multiq.conf b/tests/kernel/sched/schedule_api/prj_multiq.conf index 77b3a49fd34..18d04dd8656 100644 --- a/tests/kernel/sched/schedule_api/prj_multiq.conf +++ b/tests/kernel/sched/schedule_api/prj_multiq.conf @@ -5,4 +5,3 @@ CONFIG_SCHED_MULTIQ=y CONFIG_MAX_THREAD_BYTES=5 CONFIG_MP_MAX_NUM_CPUS=1 CONFIG_ZTEST_FATAL_HOOK=y -CONFIG_MINIMAL_LIBC=y From 24b3646c76ab717ab01cc269c69090e18f8d9861 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:40 +0200 Subject: [PATCH 2324/2402] Revert "[nrf noup] ci: NCS-specific CI tweaks" This reverts commit 4cf7a19e8939c0f44293e431a11139d41e115328. Signed-off-by: Gerard Marull-Paretas --- .github/workflows/commit-tags.yml | 31 -------------------------- .github/workflows/compliance.yml | 8 +++---- Jenkinsfile | 5 ----- scripts/gitlint/zephyr_commit_rules.py | 4 ++-- 4 files changed, 6 insertions(+), 42 deletions(-) delete mode 100644 .github/workflows/commit-tags.yml delete mode 100644 Jenkinsfile diff --git a/.github/workflows/commit-tags.yml b/.github/workflows/commit-tags.yml deleted file mode 100644 index 9e0323f9498..00000000000 --- a/.github/workflows/commit-tags.yml +++ /dev/null @@ -1,31 +0,0 @@ -name: Commit tags - -on: pull_request - -jobs: - commit_tags: - runs-on: ubuntu-22.04 - name: Run commit tags checks on patch series (PR) - steps: - - name: Update PATH for west - run: | - echo "$HOME/.local/bin" >> $GITHUB_PATH - - - name: Checkout the code - uses: actions/checkout@v3 - with: - ref: ${{ github.event.pull_request.head.sha }} - fetch-depth: 0 - - - name: Install python dependencies - run: | - pip3 install setuptools - pip3 install wheel - pip3 install gitlint - - - name: Run the commit tags - uses: nrfconnect/action-commit-tags@main - with: - target: '.' - baserev: origin/${{ github.base_ref }} - revrange: 'none' diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 5dc913626cd..219fbfae607 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -38,8 +38,8 @@ jobs: git config --global user.name "Your Name" git remote -v # Ensure there's no merge commits in the PR - #[[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \ - #(echo "::error ::Merge commits not allowed, rebase instead";false) + [[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \ + (echo "::error ::Merge commits not allowed, rebase instead";false) git rebase origin/${BASE_REF} # debug git log --pretty=oneline | head -n 10 @@ -57,8 +57,8 @@ jobs: # debug ls -la git log --pretty=oneline | head -n 10 - ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -e Kconfig \ - -e KconfigBasicNoModules -e ModulesMaintainers -c origin/${BASE_REF}.. + ./scripts/ci/check_compliance.py --annotate -e KconfigBasic \ + -c origin/${BASE_REF}.. - name: upload-results uses: actions/upload-artifact@v4 diff --git a/Jenkinsfile b/Jenkinsfile deleted file mode 100644 index 3b9cf002239..00000000000 --- a/Jenkinsfile +++ /dev/null @@ -1,5 +0,0 @@ -@Library("CI_LIB") _ - -def pipeline = new ncs.sdk_zephyr.Main() - -pipeline.run(JOB_NAME) diff --git a/scripts/gitlint/zephyr_commit_rules.py b/scripts/gitlint/zephyr_commit_rules.py index d39c7997e26..ea31c6737f3 100644 --- a/scripts/gitlint/zephyr_commit_rules.py +++ b/scripts/gitlint/zephyr_commit_rules.py @@ -78,7 +78,7 @@ class TitleMaxLengthRevert(LineRule): name = "title-max-length-no-revert" id = "UC5" target = CommitMessageTitle - options_spec = [IntOption('line-length', 120, "Max line length")] + options_spec = [IntOption('line-length', 75, "Max line length")] violation_message = "Commit title exceeds max length ({0}>{1})" def validate(self, line, _commit): @@ -103,7 +103,7 @@ class MaxLineLengthExceptions(LineRule): name = "max-line-length-with-exceptions" id = "UC4" target = CommitMessageBody - options_spec = [IntOption('line-length', 120, "Max line length")] + options_spec = [IntOption('line-length', 75, "Max line length")] violation_message = "Commit message body line exceeds max length ({0}>{1})" def validate(self, line, _commit): From 82b067c7d3348428400e0b936690969efc22e2c2 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:41 +0200 Subject: [PATCH 2325/2402] Revert "[nrf fromlist] Bluetooth: ATT: lock scheduler when sending from user thread" This reverts commit e71b56e87ba8b50962709a68593076a771bfe50e. Signed-off-by: Gerard Marull-Paretas --- subsys/bluetooth/host/att.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/subsys/bluetooth/host/att.c b/subsys/bluetooth/host/att.c index 2ed3dfcb768..35be784c209 100644 --- a/subsys/bluetooth/host/att.c +++ b/subsys/bluetooth/host/att.c @@ -3863,19 +3863,14 @@ int bt_att_req_send(struct bt_conn *conn, struct bt_att_req *req) __ASSERT_NO_MSG(conn); __ASSERT_NO_MSG(req); - k_sched_lock(); - att = att_get(conn); if (!att) { - k_sched_unlock(); return -ENOTCONN; } sys_slist_append(&att->reqs, &req->node); att_req_send_process(att); - k_sched_unlock(); - return 0; } From d47fda791940b9a980f670b467f23aff6a54261a Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:41 +0200 Subject: [PATCH 2326/2402] Revert "[nrf fromlist] net: sockets: packet: Ignore the packet type if LL address is not set" This reverts commit 04aecc5917ed08d4e9d4b7705f5aa99d7c4e4c0f. Signed-off-by: Gerard Marull-Paretas --- subsys/net/lib/sockets/sockets_packet.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/subsys/net/lib/sockets/sockets_packet.c b/subsys/net/lib/sockets/sockets_packet.c index ce4f83190c4..bcf063abe29 100644 --- a/subsys/net/lib/sockets/sockets_packet.c +++ b/subsys/net/lib/sockets/sockets_packet.c @@ -144,10 +144,6 @@ static void zpacket_set_eth_pkttype(struct net_if *iface, struct sockaddr_ll *addr, struct net_linkaddr *lladdr) { - if (lladdr == NULL || lladdr->addr == NULL) { - return; - } - if (net_eth_is_addr_broadcast((struct net_eth_addr *)lladdr->addr)) { addr->sll_pkttype = PACKET_BROADCAST; } else if (net_eth_is_addr_multicast( From 68db38b516fbed2dc6be13c8628de7c45ff8d65e Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:41 +0200 Subject: [PATCH 2327/2402] Revert "[nrf fromtree] manifest: remove .git suffixes from repo-paths" This reverts commit 9982b0f82554206e4c5ecd79919aea8b212447bf. Signed-off-by: Gerard Marull-Paretas --- west.yml | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/west.yml b/west.yml index 4d04f7fecaf..da5a202241b 100644 --- a/west.yml +++ b/west.yml @@ -40,77 +40,77 @@ manifest: - babblesim - name: babblesim_base remote: babblesim - repo-path: base + repo-path: base.git path: tools/bsim/components revision: 19d62424c0802c6c9fc15528febe666e40f372a1 groups: - babblesim - name: babblesim_ext_2G4_libPhyComv1 remote: babblesim - repo-path: ext_2G4_libPhyComv1 + repo-path: ext_2G4_libPhyComv1.git path: tools/bsim/components/ext_2G4_libPhyComv1 revision: 9018113a362fa6c9e8f4b9cab9e5a8f12cc46b94 groups: - babblesim - name: babblesim_ext_2G4_phy_v1 remote: babblesim - repo-path: ext_2G4_phy_v1 + repo-path: ext_2G4_phy_v1.git path: tools/bsim/components/ext_2G4_phy_v1 revision: d47c6dd90035b41b14f6921785ccb7b8484868e2 groups: - babblesim - name: babblesim_ext_2G4_channel_NtNcable remote: babblesim - repo-path: ext_2G4_channel_NtNcable + repo-path: ext_2G4_channel_NtNcable.git path: tools/bsim/components/ext_2G4_channel_NtNcable revision: 20a38c997f507b0aa53817aab3d73a462fff7af1 groups: - babblesim - name: babblesim_ext_2G4_channel_multiatt remote: babblesim - repo-path: ext_2G4_channel_multiatt + repo-path: ext_2G4_channel_multiatt.git path: tools/bsim/components/ext_2G4_channel_multiatt revision: bde72a57384dde7a4310bcf3843469401be93074 groups: - babblesim - name: babblesim_ext_2G4_modem_magic remote: babblesim - repo-path: ext_2G4_modem_magic + repo-path: ext_2G4_modem_magic.git path: tools/bsim/components/ext_2G4_modem_magic revision: cb70771794f0bf6f262aa474848611c68ae8f1ed groups: - babblesim - name: babblesim_ext_2G4_modem_BLE_simple remote: babblesim - repo-path: ext_2G4_modem_BLE_simple + repo-path: ext_2G4_modem_BLE_simple.git path: tools/bsim/components/ext_2G4_modem_BLE_simple revision: 809ab073159c9ab6686c2fea5749b0702e0909f7 groups: - babblesim - name: babblesim_ext_2G4_device_burst_interferer remote: babblesim - repo-path: ext_2G4_device_burst_interferer + repo-path: ext_2G4_device_burst_interferer.git path: tools/bsim/components/ext_2G4_device_burst_interferer revision: 5b5339351d6e6a2368c686c734dc8b2fc65698fc groups: - babblesim - name: babblesim_ext_2G4_device_WLAN_actmod remote: babblesim - repo-path: ext_2G4_device_WLAN_actmod + repo-path: ext_2G4_device_WLAN_actmod.git path: tools/bsim/components/ext_2G4_device_WLAN_actmod revision: 9cb6d8e72695f6b785e57443f0629a18069d6ce4 groups: - babblesim - name: babblesim_ext_2G4_device_playback remote: babblesim - repo-path: ext_2G4_device_playback + repo-path: ext_2G4_device_playback.git path: tools/bsim/components/ext_2G4_device_playback revision: 85c645929cf1ce995d8537107d9dcbd12ed64036 groups: - babblesim - name: babblesim_ext_libCryptov1 remote: babblesim - repo-path: ext_libCryptov1 + repo-path: ext_libCryptov1.git path: tools/bsim/components/ext_libCryptov1 revision: eed6d7038e839153e340bd333bc43541cb90ba64 groups: From e2e355586afe3fc583124e73d0f830aa7a9e1c60 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:41 +0200 Subject: [PATCH 2328/2402] Revert "[nrf fromlist] kconfig: shell: fix incorrect shell stack size for Thread" This reverts commit 724394e5c95d1424daead22e5550d06c26c92fcb. Signed-off-by: Gerard Marull-Paretas --- subsys/shell/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/subsys/shell/Kconfig b/subsys/shell/Kconfig index 618570af1e2..45e469ac457 100644 --- a/subsys/shell/Kconfig +++ b/subsys/shell/Kconfig @@ -40,8 +40,9 @@ endif config SHELL_STACK_SIZE int "Shell thread stack size" - default 3168 if OPENTHREAD_SHELL + default 3168 if OPENTHREAD_SHELL && OPENTHREAD_JOINER default 3072 if 64BIT + default 2616 if OPENTHREAD_SHELL default 2048 if MULTITHREADING default 0 if !MULTITHREADING help From c731bf15f8fb351cc3e4f7464cbf396ad783a16b Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:41 +0200 Subject: [PATCH 2329/2402] Revert "[nrf fromlist] modules: hal_nordic: remove weak nrf_802154_clock_hfclk_ready" This reverts commit 7e15ea29496a13608de49588efa0a2bdd7511900. Signed-off-by: Gerard Marull-Paretas --- .../sl_opensource/platform/nrf_802154_clock_zephyr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/modules/hal_nordic/nrf_802154/sl_opensource/platform/nrf_802154_clock_zephyr.c b/modules/hal_nordic/nrf_802154/sl_opensource/platform/nrf_802154_clock_zephyr.c index 3a3d9501d0c..c9260bf278a 100644 --- a/modules/hal_nordic/nrf_802154/sl_opensource/platform/nrf_802154_clock_zephyr.c +++ b/modules/hal_nordic/nrf_802154/sl_opensource/platform/nrf_802154_clock_zephyr.c @@ -109,6 +109,11 @@ bool nrf_802154_clock_lfclk_is_running(void) return lfclk_is_running; } +__WEAK void nrf_802154_clock_hfclk_ready(void) +{ + /* Intentionally empty. */ +} + __WEAK void nrf_802154_clock_lfclk_ready(void) { /* Intentionally empty. */ From bfd3104d68004c77a94ef3c62b5f7c5a14d2f0aa Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:42 +0200 Subject: [PATCH 2330/2402] Revert "[nrf fromlist] drivers: mbox: nrf_bellboard: add initial driver" This reverts commit cc15acc1654fb0687e6cf107b8cb692d03405fbf. Signed-off-by: Gerard Marull-Paretas --- drivers/mbox/CMakeLists.txt | 2 - drivers/mbox/Kconfig | 1 - drivers/mbox/Kconfig.nrf_bellboard | 16 --- drivers/mbox/mbox_nrf_bellboard_local.c | 169 ----------------------- drivers/mbox/mbox_nrf_bellboard_remote.c | 62 --------- 5 files changed, 250 deletions(-) delete mode 100644 drivers/mbox/Kconfig.nrf_bellboard delete mode 100644 drivers/mbox/mbox_nrf_bellboard_local.c delete mode 100644 drivers/mbox/mbox_nrf_bellboard_remote.c diff --git a/drivers/mbox/CMakeLists.txt b/drivers/mbox/CMakeLists.txt index 1d5c65cded7..b8e28afe6b4 100644 --- a/drivers/mbox/CMakeLists.txt +++ b/drivers/mbox/CMakeLists.txt @@ -12,5 +12,3 @@ zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_MAILBOX mbox_nxp_mailbox.c) zephyr_library_sources_ifdef(CONFIG_MBOX_ANDES_PLIC_SW mbox_andes_plic_sw.c) zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_VEVIF_LOCAL mbox_nrf_vevif_local.c) zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_VEVIF_REMOTE mbox_nrf_vevif_remote.c) -zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_BELLBOARD_LOCAL mbox_nrf_bellboard_local.c) -zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_BELLBOARD_REMOTE mbox_nrf_bellboard_remote.c) diff --git a/drivers/mbox/Kconfig b/drivers/mbox/Kconfig index 7f00324ba47..c6fe36832c9 100644 --- a/drivers/mbox/Kconfig +++ b/drivers/mbox/Kconfig @@ -18,7 +18,6 @@ source "drivers/mbox/Kconfig.nxp_imx" source "drivers/mbox/Kconfig.nxp_mailbox" source "drivers/mbox/Kconfig.andes" source "drivers/mbox/Kconfig.nrf_vevif" -source "drivers/mbox/Kconfig.nrf_bellboard" config MBOX_INIT_PRIORITY int "MBOX init priority" diff --git a/drivers/mbox/Kconfig.nrf_bellboard b/drivers/mbox/Kconfig.nrf_bellboard deleted file mode 100644 index 45233122bd5..00000000000 --- a/drivers/mbox/Kconfig.nrf_bellboard +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config MBOX_NRF_BELLBOARD_LOCAL - bool "nRF BELLBOARD local driver" - depends on DT_HAS_NORDIC_NRF_BELLBOARD_LOCAL_ENABLED - default y - help - Mailbox driver for local Nordic nRF BELLBOARD - -config MBOX_NRF_BELLBOARD_REMOTE - bool "nRF BELLBOARD remote driver" - depends on DT_HAS_NORDIC_NRF_BELLBOARD_REMOTE_ENABLED - default y - help - Mailbox driver for remote Nordic nRF BELLBOARD diff --git a/drivers/mbox/mbox_nrf_bellboard_local.c b/drivers/mbox/mbox_nrf_bellboard_local.c deleted file mode 100644 index 99d05351aaa..00000000000 --- a/drivers/mbox/mbox_nrf_bellboard_local.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT nordic_nrf_bellboard_local - -#include -#include -#include - -#include - -#define BELLBOARD_NUM_IRQS 4U - -BUILD_ASSERT(DT_NUM_IRQS(DT_DRV_INST(0)) <= BELLBOARD_NUM_IRQS, "# interrupt exceeds maximum"); - -BUILD_ASSERT((DT_INST_PROP_LEN(0, nordic_interrupt_mapping) % 2) == 0, - "# interrupt mappings not specified in pairs"); - -/* BELLBOARD event mappings */ -#define EVT_MAPPING_ITEM(idx) DT_INST_PROP_BY_IDX(0, nordic_interrupt_mapping, idx) -#define BELLBOARD_GET_EVT_MAPPING(idx, _) \ - COND_CODE_1( \ - DT_INST_PROP_HAS_IDX(0, nordic_interrupt_mapping, UTIL_INC(UTIL_X2(idx))), \ - ([EVT_MAPPING_ITEM(UTIL_INC(UTIL_X2(idx)))] = EVT_MAPPING_ITEM(UTIL_X2(idx)),), \ - ()) - -static const uint32_t evt_mappings[BELLBOARD_NUM_IRQS] = { - LISTIFY(DT_NUM_IRQS(DT_DRV_INST(0)), BELLBOARD_GET_EVT_MAPPING, ())}; - -/* BELLBOARD instance */ -static NRF_BELLBOARD_Type *bellboard = (NRF_BELLBOARD_Type *)DT_INST_REG_ADDR(0); - -/* BELLBOARD runtime resources */ -static mbox_callback_t cbs[NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT]; -static void *cbs_ctx[NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT]; -static uint32_t evt_enabled_masks[BELLBOARD_NUM_IRQS]; - -static void bellboard_local_isr(const void *parameter) -{ - uint8_t irq_idx = (uint8_t)(uintptr_t)parameter; - uint32_t int_pend; - - int_pend = nrf_bellboard_int_pending_get(bellboard, irq_idx); - - for (uint8_t i = 0U; i < NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT; i++) { - nrf_bellboard_event_t event = nrf_bellboard_triggered_event_get(i); - - if (nrf_bellboard_event_check(bellboard, event)) { - nrf_bellboard_event_clear(bellboard, event); - } - - if ((int_pend & BIT(i)) != 0U) { - if (cbs[i] != NULL) { - cbs[i](DEVICE_DT_INST_GET(0), i, cbs_ctx[i], NULL); - } - } - } -} - -static uint32_t bellboard_local_max_channels_get(const struct device *dev) -{ - ARG_UNUSED(dev); - - return NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT; -} - -static int bellboard_local_register_callback(const struct device *dev, uint32_t id, - mbox_callback_t cb, void *user_data) -{ - ARG_UNUSED(dev); - - if (id >= NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT) { - return -EINVAL; - } - - cbs[id] = cb; - cbs_ctx[id] = user_data; - - return 0; -} - -static int bellboard_local_set_enabled(const struct device *dev, uint32_t id, bool enable) -{ - bool valid_found = false; - - ARG_UNUSED(dev); - - if (id >= NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT) { - return -EINVAL; - } - - for (uint8_t i = 0U; i < BELLBOARD_NUM_IRQS; i++) { - uint32_t *evt_enabled_mask; - - if ((evt_mappings[i] == 0U) || ((evt_mappings[i] & BIT(id)) == 0U)) { - continue; - } - - valid_found = true; - evt_enabled_mask = &evt_enabled_masks[i]; - - if (enable) { - if ((*evt_enabled_mask & BIT(id)) != 0U) { - return -EALREADY; - } - - *evt_enabled_mask |= BIT(id); - nrf_bellboard_int_enable(bellboard, i, BIT(id)); - } else { - if ((*evt_enabled_mask & BIT(id)) == 0U) { - return -EALREADY; - } - - *evt_enabled_mask &= ~BIT(id); - nrf_bellboard_int_disable(bellboard, i, BIT(id)); - } - } - - if (!valid_found) { - return -EINVAL; - } - - return 0; -} - -static const struct mbox_driver_api bellboard_local_driver_api = { - .max_channels_get = bellboard_local_max_channels_get, - .register_callback = bellboard_local_register_callback, - .set_enabled = bellboard_local_set_enabled, -}; - -#define BELLBOARD_IRQ_CONFIGURE(name, idx) \ - COND_CODE_1(DT_INST_IRQ_HAS_NAME(0, name), \ - (IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, name, irq), \ - DT_INST_IRQ_BY_NAME(0, name, priority), bellboard_local_isr, \ - (const void *)idx, 0); \ - irq_enable(DT_INST_IRQ_BY_NAME(0, name, irq));), \ - ()) - -static int bellboard_local_init(const struct device *dev) -{ - uint32_t evt_all_mappings = - evt_mappings[0] | evt_mappings[1] | evt_mappings[2] | evt_mappings[3]; - - ARG_UNUSED(dev); - - nrf_bellboard_int_disable(bellboard, 0, evt_mappings[0]); - nrf_bellboard_int_disable(bellboard, 1, evt_mappings[1]); - nrf_bellboard_int_disable(bellboard, 2, evt_mappings[2]); - nrf_bellboard_int_disable(bellboard, 3, evt_mappings[3]); - - for (uint8_t i = 0U; i < NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT; i++) { - if ((evt_all_mappings & BIT(i)) != 0U) { - nrf_bellboard_event_clear(bellboard, nrf_bellboard_triggered_event_get(i)); - } - } - - BELLBOARD_IRQ_CONFIGURE(irq0, 0); - BELLBOARD_IRQ_CONFIGURE(irq1, 1); - BELLBOARD_IRQ_CONFIGURE(irq2, 2); - BELLBOARD_IRQ_CONFIGURE(irq3, 3); - - return 0; -} - -DEVICE_DT_INST_DEFINE(0, bellboard_local_init, NULL, NULL, NULL, POST_KERNEL, - CONFIG_MBOX_INIT_PRIORITY, &bellboard_local_driver_api); diff --git a/drivers/mbox/mbox_nrf_bellboard_remote.c b/drivers/mbox/mbox_nrf_bellboard_remote.c deleted file mode 100644 index c362522c0bf..00000000000 --- a/drivers/mbox/mbox_nrf_bellboard_remote.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT nordic_nrf_bellboard_remote - -#include -#include - -#include - -struct mbox_bellboard_remote_conf { - NRF_BELLBOARD_Type *bellboard; -}; - -static int bellboard_remote_send(const struct device *dev, uint32_t id, const struct mbox_msg *msg) -{ - const struct mbox_bellboard_remote_conf *config = dev->config; - - if (id >= BELLBOARD_TASKS_TRIGGER_MaxCount) { - return -EINVAL; - } - - if (msg != NULL) { - return -ENOTSUP; - } - - nrfy_bellboard_task_trigger(config->bellboard, nrf_bellboard_trigger_task_get(id)); - - return 0; -} - -static int bellboard_remote_mtu_get(const struct device *dev) -{ - ARG_UNUSED(dev); - - return 0; -} - -static uint32_t bellboard_remote_max_channels_get(const struct device *dev) -{ - ARG_UNUSED(dev); - - return BELLBOARD_TASKS_TRIGGER_MaxCount; -} - -static const struct mbox_driver_api bellboard_remote_driver_api = { - .send = bellboard_remote_send, - .mtu_get = bellboard_remote_mtu_get, - .max_channels_get = bellboard_remote_max_channels_get, -}; - -#define BELLBOARD_REMOTE_DEFINE(inst) \ - static const struct mbox_bellboard_remote_conf conf##inst = { \ - .bellboard = (NRF_BELLBOARD_Type *)DT_INST_REG_ADDR(inst), \ - }; \ - \ - DEVICE_DT_INST_DEFINE(inst, NULL, NULL, NULL, &conf##inst, POST_KERNEL, \ - CONFIG_MBOX_INIT_PRIORITY, &bellboard_remote_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(BELLBOARD_REMOTE_DEFINE) From 421daa43f4132e5fa6a17727a6441e079d7e5d41 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:42 +0200 Subject: [PATCH 2331/2402] Revert "[nrf fromlist] dts: bindings: mbox: add nordic,nrf-bellboard-local|remote" This reverts commit 76156d457aab3145e9366602955cac2608d37667. Signed-off-by: Gerard Marull-Paretas --- .../mbox/nordic,nrf-bellboard-common.yaml | 11 ----- .../mbox/nordic,nrf-bellboard-local.yaml | 43 ------------------- .../mbox/nordic,nrf-bellboard-remote.yaml | 22 ---------- 3 files changed, 76 deletions(-) delete mode 100644 dts/bindings/mbox/nordic,nrf-bellboard-common.yaml delete mode 100644 dts/bindings/mbox/nordic,nrf-bellboard-local.yaml delete mode 100644 dts/bindings/mbox/nordic,nrf-bellboard-remote.yaml diff --git a/dts/bindings/mbox/nordic,nrf-bellboard-common.yaml b/dts/bindings/mbox/nordic,nrf-bellboard-common.yaml deleted file mode 100644 index 0d1d0bc26e2..00000000000 --- a/dts/bindings/mbox/nordic,nrf-bellboard-common.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -include: [base.yaml, "mailbox-controller.yaml"] - -properties: - reg: - required: true - -mbox-cells: - - channel diff --git a/dts/bindings/mbox/nordic,nrf-bellboard-local.yaml b/dts/bindings/mbox/nordic,nrf-bellboard-local.yaml deleted file mode 100644 index 5c1709987cc..00000000000 --- a/dts/bindings/mbox/nordic,nrf-bellboard-local.yaml +++ /dev/null @@ -1,43 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: | - Nordic BELLBOARD - - BELLBOARD provides support for inter-domain software signaling. It implements - a set of tasks and events intended for signaling within an interprocessor - communication (IPC) framework. When used in local mode, the BELLBOARD - instance is used to receive events triggered by other remote cores. - - Example definition: - - bellboard: mailbox@deadbeef { - compatible = "nordic,nrf-bellboard-local"; - reg = <0xdeadbeef 0x1000>; - interrupts = <98 NRF_DEFAULT_IRQ_PRIORITY>, - <99 NRF_DEFAULT_IRQ_PRIORITY>; - interrupt-names = "irq2", "irq3"; - nordic,interrupt-mapping = <0x0000000f 2>, <0x000000f0 3>; - #mbox-cells = <1>; - }; - -compatible: "nordic,nrf-bellboard-local" - -include: "nordic,nrf-bellboard-common.yaml" - -properties: - interrupts: - required: true - - interrupt-names: - required: true - - nordic,interrupt-mapping: - type: array - required: true - description: | - Set of interrupt mapping pairs. Each pair consists of a bitmask and an - interrupt identifier. The bitmask is used to indicate which of the 32 - possible events are mapped to the given interrupt. For example, given - <0x0000000f 2>, the first four events are mapped to interrupt 2 - (irq2). diff --git a/dts/bindings/mbox/nordic,nrf-bellboard-remote.yaml b/dts/bindings/mbox/nordic,nrf-bellboard-remote.yaml deleted file mode 100644 index ae17fc916a1..00000000000 --- a/dts/bindings/mbox/nordic,nrf-bellboard-remote.yaml +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: | - Nordic BELLBOARD - - BELLBOARD provides support for inter-domain software signaling. It implements - a set of tasks and events intended for signaling within an interprocessor - communication (IPC) framework. When used in remote mode, the BELLBOARD - instance is used to trigger events to another core. - - Example definition: - - bellboard: mailbox@deadbeef { - compatible = "nordic,nrf-bellboard-remote"; - reg = <0xdeadbeef 0x1000>; - #mbox-cells = <1>; - }; - -compatible: "nordic,nrf-bellboard-remote" - -include: "nordic,nrf-bellboard-common.yaml" From 1005793256bf4580b3befbf6ad0e5772ffb549d9 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:42 +0200 Subject: [PATCH 2332/2402] Revert "[nrf fromlist] drivers: mbox: add initial driver for nRF VEVIF" This reverts commit 630a73a6c641eb2f3152aba23920862439fa4096. Signed-off-by: Gerard Marull-Paretas --- drivers/mbox/CMakeLists.txt | 2 - drivers/mbox/Kconfig | 1 - drivers/mbox/Kconfig.nrf_vevif | 16 ---- drivers/mbox/mbox_nrf_vevif_local.c | 123 --------------------------- drivers/mbox/mbox_nrf_vevif_remote.c | 76 ----------------- 5 files changed, 218 deletions(-) delete mode 100644 drivers/mbox/Kconfig.nrf_vevif delete mode 100644 drivers/mbox/mbox_nrf_vevif_local.c delete mode 100644 drivers/mbox/mbox_nrf_vevif_remote.c diff --git a/drivers/mbox/CMakeLists.txt b/drivers/mbox/CMakeLists.txt index b8e28afe6b4..89e5d58e65c 100644 --- a/drivers/mbox/CMakeLists.txt +++ b/drivers/mbox/CMakeLists.txt @@ -10,5 +10,3 @@ zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_S32_MRU mbox_nxp_s32_mru.c) zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_IMX_MU mbox_nxp_imx_mu.c) zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_MAILBOX mbox_nxp_mailbox.c) zephyr_library_sources_ifdef(CONFIG_MBOX_ANDES_PLIC_SW mbox_andes_plic_sw.c) -zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_VEVIF_LOCAL mbox_nrf_vevif_local.c) -zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_VEVIF_REMOTE mbox_nrf_vevif_remote.c) diff --git a/drivers/mbox/Kconfig b/drivers/mbox/Kconfig index c6fe36832c9..67041e91f59 100644 --- a/drivers/mbox/Kconfig +++ b/drivers/mbox/Kconfig @@ -17,7 +17,6 @@ source "drivers/mbox/Kconfig.nxp_s32" source "drivers/mbox/Kconfig.nxp_imx" source "drivers/mbox/Kconfig.nxp_mailbox" source "drivers/mbox/Kconfig.andes" -source "drivers/mbox/Kconfig.nrf_vevif" config MBOX_INIT_PRIORITY int "MBOX init priority" diff --git a/drivers/mbox/Kconfig.nrf_vevif b/drivers/mbox/Kconfig.nrf_vevif deleted file mode 100644 index 4abb0ef8241..00000000000 --- a/drivers/mbox/Kconfig.nrf_vevif +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config MBOX_NRF_VEVIF_LOCAL - bool "nRF VEVIF local driver" - depends on DT_HAS_NORDIC_NRF_VEVIF_LOCAL_ENABLED - default y - help - Mailbox driver for local Nordic nRF VEVIF (VPR Event Interface) - -config MBOX_NRF_VEVIF_REMOTE - bool "nRF VEVIF remote driver" - depends on DT_HAS_NORDIC_NRF_VEVIF_REMOTE_ENABLED - default y - help - Mailbox driver for remote Nordic nRF VEVIF (VPR Event Interface) diff --git a/drivers/mbox/mbox_nrf_vevif_local.c b/drivers/mbox/mbox_nrf_vevif_local.c deleted file mode 100644 index 31b89e1e6fb..00000000000 --- a/drivers/mbox/mbox_nrf_vevif_local.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT nordic_nrf_vevif_local - -#include -#include - -#include -#include -#include - -#define VEVIF_TASKS_NUM DT_INST_PROP(0, nordic_tasks) -#define VEVIF_TASKS_MASK DT_INST_PROP(0, nordic_tasks_mask) - -BUILD_ASSERT(VEVIF_TASKS_NUM <= VPR_TASKS_TRIGGER_MaxCount, "Number of tasks exceeds maximum"); -BUILD_ASSERT(VEVIF_TASKS_NUM == DT_NUM_IRQS(DT_DRV_INST(0)), "# IRQs != # tasks"); - -/* callbacks */ -struct mbox_vevif_local_cbs { - mbox_callback_t cb[VEVIF_TASKS_NUM]; - void *user_data[VEVIF_TASKS_NUM]; - uint32_t enabled_mask; -}; - -static struct mbox_vevif_local_cbs cbs; - -/* IRQ list */ -#define VEVIF_IRQN(idx, _) DT_INST_IRQ_BY_IDX(0, idx, irq) - -static const uint8_t vevif_irqs[VEVIF_TASKS_NUM] = { - LISTIFY(DT_NUM_IRQS(DT_DRV_INST(0)), VEVIF_IRQN, (,)) -}; - -static void vevif_local_isr(const void *parameter) -{ - uint8_t id = *(uint8_t *)parameter; - - nrf_vpr_csr_vevif_tasks_clear(BIT(id)); - - if (cbs.cb[id] != NULL) { - cbs.cb[id](DEVICE_DT_INST_GET(0), id, cbs.user_data[id], NULL); - } -} - -static inline bool vevif_local_is_task_valid(uint32_t id) -{ - return (id < VEVIF_TASKS_NUM) && ((VEVIF_TASKS_MASK & BIT(id)) != 0U); -} - -static uint32_t vevif_local_max_channels_get(const struct device *dev) -{ - ARG_UNUSED(dev); - - return VEVIF_TASKS_NUM; -} - -static int vevif_local_register_callback(const struct device *dev, uint32_t id, mbox_callback_t cb, - void *user_data) -{ - ARG_UNUSED(dev); - - if (!vevif_local_is_task_valid(id)) { - return -EINVAL; - } - - cbs.cb[id] = cb; - cbs.user_data[id] = user_data; - - return 0; -} - -static int vevif_local_set_enabled(const struct device *dev, uint32_t id, bool enable) -{ - ARG_UNUSED(dev); - - if (!vevif_local_is_task_valid(id)) { - return -EINVAL; - } - - if (enable) { - if ((cbs.enabled_mask & BIT(id)) != 0U) { - return -EALREADY; - } - - cbs.enabled_mask |= BIT(id); - irq_enable(vevif_irqs[id]); - } else { - if ((cbs.enabled_mask & BIT(id)) == 0U) { - return -EALREADY; - } - - cbs.enabled_mask &= ~BIT(id); - irq_disable(vevif_irqs[id]); - } - - return 0; -} - -static const struct mbox_driver_api vevif_local_driver_api = { - .max_channels_get = vevif_local_max_channels_get, - .register_callback = vevif_local_register_callback, - .set_enabled = vevif_local_set_enabled, -}; - -#define VEVIF_IRQ_CONNECT(idx, _) \ - IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, idx, irq), DT_INST_IRQ_BY_IDX(0, idx, priority), \ - vevif_local_isr, &vevif_irqs[idx], 0) - -static int vevif_local_init(const struct device *dev) -{ - nrf_vpr_csr_rtperiph_enable_set(true); - nrf_vpr_csr_vevif_tasks_clear(NRF_VPR_TASK_TRIGGER_ALL_MASK); - - LISTIFY(DT_NUM_IRQS(DT_DRV_INST(0)), VEVIF_IRQ_CONNECT, (;)); - - return 0; -} - -DEVICE_DT_INST_DEFINE(0, vevif_local_init, NULL, NULL, NULL, POST_KERNEL, CONFIG_MBOX_INIT_PRIORITY, - &vevif_local_driver_api); diff --git a/drivers/mbox/mbox_nrf_vevif_remote.c b/drivers/mbox/mbox_nrf_vevif_remote.c deleted file mode 100644 index cb5d7c507c5..00000000000 --- a/drivers/mbox/mbox_nrf_vevif_remote.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT nordic_nrf_vevif_remote - -#include -#include - -#include - -struct mbox_vevif_remote_conf { - NRF_VPR_Type *vpr; - uint32_t tasks_mask; - uint8_t tasks; -}; - -static inline bool vevif_remote_is_task_valid(const struct device *dev, uint32_t id) -{ - const struct mbox_vevif_remote_conf *config = dev->config; - - return (id < config->tasks) && ((config->tasks_mask & BIT(id)) != 0U); -} - -static int vevif_remote_send(const struct device *dev, uint32_t id, const struct mbox_msg *msg) -{ - const struct mbox_vevif_remote_conf *config = dev->config; - - if (!vevif_remote_is_task_valid(dev, id)) { - return -EINVAL; - } - - if (msg != NULL) { - return -ENOTSUP; - } - - nrfy_vpr_task_trigger(config->vpr, nrfy_vpr_trigger_task_get(id)); - - return 0; -} - -static int vevif_remote_mtu_get(const struct device *dev) -{ - ARG_UNUSED(dev); - - return 0; -} - -static uint32_t vevif_remote_max_channels_get(const struct device *dev) -{ - const struct mbox_vevif_remote_conf *config = dev->config; - - return config->tasks; -} - -static const struct mbox_driver_api vevif_remote_driver_api = { - .send = vevif_remote_send, - .mtu_get = vevif_remote_mtu_get, - .max_channels_get = vevif_remote_max_channels_get, -}; - -#define VEVIF_REMOTE_DEFINE(inst) \ - BUILD_ASSERT(DT_INST_PROP(inst, nordic_tasks) <= VPR_TASKS_TRIGGER_MaxCount, \ - "Number of tasks exceeds maximum"); \ - \ - static const struct mbox_vevif_remote_conf conf##inst = { \ - .vpr = (NRF_VPR_Type *)DT_INST_REG_ADDR(inst), \ - .tasks = DT_INST_PROP(inst, nordic_tasks), \ - .tasks_mask = DT_INST_PROP(inst, nordic_tasks_mask), \ - }; \ - \ - DEVICE_DT_INST_DEFINE(inst, NULL, NULL, NULL, &conf##inst, POST_KERNEL, \ - CONFIG_MBOX_INIT_PRIORITY, &vevif_remote_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(VEVIF_REMOTE_DEFINE) From efe0ac52f372d39ff7ad6163db94dc3a19233713 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:42 +0200 Subject: [PATCH 2333/2402] Revert "[nrf fromlist] dts: bindings: mbox: add nordic,nrf-vevif-local|remote" This reverts commit 77878202ae4e676750b2337b60a30d3f69d9c19a. Signed-off-by: Gerard Marull-Paretas --- .../mbox/nordic,nrf-vevif-common.yaml | 18 ----------- dts/bindings/mbox/nordic,nrf-vevif-local.yaml | 32 ------------------- .../mbox/nordic,nrf-vevif-remote.yaml | 29 ----------------- 3 files changed, 79 deletions(-) delete mode 100644 dts/bindings/mbox/nordic,nrf-vevif-common.yaml delete mode 100644 dts/bindings/mbox/nordic,nrf-vevif-local.yaml delete mode 100644 dts/bindings/mbox/nordic,nrf-vevif-remote.yaml diff --git a/dts/bindings/mbox/nordic,nrf-vevif-common.yaml b/dts/bindings/mbox/nordic,nrf-vevif-common.yaml deleted file mode 100644 index b7cb15457f6..00000000000 --- a/dts/bindings/mbox/nordic,nrf-vevif-common.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -include: mailbox-controller.yaml - -properties: - nordic,tasks: - type: int - required: true - description: Number of tasks supported by the VEVIF instance. - - nordic,tasks-mask: - type: int - required: true - description: Mask of tasks supported by the VEVIF instance. - -mbox-cells: - - channel diff --git a/dts/bindings/mbox/nordic,nrf-vevif-local.yaml b/dts/bindings/mbox/nordic,nrf-vevif-local.yaml deleted file mode 100644 index 5d23cfdcf1e..00000000000 --- a/dts/bindings/mbox/nordic,nrf-vevif-local.yaml +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: | - Nordic VEVIF (VPR Event Interface) - Local - - VEVIF is an event interface for VPR, allowing connection to the domain's DPPI - system. VEVIF can also generate IRQs to other CPUs. - - Example definition: - - cpuppr: cpu@d { - ... - cpuppr_vevif_local: mailbox { - compatible = "nordic,nrf-vevif-local"; - interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, - <1 NRF_DEFAULT_IRQ_PRIORITY>, - ... - ; - #mbox-cells = <1>; - nordic,tasks = <16>; - nordic,tasks-mask: <0xfffffff0>; - }; - }; - -compatible: "nordic,nrf-vevif-local" - -include: [base.yaml, "nordic,nrf-vevif-common.yaml"] - -properties: - interrupts: - required: true diff --git a/dts/bindings/mbox/nordic,nrf-vevif-remote.yaml b/dts/bindings/mbox/nordic,nrf-vevif-remote.yaml deleted file mode 100644 index 07522fed99d..00000000000 --- a/dts/bindings/mbox/nordic,nrf-vevif-remote.yaml +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: | - Nordic VEVIF (VPR Event Interface) - Remote - - VEVIF is an event interface for VPR, allowing connection to the domain's DPPI - system. VEVIF can also generate IRQs to other CPUs. - - Example definition: - - cpuppr_vpr: vpr@deadbeef{ - ... - cpuppr_vevif_remote: mailbox@0 { - compatible = "nordic,nrf-vevif-remote"; - reg = <0x0 0x1000>; - #mbox-cells = <1>; - nordic,tasks = <16>; - nordic,tasks-mask: <0xfffffff0>; - }; - }; - -compatible: "nordic,nrf-vevif-remote" - -include: [base.yaml, "nordic,nrf-vevif-common.yaml"] - -properties: - reg: - required: true From f2fb21561939ffebc08b14d3d66ac60bb8714403 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:43 +0200 Subject: [PATCH 2334/2402] Revert "[nrf fromlist] drivers: ieee802154: gracefully handle invalid Ack timestamp" This reverts commit f2de48f36b21d9b1f0f43239c7a08aca950e5523. Signed-off-by: Gerard Marull-Paretas --- drivers/ieee802154/ieee802154_nrf5.c | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/drivers/ieee802154/ieee802154_nrf5.c b/drivers/ieee802154/ieee802154_nrf5.c index ecc758455d7..39891c635c9 100644 --- a/drivers/ieee802154/ieee802154_nrf5.c +++ b/drivers/ieee802154/ieee802154_nrf5.c @@ -387,17 +387,6 @@ static int handle_ack(struct nrf5_802154_data *nrf5_radio) struct net_pkt *ack_pkt; int err = 0; -#if defined(CONFIG_NET_PKT_TIMESTAMP) - if (nrf5_radio->ack_frame.time == NRF_802154_NO_TIMESTAMP) { - /* Ack timestamp is invalid and cannot be used by the upper layer. - * Report the transmission as failed as if the Ack was not received at all. - */ - LOG_WRN("Invalid ACK timestamp."); - err = -ENOMSG; - goto free_nrf_ack; - } -#endif - if (IS_ENABLED(CONFIG_IEEE802154_NRF5_FCS_IN_LENGTH)) { ack_len = nrf5_radio->ack_frame.psdu[0]; } else { @@ -1141,14 +1130,8 @@ void nrf_802154_transmitted_raw(uint8_t *frame, nrf5_data.ack_frame.lqi = metadata->data.transmitted.lqi; #if defined(CONFIG_NET_PKT_TIMESTAMP) - if (metadata->data.transmitted.time == NRF_802154_NO_TIMESTAMP) { - /* Ack timestamp is invalid. Keep this value to detect it when handling Ack - */ - nrf5_data.ack_frame.time = NRF_802154_NO_TIMESTAMP; - } else { - nrf5_data.ack_frame.time = nrf_802154_timestamp_end_to_phr_convert( - metadata->data.transmitted.time, nrf5_data.ack_frame.psdu[0]); - } + nrf5_data.ack_frame.time = nrf_802154_timestamp_end_to_phr_convert( + metadata->data.transmitted.time, nrf5_data.ack_frame.psdu[0]); #endif } From 0b8d69941eb55fd085e1e45bab519e7159a05132 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:43 +0200 Subject: [PATCH 2335/2402] Revert "[nrf fromlist] samples: net: cellular_modem: add nRF9160 DK's nRF52840" This reverts commit 3a97de47ca5cde5dba3a6584add1aa6b60d3ac5a. Signed-off-by: Gerard Marull-Paretas --- .../boards/nrf9160dk_nrf52840.conf | 13 ------------- .../boards/nrf9160dk_nrf52840.overlay | 18 ------------------ 2 files changed, 31 deletions(-) delete mode 100644 samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf delete mode 100644 samples/net/cellular_modem/boards/nrf9160dk_nrf52840.overlay diff --git a/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf b/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf deleted file mode 100644 index 2af3b6d2a41..00000000000 --- a/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_UART_ASYNC_API=y - -# Align with the Serial LTE Modem (SLM) application. -CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE=1500 -CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES=1500 - -# Allow large UART TXs to go through @115200. -CONFIG_MODEM_BACKEND_UART_ASYNC_TRANSMIT_TIMEOUT_MS=200 - -# Print logs and printk() output on uart0. -CONFIG_LOG=y -CONFIG_LOG_BACKEND_UART=y -CONFIG_MODEM_LOG_LEVEL_DBG=y diff --git a/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.overlay b/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.overlay deleted file mode 100644 index c639ec8b305..00000000000 --- a/samples/net/cellular_modem/boards/nrf9160dk_nrf52840.overlay +++ /dev/null @@ -1,18 +0,0 @@ -#include - -/ { - aliases { - modem = &modem; - }; -}; - -&uart1 { - current-speed = <115200>; - hw-flow-control; - - modem: modem { - compatible = "nordic,nrf91-slm"; - status = "okay"; - mdm-power-gpios = <&interface_to_nrf9160 4 GPIO_ACTIVE_LOW>; - }; -}; From 060b09c49ba9869cab77f9f48851019cb773d61d Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:43 +0200 Subject: [PATCH 2336/2402] Revert "[nrf fromlist] samples: net: cellular_modem: small fixes/improvements" This reverts commit bd0953fe392f6e5f787ce92f85ada2ded6207eab. Signed-off-by: Gerard Marull-Paretas --- samples/net/cellular_modem/prj.conf | 4 --- samples/net/cellular_modem/src/main.c | 39 +++++++++++++-------------- 2 files changed, 19 insertions(+), 24 deletions(-) diff --git a/samples/net/cellular_modem/prj.conf b/samples/net/cellular_modem/prj.conf index ab44ca9528e..52d0ca26bde 100644 --- a/samples/net/cellular_modem/prj.conf +++ b/samples/net/cellular_modem/prj.conf @@ -22,7 +22,3 @@ CONFIG_NET_CONNECTION_MANAGER=y CONFIG_MODEM=y CONFIG_PM_DEVICE=y CONFIG_MODEM_CELLULAR=y - -# Logging -CONFIG_MODEM_MODULES_LOG_LEVEL_DBG=y -#CONFIG_MODEM_CMUX_LOG_LEVEL_DBG=y diff --git a/samples/net/cellular_modem/src/main.c b/samples/net/cellular_modem/src/main.c index b7e738d13e5..6ab5ddc297d 100644 --- a/samples/net/cellular_modem/src/main.c +++ b/samples/net/cellular_modem/src/main.c @@ -160,7 +160,7 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t continue; } - printk("Receiving echoed packet\n"); + printk("Receiving echoed packet"); ret = zsock_recv(socket_fd, sample_recv_buffer, sizeof(sample_recv_buffer), 0); if (ret != sizeof(sample_test_packet)) { printk("Echoed sample test packet has incorrect size\n"); @@ -181,10 +181,10 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t printk("Echo transmit time %ums\n", echo_received_ms - send_start_ms); } - printk("Successfully sent and received %u of %u packets\n", packets_sent, + printk("Successfully sent %u packets of %u packets\n", packets_sent, SAMPLE_TEST_ECHO_PACKETS); - printk("Average time per successful echo: %u ms\n", + printk("Average time per echo: %u ms\n", accumulated_ms / packets_sent); printk("Close UDP socket\n"); @@ -265,7 +265,10 @@ int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint int main(void) { struct net_if *const iface = net_if_get_first_by_type(&NET_L2_GET_NAME(PPP)); + uint32_t raised_event; uint16_t *port; + const void *info; + size_t info_len; int ret; init_sample_test_packet(); @@ -281,8 +284,9 @@ int main(void) } printk("Waiting for L4 connected\n"); - ret = net_mgmt_event_wait_on_iface(iface, NET_EVENT_L4_CONNECTED, NULL, NULL, NULL, - K_SECONDS(120)); + ret = net_mgmt_event_wait_on_iface(iface, + NET_EVENT_L4_CONNECTED, &raised_event, &info, + &info_len, K_SECONDS(120)); if (ret != 0) { printk("L4 was not connected in time\n"); @@ -290,12 +294,9 @@ int main(void) } printk("Waiting for DNS server added\n"); - ret = net_mgmt_event_wait_on_iface(iface, NET_EVENT_DNS_SERVER_ADD, NULL, NULL, NULL, - K_SECONDS(10)); - if (ret) { - printk("DNS server was not added in time\n"); - return -1; - } + ret = net_mgmt_event_wait_on_iface(iface, + NET_EVENT_DNS_SERVER_ADD, &raised_event, &info, + &info_len, K_SECONDS(10)); printk("Retrieving cellular info\n"); print_cellular_info(); @@ -332,7 +333,7 @@ int main(void) sample_test_dns_addrinfo.ai_addrlen, port); if (ret < 0) { - printk("Failed to send echos\n"); + printk("Failed to send echo\n"); return -1; } @@ -354,26 +355,24 @@ int main(void) pm_device_action_run(modem, PM_DEVICE_ACTION_RESUME); printk("Waiting for L4 connected\n"); - ret = net_mgmt_event_wait_on_iface(iface, NET_EVENT_L4_CONNECTED, NULL, NULL, NULL, - K_SECONDS(60)); + ret = net_mgmt_event_wait_on_iface(net_if_get_default(), + NET_EVENT_L4_CONNECTED, &raised_event, &info, + &info_len, K_SECONDS(60)); + if (ret != 0) { printk("L4 was not connected in time\n"); return -1; } - printk("L4 connected\n"); - - /* Wait a bit to avoid (unsuccessfully) trying to send the first echo packet too quickly. */ - k_sleep(K_SECONDS(1)); ret = sample_echo_packet(&sample_test_dns_addrinfo.ai_addr, sample_test_dns_addrinfo.ai_addrlen, port); if (ret < 0) { - printk("Failed to send echos after restart\n"); + printk("Failed to send echo after restart\n"); return -1; } - ret = net_if_down(iface); + ret = net_if_down(net_if_get_default()); if (ret < 0) { printk("Failed to bring down network interface\n"); return -1; From 0f03c0a0df9351d089cd5e2a687e06464519d088 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:43 +0200 Subject: [PATCH 2337/2402] Revert "[nrf fromlist] modem: backends: uart_async: log the number of bytes dropped" This reverts commit 53f95da47e946c118367fd3724d9b6410cfe9ea3. Signed-off-by: Gerard Marull-Paretas --- subsys/modem/backends/modem_backend_uart_async.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/subsys/modem/backends/modem_backend_uart_async.c b/subsys/modem/backends/modem_backend_uart_async.c index 0fa3684780e..29107198c2f 100644 --- a/subsys/modem/backends/modem_backend_uart_async.c +++ b/subsys/modem/backends/modem_backend_uart_async.c @@ -114,8 +114,7 @@ static void modem_backend_uart_async_event_handler(const struct device *dev, if (received < evt->data.rx.len) { ring_buf_reset(&backend->async.receive_rb); k_spin_unlock(&backend->async.receive_rb_lock, key); - LOG_WRN("Receive buffer overrun (%u/%u dropped)", - evt->data.rx.len - received, evt->data.rx.len); + LOG_WRN("Receive buffer overrun"); break; } From 9a509bba2a413a7eb499bfa846c058d31688b8fd Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:43 +0200 Subject: [PATCH 2338/2402] Revert "[nrf fromlist] Bluetooth: Controller: Remove experimental from LE Set Host Feature" This reverts commit 1ead4c257b3b67b92e0e3f39eb2c763673cc666a. Signed-off-by: Gerard Marull-Paretas --- subsys/bluetooth/controller/Kconfig | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/subsys/bluetooth/controller/Kconfig b/subsys/bluetooth/controller/Kconfig index a7b2c1a74f1..bff6c17bca6 100644 --- a/subsys/bluetooth/controller/Kconfig +++ b/subsys/bluetooth/controller/Kconfig @@ -853,14 +853,11 @@ config BT_CTLR_SYNC_ISO_PDU_LEN_MAX endif # BT_CTLR_ADV_EXT config BT_CTLR_SET_HOST_FEATURE - bool "LE Set Host Feature Command" if !BT_LL_SW_SPLIT + bool "LE Set Host Feature Command [EXPERIMENTAL]" + select EXPERIMENTAL help Enables optional LE Set Host Feature Command -config BT_CTLR_SET_HOST_FEATURE - bool "LE Set Host Feature Command (Split Link Layer) [EXPERIMENTAL]" if BT_LL_SW_SPLIT - select EXPERIMENTAL if BT_LL_SW_SPLIT - config BT_CTLR_CENTRAL_ISO bool "LE Connected Isochronous Stream Central" if !BT_LL_SW_SPLIT depends on BT_CTLR_CENTRAL_ISO_SUPPORT && BT_CENTRAL From d4af7ad3e39688d695bc07900e3be1579672d180 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 30 Apr 2024 11:04:44 +0200 Subject: [PATCH 2339/2402] Revert "[nrf fromlist] samples: net: cellular_modem: small improvements" This reverts commit 509dcb2757b9ec83cddba8a7f166fb11dcef3208. Signed-off-by: Gerard Marull-Paretas --- samples/net/cellular_modem/README.rst | 2 +- samples/net/cellular_modem/src/main.c | 63 +++++++++++---------------- 2 files changed, 26 insertions(+), 39 deletions(-) diff --git a/samples/net/cellular_modem/README.rst b/samples/net/cellular_modem/README.rst index b845b2e37d8..384d8b3bef5 100644 --- a/samples/net/cellular_modem/README.rst +++ b/samples/net/cellular_modem/README.rst @@ -18,7 +18,7 @@ Notes This sample uses the devicetree alias modem to identify the modem instance to use. The sample also presumes that -the modem driver creates the only PPP network interface. +the modem driver creates the only network interface. Setup ***** diff --git a/samples/net/cellular_modem/src/main.c b/samples/net/cellular_modem/src/main.c index 6ab5ddc297d..35a97d3e831 100644 --- a/samples/net/cellular_modem/src/main.c +++ b/samples/net/cellular_modem/src/main.c @@ -127,7 +127,7 @@ static int sample_dns_request(void) return 0; } -int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t *port) +int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen) { int ret; int socket_fd; @@ -140,16 +140,22 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t socket_fd = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); if (socket_fd < 0) { - printk("Failed to open socket (%d)\n", errno); + printk("Failed to open socket\n"); return -1; } printk("Socket opened\n"); - *port = htons(SAMPLE_TEST_ENDPOINT_UDP_ECHO_PORT); + if (ai_addr->sa_family == AF_INET) { + net_sin(ai_addr)->sin_port = htons(SAMPLE_TEST_ENDPOINT_UDP_ECHO_PORT); + } else if (ai_addr->sa_family == AF_INET6) { + net_sin6(ai_addr)->sin6_port = htons(SAMPLE_TEST_ENDPOINT_UDP_ECHO_PORT); + } else { + printk("Unsupported address family\n"); + return -1; + } for (uint32_t i = 0; i < SAMPLE_TEST_ECHO_PACKETS; i++) { - printk("Sending echo packet\n"); send_start_ms = k_uptime_get_32(); ret = zsock_sendto(socket_fd, sample_test_packet, sizeof(sample_test_packet), 0, @@ -160,7 +166,6 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t continue; } - printk("Receiving echoed packet"); ret = zsock_recv(socket_fd, sample_recv_buffer, sizeof(sample_recv_buffer), 0); if (ret != sizeof(sample_test_packet)) { printk("Echoed sample test packet has incorrect size\n"); @@ -199,7 +204,7 @@ int sample_echo_packet(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t } -int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint16_t *port) +int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen) { int ret; int socket_fd; @@ -219,7 +224,14 @@ int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint printk("Socket opened\n"); - *port = htons(SAMPLE_TEST_ENDPOINT_UDP_RECEIVE_PORT); + if (ai_addr->sa_family == AF_INET) { + net_sin(ai_addr)->sin_port = htons(SAMPLE_TEST_ENDPOINT_UDP_RECEIVE_PORT); + } else if (ai_addr->sa_family == AF_INET6) { + net_sin6(ai_addr)->sin6_port = htons(SAMPLE_TEST_ENDPOINT_UDP_RECEIVE_PORT); + } else { + printk("Unsupported address family\n"); + return -1; + } printk("Sending %u packets\n", SAMPLE_TEST_TRANSMIT_PACKETS); send_start_ms = k_uptime_get_32(); @@ -264,9 +276,7 @@ int sample_transmit_packets(struct sockaddr *ai_addr, socklen_t ai_addrlen, uint int main(void) { - struct net_if *const iface = net_if_get_first_by_type(&NET_L2_GET_NAME(PPP)); uint32_t raised_event; - uint16_t *port; const void *info; size_t info_len; int ret; @@ -277,14 +287,14 @@ int main(void) pm_device_action_run(modem, PM_DEVICE_ACTION_RESUME); printk("Bring up network interface\n"); - ret = net_if_up(iface); + ret = net_if_up(net_if_get_default()); if (ret < 0) { printk("Failed to bring up network interface\n"); return -1; } printk("Waiting for L4 connected\n"); - ret = net_mgmt_event_wait_on_iface(iface, + ret = net_mgmt_event_wait_on_iface(net_if_get_default(), NET_EVENT_L4_CONNECTED, &raised_event, &info, &info_len, K_SECONDS(120)); @@ -294,7 +304,7 @@ int main(void) } printk("Waiting for DNS server added\n"); - ret = net_mgmt_event_wait_on_iface(iface, + ret = net_mgmt_event_wait_on_iface(net_if_get_default(), NET_EVENT_DNS_SERVER_ADD, &raised_event, &info, &info_len, K_SECONDS(10)); @@ -308,29 +318,8 @@ int main(void) return -1; } - { - char ip_str[INET6_ADDRSTRLEN]; - const void *src; - - switch (sample_test_dns_addrinfo.ai_addr.sa_family) { - case AF_INET: - src = &net_sin(&sample_test_dns_addrinfo.ai_addr)->sin_addr; - port = &net_sin(&sample_test_dns_addrinfo.ai_addr)->sin_port; - break; - case AF_INET6: - src = &net_sin6(&sample_test_dns_addrinfo.ai_addr)->sin6_addr; - port = &net_sin6(&sample_test_dns_addrinfo.ai_addr)->sin6_port; - break; - default: - printk("Unsupported address family\n"); - return -1; - } - inet_ntop(sample_test_dns_addrinfo.ai_addr.sa_family, src, ip_str, sizeof(ip_str)); - printk("Resolved to %s\n", ip_str); - } - ret = sample_echo_packet(&sample_test_dns_addrinfo.ai_addr, - sample_test_dns_addrinfo.ai_addrlen, port); + sample_test_dns_addrinfo.ai_addrlen); if (ret < 0) { printk("Failed to send echo\n"); @@ -338,7 +327,7 @@ int main(void) } ret = sample_transmit_packets(&sample_test_dns_addrinfo.ai_addr, - sample_test_dns_addrinfo.ai_addrlen, port); + sample_test_dns_addrinfo.ai_addrlen); if (ret < 0) { printk("Failed to send packets\n"); @@ -353,8 +342,6 @@ int main(void) } pm_device_action_run(modem, PM_DEVICE_ACTION_RESUME); - - printk("Waiting for L4 connected\n"); ret = net_mgmt_event_wait_on_iface(net_if_get_default(), NET_EVENT_L4_CONNECTED, &raised_event, &info, &info_len, K_SECONDS(60)); @@ -365,7 +352,7 @@ int main(void) } ret = sample_echo_packet(&sample_test_dns_addrinfo.ai_addr, - sample_test_dns_addrinfo.ai_addrlen, port); + sample_test_dns_addrinfo.ai_addrlen); if (ret < 0) { printk("Failed to send echo after restart\n"); From cce72196f80c7a5e37cc6c3d9059e35153f08abc Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 15 Apr 2024 11:02:41 +0300 Subject: [PATCH 2340/2402] [nrf fromlist] samples: net: Disable native_posix target in more samples MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The native_posix compilations fail with various socket errors like this: samples/net/sockets/can/src/main.c:65:9: error: implicit \ declaration of function ‘send’ [-Werror=implicit-function-declaration] 65 | ret = send(fd, &sframe, sizeof(sframe), 0); | ^~~~ So disable the native_posix board from networking samples as native_posix board is not compatible with CONFIG_POSIX_API This is related to commit b8fc1c4c3e ("samples: net: Disable native_posix target in samples") but disables more network samples for native_posix board. Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71485 Signed-off-by: Jukka Rissanen (cherry picked from commit 883bc85a5493d8fe06eee7b8e2224309f7b95b53) --- samples/net/sockets/can/sample.yaml | 4 ++++ samples/net/sockets/dumb_http_server_mt/sample.yaml | 4 ++++ samples/net/sockets/http_client/sample.yaml | 4 ++++ samples/net/sockets/packet/sample.yaml | 2 -- samples/net/sockets/txtime/sample.yaml | 2 -- samples/net/sockets/websocket_client/sample.yaml | 4 ++++ 6 files changed, 16 insertions(+), 4 deletions(-) diff --git a/samples/net/sockets/can/sample.yaml b/samples/net/sockets/can/sample.yaml index 4e1d9d1c9fa..a9dff7079d3 100644 --- a/samples/net/sockets/can/sample.yaml +++ b/samples/net/sockets/can/sample.yaml @@ -8,6 +8,10 @@ common: filter: dt_chosen_enabled("zephyr,canbus") and not dt_compat_enabled("kvaser,pcican") depends_on: can harness: console + # native_posix does not work with CONFIG_POSIX_API + platform_exclude: + - native_posix + - native_posix/native/64 tests: sample.net.sockets.can.one_socket: extra_configs: diff --git a/samples/net/sockets/dumb_http_server_mt/sample.yaml b/samples/net/sockets/dumb_http_server_mt/sample.yaml index fa69fea8c97..dc0c8182246 100644 --- a/samples/net/sockets/dumb_http_server_mt/sample.yaml +++ b/samples/net/sockets/dumb_http_server_mt/sample.yaml @@ -9,6 +9,10 @@ common: - net - socket - http + # native_posix does not work with CONFIG_POSIX_API + platform_exclude: + - native_posix + - native_posix/native/64 tests: sample.net.sockets.dumb_http_server_mt: extra_configs: diff --git a/samples/net/sockets/http_client/sample.yaml b/samples/net/sockets/http_client/sample.yaml index 271f61b94ec..afd14a1a255 100644 --- a/samples/net/sockets/http_client/sample.yaml +++ b/samples/net/sockets/http_client/sample.yaml @@ -5,6 +5,10 @@ common: - http_client min_ram: 32 depends_on: netif + # native_posix does not work with CONFIG_POSIX_API + platform_exclude: + - native_posix + - native_posix/native/64 sample: description: HTTP client sample name: http_client diff --git a/samples/net/sockets/packet/sample.yaml b/samples/net/sockets/packet/sample.yaml index dc816ac52e8..723978b5de8 100644 --- a/samples/net/sockets/packet/sample.yaml +++ b/samples/net/sockets/packet/sample.yaml @@ -5,8 +5,6 @@ tests: sample.net.sockets.packet: harness: net platform_allow: - - native_posix - - native_posix/native/64 - native_sim - native_sim/native/64 integration_platforms: diff --git a/samples/net/sockets/txtime/sample.yaml b/samples/net/sockets/txtime/sample.yaml index feb099bd63b..18613f4b87a 100644 --- a/samples/net/sockets/txtime/sample.yaml +++ b/samples/net/sockets/txtime/sample.yaml @@ -3,8 +3,6 @@ common: depends_on: netif # We can only run this in platforms that support PTP clock and TXTIME platform_allow: - - native_posix - - native_posix/native/64 - native_sim - native_sim/native/64 - qemu_x86 diff --git a/samples/net/sockets/websocket_client/sample.yaml b/samples/net/sockets/websocket_client/sample.yaml index a0472b856f9..df7603cf1a1 100644 --- a/samples/net/sockets/websocket_client/sample.yaml +++ b/samples/net/sockets/websocket_client/sample.yaml @@ -7,6 +7,10 @@ common: - websocket min_ram: 35 depends_on: netif + # native_posix does not work with CONFIG_POSIX_API + platform_exclude: + - native_posix + - native_posix/native/64 sample: description: Websocket client sample name: websocket_client From 1552882744a9ce10e528f2c4a60bdf5de48e2352 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 15 Apr 2024 15:54:58 +0200 Subject: [PATCH 2341/2402] [nrf fromlist] samples: net: tftp_client: do not allow native_posix Because CONFIG_POSIX_API (required) cannot be selected on that platform, resulting in build failures. Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71516 Signed-off-by: Gerard Marull-Paretas (cherry picked from commit e4d137eadddbd87b879380c19b8f2f7d852165b4) --- samples/net/tftp_client/sample.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/samples/net/tftp_client/sample.yaml b/samples/net/tftp_client/sample.yaml index 3ccedecafe9..6e53b0f1881 100644 --- a/samples/net/tftp_client/sample.yaml +++ b/samples/net/tftp_client/sample.yaml @@ -6,7 +6,6 @@ tests: harness: net depends_on: netif platform_allow: - - native_posix - native_sim integration_platforms: - native_sim From ffbf62c7753b85cb9e274bef5fef441c871d7f4c Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Mon, 15 Apr 2024 14:59:19 +0100 Subject: [PATCH 2342/2402] [nrf fromlist] boards: Fix doc build warnings Fixes warnings when building documentation due to additional SoC names being part of the Kconfig symbols which they should not be Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71517 Signed-off-by: Jamie McCrae (cherry picked from commit eeec8c22a1b16bb40cb31a2b6b58696972a3aded) --- boards/bcdevices/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 | 2 +- boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb | 2 +- boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk | 4 ++-- boards/nxp/imx93_evk/Kconfig.imx93_evk | 4 ++-- boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 | 4 ++-- boards/rak/rak5010/Kconfig.rak5010 | 2 +- boards/starfive/visionfive2/Kconfig.visionfive2 | 2 +- boards/ti/sk_am62/Kconfig.sk_am62 | 6 ++---- boards/we/proteus2ev/Kconfig.we_proteus2ev | 2 +- 9 files changed, 13 insertions(+), 15 deletions(-) diff --git a/boards/bcdevices/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 b/boards/bcdevices/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 index 2b69264a29c..1abf2e23fd8 100644 --- a/boards/bcdevices/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 +++ b/boards/bcdevices/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 @@ -3,5 +3,5 @@ # Copyright (c) 2021 Blue Clover # SPDX-License-Identifier: Apache-2.0 -config BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 +config BOARD_BLUECLOVER_PLT_DEMO_V2 select SOC_NRF52832_QFAA diff --git a/boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb b/boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb index 8a04ffd502d..60fa87104fc 100644 --- a/boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb +++ b/boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb @@ -3,5 +3,5 @@ # Copyright (c) 2021 Michal Morsisko # SPDX-License-Identifier: Apache-2.0 -config BOARD_EBYTE_E73_TBB_NRF52832 +config BOARD_EBYTE_E73_TBB select SOC_NRF52832_QFAA diff --git a/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk b/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk index 4ec5b6ee62d..12f6e2efd48 100644 --- a/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk +++ b/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk @@ -1,5 +1,5 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -config BOARD_NRF54L15PDK_NRF54L15_CPUAPP - select SOC_NRF54L15_ENGA_CPUAPP +config BOARD_NRF54L15PDK + select SOC_NRF54L15_ENGA_CPUAPP if BOARD_NRF54L15PDK_NRF54L15_CPUAPP diff --git a/boards/nxp/imx93_evk/Kconfig.imx93_evk b/boards/nxp/imx93_evk/Kconfig.imx93_evk index e3121418393..0115518a6d2 100644 --- a/boards/nxp/imx93_evk/Kconfig.imx93_evk +++ b/boards/nxp/imx93_evk/Kconfig.imx93_evk @@ -1,6 +1,6 @@ # Copyright 2022,2024 NXP # SPDX-License-Identifier: Apache-2.0 -config BOARD_IMX93_EVK_MIMX9352_A55 - select SOC_MIMX9352_A55 +config BOARD_IMX93_EVK + select SOC_MIMX9352_A55 if BOARD_IMX93_EVK_MIMX9352_A55 select SOC_PART_NUMBER_MIMX9352CVUXK diff --git a/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 b/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 index cfd9ba449db..081124dd1a8 100644 --- a/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 +++ b/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 @@ -1,6 +1,6 @@ # Copyright 2023 NXP # SPDX-License-Identifier: Apache-2.0 -config BOARD_VMU_RT1170_MIMXRT1176_CM7 - select SOC_MIMXRT1176_CM7 +config BOARD_VMU_RT1170 + select SOC_MIMXRT1176_CM7 if BOARD_VMU_RT1170_MIMXRT1176_CM7 select SOC_PART_NUMBER_MIMXRT1176DVMAA diff --git a/boards/rak/rak5010/Kconfig.rak5010 b/boards/rak/rak5010/Kconfig.rak5010 index ced2b62b39c..4c5db16669d 100644 --- a/boards/rak/rak5010/Kconfig.rak5010 +++ b/boards/rak/rak5010/Kconfig.rak5010 @@ -3,5 +3,5 @@ # Copyright (c) 2020 Guillaume Paquet # SPDX-License-Identifier: Apache-2.0 -config BOARD_RAK5010_NRF52840 +config BOARD_RAK5010 select SOC_NRF52840_QIAA diff --git a/boards/starfive/visionfive2/Kconfig.visionfive2 b/boards/starfive/visionfive2/Kconfig.visionfive2 index e451964f979..d2988440b2d 100644 --- a/boards/starfive/visionfive2/Kconfig.visionfive2 +++ b/boards/starfive/visionfive2/Kconfig.visionfive2 @@ -1,5 +1,5 @@ # Copyright (c) 2024 Kanak Shilledar # SPDX-License-Identifier: Apache-2.0 -config BOARD_VISIONFIVE2_JH7110 +config BOARD_VISIONFIVE2 select SOC_JH7110 diff --git a/boards/ti/sk_am62/Kconfig.sk_am62 b/boards/ti/sk_am62/Kconfig.sk_am62 index d7e83cba87a..fab6d884508 100644 --- a/boards/ti/sk_am62/Kconfig.sk_am62 +++ b/boards/ti/sk_am62/Kconfig.sk_am62 @@ -5,7 +5,5 @@ # # SPDX-License-Identifier: Apache-2.0 -config BOARD_SK_AM62_AM6234_M4 - select SOC_AM6234_M4 - help - TI AM62x M4 Starter Kit (SK) Evaluation Module (EVM) +config BOARD_SK_AM62 + select SOC_AM6234_M4 if BOARD_SK_AM62_AM6234_M4 diff --git a/boards/we/proteus2ev/Kconfig.we_proteus2ev b/boards/we/proteus2ev/Kconfig.we_proteus2ev index 60aa73fb142..b18f4c4f9bb 100644 --- a/boards/we/proteus2ev/Kconfig.we_proteus2ev +++ b/boards/we/proteus2ev/Kconfig.we_proteus2ev @@ -1,5 +1,5 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -config BOARD_WE_PROTEUS2EV_NRF52832 +config BOARD_WE_PROTEUS2EV select SOC_NRF52832_CIAA From 24663df1abb2af207fdfba31e025229350231b31 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Mon, 15 Apr 2024 14:12:11 +0200 Subject: [PATCH 2343/2402] [nrf fromlist] scripts: support soc/boards in Zephyr modules Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71519 Extend check_compliance with support for soc and boards defined Zephyr modules. Signed-off-by: Torsten Rasmussen --- scripts/ci/check_compliance.py | 45 +++++++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index 95c7e26a5ea..ba44e084e6d 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -379,7 +379,7 @@ def get_modules(self, modules_file, settings_file): )) fp_module_file.write(content) - def get_kconfig_dts(self, kconfig_dts_file, settings_file): + def get_module_setting_root(self, root, settings_file): """ Generate the Kconfig.dts using dts/bindings as the source. @@ -388,10 +388,7 @@ def get_kconfig_dts(self, kconfig_dts_file, settings_file): """ # Invoke the script directly using the Python executable since this is # not a module nor a pip-installed Python utility - zephyr_drv_kconfig_path = os.path.join(ZEPHYR_BASE, "scripts", "dts", - "gen_driver_kconfig_dts.py") - binding_paths = [] - binding_paths.append(os.path.join(ZEPHYR_BASE, "dts", "bindings")) + root_paths = [] if os.path.exists(settings_file): with open(settings_file, 'r') as fp_setting_file: @@ -399,9 +396,29 @@ def get_kconfig_dts(self, kconfig_dts_file, settings_file): lines = content.strip().split('\n') for line in lines: - if line.startswith('"DTS_ROOT":'): - _, dts_root_path = line.split(":", 1) - binding_paths.append(os.path.join(dts_root_path.strip('"'), "dts", "bindings")) + root = root.upper() + if line.startswith(f'"{root}_ROOT":'): + _, root_path = line.split(":", 1) + root_paths.append(Path(root_path.strip('"'))) + return root_paths + + def get_kconfig_dts(self, kconfig_dts_file, settings_file): + """ + Generate the Kconfig.dts using dts/bindings as the source. + + This is needed to complete Kconfig compliance tests. + + """ + # Invoke the script directly using the Python executable since this is + # not a module nor a pip-installed Python utility + zephyr_drv_kconfig_path = os.path.join(ZEPHYR_BASE, "scripts", "dts", + "gen_driver_kconfig_dts.py") + binding_paths = [] + binding_paths.append(os.path.join(ZEPHYR_BASE, "dts", "bindings")) + + dts_root_paths = self.get_module_setting_root('dts', settings_file) + for p in dts_root_paths: + binding_paths.append(p / "dts" / "bindings") cmd = [sys.executable, zephyr_drv_kconfig_path, '--kconfig-out', kconfig_dts_file, '--bindings-dirs'] @@ -439,7 +456,7 @@ def get_v1_model_syms(self, kconfig_v1_file, kconfig_v1_syms_file): fp_kconfig_v1_syms_file.write('\n\t' + kconfiglib.TYPE_TO_STR[s.type]) fp_kconfig_v1_syms_file.write('\n\n') - def get_v2_model(self, kconfig_dir): + def get_v2_model(self, kconfig_dir, settings_file): """ Get lists of v2 boards and SoCs and put them in a file that is parsed by Kconfig @@ -451,8 +468,12 @@ def get_v2_model(self, kconfig_dir): kconfig_boards_file = os.path.join(kconfig_dir, 'boards', 'Kconfig.boards') kconfig_defconfig_file = os.path.join(kconfig_dir, 'boards', 'Kconfig.defconfig') - root_args = argparse.Namespace(**{'board_roots': [Path(ZEPHYR_BASE)], - 'soc_roots': [Path(ZEPHYR_BASE)], 'board': None}) + board_roots = self.get_module_setting_root('board', settings_file) + board_roots.insert(0, Path(ZEPHYR_BASE)) + soc_roots = self.get_module_setting_root('soc', settings_file) + soc_roots.insert(0, Path(ZEPHYR_BASE)) + root_args = argparse.Namespace(**{'board_roots': board_roots, + 'soc_roots': soc_roots, 'board': None}) v2_boards = list_boards.find_v2_boards(root_args) with open(kconfig_defconfig_file, 'w') as fp: @@ -558,7 +579,7 @@ def parse_kconfig(self, filename="Kconfig", hwm=None): os.makedirs(os.path.join(kconfiglib_dir, 'arch'), exist_ok=True) os.environ["BOARD_DIR"] = kconfiglib_boards_dir - self.get_v2_model(kconfiglib_dir) + self.get_v2_model(kconfiglib_dir, os.path.join(kconfiglib_dir, "settings_file.txt")) # Tells Kconfiglib to generate warnings for all references to undefined # symbols within Kconfig files From 1758a3204dd9627f78974cd0815a6df2c9519974 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Mon, 15 Apr 2024 09:23:00 +0100 Subject: [PATCH 2344/2402] [nrf fromtree] cmake: modules: boards: Add normalised variables Adds a new variable NORMALIZED_BOARD_QUALIFIERS which contains the board qualifiers in file-name format, this allows for constructing strings in applications (e.g. for folder names) prior to Zephyr being found for things like APPLICATION_CONFIG_DIR. Also adds NORMALIZED_BOARD_TARGET. Signed-off-by: Jamie McCrae (cherry picked from commit a2ed8162c8c42a4301264709e9e476ef9eaa0552) --- cmake/modules/boards.cmake | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index cb07262f150..b1e2b21abce 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -21,13 +21,18 @@ # Outcome: # The following variables will be defined when this CMake module completes: # -# - BOARD: Board, without revision field. -# - BOARD_REVISION: Board revision -# - BOARD_DIR: Board directory with the implementation for selected board -# - ARCH_DIR: Arch dir for extracted from selected board -# - BOARD_ROOT: BOARD_ROOT with ZEPHYR_BASE appended -# - BOARD_EXTENSION_DIRS: List of board extension directories (If -# BOARD_EXTENSIONS is not explicitly disabled) +# - BOARD: Board, without revision field. +# - BOARD_REVISION: Board revision +# - BOARD_QUALIFIERS: Board qualifiers +# - NORMALIZED_BOARD_QUALIFIERS: Board qualifiers in lower-case format where slashes have been +# replaced with underscores +# - NORMALIZED_BOARD_TARGET: Board target in lower-case format where slashes have been +# replaced with underscores +# - BOARD_DIR: Board directory with the implementation for selected board +# - ARCH_DIR: Arch dir for extracted from selected board +# - BOARD_ROOT: BOARD_ROOT with ZEPHYR_BASE appended +# - BOARD_EXTENSION_DIRS: List of board extension directories (If +# BOARD_EXTENSIONS is not explicitly disabled) # # The following targets will be defined when this CMake module completes: # - board: when invoked, a list of valid boards will be printed @@ -336,8 +341,13 @@ endif() if(DEFINED BOARD_QUALIFIERS) string(REGEX REPLACE "^/" "qualifiers: " board_message_qualifiers "${BOARD_QUALIFIERS}") set(board_message "${board_message}, ${board_message_qualifiers}") + + string(REPLACE "/" "_" NORMALIZED_BOARD_QUALIFIERS "${BOARD_QUALIFIERS}") endif() +set(NORMALIZED_BOARD_TARGET "${BOARD}${BOARD_QUALIFIERS}") +string(REPLACE "/" "_" NORMALIZED_BOARD_TARGET "${NORMALIZED_BOARD_TARGET}") + message(STATUS "${board_message}") add_custom_target(boards ${list_boards_commands} USES_TERMINAL) From 4fa036ea4d3d2990f652f701b2c3877195e7ef7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Ciupis?= Date: Wed, 10 Apr 2024 11:37:21 +0200 Subject: [PATCH 2345/2402] [nrf fromtree] soc: nordic: nrf53: network CPU Force-OFF management MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit introduces a common API for managing nRF53 SoC network CPU Force-OFF state. From the application CPU point of view, the network CPU is a shared resource used by multiple users. The current solution where every user controls the network core state directly leads to dependencies between users and does not scale well. To address this problem there should be a single entity responsible for controlling the network CPU Force-OFF signal. This commit introduces such module. Signed-off-by: Jędrzej Ciupis (cherry picked from commit ec3c3f153b0c1d074c9739d416ee1d40c80481d9) --- soc/nordic/nrf53/CMakeLists.txt | 1 + soc/nordic/nrf53/Kconfig | 7 +++ soc/nordic/nrf53/nrf53_cpunet_mgmt.c | 68 ++++++++++++++++++++++++++++ soc/nordic/nrf53/nrf53_cpunet_mgmt.h | 31 +++++++++++++ 4 files changed, 107 insertions(+) create mode 100644 soc/nordic/nrf53/nrf53_cpunet_mgmt.c create mode 100644 soc/nordic/nrf53/nrf53_cpunet_mgmt.h diff --git a/soc/nordic/nrf53/CMakeLists.txt b/soc/nordic/nrf53/CMakeLists.txt index 0e8b1e69a29..145a425e55a 100644 --- a/soc/nordic/nrf53/CMakeLists.txt +++ b/soc/nordic/nrf53/CMakeLists.txt @@ -3,6 +3,7 @@ zephyr_library_sources(soc.c) zephyr_include_directories(.) +zephyr_library_sources_ifdef(CONFIG_SOC_NRF53_CPUNET_MGMT nrf53_cpunet_mgmt.c) zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC sync_rtc.c) if (CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED AND diff --git a/soc/nordic/nrf53/Kconfig b/soc/nordic/nrf53/Kconfig index 7ef9546058d..cc7bdaa5dc6 100644 --- a/soc/nordic/nrf53/Kconfig +++ b/soc/nordic/nrf53/Kconfig @@ -24,6 +24,7 @@ config SOC_NRF5340_CPUAPP select ARMV8_M_DSP select HAS_POWEROFF select SOC_COMPATIBLE_NRF5340_CPUAPP + select SOC_NRF53_CPUNET_MGMT imply SOC_NRF53_RTC_PRETICK imply SOC_NRF53_ANOMALY_168_WORKAROUND @@ -138,6 +139,12 @@ config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 help hidden option for including the nRF GPIO pin forwarding +config SOC_NRF53_CPUNET_MGMT + bool + select ONOFF + help + hidden option for including the nRF53 network CPU management + if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM config SOC_ENABLE_LFXO diff --git a/soc/nordic/nrf53/nrf53_cpunet_mgmt.c b/soc/nordic/nrf53/nrf53_cpunet_mgmt.c new file mode 100644 index 00000000000..57a23d29bb8 --- /dev/null +++ b/soc/nordic/nrf53/nrf53_cpunet_mgmt.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file Nordic Semiconductor nRF53 processors family management helper for the network CPU. + */ + +#include + +#include +#include +#include +#include +#include + +#include + +static struct onoff_manager cpunet_mgr; + +static void onoff_start(struct onoff_manager *mgr, onoff_notify_fn notify) +{ + nrf_reset_network_force_off(NRF_RESET, false); + + notify(mgr, 0); +} + +static void onoff_stop(struct onoff_manager *mgr, onoff_notify_fn notify) +{ + nrf_reset_network_force_off(NRF_RESET, true); + + notify(mgr, 0); +} + +static int nrf53_cpunet_mgmt_init(void) +{ + static const struct onoff_transitions transitions = { + .start = onoff_start, + .stop = onoff_stop + }; + + return onoff_manager_init(&cpunet_mgr, &transitions); +} + +SYS_INIT(nrf53_cpunet_mgmt_init, PRE_KERNEL_1, 0); + +void nrf53_cpunet_enable(bool on) +{ + int ret; + int ignored; + struct onoff_client cli; + + if (on) { + sys_notify_init_spinwait(&cli.notify); + + ret = onoff_request(&cpunet_mgr, &cli); + __ASSERT_NO_MSG(ret >= 0); + + /* The transition is synchronous and shall take effect immediately. */ + ret = sys_notify_fetch_result(&cli.notify, &ignored); + } else { + ret = onoff_release(&cpunet_mgr); + } + + __ASSERT_NO_MSG(ret >= 0); +} diff --git a/soc/nordic/nrf53/nrf53_cpunet_mgmt.h b/soc/nordic/nrf53/nrf53_cpunet_mgmt.h new file mode 100644 index 00000000000..0273061c20c --- /dev/null +++ b/soc/nordic/nrf53/nrf53_cpunet_mgmt.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file Nordic Semiconductor nRF53 processors family management helper for the network CPU. + */ + +#ifndef NRF53_CPUNET_MGMT_H__ +#define NRF53_CPUNET_MGMT_H__ + +#include + +/** + * @brief Enables or disables nRF53 network CPU. + * + * This function shall be used to control the network CPU exclusively. Internally, it keeps track of + * the requests to enable or disable nRF53 network CPU. It guarantees to enable the network CPU if + * at least one user requests it and to keep it enabled until all users release it. + * + * In conseqeuence, if @p on equals @c true then the network CPU is guaranteed to be enabled when + * this function returns. If @p on equals @c false then nothing can be inferred about the state of + * the network CPU when the function returns. + * + * @param on indicates whether the network CPU shall be powered on or off. + */ +void nrf53_cpunet_enable(bool on); + +#endif /* NRF53_CPUNET_MGMT_H__ */ From 955ca269dd22d14c7ae7ed061c0b402547e13834 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Ciupis?= Date: Wed, 10 Apr 2024 11:51:14 +0200 Subject: [PATCH 2346/2402] [nrf fromtree] boards: nrf53: switch to the network CPU management API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switch to the network CPU management API from direct nrfx calls. Signed-off-by: Jędrzej Ciupis (cherry picked from commit 2b23a52642701d2b8f6df6de07c0a2511b28dcc9) --- .../bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c | 4 ++-- .../nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c | 4 ++-- boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c | 4 ++-- boards/nordic/thingy53/board.c | 4 ++-- boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c | 4 ++-- drivers/bluetooth/hci/nrf53_support.c | 6 +++--- samples/subsys/ipc/ipc_service/icmsg/src/main.c | 6 +++--- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c index 49c0e5a1c73..c4f39467314 100644 --- a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c @@ -10,7 +10,7 @@ #include #include -#include +#include LOG_MODULE_REGISTER(bl5340_dvk_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); @@ -50,7 +50,7 @@ static int remoteproc_mgr_boot(void) */ /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); + nrf53_cpunet_enable(true); LOG_DBG("Network MCU released."); #endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c index f9082e6ca40..3d08a5dd4cd 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include LOG_MODULE_REGISTER(nrf5340_audio_dk_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); @@ -71,7 +71,7 @@ static int remoteproc_mgr_boot(void) */ /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); + nrf53_cpunet_enable(true); LOG_DBG("Network MCU released."); #endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ diff --git a/boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c b/boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c index dadba8c0f54..3b85d55dfd0 100644 --- a/boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c +++ b/boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c @@ -9,7 +9,7 @@ #include #include -#include +#include LOG_MODULE_REGISTER(nrf5340dk_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); @@ -49,7 +49,7 @@ static int remoteproc_mgr_boot(void) */ /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); + nrf53_cpunet_enable(true); LOG_DBG("Network MCU released."); #endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ diff --git a/boards/nordic/thingy53/board.c b/boards/nordic/thingy53/board.c index 67059bd4ee8..491808f236a 100644 --- a/boards/nordic/thingy53/board.c +++ b/boards/nordic/thingy53/board.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include LOG_MODULE_REGISTER(thingy53_board_init); @@ -52,7 +52,7 @@ static void enable_cpunet(void) */ /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); + nrf53_cpunet_enable(true); LOG_DBG("Network MCU released."); #endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c index bf0626ce30b..cd8281cb2bf 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c @@ -9,7 +9,7 @@ #include #include -#include +#include #if defined(CONFIG_BOARD_PAN1783_EVB_NRF5340_CPUAPP) LOG_MODULE_REGISTER(pan1783_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); @@ -42,7 +42,7 @@ static int remoteproc_mgr_boot(void) remoteproc_mgr_config(); /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); + nrf53_cpunet_enable(true); LOG_DBG("Network MCU released."); diff --git a/drivers/bluetooth/hci/nrf53_support.c b/drivers/bluetooth/hci/nrf53_support.c index 995586eb325..2d0f64ac428 100644 --- a/drivers/bluetooth/hci/nrf53_support.c +++ b/drivers/bluetooth/hci/nrf53_support.c @@ -6,7 +6,7 @@ #include #include -#include +#include #if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) #include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> #else @@ -21,7 +21,7 @@ int bt_hci_transport_teardown(const struct device *dev) { ARG_UNUSED(dev); /* Put the Network MCU in Forced-OFF mode. */ - nrf_reset_network_force_off(NRF_RESET, true); + nrf53_cpunet_enable(false); LOG_DBG("Network MCU placed in Forced-OFF mode"); return 0; @@ -43,7 +43,7 @@ int bt_hci_transport_setup(const struct device *dev) #endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); + nrf53_cpunet_enable(true); return 0; } diff --git a/samples/subsys/ipc/ipc_service/icmsg/src/main.c b/samples/subsys/ipc/ipc_service/icmsg/src/main.c index 3500b472e7d..d10fa6c8bf6 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/src/main.c +++ b/samples/subsys/ipc/ipc_service/icmsg/src/main.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include #include "common.h" @@ -130,7 +130,7 @@ int main(void) k_msleep(500); LOG_INF("Stop network core"); - nrf_reset_network_force_off(NRF_RESET, true); + nrf53_cpunet_enable(false); LOG_INF("Reset IPC service"); @@ -158,7 +158,7 @@ int main(void) } LOG_INF("Run network core"); - nrf_reset_network_force_off(NRF_RESET, false); + nrf53_cpunet_enable(true); k_sem_take(&bound_sem, K_FOREVER); From 2d2a2e0ae943910f1e005d9709b4df9e0d8b6206 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Ciupis?= Date: Thu, 11 Apr 2024 08:20:21 +0200 Subject: [PATCH 2347/2402] [nrf fromtree] boards: raytac: remove direct RESET register access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace direct access to RESET register to control the network CPU with dedicated API, which allows safely sharing the network CPU with other users. Signed-off-by: Jędrzej Ciupis (cherry picked from commit 2371dce46bc8fba09438c1c52904d0204cd76aaa) --- .../mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c | 3 ++- .../mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c index 97ae3fc1bd0..64e335869fb 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c @@ -10,6 +10,7 @@ #include #include +#include LOG_MODULE_REGISTER(raytac_mdbt53_db_40_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); @@ -49,7 +50,7 @@ static int remoteproc_mgr_boot(const struct device *dev) */ /* Release the Network MCU, 'Release force off signal' */ - NRF_RESET->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release; + nrf53_cpunet_enable(true); LOG_DBG("Network MCU released."); #endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c index fd48ae16fd6..ec4567274c4 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c @@ -49,7 +49,7 @@ static int remoteproc_mgr_boot(const struct device *dev) */ /* Release the Network MCU, 'Release force off signal' */ - NRF_RESET->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release; + nrf53_cpunet_enable(true); LOG_DBG("Network MCU released."); #endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ From 51c8066bf063263b457ecb3f6f179d80cd0238e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20G=C5=82=C4=85b?= Date: Fri, 5 Apr 2024 10:43:41 +0200 Subject: [PATCH 2348/2402] [nrf fromtree] tests: drivers: clock_control: Add nRF54L15 to platform allow MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nRF54L15 to platform_allow in the sample.yaml: - clock_control_api, - nrf_clock_calibration, - nrf_lf_clock_start, - onoff. Signed-off-by: Sebastian Głąb (cherry picked from commit 5600ae335b104f6ba088693946ee3e60b63161b9) --- .../clock_control/clock_control_api/testcase.yaml | 2 ++ .../clock_control/nrf_clock_calibration/testcase.yaml | 1 + .../clock_control/nrf_lf_clock_start/testcase.yaml | 9 +++++++++ tests/drivers/clock_control/onoff/testcase.yaml | 1 + 4 files changed, 13 insertions(+) diff --git a/tests/drivers/clock_control/clock_control_api/testcase.yaml b/tests/drivers/clock_control/clock_control_api/testcase.yaml index 7a3552fd4e7..356893f400f 100644 --- a/tests/drivers/clock_control/clock_control_api/testcase.yaml +++ b/tests/drivers/clock_control/clock_control_api/testcase.yaml @@ -8,6 +8,7 @@ tests: - nrf52dk/nrf52832 - nrf52840dk/nrf52840 - nrf9160dk/nrf9160 + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf51dk/nrf51822 drivers.clock.clock_control_nrf5_lfclk_rc: @@ -18,6 +19,7 @@ tests: - nrf51dk/nrf51822 - nrf52dk/nrf52832 - nrf52840dk/nrf52840 + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf51dk/nrf51822 extra_args: CONF_FILE="nrf_lfclk_rc.conf" diff --git a/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml b/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml index 2e2934b33ea..e5f1248f5ec 100644 --- a/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml +++ b/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml @@ -7,5 +7,6 @@ tests: - nrf51dk/nrf51822 - nrf52dk/nrf52832 - nrf52840dk/nrf52840 + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf51dk/nrf51822 diff --git a/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml b/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml index a5716326ab9..c35d4529722 100644 --- a/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml +++ b/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml @@ -13,6 +13,7 @@ tests: - nrf9160dk/nrf9160 - nrf5340dk/nrf5340/cpuapp - nrf5340dk/nrf5340/cpunet + - nrf54l15pdk/nrf54l15/cpuapp extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_STABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y @@ -27,6 +28,7 @@ tests: - nrf9160dk/nrf9160 - nrf5340dk/nrf5340/cpuapp - nrf5340dk/nrf5340/cpunet + - nrf54l15pdk/nrf54l15/cpuapp extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y @@ -41,6 +43,7 @@ tests: - nrf9160dk/nrf9160 - nrf5340dk/nrf5340/cpuapp - nrf5340dk/nrf5340/cpunet + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf51dk/nrf51822 extra_configs: @@ -54,6 +57,7 @@ tests: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf5340dk/nrf5340/cpunet + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf51dk/nrf51822 extra_configs: @@ -67,6 +71,7 @@ tests: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf5340dk/nrf5340/cpunet + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf51dk/nrf51822 extra_configs: @@ -80,6 +85,7 @@ tests: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf5340dk/nrf5340/cpunet + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf51dk/nrf51822 extra_configs: @@ -93,6 +99,7 @@ tests: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf5340dk/nrf5340/cpunet + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf51dk/nrf51822 extra_configs: @@ -106,6 +113,7 @@ tests: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf5340dk/nrf5340/cpunet + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf51dk/nrf51822 extra_configs: @@ -119,6 +127,7 @@ tests: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf5340dk/nrf5340/cpunet + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf51dk/nrf51822 extra_configs: diff --git a/tests/drivers/clock_control/onoff/testcase.yaml b/tests/drivers/clock_control/onoff/testcase.yaml index 91239e3b538..867ae2dce40 100644 --- a/tests/drivers/clock_control/onoff/testcase.yaml +++ b/tests/drivers/clock_control/onoff/testcase.yaml @@ -7,6 +7,7 @@ tests: - nrf51dk/nrf51822 - nrf52dk/nrf52832 - nrf52840dk/nrf52840 + - nrf54l15pdk/nrf54l15/cpuapp - nrf9160dk/nrf9160 integration_platforms: - nrf51dk/nrf51822 From 08dee4bd57722e199e249e4b87b7f9961e3c92de Mon Sep 17 00:00:00 2001 From: Brad Kemp Date: Tue, 2 Apr 2024 13:26:20 -0400 Subject: [PATCH 2349/2402] [nrf fromtree] net: wifi: shell: update wifi ap enable to use get opt parsing The commit 8256d02d3a9625c03e1d584cf54b1f0cc1ae164b introduced getopt parsing for the wifi connect command This needs to be updated for the wifi ap enable since ap enable also uses the same parsing as connect. The use of getopt removes the parameter ordering restrictions Signed-off-by: Brad Kemp (cherry picked from commit 3e2c067010cd26220d66d3237d891f6e4a3ed05e) --- subsys/net/l2/wifi/wifi_shell.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 946a9b1939e..99d49535fa0 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -496,12 +496,8 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv } break; case 'p': - if (secure_connection) { - params->psk = optarg; - params->psk_length = strlen(params->psk); - } else { - PR_WARNING("Passphrase provided without security configuration\n"); - } + params->psk = optarg; + params->psk_length = strlen(params->psk); break; case 'c': channel = strtol(optarg, &endptr, 10); @@ -568,7 +564,7 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv ¶ms->bssid[4], ¶ms->bssid[5]); break; case 'h': - shell_help(sh); + return -ENOEXEC; break; default: PR_ERROR("Invalid option %c\n", opt); @@ -576,7 +572,9 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv return -EINVAL; } } - + if (params->psk && !secure_connection) { + PR_WARNING("Passphrase provided without security configuration\n"); + } return 0; } @@ -1244,7 +1242,7 @@ static int cmd_wifi_ap_enable(const struct shell *sh, size_t argc, int ret; context.sh = sh; - if (__wifi_args_to_params(sh, argc - 1, &argv[1], &cnx_params, WIFI_MODE_AP)) { + if (__wifi_args_to_params(sh, argc, &argv[0], &cnx_params, WIFI_MODE_AP)) { shell_help(sh); return -ENOEXEC; } @@ -1847,15 +1845,18 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_cmd_ap, cmd_wifi_ap_disable, 1, 0), SHELL_CMD_ARG(enable, NULL, - "\"\"\n" - "\n" - "[PSK: valid only for secure SSIDs]\n" - "[Security type: valid only for secure SSIDs]\n" + "-s --ssid=\n" + "-c --channel=\n" + "-p --passphrase= (valid only for secure SSIDs)\n" + "-k --key-mgmt= (valid only for secure SSIDs)\n" "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP, 7: WPA-PSK\n" - "[MFP (optional: needs security type to be specified)]\n" - ": 0:Disable, 1:Optional, 2:Required.\n", + "-w --ieee-80211w= (optional: needs security type to be specified)\n" + "0:Disable, 1:Optional, 2:Required\n" + "-b --band= (2 -2.6GHz, 5 - 5Ghz, 6 - 6GHz)\n" + "-m --bssid=\n" + "-h --help (prints help)", cmd_wifi_ap_enable, - 3, 3), + 2, 13), SHELL_CMD_ARG(stations, NULL, "List stations connected to the AP", cmd_wifi_ap_stations, From 73bef57621faa003a733c541fdcd8eeaeed75b44 Mon Sep 17 00:00:00 2001 From: Ravi Dondaputi Date: Mon, 15 Apr 2024 13:36:31 +0530 Subject: [PATCH 2350/2402] [nrf fromlist] net: wifi: shell: Correct help text for `connect` command Since `NONE` is a valid option for key management in `connect` command, we should remove the part in help text which says: "valid only for secure SSIDs". Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71319 Signed-off-by: Ravi Dondaputi --- subsys/net/l2/wifi/wifi_shell.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 99d49535fa0..bae31b9c3ed 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -1905,7 +1905,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_commands, "[-c --channel]: Channel that needs to be scanned for connection. 0:any channel.\n" "[-b, --band] 0: any band (2:2.4GHz, 5:5GHz, 6:6GHz]\n" "[-p, --psk]: Passphrase (valid only for secure SSIDs)\n" - "[-k, --key-mgmt]: Key Management type (valid only for secure SSIDs)\n" + "[-k, --key-mgmt]: Key Management type\n" "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP, 7: WPA-PSK\n" "[-w, --ieee-80211w]: MFP (optional: needs security type to be specified)\n" ": 0:Disable, 1:Optional, 2:Required.\n" From da1af7e1288d011b76df72b71334749003ffa95b Mon Sep 17 00:00:00 2001 From: Ravi Dondaputi Date: Mon, 15 Apr 2024 17:45:02 +0530 Subject: [PATCH 2351/2402] [nrf fromlist] net: wifi: shell: Remove redundant break Having a `break` statement after `return` is redundant and needs to be removed. Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71319 Signed-off-by: Ravi Dondaputi --- subsys/net/l2/wifi/wifi_shell.c | 1 - 1 file changed, 1 deletion(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index bae31b9c3ed..46a2457c6c8 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -565,7 +565,6 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv break; case 'h': return -ENOEXEC; - break; default: PR_ERROR("Invalid option %c\n", opt); shell_help(sh); From 4dd0af500d9911ce3953d29c0eb9cbbba8eefb08 Mon Sep 17 00:00:00 2001 From: Piotr Kosycarz Date: Wed, 10 Apr 2024 13:00:14 +0200 Subject: [PATCH 2352/2402] [nrf fromtree] boards: nordic: nrf54h20dk: enable HWFC For both UARTs connected to debugger chip. Signed-off-by: Piotr Kosycarz (cherry picked from commit c7c6cb4c99b09a1cdc4686f5f0ef6fe7a0c17d6c) --- boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 1 + boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts | 1 + boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 8c6512861e8..495271d576b 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -173,4 +173,5 @@ pinctrl-0 = <&uart136_default>; pinctrl-1 = <&uart136_sleep>; pinctrl-names = "default", "sleep"; + hw-flow-control; }; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts index edce1a8b275..679afcdc8f9 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts @@ -46,6 +46,7 @@ pinctrl-0 = <&uart135_default>; pinctrl-1 = <&uart135_sleep>; pinctrl-names = "default", "sleep"; + hw-flow-control; }; &uart136 { diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index 3efa07f6349..b2f14ff2525 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -69,6 +69,7 @@ pinctrl-0 = <&uart135_default>; pinctrl-1 = <&uart135_sleep>; pinctrl-names = "default", "sleep"; + hw-flow-control; }; &uart136 { From b3ec34595efd1462c60b7b811d27f2e745c7ed9a Mon Sep 17 00:00:00 2001 From: Chaitanya Tata Date: Mon, 15 Apr 2024 17:31:16 +0530 Subject: [PATCH 2353/2402] [nrf fromtree] boards: nrf54h20dk: Enable shell input This enables typing commands in shell over UART. Signed-off-by: Chaitanya Tata (cherry picked from commit c091c944b6caaf4fa0ae79fe8785ed207b6ce39e) --- boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 1 + boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts | 1 + boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 495271d576b..21a7b9ca7e2 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -22,6 +22,7 @@ zephyr,code-partition = &cpuapp_slot0_partition; zephyr,flash = &mram1x; zephyr,sram = &cpuapp_data; + zephyr,shell-uart = &uart136; }; aliases { diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts index 679afcdc8f9..4cfad97323e 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts @@ -26,6 +26,7 @@ zephyr,code-partition = &cpuppr_code_partition; zephyr,flash = &mram1x; zephyr,sram = &cpuppr_code_data; + zephyr,shell-uart = &uart135; }; }; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index b2f14ff2525..a3d3736fde2 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -23,6 +23,7 @@ zephyr,code-partition = &cpurad_slot0_partition; zephyr,flash = &mram1x; zephyr,sram = &cpurad_ram0; + zephyr,shell-uart = &uart135; }; }; From 443cae032ef887b04063a8d25bf3a26d0acb20b7 Mon Sep 17 00:00:00 2001 From: Kamil Gawor Date: Mon, 15 Apr 2024 11:52:36 +0200 Subject: [PATCH 2354/2402] [nrf fromlist] boards: nordic: nrf54h20dk: Change IPC default backend Change IPC backend between Application and Radio core to icbmsg which is more future proof than legacy icmsg_me backend. Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71492 Signed-off-by: Kamil Gawor (cherry picked from commit dba219bc9c7c9a170c42f04ce0b78011a9f3dfa3) --- boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi | 1 + boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 3 ++- boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts | 3 ++- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi index 9c3d971b9bc..539e80d149a 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi @@ -21,6 +21,7 @@ }; cpuapp_cpurad_ipc: ipc-2-3 { + compatible = "zephyr,ipc-icbmsg"; status = "disabled"; mboxes = <&cpuapp_bellboard 18>, <&cpurad_bellboard 12>; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 21a7b9ca7e2..f6427f477b2 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -111,10 +111,11 @@ }; &cpuapp_cpurad_ipc { - compatible = "zephyr,ipc-icmsg-me-initiator"; mbox-names = "rx", "tx"; tx-region = <&cpuapp_cpurad_ipc_shm>; rx-region = <&cpurad_cpuapp_ipc_shm>; + tx-blocks = <32>; + rx-blocks = <32>; }; &cpuapp_cpuppr_ipc { diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index a3d3736fde2..2b970a1b3e2 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -45,10 +45,11 @@ }; &cpuapp_cpurad_ipc { - compatible = "zephyr,ipc-icmsg-me-follower"; mbox-names = "tx", "rx"; tx-region = <&cpurad_cpuapp_ipc_shm>; rx-region = <&cpuapp_cpurad_ipc_shm>; + tx-blocks = <32>; + rx-blocks = <32>; }; &cpurad_dma_region { From 12bfeea211d9928d0fecfca8b45c42d3a81eafbe Mon Sep 17 00:00:00 2001 From: Kamil Gawor Date: Mon, 15 Apr 2024 14:05:47 +0200 Subject: [PATCH 2355/2402] [nrf fromlist] boards: nordic: nrf54h20dk: Add configuration for BLE Add default configuration related to BLE protocol, for Application and Radio core on nRF54h20 platform. Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71501 Signed-off-by: Kamil Gawor (cherry picked from commit 0fba136786caeb79398de81cd189c4949e4c14ca) --- .../nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 13 ++++++++- .../nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts | 13 ++++++++- .../boards/nrf54h20dk_nrf54h20_cpurad.overlay | 27 ------------------- 3 files changed, 24 insertions(+), 29 deletions(-) delete mode 100644 samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index f6427f477b2..93259180e43 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -23,6 +23,7 @@ zephyr,flash = &mram1x; zephyr,sram = &cpuapp_data; zephyr,shell-uart = &uart136; + zephyr,bt-hci-ipc = &ipc0; }; aliases { @@ -93,24 +94,34 @@ status = "okay"; }; +&cpuapp_cpurad_ram0x_region { + status = "okay"; +}; + &shared_ram3x_region { status = "okay"; }; &cpuapp_bellboard { + status = "okay"; interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; interrupt-names = "irq0"; /* irq0: 0: cpuapp-cpusec, 13: cpuapp-cpuppr, 18: cpuapp-cpurad */ nordic,interrupt-mapping = <0x00042001 0>; }; +&cpurad_bellboard { + status = "okay"; +}; + &cpusec_cpuapp_ipc { mbox-names = "tx", "rx"; tx-region = <&cpuapp_cpusec_ipc_shm>; rx-region = <&cpusec_cpuapp_ipc_shm>; }; -&cpuapp_cpurad_ipc { +ipc0: &cpuapp_cpurad_ipc { + status = "okay"; mbox-names = "rx", "tx"; tx-region = <&cpuapp_cpurad_ipc_shm>; rx-region = <&cpurad_cpuapp_ipc_shm>; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index 2b970a1b3e2..c0b9c0b47b7 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -24,6 +24,7 @@ zephyr,flash = &mram1x; zephyr,sram = &cpurad_ram0; zephyr,shell-uart = &uart135; + zephyr,bt-hci-ipc = &ipc0; }; }; @@ -31,20 +32,30 @@ status = "okay"; }; +&cpuapp_cpurad_ram0x_region { + status = "okay"; +}; + &cpurad_bellboard { + status = "okay"; interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; interrupt-names = "irq0"; /* irq0: 0: cpurad-cpusec, 12: cpurad-cpuapp */ nordic,interrupt-mapping = <0x00001001 0>; }; +&cpuapp_bellboard { + status = "okay"; +}; + &cpusec_cpurad_ipc { mbox-names = "tx", "rx"; tx-region = <&cpurad_cpusec_ipc_shm>; rx-region = <&cpusec_cpurad_ipc_shm>; }; -&cpuapp_cpurad_ipc { +ipc0: &cpuapp_cpurad_ipc { + status = "okay"; mbox-names = "tx", "rx"; tx-region = <&cpurad_cpuapp_ipc_shm>; rx-region = <&cpuapp_cpurad_ipc_shm>; diff --git a/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay deleted file mode 100644 index 02db7c39272..00000000000 --- a/samples/bluetooth/hci_ipc/boards/nrf54h20dk_nrf54h20_cpurad.overlay +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,bt-hci-ipc = &ipc0; - }; -}; - -ipc0: &cpuapp_cpurad_ipc { - status = "okay"; -}; - -&cpuapp_cpurad_ram0x_region { - status = "okay"; -}; - -&cpurad_bellboard { - status = "okay"; -}; - -&cpuapp_bellboard { - status = "okay"; -}; From 2c8aad6f4ed4f550a01b86f935d145b5ad43b4e2 Mon Sep 17 00:00:00 2001 From: Bartosz Sokolski Date: Thu, 11 Apr 2024 11:05:55 +0200 Subject: [PATCH 2356/2402] [nrf fromtree] boards: nrf54l15pdk_nrf54l15_cpuapp: add twister yaml for PDK 0.3.0 add twister yaml to support PDK 0.3.0 in tests Signed-off-by: Bartosz Sokolski (cherry picked from commit e1ef3e41deccba17f217b1992e6c04ae6151e279) --- .../nrf54l15pdk_nrf54l15_cpuapp_0_3_0.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.yaml diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.yaml b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.yaml new file mode 100644 index 00000000000..a19bc8fdc8b --- /dev/null +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.yaml @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l15pdk@0.3.0/nrf54l15/cpuapp +name: nRF54l15-PDK-nRF54l15-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 256 +flash: 1536 +supported: + - counter + - gpio + - i2c + - spi + - watchdog + - i2s From 85ed6f2655de3528e58e766505a02bbd46dcbeaf Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Tue, 9 Apr 2024 15:49:05 +0100 Subject: [PATCH 2357/2402] [nrf fromlist] cmake: modules: extensions: Rename prefix in functions Renames a prefix in a function to avoid clashes with global variable that have the same name Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71280 Signed-off-by: Jamie McCrae (cherry picked from commit 030130573a035f50f0cc931763e4767dd3e8ab3b) --- cmake/modules/extensions.cmake | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index 4c989e808ae..2c1866c422a 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -2865,9 +2865,9 @@ endfunction() # function(zephyr_file_suffix filename) set(single_args SUFFIX) - cmake_parse_arguments(FILE "" "${single_args}" "" ${ARGN}) + cmake_parse_arguments(SFILE "" "${single_args}" "" ${ARGN}) - if(NOT DEFINED FILE_SUFFIX OR NOT DEFINED ${filename}) + if(NOT DEFINED SFILE_SUFFIX OR NOT DEFINED ${filename}) # If the file suffix variable is not known then there is nothing to do, return early return() endif() @@ -2883,7 +2883,7 @@ function(zephyr_file_suffix filename) # Search for the full stop so we know where to add the file suffix before the file extension cmake_path(GET file EXTENSION file_ext) cmake_path(REMOVE_EXTENSION file OUTPUT_VARIABLE new_filename) - cmake_path(APPEND_STRING new_filename "_${FILE_SUFFIX}${file_ext}") + cmake_path(APPEND_STRING new_filename "_${SFILE_SUFFIX}${file_ext}") # Use the filename with the suffix if it exists, if not then fall back to the default if(EXISTS "${new_filename}") From 77a71701509491a6cf0a220b80537dff08ac304d Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Wed, 3 Apr 2024 13:46:16 +0200 Subject: [PATCH 2358/2402] [nrf fromtree] Bluetooth: Controller: Fix regression in BT_RX_STACK_SIZE use Fix regression in BT_RX_STACK_SIZE use due to commit b91728619c05 ("Bluetooth: host: remove `CONFIG_BT_RECV_BLOCKING`"). Profiling of Controller Rx thread has been mentioned in commit 586ba9fd13e8 ("Bluetooth: Controller: Increase BT_RX_STACK_SIZE for BT_HCI_RAW enabled"). Also, move the TX_STACK_SIZE value as default in Kconfig from the explicit value being set in hci_ipc sample. Signed-off-by: Vinayak Kariappa Chettimada (cherry picked from commit 7ece6aed16c270ccc6736e815be7cf7c3fd77f50) --- .../hci_ipc/nrf5340_cpunet_bis-bt_ll_sw_split.conf | 6 ------ .../hci_ipc/nrf5340_cpunet_cis-bt_ll_sw_split.conf | 6 ------ .../hci_ipc/nrf5340_cpunet_df-bt_ll_sw_split.conf | 6 ------ .../hci_ipc/nrf5340_cpunet_iso-bt_ll_sw_split.conf | 6 ------ .../nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf | 6 ------ .../nrf5340_cpunet_iso_central-bt_ll_sw_split.conf | 6 ------ .../nrf5340_cpunet_iso_peripheral-bt_ll_sw_split.conf | 6 ------ .../nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf | 6 ------ samples/bluetooth/peripheral_hr/prj_minimal.conf | 1 - subsys/bluetooth/controller/Kconfig.ll_sw_split | 9 +++++++-- subsys/bluetooth/controller/hci/hci_driver.c | 2 +- subsys/bluetooth/host/Kconfig | 2 +- .../nrf5340_cpunet_iso_acl_group-bt_ll_sw_split.conf | 6 ------ 13 files changed, 9 insertions(+), 59 deletions(-) diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_bis-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_bis-bt_ll_sw_split.conf index f0a22f760f9..6b407a208f7 100644 --- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_bis-bt_ll_sw_split.conf +++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_bis-bt_ll_sw_split.conf @@ -24,12 +24,6 @@ CONFIG_BT_BUF_ACL_RX_SIZE=255 CONFIG_BT_BUF_ACL_TX_SIZE=251 CONFIG_BT_BUF_CMD_TX_SIZE=255 -# Tx/Rx Thread Stack Sizes -CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT=y -CONFIG_BT_HCI_TX_STACK_SIZE=1152 -CONFIG_BT_RX_STACK_SIZE=640 -CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE=448 - # Host features CONFIG_BT_EXT_ADV=y CONFIG_BT_PER_ADV=y diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_cis-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_cis-bt_ll_sw_split.conf index 7fab285f3be..6dd49214caa 100644 --- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_cis-bt_ll_sw_split.conf +++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_cis-bt_ll_sw_split.conf @@ -24,12 +24,6 @@ CONFIG_BT_BUF_ACL_RX_SIZE=255 CONFIG_BT_BUF_ACL_TX_SIZE=251 CONFIG_BT_BUF_CMD_TX_SIZE=255 -# Tx/Rx Thread Stack Sizes -CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT=y -CONFIG_BT_HCI_TX_STACK_SIZE=1152 -CONFIG_BT_RX_STACK_SIZE=640 -CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE=448 - # Host features CONFIG_BT_EXT_ADV=y CONFIG_BT_PER_ADV=n diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_df-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_df-bt_ll_sw_split.conf index 21d4a042ad7..ab87866b19a 100644 --- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_df-bt_ll_sw_split.conf +++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_df-bt_ll_sw_split.conf @@ -24,12 +24,6 @@ CONFIG_BT_BUF_ACL_RX_SIZE=255 CONFIG_BT_BUF_ACL_TX_SIZE=251 CONFIG_BT_BUF_CMD_TX_SIZE=255 -# Tx/Rx Thread Stack Sizes -CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT=y -CONFIG_BT_HCI_TX_STACK_SIZE=1152 -CONFIG_BT_RX_STACK_SIZE=640 -CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE=448 - # Host features CONFIG_BT_EXT_ADV=y CONFIG_BT_PER_ADV=y diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso-bt_ll_sw_split.conf index f80f324be53..0bb34dfa790 100644 --- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso-bt_ll_sw_split.conf +++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso-bt_ll_sw_split.conf @@ -25,12 +25,6 @@ CONFIG_BT_BUF_ACL_RX_SIZE=255 CONFIG_BT_BUF_ACL_TX_SIZE=251 CONFIG_BT_BUF_CMD_TX_SIZE=255 -# Tx/Rx Thread Stack Sizes -CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT=y -CONFIG_BT_HCI_TX_STACK_SIZE=1152 -CONFIG_BT_RX_STACK_SIZE=640 -CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE=448 - # Host features CONFIG_BT_EXT_ADV=y CONFIG_BT_PER_ADV=y diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf index 74dc735c076..12f3b8a1147 100644 --- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf +++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf @@ -16,12 +16,6 @@ CONFIG_BT_HCI_RAW_RESERVE=1 # Host number of completed commands does not follow normal flow control. CONFIG_BT_BUF_CMD_TX_COUNT=10 -# Tx/Rx Thread Stack Sizes -CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT=y -CONFIG_BT_HCI_TX_STACK_SIZE=1152 -CONFIG_BT_RX_STACK_SIZE=640 -CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE=448 - # Host CONFIG_BT_BROADCASTER=y CONFIG_BT_PERIPHERAL=n diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_central-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_central-bt_ll_sw_split.conf index f29917aaf93..e7ec0c140d6 100644 --- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_central-bt_ll_sw_split.conf +++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_central-bt_ll_sw_split.conf @@ -21,12 +21,6 @@ CONFIG_BT_BUF_ACL_RX_SIZE=255 CONFIG_BT_BUF_ACL_TX_SIZE=251 CONFIG_BT_BUF_CMD_TX_SIZE=255 -# Tx/Rx Thread Stack Sizes -CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT=y -CONFIG_BT_HCI_TX_STACK_SIZE=1152 -CONFIG_BT_RX_STACK_SIZE=640 -CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE=448 - # Host CONFIG_BT_BROADCASTER=n CONFIG_BT_PERIPHERAL=n diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_peripheral-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_peripheral-bt_ll_sw_split.conf index ddd7d7e7b31..fa3d303604e 100644 --- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_peripheral-bt_ll_sw_split.conf +++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_peripheral-bt_ll_sw_split.conf @@ -21,12 +21,6 @@ CONFIG_BT_BUF_ACL_RX_SIZE=255 CONFIG_BT_BUF_ACL_TX_SIZE=251 CONFIG_BT_BUF_CMD_TX_SIZE=255 -# Tx/Rx Thread Stack Sizes -CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT=y -CONFIG_BT_HCI_TX_STACK_SIZE=1152 -CONFIG_BT_RX_STACK_SIZE=640 -CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE=448 - # Host CONFIG_BT_BROADCASTER=y CONFIG_BT_PERIPHERAL=y diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf index d88aa87f8aa..d139e83996a 100644 --- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf +++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf @@ -16,12 +16,6 @@ CONFIG_BT_HCI_RAW_RESERVE=1 # Host number of completed commands does not follow normal flow control. CONFIG_BT_BUF_CMD_TX_COUNT=10 -# Tx/Rx Thread Stack Sizes -CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT=y -CONFIG_BT_HCI_TX_STACK_SIZE=1152 -CONFIG_BT_RX_STACK_SIZE=640 -CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE=448 - # Host CONFIG_BT_BROADCASTER=n CONFIG_BT_PERIPHERAL=n diff --git a/samples/bluetooth/peripheral_hr/prj_minimal.conf b/samples/bluetooth/peripheral_hr/prj_minimal.conf index 888c75d8a5d..a9feeb48cb0 100644 --- a/samples/bluetooth/peripheral_hr/prj_minimal.conf +++ b/samples/bluetooth/peripheral_hr/prj_minimal.conf @@ -69,7 +69,6 @@ CONFIG_ARM_MPU=n # idle 00 : STACK: unused 208 usage 48 / 256 (18 %); CPU: 97 % # main : STACK: unused 576 usage 448 / 1024 (43 %); CPU: 0 % CONFIG_BT_RX_STACK_SIZE=1024 -CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE=448 CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT=y CONFIG_BT_HCI_TX_STACK_SIZE=640 CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=512 diff --git a/subsys/bluetooth/controller/Kconfig.ll_sw_split b/subsys/bluetooth/controller/Kconfig.ll_sw_split index ba43622604a..bce9b76186f 100644 --- a/subsys/bluetooth/controller/Kconfig.ll_sw_split +++ b/subsys/bluetooth/controller/Kconfig.ll_sw_split @@ -99,10 +99,15 @@ config BT_CTLR_ULL_LLL_PRIO_SUPPORT bool config BT_CTLR_RX_PRIO_STACK_SIZE - # Controller's Co-Operative high priority Rx thread stack size. - int "High priority Rx thread stack size" + # Hidden, Controller's Co-Operative high priority Rx thread stack size. + int default 448 +config BT_CTLR_RX_STACK_SIZE + # Hidden, Controller's Co-Operative Rx thread stack size. + int + default 768 + config BT_CTLR_SETTINGS bool "Settings System" depends on SETTINGS diff --git a/subsys/bluetooth/controller/hci/hci_driver.c b/subsys/bluetooth/controller/hci/hci_driver.c index cc315a99df6..9c66594bcda 100644 --- a/subsys/bluetooth/controller/hci/hci_driver.c +++ b/subsys/bluetooth/controller/hci/hci_driver.c @@ -73,7 +73,7 @@ struct k_thread prio_recv_thread_data; static K_KERNEL_STACK_DEFINE(prio_recv_thread_stack, CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE); struct k_thread recv_thread_data; -static K_KERNEL_STACK_DEFINE(recv_thread_stack, CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE); +static K_KERNEL_STACK_DEFINE(recv_thread_stack, CONFIG_BT_CTLR_RX_STACK_SIZE); #if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL) static struct k_poll_signal hbuf_signal; diff --git a/subsys/bluetooth/host/Kconfig b/subsys/bluetooth/host/Kconfig index 0be375007ca..1753c7a2d6a 100644 --- a/subsys/bluetooth/host/Kconfig +++ b/subsys/bluetooth/host/Kconfig @@ -48,7 +48,7 @@ config BT_HCI_TX_STACK_SIZE default 512 if BT_H4 default 512 if BT_H5 default 416 if BT_SPI - default 940 if BT_CTLR && BT_LL_SW_SPLIT && (NO_OPTIMIZATIONS || BT_ISO_BROADCAST) + default 1152 if BT_CTLR && BT_LL_SW_SPLIT && (NO_OPTIMIZATIONS || BT_ISO_BROADCAST) default 1024 if BT_CTLR && BT_LL_SW_SPLIT && BT_CENTRAL default 768 if BT_CTLR && BT_LL_SW_SPLIT default 512 if BT_USERCHAN diff --git a/tests/bsim/bluetooth/ll/cis/sysbuild/hci_ipc/nrf5340_cpunet_iso_acl_group-bt_ll_sw_split.conf b/tests/bsim/bluetooth/ll/cis/sysbuild/hci_ipc/nrf5340_cpunet_iso_acl_group-bt_ll_sw_split.conf index a3c8f43c71f..4a53b153a5c 100644 --- a/tests/bsim/bluetooth/ll/cis/sysbuild/hci_ipc/nrf5340_cpunet_iso_acl_group-bt_ll_sw_split.conf +++ b/tests/bsim/bluetooth/ll/cis/sysbuild/hci_ipc/nrf5340_cpunet_iso_acl_group-bt_ll_sw_split.conf @@ -25,12 +25,6 @@ CONFIG_BT_BUF_ACL_RX_SIZE=255 CONFIG_BT_BUF_ACL_TX_SIZE=251 CONFIG_BT_BUF_CMD_TX_SIZE=255 -# Tx/Rx Thread Stack Sizes -CONFIG_BT_HCI_TX_STACK_SIZE_WITH_PROMPT=y -CONFIG_BT_HCI_TX_STACK_SIZE=1152 -CONFIG_BT_RX_STACK_SIZE=640 -CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE=448 - # Host features CONFIG_BT_EXT_ADV=y CONFIG_BT_PER_ADV=y From 12f0521d1fcaafc39f96e6804536b584644db433 Mon Sep 17 00:00:00 2001 From: Andrzej Puzdrowski Date: Fri, 12 Apr 2024 11:49:02 +0200 Subject: [PATCH 2359/2402] [nrf fromlist] soc/nordic/comomn: Added HAS_HW_NRF_GPIO2 Added Kconfig indicator boolean for HW instance of GPIO2. Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71425 Signed-off-by: Andrzej Puzdrowski (cherry picked from commit cc1de21afbd706b8953cb3301d8eebbc22992816) --- soc/nordic/common/Kconfig.peripherals | 3 +++ 1 file changed, 3 insertions(+) diff --git a/soc/nordic/common/Kconfig.peripherals b/soc/nordic/common/Kconfig.peripherals index bc79b63d1d8..817002f7282 100644 --- a/soc/nordic/common/Kconfig.peripherals +++ b/soc/nordic/common/Kconfig.peripherals @@ -74,6 +74,9 @@ config HAS_HW_NRF_GPIO0 config HAS_HW_NRF_GPIO1 def_bool $(dt_nodelabel_enabled_with_compat,gpio1,$(DT_COMPAT_NORDIC_NRF_GPIO)) +config HAS_HW_NRF_GPIO2 + def_bool $(dt_nodelabel_enabled_with_compat,gpio2,$(DT_COMPAT_NORDIC_NRF_GPIO)) + config HAS_HW_NRF_GPIOTE0 def_bool $(dt_nodelabel_enabled_with_compat,gpiote0,$(DT_COMPAT_NORDIC_NRF_GPIOTE)) From d39eff89a3ced3a9fdbdb5ad4d7cb513a9628ac7 Mon Sep 17 00:00:00 2001 From: Ravi Dondaputi Date: Tue, 16 Apr 2024 19:13:37 +0530 Subject: [PATCH 2360/2402] [nrf fromlist] wifi: shell: Support WPA auto personal security mode Applications need to run a scan to identify the security mode before attempting the connection which adds to the time taken for connection to be established. To avoid the initial scan, support auto security mode which will enable STA to choose between WPA, WPA2 and WPA3, based on the network configuration. Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71044 Signed-off-by: Ravi Dondaputi (cherry picked from commit e9375df78af4ce0589ed8651a500c5d45617fdf2) --- include/zephyr/net/wifi.h | 2 ++ subsys/net/l2/wifi/wifi_mgmt.c | 3 ++- subsys/net/l2/wifi/wifi_shell.c | 5 +++-- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/include/zephyr/net/wifi.h b/include/zephyr/net/wifi.h index a0840a2319a..ebfc76d2192 100644 --- a/include/zephyr/net/wifi.h +++ b/include/zephyr/net/wifi.h @@ -49,6 +49,8 @@ enum wifi_security_type { WIFI_SECURITY_TYPE_WEP, /** WPA-PSK security. */ WIFI_SECURITY_TYPE_WPA_PSK, + /** WPA/WPA2/WPA3 PSK security. */ + WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL, __WIFI_SECURITY_TYPE_AFTER_LAST, WIFI_SECURITY_TYPE_MAX = __WIFI_SECURITY_TYPE_AFTER_LAST - 1, diff --git a/subsys/net/l2/wifi/wifi_mgmt.c b/subsys/net/l2/wifi/wifi_mgmt.c index 72552d371d7..51e76aec5fb 100644 --- a/subsys/net/l2/wifi/wifi_mgmt.c +++ b/subsys/net/l2/wifi/wifi_mgmt.c @@ -275,7 +275,8 @@ static int wifi_connect(uint32_t mgmt_request, struct net_if *iface, (params->ssid_length == 0U) || ((params->security == WIFI_SECURITY_TYPE_PSK || params->security == WIFI_SECURITY_TYPE_WPA_PSK || - params->security == WIFI_SECURITY_TYPE_PSK_SHA256) && + params->security == WIFI_SECURITY_TYPE_PSK_SHA256 || + params->security == WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL) && ((params->psk_length < 8) || (params->psk_length > 64) || (params->psk_length == 0U) || !params->psk)) || ((params->security == WIFI_SECURITY_TYPE_SAE) && diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 46a2457c6c8..954b6aecc07 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -1904,8 +1904,9 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_commands, "[-c --channel]: Channel that needs to be scanned for connection. 0:any channel.\n" "[-b, --band] 0: any band (2:2.4GHz, 5:5GHz, 6:6GHz]\n" "[-p, --psk]: Passphrase (valid only for secure SSIDs)\n" - "[-k, --key-mgmt]: Key Management type\n" - "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP, 7: WPA-PSK\n" + "[-k, --key-mgmt]: Key Management type (valid only for secure SSIDs)\n" + "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP," + " 7: WPA-PSK, 8: WPA-Auto-Personal\n" "[-w, --ieee-80211w]: MFP (optional: needs security type to be specified)\n" ": 0:Disable, 1:Optional, 2:Required.\n" "[-m, --bssid]: MAC address of the AP (BSSID).\n" From 7b8fb26cbfc35eb142438a957906d29a2f13c749 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 9 Apr 2024 11:21:16 +0200 Subject: [PATCH 2361/2402] [nrf fromtree] manifest: Update hal_nordic fix nrfx_uarte fixes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update hal nordic with fixes in the driver and MDK (EasyDMA UARTE MAXCNT). Signed-off-by: Krzysztof Chruściński (cherry picked from commit 3163f24a11887f203da0a2d7760f398cca05b612) --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 9fdaa6b2be8..39252a3dfa4 100644 --- a/west.yml +++ b/west.yml @@ -183,7 +183,7 @@ manifest: groups: - hal - name: hal_nordic - revision: fc2bab706f195c64d40016c9855b8acd7c235ded + revision: f8e4d73a78316ea9ef85f09f24a3a229e40c1a80 path: modules/hal/nordic groups: - hal From 2ace1ea2ce5019cb8a5024c73e4456c44b8fd885 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Thu, 4 Apr 2024 15:07:45 +0200 Subject: [PATCH 2362/2402] [nrf fromtree] drivers: serial: nrfx_uarte2: Clean error state on rx_enable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clean error state on re-enabling RX. If previous transmission ended with an error it should not impact next receiving session. Signed-off-by: Krzysztof Chruściński (cherry picked from commit d27842c9536e62fb21bc49bd425928e35d2af849) --- drivers/serial/uart_nrfx_uarte2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/serial/uart_nrfx_uarte2.c b/drivers/serial/uart_nrfx_uarte2.c index 0b8350714eb..ebe85448cea 100644 --- a/drivers/serial/uart_nrfx_uarte2.c +++ b/drivers/serial/uart_nrfx_uarte2.c @@ -506,6 +506,7 @@ static int api_rx_enable(const struct device *dev, uint8_t *buf, size_t len, int * flags are already known to the driver (e.g. if flushed data shall be * kept or not). */ + adata->err = 0; adata->en_rx_buf = buf; adata->en_rx_len = len; From 7b3063a1d9877af7ac2d25385793d0765452691c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 8 Apr 2024 17:23:01 +0200 Subject: [PATCH 2363/2402] [nrf fromtree] drivers: serial: uart_async_rx: Fix uart_async_rx_reset function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing fields clearing to the resetting function. Signed-off-by: Krzysztof Chruściński (cherry picked from commit 8f89013789a86a43941e4cf342d9cf7482b768fd) --- drivers/serial/uart_async_rx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/serial/uart_async_rx.c b/drivers/serial/uart_async_rx.c index 7c51a6cd251..8ee3fc54af1 100644 --- a/drivers/serial/uart_async_rx.c +++ b/drivers/serial/uart_async_rx.c @@ -126,6 +126,9 @@ void uart_async_rx_reset(struct uart_async_rx *rx_data) { rx_data->free_buf_cnt = rx_data->config->buf_cnt; rx_data->rd_idx = 0; + rx_data->rd_buf_idx = 0; + rx_data->drv_buf_idx = 0; + rx_data->pending_bytes = 0; for (uint8_t i = 0; i < rx_data->config->buf_cnt; i++) { buf_reset(get_buf(rx_data, i)); } From 0fb3fdcedb1db19f7899cf8a1a50c2d9651fbdaa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 9 Apr 2024 07:55:19 +0200 Subject: [PATCH 2364/2402] [nrf fromtree] tests: drivers: uart: uart_pm: Limit scope for nrf54l15 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some configurations which are not valid for nrf54l15. Mainly those which are using ENHANCED_POLL_OUT option which is not applicable for nrf54l15 because it has ENDTX_STOPTX short so PPI connection is not needed. Signed-off-by: Krzysztof Chruściński (cherry picked from commit c72b6a75ba17d1216dd2d389e66566989667fb2e) --- tests/drivers/uart/uart_pm/testcase.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tests/drivers/uart/uart_pm/testcase.yaml b/tests/drivers/uart/uart_pm/testcase.yaml index f90eed73949..355bb3c4282 100644 --- a/tests/drivers/uart/uart_pm/testcase.yaml +++ b/tests/drivers/uart/uart_pm/testcase.yaml @@ -5,6 +5,7 @@ common: harness: ztest platform_allow: - nrf52840dk/nrf52840 + - nrf54l15pdk/nrf54l15/cpuapp - nrf52_bsim harness_config: fixture: gpio_loopback @@ -24,6 +25,8 @@ tests: - CONFIG_UART_0_ENHANCED_POLL_OUT=n - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y extra_args: DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840.overlay;nrf_rx_disable.overlay" + platform_exclude: + - nrf54l15pdk/nrf54l15/cpuapp drivers.uart.pm.enhanced_poll: extra_configs: @@ -31,6 +34,8 @@ tests: - CONFIG_UART_ASYNC_API=n - CONFIG_UART_0_ENHANCED_POLL_OUT=y - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y + platform_exclude: + - nrf54l15pdk/nrf54l15/cpuapp drivers.uart.pm.int_driven: extra_configs: @@ -47,6 +52,8 @@ tests: - CONFIG_UART_ASYNC_API=n - CONFIG_UART_0_ENHANCED_POLL_OUT=y - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y + platform_exclude: + - nrf54l15pdk/nrf54l15/cpuapp drivers.uart.pm.async: extra_configs: @@ -69,3 +76,5 @@ tests: - CONFIG_NRFX_TIMER2=y - CONFIG_UART_0_ENHANCED_POLL_OUT=y - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y + platform_exclude: + - nrf54l15pdk/nrf54l15/cpuapp From f77e4e98908a2bc02cdbaa956f0a52b96e42c595 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 9 Apr 2024 09:59:26 +0200 Subject: [PATCH 2365/2402] [nrf fromtree] tests: drivers: uart: uart_pm: Add support for nrf54h20dk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add configuration for nrf54h20dk. Signed-off-by: Krzysztof Chruściński (cherry picked from commit 8e65ed94cb0563a6ec8ee651576a49ef0e380fb3) --- .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 31 +++++++++++++++++++ tests/drivers/uart/uart_pm/testcase.yaml | 5 +++ 2 files changed, 36 insertions(+) create mode 100644 tests/drivers/uart/uart_pm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay diff --git a/tests/drivers/uart/uart_pm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/uart/uart_pm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..d01ebce4c8a --- /dev/null +++ b/tests/drivers/uart/uart_pm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart135_default_alt: uart135_default_alt { + group1 { + psels = , + ; + }; + }; + + uart135_sleep_alt: uart135_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; + +dut: &uart135 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart135_default_alt>; + pinctrl-1 = <&uart135_sleep_alt>; + pinctrl-names = "default", "sleep"; + memory-regions = <&cpuapp_dma_region>; +}; diff --git a/tests/drivers/uart/uart_pm/testcase.yaml b/tests/drivers/uart/uart_pm/testcase.yaml index 355bb3c4282..c7c7b803442 100644 --- a/tests/drivers/uart/uart_pm/testcase.yaml +++ b/tests/drivers/uart/uart_pm/testcase.yaml @@ -6,6 +6,7 @@ common: platform_allow: - nrf52840dk/nrf52840 - nrf54l15pdk/nrf54l15/cpuapp + - nrf54h20dk/nrf54h20/cpuapp - nrf52_bsim harness_config: fixture: gpio_loopback @@ -27,6 +28,7 @@ tests: extra_args: DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840.overlay;nrf_rx_disable.overlay" platform_exclude: - nrf54l15pdk/nrf54l15/cpuapp + - nrf54h20dk/nrf54h20/cpuapp drivers.uart.pm.enhanced_poll: extra_configs: @@ -36,6 +38,7 @@ tests: - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y platform_exclude: - nrf54l15pdk/nrf54l15/cpuapp + - nrf54h20dk/nrf54h20/cpuapp drivers.uart.pm.int_driven: extra_configs: @@ -54,6 +57,7 @@ tests: - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y platform_exclude: - nrf54l15pdk/nrf54l15/cpuapp + - nrf54h20dk/nrf54h20/cpuapp drivers.uart.pm.async: extra_configs: @@ -78,3 +82,4 @@ tests: - CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=y platform_exclude: - nrf54l15pdk/nrf54l15/cpuapp + - nrf54h20dk/nrf54h20/cpuapp From e51431446b8c5b324a04beed4681529d64ccdef9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Thu, 4 Apr 2024 10:24:12 +0200 Subject: [PATCH 2366/2402] [nrf fromlist] tests: drivers: uart: async_api: Add nrf54h20 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add overlays for nrf54h20dk. Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71260 Signed-off-by: Krzysztof Chruściński (cherry picked from commit b10fd761ce2e5e847e4cfc132c2f4e828c75cb7a) --- .../boards/nrf54h20dk_nrf54h20_common.dtsi | 25 +++++++++++++++++++ .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 11 ++++++++ .../boards/nrf54h20dk_nrf54h20_cpurad.overlay | 11 ++++++++ 3 files changed, 47 insertions(+) create mode 100644 tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_common.dtsi create mode 100644 tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay create mode 100644 tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpurad.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_common.dtsi new file mode 100644 index 00000000000..172d75904e4 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_common.dtsi @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +&pinctrl { + uart135_default_alt: uart135_default_alt { + group1 { + psels = , + ; + }; + }; + + uart135_sleep_alt: uart135_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; + +dut: &uart135 { + status = "okay"; + pinctrl-0 = <&uart135_default_alt>; + pinctrl-1 = <&uart135_sleep_alt>; + pinctrl-names = "default", "sleep"; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..a8fe36d37bb --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include "nrf54h20dk_nrf54h20_common.dtsi" + +&cpuapp_dma_region { + status = "okay"; +}; + +&dut { + memory-regions = <&cpuapp_dma_region>; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpurad.overlay new file mode 100644 index 00000000000..32f95625201 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/nrf54h20dk_nrf54h20_cpurad.overlay @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include "nrf54h20dk_nrf54h20_common.dtsi" + +&cpurad_dma_region { + status = "okay"; +}; + +&dut { + memory-regions = <&cpurad_dma_region>; +}; From 16458fffeed93fdd45432c636ebf193b82041606 Mon Sep 17 00:00:00 2001 From: Bartosz Miller Date: Fri, 5 Apr 2024 11:51:47 +0200 Subject: [PATCH 2367/2402] [nrf fromtree] drivers: Extend coverage for UARTE driver Add more test cases for UARTE driver API Signed-off-by: Bartosz Miller (cherry picked from commit 211477f87401dfe57603e725e0332baf41cff082) --- .../uart/uart_elementary/CMakeLists.txt | 10 + tests/drivers/uart/uart_elementary/Kconfig | 11 + tests/drivers/uart/uart_elementary/README.txt | 13 + .../boards/nrf5340dk_nrf5340_cpuapp.conf | 1 + .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 32 ++ .../boards/nrf54h20dk_nrf54h20_common.dtsi | 37 ++ .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 3 + ...f54h20dk_nrf54h20_cpuapp_dual_uart.overlay | 56 +++ .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 31 ++ ...54l15pdk_nrf54l15_cpuapp_dual_uart.overlay | 51 +++ tests/drivers/uart/uart_elementary/prj.conf | 6 + tests/drivers/uart/uart_elementary/src/main.c | 322 ++++++++++++++++++ .../uart/uart_elementary/testcase.yaml | 35 ++ 13 files changed, 608 insertions(+) create mode 100644 tests/drivers/uart/uart_elementary/CMakeLists.txt create mode 100644 tests/drivers/uart/uart_elementary/Kconfig create mode 100644 tests/drivers/uart/uart_elementary/README.txt create mode 100644 tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.conf create mode 100644 tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.overlay create mode 100644 tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi create mode 100644 tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp.overlay create mode 100644 tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay create mode 100644 tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay create mode 100644 tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay create mode 100644 tests/drivers/uart/uart_elementary/prj.conf create mode 100644 tests/drivers/uart/uart_elementary/src/main.c create mode 100644 tests/drivers/uart/uart_elementary/testcase.yaml diff --git a/tests/drivers/uart/uart_elementary/CMakeLists.txt b/tests/drivers/uart/uart_elementary/CMakeLists.txt new file mode 100644 index 00000000000..59b31ee68a9 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(uart_high_level_api) + +target_sources(app PRIVATE + src/main.c + ) diff --git a/tests/drivers/uart/uart_elementary/Kconfig b/tests/drivers/uart/uart_elementary/Kconfig new file mode 100644 index 00000000000..aed523c5832 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/Kconfig @@ -0,0 +1,11 @@ +# UART test configuration options +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config DUAL_UART_TEST + bool "Enable dual UART test" + +config SETUP_MISMATCH_TEST + bool "Enable mismatched configuration in dual UART test" + +source "Kconfig.zephyr" diff --git a/tests/drivers/uart/uart_elementary/README.txt b/tests/drivers/uart/uart_elementary/README.txt new file mode 100644 index 00000000000..5af85beff46 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/README.txt @@ -0,0 +1,13 @@ +The purpose of this test is to validate basic UART driver functions, +that are not tested elsewhere. +UART interrupt mode is used for the tests purpose. + +Hardware setup required for these tests: +For single uart conviguration - UART0 TX connected to RX and CTS to RTS +For dual uart configuratiom - UART0 and UART1 TXs and RXs cross-connected + +These test cases cover: +- UART configuration, +- UART error check, +- UART callback setup, +- Dual UART transmission with matched and mismatched configurations diff --git a/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.conf b/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.conf new file mode 100644 index 00000000000..064e78b6f74 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.conf @@ -0,0 +1 @@ +CONFIG_UART_NRFX_UARTE_LEGACY_SHIM=n diff --git a/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.overlay new file mode 100644 index 00000000000..f98f3657f13 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +&pinctrl { + uart1_default_alt: uart1_default_alt { + group1 { + psels = , + , + , + ; + }; + }; + + uart1_sleep_alt: uart1_sleep_alt { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; +}; + +dut: &uart1 { + current-speed = <115200>; + compatible = "nordic,nrf-uarte"; + status = "okay"; + pinctrl-0 = <&uart1_default_alt>; + pinctrl-1 = <&uart1_sleep_alt>; + pinctrl-names = "default", "sleep"; + hw-flow-control; +}; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi new file mode 100644 index 00000000000..22d8378937c --- /dev/null +++ b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +&cpuapp_dma_region { + status="okay"; +}; + +&pinctrl { + uart135_default_alt: uart135_default_alt { + group1 { + psels = , + , + , + ; + }; + }; + + uart135_sleep_alt: uart135_sleep_alt { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; +}; + +dut: &uart135 { + status = "okay"; + memory-regions = <&cpuapp_dma_region>; + pinctrl-0 = <&uart135_default_alt>; + pinctrl-1 = <&uart135_sleep_alt>; + pinctrl-names = "default", "sleep"; + current-speed = <115200>; + hw-flow-control; + +}; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..f65b4dd3b0b --- /dev/null +++ b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include "nrf54h20dk_nrf54h20_common.dtsi" diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay new file mode 100644 index 00000000000..23c36ee8974 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include "nrf54h20dk_nrf54h20_common.dtsi" + + +&pinctrl { + uart135_default_alt: uart135_default_alt { + group1 { + psels = , + ; + }; + }; + + uart135_sleep_alt: uart135_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; + +dut: &uart135 { + status = "okay"; + memory-regions = <&cpuapp_dma_region>; + pinctrl-0 = <&uart135_default_alt>; + pinctrl-1 = <&uart135_sleep_alt>; + pinctrl-names = "default", "sleep"; + current-speed = <115200>; +}; + +&pinctrl { + uart137_default_alt: uart137_default_alt { + group1 { + psels = , + ; + }; + }; + + uart137_sleep_alt: uart137_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; + +dut_aux: &uart137 { + status = "okay"; + memory-regions = <&cpuapp_dma_region>; + pinctrl-0 = <&uart137_default_alt>; + pinctrl-1 = <&uart137_sleep_alt>; + pinctrl-names = "default", "sleep"; + current-speed = <115200>; +}; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay new file mode 100644 index 00000000000..cf481b7a161 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +&pinctrl { + uart21_default: uart21_default { + group1 { + psels = , + , + , + ; + }; + }; + + uart21_sleep: uart21_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; +}; + +dut: &uart21 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart21_default>; + pinctrl-1 = <&uart21_sleep>; + pinctrl-names = "default", "sleep"; + hw-flow-control; +}; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay new file mode 100644 index 00000000000..2031f7a2444 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +&pinctrl { + uart21_default: uart21_default { + group1 { + psels = , + ; + bias-pull-up; + }; + }; + + uart21_sleep: uart21_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + uart22_default: uart22_default { + group1 { + psels = , + ; + bias-pull-up; + }; + }; + + uart22_sleep: uart22_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; + +dut: &uart21 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart21_default>; + pinctrl-1 = <&uart21_sleep>; + pinctrl-names = "default", "sleep"; +}; + +dut_aux: &uart22 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart22_default>; + pinctrl-1 = <&uart22_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/tests/drivers/uart/uart_elementary/prj.conf b/tests/drivers/uart/uart_elementary/prj.conf new file mode 100644 index 00000000000..26c93d320a7 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/prj.conf @@ -0,0 +1,6 @@ +CONFIG_SERIAL=y +CONFIG_ZTEST=y +CONFIG_TEST_USERSPACE=y +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_UART_USE_RUNTIME_CONFIGURE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/tests/drivers/uart/uart_elementary/src/main.c b/tests/drivers/uart/uart_elementary/src/main.c new file mode 100644 index 00000000000..d7d85ee9542 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/src/main.c @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @addtogroup t_driver_uart + * @{ + * @defgroup t_uart_elementary test_uart_elementary + * @} + */ + +#include +#include + +#if DT_NODE_EXISTS(DT_NODELABEL(dut)) +#define UART_NODE DT_NODELABEL(dut) +#else +#define UART_NODE DT_CHOSEN(zephyr_console) +#endif + +#if DT_NODE_EXISTS(DT_NODELABEL(dut_aux)) +#define UART_NODE_AUX DT_NODELABEL(dut_aux) +#else +#define UART_NODE_AUX DT_CHOSEN(zephyr_console) +#endif + +#define SLEEP_TIME_US 1000 +#define TEST_BUFFER_LEN 10 + +static const struct device *const uart_dev = DEVICE_DT_GET(UART_NODE); + +const uint8_t test_pattern[TEST_BUFFER_LEN] = { 0x11, 0x12, 0x13, 0x14, 0x15, + 0x16, 0x17, 0x18, 0x19, 0x20 }; +static uint8_t test_buffer[TEST_BUFFER_LEN]; +static volatile uint8_t uart_error_counter; + +#if defined(CONFIG_DUAL_UART_TEST) +static const struct device *const uart_dev_aux = DEVICE_DT_GET(UART_NODE_AUX); +static uint8_t test_buffer_aux[TEST_BUFFER_LEN]; +static volatile uint8_t aux_uart_error; +#endif + +/* + * ISR for UART TX action + */ +static void uart_tx_interrupt_service(const struct device *dev, int *tx_byte_offset) +{ + uint8_t bytes_sent = 0; + uint8_t *tx_data_pointer = (uint8_t *)(test_pattern + *tx_byte_offset); + + if (*tx_byte_offset < TEST_BUFFER_LEN) { + bytes_sent = uart_fifo_fill(dev, tx_data_pointer, 1); + *tx_byte_offset += bytes_sent; + } else { + *tx_byte_offset = 0; + uart_irq_tx_disable(dev); + } +} + +/* + * ISR for UART RX action + */ +static void uart_rx_interrupt_service(const struct device *dev, uint8_t *receive_buffer_pointer, + int *rx_byte_offset) +{ + int rx_data_length = 0; + int bytes_received = 0; + + do { + rx_data_length = uart_fifo_read(dev, receive_buffer_pointer + *rx_byte_offset, + TEST_BUFFER_LEN); + bytes_received += rx_data_length; + } while (rx_data_length); + *rx_byte_offset += bytes_received; +} + +/* + * Callback function for MAIN UART interrupt based transmission test + */ +static void interrupt_driven_uart_callback_main_uart(const struct device *dev, void *user_data) +{ + int err; + static int tx_byte_offset; + static int rx_byte_offset; + + uart_irq_update(dev); + err = uart_err_check(dev); + if (err != 0) { + uart_error_counter++; + } + while (uart_irq_is_pending(dev)) { + if (uart_irq_rx_ready(dev)) { + uart_rx_interrupt_service(dev, (uint8_t *)user_data, &rx_byte_offset); + } + if (uart_irq_tx_ready(dev)) { + uart_tx_interrupt_service(dev, &tx_byte_offset); + } + } +} + +#if defined(CONFIG_DUAL_UART_TEST) +/* + * Callback function for AUX UART interrupt based transmission test + */ +static void interrupt_driven_uart_callback_aux_uart(const struct device *dev, void *user_data) +{ + int err; + static int tx_byte_offset_aux; + static int rx_byte_offset_aux; + + uart_irq_update(dev); + err = uart_err_check(dev); +#if !defined(CONFIG_COVERAGE) + /* This assetion will fail with coverge enabled + * When in coverage mode it has no impact on test case execution + */ + zassert_equal(err, 0, "Unexpected UART device: %s error: %d", dev->name, err); +#endif /* CONFIG_COVERAGE */ + while (uart_irq_is_pending(dev)) { + if (uart_irq_rx_ready(dev)) { + uart_rx_interrupt_service(dev, (uint8_t *)user_data, &rx_byte_offset_aux); + } + if (uart_irq_tx_ready(dev)) { + uart_tx_interrupt_service(dev, &tx_byte_offset_aux); + } + } +} +#endif /* CONFIG_DUAL_UART_TEST */ + +/* + * Test UART proper configuration call + */ +ZTEST(uart_elementary, test_uart_proper_configuration) +{ + Z_TEST_SKIP_IFDEF(CONFIG_DUAL_UART_TEST); + + int err; + struct uart_config test_expected_uart_config; + struct uart_config test_uart_config = { .baudrate = 115200, + .parity = UART_CFG_PARITY_NONE, + .stop_bits = UART_CFG_STOP_BITS_1, + .data_bits = UART_CFG_DATA_BITS_8, + .flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS }; + + err = uart_configure(uart_dev, &test_uart_config); + zassert_equal(err, 0, "'uart_configure' api call - unexpected error: %d", err); + + err = uart_config_get(uart_dev, &test_expected_uart_config); + zassert_equal(err, 0, "'uart_config_get' api call - unexpected error raised : %d", err); + + zassert_equal(test_uart_config.baudrate, test_expected_uart_config.baudrate, + "Set and actual UART config baudrate mismatch: %d != %d", + test_uart_config.baudrate, test_expected_uart_config.baudrate); + + zassert_equal(test_uart_config.parity, test_expected_uart_config.parity, + "Set and actual UART config parity mismatch: %d != %d", + test_uart_config.parity, test_expected_uart_config.parity); + + zassert_equal(test_uart_config.stop_bits, test_expected_uart_config.stop_bits, + "Set and actual UART config stop_bits mismatch: %d != %d", + test_uart_config.stop_bits, test_expected_uart_config.stop_bits); + + zassert_equal(test_uart_config.data_bits, test_expected_uart_config.data_bits, + "Set and actual UART config data_bits mismatch: %d != %d", + test_uart_config.data_bits, test_expected_uart_config.data_bits); + + zassert_equal(test_uart_config.flow_ctrl, test_expected_uart_config.flow_ctrl, + "Set and actual UART config flow_ctrl mismatch: %d != %d", + test_uart_config.flow_ctrl, test_expected_uart_config.flow_ctrl); +} + +/* + * Test UART improper configuration call + */ +ZTEST(uart_elementary, test_uart_improper_configuration) +{ + Z_TEST_SKIP_IFDEF(CONFIG_DUAL_UART_TEST); + + int err; + struct uart_config test_uart_config = { .baudrate = 115200, + .parity = 7, + .stop_bits = UART_CFG_STOP_BITS_1, + .data_bits = UART_CFG_DATA_BITS_8, + .flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS }; + + err = uart_configure(uart_dev, &test_uart_config); + zassert_not_equal( + err, 0, + "'uart_configure' with incorrect configuration havent't raised an error, err=%d", + err); +} + +#if !defined(CONFIG_DUAL_UART_TEST) +/* + * Test UART basic interrupt based transmission (with loopback) + */ +ZTEST(uart_elementary, test_uart_basic_transmission) +{ + int err; + struct uart_config test_uart_config = { .baudrate = 115200, + .parity = UART_CFG_PARITY_ODD, + .stop_bits = UART_CFG_STOP_BITS_1, + .data_bits = UART_CFG_DATA_BITS_8, + .flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS }; + + err = uart_configure(uart_dev, &test_uart_config); + zassert_equal(err, 0, "Unexpected error when configuring UART0: %d", err); + + err = uart_irq_callback_set(uart_dev, interrupt_driven_uart_callback_main_uart); + zassert_equal(err, 0, "Unexpected error when setting callback %d", err); + err = uart_irq_callback_user_data_set(uart_dev, interrupt_driven_uart_callback_main_uart, + (void *)test_buffer); + zassert_equal(err, 0, "Unexpected error when setting user data for callback %d", err); + uart_irq_err_enable(uart_dev); + uart_irq_rx_enable(uart_dev); + uart_irq_tx_enable(uart_dev); + + /* wait for the tramission to finish (no polling is intentional) */ + k_sleep(K_USEC(100 * SLEEP_TIME_US)); + + uart_irq_tx_disable(uart_dev); + uart_irq_rx_disable(uart_dev); + uart_irq_err_disable(uart_dev); + for (int index = 0; index < TEST_BUFFER_LEN; index++) { + zassert_equal(test_buffer[index], test_pattern[index], + "Recieived data byte %d does not match pattern 0x%x != 0x%x", index, + test_buffer[index], test_pattern[index]); + } +} +#else +/* + * Test UART interrupt based transmission between two ports + */ +ZTEST(uart_elementary, test_uart_dual_port_transmission) +{ + int err; + struct uart_config test_uart_config = { .baudrate = 115200, + .parity = UART_CFG_PARITY_NONE, + .stop_bits = UART_CFG_STOP_BITS_1, + .data_bits = UART_CFG_DATA_BITS_8, + .flow_ctrl = UART_CFG_FLOW_CTRL_NONE }; + +#if defined(CONFIG_SETUP_MISMATCH_TEST) + struct uart_config test_uart_config_aux = { .baudrate = 9600, + .parity = UART_CFG_PARITY_NONE, + .stop_bits = UART_CFG_STOP_BITS_1, + .data_bits = UART_CFG_DATA_BITS_8, + .flow_ctrl = UART_CFG_FLOW_CTRL_NONE }; +#endif + err = uart_configure(uart_dev, &test_uart_config); + zassert_equal(err, 0, "Unexpected error when configuring UART0: %d", err); + +#if defined(CONFIG_SETUP_MISMATCH_TEST) + err = uart_configure(uart_dev_aux, &test_uart_config_aux); +#else + err = uart_configure(uart_dev_aux, &test_uart_config); +#endif + + zassert_equal(err, 0, "Unexpected error when configuring UART1: %d", err); + + err = uart_irq_callback_set(uart_dev, interrupt_driven_uart_callback_main_uart); + zassert_equal(err, 0, "Unexpected error when setting callback for UART0 %d", err); + err = uart_irq_callback_user_data_set(uart_dev, interrupt_driven_uart_callback_main_uart, + (void *)test_buffer); + zassert_equal(err, 0, "Unexpected error when setting user data for UART0 callback %d", err); + + err = uart_irq_callback_set(uart_dev_aux, interrupt_driven_uart_callback_aux_uart); + zassert_equal(err, 0, "Unexpected error when setting callback for UART1 %d", err); + err = uart_irq_callback_user_data_set(uart_dev_aux, interrupt_driven_uart_callback_aux_uart, + (void *)test_buffer_aux); + zassert_equal(err, 0, "Unexpected error when setting user data for UART1 callback %d", err); + + uart_irq_err_enable(uart_dev); + uart_irq_err_enable(uart_dev_aux); + + uart_irq_tx_enable(uart_dev); + uart_irq_tx_enable(uart_dev_aux); + + uart_irq_rx_enable(uart_dev); + uart_irq_rx_enable(uart_dev_aux); + + /* wait for the tramission to finish (no polling is intentional) */ + k_sleep(K_USEC(100 * SLEEP_TIME_US)); + + uart_irq_tx_disable(uart_dev); + uart_irq_tx_disable(uart_dev_aux); + uart_irq_rx_disable(uart_dev); + uart_irq_rx_disable(uart_dev_aux); + uart_irq_err_disable(uart_dev); + uart_irq_err_disable(uart_dev_aux); + +#if defined(CONFIG_SETUP_MISMATCH_TEST) + zassert_not_equal(uart_error_counter, 0); +#else + for (int index = 0; index < TEST_BUFFER_LEN; index++) { + zassert_equal(test_buffer[index], test_pattern[index], + "UART0 recieived data byte %d does not match pattern 0x%x != 0x%x", + index, test_buffer[index], test_pattern[index]); + zassert_equal(test_buffer_aux[index], test_pattern[index], + "UART1 recieived data byte %d does not match pattern 0x%x != 0x%x", + index, test_buffer_aux[index], test_pattern[index]); + } +#endif /* CONFIG_SETUP_MISMATCH_TEST */ +} +#endif /* CONFIG_DUAL_UART_TEST */ + +/* + * Test setup + */ +void *test_setup(void) +{ + zassert_true(device_is_ready(uart_dev), "UART0 device is not ready"); +#if defined(CONFIG_DUAL_UART_TEST) + zassert_true(device_is_ready(uart_dev_aux), "UART1 device is not ready"); +#endif + + return NULL; +} + +ZTEST_SUITE(uart_elementary, NULL, test_setup, NULL, NULL, NULL); diff --git a/tests/drivers/uart/uart_elementary/testcase.yaml b/tests/drivers/uart/uart_elementary/testcase.yaml new file mode 100644 index 00000000000..7c06967e7ad --- /dev/null +++ b/tests/drivers/uart/uart_elementary/testcase.yaml @@ -0,0 +1,35 @@ +common: + tags: drivers uart + depends_on: gpio + harness: ztest + harness_config: + fixture: gpio_loopback +tests: + drivers.uart.uart_elementary: + filter: CONFIG_SERIAL_SUPPORT_INTERRUPT + platform_allow: + - nrf54h20dk/nrf54h20/cpuapp + - nrf54l15pdk/nrf54l15/cpuapp + - nrf5340dk/nrf5340/cpuapp + drivers.uart.uart_elementary_dual_nrf54h: + filter: CONFIG_SERIAL_SUPPORT_INTERRUPT + platform_allow: + - nrf54h20dk/nrf54h20/cpuapp + extra_args: DTC_OVERLAY_FILE="boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay" + extra_configs: + - CONFIG_DUAL_UART_TEST=y + drivers.uart.uart_elementary_dual_setup_mismatch_nrf54h: + filter: CONFIG_SERIAL_SUPPORT_INTERRUPT + platform_allow: + - nrf54h20dk/nrf54h20/cpuapp + extra_args: DTC_OVERLAY_FILE="boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay" + extra_configs: + - CONFIG_DUAL_UART_TEST=y + - CONFIG_SETUP_MISMATCH_TEST=y + drivers.uart.uart_elementary_dual_nrf54l: + filter: CONFIG_SERIAL_SUPPORT_INTERRUPT + platform_allow: + - nrf54l15pdk/nrf54l15/cpuapp + extra_args: DTC_OVERLAY_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay" + extra_configs: + - CONFIG_DUAL_UART_TEST=y From 6498044123c17077106d4ae9c2dc605e065cb85a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Wed, 17 Apr 2024 17:49:34 +0200 Subject: [PATCH 2368/2402] [nrf fromtree] tests: drivers: uart: uart_elementary: Fix RX handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rx_byte_offset was wrongly updated which could lead to test failures. Signed-off-by: Krzysztof Chruściński (cherry picked from commit b36550b8a509eb30b5524b56d4cf3fcea4c87dd2) --- tests/drivers/uart/uart_elementary/src/main.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tests/drivers/uart/uart_elementary/src/main.c b/tests/drivers/uart/uart_elementary/src/main.c index d7d85ee9542..1c4df3273a7 100644 --- a/tests/drivers/uart/uart_elementary/src/main.c +++ b/tests/drivers/uart/uart_elementary/src/main.c @@ -66,14 +66,12 @@ static void uart_rx_interrupt_service(const struct device *dev, uint8_t *receive int *rx_byte_offset) { int rx_data_length = 0; - int bytes_received = 0; do { rx_data_length = uart_fifo_read(dev, receive_buffer_pointer + *rx_byte_offset, TEST_BUFFER_LEN); - bytes_received += rx_data_length; + *rx_byte_offset += rx_data_length; } while (rx_data_length); - *rx_byte_offset += bytes_received; } /* From 51407a9bf1e44777d124bfe1f3b9c373c0832d16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 23 Jan 2024 11:46:02 +0100 Subject: [PATCH 2369/2402] [nrf fromtree] tests: drivers: spi: Add test for SPI master and slave MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add test which is using one SPI master and one SPI slave instance. There is already a loopback test for SPI master so this test is focusing on SPI slave API. Test requires 4 pairs of GPIO pins shortened together. One set of pins is used by SPI master and one for SPI slave. Signed-off-by: Krzysztof Chruściński (cherry picked from commit 1cd7f5150708ef066bbd679ac1f58f42a2b647be) --- tests/drivers/spi/spi_slave/CMakeLists.txt | 10 + .../boards/nrf52840dk_nrf52840.overlay | 67 +++ .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 73 +++ tests/drivers/spi/spi_slave/prj.conf | 6 + tests/drivers/spi/spi_slave/src/main.c | 452 ++++++++++++++++++ tests/drivers/spi/spi_slave/testcase.yaml | 10 + 6 files changed, 618 insertions(+) create mode 100644 tests/drivers/spi/spi_slave/CMakeLists.txt create mode 100644 tests/drivers/spi/spi_slave/boards/nrf52840dk_nrf52840.overlay create mode 100644 tests/drivers/spi/spi_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay create mode 100644 tests/drivers/spi/spi_slave/prj.conf create mode 100644 tests/drivers/spi/spi_slave/src/main.c create mode 100644 tests/drivers/spi/spi_slave/testcase.yaml diff --git a/tests/drivers/spi/spi_slave/CMakeLists.txt b/tests/drivers/spi/spi_slave/CMakeLists.txt new file mode 100644 index 00000000000..f9f7a6bdae4 --- /dev/null +++ b/tests/drivers/spi/spi_slave/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(spi_slave) + +FILE(GLOB app_sources src/*.c) + +target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/spi/spi_slave/boards/nrf52840dk_nrf52840.overlay b/tests/drivers/spi/spi_slave/boards/nrf52840dk_nrf52840.overlay new file mode 100644 index 00000000000..477917e0ca7 --- /dev/null +++ b/tests/drivers/spi/spi_slave/boards/nrf52840dk_nrf52840.overlay @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + spi3_default_alt: spi3_default_alt { + group1 { + psels = , + , + ; + }; + }; + + spi3_sleep_alt: spi3_sleep_alt { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spi1_default_alt: spi1_default_alt { + group1 { + psels = , + , + , + ; + }; + }; + + spi1_sleep_alt: spi1_sleep_alt { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + +}; + +&spi3 { + status = "okay"; + pinctrl-0 = <&spi3_default_alt>; + pinctrl-1 = <&spi3_sleep_alt>; + pinctrl-names = "default", "sleep"; + overrun-character = <0x00>; + cs-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + dut_spi_dt: test-spi-dev@0 { + compatible = "vnd,spi-device"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +dut_spis: &spi1 { + compatible = "nordic,nrf-spis"; + status = "okay"; + def-char = <0x00>; + pinctrl-0 = <&spi1_default_alt>; + pinctrl-1 = <&spi1_sleep_alt>; + pinctrl-names = "default", "sleep"; +}; diff --git a/tests/drivers/spi/spi_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay new file mode 100644 index 00000000000..d431f278337 --- /dev/null +++ b/tests/drivers/spi/spi_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + spi22_default_alt: spi22_default_alt { + group1 { + psels = , + , + ; + }; + }; + + spi22_sleep_alt: spi22_sleep_alt { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spi21_default_alt: spi21_default_alt { + group1 { + psels = , + , + , + ; + }; + }; + + spi21_sleep_alt: spi21_sleep_alt { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + +}; + +&gpio2 { + status = "okay"; +}; + +&spi22 { + status = "okay"; + pinctrl-0 = <&spi22_default_alt>; + pinctrl-1 = <&spi22_sleep_alt>; + pinctrl-names = "default", "sleep"; + overrun-character = <0x00>; + cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + dut_spi_dt: test-spi-dev@0 { + compatible = "vnd,spi-device"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +dut_spis: &spi21 { + compatible = "nordic,nrf-spis"; + status = "okay"; + def-char = <0x00>; + pinctrl-0 = <&spi21_default_alt>; + pinctrl-1 = <&spi21_sleep_alt>; + pinctrl-names = "default", "sleep"; + /delete-property/rx-delay-supported; + /delete-property/rx-delay; +}; diff --git a/tests/drivers/spi/spi_slave/prj.conf b/tests/drivers/spi/spi_slave/prj.conf new file mode 100644 index 00000000000..840a8f87d9a --- /dev/null +++ b/tests/drivers/spi/spi_slave/prj.conf @@ -0,0 +1,6 @@ +CONFIG_SPI=y +CONFIG_SPI_SLAVE=y +CONFIG_GPIO=y +CONFIG_POLL=y +CONFIG_SPI_ASYNC=y +CONFIG_ZTEST=y diff --git a/tests/drivers/spi/spi_slave/src/main.c b/tests/drivers/spi/spi_slave/src/main.c new file mode 100644 index 00000000000..7a6ca1b7545 --- /dev/null +++ b/tests/drivers/spi/spi_slave/src/main.c @@ -0,0 +1,452 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#define SPI_MODE (SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_LINES_SINGLE) +#define SPIM_OP (SPI_OP_MODE_MASTER | SPI_MODE) +#define SPIS_OP (SPI_OP_MODE_SLAVE | SPI_MODE) + +static struct spi_dt_spec spim = SPI_DT_SPEC_GET(DT_NODELABEL(dut_spi_dt), SPIM_OP, 0); +static const struct device *spis_dev = DEVICE_DT_GET(DT_NODELABEL(dut_spis)); +static const struct spi_config spis_config = { + .operation = SPIS_OP +}; + +static struct k_poll_signal async_sig = K_POLL_SIGNAL_INITIALIZER(async_sig); +static struct k_poll_event async_evt = + K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &async_sig); + +#define MEMORY_SECTION(node) \ + COND_CODE_1(DT_NODE_HAS_PROP(node, memory_regions), \ + (__attribute__((__section__( \ + LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(node, memory_regions)))))), \ + ()) + +static uint8_t spim_buffer[32] MEMORY_SECTION(DT_BUS(DT_NODELABEL(dut_spi_dt))); +static uint8_t spis_buffer[32] MEMORY_SECTION(DT_NODELABEL(dut_spis)); + +struct test_data { + struct k_work_delayable test_work; + struct k_sem sem; + int spim_alloc_idx; + int spis_alloc_idx; + struct spi_buf_set sets[4]; + struct spi_buf_set *mtx_set; + struct spi_buf_set *mrx_set; + struct spi_buf_set *stx_set; + struct spi_buf_set *srx_set; + struct spi_buf bufs[8]; +}; + +static struct test_data tdata; + +/* Allocate buffer from spim or spis space. */ +static uint8_t *buf_alloc(size_t len, bool spim) +{ + int *idx = spim ? &tdata.spim_alloc_idx : &tdata.spis_alloc_idx; + uint8_t *buf = spim ? spim_buffer : spis_buffer; + size_t total = spim ? sizeof(spim_buffer) : sizeof(spis_buffer); + uint8_t *rv; + + if (*idx + len > total) { + zassert_false(true); + + return NULL; + } + + rv = &buf[*idx]; + *idx += len; + + return rv; +} + +static void work_handler(struct k_work *work) +{ + struct k_work_delayable *dwork = k_work_delayable_from_work(work); + struct test_data *td = CONTAINER_OF(dwork, struct test_data, test_work); + int rv; + + rv = spi_transceive_dt(&spim, td->mtx_set, td->mrx_set); + if (rv == 0) { + k_sem_give(&td->sem); + } +} + +/** Copies data from buffers in the set to a single buffer which makes it easier + * to compare transmitted and received data. + * + * @param buf Output buffer. + * @param len Buffer length. + * @param set Set of buffers. + * + * @return Number of bytes copied. + */ +static int cpy_data(uint8_t *buf, size_t len, struct spi_buf_set *set) +{ + int idx = 0; + + for (size_t i = 0; i < set->count; i++) { + size_t l = set->buffers[i].len; + + if (len - idx >= l) { + memcpy(&buf[idx], set->buffers[i].buf, l); + idx += l; + } else { + return -1; + } + } + + return idx; +} + +/** Compare two sets. + * + * @param tx_set TX set. + * @param rx_set RX set. + * @param same_size True if it is expected to have the same amount of data in both sets. + * + * @return 0 if data is the same and other value indicate that check failed. + */ +static int check_buffers(struct spi_buf_set *tx_set, struct spi_buf_set *rx_set, bool same_size) +{ + static uint8_t tx_data[256]; + static uint8_t rx_data[256]; + int rx_len; + int tx_len; + + if (!tx_set || !rx_set) { + return 0; + } + + rx_len = cpy_data(rx_data, sizeof(rx_data), rx_set); + tx_len = cpy_data(tx_data, sizeof(tx_data), tx_set); + if (same_size && (rx_len != tx_len)) { + return -1; + } + + return memcmp(tx_data, rx_data, rx_len); +} + +/** Calculate expected number of received bytes by the slave. + * + * It is used to check if SPI API call for slave returns correct value. + * @param tx_set TX set. + * @param rx_set RX set. + * + * @return Expected amount of received bytes. + */ +static int slave_rx_len(struct spi_buf_set *tx_set, struct spi_buf_set *rx_set) +{ + size_t tx_len = 0; + size_t rx_len = 0; + + if (!tx_set || !rx_set) { + return 0; + } + + for (size_t i = 0; i < tx_set->count; i++) { + tx_len += tx_set->buffers[i].len; + } + + for (size_t i = 0; i < rx_set->count; i++) { + rx_len += rx_set->buffers[i].len; + } + + return MIN(rx_len, tx_len); +} + +/** Generic function which runs the test with sets prepared in the test data structure. */ +static void run_test(bool m_same_size, bool s_same_size, bool async) +{ + int rv; + int slave_rv; + int srx_len; + + rv = k_work_schedule(&tdata.test_work, K_MSEC(10)); + zassert_equal(rv, 1); + + if (!async) { + slave_rv = spi_transceive(spis_dev, &spis_config, tdata.stx_set, tdata.srx_set); + if (slave_rv == -ENOTSUP) { + ztest_test_skip(); + } + } else { + rv = spi_transceive_signal(spis_dev, &spis_config, tdata.stx_set, tdata.srx_set, + &async_sig); + if (rv == -ENOTSUP) { + ztest_test_skip(); + } + zassert_equal(rv, 0); + + /* Transfer not finished yet */ + rv = k_sem_take(&tdata.sem, K_NO_WAIT); + zassert_equal(rv, -EBUSY); + + rv = k_poll(&async_evt, 1, K_MSEC(200)); + zassert_false(rv, "one or more events are not ready"); + + slave_rv = async_evt.signal->result; + + /* Reinitializing for next call */ + async_evt.signal->signaled = 0U; + async_evt.state = K_POLL_STATE_NOT_READY; + } + + rv = k_sem_take(&tdata.sem, K_MSEC(100)); + zassert_equal(rv, 0); + + srx_len = slave_rx_len(tdata.mtx_set, tdata.srx_set); + + zassert_equal(slave_rv, srx_len, "Got: %d but expected:%d", slave_rv, srx_len); + + rv = check_buffers(tdata.mtx_set, tdata.srx_set, m_same_size); + zassert_equal(rv, 0); + + rv = check_buffers(tdata.stx_set, tdata.mrx_set, s_same_size); + zassert_equal(rv, 0); +} + +/** Basic test where slave and master have RX and TX sets which contains only one + * same size buffer. + */ +static void test_basic(bool async) +{ + size_t len = 16; + + for (int i = 0; i < 4; i++) { + tdata.bufs[i].buf = buf_alloc(len, i < 2); + tdata.bufs[i].len = len; + tdata.sets[i].buffers = &tdata.bufs[i]; + tdata.sets[i].count = 1; + } + + tdata.mtx_set = &tdata.sets[0]; + tdata.mrx_set = &tdata.sets[1]; + tdata.stx_set = &tdata.sets[2]; + tdata.srx_set = &tdata.sets[3]; + + run_test(true, true, async); +} + +ZTEST(spi_slave, test_basic) +{ + test_basic(false); +} + +ZTEST(spi_slave, test_basic_async) +{ + test_basic(true); +} + +/** Setup a transfer where RX buffer on master and slave are shorter than + * TX buffers. RX buffers shall contain beginning of TX data and last TX + * bytes that did not fit in the RX buffers shall be lost. + */ +static void test_short_rx(bool async) +{ + size_t len = 16; + + tdata.bufs[0].buf = buf_alloc(len, true); + tdata.bufs[0].len = len; + tdata.bufs[1].buf = buf_alloc(len, true); + tdata.bufs[1].len = len - 3; /* RX buffer */ + tdata.bufs[2].buf = buf_alloc(len, false); + tdata.bufs[2].len = len; + tdata.bufs[3].buf = buf_alloc(len, false); + tdata.bufs[3].len = len - 4; /* RX buffer */ + + for (int i = 0; i < 4; i++) { + tdata.sets[i].buffers = &tdata.bufs[i]; + tdata.sets[i].count = 1; + } + + tdata.mtx_set = &tdata.sets[0]; + tdata.mrx_set = &tdata.sets[1]; + tdata.stx_set = &tdata.sets[2]; + tdata.srx_set = &tdata.sets[3]; + + run_test(false, false, async); +} + +ZTEST(spi_slave, test_short_rx) +{ + test_short_rx(false); +} + +ZTEST(spi_slave, test_short_rx_async) +{ + test_short_rx(true); +} + +/** Test where only master transmits. */ +static void test_only_tx(bool async) +{ + size_t len = 16; + + /* MTX buffer */ + tdata.bufs[0].buf = buf_alloc(len, true); + tdata.bufs[0].len = len; + tdata.sets[0].buffers = &tdata.bufs[0]; + tdata.sets[0].count = 1; + tdata.mtx_set = &tdata.sets[0]; + tdata.mrx_set = NULL; + + /* STX buffer */ + tdata.bufs[1].buf = buf_alloc(len, false); + tdata.bufs[1].len = len; + tdata.sets[1].buffers = &tdata.bufs[1]; + tdata.sets[1].count = 1; + tdata.srx_set = &tdata.sets[1]; + tdata.stx_set = NULL; + + run_test(true, true, async); +} + +ZTEST(spi_slave, test_only_tx) +{ + test_only_tx(false); +} + +ZTEST(spi_slave, test_only_tx_async) +{ + test_only_tx(true); +} + +/** Test where only master transmits and slave receives in chunks. */ +static void test_only_tx_in_chunks(bool async) +{ + size_t len1 = 7; + size_t len2 = 8; + + /* MTX buffer */ + tdata.bufs[0].buf = buf_alloc(len1 + len2, true); + tdata.bufs[0].len = len1 + len2; + tdata.sets[0].buffers = &tdata.bufs[0]; + tdata.sets[0].count = 1; + tdata.mtx_set = &tdata.sets[0]; + tdata.mrx_set = NULL; + + /* STX buffer */ + tdata.bufs[1].buf = buf_alloc(len1, false); + tdata.bufs[1].len = len1; + tdata.bufs[2].buf = buf_alloc(len2, false); + tdata.bufs[2].len = len2; + tdata.sets[1].buffers = &tdata.bufs[1]; + tdata.sets[1].count = 2; + tdata.srx_set = &tdata.sets[1]; + tdata.stx_set = NULL; + + run_test(true, true, async); +} + +ZTEST(spi_slave, test_only_tx_in_chunks) +{ + test_only_tx_in_chunks(false); +} + +ZTEST(spi_slave, test_only_tx_in_chunks_async) +{ + test_only_tx_in_chunks(true); +} + +/** Test where only slave transmits. */ +static void test_only_rx(bool async) +{ + size_t len = 16; + + /* MTX buffer */ + tdata.bufs[0].buf = buf_alloc(len, true); + tdata.bufs[0].len = len; + tdata.sets[0].buffers = &tdata.bufs[0]; + tdata.sets[0].count = 1; + tdata.mrx_set = &tdata.sets[0]; + tdata.mtx_set = NULL; + + /* STX buffer */ + tdata.bufs[1].buf = buf_alloc(len, false); + tdata.bufs[1].len = len; + tdata.sets[1].buffers = &tdata.bufs[1]; + tdata.sets[1].count = 1; + tdata.stx_set = &tdata.sets[1]; + tdata.srx_set = NULL; + + run_test(true, true, async); +} + +ZTEST(spi_slave, test_only_rx) +{ + test_only_rx(false); +} + +ZTEST(spi_slave, test_only_rx_async) +{ + test_only_rx(true); +} + +/** Test where only slave transmits in chunks. */ +static void test_only_rx_in_chunks(bool async) +{ + size_t len1 = 7; + size_t len2 = 9; + + /* MTX buffer */ + tdata.bufs[0].buf = buf_alloc(len1 + len2, true); + tdata.bufs[0].len = len1 + len2; + tdata.sets[0].buffers = &tdata.bufs[0]; + tdata.sets[0].count = 1; + tdata.mrx_set = &tdata.sets[0]; + tdata.mtx_set = NULL; + + /* STX buffer */ + tdata.bufs[1].buf = buf_alloc(len1, false); + tdata.bufs[1].len = len1; + tdata.bufs[2].buf = buf_alloc(len2, false); + tdata.bufs[2].len = len2; + tdata.sets[1].buffers = &tdata.bufs[1]; + tdata.sets[1].count = 2; + tdata.stx_set = &tdata.sets[1]; + tdata.srx_set = NULL; + + run_test(true, true, async); +} + +ZTEST(spi_slave, test_only_rx_in_chunks) +{ + test_only_rx_in_chunks(false); +} + +ZTEST(spi_slave, test_only_rx_in_chunks_async) +{ + test_only_rx_in_chunks(true); +} + +static void before(void *not_used) +{ + ARG_UNUSED(not_used); + + memset(&tdata, 0, sizeof(tdata)); + for (size_t i = 0; i < sizeof(spim_buffer); i++) { + spim_buffer[i] = (uint8_t)i; + } + for (size_t i = 0; i < sizeof(spis_buffer); i++) { + spis_buffer[i] = (uint8_t)(i + 0x80); + } + + k_work_init_delayable(&tdata.test_work, work_handler); + k_sem_init(&tdata.sem, 0, 1); +} + +static void *suite_setup(void) +{ + return NULL; +} + +ZTEST_SUITE(spi_slave, NULL, suite_setup, before, NULL, NULL); diff --git a/tests/drivers/spi/spi_slave/testcase.yaml b/tests/drivers/spi/spi_slave/testcase.yaml new file mode 100644 index 00000000000..1b5a46cc9e6 --- /dev/null +++ b/tests/drivers/spi/spi_slave/testcase.yaml @@ -0,0 +1,10 @@ +tests: + drivers.spi_slave.api: + depends_on: spi + tags: drivers spi + harness: ztest + harness_config: + fixture: gpio_spi_loopback + platform_allow: nrf52840dk/nrf52840 nrf54l15pdk/nrf54l15/cpuapp + integration_platforms: + - nrf52840dk/nrf52840 From 1c5cc9de2a2d14f0ff4cbddf595d9705c40ca3d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Wed, 3 Apr 2024 12:15:46 +0200 Subject: [PATCH 2370/2402] [nrf fromtree] dts: common: nordic: nrf54: Add rx-delay property to SPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add rx-delay property to all SPI nodes. Signed-off-by: Krzysztof Chruściński (cherry picked from commit 8acc6a961a895b91fcfc06a71ba58dfd836b8a45) --- .../nordic/nrf54l15_cpuapp_peripherals.dtsi | 10 ++++++++++ dts/common/nordic/nrf54h20.dtsi | 20 +++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi index eb161844841..3e4d3641069 100644 --- a/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi +++ b/dts/arm/nordic/nrf54l15_cpuapp_peripherals.dtsi @@ -24,6 +24,8 @@ spi00: spi@4a000 { interrupts = <74 NRF_DEFAULT_IRQ_PRIORITY>; max-frequency = ; easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; status = "disabled"; }; @@ -124,6 +126,8 @@ spi20: spi@c6000 { interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>; max-frequency = ; easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; status = "disabled"; }; @@ -159,6 +163,8 @@ spi21: spi@c7000 { interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>; max-frequency = ; easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; status = "disabled"; }; @@ -194,6 +200,8 @@ spi22: spi@c8000 { interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>; max-frequency = ; easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; status = "disabled"; }; @@ -391,6 +399,8 @@ spi30: spi@104000 { interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>; max-frequency = ; easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; status = "disabled"; }; diff --git a/dts/common/nordic/nrf54h20.dtsi b/dts/common/nordic/nrf54h20.dtsi index b8456d719c0..7d5a64d0a83 100644 --- a/dts/common/nordic/nrf54h20.dtsi +++ b/dts/common/nordic/nrf54h20.dtsi @@ -369,6 +369,8 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; }; uart120: uart@8e6000 { @@ -387,6 +389,8 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; }; cpuppr_vpr: vpr@908000 { @@ -644,6 +648,8 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; }; uart130: uart@9a5000 { @@ -672,6 +678,8 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; }; uart131: uart@9a6000 { @@ -734,6 +742,8 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; }; uart132: uart@9b5000 { @@ -762,6 +772,8 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; }; uart133: uart@9b6000 { @@ -824,6 +836,8 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; }; uart134: uart@9c5000 { @@ -852,6 +866,8 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; }; uart135: uart@9c6000 { @@ -914,6 +930,8 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; }; uart136: uart@9d5000 { @@ -942,6 +960,8 @@ max-frequency = ; #address-cells = <1>; #size-cells = <0>; + rx-delay-supported; + rx-delay = <1>; }; uart137: uart@9d6000 { From 0bdee3c8a8c20f5f7b48437885f430ec4ea9ae7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Tue, 2 Apr 2024 14:04:18 +0200 Subject: [PATCH 2371/2402] [nrf fromtree] tests: drivers: spi: spi_loopback_test: Add nrf54h20dk support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for nrf54h20dk for the SPI loopback test. Signed-off-by: Krzysztof Chruściński (cherry picked from commit 1e6a2a00e236e6ed33e27f33a79bf9c44db81d89) --- .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 tests/drivers/spi/spi_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/spi/spi_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..5ab0e84eeaa --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + spi130_default: spi130_default { + group1 { + psels = , + , + ; + }; + }; + + spi130_sleep: spi130_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; + +&spi130 { + status = "okay"; + pinctrl-0 = <&spi130_default>; + pinctrl-1 = <&spi130_sleep>; + pinctrl-names = "default", "sleep"; + overrun-character = <0x00>; + memory-regions = <&cpuapp_dma_region>; + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = ; + }; + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = ; + }; +}; From 4aa01ece24d527919eb1148471a07616103ced97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Fri, 19 Apr 2024 08:49:02 +0200 Subject: [PATCH 2372/2402] [nrf fromlist] tests: drivers: spi: spi_slave: Add nrf54h20dk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add configuration for nrf54h20dk to the test. Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/71677 Signed-off-by: Krzysztof Chruściński (cherry picked from commit 5aeae3b35c79025d473a8ff0a9c3880f78fd5de2) --- .../boards/nrf54h20dk_nrf54h20_common.dtsi | 79 +++++++++++++++++++ .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 14 ++++ .../boards/nrf54h20dk_nrf54h20_cpurad.overlay | 14 ++++ tests/drivers/spi/spi_slave/src/main.c | 1 + tests/drivers/spi/spi_slave/testcase.yaml | 4 +- 5 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_common.dtsi create mode 100644 tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay create mode 100644 tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpurad.overlay diff --git a/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_common.dtsi new file mode 100644 index 00000000000..0a9425cc2f9 --- /dev/null +++ b/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_common.dtsi @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + spi130_default_alt: spi130_default_alt { + group1 { + psels = , + , + ; + }; + }; + + spi130_sleep_alt: spi130_sleep_alt { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spis131_default_alt: spis131_default_alt { + group1 { + psels = , + , + , + ; + }; + }; + + spis131_sleep_alt: spis131_sleep_alt { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + +}; + +&gpio0 { + status = "okay"; +}; + +&gpiote130 { + status = "okay"; + owned-channels = <7>; +}; + +dut_spi: &spi130 { + compatible = "nordic,nrf-spim"; + status = "okay"; + pinctrl-0 = <&spi130_default_alt>; + pinctrl-1 = <&spi130_sleep_alt>; + pinctrl-names = "default", "sleep"; + overrun-character = <0x00>; + cs-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + dut_spi_dt: test-spi-dev@0 { + compatible = "vnd,spi-device"; + reg = <0>; + spi-max-frequency = <500000>; + }; +}; + +dut_spis: &spi131 { + compatible = "nordic,nrf-spis"; + status = "okay"; + def-char = <0x00>; + pinctrl-0 = <&spis131_default_alt>; + pinctrl-1 = <&spis131_sleep_alt>; + pinctrl-names = "default", "sleep"; + /delete-property/rx-delay-supported; + /delete-property/rx-delay; +}; diff --git a/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..ff337ebdec4 --- /dev/null +++ b/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "nrf54h20dk_nrf54h20_common.dtsi" + +&dut_spi { + memory-regions = <&cpuapp_dma_region>; +}; + +&dut_spis { + memory-regions = <&cpuapp_dma_region>; +}; diff --git a/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpurad.overlay new file mode 100644 index 00000000000..936bd5b15d5 --- /dev/null +++ b/tests/drivers/spi/spi_slave/boards/nrf54h20dk_nrf54h20_cpurad.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "nrf54h20dk_nrf54h20_common.dtsi" + +&dut_spi { + memory-regions = <&cpurad_dma_region>; +}; + +&dut_spis { + memory-regions = <&cpurad_dma_region>; +}; diff --git a/tests/drivers/spi/spi_slave/src/main.c b/tests/drivers/spi/spi_slave/src/main.c index 7a6ca1b7545..5f441480c12 100644 --- a/tests/drivers/spi/spi_slave/src/main.c +++ b/tests/drivers/spi/spi_slave/src/main.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #define SPI_MODE (SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_LINES_SINGLE) diff --git a/tests/drivers/spi/spi_slave/testcase.yaml b/tests/drivers/spi/spi_slave/testcase.yaml index 1b5a46cc9e6..c38b3e72952 100644 --- a/tests/drivers/spi/spi_slave/testcase.yaml +++ b/tests/drivers/spi/spi_slave/testcase.yaml @@ -5,6 +5,8 @@ tests: harness: ztest harness_config: fixture: gpio_spi_loopback - platform_allow: nrf52840dk/nrf52840 nrf54l15pdk/nrf54l15/cpuapp + platform_allow: | + nrf52840dk/nrf52840 nrf54l15pdk/nrf54l15/cpuapp nrf54h20dk/nrf54h20/cpuapp + nrf54h20dk/nrf54h20/cpurad integration_platforms: - nrf52840dk/nrf52840 From 1f655d6c493df7116203c75ca1ba603633242da3 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Mon, 15 Apr 2024 14:12:27 +0200 Subject: [PATCH 2373/2402] [nrf fromtree] tests: drivers: timer: nrf_grtc_timer: add nRF54H20 target GRTC peripheral is present on nRF54H20, so the tests should be executed on this target as well. Signed-off-by: Nikodem Kastelik (cherry picked from commit 1f9bec7f0844784cc790cac20b85d098294ecbfa) --- tests/drivers/timer/nrf_grtc_timer/testcase.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/drivers/timer/nrf_grtc_timer/testcase.yaml b/tests/drivers/timer/nrf_grtc_timer/testcase.yaml index f611a518a70..00ac1ed584b 100644 --- a/tests/drivers/timer/nrf_grtc_timer/testcase.yaml +++ b/tests/drivers/timer/nrf_grtc_timer/testcase.yaml @@ -1,4 +1,7 @@ tests: drivers.timer.nrf_grtc_timer: tags: drivers - platform_allow: nrf54l15pdk/nrf54l15/cpuapp + platform_allow: + - nrf54l15pdk/nrf54l15/cpuapp + - nrf54h20dk/nrf54h20/cpuapp + - nrf54h20dk/nrf54h20/cpurad From ab8d66dd12917eb4d2e757f6bdb8b44bed5e556d Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Fri, 12 Apr 2024 13:41:15 +0200 Subject: [PATCH 2374/2402] [nrf fromtree] soc: nordic: add nRF54 TWIS HAS_HW symbols Add HAS_HW symbols for TWIS instances found on nRF54H20 and nRF54L15 devices. Signed-off-by: Nikodem Kastelik (cherry picked from commit 03cb84ffda13cce818180e2f827c0462f8d75197) --- soc/nordic/common/Kconfig.peripherals | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/soc/nordic/common/Kconfig.peripherals b/soc/nordic/common/Kconfig.peripherals index 817002f7282..f0adc82d44a 100644 --- a/soc/nordic/common/Kconfig.peripherals +++ b/soc/nordic/common/Kconfig.peripherals @@ -530,6 +530,42 @@ config HAS_HW_NRF_TWIS2 config HAS_HW_NRF_TWIS3 def_bool $(dt_nodelabel_enabled_with_compat,i2c3,$(DT_COMPAT_NORDIC_NRF_TWIS)) +config HAS_HW_NRF_TWIS20 + def_bool $(dt_nodelabel_enabled_with_compat,i2c20,$(DT_COMPAT_NORDIC_NRF_TWIS)) + +config HAS_HW_NRF_TWIS21 + def_bool $(dt_nodelabel_enabled_with_compat,i2c21,$(DT_COMPAT_NORDIC_NRF_TWIS)) + +config HAS_HW_NRF_TWIS22 + def_bool $(dt_nodelabel_enabled_with_compat,i2c22,$(DT_COMPAT_NORDIC_NRF_TWIS)) + +config HAS_HW_NRF_TWIS30 + def_bool $(dt_nodelabel_enabled_with_compat,i2c30,$(DT_COMPAT_NORDIC_NRF_TWIS)) + +config HAS_HW_NRF_TWIS130 + def_bool $(dt_nodelabel_enabled_with_compat,i2c130,$(DT_COMPAT_NORDIC_NRF_TWIS)) + +config HAS_HW_NRF_TWIS131 + def_bool $(dt_nodelabel_enabled_with_compat,i2c131,$(DT_COMPAT_NORDIC_NRF_TWIS)) + +config HAS_HW_NRF_TWIS132 + def_bool $(dt_nodelabel_enabled_with_compat,i2c132,$(DT_COMPAT_NORDIC_NRF_TWIS)) + +config HAS_HW_NRF_TWIS133 + def_bool $(dt_nodelabel_enabled_with_compat,i2c133,$(DT_COMPAT_NORDIC_NRF_TWIS)) + +config HAS_HW_NRF_TWIS134 + def_bool $(dt_nodelabel_enabled_with_compat,i2c134,$(DT_COMPAT_NORDIC_NRF_TWIS)) + +config HAS_HW_NRF_TWIS135 + def_bool $(dt_nodelabel_enabled_with_compat,i2c135,$(DT_COMPAT_NORDIC_NRF_TWIS)) + +config HAS_HW_NRF_TWIS136 + def_bool $(dt_nodelabel_enabled_with_compat,i2c136,$(DT_COMPAT_NORDIC_NRF_TWIS)) + +config HAS_HW_NRF_TWIS137 + def_bool $(dt_nodelabel_enabled_with_compat,i2c137,$(DT_COMPAT_NORDIC_NRF_TWIS)) + config HAS_HW_NRF_UART0 def_bool $(dt_nodelabel_enabled_with_compat,uart0,$(DT_COMPAT_NORDIC_NRF_UART)) From 0301be3da47b8ec638e3851ef78a07208729df51 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Fri, 12 Apr 2024 14:13:31 +0200 Subject: [PATCH 2375/2402] [nrf fromtree] tests: boards: nrf: add i2c driver test with TWIS slave Test defines a lopback between i2c driver master and nrfx TWIS slave to verify their functional correctness. Signed-off-by: Nikodem Kastelik (cherry picked from commit 01ea0f2d7e433c0a9e9eb639f60987b075e07870) --- tests/boards/nrf/i2c/i2c_slave/CMakeLists.txt | 10 ++ .../i2c_slave/boards/nrf52840dk_nrf52840.conf | 1 + .../boards/nrf52840dk_nrf52840.overlay | 60 ++++++++ .../boards/nrf5340dk_nrf5340_cpuapp.conf | 1 + .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 58 +++++++ .../boards/nrf54h20dk_nrf54h20_cpuapp.conf | 1 + .../boards/nrf54h20dk_nrf54h20_cpuapp.overlay | 63 ++++++++ .../boards/nrf54l15pdk_nrf54l15_cpuapp.conf | 1 + .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 59 +++++++ tests/boards/nrf/i2c/i2c_slave/prj.conf | 2 + tests/boards/nrf/i2c/i2c_slave/src/main.c | 145 ++++++++++++++++++ tests/boards/nrf/i2c/i2c_slave/testcase.yaml | 12 ++ 12 files changed, 413 insertions(+) create mode 100644 tests/boards/nrf/i2c/i2c_slave/CMakeLists.txt create mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.conf create mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay create mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.conf create mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.overlay create mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.conf create mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay create mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.conf create mode 100644 tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay create mode 100644 tests/boards/nrf/i2c/i2c_slave/prj.conf create mode 100644 tests/boards/nrf/i2c/i2c_slave/src/main.c create mode 100644 tests/boards/nrf/i2c/i2c_slave/testcase.yaml diff --git a/tests/boards/nrf/i2c/i2c_slave/CMakeLists.txt b/tests/boards/nrf/i2c/i2c_slave/CMakeLists.txt new file mode 100644 index 00000000000..43130d6a07d --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(i2c_slave) + +FILE(GLOB app_sources src/*.c) + +target_sources(app PRIVATE ${app_sources}) diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.conf b/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.conf new file mode 100644 index 00000000000..e79ad7a8126 --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.conf @@ -0,0 +1 @@ +CONFIG_NRFX_TWIS1=y diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay new file mode 100644 index 00000000000..8628731faf4 --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay @@ -0,0 +1,60 @@ +/ { + aliases { + i2c-slave = &i2c1; + }; +}; + +&pinctrl { + i2c0_default_alt: i2c0_default_alt { + group1 { + psels = , + ; + }; + }; + + i2c0_sleep_alt: i2c0_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c1_default_alt: i2c1_default_alt { + group1 { +/* Temporary workaround as it is currently not possible + * to configure pins for TWIS with pinctrl. */ + psels = , + ; + bias-pull-up; + }; + }; + + i2c1_sleep_alt: i2c1_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; + +&i2c0 { + compatible = "nordic,nrf-twim"; + status = "okay"; + pinctrl-0 = <&i2c0_default_alt>; + pinctrl-1 = <&i2c0_sleep_alt>; + pinctrl-names = "default", "sleep"; + sensor: sensor@54 { + reg = <0x54>; + }; +}; + + +&i2c1 { + compatible = "nordic,nrf-twis"; + status = "okay"; + pinctrl-0 = <&i2c1_default_alt>; + pinctrl-1 = <&i2c1_sleep_alt>; + pinctrl-names = "default", "sleep"; +}; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.conf b/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.conf new file mode 100644 index 00000000000..a7bedf1f04b --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.conf @@ -0,0 +1 @@ +CONFIG_NRFX_TWIS2=y diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.overlay new file mode 100644 index 00000000000..d473a04f85c --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -0,0 +1,58 @@ +/ { + aliases { + i2c-slave = &i2c2; + }; +}; + +&pinctrl { + i2c1_default_alt: i2c1_default_alt { + group1 { + psels = , + ; + }; + }; + + i2c1_sleep_alt: i2c1_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c2_default_alt: i2c2_default_alt { + group1 { +/* Temporary workaround as it is currently not possible + * to configure pins for TWIS with pinctrl. */ + psels = , + ; + bias-pull-up; + }; + }; + + i2c2_sleep_alt: i2c2_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; + +&i2c1 { + compatible = "nordic,nrf-twim"; + status = "okay"; + pinctrl-0 = <&i2c1_default_alt>; + pinctrl-1 = <&i2c1_sleep_alt>; + pinctrl-names = "default", "sleep"; + sensor: sensor@54 { + reg = <0x54>; + }; +}; + +&i2c2 { + compatible = "nordic,nrf-twis"; + pinctrl-0 = <&i2c2_default_alt>; + pinctrl-1 = <&i2c2_sleep_alt>; + pinctrl-names = "default", "sleep"; +}; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.conf b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.conf new file mode 100644 index 00000000000..157e0a11f72 --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.conf @@ -0,0 +1 @@ +CONFIG_NRFX_TWIS131=y diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..73d1d85cf45 --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -0,0 +1,63 @@ +/ { + aliases { + i2c-slave = &i2c131; + }; +}; + +&pinctrl { + i2c130_default_alt: i2c130_default_alt { + group1 { + psels = , + ; + }; + }; + + i2c130_sleep_alt: i2c130_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c131_default_alt: i2c131_default_alt { + group1 { +/* Temporary workaround as it is currently not possible + * to configure pins for TWIS with pinctrl. */ + psels = , + ; + bias-pull-up; + }; + }; + + i2c131_sleep_alt: i2c131_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; + +&i2c130 { + compatible = "nordic,nrf-twim"; + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c130_default_alt>; + pinctrl-1 = <&i2c130_sleep_alt>; + pinctrl-names = "default", "sleep"; + memory-regions = <&cpuapp_dma_region>; + sensor: sensor@54 { + reg = <0x54>; + }; +}; + +&i2c131 { + compatible = "nordic,nrf-twis"; + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c131_default_alt>; + pinctrl-1 = <&i2c131_sleep_alt>; + pinctrl-names = "default", "sleep"; + memory-regions = <&cpuapp_dma_region>; +}; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.conf b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.conf new file mode 100644 index 00000000000..b01af3b36a7 --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.conf @@ -0,0 +1 @@ +CONFIG_NRFX_TWIS22=y diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay new file mode 100644 index 00000000000..d60e42659ee --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay @@ -0,0 +1,59 @@ +/ { + aliases { + i2c-slave = &i2c22; + }; +}; + +&pinctrl { + i2c21_default_alt: i2c21_default_alt { + group1 { + psels = , + ; + }; + }; + + i2c21_sleep_alt: i2c21_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c22_default_alt: i2c22_default_alt { + group1 { +/* Temporary workaround as it is currently not possible + * to configure pins for TWIS with pinctrl. */ + psels = , + ; + bias-pull-up; + }; + }; + + i2c22_sleep_alt: i2c22_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; + +&i2c21 { + compatible = "nordic,nrf-twim"; + status = "okay"; + pinctrl-0 = <&i2c21_default_alt>; + pinctrl-1 = <&i2c21_sleep_alt>; + pinctrl-names = "default", "sleep"; + sensor: sensor@54 { + reg = <0x54>; + }; +}; + +&i2c22 { + compatible = "nordic,nrf-twis"; + status = "okay"; + pinctrl-0 = <&i2c22_default_alt>; + pinctrl-1 = <&i2c22_sleep_alt>; + pinctrl-names = "default", "sleep"; +}; diff --git a/tests/boards/nrf/i2c/i2c_slave/prj.conf b/tests/boards/nrf/i2c/i2c_slave/prj.conf new file mode 100644 index 00000000000..4b19609ecfb --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/prj.conf @@ -0,0 +1,2 @@ +CONFIG_I2C=y +CONFIG_ZTEST=y diff --git a/tests/boards/nrf/i2c/i2c_slave/src/main.c b/tests/boards/nrf/i2c/i2c_slave/src/main.c new file mode 100644 index 00000000000..1de4b16bc2c --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/src/main.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#if CONFIG_NRFX_TWIS1 +#define I2C_S_INSTANCE 1 +#elif CONFIG_NRFX_TWIS2 +#define I2C_S_INSTANCE 2 +#elif CONFIG_NRFX_TWIS22 +#define I2C_S_INSTANCE 22 +#elif CONFIG_NRFX_TWIS131 +#define I2C_S_INSTANCE 131 +#else +#error "TWIS instance not enabled or not supported" +#endif + +#define NODE_SENSOR DT_NODELABEL(sensor) +#define NODE_TWIS DT_ALIAS(i2c_slave) + +#define TWIS_MEMORY_SECTION \ + COND_CODE_1(DT_NODE_HAS_PROP(NODE_TWIS, memory_regions), \ + (__attribute__((__section__( \ + LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(NODE_TWIS, memory_regions)))))), \ + ()) + +#define TEST_DATA_SIZE 6 +static const uint8_t msg[TEST_DATA_SIZE] = "Nordic"; +static const nrfx_twis_t twis = NRFX_TWIS_INSTANCE(I2C_S_INSTANCE); + +static uint8_t i2c_slave_buffer[TEST_DATA_SIZE] TWIS_MEMORY_SECTION; +static uint8_t i2c_master_buffer[TEST_DATA_SIZE]; +struct i2c_api_twis_fixture { + const struct device *dev; + uint8_t addr; + uint8_t *const master_buffer; + uint8_t *const slave_buffer; +}; + +void i2s_slave_handler(nrfx_twis_evt_t const *p_event) +{ + switch (p_event->type) { + case NRFX_TWIS_EVT_READ_REQ: + nrfx_twis_tx_prepare(&twis, i2c_slave_buffer, TEST_DATA_SIZE); + TC_PRINT("TWIS event: read request\n"); + break; + case NRFX_TWIS_EVT_READ_DONE: + TC_PRINT("TWIS event: read done\n"); + break; + case NRFX_TWIS_EVT_WRITE_REQ: + nrfx_twis_rx_prepare(&twis, i2c_slave_buffer, TEST_DATA_SIZE); + TC_PRINT("TWIS event: write request\n"); + break; + case NRFX_TWIS_EVT_WRITE_DONE: + zassert_mem_equal(i2c_slave_buffer, msg, TEST_DATA_SIZE); + TC_PRINT("TWIS event: write done\n"); + break; + default: + TC_PRINT("TWIS event: %d\n", p_event->type); + break; + } +} + +static void *test_setup(void) +{ + static struct i2c_api_twis_fixture fixture = { + .dev = DEVICE_DT_GET(DT_BUS(NODE_SENSOR)), + .addr = DT_REG_ADDR(NODE_SENSOR), + .master_buffer = i2c_master_buffer, + .slave_buffer = i2c_slave_buffer, + }; + const nrfx_twis_config_t config = { + .addr = {fixture.addr, 0}, + .skip_gpio_cfg = true, + .skip_psel_cfg = true, + }; + int ret; + + zassert_equal(NRFX_SUCCESS, nrfx_twis_init(&twis, &config, i2s_slave_handler), + "TWIS initialization failed"); + + PINCTRL_DT_DEFINE(NODE_TWIS); + ret = pinctrl_apply_state(PINCTRL_DT_DEV_CONFIG_GET(NODE_TWIS), PINCTRL_STATE_DEFAULT); + zassert_ok(ret); + + IRQ_CONNECT(DT_IRQN(NODE_TWIS), DT_IRQ(NODE_TWIS, priority), + NRFX_TWIS_INST_HANDLER_GET(I2C_S_INSTANCE), NULL, 0); + + nrfx_twis_enable(&twis); + + return &fixture; +} + +static void cleanup_buffers(void *argc) +{ + struct i2c_api_twis_fixture *fixture = (struct i2c_api_twis_fixture *)argc; + + memset(fixture->slave_buffer, 0, TEST_DATA_SIZE); + memset(fixture->master_buffer, 0, TEST_DATA_SIZE); +} + +ZTEST_USER_F(i2c_api_twis, test_i2c_read_write) +{ + int ret = i2c_write_read(fixture->dev, fixture->addr, msg, TEST_DATA_SIZE, + fixture->master_buffer, TEST_DATA_SIZE); + + zassert_ok(ret); + zassert_mem_equal(fixture->master_buffer, msg, TEST_DATA_SIZE); +} + +ZTEST_USER_F(i2c_api_twis, test_i2c_read) +{ + /* Prepare slave data */ + strncpy(fixture->slave_buffer, msg, TEST_DATA_SIZE); + zassert_mem_equal(fixture->slave_buffer, msg, TEST_DATA_SIZE); + + int ret = i2c_read(fixture->dev, fixture->master_buffer, TEST_DATA_SIZE, fixture->addr); + + zassert_ok(ret); + zassert_mem_equal(fixture->master_buffer, msg, TEST_DATA_SIZE); +} + +ZTEST_USER_F(i2c_api_twis, test_i2c_write) +{ + int ret = i2c_write(fixture->dev, msg, TEST_DATA_SIZE, fixture->addr); + + zassert_ok(ret); + zassert_mem_equal(fixture->slave_buffer, msg, TEST_DATA_SIZE); +} + +ZTEST_SUITE(i2c_api_twis, NULL, test_setup, NULL, cleanup_buffers, NULL); diff --git a/tests/boards/nrf/i2c/i2c_slave/testcase.yaml b/tests/boards/nrf/i2c/i2c_slave/testcase.yaml new file mode 100644 index 00000000000..1309b60146e --- /dev/null +++ b/tests/boards/nrf/i2c/i2c_slave/testcase.yaml @@ -0,0 +1,12 @@ +tests: + boards.nrf.i2c.i2c_slave: + depends_on: i2c + tags: drivers i2c + harness: ztest + harness_config: + fixture: i2c_loopback + platform_allow: nrf52840dk/nrf52840 nrf5340dk/nrf5340/cpuapp nrf54l15pdk/nrf54l15/cpuapp + integration_platforms: + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf54l15pdk/nrf54l15/cpuapp From 0b1ebb5e018ef7829582eebc815d9eea35e58263 Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Wed, 17 Apr 2024 08:12:58 +0200 Subject: [PATCH 2376/2402] [nrf fromtree] soc: nordic: Fix undefined z_arm_platform_init Fixes #71511 Follow-up to #70977 Update the approach by moving the `PROVIDE` directive to a separate linker script added using `zephyr_linker_sources()`. This makes the change more likely to propagate to existing samples which are using CONFIG_CUSTOM_LINKER_SCRIPT. Signed-off-by: Grzegorz Swiderski (cherry picked from commit f16b33e902d4bae8c0a72c0c568f9c33ce6f6209) --- soc/nordic/CMakeLists.txt | 4 +++- soc/nordic/common/CMakeLists.txt | 2 ++ soc/nordic/{linker.ld => common/arm_platform_init.ld} | 11 ----------- soc/nordic/common/vpr/CMakeLists.txt | 2 ++ 4 files changed, 7 insertions(+), 12 deletions(-) rename soc/nordic/{linker.ld => common/arm_platform_init.ld} (52%) diff --git a/soc/nordic/CMakeLists.txt b/soc/nordic/CMakeLists.txt index 6dae6e97fb2..9797d2e717a 100644 --- a/soc/nordic/CMakeLists.txt +++ b/soc/nordic/CMakeLists.txt @@ -2,7 +2,9 @@ zephyr_library() -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "SoC Linker script") +if(CONFIG_ARM) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "SoC Linker script") +endif() zephyr_library_sources( validate_base_addresses.c diff --git a/soc/nordic/common/CMakeLists.txt b/soc/nordic/common/CMakeLists.txt index b574cafc0c7..805113f53d6 100644 --- a/soc/nordic/common/CMakeLists.txt +++ b/soc/nordic/common/CMakeLists.txt @@ -3,6 +3,8 @@ add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr) +zephyr_linker_sources_ifdef(CONFIG_ARM SECTIONS arm_platform_init.ld) + zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) zephyr_include_directories(.) diff --git a/soc/nordic/linker.ld b/soc/nordic/common/arm_platform_init.ld similarity index 52% rename from soc/nordic/linker.ld rename to soc/nordic/common/arm_platform_init.ld index c8dbb426592..9773ada3dcf 100644 --- a/soc/nordic/linker.ld +++ b/soc/nordic/common/arm_platform_init.ld @@ -4,16 +4,5 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_ARM) -#include - /* Let SystemInit() be called in place of z_arm_platform_init() by default. */ PROVIDE(z_arm_platform_init = SystemInit); - -#elif defined(CONFIG_RISCV) -#include - -#else -#error Unsupported architecture - -#endif diff --git a/soc/nordic/common/vpr/CMakeLists.txt b/soc/nordic/common/vpr/CMakeLists.txt index 3849a3fdc94..d418954eebc 100644 --- a/soc/nordic/common/vpr/CMakeLists.txt +++ b/soc/nordic/common/vpr/CMakeLists.txt @@ -4,3 +4,5 @@ zephyr_include_directories(.) zephyr_library_sources(soc_idle.c soc_irq.S soc_irq.c vector.S) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") From 7ad93e14a3375bab75c75f3e79655d8f83fabc84 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20G=C5=82=C4=85b?= Date: Fri, 12 Apr 2024 12:26:27 +0200 Subject: [PATCH 2377/2402] [nrf fromtree] tests: drivers: spi: Add negative test cases MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extend test coverage by adding tests that check invalid use of the SPI API. Signed-off-by: Sebastian Głąb (cherry picked from commit 5e4bbd5c7c37b55b9b6df63ba7165f0b8ff6506c) --- .../spi/spi_error_cases/CMakeLists.txt | 10 + .../boards/nrf52840dk_nrf52840.overlay | 72 +++++ .../nrf54l15pdk_nrf54l15_cpuapp.overlay | 78 ++++++ tests/drivers/spi/spi_error_cases/prj.conf | 7 + tests/drivers/spi/spi_error_cases/src/main.c | 263 ++++++++++++++++++ .../drivers/spi/spi_error_cases/testcase.yaml | 12 + 6 files changed, 442 insertions(+) create mode 100644 tests/drivers/spi/spi_error_cases/CMakeLists.txt create mode 100644 tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay create mode 100644 tests/drivers/spi/spi_error_cases/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay create mode 100644 tests/drivers/spi/spi_error_cases/prj.conf create mode 100644 tests/drivers/spi/spi_error_cases/src/main.c create mode 100644 tests/drivers/spi/spi_error_cases/testcase.yaml diff --git a/tests/drivers/spi/spi_error_cases/CMakeLists.txt b/tests/drivers/spi/spi_error_cases/CMakeLists.txt new file mode 100644 index 00000000000..2ac4bdbef4d --- /dev/null +++ b/tests/drivers/spi/spi_error_cases/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(spi_error_cases) + +FILE(GLOB app_sources src/*.c) + +target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay b/tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay new file mode 100644 index 00000000000..183d6da9967 --- /dev/null +++ b/tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + spi3_default_alt: spi3_default_alt { + group1 { + psels = , + , + ; + }; + }; + + spi3_sleep_alt: spi3_sleep_alt { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spi1_default_alt: spi1_default_alt { + group1 { + psels = , + , + , + ; + }; + }; + + spi1_sleep_alt: spi1_sleep_alt { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + +}; + +dut_spi: &spi3 { + status = "okay"; + pinctrl-0 = <&spi3_default_alt>; + pinctrl-1 = <&spi3_sleep_alt>; + pinctrl-names = "default", "sleep"; + overrun-character = <0x00>; + cs-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + dut_spi_dt: test-spi-dev@0 { + compatible = "vnd,spi-device"; + reg = <0>; + spi-max-frequency = <200000>; + }; +}; + +dut_spis: &spi1 { + compatible = "nordic,nrf-spis"; + status = "okay"; + def-char = <0x00>; + pinctrl-0 = <&spi1_default_alt>; + pinctrl-1 = <&spi1_sleep_alt>; + pinctrl-names = "default", "sleep"; + dut_spis_dt: test-spis-dev@0 { + compatible = "vnd,spi-device"; + reg = <0>; + spi-max-frequency = <200000>; + }; +}; diff --git a/tests/drivers/spi/spi_error_cases/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_error_cases/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay new file mode 100644 index 00000000000..2a0394c3f60 --- /dev/null +++ b/tests/drivers/spi/spi_error_cases/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + spi22_default_alt: spi22_default_alt { + group1 { + psels = , + , + ; + }; + }; + + spi22_sleep_alt: spi22_sleep_alt { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spi21_default_alt: spi21_default_alt { + group1 { + psels = , + , + , + ; + }; + }; + + spi21_sleep_alt: spi21_sleep_alt { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + +}; + +&gpio2 { + status = "okay"; +}; + +dut_spi: &spi22 { + status = "okay"; + pinctrl-0 = <&spi22_default_alt>; + pinctrl-1 = <&spi22_sleep_alt>; + pinctrl-names = "default", "sleep"; + overrun-character = <0x00>; + cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + dut_spi_dt: test-spi-dev@0 { + compatible = "vnd,spi-device"; + reg = <0>; + spi-max-frequency = <200000>; + }; +}; + +dut_spis: &spi21 { + compatible = "nordic,nrf-spis"; + status = "okay"; + def-char = <0x00>; + pinctrl-0 = <&spi21_default_alt>; + pinctrl-1 = <&spi21_sleep_alt>; + pinctrl-names = "default", "sleep"; + dut_spis_dt: test-spis-dev@0 { + compatible = "vnd,spi-device"; + reg = <0>; + spi-max-frequency = <200000>; + }; + /delete-property/rx-delay-supported; + /delete-property/rx-delay; +}; diff --git a/tests/drivers/spi/spi_error_cases/prj.conf b/tests/drivers/spi/spi_error_cases/prj.conf new file mode 100644 index 00000000000..1161e03f477 --- /dev/null +++ b/tests/drivers/spi/spi_error_cases/prj.conf @@ -0,0 +1,7 @@ +CONFIG_SPI=y +CONFIG_SPI_SLAVE=y +CONFIG_GPIO=y +CONFIG_POLL=y +CONFIG_SPI_ASYNC=y +CONFIG_SPI_EXTENDED_MODES=y +CONFIG_ZTEST=y diff --git a/tests/drivers/spi/spi_error_cases/src/main.c b/tests/drivers/spi/spi_error_cases/src/main.c new file mode 100644 index 00000000000..0b44812db84 --- /dev/null +++ b/tests/drivers/spi/spi_error_cases/src/main.c @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#define SPI_MODE (SPI_MODE_CPOL | SPI_WORD_SET(8) | SPI_LINES_SINGLE) +#define SPIM_OP (SPI_OP_MODE_MASTER | SPI_MODE) +#define SPIS_OP (SPI_OP_MODE_SLAVE | SPI_MODE) + +static struct spi_dt_spec spim = SPI_DT_SPEC_GET(DT_NODELABEL(dut_spi_dt), SPIM_OP, 0); +static struct spi_dt_spec spis = SPI_DT_SPEC_GET(DT_NODELABEL(dut_spis_dt), SPIS_OP, 0); + +#define MEMORY_SECTION(node) \ + COND_CODE_1(DT_NODE_HAS_PROP(node, memory_regions), \ + (__attribute__((__section__( \ + LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(node, memory_regions)))))), \ + ()) + +static uint8_t spim_buffer[32] MEMORY_SECTION(DT_NODELABEL(dut_spi)); +static uint8_t spis_buffer[32] MEMORY_SECTION(DT_NODELABEL(dut_spis)); + +struct test_data { + int spim_alloc_idx; + int spis_alloc_idx; + struct spi_buf_set sets[4]; + struct spi_buf_set *mtx_set; + struct spi_buf_set *mrx_set; + struct spi_buf_set *stx_set; + struct spi_buf_set *srx_set; + struct spi_buf bufs[4]; +}; + +static struct test_data tdata; + +/* Allocate buffer from spim or spis space. */ +static uint8_t *buf_alloc(size_t len, bool spim) +{ + int *idx = spim ? &tdata.spim_alloc_idx : &tdata.spis_alloc_idx; + uint8_t *buf = spim ? spim_buffer : spis_buffer; + size_t total = spim ? sizeof(spim_buffer) : sizeof(spis_buffer); + uint8_t *rv; + + if (*idx + len > total) { + zassert_false(true); + + return NULL; + } + + rv = &buf[*idx]; + *idx += len; + + return rv; +} + +ZTEST(spi_error_cases, test_SPI_HALF_DUPLEX_not_supported) +{ + int rv; + int slave_rv; + struct spi_dt_spec spim_invalid = spim; + struct spi_dt_spec spis_invalid = spis; + + spim_invalid.config.operation |= SPI_HALF_DUPLEX; + spis_invalid.config.operation |= SPI_HALF_DUPLEX; + + rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(rv, -ENOTSUP, "Got %d instead", rv); + slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -ENOTSUP, "Got %d instead", slave_rv); +} + +ZTEST(spi_error_cases, test_SPI_OP_MODE_invalid) +{ + int rv; + int slave_rv; + struct spi_dt_spec spim_invalid = spim; + struct spi_dt_spec spis_invalid = spis; + + spim_invalid.config.operation |= SPI_OP_MODE_SLAVE; + spis_invalid.config.operation &= !SPI_OP_MODE_SLAVE; + + /* Check that Operation Mode Slave on spim is not supported */ + rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(rv, -EINVAL, "Got %d instead", rv); + /* Check that Operation Mode Master on spis is not supported */ + slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); +} + +ZTEST(spi_error_cases, test_SPI_MODE_LOOP_not_supported) +{ + int rv; + int slave_rv; + struct spi_dt_spec spim_invalid = spim; + struct spi_dt_spec spis_invalid = spis; + + spim_invalid.config.operation |= SPI_MODE_LOOP; + spis_invalid.config.operation |= SPI_MODE_LOOP; + + rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(rv, -EINVAL, "Got %d instead", rv); + slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); +} + +ZTEST(spi_error_cases, test_only_SPI_LINES_SINGLE_supported) +{ + int rv; + int slave_rv; + struct spi_dt_spec spim_invalid = spim; + struct spi_dt_spec spis_invalid = spis; + + spim_invalid.config.operation |= SPI_LINES_DUAL; + spis_invalid.config.operation |= SPI_LINES_DUAL; + + rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(rv, -EINVAL, "Got %d instead", rv); + slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); + + spim_invalid = spim; + spis_invalid = spis; + spim_invalid.config.operation |= SPI_LINES_QUAD; + spis_invalid.config.operation |= SPI_LINES_QUAD; + + rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(rv, -EINVAL, "Got %d instead", rv); + slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); + + spim_invalid = spim; + spis_invalid = spis; + spim_invalid.config.operation |= SPI_LINES_OCTAL; + spis_invalid.config.operation |= SPI_LINES_OCTAL; + + rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(rv, -EINVAL, "Got %d instead", rv); + slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); +} + +ZTEST(spi_error_cases, test_only_8BIT_supported) +{ + int rv; + int slave_rv; + struct spi_dt_spec spim_invalid = spim; + struct spi_dt_spec spis_invalid = spis; + + spim_invalid.config.operation |= SPI_WORD_SET(16); + spis_invalid.config.operation |= SPI_WORD_SET(16); + + rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(rv, -EINVAL, "Got %d instead", rv); + slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); +} + +ZTEST(spi_error_cases, test_unsupported_frequency) +{ + int rv; + struct spi_dt_spec spim_invalid = spim; + + spim_invalid.config.frequency = 124999; + + rv = spi_transceive_dt(&spim_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(rv, -EINVAL, "Got %d instead", rv); +} + +ZTEST(spi_error_cases, test_CS_unsupported_on_slave) +{ + int slave_rv; + struct spi_dt_spec spis_invalid = spis; + struct gpio_dt_spec test_gpio = { DEVICE_DT_GET(DT_NODELABEL(gpio1)), 10, GPIO_ACTIVE_LOW }; + + spis_invalid.config.cs.gpio = test_gpio; + + slave_rv = spi_transceive_dt(&spis_invalid, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); +} + +ZTEST(spi_error_cases, test_spis_scattered_tx_buf_not_supported) +{ + int slave_rv; + + tdata.sets[2].count = 2; + slave_rv = spi_transceive_dt(&spis, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -ENOTSUP, "Got %d instead", slave_rv); +} + +ZTEST(spi_error_cases, test_spis_scattered_rx_buf_not_supported) +{ + int slave_rv; + + tdata.sets[3].count = 2; + slave_rv = spi_transceive_dt(&spis, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -ENOTSUP, "Got %d instead", slave_rv); +} + +ZTEST(spi_error_cases, test_spis_tx_buf_too_big) +{ + int slave_rv; + + tdata.bufs[2].len = (size_t)65536; + slave_rv = spi_transceive_dt(&spis, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); +} + +ZTEST(spi_error_cases, test_spis_rx_buf_too_big) +{ + int slave_rv; + + tdata.bufs[3].len = (size_t)65536; + slave_rv = spi_transceive_dt(&spis, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -EINVAL, "Got %d instead", slave_rv); +} + +ZTEST(spi_error_cases, test_spis_tx_buf_not_in_ram) +{ + int slave_rv; + + tdata.bufs[2].buf = (void *)0x12345678; + slave_rv = spi_transceive_dt(&spis, tdata.stx_set, tdata.srx_set); + zassert_equal(slave_rv, -ENOTSUP, "Got %d instead", slave_rv); +} + +static void before(void *not_used) +{ + ARG_UNUSED(not_used); + size_t len = 16; + + memset(&tdata, 0, sizeof(tdata)); + for (size_t i = 0; i < sizeof(spim_buffer); i++) { + spim_buffer[i] = (uint8_t)i; + } + for (size_t i = 0; i < sizeof(spis_buffer); i++) { + spis_buffer[i] = (uint8_t)i; + } + + for (int i = 0; i < 4; i++) { + tdata.bufs[i].buf = buf_alloc(len, i < 2); + tdata.bufs[i].len = len; + tdata.sets[i].buffers = &tdata.bufs[i]; + tdata.sets[i].count = 1; + } + + tdata.mtx_set = &tdata.sets[0]; + tdata.mrx_set = &tdata.sets[1]; + tdata.stx_set = &tdata.sets[2]; + tdata.srx_set = &tdata.sets[3]; +} + +static void *suite_setup(void) +{ + return NULL; +} + +ZTEST_SUITE(spi_error_cases, NULL, suite_setup, before, NULL, NULL); diff --git a/tests/drivers/spi/spi_error_cases/testcase.yaml b/tests/drivers/spi/spi_error_cases/testcase.yaml new file mode 100644 index 00000000000..9c7e40167e7 --- /dev/null +++ b/tests/drivers/spi/spi_error_cases/testcase.yaml @@ -0,0 +1,12 @@ +tests: + drivers.spi.spi_error_cases: + depends_on: spi + tags: drivers spi + harness: ztest + harness_config: + fixture: gpio_spi_loopback + platform_allow: + - nrf52840dk/nrf52840 + - nrf54l15pdk/nrf54l15/cpuapp + integration_platforms: + - nrf52840dk/nrf52840 From 56e3a0abf4376831b1c0e0aa933eb794d154b8b6 Mon Sep 17 00:00:00 2001 From: Dominik Ermel Date: Tue, 23 Apr 2024 16:21:08 +0000 Subject: [PATCH 2378/2402] [nrf fromtree] mcumgr/img_mgmt: Fix zcbor logic in os_mgmt_bootloader_info There have been to problems with the code where zcbor_bool_encode has been fed value instead of expected pointer and the result of previous zcbor_encode operations has not been taken to evaluate value of ok status. The change also replaces usage of #if IS_ENABLED with #ifdef, as IS_ENABLED should not be used outside if(). Signed-off-by: Dominik Ermel (cherry picked from commit c007e717d4bda353a8147c90fbe21456aa44b4c8) --- subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c index 29e222d1de9..9fc02f81661 100644 --- a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c +++ b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c @@ -469,9 +469,9 @@ os_mgmt_bootloader_info(struct smp_streamer *ctxt) ok = zcbor_tstr_put_lit(zse, "mode") && zcbor_int32_put(zse, BOOTLOADER_MODE); -#if IS_ENABLED(CONFIG_MCUBOOT_BOOTLOADER_NO_DOWNGRADE) - ok = zcbor_tstr_put_lit(zse, "no-downgrade") && - zcbor_bool_encode(zse, true); +#ifdef CONFIG_MCUBOOT_BOOTLOADER_NO_DOWNGRADE + ok = ok && zcbor_tstr_put_lit(zse, "no-downgrade") && + zcbor_bool_encode(zse, &(bool){true}); #endif } else { return OS_MGMT_ERR_QUERY_YIELDS_NO_ANSWER; From 2e73c44e405972528b8dfd4c6c37f44e047398b0 Mon Sep 17 00:00:00 2001 From: Bartosz Miller Date: Thu, 18 Apr 2024 10:57:05 +0200 Subject: [PATCH 2379/2402] [nrf fromtree] tests: drivers: uart: uart_elementary: Fix 'config_mismatch' test case UART error may be reported with random timing from either UART in configuration mismatch case. The test case is now aligned to such behaviour. Signed-off-by: Bartosz Miller (cherry picked from commit 3147243c8f6be6856339bcf33a23a21bf97b8ab2) --- tests/drivers/uart/uart_elementary/src/main.c | 15 ++++++++------- tests/drivers/uart/uart_elementary/testcase.yaml | 8 ++++++++ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/tests/drivers/uart/uart_elementary/src/main.c b/tests/drivers/uart/uart_elementary/src/main.c index 1c4df3273a7..df8c7b54b10 100644 --- a/tests/drivers/uart/uart_elementary/src/main.c +++ b/tests/drivers/uart/uart_elementary/src/main.c @@ -40,6 +40,7 @@ static volatile uint8_t uart_error_counter; static const struct device *const uart_dev_aux = DEVICE_DT_GET(UART_NODE_AUX); static uint8_t test_buffer_aux[TEST_BUFFER_LEN]; static volatile uint8_t aux_uart_error; +static volatile uint8_t aux_uart_error_counter; #endif /* @@ -110,12 +111,9 @@ static void interrupt_driven_uart_callback_aux_uart(const struct device *dev, vo uart_irq_update(dev); err = uart_err_check(dev); -#if !defined(CONFIG_COVERAGE) - /* This assetion will fail with coverge enabled - * When in coverage mode it has no impact on test case execution - */ - zassert_equal(err, 0, "Unexpected UART device: %s error: %d", dev->name, err); -#endif /* CONFIG_COVERAGE */ + if (err != 0) { + aux_uart_error_counter++; + } while (uart_irq_is_pending(dev)) { if (uart_irq_rx_ready(dev)) { uart_rx_interrupt_service(dev, (uint8_t *)user_data, &rx_byte_offset_aux); @@ -290,7 +288,10 @@ ZTEST(uart_elementary, test_uart_dual_port_transmission) uart_irq_err_disable(uart_dev_aux); #if defined(CONFIG_SETUP_MISMATCH_TEST) - zassert_not_equal(uart_error_counter, 0); + TC_PRINT("Mismatched configuration test\n"); + zassert_not_equal(uart_error_counter + aux_uart_error_counter, 0, + "UART configuration mismatch error not detected"); + #else for (int index = 0; index < TEST_BUFFER_LEN; index++) { zassert_equal(test_buffer[index], test_pattern[index], diff --git a/tests/drivers/uart/uart_elementary/testcase.yaml b/tests/drivers/uart/uart_elementary/testcase.yaml index 7c06967e7ad..d8aa90d0536 100644 --- a/tests/drivers/uart/uart_elementary/testcase.yaml +++ b/tests/drivers/uart/uart_elementary/testcase.yaml @@ -33,3 +33,11 @@ tests: extra_args: DTC_OVERLAY_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay" extra_configs: - CONFIG_DUAL_UART_TEST=y + drivers.uart.uart_elementary_dual_setup_mismatch_nrf54l: + filter: CONFIG_SERIAL_SUPPORT_INTERRUPT + platform_allow: + - nrf54l15pdk/nrf54l15/cpuapp + extra_args: DTC_OVERLAY_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_dual_uart.overlay" + extra_configs: + - CONFIG_DUAL_UART_TEST=y + - CONFIG_SETUP_MISMATCH_TEST=y From c39f4b1e097bc52d353e6425b157ba99af129ed5 Mon Sep 17 00:00:00 2001 From: Carles Cufi Date: Fri, 30 Nov 2018 14:07:56 +0100 Subject: [PATCH 2380/2402] [nrf noup] ci: NCS-specific CI tweaks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Necessary changes for NCS CI. - Add a Jenkinsfile - Add a commit-tags workflow: This enables sauce tag checking in sdk-zephyr - compliance.yml: Disable check for merge commits, since we have upmerges downstream. Also, since in the code we refer to Kconfig symbols that are defined in the sdk-nrf repository, the Kconfig checks (Kconfig, KconfigBasic and KconfigBasicNoModules) will not pass so exclude them. Also, disable any maintainers-related checks - scripts/gitlint: Extend the max commit line lengths for Gitlint to account for sauce tags Signed-off-by: Carles Cufi Signed-off-by: Dominik Ermel Signed-off-by: Martí Bolívar Signed-off-by: Vinayak Kariappa Chettimada Signed-off-by: Krishna T Signed-off-by: Dominik Ermel Signed-off-by: Carles Cufi (cherry picked from commit 6b014316c607f99f927c6e05917ee73167e08f03) (cherry picked from commit d68a96e7be44ada31fe6e9a8d28e943298a6211f) --- .github/workflows/commit-tags.yml | 31 ++++++++++++++++++++++++++ .github/workflows/compliance.yml | 8 +++---- Jenkinsfile | 5 +++++ scripts/gitlint/zephyr_commit_rules.py | 4 ++-- 4 files changed, 42 insertions(+), 6 deletions(-) create mode 100644 .github/workflows/commit-tags.yml create mode 100644 Jenkinsfile diff --git a/.github/workflows/commit-tags.yml b/.github/workflows/commit-tags.yml new file mode 100644 index 00000000000..9e0323f9498 --- /dev/null +++ b/.github/workflows/commit-tags.yml @@ -0,0 +1,31 @@ +name: Commit tags + +on: pull_request + +jobs: + commit_tags: + runs-on: ubuntu-22.04 + name: Run commit tags checks on patch series (PR) + steps: + - name: Update PATH for west + run: | + echo "$HOME/.local/bin" >> $GITHUB_PATH + + - name: Checkout the code + uses: actions/checkout@v3 + with: + ref: ${{ github.event.pull_request.head.sha }} + fetch-depth: 0 + + - name: Install python dependencies + run: | + pip3 install setuptools + pip3 install wheel + pip3 install gitlint + + - name: Run the commit tags + uses: nrfconnect/action-commit-tags@main + with: + target: '.' + baserev: origin/${{ github.base_ref }} + revrange: 'none' diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 5e6e2cff9a6..88c98e84710 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -38,8 +38,8 @@ jobs: git config --global user.name "Your Name" git remote -v # Ensure there's no merge commits in the PR - [[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \ - (echo "::error ::Merge commits not allowed, rebase instead";false) + #[[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \ + #(echo "::error ::Merge commits not allowed, rebase instead";false) git rebase origin/${BASE_REF} # debug git log --pretty=oneline | head -n 10 @@ -59,8 +59,8 @@ jobs: git log --pretty=oneline | head -n 10 # Increase rename limit to allow for large PRs git config diff.renameLimit 10000 - ./scripts/ci/check_compliance.py --annotate -e KconfigBasic \ - -c origin/${BASE_REF}.. + ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -e Kconfig \ + -e KconfigBasicNoModules -e ModulesMaintainers -c origin/${BASE_REF}.. - name: upload-results uses: actions/upload-artifact@v4 diff --git a/Jenkinsfile b/Jenkinsfile new file mode 100644 index 00000000000..3b9cf002239 --- /dev/null +++ b/Jenkinsfile @@ -0,0 +1,5 @@ +@Library("CI_LIB") _ + +def pipeline = new ncs.sdk_zephyr.Main() + +pipeline.run(JOB_NAME) diff --git a/scripts/gitlint/zephyr_commit_rules.py b/scripts/gitlint/zephyr_commit_rules.py index a2c9cd3cb7f..ef317e22684 100644 --- a/scripts/gitlint/zephyr_commit_rules.py +++ b/scripts/gitlint/zephyr_commit_rules.py @@ -78,7 +78,7 @@ class TitleMaxLengthRevert(LineRule): name = "title-max-length-no-revert" id = "UC5" target = CommitMessageTitle - options_spec = [IntOption('line-length', 75, "Max line length")] + options_spec = [IntOption('line-length', 120, "Max line length")] violation_message = "Commit title exceeds max length ({0}>{1})" def validate(self, line, _commit): @@ -103,7 +103,7 @@ class MaxLineLengthExceptions(LineRule): name = "max-line-length-with-exceptions" id = "UC4" target = CommitMessageBody - options_spec = [IntOption('line-length', 75, "Max line length")] + options_spec = [IntOption('line-length', 120, "Max line length")] violation_message = "Commit message body line exceeds max length ({0}>{1})" def validate(self, line, _commit): From 14cf3aa0fef8ffef4c4978cb0443f43f2dbe9038 Mon Sep 17 00:00:00 2001 From: Dominik Ermel Date: Wed, 27 Sep 2023 09:41:10 +0000 Subject: [PATCH 2381/2402] [nrf noup] test: schedule_api: Use Minimal C library There is no point to use PICOLIB here as it bloats the tests. Signed-off-by: Dominik Ermel (cherry picked from commit 350e687dd5c75ac574fbea06200b8f02b854a7c7) --- tests/kernel/sched/schedule_api/prj.conf | 1 + tests/kernel/sched/schedule_api/prj_dumb.conf | 1 + tests/kernel/sched/schedule_api/prj_multiq.conf | 1 + 3 files changed, 3 insertions(+) diff --git a/tests/kernel/sched/schedule_api/prj.conf b/tests/kernel/sched/schedule_api/prj.conf index fe5125047e3..785e9a3987b 100644 --- a/tests/kernel/sched/schedule_api/prj.conf +++ b/tests/kernel/sched/schedule_api/prj.conf @@ -7,3 +7,4 @@ CONFIG_MAX_THREAD_BYTES=5 CONFIG_TEST_USERSPACE=y CONFIG_MP_MAX_NUM_CPUS=1 CONFIG_ZTEST_FATAL_HOOK=y +CONFIG_MINIMAL_LIBC=y diff --git a/tests/kernel/sched/schedule_api/prj_dumb.conf b/tests/kernel/sched/schedule_api/prj_dumb.conf index c0ddfbd7c3f..a1d0cf6dced 100644 --- a/tests/kernel/sched/schedule_api/prj_dumb.conf +++ b/tests/kernel/sched/schedule_api/prj_dumb.conf @@ -5,3 +5,4 @@ CONFIG_SCHED_DUMB=y CONFIG_MAX_THREAD_BYTES=5 CONFIG_MP_MAX_NUM_CPUS=1 CONFIG_ZTEST_FATAL_HOOK=y +CONFIG_MINIMAL_LIBC=y diff --git a/tests/kernel/sched/schedule_api/prj_multiq.conf b/tests/kernel/sched/schedule_api/prj_multiq.conf index 6b28a1f39b2..cfe09fbce47 100644 --- a/tests/kernel/sched/schedule_api/prj_multiq.conf +++ b/tests/kernel/sched/schedule_api/prj_multiq.conf @@ -7,3 +7,4 @@ CONFIG_MP_MAX_NUM_CPUS=1 CONFIG_ZTEST_FATAL_HOOK=y CONFIG_NUM_COOP_PRIORITIES=30 CONFIG_NUM_PREEMPT_PRIORITIES=40 +CONFIG_MINIMAL_LIBC=y From cf41e66dd8d1cd017479631e4cf3c91b6f3e54c8 Mon Sep 17 00:00:00 2001 From: Jan Tore Guggedal Date: Mon, 18 May 2020 20:50:13 +0200 Subject: [PATCH 2382/2402] [nrf noup] net: mqtt: Provide option to enable TLS session caching Provides an option to enable TLS session caching for an MQTT client's secure socket. Signed-off-by: Jan Tore Guggedal Signed-off-by: Robert Lubos Signed-off-by: Dominik Ermel Signed-off-by: Johann Fischer (cherry picked from commit 05e424a60315d7083c1b2c3391010b54bd42443a) --- include/zephyr/net/mqtt.h | 3 +++ subsys/net/lib/mqtt/mqtt_transport_socket_tls.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/include/zephyr/net/mqtt.h b/include/zephyr/net/mqtt.h index 987b3726caf..d3c1c814b9d 100644 --- a/include/zephyr/net/mqtt.h +++ b/include/zephyr/net/mqtt.h @@ -371,6 +371,9 @@ struct mqtt_sec_config { uint32_t alpn_protocol_name_count; #endif + /** Indicates the preference for enabling TLS session caching. */ + int session_cache; + /** Peer hostname for ceritificate verification. * May be NULL to skip hostname verification. */ diff --git a/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c b/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c index a33cee5aecf..445f45c95df 100644 --- a/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c +++ b/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c @@ -91,6 +91,16 @@ int mqtt_client_tls_connect(struct mqtt_client *client) } } + if (tls_config->session_cache == TLS_SESSION_CACHE_ENABLED) { + ret = zsock_setsockopt(client->transport.tls.sock, SOL_TLS, + TLS_SESSION_CACHE, + &tls_config->session_cache, + sizeof(tls_config->session_cache)); + if (ret < 0) { + goto error; + } + } + if (tls_config->cert_nocopy != TLS_CERT_NOCOPY_NONE) { ret = zsock_setsockopt(client->transport.tls.sock, SOL_TLS, TLS_CERT_NOCOPY, &tls_config->cert_nocopy, From aed2d4a080ce139d653b86abfe67f119472cbf2b Mon Sep 17 00:00:00 2001 From: Mirko Covizzi Date: Thu, 10 Mar 2022 00:25:50 -0800 Subject: [PATCH 2383/2402] [nrf noup] net: mqtt: add native TLS support This commit adds an extra parameter in the configuration structure to configure native TLS support at runtime. Signed-off-by: Mirko Covizzi (cherry picked from commit 63940d988b3879983d2c36270e703422c5dd7d05) --- doc/connectivity/networking/api/mqtt.rst | 3 +++ include/zephyr/net/mqtt.h | 3 +++ subsys/net/lib/mqtt/mqtt_transport_socket_tls.c | 7 ++++++- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/doc/connectivity/networking/api/mqtt.rst b/doc/connectivity/networking/api/mqtt.rst index b232f125333..79da5abe57b 100644 --- a/doc/connectivity/networking/api/mqtt.rst +++ b/doc/connectivity/networking/api/mqtt.rst @@ -150,6 +150,7 @@ additional configuration information: tls_config->sec_tag_list = m_sec_tags; tls_config->sec_tag_count = ARRAY_SIZE(m_sec_tags); tls_config->hostname = MQTT_BROKER_HOSTNAME; + tls_config->set_native_tls = true; In this sample code, the ``m_sec_tags`` array holds a list of tags, referencing TLS credentials that the MQTT library should use for authentication. We do not specify @@ -162,6 +163,8 @@ Note, that TLS credentials referenced by the ``m_sec_tags`` array must be registered in the system first. For more information on how to do that, refer to :ref:`secure sockets documentation `. +Finally, ``set_native_tls`` can be optionally set to enable native TLS support instead of offloading TLS operations to the modem. + An example of how to use TLS with MQTT is also present in :zephyr:code-sample:`mqtt-publisher` sample application. diff --git a/include/zephyr/net/mqtt.h b/include/zephyr/net/mqtt.h index d3c1c814b9d..54b2532f0fa 100644 --- a/include/zephyr/net/mqtt.h +++ b/include/zephyr/net/mqtt.h @@ -381,6 +381,9 @@ struct mqtt_sec_config { /** Indicates the preference for copying certificates to the heap. */ int cert_nocopy; + + /** Set socket to native TLS */ + bool set_native_tls; }; /** @brief MQTT transport type. */ diff --git a/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c b/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c index 445f45c95df..c3816e5949f 100644 --- a/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c +++ b/subsys/net/lib/mqtt/mqtt_transport_socket_tls.c @@ -22,10 +22,15 @@ int mqtt_client_tls_connect(struct mqtt_client *client) { const struct sockaddr *broker = client->broker; struct mqtt_sec_config *tls_config = &client->transport.tls.config; + int type = SOCK_STREAM; int ret; + if (tls_config->set_native_tls) { + type |= SOCK_NATIVE_TLS; + } + client->transport.tls.sock = zsock_socket(broker->sa_family, - SOCK_STREAM, IPPROTO_TLS_1_2); + type, IPPROTO_TLS_1_2); if (client->transport.tls.sock < 0) { return -errno; } From 99c9a2b7600ecf4035ef7c8c2894ee2e540f25ff Mon Sep 17 00:00:00 2001 From: Markus Swarowsky Date: Mon, 4 Dec 2023 15:27:08 +0100 Subject: [PATCH 2384/2402] [nrf noup] soc: arm: nRF53: Add SPU Flash/RAM alignment TF-M will uses SPU alignment during build time to make sure all partitions can be locked down with the SPU. So adding them for nRF53 Signed-off-by: Markus Swarowsky Signed-off-by: Dominik Ermel (cherry picked from commit 90826581f1ee32b99f1cafdffc2e634a495d8ee3) --- soc/nordic/nrf53/Kconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/soc/nordic/nrf53/Kconfig b/soc/nordic/nrf53/Kconfig index cc7bdaa5dc6..5f0d5b12326 100644 --- a/soc/nordic/nrf53/Kconfig +++ b/soc/nordic/nrf53/Kconfig @@ -127,12 +127,26 @@ config NRF_SPU_FLASH_REGION_SIZE help FLASH region size for the NRF_SPU peripheral +config NRF_SPU_FLASH_REGION_ALIGNMENT + hex + default 0x4000 + help + FLASH regions must be aligned to this value due to SPU HW + limitations. + config NRF_SPU_RAM_REGION_SIZE hex default 0x2000 help RAM region size for the NRF_SPU peripheral +config NRF_SPU_RAM_REGION_ALIGNMENT + hex + default 0x2000 + help + RAM regions must be aligned to this value due to SPU HW + limitations. + config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 bool depends on NRF_SOC_SECURE_SUPPORTED From 69121665915838ce1b6736e7935db13681e08d27 Mon Sep 17 00:00:00 2001 From: Markus Swarowsky Date: Mon, 4 Dec 2023 15:27:14 +0100 Subject: [PATCH 2385/2402] [nrf noup] soc: arm: nRF91: Add SPU Flash/RAM alignment TF-M will uses SPU alignment during build time to make sure all partitions can be locked down with the SPU. So adding them for nRF91 Signed-off-by: Markus Swarowsky Signed-off-by: Dominik Ermel (cherry picked from commit 83be41dde2e00776f02e583d8e6e55743b6c2ef7) --- soc/nordic/nrf91/Kconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/soc/nordic/nrf91/Kconfig b/soc/nordic/nrf91/Kconfig index ed38eff73a2..8001f3aca3a 100644 --- a/soc/nordic/nrf91/Kconfig +++ b/soc/nordic/nrf91/Kconfig @@ -24,6 +24,13 @@ config NRF_SPU_FLASH_REGION_SIZE help FLASH region size for the NRF_SPU peripheral +config NRF_SPU_FLASH_REGION_ALIGNMENT + hex + default 0x8000 + help + FLASH regions must be aligned to this value due to SPU HW + limitations. + config NRF_SPU_RAM_REGION_SIZE hex default 0x2000 @@ -34,4 +41,11 @@ config NRF_ENABLE_ICACHE bool "Instruction cache (I-Cache)" default y +config NRF_SPU_RAM_REGION_ALIGNMENT + hex + default 0x2000 + help + RAM regions must be aligned to this value due to SPU HW + limitations. + endif # SOC_SERIES_NRF91X From 82e60763d2eaf1982f634e61ea8c428312cf8f1c Mon Sep 17 00:00:00 2001 From: Marek Pieta Date: Mon, 14 Nov 2022 11:22:06 +0100 Subject: [PATCH 2386/2402] [nrf noup] boards: thingy53_nrf5340: Add common partition map Change introduces common static Partition Manager configuration. The tfm_nonsecure partition must be SPU region aligned. Ref: NCSDK-18033 Ref: NCSDK-19515 Signed-off-by: Marek Pieta Signed-off-by: Markus Swarowsky (cherry picked from commit cb04671ad6e0de80e4441e996cc29416af40caaa) --- .../pm_static_thingy53_nrf5340_cpuapp.yml | 55 ++++++++++++++ .../pm_static_thingy53_nrf5340_cpuapp_ns.yml | 73 +++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp.yml create mode 100644 boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp_ns.yml diff --git a/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp.yml b/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp.yml new file mode 100644 index 00000000000..7a48d51ec33 --- /dev/null +++ b/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp.yml @@ -0,0 +1,55 @@ +app: + address: 0x10200 + region: flash_primary + size: 0xdfe00 +mcuboot: + address: 0x0 + region: flash_primary + size: 0x10000 +mcuboot_pad: + address: 0x10000 + region: flash_primary + size: 0x200 +mcuboot_primary: + address: 0x10000 + orig_span: &id001 + - mcuboot_pad + - app + region: flash_primary + size: 0xe0000 + span: *id001 +mcuboot_primary_app: + address: 0x10200 + orig_span: &id002 + - app + region: flash_primary + size: 0xdfe00 + span: *id002 +settings_storage: + address: 0xf0000 + region: flash_primary + size: 0x10000 +mcuboot_primary_1: + address: 0x0 + size: 0x40000 + device: flash_ctrl + region: ram_flash +mcuboot_secondary: + address: 0x00000 + size: 0xe0000 + device: MX25R64 + region: external_flash +mcuboot_secondary_1: + address: 0xe0000 + size: 0x40000 + device: MX25R64 + region: external_flash +external_flash: + address: 0x120000 + size: 0x6e0000 + device: MX25R64 + region: external_flash +pcd_sram: + address: 0x20000000 + size: 0x2000 + region: sram_primary diff --git a/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp_ns.yml b/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp_ns.yml new file mode 100644 index 00000000000..70ffe6d9c12 --- /dev/null +++ b/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp_ns.yml @@ -0,0 +1,73 @@ +mcuboot: + address: 0x0 + region: flash_primary + size: 0x10000 +mcuboot_pad: + address: 0x10000 + region: flash_primary + size: 0x200 +tfm_secure: + address: 0x10000 + size: 0xc000 + span: [mcuboot_pad, tfm] +tfm_nonsecure: + address: 0x1c000 + size: 0xd4000 + span: [app] +tfm: + address: 0x10200 + region: flash_primary + size: 0xbe00 +app: + address: 0x1c000 + region: flash_primary + size: 0xd4000 +mcuboot_primary: + address: 0x10000 + orig_span: &id001 + - mcuboot_pad + - tfm + - app + region: flash_primary + size: 0xe0000 + span: *id001 +mcuboot_primary_app: + address: 0x10200 + orig_span: &id002 + - tfm + - app + region: flash_primary + size: 0xdfe00 + span: *id002 +nonsecure_storage: + address: 0xf0000 + size: 0x10000 + span: [settings_storage] +settings_storage: + address: 0xf0000 + region: flash_primary + size: 0x10000 +mcuboot_primary_1: + address: 0x0 + size: 0x40000 + device: flash_ctrl + region: ram_flash +mcuboot_secondary: + address: 0x00000 + size: 0xe0000 + device: MX25R64 + region: external_flash +mcuboot_secondary_1: + address: 0xe0000 + size: 0x40000 + device: MX25R64 + region: external_flash +external_flash: + address: 0x120000 + size: 0x6e0000 + device: MX25R64 + region: external_flash +pcd_sram: + address: 0x20000000 + size: 0x2000 + region: sram_primary From 0cbfe199bfd402a6f627b3d13a911ae05406d287 Mon Sep 17 00:00:00 2001 From: Mateusz Kapala Date: Thu, 2 Feb 2023 11:04:23 +0100 Subject: [PATCH 2387/2402] [nrf noup] boards: arm: thingy53: Disable USB CDC added by MCUBoot Enabling USB CDC by default in Thingy:53 board configuration caused that there were two instances of USB CDC in MCUBoot. Change disables one instance which was added automatically by NCS if MCUBoot bootloader was built as a child image. Jira: NCSDK-18596 Signed-off-by: Mateusz Kapala Signed-off-by: Johann Fischer (cherry picked from commit 778b2a956086de2f6aec01f39651a25e3613cdae) (cherry picked from commit 6799c02cb60196ac26ebc1c1aeee54ca105f8e75) --- boards/nordic/thingy53/Kconfig.defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/boards/nordic/thingy53/Kconfig.defconfig b/boards/nordic/thingy53/Kconfig.defconfig index 701bd9be4e6..f498c936eb5 100644 --- a/boards/nordic/thingy53/Kconfig.defconfig +++ b/boards/nordic/thingy53/Kconfig.defconfig @@ -133,6 +133,13 @@ endif # LOG endif # BOARD_SERIAL_BACKEND_CDC_ACM +# By default, a USB CDC ACM instance is already enabled in the board's DTS. +# It is not necessary for nRF Connect SDK to add another instance if MCUBoot +# bootloader is built as a child image. +config MCUBOOT_USB_SUPPORT + bool + default n + endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS if BOARD_THINGY53_NRF5340_CPUNET From 6e623f79c2183cf1eff280f00a23fa5cde621aa4 Mon Sep 17 00:00:00 2001 From: Marek Pieta Date: Mon, 28 Nov 2022 15:31:33 +0100 Subject: [PATCH 2388/2402] [nrf noup] boards: thingy53_nrf5340: Enable MCUboot by default Change enables MCUboot bootloader by default to allow programming samples and applications without external programmer (using MCUboot serial recovery). Change also enables network core to prevent build failures when building MCUboot with nRF53 multi image DFU. Jira: NCSDK-18263 Signed-off-by: Marek Pieta Signed-off-by: Vinayak Kariappa Chettimada Signed-off-by: Johann Fischer Signed-off-by: Joakim Andersson (cherry picked from commit ff85910bf8ed1aac0571bca0e7f206782234efbb) --- boards/nordic/thingy53/Kconfig.defconfig | 6 ++++++ boards/nordic/thingy53/thingy53_nrf5340_common.dtsi | 1 + 2 files changed, 7 insertions(+) diff --git a/boards/nordic/thingy53/Kconfig.defconfig b/boards/nordic/thingy53/Kconfig.defconfig index f498c936eb5..d849fda09ed 100644 --- a/boards/nordic/thingy53/Kconfig.defconfig +++ b/boards/nordic/thingy53/Kconfig.defconfig @@ -5,6 +5,12 @@ if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS +config BOOTLOADER_MCUBOOT + default y if !MCUBOOT + +config BOARD_ENABLE_CPUNET + default y if !MCUBOOT + # Code Partition: # # For the secure version of the board the firmware is linked at the beginning diff --git a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi index 694a6960584..54efd588cf7 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi +++ b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi @@ -16,6 +16,7 @@ zephyr,bt-hci-ipc = &ipc0; nordic,802154-spinel-ipc = &ipc0; zephyr,ieee802154 = &ieee802154; + nordic,pm-ext-flash = &mx25r64; }; buttons { From 55be58b8659fec1c0cfe7d773634a0191c60f974 Mon Sep 17 00:00:00 2001 From: Maximilian Deubel Date: Wed, 15 Nov 2023 12:55:40 +0100 Subject: [PATCH 2389/2402] [nrf noup] boards: arm: nrf9131ek: enable tfm This patch backports the nrf9131ek to a time before tfm was refactored. To be reverted when TF-M is updated. Signed-off-by: Maximilian Deubel Signed-off-by: Dominik Ermel (cherry picked from commit d0b22f5deb110cbe508a847faf79d4b7add5b4bf) --- boards/nordic/nrf9131ek/Kconfig.defconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/boards/nordic/nrf9131ek/Kconfig.defconfig b/boards/nordic/nrf9131ek/Kconfig.defconfig index b63e7ef8d34..8e0e1d02d1d 100644 --- a/boards/nordic/nrf9131ek/Kconfig.defconfig +++ b/boards/nordic/nrf9131ek/Kconfig.defconfig @@ -5,6 +5,21 @@ if BOARD_NRF9131EK_NRF9131 || BOARD_NRF9131EK_NRF9131_NS +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y if BOARD_NRF9131EK_NRF9131_NS + +if BUILD_WITH_TFM + +# By default, if we build with TF-M, instruct build system to +# flash the combined TF-M (Secure) & Zephyr (Non Secure) image +config TFM_FLASH_MERGED_BINARY + bool + default y + +endif # BUILD_WITH_TFM + # For the secure version of the board the firmware is linked at the beginning # of the flash, or into the code-partition defined in DT if it is intended to # be loaded by MCUboot. If the secure firmware is to be combined with a non- From 91b6032820a140a6722f0838544f55d69b99a3e1 Mon Sep 17 00:00:00 2001 From: Sigvart Hovland Date: Fri, 3 May 2019 14:21:52 +0200 Subject: [PATCH 2390/2402] [nrf noup] tree-wide: support NCS Partition Manager (PM) definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Partition Manager (PM) is a component of the nRF Connect SDK (NCS) which uses yaml files to resolve flash partition placement with a holistic view of the entire device, including each firmware image present on the flash device, and various subsystems, such as settings and NFFS. When this NCS extension is used, various source files which would use partition information from devicetree in "vanilla" zephyr instead use defines generated by PM instead. This commit removes support for HEX_FILES_TO_MERGE, as it conflicts with PM. The settings subsystem pm.yml defines a partition 'settings_storage'. The nffs subsystem pm.yml defines 'nffs_storage'. Leverage label translation to avoid patching partition names. Refer to the NCS documentation page for this feature for more details. This is a long-running out of tree patch which has been worked on by several people. The following sign-offs are in alphabetical order by first name. Signed-off-by: Andrzej Głąbek Signed-off-by: Andrzej Puzdrowski Signed-off-by: Håkon Øye Amundsen Signed-off-by: Ioannis Glaropoulos Signed-off-by: Joakim Andersson Signed-off-by: Johann Fischer Signed-off-by: Martí Bolívar Signed-off-by: Ole Sæther Signed-off-by: Robert Lubos Signed-off-by: Sebastian Bøe Signed-off-by: Sigvart Hovland Signed-off-by: Thomas Stenersen Signed-off-by: Torsten Rasmussen Signed-off-by: Øyvind Rønningstad Signed-off-by: Trond Einar Snekvik Signed-off-by: Gerard Marull-Paretas Signed-off-by: Tomasz Moń Signed-off-by: Dominik Ermel (cherry picked from commit a7fb26837763ee7c21fb666fe2faa8c7503a17f1) (cherry picked from commit ea83f6ccc7786349ddcf267af19a1b63e0fe950f) --- arch/arm/core/mpu/arm_mpu_regions.c | 13 ++++++ cmake/modules/kernel.cmake | 4 ++ drivers/flash/soc_flash_nrf.c | 11 +++++ .../arch/arm/cortex_m/scripts/linker.ld | 46 +++++++++++++++++++ include/zephyr/storage/flash_map.h | 6 +++ lib/heap/Kconfig | 2 +- lib/libc/common/source/stdlib/malloc.c | 18 +++++++- subsys/fs/littlefs_fs.c | 7 ++- subsys/ipc/rpmsg_service/rpmsg_backend.h | 27 +++++++++++ 9 files changed, 130 insertions(+), 4 deletions(-) diff --git a/arch/arm/core/mpu/arm_mpu_regions.c b/arch/arm/core/mpu/arm_mpu_regions.c index 6af62f84078..cfe1230c907 100644 --- a/arch/arm/core/mpu/arm_mpu_regions.c +++ b/arch/arm/core/mpu/arm_mpu_regions.c @@ -8,6 +8,9 @@ #include #include +#if USE_PARTITION_MANAGER +#include +#endif static const struct arm_mpu_region mpu_regions[] = { /* Region 0 */ @@ -21,6 +24,14 @@ static const struct arm_mpu_region mpu_regions[] = { #endif /* Region 1 */ MPU_REGION_ENTRY("SRAM_0", +#if USE_PARTITION_MANAGER + PM_SRAM_ADDRESS, +#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) + REGION_RAM_ATTR(PM_SRAM_ADDRESS, PM_SRAM_SIZE)), +#else + REGION_RAM_ATTR(REGION_SRAM_SIZE)), +#endif +#else CONFIG_SRAM_BASE_ADDRESS, #if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \ @@ -28,6 +39,8 @@ static const struct arm_mpu_region mpu_regions[] = { #else REGION_RAM_ATTR(REGION_SRAM_SIZE)), #endif + +#endif /* USE_PARTITION_MANAGER */ }; const struct arm_mpu_config mpu_config = { diff --git a/cmake/modules/kernel.cmake b/cmake/modules/kernel.cmake index a093d46691f..06e1642f362 100644 --- a/cmake/modules/kernel.cmake +++ b/cmake/modules/kernel.cmake @@ -243,3 +243,7 @@ if("${CMAKE_EXTRA_GENERATOR}" STREQUAL "Eclipse CDT4") include(${ZEPHYR_BASE}/cmake/ide/eclipse_cdt4_generator_amendment.cmake) eclipse_cdt4_generator_amendment(1) endif() + +if(ZEPHYR_NRF_MODULE_DIR) + include(${ZEPHYR_NRF_MODULE_DIR}/cmake/partition_manager.cmake) +endif() diff --git a/drivers/flash/soc_flash_nrf.c b/drivers/flash/soc_flash_nrf.c index cc840309264..b5a3fefa1e5 100644 --- a/drivers/flash/soc_flash_nrf.c +++ b/drivers/flash/soc_flash_nrf.c @@ -37,6 +37,11 @@ LOG_MODULE_REGISTER(flash_nrf); #define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash) +#if CONFIG_TRUSTED_EXECUTION_NONSECURE && USE_PARTITION_MANAGER +#include +#include +#endif /* CONFIG_TRUSTED_EXECUTION_NONSECURE && USE_PARTITION_MANAGER */ + #ifndef CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE #define FLASH_SLOT_WRITE 7500 #if defined(CONFIG_SOC_FLASH_NRF_PARTIAL_ERASE) @@ -166,6 +171,12 @@ static int flash_nrf_read(const struct device *dev, off_t addr, } #endif +#if CONFIG_TRUSTED_EXECUTION_NONSECURE && USE_PARTITION_MANAGER && PM_APP_ADDRESS + if (addr < PM_APP_ADDRESS) { + return soc_secure_mem_read(data, (void *)addr, len); + } +#endif + nrf_nvmc_buffer_read(data, (uint32_t)addr, len); return 0; diff --git a/include/zephyr/arch/arm/cortex_m/scripts/linker.ld b/include/zephyr/arch/arm/cortex_m/scripts/linker.ld index d061468d2ac..14eb78f3e70 100644 --- a/include/zephyr/arch/arm/cortex_m/scripts/linker.ld +++ b/include/zephyr/arch/arm/cortex_m/scripts/linker.ld @@ -26,6 +26,35 @@ #endif #define RAMABLE_REGION RAM +#if USE_PARTITION_MANAGER + +#include + +#if CONFIG_NCS_IS_VARIANT_IMAGE && defined(PM_S0_ID) +/* We are linking against S1, create symbol containing the flash ID of S0. + * This is used when writing code operating on the "other" slot. + */ +_image_1_primary_slot_id = PM_S0_ID; + +#else /* ! CONFIG_NCS_IS_VARIANT_IMAGE */ + +#ifdef PM_S1_ID +/* We are linking against S0, create symbol containing the flash ID of S1. + * This is used when writing code operating on the "other" slot. + */ +_image_1_primary_slot_id = PM_S1_ID; +#endif /* PM_S1_ID */ + +#endif /* CONFIG_NCS_IS_VARIANT_IMAGE */ + +#define ROM_ADDR PM_ADDRESS +#define ROM_SIZE PM_SIZE + +#define RAM_SIZE PM_SRAM_SIZE +#define RAM_ADDR PM_SRAM_ADDRESS + +#else /* ! USE_PARTITION_MANAGER */ + #if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0) #define ROM_ADDR RAM_ADDR #else @@ -58,6 +87,23 @@ #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS #endif +#endif /* USE_PARTITION_MANAGER */ + +#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay) +#define CCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ccm)) +#define CCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ccm)) +#endif + +#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay) +#define ITCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_itcm)) +#define ITCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_itcm)) +#endif + +#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay) +#define DTCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm)) +#define DTCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm)) +#endif + #if defined(CONFIG_CUSTOM_SECTION_ALIGN) _region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE; #else diff --git a/include/zephyr/storage/flash_map.h b/include/zephyr/storage/flash_map.h index 37b7c7f3223..c53cbef8957 100644 --- a/include/zephyr/storage/flash_map.h +++ b/include/zephyr/storage/flash_map.h @@ -273,6 +273,10 @@ const char *flash_area_label(const struct flash_area *fa); */ uint8_t flash_area_erased_val(const struct flash_area *fa); +#if USE_PARTITION_MANAGER +#include +#else + /** * Returns non-0 value if fixed-partition of given DTS node label exists. * @@ -330,6 +334,8 @@ uint8_t flash_area_erased_val(const struct flash_area *fa); #define FIXED_PARTITION_DEVICE(label) \ DEVICE_DT_GET(DT_MTD_FROM_FIXED_PARTITION(DT_NODELABEL(label))) +#endif /* USE_PARTITION_MANAGER */ + #ifdef __cplusplus } #endif diff --git a/lib/heap/Kconfig b/lib/heap/Kconfig index 7f01b280b3b..68476eb735c 100644 --- a/lib/heap/Kconfig +++ b/lib/heap/Kconfig @@ -68,7 +68,7 @@ config HEAP_LISTENER choice prompt "Supported heap sizes" depends on !64BIT - default SYS_HEAP_SMALL_ONLY if (SRAM_SIZE <= 256) + default SYS_HEAP_SMALL_ONLY if (SRAM_SIZE <= 256) && !PARTITION_MANAGER_ENABLED default SYS_HEAP_AUTO help Heaps using reduced-size chunk headers can accommodate so called diff --git a/lib/libc/common/source/stdlib/malloc.c b/lib/libc/common/source/stdlib/malloc.c index e3a5db6f7d5..2f469d673e4 100644 --- a/lib/libc/common/source/stdlib/malloc.c +++ b/lib/libc/common/source/stdlib/malloc.c @@ -25,6 +25,20 @@ #include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); +#if USE_PARTITION_MANAGER + +#include + +#define RAM_SIZE PM_SRAM_SIZE +#define RAM_ADDR PM_SRAM_ADDRESS + +#else /* ! USE_PARTITION_MANAGER */ + +#define RAM_SIZE (KB((size_t) CONFIG_SRAM_SIZE)) +#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS + +#endif /* USE_PARTITION_MANAGER */ + #ifdef CONFIG_COMMON_LIBC_MALLOC #if (CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE != 0) @@ -106,8 +120,8 @@ static POOL_SECTION unsigned char __aligned(HEAP_ALIGN) malloc_arena[HEAP_SIZE]; extern char _heap_sentry[]; # define HEAP_SIZE ROUND_DOWN((POINTER_TO_UINT(_heap_sentry) - HEAP_BASE), HEAP_ALIGN) # else -# define HEAP_SIZE ROUND_DOWN((KB((size_t) CONFIG_SRAM_SIZE) - \ - ((size_t) HEAP_BASE - (size_t) CONFIG_SRAM_BASE_ADDRESS)), HEAP_ALIGN) +# define HEAP_SIZE ROUND_DOWN((RAM_SIZE - \ + ((size_t) HEAP_BASE - (size_t) RAM_ADDR)), HEAP_ALIGN) # endif /* else CONFIG_XTENSA */ # endif /* else CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE > 0 */ diff --git a/subsys/fs/littlefs_fs.c b/subsys/fs/littlefs_fs.c index b373ca92ba8..3fc84c2922d 100644 --- a/subsys/fs/littlefs_fs.c +++ b/subsys/fs/littlefs_fs.c @@ -1054,7 +1054,12 @@ struct fs_mount_t FS_FSTAB_ENTRY(DT_DRV_INST(inst)) = { \ .type = FS_LITTLEFS, \ .mnt_point = DT_INST_PROP(inst, mount_point), \ .fs_data = &fs_data_##inst, \ - .storage_dev = (void *)DT_FIXED_PARTITION_ID(FS_PARTITION(inst)), \ + .storage_dev = (void *) \ + COND_CODE_1(USE_PARTITION_MANAGER, \ + (COND_CODE_1(FIXED_PARTITION_EXISTS(littlefs_storage), \ + (FIXED_PARTITION_ID(littlefs_storage)), \ + (FIXED_PARTITION_ID(storage)))), \ + (DT_FIXED_PARTITION_ID(FS_PARTITION(inst)))), \ .flags = FSTAB_ENTRY_DT_MOUNT_FLAGS(DT_DRV_INST(inst)), \ }; diff --git a/subsys/ipc/rpmsg_service/rpmsg_backend.h b/subsys/ipc/rpmsg_service/rpmsg_backend.h index a74e46b8520..9996e1d74d9 100644 --- a/subsys/ipc/rpmsg_service/rpmsg_backend.h +++ b/subsys/ipc/rpmsg_service/rpmsg_backend.h @@ -13,8 +13,35 @@ extern "C" { #endif +#if CONFIG_PARTITION_MANAGER_ENABLED + +#include "pm_config.h" + +#if defined(PM_RPMSG_NRF53_SRAM_ADDRESS) || defined(PM__RPMSG_NRF53_SRAM_ADDRESS) + +#if defined(PM_RPMSG_NRF53_SRAM_ADDRESS) +#define VDEV_START_ADDR PM_RPMSG_NRF53_SRAM_ADDRESS +#define VDEV_SIZE PM_RPMSG_NRF53_SRAM_SIZE +#else +/* The current image is a child image in a different domain than the image + * which defined the required values. To reach the values of the parent domain + * we use the 'PM__' variant of the define. + */ +#define VDEV_START_ADDR PM__RPMSG_NRF53_SRAM_ADDRESS +#define VDEV_SIZE PM__RPMSG_NRF53_SRAM_SIZE +#endif /* defined(PM_RPMSG_NRF53_SRAM_ADDRESS) */ + +#else #define VDEV_START_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ipc_shm)) #define VDEV_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ipc_shm)) +#endif /* defined(PM_RPMSG_NRF53_SRAM_ADDRESS) || defined(PM__RPMSG_NRF53_SRAM_ADDRESS) */ + +#else + +#define VDEV_START_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ipc_shm)) +#define VDEV_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ipc_shm)) + +#endif /* CONFIG_PARTITION_MANAGER_ENABLED */ #define VDEV_STATUS_ADDR VDEV_START_ADDR #define VDEV_STATUS_SIZE 0x400 From 4d6f8b4d50b9d0aa76635b5410a02fc18837d03b Mon Sep 17 00:00:00 2001 From: Mateusz Michalek Date: Wed, 20 Mar 2024 12:10:13 +0100 Subject: [PATCH 2391/2402] [nrf noup] samples: smp_svr: configuration for nrf54l15 Configuration allows DFU with serial transport using mcumgr and over BT using nRF Connect. Signed-off-by: Mateusz Michalek --- samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml index 6a3669b2438..04e19dfb48e 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml +++ b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml @@ -12,9 +12,11 @@ tests: - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 + - nrf54l15pdk/nrf54l15/cpuapp integration_platforms: - nrf52dk/nrf52832 - nrf52840dk/nrf52840 + - nrf54l15pdk/nrf54l15/cpuapp sample.mcumgr.smp_svr.bt_static_svc: extra_args: OVERLAY_CONFIG="overlay-bt.conf" extra_configs: From e2b6a2d4d387e9d38f59befcdade925663125594 Mon Sep 17 00:00:00 2001 From: Kamil Gawor Date: Tue, 9 Apr 2024 14:24:34 +0200 Subject: [PATCH 2392/2402] [nrf noup] entropy: Add fake entropy nRF PRNG driver This adds temporary entropy driver simulation for nRF54h20 device since final entropy source is not available yet. TODO: Remove this commit when proper solution will be available. Jira: NCSDK-25947 Signed-off-by: Kamil Gawor (cherry picked from commit c976657eb74bfb052d93479be37594bddeff3d86) --- .../nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 6 ++ .../nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts | 6 ++ drivers/entropy/CMakeLists.txt | 7 ++ drivers/entropy/Kconfig | 1 + drivers/entropy/Kconfig.nrf_prng | 19 ++++ drivers/entropy/fake_entropy_nrf_prng.c | 101 ++++++++++++++++++ dts/bindings/rng/nordic,nrf-prng.yaml | 8 ++ 7 files changed, 148 insertions(+) create mode 100644 drivers/entropy/Kconfig.nrf_prng create mode 100644 drivers/entropy/fake_entropy_nrf_prng.c create mode 100644 dts/bindings/rng/nordic,nrf-prng.yaml diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 93259180e43..f5513a288ab 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -24,6 +24,7 @@ zephyr,sram = &cpuapp_data; zephyr,shell-uart = &uart136; zephyr,bt-hci-ipc = &ipc0; + zephyr,entropy = &prng; }; aliases { @@ -88,6 +89,11 @@ label = "Green LED 3"; }; }; + + prng: prng { + compatible = "nordic,entropy-prng"; + status = "okay"; + }; }; &cpuapp_ram0x_region { diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index c0b9c0b47b7..d72aa791091 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -25,6 +25,12 @@ zephyr,sram = &cpurad_ram0; zephyr,shell-uart = &uart135; zephyr,bt-hci-ipc = &ipc0; + zephyr,entropy = &prng; + }; + + prng: prng { + compatible = "nordic,entropy-prng"; + status = "okay"; }; }; diff --git a/drivers/entropy/CMakeLists.txt b/drivers/entropy/CMakeLists.txt index c3d37e1461a..1ea31981857 100644 --- a/drivers/entropy/CMakeLists.txt +++ b/drivers/entropy/CMakeLists.txt @@ -34,6 +34,13 @@ zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_SE entropy_gecko_se. zephyr_library_sources_ifdef(CONFIG_ENTROPY_PSA_CRYPTO_RNG entropy_psa_crypto.c) zephyr_library_sources_ifdef(CONFIG_ENTROPY_NPCX_DRBG entropy_npcx_drbg.c) +if (CONFIG_FAKE_ENTROPY_NRF_PRNG) + zephyr_library_sources(fake_entropy_nrf_prng.c) + + message(WARNING "\nA nRF PRNG is used, which does not produce real random bits." + "This is not secure and should therefore never be used in a product.") +endif() + if (CONFIG_BUILD_WITH_TFM) target_include_directories(${ZEPHYR_CURRENT_LIBRARY} PRIVATE $/api_ns/interface/include diff --git a/drivers/entropy/Kconfig b/drivers/entropy/Kconfig index 34c020256bf..b1479756460 100644 --- a/drivers/entropy/Kconfig +++ b/drivers/entropy/Kconfig @@ -36,6 +36,7 @@ source "drivers/entropy/Kconfig.neorv32" source "drivers/entropy/Kconfig.bt_hci" source "drivers/entropy/Kconfig.psa_crypto" source "drivers/entropy/Kconfig.npcx" +source "drivers/entropy/Kconfig.nrf_prng" config ENTROPY_HAS_DRIVER bool diff --git a/drivers/entropy/Kconfig.nrf_prng b/drivers/entropy/Kconfig.nrf_prng new file mode 100644 index 00000000000..e1b1a9ab4fe --- /dev/null +++ b/drivers/entropy/Kconfig.nrf_prng @@ -0,0 +1,19 @@ +# nRF fake entropy prng generator driver configuration + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if ENTROPY_GENERATOR + +config FAKE_ENTROPY_NRF_PRNG + bool "A fake nRF entropy driver" + default y + depends on DT_HAS_NORDIC_ENTROPY_PRNG_ENABLED + depends on SOC_SERIES_NRF54HX + select ENTROPY_HAS_DRIVER + help + This is a super simple PRNG driver that can be used on nRF platforms that + do not have an entropy source. + This is NOT SAFE to use for cryptographic operations! + +endif diff --git a/drivers/entropy/fake_entropy_nrf_prng.c b/drivers/entropy/fake_entropy_nrf_prng.c new file mode 100644 index 00000000000..8624c844405 --- /dev/null +++ b/drivers/entropy/fake_entropy_nrf_prng.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#define DT_DRV_COMPAT nordic_entropy_prng + +/* This file implements a pseudo-RNG + * https://vigna.di.unimi.it/xorshift/xoshiro128plus.c + */ + +static uint32_t s[4]; + +static inline uint32_t rotl(const uint32_t x, int k) +{ + return (x << k) | (x >> (32 - k)); +} + +static uint32_t rng_next(void) +{ + const uint32_t result = rotl(s[0] + s[3], 7) + s[0]; + + const uint32_t t = s[1] << 9; + + s[2] ^= s[0]; + s[3] ^= s[1]; + s[1] ^= s[2]; + s[0] ^= s[3]; + + s[2] ^= t; + + s[3] = rotl(s[3], 11); + + return result; +} + +static int entropy_prng_get_entropy(const struct device *dev, uint8_t *buffer, uint16_t length) +{ + ARG_UNUSED(dev); + + while (length) { + /* + * Note that only 1 thread (Zephyr thread or HW models), runs at + * a time, therefore there is no need to use random_r() + */ + uint32_t value = rng_next(); + + size_t to_copy = MIN(length, sizeof(long)); + + memcpy(buffer, &value, to_copy); + buffer += to_copy; + length -= to_copy; + } + + return 0; +} + +static int entropy_prng_get_entropy_isr(const struct device *dev, uint8_t *buf, uint16_t len, + uint32_t flags) +{ + ARG_UNUSED(flags); + + int err; + + /* + * entropy_prng_get_entropy() is also safe for ISRs + * and always produces data. + */ + err = entropy_prng_get_entropy(dev, buf, len); + if (err < 0) { + return err; + } else { + return len; + } +} + +static int entropy_prng_init(const struct device *dev) +{ + ARG_UNUSED(dev); + + /* Picked some arbitrary initial seed. */ + s[0] = 0xAF568BC0; + s[1] = 0xAC34307E; + s[2] = 0x9B7F6DD1; + s[3] = 0xD84319FC; + return 0; +} + +static const struct entropy_driver_api entropy_prng_api_funcs = { + .get_entropy = entropy_prng_get_entropy, .get_entropy_isr = entropy_prng_get_entropy_isr}; + +DEVICE_DT_INST_DEFINE(0, entropy_prng_init, NULL, NULL, NULL, PRE_KERNEL_1, + CONFIG_ENTROPY_INIT_PRIORITY, &entropy_prng_api_funcs); diff --git a/dts/bindings/rng/nordic,nrf-prng.yaml b/dts/bindings/rng/nordic,nrf-prng.yaml new file mode 100644 index 00000000000..8936393a0b6 --- /dev/null +++ b/dts/bindings/rng/nordic,nrf-prng.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +description: This is a super simple PRNG + +compatible: "nordic,entropy-prng" + +include: base.yaml From e7aa7008b0c1c668ed4d4a20ee4c5662b57faa31 Mon Sep 17 00:00:00 2001 From: Piotr Kosycarz Date: Wed, 10 Apr 2024 15:32:12 +0200 Subject: [PATCH 2393/2402] [nrf noup] test-spec: include nrf54 boards in low-level test trigger All changes in nrf54 boards will trigger low-level testing. Signed-off-by: Piotr Kosycarz (cherry picked from commit 3c68e19f4eb40c472b8be4fdff067c2519f7379f) --- .github/test-spec.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/test-spec.yml b/.github/test-spec.yml index a4776a433f3..876e7eeff04 100644 --- a/.github/test-spec.yml +++ b/.github/test-spec.yml @@ -293,6 +293,7 @@ "CI-test-low-level": - "dts/**/*" + - "boards/nordic/nrf54*/**/*" - "include/zephyr/**/*" - "tests/arch/**/*" - "arch/**/*" From c8cc6634d2bd1c03e150342b7b0568c0eb191c92 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Fri, 12 Apr 2024 14:13:12 +0200 Subject: [PATCH 2394/2402] [nrf noup] boards: add nrf54l15/nrf54l15/cpuapp/ns as board variant This commit adds the nRF54l15//nrf54l15/cpuapp/ns board variant to sdk-zephyr. It allows to build nRF54l15pdk with TF-M in nRF Connect SDK. This is done as a nrf noup patch as the out-of-tree board extension feature is not available. When zephyrproject-rtos/zephyr#69548 is completed, then this commit can be reverted and the variant be placed in sdk-nrf repository. Signed-off-by: Torsten Rasmussen --- boards/nordic/nrf54l15pdk/Kconfig | 43 ++++++ boards/nordic/nrf54l15pdk/Kconfig.defconfig | 18 +++ boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk | 2 +- boards/nordic/nrf54l15pdk/board.cmake | 8 ++ boards/nordic/nrf54l15pdk/board.yml | 3 + ...rf54l15pdk_nrf54l15_cpuapp_ns-pinctrl.dtsi | 38 +++++ .../nrf54l15pdk_nrf54l15_cpuapp_ns.dts | 132 ++++++++++++++++++ .../nrf54l15pdk_nrf54l15_cpuapp_ns.yaml | 22 +++ .../nrf54l15pdk_nrf54l15_cpuapp_ns_defconfig | 37 +++++ 9 files changed, 302 insertions(+), 1 deletion(-) create mode 100644 boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns-pinctrl.dtsi create mode 100644 boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.dts create mode 100644 boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.yaml create mode 100644 boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns_defconfig diff --git a/boards/nordic/nrf54l15pdk/Kconfig b/boards/nordic/nrf54l15pdk/Kconfig index 638ce57499d..db822a14820 100644 --- a/boards/nordic/nrf54l15pdk/Kconfig +++ b/boards/nordic/nrf54l15pdk/Kconfig @@ -11,3 +11,46 @@ config BOARD_ENABLE_DCDC default y endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP + +if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS + +# TODO: Remove the options bellow when (NCSDK-25023) is done +config NRF_SPU_FLASH_REGION_SIZE + hex + default 0x4000 + # This option does not apply to 54, but we pretend the HW has this limitation + # for now for easier porting. NCSDK-25023 + help + FLASH region size for the NRF_SPU peripheral. For nrf54 the + region size is configurable per-region so this option does + not apply. + +config NRF_SPU_FLASH_REGION_ALIGNMENT + hex + default 0x4000 + # This option does not apply to 54, but we pretend the HW has this limitation + # for now for easier porting. NCSDK-25023 + help + FLASH region size for the NRF_SPU peripheral. For nrf54 the + region size is configurable per-region so this option does + not apply. + +config NRF_SPU_RAM_REGION_SIZE + hex + default 0x2000 + # This HW limitation does not apply to 54, but we pretend + # it does for now for easier porting. NCSDK-25023 + help + RAM region size for the NRF_SPU peripheral. For nrf54 the + region size is configurable per-region so this option does + not apply. + + +config NRF_SPU_RAM_REGION_ALIGNMENT + hex + default 0x1000 + help + RAM regions must be aligned to this value due to SPU HW + limitations. + +endif #BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS diff --git a/boards/nordic/nrf54l15pdk/Kconfig.defconfig b/boards/nordic/nrf54l15pdk/Kconfig.defconfig index 1c83abbb020..3203a5b97ea 100644 --- a/boards/nordic/nrf54l15pdk/Kconfig.defconfig +++ b/boards/nordic/nrf54l15pdk/Kconfig.defconfig @@ -10,3 +10,21 @@ config ROM_START_OFFSET default 0x800 if BOOTLOADER_MCUBOOT endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP + +if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS + +config BT_CTLR + default BT + +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS + +# By default, if we build with TF-M, instruct build system to +# flash the combined TF-M (Secure) & Zephyr (Non Secure) image +config TFM_FLASH_MERGED_BINARY + default y + depends on BUILD_WITH_TFM + +endif #BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS diff --git a/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk b/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk index 12f6e2efd48..36ee21a55b6 100644 --- a/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk +++ b/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_NRF54L15PDK - select SOC_NRF54L15_ENGA_CPUAPP if BOARD_NRF54L15PDK_NRF54L15_CPUAPP + select SOC_NRF54L15_ENGA_CPUAPP if BOARD_NRF54L15PDK_NRF54L15_CPUAPP || BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS diff --git a/boards/nordic/nrf54l15pdk/board.cmake b/boards/nordic/nrf54l15pdk/board.cmake index 2107fb5d71e..5a1e4b3221d 100644 --- a/boards/nordic/nrf54l15pdk/board.cmake +++ b/boards/nordic/nrf54l15pdk/board.cmake @@ -3,6 +3,14 @@ board_runner_args(jlink "--device=cortex-m33" "--speed=4000") +if(BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf54l15pdk/board.yml b/boards/nordic/nrf54l15pdk/board.yml index 3b0fc447385..69b51223209 100644 --- a/boards/nordic/nrf54l15pdk/board.yml +++ b/boards/nordic/nrf54l15pdk/board.yml @@ -3,6 +3,9 @@ board: vendor: nordic socs: - name: nrf54l15 + variants: + - name: ns + cpucluster: cpuapp revision: format: major.minor.patch default: "0.2.1" diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns-pinctrl.dtsi b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns-pinctrl.dtsi new file mode 100644 index 00000000000..b4b924e90ef --- /dev/null +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns-pinctrl.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +&pinctrl { + uart20_default: uart20_default { + group1 { + psels = , + ; + }; + }; + + uart20_sleep: uart20_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + uart30_default: uart30_default { + group1 { + psels = , + ; + }; + }; + + uart30_sleep: uart30_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + +}; diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.dts new file mode 100644 index 00000000000..49fd1ac0ece --- /dev/null +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.dts @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +/dts-v1/; +#include +#include "nrf54l15pdk_nrf54l15_cpuapp_ns-pinctrl.dtsi" + +/ { + chosen { + zephyr,console = &uart20; + /* TODO: NCSDK-24862: We don't support configuring RRAM and SRAM + * regions in the DTS file yet. The partition manager configures + * these regions now. + */ + zephyr,shell-uart = &uart20; + zephyr,flash = &rram0; + zephyr,sram = &sram0; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + led1: led_1 { + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + led2: led_2 { + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + led3: led_3 { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio1 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + button2: button_2 { + gpios = <&gpio2 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + button3: button_3 { + gpios = <&gpio2 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + }; +}; + +&uart20 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart30 { + /* Disable so that TF-M can use this UART */ + status = "disabled"; + + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&grtc { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.yaml b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.yaml new file mode 100644 index 00000000000..460803eaa53 --- /dev/null +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +identifier: nrf54l15pdk/nrf54l15/cpuapp/ns +name: nRF54l15-PDK-nRF54l15-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 256 +flash: 1524 +supported: + - adc + - gpio + - i2c + - spi + - counter + - watchdog + - adc + - i2s diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns_defconfig b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns_defconfig new file mode 100644 index 00000000000..ec01756bfd4 --- /dev/null +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns_defconfig @@ -0,0 +1,37 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 54l +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y + +# Enable GPIO +CONFIG_GPIO=y + +# NCSDK-26634: Rollback protection is not supported yet +CONFIG_TFM_PS_ROLLBACK_PROTECTION=n + +# NCSDK-22600: Built-in keys are not supported yet. +CONFIG_TFM_CRYPTO_BUILTIN_KEYS=n + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y From 59220de44c52c2f2772ae7647738dbeafb770af1 Mon Sep 17 00:00:00 2001 From: Piotr Kosycarz Date: Wed, 17 Apr 2024 14:05:02 +0200 Subject: [PATCH 2395/2402] [nrf noup] boards: nordic: nrf54l15pdk: enable HWFC Define RTS and CTS pins. This commit can be dropped when those upstream changes will be included: https://github.com/zephyrproject-rtos/zephyr/pull/70892 https://github.com/zephyrproject-rtos/zephyr/pull/71605 Signed-off-by: Piotr Kosycarz (cherry picked from commit c22c9c258ce776b88dac8a917ab13f46a4c7db85) --- .../nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi | 22 +++++++++++++++---- .../nrf54l15pdk_nrf54l15_cpuapp.dts | 1 + 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi index 02b02bc8171..96c53f948fc 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi @@ -7,14 +7,21 @@ uart20_default: uart20_default { group1 { psels = , - ; + ; + }; + group2 { + psels = , + ; + bias-pull-up; }; }; uart20_sleep: uart20_sleep { group1 { psels = , - ; + , + , + ; low-power-enable; }; }; @@ -22,14 +29,21 @@ uart30_default: uart30_default { group1 { psels = , - ; + ; + }; + group2 { + psels = , + ; + bias-pull-up; }; }; uart30_sleep: uart30_sleep { group1 { psels = , - ; + , + , + ; low-power-enable; }; }; diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts index c801ddc8dc5..0b9e76ff083 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -96,6 +96,7 @@ pinctrl-0 = <&uart20_default>; pinctrl-1 = <&uart20_sleep>; pinctrl-names = "default", "sleep"; + hw-flow-control; }; &uart30 { From a41c7c315b0914cbbe54796ce34a5373c35bae50 Mon Sep 17 00:00:00 2001 From: Andrzej Puzdrowski Date: Fri, 12 Apr 2024 17:53:35 +0200 Subject: [PATCH 2396/2402] [nrf noup] samples/**/smp_svr: testcase of nrf54l15pdk with ext-flash Added description of sample testcase for building smp_svr with support of secondary partition in on PDK spi_nor flash. Signed-off-by: Andrzej Puzdrowski (cherry picked from commit 849d51f27998807371199e36cf7995652b4864a1) --- samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml index 04e19dfb48e..81b06ca5634 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml +++ b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml @@ -104,3 +104,15 @@ tests: - mg100 integration_platforms: - nrf52840dk/nrf52840 + sample.mcumgr.smp_svr.bt.nrf54l15pdk.ext_flash: + extra_args: + - OVERLAY_CONFIG="overlay-bt.conf" + - DTC_OVERLAY_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_ext_flash.overlay" + - mcuboot_CONF_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_ext_flash.conf" + - mcuboot_EXTRA_DTC_OVERLAY_FILE="boards/nrf54l15pdk_nrf54l15_cpuapp_ext_flash.overlay" + extra_configs: + - CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y + platform_allow: + - nrf54l15pdk/nrf54l15/cpuapp + integration_platforms: + - nrf54l15pdk/nrf54l15/cpuapp From 9a0218b0560aa2613ddf9e22c77dd237d5412bfa Mon Sep 17 00:00:00 2001 From: Markus Swarowsky Date: Fri, 19 Apr 2024 12:58:47 +0200 Subject: [PATCH 2397/2402] [nrf noup] samples: psa_crypto: Remove support for Nordic boards We have our own psa crypto samples to show how to used PSA crypto with NCS. This sample still uses CONFIG_MBEDTLS_BUILTIN which is not supported anymore, therefore removing the support for it in NCS. Ref: NCSDK-17944 Signed-off-by: Markus Swarowsky --- samples/tfm_integration/psa_crypto/sample.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/samples/tfm_integration/psa_crypto/sample.yaml b/samples/tfm_integration/psa_crypto/sample.yaml index 3f25acf88f3..ec0a1f8dd3f 100644 --- a/samples/tfm_integration/psa_crypto/sample.yaml +++ b/samples/tfm_integration/psa_crypto/sample.yaml @@ -12,7 +12,6 @@ tests: - csr - mcuboot platform_allow: mps2/an521/cpu0/ns v2m_musca_s1/musca_s1/ns - nrf5340dk/nrf5340/cpuapp/ns nrf9160dk/nrf9160/ns stm32l562e_dk/stm32l562xx/ns bl5340_dvk/nrf5340/cpuapp/ns harness: console harness_config: From b0b3a063009d891c80c7e0448145034c2cd43e6b Mon Sep 17 00:00:00 2001 From: Andrzej Puzdrowski Date: Fri, 12 Apr 2024 11:42:38 +0200 Subject: [PATCH 2398/2402] [nrf noup] boards/nordic/nrf54l15pdk: added mx25r64 flash DTS Added DTS of PDK's mx25r64 flash memory. Memory is described under spi00 peripheral and can be controlled used flash spi_nor driver. To be reverted once upstream PR can be applied cleanly https://github.com/zephyrproject-rtos/zephyr/pull/71425 Signed-off-by: Andrzej Puzdrowski --- .../nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi | 17 ++++++++++++ .../nrf54l15pdk_nrf54l15_cpuapp.dts | 27 +++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi index 96c53f948fc..31c2f820f3f 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi @@ -47,4 +47,21 @@ low-power-enable; }; }; + + spi0_default: spi0_default { + group1 { + psels = , + , + ; + }; + }; + + spi0_sleep: spi0_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; }; diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts index 0b9e76ff083..e6ef815e783 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -77,6 +77,7 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; + spi-flash0 = &mx25r64; }; }; @@ -174,3 +175,29 @@ &clock { status = "okay"; }; + +&spi00 { + status = "okay"; + cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; + + mx25r64: mx25r6435f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + status = "disabled"; + spi-max-frequency = <8000000>; + jedec-id = [c2 28 17]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + }; +}; From 1970b3c5484050540a2705af7a47eb14038c6764 Mon Sep 17 00:00:00 2001 From: Grzegorz Chwierut Date: Wed, 24 Apr 2024 12:22:51 +0200 Subject: [PATCH 2399/2402] [nrf noup] boards: nrf54l15pdk: ROM_START_OFFSET Sets up default for builds with partition manager. Signed-off-by: Mateusz Michalek Signed-off-by: Grzegorz Chwierut --- boards/nordic/nrf54l15pdk/Kconfig.defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/nordic/nrf54l15pdk/Kconfig.defconfig b/boards/nordic/nrf54l15pdk/Kconfig.defconfig index 3203a5b97ea..87b8c1d0cc3 100644 --- a/boards/nordic/nrf54l15pdk/Kconfig.defconfig +++ b/boards/nordic/nrf54l15pdk/Kconfig.defconfig @@ -7,6 +7,7 @@ config BT_CTLR default BT config ROM_START_OFFSET + default 0 if PARTITION_MANAGER_ENABLED default 0x800 if BOOTLOADER_MCUBOOT endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP From 00bf0097c3a178b2b223fa5c9d3378ae2d96d02f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karol=20Laso=C5=84czyk?= Date: Wed, 7 Feb 2024 14:21:59 +0100 Subject: [PATCH 2400/2402] [nrf noup] boards: Enable ADC in nRF54L15 PDK configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Simple enabling adc node. Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/68692 Applied as noup because it can't be applied cleanly. Signed-off-by: Karol Lasończyk (cherry picked from commit 88adda3b14f726645c0a3ebac6d6fab571144f11) --- boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts index e6ef815e783..f64952ba886 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -201,3 +201,7 @@ t-exit-dpd = <35000>; }; }; + +&adc { + status = "okay"; +}; From 15cc59d1c2507d330c1eb58c359d3fc681b961a6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karol=20Laso=C5=84czyk?= Date: Fri, 26 Apr 2024 16:32:56 +0200 Subject: [PATCH 2401/2402] [nrf noup] boards: nordic: Add PWM support for LEDs on nRF54 DKs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds support for first possible LED to be connected with HW PWM. Upstream PR: https://github.com/zephyrproject-rtos/zephyr/pull/72010 Merged as noup because of conflicts. Signed-off-by: Karol Lasończyk (cherry picked from commit 382a1ee791e3637b5b7d25f22905017c24997438) --- .../nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi | 13 +++++++++++++ .../nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 15 +++++++++++++++ .../nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi | 13 +++++++++++++ .../nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts | 15 +++++++++++++++ .../nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay | 15 +++++++++++++++ 5 files changed, 71 insertions(+) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi index 6c6da3fa747..0c842057d64 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi @@ -50,4 +50,17 @@ ; }; }; + + /omit-if-no-ref/ pwm120_default: pwm120_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ pwm120_sleep: pwm120_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; }; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index f5513a288ab..5406d113833 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -32,6 +32,7 @@ led1 = &led1; led2 = &led2; led3 = &led3; + pwm-led0 = &pwm_led0; sw0 = &button0; sw1 = &button1; sw2 = &button2; @@ -90,6 +91,13 @@ }; }; + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm120 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + prng: prng { compatible = "nordic,entropy-prng"; status = "okay"; @@ -194,3 +202,10 @@ ipc0: &cpuapp_cpurad_ipc { pinctrl-names = "default", "sleep"; hw-flow-control; }; + +&pwm120 { + status = "okay"; + pinctrl-0 = <&pwm120_default>; + pinctrl-1 = <&pwm120_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi index 31c2f820f3f..89ad7599870 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi @@ -64,4 +64,17 @@ low-power-enable; }; }; + + /omit-if-no-ref/ pwm20_default: pwm20_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; }; diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts index f64952ba886..395f92d638c 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts @@ -43,6 +43,13 @@ }; }; + pwmleds { + compatible = "pwm-leds"; + pwm_led1: pwm_led_1 { + pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + buttons { compatible = "gpio-keys"; button0: button_0 { @@ -72,6 +79,7 @@ led1 = &led1; led2 = &led2; led3 = &led3; + pwm-led0 = &pwm_led1; watchdog0 = &wdt30; sw0 = &button0; sw1 = &button1; @@ -205,3 +213,10 @@ &adc { status = "okay"; }; + +&pwm20 { + status = "okay"; + pinctrl-0 = <&pwm20_default>; + pinctrl-1 = <&pwm20_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay index d8262dde994..99ba6ff3062 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay @@ -36,3 +36,18 @@ &button3 { gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; }; + +&pinctrl { + /omit-if-no-ref/ pwm20_default: pwm20_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; +}; From 34de08466ee7197576cfa11663b264d0fec57c9a Mon Sep 17 00:00:00 2001 From: Jan Tore Guggedal Date: Tue, 30 Apr 2024 11:16:03 +0200 Subject: [PATCH 2402/2402] [nrf noup] drivers: flash: Fix spi_nor_set_address_mode and exit_dpd There was unneeded check for enter_4byte_addr_exist, that would be set by existence of enter-4byte-addr property, as the function is generic DTS/SFPD implementation and parsed parameter to obtain the information. The check was breaking usage of SFDP as with SFDP the parameter may never be provided. The commit removes the check and the enter_4byte_addr_exist, as it does not seem needed for anything. The incorrectly placed conditional compilation for DPD exit sequence has broken DPD exit in case where such sequence is not needed. Signed-off-by: Dominik Ermel Signed-off-by: Jan Tore Guggedal --- drivers/flash/spi_nor.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/flash/spi_nor.c b/drivers/flash/spi_nor.c index 39741df085f..0b4ab8fba0d 100644 --- a/drivers/flash/spi_nor.c +++ b/drivers/flash/spi_nor.c @@ -155,7 +155,6 @@ struct spi_nor_config { bool dpd_exist:1; bool dpd_wakeup_sequence_exist:1; bool mxicy_mx25r_power_mode_exist:1; - bool enter_4byte_addr_exist:1; bool reset_gpios_exist:1; bool requires_ulbpr_exist:1; bool wp_gpios_exist:1; @@ -520,10 +519,11 @@ static int exit_dpd(const struct device *const dev) const struct spi_nor_config *cfg = dev->config; if (cfg->dpd_exist) { +#if ANY_INST_HAS_DPD delay_until_exit_dpd_ok(dev); -#if ANY_INST_HAS_DPD_WAKEUP_SEQUENCE if (cfg->dpd_wakeup_sequence_exist) { +#if ANY_INST_HAS_DPD_WAKEUP_SEQUENCE /* Assert CSn and wait for tCRDP. * * Unfortunately the SPI API doesn't allow us to @@ -536,6 +536,7 @@ static int exit_dpd(const struct device *const dev) /* Deassert CSn and wait for tRDP */ k_sleep(K_MSEC(cfg->t_rdp_ms)); +#endif /* DPD_WAKEUP_SEQUENCE */ } else { ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_RDPD); @@ -547,7 +548,7 @@ static int exit_dpd(const struct device *const dev) } #endif /* T_EXIT_DPD */ } -#endif /* DPD_WAKEUP_SEQUENCE */ +#endif /* ANY_INST_HAS_DPD */ } return ret; } @@ -1036,10 +1037,8 @@ static int spi_nor_read_jedec_id(const struct device *dev, static int spi_nor_set_address_mode(const struct device *dev, uint8_t enter_4byte_addr) { - const struct spi_nor_config *cfg = dev->config; - int ret = -ENOSYS; + int ret = 0; - if (cfg->enter_4byte_addr_exist) { /* Do nothing if not provided (either no bits or all bits * set). */ @@ -1074,7 +1073,6 @@ static int spi_nor_set_address_mode(const struct device *dev, } release_device(dev); - } return ret; } @@ -1664,7 +1662,6 @@ static const struct flash_driver_api spi_nor_api = { .dpd_exist = DT_INST_PROP(idx, has_dpd), \ .dpd_wakeup_sequence_exist = DT_INST_NODE_HAS_PROP(idx, dpd_wakeup_sequence), \ .mxicy_mx25r_power_mode_exist = DT_INST_NODE_HAS_PROP(idx, mxicy_mx25r_power_mode), \ - .enter_4byte_addr_exist = DT_INST_NODE_HAS_PROP(idx, enter_4byte_addr), \ .reset_gpios_exist = DT_INST_NODE_HAS_PROP(idx, reset_gpios), \ .requires_ulbpr_exist = DT_INST_PROP(idx, requires_ulbpr), \ .wp_gpios_exist = DT_INST_NODE_HAS_PROP(idx, wp_gpios), \

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zDTUuv!J>om`*B{fH2O^MV+NusCkMttviqOO&%MXZdxE#wriJdTXcsop zJ8KQEg|4Wpmh9_ zs3Ji`P5j(@F*qF_wpk6P{@?_HqP>oztN>b-NmG?`0Zl5H<5-A*m{F~iBZ#LdSK!YLMtWKUKIZ1qM;YhInsh29Y=ZyuDp?TKzlY>a zm{Hg_85exi4n~mj**dAHSFSpItet5LJUt!2VXtzOq!S)&b3M4HP~&E!X@~+Qi8Xnh Y18n4Coco++ChzM=04JU>oB#j-0GUhq$N&HU literal 0 HcmV?d00001 diff --git a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki-pinctrl.dtsi b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki-pinctrl.dtsi new file mode 100644 index 00000000000..983bdb1ac6d --- /dev/null +++ b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki-pinctrl.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "pinctrl/m2l31ki-pinctrl.h" + +&pinctrl { + uart0_default: uart0_default { + group0 { + pinmux = , + ; + }; + }; + + /* TX/RX/RTS/CTS/RST --> D1/D0/A2/A3/D2 --> PB3/PB2/PB8/PB9/PC9 */ + uart1_default: uart1_default { + group0 { + pinmux = , + , + , + , + ; + }; + }; +}; diff --git a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.dts b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.dts new file mode 100644 index 00000000000..b874a0eb78e --- /dev/null +++ b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.dts @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "numaker_m2l31ki-pinctrl.dtsi" +#include + +/ { + model = "Nuvoton NuMaker M2L31KI board"; + compatible = "nuvoton,numaker-m2l31ki"; + + aliases { + led0 = &red_led; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpioc 14 GPIO_ACTIVE_LOW>; + label = "User LD1"; + }; + }; +}; + +&scc { + /* For USB 1.1 Host/Device/OTG, configure to 192MHz, which can generate necessary 48MHz. */ + /* For USB 2.0 Host/Device/OTG or no USB application, comment out to use default. */ + core-clock = ; +}; + +&gpioc { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00008000>; + }; + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x00008000 0x00038000>; + }; + slot1_partition: partition@40000 { + label = "image-1"; + reg = <0x00040000 0x00038000>; + }; + storage_partition: partition@78000 { + label = "storage"; + reg = <0x00078000 0x00008000>; + }; + }; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(168)>; +}; + +&uart0 { + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml new file mode 100644 index 00000000000..4276ce3573c --- /dev/null +++ b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +identifier: numaker_m2l31ki +name: NUVOTON NUMAKER-M2L31KI Kit +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 168 +flash: 512 +supported: + - gpio +vendor: nuvoton diff --git a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki_defconfig b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki_defconfig new file mode 100644 index 00000000000..e59234cb73c --- /dev/null +++ b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_PINCTRL=y +CONFIG_GPIO=y + +# Enable system clock controller driver +CONFIG_CLOCK_CONTROL=y +CONFIG_CLOCK_CONTROL_NUMAKER_SCC=y + +# Enable MPU +CONFIG_ARM_MPU=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000 + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable RMC +CONFIG_FLASH=y diff --git a/boards/nuvoton/numaker_m2l31ki/support/openocd.cfg b/boards/nuvoton/numaker_m2l31ki/support/openocd.cfg new file mode 100644 index 00000000000..c393f756c4d --- /dev/null +++ b/boards/nuvoton/numaker_m2l31ki/support/openocd.cfg @@ -0,0 +1,2 @@ +source [find interface/nulink.cfg] +source [find target/numicro.cfg] From de41005fe93a6539459b7191b2233989886da46b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alperen=20=C5=9Eener?= Date: Wed, 6 Mar 2024 09:51:14 +0100 Subject: [PATCH 1117/2402] tests: bluetooth: Update ICS for Mesh v1.1, DFU v1.0 and MBT v1.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Mesh v1.1, DFU v1.0 and MBT v1.0 are supported by default in the stack. In this regard, this commit updates the ICS file and Launch Studio Project file to reflect supported features. Signed-off-by: Alperen Şener --- .../ICS_Zephyr_Bluetooth_Host.pts | 192 +++++++++++++++++- .../Project_Zephyr_Bluetooth_Host.bls | 192 +++++++++++++++++- 2 files changed, 366 insertions(+), 18 deletions(-) diff --git a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts index 3333e4bff11..9df1f912dc5 100644 --- a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts +++ b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts @@ -1,6 +1,6 @@ - 225924 + 234540 Zephyr_Bluetooth_Host @@ -2212,10 +2212,46 @@ MESH + + 11
    + 11 +     + + 11
    + 20 +     + + 4
    + 14 +     + + 11
    + 12 +     + + 11
    + 23 +     + + 11
    + 24 +     + + 4
    + 15 +     12
    12     + + 12
    + 8 +     + + 10
    + 5 +     18
    12 @@ -2224,29 +2260,81 @@ 1a
    2     + + 11
    + 18 +     + + 11
    + 14 +     + + 11
    + 16 +     4
    13     + + 0
    + 2 +     + + 11
    + 6 +     + + 11
    + 19 +     2
    3     - 0a
    - 3 + 18
    + 13     - 0
    - 1 + 11
    + 15     - 0a
    - 1 + 11
    + 13     - 0a
    - 2 + 12
    + 7 +     + + 11
    + 17 +     + + 4
    + 16 +     + + 11
    + 5 +     + + 11
    + 22 +     + + 11
    + 21 +     + + 12
    + 11 +     + + 4
    + 17     2
    @@ -9127,5 +9215,91 @@ 6     + + MBT + + 10
    + 1 +     + + 3
    + 1 +     + + 20
    + 2 +     + + 20
    + 1 +     + + 3
    + 2 +     + + 0
    + 1 +     + + 10
    + 2 +     +     + + DFU + + 3
    + 3 +     + + 3
    + 2 +     + + 22
    + 3 +     + + 10
    + 1 +     + + 11
    + 1 +     + + 30
    + 1 +     + + 0
    + 1 +     + + 11
    + 2 +     + + 3
    + 1 +     + + 20
    + 1 +     + + 22
    + 1 +     + + 21
    + 2 +     + + 21
    + 1 +     +     \ No newline at end of file diff --git a/tests/bluetooth/qualification/Project_Zephyr_Bluetooth_Host.bls b/tests/bluetooth/qualification/Project_Zephyr_Bluetooth_Host.bls index b08c4172cf2..c92ffe03656 100644 --- a/tests/bluetooth/qualification/Project_Zephyr_Bluetooth_Host.bls +++ b/tests/bluetooth/qualification/Project_Zephyr_Bluetooth_Host.bls @@ -1,6 +1,6 @@  - 225924 + 234540 Zephyr_Bluetooth_Host 83 @@ -2215,10 +2215,46 @@ MESH + + 11
    + 11 +     + + 11
    + 20 +     + + 4
    + 14 +     + + 11
    + 12 +     + + 11
    + 23 +     + + 11
    + 24 +     + + 4
    + 15 +     12
    12     + + 12
    + 8 +     + + 10
    + 5 +     18
    12 @@ -2227,29 +2263,81 @@ 1a
    2     + + 11
    + 18 +     + + 11
    + 14 +     + + 11
    + 16 +     4
    13     + + 0
    + 2 +     + + 11
    + 6 +     + + 11
    + 19 +     2
    3     - 0a
    - 3 + 18
    + 13     - 0
    - 1 + 11
    + 15     - 0a
    - 1 + 11
    + 13     - 0a
    - 2 + 12
    + 7 +     + + 11
    + 17 +     + + 4
    + 16 +     + + 11
    + 5 +     + + 11
    + 22 +     + + 11
    + 21 +     + + 12
    + 11 +     + + 4
    + 17     2
    @@ -9130,5 +9218,91 @@ 6     + + MBT + + 10
    + 1 +     + + 3
    + 1 +     + + 20
    + 2 +     + + 20
    + 1 +     + + 3
    + 2 +     + + 0
    + 1 +     + + 10
    + 2 +     +     + + DFU + + 3
    + 3 +     + + 3
    + 2 +     + + 22
    + 3 +     + + 10
    + 1 +     + + 11
    + 1 +     + + 30
    + 1 +     + + 0
    + 1 +     + + 11
    + 2 +     + + 3
    + 1 +     + + 20
    + 1 +     + + 22
    + 1 +     + + 21
    + 2 +     + + 21
    + 1 +     +     \ No newline at end of file From 2396b01b1ea2b0b6a61591155508cf19cd9d367c Mon Sep 17 00:00:00 2001 From: Wafer Xie Date: Wed, 20 Mar 2024 14:40:31 +0000 Subject: [PATCH 1118/2402] drivers: eth: stellaris: Fix driver poll all packets from ethernet The number of interrupts received by the driver maybe less than the number of data packets received by Ethernet, so the driver should read the packets number from the register REG_MACNP value. Signed-off-by: Wafer Xie --- drivers/ethernet/eth_stellaris.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/ethernet/eth_stellaris.c b/drivers/ethernet/eth_stellaris.c index 81dc9ac92d2..30de5d47ad2 100644 --- a/drivers/ethernet/eth_stellaris.c +++ b/drivers/ethernet/eth_stellaris.c @@ -202,7 +202,7 @@ static struct net_pkt *eth_stellaris_rx_pkt(const struct device *dev, return NULL; } -static void eth_stellaris_rx(const struct device *dev) +static int eth_stellaris_rx(const struct device *dev) { struct eth_stellaris_runtime *dev_data = dev->data; struct net_if *iface = dev_data->iface; @@ -219,19 +219,21 @@ static void eth_stellaris_rx(const struct device *dev) goto pkt_unref; } - return; + return 0; pkt_unref: net_pkt_unref(pkt); err_mem: eth_stellaris_rx_error(iface); + return -EIO; } static void eth_stellaris_isr(const struct device *dev) { struct eth_stellaris_runtime *dev_data = dev->data; int isr_val = sys_read32(REG_MACRIS); + int num_packets; uint32_t lock; lock = irq_lock(); @@ -240,7 +242,18 @@ static void eth_stellaris_isr(const struct device *dev) sys_write32(isr_val, REG_MACRIS); if (isr_val & BIT_MACRIS_RXINT) { - eth_stellaris_rx(dev); + /* + * When multiple packets are received by the Ethernet, + * only one interrupt may be dispatched to the driver + * Therefore, it is necessary to obtain the register NP value + * to get how many packets are in the Ethernet. + */ + num_packets = sys_read32(REG_MACNP); + for (int i = 0; i < np; i++) { + if (eth_stellaris_rx(dev) != 0) { + break; + } + } } if (isr_val & BIT_MACRIS_TXEMP) { From 292aafef5a097e3e9e95a05f0beef820f4ba6702 Mon Sep 17 00:00:00 2001 From: Marcin Szymczyk Date: Thu, 14 Mar 2024 16:57:42 +0100 Subject: [PATCH 1119/2402] arch: riscv: disable interrupts before `wfi` According to RISC-V Instruction Set Manual Chapter 3.3.2: "The operation of WFI must be unaffected by the global interrupt bits in mstatus [...] WFI is also required to resume execution for locally enabled interrupts pending at any privilege level, regardless of the global interrupt enable at each privilege level." Disabling interrupts before executing `wfi` prevents a corner case where an IRQ is presented just before executing `wfi`, which would cause it to return directly into `wfi` and potentially get stuck in sleep, instead of continuing to background processing. When execution is resumed, interrupts are reenabled and appropriate IRQ Handlers should be executed. Signed-off-by: Marcin Szymczyk --- arch/riscv/core/cpu_idle.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/core/cpu_idle.c b/arch/riscv/core/cpu_idle.c index 0d8e4fedeb2..1d47680cef2 100644 --- a/arch/riscv/core/cpu_idle.c +++ b/arch/riscv/core/cpu_idle.c @@ -10,13 +10,13 @@ void __weak arch_cpu_idle(void) { sys_trace_idle(); - irq_unlock(MSTATUS_IEN); __asm__ volatile("wfi"); + irq_unlock(MSTATUS_IEN); } void __weak arch_cpu_atomic_idle(unsigned int key) { sys_trace_idle(); - irq_unlock(key); __asm__ volatile("wfi"); + irq_unlock(key); } From d248b7bf07bf444278f6e4cef4ef1cede8dad340 Mon Sep 17 00:00:00 2001 From: Marcin Szymczyk Date: Fri, 15 Mar 2024 15:03:57 +0100 Subject: [PATCH 1120/2402] soc: nordic: vpr: add workaround for MSTATUS.MIE not waking VPR up Due to HW issue, VPR needs to keep MSTATUS.MIE enabled during sleep. Otherwise, interrupts will not wake it up. Signed-off-by: Marcin Szymczyk --- soc/nordic/common/vpr/CMakeLists.txt | 2 +- soc/nordic/common/vpr/Kconfig | 1 + soc/nordic/common/vpr/soc_idle.c | 31 ++++++++++++++++++++++++++++ 3 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 soc/nordic/common/vpr/soc_idle.c diff --git a/soc/nordic/common/vpr/CMakeLists.txt b/soc/nordic/common/vpr/CMakeLists.txt index f69b830b465..d418954eebc 100644 --- a/soc/nordic/common/vpr/CMakeLists.txt +++ b/soc/nordic/common/vpr/CMakeLists.txt @@ -3,6 +3,6 @@ zephyr_include_directories(.) -zephyr_library_sources(soc_irq.S soc_irq.c vector.S) +zephyr_library_sources(soc_idle.c soc_irq.S soc_irq.c vector.S) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/nordic/common/vpr/Kconfig b/soc/nordic/common/vpr/Kconfig index baef3432a90..35d203c42dc 100644 --- a/soc/nordic/common/vpr/Kconfig +++ b/soc/nordic/common/vpr/Kconfig @@ -15,5 +15,6 @@ config RISCV_CORE_NORDIC_VPR select RISCV_SOC_HAS_ISR_STACKING select RISCV_SOC_CONTEXT_SAVE select HAS_FLASH_LOAD_OFFSET + select ARCH_CPU_IDLE_CUSTOM help Enable support for the RISC-V Nordic VPR core. diff --git a/soc/nordic/common/vpr/soc_idle.c b/soc/nordic/common/vpr/soc_idle.c new file mode 100644 index 00000000000..f5f77120e1a --- /dev/null +++ b/soc/nordic/common/vpr/soc_idle.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* + * Due to a HW issue, VPR requires MSTATUS.MIE to be enabled when entering sleep. + * Otherwise it would not wake up. + */ +void arch_cpu_idle(void) +{ + sys_trace_idle(); + irq_unlock(MSTATUS_IEN); + __asm__ volatile("wfi"); +} + +void arch_cpu_atomic_idle(unsigned int key) +{ + sys_trace_idle(); + irq_unlock(MSTATUS_IEN); + __asm__ volatile("wfi"); + + /* Disable interrupts if needed. */ + __asm__ volatile ("csrc mstatus, %0" + : + : "r" (~key & MSTATUS_IEN) + : "memory"); +} From a994dc5a35420ab8aeab6f81501e1c06756ab0ec Mon Sep 17 00:00:00 2001 From: Marcin Szymczyk Date: Tue, 19 Mar 2024 10:39:53 +0100 Subject: [PATCH 1121/2402] soc: nordic: vpr: remove enabling `MSTATUS.MIE` in boot time Interrupts should not be enabled this early in boot time. Driver initializations expect IRQs not to arrive when setting up HW. Remove enabling `MSTATUS.MIE` in `__start`. It will be enabled when main thread is switched to, as threads by default start with enabled `MSTATUS.MIE`. Signed-off-by: Marcin Szymczyk --- soc/nordic/common/vpr/vector.S | 4 ---- 1 file changed, 4 deletions(-) diff --git a/soc/nordic/common/vpr/vector.S b/soc/nordic/common/vpr/vector.S index b8c6d97170c..84feb3e56b3 100644 --- a/soc/nordic/common/vpr/vector.S +++ b/soc/nordic/common/vpr/vector.S @@ -20,9 +20,5 @@ SECTION_FUNC(vectors, __start) la t0, _irq_vector_table csrw 0x307, t0 - /* Enable mstatus.mie */ - li t0, 0x1888 - csrw mstatus, t0 - /* Call into Zephyr initialization. */ tail __initialize From 4235efc7bd4e5b420cd960237e24ee7107627d19 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 15:39:54 +0100 Subject: [PATCH 1122/2402] samples|tests several: Support using nrf5340bsim hwmv2 names For all samples which handle the nrf5340bsim in some special way (for example in sysbuild files, or by checking what samples are supported) handle also building with the hwmv2 names. Also, let's fix the cmake info message in these respective samples which tells the user which board target is used for which part of the app. Signed-off-by: Alberto Escolar Piedras --- samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild | 1 + samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild | 1 + samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild | 1 + samples/bluetooth/public_broadcast_source/Kconfig.sysbuild | 1 + samples/bluetooth/unicast_audio_client/Kconfig.sysbuild | 1 + samples/bluetooth/unicast_audio_server/Kconfig.sysbuild | 1 + samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt | 3 ++- samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild | 1 + samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt | 5 +++-- samples/drivers/mbox/CMakeLists.txt | 3 ++- samples/drivers/mbox/Kconfig.sysbuild | 1 + samples/drivers/mbox/remote/CMakeLists.txt | 3 ++- samples/subsys/logging/multidomain/CMakeLists.txt | 3 ++- samples/subsys/logging/multidomain/Kconfig.sysbuild | 1 + .../audio_samples/broadcast_audio_sink/Kconfig.sysbuild | 1 + .../audio_samples/unicast_audio_client/Kconfig.sysbuild | 1 + tests/bsim/bluetooth/ll/bis/Kconfig.sysbuild | 2 ++ tests/bsim/bluetooth/ll/cis/Kconfig.sysbuild | 2 ++ tests/bsim/bluetooth/ll/conn/Kconfig.sysbuild | 2 ++ 19 files changed, 28 insertions(+), 6 deletions(-) diff --git a/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild b/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild index d609fd0ec85..a85b5ab2bb0 100644 --- a/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild +++ b/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild @@ -8,6 +8,7 @@ config NET_CORE_BOARD default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if "$(BOARD)$(BOARD_IDENTIFIER)" = "nrf5340bsim/nrf5340/cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild b/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild index d609fd0ec85..a85b5ab2bb0 100644 --- a/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild +++ b/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild @@ -8,6 +8,7 @@ config NET_CORE_BOARD default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if "$(BOARD)$(BOARD_IDENTIFIER)" = "nrf5340bsim/nrf5340/cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild b/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild index d609fd0ec85..a85b5ab2bb0 100644 --- a/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild +++ b/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild @@ -8,6 +8,7 @@ config NET_CORE_BOARD default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if "$(BOARD)$(BOARD_IDENTIFIER)" = "nrf5340bsim/nrf5340/cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild b/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild index d609fd0ec85..e66e696d984 100644 --- a/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild +++ b/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild @@ -8,6 +8,7 @@ config NET_CORE_BOARD default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if $(BOARD)$(BOARD_IDENTIFIER) = "nrf5340bsim/nrf5340/cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild b/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild index d609fd0ec85..e66e696d984 100644 --- a/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild +++ b/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild @@ -8,6 +8,7 @@ config NET_CORE_BOARD default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if $(BOARD)$(BOARD_IDENTIFIER) = "nrf5340bsim/nrf5340/cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild b/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild index d609fd0ec85..e66e696d984 100644 --- a/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild +++ b/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild @@ -8,6 +8,7 @@ config NET_CORE_BOARD default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if $(BOARD)$(BOARD_IDENTIFIER) = "nrf5340bsim/nrf5340/cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt b/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt index a09354a9e05..179ceeb5467 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt +++ b/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt @@ -8,8 +8,9 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) if(("${BOARD}" STREQUAL "nrf5340dk") OR + ("${BOARD}${BOARD_IDENTIFIER}" STREQUAL "nrf5340bsim/nrf5340/cpuapp") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpuapp")) - message(INFO " ${BOARD} used for Application Core") + message(INFO " ${BOARD}${BOARD_IDENTIFIER} used for Application Core") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild b/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild index e6d2ccd9930..34b23ce2113 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild +++ b/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild @@ -8,3 +8,4 @@ config NET_CORE_BOARD string default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if $(BOARD)$(BOARD_IDENTIFIER) = "nrf5340bsim/nrf5340/cpuapp" diff --git a/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt b/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt index 341d961d8f0..b9335266efd 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt +++ b/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt @@ -8,8 +8,9 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) if(("${BOARD}" STREQUAL "nrf5340dk") OR - ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpunet")) - message(INFO " ${BOARD} used for Network Core") + ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpunet") OR + ("${BOARD}" STREQUAL "nrf5340bsim")) + message(INFO " ${BOARD}${BOARD_IDENTIFIER} used for Network Core") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/drivers/mbox/CMakeLists.txt b/samples/drivers/mbox/CMakeLists.txt index dee828b30ba..da90bcaed32 100644 --- a/samples/drivers/mbox/CMakeLists.txt +++ b/samples/drivers/mbox/CMakeLists.txt @@ -12,6 +12,7 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr) if(("${BOARD}" STREQUAL "nrf5340dk") OR + ("${BOARD}${BOARD_IDENTIFIER}" STREQUAL "nrf5340bsim/nrf5340/cpuapp") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpuapp") OR ("${BOARD}" STREQUAL "adp_xc7k") OR ("${BOARD}" STREQUAL "mimxrt1170_evkb") OR @@ -19,7 +20,7 @@ if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "mimxrt1160_evk") OR ("${BOARD}" STREQUAL "lpcxpresso55s69") OR ("${BOARD}" STREQUAL "nrf54h20dk")) - message(STATUS "${BOARD} compile as Main in this sample") + message(STATUS "${BOARD}${BOARD_IDENTIFIER} compile as Main in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/drivers/mbox/Kconfig.sysbuild b/samples/drivers/mbox/Kconfig.sysbuild index dfc99e4aea1..7efe65b4c8f 100644 --- a/samples/drivers/mbox/Kconfig.sysbuild +++ b/samples/drivers/mbox/Kconfig.sysbuild @@ -9,6 +9,7 @@ config REMOTE_BOARD string default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if $(BOARD)$(BOARD_IDENTIFIER) = "nrf5340bsim/nrf5340/cpuapp" default "adp_xc7k/ae350" if $(BOARD) = "adp_xc7k" default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb" default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" diff --git a/samples/drivers/mbox/remote/CMakeLists.txt b/samples/drivers/mbox/remote/CMakeLists.txt index 9a16f7588c6..33c4ad3cc28 100644 --- a/samples/drivers/mbox/remote/CMakeLists.txt +++ b/samples/drivers/mbox/remote/CMakeLists.txt @@ -10,6 +10,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) if(("${BOARD}" STREQUAL "nrf5340dk") OR + ("${BOARD}" STREQUAL "nrf5340bsim") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpunet") OR ("${BOARD}" STREQUAL "mimxrt1170_evkb") OR ("${BOARD}" STREQUAL "mimxrt1170_evk") OR @@ -17,7 +18,7 @@ if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "lpcxpresso55s69") OR ("${BOARD}" STREQUAL "adp_xc7k") OR ("${BOARD}" STREQUAL "nrf54h20dk")) - message(STATUS "${BOARD} compile as remote in this sample") + message(STATUS "${BOARD}${BOARD_IDENTIFIER} compile as remote in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/subsys/logging/multidomain/CMakeLists.txt b/samples/subsys/logging/multidomain/CMakeLists.txt index d800a86fac2..d2893ffa1dc 100644 --- a/samples/subsys/logging/multidomain/CMakeLists.txt +++ b/samples/subsys/logging/multidomain/CMakeLists.txt @@ -9,8 +9,9 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) if(NOT(("${BOARD}" STREQUAL "nrf5340dk") + OR ("${BOARD}${BOARD_IDENTIFIER}" STREQUAL "nrf5340bsim/nrf5340/cpuapp") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpuapp"))) - message(FATAL_ERROR "${BOARD} is not supported for this sample") + message(FATAL_ERROR "${BOARD}${BOARD_IDENTIFIER} is not supported for this sample") endif() project(log_multidomain) diff --git a/samples/subsys/logging/multidomain/Kconfig.sysbuild b/samples/subsys/logging/multidomain/Kconfig.sysbuild index e6d2ccd9930..34b23ce2113 100644 --- a/samples/subsys/logging/multidomain/Kconfig.sysbuild +++ b/samples/subsys/logging/multidomain/Kconfig.sysbuild @@ -8,3 +8,4 @@ config NET_CORE_BOARD string default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if $(BOARD)$(BOARD_IDENTIFIER) = "nrf5340bsim/nrf5340/cpuapp" diff --git a/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/Kconfig.sysbuild b/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/Kconfig.sysbuild index 6ef6bede28d..c661fef422e 100644 --- a/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/Kconfig.sysbuild +++ b/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/Kconfig.sysbuild @@ -8,3 +8,4 @@ config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX # Let's pass the test arguments to the application MCU test # otherwise by default they would have gone to the net core. default 0 if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default 0 if $(BOARD) = "nrf5340bsim" diff --git a/tests/bsim/bluetooth/audio_samples/unicast_audio_client/Kconfig.sysbuild b/tests/bsim/bluetooth/audio_samples/unicast_audio_client/Kconfig.sysbuild index 4e7f66926c2..e29e9bb5642 100644 --- a/tests/bsim/bluetooth/audio_samples/unicast_audio_client/Kconfig.sysbuild +++ b/tests/bsim/bluetooth/audio_samples/unicast_audio_client/Kconfig.sysbuild @@ -8,3 +8,4 @@ config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX # Let's pass the test arguments to the application MCU test # otherwise by default they would have gone to the net core. default 0 if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default 0 if $(BOARD) = "nrf5340bsim" diff --git a/tests/bsim/bluetooth/ll/bis/Kconfig.sysbuild b/tests/bsim/bluetooth/ll/bis/Kconfig.sysbuild index 6c89fddc9f3..2ccde2c76ae 100644 --- a/tests/bsim/bluetooth/ll/bis/Kconfig.sysbuild +++ b/tests/bsim/bluetooth/ll/bis/Kconfig.sysbuild @@ -6,9 +6,11 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if $(BOARD)$(BOARD_IDENTIFIER) = "nrf5340bsim/nrf5340/cpuapp" config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX int # Let's pass the test arguments to the application MCU test # otherwise by default they would have gone to the net core. default 0 if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default 0 if $(BOARD) = "nrf5340bsim" diff --git a/tests/bsim/bluetooth/ll/cis/Kconfig.sysbuild b/tests/bsim/bluetooth/ll/cis/Kconfig.sysbuild index 6c89fddc9f3..2ccde2c76ae 100644 --- a/tests/bsim/bluetooth/ll/cis/Kconfig.sysbuild +++ b/tests/bsim/bluetooth/ll/cis/Kconfig.sysbuild @@ -6,9 +6,11 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if $(BOARD)$(BOARD_IDENTIFIER) = "nrf5340bsim/nrf5340/cpuapp" config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX int # Let's pass the test arguments to the application MCU test # otherwise by default they would have gone to the net core. default 0 if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default 0 if $(BOARD) = "nrf5340bsim" diff --git a/tests/bsim/bluetooth/ll/conn/Kconfig.sysbuild b/tests/bsim/bluetooth/ll/conn/Kconfig.sysbuild index 6c89fddc9f3..2ccde2c76ae 100644 --- a/tests/bsim/bluetooth/ll/conn/Kconfig.sysbuild +++ b/tests/bsim/bluetooth/ll/conn/Kconfig.sysbuild @@ -6,9 +6,11 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340bsim/nrf5340/cpunet" if $(BOARD)$(BOARD_IDENTIFIER) = "nrf5340bsim/nrf5340/cpuapp" config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX int # Let's pass the test arguments to the application MCU test # otherwise by default they would have gone to the net core. default 0 if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default 0 if $(BOARD) = "nrf5340bsim" From 816acb9f0f9b24b3683e67076fc7bac373f9afec Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 19 Mar 2024 10:45:48 +0100 Subject: [PATCH 1123/2402] samples: docs: Correct nrf5340bsim hwmv1 naming to hwmv2 Replace the uses of the hwmv1 names in the samples documentation with the corresponding hwmv2 ones. Signed-off-by: Alberto Escolar Piedras --- samples/bluetooth/broadcast_audio_sink/README.rst | 2 +- samples/bluetooth/broadcast_audio_source/README.rst | 2 +- samples/bluetooth/public_broadcast_sink/README.rst | 2 +- samples/bluetooth/public_broadcast_source/README.rst | 2 +- samples/bluetooth/unicast_audio_client/README.rst | 2 +- samples/boards/nrf/nrf53_sync_rtc/README.rst | 2 +- samples/drivers/mbox/README.rst | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/samples/bluetooth/broadcast_audio_sink/README.rst b/samples/bluetooth/broadcast_audio_sink/README.rst index 3c2d8d39d17..5c837c1652c 100644 --- a/samples/bluetooth/broadcast_audio_sink/README.rst +++ b/samples/bluetooth/broadcast_audio_sink/README.rst @@ -63,7 +63,7 @@ Similarly to how you would for real HW, you can do: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_sink/ - :board: nrf5340bsim_nrf5340_cpuapp + :board: nrf5340bsim/nrf5340/cpuapp :goals: build :west-args: --sysbuild diff --git a/samples/bluetooth/broadcast_audio_source/README.rst b/samples/bluetooth/broadcast_audio_source/README.rst index 515eb64177e..67b576d4046 100644 --- a/samples/bluetooth/broadcast_audio_source/README.rst +++ b/samples/bluetooth/broadcast_audio_source/README.rst @@ -62,7 +62,7 @@ Similarly to how you would for real HW, you can do: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_source/ - :board: nrf5340bsim_nrf5340_cpuapp + :board: nrf5340bsim/nrf5340/cpuapp :goals: build :west-args: --sysbuild diff --git a/samples/bluetooth/public_broadcast_sink/README.rst b/samples/bluetooth/public_broadcast_sink/README.rst index 2ec0e41e7e5..6be21803d94 100644 --- a/samples/bluetooth/public_broadcast_sink/README.rst +++ b/samples/bluetooth/public_broadcast_sink/README.rst @@ -60,7 +60,7 @@ Similarly to how you would for real HW, you can do: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/public_broadcast_sink/ - :board: nrf5340bsim_nrf5340_cpuapp + :board: nrf5340bsim/nrf5340/cpuapp :goals: build :west-args: --sysbuild diff --git a/samples/bluetooth/public_broadcast_source/README.rst b/samples/bluetooth/public_broadcast_source/README.rst index d0d1cf44afa..7d7a5852198 100644 --- a/samples/bluetooth/public_broadcast_source/README.rst +++ b/samples/bluetooth/public_broadcast_source/README.rst @@ -60,7 +60,7 @@ Similarly to how you would for real HW, you can do: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/public_broadcast_source/ - :board: nrf5340bsim_nrf5340_cpuapp + :board: nrf5340bsim/nrf5340/cpuapp :goals: build :west-args: --sysbuild diff --git a/samples/bluetooth/unicast_audio_client/README.rst b/samples/bluetooth/unicast_audio_client/README.rst index 19e7cdf8679..67087dfdfcc 100644 --- a/samples/bluetooth/unicast_audio_client/README.rst +++ b/samples/bluetooth/unicast_audio_client/README.rst @@ -78,6 +78,6 @@ Building for a simulated nrf5340bsim .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_client/ - :board: nrf5340bsim_nrf5340_cpuapp + :board: nrf5340bsim/nrf5340/cpuapp :goals: build :west-args: --sysbuild diff --git a/samples/boards/nrf/nrf53_sync_rtc/README.rst b/samples/boards/nrf/nrf53_sync_rtc/README.rst index 7d2a2945ffc..0f5cfb574f7 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/README.rst +++ b/samples/boards/nrf/nrf53_sync_rtc/README.rst @@ -84,7 +84,7 @@ Building the application for the simulated nrf5340bsim .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/nrf53_sync_rtc :host-os: unix - :board: nrf5340bsim_nrf5340_cpuapp + :board: nrf5340bsim/nrf5340/cpuapp :goals: build :west-args: --sysbuild diff --git a/samples/drivers/mbox/README.rst b/samples/drivers/mbox/README.rst index e4ab895ade4..9adcd697c3e 100644 --- a/samples/drivers/mbox/README.rst +++ b/samples/drivers/mbox/README.rst @@ -67,7 +67,7 @@ Building the application for the simulated nrf5340bsim .. zephyr-app-commands:: :zephyr-app: samples/drivers/mbox/ :host-os: unix - :board: nrf5340bsim_nrf5340_cpuapp + :board: nrf5340bsim/nrf5340/cpuapp :goals: build :west-args: --sysbuild From adbe6dea3752c421ec95f83e95a72e1f6d0f8ccc Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 15:13:36 +0100 Subject: [PATCH 1124/2402] nrf53_bsim: Remove hwmv1 twister definition Remove the hwmv1 twister board definitions for the nrf5340_bsim targets in preparation to transition to the new definitions for hwmv2 Signed-off-by: Alberto Escolar Piedras --- .../nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml | 15 --------------- .../nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml | 15 --------------- 2 files changed, 30 deletions(-) delete mode 100644 boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml delete mode 100644 boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml deleted file mode 100644 index 448d4f330c3..00000000000 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nrf5340bsim_nrf5340_cpuapp -name: NRF53 BabbleSim - Application Core target -type: native -arch: posix -simulation: native -env: - - BSIM_OUT_PATH -toolchain: - - zephyr -testing: - ignore_tags: - - gpio - - modem - - uart - - bsim_skip_CI diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml deleted file mode 100644 index 4cd71ff3566..00000000000 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nrf5340bsim_nrf5340_cpunet -name: NRF53 Net Core BabbleSim board -type: native -arch: posix -simulation: native -env: - - BSIM_OUT_PATH -toolchain: - - zephyr -testing: - ignore_tags: - - gpio - - modem - - uart - - bsim_skip_CI From 1f4f307bd20e9340262afa580b14a846d0b8e3b6 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 15:16:39 +0100 Subject: [PATCH 1125/2402] samples|tests/* yamls: Replace all nrf5340bsim hwmv1 names w hwmv2 version Replace all instances of nrf5340bsim_nrf5340_cpunet & nrf5340bsim_nrf5340_cpuapp with nrf5340bsim/nrf5340/cpunet & nrf5340bsim/nrf5340/cpuapp In these samples/tests twister yamls definitions. Signed-off-by: Alberto Escolar Piedras --- .../bluetooth/broadcast_audio_sink/sample.yaml | 2 +- .../bluetooth/broadcast_audio_source/sample.yaml | 2 +- samples/bluetooth/hci_ipc/sample.yaml | 16 ++++++++-------- .../bluetooth/public_broadcast_sink/sample.yaml | 2 +- .../public_broadcast_source/sample.yaml | 2 +- .../bluetooth/unicast_audio_client/sample.yaml | 2 +- .../bluetooth/unicast_audio_server/sample.yaml | 2 +- .../nrf/ieee802154/802154_rpmsg/sample.yaml | 2 +- samples/boards/nrf/nrf53_sync_rtc/sample.yaml | 2 +- samples/drivers/mbox/sample.yaml | 2 +- samples/subsys/logging/multidomain/sample.yaml | 4 ++-- tests/bsim/bluetooth/ll/bis/testcase.yaml | 16 ++++++++-------- tests/drivers/entropy/api/testcase.yaml | 2 +- tests/drivers/timer/nrf_rtc_timer/testcase.yaml | 4 ++-- 14 files changed, 30 insertions(+), 30 deletions(-) diff --git a/samples/bluetooth/broadcast_audio_sink/sample.yaml b/samples/bluetooth/broadcast_audio_sink/sample.yaml index 51b1d04b0ed..d44b5585f79 100644 --- a/samples/bluetooth/broadcast_audio_sink/sample.yaml +++ b/samples/bluetooth/broadcast_audio_sink/sample.yaml @@ -8,7 +8,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf5340dk/nrf5340/cpuapp - - nrf5340bsim_nrf5340_cpuapp + - nrf5340bsim/nrf5340/cpuapp integration_platforms: - qemu_x86 - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/broadcast_audio_source/sample.yaml b/samples/bluetooth/broadcast_audio_source/sample.yaml index 4df6ed34f54..047323dd3c7 100644 --- a/samples/bluetooth/broadcast_audio_source/sample.yaml +++ b/samples/bluetooth/broadcast_audio_source/sample.yaml @@ -8,7 +8,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf5340dk/nrf5340/cpuapp - - nrf5340bsim_nrf5340_cpuapp + - nrf5340bsim/nrf5340/cpuapp integration_platforms: - qemu_x86 - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/hci_ipc/sample.yaml b/samples/bluetooth/hci_ipc/sample.yaml index e0612025e6d..e88726aa45f 100644 --- a/samples/bluetooth/hci_ipc/sample.yaml +++ b/samples/bluetooth/hci_ipc/sample.yaml @@ -8,7 +8,7 @@ tests: platform_allow: - nrf5340dk/nrf5340/cpunet - nrf5340_audio_dk/nrf5340/cpunet - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf5340dk/nrf5340/cpunet - nrf5340_audio_dk/nrf5340/cpunet @@ -19,7 +19,7 @@ tests: platform_allow: - nrf5340dk/nrf5340/cpunet - nrf5340_audio_dk/nrf5340/cpunet - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf5340dk/nrf5340/cpunet - nrf5340_audio_dk/nrf5340/cpunet @@ -30,7 +30,7 @@ tests: platform_allow: - nrf5340dk/nrf5340/cpunet - nrf5340_audio_dk/nrf5340/cpunet - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.bis.bt_ll_sw_split: @@ -40,7 +40,7 @@ tests: platform_allow: - nrf5340dk/nrf5340/cpunet - nrf5340_audio_dk/nrf5340/cpunet - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso_central.bt_ll_sw_split: @@ -50,7 +50,7 @@ tests: platform_allow: - nrf5340dk/nrf5340/cpunet - nrf5340_audio_dk/nrf5340/cpunet - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso_peripheral.bt_ll_sw_split: @@ -60,7 +60,7 @@ tests: platform_allow: - nrf5340dk/nrf5340/cpunet - nrf5340_audio_dk/nrf5340/cpunet - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.cis.bt_ll_sw_split: @@ -70,7 +70,7 @@ tests: platform_allow: - nrf5340dk/nrf5340/cpunet - nrf5340_audio_dk/nrf5340/cpunet - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso.bt_ll_sw_split: @@ -79,7 +79,7 @@ tests: extra_args: CONF_FILE="nrf5340_cpunet_iso-bt_ll_sw_split.conf" platform_allow: - nrf5340dk/nrf5340/cpunet - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.df.bt_ll_sw_split: diff --git a/samples/bluetooth/public_broadcast_sink/sample.yaml b/samples/bluetooth/public_broadcast_sink/sample.yaml index 3f2302aa4b1..cf437a73703 100644 --- a/samples/bluetooth/public_broadcast_sink/sample.yaml +++ b/samples/bluetooth/public_broadcast_sink/sample.yaml @@ -8,7 +8,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf5340dk/nrf5340/cpuapp - - nrf5340bsim_nrf5340_cpuapp + - nrf5340bsim/nrf5340/cpuapp integration_platforms: - qemu_x86 - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/public_broadcast_source/sample.yaml b/samples/bluetooth/public_broadcast_source/sample.yaml index f4f1fc435f7..d40c0485557 100644 --- a/samples/bluetooth/public_broadcast_source/sample.yaml +++ b/samples/bluetooth/public_broadcast_source/sample.yaml @@ -8,7 +8,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf5340dk/nrf5340/cpuapp - - nrf5340bsim_nrf5340_cpuapp + - nrf5340bsim/nrf5340/cpuapp integration_platforms: - qemu_x86 - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/unicast_audio_client/sample.yaml b/samples/bluetooth/unicast_audio_client/sample.yaml index 1b488d9eb94..536ab9144f0 100644 --- a/samples/bluetooth/unicast_audio_client/sample.yaml +++ b/samples/bluetooth/unicast_audio_client/sample.yaml @@ -7,7 +7,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf5340bsim_nrf5340_cpuapp + - nrf5340bsim/nrf5340/cpuapp - nrf5340dk/nrf5340/cpuapp - native_sim tags: bluetooth diff --git a/samples/bluetooth/unicast_audio_server/sample.yaml b/samples/bluetooth/unicast_audio_server/sample.yaml index 0ff20f735d7..fc14175a2d1 100644 --- a/samples/bluetooth/unicast_audio_server/sample.yaml +++ b/samples/bluetooth/unicast_audio_server/sample.yaml @@ -7,7 +7,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf5340bsim_nrf5340_cpuapp + - nrf5340bsim/nrf5340/cpuapp - nrf5340dk/nrf5340/cpuapp - native_sim tags: bluetooth diff --git a/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml b/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml index f1a7fae2a9a..bf4b9fe220a 100644 --- a/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml +++ b/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml @@ -7,4 +7,4 @@ tests: build_only: true platform_allow: - nrf5340dk/nrf5340/cpunet - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet diff --git a/samples/boards/nrf/nrf53_sync_rtc/sample.yaml b/samples/boards/nrf/nrf53_sync_rtc/sample.yaml index 95e0471073f..586cab7def4 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/sample.yaml +++ b/samples/boards/nrf/nrf53_sync_rtc/sample.yaml @@ -13,7 +13,7 @@ tests: harness: remote sample.boards.nrf.nrf53_sync_rtc.simu: platform_allow: - - nrf5340bsim_nrf5340_cpuapp + - nrf5340bsim/nrf5340/cpuapp harness: console harness_config: type: multi_line diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml index be5ba74edf7..2b401812ae5 100644 --- a/samples/drivers/mbox/sample.yaml +++ b/samples/drivers/mbox/sample.yaml @@ -64,7 +64,7 @@ tests: sample.drivers.mbox.simu: platform_allow: - - nrf5340bsim_nrf5340_cpuapp + - nrf5340bsim/nrf5340/cpuapp harness: console harness_config: type: multi_line diff --git a/samples/subsys/logging/multidomain/sample.yaml b/samples/subsys/logging/multidomain/sample.yaml index 9d0075017fa..5fba4c37853 100644 --- a/samples/subsys/logging/multidomain/sample.yaml +++ b/samples/subsys/logging/multidomain/sample.yaml @@ -12,9 +12,9 @@ tests: build_only: true sample.logging.multidomain.ipc_static_vrings.simu: platform_allow: - - nrf5340bsim_nrf5340_cpuapp + - nrf5340bsim/nrf5340/cpuapp integration_platforms: - - nrf5340bsim_nrf5340_cpuapp + - nrf5340bsim/nrf5340/cpuapp harness: console harness_config: type: multi_line diff --git a/tests/bsim/bluetooth/ll/bis/testcase.yaml b/tests/bsim/bluetooth/ll/bis/testcase.yaml index ee619560a79..c13d68f3fb7 100644 --- a/tests/bsim/bluetooth/ll/bis/testcase.yaml +++ b/tests/bsim/bluetooth/ll/bis/testcase.yaml @@ -9,12 +9,12 @@ tests: sysbuild: true platform_allow: - nrf52_bsim - - nrf5340bsim_nrf5340_cpuapp - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpuapp + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf52_bsim - - nrf5340bsim_nrf5340_cpuapp - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpuapp + - nrf5340bsim/nrf5340/cpunet harness: bsim harness_config: bsim_exe_name: tests_bsim_bluetooth_ll_bis_prj_conf @@ -22,10 +22,10 @@ tests: extra_args: OVERLAY_CONFIG=overlay-ticker_expire_info.conf platform_allow: - nrf52_bsim - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf52_bsim - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet harness: bsim harness_config: bsim_exe_name: tests_bsim_bluetooth_ll_bis_prj_conf_overlay-ticker_expire_info_conf @@ -33,10 +33,10 @@ tests: extra_args: CONF_FILE=prj_vs_dp.conf platform_allow: - nrf52_bsim - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf52_bsim - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet harness: bsim harness_config: bsim_exe_name: tests_bsim_bluetooth_ll_bis_prj_vs_dp_conf diff --git a/tests/drivers/entropy/api/testcase.yaml b/tests/drivers/entropy/api/testcase.yaml index dfab54db635..f875cadab42 100644 --- a/tests/drivers/entropy/api/testcase.yaml +++ b/tests/drivers/entropy/api/testcase.yaml @@ -7,7 +7,7 @@ tests: drivers.entropy.bt_hci: platform_allow: - nrf52_bsim - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpunet extra_args: - DTC_OVERLAY_FILE=./entropy_bt_hci.overlay - OVERLAY_CONFIG=./entropy_bt_hci.conf diff --git a/tests/drivers/timer/nrf_rtc_timer/testcase.yaml b/tests/drivers/timer/nrf_rtc_timer/testcase.yaml index d946e37062d..b2df4296a4b 100644 --- a/tests/drivers/timer/nrf_rtc_timer/testcase.yaml +++ b/tests/drivers/timer/nrf_rtc_timer/testcase.yaml @@ -19,7 +19,7 @@ tests: - nrf52dk/nrf52832 - nrf52840dk/nrf52840 - nrf52_bsim - - nrf5340bsim_nrf5340_cpuapp - - nrf5340bsim_nrf5340_cpunet + - nrf5340bsim/nrf5340/cpuapp + - nrf5340bsim/nrf5340/cpunet integration_platforms: - nrf52dk/nrf52832 From 18ddfdddecab1ef71812fefd9cbdffadff7559ac Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 18 Mar 2024 15:46:23 +0100 Subject: [PATCH 1126/2402] nrf53_bsim: Add twister definition with hwmv2 names Which replace the old hwmv1 ones. Signed-off-by: Alberto Escolar Piedras --- .../nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml | 15 +++++++++++++++ .../nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml | 15 +++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml create mode 100644 boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000..055bc9e578f --- /dev/null +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml @@ -0,0 +1,15 @@ +identifier: nrf5340bsim/nrf5340/cpuapp +name: NRF53 BabbleSim - Application Core target +type: native +arch: posix +simulation: native +env: + - BSIM_OUT_PATH +toolchain: + - zephyr +testing: + ignore_tags: + - gpio + - modem + - uart + - bsim_skip_CI diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml new file mode 100644 index 00000000000..f88fb9c6ca8 --- /dev/null +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml @@ -0,0 +1,15 @@ +identifier: nrf5340bsim/nrf5340/cpunet +name: NRF53 Net Core BabbleSim board +type: native +arch: posix +simulation: native +env: + - BSIM_OUT_PATH +toolchain: + - zephyr +testing: + ignore_tags: + - gpio + - modem + - uart + - bsim_skip_CI From 685429c2d1c18acf117b606b3d5c8ea021a0da75 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 19 Mar 2024 14:34:57 +0100 Subject: [PATCH 1127/2402] boards nrf53_bsim docs: Replace nrf5340bsim hwmv1 naming with hwmv2 Replace the uses of the hwmv1 names in the board documentation with the corresponding hwmv2 ones. Signed-off-by: Alberto Escolar Piedras --- boards/native/nrf_bsim/doc/nrf5340bsim.rst | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/boards/native/nrf_bsim/doc/nrf5340bsim.rst b/boards/native/nrf_bsim/doc/nrf5340bsim.rst index f2ece408e08..2d6190e7c46 100644 --- a/boards/native/nrf_bsim/doc/nrf5340bsim.rst +++ b/boards/native/nrf_bsim/doc/nrf5340bsim.rst @@ -13,7 +13,7 @@ Overview ******** To allow simulating nrf5340 SOCs two Zephyr target boards are provided: the -``nrf5340bsim_nrf5340_cpuapp`` and ``nrf5340bsim_nrf5340_cpunet``. +``nrf5340bsim/nrf5340/cpuapp`` and ``nrf5340bsim/nrf5340/cpunet``. These use `BabbleSim`_ to simulate the radio activity, and the :ref:`POSIX architecture` and the `native simulator`_ to @@ -22,8 +22,8 @@ providing native code execution performance and easy debugging using native tools, but inherits :ref:`its limitations `. Just like for the nrf5340dk targets, -the nrf5340bsim_nrf5340_cpuapp build target provides support for the application core, -and the nrf5340bsim_nrf5340_cpunet build target provides support for the network +the nrf5340bsim/nrf5340/cpuapp build target provides support for the application core, +and the nrf5340bsim/nrf5340/cpunet build target provides support for the network core on the simulated nRF5340 SOC. These boards include models of some of the nRF5340 SOC peripherals: @@ -65,7 +65,7 @@ Building for, and using these boards ************************************ If you are interested in developing on only one of the MCUs in this SOC, you -can use the corresponding simulated target, nrf5340bsim_nrf5340_cpuapp or nrf5340bsim_nrf5340_cpunet +can use the corresponding simulated target, nrf5340bsim/nrf5340/cpuapp or nrf5340bsim/nrf5340/cpunet following the instructions from the :ref:`nrf52_bsim board `. Simply change the board/target appropriately when building. @@ -83,8 +83,8 @@ Simply change the board/target appropriately when building. Assembling both MCUs images into a single executable **************************************************** -By default, when you build targeting either nrf5340bsim_nrf5340_cpuapp or -nrf5340bsim_nrf5340_cpunet you will end up with a library (``zephyr/zephyr.elf``) that corresponds +By default, when you build targeting either nrf5340bsim/nrf5340/cpuapp or +nrf5340bsim/nrf5340/cpunet you will end up with a library (``zephyr/zephyr.elf``) that corresponds to that MCU code image, and an executable (``zephyr/zephyr.exe``) that includes the native simulator runner, SOC HW models, that image, and an empty image for the other MCU. @@ -112,7 +112,7 @@ ARM's TrustZone is not modelled in these boards. This means that: * There is no differentiation between secure and non secure execution states or bus accesses. * All RAM, flash and peripherals are in principle accessible from all SW. Peripherals with their own interconnect master ports can, in principle, access any other peripheral or RAM area. -* There is no nrf5340bsim_nrf5340_cpuapp_ns board/build target, or posibility of mixing secure +* There is no nrf5340bsim/nrf5340/cpuapp/ns board/build target, or posibility of mixing secure and non-secure images. * Currently there is no model of the SPU, and therefore neither flash, RAM areas or peripherals can be labelled as restricted for secure or non secure access. From e0a23663f6fa0677f66b4e058fe7200eba6e575f Mon Sep 17 00:00:00 2001 From: Piotr Pryga Date: Wed, 13 Mar 2024 11:23:21 +0100 Subject: [PATCH 1128/2402] dts: nrf54h20: move GRTC channels allocation to the SOC dtsi The GRTC channels and irqs configuration for Radio domain is SOC specific not board specific. Move the configuration to SOC dtsi file. Signed-off-by: Piotr Pryga --- boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts | 3 --- dts/arm/nordic/nrf54h20_cpurad.dtsi | 6 +++++- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index fd65d2d495a..3efa07f6349 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -60,9 +60,6 @@ &grtc { status = "okay"; - child-owned-channels = <8 9 10 11 12>; - nonsecure-channels = <8 9 10 11 12>; - owned-channels = <7 8 9 10 11 12 13 14>; }; &uart135 { diff --git a/dts/arm/nordic/nrf54h20_cpurad.dtsi b/dts/arm/nordic/nrf54h20_cpurad.dtsi index 7b7f236de0c..f30c777dbe2 100644 --- a/dts/arm/nordic/nrf54h20_cpurad.dtsi +++ b/dts/arm/nordic/nrf54h20_cpurad.dtsi @@ -47,6 +47,10 @@ cpuppr_vevif: &cpuppr_vevif_remote {}; }; &grtc { + owned-channels = <7 8 9 10 11 12 13 14>; + child-owned-channels = <8 9 10 11 12>; + nonsecure-channels = <8 9 10 11 12>; interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>, - <108 NRF_DEFAULT_IRQ_PRIORITY>; + <109 NRF_DEFAULT_IRQ_PRIORITY>, + <110 NRF_DEFAULT_IRQ_PRIORITY>; }; From 3140b9585beea994a8d1b919e78541ebe8749889 Mon Sep 17 00:00:00 2001 From: Piotr Pryga Date: Wed, 13 Mar 2024 11:25:15 +0100 Subject: [PATCH 1129/2402] dts: nrf54h20: Add missing global dppic and ipcst configs There were missing global dppic and ipct channels configuration that allows to deliver events from global peripherlas like GRTC to Radio domain. Add missing configuration to nrf54h20 dtsi file. Signed-off-by: Piotr Pryga --- dts/arm/nordic/nrf54h20_cpurad.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/dts/arm/nordic/nrf54h20_cpurad.dtsi b/dts/arm/nordic/nrf54h20_cpurad.dtsi index f30c777dbe2..4bdaf76e348 100644 --- a/dts/arm/nordic/nrf54h20_cpurad.dtsi +++ b/dts/arm/nordic/nrf54h20_cpurad.dtsi @@ -54,3 +54,23 @@ cpuppr_vevif: &cpuppr_vevif_remote {}; <109 NRF_DEFAULT_IRQ_PRIORITY>, <110 NRF_DEFAULT_IRQ_PRIORITY>; }; + +&dppic130 { + owned-channels = <0>; + sink-channels = <0>; + nonsecure-channels = <0>; + status = "okay"; +}; + +&dppic132 { + owned-channels = <0>; + source-channels = <0>; + nonsecure-channels = <0>; + status = "okay"; +}; + +&ipct130 { + owned-channels = <0>; + source-channel-links = <0 3 0>; + status = "okay"; +}; From 0dcf3c197e69a44791954285c740171e88e50b0b Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Tue, 12 Mar 2024 16:12:07 +0100 Subject: [PATCH 1130/2402] Bluetooth: Audio: Increase PA sync timeouts Increase the timeouts to be 60 instead of 6. The reason for this is that some controllers (like the Zephyr controller) will reserve some of these to ensure stability, and in fact with skip = 5 and retry = 6, it would still send the PA reports at every interval. To accomodate a higher timeout value, the functions used to convert PA intervals to PA timeouts have been updated. Signed-off-by: Emil Gydesen --- samples/bluetooth/broadcast_audio_sink/src/main.c | 13 ++++++------- samples/bluetooth/public_broadcast_sink/src/main.c | 11 ++++------- .../bluetooth/tmap_bmr/src/bap_broadcast_sink.c | 14 +++++--------- subsys/bluetooth/audio/bap_broadcast_sink.c | 14 +++++--------- subsys/bluetooth/audio/shell/bap.c | 11 ++++------- subsys/bluetooth/audio/shell/bap_scan_delegator.c | 13 ++++++------- tests/bluetooth/tester/src/btp_bap_broadcast.c | 2 +- .../bluetooth/audio/src/bap_broadcast_sink_test.c | 10 +++++----- .../bluetooth/audio/src/bap_scan_delegator_test.c | 13 ++++++------- tests/bsim/bluetooth/audio/src/cap_acceptor_test.c | 10 +++++----- tests/bsim/bluetooth/audio/src/common.h | 2 +- .../audio/src/pbp_public_broadcast_sink_test.c | 14 ++++---------- .../audio/test_scripts/bap_broadcast_audio.sh | 2 +- .../test_scripts/bap_broadcast_audio_assistant.sh | 2 +- tests/bsim/bluetooth/audio/test_scripts/pbp.sh | 2 +- 15 files changed, 55 insertions(+), 78 deletions(-) diff --git a/samples/bluetooth/broadcast_audio_sink/src/main.c b/samples/bluetooth/broadcast_audio_sink/src/main.c index c5e89bd9993..d34a373a4b5 100644 --- a/samples/bluetooth/broadcast_audio_sink/src/main.c +++ b/samples/bluetooth/broadcast_audio_sink/src/main.c @@ -38,7 +38,7 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_SCAN_SELF) || IS_ENABLED(CONFIG_SCAN_OFFLOAD), #endif /* CONFIG_SCAN_SELF */ #define INVALID_BROADCAST_ID (BT_AUDIO_BROADCAST_ID_MAX + 1) -#define SYNC_RETRY_COUNT 6 /* similar to retries for connections */ +#define PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO 20 /* Set the timeout relative to interval */ #define PA_SYNC_SKIP 5 #define NAME_LEN sizeof(CONFIG_TARGET_BROADCAST_NAME) + 1 #define BROADCAST_DATA_ELEMENT_SIZE sizeof(int16_t) @@ -870,16 +870,15 @@ static uint16_t interval_to_sync_timeout(uint16_t pa_interval) /* Use maximum value to maximize chance of success */ pa_timeout = BT_GAP_PER_ADV_MAX_TIMEOUT; } else { - /* Ensure that the following calculation does not overflow silently */ - __ASSERT(SYNC_RETRY_COUNT < 10, - "SYNC_RETRY_COUNT shall be less than 10"); + uint32_t interval_ms; + uint32_t timeout; /* Add retries and convert to unit in 10's of ms */ - pa_timeout = ((uint32_t)pa_interval * SYNC_RETRY_COUNT) / 10; + interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(pa_interval); + timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10; /* Enforce restraints */ - pa_timeout = CLAMP(pa_timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, - BT_GAP_PER_ADV_MAX_TIMEOUT); + pa_timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT); } return pa_timeout; diff --git a/samples/bluetooth/public_broadcast_sink/src/main.c b/samples/bluetooth/public_broadcast_sink/src/main.c index 686ee087a73..d3a6087d0a8 100644 --- a/samples/bluetooth/public_broadcast_sink/src/main.c +++ b/samples/bluetooth/public_broadcast_sink/src/main.c @@ -25,7 +25,7 @@ #define SEM_TIMEOUT K_SECONDS(10) #define PA_SYNC_SKIP 5 -#define SYNC_RETRY_COUNT 6 /* similar to retries for connections */ +#define PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO 20 /* Set the timeout relative to interval */ #define INVALID_BROADCAST_ID 0xFFFFFFFF static bool pbs_found; @@ -114,19 +114,16 @@ static struct bt_pacs_cap cap = { static uint16_t interval_to_sync_timeout(uint16_t interval) { uint32_t interval_ms; - uint16_t timeout; - - /* Ensure that the following calculation does not overflow silently */ - __ASSERT(SYNC_RETRY_COUNT < 10, "SYNC_RETRY_COUNT shall be less than 10"); + uint32_t timeout; /* Add retries and convert to unit in 10's of ms */ interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(interval); - timeout = (interval_ms * SYNC_RETRY_COUNT) / 10; + timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10; /* Enforce restraints */ timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT); - return timeout; + return (uint16_t)timeout; } static void sync_broadcast_pa(const struct bt_le_scan_recv_info *info, diff --git a/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c b/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c index fe82040d45a..fd9c0fab7b0 100644 --- a/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c +++ b/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c @@ -15,7 +15,7 @@ #define SEM_TIMEOUT K_SECONDS(10) #define PA_SYNC_SKIP 5 -#define SYNC_RETRY_COUNT 6 /* similar to retries for connections */ +#define PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO 20 /* Set the timeout relative to interval */ #define INVALID_BROADCAST_ID 0xFFFFFFFF static bool tmap_bms_found; @@ -102,20 +102,16 @@ static struct bt_pacs_cap cap = { static uint16_t interval_to_sync_timeout(uint16_t interval) { uint32_t interval_ms; - uint16_t timeout; - - /* Ensure that the following calculation does not overflow silently */ - __ASSERT(SYNC_RETRY_COUNT < 10, "SYNC_RETRY_COUNT shall be less than 10"); + uint32_t timeout; /* Add retries and convert to unit in 10's of ms */ interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(interval); - timeout = (interval_ms * SYNC_RETRY_COUNT) / 10; + timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10; /* Enforce restraints */ - timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, - BT_GAP_PER_ADV_MAX_TIMEOUT); + timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT); - return timeout; + return (uint16_t)timeout; } static void sync_broadcast_pa(const struct bt_le_scan_recv_info *info, diff --git a/subsys/bluetooth/audio/bap_broadcast_sink.c b/subsys/bluetooth/audio/bap_broadcast_sink.c index cdcd7fb477b..97a1206b13a 100644 --- a/subsys/bluetooth/audio/bap_broadcast_sink.c +++ b/subsys/bluetooth/audio/bap_broadcast_sink.c @@ -32,7 +32,7 @@ LOG_MODULE_REGISTER(bt_bap_broadcast_sink, CONFIG_BT_BAP_BROADCAST_SINK_LOG_LEVE #include "common/bt_str.h" -#define SYNC_RETRY_COUNT 6 /* similar to retries for connections */ +#define PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO 20 /* Set the timeout relative to interval */ #define BROADCAST_SYNC_MIN_INDEX (BIT(1)) /* any value above 0xFFFFFF is invalid, so we can just use 0xFFFFFFFF to denote @@ -908,20 +908,16 @@ static void biginfo_recv(struct bt_le_per_adv_sync *sync, static uint16_t interval_to_sync_timeout(uint16_t interval) { uint32_t interval_ms; - uint16_t timeout; - - /* Ensure that the following calculation does not overflow silently */ - __ASSERT(SYNC_RETRY_COUNT < 10, "SYNC_RETRY_COUNT shall be less than 10"); + uint32_t timeout; /* Add retries and convert to unit in 10's of ms */ interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(interval); - timeout = (interval_ms * SYNC_RETRY_COUNT) / 10; + timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10; /* Enforce restraints */ - timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, - BT_GAP_PER_ADV_MAX_TIMEOUT); + timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT); - return timeout; + return (uint16_t)timeout; } int bt_bap_broadcast_sink_register_cb(struct bt_bap_broadcast_sink_cb *cb) diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index 343f14eeddd..6bf781ed65e 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -2144,7 +2144,7 @@ static int cmd_preset(const struct shell *sh, size_t argc, char *argv[]) #if defined(CONFIG_BT_BAP_BROADCAST_SINK) #define INVALID_BROADCAST_ID (BT_AUDIO_BROADCAST_ID_MAX + 1) -#define SYNC_RETRY_COUNT 6 /* similar to retries for connections */ +#define PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO 20 /* Set the timeout relative to interval */ #define PA_SYNC_SKIP 5 static struct broadcast_sink_auto_scan { @@ -2165,19 +2165,16 @@ static void clear_auto_scan(void) static uint16_t interval_to_sync_timeout(uint16_t interval) { uint32_t interval_ms; - uint16_t timeout; - - /* Ensure that the following calculation does not overflow silently */ - __ASSERT(SYNC_RETRY_COUNT < 10, "SYNC_RETRY_COUNT shall be less than 10"); + uint32_t timeout; /* Add retries and convert to unit in 10's of ms */ interval_ms = BT_GAP_PER_ADV_INTERVAL_TO_MS(interval); - timeout = (interval_ms * SYNC_RETRY_COUNT) / 10; + timeout = (interval_ms * PA_SYNC_INTERVAL_TO_TIMEOUT_RATIO) / 10; /* Enforce restraints */ timeout = CLAMP(timeout, BT_GAP_PER_ADV_MIN_TIMEOUT, BT_GAP_PER_ADV_MAX_TIMEOUT); - return timeout; + return (uint16_t)timeout; } static bool scan_check_and_sync_broadcast(struct bt_data *data, void *user_data) diff --git a/subsys/bluetooth/audio/shell/bap_scan_delegator.c b/subsys/bluetooth/audio/shell/bap_scan_delegator.c index b89e48360a6..6b8e703a899 100644 --- a/subsys/bluetooth/audio/shell/bap_scan_delegator.c +++ b/subsys/bluetooth/audio/shell/bap_scan_delegator.c @@ -19,7 +19,7 @@ #include     RFC 6763 */ struct dns_sd_rec { - /** - e.g. "My HTTP Server" */ + /** "" - e.g. "My HTTP Server" */ const char *instance; - /** Top half of the such as "_http" */ + /** Top half of the "" such as "_http" */ const char *service; - /** Bottom half of the "_tcp" or "_udp" */ + /** Bottom half of the "" "_tcp" or "_udp" */ const char *proto; - /** such as "local" or "zephyrproject.org" */ + /** "" such as "local" or "zephyrproject.org" */ const char *domain; /** DNS TXT record */ const char *text; @@ -235,6 +231,8 @@ struct dns_sd_rec { const uint16_t *port; }; +/** @cond INTERNAL_HIDDEN */ + /** * @brief Empty TXT specifier for DNS-SD * diff --git a/include/zephyr/net/mdns_responder.h b/include/zephyr/net/mdns_responder.h new file mode 100644 index 00000000000..6ec9bb4c706 --- /dev/null +++ b/include/zephyr/net/mdns_responder.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief mDNS responder API + * + * This file contains the mDNS responder API. These APIs are used by the + * to register mDNS records. + */ + +#ifndef ZEPHYR_INCLUDE_NET_MDNS_RESPONDER_H_ +#define ZEPHYR_INCLUDE_NET_MDNS_RESPONDER_H_ + +#include +#include + +/** + * @brief Register continuous memory of @ref dns_sd_rec records. + * + * mDNS responder will start with iteration over mDNS records registered using + * @ref DNS_SD_REGISTER_SERVICE (if any) and then go over external records. + * + * @param records A pointer to an array of mDNS records. It is stored internally + * without copying the content so it must be kept valid. It can + * be set to NULL, e.g. before freeing the memory block. + * @param count The number of elements + * @return 0 for OK; -EINVAL for invalid parameters. + */ +int mdns_responder_set_ext_records(const struct dns_sd_rec *records, size_t count); + +#endif /* ZEPHYR_INCLUDE_NET_MDNS_RESPONDER_H_ */ diff --git a/subsys/net/lib/dns/dns_sd.c b/subsys/net/lib/dns/dns_sd.c index fa55a24271b..31fd8f6b9dd 100644 --- a/subsys/net/lib/dns/dns_sd.c +++ b/subsys/net/lib/dns/dns_sd.c @@ -857,6 +857,7 @@ int dns_sd_handle_service_type_enum(const struct dns_sd_rec *inst, if (!port_in_use(proto, ntohs(*(inst->port)), addr4, addr6)) { /* Service is not yet bound, so do not advertise */ + NET_DBG("service not bound"); return -EHOSTDOWN; } diff --git a/subsys/net/lib/dns/dns_sd.h b/subsys/net/lib/dns/dns_sd.h index a28062a3e3a..d32eb2cbae4 100644 --- a/subsys/net/lib/dns/dns_sd.h +++ b/subsys/net/lib/dns/dns_sd.h @@ -33,6 +33,12 @@ extern "C" { #define DNS_SD_FOREACH(it) \ STRUCT_SECTION_FOREACH(dns_sd_rec, it) +#define DNS_SD_COUNT(dst) \ + STRUCT_SECTION_COUNT(dns_sd_rec, dst) + +#define DNS_SD_GET(i, dst) \ + STRUCT_SECTION_GET(dns_sd_rec, i, dst) + /** * @brief Extract labels from a DNS-SD PTR query * diff --git a/subsys/net/lib/dns/mdns_responder.c b/subsys/net/lib/dns/mdns_responder.c index 90f958725bc..15a4c276467 100644 --- a/subsys/net/lib/dns/mdns_responder.c +++ b/subsys/net/lib/dns/mdns_responder.c @@ -52,6 +52,8 @@ static struct net_context *ipv6[MAX_IPV6_IFACE_COUNT]; #endif static struct net_mgmt_event_callback mgmt_cb; +static const struct dns_sd_rec *external_records; +static size_t external_records_count; #define BUF_ALLOC_TIMEOUT K_MSEC(100) @@ -340,6 +342,7 @@ static void send_sd_response(struct net_context *ctx, struct net_buf *result) { int ret; + const struct dns_sd_rec *record; /* filter must be zero-initialized for "wildcard" port */ struct dns_sd_rec filter = {0}; struct sockaddr dst; @@ -359,6 +362,8 @@ static void send_sd_response(struct net_context *ctx, ARRAY_SIZE(domain_buf), }; size_t n = ARRAY_SIZE(label); + size_t rec_num; + size_t ext_rec_num = external_records_count; BUILD_ASSERT(ARRAY_SIZE(label) == ARRAY_SIZE(size), ""); @@ -423,7 +428,21 @@ static void send_sd_response(struct net_context *ctx, service_type_enum = true; } - DNS_SD_FOREACH(record) { + DNS_SD_COUNT(&rec_num); + + while (rec_num > 0 || ext_rec_num > 0) { + /* + * The loop will always iterate over all entries, it can be done + * backwards for simplicity + */ + if (rec_num > 0) { + DNS_SD_GET(rec_num - 1, &record); + rec_num--; + } else { + record = &external_records[ext_rec_num - 1]; + ext_rec_num--; + } + /* Checks validity and then compare */ if (dns_sd_rec_match(record, &filter)) { NET_DBG("matched query: %s.%s.%s.%s port: %u", @@ -760,6 +779,8 @@ static int init_listener(void) static int mdns_responder_init(void) { + external_records = NULL; + external_records_count = 0; net_mgmt_init_event_callback(&mgmt_cb, mdns_iface_event_handler, NET_EVENT_IF_UP); @@ -769,4 +790,16 @@ static int mdns_responder_init(void) return init_listener(); } +int mdns_responder_set_ext_records(const struct dns_sd_rec *records, size_t count) +{ + if (records == NULL || count == 0) { + return -EINVAL; + } + + external_records = records; + external_records_count = count; + + return 0; +} + SYS_INIT(mdns_responder_init, APPLICATION, CONFIG_MDNS_RESPONDER_INIT_PRIO); From 5e46a49358ecd7949f954d1a644ae7683e4f63be Mon Sep 17 00:00:00 2001 From: Konrad Derda Date: Thu, 7 Mar 2024 12:18:03 +0100 Subject: [PATCH 1219/2402] tests: net: mdns: add test for external mDNS records This commit adds a test for externally stored mDNS records for mDNS responder. Signed-off-by: Konrad Derda --- tests/net/lib/mdns_responder/CMakeLists.txt | 13 + tests/net/lib/mdns_responder/prj.conf | 30 ++ tests/net/lib/mdns_responder/src/main.c | 443 ++++++++++++++++++++ tests/net/lib/mdns_responder/testcase.yaml | 9 + 4 files changed, 495 insertions(+) create mode 100644 tests/net/lib/mdns_responder/CMakeLists.txt create mode 100644 tests/net/lib/mdns_responder/prj.conf create mode 100644 tests/net/lib/mdns_responder/src/main.c create mode 100644 tests/net/lib/mdns_responder/testcase.yaml diff --git a/tests/net/lib/mdns_responder/CMakeLists.txt b/tests/net/lib/mdns_responder/CMakeLists.txt new file mode 100644 index 00000000000..00c8d5c34c1 --- /dev/null +++ b/tests/net/lib/mdns_responder/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(mdns_responder) + +target_include_directories(app PRIVATE + ${ZEPHYR_BASE}/subsys/net/lib/dns + ${ZEPHYR_BASE}/subsys/net/ip +) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/tests/net/lib/mdns_responder/prj.conf b/tests/net/lib/mdns_responder/prj.conf new file mode 100644 index 00000000000..f7c6945827c --- /dev/null +++ b/tests/net/lib/mdns_responder/prj.conf @@ -0,0 +1,30 @@ +# Networking config +CONFIG_NETWORKING=y +CONFIG_NET_TEST=y +CONFIG_NET_DRIVERS=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_IPV4=y +CONFIG_NET_IPV6=y + +# Network driver config +CONFIG_TEST_RANDOM_GENERATOR=y + +CONFIG_MDNS_RESPONDER=y +CONFIG_NET_HOSTNAME_ENABLE=y +CONFIG_DNS_SD=y +CONFIG_DNS_SD_LOG_LEVEL_DBG=y + +CONFIG_ZTEST=y +CONFIG_ZTEST_STACK_SIZE=2048 + +# Maybe avoid stack overflow on mps2/an385? +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_NET_MAX_CONTEXTS=8 +CONFIG_NET_L2_DUMMY=y +CONFIG_NET_L2_ETHERNET=n +CONFIG_NET_LOOPBACK=n +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUM=n +CONFIG_NET_PKT_RX_COUNT=16 +CONFIG_NET_PKT_TX_COUNT=16 diff --git a/tests/net/lib/mdns_responder/src/main.c b/tests/net/lib/mdns_responder/src/main.c new file mode 100644 index 00000000000..25a50ffe5cf --- /dev/null +++ b/tests/net/lib/mdns_responder/src/main.c @@ -0,0 +1,443 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define LOG_LEVEL LOG_LEVEL_DBG +#include +LOG_MODULE_REGISTER(mdns_resp_test); + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#define NULL_CHAR_SIZE 1 +#define EXT_RECORDS_NUM 3 +#define MAX_RESP_PKTS 8 +#define MAX_TXT_SIZE 128 +#define RESPONSE_TIMEOUT (K_MSEC(250)) + +struct service_info { + bool used; + char instance[DNS_SD_INSTANCE_MAX_SIZE + NULL_CHAR_SIZE]; + char service[DNS_SD_SERVICE_MAX_SIZE + NULL_CHAR_SIZE]; + char proto[DNS_SD_PROTO_SIZE + NULL_CHAR_SIZE]; + char domain[DNS_SD_DOMAIN_MAX_SIZE + NULL_CHAR_SIZE]; + char text[MAX_TXT_SIZE]; + uint16_t port; + struct dns_sd_rec *record; +}; + +static struct net_if *iface1; + +static struct net_if_test { + uint8_t idx; /* not used for anything, just a dummy value */ + uint8_t mac_addr[sizeof(struct net_eth_addr)]; + struct net_linkaddr ll_addr; +} net_iface1_data; + +static const uint8_t ipv6_hdr_start[] = { +0x60, 0x05, 0xe7, 0x00 +}; + +static const uint8_t ipv6_hdr_rest[] = { +0x11, 0xff, 0xfe, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9f, 0x74, 0x88, +0x9c, 0x1b, 0x44, 0x72, 0x39, 0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfb +}; + +static const uint8_t dns_sd_service_enumeration_query[] = { +0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, +0x5f, 0x73, 0x65, 0x72, 0x76, 0x69, 0x63, 0x65, 0x73, 0x07, 0x5f, 0x64, 0x6e, +0x73, 0x2d, 0x73, 0x64, 0x04, 0x5f, 0x75, 0x64, 0x70, 0x05, 0x6c, 0x6f, 0x63, +0x61, 0x6c, 0x00, 0x00, 0x0c, 0x00, 0x01 +}; + +static const uint8_t service_enum_start[] = { +0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x09, +0x5f, 0x73, 0x65, 0x72, 0x76, 0x69, 0x63, 0x65, 0x73, 0x07, 0x5f, 0x64, 0x6e, +0x73, 0x2d, 0x73, 0x64, 0x04, 0x5f, 0x75, 0x64, 0x70, 0x05, 0x6c, 0x6f, 0x63, +0x61, 0x6c, 0x00, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x00, 0x11, 0x94 +}; + +static const uint8_t payload_bar_udp_local[] = { +0x00, 0x0c, 0x04, 0x5f, 0x62, 0x61, 0x72, 0x04, 0x5f, 0x75, 0x64, 0x70, 0xc0, +0x23 +}; + +static const uint8_t payload_custom_tcp_local[] = { +0x00, 0x0f, 0x07, 0x5f, 0x63, 0x75, 0x73, 0x74, 0x6f, 0x6d, 0x04, +0x5f, 0x74, 0x63, 0x70, 0xc0, 0x23 +}; + +static const uint8_t payload_foo_tcp_local[] = { +0x00, 0x0c, 0x04, 0x5f, 0x66, 0x6f, 0x6f, 0x04, 0x5f, 0x74, 0x63, 0x70, 0xc0, +0x23 +}; + +static const uint8_t payload_foo_udp_local[] = { +0x00, 0x0c, 0x04, 0x5f, 0x66, 0x6f, 0x6f, 0x04, 0x5f, 0x75, 0x64, 0x70, 0xc0, +0x23 +}; + +static uint8_t mdns_server_ipv6_addr[] = { +0xff, 0x02, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xfb +}; + +static struct in6_addr ll_addr = {{{ +0xfe, 0x80, 0x43, 0xb8, 0, 0, 0, 0, 0x9f, 0x74, 0x88, 0x9c, 0x1b, 0x44, 0x72, 0x39 +}}}; + +static struct in6_addr sender_ll_addr = {{{ +0xfe, 0x80, 0, 0, 0, 0, 0, 0, 0x9f, 0x74, 0x88, 0x9c, 0x1b, 0x44, 0x72, 0x39 +}}}; + +static bool test_started; +static struct k_sem wait_data; +static struct net_pkt *response_pkts[MAX_RESP_PKTS]; +static size_t responses_count; +static struct service_info services[EXT_RECORDS_NUM]; +static struct dns_sd_rec records[EXT_RECORDS_NUM]; + +static uint8_t *net_iface_get_mac(const struct device *dev) +{ + struct net_if_test *data = dev->data; + + if (data->mac_addr[2] == 0x00) { + /* 00-00-5E-00-53-xx Documentation RFC 7042 */ + data->mac_addr[0] = 0x00; + data->mac_addr[1] = 0x00; + data->mac_addr[2] = 0x5E; + data->mac_addr[3] = 0x00; + data->mac_addr[4] = 0x53; + data->mac_addr[5] = 0x01; + } + + data->ll_addr.addr = data->mac_addr; + data->ll_addr.len = 6U; + + return data->mac_addr; +} + +static void net_iface_init(struct net_if *iface) +{ + uint8_t *mac = net_iface_get_mac(net_if_get_device(iface)); + + net_if_set_link_addr(iface, mac, sizeof(struct net_eth_addr), + NET_LINK_ETHERNET); +} + +static int sender_iface(const struct device *dev, struct net_pkt *pkt) +{ + struct net_ipv6_hdr *hdr; + + if (!pkt->buffer) { + return -ENODATA; + } + + if (test_started) { + hdr = NET_IPV6_HDR(pkt); + + if (net_ipv6_addr_cmp_raw(hdr->dst, mdns_server_ipv6_addr)) { + if (responses_count < MAX_RESP_PKTS) { + net_pkt_ref(pkt); + response_pkts[responses_count++] = pkt; + k_sem_give(&wait_data); + } + } + } + + return 0; +} + +static struct dummy_api net_iface_api = { + .iface_api.init = net_iface_init, + .send = sender_iface, +}; + +#define _ETH_L2_LAYER DUMMY_L2 +#define _ETH_L2_CTX_TYPE NET_L2_GET_CTX_TYPE(DUMMY_L2) + +NET_DEVICE_INIT_INSTANCE(net_iface1_test, + "iface1", + iface1, + NULL, + NULL, + &net_iface1_data, + NULL, + CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, + &net_iface_api, + _ETH_L2_LAYER, + _ETH_L2_CTX_TYPE, + 127); + +static void *test_setup(void) +{ + struct net_if_addr *ifaddr; + int idx; + + memset(response_pkts, 0, sizeof(response_pkts)); + memset(services, 0, sizeof(services)); + memset(records, 0, sizeof(records)); + + responses_count = 0; + + /* Cross assign records and buffers to entries for allocation */ + for (int i = 0; i < EXT_RECORDS_NUM; ++i) { + services[i].record = &records[i]; + + records[i].instance = services[i].instance; + records[i].service = services[i].service; + records[i].proto = services[i].proto; + records[i].domain = services[i].domain; + records[i].text = services[i].text; + records[i].port = &services[i].port; + } + + mdns_responder_set_ext_records(records, EXT_RECORDS_NUM); + + /* The semaphore is there to wait the data to be received. */ + k_sem_init(&wait_data, 0, UINT_MAX); + + iface1 = net_if_get_by_index(1); + + zassert_not_null(iface1, "Iface1 is NULL"); + + ((struct net_if_test *) net_if_get_device(iface1)->data)->idx = + net_if_get_by_iface(iface1); + + idx = net_if_get_by_iface(iface1); + zassert_equal(idx, 1, "Invalid index iface1"); + + zassert_not_null(iface1, "Interface 1"); + + ifaddr = net_if_ipv6_addr_add(iface1, &ll_addr, + NET_ADDR_MANUAL, 0); + + net_ipv6_nbr_add(iface1, &sender_ll_addr, net_if_get_link_addr(iface1), false, + NET_IPV6_NBR_STATE_STATIC); + + zassert_not_null(ifaddr, "Failed to add LL-addr"); + + /* we need to set the addresses preferred */ + ifaddr->addr_state = NET_ADDR_PREFERRED; + + net_if_up(iface1); + + return NULL; +} + +static void free_service(struct service_info *service) +{ + service->used = false; + service->instance[0] = '\0'; + service->service[0] = '\0'; + service->proto[0] = '\0'; + service->domain[0] = '\0'; + service->port = 0; + +} + +static void free_ext_record(struct dns_sd_rec *rec) +{ + for (int i = 0; i < EXT_RECORDS_NUM; ++i) { + if (services[i].record == rec) { + free_service(&services[i]); + return; + } + } +} + +static void before(void *d) +{ + ARG_UNUSED(d); + + test_started = true; +} + +static void cleanup(void *d) +{ + ARG_UNUSED(d); + + test_started = false; + + for (size_t i = 0; i < responses_count; ++i) { + if (response_pkts[i]) { + net_pkt_unref(response_pkts[i]); + response_pkts[i] = NULL; + } + } + + /* Clear semaphore counter */ + while (k_sem_take(&wait_data, K_NO_WAIT) == 0) { + /* NOP */ + } + + for (int i = 0; i < EXT_RECORDS_NUM; ++i) { + if (services[i].used) { + free_service(&services[i]); + } + } +} + +static void send_msg(const uint8_t *data, size_t len) +{ + struct net_pkt *pkt; + int res; + + pkt = net_pkt_alloc_with_buffer(iface1, NET_IPV6UDPH_LEN + len, AF_UNSPEC, + 0, K_FOREVER); + zassert_not_null(pkt, "PKT is null"); + + res = net_pkt_write(pkt, ipv6_hdr_start, sizeof(ipv6_hdr_start)); + zassert_equal(res, 0, "pkt write for header start failed"); + + res = net_pkt_write_be16(pkt, len + NET_UDPH_LEN); + zassert_equal(res, 0, "pkt write for header length failed"); + + res = net_pkt_write(pkt, ipv6_hdr_rest, sizeof(ipv6_hdr_rest)); + zassert_equal(res, 0, "pkt write for rest of the header failed"); + + res = net_pkt_write_be16(pkt, 5353); + zassert_equal(res, 0, "pkt write for UDP src port failed"); + + res = net_pkt_write_be16(pkt, 5353); + zassert_equal(res, 0, "pkt write for UDP dst port failed"); + + res = net_pkt_write_be16(pkt, len + NET_UDPH_LEN); + zassert_equal(res, 0, "pkt write for UDP length failed"); + + /* to simplify testing checking of UDP checksum is disabled in prj.conf */ + res = net_pkt_write_be16(pkt, 0); + zassert_equal(res, 0, "net_pkt_write_be16() for UDP checksum failed"); + + res = net_pkt_write(pkt, data, len); + zassert_equal(res, 0, "net_pkt_write() for data failed"); + + res = net_recv_data(iface1, pkt); + zassert_equal(res, 0, "net_recv_data() failed"); +} + +static struct dns_sd_rec *alloc_ext_record(const char *instance, const char *service, + const char *proto, const char *domain, uint8_t *txt, + size_t txt_len, uint16_t port) +{ + for (int i = 0; i < EXT_RECORDS_NUM; ++i) { + if (!services[i].used) { + services[i].used = true; + + strcpy(services[i].instance, instance); + strcpy(services[i].service, service); + strcpy(services[i].proto, proto); + strcpy(services[i].domain, domain); + + if (txt && txt_len) { + memcpy(services[i].text, txt, txt_len); + } + + services[i].port = htons(port); + services[i].record->text_size = txt_len; + + return services[i].record; + } + } + + return NULL; +} + +static void check_service_type_enum_resp(struct net_pkt *pkt, const uint8_t *payload, size_t len) +{ + int res; + + net_pkt_cursor_init(pkt); + + net_pkt_set_overwrite(pkt, true); + net_pkt_skip(pkt, NET_IPV6UDPH_LEN); + + res = net_buf_data_match(pkt->cursor.buf, pkt->cursor.pos - pkt->cursor.buf->data, + service_enum_start, sizeof(service_enum_start)); + + zassert_equal(res, sizeof(service_enum_start), + "mDNS content beginning does not match"); + + net_pkt_skip(pkt, sizeof(service_enum_start)); + + res = net_pkt_get_len(pkt) - net_pkt_get_current_offset(pkt); + zassert_equal(res, len, "Remaining packet's length does match payload's length"); + + res = net_buf_data_match(pkt->cursor.buf, pkt->cursor.pos - pkt->cursor.buf->data, payload, + len); + zassert_equal(res, len, "Payload does not match"); +} + +ZTEST(test_mdns_responder, test_external_records) +{ + int res; + struct dns_sd_rec *records[EXT_RECORDS_NUM]; + + /* mDNS responder can advertise only ports that are bound - reuse its own port */ + DNS_SD_REGISTER_UDP_SERVICE(foo, "zephyr", "_foo", "local", DNS_SD_EMPTY_TXT, 5353); + + records[0] = alloc_ext_record("test_rec", "_custom", "_tcp", "local", NULL, 0, 5353); + zassert_not_null(records[0], "Failed to alloc the record"); + + records[1] = alloc_ext_record("foo", "_bar", "_udp", "local", NULL, 0, 5353); + zassert_not_null(records[1], "Failed to alloc the record"); + + records[2] = alloc_ext_record("bar", "_foo", "_tcp", "local", NULL, 0, 5353); + zassert_not_null(records[2], "Failed to alloc the record"); + + /* Request service type enumeration */ + send_msg(dns_sd_service_enumeration_query, sizeof(dns_sd_service_enumeration_query)); + + /* Expect 4 packets */ + for (int i = 0; i < 4; ++i) { + res = k_sem_take(&wait_data, RESPONSE_TIMEOUT); + zassert_equal(res, 0, "Did not receive a response number %d", i + 1); + } + + /* Responder always starts with statically allocated services */ + check_service_type_enum_resp(response_pkts[0], payload_foo_udp_local, + sizeof(payload_foo_udp_local)); + + /* Responder iterates through external records backwards so check responses in LIFO seq. */ + check_service_type_enum_resp(response_pkts[1], payload_foo_tcp_local, + sizeof(payload_foo_tcp_local)); + check_service_type_enum_resp(response_pkts[2], payload_bar_udp_local, + sizeof(payload_bar_udp_local)); + check_service_type_enum_resp(response_pkts[3], payload_custom_tcp_local, + sizeof(payload_custom_tcp_local)); + + /* Remove record from the middle */ + free_ext_record(records[1]); + + /* Repeat service type enumeration */ + send_msg(dns_sd_service_enumeration_query, sizeof(dns_sd_service_enumeration_query)); + + /* Expect 3 packets */ + for (int i = 0; i < 3; ++i) { + res = k_sem_take(&wait_data, RESPONSE_TIMEOUT); + zassert_equal(res, 0, "Did not receive a response number %d", i + 1); + } + + /* Repeat checks without the removed record */ + check_service_type_enum_resp(response_pkts[4], payload_foo_udp_local, + sizeof(payload_foo_udp_local)); + check_service_type_enum_resp(response_pkts[5], payload_foo_tcp_local, + sizeof(payload_foo_tcp_local)); + check_service_type_enum_resp(response_pkts[6], payload_custom_tcp_local, + sizeof(payload_custom_tcp_local)); +} + +ZTEST_SUITE(test_mdns_responder, NULL, test_setup, before, cleanup, NULL); diff --git a/tests/net/lib/mdns_responder/testcase.yaml b/tests/net/lib/mdns_responder/testcase.yaml new file mode 100644 index 00000000000..ae9f6d9dbf2 --- /dev/null +++ b/tests/net/lib/mdns_responder/testcase.yaml @@ -0,0 +1,9 @@ +common: + tags: + - dns + - net + depends_on: netif +tests: + net.mdns: + min_ram: 21 + timeout: 600 From 1bea938c9f8c02190daa582144a3cff65e1a12f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Mon, 18 Mar 2024 08:04:27 +0100 Subject: [PATCH 1220/2402] mgmt: hawkbit: remove hb_context.status_buffer_size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit remove hb_context.status_buffer_size and replace it with sizeof(hb_context.status_buffer), because hb_context.status_buffer_size is never set. Signed-off-by: Fin Maaß --- subsys/mgmt/hawkbit/hawkbit.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c index 90d493c3849..e3ea6592b64 100644 --- a/subsys/mgmt/hawkbit/hawkbit.c +++ b/subsys/mgmt/hawkbit/hawkbit.c @@ -81,7 +81,6 @@ static struct hawkbit_context { uint8_t *response_data; int32_t json_action_id; size_t url_buffer_size; - size_t status_buffer_size; struct hawkbit_download dl; struct http_request http_req; struct flash_img_context flash_ctx; @@ -853,7 +852,7 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type ret = json_obj_encode_buf(json_cfg_descr, ARRAY_SIZE(json_cfg_descr), &cfg, hb_context.status_buffer, - hb_context.status_buffer_size - 1); + sizeof(hb_context.status_buffer)); if (ret) { LOG_ERR("Can't encode the JSON script (%s): %d", "HAWKBIT_CONFIG_DEVICE", ret); @@ -885,7 +884,7 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type ret = json_obj_encode_buf(json_close_descr, ARRAY_SIZE(json_close_descr), &close, hb_context.status_buffer, - hb_context.status_buffer_size - 1); + sizeof(hb_context.status_buffer)); if (ret) { LOG_ERR("Can't encode the JSON script (%s): %d", "HAWKBIT_CLOSE", ret); return false; @@ -932,7 +931,7 @@ static bool send_request(enum http_method method, enum hawkbit_http_request type ret = json_obj_encode_buf(json_dep_fbk_descr, ARRAY_SIZE(json_dep_fbk_descr), &feedback, hb_context.status_buffer, - hb_context.status_buffer_size - 1); + sizeof(hb_context.status_buffer)); if (ret) { LOG_ERR("Can't encode the JSON script (%s): %d", "HAWKBIT_REPORT", ret); return ret; From fddbd79cf7d18d11e61671601f76613d659af24b Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 22 Mar 2024 09:11:39 +0100 Subject: [PATCH 1221/2402] tests/drivers/can/timing: Remove unused overlays The native_{posix,sim}_64 boards are not anymore twister targets, native_{posix,sim}/native/64 are, and those default to just use the overlays for the non variant version. These 2 overlays were not used by anything. Remove them. Signed-off-by: Alberto Escolar Piedras --- tests/drivers/can/timing/boards/native_posix_64.conf | 1 - tests/drivers/can/timing/boards/native_sim_64.conf | 1 - 2 files changed, 2 deletions(-) delete mode 100644 tests/drivers/can/timing/boards/native_posix_64.conf delete mode 100644 tests/drivers/can/timing/boards/native_sim_64.conf diff --git a/tests/drivers/can/timing/boards/native_posix_64.conf b/tests/drivers/can/timing/boards/native_posix_64.conf deleted file mode 100644 index 7b071f3a54f..00000000000 --- a/tests/drivers/can/timing/boards/native_posix_64.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_TEST_ALL_BITRATES=y diff --git a/tests/drivers/can/timing/boards/native_sim_64.conf b/tests/drivers/can/timing/boards/native_sim_64.conf deleted file mode 100644 index 7b071f3a54f..00000000000 --- a/tests/drivers/can/timing/boards/native_sim_64.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_TEST_ALL_BITRATES=y From 66b475a3aa4d73f4ddd5be5a7a1e0f3c7028e539 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Thu, 7 Mar 2024 10:06:34 +0100 Subject: [PATCH 1222/2402] scripts: remove board name from the qualifiers in list_boards.py Fixes: #69329 The board name was printed as part of printing board qualifiers because those was being concatenated in the `board_v2_qualifiers()` method. Keep the qualifiers separated from the board name and let the caller concatenate the strings when required. Completion scripts are also updated to handle the corrected behaviour. Signed-off-by: Torsten Rasmussen --- cmake/modules/boards.cmake | 8 +++++--- scripts/ci/check_compliance.py | 3 ++- scripts/list_boards.py | 18 +++++++----------- .../completion/west-completion.bash | 9 +++++++-- .../completion/west-completion.fish | 19 ++++++------------- .../completion/west-completion.zsh | 9 ++++++--- 6 files changed, 33 insertions(+), 33 deletions(-) diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index c439537faa0..47c29e2ded3 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -284,12 +284,14 @@ elseif(HWMv2) string(REGEX REPLACE "^//" "/${LIST_BOARD_SOCS}/" BOARD_QUALIFIERS "${BOARD_QUALIFIERS}") endif() - if(NOT ("${BOARD}${BOARD_QUALIFIERS}" IN_LIST LIST_BOARD_QUALIFIERS)) - string(REPLACE ";" "\n" LIST_BOARD_QUALIFIERS "${LIST_BOARD_QUALIFIERS}") + set(board_targets ${LIST_BOARD_QUALIFIERS}) + list(TRANSFORM board_targets PREPEND "${BOARD}/") + if(NOT ("${BOARD}${BOARD_QUALIFIERS}" IN_LIST board_targets)) + string(REPLACE ";" "\n" board_targets "${board_targets}") unset(CACHED_BOARD CACHE) message(FATAL_ERROR "Board qualifiers `${BOARD_QUALIFIERS}` for board \ `${BOARD}` not found. Please specify a valid board target.\n" - "Valid board qualifiers for ${BOARD_NAME} are:\n${LIST_BOARD_QUALIFIERS}\n") + "Valid board targets for ${BOARD_NAME} are:\n${board_targets}\n") endif() endif() else() diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index c351643401c..a77bd580453 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -449,7 +449,8 @@ def get_v2_model(self, kconfig_dir): fp.write('config ' + board_str + '\n') fp.write('\t bool\n') for qualifier in list_boards.board_v2_qualifiers(board): - board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", qualifier).upper() + board_str = ('BOARD_' + board.name + '_' + + re.sub(r"[^a-zA-Z0-9_]", "_", qualifier)).upper() fp.write('config ' + board_str + '\n') fp.write('\t bool\n') fp.write( diff --git a/scripts/list_boards.py b/scripts/list_boards.py index 03b1adaca83..5321f31b0bc 100755 --- a/scripts/list_boards.py +++ b/scripts/list_boards.py @@ -275,10 +275,10 @@ def add_args_formatting(parser): help='''CMake Format string to use to list each board''') -def variant_v2_qualifiers(variant, qualifiers): - qualifiers_list = [qualifiers + '/' + variant.name] +def variant_v2_qualifiers(variant, qualifiers = None): + qualifiers_list = [variant.name] if qualifiers is None else [qualifiers + '/' + variant.name] for v in variant.variants: - qualifiers_list.extend(variant_v2_qualifiers(v, qualifiers + '/' + variant.name)) + qualifiers_list.extend(variant_v2_qualifiers(v, qualifiers_list[0])) return qualifiers_list @@ -288,21 +288,17 @@ def board_v2_qualifiers(board): for s in board.socs: if s.cpuclusters: for c in s.cpuclusters: - id_str = board.name + '/' + s.name + '/' + c.name + id_str = s.name + '/' + c.name qualifiers_list.append(id_str) for v in c.variants: qualifiers_list.extend(variant_v2_qualifiers(v, id_str)) else: - id_str = board.name + '/' + s.name - qualifiers_list.append(id_str) + qualifiers_list.append(s.name) for v in s.variants: - qualifiers_list.extend(variant_v2_qualifiers(v, id_str)) - - if not board.socs: - qualifiers_list.append(board.name) + qualifiers_list.extend(variant_v2_qualifiers(v, s.name)) for v in board.variants: - qualifiers_list.extend(variant_v2_qualifiers(v, board.name)) + qualifiers_list.extend(variant_v2_qualifiers(v)) return qualifiers_list diff --git a/scripts/west_commands/completion/west-completion.bash b/scripts/west_commands/completion/west-completion.bash index 2ccc4446ad3..d812e8933b1 100644 --- a/scripts/west_commands/completion/west-completion.bash +++ b/scripts/west_commands/completion/west-completion.bash @@ -392,8 +392,13 @@ __set_comp_west_projs() __set_comp_west_boards() { - boards="$(__west_x boards --format={identifiers} "$@")\n$(__west_x boards --format={name} "$@")" - __set_comp ${boards//,/\ } + boards=( $(__west_x boards --format='{name}|{qualifiers}' "$@") ) + for i in ${!boards[@]}; do + name="${boards[$i]%%|*}" + transformed_board="${boards[$i]//|//}" + boards[$i]="${transformed_board//,/\ ${name}\/}" + done + __set_comp ${boards[@]} } __comp_west_west() diff --git a/scripts/west_commands/completion/west-completion.fish b/scripts/west_commands/completion/west-completion.fish index 33c6942dd8e..51e61141e8a 100644 --- a/scripts/west_commands/completion/west-completion.fish +++ b/scripts/west_commands/completion/west-completion.fish @@ -196,19 +196,12 @@ function __zephyr_west_complete_help end function __zephyr_west_complete_board - # HWMv1 - set -l boards (west 2>/dev/null boards --format="{name} {arch}") + set -l boards (west 2>/dev/null boards --format="{name}|{qualifiers}") for board in $boards - set -l b (string split " " $board) - printf "%s\n" $b[1]\t"$b[2]" - end - - # HWMv2 - set -l boards (west 2>/dev/null boards --format="{identifiers}") - for board in $boards - set -l b (string split "," $board) - for variant in $b - printf "%s\n" $variant[1] + set -l b (string split "|" $board) + set -l qualifiers (string split "," $b[2]) + for i in $qualifiers + printf "%s\n" $b[1]/$i end end end @@ -307,7 +300,7 @@ complete -c west -n "__zephyr_west_seen_subcommand_from boards" -l soc-root -xa # build complete -c west -n "__zephyr_west_use_subcommand; and __zephyr_west_check_if_in_workspace" -ra build -d "compile a Zephyr application" complete -c west -n "__zephyr_west_seen_subcommand_from build" -ra "(__zephyr_west_complete_directories)" -complete -c west -n "__zephyr_west_seen_subcommand_from build" -o b -l board -xa "(__zephyr_west_complete_board)" -d "board to build for" +complete -c west -n "__zephyr_west_seen_subcommand_from build" -o b -l board -xa "(__zephyr_west_complete_board)" complete -c west -n "__zephyr_west_seen_subcommand_from build" -o d -l build-dir -xa "(__zephyr_west_complete_directories)" -d "build directory to create or use" complete -c west -n "__zephyr_west_seen_subcommand_from build" -o f -l force -d "ignore errors and continue" complete -c west -n "__zephyr_west_seen_subcommand_from build" -l sysbuild -d "create multi-domain build system" diff --git a/scripts/west_commands/completion/west-completion.zsh b/scripts/west_commands/completion/west-completion.zsh index 000b43a87b3..e1a01199884 100644 --- a/scripts/west_commands/completion/west-completion.zsh +++ b/scripts/west_commands/completion/west-completion.zsh @@ -102,9 +102,12 @@ _get_west_projs() { } _get_west_boards() { - _west_boards="$(__west_x boards --format={identifiers})\n$(__west_x boards --format={name})" - _west_boards=${_west_boards//$'\n'/\ } - _west_boards=${_west_boards//,/\ } + _west_boards=( $(__west_x boards --format='{name}|{qualifiers}') ) + for i in {1..${#_west_boards[@]}}; do + local name="${_west_boards[$i]%%|*}" + local transformed_board="${_west_boards[$i]//|//}" + _west_boards[$i]="${transformed_board//,/ ${name}/}" + done _west_boards=(${(@s/ /)_west_boards}) _describe 'boards' _west_boards From b29d73fcc476855b6c9960d60537ca36dbc048e7 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Wed, 6 Mar 2024 11:01:21 +0100 Subject: [PATCH 1223/2402] cmake: add CMake configure dependency to board.yml Fixes: #69840 Add CMake configure dependency on the board's board.yml file. This dependency ensures that CMake will re-run and pickup any changes to the current board's board.yml file. Signed-off-by: Torsten Rasmussen --- cmake/modules/boards.cmake | 1 + cmake/modules/soc_v2.cmake | 1 + 2 files changed, 2 insertions(+) diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index 47c29e2ded3..ee81b264c1f 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -199,6 +199,7 @@ if(NOT "${ret_board}" STREQUAL "") set(multi_val "REVISIONS;SOCS;QUALIFIERS") cmake_parse_arguments(LIST_BOARD "" "${single_val}" "${multi_val}" ${ret_board}) set(BOARD_DIR ${LIST_BOARD_DIR} CACHE PATH "Board directory for board (${BOARD})" FORCE) + set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${BOARD_DIR}/board.yml) # Create two CMake variables identifying the hw model. # CMake variable: HWM=[v1,v2] diff --git a/cmake/modules/soc_v2.cmake b/cmake/modules/soc_v2.cmake index 866958e1f80..6a03dd2cbf0 100644 --- a/cmake/modules/soc_v2.cmake +++ b/cmake/modules/soc_v2.cmake @@ -28,4 +28,5 @@ if(HWMv2) set(SOC_FAMILY ${CONFIG_SOC_FAMILY}) set(SOC_V2_DIR ${SOC_${SOC_NAME}_DIR}) set(SOC_FULL_DIR ${SOC_V2_DIR}) + set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${SOC_V2_DIR}/soc.yml) endif() From 07edc9a07061f5c3f13407e6f71d0263a5e57727 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Fri, 10 Nov 2023 15:46:04 +0100 Subject: [PATCH 1224/2402] drivers: net: nsos: new driver for Native Simulator offloaded sockets Add driver for 'native_sim' target that implements offloaded socket networking by the use of host networking stack and wrapped BSD sockets API. This driver has following advantages over existing networking drivers for emulated platforms that are already in tree: * no TUN/TAP use means that no additional setup is required on the host side: * possible to use it within unpriviledged Docker containers, either for development or in CI * possibility to use and test offloaded sockets (CONFIG_NET_SOCKETS_OFFLOAD=y) with emulated target, which allows to increase tests coverage of this feature, without requirement of using hardware Native Simulator host libc has different error codes than embedded libc used by Zephyr. Convert between those. Signed-off-by: Marcin Niestroj --- drivers/net/CMakeLists.txt | 10 + drivers/net/Kconfig | 16 ++ drivers/net/nsos.h | 100 +++++++ drivers/net/nsos_adapt.c | 333 +++++++++++++++++++++++ drivers/net/nsos_errno.c | 125 +++++++++ drivers/net/nsos_errno.h | 95 +++++++ drivers/net/nsos_sockets.c | 532 +++++++++++++++++++++++++++++++++++++ 7 files changed, 1211 insertions(+) create mode 100644 drivers/net/nsos.h create mode 100644 drivers/net/nsos_adapt.c create mode 100644 drivers/net/nsos_errno.c create mode 100644 drivers/net/nsos_errno.h create mode 100644 drivers/net/nsos_sockets.c diff --git a/drivers/net/CMakeLists.txt b/drivers/net/CMakeLists.txt index 0b431455a2a..d839b9690c3 100644 --- a/drivers/net/CMakeLists.txt +++ b/drivers/net/CMakeLists.txt @@ -9,3 +9,13 @@ if(CONFIG_NET_NATIVE) zephyr_library_sources_ifdef(CONFIG_SLIP slip.c) zephyr_library_sources_ifdef(CONFIG_NET_PPP ppp.c) endif() + +if(CONFIG_NET_NATIVE_OFFLOADED_SOCKETS) + zephyr_library_include_directories( + ${ZEPHYR_BASE}/subsys/net/lib/sockets + ) + zephyr_library_sources(nsos_errno.c) + zephyr_library_sources(nsos_sockets.c) + target_sources(native_simulator INTERFACE nsos_adapt.c) + target_sources(native_simulator INTERFACE nsos_errno.c) +endif() diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index e0167e80ccb..5ebda70c1d1 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -224,4 +224,20 @@ config NET_CANBUS_INIT_PRIORITY endif # NET_CAN +# +# Native simulator offloaded sockets +# + +config NET_NATIVE_OFFLOADED_SOCKETS + bool "Native Simulator offloaded sockets" + depends on ARCH_POSIX + depends on NATIVE_LIBRARY + depends on NET_SOCKETS_OFFLOAD + help + Offloaded sockets for Native Simulator utilize host BSD sockets API (like socket(), + connect(), send(), recvfrom(), etc.) in order to provide networking capability. + + This driver main advantage is that it is possible to use this driver without any + additional setup on the host side, unlike with the native TAP Ethernet driver. + endif # NET_DRIVERS diff --git a/drivers/net/nsos.h b/drivers/net/nsos.h new file mode 100644 index 00000000000..13a6b8f8826 --- /dev/null +++ b/drivers/net/nsos.h @@ -0,0 +1,100 @@ +/** + * Copyright (c) 2023-2024 Marcin Niestroj + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRIVERS_NET_NSOS_H__ +#define __DRIVERS_NET_NSOS_H__ + +#include +#include + +/* Protocol families. */ +#define NSOS_MID_PF_UNSPEC 0 /**< Unspecified protocol family. */ +#define NSOS_MID_PF_INET 1 /**< IP protocol family version 4. */ + +/* Address families. */ +#define NSOS_MID_AF_UNSPEC NSOS_MID_PF_UNSPEC /**< Unspecified address family. */ +#define NSOS_MID_AF_INET NSOS_MID_PF_INET /**< IP protocol family version 4. */ + +/** Protocol numbers from IANA/BSD */ +enum nsos_mid_net_ip_protocol { + NSOS_MID_IPPROTO_IP = 0, /**< IP protocol (pseudo-val for setsockopt() */ + NSOS_MID_IPPROTO_ICMP = 1, /**< ICMP protocol */ + NSOS_MID_IPPROTO_IGMP = 2, /**< IGMP protocol */ + NSOS_MID_IPPROTO_IPIP = 4, /**< IPIP tunnels */ + NSOS_MID_IPPROTO_TCP = 6, /**< TCP protocol */ + NSOS_MID_IPPROTO_UDP = 17, /**< UDP protocol */ + NSOS_MID_IPPROTO_IPV6 = 41, /**< IPv6 protocol */ + NSOS_MID_IPPROTO_ICMPV6 = 58, /**< ICMPv6 protocol */ + NSOS_MID_IPPROTO_RAW = 255, /**< RAW IP packets */ +}; + +/** Socket type */ +enum nsos_mid_net_sock_type { + NSOS_MID_SOCK_STREAM = 1, /**< Stream socket type */ + NSOS_MID_SOCK_DGRAM, /**< Datagram socket type */ + NSOS_MID_SOCK_RAW /**< RAW socket type */ +}; + +#define NSOS_MID_MSG_PEEK 0x02 +#define NSOS_MID_MSG_TRUNC 0x20 +#define NSOS_MID_MSG_DONTWAIT 0x40 +#define NSOS_MID_MSG_WAITALL 0x100 + +struct nsos_mid_sockaddr { + uint16_t sa_family; /* Address family */ + char sa_data[]; /* Socket address */ +}; + +struct nsos_mid_sockaddr_in { + uint16_t sin_family; /* AF_INET */ + uint16_t sin_port; /* Port number */ + uint32_t sin_addr; /* IPv4 address */ +}; + +struct nsos_mid_sockaddr_in6 { + uint16_t sin6_family; /* AF_INET6 */ + uint16_t sin6_port; /* Port number */ + uint32_t sin6_flowinfo; /* IPv6 flow info */ + uint8_t sin6_addr[16]; + uint32_t sin6_scope_id; /* Set of interfaces for a scope */ +}; + +struct nsos_mid_sockaddr_storage { + union { + struct nsos_mid_sockaddr_in sockaddr_in; + struct nsos_mid_sockaddr_in6 sockaddr_in6; + }; +}; + +struct nsos_mid_pollfd { + int fd; + short events; + short revents; +}; + +static inline void nsos_socket_flag_convert(int *flags_a, int flag_a, + int *flags_b, int flag_b) +{ + if ((*flags_a) & flag_a) { + *flags_a &= ~flag_a; + *flags_b |= flag_b; + } +} + +int nsos_adapt_get_errno(void); + +int nsos_adapt_socket(int family, int type, int proto); + +int nsos_adapt_bind(int fd, const struct nsos_mid_sockaddr *addr, size_t addrlen); +int nsos_adapt_connect(int fd, const struct nsos_mid_sockaddr *addr, size_t addrlen); +int nsos_adapt_listen(int fd, int backlog); +int nsos_adapt_accept(int fd, struct nsos_mid_sockaddr *addr, size_t *addrlen); +int nsos_adapt_sendto(int fd, const void *buf, size_t len, int flags, + const struct nsos_mid_sockaddr *addr, size_t addrlen); +int nsos_adapt_recvfrom(int fd, void *buf, size_t len, int flags, + struct nsos_mid_sockaddr *addr, size_t *addrlen); + +#endif /* __DRIVERS_NET_NSOS_H__ */ diff --git a/drivers/net/nsos_adapt.c b/drivers/net/nsos_adapt.c new file mode 100644 index 00000000000..37dfe9b2368 --- /dev/null +++ b/drivers/net/nsos_adapt.c @@ -0,0 +1,333 @@ +/** + * Copyright (c) 2023-2024 Marcin Niestroj + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * + * Linux (bottom) side of NSOS (Native Simulator Offloaded Sockets). + */ + +#include +#include +#include +#include +#include + +#include "nsos.h" +#include "nsos_errno.h" + +#include "nsi_tracing.h" + +#include + +int nsos_adapt_get_errno(void) +{ + return errno_to_nsos_mid(errno); +} + +static int socket_family_from_nsos_mid(int family_mid, int *family) +{ + switch (family_mid) { + case NSOS_MID_AF_UNSPEC: + *family = AF_UNSPEC; + break; + case NSOS_MID_AF_INET: + *family = AF_INET; + break; + default: + nsi_print_warning("%s: socket family %d not supported\n", __func__, family_mid); + return -NSOS_MID_EAFNOSUPPORT; + } + + return 0; +} + +static int socket_proto_from_nsos_mid(int proto_mid, int *proto) +{ + switch (proto_mid) { + case NSOS_MID_IPPROTO_IP: + *proto = IPPROTO_IP; + break; + case NSOS_MID_IPPROTO_ICMP: + *proto = IPPROTO_ICMP; + break; + case NSOS_MID_IPPROTO_IGMP: + *proto = IPPROTO_IGMP; + break; + case NSOS_MID_IPPROTO_IPIP: + *proto = IPPROTO_IPIP; + break; + case NSOS_MID_IPPROTO_TCP: + *proto = IPPROTO_TCP; + break; + case NSOS_MID_IPPROTO_UDP: + *proto = IPPROTO_UDP; + break; + case NSOS_MID_IPPROTO_IPV6: + *proto = IPPROTO_IPV6; + break; + case NSOS_MID_IPPROTO_RAW: + *proto = IPPROTO_RAW; + break; + default: + nsi_print_warning("%s: socket protocol %d not supported\n", __func__, proto_mid); + return -NSOS_MID_EPROTONOSUPPORT; + } + + return 0; +} + +static int socket_type_from_nsos_mid(int type_mid, int *type) +{ + switch (type_mid) { + case NSOS_MID_SOCK_STREAM: + *type = SOCK_STREAM; + break; + case NSOS_MID_SOCK_DGRAM: + *type = SOCK_DGRAM; + break; + case NSOS_MID_SOCK_RAW: + *type = SOCK_RAW; + break; + default: + nsi_print_warning("%s: socket type %d not supported\n", __func__, type_mid); + return -NSOS_MID_ESOCKTNOSUPPORT; + } + + return 0; +} + +static int socket_flags_from_nsos_mid(int flags_mid) +{ + int flags = 0; + + nsos_socket_flag_convert(&flags_mid, NSOS_MID_MSG_PEEK, + &flags, MSG_PEEK); + nsos_socket_flag_convert(&flags_mid, NSOS_MID_MSG_TRUNC, + &flags, MSG_TRUNC); + nsos_socket_flag_convert(&flags_mid, NSOS_MID_MSG_DONTWAIT, + &flags, MSG_DONTWAIT); + nsos_socket_flag_convert(&flags_mid, NSOS_MID_MSG_WAITALL, + &flags, MSG_WAITALL); + + if (flags_mid != 0) { + return -NSOS_MID_EINVAL; + } + + return flags; +} + +int nsos_adapt_socket(int family_mid, int type_mid, int proto_mid) +{ + int family; + int type; + int proto; + int ret; + + ret = socket_family_from_nsos_mid(family_mid, &family); + if (ret < 0) { + return ret; + } + + ret = socket_type_from_nsos_mid(type_mid, &type); + if (ret < 0) { + return ret; + } + + ret = socket_proto_from_nsos_mid(proto_mid, &proto); + if (ret < 0) { + return ret; + } + + ret = socket(family, type, proto); + if (ret < 0) { + return -errno_to_nsos_mid(errno); + } + + return ret; +} + +static int sockaddr_from_nsos_mid(struct sockaddr **addr, socklen_t *addrlen, + const struct nsos_mid_sockaddr *addr_mid, size_t addrlen_mid) +{ + if (!addr_mid || addrlen_mid == 0) { + *addr = NULL; + *addrlen = 0; + + return 0; + } + + switch (addr_mid->sa_family) { + case NSOS_MID_AF_INET: { + const struct nsos_mid_sockaddr_in *addr_in_mid = + (const struct nsos_mid_sockaddr_in *)addr_mid; + struct sockaddr_in *addr_in = (struct sockaddr_in *)*addr; + + addr_in->sin_family = AF_INET; + addr_in->sin_port = addr_in_mid->sin_port; + addr_in->sin_addr.s_addr = addr_in_mid->sin_addr; + + *addrlen = sizeof(*addr_in); + + return 0; + } + } + + return -NSOS_MID_EINVAL; +} + +static int sockaddr_to_nsos_mid(const struct sockaddr *addr, socklen_t addrlen, + struct nsos_mid_sockaddr *addr_mid, size_t *addrlen_mid) +{ + if (!addr || addrlen == 0) { + *addrlen_mid = 0; + + return 0; + } + + switch (addr->sa_family) { + case AF_INET: { + struct nsos_mid_sockaddr_in *addr_in_mid = + (struct nsos_mid_sockaddr_in *)addr_mid; + const struct sockaddr_in *addr_in = (const struct sockaddr_in *)addr; + + if (addr_in_mid) { + addr_in_mid->sin_family = NSOS_MID_AF_INET; + addr_in_mid->sin_port = addr_in->sin_port; + addr_in_mid->sin_addr = addr_in->sin_addr.s_addr; + } + + if (addrlen_mid) { + *addrlen_mid = sizeof(*addr_in); + } + + return 0; + } + } + + nsi_print_warning("%s: socket family %d not supported\n", __func__, addr->sa_family); + + return -NSOS_MID_EINVAL; +} + +int nsos_adapt_bind(int fd, const struct nsos_mid_sockaddr *addr_mid, size_t addrlen_mid) +{ + struct sockaddr_storage addr_storage; + struct sockaddr *addr = (struct sockaddr *)&addr_storage; + socklen_t addrlen; + int ret; + + ret = sockaddr_from_nsos_mid(&addr, &addrlen, addr_mid, addrlen_mid); + if (ret < 0) { + return ret; + } + + ret = bind(fd, addr, addrlen); + if (ret < 0) { + return -errno_to_nsos_mid(errno); + } + + return ret; +} + +int nsos_adapt_connect(int fd, const struct nsos_mid_sockaddr *addr_mid, size_t addrlen_mid) +{ + struct sockaddr_storage addr_storage; + struct sockaddr *addr = (struct sockaddr *)&addr_storage; + socklen_t addrlen; + int ret; + + ret = sockaddr_from_nsos_mid(&addr, &addrlen, addr_mid, addrlen_mid); + if (ret < 0) { + return ret; + } + + ret = connect(fd, addr, addrlen); + if (ret < 0) { + return -errno_to_nsos_mid(errno); + } + + return ret; +} + +int nsos_adapt_listen(int fd, int backlog) +{ + int ret; + + ret = listen(fd, backlog); + if (ret < 0) { + return -errno_to_nsos_mid(errno); + } + + return ret; +} + +int nsos_adapt_accept(int fd, struct nsos_mid_sockaddr *addr_mid, size_t *addrlen_mid) +{ + struct sockaddr_storage addr_storage; + struct sockaddr *addr = (struct sockaddr *)&addr_storage; + socklen_t addrlen = sizeof(addr_storage); + int ret; + int err; + + ret = accept(fd, addr, &addrlen); + if (ret < 0) { + return -errno_to_nsos_mid(errno); + } + + err = sockaddr_to_nsos_mid(addr, addrlen, addr_mid, addrlen_mid); + if (err) { + return err; + } + + return ret; +} + +int nsos_adapt_sendto(int fd, const void *buf, size_t len, int flags, + const struct nsos_mid_sockaddr *addr_mid, size_t addrlen_mid) +{ + struct sockaddr_storage addr_storage; + struct sockaddr *addr = (struct sockaddr *)&addr_storage; + socklen_t addrlen; + int ret; + + ret = sockaddr_from_nsos_mid(&addr, &addrlen, addr_mid, addrlen_mid); + if (ret < 0) { + return ret; + } + + ret = sendto(fd, buf, len, + socket_flags_from_nsos_mid(flags) | MSG_NOSIGNAL, + addr, addrlen); + if (ret < 0) { + return -errno_to_nsos_mid(errno); + } + + return ret; +} + +int nsos_adapt_recvfrom(int fd, void *buf, size_t len, int flags, + struct nsos_mid_sockaddr *addr_mid, size_t *addrlen_mid) +{ + struct sockaddr_storage addr_storage; + struct sockaddr *addr = (struct sockaddr *)&addr_storage; + socklen_t addrlen = sizeof(addr_storage); + int ret; + int err; + + ret = recvfrom(fd, buf, len, socket_flags_from_nsos_mid(flags), + addr, &addrlen); + if (ret < 0) { + return -errno_to_nsos_mid(errno); + } + + err = sockaddr_to_nsos_mid(addr, addrlen, addr_mid, addrlen_mid); + if (err) { + return err; + } + + return ret; +} diff --git a/drivers/net/nsos_errno.c b/drivers/net/nsos_errno.c new file mode 100644 index 00000000000..417c1af4f06 --- /dev/null +++ b/drivers/net/nsos_errno.c @@ -0,0 +1,125 @@ +/** + * Copyright (c) 2023-2024 Marcin Niestroj + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nsos_errno.h" + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0])) +#endif + +struct nsos_mid_errno_map { + /** Zephyr/host error code */ + int err; + /** NSOS middleground error code */ + int mid_err; +}; + +#define ERR(_name) \ + { _name, NSOS_MID_ ## _name } + +static const struct nsos_mid_errno_map map[] = { + ERR(EPERM), + ERR(ENOENT), + ERR(ESRCH), + ERR(EINTR), + ERR(EIO), + ERR(ENXIO), + ERR(E2BIG), + ERR(ENOEXEC), + ERR(EBADF), + ERR(ECHILD), + ERR(EAGAIN), + ERR(ENOMEM), + ERR(EACCES), + ERR(EFAULT), + ERR(ENOTBLK), + ERR(EBUSY), + ERR(EEXIST), + ERR(EXDEV), + ERR(ENODEV), + ERR(ENOTDIR), + ERR(EISDIR), + ERR(EINVAL), + ERR(ENFILE), + ERR(EMFILE), + ERR(ENOTTY), + ERR(ETXTBSY), + ERR(EFBIG), + ERR(ENOSPC), + ERR(ESPIPE), + ERR(EROFS), + ERR(EMLINK), + ERR(EPIPE), + ERR(EDOM), + ERR(ERANGE), + ERR(ENOMSG), + ERR(EDEADLK), + ERR(ENOLCK), + ERR(ENOSTR), + ERR(ENODATA), + ERR(ETIME), + ERR(ENOSR), + ERR(EPROTO), + ERR(EBADMSG), + ERR(ENOSYS), + ERR(ENOTEMPTY), + ERR(ENAMETOOLONG), + ERR(ELOOP), + ERR(EOPNOTSUPP), + ERR(EPFNOSUPPORT), + ERR(ECONNRESET), + ERR(ENOBUFS), + ERR(EAFNOSUPPORT), + ERR(EPROTOTYPE), + ERR(ENOTSOCK), + ERR(ENOPROTOOPT), + ERR(ESHUTDOWN), + ERR(ECONNREFUSED), + ERR(EADDRINUSE), + ERR(ECONNABORTED), + ERR(ENETUNREACH), + ERR(ENETDOWN), + ERR(ETIMEDOUT), + ERR(EHOSTDOWN), + ERR(EHOSTUNREACH), + ERR(EINPROGRESS), + ERR(EALREADY), + ERR(EDESTADDRREQ), + ERR(EMSGSIZE), + ERR(EPROTONOSUPPORT), + ERR(ESOCKTNOSUPPORT), + ERR(EADDRNOTAVAIL), + ERR(ENETRESET), + ERR(EISCONN), + ERR(ENOTCONN), + ERR(ETOOMANYREFS), + ERR(ENOTSUP), + ERR(EILSEQ), + ERR(EOVERFLOW), + ERR(ECANCELED), +}; + +int errno_to_nsos_mid(int err) +{ + for (int i = 0; i < ARRAY_SIZE(map); i++) { + if (map[i].err == err) { + return map[i].mid_err; + } + } + + return err; +} + +int errno_from_nsos_mid(int err) +{ + for (int i = 0; i < ARRAY_SIZE(map); i++) { + if (map[i].mid_err == err) { + return map[i].err; + } + } + + return err; +} diff --git a/drivers/net/nsos_errno.h b/drivers/net/nsos_errno.h new file mode 100644 index 00000000000..8e9b6214671 --- /dev/null +++ b/drivers/net/nsos_errno.h @@ -0,0 +1,95 @@ +/** + * Copyright (c) 2023-2024 Marcin Niestroj + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRIVERS_NET_NSOS_ERRNO_H__ +#define __DRIVERS_NET_NSOS_ERRNO_H__ + +#include + +#define NSOS_MID_EPERM 1 /**< Not owner */ +#define NSOS_MID_ENOENT 2 /**< No such file or directory */ +#define NSOS_MID_ESRCH 3 /**< No such context */ +#define NSOS_MID_EINTR 4 /**< Interrupted system call */ +#define NSOS_MID_EIO 5 /**< I/O error */ +#define NSOS_MID_ENXIO 6 /**< No such device or address */ +#define NSOS_MID_E2BIG 7 /**< Arg list too long */ +#define NSOS_MID_ENOEXEC 8 /**< Exec format error */ +#define NSOS_MID_EBADF 9 /**< Bad file number */ +#define NSOS_MID_ECHILD 10 /**< No children */ +#define NSOS_MID_EAGAIN 11 /**< No more contexts */ +#define NSOS_MID_ENOMEM 12 /**< Not enough core */ +#define NSOS_MID_EACCES 13 /**< Permission denied */ +#define NSOS_MID_EFAULT 14 /**< Bad address */ +#define NSOS_MID_ENOTBLK 15 /**< Block device required */ +#define NSOS_MID_EBUSY 16 /**< Mount device busy */ +#define NSOS_MID_EEXIST 17 /**< File exists */ +#define NSOS_MID_EXDEV 18 /**< Cross-device link */ +#define NSOS_MID_ENODEV 19 /**< No such device */ +#define NSOS_MID_ENOTDIR 20 /**< Not a directory */ +#define NSOS_MID_EISDIR 21 /**< Is a directory */ +#define NSOS_MID_EINVAL 22 /**< Invalid argument */ +#define NSOS_MID_ENFILE 23 /**< File table overflow */ +#define NSOS_MID_EMFILE 24 /**< Too many open files */ +#define NSOS_MID_ENOTTY 25 /**< Not a typewriter */ +#define NSOS_MID_ETXTBSY 26 /**< Text file busy */ +#define NSOS_MID_EFBIG 27 /**< File too large */ +#define NSOS_MID_ENOSPC 28 /**< No space left on device */ +#define NSOS_MID_ESPIPE 29 /**< Illegal seek */ +#define NSOS_MID_EROFS 30 /**< Read-only file system */ +#define NSOS_MID_EMLINK 31 /**< Too many links */ +#define NSOS_MID_EPIPE 32 /**< Broken pipe */ +#define NSOS_MID_EDOM 33 /**< Argument too large */ +#define NSOS_MID_ERANGE 34 /**< Result too large */ +#define NSOS_MID_ENOMSG 35 /**< Unexpected message type */ +#define NSOS_MID_EDEADLK 45 /**< Resource deadlock avoided */ +#define NSOS_MID_ENOLCK 46 /**< No locks available */ +#define NSOS_MID_ENOSTR 60 /**< STREAMS device required */ +#define NSOS_MID_ENODATA 61 /**< Missing expected message data */ +#define NSOS_MID_ETIME 62 /**< STREAMS timeout occurred */ +#define NSOS_MID_ENOSR 63 /**< Insufficient memory */ +#define NSOS_MID_EPROTO 71 /**< Generic STREAMS error */ +#define NSOS_MID_EBADMSG 77 /**< Invalid STREAMS message */ +#define NSOS_MID_ENOSYS 88 /**< Function not implemented */ +#define NSOS_MID_ENOTEMPTY 90 /**< Directory not empty */ +#define NSOS_MID_ENAMETOOLONG 91 /**< File name too long */ +#define NSOS_MID_ELOOP 92 /**< Too many levels of symbolic links */ +#define NSOS_MID_EOPNOTSUPP 95 /**< Operation not supported on socket */ +#define NSOS_MID_EPFNOSUPPORT 96 /**< Protocol family not supported */ +#define NSOS_MID_ECONNRESET 104 /**< Connection reset by peer */ +#define NSOS_MID_ENOBUFS 105 /**< No buffer space available */ +#define NSOS_MID_EAFNOSUPPORT 106 /**< Addr family not supported */ +#define NSOS_MID_EPROTOTYPE 107 /**< Protocol wrong type for socket */ +#define NSOS_MID_ENOTSOCK 108 /**< Socket operation on non-socket */ +#define NSOS_MID_ENOPROTOOPT 109 /**< Protocol not available */ +#define NSOS_MID_ESHUTDOWN 110 /**< Can't send after socket shutdown */ +#define NSOS_MID_ECONNREFUSED 111 /**< Connection refused */ +#define NSOS_MID_EADDRINUSE 112 /**< Address already in use */ +#define NSOS_MID_ECONNABORTED 113 /**< Software caused connection abort */ +#define NSOS_MID_ENETUNREACH 114 /**< Network is unreachable */ +#define NSOS_MID_ENETDOWN 115 /**< Network is down */ +#define NSOS_MID_ETIMEDOUT 116 /**< Connection timed out */ +#define NSOS_MID_EHOSTDOWN 117 /**< Host is down */ +#define NSOS_MID_EHOSTUNREACH 118 /**< No route to host */ +#define NSOS_MID_EINPROGRESS 119 /**< Operation now in progress */ +#define NSOS_MID_EALREADY 120 /**< Operation already in progress */ +#define NSOS_MID_EDESTADDRREQ 121 /**< Destination address required */ +#define NSOS_MID_EMSGSIZE 122 /**< Message size */ +#define NSOS_MID_EPROTONOSUPPORT 123 /**< Protocol not supported */ +#define NSOS_MID_ESOCKTNOSUPPORT 124 /**< Socket type not supported */ +#define NSOS_MID_EADDRNOTAVAIL 125 /**< Can't assign requested address */ +#define NSOS_MID_ENETRESET 126 /**< Network dropped connection on reset */ +#define NSOS_MID_EISCONN 127 /**< Socket is already connected */ +#define NSOS_MID_ENOTCONN 128 /**< Socket is not connected */ +#define NSOS_MID_ETOOMANYREFS 129 /**< Too many references: can't splice */ +#define NSOS_MID_ENOTSUP 134 /**< Unsupported value */ +#define NSOS_MID_EILSEQ 138 /**< Illegal byte sequence */ +#define NSOS_MID_EOVERFLOW 139 /**< Value overflow */ +#define NSOS_MID_ECANCELED 140 /**< Operation canceled */ + +int errno_to_nsos_mid(int err); +int errno_from_nsos_mid(int err); + +#endif /* __DRIVERS_NET_NSOS_ERRNO_H__ */ diff --git a/drivers/net/nsos_sockets.c b/drivers/net/nsos_sockets.c new file mode 100644 index 00000000000..4d3ea153ba1 --- /dev/null +++ b/drivers/net/nsos_sockets.c @@ -0,0 +1,532 @@ +/** + * Copyright (c) 2023-2024 Marcin Niestroj + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * + * Zephyr (top) side of NSOS (Native Simulator Offloaded Sockets). + */ + +#include +#include +#include +#include +#include + +#include "sockets_internal.h" +#include "nsos.h" +#include "nsos_errno.h" + +#include "nsi_host_trampolines.h" + +/* Increment by 1 to make sure we do not store the value of 0, which has + * a special meaning in the fdtable subsys. + */ +#define FD_TO_OBJ(fd) ((void *)(intptr_t)((fd) + 1)) +#define OBJ_TO_FD(obj) (((int)(intptr_t)(obj)) - 1) + +static int socket_family_to_nsos_mid(int family, int *family_mid) +{ + switch (family) { + case AF_UNSPEC: + *family_mid = NSOS_MID_AF_UNSPEC; + break; + case AF_INET: + *family_mid = NSOS_MID_AF_INET; + break; + default: + return -NSOS_MID_EAFNOSUPPORT; + } + + return 0; +} + +static int socket_proto_to_nsos_mid(int proto, int *proto_mid) +{ + switch (proto) { + case IPPROTO_IP: + *proto_mid = NSOS_MID_IPPROTO_IP; + break; + case IPPROTO_ICMP: + *proto_mid = NSOS_MID_IPPROTO_ICMP; + break; + case IPPROTO_IGMP: + *proto_mid = NSOS_MID_IPPROTO_IGMP; + break; + case IPPROTO_IPIP: + *proto_mid = NSOS_MID_IPPROTO_IPIP; + break; + case IPPROTO_TCP: + *proto_mid = NSOS_MID_IPPROTO_TCP; + break; + case IPPROTO_UDP: + *proto_mid = NSOS_MID_IPPROTO_UDP; + break; + case IPPROTO_IPV6: + *proto_mid = NSOS_MID_IPPROTO_IPV6; + break; + case IPPROTO_RAW: + *proto_mid = NSOS_MID_IPPROTO_RAW; + break; + default: + return -NSOS_MID_EPROTONOSUPPORT; + } + + return 0; +} + +static int socket_type_to_nsos_mid(int type, int *type_mid) +{ + switch (type) { + case SOCK_STREAM: + *type_mid = NSOS_MID_SOCK_STREAM; + break; + case SOCK_DGRAM: + *type_mid = NSOS_MID_SOCK_DGRAM; + break; + case SOCK_RAW: + *type_mid = NSOS_MID_SOCK_RAW; + break; + default: + return -NSOS_MID_ESOCKTNOSUPPORT; + } + + return 0; +} + +static int socket_flags_to_nsos_mid(int flags) +{ + int flags_mid = 0; + + nsos_socket_flag_convert(&flags, ZSOCK_MSG_PEEK, + &flags_mid, NSOS_MID_MSG_PEEK); + nsos_socket_flag_convert(&flags, ZSOCK_MSG_TRUNC, + &flags_mid, NSOS_MID_MSG_TRUNC); + nsos_socket_flag_convert(&flags, ZSOCK_MSG_DONTWAIT, + &flags_mid, NSOS_MID_MSG_DONTWAIT); + nsos_socket_flag_convert(&flags, ZSOCK_MSG_WAITALL, + &flags_mid, NSOS_MID_MSG_WAITALL); + + if (flags != 0) { + return -NSOS_MID_EINVAL; + } + + return flags_mid; +} + +static const struct socket_op_vtable nsos_socket_fd_op_vtable; + +static int nsos_socket_create(int family, int type, int proto) +{ + int fd; + int sock; + int family_mid; + int type_mid; + int proto_mid; + int err; + + err = socket_family_to_nsos_mid(family, &family_mid); + if (err) { + errno = errno_from_nsos_mid(-err); + return -1; + } + + err = socket_type_to_nsos_mid(type, &type_mid); + if (err) { + errno = errno_from_nsos_mid(-err); + return -1; + } + + err = socket_proto_to_nsos_mid(proto, &proto_mid); + if (err) { + errno = errno_from_nsos_mid(-err); + return -1; + } + + fd = z_reserve_fd(); + if (fd < 0) { + return -1; + } + + sock = nsos_adapt_socket(family_mid, type_mid, proto_mid); + if (sock < 0) { + errno = errno_from_nsos_mid(-sock); + goto free_fd; + } + + z_finalize_fd(fd, FD_TO_OBJ(sock), &nsos_socket_fd_op_vtable.fd_vtable); + + return fd; + +free_fd: + z_free_fd(fd); + + return -1; +} + +static int nsos_adapt_get_zephyr_errno(void) +{ + return errno_from_nsos_mid(nsos_adapt_get_errno()); +} + +static ssize_t nsos_read(void *obj, void *buf, size_t sz) +{ + int ret; + + ret = nsi_host_read(OBJ_TO_FD(obj), buf, sz); + if (ret < 0) { + errno = nsos_adapt_get_zephyr_errno(); + } + + return ret; +} + +static ssize_t nsos_write(void *obj, const void *buf, size_t sz) +{ + int ret; + + ret = nsi_host_write(OBJ_TO_FD(obj), buf, sz); + if (ret < 0) { + errno = nsos_adapt_get_zephyr_errno(); + } + + return ret; +} + +static int nsos_close(void *obj) +{ + int ret; + + ret = nsi_host_close(OBJ_TO_FD(obj)); + if (ret < 0) { + errno = nsos_adapt_get_zephyr_errno(); + } + + return ret; +} + +static int nsos_ioctl(void *obj, unsigned int request, va_list args) +{ + switch (request) { + case ZFD_IOCTL_POLL_PREPARE: + return -EXDEV; + + case ZFD_IOCTL_POLL_UPDATE: + return -EOPNOTSUPP; + + case ZFD_IOCTL_POLL_OFFLOAD: + return -EOPNOTSUPP; + } + + return -EINVAL; +} + +static int sockaddr_to_nsos_mid(const struct sockaddr *addr, socklen_t *addrlen, + struct nsos_mid_sockaddr **addr_mid, size_t *addrlen_mid) +{ + if (!addr || !addrlen) { + *addr_mid = NULL; + *addrlen_mid = 0; + + return 0; + } + + switch (addr->sa_family) { + case AF_INET: { + const struct sockaddr_in *addr_in = + (const struct sockaddr_in *)addr; + struct nsos_mid_sockaddr_in *addr_in_mid = + (struct nsos_mid_sockaddr_in *)*addr_mid; + + if (*addrlen < sizeof(*addr_in)) { + return -NSOS_MID_EINVAL; + } + + addr_in_mid->sin_family = NSOS_MID_AF_INET; + addr_in_mid->sin_port = addr_in->sin_port; + addr_in_mid->sin_addr = addr_in->sin_addr.s_addr; + + *addrlen_mid = sizeof(*addr_in_mid); + + return 0; + } + } + + return -NSOS_MID_EINVAL; +} + +static int sockaddr_from_nsos_mid(struct sockaddr *addr, socklen_t *addrlen, + const struct nsos_mid_sockaddr *addr_mid, size_t addrlen_mid) +{ + if (!addr || !addrlen) { + return 0; + } + + switch (addr_mid->sa_family) { + case NSOS_MID_AF_INET: { + const struct nsos_mid_sockaddr_in *addr_in_mid = + (const struct nsos_mid_sockaddr_in *)addr_mid; + struct sockaddr_in addr_in; + + addr_in.sin_family = AF_INET; + addr_in.sin_port = addr_in_mid->sin_port; + addr_in.sin_addr.s_addr = addr_in_mid->sin_addr; + + memcpy(addr, &addr_in, MIN(*addrlen, sizeof(addr_in))); + *addrlen = sizeof(addr_in); + + return 0; + } + } + + return -NSOS_MID_EINVAL; +} + +static int nsos_bind(void *obj, const struct sockaddr *addr, socklen_t addrlen) +{ + struct nsos_mid_sockaddr_storage addr_storage_mid; + struct nsos_mid_sockaddr *addr_mid = (struct nsos_mid_sockaddr *)&addr_storage_mid; + size_t addrlen_mid; + int ret; + + ret = sockaddr_to_nsos_mid(addr, &addrlen, &addr_mid, &addrlen_mid); + if (ret < 0) { + goto return_ret; + } + + ret = nsos_adapt_bind(OBJ_TO_FD(obj), addr_mid, addrlen_mid); + +return_ret: + if (ret < 0) { + errno = errno_from_nsos_mid(-ret); + return -1; + } + + return ret; +} + +static int nsos_connect(void *obj, const struct sockaddr *addr, socklen_t addrlen) +{ + struct nsos_mid_sockaddr_storage addr_storage_mid; + struct nsos_mid_sockaddr *addr_mid = (struct nsos_mid_sockaddr *)&addr_storage_mid; + size_t addrlen_mid; + int ret; + + ret = sockaddr_to_nsos_mid(addr, &addrlen, &addr_mid, &addrlen_mid); + if (ret < 0) { + goto return_ret; + } + + ret = nsos_adapt_connect(OBJ_TO_FD(obj), addr_mid, addrlen_mid); + +return_ret: + if (ret < 0) { + errno = errno_from_nsos_mid(-ret); + return -1; + } + + return ret; +} + +static int nsos_listen(void *obj, int backlog) +{ + int ret; + + ret = nsos_adapt_listen(OBJ_TO_FD(obj), backlog); + if (ret < 0) { + errno = errno_from_nsos_mid(-ret); + return -1; + } + + return ret; +} + +static int nsos_accept(void *obj, struct sockaddr *addr, socklen_t *addrlen) +{ + struct nsos_mid_sockaddr_storage addr_storage_mid; + struct nsos_mid_sockaddr *addr_mid = (struct nsos_mid_sockaddr *)&addr_storage_mid; + size_t addrlen_mid = sizeof(addr_storage_mid); + int ret; + + ret = nsos_adapt_accept(OBJ_TO_FD(obj), addr_mid, &addrlen_mid); + if (ret < 0) { + errno = errno_from_nsos_mid(-ret); + return -1; + } + + adapt_fd = ret; + + ret = sockaddr_from_nsos_mid(addr, addrlen, addr_mid, addrlen_mid); + if (ret < 0) { + errno = errno_from_nsos_mid(-ret); + goto close_adapt_fd; + } + + zephyr_fd = z_reserve_fd(); + if (zephyr_fd < 0) { + goto close_adapt_fd; + } + + z_finalize_fd(zephyr_fd, FD_TO_OBJ(adapt_fd), &nsos_socket_fd_op_vtable.fd_vtable); + + return zephyr_fd; + +close_adapt_fd: + nsi_host_close(adapt_fd); + + return -1; +} + +static ssize_t nsos_sendto(void *obj, const void *buf, size_t len, int flags, + const struct sockaddr *addr, socklen_t addrlen) +{ + struct nsos_mid_sockaddr_storage addr_storage_mid; + struct nsos_mid_sockaddr *addr_mid = (struct nsos_mid_sockaddr *)&addr_storage_mid; + size_t addrlen_mid = sizeof(addr_storage_mid); + int flags_mid; + int ret; + + ret = socket_flags_to_nsos_mid(flags); + if (ret < 0) { + goto return_ret; + } + + flags_mid = ret; + + ret = sockaddr_to_nsos_mid(addr, &addrlen, &addr_mid, &addrlen_mid); + if (ret < 0) { + goto return_ret; + } + + ret = nsos_adapt_sendto(OBJ_TO_FD(obj), buf, len, flags_mid, + addr_mid, addrlen_mid); + +return_ret: + if (ret < 0) { + errno = errno_from_nsos_mid(-ret); + return -1; + } + + return ret; +} + +static ssize_t nsos_sendmsg(void *obj, const struct msghdr *msg, int flags) +{ + errno = ENOTSUP; + return -1; +} + +static ssize_t nsos_recvfrom(void *obj, void *buf, size_t len, int flags, + struct sockaddr *addr, socklen_t *addrlen) +{ + struct nsos_mid_sockaddr_storage addr_storage_mid; + struct nsos_mid_sockaddr *addr_mid = (struct nsos_mid_sockaddr *)&addr_storage_mid; + size_t addrlen_mid = sizeof(addr_storage_mid); + int flags_mid; + int ret; + + ret = socket_flags_to_nsos_mid(flags); + if (ret < 0) { + goto return_ret; + } + + flags_mid = ret; + + ret = nsos_adapt_recvfrom(OBJ_TO_FD(obj), buf, len, flags_mid, + addr_mid, &addrlen_mid); + if (ret < 0) { + goto return_ret; + } + + sockaddr_from_nsos_mid(addr, addrlen, addr_mid, addrlen_mid); + +return_ret: + if (ret < 0) { + errno = errno_from_nsos_mid(-ret); + return -1; + } + + return ret; +} + +static ssize_t nsos_recvmsg(void *obj, struct msghdr *msg, int flags) +{ + errno = ENOTSUP; + return -1; +} + +static const struct socket_op_vtable nsos_socket_fd_op_vtable = { + .fd_vtable = { + .read = nsos_read, + .write = nsos_write, + .close = nsos_close, + .ioctl = nsos_ioctl, + }, + .bind = nsos_bind, + .connect = nsos_connect, + .listen = nsos_listen, + .accept = nsos_accept, + .sendto = nsos_sendto, + .sendmsg = nsos_sendmsg, + .recvfrom = nsos_recvfrom, + .recvmsg = nsos_recvmsg, +}; + +static bool nsos_is_supported(int family, int type, int proto) +{ + int dummy; + int err; + + err = socket_family_to_nsos_mid(family, &dummy); + if (err) { + return false; + } + + err = socket_type_to_nsos_mid(type, &dummy); + if (err) { + return false; + } + + err = socket_proto_to_nsos_mid(proto, &dummy); + if (err) { + return false; + } + + return true; +} + +NET_SOCKET_OFFLOAD_REGISTER(nsos, CONFIG_NET_SOCKETS_OFFLOAD_PRIORITY, AF_UNSPEC, + nsos_is_supported, nsos_socket_create); + +static int nsos_socket_offload_init(const struct device *arg) +{ + ARG_UNUSED(arg); + + return 0; +} + +static void nsos_iface_api_init(struct net_if *iface) +{ + iface->if_dev->socket_offload = nsos_socket_create; +} + +static int nsos_iface_enable(const struct net_if *iface, bool enabled) +{ + ARG_UNUSED(iface); + ARG_UNUSED(enabled); + return 0; +} + +static struct offloaded_if_api nsos_iface_offload_api = { + .iface_api.init = nsos_iface_api_init, + .enable = nsos_iface_enable, +}; + +NET_DEVICE_OFFLOAD_INIT(nsos_socket, "nsos_socket", + nsos_socket_offload_init, + NULL, + NULL, NULL, + 0, &nsos_iface_offload_api, NET_ETH_MTU); From d1adffc123cad8035c84e688ddc2276bbdbed135 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Fri, 10 Nov 2023 22:07:10 +0100 Subject: [PATCH 1225/2402] drivers: net: nsos: add DNS offload support Extend driver to support DNS by offloading getaddrinfo() and freeaddrinfo() APIs. Signed-off-by: Marcin Niestroj --- drivers/net/CMakeLists.txt | 2 + drivers/net/nsos.h | 18 +++ drivers/net/nsos_adapt.c | 224 +++++++++++++++++++++++++++++++++++++ drivers/net/nsos_netdb.c | 73 ++++++++++++ drivers/net/nsos_netdb.h | 36 ++++++ drivers/net/nsos_sockets.c | 137 +++++++++++++++++++++++ 6 files changed, 490 insertions(+) create mode 100644 drivers/net/nsos_netdb.c create mode 100644 drivers/net/nsos_netdb.h diff --git a/drivers/net/CMakeLists.txt b/drivers/net/CMakeLists.txt index d839b9690c3..a9f9bb38293 100644 --- a/drivers/net/CMakeLists.txt +++ b/drivers/net/CMakeLists.txt @@ -15,7 +15,9 @@ if(CONFIG_NET_NATIVE_OFFLOADED_SOCKETS) ${ZEPHYR_BASE}/subsys/net/lib/sockets ) zephyr_library_sources(nsos_errno.c) + zephyr_library_sources(nsos_netdb.c) zephyr_library_sources(nsos_sockets.c) target_sources(native_simulator INTERFACE nsos_adapt.c) target_sources(native_simulator INTERFACE nsos_errno.c) + target_sources(native_simulator INTERFACE nsos_netdb.c) endif() diff --git a/drivers/net/nsos.h b/drivers/net/nsos.h index 13a6b8f8826..1c19fc99936 100644 --- a/drivers/net/nsos.h +++ b/drivers/net/nsos.h @@ -75,6 +75,17 @@ struct nsos_mid_pollfd { short revents; }; +struct nsos_mid_addrinfo { + int ai_flags; + int ai_family; + int ai_socktype; + int ai_protocol; + size_t ai_addrlen; + struct nsos_mid_sockaddr *ai_addr; + char *ai_canonname; + struct nsos_mid_addrinfo *ai_next; +}; + static inline void nsos_socket_flag_convert(int *flags_a, int flag_a, int *flags_b, int flag_b) { @@ -97,4 +108,11 @@ int nsos_adapt_sendto(int fd, const void *buf, size_t len, int flags, int nsos_adapt_recvfrom(int fd, void *buf, size_t len, int flags, struct nsos_mid_sockaddr *addr, size_t *addrlen); + +int nsos_adapt_getaddrinfo(const char *node, const char *service, + const struct nsos_mid_addrinfo *hints, + struct nsos_mid_addrinfo **res, + int *system_errno); +void nsos_adapt_freeaddrinfo(struct nsos_mid_addrinfo *res); + #endif /* __DRIVERS_NET_NSOS_H__ */ diff --git a/drivers/net/nsos_adapt.c b/drivers/net/nsos_adapt.c index 37dfe9b2368..348866fba78 100644 --- a/drivers/net/nsos_adapt.c +++ b/drivers/net/nsos_adapt.c @@ -11,18 +11,27 @@ */ #include +#include #include #include +#include +#include #include #include #include "nsos.h" #include "nsos_errno.h" +#include "nsos_netdb.h" #include "nsi_tracing.h" #include +#ifndef CONTAINER_OF +#define CONTAINER_OF(ptr, type, field) \ + ((type *)(((char *)(ptr)) - offsetof(type, field))) +#endif + int nsos_adapt_get_errno(void) { return errno_to_nsos_mid(errno); @@ -45,6 +54,23 @@ static int socket_family_from_nsos_mid(int family_mid, int *family) return 0; } +static int socket_family_to_nsos_mid(int family, int *family_mid) +{ + switch (family) { + case AF_UNSPEC: + *family_mid = NSOS_MID_AF_UNSPEC; + break; + case AF_INET: + *family_mid = NSOS_MID_AF_INET; + break; + default: + nsi_print_warning("%s: socket family %d not supported\n", __func__, family); + return -NSOS_MID_EAFNOSUPPORT; + } + + return 0; +} + static int socket_proto_from_nsos_mid(int proto_mid, int *proto) { switch (proto_mid) { @@ -80,6 +106,41 @@ static int socket_proto_from_nsos_mid(int proto_mid, int *proto) return 0; } +static int socket_proto_to_nsos_mid(int proto, int *proto_mid) +{ + switch (proto) { + case IPPROTO_IP: + *proto_mid = NSOS_MID_IPPROTO_IP; + break; + case IPPROTO_ICMP: + *proto_mid = NSOS_MID_IPPROTO_ICMP; + break; + case IPPROTO_IGMP: + *proto_mid = NSOS_MID_IPPROTO_IGMP; + break; + case IPPROTO_IPIP: + *proto_mid = NSOS_MID_IPPROTO_IPIP; + break; + case IPPROTO_TCP: + *proto_mid = NSOS_MID_IPPROTO_TCP; + break; + case IPPROTO_UDP: + *proto_mid = NSOS_MID_IPPROTO_UDP; + break; + case IPPROTO_IPV6: + *proto_mid = NSOS_MID_IPPROTO_IPV6; + break; + case IPPROTO_RAW: + *proto_mid = NSOS_MID_IPPROTO_RAW; + break; + default: + nsi_print_warning("%s: socket protocol %d not supported\n", __func__, proto); + return -NSOS_MID_EPROTONOSUPPORT; + } + + return 0; +} + static int socket_type_from_nsos_mid(int type_mid, int *type) { switch (type_mid) { @@ -100,6 +161,26 @@ static int socket_type_from_nsos_mid(int type_mid, int *type) return 0; } +static int socket_type_to_nsos_mid(int type, int *type_mid) +{ + switch (type) { + case SOCK_STREAM: + *type_mid = NSOS_MID_SOCK_STREAM; + break; + case SOCK_DGRAM: + *type_mid = NSOS_MID_SOCK_DGRAM; + break; + case SOCK_RAW: + *type_mid = NSOS_MID_SOCK_RAW; + break; + default: + nsi_print_warning("%s: socket type %d not supported\n", __func__, type); + return -NSOS_MID_ESOCKTNOSUPPORT; + } + + return 0; +} + static int socket_flags_from_nsos_mid(int flags_mid) { int flags = 0; @@ -331,3 +412,146 @@ int nsos_adapt_recvfrom(int fd, void *buf, size_t len, int flags, return ret; } + +struct nsos_addrinfo_wrap { + struct nsos_mid_addrinfo addrinfo_mid; + struct nsos_mid_sockaddr_storage addr_storage; + struct addrinfo *addrinfo; +}; + +static int addrinfo_to_nsos_mid(struct addrinfo *res, + struct nsos_mid_addrinfo **mid_res) +{ + struct nsos_addrinfo_wrap *nsos_res_wraps; + size_t idx_res = 0; + size_t n_res = 0; + int ret; + + for (struct addrinfo *res_p = res; res_p; res_p = res_p->ai_next) { + n_res++; + } + + if (n_res == 0) { + return 0; + } + + nsos_res_wraps = calloc(n_res, sizeof(*nsos_res_wraps)); + if (!nsos_res_wraps) { + return -NSOS_MID_ENOMEM; + } + + for (struct addrinfo *res_p = res; res_p; res_p = res_p->ai_next, idx_res++) { + struct nsos_addrinfo_wrap *wrap = &nsos_res_wraps[idx_res]; + + wrap->addrinfo = res_p; + + wrap->addrinfo_mid.ai_flags = res_p->ai_flags; + + ret = socket_family_to_nsos_mid(res_p->ai_family, &wrap->addrinfo_mid.ai_family); + if (ret < 0) { + goto free_wraps; + } + + ret = socket_type_to_nsos_mid(res_p->ai_socktype, &wrap->addrinfo_mid.ai_socktype); + if (ret < 0) { + goto free_wraps; + } + + ret = socket_proto_to_nsos_mid(res_p->ai_protocol, &wrap->addrinfo_mid.ai_protocol); + if (ret < 0) { + goto free_wraps; + } + + wrap->addrinfo_mid.ai_addr = + (struct nsos_mid_sockaddr *)&wrap->addr_storage; + wrap->addrinfo_mid.ai_addrlen = sizeof(wrap->addr_storage); + + ret = sockaddr_to_nsos_mid(res_p->ai_addr, res_p->ai_addrlen, + wrap->addrinfo_mid.ai_addr, + &wrap->addrinfo_mid.ai_addrlen); + if (ret < 0) { + goto free_wraps; + } + + wrap->addrinfo_mid.ai_canonname = + res_p->ai_canonname ? strdup(res_p->ai_canonname) : NULL; + wrap->addrinfo_mid.ai_next = &wrap[1].addrinfo_mid; + } + + nsos_res_wraps[n_res - 1].addrinfo_mid.ai_next = NULL; + + *mid_res = &nsos_res_wraps->addrinfo_mid; + + return 0; + +free_wraps: + for (struct nsos_mid_addrinfo *res_p = &nsos_res_wraps[0].addrinfo_mid; + res_p; + res_p = res_p->ai_next) { + free(res_p->ai_canonname); + } + + free(nsos_res_wraps); + + return ret; +} + +int nsos_adapt_getaddrinfo(const char *node, const char *service, + const struct nsos_mid_addrinfo *hints_mid, + struct nsos_mid_addrinfo **res_mid, + int *system_errno) +{ + struct addrinfo hints; + struct addrinfo *res = NULL; + int ret; + + if (hints_mid) { + hints.ai_flags = hints_mid->ai_flags; + + ret = socket_family_from_nsos_mid(hints_mid->ai_family, &hints.ai_family); + if (ret < 0) { + *system_errno = -ret; + return NSOS_MID_EAI_SYSTEM; + } + + ret = socket_type_from_nsos_mid(hints_mid->ai_socktype, &hints.ai_socktype); + if (ret < 0) { + *system_errno = -ret; + return NSOS_MID_EAI_SYSTEM; + } + + ret = socket_proto_from_nsos_mid(hints_mid->ai_protocol, &hints.ai_protocol); + if (ret < 0) { + *system_errno = -ret; + return NSOS_MID_EAI_SYSTEM; + } + } + + ret = getaddrinfo(node, service, + hints_mid ? &hints : NULL, + &res); + if (ret < 0) { + return ret; + } + + ret = addrinfo_to_nsos_mid(res, res_mid); + if (ret < 0) { + *system_errno = -ret; + return NSOS_MID_EAI_SYSTEM; + } + + return ret; +} + +void nsos_adapt_freeaddrinfo(struct nsos_mid_addrinfo *res_mid) +{ + struct nsos_addrinfo_wrap *wrap = + CONTAINER_OF(res_mid, struct nsos_addrinfo_wrap, addrinfo_mid); + + for (struct nsos_mid_addrinfo *res_p = res_mid; res_p; res_p = res_p->ai_next) { + free(res_p->ai_canonname); + } + + freeaddrinfo(wrap->addrinfo); + free(wrap); +} diff --git a/drivers/net/nsos_netdb.c b/drivers/net/nsos_netdb.c new file mode 100644 index 00000000000..60b8324dcb4 --- /dev/null +++ b/drivers/net/nsos_netdb.c @@ -0,0 +1,73 @@ +/** + * Copyright (c) 2023-2024 Marcin Niestroj + * + * SPDX-License-Identifier: Apache-2.0 + * + * netdb.h related code common to Zephyr (top: nsos_sockets.c) and Linux + * (bottom: nsos_adapt.c). + * + * It is needed by both sides to share the same macro definitions/values + * (prefixed with NSOS_MID_), which is not possible to achieve with two separate + * standard libc libraries, since they use different values for the same + * symbols. + */ + +#include "nsos_netdb.h" + +#ifdef __ZEPHYR__ + +#include +#define ERR(_name) \ + { DNS_ ## _name, NSOS_MID_ ## _name } + +#else + +#include +#define ERR(_name) \ + { _name, NSOS_MID_ ## _name } + +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0])) +#endif + +struct nsos_eai_map { + int err; + int mid_err; +}; + +static const struct nsos_eai_map map[] = { + ERR(EAI_BADFLAGS), + ERR(EAI_NONAME), + ERR(EAI_AGAIN), + ERR(EAI_FAIL), + ERR(EAI_FAMILY), + ERR(EAI_SOCKTYPE), + ERR(EAI_SERVICE), + ERR(EAI_MEMORY), + ERR(EAI_SYSTEM), + ERR(EAI_OVERFLOW), +}; + +int eai_to_nsos_mid(int err) +{ + for (int i = 0; i < ARRAY_SIZE(map); i++) { + if (map[i].err == err) { + return map[i].mid_err; + } + } + + return err; +} + +int eai_from_nsos_mid(int err) +{ + for (int i = 0; i < ARRAY_SIZE(map); i++) { + if (map[i].mid_err == err) { + return map[i].err; + } + } + + return err; +} diff --git a/drivers/net/nsos_netdb.h b/drivers/net/nsos_netdb.h new file mode 100644 index 00000000000..d15f2c08eb8 --- /dev/null +++ b/drivers/net/nsos_netdb.h @@ -0,0 +1,36 @@ +/** + * Copyright (c) 2023-2024 Marcin Niestroj + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRIVERS_NET_NSOS_NETDB_H__ +#define __DRIVERS_NET_NSOS_NETDB_H__ + +enum nsos_resolve_status { + /** Invalid value for `ai_flags' field */ + NSOS_MID_EAI_BADFLAGS = -1, + /** NAME or SERVICE is unknown */ + NSOS_MID_EAI_NONAME = -2, + /** Temporary failure in name resolution */ + NSOS_MID_EAI_AGAIN = -3, + /** Non-recoverable failure in name res */ + NSOS_MID_EAI_FAIL = -4, + /** `ai_family' not supported */ + NSOS_MID_EAI_FAMILY = -6, + /** `ai_socktype' not supported */ + NSOS_MID_EAI_SOCKTYPE = -7, + /** SRV not supported for `ai_socktype' */ + NSOS_MID_EAI_SERVICE = -8, + /** Memory allocation failure */ + NSOS_MID_EAI_MEMORY = -10, + /** System error returned in `errno' */ + NSOS_MID_EAI_SYSTEM = -11, + /** Argument buffer overflow */ + NSOS_MID_EAI_OVERFLOW = -12, +}; + +int eai_to_nsos_mid(int err); +int eai_from_nsos_mid(int err); + +#endif /* __DRIVERS_NET_NSOS_NETDB_H__ */ diff --git a/drivers/net/nsos_sockets.c b/drivers/net/nsos_sockets.c index 4d3ea153ba1..fd6c028314c 100644 --- a/drivers/net/nsos_sockets.c +++ b/drivers/net/nsos_sockets.c @@ -10,6 +10,10 @@ * Zephyr (top) side of NSOS (Native Simulator Offloaded Sockets). */ +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L + +#include #include #include #include @@ -19,6 +23,7 @@ #include "sockets_internal.h" #include "nsos.h" #include "nsos_errno.h" +#include "nsos_netdb.h" #include "nsi_host_trampolines.h" @@ -501,6 +506,136 @@ static bool nsos_is_supported(int family, int type, int proto) NET_SOCKET_OFFLOAD_REGISTER(nsos, CONFIG_NET_SOCKETS_OFFLOAD_PRIORITY, AF_UNSPEC, nsos_is_supported, nsos_socket_create); +struct zsock_addrinfo_wrap { + struct zsock_addrinfo addrinfo; + struct sockaddr_storage addr_storage; + struct nsos_mid_addrinfo *addrinfo_mid; +}; + +/* + * (Zephyr) + * zsock_addrinfo_wrap + * ----------------------- + * | zsock_addrinfo | + * ----------------------- (trampoline) + * | sockaddr_storage | nsos_addrinfo_wrap + * ----------------------- ----------------------------- + * | nsos_mid_addrinfo * | -> | nsos_mid_addrinfo | + * ----------------------- ----------------------------- + * | nsos_mid_sockaddr_storage | + * ----------------------------- (Linux host) + * | addrinfo * | -> addrinfo + * ----------------------------- + */ + +static int addrinfo_from_nsos_mid(struct nsos_mid_addrinfo *nsos_res, + struct zsock_addrinfo **res) +{ + struct zsock_addrinfo_wrap *res_wraps; + size_t idx_res = 0; + size_t n_res = 0; + + for (struct nsos_mid_addrinfo *res_p = nsos_res; res_p; res_p = res_p->ai_next) { + n_res++; + } + + if (n_res == 0) { + return 0; + } + + res_wraps = k_calloc(n_res, sizeof(*res_wraps)); + if (!res_wraps) { + return -ENOMEM; + } + + for (struct nsos_mid_addrinfo *res_p = nsos_res; res_p; res_p = res_p->ai_next, idx_res++) { + struct zsock_addrinfo_wrap *wrap = &res_wraps[idx_res]; + + wrap->addrinfo_mid = res_p; + + wrap->addrinfo.ai_flags = res_p->ai_flags; + wrap->addrinfo.ai_family = res_p->ai_family; + wrap->addrinfo.ai_socktype = res_p->ai_socktype; + wrap->addrinfo.ai_protocol = res_p->ai_protocol; + + wrap->addrinfo.ai_addr = + (struct sockaddr *)&wrap->addr_storage; + wrap->addrinfo.ai_addrlen = sizeof(wrap->addr_storage); + + sockaddr_from_nsos_mid(wrap->addrinfo.ai_addr, &wrap->addrinfo.ai_addrlen, + res_p->ai_addr, res_p->ai_addrlen); + + wrap->addrinfo.ai_canonname = + res_p->ai_canonname ? strdup(res_p->ai_canonname) : NULL; + wrap->addrinfo.ai_next = &wrap[1].addrinfo; + } + + res_wraps[n_res - 1].addrinfo.ai_next = NULL; + + *res = &res_wraps->addrinfo; + + return 0; +} + +static int nsos_getaddrinfo(const char *node, const char *service, + const struct zsock_addrinfo *hints, + struct zsock_addrinfo **res) +{ + struct nsos_mid_addrinfo hints_mid; + struct nsos_mid_addrinfo *res_mid; + int system_errno; + int ret; + + if (!res) { + return -EINVAL; + } + + if (hints) { + hints_mid.ai_flags = hints->ai_flags; + hints_mid.ai_family = hints->ai_family; + hints_mid.ai_socktype = hints->ai_socktype; + hints_mid.ai_protocol = hints->ai_protocol; + } + + ret = nsos_adapt_getaddrinfo(node, service, + hints ? &hints_mid : NULL, + &res_mid, + &system_errno); + if (ret < 0) { + if (ret == NSOS_MID_EAI_SYSTEM) { + errno = errno_from_nsos_mid(system_errno); + } + + return eai_from_nsos_mid(ret); + } + + ret = addrinfo_from_nsos_mid(res_mid, res); + if (ret < 0) { + errno = -ret; + return EAI_SYSTEM; + } + + return ret; +} + +static void nsos_freeaddrinfo(struct zsock_addrinfo *res) +{ + struct zsock_addrinfo_wrap *wrap = + CONTAINER_OF(res, struct zsock_addrinfo_wrap, addrinfo); + + for (struct zsock_addrinfo *res_p = res; res_p; res_p = res_p->ai_next) { + free(res_p->ai_canonname); + } + + nsos_adapt_freeaddrinfo(wrap->addrinfo_mid); + k_free(wrap); +} + +static const struct socket_dns_offload nsos_dns_ops = { + .getaddrinfo = nsos_getaddrinfo, + .freeaddrinfo = nsos_freeaddrinfo, +}; + static int nsos_socket_offload_init(const struct device *arg) { ARG_UNUSED(arg); @@ -511,6 +646,8 @@ static int nsos_socket_offload_init(const struct device *arg) static void nsos_iface_api_init(struct net_if *iface) { iface->if_dev->socket_offload = nsos_socket_create; + + socket_offload_dns_register(&nsos_dns_ops); } static int nsos_iface_enable(const struct net_if *iface, bool enabled) From 4317cd4576505f538a4cbd788d0f26cdbdaf7957 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Thu, 22 Feb 2024 15:01:18 +0100 Subject: [PATCH 1226/2402] drivers: net: nsos: add IPv6 support Add support for IPv6 socket offloading, next to existing IPv4 support. Signed-off-by: Marcin Niestroj --- drivers/net/nsos.h | 3 ++- drivers/net/nsos_adapt.c | 41 ++++++++++++++++++++++++++++++++++++++ drivers/net/nsos_sockets.c | 39 ++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/net/nsos.h b/drivers/net/nsos.h index 1c19fc99936..c36e54551ab 100644 --- a/drivers/net/nsos.h +++ b/drivers/net/nsos.h @@ -13,10 +13,12 @@ /* Protocol families. */ #define NSOS_MID_PF_UNSPEC 0 /**< Unspecified protocol family. */ #define NSOS_MID_PF_INET 1 /**< IP protocol family version 4. */ +#define NSOS_MID_PF_INET6 2 /**< IP protocol family version 6. */ /* Address families. */ #define NSOS_MID_AF_UNSPEC NSOS_MID_PF_UNSPEC /**< Unspecified address family. */ #define NSOS_MID_AF_INET NSOS_MID_PF_INET /**< IP protocol family version 4. */ +#define NSOS_MID_AF_INET6 NSOS_MID_PF_INET6 /**< IP protocol family version 6. */ /** Protocol numbers from IANA/BSD */ enum nsos_mid_net_ip_protocol { @@ -57,7 +59,6 @@ struct nsos_mid_sockaddr_in { struct nsos_mid_sockaddr_in6 { uint16_t sin6_family; /* AF_INET6 */ uint16_t sin6_port; /* Port number */ - uint32_t sin6_flowinfo; /* IPv6 flow info */ uint8_t sin6_addr[16]; uint32_t sin6_scope_id; /* Set of interfaces for a scope */ }; diff --git a/drivers/net/nsos_adapt.c b/drivers/net/nsos_adapt.c index 348866fba78..f526e6595c5 100644 --- a/drivers/net/nsos_adapt.c +++ b/drivers/net/nsos_adapt.c @@ -46,6 +46,9 @@ static int socket_family_from_nsos_mid(int family_mid, int *family) case NSOS_MID_AF_INET: *family = AF_INET; break; + case NSOS_MID_AF_INET6: + *family = AF_INET6; + break; default: nsi_print_warning("%s: socket family %d not supported\n", __func__, family_mid); return -NSOS_MID_EAFNOSUPPORT; @@ -63,6 +66,9 @@ static int socket_family_to_nsos_mid(int family, int *family_mid) case AF_INET: *family_mid = NSOS_MID_AF_INET; break; + case AF_INET6: + *family_mid = NSOS_MID_AF_INET6; + break; default: nsi_print_warning("%s: socket family %d not supported\n", __func__, family); return -NSOS_MID_EAFNOSUPPORT; @@ -255,6 +261,22 @@ static int sockaddr_from_nsos_mid(struct sockaddr **addr, socklen_t *addrlen, return 0; } + case NSOS_MID_AF_INET6: { + const struct nsos_mid_sockaddr_in6 *addr_in_mid = + (const struct nsos_mid_sockaddr_in6 *)addr_mid; + struct sockaddr_in6 *addr_in = (struct sockaddr_in6 *)*addr; + + addr_in->sin6_family = AF_INET6; + addr_in->sin6_port = addr_in_mid->sin6_port; + addr_in->sin6_flowinfo = 0; + memcpy(addr_in->sin6_addr.s6_addr, addr_in_mid->sin6_addr, + sizeof(addr_in->sin6_addr.s6_addr)); + addr_in->sin6_scope_id = addr_in_mid->sin6_scope_id; + + *addrlen = sizeof(*addr_in); + + return 0; + } } return -NSOS_MID_EINVAL; @@ -287,6 +309,25 @@ static int sockaddr_to_nsos_mid(const struct sockaddr *addr, socklen_t addrlen, return 0; } + case AF_INET6: { + struct nsos_mid_sockaddr_in6 *addr_in_mid = + (struct nsos_mid_sockaddr_in6 *)addr_mid; + const struct sockaddr_in6 *addr_in = (const struct sockaddr_in6 *)addr; + + if (addr_in_mid) { + addr_in_mid->sin6_family = NSOS_MID_AF_INET6; + addr_in_mid->sin6_port = addr_in->sin6_port; + memcpy(addr_in_mid->sin6_addr, addr_in->sin6_addr.s6_addr, + sizeof(addr_in_mid->sin6_addr)); + addr_in_mid->sin6_scope_id = addr_in->sin6_scope_id; + } + + if (addrlen_mid) { + *addrlen_mid = sizeof(*addr_in); + } + + return 0; + } } nsi_print_warning("%s: socket family %d not supported\n", __func__, addr->sa_family); diff --git a/drivers/net/nsos_sockets.c b/drivers/net/nsos_sockets.c index fd6c028314c..89257072bd6 100644 --- a/drivers/net/nsos_sockets.c +++ b/drivers/net/nsos_sockets.c @@ -42,6 +42,9 @@ static int socket_family_to_nsos_mid(int family, int *family_mid) case AF_INET: *family_mid = NSOS_MID_AF_INET; break; + case AF_INET6: + *family_mid = NSOS_MID_AF_INET6; + break; default: return -NSOS_MID_EAFNOSUPPORT; } @@ -258,6 +261,26 @@ static int sockaddr_to_nsos_mid(const struct sockaddr *addr, socklen_t *addrlen, return 0; } + case AF_INET6: { + const struct sockaddr_in6 *addr_in = + (const struct sockaddr_in6 *)addr; + struct nsos_mid_sockaddr_in6 *addr_in_mid = + (struct nsos_mid_sockaddr_in6 *)*addr_mid; + + if (*addrlen < sizeof(*addr_in)) { + return -NSOS_MID_EINVAL; + } + + addr_in_mid->sin6_family = NSOS_MID_AF_INET6; + addr_in_mid->sin6_port = addr_in->sin6_port; + memcpy(addr_in_mid->sin6_addr, addr_in->sin6_addr.s6_addr, + sizeof(addr_in_mid->sin6_addr)); + addr_in_mid->sin6_scope_id = addr_in->sin6_scope_id; + + *addrlen_mid = sizeof(*addr_in_mid); + + return 0; + } } return -NSOS_MID_EINVAL; @@ -285,6 +308,22 @@ static int sockaddr_from_nsos_mid(struct sockaddr *addr, socklen_t *addrlen, return 0; } + case NSOS_MID_AF_INET6: { + const struct nsos_mid_sockaddr_in6 *addr_in_mid = + (const struct nsos_mid_sockaddr_in6 *)addr_mid; + struct sockaddr_in6 addr_in; + + addr_in.sin6_family = AF_INET6; + addr_in.sin6_port = addr_in_mid->sin6_port; + memcpy(addr_in.sin6_addr.s6_addr, addr_in_mid->sin6_addr, + sizeof(addr_in.sin6_addr.s6_addr)); + addr_in.sin6_scope_id = addr_in_mid->sin6_scope_id; + + memcpy(addr, &addr_in, MIN(*addrlen, sizeof(addr_in))); + *addrlen = sizeof(addr_in); + + return 0; + } } return -NSOS_MID_EINVAL; From 483c41d2098d48c9fccdda5aa3d1d1dfa92e7379 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Thu, 22 Feb 2024 15:01:05 +0100 Subject: [PATCH 1227/2402] drivers: net: nsos: add F_GETFL and F_SETFL support This allows to use Zephyr TLS subsystem with Native Sim offloaded sockets. Signed-off-by: Marcin Niestroj --- drivers/net/CMakeLists.txt | 2 + drivers/net/nsos.h | 3 ++ drivers/net/nsos_adapt.c | 23 +++++++++++ drivers/net/nsos_fcntl.c | 84 ++++++++++++++++++++++++++++++++++++++ drivers/net/nsos_fcntl.h | 22 ++++++++++ drivers/net/nsos_sockets.c | 24 +++++++++++ 6 files changed, 158 insertions(+) create mode 100644 drivers/net/nsos_fcntl.c create mode 100644 drivers/net/nsos_fcntl.h diff --git a/drivers/net/CMakeLists.txt b/drivers/net/CMakeLists.txt index a9f9bb38293..8516d4472ef 100644 --- a/drivers/net/CMakeLists.txt +++ b/drivers/net/CMakeLists.txt @@ -15,9 +15,11 @@ if(CONFIG_NET_NATIVE_OFFLOADED_SOCKETS) ${ZEPHYR_BASE}/subsys/net/lib/sockets ) zephyr_library_sources(nsos_errno.c) + zephyr_library_sources(nsos_fcntl.c) zephyr_library_sources(nsos_netdb.c) zephyr_library_sources(nsos_sockets.c) target_sources(native_simulator INTERFACE nsos_adapt.c) target_sources(native_simulator INTERFACE nsos_errno.c) + target_sources(native_simulator INTERFACE nsos_fcntl.c) target_sources(native_simulator INTERFACE nsos_netdb.c) endif() diff --git a/drivers/net/nsos.h b/drivers/net/nsos.h index c36e54551ab..d9ac86c910a 100644 --- a/drivers/net/nsos.h +++ b/drivers/net/nsos.h @@ -110,6 +110,9 @@ int nsos_adapt_recvfrom(int fd, void *buf, size_t len, int flags, struct nsos_mid_sockaddr *addr, size_t *addrlen); +int nsos_adapt_fcntl_getfl(int fd); +int nsos_adapt_fcntl_setfl(int fd, int flags); + int nsos_adapt_getaddrinfo(const char *node, const char *service, const struct nsos_mid_addrinfo *hints, struct nsos_mid_addrinfo **res, diff --git a/drivers/net/nsos_adapt.c b/drivers/net/nsos_adapt.c index f526e6595c5..fe7f9ba47ac 100644 --- a/drivers/net/nsos_adapt.c +++ b/drivers/net/nsos_adapt.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -21,6 +22,7 @@ #include "nsos.h" #include "nsos_errno.h" +#include "nsos_fcntl.h" #include "nsos_netdb.h" #include "nsi_tracing.h" @@ -596,3 +598,24 @@ void nsos_adapt_freeaddrinfo(struct nsos_mid_addrinfo *res_mid) freeaddrinfo(wrap->addrinfo); free(wrap); } + +int nsos_adapt_fcntl_getfl(int fd) +{ + int flags; + + flags = fcntl(fd, F_GETFL); + + return fl_to_nsos_mid(flags); +} + +int nsos_adapt_fcntl_setfl(int fd, int flags) +{ + int ret; + + ret = fcntl(fd, F_SETFL, fl_from_nsos_mid(flags)); + if (ret < 0) { + return -errno_to_nsos_mid(errno); + } + + return 0; +} diff --git a/drivers/net/nsos_fcntl.c b/drivers/net/nsos_fcntl.c new file mode 100644 index 00000000000..be49d3ec63e --- /dev/null +++ b/drivers/net/nsos_fcntl.c @@ -0,0 +1,84 @@ +/** + * Copyright (c) 2023-2024 Marcin Niestroj + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * + * fcntl.h related code common to Zephyr (top: nsos_sockets.c) and Linux + * (bottom: nsos_adapt.c). + * + * It is needed by both sides to share the same macro definitions/values + * (prefixed with NSOS_MID_), which is not possible to achieve with two separate + * standard libc libraries, since they use different values for the same + * symbols. + */ + +#include + +#include "nsos_errno.h" +#include "nsos_fcntl.h" + +#include + +static int fl_to_nsos_mid_(int flags, bool strict) +{ + int flags_mid = 0; + +#define TO_NSOS_MID(_flag) \ + if (flags & (_flag)) { \ + flags &= ~(_flag); \ + flags_mid |= NSOS_MID_ ## _flag; \ + } + + TO_NSOS_MID(O_RDONLY); + TO_NSOS_MID(O_WRONLY); + TO_NSOS_MID(O_RDWR); + + TO_NSOS_MID(O_APPEND); + TO_NSOS_MID(O_EXCL); + TO_NSOS_MID(O_NONBLOCK); + +#undef TO_NSOS_MID + + if (strict && flags != 0) { + return -NSOS_MID_EINVAL; + } + + return flags_mid; +} + +int fl_to_nsos_mid(int flags) +{ + return fl_to_nsos_mid_(flags, false); +} + +int fl_to_nsos_mid_strict(int flags) +{ + return fl_to_nsos_mid_(flags, true); +} + +int fl_from_nsos_mid(int flags_mid) +{ + int flags = 0; + +#define FROM_NSOS_MID(_flag) \ + if (flags_mid & NSOS_MID_ ## _flag) { \ + flags_mid &= ~NSOS_MID_ ## _flag; \ + flags |= _flag; \ + } + + FROM_NSOS_MID(O_RDONLY); + FROM_NSOS_MID(O_WRONLY); + FROM_NSOS_MID(O_RDWR); + + FROM_NSOS_MID(O_APPEND); + FROM_NSOS_MID(O_EXCL); + FROM_NSOS_MID(O_NONBLOCK); + +#undef FROM_NSOS_MID + + return flags; +} diff --git a/drivers/net/nsos_fcntl.h b/drivers/net/nsos_fcntl.h new file mode 100644 index 00000000000..3cab88896f7 --- /dev/null +++ b/drivers/net/nsos_fcntl.h @@ -0,0 +1,22 @@ +/** + * Copyright (c) 2023-2024 Marcin Niestroj + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRIVERS_NET_NSOS_FCNTL_H__ +#define __DRIVERS_NET_NSOS_FCNTL_H__ + +#define NSOS_MID_O_RDONLY 00 +#define NSOS_MID_O_WRONLY 01 +#define NSOS_MID_O_RDWR 02 + +#define NSOS_MID_O_APPEND 0x0400 +#define NSOS_MID_O_EXCL 0x0800 +#define NSOS_MID_O_NONBLOCK 0x4000 + +int fl_to_nsos_mid(int flags); +int fl_to_nsos_mid_strict(int flags); +int fl_from_nsos_mid(int flags); + +#endif /* __DRIVERS_NET_NSOS_FCNTL_H__ */ diff --git a/drivers/net/nsos_sockets.c b/drivers/net/nsos_sockets.c index 89257072bd6..abb4c1a36db 100644 --- a/drivers/net/nsos_sockets.c +++ b/drivers/net/nsos_sockets.c @@ -18,11 +18,13 @@ #include #include #include +#include #include #include "sockets_internal.h" #include "nsos.h" #include "nsos_errno.h" +#include "nsos_fcntl.h" #include "nsos_netdb.h" #include "nsi_host_trampolines.h" @@ -227,6 +229,28 @@ static int nsos_ioctl(void *obj, unsigned int request, va_list args) case ZFD_IOCTL_POLL_OFFLOAD: return -EOPNOTSUPP; + + case F_GETFL: { + int flags; + + flags = nsos_adapt_fcntl_getfl(OBJ_TO_FD(obj)); + + return fl_from_nsos_mid(flags); + } + + case F_SETFL: { + int flags = va_arg(args, int); + int ret; + + ret = fl_to_nsos_mid_strict(flags); + if (ret < 0) { + return -errno_from_nsos_mid(-ret); + } + + ret = nsos_adapt_fcntl_setfl(OBJ_TO_FD(obj), flags); + + return -errno_from_nsos_mid(-ret); + } } return -EINVAL; From 8487fcca5b450e7c14a70040c2a305956ae6eca1 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Tue, 6 Feb 2024 13:24:09 +0100 Subject: [PATCH 1228/2402] drivers: net: nsos: implement poll() syscall Use NSI_HW_EVENT() in order to periodically check for events in host sockets. Whenever there is a socket event ready to be processed by Zephyr, raise native_sim (newly introduced) CPU interrupt, so that Zephyr driver can signal readiness with k_poll(). Maintain a list of Zephyr poll() executions in Zephyr context. Iterate through them whenever there is some event to be processed. Signed-off-by: Marcin Niestroj --- boards/native/native_sim/board_soc.h | 2 + drivers/net/CMakeLists.txt | 4 + drivers/net/Kconfig | 16 ++- drivers/net/nsos.h | 4 + drivers/net/nsos_adapt.c | 128 ++++++++++++++++++ drivers/net/nsos_sockets.c | 195 +++++++++++++++++++++++---- 6 files changed, 322 insertions(+), 27 deletions(-) diff --git a/boards/native/native_sim/board_soc.h b/boards/native/native_sim/board_soc.h index 2d2419038f4..81cc5679482 100644 --- a/boards/native/native_sim/board_soc.h +++ b/boards/native/native_sim/board_soc.h @@ -22,4 +22,6 @@ #include "nsi_cpu0_interrupts.h" +#define NSOS_IRQ 3 + #endif /* BOARDS_POSIX_NATIVE_SIM_BOARD_SOC_H */ diff --git a/drivers/net/CMakeLists.txt b/drivers/net/CMakeLists.txt index 8516d4472ef..456d27c02e9 100644 --- a/drivers/net/CMakeLists.txt +++ b/drivers/net/CMakeLists.txt @@ -18,6 +18,10 @@ if(CONFIG_NET_NATIVE_OFFLOADED_SOCKETS) zephyr_library_sources(nsos_fcntl.c) zephyr_library_sources(nsos_netdb.c) zephyr_library_sources(nsos_sockets.c) + target_compile_options(native_simulator BEFORE INTERFACE + -I${BOARD_DIR} + -DNSOS_EPOLL_WAIT_INTERVAL=${CONFIG_NET_NATIVE_OFFLOADED_SOCKETS_EPOLL_WAIT_INTERVAL} + ) target_sources(native_simulator INTERFACE nsos_adapt.c) target_sources(native_simulator INTERFACE nsos_errno.c) target_sources(native_simulator INTERFACE nsos_fcntl.c) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 5ebda70c1d1..c9ad4e34e87 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -228,7 +228,7 @@ endif # NET_CAN # Native simulator offloaded sockets # -config NET_NATIVE_OFFLOADED_SOCKETS +menuconfig NET_NATIVE_OFFLOADED_SOCKETS bool "Native Simulator offloaded sockets" depends on ARCH_POSIX depends on NATIVE_LIBRARY @@ -240,4 +240,18 @@ config NET_NATIVE_OFFLOADED_SOCKETS This driver main advantage is that it is possible to use this driver without any additional setup on the host side, unlike with the native TAP Ethernet driver. +if NET_NATIVE_OFFLOADED_SOCKETS + +config NET_NATIVE_OFFLOADED_SOCKETS_EPOLL_WAIT_INTERVAL + int "Interval between epoll_wait() calls (in simulated microseconds)" + default 1000 + help + Number of simulated microseconds before next epoll_wait() call, when there were no pending + events detected. + + Decrease that value when lower network traffic latency is expected, at the expense of more + CPU processing overhead. + +endif # NET_NATIVE_OFFLOADED_SOCKETS + endif # NET_DRIVERS diff --git a/drivers/net/nsos.h b/drivers/net/nsos.h index d9ac86c910a..14b495177c3 100644 --- a/drivers/net/nsos.h +++ b/drivers/net/nsos.h @@ -74,6 +74,8 @@ struct nsos_mid_pollfd { int fd; short events; short revents; + + void (*cb)(struct nsos_mid_pollfd *pollfd_mid); }; struct nsos_mid_addrinfo { @@ -109,6 +111,8 @@ int nsos_adapt_sendto(int fd, const void *buf, size_t len, int flags, int nsos_adapt_recvfrom(int fd, void *buf, size_t len, int flags, struct nsos_mid_sockaddr *addr, size_t *addrlen); +void nsos_adapt_poll_add(struct nsos_mid_pollfd *pollfd); +void nsos_adapt_poll_remove(struct nsos_mid_pollfd *pollfd); int nsos_adapt_fcntl_getfl(int fd); int nsos_adapt_fcntl_setfl(int fd, int flags); diff --git a/drivers/net/nsos_adapt.c b/drivers/net/nsos_adapt.c index fe7f9ba47ac..a7ecd46eeb4 100644 --- a/drivers/net/nsos_adapt.c +++ b/drivers/net/nsos_adapt.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -25,10 +26,21 @@ #include "nsos_fcntl.h" #include "nsos_netdb.h" +#include "board_soc.h" +#include "irq_ctrl.h" +#include "nsi_hws_models_if.h" +#include "nsi_tasks.h" #include "nsi_tracing.h" #include +static int nsos_epoll_fd; +static int nsos_adapt_nfds; + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0])) +#endif + #ifndef CONTAINER_OF #define CONTAINER_OF(ptr, type, field) \ ((type *)(((char *)(ptr)) - offsetof(type, field))) @@ -456,6 +468,71 @@ int nsos_adapt_recvfrom(int fd, void *buf, size_t len, int flags, return ret; } +#define MAP_POLL_EPOLL(_event_from, _event_to) \ + if (events_from & (_event_from)) { \ + events_from &= ~(_event_from); \ + events_to |= _event_to; \ + } + +static int nsos_poll_to_epoll_events(int events_from) +{ + int events_to = 0; + + MAP_POLL_EPOLL(POLLIN, EPOLLIN); + MAP_POLL_EPOLL(POLLOUT, EPOLLOUT); + MAP_POLL_EPOLL(POLLERR, EPOLLERR); + + return events_to; +} + +static int nsos_epoll_to_poll_events(int events_from) +{ + int events_to = 0; + + MAP_POLL_EPOLL(EPOLLIN, POLLIN); + MAP_POLL_EPOLL(EPOLLOUT, POLLOUT); + MAP_POLL_EPOLL(EPOLLERR, POLLERR); + + return events_to; +} + +#undef MAP_POLL_EPOLL + +static uint64_t nsos_adapt_poll_time = NSI_NEVER; + +void nsos_adapt_poll_add(struct nsos_mid_pollfd *pollfd) +{ + struct epoll_event ev = { + .data.ptr = pollfd, + .events = nsos_poll_to_epoll_events(pollfd->events), + }; + int err; + + nsos_adapt_nfds++; + + err = epoll_ctl(nsos_epoll_fd, EPOLL_CTL_ADD, pollfd->fd, &ev); + if (err) { + nsi_print_error_and_exit("error in EPOLL_CTL_ADD: errno=%d\n", errno); + return; + } + + nsos_adapt_poll_time = nsi_hws_get_time() + 1; + nsi_hws_find_next_event(); +} + +void nsos_adapt_poll_remove(struct nsos_mid_pollfd *pollfd) +{ + int err; + + err = epoll_ctl(nsos_epoll_fd, EPOLL_CTL_DEL, pollfd->fd, NULL); + if (err) { + nsi_print_error_and_exit("error in EPOLL_CTL_ADD: errno=%d\n", errno); + return; + } + + nsos_adapt_nfds--; +} + struct nsos_addrinfo_wrap { struct nsos_mid_addrinfo addrinfo_mid; struct nsos_mid_sockaddr_storage addr_storage; @@ -619,3 +696,54 @@ int nsos_adapt_fcntl_setfl(int fd, int flags) return 0; } + +static void nsos_adapt_init(void) +{ + nsos_epoll_fd = epoll_create(1); + if (nsos_epoll_fd < 0) { + nsi_print_error_and_exit("error from epoll_create(): errno=%d\n", errno); + return; + } +} + +NSI_TASK(nsos_adapt_init, HW_INIT, 500); + +static void nsos_adapt_poll_triggered(void) +{ + static struct epoll_event events[1024]; + int ret; + + if (nsos_adapt_nfds == 0) { + nsos_adapt_poll_time = NSI_NEVER; + return; + } + + ret = epoll_wait(nsos_epoll_fd, events, ARRAY_SIZE(events), 0); + if (ret < 0) { + if (errno == EINTR) { + nsi_print_warning("interrupted epoll_wait()\n"); + nsos_adapt_poll_time = nsi_hws_get_time() + 1; + return; + } + + nsi_print_error_and_exit("error in nsos_adapt poll(): errno=%d\n", errno); + + nsos_adapt_poll_time = NSI_NEVER; + return; + } + + for (int i = 0; i < ret; i++) { + struct nsos_mid_pollfd *pollfd = events[i].data.ptr; + + pollfd->revents = nsos_epoll_to_poll_events(events[i].events); + } + + if (ret > 0) { + hw_irq_ctrl_set_irq(NSOS_IRQ); + nsos_adapt_poll_time = nsi_hws_get_time() + 1; + } else { + nsos_adapt_poll_time = nsi_hws_get_time() + NSOS_EPOLL_WAIT_INTERVAL; + } +} + +NSI_HW_EVENT(nsos_adapt_poll_time, nsos_adapt_poll_triggered, 500); diff --git a/drivers/net/nsos_sockets.c b/drivers/net/nsos_sockets.c index abb4c1a36db..03bc5a7ac8a 100644 --- a/drivers/net/nsos_sockets.c +++ b/drivers/net/nsos_sockets.c @@ -13,6 +13,7 @@ #undef _POSIX_C_SOURCE #define _POSIX_C_SOURCE 200809L +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include "sockets_internal.h" #include "nsos.h" @@ -29,11 +31,19 @@ #include "nsi_host_trampolines.h" -/* Increment by 1 to make sure we do not store the value of 0, which has - * a special meaning in the fdtable subsys. - */ -#define FD_TO_OBJ(fd) ((void *)(intptr_t)((fd) + 1)) -#define OBJ_TO_FD(obj) (((int)(intptr_t)(obj)) - 1) +BUILD_ASSERT(CONFIG_HEAP_MEM_POOL_SIZE > 0); + +#define NSOS_IRQ_FLAGS (0) +#define NSOS_IRQ_PRIORITY (2) + +struct nsos_socket { + struct nsos_mid_pollfd pollfd; + struct k_poll_signal poll; + + sys_dnode_t node; +}; + +static sys_dlist_t nsos_sockets = SYS_DLIST_STATIC_INIT(&nsos_sockets); static int socket_family_to_nsos_mid(int family, int *family_mid) { @@ -132,7 +142,7 @@ static const struct socket_op_vtable nsos_socket_fd_op_vtable; static int nsos_socket_create(int family, int type, int proto) { int fd; - int sock; + struct nsos_socket *sock; int family_mid; int type_mid; int proto_mid; @@ -161,16 +171,25 @@ static int nsos_socket_create(int family, int type, int proto) return -1; } - sock = nsos_adapt_socket(family_mid, type_mid, proto_mid); - if (sock < 0) { - errno = errno_from_nsos_mid(-sock); + sock = k_malloc(sizeof(*sock)); + if (!sock) { + errno = ENOMEM; goto free_fd; } - z_finalize_fd(fd, FD_TO_OBJ(sock), &nsos_socket_fd_op_vtable.fd_vtable); + sock->pollfd.fd = nsos_adapt_socket(family_mid, type_mid, proto_mid); + if (sock->pollfd.fd < 0) { + errno = errno_from_nsos_mid(-sock->pollfd.fd); + goto free_sock; + } + + z_finalize_fd(fd, sock, &nsos_socket_fd_op_vtable.fd_vtable); return fd; +free_sock: + k_free(sock); + free_fd: z_free_fd(fd); @@ -184,9 +203,10 @@ static int nsos_adapt_get_zephyr_errno(void) static ssize_t nsos_read(void *obj, void *buf, size_t sz) { + struct nsos_socket *sock = obj; int ret; - ret = nsi_host_read(OBJ_TO_FD(obj), buf, sz); + ret = nsi_host_read(sock->pollfd.fd, buf, sz); if (ret < 0) { errno = nsos_adapt_get_zephyr_errno(); } @@ -196,9 +216,10 @@ static ssize_t nsos_read(void *obj, void *buf, size_t sz) static ssize_t nsos_write(void *obj, const void *buf, size_t sz) { + struct nsos_socket *sock = obj; int ret; - ret = nsi_host_write(OBJ_TO_FD(obj), buf, sz); + ret = nsi_host_write(sock->pollfd.fd, buf, sz); if (ret < 0) { errno = nsos_adapt_get_zephyr_errno(); } @@ -208,9 +229,10 @@ static ssize_t nsos_write(void *obj, const void *buf, size_t sz) static int nsos_close(void *obj) { + struct nsos_socket *sock = obj; int ret; - ret = nsi_host_close(OBJ_TO_FD(obj)); + ret = nsi_host_close(sock->pollfd.fd); if (ret < 0) { errno = nsos_adapt_get_zephyr_errno(); } @@ -218,14 +240,100 @@ static int nsos_close(void *obj) return ret; } +static void pollcb(struct nsos_mid_pollfd *pollfd) +{ + struct nsos_socket *sock = CONTAINER_OF(pollfd, struct nsos_socket, pollfd); + + k_poll_signal_raise(&sock->poll, sock->pollfd.revents); +} + +static int nsos_poll_prepare(struct nsos_socket *sock, struct zsock_pollfd *pfd, + struct k_poll_event **pev, struct k_poll_event *pev_end) +{ + unsigned int signaled; + int flags; + + sock->pollfd.events = pfd->events; + sock->pollfd.revents = 0; + sock->pollfd.cb = pollcb; + + if (*pev == pev_end) { + errno = ENOMEM; + return -1; + } + + k_poll_signal_init(&sock->poll); + k_poll_event_init(*pev, K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &sock->poll); + + sys_dlist_append(&nsos_sockets, &sock->node); + + nsos_adapt_poll_add(&sock->pollfd); + + /* Let other sockets use another k_poll_event */ + (*pev)++; + + signaled = 0; + flags = 0; + + k_poll_signal_check(&sock->poll, &signaled, &flags); + if (!signaled) { + return 0; + } + + /* Events are ready, don't wait */ + return -EALREADY; +} + +static int nsos_poll_update(struct nsos_socket *sock, struct zsock_pollfd *pfd, + struct k_poll_event **pev) +{ + unsigned int signaled; + int flags; + + (*pev)++; + + signaled = 0; + flags = 0; + + nsos_adapt_poll_remove(&sock->pollfd); + sys_dlist_remove(&sock->node); + + k_poll_signal_check(&sock->poll, &signaled, &flags); + if (!signaled) { + return 0; + } + + pfd->revents = flags; + + return 0; +} + static int nsos_ioctl(void *obj, unsigned int request, va_list args) { + struct nsos_socket *sock = obj; + switch (request) { - case ZFD_IOCTL_POLL_PREPARE: - return -EXDEV; + case ZFD_IOCTL_POLL_PREPARE: { + struct zsock_pollfd *pfd; + struct k_poll_event **pev; + struct k_poll_event *pev_end; - case ZFD_IOCTL_POLL_UPDATE: - return -EOPNOTSUPP; + pfd = va_arg(args, struct zsock_pollfd *); + pev = va_arg(args, struct k_poll_event **); + pev_end = va_arg(args, struct k_poll_event *); + + return nsos_poll_prepare(obj, pfd, pev, pev_end); + } + + case ZFD_IOCTL_POLL_UPDATE: { + struct zsock_pollfd *pfd; + struct k_poll_event **pev; + + pfd = va_arg(args, struct zsock_pollfd *); + pev = va_arg(args, struct k_poll_event **); + + return nsos_poll_update(obj, pfd, pev); + } case ZFD_IOCTL_POLL_OFFLOAD: return -EOPNOTSUPP; @@ -233,7 +341,7 @@ static int nsos_ioctl(void *obj, unsigned int request, va_list args) case F_GETFL: { int flags; - flags = nsos_adapt_fcntl_getfl(OBJ_TO_FD(obj)); + flags = nsos_adapt_fcntl_getfl(sock->pollfd.fd); return fl_from_nsos_mid(flags); } @@ -247,7 +355,7 @@ static int nsos_ioctl(void *obj, unsigned int request, va_list args) return -errno_from_nsos_mid(-ret); } - ret = nsos_adapt_fcntl_setfl(OBJ_TO_FD(obj), flags); + ret = nsos_adapt_fcntl_setfl(sock->pollfd.fd, flags); return -errno_from_nsos_mid(-ret); } @@ -355,6 +463,7 @@ static int sockaddr_from_nsos_mid(struct sockaddr *addr, socklen_t *addrlen, static int nsos_bind(void *obj, const struct sockaddr *addr, socklen_t addrlen) { + struct nsos_socket *sock = obj; struct nsos_mid_sockaddr_storage addr_storage_mid; struct nsos_mid_sockaddr *addr_mid = (struct nsos_mid_sockaddr *)&addr_storage_mid; size_t addrlen_mid; @@ -365,7 +474,7 @@ static int nsos_bind(void *obj, const struct sockaddr *addr, socklen_t addrlen) goto return_ret; } - ret = nsos_adapt_bind(OBJ_TO_FD(obj), addr_mid, addrlen_mid); + ret = nsos_adapt_bind(sock->pollfd.fd, addr_mid, addrlen_mid); return_ret: if (ret < 0) { @@ -378,6 +487,7 @@ static int nsos_bind(void *obj, const struct sockaddr *addr, socklen_t addrlen) static int nsos_connect(void *obj, const struct sockaddr *addr, socklen_t addrlen) { + struct nsos_socket *sock = obj; struct nsos_mid_sockaddr_storage addr_storage_mid; struct nsos_mid_sockaddr *addr_mid = (struct nsos_mid_sockaddr *)&addr_storage_mid; size_t addrlen_mid; @@ -388,7 +498,7 @@ static int nsos_connect(void *obj, const struct sockaddr *addr, socklen_t addrle goto return_ret; } - ret = nsos_adapt_connect(OBJ_TO_FD(obj), addr_mid, addrlen_mid); + ret = nsos_adapt_connect(sock->pollfd.fd, addr_mid, addrlen_mid); return_ret: if (ret < 0) { @@ -401,9 +511,10 @@ static int nsos_connect(void *obj, const struct sockaddr *addr, socklen_t addrle static int nsos_listen(void *obj, int backlog) { + struct nsos_socket *sock = obj; int ret; - ret = nsos_adapt_listen(OBJ_TO_FD(obj), backlog); + ret = nsos_adapt_listen(sock->pollfd.fd, backlog); if (ret < 0) { errno = errno_from_nsos_mid(-ret); return -1; @@ -414,12 +525,16 @@ static int nsos_listen(void *obj, int backlog) static int nsos_accept(void *obj, struct sockaddr *addr, socklen_t *addrlen) { + struct nsos_socket *accept_sock = obj; struct nsos_mid_sockaddr_storage addr_storage_mid; struct nsos_mid_sockaddr *addr_mid = (struct nsos_mid_sockaddr *)&addr_storage_mid; size_t addrlen_mid = sizeof(addr_storage_mid); + int adapt_fd; + int zephyr_fd; + struct nsos_socket *conn_sock; int ret; - ret = nsos_adapt_accept(OBJ_TO_FD(obj), addr_mid, &addrlen_mid); + ret = nsos_adapt_accept(accept_sock->pollfd.fd, addr_mid, &addrlen_mid); if (ret < 0) { errno = errno_from_nsos_mid(-ret); return -1; @@ -438,10 +553,21 @@ static int nsos_accept(void *obj, struct sockaddr *addr, socklen_t *addrlen) goto close_adapt_fd; } - z_finalize_fd(zephyr_fd, FD_TO_OBJ(adapt_fd), &nsos_socket_fd_op_vtable.fd_vtable); + conn_sock = k_malloc(sizeof(*conn_sock)); + if (!conn_sock) { + errno = ENOMEM; + goto free_zephyr_fd; + } + + conn_sock->pollfd.fd = adapt_fd; + + z_finalize_fd(zephyr_fd, conn_sock, &nsos_socket_fd_op_vtable.fd_vtable); return zephyr_fd; +free_zephyr_fd: + z_free_fd(zephyr_fd); + close_adapt_fd: nsi_host_close(adapt_fd); @@ -451,6 +577,7 @@ static int nsos_accept(void *obj, struct sockaddr *addr, socklen_t *addrlen) static ssize_t nsos_sendto(void *obj, const void *buf, size_t len, int flags, const struct sockaddr *addr, socklen_t addrlen) { + struct nsos_socket *sock = obj; struct nsos_mid_sockaddr_storage addr_storage_mid; struct nsos_mid_sockaddr *addr_mid = (struct nsos_mid_sockaddr *)&addr_storage_mid; size_t addrlen_mid = sizeof(addr_storage_mid); @@ -469,7 +596,7 @@ static ssize_t nsos_sendto(void *obj, const void *buf, size_t len, int flags, goto return_ret; } - ret = nsos_adapt_sendto(OBJ_TO_FD(obj), buf, len, flags_mid, + ret = nsos_adapt_sendto(sock->pollfd.fd, buf, len, flags_mid, addr_mid, addrlen_mid); return_ret: @@ -490,6 +617,7 @@ static ssize_t nsos_sendmsg(void *obj, const struct msghdr *msg, int flags) static ssize_t nsos_recvfrom(void *obj, void *buf, size_t len, int flags, struct sockaddr *addr, socklen_t *addrlen) { + struct nsos_socket *sock = obj; struct nsos_mid_sockaddr_storage addr_storage_mid; struct nsos_mid_sockaddr *addr_mid = (struct nsos_mid_sockaddr *)&addr_storage_mid; size_t addrlen_mid = sizeof(addr_storage_mid); @@ -503,7 +631,7 @@ static ssize_t nsos_recvfrom(void *obj, void *buf, size_t len, int flags, flags_mid = ret; - ret = nsos_adapt_recvfrom(OBJ_TO_FD(obj), buf, len, flags_mid, + ret = nsos_adapt_recvfrom(sock->pollfd.fd, buf, len, flags_mid, addr_mid, &addrlen_mid); if (ret < 0) { goto return_ret; @@ -699,10 +827,25 @@ static const struct socket_dns_offload nsos_dns_ops = { .freeaddrinfo = nsos_freeaddrinfo, }; +static void nsos_isr(const void *obj) +{ + struct nsos_socket *sock; + + SYS_DLIST_FOR_EACH_CONTAINER(&nsos_sockets, sock, node) { + if (sock->pollfd.revents) { + sock->pollfd.cb(&sock->pollfd); + } + } +} + static int nsos_socket_offload_init(const struct device *arg) { ARG_UNUSED(arg); + IRQ_CONNECT(NSOS_IRQ, NSOS_IRQ_PRIORITY, + nsos_isr, NULL, NSOS_IRQ_FLAGS); + irq_enable(NSOS_IRQ); + return 0; } From 4f9e3fa1b71683e70f065cb880464573a10cd93d Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Fri, 23 Feb 2024 14:10:26 +0100 Subject: [PATCH 1229/2402] drivers: net: nsos: support blocking accept() and recvfrom() So far only non-blocking accept() and recvfrom() were suported. This patch implements blocking behavior, with the use of poll(fd, POLLIN) as helper mechanism. Signed-off-by: Marcin Niestroj --- drivers/net/nsos_sockets.c | 93 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 90 insertions(+), 3 deletions(-) diff --git a/drivers/net/nsos_sockets.c b/drivers/net/nsos_sockets.c index 03bc5a7ac8a..b70940697a9 100644 --- a/drivers/net/nsos_sockets.c +++ b/drivers/net/nsos_sockets.c @@ -37,6 +37,7 @@ BUILD_ASSERT(CONFIG_HEAP_MEM_POOL_SIZE > 0); #define NSOS_IRQ_PRIORITY (2) struct nsos_socket { + int fd; struct nsos_mid_pollfd pollfd; struct k_poll_signal poll; @@ -177,6 +178,8 @@ static int nsos_socket_create(int family, int type, int proto) goto free_fd; } + sock->fd = fd; + sock->pollfd.fd = nsos_adapt_socket(family_mid, type_mid, proto_mid); if (sock->pollfd.fd < 0) { errno = errno_from_nsos_mid(-sock->pollfd.fd); @@ -523,6 +526,59 @@ static int nsos_listen(void *obj, int backlog) return ret; } +static int nsos_wait_for_pollin(struct nsos_socket *sock) +{ + struct zsock_pollfd pfd = { + .fd = sock->fd, + .events = ZSOCK_POLLIN, + }; + struct k_poll_event poll_events[1]; + struct k_poll_event *pev = poll_events; + struct k_poll_event *pev_end = poll_events + ARRAY_SIZE(poll_events); + int ret; + + ret = nsos_poll_prepare(sock, &pfd, &pev, pev_end); + if (ret == -EALREADY) { + return 0; + } else if (ret < 0) { + return ret; + } + + ret = k_poll(poll_events, ARRAY_SIZE(poll_events), K_FOREVER); + if (ret != 0 && ret != -EAGAIN && ret != -EINTR) { + return ret; + } + + pev = poll_events; + nsos_poll_update(sock, &pfd, &pev); + + return 0; +} + +static int nsos_accept_with_poll(struct nsos_socket *sock, + struct nsos_mid_sockaddr *addr_mid, + size_t *addrlen_mid) +{ + int ret = 0; + int flags; + + flags = nsos_adapt_fcntl_getfl(sock->pollfd.fd); + + if (!(flags & NSOS_MID_O_NONBLOCK)) { + ret = nsos_wait_for_pollin(sock); + if (ret < 0) { + return ret; + } + } + + ret = nsos_adapt_accept(sock->pollfd.fd, addr_mid, addrlen_mid); + if (ret < 0) { + return -errno_from_nsos_mid(-ret); + } + + return ret; +} + static int nsos_accept(void *obj, struct sockaddr *addr, socklen_t *addrlen) { struct nsos_socket *accept_sock = obj; @@ -534,7 +590,7 @@ static int nsos_accept(void *obj, struct sockaddr *addr, socklen_t *addrlen) struct nsos_socket *conn_sock; int ret; - ret = nsos_adapt_accept(accept_sock->pollfd.fd, addr_mid, &addrlen_mid); + ret = nsos_accept_with_poll(accept_sock, addr_mid, &addrlen_mid); if (ret < 0) { errno = errno_from_nsos_mid(-ret); return -1; @@ -559,6 +615,7 @@ static int nsos_accept(void *obj, struct sockaddr *addr, socklen_t *addrlen) goto free_zephyr_fd; } + conn_sock->fd = zephyr_fd; conn_sock->pollfd.fd = adapt_fd; z_finalize_fd(zephyr_fd, conn_sock, &nsos_socket_fd_op_vtable.fd_vtable); @@ -614,6 +671,36 @@ static ssize_t nsos_sendmsg(void *obj, const struct msghdr *msg, int flags) return -1; } +static int nsos_recvfrom_with_poll(struct nsos_socket *sock, void *buf, size_t len, int flags, + struct nsos_mid_sockaddr *addr_mid, size_t *addrlen_mid) +{ + int ret = 0; + int sock_flags; + bool non_blocking; + + if (flags & MSG_DONTWAIT) { + non_blocking = true; + } else { + sock_flags = nsos_adapt_fcntl_getfl(sock->pollfd.fd); + non_blocking = sock_flags & NSOS_MID_O_NONBLOCK; + } + + if (!non_blocking) { + ret = nsos_wait_for_pollin(sock); + if (ret < 0) { + return ret; + } + } + + ret = nsos_adapt_recvfrom(sock->pollfd.fd, buf, len, flags, + addr_mid, addrlen_mid); + if (ret < 0) { + return -errno_from_nsos_mid(-ret); + } + + return ret; +} + static ssize_t nsos_recvfrom(void *obj, void *buf, size_t len, int flags, struct sockaddr *addr, socklen_t *addrlen) { @@ -631,8 +718,8 @@ static ssize_t nsos_recvfrom(void *obj, void *buf, size_t len, int flags, flags_mid = ret; - ret = nsos_adapt_recvfrom(sock->pollfd.fd, buf, len, flags_mid, - addr_mid, &addrlen_mid); + ret = nsos_recvfrom_with_poll(sock, buf, len, flags_mid, + addr_mid, &addrlen_mid); if (ret < 0) { goto return_ret; } From 5c4b587f074fc9748d90d635e564c78cfea955b2 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Sat, 11 Nov 2023 16:03:47 +0100 Subject: [PATCH 1230/2402] samples: http_get: add tests with Native Simulator offloaded sockets 'http_get' is one of the few samples that just require connection to internet (google.com over HTTP or HTTPS) and check if HTTP GET was successful. Use it for minimal coverage of Native Simulator offloaded sockets: * DNS resolving * basic TCP transfer * compatibility with Zephyr TLS subsystem (which required some fcntl() operations) Signed-off-by: Marcin Niestroj --- .../net/sockets/http_get/overlay-nsos.conf | 6 ++++ samples/net/sockets/http_get/sample.yaml | 30 ++++++++++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) create mode 100644 samples/net/sockets/http_get/overlay-nsos.conf diff --git a/samples/net/sockets/http_get/overlay-nsos.conf b/samples/net/sockets/http_get/overlay-nsos.conf new file mode 100644 index 00000000000..0af19c1b112 --- /dev/null +++ b/samples/net/sockets/http_get/overlay-nsos.conf @@ -0,0 +1,6 @@ +CONFIG_ETH_NATIVE_POSIX=n +CONFIG_NET_DRIVERS=y +CONFIG_NET_SOCKETS=y +CONFIG_NET_SOCKETS_OFFLOAD=y +CONFIG_NET_NATIVE_OFFLOADED_SOCKETS=y +CONFIG_HEAP_MEM_POOL_SIZE=1024 diff --git a/samples/net/sockets/http_get/sample.yaml b/samples/net/sockets/http_get/sample.yaml index 2de78ce0bee..4bdb915f2e5 100644 --- a/samples/net/sockets/http_get/sample.yaml +++ b/samples/net/sockets/http_get/sample.yaml @@ -3,7 +3,6 @@ sample: name: socket_http_get common: filter: CONFIG_FULL_LIBC_SUPPORTED - harness: net min_ram: 32 min_flash: 80 tags: @@ -11,12 +10,14 @@ common: - socket tests: sample.net.sockets.http_get: + harness: net extra_configs: - CONFIG_NET_SOCKETS_POSIX_NAMES=y # Forcibly defines CONFIG_POSIX_API, which is incompatible with # CONFIG_NET_SOCKETS_POSIX_NAMES. sample.net.sockets.http_get.posix: filter: not CONFIG_NET_SOCKETS_OFFLOAD and not CONFIG_NATIVE_LIBC + harness: net platform_exclude: - cc3220sf_launchxl - cc3235sf_launchxl @@ -25,8 +26,35 @@ tests: - CONFIG_POSIX_API=y sample.net.sockets.http_get.offload.simplelink: platform_allow: cc3220sf_launchxl + harness: net tags: - net - socket - offload - simplelink + sample.get.sockets.http_get.nsos.http: + harness: console + harness_config: + type: multi_line + ordered: true + regex: + - "(.*)(.*)" + - "The document has moved" + - "(.*)(.*)" + platform_allow: + - native_sim + - native_sim/native/64 + extra_args: OVERLAY_CONFIG="overlay-nsos.conf" + sample.get.sockets.http_get.nsos.https: + harness: console + harness_config: + type: multi_line + ordered: true + regex: + - "(.*)(.*)" + - "The document has moved" + - "(.*)(.*)" + platform_allow: + - native_sim + - native_sim/native/64 + extra_args: OVERLAY_CONFIG="overlay-nsos.conf;overlay-tls.conf" From 9359903bd6efecbc060cc1f88eed3b3b7aa0dc77 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Fri, 23 Feb 2024 14:35:48 +0100 Subject: [PATCH 1231/2402] samples: net: echo_server: add native_sim to allowed platforms 'native_sim' builds without any issues as part of twister and it also works when manually setting up Ethernet virtual device (using tools/net-tools/net-setup.sh). Signed-off-by: Marcin Niestroj --- samples/net/sockets/echo_server/sample.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/samples/net/sockets/echo_server/sample.yaml b/samples/net/sockets/echo_server/sample.yaml index a04c96fe4a0..c7d01f9fe49 100644 --- a/samples/net/sockets/echo_server/sample.yaml +++ b/samples/net/sockets/echo_server/sample.yaml @@ -18,6 +18,7 @@ tests: - qemu_cortex_m3 - frdm_kw41z - qemu_cortex_a53 + - native_sim integration_platforms: - qemu_x86 sample.net.sockets.echo_server.802154: From 81574fd1dfb18038ff03df920cb3983a63b152e1 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Fri, 23 Feb 2024 14:25:10 +0100 Subject: [PATCH 1232/2402] samples: net: echo_server: add config for native_sim offloaded sockets Add configuration for Native Simulator offloaded sockets. Signed-off-by: Marcin Niestroj --- samples/net/sockets/echo_server/overlay-nsos.conf | 9 +++++++++ samples/net/sockets/echo_server/sample.yaml | 5 +++++ 2 files changed, 14 insertions(+) create mode 100644 samples/net/sockets/echo_server/overlay-nsos.conf diff --git a/samples/net/sockets/echo_server/overlay-nsos.conf b/samples/net/sockets/echo_server/overlay-nsos.conf new file mode 100644 index 00000000000..eaee3e55615 --- /dev/null +++ b/samples/net/sockets/echo_server/overlay-nsos.conf @@ -0,0 +1,9 @@ +CONFIG_ETH_NATIVE_POSIX=n +CONFIG_NET_DRIVERS=y +CONFIG_NET_SOCKETS=y +CONFIG_NET_SOCKETS_OFFLOAD=y +CONFIG_NET_NATIVE_OFFLOADED_SOCKETS=y +CONFIG_HEAP_MEM_POOL_SIZE=1024 + +# IPv6 DAD requires lower level network interface access, below exposed socket-level access +CONFIG_NET_IPV6_DAD=n diff --git a/samples/net/sockets/echo_server/sample.yaml b/samples/net/sockets/echo_server/sample.yaml index c7d01f9fe49..93bdb943623 100644 --- a/samples/net/sockets/echo_server/sample.yaml +++ b/samples/net/sockets/echo_server/sample.yaml @@ -133,3 +133,8 @@ tests: - qemu_x86_64 integration_platforms: - qemu_x86 + sample.net.sockets.echo_server.nsos: + platform_allow: + - native_sim + extra_args: + - OVERLAY_CONFIG="overlay-nsos.conf" From 64ff60a870e30a6394e892666f98295db8b53940 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Fri, 23 Feb 2024 14:58:54 +0100 Subject: [PATCH 1233/2402] doc: networking: document native_sim with offloaded sockets Document how offloaded sockets can be used with 'native_sim' for networking capability. Signed-off-by: Marcin Niestroj --- .../networking/native_sim_setup.rst | 65 +++++++++++++++++-- .../networking/networking_with_host.rst | 3 +- 2 files changed, 61 insertions(+), 7 deletions(-) diff --git a/doc/connectivity/networking/native_sim_setup.rst b/doc/connectivity/networking/native_sim_setup.rst index 166ff707c89..4c954357006 100644 --- a/doc/connectivity/networking/native_sim_setup.rst +++ b/doc/connectivity/networking/native_sim_setup.rst @@ -7,7 +7,10 @@ Networking with native_sim board :local: :depth: 2 -This page describes how to set up a virtual network between a (Linux) host +Using virtual/TAP Ethernet driver +********************************* + +This paragraph describes how to set up a virtual network between a (Linux) host and a Zephyr application running in a :ref:`native_sim ` board. In this example, the :zephyr:code-sample:`sockets-echo-server` sample application from @@ -16,7 +19,7 @@ native_sim board instance is connected to a Linux host using a tuntap device which is modeled in Linux as an Ethernet network interface. Prerequisites -************* +============= On the Linux Host, fetch the Zephyr ``net-tools`` project, which is located in a separate Git repository: @@ -27,7 +30,7 @@ in a separate Git repository: Basic Setup -*********** +=========== For the steps below, you will need three terminal windows: @@ -39,7 +42,7 @@ For the steps below, you will need three terminal windows: instance (optional). Step 1 - Create Ethernet interface -================================== +---------------------------------- Before starting native_sim with network emulation, a network interface should be created. @@ -59,7 +62,7 @@ by running ``net-setup.sh`` like this: Step 2 - Start app in native_sim board -====================================== +-------------------------------------- Build and start the ``echo_server`` sample application. @@ -74,7 +77,7 @@ In terminal #2, type: Step 3 - Connect to console (optional) -====================================== +-------------------------------------- The console window should be launched automatically when the Zephyr instance is started but if it does not show up, you can manually connect to the console. @@ -89,3 +92,53 @@ You can manually connect to it like this: .. code-block:: console screen /dev/pts/5 + +Using offloaded sockets +*********************** + +The main advantage over `Using virtual/TAP Ethernet driver`_ is not needing to +setup a virtual network interface on the host machine. This means that no +leveraged (root) privileges are needed. + +Step 1 - Start app in native_sim board +====================================== + +Build and start the ``echo_server`` sample application: + +.. zephyr-app-commands:: + :zephyr-app: samples/net/sockets/echo_server + :host-os: unix + :board: native_sim + :gen-args: -DEXTRA_CONF_FILE=overlay-nsos.conf + :goals: run + :compact: + +Step 2 - run echo-client from net-tools +======================================= + +On the Linux Host, fetch the Zephyr ``net-tools`` project, which is located +in a separate Git repository: + +.. code-block:: console + + git clone https://github.com/zephyrproject-rtos/net-tools + +.. note:: + + Native Simulator with the offloaded sockets network driver is using the same + network interface/namespace as any other (Linux) application that uses BSD + sockets API. This means that :zephyr:code-sample:`sockets-echo-server` and + ``echo-client`` applications will communicate over localhost/loopback + interface (address ``127.0.0.1``). + +To run UDP test, type: + +.. code-block:: console + + ./echo-client 127.0.0.1 + +For TCP test, type: + +.. code-block:: console + + ./echo-client -t 127.0.0.1 diff --git a/doc/connectivity/networking/networking_with_host.rst b/doc/connectivity/networking/networking_with_host.rst index 995e7dc0f80..b7ea3fd5257 100644 --- a/doc/connectivity/networking/networking_with_host.rst +++ b/doc/connectivity/networking/networking_with_host.rst @@ -59,7 +59,8 @@ possible: system. This is the most convenient way to debug the Zephyr system as one can attach host debugger directly to the running Zephyr instance. This requires that there is an adaptation driver in Zephyr for interfacing - with the host system. An Ethernet driver exists in Zephyr for this purpose. + with the host system. Two possible network drivers can be used for this + purpose, a TAP virtual Ethernet driver and an offloaded sockets driver. See :ref:`networking_with_native_sim` for details. * USB device networking. From 0f5b5b673bd9b28f5c1bc6355df45e8235921e5a Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Fri, 23 Feb 2024 15:10:31 +0100 Subject: [PATCH 1234/2402] boards: native_sim: document offloaded sockets driver Document offloaded sockets driver, which is an alternative to Ethernet driver for networking applications. Signed-off-by: Marcin Niestroj Co-authored-by: Alberto Escolar Piedras --- boards/native/native_sim/doc/index.rst | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/boards/native/native_sim/doc/index.rst b/boards/native/native_sim/doc/index.rst index 3745db84b56..0a304ca941c 100644 --- a/boards/native/native_sim/doc/index.rst +++ b/boards/native/native_sim/doc/index.rst @@ -379,6 +379,19 @@ The following peripherals are currently provided with this board: .. _net-tools: https://github.com/zephyrproject-rtos/net-tools +.. _nsim_per_offloaded_sockets: + +**Offloaded sockets driver** + This driver is an alternative to the :ref:`TAP based ethernet driver + `. Instead of using a virtual network in the Linux side, this + driver utilizes Linux's standard BSD socket API. With this, multiple Zephyr + applications can communicate over the Linux loopback interface. + The benefit of this approach is that root privileges are not required and + that the process is connected to the same interface as other Linux processes + instead of a virtual network, facilitating testing without the need for extra + setup in the host. The drawback is that the L2 layer of Zephyr's networking + stack is not exercised. + .. _nsim_bt_host_cont: **Bluetooth controller** @@ -697,6 +710,7 @@ host libC (:kconfig:option:`CONFIG_EXTERNAL_LIBC`): Input, Input SDL touch, :kconfig:option:`CONFIG_INPUT_SDL_TOUCH`, All Input, Linux evdev, :kconfig:option:`CONFIG_NATIVE_LINUX_EVDEV`, All Logger backend, :ref:`Native backend `, :kconfig:option:`CONFIG_LOG_BACKEND_NATIVE_POSIX`, All + Offloaded sockets, :ref:`nsim_per_offloaded_sockets`, :kconfig:option:`CONFIG_NET_NATIVE_OFFLOADED_SOCKETS`, All RTC, RTC emul, :kconfig:option:`CONFIG_RTC_EMUL`, All Serial, :ref:`UART native posix/PTTY `, :kconfig:option:`CONFIG_UART_NATIVE_POSIX`, All Serial, :ref:`UART native TTY `, :kconfig:option:`CONFIG_UART_NATIVE_TTY`, All From 38ad4b6d43cfc875a7ce8fdbe96825aa3e86ce6d Mon Sep 17 00:00:00 2001 From: Noah Pendleton Date: Tue, 23 Jan 2024 10:19:45 -0500 Subject: [PATCH 1235/2402] net: sockets: tls: Add error log when cert parse fails Add an error log if there's a failure when attempting to load certificates during socket connect. Signed-off-by: Noah Pendleton --- subsys/net/lib/sockets/sockets_tls.c | 1 + 1 file changed, 1 insertion(+) diff --git a/subsys/net/lib/sockets/sockets_tls.c b/subsys/net/lib/sockets/sockets_tls.c index 513d1f68c73..ae64464f46c 100644 --- a/subsys/net/lib/sockets/sockets_tls.c +++ b/subsys/net/lib/sockets/sockets_tls.c @@ -974,6 +974,7 @@ static int tls_add_ca_certificate(struct tls_context *tls, } if (err != 0) { + NET_ERR("Failed to parse CA certificate, err: -0x%x", -err); return -EINVAL; } From 3c3ac732ad519766b2d63c6cf1c4fe758df01e1c Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Thu, 14 Mar 2024 14:51:59 -0500 Subject: [PATCH 1236/2402] west.yml: Pull in the NXP HAL changes for MCX Flash support Get HAL changes to add MCX Flash support Signed-off-by: Mahesh Mahadevan --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 6dd472de8b8..7cfc6a23391 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 3c4f74b405ca174fe3eb5f3b74c355376ee9a69f + revision: fca2c47e874b940bfea5f5f6d6ee725674c81842 path: modules/hal/nxp groups: - hal From 84febc392969b1edb63ed84b4e5dbb88e4341c9f Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Mon, 6 Mar 2023 13:48:43 -0600 Subject: [PATCH 1237/2402] dts: Add support for MCX internal flash Add support for internal flash Signed-off-by: Mahesh Mahadevan --- dts/arm/nxp/nxp_mcxn94x_common.dtsi | 2 +- dts/bindings/flash_controller/nxp,iap-msf1.yaml | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) create mode 100644 dts/bindings/flash_controller/nxp,iap-msf1.yaml diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi index 6b32d7823e3..aa982c21388 100644 --- a/dts/arm/nxp/nxp_mcxn94x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi @@ -512,7 +512,7 @@ }; fmu: flash-controller@43000 { - compatible = "nxp,iap-mcx"; + compatible = "nxp,iap-msf1"; reg = <0x43000 0x1000>; interrupts = <138 0>; status = "disabled"; diff --git a/dts/bindings/flash_controller/nxp,iap-msf1.yaml b/dts/bindings/flash_controller/nxp,iap-msf1.yaml new file mode 100644 index 00000000000..63eef10a7d7 --- /dev/null +++ b/dts/bindings/flash_controller/nxp,iap-msf1.yaml @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP MSF1 Flash Memory Module (FMU) + +compatible: "nxp,iap-msf1" + +include: flash-controller.yaml From 68ed426751f66224e2c1cbcca8836779d33d74ce Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Mon, 6 Mar 2023 14:28:27 -0600 Subject: [PATCH 1238/2402] drivers: flash: Update mcux driver to add support for MCX flash Add support for the MCX flash Signed-off-by: Mahesh Mahadevan --- drivers/flash/Kconfig.mcux | 3 ++- drivers/flash/soc_flash_mcux.c | 6 +++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/flash/Kconfig.mcux b/drivers/flash/Kconfig.mcux index 52e7220595b..2cf9eac494d 100644 --- a/drivers/flash/Kconfig.mcux +++ b/drivers/flash/Kconfig.mcux @@ -7,7 +7,8 @@ config SOC_FLASH_MCUX DT_HAS_NXP_KINETIS_FTFE_ENABLED || \ DT_HAS_NXP_KINETIS_FTFL_ENABLED || \ DT_HAS_NXP_IAP_FMC55_ENABLED || \ - DT_HAS_NXP_IAP_FMC553_ENABLED + DT_HAS_NXP_IAP_FMC553_ENABLED || \ + DT_HAS_NXP_IAP_MSF1_ENABLED select FLASH_HAS_PAGE_LAYOUT select FLASH_HAS_DRIVER_ENABLED select MPU_ALLOW_FLASH_WRITE if ARM_MPU diff --git a/drivers/flash/soc_flash_mcux.c b/drivers/flash/soc_flash_mcux.c index f3f4059da44..16e75698d5d 100644 --- a/drivers/flash/soc_flash_mcux.c +++ b/drivers/flash/soc_flash_mcux.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2016 Linaro Limited + * Copyright 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -33,6 +34,9 @@ LOG_MODULE_REGISTER(flash_mcux); #elif DT_NODE_HAS_STATUS(DT_INST(0, nxp_iap_fmc553), okay) #define DT_DRV_COMPAT nxp_iap_fmc553 #define SOC_HAS_IAP 1 +#elif DT_NODE_HAS_STATUS(DT_INST(0, nxp_iap_msf1), okay) +#define DT_DRV_COMPAT nxp_iap_msf1 +#define SOC_HAS_IAP_MSF1 1 #else #error No matching compatible for soc_flash_mcux.c #endif @@ -293,7 +297,7 @@ static int flash_mcux_init(const struct device *dev) rc = FLASH_Init(&priv->config); -#ifdef SOC_HAS_IAP +#if defined(SOC_HAS_IAP) || defined(SOC_HAS_IAP_MSF1) FLASH_GetProperty(&priv->config, kFLASH_PropertyPflashBlockBaseAddr, &pflash_block_base); #else From ee3db01d1ae858803c5ab533105534acca7dd97c Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Thu, 14 Mar 2024 13:25:34 -0500 Subject: [PATCH 1239/2402] boards: frdm_mcxn947: Add MCUboot support Add support for MCUboot running from internal flash. Remove the MCUboot conditional check. Signed-off-by: Mahesh Mahadevan --- boards/nxp/frdm_mcxn947/board.c | 3 --- boards/nxp/frdm_mcxn947/doc/index.rst | 2 ++ boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 25 +++++++++++++++++++ .../frdm_mcxn947_mcxn947_cpu0.dts | 1 + 4 files changed, 28 insertions(+), 3 deletions(-) diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index 89b57008207..40b3d42fc74 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -48,8 +48,6 @@ void power_mode_od(void) static int frdm_mcxn947_init(void) { - /* Do not re-run this clock init code if using MCUBoot */ -#ifndef CONFIG_BOOTLOADER_MCUBOOT enable_lpcac(); power_mode_od(); @@ -87,7 +85,6 @@ static int frdm_mcxn947_init(void) /* Set AHBCLKDIV divider to value 1 */ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); -#endif /* CONFIG_BOOTLOADER_MCUBOOT */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay) CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u); diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index 3ba8cf4c98f..171e49eca43 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -61,6 +61,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | CLOCK | on-chip | clock_control | +-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ Targets available ================== diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index b7b0f94207d..97b140c14dc 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -63,3 +63,28 @@ &os_timer { status = "okay"; }; + +&flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 DT_SIZE_K(960)>; + }; + slot1_partition: partition@100000 { + label = "image-1"; + reg = <0x00100000 DT_SIZE_K(960)>; + }; + scratch_partition: partition@1f0000 { + label = "image-scratch"; + reg = <0x001f0000 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts index 331bacf00e6..f69157e4b6f 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts @@ -21,6 +21,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash; zephyr,flash-controller = &fmu; + zephyr,code-partition = &slot0_partition; zephyr,console = &flexcomm4_lpuart4; zephyr,shell-uart = &flexcomm4_lpuart4; }; From e25c68be5dcced3ced2a6269df8e47c8921a8235 Mon Sep 17 00:00:00 2001 From: Kapil Bhatt Date: Fri, 22 Mar 2024 15:24:38 +0530 Subject: [PATCH 1240/2402] net: wifi: Set default values of dwell time Dwell time Active or Passive is optional in wifi scan. If user don't set the Dwell time value, it will be set as 0. We are adding a range check in scan extensions for dwell time. So need to set default values. Signed-off-by: Kapil Bhatt --- subsys/net/l2/wifi/wifi_shell.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index a2e6df39256..92afbc368bd 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -764,7 +764,7 @@ static int wifi_scan_args_to_params(const struct shell *sh, static int cmd_wifi_scan(const struct shell *sh, size_t argc, char *argv[]) { struct net_if *iface = net_if_get_first_wifi(); - struct wifi_scan_params params = { 0 }; + struct wifi_scan_params params = { .dwell_time_active = 50, .dwell_time_passive = 130, }; bool do_scan = true; int opt_num; From 37a1d28a36aecbfd2f5f054230462e8df45777f0 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 22 Mar 2024 16:25:48 +0100 Subject: [PATCH 1241/2402] Revert "scripts: remove board name from the qualifiers in list_boards.py" This reverts commit 66b475a3aa4d73f4ddd5be5a7a1e0f3c7028e539. This commit has broken CI. Let's revert it. See https://github.com/zephyrproject-rtos/zephyr/issues/70614 Signed-off-by: Alberto Escolar Piedras --- cmake/modules/boards.cmake | 8 +++----- scripts/ci/check_compliance.py | 3 +-- scripts/list_boards.py | 18 +++++++++++------- .../completion/west-completion.bash | 9 ++------- .../completion/west-completion.fish | 19 +++++++++++++------ .../completion/west-completion.zsh | 9 +++------ 6 files changed, 33 insertions(+), 33 deletions(-) diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index ee81b264c1f..63e2b7af4cc 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -285,14 +285,12 @@ elseif(HWMv2) string(REGEX REPLACE "^//" "/${LIST_BOARD_SOCS}/" BOARD_QUALIFIERS "${BOARD_QUALIFIERS}") endif() - set(board_targets ${LIST_BOARD_QUALIFIERS}) - list(TRANSFORM board_targets PREPEND "${BOARD}/") - if(NOT ("${BOARD}${BOARD_QUALIFIERS}" IN_LIST board_targets)) - string(REPLACE ";" "\n" board_targets "${board_targets}") + if(NOT ("${BOARD}${BOARD_QUALIFIERS}" IN_LIST LIST_BOARD_QUALIFIERS)) + string(REPLACE ";" "\n" LIST_BOARD_QUALIFIERS "${LIST_BOARD_QUALIFIERS}") unset(CACHED_BOARD CACHE) message(FATAL_ERROR "Board qualifiers `${BOARD_QUALIFIERS}` for board \ `${BOARD}` not found. Please specify a valid board target.\n" - "Valid board targets for ${BOARD_NAME} are:\n${board_targets}\n") + "Valid board qualifiers for ${BOARD_NAME} are:\n${LIST_BOARD_QUALIFIERS}\n") endif() endif() else() diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index a77bd580453..c351643401c 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -449,8 +449,7 @@ def get_v2_model(self, kconfig_dir): fp.write('config ' + board_str + '\n') fp.write('\t bool\n') for qualifier in list_boards.board_v2_qualifiers(board): - board_str = ('BOARD_' + board.name + '_' + - re.sub(r"[^a-zA-Z0-9_]", "_", qualifier)).upper() + board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", qualifier).upper() fp.write('config ' + board_str + '\n') fp.write('\t bool\n') fp.write( diff --git a/scripts/list_boards.py b/scripts/list_boards.py index 5321f31b0bc..03b1adaca83 100755 --- a/scripts/list_boards.py +++ b/scripts/list_boards.py @@ -275,10 +275,10 @@ def add_args_formatting(parser): help='''CMake Format string to use to list each board''') -def variant_v2_qualifiers(variant, qualifiers = None): - qualifiers_list = [variant.name] if qualifiers is None else [qualifiers + '/' + variant.name] +def variant_v2_qualifiers(variant, qualifiers): + qualifiers_list = [qualifiers + '/' + variant.name] for v in variant.variants: - qualifiers_list.extend(variant_v2_qualifiers(v, qualifiers_list[0])) + qualifiers_list.extend(variant_v2_qualifiers(v, qualifiers + '/' + variant.name)) return qualifiers_list @@ -288,17 +288,21 @@ def board_v2_qualifiers(board): for s in board.socs: if s.cpuclusters: for c in s.cpuclusters: - id_str = s.name + '/' + c.name + id_str = board.name + '/' + s.name + '/' + c.name qualifiers_list.append(id_str) for v in c.variants: qualifiers_list.extend(variant_v2_qualifiers(v, id_str)) else: - qualifiers_list.append(s.name) + id_str = board.name + '/' + s.name + qualifiers_list.append(id_str) for v in s.variants: - qualifiers_list.extend(variant_v2_qualifiers(v, s.name)) + qualifiers_list.extend(variant_v2_qualifiers(v, id_str)) + + if not board.socs: + qualifiers_list.append(board.name) for v in board.variants: - qualifiers_list.extend(variant_v2_qualifiers(v)) + qualifiers_list.extend(variant_v2_qualifiers(v, board.name)) return qualifiers_list diff --git a/scripts/west_commands/completion/west-completion.bash b/scripts/west_commands/completion/west-completion.bash index d812e8933b1..2ccc4446ad3 100644 --- a/scripts/west_commands/completion/west-completion.bash +++ b/scripts/west_commands/completion/west-completion.bash @@ -392,13 +392,8 @@ __set_comp_west_projs() __set_comp_west_boards() { - boards=( $(__west_x boards --format='{name}|{qualifiers}' "$@") ) - for i in ${!boards[@]}; do - name="${boards[$i]%%|*}" - transformed_board="${boards[$i]//|//}" - boards[$i]="${transformed_board//,/\ ${name}\/}" - done - __set_comp ${boards[@]} + boards="$(__west_x boards --format={identifiers} "$@")\n$(__west_x boards --format={name} "$@")" + __set_comp ${boards//,/\ } } __comp_west_west() diff --git a/scripts/west_commands/completion/west-completion.fish b/scripts/west_commands/completion/west-completion.fish index 51e61141e8a..33c6942dd8e 100644 --- a/scripts/west_commands/completion/west-completion.fish +++ b/scripts/west_commands/completion/west-completion.fish @@ -196,12 +196,19 @@ function __zephyr_west_complete_help end function __zephyr_west_complete_board - set -l boards (west 2>/dev/null boards --format="{name}|{qualifiers}") + # HWMv1 + set -l boards (west 2>/dev/null boards --format="{name} {arch}") for board in $boards - set -l b (string split "|" $board) - set -l qualifiers (string split "," $b[2]) - for i in $qualifiers - printf "%s\n" $b[1]/$i + set -l b (string split " " $board) + printf "%s\n" $b[1]\t"$b[2]" + end + + # HWMv2 + set -l boards (west 2>/dev/null boards --format="{identifiers}") + for board in $boards + set -l b (string split "," $board) + for variant in $b + printf "%s\n" $variant[1] end end end @@ -300,7 +307,7 @@ complete -c west -n "__zephyr_west_seen_subcommand_from boards" -l soc-root -xa # build complete -c west -n "__zephyr_west_use_subcommand; and __zephyr_west_check_if_in_workspace" -ra build -d "compile a Zephyr application" complete -c west -n "__zephyr_west_seen_subcommand_from build" -ra "(__zephyr_west_complete_directories)" -complete -c west -n "__zephyr_west_seen_subcommand_from build" -o b -l board -xa "(__zephyr_west_complete_board)" +complete -c west -n "__zephyr_west_seen_subcommand_from build" -o b -l board -xa "(__zephyr_west_complete_board)" -d "board to build for" complete -c west -n "__zephyr_west_seen_subcommand_from build" -o d -l build-dir -xa "(__zephyr_west_complete_directories)" -d "build directory to create or use" complete -c west -n "__zephyr_west_seen_subcommand_from build" -o f -l force -d "ignore errors and continue" complete -c west -n "__zephyr_west_seen_subcommand_from build" -l sysbuild -d "create multi-domain build system" diff --git a/scripts/west_commands/completion/west-completion.zsh b/scripts/west_commands/completion/west-completion.zsh index e1a01199884..000b43a87b3 100644 --- a/scripts/west_commands/completion/west-completion.zsh +++ b/scripts/west_commands/completion/west-completion.zsh @@ -102,12 +102,9 @@ _get_west_projs() { } _get_west_boards() { - _west_boards=( $(__west_x boards --format='{name}|{qualifiers}') ) - for i in {1..${#_west_boards[@]}}; do - local name="${_west_boards[$i]%%|*}" - local transformed_board="${_west_boards[$i]//|//}" - _west_boards[$i]="${transformed_board//,/ ${name}/}" - done + _west_boards="$(__west_x boards --format={identifiers})\n$(__west_x boards --format={name})" + _west_boards=${_west_boards//$'\n'/\ } + _west_boards=${_west_boards//,/\ } _west_boards=(${(@s/ /)_west_boards}) _describe 'boards' _west_boards From e2f38403800278a48bea67ab977aa557f80284ba Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Thu, 14 Mar 2024 15:17:51 -0700 Subject: [PATCH 1242/2402] kernel: Fix possible overflow in k_mem_map k_mem_map additionally allocates two guard pages that are not mapped. These pages are not being accounted when checking the provided size and when they are added an overflow can happen and the mapped memory is not correct. Signed-off-by: Flavio Ceolin --- kernel/mmu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/kernel/mmu.c b/kernel/mmu.c index cef9b5c18d2..eda0c50a255 100644 --- a/kernel/mmu.c +++ b/kernel/mmu.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); @@ -575,6 +577,11 @@ void *k_mem_map(size_t size, uint32_t flags) __ASSERT((flags & K_MEM_CACHE_MASK) == 0U, "%s does not support explicit cache settings", __func__); + CHECKIF(size_add_overflow(size, CONFIG_MMU_PAGE_SIZE * 2, &total_size)) { + LOG_ERR("too large size %zu passed to %s", size, __func__); + return NULL; + } + key = k_spin_lock(&z_mm_lock); /* Need extra for the guard pages (before and after) which we From 0f5c08548adf421de89e5c6903c71ee725679b9a Mon Sep 17 00:00:00 2001 From: Michal Smola Date: Mon, 11 Mar 2024 12:13:12 +0100 Subject: [PATCH 1243/2402] twister: qemu: fix mps2_an521 on Windows tfm_integration samples fail on Windows on mps2_an521 platform, because output from ninja process running QEMU freezes in re-build phase. Fix it by implementing named pipes to read output from QEMU process directly using os.open and os.read methods. Signed-off-by: Michal Smola --- scripts/pylib/twister/twisterlib/handlers.py | 49 ++++++++++++------- .../pylib/twister/twisterlib/testinstance.py | 5 +- 2 files changed, 34 insertions(+), 20 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py index a2cd97d8079..8a732f28ad4 100755 --- a/scripts/pylib/twister/twisterlib/handlers.py +++ b/scripts/pylib/twister/twisterlib/handlers.py @@ -1050,15 +1050,13 @@ def get_fifo(self): class QEMUWinHandler(Handler): - """Spawns a thread to monitor QEMU output on Windows OS + """Spawns a thread to monitor QEMU output from pipes on Windows OS - We redirect subprocess output to pipe and monitor the pipes for output. - We need to do this as once qemu starts, it runs forever until killed. - Test cases emit special messages to the console as they run, we check - for these to collect whether the test passed or failed. - The pipe includes also messages from ninja command which is used for - running QEMU. - """ + QEMU creates single duplex pipe at //.pipe/path, where path is fifo_fn. + We need to do this as once qemu starts, it runs forever until killed. + Test cases emit special messages to the console as they run, we check + for these to collect whether the test passed or failed. + """ def __init__(self, instance, type_str): """Constructor @@ -1068,6 +1066,8 @@ def __init__(self, instance, type_str): super().__init__(instance, type_str) self.pid_fn = os.path.join(instance.build_dir, "qemu.pid") + self.fifo_fn = os.path.join(instance.build_dir, "qemu-fifo") + self.pipe_handle = None self.pid = 0 self.thread = None self.stop_thread = False @@ -1109,6 +1109,8 @@ def _stop_qemu_process(pid): except (ProcessLookupError, psutil.NoSuchProcess): # Oh well, as long as it's dead! User probably sent Ctrl-C pass + except OSError: + pass @staticmethod def _monitor_update_instance_info(handler, handler_time, out_state): @@ -1165,15 +1167,21 @@ def _update_instance_info(self, harness_state, is_timeout): self.instance.reason = "Exited with {}".format(self.returncode) self.instance.add_missing_case_status("blocked") - def _enqueue_char(self, stdout, queue): + def _enqueue_char(self, queue): while not self.stop_thread: + if not self.pipe_handle: + try: + self.pipe_handle = os.open(r"\\.\pipe\\" + self.fifo_fn, os.O_RDONLY) + except FileNotFoundError as e: + if e.args[0] == 2: + # Pipe is not opened yet, try again after a delay. + time.sleep(1) + continue + + c = "" try: - c = stdout.read(1) - except ValueError: - # Reading on closed file exception can occur when subprocess is killed. - # Can be ignored. - pass - else: + c = os.read(self.pipe_handle, 1) + finally: queue.put(c) def _monitor_output(self, queue, timeout, logfile, pid_fn, harness, ignore_unexpected_eof=False): @@ -1283,10 +1291,11 @@ def handle(self, harness): self.stop_thread = False queue = Queue() - with subprocess.Popen(command, stdout=subprocess.PIPE, stderr=subprocess.PIPE, cwd=self.build_dir) as proc: + with subprocess.Popen(command, stdout=subprocess.DEVNULL, stderr=subprocess.STDOUT, + cwd=self.build_dir) as proc: logger.debug("Spawning QEMUHandler Thread for %s" % self.name) - self.thread = threading.Thread(target=self._enqueue_char, args=(proc.stdout, queue)) + self.thread = threading.Thread(target=self._enqueue_char, args=(queue,)) self.thread.daemon = True self.thread.start() @@ -1312,6 +1321,12 @@ def handle(self, harness): logger.debug(f"return code from QEMU ({self.pid}): {self.returncode}") + os.close(self.pipe_handle) + self.pipe_handle = None + self._update_instance_info(harness.state, is_timeout) self._final_handle_actions(harness, 0) + + def get_fifo(self): + return self.fifo_fn diff --git a/scripts/pylib/twister/twisterlib/testinstance.py b/scripts/pylib/twister/twisterlib/testinstance.py index 5f00cbe901a..5ec183a6a87 100644 --- a/scripts/pylib/twister/twisterlib/testinstance.py +++ b/scripts/pylib/twister/twisterlib/testinstance.py @@ -181,11 +181,10 @@ def setup_handler(self, env): if self.platform.simulation == "qemu": if os.name != "nt": handler = QEMUHandler(self, "qemu") - handler.args.append(f"QEMU_PIPE={handler.get_fifo()}") - handler.ready = True else: handler = QEMUWinHandler(self, "qemu") - handler.ready = True + handler.args.append(f"QEMU_PIPE={handler.get_fifo()}") + handler.ready = True else: handler = SimulationHandler(self, self.platform.simulation) From 06f6c5c992a2ac707e449707ff6283478d449d89 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Thu, 21 Mar 2024 18:29:37 +0100 Subject: [PATCH 1244/2402] doc: bsim: Move contents into .rst This makes the information more discoverable and linkable in the docs. Signed-off-by: Jonathan Rico --- doc/develop/test/bsim.rst | 104 ++++++++++++++++++++++++++++++++++++-- tests/bsim/README.md | 96 ----------------------------------- 2 files changed, 99 insertions(+), 101 deletions(-) delete mode 100644 tests/bsim/README.md diff --git a/doc/develop/test/bsim.rst b/doc/develop/test/bsim.rst index bc94d6b1e21..a7a97cef3a1 100644 --- a/doc/develop/test/bsim.rst +++ b/doc/develop/test/bsim.rst @@ -29,7 +29,7 @@ Types of tests ************** Tests without radio activity: bsim tests with twister ------------------------------------------------------ +===================================================== The :ref:`bsim boards` can be used without radio activity, and in that case, it is not necessary to connect them to a physical layer simulation. Thanks to this, these target boards can @@ -37,16 +37,20 @@ be used just like :ref:`native_sim` with :ref:`twister ` for more info. .. _EDTT: https://github.com/EDTTool/EDTT + +Building and running the tests +****************************** + +See the :ref:`nrf52_bsim` page for setting up the simulator. + +The scripts also expect a few environment variables to be set. +For example, from Zephyr's root folder, you can run: + +.. code-block:: bash + + # Build all the tests + ${ZEPHYR_BASE}/tests/bsim/compile.sh + + # Run them (in parallel) + RESULTS_FILE=${ZEPHYR_BASE}/myresults.xml \ + SEARCH_PATH=${ZEPHYR_BASE}/tests/bsim \ + ${ZEPHYR_BASE}/tests/bsim/run_parallel.sh + +Or to build and run only a specific subset, e.g. host advertising tests: + +.. code-block:: bash + + # Build the Bluetooth host advertising tests + ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/adv/compile.sh + + # Run them (in parallel) + RESULTS_FILE=${ZEPHYR_BASE}/myresults.xml \ + SEARCH_PATH=${ZEPHYR_BASE}/tests/bsim/bluetooth/host/adv \ + ${ZEPHYR_BASE}/tests/bsim/run_parallel.sh + +Check the ``run_parallel.sh`` help for more options and examples on how to use this script to run +the tests in batch. + +After building the tests' required binaries you can run a test directly using its individual test +script. + +For example you can build the required binaries for the networking tests with + +.. code-block:: bash + + WORK_DIR=${ZEPHYR_BASE}/bsim_out ${ZEPHYR_BASE}/tests/bsim/net/compile.sh + +and then directly run one of the tests: + +.. code-block:: bash + + ${ZEPHYR_BASE}/tests/bsim/net/sockets/echo_test/tests_scripts/echo_test_802154.sh + +Conventions +=========== + +Build scripts +------------- + +The build scripts ``compile.sh`` simply build all the required test and sample applications +for the tests' scripts placed in the subfolders below. + +This build scripts use the common compile.source which provide a function (compile) which calls +cmake and ninja with the provided application, configuration and overlay files. + +To speed up compilation for users interested only in a subset of tests, several compile scripts +exist in several subfolders, where the upper ones call into the lower ones. + +Note that cmake and ninja are used directly instead of the ``west build`` wrapper as west is not +required, and some Zephyr users do not use or have west, but still use the build and tests scripts. + +Test scripts +------------ + +- Each test is defined by a shell script with the extension ``.sh``. +- Scripts starting with an underscore (``_``) are ignored. +- Test scripts expect that the binaries they require are already built, and will spawn the processes + for the simulated devices and physical layer simulation with the necessary command line options. +- Tests must return 0 to the invoking shell if the test passes, and not 0 if the test fails. +- It is recommended to have a single test for each test script. +- Each test must have a unique simulation id, to enable running different tests in parallel. +- The test scripts should not compile the images on their own. +- Neither the scripts nor the images should modify the workstation filesystem content beyond the + ``${BSIM_OUT_PATH}/results//`` or ``/tmp/`` folders. + That is, they should not leave stray files behind. +- If the test scripts or the test binaries create temporary files, they should preferably do so by + placing them in the ``${BSIM_OUT_PATH}/results//`` folder. + Otherwise they should be named as to avoid conflicts with other test scripts which may be running + in parallel. +- When running tests that require several consecutive simulations, for ex. if simulating a device + pairing, powering off, and powering up after as a new simulation, + they should strive for using separate simulation ids for each simulation part, + in that way ensuring that the simulation radio activity of each segment can be inspected a + posteriori. diff --git a/tests/bsim/README.md b/tests/bsim/README.md deleted file mode 100644 index 1f3894f331d..00000000000 --- a/tests/bsim/README.md +++ /dev/null @@ -1,96 +0,0 @@ -This folder contains tests meant to be run with BabbleSim's physical layer -simulation, and therefore cannot be run directly from twister. - -The compile.sh and run_parallel.sh scripts are used by the CI system to build -the needed images and execute these tests in batch. - -You can also run them manually if desired, but be sure to call them setting -the variables they expect. For example, from Zephyr's root folder, you can run: - -``` -WORK_DIR=${ZEPHYR_BASE}/bsim_out tests/bsim/compile.sh -RESULTS_FILE=${ZEPHYR_BASE}/myresults.xml SEARCH_PATH=tests/bsim tests/bsim/run_parallel.sh -``` - -Or to run only a specific subset, e.g. host advertising tests: - -``` -WORK_DIR=${ZEPHYR_BASE}/bsim_out tests/bsim/bluetooth/host/compile.sh -RESULTS_FILE=${ZEPHYR_BASE}/myresults.xml \ -SEARCH_PATH=tests/bsim/bluetooth/host/adv tests/bsim/run_parallel.sh -``` - -Check the run_parallel.sh help for more options and examples on how to use this script to run these -tests in batch. - -After building the tests' required binaries you can run a test directly with its individual -test scripts. - -For example you can build the required binaries for the networking tests with - -``` -WORK_DIR=${ZEPHYR_BASE}/bsim_out tests/bsim/net/compile.sh -``` -and then directly run one of the tests: - -``` -tests/bsim/net/sockets/echo_test/tests_scripts/echo_test_802154.sh -``` - - -Generating coverage reports ---------------------------- - -You can use `tests/bsim/generate_coverage_report.sh` to generate a coverage report -of the BabbleSim tests which have been run. Check its help for more info. - - -Conventions about these tests scripts -------------------------------------- - -Each test is defined by a shell script with the extension `.sh`. -Scripts starting with an underscore (`_`) are ignored. - -Each of these test scripts expects the binaries their require already built, and will execute -the required simulated devices and physical layer simulation with the required command line -options. - -Tests must return 0 to the invoking shell if the test passes, and not 0 if the test -fails. - -It is recommended to have a single test for each test script. - -Each test must have a unique simulation id, to enable running different tests in parallel. - -These scripts should not compile the images on their own. - -Neither the scripts nor the images should modify the workstation filesystem content beyond the -`${BSIM_OUT_PATH}/results//` or `/tmp/` folders. -That is, they should not leave straneous files behind. - -If these scripts or the test binaries create temporary files, they should preferably do so by -placing them in the `${BSIM_OUT_PATH}/results//` folder. -Otherwise they should be named as to avoid conflicts with other test scripts which may be running -in parallel. - -When running tests that require several consecutive simulations, for ex. if simulating a device -pairing, powering off, and powering up after as a new simulation, -they should strive for using separate simulation ids for each simulation part, -in that way ensuring that the simulation radio activity of each segment can be inspected a -posteriori. - - -Conventions about the build scripts ------------------------------------ - -The build scripts (compile.sh) simply build all the required test and sample applications -for the tests' scripts placed in the subfolders below. - -This build scripts use the common compile.source which provide a function (compile) which calls -cmake and ninja with the provided application, configuration and overlay files. - -To speed up compilation for users interested only in a subset of tests, several compile scripts -exist in several subfolders, where the upper ones call into the lower ones. - -Note that cmake and ninja are used directly instead of the `west build` wrapper as west is not -required, and some Zephyr users do not use or have west, but still use this build and tests scripts. From d36dd8097e2659bb74c846527bfc6b6ef595e03f Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Wed, 20 Mar 2024 18:02:34 -0400 Subject: [PATCH 1245/2402] posix: clock: implement clock_getres() clock_getres() is required by the POSIX_TIMERS Option Group as detailed in Section E.1 of IEEE-1003.1-2017. The POSIX_TIMERS Option Group is required for PSE51, PSE52, PSE53, and PSE54 conformance, and is otherwise mandatory for any POSIX conforming system as per Section A.2.1.3 of IEEE-1003-1.2017. With this, we have complete support for the POSIX_TIMERS Option Group. Signed-off-by: Christopher Friedt --- include/zephyr/posix/time.h | 1 + lib/posix/options/clock.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/include/zephyr/posix/time.h b/include/zephyr/posix/time.h index 417923c4377..8038e783030 100644 --- a/include/zephyr/posix/time.h +++ b/include/zephyr/posix/time.h @@ -87,6 +87,7 @@ static inline int32_t _ts_to_ms(const struct timespec *to) } int clock_gettime(clockid_t clock_id, struct timespec *ts); +int clock_getres(clockid_t clock_id, struct timespec *ts); int clock_settime(clockid_t clock_id, const struct timespec *ts); int clock_getcpuclockid(pid_t pid, clockid_t *clock_id); /* Timer APIs */ diff --git a/lib/posix/options/clock.c b/lib/posix/options/clock.c index a8835a44248..48789ae49c2 100644 --- a/lib/posix/options/clock.c +++ b/lib/posix/options/clock.c @@ -97,6 +97,28 @@ int clock_gettime(clockid_t clock_id, struct timespec *ts) return 0; } +int clock_getres(clockid_t clock_id, struct timespec *res) +{ + BUILD_ASSERT(CONFIG_SYS_CLOCK_TICKS_PER_SEC > 0 && + CONFIG_SYS_CLOCK_TICKS_PER_SEC <= NSEC_PER_SEC, + "CONFIG_SYS_CLOCK_TICKS_PER_SEC must be > 0 and <= NSEC_PER_SEC"); + + if (!(clock_id == CLOCK_MONOTONIC || clock_id == CLOCK_REALTIME || + clock_id == CLOCK_PROCESS_CPUTIME_ID)) { + errno = EINVAL; + return -1; + } + + if (res != NULL) { + *res = (struct timespec){ + .tv_sec = 0, + .tv_nsec = NSEC_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC, + }; + } + + return 0; +} + /** * @brief Set the time of the specified clock. * From 0084092faee8dd1ce323eb1de02a68fbe7a37317 Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Wed, 20 Mar 2024 18:06:01 -0400 Subject: [PATCH 1246/2402] tests: posix: add a test for clock_getres() Add a test for clock_getres(). Signed-off-by: Christopher Friedt --- tests/posix/common/src/clock.c | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tests/posix/common/src/clock.c b/tests/posix/common/src/clock.c index 07a825434c5..bb7a6729b5a 100644 --- a/tests/posix/common/src/clock.c +++ b/tests/posix/common/src/clock.c @@ -227,4 +227,48 @@ ZTEST(clock, test_clock_getcpuclockid) zassert_equal(ret, EPERM, "POSIX clock_getcpuclock id failed"); } +ZTEST(clock, test_clock_getres) +{ + int ret; + struct timespec res; + const struct timespec one_ns = { + .tv_sec = 0, + .tv_nsec = 1, + }; + + struct arg { + clockid_t clock_id; + struct timespec *res; + int expect; + }; + + const struct arg args[] = { + /* permuting over "invalid" inputs */ + {CLOCK_INVALID, NULL, -1}, + {CLOCK_INVALID, &res, -1}, + {CLOCK_REALTIME, NULL, 0}, + {CLOCK_MONOTONIC, NULL, 0}, + {CLOCK_PROCESS_CPUTIME_ID, NULL, 0}, + + /* all valid inputs */ + {CLOCK_REALTIME, &res, 0}, + {CLOCK_MONOTONIC, &res, 0}, + {CLOCK_PROCESS_CPUTIME_ID, &res, 0}, + }; + + ARRAY_FOR_EACH_PTR(args, arg) { + errno = 0; + res = (struct timespec){0}; + ret = clock_getres(arg->clock_id, arg->res); + zassert_equal(ret, arg->expect); + if (ret != 0) { + zassert_equal(errno, EINVAL); + continue; + } + if (arg->res != NULL) { + zassert_true(tp_ge(arg->res, &one_ns)); + } + } +} + ZTEST_SUITE(clock, NULL, NULL, NULL, NULL, NULL); From 457e44073b8d7dae9164c8bff73d9f443c39fcb7 Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Wed, 20 Mar 2024 18:09:37 -0400 Subject: [PATCH 1247/2402] doc: posix: mark clock_getres() as supported Mark clock_getres() as supported in the POSIX_TIMERS Option Group. Signed-off-by: Christopher Friedt --- doc/services/portability/posix/option_groups/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst index 079f631a3e1..6a241266b2f 100644 --- a/doc/services/portability/posix/option_groups/index.rst +++ b/doc/services/portability/posix/option_groups/index.rst @@ -332,7 +332,7 @@ POSIX_TIMERS :header: API, Supported :widths: 50,10 - clock_getres(), + clock_getres(),yes clock_gettime(),yes clock_settime(),yes nanosleep(),yes From 61c41399256e6e75df794d2338be8d2b75d5a1d8 Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Tue, 19 Mar 2024 06:03:16 -0400 Subject: [PATCH 1248/2402] posix: rwlock: pthread_rwlockattr_init / destroy in lib Move the implementation of the following functions into the posix library rather than having themn as static inline functions. * pthread_rwlockattr_init() * pthread_rwlockattr_destroy() Signed-off-by: Christopher Friedt --- include/zephyr/posix/pthread.h | 12 ++---------- lib/posix/options/rwlock.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 10 deletions(-) diff --git a/include/zephyr/posix/pthread.h b/include/zephyr/posix/pthread.h index 7ffdb1318d8..e7bc422b358 100644 --- a/include/zephyr/posix/pthread.h +++ b/include/zephyr/posix/pthread.h @@ -390,22 +390,14 @@ int pthread_equal(pthread_t pt1, pthread_t pt2); * * See IEEE 1003.1 */ -static inline int pthread_rwlockattr_destroy(pthread_rwlockattr_t *attr) -{ - ARG_UNUSED(attr); - return 0; -} +int pthread_rwlockattr_destroy(pthread_rwlockattr_t *attr); /** * @brief initialize the read-write lock attributes object. * * See IEEE 1003.1 */ -static inline int pthread_rwlockattr_init(pthread_rwlockattr_t *attr) -{ - ARG_UNUSED(attr); - return 0; -} +int pthread_rwlockattr_init(pthread_rwlockattr_t *attr); int pthread_attr_getguardsize(const pthread_attr_t *ZRESTRICT attr, size_t *ZRESTRICT guardsize); int pthread_attr_getstacksize(const pthread_attr_t *attr, size_t *stacksize); diff --git a/lib/posix/options/rwlock.c b/lib/posix/options/rwlock.c index 34d10c6dfa6..27906ecf3a0 100644 --- a/lib/posix/options/rwlock.c +++ b/lib/posix/options/rwlock.c @@ -21,6 +21,10 @@ struct posix_rwlock { k_tid_t wr_owner; }; +struct posix_rwlockattr { + bool initialized: 1; +}; + int64_t timespec_to_timeoutms(const struct timespec *abstime); static uint32_t read_lock_acquire(struct posix_rwlock *rwl, int32_t timeout); static uint32_t write_lock_acquire(struct posix_rwlock *rwl, int32_t timeout); @@ -384,3 +388,31 @@ static uint32_t write_lock_acquire(struct posix_rwlock *rwl, int32_t timeout) } return ret; } + +int pthread_rwlockattr_init(pthread_rwlockattr_t *attr) +{ + struct posix_rwlockattr *const a = (struct posix_rwlockattr *)attr; + + if (a == NULL) { + return EINVAL; + } + + *a = (struct posix_rwlockattr){ + .initialized = true, + }; + + return 0; +} + +int pthread_rwlockattr_destroy(pthread_rwlockattr_t *attr) +{ + struct posix_rwlockattr *const a = (struct posix_rwlockattr *)attr; + + if (a == NULL || !a->initialized) { + return EINVAL; + } + + *a = (struct posix_rwlockattr){0}; + + return 0; +} From 1847280fb443a6093cbcccc87c91af1e48db1f93 Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Tue, 19 Mar 2024 06:11:27 -0400 Subject: [PATCH 1249/2402] posix: rwlock: implement pthread_rwlockattr_setpshared Implement pthread_rwlockattr_setpshared() and pthread_rwlockattr_getpshared(). Both functions are required by the _POSIX_READER_WRITER_LOCKS Option as detailed in Section E.1 of IEEE-1003.1-2017. The _POSIX_READER_WRITER_LOCKS Option is required for PSE51, PSE52, PSE53, and PSE54 conformance, and is otherwise mandatory for any POSIX conforming system as per Section A.2.1.3 of IEEE-1003-1.2017. Signed-off-by: Christopher Friedt --- include/zephyr/posix/pthread.h | 4 ++++ lib/posix/options/rwlock.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/include/zephyr/posix/pthread.h b/include/zephyr/posix/pthread.h index e7bc422b358..eb786f80e19 100644 --- a/include/zephyr/posix/pthread.h +++ b/include/zephyr/posix/pthread.h @@ -399,6 +399,10 @@ int pthread_rwlockattr_destroy(pthread_rwlockattr_t *attr); */ int pthread_rwlockattr_init(pthread_rwlockattr_t *attr); +int pthread_rwlockattr_getpshared(const pthread_rwlockattr_t *ZRESTRICT attr, + int *ZRESTRICT pshared); +int pthread_rwlockattr_setpshared(pthread_rwlockattr_t *attr, int pshared); + int pthread_attr_getguardsize(const pthread_attr_t *ZRESTRICT attr, size_t *ZRESTRICT guardsize); int pthread_attr_getstacksize(const pthread_attr_t *attr, size_t *stacksize); int pthread_attr_setguardsize(pthread_attr_t *attr, size_t guardsize); diff --git a/lib/posix/options/rwlock.c b/lib/posix/options/rwlock.c index 27906ecf3a0..b8a91a03232 100644 --- a/lib/posix/options/rwlock.c +++ b/lib/posix/options/rwlock.c @@ -23,6 +23,7 @@ struct posix_rwlock { struct posix_rwlockattr { bool initialized: 1; + bool pshared: 1; }; int64_t timespec_to_timeoutms(const struct timespec *abstime); @@ -389,6 +390,37 @@ static uint32_t write_lock_acquire(struct posix_rwlock *rwl, int32_t timeout) return ret; } +int pthread_rwlockattr_getpshared(const pthread_rwlockattr_t *ZRESTRICT attr, + int *ZRESTRICT pshared) +{ + struct posix_rwlockattr *const a = (struct posix_rwlockattr *)attr; + + if (a == NULL || !a->initialized) { + return EINVAL; + } + + *pshared = a->pshared; + + return 0; +} + +int pthread_rwlockattr_setpshared(pthread_rwlockattr_t *attr, int pshared) +{ + struct posix_rwlockattr *const a = (struct posix_rwlockattr *)attr; + + if (a == NULL || !a->initialized) { + return EINVAL; + } + + if (!(pshared == PTHREAD_PROCESS_PRIVATE || pshared == PTHREAD_PROCESS_SHARED)) { + return EINVAL; + } + + a->pshared = pshared; + + return 0; +} + int pthread_rwlockattr_init(pthread_rwlockattr_t *attr) { struct posix_rwlockattr *const a = (struct posix_rwlockattr *)attr; @@ -399,6 +431,7 @@ int pthread_rwlockattr_init(pthread_rwlockattr_t *attr) *a = (struct posix_rwlockattr){ .initialized = true, + .pshared = PTHREAD_PROCESS_PRIVATE, }; return 0; From a010ad23bd646514e69b361bccf1ef510339ef50 Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Tue, 19 Mar 2024 06:21:55 -0400 Subject: [PATCH 1250/2402] tests: posix: tests for pthread_rwlockattr_setpshared Add tests for pthread_rwlockattr_setpshared() and pthread_rwlockattr_getpshared(). Signed-off-by: Christopher Friedt --- tests/posix/common/src/rwlock.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/tests/posix/common/src/rwlock.c b/tests/posix/common/src/rwlock.c index 44d3cce2971..a7012fc5832 100644 --- a/tests/posix/common/src/rwlock.c +++ b/tests/posix/common/src/rwlock.c @@ -117,6 +117,33 @@ ZTEST(rwlock, test_rw_lock) zassert_ok(pthread_rwlock_destroy(&rwlock), "Failed to destroy rwlock"); } +static void test_pthread_rwlockattr_pshared_common(bool set, int pshared) +{ + int tmp_pshared = 4242; + pthread_rwlockattr_t attr; + + zassert_ok(pthread_rwlockattr_init(&attr)); + zassert_ok(pthread_rwlockattr_getpshared(&attr, &tmp_pshared)); + zassert_equal(tmp_pshared, PTHREAD_PROCESS_PRIVATE); + if (set) { + zassert_ok(pthread_rwlockattr_setpshared(&attr, pshared)); + zassert_ok(pthread_rwlockattr_getpshared(&attr, &tmp_pshared)); + zassert_equal(tmp_pshared, pshared); + } + zassert_ok(pthread_rwlockattr_destroy(&attr)); +} + +ZTEST(rwlock, test_pthread_rwlockattr_getpshared) +{ + test_pthread_rwlockattr_pshared_common(false, 0); +} + +ZTEST(rwlock, test_pthread_rwlockattr_setpshared) +{ + test_pthread_rwlockattr_pshared_common(true, PTHREAD_PROCESS_PRIVATE); + test_pthread_rwlockattr_pshared_common(true, PTHREAD_PROCESS_SHARED); +} + static void before(void *arg) { ARG_UNUSED(arg); From 8de8bcc99c486ccb05faed39869773230be32fa0 Mon Sep 17 00:00:00 2001 From: Christopher Friedt Date: Tue, 19 Mar 2024 06:22:31 -0400 Subject: [PATCH 1251/2402] doc: posix: mark pthread_rwlockattr_setpshared as supported Mark pthread_rwlockattr_setpshared() and pthread_rwlockattr_getpshared() as supported in the POSIX Options documentation. Signed-off-by: Christopher Friedt --- doc/services/portability/posix/conformance/index.rst | 2 +- doc/services/portability/posix/option_groups/index.rst | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/services/portability/posix/conformance/index.rst b/doc/services/portability/posix/conformance/index.rst index b2c46529246..2b2e687d94e 100644 --- a/doc/services/portability/posix/conformance/index.rst +++ b/doc/services/portability/posix/conformance/index.rst @@ -64,7 +64,7 @@ POSIX System Interfaces :ref:`_POSIX_CLOCK_SELECTION`, 200809L, :kconfig:option:`CONFIG_POSIX_CLOCK` _POSIX_MAPPED_FILES, -1, :ref:`†` _POSIX_MEMORY_PROTECTION, -1, :ref:`†` - :ref:`_POSIX_READER_WRITER_LOCKS`, -1, :kconfig:option:`CONFIG_PTHREAD_IPC` + :ref:`_POSIX_READER_WRITER_LOCKS`, 200809L, :kconfig:option:`CONFIG_PTHREAD_IPC` _POSIX_REALTIME_SIGNALS, -1, :ref:`†` :ref:`_POSIX_SEMAPHORES`, 200809L, :kconfig:option:`CONFIG_PTHREAD_IPC` :ref:`_POSIX_SPIN_LOCKS`, 200809L, :kconfig:option:`CONFIG_PTHREAD_SPINLOCK` diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst index 6a241266b2f..569cfe45aa5 100644 --- a/doc/services/portability/posix/option_groups/index.rst +++ b/doc/services/portability/posix/option_groups/index.rst @@ -401,9 +401,9 @@ _POSIX_READER_WRITER_LOCKS pthread_rwlock_unlock(),yes pthread_rwlock_wrlock(),yes pthread_rwlockattr_destroy(),yes - pthread_rwlockattr_getpshared(), + pthread_rwlockattr_getpshared(),yes pthread_rwlockattr_init(),yes - pthread_rwlockattr_setpshared(), + pthread_rwlockattr_setpshared(),yes .. _posix_option_thread_attr_stackaddr: From 7207f35758190231c451d2033cddadf68378ce40 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Wed, 20 Mar 2024 16:48:25 +0100 Subject: [PATCH 1252/2402] net: tcp: Fix ACK check in LAST_ACK state The final ACK check during passive close was wrong - we should not compare its SEQ number with the ACK number we've sent last, but rather compare the ACK number it acknowledges matches our current SEQ number on the connection. This ensures, that the ACK received is really acknowledging the FIN packet we've sent from our side, and is not just some earlier retransmission. Currently the latter could be the case, and we've closed the connection prematurely. In result, when the real "final ACK" arrived, the TCP stack replied with RST. Subsequently, we should increment the SEQ number on the connection after sending FIN packet, so that we are able to identify final ACK correctly, just as it's done in active close cases. Signed-off-by: Robert Lubos --- subsys/net/ip/tcp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/subsys/net/ip/tcp.c b/subsys/net/ip/tcp.c index 598af5050e6..6636b3d3032 100644 --- a/subsys/net/ip/tcp.c +++ b/subsys/net/ip/tcp.c @@ -3006,6 +3006,7 @@ static enum net_verdict tcp_in(struct tcp *conn, struct net_pkt *pkt) conn_ack(conn, + 1); tcp_out(conn, FIN | ACK); + conn_seq(conn, + 1); next = TCP_LAST_ACK; verdict = NET_OK; keep_alive_timer_stop(conn); @@ -3032,6 +3033,7 @@ static enum net_verdict tcp_in(struct tcp *conn, struct net_pkt *pkt) conn_ack(conn, + len + 1); tcp_out(conn, FIN | ACK); + conn_seq(conn, + 1); next = TCP_LAST_ACK; keep_alive_timer_stop(conn); tcp_setup_last_ack_timer(conn); @@ -3224,11 +3226,12 @@ static enum net_verdict tcp_in(struct tcp *conn, struct net_pkt *pkt) break; case TCP_CLOSE_WAIT: tcp_out(conn, FIN); + conn_seq(conn, + 1); next = TCP_LAST_ACK; tcp_setup_last_ack_timer(conn); break; case TCP_LAST_ACK: - if (th && FL(&fl, ==, ACK, th_seq(th) == conn->ack)) { + if (th && FL(&fl, ==, ACK, th_ack(th) == conn->seq)) { tcp_send_timer_cancel(conn); do_close = true; verdict = NET_OK; From c6b07ef8db1f5ecf06ca9a22fb4a34c65b922231 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Tue, 5 Mar 2024 16:41:10 -0600 Subject: [PATCH 1253/2402] dts: bindings: Add RW PMU binding Add RW PMU binding. PMU is what records and enables the reset causes. Signed-off-by: Declan Snyder --- dts/bindings/power/nxp,rw-pmu.yaml | 14 ++++++++++++++ include/zephyr/dt-bindings/power/nxp_rw_pmu.h | 19 +++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 dts/bindings/power/nxp,rw-pmu.yaml create mode 100644 include/zephyr/dt-bindings/power/nxp_rw_pmu.h diff --git a/dts/bindings/power/nxp,rw-pmu.yaml b/dts/bindings/power/nxp,rw-pmu.yaml new file mode 100644 index 00000000000..17e593e2322 --- /dev/null +++ b/dts/bindings/power/nxp,rw-pmu.yaml @@ -0,0 +1,14 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP RW PMU + +compatible: "nxp,rw-pmu" + +include: base.yaml + +properties: + reset-causes-en: + type: array + description: | + List reset causes to enable, using bitmasks of SYS_RESET registers. diff --git a/include/zephyr/dt-bindings/power/nxp_rw_pmu.h b/include/zephyr/dt-bindings/power/nxp_rw_pmu.h new file mode 100644 index 00000000000..14d474c03a8 --- /dev/null +++ b/include/zephyr/dt-bindings/power/nxp_rw_pmu.h @@ -0,0 +1,19 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_ + +#define PMU_RESET_CM33_SOFT_RESET 0x1 +#define PMU_RESET_CM33_LOCKUP 0x2 +#define PMU_RESET_WATCHDOG 0x4 +#define PMU_RESET_AP_RESET 0x8 +#define PMU_RESET_CODE_WATCHDOG 0x10 +#define PMU_RESET_ITRC 0x20 +#define PMU_RESET_RESETB 0x40 +#define PMU_RESET_ALL 0x7F + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_ */ From 9607543496913a53d539aa7e6dcce9be90c87c83 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Tue, 5 Mar 2024 16:43:16 -0600 Subject: [PATCH 1254/2402] drivers: hwinfo: Add RW hwinfo driver Add RW hwinfo driver Signed-off-by: Declan Snyder --- drivers/hwinfo/CMakeLists.txt | 1 + drivers/hwinfo/Kconfig | 7 +++ drivers/hwinfo/hwinfo_rw61x.c | 88 +++++++++++++++++++++++++++++++++++ 3 files changed, 96 insertions(+) create mode 100644 drivers/hwinfo/hwinfo_rw61x.c diff --git a/drivers/hwinfo/CMakeLists.txt b/drivers/hwinfo/CMakeLists.txt index ab3b587dc75..2e7d91141be 100644 --- a/drivers/hwinfo/CMakeLists.txt +++ b/drivers/hwinfo/CMakeLists.txt @@ -28,3 +28,4 @@ zephyr_library_sources_ifdef(CONFIG_HWINFO_SAM4L hwinfo_sam4l.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_SMARTBOND hwinfo_smartbond.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_STM32 hwinfo_stm32.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_ANDES hwinfo_andes.c) +zephyr_library_sources_ifdef(CONFIG_HWINFO_RW61X hwinfo_rw61x.c) diff --git a/drivers/hwinfo/Kconfig b/drivers/hwinfo/Kconfig index 81888bd3a78..467a36ad8af 100644 --- a/drivers/hwinfo/Kconfig +++ b/drivers/hwinfo/Kconfig @@ -192,4 +192,11 @@ config HWINFO_ANDES help Enable Andes hwinfo driver +config HWINFO_RW61X + bool "RW61X hwinfo" + default y + depends on SOC_SERIES_RW6XX + help + Enable RW61X hwinfo driver + endif diff --git a/drivers/hwinfo/hwinfo_rw61x.c b/drivers/hwinfo/hwinfo_rw61x.c new file mode 100644 index 00000000000..a5b24c5d437 --- /dev/null +++ b/drivers/hwinfo/hwinfo_rw61x.c @@ -0,0 +1,88 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include + +/* Because of the ROM clearing the reset register and using scratch register + * which cannot be cleared, we have to "fake" this to meet the hwinfo api. + * Technically all the reset causes are already cleared by the ROM, but we will + * still clear them ourselves on the first call to clear them by user. + */ +static bool reset_cleared; + +ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) +{ + uint32_t id_length = length; + + if (OCOTP_ReadUniqueID(buffer, &id_length)) { + return -EINVAL; + } + + return (ssize_t)id_length; +} + +int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported) +{ + *supported = ( + RESET_SOFTWARE | + RESET_CPU_LOCKUP | + RESET_WATCHDOG | + RESET_SECURITY | + RESET_DEBUG | + RESET_HARDWARE + ); + + return 0; +} + +int z_impl_hwinfo_get_reset_cause(uint32_t *cause) +{ + if (reset_cleared) { + *cause = 0; + return 0; + } + + uint32_t reset_cause = POWER_GetResetCause(); + + switch (reset_cause) { + case kPOWER_ResetCauseSysResetReq: + *cause = RESET_SOFTWARE; + break; + case kPOWER_ResetCauseLockup: + *cause = RESET_CPU_LOCKUP; + break; + case kPOWER_ResetCauseWdt: + *cause = RESET_WATCHDOG; + break; + case kPOWER_ResetCauseApResetReq: + *cause = RESET_DEBUG; + break; + case kPOWER_ResetCauseCodeWdt: + case kPOWER_ResetCauseItrc: + *cause = RESET_SECURITY; + break; + case kPOWER_ResetCauseResetB: + *cause = RESET_HARDWARE; + break; + default: + *cause = 0; + break; + } + + return 0; +} + +int z_impl_hwinfo_clear_reset_cause(void) +{ + POWER_ClearResetCause(kPOWER_ResetCauseAll); + + reset_cleared = true; + + return 0; +} From 711375695e2058a60c785646ef801c209c57f9d5 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Tue, 19 Mar 2024 14:41:16 -0500 Subject: [PATCH 1255/2402] soc: nxp: rw: Support Reset cause setting Support reset causes on RW SOC Signed-off-by: Declan Snyder --- dts/arm/nxp/nxp_rw6xx_common.dtsi | 6 ++++++ soc/nxp/rw/soc.c | 12 ++++++++++++ 2 files changed, 18 insertions(+) diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index 978a4d94688..d6cc8643a8b 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { chosen { @@ -69,6 +70,11 @@ #clock-cells = <1>; }; + pmu: pmu@31000 { + reg = <0x31000 0x130>; + compatible = "nxp,rw-pmu"; + }; + trng: random@14000 { compatible = "nxp,kinetis-trng"; reg = <0x14000 0x1000>; diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c index 3da03e8409f..350b019a2cd 100644 --- a/soc/nxp/rw/soc.c +++ b/soc/nxp/rw/soc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -246,6 +247,17 @@ static int nxp_rw600_init(void) POWER_EnableResetSource(kPOWER_ResetSourceWdt); #endif +#define PMU_RESET_CAUSES_ \ + DT_FOREACH_PROP_ELEM_SEP(DT_NODELABEL(pmu), reset_causes_en, DT_PROP_BY_IDX, (|)) +#define PMU_RESET_CAUSES \ + COND_CODE_0(IS_EMPTY(PMU_RESET_CAUSES_), (PMU_RESET_CAUSES_), (0)) +#define WDT_RESET \ + COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(wwdt), (kPOWER_ResetSourceWdt), (0)) +#define RESET_CAUSES \ + (PMU_RESET_CAUSES | WDT_RESET) + + POWER_EnableResetSource(RESET_CAUSES); + /* Initialize clock */ clock_init(); From 739573ee8e43b0d185606732501c25a6da96f1d7 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Tue, 19 Mar 2024 14:42:01 -0500 Subject: [PATCH 1256/2402] boards: rd_rw612_bga: Enable HWINFO Enable some reset causes in PMU node and indicate in the yaml support for hwinfo. Signed-off-by: Declan Snyder --- boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi | 6 ++++++ boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml | 1 + 2 files changed, 7 insertions(+) diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index 3ef537e7695..e2793a1a091 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -136,3 +136,9 @@ arduino_i2c: &flexcomm2 { &ctimer0 { status = "okay"; }; + +&pmu { + reset-causes-en = , + , + ; +}; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml index 6990f314240..61d73f05f95 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -22,3 +22,4 @@ supported: - entropy - watchdog - counter + - hwinfo From 796d9162d144dbe7ec7ed0b13b618c251725b438 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Thu, 14 Mar 2024 15:27:32 -0700 Subject: [PATCH 1257/2402] x86: x86_64: fix tls setup in early boot During early boot in assembly, the function parameter to z_x86_early_tls_update_gdt() should be the pointer to the interrupt stack. However, what was passed instead was the pointer to the x86_cpuboot struct. So fix it to actually pass the stack pointer (which is stashed inside the x86_cpuboot struct). Signed-off-by: Daniel Leung --- arch/x86/core/intel64/locore.S | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/core/intel64/locore.S b/arch/x86/core/intel64/locore.S index dd541921742..d68e80c423f 100644 --- a/arch/x86/core/intel64/locore.S +++ b/arch/x86/core/intel64/locore.S @@ -260,13 +260,16 @@ enter_code64: rep stosq #endif - /* Enter C domain now that we have a stack set up, never to return */ - movq %rbp, %rdi #ifdef CONFIG_STACK_CANARIES_TLS + movq %rsp, %rdi pushq %rsp call z_x86_early_tls_update_gdt popq %rsp #endif + + /* Enter C domain now that we have a stack set up, never to return */ + movq %rbp, %rdi + call z_x86_cpu_init /* 64 bit OS entry point, used by EFI support. UEFI From 33f586f312e9ea2668164d17528f72c925e7f61a Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Sat, 24 Feb 2024 00:37:07 -0800 Subject: [PATCH 1258/2402] xtensa: mmu: no need to ignore array bound for SoC MMU ranges The #pragma to ignore array bounds for xtensa_soc_mmu_ranges[] was a remnant before code refactoring during review. Since this array is no longer declared __weak and as a zero length array, the #pragma to ignore array bounds is no longer needed. So remove them. Signed-off-by: Daniel Leung --- arch/xtensa/core/ptables.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/arch/xtensa/core/ptables.c b/arch/xtensa/core/ptables.c index bd2e8a61581..10b199bcf1e 100644 --- a/arch/xtensa/core/ptables.c +++ b/arch/xtensa/core/ptables.c @@ -284,19 +284,6 @@ static void xtensa_init_page_tables(void) map_memory(range->start, range->end, attrs, shared); } -/** - * GCC complains about usage of the SoC MMU range ARRAY_SIZE - * (xtensa_soc_mmu_ranges) as the default weak declaration is - * an empty array, and any access to its element is considered - * out of bound access. However, we have a number of element - * variable to guard against this (... if done correctly). - * Besides, this will almost be overridden by the SoC layer. - * So tell GCC to ignore this. - */ -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Warray-bounds" -#endif for (entry = 0; entry < xtensa_soc_mmu_ranges_num; entry++) { const struct xtensa_mmu_range *range = &xtensa_soc_mmu_ranges[entry]; bool shared; @@ -307,9 +294,7 @@ static void xtensa_init_page_tables(void) map_memory(range->start, range->end, attrs, shared); } -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif + /* Finally, the direct-mapped pages used in the page tables * must be fixed up to use the same cache attribute (but these * must be writable, obviously). They shouldn't be left at From d89e7f63fd4d28fbfe54c418b7bea41602d76212 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Thu, 15 Feb 2024 11:50:43 -0800 Subject: [PATCH 1259/2402] xtensa: exiting simulator on fatal errors There was old code to exit the simulator when there is a fatal error. This updates the #ifdef and the function name so that it can be used to exit both QEMU and simulator when a fatal error occurs. This should help with twister runs as this will fail immediately instead of having wait for timeout. Signed-off-by: Daniel Leung --- arch/xtensa/core/fatal.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/xtensa/core/fatal.c b/arch/xtensa/core/fatal.c index c6bd07c2b44..6ec5549f2e4 100644 --- a/arch/xtensa/core/fatal.c +++ b/arch/xtensa/core/fatal.c @@ -16,7 +16,7 @@ #include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); -#ifdef XT_SIMULATOR +#if defined(CONFIG_SIMULATOR_XTENSA) || defined(XT_SIMULATOR) #include #endif @@ -109,8 +109,8 @@ void xtensa_fatal_error(unsigned int reason, const z_arch_esf_t *esf) z_fatal_error(reason, esf); } -#ifdef XT_SIMULATOR -void exit(int return_code) +#if defined(CONFIG_SIMULATOR_XTENSA) || defined(XT_SIMULATOR) +void xtensa_simulator_exit(int return_code) { __asm__ ( "mov a3, %[code]\n\t" @@ -119,13 +119,13 @@ void exit(int return_code) : : [code] "r" (return_code), [call] "i" (SYS_exit) : "a3", "a2"); + + CODE_UNREACHABLE; } -#endif -#ifdef XT_SIMULATOR -FUNC_NORETURN void z_system_halt(unsigned int reason) +FUNC_NORETURN void arch_system_halt(unsigned int reason) { - exit(255 - reason); + xtensa_simulator_exit(255 - reason); CODE_UNREACHABLE; } #endif From 75a3805c8b96914ea867cb9d03aa32d88344a2b6 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Tue, 19 Mar 2024 12:22:48 +0100 Subject: [PATCH 1260/2402] kconfig: lto: Disable when data relocation is enabled As per issue #69730, building arch.shared_interrupt.lto and kernel.common.lto for mimxrt685_evk or mimxrt595_evk/mimxrt595s/cm33 is currently broken due to their usage of CONFIG_CODE_DATA_RELOCATION. This commit disables LTO when CODE_DATA_RELOCATION is enabled, allowing PRs with changes in the kernel code to pass the CI check. On the down side, builds affected by this change produce a new warning: > warning: LTO (defined at Kconfig.zephyr:430) was assigned the value > 'y' but got the value 'n'. Check these unsatisfied dependencies: > (!CODE_DATA_RELOCATION) (=n) Signed-off-by: Reto Schneider --- Kconfig.zephyr | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Kconfig.zephyr b/Kconfig.zephyr index eb4399c297f..b315a0e7aad 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -429,7 +429,9 @@ endchoice config LTO bool "Link Time Optimization [EXPERIMENTAL]" - depends on (!(GEN_ISR_TABLES || GEN_IRQ_VECTOR_TABLE) || ISR_TABLES_LOCAL_DECLARATION) && !NATIVE_LIBRARY + depends on !(GEN_ISR_TABLES || GEN_IRQ_VECTOR_TABLE) || ISR_TABLES_LOCAL_DECLARATION + depends on !NATIVE_LIBRARY + depends on !CODE_DATA_RELOCATION select EXPERIMENTAL help This option enables Link Time Optimization. From f4430827d8dbf0e8a7c1f7fcb25e84acee99c744 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 15 Mar 2024 16:21:30 +0100 Subject: [PATCH 1261/2402] tests: kernel: common: lto: Exclude builds with warning Trying to enable LTO when CODE_DATA_RELOCATION is already enabled produces a warning. This commit prevents twister from building such combinations for kernel.common.lto. Signed-off-by: Reto Schneider --- tests/kernel/common/testcase.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/kernel/common/testcase.yaml b/tests/kernel/common/testcase.yaml index d02a4f5ae8f..c4c17e2eb51 100644 --- a/tests/kernel/common/testcase.yaml +++ b/tests/kernel/common/testcase.yaml @@ -48,7 +48,8 @@ tests: extra_configs: - CONFIG_PICOLIBC=y kernel.common.lto: - filter: CONFIG_ISR_TABLES_LOCAL_DECLARATION_SUPPORTED + # CONFIG_CODE_DATA_RELOCATION causes a build error (issue #69730) + filter: CONFIG_ISR_TABLES_LOCAL_DECLARATION_SUPPORTED and not CONFIG_CODE_DATA_RELOCATION tags: lto extra_configs: - CONFIG_TEST_USERSPACE=n From 397b8465dc6bd771685d31321c104ad7d3a315f9 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 15 Mar 2024 16:21:30 +0100 Subject: [PATCH 1262/2402] tests: kernel: interrupt: lto: Exclude builds with warning Trying to enable LTO when CODE_DATA_RELOCATION is already enabled produces a warning. This commit prevents twister from building such combinations for arch.shared_interrupt.lto. Signed-off-by: Reto Schneider --- tests/kernel/interrupt/testcase.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/kernel/interrupt/testcase.yaml b/tests/kernel/interrupt/testcase.yaml index a73f0e26b26..78d81a579d0 100644 --- a/tests/kernel/interrupt/testcase.yaml +++ b/tests/kernel/interrupt/testcase.yaml @@ -75,4 +75,7 @@ tests: - CONFIG_TEST_USERSPACE=n - CONFIG_ISR_TABLES_LOCAL_DECLARATION=y - CONFIG_LTO=y - filter: not CONFIG_TRUSTED_EXECUTION_NONSECURE and CONFIG_ISR_TABLES_LOCAL_DECLARATION_SUPPORTED + # CONFIG_CODE_DATA_RELOCATION causes a build error (issue #69730) + filter: > + not CONFIG_TRUSTED_EXECUTION_NONSECURE and CONFIG_ISR_TABLES_LOCAL_DECLARATION_SUPPORTED + and not CONFIG_CODE_DATA_RELOCATION From 6b9d01f995c72d1c747a98dbc866d052a0f29cb0 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Wed, 20 Mar 2024 15:57:49 -0700 Subject: [PATCH 1263/2402] intel_adsp/ace: power: No pending transaction before power gate Issue an upstream read transaction through uncached memory to flush out all pending transactions before power down the host domain. Signed-off-by: Flavio Ceolin --- drivers/power_domain/power_domain_intel_adsp.c | 4 ++-- soc/intel/intel_adsp/ace/multiprocessing.c | 16 ---------------- soc/intel/intel_adsp/ace/power.c | 14 ++++++++++++++ 3 files changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/power_domain/power_domain_intel_adsp.c b/drivers/power_domain/power_domain_intel_adsp.c index 8a82f26650f..3f816c69146 100644 --- a/drivers/power_domain/power_domain_intel_adsp.c +++ b/drivers/power_domain/power_domain_intel_adsp.c @@ -36,10 +36,10 @@ static int pd_intel_adsp_set_power_enable(struct pg_bits *bits, bool power_enabl } } else { #if CONFIG_SOC_INTEL_ACE15_MTPM - extern uint32_t g_key_read_holder; + extern uint32_t adsp_pending_buffer; if (bits->SPA_bit == INTEL_ADSP_HST_DOMAIN_BIT) { - volatile uint32_t *key_read_ptr = &g_key_read_holder; + volatile uint32_t *key_read_ptr = &adsp_pending_buffer; uint32_t key_value = *key_read_ptr; if (key_value != INTEL_ADSP_ACE15_MAGIC_KEY) diff --git a/soc/intel/intel_adsp/ace/multiprocessing.c b/soc/intel/intel_adsp/ace/multiprocessing.c index 3170a8f1090..f530232e896 100644 --- a/soc/intel/intel_adsp/ace/multiprocessing.c +++ b/soc/intel/intel_adsp/ace/multiprocessing.c @@ -27,11 +27,6 @@ #define ACE_INTC_IRQ DT_IRQN(DT_NODELABEL(ace_intc)) -#if CONFIG_SOC_INTEL_ACE15_MTPM -/* .bss is uncached, we further check it below */ -uint32_t g_key_read_holder; -#endif /* CONFIG_SOC_INTEL_ACE15_MTPM */ - static void ipc_isr(void *arg) { uint32_t cpu_id = arch_proc_id(); @@ -88,17 +83,6 @@ void soc_mp_init(void) /* Set the core 0 active */ soc_cpus_active[0] = true; -#if CONFIG_SOC_INTEL_ACE15_MTPM -#if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1) - /* - * Only when more than 1 CPUs is enabled, then this is in uncached area. - * Otherwise, this is in cached area and will fail this test. - */ - __ASSERT(!sys_cache_is_ptr_cached(&g_key_read_holder), - "g_key_read_holder must be uncached"); -#endif /* defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1) */ - g_key_read_holder = INTEL_ADSP_ACE15_MAGIC_KEY; -#endif /* CONFIG_SOC_INTEL_ACE15_MTPM */ } static int host_runtime_get(void) diff --git a/soc/intel/intel_adsp/ace/power.c b/soc/intel/intel_adsp/ace/power.c index b9f1ba9fbd9..e94e1b0f17c 100644 --- a/soc/intel/intel_adsp/ace/power.c +++ b/soc/intel/intel_adsp/ace/power.c @@ -25,6 +25,13 @@ #define SRAM_ALIAS_BASE 0xA0000000 #define SRAM_ALIAS_MASK 0xF0000000 +#if CONFIG_SOC_INTEL_ACE15_MTPM +/* Used to force any pending transaction by HW issuing an upstream read before + * power down host domain. + */ +uint8_t adsp_pending_buffer[CONFIG_DCACHE_LINE_SIZE] __aligned(CONFIG_DCACHE_LINE_SIZE); +#endif /* CONFIG_SOC_INTEL_ACE15_MTPM */ + __imr void power_init(void) { #if CONFIG_ADSP_IDLE_CLOCK_GATING @@ -34,6 +41,13 @@ __imr void power_init(void) /* Disable idle power and clock gating */ DSPCS.bootctl[0].bctl |= DSPBR_BCTL_WAITIPCG | DSPBR_BCTL_WAITIPPG; #endif /* CONFIG_ADSP_IDLE_CLOCK_GATING */ + +#if CONFIG_SOC_INTEL_ACE15_MTPM + *((uint32_t *)sys_cache_cached_ptr_get(&adsp_pending_buffer)) = + INTEL_ADSP_ACE15_MAGIC_KEY; + cache_data_flush_range(sys_cache_cached_ptr_get(&adsp_pending_buffer), + sizeof(adsp_pending_buffer)); +#endif /* CONFIG_SOC_INTEL_ACE15_MTPM */ } #ifdef CONFIG_PM From 09abd850d931fbafd3ae2ea1e9583995a50dd9b1 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 22 Mar 2024 16:21:48 +0200 Subject: [PATCH 1264/2402] net: shell: Do not print DHCPv4 info if IPv4 is not available If the network interface does not enable IPv4, then it is pointless to print DHCPv4 information when invoking "iface" shell command. Signed-off-by: Jukka Rissanen --- subsys/net/lib/shell/iface.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/subsys/net/lib/shell/iface.c b/subsys/net/lib/shell/iface.c index 7301cadaced..f5e8ab5ae6c 100644 --- a/subsys/net/lib/shell/iface.c +++ b/subsys/net/lib/shell/iface.c @@ -483,18 +483,20 @@ static void iface_cb(struct net_if *iface, void *user_data) #endif /* CONFIG_NET_IPV4 */ #if defined(CONFIG_NET_DHCPV4) - PR("DHCPv4 lease time : %u\n", - iface->config.dhcpv4.lease_time); - PR("DHCPv4 renew time : %u\n", - iface->config.dhcpv4.renewal_time); - PR("DHCPv4 server : %s\n", - net_sprint_ipv4_addr(&iface->config.dhcpv4.server_id)); - PR("DHCPv4 requested : %s\n", - net_sprint_ipv4_addr(&iface->config.dhcpv4.requested_ip)); - PR("DHCPv4 state : %s\n", - net_dhcpv4_state_name(iface->config.dhcpv4.state)); - PR("DHCPv4 attempts : %d\n", - iface->config.dhcpv4.attempts); + if (net_if_flag_is_set(iface, NET_IF_IPV4)) { + PR("DHCPv4 lease time : %u\n", + iface->config.dhcpv4.lease_time); + PR("DHCPv4 renew time : %u\n", + iface->config.dhcpv4.renewal_time); + PR("DHCPv4 server : %s\n", + net_sprint_ipv4_addr(&iface->config.dhcpv4.server_id)); + PR("DHCPv4 requested : %s\n", + net_sprint_ipv4_addr(&iface->config.dhcpv4.requested_ip)); + PR("DHCPv4 state : %s\n", + net_dhcpv4_state_name(iface->config.dhcpv4.state)); + PR("DHCPv4 attempts : %d\n", + iface->config.dhcpv4.attempts); + } #endif /* CONFIG_NET_DHCPV4 */ #else From 6c300c9c66e7a73bf46c1d9aec166e09ba410383 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Wed, 20 Mar 2024 17:18:17 +0100 Subject: [PATCH 1265/2402] tests: net: buf: Improve testing coverage Before this commit, cloning a buffer was tested only for a buffer belonging to a reference counted pool. By using a buffer from a pool that does not support reference counting, the added test ensures that the non-ref-counting code path also works. Signed-off-by: Reto Schneider --- tests/net/buf/src/main.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/tests/net/buf/src/main.c b/tests/net/buf/src/main.c index 1cc8ecc8cfb..d9a54f3a28e 100644 --- a/tests/net/buf/src/main.c +++ b/tests/net/buf/src/main.c @@ -408,12 +408,13 @@ ZTEST(net_buf_tests, test_net_buf_multi_frags) "Incorrect frag destroy callback count"); } -ZTEST(net_buf_tests, test_net_buf_clone) +ZTEST(net_buf_tests, test_net_buf_clone_ref_count) { struct net_buf *buf, *clone; destroy_called = 0; + /* Heap pool supports reference counting */ buf = net_buf_alloc_len(&bufs_pool, 74, K_NO_WAIT); zassert_not_null(buf, "Failed to get buffer"); @@ -427,6 +428,30 @@ ZTEST(net_buf_tests, test_net_buf_clone) zassert_equal(destroy_called, 2, "Incorrect destroy callback count"); } +ZTEST(net_buf_tests, test_net_buf_clone_no_ref_count) +{ + struct net_buf *buf, *clone; + const uint8_t data[3] = {0x11, 0x22, 0x33}; + + destroy_called = 0; + + /* Fixed pool does not support reference counting */ + buf = net_buf_alloc_len(&fixed_pool, 3, K_NO_WAIT); + zassert_not_null(buf, "Failed to get buffer"); + net_buf_add_mem(buf, data, sizeof(data)); + + clone = net_buf_clone(buf, K_NO_WAIT); + zassert_not_null(clone, "Failed to get clone buffer"); + zassert_not_equal(buf->data, clone->data, + "No reference counting support, different pointers expected"); + zassert_mem_equal(clone->data, data, sizeof(data)); + + net_buf_unref(buf); + net_buf_unref(clone); + + zassert_equal(destroy_called, 2, "Incorrect destroy callback count"); +} + ZTEST(net_buf_tests, test_net_buf_fixed_pool) { struct net_buf *buf; From a28d5df5c643614042ca04caf65fcb274c1e956a Mon Sep 17 00:00:00 2001 From: Jonathon Penix Date: Mon, 11 Mar 2024 12:39:17 -0700 Subject: [PATCH 1266/2402] tests: coredump: Change additional boards to directly call k_panic() The riscv_virtual, hifive_unleashed, and hifive_unmatched boards all timeout on this test if they actually perform the null dereference when they are simulated. Whether the null dereference happens seems to depend on the compiler used as well as whether optimizations are enabled though. To make this more consistent, handle these boards in the same way as others which use Renode simulation and have them directly call k_panic(). Signed-off-by: Jonathon Penix --- tests/subsys/debug/coredump/src/main.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/subsys/debug/coredump/src/main.c b/tests/subsys/debug/coredump/src/main.c index 3f18ef9e2d6..82f6f95ade5 100644 --- a/tests/subsys/debug/coredump/src/main.c +++ b/tests/subsys/debug/coredump/src/main.c @@ -29,8 +29,11 @@ void func_3(uint32_t *addr) { #if defined(CONFIG_BOARD_M2GL025_MIV) || \ defined(CONFIG_BOARD_HIFIVE1) || \ + defined(CONFIG_BOARD_HIFIVE_UNLEASHED) || \ + defined(CONFIG_BOARD_HIFIVE_UNMATCHED) || \ defined(CONFIG_BOARD_LONGAN_NANO) || \ defined(CONFIG_BOARD_QEMU_XTENSA) || \ + defined(CONFIG_BOARD_RISCV32_VIRTUAL) || \ defined(CONFIG_SOC_FAMILY_INTEL_ADSP) ARG_UNUSED(addr); /* Call k_panic() directly so Renode doesn't pause execution. From 3723493f60a10f17d8d117fb8288a75da20cdd74 Mon Sep 17 00:00:00 2001 From: Jonathon Penix Date: Mon, 11 Mar 2024 12:39:38 -0700 Subject: [PATCH 1267/2402] tests: coredump: Disable optimizations to prevent unexpected failures debug.coredump.logging_backend is currently failing for most of the targets I have tried when building with clang. Depending on the target, func_3 invokes undefined behavior by dereferencing addr (which is NULL) which can lead to the compiler optimizing out significant portions of the code, resulting in unexpected/incorrect failures. Here, clang seems to inline func_3 into main then marks the inlined implementation as unreachable (due to the UB) and removes it and everything after it in main. So, we fall through to whatever code lies past main, resulting in a test failure (timeout) from what I've seen. GCC seems to do similar things, but creates an invalid opcode instruction so the test still succeeds. clang is correct in both optimizing this behavior out and leaving buggy code behind, so disable optimizations for func_3 to keep things under control and prevent the incorrect failures. Signed-off-by: Jonathon Penix --- tests/subsys/debug/coredump/src/main.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/subsys/debug/coredump/src/main.c b/tests/subsys/debug/coredump/src/main.c index 82f6f95ade5..fac5395971c 100644 --- a/tests/subsys/debug/coredump/src/main.c +++ b/tests/subsys/debug/coredump/src/main.c @@ -25,7 +25,10 @@ void k_sys_fatal_error_handler(unsigned int reason, const z_arch_esf_t *pEsf) k_fatal_halt(reason); } -void func_3(uint32_t *addr) +/* Turn off optimizations to prevent the compiler from optimizing this away + * due to the null pointer dereference. + */ +__no_optimization void func_3(uint32_t *addr) { #if defined(CONFIG_BOARD_M2GL025_MIV) || \ defined(CONFIG_BOARD_HIFIVE1) || \ From a622407bd379694f85402c32f46b8a6f67db49ec Mon Sep 17 00:00:00 2001 From: Chen Xingyu Date: Sun, 14 Jan 2024 20:33:57 +0800 Subject: [PATCH 1268/2402] drivers: gpio: dw: Switch to `DT_INST_IRQN_BY_IDX` Switch to using `DT_*IRQN` helpers for obtaining the IRQ number instead of directly accessing the `irq` cell. This change ensures that the encoded values for multi-level interrupts are correctly retrieved. Signed-off-by: Chen Xingyu --- drivers/gpio/gpio_dw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio_dw.c b/drivers/gpio/gpio_dw.c index cd1a97a6afa..182a841417c 100644 --- a/drivers/gpio/gpio_dw.c +++ b/drivers/gpio/gpio_dw.c @@ -437,10 +437,10 @@ static int gpio_dw_initialize(const struct device *port) COND_CODE_1(DT_INST_IRQ_HAS_CELL(n, flags), (DT_INST_IRQ(n, flags)), (0)) #define GPIO_CFG_IRQ(idx, n) \ - IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, idx, irq), \ + IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, idx), \ DT_INST_IRQ(n, priority), gpio_dw_isr, \ DEVICE_DT_INST_GET(n), INST_IRQ_FLAGS(n)); \ - irq_enable(DT_INST_IRQ_BY_IDX(n, idx, irq)); \ + irq_enable(DT_INST_IRQN_BY_IDX(n, idx)); \ #define GPIO_DW_INIT(n) \ static void gpio_config_##n##_irq(const struct device *port) \ From b72e78f7ca630b3b5caef715ea29dd7e5ad054d6 Mon Sep 17 00:00:00 2001 From: Chen Xingyu Date: Fri, 22 Mar 2024 01:22:24 +0800 Subject: [PATCH 1269/2402] tests: drivers: build_all: gpio: Build gpio_dw This commit adds gpio_dw to the build_all CI test to ensure the driver is always buildable. Signed-off-by: Chen Xingyu --- tests/drivers/build_all/gpio/app.overlay | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tests/drivers/build_all/gpio/app.overlay b/tests/drivers/build_all/gpio/app.overlay index 53380f932ca..b594214586a 100644 --- a/tests/drivers/build_all/gpio/app.overlay +++ b/tests/drivers/build_all/gpio/app.overlay @@ -23,6 +23,14 @@ status = "okay"; }; + test_gpio_dw: gpio@c0ffee { + compatible = "snps,designware-gpio"; + gpio-controller; + reg = <0xc0ffee 0x1000>; + #gpio-cells = <0x2>; + status = "okay"; + }; + test_i2c: i2c@11112222 { #address-cells = <1>; #size-cells = <0>; From 7273f212e35bab8f7681fadceceeeb67d039aad7 Mon Sep 17 00:00:00 2001 From: Chen Xingyu Date: Fri, 22 Mar 2024 10:25:34 +0800 Subject: [PATCH 1270/2402] drivers: gpio: dw: Address warning of unused `gpio_dw_isr` This commit conditionally masks out `gpio_dw_isr` to prevent a build warning if none of the instances of this driver are connected to an IRQ. Signed-off-by: Chen Xingyu --- drivers/gpio/gpio_dw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio_dw.c b/drivers/gpio/gpio_dw.c index 182a841417c..1aaaaee6117 100644 --- a/drivers/gpio/gpio_dw.c +++ b/drivers/gpio/gpio_dw.c @@ -384,6 +384,7 @@ static inline int gpio_dw_manage_callback(const struct device *port, return gpio_manage_callback(&context->callbacks, callback, set); } +#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts) static void gpio_dw_isr(const struct device *port) { struct gpio_dw_runtime *context = port->data; @@ -396,6 +397,7 @@ static void gpio_dw_isr(const struct device *port) gpio_fire_callbacks(&context->callbacks, port, int_status); } +#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts) */ static const struct gpio_driver_api api_funcs = { .pin_configure = gpio_dw_config, From 5aa4ae6ed54f91f2b99cf7e24ff50a155254ffc7 Mon Sep 17 00:00:00 2001 From: Pisit Sawangvonganan Date: Sat, 10 Feb 2024 00:06:50 +0700 Subject: [PATCH 1271/2402] drivers: can: stm32: fdcan: refactor register bits remap Optimize bit remapping in STM32 FDCAN driver by grouping consecutive bits. Additionally, leverage shared bit mapping between MCAN_IR and MCAN_IE to consolidate switch cases. Signed-off-by: Pisit Sawangvonganan --- drivers/can/can_stm32_fdcan.c | 135 +++++++++------------------------- 1 file changed, 33 insertions(+), 102 deletions(-) diff --git a/drivers/can/can_stm32_fdcan.c b/drivers/can/can_stm32_fdcan.c index 5eb3210eb31..3f00818e2fc 100644 --- a/drivers/can/can_stm32_fdcan.c +++ b/drivers/can/can_stm32_fdcan.c @@ -202,6 +202,7 @@ static inline uint16_t can_stm32fd_remap_reg(uint16_t reg) case CAN_MCAN_TXEFC: __ASSERT_NO_MSG(false); remap = CAN_STM32FD_REGISTER_UNSUPPORTED; + break; case CAN_MCAN_XIDAM: remap = CAN_STM32FD_XIDAM; break; @@ -275,58 +276,23 @@ static int can_stm32fd_read_reg(const struct device *dev, uint16_t reg, uint32_t switch (reg) { case CAN_MCAN_IR: - /* Remap IR bits */ - *val |= FIELD_PREP(CAN_MCAN_IR_ARA, FIELD_GET(CAN_STM32FD_IR_ARA, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_PED, FIELD_GET(CAN_STM32FD_IR_PED, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_PEA, FIELD_GET(CAN_STM32FD_IR_PEA, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_WDI, FIELD_GET(CAN_STM32FD_IR_WDI, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_BO, FIELD_GET(CAN_STM32FD_IR_BO, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_EW, FIELD_GET(CAN_STM32FD_IR_EW, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_EP, FIELD_GET(CAN_STM32FD_IR_EP, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_ELO, FIELD_GET(CAN_STM32FD_IR_ELO, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_TOO, FIELD_GET(CAN_STM32FD_IR_TOO, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_MRAF, FIELD_GET(CAN_STM32FD_IR_MRAF, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_TSW, FIELD_GET(CAN_STM32FD_IR_TSW, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_TEFL, FIELD_GET(CAN_STM32FD_IR_TEFL, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_TEFF, FIELD_GET(CAN_STM32FD_IR_TEFF, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_TEFN, FIELD_GET(CAN_STM32FD_IR_TEFN, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_TFE, FIELD_GET(CAN_STM32FD_IR_TFE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_TCF, FIELD_GET(CAN_STM32FD_IR_TCF, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_TC, FIELD_GET(CAN_STM32FD_IR_TC, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_HPM, FIELD_GET(CAN_STM32FD_IR_HPM, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_RF1L, FIELD_GET(CAN_STM32FD_IR_RF1L, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_RF1F, FIELD_GET(CAN_STM32FD_IR_RF1F, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_RF1N, FIELD_GET(CAN_STM32FD_IR_RF1N, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_RF0L, FIELD_GET(CAN_STM32FD_IR_RF0L, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_RF0F, FIELD_GET(CAN_STM32FD_IR_RF0F, bits)); - *val |= FIELD_PREP(CAN_MCAN_IR_RF0N, FIELD_GET(CAN_STM32FD_IR_RF0N, bits)); - break; + __fallthrough; case CAN_MCAN_IE: - /* Remap IE bits */ - *val |= FIELD_PREP(CAN_MCAN_IE_ARAE, FIELD_GET(CAN_STM32FD_IE_ARAE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_PEDE, FIELD_GET(CAN_STM32FD_IE_PEDE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_PEAE, FIELD_GET(CAN_STM32FD_IE_PEAE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_WDIE, FIELD_GET(CAN_STM32FD_IE_WDIE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_BOE, FIELD_GET(CAN_STM32FD_IE_BOE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_EWE, FIELD_GET(CAN_STM32FD_IE_EWE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_EPE, FIELD_GET(CAN_STM32FD_IE_EPE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_ELOE, FIELD_GET(CAN_STM32FD_IE_ELOE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_TOOE, FIELD_GET(CAN_STM32FD_IE_TOOE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_MRAFE, FIELD_GET(CAN_STM32FD_IE_MRAFE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_TSWE, FIELD_GET(CAN_STM32FD_IE_TSWE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_TEFLE, FIELD_GET(CAN_STM32FD_IE_TEFLE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_TEFFE, FIELD_GET(CAN_STM32FD_IE_TEFFE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_TEFNE, FIELD_GET(CAN_STM32FD_IE_TEFNE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_TFEE, FIELD_GET(CAN_STM32FD_IE_TFEE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_TCFE, FIELD_GET(CAN_STM32FD_IE_TCFE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_TCE, FIELD_GET(CAN_STM32FD_IE_TCE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_HPME, FIELD_GET(CAN_STM32FD_IE_HPME, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_RF1LE, FIELD_GET(CAN_STM32FD_IE_RF1LE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_RF1FE, FIELD_GET(CAN_STM32FD_IE_RF1FE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_RF1NE, FIELD_GET(CAN_STM32FD_IE_RF1NE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_RF0LE, FIELD_GET(CAN_STM32FD_IE_RF0LE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_RF0FE, FIELD_GET(CAN_STM32FD_IE_RF0FE, bits)); - *val |= FIELD_PREP(CAN_MCAN_IE_RF0NE, FIELD_GET(CAN_STM32FD_IE_RF0NE, bits)); + /* Remap IR/IE bits, ignoring unsupported bits */ + /* Group 1 map bits 23-16 (stm32fd) to 29-22 (mcan) */ + *val |= ((bits & GENMASK(23, 16)) << 6); + + /* Group 2 map bits 15-11 (stm32fd) to 18-14 (mcan) */ + *val |= ((bits & GENMASK(15, 11)) << 3); + + /* Group 3 map bits 10-4 (stm32fd) to 12-6 (mcan) */ + *val |= ((bits & GENMASK(10, 4)) << 2); + + /* Group 4 map bits 3-1 (stm32fd) to 4-2 (mcan) */ + *val |= ((bits & GENMASK(3, 1)) << 1); + + /* Group 5 map bits 0 (mcan) to 0 (stm32fd) */ + *val |= ((bits & GENMASK(0, 0)) << 0); break; case CAN_MCAN_ILS: /* Only remap ILS groups used in can_mcan.c */ @@ -366,58 +332,23 @@ static int can_stm32fd_write_reg(const struct device *dev, uint16_t reg, uint32_ switch (reg) { case CAN_MCAN_IR: - /* Remap IR bits, ignoring unsupported bits */ - bits |= FIELD_PREP(CAN_STM32FD_IR_ARA, FIELD_GET(CAN_MCAN_IR_ARA, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_PED, FIELD_GET(CAN_MCAN_IR_PED, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_PEA, FIELD_GET(CAN_MCAN_IR_PEA, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_WDI, FIELD_GET(CAN_MCAN_IR_WDI, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_BO, FIELD_GET(CAN_MCAN_IR_BO, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_EW, FIELD_GET(CAN_MCAN_IR_EW, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_EP, FIELD_GET(CAN_MCAN_IR_EP, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_ELO, FIELD_GET(CAN_MCAN_IR_ELO, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_TOO, FIELD_GET(CAN_MCAN_IR_TOO, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_MRAF, FIELD_GET(CAN_MCAN_IR_MRAF, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_TSW, FIELD_GET(CAN_MCAN_IR_TSW, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_TEFL, FIELD_GET(CAN_MCAN_IR_TEFL, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_TEFF, FIELD_GET(CAN_MCAN_IR_TEFF, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_TEFN, FIELD_GET(CAN_MCAN_IR_TEFN, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_TFE, FIELD_GET(CAN_MCAN_IR_TFE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_TCF, FIELD_GET(CAN_MCAN_IR_TCF, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_TC, FIELD_GET(CAN_MCAN_IR_TC, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_HPM, FIELD_GET(CAN_MCAN_IR_HPM, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_RF1L, FIELD_GET(CAN_MCAN_IR_RF1L, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_RF1F, FIELD_GET(CAN_MCAN_IR_RF1F, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_RF1N, FIELD_GET(CAN_MCAN_IR_RF1N, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_RF0L, FIELD_GET(CAN_MCAN_IR_RF0L, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_RF0F, FIELD_GET(CAN_MCAN_IR_RF0F, val)); - bits |= FIELD_PREP(CAN_STM32FD_IR_RF0N, FIELD_GET(CAN_MCAN_IR_RF0N, val)); - break; + __fallthrough; case CAN_MCAN_IE: - /* Remap IE bits, ignoring unsupported bits */ - bits |= FIELD_PREP(CAN_STM32FD_IE_ARAE, FIELD_GET(CAN_MCAN_IE_ARAE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_PEDE, FIELD_GET(CAN_MCAN_IE_PEDE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_PEAE, FIELD_GET(CAN_MCAN_IE_PEAE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_WDIE, FIELD_GET(CAN_MCAN_IE_WDIE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_BOE, FIELD_GET(CAN_MCAN_IE_BOE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_EWE, FIELD_GET(CAN_MCAN_IE_EWE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_EPE, FIELD_GET(CAN_MCAN_IE_EPE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_ELOE, FIELD_GET(CAN_MCAN_IE_ELOE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_TOOE, FIELD_GET(CAN_MCAN_IE_TOOE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_MRAFE, FIELD_GET(CAN_MCAN_IE_MRAFE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_TSWE, FIELD_GET(CAN_MCAN_IE_TSWE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_TEFLE, FIELD_GET(CAN_MCAN_IE_TEFLE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_TEFFE, FIELD_GET(CAN_MCAN_IE_TEFFE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_TEFNE, FIELD_GET(CAN_MCAN_IE_TEFNE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_TFEE, FIELD_GET(CAN_MCAN_IE_TFEE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_TCFE, FIELD_GET(CAN_MCAN_IE_TCFE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_TCE, FIELD_GET(CAN_MCAN_IE_TCE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_HPME, FIELD_GET(CAN_MCAN_IE_HPME, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_RF1LE, FIELD_GET(CAN_MCAN_IE_RF1LE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_RF1FE, FIELD_GET(CAN_MCAN_IE_RF1FE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_RF1NE, FIELD_GET(CAN_MCAN_IE_RF1NE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_RF0LE, FIELD_GET(CAN_MCAN_IE_RF0LE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_RF0FE, FIELD_GET(CAN_MCAN_IE_RF0FE, val)); - bits |= FIELD_PREP(CAN_STM32FD_IE_RF0NE, FIELD_GET(CAN_MCAN_IE_RF0NE, val)); + /* Remap IR/IE bits, ignoring unsupported bits */ + /* Group 1 map bits 29-22 (mcan) to 23-16 (stm32fd) */ + bits |= ((val & GENMASK(29, 22)) >> 6); + + /* Group 2 map bits 18-14 (mcan) to 15-11 (stm32fd) */ + bits |= ((val & GENMASK(18, 14)) >> 3); + + /* Group 3 map bits 12-6 (mcan) to 10-4 (stm32fd) */ + bits |= ((val & GENMASK(12, 6)) >> 2); + + /* Group 4 map bits 4-2 (mcan) to 3-1 (stm32fd) */ + bits |= ((val & GENMASK(4, 2)) >> 1); + + /* Group 5 map bits 0 (mcan) to 0 (stm32fd) */ + bits |= ((val & GENMASK(0, 0)) >> 0); break; case CAN_MCAN_ILS: /* Only remap ILS groups used in can_mcan.c */ From a02da6f2dd095e6386a6336dd375df308248f137 Mon Sep 17 00:00:00 2001 From: Peter Johanson Date: Fri, 22 Mar 2024 16:54:17 -0700 Subject: [PATCH 1272/2402] input: Add absolute input code for multitouch slot To support multitouch, input devices can report an absolute value to identify the specific slot to which the subsequent data is linked. Add a new code for `INPUT_ABS_MT_SLOT` for this purpose. Signed-off-by: Peter Johanson --- include/zephyr/dt-bindings/input/input-event-codes.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/zephyr/dt-bindings/input/input-event-codes.h b/include/zephyr/dt-bindings/input/input-event-codes.h index 34dd00f8514..5f75bac26e6 100644 --- a/include/zephyr/dt-bindings/input/input-event-codes.h +++ b/include/zephyr/dt-bindings/input/input-event-codes.h @@ -232,6 +232,7 @@ */ #define INPUT_ABS_BRAKE 0x0a /**< Absolute brake position */ #define INPUT_ABS_GAS 0x09 /**< Absolute gas position */ +#define INPUT_ABS_MT_SLOT 0x2f /**< Absolute multitouch slot identifier */ #define INPUT_ABS_RUDDER 0x07 /**< Absolute rudder position */ #define INPUT_ABS_RX 0x03 /**< Absolute rotation around X axis */ #define INPUT_ABS_RY 0x04 /**< Absolute rotation around Y axis */ From 9bf0a24f2e08eb55067c666d83c0d05bfd4ef825 Mon Sep 17 00:00:00 2001 From: Kevin ORourke Date: Thu, 21 Mar 2024 09:09:24 +0100 Subject: [PATCH 1273/2402] drivers: clock_control: stm32: clock_control_on Make clock_control_on for STM32 behave the same as the HAL, delaying after enabling peripheral clocks. Otherwise it may return before the clock is actually enabled, causing subsequent writes to peripheral registers to be silently ignored. Signed-off-by: Kevin ORourke --- drivers/clock_control/clock_stm32_ll_common.c | 6 ++++++ drivers/clock_control/clock_stm32_ll_h5.c | 4 ++++ drivers/clock_control/clock_stm32_ll_h7.c | 6 ++++++ drivers/clock_control/clock_stm32_ll_u5.c | 4 ++++ drivers/clock_control/clock_stm32_ll_wba.c | 5 +++++ 5 files changed, 25 insertions(+) diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index d3adbe62535..024e3365616 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -200,6 +200,7 @@ static inline int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) { struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); + volatile int temp; ARG_UNUSED(dev); @@ -210,6 +211,11 @@ static inline int stm32_clock_control_on(const struct device *dev, sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr); + /* Delay after enabling the clock, to allow it to become active. + * See (for example) RM0440 7.2.17 + */ + temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); + UNUSED(temp); return 0; } diff --git a/drivers/clock_control/clock_stm32_ll_h5.c b/drivers/clock_control/clock_stm32_ll_h5.c index f6f0bbb0033..28e2dd3e009 100644 --- a/drivers/clock_control/clock_stm32_ll_h5.c +++ b/drivers/clock_control/clock_stm32_ll_h5.c @@ -145,6 +145,7 @@ static inline int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) { struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); + volatile int temp; ARG_UNUSED(dev); @@ -155,6 +156,9 @@ static inline int stm32_clock_control_on(const struct device *dev, sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr); + /* Delay after enabling the clock, to allow it to become active */ + temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); + UNUSED(temp); return 0; } diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index 871b1d50a3a..e4d78e5ce60 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -360,6 +360,7 @@ static inline int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) { struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); + volatile int temp; ARG_UNUSED(dev); @@ -371,6 +372,11 @@ static inline int stm32_clock_control_on(const struct device *dev, z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY); sys_set_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr); + /* Delay after enabling the clock, to allow it to become active. + * See RM0433 8.5.10 "Clock enabling delays" + */ + temp = sys_read32(STM32H7_BUS_CLK_REG + pclken->bus); + UNUSED(temp); z_stm32_hsem_unlock(CFG_HW_RCC_SEMID); diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c index 8fe0608d50c..ec4d11546f3 100644 --- a/drivers/clock_control/clock_stm32_ll_u5.c +++ b/drivers/clock_control/clock_stm32_ll_u5.c @@ -149,6 +149,7 @@ static inline int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) { struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); + volatile int temp; ARG_UNUSED(dev); @@ -159,6 +160,9 @@ static inline int stm32_clock_control_on(const struct device *dev, sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr); + /* Delay after enabling the clock, to allow it to become active */ + temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); + UNUSED(temp); return 0; } diff --git a/drivers/clock_control/clock_stm32_ll_wba.c b/drivers/clock_control/clock_stm32_ll_wba.c index 5cc3b8651c7..c11aec07146 100644 --- a/drivers/clock_control/clock_stm32_ll_wba.c +++ b/drivers/clock_control/clock_stm32_ll_wba.c @@ -62,6 +62,7 @@ static inline int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) { struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); + volatile int temp; ARG_UNUSED(dev); @@ -72,6 +73,10 @@ static inline int stm32_clock_control_on(const struct device *dev, sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr); + /* Delay after enabling the clock, to allow it to become active */ + temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); + UNUSED(temp); + return 0; } From 9dd87a719433fa76ab35000c808b7988198a7b5a Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Wed, 20 Mar 2024 16:41:25 +0100 Subject: [PATCH 1274/2402] net: buf: Support copying of user data This functionality is useful on the following scenario: 1) The first buffer in a net_pkt contains user data which is relevant for the (whole) net_pkt. 2) When inserting a new buffer in front of the net_pkt, the (previously) first buffer (and its user data) are no longer accessible via net_pkt->buffer. 3) net_buf_user_data_copy() allows to simply copy the user data from the old to the new first buffer. Signed-off-by: Reto Schneider --- include/zephyr/net/buf.h | 11 +++++++++++ subsys/net/buf.c | 18 ++++++++++++++++++ tests/net/buf/src/main.c | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+) diff --git a/include/zephyr/net/buf.h b/include/zephyr/net/buf.h index 8b6ebdcafd9..18ff833a38c 100644 --- a/include/zephyr/net/buf.h +++ b/include/zephyr/net/buf.h @@ -1467,6 +1467,17 @@ static inline void * __must_check net_buf_user_data(const struct net_buf *buf) return (void *)buf->user_data; } +/** + * @brief Copy user data from one to another buffer. + * + * @param dst A valid pointer to a buffer gettings its user data overwritten. + * @param src A valid pointer to a buffer gettings its user data copied. User data size must be + * equal to or exceed @a dst. + * + * @return 0 on success or negative error number on failure. + */ +int net_buf_user_data_copy(struct net_buf *dst, const struct net_buf *src); + /** * @brief Initialize buffer with the given headroom. * diff --git a/subsys/net/buf.c b/subsys/net/buf.c index 7a82c83ddb7..1101a2b0adb 100644 --- a/subsys/net/buf.c +++ b/subsys/net/buf.c @@ -542,6 +542,24 @@ struct net_buf *net_buf_clone(struct net_buf *buf, k_timeout_t timeout) return clone; } +int net_buf_user_data_copy(struct net_buf *dst, const struct net_buf *src) +{ + __ASSERT_NO_MSG(dst); + __ASSERT_NO_MSG(src); + + if (dst == src) { + return 0; + } + + if (dst->user_data_size < src->user_data_size) { + return -EINVAL; + } + + memcpy(dst->user_data, src->user_data, src->user_data_size); + + return 0; +} + struct net_buf *net_buf_frag_last(struct net_buf *buf) { __ASSERT_NO_MSG(buf); diff --git a/tests/net/buf/src/main.c b/tests/net/buf/src/main.c index d9a54f3a28e..5d2cb451c16 100644 --- a/tests/net/buf/src/main.c +++ b/tests/net/buf/src/main.c @@ -756,6 +756,39 @@ ZTEST(net_buf_tests, test_net_buf_user_data) net_buf_unref(buf); } +ZTEST(net_buf_tests, test_net_buf_user_data_copy) +{ + struct net_buf *buf_user_data_small, *buf_user_data_big; + uint32_t *src_user_data, *dst_user_data; + + buf_user_data_small = net_buf_alloc_len(&bufs_pool, 1, K_NO_WAIT); + zassert_not_null(buf_user_data_small, "Failed to get buffer"); + src_user_data = net_buf_user_data(buf_user_data_small); + *src_user_data = 0xAABBCCDD; + + /* Happy case: Size of user data in destination buf is bigger than the source buf one */ + buf_user_data_big = net_buf_alloc_len(&var_pool, 1, K_NO_WAIT); + zassert_not_null(buf_user_data_big, "Failed to get buffer"); + dst_user_data = net_buf_user_data(buf_user_data_big); + *dst_user_data = 0x11223344; + + zassert_ok(net_buf_user_data_copy(buf_user_data_big, buf_user_data_small)); + zassert_equal(*src_user_data, 0xAABBCCDD); + + /* Error case: User data size of destination buffer is too small */ + zassert_not_ok(net_buf_user_data_copy(buf_user_data_small, buf_user_data_big), + "User data size in destination buffer too small"); + + net_buf_unref(buf_user_data_big); + + /* Corner case: Same buffer used as source and target */ + zassert_ok(net_buf_user_data_copy(buf_user_data_small, buf_user_data_small), + "No-op is tolerated"); + zassert_equal(*src_user_data, 0xAABBCCDD, "User data remains the same"); + + net_buf_unref(buf_user_data_small); +} + ZTEST(net_buf_tests, test_net_buf_comparison) { struct net_buf *buf; From 3fde2c50c6eff593317ec8e6bd6771e4101864ea Mon Sep 17 00:00:00 2001 From: Marcin Szkudlinski Date: Mon, 4 Mar 2024 13:25:53 +0100 Subject: [PATCH 1275/2402] tracing: add intel ADSP memory window backend This commits adds a tracing backend based on Intel ADSP debug memory window Signed-off-by: Marcin Szkudlinski --- .../common/include/adsp_debug_window.h | 4 ++ subsys/tracing/CMakeLists.txt | 5 ++ subsys/tracing/Kconfig | 8 +++ .../tracing_backend_adsp_memory_window.c | 65 +++++++++++++++++++ subsys/tracing/tracing_core.c | 2 + 5 files changed, 84 insertions(+) create mode 100644 subsys/tracing/tracing_backend_adsp_memory_window.c diff --git a/soc/intel/intel_adsp/common/include/adsp_debug_window.h b/soc/intel/intel_adsp/common/include/adsp_debug_window.h index 868d549c5e5..e4e09f70aed 100644 --- a/soc/intel/intel_adsp/common/include/adsp_debug_window.h +++ b/soc/intel/intel_adsp/common/include/adsp_debug_window.h @@ -41,12 +41,16 @@ #define ADSP_DW_SLOT_SIZE ADSP_DW_PAGE_SIZE #define ADSP_DW_SLOT_COUNT 15 +/* debug window slots usage */ +#define ADSP_DW_SLOT_NUM_TRACE 1 + /* debug log slot types */ #define ADSP_DW_SLOT_UNUSED 0x00000000 #define ADSP_DW_SLOT_CRITICAL_LOG 0x54524300 #define ADSP_DW_SLOT_DEBUG_LOG 0x474f4c00 /* byte 0: core ID */ #define ADSP_DW_SLOT_GDB_STUB 0x42444700 #define ADSP_DW_SLOT_TELEMETRY 0x4c455400 +#define ADSP_DW_SLOT_TRACE 0x54524143 #define ADSP_DW_SLOT_BROKEN 0x44414544 /* for debug and critical types */ diff --git a/subsys/tracing/CMakeLists.txt b/subsys/tracing/CMakeLists.txt index 6d9bb689f00..98c0939c982 100644 --- a/subsys/tracing/CMakeLists.txt +++ b/subsys/tracing/CMakeLists.txt @@ -41,6 +41,11 @@ zephyr_sources_ifdef( tracing_backend_ram.c ) +zephyr_sources_ifdef( + CONFIG_TRACING_BACKEND_ADSP_MEMORY_WINDOW + tracing_backend_adsp_memory_window.c + ) + endif() if(NOT CONFIG_PERCEPIO_TRACERECORDER AND NOT CONFIG_TRACING_CTF diff --git a/subsys/tracing/Kconfig b/subsys/tracing/Kconfig index d7aa7b12e44..ea51c7dabc4 100644 --- a/subsys/tracing/Kconfig +++ b/subsys/tracing/Kconfig @@ -160,6 +160,14 @@ config TRACING_BACKEND_RAM Use a ram buffer to output tracing data which can be dumped to a file at runtime with a debugger. See gdb dump binary memory documentation for example. + +config TRACING_BACKEND_ADSP_MEMORY_WINDOW + bool "Memory window in RAM" + depends on SOC_FAMILY_INTEL_ADSP + depends on TRACING_SYNC + help + Use ADSP memory debug memory window to output tracing data + endchoice config RAM_TRACING_BUFFER_SIZE diff --git a/subsys/tracing/tracing_backend_adsp_memory_window.c b/subsys/tracing/tracing_backend_adsp_memory_window.c new file mode 100644 index 00000000000..2efcb6477f3 --- /dev/null +++ b/subsys/tracing/tracing_backend_adsp_memory_window.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +/* structure of memory window */ +struct tracing_backend_adsp_memory_window { + uint32_t head_offset; /* offset of the first not used byte in data[] */ + uint8_t data[]; /* tracing data */ +} __packed __aligned(8); + +#define ADSP_TRACING_WINDOW_DATA_SIZE \ + (ADSP_DW_SLOT_SIZE - offsetof(struct tracing_backend_adsp_memory_window, data)) + +static volatile struct tracing_backend_adsp_memory_window *mem_window; + +static void tracing_backend_adsp_memory_window_output( + const struct tracing_backend *backend, + uint8_t *data, uint32_t length) +{ + /* copy data to ring buffer, + * to make FW part fast, there's no sync with the data reader + * the reader MUST read data before they got overwritten + */ + size_t to_copy = MIN(length, ADSP_TRACING_WINDOW_DATA_SIZE - mem_window->head_offset); + + memcpy((void *)(mem_window->data + mem_window->head_offset), data, to_copy); + + length -= to_copy; + if (length) { + memcpy((void *)mem_window->data, data + to_copy, length); + mem_window->head_offset = length; + } else + mem_window->head_offset += to_copy; +} + +static void tracing_backend_adsp_memory_window_init(void) +{ + volatile struct adsp_debug_window *window = ADSP_DW; + + window->descs[ADSP_DW_SLOT_NUM_TRACE].type = ADSP_DW_SLOT_TRACE; + window->descs[ADSP_DW_SLOT_NUM_TRACE].resource_id = 0; + mem_window = (struct tracing_backend_adsp_memory_window *) + ADSP_DW->slots[ADSP_DW_SLOT_NUM_TRACE]; + + mem_window->head_offset = 0; +} + +const struct tracing_backend_api tracing_backend_adsp_memory_window_api = { + .init = tracing_backend_adsp_memory_window_init, + .output = tracing_backend_adsp_memory_window_output +}; + +TRACING_BACKEND_DEFINE(tracing_backend_adsp_memory_window, tracing_backend_adsp_memory_window_api); diff --git a/subsys/tracing/tracing_core.c b/subsys/tracing/tracing_core.c index aa41068b402..85dae090526 100644 --- a/subsys/tracing/tracing_core.c +++ b/subsys/tracing/tracing_core.c @@ -29,6 +29,8 @@ #define TRACING_BACKEND_NAME "tracing_backend_posix" #elif defined CONFIG_TRACING_BACKEND_RAM #define TRACING_BACKEND_NAME "tracing_backend_ram" +#elif defined CONFIG_TRACING_BACKEND_ADSP_MEMORY_WINDOW +#define TRACING_BACKEND_NAME "tracing_backend_adsp_memory_window" #else #define TRACING_BACKEND_NAME "" #endif From a0d75923aa5d2139d53b08ccc5119d1944bc693c Mon Sep 17 00:00:00 2001 From: Charles Dias Date: Sat, 9 Mar 2024 18:30:24 -0300 Subject: [PATCH 1276/2402] boards: shields: Add Seeed Studio XIAO Expansion Board Add Seeed Studio XIAO Expansion Board: - User button - SSD1306 128x64 pixels - MicroSD - PFC8563 RTC Signed-off-by: Charles Dias --- .../Kconfig.defconfig | 27 +++++++ .../seeed_xiao_expansion_board/Kconfig.shield | 5 ++ .../doc/img/seeed_xiao_expansion_board.webp | Bin 0 -> 24712 bytes .../seeed_xiao_expansion_board/doc/index.rst | 76 ++++++++++++++++++ .../seeed_xiao_expansion_board.overlay | 65 +++++++++++++++ 5 files changed, 173 insertions(+) create mode 100644 boards/shields/seeed_xiao_expansion_board/Kconfig.defconfig create mode 100644 boards/shields/seeed_xiao_expansion_board/Kconfig.shield create mode 100644 boards/shields/seeed_xiao_expansion_board/doc/img/seeed_xiao_expansion_board.webp create mode 100644 boards/shields/seeed_xiao_expansion_board/doc/index.rst create mode 100644 boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay diff --git a/boards/shields/seeed_xiao_expansion_board/Kconfig.defconfig b/boards/shields/seeed_xiao_expansion_board/Kconfig.defconfig new file mode 100644 index 00000000000..ccc874d270b --- /dev/null +++ b/boards/shields/seeed_xiao_expansion_board/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2024 Charles Dias +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_SEEED_XIAO_EXPANSION_BOARD + +if DISPLAY + +if LVGL + +config LV_Z_VDB_SIZE + default 64 + +config LV_DPI_DEF + default 148 + +config LV_Z_BITS_PER_PIXEL + default 1 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_1 +endchoice + +endif # LVGL + +endif # DISPLAY + +endif # SHIELD_SEEED_XIAO_EXPANSION_BOARD diff --git a/boards/shields/seeed_xiao_expansion_board/Kconfig.shield b/boards/shields/seeed_xiao_expansion_board/Kconfig.shield new file mode 100644 index 00000000000..a7665933c8c --- /dev/null +++ b/boards/shields/seeed_xiao_expansion_board/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Charles Dias +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_SEEED_XIAO_EXPANSION_BOARD + def_bool $(shields_list_contains,seeed_xiao_expansion_board) diff --git a/boards/shields/seeed_xiao_expansion_board/doc/img/seeed_xiao_expansion_board.webp b/boards/shields/seeed_xiao_expansion_board/doc/img/seeed_xiao_expansion_board.webp new file mode 100644 index 0000000000000000000000000000000000000000..4a2c6b8df96635254821933afacf0d5f36fcd6ff GIT binary patch literal 24712 zcmV(oK=Hp)Nk&G1U;qGDMM6+kP&il$0000G0002L0RVFW06|PpNHP!r00HoZ{r~#3 z{r^3ZkRZjOg0-d8-Cd^CXLWaXoo|&{^prj1xl3*J8SYSAi$nBr0eIz=SCZ%R z@w^rh69B9k`uz5<;*HqQko@tgJ|I?IX1{x@5~U}f7${V>RH2NI_5=$PuS0bxt0iq` zOED7mjRoa4r*01uAR`jdra3EGijJ^{XzSZc{e_1Acc{Rx#t4kSbEwGjvm-=>dOs>P zduM=pv0-iOm&+qS8`-(3>Gk%4Sb1^)MY(rU%i(sY z0HxOdw|Rd-(tySyi_xAlKWIlzFW$@jX^0F_XsyA7xLw_#(|xpWOV%5Hq@>wchlmxs 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It enables +building prototypes and projects in an easy and quick way. With its rich +peripherals, you could explore the infinite possibilities of Seeed Studio +XIAO series. + +.. figure:: img/seeed_xiao_expansion_board.webp + :align: center + :alt: Seeed Studio XIAO Expansion Board + + Seeed Studio XIAO Expansion Board (Credit: Seeed Studio) + +Pin Assignments +=============== + ++-----------------------+---------------------------------------------+ +| Shield Connector Pin | Function | ++=======================+=============================================+ +| 0 | Grove*1 (A0, D0) | ++-----------------------+---------------------------------------------+ +| 1 | User button | ++-----------------------+---------------------------------------------+ +| 2 | MicroSD SPI CSn | ++-----------------------+---------------------------------------------+ +| 3 | Buzzer(A3) | ++-----------------------+---------------------------------------------+ +| 4 | Grove*2 I2C SDA | ++-----------------------+---------------------------------------------+ +| 5 | Grove*2 I2C SCL | ++-----------------------+---------------------------------------------+ +| 6 | Grove*1 UART TX | ++-----------------------+---------------------------------------------+ +| 7 | Grove*1 UART RX | ++-----------------------+---------------------------------------------+ +| 8 | MicroSD SPI SCK (Serial Clock Input) | ++-----------------------+---------------------------------------------+ +| 9 | MicroSD SPI MISO (Serial Data Input) | ++-----------------------+---------------------------------------------+ +| 10 | MicroSD SPI MOSI (Serial Data Output) | ++-----------------------+---------------------------------------------+ + +Programming +*********** + +LED Button Sample +================= + +Set ``-DSHIELD=seeed_xiao_expansion_board`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: xiao_ble/nrf52840 + :shield: seeed_xiao_expansion_board + :goals: build + +LVGL Basic Sample +========================== + +Set ``-DSHIELD=seeed_xiao_expansion_board`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/display/lvgl + :board: xiao_ble/nrf52840 + :shield: seeed_xiao_expansion_board + :goals: build + +.. _Seeed Studio XIAO series: + https://www.seeedstudio.com/XIAO-c-1964.html diff --git a/boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay b/boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay new file mode 100644 index 00000000000..cd318d5fe50 --- /dev/null +++ b/boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024 Charles Dias + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,display = &ssd1306_128x64; + zephyr,rtc = &pfc8563_rtc; + }; + + buttons { + compatible = "gpio-keys"; + xiao_button0: button_0 { + gpios = <&xiao_d 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; + + aliases { + sw0 = &xiao_button0; + rtc = &pfc8563_rtc; + }; +}; + +&xiao_i2c { + status = "okay"; + + ssd1306_128x64: ssd1306@3c { + compatible = "solomon,ssd1306fb"; + reg = <0x3c>; + width = <128>; + height = <64>; + segment-offset = <0>; + page-offset = <0>; + display-offset = <0>; + multiplex-ratio = <63>; + segment-remap; + com-invdir; + prechargep = <0x22>; + }; + + pfc8563_rtc: pfc8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + status = "okay"; + }; +}; + +&xiao_spi { + status = "okay"; + cs-gpios = <&xiao_d 2 GPIO_ACTIVE_LOW>; + + sdhc0: sdhc@0 { + compatible = "zephyr,sdhc-spi-slot"; + reg = <0>; + status = "okay"; + mmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + spi-max-frequency = <24000000>; + }; +}; From 9fd211a3f8e2c7969aa029497833f4528851d444 Mon Sep 17 00:00:00 2001 From: David Brown Date: Thu, 22 Feb 2024 13:07:26 -0700 Subject: [PATCH 1277/2402] boards: arm: sparkfun_pro_micro_rp2040: Add RGB LED The SparkFun Pro Micro RP2040 board has an WS2812-style RGB LED connected to a GPIO pin. Add this to the devicetree so that this device can be used. Signed-off-by: David Brown --- .../sparkfun_pro_micro_rp2040-pinctrl.dtsi | 6 +++++ .../sparkfun_pro_micro_rp2040.dts | 24 +++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi index 3bca8b4f384..5b9c353f802 100644 --- a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi @@ -49,4 +49,10 @@ clocks_default: clocks_default { }; + + ws2812_pio0_default: ws2812_pio_default { + ws2812 { + pinmux = ; + }; + }; }; diff --git a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts index 1d92bcf1cba..43761b85a14 100644 --- a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts @@ -10,6 +10,7 @@ #include "sparkfun_pro_micro_rp2040-pinctrl.dtsi" #include "sparkfun_pro_micro_connector.dtsi" #include +#include / { chosen { @@ -22,6 +23,7 @@ aliases { watchdog0 = &wdt0; + led-strip = &ws2812; }; }; @@ -96,6 +98,28 @@ pinctrl-names = "default"; }; +&pio0 { + status = "okay"; + + pio-ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio0_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + ws2812: ws2812 { + status = "okay"; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + chain-length = <1>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; zephyr_udc0: &usbd { status = "okay"; From 0e94934c4b35617302de30b97e4cf0f362a4ed50 Mon Sep 17 00:00:00 2001 From: Mayank Mahajan Date: Tue, 13 Feb 2024 14:44:45 +0530 Subject: [PATCH 1278/2402] Add: Support for pyocd runner for mr_canhubk3 board Modifying board.cmake file of mr_canhubk3 for pyocd support. Signed-off-by: Mayank Mahajan --- boards/nxp/mr_canhubk3/board.cmake | 2 ++ boards/nxp/mr_canhubk3/doc/index.rst | 15 ++++++++++----- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/boards/nxp/mr_canhubk3/board.cmake b/boards/nxp/mr_canhubk3/board.cmake index 5f51e931a7b..c75ff6778b8 100644 --- a/boards/nxp/mr_canhubk3/board.cmake +++ b/boards/nxp/mr_canhubk3/board.cmake @@ -12,6 +12,8 @@ else() endif() board_runner_args(jlink "--device=S32K344" "--reset-after-load") +board_runner_args(pyocd "--target=s32k344") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/trace32.board.cmake) diff --git a/boards/nxp/mr_canhubk3/doc/index.rst b/boards/nxp/mr_canhubk3/doc/index.rst index 8ae701e3d30..7ea37ee1b08 100644 --- a/boards/nxp/mr_canhubk3/doc/index.rst +++ b/boards/nxp/mr_canhubk3/doc/index.rst @@ -266,9 +266,10 @@ Programming and Debugging Applications for the ``mr_canhubk3`` board can be built in the usual way as documented in :ref:`build_an_application`. -This board configuration supports `Lauterbach TRACE32`_ and `SEGGER J-Link`_ +This board configuration supports `Lauterbach TRACE32`_, `SEGGER J-Link`_ and `pyOCD`_ West runners for flashing and debugging applications. Follow the steps described -in :ref:`lauterbach-trace32-debug-host-tools` and :ref:`jlink-debug-host-tools`, +in :ref:`lauterbach-trace32-debug-host-tools`, :ref:`jlink-debug-host-tools` and +:ref:`pyocd-debug-host-tools`, to setup the flash and debug host tools for these runners, respectively. The default runner is J-Link. @@ -276,7 +277,8 @@ Flashing ======== Run the ``west flash`` command to flash the application using SEGGER J-Link. -Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32. +Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32, or +``west flash -r pyocd``` to use pyOCD. The Lauterbach TRACE32 runner supports additional options that can be passed through command line: @@ -309,8 +311,8 @@ Debugging ========= Run the ``west debug`` command to start a GDB session using SEGGER J-Link. -Alternatively, run ``west debug -r trace32`` to launch the Lauterbach TRACE32 -software debugging interface. +Alternatively, run ``west debug -r trace32`` or ``west debug -r pyocd`` +to launch the Lauterbach TRACE32 or pyOCD software debugging interface respectively. References ********** @@ -337,3 +339,6 @@ References .. _SEGGER J-Link: https://wiki.segger.com/NXP_S32K3xx + +.. _pyOCD: + https://pyocd.io/ From 4045975c80763e6b26c65e83aa8e2035439c0c21 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Thu, 9 Nov 2023 08:08:11 -0600 Subject: [PATCH 1279/2402] drivers: timer: NXP OS Timer updated for low power modes Add ability to set a wakeup counter in case OS Timer is disabled in certain low power modes. Also add code to compensate the tick value. Signed-off-by: Mahesh Mahadevan --- drivers/timer/Kconfig.mcux_os | 10 ++ drivers/timer/mcux_os_timer.c | 161 +++++++++++++++++++++++++-- dts/bindings/timer/nxp,os-timer.yaml | 7 ++ 3 files changed, 171 insertions(+), 7 deletions(-) diff --git a/drivers/timer/Kconfig.mcux_os b/drivers/timer/Kconfig.mcux_os index 972a669c86e..22aef2ccdde 100644 --- a/drivers/timer/Kconfig.mcux_os +++ b/drivers/timer/Kconfig.mcux_os @@ -11,3 +11,13 @@ config MCUX_OS_TIMER help This module implements a kernel device driver for the NXP OS event timer and provides the standard "system clock driver" interfaces. + +if MCUX_OS_TIMER + +config MCUX_OS_TIMER_PM_POWERED_OFF + bool "Reinitialize the OS Timer" + help + OS Timer is turned off in certain low power modes. When this option is + picked, OS Timer will take steps to store state and reinitialize on wakeups. + +endif # MCUX_OS_TIMER diff --git a/drivers/timer/mcux_os_timer.c b/drivers/timer/mcux_os_timer.c index f65459505a5..c278f59ed95 100644 --- a/drivers/timer/mcux_os_timer.c +++ b/drivers/timer/mcux_os_timer.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include "fsl_ostimer.h" #include "fsl_power.h" @@ -27,13 +29,26 @@ static struct k_spinlock lock; static uint64_t last_count; static OSTIMER_Type *base; +/* Total cycles of the timer compensated to include the time lost in "sleep/deep sleep" modes. + * This maintains the timer count to account for the case if the OS Timer is reset in + * certain deep sleep modes and the time elapsed when it is powered off. + */ +static uint64_t cyc_sys_compensated; +#if DT_NODE_HAS_STATUS(DT_NODELABEL(standby), okay) && CONFIG_PM +static const struct device *counter_dev; +#endif + +static uint64_t mcux_lpc_ostick_get_compensated_timer_value(void) +{ + return (OSTIMER_GetCurrentTimerValue(base) + cyc_sys_compensated); +} void mcux_lpc_ostick_isr(const void *arg) { ARG_UNUSED(arg); k_spinlock_key_t key = k_spin_lock(&lock); - uint64_t now = OSTIMER_GetCurrentTimerValue(base); + uint64_t now = mcux_lpc_ostick_get_compensated_timer_value(); uint32_t dticks = (uint32_t)((now - last_count) / CYC_PER_TICK); /* Clear interrupt flag by writing 1. */ @@ -54,6 +69,104 @@ void mcux_lpc_ostick_isr(const void *arg) sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1); } +#if DT_NODE_HAS_STATUS(DT_NODELABEL(standby), okay) && CONFIG_PM + +/* The OS Timer is disabled in certain low power modes and cannot wakeup the system + * on timeout. This function will be called by the low power code to allow the + * OS Timer to save off the count if needed and also start a wakeup counter + * that would wakeup the system from deep power down modes. + */ +static uint32_t mcux_lpc_ostick_set_counter_timeout(int32_t curr_timeout) +{ + uint32_t ret = 0; + + if (counter_dev) { + uint32_t timeout; + int32_t ticks; + struct counter_top_cfg top_cfg = { 0 }; + + timeout = k_ticks_to_us_ceil32(curr_timeout); + + ticks = counter_us_to_ticks(counter_dev, timeout); + ticks = CLAMP(ticks, 1, counter_get_max_top_value(counter_dev)); + + top_cfg.ticks = ticks; + top_cfg.callback = NULL; + top_cfg.user_data = NULL; + top_cfg.flags = 0; + if (counter_set_top_value(counter_dev, &top_cfg) != 0) { + /* Setting top value failed, try setting an alarm */ + struct counter_alarm_cfg alarm_cfg; + + alarm_cfg.ticks = ticks; + alarm_cfg.callback = NULL; + alarm_cfg.user_data = NULL; + alarm_cfg.flags = 0; + + if (counter_set_channel_alarm(counter_dev, 0, &alarm_cfg) != 0) { + ret = 1; + goto done; + } + } + +#if CONFIG_MCUX_OS_TIMER_PM_POWERED_OFF + /* Capture the current timer value for cases where it loses its state + * in low power modes. + */ + cyc_sys_compensated += OSTIMER_GetCurrentTimerValue(base); +#endif + + /* Counter is set to wakeup the system after the requested time */ + if (counter_start(counter_dev) != 0) { + ret = 1; + } + } else { + ret = 1; + } + +done: + return ret; +} + +/* After exit from certain low power modes where the OS Timer was disabled, the + * current tick value should be updated to account for the period when the OS Timer + * was disabled. Also in certain cases, the OS Timer might lose its state and needs + * to be reinitialized. + */ +static uint32_t mcux_lpc_ostick_compensate_system_timer(void) +{ + uint32_t ret = 0; + + if (counter_dev) { + uint32_t slept_time_ticks; + uint32_t slept_time_us; + + counter_stop(counter_dev); + + counter_get_value(counter_dev, &slept_time_ticks); + + if (!(counter_is_counting_up(counter_dev))) { + slept_time_ticks = counter_get_top_value(counter_dev) - slept_time_ticks; + } + slept_time_us = counter_ticks_to_us(counter_dev, slept_time_ticks); + cyc_sys_compensated += (k_us_to_ticks_floor32(slept_time_us) * CYC_PER_TICK); + +#if CONFIG_MCUX_OS_TIMER_PM_POWERED_OFF + /* Reactivate os_timer for cases where it loses its state */ + OSTIMER_Init(base); +#endif + + /* Announce the time slept to the kernel*/ + mcux_lpc_ostick_isr(NULL); + } else { + ret = 1; + } + + return ret; +} + +#endif + void sys_clock_set_timeout(int32_t ticks, bool idle) { ARG_UNUSED(idle); @@ -63,11 +176,28 @@ void sys_clock_set_timeout(int32_t ticks, bool idle) return; } +#if DT_NODE_HAS_STATUS(DT_NODELABEL(standby), okay) && CONFIG_PM + if (idle) { + /* OS Timer may not be able to wakeup in certain low power modes. + * For these cases, we start a counter that can wakeup + * from low power modes. + */ + if (pm_state_next_get(0)->state == PM_STATE_STANDBY) { + if (mcux_lpc_ostick_set_counter_timeout(ticks) == 0) { + /* A low power counter has been started. No need to + * go further, simply return + */ + return; + } + } + } +#endif + ticks = ticks == K_TICKS_FOREVER ? MAX_TICKS : ticks; ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS); k_spinlock_key_t key = k_spin_lock(&lock); - uint64_t now = OSTIMER_GetCurrentTimerValue(base); + uint64_t now = mcux_lpc_ostick_get_compensated_timer_value(); uint32_t adj, cyc = ticks * CYC_PER_TICK; /* Round up to next tick boundary. */ @@ -83,7 +213,7 @@ void sys_clock_set_timeout(int32_t ticks, bool idle) cyc += CYC_PER_TICK; } - OSTIMER_SetMatchValue(base, cyc + last_count, NULL); + OSTIMER_SetMatchValue(base, cyc + last_count - cyc_sys_compensated, NULL); k_spin_unlock(&lock, key); } @@ -96,7 +226,7 @@ uint32_t sys_clock_elapsed(void) } k_spinlock_key_t key = k_spin_lock(&lock); - uint32_t ret = ((uint32_t)OSTIMER_GetCurrentTimerValue(base) - + uint32_t ret = ((uint32_t)mcux_lpc_ostick_get_compensated_timer_value() - (uint32_t)last_count) / CYC_PER_TICK; k_spin_unlock(&lock, key); @@ -105,12 +235,24 @@ uint32_t sys_clock_elapsed(void) uint32_t sys_clock_cycle_get_32(void) { - return (uint32_t)OSTIMER_GetCurrentTimerValue(base); + return (uint32_t)mcux_lpc_ostick_get_compensated_timer_value(); } uint64_t sys_clock_cycle_get_64(void) { - return OSTIMER_GetCurrentTimerValue(base); + return mcux_lpc_ostick_get_compensated_timer_value(); +} + +void sys_clock_idle_exit(void) +{ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(standby), okay) && CONFIG_PM + /* The tick should be compensated for states where the + * OS Timer is disabled + */ + if (pm_state_next_get(0)->state == PM_STATE_STANDBY) { + mcux_lpc_ostick_compensate_system_timer(); + } +#endif } static int sys_clock_driver_init(void) @@ -129,12 +271,17 @@ static int sys_clock_driver_init(void) /* Initialize the OS timer, setting clock configuration. */ OSTIMER_Init(base); - last_count = OSTIMER_GetCurrentTimerValue(base); + last_count = mcux_lpc_ostick_get_compensated_timer_value(); OSTIMER_SetMatchValue(base, last_count + CYC_PER_TICK, NULL); /* Enable event timer interrupt */ irq_enable(DT_INST_IRQN(0)); +/* On some SoC's, OS Timer cannot wakeup from low power mode in standby modes */ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(standby), okay) && CONFIG_PM + counter_dev = DEVICE_DT_GET_OR_NULL(DT_INST_PHANDLE(0, deep_sleep_counter)); +#endif + return 0; } diff --git a/dts/bindings/timer/nxp,os-timer.yaml b/dts/bindings/timer/nxp,os-timer.yaml index 649bce77c5e..eb945b807fc 100644 --- a/dts/bindings/timer/nxp,os-timer.yaml +++ b/dts/bindings/timer/nxp,os-timer.yaml @@ -13,3 +13,10 @@ properties: interrupts: required: true + + deep-sleep-counter: + type: phandle + description: | + Instance of a counter peripheral. The OS Timer maybe powered off in + certain deep power down modes. The OS Timer driver will use this + counter to wakeup and also to keep track of system time. From f36570a357b12d44bb7f5560d6e6efd9d0ea13d1 Mon Sep 17 00:00:00 2001 From: Dawid Niedzwiecki Date: Mon, 18 Mar 2024 10:34:59 +0100 Subject: [PATCH 1280/2402] ztest: define _POSIX_C_SOURCE macro Add declaration of the _POSIX_C_SOURCE < 200809L for ztest library for declaration of strtok_r and strdup functions. Signed-off-by: Dawid Niedzwiecki --- subsys/testsuite/ztest/CMakeLists.txt | 4 ++++ subsys/testsuite/ztest/src/ztest_posix.c | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/subsys/testsuite/ztest/CMakeLists.txt b/subsys/testsuite/ztest/CMakeLists.txt index 4d29ac033c3..98b1cf17607 100644 --- a/subsys/testsuite/ztest/CMakeLists.txt +++ b/subsys/testsuite/ztest/CMakeLists.txt @@ -15,6 +15,10 @@ if(DEFINED TC_RUNID) endif() zephyr_library() + +# For strtok_r() and strdup() +zephyr_library_compile_options(-D_POSIX_C_SOURCE=200809L) + zephyr_library_sources( src/ztest.c src/ztest_error_hook.c diff --git a/subsys/testsuite/ztest/src/ztest_posix.c b/subsys/testsuite/ztest/src/ztest_posix.c index 438e11a56db..744219538cd 100644 --- a/subsys/testsuite/ztest/src/ztest_posix.c +++ b/subsys/testsuite/ztest/src/ztest_posix.c @@ -4,9 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -#undef _POSIX_C_SOURCE -#define _POSIX_C_SOURCE 200809L - #include #include #include "cmdline.h" /* native_sim command line options header */ From 3664ed64c3c1f4a0e9022a35c021340fed6a2c94 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 8 Nov 2023 08:54:57 -0800 Subject: [PATCH 1281/2402] arch: move arch_interface.h under zephyr/arch arch_interface.h is for architecture and should not be under sys/. So move it under include/zephyr/arch/. Signed-off-by: Daniel Leung --- arch/arm64/core/smp.c | 2 +- arch/riscv/core/pmp.c | 2 +- arch/xtensa/include/xtensa_internal.h | 2 +- drivers/interrupt_controller/intc_cavs.c | 2 +- drivers/sensor/qdec_nxp_s32/qdec_nxp_s32.c | 2 +- include/zephyr/{sys => arch}/arch_interface.h | 6 +++--- include/zephyr/arch/cpu.h | 2 +- include/zephyr/internal/syscall_handler.h | 2 +- include/zephyr/kernel/thread.h | 2 +- include/zephyr/timing/timing.h | 2 +- kernel/include/kernel_arch_interface.h | 4 ++-- samples/kernel/condition_variables/condvar/src/main.c | 1 - samples/kernel/condition_variables/simple/src/main.c | 1 - subsys/shell/modules/device_service.c | 2 +- subsys/testsuite/include/zephyr/interrupt_util.h | 2 +- subsys/testsuite/ztest/include/zephyr/arch/cpu.h | 2 +- tests/arch/common/timing/src/main.c | 2 +- 17 files changed, 18 insertions(+), 20 deletions(-) rename include/zephyr/{sys => arch}/arch_interface.h (99%) diff --git a/arch/arm64/core/smp.c b/arch/arm64/core/smp.c index 97fd60b4236..76ccd770908 100644 --- a/arch/arm64/core/smp.c +++ b/arch/arm64/core/smp.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include "boot.h" diff --git a/arch/riscv/core/pmp.c b/arch/riscv/core/pmp.c index bfeb1c025cd..3807b3b103b 100644 --- a/arch/riscv/core/pmp.c +++ b/arch/riscv/core/pmp.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL diff --git a/arch/xtensa/include/xtensa_internal.h b/arch/xtensa/include/xtensa_internal.h index b97c109a994..60b512ab571 100644 --- a/arch/xtensa/include/xtensa_internal.h +++ b/arch/xtensa/include/xtensa_internal.h @@ -11,7 +11,7 @@ #include #include -#include +#include /** * @ingroup xtensa_internal_apis diff --git a/drivers/interrupt_controller/intc_cavs.c b/drivers/interrupt_controller/intc_cavs.c index 4313bbecfac..47e4940e139 100644 --- a/drivers/interrupt_controller/intc_cavs.c +++ b/drivers/interrupt_controller/intc_cavs.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include "intc_cavs.h" #if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1) diff --git a/drivers/sensor/qdec_nxp_s32/qdec_nxp_s32.c b/drivers/sensor/qdec_nxp_s32/qdec_nxp_s32.c index 1b233d500e5..56e31f357f4 100644 --- a/drivers/sensor/qdec_nxp_s32/qdec_nxp_s32.c +++ b/drivers/sensor/qdec_nxp_s32/qdec_nxp_s32.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #ifndef M_PI #define M_PI 3.14159265358979323846 diff --git a/include/zephyr/sys/arch_interface.h b/include/zephyr/arch/arch_interface.h similarity index 99% rename from include/zephyr/sys/arch_interface.h rename to include/zephyr/arch/arch_interface.h index 0ffc95c663b..9faa9df005f 100644 --- a/include/zephyr/sys/arch_interface.h +++ b/include/zephyr/arch/arch_interface.h @@ -24,8 +24,8 @@ * include/kernel.h and other public headers depend on definitions in this * header. */ -#ifndef ZEPHYR_INCLUDE_SYS_ARCH_INTERFACE_H_ -#define ZEPHYR_INCLUDE_SYS_ARCH_INTERFACE_H_ +#ifndef ZEPHYR_INCLUDE_ARCH_ARCH_INTERFACE_H_ +#define ZEPHYR_INCLUDE_ARCH_ARCH_INTERFACE_H_ #ifndef _ASMLANGUAGE #include @@ -1248,4 +1248,4 @@ void arch_spin_relax(void); #endif /* _ASMLANGUAGE */ -#endif /* ZEPHYR_INCLUDE_SYS_ARCH_INTERFACE_H_ */ +#endif /* ZEPHYR_INCLUDE_ARCH_ARCH_INTERFACE_H_ */ diff --git a/include/zephyr/arch/cpu.h b/include/zephyr/arch/cpu.h index 17ec125b395..11abe8df8c0 100644 --- a/include/zephyr/arch/cpu.h +++ b/include/zephyr/arch/cpu.h @@ -9,7 +9,7 @@ #ifndef ZEPHYR_INCLUDE_ARCH_CPU_H_ #define ZEPHYR_INCLUDE_ARCH_CPU_H_ -#include +#include #if defined(CONFIG_X86) #include diff --git a/include/zephyr/internal/syscall_handler.h b/include/zephyr/internal/syscall_handler.h index a9b9a642c76..d3879621917 100644 --- a/include/zephyr/internal/syscall_handler.h +++ b/include/zephyr/internal/syscall_handler.h @@ -17,7 +17,7 @@ #ifndef _ASMLANGUAGE #include -#include +#include #include #include #include diff --git a/include/zephyr/kernel/thread.h b/include/zephyr/kernel/thread.h index 91cf710e870..c319404f44f 100644 --- a/include/zephyr/kernel/thread.h +++ b/include/zephyr/kernel/thread.h @@ -12,7 +12,7 @@ #endif #include -#include +#include /** * @typedef k_thread_entry_t diff --git a/include/zephyr/timing/timing.h b/include/zephyr/timing/timing.h index a0c4a644abb..d4191d10b3e 100644 --- a/include/zephyr/timing/timing.h +++ b/include/zephyr/timing/timing.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_INCLUDE_TIMING_TIMING_H_ #define ZEPHYR_INCLUDE_TIMING_TIMING_H_ -#include +#include #include #ifdef __cplusplus diff --git a/kernel/include/kernel_arch_interface.h b/kernel/include/kernel_arch_interface.h index 73884463520..a20c7a706bb 100644 --- a/kernel/include/kernel_arch_interface.h +++ b/kernel/include/kernel_arch_interface.h @@ -9,7 +9,7 @@ * @brief Internal kernel APIs implemented at the architecture layer. * * Not all architecture-specific defines are here, APIs that are used - * by public functions and macros are defined in include/sys/arch_interface.h. + * by public functions and macros are defined in include/zephyr/arch/arch_interface.h. * * For all inline functions prototyped here, the implementation is expected * to be provided by arch/ARCH/include/kernel_arch_func.h @@ -18,7 +18,7 @@ #define ZEPHYR_KERNEL_INCLUDE_KERNEL_ARCH_INTERFACE_H_ #include -#include +#include #ifndef _ASMLANGUAGE diff --git a/samples/kernel/condition_variables/condvar/src/main.c b/samples/kernel/condition_variables/condvar/src/main.c index 7f7278814ca..5eb064e4078 100644 --- a/samples/kernel/condition_variables/condvar/src/main.c +++ b/samples/kernel/condition_variables/condvar/src/main.c @@ -5,7 +5,6 @@ */ #include #include -#include #define NUM_THREADS 3 #define TCOUNT 10 diff --git a/samples/kernel/condition_variables/simple/src/main.c b/samples/kernel/condition_variables/simple/src/main.c index d8aba186a3d..6fc2951b72e 100644 --- a/samples/kernel/condition_variables/simple/src/main.c +++ b/samples/kernel/condition_variables/simple/src/main.c @@ -6,7 +6,6 @@ #include #include -#include #define NUM_THREADS 20 #define STACK_SIZE (1024) diff --git a/subsys/shell/modules/device_service.c b/subsys/shell/modules/device_service.c index c11c8b4a7b9..fec4b25f6b9 100644 --- a/subsys/shell/modules/device_service.c +++ b/subsys/shell/modules/device_service.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include static const char *get_device_name(const struct device *dev, char *buf, diff --git a/subsys/testsuite/include/zephyr/interrupt_util.h b/subsys/testsuite/include/zephyr/interrupt_util.h index 61d1206d5f8..0bccd53cc51 100644 --- a/subsys/testsuite/include/zephyr/interrupt_util.h +++ b/subsys/testsuite/include/zephyr/interrupt_util.h @@ -109,7 +109,7 @@ static inline void trigger_irq(int irq) #include #define VECTOR_MASK 0xFF #else -#include +#include #define LOAPIC_ICR_IPI_TEST 0x00004000U #endif diff --git a/subsys/testsuite/ztest/include/zephyr/arch/cpu.h b/subsys/testsuite/ztest/include/zephyr/arch/cpu.h index 5969b0ce109..db65632029e 100644 --- a/subsys/testsuite/ztest/include/zephyr/arch/cpu.h +++ b/subsys/testsuite/ztest/include/zephyr/arch/cpu.h @@ -61,7 +61,7 @@ static inline bool arch_irq_unlocked(unsigned int key) } #endif /* __cplusplus */ -#include +#include #endif /* ZEPHYR_SUBSYS_TESTSUITE_ZTEST_INCLUDE_ARCH_CPU_H */ diff --git a/tests/arch/common/timing/src/main.c b/tests/arch/common/timing/src/main.c index 4beaee01f87..83ff500a114 100644 --- a/tests/arch/common/timing/src/main.c +++ b/tests/arch/common/timing/src/main.c @@ -5,7 +5,7 @@ */ #include #include -#include +#include #if defined(CONFIG_SMP) && CONFIG_MP_MAX_NUM_CPUS > 1 #define SMP_TEST From 6ea749de528387c1e897563b566dfe8a8cf61d90 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 8 Nov 2023 09:05:17 -0800 Subject: [PATCH 1282/2402] arch: rename arch_start_cpu() to arch_cpu_start() Rename arch_start_cpu() to arch_cpu_start() so it belongs to the "cpu" namespace. Signed-off-by: Daniel Leung --- arch/arc/core/smp.c | 4 ++-- arch/arm/core/cortex_a_r/smp.c | 2 +- arch/arm64/core/smp.c | 2 +- arch/riscv/core/smp.c | 2 +- arch/x86/core/intel64/cpu.c | 2 +- doc/kernel/services/smp/smp.rst | 2 +- doc/kernel/services/smp/smpinit.svg | 2 +- doc/releases/migration-guide-3.7.rst | 2 ++ include/zephyr/arch/arch_interface.h | 2 +- kernel/smp.c | 2 +- soc/espressif/esp32/esp32-mp.c | 2 +- soc/intel/intel_adsp/common/multiprocessing.c | 4 ++-- tests/kernel/mp/src/main.c | 6 +++--- tests/kernel/spinlock/src/main.c | 2 +- 14 files changed, 19 insertions(+), 17 deletions(-) diff --git a/arch/arc/core/smp.c b/arch/arc/core/smp.c index 6bc89883fad..767c463180d 100644 --- a/arch/arc/core/smp.c +++ b/arch/arc/core/smp.c @@ -39,7 +39,7 @@ volatile char *arc_cpu_sp; volatile _cpu_t *_curr_cpu[CONFIG_MP_MAX_NUM_CPUS]; /* Called from Zephyr initialization */ -void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz, +void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_t fn, void *arg) { _curr_cpu[cpu_num] = &(_kernel.cpus[cpu_num]); @@ -114,7 +114,7 @@ void arch_secondary_cpu_init(int cpu_num) DT_IRQ(DT_NODELABEL(ici), priority), 0); irq_enable(DT_IRQN(DT_NODELABEL(ici))); #endif - /* call the function set by arch_start_cpu */ + /* call the function set by arch_cpu_start */ fn = arc_cpu_init[cpu_num].fn; fn(arc_cpu_init[cpu_num].arg); diff --git a/arch/arm/core/cortex_a_r/smp.c b/arch/arm/core/cortex_a_r/smp.c index f581c770310..85a8650d02f 100644 --- a/arch/arm/core/cortex_a_r/smp.c +++ b/arch/arm/core/cortex_a_r/smp.c @@ -90,7 +90,7 @@ extern int z_arm_mmu_init(void); #endif /* Called from Zephyr initialization */ -void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_t fn, void *arg) +void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_t fn, void *arg) { int cpu_count, i, j; uint32_t cpu_mpid = 0; diff --git a/arch/arm64/core/smp.c b/arch/arm64/core/smp.c index 76ccd770908..3413a578025 100644 --- a/arch/arm64/core/smp.c +++ b/arch/arm64/core/smp.c @@ -62,7 +62,7 @@ static uint64_t cpu_map[CONFIG_MP_MAX_NUM_CPUS] = { extern void z_arm64_mm_init(bool is_primary_core); /* Called from Zephyr initialization */ -void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz, +void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_t fn, void *arg) { int cpu_count; diff --git a/arch/riscv/core/smp.c b/arch/riscv/core/smp.c index 54de29c0551..fe9f349f6bc 100644 --- a/arch/riscv/core/smp.c +++ b/arch/riscv/core/smp.c @@ -27,7 +27,7 @@ extern void __start(void); void soc_interrupt_init(void); #endif -void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz, +void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_t fn, void *arg) { riscv_cpu_init[cpu_num].fn = fn; diff --git a/arch/x86/core/intel64/cpu.c b/arch/x86/core/intel64/cpu.c index 2a845960b87..f5b3af53fad 100644 --- a/arch/x86/core/intel64/cpu.c +++ b/arch/x86/core/intel64/cpu.c @@ -138,7 +138,7 @@ struct x86_cpuboot x86_cpuboot[] = { * will enter the kernel at fn(arg), running on the specified stack. */ -void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz, +void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_t fn, void *arg) { #if CONFIG_MP_MAX_NUM_CPUS > 1 diff --git a/doc/kernel/services/smp/smp.rst b/doc/kernel/services/smp/smp.rst index 0a94ed022b0..ca1e0149ad5 100644 --- a/doc/kernel/services/smp/smp.rst +++ b/doc/kernel/services/smp/smp.rst @@ -132,7 +132,7 @@ happens on a single CPU before other CPUs are brought online. Just before entering the application :c:func:`main` function, the kernel calls :c:func:`z_smp_init` to launch the SMP initialization process. This enumerates over the configured CPUs, calling into the architecture -layer using :c:func:`arch_start_cpu` for each one. This function is +layer using :c:func:`arch_cpu_start` for each one. This function is passed a memory region to use as a stack on the foreign CPU (in practice it uses the area that will become that CPU's interrupt stack), the address of a local :c:func:`smp_init_top` callback function to diff --git a/doc/kernel/services/smp/smpinit.svg b/doc/kernel/services/smp/smpinit.svg index 13227081b0c..7495df78316 100644 --- a/doc/kernel/services/smp/smpinit.svg +++ b/doc/kernel/services/smp/smpinit.svg @@ -309,7 +309,7 @@ id="tspan3682" x="33.970718" y="46.338062" - style="stroke-width:0.34572953">arch_start_cpu() + style="stroke-width:0.34572953">arch_cpu_start() Date: Thu, 14 Mar 2024 14:48:15 +0200 Subject: [PATCH 1283/2402] soc: rcar_gen3: set correct NUM_IRQS for ARM64 R-Car Gen3 boards Align number of interrupts for ARM64 R-Car Gen3 boards with the documentation. Signed-off-by: Mykola Kvach --- soc/renesas/rcar/rcar_gen3/Kconfig.defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/soc/renesas/rcar/rcar_gen3/Kconfig.defconfig b/soc/renesas/rcar/rcar_gen3/Kconfig.defconfig index 173efde9137..da9a5674d46 100644 --- a/soc/renesas/rcar/rcar_gen3/Kconfig.defconfig +++ b/soc/renesas/rcar/rcar_gen3/Kconfig.defconfig @@ -6,8 +6,7 @@ if SOC_SERIES_RCAR_GEN3 config NUM_IRQS - default 512 if SOC_R8A77951_R7 - default 240 if SOC_R8A77961 || SOC_R8A77951_A57 + default 512 config PINCTRL default y From 0a8ef12c3e7a9a9b71c6db40203ddedbe3171741 Mon Sep 17 00:00:00 2001 From: Fabian Blatz Date: Wed, 20 Mar 2024 08:38:15 +0100 Subject: [PATCH 1284/2402] manifest: update LVGL to v8.4.0 Related to zephyrproject-rtos/lvgl#51 Signed-off-by: Fabian Blatz --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 7cfc6a23391..3df67baa1df 100644 --- a/west.yml +++ b/west.yml @@ -274,7 +274,7 @@ manifest: revision: 1bf2120cffcedae174ae35d695a28a46caefcb23 path: modules/lib/loramac-node - name: lvgl - revision: 2b76c641749725ac90c6ac7959ca7718804cf356 + revision: 2b498e6f36d6b82ae1da12c8b7742e318624ecf5 path: modules/lib/gui/lvgl - name: mbedtls revision: 6ec4abdcda78dfc47315af568f93e5ad4398dea0 From c97a8131c1d9c8fc16d80905f68658d9f2806d5a Mon Sep 17 00:00:00 2001 From: Aleksandr Khromykh Date: Mon, 25 Mar 2024 13:49:26 +0100 Subject: [PATCH 1285/2402] Samples: Bluetooth: HCI: add missed callback pointer USB initialization function mandates pointer to callback. Seems this pointer was missed in hci_usb sample. Commit fixes this. Signed-off-by: Aleksandr Khromykh --- samples/bluetooth/hci_usb/src/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/samples/bluetooth/hci_usb/src/main.c b/samples/bluetooth/hci_usb/src/main.c index 8e91caadd33..c27af0e56db 100644 --- a/samples/bluetooth/hci_usb/src/main.c +++ b/samples/bluetooth/hci_usb/src/main.c @@ -14,7 +14,7 @@ static int enable_usb_device_next(void) { - struct usbd_contex *sample_usbd = sample_usbd_init_device(); + struct usbd_contex *sample_usbd = sample_usbd_init_device(NULL); if (sample_usbd == NULL) { printk("Failed to initialize USB device"); From af311c61aea82927f46c5048713f7b2d1d9ee917 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 24 Mar 2024 21:05:53 +0200 Subject: [PATCH 1286/2402] net: pkt: Add prototype for net_pkt_get_reserve_data The prototype for net_pkt_get_reserve_data() was missing in the header file. Only a debug version of it was set in the net_pkt.h Signed-off-by: Jukka Rissanen --- include/zephyr/net/net_pkt.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/zephyr/net/net_pkt.h b/include/zephyr/net/net_pkt.h index c3ef9418085..c668bc72492 100644 --- a/include/zephyr/net/net_pkt.h +++ b/include/zephyr/net/net_pkt.h @@ -1485,6 +1485,25 @@ void net_pkt_print_frags(struct net_pkt *pkt); #define net_pkt_print_frags(pkt) #endif +/** + * @brief Get a data buffer from a given pool. + * + * @details Normally this version is not useful for applications + * but is mainly used by network fragmentation code. + * + * @param pool The net_buf pool to use. + * @param min_len Minimum length of the requested fragment. + * @param timeout Affects the action taken should the net buf pool be empty. + * If K_NO_WAIT, then return immediately. If K_FOREVER, then + * wait as long as necessary. Otherwise, wait up to the specified time. + * + * @return Network buffer if successful, NULL otherwise. + */ +#if !defined(NET_PKT_DEBUG_ENABLED) +struct net_buf *net_pkt_get_reserve_data(struct net_buf_pool *pool, + size_t min_len, k_timeout_t timeout); +#endif + /** * @brief Get RX DATA buffer from pool. * Normally you should use net_pkt_get_frag() instead. From 3041f05d183e4568e0b12a398f36bb183c95c3de Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 21 Mar 2024 12:30:57 +0100 Subject: [PATCH 1287/2402] tests/bsim/bt l2cap/stress: Be more silent This test was way too verbose (produced a log over 65000 lines long). Let's mute it a bit. If the test fails, developers can raise the log level as needed. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/bluetooth/host/l2cap/stress/prj_syswq.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/bsim/bluetooth/host/l2cap/stress/prj_syswq.conf b/tests/bsim/bluetooth/host/l2cap/stress/prj_syswq.conf index 040efd6df26..3cddbe332cd 100644 --- a/tests/bsim/bluetooth/host/l2cap/stress/prj_syswq.conf +++ b/tests/bsim/bluetooth/host/l2cap/stress/prj_syswq.conf @@ -47,7 +47,7 @@ CONFIG_LOG=y CONFIG_ASSERT=y CONFIG_NET_BUF_POOL_USAGE=y -CONFIG_BT_L2CAP_LOG_LEVEL_DBG=y +# CONFIG_BT_L2CAP_LOG_LEVEL_DBG=y # CONFIG_BT_CONN_LOG_LEVEL_DBG=y CONFIG_LOG_THREAD_ID_PREFIX=y CONFIG_THREAD_NAME=y From 61be043f26da849d4ecf62d3e8bfe61346dbea66 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 12:26:48 +0100 Subject: [PATCH 1288/2402] tests/bsim/sh_common.source: Set a variable with the board target string As now, with hwmv2, boards can have "/" in their name, and the board name is not anymore the complete target name, let's set a new variable with the whole board target name, but converted into the format which can be used in paths. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/sh_common.source | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/bsim/sh_common.source b/tests/bsim/sh_common.source index ddcce6df818..7c29aa41af4 100644 --- a/tests/bsim/sh_common.source +++ b/tests/bsim/sh_common.source @@ -9,6 +9,9 @@ _process_ids=""; #Give a default value to BOARD if it does not have one yet: BOARD="${BOARD:-nrf52_bsim}" +#The board target full string (with qualifiers): +BOARD_TS="${BOARD//\//_}" + function run_in_background(){ $@ & _process_ids="$_process_ids $!" } From 0053f03d595d76ede9ec9609099e5a03b7c6a5f1 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 14:33:46 +0100 Subject: [PATCH 1289/2402] tests/bsim/sh_common.source: Add function to guess test name Some developers want to programmatically get the test name instead of hardcoding it. So let's have a common function for this. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/sh_common.source | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tests/bsim/sh_common.source b/tests/bsim/sh_common.source index 7c29aa41af4..2dac776f024 100644 --- a/tests/bsim/sh_common.source +++ b/tests/bsim/sh_common.source @@ -48,3 +48,20 @@ function Execute() { check_program_exists $1 run_in_background timeout --kill-after=5 -v ${EXECUTE_TIMEOUT} $@ } + +function _guess_test_relpath(){ + local PA="$(realpath --relative-to "${ZEPHYR_BASE}" $(dirname "${BASH_SOURCE[2]}"))" + echo $PA | sed -E 's/\/tests?_scripts//' +} + +# For a caller running from a tests_script/ folder, get the path of its parent +# relative to $ZEPHYR_BASE +function guess_test_relpath(){ + echo $(_guess_test_relpath) +} + +# For a caller running from a tests_script/ folder, get the path of its parent +# relative to $ZEPHYR_BASE, replacing "/" with "_" +function guess_test_long_name(){ + echo $(_guess_test_relpath) | tr / _ +} From 5acc7c48157e605c2eb8c98f999ac379701b2f14 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 11:51:23 +0100 Subject: [PATCH 1290/2402] tests/bsim bt host/adv: Tests scripts cleanup Ensure we call the common source script before using the BOARD variable; Use the common scripts to perform common functions and do a cleanup. Do not set variables to their defaults, set things closer to were they are needed; Do not perform unnecesary checks; And in general avoid unnecessary complexity. Also, remove all timeouts which were unnecessarily too short Signed-off-by: Alberto Escolar Piedras --- .../host/adv/chain/tests_scripts/adv_chain.sh | 1 - .../css_sample_data/test_scripts/_compile.sh | 15 ++++-- .../css_sample_data/test_scripts/_env.sh | 15 ------ .../css_sample_data/test_scripts/run_tests.sh | 48 +++++-------------- .../ead_sample/test_scripts/ead_sample.sh | 1 - .../adv/extended/tests_scripts/ext_adv.sh | 1 - .../extended/tests_scripts/ext_adv_conn.sh | 1 - .../extended/tests_scripts/ext_adv_conn_x5.sh | 1 - .../adv/periodic/tests_scripts/per_adv.sh | 1 - .../periodic/tests_scripts/per_adv_conn.sh | 1 - .../tests_scripts/per_adv_conn_privacy.sh | 1 - .../tests_scripts/per_adv_long_data.sh | 1 - .../host/adv/resume/test_scripts/_compile.sh | 19 ++++---- .../host/adv/resume/test_scripts/_env.sh | 11 ----- .../adv/resume/test_scripts/run_adv_resume.sh | 7 +-- .../resume/test_scripts/run_adv_resume_2.sh | 8 ++-- 16 files changed, 36 insertions(+), 96 deletions(-) delete mode 100755 tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_env.sh delete mode 100755 tests/bsim/bluetooth/host/adv/resume/test_scripts/_env.sh diff --git a/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh b/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh index ab3f1c07896..b50de2bf31a 100755 --- a/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh +++ b/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh @@ -8,7 +8,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="adv_chain" verbosity_level=2 -EXECUTE_TIMEOUT=10 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh index 42376ab5231..af200055c53 100755 --- a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh @@ -1,11 +1,16 @@ -#!/bin/env bash +#!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -source "${bash_source_dir}/_env.sh" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -west build -b nrf52_bsim && \ - cp -v build/zephyr/zephyr.exe "${test_exe}" +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 + +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)" compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_env.sh b/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_env.sh deleted file mode 100755 index c0d2ab3b7eb..00000000000 --- a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_env.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -test_name="$(basename "$(realpath "$bash_source_dir/..")")" -bsim_bin="${BSIM_OUT_PATH}/bin" -verbosity_level=2 -BOARD="${BOARD:-nrf52_bsim}" -simulation_id="$test_name" -test_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_adv_encrypted_${test_name}_prj_conf" diff --git a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/run_tests.sh b/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/run_tests.sh index 13dc7f31ef2..eb7a8b0c954 100755 --- a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/run_tests.sh +++ b/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/run_tests.sh @@ -1,67 +1,41 @@ -#!/bin/env bash +#!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" - -process_ids="" -exit_code=0 - -function Execute() { - if [ ! -f $1 ]; then - echo -e " \e[91m$(pwd)/$(basename $1) cannot be found (did you forget to\ - compile it?)\e[39m" - exit 1 - fi - timeout 30 $@ & - process_ids="$process_ids $!" -} - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" +simulation_id="$(guess_test_long_name)" +verbosity_level=2 +test_exe="bs_${BOARD}_$(guess_test_long_name)_prj_conf" cd ${BSIM_OUT_PATH}/bin data_set=1 -Execute "$test_exe" \ +Execute ./"$test_exe" \ -v=${verbosity_level} -s="${simulation_id}_${data_set}" -d=0 -testid=central \ -RealEncryption=1 -argstest data-set="${data_set}" -Execute "$test_exe" \ +Execute ./"$test_exe" \ -v=${verbosity_level} -s="${simulation_id}_${data_set}" -d=1 -testid=peripheral \ -RealEncryption=1 -argstest data-set="${data_set}" Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s="${simulation_id}_${data_set}" \ -D=2 -sim_length=60e6 $@ -for process_id in $process_ids; do - wait $process_id || let "exit_code=$?" -done -process_ids='' +wait_for_background_jobs data_set=2 -Execute "$test_exe" \ +Execute ./"$test_exe" \ -v=${verbosity_level} -s="${simulation_id}_${data_set}" -d=0 -testid=central \ -RealEncryption=1 -argstest data-set="${data_set}" -Execute "$test_exe" \ +Execute ./"$test_exe" \ -v=${verbosity_level} -s="${simulation_id}_${data_set}" -d=1 -testid=peripheral \ -RealEncryption=1 -argstest data-set="${data_set}" Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s="${simulation_id}_${data_set}" \ -D=2 -sim_length=60e6 $@ -for process_id in $process_ids; do - wait $process_id || let "exit_code=$?" -done - -if [ ${exit_code} -ne 0 ]; then - exit_code=1 -fi - -exit $exit_code # the last exit code != 0 +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/adv/encrypted/ead_sample/test_scripts/ead_sample.sh b/tests/bsim/bluetooth/host/adv/encrypted/ead_sample/test_scripts/ead_sample.sh index 926a42d739f..8a7c0ca0696 100755 --- a/tests/bsim/bluetooth/host/adv/encrypted/ead_sample/test_scripts/ead_sample.sh +++ b/tests/bsim/bluetooth/host/adv/encrypted/ead_sample/test_scripts/ead_sample.sh @@ -6,7 +6,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="ead_sample" verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv.sh b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv.sh index 65885a5822e..84fc0cd65cc 100755 --- a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv.sh +++ b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv.sh @@ -11,7 +11,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="ext_adv" verbosity_level=2 -EXECUTE_TIMEOUT=10 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn.sh b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn.sh index b3d26cbd91b..6bee0bfc3ba 100755 --- a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn.sh +++ b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn.sh @@ -13,7 +13,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="ext_adv_conn" verbosity_level=2 -EXECUTE_TIMEOUT=10 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn_x5.sh b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn_x5.sh index 8d54475552f..9abfca4d5a1 100755 --- a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn_x5.sh +++ b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn_x5.sh @@ -13,7 +13,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="ext_adv_conn_x5" verbosity_level=2 -EXECUTE_TIMEOUT=10 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv.sh b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv.sh index aa2e8249fae..cce67bd932b 100755 --- a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv.sh +++ b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv.sh @@ -9,7 +9,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="per_adv" verbosity_level=2 -EXECUTE_TIMEOUT=10 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn.sh b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn.sh index de535d78727..ea817d4f631 100755 --- a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn.sh +++ b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn.sh @@ -9,7 +9,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="per_adv_conn" verbosity_level=2 -EXECUTE_TIMEOUT=10 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn_privacy.sh b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn_privacy.sh index d7d2ad91414..5be5a68fce7 100755 --- a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn_privacy.sh +++ b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn_privacy.sh @@ -9,7 +9,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="per_adv_conn_privacy" verbosity_level=2 -EXECUTE_TIMEOUT=10 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_long_data.sh b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_long_data.sh index 7cac7527c99..802a64919e7 100755 --- a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_long_data.sh +++ b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_long_data.sh @@ -9,7 +9,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="per_adv_long_data" verbosity_level=2 -EXECUTE_TIMEOUT=10 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/resume/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/adv/resume/test_scripts/_compile.sh index 649d9f2b1bb..7fad3e25a89 100755 --- a/tests/bsim/bluetooth/host/adv/resume/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/adv/resume/test_scripts/_compile.sh @@ -1,16 +1,17 @@ #!/usr/bin/env bash -# Copyright 2022 Nordic Semiconductor ASA +# Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -# Place yourself in the test's root (i.e. ./../) -west build -b nrf52_bsim -d build_test && \ - cp build_test/zephyr/zephyr.exe "${test_exe}" +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 -west build -b nrf52_bsim -d build_test_2 -- -DCONF_FILE=prj_2.conf && \ - cp build_test_2/zephyr/zephyr.exe "${test_2_exe}" +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)" compile +app="$(guess_test_relpath)" conf_file=prj_2.conf compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/adv/resume/test_scripts/_env.sh b/tests/bsim/bluetooth/host/adv/resume/test_scripts/_env.sh deleted file mode 100755 index ccd11480a19..00000000000 --- a/tests/bsim/bluetooth/host/adv/resume/test_scripts/_env.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -test_name="$(basename "$(realpath "$bash_source_dir/..")")" -bsim_bin="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" -test_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_adv_resume_prj_conf" -test_2_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_adv_resume_prj_2_conf" diff --git a/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume.sh b/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume.sh index ee9d971fb23..3a1fa18594d 100755 --- a/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume.sh +++ b/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume.sh @@ -3,14 +3,11 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -simulation_id="${test_name}" +simulation_id="$(guess_test_long_name)" verbosity_level=2 -EXECUTE_TIMEOUT=30 +test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume_2.sh b/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume_2.sh index 911737232ec..3ee0700268c 100755 --- a/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume_2.sh +++ b/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume_2.sh @@ -3,14 +3,12 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -simulation_id="${test_name}_2" +simulation_id="$(guess_test_long_name)_2" verbosity_level=2 -EXECUTE_TIMEOUT=30 +test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +test_2_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_2_conf" cd ${BSIM_OUT_PATH}/bin From 39c9a995cbea84d9ab160bef8656bf764055f79c Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 14:39:53 +0100 Subject: [PATCH 1291/2402] tests/bsim bt host/att: Test scripts cleanup Use the common scripts so we have a consitent way of running the tests, report failures in the same way, can stop them with ctrl+C, properly wait for all processes to exit.. Let's also place the test scripts in the test_scripts/ folder as it is convention. Signed-off-by: Alberto Escolar Piedras (f) ests/bsim bt att: Use common s --- .../bluetooth/host/att/long_read/_build.sh | 14 -------- .../bsim/bluetooth/host/att/long_read/run.sh | 26 -------------- .../host/att/long_read/test_scripts/_build.sh | 16 +++++++++ .../host/att/long_read/test_scripts/run.sh | 22 ++++++++++++ .../att/mtu_update/test_scripts/_compile.sh | 13 +++---- .../host/att/mtu_update/test_scripts/_env.sh | 15 -------- .../att/mtu_update/test_scripts/run_test.sh | 8 ++--- .../bluetooth/host/att/open_close/_build.sh | 16 --------- .../bsim/bluetooth/host/att/open_close/run.sh | 36 ------------------- .../att/open_close/test_scripts/_build.sh | 16 +++++++++ .../host/att/open_close/test_scripts/run.sh | 24 +++++++++++++ .../host/att/pipeline/scripts/_compile.sh | 20 ----------- .../att/pipeline/test_scripts/_compile.sh | 15 ++++++++ .../pipeline/{scripts => test_scripts}/run.sh | 9 ++--- .../read_fill_buf/test_scripts/_compile.sh | 20 +++++------ .../att/read_fill_buf/test_scripts/_env.sh | 16 --------- .../read_fill_buf/test_scripts/run_tests.sh | 33 ++++------------- .../retry_on_sec_err/test_scripts/_compile.sh | 22 ++++++------ .../att/retry_on_sec_err/test_scripts/_env.sh | 15 -------- .../retry_on_sec_err/test_scripts/run_test.sh | 8 +++-- .../test_scripts/run_test_security_request.sh | 9 ++--- .../host/att/sequential/scripts/_compile.sh | 18 ---------- .../att/sequential/test_scripts/_compile.sh | 15 ++++++++ .../{scripts => test_scripts}/sequential.sh | 14 +++----- 24 files changed, 158 insertions(+), 262 deletions(-) delete mode 100755 tests/bsim/bluetooth/host/att/long_read/_build.sh delete mode 100755 tests/bsim/bluetooth/host/att/long_read/run.sh create mode 100755 tests/bsim/bluetooth/host/att/long_read/test_scripts/_build.sh create mode 100755 tests/bsim/bluetooth/host/att/long_read/test_scripts/run.sh delete mode 100755 tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_env.sh delete mode 100755 tests/bsim/bluetooth/host/att/open_close/_build.sh delete mode 100755 tests/bsim/bluetooth/host/att/open_close/run.sh create mode 100755 tests/bsim/bluetooth/host/att/open_close/test_scripts/_build.sh create mode 100755 tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh delete mode 100755 tests/bsim/bluetooth/host/att/pipeline/scripts/_compile.sh create mode 100755 tests/bsim/bluetooth/host/att/pipeline/test_scripts/_compile.sh rename tests/bsim/bluetooth/host/att/pipeline/{scripts => test_scripts}/run.sh (92%) delete mode 100755 tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_env.sh delete mode 100755 tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_env.sh delete mode 100755 tests/bsim/bluetooth/host/att/sequential/scripts/_compile.sh create mode 100755 tests/bsim/bluetooth/host/att/sequential/test_scripts/_compile.sh rename tests/bsim/bluetooth/host/att/sequential/{scripts => test_scripts}/sequential.sh (64%) diff --git a/tests/bsim/bluetooth/host/att/long_read/_build.sh b/tests/bsim/bluetooth/host/att/long_read/_build.sh deleted file mode 100755 index 637512b3826..00000000000 --- a/tests/bsim/bluetooth/host/att/long_read/_build.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/usr/bin/env bash - -set -eu -dotslash="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -bin_dir="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" - -cd "${dotslash}" - -compile_path="${bin_dir}/bs_${BOARD}_" -compile_path+="$(realpath --relative-to "$(west topdir)"/zephyr prj.conf | tr /. _)" - -west build -b nrf52_bsim -cp -v build/zephyr/zephyr.exe "${compile_path}" diff --git a/tests/bsim/bluetooth/host/att/long_read/run.sh b/tests/bsim/bluetooth/host/att/long_read/run.sh deleted file mode 100755 index b1b7a5c6eb0..00000000000 --- a/tests/bsim/bluetooth/host/att/long_read/run.sh +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env bash - -set -eu -dotslash="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -bin_dir="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" - -cd "${dotslash}" - -compile_path="${bin_dir}/bs_${BOARD}_" -compile_path+="$(realpath --relative-to "$(west topdir)"/zephyr prj.conf | tr /. _)" - -args_all=(-s=long_read -D=2) -args_dev=(-v=2 -RealEncryption=1 -testid=the_test) -sim_seconds=60 - -echo "Simulation time: $sim_seconds seconds" - -# bs_2G4_phy_v1 requires pwd to at its location -cd "${BSIM_OUT_PATH}/bin" - -("${compile_path}" "${args_all[@]}" "${args_dev[@]}" -d=0 || echo d0 $?) & -("${compile_path}" "${args_all[@]}" "${args_dev[@]}" -d=1 || echo d1 $?) & -(./bs_2G4_phy_v1 "${args_all[@]}" -v=6 -sim_length=$((sim_seconds * 10 ** 6)) || echo phy $?) & - -wait diff --git a/tests/bsim/bluetooth/host/att/long_read/test_scripts/_build.sh b/tests/bsim/bluetooth/host/att/long_read/test_scripts/_build.sh new file mode 100755 index 00000000000..af200055c53 --- /dev/null +++ b/tests/bsim/bluetooth/host/att/long_read/test_scripts/_build.sh @@ -0,0 +1,16 @@ +#!/usr/bin/env bash +# Copyright 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +set -eu + +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 + +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)" compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/att/long_read/test_scripts/run.sh b/tests/bsim/bluetooth/host/att/long_read/test_scripts/run.sh new file mode 100755 index 00000000000..b6b9ca57fec --- /dev/null +++ b/tests/bsim/bluetooth/host/att/long_read/test_scripts/run.sh @@ -0,0 +1,22 @@ +#!/usr/bin/env bash +# Copyright 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +set -eu + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +simulation_id="long_read" +dev_exe=bs_${BOARD}_$(guess_test_long_name)_prj_conf +args_all=(-s=${simulation_id} -D=2) +args_dev=(-v=2 -RealEncryption=1 -testid=the_test) + +cd "${BSIM_OUT_PATH}/bin" + +Execute ./${dev_exe} "${args_all[@]}" "${args_dev[@]}" -d=0 + +Execute ./${dev_exe} "${args_all[@]}" "${args_dev[@]}" -d=1 + +Execute ./bs_2G4_phy_v1 "${args_all[@]}" -v=6 -sim_length=60e6 + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_compile.sh index 2eedd8970c6..ca1f96b562c 100755 --- a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_compile.sh @@ -3,17 +3,12 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" -BOARD="${BOARD:-nrf52_bsim}" -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" INCR_BUILD=1 -mkdir -p ${WORK_DIR} source ${ZEPHYR_BASE}/tests/bsim/compile.source -app="tests/bsim/bluetooth/$test_name" compile + +app="$(guess_test_relpath)" compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_env.sh b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_env.sh deleted file mode 100755 index 8d101eabcdd..00000000000 --- a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_env.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -test_name="$(basename "$(realpath "$bash_source_dir/..")")" -bsim_bin="${BSIM_OUT_PATH}/bin" -verbosity_level=2 -BOARD="${BOARD:-nrf52_bsim}" -simulation_id="$test_name" -central_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_att_mtu_update_prj_conf" -peripheral_exe="${central_exe}" diff --git a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh index 255f6f4f9fa..c49ac8369b2 100755 --- a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh @@ -3,14 +3,12 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -simulation_id="$test_name" +simulation_id="$(guess_test_long_name)" verbosity_level=2 -EXECUTE_TIMEOUT=30 +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/att/open_close/_build.sh b/tests/bsim/bluetooth/host/att/open_close/_build.sh deleted file mode 100755 index 649682554f5..00000000000 --- a/tests/bsim/bluetooth/host/att/open_close/_build.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env bash -# Copyright (c) 2023 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -set -eu -dotslash="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -bin_dir="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" - -cd "${dotslash}" - -compile_path="${bin_dir}/bs_${BOARD}_" -compile_path+="$(realpath --relative-to "$(west topdir)"/zephyr prj.conf | tr /. _)" - -west build -b nrf52_bsim -cp -v build/zephyr/zephyr.exe "${compile_path}" diff --git a/tests/bsim/bluetooth/host/att/open_close/run.sh b/tests/bsim/bluetooth/host/att/open_close/run.sh deleted file mode 100755 index 3d8372e08ae..00000000000 --- a/tests/bsim/bluetooth/host/att/open_close/run.sh +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env bash -# Copyright (c) 2023 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -set -eu - -dotslash="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -bin_dir="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" - -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source - -cd "${dotslash}" - -compile_name="bs_${BOARD}_" -compile_name+="$(realpath --relative-to "$(west topdir)"/zephyr prj.conf | tr /. _)" - -compile_path="${bin_dir}/${compile_name}" -simulation_id="${compile_name}_$(basename "${BASH_SOURCE[0]}" | tr /. _)" - -args_all=(-s="${simulation_id}" -D=2) -args_dev=(-v=2 -RealEncryption=1 -testid=the_test) -sim_seconds=200 - -echo "Simulation time: $sim_seconds seconds" - -EXECUTE_TIMEOUT=60 - -# bs_2G4_phy_v1 requires pwd to at its location -cd "${BSIM_OUT_PATH}/bin" - -Execute "${compile_path}" "${args_all[@]}" "${args_dev[@]}" -d=1 -Execute ./bs_2G4_phy_v1 "${args_all[@]}" -v=6 -sim_length=$((sim_seconds * 10 ** 6)) -Execute "${compile_path}" "${args_all[@]}" "${args_dev[@]}" -d=0 - -wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/att/open_close/test_scripts/_build.sh b/tests/bsim/bluetooth/host/att/open_close/test_scripts/_build.sh new file mode 100755 index 00000000000..af200055c53 --- /dev/null +++ b/tests/bsim/bluetooth/host/att/open_close/test_scripts/_build.sh @@ -0,0 +1,16 @@ +#!/usr/bin/env bash +# Copyright 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +set -eu + +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 + +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)" compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh b/tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh new file mode 100755 index 00000000000..e66c4f13d9c --- /dev/null +++ b/tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh @@ -0,0 +1,24 @@ +#!/usr/bin/env bash +# Copyright (c) 2023 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +set -eu + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +test_path=$(guess_test_long_name) +dev_exe="bs_${BOARD}_${test_path}_prj_conf" +simulation_id="${test_path}" + +EXECUTE_TIMEOUT=60 + +cd "${BSIM_OUT_PATH}/bin" + +args_all=(-s="${simulation_id}" -D=2) +args_dev=(-v=2 -RealEncryption=1 -testid=the_test) + +Execute ./"${dev_exe}" "${args_all[@]}" "${args_dev[@]}" -d=1 +Execute ./bs_2G4_phy_v1 "${args_all[@]}" -v=6 -sim_length=200e6 +Execute ./"${dev_exe}" "${args_all[@]}" "${args_dev[@]}" -d=0 + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/att/pipeline/scripts/_compile.sh b/tests/bsim/bluetooth/host/att/pipeline/scripts/_compile.sh deleted file mode 100755 index 836f306cf1c..00000000000 --- a/tests/bsim/bluetooth/host/att/pipeline/scripts/_compile.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Path checks, etc -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source - -BOARD="${BOARD:-nrf52_bsim}" -dut_exe="bs_${BOARD}_tests_bsim_bluetooth_host_att_pipeline_dut_prj_conf" -tester_exe="bs_${BOARD}_tests_bsim_bluetooth_host_att_pipeline_tester_prj_conf" - -# terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh - -west build -b ${BOARD} -d build_a dut && \ - cp build_a/zephyr/zephyr.exe "${BSIM_OUT_PATH}/bin/${dut_exe}" && - -# b stands for bad -west build -b ${BOARD} -d build_b tester && \ - cp build_b/zephyr/zephyr.exe "${BSIM_OUT_PATH}/bin/${tester_exe}" diff --git a/tests/bsim/bluetooth/host/att/pipeline/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/pipeline/test_scripts/_compile.sh new file mode 100755 index 00000000000..3579ab2e772 --- /dev/null +++ b/tests/bsim/bluetooth/host/att/pipeline/test_scripts/_compile.sh @@ -0,0 +1,15 @@ +#!/usr/bin/env bash +# Copyright 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +set -eu + +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)"/dut compile +app="$(guess_test_relpath)"/tester compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/att/pipeline/scripts/run.sh b/tests/bsim/bluetooth/host/att/pipeline/test_scripts/run.sh similarity index 92% rename from tests/bsim/bluetooth/host/att/pipeline/scripts/run.sh rename to tests/bsim/bluetooth/host/att/pipeline/test_scripts/run.sh index 1edaf2e05a0..416484c27d2 100755 --- a/tests/bsim/bluetooth/host/att/pipeline/scripts/run.sh +++ b/tests/bsim/bluetooth/host/att/pipeline/test_scripts/run.sh @@ -2,16 +2,13 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -BOARD="${BOARD:-nrf52_bsim}" +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + dut_exe="bs_${BOARD}_tests_bsim_bluetooth_host_att_pipeline_dut_prj_conf" tester_exe="bs_${BOARD}_tests_bsim_bluetooth_host_att_pipeline_tester_prj_conf" -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source - -test_name="att_pipeline" -simulation_id="${test_name}" +simulation_id="att_pipeline" verbosity_level=2 -EXECUTE_TIMEOUT=30 sim_length_us=100e6 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_compile.sh index ee045695cda..1fa38a6d27f 100755 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_compile.sh @@ -1,18 +1,16 @@ -#!/bin/env bash +#!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -source "${bash_source_dir}/_env.sh" +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 -pushd client -west build -b nrf52_bsim && \ - cp -v build/zephyr/zephyr.exe "${test_exe_d0}" -popd +source ${ZEPHYR_BASE}/tests/bsim/compile.source -pushd server -west build -b nrf52_bsim && \ - cp -v build/zephyr/zephyr.exe "${test_exe_d1}" -popd +app="$(guess_test_relpath)"/client compile +app="$(guess_test_relpath)"/server compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_env.sh b/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_env.sh deleted file mode 100755 index c911274987f..00000000000 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_env.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -test_name="$(basename "$(realpath "$bash_source_dir/..")")" -bsim_bin="${BSIM_OUT_PATH}/bin" -verbosity_level=2 -BOARD="${BOARD:-nrf52_bsim}" -simulation_id="$test_name" -test_exe_d0="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_att_${test_name}_client_prj_conf" -test_exe_d1="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_att_${test_name}_server_prj_conf" diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/run_tests.sh b/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/run_tests.sh index 8c5adcad765..8f540dfaba1 100755 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/run_tests.sh +++ b/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/run_tests.sh @@ -3,26 +3,13 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -process_ids="" -exit_code=0 - -function Execute() { - if [ ! -f $1 ]; then - echo -e " \e[91m$(pwd)/$(basename $1) cannot be found (did you forget to\ - compile it?)\e[39m" - exit 1 - fi - echo -E "$@" - timeout 30 $@ & - process_ids="$process_ids $!" -} - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" +verbosity_level=2 +simulation_id="read_fill_buf" +test_exe_d0="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_client_prj_conf" +test_exe_d1="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_server_prj_conf" cd ${BSIM_OUT_PATH}/bin @@ -37,12 +24,4 @@ Execute "$test_exe_d1" \ Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s="${simulation_id}" \ -D=2 -sim_length=60e6 $@ -for process_id in $process_ids; do - wait $process_id || let "exit_code=$?" -done - -if [ ${exit_code} -ne 0 ]; then - exit_code=1 -fi - -exit $exit_code # the last exit code != 0 +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_compile.sh index 88a5454b674..1fa38a6d27f 100755 --- a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_compile.sh @@ -1,18 +1,16 @@ -#!/bin/env bash -# Copyright 2023 Codecoup +#!/usr/bin/env bash +# Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -source "${bash_source_dir}/_env.sh" +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 -pushd client -west build -b nrf52_bsim && \ - cp -v build/zephyr/zephyr.exe "${test_exe_d0}" -popd +source ${ZEPHYR_BASE}/tests/bsim/compile.source -pushd server -west build -b nrf52_bsim && \ - cp -v build/zephyr/zephyr.exe "${test_exe_d1}" -popd +app="$(guess_test_relpath)"/client compile +app="$(guess_test_relpath)"/server compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_env.sh b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_env.sh deleted file mode 100755 index 66b074ca3d8..00000000000 --- a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_env.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/env bash -# Copyright 2023 Codecoup -# SPDX-License-Identifier: Apache-2.0 - -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -test_name="$(basename "$(realpath "$bash_source_dir/..")")" -bsim_bin="${BSIM_OUT_PATH}/bin" -verbosity_level=2 -BOARD="${BOARD:-nrf52_bsim}" -test_exe_d0="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_att_${test_name}_client_prj_conf" -test_exe_d1="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_att_${test_name}_server_prj_conf" diff --git a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test.sh index 8ea8f38cddc..b822a7c1a96 100755 --- a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test.sh @@ -3,12 +3,14 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -simulation_id=$(basename "$0") -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source +simulation_id="retry_on_sec_err" +verbosity_level=2 +test_exe_d0="./bs_${BOARD}_$(guess_test_long_name)_client_prj_conf" +test_exe_d1="./bs_${BOARD}_$(guess_test_long_name)_server_prj_conf" + cd ${BSIM_OUT_PATH}/bin printf "\n\n===== ATT retry on security error (auto security elevation) ======\n\n" diff --git a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test_security_request.sh b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test_security_request.sh index 8d7c86c4d04..311def7e06f 100755 --- a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test_security_request.sh +++ b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test_security_request.sh @@ -3,12 +3,13 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -simulation_id=$(basename "$0") -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source +simulation_id="retry_on_sec_err_seq_request" +verbosity_level=2 +test_exe_d0="./bs_${BOARD}_$(guess_test_long_name)_client_prj_conf" +test_exe_d1="./bs_${BOARD}_$(guess_test_long_name)_server_prj_conf" + cd ${BSIM_OUT_PATH}/bin printf "\n\n==== ATT retry on security error (peripheral security request) ====\n\n" diff --git a/tests/bsim/bluetooth/host/att/sequential/scripts/_compile.sh b/tests/bsim/bluetooth/host/att/sequential/scripts/_compile.sh deleted file mode 100755 index 2e81445690f..00000000000 --- a/tests/bsim/bluetooth/host/att/sequential/scripts/_compile.sh +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Path checks, etc -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source - -BOARD="${BOARD:-nrf52_bsim}" -dut_exe="bs_${BOARD}_tests_bsim_bluetooth_host_att_sequential_dut_prj_conf" -tester_exe="bs_${BOARD}_tests_bsim_bluetooth_host_att_sequential_tester_prj_conf" - -# terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh - -west build -b ${BOARD} -d build_dut dut && \ - cp build_dut/zephyr/zephyr.exe "${BSIM_OUT_PATH}/bin/${dut_exe}" && -west build -b ${BOARD} -d build_tester tester && \ - cp build_tester/zephyr/zephyr.exe "${BSIM_OUT_PATH}/bin/${tester_exe}" diff --git a/tests/bsim/bluetooth/host/att/sequential/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/sequential/test_scripts/_compile.sh new file mode 100755 index 00000000000..3579ab2e772 --- /dev/null +++ b/tests/bsim/bluetooth/host/att/sequential/test_scripts/_compile.sh @@ -0,0 +1,15 @@ +#!/usr/bin/env bash +# Copyright 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +set -eu + +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)"/dut compile +app="$(guess_test_relpath)"/tester compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/att/sequential/scripts/sequential.sh b/tests/bsim/bluetooth/host/att/sequential/test_scripts/sequential.sh similarity index 64% rename from tests/bsim/bluetooth/host/att/sequential/scripts/sequential.sh rename to tests/bsim/bluetooth/host/att/sequential/test_scripts/sequential.sh index 61153432781..c7db4e95820 100755 --- a/tests/bsim/bluetooth/host/att/sequential/scripts/sequential.sh +++ b/tests/bsim/bluetooth/host/att/sequential/test_scripts/sequential.sh @@ -2,22 +2,18 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -BOARD="${BOARD:-nrf52_bsim}" -dut_exe="bs_${BOARD}_tests_bsim_bluetooth_host_att_sequential_dut_prj_conf" -tester_exe="bs_${BOARD}_tests_bsim_bluetooth_host_att_sequential_tester_prj_conf" - source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -test_name="att_sequential" -simulation_id="${test_name}" +simulation_id="att_sequential" verbosity_level=2 -EXECUTE_TIMEOUT=30 -sim_length_us=10e6 + +dut_exe="bs_${BOARD}_$(guess_test_long_name)_dut_prj_conf" +tester_exe="bs_${BOARD}_$(guess_test_long_name)_tester_prj_conf" cd ${BSIM_OUT_PATH}/bin Execute ./bs_2G4_phy_v1 \ - -v=${verbosity_level} -s="${simulation_id}" -D=2 -sim_length=${sim_length_us} $@ + -v=${verbosity_level} -s="${simulation_id}" -D=2 -sim_length=10e6 $@ Execute "./$tester_exe" \ -v=${verbosity_level} -s="${simulation_id}" -d=1 -testid=tester -RealEncryption=0 -rs=100 From 48e813ed6ef25bd55d6a4aafe99822b67b265bf4 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 16:11:43 +0100 Subject: [PATCH 1292/2402] tests/bsim bt gatt/ccc_store: Minor cleanup Ensure we call the common source script before using the BOARD variable, and let's not set things which are already set to the same by default Signed-off-by: Alberto Escolar Piedras --- .../gatt/ccc_store/test_scripts/_compile.sh | 17 +++++++++-------- .../host/gatt/ccc_store/test_scripts/_env.sh | 16 ---------------- .../gatt/ccc_store/test_scripts/ccc_store.sh | 6 ++---- .../gatt/ccc_store/test_scripts/ccc_store_2.sh | 6 ++---- 4 files changed, 13 insertions(+), 32 deletions(-) delete mode 100755 tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_env.sh diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_compile.sh index bf28e0cb936..ac5eb694236 100755 --- a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_compile.sh @@ -1,14 +1,15 @@ -#!/bin/env bash +#!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -source "${bash_source_dir}/_env.sh" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source -west build -b nrf52_bsim -d build_test && \ - cp -v build_test/zephyr/zephyr.exe "${test_exe}" +app="$(guess_test_relpath)" compile +app="$(guess_test_relpath)" conf_file=prj_2.conf compile -west build -b nrf52_bsim -d build_test_2 -- -DCONF_FILE=prj_2.conf && \ - cp -v build_test_2/zephyr/zephyr.exe "${test_exe_2}" +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_env.sh b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_env.sh deleted file mode 100755 index b72b396d89c..00000000000 --- a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_env.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -test_name="$(basename "$(realpath "$bash_source_dir/..")")" -bsim_bin="${BSIM_OUT_PATH}/bin" -verbosity_level=2 -BOARD="${BOARD:-nrf52_bsim}" -simulation_id="$test_name" -test_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_gatt_ccc_store_prj_conf" -test_exe_2="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_gatt_ccc_store_prj_2_conf" diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store.sh b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store.sh index 76480a4ae32..ef47bab1a91 100755 --- a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store.sh +++ b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store.sh @@ -4,11 +4,9 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -test_name='ccc_store' -test_exe="bs_${BOARD}_tests_bsim_bluetooth_host_gatt_${test_name}_prj_conf" -simulation_id="${test_name}" +test_exe="bs_${BOARD}_$(guess_test_long_name)_prj_conf" +simulation_id="ccc_store" verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_2.sh b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_2.sh index d6bb2a18d73..ec74cb27dd8 100755 --- a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_2.sh +++ b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_2.sh @@ -4,11 +4,9 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -test_name='ccc_store' -test_exe="bs_${BOARD}_tests_bsim_bluetooth_host_gatt_${test_name}_prj_2_conf" -simulation_id="${test_name}_2" +test_exe="bs_${BOARD}_$(guess_test_long_name)_prj_2_conf" +simulation_id="ccc_store_2" verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin From f1aaff5115b9a350b3ff33f4fe543675ce3f8a85 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 16:38:00 +0100 Subject: [PATCH 1293/2402] tests/bsim bt gatt/settings: Use common scripts Use the common scripts and do a minor cleanup Signed-off-by: Alberto Escolar Piedras --- .../host/gatt/settings/test_scripts/_compile.sh | 15 +++++++-------- .../host/gatt/settings/test_scripts/_env.sh | 11 ----------- .../settings/test_scripts/run_gatt_settings.sh | 8 +++----- .../settings/test_scripts/run_gatt_settings_2.sh | 6 ++---- 4 files changed, 12 insertions(+), 28 deletions(-) delete mode 100755 tests/bsim/bluetooth/host/gatt/settings/test_scripts/_env.sh diff --git a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_compile.sh index cd43f722c83..ac5eb694236 100755 --- a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_compile.sh @@ -3,14 +3,13 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source -# Place yourself in the test's root (i.e. ./../) -west build -b nrf52_bsim -d build_test && \ - cp build_test/zephyr/zephyr.exe "${test_exe}" +app="$(guess_test_relpath)" compile +app="$(guess_test_relpath)" conf_file=prj_2.conf compile -west build -b nrf52_bsim -d build_test_2 -- -DCONF_FILE=prj_2.conf && \ - cp build_test_2/zephyr/zephyr.exe "${test_2_exe}" +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_env.sh b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_env.sh deleted file mode 100755 index 22e1f9e6518..00000000000 --- a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_env.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -test_name="$(basename "$(realpath "$bash_source_dir/..")")" -bsim_bin="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" -test_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_gatt_settings_prj_conf" -test_2_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_gatt_settings_prj_2_conf" diff --git a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings.sh b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings.sh index 269ecbc9072..2a78f040771 100755 --- a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings.sh +++ b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings.sh @@ -3,14 +3,12 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -simulation_id="${test_name}" +simulation_id="settings" verbosity_level=2 -EXECUTE_TIMEOUT=30 +EXECUTE_TIMEOUT=120 +test_exe="./bs_${BOARD}_$(guess_test_long_name)_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings_2.sh b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings_2.sh index 873a0e670b0..6042d9eeb1e 100755 --- a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings_2.sh +++ b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings_2.sh @@ -3,14 +3,12 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -simulation_id="${test_name}_2" +simulation_id="settings_2" verbosity_level=2 EXECUTE_TIMEOUT=120 +test_2_exe="./bs_${BOARD}_$(guess_test_long_name)_prj_2_conf" cd ${BSIM_OUT_PATH}/bin From 769910b3e99c7f82158a37a6e4723b083f30c3d6 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 16:43:10 +0100 Subject: [PATCH 1294/2402] tests/bsim bt host/l2cap: Tests scripts cleanup Use the common scripts to perform common functions and do a cleanup. Do not set variables to their defaults, set things closer to were they are needed; Do not perform unnecesary checks; And in general avoid unnecessary complexity. Signed-off-by: Alberto Escolar Piedras --- .../l2cap/credits/tests_scripts/_compile.sh | 21 +++++++--------- .../credits/tests_scripts/l2cap_credits.sh | 16 ++----------- .../tests_scripts/l2cap_credits_ecred.sh | 18 ++++++++++++++ .../tests_scripts/_compile.sh | 24 +++++++------------ .../tests_scripts/l2cap_credits_seg_recv.sh | 16 ++----------- .../l2cap_credits_seg_recv_ecred.sh | 18 ++++++++++++++ .../l2cap/frags/tests_scripts/_compile.sh | 18 +++++++------- .../host/l2cap/frags/tests_scripts/run.sh | 6 ++--- .../send_on_connect/tests_scripts/l2cap.sh | 2 -- .../host/l2cap/split/scripts/_compile.sh | 18 -------------- .../host/l2cap/split/test_scripts/_compile.sh | 15 ++++++++++++ .../{scripts => test_scripts}/l2cap_split.sh | 11 ++++----- .../l2cap/stress/tests_scripts/_compile.sh | 18 +++++++------- .../host/l2cap/stress/tests_scripts/l2cap.sh | 4 ++-- .../l2cap/stress/tests_scripts/l2cap_syswq.sh | 6 ++--- 15 files changed, 98 insertions(+), 113 deletions(-) create mode 100755 tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits_ecred.sh create mode 100755 tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv_ecred.sh delete mode 100755 tests/bsim/bluetooth/host/l2cap/split/scripts/_compile.sh create mode 100755 tests/bsim/bluetooth/host/l2cap/split/test_scripts/_compile.sh rename tests/bsim/bluetooth/host/l2cap/split/{scripts => test_scripts}/l2cap_split.sh (69%) diff --git a/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/_compile.sh index e18721da5f9..98c4d1bb18a 100755 --- a/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/_compile.sh @@ -1,20 +1,15 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +set -eu -# Path checks, etc -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -# Place yourself in the test's root (i.e. ./../) -rm -rf ${BSIM_OUT_PATH}/bin/bs_nrf52_bsim_tests* +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source -# terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh +app="$(guess_test_relpath)" compile +app="$(guess_test_relpath)" conf_file=prj_ecred.conf compile -bsim_exe=bs_nrf52_bsim_tests_bsim_bluetooth_host_l2cap_credits_prj_conf -west build -b nrf52_bsim && \ - cp build/zephyr/zephyr.exe ${BSIM_OUT_PATH}/bin/${bsim_exe} - -bsim_exe=bs_nrf52_bsim_tests_bsim_bluetooth_host_l2cap_credits_prj_ecred_conf -west build -b nrf52_bsim -d build_ecred -- -DCONF_FILE=prj_ecred.conf && \ - cp build_ecred/zephyr/zephyr.exe ${BSIM_OUT_PATH}/bin/${bsim_exe} +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits.sh b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits.sh index fb2588cfd87..1a4aae35915 100755 --- a/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits.sh +++ b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits.sh @@ -5,23 +5,11 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 -EXECUTE_TIMEOUT=20 +simulation_id=$(guess_test_long_name) +bsim_exe=./bs_${BOARD}_$(guess_test_long_name)_prj_conf cd ${BSIM_OUT_PATH}/bin -simulation_id=bluetooth_host_l2cap_credits_prj_conf -bsim_exe=./bs_nrf52_bsim_tests_bsim_bluetooth_host_l2cap_credits_prj_conf - -Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=420 -Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=100 - -Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=30e6 $@ - -wait_for_background_jobs - -simulation_id=bluetooth_host_l2cap_credits_prj_ecred_conf -bsim_exe=./bs_nrf52_bsim_tests_bsim_bluetooth_host_l2cap_credits_prj_ecred_conf - Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=420 Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=100 diff --git a/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits_ecred.sh b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits_ecred.sh new file mode 100755 index 00000000000..eb68324bd31 --- /dev/null +++ b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits_ecred.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash +# Copyright (c) 2023 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +verbosity_level=2 +simulation_id=$(guess_test_long_name)_ecred +bsim_exe=./bs_${BOARD}_$(guess_test_long_name)_prj_ecred_conf + +cd ${BSIM_OUT_PATH}/bin + +Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=420 +Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=100 + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=30e6 $@ + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/_compile.sh index 311e818a60a..98c4d1bb18a 100755 --- a/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/_compile.sh @@ -1,23 +1,15 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +set -eu -# Usage: Place yourself in the test's root (i.e. ./../) +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -export BOARD=nrf52_bsim +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source -# Path checks, etc -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source +app="$(guess_test_relpath)" compile +app="$(guess_test_relpath)" conf_file=prj_ecred.conf compile -rm -rf ${BSIM_OUT_PATH}/bin/bs_nrf52_bsim_tests* - -# terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh - -bsim_exe=bs_nrf52_bsim_tests_bsim_bluetooth_host_l2cap_credits_seg_recv_prj_conf -west build -b nrf52_bsim && \ - cp build/zephyr/zephyr.exe ${BSIM_OUT_PATH}/bin/${bsim_exe} - -bsim_exe=bs_nrf52_bsim_tests_bsim_bluetooth_host_l2cap_credits_seg_recv_prj_ecred_conf -west build -b nrf52_bsim -d build_ecred -- -DCONF_FILE=prj_ecred.conf && \ - cp build_ecred/zephyr/zephyr.exe ${BSIM_OUT_PATH}/bin/${bsim_exe} +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv.sh b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv.sh index 4dfa15cbdb2..1a4aae35915 100755 --- a/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv.sh +++ b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv.sh @@ -5,23 +5,11 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 -EXECUTE_TIMEOUT=20 +simulation_id=$(guess_test_long_name) +bsim_exe=./bs_${BOARD}_$(guess_test_long_name)_prj_conf cd ${BSIM_OUT_PATH}/bin -simulation_id=bluetooth_host_l2cap_credits_seg_recv_prj_conf -bsim_exe=./bs_nrf52_bsim_tests_bsim_bluetooth_host_l2cap_credits_seg_recv_prj_conf - -Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=420 -Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=100 - -Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=30e6 $@ - -wait_for_background_jobs - -simulation_id=bluetooth_host_l2cap_credits_seg_recv_prj_ecred_conf -bsim_exe=./bs_nrf52_bsim_tests_bsim_bluetooth_host_l2cap_credits_seg_recv_prj_ecred_conf - Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=420 Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=100 diff --git a/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv_ecred.sh b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv_ecred.sh new file mode 100755 index 00000000000..eb68324bd31 --- /dev/null +++ b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv_ecred.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash +# Copyright (c) 2023 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +verbosity_level=2 +simulation_id=$(guess_test_long_name)_ecred +bsim_exe=./bs_${BOARD}_$(guess_test_long_name)_prj_ecred_conf + +cd ${BSIM_OUT_PATH}/bin + +Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=420 +Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=100 + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=30e6 $@ + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/_compile.sh index e4d6157f76f..17b454f9d7c 100755 --- a/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/_compile.sh @@ -1,16 +1,14 @@ #!/usr/bin/env bash -# Copyright 2024 Nordic Semiconductor ASA +# Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +set -eu -# Path checks, etc -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -# Place yourself in the test's root (i.e. ./../) -rm -rf ${BSIM_OUT_PATH}/bin/bs_nrf52_bsim_tests* +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source -# terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh +app="$(guess_test_relpath)" compile -bsim_exe=bs_nrf52_bsim_tests_bsim_bluetooth_host_l2cap_frags_prj_conf -west build -b nrf52_bsim && \ - cp build/zephyr/zephyr.exe ${BSIM_OUT_PATH}/bin/${bsim_exe} +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/run.sh b/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/run.sh index 2c71c95001e..e14372a1052 100755 --- a/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/run.sh +++ b/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/run.sh @@ -5,13 +5,11 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 -EXECUTE_TIMEOUT=20 +simulation_id=$(guess_test_long_name) +bsim_exe=./bs_${BOARD}_$(guess_test_long_name)_prj_conf cd ${BSIM_OUT_PATH}/bin -simulation_id=bluetooth_host_l2cap_frags_prj_conf -bsim_exe=./bs_nrf52_bsim_tests_bsim_bluetooth_host_l2cap_frags_prj_conf - Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=420 Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=100 diff --git a/tests/bsim/bluetooth/host/l2cap/send_on_connect/tests_scripts/l2cap.sh b/tests/bsim/bluetooth/host/l2cap/send_on_connect/tests_scripts/l2cap.sh index 7fa0459c327..d6e3f60d391 100755 --- a/tests/bsim/bluetooth/host/l2cap/send_on_connect/tests_scripts/l2cap.sh +++ b/tests/bsim/bluetooth/host/l2cap/send_on_connect/tests_scripts/l2cap.sh @@ -22,8 +22,6 @@ Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ wait_for_background_jobs simulation_id="l2cap_send_on_connect_ecred" -verbosity_level=2 -EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/l2cap/split/scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/split/scripts/_compile.sh deleted file mode 100755 index 79521b64900..00000000000 --- a/tests/bsim/bluetooth/host/l2cap/split/scripts/_compile.sh +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Path checks, etc -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source - -BOARD="${BOARD:-nrf52_bsim}" -dut_exe="bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_split_dut_prj_conf" -tester_exe="bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_split_tester_prj_conf" - -# terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh - -west build -b ${BOARD} -d build_dut dut && \ - cp build_dut/zephyr/zephyr.exe "${BSIM_OUT_PATH}/bin/${dut_exe}" && -west build -b ${BOARD} -d build_tester tester && \ - cp build_tester/zephyr/zephyr.exe "${BSIM_OUT_PATH}/bin/${tester_exe}" diff --git a/tests/bsim/bluetooth/host/l2cap/split/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/split/test_scripts/_compile.sh new file mode 100755 index 00000000000..3579ab2e772 --- /dev/null +++ b/tests/bsim/bluetooth/host/l2cap/split/test_scripts/_compile.sh @@ -0,0 +1,15 @@ +#!/usr/bin/env bash +# Copyright 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +set -eu + +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)"/dut compile +app="$(guess_test_relpath)"/tester compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/l2cap/split/scripts/l2cap_split.sh b/tests/bsim/bluetooth/host/l2cap/split/test_scripts/l2cap_split.sh similarity index 69% rename from tests/bsim/bluetooth/host/l2cap/split/scripts/l2cap_split.sh rename to tests/bsim/bluetooth/host/l2cap/split/test_scripts/l2cap_split.sh index f0b4684f5a2..8c26c0e4bd8 100755 --- a/tests/bsim/bluetooth/host/l2cap/split/scripts/l2cap_split.sh +++ b/tests/bsim/bluetooth/host/l2cap/split/test_scripts/l2cap_split.sh @@ -2,16 +2,13 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -BOARD="${BOARD:-nrf52_bsim}" -dut_exe="bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_split_dut_prj_conf" -tester_exe="bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_split_tester_prj_conf" - source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -test_name="l2cap_split" -simulation_id="${test_name}" +dut_exe="bs_${BOARD}_$(guess_test_long_name)_dut_prj_conf" +tester_exe="bs_${BOARD}_$(guess_test_long_name)_tester_prj_conf" + +simulation_id="l2cap_split" verbosity_level=2 -EXECUTE_TIMEOUT=30 sim_length_us=30e6 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/_compile.sh index 6e0810d7697..56cf572829e 100755 --- a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/_compile.sh @@ -1,17 +1,15 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +set -eu -# Path checks, etc -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -# Place yourself in the test's root (i.e. ./../) -rm -rf ${BSIM_OUT_PATH}/bin/bs_nrf52_bsim_tests* +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source -# terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh +app="$(guess_test_relpath)" compile +app="$(guess_test_relpath)" conf_file=prj_syswq.conf compile -bsim_exe=bs_nrf52_bsim_tests_bsim_bluetooth_host_l2cap_stress_prj_conf - -west build -b nrf52_bsim && \ - cp build/zephyr/zephyr.exe ${BSIM_OUT_PATH}/bin/${bsim_exe} +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh index f365f96a7e8..9d2a760a6d0 100755 --- a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh +++ b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh @@ -9,10 +9,10 @@ simulation_id="l2cap_stress" verbosity_level=2 EXECUTE_TIMEOUT=240 -cd ${BSIM_OUT_PATH}/bin - bsim_exe=./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_stress_prj_conf +cd ${BSIM_OUT_PATH}/bin + Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=43 Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=42 diff --git a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh index 40492162279..c71363d834b 100755 --- a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh +++ b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh @@ -7,12 +7,12 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # EATT test simulation_id="l2cap_stress_syswq" verbosity_level=2 -EXECUTE_TIMEOUT=120 - -cd ${BSIM_OUT_PATH}/bin +EXECUTE_TIMEOUT=240 bsim_exe=./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_stress_prj_syswq_conf +cd ${BSIM_OUT_PATH}/bin + Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=43 Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=42 From e9c6f37daf61a50808e3a6c145bed8ca24bbe07e Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 17:12:02 +0100 Subject: [PATCH 1295/2402] tests/bsim bt host/misc: Tests scripts cleanup Ensure we call the common source script before using the BOARD variable; Use the common scripts to perform common functions and do a cleanup. Do not set variables to their defaults, set things closer to were they are needed; Do not perform unnecesary checks; And in general avoid unnecessary complexity. And return !=0 on error. Signed-off-by: Alberto Escolar Piedras --- .../host/misc/disconnect/scripts/_compile.sh | 18 ------------------ .../misc/disconnect/test_scripts/_compile.sh | 14 ++++++++++++++ .../{scripts => test_scripts}/disconnect.sh | 13 ++++++------- .../host/misc/hfc/scripts/_compile.sh | 17 ----------------- .../host/misc/hfc/test_scripts/_compile.sh | 14 ++++++++++++++ .../misc/hfc/{scripts => test_scripts}/run.sh | 0 .../tests_scripts/_compile.sh | 19 ++++++++----------- .../tests_scripts/unregister_conn_cb.sh | 5 ++--- 8 files changed, 44 insertions(+), 56 deletions(-) delete mode 100755 tests/bsim/bluetooth/host/misc/disconnect/scripts/_compile.sh create mode 100755 tests/bsim/bluetooth/host/misc/disconnect/test_scripts/_compile.sh rename tests/bsim/bluetooth/host/misc/disconnect/{scripts => test_scripts}/disconnect.sh (83%) delete mode 100755 tests/bsim/bluetooth/host/misc/hfc/scripts/_compile.sh create mode 100755 tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh rename tests/bsim/bluetooth/host/misc/hfc/{scripts => test_scripts}/run.sh (100%) diff --git a/tests/bsim/bluetooth/host/misc/disconnect/scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/disconnect/scripts/_compile.sh deleted file mode 100755 index 555faa068f2..00000000000 --- a/tests/bsim/bluetooth/host/misc/disconnect/scripts/_compile.sh +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Path checks, etc -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source - -BOARD="${BOARD:-nrf52_bsim}" -dut_exe="bs_${BOARD}_tests_bsim_bluetooth_host_misc_disconnect_dut_prj_conf" -tester_exe="bs_${BOARD}_tests_bsim_bluetooth_host_misc_disconnect_tester_prj_conf" - -# terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh - -west build -b ${BOARD} -d build_dut dut && \ - cp build_dut/zephyr/zephyr.exe "${BSIM_OUT_PATH}/bin/${dut_exe}" && -west build -b ${BOARD} -d build_tester tester && \ - cp build_tester/zephyr/zephyr.exe "${BSIM_OUT_PATH}/bin/${tester_exe}" diff --git a/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/_compile.sh new file mode 100755 index 00000000000..fbdcdbacac2 --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/_compile.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +# Copyright 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +set -eu + +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source +app="$(guess_test_relpath)"/dut compile +app="$(guess_test_relpath)"/tester compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/misc/disconnect/scripts/disconnect.sh b/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/disconnect.sh similarity index 83% rename from tests/bsim/bluetooth/host/misc/disconnect/scripts/disconnect.sh rename to tests/bsim/bluetooth/host/misc/disconnect/test_scripts/disconnect.sh index 4380119a3e7..438dfdf5f27 100755 --- a/tests/bsim/bluetooth/host/misc/disconnect/scripts/disconnect.sh +++ b/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/disconnect.sh @@ -2,16 +2,13 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -BOARD="${BOARD:-nrf52_bsim}" -dut_exe="bs_${BOARD}_tests_bsim_bluetooth_host_misc_disconnect_dut_prj_conf" -tester_exe="bs_${BOARD}_tests_bsim_bluetooth_host_misc_disconnect_tester_prj_conf" - source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -test_name="misc_disconnect" -simulation_id="${test_name}" +dut_exe="bs_${BOARD}_$(guess_test_long_name)_dut_prj_conf" +tester_exe="bs_${BOARD}_$(guess_test_long_name)_tester_prj_conf" + +simulation_id="misc_disconnect" verbosity_level=2 -EXECUTE_TIMEOUT=30 sim_length_us=10e6 cd ${BSIM_OUT_PATH}/bin @@ -46,3 +43,5 @@ for j in {0..1}; do echo "${BSIM_OUT_PATH}/results/${simulation_id}/Trace_$i.Tx.pcap" echo "${BSIM_OUT_PATH}/results/${simulation_id}/Trace_$i.Rx.pcap" done + +exit $exit_code diff --git a/tests/bsim/bluetooth/host/misc/hfc/scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/hfc/scripts/_compile.sh deleted file mode 100755 index 499362605fc..00000000000 --- a/tests/bsim/bluetooth/host/misc/hfc/scripts/_compile.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Path checks, etc -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source - -# Place yourself in the test's root (i.e. ./../) -rm -rf ${BSIM_OUT_PATH}/bin/bs_nrf52_bsim_tests* - -# terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh - -bsim_exe=bs_nrf52_bsim_tests_bsim_bluetooth_host_misc_hfc_prj_conf - -west build -b nrf52_bsim && \ - cp build/zephyr/zephyr.exe ${BSIM_OUT_PATH}/bin/${bsim_exe} diff --git a/tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh new file mode 100755 index 00000000000..17b454f9d7c --- /dev/null +++ b/tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +# Copyright 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +set -eu + +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)" compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/misc/hfc/scripts/run.sh b/tests/bsim/bluetooth/host/misc/hfc/test_scripts/run.sh similarity index 100% rename from tests/bsim/bluetooth/host/misc/hfc/scripts/run.sh rename to tests/bsim/bluetooth/host/misc/hfc/test_scripts/run.sh diff --git a/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/_compile.sh index b6b361b86d4..17b454f9d7c 100755 --- a/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/_compile.sh @@ -1,17 +1,14 @@ #!/usr/bin/env bash -#Copyright (c) 2024 NXP -#Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +set -eu -# Path checks, etc -source ${ZEPHYR_BASE}/tests/bsim/sh_common.source +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -# Place yourself in the test's root (i.e. ./../) -rm -rf ${BSIM_OUT_PATH}/bin/bs_nrf52_bsim_tests* +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source -# terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh +app="$(guess_test_relpath)" compile -bsim_exe=bs_nrf52_bsim_tests_bsim_bluetooth_host_misc_unregister_conn_cb_prj_conf -west build -b nrf52_bsim && \ - cp build/zephyr/zephyr.exe ${BSIM_OUT_PATH}/bin/${bsim_exe} +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/unregister_conn_cb.sh b/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/unregister_conn_cb.sh index 8fc8bcafaf7..8bfb9aebf87 100755 --- a/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/unregister_conn_cb.sh +++ b/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/unregister_conn_cb.sh @@ -12,11 +12,10 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source #neither flag change can be found, callback function was unregistered as expected simulation_id="unregister_conn_cb" verbosity_level=2 -EXECUTE_TIMEOUT=20 -cd ${BSIM_OUT_PATH}/bin +bsim_exe=./bs_${BOARD}_tests_bsim_bluetooth_host_misc_unregister_conn_cb_prj_conf -bsim_exe=./bs_nrf52_bsim_tests_bsim_bluetooth_host_misc_unregister_conn_cb_prj_conf +cd ${BSIM_OUT_PATH}/bin Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=420 Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=100 From 06326dc8c2c6667448eda30d2adf62adc6d718ba Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 17:14:40 +0100 Subject: [PATCH 1296/2402] tests/bsim bt host/privacy/*: Tests scripts cleanup Ensure we call the common source script before using the BOARD variable; Use the common scripts to perform common functions and do a cleanup. Do not set variables to their defaults, set things closer to were they are needed; Do not perform unnecesary checks; And in general avoid unnecessary complexity. And for the 2 parts of the peripheral rpa sharing test, use different sim_ids, so the traces for each part can be checked. Signed-off-by: Alberto Escolar Piedras --- .../privacy/central/test_scripts/_compile.sh | 12 ++--------- .../host/privacy/central/test_scripts/_env.sh | 11 ---------- .../privacy/central/test_scripts/run_test.sh | 9 ++++---- .../privacy/device/test_scripts/_compile.sh | 12 ++++++----- .../host/privacy/device/test_scripts/_env.sh | 12 ----------- .../privacy/device/test_scripts/run_tests.sh | 6 ++---- .../privacy/legacy/test_scripts/_compile.sh | 12 +++++------ .../host/privacy/legacy/test_scripts/_env.sh | 11 ---------- .../privacy/legacy/test_scripts/run_test.sh | 7 +++---- .../peripheral/test_scripts/_compile.sh | 16 +++++++++----- .../privacy/peripheral/test_scripts/_env.sh | 14 ------------- .../peripheral/test_scripts/run_test.sh | 11 +++------- .../test_scripts/run_test_rpa_expired.sh | 10 +++------ .../test_scripts/run_test_rpa_sharing.sh | 21 +++++++------------ 14 files changed, 48 insertions(+), 116 deletions(-) delete mode 100755 tests/bsim/bluetooth/host/privacy/central/test_scripts/_env.sh delete mode 100755 tests/bsim/bluetooth/host/privacy/device/test_scripts/_env.sh delete mode 100755 tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_env.sh delete mode 100755 tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_env.sh diff --git a/tests/bsim/bluetooth/host/privacy/central/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/central/test_scripts/_compile.sh index f1803766794..2152b9cc57c 100755 --- a/tests/bsim/bluetooth/host/privacy/central/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/privacy/central/test_scripts/_compile.sh @@ -3,19 +3,11 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -source "${bash_source_dir}/_env.sh" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" -BOARD="${BOARD:-nrf52_bsim}" -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" INCR_BUILD=1 -mkdir -p ${WORK_DIR} +source ${ZEPHYR_BASE}/tests/bsim/compile.source -west build -b nrf52_bsim -cp build/zephyr/zephyr.exe $central_exe +app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/privacy/central/test_scripts/_env.sh b/tests/bsim/bluetooth/host/privacy/central/test_scripts/_env.sh deleted file mode 100755 index 0db56a594dc..00000000000 --- a/tests/bsim/bluetooth/host/privacy/central/test_scripts/_env.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -bsim_bin="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" -central_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_privacy_central_prj_conf" -peripheral_exe="${central_exe}" diff --git a/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh index ce65d58f6ce..d61b0e0d0bb 100755 --- a/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh @@ -3,14 +3,13 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 -simulation_id="$(basename "$(realpath "$bash_source_dir/..")")" -EXECUTE_TIMEOUT=30 +simulation_id="$(guess_test_long_name)" + +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/privacy/device/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/device/test_scripts/_compile.sh index 42376ab5231..2152b9cc57c 100755 --- a/tests/bsim/bluetooth/host/privacy/device/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/privacy/device/test_scripts/_compile.sh @@ -1,11 +1,13 @@ -#!/bin/env bash +#!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -source "${bash_source_dir}/_env.sh" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -west build -b nrf52_bsim && \ - cp -v build/zephyr/zephyr.exe "${test_exe}" +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/privacy/device/test_scripts/_env.sh b/tests/bsim/bluetooth/host/privacy/device/test_scripts/_env.sh deleted file mode 100755 index ee8b534d1db..00000000000 --- a/tests/bsim/bluetooth/host/privacy/device/test_scripts/_env.sh +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -bsim_bin="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" -test_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_privacy_device_prj_conf" diff --git a/tests/bsim/bluetooth/host/privacy/device/test_scripts/run_tests.sh b/tests/bsim/bluetooth/host/privacy/device/test_scripts/run_tests.sh index d02b58df58d..131f857396c 100755 --- a/tests/bsim/bluetooth/host/privacy/device/test_scripts/run_tests.sh +++ b/tests/bsim/bluetooth/host/privacy/device/test_scripts/run_tests.sh @@ -3,14 +3,12 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 -simulation_id="$(basename "$(realpath "$bash_source_dir/..")")" -EXECUTE_TIMEOUT=30 +simulation_id="$(guess_test_long_name)" +test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_compile.sh index b754a9cc481..2152b9cc57c 100755 --- a/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_compile.sh @@ -3,13 +3,11 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -# terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source -west build -b nrf52_bsim && \ - cp build/zephyr/zephyr.exe $central_exe +app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_env.sh b/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_env.sh deleted file mode 100755 index 714fe3eb996..00000000000 --- a/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_env.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -bsim_bin="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" -central_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_privacy_legacy_prj_conf" -peripheral_exe="${central_exe}" diff --git a/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/run_test.sh index ccbe6e844f2..95acccc613d 100755 --- a/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/run_test.sh @@ -3,14 +3,13 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 -simulation_id="$(basename "$(realpath "$bash_source_dir/..")")" -EXECUTE_TIMEOUT=30 +simulation_id="$(guess_test_long_name)" +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_compile.sh index 28420639ac4..0f0ca567252 100755 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_compile.sh @@ -3,10 +3,16 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -west build -b nrf52_bsim && \ - cp build/zephyr/zephyr.exe $central_exe +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 + +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)" compile +app="$(guess_test_relpath)" conf_file=prj_rpa_expired.conf compile +app="$(guess_test_relpath)" conf_file=prj_rpa_sharing.conf compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_env.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_env.sh deleted file mode 100755 index 3c86078a7a6..00000000000 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_env.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -bsim_bin="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" -central_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_privacy_peripheral_prj_conf" -peripheral_exe="${central_exe}" -central_exe_rpa_sharing="\ -${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_privacy_peripheral_prj_rpa_sharing_conf" -peripheral_exe_rpa_sharing="${central_exe_rpa_sharing}" diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh index 169d9b8510b..eda6a285b8a 100755 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh @@ -3,14 +3,13 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id="host_privacy_peripheral" -EXECUTE_TIMEOUT=30 + +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin @@ -18,12 +17,10 @@ Execute "$central_exe" \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -RealEncryption=1 \ -flash="${simulation_id}.central.log.bin" -flash_erase - Execute "$peripheral_exe" \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -RealEncryption=1 \ -flash="${simulation_id}.peripheral.log.bin" -flash_erase - Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ -D=2 -sim_length=70e6 $@ @@ -33,12 +30,10 @@ Execute "$central_exe" \ -v=${verbosity_level} -s=${simulation_id}.2 -d=0 -testid=central -RealEncryption=1 \ -flash="${simulation_id}.central.log.bin" -flash_rm - Execute "$peripheral_exe" \ -v=${verbosity_level} -s=${simulation_id}.2 -d=1 -testid=peripheral -RealEncryption=1 \ -flash="${simulation_id}.peripheral.log.bin" -flash_rm - Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id}.2 \ -D=2 -sim_length=70e6 $@ diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh index 73d1e199de9..8d8fa763571 100755 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh @@ -3,21 +3,17 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id="rpa_expired" -EXECUTE_TIMEOUT=30 - -cd ${BSIM_OUT_PATH}/bin central_exe_rpa_expired="\ -${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_privacy_peripheral_prj_rpa_expired_conf" +${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_rpa_expired_conf" peripheral_exe_rpa_expired="${central_exe_rpa_expired}" +cd ${BSIM_OUT_PATH}/bin + Execute "$central_exe_rpa_expired" \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central_rpa_check \ -RealEncryption=1 -flash="${simulation_id}.central.log.bin" -flash_erase diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh index 2b0d5e4c4b7..d927177e4fa 100755 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh @@ -3,15 +3,14 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 -simulation_id="$(basename "$(realpath "$bash_source_dir/..")")" -simulation_id="${simulation_id}_rpa_sharing" -EXECUTE_TIMEOUT=30 +simulation_id="$(guess_test_long_name)_rpa_sharing" + +central_exe_rpa_sharing="\ +${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_rpa_sharing_conf" +peripheral_exe_rpa_sharing="${central_exe_rpa_sharing}" cd ${BSIM_OUT_PATH}/bin @@ -19,28 +18,24 @@ Execute "$central_exe_rpa_sharing" \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -RealEncryption=1 \ -flash="${simulation_id}.central.log.bin" - Execute "$peripheral_exe_rpa_sharing" \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -RealEncryption=1 \ -flash="${simulation_id}.peripheral.log.bin" - Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ -D=2 -sim_length=70e6 $@ wait_for_background_jobs Execute "$central_exe_rpa_sharing" \ - -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -RealEncryption=1 \ + -v=${verbosity_level} -s=${simulation_id}_2 -d=0 -testid=central -RealEncryption=1 \ -flash="${simulation_id}.central.log.bin" -flash_rm - Execute "$peripheral_exe_rpa_sharing" \ - -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -RealEncryption=1 \ + -v=${verbosity_level} -s=${simulation_id}_2 -d=1 -testid=peripheral -RealEncryption=1 \ -flash="${simulation_id}.peripheral.log.bin" -flash_rm - -Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id}_2 \ -D=2 -sim_length=70e6 $@ wait_for_background_jobs From 8002730b655c16ab99c9cd91fcbeee1de6a86f80 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 21 Mar 2024 11:20:54 +0100 Subject: [PATCH 1297/2402] tests/bsim bt host/security/*: Test scripts cleanup Use the common scripts to perform common functions and do a cleanup. Do not set variables to their defaults, set things closer to were they are needed; Do not perform unnecesary checks; And in general avoid unnecessary complexity. Some of the _compile scripts were rotten => Fix them. Signed-off-by: Alberto Escolar Piedras --- .../test_scripts/_compile.sh | 11 ++----- .../test_scripts/_env.sh | 15 --------- .../test_scripts/run_test.sh | 9 +++--- .../test_scripts/_compile.sh | 12 ++----- .../test_scripts/_env.sh | 30 ------------------ .../test_scripts/run_test.sh | 8 ++--- .../test_scripts/_compile.sh | 12 ++----- .../bond_per_connection/test_scripts/_env.sh | 30 ------------------ .../test_scripts/run_test.sh | 11 ++++--- .../ccc_update/test_scripts/_compile.sh | 14 +++++---- .../security/ccc_update/test_scripts/_env.sh | 16 ---------- .../ccc_update/test_scripts/ccc_update.sh | 3 +- .../ccc_update/test_scripts/ccc_update_2.sh | 3 +- .../id_addr_update/test_scripts/_compile.sh | 14 ++------- .../id_addr_update/test_scripts/_env.sh | 31 ------------------- .../id_addr_update/test_scripts/run_test.sh | 11 ++++--- .../test_scripts/_compile.sh | 18 ++++------- .../test_scripts/security_changed_callback.sh | 3 +- 18 files changed, 47 insertions(+), 204 deletions(-) delete mode 100755 tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_env.sh delete mode 100755 tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_env.sh delete mode 100755 tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_env.sh delete mode 100755 tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_env.sh delete mode 100755 tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_env.sh diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_compile.sh index 878c256b891..ca70f8349ff 100755 --- a/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_compile.sh @@ -3,18 +3,11 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" - -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" -BOARD="${BOARD:-nrf52_bsim}" -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" INCR_BUILD=1 -mkdir -p ${WORK_DIR} + source ${ZEPHYR_BASE}/tests/bsim/compile.source -app="tests/bsim/bluetooth/$test_name" compile +app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_env.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_env.sh deleted file mode 100755 index 102e63a5ef1..00000000000 --- a/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_env.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -test_name="security_bond_overwrite_allowed" -bsim_bin="${BSIM_OUT_PATH}/bin" -verbosity_level=2 -BOARD="${BOARD:-nrf52_bsim}" -simulation_id="$test_name" -central_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_${test_name}_prj_conf" -peripheral_exe="${central_exe}" diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/run_test.sh index 3aecac00ee0..c77a4bfd7d8 100755 --- a/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/run_test.sh @@ -3,12 +3,13 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -EXECUTE_TIMEOUT=30 +simulation_id="security_bond_overwrite_allowed" +verbosity_level=2 + +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_compile.sh index 878c256b891..5fb4d1a3db3 100755 --- a/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_compile.sh @@ -3,18 +3,10 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" - -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" -BOARD="${BOARD:-nrf52_bsim}" -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" INCR_BUILD=1 -mkdir -p ${WORK_DIR} + source ${ZEPHYR_BASE}/tests/bsim/compile.source -app="tests/bsim/bluetooth/$test_name" compile +app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_env.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_env.sh deleted file mode 100755 index 982ba75d4f5..00000000000 --- a/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_env.sh +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -test_name="security_bond_overwrite_denied" -bsim_bin="${BSIM_OUT_PATH}/bin" -verbosity_level=2 -BOARD="${BOARD:-nrf52_bsim}" -simulation_id="$test_name" -central_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_${test_name}_prj_conf" -peripheral_exe="${central_exe}" - -function print_var { - # Print a shell-sourceable variable definition. - local var_name="$1" - local var_repr="${!var_name@Q}" - echo "$var_name=$var_repr" -} - -print_var test_name -print_var bsim_bin -print_var verbosity_level -print_var BOARD -print_var simulation_id -print_var central_exe -print_var peripheral_exe diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/run_test.sh index 6f00e23c70c..20f67117927 100755 --- a/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/run_test.sh @@ -3,13 +3,13 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -EXECUTE_TIMEOUT=30 +simulation_id="security_bond_overwrite_denied" +verbosity_level=2 +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_compile.sh index f03de68b83f..4cdee31addb 100755 --- a/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_compile.sh @@ -3,18 +3,10 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" - -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" -BOARD="${BOARD:-nrf52_bsim}" -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" INCR_BUILD=1 -mkdir -p ${WORK_DIR} + source ${ZEPHYR_BASE}/tests/bsim/compile.source -app="tests/bsim/bluetooth/$test_name" compile +app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_env.sh b/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_env.sh deleted file mode 100755 index 173f0d2eedf..00000000000 --- a/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_env.sh +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -test_name="security_bond_per_connection" -bsim_bin="${BSIM_OUT_PATH}/bin" -verbosity_level=2 -BOARD="${BOARD:-nrf52_bsim}" -simulation_id="$test_name" -central_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_${test_name}_prj_conf" -peripheral_exe="${central_exe}" - -function print_var { - # Print a shell-sourceable variable definition. - local var_name="$1" - local var_repr="${!var_name@Q}" - echo "$var_name=$var_repr" -} - -print_var test_name -print_var bsim_bin -print_var verbosity_level -print_var BOARD -print_var simulation_id -print_var central_exe -print_var peripheral_exe diff --git a/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/run_test.sh index 351f44523cc..c2a765b487c 100755 --- a/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/run_test.sh @@ -3,13 +3,14 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -EXECUTE_TIMEOUT=30 +verbosity_level=2 + +simulation_id="security_bond_per_connection" + +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_compile.sh index bf28e0cb936..593ef45dfc1 100755 --- a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_compile.sh @@ -3,12 +3,14 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -source "${bash_source_dir}/_env.sh" +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 -west build -b nrf52_bsim -d build_test && \ - cp -v build_test/zephyr/zephyr.exe "${test_exe}" +source ${ZEPHYR_BASE}/tests/bsim/compile.source -west build -b nrf52_bsim -d build_test_2 -- -DCONF_FILE=prj_2.conf && \ - cp -v build_test_2/zephyr/zephyr.exe "${test_exe_2}" +app="$(guess_test_relpath)" compile +app="$(guess_test_relpath)" conf_file=prj_2.conf compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_env.sh b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_env.sh deleted file mode 100755 index 701b4b5d2d6..00000000000 --- a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_env.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -test_name="$(basename "$(realpath "$bash_source_dir/..")")" -bsim_bin="${BSIM_OUT_PATH}/bin" -verbosity_level=2 -BOARD="${BOARD:-nrf52_bsim}" -simulation_id="$test_name" -test_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_security_ccc_update_prj_conf" -test_exe_2="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_security_ccc_update_prj_2_conf" diff --git a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update.sh b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update.sh index aaf3c7899f3..17432a38a7e 100755 --- a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update.sh +++ b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update.sh @@ -1,4 +1,4 @@ -#!/bin/env bash +#!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 @@ -8,7 +8,6 @@ test_name='ccc_update' test_exe="bs_${BOARD}_tests_bsim_bluetooth_host_security_${test_name}_prj_conf" simulation_id="${test_name}" verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_2.sh b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_2.sh index ab9097d9d5e..c267186e9b4 100755 --- a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_2.sh +++ b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_2.sh @@ -1,4 +1,4 @@ -#!/bin/env bash +#!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 @@ -8,7 +8,6 @@ test_name='ccc_update' test_exe="bs_${BOARD}_tests_bsim_bluetooth_host_security_${test_name}_prj_2_conf" simulation_id="${test_name}_2" verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_compile.sh index ca555ea526c..00c33e102ce 100755 --- a/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_compile.sh @@ -3,22 +3,14 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" - -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" -BOARD="${BOARD:-nrf52_bsim}" -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" INCR_BUILD=1 -mkdir -p ${WORK_DIR} + source ${ZEPHYR_BASE}/tests/bsim/compile.source -app="tests/bsim/bluetooth/host/security/$test_name/central" compile -app="tests/bsim/bluetooth/host/security/$test_name/peripheral" compile +app="$(guess_test_relpath)/central" compile +app="$(guess_test_relpath)/peripheral" compile wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_env.sh b/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_env.sh deleted file mode 100755 index 8ac4b9eaf69..00000000000 --- a/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_env.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -test_name="id_addr_update" -bsim_bin="${BSIM_OUT_PATH}/bin" -verbosity_level=2 -board="${BOARD:-nrf52_bsim}" -simulation_id="$test_name" -test_path="tests_bsim_bluetooth_host_security_${test_name}" -central_exe="${bsim_bin}/bs_${board}_${test_path}_central_prj_conf" -peripheral_exe="${bsim_bin}/bs_${board}_${test_path}_peripheral_prj_conf" - -function print_var { - # Print a shell-sourceable variable definition. - local var_name="$1" - local var_repr="${!var_name@Q}" - echo "$var_name=$var_repr" -} - -print_var test_name -print_var bsim_bin -print_var verbosity_level -print_var board -print_var simulation_id -print_var central_exe -print_var peripheral_exe diff --git a/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/run_test.sh index b44fa62d61c..2b79511a307 100755 --- a/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/run_test.sh @@ -3,13 +3,14 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -# Read variable definitions output by _env.sh -source "${bash_source_dir}/_env.sh" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -EXECUTE_TIMEOUT=10 +verbosity_level=2 +simulation_id="id_addr_update" + +test_path="$(guess_test_long_name)" +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_${test_path}_central_prj_conf" +peripheral_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_${test_path}_peripheral_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/_compile.sh index a7d3a9c569f..4cdee31addb 100755 --- a/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/_compile.sh @@ -1,18 +1,12 @@ -#!/bin/env bash +#!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -# Terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 -test_name='security_changed_callback' - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" -bsim_bin="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" -test_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_security_${test_name}_prj_conf" - -west build -b nrf52_bsim -d build && \ - cp -v build/zephyr/zephyr.exe "${test_exe}" +source ${ZEPHYR_BASE}/tests/bsim/compile.source +app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/security_changed_callback.sh b/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/security_changed_callback.sh index 122ba43e12f..492e8249dab 100755 --- a/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/security_changed_callback.sh +++ b/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/security_changed_callback.sh @@ -1,4 +1,4 @@ -#!/bin/env bash +#!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 @@ -8,7 +8,6 @@ test_name='security_changed_callback' test_exe="bs_${BOARD}_tests_bsim_bluetooth_host_security_${test_name}_prj_conf" simulation_id="${test_name}" verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin From a7d381854e93c33f09c2cccc939fd125cce3e5a7 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 21 Mar 2024 14:07:44 +0100 Subject: [PATCH 1298/2402] tests/bsim bt host/iso/*: Test scripts cleanup Use the common scripts to perform common functions and do a cleanup. Signed-off-by: Alberto Escolar Piedras --- .../host/iso/cis/tests_scripts/_compile.sh | 16 +++++----------- .../bluetooth/host/iso/cis/tests_scripts/_env.sh | 14 -------------- 2 files changed, 5 insertions(+), 25 deletions(-) delete mode 100755 tests/bsim/bluetooth/host/iso/cis/tests_scripts/_env.sh diff --git a/tests/bsim/bluetooth/host/iso/cis/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/iso/cis/tests_scripts/_compile.sh index f1803766794..4fa833c38ac 100755 --- a/tests/bsim/bluetooth/host/iso/cis/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/iso/cis/tests_scripts/_compile.sh @@ -1,21 +1,15 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -source "${bash_source_dir}/_env.sh" -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" -BOARD="${BOARD:-nrf52_bsim}" -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" INCR_BUILD=1 -mkdir -p ${WORK_DIR} -west build -b nrf52_bsim -cp build/zephyr/zephyr.exe $central_exe +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)" compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/iso/cis/tests_scripts/_env.sh b/tests/bsim/bluetooth/host/iso/cis/tests_scripts/_env.sh deleted file mode 100755 index f595a2006e3..00000000000 --- a/tests/bsim/bluetooth/host/iso/cis/tests_scripts/_env.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/usr/bin/env bash -# Copyright 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" - -test_name="$(basename "$(realpath "$bash_source_dir/..")")" -bsim_bin="${BSIM_OUT_PATH}/bin" -verbosity_level=2 -BOARD="${BOARD:-nrf52_bsim}" -simulation_id="$test_name" -central_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_iso_cis_prj_conf" -peripheral_exe="${central_exe}" From a7ea72cee0b5562543b96d27463f734cc186dee7 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 21 Mar 2024 14:09:38 +0100 Subject: [PATCH 1299/2402] tests/bsim bt host/id/settings: Test scripts cleanup Use the common scripts to perform common functions and do a cleanup. Signed-off-by: Alberto Escolar Piedras --- .../host/id/settings/test_scripts/_compile.sh | 15 +++++++++------ .../host/id/settings/test_scripts/settings.sh | 1 - 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh index 9c23bf1a934..af200055c53 100755 --- a/tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh @@ -3,11 +3,14 @@ # SPDX-License-Identifier: Apache-2.0 set -eu -bash_source_dir="$(realpath "$(dirname "${BASH_SOURCE[0]}")")" -bsim_bin="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" -test_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_id_settings_prj_conf" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -west build -b nrf52_bsim -d build && \ - cp -v build/zephyr/zephyr.exe "${test_exe}" +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 + +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)" compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/id/settings/test_scripts/settings.sh b/tests/bsim/bluetooth/host/id/settings/test_scripts/settings.sh index 2221b5c1ea4..7e031a930c1 100755 --- a/tests/bsim/bluetooth/host/id/settings/test_scripts/settings.sh +++ b/tests/bsim/bluetooth/host/id/settings/test_scripts/settings.sh @@ -7,7 +7,6 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source test_exe="bs_${BOARD}_tests_bsim_bluetooth_host_id_settings_prj_conf" simulation_id="id_settings" verbosity_level=2 -EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin From ab3e4d4bbeb6cd3ee1c64839a8d6ee68ee0b26ff Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 21 Mar 2024 14:28:56 +0100 Subject: [PATCH 1300/2402] tests/bsim/bluetooth/audio: Use common scripts Use the common functions instead of replicating functionality and do a minor cleanup Signed-off-by: Alberto Escolar Piedras --- .../bap_bass_server_sync_client_rem.sh | 26 +++---------------- .../bap_bass_server_sync_server_rem.sh | 25 +++--------------- 2 files changed, 7 insertions(+), 44 deletions(-) diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_client_rem.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_client_rem.sh index a20060b2e6c..1cbdbd03f6e 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_client_rem.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_client_rem.sh @@ -1,26 +1,12 @@ #!/usr/bin/env bash -# # Copyright (c) 2020-2022 Nordic Semiconductor ASA # # SPDX-License-Identifier: Apache-2.0 +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + SIMULATION_ID="bass_server_sync_client_rem" VERBOSITY_LEVEL=2 -PROCESS_IDS=""; EXIT_CODE=0 - -function Execute(){ - if [ ! -f $1 ]; then - echo -e " \e[91m`pwd`/`basename $1` cannot be found (did you forget to\ - compile it?)\e[39m" - exit 1 - fi - timeout 20 $@ & PROCESS_IDS="$PROCESS_IDS $!" -} - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -#Give a default value to BOARD if it does not have one yet: -BOARD="${BOARD:-nrf52_bsim}" cd ${BSIM_OUT_PATH}/bin @@ -34,15 +20,11 @@ Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 \ -testid=bap_broadcast_assistant_server_sync_client_rem -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=bass_broadcaster -rs=69 -D=3 # Simulation time should be larger than the WAIT_TIME in common.h Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -D=3 \ -sim_length=60e6 $@ -for PROCESS_ID in $PROCESS_IDS; do - wait $PROCESS_ID || let "EXIT_CODE=$?" -done - -exit $EXIT_CODE #the last exit code != 0 +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_server_rem.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_server_rem.sh index 65dedab5363..c4bd2f68751 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_server_rem.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_server_rem.sh @@ -1,26 +1,11 @@ #!/usr/bin/env bash -# # Copyright (c) 2020-2022 Nordic Semiconductor ASA # # SPDX-License-Identifier: Apache-2.0 +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source SIMULATION_ID="bass_server_sync_server_rem" VERBOSITY_LEVEL=2 -PROCESS_IDS=""; EXIT_CODE=0 - -function Execute(){ - if [ ! -f $1 ]; then - echo -e " \e[91m`pwd`/`basename $1` cannot be found (did you forget to\ - compile it?)\e[39m" - exit 1 - fi - timeout 20 $@ & PROCESS_IDS="$PROCESS_IDS $!" -} - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -#Give a default value to BOARD if it does not have one yet: -BOARD="${BOARD:-nrf52_bsim}" cd ${BSIM_OUT_PATH}/bin @@ -34,15 +19,11 @@ Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 \ -testid=bap_broadcast_assistant_server_sync_server_rem -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=bass_broadcaster -rs=69 -D=3 # Simulation time should be larger than the WAIT_TIME in common.h Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -D=3 \ -sim_length=60e6 $@ -for PROCESS_ID in $PROCESS_IDS; do - wait $PROCESS_ID || let "EXIT_CODE=$?" -done - -exit $EXIT_CODE #the last exit code != 0 +wait_for_background_jobs From 42d97fdf991fdaf28aa020b43409c539521f09a4 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 21 Mar 2024 14:29:55 +0100 Subject: [PATCH 1301/2402] tests/bsim/bluetooth/ll/conn: Use common scripts Use the common functions instead of replicating functionality and do a minor cleanup Signed-off-by: Alberto Escolar Piedras --- .../conn/tests_scripts/basic_conn20_split.sh | 22 +++---------------- 1 file changed, 3 insertions(+), 19 deletions(-) diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn20_split.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn20_split.sh index e61759d7338..17bd4ed9205 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn20_split.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn20_split.sh @@ -1,26 +1,13 @@ #!/usr/bin/env bash # Copyright 2018 Oticon A/S # SPDX-License-Identifier: Apache-2.0 +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source # Basic connection test: a central connects to a peripheral # using the split controller (ULL LLL) - central disconnects and reconnects 20 times simulation_id="basic_conn20_split" verbosity_level=2 -process_ids=""; exit_code=0 - -function Execute(){ - if [ ! -f $1 ]; then - echo -e " \e[91m`pwd`/`basename $1` cannot be found (did you forget to\ - compile it?)\e[39m" - exit 1 - fi - timeout 55 $@ & process_ids="$process_ids $!" -} - -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" - -#Give a default value to BOARD if it does not have one yet: -BOARD="${BOARD:-nrf52_bsim}" +EXECUTE_TIMEOUT=60 cd ${BSIM_OUT_PATH}/bin @@ -35,7 +22,4 @@ Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_conf\ Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ -D=2 -sim_length=100e6 $@ -for process_id in $process_ids; do - wait $process_id || let "exit_code=$?" -done -exit $exit_code #the last exit code != 0 +wait_for_background_jobs From 1d231dda332f0c132e6eeaea96cb4f85267ebaf1 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 21 Mar 2024 14:30:54 +0100 Subject: [PATCH 1302/2402] tests/bsim/bluetooth/host/gatt: Use common scripts Use the common functions instead of replicating functionality Signed-off-by: Alberto Escolar Piedras --- .../gatt/sc_indicate/test_scripts/_compile.sh | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/_compile.sh index b07577a9878..b45cd9fb77d 100755 --- a/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/_compile.sh @@ -1,18 +1,15 @@ -#!/bin/env bash +#!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu -# Terminate running simulations (if any) -${BSIM_COMPONENTS_PATH}/common/stop_bsim.sh +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" +INCR_BUILD=1 +source ${ZEPHYR_BASE}/tests/bsim/compile.source -test_name='sc_indicate' +app="$(guess_test_relpath)" compile -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" -bsim_bin="${BSIM_OUT_PATH}/bin" -BOARD="${BOARD:-nrf52_bsim}" -test_exe="${bsim_bin}/bs_${BOARD}_tests_bsim_bluetooth_host_gatt_${test_name}_prj_conf" -west build -b nrf52_bsim -d build && \ - cp -v build/zephyr/zephyr.exe "${test_exe}" +wait_for_background_jobs From fd8857539d79aa25243e5fdd25ff327ffb8f1415 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 14:41:16 +0100 Subject: [PATCH 1303/2402] tests/bsim: All scripts: Use boardtarget string instead of BOARD In all scripts, where we were using the BOARD variable let's use BOARD_TS which is the full BOARD target string with "/" replaced with "_" This is neccessary to support hwmv2 board names Signed-off-by: Alberto Escolar Piedras --- .../audio/test_scripts/_csip_notify.sh | 4 ++-- .../test_scripts/bap_bass_client_sync.sh | 6 +++--- .../bap_bass_server_sync_client_rem.sh | 6 +++--- .../bap_bass_server_sync_server_rem.sh | 6 +++--- .../audio/test_scripts/bap_broadcast_audio.sh | 8 ++++---- .../bap_broadcast_audio_assistant.sh | 6 +++--- .../audio/test_scripts/bap_unicast_audio.sh | 4 ++-- .../bap_unicast_audio_acl_disconnect.sh | 4 ++-- .../audio/test_scripts/cap_broadcast.sh | 4 ++-- .../audio/test_scripts/cap_broadcast_ac_12.sh | 4 ++-- .../audio/test_scripts/cap_broadcast_ac_13.sh | 4 ++-- .../audio/test_scripts/cap_broadcast_ac_14.sh | 4 ++-- .../test_scripts/cap_capture_and_render.sh | 6 +++--- .../audio/test_scripts/cap_unicast.sh | 4 ++-- .../audio/test_scripts/cap_unicast_ac_1.sh | 4 ++-- .../audio/test_scripts/cap_unicast_ac_10.sh | 4 ++-- .../audio/test_scripts/cap_unicast_ac_11_i.sh | 4 ++-- .../test_scripts/cap_unicast_ac_11_ii.sh | 6 +++--- .../audio/test_scripts/cap_unicast_ac_2.sh | 4 ++-- .../audio/test_scripts/cap_unicast_ac_3.sh | 4 ++-- .../audio/test_scripts/cap_unicast_ac_4.sh | 4 ++-- .../audio/test_scripts/cap_unicast_ac_5.sh | 4 ++-- .../audio/test_scripts/cap_unicast_ac_6_i.sh | 4 ++-- .../audio/test_scripts/cap_unicast_ac_6_ii.sh | 6 +++--- .../audio/test_scripts/cap_unicast_ac_7_i.sh | 4 ++-- .../audio/test_scripts/cap_unicast_ac_7_ii.sh | 6 +++--- .../audio/test_scripts/cap_unicast_ac_8_i.sh | 4 ++-- .../audio/test_scripts/cap_unicast_ac_8_ii.sh | 6 +++--- .../audio/test_scripts/cap_unicast_ac_9_i.sh | 4 ++-- .../audio/test_scripts/cap_unicast_ac_9_ii.sh | 6 +++--- .../audio/test_scripts/cap_unicast_inval.sh | 4 ++-- .../audio/test_scripts/cap_unicast_timeout.sh | 4 ++-- .../bsim/bluetooth/audio/test_scripts/csip.sh | 8 ++++---- .../audio/test_scripts/csip_encrypted_sirk.sh | 8 ++++---- .../audio/test_scripts/csip_forced_release.sh | 8 ++++---- .../audio/test_scripts/csip_new_sirk.sh | 8 ++++---- .../audio/test_scripts/csip_no_lock.sh | 8 ++++---- .../audio/test_scripts/csip_no_rank.sh | 8 ++++---- .../audio/test_scripts/csip_no_size.sh | 8 ++++---- .../test_scripts/gmap_broadcast_ac_12.sh | 4 ++-- .../test_scripts/gmap_broadcast_ac_13.sh | 4 ++-- .../test_scripts/gmap_broadcast_ac_14.sh | 4 ++-- .../audio/test_scripts/gmap_unicast_ac_1.sh | 4 ++-- .../test_scripts/gmap_unicast_ac_11_i.sh | 4 ++-- .../test_scripts/gmap_unicast_ac_11_ii.sh | 6 +++--- .../audio/test_scripts/gmap_unicast_ac_2.sh | 4 ++-- .../audio/test_scripts/gmap_unicast_ac_3.sh | 4 ++-- .../audio/test_scripts/gmap_unicast_ac_4.sh | 4 ++-- .../audio/test_scripts/gmap_unicast_ac_5.sh | 4 ++-- .../audio/test_scripts/gmap_unicast_ac_6_i.sh | 4 ++-- .../test_scripts/gmap_unicast_ac_6_ii.sh | 6 +++--- .../test_scripts/gmap_unicast_ac_7_ii.sh | 6 +++--- .../audio/test_scripts/gmap_unicast_ac_8_i.sh | 4 ++-- .../test_scripts/gmap_unicast_ac_8_ii.sh | 6 +++--- .../bsim/bluetooth/audio/test_scripts/has.sh | 4 ++-- .../audio/test_scripts/has_offline.sh | 4 ++-- .../bsim/bluetooth/audio/test_scripts/ias.sh | 4 ++-- .../bluetooth/audio/test_scripts/mcs_mcc.sh | 4 ++-- .../audio/test_scripts/media_controller.sh | 6 +++--- .../bsim/bluetooth/audio/test_scripts/micp.sh | 6 +++--- .../audio/test_scripts/pacs_notify.sh | 4 ++-- .../bsim/bluetooth/audio/test_scripts/pbp.sh | 4 ++-- .../bsim/bluetooth/audio/test_scripts/tbs.sh | 6 +++--- .../bsim/bluetooth/audio/test_scripts/tmap.sh | 4 ++-- .../bsim/bluetooth/audio/test_scripts/vcp.sh | 6 +++--- .../tests_scripts/broadcast_audio.sh | 4 ++-- tests/bsim/bluetooth/audio_samples/compile.sh | 10 +++++----- .../tests_scripts/unicast_client.sh | 4 ++-- .../basic_conn_split_hci_uart.sh | 8 ++++---- .../basic_conn_split_hci_uart_async.sh | 8 ++++---- .../host/adv/chain/tests_scripts/adv_chain.sh | 4 ++-- .../css_sample_data/test_scripts/run_tests.sh | 2 +- .../ead_sample/test_scripts/ead_sample.sh | 4 ++-- .../adv/extended/tests_scripts/ext_adv.sh | 4 ++-- .../extended/tests_scripts/ext_adv_conn.sh | 4 ++-- .../extended/tests_scripts/ext_adv_conn_x5.sh | 4 ++-- .../adv/periodic/tests_scripts/per_adv.sh | 4 ++-- .../periodic/tests_scripts/per_adv_conn.sh | 4 ++-- .../tests_scripts/per_adv_conn_privacy.sh | 4 ++-- .../tests_scripts/per_adv_long_data.sh | 4 ++-- .../adv/resume/test_scripts/run_adv_resume.sh | 2 +- .../resume/test_scripts/run_adv_resume_2.sh | 4 ++-- .../att/eatt/tests_scripts/autoconnect.sh | 4 ++-- .../host/att/eatt/tests_scripts/collision.sh | 4 ++-- .../host/att/eatt/tests_scripts/lowres.sh | 4 ++-- .../att/eatt/tests_scripts/multiple_conn.sh | 4 ++-- .../att/eatt/tests_scripts/reconfigure.sh | 4 ++-- .../att/eatt_notif/test_scripts/eatt_notif.sh | 4 ++-- .../host/att/long_read/test_scripts/run.sh | 2 +- .../att/mtu_update/test_scripts/run_test.sh | 2 +- .../host/att/open_close/test_scripts/run.sh | 2 +- .../host/att/pipeline/test_scripts/run.sh | 4 ++-- .../read_fill_buf/test_scripts/run_tests.sh | 4 ++-- .../retry_on_sec_err/test_scripts/run_test.sh | 4 ++-- .../test_scripts/run_test_security_request.sh | 4 ++-- .../att/sequential/test_scripts/sequential.sh | 4 ++-- .../gatt/authorization/test_scripts/gatt.sh | 4 ++-- .../gatt/caching/test_scripts/_run_test.sh | 4 ++-- .../gatt/ccc_store/test_scripts/ccc_store.sh | 2 +- .../ccc_store/test_scripts/ccc_store_2.sh | 2 +- .../host/gatt/general/test_scripts/gatt.sh | 4 ++-- .../gatt/notify/test_scripts/_run_test.sh | 4 ++-- .../test_scripts/_notify-debug.sh | 4 ++-- .../notify_multiple/test_scripts/notify.sh | 4 ++-- .../sc_indicate/test_scripts/sc_indicate.sh | 2 +- .../test_scripts/run_gatt_settings.sh | 2 +- .../test_scripts/run_gatt_settings_2.sh | 2 +- .../host/id/settings/test_scripts/settings.sh | 2 +- .../host/iso/cis/tests_scripts/cis.sh | 4 ++-- .../credits/tests_scripts/l2cap_credits.sh | 2 +- .../tests_scripts/l2cap_credits_ecred.sh | 2 +- .../tests_scripts/l2cap_credits_seg_recv.sh | 2 +- .../l2cap_credits_seg_recv_ecred.sh | 2 +- .../host/l2cap/frags/tests_scripts/run.sh | 2 +- .../host/l2cap/general/tests_scripts/l2cap.sh | 4 ++-- .../send_on_connect/tests_scripts/l2cap.sh | 8 ++++---- .../l2cap/split/test_scripts/l2cap_split.sh | 4 ++-- .../host/l2cap/stress/tests_scripts/l2cap.sh | 2 +- .../l2cap/stress/tests_scripts/l2cap_syswq.sh | 2 +- .../l2cap/userdata/tests_scripts/l2cap.sh | 4 ++-- .../misc/disable/tests_scripts/disable.sh | 2 +- .../tests_scripts/disable_with_gatt.sh | 4 ++-- .../disconnect/test_scripts/disconnect.sh | 4 ++-- .../host/misc/hfc/test_scripts/run.sh | 2 +- .../tests_scripts/unregister_conn_cb.sh | 2 +- .../privacy/central/test_scripts/run_test.sh | 2 +- .../privacy/device/test_scripts/run_tests.sh | 2 +- .../privacy/legacy/test_scripts/run_test.sh | 2 +- .../peripheral/test_scripts/run_test.sh | 2 +- .../test_scripts/run_test_rpa_expired.sh | 2 +- .../test_scripts/run_test_rpa_sharing.sh | 2 +- .../test_scripts/run_test.sh | 2 +- .../test_scripts/run_test.sh | 2 +- .../test_scripts/run_test.sh | 2 +- .../ccc_update/test_scripts/ccc_update.sh | 2 +- .../ccc_update/test_scripts/ccc_update_2.sh | 2 +- .../id_addr_update/test_scripts/run_test.sh | 4 ++-- .../test_scripts/security_changed_callback.sh | 2 +- .../ll/advx/tests_scripts/basic_advx.sh | 4 ++-- .../basic_advx_ticker_expire_info.sh | 4 ++-- .../ll/bis/tests_scripts/broadcast_iso.sh | 4 ++-- .../broadcast_iso_ticker_expire_info.sh | 4 ++-- .../bis/tests_scripts/broadcast_iso_vs_dp.sh | 4 ++-- .../ll/cis/tests_scripts/connected_iso.sh | 20 +++++++++---------- .../tests_scripts/connected_iso_acl_first.sh | 20 +++++++++---------- ...onnected_iso_acl_first_ft_cen_skip_2_se.sh | 6 ++++-- ...onnected_iso_acl_first_ft_cen_skip_4_se.sh | 6 ++++-- ...onnected_iso_acl_first_ft_per_skip_2_se.sh | 6 ++++-- ...onnected_iso_acl_first_ft_per_skip_4_se.sh | 6 ++++-- .../tests_scripts/connected_iso_acl_group.sh | 10 +++++----- .../connected_iso_acl_group_acl_first.sh | 10 +++++----- .../tests_scripts/connected_iso_legacy_adv.sh | 20 +++++++++---------- .../connected_iso_legacy_adv_acl_first.sh | 20 +++++++++---------- .../connected_iso_peripheral_cis.sh | 4 ++-- .../conn/tests_scripts/basic_conn20_split.sh | 4 ++-- .../basic_conn_encrypted_split.sh | 4 ++-- .../basic_conn_encrypted_split_privacy.sh | 4 ++-- ...basic_conn_encrypted_split_single_timer.sh | 4 ++-- .../ll/conn/tests_scripts/basic_conn_split.sh | 4 ++-- .../tests_scripts/basic_conn_split_low_lat.sh | 4 ++-- .../tests_scripts/_controller_tests_inner.sh | 4 ++-- .../ll/edtt/tests_scripts/gatt.llcp.sh | 4 ++-- .../ll/multiple_id/tests_scripts/multiple.sh | 4 ++-- .../ll/throughput/tests_scripts/gatt_write.sh | 4 ++-- tests/bsim/bluetooth/mesh/_mesh_test.sh | 4 ++-- .../tests_scripts/echo_test_802154.sh | 4 ++-- .../echo_test/tests_scripts/echo_test_ot.sh | 4 ++-- 167 files changed, 390 insertions(+), 382 deletions(-) diff --git a/tests/bsim/bluetooth/audio/test_scripts/_csip_notify.sh b/tests/bsim/bluetooth/audio/test_scripts/_csip_notify.sh index e5ada46b6c2..617a6b56766 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/_csip_notify.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/_csip_notify.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running CSIP Notify test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=csip_notify_server -rs=24 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=csip_notify_client -rs=46 -D=2 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \ diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh index 1410af91138..fb2f5d329cb 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh @@ -14,15 +14,15 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running BASS Client Sync =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=bap_scan_delegator_client_sync \ -rs=24 -D=3 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 \ -testid=bap_broadcast_assistant_client_sync -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=bass_broadcaster -rs=69 -D=3 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_client_rem.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_client_rem.sh index 1cbdbd03f6e..6c90c3b63b5 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_client_rem.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_client_rem.sh @@ -12,15 +12,15 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running BASS Server Sync Client Remove =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 \ -testid=bap_scan_delegator_server_sync_client_rem -rs=24 -D=3 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 \ -testid=bap_broadcast_assistant_server_sync_client_rem -rs=46 -D=3 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=bass_broadcaster -rs=69 -D=3 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_server_rem.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_server_rem.sh index c4bd2f68751..a55c497e258 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_server_rem.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_server_sync_server_rem.sh @@ -11,15 +11,15 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running BASS Server Sync Server Remove =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 \ -testid=bap_scan_delegator_server_sync_server_rem -rs=24 -D=3 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 \ -testid=bap_broadcast_assistant_server_sync_server_rem -rs=46 -D=3 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=bass_broadcaster -rs=69 -D=3 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio.sh index b1067fa22f2..0a2be7c26d9 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio.sh @@ -15,11 +15,11 @@ printf "\n\n======== Broadcaster test =========\n\n" SIMULATION_ID="broadcaster" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=broadcast_source -rs=23 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=broadcast_sink -rs=27 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h @@ -32,11 +32,11 @@ printf "\n\n======== Broadcaster sink disconnect test =========\n\n" SIMULATION_ID="broadcaster_sink_disconnect" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=broadcast_source -rs=23 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 \ -testid=broadcast_sink_disconnect -rs=27 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_assistant.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_assistant.sh index aec89f7c6c2..4c5bf1dc6f3 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_assistant.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_broadcast_audio_assistant.sh @@ -14,15 +14,15 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running BAP Broadcast Audio Assistant =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 \ -testid=broadcast_sink_with_assistant -rs=24 -D=3 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 \ -testid=bap_broadcast_assistant_client_sync -rs=46 -D=3 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 \ -testid=broadcast_source -rs=69 -D=3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio.sh index c804336ec1f..7430b835c23 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Unicast Audio test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=unicast_client -rs=23 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=unicast_server -rs=28 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh index e3852b539ab..8976fe7330a 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Unicast Audio ACL Disconnect test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=unicast_client_acl_disconnect -rs=23 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=unicast_server_acl_disconnect -rs=28 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast.sh index ce2b37d1eae..4eb4d4f5d04 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running CAP broadcast test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_broadcast -rs=46 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_broadcast -rs=23 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_12.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_12.sh index e0a48c20701..607d6837699 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_12.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_12.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_12() { printf "\n\n======== Running CAP AC_12 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_12 \ -RealEncryption=1 -rs=23 -D=2 -argstest preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_broadcast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_13.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_13.sh index c07b59e8856..cccda168efa 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_13.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_13.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_13() { printf "\n\n======== Running CAP AC_13 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_13 \ -RealEncryption=1 -rs=23 -D=2 -argstest preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_broadcast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_14.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_14.sh index 4788975e59f..68f8446e1d9 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_14.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_ac_14.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_14() { printf "\n\n======== Running CAP AC_14 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_14 \ -RealEncryption=1 -rs=23 -D=2 -argstest preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_broadcast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_capture_and_render.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_capture_and_render.sh index e80df63b7ce..a6c6445feef 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_capture_and_render.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_capture_and_render.sh @@ -14,15 +14,15 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running CAP commander capture and rendering test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_commander_capture_and_render \ -rs=46 -D=3 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_capture_and_render \ -rs=23 -D=3 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_capture_and_render \ -rs=69 -D=3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast.sh index a4404412b3c..c65aa58ce5d 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running CAP unicast test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_unicast -rs=46 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast -rs=23 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_1.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_1.sh index 199b0144b34..e09ac9e5d3a 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_1.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_1.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_1() { printf "\n\n======== Running CAP AC_1 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_1 \ -RealEncryption=1 -rs=23 -D=2 -argstest sink_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_10.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_10.sh index af35c7ad66b..7a50f10cca5 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_10.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_10.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_10() { printf "\n\n======== Running CAP AC_10 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_10 \ -RealEncryption=1 -rs=23 -D=2 -argstest source_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_i.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_i.sh index 0356cd0b594..e74192f47ec 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_i.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_i.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_11_I() { printf "\n\n======== Running CAP AC_11_I with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_11_i \ -RealEncryption=1 -rs=23 -D=2 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_ii.sh index c83bdc8c4be..2280172b4ae 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_ii.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_ii.sh @@ -15,15 +15,15 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_11_II() { printf "\n\n======== Running CAP AC_11_II with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_11_ii \ -RealEncryption=1 -rs=23 -D=3 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=69 -D=3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_2.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_2.sh index 76a9b762fd1..0987accc4b2 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_2.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_2.sh @@ -16,11 +16,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_2() { printf "\n\n======== Running CAP AC_2 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_2 \ -RealEncryption=1 -rs=23 -D=2 -argstest source_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_3.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_3.sh index e4682d10197..79e8a39d186 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_3.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_3.sh @@ -16,11 +16,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_3() { printf "\n\n======== Running CAP AC_3 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_3 \ -RealEncryption=1 -rs=23 -D=2 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_4.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_4.sh index a863b359252..b24a16f39a2 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_4.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_4.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_4() { printf "\n\n======== Running CAP AC_4 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_4 \ -RealEncryption=1 -rs=23 -D=2 -argstest sink_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_5.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_5.sh index 5eb9f6f5e30..d42716febf8 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_5.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_5.sh @@ -16,11 +16,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_5() { printf "\n\n======== Running CAP AC_5 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_5 \ -RealEncryption=1 -rs=23 -D=2 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_i.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_i.sh index 7a848655619..344ebb0448b 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_i.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_i.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_6_I() { printf "\n\n======== Running CAP AC_6_I with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_6_i \ -RealEncryption=1 -rs=23 -D=2 -argstest sink_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_ii.sh index bb3a4dca003..e04df696908 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_ii.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_ii.sh @@ -15,15 +15,15 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_6_II() { printf "\n\n======== Running CAP AC_6_II with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_6_ii \ -RealEncryption=1 -rs=23 -D=3 -argstest sink_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=69 -D=3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_i.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_i.sh index 279322562ed..3eebbc3421f 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_i.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_i.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_7_I() { printf "\n\n======== Running CAP AC_7_I with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_7_i \ -RealEncryption=1 -rs=23 -D=2 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_ii.sh index bea1ee05173..ce6c9abdf89 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_ii.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_ii.sh @@ -15,15 +15,15 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_7_II() { printf "\n\n======== Running CAP AC_7_II with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_7_ii \ -RealEncryption=1 -rs=23 -D=3 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=69 -D=3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_i.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_i.sh index 420e08646f4..7b1e7d68481 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_i.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_i.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_8_I() { printf "\n\n======== Running CAP AC_8_I with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_8_i \ -RealEncryption=1 -rs=23 -D=2 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_ii.sh index 5de94703d69..25e07a6c149 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_ii.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_ii.sh @@ -15,15 +15,15 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_8_II() { printf "\n\n======== Running CAP AC_8_II with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_8_ii \ -RealEncryption=1 -rs=23 -D=3 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=69 -D=3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_i.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_i.sh index 75dc048593f..1a00f55e433 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_i.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_i.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_9_I() { printf "\n\n======== Running CAP AC_9_I with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_9_i \ -RealEncryption=1 -rs=23 -D=2 -argstest source_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_ii.sh index 75a02a1e38b..207d81f663e 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_ii.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_ii.sh @@ -15,15 +15,15 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_9_II() { printf "\n\n======== Running CAP AC_9_II with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_9_ii \ -RealEncryption=1 -rs=23 -D=3 -argstest source_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_unicast \ -RealEncryption=1 -rs=69 -D=3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh index 6869821f35b..4ed5224e52f 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running CAP unicast test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_unicast_inval -rs=46 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast -rs=23 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_timeout.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_timeout.sh index 65b088e9805..aac22facc1b 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_timeout.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_timeout.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running CAP unicast timeout test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_unicast_timeout -rs=46 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast_timeout -rs=23 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip.sh b/tests/bsim/bluetooth/audio/test_scripts/csip.sh index 40c7f8e3fc8..5263c927a78 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip.sh @@ -16,19 +16,19 @@ cd ${BSIM_OUT_PATH}/bin SIMULATION_ID="csip" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=csip_set_coordinator \ -RealEncryption=1 -rs=1 -D=4 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=csip_set_member \ -RealEncryption=1 -rs=2 -D=4 -argstest rank 1 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=csip_set_member \ -RealEncryption=1 -rs=3 -D=4 -argstest rank 2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=3 -testid=csip_set_member \ -RealEncryption=1 -rs=4 -D=4 -argstest rank 3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_encrypted_sirk.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_encrypted_sirk.sh index b0bdd21f932..388551c5d0c 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_encrypted_sirk.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_encrypted_sirk.sh @@ -16,19 +16,19 @@ cd ${BSIM_OUT_PATH}/bin SIMULATION_ID="csip_sirk_encrypted" printf "\n\n======== Running test with SIRK encrypted ========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=csip_set_coordinator \ -RealEncryption=1 -rs=1 -D=4 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=csip_set_member_enc \ -RealEncryption=1 -rs=2 -D=4 -argstest rank 1 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=csip_set_member_enc \ -RealEncryption=1 -rs=3 -D=4 -argstest rank 2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=3 -testid=csip_set_member_enc \ -RealEncryption=1 -rs=4 -D=4 -argstest rank 3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_forced_release.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_forced_release.sh index ee901496a64..32c84dfbaea 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_forced_release.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_forced_release.sh @@ -16,19 +16,19 @@ cd ${BSIM_OUT_PATH}/bin SIMULATION_ID="csip_forced_release" printf "\n\n======== Running test with forced release of lock ========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=csip_set_coordinator \ -RealEncryption=1 -rs=1 -D=4 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=csip_set_member \ -RealEncryption=1 -rs=2 -D=4 -argstest rank 1 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=csip_set_member \ -RealEncryption=1 -rs=3 -D=4 -argstest rank 2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=3 -testid=csip_set_member_release \ -RealEncryption=1 -rs=4 -D=4 -argstest rank 3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_new_sirk.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_new_sirk.sh index 2fb9676d759..debdca99b12 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_new_sirk.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_new_sirk.sh @@ -16,19 +16,19 @@ cd ${BSIM_OUT_PATH}/bin SIMULATION_ID="csip_new_sirk" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=csip_set_coordinator_new_sirk \ -RealEncryption=1 -rs=1 -D=4 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=csip_set_member_new_sirk \ -RealEncryption=1 -rs=2 -D=4 -argstest rank 1 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=csip_set_member_new_sirk \ -RealEncryption=1 -rs=3 -D=4 -argstest rank 2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=3 -testid=csip_set_member_new_sirk \ -RealEncryption=1 -rs=4 -D=4 -argstest rank 3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_no_lock.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_no_lock.sh index bd078ca35d5..8f8d72fed6f 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_no_lock.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_no_lock.sh @@ -15,19 +15,19 @@ cd ${BSIM_OUT_PATH}/bin SIMULATION_ID="csip_no_lock" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=csip_set_coordinator \ -RealEncryption=1 -rs=1 -D=4 -argstest no-lock -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=csip_set_member \ -RealEncryption=1 -rs=2 -D=4 -argstest rank 1 not-lockable -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=csip_set_member \ -RealEncryption=1 -rs=3 -D=4 -argstest rank 2 not-lockable -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=3 -testid=csip_set_member \ -RealEncryption=1 -rs=4 -D=4 -argstest rank 3 not-lockable diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_no_rank.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_no_rank.sh index 64127a93ebe..ad73a00fcd1 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_no_rank.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_no_rank.sh @@ -15,19 +15,19 @@ cd ${BSIM_OUT_PATH}/bin SIMULATION_ID="csip_no_rank" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=csip_set_coordinator \ -RealEncryption=1 -rs=1 -D=4 -argstest no-rank no-lock -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=csip_set_member \ -RealEncryption=1 -rs=2 -D=4 -argstest rank 0 not-lockable -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=csip_set_member \ -RealEncryption=1 -rs=3 -D=4 -argstest rank 0 not-lockable -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=3 -testid=csip_set_member \ -RealEncryption=1 -rs=4 -D=4 -argstest rank 0 not-lockable diff --git a/tests/bsim/bluetooth/audio/test_scripts/csip_no_size.sh b/tests/bsim/bluetooth/audio/test_scripts/csip_no_size.sh index 0334d36470f..f76d350b29d 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/csip_no_size.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/csip_no_size.sh @@ -15,19 +15,19 @@ cd ${BSIM_OUT_PATH}/bin SIMULATION_ID="csip_no_size" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=csip_set_coordinator \ -RealEncryption=1 -rs=1 -D=4 -argstest no-size -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=csip_set_member \ -RealEncryption=1 -rs=2 -D=4 -argstest rank 1 size 0 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=csip_set_member \ -RealEncryption=1 -rs=3 -D=4 -argstest rank 2 size 0 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=3 -testid=csip_set_member \ -RealEncryption=1 -rs=4 -D=4 -argstest rank 3s size 0 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_12.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_12.sh index fa9d62b8e16..7f8c28b19a3 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_12.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_12.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_12() { printf "\n\n======== Running GMAP AC_12 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_12 \ -RealEncryption=1 -rs=23 -D=2 -argstest broadcast_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_broadcast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_13.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_13.sh index 0f442f2e3a7..7f84a8b4868 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_13.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_13.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_13() { printf "\n\n======== Running GMAP AC_13 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_13 \ -RealEncryption=1 -rs=23 -D=2 -argstest broadcast_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_broadcast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_14.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_14.sh index dbde3ef33c7..a16adf3af1b 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_14.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_broadcast_ac_14.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_14() { printf "\n\n======== Running GMAP AC_14 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_14 \ -RealEncryption=1 -rs=23 -D=2 -argstest broadcast_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_broadcast \ -RealEncryption=1 -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_1.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_1.sh index 37664d7c6aa..cf5c7ea0cf5 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_1.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_1.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_1() { printf "\n\n======== Running GMAP AC_1 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_1 -RealEncryption=1 \ -rs=23 -D=2 -argstest sink_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_11_i.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_11_i.sh index 8ba1f94696d..29212355a60 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_11_i.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_11_i.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_11_I() { printf "\n\n======== Running GMAP AC_11_I with %s and %s =========\n\n" $1 $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_11_i -RealEncryption=1 \ -rs=23 -D=2 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_11_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_11_ii.sh index 7fcf451cfa8..fa14ae28a31 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_11_ii.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_11_ii.sh @@ -15,15 +15,15 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_11_II() { printf "\n\n======== Running GMAP AC_11_II with %s and %s =========\n\n" $1 $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_11_ii -RealEncryption=1 \ -rs=23 -D=3 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=gmap_ugt -RealEncryption=1 \ -rs=69 -D=3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_2.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_2.sh index d297b591a64..69ad6b807c2 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_2.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_2.sh @@ -16,11 +16,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_2() { printf "\n\n======== Running GMAP AC_2 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_2 -RealEncryption=1 \ -rs=23 -D=2 -argstest source_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_3.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_3.sh index a23c5f61fa7..0883d9a5b36 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_3.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_3.sh @@ -16,11 +16,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_3() { printf "\n\n======== Running GMAP AC_3 with %s and %s =========\n\n" $1 $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_3 -RealEncryption=1 \ -rs=23 -D=2 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_4.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_4.sh index 84a4d425c66..be127ae7bb3 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_4.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_4.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_4() { printf "\n\n======== Running GMAP AC_4 with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_4 -RealEncryption=1 \ -rs=23 -D=2 -argstest sink_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_5.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_5.sh index 1be847e2f64..b5cf2c93421 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_5.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_5.sh @@ -16,11 +16,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_5() { printf "\n\n======== Running GMAP AC_5 with %s and %s =========\n\n" $1 $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_5 -RealEncryption=1 \ -rs=23 -D=2 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_6_i.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_6_i.sh index 59810ccf940..2fa042b5b2c 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_6_i.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_6_i.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_6_I() { printf "\n\n======== Running GMAP AC_6_I with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_6_i -RealEncryption=1 \ -rs=23 -D=2 -argstest sink_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_6_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_6_ii.sh index 355a2f365ac..ece76364ab0 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_6_ii.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_6_ii.sh @@ -15,15 +15,15 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_6_II() { printf "\n\n======== Running GMAP AC_6_II with %s =========\n\n" $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_6_ii -RealEncryption=1 \ -rs=23 -D=3 -argstest sink_preset $1 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=gmap_ugt -RealEncryption=1 \ -rs=69 -D=3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_7_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_7_ii.sh index 37b60a18cf0..edb6cbc69fd 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_7_ii.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_7_ii.sh @@ -15,15 +15,15 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_7_II() { printf "\n\n======== Running GMAP AC_7_II with %s and %s =========\n\n" $1 $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_7_ii -RealEncryption=1 \ -rs=23 -D=3 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=gmap_ugt -RealEncryption=1 \ -rs=69 -D=3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_8_i.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_8_i.sh index b8d6ebcbe61..ced2d67d754 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_8_i.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_8_i.sh @@ -15,11 +15,11 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_8_I() { printf "\n\n======== Running GMAP AC_8_I with %s and %s =========\n\n" $1 $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_8_i -RealEncryption=1 \ -rs=23 -D=2 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=2 diff --git a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_8_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_8_ii.sh index 35c0fba70a1..14d56906b5a 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_8_ii.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/gmap_unicast_ac_8_ii.sh @@ -15,15 +15,15 @@ cd ${BSIM_OUT_PATH}/bin function Execute_AC_8_II() { printf "\n\n======== Running GMAP AC_8_II with %s and %s =========\n\n" $1 $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=gmap_ugg_ac_8_ii -RealEncryption=1 \ -rs=23 -D=3 -argstest sink_preset $1 source_preset $2 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=gmap_ugt -RealEncryption=1 \ -rs=46 -D=3 - Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ + Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=gmap_ugt -RealEncryption=1 \ -rs=69 -D=3 diff --git a/tests/bsim/bluetooth/audio/test_scripts/has.sh b/tests/bsim/bluetooth/audio/test_scripts/has.sh index 3d7f6508fd0..54fa56ae460 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/has.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/has.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running HAS main (API) test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=has -rs=24 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=has_client -rs=46 -D=2 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \ diff --git a/tests/bsim/bluetooth/audio/test_scripts/has_offline.sh b/tests/bsim/bluetooth/audio/test_scripts/has_offline.sh index 7e5b0a40d7a..c6844d4f1b3 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/has_offline.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/has_offline.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n Running Preset Changed Offline Behavior test \n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=has_offline_behavior -rs=24 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=has_client_offline_behavior -rs=46 -D=2 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \ diff --git a/tests/bsim/bluetooth/audio/test_scripts/ias.sh b/tests/bsim/bluetooth/audio/test_scripts/ias.sh index cf3afed69ed..6655f9f23f0 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/ias.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/ias.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running IAS main (API) test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=ias -rs=23 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=ias_client -rs=6 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/mcs_mcc.sh b/tests/bsim/bluetooth/audio/test_scripts/mcs_mcc.sh index f901aa34f41..7e72d47916b 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/mcs_mcc.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/mcs_mcc.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running MCS and MCC test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=mcc -rs=46 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=mcs -rs=23 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/media_controller.sh b/tests/bsim/bluetooth/audio/test_scripts/media_controller.sh index 3e504f7275e..ca53b2b0be7 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/media_controller.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/media_controller.sh @@ -14,7 +14,7 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running media controller local_player test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=media_controller_local_player -rs=23 -D=1 # Simulation time should be larger than the WAIT_TIME in common.h @@ -25,10 +25,10 @@ wait_for_background_jobs printf "\n\n======== Running media controller remote_player test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=media_controller_remote_player -rs=46 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=media_controller_server -rs=23 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/micp.sh b/tests/bsim/bluetooth/audio/test_scripts/micp.sh index 56bc0ac4650..a943107ad7d 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/micp.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/micp.sh @@ -14,7 +14,7 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n==== Running MICP Microphone Device Only (API) test ====n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=micp_mic_dev_only -rs=23 -D=1 # Simulation time should be larger than the WAIT_TIME in common.h @@ -25,10 +25,10 @@ wait_for_background_jobs printf "\n\n==== Running MICP Microphone Device and MICP Microphone Controller test ====n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=micp_mic_dev -rs=23 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=micp_mic_ctlr -rs=46 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/pacs_notify.sh b/tests/bsim/bluetooth/audio/test_scripts/pacs_notify.sh index 721a794cbd3..90fcf1080f8 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/pacs_notify.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/pacs_notify.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running PACS Notify test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=pacs_notify_server -rs=24 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=pacs_notify_client -rs=46 -D=2 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \ diff --git a/tests/bsim/bluetooth/audio/test_scripts/pbp.sh b/tests/bsim/bluetooth/audio/test_scripts/pbp.sh index ff5499a14f8..416203c0f15 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/pbp.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/pbp.sh @@ -15,10 +15,10 @@ printf "\n\n======== Public Broadcaster test =========\n\n" SIMULATION_ID="pbp_broadcaster" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=public_broadcast_source -rs=27 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=public_broadcast_sink -rs=27 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/tbs.sh b/tests/bsim/bluetooth/audio/test_scripts/tbs.sh index 491443a60aa..02d044bf622 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/tbs.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/tbs.sh @@ -15,7 +15,7 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n==== Running TBS Server Only (API) test ====n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=tbs_test_server_only -rs=23 -D=1 # Simulation time should be larger than the WAIT_TIME in common.h @@ -26,10 +26,10 @@ wait_for_background_jobs printf "\n\n==== Running TBS server & client tests ====n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=tbs -rs=23 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=tbs_client -rs=6 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/tmap.sh b/tests/bsim/bluetooth/audio/test_scripts/tmap.sh index 069d4b463bb..7bf4dc2ba7c 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/tmap.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/tmap.sh @@ -14,10 +14,10 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running TMAP client & server test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=tmap_client -rs=24 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=tmap_server -rs=23 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio/test_scripts/vcp.sh b/tests/bsim/bluetooth/audio/test_scripts/vcp.sh index 8d394c225b6..b90d0deba26 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/vcp.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/vcp.sh @@ -14,7 +14,7 @@ cd ${BSIM_OUT_PATH}/bin printf "\n\n======== Running VCP Volume Renderer standalone (API) test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=vcp_vol_rend_standalone -rs=23 -D=1 # Simulation time should be larger than the WAIT_TIME in common.h @@ -25,10 +25,10 @@ wait_for_background_jobs printf "\n\n======== Running VCP Volume Renderer and VCP Volume Controller test =========\n\n" -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=vcp_vol_rend -rs=23 -D=2 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=vcp_vol_ctlr -rs=46 -D=2 # Simulation time should be larger than the WAIT_TIME in common.h diff --git a/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/tests_scripts/broadcast_audio.sh b/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/tests_scripts/broadcast_audio.sh index e1881cbe920..3a0cb45f9d4 100755 --- a/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/tests_scripts/broadcast_audio.sh +++ b/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/tests_scripts/broadcast_audio.sh @@ -16,10 +16,10 @@ EXECUTE_TIMEOUT=200 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_samples_bluetooth_broadcast_audio_source_prj_conf \ +Execute ./bs_${BOARD_TS}_samples_bluetooth_broadcast_audio_source_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=1 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_samples_broadcast_audio_sink_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_samples_broadcast_audio_sink_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=1 \ -testid=broadcast_audio_sink diff --git a/tests/bsim/bluetooth/audio_samples/compile.sh b/tests/bsim/bluetooth/audio_samples/compile.sh index 79b1a212c6e..a54aace2777 100755 --- a/tests/bsim/bluetooth/audio_samples/compile.sh +++ b/tests/bsim/bluetooth/audio_samples/compile.sh @@ -25,19 +25,19 @@ if [ "${BOARD}" == "nrf5340bsim_nrf5340_cpuapp" ]; then app=tests/bsim/bluetooth/audio_samples/unicast_audio_client sysbuild=1 compile app=tests/bsim/bluetooth/audio_samples/broadcast_audio_sink sysbuild=1 \ conf_file=${ZEPHYR_BASE}/samples/bluetooth/broadcast_audio_sink/prj.conf \ - exe_name=bs_${BOARD}_${app}_prj_conf sysbuild=1 compile + exe_name=bs_${BOARD_TS}_${app}_prj_conf sysbuild=1 compile else app=samples/bluetooth/unicast_audio_server conf_overlay=overlay-bt_ll_sw_split.conf \ - exe_name=bs_${BOARD}_${app}_prj_conf sysbuild=1 compile + exe_name=bs_${BOARD_TS}_${app}_prj_conf sysbuild=1 compile app=samples/bluetooth/broadcast_audio_source conf_overlay=overlay-bt_ll_sw_split.conf \ - exe_name=bs_${BOARD}_${app}_prj_conf sysbuild=1 compile + exe_name=bs_${BOARD_TS}_${app}_prj_conf sysbuild=1 compile app=tests/bsim/bluetooth/audio_samples/unicast_audio_client \ conf_overlay=${ZEPHYR_BASE}/samples/bluetooth/unicast_audio_client/overlay-bt_ll_sw_split.conf \ - exe_name=bs_${BOARD}_${app}_prj_conf sysbuild=1 compile + exe_name=bs_${BOARD_TS}_${app}_prj_conf sysbuild=1 compile app=tests/bsim/bluetooth/audio_samples/broadcast_audio_sink \ conf_file=${ZEPHYR_BASE}/samples/bluetooth/broadcast_audio_sink/prj.conf \ conf_overlay=${ZEPHYR_BASE}/samples/bluetooth/broadcast_audio_sink/overlay-bt_ll_sw_split.conf \ - exe_name=bs_${BOARD}_${app}_prj_conf sysbuild=1 compile + exe_name=bs_${BOARD_TS}_${app}_prj_conf sysbuild=1 compile fi wait_for_background_jobs diff --git a/tests/bsim/bluetooth/audio_samples/unicast_audio_client/tests_scripts/unicast_client.sh b/tests/bsim/bluetooth/audio_samples/unicast_audio_client/tests_scripts/unicast_client.sh index 6387b68af7f..065551b7e85 100755 --- a/tests/bsim/bluetooth/audio_samples/unicast_audio_client/tests_scripts/unicast_client.sh +++ b/tests/bsim/bluetooth/audio_samples/unicast_audio_client/tests_scripts/unicast_client.sh @@ -16,10 +16,10 @@ EXECUTE_TIMEOUT=100 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_samples_bluetooth_unicast_audio_server_prj_conf \ +Execute ./bs_${BOARD_TS}_samples_bluetooth_unicast_audio_server_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=1 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_audio_samples_unicast_audio_client_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_samples_unicast_audio_client_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=1 \ -testid=unicast_client diff --git a/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart.sh b/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart.sh index 014a3bf98c0..7f5907763d6 100755 --- a/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart.sh +++ b/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart.sh @@ -21,22 +21,22 @@ UART_CEN=${UART_DIR}/central # Note the host+app devices are NOT connected to the phy, only the controllers are. # Peripheral app + host : -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_hci_uart_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_hci_uart_conf \ -v=${verbosity_level} -s=${simulation_id} -d=10 -nosim -RealEncryption=0 \ -testid=peripheral -rs=23 -uart1_fifob_rxfile=${UART_PER}.rx -uart1_fifob_txfile=${UART_PER}.tx # Peripheral controller: -Execute ./bs_${BOARD}_samples_bluetooth_hci_uart_prj_conf \ +Execute ./bs_${BOARD_TS}_samples_bluetooth_hci_uart_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -rs=23 -uart1_fifob_rxfile=${UART_PER}.tx -uart1_fifob_txfile=${UART_PER}.rx \ # Central app + host -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_hci_uart_conf\ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_hci_uart_conf\ -v=${verbosity_level} -s=${simulation_id} -d=11 -nosim -RealEncryption=0 \ -testid=central -rs=6 -uart1_fifob_rxfile=${UART_CEN}.rx -uart1_fifob_txfile=${UART_CEN}.tx # Central controller: -Execute ./bs_${BOARD}_samples_bluetooth_hci_uart_prj_conf \ +Execute ./bs_${BOARD_TS}_samples_bluetooth_hci_uart_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -rs=23 -uart1_fifob_rxfile=${UART_CEN}.tx -uart1_fifob_txfile=${UART_CEN}.rx diff --git a/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart_async.sh b/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart_async.sh index a2d3728eb4d..a1dc0e1a482 100755 --- a/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart_async.sh +++ b/tests/bsim/bluetooth/hci_uart/tests_scripts/basic_conn_split_hci_uart_async.sh @@ -21,22 +21,22 @@ UART_CEN=${UART_DIR}/central # Note the host+app devices are NOT connected to the phy, only the controllers are. # Peripheral app + host : -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_hci_uart_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_hci_uart_conf \ -v=${verbosity_level} -s=${simulation_id} -d=10 -nosim -RealEncryption=0 \ -testid=peripheral -rs=23 -uart1_fifob_rxfile=${UART_PER}.rx -uart1_fifob_txfile=${UART_PER}.tx # Peripheral controller: -Execute ./bs_${BOARD}_samples_bluetooth_hci_uart_async_prj_conf \ +Execute ./bs_${BOARD_TS}_samples_bluetooth_hci_uart_async_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -rs=23 -uart1_fifob_rxfile=${UART_PER}.tx -uart1_fifob_txfile=${UART_PER}.rx # Central app + host -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_hci_uart_conf\ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_hci_uart_conf\ -v=${verbosity_level} -s=${simulation_id} -d=11 -nosim -RealEncryption=0 \ -testid=central -rs=6 -uart1_fifob_rxfile=${UART_CEN}.rx -uart1_fifob_txfile=${UART_CEN}.tx # Central controller: -Execute ./bs_${BOARD}_samples_bluetooth_hci_uart_async_prj_conf \ +Execute ./bs_${BOARD_TS}_samples_bluetooth_hci_uart_async_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -rs=23 -uart1_fifob_rxfile=${UART_CEN}.tx -uart1_fifob_txfile=${UART_CEN}.rx diff --git a/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh b/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh index b50de2bf31a..045b1eba649 100755 --- a/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh +++ b/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh @@ -11,10 +11,10 @@ verbosity_level=2 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_chain_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_chain_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=adv -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_chain_prj_conf\ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_chain_prj_conf\ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=scan Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/run_tests.sh b/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/run_tests.sh index eb7a8b0c954..0ac5936aaa3 100755 --- a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/run_tests.sh +++ b/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/run_tests.sh @@ -6,7 +6,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="$(guess_test_long_name)" verbosity_level=2 -test_exe="bs_${BOARD}_$(guess_test_long_name)_prj_conf" +test_exe="bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/encrypted/ead_sample/test_scripts/ead_sample.sh b/tests/bsim/bluetooth/host/adv/encrypted/ead_sample/test_scripts/ead_sample.sh index 8a7c0ca0696..ae3b7d53f00 100755 --- a/tests/bsim/bluetooth/host/adv/encrypted/ead_sample/test_scripts/ead_sample.sh +++ b/tests/bsim/bluetooth/host/adv/encrypted/ead_sample/test_scripts/ead_sample.sh @@ -9,10 +9,10 @@ verbosity_level=2 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_encrypted_ead_sample_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_encrypted_ead_sample_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_encrypted_ead_sample_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_encrypted_ead_sample_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv.sh b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv.sh index 84fc0cd65cc..d164626e420 100755 --- a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv.sh +++ b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv.sh @@ -14,11 +14,11 @@ verbosity_level=2 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_extended_prj_advertiser_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_extended_prj_advertiser_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -testid=ext_adv_advertiser -rs=23 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_extended_prj_scanner_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_extended_prj_scanner_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -testid=ext_adv_scanner -rs=6 diff --git a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn.sh b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn.sh index 6bee0bfc3ba..50a56853be6 100755 --- a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn.sh +++ b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn.sh @@ -16,11 +16,11 @@ verbosity_level=2 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_extended_prj_advertiser_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_extended_prj_advertiser_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -testid=ext_adv_conn_advertiser -rs=23 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_extended_prj_scanner_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_extended_prj_scanner_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -testid=ext_adv_conn_scanner -rs=6 diff --git a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn_x5.sh b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn_x5.sh index 9abfca4d5a1..c5f3b3d10c2 100755 --- a/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn_x5.sh +++ b/tests/bsim/bluetooth/host/adv/extended/tests_scripts/ext_adv_conn_x5.sh @@ -16,11 +16,11 @@ verbosity_level=2 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_extended_prj_advertiser_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_extended_prj_advertiser_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -testid=ext_adv_conn_advertiser_x5 -rs=23 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_extended_prj_scanner_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_extended_prj_scanner_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -testid=ext_adv_conn_scanner_x5 -rs=6 diff --git a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv.sh b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv.sh index cce67bd932b..4e88aa57cc5 100755 --- a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv.sh +++ b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv.sh @@ -12,11 +12,11 @@ verbosity_level=2 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -testid=per_adv_advertiser -rs=23 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -testid=per_adv_syncer -rs=6 diff --git a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn.sh b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn.sh index ea817d4f631..9c4823538f6 100755 --- a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn.sh +++ b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn.sh @@ -12,11 +12,11 @@ verbosity_level=2 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -testid=per_adv_conn_advertiser -rs=23 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -testid=per_adv_conn_syncer -rs=6 diff --git a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn_privacy.sh b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn_privacy.sh index 5be5a68fce7..a8d2cdcd31d 100755 --- a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn_privacy.sh +++ b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_conn_privacy.sh @@ -12,11 +12,11 @@ verbosity_level=2 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -testid=per_adv_conn_privacy_advertiser -rs=23 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_periodic_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -testid=per_adv_conn_privacy_syncer -rs=6 diff --git a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_long_data.sh b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_long_data.sh index 802a64919e7..53ef8e9cbf7 100755 --- a/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_long_data.sh +++ b/tests/bsim/bluetooth/host/adv/periodic/tests_scripts/per_adv_long_data.sh @@ -12,11 +12,11 @@ verbosity_level=2 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_periodic_prj_long_data_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_periodic_prj_long_data_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -testid=per_adv_long_data_advertiser -rs=23 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_adv_periodic_prj_long_data_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_periodic_prj_long_data_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -testid=per_adv_long_data_syncer -rs=6 diff --git a/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume.sh b/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume.sh index 3a1fa18594d..4071a39deb7 100755 --- a/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume.sh +++ b/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume.sh @@ -7,7 +7,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="$(guess_test_long_name)" verbosity_level=2 -test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume_2.sh b/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume_2.sh index 3ee0700268c..68f96a28fd5 100755 --- a/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume_2.sh +++ b/tests/bsim/bluetooth/host/adv/resume/test_scripts/run_adv_resume_2.sh @@ -7,8 +7,8 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="$(guess_test_long_name)_2" verbosity_level=2 -test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" -test_2_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_2_conf" +test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" +test_2_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_2_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/autoconnect.sh b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/autoconnect.sh index ac420c136e7..2d22d4b817e 100755 --- a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/autoconnect.sh +++ b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/autoconnect.sh @@ -10,10 +10,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_prj_autoconnect_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_prj_autoconnect_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central_autoconnect -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_prj_autoconnect_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_prj_autoconnect_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral_autoconnect Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/collision.sh b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/collision.sh index 75da68b029b..d824a4b6895 100755 --- a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/collision.sh +++ b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/collision.sh @@ -10,10 +10,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_prj_collision_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_prj_collision_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_prj_collision_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_prj_collision_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/lowres.sh b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/lowres.sh index 4c7ff4ff773..92abc234ed1 100755 --- a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/lowres.sh +++ b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/lowres.sh @@ -10,10 +10,10 @@ EXECUTE_TIMEOUT=20 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_prj_autoconnect_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_prj_autoconnect_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central_lowres -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_prj_lowres_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_prj_lowres_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral_lowres Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/multiple_conn.sh b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/multiple_conn.sh index 5cc4ec693a0..962c10d5631 100755 --- a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/multiple_conn.sh +++ b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/multiple_conn.sh @@ -10,10 +10,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_prj_multiple_conn_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_prj_multiple_conn_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_prj_multiple_conn_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_prj_multiple_conn_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/reconfigure.sh b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/reconfigure.sh index 2a9000b2429..e95468a522f 100755 --- a/tests/bsim/bluetooth/host/att/eatt/tests_scripts/reconfigure.sh +++ b/tests/bsim/bluetooth/host/att/eatt/tests_scripts/reconfigure.sh @@ -10,10 +10,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_prj_autoconnect_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_prj_autoconnect_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central_reconfigure -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_prj_autoconnect_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_prj_autoconnect_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral_reconfigure Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/att/eatt_notif/test_scripts/eatt_notif.sh b/tests/bsim/bluetooth/host/att/eatt_notif/test_scripts/eatt_notif.sh index 3385b6fe6dc..d2df9216cf7 100755 --- a/tests/bsim/bluetooth/host/att/eatt_notif/test_scripts/eatt_notif.sh +++ b/tests/bsim/bluetooth/host/att/eatt_notif/test_scripts/eatt_notif.sh @@ -12,10 +12,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_notif_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_notif_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=client -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_att_eatt_notif_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_eatt_notif_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=server Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/att/long_read/test_scripts/run.sh b/tests/bsim/bluetooth/host/att/long_read/test_scripts/run.sh index b6b9ca57fec..148865c5474 100755 --- a/tests/bsim/bluetooth/host/att/long_read/test_scripts/run.sh +++ b/tests/bsim/bluetooth/host/att/long_read/test_scripts/run.sh @@ -7,7 +7,7 @@ set -eu source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="long_read" -dev_exe=bs_${BOARD}_$(guess_test_long_name)_prj_conf +dev_exe=bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf args_all=(-s=${simulation_id} -D=2) args_dev=(-v=2 -RealEncryption=1 -testid=the_test) diff --git a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh index c49ac8369b2..37901c362a3 100755 --- a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/run_test.sh @@ -7,7 +7,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="$(guess_test_long_name)" verbosity_level=2 -central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh b/tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh index e66c4f13d9c..b247a5be0be 100755 --- a/tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh +++ b/tests/bsim/bluetooth/host/att/open_close/test_scripts/run.sh @@ -7,7 +7,7 @@ set -eu source ${ZEPHYR_BASE}/tests/bsim/sh_common.source test_path=$(guess_test_long_name) -dev_exe="bs_${BOARD}_${test_path}_prj_conf" +dev_exe="bs_${BOARD_TS}_${test_path}_prj_conf" simulation_id="${test_path}" EXECUTE_TIMEOUT=60 diff --git a/tests/bsim/bluetooth/host/att/pipeline/test_scripts/run.sh b/tests/bsim/bluetooth/host/att/pipeline/test_scripts/run.sh index 416484c27d2..a31fa94d7da 100755 --- a/tests/bsim/bluetooth/host/att/pipeline/test_scripts/run.sh +++ b/tests/bsim/bluetooth/host/att/pipeline/test_scripts/run.sh @@ -4,8 +4,8 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -dut_exe="bs_${BOARD}_tests_bsim_bluetooth_host_att_pipeline_dut_prj_conf" -tester_exe="bs_${BOARD}_tests_bsim_bluetooth_host_att_pipeline_tester_prj_conf" +dut_exe="bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_pipeline_dut_prj_conf" +tester_exe="bs_${BOARD_TS}_tests_bsim_bluetooth_host_att_pipeline_tester_prj_conf" simulation_id="att_pipeline" verbosity_level=2 diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/run_tests.sh b/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/run_tests.sh index 8f540dfaba1..2c51d5ff3f5 100755 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/run_tests.sh +++ b/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/run_tests.sh @@ -8,8 +8,8 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id="read_fill_buf" -test_exe_d0="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_client_prj_conf" -test_exe_d1="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_server_prj_conf" +test_exe_d0="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_client_prj_conf" +test_exe_d1="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_server_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test.sh index b822a7c1a96..da52822211f 100755 --- a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test.sh @@ -8,8 +8,8 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="retry_on_sec_err" verbosity_level=2 -test_exe_d0="./bs_${BOARD}_$(guess_test_long_name)_client_prj_conf" -test_exe_d1="./bs_${BOARD}_$(guess_test_long_name)_server_prj_conf" +test_exe_d0="./bs_${BOARD_TS}_$(guess_test_long_name)_client_prj_conf" +test_exe_d1="./bs_${BOARD_TS}_$(guess_test_long_name)_server_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test_security_request.sh b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test_security_request.sh index 311def7e06f..15c973a8cd1 100755 --- a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test_security_request.sh +++ b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/run_test_security_request.sh @@ -7,8 +7,8 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="retry_on_sec_err_seq_request" verbosity_level=2 -test_exe_d0="./bs_${BOARD}_$(guess_test_long_name)_client_prj_conf" -test_exe_d1="./bs_${BOARD}_$(guess_test_long_name)_server_prj_conf" +test_exe_d0="./bs_${BOARD_TS}_$(guess_test_long_name)_client_prj_conf" +test_exe_d1="./bs_${BOARD_TS}_$(guess_test_long_name)_server_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/att/sequential/test_scripts/sequential.sh b/tests/bsim/bluetooth/host/att/sequential/test_scripts/sequential.sh index c7db4e95820..b67a1fa379d 100755 --- a/tests/bsim/bluetooth/host/att/sequential/test_scripts/sequential.sh +++ b/tests/bsim/bluetooth/host/att/sequential/test_scripts/sequential.sh @@ -7,8 +7,8 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="att_sequential" verbosity_level=2 -dut_exe="bs_${BOARD}_$(guess_test_long_name)_dut_prj_conf" -tester_exe="bs_${BOARD}_$(guess_test_long_name)_tester_prj_conf" +dut_exe="bs_${BOARD_TS}_$(guess_test_long_name)_dut_prj_conf" +tester_exe="bs_${BOARD_TS}_$(guess_test_long_name)_tester_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/gatt/authorization/test_scripts/gatt.sh b/tests/bsim/bluetooth/host/gatt/authorization/test_scripts/gatt.sh index edad0eb86c9..359247e08d9 100755 --- a/tests/bsim/bluetooth/host/gatt/authorization/test_scripts/gatt.sh +++ b/tests/bsim/bluetooth/host/gatt/authorization/test_scripts/gatt.sh @@ -10,10 +10,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_authorization_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_authorization_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=gatt_client -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_authorization_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_authorization_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=gatt_server Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/gatt/caching/test_scripts/_run_test.sh b/tests/bsim/bluetooth/host/gatt/caching/test_scripts/_run_test.sh index 932e7c23a76..a8399b79eb9 100755 --- a/tests/bsim/bluetooth/host/gatt/caching/test_scripts/_run_test.sh +++ b/tests/bsim/bluetooth/host/gatt/caching/test_scripts/_run_test.sh @@ -9,10 +9,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_caching_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_caching_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=${client_id} -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_caching_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_caching_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=${server_id} Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store.sh b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store.sh index ef47bab1a91..108ce0ba219 100755 --- a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store.sh +++ b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store.sh @@ -4,7 +4,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -test_exe="bs_${BOARD}_$(guess_test_long_name)_prj_conf" +test_exe="bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" simulation_id="ccc_store" verbosity_level=2 diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_2.sh b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_2.sh index ec74cb27dd8..5907d7f1f66 100755 --- a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_2.sh +++ b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_2.sh @@ -4,7 +4,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -test_exe="bs_${BOARD}_$(guess_test_long_name)_prj_2_conf" +test_exe="bs_${BOARD_TS}_$(guess_test_long_name)_prj_2_conf" simulation_id="ccc_store_2" verbosity_level=2 diff --git a/tests/bsim/bluetooth/host/gatt/general/test_scripts/gatt.sh b/tests/bsim/bluetooth/host/gatt/general/test_scripts/gatt.sh index eb6f22ace1a..4cae0b21812 100755 --- a/tests/bsim/bluetooth/host/gatt/general/test_scripts/gatt.sh +++ b/tests/bsim/bluetooth/host/gatt/general/test_scripts/gatt.sh @@ -14,10 +14,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_general_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_general_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=gatt_client -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_general_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_general_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=gatt_server Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/gatt/notify/test_scripts/_run_test.sh b/tests/bsim/bluetooth/host/gatt/notify/test_scripts/_run_test.sh index 4d02d42a00c..ae652cf94ac 100755 --- a/tests/bsim/bluetooth/host/gatt/notify/test_scripts/_run_test.sh +++ b/tests/bsim/bluetooth/host/gatt/notify/test_scripts/_run_test.sh @@ -10,10 +10,10 @@ EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_notify_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_notify_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=${client_id} -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_notify_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_notify_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=${server_id} Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/gatt/notify_multiple/test_scripts/_notify-debug.sh b/tests/bsim/bluetooth/host/gatt/notify_multiple/test_scripts/_notify-debug.sh index 08de518bec4..b104a3d666a 100755 --- a/tests/bsim/bluetooth/host/gatt/notify_multiple/test_scripts/_notify-debug.sh +++ b/tests/bsim/bluetooth/host/gatt/notify_multiple/test_scripts/_notify-debug.sh @@ -26,11 +26,11 @@ if [[ $2 == "debug" ]]; then fi if [[ $1 == "client" ]]; then -$GDB_P ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_notify_multiple_prj_conf \ +$GDB_P ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_notify_multiple_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=gatt_client elif [[ $1 == "server" ]]; then -$GDB_P ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_notify_multiple_prj_conf \ +$GDB_P ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_notify_multiple_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=gatt_server else diff --git a/tests/bsim/bluetooth/host/gatt/notify_multiple/test_scripts/notify.sh b/tests/bsim/bluetooth/host/gatt/notify_multiple/test_scripts/notify.sh index b4cf3fd91a3..11e85961622 100755 --- a/tests/bsim/bluetooth/host/gatt/notify_multiple/test_scripts/notify.sh +++ b/tests/bsim/bluetooth/host/gatt/notify_multiple/test_scripts/notify.sh @@ -11,10 +11,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_notify_multiple_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_notify_multiple_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=gatt_client -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_gatt_notify_multiple_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_notify_multiple_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=gatt_server Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/sc_indicate.sh b/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/sc_indicate.sh index b46ae13929c..3018a5c8771 100755 --- a/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/sc_indicate.sh +++ b/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/sc_indicate.sh @@ -5,7 +5,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source test_name='sc_indicate' -test_exe="bs_${BOARD}_tests_bsim_bluetooth_host_gatt_${test_name}_prj_conf" +test_exe="bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_${test_name}_prj_conf" simulation_id="${test_name}" verbosity_level=2 EXECUTE_TIMEOUT=30 diff --git a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings.sh b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings.sh index 2a78f040771..e6012eb616a 100755 --- a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings.sh +++ b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings.sh @@ -8,7 +8,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="settings" verbosity_level=2 EXECUTE_TIMEOUT=120 -test_exe="./bs_${BOARD}_$(guess_test_long_name)_prj_conf" +test_exe="./bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings_2.sh b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings_2.sh index 6042d9eeb1e..b4d3d16b01f 100755 --- a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings_2.sh +++ b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/run_gatt_settings_2.sh @@ -8,7 +8,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="settings_2" verbosity_level=2 EXECUTE_TIMEOUT=120 -test_2_exe="./bs_${BOARD}_$(guess_test_long_name)_prj_2_conf" +test_2_exe="./bs_${BOARD_TS}_$(guess_test_long_name)_prj_2_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/id/settings/test_scripts/settings.sh b/tests/bsim/bluetooth/host/id/settings/test_scripts/settings.sh index 7e031a930c1..ea9f7660887 100755 --- a/tests/bsim/bluetooth/host/id/settings/test_scripts/settings.sh +++ b/tests/bsim/bluetooth/host/id/settings/test_scripts/settings.sh @@ -4,7 +4,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -test_exe="bs_${BOARD}_tests_bsim_bluetooth_host_id_settings_prj_conf" +test_exe="bs_${BOARD_TS}_tests_bsim_bluetooth_host_id_settings_prj_conf" simulation_id="id_settings" verbosity_level=2 diff --git a/tests/bsim/bluetooth/host/iso/cis/tests_scripts/cis.sh b/tests/bsim/bluetooth/host/iso/cis/tests_scripts/cis.sh index 5cf55fde8e3..b693f094567 100755 --- a/tests/bsim/bluetooth/host/iso/cis/tests_scripts/cis.sh +++ b/tests/bsim/bluetooth/host/iso/cis/tests_scripts/cis.sh @@ -10,10 +10,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_iso_cis_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_iso_cis_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_iso_cis_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_iso_cis_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits.sh b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits.sh index 1a4aae35915..5595dde430c 100755 --- a/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits.sh +++ b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits.sh @@ -6,7 +6,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id=$(guess_test_long_name) -bsim_exe=./bs_${BOARD}_$(guess_test_long_name)_prj_conf +bsim_exe=./bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits_ecred.sh b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits_ecred.sh index eb68324bd31..46ba8a27033 100755 --- a/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits_ecred.sh +++ b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/l2cap_credits_ecred.sh @@ -6,7 +6,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id=$(guess_test_long_name)_ecred -bsim_exe=./bs_${BOARD}_$(guess_test_long_name)_prj_ecred_conf +bsim_exe=./bs_${BOARD_TS}_$(guess_test_long_name)_prj_ecred_conf cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv.sh b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv.sh index 1a4aae35915..5595dde430c 100755 --- a/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv.sh +++ b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv.sh @@ -6,7 +6,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id=$(guess_test_long_name) -bsim_exe=./bs_${BOARD}_$(guess_test_long_name)_prj_conf +bsim_exe=./bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv_ecred.sh b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv_ecred.sh index eb68324bd31..46ba8a27033 100755 --- a/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv_ecred.sh +++ b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/l2cap_credits_seg_recv_ecred.sh @@ -6,7 +6,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id=$(guess_test_long_name)_ecred -bsim_exe=./bs_${BOARD}_$(guess_test_long_name)_prj_ecred_conf +bsim_exe=./bs_${BOARD_TS}_$(guess_test_long_name)_prj_ecred_conf cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/run.sh b/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/run.sh index e14372a1052..e3a7b8e624d 100755 --- a/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/run.sh +++ b/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/run.sh @@ -6,7 +6,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id=$(guess_test_long_name) -bsim_exe=./bs_${BOARD}_$(guess_test_long_name)_prj_conf +bsim_exe=./bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/l2cap/general/tests_scripts/l2cap.sh b/tests/bsim/bluetooth/host/l2cap/general/tests_scripts/l2cap.sh index adfae72c459..3784ccfa1e0 100755 --- a/tests/bsim/bluetooth/host/l2cap/general/tests_scripts/l2cap.sh +++ b/tests/bsim/bluetooth/host/l2cap/general/tests_scripts/l2cap.sh @@ -11,10 +11,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_general_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_general_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -rs=43 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_general_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_general_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -rs=42 Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/l2cap/send_on_connect/tests_scripts/l2cap.sh b/tests/bsim/bluetooth/host/l2cap/send_on_connect/tests_scripts/l2cap.sh index d6e3f60d391..32c5eebda06 100755 --- a/tests/bsim/bluetooth/host/l2cap/send_on_connect/tests_scripts/l2cap.sh +++ b/tests/bsim/bluetooth/host/l2cap/send_on_connect/tests_scripts/l2cap.sh @@ -10,10 +10,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_send_on_connect_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_send_on_connect_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_send_on_connect_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_send_on_connect_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ @@ -25,10 +25,10 @@ simulation_id="l2cap_send_on_connect_ecred" cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_send_on_connect_prj_ecred_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_send_on_connect_prj_ecred_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_send_on_connect_prj_ecred_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_send_on_connect_prj_ecred_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/l2cap/split/test_scripts/l2cap_split.sh b/tests/bsim/bluetooth/host/l2cap/split/test_scripts/l2cap_split.sh index 8c26c0e4bd8..fe3c3495025 100755 --- a/tests/bsim/bluetooth/host/l2cap/split/test_scripts/l2cap_split.sh +++ b/tests/bsim/bluetooth/host/l2cap/split/test_scripts/l2cap_split.sh @@ -4,8 +4,8 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -dut_exe="bs_${BOARD}_$(guess_test_long_name)_dut_prj_conf" -tester_exe="bs_${BOARD}_$(guess_test_long_name)_tester_prj_conf" +dut_exe="bs_${BOARD_TS}_$(guess_test_long_name)_dut_prj_conf" +tester_exe="bs_${BOARD_TS}_$(guess_test_long_name)_tester_prj_conf" simulation_id="l2cap_split" verbosity_level=2 diff --git a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh index 9d2a760a6d0..975a5abd232 100755 --- a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh +++ b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap.sh @@ -9,7 +9,7 @@ simulation_id="l2cap_stress" verbosity_level=2 EXECUTE_TIMEOUT=240 -bsim_exe=./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_stress_prj_conf +bsim_exe=./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_stress_prj_conf cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh index c71363d834b..b6e24b06780 100755 --- a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh +++ b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/l2cap_syswq.sh @@ -9,7 +9,7 @@ simulation_id="l2cap_stress_syswq" verbosity_level=2 EXECUTE_TIMEOUT=240 -bsim_exe=./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_stress_prj_syswq_conf +bsim_exe=./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_stress_prj_syswq_conf cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/l2cap.sh b/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/l2cap.sh index 6700f12781b..a8cbad81d9d 100755 --- a/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/l2cap.sh +++ b/tests/bsim/bluetooth/host/l2cap/userdata/tests_scripts/l2cap.sh @@ -10,10 +10,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_userdata_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_userdata_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_l2cap_userdata_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_l2cap_userdata_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/misc/disable/tests_scripts/disable.sh b/tests/bsim/bluetooth/host/misc/disable/tests_scripts/disable.sh index 8fb3bfa648e..0be9af35e7a 100755 --- a/tests/bsim/bluetooth/host/misc/disable/tests_scripts/disable.sh +++ b/tests/bsim/bluetooth/host/misc/disable/tests_scripts/disable.sh @@ -11,7 +11,7 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_misc_disable_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_misc_disable_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=disable Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/misc/disable/tests_scripts/disable_with_gatt.sh b/tests/bsim/bluetooth/host/misc/disable/tests_scripts/disable_with_gatt.sh index 5c3d8916c6b..f81a8fe6e4d 100755 --- a/tests/bsim/bluetooth/host/misc/disable/tests_scripts/disable_with_gatt.sh +++ b/tests/bsim/bluetooth/host/misc/disable/tests_scripts/disable_with_gatt.sh @@ -14,10 +14,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_misc_disable_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_misc_disable_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=gatt_client -Execute ./bs_${BOARD}_tests_bsim_bluetooth_host_misc_disable_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_misc_disable_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=gatt_server Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/disconnect.sh b/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/disconnect.sh index 438dfdf5f27..ada291fa88a 100755 --- a/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/disconnect.sh +++ b/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/disconnect.sh @@ -4,8 +4,8 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source -dut_exe="bs_${BOARD}_$(guess_test_long_name)_dut_prj_conf" -tester_exe="bs_${BOARD}_$(guess_test_long_name)_tester_prj_conf" +dut_exe="bs_${BOARD_TS}_$(guess_test_long_name)_dut_prj_conf" +tester_exe="bs_${BOARD_TS}_$(guess_test_long_name)_tester_prj_conf" simulation_id="misc_disconnect" verbosity_level=2 diff --git a/tests/bsim/bluetooth/host/misc/hfc/test_scripts/run.sh b/tests/bsim/bluetooth/host/misc/hfc/test_scripts/run.sh index f043d3f33b5..fd1a534e5dc 100755 --- a/tests/bsim/bluetooth/host/misc/hfc/test_scripts/run.sh +++ b/tests/bsim/bluetooth/host/misc/hfc/test_scripts/run.sh @@ -10,7 +10,7 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -bsim_exe=./bs_${BOARD}_tests_bsim_bluetooth_host_misc_hfc_prj_conf +bsim_exe=./bs_${BOARD_TS}_tests_bsim_bluetooth_host_misc_hfc_prj_conf Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=dut -rs=420 Execute "${bsim_exe}" -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peer -rs=69 diff --git a/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/unregister_conn_cb.sh b/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/unregister_conn_cb.sh index 8bfb9aebf87..ad2b4dc0bb5 100755 --- a/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/unregister_conn_cb.sh +++ b/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/unregister_conn_cb.sh @@ -13,7 +13,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="unregister_conn_cb" verbosity_level=2 -bsim_exe=./bs_${BOARD}_tests_bsim_bluetooth_host_misc_unregister_conn_cb_prj_conf +bsim_exe=./bs_${BOARD_TS}_tests_bsim_bluetooth_host_misc_unregister_conn_cb_prj_conf cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh index d61b0e0d0bb..766df63d256 100755 --- a/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/privacy/central/test_scripts/run_test.sh @@ -8,7 +8,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id="$(guess_test_long_name)" -central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/privacy/device/test_scripts/run_tests.sh b/tests/bsim/bluetooth/host/privacy/device/test_scripts/run_tests.sh index 131f857396c..87b97841b15 100755 --- a/tests/bsim/bluetooth/host/privacy/device/test_scripts/run_tests.sh +++ b/tests/bsim/bluetooth/host/privacy/device/test_scripts/run_tests.sh @@ -8,7 +8,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id="$(guess_test_long_name)" -test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/run_test.sh index 95acccc613d..2e83ef3857a 100755 --- a/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/run_test.sh @@ -8,7 +8,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id="$(guess_test_long_name)" -central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh index eda6a285b8a..6564e615e0e 100755 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test.sh @@ -8,7 +8,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source verbosity_level=2 simulation_id="host_privacy_peripheral" -central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh index 8d8fa763571..adbbf293250 100755 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_expired.sh @@ -9,7 +9,7 @@ verbosity_level=2 simulation_id="rpa_expired" central_exe_rpa_expired="\ -${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_rpa_expired_conf" +${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_rpa_expired_conf" peripheral_exe_rpa_expired="${central_exe_rpa_expired}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh index d927177e4fa..97389f1e129 100755 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/run_test_rpa_sharing.sh @@ -9,7 +9,7 @@ verbosity_level=2 simulation_id="$(guess_test_long_name)_rpa_sharing" central_exe_rpa_sharing="\ -${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_rpa_sharing_conf" +${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_rpa_sharing_conf" peripheral_exe_rpa_sharing="${central_exe_rpa_sharing}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/run_test.sh index c77a4bfd7d8..1c84dda23ae 100755 --- a/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/run_test.sh @@ -8,7 +8,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="security_bond_overwrite_allowed" verbosity_level=2 -central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/run_test.sh index 20f67117927..ea61a870aa2 100755 --- a/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/run_test.sh @@ -8,7 +8,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="security_bond_overwrite_denied" verbosity_level=2 -central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/run_test.sh index c2a765b487c..d7c87b399c0 100755 --- a/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/run_test.sh @@ -9,7 +9,7 @@ verbosity_level=2 simulation_id="security_bond_per_connection" -central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_$(guess_test_long_name)_prj_conf" +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_prj_conf" peripheral_exe="${central_exe}" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update.sh b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update.sh index 17432a38a7e..d577ad974ef 100755 --- a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update.sh +++ b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update.sh @@ -5,7 +5,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source test_name='ccc_update' -test_exe="bs_${BOARD}_tests_bsim_bluetooth_host_security_${test_name}_prj_conf" +test_exe="bs_${BOARD_TS}_tests_bsim_bluetooth_host_security_${test_name}_prj_conf" simulation_id="${test_name}" verbosity_level=2 diff --git a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_2.sh b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_2.sh index c267186e9b4..49a27c4524e 100755 --- a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_2.sh +++ b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_2.sh @@ -5,7 +5,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source test_name='ccc_update' -test_exe="bs_${BOARD}_tests_bsim_bluetooth_host_security_${test_name}_prj_2_conf" +test_exe="bs_${BOARD_TS}_tests_bsim_bluetooth_host_security_${test_name}_prj_2_conf" simulation_id="${test_name}_2" verbosity_level=2 diff --git a/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/run_test.sh index 2b79511a307..3ff3d35db0e 100755 --- a/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/run_test.sh +++ b/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/run_test.sh @@ -9,8 +9,8 @@ verbosity_level=2 simulation_id="id_addr_update" test_path="$(guess_test_long_name)" -central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_${test_path}_central_prj_conf" -peripheral_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD}_${test_path}_peripheral_prj_conf" +central_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_${test_path}_central_prj_conf" +peripheral_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_${test_path}_peripheral_prj_conf" cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/security_changed_callback.sh b/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/security_changed_callback.sh index 492e8249dab..5abb7bef444 100755 --- a/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/security_changed_callback.sh +++ b/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/security_changed_callback.sh @@ -5,7 +5,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source test_name='security_changed_callback' -test_exe="bs_${BOARD}_tests_bsim_bluetooth_host_security_${test_name}_prj_conf" +test_exe="bs_${BOARD_TS}_tests_bsim_bluetooth_host_security_${test_name}_prj_conf" simulation_id="${test_name}" verbosity_level=2 diff --git a/tests/bsim/bluetooth/ll/advx/tests_scripts/basic_advx.sh b/tests/bsim/bluetooth/ll/advx/tests_scripts/basic_advx.sh index 0fc0a93a112..540611f69a3 100755 --- a/tests/bsim/bluetooth/ll/advx/tests_scripts/basic_advx.sh +++ b/tests/bsim/bluetooth/ll/advx/tests_scripts/basic_advx.sh @@ -12,10 +12,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_advx_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_advx_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=advx -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_advx_prj_conf\ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_advx_prj_conf\ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=scanx Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/advx/tests_scripts/basic_advx_ticker_expire_info.sh b/tests/bsim/bluetooth/ll/advx/tests_scripts/basic_advx_ticker_expire_info.sh index 8da82c7cea2..cabee84f015 100755 --- a/tests/bsim/bluetooth/ll/advx/tests_scripts/basic_advx_ticker_expire_info.sh +++ b/tests/bsim/bluetooth/ll/advx/tests_scripts/basic_advx_ticker_expire_info.sh @@ -12,10 +12,10 @@ EXECUTE_TIMEOUT=120 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_advx_prj_conf_overlay-ticker_expire_info_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_advx_prj_conf_overlay-ticker_expire_info_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=advx -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_advx_prj_conf_overlay-ticker_expire_info_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_advx_prj_conf_overlay-ticker_expire_info_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=scanx Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh index 7ee43972aa2..762648523a7 100755 --- a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh +++ b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh @@ -12,10 +12,10 @@ EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_bis_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=receive -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_bis_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=broadcast Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_ticker_expire_info.sh b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_ticker_expire_info.sh index 4d4c5c54441..463676cde89 100755 --- a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_ticker_expire_info.sh +++ b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_ticker_expire_info.sh @@ -12,10 +12,10 @@ EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_bis_prj_conf_overlay-ticker_expire_info_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf_overlay-ticker_expire_info_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=receive -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_bis_prj_conf_overlay-ticker_expire_info_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf_overlay-ticker_expire_info_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=broadcast Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh index 77adc207684..b575efeed6c 100755 --- a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh +++ b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh @@ -12,10 +12,10 @@ EXECUTE_TIMEOUT=30 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_bis_prj_vs_dp_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_vs_dp_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=receive_vs_dp -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_bis_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=broadcast Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso.sh b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso.sh index f21cd80b9ab..fe8e1185608 100755 --- a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso.sh +++ b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso.sh @@ -12,34 +12,34 @@ EXECUTE_TIMEOUT=200 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ -v=${verbosity_level} -s=${simulation_id} -d=2 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ -v=${verbosity_level} -s=${simulation_id} -d=3 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ -v=${verbosity_level} -s=${simulation_id} -d=4 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ -v=${verbosity_level} -s=${simulation_id} -d=5 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ -v=${verbosity_level} -s=${simulation_id} -d=6 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ -v=${verbosity_level} -s=${simulation_id} -d=7 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ -v=${verbosity_level} -s=${simulation_id} -d=8 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay_conf \ -v=${verbosity_level} -s=${simulation_id} -d=9 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first.sh b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first.sh index 7c015e67d57..36e1396f253 100755 --- a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first.sh +++ b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first.sh @@ -12,34 +12,34 @@ EXECUTE_TIMEOUT=200 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=2 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=3 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=4 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=5 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=6 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=7 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=8 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=9 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_cen_skip_2_se.sh b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_cen_skip_2_se.sh index bb08f582574..cc7f7291ac9 100755 --- a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_cen_skip_2_se.sh +++ b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_cen_skip_2_se.sh @@ -12,10 +12,12 @@ EXECUTE_TIMEOUT=60 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_cen_skip_2_se_conf \ +Execute \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_cen_skip_2_se_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_cen_skip_2_se_conf \ +Execute \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_cen_skip_2_se_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_cen_skip_4_se.sh b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_cen_skip_4_se.sh index f75790e3fcf..8e135197433 100755 --- a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_cen_skip_4_se.sh +++ b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_cen_skip_4_se.sh @@ -12,10 +12,12 @@ EXECUTE_TIMEOUT=60 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_cen_skip_4_se_conf \ +Execute \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_cen_skip_4_se_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_cen_skip_4_se_conf \ +Execute \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_cen_skip_4_se_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_per_skip_2_se.sh b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_per_skip_2_se.sh index 84d3c5c4ed3..a190e954641 100755 --- a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_per_skip_2_se.sh +++ b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_per_skip_2_se.sh @@ -12,10 +12,12 @@ EXECUTE_TIMEOUT=60 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_per_skip_2_se_conf \ +Execute \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_per_skip_2_se_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_per_skip_2_se_conf \ +Execute \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_per_skip_2_se_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_per_skip_4_se.sh b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_per_skip_4_se.sh index 8fd00d9a057..16defd80181 100755 --- a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_per_skip_4_se.sh +++ b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_first_ft_per_skip_4_se.sh @@ -12,10 +12,12 @@ EXECUTE_TIMEOUT=60 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_per_skip_4_se_conf \ +Execute \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_per_skip_4_se_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_per_skip_4_se_conf \ +Execute \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_first_ft_per_skip_4_se_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_group.sh b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_group.sh index 8dba9ea15db..1671bdaf3d1 100755 --- a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_group.sh +++ b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_group.sh @@ -12,19 +12,19 @@ EXECUTE_TIMEOUT=200 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_conf \ -v=${verbosity_level} -s=${simulation_id} -d=2 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_conf \ -v=${verbosity_level} -s=${simulation_id} -d=3 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_conf \ -v=${verbosity_level} -s=${simulation_id} -d=4 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_group_acl_first.sh b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_group_acl_first.sh index 85e018ce71e..75c3a7d9b58 100755 --- a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_group_acl_first.sh +++ b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_acl_group_acl_first.sh @@ -12,19 +12,19 @@ EXECUTE_TIMEOUT=200 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=2 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=3 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-acl_group_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=4 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_legacy_adv.sh b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_legacy_adv.sh index df295ec646c..5574a0cbecf 100755 --- a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_legacy_adv.sh +++ b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_legacy_adv.sh @@ -12,34 +12,34 @@ EXECUTE_TIMEOUT=200 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ -v=${verbosity_level} -s=${simulation_id} -d=2 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ -v=${verbosity_level} -s=${simulation_id} -d=3 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ -v=${verbosity_level} -s=${simulation_id} -d=4 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ -v=${verbosity_level} -s=${simulation_id} -d=5 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ -v=${verbosity_level} -s=${simulation_id} -d=6 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ -v=${verbosity_level} -s=${simulation_id} -d=7 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ -v=${verbosity_level} -s=${simulation_id} -d=8 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_conf \ -v=${verbosity_level} -s=${simulation_id} -d=9 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_legacy_adv_acl_first.sh b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_legacy_adv_acl_first.sh index 998ef520988..1798969f72e 100755 --- a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_legacy_adv_acl_first.sh +++ b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_legacy_adv_acl_first.sh @@ -12,34 +12,34 @@ EXECUTE_TIMEOUT=200 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=2 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=3 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=4 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=5 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=6 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=7 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=8 -testid=peripheral -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-legacy_adv_acl_first_conf \ -v=${verbosity_level} -s=${simulation_id} -d=9 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_peripheral_cis.sh b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_peripheral_cis.sh index 94c89bcf01d..ab1e5c72392 100755 --- a/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_peripheral_cis.sh +++ b/tests/bsim/bluetooth/ll/cis/tests_scripts/connected_iso_peripheral_cis.sh @@ -11,10 +11,10 @@ EXECUTE_TIMEOUT=100 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-peripheral_cis_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-peripheral_cis_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-peripheral_cis_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_cis_prj_conf_overlay-peripheral_cis_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn20_split.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn20_split.sh index 17bd4ed9205..4523f9846ce 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn20_split.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn20_split.sh @@ -11,11 +11,11 @@ EXECUTE_TIMEOUT=60 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -testid=peripheral_repeat20 -rs=23 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_conf\ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_conf\ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -testid=central_repeat20 -rs=6 diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split.sh index 150b2fd2960..7d4e5946441 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split.sh @@ -12,11 +12,11 @@ EXECUTE_TIMEOUT=5 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=1 \ -testid=peripheral -rs=23 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=1 \ -testid=central_encrypted -rs=6 diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_privacy.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_privacy.sh index 53293f0bb12..f3a898e1739 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_privacy.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_privacy.sh @@ -13,12 +13,12 @@ EXECUTE_TIMEOUT=5 cd ${BSIM_OUT_PATH}/bin Execute \ - ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_privacy_conf \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_privacy_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=1 \ -testid=peripheral -rs=23 Execute \ - ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_privacy_conf \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_privacy_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=1 \ -testid=central_encrypted -rs=6 diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_single_timer.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_single_timer.sh index 2c81b2f3838..683aad85b6d 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_single_timer.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_single_timer.sh @@ -12,11 +12,11 @@ EXECUTE_TIMEOUT=5 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_single_timer_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_single_timer_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=1 \ -testid=peripheral -rs=23 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_single_timer_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_single_timer_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=1 \ -testid=central_encrypted -rs=6 diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split.sh index 621ab1d3720..1946b388afb 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split.sh @@ -12,11 +12,11 @@ EXECUTE_TIMEOUT=5 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -testid=peripheral -rs=23 -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_conf\ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_conf\ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -testid=central -rs=6 diff --git a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split_low_lat.sh b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split_low_lat.sh index 4e7f993c456..9c21fc4d922 100755 --- a/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split_low_lat.sh +++ b/tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_split_low_lat.sh @@ -13,12 +13,12 @@ EXECUTE_TIMEOUT=5 cd ${BSIM_OUT_PATH}/bin Execute \ - ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_low_lat_conf \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_low_lat_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=0 \ -testid=peripheral -rs=23 Execute \ - ./bs_${BOARD}_tests_bsim_bluetooth_ll_conn_prj_split_low_lat_conf \ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_conn_prj_split_low_lat_conf \ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=0 \ -testid=central -rs=6 diff --git a/tests/bsim/bluetooth/ll/edtt/tests_scripts/_controller_tests_inner.sh b/tests/bsim/bluetooth/ll/edtt/tests_scripts/_controller_tests_inner.sh index e75f6ffbe35..52f04e2e6e3 100755 --- a/tests/bsim/bluetooth/ll/edtt/tests_scripts/_controller_tests_inner.sh +++ b/tests/bsim/bluetooth/ll/edtt/tests_scripts/_controller_tests_inner.sh @@ -95,11 +95,11 @@ _Execute ./src/edttool.py -s=${SIMULATION_ID} -d=2 --transport bsim \ cd ${BSIM_OUT_PATH}/bin _Execute \ - ${RR_ARGS_1} ./bs_${BOARD}_tests_bsim_bluetooth_ll_edtt_hci_test_app_${PRJ_CONF_1}\ + ${RR_ARGS_1} ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_edtt_hci_test_app_${PRJ_CONF_1}\ -s=${SIMULATION_ID} -d=0 -v=${VERBOSITY_LEVEL_DEV1} -RealEncryption=1 _Execute \ - ${RR_ARGS_2} ./bs_${BOARD}_tests_bsim_bluetooth_ll_edtt_hci_test_app_${PRJ_CONF_2}\ + ${RR_ARGS_2} ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_edtt_hci_test_app_${PRJ_CONF_2}\ -s=${SIMULATION_ID} -d=1 -v=${VERBOSITY_LEVEL_DEV2} -RealEncryption=1 _Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL_PHY} -s=${SIMULATION_ID} \ diff --git a/tests/bsim/bluetooth/ll/edtt/tests_scripts/gatt.llcp.sh b/tests/bsim/bluetooth/ll/edtt/tests_scripts/gatt.llcp.sh index d16b743435d..a814b505814 100755 --- a/tests/bsim/bluetooth/ll/edtt/tests_scripts/gatt.llcp.sh +++ b/tests/bsim/bluetooth/ll/edtt/tests_scripts/gatt.llcp.sh @@ -22,11 +22,11 @@ Execute ./src/edttool.py -s=${SIMULATION_ID} -d=0 --transport bsim \ cd ${BSIM_OUT_PATH}/bin Execute \ - ./bs_${BOARD}_tests_bsim_bluetooth_ll_edtt_hci_test_app_prj_tst_llcp_conf\ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_edtt_hci_test_app_prj_tst_llcp_conf\ -s=${SIMULATION_ID} -d=1 -v=${VERBOSITY_LEVEL} -RealEncryption=1 Execute \ - ./bs_${BOARD}_tests_bsim_bluetooth_ll_edtt_gatt_test_app_prj_llcp_conf\ + ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_edtt_gatt_test_app_prj_llcp_conf\ -s=${SIMULATION_ID} -d=2 -v=${VERBOSITY_LEVEL} -RealEncryption=1 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \ diff --git a/tests/bsim/bluetooth/ll/multiple_id/tests_scripts/multiple.sh b/tests/bsim/bluetooth/ll/multiple_id/tests_scripts/multiple.sh index cfbac8c313f..91b93f0c8d1 100755 --- a/tests/bsim/bluetooth/ll/multiple_id/tests_scripts/multiple.sh +++ b/tests/bsim/bluetooth/ll/multiple_id/tests_scripts/multiple.sh @@ -11,10 +11,10 @@ EXECUTE_TIMEOUT=1800 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_multiple_id_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_multiple_id_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_multiple_id_prj_conf\ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_multiple_id_prj_conf\ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh b/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh index 64a3dabac3b..ff79071857f 100755 --- a/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh +++ b/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh @@ -10,10 +10,10 @@ EXECUTE_TIMEOUT=60 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_throughput_prj_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_throughput_prj_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central -Execute ./bs_${BOARD}_tests_bsim_bluetooth_ll_throughput_prj_conf\ +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_throughput_prj_conf\ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/bluetooth/mesh/_mesh_test.sh b/tests/bsim/bluetooth/mesh/_mesh_test.sh index 5df01a1bf78..fac62d335be 100755 --- a/tests/bsim/bluetooth/mesh/_mesh_test.sh +++ b/tests/bsim/bluetooth/mesh/_mesh_test.sh @@ -60,9 +60,9 @@ function RunTest(){ conf=${conf:-prj_conf} if [ ${overlay} ]; then - exe_name=./bs_${BOARD}_tests_bsim_bluetooth_mesh_${conf}_${overlay} + exe_name=./bs_${BOARD_TS}_tests_bsim_bluetooth_mesh_${conf}_${overlay} else - exe_name=./bs_${BOARD}_tests_bsim_bluetooth_mesh_${conf} + exe_name=./bs_${BOARD_TS}_tests_bsim_bluetooth_mesh_${conf} fi Execute \ diff --git a/tests/bsim/net/sockets/echo_test/tests_scripts/echo_test_802154.sh b/tests/bsim/net/sockets/echo_test/tests_scripts/echo_test_802154.sh index 0adb4cc27e7..713f6884268 100755 --- a/tests/bsim/net/sockets/echo_test/tests_scripts/echo_test_802154.sh +++ b/tests/bsim/net/sockets/echo_test/tests_scripts/echo_test_802154.sh @@ -17,11 +17,11 @@ EXECUTE_TIMEOUT=100 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_net_sockets_echo_test_prj_conf_overlay-802154_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_net_sockets_echo_test_prj_conf_overlay-802154_conf \ -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=1 \ -testid=echo_client -Execute ./bs_${BOARD}_samples_net_sockets_echo_server_prj_conf_overlay-802154_conf\ +Execute ./bs_${BOARD_TS}_samples_net_sockets_echo_server_prj_conf_overlay-802154_conf\ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=1 \ Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ diff --git a/tests/bsim/net/sockets/echo_test/tests_scripts/echo_test_ot.sh b/tests/bsim/net/sockets/echo_test/tests_scripts/echo_test_ot.sh index 56a364528a5..66f4cbf2942 100755 --- a/tests/bsim/net/sockets/echo_test/tests_scripts/echo_test_ot.sh +++ b/tests/bsim/net/sockets/echo_test/tests_scripts/echo_test_ot.sh @@ -17,11 +17,11 @@ EXECUTE_TIMEOUT=100 cd ${BSIM_OUT_PATH}/bin -Execute ./bs_${BOARD}_tests_bsim_net_sockets_echo_test_prj_conf_overlay-ot_conf \ +Execute ./bs_${BOARD_TS}_tests_bsim_net_sockets_echo_test_prj_conf_overlay-ot_conf \ -v=${verbosity_level} -s=${simulation_id} -start_offset=2e6 -d=0 -RealEncryption=1 \ -testid=echo_client -Execute ./bs_${BOARD}_samples_net_sockets_echo_server_prj_conf_overlay-ot_conf\ +Execute ./bs_${BOARD_TS}_samples_net_sockets_echo_server_prj_conf_overlay-ot_conf\ -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=1 \ Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ From 13206221b0d96026327f19e02fca429646761cce Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 20 Mar 2024 14:40:33 +0100 Subject: [PATCH 1304/2402] tests/bsim: build scripts: Use hwmv2 board names Use the hwmv2 board names instead of the hwmv1 ones. Signed-off-by: Alberto Escolar Piedras --- tests/bsim/bluetooth/audio_samples/compile.sh | 2 +- tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh | 2 +- tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/bsim/bluetooth/audio_samples/compile.sh b/tests/bsim/bluetooth/audio_samples/compile.sh index a54aace2777..fa6f232c497 100755 --- a/tests/bsim/bluetooth/audio_samples/compile.sh +++ b/tests/bsim/bluetooth/audio_samples/compile.sh @@ -19,7 +19,7 @@ mkdir -p ${WORK_DIR} source ${ZEPHYR_BASE}/tests/bsim/compile.source -if [ "${BOARD}" == "nrf5340bsim_nrf5340_cpuapp" ]; then +if [ "${BOARD_TS}" == "nrf5340bsim_nrf5340_cpuapp" ]; then app=samples/bluetooth/unicast_audio_server sysbuild=1 compile app=samples/bluetooth/broadcast_audio_source sysbuild=1 compile app=tests/bsim/bluetooth/audio_samples/unicast_audio_client sysbuild=1 compile diff --git a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh index 65769185867..6e1dea448d6 100755 --- a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh +++ b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh @@ -13,7 +13,7 @@ set -ue WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" -BOARD="${BOARD:-nrf5340bsim_nrf5340_cpuapp}" +export BOARD="${BOARD:-nrf5340bsim/nrf5340/cpuapp}" mkdir -p ${WORK_DIR} diff --git a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh index e8d78683b2e..a0092fe5ea0 100755 --- a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh +++ b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh @@ -13,6 +13,7 @@ set -ue WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" +export BOARD="${BOARD:-nrf5340bsim/nrf5340/cpunet}" mkdir -p ${WORK_DIR} From 13e31b27362b6de90c12e65a758580374cb54ac2 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 21 Mar 2024 15:07:17 +0100 Subject: [PATCH 1305/2402] tests/bsim/compile.source: Provide common check and default Provide a common check for BSIM_COMPONENTS_PATH and a default WORK_DIR So we avoid boilerplate in other scripts Signed-off-by: Alberto Escolar Piedras --- tests/bsim/compile.source | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/bsim/compile.source b/tests/bsim/compile.source index aadb6edd880..515e9cc693d 100644 --- a/tests/bsim/compile.source +++ b/tests/bsim/compile.source @@ -3,6 +3,10 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source +: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" + +WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" + function print_error_info(){ echo -e "\033[0;31mFailure building ${app} ${conf_file} for ${BOARD}\033[0m\n\ You can rebuild it with\n\ From a5f255d6040a5672f2f766b383074645ec2e848b Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 21 Mar 2024 15:12:13 +0100 Subject: [PATCH 1306/2402] tests/bsim sh scripts: Reduce boilerplate Remove the boilerplate which is not necessary beacuse it is already provided by the common scripts Signed-off-by: Alberto Escolar Piedras --- tests/bsim/bluetooth/audio/compile.sh | 13 +------------ tests/bsim/bluetooth/audio_samples/compile.sh | 10 +--------- .../bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh | 9 +-------- .../bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh | 9 +-------- tests/bsim/bluetooth/compile.sh | 10 +--------- tests/bsim/bluetooth/hci_uart/compile.sh | 10 +--------- tests/bsim/bluetooth/host/adv/compile.sh | 11 +---------- .../css_sample_data/test_scripts/_compile.sh | 1 - .../host/adv/resume/test_scripts/_compile.sh | 2 -- tests/bsim/bluetooth/host/att/compile.sh | 11 +---------- .../host/att/long_read/test_scripts/_build.sh | 2 -- .../host/att/mtu_update/test_scripts/_compile.sh | 1 - .../host/att/open_close/test_scripts/_build.sh | 1 - .../host/att/pipeline/test_scripts/_compile.sh | 2 -- .../host/att/read_fill_buf/test_scripts/_compile.sh | 2 -- .../att/retry_on_sec_err/test_scripts/_compile.sh | 2 -- .../host/att/sequential/test_scripts/_compile.sh | 2 -- tests/bsim/bluetooth/host/compile.sh | 10 +--------- .../host/gatt/ccc_store/test_scripts/_compile.sh | 2 -- tests/bsim/bluetooth/host/gatt/compile.sh | 11 +---------- .../host/gatt/sc_indicate/test_scripts/_compile.sh | 3 --- .../host/gatt/settings/test_scripts/_compile.sh | 2 -- .../host/id/settings/test_scripts/_compile.sh | 2 -- .../host/iso/cis/tests_scripts/_compile.sh | 2 -- tests/bsim/bluetooth/host/l2cap/compile.sh | 11 +---------- .../host/l2cap/credits/tests_scripts/_compile.sh | 2 -- .../credits_seg_recv/tests_scripts/_compile.sh | 2 -- .../host/l2cap/frags/tests_scripts/_compile.sh | 2 -- .../host/l2cap/split/test_scripts/_compile.sh | 2 -- .../host/l2cap/stress/tests_scripts/_compile.sh | 2 -- .../host/misc/disconnect/test_scripts/_compile.sh | 3 +-- .../host/misc/hfc/test_scripts/_compile.sh | 3 +-- .../unregister_conn_cb/tests_scripts/_compile.sh | 3 +-- .../host/privacy/central/test_scripts/_compile.sh | 3 +-- .../host/privacy/device/test_scripts/_compile.sh | 4 +--- .../host/privacy/legacy/test_scripts/_compile.sh | 4 +--- .../privacy/peripheral/test_scripts/_compile.sh | 3 --- .../bond_overwrite_allowed/test_scripts/_compile.sh | 3 --- .../bond_overwrite_denied/test_scripts/_compile.sh | 3 +-- .../bond_per_connection/test_scripts/_compile.sh | 3 +-- .../security/ccc_update/test_scripts/_compile.sh | 2 -- tests/bsim/bluetooth/host/security/compile.sh | 11 +---------- .../id_addr_update/test_scripts/_compile.sh | 2 -- .../test_scripts/_compile.sh | 3 +-- tests/bsim/bluetooth/ll/cis/compile.sh | 10 +--------- tests/bsim/bluetooth/ll/compile.sh | 10 +--------- tests/bsim/bluetooth/mesh/compile.sh | 9 +-------- tests/bsim/compile.sh | 11 +---------- tests/bsim/drivers/uart/compile.sh | 11 +---------- tests/bsim/net/compile.sh | 11 +---------- 50 files changed, 27 insertions(+), 236 deletions(-) diff --git a/tests/bsim/bluetooth/audio/compile.sh b/tests/bsim/bluetooth/audio/compile.sh index ae714ec1145..f7bfa8f71b7 100755 --- a/tests/bsim/bluetooth/audio/compile.sh +++ b/tests/bsim/bluetooth/audio/compile.sh @@ -6,18 +6,7 @@ #set -x #uncomment this line for debugging set -ue - - - -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/audio_samples/compile.sh b/tests/bsim/bluetooth/audio_samples/compile.sh index fa6f232c497..e12dd326516 100755 --- a/tests/bsim/bluetooth/audio_samples/compile.sh +++ b/tests/bsim/bluetooth/audio_samples/compile.sh @@ -7,15 +7,7 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh index 6e1dea448d6..ea9afa930e5 100755 --- a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh +++ b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh @@ -6,17 +6,10 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" export BOARD="${BOARD:-nrf5340bsim/nrf5340/cpuapp}" -mkdir -p ${WORK_DIR} - source ${ZEPHYR_BASE}/tests/bsim/compile.source app=tests/bsim/bluetooth/ll/conn conf_file=prj_split_privacy.conf sysbuild=1 compile diff --git a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh index a0092fe5ea0..dcb20010a1b 100755 --- a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh +++ b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh @@ -6,17 +6,10 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" export BOARD="${BOARD:-nrf5340bsim/nrf5340/cpunet}" -mkdir -p ${WORK_DIR} - source ${ZEPHYR_BASE}/tests/bsim/sh_common.source ${ZEPHYR_BASE}/tests/bsim/bluetooth/ll/compile.sh diff --git a/tests/bsim/bluetooth/compile.sh b/tests/bsim/bluetooth/compile.sh index c0e3d813d72..84a4f8c981a 100755 --- a/tests/bsim/bluetooth/compile.sh +++ b/tests/bsim/bluetooth/compile.sh @@ -6,15 +6,7 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/bluetooth/hci_uart/compile.sh b/tests/bsim/bluetooth/hci_uart/compile.sh index 60eb464867a..e617ca0d309 100755 --- a/tests/bsim/bluetooth/hci_uart/compile.sh +++ b/tests/bsim/bluetooth/hci_uart/compile.sh @@ -6,15 +6,7 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/adv/compile.sh b/tests/bsim/bluetooth/host/adv/compile.sh index 026b436f0cd..17acdbd3d0a 100755 --- a/tests/bsim/bluetooth/host/adv/compile.sh +++ b/tests/bsim/bluetooth/host/adv/compile.sh @@ -6,16 +6,7 @@ #set -x #uncomment this line for debugging set -ue - -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh index af200055c53..de926e8b267 100755 --- a/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/test_scripts/_compile.sh @@ -6,7 +6,6 @@ set -eu : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/adv/resume/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/adv/resume/test_scripts/_compile.sh index 7fad3e25a89..baa42cdb7a6 100755 --- a/tests/bsim/bluetooth/host/adv/resume/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/adv/resume/test_scripts/_compile.sh @@ -3,10 +3,8 @@ # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/att/compile.sh b/tests/bsim/bluetooth/host/att/compile.sh index 8361a9e8644..b3da250ba1b 100755 --- a/tests/bsim/bluetooth/host/att/compile.sh +++ b/tests/bsim/bluetooth/host/att/compile.sh @@ -6,16 +6,7 @@ #set -x #uncomment this line for debugging set -ue - -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/att/long_read/test_scripts/_build.sh b/tests/bsim/bluetooth/host/att/long_read/test_scripts/_build.sh index af200055c53..718910a63c4 100755 --- a/tests/bsim/bluetooth/host/att/long_read/test_scripts/_build.sh +++ b/tests/bsim/bluetooth/host/att/long_read/test_scripts/_build.sh @@ -3,10 +3,8 @@ # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_compile.sh index ca1f96b562c..42740d4bfc9 100755 --- a/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/att/mtu_update/test_scripts/_compile.sh @@ -5,7 +5,6 @@ set -eu : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/att/open_close/test_scripts/_build.sh b/tests/bsim/bluetooth/host/att/open_close/test_scripts/_build.sh index af200055c53..de926e8b267 100755 --- a/tests/bsim/bluetooth/host/att/open_close/test_scripts/_build.sh +++ b/tests/bsim/bluetooth/host/att/open_close/test_scripts/_build.sh @@ -6,7 +6,6 @@ set -eu : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/att/pipeline/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/pipeline/test_scripts/_compile.sh index 3579ab2e772..ff0f485b17d 100755 --- a/tests/bsim/bluetooth/host/att/pipeline/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/att/pipeline/test_scripts/_compile.sh @@ -2,10 +2,8 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_compile.sh index 1fa38a6d27f..6c80f22923a 100755 --- a/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/att/read_fill_buf/test_scripts/_compile.sh @@ -1,11 +1,9 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_compile.sh index 1fa38a6d27f..6c80f22923a 100755 --- a/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/att/retry_on_sec_err/test_scripts/_compile.sh @@ -1,11 +1,9 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/att/sequential/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/att/sequential/test_scripts/_compile.sh index 3579ab2e772..ff0f485b17d 100755 --- a/tests/bsim/bluetooth/host/att/sequential/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/att/sequential/test_scripts/_compile.sh @@ -2,10 +2,8 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/compile.sh b/tests/bsim/bluetooth/host/compile.sh index f2a61050216..de3fd1cd940 100755 --- a/tests/bsim/bluetooth/host/compile.sh +++ b/tests/bsim/bluetooth/host/compile.sh @@ -7,15 +7,7 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_compile.sh index ac5eb694236..cb72bfca81c 100755 --- a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/_compile.sh @@ -2,10 +2,8 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/gatt/compile.sh b/tests/bsim/bluetooth/host/gatt/compile.sh index 21ca39f3d99..3fc026e67cc 100755 --- a/tests/bsim/bluetooth/host/gatt/compile.sh +++ b/tests/bsim/bluetooth/host/gatt/compile.sh @@ -6,16 +6,7 @@ #set -x #uncomment this line for debugging set -ue - -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/_compile.sh index b45cd9fb77d..80030a894f2 100755 --- a/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/gatt/sc_indicate/test_scripts/_compile.sh @@ -2,14 +2,11 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source app="$(guess_test_relpath)" compile - wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_compile.sh index ac5eb694236..cb72bfca81c 100755 --- a/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/gatt/settings/test_scripts/_compile.sh @@ -2,10 +2,8 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh index af200055c53..718910a63c4 100755 --- a/tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/id/settings/test_scripts/_compile.sh @@ -3,10 +3,8 @@ # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/iso/cis/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/iso/cis/tests_scripts/_compile.sh index 4fa833c38ac..e717a4b2bbe 100755 --- a/tests/bsim/bluetooth/host/iso/cis/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/iso/cis/tests_scripts/_compile.sh @@ -2,10 +2,8 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/l2cap/compile.sh b/tests/bsim/bluetooth/host/l2cap/compile.sh index c86527f00e1..b08686e12ab 100755 --- a/tests/bsim/bluetooth/host/l2cap/compile.sh +++ b/tests/bsim/bluetooth/host/l2cap/compile.sh @@ -6,16 +6,7 @@ #set -x #uncomment this line for debugging set -ue - -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/_compile.sh index 98c4d1bb18a..12c5b388261 100755 --- a/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/l2cap/credits/tests_scripts/_compile.sh @@ -2,10 +2,8 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/_compile.sh index 98c4d1bb18a..12c5b388261 100755 --- a/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/l2cap/credits_seg_recv/tests_scripts/_compile.sh @@ -2,10 +2,8 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/_compile.sh index 17b454f9d7c..80030a894f2 100755 --- a/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/l2cap/frags/tests_scripts/_compile.sh @@ -2,10 +2,8 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/l2cap/split/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/split/test_scripts/_compile.sh index 3579ab2e772..ff0f485b17d 100755 --- a/tests/bsim/bluetooth/host/l2cap/split/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/l2cap/split/test_scripts/_compile.sh @@ -2,10 +2,8 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/_compile.sh index 56cf572829e..a30326f1afc 100755 --- a/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/l2cap/stress/tests_scripts/_compile.sh @@ -2,10 +2,8 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/_compile.sh index fbdcdbacac2..ff0f485b17d 100755 --- a/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/misc/disconnect/test_scripts/_compile.sh @@ -2,12 +2,11 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source + app="$(guess_test_relpath)"/dut compile app="$(guess_test_relpath)"/tester compile diff --git a/tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh index 17b454f9d7c..e717a4b2bbe 100755 --- a/tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/misc/hfc/test_scripts/_compile.sh @@ -2,11 +2,10 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 + source ${ZEPHYR_BASE}/tests/bsim/compile.source app="$(guess_test_relpath)" compile diff --git a/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/_compile.sh b/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/_compile.sh index 17b454f9d7c..e717a4b2bbe 100755 --- a/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/misc/unregister_conn_cb/tests_scripts/_compile.sh @@ -2,11 +2,10 @@ # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 + source ${ZEPHYR_BASE}/tests/bsim/compile.source app="$(guess_test_relpath)" compile diff --git a/tests/bsim/bluetooth/host/privacy/central/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/central/test_scripts/_compile.sh index 2152b9cc57c..87cd4f6ba95 100755 --- a/tests/bsim/bluetooth/host/privacy/central/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/privacy/central/test_scripts/_compile.sh @@ -3,11 +3,10 @@ # SPDX-License-Identifier: Apache-2.0 set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 + source ${ZEPHYR_BASE}/tests/bsim/compile.source app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/privacy/device/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/device/test_scripts/_compile.sh index 2152b9cc57c..a8e0fb1530e 100755 --- a/tests/bsim/bluetooth/host/privacy/device/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/privacy/device/test_scripts/_compile.sh @@ -1,13 +1,11 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 + source ${ZEPHYR_BASE}/tests/bsim/compile.source app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_compile.sh index 2152b9cc57c..a8e0fb1530e 100755 --- a/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/privacy/legacy/test_scripts/_compile.sh @@ -1,13 +1,11 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 + source ${ZEPHYR_BASE}/tests/bsim/compile.source app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_compile.sh index 0f0ca567252..47da5e42c62 100755 --- a/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/privacy/peripheral/test_scripts/_compile.sh @@ -1,12 +1,9 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_compile.sh index ca70f8349ff..7bb547b3f25 100755 --- a/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/bond_overwrite_allowed/test_scripts/_compile.sh @@ -1,12 +1,9 @@ #!/usr/bin/env bash # Copyright 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu - : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_compile.sh index 5fb4d1a3db3..b3605e1ee2b 100755 --- a/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/bond_overwrite_denied/test_scripts/_compile.sh @@ -1,12 +1,11 @@ #!/usr/bin/env bash # Copyright 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source + app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_compile.sh index 4cdee31addb..a8e0fb1530e 100755 --- a/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/bond_per_connection/test_scripts/_compile.sh @@ -1,12 +1,11 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source + app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_compile.sh index 593ef45dfc1..e33fe48bdbe 100755 --- a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/_compile.sh @@ -1,11 +1,9 @@ #!/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/security/compile.sh b/tests/bsim/bluetooth/host/security/compile.sh index 4930a817616..9296cd8e4c1 100755 --- a/tests/bsim/bluetooth/host/security/compile.sh +++ b/tests/bsim/bluetooth/host/security/compile.sh @@ -6,16 +6,7 @@ #set -x #uncomment this line for debugging set -ue - -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_compile.sh index 00c33e102ce..f0f386a9e6b 100755 --- a/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/id_addr_update/test_scripts/_compile.sh @@ -1,11 +1,9 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/_compile.sh b/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/_compile.sh index 4cdee31addb..a8e0fb1530e 100755 --- a/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/_compile.sh +++ b/tests/bsim/bluetooth/host/security/security_changed_callback/test_scripts/_compile.sh @@ -1,12 +1,11 @@ #!/usr/bin/env bash # Copyright 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 - set -eu : "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" INCR_BUILD=1 source ${ZEPHYR_BASE}/tests/bsim/compile.source + app="$(guess_test_relpath)" _compile diff --git a/tests/bsim/bluetooth/ll/cis/compile.sh b/tests/bsim/bluetooth/ll/cis/compile.sh index 3db63a86c8b..b3b8379497c 100755 --- a/tests/bsim/bluetooth/ll/cis/compile.sh +++ b/tests/bsim/bluetooth/ll/cis/compile.sh @@ -6,15 +6,7 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/ll/compile.sh b/tests/bsim/bluetooth/ll/compile.sh index 89f4c7b55dd..487e34da4ab 100755 --- a/tests/bsim/bluetooth/ll/compile.sh +++ b/tests/bsim/bluetooth/ll/compile.sh @@ -6,15 +6,7 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" - -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/bluetooth/mesh/compile.sh b/tests/bsim/bluetooth/mesh/compile.sh index de112f96afc..aa86e6ccb25 100755 --- a/tests/bsim/bluetooth/mesh/compile.sh +++ b/tests/bsim/bluetooth/mesh/compile.sh @@ -6,14 +6,7 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source diff --git a/tests/bsim/compile.sh b/tests/bsim/compile.sh index 2b0e0a76a27..3b1a7dce635 100755 --- a/tests/bsim/compile.sh +++ b/tests/bsim/compile.sh @@ -7,16 +7,7 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" -BOARD="${BOARD:-nrf52_bsim}" -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/drivers/uart/compile.sh b/tests/bsim/drivers/uart/compile.sh index 5bd35772bb5..502916b20b9 100755 --- a/tests/bsim/drivers/uart/compile.sh +++ b/tests/bsim/drivers/uart/compile.sh @@ -7,16 +7,7 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" -BOARD="${BOARD:-nrf52_bsim}" -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/sh_common.source diff --git a/tests/bsim/net/compile.sh b/tests/bsim/net/compile.sh index e134d7ee5d6..a0338de4c6f 100755 --- a/tests/bsim/net/compile.sh +++ b/tests/bsim/net/compile.sh @@ -7,16 +7,7 @@ #set -x #uncomment this line for debugging set -ue -: "${BSIM_OUT_PATH:?BSIM_OUT_PATH must be defined}" -: "${BSIM_COMPONENTS_PATH:?BSIM_COMPONENTS_PATH must be defined}" -: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root\ - directory}" - -WORK_DIR="${WORK_DIR:-${ZEPHYR_BASE}/bsim_out}" -BOARD="${BOARD:-nrf52_bsim}" -BOARD_ROOT="${BOARD_ROOT:-${ZEPHYR_BASE}}" - -mkdir -p ${WORK_DIR} +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}" source ${ZEPHYR_BASE}/tests/bsim/compile.source From 5ab2635b0701a6c4d9ca2dcef68dba88a5c42e84 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Thu, 21 Mar 2024 15:36:55 +0100 Subject: [PATCH 1307/2402] ci: bsim tests: Use hwmv2 board names Refer to the nrf5340 bsim boards by their hwmv2 name. As a bonus remove a few variable settings which match the defaults from the scripts. Signed-off-by: Alberto Escolar Piedras --- .github/workflows/bsim-tests.yaml | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 97a84732980..9de3f36458c 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -154,22 +154,19 @@ jobs: if: steps.check-bluetooth-files.outputs.any_changed == 'true' || steps.check-common-files.outputs.any_changed == 'true' run: | export ZEPHYR_BASE=${PWD} - export WORK_DIR=${ZEPHYR_BASE}/bsim_bt # Build and run the BT tests for nrf52_bsim: nice tests/bsim/bluetooth/compile.sh RESULTS_FILE=${ZEPHYR_BASE}/${bsim_bt_52_test_results_file} \ TESTS_FILE=tests/bsim/bluetooth/tests.nrf52bsim.txt tests/bsim/run_parallel.sh - # Build and run the BT controller tests also for the nrf5340bsim_nrf5340_cpunet - BOARD=nrf5340bsim_nrf5340_cpunet \ + # Build and run the BT controller tests also for the nrf5340bsim/nrf5340/cpunet nice tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpunet.sh - BOARD=nrf5340bsim_nrf5340_cpunet \ + BOARD=nrf5340bsim/nrf5340/cpunet \ RESULTS_FILE=${ZEPHYR_BASE}/${bsim_bt_53_test_results_file} \ TESTS_FILE=tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpunet.txt \ tests/bsim/run_parallel.sh # Build and run the nrf5340 split stack tests set - BOARD=nrf5340bsim_nrf5340_cpuapp \ nice tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh - BOARD=nrf5340bsim_nrf5340_cpuapp \ + BOARD=nrf5340bsim/nrf5340/cpuapp \ RESULTS_FILE=${ZEPHYR_BASE}/${bsim_bt_53split_test_results_file} \ TESTS_FILE=tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpuapp.txt \ tests/bsim/run_parallel.sh From ccd36125753e77b41eb049da930f2b27dbab62bc Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Thu, 21 Mar 2024 14:11:04 +0000 Subject: [PATCH 1308/2402] scripts: tests: Remove test_harness straggling dirs Current test_harness after its expansion leaves straggling mock_platform directory. This fixes that error. Signed-off-by: Lukasz Mrugala --- scripts/tests/twister/test_harness.py | 57 +++++++++++++++++++-------- 1 file changed, 41 insertions(+), 16 deletions(-) diff --git a/scripts/tests/twister/test_harness.py b/scripts/tests/twister/test_harness.py index cdf82439fba..f9898700af4 100644 --- a/scripts/tests/twister/test_harness.py +++ b/scripts/tests/twister/test_harness.py @@ -73,7 +73,7 @@ def test_harness_process_test(line, fault, fail_on_fault, cap_cov, exp_stat, exp assert harness.capture_coverage == cap_cov -def test_robot_configure(): +def test_robot_configure(tmp_path): #Arrange mock_platform = mock.Mock() mock_platform.name = "mock_platform" @@ -83,7 +83,10 @@ def test_robot_configure(): mock_testsuite.name = "mock_testsuite" mock_testsuite.harness_config = {} - instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir="") + outdir = tmp_path / 'gtest_out' + outdir.mkdir() + + instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir) instance.testsuite.harness_config = { 'robot_test_path': '/path/to/robot/test' } @@ -97,7 +100,7 @@ def test_robot_configure(): assert robot_harness.path == '/path/to/robot/test' -def test_robot_handle(): +def test_robot_handle(tmp_path): #Arrange mock_platform = mock.Mock() mock_platform.name = "mock_platform" @@ -107,7 +110,10 @@ def test_robot_handle(): mock_testsuite.name = "mock_testsuite" mock_testsuite.harness_config = {} - instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir="") + outdir = tmp_path / 'gtest_out' + outdir.mkdir() + + instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir) handler = Robot() handler.instance = instance @@ -130,7 +136,7 @@ def test_robot_handle(): TEST_DATA_2, ids=["passed", "failed"] ) -def test_robot_run_robot_test(caplog, exp_out, returncode, expected_status): +def test_robot_run_robot_test(tmp_path, caplog, exp_out, returncode, expected_status): # Arrange command = "command" @@ -148,7 +154,10 @@ def test_robot_run_robot_test(caplog, exp_out, returncode, expected_status): mock_testsuite.name = "mock_testsuite" mock_testsuite.harness_config = {} - instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir="") + outdir = tmp_path / 'gtest_out' + outdir.mkdir() + + instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir) instance.build_dir = "build_dir" open_mock = mock.mock_open() @@ -183,7 +192,7 @@ def test_robot_run_robot_test(caplog, exp_out, returncode, expected_status): TEST_DATA_3, ids=["one line", "multi line"] ) -def test_console_configure(type, num_patterns): +def test_console_configure(tmp_path, type, num_patterns): #Arrange mock_platform = mock.Mock() mock_platform.name = "mock_platform" @@ -193,7 +202,10 @@ def test_console_configure(type, num_patterns): mock_testsuite.name = "mock_testsuite" mock_testsuite.harness_config = {} - instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir="") + outdir = tmp_path / 'gtest_out' + outdir.mkdir() + + instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir) instance.testsuite.harness_config = { 'type': type, 'regex': ['pattern1', 'pattern2'] @@ -223,7 +235,7 @@ def test_console_configure(type, num_patterns): TEST_DATA_4, ids=["one line", "multi line ordered", "multi line not ordered", "logger error", "fail on fault", "GCOV START", "GCOV END"] ) -def test_console_handle(line_type, ordered_val, exp_state, line, exp_fault, exp_capture): +def test_console_handle(tmp_path, line_type, ordered_val, exp_state, line, exp_fault, exp_capture): mock_platform = mock.Mock() mock_platform.name = "mock_platform" mock_platform.normalized_name = "mock_platform" @@ -232,7 +244,10 @@ def test_console_handle(line_type, ordered_val, exp_state, line, exp_fault, exp_ mock_testsuite.name = "mock_testsuite" mock_testsuite.harness_config = {} - instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir="") + outdir = tmp_path / 'gtest_out' + outdir.mkdir() + + instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir) console = Console() console.instance = instance @@ -278,7 +293,7 @@ def test_console_handle(line_type, ordered_val, exp_state, line, exp_fault, exp_ ids=["hardware pty", "hardware", "non hardware"] ) -def test_pytest__generate_parameters_for_hardware(pty_value, hardware_value): +def test_pytest__generate_parameters_for_hardware(tmp_path, pty_value, hardware_value): #Arrange mock_platform = mock.Mock() mock_platform.name = "mock_platform" @@ -288,7 +303,10 @@ def test_pytest__generate_parameters_for_hardware(pty_value, hardware_value): mock_testsuite.name = "mock_testsuite" mock_testsuite.harness_config = {} - instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir="") + outdir = tmp_path / 'gtest_out' + outdir.mkdir() + + instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir) handler = mock.Mock() handler.instance = instance @@ -351,7 +369,7 @@ def test__update_command_with_env_dependencies(): assert result_cmd == ['cmd', '-p', 'twister_harness.plugin'] -def test_pytest_run(caplog): +def test_pytest_run(tmp_path, caplog): # Arrange timeout = 10 cmd=['command'] @@ -375,7 +393,11 @@ def test_pytest_run(caplog): options = mock.Mock(verbose= 0), type_str = 'handler_type' ) - instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir="") + + outdir = tmp_path / 'gtest_out' + outdir.mkdir() + + instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir) instance.handler = handler test_obj = Pytest() @@ -418,7 +440,7 @@ def test_get_harness(name): TEST_DATA_7, ids=['testsuite', 'testcase', 'pass', 'skip', 'failed', 'ztest pass', 'ztest fail'] ) -def test_test_handle(caplog, exp_out, line, exp_suite_name, exp_status, ztest, state): +def test_test_handle(tmp_path, caplog, exp_out, line, exp_suite_name, exp_status, ztest, state): # Arrange line = line mock_platform = mock.Mock() @@ -429,7 +451,10 @@ def test_test_handle(caplog, exp_out, line, exp_suite_name, exp_status, ztest, s mock_testsuite.name = "mock_testsuite" mock_testsuite.harness_config = {} - instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir="") + outdir = tmp_path / 'gtest_out' + outdir.mkdir() + + instance = TestInstance(testsuite=mock_testsuite, platform=mock_platform, outdir=outdir) test_obj = Test() test_obj.configure(instance) From 568f754f59a56fb0a5569fdf363ab36f4a0d5d1a Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Thu, 21 Mar 2024 14:31:26 +0100 Subject: [PATCH 1309/2402] twister: fix platform len check for device-testing For using --device-testing with --device-serial or --device-serial-pty it is necessary to provide the platform to be used for testing. Not specifying a platform or specifying more than one is an error. Signed-off-by: Luca Burelli --- scripts/pylib/twister/twisterlib/environment.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/environment.py b/scripts/pylib/twister/twisterlib/environment.py index 66b8b41d654..daa691c19d0 100644 --- a/scripts/pylib/twister/twisterlib/environment.py +++ b/scripts/pylib/twister/twisterlib/environment.py @@ -786,10 +786,10 @@ def parse_arguments(parser, args, options = None): logger.error("valgrind enabled but valgrind executable not found") sys.exit(1) - if options.device_testing and (options.device_serial or options.device_serial_pty) and len(options.platform) > 1: - logger.error("""When --device-testing is used with - --device-serial or --device-serial-pty, - only one platform is allowed""") + if options.device_testing and (options.device_serial or options.device_serial_pty) and len(options.platform) != 1: + logger.error("When --device-testing is used with --device-serial " + "or --device-serial-pty, exactly one platform must " + "be specified") sys.exit(1) if options.device_flash_with_test and not options.device_testing: From 5800c53b3e319d2ef056300506426b191ed76ad1 Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Thu, 21 Mar 2024 14:58:06 +0100 Subject: [PATCH 1310/2402] twister: tests: add "no platform" test case for --device-testing Add a test case for --device-testing without a platform specified. Also adjust the error message to match current code. Signed-off-by: Luca Burelli --- scripts/tests/twister/test_environment.py | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/scripts/tests/twister/test_environment.py b/scripts/tests/twister/test_environment.py index feb7ae6a5a1..4623fad0bc4 100644 --- a/scripts/tests/twister/test_environment.py +++ b/scripts/tests/twister/test_environment.py @@ -55,6 +55,19 @@ ['--enable-valgrind'], 'valgrind enabled but valgrind executable not found' ), + ( + None, + None, + None, + [ + '--device-testing', + '--device-serial', + 'dummy', + ], + 'When --device-testing is used with --device-serial' \ + ' or --device-serial-pty, exactly one platform must' \ + ' be specified' + ), ( None, None, @@ -69,7 +82,8 @@ 'dummy_platform2' ], 'When --device-testing is used with --device-serial' \ - ' or --device-serial-pty, only one platform is allowed' + ' or --device-serial-pty, exactly one platform must' \ + ' be specified' ), # Note the underscore. ( @@ -124,6 +138,7 @@ 'west runner without west flash', 'west-flash without device-testing', 'valgrind without executable', + 'device serial without platform', 'device serial with multiple platforms', 'device flash with test without device testing', 'shuffle-tests without subset', From c1e29cc10720cbb059fb925d0d23ad536689cd34 Mon Sep 17 00:00:00 2001 From: Kapil Bhatt Date: Thu, 21 Mar 2024 18:04:54 +0530 Subject: [PATCH 1311/2402] net: wifi: Add channel validity check for AP mode Channel is mandatory for AP mode. It is processed only if its less than or equal to three characters. Otherwise we need to throw error for channel in AP mode. Signed-off-by: Kapil Bhatt --- subsys/net/l2/wifi/wifi_shell.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 92afbc368bd..1eb1c7d1947 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -541,6 +541,11 @@ static int __wifi_args_to_params(size_t argc, char *argv[], idx++; } + if ((idx == 1) && (iface_mode == WIFI_MODE_AP)) { + PR_ERROR("Invalid channel: %s\n", argv[idx]); + return -EINVAL; + } + /* PSK (optional) */ if (idx < argc) { params->psk = argv[idx]; From c69986da4caa0a05b46435b119d58a26d7518138 Mon Sep 17 00:00:00 2001 From: Jon Ringle Date: Tue, 12 Mar 2024 11:45:22 -0400 Subject: [PATCH 1312/2402] soc: atmel: saml2x: Don't do a GCLK SWRST Doing a `GCLK->CTRLA.bit.SWRST = 1` will cause boot chaining to hang. Setting the CPU clock to run from OSCULP32K during initialization is all that is needed. Signed-off-by: Jon Ringle --- soc/atmel/sam0/common/soc_saml2x.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/soc/atmel/sam0/common/soc_saml2x.c b/soc/atmel/sam0/common/soc_saml2x.c index 6f29f9c525d..e7d4746fcb1 100644 --- a/soc/atmel/sam0/common/soc_saml2x.c +++ b/soc/atmel/sam0/common/soc_saml2x.c @@ -31,10 +31,6 @@ static inline void gclk_reset(void) { - GCLK->CTRLA.bit.SWRST = 1; - while (GCLK->SYNCBUSY.bit.SWRST) { - } - /* by default, OSC16M will be enabled at 4 MHz, and the CPU will * run from it. to permit initialization, the CPU is temporarily * clocked from OSCULP32K, and OSC16M is disabled From d7ba98aba5b0e0b82d6873961a889662ad6a4202 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Sun, 17 Mar 2024 15:03:17 +0200 Subject: [PATCH 1313/2402] net: virtual: Add macro to instantiate multiple interfaces Add NET_VIRTUAL_INTERFACE_INIT_INSTANCE() macro which can be used to create multiple virtual network interfaces in one go. Signed-off-by: Jukka Rissanen --- include/zephyr/net/virtual.h | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/include/zephyr/net/virtual.h b/include/zephyr/net/virtual.h index 4509ff351ff..8ffbbe4efe6 100644 --- a/include/zephyr/net/virtual.h +++ b/include/zephyr/net/virtual.h @@ -293,6 +293,14 @@ net_virtual_get_iface_capabilities(struct net_if *iface) Z_NET_DEVICE_INIT(node_id, dev_id, name, init_fn, pm, data, \ config, prio, api, VIRTUAL_L2, \ NET_L2_GET_CTX_TYPE(VIRTUAL_L2), mtu) + +#define Z_NET_VIRTUAL_INTERFACE_INIT_INSTANCE(node_id, dev_id, name, \ + inst, init_fn, pm, data, \ + config, prio, api, mtu) \ + Z_NET_DEVICE_INIT_INSTANCE(node_id, dev_id, name, inst, \ + init_fn, pm, data, \ + config, prio, api, VIRTUAL_L2, \ + NET_L2_GET_CTX_TYPE(VIRTUAL_L2), mtu) /** @endcond */ /** @@ -322,6 +330,36 @@ net_virtual_get_iface_capabilities(struct net_if *iface) init_fn, pm, data, config, prio, \ api, mtu) +/** + * @brief Create a virtual network interface. Binding to another interface + * is done at runtime by calling net_virtual_interface_attach(). + * The attaching is done automatically when setting up tunneling + * when peer IP address is set in IP tunneling driver. + * + * @param dev_id Network device id. + * @param name The name this instance of the driver exposes to + * the system. + * @param inst instance number + * @param init_fn Address to the init function of the driver. + * @param pm Reference to struct pm_device associated with the device. + * (optional). + * @param data Pointer to the device's private data. + * @param config The address to the structure containing the + * configuration information for this instance of the driver. + * @param prio The initialization level at which configuration occurs. + * @param api Provides an initial pointer to the API function struct + * used by the driver. Can be NULL. + * @param mtu Maximum transfer unit in bytes for this network interface. + * This is the default value and its value can be tweaked at runtime. + */ +#define NET_VIRTUAL_INTERFACE_INIT_INSTANCE(dev_id, name, inst, \ + init_fn, pm, data, \ + config, prio, api, mtu) \ + Z_NET_VIRTUAL_INTERFACE_INIT_INSTANCE(DT_INVALID_NODE, dev_id, \ + name, inst, \ + init_fn, pm, data, config, \ + prio, api, mtu) + /** * @} */ From ce8c618b6bff89c93eb254f0970b0a8bce880291 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 20 Mar 2024 18:02:40 +0200 Subject: [PATCH 1314/2402] net: virtual: Fix the virtual L2 receive function The function needs to loop through the virtual interfaces tied to this physical interface. Signed-off-by: Jukka Rissanen --- subsys/net/l2/virtual/virtual.c | 36 ++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/subsys/net/l2/virtual/virtual.c b/subsys/net/l2/virtual/virtual.c index ad50eb12041..c30bccb439e 100644 --- a/subsys/net/l2/virtual/virtual.c +++ b/subsys/net/l2/virtual/virtual.c @@ -22,10 +22,40 @@ LOG_MODULE_REGISTER(net_virtual, CONFIG_NET_L2_VIRTUAL_LOG_LEVEL); static enum net_verdict virtual_recv(struct net_if *iface, struct net_pkt *pkt) { - ARG_UNUSED(iface); - ARG_UNUSED(pkt); + struct virtual_interface_context *ctx, *tmp; + const struct virtual_interface_api *api; + enum net_verdict verdict; + sys_slist_t *interfaces; - return NET_CONTINUE; + interfaces = &iface->config.virtual_interfaces; + + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(interfaces, ctx, tmp, node) { + if (ctx->virtual_iface == NULL) { + continue; + } + + api = net_if_get_device(ctx->virtual_iface)->api; + if (!api || api->recv == NULL) { + continue; + } + + if (!net_if_is_up(ctx->virtual_iface)) { + NET_DBG("Interface %d is down.", + net_if_get_by_iface(ctx->virtual_iface)); + continue; + } + + verdict = api->recv(ctx->virtual_iface, pkt); + if (verdict == NET_CONTINUE) { + continue; + } + + return verdict; + } + + NET_DBG("No handler, dropping pkt %p len %zu", pkt, net_pkt_get_len(pkt)); + + return NET_DROP; } static int virtual_send(struct net_if *iface, struct net_pkt *pkt) From f61453de10ef488a74f430281150ee7c5f4fd1e8 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 20 Mar 2024 18:03:53 +0200 Subject: [PATCH 1315/2402] net: virtual: Add statistics collection Collect statistics of sent/received network packets for the virtual interface. Signed-off-by: Jukka Rissanen --- subsys/net/l2/virtual/virtual.c | 41 ++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/subsys/net/l2/virtual/virtual.c b/subsys/net/l2/virtual/virtual.c index c30bccb439e..299f6ecbfc2 100644 --- a/subsys/net/l2/virtual/virtual.c +++ b/subsys/net/l2/virtual/virtual.c @@ -16,6 +16,7 @@ LOG_MODULE_REGISTER(net_virtual, CONFIG_NET_L2_VIRTUAL_LOG_LEVEL); #include #include "net_private.h" +#include "net_stats.h" #define NET_BUF_TIMEOUT K_MSEC(100) @@ -50,6 +51,21 @@ static enum net_verdict virtual_recv(struct net_if *iface, continue; } + if (IS_ENABLED(CONFIG_NET_STATISTICS)) { + size_t pkt_len; + + pkt_len = net_pkt_get_len(pkt); + + NET_DBG("Received pkt %p len %zu", pkt, pkt_len); + + net_stats_update_bytes_recv(ctx->virtual_iface, + pkt_len); + } + + if (verdict == NET_DROP) { + net_stats_update_processing_error(ctx->virtual_iface); + } + return verdict; } @@ -61,15 +77,27 @@ static enum net_verdict virtual_recv(struct net_if *iface, static int virtual_send(struct net_if *iface, struct net_pkt *pkt) { const struct virtual_interface_api *api = net_if_get_device(iface)->api; + size_t pkt_len; + int ret; if (!api) { return -ENOENT; } + if (IS_ENABLED(CONFIG_NET_STATISTICS)) { + pkt_len = net_pkt_get_len(pkt); + } + /* As we are just passing data through, the net_pkt is not freed here. */ + ret = api->send(iface, pkt); + + if (IS_ENABLED(CONFIG_NET_STATISTICS) && ret == 0) { + NET_DBG("Sent pkt %p len %zu", pkt, pkt_len); + net_stats_update_bytes_sent(iface, pkt_len); + } - return api->send(iface, pkt); + return ret; } static int virtual_enable(struct net_if *iface, bool state) @@ -388,6 +416,17 @@ enum net_verdict net_virtual_input(struct net_if *input_iface, continue; } + if (IS_ENABLED(CONFIG_NET_STATISTICS)) { + size_t pkt_len; + + pkt_len = net_pkt_get_len(pkt); + + NET_DBG("Received pkt %p len %zu", pkt, pkt_len); + + net_stats_update_bytes_recv(ctx->virtual_iface, + pkt_len); + } + return verdict; } From 8a972d969fb15d3dd201a6c949a3bb92422448ea Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 21 Mar 2024 12:24:10 +0200 Subject: [PATCH 1316/2402] net: pkt: IP tunneling needs to store remote address Use the "remote" sockaddr field for storing the remote tunnel end point address. This is used also by offloading but tunneling and offloading are not used at the same time for the same interface so sharing the variable will not conflict. Signed-off-by: Jukka Rissanen --- include/zephyr/net/net_pkt.h | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/include/zephyr/net/net_pkt.h b/include/zephyr/net/net_pkt.h index c668bc72492..559ac1faea8 100644 --- a/include/zephyr/net/net_pkt.h +++ b/include/zephyr/net/net_pkt.h @@ -290,11 +290,20 @@ struct net_pkt { */ uint8_t priority; -#if defined(CONFIG_NET_OFFLOAD) +#if defined(CONFIG_NET_OFFLOAD) || defined(CONFIG_NET_L2_IPIP) /* Remote address of the recived packet. This is only used by - * network interfaces with an offloaded TCP/IP stack. + * network interfaces with an offloaded TCP/IP stack, or if we + * have network tunneling in use. */ - struct sockaddr remote; + union { + struct sockaddr remote; + + /* This will make sure that there is enough storage to store + * the address struct. The access to value is via remote + * address. + */ + struct sockaddr_storage remote_storage; + }; #endif /* CONFIG_NET_OFFLOAD */ /* @endcond */ @@ -1355,6 +1364,20 @@ static inline bool net_pkt_filter_local_in_recv_ok(struct net_pkt *pkt) #endif /* CONFIG_NET_PKT_FILTER && CONFIG_NET_PKT_FILTER_LOCAL_IN_HOOK */ +#if defined(CONFIG_NET_OFFLOAD) || defined(CONFIG_NET_L2_IPIP) +static inline struct sockaddr *net_pkt_remote_address(struct net_pkt *pkt) +{ + return &pkt->remote; +} + +static inline void net_pkt_set_remote_address(struct net_pkt *pkt, + struct sockaddr *address, + socklen_t len) +{ + memcpy(&pkt->remote, address, len); +} +#endif /* CONFIG_NET_OFFLOAD || CONFIG_NET_L2_IPIP */ + /* @endcond */ /** From 2c1f10b60ee053b243902e544f8bc55e3e37a084 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 21 Mar 2024 12:30:24 +0200 Subject: [PATCH 1317/2402] net: virtual: Remove the input callback as obsolete The input callback was an unfortunate idea which just complicated how the packet flows through virtual interfaces so removing it. The data is passed normally through the recv callback from now on. Signed-off-by: Jukka Rissanen --- include/zephyr/net/virtual.h | 11 ++---- subsys/net/l2/virtual/virtual.c | 65 --------------------------------- 2 files changed, 3 insertions(+), 73 deletions(-) diff --git a/include/zephyr/net/virtual.h b/include/zephyr/net/virtual.h index 8ffbbe4efe6..36add6d97dc 100644 --- a/include/zephyr/net/virtual.h +++ b/include/zephyr/net/virtual.h @@ -88,18 +88,13 @@ struct virtual_interface_api { /** Send a network packet */ int (*send)(struct net_if *iface, struct net_pkt *pkt); - /** Receive a network packet */ - enum net_verdict (*recv)(struct net_if *iface, struct net_pkt *pkt); - - /** Check if this received network packet is for this interface. + /** + * Receive a network packet. * The callback returns NET_CONTINUE if this interface will accept the * packet and pass it upper layers, NET_DROP if the packet is to be * dropped and NET_OK to pass it to next interface. */ - enum net_verdict (*input)(struct net_if *input_iface, - struct net_if *iface, - struct net_addr *remote_addr, - struct net_pkt *pkt); + enum net_verdict (*recv)(struct net_if *iface, struct net_pkt *pkt); /** Pass the attachment information to virtual interface */ int (*attach)(struct net_if *virtual_iface, struct net_if *iface); diff --git a/subsys/net/l2/virtual/virtual.c b/subsys/net/l2/virtual/virtual.c index 299f6ecbfc2..4e0fa0311b0 100644 --- a/subsys/net/l2/virtual/virtual.c +++ b/subsys/net/l2/virtual/virtual.c @@ -368,71 +368,6 @@ enum net_l2_flags net_virtual_set_flags(struct net_if *iface, return old_flags; } -enum net_verdict net_virtual_input(struct net_if *input_iface, - struct net_addr *remote_addr, - struct net_pkt *pkt) -{ - struct virtual_interface_context *ctx, *tmp; - const struct virtual_interface_api *virt; - struct net_pkt_cursor hdr_start; - enum net_verdict verdict; - sys_slist_t *interfaces; - uint8_t iptype; - - net_pkt_cursor_backup(pkt, &hdr_start); - - if (net_pkt_read_u8(pkt, &iptype)) { - return NET_DROP; - } - - net_pkt_cursor_restore(pkt, &hdr_start); - - switch (iptype & 0xf0) { - case 0x60: - net_pkt_set_family(pkt, AF_INET6); - break; - case 0x40: - net_pkt_set_family(pkt, AF_INET); - break; - default: - return NET_DROP; - } - - interfaces = &input_iface->config.virtual_interfaces; - - SYS_SLIST_FOR_EACH_CONTAINER_SAFE(interfaces, ctx, tmp, node) { - if (ctx->virtual_iface == NULL) { - continue; - } - - virt = net_if_get_device(ctx->virtual_iface)->api; - if (!virt || virt->input == NULL) { - continue; - } - - verdict = virt->input(input_iface, ctx->virtual_iface, - remote_addr, pkt); - if (verdict == NET_OK) { - continue; - } - - if (IS_ENABLED(CONFIG_NET_STATISTICS)) { - size_t pkt_len; - - pkt_len = net_pkt_get_len(pkt); - - NET_DBG("Received pkt %p len %zu", pkt, pkt_len); - - net_stats_update_bytes_recv(ctx->virtual_iface, - pkt_len); - } - - return verdict; - } - - return NET_DROP; -} - void net_virtual_init(struct net_if *iface) { struct virtual_interface_context *ctx; From 280391ded894aed389cf3dc223c1acb009843211 Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 21 Mar 2024 12:35:31 +0200 Subject: [PATCH 1318/2402] net: ipip: Refactor the IP tunneling support Refactor the IP tunneling support as the input callback was removed in previous commit. The data will flow through the recv callback now as expected. Signed-off-by: Jukka Rissanen --- include/zephyr/net/virtual.h | 4 +- subsys/net/ip/ipv4.c | 20 ++- subsys/net/ip/ipv6.c | 20 ++- subsys/net/ip/net_private.h | 2 + subsys/net/l2/virtual/ipip/ipip.c | 237 +++++++++++++++++++++--------- 5 files changed, 201 insertions(+), 82 deletions(-) diff --git a/include/zephyr/net/virtual.h b/include/zephyr/net/virtual.h index 36add6d97dc..cbcf0dbe7d0 100644 --- a/include/zephyr/net/virtual.h +++ b/include/zephyr/net/virtual.h @@ -90,9 +90,9 @@ struct virtual_interface_api { /** * Receive a network packet. - * The callback returns NET_CONTINUE if this interface will accept the + * The callback returns NET_OK if this interface will accept the * packet and pass it upper layers, NET_DROP if the packet is to be - * dropped and NET_OK to pass it to next interface. + * dropped and NET_CONTINUE to pass it to next interface. */ enum net_verdict (*recv)(struct net_if *iface, struct net_pkt *pkt); diff --git a/subsys/net/ip/ipv4.c b/subsys/net/ip/ipv4.c index cf318b1416d..36ac0c4787b 100644 --- a/subsys/net/ip/ipv4.c +++ b/subsys/net/ip/ipv4.c @@ -246,7 +246,7 @@ enum net_verdict net_ipv4_input(struct net_pkt *pkt, bool is_loopback) uint8_t opts_len; int pkt_len; -#if defined(CONFIG_NET_L2_VIRTUAL) +#if defined(CONFIG_NET_L2_IPIP) struct net_pkt_cursor hdr_start; net_pkt_cursor_backup(pkt, &hdr_start); @@ -403,21 +403,27 @@ enum net_verdict net_ipv4_input(struct net_pkt *pkt, bool is_loopback) } break; -#if defined(CONFIG_NET_L2_VIRTUAL) +#if defined(CONFIG_NET_L2_IPIP) case IPPROTO_IPV6: case IPPROTO_IPIP: { - struct net_addr remote_addr; + struct sockaddr_in remote_addr = { 0 }; + struct net_if *tunnel_iface; - remote_addr.family = AF_INET; - net_ipv4_addr_copy_raw((uint8_t *)&remote_addr.in_addr, hdr->src); + remote_addr.sin_family = AF_INET; + net_ipv4_addr_copy_raw((uint8_t *)&remote_addr.sin_addr, hdr->src); + + net_pkt_set_remote_address(pkt, (struct sockaddr *)&remote_addr, + sizeof(struct sockaddr_in)); /* Get rid of the old IP header */ net_pkt_cursor_restore(pkt, &hdr_start); net_pkt_pull(pkt, net_pkt_ip_hdr_len(pkt) + net_pkt_ipv4_opts_len(pkt)); - return net_virtual_input(net_pkt_iface(pkt), &remote_addr, - pkt); + tunnel_iface = net_ipip_get_virtual_interface(net_pkt_iface(pkt)); + if (tunnel_iface != NULL && net_if_l2(tunnel_iface)->recv != NULL) { + return net_if_l2(tunnel_iface)->recv(net_pkt_iface(pkt), pkt); + } } #endif } diff --git a/subsys/net/ip/ipv6.c b/subsys/net/ip/ipv6.c index 8276d9a7f8f..2a99abc6b89 100644 --- a/subsys/net/ip/ipv6.c +++ b/subsys/net/ip/ipv6.c @@ -466,7 +466,7 @@ enum net_verdict net_ipv6_input(struct net_pkt *pkt, bool is_loopback) union net_ip_header ip; int pkt_len; -#if defined(CONFIG_NET_L2_VIRTUAL) +#if defined(CONFIG_NET_L2_IPIP) struct net_pkt_cursor hdr_start; net_pkt_cursor_backup(pkt, &hdr_start); @@ -725,20 +725,28 @@ enum net_verdict net_ipv6_input(struct net_pkt *pkt, bool is_loopback) verdict = NET_OK; } break; -#if defined(CONFIG_NET_L2_VIRTUAL) + +#if defined(CONFIG_NET_L2_IPIP) case IPPROTO_IPV6: case IPPROTO_IPIP: { - struct net_addr remote_addr; + struct sockaddr_in6 remote_addr = { 0 }; + struct net_if *tunnel_iface; + + remote_addr.sin6_family = AF_INET6; + net_ipv6_addr_copy_raw((uint8_t *)&remote_addr.sin6_addr, hdr->src); - remote_addr.family = AF_INET6; - net_ipv6_addr_copy_raw((uint8_t *)&remote_addr.in6_addr, hdr->src); + net_pkt_set_remote_address(pkt, (struct sockaddr *)&remote_addr, + sizeof(struct sockaddr_in6)); /* Get rid of the old IP header */ net_pkt_cursor_restore(pkt, &hdr_start); net_pkt_pull(pkt, net_pkt_ip_hdr_len(pkt) + net_pkt_ipv6_ext_len(pkt)); - return net_virtual_input(pkt_iface, &remote_addr, pkt); + tunnel_iface = net_ipip_get_virtual_interface(net_pkt_iface(pkt)); + if (tunnel_iface != NULL && net_if_l2(tunnel_iface)->recv != NULL) { + return net_if_l2(tunnel_iface)->recv(net_pkt_iface(pkt), pkt); + } } #endif } diff --git a/subsys/net/ip/net_private.h b/subsys/net/ip/net_private.h index b3fef2dee9f..a0500f0c862 100644 --- a/subsys/net/ip/net_private.h +++ b/subsys/net/ip/net_private.h @@ -69,6 +69,8 @@ extern int net_icmp_call_ipv6_handlers(struct net_pkt *pkt, struct net_ipv6_hdr *ipv6_hdr, struct net_icmp_hdr *icmp_hdr); +extern struct net_if *net_ipip_get_virtual_interface(struct net_if *input_iface); + #if defined(CONFIG_NET_NATIVE) || defined(CONFIG_NET_OFFLOAD) extern void net_context_init(void); extern const char *net_context_state(struct net_context *context); diff --git a/subsys/net/l2/virtual/ipip/ipip.c b/subsys/net/l2/virtual/ipip/ipip.c index 3fc64151b91..52e595a7358 100644 --- a/subsys/net/l2/virtual/ipip/ipip.c +++ b/subsys/net/l2/virtual/ipip/ipip.c @@ -32,6 +32,10 @@ LOG_MODULE_REGISTER(net_virtual_ipip, CONFIG_NET_L2_IPIP_LOG_LEVEL); #define PKT_ALLOC_TIME K_MSEC(50) +static K_MUTEX_DEFINE(lock); + +static void init_context_iface(void); + struct ipip_context { struct net_if *iface; struct net_if *attached_to; @@ -45,10 +49,20 @@ struct ipip_context { const struct in6_addr *my6addr; }; + bool is_used; bool status; bool init_done; }; +static int virt_dev_init(const struct device *dev) +{ + ARG_UNUSED(dev); + + init_context_iface(); + + return 0; +} + static void iface_init(struct net_if *iface) { struct ipip_context *ctx = net_if_get_device(iface)->data; @@ -252,35 +266,20 @@ static int interface_send(struct net_if *iface, struct net_pkt *pkt) return ret; } -static enum net_verdict interface_recv(struct net_if *iface, - struct net_pkt *pkt) -{ - if (DEBUG_RX) { - char str[sizeof("RX iface xx")]; - - snprintk(str, sizeof(str), "RX iface %d", - net_if_get_by_iface(iface)); - - net_pkt_hexdump(pkt, str); - } - - return NET_CONTINUE; -} - static bool verify_remote_addr(struct ipip_context *ctx, - struct net_addr *remote_addr) + struct sockaddr *remote_addr) { - if (ctx->family != remote_addr->family) { + if (ctx->family != remote_addr->sa_family) { return false; } if (ctx->family == AF_INET) { - if (memcmp(&ctx->peer.in_addr, &remote_addr->in_addr, + if (memcmp(&ctx->peer.in_addr, &net_sin(remote_addr)->sin_addr, sizeof(struct in_addr)) == 0) { return true; } } else { - if (memcmp(&ctx->peer.in6_addr, &remote_addr->in6_addr, + if (memcmp(&ctx->peer.in6_addr, &net_sin6(remote_addr)->sin6_addr, sizeof(struct in6_addr)) == 0) { return true; } @@ -289,28 +288,61 @@ static bool verify_remote_addr(struct ipip_context *ctx, return false; } -static enum net_verdict interface_input(struct net_if *input_iface, - struct net_if *virtual_iface, - struct net_addr *remote_addr, - struct net_pkt *pkt) +static enum net_verdict interface_recv(struct net_if *iface, + struct net_pkt *pkt) { - struct ipip_context *ctx = net_if_get_device(virtual_iface)->data; - struct net_if *iface; + struct ipip_context *ctx = net_if_get_device(iface)->data; + struct net_pkt_cursor hdr_start; + uint8_t iptype; + + net_pkt_cursor_backup(pkt, &hdr_start); + + if (net_pkt_read_u8(pkt, &iptype)) { + return NET_DROP; + } + + net_pkt_cursor_restore(pkt, &hdr_start); + + switch (iptype & 0xf0) { + case 0x60: + net_pkt_set_family(pkt, AF_INET6); + break; + case 0x40: + net_pkt_set_family(pkt, AF_INET); + break; + default: + return NET_DROP; + } /* Make sure we are receiving data from remote end of the * tunnel. See RFC4213 chapter 4 for details. */ - if (!verify_remote_addr(ctx, remote_addr)) { - NET_DBG("DROP: remote address unknown"); + if (!verify_remote_addr(ctx, net_pkt_remote_address(pkt))) { + NET_DBG("DROP: remote address %s unknown", + net_pkt_remote_address(pkt)->sa_family == AF_INET6 ? + net_sprint_ipv6_addr(&net_sin6(net_pkt_remote_address(pkt))->sin6_addr) : + net_sprint_ipv4_addr(&net_sin(net_pkt_remote_address(pkt))->sin_addr)); return NET_DROP; } + if (DEBUG_RX) { + char str[sizeof("RX iface xx")]; + + snprintk(str, sizeof(str), "RX iface %d", + net_if_get_by_iface(iface)); + + net_pkt_hexdump(pkt, str); + } + /* net_pkt cursor must point to correct place so that we can fetch * the network header. */ if (IS_ENABLED(CONFIG_NET_IPV6) && net_pkt_family(pkt) == AF_INET6) { NET_PKT_DATA_ACCESS_DEFINE(access, struct net_ipv6_hdr); struct net_ipv6_hdr *hdr; + struct net_if *iface_test; + + net_pkt_cursor_backup(pkt, &hdr_start); hdr = (struct net_ipv6_hdr *)net_pkt_get_data(pkt, &access); if (!hdr) { @@ -318,22 +350,17 @@ static enum net_verdict interface_input(struct net_if *input_iface, } /* RFC4213 chapter 3.6 */ - iface = net_if_ipv6_select_src_iface((struct in6_addr *)hdr->dst); - if (iface == NULL) { + iface_test = net_if_ipv6_select_src_iface((struct in6_addr *)hdr->dst); + if (iface_test == NULL) { NET_DBG("DROP: not for me (dst %s)", net_sprint_ipv6_addr(&hdr->dst)); return NET_DROP; } - if (!net_if_is_up(iface)) { - NET_DBG("DROP: interface %d down", - net_if_get_by_iface(iface)); - return NET_DROP; - } - - if (input_iface != ctx->attached_to || - virtual_iface != iface) { - NET_DBG("DROP: wrong interface"); + if (iface != iface_test) { + NET_DBG("DROP: wrong interface %d (%p), expecting %d (%p)", + net_if_get_by_iface(iface_test), iface_test, + net_if_get_by_iface(iface), iface); return NET_DROP; } @@ -345,38 +372,56 @@ static enum net_verdict interface_input(struct net_if *input_iface, net_pkt_set_iface(pkt, iface); - return net_if_recv_data(iface, pkt); + net_pkt_cursor_restore(pkt, &hdr_start); + + return net_ipv6_input(pkt, false); } if (IS_ENABLED(CONFIG_NET_IPV4) && net_pkt_family(pkt) == AF_INET) { NET_PKT_DATA_ACCESS_DEFINE(access, struct net_ipv4_hdr); struct net_ipv4_hdr *hdr; + struct net_if *iface_test; + uint16_t sum; + + net_pkt_cursor_backup(pkt, &hdr_start); hdr = (struct net_ipv4_hdr *)net_pkt_get_data(pkt, &access); if (!hdr) { return NET_DROP; } - iface = net_if_ipv4_select_src_iface((struct in_addr *)hdr->dst); - if (iface == NULL) { + iface_test = net_if_ipv4_select_src_iface((struct in_addr *)hdr->dst); + if (iface_test == NULL) { NET_DBG("DROP: not for me (dst %s)", net_sprint_ipv4_addr(&hdr->dst)); return NET_DROP; } - if (!net_if_is_up(iface)) { - NET_DBG("DROP: interface %d down", - net_if_get_by_iface(iface)); + if (iface != iface_test) { + NET_DBG("DROP: wrong interface %d (%p), expecting %d (%p)", + net_if_get_by_iface(iface_test), iface_test, + net_if_get_by_iface(iface), iface); return NET_DROP; } /* TTL fields is decremented, RFC2003 chapter 3.1 */ hdr->ttl--; + + /* Recalculate the checksum because TTL was changed */ + hdr->chksum = 0U; + + sum = calc_chksum(0, access.data, access.size); + sum = (sum == 0U) ? 0xffff : htons(sum); + + hdr->chksum = ~sum; + (void)net_pkt_set_data(pkt, &access); net_pkt_set_iface(pkt, iface); - return net_if_recv_data(iface, pkt); + net_pkt_cursor_restore(pkt, &hdr_start); + + return net_ipv4_input(pkt, false); } return NET_CONTINUE; @@ -390,25 +435,35 @@ static int interface_attach(struct net_if *iface, struct net_if *lower_iface) return -ENOENT; } + k_mutex_lock(&lock, K_FOREVER); + ctx = net_if_get_device(iface)->data; ctx->attached_to = lower_iface; + ctx->iface = iface; - if (IS_ENABLED(CONFIG_NET_IPV6) && ctx->family == AF_INET6) { - struct net_if_addr *ifaddr; - struct in6_addr iid; - - /* RFC4213 chapter 3.7 */ - net_ipv6_addr_create_iid(&iid, net_if_get_link_addr(iface)); - - ifaddr = net_if_ipv6_addr_add(iface, &iid, NET_ADDR_AUTOCONF, - 0); - if (!ifaddr) { - NET_ERR("Cannot add %s address to interface %p", - net_sprint_ipv6_addr(&iid), - iface); + if (lower_iface == NULL) { + ctx->is_used = false; + } else { + ctx->is_used = true; + + if (IS_ENABLED(CONFIG_NET_IPV6) && ctx->family == AF_INET6) { + struct net_if_addr *ifaddr; + struct in6_addr iid; + + /* RFC4213 chapter 3.7 */ + net_ipv6_addr_create_iid(&iid, net_if_get_link_addr(iface)); + + ifaddr = net_if_ipv6_addr_add(iface, &iid, NET_ADDR_AUTOCONF, 0); + if (!ifaddr) { + NET_ERR("Cannot add %s address to interface %p", + net_sprint_ipv6_addr(&iid), + iface); + } } } + k_mutex_unlock(&lock); + return 0; } @@ -541,21 +596,69 @@ static const struct virtual_interface_api ipip_iface_api = { .stop = interface_stop, .send = interface_send, .recv = interface_recv, - .input = interface_input, .attach = interface_attach, .set_config = interface_set_config, .get_config = interface_get_config, }; -#define NET_IPIP_DATA(x, _) \ +#define NET_IPIP_INTERFACE_INIT(x, _) \ static struct ipip_context ipip_context_data_##x = { \ + }; \ + NET_VIRTUAL_INTERFACE_INIT_INSTANCE(ipip_##x, \ + "IP_TUNNEL" #x, \ + x, \ + virt_dev_init, \ + NULL, \ + &ipip_context_data_##x, \ + NULL, /* config */ \ + CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \ + &ipip_iface_api, \ + IPIPV4_MTU) + +LISTIFY(CONFIG_NET_L2_IPIP_TUNNEL_COUNT, NET_IPIP_INTERFACE_INIT, (;), _); + +#define INIT_IPIP_CONTEXT_PTR(x, _) \ + [x] = &ipip_context_data_##x + +static struct ipip_context *ipip_ctx[] = { + LISTIFY(CONFIG_NET_L2_IPIP_TUNNEL_COUNT, INIT_IPIP_CONTEXT_PTR, (,), _) +}; + +#define INIT_IPIP_CONTEXT_IFACE(x, _) \ + ipip_context_data_##x.iface = NET_IF_GET(ipip_##x, x) + +static void init_context_iface(void) +{ + static bool init_done; + + if (init_done) { + return; } -#define NET_IPIP_INTERFACE_INIT(x, _) \ - NET_VIRTUAL_INTERFACE_INIT(ipip##x, "IP_TUNNEL" #x, NULL, \ - NULL, &ipip_context_data_##x, NULL, \ - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \ - &ipip_iface_api, IPIPV4_MTU) + init_done = true; -LISTIFY(CONFIG_NET_L2_IPIP_TUNNEL_COUNT, NET_IPIP_DATA, (;), _); -LISTIFY(CONFIG_NET_L2_IPIP_TUNNEL_COUNT, NET_IPIP_INTERFACE_INIT, (;), _); + LISTIFY(CONFIG_NET_L2_IPIP_TUNNEL_COUNT, INIT_IPIP_CONTEXT_IFACE, (;), _); +} + +struct net_if *net_ipip_get_virtual_interface(struct net_if *input_iface) +{ + struct net_if *iface = NULL; + + k_mutex_lock(&lock, K_FOREVER); + + ARRAY_FOR_EACH(ipip_ctx, i) { + if (ipip_ctx[i] == NULL || !ipip_ctx[i]->is_used) { + continue; + } + + if (input_iface == ipip_ctx[i]->attached_to) { + iface = ipip_ctx[i]->iface; + goto out; + } + } + +out: + k_mutex_unlock(&lock); + + return iface; +} From 4ac3392611a1e39d403c367f8830f01083d6523a Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 21 Mar 2024 12:37:23 +0200 Subject: [PATCH 1319/2402] tests: net: virtual: Fix the tests The tests are now working as expected after the virtual interface refactoring which required changes to IP tunneling. Signed-off-by: Jukka Rissanen --- tests/net/virtual/src/main.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/tests/net/virtual/src/main.c b/tests/net/virtual/src/main.c index 003bebd33e0..11eaf6bc6ad 100644 --- a/tests/net/virtual/src/main.c +++ b/tests/net/virtual/src/main.c @@ -738,6 +738,12 @@ ZTEST(net_virtual, test_virtual_05_set_peer) net_if_get_by_iface(iface), net_if_get_by_iface(dummy_interfaces[0]), ret); + + ret = net_virtual_interface_attach(iface, NULL); + zassert_equal(ret, 0, "Cannot deattach %d from %d (%d)", + net_if_get_by_iface(iface), + net_if_get_by_iface(eth_interfaces[0]), + ret); } ZTEST(net_virtual, test_virtual_06_get_peer) @@ -792,11 +798,24 @@ ZTEST(net_virtual, test_virtual_07_verify_name) "Cannot get name"); } +ZTEST(net_virtual, test_virtual_08_detach) +{ + struct net_if *iface = virtual_interfaces[0]; + int ret; + + ret = net_virtual_interface_attach(iface, NULL); + zassert_true((ret == 0) || (ret == -EALREADY), + "Cannot deattach %d from %d (%d)", + net_if_get_by_iface(iface), + net_if_get_by_iface(eth_interfaces[0]), + ret); +} + ZTEST(net_virtual, test_virtual_08_send_data_to_tunnel) { struct virtual_interface_req_params params = { 0 }; struct net_if *iface = virtual_interfaces[0]; - struct net_if *attached; + struct net_if *attached = eth_interfaces[0]; struct sockaddr dst_addr, src_addr; void *addr; int addrlen; @@ -1011,7 +1030,12 @@ static void test_virtual_recv_data_from_tunnel(int remote_ip, net_pkt_write(inner, test_data, strlen(test_data)); net_pkt_cursor_init(inner); - net_ipv4_finalize(inner, IPPROTO_UDP); + + if (virtual_addr.sa_family == AF_INET) { + net_ipv4_finalize(inner, IPPROTO_UDP); + } else { + net_ipv6_finalize(inner, IPPROTO_UDP); + } net_buf_frag_add(outer->buffer, inner->buffer); inner->buffer = NULL; @@ -1050,7 +1074,7 @@ static void test_virtual_recv_data_from_tunnel(int remote_ip, } if (expected_ok) { - zassert_equal(verdict, NET_CONTINUE, + zassert_equal(verdict, NET_OK, "Packet not accepted (%d)", verdict); } else { From e0133cfa170e196b60e7d55c3b4b712d9ea2e56e Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Thu, 21 Mar 2024 15:52:51 +0200 Subject: [PATCH 1320/2402] doc: migration-guide-3.7: Add virtual net interface information The virtual interface API "input" callback is removed and its functionality is implemented in "recv" callback. This change affected the IP tunneling implementation in the network stack. Signed-off-by: Jukka Rissanen --- doc/releases/migration-guide-3.7.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index 5e22815348c..451e54ecfd3 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -175,6 +175,10 @@ Networking one IPv4 address / network interface, the netmask must be specified for each IPv4 address separately. (:github:`68419`) +* Virtual network interface API no longer has the `input` callback. The input callback was + used to read the inner IPv4/IPv6 packets in an IP tunnel. This incoming tunnel read is now + implemented in `recv` callback. (:github:`70549`) + Other Subsystems **************** From 4c9d27d9763b4e21a4d04a20094fe88ee2786253 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 25 Mar 2024 11:27:32 +0100 Subject: [PATCH 1321/2402] MAINTAINERS: Add aescolar as collaborator for the C library Add aescolar as collaborator for the C library. Note that as maintainer of the "native" ports, I have been taking care of the host C library integration in Zephyr. Signed-off-by: Alberto Escolar Piedras --- MAINTAINERS.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index a2d2ecc9da2..51f6267f260 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -556,6 +556,7 @@ C library: maintainers: - stephanosio collaborators: + - aescolar - nashif - keith-packard - cfriedt From 3c56af6c8747998b835432afce7d0f5c8756fe7f Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Mon, 25 Mar 2024 08:10:19 -0400 Subject: [PATCH 1322/2402] drivers: serial: bt: Fix Max payload to be transmitted with minimum MTU As correctly pointed during the initial PR Review, when the MTU-size is 23 the effective payload that can be transferred is MTU-3 = 20. Thus, this change to be consistent. Signed-off-by: Luis Ubieda --- drivers/serial/uart_bt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/uart_bt.c b/drivers/serial/uart_bt.c index 79353fe7307..bf9bf98a653 100644 --- a/drivers/serial/uart_bt.c +++ b/drivers/serial/uart_bt.c @@ -101,7 +101,7 @@ static void tx_work_handler(struct k_work *work) * size per-connection. This has the trade-off of limiting * throughput but allows multi-connection support. */ - len = ring_buf_get_claim(dev_data->uart.tx_ringbuf, &data, 23); + len = ring_buf_get_claim(dev_data->uart.tx_ringbuf, &data, 20); if (len > 0) { err = bt_nus_inst_send(NULL, dev_data->bt.inst, data, len); if (err) { From 6266dc11a943541becae686526dd81f6f1045a51 Mon Sep 17 00:00:00 2001 From: Dominik Ermel Date: Mon, 25 Mar 2024 13:08:07 +0000 Subject: [PATCH 1323/2402] drivers: flash: spi nor: Fix missing init of hold pin There has been missing line initializing the hold pin, which caused SPI NOR device init to fail with -ENODEV, if property defining such pin has been present in device definition. Fixes #70661 Signed-off-by: Dominik Ermel --- drivers/flash/spi_nor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/flash/spi_nor.c b/drivers/flash/spi_nor.c index b30dd171b9b..3e29e06c3f6 100644 --- a/drivers/flash/spi_nor.c +++ b/drivers/flash/spi_nor.c @@ -1683,7 +1683,8 @@ static const struct flash_driver_api spi_nor_api = { IF_ENABLED(ANY_INST_HAS_DPD_WAKEUP_SEQUENCE, (INIT_WAKEUP_SEQ_PARAMS(idx),)) \ IF_ENABLED(ANY_INST_HAS_MXICY_MX25R_POWER_MODE, (INIT_MXICY_MX25R_POWER_MODE(idx),)) \ IF_ENABLED(ANY_INST_HAS_RESET_GPIOS, (INIT_RESET_GPIOS(idx),)) \ - IF_ENABLED(ANY_INST_HAS_WP_GPIOS, (INIT_WP_GPIOS(idx),)) + IF_ENABLED(ANY_INST_HAS_WP_GPIOS, (INIT_WP_GPIOS(idx),)) \ + IF_ENABLED(ANY_INST_HAS_HOLD_GPIOS, (INIT_HOLD_GPIOS(idx),)) #define GENERATE_CONFIG_STRUCT(idx) \ static const struct spi_nor_config spi_nor_##idx##_config = { \ From bcd1d193221ec79015c4f8e6b571c92a6de82a49 Mon Sep 17 00:00:00 2001 From: Simon Hein Date: Fri, 8 Mar 2024 12:00:10 +0100 Subject: [PATCH 1324/2402] kernel: add closing comments to config endifs Add a closing comment to the endif with the configuration information to which the endif belongs too. To make the code more clearer if the configs need adaptions. Signed-off-by: Simon Hein --- include/zephyr/kernel/internal/mm.h | 16 +-- include/zephyr/kernel/internal/smp.h | 2 +- include/zephyr/kernel/mm.h | 2 +- include/zephyr/kernel/mm/demand_paging.h | 2 +- include/zephyr/kernel/obj_core.h | 8 +- include/zephyr/kernel/stats.h | 4 +- include/zephyr/kernel/thread.h | 56 ++++----- include/zephyr/kernel/thread_stack.h | 14 +-- kernel/atomic_c.c | 4 +- kernel/banner.c | 6 +- kernel/condvar.c | 14 +-- kernel/cpu_mask.c | 6 +- kernel/dynamic.c | 10 +- kernel/events.c | 20 ++-- kernel/fatal.c | 2 +- kernel/idle.c | 8 +- kernel/include/kernel_arch_interface.h | 4 +- kernel/include/kernel_internal.h | 24 ++-- kernel/include/kernel_offsets.h | 20 ++-- kernel/include/ksched.h | 6 +- kernel/include/kswap.h | 26 ++-- kernel/include/kthread.h | 6 +- kernel/include/mmu.h | 6 +- kernel/include/priority_q.h | 2 +- kernel/include/timeout_q.h | 2 +- kernel/init.c | 52 ++++---- kernel/irq_offload.c | 2 +- kernel/mailbox.c | 14 +-- kernel/mem_domain.c | 14 +-- kernel/mem_slab.c | 28 ++--- kernel/mempool.c | 2 +- kernel/mmu.c | 28 ++--- kernel/msg_q.c | 20 ++-- kernel/mutex.c | 12 +- kernel/obj_core.c | 4 +- kernel/pipes.c | 24 ++-- kernel/poll.c | 16 +-- kernel/queue.c | 14 +-- kernel/sched.c | 146 ++++++++++++----------- kernel/sem.c | 16 +-- kernel/smp.c | 8 +- kernel/stack.c | 12 +- kernel/thread.c | 90 +++++++------- kernel/timeout.c | 10 +- kernel/timer.c | 16 +-- kernel/usage.c | 38 +++--- kernel/userspace.c | 22 ++-- kernel/userspace_handler.c | 2 +- kernel/work.c | 8 +- 49 files changed, 437 insertions(+), 431 deletions(-) diff --git a/include/zephyr/kernel/internal/mm.h b/include/zephyr/kernel/internal/mm.h index b6bcd1aa3b1..abb393e3d67 100644 --- a/include/zephyr/kernel/internal/mm.h +++ b/include/zephyr/kernel/internal/mm.h @@ -39,7 +39,7 @@ (CONFIG_SRAM_BASE_ADDRESS + CONFIG_SRAM_OFFSET)) #else #define Z_MEM_VM_OFFSET 0 -#endif +#endif /* CONFIG_MMU */ #define Z_MEM_PHYS_ADDR(virt) ((virt) - Z_MEM_VM_OFFSET) #define Z_MEM_VIRT_ADDR(phys) ((phys) + Z_MEM_VM_OFFSET) @@ -70,26 +70,26 @@ static inline uintptr_t z_mem_phys_addr(void *virt) __ASSERT( #if CONFIG_KERNEL_VM_BASE != 0 (addr >= CONFIG_KERNEL_VM_BASE) && -#endif +#endif /* CONFIG_KERNEL_VM_BASE != 0 */ #if (CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_SIZE) != 0 (addr < (CONFIG_KERNEL_VM_BASE + (CONFIG_KERNEL_VM_SIZE))), #else false, -#endif +#endif /* CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_SIZE != 0 */ "address %p not in permanent mappings", virt); #else /* Should be identity-mapped */ __ASSERT( #if CONFIG_SRAM_BASE_ADDRESS != 0 (addr >= CONFIG_SRAM_BASE_ADDRESS) && -#endif +#endif /* CONFIG_SRAM_BASE_ADDRESS != 0 */ #if (CONFIG_SRAM_BASE_ADDRESS + (CONFIG_SRAM_SIZE * 1024UL)) != 0 (addr < (CONFIG_SRAM_BASE_ADDRESS + (CONFIG_SRAM_SIZE * 1024UL))), #else false, -#endif +#endif /* (CONFIG_SRAM_BASE_ADDRESS + (CONFIG_SRAM_SIZE * 1024UL)) != 0 */ "physical address 0x%lx not in RAM", (unsigned long)addr); #endif /* CONFIG_MMU */ @@ -111,15 +111,15 @@ static inline void *z_mem_virt_addr(uintptr_t phys) __ASSERT( #if CONFIG_SRAM_BASE_ADDRESS != 0 (phys >= CONFIG_SRAM_BASE_ADDRESS) && -#endif +#endif /* CONFIG_SRAM_BASE_ADDRESS != 0 */ #if (CONFIG_SRAM_BASE_ADDRESS + (CONFIG_SRAM_SIZE * 1024UL)) != 0 (phys < (CONFIG_SRAM_BASE_ADDRESS + (CONFIG_SRAM_SIZE * 1024UL))), #else false, -#endif +#endif /* (CONFIG_SRAM_BASE_ADDRESS + (CONFIG_SRAM_SIZE * 1024UL)) != 0 */ "physical address 0x%lx not in RAM", (unsigned long)phys); -#endif +#endif /* CONFIG_KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK */ /* TODO add assertion that this page frame is pinned to boot mapping, * the above check won't be sufficient with demand paging diff --git a/include/zephyr/kernel/internal/smp.h b/include/zephyr/kernel/internal/smp.h index e2b3ae15aec..98c1391e266 100644 --- a/include/zephyr/kernel/internal/smp.h +++ b/include/zephyr/kernel/internal/smp.h @@ -8,4 +8,4 @@ void z_sched_ipi(void); -#endif +#endif /* ZEPHYR_INCLUDE_KERNEL_INTERNAL_SMP_H_ */ diff --git a/include/zephyr/kernel/mm.h b/include/zephyr/kernel/mm.h index 715bc94021f..b391bdbab19 100644 --- a/include/zephyr/kernel/mm.h +++ b/include/zephyr/kernel/mm.h @@ -11,7 +11,7 @@ #include #if defined(CONFIG_ARM_MMU) && defined(CONFIG_ARM64) #include -#endif +#endif /* CONFIG_ARM_MMU && CONFIG_ARM64 */ #include diff --git a/include/zephyr/kernel/mm/demand_paging.h b/include/zephyr/kernel/mm/demand_paging.h index 10412d3a766..35dae90a235 100644 --- a/include/zephyr/kernel/mm/demand_paging.h +++ b/include/zephyr/kernel/mm/demand_paging.h @@ -47,7 +47,7 @@ struct k_mem_paging_stats_t { #if !defined(CONFIG_DEMAND_PAGING_ALLOW_IRQ) || defined(__DOXYGEN__) /** Number of page faults while in ISR */ unsigned long in_isr; -#endif +#endif /* !CONFIG_DEMAND_PAGING_ALLOW_IRQ */ } pagefaults; struct { diff --git a/include/zephyr/kernel/obj_core.h b/include/zephyr/kernel/obj_core.h index 1dedccbfc4f..c6c484f8333 100644 --- a/include/zephyr/kernel/obj_core.h +++ b/include/zephyr/kernel/obj_core.h @@ -76,7 +76,7 @@ struct k_obj_core; #else #define K_OBJ_CORE_INIT(objp, type) do { } while (0) #define K_OBJ_CORE_LINK(objp) do { } while (0) -#endif +#endif /* CONFIG_OBJ_CORE */ /** * INTERNAL_HIDDEN @endcond @@ -114,7 +114,7 @@ struct k_obj_type { #ifdef CONFIG_OBJ_CORE_STATS /** Pointer to object core statistics descriptor */ struct k_obj_core_stats_desc *stats_desc; -#endif +#endif /* CONFIG_OBJ_CORE_STATS */ }; /** Object core structure */ @@ -123,7 +123,7 @@ struct k_obj_core { struct k_obj_type *type; /**< Object type to which object belongs */ #ifdef CONFIG_OBJ_CORE_STATS void *stats; /**< Pointer to kernel object's stats */ -#endif +#endif /* CONFIG_OBJ_CORE_STATS */ }; /** @@ -280,7 +280,7 @@ static inline void k_obj_core_stats_init(struct k_obj_core *obj_core, { obj_core->stats = stats; } -#endif +#endif /* CONFIG_OBJ_CORE_STATS */ /** * @brief Register kernel object for gathering statistics diff --git a/include/zephyr/kernel/stats.h b/include/zephyr/kernel/stats.h index 812c963751f..7a2873c4de2 100644 --- a/include/zephyr/kernel/stats.h +++ b/include/zephyr/kernel/stats.h @@ -26,8 +26,8 @@ struct k_cycle_stats { uint64_t longest; /**< \# of cycles in longest usage window */ uint32_t num_windows; /**< \# of usage windows */ /** @} */ -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ bool track_usage; /**< true if gathering usage stats */ }; -#endif +#endif /* ZEPHYR_INCLUDE_KERNEL_STATS_H_ */ diff --git a/include/zephyr/kernel/thread.h b/include/zephyr/kernel/thread.h index c319404f44f..062e4a36ecb 100644 --- a/include/zephyr/kernel/thread.h +++ b/include/zephyr/kernel/thread.h @@ -9,7 +9,7 @@ #ifdef CONFIG_DEMAND_PAGING_THREAD_STATS #include -#endif +#endif /* CONFIG_DEMAND_PAGING_THREAD_STATS */ #include #include @@ -38,7 +38,7 @@ struct __thread_entry { void *parameter2; void *parameter3; }; -#endif +#endif /* CONFIG_THREAD_MONITOR */ struct k_thread; @@ -96,14 +96,14 @@ struct _thread_base { #else /* Little Endian */ int8_t prio; uint8_t sched_locked; -#endif +#endif /* CONFIG_BIG_ENDIAN */ }; uint16_t preempt; }; #ifdef CONFIG_SCHED_DEADLINE int prio_deadline; -#endif +#endif /* CONFIG_SCHED_DEADLINE */ uint32_t order_key; @@ -117,7 +117,7 @@ struct _thread_base { /* Recursive count of irq_lock() calls */ uint8_t global_lock_count; -#endif +#endif /* CONFIG_SMP */ #ifdef CONFIG_SCHED_CPU_MASK /* "May run on" bits for each CPU */ @@ -125,7 +125,7 @@ struct _thread_base { uint8_t cpu_mask; #else uint16_t cpu_mask; -#endif +#endif /* CONFIG_MP_MAX_NUM_CPUS */ #endif /* CONFIG_SCHED_CPU_MASK */ /* data returned by APIs */ @@ -134,17 +134,17 @@ struct _thread_base { #ifdef CONFIG_SYS_CLOCK_EXISTS /* this thread's entry in a timeout queue */ struct _timeout timeout; -#endif +#endif /* CONFIG_SYS_CLOCK_EXISTS */ #ifdef CONFIG_TIMESLICE_PER_THREAD int32_t slice_ticks; k_thread_timeslice_fn_t slice_expired; void *slice_data; -#endif +#endif /* CONFIG_TIMESLICE_PER_THREAD */ #ifdef CONFIG_SCHED_THREAD_USAGE struct k_cycle_stats usage; /* Track thread usage statistics */ -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE */ }; typedef struct _thread_base _thread_base_t; @@ -190,9 +190,9 @@ struct _mem_domain_info { struct _thread_userspace_local_data { #if defined(CONFIG_ERRNO) && !defined(CONFIG_ERRNO_IN_TLS) && !defined(CONFIG_LIBC_ERRNO) int errno_var; -#endif +#endif /* CONFIG_ERRNO && !CONFIG_ERRNO_IN_TLS && !CONFIG_LIBC_ERRNO */ }; -#endif +#endif /* CONFIG_THREAD_USERSPACE_LOCAL_DATA */ typedef struct k_thread_runtime_stats { #ifdef CONFIG_SCHED_THREAD_USAGE @@ -203,7 +203,7 @@ typedef struct k_thread_runtime_stats { * as the total # of non-idle cycles. In the context of CPU statistics, * it refers to the sum of non-idle + idle cycles. */ -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE */ #ifdef CONFIG_SCHED_THREAD_USAGE_ANALYSIS /* @@ -216,7 +216,7 @@ typedef struct k_thread_runtime_stats { uint64_t current_cycles; /* current # of non-idle cycles */ uint64_t peak_cycles; /* peak # of non-idle cycles */ uint64_t average_cycles; /* average # of non-idle cycles */ -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ #ifdef CONFIG_SCHED_THREAD_USAGE_ALL /* @@ -226,7 +226,7 @@ typedef struct k_thread_runtime_stats { */ uint64_t idle_cycles; -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ALL */ #if defined(__cplusplus) && !defined(CONFIG_SCHED_THREAD_USAGE) && \ !defined(CONFIG_SCHED_THREAD_USAGE_ANALYSIS) && !defined(CONFIG_SCHED_THREAD_USAGE_ALL) @@ -262,7 +262,7 @@ struct k_thread { #if defined(CONFIG_POLL) struct z_poller poller; -#endif +#endif /* CONFIG_POLL */ #if defined(CONFIG_EVENTS) struct k_thread *next_event_link; @@ -272,7 +272,7 @@ struct k_thread { /** true if timeout should not wake the thread */ bool no_wake_on_timeout; -#endif +#endif /* CONFIG_EVENTS */ #if defined(CONFIG_THREAD_MONITOR) /** thread entry and parameters description */ @@ -280,28 +280,28 @@ struct k_thread { /** next item in list of all threads */ struct k_thread *next_thread; -#endif +#endif /* CONFIG_THREAD_MONITOR */ #if defined(CONFIG_THREAD_NAME) /** Thread name */ char name[CONFIG_THREAD_MAX_NAME_LEN]; -#endif +#endif /* CONFIG_THREAD_NAME */ #ifdef CONFIG_THREAD_CUSTOM_DATA /** crude thread-local storage */ void *custom_data; -#endif +#endif /* CONFIG_THREAD_CUSTOM_DATA */ #ifdef CONFIG_THREAD_USERSPACE_LOCAL_DATA struct _thread_userspace_local_data *userspace_local_data; -#endif +#endif /* CONFIG_THREAD_USERSPACE_LOCAL_DATA */ #if defined(CONFIG_ERRNO) && !defined(CONFIG_ERRNO_IN_TLS) && !defined(CONFIG_LIBC_ERRNO) #ifndef CONFIG_USERSPACE /** per-thread errno variable */ int errno_var; -#endif -#endif +#endif /* CONFIG_USERSPACE */ +#endif /* CONFIG_ERRNO && !CONFIG_ERRNO_IN_TLS && !CONFIG_LIBC_ERRNO */ #if defined(CONFIG_THREAD_STACK_INFO) /** Stack Info */ @@ -328,7 +328,7 @@ struct k_thread { /** Context handle returned via arch_switch() */ void *switch_handle; -#endif +#endif /* CONFIG_USE_SWITCH */ /** resource pool */ struct k_heap *resource_pool; @@ -340,21 +340,21 @@ struct k_thread { #ifdef CONFIG_DEMAND_PAGING_THREAD_STATS /** Paging statistics */ struct k_mem_paging_stats_t paging_stats; -#endif +#endif /* CONFIG_DEMAND_PAGING_THREAD_STATS */ #ifdef CONFIG_PIPES /** Pipe descriptor used with blocking k_pipe operations */ struct _pipe_desc pipe_desc; -#endif +#endif /* CONFIG_PIPES */ #ifdef CONFIG_OBJ_CORE_THREAD struct k_obj_core obj_core; -#endif +#endif /* CONFIG_OBJ_CORE_THREAD */ #ifdef CONFIG_SMP /** threads waiting in k_thread_suspend() */ _wait_q_t halt_queue; -#endif +#endif /* CONFIG_SMP */ /** arch-specifics: must always be at the end */ struct _thread_arch arch; @@ -363,4 +363,4 @@ struct k_thread { typedef struct k_thread _thread_t; typedef struct k_thread *k_tid_t; -#endif +#endif /* ZEPHYR_INCLUDE_KERNEL_THREAD_H_ */ diff --git a/include/zephyr/kernel/thread_stack.h b/include/zephyr/kernel/thread_stack.h index 133f055c08f..1cfab4b1c15 100644 --- a/include/zephyr/kernel/thread_stack.h +++ b/include/zephyr/kernel/thread_stack.h @@ -92,7 +92,7 @@ static inline char *z_stack_ptr_align(char *ptr) #define K_KERNEL_STACK_RESERVED ((size_t)ARCH_KERNEL_STACK_RESERVED) #else #define K_KERNEL_STACK_RESERVED ((size_t)0) -#endif +#endif /* ARCH_KERNEL_STACK_RESERVED */ #define Z_KERNEL_STACK_SIZE_ADJUST(size) (ROUND_UP(size, \ ARCH_STACK_PTR_ALIGN) + \ @@ -102,7 +102,7 @@ static inline char *z_stack_ptr_align(char *ptr) #define Z_KERNEL_STACK_OBJ_ALIGN ARCH_KERNEL_STACK_OBJ_ALIGN #else #define Z_KERNEL_STACK_OBJ_ALIGN ARCH_STACK_PTR_ALIGN -#endif +#endif /* ARCH_KERNEL_STACK_OBJ_ALIGN */ #define Z_KERNEL_STACK_LEN(size) \ ROUND_UP(Z_KERNEL_STACK_SIZE_ADJUST(size), Z_KERNEL_STACK_OBJ_ALIGN) @@ -232,7 +232,7 @@ static inline char *z_stack_ptr_align(char *ptr) #else #define K_KERNEL_PINNED_STACK_DEFINE(sym, size) \ Z_KERNEL_STACK_DEFINE_IN(sym, size, __kstackmem) -#endif +#endif /* CONFIG_LINKER_USE_PINNED_SECTION */ /** * @brief Define a toplevel array of kernel stack memory regions @@ -265,7 +265,7 @@ static inline char *z_stack_ptr_align(char *ptr) #else #define K_KERNEL_PINNED_STACK_ARRAY_DEFINE(sym, nmemb, size) \ Z_KERNEL_STACK_ARRAY_DEFINE_IN(sym, nmemb, size, __kstackmem) -#endif +#endif /* CONFIG_LINKER_USE_PINNED_SECTION */ /** * @brief Define an embedded stack memory region @@ -320,7 +320,7 @@ static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) #define K_THREAD_STACK_RESERVED ((size_t)(ARCH_THREAD_STACK_RESERVED)) #else #define K_THREAD_STACK_RESERVED ((size_t)0U) -#endif +#endif /* ARCH_THREAD_STACK_RESERVED */ /** * @brief Properly align the lowest address of a stack object @@ -553,7 +553,7 @@ static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) #else #define K_THREAD_PINNED_STACK_DEFINE(sym, size) \ K_THREAD_STACK_DEFINE(sym, size) -#endif +#endif /* CONFIG_LINKER_USE_PINNED_SECTION */ /** * @brief Calculate size of stacks to be allocated in a stack array @@ -611,7 +611,7 @@ static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) #else #define K_THREAD_PINNED_STACK_ARRAY_DEFINE(sym, nmemb, size) \ K_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) -#endif +#endif /* CONFIG_LINKER_USE_PINNED_SECTION */ /** * @brief Define an embedded stack memory region diff --git a/kernel/atomic_c.c b/kernel/atomic_c.c index 1790953cb11..c873192af74 100644 --- a/kernel/atomic_c.c +++ b/kernel/atomic_c.c @@ -56,7 +56,7 @@ static struct k_spinlock lock; #else #define ATOMIC_SYSCALL_HANDLER_TARGET(name) #define ATOMIC_SYSCALL_HANDLER_TARGET_VALUE(name) -#endif +#endif /* CONFIG_USERSPACE */ /** * @@ -411,4 +411,4 @@ ATOMIC_SYSCALL_HANDLER_TARGET_VALUE(atomic_nand); #include #include #include -#endif +#endif /* CONFIG_USERSPACE */ diff --git a/kernel/banner.c b/kernel/banner.c index a9925ea7b54..5274c3e0d6f 100644 --- a/kernel/banner.c +++ b/kernel/banner.c @@ -14,15 +14,15 @@ #define BANNER_POSTFIX " (delayed boot " DELAY_STR "ms)" #else #define BANNER_POSTFIX "" -#endif +#endif /* defined(CONFIG_BOOT_DELAY) && (CONFIG_BOOT_DELAY > 0) */ #ifndef BANNER_VERSION #ifdef BUILD_VERSION #define BANNER_VERSION STRINGIFY(BUILD_VERSION) #else #define BANNER_VERSION KERNEL_VERSION_STRING -#endif -#endif +#endif /* BUILD_VERSION */ +#endif /* !BANNER_VERSION */ void boot_banner(void) { diff --git a/kernel/condvar.c b/kernel/condvar.c index 1aa26e937d3..9d8ca7a5bc8 100644 --- a/kernel/condvar.c +++ b/kernel/condvar.c @@ -14,7 +14,7 @@ #ifdef CONFIG_OBJ_CORE_CONDVAR static struct k_obj_type obj_type_condvar; -#endif +#endif /* CONFIG_OBJ_CORE_CONDVAR */ static struct k_spinlock lock; @@ -25,7 +25,7 @@ int z_impl_k_condvar_init(struct k_condvar *condvar) #ifdef CONFIG_OBJ_CORE_CONDVAR k_obj_core_init_and_link(K_OBJ_CORE(condvar), &obj_type_condvar); -#endif +#endif /* CONFIG_OBJ_CORE_CONDVAR */ SYS_PORT_TRACING_OBJ_INIT(k_condvar, condvar, 0); @@ -39,7 +39,7 @@ int z_vrfy_k_condvar_init(struct k_condvar *condvar) return z_impl_k_condvar_init(condvar); } #include -#endif +#endif /* CONFIG_USERSPACE */ int z_impl_k_condvar_signal(struct k_condvar *condvar) { @@ -71,7 +71,7 @@ int z_vrfy_k_condvar_signal(struct k_condvar *condvar) return z_impl_k_condvar_signal(condvar); } #include -#endif +#endif /* CONFIG_USERSPACE */ int z_impl_k_condvar_broadcast(struct k_condvar *condvar) { @@ -104,7 +104,7 @@ int z_vrfy_k_condvar_broadcast(struct k_condvar *condvar) return z_impl_k_condvar_broadcast(condvar); } #include -#endif +#endif /* CONFIG_USERSPACE */ int z_impl_k_condvar_wait(struct k_condvar *condvar, struct k_mutex *mutex, k_timeout_t timeout) @@ -133,7 +133,7 @@ int z_vrfy_k_condvar_wait(struct k_condvar *condvar, struct k_mutex *mutex, return z_impl_k_condvar_wait(condvar, mutex, timeout); } #include -#endif +#endif /* CONFIG_USERSPACE */ #ifdef CONFIG_OBJ_CORE_CONDVAR static int init_condvar_obj_core_list(void) @@ -155,4 +155,4 @@ static int init_condvar_obj_core_list(void) SYS_INIT(init_condvar_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_CONDVAR */ diff --git a/kernel/cpu_mask.c b/kernel/cpu_mask.c index 4efeb29035e..4f42228f3ed 100644 --- a/kernel/cpu_mask.c +++ b/kernel/cpu_mask.c @@ -13,7 +13,7 @@ extern struct k_spinlock _sched_spinlock; # ifdef CONFIG_SMP /* Right now we use a two byte for this mask */ BUILD_ASSERT(CONFIG_MP_MAX_NUM_CPUS <= 16, "Too many CPUs for mask word"); -# endif +# endif /* CONFIG_SMP */ static int cpu_mask_mod(k_tid_t thread, uint32_t enable_mask, uint32_t disable_mask) @@ -23,7 +23,7 @@ static int cpu_mask_mod(k_tid_t thread, uint32_t enable_mask, uint32_t disable_m #ifdef CONFIG_SCHED_CPU_MASK_PIN_ONLY __ASSERT(z_is_thread_prevented_from_running(thread), "Running threads cannot change CPU pin"); -#endif +#endif /* CONFIG_SCHED_CPU_MASK_PIN_ONLY */ K_SPINLOCK(&_sched_spinlock) { if (z_is_thread_prevented_from_running(thread)) { @@ -39,7 +39,7 @@ static int cpu_mask_mod(k_tid_t thread, uint32_t enable_mask, uint32_t disable_m __ASSERT((m == 0) || ((m & (m - 1)) == 0), "Only one CPU allowed in mask when PIN_ONLY"); -#endif +#endif /* defined(CONFIG_ASSERT) && defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY) */ return ret; } diff --git a/kernel/dynamic.c b/kernel/dynamic.c index b9d34cbb52c..66cd99853c0 100644 --- a/kernel/dynamic.c +++ b/kernel/dynamic.c @@ -20,7 +20,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #define BA_SIZE CONFIG_DYNAMIC_THREAD_POOL_SIZE #else #define BA_SIZE 1 -#endif +#endif /* CONFIG_DYNAMIC_THREAD_POOL_SIZE > 0 */ struct dyn_cb_data { k_tid_t tid; @@ -71,7 +71,7 @@ static k_thread_stack_t *stack_alloc_dyn(size_t size, int flags) * enabled we can't proceed. */ return NULL; -#endif +#endif /* CONFIG_DYNAMIC_OBJECTS */ } return z_thread_stack_alloc_dyn(Z_KERNEL_STACK_OBJ_ALIGN, @@ -106,7 +106,7 @@ static inline k_thread_stack_t *z_vrfy_k_thread_stack_alloc(size_t size, int fla return z_impl_k_thread_stack_alloc(size, flags); } #include -#endif +#endif /* CONFIG_USERSPACE */ static void dyn_cb(const struct k_thread *thread, void *user_data) { @@ -154,7 +154,7 @@ int z_impl_k_thread_stack_free(k_thread_stack_t *stack) } #else k_free(stack); -#endif +#endif /* CONFIG_USERSPACE */ } else { LOG_DBG("Invalid stack %p", stack); return -EINVAL; @@ -169,4 +169,4 @@ static inline int z_vrfy_k_thread_stack_free(k_thread_stack_t *stack) return z_impl_k_thread_stack_free(stack); } #include -#endif +#endif /* CONFIG_USERSPACE */ diff --git a/kernel/events.c b/kernel/events.c index 8cb90dc6160..082f418cbe0 100644 --- a/kernel/events.c +++ b/kernel/events.c @@ -47,7 +47,7 @@ struct event_walk_data { #ifdef CONFIG_OBJ_CORE_EVENT static struct k_obj_type obj_type_event; -#endif +#endif /* CONFIG_OBJ_CORE_EVENT */ void z_impl_k_event_init(struct k_event *event) { @@ -62,7 +62,7 @@ void z_impl_k_event_init(struct k_event *event) #ifdef CONFIG_OBJ_CORE_EVENT k_obj_core_init_and_link(K_OBJ_CORE(event), &obj_type_event); -#endif +#endif /* CONFIG_OBJ_CORE_EVENT */ } #ifdef CONFIG_USERSPACE @@ -72,7 +72,7 @@ void z_vrfy_k_event_init(struct k_event *event) z_impl_k_event_init(event); } #include -#endif +#endif /* CONFIG_USERSPACE */ /** * @brief determine if desired set of events been satisfied @@ -191,7 +191,7 @@ uint32_t z_vrfy_k_event_post(struct k_event *event, uint32_t events) return z_impl_k_event_post(event, events); } #include -#endif +#endif /* CONFIG_USERSPACE */ uint32_t z_impl_k_event_set(struct k_event *event, uint32_t events) { @@ -205,7 +205,7 @@ uint32_t z_vrfy_k_event_set(struct k_event *event, uint32_t events) return z_impl_k_event_set(event, events); } #include -#endif +#endif /* CONFIG_USERSPACE */ uint32_t z_impl_k_event_set_masked(struct k_event *event, uint32_t events, uint32_t events_mask) @@ -221,7 +221,7 @@ uint32_t z_vrfy_k_event_set_masked(struct k_event *event, uint32_t events, return z_impl_k_event_set_masked(event, events, events_mask); } #include -#endif +#endif /* CONFIG_USERSPACE */ uint32_t z_impl_k_event_clear(struct k_event *event, uint32_t events) { @@ -235,7 +235,7 @@ uint32_t z_vrfy_k_event_clear(struct k_event *event, uint32_t events) return z_impl_k_event_clear(event, events); } #include -#endif +#endif /* CONFIG_USERSPACE */ static uint32_t k_event_wait_internal(struct k_event *event, uint32_t events, unsigned int options, k_timeout_t timeout) @@ -321,7 +321,7 @@ uint32_t z_vrfy_k_event_wait(struct k_event *event, uint32_t events, return z_impl_k_event_wait(event, events, reset, timeout); } #include -#endif +#endif /* CONFIG_USERSPACE */ /** * Wait for all of the specified events @@ -343,7 +343,7 @@ uint32_t z_vrfy_k_event_wait_all(struct k_event *event, uint32_t events, return z_impl_k_event_wait_all(event, events, reset, timeout); } #include -#endif +#endif /* CONFIG_USERSPACE */ #ifdef CONFIG_OBJ_CORE_EVENT static int init_event_obj_core_list(void) @@ -364,4 +364,4 @@ static int init_event_obj_core_list(void) SYS_INIT(init_event_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_EVENT */ diff --git a/kernel/fatal.c b/kernel/fatal.c index dae2eb60950..caee224bf5f 100644 --- a/kernel/fatal.c +++ b/kernel/fatal.c @@ -108,7 +108,7 @@ void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf) if ((esf != NULL) && arch_is_in_nested_exception(esf)) { LOG_ERR("Fault during interrupt handling\n"); } -#endif +#endif /* CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION */ LOG_ERR("Current thread: %p (%s)", thread, thread_name_get(thread)); diff --git a/kernel/idle.c b/kernel/idle.c index ae39f710b07..bef193aa8e8 100644 --- a/kernel/idle.c +++ b/kernel/idle.c @@ -30,7 +30,7 @@ void z_pm_save_idle_exit(void) #endif /* CONFIG_PM */ #ifdef CONFIG_SYS_CLOCK_EXISTS sys_clock_idle_exit(); -#endif +#endif /* CONFIG_SYS_CLOCK_EXISTS */ } void idle(void *unused1, void *unused2, void *unused3) @@ -87,7 +87,7 @@ void idle(void *unused1, void *unused2, void *unused3) } #else k_cpu_idle(); -#endif +#endif /* CONFIG_PM */ #if !defined(CONFIG_PREEMPT_ENABLED) # if !defined(CONFIG_USE_SWITCH) || defined(CONFIG_SPARC) @@ -103,8 +103,8 @@ void idle(void *unused1, void *unused2, void *unused3) if (_kernel.ready_q.cache != _current) { z_swap_unlocked(); } -# endif -#endif +# endif /* !defined(CONFIG_USE_SWITCH) || defined(CONFIG_SPARC) */ +#endif /* !defined(CONFIG_PREEMPT_ENABLED) */ } } diff --git a/kernel/include/kernel_arch_interface.h b/kernel/include/kernel_arch_interface.h index a20c7a706bb..18944dc78a0 100644 --- a/kernel/include/kernel_arch_interface.h +++ b/kernel/include/kernel_arch_interface.h @@ -37,7 +37,7 @@ extern "C" { * @param usec_to_wait Wait period, in microseconds */ void arch_busy_wait(uint32_t usec_to_wait); -#endif +#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */ /** @} */ @@ -154,7 +154,7 @@ int arch_swap(unsigned int key); */ static ALWAYS_INLINE void arch_thread_return_value_set(struct k_thread *thread, unsigned int value); -#endif /* CONFIG_USE_SWITCH i*/ +#endif /* CONFIG_USE_SWITCH */ #ifdef CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN /** diff --git a/kernel/include/kernel_internal.h b/kernel/include/kernel_internal.h index 34ff4c0f883..a5e69b8935b 100644 --- a/kernel/include/kernel_internal.h +++ b/kernel/include/kernel_internal.h @@ -43,7 +43,7 @@ static inline void z_data_copy(void) { /* Do nothing */ } -#endif +#endif /* CONFIG_XIP */ #ifdef CONFIG_LINKER_USE_BOOT_SECTION void z_bss_zero_boot(void); @@ -52,7 +52,7 @@ static inline void z_bss_zero_boot(void) { /* Do nothing */ } -#endif +#endif /* CONFIG_LINKER_USE_BOOT_SECTION */ #ifdef CONFIG_LINKER_USE_PINNED_SECTION void z_bss_zero_pinned(void); @@ -61,7 +61,7 @@ static inline void z_bss_zero_pinned(void) { /* Do nothing */ } -#endif +#endif /* CONFIG_LINKER_USE_PINNED_SECTION */ FUNC_NORETURN void z_cstart(void); @@ -135,27 +135,27 @@ z_thread_return_value_set_with_data(struct k_thread *thread, extern void z_smp_init(void); #ifdef CONFIG_SYS_CLOCK_EXISTS extern void smp_timer_init(void); -#endif -#endif +#endif /* CONFIG_SYS_CLOCK_EXISTS */ +#endif /* CONFIG_SMP */ extern void z_early_rand_get(uint8_t *buf, size_t length); #if CONFIG_STACK_POINTER_RANDOM extern int z_stack_adjust_initialized; -#endif +#endif /* CONFIG_STACK_POINTER_RANDOM */ extern struct k_thread z_main_thread; #ifdef CONFIG_MULTITHREADING extern struct k_thread z_idle_threads[CONFIG_MP_MAX_NUM_CPUS]; -#endif +#endif /* CONFIG_MULTITHREADING */ K_KERNEL_PINNED_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, CONFIG_ISR_STACK_SIZE); #ifdef CONFIG_GEN_PRIV_STACKS extern uint8_t *z_priv_stack_find(k_thread_stack_t *stack); -#endif +#endif /* CONFIG_GEN_PRIV_STACKS */ /* Calculate stack usage. */ int z_stack_space_get(const uint8_t *stack_start, size_t size, size_t *unused_ptr); @@ -189,7 +189,7 @@ struct gdb_ctx; * and synchronously communicate with gdb on host. */ extern int z_gdb_main_loop(struct gdb_ctx *ctx); -#endif +#endif /* CONFIG_GDBSTUB */ #ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING void z_thread_mark_switched_in(void); @@ -263,7 +263,7 @@ bool pm_system_suspend(int32_t ticks); */ void pm_system_resume(void); -#endif +#endif /* CONFIG_PM */ #ifdef CONFIG_DEMAND_PAGING_TIMING_HISTOGRAM /** @@ -287,7 +287,7 @@ int z_thread_stats_query(struct k_obj_core *obj_core, void *stats); int z_thread_stats_reset(struct k_obj_core *obj_core); int z_thread_stats_disable(struct k_obj_core *obj_core); int z_thread_stats_enable(struct k_obj_core *obj_core); -#endif +#endif /* CONFIG_OBJ_CORE_STATS_THREAD */ #ifdef CONFIG_OBJ_CORE_STATS_SYSTEM int z_cpu_stats_raw(struct k_obj_core *obj_core, void *stats); @@ -295,7 +295,7 @@ int z_cpu_stats_query(struct k_obj_core *obj_core, void *stats); int z_kernel_stats_raw(struct k_obj_core *obj_core, void *stats); int z_kernel_stats_query(struct k_obj_core *obj_core, void *stats); -#endif +#endif /* CONFIG_OBJ_CORE_STATS_SYSTEM */ #ifdef __cplusplus } diff --git a/kernel/include/kernel_offsets.h b/kernel/include/kernel_offsets.h index 5644dbb1575..41b310a0818 100644 --- a/kernel/include/kernel_offsets.h +++ b/kernel/include/kernel_offsets.h @@ -34,23 +34,23 @@ GEN_OFFSET_SYM(_kernel_t, cpus); #if defined(CONFIG_FPU_SHARING) GEN_OFFSET_SYM(_cpu_t, fp_ctx); -#endif +#endif /* CONFIG_FPU_SHARING */ #ifdef CONFIG_PM GEN_OFFSET_SYM(_kernel_t, idle); -#endif +#endif /* CONFIG_PM */ #ifndef CONFIG_SCHED_CPU_MASK_PIN_ONLY GEN_OFFSET_SYM(_kernel_t, ready_q); -#endif +#endif /* CONFIG_SCHED_CPU_MASK_PIN_ONLY */ #ifndef CONFIG_SMP GEN_OFFSET_SYM(_ready_q_t, cache); -#endif +#endif /* CONFIG_SMP */ #ifdef CONFIG_FPU_SHARING GEN_OFFSET_SYM(_kernel_t, current_fp); -#endif +#endif /* CONFIG_FPU_SHARING */ GEN_OFFSET_SYM(_thread_base_t, user_options); @@ -60,15 +60,15 @@ GEN_OFFSET_SYM(_thread_t, arch); #ifdef CONFIG_USE_SWITCH GEN_OFFSET_SYM(_thread_t, switch_handle); -#endif +#endif /* CONFIG_USE_SWITCH */ #ifdef CONFIG_THREAD_STACK_INFO GEN_OFFSET_SYM(_thread_t, stack_info); -#endif +#endif /* CONFIG_THREAD_STACK_INFO */ #ifdef CONFIG_THREAD_LOCAL_STORAGE GEN_OFFSET_SYM(_thread_t, tls); -#endif +#endif /* CONFIG_THREAD_LOCAL_STORAGE */ GEN_ABSOLUTE_SYM(__z_interrupt_stack_SIZEOF, sizeof(z_interrupt_stacks[0])); @@ -76,12 +76,12 @@ GEN_ABSOLUTE_SYM(__z_interrupt_stack_SIZEOF, sizeof(z_interrupt_stacks[0])); #ifdef CONFIG_DEVICE_DEPS GEN_ABSOLUTE_SYM(_DEVICE_STRUCT_HANDLES_OFFSET, offsetof(struct device, deps)); -#endif +#endif /* CONFIG_DEVICE_DEPS */ #ifdef CONFIG_PM_DEVICE GEN_ABSOLUTE_SYM(_DEVICE_STRUCT_PM_OFFSET, offsetof(struct device, pm)); -#endif +#endif /* CONFIG_PM_DEVICE */ /* member offsets in the pm_device structure. Used in image post-processing */ diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index 5ef720bf54b..74e4bc9f119 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -34,7 +34,7 @@ BUILD_ASSERT(K_LOWEST_APPLICATION_THREAD_PRIO #else #define Z_VALID_PRIO(prio, entry_point) ((prio) == -1) #define Z_ASSERT_VALID_PRIO(prio, entry_point) __ASSERT((prio) == -1, "") -#endif +#endif /* CONFIG_MULTITHREADING */ void z_sched_init(void); void z_move_thread_to_end_of_prio_q(struct k_thread *thread); @@ -80,7 +80,7 @@ static inline bool z_is_idle_thread_object(struct k_thread *thread) return thread->base.is_idle; #else return thread == &z_idle_threads[0]; -#endif +#endif /* CONFIG_SMP */ #else return false; #endif /* CONFIG_MULTITHREADING */ @@ -417,7 +417,7 @@ static inline void z_sched_usage_switch(struct k_thread *thread) #ifdef CONFIG_SCHED_THREAD_USAGE z_sched_usage_stop(); z_sched_usage_start(thread); -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE */ } #endif /* ZEPHYR_KERNEL_INCLUDE_KSCHED_H_ */ diff --git a/kernel/include/kswap.h b/kernel/include/kswap.h index 862969ac79a..d3638b6179a 100644 --- a/kernel/include/kswap.h +++ b/kernel/include/kswap.h @@ -15,7 +15,7 @@ extern void z_check_stack_sentinel(void); #else #define z_check_stack_sentinel() /**/ -#endif +#endif /* CONFIG_STACK_SENTINEL */ extern struct k_spinlock _sched_spinlock; @@ -63,7 +63,7 @@ static inline void z_sched_switch_spin(struct k_thread *thread) * non-null. */ barrier_dmem_fence_full(); -#endif +#endif /* CONFIG_SMP */ } /* New style context switching. arch_switch() is a lower level @@ -99,8 +99,8 @@ static ALWAYS_INLINE unsigned int do_swap(unsigned int key, __ASSERT(arch_irq_unlocked(key) || _current->base.thread_state & (_THREAD_DUMMY | _THREAD_DEAD), "Context switching while holding lock!"); -# endif -#endif +# endif /* CONFIG_ARM64 */ +#endif /* CONFIG_SPIN_VALIDATE */ old_thread = _current; @@ -131,18 +131,18 @@ static ALWAYS_INLINE unsigned int do_swap(unsigned int key, if (!is_spinlock) { z_smp_release_global_lock(new_thread); } -#endif +#endif /* CONFIG_SMP */ z_thread_mark_switched_out(); z_sched_switch_spin(new_thread); _current_cpu->current = new_thread; #ifdef CONFIG_TIMESLICING z_reset_time_slice(new_thread); -#endif +#endif /* CONFIG_TIMESLICING */ #ifdef CONFIG_SPIN_VALIDATE z_spin_lock_set_owner(&_sched_spinlock); -#endif +#endif /* CONFIG_SPIN_VALIDATE */ arch_cohere_stacks(old_thread, NULL, new_thread); @@ -152,7 +152,7 @@ static ALWAYS_INLINE unsigned int do_swap(unsigned int key, * time. See z_sched_switch_spin(). */ z_requeue_current(old_thread); -#endif +#endif /* CONFIG_SMP */ void *newsh = new_thread->switch_handle; if (IS_ENABLED(CONFIG_SMP)) { @@ -241,24 +241,24 @@ static inline void z_dummy_thread_init(struct k_thread *dummy_thread) dummy_thread->base.thread_state = _THREAD_DUMMY; #ifdef CONFIG_SCHED_CPU_MASK dummy_thread->base.cpu_mask = -1; -#endif +#endif /* CONFIG_SCHED_CPU_MASK */ dummy_thread->base.user_options = K_ESSENTIAL; #ifdef CONFIG_THREAD_STACK_INFO dummy_thread->stack_info.start = 0U; dummy_thread->stack_info.size = 0U; -#endif +#endif /* CONFIG_THREAD_STACK_INFO */ #ifdef CONFIG_USERSPACE dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default; -#endif +#endif /* CONFIG_USERSPACE */ #if (K_HEAP_MEM_POOL_SIZE > 0) k_thread_system_pool_assign(dummy_thread); #else dummy_thread->resource_pool = NULL; -#endif +#endif /* K_HEAP_MEM_POOL_SIZE */ #ifdef CONFIG_TIMESLICE_PER_THREAD dummy_thread->base.slice_ticks = 0; -#endif +#endif /* CONFIG_TIMESLICE_PER_THREAD */ _current_cpu->current = dummy_thread; } diff --git a/kernel/include/kthread.h b/kernel/include/kthread.h index 96a41d394a3..423e6989fd4 100644 --- a/kernel/include/kthread.h +++ b/kernel/include/kthread.h @@ -17,7 +17,7 @@ * thread->next_thread (until NULL) */ extern struct k_spinlock z_thread_monitor_lock; -#endif +#endif /* CONFIG_THREAD_MONITOR */ /* clean up when a thread is aborted */ @@ -42,8 +42,8 @@ static inline void thread_schedule_new(struct k_thread *thread, k_timeout_t dela #else ARG_UNUSED(delay); k_thread_start(thread); -#endif +#endif /* CONFIG_SYS_CLOCK_EXISTS */ } -#endif +#endif /* CONFIG_MULTITHREADING */ #endif /* ZEPHYR_KERNEL_INCLUDE_THREAD_H_ */ diff --git a/kernel/include/mmu.h b/kernel/include/mmu.h index 88795560e4c..4650b65bc89 100644 --- a/kernel/include/mmu.h +++ b/kernel/include/mmu.h @@ -54,7 +54,7 @@ #define Z_FREE_VM_START Z_BOOT_PHYS_TO_VIRT(Z_PHYS_RAM_END) #else #define Z_FREE_VM_START Z_KERNEL_VIRT_END -#endif +#endif /* CONFIG_ARCH_MAPS_ALL_RAM */ /* * Macros and data structures for physical page frame accounting, @@ -121,7 +121,7 @@ struct z_page_frame { } __aligned(4); #else } __packed; -#endif +#endif /* CONFIG_XTENSA */ static inline bool z_page_frame_is_pinned(struct z_page_frame *pf) { @@ -237,7 +237,7 @@ void z_page_frames_dump(void); CONFIG_MMU_PAGE_SIZE)) #else #define Z_VM_RESERVED 0 -#endif +#endif /* CONFIG_DEMAND_PAGING */ #ifdef CONFIG_DEMAND_PAGING /* diff --git a/kernel/include/priority_q.h b/kernel/include/priority_q.h index 61496aa47df..e9ea0bff407 100644 --- a/kernel/include/priority_q.h +++ b/kernel/include/priority_q.h @@ -16,7 +16,7 @@ # define _priq_run_best _priq_dumb_mask_best # else # define _priq_run_best z_priq_dumb_best -# endif +# endif /* CONFIG_SCHED_CPU_MASK */ /* Scalable Scheduling */ #elif defined(CONFIG_SCHED_SCALABLE) #define _priq_run_add z_priq_rb_add diff --git a/kernel/include/timeout_q.h b/kernel/include/timeout_q.h index ad9564f05bd..a62242a9f3c 100644 --- a/kernel/include/timeout_q.h +++ b/kernel/include/timeout_q.h @@ -73,7 +73,7 @@ static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t tic ARG_UNUSED(ticks); } -#endif +#endif /* CONFIG_SYS_CLOCK_EXISTS */ #ifdef __cplusplus } diff --git a/kernel/init.c b/kernel/init.c index 81705e87cc5..506e3efbc55 100644 --- a/kernel/init.c +++ b/kernel/init.c @@ -85,7 +85,7 @@ static void z_init_static_threads(void) pos->thread); } } -#endif +#endif /* CONFIG_USERSPACE */ /* * Non-legacy static threads may be started immediately or @@ -128,12 +128,12 @@ enum init_level { INIT_LEVEL_APPLICATION, #ifdef CONFIG_SMP INIT_LEVEL_SMP, -#endif +#endif /* CONFIG_SMP */ }; #ifdef CONFIG_SMP extern const struct init_entry __init_SMP_start[]; -#endif +#endif /* CONFIG_SMP */ /* * storage space for the interrupt stack @@ -173,8 +173,8 @@ static struct k_obj_core_stats_desc kernel_stats_desc = { .disable = NULL, .enable = NULL, }; -#endif -#endif +#endif /* CONFIG_OBJ_CORE_STATS_SYSTEM */ +#endif /* CONFIG_OBJ_CORE_SYSTEM */ /* LCOV_EXCL_START * @@ -245,7 +245,7 @@ void z_bss_zero(void) #ifdef CONFIG_COVERAGE_GCOV z_early_memset(&__gcov_bss_start, 0, ((uintptr_t) &__gcov_bss_end - (uintptr_t) &__gcov_bss_start)); -#endif +#endif /* CONFIG_COVERAGE_GCOV */ } #ifdef CONFIG_LINKER_USE_BOOT_SECTION @@ -279,7 +279,7 @@ void z_bss_zero_boot(void) __boot_func #else __pinned_func -#endif +#endif /* CONFIG_LINKER_USE_BOOT_SECTION */ void z_bss_zero_pinned(void) { z_early_memset(&lnkr_pinned_bss_start, 0, @@ -293,7 +293,7 @@ void z_bss_zero_pinned(void) extern __thread volatile uintptr_t __stack_chk_guard; #else extern volatile uintptr_t __stack_chk_guard; -#endif +#endif /* CONFIG_STACK_CANARIES_TLS */ #endif /* CONFIG_STACK_CANARIES */ /* LCOV_EXCL_STOP */ @@ -322,7 +322,7 @@ static void z_sys_init_run_level(enum init_level level) __init_APPLICATION_start, #ifdef CONFIG_SMP __init_SMP_start, -#endif +#endif /* CONFIG_SMP */ /* End marker */ __init_end, }; @@ -391,13 +391,13 @@ static void bg_thread_main(void *unused1, void *unused2, void *unused3) z_sys_init_run_level(INIT_LEVEL_POST_KERNEL); #if CONFIG_STACK_POINTER_RANDOM z_stack_adjust_initialized = 1; -#endif +#endif /* CONFIG_STACK_POINTER_RANDOM */ boot_banner(); #if defined(CONFIG_CPP) void z_cpp_init_static(void); z_cpp_init_static(); -#endif +#endif /* CONFIG_CPP */ /* Final init level before app starts */ z_sys_init_run_level(INIT_LEVEL_APPLICATION); @@ -406,14 +406,14 @@ static void bg_thread_main(void *unused1, void *unused2, void *unused3) #ifdef CONFIG_KERNEL_COHERENCE __ASSERT_NO_MSG(arch_mem_coherent(&_kernel)); -#endif +#endif /* CONFIG_KERNEL_COHERENCE */ #ifdef CONFIG_SMP if (!IS_ENABLED(CONFIG_SMP_BOOT_DELAY)) { z_smp_init(); } z_sys_init_run_level(INIT_LEVEL_SMP); -#endif +#endif /* CONFIG_SMP */ #ifdef CONFIG_MMU z_mem_manage_boot_finish(); @@ -429,7 +429,7 @@ static void bg_thread_main(void *unused1, void *unused2, void *unused3) #ifdef CONFIG_COVERAGE_DUMP /* Dump coverage data once the main() has exited. */ gcov_coverage_dump(); -#endif +#endif /* CONFIG_COVERAGE_DUMP */ } /* LCOV_EXCL_LINE ... because we just dumped final coverage data */ #if defined(CONFIG_MULTITHREADING) @@ -446,7 +446,7 @@ static void init_idle_thread(int i) snprintk(tname, 8, "idle %02d", i); #else char *tname = "idle"; -#endif +#endif /* CONFIG_MP_MAX_NUM_CPUS */ #else char *tname = NULL; @@ -460,7 +460,7 @@ static void init_idle_thread(int i) #ifdef CONFIG_SMP thread->base.is_idle = 1U; -#endif +#endif /* CONFIG_SMP */ } void z_init_cpu(int id) @@ -524,7 +524,7 @@ static char *prepare_multithreading(void) * to work as intended */ _kernel.ready_q.cache = &z_main_thread; -#endif +#endif /* CONFIG_SMP */ stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack, CONFIG_MAIN_STACK_SIZE, bg_thread_main, NULL, NULL, NULL, @@ -551,7 +551,7 @@ static FUNC_NORETURN void switch_to_main_thread(char *stack_ptr) * will never be rescheduled in. */ z_swap_unlocked(); -#endif +#endif /* CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN */ CODE_UNREACHABLE; /* LCOV_EXCL_LINE */ } #endif /* CONFIG_MULTITHREADING */ @@ -573,7 +573,7 @@ void __weak z_early_rand_get(uint8_t *buf, size_t length) buf += rc; } } -#endif +#endif /* CONFIG_ENTROPY_HAS_DRIVER */ while (length > 0) { uint32_t val; @@ -621,7 +621,7 @@ FUNC_NORETURN void z_cstart(void) struct k_thread dummy_thread; z_dummy_thread_init(&dummy_thread); -#endif +#endif /* CONFIG_MULTITHREADING */ /* do any necessary initialization of static devices */ z_device_state_init(); @@ -640,7 +640,7 @@ FUNC_NORETURN void z_cstart(void) #ifdef CONFIG_TIMING_FUNCTIONS_NEED_AT_BOOT timing_init(); timing_start(); -#endif +#endif /* CONFIG_TIMING_FUNCTIONS_NEED_AT_BOOT */ #ifdef CONFIG_MULTITHREADING switch_to_main_thread(prepare_multithreading()); @@ -661,7 +661,7 @@ FUNC_NORETURN void z_cstart(void) while (true) { } /* LCOV_EXCL_STOP */ -#endif +#endif /* ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING */ #endif /* CONFIG_MULTITHREADING */ /* @@ -683,7 +683,7 @@ static int init_cpu_obj_core_list(void) #ifdef CONFIG_OBJ_CORE_STATS_SYSTEM k_obj_type_stats_init(&obj_type_cpu, &cpu_stats_desc); -#endif +#endif /* CONFIG_OBJ_CORE_STATS_SYSTEM */ return 0; } @@ -697,13 +697,13 @@ static int init_kernel_obj_core_list(void) #ifdef CONFIG_OBJ_CORE_STATS_SYSTEM k_obj_type_stats_init(&obj_type_kernel, &kernel_stats_desc); -#endif +#endif /* CONFIG_OBJ_CORE_STATS_SYSTEM */ k_obj_core_init_and_link(K_OBJ_CORE(&_kernel), &obj_type_kernel); #ifdef CONFIG_OBJ_CORE_STATS_SYSTEM k_obj_core_stats_register(K_OBJ_CORE(&_kernel), _kernel.usage, sizeof(_kernel.usage)); -#endif +#endif /* CONFIG_OBJ_CORE_STATS_SYSTEM */ return 0; } @@ -713,4 +713,4 @@ SYS_INIT(init_cpu_obj_core_list, PRE_KERNEL_1, SYS_INIT(init_kernel_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_SYSTEM */ diff --git a/kernel/irq_offload.c b/kernel/irq_offload.c index e27c210a9d5..f6db81ccf3e 100644 --- a/kernel/irq_offload.c +++ b/kernel/irq_offload.c @@ -19,5 +19,5 @@ void irq_offload(irq_offload_routine_t routine, const void *parameter) k_sem_take(&offload_sem, K_FOREVER); arch_irq_offload(routine, parameter); k_sem_give(&offload_sem); -#endif +#endif /* CONFIG_IRQ_OFFLOAD_NESTED */ } diff --git a/kernel/mailbox.c b/kernel/mailbox.c index 8e796a4a31b..0d690768c21 100644 --- a/kernel/mailbox.c +++ b/kernel/mailbox.c @@ -22,7 +22,7 @@ #ifdef CONFIG_OBJ_CORE_MAILBOX static struct k_obj_type obj_type_mailbox; -#endif +#endif /* CONFIG_OBJ_CORE_MAILBOX */ #if (CONFIG_NUM_MBOX_ASYNC_MSGS > 0) @@ -97,7 +97,7 @@ void k_mbox_init(struct k_mbox *mbox) #ifdef CONFIG_OBJ_CORE_MAILBOX k_obj_core_init_and_link(K_OBJ_CORE(mbox), &obj_type_mailbox); -#endif +#endif /* CONFIG_OBJ_CORE_MAILBOX */ SYS_PORT_TRACING_OBJ_INIT(k_mbox, mbox); } @@ -189,7 +189,7 @@ static void mbox_message_dispose(struct k_mbox_msg *rx_msg) } return; } -#endif +#endif /* CONFIG_NUM_MBOX_ASYNC_MSGS */ /* synchronous send: wake up sending thread */ arch_thread_return_value_set(sending_thread, 0); @@ -256,7 +256,7 @@ static int mbox_message_put(struct k_mbox *mbox, struct k_mbox_msg *tx_msg, z_reschedule(&mbox->lock, key); return 0; } -#endif +#endif /* CONFIG_NUM_MBOX_ASYNC_MSGS */ SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_mbox, message_put, mbox, timeout); /* @@ -286,7 +286,7 @@ static int mbox_message_put(struct k_mbox *mbox, struct k_mbox_msg *tx_msg, k_spin_unlock(&mbox->lock, key); return 0; } -#endif +#endif /* CONFIG_NUM_MBOX_ASYNC_MSGS */ SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_mbox, message_put, mbox, timeout); /* synchronous send: sender waits on tx queue for receiver or timeout */ @@ -335,7 +335,7 @@ void k_mbox_async_put(struct k_mbox *mbox, struct k_mbox_msg *tx_msg, (void)mbox_message_put(mbox, &async->tx_msg, K_FOREVER); SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mbox, async_put, mbox, sem); } -#endif +#endif /* CONFIG_NUM_MBOX_ASYNC_MSGS */ void k_mbox_data_get(struct k_mbox_msg *rx_msg, void *buffer) { @@ -463,4 +463,4 @@ static int init_mailbox_obj_core_list(void) SYS_INIT(init_mailbox_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_MAILBOX */ diff --git a/kernel/mem_domain.c b/kernel/mem_domain.c index fd8f05344a1..5c41c1418fe 100644 --- a/kernel/mem_domain.c +++ b/kernel/mem_domain.c @@ -43,7 +43,7 @@ static bool check_add_partition(struct k_mem_domain *domain, part->start); return false; } -#endif +#endif /* CONFIG_EXECUTE_XOR_WRITE */ if (part->size == 0U) { LOG_ERR("zero sized partition at %p with base 0x%lx", @@ -124,7 +124,7 @@ int k_mem_domain_init(struct k_mem_domain *domain, uint8_t num_parts, ret = -ENOMEM; goto unlock_out; } -#endif +#endif /* CONFIG_ARCH_MEM_DOMAIN_DATA */ if (num_parts != 0U) { uint32_t i; @@ -145,7 +145,7 @@ int k_mem_domain_init(struct k_mem_domain *domain, uint8_t num_parts, CHECKIF(ret2 != 0) { ret = ret2; } -#endif +#endif /* CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API */ } } @@ -200,7 +200,7 @@ int k_mem_domain_add_partition(struct k_mem_domain *domain, #ifdef CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API ret = arch_mem_domain_partition_add(domain, p_idx); -#endif +#endif /* CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API */ unlock_out: k_spin_unlock(&z_mem_domain_lock, key); @@ -242,7 +242,7 @@ int k_mem_domain_remove_partition(struct k_mem_domain *domain, #ifdef CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API ret = arch_mem_domain_partition_remove(domain, p_idx); -#endif +#endif /* CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API */ /* A zero-sized partition denotes it's a free partition */ domain->partitions[p_idx].size = 0U; @@ -271,7 +271,7 @@ static int add_thread_locked(struct k_mem_domain *domain, #ifdef CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API ret = arch_mem_domain_thread_add(thread); -#endif +#endif /* CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API */ return ret; } @@ -287,7 +287,7 @@ static int remove_thread_locked(struct k_thread *thread) #ifdef CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API ret = arch_mem_domain_thread_remove(thread); -#endif +#endif /* CONFIG_ARCH_MEM_DOMAIN_SYNCHRONOUS_API */ return ret; } diff --git a/kernel/mem_slab.c b/kernel/mem_slab.c index 3be1066d2b7..609063ef630 100644 --- a/kernel/mem_slab.c +++ b/kernel/mem_slab.c @@ -55,7 +55,7 @@ static int k_mem_slab_stats_query(struct k_obj_core *obj_core, void *stats) ptr->max_allocated_bytes = slab->info.max_used * slab->info.block_size; #else ptr->max_allocated_bytes = 0; -#endif +#endif /* CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION */ k_spin_unlock(&slab->lock, key); return 0; @@ -73,7 +73,7 @@ static int k_mem_slab_stats_reset(struct k_obj_core *obj_core) #ifdef CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION slab->info.max_used = slab->info.num_used; -#endif +#endif /* CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION */ k_spin_unlock(&slab->lock, key); @@ -89,8 +89,8 @@ static struct k_obj_core_stats_desc mem_slab_stats_desc = { .disable = NULL, .enable = NULL, }; -#endif -#endif +#endif /* CONFIG_OBJ_CORE_STATS_MEM_SLAB */ +#endif /* CONFIG_OBJ_CORE_MEM_SLAB */ /** * @brief Initialize kernel memory slab subsystem. @@ -141,8 +141,8 @@ static int init_mem_slab_obj_core_list(void) offsetof(struct k_mem_slab, obj_core)); #ifdef CONFIG_OBJ_CORE_STATS_MEM_SLAB k_obj_type_stats_init(&obj_type_mem_slab, &mem_slab_stats_desc); -#endif -#endif +#endif /* CONFIG_OBJ_CORE_STATS_MEM_SLAB */ +#endif /* CONFIG_OBJ_CORE_MEM_SLAB */ /* Initialize statically defined mem_slabs */ @@ -158,8 +158,8 @@ static int init_mem_slab_obj_core_list(void) #ifdef CONFIG_OBJ_CORE_STATS_MEM_SLAB k_obj_core_stats_register(K_OBJ_CORE(slab), &slab->info, sizeof(struct k_mem_slab_info)); -#endif -#endif +#endif /* CONFIG_OBJ_CORE_STATS_MEM_SLAB */ +#endif /* CONFIG_OBJ_CORE_MEM_SLAB */ } out: @@ -182,7 +182,7 @@ int k_mem_slab_init(struct k_mem_slab *slab, void *buffer, #ifdef CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION slab->info.max_used = 0U; -#endif +#endif /* CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION */ rc = create_free_list(slab); if (rc < 0) { @@ -191,11 +191,11 @@ int k_mem_slab_init(struct k_mem_slab *slab, void *buffer, #ifdef CONFIG_OBJ_CORE_MEM_SLAB k_obj_core_init_and_link(K_OBJ_CORE(slab), &obj_type_mem_slab); -#endif +#endif /* CONFIG_OBJ_CORE_MEM_SLAB */ #ifdef CONFIG_OBJ_CORE_STATS_MEM_SLAB k_obj_core_stats_register(K_OBJ_CORE(slab), &slab->info, sizeof(struct k_mem_slab_info)); -#endif +#endif /* CONFIG_OBJ_CORE_STATS_MEM_SLAB */ z_waitq_init(&slab->wait_q); k_object_init(slab); @@ -221,7 +221,7 @@ int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout) #ifdef CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION slab->info.max_used = MAX(slab->info.num_used, slab->info.max_used); -#endif +#endif /* CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION */ result = 0; } else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT) || @@ -298,7 +298,7 @@ int k_mem_slab_runtime_stats_get(struct k_mem_slab *slab, struct sys_memory_stat slab->info.block_size; #else stats->max_allocated_bytes = 0; -#endif +#endif /* CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION */ k_spin_unlock(&slab->lock, key); @@ -320,4 +320,4 @@ int k_mem_slab_runtime_stats_reset_max(struct k_mem_slab *slab) return 0; } -#endif +#endif /* CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION */ diff --git a/kernel/mempool.c b/kernel/mempool.c index b3943b52728..13e9c7abec2 100644 --- a/kernel/mempool.c +++ b/kernel/mempool.c @@ -119,7 +119,7 @@ void k_thread_system_pool_assign(struct k_thread *thread) } #else #define _SYSTEM_HEAP NULL -#endif +#endif /* K_HEAP_MEM_POOL_SIZE */ void *z_thread_aligned_alloc(size_t align, size_t size) { diff --git a/kernel/mmu.c b/kernel/mmu.c index eda0c50a255..6cb444f629d 100644 --- a/kernel/mmu.c +++ b/kernel/mmu.c @@ -24,7 +24,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #ifdef CONFIG_DEMAND_PAGING #include -#endif +#endif /* CONFIG_DEMAND_PAGING */ /* * General terminology: @@ -76,7 +76,7 @@ static bool page_frames_initialized; #define COLOR(x) printk(_CONCAT(ANSI_, x)) #else #define COLOR(x) do { } while (false) -#endif +#endif /* COLOR_PAGE_FRAMES */ /* LCOV_EXCL_START */ static void page_frame_dump(struct z_page_frame *pf) @@ -729,7 +729,7 @@ size_t k_mem_free_get(void) } #else ret = z_free_page_count; -#endif +#endif /* CONFIG_DEMAND_PAGING */ k_spin_unlock(&z_mm_lock, key); return ret * (size_t)CONFIG_MMU_PAGE_SIZE; @@ -767,7 +767,7 @@ void z_phys_map(uint8_t **virt_ptr, uintptr_t phys, size_t size, uint32_t flags) #ifndef CONFIG_KERNEL_DIRECT_MAP __ASSERT(!(flags & K_MEM_DIRECT_MAP), "The direct-map is not enabled"); -#endif +#endif /* CONFIG_KERNEL_DIRECT_MAP */ addr_offset = k_mem_region_align(&aligned_phys, &aligned_size, phys, size, CONFIG_MMU_PAGE_SIZE); @@ -959,12 +959,12 @@ void z_mem_manage_init(void) * boot process. Will be un-pinned once boot process completes. */ mark_linker_section_pinned(lnkr_boot_start, lnkr_boot_end, true); -#endif +#endif /* CONFIG_LINKER_USE_BOOT_SECTION */ #ifdef CONFIG_LINKER_USE_PINNED_SECTION /* Pin the page frames correspondng to the pinned symbols */ mark_linker_section_pinned(lnkr_pinned_start, lnkr_pinned_end, true); -#endif +#endif /* CONFIG_LINKER_USE_PINNED_SECTION */ /* Any remaining pages that aren't mapped, reserved, or pinned get * added to the free pages list @@ -979,10 +979,10 @@ void z_mem_manage_init(void) #ifdef CONFIG_DEMAND_PAGING #ifdef CONFIG_DEMAND_PAGING_TIMING_HISTOGRAM z_paging_histogram_init(); -#endif +#endif /* CONFIG_DEMAND_PAGING_TIMING_HISTOGRAM */ k_mem_paging_backing_store_init(); k_mem_paging_eviction_init(); -#endif +#endif /* CONFIG_DEMAND_PAGING */ #if __ASSERT_ON page_frames_initialized = true; #endif @@ -996,7 +996,7 @@ void z_mem_manage_init(void) * memory to be cleared. */ z_bss_zero(); -#endif +#endif /* CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT */ } void z_mem_manage_boot_finish(void) @@ -1006,7 +1006,7 @@ void z_mem_manage_boot_finish(void) * as they don't need to be in memory all the time anymore. */ mark_linker_section_pinned(lnkr_boot_start, lnkr_boot_end, false); -#endif +#endif /* CONFIG_LINKER_USE_BOOT_SECTION */ } #ifdef CONFIG_DEMAND_PAGING @@ -1016,7 +1016,7 @@ struct k_mem_paging_stats_t paging_stats; extern struct k_mem_paging_histogram_t z_paging_histogram_eviction; extern struct k_mem_paging_histogram_t z_paging_histogram_backing_store_page_in; extern struct k_mem_paging_histogram_t z_paging_histogram_backing_store_page_out; -#endif +#endif /* CONFIG_DEMAND_PAGING_STATS */ static inline void do_backing_store_page_in(uintptr_t location) { @@ -1162,7 +1162,7 @@ static int page_frame_prepare_locked(struct z_page_frame *pf, bool *dirty_ptr, __ASSERT(!z_page_frame_is_busy(pf), "page frame 0x%lx is already busy", phys); pf->flags |= Z_PAGE_FRAME_BUSY; -#endif +#endif /* CONFIG_DEMAND_PAGING_ALLOW_IRQ */ /* Update dirty parameter, since we set to true if it wasn't backed * even if otherwise clean */ @@ -1320,7 +1320,7 @@ static inline void paging_stats_faults_inc(struct k_thread *faulting_thread, } #else ARG_UNUSED(faulting_thread); -#endif +#endif /* CONFIG_DEMAND_PAGING_THREAD_STATS */ #ifndef CONFIG_DEMAND_PAGING_ALLOW_IRQ if (k_is_in_isr()) { @@ -1328,7 +1328,7 @@ static inline void paging_stats_faults_inc(struct k_thread *faulting_thread, #ifdef CONFIG_DEMAND_PAGING_THREAD_STATS faulting_thread->paging_stats.pagefaults.in_isr++; -#endif +#endif /* CONFIG_DEMAND_PAGING_THREAD_STATS */ } #endif /* CONFIG_DEMAND_PAGING_ALLOW_IRQ */ #endif /* CONFIG_DEMAND_PAGING_STATS */ diff --git a/kernel/msg_q.c b/kernel/msg_q.c index e11e9a2527e..b315cde80e1 100644 --- a/kernel/msg_q.c +++ b/kernel/msg_q.c @@ -27,7 +27,7 @@ #ifdef CONFIG_OBJ_CORE_MSGQ static struct k_obj_type obj_type_msgq; -#endif +#endif /* CONFIG_OBJ_CORE_MSGQ */ #ifdef CONFIG_POLL static inline void handle_poll_events(struct k_msgq *msgq, uint32_t state) @@ -55,7 +55,7 @@ void k_msgq_init(struct k_msgq *msgq, char *buffer, size_t msg_size, #ifdef CONFIG_OBJ_CORE_MSGQ k_obj_core_init_and_link(K_OBJ_CORE(msgq), &obj_type_msgq); -#endif +#endif /* CONFIG_OBJ_CORE_MSGQ */ SYS_PORT_TRACING_OBJ_INIT(k_msgq, msgq); @@ -98,7 +98,7 @@ int z_vrfy_k_msgq_alloc_init(struct k_msgq *msgq, size_t msg_size, return z_impl_k_msgq_alloc_init(msgq, msg_size, max_msgs); } #include -#endif +#endif /* CONFIG_USERSPACE */ int k_msgq_cleanup(struct k_msgq *msgq) { @@ -193,7 +193,7 @@ static inline int z_vrfy_k_msgq_put(struct k_msgq *msgq, const void *data, return z_impl_k_msgq_put(msgq, data, timeout); } #include -#endif +#endif /* CONFIG_USERSPACE */ void z_impl_k_msgq_get_attrs(struct k_msgq *msgq, struct k_msgq_attrs *attrs) { @@ -211,7 +211,7 @@ static inline void z_vrfy_k_msgq_get_attrs(struct k_msgq *msgq, z_impl_k_msgq_get_attrs(msgq, attrs); } #include -#endif +#endif /* CONFIG_USERSPACE */ int z_impl_k_msgq_get(struct k_msgq *msgq, void *data, k_timeout_t timeout) { @@ -291,7 +291,7 @@ static inline int z_vrfy_k_msgq_get(struct k_msgq *msgq, void *data, return z_impl_k_msgq_get(msgq, data, timeout); } #include -#endif +#endif /* CONFIG_USERSPACE */ int z_impl_k_msgq_peek(struct k_msgq *msgq, void *data) { @@ -325,7 +325,7 @@ static inline int z_vrfy_k_msgq_peek(struct k_msgq *msgq, void *data) return z_impl_k_msgq_peek(msgq, data); } #include -#endif +#endif /* CONFIG_USERSPACE */ int z_impl_k_msgq_peek_at(struct k_msgq *msgq, void *data, uint32_t idx) { @@ -371,7 +371,7 @@ static inline int z_vrfy_k_msgq_peek_at(struct k_msgq *msgq, void *data, uint32_ return z_impl_k_msgq_peek_at(msgq, data, idx); } #include -#endif +#endif /* CONFIG_USERSPACE */ void z_impl_k_msgq_purge(struct k_msgq *msgq) { @@ -416,7 +416,7 @@ static inline uint32_t z_vrfy_k_msgq_num_used_get(struct k_msgq *msgq) } #include -#endif +#endif /* CONFIG_USERSPACE */ #ifdef CONFIG_OBJ_CORE_MSGQ static int init_msgq_obj_core_list(void) @@ -438,4 +438,4 @@ static int init_msgq_obj_core_list(void) SYS_INIT(init_msgq_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_MSGQ */ diff --git a/kernel/mutex.c b/kernel/mutex.c index 328a75ca9d4..e5ead48b9c9 100644 --- a/kernel/mutex.c +++ b/kernel/mutex.c @@ -49,7 +49,7 @@ static struct k_spinlock lock; #ifdef CONFIG_OBJ_CORE_MUTEX static struct k_obj_type obj_type_mutex; -#endif +#endif /* CONFIG_OBJ_CORE_MUTEX */ int z_impl_k_mutex_init(struct k_mutex *mutex) { @@ -62,7 +62,7 @@ int z_impl_k_mutex_init(struct k_mutex *mutex) #ifdef CONFIG_OBJ_CORE_MUTEX k_obj_core_init_and_link(K_OBJ_CORE(mutex), &obj_type_mutex); -#endif +#endif /* CONFIG_OBJ_CORE_MUTEX */ SYS_PORT_TRACING_OBJ_INIT(k_mutex, mutex, 0); @@ -76,7 +76,7 @@ static inline int z_vrfy_k_mutex_init(struct k_mutex *mutex) return z_impl_k_mutex_init(mutex); } #include -#endif +#endif /* CONFIG_USERSPACE */ static int32_t new_prio_for_inheritance(int32_t target, int32_t limit) { @@ -205,7 +205,7 @@ static inline int z_vrfy_k_mutex_lock(struct k_mutex *mutex, return z_impl_k_mutex_lock(mutex, timeout); } #include -#endif +#endif /* CONFIG_USERSPACE */ int z_impl_k_mutex_unlock(struct k_mutex *mutex) { @@ -289,7 +289,7 @@ static inline int z_vrfy_k_mutex_unlock(struct k_mutex *mutex) return z_impl_k_mutex_unlock(mutex); } #include -#endif +#endif /* CONFIG_USERSPACE */ #ifdef CONFIG_OBJ_CORE_MUTEX static int init_mutex_obj_core_list(void) @@ -310,4 +310,4 @@ static int init_mutex_obj_core_list(void) SYS_INIT(init_mutex_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_MUTEX */ diff --git a/kernel/obj_core.c b/kernel/obj_core.c index 8ac4f737d2d..ebd88430ac2 100644 --- a/kernel/obj_core.c +++ b/kernel/obj_core.c @@ -28,7 +28,7 @@ void k_obj_core_init(struct k_obj_core *obj_core, struct k_obj_type *type) obj_core->type = type; #ifdef CONFIG_OBJ_CORE_STATS obj_core->stats = NULL; -#endif +#endif /* CONFIG_OBJ_CORE_STATS */ } void k_obj_core_link(struct k_obj_core *obj_core) @@ -324,4 +324,4 @@ int k_obj_core_stats_enable(struct k_obj_core *obj_core) return rv; } -#endif +#endif /* CONFIG_OBJ_CORE_STATS */ diff --git a/kernel/pipes.c b/kernel/pipes.c index 355377c2a79..de5c6656165 100644 --- a/kernel/pipes.c +++ b/kernel/pipes.c @@ -33,7 +33,7 @@ static int pipe_get_internal(k_spinlock_key_t key, struct k_pipe *pipe, k_timeout_t timeout); #ifdef CONFIG_OBJ_CORE_PIPE static struct k_obj_type obj_type_pipe; -#endif +#endif /* CONFIG_OBJ_CORE_PIPE */ void k_pipe_init(struct k_pipe *pipe, unsigned char *buffer, size_t size) @@ -52,12 +52,12 @@ void k_pipe_init(struct k_pipe *pipe, unsigned char *buffer, size_t size) #if defined(CONFIG_POLL) sys_dlist_init(&pipe->poll_events); -#endif +#endif /* CONFIG_POLL */ k_object_init(pipe); #ifdef CONFIG_OBJ_CORE_PIPE k_obj_core_init_and_link(K_OBJ_CORE(pipe), &obj_type_pipe); -#endif +#endif /* CONFIG_OBJ_CORE_PIPE */ } int z_impl_k_pipe_alloc_init(struct k_pipe *pipe, size_t size) @@ -94,7 +94,7 @@ static inline int z_vrfy_k_pipe_alloc_init(struct k_pipe *pipe, size_t size) return z_impl_k_pipe_alloc_init(pipe, size); } #include -#endif +#endif /* CONFIG_USERSPACE */ static inline void handle_poll_events(struct k_pipe *pipe) { @@ -102,7 +102,7 @@ static inline void handle_poll_events(struct k_pipe *pipe) z_handle_obj_poll_events(&pipe->poll_events, K_POLL_STATE_PIPE_DATA_AVAILABLE); #else ARG_UNUSED(pipe); -#endif +#endif /* CONFIG_POLL */ } void z_impl_k_pipe_flush(struct k_pipe *pipe) @@ -127,7 +127,7 @@ void z_vrfy_k_pipe_flush(struct k_pipe *pipe) z_impl_k_pipe_flush(pipe); } #include -#endif +#endif /* CONFIG_USERSPACE */ void z_impl_k_pipe_buffer_flush(struct k_pipe *pipe) { @@ -154,7 +154,7 @@ void z_vrfy_k_pipe_buffer_flush(struct k_pipe *pipe) z_impl_k_pipe_buffer_flush(pipe); } -#endif +#endif /* CONFIG_USERSPACE */ int k_pipe_cleanup(struct k_pipe *pipe) { @@ -526,7 +526,7 @@ int z_vrfy_k_pipe_put(struct k_pipe *pipe, const void *data, timeout); } #include -#endif +#endif /* CONFIG_USERSPACE */ static int pipe_get_internal(k_spinlock_key_t key, struct k_pipe *pipe, void *data, size_t bytes_to_read, @@ -734,7 +734,7 @@ int z_vrfy_k_pipe_get(struct k_pipe *pipe, void *data, size_t bytes_to_read, timeout); } #include -#endif +#endif /* CONFIG_USERSPACE */ size_t z_impl_k_pipe_read_avail(struct k_pipe *pipe) { @@ -771,7 +771,7 @@ size_t z_vrfy_k_pipe_read_avail(struct k_pipe *pipe) return z_impl_k_pipe_read_avail(pipe); } #include -#endif +#endif /* CONFIG_USERSPACE */ size_t z_impl_k_pipe_write_avail(struct k_pipe *pipe) { @@ -808,7 +808,7 @@ size_t z_vrfy_k_pipe_write_avail(struct k_pipe *pipe) return z_impl_k_pipe_write_avail(pipe); } #include -#endif +#endif /* CONFIG_USERSPACE */ #ifdef CONFIG_OBJ_CORE_PIPE static int init_pipe_obj_core_list(void) @@ -829,4 +829,4 @@ static int init_pipe_obj_core_list(void) SYS_INIT(init_pipe_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_PIPE */ diff --git a/kernel/poll.c b/kernel/poll.c index d983af7e20e..185aba609c2 100644 --- a/kernel/poll.c +++ b/kernel/poll.c @@ -93,7 +93,7 @@ static inline bool is_condition_met(struct k_poll_event *event, uint32_t *state) *state = K_POLL_STATE_PIPE_DATA_AVAILABLE; return true; } -#endif +#endif /* CONFIG_PIPES */ case K_POLL_TYPE_IGNORE: break; default: @@ -159,7 +159,7 @@ static inline void register_event(struct k_poll_event *event, __ASSERT(event->pipe != NULL, "invalid pipe\n"); add_event(&event->pipe->poll_events, event, poller); break; -#endif +#endif /* CONFIG_PIPES */ case K_POLL_TYPE_IGNORE: /* nothing to do */ break; @@ -200,7 +200,7 @@ static inline void clear_event_registration(struct k_poll_event *event) __ASSERT(event->pipe != NULL, "invalid pipe\n"); remove_event = true; break; -#endif +#endif /* CONFIG_PIPES */ case K_POLL_TYPE_IGNORE: /* nothing to do */ break; @@ -417,7 +417,7 @@ static inline int z_vrfy_k_poll(struct k_poll_event *events, case K_POLL_TYPE_PIPE_DATA_AVAILABLE: K_OOPS(K_SYSCALL_OBJ(e->pipe, K_OBJ_PIPE)); break; -#endif +#endif /* CONFIG_PIPES */ default: ret = -EINVAL; goto out_free; @@ -435,7 +435,7 @@ static inline int z_vrfy_k_poll(struct k_poll_event *events, K_OOPS(1); } #include -#endif +#endif /* CONFIG_USERSPACE */ /* must be called with interrupts locked */ static int signal_poll_event(struct k_poll_event *event, uint32_t state) @@ -494,7 +494,7 @@ static inline void z_vrfy_k_poll_signal_init(struct k_poll_signal *sig) z_impl_k_poll_signal_init(sig); } #include -#endif +#endif /* CONFIG_USERSPACE */ void z_impl_k_poll_signal_reset(struct k_poll_signal *sig) { @@ -522,7 +522,7 @@ void z_vrfy_k_poll_signal_check(struct k_poll_signal *sig, z_impl_k_poll_signal_check(sig, signaled, result); } #include -#endif +#endif /* CONFIG_USERSPACE */ int z_impl_k_poll_signal_raise(struct k_poll_signal *sig, int result) { @@ -565,7 +565,7 @@ static inline void z_vrfy_k_poll_signal_reset(struct k_poll_signal *sig) } #include -#endif +#endif /* CONFIG_USERSPACE */ static void triggered_work_handler(struct k_work *work) { diff --git a/kernel/queue.c b/kernel/queue.c index 04aaa149d97..b99bfb0174a 100644 --- a/kernel/queue.c +++ b/kernel/queue.c @@ -76,7 +76,7 @@ static inline void z_vrfy_k_queue_init(struct k_queue *queue) z_impl_k_queue_init(queue); } #include -#endif +#endif /* CONFIG_USERSPACE */ static void prepare_thread_to_run(struct k_thread *thread, void *data) { @@ -91,7 +91,7 @@ static inline void handle_poll_events(struct k_queue *queue, uint32_t state) #else ARG_UNUSED(queue); ARG_UNUSED(state); -#endif +#endif /* CONFIG_POLL */ } void z_impl_k_queue_cancel_wait(struct k_queue *queue) @@ -118,7 +118,7 @@ static inline void z_vrfy_k_queue_cancel_wait(struct k_queue *queue) z_impl_k_queue_cancel_wait(queue); } #include -#endif +#endif /* CONFIG_USERSPACE */ static int32_t queue_insert(struct k_queue *queue, void *prev, void *data, bool alloc, bool is_append) @@ -221,7 +221,7 @@ static inline int32_t z_vrfy_k_queue_alloc_append(struct k_queue *queue, return z_impl_k_queue_alloc_append(queue, data); } #include -#endif +#endif /* CONFIG_USERSPACE */ int32_t z_impl_k_queue_alloc_prepend(struct k_queue *queue, void *data) { @@ -242,7 +242,7 @@ static inline int32_t z_vrfy_k_queue_alloc_prepend(struct k_queue *queue, return z_impl_k_queue_alloc_prepend(queue, data); } #include -#endif +#endif /* CONFIG_USERSPACE */ int k_queue_append_list(struct k_queue *queue, void *head, void *tail) { @@ -454,7 +454,7 @@ static int init_fifo_obj_core_list(void) SYS_INIT(init_fifo_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_FIFO */ #ifdef CONFIG_OBJ_CORE_LIFO struct k_obj_type _obj_type_lifo; @@ -477,4 +477,4 @@ static int init_lifo_obj_core_list(void) SYS_INIT(init_lifo_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_LIFO */ diff --git a/kernel/sched.c b/kernel/sched.c index 57974044f94..bcc80d63bba 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -50,7 +50,7 @@ static inline int is_metairq(struct k_thread *thread) #else ARG_UNUSED(thread); return 0; -#endif +#endif /* CONFIG_NUM_METAIRQ_PRIORITIES */ } #if CONFIG_ASSERT @@ -58,7 +58,7 @@ static inline bool is_thread_dummy(struct k_thread *thread) { return (thread->base.thread_state & _THREAD_DUMMY) != 0U; } -#endif +#endif /* CONFIG_ASSERT */ /* * Return value same as e.g. memcmp @@ -98,7 +98,7 @@ int32_t z_sched_prio_cmp(struct k_thread *thread_1, */ return (int32_t) (d2 - d1); } -#endif +#endif /* CONFIG_SCHED_DEADLINE */ return 0; } @@ -154,7 +154,7 @@ static ALWAYS_INLINE struct k_thread *_priq_dumb_mask_best(sys_dlist_t *pq) } return NULL; } -#endif +#endif /* CONFIG_SCHED_CPU_MASK */ #if defined(CONFIG_SCHED_DUMB) || defined(CONFIG_WAITQ_DUMB) static ALWAYS_INLINE void z_priq_dumb_add(sys_dlist_t *pq, @@ -174,7 +174,7 @@ static ALWAYS_INLINE void z_priq_dumb_add(sys_dlist_t *pq, sys_dlist_append(pq, &thread->base.qnode_dlist); } -#endif +#endif /* CONFIG_SCHED_DUMB || CONFIG_WAITQ_DUMB */ static ALWAYS_INLINE void *thread_runq(struct k_thread *thread) { @@ -193,7 +193,7 @@ static ALWAYS_INLINE void *thread_runq(struct k_thread *thread) #else ARG_UNUSED(thread); return &_kernel.ready_q.runq; -#endif +#endif /* CONFIG_SCHED_CPU_MASK_PIN_ONLY */ } static ALWAYS_INLINE void *curr_cpu_runq(void) @@ -202,7 +202,7 @@ static ALWAYS_INLINE void *curr_cpu_runq(void) return &arch_curr_cpu()->ready_q.runq; #else return &_kernel.ready_q.runq; -#endif +#endif /* CONFIG_SCHED_CPU_MASK_PIN_ONLY */ } static ALWAYS_INLINE void runq_add(struct k_thread *thread) @@ -239,7 +239,7 @@ static ALWAYS_INLINE void queue_thread(struct k_thread *thread) /* add current to end of queue means "yield" */ _current_cpu->swap_ok = true; } -#endif +#endif /* CONFIG_SMP */ } static ALWAYS_INLINE void dequeue_thread(struct k_thread *thread) @@ -266,7 +266,7 @@ static void signal_pending_ipi(void) arch_sched_ipi(); } } -#endif +#endif /* CONFIG_SMP && CONFIG_SCHED_IPI_SUPPORTED */ } #ifdef CONFIG_SMP @@ -296,7 +296,7 @@ static inline bool is_halting(struct k_thread *thread) return (thread->base.thread_state & (_THREAD_ABORTING | _THREAD_SUSPENDING)) != 0U; } -#endif +#endif /* CONFIG_SMP */ /* Clear the halting bits (_THREAD_ABORTING and _THREAD_SUSPENDING) */ static inline void clear_halting(struct k_thread *thread) @@ -311,7 +311,7 @@ static ALWAYS_INLINE struct k_thread *next_up(void) halt_thread(_current, is_aborting(_current) ? _THREAD_DEAD : _THREAD_SUSPENDED); } -#endif +#endif /* CONFIG_SMP */ struct k_thread *thread = runq_best(); @@ -332,6 +332,9 @@ static ALWAYS_INLINE struct k_thread *next_up(void) } } #endif +/* CONFIG_NUM_METAIRQ_PRIORITIES > 0 && + * CONFIG_NUM_COOP_PRIORITIES > CONFIG_NUM_METAIRQ_PRIORITIES + */ #ifndef CONFIG_SMP /* In uniprocessor mode, we can leave the current thread in @@ -386,7 +389,7 @@ static ALWAYS_INLINE struct k_thread *next_up(void) _current_cpu->swap_ok = false; return thread; -#endif +#endif /* CONFIG_SMP */ } static void move_thread_to_end_of_prio_q(struct k_thread *thread) @@ -404,7 +407,7 @@ static void flag_ipi(void) if (arch_num_cpus() > 1) { _kernel.pending_ipi = true; } -#endif +#endif /* CONFIG_SMP && CONFIG_SCHED_IPI_SUPPORTED */ } #ifdef CONFIG_TIMESLICING @@ -421,7 +424,7 @@ static bool slice_expired[CONFIG_MP_MAX_NUM_CPUS]; * a noop condition in z_time_slice(). */ static struct k_thread *pending_current; -#endif +#endif /* CONFIG_SWAP_NONATOMIC */ static inline int slice_time(struct k_thread *thread) { @@ -433,7 +436,7 @@ static inline int slice_time(struct k_thread *thread) } #else ARG_UNUSED(thread); -#endif +#endif /* CONFIG_TIMESLICE_PER_THREAD */ return ret; } @@ -447,7 +450,7 @@ static inline bool sliceable(struct k_thread *thread) #ifdef CONFIG_TIMESLICE_PER_THREAD ret |= thread->base.slice_ticks != 0; -#endif +#endif /* CONFIG_TIMESLICE_PER_THREAD */ return ret; } @@ -498,7 +501,7 @@ void k_thread_time_slice_set(struct k_thread *thread, int32_t thread_slice_ticks thread->base.slice_data = data; } } -#endif +#endif /* CONFIG_TIMESLICE_PER_THREAD */ /* Called out of each timer interrupt */ void z_time_slice(void) @@ -513,7 +516,7 @@ void z_time_slice(void) return; } pending_current = NULL; -#endif +#endif /* CONFIG_SWAP_NONATOMIC */ if (slice_expired[_current_cpu->id] && sliceable(curr)) { #ifdef CONFIG_TIMESLICE_PER_THREAD @@ -522,7 +525,7 @@ void z_time_slice(void) curr->base.slice_expired(curr, curr->base.slice_data); key = k_spin_lock(&_sched_spinlock); } -#endif +#endif /* CONFIG_TIMESLICE_PER_THREAD */ if (!z_is_thread_prevented_from_running(curr)) { move_thread_to_end_of_prio_q(curr); } @@ -530,7 +533,7 @@ void z_time_slice(void) } k_spin_unlock(&_sched_spinlock, key); } -#endif +#endif /* CONFIG_TIMESLICING */ /* Track cooperative threads preempted by metairqs so we can return to * them specifically. Called at the moment a new thread has been @@ -551,6 +554,9 @@ static void update_metairq_preempt(struct k_thread *thread) #else ARG_UNUSED(thread); #endif +/* CONFIG_NUM_METAIRQ_PRIORITIES > 0 && + * CONFIG_NUM_COOP_PRIORITIES > CONFIG_NUM_METAIRQ_PRIORITIES + */ } static void update_cache(int preempt_ok) @@ -563,7 +569,7 @@ static void update_cache(int preempt_ok) if (thread != _current) { z_reset_time_slice(thread); } -#endif +#endif /* CONFIG_TIMESLICING */ update_metairq_preempt(thread); _kernel.ready_q.cache = thread; } else { @@ -578,7 +584,7 @@ static void update_cache(int preempt_ok) * reason the scheduler will make the same decision anyway. */ _current_cpu->swap_ok = preempt_ok; -#endif +#endif /* CONFIG_SMP */ } static bool thread_active_elsewhere(struct k_thread *thread) @@ -598,7 +604,7 @@ static bool thread_active_elsewhere(struct k_thread *thread) return true; } } -#endif +#endif /* CONFIG_SMP */ ARG_UNUSED(thread); return false; } @@ -607,7 +613,7 @@ static void ready_thread(struct k_thread *thread) { #ifdef CONFIG_KERNEL_COHERENCE __ASSERT_NO_MSG(arch_mem_coherent(thread)); -#endif +#endif /* CONFIG_KERNEL_COHERENCE */ /* If thread is queued already, do not try and added it to the * run queue again @@ -693,7 +699,7 @@ static void z_thread_halt(struct k_thread *thread, k_spinlock_key_t key, */ #ifdef CONFIG_SCHED_IPI_SUPPORTED arch_sched_ipi(); -#endif +#endif /* CONFIG_SCHED_IPI_SUPPORTED */ } if (is_halting(thread) && (thread != _current)) { @@ -719,7 +725,7 @@ static void z_thread_halt(struct k_thread *thread, k_spinlock_key_t key, } return; /* lock has been released */ } -#endif +#endif /* CONFIG_SMP */ halt_thread(thread, terminate ? _THREAD_DEAD : _THREAD_SUSPENDED); if ((thread == _current) && !arch_is_in_isr()) { z_swap(&_sched_spinlock, key); @@ -757,7 +763,7 @@ static inline void z_vrfy_k_thread_suspend(struct k_thread *thread) z_impl_k_thread_suspend(thread); } #include -#endif +#endif /* CONFIG_USERSPACE */ void z_impl_k_thread_resume(struct k_thread *thread) { @@ -786,7 +792,7 @@ static inline void z_vrfy_k_thread_resume(struct k_thread *thread) z_impl_k_thread_resume(thread); } #include -#endif +#endif /* CONFIG_USERSPACE */ static _wait_q_t *pended_on_thread(struct k_thread *thread) { @@ -829,7 +835,7 @@ static void pend_locked(struct k_thread *thread, _wait_q_t *wait_q, { #ifdef CONFIG_KERNEL_COHERENCE __ASSERT_NO_MSG(wait_q == NULL || arch_mem_coherent(wait_q)); -#endif +#endif /* CONFIG_KERNEL_COHERENCE */ add_to_waitq_locked(thread, wait_q); add_thread_timeout(thread, timeout); } @@ -873,7 +879,7 @@ void z_sched_wake_thread(struct k_thread *thread, bool is_timeout) if (do_nothing) { continue; } -#endif +#endif /* CONFIG_EVENTS */ if (!killed) { /* The thread is not being killed */ @@ -899,14 +905,14 @@ void z_thread_timeout(struct _timeout *timeout) z_sched_wake_thread(thread, true); } -#endif +#endif /* CONFIG_SYS_CLOCK_EXISTS */ int z_pend_curr(struct k_spinlock *lock, k_spinlock_key_t key, _wait_q_t *wait_q, k_timeout_t timeout) { #if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC) pending_current = _current; -#endif +#endif /* CONFIG_TIMESLICING && CONFIG_SWAP_NONATOMIC */ __ASSERT_NO_MSG(sizeof(_sched_spinlock) == 0 || lock != &_sched_spinlock); /* We do a "lock swap" prior to calling z_swap(), such that @@ -994,7 +1000,7 @@ static inline bool resched(uint32_t key) { #ifdef CONFIG_SMP _current_cpu->swap_ok = 0; -#endif +#endif /* CONFIG_SMP */ return arch_irq_unlocked(key) && !arch_is_in_isr(); } @@ -1014,7 +1020,7 @@ static inline bool need_swap(void) /* Check if the next ready thread is the same as the current thread */ new_thread = _kernel.ready_q.cache; return new_thread != _current; -#endif +#endif /* CONFIG_SMP */ } void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key) @@ -1079,7 +1085,7 @@ struct k_thread *z_swap_next_thread(void) return ret; #else return _kernel.ready_q.cache; -#endif +#endif /* CONFIG_SMP */ } #ifdef CONFIG_USE_SWITCH @@ -1148,7 +1154,7 @@ void *z_get_next_switch_handle(void *interrupted) #ifdef CONFIG_TIMESLICING z_reset_time_slice(new_thread); -#endif +#endif /* CONFIG_TIMESLICING */ #ifdef CONFIG_SPIN_VALIDATE /* Changed _current! Update the spinlock @@ -1157,7 +1163,7 @@ void *z_get_next_switch_handle(void *interrupted) * release the lock. */ z_spin_lock_set_owner(&_sched_spinlock); -#endif +#endif /* CONFIG_SPIN_VALIDATE */ /* A queued (runnable) old/current thread * needs to be added back to the run queue @@ -1183,9 +1189,9 @@ void *z_get_next_switch_handle(void *interrupted) _current->switch_handle = interrupted; set_current(_kernel.ready_q.cache); return _current->switch_handle; -#endif +#endif /* CONFIG_SMP */ } -#endif +#endif /* CONFIG_USE_SWITCH */ int z_unpend_all(_wait_q_t *wait_q) { @@ -1226,7 +1232,7 @@ void z_sched_init(void) } #else init_ready_q(&_kernel.ready_q); -#endif +#endif /* CONFIG_SCHED_CPU_MASK_PIN_ONLY */ } int z_impl_k_thread_priority_get(k_tid_t thread) @@ -1241,7 +1247,7 @@ static inline int z_vrfy_k_thread_priority_get(k_tid_t thread) return z_impl_k_thread_priority_get(thread); } #include -#endif +#endif /* CONFIG_USERSPACE */ void z_impl_k_thread_priority_set(k_tid_t thread, int prio) { @@ -1270,11 +1276,11 @@ static inline void z_vrfy_k_thread_priority_set(k_tid_t thread, int prio) K_OOPS(K_SYSCALL_VERIFY_MSG((int8_t)prio >= thread->base.prio, "thread priority may only be downgraded (%d < %d)", prio, thread->base.prio)); -#endif +#endif /* CONFIG_USERSPACE_THREAD_MAY_RAISE_PRIORITY */ z_impl_k_thread_priority_set(thread, prio); } #include -#endif +#endif /* CONFIG_USERSPACE */ #ifdef CONFIG_SCHED_DEADLINE void z_impl_k_thread_deadline_set(k_tid_t tid, int deadline) @@ -1312,8 +1318,8 @@ static inline void z_vrfy_k_thread_deadline_set(k_tid_t tid, int deadline) z_impl_k_thread_deadline_set((k_tid_t)thread, deadline); } #include -#endif -#endif +#endif /* CONFIG_USERSPACE */ +#endif /* CONFIG_SCHED_DEADLINE */ bool k_can_yield(void) { @@ -1344,7 +1350,7 @@ static inline void z_vrfy_k_yield(void) z_impl_k_yield(); } #include -#endif +#endif /* CONFIG_USERSPACE */ static int32_t z_tick_sleep(k_ticks_t ticks) { @@ -1360,7 +1366,7 @@ static int32_t z_tick_sleep(k_ticks_t ticks) k_yield(); return 0; } -#endif +#endif /* CONFIG_MULTITHREADING */ if (Z_TICK_ABS(ticks) <= 0) { expected_wakeup_ticks = ticks + sys_clock_tick_get_32(); @@ -1374,7 +1380,7 @@ static int32_t z_tick_sleep(k_ticks_t ticks) #if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC) pending_current = _current; -#endif +#endif /* CONFIG_TIMESLICING && CONFIG_SWAP_NONATOMIC */ unready_thread(_current); z_add_thread_timeout(_current, timeout); z_mark_thread_as_suspended(_current); @@ -1390,7 +1396,7 @@ static int32_t z_tick_sleep(k_ticks_t ticks) #else /* busy wait to be time coherent since subsystems may depend on it */ z_impl_k_busy_wait(k_ticks_to_us_ceil32(expected_wakeup_ticks)); -#endif +#endif /* CONFIG_MULTITHREADING */ return 0; } @@ -1410,7 +1416,7 @@ int32_t z_impl_k_sleep(k_timeout_t timeout) #else /* In Single Thread, just wait for an interrupt saving power */ k_cpu_idle(); -#endif +#endif /* CONFIG_MULTITHREADING */ SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER); return (int32_t) K_TICKS_FOREVER; @@ -1433,7 +1439,7 @@ static inline int32_t z_vrfy_k_sleep(k_timeout_t timeout) return z_impl_k_sleep(timeout); } #include -#endif +#endif /* CONFIG_USERSPACE */ int32_t z_impl_k_usleep(int us) { @@ -1457,7 +1463,7 @@ static inline int32_t z_vrfy_k_usleep(int us) return z_impl_k_usleep(us); } #include -#endif +#endif /* CONFIG_USERSPACE */ void z_impl_k_wakeup(k_tid_t thread) { @@ -1491,7 +1497,7 @@ void z_impl_k_wakeup(k_tid_t thread) #ifdef CONFIG_TRACE_SCHED_IPI extern void z_trace_sched_ipi(void); -#endif +#endif /* CONFIG_TRACE_SCHED_IPI */ #ifdef CONFIG_SMP void z_sched_ipi(void) @@ -1501,15 +1507,15 @@ void z_sched_ipi(void) */ #ifdef CONFIG_TRACE_SCHED_IPI z_trace_sched_ipi(); -#endif +#endif /* CONFIG_TRACE_SCHED_IPI */ #ifdef CONFIG_TIMESLICING if (sliceable(_current)) { z_time_slice(); } -#endif +#endif /* CONFIG_TIMESLICING */ } -#endif +#endif /* CONFIG_SMP */ #ifdef CONFIG_USERSPACE static inline void z_vrfy_k_wakeup(k_tid_t thread) @@ -1518,7 +1524,7 @@ static inline void z_vrfy_k_wakeup(k_tid_t thread) z_impl_k_wakeup(thread); } #include -#endif +#endif /* CONFIG_USERSPACE */ k_tid_t z_impl_k_sched_current_thread_query(void) { @@ -1528,13 +1534,13 @@ k_tid_t z_impl_k_sched_current_thread_query(void) * local interrupts when reading it. */ unsigned int k = arch_irq_lock(); -#endif +#endif /* CONFIG_SMP */ k_tid_t ret = _current_cpu->current; #ifdef CONFIG_SMP arch_irq_unlock(k); -#endif +#endif /* CONFIG_SMP */ return ret; } @@ -1544,7 +1550,7 @@ static inline k_tid_t z_vrfy_k_sched_current_thread_query(void) return z_impl_k_sched_current_thread_query(); } #include -#endif +#endif /* CONFIG_USERSPACE */ int z_impl_k_is_preempt_thread(void) { @@ -1557,7 +1563,7 @@ static inline int z_vrfy_k_is_preempt_thread(void) return z_impl_k_is_preempt_thread(); } #include -#endif +#endif /* CONFIG_USERSPACE */ static inline void unpend_all(_wait_q_t *wait_q) { @@ -1573,7 +1579,7 @@ static inline void unpend_all(_wait_q_t *wait_q) #ifdef CONFIG_THREAD_ABORT_HOOK extern void thread_abort_hook(struct k_thread *thread); -#endif +#endif /* CONFIG_THREAD_ABORT_HOOK */ /** * @brief Dequeues the specified thread @@ -1604,7 +1610,7 @@ static void halt_thread(struct k_thread *thread, uint8_t new_state) } #ifdef CONFIG_SMP unpend_all(&thread->halt_queue); -#endif +#endif /* CONFIG_SMP */ update_cache(1); if (new_state == _THREAD_SUSPENDED) { @@ -1613,28 +1619,28 @@ static void halt_thread(struct k_thread *thread, uint8_t new_state) #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) arch_float_disable(thread); -#endif +#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ SYS_PORT_TRACING_FUNC(k_thread, sched_abort, thread); z_thread_monitor_exit(thread); #ifdef CONFIG_THREAD_ABORT_HOOK thread_abort_hook(thread); -#endif +#endif /* CONFIG_THREAD_ABORT_HOOK */ #ifdef CONFIG_OBJ_CORE_THREAD #ifdef CONFIG_OBJ_CORE_STATS_THREAD k_obj_core_stats_deregister(K_OBJ_CORE(thread)); -#endif +#endif /* CONFIG_OBJ_CORE_STATS_THREAD */ k_obj_core_unlink(K_OBJ_CORE(thread)); -#endif +#endif /* CONFIG_OBJ_CORE_THREAD */ #ifdef CONFIG_USERSPACE z_mem_domain_exit_thread(thread); k_thread_perms_all_clear(thread); k_object_uninit(thread->stack_obj); k_object_uninit(thread); -#endif +#endif /* CONFIG_USERSPACE */ } } @@ -1666,7 +1672,7 @@ void z_impl_k_thread_abort(struct k_thread *thread) SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_thread, abort, thread); } -#endif +#endif /* !CONFIG_ARCH_HAS_THREAD_ABORT */ int z_impl_k_thread_join(struct k_thread *thread, k_timeout_t timeout) { @@ -1723,7 +1729,7 @@ static bool thread_obj_validate(struct k_thread *thread) default: #ifdef CONFIG_LOG k_object_dump_error(ret, thread, ko, K_OBJ_THREAD); -#endif +#endif /* CONFIG_LOG */ K_OOPS(K_SYSCALL_VERIFY_MSG(ret, "access denied")); } CODE_UNREACHABLE; /* LCOV_EXCL_LINE */ diff --git a/kernel/sem.c b/kernel/sem.c index 2f8de51ed83..819abd3879c 100644 --- a/kernel/sem.c +++ b/kernel/sem.c @@ -40,7 +40,7 @@ static struct k_spinlock lock; #ifdef CONFIG_OBJ_CORE_SEM static struct k_obj_type obj_type_sem; -#endif +#endif /* CONFIG_OBJ_CORE_SEM */ int z_impl_k_sem_init(struct k_sem *sem, unsigned int initial_count, unsigned int limit) @@ -62,12 +62,12 @@ int z_impl_k_sem_init(struct k_sem *sem, unsigned int initial_count, z_waitq_init(&sem->wait_q); #if defined(CONFIG_POLL) sys_dlist_init(&sem->poll_events); -#endif +#endif /* CONFIG_POLL */ k_object_init(sem); #ifdef CONFIG_OBJ_CORE_SEM k_obj_core_init_and_link(K_OBJ_CORE(sem), &obj_type_sem); -#endif +#endif /* CONFIG_OBJ_CORE_SEM */ return 0; } @@ -80,7 +80,7 @@ int z_vrfy_k_sem_init(struct k_sem *sem, unsigned int initial_count, return z_impl_k_sem_init(sem, initial_count, limit); } #include -#endif +#endif /* CONFIG_USERSPACE */ static inline bool handle_poll_events(struct k_sem *sem) { @@ -90,7 +90,7 @@ static inline bool handle_poll_events(struct k_sem *sem) #else ARG_UNUSED(sem); return false; -#endif +#endif /* CONFIG_POLL */ } void z_impl_k_sem_give(struct k_sem *sem) @@ -127,7 +127,7 @@ static inline void z_vrfy_k_sem_give(struct k_sem *sem) z_impl_k_sem_give(sem); } #include -#endif +#endif /* CONFIG_USERSPACE */ int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout) { @@ -207,7 +207,7 @@ static inline unsigned int z_vrfy_k_sem_count_get(struct k_sem *sem) } #include -#endif +#endif /* CONFIG_USERSPACE */ #ifdef CONFIG_OBJ_CORE_SEM static int init_sem_obj_core_list(void) @@ -228,4 +228,4 @@ static int init_sem_obj_core_list(void) SYS_INIT(init_sem_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_SEM */ diff --git a/kernel/smp.c b/kernel/smp.c index 6b5a12ad2af..6e6cad2688f 100644 --- a/kernel/smp.c +++ b/kernel/smp.c @@ -49,7 +49,7 @@ static struct cpu_start_cb { #ifdef CONFIG_SYS_CLOCK_EXISTS /** True if smp_timer_init() needs to be called. */ bool reinit_timer; -#endif +#endif /* CONFIG_SYS_CLOCK_EXISTS */ } cpu_start_fn; static struct k_spinlock cpu_start_lock; @@ -130,7 +130,7 @@ static inline void smp_init_top(void *arg) if ((arg == NULL) || csc.reinit_timer) { smp_timer_init(); } -#endif +#endif /* CONFIG_SYS_CLOCK_EXISTS */ /* Do additional initialization steps if needed. */ if (csc.fn != NULL) { @@ -177,7 +177,7 @@ void k_smp_cpu_start(int id, smp_init_fn fn, void *arg) #ifdef CONFIG_SYS_CLOCK_EXISTS cpu_start_fn.reinit_timer = true; -#endif +#endif /* CONFIG_SYS_CLOCK_EXISTS */ /* We are only starting one CPU so we do not need to synchronize * across all CPUs using the start_flag. So just set it to 1. @@ -206,7 +206,7 @@ void k_smp_cpu_resume(int id, smp_init_fn fn, void *arg, cpu_start_fn.reinit_timer = reinit_timer; #else ARG_UNUSED(reinit_timer); -#endif +#endif /* CONFIG_SYS_CLOCK_EXISTS */ /* We are only starting one CPU so we do not need to synchronize * across all CPUs using the start_flag. So just set it to 1. diff --git a/kernel/stack.c b/kernel/stack.c index 6ada39c9b1e..822abfca363 100644 --- a/kernel/stack.c +++ b/kernel/stack.c @@ -21,7 +21,7 @@ #ifdef CONFIG_OBJ_CORE_STACK static struct k_obj_type obj_type_stack; -#endif +#endif /* CONFIG_OBJ_CORE_STACK */ void k_stack_init(struct k_stack *stack, stack_data_t *buffer, uint32_t num_entries) @@ -36,7 +36,7 @@ void k_stack_init(struct k_stack *stack, stack_data_t *buffer, #ifdef CONFIG_OBJ_CORE_STACK k_obj_core_init_and_link(K_OBJ_CORE(stack), &obj_type_stack); -#endif +#endif /* CONFIG_OBJ_CORE_STACK */ } int32_t z_impl_k_stack_alloc_init(struct k_stack *stack, uint32_t num_entries) @@ -69,7 +69,7 @@ static inline int32_t z_vrfy_k_stack_alloc_init(struct k_stack *stack, return z_impl_k_stack_alloc_init(stack, num_entries); } #include -#endif +#endif /* CONFIG_USERSPACE */ int k_stack_cleanup(struct k_stack *stack) { @@ -137,7 +137,7 @@ static inline int z_vrfy_k_stack_push(struct k_stack *stack, stack_data_t data) return z_impl_k_stack_push(stack, data); } #include -#endif +#endif /* CONFIG_USERSPACE */ int z_impl_k_stack_pop(struct k_stack *stack, stack_data_t *data, k_timeout_t timeout) @@ -192,7 +192,7 @@ static inline int z_vrfy_k_stack_pop(struct k_stack *stack, return z_impl_k_stack_pop(stack, data, timeout); } #include -#endif +#endif /* CONFIG_USERSPACE */ #ifdef CONFIG_OBJ_CORE_STACK static int init_stack_obj_core_list(void) @@ -213,4 +213,4 @@ static int init_stack_obj_core_list(void) SYS_INIT(init_stack_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_STACK */ diff --git a/kernel/thread.c b/kernel/thread.c index dc512a456d4..729be274b09 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -47,7 +47,7 @@ static struct k_obj_core_stats_desc thread_stats_desc = { .disable = z_thread_stats_disable, .enable = z_thread_stats_enable, }; -#endif +#endif /* CONFIG_OBJ_CORE_STATS_THREAD */ static int init_thread_obj_core_list(void) { @@ -56,18 +56,18 @@ static int init_thread_obj_core_list(void) #ifdef CONFIG_OBJ_CORE_THREAD z_obj_type_init(&obj_type_thread, K_OBJ_TYPE_THREAD_ID, offsetof(struct k_thread, obj_core)); -#endif +#endif /* CONFIG_OBJ_CORE_THREAD */ #ifdef CONFIG_OBJ_CORE_STATS_THREAD k_obj_type_stats_init(&obj_type_thread, &thread_stats_desc); -#endif +#endif /* CONFIG_OBJ_CORE_STATS_THREAD */ return 0; } SYS_INIT(init_thread_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_THREAD */ #define _FOREACH_STATIC_THREAD(thread_data) \ @@ -91,7 +91,7 @@ static inline void z_vrfy_k_thread_custom_data_set(void *data) z_impl_k_thread_custom_data_set(data); } #include -#endif +#endif /* CONFIG_USERSPACE */ void *z_impl_k_thread_custom_data_get(void) { @@ -338,8 +338,8 @@ static inline void z_vrfy_k_thread_start(struct k_thread *thread) return z_impl_k_thread_start(thread); } #include -#endif -#endif +#endif /* CONFIG_USERSPACE */ +#endif /* CONFIG_MULTITHREADING */ #if CONFIG_STACK_POINTER_RANDOM @@ -388,7 +388,7 @@ static char *setup_thread_stack(struct k_thread *new_thread, stack_buf_start = Z_THREAD_STACK_BUFFER(stack); stack_buf_size = stack_obj_size - K_THREAD_STACK_RESERVED; } else -#endif +#endif /* CONFIG_USERSPACE */ { /* Object cannot host a user mode thread */ stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size); @@ -417,7 +417,7 @@ static char *setup_thread_stack(struct k_thread *new_thread, #ifdef CONFIG_INIT_STACKS memset(stack_buf_start, 0xaa, stack_buf_size); -#endif +#endif /* CONFIG_INIT_STACKS */ #ifdef CONFIG_STACK_SENTINEL /* Put the stack sentinel at the lowest 4 bytes of the stack area. * We periodically check that it's still present and kill the thread @@ -436,10 +436,10 @@ static char *setup_thread_stack(struct k_thread *new_thread, delta += tls_size; new_thread->userspace_local_data = (struct _thread_userspace_local_data *)(stack_ptr - delta); -#endif +#endif /* CONFIG_THREAD_USERSPACE_LOCAL_DATA */ #if CONFIG_STACK_POINTER_RANDOM delta += random_offset(stack_buf_size); -#endif +#endif /* CONFIG_STACK_POINTER_RANDOM */ delta = ROUND_UP(delta, ARCH_STACK_PTR_ALIGN); #ifdef CONFIG_THREAD_STACK_INFO /* Initial values. Arches which implement MPU guards that "borrow" @@ -452,7 +452,7 @@ static char *setup_thread_stack(struct k_thread *new_thread, new_thread->stack_info.start = (uintptr_t)stack_buf_start; new_thread->stack_info.size = stack_buf_size; new_thread->stack_info.delta = delta; -#endif +#endif /* CONFIG_THREAD_STACK_INFO */ stack_ptr -= delta; return stack_ptr; @@ -479,8 +479,8 @@ char *z_setup_new_thread(struct k_thread *new_thread, k_obj_core_stats_register(K_OBJ_CORE(new_thread), &new_thread->base.usage, sizeof(new_thread->base.usage)); -#endif -#endif +#endif /* CONFIG_OBJ_CORE_STATS_THREAD */ +#endif /* CONFIG_OBJ_CORE_THREAD */ #ifdef CONFIG_USERSPACE __ASSERT((options & K_USER) == 0U || z_stack_is_user_capable(stack), @@ -493,7 +493,7 @@ char *z_setup_new_thread(struct k_thread *new_thread, /* Any given thread has access to itself */ k_object_access_grant(new_thread, new_thread); -#endif +#endif /* CONFIG_USERSPACE */ z_waitq_init(&new_thread->join_queue); /* Initialize various struct k_thread members */ @@ -513,7 +513,7 @@ char *z_setup_new_thread(struct k_thread *new_thread, __ASSERT_NO_MSG(!arch_mem_coherent(stack)); #endif /* CONFIG_DYNAMIC_THREAD */ -#endif +#endif /* CONFIG_KERNEL_COHERENCE */ arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3); @@ -527,14 +527,14 @@ char *z_setup_new_thread(struct k_thread *new_thread, */ __ASSERT(new_thread->switch_handle != NULL, "arch layer failed to initialize switch_handle"); -#endif +#endif /* CONFIG_USE_SWITCH */ #ifdef CONFIG_THREAD_CUSTOM_DATA /* Initialize custom data field (value is opaque to kernel) */ new_thread->custom_data = NULL; -#endif +#endif /* CONFIG_THREAD_CUSTOM_DATA */ #ifdef CONFIG_EVENTS new_thread->no_wake_on_timeout = false; -#endif +#endif /* CONFIG_EVENTS */ #ifdef CONFIG_THREAD_MONITOR new_thread->entry.pEntry = entry; new_thread->entry.parameter1 = p1; @@ -546,7 +546,7 @@ char *z_setup_new_thread(struct k_thread *new_thread, new_thread->next_thread = _kernel.threads; _kernel.threads = new_thread; k_spin_unlock(&z_thread_monitor_lock, key); -#endif +#endif /* CONFIG_THREAD_MONITOR */ #ifdef CONFIG_THREAD_NAME if (name != NULL) { strncpy(new_thread->name, name, @@ -556,42 +556,42 @@ char *z_setup_new_thread(struct k_thread *new_thread, } else { new_thread->name[0] = '\0'; } -#endif +#endif /* CONFIG_THREAD_NAME */ #ifdef CONFIG_SCHED_CPU_MASK if (IS_ENABLED(CONFIG_SCHED_CPU_MASK_PIN_ONLY)) { new_thread->base.cpu_mask = 1; /* must specify only one cpu */ } else { new_thread->base.cpu_mask = -1; /* allow all cpus */ } -#endif +#endif /* CONFIG_SCHED_CPU_MASK */ #ifdef CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN /* _current may be null if the dummy thread is not used */ if (!_current) { new_thread->resource_pool = NULL; return stack_ptr; } -#endif +#endif /* CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN */ #ifdef CONFIG_USERSPACE z_mem_domain_init_thread(new_thread); if ((options & K_INHERIT_PERMS) != 0U) { k_thread_perms_inherit(_current, new_thread); } -#endif +#endif /* CONFIG_USERSPACE */ #ifdef CONFIG_SCHED_DEADLINE new_thread->base.prio_deadline = 0; -#endif +#endif /* CONFIG_SCHED_DEADLINE */ new_thread->resource_pool = _current->resource_pool; #ifdef CONFIG_SMP z_waitq_init(&new_thread->halt_queue); -#endif +#endif /* CONFIG_SMP */ #ifdef CONFIG_SCHED_THREAD_USAGE new_thread->base.usage = (struct k_cycle_stats) {}; new_thread->base.usage.track_usage = CONFIG_SCHED_THREAD_USAGE_AUTO_ENABLE; -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE */ SYS_PORT_TRACING_OBJ_FUNC(k_thread, create, new_thread); @@ -661,7 +661,7 @@ k_tid_t z_vrfy_k_thread_create(struct k_thread *new_thread, stack_obj_size = stack_object->data.stack_data->size; #else stack_obj_size = stack_object->data.stack_size; -#endif +#endif /* CONFIG_GEN_PRIV_STACKS */ K_OOPS(K_SYSCALL_VERIFY_MSG(total_size <= stack_obj_size, "stack size %zu is too big, max is %zu", total_size, stack_obj_size)); @@ -707,12 +707,12 @@ void z_init_thread_base(struct _thread_base *thread_base, int priority, #ifdef CONFIG_SMP thread_base->is_idle = 0; -#endif +#endif /* CONFIG_SMP */ #ifdef CONFIG_TIMESLICE_PER_THREAD thread_base->slice_ticks = 0; thread_base->slice_expired = NULL; -#endif +#endif /* CONFIG_TIMESLICE_PER_THREAD */ /* swap_data does not need to be initialized */ @@ -731,30 +731,30 @@ FUNC_NORETURN void k_thread_user_mode_enter(k_thread_entry_t entry, _current->entry.parameter1 = p1; _current->entry.parameter2 = p2; _current->entry.parameter3 = p3; -#endif +#endif /* CONFIG_THREAD_MONITOR */ #ifdef CONFIG_USERSPACE __ASSERT(z_stack_is_user_capable(_current->stack_obj), "dropping to user mode with kernel-only stack object"); #ifdef CONFIG_THREAD_USERSPACE_LOCAL_DATA memset(_current->userspace_local_data, 0, sizeof(struct _thread_userspace_local_data)); -#endif +#endif /* CONFIG_THREAD_USERSPACE_LOCAL_DATA */ #ifdef CONFIG_THREAD_LOCAL_STORAGE arch_tls_stack_setup(_current, (char *)(_current->stack_info.start + _current->stack_info.size)); -#endif +#endif /* CONFIG_THREAD_LOCAL_STORAGE */ arch_user_mode_enter(entry, p1, p2, p3); #else /* XXX In this case we do not reset the stack */ z_thread_entry(entry, p1, p2, p3); -#endif +#endif /* CONFIG_USERSPACE */ } #if defined(CONFIG_INIT_STACKS) && defined(CONFIG_THREAD_STACK_INFO) #ifdef CONFIG_STACK_GROWS_UP #error "Unsupported configuration for stack analysis" -#endif +#endif /* CONFIG_STACK_GROWS_UP */ int z_stack_space_get(const uint8_t *stack_start, size_t size, size_t *unused_ptr) { @@ -858,25 +858,25 @@ static inline k_ticks_t z_vrfy_k_thread_timeout_expires_ticks( return z_impl_k_thread_timeout_expires_ticks(thread); } #include -#endif +#endif /* CONFIG_USERSPACE */ #ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING void z_thread_mark_switched_in(void) { #if defined(CONFIG_SCHED_THREAD_USAGE) && !defined(CONFIG_USE_SWITCH) z_sched_usage_start(_current); -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE && !CONFIG_USE_SWITCH */ #ifdef CONFIG_TRACING SYS_PORT_TRACING_FUNC(k_thread, switched_in); -#endif +#endif /* CONFIG_TRACING */ } void z_thread_mark_switched_out(void) { #if defined(CONFIG_SCHED_THREAD_USAGE) && !defined(CONFIG_USE_SWITCH) z_sched_usage_stop(); -#endif +#endif /*CONFIG_SCHED_THREAD_USAGE && !CONFIG_USE_SWITCH */ #ifdef CONFIG_TRACING #ifdef CONFIG_THREAD_LOCAL_STORAGE @@ -884,9 +884,9 @@ void z_thread_mark_switched_out(void) if (!_current_cpu->current || (_current_cpu->current->base.thread_state & _THREAD_DUMMY) != 0) return; -#endif +#endif /* CONFIG_THREAD_LOCAL_STORAGE */ SYS_PORT_TRACING_FUNC(k_thread, switched_out); -#endif +#endif /* CONFIG_TRACING */ } #endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */ @@ -901,7 +901,7 @@ int k_thread_runtime_stats_get(k_tid_t thread, z_sched_thread_usage(thread, stats); #else *stats = (k_thread_runtime_stats_t) {}; -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE */ return 0; } @@ -910,7 +910,7 @@ int k_thread_runtime_stats_all_get(k_thread_runtime_stats_t *stats) { #ifdef CONFIG_SCHED_THREAD_USAGE_ALL k_thread_runtime_stats_t tmp_stats; -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ALL */ if (stats == NULL) { return -EINVAL; @@ -932,10 +932,10 @@ int k_thread_runtime_stats_all_get(k_thread_runtime_stats_t *stats) stats->current_cycles += tmp_stats.current_cycles; stats->peak_cycles += tmp_stats.peak_cycles; stats->average_cycles += tmp_stats.average_cycles; -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ stats->idle_cycles += tmp_stats.idle_cycles; } -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ALL */ return 0; } diff --git a/kernel/timeout.c b/kernel/timeout.c index b667abafe99..3d5cb51c0f0 100644 --- a/kernel/timeout.c +++ b/kernel/timeout.c @@ -105,7 +105,7 @@ void z_add_timeout(struct _timeout *to, _timeout_func_t fn, #ifdef CONFIG_KERNEL_COHERENCE __ASSERT_NO_MSG(arch_mem_coherent(to)); -#endif +#endif /* CONFIG_KERNEL_COHERENCE */ __ASSERT(!sys_dnode_is_linked(&to->node), ""); to->fn = fn; @@ -255,7 +255,7 @@ void sys_clock_announce(int32_t ticks) #ifdef CONFIG_TIMESLICING z_time_slice(); -#endif +#endif /* CONFIG_TIMESLICING */ } int64_t sys_clock_tick_get(void) @@ -274,7 +274,7 @@ uint32_t sys_clock_tick_get_32(void) return (uint32_t)sys_clock_tick_get(); #else return (uint32_t)curr_tick; -#endif +#endif /* CONFIG_TICKLESS_KERNEL */ } int64_t z_impl_k_uptime_ticks(void) @@ -288,7 +288,7 @@ static inline int64_t z_vrfy_k_uptime_ticks(void) return z_impl_k_uptime_ticks(); } #include -#endif +#endif /* CONFIG_USERSPACE */ k_timepoint_t sys_timepoint_calc(k_timeout_t timeout) { @@ -337,4 +337,4 @@ void z_vrfy_sys_clock_tick_set(uint64_t tick) { z_impl_sys_clock_tick_set(tick); } -#endif +#endif /* CONFIG_ZTEST */ diff --git a/kernel/timer.c b/kernel/timer.c index 48cc69baffe..8eafbb4d7e3 100644 --- a/kernel/timer.c +++ b/kernel/timer.c @@ -17,7 +17,7 @@ static struct k_spinlock lock; #ifdef CONFIG_OBJ_CORE_TIMER static struct k_obj_type obj_type_timer; -#endif +#endif /* CONFIG_OBJ_CORE_TIMER */ /** * @brief Handle expiration of a kernel timer object. @@ -72,7 +72,7 @@ void z_timer_expiration_handler(struct _timeout *t) * down" behavior on timeout addition). */ next = K_TIMEOUT_ABS_TICKS(k_uptime_ticks() + 1 + next.ticks); -#endif +#endif /* CONFIG_TIMEOUT_64BIT */ z_add_timeout(&timer->timeout, z_timer_expiration_handler, next); } @@ -132,7 +132,7 @@ void k_timer_init(struct k_timer *timer, #ifdef CONFIG_OBJ_CORE_TIMER k_obj_core_init_and_link(K_OBJ_CORE(timer), &obj_type_timer); -#endif +#endif /* CONFIG_OBJ_CORE_TIMER */ } @@ -189,7 +189,7 @@ static inline void z_vrfy_k_timer_start(struct k_timer *timer, z_impl_k_timer_start(timer, duration, period); } #include -#endif +#endif /* CONFIG_USERSPACE */ void z_impl_k_timer_stop(struct k_timer *timer) { @@ -222,7 +222,7 @@ static inline void z_vrfy_k_timer_stop(struct k_timer *timer) z_impl_k_timer_stop(timer); } #include -#endif +#endif /* CONFIG_USERSPACE */ uint32_t z_impl_k_timer_status_get(struct k_timer *timer) { @@ -242,7 +242,7 @@ static inline uint32_t z_vrfy_k_timer_status_get(struct k_timer *timer) return z_impl_k_timer_status_get(timer); } #include -#endif +#endif /* CONFIG_USERSPACE */ uint32_t z_impl_k_timer_status_sync(struct k_timer *timer) { @@ -342,7 +342,7 @@ static inline void z_vrfy_k_timer_user_data_set(struct k_timer *timer, } #include -#endif +#endif /* CONFIG_USERSPACE */ #ifdef CONFIG_OBJ_CORE_TIMER static int init_timer_obj_core_list(void) @@ -362,4 +362,4 @@ static int init_timer_obj_core_list(void) } SYS_INIT(init_timer_obj_core_list, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif +#endif /* CONFIG_OBJ_CORE_TIMER */ diff --git a/kernel/usage.c b/kernel/usage.c index de497e2879c..7ec5e30c8d2 100644 --- a/kernel/usage.c +++ b/kernel/usage.c @@ -14,7 +14,7 @@ /* Need one of these for this to work */ #if !defined(CONFIG_USE_SWITCH) && !defined(CONFIG_INSTRUMENT_THREAD_SWITCHING) #error "No data backend configured for CONFIG_SCHED_THREAD_USAGE" -#endif +#endif /* !CONFIG_USE_SWITCH && !CONFIG_INSTRUMENT_THREAD_SWITCHING */ static struct k_spinlock usage_lock; @@ -26,7 +26,7 @@ static uint32_t usage_now(void) now = (uint32_t)timing_counter_get(); #else now = k_cycle_get_32(); -#endif +#endif /* CONFIG_THREAD_RUNTIME_STATS_USE_TIMING_FUNCTIONS */ /* Edge case: we use a zero as a null ("stop() already called") */ return (now == 0) ? 1 : now; @@ -51,12 +51,12 @@ static void sched_cpu_update_usage(struct _cpu *cpu, uint32_t cycles) } else { cpu->usage->current = 0; cpu->usage->num_windows++; -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ } } #else #define sched_cpu_update_usage(cpu, cycles) do { } while (0) -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ALL */ static void sched_thread_update_usage(struct k_thread *thread, uint32_t cycles) { @@ -68,7 +68,7 @@ static void sched_thread_update_usage(struct k_thread *thread, uint32_t cycles) if (thread->base.usage.longest < thread->base.usage.current) { thread->base.usage.longest = thread->base.usage.current; } -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ } void z_sched_usage_start(struct k_thread *thread) @@ -93,7 +93,7 @@ void z_sched_usage_start(struct k_thread *thread) */ _current_cpu->usage0 = usage_now(); -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ } void z_sched_usage_stop(void) @@ -159,7 +159,7 @@ void z_sched_cpu_usage(uint8_t cpu_id, struct k_thread_runtime_stats *stats) stats->average_cycles = stats->total_cycles / cpu->usage->num_windows; } -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ stats->idle_cycles = _kernel.cpus[cpu_id].idle_thread->base.usage.total; @@ -168,7 +168,7 @@ void z_sched_cpu_usage(uint8_t cpu_id, struct k_thread_runtime_stats *stats) k_spin_unlock(&usage_lock, key); } -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ALL */ void z_sched_thread_usage(struct k_thread *thread, struct k_thread_runtime_stats *stats) @@ -215,11 +215,11 @@ void z_sched_thread_usage(struct k_thread *thread, stats->average_cycles = stats->total_cycles / thread->base.usage.num_windows; } -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ #ifdef CONFIG_SCHED_THREAD_USAGE_ALL stats->idle_cycles = 0; -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ALL */ stats->execution_cycles = thread->base.usage.total; k_spin_unlock(&usage_lock, key); @@ -273,7 +273,7 @@ int k_thread_runtime_stats_disable(k_tid_t thread) return 0; } -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ #ifdef CONFIG_SCHED_THREAD_USAGE_ALL void k_sys_runtime_stats_enable(void) @@ -303,7 +303,7 @@ void k_sys_runtime_stats_enable(void) #ifdef CONFIG_SCHED_THREAD_USAGE_ANALYSIS _kernel.cpus[i].usage->num_windows++; _kernel.cpus[i].usage->current = 0; -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ } k_spin_unlock(&usage_lock, key); @@ -342,7 +342,7 @@ void k_sys_runtime_stats_disable(void) k_spin_unlock(&usage_lock, key); } -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ALL */ #ifdef CONFIG_OBJ_CORE_STATS_THREAD int z_thread_stats_raw(struct k_obj_core *obj_core, void *stats) @@ -382,7 +382,7 @@ int z_thread_stats_reset(struct k_obj_core *obj_core) stats->current = 0ULL; stats->longest = 0ULL; stats->num_windows = (thread->base.usage.track_usage) ? 1U : 0U; -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ if (thread != _current_cpu->current) { @@ -423,7 +423,7 @@ int z_thread_stats_disable(struct k_obj_core *obj_core) return k_thread_runtime_stats_disable(thread); #else return -ENOTSUP; -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ } int z_thread_stats_enable(struct k_obj_core *obj_core) @@ -436,9 +436,9 @@ int z_thread_stats_enable(struct k_obj_core *obj_core) return k_thread_runtime_stats_enable(thread); #else return -ENOTSUP; -#endif +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ } -#endif +#endif /* CONFIG_OBJ_CORE_STATS_THREAD */ #ifdef CONFIG_OBJ_CORE_STATS_SYSTEM int z_cpu_stats_raw(struct k_obj_core *obj_core, void *stats) @@ -462,7 +462,7 @@ int z_cpu_stats_query(struct k_obj_core *obj_core, void *stats) return 0; } -#endif +#endif /* CONFIG_OBJ_CORE_STATS_SYSTEM */ #ifdef CONFIG_OBJ_CORE_STATS_SYSTEM int z_kernel_stats_raw(struct k_obj_core *obj_core, void *stats) @@ -483,4 +483,4 @@ int z_kernel_stats_query(struct k_obj_core *obj_core, void *stats) return k_thread_runtime_stats_all_get(stats); } -#endif +#endif /* CONFIG_OBJ_CORE_STATS_SYSTEM */ diff --git a/kernel/userspace.c b/kernel/userspace.c index ecdc1348d09..c87421d0725 100644 --- a/kernel/userspace.c +++ b/kernel/userspace.c @@ -25,7 +25,7 @@ #ifdef Z_LIBC_PARTITION_EXISTS K_APPMEM_PARTITION_DEFINE(z_libc_partition); -#endif +#endif /* Z_LIBC_PARTITION_EXISTS */ /* TODO: Find a better place to put this. Since we pull the entire * lib..__modules__crypto__mbedtls.a globals into app shared memory @@ -33,7 +33,7 @@ K_APPMEM_PARTITION_DEFINE(z_libc_partition); */ #ifdef CONFIG_MBEDTLS K_APPMEM_PARTITION_DEFINE(k_mbedtls_partition); -#endif +#endif /* CONFIG_MBEDTLS */ #include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); @@ -68,14 +68,14 @@ static struct k_spinlock objfree_lock; /* k_object_free */ #define STACK_ELEMENT_DATA_SIZE(size) Z_THREAD_STACK_SIZE_ADJUST(size) #endif /* CONFIG_GEN_PRIV_STACKS */ -#endif +#endif /* CONFIG_DYNAMIC_OBJECTS */ static struct k_spinlock obj_lock; /* kobj struct data */ #define MAX_THREAD_BITS (CONFIG_MAX_THREAD_BYTES * 8) #ifdef CONFIG_DYNAMIC_OBJECTS extern uint8_t _thread_idx_map[CONFIG_MAX_THREAD_BYTES]; -#endif +#endif /* CONFIG_DYNAMIC_OBJECTS */ static void clear_perms_cb(struct k_object *ko, void *ctx_ptr); @@ -102,7 +102,7 @@ const char *otype_to_str(enum k_objects otype) #else ARG_UNUSED(otype); ret = NULL; -#endif +#endif /* CONFIG_LOG */ return ret; } @@ -147,7 +147,7 @@ uint8_t *z_priv_stack_find(k_thread_stack_t *stack) #define DYN_OBJ_DATA_ALIGN_K_THREAD (ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT) #else #define DYN_OBJ_DATA_ALIGN_K_THREAD (sizeof(void *)) -#endif +#endif /* ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT */ #ifdef CONFIG_DYNAMIC_THREAD_STACK_SIZE #ifndef CONFIG_MPU_STACK_GUARD @@ -211,7 +211,7 @@ static size_t obj_align_get(enum k_objects otype) ret = ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT; #else ret = __alignof(struct dyn_obj); -#endif +#endif /* ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT */ break; default: ret = __alignof(struct dyn_obj); @@ -349,11 +349,11 @@ static struct k_object *dynamic_object_create(enum k_objects otype, size_t align Z_THREAD_STACK_OBJ_ALIGN(size)); #else dyn->kobj.name = dyn->data; -#endif +#endif /* CONFIG_ARM_MPU || CONFIG_ARC_MPU */ #else dyn->kobj.name = dyn->data; dyn->kobj.data.stack_size = adjusted_size; -#endif +#endif /* CONFIG_GEN_PRIV_STACKS */ } else { dyn->data = z_thread_aligned_alloc(align, obj_size_get(otype) + size); if (dyn->data == NULL) { @@ -561,7 +561,7 @@ static void unref_check(struct k_object *ko, uintptr_t index) case K_OBJ_PIPE: k_pipe_cleanup((struct k_pipe *)ko->name); break; -#endif +#endif /* CONFIG_PIPES */ case K_OBJ_MSGQ: k_msgq_cleanup((struct k_msgq *)ko->name); break; @@ -577,7 +577,7 @@ static void unref_check(struct k_object *ko, uintptr_t index) k_free(dyn->data); k_free(dyn); out: -#endif +#endif /* CONFIG_DYNAMIC_OBJECTS */ k_spin_unlock(&obj_lock, key); } diff --git a/kernel/userspace_handler.c b/kernel/userspace_handler.c index a1cf9f9d7a3..a26c50828d7 100644 --- a/kernel/userspace_handler.c +++ b/kernel/userspace_handler.c @@ -25,7 +25,7 @@ static struct k_object *validate_kernel_object(const void *obj, if (ret != 0) { #ifdef CONFIG_LOG k_object_dump_error(ret, obj, ko, otype); -#endif +#endif /* CONFIG_LOG */ return NULL; } diff --git a/kernel/work.c b/kernel/work.c index 269e73465cb..cf73bdbcabe 100644 --- a/kernel/work.c +++ b/kernel/work.c @@ -471,7 +471,7 @@ bool k_work_flush(struct k_work *work, __ASSERT_NO_MSG(sync != NULL); #ifdef CONFIG_KERNEL_COHERENCE __ASSERT_NO_MSG(arch_mem_coherent(sync)); -#endif +#endif /* CONFIG_KERNEL_COHERENCE */ SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_work, flush, work); @@ -583,7 +583,7 @@ bool k_work_cancel_sync(struct k_work *work, __ASSERT_NO_MSG(!k_is_in_isr()); #ifdef CONFIG_KERNEL_COHERENCE __ASSERT_NO_MSG(arch_mem_coherent(sync)); -#endif +#endif /* CONFIG_KERNEL_COHERENCE */ SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_work, cancel_sync, work, sync); @@ -1066,7 +1066,7 @@ bool k_work_cancel_delayable_sync(struct k_work_delayable *dwork, __ASSERT_NO_MSG(!k_is_in_isr()); #ifdef CONFIG_KERNEL_COHERENCE __ASSERT_NO_MSG(arch_mem_coherent(sync)); -#endif +#endif /* CONFIG_KERNEL_COHERENCE */ SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_work, cancel_delayable_sync, dwork, sync); @@ -1098,7 +1098,7 @@ bool k_work_flush_delayable(struct k_work_delayable *dwork, __ASSERT_NO_MSG(!k_is_in_isr()); #ifdef CONFIG_KERNEL_COHERENCE __ASSERT_NO_MSG(arch_mem_coherent(sync)); -#endif +#endif /* CONFIG_KERNEL_COHERENCE */ SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_work, flush_delayable, dwork, sync); From d65b6bc199327c1ae882565afe52b65068c55676 Mon Sep 17 00:00:00 2001 From: Lucas Tamborrino Date: Thu, 27 Apr 2023 10:44:56 -0300 Subject: [PATCH 1325/2402] twister: add flash-before option Add option to flash board before attach serial. Current implementation performs the following sequence: 1. Open serial port to listen to board log output 2. Flash device In case of ESP32 where it uses the same serial port for both operations, flashing needs to come first. This PR adds a twister option named --flash-before which enables the process above, allowing tests to be performed properly. Signed-off-by: Lucas Tamborrino --- .../pylib/twister/twisterlib/environment.py | 14 ++++++++++++++ scripts/pylib/twister/twisterlib/handlers.py | 19 ++++++++++++++++++- .../pylib/twister/twisterlib/hardwaremap.py | 18 +++++++++++++----- scripts/schemas/twister/hwmap-schema.yaml | 3 +++ 4 files changed, 48 insertions(+), 6 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/environment.py b/scripts/pylib/twister/twisterlib/environment.py index daa691c19d0..86770eb4bf8 100644 --- a/scripts/pylib/twister/twisterlib/environment.py +++ b/scripts/pylib/twister/twisterlib/environment.py @@ -178,6 +178,12 @@ def add_parse_arguments(parser = None): when flash operation also executes test case on the platform. """) + parser.add_argument("--flash-before", action="store_true", default=False, + help="""Flash device before attaching to serial port. + This is useful for devices that share the same port for programming + and serial console, where flash must come first. + """) + test_or_build.add_argument( "-b", "--build-only", action="store_true", default="--prep-artifacts-for-testing" in sys.argv, help="Only build the code, do not attempt to run the code on targets.") @@ -796,6 +802,14 @@ def parse_arguments(parser, args, options = None): logger.error("--device-flash-with-test requires --device_testing") sys.exit(1) + if options.flash_before and options.device_flash_with_test: + logger.error("--device-flash-with-test does not apply when --flash-before is used") + sys.exit(1) + + if options.flash_before and options.device_serial_pty: + logger.error("--device-serial-pty cannot be used when --flash-before is set (for now)") + sys.exit(1) + if options.shuffle_tests and options.subset is None: logger.error("--shuffle-tests requires --subset") sys.exit(1) diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py index 8a732f28ad4..ed0ee9003b1 100755 --- a/scripts/pylib/twister/twisterlib/handlers.py +++ b/scripts/pylib/twister/twisterlib/handlers.py @@ -378,6 +378,10 @@ def monitor_serial(self, ser, halt_event, harness): # from the test. harness.capture_coverage = True + # Wait for serial connection + while not ser.isOpen(): + time.sleep(0.1) + # Clear serial leftover. ser.reset_input_buffer() @@ -647,9 +651,13 @@ def handle(self, harness): if hardware.flash_with_test: flash_timeout += self.get_test_timeout() + serial_port = None + if hardware.flash_before is False: + serial_port = serial_device + try: ser = self._create_serial_connection( - serial_device, + serial_port, hardware.baud, flash_timeout, serial_pty, @@ -703,6 +711,15 @@ def handle(self, harness): if post_flash_script: self.run_custom_script(post_flash_script, 30) + # Connect to device after flashing it + if hardware.flash_before: + try: + logger.debug(f"Attach serial device {serial_device} @ {hardware.baud} baud") + ser.port = serial_device + ser.open() + except serial.SerialException: + return + if not flash_error: # Always wait at most the test timeout here after flashing. t.join(self.get_test_timeout()) diff --git a/scripts/pylib/twister/twisterlib/hardwaremap.py b/scripts/pylib/twister/twisterlib/hardwaremap.py index 27bca007185..2ef780c3838 100644 --- a/scripts/pylib/twister/twisterlib/hardwaremap.py +++ b/scripts/pylib/twister/twisterlib/hardwaremap.py @@ -49,7 +49,8 @@ def __init__(self, post_flash_script=None, runner=None, flash_timeout=60, - flash_with_test=False): + flash_with_test=False, + flash_before=False): self.serial = serial self.baud = serial_baud or 115200 @@ -63,6 +64,7 @@ def __init__(self, self.product = product self.runner = runner self.runner_params = runner_params + self.flash_before = flash_before self.fixtures = [] self.post_flash_script = post_flash_script self.post_script = post_script @@ -177,7 +179,8 @@ def discover(self): False, baud=self.options.device_serial_baud, flash_timeout=self.options.device_flash_timeout, - flash_with_test=self.options.device_flash_with_test + flash_with_test=self.options.device_flash_with_test, + flash_before=self.options.flash_before, ) elif self.options.device_serial_pty: @@ -186,7 +189,8 @@ def discover(self): self.options.pre_script, True, flash_timeout=self.options.device_flash_timeout, - flash_with_test=self.options.device_flash_with_test + flash_with_test=self.options.device_flash_with_test, + flash_before=False, ) # the fixtures given by twister command explicitly should be assigned to each DUT @@ -207,9 +211,9 @@ def summary(self, selected_platforms): print(tabulate(table, headers=header, tablefmt="github")) - def add_device(self, serial, platform, pre_script, is_pty, baud=None, flash_timeout=60, flash_with_test=False): + def add_device(self, serial, platform, pre_script, is_pty, baud=None, flash_timeout=60, flash_with_test=False, flash_before=False): device = DUT(platform=platform, connected=True, pre_script=pre_script, serial_baud=baud, - flash_timeout=flash_timeout, flash_with_test=flash_with_test + flash_timeout=flash_timeout, flash_with_test=flash_with_test, flash_before=flash_before ) if is_pty: device.serial_pty = serial @@ -229,6 +233,9 @@ def load(self, map_file): flash_with_test = dut.get('flash_with_test') if flash_with_test is None: flash_with_test = self.options.device_flash_with_test + flash_before = dut.get('flash_before') + if flash_before is None: + flash_before = self.options.flash_before and (not (flash_with_test or serial_pty)) platform = dut.get('platform') id = dut.get('id') runner = dut.get('runner') @@ -251,6 +258,7 @@ def load(self, map_file): serial_baud=baud, connected=connected, pre_script=pre_script, + flash_before=flash_before, post_script=post_script, post_flash_script=post_flash_script, flash_timeout=flash_timeout, diff --git a/scripts/schemas/twister/hwmap-schema.yaml b/scripts/schemas/twister/hwmap-schema.yaml index 3ecb064ddfc..1865462fc46 100644 --- a/scripts/schemas/twister/hwmap-schema.yaml +++ b/scripts/schemas/twister/hwmap-schema.yaml @@ -61,3 +61,6 @@ sequence: "flash_with_test": type: bool required: false + "flash_before": + type: bool + required: false From fe4b03baf3002205bd743a319d20648876dd7675 Mon Sep 17 00:00:00 2001 From: "Mike J. Chen" Date: Fri, 22 Mar 2024 12:39:05 -0700 Subject: [PATCH 1326/2402] drivers: i3c: i3c_mcux: Fix bug in do_one_xfer Error check was incorrect, causing wait for complete not to be done. This can result in emit stop not working on writes because controller won't do the stop if it is still busy processing transmit. Signed-off-by: Mike J. Chen --- drivers/i3c/i3c_mcux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i3c/i3c_mcux.c b/drivers/i3c/i3c_mcux.c index f3bd50d9b2a..70fd991c4ee 100644 --- a/drivers/i3c/i3c_mcux.c +++ b/drivers/i3c/i3c_mcux.c @@ -1031,7 +1031,7 @@ static int mcux_i3c_do_one_xfer(I3C_Type *base, struct mcux_i3c_data *data, ret = mcux_i3c_do_one_xfer_write(base, buf, buf_sz, no_ending); } - if (ret) { + if (ret < 0) { goto out_one_xfer; } From feecb751b28b24077d1db63061b0ad182abe52d1 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 22 Mar 2024 10:16:54 +0100 Subject: [PATCH 1327/2402] samples/bluetooth/unicast_audio_server: Fix nrf5340bsim board name The nrf5340bsim_nrf5340_cpuapp hwmv1 board name was replaced with nrf5340bsim/nrf5340/cpuapp in hwmv2. Let's fix it Signed-off-by: Alberto Escolar Piedras --- samples/bluetooth/unicast_audio_server/README.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/samples/bluetooth/unicast_audio_server/README.rst b/samples/bluetooth/unicast_audio_server/README.rst index 9caeac854a7..b3f40dfa820 100644 --- a/samples/bluetooth/unicast_audio_server/README.rst +++ b/samples/bluetooth/unicast_audio_server/README.rst @@ -78,6 +78,6 @@ Building for a simulated nrf5340bsim .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_server/ - :board: nrf5340bsim_nrf5340_cpuapp + :board: nrf5340bsim/nrf5340/cpuapp :goals: build :west-args: --sysbuild From 137efd1c30c120eec9b7f1d2507e8da988a3bd71 Mon Sep 17 00:00:00 2001 From: Lingao Meng Date: Thu, 21 Mar 2024 09:30:47 +0800 Subject: [PATCH 1328/2402] drivers: bluetooth: hci: Fix userchan insufficient buf cause dead-loop. If insufficient buf for given event, will cause dead-loop. Signed-off-by: Lingao Meng --- drivers/bluetooth/hci/userchan.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/bluetooth/hci/userchan.c b/drivers/bluetooth/hci/userchan.c index a94ca5f46be..7c2db034850 100644 --- a/drivers/bluetooth/hci/userchan.c +++ b/drivers/bluetooth/hci/userchan.c @@ -220,7 +220,7 @@ static void rx_thread(void *p1, void *p2, void *p3) buf = get_rx(frame_start); if (!buf) { LOG_DBG("Discard adv report due to insufficient buf"); - continue; + goto next; } buf_tailroom = net_buf_tailroom(buf); @@ -229,7 +229,7 @@ static void rx_thread(void *p1, void *p2, void *p3) LOG_ERR("Not enough space in buffer %zu/%zu", buf_add_len, buf_tailroom); net_buf_unref(buf); - continue; + goto next; } net_buf_add_mem(buf, frame_start + sizeof(packet_type), buf_add_len); @@ -237,6 +237,8 @@ static void rx_thread(void *p1, void *p2, void *p3) LOG_DBG("Calling bt_recv(%p)", buf); bt_recv(buf); + +next: len -= decoded_len; frame_start += decoded_len; } From 7e39db9bce035414dc3173fefaadfab27f21d2c2 Mon Sep 17 00:00:00 2001 From: Aleksandr Khromykh Date: Tue, 19 Mar 2024 14:35:24 +0100 Subject: [PATCH 1329/2402] Bluetooth: Mesh: analyze multicast model rx status Commit adds analyzing of returned status of element rx. If at least one element receives multicast message then access layer will return suceess status. If option CONFIG_BT_MESH_ACCESS_LAYER_MSG is enabled then access layer will return success always. Function bt_mesh_access_recv has been introduced to cover case when real model statuses should be returned over oppcode aggregator model despite access returns success. Signed-off-by: Aleksandr Khromykh --- subsys/bluetooth/mesh/Kconfig | 8 ++++++++ subsys/bluetooth/mesh/access.c | 24 ++++++++++++++++++++++-- subsys/bluetooth/mesh/access.h | 1 + 3 files changed, 31 insertions(+), 2 deletions(-) diff --git a/subsys/bluetooth/mesh/Kconfig b/subsys/bluetooth/mesh/Kconfig index b7590b8790e..88fccf0961c 100644 --- a/subsys/bluetooth/mesh/Kconfig +++ b/subsys/bluetooth/mesh/Kconfig @@ -697,6 +697,14 @@ config BT_MESH_ACCESS_LAYER_MSG Bluetooth access layer messages without the need to instantiate Bluetooth Mesh models. + Please note that Bluetooth Mesh stack stores authentication sequence from + any message that passed over network cache if this option is enabled. + It happens despite the device does not have necessary application keys or + there are unknown model operation codes. It causes the situation when device + will update the replay protection cache for messages those cannot be handled + in the stack. For example, spamming broadcast messages those stack cannot handle + might wear out persistent memory. + config BT_MESH_MODEL_VND_MSG_CID_FORCE bool "Force vendor model to use the corresponding CID field message" default y diff --git a/subsys/bluetooth/mesh/access.c b/subsys/bluetooth/mesh/access.c index 51471097c9e..0ad4e7164ad 100644 --- a/subsys/bluetooth/mesh/access.c +++ b/subsys/bluetooth/mesh/access.c @@ -1545,17 +1545,20 @@ int bt_mesh_model_recv(struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) if (index >= dev_comp->elem_count) { LOG_ERR("Invalid address 0x%02x", ctx->recv_dst); - err = ACCESS_STATUS_INVALID_ADDRESS; + return ACCESS_STATUS_INVALID_ADDRESS; } else { const struct bt_mesh_elem *elem = &dev_comp->elem[index]; err = element_model_recv(ctx, buf, elem, opcode); } } else { + err = ACCESS_STATUS_MESSAGE_NOT_UNDERSTOOD; for (index = 0; index < dev_comp->elem_count; index++) { const struct bt_mesh_elem *elem = &dev_comp->elem[index]; + int err_elem; - (void)element_model_recv(ctx, buf, elem, opcode); + err_elem = element_model_recv(ctx, buf, elem, opcode); + err = err_elem == ACCESS_STATUS_SUCCESS ? err_elem : err; } } @@ -1566,6 +1569,23 @@ int bt_mesh_model_recv(struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) return err; } +int bt_mesh_access_recv(struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) +{ + int err; + + err = bt_mesh_model_recv(ctx, buf); + + if (IS_ENABLED(CONFIG_BT_MESH_ACCESS_LAYER_MSG) && msg_cb) { + /* Mesh assumes that the application has processed the message. + * Access layer returns success to trigger RPL update and prevent + * replay attack over application. + */ + err = 0; + } + + return err; +} + int bt_mesh_model_send(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *msg, const struct bt_mesh_send_cb *cb, void *cb_data) diff --git a/subsys/bluetooth/mesh/access.h b/subsys/bluetooth/mesh/access.h index 210fceee319..ff1728b371c 100644 --- a/subsys/bluetooth/mesh/access.h +++ b/subsys/bluetooth/mesh/access.h @@ -59,6 +59,7 @@ const struct bt_mesh_comp *bt_mesh_comp_get(void); const struct bt_mesh_model *bt_mesh_model_get(bool vnd, uint8_t elem_idx, uint8_t mod_idx); +int bt_mesh_access_recv(struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf); int bt_mesh_model_recv(struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf); int bt_mesh_comp_register(const struct bt_mesh_comp *comp); From 21eafe6b914bfaaa8503760ed4910f2c56606d11 Mon Sep 17 00:00:00 2001 From: Aleksandr Khromykh Date: Tue, 19 Mar 2024 14:42:34 +0100 Subject: [PATCH 1330/2402] Bluetooth: Mesh: store rpl only if incoming data is accepted Commit prevents updating replay protection list on any frame came from the network layer. Replay protection cache is updated only if - transport handles transport command without errors - access layer handles model message without errors - transport frame has correct length Signed-off-by: Aleksandr Khromykh --- subsys/bluetooth/mesh/lpn.c | 3 +- subsys/bluetooth/mesh/rpl.c | 10 +++--- subsys/bluetooth/mesh/transport.c | 55 +++++++++++++++++-------------- 3 files changed, 36 insertions(+), 32 deletions(-) diff --git a/subsys/bluetooth/mesh/lpn.c b/subsys/bluetooth/mesh/lpn.c index f6f906b12fe..0d14c9c55e5 100644 --- a/subsys/bluetooth/mesh/lpn.c +++ b/subsys/bluetooth/mesh/lpn.c @@ -675,7 +675,7 @@ int bt_mesh_lpn_friend_offer(struct bt_mesh_net_rx *rx, err = send_friend_poll(); if (err) { - /* Will retry sending later */ + LOG_WRN("LPN didn't succeed poll sending (err %d)", err); for (int i = 0; i < ARRAY_SIZE(lpn->cred); i++) { if (lpn->sub->keys[i].valid) { bt_mesh_friend_cred_destroy(&lpn->cred[i]); @@ -686,7 +686,6 @@ int bt_mesh_lpn_friend_offer(struct bt_mesh_net_rx *rx, lpn->frnd = BT_MESH_ADDR_UNASSIGNED; lpn->recv_win = 0U; lpn->queue_size = 0U; - return err; } return 0; diff --git a/subsys/bluetooth/mesh/rpl.c b/subsys/bluetooth/mesh/rpl.c index df67ddf9d2e..2170a946671 100644 --- a/subsys/bluetooth/mesh/rpl.c +++ b/subsys/bluetooth/mesh/rpl.c @@ -102,12 +102,12 @@ void bt_mesh_rpl_update(struct bt_mesh_rpl *rpl, } /* Check the Replay Protection List for a replay attempt. If non-NULL match - * parameter is given the RPL slot is returned but it is not immediately - * updated (needed for segmented messages), whereas if a NULL match is given - * the RPL is immediately updated (used for unsegmented messages). + * parameter is given the RPL slot is returned, but it is not immediately + * updated. This is used to prevent storing data in RPL that has been rejected + * by upper logic (access, transport commands) and for receiving the segmented messages. + * If a NULL match is given the RPL is immediately updated (used for proxy configuration). */ -bool bt_mesh_rpl_check(struct bt_mesh_net_rx *rx, - struct bt_mesh_rpl **match) +bool bt_mesh_rpl_check(struct bt_mesh_net_rx *rx, struct bt_mesh_rpl **match) { struct bt_mesh_rpl *rpl; int i; diff --git a/subsys/bluetooth/mesh/transport.c b/subsys/bluetooth/mesh/transport.c index a0364dceb25..66678911f1b 100644 --- a/subsys/bluetooth/mesh/transport.c +++ b/subsys/bluetooth/mesh/transport.c @@ -796,23 +796,22 @@ static int sdu_recv(struct bt_mesh_net_rx *rx, uint8_t hdr, uint8_t aszmic, LOG_DBG("AKF %u AID 0x%02x", !ctx.crypto.dev_key, AID(&hdr)); if (!rx->local_match) { - return 0; + /* if friend_match was set the frame is for LPN which we are friends. */ + return rx->friend_match ? 0 : -ENXIO; } rx->ctx.app_idx = bt_mesh_app_key_find(ctx.crypto.dev_key, AID(&hdr), rx, sdu_try_decrypt, &ctx); if (rx->ctx.app_idx == BT_MESH_KEY_UNUSED) { LOG_DBG("No matching AppKey"); - return 0; + return -EACCES; } rx->ctx.uuid = ctx.crypto.ad; LOG_DBG("Decrypted (AppIdx: 0x%03x)", rx->ctx.app_idx); - (void)bt_mesh_model_recv(&rx->ctx, sdu); - - return 0; + return bt_mesh_access_recv(&rx->ctx, sdu); } static struct seg_tx *seg_tx_lookup(uint16_t seq_zero, uint8_t obo, uint16_t addr) @@ -1027,6 +1026,8 @@ static int trans_unseg(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx, { NET_BUF_SIMPLE_DEFINE_STATIC(sdu, BT_MESH_SDU_UNSEG_MAX); uint8_t hdr; + struct bt_mesh_rpl *rpl = NULL; + int err; LOG_DBG("AFK %u AID 0x%02x", AKF(buf->data), AID(buf->data)); @@ -1035,7 +1036,7 @@ static int trans_unseg(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx, return -EBADMSG; } - if (bt_mesh_rpl_check(rx, NULL)) { + if (bt_mesh_rpl_check(rx, &rpl)) { LOG_WRN("Replay: src 0x%04x dst 0x%04x seq 0x%06x", rx->ctx.addr, rx->ctx.recv_dst, rx->seq); return -EINVAL; @@ -1044,18 +1045,22 @@ static int trans_unseg(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx, hdr = net_buf_simple_pull_u8(buf); if (rx->ctl) { - return ctl_recv(rx, hdr, buf, seq_auth); - } - - if (buf->len < 1 + APP_MIC_LEN(0)) { + err = ctl_recv(rx, hdr, buf, seq_auth); + } else if (buf->len < 1 + APP_MIC_LEN(0)) { LOG_ERR("Too short SDU + MIC"); - return -EINVAL; + err = -EINVAL; + } else { + /* Adjust the length to not contain the MIC at the end */ + buf->len -= APP_MIC_LEN(0); + err = sdu_recv(rx, hdr, 0, buf, &sdu, NULL); } - /* Adjust the length to not contain the MIC at the end */ - buf->len -= APP_MIC_LEN(0); + /* Update rpl only if there is place and upper logic accepted incoming data. */ + if (err == 0 && rpl != NULL) { + bt_mesh_rpl_update(rpl, rx); + } - return sdu_recv(rx, hdr, 0, buf, &sdu, NULL); + return err; } int bt_mesh_ctl_send(struct bt_mesh_net_tx *tx, uint8_t ctl_op, void *data, @@ -1558,17 +1563,6 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, } LOG_DBG("Complete SDU"); - - if (rpl) { - bt_mesh_rpl_update(rpl, net_rx); - /* Update the seg, unless it has already been surpassed: - * This needs to happen after rpl_update to ensure that the IV - * update reset logic inside rpl_update doesn't overwrite the - * change. - */ - rpl->seg = MAX(rpl->seg, auth_seqnum); - } - *pdu_type = BT_MESH_FRIEND_PDU_COMPLETE; /* If this fails, the work handler will either exit early because the @@ -1602,6 +1596,17 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, err = sdu_recv(net_rx, *hdr, ASZMIC(hdr), &seg_buf, &sdu, rx); } + /* Update rpl only if there is place and upper logic accepted incoming data. */ + if (err == 0 && rpl != NULL) { + bt_mesh_rpl_update(rpl, net_rx); + /* Update the seg, unless it has already been surpassed: + * This needs to happen after rpl_update to ensure that the IV + * update reset logic inside rpl_update doesn't overwrite the + * change. + */ + rpl->seg = MAX(rpl->seg, auth_seqnum); + } + seg_rx_reset(rx, false); return err; From 7d6880cc7d46c36e77cc8448ae839324ad5842a5 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 22 Mar 2024 09:41:38 -0500 Subject: [PATCH 1331/2402] west.yml: Update NXP HAL to get SDK cache driver for MCXN947 Update MCXN947 to include the SDK cache driver Signed-off-by: Mahesh Mahadevan --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 3df67baa1df..508eca02d0b 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: fca2c47e874b940bfea5f5f6d6ee725674c81842 + revision: 1a360dbcd58e9f8bc30320bc82e907c03271c5f4 path: modules/hal/nxp groups: - hal From f27aa9922bb6dd2cfaaeac5f55375ae3d59b3739 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Thu, 14 Mar 2024 16:43:17 -0500 Subject: [PATCH 1332/2402] dts: mcxn947: Add FlexSPI node Add support for FlexSPI for MCXN947 SoC Signed-off-by: Mahesh Mahadevan --- dts/arm/nxp/nxp_mcxn94x_common.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi index aa982c21388..7207f7b8aa7 100644 --- a/dts/arm/nxp/nxp_mcxn94x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi @@ -544,6 +544,15 @@ status = "disabled"; }; +&flexspi { + compatible = "nxp,imx-flexspi"; + interrupts = <58 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&syscon MCUX_FLEXSPI_CLK>; +}; + &nvic { arm,num-irq-priority-bits = <3>; }; From b0dbd9a87ee88bac008d8b822471016ad94411d6 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 19 Mar 2024 14:48:19 -0500 Subject: [PATCH 1333/2402] soc: mcxnx4x: Add FlexSPI support Add support for FlexSPI Signed-off-by: Mahesh Mahadevan --- soc/nxp/mcx/Kconfig | 25 +++++++++++++++++++ soc/nxp/mcx/mcxnx4x/CMakeLists.txt | 11 ++++++--- soc/nxp/mcx/mcxnx4x/Kconfig | 25 +++++++++++++++++++ soc/nxp/mcx/mcxnx4x/Kconfig.defconfig | 17 ------------- soc/nxp/mcx/mcxnx4x/flash_clock_setup.c | 33 +++++++++++++++++++++++++ soc/nxp/mcx/mcxnx4x/soc.h | 3 +++ 6 files changed, 94 insertions(+), 20 deletions(-) create mode 100644 soc/nxp/mcx/mcxnx4x/flash_clock_setup.c diff --git a/soc/nxp/mcx/Kconfig b/soc/nxp/mcx/Kconfig index b8ac7a08f17..b2a5c5ab8e7 100644 --- a/soc/nxp/mcx/Kconfig +++ b/soc/nxp/mcx/Kconfig @@ -10,4 +10,29 @@ if SOC_FAMILY_NXP_MCX rsource "*/Kconfig" +if FLASH_MCUX_FLEXSPI_XIP + +# Avoid RWW hazards by defaulting logging to disabled +choice FLASH_LOG_LEVEL_CHOICE + default FLASH_LOG_LEVEL_OFF +endchoice + +choice MEMC_LOG_LEVEL_CHOICE + default MEMC_LOG_LEVEL_OFF +endchoice + +endif + +if FLASH_MCUX_FLEXSPI_XIP + +# Code relocation is needed when FLASH_MCUX_FLEXSPI_XIP is enabled +config CODE_DATA_RELOCATION_SRAM + default y + +config FLASH_MCUX_FLEXSPI_XIP_MEM + string + default "RAM" + +endif # FLASH_MCUX_FLEXSPI_XIP + endif # SOC_FAMILY_NXP_MCX diff --git a/soc/nxp/mcx/mcxnx4x/CMakeLists.txt b/soc/nxp/mcx/mcxnx4x/CMakeLists.txt index 0a382670bc2..588876205bb 100644 --- a/soc/nxp/mcx/mcxnx4x/CMakeLists.txt +++ b/soc/nxp/mcx/mcxnx4x/CMakeLists.txt @@ -8,9 +8,14 @@ # Flexcomm SDK driver zephyr_compile_definitions_ifdef(CONFIG_NXP_LP_FLEXCOMM LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER=1) -zephyr_sources( - soc.c - ) +zephyr_sources(soc.c) + +if(CONFIG_FLASH_MCUX_FLEXSPI_NOR) + zephyr_sources(flash_clock_setup.c) + if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) + zephyr_code_relocate(FILES flash_clock_setup.c LOCATION ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT) + endif() +endif() zephyr_include_directories(.) diff --git a/soc/nxp/mcx/mcxnx4x/Kconfig b/soc/nxp/mcx/mcxnx4x/Kconfig index c36f8b0b001..b3010603d8e 100644 --- a/soc/nxp/mcx/mcxnx4x/Kconfig +++ b/soc/nxp/mcx/mcxnx4x/Kconfig @@ -35,4 +35,29 @@ config MCUX_CORE_SUFFIX default "_cm33_core0" if SOC_MCXN947_CPU0 default "_cm33_core1" if SOC_MCXN947_CPU1 +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi + +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) +DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(DT_FLASH_PARENT_IS_FLEXSPI) + +config FLASH_SIZE + default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ + if $(DT_FLASH_HAS_SIZE_PROP) + +config FLASH_MCUX_FLEXSPI_XIP + bool + default $(DT_FLASH_PARENT_IS_FLEXSPI) + select XIP + help + Allows for the soc to safely initialize the clocks for the + FlexSpi when planning to execute code in FlexSpi Memory. + endif # SOC_SERIES_MCXNX4X diff --git a/soc/nxp/mcx/mcxnx4x/Kconfig.defconfig b/soc/nxp/mcx/mcxnx4x/Kconfig.defconfig index 0c64fdaa649..d5ef60d2578 100644 --- a/soc/nxp/mcx/mcxnx4x/Kconfig.defconfig +++ b/soc/nxp/mcx/mcxnx4x/Kconfig.defconfig @@ -12,23 +12,6 @@ config ROM_START_OFFSET config ZTEST_NO_YIELD default y if (PM && ZTEST) -DT_CHOSEN_Z_FLASH := zephyr,flash -DT_COMPAT_FLEXSPI := nxp,imx-flexspi - -DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) -DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) - -DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) -DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ - if $(DT_FLASH_PARENT_IS_FLEXSPI) - -config FLASH_SIZE - default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ - if $(DT_FLASH_HAS_SIZE_PROP) - if MCUX_OS_TIMER config SYS_CLOCK_HW_CYCLES_PER_SEC diff --git a/soc/nxp/mcx/mcxnx4x/flash_clock_setup.c b/soc/nxp/mcx/mcxnx4x/flash_clock_setup.c new file mode 100644 index 00000000000..c5312873035 --- /dev/null +++ b/soc/nxp/mcx/mcxnx4x/flash_clock_setup.c @@ -0,0 +1,33 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate) +{ + /* PLL0 is set to 150 MHz */ + uint32_t pll_rate = 150000000; + uint8_t divider; + + /* Disable the FLEXSPI clock */ + SYSCON->FLEXSPICLKSEL = 0; + + divider = ((pll_rate + (rate - 1)) / rate) - 1; + /* Max divider value is 8 */ + divider = MIN(divider, 8); + SYSCON->FLEXSPICLKDIV = divider; + + /* Switch FLEXSPI to PLL0 */ + SYSCON->FLEXSPICLKSEL = 1; + + return 0; +} + +void flexspi_clock_safe_config(void) +{ + /* Switch FLEXSPI to FRO_HF */ + SYSCON->FLEXSPICLKSEL = 3; + +} diff --git a/soc/nxp/mcx/mcxnx4x/soc.h b/soc/nxp/mcx/mcxnx4x/soc.h index 185b400f772..d6f88da592f 100644 --- a/soc/nxp/mcx/mcxnx4x/soc.h +++ b/soc/nxp/mcx/mcxnx4x/soc.h @@ -18,6 +18,9 @@ extern "C" { #endif +int flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); +void flexspi_clock_safe_config(void); + #ifdef __cplusplus } #endif From 517753e4758b2ac595d7b9dd3b885f202a673995 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 19 Mar 2024 14:49:00 -0500 Subject: [PATCH 1334/2402] boards: frdm_mcxn947: Add support for the QSPI flash Add support for the QSPI flash connected over FlexSPI Signed-off-by: Mahesh Mahadevan --- boards/nxp/frdm_mcxn947/board.c | 8 ++++ boards/nxp/frdm_mcxn947/doc/index.rst | 2 + .../frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi | 21 ++++++++++ boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 38 +++++++++++++++++++ .../frdm_mcxn947_mcxn947_cpu0.dts | 8 ++++ 5 files changed, 77 insertions(+) diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index 40b3d42fc74..f43964fee6e 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -6,6 +6,7 @@ #include #include #include +#include /* Board xtal frequency in Hz */ #define BOARD_XTAL0_CLK_HZ 24000000U @@ -66,6 +67,13 @@ static int frdm_mcxn947_init(void) /* Enable FRO HF(48MHz) output */ CLOCK_SetupFROHFClocking(48000000U); +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP + /* Call function flexspi_clock_safe_config() to move FleXSPI clock to a stable + * clock source when updating the PLL if in XIP (execute code from FlexSPI memory + */ + flexspi_clock_safe_config(); +#endif + /* Set up PLL0 */ const pll_setup_t pll0Setup = { .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index 171e49eca43..1edcf7c6417 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -63,6 +63,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | FLASH | on-chip | soc flash | +-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ Targets available ================== diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi index f9d6e6d36ae..20da3d13273 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi @@ -16,4 +16,25 @@ input-enable; }; }; + + pinmux_flexspi: pinmux_flexspi { + group0 { + pinmux = , + , + , + , + ; + input-enable; + slew-rate = "fast"; + drive-strength = "low"; + }; + group1 { + pinmux = , + ; + input-enable; + slew-rate = "fast"; + drive-strength = "low"; + bias-pull-up; + }; + }; }; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 97b140c14dc..b0b6304c1f6 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -88,3 +88,41 @@ }; }; }; + +&flexspi { + pinctrl-0 = <&pinmux_flexspi>; + pinctrl-names = "default"; + ahb-prefetch; + ahb-bufferable; + ahb-cacheable; + ahb-read-addr-opt; + combination-mode; + rx-clock-source = <1>; + + /* WINBOND flash memory*/ + w25q64jvssiq: w25q64jvssiq@0 { + compatible = "nxp,imx-flexspi-nor"; + status = "disabled"; + size = <67108864>; + reg = <0>; + spi-max-frequency = <133000000>; + jedec-id = [ef 40 17]; + erase-block-size = <4096>; + write-block-size = <1>; + cs-interval-unit = <1>; + cs-interval = <2>; + cs-hold-time = <3>; + cs-setup-time = <3>; + data-valid-time = <2>; + column-space = <0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + storage_partition: partition@0 { + label = "storage"; + reg = <0x0 DT_SIZE_M(8)>; + }; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts index f69157e4b6f..a22a3623c4b 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts @@ -72,3 +72,11 @@ &flexcomm4_lpuart4 { status = "okay"; }; + +&flexspi { + status = "okay"; +}; + +&w25q64jvssiq { + status = "okay"; +}; From 93d005fc87481a6daaec7a70aca7a315e443f993 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Mon, 18 Mar 2024 08:11:10 -0300 Subject: [PATCH 1335/2402] samples: hwmv2: rename espxx_luatos_core files This board has variant model "usb" and is currently missing hwmv2 changes. Signed-off-by: Sylvio Alves --- ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...sb.conf => esp32c3_luatos_core_esp32c3_usb.conf} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...sb.conf => esp32c3_luatos_core_esp32c3_usb.conf} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... => esp32s3_luatos_core_esp32s3_procpu_usb.conf} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...sb.conf => esp32c3_luatos_core_esp32c3_usb.conf} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...sb.conf => esp32c3_luatos_core_esp32c3_usb.conf} | 0 ...sb.conf => esp32c3_luatos_core_esp32c3_usb.conf} | 0 ... => esp32s3_luatos_core_esp32s3_procpu_usb.conf} | 0 ...sb.conf => esp32c3_luatos_core_esp32c3_usb.conf} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... => esp32s3_luatos_core_esp32s3_procpu_usb.conf} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...sb.conf => esp32c3_luatos_core_esp32c3_usb.conf} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... => esp32s3_luatos_core_esp32s3_procpu_usb.conf} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...sb.conf => esp32c3_luatos_core_esp32c3_usb.conf} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... => esp32s3_luatos_core_esp32s3_procpu_usb.conf} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...sb.conf => esp32c3_luatos_core_esp32c3_usb.conf} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...sb.conf => esp32c3_luatos_core_esp32c3_usb.conf} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... => esp32s3_luatos_core_esp32s3_procpu_usb.conf} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 ...sb.conf => esp32c3_luatos_core_esp32c3_usb.conf} | 0 ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ...conf => esp32s3_luatos_core_esp32s3_procpu.conf} | 0 ...y => esp32s3_luatos_core_esp32s3_procpu.overlay} | 0 ... => esp32s3_luatos_core_esp32s3_procpu_usb.conf} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 .../timer_behavior/boards/esp32s3_devkitm.overlay | 13 ------------- ...rlay => esp32c3_luatos_core_esp32c3_usb.overlay} | 0 ... esp32s3_luatos_core_esp32s3_procpu_usb.overlay} | 0 51 files changed, 13 deletions(-) rename samples/basic/blinky_pwm/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename samples/basic/blinky_pwm/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename samples/boards/esp32/deep_sleep/boards/{esp32c3_luatos_core_usb.conf => esp32c3_luatos_core_esp32c3_usb.conf} (100%) rename samples/boards/esp32/deep_sleep/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename samples/drivers/adc/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename samples/drivers/adc/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename samples/drivers/counter/alarm/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename samples/drivers/counter/alarm/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename samples/net/wifi/boards/{esp32c3_luatos_core_usb.conf => esp32c3_luatos_core_esp32c3_usb.conf} (100%) rename samples/net/wifi/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename samples/net/wifi/boards/{esp32s3_luatos_core_usb.conf => esp32s3_luatos_core_esp32s3_procpu_usb.conf} (100%) rename samples/net/wifi/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename samples/sensor/die_temp_polling/boards/{esp32c3_luatos_core_usb.conf => esp32c3_luatos_core_esp32c3_usb.conf} (100%) rename samples/sensor/die_temp_polling/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename samples/sensor/qdec/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename samples/subsys/nvs/boards/{esp32c3_luatos_core_usb.conf => esp32c3_luatos_core_esp32c3_usb.conf} (100%) rename samples/subsys/settings/boards/{esp32c3_luatos_core_usb.conf => esp32c3_luatos_core_esp32c3_usb.conf} (100%) rename samples/subsys/settings/boards/{esp32s3_luatos_core_usb.conf => esp32s3_luatos_core_esp32s3_procpu_usb.conf} (100%) rename tests/drivers/adc/adc_api/boards/{esp32c3_luatos_core_usb.conf => esp32c3_luatos_core_esp32c3_usb.conf} (100%) rename tests/drivers/adc/adc_api/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename tests/drivers/adc/adc_api/boards/{esp32s3_luatos_core_usb.conf => esp32s3_luatos_core_esp32s3_procpu_usb.conf} (100%) rename tests/drivers/adc/adc_api/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename tests/drivers/counter/counter_basic_api/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename tests/drivers/counter/counter_basic_api/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{esp32c3_luatos_core_usb.conf => esp32c3_luatos_core_esp32c3_usb.conf} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{esp32s3_luatos_core_usb.conf => esp32s3_luatos_core_esp32s3_procpu_usb.conf} (100%) rename tests/drivers/dma/chan_blen_transfer/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename tests/drivers/dma/loop_transfer/boards/{esp32c3_luatos_core_usb.conf => esp32c3_luatos_core_esp32c3_usb.conf} (100%) rename tests/drivers/dma/loop_transfer/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename tests/drivers/dma/loop_transfer/boards/{esp32s3_luatos_core_usb.conf => esp32s3_luatos_core_esp32s3_procpu_usb.conf} (100%) rename tests/drivers/dma/loop_transfer/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename tests/drivers/flash/common/boards/{esp32c3_luatos_core_usb.conf => esp32c3_luatos_core_esp32c3_usb.conf} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename tests/drivers/gpio/gpio_basic_api/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename tests/drivers/pwm/pwm_api/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename tests/drivers/pwm/pwm_api/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename tests/drivers/pwm/pwm_loopback/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{esp32c3_luatos_core_usb.conf => esp32c3_luatos_core_esp32c3_usb.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename tests/drivers/spi/spi_loopback/boards/{esp32s3_luatos_core_usb.conf => esp32s3_luatos_core_esp32s3_procpu_usb.conf} (100%) rename tests/drivers/spi/spi_loopback/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{esp32c3_luatos_core_usb.conf => esp32c3_luatos_core_esp32c3_usb.conf} (100%) rename tests/drivers/uart/uart_async_api/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{esp32s3_luatos_core.conf => esp32s3_luatos_core_esp32s3_procpu.conf} (100%) rename tests/drivers/uart/uart_async_api/boards/{esp32s3_luatos_core.overlay => esp32s3_luatos_core_esp32s3_procpu.overlay} (100%) rename tests/drivers/uart/uart_async_api/boards/{esp32s3_luatos_core_usb.conf => esp32s3_luatos_core_esp32s3_procpu_usb.conf} (100%) rename tests/drivers/uart/uart_async_api/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) delete mode 100644 tests/kernel/timer/timer_behavior/boards/esp32s3_devkitm.overlay rename tests/subsys/debug/coredump_backends/boards/{esp32c3_luatos_core_usb.overlay => esp32c3_luatos_core_esp32c3_usb.overlay} (100%) rename tests/subsys/debug/coredump_backends/boards/{esp32s3_luatos_core_usb.overlay => esp32s3_luatos_core_esp32s3_procpu_usb.overlay} (100%) diff --git a/samples/basic/blinky_pwm/boards/esp32c3_luatos_core_usb.overlay b/samples/basic/blinky_pwm/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from samples/basic/blinky_pwm/boards/esp32c3_luatos_core_usb.overlay rename to samples/basic/blinky_pwm/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/samples/basic/blinky_pwm/boards/esp32s3_luatos_core_usb.overlay b/samples/basic/blinky_pwm/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from samples/basic/blinky_pwm/boards/esp32s3_luatos_core_usb.overlay rename to samples/basic/blinky_pwm/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_usb.conf b/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_esp32c3_usb.conf similarity index 100% rename from samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_usb.conf rename to samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_esp32c3_usb.conf diff --git a/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_usb.overlay b/samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_usb.overlay rename to samples/boards/esp32/deep_sleep/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/samples/drivers/adc/boards/esp32c3_luatos_core_usb.overlay b/samples/drivers/adc/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from samples/drivers/adc/boards/esp32c3_luatos_core_usb.overlay rename to samples/drivers/adc/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/samples/drivers/adc/boards/esp32s3_luatos_core_usb.overlay b/samples/drivers/adc/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from samples/drivers/adc/boards/esp32s3_luatos_core_usb.overlay rename to samples/drivers/adc/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/samples/drivers/counter/alarm/boards/esp32c3_luatos_core_usb.overlay b/samples/drivers/counter/alarm/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/esp32c3_luatos_core_usb.overlay rename to samples/drivers/counter/alarm/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/samples/drivers/counter/alarm/boards/esp32s3_luatos_core_usb.overlay b/samples/drivers/counter/alarm/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/esp32s3_luatos_core_usb.overlay rename to samples/drivers/counter/alarm/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/samples/net/wifi/boards/esp32c3_luatos_core_usb.conf b/samples/net/wifi/boards/esp32c3_luatos_core_esp32c3_usb.conf similarity index 100% rename from samples/net/wifi/boards/esp32c3_luatos_core_usb.conf rename to samples/net/wifi/boards/esp32c3_luatos_core_esp32c3_usb.conf diff --git a/samples/net/wifi/boards/esp32c3_luatos_core_usb.overlay b/samples/net/wifi/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from samples/net/wifi/boards/esp32c3_luatos_core_usb.overlay rename to samples/net/wifi/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/samples/net/wifi/boards/esp32s3_luatos_core_usb.conf b/samples/net/wifi/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf similarity index 100% rename from samples/net/wifi/boards/esp32s3_luatos_core_usb.conf rename to samples/net/wifi/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf diff --git a/samples/net/wifi/boards/esp32s3_luatos_core_usb.overlay b/samples/net/wifi/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from samples/net/wifi/boards/esp32s3_luatos_core_usb.overlay rename to samples/net/wifi/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_usb.conf b/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_esp32c3_usb.conf similarity index 100% rename from samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_usb.conf rename to samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_esp32c3_usb.conf diff --git a/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_usb.overlay b/samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_usb.overlay rename to samples/sensor/die_temp_polling/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/samples/sensor/qdec/boards/esp32s3_luatos_core_usb.overlay b/samples/sensor/qdec/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from samples/sensor/qdec/boards/esp32s3_luatos_core_usb.overlay rename to samples/sensor/qdec/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/samples/subsys/nvs/boards/esp32c3_luatos_core_usb.conf b/samples/subsys/nvs/boards/esp32c3_luatos_core_esp32c3_usb.conf similarity index 100% rename from samples/subsys/nvs/boards/esp32c3_luatos_core_usb.conf rename to samples/subsys/nvs/boards/esp32c3_luatos_core_esp32c3_usb.conf diff --git a/samples/subsys/settings/boards/esp32c3_luatos_core_usb.conf b/samples/subsys/settings/boards/esp32c3_luatos_core_esp32c3_usb.conf similarity index 100% rename from samples/subsys/settings/boards/esp32c3_luatos_core_usb.conf rename to samples/subsys/settings/boards/esp32c3_luatos_core_esp32c3_usb.conf diff --git a/samples/subsys/settings/boards/esp32s3_luatos_core_usb.conf b/samples/subsys/settings/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf similarity index 100% rename from samples/subsys/settings/boards/esp32s3_luatos_core_usb.conf rename to samples/subsys/settings/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf diff --git a/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_usb.conf b/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_esp32c3_usb.conf similarity index 100% rename from tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_usb.conf rename to tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_esp32c3_usb.conf diff --git a/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_usb.overlay b/tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_usb.overlay rename to tests/drivers/adc/adc_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_usb.conf b/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf similarity index 100% rename from tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_usb.conf rename to tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf diff --git a/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_usb.overlay b/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_usb.overlay rename to tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/esp32c3_luatos_core_usb.overlay b/tests/drivers/counter/counter_basic_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/esp32c3_luatos_core_usb.overlay rename to tests/drivers/counter/counter_basic_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/esp32s3_luatos_core_usb.overlay b/tests/drivers/counter/counter_basic_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/esp32s3_luatos_core_usb.overlay rename to tests/drivers/counter/counter_basic_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_usb.conf b/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_esp32c3_usb.conf similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_usb.conf rename to tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_esp32c3_usb.conf diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_usb.overlay b/tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_usb.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_usb.conf b/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_usb.conf rename to tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_usb.overlay b/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_usb.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_usb.conf b/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_esp32c3_usb.conf similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_usb.conf rename to tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_esp32c3_usb.conf diff --git a/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_usb.overlay b/tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_usb.overlay rename to tests/drivers/dma/loop_transfer/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_usb.conf b/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_usb.conf rename to tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf diff --git a/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_usb.overlay b/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_usb.overlay rename to tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/tests/drivers/flash/common/boards/esp32c3_luatos_core_usb.conf b/tests/drivers/flash/common/boards/esp32c3_luatos_core_esp32c3_usb.conf similarity index 100% rename from tests/drivers/flash/common/boards/esp32c3_luatos_core_usb.conf rename to tests/drivers/flash/common/boards/esp32c3_luatos_core_esp32c3_usb.conf diff --git a/tests/drivers/gpio/gpio_basic_api/boards/esp32c3_luatos_core_usb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/esp32c3_luatos_core_usb.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/esp32s3_luatos_core_usb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/esp32s3_luatos_core_usb.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/tests/drivers/pwm/pwm_api/boards/esp32c3_luatos_core_usb.overlay b/tests/drivers/pwm/pwm_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from tests/drivers/pwm/pwm_api/boards/esp32c3_luatos_core_usb.overlay rename to tests/drivers/pwm/pwm_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/tests/drivers/pwm/pwm_api/boards/esp32s3_luatos_core_usb.overlay b/tests/drivers/pwm/pwm_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from tests/drivers/pwm/pwm_api/boards/esp32s3_luatos_core_usb.overlay rename to tests/drivers/pwm/pwm_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/tests/drivers/pwm/pwm_loopback/boards/esp32s3_luatos_core_usb.overlay b/tests/drivers/pwm/pwm_loopback/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from tests/drivers/pwm/pwm_loopback/boards/esp32s3_luatos_core_usb.overlay rename to tests/drivers/pwm/pwm_loopback/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/esp32c3_luatos_core_usb.conf b/tests/drivers/spi/spi_loopback/boards/esp32c3_luatos_core_esp32c3_usb.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/esp32c3_luatos_core_usb.conf rename to tests/drivers/spi/spi_loopback/boards/esp32c3_luatos_core_esp32c3_usb.conf diff --git a/tests/drivers/spi/spi_loopback/boards/esp32c3_luatos_core_usb.overlay b/tests/drivers/spi/spi_loopback/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/esp32c3_luatos_core_usb.overlay rename to tests/drivers/spi/spi_loopback/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/esp32s3_luatos_core_usb.conf b/tests/drivers/spi/spi_loopback/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/esp32s3_luatos_core_usb.conf rename to tests/drivers/spi/spi_loopback/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf diff --git a/tests/drivers/spi/spi_loopback/boards/esp32s3_luatos_core_usb.overlay b/tests/drivers/spi/spi_loopback/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/esp32s3_luatos_core_usb.overlay rename to tests/drivers/spi/spi_loopback/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/esp32c3_luatos_core_usb.conf b/tests/drivers/uart/uart_async_api/boards/esp32c3_luatos_core_esp32c3_usb.conf similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/esp32c3_luatos_core_usb.conf rename to tests/drivers/uart/uart_async_api/boards/esp32c3_luatos_core_esp32c3_usb.conf diff --git a/tests/drivers/uart/uart_async_api/boards/esp32c3_luatos_core_usb.overlay b/tests/drivers/uart/uart_async_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/esp32c3_luatos_core_usb.overlay rename to tests/drivers/uart/uart_async_api/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core.conf b/tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_esp32s3_procpu.conf similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core.conf rename to tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_esp32s3_procpu.conf diff --git a/tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core.overlay b/tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_esp32s3_procpu.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core.overlay rename to tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_esp32s3_procpu.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_usb.conf b/tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_usb.conf rename to tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.conf diff --git a/tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_usb.overlay b/tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_usb.overlay rename to tests/drivers/uart/uart_async_api/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay diff --git a/tests/kernel/timer/timer_behavior/boards/esp32s3_devkitm.overlay b/tests/kernel/timer/timer_behavior/boards/esp32s3_devkitm.overlay deleted file mode 100644 index e8bc477d394..00000000000 --- a/tests/kernel/timer/timer_behavior/boards/esp32s3_devkitm.overlay +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2023 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - resources { - compatible = "test-kernel-timer-behavior-external"; - - timerout-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - }; -}; diff --git a/tests/subsys/debug/coredump_backends/boards/esp32c3_luatos_core_usb.overlay b/tests/subsys/debug/coredump_backends/boards/esp32c3_luatos_core_esp32c3_usb.overlay similarity index 100% rename from tests/subsys/debug/coredump_backends/boards/esp32c3_luatos_core_usb.overlay rename to tests/subsys/debug/coredump_backends/boards/esp32c3_luatos_core_esp32c3_usb.overlay diff --git a/tests/subsys/debug/coredump_backends/boards/esp32s3_luatos_core_usb.overlay b/tests/subsys/debug/coredump_backends/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay similarity index 100% rename from tests/subsys/debug/coredump_backends/boards/esp32s3_luatos_core_usb.overlay rename to tests/subsys/debug/coredump_backends/boards/esp32s3_luatos_core_esp32s3_procpu_usb.overlay From 8d83b76f841a749e91ad643e6fa83c5af2dffe6e Mon Sep 17 00:00:00 2001 From: Armando Visconti Date: Mon, 29 Jan 2024 11:12:41 +0100 Subject: [PATCH 1336/2402] drivers/sensor: add support to STTS22H temperature sensor The STTS22H is an ultralow-power, high-accuracy, digital temperature sensor offering high performance over the entire operating temperature range. This driver is based on stmemsc HAL i/f v2.3 https://www.st.com/resource/en/datasheet/stts22h.pdf Signed-off-by: Armando Visconti --- drivers/sensor/CMakeLists.txt | 1 + drivers/sensor/Kconfig | 1 + drivers/sensor/stts22h/CMakeLists.txt | 12 + drivers/sensor/stts22h/Kconfig | 24 ++ drivers/sensor/stts22h/stts22h.c | 212 ++++++++++++++++++ drivers/sensor/stts22h/stts22h.h | 63 ++++++ drivers/sensor/stts22h/stts22h_trigger.c | 162 +++++++++++++ dts/bindings/sensor/st,stts22h-i2c.yaml | 68 ++++++ include/zephyr/dt-bindings/sensor/stts22h.h | 18 ++ tests/drivers/build_all/sensor/i2c.dtsi | 8 + .../sensor/sensors_trigger_global.conf | 1 + .../sensor/sensors_trigger_none.conf | 1 + .../build_all/sensor/sensors_trigger_own.conf | 1 + 13 files changed, 572 insertions(+) create mode 100644 drivers/sensor/stts22h/CMakeLists.txt create mode 100644 drivers/sensor/stts22h/Kconfig create mode 100644 drivers/sensor/stts22h/stts22h.c create mode 100644 drivers/sensor/stts22h/stts22h.h create mode 100644 drivers/sensor/stts22h/stts22h_trigger.c create mode 100644 dts/bindings/sensor/st,stts22h-i2c.yaml create mode 100644 include/zephyr/dt-bindings/sensor/stts22h.h diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index d553ecd4625..c6725dbc3a2 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -139,6 +139,7 @@ add_subdirectory_ifdef(CONFIG_SM351LT sm351lt) add_subdirectory_ifdef(CONFIG_STM32_TEMP stm32_temp) add_subdirectory_ifdef(CONFIG_STM32_VBAT stm32_vbat) add_subdirectory_ifdef(CONFIG_STM32_VREF stm32_vref) +add_subdirectory_ifdef(CONFIG_STTS22H stts22h) add_subdirectory_ifdef(CONFIG_STTS751 stts751) add_subdirectory_ifdef(CONFIG_SX9500 sx9500) add_subdirectory_ifdef(CONFIG_TACH_IT8XXX2 ite_tach_it8xxx2) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index fa956332534..594778be1d2 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -224,6 +224,7 @@ source "drivers/sensor/sm351lt/Kconfig" source "drivers/sensor/stm32_temp/Kconfig" source "drivers/sensor/stm32_vbat/Kconfig" source "drivers/sensor/stm32_vref/Kconfig" +source "drivers/sensor/stts22h/Kconfig" source "drivers/sensor/stts751/Kconfig" source "drivers/sensor/sx9500/Kconfig" source "drivers/sensor/tcn75a/Kconfig" diff --git a/drivers/sensor/stts22h/CMakeLists.txt b/drivers/sensor/stts22h/CMakeLists.txt new file mode 100644 index 00000000000..526ac3b1a2b --- /dev/null +++ b/drivers/sensor/stts22h/CMakeLists.txt @@ -0,0 +1,12 @@ +# ST Microelectronics STTS22H temperature sensor +# +# Copyright (c) 2024 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 +# +zephyr_library() + +zephyr_library_sources(stts22h.c) +zephyr_library_sources_ifdef(CONFIG_STTS22H_TRIGGER stts22h_trigger.c) + +zephyr_library_include_directories(../stmemsc) diff --git a/drivers/sensor/stts22h/Kconfig b/drivers/sensor/stts22h/Kconfig new file mode 100644 index 00000000000..0adc441659b --- /dev/null +++ b/drivers/sensor/stts22h/Kconfig @@ -0,0 +1,24 @@ +# ST Microelectronics STTS22H temperature sensor + +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +menuconfig STTS22H + bool "STTS22H temperature sensor" + default y + depends on DT_HAS_ST_STTS22H_ENABLED + depends on ZEPHYR_HAL_ST_MODULE + select I2C + select HAS_STMEMSC + select USE_STDC_STTS22H + help + Enable driver for STTS22H I2C-based temperature sensor. + +if STTS22H + +module = STTS22H +thread_priority = 10 +thread_stack_size = 1024 +source "drivers/sensor/Kconfig.trigger_template" + +endif # STTS22H diff --git a/drivers/sensor/stts22h/stts22h.c b/drivers/sensor/stts22h/stts22h.c new file mode 100644 index 00000000000..fe5bb2dc0ff --- /dev/null +++ b/drivers/sensor/stts22h/stts22h.c @@ -0,0 +1,212 @@ +/* ST Microelectronics STTS22H temperature sensor + * + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + * + * Datasheet: + * https://www.st.com/resource/en/datasheet/stts22h.pdf + */ + +#define DT_DRV_COMPAT st_stts22h + +#include +#include +#include +#include +#include +#include +#include + +#include "stts22h.h" + +LOG_MODULE_REGISTER(STTS22H, CONFIG_SENSOR_LOG_LEVEL); + +static inline int stts22h_set_odr_raw(const struct device *dev, stts22h_odr_temp_t odr) +{ + const struct stts22h_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + + return stts22h_temp_data_rate_set(ctx, odr); +} + +static int stts22h_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + struct stts22h_data *data = dev->data; + const struct stts22h_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + int16_t raw_temp; + + if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_AMBIENT_TEMP) { + LOG_ERR("Invalid channel: %d", chan); + return -ENOTSUP; + } + + if (stts22h_temperature_raw_get(ctx, &raw_temp) < 0) { + LOG_ERR("Failed to read sample"); + return -EIO; + } + + data->sample_temp = raw_temp; + + return 0; +} + +static inline void stts22h_temp_convert(struct sensor_value *val, int16_t raw_val) +{ + val->val1 = raw_val / 100; + val->val2 = ((int32_t)raw_val % 100) * 10000; +} + +static int stts22h_channel_get(const struct device *dev, + enum sensor_channel chan, + struct sensor_value *val) +{ + struct stts22h_data *data = dev->data; + + if (chan != SENSOR_CHAN_AMBIENT_TEMP) { + LOG_ERR("Invalid channel: %d", chan); + return -ENOTSUP; + } + + stts22h_temp_convert(val, data->sample_temp); + + return 0; +} + +static const uint8_t stts22h_map[6] = {0, 1, 25, 50, 100, 200}; + +static int stts22h_odr_set(const struct device *dev, + const struct sensor_value *val) +{ + int odr; + + for (odr = 0; odr < ARRAY_SIZE(stts22h_map); odr++) { + if (val->val1 <= stts22h_map[odr]) { + break; + } + } + + switch (odr) { + case 0: + return stts22h_set_odr_raw(dev, STTS22H_POWER_DOWN); + case 1: + return stts22h_set_odr_raw(dev, STTS22H_1Hz); + case 2: + return stts22h_set_odr_raw(dev, STTS22H_25Hz); + case 3: + return stts22h_set_odr_raw(dev, STTS22H_50Hz); + case 4: + return stts22h_set_odr_raw(dev, STTS22H_100Hz); + case 5: + return stts22h_set_odr_raw(dev, STTS22H_200Hz); + default: + LOG_ERR("bad frequency: %d (odr = %d)", val->val1, odr); + return -EINVAL; + } +} + +static int stts22h_attr_set(const struct device *dev, + enum sensor_channel chan, + enum sensor_attribute attr, + const struct sensor_value *val) +{ + if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_AMBIENT_TEMP) { + LOG_ERR("Invalid channel: %d", chan); + return -ENOTSUP; + } + + switch (attr) { + case SENSOR_ATTR_SAMPLING_FREQUENCY: + return stts22h_odr_set(dev, val); + default: + LOG_ERR("Attribute %d not supported.", attr); + return -ENOTSUP; + } + + return 0; +} + +static const struct sensor_driver_api stts22h_api_funcs = { + .attr_set = stts22h_attr_set, + .sample_fetch = stts22h_sample_fetch, + .channel_get = stts22h_channel_get, +#if CONFIG_STTS22H_TRIGGER + .trigger_set = stts22h_trigger_set, +#endif +}; + +static int stts22h_init_chip(const struct device *dev) +{ + const struct stts22h_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + uint8_t chip_id, odr; + + if (stts22h_dev_id_get(ctx, &chip_id) < 0) { + LOG_ERR("Failed reading chip id"); + return -EIO; + } + + LOG_INF("chip id 0x%02x", chip_id); + + if (stts22h_auto_increment_set(ctx, 1) < 0) { + LOG_ERR("Failed to set autoincr"); + return -EIO; + } + + /* set odr from DT */ + odr = cfg->odr; + LOG_INF("sensor odr is %d", odr); + if (stts22h_set_odr_raw(dev, odr) < 0) { + LOG_ERR("Failed to set sampling rate"); + return -EIO; + } + + return 0; +} + +static int stts22h_init(const struct device *dev) +{ + struct stts22h_data *data = dev->data; +#ifdef CONFIG_STTS22H_TRIGGER + const struct stts22h_config *cfg = dev->config; +#endif + + LOG_INF("Initialize device %s", dev->name); + data->dev = dev; + + if (stts22h_init_chip(dev) < 0) { + LOG_ERR("Failed to initialize chip"); + return -EIO; + } + +#ifdef CONFIG_STTS22H_TRIGGER + if (cfg->int_gpio.port) { + if (stts22h_init_interrupt(dev) < 0) { + LOG_ERR("Failed to initialize interrupt."); + return -EIO; + } + } +#endif + + return 0; +} + +#define STTS22H_DEFINE(inst) \ + static struct stts22h_data stts22h_data_##inst; \ + \ + static const struct stts22h_config stts22h_config_##inst = { \ + STMEMSC_CTX_I2C(&stts22h_config_##inst.i2c), \ + .i2c = I2C_DT_SPEC_INST_GET(inst), \ + .temp_hi = DT_INST_PROP(inst, temperature_hi_threshold), \ + .temp_lo = DT_INST_PROP(inst, temperature_lo_threshold), \ + .odr = DT_INST_PROP(inst, sampling_rate), \ + IF_ENABLED(CONFIG_STTS22H_TRIGGER, \ + (.int_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, { 0 }),)) \ + }; \ + \ + SENSOR_DEVICE_DT_INST_DEFINE(inst, stts22h_init, NULL, \ + &stts22h_data_##inst, &stts22h_config_##inst, POST_KERNEL, \ + CONFIG_SENSOR_INIT_PRIORITY, &stts22h_api_funcs); \ + +DT_INST_FOREACH_STATUS_OKAY(STTS22H_DEFINE) diff --git a/drivers/sensor/stts22h/stts22h.h b/drivers/sensor/stts22h/stts22h.h new file mode 100644 index 00000000000..66d2c4e8ca4 --- /dev/null +++ b/drivers/sensor/stts22h/stts22h.h @@ -0,0 +1,63 @@ +/* ST Microelectronics STTS22H temperature sensor + * + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + * + * Datasheet: + * https://www.st.com/resource/en/datasheet/stts22h.pdf + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_STTS22H_STTS22H_H_ +#define ZEPHYR_DRIVERS_SENSOR_STTS22H_STTS22H_H_ + +#include +#include +#include +#include +#include +#include "stts22h_reg.h" + +#include + +struct stts22h_config { + stmdev_ctx_t ctx; + const struct i2c_dt_spec i2c; +#ifdef CONFIG_STTS22H_TRIGGER + const struct gpio_dt_spec int_gpio; +#endif + uint8_t temp_hi; + uint8_t temp_lo; + uint8_t odr; +}; + +struct stts22h_data { + const struct device *dev; + int16_t sample_temp; + +#ifdef CONFIG_STTS22H_TRIGGER + struct gpio_callback gpio_cb; + + const struct sensor_trigger *thsld_trigger; + sensor_trigger_handler_t thsld_handler; + +#if defined(CONFIG_STTS22H_TRIGGER_OWN_THREAD) + K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_STTS22H_THREAD_STACK_SIZE); + struct k_thread thread; + struct k_sem gpio_sem; +#elif defined(CONFIG_STTS22H_TRIGGER_GLOBAL_THREAD) + struct k_work work; +#endif + +#endif /* CONFIG_STTS22H_TRIGGER */ +}; + +#ifdef CONFIG_STTS22H_TRIGGER +int stts22h_trigger_set(const struct device *dev, + const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); + +int stts22h_init_interrupt(const struct device *dev); +#endif + +#endif /* ZEPHYR_DRIVERS_SENSOR_STTS22H_STTS22H_H_ */ diff --git a/drivers/sensor/stts22h/stts22h_trigger.c b/drivers/sensor/stts22h/stts22h_trigger.c new file mode 100644 index 00000000000..05a7a48d726 --- /dev/null +++ b/drivers/sensor/stts22h/stts22h_trigger.c @@ -0,0 +1,162 @@ +/* ST Microelectronics STTS22H temperature sensor + * + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + * + * Datasheet: + * https://www.st.com/resource/en/datasheet/stts22h.pdf + */ + +#define DT_DRV_COMPAT st_stts22h + +#include +#include +#include +#include + +#include "stts22h.h" + +LOG_MODULE_DECLARE(STTS22H, CONFIG_SENSOR_LOG_LEVEL); + +/** + * stts22h_trigger_set - link external trigger to event data ready + */ +int stts22h_trigger_set(const struct device *dev, + const struct sensor_trigger *trig, + sensor_trigger_handler_t handler) +{ + struct stts22h_data *stts22h = dev->data; + const struct stts22h_config *config = dev->config; + + if (!config->int_gpio.port) { + return -ENOTSUP; + } + + if (trig->chan != SENSOR_CHAN_ALL && + trig->chan != SENSOR_CHAN_AMBIENT_TEMP) { + LOG_ERR("Unsupported sensor trigger %d", trig->chan); + return -ENOTSUP; + } + + stts22h->thsld_handler = handler; + stts22h->thsld_trigger = trig; + + return 0; +} + +/** + * stts22h_handle_interrupt - handle the thsld event + * read data and call handler if registered any + */ +static void stts22h_handle_interrupt(const struct device *dev) +{ + struct stts22h_data *stts22h = dev->data; + const struct stts22h_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + stts22h_temp_trlhd_src_t status; + + stts22h_temp_trshld_src_get(ctx, &status); + + if (stts22h->thsld_handler != NULL && + (status.under_thl || status.over_thh)) { + stts22h->thsld_handler(dev, stts22h->thsld_trigger); + } + + gpio_pin_interrupt_configure_dt(&cfg->int_gpio, GPIO_INT_EDGE_TO_ACTIVE); +} + +static void stts22h_gpio_callback(const struct device *dev, + struct gpio_callback *cb, uint32_t pins) +{ + struct stts22h_data *stts22h = + CONTAINER_OF(cb, struct stts22h_data, gpio_cb); + const struct stts22h_config *cfg = stts22h->dev->config; + + ARG_UNUSED(pins); + + gpio_pin_interrupt_configure_dt(&cfg->int_gpio, GPIO_INT_DISABLE); + +#if defined(CONFIG_STTS22H_TRIGGER_OWN_THREAD) + k_sem_give(&stts22h->gpio_sem); +#elif defined(CONFIG_STTS22H_TRIGGER_GLOBAL_THREAD) + k_work_submit(&stts22h->work); +#endif /* CONFIG_STTS22H_TRIGGER_OWN_THREAD */ +} + +#ifdef CONFIG_STTS22H_TRIGGER_OWN_THREAD +static void stts22h_thread(void *p1, void *p2, void *p3) +{ + ARG_UNUSED(p2); + ARG_UNUSED(p3); + + struct stts22h_data *stts22h = p1; + + while (1) { + k_sem_take(&stts22h->gpio_sem, K_FOREVER); + stts22h_handle_interrupt(stts22h->dev); + } +} +#endif /* CONFIG_STTS22H_TRIGGER_OWN_THREAD */ + +#ifdef CONFIG_STTS22H_TRIGGER_GLOBAL_THREAD +static void stts22h_work_cb(struct k_work *work) +{ + struct stts22h_data *stts22h = + CONTAINER_OF(work, struct stts22h_data, work); + + stts22h_handle_interrupt(stts22h->dev); +} +#endif /* CONFIG_STTS22H_TRIGGER_GLOBAL_THREAD */ + +int stts22h_init_interrupt(const struct device *dev) +{ + struct stts22h_data *stts22h = dev->data; + const struct stts22h_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + int ret; + + if (!gpio_is_ready_dt(&cfg->int_gpio)) { + LOG_ERR("GPIO device not ready"); + return -ENODEV; + } + +#if defined(CONFIG_STTS22H_TRIGGER_OWN_THREAD) + k_sem_init(&stts22h->gpio_sem, 0, K_SEM_MAX_LIMIT); + + k_thread_create(&stts22h->thread, stts22h->thread_stack, + CONFIG_STTS22H_THREAD_STACK_SIZE, + stts22h_thread, stts22h, + NULL, NULL, K_PRIO_COOP(CONFIG_STTS22H_THREAD_PRIORITY), + 0, K_NO_WAIT); + k_thread_name_set(&stts22h->thread, dev->name); +#elif defined(CONFIG_STTS22H_TRIGGER_GLOBAL_THREAD) + stts22h->work.handler = stts22h_work_cb; +#endif /* CONFIG_STTS22H_TRIGGER_OWN_THREAD */ + + ret = gpio_pin_configure_dt(&cfg->int_gpio, GPIO_INPUT); + if (ret < 0) { + LOG_DBG("Could not configure gpio"); + return ret; + } + + gpio_init_callback(&stts22h->gpio_cb, stts22h_gpio_callback, BIT(cfg->int_gpio.pin)); + + if (gpio_add_callback(cfg->int_gpio.port, &stts22h->gpio_cb) < 0) { + LOG_DBG("Could not set gpio callback"); + return -EIO; + } + + /* Enable interrupt on high/low temperature threshold */ + if (stts22h_temp_trshld_high_set(ctx, cfg->temp_hi) < 0) { + LOG_DBG("Could not set gpio callback"); + return -EIO; + } + + if (stts22h_temp_trshld_low_set(ctx, cfg->temp_lo) < 0) { + LOG_DBG("Could not set gpio callback"); + return -EIO; + } + + return gpio_pin_interrupt_configure_dt(&cfg->int_gpio, GPIO_INT_EDGE_TO_ACTIVE); +} diff --git a/dts/bindings/sensor/st,stts22h-i2c.yaml b/dts/bindings/sensor/st,stts22h-i2c.yaml new file mode 100644 index 00000000000..36b2e2d2a9a --- /dev/null +++ b/dts/bindings/sensor/st,stts22h-i2c.yaml @@ -0,0 +1,68 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +description: | + STMicroelectronics STTS22H temperature sensor connected to I2C bus + When setting the sampling-rate property in a .dts or .dtsi file you + may include stts22h.h and use the macros defined there. + + Example: + #include + + stts22h: stts22h@0 { + ... + + sampling-rate = ; + }; + +compatible: "st,stts22h" + +include: [sensor-device.yaml, i2c-device.yaml] + +properties: + int-gpios: + type: phandle-array + description: interrupt pin + + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. + + temperature-hi-threshold: + type: int + default: 0 + description: | + HIGH temperature threshold above which an alarm is triggered. + Valid range is 0 to 255. It defaults to 0 (alarm off) which is + the configuration at power-up. This threshold must be calculated + from a temperature T in Celsius using the formula + temperature-hi-threshold = 63 + T/0.64 C. + + + temperature-lo-threshold: + type: int + default: 0 + description: | + LOW temperature threshold below which an alarm is triggered. + Valid range is 0 to 255. It defaults to 0 (alarm off) which is + the configuration at power-up. This threshold must be calculated + from a temperature T in Celsius using the formula + temperature-lo-threshold = 63 + T/0.64 C. + + sampling-rate: + type: int + default: 0x0 + description: | + Specify the default output data rate expressed in samples per second (Hz). + The values are taken in accordance to stts22h_odr_temp_t enumerative in hal/st + module. Default 0x0 (power down) matches the power-up configuration. + + - 0x00 # STTS22H_POWER_DOWN + - 0x01 # STTS22H_ONE_SHOT + - 0x04 # STTS22H_1Hz + - 0x02 # STTS22H_25Hz + - 0x12 # STTS22H_50Hz + - 0x22 # STTS22H_100Hz + - 0x32 # STTS22H_200Hz + + enum: [0x00, 0x01, 0x02, 0x04, 0x12, 0x22, 0x32] diff --git a/include/zephyr/dt-bindings/sensor/stts22h.h b/include/zephyr/dt-bindings/sensor/stts22h.h new file mode 100644 index 00000000000..bf033c818ba --- /dev/null +++ b/include/zephyr/dt-bindings/sensor/stts22h.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_STTS22H_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_STTS22H_H_ + +/* Output Data Rates */ +#define STTS22H_POWER_DOWN 0x00 +#define STTS22H_ONE_SHOT 0x01 +#define STTS22H_1Hz 0x04 +#define STTS22H_25Hz 0x02 +#define STTS22H_50Hz 0x12 +#define STTS22H_100Hz 0x22 +#define STTS22H_200Hz 0x32 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_STTS22H_H_ */ diff --git a/tests/drivers/build_all/sensor/i2c.dtsi b/tests/drivers/build_all/sensor/i2c.dtsi index 6b6a6a98721..a7948313291 100644 --- a/tests/drivers/build_all/sensor/i2c.dtsi +++ b/tests/drivers/build_all/sensor/i2c.dtsi @@ -20,6 +20,7 @@ #include #include #include +#include /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * @@ -985,3 +986,10 @@ test_i2c_max31790: max31790@85 { channel = <6>; }; }; + +test_i2c_stts22h: stts22h@86 { + compatible = "st,stts22h"; + reg = <0x86>; + int-gpios = <&test_gpio 0 0>; + sampling-rate = ; +}; diff --git a/tests/drivers/build_all/sensor/sensors_trigger_global.conf b/tests/drivers/build_all/sensor/sensors_trigger_global.conf index 75d24e13857..d6cdef2021c 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_global.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_global.conf @@ -50,6 +50,7 @@ CONFIG_MPU6050_TRIGGER_GLOBAL_THREAD=y CONFIG_MPU9250_TRIGGER_GLOBAL_THREAD=y CONFIG_SHT3XD_TRIGGER_GLOBAL_THREAD=y CONFIG_SM351LT_TRIGGER_GLOBAL_THREAD=y +CONFIG_STTS22H_TRIGGER_GLOBAL_THREAD=y CONFIG_STTS751_TRIGGER_GLOBAL_THREAD=y CONFIG_SX9500_TRIGGER_GLOBAL_THREAD=y CONFIG_TCN75A_TRIGGER_GLOBAL_THREAD=y diff --git a/tests/drivers/build_all/sensor/sensors_trigger_none.conf b/tests/drivers/build_all/sensor/sensors_trigger_none.conf index 665975a0d62..375e7d8ebe3 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_none.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_none.conf @@ -50,6 +50,7 @@ CONFIG_MPU6050_TRIGGER_NONE=y CONFIG_MPU9250_TRIGGER_NONE=y CONFIG_SHT3XD_TRIGGER_NONE=y CONFIG_SM351LT_TRIGGER_NONE=y +CONFIG_STTS22H_TRIGGER_NONE=y CONFIG_STTS751_TRIGGER_NONE=y CONFIG_SX9500_TRIGGER_NONE=y CONFIG_TCN75A_TRIGGER_NONE=y diff --git a/tests/drivers/build_all/sensor/sensors_trigger_own.conf b/tests/drivers/build_all/sensor/sensors_trigger_own.conf index 71aed7dfaab..76691a6994a 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_own.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_own.conf @@ -49,6 +49,7 @@ CONFIG_MPU6050_TRIGGER_OWN_THREAD=y CONFIG_MPU9250_TRIGGER_OWN_THREAD=y CONFIG_SHT3XD_TRIGGER_OWN_THREAD=y CONFIG_SM351LT_TRIGGER_OWN_THREAD=y +CONFIG_STTS22H_TRIGGER_OWN_THREAD=y CONFIG_STTS751_TRIGGER_OWN_THREAD=y CONFIG_SX9500_TRIGGER_OWN_THREAD=y CONFIG_TCN75A_TRIGGER_OWN_THREAD=y From 2001142bf0bf47a304faca5cda4b9fcc15bbf07e Mon Sep 17 00:00:00 2001 From: Armando Visconti Date: Tue, 30 Jan 2024 17:04:43 +0100 Subject: [PATCH 1337/2402] boards: arm: sensortile_box_pro: add stts22h sensor Extend sensortile_box_pro with stts22h temperature sensor support. Signed-off-by: Armando Visconti --- boards/st/sensortile_box_pro/sensortile_box_pro.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/boards/st/sensortile_box_pro/sensortile_box_pro.dts b/boards/st/sensortile_box_pro/sensortile_box_pro.dts index 951fb52fd81..8bd870151a5 100644 --- a/boards/st/sensortile_box_pro/sensortile_box_pro.dts +++ b/boards/st/sensortile_box_pro/sensortile_box_pro.dts @@ -206,7 +206,7 @@ stm32_lp_tick_source: &lptim1 { int1-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>; int2-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; - drdy-pin = <2>; + drdy-pin = <1>; }; }; @@ -256,6 +256,13 @@ stm32_lp_tick_source: &lptim1 { irq-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; status = "okay"; }; + + stts22h@38 { + compatible = "st,stts22h"; + reg = <0x38>; + int-gpios = <&gpiob 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; }; &i2c2 { From b929cf94e7afe581ede679cfeede63c47a6fb7e4 Mon Sep 17 00:00:00 2001 From: Armando Visconti Date: Tue, 30 Jan 2024 17:06:18 +0100 Subject: [PATCH 1338/2402] sample: board: sensortile_box_pro: add stts22h sensor support Extend sensor sample reading also stts22h temperature data. Signed-off-by: Armando Visconti --- .../sensors-on-board/src/main.c | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/samples/boards/sensortile_box_pro/sensors-on-board/src/main.c b/samples/boards/sensortile_box_pro/sensors-on-board/src/main.c index cc27fc2c125..6ba2e3e226b 100644 --- a/samples/boards/sensortile_box_pro/sensors-on-board/src/main.c +++ b/samples/boards/sensortile_box_pro/sensors-on-board/src/main.c @@ -75,6 +75,16 @@ static void lis2du12_trigger_handler(const struct device *dev, } #endif +#ifdef CONFIG_STTS22H_TRIGGER +static int stts22h_trig_cnt; + +static void stts22h_trigger_handler(const struct device *dev, + const struct sensor_trigger *trig) +{ + stts22h_trig_cnt++; +} +#endif + static void lps22df_config(const struct device *lps22df) { struct sensor_value odr_attr; @@ -201,6 +211,29 @@ static void lis2du12_config(const struct device *lis2du12) #endif } +static void stts22h_config(const struct device *stts22h) +{ + struct sensor_value odr_attr; + + /* set STTS22H sampling frequency to 100 Hz */ + odr_attr.val1 = 100; + odr_attr.val2 = 0; + + if (sensor_attr_set(stts22h, SENSOR_CHAN_AMBIENT_TEMP, + SENSOR_ATTR_SAMPLING_FREQUENCY, &odr_attr) < 0) { + printk("Cannot set sampling frequency for STTS22H\n"); + return; + } + +#ifdef CONFIG_STTS22H_TRIGGER + struct sensor_trigger trig; + + trig.type = SENSOR_TRIG_DATA_READY; + trig.chan = SENSOR_CHAN_AMBIENT_TEMP; + sensor_trigger_set(stts22h, &trig, stts22h_trigger_handler); +#endif +} + static int led_pattern_out(void) { const struct gpio_dt_spec led0_gpio = GPIO_DT_SPEC_GET(DT_ALIAS(led0), gpios); @@ -271,6 +304,7 @@ int main(void) const struct device *const lsm6dsv16x = DEVICE_DT_GET_ONE(st_lsm6dsv16x); const struct device *const lis2mdl = DEVICE_DT_GET_ONE(st_lis2mdl); const struct device *const lis2du12 = DEVICE_DT_GET_ONE(st_lis2du12); + const struct device *const stts22h = DEVICE_DT_GET_ONE(st_stts22h); if (!device_is_ready(hts221)) { printk("%s: device not ready.\n", hts221->name); @@ -292,7 +326,12 @@ int main(void) printk("%s: device not ready.\n", lis2du12->name); return 0; } + if (!device_is_ready(stts22h)) { + printk("%s: device not ready.\n", stts22h->name); + return 0; + } + stts22h_config(stts22h); lis2du12_config(lis2du12); lis2mdl_config(lis2mdl); lps22df_config(lps22df); @@ -305,6 +344,7 @@ int main(void) struct sensor_value lis2mdl_magn[3]; struct sensor_value lis2mdl_temp; struct sensor_value lis2du12_accel[3]; + struct sensor_value stts22h_temp; /* handle HTS221 sensor */ if (sensor_sample_fetch(hts221) < 0) { @@ -340,6 +380,13 @@ int main(void) } #endif +#ifndef CONFIG_STTS22H_TRIGGER + if (sensor_sample_fetch(stts22h) < 0) { + printf("STTS22H Sensor sample update error\n"); + return 0; + } +#endif + sensor_channel_get(hts221, SENSOR_CHAN_HUMIDITY, &hts221_hum); sensor_channel_get(hts221, SENSOR_CHAN_AMBIENT_TEMP, &hts221_temp); sensor_channel_get(lps22df, SENSOR_CHAN_AMBIENT_TEMP, &lps22df_temp); @@ -349,6 +396,7 @@ int main(void) sensor_channel_get(lis2mdl, SENSOR_CHAN_MAGN_XYZ, lis2mdl_magn); sensor_channel_get(lis2mdl, SENSOR_CHAN_DIE_TEMP, &lis2mdl_temp); sensor_channel_get(lis2du12, SENSOR_CHAN_ACCEL_XYZ, lis2du12_accel); + sensor_channel_get(stts22h, SENSOR_CHAN_AMBIENT_TEMP, &stts22h_temp); /* Display sensor data */ @@ -397,6 +445,10 @@ int main(void) sensor_value_to_double(&lis2du12_accel[1]), sensor_value_to_double(&lis2du12_accel[2])); + /* STTS22H temperature */ + printf("STTS22H: Temperature: %.1f C\n", + sensor_value_to_double(&stts22h_temp)); + #ifdef CONFIG_LPS2XDF_TRIGGER printk("%d:: lps22df trig %d\n", cnt, lps22df_trig_cnt); #endif @@ -414,6 +466,10 @@ int main(void) printk("%d:: lis2du12 trig %d\n", cnt, lis2du12_trig_cnt); #endif +#ifdef CONFIG_STTS22H_TRIGGER + printk("%d:: stts22h trig %d\n", cnt, stts22h_trig_cnt); +#endif + k_sleep(K_MSEC(2000)); } } From 06caa9cde648842278118afd91a0adfe51ab194c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 25 Mar 2024 12:27:59 +0100 Subject: [PATCH 1339/2402] boards: infineon: s/cypress/infineon Sphinx reference used cypress instead of infineon. This causes build warnings, as the same tag is part of boards/cypress/index.rst. Signed-off-by: Gerard Marull-Paretas --- boards/infineon/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/infineon/index.rst b/boards/infineon/index.rst index 729b67d60a6..bc2038ec2dc 100644 --- a/boards/infineon/index.rst +++ b/boards/infineon/index.rst @@ -1,4 +1,4 @@ -.. _boards-cypress: +.. _boards-infineon: Infineon Technologies ##################### From bc140e1a36ddd5cbdd71795959a304418f8e61b2 Mon Sep 17 00:00:00 2001 From: Clement Dysli Date: Tue, 30 Jan 2024 18:26:09 +0100 Subject: [PATCH 1340/2402] drivers: input: add cf1133 controller touchscreen The driver allows to use CF1133 controller touchscreen (I2C) Signed-off-by: Clement Dysli --- drivers/input/CMakeLists.txt | 1 + drivers/input/Kconfig | 1 + drivers/input/Kconfig.cf1133 | 29 ++ drivers/input/input_cf1133.c | 334 ++++++++++++++++++++++ dts/bindings/input/sitronix,cf1133.yaml | 18 ++ tests/drivers/build_all/input/app.overlay | 7 + 6 files changed, 390 insertions(+) create mode 100644 drivers/input/Kconfig.cf1133 create mode 100644 drivers/input/input_cf1133.c create mode 100644 dts/bindings/input/sitronix,cf1133.yaml diff --git a/drivers/input/CMakeLists.txt b/drivers/input/CMakeLists.txt index d1f647cd0e9..67311587fd5 100644 --- a/drivers/input/CMakeLists.txt +++ b/drivers/input/CMakeLists.txt @@ -8,6 +8,7 @@ zephyr_library_sources_ifdef(CONFIG_INPUT_ADC_KEYS input_adc_keys.c) zephyr_library_sources_ifdef(CONFIG_INPUT_ANALOG_AXIS input_analog_axis.c) zephyr_library_sources_ifdef(CONFIG_INPUT_ANALOG_AXIS_SETTINGS input_analog_axis_settings.c) zephyr_library_sources_ifdef(CONFIG_INPUT_CAP1203 input_cap1203.c) +zephyr_library_sources_ifdef(CONFIG_INPUT_CF1133 input_cf1133.c) zephyr_library_sources_ifdef(CONFIG_INPUT_CST816S input_cst816s.c) zephyr_library_sources_ifdef(CONFIG_INPUT_ESP32_TOUCH_SENSOR input_esp32_touch_sensor.c) zephyr_library_sources_ifdef(CONFIG_INPUT_FT5336 input_ft5336.c) diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 8c68af65fb2..4562fda5a33 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -9,6 +9,7 @@ menu "Input drivers" source "drivers/input/Kconfig.adc_keys" source "drivers/input/Kconfig.analog_axis" source "drivers/input/Kconfig.cap1203" +source "drivers/input/Kconfig.cf1133" source "drivers/input/Kconfig.cst816s" source "drivers/input/Kconfig.esp32" source "drivers/input/Kconfig.evdev" diff --git a/drivers/input/Kconfig.cf1133 b/drivers/input/Kconfig.cf1133 new file mode 100644 index 00000000000..d3e3a513ed2 --- /dev/null +++ b/drivers/input/Kconfig.cf1133 @@ -0,0 +1,29 @@ +# Copyright (c) 2024 Kickmaker +# SPDX-License-Identifier: Apache-2.0 + +menuconfig INPUT_CF1133 + bool "CF1133 capacitive touch panel driver" + default y + depends on DT_HAS_SITRONIX_CF1133_ENABLED + select I2C + help + Enable driver for Sitronix capacitive touch panel + controller. This driver should support CF1133. + +if INPUT_CF1133 + +config INPUT_CF1133_INTERRUPT + bool "Interrupt" + default y + help + Enable interrupt support (requires all instances + of CF1133 have the INT gpio connected). + +config INPUT_CF1133_PERIOD_MS + int "Sample period" + depends on !INPUT_CF1133_INTERRUPT + default 10 + help + Sample period in milliseconds when in polling mode. + +endif # INPUT_CF1133 diff --git a/drivers/input/input_cf1133.c b/drivers/input/input_cf1133.c new file mode 100644 index 00000000000..4907772f37d --- /dev/null +++ b/drivers/input/input_cf1133.c @@ -0,0 +1,334 @@ +/* + * Copyright (c) 2024, Kickmaker + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Address by default is 0x55 */ + +#define DT_DRV_COMPAT sitronix_cf1133 + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(cf1133, CONFIG_INPUT_LOG_LEVEL); + +/* cf1133 used registers */ +#define FIRMWARE_VERSION 0x0 +#define STATUS_REG 0x1 +#define DEVICE_CONTROL_REG 0x2 +#define TIMEOUT_TO_IDLE_REG 0x3 +#define XY_RESOLUTION_HIGH 0x4 +#define X_RESOLUTION_LOW 0x5 +#define Y_RESOLUTION_LOW 0x6 +#define DEVICE_CONTROL_REG2 0x09 +#define FIRMWARE_REVISION_3 0x0C +#define FIRMWARE_REVISION_2 0x0D +#define FIRMWARE_REVISION_1 0x0E +#define FIRMWARE_REVISION_0 0x0F +#define FINGERS 0x10 +#define KEYS_REG 0x11 +#define XY0_COORD_H 0x12 +#define X0_COORD_L 0x13 +#define Y0_COORD_L 0x14 +#define I2C_PROTOCOL 0x3E +#define MAX_NUM_TOUCHES 0x3F +#define DATA_0_HIGH 0x40 +#define DATA_0_LOW 0x41 +#define MISC_CONTROL 0xF1 +#define SMART_WAKE_UP_REG 0xF2 +#define CHIP_ID 0xF4 +#define PAGE_REG 0xFF + +/* Constants */ +#define SUPPORTED_POINT 0x1 +#define PIXEL_DATA_LENGTH_B 0x3 +#define PIXEL_DATA_LENGTH_A 0x4 +#define SITRONIX_RESERVED_TYPE_0 0x0 +#define SITRONIX_A_TYPE 0x1 +#define SITRONIX_B_TYPE 0x2 + +/* Mask */ +#define ONE_D_SENSING_CONTROL_SHFT GENMASK(1, 1) +#define ONE_D_SENSING_CONTROL_BMSK GENMASK(1, 0) +#define I2C_PROTOCOL_BMSK GENMASK(1, 0) +#define TOUCH_POINT_VALID_MSK GENMASK(7, 7) + +/* Offset for coordinates registers */ +#define XY_COORD_H 0x0 +#define X_COORD_L 0x1 +#define Y_COORD_L 0x2 + +/* CF1133 configuration (DT) */ +struct cf1133_config { + /** I2C bus. */ + struct i2c_dt_spec bus; +#ifdef CONFIG_INPUT_CF1133_INTERRUPT + /** Interrupt GPIO information. */ + struct gpio_dt_spec int_gpio; +#endif +}; + +/* CF1133 data */ +struct cf1133_data { + /** Device pointer. */ + const struct device *dev; + /** Work queue (for deferred read). */ + struct k_work work; +#ifdef CONFIG_INPUT_CF1133_INTERRUPT + /** Interrupt GPIO callback. */ + struct gpio_callback int_gpio_cb; +#else + /* Timer (polling mode) */ + struct k_timer timer; +#endif + /* Last pressed state */ + uint8_t pressed_old : 1; + uint8_t pressed : 1; + + int resolution_x; + int resolution_y; + uint8_t touch_protocol_type; + uint8_t pixel_length; + uint8_t chip_id; +}; + +static int cf1133_get_chip_id(const struct device *dev) +{ + int ret; + uint8_t buffer[3]; + uint8_t num_x; + uint8_t num_y; + const struct cf1133_config *config = dev->config; + struct cf1133_data *data = dev->data; + + ret = i2c_burst_read_dt(&config->bus, CHIP_ID, buffer, sizeof(buffer)); + if (ret < 0) { + LOG_ERR("Read burst failed: %d", ret); + return ret; + } + if (buffer[0] == 0) { + if (buffer[1] + buffer[2] > 32) { + data->chip_id = 2; + } else { + data->chip_id = 0; + } + } else { + data->chip_id = buffer[0]; + } + num_x = buffer[1]; + num_y = buffer[2]; + LOG_DBG("Chip ID = %d, num_x = %d, num_y = %d", data->chip_id, num_x, num_y); + + return 0; +} + +static int cf1133_get_protocol_type(const struct device *dev) +{ + int ret; + uint8_t buffer; + uint8_t sensing_mode; + const struct cf1133_config *config = dev->config; + struct cf1133_data *data = dev->data; + + if (data->chip_id <= 3) { + ret = i2c_reg_read_byte_dt(&config->bus, I2C_PROTOCOL, &buffer); + if (ret < 0) { + LOG_ERR("read i2c protocol failed: %d", ret); + return ret; + } + data->touch_protocol_type = FIELD_GET(I2C_PROTOCOL_BMSK, buffer); + LOG_DBG("i2c protocol = %d", data->touch_protocol_type); + sensing_mode = FIELD_GET(ONE_D_SENSING_CONTROL_BMSK << ONE_D_SENSING_CONTROL_SHFT, + buffer); + LOG_DBG("sensing mode = %d", sensing_mode); + } else { + data->touch_protocol_type = SITRONIX_A_TYPE; + LOG_DBG("i2c protocol = %d", data->touch_protocol_type); + + ret = i2c_reg_read_byte_dt(&config->bus, 0xf0, &buffer); + if (ret < 0) { + LOG_ERR("read sensing mode failed: (%d)", ret); + return ret; + } + sensing_mode = FIELD_GET(ONE_D_SENSING_CONTROL_BMSK, buffer); + LOG_DBG("sensing mode = %d", sensing_mode); + } + return 0; +} + +static int cf1133_ts_init(const struct device *dev) +{ + struct cf1133_data *data = dev->data; + int ret; + + /* Get device status before use to do at least once */ + ret = cf1133_get_chip_id(dev); + if (ret < 0) { + LOG_ERR("Read chip id failed: %d", ret); + return ret; + } + + ret = cf1133_get_protocol_type(dev); + if (ret < 0) { + LOG_ERR("Read protocol failed: %d", ret); + return ret; + } + + if (data->touch_protocol_type == SITRONIX_A_TYPE) { + data->pixel_length = PIXEL_DATA_LENGTH_A; + } else { + data->pixel_length = PIXEL_DATA_LENGTH_B; + } + LOG_DBG("Pixel length: %d", data->pixel_length); + return ret; +} + +static int cf1133_process(const struct device *dev) +{ + const struct cf1133_config *config = dev->config; + struct cf1133_data *data = dev->data; + uint16_t y; + uint16_t x; + int ret; + uint8_t buffer[1 + SUPPORTED_POINT * PIXEL_DATA_LENGTH_A]; + + /* Coordinates are retrieved for one valid touch point detected*/ + ret = i2c_burst_read_dt(&config->bus, KEYS_REG, buffer, + 1 + SUPPORTED_POINT * data->pixel_length); + if (ret < 0) { + LOG_ERR("Read coordinates failed: %d", ret); + return ret; + } + + /* Coordinates for one valid touch point */ + if (buffer[1 + XY_COORD_H] & TOUCH_POINT_VALID_MSK) { + x = (uint16_t)(buffer[1 + XY_COORD_H] & 0x70) << 4 | buffer[1 + X_COORD_L]; + y = (uint16_t)(buffer[1 + XY_COORD_H] & 0x07) << 8 | buffer[1 + Y_COORD_L]; + data->pressed = true; + + if (!data->pressed_old) { + /* Finger pressed */ + input_report_abs(dev, INPUT_ABS_X, x, false, K_FOREVER); + input_report_abs(dev, INPUT_ABS_Y, y, false, K_FOREVER); + input_report_key(dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER); + LOG_DBG("Finger is touching x = %i y = %i", x, y); + } else if (data->pressed_old) { + /* Continuous pressed */ + input_report_abs(dev, INPUT_ABS_X, x, false, K_FOREVER); + input_report_abs(dev, INPUT_ABS_Y, y, false, K_FOREVER); + LOG_DBG("Finger keeps touching x = %i y = %i", x, y); + } + } else { + data->pressed = false; + + if (data->pressed_old) { + /* Finger removed */ + input_report_key(dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER); + LOG_DBG("Finger is removed"); + } + } + + data->pressed_old = data->pressed; + + return 0; +} + +static void cf1133_work_handler(struct k_work *work) +{ + struct cf1133_data *data = CONTAINER_OF(work, struct cf1133_data, work); + + cf1133_process(data->dev); +} + +#ifdef CONFIG_INPUT_CF1133_INTERRUPT + +static void cf1133_isr_handler(const struct device *dev, struct gpio_callback *cb, uint32_t pins) +{ + struct cf1133_data *data = CONTAINER_OF(cb, struct cf1133_data, int_gpio_cb); + + k_work_submit(&data->work); +} +#else +static void cf1133_timer_handler(struct k_timer *timer) +{ + struct cf1133_data *data = CONTAINER_OF(timer, struct cf1133_data, timer); + + k_work_submit(&data->work); +} +#endif + +static int cf1133_init(const struct device *dev) +{ + const struct cf1133_config *config = dev->config; + struct cf1133_data *data = dev->data; + int ret; + + if (!i2c_is_ready_dt(&config->bus)) { + LOG_ERR("I2C controller device not ready"); + return -ENODEV; + } + + data->dev = dev; + k_work_init(&data->work, cf1133_work_handler); + +#ifdef CONFIG_INPUT_CF1133_INTERRUPT + + LOG_DBG("Int conf for TS gpio: %d", &config->int_gpio); + + if (!gpio_is_ready_dt(&config->int_gpio)) { + LOG_ERR("Interrupt GPIO controller device not ready"); + return -ENODEV; + } + + ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT); + if (ret < 0) { + LOG_ERR("Could not configure interrupt GPIO pin"); + return ret; + } + + gpio_init_callback(&data->int_gpio_cb, cf1133_isr_handler, BIT(config->int_gpio.pin)); + + ret = gpio_add_callback(config->int_gpio.port, &data->int_gpio_cb); + if (ret < 0) { + LOG_ERR("Could not set gpio callback"); + return ret; + } + + ret = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE); + if (ret < 0) { + LOG_ERR("Could not configure interrupt GPIO interrupt."); + return ret; + } +#else + LOG_DBG("Timer Mode"); + k_timer_init(&data->timer, cf1133_timer_handler, NULL); + k_timer_start(&data->timer, K_MSEC(CONFIG_INPUT_CF1133_PERIOD_MS), + K_MSEC(CONFIG_INPUT_CF1133_PERIOD_MS)); +#endif + + ret = cf1133_ts_init(dev); + if (ret < 0) { + LOG_ERR("Init information of sensor failed: %d", ret); + return ret; + } + return 0; +} + +#define CF1133_INIT(index) \ + static const struct cf1133_config cf1133_config_##index = { \ + .bus = I2C_DT_SPEC_INST_GET(index), \ + IF_ENABLED(CONFIG_INPUT_CF1133_INTERRUPT, \ + (.int_gpio = GPIO_DT_SPEC_INST_GET(index, int_gpios), \ + )) \ + }; \ + static struct cf1133_data cf1133_data_##index; \ + \ + DEVICE_DT_INST_DEFINE(index, cf1133_init, NULL, &cf1133_data_##index, \ + &cf1133_config_##index, POST_KERNEL, \ + CONFIG_INPUT_INIT_PRIORITY, NULL); + +DT_INST_FOREACH_STATUS_OKAY(CF1133_INIT); diff --git a/dts/bindings/input/sitronix,cf1133.yaml b/dts/bindings/input/sitronix,cf1133.yaml new file mode 100644 index 00000000000..45c7eb56e8e --- /dev/null +++ b/dts/bindings/input/sitronix,cf1133.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2024, Kickmaker +# +# SPDX-License-Identifier: Apache-2.0 + + +description: CF1133 capacitive touch panels + +compatible: "sitronix,cf1133" + +include: i2c-device.yaml + +properties: + int-gpios: + type: phandle-array + description: | + Interrupt GPIO. Used by the controller to signal touch data is + available. Active low. diff --git a/tests/drivers/build_all/input/app.overlay b/tests/drivers/build_all/input/app.overlay index 996af07499a..f5661d5196c 100644 --- a/tests/drivers/build_all/input/app.overlay +++ b/tests/drivers/build_all/input/app.overlay @@ -211,6 +211,13 @@ sleep1-enable; sleep2-enable; }; + + cf1133@6 { + compatible = "sitronix,cf1133"; + reg = <0x6>; + int-gpios = <&test_gpio 0 0>; + }; + }; spi@2 { From 3d81167eafdf60e91a8240d550e0072c73779df8 Mon Sep 17 00:00:00 2001 From: Mayank Mahajan Date: Wed, 24 Jan 2024 16:52:22 +0530 Subject: [PATCH 1341/2402] ADD: GNSS Driver for U-BLOX M10 & Support for UBX Messages MODEM_UBX: Adds Support for UBX Messages in Modem Subsystem. GNSS API Supported: get_supported_systems, set_fix_rate, get_fix_rate, set_enabled_systems, get_enabled_systems, set_navigation_mode, get_navigation_mode. Boards Tested: MIMXRT1062_FMURT6, VMU_RT1170. Note: Partial support for U-BLOX Messages is provided as of now. Signed-off-by: Sumit Batra Signed-off-by: Mayank Mahajan --- drivers/gnss/CMakeLists.txt | 2 + drivers/gnss/Kconfig | 7 + drivers/gnss/Kconfig.u_blox_m10 | 29 + drivers/gnss/gnss_u_blox_m10.c | 1045 +++++++++++++++++ .../gnss_u_blox_protocol.c | 180 +++ .../gnss_u_blox_protocol.h | 251 ++++ .../gnss_u_blox_protocol_defines.h | 258 ++++ dts/bindings/gnss/u-blox,m10.yaml | 17 + include/zephyr/dt-bindings/gnss/u_blox_m10.h | 23 + include/zephyr/modem/ubx.h | 175 +++ .../gnss/boards/mimxrt1062_fmurt6.conf | 4 + .../gnss/boards/mimxrt1062_fmurt6.overlay | 25 + .../drivers/gnss/boards/vmu_rt1170.overlay | 22 + subsys/modem/CMakeLists.txt | 1 + subsys/modem/Kconfig | 15 + subsys/modem/modem_ubx.c | 338 ++++++ 16 files changed, 2392 insertions(+) create mode 100644 drivers/gnss/Kconfig.u_blox_m10 create mode 100644 drivers/gnss/gnss_u_blox_m10.c create mode 100644 drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol.c create mode 100644 drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol.h create mode 100644 drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol_defines.h create mode 100644 dts/bindings/gnss/u-blox,m10.yaml create mode 100644 include/zephyr/dt-bindings/gnss/u_blox_m10.h create mode 100644 include/zephyr/modem/ubx.h create mode 100644 samples/drivers/gnss/boards/mimxrt1062_fmurt6.conf create mode 100644 samples/drivers/gnss/boards/mimxrt1062_fmurt6.overlay create mode 100644 samples/drivers/gnss/boards/vmu_rt1170.overlay create mode 100644 subsys/modem/modem_ubx.c diff --git a/drivers/gnss/CMakeLists.txt b/drivers/gnss/CMakeLists.txt index cfa5c6ed210..32346282c04 100644 --- a/drivers/gnss/CMakeLists.txt +++ b/drivers/gnss/CMakeLists.txt @@ -9,3 +9,5 @@ zephyr_library_sources_ifdef(CONFIG_GNSS_NMEA0183 gnss_nmea0183.c) zephyr_library_sources_ifdef(CONFIG_GNSS_NMEA0183_MATCH gnss_nmea0183_match.c) zephyr_library_sources_ifdef(CONFIG_GNSS_NMEA_GENERIC gnss_nmea_generic.c) zephyr_library_sources_ifdef(CONFIG_GNSS_QUECTEL_LCX6G gnss_quectel_lcx6g.c) +zephyr_library_sources_ifdef(CONFIG_GNSS_U_BLOX_M10 gnss_u_blox_m10.c) +zephyr_library_sources_ifdef(CONFIG_GNSS_U_BLOX_PROTOCOL gnss_u_blox_protocol/gnss_u_blox_protocol.c) diff --git a/drivers/gnss/Kconfig b/drivers/gnss/Kconfig index 2ff552940a3..db9762bd87b 100644 --- a/drivers/gnss/Kconfig +++ b/drivers/gnss/Kconfig @@ -60,11 +60,18 @@ config GNSS_INIT_PRIORITY help Driver initialization priority for GNSS drivers. +config GNSS_U_BLOX_PROTOCOL + bool "GNSS U-BLOX protocol" + select MODEM_UBX + help + Enable gnss u-blox protocol. + module = GNSS module-str = gnss source "subsys/logging/Kconfig.template.log_config" rsource "Kconfig.generic" rsource "Kconfig.quectel_lcx6g" +rsource "Kconfig.u_blox_m10" endif diff --git a/drivers/gnss/Kconfig.u_blox_m10 b/drivers/gnss/Kconfig.u_blox_m10 new file mode 100644 index 00000000000..b651dd69ee9 --- /dev/null +++ b/drivers/gnss/Kconfig.u_blox_m10 @@ -0,0 +1,29 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config GNSS_U_BLOX_M10 + bool "U-BLOX M10 GNSS Module" + default y + depends on GNSS + depends on DT_HAS_U_BLOX_M10_ENABLED + select MODEM_MODULES + select MODEM_BACKEND_UART + select MODEM_CHAT + select MODEM_UBX + select GNSS_PARSE + select GNSS_NMEA0183 + select GNSS_NMEA0183_MATCH + select GNSS_U_BLOX_PROTOCOL + select UART_USE_RUNTIME_CONFIGURE + help + Enable U-BLOX M10 GNSS modem driver. + +config GNSS_U_BLOX_M10_SATELLITES_COUNT + int "Maximum satellite count" + depends on GNSS_SATELLITES + default 24 + help + Maximum number of satellite that the driver that can be decoded from + the GNSS device. This does not affect the number of devices that the + device is actually tracking, just how many of those can be reported + in the satellites callback. diff --git a/drivers/gnss/gnss_u_blox_m10.c b/drivers/gnss/gnss_u_blox_m10.c new file mode 100644 index 00000000000..a5bb8d1e07d --- /dev/null +++ b/drivers/gnss/gnss_u_blox_m10.c @@ -0,0 +1,1045 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gnss_nmea0183.h" +#include "gnss_nmea0183_match.h" +#include "gnss_parse.h" + +#include "gnss_u_blox_protocol/gnss_u_blox_protocol.h" + +#include +LOG_MODULE_REGISTER(ubx_m10, CONFIG_GNSS_LOG_LEVEL); + +#define DT_DRV_COMPAT u_blox_m10 + +#define UART_RECV_BUF_SZ 128 +#define UART_TRNF_BUF_SZ 128 + +#define CHAT_RECV_BUF_SZ 256 +#define CHAT_ARGV_SZ 32 + +#define UBX_RECV_BUF_SZ UBX_FRM_SZ_MAX +#define UBX_TRNS_BUF_SZ UBX_FRM_SZ_MAX +#define UBX_WORK_BUF_SZ UBX_FRM_SZ_MAX + +#define UBX_FRM_BUF_SZ UBX_FRM_SZ_MAX + +#define MODEM_UBX_SCRIPT_TIMEOUT_MS 1000 +#define UBX_M10_SCRIPT_RETRY_DEFAULT 10 + +#define UBX_M10_GNSS_SYS_CNT 8 +#define UBX_M10_GNSS_SUPP_SYS_CNT 6 +/* The datasheet of the device doesn't specify boot time. But 1 sec helped significantly. */ +#define UBX_M10_BOOT_TIME_MS 1000 + +struct ubx_m10_config { + const struct device *uart; + const uint32_t uart_baudrate; +}; + +struct ubx_m10_data { + struct gnss_nmea0183_match_data match_data; +#if CONFIG_GNSS_SATELLITES + struct gnss_satellite satellites[CONFIG_GNSS_U_BLOX_M10_SATELLITES_COUNT]; +#endif + + /* UART backend */ + struct modem_pipe *uart_pipe; + struct modem_backend_uart uart_backend; + uint8_t uart_backend_receive_buf[UART_RECV_BUF_SZ]; + uint8_t uart_backend_transmit_buf[UART_TRNF_BUF_SZ]; + + /* Modem chat */ + struct modem_chat chat; + uint8_t chat_receive_buf[CHAT_RECV_BUF_SZ]; + uint8_t *chat_argv[CHAT_ARGV_SZ]; + + /* Modem ubx */ + struct modem_ubx ubx; + uint8_t ubx_receive_buf[UBX_RECV_BUF_SZ]; + uint8_t ubx_work_buf[UBX_WORK_BUF_SZ]; + + /* Modem ubx script */ + struct modem_ubx_script script; + uint8_t request_buf[UBX_FRM_BUF_SZ]; + uint8_t response_buf[UBX_FRM_BUF_SZ]; + uint8_t match_buf[UBX_FRM_BUF_SZ]; + + struct k_spinlock lock; +}; + +MODEM_CHAT_MATCHES_DEFINE(unsol_matches, + MODEM_CHAT_MATCH_WILDCARD("$??GGA,", ",*", gnss_nmea0183_match_gga_callback), + MODEM_CHAT_MATCH_WILDCARD("$??RMC,", ",*", gnss_nmea0183_match_rmc_callback), +#if CONFIG_GNSS_SATELLITES + MODEM_CHAT_MATCH_WILDCARD("$??GSV,", ",*", gnss_nmea0183_match_gsv_callback), +#endif +); + +static int ubx_m10_resume(const struct device *dev) +{ + struct ubx_m10_data *data = dev->data; + int ret; + + ret = modem_pipe_open(data->uart_pipe); + if (ret < 0) { + return ret; + } + + ret = modem_chat_attach(&data->chat, data->uart_pipe); + if (ret < 0) { + (void)modem_pipe_close(data->uart_pipe); + return ret; + } + + return ret; +} + +static int ubx_m10_turn_off(const struct device *dev) +{ + struct ubx_m10_data *data = dev->data; + + return modem_pipe_close(data->uart_pipe); +} + +static int ubx_m10_init_nmea0183_match(const struct device *dev) +{ + struct ubx_m10_data *data = dev->data; + + const struct gnss_nmea0183_match_config match_config = { + .gnss = dev, +#if CONFIG_GNSS_SATELLITES + .satellites = data->satellites, + .satellites_size = ARRAY_SIZE(data->satellites), +#endif + }; + + return gnss_nmea0183_match_init(&data->match_data, &match_config); +} + +static void ubx_m10_init_pipe(const struct device *dev) +{ + const struct ubx_m10_config *cfg = dev->config; + struct ubx_m10_data *data = dev->data; + + const struct modem_backend_uart_config uart_backend_config = { + .uart = cfg->uart, + .receive_buf = data->uart_backend_receive_buf, + .receive_buf_size = sizeof(data->uart_backend_receive_buf), + .transmit_buf = data->uart_backend_transmit_buf, + .transmit_buf_size = ARRAY_SIZE(data->uart_backend_transmit_buf), + }; + + data->uart_pipe = modem_backend_uart_init(&data->uart_backend, &uart_backend_config); +} + +static uint8_t ubx_m10_char_delimiter[] = {'\r', '\n'}; + +static int ubx_m10_init_chat(const struct device *dev) +{ + struct ubx_m10_data *data = dev->data; + + const struct modem_chat_config chat_config = { + .user_data = data, + .receive_buf = data->chat_receive_buf, + .receive_buf_size = sizeof(data->chat_receive_buf), + .delimiter = ubx_m10_char_delimiter, + .delimiter_size = ARRAY_SIZE(ubx_m10_char_delimiter), + .filter = NULL, + .filter_size = 0, + .argv = data->chat_argv, + .argv_size = ARRAY_SIZE(data->chat_argv), + .unsol_matches = unsol_matches, + .unsol_matches_size = ARRAY_SIZE(unsol_matches), + }; + + return modem_chat_init(&data->chat, &chat_config); +} + +static int ubx_m10_init_ubx(const struct device *dev) +{ + struct ubx_m10_data *data = dev->data; + + const struct modem_ubx_config ubx_config = { + .user_data = data, + .receive_buf = data->ubx_receive_buf, + .receive_buf_size = sizeof(data->ubx_receive_buf), + .work_buf = data->ubx_work_buf, + .work_buf_size = sizeof(data->ubx_work_buf), + }; + + return modem_ubx_init(&data->ubx, &ubx_config); +} + +/** + * @brief Changes modem module (chat or ubx) attached to the uart pipe. + * @param dev Dev instance + * @param change_from_to 0 for changing from "chat" to "ubx", 1 for changing from "ubx" to "chat" + * @returns 0 if successful + * @returns negative errno code if failure + */ +static int ubx_m10_modem_module_change(const struct device *dev, bool change_from_to) +{ + struct ubx_m10_data *data = dev->data; + int ret; + + if (change_from_to == 0) { + modem_chat_release(&data->chat); + ret = modem_ubx_attach(&data->ubx, data->uart_pipe); + } else { /* change_from_to == 1 */ + modem_ubx_release(&data->ubx); + ret = modem_chat_attach(&data->chat, data->uart_pipe); + } + + if (ret < 0) { + (void)modem_pipe_close(data->uart_pipe); + } + + return ret; +} + +static int ubx_m10_modem_ubx_run_script(const struct device *dev, + struct modem_ubx_script *modem_ubx_script_tx) +{ + struct ubx_m10_data *data = dev->data; + int ret; + + ret = ubx_m10_modem_module_change(dev, 0); + if (ret < 0) { + goto reset_modem_module; + } + + ret = modem_ubx_run_script(&data->ubx, modem_ubx_script_tx); + if (ret < 0) { + goto reset_modem_module; + } + +reset_modem_module: + ret |= ubx_m10_modem_module_change(dev, 1); + + return ret; +} + +static void ubx_m10_modem_ubx_script_fill(const struct device *dev) +{ + struct ubx_m10_data *data = dev->data; + + data->script.request = (struct ubx_frame *)data->request_buf; + data->script.response = (struct ubx_frame *)data->response_buf; + data->script.match = (struct ubx_frame *)data->match_buf; + data->script.retry_count = UBX_M10_SCRIPT_RETRY_DEFAULT; + data->script.timeout = K_MSEC(MODEM_UBX_SCRIPT_TIMEOUT_MS); +} + +static int ubx_m10_modem_ubx_script_init(const struct device *dev, void *payload, uint16_t payld_sz, + enum ubx_msg_class msg_cls, enum ubx_config_message msg_id) +{ + int ret; + struct ubx_m10_data *data = dev->data; + struct ubx_cfg_ack_payload match_payload = { + .message_class = msg_cls, + .message_id = msg_id, + }; + + ubx_m10_modem_ubx_script_fill(dev); + + ret = ubx_create_and_validate_frame(data->match_buf, sizeof(data->match_buf), UBX_CLASS_ACK, + UBX_ACK_ACK, &match_payload, UBX_CFG_ACK_PAYLOAD_SZ); + if (ret < 0) { + return ret; + } + + ret = ubx_create_and_validate_frame(data->request_buf, sizeof(data->request_buf), msg_cls, + msg_id, payload, payld_sz); + if (ret < 0) { + return ret; + } + + return ret; +} + +static int ubx_m10_ubx_cfg_rate(const struct device *dev) +{ + int ret; + k_spinlock_key_t key; + struct ubx_m10_data *data = dev->data; + struct ubx_cfg_rate_payload payload; + + key = k_spin_lock(&data->lock); + + ubx_cfg_rate_payload_default(&payload); + + ret = ubx_m10_modem_ubx_script_init(dev, &payload, UBX_CFG_RATE_PAYLOAD_SZ, UBX_CLASS_CFG, + UBX_CFG_RATE); + if (ret < 0) { + goto unlock; + } + + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto unlock; + } + +unlock: + k_spin_unlock(&data->lock, key); + + return ret; +} + +static int ubx_m10_ubx_cfg_prt_set(const struct device *dev, uint32_t target_baudrate, + uint8_t retry) +{ + int ret; + k_spinlock_key_t key; + struct ubx_m10_data *data = dev->data; + struct ubx_cfg_prt_set_payload payload; + + key = k_spin_lock(&data->lock); + + ubx_cfg_prt_set_payload_default(&payload); + payload.baudrate = target_baudrate; + + ret = ubx_m10_modem_ubx_script_init(dev, &payload, UBX_CFG_PRT_SET_PAYLOAD_SZ, + UBX_CLASS_CFG, UBX_CFG_PRT); + if (ret < 0) { + goto unlock; + } + + data->script.retry_count = retry; + /* Returns failure if "target_baudrate" is different than device's currently set baudrate, + * because the device will change its baudrate and respond with UBX-ACK with new baudrate, + * which we will miss. Hence, we need to change uart's baudrate after sending the frame + * (in order to receive response as well), which we are not doing right now. + */ + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto unlock; + } + +unlock: + k_spin_unlock(&data->lock, key); + + return ret; +} + +static int ubx_m10_ubx_cfg_rst(const struct device *dev, uint8_t reset_mode) +{ + int ret; + k_spinlock_key_t key; + struct ubx_m10_data *data = dev->data; + struct ubx_cfg_rst_payload payload; + + key = k_spin_lock(&data->lock); + + ubx_cfg_rst_payload_default(&payload); + + payload.nav_bbr_mask = UBX_CFG_RST_NAV_BBR_MASK_HOT_START; + payload.reset_mode = reset_mode; + + ret = ubx_m10_modem_ubx_script_init(dev, &payload, UBX_CFG_RST_PAYLOAD_SZ, UBX_CLASS_CFG, + UBX_CFG_RST); + if (ret < 0) { + goto unlock; + } + + data->script.match = NULL; + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto unlock; + } + + if (reset_mode == UBX_CFG_RST_RESET_MODE_CONTROLLED_GNSS_STOP) { + k_sleep(K_MSEC(UBX_CFG_RST_WAIT_MS)); + } + +unlock: + k_spin_unlock(&data->lock, key); + + return ret; +} + +static int ubx_m10_set_uart_baudrate(const struct device *dev, uint32_t baudrate) +{ + int ret; + k_spinlock_key_t key; + struct ubx_m10_data *data = dev->data; + const struct ubx_m10_config *config = dev->config; + struct uart_config uart_cfg; + + key = k_spin_lock(&data->lock); + + ret = ubx_m10_turn_off(dev); + if (ret < 0) { + goto reset_and_unlock; + } + + ret = uart_config_get(config->uart, &uart_cfg); + if (ret < 0) { + goto reset_and_unlock; + } + uart_cfg.baudrate = baudrate; + + ret = uart_configure(config->uart, &uart_cfg); + if (ret < 0) { + goto reset_and_unlock; + } + +reset_and_unlock: + ubx_m10_init_pipe(dev); + ret |= ubx_m10_resume(dev); + if (ret < 0) { + goto unlock; + } + +unlock: + k_spin_unlock(&data->lock, key); + + return ret; +} + +static bool ubx_m10_validate_baudrate(const struct device *dev, uint32_t baudrate) +{ + for (int i = 0; i < UBX_BAUDRATE_COUNT; ++i) { + if (baudrate == ubx_baudrate[i]) { + return true; + } + } + + return false; +} + +/* This function will return failure if "target_baudrate" != device's current baudrate. + * Refer the function description of ubx_m10_ubx_cfg_prt_set for a detailed explanation. + */ +static int ubx_m10_configure_gnss_device_baudrate_prerequisite(const struct device *dev) +{ + /* Retry = 1 should be enough, but setting 2 just to be safe. */ + int ret, retry = 2; + const struct ubx_m10_config *config = dev->config; + uint32_t target_baudrate = config->uart_baudrate; + + ret = ubx_m10_validate_baudrate(dev, target_baudrate); + if (ret < 0) { + return ret; + } + + /* Try communication with device with all possible baudrates, because initially we don't + * know the currently set baudrate of the device. We will match the baudrate in one of the + * following attempts and the device will thus change its baudrate to "target_baudrate". + */ + for (int i = 0; i < UBX_BAUDRATE_COUNT; ++i) { + /* Set baudrate of UART pipe as ubx_baudrate[i]. */ + ret = ubx_m10_set_uart_baudrate(dev, ubx_baudrate[i]); + if (ret < 0) { + return ret; + } + + /* Try setting baudrate of device as target_baudrate. */ + ret = ubx_m10_ubx_cfg_prt_set(dev, target_baudrate, retry); + if (ret == 0) { + break; + } + } + + /* Reset baudrate of UART pipe as target_baudrate. */ + ret = ubx_m10_set_uart_baudrate(dev, target_baudrate); + if (ret < 0) { + return ret; + } + + return 0; +} + +static int ubx_m10_configure_gnss_device_baudrate(const struct device *dev) +{ + int ret; + const struct ubx_m10_config *config = dev->config; + uint32_t target_baudrate = config->uart_baudrate; + + ret = ubx_m10_validate_baudrate(dev, target_baudrate); + if (ret < 0) { + return ret; + } + + ret = ubx_m10_ubx_cfg_prt_set(dev, target_baudrate, UBX_M10_SCRIPT_RETRY_DEFAULT); + if (ret < 0) { + return ret; + } + + return 0; +} + +static int ubx_m10_configure_messages(const struct device *dev) +{ + int ret; + k_spinlock_key_t key; + struct ubx_m10_data *data = dev->data; + struct ubx_cfg_msg_payload payload; + + key = k_spin_lock(&data->lock); + + ubx_cfg_msg_payload_default(&payload); + + /* Enabling GGA, RMC and GSV messages. */ + payload.rate = 1; + uint8_t message_enable[] = {UBX_NMEA_GGA, UBX_NMEA_RMC, UBX_NMEA_GSV}; + + for (int i = 0; i < sizeof(message_enable); ++i) { + payload.message_id = message_enable[i]; + ret = ubx_m10_modem_ubx_script_init(dev, &payload, UBX_CFG_MSG_PAYLOAD_SZ, + UBX_CLASS_CFG, UBX_CFG_MSG); + if (ret < 0) { + goto unlock; + } + + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto unlock; + } + } + + /* Disabling DTM, GBS, GLL, GNS, GRS, GSA, GST, VLW, VTG and ZDA messages. */ + payload.rate = 0; + uint8_t message_disable[] = {UBX_NMEA_DTM, UBX_NMEA_GBS, UBX_NMEA_GLL, UBX_NMEA_GNS, + UBX_NMEA_GRS, UBX_NMEA_GSA, UBX_NMEA_GST, UBX_NMEA_VLW, + UBX_NMEA_VTG, UBX_NMEA_ZDA}; + + for (int i = 0; i < sizeof(message_disable); ++i) { + payload.message_id = message_disable[i]; + ret = ubx_m10_modem_ubx_script_init(dev, &payload, UBX_CFG_MSG_PAYLOAD_SZ, + UBX_CLASS_CFG, UBX_CFG_MSG); + if (ret < 0) { + goto unlock; + } + + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto unlock; + } + } + +unlock: + k_spin_unlock(&data->lock, key); + + return ret; +} + +static int ubx_m10_navigation_mode_to_ubx_dynamic_model(const struct device *dev, + enum gnss_navigation_mode mode) +{ + switch (mode) { + case GNSS_NAVIGATION_MODE_ZERO_DYNAMICS: + return UBX_DYN_MODEL_STATIONARY; + case GNSS_NAVIGATION_MODE_LOW_DYNAMICS: + return UBX_DYN_MODEL_PORTABLE; + case GNSS_NAVIGATION_MODE_BALANCED_DYNAMICS: + return UBX_DYN_MODEL_AIRBONE1G; + case GNSS_NAVIGATION_MODE_HIGH_DYNAMICS: + return UBX_DYN_MODEL_AIRBONE4G; + default: + return -EINVAL; + } +} + +static int ubx_m10_ubx_dynamic_model_to_navigation_mode(const struct device *dev, + enum ubx_dynamic_model dynamic_model) +{ + switch (dynamic_model) { + case UBX_DYN_MODEL_PORTABLE: + return GNSS_NAVIGATION_MODE_LOW_DYNAMICS; + case UBX_DYN_MODEL_STATIONARY: + return GNSS_NAVIGATION_MODE_ZERO_DYNAMICS; + case UBX_DYN_MODEL_PEDESTRIAN: + return GNSS_NAVIGATION_MODE_LOW_DYNAMICS; + case UBX_DYN_MODEL_AUTOMOTIV: + return GNSS_NAVIGATION_MODE_LOW_DYNAMICS; + case UBX_DYN_MODEL_SEA: + return GNSS_NAVIGATION_MODE_BALANCED_DYNAMICS; + case UBX_DYN_MODEL_AIRBONE1G: + return GNSS_NAVIGATION_MODE_BALANCED_DYNAMICS; + case UBX_DYN_MODEL_AIRBONE2G: + return GNSS_NAVIGATION_MODE_BALANCED_DYNAMICS; + case UBX_DYN_MODEL_AIRBONE4G: + return GNSS_NAVIGATION_MODE_HIGH_DYNAMICS; + case UBX_DYN_MODEL_WIRST: + return GNSS_NAVIGATION_MODE_BALANCED_DYNAMICS; + case UBX_DYN_MODEL_BIKE: + return GNSS_NAVIGATION_MODE_HIGH_DYNAMICS; + default: + return -EINVAL; + } +} + +static int ubx_m10_set_navigation_mode(const struct device *dev, enum gnss_navigation_mode mode) +{ + int ret; + k_spinlock_key_t key; + struct ubx_m10_data *data = dev->data; + struct ubx_cfg_nav5_payload payload; + + key = k_spin_lock(&data->lock); + + ubx_cfg_nav5_payload_default(&payload); + + ret = ubx_m10_navigation_mode_to_ubx_dynamic_model(dev, mode); + if (ret < 0) { + goto unlock; + } + + payload.dyn_model = ret; + + ret = ubx_m10_modem_ubx_script_init(dev, &payload, UBX_CFG_NAV5_PAYLOAD_SZ, UBX_CLASS_CFG, + UBX_CFG_NAV5); + if (ret < 0) { + goto unlock; + } + + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto unlock; + } + + k_sleep(K_MSEC(UBX_CFG_NAV5_WAIT_MS)); + +unlock: + k_spin_unlock(&data->lock, key); + + return ret; +} + +static int ubx_m10_get_navigation_mode(const struct device *dev, enum gnss_navigation_mode *mode) +{ + int ret; + k_spinlock_key_t key; + struct ubx_m10_data *data = dev->data; + enum ubx_dynamic_model dynamic_model; + + key = k_spin_lock(&data->lock); + + ret = ubx_m10_modem_ubx_script_init(dev, NULL, UBX_FRM_GET_PAYLOAD_SZ, UBX_CLASS_CFG, + UBX_CFG_NAV5); + if (ret < 0) { + goto unlock; + } + + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto unlock; + } + + struct ubx_frame *response = data->script.response; + + dynamic_model = ((struct ubx_cfg_nav5_payload *)response->payload_and_checksum)->dyn_model; + ret = ubx_m10_ubx_dynamic_model_to_navigation_mode(dev, dynamic_model); + if (ret < 0) { + goto unlock; + } + + *mode = ret; + +unlock: + k_spin_unlock(&data->lock, key); + + return ret; +} + +static int ubx_m10_get_supported_systems(const struct device *dev, gnss_systems_t *systems) +{ + *systems = (GNSS_SYSTEM_GPS | GNSS_SYSTEM_GLONASS | GNSS_SYSTEM_GALILEO | + GNSS_SYSTEM_BEIDOU | GNSS_SYSTEM_SBAS | GNSS_SYSTEM_QZSS); + + return 0; +} + +static int ubx_m10_ubx_gnss_id_to_gnss_system(const struct device *dev, enum ubx_gnss_id gnss_id) +{ + switch (gnss_id) { + case UBX_GNSS_ID_GPS: + return GNSS_SYSTEM_GPS; + case UBX_GNSS_ID_SBAS: + return GNSS_SYSTEM_SBAS; + case UBX_GNSS_ID_GALILEO: + return GNSS_SYSTEM_GALILEO; + case UBX_GNSS_ID_BEIDOU: + return GNSS_SYSTEM_BEIDOU; + case UBX_GNSS_ID_QZSS: + return GNSS_SYSTEM_QZSS; + case UBX_GNSS_ID_GLONASS: + return GNSS_SYSTEM_GLONASS; + default: + return -EINVAL; + }; +} + +static int ubx_m10_config_block_fill(const struct device *dev, gnss_systems_t gnss_system, + struct ubx_cfg_gnss_payload *payload, uint8_t index, + uint32_t enable) +{ + uint32_t signal_config; + + switch (gnss_system) { + case GNSS_SYSTEM_GPS: + payload->config_blocks[index].gnss_id = UBX_GNSS_ID_GPS; + signal_config = UBX_CFG_GNSS_FLAG_SGN_CNF_GPS_L1C_A; + break; + case GNSS_SYSTEM_GLONASS: + payload->config_blocks[index].gnss_id = UBX_GNSS_ID_GLONASS; + signal_config = UBX_CFG_GNSS_FLAG_SGN_CNF_GLONASS_L1; + break; + case GNSS_SYSTEM_GALILEO: + payload->config_blocks[index].gnss_id = UBX_GNSS_ID_GALILEO; + signal_config = UBX_CFG_GNSS_FLAG_SGN_CNF_GALILEO_E1; + break; + case GNSS_SYSTEM_BEIDOU: + payload->config_blocks[index].gnss_id = UBX_GNSS_ID_BEIDOU; + signal_config = UBX_CFG_GNSS_FLAG_SGN_CNF_BEIDOU_B1I; + break; + case GNSS_SYSTEM_QZSS: + payload->config_blocks[index].gnss_id = UBX_GNSS_ID_QZSS; + signal_config = UBX_CFG_GNSS_FLAG_SGN_CNF_QZSS_L1C_A; + break; + case GNSS_SYSTEM_SBAS: + payload->config_blocks[index].gnss_id = UBX_GNSS_ID_SBAS; + signal_config = UBX_CFG_GNSS_FLAG_SGN_CNF_SBAS_L1C_A; + break; + default: + return -EINVAL; + }; + + payload->config_blocks[index].flags = enable | signal_config; + + return 0; +} + +static int ubx_m10_set_enabled_systems(const struct device *dev, gnss_systems_t systems) +{ + int ret; + k_spinlock_key_t key; + struct ubx_m10_data *data = dev->data; + + key = k_spin_lock(&data->lock); + + struct ubx_cfg_gnss_payload *payload; + + /* Get number of tracking channels for each supported gnss system by sending CFG-GNSS. */ + ret = ubx_m10_modem_ubx_script_init(dev, NULL, UBX_FRM_GET_PAYLOAD_SZ, UBX_CLASS_CFG, + UBX_CFG_GNSS); + if (ret < 0) { + goto unlock; + } + + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto unlock; + } + + struct ubx_frame *response = data->script.response; + uint16_t res_trk_ch_sum = 0, max_trk_ch_sum = 0; + + /* Calculate sum of reserved and maximum tracking channels for each supported gnss system, + * and assert that the sum is not greater than the number of tracking channels in use. + */ + payload = (struct ubx_cfg_gnss_payload *) response->payload_and_checksum; + for (int i = 0; i < payload->num_config_blocks; ++i) { + ret = ubx_m10_ubx_gnss_id_to_gnss_system(dev, payload->config_blocks[i].gnss_id); + if (ret < 0) { + ret = -EINVAL; + goto unlock; + } + + if (ret & systems) { + res_trk_ch_sum += payload->config_blocks[i].num_res_trk_ch; + max_trk_ch_sum += payload->config_blocks[i].max_num_trk_ch; + } + + if (res_trk_ch_sum > payload->num_trk_ch_use || + max_trk_ch_sum > payload->num_trk_ch_use) { + ret = -EINVAL; + goto unlock; + } + } + + /* Prepare payload (payload) for sending CFG-GNSS for enabling the gnss systems. */ + payload = malloc(sizeof(*payload) + + sizeof(struct ubx_cfg_gnss_payload_config_block) * UBX_M10_GNSS_SUPP_SYS_CNT); + payload->num_config_blocks = UBX_M10_GNSS_SUPP_SYS_CNT; + + ubx_cfg_gnss_payload_default(payload); + + uint8_t filled_blocks = 0; + gnss_systems_t supported_systems; + + ret = ubx_m10_get_supported_systems(dev, &supported_systems); + if (ret < 0) { + goto free_and_unlock; + } + + for (int i = 0; i < UBX_M10_GNSS_SYS_CNT; ++i) { + gnss_systems_t gnss_system = 1 << i; + + if (gnss_system & supported_systems) { + uint32_t enable = (systems & gnss_system) ? + UBX_CFG_GNSS_FLAG_ENABLE : UBX_CFG_GNSS_FLAG_DISABLE; + + ret = ubx_m10_config_block_fill(dev, gnss_system, payload, filled_blocks, + enable); + if (ret < 0) { + goto free_and_unlock; + } + + ++filled_blocks; + } + } + + ret = ubx_m10_modem_ubx_script_init(dev, payload, + UBX_CFG_GNSS_PAYLOAD_SZ(UBX_M10_GNSS_SUPP_SYS_CNT), + UBX_CLASS_CFG, UBX_CFG_GNSS); + if (ret < 0) { + goto free_and_unlock; + } + + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto free_and_unlock; + } + + k_sleep(K_MSEC(UBX_CFG_GNSS_WAIT_MS)); + +free_and_unlock: + free(payload); + +unlock: + k_spin_unlock(&data->lock, key); + + return ret; +} + +static int ubx_m10_get_enabled_systems(const struct device *dev, gnss_systems_t *systems) +{ + int ret; + k_spinlock_key_t key; + struct ubx_m10_data *data = dev->data; + + key = k_spin_lock(&data->lock); + + ret = ubx_m10_modem_ubx_script_init(dev, NULL, UBX_FRM_GET_PAYLOAD_SZ, UBX_CLASS_CFG, + UBX_CFG_GNSS); + if (ret < 0) { + goto unlock; + } + + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto unlock; + } + + struct ubx_frame *response = data->script.response; + struct ubx_cfg_gnss_payload *payload = + (struct ubx_cfg_gnss_payload *) response->payload_and_checksum; + + *systems = 0; + for (int i = 0; i < payload->num_config_blocks; ++i) { + if (payload->config_blocks[i].flags & UBX_CFG_GNSS_FLAG_ENABLE) { + enum ubx_gnss_id gnss_id = payload->config_blocks[i].gnss_id; + + ret = ubx_m10_ubx_gnss_id_to_gnss_system(dev, gnss_id); + if (ret < 0) { + goto unlock; + } + + *systems |= ret; + } + } + +unlock: + k_spin_unlock(&data->lock, key); + + return ret; +} + +static int ubx_m10_set_fix_rate(const struct device *dev, uint32_t fix_interval_ms) +{ + int ret; + k_spinlock_key_t key; + struct ubx_m10_data *data = dev->data; + struct ubx_cfg_rate_payload payload; + + if (fix_interval_ms < 50) { + return -1; + } + + key = k_spin_lock(&data->lock); + + ubx_cfg_rate_payload_default(&payload); + payload.meas_rate_ms = fix_interval_ms; + + ret = ubx_m10_modem_ubx_script_init(dev, &payload, UBX_CFG_RATE_PAYLOAD_SZ, UBX_CLASS_CFG, + UBX_CFG_RATE); + if (ret < 0) { + goto unlock; + } + + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto unlock; + } + +unlock: + k_spin_unlock(&data->lock, key); + + return ret; +} + +static int ubx_m10_get_fix_rate(const struct device *dev, uint32_t *fix_interval_ms) +{ + int ret; + k_spinlock_key_t key; + struct ubx_m10_data *data = dev->data; + struct ubx_cfg_rate_payload *payload; + + key = k_spin_lock(&data->lock); + + ret = ubx_m10_modem_ubx_script_init(dev, NULL, UBX_FRM_GET_PAYLOAD_SZ, UBX_CLASS_CFG, + UBX_CFG_RATE); + if (ret < 0) { + goto unlock; + } + + ret = ubx_m10_modem_ubx_run_script(dev, &(data->script)); + if (ret < 0) { + goto unlock; + } + + struct ubx_frame *response = data->script.response; + + payload = (struct ubx_cfg_rate_payload *) response->payload_and_checksum; + *fix_interval_ms = payload->meas_rate_ms; + +unlock: + k_spin_unlock(&data->lock, key); + + return ret; +} + +static struct gnss_driver_api gnss_api = { + .set_fix_rate = ubx_m10_set_fix_rate, + .get_fix_rate = ubx_m10_get_fix_rate, + .set_navigation_mode = ubx_m10_set_navigation_mode, + .get_navigation_mode = ubx_m10_get_navigation_mode, + .set_enabled_systems = ubx_m10_set_enabled_systems, + .get_enabled_systems = ubx_m10_get_enabled_systems, + .get_supported_systems = ubx_m10_get_supported_systems, +}; + +static int ubx_m10_configure(const struct device *dev) +{ + int ret; + + /* The return value could be ignored. See function description for more details. */ + (void)ubx_m10_configure_gnss_device_baudrate_prerequisite(dev); + + /* Stopping GNSS messages for clearer communication while configuring the device. */ + ret = ubx_m10_ubx_cfg_rst(dev, UBX_CFG_RST_RESET_MODE_CONTROLLED_GNSS_STOP); + if (ret < 0) { + goto reset; + } + + ret = ubx_m10_ubx_cfg_rate(dev); + if (ret < 0) { + LOG_ERR("Configuring rate failed. Returned %d.", ret); + goto reset; + } + + ret = ubx_m10_configure_gnss_device_baudrate(dev); + if (ret < 0) { + LOG_ERR("Configuring baudrate failed. Returned %d.", ret); + goto reset; + } + + ret = ubx_m10_configure_messages(dev); + if (ret < 0) { + LOG_ERR("Configuring messages failed. Returned %d.", ret); + goto reset; + } + +reset: + ret = ubx_m10_ubx_cfg_rst(dev, UBX_CFG_RST_RESET_MODE_CONTROLLED_GNSS_START); + if (ret < 0) { + goto reset; + } + + return ret; +} + +static int ubx_m10_init(const struct device *dev) +{ + int ret; + + k_sleep(K_MSEC(UBX_M10_BOOT_TIME_MS)); + + ret = ubx_m10_init_nmea0183_match(dev); + if (ret < 0) { + return ret; + } + + ubx_m10_init_pipe(dev); + + ret = ubx_m10_init_chat(dev); + if (ret < 0) { + return ret; + } + + ret = ubx_m10_init_ubx(dev); + if (ret < 0) { + return ret; + } + + ret = ubx_m10_resume(dev); + if (ret < 0) { + return ret; + } + + ret = ubx_m10_configure(dev); + if (ret < 0) { + return ret; + } + + return 0; +} + +#define UBX_M10(inst) \ + static struct ubx_m10_config ubx_m10_cfg_##inst = { \ + .uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \ + .uart_baudrate = DT_PROP(DT_DRV_INST(inst), uart_baudrate), \ + }; \ + \ + static struct ubx_m10_data ubx_m10_data_##inst = { \ + .script.request = (struct ubx_frame *)ubx_m10_data_##inst.request_buf, \ + .script.response = (struct ubx_frame *)ubx_m10_data_##inst.response_buf, \ + .script.match = (struct ubx_frame *)ubx_m10_data_##inst.match_buf, \ + .script.retry_count = UBX_M10_SCRIPT_RETRY_DEFAULT, \ + .script.timeout = K_MSEC(MODEM_UBX_SCRIPT_TIMEOUT_MS), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(inst, \ + ubx_m10_init, \ + NULL, \ + &ubx_m10_data_##inst, \ + &ubx_m10_cfg_##inst, \ + POST_KERNEL, \ + CONFIG_GNSS_INIT_PRIORITY, \ + &gnss_api); + +DT_INST_FOREACH_STATUS_OKAY(UBX_M10) diff --git a/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol.c b/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol.c new file mode 100644 index 00000000000..d9a42baa1ba --- /dev/null +++ b/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol.c @@ -0,0 +1,180 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "gnss_u_blox_protocol.h" + +const uint32_t ubx_baudrate[UBX_BAUDRATE_COUNT] = { + 4800, + 9600, + 19200, + 38400, + 57600, + 115200, + 230400, + 460800, + 921600, +}; + +static inline int ubx_validate_payload_size_ack(uint8_t msg_id, uint16_t payload_size) +{ + switch (msg_id) { + case UBX_ACK_ACK: + return payload_size == UBX_CFG_ACK_PAYLOAD_SZ ? 0 : -1; + case UBX_ACK_NAK: + return payload_size == UBX_CFG_NAK_PAYLOAD_SZ ? 0 : -1; + default: + return -1; + } +} + +static inline int ubx_validate_payload_size_cfg(uint8_t msg_id, uint16_t payload_size) +{ + switch (msg_id) { + case UBX_CFG_RATE: + return payload_size == UBX_CFG_RATE_PAYLOAD_SZ ? 0 : -1; + case UBX_CFG_PRT: + return (payload_size == UBX_CFG_PRT_POLL_PAYLOAD_SZ || + payload_size == UBX_CFG_PRT_SET_PAYLOAD_SZ) ? 0 : -1; + case UBX_CFG_RST: + return payload_size == UBX_CFG_RST_PAYLOAD_SZ ? 0 : -1; + case UBX_CFG_NAV5: + return payload_size == UBX_CFG_NAV5_PAYLOAD_SZ ? 0 : -1; + case UBX_CFG_GNSS: + return ((payload_size - UBX_CFG_GNSS_PAYLOAD_INIT_SZ) % + UBX_CFG_GNSS_PAYLOAD_CFG_BLK_SZ == 0) ? 0 : -1; + case UBX_CFG_MSG: + return payload_size == UBX_CFG_MSG_PAYLOAD_SZ ? 0 : -1; + default: + return -1; + } +} + +static inline int ubx_validate_payload_size(uint8_t msg_cls, uint8_t msg_id, uint16_t payload_size) +{ + if (payload_size == 0) { + return 0; + } + + if (payload_size > UBX_PAYLOAD_SZ_MAX) { + return -1; + } + + switch (msg_cls) { + case UBX_CLASS_ACK: + return ubx_validate_payload_size_ack(msg_id, payload_size); + case UBX_CLASS_CFG: + return ubx_validate_payload_size_cfg(msg_id, payload_size); + default: + return -1; + } +} + +int ubx_create_and_validate_frame(uint8_t *ubx_frame, uint16_t ubx_frame_size, uint8_t msg_cls, + uint8_t msg_id, const void *payload, uint16_t payload_size) +{ + if (ubx_validate_payload_size(msg_cls, msg_id, payload_size)) { + return -1; + } + + return modem_ubx_create_frame(ubx_frame, ubx_frame_size, msg_cls, msg_id, payload, + payload_size); +} + +void ubx_cfg_ack_payload_default(struct ubx_cfg_ack_payload *payload) +{ + payload->message_class = UBX_CLASS_CFG; + payload->message_id = UBX_CFG_PRT; +} + +void ubx_cfg_rate_payload_default(struct ubx_cfg_rate_payload *payload) +{ + payload->meas_rate_ms = 1000; + payload->nav_rate = 1; + payload->time_ref = UBX_CFG_RATE_TIME_REF_UTC; +} + +void ubx_cfg_prt_poll_payload_default(struct ubx_cfg_prt_poll_payload *payload) +{ + payload->port_id = UBX_PORT_NUMBER_UART; +} + +void ubx_cfg_prt_set_payload_default(struct ubx_cfg_prt_set_payload *payload) +{ + payload->port_id = UBX_PORT_NUMBER_UART; + payload->reserved0 = UBX_CFG_PRT_RESERVED0; + payload->tx_ready_pin_conf = UBX_CFG_PRT_TX_READY_PIN_CONF_POL_HIGH; + payload->port_mode = UBX_CFG_PRT_PORT_MODE_CHAR_LEN_8 | UBX_CFG_PRT_PORT_MODE_PARITY_NONE | + UBX_CFG_PRT_PORT_MODE_STOP_BITS_1; + payload->baudrate = ubx_baudrate[3]; + payload->in_proto_mask = UBX_CFG_PRT_IN_PROTO_UBX | UBX_CFG_PRT_IN_PROTO_NMEA | + UBX_CFG_PRT_IN_PROTO_RTCM; + payload->out_proto_mask = UBX_CFG_PRT_OUT_PROTO_UBX | UBX_CFG_PRT_OUT_PROTO_NMEA | + UBX_CFG_PRT_OUT_PROTO_RTCM3; + payload->flags = UBX_CFG_PRT_FLAGS_DEFAULT; + payload->reserved1 = UBX_CFG_PRT_RESERVED1; +} + +void ubx_cfg_rst_payload_default(struct ubx_cfg_rst_payload *payload) +{ + payload->nav_bbr_mask = UBX_CFG_RST_NAV_BBR_MASK_HOT_START; + payload->reset_mode = UBX_CFG_RST_RESET_MODE_CONTROLLED_SOFT_RESET; + payload->reserved0 = UBX_CFG_RST_RESERVED0; +} + +void ubx_cfg_nav5_payload_default(struct ubx_cfg_nav5_payload *payload) +{ + payload->mask = UBX_CFG_NAV5_MASK_ALL; + payload->dyn_model = UBX_DYN_MODEL_PORTABLE; + + payload->fix_mode = UBX_FIX_AUTO_FIX; + + payload->fixed_alt = UBX_CFG_NAV5_FIXED_ALT_DEFAULT; + payload->fixed_alt_var = UBX_CFG_NAV5_FIXED_ALT_VAR_DEFAULT; + + payload->min_elev = UBX_CFG_NAV5_MIN_ELEV_DEFAULT; + payload->dr_limit = UBX_CFG_NAV5_DR_LIMIT_DEFAULT; + + payload->p_dop = UBX_CFG_NAV5_P_DOP_DEFAULT; + payload->t_dop = UBX_CFG_NAV5_T_DOP_DEFAULT; + payload->p_acc = UBX_CFG_NAV5_P_ACC_DEFAULT; + payload->t_acc = UBX_CFG_NAV5_T_ACC_DEFAULT; + + payload->static_hold_threshold = UBX_CFG_NAV5_STATIC_HOLD_THRESHOLD_DEFAULT; + payload->dgnss_timeout = UBX_CFG_NAV5_DGNSS_TIMEOUT_DEFAULT; + payload->cno_threshold_num_svs = UBX_CFG_NAV5_CNO_THRESHOLD_NUM_SVS_DEFAULT; + payload->cno_threshold = UBX_CFG_NAV5_CNO_THRESHOLD_DEFAULT; + + payload->reserved0 = UBX_CFG_NAV5_RESERVED0; + + payload->static_hold_dist_threshold = UBX_CFG_NAV5_STATIC_HOLD_DIST_THRESHOLD; + payload->utc_standard = UBX_CFG_NAV5_UTC_STANDARD_DEFAULT; +} + +static struct ubx_cfg_gnss_payload_config_block ubx_cfg_gnss_payload_config_block_default = { + .gnss_id = UBX_GNSS_ID_GPS, + .num_res_trk_ch = 0x00, + .max_num_trk_ch = 0x00, + .reserved0 = UBX_CFG_GNSS_RESERVED0, + .flags = UBX_CFG_GNSS_FLAG_ENABLE | UBX_CFG_GNSS_FLAG_SGN_CNF_GPS_L1C_A, +}; + +void ubx_cfg_gnss_payload_default(struct ubx_cfg_gnss_payload *payload) +{ + payload->msg_ver = UBX_CFG_GNSS_MSG_VER; + payload->num_trk_ch_hw = UBX_CFG_GNSS_NUM_TRK_CH_HW_DEFAULT; + payload->num_trk_ch_use = UBX_CFG_GNSS_NUM_TRK_CH_USE_DEFAULT; + + for (int i = 0; i < payload->num_config_blocks; ++i) { + payload->config_blocks[i] = ubx_cfg_gnss_payload_config_block_default; + } +} + +void ubx_cfg_msg_payload_default(struct ubx_cfg_msg_payload *payload) +{ + payload->message_class = UBX_CLASS_NMEA; + payload->message_id = UBX_NMEA_GGA; + payload->rate = UBX_CFG_MSG_RATE_DEFAULT; +} diff --git a/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol.h b/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol.h new file mode 100644 index 00000000000..6842a708def --- /dev/null +++ b/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol.h @@ -0,0 +1,251 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "gnss_u_blox_protocol_defines.h" + +#ifndef ZEPHYR_U_BLOX_PROTOCOL_ +#define ZEPHYR_U_BLOX_PROTOCOL_ + +#define UBX_BAUDRATE_COUNT 9 + +/* When a configuration frame is sent, the device requires some delay to reflect the changes. */ +/* TODO: check what is the precise waiting time for each message. */ +#define UBX_CFG_RST_WAIT_MS 6000 +#define UBX_CFG_GNSS_WAIT_MS 6000 +#define UBX_CFG_NAV5_WAIT_MS 6000 + +extern const uint32_t ubx_baudrate[UBX_BAUDRATE_COUNT]; + +#define UBX_FRM_GET_PAYLOAD_SZ 0 +#define UBX_CFG_ACK_PAYLOAD_SZ 2 +#define UBX_CFG_NAK_PAYLOAD_SZ 2 +#define UBX_CFG_RATE_PAYLOAD_SZ 6 +#define UBX_CFG_PRT_POLL_PAYLOAD_SZ 1 +#define UBX_CFG_PRT_POLL_FRM_SZ (UBX_FRM_SZ_WO_PAYLOAD + UBX_CFG_PRT_POLL_PAYLOAD_SZ) +#define UBX_CFG_PRT_SET_PAYLOAD_SZ 20 +#define UBX_CFG_PRT_SET_FRM_SZ (UBX_FRM_SZ_WO_PAYLOAD + UBX_CFG_PRT_SET_PAYLOAD_SZ) +#define UBX_CFG_RST_PAYLOAD_SZ 4 +#define UBX_CFG_RST_FRM_SZ (UBX_FRM_SZ_WO_PAYLOAD + UBX_CFG_RST_PAYLOAD_SZ) +#define UBX_CFG_NAV5_PAYLOAD_SZ 36 +#define UBX_CFG_NAV5_FRM_SZ (UBX_FRM_SZ_WO_PAYLOAD + UBX_CFG_NAV5_PAYLOAD_SZ) +#define UBX_CFG_MSG_PAYLOAD_SZ 3 +#define UBX_CFG_MSG_FRM_SZ (UBX_FRM_SZ_WO_PAYLOAD + UBX_CFG_MSG_PAYLOAD_SZ) +#define UBX_CFG_GNSS_PAYLOAD_INIT_SZ 4 +#define UBX_CFG_GNSS_PAYLOAD_CFG_BLK_SZ 8 +#define UBX_CFG_GNSS_PAYLOAD_SZ(n) \ + (UBX_CFG_GNSS_PAYLOAD_INIT_SZ + UBX_CFG_GNSS_PAYLOAD_CFG_BLK_SZ * n) +#define UBX_CFG_GNSS_FRM_SZ(n) (UBX_FRM_SZ_WO_PAYLOAD + UBX_CFG_GNSS_PAYLOAD_SZ(n)) + + +int ubx_create_and_validate_frame(uint8_t *ubx_frame, uint16_t ubx_frame_size, uint8_t msg_cls, + uint8_t msg_id, const void *payload, uint16_t payload_size); + +struct ubx_cfg_ack_payload { + uint8_t message_class; + uint8_t message_id; +}; + +void ubx_cfg_ack_payload_default(struct ubx_cfg_ack_payload *payload); + +#define UBX_CFG_RATE_TIME_REF_UTC 0 /* Align measurements to UTC time. */ +#define UBX_CFG_RATE_TIME_REF_GPS 1 /* Align measurements to GPS time. */ +#define UBX_CFG_RATE_TIME_REF_GLO 2 /* Align measurements to GLONASS time. */ +#define UBX_CFG_RATE_TIME_REF_BDS 3 /* Align measurements to BeiDou time. */ +#define UBX_CFG_RATE_TIME_REF_GAL 4 /* Align measurements to Galileo time. */ + +struct ubx_cfg_rate_payload { + uint16_t meas_rate_ms; + uint16_t nav_rate; + uint16_t time_ref; +}; + +void ubx_cfg_rate_payload_default(struct ubx_cfg_rate_payload *payload); + +struct ubx_cfg_prt_poll_payload { + uint8_t port_id; +}; + +void ubx_cfg_prt_poll_payload_default(struct ubx_cfg_prt_poll_payload *payload); + +#define UBX_CFG_PRT_IN_PROTO_UBX BIT(0) +#define UBX_CFG_PRT_IN_PROTO_NMEA BIT(1) +#define UBX_CFG_PRT_IN_PROTO_RTCM BIT(2) +#define UBX_CFG_PRT_IN_PROTO_RTCM3 BIT(5) +#define UBX_CFG_PRT_OUT_PROTO_UBX BIT(0) +#define UBX_CFG_PRT_OUT_PROTO_NMEA BIT(1) +#define UBX_CFG_PRT_OUT_PROTO_RTCM3 BIT(5) + +#define UBX_CFG_PRT_PORT_MODE_CHAR_LEN_5 0U +#define UBX_CFG_PRT_PORT_MODE_CHAR_LEN_6 BIT(6) +#define UBX_CFG_PRT_PORT_MODE_CHAR_LEN_7 BIT(7) +#define UBX_CFG_PRT_PORT_MODE_CHAR_LEN_8 (BIT(6) | BIT(7)) + +#define UBX_CFG_PRT_PORT_MODE_PARITY_EVEN 0U +#define UBX_CFG_PRT_PORT_MODE_PARITY_ODD BIT(9) +#define UBX_CFG_PRT_PORT_MODE_PARITY_NONE BIT(11) + +#define UBX_CFG_PRT_PORT_MODE_STOP_BITS_1 0U +#define UBX_CFG_PRT_PORT_MODE_STOP_BITS_1_HALF BIT(12) +#define UBX_CFG_PRT_PORT_MODE_STOP_BITS_2 BIT(13) +#define UBX_CFG_PRT_PORT_MODE_STOP_BITS_HALF (BIT(12) | BIT(13)) + +#define UBX_CFG_PRT_RESERVED0 0x00 +#define UBX_CFG_PRT_TX_READY_PIN_CONF_DEFAULT 0x0000 +#define UBX_CFG_PRT_TX_READY_PIN_CONF_EN BIT(0) +#define UBX_CFG_PRT_TX_READY_PIN_CONF_POL_LOW BIT(1) +#define UBX_CFG_PRT_TX_READY_PIN_CONF_POL_HIGH 0U +#define UBX_CFG_PRT_RESERVED1 0x00 +#define UBX_CFG_PRT_FLAGS_DEFAULT 0x0000 +#define UBX_CFG_PRT_FLAGS_EXTENDED_TX_TIMEOUT BIT(0) + +struct ubx_cfg_prt_set_payload { + uint8_t port_id; + uint8_t reserved0; + uint16_t tx_ready_pin_conf; + uint32_t port_mode; + uint32_t baudrate; + uint16_t in_proto_mask; + uint16_t out_proto_mask; + uint16_t flags; + uint8_t reserved1; +}; + +void ubx_cfg_prt_set_payload_default(struct ubx_cfg_prt_set_payload *payload); + +#define UBX_CFG_RST_NAV_BBR_MASK_HOT_START 0x0000 +#define UBX_CFG_RST_NAV_BBR_MASK_WARM_START 0x0001 +#define UBX_CFG_RST_NAV_BBR_MASK_COLD_START 0xFFFF + +#define UBX_CFG_RST_RESET_MODE_HARD_RESET 0x00 +#define UBX_CFG_RST_RESET_MODE_CONTROLLED_SOFT_RESET 0x01 +#define UBX_CFG_RST_RESET_MODE_CONTROLLED_SOFT_RESET_GNSS_ONLY 0x02 +#define UBX_CFG_RST_RESET_MODE_HARD_RESET_AFTER_SHUTDOWN 0x04 +#define UBX_CFG_RST_RESET_MODE_CONTROLLED_GNSS_STOP 0x08 +#define UBX_CFG_RST_RESET_MODE_CONTROLLED_GNSS_START 0x09 + +#define UBX_CFG_RST_RESERVED0 0x00 + +struct ubx_cfg_rst_payload { + uint16_t nav_bbr_mask; + uint8_t reset_mode; + uint8_t reserved0; +}; + +void ubx_cfg_rst_payload_default(struct ubx_cfg_rst_payload *payload); + +#define UBX_CFG_NAV5_MASK_ALL 0x05FF +#define UBX_CFG_NAV5_FIX_MODE_DEFAULT UBX_FIX_AUTO_FIX +#define UBX_CFG_NAV5_FIXED_ALT_DEFAULT 0 +#define UBX_CFG_NAV5_FIXED_ALT_VAR_DEFAULT 1U +#define UBX_CFG_NAV5_MIN_ELEV_DEFAULT 5 +#define UBX_CFG_NAV5_DR_LIMIT_DEFAULT 3U +#define UBX_CFG_NAV5_P_DOP_DEFAULT 100U +#define UBX_CFG_NAV5_T_DOP_DEFAULT 100U +#define UBX_CFG_NAV5_P_ACC_DEFAULT 100U +#define UBX_CFG_NAV5_T_ACC_DEFAULT 350U +#define UBX_CFG_NAV5_STATIC_HOLD_THRESHOLD_DEFAULT 0U +#define UBX_CFG_NAV5_DGNSS_TIMEOUT_DEFAULT 60U +#define UBX_CFG_NAV5_CNO_THRESHOLD_NUM_SVS_DEFAULT 0U +#define UBX_CFG_NAV5_CNO_THRESHOLD_DEFAULT 0U +#define UBX_CFG_NAV5_RESERVED0 0U +#define UBX_CFG_NAV5_STATIC_HOLD_DIST_THRESHOLD 0U +#define UBX_CFG_NAV5_UTC_STANDARD_DEFAULT UBX_UTC_AUTOUTC + +struct ubx_cfg_nav5_payload { + uint16_t mask; + uint8_t dyn_model; + + uint8_t fix_mode; + + int32_t fixed_alt; + uint32_t fixed_alt_var; + + int8_t min_elev; + uint8_t dr_limit; + + uint16_t p_dop; + uint16_t t_dop; + uint16_t p_acc; + uint16_t t_acc; + + uint8_t static_hold_threshold; + uint8_t dgnss_timeout; + uint8_t cno_threshold_num_svs; + uint8_t cno_threshold; + + uint16_t reserved0; + + uint16_t static_hold_dist_threshold; + uint8_t utc_standard; +}; + +void ubx_cfg_nav5_payload_default(struct ubx_cfg_nav5_payload *payload); + +#define UBX_CFG_GNSS_MSG_VER 0x00 +#define UBX_CFG_GNSS_NUM_TRK_CH_HW_DEFAULT 0x31 +#define UBX_CFG_GNSS_NUM_TRK_CH_USE_DEFAULT 0x31 + +#define UBX_CFG_GNSS_RESERVED0 0x00 +#define UBX_CFG_GNSS_FLAG_ENABLE BIT(0) +#define UBX_CFG_GNSS_FLAG_DISABLE 0U +#define UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT 16 +/* When gnss_id is 0 (GPS) */ +#define UBX_CFG_GNSS_FLAG_SGN_CNF_GPS_L1C_A (0x01 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +#define UBX_CFG_GNSS_FLAG_SGN_CNF_GPS_L2C (0x10 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +#define UBX_CFG_GNSS_FLAG_SGN_CNF_GPS_L5 (0x20 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +/* When gnss_id is 1 (SBAS) */ +#define UBX_CFG_GNSS_FLAG_SGN_CNF_SBAS_L1C_A (0x01 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +/* When gnss_id is 2 (Galileo) */ +#define UBX_CFG_GNSS_FLAG_SGN_CNF_GALILEO_E1 (0x01 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +#define UBX_CFG_GNSS_FLAG_SGN_CNF_GALILEO_E5A (0x10 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +#define UBX_CFG_GNSS_FLAG_SGN_CNF_GALILEO_E5B (0x20 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +/* When gnss_id is 3 (BeiDou) */ +#define UBX_CFG_GNSS_FLAG_SGN_CNF_BEIDOU_B1I (0x01 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +#define UBX_CFG_GNSS_FLAG_SGN_CNF_BEIDOU_B2I (0x10 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +#define UBX_CFG_GNSS_FLAG_SGN_CNF_BEIDOU_B2A (0x80 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +/* When gnss_id is 4 (IMES) */ +#define UBX_CFG_GNSS_FLAG_SGN_CNF_IMES_L1 (0x01 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +/* When gnss_id is 5 (QZSS) */ +#define UBX_CFG_GNSS_FLAG_SGN_CNF_QZSS_L1C_A (0x01 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +#define UBX_CFG_GNSS_FLAG_SGN_CNF_QZSS_L1S (0x04 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +#define UBX_CFG_GNSS_FLAG_SGN_CNF_QZSS_L2C (0x10 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +#define UBX_CFG_GNSS_FLAG_SGN_CNF_QZSS_L5 (0x20 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +/* When gnss_id is 6 (GLONASS) */ +#define UBX_CFG_GNSS_FLAG_SGN_CNF_GLONASS_L1 (0x01 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) +#define UBX_CFG_GNSS_FLAG_SGN_CNF_GLONASS_L2 (0x10 << UBX_CFG_GNSS_FLAG_SGN_CNF_SHIFT) + +struct ubx_cfg_gnss_payload_config_block { + uint8_t gnss_id; + uint8_t num_res_trk_ch; + uint8_t max_num_trk_ch; + uint8_t reserved0; + uint32_t flags; +}; + +struct ubx_cfg_gnss_payload { + uint8_t msg_ver; + uint8_t num_trk_ch_hw; + uint8_t num_trk_ch_use; + uint8_t num_config_blocks; + struct ubx_cfg_gnss_payload_config_block config_blocks[]; +}; + +void ubx_cfg_gnss_payload_default(struct ubx_cfg_gnss_payload *payload); + +#define UBX_CFG_MSG_RATE_DEFAULT 1 + +struct ubx_cfg_msg_payload { + uint8_t message_class; + uint8_t message_id; + uint8_t rate; +}; + +void ubx_cfg_msg_payload_default(struct ubx_cfg_msg_payload *payload); + +#endif /* ZEPHYR_U_BLOX_PROTOCOL_ */ diff --git a/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol_defines.h b/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol_defines.h new file mode 100644 index 00000000000..870f3f48806 --- /dev/null +++ b/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol_defines.h @@ -0,0 +1,258 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Referred some enum definitions from file "include/zephyr/drivers/gnss/ublox_neo_m8_defines.h" + * from the pull request #46447 (link - https://github.com/zephyrproject-rtos/zephyr/pull/46447). + */ + +#ifndef ZEPHYR_U_BLOX_PROTOCOL_DEFINES_ +#define ZEPHYR_U_BLOX_PROTOCOL_DEFINES_ + +enum ubx_gnss_id { + UBX_GNSS_ID_GPS = 0, + UBX_GNSS_ID_SBAS = 1, + UBX_GNSS_ID_GALILEO = 2, + UBX_GNSS_ID_BEIDOU = 3, + UBX_GNSS_ID_IMES = 4, + UBX_GNSS_ID_QZSS = 5, + UBX_GNSS_ID_GLONASS = 6, +}; + +enum ubx_port_number { + UBX_PORT_NUMBER_DDC = 0, + UBX_PORT_NUMBER_UART, + UBX_PORT_NUMBER_USB, + UBX_PORT_NUMBER_SPI, +}; + +enum ubx_dynamic_model { + UBX_DYN_MODEL_PORTABLE = 0, + UBX_DYN_MODEL_STATIONARY = 2, + UBX_DYN_MODEL_PEDESTRIAN = 3, + UBX_DYN_MODEL_AUTOMOTIV = 4, + UBX_DYN_MODEL_SEA = 5, + UBX_DYN_MODEL_AIRBONE1G = 6, + UBX_DYN_MODEL_AIRBONE2G = 7, + UBX_DYN_MODEL_AIRBONE4G = 8, + UBX_DYN_MODEL_WIRST = 9, + UBX_DYN_MODEL_BIKE = 10, +}; + +enum ubx_fix_mode { + UBX_FIX_P_2D = 1, + UBX_FIX_P_3D, + UBX_FIX_AUTO_FIX, +}; + +enum ubx_utc_standard { + UBX_UTC_AUTOUTC = 0, + UBX_UTC_GPS = 3, + UBX_UTC_GALILEO = 5, + UBX_UTC_GLONASS, + UBX_UTC_BEIDOU, + UBX_UTC_NAVIC, +}; + +enum ubx_msg_class { + UBX_CLASS_NAV = 0x01, + UBX_CLASS_RXM = 0x02, + UBX_CLASS_INF = 0x04, + UBX_CLASS_ACK = 0x05, + UBX_CLASS_CFG = 0x06, + UBX_CLASS_UPD = 0x09, + UBX_CLASS_MON = 0x0A, + UBX_CLASS_AID = 0x0B, + UBX_CLASS_TIM = 0x0D, + UBX_CLASS_ESF = 0x10, + UBX_CLASS_MGA = 0x13, + UBX_CLASS_LOG = 0x21, + UBX_CLASS_SEC = 0x27, + UBX_CLASS_HNR = 0x28, + UBX_CLASS_NMEA = 0xF0, +}; + +enum ubx_ack_message { + UBX_ACK_ACK = 0x01, + UBX_ACK_NAK = 0x00, +}; + +enum ubx_config_message { + UBX_CFG_ANT = 0x13, + UBX_CFG_BATCH = 0x93, + UBX_CFG_CFG = 0x09, + UBX_CFG_DAT = 0x06, + UBX_CFG_DGNSS = 0x70, + UBX_CFG_DOSC = 0x61, + UBX_CFG_ESFALG = 0x56, + UBX_CFG_ESFAE = 0x4C, + UBX_CFG_ESFGE = 0x4D, + UBX_CFG_ESFWTE = 0x82, + UBX_CFG_ESRCE = 0x60, + UBX_CFG_GEOFENCE = 0x69, + UBX_CFG_GNSS = 0x3E, + UBX_CFG_HNR = 0x5C, + UBX_CFG_INF = 0x02, + UBX_CFG_ITFM = 0x39, + UBX_CFG_LOGFILTER = 0x47, + UBX_CFG_MSG = 0x01, + UBX_CFG_NAV5 = 0x24, + UBX_CFG_NAVX5 = 0x23, + UBX_CFG_NMEA = 0x17, + UBX_CFG_ODO = 0x1E, + UBX_CFG_PM2 = 0x3B, + UBX_CFG_PMS = 0x86, + UBX_CFG_PRT = 0x00, + UBX_CFG_PWR = 0x57, + UBX_CFG_RATE = 0x08, + UBX_CFG_RINV = 0x34, + UBX_CFG_RST = 0x04, + UBX_CFG_RXM = 0x11, + UBX_CFG_SBAS = 0x16, + UBX_CFG_SENIF = 0x88, + UBX_CFG_SLAS = 0x8D, + UBX_CFG_SMGR = 0x62, + UBX_CFG_SPT = 0x64, + UBX_CFG_TMODE2 = 0x3D, + UBX_CFG_TMODE3 = 0x71, + UBX_CFG_TP5 = 0x31, + UBX_CFG_TXSLOT = 0x53, + UBX_CFG_USB = 0x1B, +}; + +enum ubx_information_message { + UBX_INF_DEBUG = 0x04, + UBX_INF_ERROR = 0x00, + UBX_INF_NOTICE = 0x02, + UBX_INF_TEST = 0x03, + UBX_INF_WARNING = 0x01, +}; + +enum ubx_logging_message { + UBX_LOG_BATCH = 0x11, + UBX_LOG_CREATE = 0x07, + UBX_LOG_ERASE = 0x03, + UBX_LOG_FINDTIME = 0x0E, + UBX_LOG_INFO = 0x08, + UBX_LOG_RETRIEVEBATCH = 0x10, + UBX_LOG_RETRIEVEPOSEXTRA = 0x0f, + UBX_LOG_RETRIEVEPOS = 0x0b, + UBX_LOG_RETRIEVESTRING = 0x0d, + UBX_LOG_RETRIEVE = 0x09, + UBX_LOG_STRING = 0x04, +}; + +enum ubx_multiple_gnss_assistance_message { + UBX_MGA_ACK = 0x60, + UBX_MGA_ANO = 0x20, + UBX_MGA_BDS = 0x03, + UBX_MGA_DBD = 0x80, + UBX_MGA_FLASH = 0x21, + UBX_MGA_GAL = 0x02, + UBX_MGA_GLO = 0x06, + UBX_MGA_GPS = 0x00, + UBX_MGA_INI = 0x40, + UBX_MGA_QZSS = 0x05, +}; + +enum ubx_monitoring_message { + UBX_MON_BATCH = 0x32, + UBX_MON_GNSS = 0x28, + UBX_MON_HW2 = 0x0B, + UBX_MON_HW = 0x09, + UBX_MON_IO = 0x02, + UBX_MON_MSGPP = 0x06, + UBX_MON_PATCH = 0x27, + UBX_MON_RXBUF = 0x07, + UBX_MON_RXR = 0x21, + UBX_MON_SMGR = 0x2E, + UBX_MON_SPT = 0x2F, + UBX_MON_TXBUF = 0x08, + UBX_MON_VER = 0x04, +}; + +enum ubx_nagivation_results_message { + UBX_NAV_AOPSTATUS = 0x60, + UBX_NAV_ATT = 0x05, + UBX_NAV_CLOCK = 0x22, + UBX_NAV_COV = 0x36, + UBX_NAV_DGPS = 0x31, + UBX_NAV_DOP = 0x04, + UBX_NAV_EELL = 0x3d, + UBX_NAV_EOE = 0x61, + UBX_NAV_GEOFENCE = 0x39, + UBX_NAV_HPPOSECEF = 0x13, + UBX_NAV_HPPOSLLH = 0x14, + UBX_NAV_NMI = 0x28, + UBX_NAV_ODO = 0x09, + UBX_NAV_ORB = 0x34, + UBX_NAV_POSECEF = 0x01, + UBX_NAV_POSLLH = 0x02, + UBX_NAV_PVT = 0x07, + UBX_NAV_RELPOSNED = 0x3C, + UBX_NAV_RESETODO = 0x10, + UBX_NAV_SAT = 0x35, + UBX_NAV_SBAS = 0x32, + UBX_NAV_SLAS = 0x42, + UBX_NAV_SOL = 0x06, + UBX_NAV_STATUS = 0x03, + UBX_NAV_SVINFO = 0x30, + UBX_NAV_SVIN = 0x3B, + UBX_NAV_TIMEBDS = 0x24, + UBX_NAV_TIMEGAL = 0x25, + UBX_NAV_TIMEGLO = 0x23, + UBX_NAV_TIMEGPS = 0x20, + UBX_NAV_TIMELS = 0x26, + UBX_NAV_TIMEUTC = 0x21, + UBX_NAV_VELECEF = 0x11, + UBX_NAV_VELNED = 0x12, +}; + +enum ubx_receiver_manager_message { + UBX_RXM_IMES = 0x61, + UBX_RXM_MEASX = 0x14, + UBX_RXM_PMREQ = 0x41, + UBX_RXM_RAWX = 0x15, + UBX_RXM_RLM = 0x59, + UBX_RXM_RTCM = 0x32, + UBX_RXM_SFRBX = 0x13, +}; + +enum ubx_timing_message { + UBX_TIM_DOSC = 0x11, + UBX_TIM_FCHG = 0x16, + UBX_TIM_HOC = 0x17, + UBX_TIM_SMEAS = 0x13, + UBX_TIM_SVIN = 0x04, + UBX_TIM_TM2 = 0x03, + UBX_TIM_TOS = 0x12, + UBX_TIM_TP = 0x01, + UBX_TIM_VCOCAL = 0x15, + UBX_TIM_VRFY = 0x06, +}; + +enum ubx_nmea_message_id { + UBX_NMEA_DTM = 0x0A, + UBX_NMEA_GBQ = 0x44, + UBX_NMEA_GBS = 0x09, + UBX_NMEA_GGA = 0x00, + UBX_NMEA_GLL = 0x01, + UBX_NMEA_GLQ = 0x43, + UBX_NMEA_GNQ = 0x42, + UBX_NMEA_GNS = 0x0D, + UBX_NMEA_GPQ = 0x40, + UBX_NMEA_GRS = 0x06, + UBX_NMEA_GSA = 0x02, + UBX_NMEA_GST = 0x07, + UBX_NMEA_GSV = 0x03, + UBX_NMEA_RMC = 0x04, + UBX_NMEA_THS = 0x0E, + UBX_NMEA_TXT = 0x41, + UBX_NMEA_VLW = 0x0F, + UBX_NMEA_VTG = 0x05, + UBX_NMEA_ZDA = 0x08, +}; + +#endif /* ZEPHYR_U_BLOX_PROTOCOL_DEFINES_ */ diff --git a/dts/bindings/gnss/u-blox,m10.yaml b/dts/bindings/gnss/u-blox,m10.yaml new file mode 100644 index 00000000000..556213d8c42 --- /dev/null +++ b/dts/bindings/gnss/u-blox,m10.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: U-BLOX M10 GNSS Module + +compatible: "u-blox,m10" + +include: + - uart-device.yaml + +properties: + uart-baudrate: + type: int + description: | + Baudrate for communication on the UART port. + default: 115200 + enum: [4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600] diff --git a/include/zephyr/dt-bindings/gnss/u_blox_m10.h b/include/zephyr/dt-bindings/gnss/u_blox_m10.h new file mode 100644 index 00000000000..b017f42dcaf --- /dev/null +++ b/include/zephyr/dt-bindings/gnss/u_blox_m10.h @@ -0,0 +1,23 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M10_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M10_H_ + +#include + +/* UART Baudrate. */ +#define UBX_M10_UART_BAUDRATE_4800 0x00 +#define UBX_M10_UART_BAUDRATE_9600 0x01 +#define UBX_M10_UART_BAUDRATE_19200 0x02 +#define UBX_M10_UART_BAUDRATE_38400 0x03 +#define UBX_M10_UART_BAUDRATE_57600 0x04 +#define UBX_M10_UART_BAUDRATE_115200 0x05 +#define UBX_M10_UART_BAUDRATE_230400 0x06 +#define UBX_M10_UART_BAUDRATE_460800 0x07 +#define UBX_M10_UART_BAUDRATE_921600 0x08 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M10_H_ */ diff --git a/include/zephyr/modem/ubx.h b/include/zephyr/modem/ubx.h new file mode 100644 index 00000000000..e51cb5cd404 --- /dev/null +++ b/include/zephyr/modem/ubx.h @@ -0,0 +1,175 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include + +#ifndef ZEPHYR_MODEM_UBX_ +#define ZEPHYR_MODEM_UBX_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Modem Ubx + * @defgroup modem_ubx Modem Ubx + * @ingroup modem + * @{ + */ + +#define UBX_FRM_HEADER_SZ 6 +#define UBX_FRM_FOOTER_SZ 2 +#define UBX_FRM_SZ_WITHOUT_PAYLOAD (UBX_FRM_HEADER_SZ + UBX_FRM_FOOTER_SZ) +#define UBX_FRM_SZ(payload_size) (payload_size + UBX_FRM_SZ_WITHOUT_PAYLOAD) + +#define UBX_PREAMBLE_SYNC_CHAR_1 0xB5 +#define UBX_PREAMBLE_SYNC_CHAR_2 0x62 + +#define UBX_FRM_PREAMBLE_SYNC_CHAR_1_IDX 0 +#define UBX_FRM_PREAMBLE_SYNC_CHAR_2_IDX 1 +#define UBX_FRM_MSG_CLASS_IDX 2 +#define UBX_FRM_MSG_ID_IDX 3 +#define UBX_FRM_PAYLOAD_SZ_L_IDX 4 +#define UBX_FRM_PAYLOAD_SZ_H_IDX 5 +#define UBX_FRM_PAYLOAD_IDX 6 +#define UBX_FRM_CHECKSUM_START_IDX 2 +#define UBX_FRM_CHECKSUM_STOP_IDX(frame_len) (frame_len - 2) + +#define UBX_PAYLOAD_SZ_MAX 256 +#define UBX_FRM_SZ_MAX UBX_FRM_SZ(UBX_PAYLOAD_SZ_MAX) + +struct ubx_frame { + uint8_t preamble_sync_char_1; + uint8_t preamble_sync_char_2; + uint8_t message_class; + uint8_t message_id; + uint8_t payload_size_low; + uint8_t payload_size_high; + uint8_t payload_and_checksum[]; +}; + +struct modem_ubx_script { + struct ubx_frame *request; + struct ubx_frame *response; + struct ubx_frame *match; + + uint16_t retry_count; + k_timeout_t timeout; +}; + +struct modem_ubx { + void *user_data; + + atomic_t state; + + uint8_t *receive_buf; + uint16_t receive_buf_size; + + uint8_t *work_buf; + uint16_t work_buf_size; + uint16_t work_buf_len; + bool ubx_preamble_sync_chars_received; + + const struct modem_ubx_script *script; + + struct modem_pipe *pipe; + + struct k_work send_work; + struct k_work process_work; + struct k_sem script_stopped_sem; + struct k_sem script_running_sem; +}; + +struct modem_ubx_config { + void *user_data; + + uint8_t *receive_buf; + uint16_t receive_buf_size; + uint8_t *work_buf; + uint16_t work_buf_size; +}; + +/** + * @brief Attach pipe to Modem Ubx + * + * @param ubx Modem Ubx instance + * @param pipe Pipe instance to attach Modem Ubx instance to + * @returns 0 if successful + * @returns negative errno code if failure + * @note Modem Ubx instance is enabled if successful + */ +int modem_ubx_attach(struct modem_ubx *ubx, struct modem_pipe *pipe); + +/** + * @brief Release pipe from Modem Ubx instance + * + * @param ubx Modem Ubx instance + */ +void modem_ubx_release(struct modem_ubx *ubx); + +/** + * @brief Initialize Modem Ubx instance + * @param ubx Modem Ubx instance + * @param config Configuration which shall be applied to the Modem Ubx instance + * @note Modem Ubx instance must be attached to a pipe instance + */ +int modem_ubx_init(struct modem_ubx *ubx, const struct modem_ubx_config *config); + +/** + * @brief Writes the ubx frame in script.request and reads back its response (if available) + * @details For each ubx frame sent, the device responds in 0, 1 or both of the following ways: + * 1. The device sends back a UBX-ACK frame to denote 'acknowledge' and 'not-acknowledge'. + * Note: the message id of UBX-ACK frame determines whether the device acknowledged. + * Ex: when we send a UBX-CFG frame, the device responds with a UBX-ACK frame. + * 2. The device sends back the same frame that we sent to it, with it's payload populated. + * It's used to get the current configuration corresponding to the frame that we sent. + * Ex: frame types such as "get" or "poll" ubx frames respond this way. + * This response (if received) is written to script.response. + * + * This function writes the ubx frame in script.request then reads back it's response. + * If script.match is not NULL, then every ubx frame received from the device is compared with + * script.match to check if a match occurred. This could be used to match UBX-ACK frame sent + * from the device by populating script.match with UBX-ACK that the script expects to receive. + * + * The script terminates when either of the following happens: + * 1. script.match is successfully received and matched. + * 2. timeout (denoted by script.timeout) occurs. + * @param ubx Modem Ubx instance + * @param script Script to be executed + * @note The length of ubx frame in the script.request should not exceed UBX_FRM_SZ_MAX + * @note Modem Ubx instance must be attached to a pipe instance + * @returns 0 if device acknowledged via UBX-ACK and no "get" response was received + * @returns positive integer denoting the length of "get" response that was received + * @returns negative errno code if failure + */ +int modem_ubx_run_script(struct modem_ubx *ubx, const struct modem_ubx_script *script); + +/** + * @brief Initialize ubx frame + * @param ubx_frame Ubx frame buffer + * @param ubx_frame_size Ubx frame buffer size + * @param msg_cls Message class + * @param msg_id Message id + * @param payload Payload buffer + * @param payload_size Payload buffer size + * @returns positive integer denoting the length of the ubx frame created + * @returns negative errno code if failure + */ +int modem_ubx_create_frame(uint8_t *ubx_frame, uint16_t ubx_frame_size, uint8_t msg_cls, + uint8_t msg_id, const void *payload, uint16_t payload_size); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_MODEM_UBX_ */ diff --git a/samples/drivers/gnss/boards/mimxrt1062_fmurt6.conf b/samples/drivers/gnss/boards/mimxrt1062_fmurt6.conf new file mode 100644 index 00000000000..a8b2dae2a79 --- /dev/null +++ b/samples/drivers/gnss/boards/mimxrt1062_fmurt6.conf @@ -0,0 +1,4 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/samples/drivers/gnss/boards/mimxrt1062_fmurt6.overlay b/samples/drivers/gnss/boards/mimxrt1062_fmurt6.overlay new file mode 100644 index 00000000000..37942aed9ba --- /dev/null +++ b/samples/drivers/gnss/boards/mimxrt1062_fmurt6.overlay @@ -0,0 +1,25 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + gnss = &lpuart2; + }; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart2>; + pinctrl-1 = <&pinmux_lpuart2_sleep>; + pinctrl-names = "default", "sleep"; + + u_blox_m10: u-blox,m10 { + status = "okay"; + compatible = "u-blox,m10"; + uart-baudrate = <115200>; + }; +}; diff --git a/samples/drivers/gnss/boards/vmu_rt1170.overlay b/samples/drivers/gnss/boards/vmu_rt1170.overlay new file mode 100644 index 00000000000..baf0b47923e --- /dev/null +++ b/samples/drivers/gnss/boards/vmu_rt1170.overlay @@ -0,0 +1,22 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + gnss = &lpuart3; + }; +}; + +&lpuart3 { + status = "okay"; + current-speed = <115200>; + + u_blox_m10: u-blox,m10 { + status = "okay"; + compatible = "u-blox,m10"; + uart-baudrate = <115200>; + }; +}; diff --git a/subsys/modem/CMakeLists.txt b/subsys/modem/CMakeLists.txt index d491e190ebe..a19916a0dd3 100644 --- a/subsys/modem/CMakeLists.txt +++ b/subsys/modem/CMakeLists.txt @@ -9,6 +9,7 @@ zephyr_library_sources_ifdef(CONFIG_MODEM_CHAT modem_chat.c) zephyr_library_sources_ifdef(CONFIG_MODEM_CMUX modem_cmux.c) zephyr_library_sources_ifdef(CONFIG_MODEM_PIPE modem_pipe.c) zephyr_library_sources_ifdef(CONFIG_MODEM_PPP modem_ppp.c) +zephyr_library_sources_ifdef(CONFIG_MODEM_UBX modem_ubx.c) add_subdirectory(backends) diff --git a/subsys/modem/Kconfig b/subsys/modem/Kconfig index 69c102a07ad..86168ad22c5 100644 --- a/subsys/modem/Kconfig +++ b/subsys/modem/Kconfig @@ -54,6 +54,21 @@ config MODEM_PPP_NET_BUF_FRAG_SIZE endif +config MODEM_UBX + bool "Modem U-BLOX module" + select RING_BUFFER + select MODEM_PIPE + help + Enable Modem U-BLOX module. + +if MODEM_UBX + +config MODEM_UBX_LOG_BUFFER + int "Modem U-BLOX log buffer size" + default 128 + +endif + module = MODEM_MODULES module-str = modem_modules source "subsys/logging/Kconfig.template.log_config" diff --git a/subsys/modem/modem_ubx.c b/subsys/modem/modem_ubx.c new file mode 100644 index 00000000000..22ce98f23eb --- /dev/null +++ b/subsys/modem/modem_ubx.c @@ -0,0 +1,338 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include +LOG_MODULE_REGISTER(modem_ubx, CONFIG_MODEM_MODULES_LOG_LEVEL); + +#define MODEM_UBX_STATE_ATTACHED_BIT 0 + +static int modem_ubx_validate_frame_size(uint16_t ubx_frame_size, uint8_t msg_cls, uint8_t msg_id, + uint16_t payload_size) +{ + if (ubx_frame_size > UBX_FRM_SZ_MAX || + ubx_frame_size < UBX_FRM_SZ_WITHOUT_PAYLOAD || + ubx_frame_size < UBX_FRM_SZ_WITHOUT_PAYLOAD + payload_size) { + return -1; + } + + return 0; +} + +int modem_ubx_create_frame(uint8_t *ubx_frame, uint16_t ubx_frame_size, uint8_t msg_cls, + uint8_t msg_id, const void *payload, uint16_t payload_size) +{ + if (modem_ubx_validate_frame_size(ubx_frame_size, msg_cls, msg_id, payload_size)) { + return -1; + } + + struct ubx_frame *frame = (struct ubx_frame *) ubx_frame; + + frame->preamble_sync_char_1 = UBX_PREAMBLE_SYNC_CHAR_1; + frame->preamble_sync_char_2 = UBX_PREAMBLE_SYNC_CHAR_2; + frame->message_class = msg_cls; + frame->message_id = msg_id; + frame->payload_size_low = payload_size; + frame->payload_size_high = payload_size >> 8; + + memcpy(frame->payload_and_checksum, payload, payload_size); + + uint16_t ubx_frame_len = payload_size + UBX_FRM_SZ_WITHOUT_PAYLOAD; + + uint8_t ckA = 0, ckB = 0; + + for (unsigned int i = UBX_FRM_CHECKSUM_START_IDX; + i < (UBX_FRM_CHECKSUM_STOP_IDX(ubx_frame_len)); i++) { + ckA += ubx_frame[i]; + ckB += ckA; + } + + frame->payload_and_checksum[payload_size] = ckA; + frame->payload_and_checksum[payload_size + 1] = ckB; + + return ubx_frame_len; +} + +static void modem_ubx_reset_received_ubx_preamble_sync_chars(struct modem_ubx *ubx) +{ + ubx->ubx_preamble_sync_chars_received = false; +} + +static void modem_ubx_reset_parser(struct modem_ubx *ubx) +{ + modem_ubx_reset_received_ubx_preamble_sync_chars(ubx); +} + +static int modem_ubx_get_payload_length(struct ubx_frame *frame) +{ + uint16_t payload_len = frame->payload_size_high; + + payload_len = payload_len << 8; + + return payload_len | frame->payload_size_low; +} + +static int modem_ubx_get_frame_length(struct ubx_frame *frame) +{ + return modem_ubx_get_payload_length(frame) + UBX_FRM_SZ_WITHOUT_PAYLOAD; +} + +static bool modem_ubx_match_frame_type(struct ubx_frame *frame_1, struct ubx_frame *frame_2) +{ + if (frame_1->message_class == frame_2->message_class + && frame_1->message_id == frame_2->message_id) { + return true; + } else { + return false; + } +} + +static bool modem_ubx_match_frame_full(struct ubx_frame *frame_1, struct ubx_frame *frame_2) +{ + if (modem_ubx_get_frame_length(frame_1) != modem_ubx_get_frame_length(frame_2)) { + return false; + } + + if (memcmp(frame_1, frame_2, modem_ubx_get_frame_length(frame_1)) == 0) { + return true; + } else { + return false; + } +} + +static void modem_ubx_script_init(struct modem_ubx *ubx, const struct modem_ubx_script *script) +{ + ubx->script = script; +} + +static int modem_ubx_run_script_helper(struct modem_ubx *ubx, const struct modem_ubx_script *script) +{ + int ret; + + if (ubx->pipe == NULL) { + return -EPERM; + } + + k_sem_reset(&ubx->script_stopped_sem); + + modem_ubx_reset_parser(ubx); + + k_work_submit(&ubx->send_work); + + if (ubx->script->match == NULL) { + return 0; + } + + ret = k_sem_take(&ubx->script_stopped_sem, script->timeout); + if (ret < 0) { + return ret; + } + + return 0; +} + +int modem_ubx_run_script(struct modem_ubx *ubx, const struct modem_ubx_script *script) +{ + int ret, attempt; + + if (modem_ubx_get_frame_length(script->request) > UBX_FRM_SZ_MAX) { + return -EFBIG; + } + + if (atomic_test_bit(&ubx->state, MODEM_UBX_STATE_ATTACHED_BIT) == false) { + return -EPERM; + } + + ret = k_sem_take(&ubx->script_running_sem, K_FOREVER); + if (ret < 0) { + return ret; + } + + modem_ubx_script_init(ubx, script); + + for (attempt = 0; attempt < script->retry_count; ++attempt) { + ret = modem_ubx_run_script_helper(ubx, script); + if (ret > -1) { + LOG_INF("Successfully executed script on attempt: %d.", attempt); + break; + } else if (ret == -EPERM) { + break; + } + } + + if (ret < 0) { + LOG_ERR("Failed to execute script successfully. Attempts: %d.", attempt); + goto unlock; + } + +unlock: + k_sem_give(&ubx->script_running_sem); + + return ret; +} + +static void modem_ubx_pipe_callback(struct modem_pipe *pipe, enum modem_pipe_event event, + void *user_data) +{ + struct modem_ubx *ubx = (struct modem_ubx *)user_data; + + if (event == MODEM_PIPE_EVENT_RECEIVE_READY) { + k_work_submit(&ubx->process_work); + } +} + +static void modem_ubx_send_handler(struct k_work *item) +{ + struct modem_ubx *ubx = CONTAINER_OF(item, struct modem_ubx, send_work); + int ret, tx_frame_len; + + tx_frame_len = modem_ubx_get_frame_length(ubx->script->request); + ret = modem_pipe_transmit(ubx->pipe, (const uint8_t *) ubx->script->request, tx_frame_len); + if (ret < tx_frame_len) { + LOG_ERR("Ubx frame transmission failed. Returned %d.", ret); + return; + } +} + +static int modem_ubx_process_received_ubx_frame(struct modem_ubx *ubx) +{ + int ret; + struct ubx_frame *received = (struct ubx_frame *) ubx->work_buf; + + if (modem_ubx_match_frame_full(received, ubx->script->match) == true) { + /* Frame matched successfully. Terminate the script. */ + k_sem_give(&ubx->script_stopped_sem); + ret = 0; + } else if (modem_ubx_match_frame_type(received, ubx->script->request) == true) { + /* Response received successfully. Script not ended. */ + memcpy(ubx->script->response, ubx->work_buf, ubx->work_buf_len); + ret = -1; + } else { + /* Ignore the received frame. The device may automatically send periodic frames. + * These frames are not relevant for our script's execution and must be ignored. + */ + ret = -1; + } + + modem_ubx_reset_parser(ubx); + + return ret; +} + +static int modem_ubx_process_received_byte(struct modem_ubx *ubx, uint8_t byte) +{ + static uint8_t prev_byte; + static uint16_t rx_ubx_frame_len; + + if (ubx->ubx_preamble_sync_chars_received == false) { + if (prev_byte == UBX_PREAMBLE_SYNC_CHAR_1 && byte == UBX_PREAMBLE_SYNC_CHAR_2) { + ubx->ubx_preamble_sync_chars_received = true; + ubx->work_buf[0] = UBX_PREAMBLE_SYNC_CHAR_1; + ubx->work_buf[1] = UBX_PREAMBLE_SYNC_CHAR_2; + ubx->work_buf_len = 2; + } + } else { + ubx->work_buf[ubx->work_buf_len] = byte; + ++ubx->work_buf_len; + + if (ubx->work_buf_len == UBX_FRM_HEADER_SZ) { + uint16_t rx_ubx_payload_len = ubx->work_buf[UBX_FRM_PAYLOAD_SZ_H_IDX]; + + rx_ubx_payload_len = ubx->work_buf[UBX_FRM_PAYLOAD_SZ_H_IDX] << 8; + rx_ubx_payload_len |= ubx->work_buf[UBX_FRM_PAYLOAD_SZ_L_IDX]; + + rx_ubx_frame_len = rx_ubx_payload_len + UBX_FRM_SZ_WITHOUT_PAYLOAD; + } + + if (ubx->work_buf_len == rx_ubx_frame_len) { + return modem_ubx_process_received_ubx_frame(ubx); + } + } + + prev_byte = byte; + + return -1; +} + +static void modem_ubx_process_handler(struct k_work *item) +{ + struct modem_ubx *ubx = CONTAINER_OF(item, struct modem_ubx, process_work); + int ret; + + ret = modem_pipe_receive(ubx->pipe, ubx->receive_buf, ubx->receive_buf_size); + if (ret < 1) { + return; + } + + for (int i = 0; i < ret; i++) { + ret = modem_ubx_process_received_byte(ubx, ubx->receive_buf[i]); + if (ret == 0) { /* Frame matched successfully. Terminate the script. */ + break; + } + } + + k_work_submit(&ubx->process_work); +} + +int modem_ubx_attach(struct modem_ubx *ubx, struct modem_pipe *pipe) +{ + if (atomic_test_and_set_bit(&ubx->state, MODEM_UBX_STATE_ATTACHED_BIT) == true) { + return 0; + } + + ubx->pipe = pipe; + modem_pipe_attach(ubx->pipe, modem_ubx_pipe_callback, ubx); + k_sem_give(&ubx->script_running_sem); + + return 0; +} + +void modem_ubx_release(struct modem_ubx *ubx) +{ + struct k_work_sync sync; + + if (atomic_test_and_clear_bit(&ubx->state, MODEM_UBX_STATE_ATTACHED_BIT) == false) { + return; + } + + modem_pipe_release(ubx->pipe); + k_work_cancel_sync(&ubx->send_work, &sync); + k_work_cancel_sync(&ubx->process_work, &sync); + k_sem_reset(&ubx->script_stopped_sem); + k_sem_reset(&ubx->script_running_sem); + ubx->work_buf_len = 0; + modem_ubx_reset_parser(ubx); + ubx->pipe = NULL; +} + +int modem_ubx_init(struct modem_ubx *ubx, const struct modem_ubx_config *config) +{ + __ASSERT_NO_MSG(ubx != NULL); + __ASSERT_NO_MSG(config != NULL); + __ASSERT_NO_MSG(config->receive_buf != NULL); + __ASSERT_NO_MSG(config->receive_buf_size > 0); + __ASSERT_NO_MSG(config->work_buf != NULL); + __ASSERT_NO_MSG(config->work_buf_size > 0); + + memset(ubx, 0x00, sizeof(*ubx)); + ubx->user_data = config->user_data; + + ubx->receive_buf = config->receive_buf; + ubx->receive_buf_size = config->receive_buf_size; + ubx->work_buf = config->work_buf; + ubx->work_buf_size = config->work_buf_size; + + ubx->pipe = NULL; + + k_work_init(&ubx->send_work, modem_ubx_send_handler); + k_work_init(&ubx->process_work, modem_ubx_process_handler); + k_sem_init(&ubx->script_stopped_sem, 0, 1); + k_sem_init(&ubx->script_running_sem, 1, 1); + + return 0; +} From fe8816f27896e528e04513d99a252e731d7900e9 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Mon, 18 Mar 2024 14:45:14 +0000 Subject: [PATCH 1342/2402] soc: renesas: rcar_gen3: Fix Kconfigs Fixes Kconfigs to not use another SOC_SERIES Kconfig name Signed-off-by: Jamie McCrae --- soc/renesas/rcar/rcar_gen3/CMakeLists.txt | 4 ++-- soc/renesas/rcar/rcar_gen3/Kconfig | 21 ++++++++------------- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/soc/renesas/rcar/rcar_gen3/CMakeLists.txt b/soc/renesas/rcar/rcar_gen3/CMakeLists.txt index 421ba3ff258..74c6c567035 100644 --- a/soc/renesas/rcar/rcar_gen3/CMakeLists.txt +++ b/soc/renesas/rcar/rcar_gen3/CMakeLists.txt @@ -2,12 +2,12 @@ # Copyright (c) 2023 EPAM Systems # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_SERIES_RCAR_GEN3_R7) +if(CONFIG_ARM) zephyr_sources(r7/soc.c) zephyr_include_directories(r7) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") -elseif(CONFIG_SOC_SERIES_RCAR_GEN3_A57) +elseif(CONFIG_ARM64) zephyr_include_directories(a57) zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) diff --git a/soc/renesas/rcar/rcar_gen3/Kconfig b/soc/renesas/rcar/rcar_gen3/Kconfig index 3d4c577e46a..c4bf5a2a161 100644 --- a/soc/renesas/rcar/rcar_gen3/Kconfig +++ b/soc/renesas/rcar/rcar_gen3/Kconfig @@ -1,26 +1,21 @@ # Copyright (c) 2021 IoT.bzh # SPDX-License-Identifier: Apache-2.0 -config SOC_SERIES_RCAR_GEN3_R7 - bool +config SOC_SERIES_RCAR_GEN3 + select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL + +config SOC_R8A77951_R7 select ARM select CPU_CORTEX_R7 select PLATFORM_SPECIFIC_INIT select CPU_HAS_DCLS - select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL -config SOC_SERIES_RCAR_GEN3_A57 - bool +config SOC_R8A77951_A57 select ARM64 select CPU_CORTEX_A57 select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL - -config SOC_R8A77951_R7 - select SOC_SERIES_RCAR_GEN3_R7 - -config SOC_R8A77951_A57 - select SOC_SERIES_RCAR_GEN3_A57 config SOC_R8A77961 - select SOC_SERIES_RCAR_GEN3_A57 + select ARM64 + select CPU_CORTEX_A57 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS From cf7d166fc1a2dd4eb36d0b359b076bcf58b622ca Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Mon, 18 Mar 2024 16:12:20 +0200 Subject: [PATCH 1343/2402] modem: backends: uart_async: increase default TX timeout The previous default value made UART TXs of size > 1145 time out at a baud rate of 115200. It should not be so small that it can cause undesirable timeouts. Signed-off-by: Tomi Fontanilles --- subsys/modem/backends/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/modem/backends/Kconfig b/subsys/modem/backends/Kconfig index 317f9d26aa8..526d179fe30 100644 --- a/subsys/modem/backends/Kconfig +++ b/subsys/modem/backends/Kconfig @@ -26,7 +26,7 @@ if MODEM_BACKEND_UART_ASYNC config MODEM_BACKEND_UART_ASYNC_TRANSMIT_TIMEOUT_MS int "Modem UART async transmit timeout in milliseconds" - default 100 + default 1000 config MODEM_BACKEND_UART_ASYNC_RECEIVE_IDLE_TIMEOUT_MS int "Modem UART async receive idle timeout in milliseconds" From 8ca15cedc2500a5a796f039ff56ee14787a0be74 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Mon, 18 Mar 2024 16:14:28 +0200 Subject: [PATCH 1344/2402] samples: net: cellular_modem: increase the post-restart sleep time A higher delay helps in getting the first post-restart echo packet to be successful. Signed-off-by: Tomi Fontanilles --- samples/net/cellular_modem/src/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/samples/net/cellular_modem/src/main.c b/samples/net/cellular_modem/src/main.c index c951ac6bbb2..e02f5d7ead1 100644 --- a/samples/net/cellular_modem/src/main.c +++ b/samples/net/cellular_modem/src/main.c @@ -376,7 +376,7 @@ int main(void) printk("L4 connected\n"); /* Wait a bit to avoid (unsuccessfully) trying to send the first echo packet too quickly. */ - k_sleep(K_SECONDS(1)); + k_sleep(K_SECONDS(5)); ret = sample_echo_packet(&sample_test_dns_addrinfo.ai_addr, sample_test_dns_addrinfo.ai_addrlen, port); From 15cc3ff0d6537ec7d967be028d18fba915367119 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Mon, 18 Mar 2024 16:16:40 +0200 Subject: [PATCH 1345/2402] modem: backends: uart: register their own log modules Instead of both using the same modem_backend_uart, for better visibility. Signed-off-by: Tomi Fontanilles --- subsys/modem/backends/modem_backend_uart.c | 3 --- subsys/modem/backends/modem_backend_uart_async.c | 2 +- subsys/modem/backends/modem_backend_uart_isr.c | 2 +- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/subsys/modem/backends/modem_backend_uart.c b/subsys/modem/backends/modem_backend_uart.c index b77a7331899..eef72069ae7 100644 --- a/subsys/modem/backends/modem_backend_uart.c +++ b/subsys/modem/backends/modem_backend_uart.c @@ -9,9 +9,6 @@ #include -#include -LOG_MODULE_REGISTER(modem_backend_uart, CONFIG_MODEM_MODULES_LOG_LEVEL); - #include static void modem_backend_uart_receive_ready_handler(struct k_work *item) diff --git a/subsys/modem/backends/modem_backend_uart_async.c b/subsys/modem/backends/modem_backend_uart_async.c index 9c06885aec1..df0a1595dc4 100644 --- a/subsys/modem/backends/modem_backend_uart_async.c +++ b/subsys/modem/backends/modem_backend_uart_async.c @@ -7,7 +7,7 @@ #include "modem_backend_uart_async.h" #include -LOG_MODULE_DECLARE(modem_backend_uart, CONFIG_MODEM_MODULES_LOG_LEVEL); +LOG_MODULE_REGISTER(modem_backend_uart_async, CONFIG_MODEM_MODULES_LOG_LEVEL); #include #include diff --git a/subsys/modem/backends/modem_backend_uart_isr.c b/subsys/modem/backends/modem_backend_uart_isr.c index 9eed7913496..bfa807c1a69 100644 --- a/subsys/modem/backends/modem_backend_uart_isr.c +++ b/subsys/modem/backends/modem_backend_uart_isr.c @@ -7,7 +7,7 @@ #include "modem_backend_uart_isr.h" #include -LOG_MODULE_DECLARE(modem_backend_uart, CONFIG_MODEM_MODULES_LOG_LEVEL); +LOG_MODULE_REGISTER(modem_backend_uart_isr, CONFIG_MODEM_MODULES_LOG_LEVEL); #include From e7805f8d721ce12488cd4b42ceda9299281e25e2 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Tue, 19 Mar 2024 08:33:34 +0200 Subject: [PATCH 1346/2402] modem: cmux: improve frame debug logging - Add the frame data length to the frame header log. - Log the dropped frames as well. Signed-off-by: Tomi Fontanilles --- subsys/modem/modem_cmux.c | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/subsys/modem/modem_cmux.c b/subsys/modem/modem_cmux.c index 0f77a8d59a5..6fdc1e52841 100644 --- a/subsys/modem/modem_cmux.c +++ b/subsys/modem/modem_cmux.c @@ -126,18 +126,22 @@ static const char *modem_cmux_frame_type_to_str(enum modem_cmux_frame_types fram return ""; } +static void modem_cmux_log_frame(const struct modem_cmux_frame *frame, + const char *action, size_t hexdump_len) +{ + LOG_DBG("%s ch:%u cr:%u pf:%u type:%s dlen:%u", action, frame->dlci_address, + frame->cr, frame->pf, modem_cmux_frame_type_to_str(frame->type), frame->data_len); + LOG_HEXDUMP_DBG(frame->data, hexdump_len, "data:"); +} + static void modem_cmux_log_transmit_frame(const struct modem_cmux_frame *frame) { - LOG_DBG("ch:%u,cr:%u,pf:%u,type:%s", frame->dlci_address, frame->cr, frame->pf, - modem_cmux_frame_type_to_str(frame->type)); - LOG_HEXDUMP_DBG(frame->data, frame->data_len, "data:"); + modem_cmux_log_frame(frame, "tx", frame->data_len); } static void modem_cmux_log_received_frame(const struct modem_cmux_frame *frame) { - LOG_DBG("ch:%u,cr:%u,pf:%u,type:%s", frame->dlci_address, frame->cr, frame->pf, - modem_cmux_frame_type_to_str(frame->type)); - LOG_HEXDUMP_DBG(frame->data, frame->data_len, "data:"); + modem_cmux_log_frame(frame, "rcvd", frame->data_len); } static const char *modem_cmux_command_type_to_str(enum modem_cmux_command_types command_type) @@ -652,6 +656,19 @@ static void modem_cmux_on_frame(struct modem_cmux *cmux) } } +static void modem_cmux_drop_frame(struct modem_cmux *cmux) +{ + LOG_WRN("Dropped frame"); + cmux->receive_state = MODEM_CMUX_RECEIVE_STATE_SOF; + +#if defined(CONFIG_MODEM_CMUX_LOG_LEVEL_DBG) + struct modem_cmux_frame *frame = &cmux->frame; + + frame->data = cmux->receive_buf; + modem_cmux_log_frame(frame, "dropped", MIN(frame->data_len, cmux->receive_buf_size)); +#endif +} + static void modem_cmux_process_received_byte(struct modem_cmux *cmux, uint8_t byte) { uint8_t fcs; @@ -797,15 +814,14 @@ static void modem_cmux_process_received_byte(struct modem_cmux *cmux, uint8_t by break; case MODEM_CMUX_RECEIVE_STATE_DROP: - LOG_WRN("Dropped frame"); - cmux->receive_state = MODEM_CMUX_RECEIVE_STATE_SOF; + modem_cmux_drop_frame(cmux); break; case MODEM_CMUX_RECEIVE_STATE_EOF: /* Validate byte is EOF */ if (byte != 0xF9) { /* Unexpected byte */ - cmux->receive_state = MODEM_CMUX_RECEIVE_STATE_SOF; + modem_cmux_drop_frame(cmux); break; } From 9cea822cc46b82627c6e5ea29eafe70cdffb6c88 Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Tue, 19 Mar 2024 09:02:54 +0200 Subject: [PATCH 1347/2402] modem: backends: uart_async: small improvements - Set all the state bits before calling uart_rx_enable() because interrupts may happen already before it returns. - Fix the byte count in the "Receive buffer overrun" log. Signed-off-by: Tomi Fontanilles --- .../modem/backends/modem_backend_uart_async.c | 30 ++++++++----------- 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/subsys/modem/backends/modem_backend_uart_async.c b/subsys/modem/backends/modem_backend_uart_async.c index df0a1595dc4..0bd98eb0e7d 100644 --- a/subsys/modem/backends/modem_backend_uart_async.c +++ b/subsys/modem/backends/modem_backend_uart_async.c @@ -112,10 +112,13 @@ static void modem_backend_uart_async_event_handler(const struct device *dev, evt->data.rx.len); if (received < evt->data.rx.len) { + const unsigned int buf_size = ring_buf_size_get(&backend->async.receive_rb); + ring_buf_reset(&backend->async.receive_rb); k_spin_unlock(&backend->async.receive_rb_lock, key); - LOG_WRN("Receive buffer overrun (%zu/%zu dropped)", - evt->data.rx.len - received, evt->data.rx.len); + + LOG_WRN("Receive buffer overrun (dropped %u + %u)", + buf_size - received, (unsigned int)evt->data.rx.len); break; } @@ -146,30 +149,24 @@ static int modem_backend_uart_async_open(void *data) struct modem_backend_uart *backend = (struct modem_backend_uart *)data; int ret; - atomic_set(&backend->async.state, 0); + atomic_clear(&backend->async.state); ring_buf_reset(&backend->async.receive_rb); - /* Reserve receive buffer 0 */ - atomic_set_bit(&backend->async.state, - MODEM_BACKEND_UART_ASYNC_STATE_RX_BUF0_USED_BIT); + atomic_set_bit(&backend->async.state, MODEM_BACKEND_UART_ASYNC_STATE_RX_BUF0_USED_BIT); + atomic_set_bit(&backend->async.state, MODEM_BACKEND_UART_ASYNC_STATE_RECEIVING_BIT); + atomic_set_bit(&backend->async.state, MODEM_BACKEND_UART_ASYNC_STATE_OPEN_BIT); - /* - * Receive buffer 0 is used internally by UART, receive ring buffer 0 is + /* Receive buffers are used internally by UART, receive ring buffer is * used to store received data. */ ret = uart_rx_enable(backend->uart, backend->async.receive_bufs[0], backend->async.receive_buf_size, CONFIG_MODEM_BACKEND_UART_ASYNC_RECEIVE_IDLE_TIMEOUT_MS * 1000L); - if (ret < 0) { + atomic_clear(&backend->async.state); return ret; } - atomic_set_bit(&backend->async.state, - MODEM_BACKEND_UART_ASYNC_STATE_RECEIVING_BIT); - atomic_set_bit(&backend->async.state, - MODEM_BACKEND_UART_ASYNC_STATE_OPEN_BIT); - modem_pipe_notify_opened(&backend->pipe); return 0; } @@ -183,15 +180,12 @@ static int modem_backend_uart_async_transmit(void *data, const uint8_t *buf, siz transmitting = atomic_test_and_set_bit(&backend->async.state, MODEM_BACKEND_UART_ASYNC_STATE_TRANSMITTING_BIT); - if (transmitting) { return 0; } /* Determine amount of bytes to transmit */ - bytes_to_transmit = (size < backend->async.transmit_buf_size) - ? size - : backend->async.transmit_buf_size; + bytes_to_transmit = MIN(size, backend->async.transmit_buf_size); /* Copy buf to transmit buffer which is passed to UART */ memcpy(backend->async.transmit_buf, buf, bytes_to_transmit); From 419a398c0154a6b9a556134b7befc2d78f29782f Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Tue, 19 Mar 2024 09:31:40 +0200 Subject: [PATCH 1348/2402] modem: backends: uart_isr: improve the reception of bytes Add a configurable delay between when a byte is received and MODEM_PIPE_EVENT_RECEIVE_READY is sent. This fixes data reception at baud rates above 460800, and most likely also reduces the workload at any baud rate when receiving bytes by not going through the work item and callbacks for every single byte. Signed-off-by: Tomi Fontanilles --- include/zephyr/modem/backend/uart.h | 2 +- subsys/modem/backends/Kconfig | 20 ++++++++++++-- subsys/modem/backends/modem_backend_uart.c | 7 ++--- .../modem/backends/modem_backend_uart_async.c | 4 +-- .../modem/backends/modem_backend_uart_isr.c | 26 ++++++++++++++----- 5 files changed, 45 insertions(+), 14 deletions(-) diff --git a/include/zephyr/modem/backend/uart.h b/include/zephyr/modem/backend/uart.h index 5f9f99370a0..0280494e350 100644 --- a/include/zephyr/modem/backend/uart.h +++ b/include/zephyr/modem/backend/uart.h @@ -42,7 +42,7 @@ struct modem_backend_uart_async { struct modem_backend_uart { const struct device *uart; struct modem_pipe pipe; - struct k_work receive_ready_work; + struct k_work_delayable receive_ready_work; struct k_work transmit_idle_work; union { diff --git a/subsys/modem/backends/Kconfig b/subsys/modem/backends/Kconfig index 526d179fe30..6bbadc2c588 100644 --- a/subsys/modem/backends/Kconfig +++ b/subsys/modem/backends/Kconfig @@ -22,14 +22,30 @@ config MODEM_BACKEND_UART_ASYNC bool "Modem UART backend module async implementation" default y if UART_ASYNC_API +if MODEM_BACKEND_UART_ISR + +config MODEM_BACKEND_UART_ISR_RECEIVE_IDLE_TIMEOUT_MS + int "Modem ISR UART delay between first byte received and RECEIVE_READY pipe event" + default 20 + help + This defines the delay, in milliseconds, that the backend waits + when receiving a byte before sending the RECEIVE_READY pipe event. + The backend will anyway send the event before this delay if buffer space runs out. + A good value is ~90% the time it takes to fill half the receive buffer. + It can be calculated as follows: + ( / 2) / ( / ) * + By default (for the modem_cellular driver): (512 / 2) / (115200 / 10) * 1000 = 22,222 => 20 + +endif + if MODEM_BACKEND_UART_ASYNC config MODEM_BACKEND_UART_ASYNC_TRANSMIT_TIMEOUT_MS - int "Modem UART async transmit timeout in milliseconds" + int "Modem async UART transmit timeout in milliseconds" default 1000 config MODEM_BACKEND_UART_ASYNC_RECEIVE_IDLE_TIMEOUT_MS - int "Modem UART async receive idle timeout in milliseconds" + int "Modem async UART receive idle timeout in milliseconds" default 30 endif diff --git a/subsys/modem/backends/modem_backend_uart.c b/subsys/modem/backends/modem_backend_uart.c index eef72069ae7..e182a3acd81 100644 --- a/subsys/modem/backends/modem_backend_uart.c +++ b/subsys/modem/backends/modem_backend_uart.c @@ -13,8 +13,8 @@ static void modem_backend_uart_receive_ready_handler(struct k_work *item) { - struct modem_backend_uart *backend = - CONTAINER_OF(item, struct modem_backend_uart, receive_ready_work); + struct modem_backend_uart *backend = CONTAINER_OF( + k_work_delayable_from_work(item), struct modem_backend_uart, receive_ready_work); modem_pipe_notify_receive_ready(&backend->pipe); } @@ -39,7 +39,8 @@ struct modem_pipe *modem_backend_uart_init(struct modem_backend_uart *backend, memset(backend, 0x00, sizeof(*backend)); backend->uart = config->uart; - k_work_init(&backend->receive_ready_work, modem_backend_uart_receive_ready_handler); + k_work_init_delayable(&backend->receive_ready_work, + modem_backend_uart_receive_ready_handler); k_work_init(&backend->transmit_idle_work, modem_backend_uart_transmit_idle_handler); #ifdef CONFIG_MODEM_BACKEND_UART_ASYNC diff --git a/subsys/modem/backends/modem_backend_uart_async.c b/subsys/modem/backends/modem_backend_uart_async.c index 0bd98eb0e7d..c7d4b6297e6 100644 --- a/subsys/modem/backends/modem_backend_uart_async.c +++ b/subsys/modem/backends/modem_backend_uart_async.c @@ -123,7 +123,7 @@ static void modem_backend_uart_async_event_handler(const struct device *dev, } k_spin_unlock(&backend->async.receive_rb_lock, key); - k_work_submit(&backend->receive_ready_work); + k_work_schedule(&backend->receive_ready_work, K_NO_WAIT); break; case UART_RX_DISABLED: @@ -215,7 +215,7 @@ static int modem_backend_uart_async_receive(void *data, uint8_t *buf, size_t siz k_spin_unlock(&backend->async.receive_rb_lock, key); if (!empty) { - k_work_submit(&backend->receive_ready_work); + k_work_schedule(&backend->receive_ready_work, K_NO_WAIT); } return (int)received; diff --git a/subsys/modem/backends/modem_backend_uart_isr.c b/subsys/modem/backends/modem_backend_uart_isr.c index bfa807c1a69..c67c8f7644e 100644 --- a/subsys/modem/backends/modem_backend_uart_isr.c +++ b/subsys/modem/backends/modem_backend_uart_isr.c @@ -30,6 +30,11 @@ static void modem_backend_uart_isr_irq_handler_receive_ready(struct modem_backen receive_rb = &backend->isr.receive_rdb[backend->isr.receive_rdb_used]; size = ring_buf_put_claim(receive_rb, &buffer, UINT32_MAX); if (size == 0) { + /* This can be caused by + * - a too long CONFIG_MODEM_BACKEND_UART_ISR_RECEIVE_IDLE_TIMEOUT_MS + * - or a too small receive_buf_size + * relatively to the (too high) baud rate and amount of incoming data. + */ LOG_WRN("Receive buffer overrun"); ring_buf_put_finish(receive_rb, 0); ring_buf_reset(receive_rb); @@ -37,14 +42,23 @@ static void modem_backend_uart_isr_irq_handler_receive_ready(struct modem_backen } ret = uart_fifo_read(backend->uart, buffer, size); - if (ret < 0) { + if (ret <= 0) { ring_buf_put_finish(receive_rb, 0); - } else { - ring_buf_put_finish(receive_rb, (uint32_t)ret); + return; } - - if (ret > 0) { - k_work_submit(&backend->receive_ready_work); + ring_buf_put_finish(receive_rb, (uint32_t)ret); + + if (ring_buf_space_get(receive_rb) > ring_buf_capacity_get(receive_rb) / 20) { + /* + * Avoid having the receiver call modem_pipe_receive() too often (e.g. every byte). + * It temporarily disables the UART RX IRQ when swapping buffers + * which can cause byte loss at higher baud rates. + */ + k_work_schedule(&backend->receive_ready_work, + K_MSEC(CONFIG_MODEM_BACKEND_UART_ISR_RECEIVE_IDLE_TIMEOUT_MS)); + } else { + /* The buffer is getting full. Run the work item immediately to free up space. */ + k_work_reschedule(&backend->receive_ready_work, K_NO_WAIT); } } From 18170ebce129dd826f00fae229f308a744033d6a Mon Sep 17 00:00:00 2001 From: Tomi Fontanilles Date: Thu, 21 Mar 2024 16:00:07 +0200 Subject: [PATCH 1349/2402] modem: cmux: make work buffer size configurable A Kconfig item is added and the buffer is embedded into the modem_cmux struct. The default value is increased from 16 to 64 bytes in an effort to reduce the number of modem_pipe_receive() calls. CONFIG_MODEM_CHAT_LOG_BUFFER is renamed to CONFIG_MODEM_CHAT_LOG_BUFFER_SIZE for consistency. Signed-off-by: Tomi Fontanilles --- doc/releases/migration-guide-3.7.rst | 6 ++++++ include/zephyr/modem/cmux.h | 2 ++ subsys/modem/Kconfig | 9 +++++++-- subsys/modem/modem_chat.c | 2 +- subsys/modem/modem_cmux.c | 7 +++---- 5 files changed, 19 insertions(+), 7 deletions(-) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index 451e54ecfd3..17884b49b3b 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -188,6 +188,12 @@ LoRaWAN MCUmgr ====== +Modem +===== + +* The ``CONFIG_MODEM_CHAT_LOG_BUFFER`` Kconfig option was + renamed to :kconfig:option:`MODEM_CHAT_LOG_BUFFER_SIZE`. + Shell ===== diff --git a/include/zephyr/modem/cmux.h b/include/zephyr/modem/cmux.h index 58959d6136b..57ee6a8505b 100644 --- a/include/zephyr/modem/cmux.h +++ b/include/zephyr/modem/cmux.h @@ -141,6 +141,8 @@ struct modem_cmux { uint16_t receive_buf_size; uint16_t receive_buf_len; + uint8_t work_buf[CONFIG_MODEM_CMUX_WORK_BUFFER_SIZE]; + /* Transmit buffer */ struct ring_buf transmit_rb; struct k_mutex transmit_rb_lock; diff --git a/subsys/modem/Kconfig b/subsys/modem/Kconfig index 86168ad22c5..a71542a706a 100644 --- a/subsys/modem/Kconfig +++ b/subsys/modem/Kconfig @@ -14,8 +14,8 @@ config MODEM_CHAT if MODEM_CHAT -config MODEM_CHAT_LOG_BUFFER - int "Modem chat log buffer size" +config MODEM_CHAT_LOG_BUFFER_SIZE + int "Modem chat log buffer size in bytes" default 128 endif @@ -29,6 +29,11 @@ config MODEM_CMUX if MODEM_CMUX +config MODEM_CMUX_WORK_BUFFER_SIZE + int "CMUX module work buffer size in bytes" + range 16 1500 + default 64 + module = MODEM_CMUX module-str = modem_cmux source "subsys/logging/Kconfig.template.log_config" diff --git a/subsys/modem/modem_chat.c b/subsys/modem/modem_chat.c index c689ff2e0ab..e2b36d19c31 100644 --- a/subsys/modem/modem_chat.c +++ b/subsys/modem/modem_chat.c @@ -20,7 +20,7 @@ LOG_MODULE_REGISTER(modem_chat, CONFIG_MODEM_MODULES_LOG_LEVEL); #if defined(CONFIG_LOG) && (CONFIG_MODEM_MODULES_LOG_LEVEL == LOG_LEVEL_DBG) -static char log_buffer[CONFIG_MODEM_CHAT_LOG_BUFFER]; +static char log_buffer[CONFIG_MODEM_CHAT_LOG_BUFFER_SIZE]; static void modem_chat_log_received_command(struct modem_chat *chat) { diff --git a/subsys/modem/modem_cmux.c b/subsys/modem/modem_cmux.c index 6fdc1e52841..3fcca3d6068 100644 --- a/subsys/modem/modem_cmux.c +++ b/subsys/modem/modem_cmux.c @@ -842,11 +842,10 @@ static void modem_cmux_receive_handler(struct k_work *item) { struct k_work_delayable *dwork = k_work_delayable_from_work(item); struct modem_cmux *cmux = CONTAINER_OF(dwork, struct modem_cmux, receive_work); - uint8_t buf[16]; int ret; /* Receive data from pipe */ - ret = modem_pipe_receive(cmux->pipe, buf, sizeof(buf)); + ret = modem_pipe_receive(cmux->pipe, cmux->work_buf, sizeof(cmux->work_buf)); if (ret < 1) { if (ret < 0) { LOG_ERR("Pipe receiving error: %d", ret); @@ -855,8 +854,8 @@ static void modem_cmux_receive_handler(struct k_work *item) } /* Process received data */ - for (uint16_t i = 0; i < (uint16_t)ret; i++) { - modem_cmux_process_received_byte(cmux, buf[i]); + for (int i = 0; i < ret; i++) { + modem_cmux_process_received_byte(cmux, cmux->work_buf[i]); } /* Reschedule received work */ From 2ca179c96e3eca078ed13db05b5f9ee7338840da Mon Sep 17 00:00:00 2001 From: Sungwoo Kim Date: Wed, 20 Mar 2024 17:56:49 -0400 Subject: [PATCH 1350/2402] Bluetooth: Host: Add a validation for `hci_le_read_max_data_len()` Check max_tx_octects and max_tx_time are in the valid range, according to the BT Core spec 5.4 [Vol 4, Part E, 7.8.46] Fix #70472 Signed-off-by: Sungwoo Kim --- include/zephyr/bluetooth/hci_types.h | 11 +++++++++++ subsys/bluetooth/host/hci_core.c | 20 ++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/zephyr/bluetooth/hci_types.h b/include/zephyr/bluetooth/hci_types.h index f4a731d1238..98ab1db7190 100644 --- a/include/zephyr/bluetooth/hci_types.h +++ b/include/zephyr/bluetooth/hci_types.h @@ -1272,6 +1272,17 @@ struct bt_hci_cp_le_set_rpa_timeout { uint16_t rpa_timeout; } __packed; +/* All limits according to BT Core spec 5.4 [Vol 4, Part E, 7.8.46] */ +#define BT_HCI_LE_MAX_TX_OCTETS_MIN 0x001B +#define BT_HCI_LE_MAX_TX_OCTETS_MAX 0x00FB +#define BT_HCI_LE_MAX_RX_OCTETS_MIN 0x001B +#define BT_HCI_LE_MAX_RX_OCTETS_MAX 0x00FB + +#define BT_HCI_LE_MAX_TX_TIME_MIN 0x0148 +#define BT_HCI_LE_MAX_TX_TIME_MAX 0x4290 +#define BT_HCI_LE_MAX_RX_TIME_MIN 0x0148 +#define BT_HCI_LE_MAX_RX_TIME_MAX 0x4290 + #define BT_HCI_OP_LE_READ_MAX_DATA_LEN BT_OP(BT_OGF_LE, 0x002f) /* 0x202f */ struct bt_hci_rp_le_read_max_data_len { uint8_t status; diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c index 2138b8ff2f2..81e894d2a70 100644 --- a/subsys/bluetooth/host/hci_core.c +++ b/subsys/bluetooth/host/hci_core.c @@ -407,6 +407,13 @@ static int hci_le_read_max_data_len(uint16_t *tx_octets, uint16_t *tx_time) *tx_time = sys_le16_to_cpu(rp->max_tx_time); net_buf_unref(rsp); + if (!IN_RANGE(*tx_octets, BT_HCI_LE_MAX_TX_OCTETS_MIN, BT_HCI_LE_MAX_TX_OCTETS_MAX)) { + LOG_WRN("tx_octets exceeds the valid range %u", *tx_octets); + } + if (!IN_RANGE(*tx_time, BT_HCI_LE_MAX_TX_TIME_MIN, BT_HCI_LE_MAX_TX_TIME_MAX)) { + LOG_WRN("tx_time exceeds the valid range %u", *tx_time); + } + return 0; } @@ -1682,6 +1689,19 @@ static void le_data_len_change(struct net_buf *buf) uint16_t max_tx_time = sys_le16_to_cpu(evt->max_tx_time); uint16_t max_rx_time = sys_le16_to_cpu(evt->max_rx_time); + if (!IN_RANGE(max_tx_octets, BT_HCI_LE_MAX_TX_OCTETS_MIN, BT_HCI_LE_MAX_TX_OCTETS_MAX)) { + LOG_WRN("max_tx_octets exceeds the valid range %u", max_tx_octets); + } + if (!IN_RANGE(max_rx_octets, BT_HCI_LE_MAX_RX_OCTETS_MIN, BT_HCI_LE_MAX_RX_OCTETS_MAX)) { + LOG_WRN("max_rx_octets exceeds the valid range %u", max_rx_octets); + } + if (!IN_RANGE(max_tx_time, BT_HCI_LE_MAX_TX_TIME_MIN, BT_HCI_LE_MAX_TX_TIME_MAX)) { + LOG_WRN("max_tx_time exceeds the valid range %u", max_tx_time); + } + if (!IN_RANGE(max_rx_time, BT_HCI_LE_MAX_RX_TIME_MIN, BT_HCI_LE_MAX_RX_TIME_MAX)) { + LOG_WRN("max_rx_time exceeds the valid range %u", max_rx_time); + } + LOG_DBG("max. tx: %u (%uus), max. rx: %u (%uus)", max_tx_octets, max_tx_time, max_rx_octets, max_rx_time); From e074f392f5592401a0ec99dc7447ea38683060d7 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 09:52:17 +0100 Subject: [PATCH 1351/2402] doc: Bluetooth: move AutoPTS setup pages In preparation of further cleanup commits. Removes noise in the navigation pane in the rendered docs. Signed-off-by: Jonathan Rico --- .../bluetooth/autopts/autopts-linux.rst | 9 +++++---- .../bluetooth/autopts/autopts-win10.rst | 7 ++++--- doc/connectivity/bluetooth/bluetooth-qual.rst | 16 ++++++++++++++++ doc/connectivity/bluetooth/index.rst | 2 -- 4 files changed, 25 insertions(+), 9 deletions(-) diff --git a/doc/connectivity/bluetooth/autopts/autopts-linux.rst b/doc/connectivity/bluetooth/autopts/autopts-linux.rst index eac940e9737..465d9c0bd2b 100644 --- a/doc/connectivity/bluetooth/autopts/autopts-linux.rst +++ b/doc/connectivity/bluetooth/autopts/autopts-linux.rst @@ -3,9 +3,6 @@ AutoPTS on Linux ################ -Overview -======== - This tutorial shows how to setup AutoPTS client on Linux with AutoPTS server running on Windows 10 virtual machine. Tested with Ubuntu 20.4 and Linux Mint 20.4. @@ -22,8 +19,12 @@ Supported methods to test zephyr bluetooth host: For running with QEMU or :ref:`native_sim `, see :ref:`bluetooth_qemu_native`. +.. contents:: + :local: + :depth: 2 + Setup Linux -=========================== +=========== Install nrftools (only required in the actual hardware test mode) ================================================================= diff --git a/doc/connectivity/bluetooth/autopts/autopts-win10.rst b/doc/connectivity/bluetooth/autopts/autopts-win10.rst index ff308261f44..0c635909e33 100644 --- a/doc/connectivity/bluetooth/autopts/autopts-win10.rst +++ b/doc/connectivity/bluetooth/autopts/autopts-win10.rst @@ -3,14 +3,15 @@ AutoPTS on Windows 10 with nRF52 board ####################################### -Overview -======== - This tutorial shows how to setup AutoPTS client and server to run both on Windows 10. We use WSL1 with Ubuntu only to build a Zephyr project to an elf file, because Zephyr SDK is not available on Windows yet. Tutorial covers only nrf52840dk. +.. contents:: + :local: + :depth: 2 + Update Windows and drivers =========================== diff --git a/doc/connectivity/bluetooth/bluetooth-qual.rst b/doc/connectivity/bluetooth/bluetooth-qual.rst index 1cc8e76f765..2c3392433d2 100644 --- a/doc/connectivity/bluetooth/bluetooth-qual.rst +++ b/doc/connectivity/bluetooth/bluetooth-qual.rst @@ -3,6 +3,22 @@ Bluetooth Qualification ####################### +Qualification setup +******************* + +The Zephyr Bluetooth host can be qualified using Bluetooth's PTS (Profile Tuning +Suite) software. It is originally a manual process, but is automated by using +the `AutoPTS automation software `_. + +The setup is described in more details in the pages linked below. + +.. toctree:: + :maxdepth: 1 + + autopts/autopts-win10.rst + autopts/autopts-linux.rst + + Qualification Listings ********************** diff --git a/doc/connectivity/bluetooth/index.rst b/doc/connectivity/bluetooth/index.rst index ce284b520d4..a39754af78b 100644 --- a/doc/connectivity/bluetooth/index.rst +++ b/doc/connectivity/bluetooth/index.rst @@ -20,7 +20,5 @@ hardware, as well as portions of a Classical Bluetooth (BR/EDR) Host layer. bluetooth-qual.rst bluetooth-tools.rst bluetooth-dev.rst - autopts/autopts-win10.rst - autopts/autopts-linux.rst api/index.rst bluetooth-shell.rst From b96efd78cebc90093e409da0016d1ac965f18462 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 14:14:34 +0100 Subject: [PATCH 1352/2402] doc: Bluetooth: clarify qualification state The BT subsystem has not been officially qualified for a somewhat long time now. The code has diverged quite a bit from what it was. Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/overview.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/connectivity/bluetooth/overview.rst b/doc/connectivity/bluetooth/overview.rst index 1f727736b2d..f36c819d464 100644 --- a/doc/connectivity/bluetooth/overview.rst +++ b/doc/connectivity/bluetooth/overview.rst @@ -35,10 +35,10 @@ Bluetooth stack. * Host-only over UART, SPI, and IPC (shared memory) * Combined (Host + Controller) -* Bluetooth-SIG qualified +* Bluetooth-SIG qualifiable - * Controller on Nordic Semiconductor hardware - * Conformance tests run regularly on all layers + * Conformance tests run regularly on all layers (Controller and Host, except + BT Classic) on Nordic Semiconductor hardware. * Bluetooth Low Energy Controller support (LE Link Layer) From 25292c8d385d80128942759161a668724faf6c5f Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Mon, 25 Mar 2024 21:44:32 +0000 Subject: [PATCH 1353/2402] xtensa: mmu: Remove unused _bss_* _bss_start and _bss_end are not used in ptables.c Just remove them. Signed-off-by: Flavio Ceolin --- arch/xtensa/core/ptables.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/xtensa/core/ptables.c b/arch/xtensa/core/ptables.c index 10b199bcf1e..8b8b3664ea2 100644 --- a/arch/xtensa/core/ptables.c +++ b/arch/xtensa/core/ptables.c @@ -108,9 +108,6 @@ extern char _heap_end[]; extern char _heap_start[]; extern char __data_start[]; extern char __data_end[]; -extern char _bss_start[]; -extern char _bss_end[]; - /* * Static definition of all code & data memory regions of the * current Zephyr image. This information must be available & From 69b831ddcbdba6728c31310f24e100a30e3384fc Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Mon, 25 Mar 2024 21:46:53 +0000 Subject: [PATCH 1354/2402] xtensa: mmu: Remove unused __data_* __data_start and __data_end are not needed in ptables.c Signed-off-by: Flavio Ceolin --- arch/xtensa/core/ptables.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/xtensa/core/ptables.c b/arch/xtensa/core/ptables.c index 8b8b3664ea2..e28fa1aa8f0 100644 --- a/arch/xtensa/core/ptables.c +++ b/arch/xtensa/core/ptables.c @@ -106,8 +106,6 @@ static sys_slist_t xtensa_domain_list; extern char _heap_end[]; extern char _heap_start[]; -extern char __data_start[]; -extern char __data_end[]; /* * Static definition of all code & data memory regions of the * current Zephyr image. This information must be available & From ac8bc6f17f6e3192f0806770c0be24932438606d Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Thu, 21 Mar 2024 22:51:18 -0300 Subject: [PATCH 1355/2402] samples: boards: esp32: add and update sample.yaml files Adds missing sample.yaml file. Update some sample.yaml to include build_only Update some sample.yaml for device testing. Signed-off-by: Sylvio Alves --- samples/boards/esp32/deep_sleep/sample.yaml | 10 ++++++++++ samples/boards/esp32/ethernet/sample.yaml | 1 + samples/boards/esp32/flash_encryption/sample.yaml | 1 + samples/boards/esp32/flash_memory_mapped/sample.yaml | 6 +++++- samples/boards/esp32/flash_memory_mapped/src/main.c | 6 ++++++ samples/boards/esp32/light_sleep/sample.yaml | 10 ++++++++++ samples/boards/esp32/spiram_test/sample.yaml | 6 ++++++ 7 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 samples/boards/esp32/deep_sleep/sample.yaml create mode 100644 samples/boards/esp32/light_sleep/sample.yaml diff --git a/samples/boards/esp32/deep_sleep/sample.yaml b/samples/boards/esp32/deep_sleep/sample.yaml new file mode 100644 index 00000000000..ad5ef41fa7f --- /dev/null +++ b/samples/boards/esp32/deep_sleep/sample.yaml @@ -0,0 +1,10 @@ +sample: + description: Sample application to test ESP32 deep-sleep mode + name: ESP32 Deep-sleep +tests: + sample.board.esp32.deep_sleep: + platform_allow: + - esp32_devkitc_wroom/esp32/procpu + - esp32c3_devkitm + tags: esp32 + build_only: true diff --git a/samples/boards/esp32/ethernet/sample.yaml b/samples/boards/esp32/ethernet/sample.yaml index 35f9b4a44af..005b30ce018 100644 --- a/samples/boards/esp32/ethernet/sample.yaml +++ b/samples/boards/esp32/ethernet/sample.yaml @@ -5,3 +5,4 @@ tests: sample.board.esp32.ethernet: platform_allow: esp32_ethernet_kit/esp32/procpu tags: esp32 + build_only: true diff --git a/samples/boards/esp32/flash_encryption/sample.yaml b/samples/boards/esp32/flash_encryption/sample.yaml index 26e7f309f09..81a7fdcc870 100644 --- a/samples/boards/esp32/flash_encryption/sample.yaml +++ b/samples/boards/esp32/flash_encryption/sample.yaml @@ -8,3 +8,4 @@ tests: - esp32_devkitc_wrover/esp32/procpu - yd_esp32/esp32/procpu tags: esp32 + build_only: true diff --git a/samples/boards/esp32/flash_memory_mapped/sample.yaml b/samples/boards/esp32/flash_memory_mapped/sample.yaml index 83ccc9f4101..8e622c431d2 100644 --- a/samples/boards/esp32/flash_memory_mapped/sample.yaml +++ b/samples/boards/esp32/flash_memory_mapped/sample.yaml @@ -7,4 +7,8 @@ tests: - esp32_devkitc_wroom/esp32/procpu - esp32c3_devkitm - esp32s3_devkitm/esp32s3/procpu - tags: esp32 + harness: console + harness_config: + type: one_line + regex: + - "memory-mapped reading matches flash API read" diff --git a/samples/boards/esp32/flash_memory_mapped/src/main.c b/samples/boards/esp32/flash_memory_mapped/src/main.c index a29d6db08ec..d836bb34816 100644 --- a/samples/boards/esp32/flash_memory_mapped/src/main.c +++ b/samples/boards/esp32/flash_memory_mapped/src/main.c @@ -53,6 +53,12 @@ int main(void) LOG_HEXDUMP_INF(mem_ptr, 32, "flash read using memory-mapped pointer"); + if (memcmp(buffer, mem_ptr, 32) == 0) { + LOG_INF("memory-mapped reading matches flash API read"); + } else { + LOG_ERR("memory-mapped reading does not match flash API read"); + } + /* unmap mapped region */ spi_flash_munmap(handle); diff --git a/samples/boards/esp32/light_sleep/sample.yaml b/samples/boards/esp32/light_sleep/sample.yaml new file mode 100644 index 00000000000..4efecbad8e0 --- /dev/null +++ b/samples/boards/esp32/light_sleep/sample.yaml @@ -0,0 +1,10 @@ +sample: + description: Sample application to test ESP32 light-sleep mode + name: ESP32 Light-sleep +tests: + sample.board.esp32.light_sleep: + platform_allow: + - esp32_devkitc_wroom/esp32/procpu + - esp32c3_devkitm + tags: esp32 + build_only: true diff --git a/samples/boards/esp32/spiram_test/sample.yaml b/samples/boards/esp32/spiram_test/sample.yaml index 20c01a3028a..695e2b2f8dc 100644 --- a/samples/boards/esp32/spiram_test/sample.yaml +++ b/samples/boards/esp32/spiram_test/sample.yaml @@ -5,3 +5,9 @@ tests: sample.board.esp32.spiram: platform_allow: esp32_devkitc_wrover/esp32/procpu tags: esp32 + harness: console + harness_config: + type: multi_line + regex: + - "SPIRAM mem test pass" + - "Internal mem test pass" From 215782aa5c5acf8e7b4886b801f95ba459845c74 Mon Sep 17 00:00:00 2001 From: Marco Argiolas Date: Tue, 13 Feb 2024 13:32:43 +0800 Subject: [PATCH 1356/2402] net: lib: lwm2m: fix function parameter for SW management object Fix build error. Signed-off-by: Marco Argiolas --- subsys/net/lib/lwm2m/lwm2m_obj_swmgmt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/lib/lwm2m/lwm2m_obj_swmgmt.c b/subsys/net/lib/lwm2m/lwm2m_obj_swmgmt.c index 1ccd22520b6..f1466be6c87 100644 --- a/subsys/net/lib/lwm2m/lwm2m_obj_swmgmt.c +++ b/subsys/net/lib/lwm2m/lwm2m_obj_swmgmt.c @@ -209,7 +209,7 @@ static void set_sw_update_state(struct lwm2m_swmgmt_data *instance, uint8_t stat instance->obj_inst_id, SWMGMT_UPDATE_STATE_ID); - ret = lwm2m_set_u8(obj_path, state); + ret = lwm2m_set_u8(&obj_path, state); if (ret != 0) { LOG_ERR("Could not set state"); } From 2f35d11bfe7d4a27d2371d65335172c9f0cd8f97 Mon Sep 17 00:00:00 2001 From: Marco Argiolas Date: Tue, 13 Feb 2024 13:17:38 +0800 Subject: [PATCH 1357/2402] net: lib: lwm2m: block 0 resets prev block transfer for same resource As stated in "[RFC7959], Section 2.5": "The Block1 Option provides no way for a single endpoint to perform multiple concurrently proceeding block-wise request payload transfer (e.g., PUT or POST) operations to the same resource. Starting a new block-wise sequence of requests to the same resource (before an old sequence from the same endpoint was finished) simply overwrites the context the server may still be keeping." Signed-off-by: Marco Argiolas --- subsys/net/lib/lwm2m/lwm2m_message_handling.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/subsys/net/lib/lwm2m/lwm2m_message_handling.c b/subsys/net/lib/lwm2m/lwm2m_message_handling.c index 19a2e1ccdd0..5cc82f165c5 100644 --- a/subsys/net/lib/lwm2m/lwm2m_message_handling.c +++ b/subsys/net/lib/lwm2m/lwm2m_message_handling.c @@ -2055,11 +2055,15 @@ static int parse_write_op(struct lwm2m_message *msg, uint16_t format) block_num = GET_BLOCK_NUM(block_opt); - /* Try to retrieve existing block context. If one not exists, - * and we've received first block, allocate new context. + /* + * RFC7959: 2.5. Using the Block1 Option + * If we've received first block, replace old context (if any) with a new one. */ r = get_block_ctx(&msg->path, &block_ctx); - if (r < 0 && block_num == 0) { + if (block_num == 0) { + /* free block context for previous incomplete transfer */ + free_block_ctx(block_ctx); + r = init_block_ctx(&msg->path, &block_ctx); } From a0e32f07ef76b7cf1da4b52d654a4e43aca3ccca Mon Sep 17 00:00:00 2001 From: Adrian Bonislawski Date: Fri, 22 Mar 2024 08:46:50 +0100 Subject: [PATCH 1358/2402] dts: intel_adsp: ace: update host dma copy alignment This will update host dma copy aligmnet as with current high value in some cases it was not possible to fully empty the buffer Signed-off-by: Adrian Bonislawski --- dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi | 8 ++++---- dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi index a6fac22ba06..9c92387e36a 100644 --- a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi @@ -460,7 +460,7 @@ dma-channels = <9>; dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; - dma-copy-alignment = <32>; + dma-copy-alignment = <16>; power-domain = <&io0_domain>; status = "okay"; }; @@ -472,7 +472,7 @@ dma-channels = <10>; dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; - dma-copy-alignment = <32>; + dma-copy-alignment = <16>; power-domain = <&io0_domain>; status = "okay"; }; @@ -484,7 +484,7 @@ dma-channels = <9>; dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; - dma-copy-alignment = <32>; + dma-copy-alignment = <16>; power-domain = <&hst_domain>; interrupts = <13 0 0>; interrupt-parent = <&ace_intc>; @@ -498,7 +498,7 @@ dma-channels = <10>; dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; - dma-copy-alignment = <32>; + dma-copy-alignment = <16>; power-domain = <&hst_domain>; interrupts = <12 0 0>; interrupt-parent = <&ace_intc>; diff --git a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi index f654133f0ef..91535c92dcd 100644 --- a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi @@ -371,7 +371,7 @@ dma-channels = <9>; dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; - dma-copy-alignment = <32>; + dma-copy-alignment = <16>; interrupts = <13 0 0>; interrupt-parent = <&ace_intc>; status = "okay"; @@ -384,7 +384,7 @@ dma-channels = <11>; dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; - dma-copy-alignment = <32>; + dma-copy-alignment = <16>; interrupts = <12 0 0>; interrupt-parent = <&ace_intc>; status = "okay"; @@ -405,7 +405,7 @@ dma-channels = <9>; dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; - dma-copy-alignment = <32>; + dma-copy-alignment = <16>; status = "okay"; }; @@ -416,7 +416,7 @@ dma-channels = <11>; dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; - dma-copy-alignment = <32>; + dma-copy-alignment = <16>; status = "okay"; }; From a0ddba5faa750b35cdc60949034b54544a79a612 Mon Sep 17 00:00:00 2001 From: Charles Dias Date: Mon, 29 Jan 2024 19:13:18 -0300 Subject: [PATCH 1359/2402] boards: arm: update STM32H7B3I DK Kconfig Update Kconfig to improve LVGL Demo performance. - enable ICache, DCache, and cache management. - enable Chrom-ART. - enable double frame buffer and full refresh. - set bits per pixel to 16. Signed-off-by: Charles Dias --- boards/st/stm32h7b3i_dk/CMakeLists.txt | 9 ++ boards/st/stm32h7b3i_dk/Kconfig.defconfig | 35 ++++++ boards/st/stm32h7b3i_dk/dc_ram.ld | 16 +++ boards/st/stm32h7b3i_dk/doc/index.rst | 135 +++++++++++++++++++--- boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts | 3 +- 5 files changed, 180 insertions(+), 18 deletions(-) create mode 100644 boards/st/stm32h7b3i_dk/CMakeLists.txt create mode 100644 boards/st/stm32h7b3i_dk/dc_ram.ld diff --git a/boards/st/stm32h7b3i_dk/CMakeLists.txt b/boards/st/stm32h7b3i_dk/CMakeLists.txt new file mode 100644 index 00000000000..6edbccee55c --- /dev/null +++ b/boards/st/stm32h7b3i_dk/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) Charles Dias +# +# SPDX-License-Identifier: Apache-2.0 +# + +# Add custom linker section to relocate framebuffers to PSRAM +zephyr_linker_sources_ifdef(CONFIG_LV_Z_VBD_CUSTOM_SECTION + SECTIONS dc_ram.ld) diff --git a/boards/st/stm32h7b3i_dk/Kconfig.defconfig b/boards/st/stm32h7b3i_dk/Kconfig.defconfig index 39101c47f7b..863570e555a 100644 --- a/boards/st/stm32h7b3i_dk/Kconfig.defconfig +++ b/boards/st/stm32h7b3i_dk/Kconfig.defconfig @@ -1,6 +1,7 @@ # STM32H7B3I DISCOVERY KIT board configuration # Copyright (c) 2022 Byte-Lab d.o.o. +# Copyright (c) 2024 Charles Dias # SPDX-License-Identifier: Apache-2.0 if BOARD_STM32H7B3I_DK @@ -16,4 +17,38 @@ config INPUT_FT5336_INTERRUPT config MEMC default y if DISPLAY +if LVGL + +config CACHE_MANAGEMENT + default y + +config LV_USE_GPU_STM32_DMA2D + default y + +config LV_GPU_DMA2D_CMSIS_INCLUDE + default "stm32h7xx.h" + +config STM32_LTDC_FB_NUM + default 2 + +config LV_Z_VDB_SIZE + default 100 + +config LV_Z_DOUBLE_VDB + default y + +config LV_Z_FULL_REFRESH + default y + +config LV_Z_VBD_CUSTOM_SECTION + default y + +config LV_Z_FLUSH_THREAD + default y + +config LV_Z_BITS_PER_PIXEL + default 16 if STM32_LTDC_RGB565 + +endif # LVGL + endif # BOARD_STM32H7B3I_DK diff --git a/boards/st/stm32h7b3i_dk/dc_ram.ld b/boards/st/stm32h7b3i_dk/dc_ram.ld new file mode 100644 index 00000000000..3f67ed559cb --- /dev/null +++ b/boards/st/stm32h7b3i_dk/dc_ram.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) Charles Dias + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay) +GROUP_START(SDRAM2) + + SECTION_PROLOGUE(_STM32_SDRAM2_SECTION_NAME, (NOLOAD),) + { + *(.lvgl_buf) + } GROUP_LINK_IN(SDRAM2) + +GROUP_END(SDRAM2) +#endif diff --git a/boards/st/stm32h7b3i_dk/doc/index.rst b/boards/st/stm32h7b3i_dk/doc/index.rst index 98f00c34234..dd1c6317e78 100644 --- a/boards/st/stm32h7b3i_dk/doc/index.rst +++ b/boards/st/stm32h7b3i_dk/doc/index.rst @@ -1,6 +1,6 @@ .. _stm32h7b3i_dk_board: -ST STM32H7B3I Discovery Kit +ST STM32H7B3I Discovery kit ########################### Overview @@ -21,16 +21,77 @@ camera, SDRAM, Octo-SPI Flash memory and RGB interface LCD with capacitive touch panel). ARDUINO® Uno V3 connectors provide easy connection to extension shields or daughterboards for specific applications. -STLINK-V3E is integrated into the board, as an embedded in-circuit debugger and -programmer for the STM32 MCU and the USB Virtual COM port bridge. The STM32H7B3I-DK -board comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive -software HAL library as well as various software examples. +Important board features include: + +- STM32H7B3LIH6Q microcontroller featuring 2 Mbytes of Flash memory and 1.4 Mbyte of RAM in BGA225 package +- 4.3" (480x272 pixels) TFT color LCD module including a capacitive touch panel with RGB interface +- Wi-Fi |reg| module compliant with 802.11 b/g/n +- USB OTG HS +- Audio codec +- 512-Mbit Octo-SPI NOR Flash memory +- 128-Mbit SDRAM +- 2 user LEDs +- User and Reset push-buttons +- Fanout daughterboard +- 1x FDCAN +- Board connectors: + - Camera (8 bit) + - USB with Micro-AB + - Stereo headset jack including analog microphone input + - Audio jack for external speakers + - microSD |trade| card + - TAG-Connect 10-pin footprint + - Arm |reg| Cortex |reg| 10-pin 1.27mm-pitch debug connector over STDC14 footprint + - ARDUINO |reg| Uno V3 expansion connector + - STMod+ expansion connector + - Audio daughterboard expansion connector + - External I2C expansion connector +- Flexible power-supply options: + - ST-LINK USB VBUS, USB OTG HS connector, or external sources +- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability .. image:: img/stm32h7b3i_dk.jpg :align: center :alt: STM32H7B3I-DK More information about the board can be found at the `STM32H7B3I-DK website`_. + +Hardware +******** + +The STM32H7B3I Discovery kit provides the following hardware components: + +- STM32H7B3LIH6Q in BGA225 package +- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU +- 280 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 2 MB Flash +- ~1.4 Mbytes SRAM +- 32-bit timers(2) +- 16-bit timers(15) +- SPI(6) +- I2C(4) +- I2S (4) +- USART(5) +- UART(5) +- USB OTG Full Speed and High Speed(1) +- CAN FD(2) +- 2xSAI (serial audio interface) +- SPDIFRX interface(1) +- HDMI-CEC(1) +- Octo-SPI memory interfaces with on-the-fly decryption(2) +- 8- to 14-bit camera interface (1) +- 8-/16-bit parallel synchronous data input/output slave interface (PSSI) +- GPIO (up to 168) with external interrupt capability +- 16-bit ADC(2) with 24 channels / 3.6 MSPS +- 1x12-bit single-channel DAC + 1x12-bit dual-channel DAC +- True Random Number Generator (RNG) +- 5 DMA controllers +- LCD-TFT Controller with XGA resolution +- Chrom-ART graphical hardware Accelerator (DMA2D) +- Hardware JPEG Codec +- Chrom-GRC™ (GFXMMU) + More information about STM32H7B3 can be found here: - `STM32H7A3/7B3 on www.st.com`_ @@ -56,6 +117,12 @@ The current Zephyr stm32h7b3i_dk board configuration supports the following hard +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| OSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ | FLASH | on-chip | flash memory | +-----------+------------+-------------------------------------+ | FMC | on-chip | memc (SDRAM) | @@ -74,11 +141,17 @@ The default configuration can be found in the defconfig file: Pin Mapping =========== -For more details please refer to `STM32H7B3I-DK website`_. +STM32H7B3I Discovery kit has 11 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32H7B3I-DK board User Manual`_. Default Zephyr Peripheral Mapping: ---------------------------------- +The STM32H7B3I Discovery kit features an Arduino Uno V3 connector. Board is +configured as follows + - UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) - UART_4 TX/RX : PH13/PH14 (Arduino Serial) - I2C4 SCL/SDA : PD12/PD13 (Arduino I2C, Touchscreen FT5336 with PH2 Interrupt Pin) @@ -101,7 +174,7 @@ Default Zephyr Peripheral Mapping: - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 - - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 + - B0-B7 : PJ12/PJ13/PJ14/PJ15/PK3/PK4/PK5/PK6 - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 @@ -115,26 +188,51 @@ by the PLL clock at 280MHz. PLL clock is fed by a 24MHz high speed external cloc Serial Port =========== -The STM32H7B3I Discovery kit has up to 8 UARTs. -The Zephyr console output is assigned to UART1 which connected to the onboard -ST-LINK/V3.0. Virtual COM port interface. Default communication settings are -115200 8N1. +The STM32H7B3I Discovery kit has up to 10 UARTs. The Zephyr console output is assigned +to UART1 which is connected to the onboard STLINK-V3E. Virtual COM port interface +default communication settings are 115200 8N1. Programming and Debugging ************************* -See :ref:`build_an_application` for more information about application builds. - +Applications for the ``stm32h7b3i_dk`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). Flashing ======== -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. -It is advised to use `STM32CubeProgrammer`_ to check and update option bytes -configuration and flash the ``stm32h7b3i_dk`` target. +STM32H7B3I Discovery kit includes an STLINK-V3E embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing may depend on the SoC option bytes configuration, which can be checked and +updated using `STM32CubeProgrammer`_. + +Flashing an application to STM32H7B3I +------------------------------------- +First, connect the STM32H7B3I Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h7b3i_dk + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm Debugging ========= @@ -151,6 +249,9 @@ You can debug an application in the usual way. Here is an example for the .. _STM32H7B3I-DK website: https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html +.. _STM32H7B3I-DK board User Manual: + https://www.st.com/resource/en/user_manual/um2569-discovery-kit-with-stm32h7b3li-mcu-stmicroelectronics.pdf + .. _STM32H7A3/7B3 on www.st.com: https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3-7b3.html diff --git a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts index 2ca13215b5e..1567585b2fd 100644 --- a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts +++ b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts @@ -55,7 +55,8 @@ device_type = "memory"; reg = <0xd0000000 DT_SIZE_M(16)>; zephyr,memory-region = "SDRAM2"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + /* Frame buffer memory cache will cause screen flickering. */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; }; transceiver0: can-phy0 { From f967e08364fa4de606f007edf585755cd1f2f042 Mon Sep 17 00:00:00 2001 From: Andries Kruithof Date: Tue, 6 Feb 2024 14:56:41 +0100 Subject: [PATCH 1360/2402] Bluetooth: audio: test: Refactor unit test The unittest for cap commander is refactored, so that tests for volumecontrol is in its own module. This avoids the problem of having all tests in one huge file. Due to their small size the tests for registering callbacks and discovery haven't been put into their own module. Signed-off-by: Andries Kruithof --- .../audio/cap_commander/CMakeLists.txt | 3 + .../audio/cap_commander/include/test_common.h | 12 + .../bluetooth/audio/cap_commander/src/main.c | 939 +----------------- .../audio/cap_commander/src/test_common.c | 43 + .../audio/cap_commander/src/test_micp.c | 293 ++++++ .../audio/cap_commander/src/test_vcp.c | 753 ++++++++++++++ 6 files changed, 1108 insertions(+), 935 deletions(-) create mode 100644 tests/bluetooth/audio/cap_commander/include/test_common.h create mode 100644 tests/bluetooth/audio/cap_commander/src/test_common.c create mode 100644 tests/bluetooth/audio/cap_commander/src/test_micp.c create mode 100644 tests/bluetooth/audio/cap_commander/src/test_vcp.c diff --git a/tests/bluetooth/audio/cap_commander/CMakeLists.txt b/tests/bluetooth/audio/cap_commander/CMakeLists.txt index 17f6ad2f4b2..11a19d9530d 100644 --- a/tests/bluetooth/audio/cap_commander/CMakeLists.txt +++ b/tests/bluetooth/audio/cap_commander/CMakeLists.txt @@ -15,4 +15,7 @@ target_sources(testbinary PRIVATE ${ZEPHYR_BASE}/subsys/bluetooth/host/uuid.c src/main.c + src/test_common.c + src/test_vcp.c + src/test_micp.c ) diff --git a/tests/bluetooth/audio/cap_commander/include/test_common.h b/tests/bluetooth/audio/cap_commander/include/test_common.h new file mode 100644 index 00000000000..e60be9cc233 --- /dev/null +++ b/tests/bluetooth/audio/cap_commander/include/test_common.h @@ -0,0 +1,12 @@ +/* test_common.h */ + +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +void test_mocks_init(void); +void test_mocks_cleanup(void); + +void test_conn_init(struct bt_conn *conn); diff --git a/tests/bluetooth/audio/cap_commander/src/main.c b/tests/bluetooth/audio/cap_commander/src/main.c index 435a9fe85dd..a55a4442dae 100644 --- a/tests/bluetooth/audio/cap_commander/src/main.c +++ b/tests/bluetooth/audio/cap_commander/src/main.c @@ -1,7 +1,7 @@ /* main.c - Application main entry point */ /* - * Copyright (c) 2023 Nordic Semiconductor ASA + * Copyright (c) 2023-2024 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,36 +9,24 @@ #include #include -#include -#include #include #include "bluetooth.h" #include "cap_commander.h" #include "conn.h" #include "expects_util.h" -#include "cap_mocks.h" +#include "test_common.h" DEFINE_FFF_GLOBALS; static void mock_init_rule_before(const struct ztest_unit_test *test, void *fixture) { - mock_cap_commander_init(); - mock_bt_aics_init(); - mock_bt_csip_init(); - mock_bt_micp_init(); - mock_bt_vcp_init(); - mock_bt_vocs_init(); + test_mocks_init(); } static void mock_destroy_rule_after(const struct ztest_unit_test *test, void *fixture) { - mock_cap_commander_cleanup(); - mock_bt_aics_cleanup(); - mock_bt_csip_cleanup(); - mock_bt_micp_cleanup(); - mock_bt_vcp_cleanup(); - mock_bt_vocs_cleanup(); + test_mocks_cleanup(); } ZTEST_RULE(mock_rule, mock_init_rule_before, mock_destroy_rule_after); @@ -47,17 +35,6 @@ struct cap_commander_test_suite_fixture { struct bt_conn conns[CONFIG_BT_MAX_CONN]; }; -static void test_conn_init(struct bt_conn *conn) -{ - conn->index = 0; - conn->info.type = BT_CONN_TYPE_LE; - conn->info.role = BT_CONN_ROLE_PERIPHERAL; - conn->info.state = BT_CONN_STATE_CONNECTED; - conn->info.security.level = BT_SECURITY_L2; - conn->info.security.enc_key_size = BT_ENC_KEY_SIZE_MAX; - conn->info.security.flags = BT_SECURITY_FLAG_OOB | BT_SECURITY_FLAG_SC; -} - static void cap_commander_test_suite_fixture_init(struct cap_commander_test_suite_fixture *fixture) { for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { @@ -187,911 +164,3 @@ ZTEST_F(cap_commander_test_suite, test_commander_discover_inval_param_null) err = bt_cap_commander_discover(NULL); zassert_equal(-EINVAL, err, "Unexpected return value %d", err); } - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = ARRAY_SIZE(fixture->conns), - .volume = 177, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ - - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - - err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.volume_changed", 1, - mock_cap_commander_volume_changed_cb_fake.call_count); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_double) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = ARRAY_SIZE(fixture->conns), - .volume = 177, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ - - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - - err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.volume_changed", 1, - mock_cap_commander_volume_changed_cb_fake.call_count); - - /* Verify that it still works as expected if we set the same value twice */ - err = bt_cap_commander_change_volume(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.volume_changed", 2, - mock_cap_commander_volume_changed_cb_fake.call_count); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_inval_param_null) -{ - int err; - - err = bt_cap_commander_change_volume(NULL); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_inval_param_null_members) -{ - const struct bt_cap_commander_change_volume_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = NULL, - .count = ARRAY_SIZE(fixture->conns), - .volume = 177, - }; - int err; - - err = bt_cap_commander_change_volume(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_inval_param_null_member) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = ARRAY_SIZE(fixture->conns), - .volume = 177, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members) - 1; i++) { - members[i].member = &fixture->conns[i]; - } - members[ARRAY_SIZE(members) - 1].member = NULL; - - err = bt_cap_commander_change_volume(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_inval_missing_cas) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = ARRAY_SIZE(fixture->conns), - .volume = 177, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ - - err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_inval_missing_vcs) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = ARRAY_SIZE(fixture->conns), - .volume = 177, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_inval_param_zero_count) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = 0U, - .volume = 177, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_change_volume(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_inval_param_inval_count) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = CONFIG_BT_MAX_CONN + 1, - .volume = 177, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_change_volume(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_offset) -{ - struct bt_cap_commander_change_volume_offset_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_offset_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].offset = 100 + i; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ - - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - - err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume_offset(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.volume_offset_changed", 1, - mock_cap_commander_volume_offset_changed_cb_fake.call_count); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_offset_double) -{ - struct bt_cap_commander_change_volume_offset_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_offset_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].offset = 100 + i; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ - - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - - err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume_offset(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.volume_offset_changed", 1, - mock_cap_commander_volume_offset_changed_cb_fake.call_count); - - /* Verify that it still works as expected if we set the same value twice */ - err = bt_cap_commander_change_volume_offset(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.volume_offset_changed", 2, - mock_cap_commander_volume_offset_changed_cb_fake.call_count); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_offset_inval_param_null) -{ - int err; - - err = bt_cap_commander_change_volume_offset(NULL); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_offset_inval_param_null_param) -{ - const struct bt_cap_commander_change_volume_offset_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = NULL, - .count = ARRAY_SIZE(fixture->conns), - }; - int err; - - err = bt_cap_commander_change_volume_offset(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_offset_inval_param_null_member) -{ - struct bt_cap_commander_change_volume_offset_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_offset_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].offset = 100 + i; - } - member_params[ARRAY_SIZE(member_params) - 1].member.member = NULL; - - err = bt_cap_commander_change_volume_offset(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_offset_inval_missing_cas) -{ - struct bt_cap_commander_change_volume_offset_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_offset_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].offset = 100 + i; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ - - err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume_offset(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_offset_inval_missing_vocs) -{ - struct bt_cap_commander_change_volume_offset_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_offset_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].offset = 100 + i; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume_offset(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_offset_inval_param_zero_count) -{ - struct bt_cap_commander_change_volume_offset_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_offset_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = 0U, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].offset = 100 + i; - } - - err = bt_cap_commander_change_volume_offset(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_offset_inval_param_inval_count) -{ - struct bt_cap_commander_change_volume_offset_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_offset_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = CONFIG_BT_MAX_CONN + 1, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].offset = 100 + i; - } - - err = bt_cap_commander_change_volume_offset(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_offset_inval_param_inval_offset_max) -{ - struct bt_cap_commander_change_volume_offset_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_offset_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].offset = BT_VOCS_MAX_OFFSET + 1; - } - - err = bt_cap_commander_change_volume_offset(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_offset_inval_param_inval_offset_min) -{ - struct bt_cap_commander_change_volume_offset_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_offset_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].offset = BT_VOCS_MIN_OFFSET - 1; - } - - err = bt_cap_commander_change_volume_offset(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_mute_state) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_mute_state_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = ARRAY_SIZE(fixture->conns), - .mute = true, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ - - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - - err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume_mute_state(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.volume_mute_changed", 1, - mock_cap_commander_volume_mute_changed_cb_fake.call_count); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_mute_state_double) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_mute_state_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = ARRAY_SIZE(fixture->conns), - .mute = true, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ - - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - - err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume_mute_state(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.volume_mute_changed", 1, - mock_cap_commander_volume_mute_changed_cb_fake.call_count); - - /* Verify that it still works as expected if we set the same value twice */ - err = bt_cap_commander_change_volume_mute_state(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.volume_mute_changed", 2, - mock_cap_commander_volume_mute_changed_cb_fake.call_count); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_mute_state_inval_param_null) -{ - int err; - - err = bt_cap_commander_change_volume_mute_state(NULL); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_mute_state_inval_param_null_members) -{ - const struct bt_cap_commander_change_volume_mute_state_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = NULL, - .count = ARRAY_SIZE(fixture->conns), - .mute = true, - }; - int err; - - err = bt_cap_commander_change_volume_mute_state(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_mute_state_inval_param_null_member) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_mute_state_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = ARRAY_SIZE(fixture->conns), - .mute = true, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members) - 1; i++) { - members[i].member = &fixture->conns[i]; - } - members[ARRAY_SIZE(members) - 1].member = NULL; - - err = bt_cap_commander_change_volume_mute_state(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_mute_state_inval_missing_cas) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_mute_state_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = ARRAY_SIZE(fixture->conns), - .mute = true, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ - - err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume_mute_state(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_mute_state_inval_missing_vcs) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_mute_state_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = ARRAY_SIZE(fixture->conns), - .mute = true, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_volume_mute_state(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_mute_state_inval_param_zero_count) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_mute_state_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = 0U, - .mute = true, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_change_volume_mute_state(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_volume_mute_state_inval_param_inval_count) -{ - union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_volume_mute_state_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .members = members, - .count = CONFIG_BT_MAX_CONN + 1, - .mute = true, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { - members[i].member = &fixture->conns[i]; - } - - err = bt_cap_commander_change_volume_mute_state(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_microphone_gain_setting) -{ - struct bt_cap_commander_change_microphone_gain_setting_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_microphone_gain_setting_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].gain = 10 + i; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ - - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - - err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_microphone_gain_setting(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.microphone_gain_setting_changed", 1, - mock_cap_commander_microphone_gain_changed_cb_fake.call_count); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_microphone_gain_setting_double) -{ - struct bt_cap_commander_change_microphone_gain_setting_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_microphone_gain_setting_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].gain = 10 + i; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ - - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - - err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_microphone_gain_setting(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.microphone_gain_setting_changed", 1, - mock_cap_commander_microphone_gain_changed_cb_fake.call_count); - - /* That that it still works as expected if we set the same value twice */ - err = bt_cap_commander_change_microphone_gain_setting(¶m); - zassert_equal(0, err, "Unexpected return value %d", err); - - zexpect_call_count("bt_cap_commander_cb.microphone_gain_setting_changed", 2, - mock_cap_commander_microphone_gain_changed_cb_fake.call_count); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_microphone_gain_setting_inval_param_null) -{ - int err; - - err = bt_cap_commander_change_microphone_gain_setting(NULL); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, - test_commander_change_microphone_gain_setting_inval_param_null_param) -{ - const struct bt_cap_commander_change_microphone_gain_setting_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = NULL, - .count = ARRAY_SIZE(fixture->conns), - }; - int err; - - err = bt_cap_commander_change_microphone_gain_setting(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, - test_commander_change_microphone_gain_setting_inval_param_null_member) -{ - struct bt_cap_commander_change_microphone_gain_setting_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_microphone_gain_setting_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].gain = 10 + i; - } - member_params[ARRAY_SIZE(member_params) - 1].member.member = NULL; - - err = bt_cap_commander_change_microphone_gain_setting(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_microphone_gain_setting_inval_missing_cas) -{ - struct bt_cap_commander_change_microphone_gain_setting_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_microphone_gain_setting_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].gain = 10 + i; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ - - err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_microphone_gain_setting(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, test_commander_change_microphone_gain_setting_inval_missing_aics) -{ - struct bt_cap_commander_change_microphone_gain_setting_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_microphone_gain_setting_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = ARRAY_SIZE(member_params), - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].gain = 10 + i; - } - - err = bt_cap_commander_register_cb(&mock_cap_commander_cb); - zassert_equal(0, err, "Unexpected return value %d", err); - - for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { - err = bt_cap_commander_discover(&fixture->conns[i]); - zassert_equal(0, err, "Unexpected return value %d", err); - } - - err = bt_cap_commander_change_microphone_gain_setting(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, - test_commander_change_microphone_gain_setting_inval_param_zero_count) -{ - struct bt_cap_commander_change_microphone_gain_setting_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_microphone_gain_setting_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = 0U, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].gain = 10 + i; - } - - err = bt_cap_commander_change_microphone_gain_setting(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} - -ZTEST_F(cap_commander_test_suite, - test_commander_change_microphone_gain_setting_inval_param_inval_count) -{ - struct bt_cap_commander_change_microphone_gain_setting_member_param - member_params[ARRAY_SIZE(fixture->conns)]; - const struct bt_cap_commander_change_microphone_gain_setting_param param = { - .type = BT_CAP_SET_TYPE_AD_HOC, - .param = member_params, - .count = CONFIG_BT_MAX_CONN + 1, - }; - int err; - - for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { - member_params[i].member.member = &fixture->conns[i]; - member_params[i].gain = 10 + i; - } - - err = bt_cap_commander_change_microphone_gain_setting(¶m); - zassert_equal(-EINVAL, err, "Unexpected return value %d", err); -} diff --git a/tests/bluetooth/audio/cap_commander/src/test_common.c b/tests/bluetooth/audio/cap_commander/src/test_common.c new file mode 100644 index 00000000000..e254694c7d9 --- /dev/null +++ b/tests/bluetooth/audio/cap_commander/src/test_common.c @@ -0,0 +1,43 @@ +/* test_common.c - common procedures for unit test of CAP commander */ + +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "cap_commander.h" +#include "conn.h" +#include "cap_mocks.h" +#include "test_common.h" + +void test_mocks_init(void) +{ + mock_cap_commander_init(); + mock_bt_aics_init(); + mock_bt_csip_init(); + mock_bt_micp_init(); + mock_bt_vcp_init(); + mock_bt_vocs_init(); +} + +void test_mocks_cleanup(void) +{ + mock_cap_commander_cleanup(); + mock_bt_aics_cleanup(); + mock_bt_csip_cleanup(); + mock_bt_micp_cleanup(); + mock_bt_vcp_cleanup(); + mock_bt_vocs_cleanup(); +} + +void test_conn_init(struct bt_conn *conn) +{ + conn->index = 0; + conn->info.type = BT_CONN_TYPE_LE; + conn->info.role = BT_CONN_ROLE_PERIPHERAL; + conn->info.state = BT_CONN_STATE_CONNECTED; + conn->info.security.level = BT_SECURITY_L2; + conn->info.security.enc_key_size = BT_ENC_KEY_SIZE_MAX; + conn->info.security.flags = BT_SECURITY_FLAG_OOB | BT_SECURITY_FLAG_SC; +} diff --git a/tests/bluetooth/audio/cap_commander/src/test_micp.c b/tests/bluetooth/audio/cap_commander/src/test_micp.c new file mode 100644 index 00000000000..4d3958d0e44 --- /dev/null +++ b/tests/bluetooth/audio/cap_commander/src/test_micp.c @@ -0,0 +1,293 @@ +/* test_micp.c - unit test for microphone settings */ + +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include + +#include "bluetooth.h" +#include "cap_commander.h" +#include "conn.h" +#include "expects_util.h" +#include "cap_mocks.h" +#include "test_common.h" + +#define FFF_GLOBALS + +struct cap_commander_test_micp_fixture { + struct bt_conn conns[CONFIG_BT_MAX_CONN]; +}; + +static void cap_commander_test_micp_fixture_init(struct cap_commander_test_micp_fixture *fixture) +{ + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + test_conn_init(&fixture->conns[i]); + } +} + +static void *cap_commander_test_micp_setup(void) +{ + struct cap_commander_test_micp_fixture *fixture; + + fixture = malloc(sizeof(*fixture)); + zassert_not_null(fixture); + + return fixture; +} + +static void cap_commander_test_micp_before(void *f) +{ + memset(f, 0, sizeof(struct cap_commander_test_micp_fixture)); + cap_commander_test_micp_fixture_init(f); +} + +static void cap_commander_test_micp_after(void *f) +{ + struct cap_commander_test_micp_fixture *fixture = f; + + bt_cap_commander_unregister_cb(&mock_cap_commander_cb); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + mock_bt_conn_disconnected(&fixture->conns[i], BT_HCI_ERR_REMOTE_USER_TERM_CONN); + } +} + +static void cap_commander_test_micp_teardown(void *f) +{ + free(f); +} + +ZTEST_SUITE(cap_commander_test_micp, NULL, cap_commander_test_micp_setup, + cap_commander_test_micp_before, cap_commander_test_micp_after, + cap_commander_test_micp_teardown); + + +ZTEST_F(cap_commander_test_micp, test_commander_change_microphone_gain_setting) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.microphone_gain_setting_changed", 1, + mock_cap_commander_microphone_gain_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_micp, test_commander_change_microphone_gain_setting_double) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.microphone_gain_setting_changed", 1, + mock_cap_commander_microphone_gain_changed_cb_fake.call_count); + + /* That that it still works as expected if we set the same value twice */ + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.microphone_gain_setting_changed", 2, + mock_cap_commander_microphone_gain_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_micp, test_commander_change_microphone_gain_setting_inval_param_null) +{ + int err; + + err = bt_cap_commander_change_microphone_gain_setting(NULL); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, + test_commander_change_microphone_gain_setting_inval_param_null_param) +{ + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = NULL, + .count = ARRAY_SIZE(fixture->conns), + }; + int err; + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, + test_commander_change_microphone_gain_setting_inval_param_null_member) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + member_params[ARRAY_SIZE(member_params) - 1].member.member = NULL; + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, test_commander_change_microphone_gain_setting_inval_missing_cas) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_micp_mic_ctlr *mic_ctlr; /* We don't care about this */ + + err = bt_micp_mic_ctlr_discover(&fixture->conns[i], &mic_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, test_commander_change_microphone_gain_setting_inval_missing_aics) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, + test_commander_change_microphone_gain_setting_inval_param_zero_count) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = 0U, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_micp, + test_commander_change_microphone_gain_setting_inval_param_inval_count) +{ + struct bt_cap_commander_change_microphone_gain_setting_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_microphone_gain_setting_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = CONFIG_BT_MAX_CONN + 1, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].gain = 10 + i; + } + + err = bt_cap_commander_change_microphone_gain_setting(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} diff --git a/tests/bluetooth/audio/cap_commander/src/test_vcp.c b/tests/bluetooth/audio/cap_commander/src/test_vcp.c new file mode 100644 index 00000000000..5d2773908d4 --- /dev/null +++ b/tests/bluetooth/audio/cap_commander/src/test_vcp.c @@ -0,0 +1,753 @@ +/* test_vcp.c - unit test for volume settings */ + +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include + +#include "bluetooth.h" +#include "cap_commander.h" +#include "conn.h" +#include "expects_util.h" +#include "cap_mocks.h" +#include "test_common.h" + +#define FFF_GLOBALS + +struct cap_commander_test_vcp_fixture { + struct bt_conn conns[CONFIG_BT_MAX_CONN]; +}; + +static void cap_commander_test_vcp_fixture_init(struct cap_commander_test_vcp_fixture *fixture) +{ + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + test_conn_init(&fixture->conns[i]); + } +} + +static void *cap_commander_test_vcp_setup(void) +{ + struct cap_commander_test_vcp_fixture *fixture; + + fixture = malloc(sizeof(*fixture)); + zassert_not_null(fixture); + + return fixture; +} + +static void cap_commander_test_vcp_before(void *f) +{ + memset(f, 0, sizeof(struct cap_commander_test_vcp_fixture)); + cap_commander_test_vcp_fixture_init(f); +} + +static void cap_commander_test_vcp_after(void *f) +{ + struct cap_commander_test_vcp_fixture *fixture = f; + + bt_cap_commander_unregister_cb(&mock_cap_commander_cb); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + mock_bt_conn_disconnected(&fixture->conns[i], BT_HCI_ERR_REMOTE_USER_TERM_CONN); + } +} + +static void cap_commander_test_vcp_teardown(void *f) +{ + free(f); +} + +ZTEST_SUITE(cap_commander_test_vcp, NULL, cap_commander_test_vcp_setup, + cap_commander_test_vcp_before, cap_commander_test_vcp_after, + cap_commander_test_vcp_teardown); + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .volume = 177, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.volume_changed", 1, + mock_cap_commander_volume_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_double) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .volume = 177, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.volume_changed", 1, + mock_cap_commander_volume_changed_cb_fake.call_count); + + /* Verify that it still works as expected if we set the same value twice */ + err = bt_cap_commander_change_volume(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.volume_changed", 2, + mock_cap_commander_volume_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_inval_param_null) +{ + int err; + + err = bt_cap_commander_change_volume(NULL); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_inval_param_null_members) +{ + const struct bt_cap_commander_change_volume_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = NULL, + .count = ARRAY_SIZE(fixture->conns), + .volume = 177, + }; + int err; + + err = bt_cap_commander_change_volume(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_inval_param_null_member) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .volume = 177, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members) - 1; i++) { + members[i].member = &fixture->conns[i]; + } + members[ARRAY_SIZE(members) - 1].member = NULL; + + err = bt_cap_commander_change_volume(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_inval_missing_cas) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .volume = 177, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ + + err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_inval_missing_vcs) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .volume = 177, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_inval_param_zero_count) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = 0U, + .volume = 177, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_change_volume(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_inval_param_inval_count) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = CONFIG_BT_MAX_CONN + 1, + .volume = 177, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_change_volume(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_offset) +{ + struct bt_cap_commander_change_volume_offset_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_offset_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].offset = 100 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume_offset(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.volume_offset_changed", 1, + mock_cap_commander_volume_offset_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_offset_double) +{ + struct bt_cap_commander_change_volume_offset_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_offset_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].offset = 100 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume_offset(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.volume_offset_changed", 1, + mock_cap_commander_volume_offset_changed_cb_fake.call_count); + + /* Verify that it still works as expected if we set the same value twice */ + err = bt_cap_commander_change_volume_offset(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.volume_offset_changed", 2, + mock_cap_commander_volume_offset_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_offset_inval_param_null) +{ + int err; + + err = bt_cap_commander_change_volume_offset(NULL); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_offset_inval_param_null_param) +{ + const struct bt_cap_commander_change_volume_offset_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = NULL, + .count = ARRAY_SIZE(fixture->conns), + }; + int err; + + err = bt_cap_commander_change_volume_offset(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_offset_inval_param_null_member) +{ + struct bt_cap_commander_change_volume_offset_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_offset_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].offset = 100 + i; + } + member_params[ARRAY_SIZE(member_params) - 1].member.member = NULL; + + err = bt_cap_commander_change_volume_offset(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_offset_inval_missing_cas) +{ + struct bt_cap_commander_change_volume_offset_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_offset_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].offset = 100 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ + + err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume_offset(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_offset_inval_missing_vocs) +{ + struct bt_cap_commander_change_volume_offset_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_offset_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].offset = 100 + i; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume_offset(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_offset_inval_param_zero_count) +{ + struct bt_cap_commander_change_volume_offset_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_offset_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = 0U, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].offset = 100 + i; + } + + err = bt_cap_commander_change_volume_offset(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_offset_inval_param_inval_count) +{ + struct bt_cap_commander_change_volume_offset_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_offset_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = CONFIG_BT_MAX_CONN + 1, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].offset = 100 + i; + } + + err = bt_cap_commander_change_volume_offset(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_offset_inval_param_inval_offset_max) +{ + struct bt_cap_commander_change_volume_offset_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_offset_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].offset = BT_VOCS_MAX_OFFSET + 1; + } + + err = bt_cap_commander_change_volume_offset(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_offset_inval_param_inval_offset_min) +{ + struct bt_cap_commander_change_volume_offset_member_param + member_params[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_offset_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .param = member_params, + .count = ARRAY_SIZE(member_params), + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(member_params); i++) { + member_params[i].member.member = &fixture->conns[i]; + member_params[i].offset = BT_VOCS_MIN_OFFSET - 1; + } + + err = bt_cap_commander_change_volume_offset(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_mute_state) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume_mute_state(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.volume_mute_changed", 1, + mock_cap_commander_volume_mute_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_mute_state_double) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ + + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + + err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume_mute_state(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.volume_mute_changed", 1, + mock_cap_commander_volume_mute_changed_cb_fake.call_count); + + /* Verify that it still works as expected if we set the same value twice */ + err = bt_cap_commander_change_volume_mute_state(¶m); + zassert_equal(0, err, "Unexpected return value %d", err); + + zexpect_call_count("bt_cap_commander_cb.volume_mute_changed", 2, + mock_cap_commander_volume_mute_changed_cb_fake.call_count); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_mute_state_inval_param_null) +{ + int err; + + err = bt_cap_commander_change_volume_mute_state(NULL); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_mute_state_inval_param_null_members) +{ + const struct bt_cap_commander_change_volume_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = NULL, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + err = bt_cap_commander_change_volume_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_mute_state_inval_param_null_member) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members) - 1; i++) { + members[i].member = &fixture->conns[i]; + } + members[ARRAY_SIZE(members) - 1].member = NULL; + + err = bt_cap_commander_change_volume_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_mute_state_inval_missing_cas) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + struct bt_vcp_vol_ctlr *vol_ctlr; /* We don't care about this */ + + err = bt_vcp_vol_ctlr_discover(&fixture->conns[i], &vol_ctlr); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_mute_state_inval_missing_vcs) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = ARRAY_SIZE(fixture->conns), + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_register_cb(&mock_cap_commander_cb); + zassert_equal(0, err, "Unexpected return value %d", err); + + for (size_t i = 0; i < ARRAY_SIZE(fixture->conns); i++) { + err = bt_cap_commander_discover(&fixture->conns[i]); + zassert_equal(0, err, "Unexpected return value %d", err); + } + + err = bt_cap_commander_change_volume_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_mute_state_inval_param_zero_count) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = 0U, + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_change_volume_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} + +ZTEST_F(cap_commander_test_vcp, test_commander_change_volume_mute_state_inval_param_inval_count) +{ + union bt_cap_set_member members[ARRAY_SIZE(fixture->conns)]; + const struct bt_cap_commander_change_volume_mute_state_param param = { + .type = BT_CAP_SET_TYPE_AD_HOC, + .members = members, + .count = CONFIG_BT_MAX_CONN + 1, + .mute = true, + }; + int err; + + for (size_t i = 0U; i < ARRAY_SIZE(members); i++) { + members[i].member = &fixture->conns[i]; + } + + err = bt_cap_commander_change_volume_mute_state(¶m); + zassert_equal(-EINVAL, err, "Unexpected return value %d", err); +} From b5a15c980f07f457d3114ec21352ad83bb00018e Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Sat, 23 Mar 2024 08:57:57 -0400 Subject: [PATCH 1361/2402] doc: posix: remove unneeded notes about XSI_THREADS_EXT Previously, XSI_THREADS_EXT included a note about undefined behaviour. However, the required functions pthread_attr_getstack(), pthread_attr_setstack(), pthread_getconcurrency(), and pthread_setconcurrency() are all conformant. Remove the unneeded note (all of them) Signed-off-by: Chris Friedt --- doc/services/portability/posix/aep/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/services/portability/posix/aep/index.rst b/doc/services/portability/posix/aep/index.rst index f8e6aa09a98..c532c2a059b 100644 --- a/doc/services/portability/posix/aep/index.rst +++ b/doc/services/portability/posix/aep/index.rst @@ -84,7 +84,7 @@ Realtime Controller System Profile (PSE52) POSIX_SIGNALS,, :ref:`†` POSIX_SINGLE_PROCESS, yes, POSIX_THREADS_BASE, yes, :ref:`†` - XSI_THREADS_EXT, yes, :ref:`†` + XSI_THREADS_EXT, yes, .. csv-table:: PSE52 Option Requirements :header: Symbol, Support, Remarks @@ -145,7 +145,7 @@ Dedicated Realtime System Profile (PSE53) POSIX_SIGNAL_JUMP,, :ref:`†` POSIX_SINGLE_PROCESS, yes, POSIX_THREADS_BASE, yes, :ref:`†` - XSI_THREADS_EXT, yes, :ref:`†` + XSI_THREADS_EXT, yes, .. csv-table:: PSE53 Option Requirements :header: Symbol, Support, Remarks From edc969cbb05a937997e32ccdc3a63dae708e3848 Mon Sep 17 00:00:00 2001 From: Maximilian Deubel Date: Tue, 27 Feb 2024 12:21:12 +0100 Subject: [PATCH 1362/2402] boards: arm: nrf9151dk: fix broken link This patch fixes a broken link in the docs for the nrf9151dk. It points to the SiP's product page for now. Signed-off-by: Maximilian Deubel --- boards/nordic/nrf9151dk/doc/index.rst | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/boards/nordic/nrf9151dk/doc/index.rst b/boards/nordic/nrf9151dk/doc/index.rst index a3a56f632c6..40979cc9089 100644 --- a/boards/nordic/nrf9151dk/doc/index.rst +++ b/boards/nordic/nrf9151dk/doc/index.rst @@ -26,9 +26,7 @@ Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: * :abbr:`WDT (Watchdog Timer)` * :abbr:`IDAU (Implementation Defined Attribution Unit)` -More information about the board can be found at the -`nRF9151 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. +More information about the board can be found at the `nRF9151 website`_. Hardware @@ -84,8 +82,7 @@ hardware features: .. _nrf9151dk_additional_hardware: Other hardware features have not been enabled yet for this board. -See `nRF9151 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF9151 DK board hardware features. +See the `nRF9151 website`_ for more information. Connections and IOs =================== @@ -198,6 +195,6 @@ References .. _IDAU: https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _nRF9151 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9151-DK +.. _nRF9151 website: https://www.nordicsemi.com/Products/nRF9151 .. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com .. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ From 5a49b7c90d8780e2a145b4cddab04f35b1d6c21a Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Mon, 25 Mar 2024 22:43:58 +0100 Subject: [PATCH 1363/2402] doc: releases: Fix GH link in migration guide v3.6 Putting a space between :github: and the PR number causes the rendered text to not link to the issue. Signed-off-by: Reto Schneider --- doc/releases/migration-guide-3.6.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/releases/migration-guide-3.6.rst b/doc/releases/migration-guide-3.6.rst index 8d8a2ac21c3..ffe93262cff 100644 --- a/doc/releases/migration-guide-3.6.rst +++ b/doc/releases/migration-guide-3.6.rst @@ -638,7 +638,7 @@ Shell * :kconfig:option:`CONFIG_SHELL_BACKEND_SERIAL_API` now does not automatically default to :kconfig:option:`CONFIG_SHELL_BACKEND_SERIAL_API_ASYNC` when :kconfig:option:`CONFIG_UART_ASYNC_API` is enabled, :kconfig:option:`CONFIG_SHELL_ASYNC_API` - also has to be enabled in order to use the asynchronous serial shell (:github: `68475`). + also has to be enabled in order to use the asynchronous serial shell (:github:`68475`). ZBus ==== From 7058c2283f06f6eb23ce5dde2dd019b14261bd84 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Wed, 20 Mar 2024 12:20:06 +0800 Subject: [PATCH 1364/2402] twister: unify test scenario path to backslash Winodws user may use the `\` as path, but in twister we use the common `/` as path separated, to avoid the mis-use, convert it to `/` in twister first normpath, and then replace the os.sep tested by: For Linux Like: west twister -p disco_l475_iot1 -s samples/hello_world/... For Windows: west twister -p disco_l475_iot1 -s samples\hello_world\... fixing: #70310 Signed-off-by: Hake Huang --- scripts/pylib/twister/twisterlib/environment.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/environment.py b/scripts/pylib/twister/twisterlib/environment.py index 86770eb4bf8..adf31a4e499 100644 --- a/scripts/pylib/twister/twisterlib/environment.py +++ b/scripts/pylib/twister/twisterlib/environment.py @@ -43,6 +43,9 @@ installed_packages = [pkg.project_name for pkg in pkg_resources.working_set] # pylint: disable=not-an-iterable PYTEST_PLUGIN_INSTALLED = 'pytest-twister-harness' in installed_packages +def norm_path(astring): + newstring = os.path.normpath(astring).replace(os.sep, '/') + return newstring def add_parse_arguments(parser = None): if parser is None: @@ -96,7 +99,7 @@ def add_parse_arguments(parser = None): help="Load a list of tests and platforms to be run from file.") case_select.add_argument( - "-T", "--testsuite-root", action="append", default=[], + "-T", "--testsuite-root", action="append", default=[], type = norm_path, help="Base directory to recursively search for test cases. All " "testcase.yaml files under here will be processed. May be " "called multiple times. Defaults to the 'samples/' and " @@ -209,7 +212,7 @@ def add_parse_arguments(parser = None): and global timeout multiplier (this parameter)""") test_xor_subtest.add_argument( - "-s", "--test", "--scenario", action="append", + "-s", "--test", "--scenario", action="append", type = norm_path, help="Run only the specified testsuite scenario. These are named by " "") From 98aa10d6eab8df6938c0dc949bd12bc244bb52e1 Mon Sep 17 00:00:00 2001 From: Kevin ORourke Date: Wed, 28 Feb 2024 14:30:03 +0100 Subject: [PATCH 1365/2402] scripts: coredump: coredump_gdbserver in pipeline Add support to coredump_gdbserver.py for running in a pipeline, communicating through stdin/stdout instead of a socket. This allows starting it from inside gdb, with: target remote | coredump_gdbserver.py --pipe Signed-off-by: Kevin ORourke --- doc/services/debugging/coredump.rst | 22 +++++++++++++- scripts/coredump/coredump_gdbserver.py | 41 ++++++++++++++++++++------ 2 files changed, 53 insertions(+), 10 deletions(-) diff --git a/doc/services/debugging/coredump.rst b/doc/services/debugging/coredump.rst index ed7bb34f51e..ed3e233d3b3 100644 --- a/doc/services/debugging/coredump.rst +++ b/doc/services/debugging/coredump.rst @@ -55,7 +55,8 @@ This usually involves the following steps: 3. Start the custom GDB server using the script :zephyr_file:`scripts/coredump/coredump_gdbserver.py` with the core dump - binary log file, and the Zephyr ELF file as parameters. + binary log file, and the Zephyr ELF file as parameters. The GDB server + can also be started from within GDB, see below. 4. Start the debugger corresponding to the target architecture. @@ -220,6 +221,25 @@ in :file:`coredump.log`: #2 0x00100492 in func_1 (addr=0x0) at zephyr/rtos/zephyr/samples/hello_world/src/main.c:28 #3 0x001004c8 in main () at zephyr/rtos/zephyr/samples/hello_world/src/main.c:42 +Starting the GDB server from within GDB +--------------------------------------- + +You can use ``target remote |`` to start the custom GDB server from inside +GDB, instead of in a separate shell. + +1. Start GDB: + + .. code-block:: console + + /x86_64-zephyr-elf/bin/x86_64-zephyr-elf-gdb build/zephyr/zephyr.elf + +2. Inside GDB, start the GDB server using the ``--pipe`` option: + + .. code-block:: console + + (gdb) target remote | ./scripts/coredump/coredump_gdbserver.py --pipe build/zephyr/zephyr.elf coredump.bin + + File Format *********** diff --git a/scripts/coredump/coredump_gdbserver.py b/scripts/coredump/coredump_gdbserver.py index f53e71b7362..3ffe3d9cfb9 100755 --- a/scripts/coredump/coredump_gdbserver.py +++ b/scripts/coredump/coredump_gdbserver.py @@ -21,6 +21,23 @@ GDBSERVER_HOST = "" +class FakeSocket: + def __init__(self) -> None: + self.in_stream = sys.stdin.buffer + self.out_stream = sys.stdout.buffer + + def recv(self, bufsize): + return self.in_stream.read(bufsize) + + def send(self, data): + n = self.out_stream.write(data) + self.out_stream.flush() + return n + + def close(self): + pass + + def parse_args(): parser = argparse.ArgumentParser(allow_abbrev=False) @@ -30,6 +47,8 @@ def parse_args(): help="Print extra debugging information") parser.add_argument("--port", type=int, default=1234, help="GDB server port") + parser.add_argument("--pipe", action="store_true", + help="Use stdio to communicate with gdb") parser.add_argument("-v", "--verbose", action="store_true", help="Print more information") @@ -99,19 +118,23 @@ def main(): gdbstub = gdbstubs.get_gdbstub(logf, elff) - # Start a GDB server - gdbserver = socket.socket(socket.AF_INET, socket.SOCK_STREAM) + if not args.pipe: + # Start a GDB server + gdbserver = socket.socket(socket.AF_INET, socket.SOCK_STREAM) - # Reuse address so we don't have to wait for socket to be - # close before we can bind to the port again - gdbserver.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1) + # Reuse address so we don't have to wait for socket to be + # close before we can bind to the port again + gdbserver.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1) - gdbserver.bind((GDBSERVER_HOST, args.port)) - gdbserver.listen(1) + gdbserver.bind((GDBSERVER_HOST, args.port)) + gdbserver.listen(1) - logger.info(f"Waiting GDB connection on port {args.port}...") + logger.info(f"Waiting GDB connection on port {args.port}...") - conn, remote = gdbserver.accept() + conn, remote = gdbserver.accept() + else: + conn = FakeSocket() + remote = "pipe" if conn: logger.info(f"Accepted GDB connection from {remote}") From e193f922cd099a1722384f1f17c76277804560de Mon Sep 17 00:00:00 2001 From: Dean Sellers Date: Thu, 21 Dec 2023 11:25:26 +1000 Subject: [PATCH 1366/2402] drivers: ethernet: enc28j60: Add DT property to set Rx filter Byte value written to the device's ERXFCON: ETHERNET RECEIVE FILTER CONTROL REGISTER Sets the devices receive packet filter, optional. If not set in device tree previous hard coded value`0xA3` is used. Uni, multi and broadcast packets with valid CRC are accepted. Signed-off-by: Dean Sellers --- drivers/ethernet/eth_enc28j60.c | 4 +++- drivers/ethernet/eth_enc28j60_priv.h | 4 ++++ dts/bindings/ethernet/microchip,enc28j60.yaml | 9 +++++++++ 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/ethernet/eth_enc28j60.c b/drivers/ethernet/eth_enc28j60.c index 502d0cc1199..d4b4f08fbc1 100644 --- a/drivers/ethernet/eth_enc28j60.c +++ b/drivers/ethernet/eth_enc28j60.c @@ -338,6 +338,7 @@ static void eth_enc28j60_gpio_callback(const struct device *dev, static int eth_enc28j60_init_buffers(const struct device *dev) { uint8_t data_estat; + const struct eth_enc28j60_config *config = dev->config; /* Reception buffers initialization */ eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXSTL); @@ -372,7 +373,7 @@ static int eth_enc28j60_init_buffers(const struct device *dev) eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXFCON); eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXFCON, - ENC28J60_RECEIVE_FILTERS); + config->hw_rx_filter); /* Waiting for OST */ /* 32 bits for this timer should be fine, rollover not an issue with initialisation */ @@ -877,6 +878,7 @@ static int eth_enc28j60_init(const struct device *dev) .interrupt = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \ .full_duplex = DT_INST_PROP(0, full_duplex), \ .timeout = CONFIG_ETH_ENC28J60_TIMEOUT, \ + .hw_rx_filter = DT_INST_PROP_OR(inst, hw_rx_filter, ENC28J60_RECEIVE_FILTERS), \ }; \ \ ETH_NET_DEVICE_DT_INST_DEFINE(inst, eth_enc28j60_init, NULL, ð_enc28j60_runtime_##inst, \ diff --git a/drivers/ethernet/eth_enc28j60_priv.h b/drivers/ethernet/eth_enc28j60_priv.h index 72275ac2abf..5b63ddabc9e 100644 --- a/drivers/ethernet/eth_enc28j60_priv.h +++ b/drivers/ethernet/eth_enc28j60_priv.h @@ -178,6 +178,9 @@ * - Multicast * - Broadcast * - CRC Check + * + * Used as default if hw-rx-filter property + * absent in DT */ #define ENC28J60_RECEIVE_FILTERS 0xA3 @@ -223,6 +226,7 @@ struct eth_enc28j60_config { struct gpio_dt_spec interrupt; uint8_t full_duplex; int32_t timeout; + uint8_t hw_rx_filter; }; struct eth_enc28j60_runtime { diff --git a/dts/bindings/ethernet/microchip,enc28j60.yaml b/dts/bindings/ethernet/microchip,enc28j60.yaml index f456b3c14fa..8c82d97e96a 100644 --- a/dts/bindings/ethernet/microchip,enc28j60.yaml +++ b/dts/bindings/ethernet/microchip,enc28j60.yaml @@ -21,3 +21,12 @@ properties: type: boolean description: | Optional feature flag - Enables full duplex reception and transmission. + + hw-rx-filter: + type: int + description: | + Byte value written to the device's + ERXFCON: ETHERNET RECEIVE FILTER CONTROL REGISTER + Sets the devices receive packet filter, optional + If not set in device tree `0xA3` is used, uni, multi and broadcast + packets with valid CRC are accepted. From 2ba0a33446175abdd2d912cfef2a9fc3aaab022e Mon Sep 17 00:00:00 2001 From: Attie Grande Date: Mon, 22 Jan 2024 22:34:51 +0000 Subject: [PATCH 1367/2402] bindesc: Add include zephyr/sys/util_macro.h Including `zephyr/bindesc.h` without `zephyr/sys/util_macro.h` already present will cause a compile error. As it's a reasonable expectation that this should work, this patch adds the missing include. Signed-off-by: Attie Grande --- include/zephyr/bindesc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/zephyr/bindesc.h b/include/zephyr/bindesc.h index 4280cf91d21..a45e69a2b9c 100644 --- a/include/zephyr/bindesc.h +++ b/include/zephyr/bindesc.h @@ -7,6 +7,8 @@ #ifndef ZEPHYR_INCLUDE_ZEPHYR_BINDESC_H_ #define ZEPHYR_INCLUDE_ZEPHYR_BINDESC_H_ +#include + #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ From 71c3c955c13d59190c8c8f5dcb29c18a6a268838 Mon Sep 17 00:00:00 2001 From: Jordan Yates Date: Thu, 22 Jun 2023 17:10:12 +1000 Subject: [PATCH 1368/2402] drivers: flash: spi_nor: use `pm_device_driver_init` Use `pm_device_driver_init` to ensure that init is run correctly regardless of the power state. Signed-off-by: Jordan Yates --- drivers/flash/spi_nor.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/flash/spi_nor.c b/drivers/flash/spi_nor.c index 3e29e06c3f6..39741df085f 100644 --- a/drivers/flash/spi_nor.c +++ b/drivers/flash/spi_nor.c @@ -1426,8 +1426,6 @@ static int spi_nor_configure(const struct device *dev) return 0; } -#ifdef CONFIG_PM_DEVICE - static int spi_nor_pm_control(const struct device *dev, enum pm_device_action action) { int rc = 0; @@ -1472,8 +1470,6 @@ static int spi_nor_pm_control(const struct device *dev, enum pm_device_action ac return rc; } -#endif /* CONFIG_PM_DEVICE */ - /** * @brief Initialize and configure the flash * @@ -1513,7 +1509,7 @@ static int spi_nor_init(const struct device *dev) } #endif /* ANY_INST_HAS_HOLD_GPIOS */ - return spi_nor_configure(dev); + return pm_device_driver_init(dev, spi_nor_pm_control); } #if defined(CONFIG_FLASH_PAGE_LAYOUT) From ce3d45375e820cb601af19b9222a880b7702a59f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Thu, 1 Feb 2024 10:48:06 +0100 Subject: [PATCH 1369/2402] drivers: serial: uart_async_rx: Remove unused field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Removing a field which was redundant. It was only incremented but never read. Signed-off-by: Krzysztof Chruściński --- drivers/serial/uart_async_rx.c | 1 - include/zephyr/drivers/serial/uart_async_rx.h | 3 --- 2 files changed, 4 deletions(-) diff --git a/drivers/serial/uart_async_rx.c b/drivers/serial/uart_async_rx.c index 68e17691c3e..92864880f4f 100644 --- a/drivers/serial/uart_async_rx.c +++ b/drivers/serial/uart_async_rx.c @@ -75,7 +75,6 @@ void uart_async_rx_on_buf_rel(struct uart_async_rx *rx_data, uint8_t *buffer) (struct uart_async_rx_buf *)(buffer - offsetof(struct uart_async_rx_buf, buffer)); rx_buf->completed = 1; - rx_data->wr_buf_idx = inc(rx_data, rx_data->wr_buf_idx); } size_t uart_async_rx_data_claim(struct uart_async_rx *rx_data, uint8_t **data, size_t length) diff --git a/include/zephyr/drivers/serial/uart_async_rx.h b/include/zephyr/drivers/serial/uart_async_rx.h index 646a2befc94..2131dfeb47c 100644 --- a/include/zephyr/drivers/serial/uart_async_rx.h +++ b/include/zephyr/drivers/serial/uart_async_rx.h @@ -54,9 +54,6 @@ struct uart_async_rx { /* Index of the next buffer to be provided to the driver. */ uint8_t drv_buf_idx; - /* Current buffer to which data is written. */ - uint8_t wr_buf_idx; - /* Current buffer from which data is being consumed. */ uint8_t rd_buf_idx; }; From 65b42260f74ed490bc2439a4904f87e4a6672338 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Thu, 1 Feb 2024 10:50:53 +0100 Subject: [PATCH 1370/2402] drivers: serial: uart_async_rx: Add buffer release to consuming function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add buffer releasing to consuming function to allow better buffer utilization since buffer is available earlier. Note that releasing in claiming function is still needed as there are cases when there are empty but completed buffers and those need to be consumed in claiming phase. Signed-off-by: Krzysztof Chruściński --- drivers/serial/uart_async_rx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/serial/uart_async_rx.c b/drivers/serial/uart_async_rx.c index 92864880f4f..70ee9c9b908 100644 --- a/drivers/serial/uart_async_rx.c +++ b/drivers/serial/uart_async_rx.c @@ -88,6 +88,9 @@ size_t uart_async_rx_data_claim(struct uart_async_rx *rx_data, uint8_t **data, s do { buf = get_buf(rx_data, rx_data->rd_buf_idx); + /* Even though buffer is released in consume phase it is possible that + * it is required here as well (e.g. was not completed previously). + */ if ((buf->rd_idx == buf->wr_idx) && (buf->completed == 1)) { usr_rx_buf_release(rx_data, buf); } else { @@ -106,6 +109,10 @@ void uart_async_rx_data_consume(struct uart_async_rx *rx_data, size_t length) struct uart_async_rx_buf *buf = get_buf(rx_data, rx_data->rd_buf_idx); buf->rd_idx += length; + /* Attempt to release the buffer if it is completed and all data is consumed. */ + if ((buf->rd_idx == buf->wr_idx) && (buf->completed == 1)) { + usr_rx_buf_release(rx_data, buf); + } atomic_sub(&rx_data->pending_bytes, length); From d2bd82eb5ff4b5248111d8019d29d3ba242bd551 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Thu, 1 Feb 2024 10:53:18 +0100 Subject: [PATCH 1371/2402] drivers: serial: uart_async_rx: Add return value to consume function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Return availability of free buffers after data is consumed. This information may be important for the module using uart_async_rx to schedule next reception if there is a new buffer available. Signed-off-by: Krzysztof Chruściński --- drivers/serial/uart_async_rx.c | 4 ++- drivers/serial/uart_async_to_irq.c | 27 ++++++++--------- include/zephyr/drivers/serial/uart_async_rx.h | 5 +++- subsys/shell/backends/shell_uart.c | 30 +++++++++---------- tests/drivers/uart/uart_async_rx/src/main.c | 19 +++++++----- 5 files changed, 45 insertions(+), 40 deletions(-) diff --git a/drivers/serial/uart_async_rx.c b/drivers/serial/uart_async_rx.c index 70ee9c9b908..a411539bb7a 100644 --- a/drivers/serial/uart_async_rx.c +++ b/drivers/serial/uart_async_rx.c @@ -104,7 +104,7 @@ size_t uart_async_rx_data_claim(struct uart_async_rx *rx_data, uint8_t **data, s return MIN(length, rem); } -void uart_async_rx_data_consume(struct uart_async_rx *rx_data, size_t length) +bool uart_async_rx_data_consume(struct uart_async_rx *rx_data, size_t length) { struct uart_async_rx_buf *buf = get_buf(rx_data, rx_data->rd_buf_idx); @@ -117,6 +117,8 @@ void uart_async_rx_data_consume(struct uart_async_rx *rx_data, size_t length) atomic_sub(&rx_data->pending_bytes, length); __ASSERT_NO_MSG(buf->rd_idx <= buf->wr_idx); + + return rx_data->free_buf_cnt > 0; } void uart_async_rx_reset(struct uart_async_rx *rx_data) diff --git a/drivers/serial/uart_async_to_irq.c b/drivers/serial/uart_async_to_irq.c index e18536449f3..59216cbc13d 100644 --- a/drivers/serial/uart_async_to_irq.c +++ b/drivers/serial/uart_async_to_irq.c @@ -198,24 +198,23 @@ int z_uart_async_to_irq_fifo_read(const struct device *dev, } memcpy(buf, claim_buf, claim_len); - uart_async_rx_data_consume(async_rx, claim_len); + bool buf_available = uart_async_rx_data_consume(async_rx, claim_len); - if (data->rx.pending_buf_req) { + if (data->rx.pending_buf_req && buf_available) { buf = uart_async_rx_buf_req(async_rx); - if (buf) { - int err; - size_t rx_len = uart_async_rx_get_buf_len(async_rx); + __ASSERT_NO_MSG(buf != NULL); + int err; + size_t rx_len = uart_async_rx_get_buf_len(async_rx); - atomic_dec(&data->rx.pending_buf_req); - err = config->api->rx_buf_rsp(dev, buf, rx_len); + atomic_dec(&data->rx.pending_buf_req); + err = config->api->rx_buf_rsp(dev, buf, rx_len); + if (err < 0) { + if (err == -EACCES) { + data->rx.pending_buf_req = 0; + err = rx_enable(dev, data, buf, rx_len); + } if (err < 0) { - if (err == -EACCES) { - data->rx.pending_buf_req = 0; - err = rx_enable(dev, data, buf, rx_len); - } - if (err < 0) { - return err; - } + return err; } } } diff --git a/include/zephyr/drivers/serial/uart_async_rx.h b/include/zephyr/drivers/serial/uart_async_rx.h index 2131dfeb47c..14e82f4905e 100644 --- a/include/zephyr/drivers/serial/uart_async_rx.h +++ b/include/zephyr/drivers/serial/uart_async_rx.h @@ -163,8 +163,11 @@ size_t uart_async_rx_data_claim(struct uart_async_rx *async_rx, uint8_t **data, * * @param async_rx Pointer to the helper instance. * @param length Amount of data to consume. It must be less or equal than amount of claimed data. + * + * @retval true If there are free buffers in the pool after data got consumed. + * @retval false If there are no free buffers. */ -void uart_async_rx_data_consume(struct uart_async_rx *async_rx, size_t length); +bool uart_async_rx_data_consume(struct uart_async_rx *async_rx, size_t length); #ifdef __cplusplus } diff --git a/subsys/shell/backends/shell_uart.c b/subsys/shell/backends/shell_uart.c index e11eebc7850..e80317664b9 100644 --- a/subsys/shell/backends/shell_uart.c +++ b/subsys/shell/backends/shell_uart.c @@ -454,26 +454,24 @@ static int async_read(struct shell_uart_async *sh_uart, memcpy(data, buf, blen); #endif - uart_async_rx_data_consume(async_rx, sh_cnt); + bool buf_available = uart_async_rx_data_consume(async_rx, sh_cnt); *cnt = sh_cnt; - if (sh_uart->pending_rx_req) { + if (sh_uart->pending_rx_req && buf_available) { uint8_t *buf = uart_async_rx_buf_req(async_rx); + size_t len = uart_async_rx_get_buf_len(async_rx); + int err; - if (buf) { - int err; - size_t len = uart_async_rx_get_buf_len(async_rx); - - atomic_dec(&sh_uart->pending_rx_req); - err = uart_rx_buf_rsp(sh_uart->common.dev, buf, len); - /* If it is too late and RX is disabled then re-enable it. */ - if (err < 0) { - if (err == -EACCES) { - sh_uart->pending_rx_req = 0; - err = rx_enable(sh_uart->common.dev, buf, len); - } else { - return err; - } + __ASSERT_NO_MSG(buf != NULL); + atomic_dec(&sh_uart->pending_rx_req); + err = uart_rx_buf_rsp(sh_uart->common.dev, buf, len); + /* If it is too late and RX is disabled then re-enable it. */ + if (err < 0) { + if (err == -EACCES) { + sh_uart->pending_rx_req = 0; + err = rx_enable(sh_uart->common.dev, buf, len); + } else { + return err; } } } diff --git a/tests/drivers/uart/uart_async_rx/src/main.c b/tests/drivers/uart/uart_async_rx/src/main.c index d95c6a69066..624c023bb63 100644 --- a/tests/drivers/uart/uart_async_rx/src/main.c +++ b/tests/drivers/uart/uart_async_rx/src/main.c @@ -41,6 +41,7 @@ ZTEST(uart_async_rx, test_rx) uint8_t *claim_buf; uint8_t *aloc_buf; struct uart_async_rx async_rx; + bool buf_available; const struct uart_async_rx_config config = { .buffer = buf, .length = sizeof(buf), @@ -87,7 +88,8 @@ ZTEST(uart_async_rx, test_rx) zassert_true(mem_check(claim_buf, 0, aloc_len - 2)); /* Consume first 2 bytes. */ - uart_async_rx_data_consume(&async_rx, 2); + buf_available = uart_async_rx_data_consume(&async_rx, 2); + zassert_true(buf_available); /* Now claim will return buffer taking into account that first 2 bytes are * consumed. @@ -98,7 +100,8 @@ ZTEST(uart_async_rx, test_rx) zassert_true(mem_check(claim_buf, 2, aloc_len - 4)); /* Consume rest of data. Get indication that it was end of the buffer. */ - uart_async_rx_data_consume(&async_rx, aloc_len - 4); + buf_available = uart_async_rx_data_consume(&async_rx, aloc_len - 4); + zassert_true(buf_available); } ZTEST(uart_async_rx, test_rx_late_consume) @@ -134,7 +137,7 @@ ZTEST(uart_async_rx, test_rx_late_consume) zassert_equal(claim_len, 1); zassert_equal(claim_buf[0], (uint8_t)i); - uart_async_rx_data_consume(&async_rx, 1); + (void)uart_async_rx_data_consume(&async_rx, 1); } claim_len = uart_async_rx_data_claim(&async_rx, &claim_buf, 100); @@ -217,13 +220,13 @@ static bool consumer(void *user_data, uint32_t cnt, bool last, int prio) test_data->exp_consume++; } - uart_async_rx_data_consume(async_rx, len); + bool buf_released = uart_async_rx_data_consume(async_rx, len); - if (test_data->pending_req) { + if (buf_released && test_data->pending_req) { buf = uart_async_rx_buf_req(async_rx); - if (buf) { - atomic_dec(&test_data->pending_req); - } + zassert_true(buf != NULL); + + atomic_dec(&test_data->pending_req); k_spinlock_key_t key = k_spin_lock(&test_data->lock); if (test_data->curr_buf == NULL) { From 17dc3da35d5ea692e015533bd4dd7a5dec6b35b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 12 Feb 2024 11:18:10 +0100 Subject: [PATCH 1372/2402] drivers: serial: uart_async_rx: Fix race condition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There was a wrong order of conditions checking. First indexes were compared and then completed flag was checked. It was possible that after checking first condition context is preempted and new data is written to the buffer and completed flag is set. In that case both conditions are met but data added in preemption is dropped. In order to avoid that completed flag must be checked first. Signed-off-by: Krzysztof Chruściński --- drivers/serial/uart_async_rx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/serial/uart_async_rx.c b/drivers/serial/uart_async_rx.c index a411539bb7a..8aadddd6bef 100644 --- a/drivers/serial/uart_async_rx.c +++ b/drivers/serial/uart_async_rx.c @@ -91,7 +91,7 @@ size_t uart_async_rx_data_claim(struct uart_async_rx *rx_data, uint8_t **data, s /* Even though buffer is released in consume phase it is possible that * it is required here as well (e.g. was not completed previously). */ - if ((buf->rd_idx == buf->wr_idx) && (buf->completed == 1)) { + if ((buf->completed == 1) && (rx_data->rd_idx == buf->wr_idx)) { usr_rx_buf_release(rx_data, buf); } else { break; @@ -110,7 +110,7 @@ bool uart_async_rx_data_consume(struct uart_async_rx *rx_data, size_t length) buf->rd_idx += length; /* Attempt to release the buffer if it is completed and all data is consumed. */ - if ((buf->rd_idx == buf->wr_idx) && (buf->completed == 1)) { + if ((buf->completed == 1) && (rx_data->rd_idx == buf->wr_idx)) { usr_rx_buf_release(rx_data, buf); } From 8bc5111c27df233520b6a94f5041f08fcd887fcb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 12 Feb 2024 11:21:22 +0100 Subject: [PATCH 1373/2402] drivers: serial: uart_async_rx: Optimize RAM usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since there is only one consumer of the data stored in the buffers, it is enough to have one read index variable which can be stored in the data associated with the module and not in the buffer space (where there is a read index for each buffer). Additionally, we can safely assume that module works with small buffers so 127 byte limit is enough. Based on that assumption completed flag can be stored on a single byte together with write index. After this change, control data for each buffer takes 1 byte (3 bytes previously). Signed-off-by: Krzysztof Chruściński --- drivers/serial/uart_async_rx.c | 16 +++++++++++----- include/zephyr/drivers/serial/uart_async_rx.h | 14 +++++++------- 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/serial/uart_async_rx.c b/drivers/serial/uart_async_rx.c index 8aadddd6bef..7c51a6cd251 100644 --- a/drivers/serial/uart_async_rx.c +++ b/drivers/serial/uart_async_rx.c @@ -54,13 +54,14 @@ void uart_async_rx_on_rdy(struct uart_async_rx *rx_data, uint8_t *buffer, size_t static void buf_reset(struct uart_async_rx_buf *buf) { - buf->rd_idx = 0; buf->wr_idx = 0; buf->completed = 0; } + static void usr_rx_buf_release(struct uart_async_rx *rx_data, struct uart_async_rx_buf *buf) { buf_reset(buf); + rx_data->rd_idx = 0; rx_data->rd_buf_idx = inc(rx_data, rx_data->rd_buf_idx); atomic_inc(&rx_data->free_buf_cnt); __ASSERT_NO_MSG(rx_data->free_buf_cnt <= rx_data->config->buf_cnt); @@ -98,8 +99,8 @@ size_t uart_async_rx_data_claim(struct uart_async_rx *rx_data, uint8_t **data, s } } while (1); - *data = &buf->buffer[buf->rd_idx]; - rem = buf->wr_idx - buf->rd_idx; + *data = &buf->buffer[rx_data->rd_idx]; + rem = buf->wr_idx - rx_data->rd_idx; return MIN(length, rem); } @@ -108,7 +109,7 @@ bool uart_async_rx_data_consume(struct uart_async_rx *rx_data, size_t length) { struct uart_async_rx_buf *buf = get_buf(rx_data, rx_data->rd_buf_idx); - buf->rd_idx += length; + rx_data->rd_idx += length; /* Attempt to release the buffer if it is completed and all data is consumed. */ if ((buf->completed == 1) && (rx_data->rd_idx == buf->wr_idx)) { usr_rx_buf_release(rx_data, buf); @@ -116,7 +117,7 @@ bool uart_async_rx_data_consume(struct uart_async_rx *rx_data, size_t length) atomic_sub(&rx_data->pending_bytes, length); - __ASSERT_NO_MSG(buf->rd_idx <= buf->wr_idx); + __ASSERT_NO_MSG(rx_data->rd_idx <= buf->wr_idx); return rx_data->free_buf_cnt > 0; } @@ -124,6 +125,7 @@ bool uart_async_rx_data_consume(struct uart_async_rx *rx_data, size_t length) void uart_async_rx_reset(struct uart_async_rx *rx_data) { rx_data->free_buf_cnt = rx_data->config->buf_cnt; + rx_data->rd_idx = 0; for (uint8_t i = 0; i < rx_data->config->buf_cnt; i++) { buf_reset(get_buf(rx_data, i)); } @@ -136,6 +138,10 @@ int uart_async_rx_init(struct uart_async_rx *rx_data, memset(rx_data, 0, sizeof(*rx_data)); rx_data->config = config; rx_data->buf_len = (config->length / config->buf_cnt) - UART_ASYNC_RX_BUF_OVERHEAD; + + if (rx_data->buf_len >= BIT(7)) { + return -EINVAL; + } uart_async_rx_reset(rx_data); return 0; diff --git a/include/zephyr/drivers/serial/uart_async_rx.h b/include/zephyr/drivers/serial/uart_async_rx.h index 14e82f4905e..4df46f36c51 100644 --- a/include/zephyr/drivers/serial/uart_async_rx.h +++ b/include/zephyr/drivers/serial/uart_async_rx.h @@ -23,15 +23,10 @@ struct uart_async_rx_buf { /* Write index which is incremented whenever new data is reported to be * received to that buffer. */ - uint8_t wr_idx; - - /* Read index which is incremented whenever data is consumed from the buffer. - * Read index cannot be higher than the write index. - */ - uint8_t rd_idx; + uint8_t wr_idx:7; /* Set to one if buffer is released by the driver. */ - uint8_t completed; + uint8_t completed:1; /* Location which is passed to the UART driver. */ uint8_t buffer[]; @@ -56,6 +51,11 @@ struct uart_async_rx { /* Current buffer from which data is being consumed. */ uint8_t rd_buf_idx; + + /* Current read index in the buffer from which data is being consumed. + * Read index which is incremented whenever data is consumed from the buffer. + */ + uint8_t rd_idx; }; /** @brief UART asynchronous RX helper configuration structure. */ From 3cad43605052542ddf56465a3694157b36152355 Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Thu, 1 Feb 2024 11:01:34 +0100 Subject: [PATCH 1374/2402] dts: bindings: add ap vendor prefix Add vendor prefix for Angst+Pfister. Signed-off-by: Jeppe Odgaard --- dts/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index c68773540b5..adb976f0851 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -58,6 +58,7 @@ analogix Analogix Semiconductor, Inc. andestech Andes Technology Corporation anvo Anvo-Systems Dresden GmbH aosong Guangzhou Aosong Electronic Co., Ltd. +ap Angst+Pfister apa Apa Electronic Co., Ltd apm Applied Micro Circuits Corporation (APM) apple Apple Inc. From 13e9e2209218b7d6adfa7360cb644bb7f406a2e3 Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Thu, 1 Feb 2024 11:10:36 +0100 Subject: [PATCH 1375/2402] dts: bindings: add fcx_mldx5 support Add bindings for the FCX-MLDx5 O2 sensor. Signed-off-by: Jeppe Odgaard --- dts/bindings/sensor/ap,fcx-mldx5.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 dts/bindings/sensor/ap,fcx-mldx5.yaml diff --git a/dts/bindings/sensor/ap,fcx-mldx5.yaml b/dts/bindings/sensor/ap,fcx-mldx5.yaml new file mode 100644 index 00000000000..8d094f12eb2 --- /dev/null +++ b/dts/bindings/sensor/ap,fcx-mldx5.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2024, Vitrolife A/S +# SPDX-License-Identifier: Apache-2.0 + +description: Angst+Pfister O2 sensor + +compatible: "ap,fcx-mldx5" + +include: [sensor-device.yaml, uart-device.yaml] From 29cc0e6aeded3e7da1ac55b6be7bc6ee1fb4cee6 Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Thu, 1 Feb 2024 19:10:18 +0100 Subject: [PATCH 1376/2402] sensor: add SENSOR_CHAN_O2 enum value Add an enum value to support O2 sensors. Signed-off-by: Jeppe Odgaard --- drivers/sensor/sensor_shell.c | 1 + include/zephyr/drivers/sensor.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/sensor/sensor_shell.c b/drivers/sensor/sensor_shell.c index b0485b8378a..758e658816a 100644 --- a/drivers/sensor/sensor_shell.c +++ b/drivers/sensor/sensor_shell.c @@ -74,6 +74,7 @@ static const char *sensor_channel_name[SENSOR_CHAN_COMMON_COUNT] = { [SENSOR_CHAN_PM_10] = "pm_10", [SENSOR_CHAN_DISTANCE] = "distance", [SENSOR_CHAN_CO2] = "co2", + [SENSOR_CHAN_O2] = "o2", [SENSOR_CHAN_VOC] = "voc", [SENSOR_CHAN_GAS_RES] = "gas_resistance", [SENSOR_CHAN_VOLTAGE] = "voltage", diff --git a/include/zephyr/drivers/sensor.h b/include/zephyr/drivers/sensor.h index 70972361097..f110a479896 100644 --- a/include/zephyr/drivers/sensor.h +++ b/include/zephyr/drivers/sensor.h @@ -120,6 +120,8 @@ enum sensor_channel { /** CO2 level, in parts per million (ppm) **/ SENSOR_CHAN_CO2, + /** O2 level, in parts per million (ppm) **/ + SENSOR_CHAN_O2, /** VOC level, in parts per billion (ppb) **/ SENSOR_CHAN_VOC, /** Gas sensor resistance in ohms. */ From 83957729dd80683d4dc7b6ec0870a6d174fd62c3 Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Thu, 1 Feb 2024 19:14:14 +0100 Subject: [PATCH 1377/2402] drivers: sensors: add fcx-mldx5 o2 sensor Add driver for Angst+Pfister O2 sensors FCX-MLD25 & FCX-MLD95 and maybe more. Tested with FCX-MLD25. Supports get O2 value, get status, and power management. Note that in suspended power mode heating output is at 20 %, thus probably not suited for a battery powered device. Signed-off-by: Jeppe Odgaard --- drivers/sensor/CMakeLists.txt | 1 + drivers/sensor/Kconfig | 1 + drivers/sensor/fcx_mldx5/CMakeLists.txt | 5 + drivers/sensor/fcx_mldx5/Kconfig | 13 + drivers/sensor/fcx_mldx5/fcx_mldx5.c | 495 ++++++++++++++++++++++ include/zephyr/drivers/sensor/fcx_mldx5.h | 34 ++ 6 files changed, 549 insertions(+) create mode 100644 drivers/sensor/fcx_mldx5/CMakeLists.txt create mode 100644 drivers/sensor/fcx_mldx5/Kconfig create mode 100644 drivers/sensor/fcx_mldx5/fcx_mldx5.c create mode 100644 include/zephyr/drivers/sensor/fcx_mldx5.h diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index c6725dbc3a2..15938bb6421 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -43,6 +43,7 @@ add_subdirectory_ifdef(CONFIG_ENS210 ens210) add_subdirectory_ifdef(CONFIG_ESP32_TEMP esp32_temp) add_subdirectory_ifdef(CONFIG_EXPLORIR_M explorir_m) add_subdirectory_ifdef(CONFIG_F75303 f75303) +add_subdirectory_ifdef(CONFIG_FCX_MLDX5 fcx_mldx5) add_subdirectory_ifdef(CONFIG_FDC2X1X fdc2x1x) add_subdirectory_ifdef(CONFIG_FXAS21002 fxas21002) add_subdirectory_ifdef(CONFIG_FXOS8700 fxos8700) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 594778be1d2..244c7d58be0 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -123,6 +123,7 @@ source "drivers/sensor/ens210/Kconfig" source "drivers/sensor/esp32_temp/Kconfig" source "drivers/sensor/explorir_m/Kconfig" source "drivers/sensor/f75303/Kconfig" +source "drivers/sensor/fcx_mldx5/Kconfig" source "drivers/sensor/fdc2x1x/Kconfig" source "drivers/sensor/fxas21002/Kconfig" source "drivers/sensor/fxos8700/Kconfig" diff --git a/drivers/sensor/fcx_mldx5/CMakeLists.txt b/drivers/sensor/fcx_mldx5/CMakeLists.txt new file mode 100644 index 00000000000..ca378984480 --- /dev/null +++ b/drivers/sensor/fcx_mldx5/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(fcx_mldx5.c) diff --git a/drivers/sensor/fcx_mldx5/Kconfig b/drivers/sensor/fcx_mldx5/Kconfig new file mode 100644 index 00000000000..b786f8b0dab --- /dev/null +++ b/drivers/sensor/fcx_mldx5/Kconfig @@ -0,0 +1,13 @@ +# FCX-MLDx5 O2 sensor configuration options + +# Copyright (c) 2024, Vitrolife A/S +# SPDX-License-Identifier: Apache-2.0 + +config FCX_MLDX5 + bool "FCX-MLDx5 O2 Sensor" + default y + depends on DT_HAS_AP_FCX_MLDX5_ENABLED + depends on UART_INTERRUPT_DRIVEN + select UART + help + Enable driver for FCX-MLD25 or FCX-MLD95 O2 Sensor. diff --git a/drivers/sensor/fcx_mldx5/fcx_mldx5.c b/drivers/sensor/fcx_mldx5/fcx_mldx5.c new file mode 100644 index 00000000000..c68bd372568 --- /dev/null +++ b/drivers/sensor/fcx_mldx5/fcx_mldx5.c @@ -0,0 +1,495 @@ +/* + * Copyright (c) 2024, Vitrolife A/S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Datasheet: + * https://sensorsandpower.angst-pfister.com/fileadmin/products/datasheets/272/Manual-FCX-MLD_1620-21914-0033-E-0821.pdf + * + */ + +#define DT_DRV_COMPAT ap_fcx_mldx5 +#include +#include +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(fcx_mldx5_sensor, CONFIG_SENSOR_LOG_LEVEL); + +#define FCX_MLDX5_STX 0x2 +#define FCX_MLDX5_ETX 0x3 + +#define FCX_MLDX5_STX_LEN 1 +#define FCX_MLDX5_CMD_LEN 2 +/* Data length depends on command type thus defined in array */ +#define FCX_MLDX5_CHECKSUM_LEN 2 +#define FCX_MLDX5_ETX_LEN 1 +#define FCX_MLDX5_HEADER_LEN \ + (FCX_MLDX5_STX_LEN + FCX_MLDX5_CMD_LEN + FCX_MLDX5_CHECKSUM_LEN + FCX_MLDX5_ETX_LEN) + +#define FCX_MLDX5_STX_INDEX 0 +#define FCX_MLDX5_CMD_INDEX (FCX_MLDX5_STX_INDEX + FCX_MLDX5_STX_LEN) +#define FCX_MLDX5_DATA_INDEX (FCX_MLDX5_CMD_INDEX + FCX_MLDX5_CMD_LEN) +#define FCX_MLDX5_CHECKSUM_INDEX(frame_len) ((frame_len)-FCX_MLDX5_CHECKSUM_LEN - FCX_MLDX5_ETX_LEN) +#define FCX_MLDX5_ETX_INDEX(frame_len) ((frame_len)-FCX_MLDX5_ETX_LEN) + +#define FCX_MLDX5_MAX_FRAME_LEN 11 +#define FCX_MLDX5_MAX_RESPONSE_DELAY 200 /* Not specified in datasheet */ +#define FCX_MLDX5_MAX_HEAT_UP_TIME 180000 + +struct fcx_mldx5_data { + struct k_mutex uart_mutex; + struct k_sem uart_rx_sem; + uint32_t o2_ppm; + uint8_t status; + uint8_t frame[FCX_MLDX5_MAX_FRAME_LEN]; + uint8_t frame_len; +}; + +struct fcx_mldx5_cfg { + const struct device *uart_dev; + uart_irq_callback_user_data_t cb; +}; + +enum fcx_mldx5_cmd { + FCX_MLDX5_CMD_READ_STATUS, + FCX_MLDX5_CMD_READ_O2_VALUE, + FCX_MLDX5_CMD_SWITCH_SENSOR_ON_OFF, + FCX_MLDX5_CMD_RESET, + FCX_MLDX5_CMD_ERROR, +}; + +enum fcx_mldx5_errors { + FCX_MLDX5_ERROR_CHECKSUM, + FCX_MLDX5_ERROR_UNKNOWN_COMMAND, + FCX_MLDX5_ERROR_PARAMETER, + FCX_MLDX5_ERROR_EEPROM, +}; + +static const char *const fcx_mldx5_cmds[] = { + [FCX_MLDX5_CMD_READ_STATUS] = "01", + [FCX_MLDX5_CMD_READ_O2_VALUE] = "02", + [FCX_MLDX5_CMD_SWITCH_SENSOR_ON_OFF] = "04", + [FCX_MLDX5_CMD_RESET] = "11", + [FCX_MLDX5_CMD_ERROR] = "EE", +}; + +static const uint8_t fcx_mldx5_cmds_data_len[] = { + [FCX_MLDX5_CMD_READ_STATUS] = 2, + [FCX_MLDX5_CMD_READ_O2_VALUE] = 5, + [FCX_MLDX5_CMD_SWITCH_SENSOR_ON_OFF] = 1, + [FCX_MLDX5_CMD_RESET] = 0, + [FCX_MLDX5_CMD_ERROR] = 2, +}; + +static const char *const fcx_mldx5_errors[] = { + [FCX_MLDX5_ERROR_CHECKSUM] = "checksum", + [FCX_MLDX5_ERROR_UNKNOWN_COMMAND] = "command", + [FCX_MLDX5_ERROR_PARAMETER] = "parameter", + [FCX_MLDX5_ERROR_EEPROM] = "eeprom", +}; + +static void fcx_mldx5_uart_flush(const struct device *uart_dev) +{ + uint8_t tmp; + + while (uart_fifo_read(uart_dev, &tmp, 1) > 0) { + continue; + } +} + +static uint8_t fcx_mldx5_calculate_checksum(const uint8_t *buf, size_t len) +{ + uint8_t checksum; + size_t i; + + if (buf == NULL || len == 0) { + return 0; + } + + checksum = buf[0]; + for (i = 1; i < len; ++i) { + checksum ^= buf[i]; + } + + return checksum; +} + +static int fcx_mldx5_frame_check_error(const struct fcx_mldx5_data *data, const char *command_sent) +{ + const uint8_t len = FCX_MLDX5_HEADER_LEN + fcx_mldx5_cmds_data_len[FCX_MLDX5_CMD_ERROR]; + const char *command_error = fcx_mldx5_cmds[FCX_MLDX5_CMD_ERROR]; + const char *command_received = &data->frame[FCX_MLDX5_CMD_INDEX]; + const char *data_received = &data->frame[FCX_MLDX5_DATA_INDEX]; + uint8_t error; + + if (data->frame_len != len || + strncmp(command_error, command_received, FCX_MLDX5_CMD_LEN) != 0) { + return 0; + } + + if (data_received[0] != 'E' || char2hex(data_received[1], &error) != 0 || + error >= ARRAY_SIZE(fcx_mldx5_errors)) { + LOG_ERR("Could not parse error value %.*s", + fcx_mldx5_cmds_data_len[FCX_MLDX5_CMD_ERROR], data_received); + } else { + LOG_ERR("Command '%s' received error '%s'", command_sent, fcx_mldx5_errors[error]); + } + + return -EIO; +} + +static int fcx_mldx5_frame_verify(const struct fcx_mldx5_data *data, enum fcx_mldx5_cmd cmd) +{ + const uint8_t frame_len = FCX_MLDX5_HEADER_LEN + fcx_mldx5_cmds_data_len[cmd]; + const char *command = fcx_mldx5_cmds[cmd]; + const char *command_received = &data->frame[FCX_MLDX5_CMD_INDEX]; + uint8_t checksum; + uint8_t checksum_received; + + if (fcx_mldx5_frame_check_error(data, command) != 0) { + return -EIO; + } else if (data->frame_len != frame_len) { + LOG_ERR("Expected command %s frame length %u not %u", command, frame_len, + data->frame_len); + return -EIO; + } else if (data->frame[FCX_MLDX5_STX_INDEX] != FCX_MLDX5_STX) { + LOG_ERR("No STX"); + return -EIO; + } else if (strncmp(command, command_received, FCX_MLDX5_CMD_LEN) != 0) { + LOG_ERR("Expected command %s not %.*s", command, FCX_MLDX5_CMD_LEN, + command_received); + return -EIO; + } else if (data->frame[FCX_MLDX5_ETX_INDEX(data->frame_len)] != FCX_MLDX5_ETX) { + LOG_ERR("No ETX"); + return -EIO; + } + + /* cmd and data bytes are used to calculate checksum */ + checksum = fcx_mldx5_calculate_checksum(command_received, + FCX_MLDX5_CMD_LEN + fcx_mldx5_cmds_data_len[cmd]); + checksum_received = + strtol(&data->frame[FCX_MLDX5_CHECKSUM_INDEX(data->frame_len)], NULL, 16); + if (checksum != checksum_received) { + LOG_ERR("Expected checksum 0x%02x not 0x%02x", checksum, checksum_received); + return -EIO; + } + + return 0; +} + +static void fcx_mldx5_uart_isr(const struct device *uart_dev, void *user_data) +{ + const struct device *dev = user_data; + struct fcx_mldx5_data *data = dev->data; + int rc, read_len; + + if (!device_is_ready(uart_dev)) { + LOG_DBG("UART device is not ready"); + return; + } + + if (!uart_irq_update(uart_dev)) { + LOG_DBG("Unable to process interrupts"); + return; + } + + if (!uart_irq_rx_ready(uart_dev)) { + LOG_DBG("No RX data"); + return; + } + + read_len = FCX_MLDX5_MAX_FRAME_LEN - data->frame_len; + rc = read_len > 0 ? uart_fifo_read(uart_dev, &data->frame[data->frame_len], read_len) + : -ENOMEM; + + if (rc < 0) { + LOG_ERR("UART read failed: %d", rc < 0 ? rc : -ERANGE); + fcx_mldx5_uart_flush(uart_dev); + LOG_HEXDUMP_ERR(data->frame, data->frame_len, "Discarding"); + } else { + data->frame_len += rc; + if (data->frame[FCX_MLDX5_ETX_INDEX(data->frame_len)] != FCX_MLDX5_ETX) { + return; + } + LOG_HEXDUMP_DBG(data->frame, data->frame_len, "Frame received"); + } + + k_sem_give(&data->uart_rx_sem); +} + +static void fcx_mldx5_uart_send(const struct device *dev, enum fcx_mldx5_cmd cmd, + const char *cmd_data) +{ + const struct fcx_mldx5_cfg *cfg = dev->config; + size_t cmd_data_len = cmd_data != NULL ? strlen(cmd_data) : 0; + size_t frame_len = FCX_MLDX5_HEADER_LEN + cmd_data_len; + char buf[FCX_MLDX5_MAX_FRAME_LEN]; + uint8_t checksum; + size_t i; + + buf[FCX_MLDX5_STX_INDEX] = FCX_MLDX5_STX; + memcpy(&buf[FCX_MLDX5_CMD_INDEX], fcx_mldx5_cmds[cmd], FCX_MLDX5_CMD_LEN); + if (cmd_data_len != 0) { + memcpy(&buf[FCX_MLDX5_DATA_INDEX], cmd_data, strlen(cmd_data)); + } + checksum = fcx_mldx5_calculate_checksum(&buf[FCX_MLDX5_CMD_INDEX], + FCX_MLDX5_CMD_LEN + cmd_data_len); + bin2hex(&checksum, 1, &buf[FCX_MLDX5_CHECKSUM_INDEX(frame_len)], + FCX_MLDX5_MAX_FRAME_LEN - FCX_MLDX5_CHECKSUM_INDEX(frame_len)); + buf[FCX_MLDX5_ETX_INDEX(frame_len)] = FCX_MLDX5_ETX; + + for (i = 0; i < frame_len; ++i) { + uart_poll_out(cfg->uart_dev, buf[i]); + } + + LOG_HEXDUMP_DBG(buf, frame_len, "Frame sent"); +} + +static int fcx_mldx5_await_receive(const struct device *dev) +{ + int rc; + const struct fcx_mldx5_cfg *cfg = dev->config; + struct fcx_mldx5_data *data = dev->data; + + uart_irq_rx_enable(cfg->uart_dev); + + rc = k_sem_take(&data->uart_rx_sem, K_MSEC(FCX_MLDX5_MAX_RESPONSE_DELAY)); + + /* Reset semaphore if sensor did not respond within maximum specified response time + */ + if (rc == -EAGAIN) { + k_sem_reset(&data->uart_rx_sem); + } + + uart_irq_rx_disable(cfg->uart_dev); + + return rc; +} + +static int fcx_mldx5_read_status_value(struct fcx_mldx5_data *data, uint8_t data_len) +{ + char *cmd_data_received = &data->frame[FCX_MLDX5_DATA_INDEX]; + uint8_t value; + + if (cmd_data_received[0] != '0' || char2hex(cmd_data_received[1], &value)) { + LOG_ERR("Could not parse status value %.*s", data_len, cmd_data_received); + return -EIO; + } + + switch (value) { + case FCX_MLDX5_STATUS_STANDBY: + break; + case FCX_MLDX5_STATUS_RAMP_UP: + break; + case FCX_MLDX5_STATUS_RUN: + break; + case FCX_MLDX5_STATUS_ERROR: + break; + default: + LOG_ERR("Status value %u invalid", value); + return -EIO; + } + + data->status = value; + return 0; +} + +static int fcx_mldx5_read_o2_value(struct fcx_mldx5_data *data) +{ + const char *o2_data = &data->frame[FCX_MLDX5_DATA_INDEX]; + uint8_t o2_data_len = fcx_mldx5_cmds_data_len[FCX_MLDX5_CMD_READ_O2_VALUE]; + uint32_t value = 0; + size_t i; + + for (i = 0; i < o2_data_len; ++i) { + if (i == 2) { + if (o2_data[i] != '.') { + goto invalid_data; + } + } else if (isdigit((int)o2_data[i]) == 0) { + goto invalid_data; + } else { + value = value * 10 + (o2_data[i] - '0'); + } + } + + data->o2_ppm = value * 100; + return 0; + +invalid_data: + LOG_HEXDUMP_ERR(o2_data, o2_data_len, "Invalid O2 data"); + return -EIO; +} + +static int fcx_mldx5_buffer_process(struct fcx_mldx5_data *data, enum fcx_mldx5_cmd cmd, + const char *cmd_data) +{ + if (fcx_mldx5_frame_verify(data, cmd) != 0) { + return -EIO; + } + + switch (cmd) { + case FCX_MLDX5_CMD_READ_STATUS: + return fcx_mldx5_read_status_value(data, fcx_mldx5_cmds_data_len[cmd]); + case FCX_MLDX5_CMD_READ_O2_VALUE: + return fcx_mldx5_read_o2_value(data); + case FCX_MLDX5_CMD_SWITCH_SENSOR_ON_OFF: + return cmd_data != NULL && data->frame[FCX_MLDX5_DATA_INDEX] == cmd_data[0]; + case FCX_MLDX5_CMD_RESET: + return 0; + default: + LOG_ERR("Unknown command 0x%02x", cmd); + return -EIO; + } +} + +static int fcx_mldx5_uart_transceive(const struct device *dev, enum fcx_mldx5_cmd cmd, + const char *cmd_data) +{ + struct fcx_mldx5_data *data = dev->data; + int rc; + + k_mutex_lock(&data->uart_mutex, K_FOREVER); + + data->frame_len = 0; + fcx_mldx5_uart_send(dev, cmd, cmd_data); + + rc = fcx_mldx5_await_receive(dev); + if (rc != 0) { + LOG_ERR("%s did not receive a response: %d", fcx_mldx5_cmds[cmd], rc); + } else { + rc = fcx_mldx5_buffer_process(data, cmd, cmd_data); + } + + k_mutex_unlock(&data->uart_mutex); + + return rc; +} + +static int fcx_mldx5_attr_get(const struct device *dev, enum sensor_channel chan, + enum sensor_attribute attr, struct sensor_value *val) +{ + struct fcx_mldx5_data *data = dev->data; + int rc; + + if (chan != SENSOR_CHAN_O2) { + return -ENOTSUP; + } + + switch (attr) { + case SENSOR_ATTR_FCX_MLDX5_STATUS: + rc = fcx_mldx5_uart_transceive(dev, FCX_MLDX5_CMD_READ_STATUS, NULL); + val->val1 = data->status; + return rc; + default: + return -ENOTSUP; + } +} + +static int fcx_mldx5_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + if (chan != SENSOR_CHAN_O2 && chan != SENSOR_CHAN_ALL) { + return -ENOTSUP; + } + + return fcx_mldx5_uart_transceive(dev, FCX_MLDX5_CMD_READ_O2_VALUE, NULL); +} + +static int fcx_mldx5_channel_get(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + struct fcx_mldx5_data *data = dev->data; + + if (chan != SENSOR_CHAN_O2) { + return -ENOTSUP; + } + + val->val1 = data->o2_ppm; + val->val2 = 0; + + return 0; +} + +static const struct sensor_driver_api fcx_mldx5_api_funcs = { + .attr_get = fcx_mldx5_attr_get, + .sample_fetch = fcx_mldx5_sample_fetch, + .channel_get = fcx_mldx5_channel_get, +}; + +#ifdef CONFIG_PM_DEVICE +static int pm_action(const struct device *dev, enum pm_device_action action) +{ + switch (action) { + case PM_DEVICE_ACTION_RESUME: + return fcx_mldx5_uart_transceive(dev, FCX_MLDX5_CMD_SWITCH_SENSOR_ON_OFF, "1"); + case PM_DEVICE_ACTION_SUSPEND: + /* Standby with 20 % heating output */ + return fcx_mldx5_uart_transceive(dev, FCX_MLDX5_CMD_SWITCH_SENSOR_ON_OFF, "0"); + default: + return -ENOTSUP; + } +} +#endif + +static int fcx_mldx5_init(const struct device *dev) +{ + int rc; + const struct fcx_mldx5_cfg *cfg = dev->config; + struct fcx_mldx5_data *data = dev->data; + + LOG_DBG("Initializing %s", dev->name); + + if (!device_is_ready(cfg->uart_dev)) { + return -ENODEV; + } + + k_mutex_init(&data->uart_mutex); + k_sem_init(&data->uart_rx_sem, 0, 1); + + uart_irq_rx_disable(cfg->uart_dev); + uart_irq_tx_disable(cfg->uart_dev); + + rc = uart_irq_callback_user_data_set(cfg->uart_dev, cfg->cb, (void *)dev); + if (rc != 0) { + LOG_ERR("UART IRQ setup failed: %d", rc); + return rc; + } + + /* Retry in case of garbled tx due to GPIO setup, crash during unfinished send or sensor + * start up time + */ + if (!WAIT_FOR(fcx_mldx5_uart_transceive(dev, FCX_MLDX5_CMD_READ_STATUS, NULL) == 0, + 1000 * USEC_PER_MSEC, k_msleep(10))) { + LOG_ERR("Read status failed"); + return -EIO; + } + + LOG_INF("%s status 0x%x", dev->name, data->status); + + return 0; +} + +#define FCX_MLDX5_INIT(n) \ + \ + static struct fcx_mldx5_data fcx_mldx5_data_##n = { \ + .status = FCX_MLDX5_STATUS_UNKNOWN, \ + }; \ + \ + static const struct fcx_mldx5_cfg fcx_mldx5_cfg_##n = { \ + .uart_dev = DEVICE_DT_GET(DT_INST_BUS(n)), \ + .cb = fcx_mldx5_uart_isr, \ + }; \ + \ + PM_DEVICE_DT_INST_DEFINE(n, pm_action); \ + \ + SENSOR_DEVICE_DT_INST_DEFINE(n, fcx_mldx5_init, PM_DEVICE_DT_INST_GET(n), \ + &fcx_mldx5_data_##n, &fcx_mldx5_cfg_##n, POST_KERNEL, \ + CONFIG_SENSOR_INIT_PRIORITY, &fcx_mldx5_api_funcs); + +DT_INST_FOREACH_STATUS_OKAY(FCX_MLDX5_INIT) diff --git a/include/zephyr/drivers/sensor/fcx_mldx5.h b/include/zephyr/drivers/sensor/fcx_mldx5.h new file mode 100644 index 00000000000..66e0d88aa25 --- /dev/null +++ b/include/zephyr/drivers/sensor/fcx_mldx5.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024, Vitrolife A/S + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_FCX_MLDX5_H_ +#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_FCX_MLDX5_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +enum sensor_attribute_fcx_mldx5 { + SENSOR_ATTR_FCX_MLDX5_STATUS = SENSOR_ATTR_PRIV_START, + SENSOR_ATTR_FCX_MLDX5_RESET, +}; + +enum fcx_mldx5_status { + FCX_MLDX5_STATUS_STANDBY = 2, + FCX_MLDX5_STATUS_RAMP_UP = 3, + FCX_MLDX5_STATUS_RUN = 4, + FCX_MLDX5_STATUS_ERROR = 5, + /* Unknown is not sent by the sensor */ + FCX_MLDX5_STATUS_UNKNOWN, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_FCX_MLDX5_H_ */ From 69e1d86371d08b2d6556ac99d72564aec0a82d71 Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Fri, 2 Feb 2024 19:51:38 +0100 Subject: [PATCH 1378/2402] tests: build_all: sensor: uart: add fcx_mldx5 Add FCX_MLDx5 uart node in the build_all tests. Signed-off-by: Jeppe Odgaard --- tests/drivers/build_all/sensor/testcase.yaml | 3 +++ tests/drivers/build_all/sensor/uart.dtsi | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/tests/drivers/build_all/sensor/testcase.yaml b/tests/drivers/build_all/sensor/testcase.yaml index bece435e252..3cae1b93cd0 100644 --- a/tests/drivers/build_all/sensor/testcase.yaml +++ b/tests/drivers/build_all/sensor/testcase.yaml @@ -22,10 +22,13 @@ tests: sensors.build: tags: sensors extra_args: OVERLAY_CONFIG=sensors_die_temp.conf + extra_configs: + - CONFIG_UART_INTERRUPT_DRIVEN=y sensors.build.pm: extra_configs: - CONFIG_PM=y - CONFIG_PM_DEVICE=y + - CONFIG_UART_INTERRUPT_DRIVEN=y sensors.generic_test: build_only: false extra_configs: diff --git a/tests/drivers/build_all/sensor/uart.dtsi b/tests/drivers/build_all/sensor/uart.dtsi index 05a2634f24a..9b0e755ebac 100644 --- a/tests/drivers/build_all/sensor/uart.dtsi +++ b/tests/drivers/build_all/sensor/uart.dtsi @@ -34,3 +34,7 @@ test_uart_a01nyub: a01nyub { test_uart_explorir_m: explorir-m { compatible = "gss,explorir-m"; }; + +test_uart_fcx_mldx5: fcx-mldx5 { + compatible = "ap,fcx-mldx5"; +}; From d1d6938a16dbed830b647d87888c137056f41f46 Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Wed, 7 Feb 2024 18:49:47 +0100 Subject: [PATCH 1379/2402] drivers: sensors: grow_r502a: remove all unused drv_data Fix compile warnings cause by removing drv_data in some functions. Signed-off-by: Jeppe Odgaard --- drivers/sensor/grow_r502a/grow_r502a.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/sensor/grow_r502a/grow_r502a.c b/drivers/sensor/grow_r502a/grow_r502a.c index 7898bb9adb9..028b5919407 100644 --- a/drivers/sensor/grow_r502a/grow_r502a.c +++ b/drivers/sensor/grow_r502a/grow_r502a.c @@ -107,7 +107,6 @@ static void uart_cb_handler(const struct device *dev, void *user_data) static int fps_led_control(const struct device *dev, struct led_params *led_control) { - struct grow_r502a_data *drv_data = dev->data; union r502a_packet rx_packet = {0}; char const led_ctrl_len = 5; @@ -137,7 +136,6 @@ static int fps_led_control(const struct device *dev, struct led_params *led_cont static int fps_verify_password(const struct device *dev) { - struct grow_r502a_data *drv_data = dev->data; union r502a_packet rx_packet = {0}; char const verify_pwd_len = 5; @@ -245,7 +243,6 @@ static int fps_read_template_table(const struct device *dev) static int fps_get_image(const struct device *dev) { - struct grow_r502a_data *drv_data = dev->data; union r502a_packet rx_packet = {0}; char const get_img_len = 1; @@ -284,7 +281,6 @@ static int fps_get_image(const struct device *dev) static int fps_image_to_char(const struct device *dev, uint8_t char_buf_idx) { - struct grow_r502a_data *drv_data = dev->data; union r502a_packet rx_packet = {0}; char const img_to_char_len = 2; @@ -312,7 +308,6 @@ static int fps_image_to_char(const struct device *dev, uint8_t char_buf_idx) static int fps_create_model(const struct device *dev) { - struct grow_r502a_data *drv_data = dev->data; union r502a_packet rx_packet = {0}; char const create_model_len = 1; @@ -340,7 +335,6 @@ static int fps_create_model(const struct device *dev) static int fps_store_model(const struct device *dev, uint16_t id) { - struct grow_r502a_data *drv_data = dev->data; union r502a_packet rx_packet = {0}; char const store_model_len = 4; @@ -380,7 +374,6 @@ static int fps_store_model(const struct device *dev, uint16_t id) static int fps_delete_model(const struct device *dev, uint16_t id, uint16_t count) { - struct grow_r502a_data *drv_data = dev->data; union r502a_packet rx_packet = {0}; char const delete_model_len = 5; From f4d55e7f684e0a0e4d82d2654d627bf9e4664c72 Mon Sep 17 00:00:00 2001 From: Bartosz Sokolski Date: Mon, 12 Feb 2024 15:37:09 +0100 Subject: [PATCH 1380/2402] drivers: nrf_qspi_nor: Add option for 2bit IO Add missing NRF_QSPI_READOC_READ2IO option handling to enable 2bit IO Signed-off-by: Bartosz Sokolski --- drivers/flash/nrf_qspi_nor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/flash/nrf_qspi_nor.c b/drivers/flash/nrf_qspi_nor.c index c2ac5f3f3ba..b3a6fbb2ec1 100644 --- a/drivers/flash/nrf_qspi_nor.c +++ b/drivers/flash/nrf_qspi_nor.c @@ -637,7 +637,8 @@ static int configure_chip(const struct device *dev) bool qe_value = (prot_if->writeoc == NRF_QSPI_WRITEOC_PP4IO) || (prot_if->writeoc == NRF_QSPI_WRITEOC_PP4O) || (prot_if->readoc == NRF_QSPI_READOC_READ4IO) || - (prot_if->readoc == NRF_QSPI_READOC_READ4O); + (prot_if->readoc == NRF_QSPI_READOC_READ4O) || + (prot_if->readoc == NRF_QSPI_READOC_READ2IO); uint8_t sr_num = 0; uint8_t qe_mask = 0; From d4965bf6c8becafc072c86045aba263578661920 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Sun, 18 Feb 2024 11:00:20 +0100 Subject: [PATCH 1381/2402] samples: drivers: memc: Add missing include Add string.h because memcpy requires this include file. Signed-off-by: Daniel Schultz --- samples/drivers/memc/src/main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/samples/drivers/memc/src/main.c b/samples/drivers/memc/src/main.c index 60bc1170761..b77f1dbf732 100644 --- a/samples/drivers/memc/src/main.c +++ b/samples/drivers/memc/src/main.c @@ -5,6 +5,7 @@ */ #include +#include #if DT_HAS_COMPAT_STATUS_OKAY(nxp_imx_flexspi) /* Use memc API to get AHB base address for the device */ From 0329aab0442bf7540a9f0feb62f3d199e4f008eb Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Sun, 18 Feb 2024 11:03:55 +0100 Subject: [PATCH 1382/2402] samples: drivers: memc: Make sample more verbose During a memory mismatch, the sample only prints an error message. Also print the read and write buffer to see the actual difference. Moreover, add a print for each compare step to see the sample is still running. Signed-off-by: Daniel Schultz --- samples/drivers/memc/src/main.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/samples/drivers/memc/src/main.c b/samples/drivers/memc/src/main.c index b77f1dbf732..772a2cdd5e1 100644 --- a/samples/drivers/memc/src/main.c +++ b/samples/drivers/memc/src/main.c @@ -70,8 +70,11 @@ int main(void) if (memcmp(memc_read_buffer, memc_write_buffer, BUF_SIZE)) { printk("Error: read data differs in range [0x%x- 0x%x]\n", i, i + (BUF_SIZE - 1)); + dump_memory(memc_write_buffer, BUF_SIZE); + dump_memory(memc_read_buffer, BUF_SIZE); return 0; } + printk("Check (%i/%i) passed!\n", j, (MEMC_SIZE / BUF_SIZE) - 1); } /* Copy any remaining space bytewise */ for (; i < MEMC_SIZE; i++) { From 21411f4678bf1484191fd3550f731aed714eb4b8 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Sun, 18 Feb 2024 10:56:28 +0100 Subject: [PATCH 1383/2402] samples: drivers: memc: Fix README The output example has not the correct indentation for the code-block directive and therefore adds this output as normal text. Signed-off-by: Daniel Schultz --- samples/drivers/memc/README.rst | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/samples/drivers/memc/README.rst b/samples/drivers/memc/README.rst index fbfcc08c606..845f239a40f 100644 --- a/samples/drivers/memc/README.rst +++ b/samples/drivers/memc/README.rst @@ -35,14 +35,20 @@ Sample Output .. code-block:: console -*** Booting Zephyr OS build zephyr-v3.2.0-2686-gd52d828c2bdc *** -Writing to memory region with base 0x38000000, size 0x800000 - -First 1KB of Data in memory: -\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\= -00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f -10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f -20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f -.... - -Read data matches written data + *** Booting Zephyr OS build zephyr-v3.2.0-2686-gd52d828c2bdc *** + Writing to memory region with base 0x38000000, size 0x800000 + + Check (0/8191) passed! + Check (1/8191) passed! + ... + Check (8190/8191) passed! + Check (8191/8191) passed! + + First 1KB of Data in memory: + \=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\=\= + 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f + 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f + 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f + .... + + Read data matches written data From f02170bd9f986826c6420a1244e2616f2e40009a Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Thu, 29 Feb 2024 19:54:51 -0800 Subject: [PATCH 1384/2402] samples: driver: memc: Fix print argument The sample wants to print the memory controller base address. However, MEMC_BASE is used as argument in printf which is defined as long long int. Use the memc pointer instead to print the base address. Signed-off-by: Daniel Schultz --- samples/drivers/memc/src/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/samples/drivers/memc/src/main.c b/samples/drivers/memc/src/main.c index 772a2cdd5e1..1347cce2b12 100644 --- a/samples/drivers/memc/src/main.c +++ b/samples/drivers/memc/src/main.c @@ -54,7 +54,7 @@ int main(void) memc_write_buffer[i] = (uint8_t)i; } printk("Writing to memory region with base %p, size 0x%0x\n\n", - MEMC_BASE, MEMC_SIZE); + memc, MEMC_SIZE); /* Copy write buffer into memc region */ for (i = 0, j = 0; j < (MEMC_SIZE / BUF_SIZE); i += BUF_SIZE, j++) { memcpy(memc + i, memc_write_buffer, BUF_SIZE); From 17d2906ccafab68aa4c253faeb1351b2c6d7cb2b Mon Sep 17 00:00:00 2001 From: Hessel van der Molen Date: Thu, 19 Oct 2023 16:47:47 +0200 Subject: [PATCH 1385/2402] scripts/size_report: display object address in overview Shows RAM/ROM address of object in RAM/ROM-report. Signed-off-by: Hessel van der Molen --- doc/develop/optimizations/tools.rst | 144 ++++++++++++++-------------- scripts/footprint/size_report | 23 +++-- 2 files changed, 86 insertions(+), 81 deletions(-) diff --git a/doc/develop/optimizations/tools.rst b/doc/develop/optimizations/tools.rst index bcd07eac36f..79f8f986f8f 100644 --- a/doc/develop/optimizations/tools.rst +++ b/doc/develop/optimizations/tools.rst @@ -59,48 +59,48 @@ Use the ``ram_report`` target with your board, as in the following example. These commands will generate something similar to the output below:: - Path Size % + Path Size % Address ======================================================================================== - Root 4637 100.00% - ├── (hidden) 4 0.09% - ├── (no paths) 2748 59.26% - │ ├── _cpus_active 4 0.09% - │ ├── _kernel 32 0.69% - │ ├── _sw_isr_table 384 8.28% - │ ├── cli.1 16 0.35% - │ ├── on.2 4 0.09% - │ ├── poll_out_lock.0 4 0.09% - │ ├── z_idle_threads 128 2.76% - │ ├── z_interrupt_stacks 2048 44.17% - │ └── z_main_thread 128 2.76% - ├── WORKSPACE 184 3.97% - │ └── modules 184 3.97% - │ └── hal 184 3.97% - │ └── nordic 184 3.97% - │ └── nrfx 184 3.97% - │ └── drivers 184 3.97% - │ └── src 184 3.97% - │ ├── nrfx_clock.c 8 0.17% - │ │ └── m_clock_cb 8 0.17% - │ ├── nrfx_gpiote.c 132 2.85% - │ │ └── m_cb 132 2.85% - │ ├── nrfx_ppi.c 4 0.09% - │ │ └── m_channels_allocated 4 0.09% - │ └── nrfx_twim.c 40 0.86% - │ └── m_cb 40 0.86% - └── ZEPHYR_BASE 1701 36.68% - ├── arch 5 0.11% - │ └── arm 5 0.11% - │ └── core 5 0.11% - │ ├── mpu 1 0.02% - │ │ └── arm_mpu.c 1 0.02% - │ │ └── static_regions_num 1 0.02% - │ └── tls.c 4 0.09% - │ └── z_arm_tls_ptr 4 0.09% - ├── drivers 258 5.56% - │ ├── ... ... ...% + Root 4637 100.00% - + ├── (hidden) 4 0.09% - + ├── (no paths) 2748 59.26% - + │ ├── _cpus_active 4 0.09% 0x20000314 + │ ├── _kernel 32 0.69% 0x20000318 + │ ├── _sw_isr_table 384 8.28% 0x00006474 + │ ├── cli.1 16 0.35% 0x20000254 + │ ├── on.2 4 0.09% 0x20000264 + │ ├── poll_out_lock.0 4 0.09% 0x200002d4 + │ ├── z_idle_threads 128 2.76% 0x20000120 + │ ├── z_interrupt_stacks 2048 44.17% 0x20000360 + │ └── z_main_thread 128 2.76% 0x200001a0 + ├── WORKSPACE 184 3.97% - + │ └── modules 184 3.97% - + │ └── hal 184 3.97% - + │ └── nordic 184 3.97% - + │ └── nrfx 184 3.97% - + │ └── drivers 184 3.97% - + │ └── src 184 3.97% - + │ ├── nrfx_clock.c 8 0.17% - + │ │ └── m_clock_cb 8 0.17% 0x200002e4 + │ ├── nrfx_gpiote.c 132 2.85% - + │ │ └── m_cb 132 2.85% 0x20000060 + │ ├── nrfx_ppi.c 4 0.09% - + │ │ └── m_channels_allocated 4 0.09% 0x200000e4 + │ └── nrfx_twim.c 40 0.86% - + │ └── m_cb 40 0.86% 0x200002ec + └── ZEPHYR_BASE 1701 36.68% - + ├── arch 5 0.11% - + │ └── arm 5 0.11% - + │ └── core 5 0.11% - + │ ├── mpu 1 0.02% - + │ │ └── arm_mpu.c 1 0.02% - + │ │ └── static_regions_num 1 0.02% 0x20000348 + │ └── tls.c 4 0.09% - + │ └── z_arm_tls_ptr 4 0.09% 0x20000240 + ├── drivers 258 5.56% - + │ ├── ... ... ...% ======================================================================================== - 4637 + 4637 Build Target: rom_report @@ -120,40 +120,40 @@ Use the ``rom_report`` target with your board, as in the following example. These commands will generate something similar to the output below:: - Path Size % + Path Size % Address ======================================================================================== - Root 21652 100.00% - ├── ... ... ...% - └── ZEPHYR_BASE 13378 61.79% - ├── arch 1718 7.93% - │ └── arm 1718 7.93% - │ └── core 1718 7.93% - │ ├── cortex_m 1020 4.71% - │ │ ├── fault.c 620 2.86% - │ │ │ ├── bus_fault.constprop.0 108 0.50% - │ │ │ ├── mem_manage_fault.constprop.0 120 0.55% - │ │ │ ├── usage_fault.constprop.0 84 0.39% - │ │ │ ├── z_arm_fault 292 1.35% - │ │ │ └── z_arm_fault_init 16 0.07% - │ │ ├── ... ... ...% - ├── boards 32 0.15% - │ └── arm 32 0.15% - │ └── reel_board 32 0.15% - │ └── board.c 32 0.15% - │ ├── __init_board_reel_board_init 8 0.04% - │ └── board_reel_board_init 24 0.11% - ├── build 194 0.90% - │ └── zephyr 194 0.90% - │ ├── isr_tables.c 192 0.89% - │ │ └── _irq_vector_table 192 0.89% - │ └── misc 2 0.01% - │ └── generated 2 0.01% - │ └── configs.c 2 0.01% - │ └── _ConfigAbsSyms 2 0.01% - ├── drivers 6162 28.46% - │ ├── ... ... ...% + Root 27828 100.00% - + ├── ... ... ...% + └── ZEPHYR_BASE 13558 48.72% - + ├── arch 1766 6.35% - + │ └── arm 1766 6.35% - + │ └── core 1766 6.35% - + │ ├── cortex_m 1020 3.67% - + │ │ ├── fault.c 620 2.23% - + │ │ │ ├── bus_fault.constprop.0 108 0.39% 0x00000749 + │ │ │ ├── mem_manage_fault.constprop.0 120 0.43% 0x000007b5 + │ │ │ ├── usage_fault.constprop.0 84 0.30% 0x000006f5 + │ │ │ ├── z_arm_fault 292 1.05% 0x0000082d + │ │ │ └── z_arm_fault_init 16 0.06% 0x00000951 + │ │ ├── ... ... ...% + ├── boards 32 0.11% - + │ └── arm 32 0.11% - + │ └── reel_board 32 0.11% - + │ └── board.c 32 0.11% - + │ ├── __init_board_reel_board_init 8 0.03% 0x000063e4 + │ └── board_reel_board_init 24 0.09% 0x00000ed5 + ├── build 194 0.70% - + │ └── zephyr 194 0.70% - + │ ├── isr_tables.c 192 0.69% - + │ │ └── _irq_vector_table 192 0.69% 0x00000040 + │ └── misc 2 0.01% - + │ └── generated 2 0.01% - + │ └── configs.c 2 0.01% - + │ └── _ConfigAbsSyms 2 0.01% 0x00005945 + ├── drivers 6282 22.57% - + │ ├── ... ... ...% ======================================================================================== - 21652 + 21652 Build Target: puncover ====================== diff --git a/scripts/footprint/size_report b/scripts/footprint/size_report index 43e35f1d5fd..becabeb25a9 100755 --- a/scripts/footprint/size_report +++ b/scripts/footprint/size_report @@ -28,6 +28,7 @@ from anytree.exporter import DictExporter import elftools from elftools.elf.elffile import ELFFile +from elftools.elf.relocation import RelocationSection from elftools.elf.sections import SymbolTableSection from elftools.dwarf.descriptions import describe_form_class from elftools.dwarf.descriptions import ( @@ -531,12 +532,13 @@ class TreeNode(NodeMixin): A symbol node. """ - def __init__(self, name, identifier, size=0, parent=None, children=None): + def __init__(self, name, identifier, size=0, parent=None, children=None, address=0): super().__init__() self._name = name self._size = size self.parent = parent self._identifier = identifier + self.address = address if children: self.children = children @@ -582,7 +584,7 @@ def generate_any_tree(symbol_dict, total_size, path_prefix): # A set of helper function for building a simple tree with a path-like # hierarchy. - def _insert_one_elem(root, path, size): + def _insert_one_elem(root, path, size, addr): cur = None node = None parent = root @@ -600,7 +602,7 @@ def generate_any_tree(symbol_dict, total_size, path_prefix): else: if node: parent = node - node = TreeNode(name=str(part), identifier=cur, size=size, parent=parent) + node = TreeNode(name=str(part), identifier=cur, size=size, parent=parent, address=addr) # Mapping paths to tree nodes path_node_map = [ @@ -616,6 +618,7 @@ def generate_any_tree(symbol_dict, total_size, path_prefix): for name, sym in symbol_dict.items(): for symbol in sym: size = get_symbol_size(symbol['symbol']) + addr = get_symbol_addr(symbol['symbol']) for file in symbol['mapped_files']: path = Path(file, name) if path.is_absolute(): @@ -633,7 +636,7 @@ def generate_any_tree(symbol_dict, total_size, path_prefix): else: dest_node = node_no_paths - _insert_one_elem(dest_node, path, size) + _insert_one_elem(dest_node, path, size, addr) if node_zephyr_base is not root: @@ -680,25 +683,27 @@ def print_any_tree(root, total_size, depth): """ Print the symbol tree. """ - print('{:101s} {:7s} {:8s}'.format( - Fore.YELLOW + "Path", "Size", "%" + Fore.RESET)) - print('=' * 110) + print('{:101s} {:7s} {:8s} {:10s}'.format( + Fore.YELLOW + "Path", "Size", "%", "Address" + Fore.RESET)) + print('=' * 126) for row in RenderTree(root, childiter=node_sort, maxlevel=depth): f = len(row.pre) + len(row.node._name) s = str(row.node._size).rjust(100-f) percent = 100 * float(row.node._size) / float(total_size) + hex_addr = "-" cc = cr = "" if not row.node.children: if row.node._name != "(hidden)": + hex_addr = "0x{:08x}".format(row.node.address) cc = Fore.CYAN cr = Fore.RESET elif row.node._name.endswith(SRC_FILE_EXT): cc = Fore.GREEN cr = Fore.RESET - print(f"{row.pre}{cc}{row.node._name} {s} {cr}{Fore.BLUE}{percent:6.2f}%{Fore.RESET}") - print('=' * 110) + print(f"{row.pre}{cc}{row.node._name} {s} {cr}{Fore.BLUE}{percent:6.2f}%{Fore.RESET} {hex_addr}") + print('=' * 126) print(f'{total_size:>101}') From 2ebb8fad7e36c8db74e81dc8c31690b8e40c472d Mon Sep 17 00:00:00 2001 From: Marco Widmer Date: Fri, 1 Mar 2024 15:11:42 +0100 Subject: [PATCH 1386/2402] pm: only define slots if CONFIG_PM is enabled The pm_device_slots section is only used by subsys/pm/pm.c. This file is only compiled if CONFIG_PM=y. pm_device_slots is unused otherwise. Don't populate pm_device_slots when CONFIG_PM=n, CONFIG_PM_DEVICE=y. Signed-off-by: Marco Widmer --- include/zephyr/pm/device.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/zephyr/pm/device.h b/include/zephyr/pm/device.h index 5b6cf0cb33c..d607fc4a042 100644 --- a/include/zephyr/pm/device.h +++ b/include/zephyr/pm/device.h @@ -274,6 +274,7 @@ BUILD_ASSERT(offsetof(struct pm_device_isr, base) == 0); */ #define Z_PM_DEVICE_NAME(dev_id) _CONCAT(__pm_device_, dev_id) +#ifdef CONFIG_PM /** * @brief Define device PM slot. * @@ -288,6 +289,9 @@ BUILD_ASSERT(offsetof(struct pm_device_isr, base) == 0); #define Z_PM_DEVICE_DEFINE_SLOT(dev_id) \ static STRUCT_SECTION_ITERABLE_ALTERNATE(pm_device_slots, device, \ _CONCAT(__pm_slot_, dev_id)) +#else +#define Z_PM_DEVICE_DEFINE_SLOT(dev_id) +#endif /* CONFIG_PM */ #ifdef CONFIG_PM_DEVICE /** From 41f1c3a2b7ce219bd90397d107f6163800ee40aa Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Mon, 11 Mar 2024 13:41:59 -0500 Subject: [PATCH 1387/2402] sensors: Move TDK sensors to a subdirectory Move all tdk/invensense sensors to a subdirectory named after the vendor. Signed-off-by: Tom Burdick --- drivers/sensor/CMakeLists.txt | 12 ++++++------ drivers/sensor/Kconfig | 12 ++++++------ drivers/sensor/{ => tdk}/icm42605/CMakeLists.txt | 0 drivers/sensor/{ => tdk}/icm42605/Kconfig | 0 drivers/sensor/{ => tdk}/icm42605/icm42605.c | 0 drivers/sensor/{ => tdk}/icm42605/icm42605.h | 0 drivers/sensor/{ => tdk}/icm42605/icm42605_reg.h | 0 drivers/sensor/{ => tdk}/icm42605/icm42605_setup.c | 0 drivers/sensor/{ => tdk}/icm42605/icm42605_setup.h | 0 drivers/sensor/{ => tdk}/icm42605/icm42605_spi.c | 0 drivers/sensor/{ => tdk}/icm42605/icm42605_spi.h | 0 drivers/sensor/{ => tdk}/icm42605/icm42605_trigger.c | 0 drivers/sensor/{ => tdk}/icm42670/CMakeLists.txt | 0 drivers/sensor/{ => tdk}/icm42670/Kconfig | 0 drivers/sensor/{ => tdk}/icm42670/icm42670.c | 0 drivers/sensor/{ => tdk}/icm42670/icm42670.h | 0 drivers/sensor/{ => tdk}/icm42670/icm42670_reg.h | 0 drivers/sensor/{ => tdk}/icm42670/icm42670_spi.c | 0 drivers/sensor/{ => tdk}/icm42670/icm42670_spi.h | 0 drivers/sensor/{ => tdk}/icm42670/icm42670_trigger.c | 0 drivers/sensor/{ => tdk}/icm42670/icm42670_trigger.h | 0 drivers/sensor/{ => tdk}/icm42688/CMakeLists.txt | 0 drivers/sensor/{ => tdk}/icm42688/Kconfig | 0 drivers/sensor/{ => tdk}/icm42688/icm42688.c | 0 drivers/sensor/{ => tdk}/icm42688/icm42688.h | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_common.c | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_decoder.c | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_decoder.h | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_emul.c | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_emul.h | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_reg.h | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_rtio.c | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_rtio.h | 0 .../sensor/{ => tdk}/icm42688/icm42688_rtio_stream.c | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_spi.c | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_spi.h | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_trigger.c | 0 drivers/sensor/{ => tdk}/icm42688/icm42688_trigger.h | 0 drivers/sensor/{ => tdk}/icp10125/CMakeLists.txt | 0 drivers/sensor/{ => tdk}/icp10125/Kconfig | 0 drivers/sensor/{ => tdk}/icp10125/icp10125.c | 0 drivers/sensor/{ => tdk}/mpu6050/CMakeLists.txt | 0 drivers/sensor/{ => tdk}/mpu6050/Kconfig | 0 drivers/sensor/{ => tdk}/mpu6050/mpu6050.c | 0 drivers/sensor/{ => tdk}/mpu6050/mpu6050.h | 0 drivers/sensor/{ => tdk}/mpu6050/mpu6050_trigger.c | 0 drivers/sensor/{ => tdk}/mpu9250/CMakeLists.txt | 0 drivers/sensor/{ => tdk}/mpu9250/Kconfig | 0 drivers/sensor/{ => tdk}/mpu9250/ak8963.c | 0 drivers/sensor/{ => tdk}/mpu9250/ak8963.h | 0 drivers/sensor/{ => tdk}/mpu9250/mpu9250.c | 0 drivers/sensor/{ => tdk}/mpu9250/mpu9250.h | 0 drivers/sensor/{ => tdk}/mpu9250/mpu9250_trigger.c | 0 53 files changed, 12 insertions(+), 12 deletions(-) rename drivers/sensor/{ => tdk}/icm42605/CMakeLists.txt (100%) rename drivers/sensor/{ => tdk}/icm42605/Kconfig (100%) rename drivers/sensor/{ => tdk}/icm42605/icm42605.c (100%) rename drivers/sensor/{ => tdk}/icm42605/icm42605.h (100%) rename drivers/sensor/{ => tdk}/icm42605/icm42605_reg.h (100%) rename drivers/sensor/{ => tdk}/icm42605/icm42605_setup.c (100%) rename drivers/sensor/{ => tdk}/icm42605/icm42605_setup.h (100%) rename drivers/sensor/{ => tdk}/icm42605/icm42605_spi.c (100%) rename drivers/sensor/{ => tdk}/icm42605/icm42605_spi.h (100%) rename drivers/sensor/{ => tdk}/icm42605/icm42605_trigger.c (100%) rename drivers/sensor/{ => tdk}/icm42670/CMakeLists.txt (100%) rename drivers/sensor/{ => tdk}/icm42670/Kconfig (100%) rename drivers/sensor/{ => tdk}/icm42670/icm42670.c (100%) rename drivers/sensor/{ => tdk}/icm42670/icm42670.h (100%) rename drivers/sensor/{ => tdk}/icm42670/icm42670_reg.h (100%) rename drivers/sensor/{ => tdk}/icm42670/icm42670_spi.c (100%) rename drivers/sensor/{ => tdk}/icm42670/icm42670_spi.h (100%) rename drivers/sensor/{ => tdk}/icm42670/icm42670_trigger.c (100%) rename drivers/sensor/{ => tdk}/icm42670/icm42670_trigger.h (100%) rename drivers/sensor/{ => tdk}/icm42688/CMakeLists.txt (100%) rename drivers/sensor/{ => tdk}/icm42688/Kconfig (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688.c (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688.h (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_common.c (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_decoder.c (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_decoder.h (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_emul.c (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_emul.h (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_reg.h (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_rtio.c (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_rtio.h (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_rtio_stream.c (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_spi.c (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_spi.h (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_trigger.c (100%) rename drivers/sensor/{ => tdk}/icm42688/icm42688_trigger.h (100%) rename drivers/sensor/{ => tdk}/icp10125/CMakeLists.txt (100%) rename drivers/sensor/{ => tdk}/icp10125/Kconfig (100%) rename drivers/sensor/{ => tdk}/icp10125/icp10125.c (100%) rename drivers/sensor/{ => tdk}/mpu6050/CMakeLists.txt (100%) rename drivers/sensor/{ => tdk}/mpu6050/Kconfig (100%) rename drivers/sensor/{ => tdk}/mpu6050/mpu6050.c (100%) rename drivers/sensor/{ => tdk}/mpu6050/mpu6050.h (100%) rename drivers/sensor/{ => tdk}/mpu6050/mpu6050_trigger.c (100%) rename drivers/sensor/{ => tdk}/mpu9250/CMakeLists.txt (100%) rename drivers/sensor/{ => tdk}/mpu9250/Kconfig (100%) rename drivers/sensor/{ => tdk}/mpu9250/ak8963.c (100%) rename drivers/sensor/{ => tdk}/mpu9250/ak8963.h (100%) rename drivers/sensor/{ => tdk}/mpu9250/mpu9250.c (100%) rename drivers/sensor/{ => tdk}/mpu9250/mpu9250.h (100%) rename drivers/sensor/{ => tdk}/mpu9250/mpu9250_trigger.c (100%) diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 15938bb6421..35790146b02 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -56,10 +56,10 @@ add_subdirectory_ifdef(CONFIG_HP206C hp206c) add_subdirectory_ifdef(CONFIG_HS300X hs300x) add_subdirectory_ifdef(CONFIG_HTS221 hts221) add_subdirectory_ifdef(CONFIG_I3G4250D i3g4250d) -add_subdirectory_ifdef(CONFIG_ICM42605 icm42605) -add_subdirectory_ifdef(CONFIG_ICM42670 icm42670) -add_subdirectory_ifdef(CONFIG_ICM42688 icm42688) -add_subdirectory_ifdef(CONFIG_ICP10125 icp10125) +add_subdirectory_ifdef(CONFIG_ICM42605 tdk/icm42605) +add_subdirectory_ifdef(CONFIG_ICM42670 tdk/icm42670) +add_subdirectory_ifdef(CONFIG_ICM42688 tdk/icm42688) +add_subdirectory_ifdef(CONFIG_ICP10125 tdk/icp10125) add_subdirectory_ifdef(CONFIG_IIS2DH iis2dh) add_subdirectory_ifdef(CONFIG_IIS2DLPC iis2dlpc) add_subdirectory_ifdef(CONFIG_IIS2ICLX iis2iclx) @@ -110,8 +110,8 @@ add_subdirectory_ifdef(CONFIG_MCP9808 mcp9808) add_subdirectory_ifdef(CONFIG_MCUX_ACMP mcux_acmp) add_subdirectory_ifdef(CONFIG_MHZ19B mhz19b) add_subdirectory_ifdef(CONFIG_MPR mpr) -add_subdirectory_ifdef(CONFIG_MPU6050 mpu6050) -add_subdirectory_ifdef(CONFIG_MPU9250 mpu9250) +add_subdirectory_ifdef(CONFIG_MPU6050 tdk/mpu6050) +add_subdirectory_ifdef(CONFIG_MPU9250 tdk/mpu9250) add_subdirectory_ifdef(CONFIG_MS5607 ms5607) add_subdirectory_ifdef(CONFIG_MS5837 ms5837) add_subdirectory_ifdef(CONFIG_NPM1300_CHARGER npm1300_charger) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 244c7d58be0..1768335979a 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -135,10 +135,10 @@ source "drivers/sensor/hp206c/Kconfig" source "drivers/sensor/hs300x/Kconfig" source "drivers/sensor/hts221/Kconfig" source "drivers/sensor/i3g4250d/Kconfig" -source "drivers/sensor/icm42605/Kconfig" -source "drivers/sensor/icm42670/Kconfig" -source "drivers/sensor/icm42688/Kconfig" -source "drivers/sensor/icp10125/Kconfig" +source "drivers/sensor/tdk/icm42605/Kconfig" +source "drivers/sensor/tdk/icm42670/Kconfig" +source "drivers/sensor/tdk/icm42688/Kconfig" +source "drivers/sensor/tdk/icp10125/Kconfig" source "drivers/sensor/iis2dh/Kconfig" source "drivers/sensor/iis2dlpc/Kconfig" source "drivers/sensor/iis2iclx/Kconfig" @@ -191,8 +191,8 @@ source "drivers/sensor/mcp9808/Kconfig" source "drivers/sensor/mcux_acmp/Kconfig" source "drivers/sensor/mhz19b/Kconfig" source "drivers/sensor/mpr/Kconfig" -source "drivers/sensor/mpu6050/Kconfig" -source "drivers/sensor/mpu9250/Kconfig" +source "drivers/sensor/tdk/mpu6050/Kconfig" +source "drivers/sensor/tdk/mpu9250/Kconfig" source "drivers/sensor/ms5607/Kconfig" source "drivers/sensor/ms5837/Kconfig" source "drivers/sensor/npm1300_charger/Kconfig" diff --git a/drivers/sensor/icm42605/CMakeLists.txt b/drivers/sensor/tdk/icm42605/CMakeLists.txt similarity index 100% rename from drivers/sensor/icm42605/CMakeLists.txt rename to drivers/sensor/tdk/icm42605/CMakeLists.txt diff --git a/drivers/sensor/icm42605/Kconfig b/drivers/sensor/tdk/icm42605/Kconfig similarity index 100% rename from drivers/sensor/icm42605/Kconfig rename to drivers/sensor/tdk/icm42605/Kconfig diff --git a/drivers/sensor/icm42605/icm42605.c b/drivers/sensor/tdk/icm42605/icm42605.c similarity index 100% rename from drivers/sensor/icm42605/icm42605.c rename to drivers/sensor/tdk/icm42605/icm42605.c diff --git a/drivers/sensor/icm42605/icm42605.h b/drivers/sensor/tdk/icm42605/icm42605.h similarity index 100% rename from drivers/sensor/icm42605/icm42605.h rename to drivers/sensor/tdk/icm42605/icm42605.h diff --git a/drivers/sensor/icm42605/icm42605_reg.h b/drivers/sensor/tdk/icm42605/icm42605_reg.h similarity index 100% rename from drivers/sensor/icm42605/icm42605_reg.h rename to drivers/sensor/tdk/icm42605/icm42605_reg.h diff --git a/drivers/sensor/icm42605/icm42605_setup.c b/drivers/sensor/tdk/icm42605/icm42605_setup.c similarity index 100% rename from drivers/sensor/icm42605/icm42605_setup.c rename to drivers/sensor/tdk/icm42605/icm42605_setup.c diff --git a/drivers/sensor/icm42605/icm42605_setup.h b/drivers/sensor/tdk/icm42605/icm42605_setup.h similarity index 100% rename from drivers/sensor/icm42605/icm42605_setup.h rename to drivers/sensor/tdk/icm42605/icm42605_setup.h diff --git a/drivers/sensor/icm42605/icm42605_spi.c b/drivers/sensor/tdk/icm42605/icm42605_spi.c similarity index 100% rename from drivers/sensor/icm42605/icm42605_spi.c rename to drivers/sensor/tdk/icm42605/icm42605_spi.c diff --git a/drivers/sensor/icm42605/icm42605_spi.h b/drivers/sensor/tdk/icm42605/icm42605_spi.h similarity index 100% rename from drivers/sensor/icm42605/icm42605_spi.h rename to drivers/sensor/tdk/icm42605/icm42605_spi.h diff --git a/drivers/sensor/icm42605/icm42605_trigger.c b/drivers/sensor/tdk/icm42605/icm42605_trigger.c similarity index 100% rename from drivers/sensor/icm42605/icm42605_trigger.c rename to drivers/sensor/tdk/icm42605/icm42605_trigger.c diff --git a/drivers/sensor/icm42670/CMakeLists.txt b/drivers/sensor/tdk/icm42670/CMakeLists.txt similarity index 100% rename from drivers/sensor/icm42670/CMakeLists.txt rename to drivers/sensor/tdk/icm42670/CMakeLists.txt diff --git a/drivers/sensor/icm42670/Kconfig b/drivers/sensor/tdk/icm42670/Kconfig similarity index 100% rename from drivers/sensor/icm42670/Kconfig rename to drivers/sensor/tdk/icm42670/Kconfig diff --git a/drivers/sensor/icm42670/icm42670.c b/drivers/sensor/tdk/icm42670/icm42670.c similarity index 100% rename from drivers/sensor/icm42670/icm42670.c rename to drivers/sensor/tdk/icm42670/icm42670.c diff --git a/drivers/sensor/icm42670/icm42670.h b/drivers/sensor/tdk/icm42670/icm42670.h similarity index 100% rename from drivers/sensor/icm42670/icm42670.h rename to drivers/sensor/tdk/icm42670/icm42670.h diff --git a/drivers/sensor/icm42670/icm42670_reg.h b/drivers/sensor/tdk/icm42670/icm42670_reg.h similarity index 100% rename from drivers/sensor/icm42670/icm42670_reg.h rename to drivers/sensor/tdk/icm42670/icm42670_reg.h diff --git a/drivers/sensor/icm42670/icm42670_spi.c b/drivers/sensor/tdk/icm42670/icm42670_spi.c similarity index 100% rename from drivers/sensor/icm42670/icm42670_spi.c rename to drivers/sensor/tdk/icm42670/icm42670_spi.c diff --git a/drivers/sensor/icm42670/icm42670_spi.h b/drivers/sensor/tdk/icm42670/icm42670_spi.h similarity index 100% rename from drivers/sensor/icm42670/icm42670_spi.h rename to drivers/sensor/tdk/icm42670/icm42670_spi.h diff --git a/drivers/sensor/icm42670/icm42670_trigger.c b/drivers/sensor/tdk/icm42670/icm42670_trigger.c similarity index 100% rename from drivers/sensor/icm42670/icm42670_trigger.c rename to drivers/sensor/tdk/icm42670/icm42670_trigger.c diff --git a/drivers/sensor/icm42670/icm42670_trigger.h b/drivers/sensor/tdk/icm42670/icm42670_trigger.h similarity index 100% rename from drivers/sensor/icm42670/icm42670_trigger.h rename to drivers/sensor/tdk/icm42670/icm42670_trigger.h diff --git a/drivers/sensor/icm42688/CMakeLists.txt b/drivers/sensor/tdk/icm42688/CMakeLists.txt similarity index 100% rename from drivers/sensor/icm42688/CMakeLists.txt rename to drivers/sensor/tdk/icm42688/CMakeLists.txt diff --git a/drivers/sensor/icm42688/Kconfig b/drivers/sensor/tdk/icm42688/Kconfig similarity index 100% rename from drivers/sensor/icm42688/Kconfig rename to drivers/sensor/tdk/icm42688/Kconfig diff --git a/drivers/sensor/icm42688/icm42688.c b/drivers/sensor/tdk/icm42688/icm42688.c similarity index 100% rename from drivers/sensor/icm42688/icm42688.c rename to drivers/sensor/tdk/icm42688/icm42688.c diff --git a/drivers/sensor/icm42688/icm42688.h b/drivers/sensor/tdk/icm42688/icm42688.h similarity index 100% rename from drivers/sensor/icm42688/icm42688.h rename to drivers/sensor/tdk/icm42688/icm42688.h diff --git a/drivers/sensor/icm42688/icm42688_common.c b/drivers/sensor/tdk/icm42688/icm42688_common.c similarity index 100% rename from drivers/sensor/icm42688/icm42688_common.c rename to drivers/sensor/tdk/icm42688/icm42688_common.c diff --git a/drivers/sensor/icm42688/icm42688_decoder.c b/drivers/sensor/tdk/icm42688/icm42688_decoder.c similarity index 100% rename from drivers/sensor/icm42688/icm42688_decoder.c rename to drivers/sensor/tdk/icm42688/icm42688_decoder.c diff --git a/drivers/sensor/icm42688/icm42688_decoder.h b/drivers/sensor/tdk/icm42688/icm42688_decoder.h similarity index 100% rename from drivers/sensor/icm42688/icm42688_decoder.h rename to drivers/sensor/tdk/icm42688/icm42688_decoder.h diff --git a/drivers/sensor/icm42688/icm42688_emul.c b/drivers/sensor/tdk/icm42688/icm42688_emul.c similarity index 100% rename from drivers/sensor/icm42688/icm42688_emul.c rename to drivers/sensor/tdk/icm42688/icm42688_emul.c diff --git a/drivers/sensor/icm42688/icm42688_emul.h b/drivers/sensor/tdk/icm42688/icm42688_emul.h similarity index 100% rename from drivers/sensor/icm42688/icm42688_emul.h rename to drivers/sensor/tdk/icm42688/icm42688_emul.h diff --git a/drivers/sensor/icm42688/icm42688_reg.h b/drivers/sensor/tdk/icm42688/icm42688_reg.h similarity index 100% rename from drivers/sensor/icm42688/icm42688_reg.h rename to drivers/sensor/tdk/icm42688/icm42688_reg.h diff --git a/drivers/sensor/icm42688/icm42688_rtio.c b/drivers/sensor/tdk/icm42688/icm42688_rtio.c similarity index 100% rename from drivers/sensor/icm42688/icm42688_rtio.c rename to drivers/sensor/tdk/icm42688/icm42688_rtio.c diff --git a/drivers/sensor/icm42688/icm42688_rtio.h b/drivers/sensor/tdk/icm42688/icm42688_rtio.h similarity index 100% rename from drivers/sensor/icm42688/icm42688_rtio.h rename to drivers/sensor/tdk/icm42688/icm42688_rtio.h diff --git a/drivers/sensor/icm42688/icm42688_rtio_stream.c b/drivers/sensor/tdk/icm42688/icm42688_rtio_stream.c similarity index 100% rename from drivers/sensor/icm42688/icm42688_rtio_stream.c rename to drivers/sensor/tdk/icm42688/icm42688_rtio_stream.c diff --git a/drivers/sensor/icm42688/icm42688_spi.c b/drivers/sensor/tdk/icm42688/icm42688_spi.c similarity index 100% rename from drivers/sensor/icm42688/icm42688_spi.c rename to drivers/sensor/tdk/icm42688/icm42688_spi.c diff --git a/drivers/sensor/icm42688/icm42688_spi.h b/drivers/sensor/tdk/icm42688/icm42688_spi.h similarity index 100% rename from drivers/sensor/icm42688/icm42688_spi.h rename to drivers/sensor/tdk/icm42688/icm42688_spi.h diff --git a/drivers/sensor/icm42688/icm42688_trigger.c b/drivers/sensor/tdk/icm42688/icm42688_trigger.c similarity index 100% rename from drivers/sensor/icm42688/icm42688_trigger.c rename to drivers/sensor/tdk/icm42688/icm42688_trigger.c diff --git a/drivers/sensor/icm42688/icm42688_trigger.h b/drivers/sensor/tdk/icm42688/icm42688_trigger.h similarity index 100% rename from drivers/sensor/icm42688/icm42688_trigger.h rename to drivers/sensor/tdk/icm42688/icm42688_trigger.h diff --git a/drivers/sensor/icp10125/CMakeLists.txt b/drivers/sensor/tdk/icp10125/CMakeLists.txt similarity index 100% rename from drivers/sensor/icp10125/CMakeLists.txt rename to drivers/sensor/tdk/icp10125/CMakeLists.txt diff --git a/drivers/sensor/icp10125/Kconfig b/drivers/sensor/tdk/icp10125/Kconfig similarity index 100% rename from drivers/sensor/icp10125/Kconfig rename to drivers/sensor/tdk/icp10125/Kconfig diff --git a/drivers/sensor/icp10125/icp10125.c b/drivers/sensor/tdk/icp10125/icp10125.c similarity index 100% rename from drivers/sensor/icp10125/icp10125.c rename to drivers/sensor/tdk/icp10125/icp10125.c diff --git a/drivers/sensor/mpu6050/CMakeLists.txt b/drivers/sensor/tdk/mpu6050/CMakeLists.txt similarity index 100% rename from drivers/sensor/mpu6050/CMakeLists.txt rename to drivers/sensor/tdk/mpu6050/CMakeLists.txt diff --git a/drivers/sensor/mpu6050/Kconfig b/drivers/sensor/tdk/mpu6050/Kconfig similarity index 100% rename from drivers/sensor/mpu6050/Kconfig rename to drivers/sensor/tdk/mpu6050/Kconfig diff --git a/drivers/sensor/mpu6050/mpu6050.c b/drivers/sensor/tdk/mpu6050/mpu6050.c similarity index 100% rename from drivers/sensor/mpu6050/mpu6050.c rename to drivers/sensor/tdk/mpu6050/mpu6050.c diff --git a/drivers/sensor/mpu6050/mpu6050.h b/drivers/sensor/tdk/mpu6050/mpu6050.h similarity index 100% rename from drivers/sensor/mpu6050/mpu6050.h rename to drivers/sensor/tdk/mpu6050/mpu6050.h diff --git a/drivers/sensor/mpu6050/mpu6050_trigger.c b/drivers/sensor/tdk/mpu6050/mpu6050_trigger.c similarity index 100% rename from drivers/sensor/mpu6050/mpu6050_trigger.c rename to drivers/sensor/tdk/mpu6050/mpu6050_trigger.c diff --git a/drivers/sensor/mpu9250/CMakeLists.txt b/drivers/sensor/tdk/mpu9250/CMakeLists.txt similarity index 100% rename from drivers/sensor/mpu9250/CMakeLists.txt rename to drivers/sensor/tdk/mpu9250/CMakeLists.txt diff --git a/drivers/sensor/mpu9250/Kconfig b/drivers/sensor/tdk/mpu9250/Kconfig similarity index 100% rename from drivers/sensor/mpu9250/Kconfig rename to drivers/sensor/tdk/mpu9250/Kconfig diff --git a/drivers/sensor/mpu9250/ak8963.c b/drivers/sensor/tdk/mpu9250/ak8963.c similarity index 100% rename from drivers/sensor/mpu9250/ak8963.c rename to drivers/sensor/tdk/mpu9250/ak8963.c diff --git a/drivers/sensor/mpu9250/ak8963.h b/drivers/sensor/tdk/mpu9250/ak8963.h similarity index 100% rename from drivers/sensor/mpu9250/ak8963.h rename to drivers/sensor/tdk/mpu9250/ak8963.h diff --git a/drivers/sensor/mpu9250/mpu9250.c b/drivers/sensor/tdk/mpu9250/mpu9250.c similarity index 100% rename from drivers/sensor/mpu9250/mpu9250.c rename to drivers/sensor/tdk/mpu9250/mpu9250.c diff --git a/drivers/sensor/mpu9250/mpu9250.h b/drivers/sensor/tdk/mpu9250/mpu9250.h similarity index 100% rename from drivers/sensor/mpu9250/mpu9250.h rename to drivers/sensor/tdk/mpu9250/mpu9250.h diff --git a/drivers/sensor/mpu9250/mpu9250_trigger.c b/drivers/sensor/tdk/mpu9250/mpu9250_trigger.c similarity index 100% rename from drivers/sensor/mpu9250/mpu9250_trigger.c rename to drivers/sensor/tdk/mpu9250/mpu9250_trigger.c From 95bf346b3bc782dc867d27fd2abe7ce04be2189b Mon Sep 17 00:00:00 2001 From: Tom Burdick Date: Mon, 11 Mar 2024 13:35:39 -0500 Subject: [PATCH 1388/2402] MAINTAINERS: add myself as TDK maintainer Rather than relying solely on the a single sensor maintainer (Maureen!) to maintain all sensor drivers in the tree, take on maintainership of TDK specific sensor drivers myself. Signed-off-by: Tom Burdick --- MAINTAINERS.yml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 51f6267f260..28060933e87 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3764,6 +3764,18 @@ Task Watchdog: tests: - drivers.syscon +TDK Sensors: + status: maintained + maintainers: + - teburd + - MaureenHelm + files: + - drivers/sensor/tdk/ + labels: + - "area: Sensors" + tests: + - drivers.sensors + "Drivers: Time Aware GPIO": status: maintained maintainers: From 9e06a8a1e699060e8a9144af7f80139ddaef3bc0 Mon Sep 17 00:00:00 2001 From: Lukas Gehreke Date: Tue, 12 Mar 2024 11:38:27 +0100 Subject: [PATCH 1389/2402] drivers: uart_pl011: Implemented runtime configure Implemented runtime configure functions for the driver. Signed-off-by: Lukas Gehreke --- drivers/serial/uart_pl011.c | 138 ++++++++++++++++++++++++++++++++---- 1 file changed, 123 insertions(+), 15 deletions(-) diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c index a480f892e91..3510fe29ba6 100644 --- a/drivers/serial/uart_pl011.c +++ b/drivers/serial/uart_pl011.c @@ -9,6 +9,7 @@ #define DT_DRV_COMPAT arm_pl011 #define SBSA_COMPAT arm_sbsa_uart +#include #include #include #include @@ -44,7 +45,7 @@ struct pl011_config { /* Device data structure */ struct pl011_data { DEVICE_MMIO_RAM; - uint32_t baud_rate; /* Baud rate */ + struct uart_config uart_cfg; bool sbsa; /* SBSA mode */ #ifdef CONFIG_UART_INTERRUPT_DRIVEN volatile bool sw_call_txdrdy; @@ -139,6 +140,115 @@ static void pl011_poll_out(const struct device *dev, get_uart(dev)->dr = (uint32_t)c; } +static int pl011_runtime_configure_internal(const struct device *dev, + const struct uart_config *cfg, + bool disable) +{ + const struct pl011_config *config = dev->config; + struct pl011_data *data = dev->data; + uint32_t lcrh; + int ret = -ENOTSUP; + + if (data->sbsa) { + goto out; + } + + if (disable) { + pl011_disable(dev); + pl011_disable_fifo(dev); + } + + lcrh = get_uart(dev)->lcr_h & ~(PL011_LCRH_FORMAT_MASK | PL011_LCRH_STP2); + + switch (cfg->parity) { + case UART_CFG_PARITY_NONE: + lcrh &= ~(BIT(1) | BIT(2)); + break; + case UART_CFG_PARITY_ODD: + lcrh |= PL011_LCRH_PARITY_ODD; + break; + case UART_CFG_PARITY_EVEN: + lcrh |= PL011_LCRH_PARTIY_EVEN; + break; + default: + goto enable; + } + + switch (cfg->stop_bits) { + case UART_CFG_STOP_BITS_1: + lcrh &= ~(PL011_LCRH_STP2); + break; + case UART_CFG_STOP_BITS_2: + lcrh |= PL011_LCRH_STP2; + break; + default: + goto enable; + } + + switch (cfg->data_bits) { + case UART_CFG_DATA_BITS_5: + lcrh |= PL011_LCRH_WLEN_SIZE(5) << PL011_LCRH_WLEN_SHIFT; + break; + case UART_CFG_DATA_BITS_6: + lcrh |= PL011_LCRH_WLEN_SIZE(6) << PL011_LCRH_WLEN_SHIFT; + break; + case UART_CFG_DATA_BITS_7: + lcrh |= PL011_LCRH_WLEN_SIZE(7) << PL011_LCRH_WLEN_SHIFT; + break; + case UART_CFG_DATA_BITS_8: + lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT; + break; + default: + goto enable; + } + + switch (cfg->flow_ctrl) { + case UART_CFG_FLOW_CTRL_NONE: + break; + default: + goto enable; + } + + /* Set baud rate */ + ret = pl011_set_baudrate(dev, config->sys_clk_freq, cfg->baudrate); + if (ret != 0) { + goto enable; + } + + /* Update settings */ + get_uart(dev)->lcr_h = lcrh; + + memcpy(&data->uart_cfg, cfg, sizeof(data->uart_cfg)); + +enable: + if (disable) { + pl011_enable_fifo(dev); + pl011_enable(dev); + } + +out: + return ret; +} + +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + +static int pl011_runtime_configure(const struct device *dev, + const struct uart_config *cfg) +{ + return pl011_runtime_configure_internal(dev, cfg, true); +} + +static int pl011_runtime_config_get(const struct device *dev, + struct uart_config *cfg) +{ + struct pl011_data *data = dev->data; + + *cfg = data->uart_cfg; + return 0; +} + +#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ + #ifdef CONFIG_UART_INTERRUPT_DRIVEN static int pl011_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len) @@ -268,6 +378,10 @@ static void pl011_irq_callback_set(const struct device *dev, static const struct uart_driver_api pl011_driver_api = { .poll_in = pl011_poll_in, .poll_out = pl011_poll_out, +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + .configure = pl011_runtime_configure, + .config_get = pl011_runtime_config_get, +#endif #ifdef CONFIG_UART_INTERRUPT_DRIVEN .fifo_fill = pl011_fifo_fill, .fifo_read = pl011_fifo_read, @@ -291,7 +405,6 @@ static int pl011_init(const struct device *dev) const struct pl011_config *config = dev->config; struct pl011_data *data = dev->data; int ret; - uint32_t lcrh; DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); @@ -324,18 +437,7 @@ static int pl011_init(const struct device *dev) } } - /* Set baud rate */ - ret = pl011_set_baudrate(dev, config->sys_clk_freq, - data->baud_rate); - if (ret != 0) { - return ret; - } - - /* Setting the default character format */ - lcrh = get_uart(dev)->lcr_h & ~(PL011_LCRH_FORMAT_MASK); - lcrh &= ~(BIT(0) | BIT(7)); - lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT; - get_uart(dev)->lcr_h = lcrh; + pl011_runtime_configure_internal(dev, &data->uart_cfg, false); /* Setting transmit and receive interrupt FIFO level */ get_uart(dev)->ifls = FIELD_PREP(PL011_IFLS_TXIFLSEL_M, TXIFLSEL_1_8_FULL) @@ -439,7 +541,13 @@ void pl011_isr(const struct device *dev) PL011_CONFIG_PORT(n) \ \ static struct pl011_data pl011_data_port_##n = { \ - .baud_rate = DT_INST_PROP(n, current_speed), \ + .uart_cfg = { \ + .baudrate = DT_INST_PROP(n, current_speed), \ + .parity = UART_CFG_PARITY_NONE, \ + .stop_bits = UART_CFG_STOP_BITS_1, \ + .data_bits = UART_CFG_DATA_BITS_8, \ + .flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \ + }, \ }; \ \ DEVICE_DT_INST_DEFINE(n, &pl011_init, \ From 5254c153b9ccda36490928c5ca625e91ccdb4f06 Mon Sep 17 00:00:00 2001 From: Juliane Schulze Date: Fri, 15 Mar 2024 15:44:45 +0100 Subject: [PATCH 1390/2402] sensor: tmag5273: fix switched mask/value argument in FIELD_GET This somehow worked without problems during the test runs, but we found a corner case where this leads to an error. Signed-off-by: Juliane Schulze --- drivers/sensor/tmag5273/tmag5273.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/sensor/tmag5273/tmag5273.c b/drivers/sensor/tmag5273/tmag5273.c index d4cd6792760..bade48fa80f 100644 --- a/drivers/sensor/tmag5273/tmag5273.c +++ b/drivers/sensor/tmag5273/tmag5273.c @@ -941,7 +941,7 @@ static inline int tmag5273_init_device_config(const struct device *dev) (int)drv_cfg->temperature; drv_data->conversion_time_us = TMAG5273_T_CONVERSION_US( - (FIELD_GET(regdata, TMAG5273_CONV_AVB_MSK)), (nb_captured_channels)); + (FIELD_GET(TMAG5273_CONV_AVB_MSK, regdata)), (nb_captured_channels)); regdata |= TMAG5273_I2C_READ_MODE_STANDARD; From 1b2bb0dbf23eebf3c51fab5d89773408f3ce08d1 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Mon, 18 Mar 2024 01:25:35 +0000 Subject: [PATCH 1391/2402] input: analog_axis: fix the variable name for calibration Use a coherent name for the calibration data structure variable name. Signed-off-by: Fabio Baltieri --- drivers/input/input_analog_axis.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/input/input_analog_axis.c b/drivers/input/input_analog_axis.c index ace693ddf58..d94c0421046 100644 --- a/drivers/input/input_analog_axis.c +++ b/drivers/input/input_analog_axis.c @@ -249,7 +249,7 @@ static int analog_axis_init(const struct device *dev) analog_axis_channel_data_##inst[ARRAY_SIZE(analog_axis_channel_cfg_##inst)]; \ \ static struct analog_axis_calibration \ - analog_axis_calibration##inst[ARRAY_SIZE(analog_axis_channel_cfg_##inst)] = { \ + analog_axis_calibration_##inst[ARRAY_SIZE(analog_axis_channel_cfg_##inst)] = { \ DT_INST_FOREACH_CHILD_STATUS_OKAY_SEP( \ inst, ANALOG_AXIS_CHANNEL_CAL_DEF, (,)) \ }; \ @@ -258,7 +258,7 @@ static int analog_axis_init(const struct device *dev) .poll_period_ms = DT_INST_PROP(inst, poll_period_ms), \ .channel_cfg = analog_axis_channel_cfg_##inst, \ .channel_data = analog_axis_channel_data_##inst, \ - .calibration = analog_axis_calibration##inst, \ + .calibration = analog_axis_calibration_##inst, \ .num_channels = ARRAY_SIZE(analog_axis_channel_cfg_##inst), \ }; \ \ From 55c14e6fa6d6b438ec157d9967b082e6f446c04a Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Mon, 18 Mar 2024 01:25:46 +0000 Subject: [PATCH 1392/2402] input: analog_axis: rework deadzone calibration code Rework the data scaling algorithm for the "deadzone" mode so that the deadzone is subtracted from the input rather than from the output. This makes the whole output range usable rather than making the output jump from the center value to the minimum deadzone range. This changes the calibration data structure as well so now all values refer to the input data, which is more coherent. Signed-off-by: Fabio Baltieri --- doc/releases/migration-guide-3.7.rst | 6 +++ drivers/input/input_analog_axis.c | 61 +++++++++++++++++----- drivers/input/input_analog_axis_settings.c | 2 +- dts/bindings/input/analog-axis.yaml | 10 ++-- include/zephyr/input/input_analog_axis.h | 4 +- tests/drivers/build_all/input/app.overlay | 2 +- 6 files changed, 64 insertions(+), 21 deletions(-) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index 17884b49b3b..b1be808035a 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -120,6 +120,12 @@ General Purpose I/O (GPIO) Input ===== +* The ``analog-axis`` deadzone calibration value has been changed to be + relative to the raw ADC values, similarly to min and max. The data structures + and properties have been renamed to reflect that (from ``out-deadzone`` to + ``in-deadzone``) and when migrating to the new definition the value should be + scaled accordingly. + Interrupt Controller ==================== diff --git a/drivers/input/input_analog_axis.c b/drivers/input/input_analog_axis.c index d94c0421046..832bd970fba 100644 --- a/drivers/input/input_analog_axis.c +++ b/drivers/input/input_analog_axis.c @@ -101,6 +101,48 @@ int analog_axis_calibration_set(const struct device *dev, return 0; } +static int32_t analog_axis_out_deadzone(const struct device *dev, + int channel, + int32_t raw_val) +{ + const struct analog_axis_config *cfg = dev->config; + const struct analog_axis_channel_config *axis_cfg = &cfg->channel_cfg[channel]; + struct analog_axis_calibration *cal = &cfg->calibration[channel]; + + int16_t in_range = cal->in_max - cal->in_min; + int16_t out_range = axis_cfg->out_max - axis_cfg->out_min; + int16_t in_mid = DIV_ROUND_CLOSEST(cal->in_min + cal->in_max, 2); + int16_t in_min = cal->in_min; + + if (abs(raw_val - in_mid) < cal->in_deadzone) { + return DIV_ROUND_CLOSEST(axis_cfg->out_max + axis_cfg->out_min, 2); + } + + in_range -= cal->in_deadzone * 2; + in_min += cal->in_deadzone; + if (raw_val < in_mid) { + raw_val += cal->in_deadzone; + } else { + raw_val -= cal->in_deadzone; + } + + return DIV_ROUND_CLOSEST((raw_val - in_min) * out_range, in_range) + axis_cfg->out_min; +} + +static int32_t analog_axis_out_linear(const struct device *dev, + int channel, + int32_t raw_val) +{ + const struct analog_axis_config *cfg = dev->config; + const struct analog_axis_channel_config *axis_cfg = &cfg->channel_cfg[channel]; + struct analog_axis_calibration *cal = &cfg->calibration[channel]; + + int16_t in_range = cal->in_max - cal->in_min; + int16_t out_range = axis_cfg->out_max - axis_cfg->out_min; + + return DIV_ROUND_CLOSEST((raw_val - cal->in_min) * out_range, in_range) + axis_cfg->out_min; +} + static void analog_axis_loop(const struct device *dev) { const struct analog_axis_config *cfg = dev->config; @@ -135,8 +177,6 @@ static void analog_axis_loop(const struct device *dev) const struct analog_axis_channel_config *axis_cfg = &cfg->channel_cfg[i]; struct analog_axis_channel_data *axis_data = &cfg->channel_data[i]; struct analog_axis_calibration *cal = &cfg->calibration[i]; - int16_t in_range = cal->in_max - cal->in_min; - int16_t out_range = axis_cfg->out_max - axis_cfg->out_min; int32_t raw_val = bufs[i]; if (axis_cfg->invert) { @@ -149,17 +189,14 @@ static void analog_axis_loop(const struct device *dev) LOG_DBG("%s: ch %d: raw_val: %d", dev->name, i, raw_val); - out = CLAMP((raw_val - cal->in_min) * out_range / in_range + axis_cfg->out_min, - axis_cfg->out_min, axis_cfg->out_max); - - if (cal->out_deadzone > 0) { - int16_t center = DIV_ROUND_CLOSEST( - axis_cfg->out_max + axis_cfg->out_min, 2); - if (abs(out - center) < cal->out_deadzone) { - out = center; - } + if (cal->in_deadzone > 0) { + out = analog_axis_out_deadzone(dev, i, raw_val); + } else { + out = analog_axis_out_linear(dev, i, raw_val); } + out = CLAMP(out, axis_cfg->out_min, axis_cfg->out_max); + if (axis_data->last_out != out) { input_report_abs(dev, axis_cfg->axis, out, true, K_FOREVER); } @@ -237,7 +274,7 @@ static int analog_axis_init(const struct device *dev) { \ .in_min = (int16_t)DT_PROP(node_id, in_min), \ .in_max = (int16_t)DT_PROP(node_id, in_max), \ - .out_deadzone = DT_PROP(node_id, out_deadzone), \ + .in_deadzone = DT_PROP(node_id, in_deadzone), \ } #define ANALOG_AXIS_INIT(inst) \ diff --git a/drivers/input/input_analog_axis_settings.c b/drivers/input/input_analog_axis_settings.c index 3d29af8b96f..b6d88a64b5c 100644 --- a/drivers/input/input_analog_axis_settings.c +++ b/drivers/input/input_analog_axis_settings.c @@ -27,7 +27,7 @@ static void analog_axis_calibration_log(const struct device *dev) analog_axis_calibration_get(dev, i, &cal); LOG_INF("%s: ch: %d min: %d max: %d deadzone: %d", - dev->name, i, cal.in_min, cal.in_max, cal.out_deadzone); + dev->name, i, cal.in_min, cal.in_max, cal.in_deadzone); } } diff --git a/dts/bindings/input/analog-axis.yaml b/dts/bindings/input/analog-axis.yaml index ded94e86c0f..62b6c04703d 100644 --- a/dts/bindings/input/analog-axis.yaml +++ b/dts/bindings/input/analog-axis.yaml @@ -16,7 +16,7 @@ description: | poll-period-ms = <15>; axis-x { io-channels = <&adc 0>; - out-deadzone = <8>; + in-deadzone = <50>; in-min = <100>; in-max = <800>; zephyr,axis = ; @@ -56,13 +56,13 @@ child-binding: Maximum value to output on input events. Defaults to 255 if unspecified. - out-deadzone: + in-deadzone: type: int default: 0 description: | - Deadzone for the output center value. If specified output values - between the center of the range plus or minus this value will be - reported as center. Defaults to 0, no deadzone. + Deadzone for the input center value. If specified input values between + the center of the range plus or minus this value will be reported as + center. Defaults to 0, no deadzone. in-min: type: int diff --git a/include/zephyr/input/input_analog_axis.h b/include/zephyr/input/input_analog_axis.h index 14492156d9c..65ab6431812 100644 --- a/include/zephyr/input/input_analog_axis.h +++ b/include/zephyr/input/input_analog_axis.h @@ -29,8 +29,8 @@ struct analog_axis_calibration { int16_t in_min; /** Input value that corresponds to the maximum output value. */ int16_t in_max; - /** Output value deadzone relative to the output range. */ - uint16_t out_deadzone; + /** Input value center deadzone. */ + uint16_t in_deadzone; }; /** diff --git a/tests/drivers/build_all/input/app.overlay b/tests/drivers/build_all/input/app.overlay index f5661d5196c..b34d781bf53 100644 --- a/tests/drivers/build_all/input/app.overlay +++ b/tests/drivers/build_all/input/app.overlay @@ -136,7 +136,7 @@ io-channels = <&test_adc 0>; out-min = <(-127)>; out-max = <127>; - out-deadzone = <8>; + in-deadzone = <8>; in-min = <(-100)>; in-max = <100>; zephyr,axis = <0>; From e9dc52c905e292c4be4fbe5884ce66f1b2a2a506 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Wed, 20 Mar 2024 15:33:56 +0800 Subject: [PATCH 1393/2402] boards: numaker_pfm_m467: change default runner to pyocd PyOCD is preferred for better support. Signed-off-by: Chun-Chieh Li --- boards/nuvoton/numaker_pfm_m467/board.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/nuvoton/numaker_pfm_m467/board.cmake b/boards/nuvoton/numaker_pfm_m467/board.cmake index 58661cdae22..6b3fc72f3a5 100644 --- a/boards/nuvoton/numaker_pfm_m467/board.cmake +++ b/boards/nuvoton/numaker_pfm_m467/board.cmake @@ -3,7 +3,7 @@ board_runner_args(pyocd "--target=m467hjhae") board_runner_args(nulink "-f") +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/nulink.board.cmake) include(${ZEPHYR_BASE}/boards/common/canopen.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) From d1a468bac96ef3a1f2764d1d69bc02c45b1ba7d1 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Wed, 20 Mar 2024 17:56:23 +0800 Subject: [PATCH 1394/2402] boards: numaker_pfm_m467: remove unsupported runners nulink and canopen Remove nulink and canopen for unsupported Signed-off-by: Chun-Chieh Li --- boards/nuvoton/numaker_pfm_m467/board.cmake | 3 --- 1 file changed, 3 deletions(-) diff --git a/boards/nuvoton/numaker_pfm_m467/board.cmake b/boards/nuvoton/numaker_pfm_m467/board.cmake index 6b3fc72f3a5..57133162dfb 100644 --- a/boards/nuvoton/numaker_pfm_m467/board.cmake +++ b/boards/nuvoton/numaker_pfm_m467/board.cmake @@ -1,9 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(pyocd "--target=m467hjhae") -board_runner_args(nulink "-f") include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nulink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/canopen.board.cmake) From f6801abe6560f39d8a624855bf1f5de83d08bb1a Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 21 Mar 2024 13:39:41 -0400 Subject: [PATCH 1395/2402] MAINTAINERS: twister: update collaborators Update collaborators for twister based on activity. Signed-off-by: Anas Nashif --- MAINTAINERS.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 28060933e87..d1221a734fe 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2960,12 +2960,13 @@ Twister: maintainers: - nashif collaborators: - - galak - PerMac - hakehuang - gopiotr - golowanow - gchwier + - LukaszMrugala + - KamilxPaszkiet files: - scripts/twister - scripts/schemas/twister/ From 4b15e48b9847a42017d6ebe19d7a3004495e3bcc Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Wed, 24 Jan 2024 12:52:21 +0100 Subject: [PATCH 1396/2402] tests: adc: boards: native_sim: fix spi addresses and missing test_gpio Give each SPI node a unique address to fix warnings. Add missing test_gpio to fix compile error for last node. Signed-off-by: Jeppe Odgaard --- .../build_all/adc/boards/native_sim.overlay | 45 ++++++++++--------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/tests/drivers/build_all/adc/boards/native_sim.overlay b/tests/drivers/build_all/adc/boards/native_sim.overlay index cc7ac9a45e2..ff4f0702b68 100644 --- a/tests/drivers/build_all/adc/boards/native_sim.overlay +++ b/tests/drivers/build_all/adc/boards/native_sim.overlay @@ -126,6 +126,7 @@ <&test_gpio 0 0>, <&test_gpio 0 0>, <&test_gpio 0 0>, + <&test_gpio 0 0>, <&test_gpio 0 0>; test_spi_mcp3204: mcp3204@0 { @@ -237,9 +238,9 @@ }; - test_spi_ads114s08: ads114s08@9 { + test_spi_ads114s08: ads114s08@c { compatible = "ti,ads114s08"; - reg = <0x9>; + reg = <0xc>; spi-max-frequency = <0>; #io-channel-cells = <1>; reset-gpios = <&test_gpio 0 0>; @@ -247,77 +248,77 @@ start-sync-gpios = <&test_gpio 0 0>; }; - test_spi_max11102: max11102@a { + test_spi_max11102: max11102@d { compatible = "maxim,max11102"; - reg = <0xa>; + reg = <0xd>; spi-max-frequency = <0>; #io-channel-cells = <1>; chsel-gpios = <&test_gpio 0 0>; }; - test_spi_max11103: max11103@b { + test_spi_max11103: max11103@e { compatible = "maxim,max11103"; - reg = <0xb>; + reg = <0xe>; spi-max-frequency = <0>; #io-channel-cells = <1>; chsel-gpios = <&test_gpio 0 0>; }; - test_spi_max11105: max11105@c { + test_spi_max11105: max11105@f { compatible = "maxim,max11105"; - reg = <0xc>; + reg = <0xf>; spi-max-frequency = <0>; #io-channel-cells = <1>; }; - test_spi_max11106: max11106@d { + test_spi_max11106: max11106@10 { compatible = "maxim,max11106"; - reg = <0xd>; + reg = <0x10>; spi-max-frequency = <0>; #io-channel-cells = <1>; chsel-gpios = <&test_gpio 0 0>; }; - test_spi_max11110: max11110@e { + test_spi_max11110: max11110@11 { compatible = "maxim,max11110"; - reg = <0xe>; + reg = <0x11>; spi-max-frequency = <0>; #io-channel-cells = <1>; }; - test_spi_max11111: max11111@f { + test_spi_max11111: max11111@12 { compatible = "maxim,max11111"; - reg = <0xf>; + reg = <0x12>; spi-max-frequency = <0>; #io-channel-cells = <1>; chsel-gpios = <&test_gpio 0 0>; }; - test_spi_max11115: max11115@10 { + test_spi_max11115: max11115@13 { compatible = "maxim,max11115"; - reg = <0x10>; + reg = <0x13>; spi-max-frequency = <0>; #io-channel-cells = <1>; }; - test_spi_max11116: max11116@11 { + test_spi_max11116: max11116@14 { compatible = "maxim,max11116"; - reg = <0x11>; + reg = <0x14>; spi-max-frequency = <0>; #io-channel-cells = <1>; }; - test_spi_max11117: max11117@12 { + test_spi_max11117: max11117@15 { compatible = "maxim,max11117"; - reg = <0x12>; + reg = <0x15>; spi-max-frequency = <0>; #io-channel-cells = <1>; }; - test_spi_ad5592: ad5592@13 { + test_spi_ad5592: ad5592@16 { compatible = "adi,ad5592"; status = "okay"; - reg = <0x13>; + reg = <0x16>; spi-max-frequency = <0>; reset-gpios = <&test_gpio 0 0>; From 2fdf88f71c6ac5862c9316097a42be548e231304 Mon Sep 17 00:00:00 2001 From: Jeppe Odgaard Date: Wed, 24 Jan 2024 12:56:02 +0100 Subject: [PATCH 1397/2402] tests: dac: overlay: change spi addresses to lowercase Change to SPI address to lowercase to fix compile warning. Signed-off-by: Jeppe Odgaard --- tests/drivers/build_all/dac/app.overlay | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/drivers/build_all/dac/app.overlay b/tests/drivers/build_all/dac/app.overlay index ee82a5e8b86..9767e3b9616 100644 --- a/tests/drivers/build_all/dac/app.overlay +++ b/tests/drivers/build_all/dac/app.overlay @@ -187,7 +187,7 @@ reset-gpios = <&test_gpio 0 0>; }; - test_spi_ad5676: ad5676@A { + test_spi_ad5676: ad5676@a { compatible = "adi,ad5676"; reg = <0xA>; spi-max-frequency = <0>; @@ -195,7 +195,7 @@ reset-gpios = <&test_gpio 0 0>; }; - test_spi_ad5679: ad5679@B { + test_spi_ad5679: ad5679@b { compatible = "adi,ad5679"; reg = <0xB>; spi-max-frequency = <0>; @@ -203,7 +203,7 @@ reset-gpios = <&test_gpio 0 0>; }; - test_spi_ad5684: ad5684@C { + test_spi_ad5684: ad5684@c { compatible = "adi,ad5684"; reg = <0xC>; spi-max-frequency = <0>; @@ -211,7 +211,7 @@ reset-gpios = <&test_gpio 0 0>; }; - test_spi_ad5686: ad5686@D { + test_spi_ad5686: ad5686@d { compatible = "adi,ad5686"; reg = <0xD>; spi-max-frequency = <0>; @@ -219,7 +219,7 @@ reset-gpios = <&test_gpio 0 0>; }; - test_spi_ad5687: ad5687@E { + test_spi_ad5687: ad5687@e { compatible = "adi,ad5687"; reg = <0xE>; spi-max-frequency = <0>; @@ -227,7 +227,7 @@ reset-gpios = <&test_gpio 0 0>; }; - test_spi_ad5689: ad5689@F { + test_spi_ad5689: ad5689@f { compatible = "adi,ad5689"; reg = <0xF>; spi-max-frequency = <0>; From 96d554467045a60a0811be5ca2139e5e068f861a Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 22 Mar 2024 10:07:25 +0100 Subject: [PATCH 1398/2402] boards nrf5340bsim: Remove hwmv1 compatible board definitions To use this functionality one must now use the hwmv2 naming (nrf5340bsim/nrf5340/cpu{app,net}). The old hwmv1 compatible names for these targets, were left provisionally while all tests in tree were ported. That being now done, these old names can be removed. After this change one cannot build anymore targeting nrf5340bsim_nrf5340_cpu{app,net} but must instead build targeting nrf5340bsim/nrf5340/cpu{app,net} For twister tests the old name were already not valid. Signed-off-by: Alberto Escolar Piedras --- boards/deprecated.cmake | 6 ++++++ .../nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpuapp | 5 ----- .../nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpunet | 5 ----- boards/native/nrf_bsim/board.yml | 12 ------------ 4 files changed, 6 insertions(+), 22 deletions(-) delete mode 100644 boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpuapp delete mode 100644 boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpunet diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 4cfd9678c2e..20e11bead5b 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -446,6 +446,12 @@ set(nrf5340_audio_dk_nrf5340_cpuapp_ns_DEPRECATED set(nrf5340_audio_dk_nrf5340_cpunet_DEPRECATED nrf5340_audio_dk/nrf5340/cpunet ) +set(nrf5340bsim_nrf5340_cpuapp_DEPRECATED + nrf5340bsim/nrf5340/cpuapp +) +set(nrf5340bsim_nrf5340_cpunet_DEPRECATED + nrf5340bsim/nrf5340/cpunet +) set(nrf5340dk_nrf5340_cpuapp_DEPRECATED nrf5340dk/nrf5340/cpuapp ) diff --git a/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpuapp b/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpuapp deleted file mode 100644 index 8e342000c3e..00000000000 --- a/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpuapp +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF5340BSIM_NRF5340_CPUAPP - select SOC_POSIX diff --git a/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpunet b/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpunet deleted file mode 100644 index e6867244e77..00000000000 --- a/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpunet +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF5340BSIM_NRF5340_CPUNET - select SOC_POSIX diff --git a/boards/native/nrf_bsim/board.yml b/boards/native/nrf_bsim/board.yml index 20c9137a233..874c661c380 100644 --- a/boards/native/nrf_bsim/board.yml +++ b/boards/native/nrf_bsim/board.yml @@ -9,15 +9,3 @@ boards: # Note this is referring to the real SOC yaml, but we only use its name and cpu-cluster definition # In practice this board uses the same native SOC (SOC_POSIX) as the nrf52_bsim - name: nrf5340 - -# These two board definitions below, together with their respective -# Kconfig.nrf5340bsim_nrf5340_cpu[app,net] exist for backwards compatibility with hwmv1 usage -# Once all their usage in tree is removed, or aliases have been introduced they can be removed. -- name: nrf5340bsim_nrf5340_cpuapp - vendor: zephyr - socs: - - name: native -- name: nrf5340bsim_nrf5340_cpunet - vendor: zephyr - socs: - - name: native From 6514b3b88d979d1999ffc6cedb54e4eb86be9a28 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 22 Mar 2024 10:18:03 +0100 Subject: [PATCH 1399/2402] bsim tests|samples: Remove uses of the nrf5340bsim hwmv1 boards Using the old hwmv1 board names is not supported anymore. So we don't need to handle them specially in the sysbuild files. Signed-off-by: Alberto Escolar Piedras --- .../audio_samples/broadcast_audio_sink/Kconfig.sysbuild | 1 - .../audio_samples/unicast_audio_client/Kconfig.sysbuild | 1 - tests/bsim/bluetooth/ll/bis/Kconfig.sysbuild | 1 - tests/bsim/bluetooth/ll/cis/Kconfig.sysbuild | 1 - tests/bsim/bluetooth/ll/conn/Kconfig.sysbuild | 1 - 5 files changed, 5 deletions(-) diff --git a/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/Kconfig.sysbuild b/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/Kconfig.sysbuild index c661fef422e..63b369429bd 100644 --- a/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/Kconfig.sysbuild +++ b/tests/bsim/bluetooth/audio_samples/broadcast_audio_sink/Kconfig.sysbuild @@ -7,5 +7,4 @@ config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX int # Let's pass the test arguments to the application MCU test # otherwise by default they would have gone to the net core. - default 0 if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" default 0 if $(BOARD) = "nrf5340bsim" diff --git a/tests/bsim/bluetooth/audio_samples/unicast_audio_client/Kconfig.sysbuild b/tests/bsim/bluetooth/audio_samples/unicast_audio_client/Kconfig.sysbuild index e29e9bb5642..ad82e381a1c 100644 --- a/tests/bsim/bluetooth/audio_samples/unicast_audio_client/Kconfig.sysbuild +++ b/tests/bsim/bluetooth/audio_samples/unicast_audio_client/Kconfig.sysbuild @@ -7,5 +7,4 @@ config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX int # Let's pass the test arguments to the application MCU test # otherwise by default they would have gone to the net core. - default 0 if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" default 0 if $(BOARD) = "nrf5340bsim" diff --git a/tests/bsim/bluetooth/ll/bis/Kconfig.sysbuild b/tests/bsim/bluetooth/ll/bis/Kconfig.sysbuild index 124326b0f19..f534fabcd22 100644 --- a/tests/bsim/bluetooth/ll/bis/Kconfig.sysbuild +++ b/tests/bsim/bluetooth/ll/bis/Kconfig.sysbuild @@ -11,5 +11,4 @@ config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX int # Let's pass the test arguments to the application MCU test # otherwise by default they would have gone to the net core. - default 0 if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" default 0 if $(BOARD) = "nrf5340bsim" diff --git a/tests/bsim/bluetooth/ll/cis/Kconfig.sysbuild b/tests/bsim/bluetooth/ll/cis/Kconfig.sysbuild index 124326b0f19..f534fabcd22 100644 --- a/tests/bsim/bluetooth/ll/cis/Kconfig.sysbuild +++ b/tests/bsim/bluetooth/ll/cis/Kconfig.sysbuild @@ -11,5 +11,4 @@ config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX int # Let's pass the test arguments to the application MCU test # otherwise by default they would have gone to the net core. - default 0 if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" default 0 if $(BOARD) = "nrf5340bsim" diff --git a/tests/bsim/bluetooth/ll/conn/Kconfig.sysbuild b/tests/bsim/bluetooth/ll/conn/Kconfig.sysbuild index 124326b0f19..f534fabcd22 100644 --- a/tests/bsim/bluetooth/ll/conn/Kconfig.sysbuild +++ b/tests/bsim/bluetooth/ll/conn/Kconfig.sysbuild @@ -11,5 +11,4 @@ config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX int # Let's pass the test arguments to the application MCU test # otherwise by default they would have gone to the net core. - default 0 if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" default 0 if $(BOARD) = "nrf5340bsim" From f22d30b853ebbf2189874e088586ce1f59cdff1e Mon Sep 17 00:00:00 2001 From: Yusuf Ahmed Date: Thu, 7 Sep 2023 14:46:00 -0700 Subject: [PATCH 1400/2402] tests/driver/adc: Add ADC accuracy test These tests, that expects boards to be properly setup, allow one to measure ADC value and compare to expected values. Two tests are added. For one, a reference voltage is expected on the ADC - and this value can be informed to the test via devicetree. The other uses DAC to generate a value that is then read from ADC. This assumes DAC is accurate. Naturally, one could make this a DAC test if ADC is assumed to be accurate. As the board setup involve connecting physical pins, they are behind twister fixtures. Signed-off-by: Yusuf Ahmed Signed-off-by: Ederson de Souza --- .../adc/adc_accuracy_test/CMakeLists.txt | 10 +++ tests/drivers/adc/adc_accuracy_test/Kconfig | 22 ++++++ .../drivers/adc/adc_accuracy_test/README.txt | 21 +++++ .../adc_accuracy_test/boards/frdm_k64f.conf | 1 + .../boards/frdm_k64f.overlay | 32 ++++++++ .../boards/frdm_kl25z.overlay | 26 +++++++ tests/drivers/adc/adc_accuracy_test/prj.conf | 2 + .../adc/adc_accuracy_test/src/dac_source.c | 78 +++++++++++++++++++ .../drivers/adc/adc_accuracy_test/src/main.c | 33 ++++++++ .../adc/adc_accuracy_test/src/ref_volt.c | 48 ++++++++++++ .../adc/adc_accuracy_test/testcase.yaml | 19 +++++ 11 files changed, 292 insertions(+) create mode 100644 tests/drivers/adc/adc_accuracy_test/CMakeLists.txt create mode 100644 tests/drivers/adc/adc_accuracy_test/Kconfig create mode 100644 tests/drivers/adc/adc_accuracy_test/README.txt create mode 100644 tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.conf create mode 100644 tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.overlay create mode 100644 tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay create mode 100644 tests/drivers/adc/adc_accuracy_test/prj.conf create mode 100644 tests/drivers/adc/adc_accuracy_test/src/dac_source.c create mode 100644 tests/drivers/adc/adc_accuracy_test/src/main.c create mode 100644 tests/drivers/adc/adc_accuracy_test/src/ref_volt.c create mode 100644 tests/drivers/adc/adc_accuracy_test/testcase.yaml diff --git a/tests/drivers/adc/adc_accuracy_test/CMakeLists.txt b/tests/drivers/adc/adc_accuracy_test/CMakeLists.txt new file mode 100644 index 00000000000..8c376af3eef --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(dac_accuracy) + +target_sources(app PRIVATE src/main.c) +target_sources_ifdef(CONFIG_REFERENCE_VOLTAGE_TEST app PRIVATE src/ref_volt.c) +target_sources_ifdef(CONFIG_DAC_SOURCE_TEST app PRIVATE src/dac_source.c) diff --git a/tests/drivers/adc/adc_accuracy_test/Kconfig b/tests/drivers/adc/adc_accuracy_test/Kconfig new file mode 100644 index 00000000000..9264c69f8bb --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/Kconfig @@ -0,0 +1,22 @@ +# Copyright (c) 2023 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +mainmenu "ADC accuracy test" + +source "Kconfig.zephyr" + +# Workaround to have commas on function arguments +ZEPHYR_USER := zephyr,user + +config DAC_SOURCE_TEST + bool + default y if $(dt_node_has_prop,/$(ZEPHYR_USER),dac) + +config REFERENCE_VOLTAGE_TEST + bool + default y if $(dt_node_has_prop,/$(ZEPHYR_USER),reference_mv) + +config NUMBER_OF_PASSES + int "Number of passes" + default 5 diff --git a/tests/drivers/adc/adc_accuracy_test/README.txt b/tests/drivers/adc/adc_accuracy_test/README.txt new file mode 100644 index 00000000000..6c233052001 --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/README.txt @@ -0,0 +1,21 @@ +ADC accuracy test + +This test checks that ADC readings match an expected value. It is +done using two approaches: + + - DAC source: a board DAC pin is set to a known value, which is then + read on an ADC one. If they match, the test passes. + + - Reference voltage: an ADC channel is read and compared to an expected + value. + +For the DAC source, it is expected that DAC and ADC are connected. This +can be indicated for twister runs by setting the fixture "dac_adc_loop". +The test then sets DAC to half its resolution and reads the ADC to see +if they match. Note that DAC and ADC are expected to generate/read +voltage on the same range. + +In the reference voltage case, the ADC is expected to be connected to a +known voltage reference, whose value is informed, in millivolts, at +property "reference_mv" from "zephyr,user" node. The test reads the ADC +to see if they match. diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.conf b/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.conf new file mode 100644 index 00000000000..5ddebe8a96e --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.conf @@ -0,0 +1 @@ +CONFIG_DAC=y diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.overlay b/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.overlay new file mode 100644 index 00000000000..ce9acbd1677 --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.overlay @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Please connect J4.3 and J4.11 together to run this test. + * J4.3 will be the ADC input and J4.11 the DAC output + */ + +/ { + zephyr,user { + io-channels = <&adc0 20>; + dac = <&dac0>; + dac-channel-id = <0>; + dac-resolution = <12>; + }; +}; + +&adc0{ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@14 { + reg = <20>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay b/tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay new file mode 100644 index 00000000000..148ecda4535 --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + zephyr,user { + io-channels = <&adc0 12>; + reference_mv = <1100>; + }; +}; + +&adc0{ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@12 { + reg = <12>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; diff --git a/tests/drivers/adc/adc_accuracy_test/prj.conf b/tests/drivers/adc/adc_accuracy_test/prj.conf new file mode 100644 index 00000000000..c82d81afb56 --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/prj.conf @@ -0,0 +1,2 @@ +CONFIG_ZTEST=y +CONFIG_ADC=y diff --git a/tests/drivers/adc/adc_accuracy_test/src/dac_source.c b/tests/drivers/adc/adc_accuracy_test/src/dac_source.c new file mode 100644 index 00000000000..34a857fb011 --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/src/dac_source.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#define DIV 2 + +#define DAC_DEVICE_NODE DT_PROP(DT_PATH(zephyr_user), dac) + +extern const struct adc_dt_spec *get_adc_channel(void); + +static const struct dac_channel_cfg dac_ch_cfg = { + .channel_id = DT_PROP(DT_PATH(zephyr_user), dac_channel_id), + .resolution = DT_PROP(DT_PATH(zephyr_user), dac_resolution), + .buffered = true +}; + +static const struct device *init_dac(void) +{ + int ret; + const struct device *const dac_dev = DEVICE_DT_GET(DAC_DEVICE_NODE); + + zassert_true(device_is_ready(dac_dev), "DAC device is not ready"); + + ret = dac_channel_setup(dac_dev, &dac_ch_cfg); + zassert_equal(ret, 0, + "Setting up of the first channel failed with code %d", ret); + + return dac_dev; +} + +static int test_dac_to_adc(void) +{ + int ret, write_val; + int32_t sample_buffer = 0; + + struct adc_sequence sequence = { + .buffer = &sample_buffer, + .buffer_size = sizeof(sample_buffer), + }; + + const struct device *dac_dev = init_dac(); + const struct adc_dt_spec *adc_channel = get_adc_channel(); + + write_val = (1U << dac_ch_cfg.resolution) / DIV; + + ret = dac_write_value(dac_dev, DT_PROP(DT_PATH(zephyr_user), dac_channel_id), write_val); + + zassert_equal(ret, 0, "dac_write_value() failed with code %d", ret); + + k_sleep(K_MSEC(10)); + + adc_sequence_init_dt(adc_channel, &sequence); + ret = adc_read_dt(adc_channel, &sequence); + + zassert_equal(ret, 0, "adc_read_dt() failed with code %d", ret); + zassert_within(sample_buffer, + (1U << adc_channel->resolution) / DIV, 32, + "Value %d read from ADC does not match expected range.", + sample_buffer); + + return TC_PASS; +} + +ZTEST(adc_accuracy_test, test_dac_to_adc) +{ + int i; + + for (i = 0; i < CONFIG_NUMBER_OF_PASSES; i++) { + zassert_true(test_dac_to_adc() == TC_PASS); + } +} diff --git a/tests/drivers/adc/adc_accuracy_test/src/main.c b/tests/drivers/adc/adc_accuracy_test/src/main.c new file mode 100644 index 00000000000..04fa08f70fb --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/src/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#if DT_NODE_HAS_PROP(DT_PATH(zephyr_user), io_channels) +static const struct adc_dt_spec adc_channel = ADC_DT_SPEC_GET(DT_PATH(zephyr_user)); +#else +#error "Unsupported board." +#endif + +const struct adc_dt_spec *get_adc_channel(void) +{ + return &adc_channel; +} + +static void *adc_setup(void) +{ + int ret; + + zassert_true(adc_is_ready_dt(&adc_channel), "ADC device is not ready"); + ret = adc_channel_setup_dt(&adc_channel); + zassert_equal(ret, 0, + "Setting up of the ADC channel failed with code %d", ret); + + return NULL; +} + +ZTEST_SUITE(adc_accuracy_test, NULL, adc_setup, NULL, NULL, NULL); diff --git a/tests/drivers/adc/adc_accuracy_test/src/ref_volt.c b/tests/drivers/adc/adc_accuracy_test/src/ref_volt.c new file mode 100644 index 00000000000..1c4806b249e --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/src/ref_volt.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#define REF_V DT_PROP(DT_PATH(zephyr_user), reference_mv) + +extern const struct adc_dt_spec *get_adc_channel(void); + +static int test_ref_to_adc(void) +{ + int ret; + int32_t sample_buffer = 0; + + struct adc_sequence sequence = { + .buffer = &sample_buffer, + .buffer_size = sizeof(sample_buffer), + }; + + const struct adc_dt_spec *adc_channel = get_adc_channel(); + + adc_sequence_init_dt(adc_channel, &sequence); + + ret = adc_read_dt(adc_channel, &sequence); + zassert_equal(ret, 0, "adc_read_dt() failed with code %d", ret); + + ret = adc_raw_to_millivolts_dt(adc_channel, &sample_buffer); + zassert_equal(ret, 0, "adc_raw_to_millivolts_dt() failed with code %d", + ret); + zassert_within(sample_buffer, REF_V, 32, + "Value %d mV read from ADC does not match expected range (%d mV).", + sample_buffer, REF_V); + + return TC_PASS; +} + +ZTEST(adc_accuracy_test, test_ref_to_adc) +{ + int i; + + for (i = 0; i < CONFIG_NUMBER_OF_PASSES; i++) { + zassert_true(test_ref_to_adc() == TC_PASS); + } +} diff --git a/tests/drivers/adc/adc_accuracy_test/testcase.yaml b/tests/drivers/adc/adc_accuracy_test/testcase.yaml new file mode 100644 index 00000000000..07bf2e50119 --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/testcase.yaml @@ -0,0 +1,19 @@ +common: + tags: + - adc + - drivers + depends_on: + - adc +tests: + drivers.adc.accuracy.dac_source: + depends_on: + - dac + harness_config: + fixture: dac_adc_loopback + platform_allow: + - frdm_k64f + drivers.adc.accuracy.ref_volt: + harness_config: + fixture: adc_ref_volt + platform_allow: + - frdm_kl25z From 5ffc76e626830e7c5d1eb1ddc9ed8cdf86b99360 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Mon, 25 Mar 2024 16:35:33 -0500 Subject: [PATCH 1401/2402] boards: nxp: frdm_mcxn947: fix debug access to secure RAM and peripherals By default, LinkServer's memory map for the MCXN947 does not define memory regions for the SRAM or peripheral bus in secure mode. This results in gdb failing to read from these memory regions unless explicitly told ignore the debugger memory map via "set mem inaccessible-by-default off". To resolve this, define memory regions for SRAM and peripherals in secure mode via the commandline arguments passed to LinkServer in board.cmake. Signed-off-by: Daniel DeGrasse --- boards/nxp/frdm_mcxn947/board.cmake | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/boards/nxp/frdm_mcxn947/board.cmake b/boards/nxp/frdm_mcxn947/board.cmake index 1eea0002274..ed9c7e01ee3 100644 --- a/boards/nxp/frdm_mcxn947/board.cmake +++ b/boards/nxp/frdm_mcxn947/board.cmake @@ -6,9 +6,18 @@ if(CONFIG_SOC_MCXN947_CPU0) board_runner_args(jlink "--device=MCXN947_M33_0" "--reset-after-load") - board_runner_args(linkserver "--device=MCXN947:MCX-N9XX-EVK:cm33_core0") + board_runner_args(linkserver "--device=MCXN947:FRDM-MCXN947:cm33_core0") board_runner_args(linkserver "--override=/device/memory/1/flash-driver=MCXN9xx_S.cfx") board_runner_args(linkserver "--override=/device/memory/1/location=0x10000000") + # Linkserver v1.4.85 and earlier do not include the secure regions in the + # MCXN947 memory map, so we add them here + board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30000000\",\ + \"size\":\"0x00060000\",\"type\":\"RAM\"\}") + board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30060000\",\ + \"size\":\"0x00008000\",\"type\":\"RAM\"\}") + # Define region for peripherals + board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\ + \"size\":\"0x00140000\",\"type\":\"RAM\"\}") else() message(FATAL_ERROR "Support for cpu1 not available yet") endif() From 35e15b522e4378d2c5d590566ab089f9c01d1d51 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Mon, 25 Mar 2024 16:48:54 -0500 Subject: [PATCH 1402/2402] boards: nxp: frdm_mcxn947: documentation fixes Correct a few issues with the documentation that were causing rendering issues, as well as the following changes: - added blurb to debug section clarifying that the default debugger firmware supports LinkServer - updated serial terminal output with board name given when building with HWMv2 Signed-off-by: Daniel DeGrasse --- boards/nxp/frdm_mcxn947/doc/index.rst | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index 1edcf7c6417..21b24ea188d 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -70,10 +70,10 @@ Targets available ================== The default configuration file -zephyr_file:`boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig` +:zephyr_file:`boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig` only enables the first core. -Other hardware features are not currently supported by the port.` +Other hardware features are not currently supported by the port. Connections and IOs =================== @@ -116,10 +116,12 @@ configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe. Using LinkServer ---------------- -Linkserver is the default runner for this board. Follow the instructions in -:ref:`mcu-link-cmsis-onboard-debug-probe` to progtam the MCU-Link firmware. -This only needs to be done if the default onboard debug circuit firmware was changed. -To put the board in ``DFU mode`` to program the firmware, short jumper J21. +Linkserver is the default runner for this board, and supports the factory +default MCU-Link firmware. Follow the instructions in +:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link +firmware. This only needs to be done if the default onboard debug circuit +firmware was changed. To put the board in ``DFU mode`` to program the firmware, +short jumper J21. Using J-Link ------------ @@ -164,7 +166,7 @@ see the following message in the terminal: .. code-block:: console *** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 *** - Hello World! frdm_mcxn947 + Hello World! frdm_mcxn947/mcxn947/cpu0 Debugging ========= @@ -182,7 +184,7 @@ should see the following message in the terminal: .. code-block:: console *** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 *** - Hello World! frdm_mcxn947 + Hello World! frdm_mcxn947/mcxn947/cpu0 .. _MCX-N947 SoC Website: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n94x-54x-highly-integrated-multicore-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N94X-N54X From 9fb8d511e1c18c12eabe3f17555bd6e3af62b4bb Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 22 Mar 2024 16:15:04 +0200 Subject: [PATCH 1403/2402] net: if: Set default interface name if needed If the driver does not set the interface name, then set a default name for it. Signed-off-by: Jukka Rissanen --- subsys/net/ip/net_if.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 36acfcb50f6..535da28bdc0 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -5244,14 +5244,20 @@ void net_if_init(void) net_tc_tx_init(); STRUCT_SECTION_FOREACH(net_if, iface) { - - init_iface(iface); - #if defined(CONFIG_NET_INTERFACE_NAME) memset(net_if_get_config(iface)->name, 0, sizeof(iface->config.name)); +#endif - set_default_name(iface); + init_iface(iface); + +#if defined(CONFIG_NET_INTERFACE_NAME) + /* If the driver did not set the name, then set + * a default name for the network interface. + */ + if (net_if_get_config(iface)->name[0] == '\0') { + set_default_name(iface); + } #endif if_count++; From 8d7982cde2c7b005c7896de6d3cea45ceac4a6b2 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 22 Mar 2024 12:46:03 +0100 Subject: [PATCH 1404/2402] MAINTAINERS: Tweak nRF BSIM filters The exclusion filter for bsim tests is currently too broad. There is "infrastructure" files inside these folders (not just in the top level folder) and users may add more. So let's change the filter to exclude tests source, cmake and kconfig files, but catch the rest. Also the documentation for the tests and workflows were missing. Signed-off-by: Alberto Escolar Piedras --- MAINTAINERS.yml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index d1221a734fe..36c22687aec 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2807,8 +2807,11 @@ nRF BSIM: - boards/native/nrf_bsim/ - tests/boards/nrf52_bsim/ - tests/bsim/ - files-exclude: - - tests/bsim/*/ + - doc/develop/test/bsim.rst + - .github/workflows/bsim-tests* + files-regex-exclude: + - tests\/bsim\/.*\/.*\.([ch]|conf) + - tests\/bsim\/.*\/(CMakeLists|Kconfig).* labels: - "platform: nRF BSIM" tests: From 2a4332ba5fc97d0f62459cb4ac13e9d7b674f265 Mon Sep 17 00:00:00 2001 From: Kamil Paszkiet Date: Thu, 21 Mar 2024 14:43:21 +0100 Subject: [PATCH 1405/2402] scripts: tests: Blackbox test expansion - error Adds tests related to filter flags: --overflow-as-errors Signed-off-by: Kamil Paszkiet --- .../tests/qemu_overflow/dummy/CMakeLists.txt | 8 ++++ .../tests/qemu_overflow/dummy/prj.conf | 1 + .../qemu_overflow/dummy/qemu_x86.overlay | 3 ++ .../tests/qemu_overflow/dummy/src/main.c | 26 ++++++++++ .../tests/qemu_overflow/dummy/test_data.yaml | 8 ++++ scripts/tests/twister_blackbox/test_error.py | 48 +++++++++++++++++++ 6 files changed, 94 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/qemu_x86.overlay create mode 100644 scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/test_data.yaml diff --git a/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/CMakeLists.txt new file mode 100644 index 00000000000..635c696edf9 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(integration) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/prj.conf new file mode 100644 index 00000000000..9467c292689 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/qemu_x86.overlay b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/qemu_x86.overlay new file mode 100644 index 00000000000..1908ef8a6d9 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/qemu_x86.overlay @@ -0,0 +1,3 @@ +&dram0 { + reg = < 0x100000 DT_SIZE_M(1) >; +}; diff --git a/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/src/main.c new file mode 100644 index 00000000000..a2b7268225b --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/src/main.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + + +ZTEST_SUITE(a1_1_tests, NULL, NULL, NULL, NULL, NULL); + +/** + * @brief Test Asserts + * + * This test verifies various assert macros provided by ztest. + * + */ +ZTEST(a1_1_tests, test_assert) +{ + zassert_true(1, "1 was false"); + zassert_false(0, "0 was true"); + zassert_is_null(NULL, "NULL was not NULL"); + zassert_not_null("foo", "\"foo\" was NULL"); + zassert_equal(1, 1, "1 was not equal to 1"); + zassert_equal_ptr(NULL, NULL, "NULL was not equal to NULL"); +} diff --git a/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/test_data.yaml new file mode 100644 index 00000000000..2a773945d70 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/qemu_overflow/dummy/test_data.yaml @@ -0,0 +1,8 @@ +tests: + always_overflow.dummy: + platform_allow: + - native_posix + - qemu_x86 + - qemu_x86_64 + integration_platforms: + - native_posix diff --git a/scripts/tests/twister_blackbox/test_error.py b/scripts/tests/twister_blackbox/test_error.py index e5b3d428ed5..c6c8f78e8ed 100644 --- a/scripts/tests/twister_blackbox/test_error.py +++ b/scripts/tests/twister_blackbox/test_error.py @@ -11,6 +11,7 @@ import os import pytest import sys +import re from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock from twisterlib.testplan import TestPlan @@ -37,6 +38,16 @@ class TestError: SystemExit ) ] + TESTDATA_2 = [ + ( + '', + r'always_overflow.dummy SKIPPED \(RAM overflow\)' + ), + ( + '--overflow-as-errors', + r'always_overflow.dummy ERROR Build failure \(build\)' + ) + ] @classmethod def setup_class(cls): @@ -72,3 +83,40 @@ def test_test(self, out_path, testroot, test, expected_exception): if expected_exception == SystemExit: assert str(exc.value) == '0' assert True + + @pytest.mark.parametrize( + 'switch, expected', + TESTDATA_2, + ids=[ + 'overflow skip', + 'overflow error', + ], + ) + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_overflow_as_errors(self, capfd, out_path, switch, expected): + path = os.path.join(TEST_DATA, 'tests', 'qemu_overflow') + test_platforms = ['qemu_x86'] + args = ['--outdir', out_path, '-T', path, '-vv'] + \ + ['--build-only'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + if switch: + args += [switch] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + print(args) + if switch: + assert str(sys_exit.value) == '1' + else: + assert str(sys_exit.value) == '0' + + assert re.search(expected, err) From b1b4dc069427884e80ca509565e4366196ee7b00 Mon Sep 17 00:00:00 2001 From: Bartosz Sokolski Date: Thu, 21 Mar 2024 10:00:31 +0100 Subject: [PATCH 1406/2402] boards: nrf54l15pdk_nrf54l15_cpuapp: add support for PDK 0.3.0 Add support for the PDK 0.3.0 Signed-off-by: Bartosz Sokolski --- boards/nordic/nrf54l15pdk/board.yml | 6 +++ .../nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay | 38 +++++++++++++++++++ boards/nordic/nrf54l15pdk/revision.cmake | 9 ----- 3 files changed, 44 insertions(+), 9 deletions(-) create mode 100644 boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay delete mode 100644 boards/nordic/nrf54l15pdk/revision.cmake diff --git a/boards/nordic/nrf54l15pdk/board.yml b/boards/nordic/nrf54l15pdk/board.yml index b33ecf7c4f6..3b0fc447385 100644 --- a/boards/nordic/nrf54l15pdk/board.yml +++ b/boards/nordic/nrf54l15pdk/board.yml @@ -3,3 +3,9 @@ board: vendor: nordic socs: - name: nrf54l15 + revision: + format: major.minor.patch + default: "0.2.1" + revisions: + - name: "0.2.1" + - name: "0.3.0" diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay new file mode 100644 index 00000000000..d8262dde994 --- /dev/null +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_3_0.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +&led0 { + gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; +}; + +&led1 { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; +}; + +&led2 { + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; +}; + +&led3 { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; +}; + +&button0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; +}; + +&button1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; +}; + +&button2 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; +}; + +&button3 { + gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; +}; diff --git a/boards/nordic/nrf54l15pdk/revision.cmake b/boards/nordic/nrf54l15pdk/revision.cmake deleted file mode 100644 index 4fe5b260db3..00000000000 --- a/boards/nordic/nrf54l15pdk/revision.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2024 Nordic Semiconductor ASA -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_check_revision(FORMAT MAJOR.MINOR.PATCH - VALID_REVISIONS 0.2.0 - DEFAULT_REVISION 0.2.0) From 8256d02d3a9625c03e1d584cf54b1f0cc1ae164b Mon Sep 17 00:00:00 2001 From: Ravi Dondaputi Date: Sun, 10 Mar 2024 23:33:41 +0530 Subject: [PATCH 1407/2402] net: wifi: shell: Use getopt API for connect options Use getopt API to process the arguments passed with connect command. Signed-off-by: Ravi Dondaputi --- subsys/net/l2/wifi/wifi_shell.c | 204 ++++++++++++++------------------ 1 file changed, 90 insertions(+), 114 deletions(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 1eb1c7d1947..eb4268856cc 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -442,73 +442,69 @@ static void wifi_mgmt_event_handler(struct net_mgmt_event_callback *cb, } } -static int __wifi_args_to_params(size_t argc, char *argv[], +static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv[], struct wifi_connect_req_params *params, enum wifi_iface_mode iface_mode) { char *endptr; int idx = 1; - const struct shell *sh = context.sh; + struct getopt_state *state; + int opt; + bool secure_connection = false; + static struct option long_options[] = {{"ssid", required_argument, 0, 's'}, + {"passphrase", required_argument, 0, 'p'}, + {"key-mgmt", required_argument, 0, 'k'}, + {"ieee-80211w", required_argument, 0, 'w'}, + {"bssid", required_argument, 0, 'm'}, + {"band", required_argument, 0, 'b'}, + {"channel", required_argument, 0, 'c'}, + {"help", no_argument, 0, 'h'}, + {0, 0, 0, 0}}; + int opt_index = 0; + uint8_t band; + const uint8_t all_bands[] = { + WIFI_FREQ_BAND_2_4_GHZ, + WIFI_FREQ_BAND_5_GHZ, + WIFI_FREQ_BAND_6_GHZ + }; + bool found = false; + char bands_str[MAX_BANDS_STR_LEN] = {0}; + size_t offset = 0; /* Defaults */ params->band = WIFI_FREQ_BAND_UNKNOWN; params->channel = WIFI_CHANNEL_ANY; params->security = WIFI_SECURITY_TYPE_NONE; + params->mfp = WIFI_MFP_OPTIONAL; - /* SSID */ - params->ssid = argv[0]; - params->ssid_length = strlen(params->ssid); - if (params->ssid_length > WIFI_SSID_MAX_LEN) { - PR_WARNING("SSID too long (max %d characters)\n", - WIFI_SSID_MAX_LEN); - return -EINVAL; - } - - /* Channel (optional: STA, mandatory: AP) */ - if ((idx < argc) && (strlen(argv[idx]) <= 3)) { - uint8_t band; - long channel = strtol(argv[idx], &endptr, 10); - const uint8_t all_bands[] = {WIFI_FREQ_BAND_2_4_GHZ, - WIFI_FREQ_BAND_5_GHZ, - WIFI_FREQ_BAND_6_GHZ}; - bool found = false; - char bands_str[MAX_BANDS_STR_LEN] = {0}; - size_t offset = 0; - - if (*endptr != '\0') { - PR_ERROR("Failed to parse channel: %s: endp: %s, err: %s\n", - argv[idx], - endptr, - strerror(errno)); - return -EINVAL; - } - - if (iface_mode == WIFI_MODE_INFRA) { - if (channel < 0) { - /* Negative channel means band */ - switch (-channel) { - case 2: - params->band = WIFI_FREQ_BAND_2_4_GHZ; - break; - case 5: - params->band = WIFI_FREQ_BAND_5_GHZ; - break; - case 6: - params->band = WIFI_FREQ_BAND_6_GHZ; - break; - default: - PR_ERROR("Invalid band: %ld\n", channel); - return -EINVAL; - } - } - } else { - if (channel < 0) { - PR_ERROR("Invalid channel: %ld\n", channel); + while ((opt = getopt_long(argc, argv, "s:p:k:w:b:c:h", long_options, &opt_index)) != -1) { + state = getopt_state_get(); + switch (opt) { + case 's': + params->ssid = optarg; + params->ssid_length = strlen(params->ssid); + if (params->ssid_length > WIFI_SSID_MAX_LEN) { + PR_WARNING("SSID too long (max %d characters)\n", + WIFI_SSID_MAX_LEN); return -EINVAL; } - } - - if (channel > 0) { + break; + case 'k': + params->security = atoi(optarg); + if (params->security) { + secure_connection = true; + } + break; + case 'p': + if (secure_connection) { + params->psk = optarg; + params->psk_length = strlen(params->psk); + } else { + PR_WARNING("Passphrase provided without security configuration\n"); + } + break; + case 'c': + long channel = strtol(optarg, &endptr, 10); for (band = 0; band < ARRAY_SIZE(all_bands); band++) { offset += snprintf(bands_str + offset, sizeof(bands_str) - offset, @@ -537,63 +533,43 @@ static int __wifi_args_to_params(size_t argc, char *argv[], } params->channel = channel; - } - idx++; - } - - if ((idx == 1) && (iface_mode == WIFI_MODE_AP)) { - PR_ERROR("Invalid channel: %s\n", argv[idx]); - return -EINVAL; - } - - /* PSK (optional) */ - if (idx < argc) { - params->psk = argv[idx]; - params->psk_length = strlen(argv[idx]); - /* Defaults */ - params->security = WIFI_SECURITY_TYPE_PSK; - params->mfp = WIFI_MFP_OPTIONAL; - idx++; - - /* Security type (optional) */ - if (idx < argc) { - unsigned int security = strtol(argv[idx], &endptr, 10); - - if (security <= WIFI_SECURITY_TYPE_MAX) { - params->security = security; - } - idx++; - - /* MFP (optional) */ - if (idx < argc) { - unsigned int mfp = strtol(argv[idx], &endptr, 10); - - if (security == WIFI_SECURITY_TYPE_NONE || - security == WIFI_SECURITY_TYPE_WPA_PSK) { - PR_ERROR("MFP not supported for security type %s\n", - wifi_security_txt(security)); + break; + case 'b': + if (iface_mode == WIFI_MODE_INFRA) { + switch (atoi(optarg)) { + case 2: + params->band = WIFI_FREQ_BAND_2_4_GHZ; + break; + case 5: + params->band = WIFI_FREQ_BAND_5_GHZ; + break; + case 6: + params->band = WIFI_FREQ_BAND_6_GHZ; + break; + default: + PR_ERROR("Invalid band: %d\n", atoi(optarg)); return -EINVAL; } - - if (mfp <= WIFI_MFP_REQUIRED) { - params->mfp = mfp; - } - idx++; } - } - - if (params->psk_length < WIFI_PSK_MIN_LEN || - (params->security != WIFI_SECURITY_TYPE_SAE && - params->psk_length > WIFI_PSK_MAX_LEN) || - (params->security == WIFI_SECURITY_TYPE_SAE && - params->psk_length > WIFI_SAE_PSWD_MAX_LEN)) { - PR_ERROR("Invalid PSK length (%d) for security type %s\n", - params->psk_length, - wifi_security_txt(params->security)); + break; + case 'w': + if (params->security == WIFI_SECURITY_TYPE_NONE || + params->security == WIFI_SECURITY_TYPE_WPA_PSK) { + PR_ERROR("MFP not supported for security type %s\n", + wifi_security_txt(params->security)); + return -EINVAL; + } + params->mfp = atoi(optarg); + break; + case 'h': + shell_help(sh); + break; + default: + PR_ERROR("Invalid option %c\n", opt); + shell_help(sh); return -EINVAL; } } - return 0; } @@ -604,7 +580,7 @@ static int cmd_wifi_connect(const struct shell *sh, size_t argc, struct wifi_connect_req_params cnx_params = { 0 }; context.sh = sh; - if (__wifi_args_to_params(argc - 1, &argv[1], &cnx_params, WIFI_MODE_INFRA)) { + if (__wifi_args_to_params(sh, argc, argv, &cnx_params, WIFI_MODE_INFRA)) { shell_help(sh); return -ENOEXEC; } @@ -1259,7 +1235,7 @@ static int cmd_wifi_ap_enable(const struct shell *sh, size_t argc, int ret; context.sh = sh; - if (__wifi_args_to_params(argc - 1, &argv[1], &cnx_params, WIFI_MODE_AP)) { + if (__wifi_args_to_params(sh, argc - 1, &argv[1], &cnx_params, WIFI_MODE_AP)) { shell_help(sh); return -ENOEXEC; } @@ -1875,16 +1851,16 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_commands, SHELL_CMD(ap, &wifi_cmd_ap, "Access Point mode commands.\n", NULL), SHELL_CMD_ARG(connect, NULL, "Connect to a Wi-Fi AP\n" - "\"\"\n" - "[channel number/band: > 0:Channel, 0:any channel,\n" - "< 0:band (-2:2.4GHz, -5:5GHz, -6:6GHz]\n" - "[PSK: valid only for secure SSIDs]\n" - "[Security type: valid only for secure SSIDs]\n" + "<-s --ssid \"\">: SSID.\n" + "[-c --channel]: Channel that needs to be scanned for connection. 0:any channel.\n" + "[-b, --band] 0: any band (2:2.4GHz, 5:5GHz, 6:6GHz]\n" + "[-p, --psk]: Passphrase (valid only for secure SSIDs)\n" + "[-k, --key-mgmt]: Key Management type (valid only for secure SSIDs)\n" "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP, 7: WPA-PSK\n" - "[MFP (optional: needs security type to be specified)]\n" + "[-w, --ieee-80211w]: MFP (optional: needs security type to be specified)\n" ": 0:Disable, 1:Optional, 2:Required.\n", cmd_wifi_connect, - 2, 4), + 2, 5), SHELL_CMD_ARG(disconnect, NULL, "Disconnect from the Wi-Fi AP.\n", cmd_wifi_disconnect, 1, 0), From 73ed81cccee9840626c3b93fa141c1442df452c1 Mon Sep 17 00:00:00 2001 From: Ravi Dondaputi Date: Mon, 11 Mar 2024 13:00:26 +0530 Subject: [PATCH 1408/2402] net: wifi: shell: Support BSSID configuration Add support for BSSID configuration in connect call. Signed-off-by: Ravi Dondaputi --- include/zephyr/net/wifi_mgmt.h | 2 ++ subsys/net/l2/wifi/wifi_shell.c | 15 ++++++++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h index e0930d2f106..2bf7e3ed4bf 100644 --- a/include/zephyr/net/wifi_mgmt.h +++ b/include/zephyr/net/wifi_mgmt.h @@ -359,6 +359,8 @@ struct wifi_connect_req_params { enum wifi_security_type security; /** MFP options */ enum wifi_mfp_options mfp; + /** BSSID */ + uint8_t bssid[WIFI_MAC_ADDR_LEN]; /** Connect timeout in seconds, SYS_FOREVER_MS for no timeout */ int timeout; }; diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index eb4268856cc..7e6943c85f7 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -477,7 +477,7 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv params->security = WIFI_SECURITY_TYPE_NONE; params->mfp = WIFI_MFP_OPTIONAL; - while ((opt = getopt_long(argc, argv, "s:p:k:w:b:c:h", long_options, &opt_index)) != -1) { + while ((opt = getopt_long(argc, argv, "s:p:k:w:b:c:m:h", long_options, &opt_index)) != -1) { state = getopt_state_get(); switch (opt) { case 's': @@ -561,6 +561,12 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv } params->mfp = atoi(optarg); break; + case 'm': + sscanf(optarg, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + ¶ms->bssid[0], ¶ms->bssid[1], + ¶ms->bssid[2], ¶ms->bssid[3], + ¶ms->bssid[4], ¶ms->bssid[5]); + break; case 'h': shell_help(sh); break; @@ -570,6 +576,7 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv return -EINVAL; } } + return 0; } @@ -1858,9 +1865,11 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_commands, "[-k, --key-mgmt]: Key Management type (valid only for secure SSIDs)\n" "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP, 6:WEP, 7: WPA-PSK\n" "[-w, --ieee-80211w]: MFP (optional: needs security type to be specified)\n" - ": 0:Disable, 1:Optional, 2:Required.\n", + ": 0:Disable, 1:Optional, 2:Required.\n" + "[-m, --bssid]: MAC address of the AP (BSSID).\n" + "[-h, --help]: Print out the help for the connect command.\n", cmd_wifi_connect, - 2, 5), + 2, 7), SHELL_CMD_ARG(disconnect, NULL, "Disconnect from the Wi-Fi AP.\n", cmd_wifi_disconnect, 1, 0), From cdd929ff33258779e25ea25af627ced175e682bc Mon Sep 17 00:00:00 2001 From: Ravi Dondaputi Date: Mon, 11 Mar 2024 17:09:18 +0530 Subject: [PATCH 1409/2402] doc: migration-guide-3.7: Add wifi shell connect cmd info Make note of the modifications done to Wi-Fi connect command in Wi-Fi shell. Signed-off-by: Ravi Dondaputi --- doc/releases/migration-guide-3.7.rst | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index b1be808035a..ab7ff0ef785 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -185,6 +185,14 @@ Networking used to read the inner IPv4/IPv6 packets in an IP tunnel. This incoming tunnel read is now implemented in `recv` callback. (:github:`70549`) +* Modified the ``wifi connect`` command to use key-value format for the arguments. In the + previous implementation, we were identifying an option using its position in the argument string. + This made it difficult to deal with optional arguments or extending the support + for other options. Having this key-value format makes it easier to extend the options that + can be passed to the connect command. + ``wifi -h`` will give more information about the usage of connect command. + (:github:`70024`) + Other Subsystems **************** From 2e3f8a5f984181794802f617ac15e9b7812820f5 Mon Sep 17 00:00:00 2001 From: Jordan Yates Date: Sun, 3 Dec 2023 21:43:29 +1000 Subject: [PATCH 1410/2402] doc: _extensions: support `snippets` option Support `zephyr-app-commands` being provided with a `snippets`, option, to specify building with the listed snippets. Signed-off-by: Jordan Yates --- doc/_extensions/zephyr/application.py | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/doc/_extensions/zephyr/application.py b/doc/_extensions/zephyr/application.py index 5e012b43aa2..f5807859bae 100644 --- a/doc/_extensions/zephyr/application.py +++ b/doc/_extensions/zephyr/application.py @@ -69,6 +69,10 @@ class ZephyrAppCommandsDirective(Directive): \:build-args: if set, additional arguments to the build invocation + \:snippets: + if set, indicates the application should be compiled with the listed snippets. + Multiple snippets can be provided in a comma separated list. + \:build-dir: if set, the application build directory will *APPEND* this (relative, Unix-separated) path to the standard build directory. This is @@ -116,6 +120,7 @@ class ZephyrAppCommandsDirective(Directive): 'conf': directives.unchanged, 'gen-args': directives.unchanged, 'build-args': directives.unchanged, + 'snippets': directives.unchanged, 'build-dir': directives.unchanged, 'build-dir-fmt': directives.unchanged, 'goals': directives.unchanged_required, @@ -147,6 +152,7 @@ def run(self): conf = self.options.get('conf', None) gen_args = self.options.get('gen-args', None) build_args = self.options.get('build-args', None) + snippets = self.options.get('snippets', None) build_dir_append = self.options.get('build-dir', '').strip('/') build_dir_fmt = self.options.get('build-dir-fmt', None) goals = self.options.get('goals').split() @@ -190,6 +196,10 @@ def run(self): # Create tools array tools = [tool] if tool != "all" else [v for v in self.TOOLS if v != 'all'] + + # Create snippet array + snippet_list = snippets.split(',') if snippets is not None else None + # Build the command content as a list, then convert to string. content = [] tool_comment = None @@ -206,6 +216,7 @@ def run(self): 'conf': conf, 'gen_args': gen_args, 'build_args': build_args, + 'snippets': snippet_list, 'build_dir': build_dir, 'build_dir_fmt': build_dir_fmt, 'goals': goals, @@ -263,6 +274,7 @@ def _generate_west(self, **kwargs): build_dir = kwargs['build_dir'] build_dir_fmt = kwargs['build_dir_fmt'] compact = kwargs['compact'] + snippets = kwargs['snippets'] west_args = kwargs['west_args'] flash_args = kwargs['flash_args'] kwargs['board'] = None @@ -272,6 +284,7 @@ def _generate_west(self, **kwargs): cmake_args = ' --{}'.format(cmake_args) if cmake_args != '' else '' west_args = ' {}'.format(west_args) if west_args else '' flash_args = ' {}'.format(flash_args) if flash_args else '' + snippet_args = ''.join(f' -S {s}' for s in snippets) if snippets else '' # ignore zephyr_app since west needs to run within # the installation. Instead rely on relative path. src = ' {}'.format(app) if app and not cd_into else '' @@ -301,8 +314,8 @@ def _generate_west(self, **kwargs): # defaulting to west. # # For now, this keeps the resulting commands working. - content.append('west build -b {}{}{}{}{}'. - format(board, west_args, build_dst, src, cmake_args)) + content.append('west build -b {}{}{}{}{}{}'. + format(board, west_args, snippet_args, build_dst, src, cmake_args)) # If we're signing, we want to do that next, so that flashing # etc. commands can use the signed file which must be created @@ -397,6 +410,7 @@ def _generate_cmake(self, **kwargs): in_tree = kwargs['in_tree'] build_dir = kwargs['build_dir'] build_args = kwargs['build_args'] + snippets = kwargs['snippets'] skip_config = kwargs['skip_config'] goals = kwargs['goals'] compact = kwargs['compact'] @@ -422,6 +436,7 @@ def _generate_cmake(self, **kwargs): # Now generate the actual cmake and make/ninja commands gen_arg = ' -GNinja' if generator == 'ninja' else '' build_args = ' {}'.format(build_args) if build_args else '' + snippet_args = ' -DSNIPPET="{}"'.format(';'.join(snippets)) if snippets else '' cmake_args = self._cmake_args(**kwargs) if not compact: @@ -433,8 +448,8 @@ def _generate_cmake(self, **kwargs): content.append('# Use cmake to configure a {}-based build' \ 'system:'.format(generator.capitalize())) # noqa: E501 - content.append('cmake{}{}{}{}'.format(cmake_build_dir, gen_arg, - cmake_args, source_dir)) + content.append('cmake{}{}{}{}{}'.format(cmake_build_dir, gen_arg, + cmake_args, snippet_args, source_dir)) if not compact: content.extend(['', '# Now run the build tool on the generated build system:']) From 8a54236d0ba6956df3913f1c886de856557a6e22 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Mon, 5 Feb 2024 12:59:50 +0000 Subject: [PATCH 1411/2402] scripts: tests: Blackbox test expansion - tooling Adds tests related to the Twister tooling: * -j, --jobs * --force-toolchain Signed-off-by: Lukasz Mrugala --- .../tests/twister_blackbox/test_tooling.py | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_tooling.py diff --git a/scripts/tests/twister_blackbox/test_tooling.py b/scripts/tests/twister_blackbox/test_tooling.py new file mode 100644 index 00000000000..67b5b3b0030 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_tooling.py @@ -0,0 +1,86 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions related to Twister's tooling. +""" +# pylint: disable=duplicate-code + +import importlib +import mock +import os +import pytest +import sys +import json + +from conftest import ZEPHYR_BASE, TEST_DATA, sample_filename_mock, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +class TestTooling: + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @pytest.mark.parametrize( + 'jobs', + ['1', '2'], + ids=['single job', 'two jobs'] + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_jobs(self, out_path, jobs): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2') + args = ['-i', '--outdir', out_path, '-T', path] + \ + ['--jobs', jobs] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + with open(os.path.join(out_path, 'twister.log')) as f: + log = f.read() + assert f'JOBS: {jobs}' in log + + assert str(sys_exit.value) == '0' + + @mock.patch.object(TestPlan, 'SAMPLE_FILENAME', sample_filename_mock) + def test_force_toolchain(self, out_path): + # nsim_vpx5 is one of the rare platforms that do not support the zephyr toolchain + test_platforms = ['nsim/nsim_vpx5'] + path = os.path.join(TEST_DATA, 'samples', 'hello_world') + args = ['-i', '--outdir', out_path, '-T', path, '-y'] + \ + ['--force-toolchain'] + \ + [] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier'], tc['status']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] + ] + + # Normally, board not supporting our toolchain would be filtered, so we check against that + assert len(filtered_j) == 1 + assert filtered_j[0][3] != 'filtered' From fd063d6ae5858319a088531ac3b26f166a80f867 Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Mon, 5 Feb 2024 13:02:34 +0000 Subject: [PATCH 1412/2402] scripts: tests: Move --ninja test to test_tooling Brings the previously-created --ninja test to its test section file. Signed-off-by: Lukasz Mrugala --- scripts/tests/twister_blackbox/test_runner.py | 27 --------------- .../tests/twister_blackbox/test_tooling.py | 33 +++++++++++++++++++ 2 files changed, 33 insertions(+), 27 deletions(-) diff --git a/scripts/tests/twister_blackbox/test_runner.py b/scripts/tests/twister_blackbox/test_runner.py index acfaf540b8f..80025ae7b9d 100644 --- a/scripts/tests/twister_blackbox/test_runner.py +++ b/scripts/tests/twister_blackbox/test_runner.py @@ -477,33 +477,6 @@ def test_runtest_only(self, capfd, out_path, test_path, test_platforms, expected assert str(sys_exit.value) == '0' - @pytest.mark.parametrize( - 'test_path, test_platforms', - TESTDATA_4, - ids=[ - 'ninja', - ] - ) - @pytest.mark.parametrize( - 'flag', - ['--ninja', '-N'] - ) - def test_ninja(self, capfd, out_path, test_path, test_platforms, flag): - args = ['--outdir', out_path, '-T', test_path, flag] + \ - [val for pair in zip( - ['-p'] * len(test_platforms), test_platforms - ) for val in pair] - - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) - - out, err = capfd.readouterr() - sys.stdout.write(out) - sys.stderr.write(err) - - assert str(sys_exit.value) == '0' - @pytest.mark.parametrize( 'test_path, test_platforms', TESTDATA_4, diff --git a/scripts/tests/twister_blackbox/test_tooling.py b/scripts/tests/twister_blackbox/test_tooling.py index 67b5b3b0030..5966b3c3089 100644 --- a/scripts/tests/twister_blackbox/test_tooling.py +++ b/scripts/tests/twister_blackbox/test_tooling.py @@ -84,3 +84,36 @@ def test_force_toolchain(self, out_path): # Normally, board not supporting our toolchain would be filtered, so we check against that assert len(filtered_j) == 1 assert filtered_j[0][3] != 'filtered' + + @pytest.mark.parametrize( + 'test_path, test_platforms', + [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), + ['qemu_x86'], + ) + ], + ids=[ + 'ninja', + ] + ) + @pytest.mark.parametrize( + 'flag', + ['--ninja', '-N'] + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_ninja(self, capfd, out_path, test_path, test_platforms, flag): + args = ['--outdir', out_path, '-T', test_path, flag] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == '0' From 03d234d593f0f91fcdfb77efb57727f41375ce11 Mon Sep 17 00:00:00 2001 From: Aleksander Wasaznik Date: Thu, 21 Mar 2024 15:14:04 +0100 Subject: [PATCH 1413/2402] Bluetooth: tests: hfc: Avoid reconnecting too fast The host refuses to connect to a peer with an address that is also used by a connection object in disconnected state. Add a guard to prevent `-EINVAL` from `bt_conn_le_create`. Signed-off-by: Aleksander Wasaznik --- tests/bsim/bluetooth/host/misc/hfc/src/main.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tests/bsim/bluetooth/host/misc/hfc/src/main.c b/tests/bsim/bluetooth/host/misc/hfc/src/main.c index a3ab3840971..15e27779170 100644 --- a/tests/bsim/bluetooth/host/misc/hfc/src/main.c +++ b/tests/bsim/bluetooth/host/misc/hfc/src/main.c @@ -81,6 +81,13 @@ static void device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t type, struct bt_conn *conn; int err; + conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, addr); + if (conn) { + LOG_DBG("Old connection is not yet purged"); + bt_conn_unref(conn); + return; + } + err = bt_le_scan_stop(); if (err) { FAIL("Stop LE scan failed (err %d)", err); From b91728619c050ccd6557be61f83d69af9d7f36b6 Mon Sep 17 00:00:00 2001 From: Aleksander Wasaznik Date: Wed, 20 Mar 2024 14:44:07 +0100 Subject: [PATCH 1414/2402] Bluetooth: host: remove `CONFIG_BT_RECV_BLOCKING` This config selects a variant of the HCI driver interface that spills out host internals unto the drivers and even the Zephyr controller. It will now be removed in favor of driver interfaces that hide the internals of the host. The new default is `CONFIG_BT_RECV_WORKQ_BT`. Any references to the removed kconfig are refactored out. Any out-of-tree driver using the removed interface can be easily adapted by copying the following implementations into the driver as private functions: - `hci_driver.h:BT_HCI_EVT_FLAG_RECV_PRIO` - `hci_driver.h:BT_HCI_EVT_FLAG_RECV` - `hci_driver.h:bt_hci_evt_get_flags` - `hci_raw.c:bt_recv_prio` In combination these symbols function as a interface adapter. These symbols will be removed in this PR in subsequent commits. Signed-off-by: Aleksander Wasaznik --- drivers/bluetooth/hci/h4.c | 16 ++------- drivers/bluetooth/hci/slz_hci.c | 9 +---- include/zephyr/drivers/bluetooth/hci_driver.h | 15 --------- subsys/bluetooth/common/Kconfig | 2 -- subsys/bluetooth/controller/hci/hci_driver.c | 8 ++--- subsys/bluetooth/host/Kconfig | 9 +---- subsys/bluetooth/host/hci_core.c | 33 +------------------ subsys/bluetooth/host/hci_core.h | 2 -- subsys/bluetooth/host/hci_ecc.c | 6 +--- .../host/misc/conn_stress/central/prj.conf | 3 -- 10 files changed, 9 insertions(+), 94 deletions(-) diff --git a/drivers/bluetooth/hci/h4.c b/drivers/bluetooth/hci/h4.c index 288e920141e..96a27f19a75 100644 --- a/drivers/bluetooth/hci/h4.c +++ b/drivers/bluetooth/hci/h4.c @@ -278,7 +278,6 @@ static size_t h4_discard(const struct device *uart, size_t len) static inline void read_payload(void) { struct net_buf *buf; - uint8_t evt_flags; int read; if (!rx.buf) { @@ -331,26 +330,15 @@ static inline void read_payload(void) rx.buf = NULL; if (rx.type == H4_EVT) { - evt_flags = bt_hci_evt_get_flags(rx.evt.evt); bt_buf_set_type(buf, BT_BUF_EVT); } else { - evt_flags = BT_HCI_EVT_FLAG_RECV; bt_buf_set_type(buf, BT_BUF_ACL_IN); } reset_rx(); - if (IS_ENABLED(CONFIG_BT_RECV_BLOCKING) && - (evt_flags & BT_HCI_EVT_FLAG_RECV_PRIO)) { - LOG_DBG("Calling bt_recv_prio(%p)", buf); - bt_recv_prio(buf); - } - - if ((evt_flags & BT_HCI_EVT_FLAG_RECV) || - !IS_ENABLED(CONFIG_BT_RECV_BLOCKING)) { - LOG_DBG("Putting buf %p to rx fifo", buf); - net_buf_put(&rx.fifo, buf); - } + LOG_DBG("Putting buf %p to rx fifo", buf); + net_buf_put(&rx.fifo, buf); } static inline void read_header(void) diff --git a/drivers/bluetooth/hci/slz_hci.c b/drivers/bluetooth/hci/slz_hci.c index 0526cb02c40..a3daf334607 100644 --- a/drivers/bluetooth/hci/slz_hci.c +++ b/drivers/bluetooth/hci/slz_hci.c @@ -55,7 +55,6 @@ uint32_t hci_common_transport_transmit(uint8_t *data, int16_t len) { struct net_buf *buf; uint8_t packet_type = data[0]; - uint8_t flags; uint8_t event_code; LOG_HEXDUMP_DBG(data, len, "host packet data:"); @@ -67,7 +66,6 @@ uint32_t hci_common_transport_transmit(uint8_t *data, int16_t len) switch (packet_type) { case h4_event: event_code = data[0]; - flags = bt_hci_evt_get_flags(event_code); buf = bt_buf_get_evt(event_code, false, K_FOREVER); break; case h4_acl: @@ -79,12 +77,7 @@ uint32_t hci_common_transport_transmit(uint8_t *data, int16_t len) } net_buf_add_mem(buf, data, len); - if (IS_ENABLED(CONFIG_BT_RECV_BLOCKING) && - (packet_type == h4_event) && (flags & BT_HCI_EVT_FLAG_RECV_PRIO)) { - bt_recv_prio(buf); - } else { - bt_recv(buf); - } + bt_recv(buf); sl_btctrl_hci_transmit_complete(0); diff --git a/include/zephyr/drivers/bluetooth/hci_driver.h b/include/zephyr/drivers/bluetooth/hci_driver.h index e8a26b2cb94..3682ebce009 100644 --- a/include/zephyr/drivers/bluetooth/hci_driver.h +++ b/include/zephyr/drivers/bluetooth/hci_driver.h @@ -49,10 +49,6 @@ enum { * Helper for the HCI driver to get HCI event flags that describes rules that. * must be followed. * - * When @kconfig{CONFIG_BT_RECV_BLOCKING} is enabled the flags - * BT_HCI_EVT_FLAG_RECV and BT_HCI_EVT_FLAG_RECV_PRIO indicates if the event - * should be given to bt_recv or bt_recv_prio. - * * @param evt HCI event code. * * @return HCI event flags for the specified event. @@ -85,10 +81,6 @@ static inline uint8_t bt_hci_evt_get_flags(uint8_t evt) * host with data from the controller. The buffer needs to have its type * set with the help of bt_buf_set_type() before calling this API. * - * When @kconfig{CONFIG_BT_RECV_BLOCKING} is defined then this API should not be used - * for so-called high priority HCI events, which should instead be delivered to - * the host stack through bt_recv_prio(). - * * @note This function must only be called from a cooperative thread. * * @param buf Network buffer containing data from the controller. @@ -176,10 +168,6 @@ struct bt_hci_driver { * return until the transport is ready for operation, meaning it * is safe to start calling the send() handler. * - * If the driver uses its own RX thread, i.e. - * @kconfig{CONFIG_BT_RECV_BLOCKING} is set, then this - * function is expected to start that thread. - * * @return 0 on success or negative error number on failure. */ int (*open)(void); @@ -190,9 +178,6 @@ struct bt_hci_driver { * Closes the HCI transport. This function must not return until the * transport is closed. * - * If the driver uses its own RX thread, i.e. - * @kconfig{CONFIG_BT_RECV_BLOCKING} is set, then this - * function is expected to abort that thread. * @return 0 on success or negative error number on failure. */ int (*close)(void); diff --git a/subsys/bluetooth/common/Kconfig b/subsys/bluetooth/common/Kconfig index 0cfb8dfb106..a5a21aece39 100644 --- a/subsys/bluetooth/common/Kconfig +++ b/subsys/bluetooth/common/Kconfig @@ -95,7 +95,6 @@ config BT_BUF_ACL_RX_SIZE config BT_BUF_ACL_RX_COUNT int "Number of incoming ACL data buffers" default NET_BUF_RX_COUNT if NET_L2_BT - default 3 if BT_RECV_BLOCKING default 6 range 1 64 help @@ -126,7 +125,6 @@ config BT_BUF_EVT_RX_SIZE config BT_BUF_EVT_RX_COUNT int "Number of HCI Event buffers" - default 3 if BT_RECV_BLOCKING default 20 if (BT_MESH && !(BT_BUF_EVT_DISCARDABLE_COUNT > 0)) default 10 range 2 255 diff --git a/subsys/bluetooth/controller/hci/hci_driver.c b/subsys/bluetooth/controller/hci/hci_driver.c index 7904836cdc7..ddc63c5d2fc 100644 --- a/subsys/bluetooth/controller/hci/hci_driver.c +++ b/subsys/bluetooth/controller/hci/hci_driver.c @@ -73,7 +73,7 @@ struct k_thread prio_recv_thread_data; static K_KERNEL_STACK_DEFINE(prio_recv_thread_stack, CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE); struct k_thread recv_thread_data; -static K_KERNEL_STACK_DEFINE(recv_thread_stack, CONFIG_BT_RX_STACK_SIZE); +static K_KERNEL_STACK_DEFINE(recv_thread_stack, CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE); #if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL) static struct k_poll_signal hbuf_signal; @@ -81,11 +81,10 @@ static sys_slist_t hbuf_pend; static int32_t hbuf_count; #endif -#if !defined(CONFIG_BT_RECV_BLOCKING) /* Copied here from `hci_raw.c`, which would be used in * conjunction with this driver when serializing HCI over wire. - * This serves as a converter from the more complicated - * `CONFIG_BT_RECV_BLOCKING` API to the normal single-receiver + * This serves as a converter from the historical (removed from + * tree) 'recv blocking' API to the normal single-receiver * `bt_recv` API. */ int bt_recv_prio(struct net_buf *buf) @@ -103,7 +102,6 @@ int bt_recv_prio(struct net_buf *buf) return bt_recv(buf); } -#endif /* CONFIG_BT_RECV_BLOCKING */ #if defined(CONFIG_BT_CTLR_ISO) diff --git a/subsys/bluetooth/host/Kconfig b/subsys/bluetooth/host/Kconfig index e124a549785..0be375007ca 100644 --- a/subsys/bluetooth/host/Kconfig +++ b/subsys/bluetooth/host/Kconfig @@ -95,7 +95,7 @@ config BT_HCI_RESERVE choice BT_RECV_CONTEXT prompt "BT RX Thread Selection" - default BT_RECV_BLOCKING if BT_LL_SW_SPLIT || BT_H4 + default BT_RECV_WORKQ_SYS if SOC_SERIES_NRF51X default BT_RECV_WORKQ_BT help Selects in which context incoming low priority HCI packets are processed. @@ -104,13 +104,6 @@ choice BT_RECV_CONTEXT or bt_recv_prio(). The choice will influence RAM usage and how fast incoming HCI packets are processed. -config BT_RECV_BLOCKING - bool "Process HCI packets in the context of bt_recv() and bt_recv_prio()" - help - When this option is selected, the host will not have its own RX thread. - With this option it is the responsibility of the HCI driver to call - bt_recv_prio from a higher priority context than bt_recv() in order to avoid deadlocks. - config BT_RECV_WORKQ_SYS bool "Process low priority HCI packets in the system work queue" help diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c index 81e894d2a70..52bc4b2611f 100644 --- a/subsys/bluetooth/host/hci_core.c +++ b/subsys/bluetooth/host/hci_core.c @@ -66,14 +66,12 @@ LOG_MODULE_REGISTER(bt_hci_core); #define HCI_CMD_TIMEOUT K_SECONDS(10) /* Stacks for the threads */ -#if !defined(CONFIG_BT_RECV_BLOCKING) static void rx_work_handler(struct k_work *work); static K_WORK_DEFINE(rx_work, rx_work_handler); #if defined(CONFIG_BT_RECV_WORKQ_BT) static struct k_work_q bt_workq; static K_KERNEL_STACK_DEFINE(rx_thread_stack, CONFIG_BT_RX_STACK_SIZE); #endif /* CONFIG_BT_RECV_WORKQ_BT */ -#endif /* !CONFIG_BT_RECV_BLOCKING */ static struct k_thread tx_thread_data; static K_KERNEL_STACK_DEFINE(tx_thread_stack, CONFIG_BT_HCI_TX_STACK_SIZE); @@ -3854,7 +3852,6 @@ void hci_event_prio(struct net_buf *buf) } } -#if !defined(CONFIG_BT_RECV_BLOCKING) static void rx_queue_put(struct net_buf *buf) { net_buf_slist_put(&bt_dev.rx_queue, buf); @@ -3868,7 +3865,6 @@ static void rx_queue_put(struct net_buf *buf) LOG_ERR("Could not submit rx_work: %d", err); } } -#endif /* !CONFIG_BT_RECV_BLOCKING */ int bt_recv(struct net_buf *buf) { @@ -3879,18 +3875,11 @@ int bt_recv(struct net_buf *buf) switch (bt_buf_get_type(buf)) { #if defined(CONFIG_BT_CONN) case BT_BUF_ACL_IN: -#if defined(CONFIG_BT_RECV_BLOCKING) - hci_acl(buf); -#else rx_queue_put(buf); -#endif return 0; #endif /* BT_CONN */ case BT_BUF_EVT: { -#if defined(CONFIG_BT_RECV_BLOCKING) - hci_event(buf); -#else struct bt_hci_evt_hdr *hdr = (void *)buf->data; uint8_t evt_flags = bt_hci_evt_get_flags(hdr->evt); @@ -3901,17 +3890,12 @@ int bt_recv(struct net_buf *buf) if (evt_flags & BT_HCI_EVT_FLAG_RECV) { rx_queue_put(buf); } -#endif - return 0; + return 0; } #if defined(CONFIG_BT_ISO) case BT_BUF_ISO_IN: -#if defined(CONFIG_BT_RECV_BLOCKING) - hci_iso(buf); -#else rx_queue_put(buf); -#endif return 0; #endif /* CONFIG_BT_ISO */ default: @@ -3921,19 +3905,6 @@ int bt_recv(struct net_buf *buf) } } -#if defined(CONFIG_BT_RECV_BLOCKING) -int bt_recv_prio(struct net_buf *buf) -{ - bt_monitor_send(bt_monitor_opcode(buf), buf->data, buf->len); - - BT_ASSERT(bt_buf_get_type(buf) == BT_BUF_EVT); - - hci_event_prio(buf); - - return 0; -} -#endif /* CONFIG_BT_RECV_BLOCKING */ - int bt_hci_driver_register(const struct bt_hci_driver *drv) { if (bt_dev.drv) { @@ -4011,7 +3982,6 @@ static void init_work(struct k_work *work) } } -#if !defined(CONFIG_BT_RECV_BLOCKING) static void rx_work_handler(struct k_work *work) { int err; @@ -4063,7 +4033,6 @@ static void rx_work_handler(struct k_work *work) } } } -#endif /* !CONFIG_BT_RECV_BLOCKING */ #if defined(CONFIG_BT_TESTING) k_tid_t bt_testing_tx_tid_get(void) diff --git a/subsys/bluetooth/host/hci_core.h b/subsys/bluetooth/host/hci_core.h index 4263706382b..d037d0add9d 100644 --- a/subsys/bluetooth/host/hci_core.h +++ b/subsys/bluetooth/host/hci_core.h @@ -366,10 +366,8 @@ struct bt_dev { /* Last sent HCI command */ struct net_buf *sent_cmd; -#if !defined(CONFIG_BT_RECV_BLOCKING) /* Queue for incoming HCI events & ACL data */ sys_slist_t rx_queue; -#endif /* Queue for outgoing HCI commands */ struct k_fifo cmd_tx_queue; diff --git a/subsys/bluetooth/host/hci_ecc.c b/subsys/bluetooth/host/hci_ecc.c index 444f80bc962..8c1b1a777b9 100644 --- a/subsys/bluetooth/host/hci_ecc.c +++ b/subsys/bluetooth/host/hci_ecc.c @@ -92,11 +92,7 @@ static void send_cmd_status(uint16_t opcode, uint8_t status) evt->opcode = sys_cpu_to_le16(opcode); evt->status = status; - if (IS_ENABLED(CONFIG_BT_RECV_BLOCKING)) { - bt_recv_prio(buf); - } else { - bt_recv(buf); - } + bt_recv(buf); } static uint8_t generate_keys(void) diff --git a/tests/bsim/bluetooth/host/misc/conn_stress/central/prj.conf b/tests/bsim/bluetooth/host/misc/conn_stress/central/prj.conf index 3b0835e86df..c5ae7e3f1a6 100644 --- a/tests/bsim/bluetooth/host/misc/conn_stress/central/prj.conf +++ b/tests/bsim/bluetooth/host/misc/conn_stress/central/prj.conf @@ -32,9 +32,6 @@ CONFIG_ASSERT_ON_ERRORS=y CONFIG_BT_RECV_WORKQ_BT=y # CONFIG_BT_RECV_WORKQ_SYS=y -# errors out getting event flags in hci_core.c -# CONFIG_BT_RECV_BLOCKING=y - # TODO: remove when test is stable CONFIG_BT_AUTO_PHY_UPDATE=n CONFIG_BT_AUTO_DATA_LEN_UPDATE=n From 3d3b5b5a48880006d44542a468647be42379f2b0 Mon Sep 17 00:00:00 2001 From: Aleksander Wasaznik Date: Wed, 20 Mar 2024 16:32:58 +0100 Subject: [PATCH 1415/2402] Bluetooth: `hci_driver.h`: Remove `bt_recv_prio` Remove `bt_recv_prio` from the HCI driver interface. It's primary purpose was to be used in conjunction with `CONFIG_BT_RECV_BLOCKING`, which has been removed. `hci_raw.c` provided a adapter implementation to make drivers implementing the `CONFIG_BT_RECV_BLOCKING` interface useable with `CONFIG_BT_HCI_RAW`. But since `bt_recv_prio` is being removed from the HCI driver interface, drivers needing the adapter should copy the adapter implementation as private internals. Signed-off-by: Aleksander Wasaznik --- include/zephyr/bluetooth/buf.h | 6 +++--- include/zephyr/drivers/bluetooth/hci_driver.h | 21 ------------------- subsys/bluetooth/host/hci_raw.c | 16 -------------- 3 files changed, 3 insertions(+), 40 deletions(-) diff --git a/include/zephyr/bluetooth/buf.h b/include/zephyr/bluetooth/buf.h index b079695d61c..6415b987257 100644 --- a/include/zephyr/bluetooth/buf.h +++ b/include/zephyr/bluetooth/buf.h @@ -103,7 +103,7 @@ struct bt_buf_data { /** Allocate a buffer for incoming data * * This will set the buffer type so bt_buf_set_type() does not need to - * be explicitly called before bt_recv_prio(). + * be explicitly called. * * @param type Type of buffer. Only BT_BUF_EVT, BT_BUF_ACL_IN and BT_BUF_ISO_IN * are allowed. @@ -116,7 +116,7 @@ struct net_buf *bt_buf_get_rx(enum bt_buf_type type, k_timeout_t timeout); /** Allocate a buffer for outgoing data * * This will set the buffer type so bt_buf_set_type() does not need to - * be explicitly called before bt_send(). + * be explicitly called. * * @param type Type of buffer. Only BT_BUF_CMD, BT_BUF_ACL_OUT or * BT_BUF_H4, when operating on H:4 mode, are allowed. @@ -132,7 +132,7 @@ struct net_buf *bt_buf_get_tx(enum bt_buf_type type, k_timeout_t timeout, /** Allocate a buffer for an HCI Event * * This will set the buffer type so bt_buf_set_type() does not need to - * be explicitly called before bt_recv_prio() or bt_recv(). + * be explicitly called. * * @param evt HCI event code * @param discardable Whether the driver considers the event discardable. diff --git a/include/zephyr/drivers/bluetooth/hci_driver.h b/include/zephyr/drivers/bluetooth/hci_driver.h index 3682ebce009..12ce698aa49 100644 --- a/include/zephyr/drivers/bluetooth/hci_driver.h +++ b/include/zephyr/drivers/bluetooth/hci_driver.h @@ -39,9 +39,7 @@ enum { #define IS_BT_QUIRK_NO_AUTO_DLE(bt_dev) ((bt_dev)->drv->quirks & BT_QUIRK_NO_AUTO_DLE) -/* @brief The HCI event shall be given to bt_recv_prio */ #define BT_HCI_EVT_FLAG_RECV_PRIO BIT(0) -/* @brief The HCI event shall be given to bt_recv. */ #define BT_HCI_EVT_FLAG_RECV BIT(1) /** @brief Get HCI event flags. @@ -89,25 +87,6 @@ static inline uint8_t bt_hci_evt_get_flags(uint8_t evt) */ int bt_recv(struct net_buf *buf); -/** - * @brief Receive high priority data from the controller/HCI driver. - * - * This is the same as bt_recv(), except that it should be used for - * so-called high priority HCI events. There's a separate - * bt_hci_evt_get_flags() helper that can be used to identify which events - * have the BT_HCI_EVT_FLAG_RECV_PRIO flag set. - * - * As with bt_recv(), the buffer needs to have its type set with the help of - * bt_buf_set_type() before calling this API. The only exception is so called - * high priority HCI events which should be delivered to the host stack through - * bt_recv_prio() instead. - * - * @param buf Network buffer containing data from the controller. - * - * @return 0 on success or negative error number on failure. - */ -int bt_recv_prio(struct net_buf *buf); - /** @brief Read static addresses from the controller. * * @param addrs Random static address and Identity Root (IR) array. diff --git a/subsys/bluetooth/host/hci_raw.c b/subsys/bluetooth/host/hci_raw.c index 16113c8d25a..2aa8a4fe3d1 100644 --- a/subsys/bluetooth/host/hci_raw.c +++ b/subsys/bluetooth/host/hci_raw.c @@ -215,22 +215,6 @@ int bt_recv(struct net_buf *buf) return 0; } -int bt_recv_prio(struct net_buf *buf) -{ - if (bt_buf_get_type(buf) == BT_BUF_EVT) { - struct bt_hci_evt_hdr *hdr = (void *)buf->data; - uint8_t evt_flags = bt_hci_evt_get_flags(hdr->evt); - - if ((evt_flags & BT_HCI_EVT_FLAG_RECV_PRIO) && - (evt_flags & BT_HCI_EVT_FLAG_RECV)) { - /* Avoid queuing the event twice */ - return 0; - } - } - - return bt_recv(buf); -} - static void bt_cmd_complete_ext(uint16_t op, uint8_t status) { struct net_buf *buf; From 171363501a3f9a928660b210ab3605efa406147a Mon Sep 17 00:00:00 2001 From: Aleksander Wasaznik Date: Wed, 20 Mar 2024 16:38:49 +0100 Subject: [PATCH 1416/2402] Bluetooth: Move `bt_hci_evt_get_flags` out of `hci_driver.h` This commit removes `bt_hci_evt_get_flags`, and the associated flag symbols. These symbols no longer serve a purpose in the driver interface after the removal of `bt_recv_prio` from the interface. The implementation of `bt_hci_evt_get_flags` is distributed to its still-existing use sites, `hci_core` and the `hci_driver` in the controller. The duplication of code is intentional. This is no longer part of any interface, and the host-developers expect the host copy of the function to change or dissapear entierly. This will allow the host implementation to progress without fear of breaking the controller implementation. Signed-off-by: Aleksander Wasaznik --- include/zephyr/drivers/bluetooth/hci_driver.h | 33 ----------------- subsys/bluetooth/controller/hci/hci_driver.c | 35 ++++++++++++++++++- subsys/bluetooth/host/hci_core.c | 34 ++++++++++++++++++ 3 files changed, 68 insertions(+), 34 deletions(-) diff --git a/include/zephyr/drivers/bluetooth/hci_driver.h b/include/zephyr/drivers/bluetooth/hci_driver.h index 12ce698aa49..e611c8b089f 100644 --- a/include/zephyr/drivers/bluetooth/hci_driver.h +++ b/include/zephyr/drivers/bluetooth/hci_driver.h @@ -39,39 +39,6 @@ enum { #define IS_BT_QUIRK_NO_AUTO_DLE(bt_dev) ((bt_dev)->drv->quirks & BT_QUIRK_NO_AUTO_DLE) -#define BT_HCI_EVT_FLAG_RECV_PRIO BIT(0) -#define BT_HCI_EVT_FLAG_RECV BIT(1) - -/** @brief Get HCI event flags. - * - * Helper for the HCI driver to get HCI event flags that describes rules that. - * must be followed. - * - * @param evt HCI event code. - * - * @return HCI event flags for the specified event. - */ -static inline uint8_t bt_hci_evt_get_flags(uint8_t evt) -{ - switch (evt) { - case BT_HCI_EVT_DISCONN_COMPLETE: - return BT_HCI_EVT_FLAG_RECV | BT_HCI_EVT_FLAG_RECV_PRIO; - /* fallthrough */ -#if defined(CONFIG_BT_CONN) || defined(CONFIG_BT_ISO) - case BT_HCI_EVT_NUM_COMPLETED_PACKETS: -#if defined(CONFIG_BT_CONN) - case BT_HCI_EVT_DATA_BUF_OVERFLOW: - __fallthrough; -#endif /* defined(CONFIG_BT_CONN) */ -#endif /* CONFIG_BT_CONN || CONFIG_BT_ISO */ - case BT_HCI_EVT_CMD_COMPLETE: - case BT_HCI_EVT_CMD_STATUS: - return BT_HCI_EVT_FLAG_RECV_PRIO; - default: - return BT_HCI_EVT_FLAG_RECV; - } -} - /** * @brief Receive data from the controller/HCI driver. * diff --git a/subsys/bluetooth/controller/hci/hci_driver.c b/subsys/bluetooth/controller/hci/hci_driver.c index ddc63c5d2fc..cc315a99df6 100644 --- a/subsys/bluetooth/controller/hci/hci_driver.c +++ b/subsys/bluetooth/controller/hci/hci_driver.c @@ -81,13 +81,46 @@ static sys_slist_t hbuf_pend; static int32_t hbuf_count; #endif +#define BT_HCI_EVT_FLAG_RECV_PRIO BIT(0) +#define BT_HCI_EVT_FLAG_RECV BIT(1) + +/** @brief Get HCI event flags. + * + * Helper for the HCI driver to get HCI event flags that describes rules that. + * must be followed. + * + * @param evt HCI event code. + * + * @return HCI event flags for the specified event. + */ +static inline uint8_t bt_hci_evt_get_flags(uint8_t evt) +{ + switch (evt) { + case BT_HCI_EVT_DISCONN_COMPLETE: + return BT_HCI_EVT_FLAG_RECV | BT_HCI_EVT_FLAG_RECV_PRIO; + /* fallthrough */ +#if defined(CONFIG_BT_CONN) || defined(CONFIG_BT_ISO) + case BT_HCI_EVT_NUM_COMPLETED_PACKETS: +#if defined(CONFIG_BT_CONN) + case BT_HCI_EVT_DATA_BUF_OVERFLOW: + __fallthrough; +#endif /* defined(CONFIG_BT_CONN) */ +#endif /* CONFIG_BT_CONN || CONFIG_BT_ISO */ + case BT_HCI_EVT_CMD_COMPLETE: + case BT_HCI_EVT_CMD_STATUS: + return BT_HCI_EVT_FLAG_RECV_PRIO; + default: + return BT_HCI_EVT_FLAG_RECV; + } +} + /* Copied here from `hci_raw.c`, which would be used in * conjunction with this driver when serializing HCI over wire. * This serves as a converter from the historical (removed from * tree) 'recv blocking' API to the normal single-receiver * `bt_recv` API. */ -int bt_recv_prio(struct net_buf *buf) +static int bt_recv_prio(struct net_buf *buf) { if (bt_buf_get_type(buf) == BT_BUF_EVT) { struct bt_hci_evt_hdr *hdr = (void *)buf->data; diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c index 52bc4b2611f..0118b5efdaa 100644 --- a/subsys/bluetooth/host/hci_core.c +++ b/subsys/bluetooth/host/hci_core.c @@ -2744,6 +2744,40 @@ static const struct event_handler normal_events[] = { sizeof(struct bt_hci_evt_hardware_error)), }; + +#define BT_HCI_EVT_FLAG_RECV_PRIO BIT(0) +#define BT_HCI_EVT_FLAG_RECV BIT(1) + +/** @brief Get HCI event flags. + * + * Helper for the HCI driver to get HCI event flags that describes rules that. + * must be followed. + * + * @param evt HCI event code. + * + * @return HCI event flags for the specified event. + */ +static inline uint8_t bt_hci_evt_get_flags(uint8_t evt) +{ + switch (evt) { + case BT_HCI_EVT_DISCONN_COMPLETE: + return BT_HCI_EVT_FLAG_RECV | BT_HCI_EVT_FLAG_RECV_PRIO; + /* fallthrough */ +#if defined(CONFIG_BT_CONN) || defined(CONFIG_BT_ISO) + case BT_HCI_EVT_NUM_COMPLETED_PACKETS: +#if defined(CONFIG_BT_CONN) + case BT_HCI_EVT_DATA_BUF_OVERFLOW: + __fallthrough; +#endif /* defined(CONFIG_BT_CONN) */ +#endif /* CONFIG_BT_CONN || CONFIG_BT_ISO */ + case BT_HCI_EVT_CMD_COMPLETE: + case BT_HCI_EVT_CMD_STATUS: + return BT_HCI_EVT_FLAG_RECV_PRIO; + default: + return BT_HCI_EVT_FLAG_RECV; + } +} + static void hci_event(struct net_buf *buf) { struct bt_hci_evt_hdr *hdr; From e9bc58bc7576bdb6642dbbb70304b93ec470053d Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Wed, 22 Nov 2023 16:12:45 +0100 Subject: [PATCH 1417/2402] drivers: gpio: xlnx_axi: fix polling mode Fix compiler errors and warnings that are issued when compiling this driver for use without the optional interrupt facilities. When interrupts are not enabled for any instance of this device, there's currently a compiler error in gpio_xlnx_axi_pin_interrupt_configure due to the function's header being located within the ifdef-block for interrupt-driven operation. Fully encapsulate the interrupt-related functions gpio_xlnx_axi_pin_interrupt_configure, gpio_xlnx_axi_manage_callback and gpio_xlnx_axi_get_pending_int with ifdefs checking for interrupt mode inorder to remove compiler warnings caused by those functions being always present so far, while not being used in the API function pointer table when all instances of this GPIO controller are operating in polling mode. This circumstance causes a "declared, but not used" compiler warning for each of those functions. Signed-off-by: Immo Birnbaum --- drivers/gpio/gpio_xlnx_axi.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/drivers/gpio/gpio_xlnx_axi.c b/drivers/gpio/gpio_xlnx_axi.c index f070e691e5d..f6ba2dd2606 100644 --- a/drivers/gpio/gpio_xlnx_axi.c +++ b/drivers/gpio/gpio_xlnx_axi.c @@ -260,39 +260,26 @@ static int gpio_xlnx_axi_pin_interrupt_configure(const struct device *dev, gpio_ irq_unlock(key); return 0; -#else - ARG_UNUSED(dev); - ARG_UNUSED(pin); - ARG_UNUSED(mode); - ARG_UNUSED(trig); - - return -ENOTSUP; -#endif } +#endif +#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts) static int gpio_xlnx_axi_manage_callback(const struct device *dev, struct gpio_callback *callback, bool set) { -#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts) struct gpio_xlnx_axi_data *data = dev->data; return gpio_manage_callback(&data->callbacks, callback, set); -#else - ARG_UNUSED(dev); - ARG_UNUSED(callback); - ARG_UNUSED(set); - - return -ENOTSUP; -#endif } +#endif +#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts) /** * Returns the pins on this devices channel which changed and also have an interrupt enabled on that * pin. Also clears the pending interrupt for that channel. */ static uint32_t gpio_xlnx_axi_get_pending_int(const struct device *dev) { -#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts) const struct gpio_xlnx_axi_config *config = dev->config; struct gpio_xlnx_axi_data *data = dev->data; const uint32_t chan_mask = BIT(config->channel); @@ -328,12 +315,8 @@ static uint32_t gpio_xlnx_axi_get_pending_int(const struct device *dev) irq_unlock(key); return interrupts; -#else - ARG_UNUSED(dev); - - return 0; -#endif } +#endif #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts) static void gpio_xlnx_axi_isr(const struct device *dev) From 0e46701d6d06449f153a1aff2c1bd7b2b3d956c9 Mon Sep 17 00:00:00 2001 From: Marco Widmer Date: Fri, 12 Jan 2024 15:00:46 +0100 Subject: [PATCH 1418/2402] modules: hal_nordic: nrfx_glue: Fix coding style We will touch these lines in the next commit. Convert the comment style to C89 instead of C99 and the indentation to tabs instead of spaces. Signed-off-by: Marco Widmer --- modules/hal_nordic/nrfx/nrfx_glue.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/modules/hal_nordic/nrfx/nrfx_glue.h b/modules/hal_nordic/nrfx/nrfx_glue.h index 748c5eafd47..3a540699df6 100644 --- a/modules/hal_nordic/nrfx/nrfx_glue.h +++ b/modules/hal_nordic/nrfx/nrfx_glue.h @@ -63,9 +63,8 @@ extern "C" { * @param irq_number IRQ number. * @param priority Priority to be set. */ -#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) // Intentionally empty. - // Priorities of IRQs are - // set through IRQ_CONNECT. +#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) \ + /* Intentionally empty. Priorities of IRQs are set through IRQ_CONNECT. */ /** * @brief Macro for enabling a specific IRQ. From 1a899ee414aa26b9224d26805eccb66635bfcc6c Mon Sep 17 00:00:00 2001 From: Marco Widmer Date: Fri, 12 Jan 2024 14:43:40 +0100 Subject: [PATCH 1419/2402] modules: hal_nordic: nrfx_glue: Fix unused argument NRFX_IRQ_PRIORITY_SET is defined as empty. This causes an unused argument warning in many callers (e.g. nrfy_gpiote_int_init). Fix it by using ARG_UNUSED for the priority argument. Signed-off-by: Marco Widmer --- modules/hal_nordic/nrfx/nrfx_glue.h | 1 + 1 file changed, 1 insertion(+) diff --git a/modules/hal_nordic/nrfx/nrfx_glue.h b/modules/hal_nordic/nrfx/nrfx_glue.h index 3a540699df6..593aff6fcc7 100644 --- a/modules/hal_nordic/nrfx/nrfx_glue.h +++ b/modules/hal_nordic/nrfx/nrfx_glue.h @@ -64,6 +64,7 @@ extern "C" { * @param priority Priority to be set. */ #define NRFX_IRQ_PRIORITY_SET(irq_number, priority) \ + ARG_UNUSED(priority) \ /* Intentionally empty. Priorities of IRQs are set through IRQ_CONNECT. */ /** From bf910873bcf5656120e72b488295e3039447a345 Mon Sep 17 00:00:00 2001 From: Jeff Welder Date: Mon, 19 Feb 2024 18:52:14 -0500 Subject: [PATCH 1420/2402] modem: modem_cellular: Add ICCID to Modem Info API Added missing SIM ICCID case to Modem Info API. Signed-off-by: Jeff Welder --- drivers/modem/modem_cellular.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index f5081d5f69a..7629a7e48fd 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -366,11 +366,27 @@ static void modem_cellular_chat_on_cesq(struct modem_chat *chat, char **argv, ui data->rsrp = (uint8_t)atoi(argv[6]); } +static void modem_cellular_chat_on_iccid(struct modem_chat *chat, char **argv, uint16_t argc, + void *user_data) +{ + struct modem_cellular_data *data = (struct modem_cellular_data *)user_data; + + if (argc != 2) { + return; + } + + strncpy(data->iccid, argv[1], sizeof(data->iccid) - 1); +} + static void modem_cellular_chat_on_imsi(struct modem_chat *chat, char **argv, uint16_t argc, void *user_data) { struct modem_cellular_data *data = (struct modem_cellular_data *)user_data; + if (argc != 2) { + return; + } + strncpy(data->imsi, argv[1], sizeof(data->imsi) - 1); } @@ -422,6 +438,7 @@ MODEM_CHAT_MATCH_DEFINE(imei_match, "", "", modem_cellular_chat_on_imei); MODEM_CHAT_MATCH_DEFINE(cgmm_match, "", "", modem_cellular_chat_on_cgmm); MODEM_CHAT_MATCH_DEFINE(csq_match, "+CSQ: ", ",", modem_cellular_chat_on_csq); MODEM_CHAT_MATCH_DEFINE(cesq_match, "+CESQ: ", ",", modem_cellular_chat_on_cesq); +MODEM_CHAT_MATCH_DEFINE(iccid_match __maybe_unused, "+ICCID: ", "", modem_cellular_chat_on_iccid); MODEM_CHAT_MATCH_DEFINE(cimi_match __maybe_unused, "", "", modem_cellular_chat_on_imsi); MODEM_CHAT_MATCH_DEFINE(cgmi_match __maybe_unused, "", "", modem_cellular_chat_on_cgmi); MODEM_CHAT_MATCH_DEFINE(cgmr_match __maybe_unused, "", "", modem_cellular_chat_on_cgmr); @@ -1400,6 +1417,9 @@ static int modem_cellular_get_modem_info(const struct device *dev, case CELLULAR_MODEM_INFO_MODEL_ID: strncpy(info, &data->model_id[0], MIN(size, sizeof(data->model_id))); break; + case CELLULAR_MODEM_INFO_SIM_ICCID: + strncpy(info, &data->iccid[0], MIN(size, sizeof(data->iccid))); + break; default: ret = -ENODATA; break; From 2f63bc7ac94b36e9b3a663cd385c0992b657fe5f Mon Sep 17 00:00:00 2001 From: Jeff Welder Date: Mon, 19 Feb 2024 18:56:45 -0500 Subject: [PATCH 1421/2402] modem: modem_cellular: Telit ME910G1 Complete Modem Info Add missing fields to complete info struct to chat script for Telit ME910G1. Also for test suite modem bg95. Signed-off-by: Jeff Welder --- drivers/modem/modem_cellular.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c index 7629a7e48fd..c66264d349f 100644 --- a/drivers/modem/modem_cellular.c +++ b/drivers/modem/modem_cellular.c @@ -438,6 +438,7 @@ MODEM_CHAT_MATCH_DEFINE(imei_match, "", "", modem_cellular_chat_on_imei); MODEM_CHAT_MATCH_DEFINE(cgmm_match, "", "", modem_cellular_chat_on_cgmm); MODEM_CHAT_MATCH_DEFINE(csq_match, "+CSQ: ", ",", modem_cellular_chat_on_csq); MODEM_CHAT_MATCH_DEFINE(cesq_match, "+CESQ: ", ",", modem_cellular_chat_on_cesq); +MODEM_CHAT_MATCH_DEFINE(qccid_match __maybe_unused, "+QCCID: ", "", modem_cellular_chat_on_iccid); MODEM_CHAT_MATCH_DEFINE(iccid_match __maybe_unused, "+ICCID: ", "", modem_cellular_chat_on_iccid); MODEM_CHAT_MATCH_DEFINE(cimi_match __maybe_unused, "", "", modem_cellular_chat_on_imsi); MODEM_CHAT_MATCH_DEFINE(cgmi_match __maybe_unused, "", "", modem_cellular_chat_on_cgmi); @@ -1621,6 +1622,8 @@ MODEM_CHAT_SCRIPT_CMDS_DEFINE(quectel_bg95_init_chat_script_cmds, MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), MODEM_CHAT_SCRIPT_CMD_RESP("AT+CIMI", cimi_match), MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+QCCID", qccid_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT+CMUX=0,0,5,127", 300)); MODEM_CHAT_SCRIPT_DEFINE(quectel_bg95_init_chat_script, quectel_bg95_init_chat_script_cmds, @@ -1948,6 +1951,10 @@ MODEM_CHAT_SCRIPT_CMDS_DEFINE(telit_me910g1_init_chat_script_cmds, MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT", 100), MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT", 100), MODEM_CHAT_SCRIPT_CMD_RESP("ATE0", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+ICCID", iccid_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CIMI", cimi_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), /* The Telit me910g1 often has an error trying * to set the PDP context. The radio must be on to set * the context, and this step must be successful. @@ -1968,6 +1975,10 @@ MODEM_CHAT_SCRIPT_CMDS_DEFINE(telit_me910g1_init_chat_script_cmds, MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMM", cgmm_match), MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMI", cgmi_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), + MODEM_CHAT_SCRIPT_CMD_RESP("AT+CGMR", cgmr_match), + MODEM_CHAT_SCRIPT_CMD_RESP("", ok_match), MODEM_CHAT_SCRIPT_CMD_RESP("AT+CFUN=1", ok_match), MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT+CMUX=0,0,5,127,10,3,30,10,2", 300)); From f207cfec549a4f0cdec9ebf66951dc79446ffa6f Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 22 Mar 2024 13:30:54 +0100 Subject: [PATCH 1422/2402] docs twister: Mention the env filter Quite many users do not know that it exists, as we don't seem to have it documented anywhere. Signed-off-by: Alberto Escolar Piedras --- doc/develop/test/twister.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/develop/test/twister.rst b/doc/develop/test/twister.rst index f84fc73b99c..35f2c087eca 100644 --- a/doc/develop/test/twister.rst +++ b/doc/develop/test/twister.rst @@ -205,6 +205,12 @@ testing: power-efficient but slow CPU or simulation platform which can perform instruction accurate simulation but does it slowly. +env: + A list of environment variables. Twister will check if all these environment variables are set, + and otherwise skip this platform. This allows the user to define a platform which should be + used, for example, only if some required software or hardware is present, and to signal that + presence to twister using these environment variables. + Test Cases ********** From 9c27b21ecbce654d3c7c8524216ba11f21a52445 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Mon, 18 Mar 2024 12:55:08 -0700 Subject: [PATCH 1423/2402] doc: security: Add information about Open Security Training Add information and links for open source security training. Signed-off-by: Flavio Ceolin --- doc/security/secure-coding.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/doc/security/secure-coding.rst b/doc/security/secure-coding.rst index fe712eea82c..579622999b4 100644 --- a/doc/security/secure-coding.rst +++ b/doc/security/secure-coding.rst @@ -206,6 +206,13 @@ injection, OS injection, classic buffer overflow, cross-site scripting, missing authentication, and missing authorization. See the `CWE/SANS top 25`_ or `OWASP Top 10`_ for commonly used lists. +A free class from the nonprofit OpenSecurityTraining2 for C/C++ developers +is available at `OST2_1001`_. It teaches how to prevent, detect, and +mitigate linear stack/heap buffer overflows, non-linear out of bound writes, +integer overflows, and other integer issues. The follow-on class, `OST2_1002`_, +covers uninitialized data access, race conditions, use-after-free, type confusion, +and information disclosure vulnerabilities. + .. Turn this into something specific. Can we find examples of mistakes. Perhaps an example of things static analysis tool has sent us. @@ -213,6 +220,10 @@ scripting, missing authentication, and missing authorization. See the .. _OWASP Top 10: https://owasp.org/www-project-top-ten/ +.. _OST2_1001: https://ost2.fyi/Vulns1001 + +.. _OST2_1002: https://ost2.fyi/Vulns1002 + Zephyr Security Subcommittee ============================ From c0d52e4837691a518d5e4fedb87c266a67ad07dd Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Mon, 11 Mar 2024 19:24:50 +0100 Subject: [PATCH 1424/2402] drivers: video: mt9m114: Run clang format Run clang format before making any changes Signed-off-by: Phi Bang Nguyen --- drivers/video/mt9m114.c | 190 ++++++++++++++++++---------------------- 1 file changed, 86 insertions(+), 104 deletions(-) diff --git a/drivers/video/mt9m114.c b/drivers/video/mt9m114.c index 0e100d25264..5db0fc5d98b 100644 --- a/drivers/video/mt9m114.c +++ b/drivers/video/mt9m114.c @@ -17,40 +17,40 @@ #include LOG_MODULE_REGISTER(mt9m114); -#define MT9M114_CHIP_ID_VAL 0x2481 +#define MT9M114_CHIP_ID_VAL 0x2481 /* Sysctl registers */ -#define MT9M114_CHIP_ID 0x0000 -#define MT9M114_COMMAND_REGISTER 0x0080 -#define MT9M114_COMMAND_REGISTER_APPLY_PATCH (1 << 0) -#define MT9M114_COMMAND_REGISTER_SET_STATE (1 << 1) -#define MT9M114_COMMAND_REGISTER_REFRESH (1 << 2) -#define MT9M114_COMMAND_REGISTER_WAIT_FOR_EVENT (1 << 3) -#define MT9M114_COMMAND_REGISTER_OK (1 << 15) -#define MT9M114_PAD_CONTROL 0x0032 -#define MT9M114_RST_AND_MISC_CONTROL 0x001A +#define MT9M114_CHIP_ID 0x0000 +#define MT9M114_COMMAND_REGISTER 0x0080 +#define MT9M114_COMMAND_REGISTER_APPLY_PATCH (1 << 0) +#define MT9M114_COMMAND_REGISTER_SET_STATE (1 << 1) +#define MT9M114_COMMAND_REGISTER_REFRESH (1 << 2) +#define MT9M114_COMMAND_REGISTER_WAIT_FOR_EVENT (1 << 3) +#define MT9M114_COMMAND_REGISTER_OK (1 << 15) +#define MT9M114_PAD_CONTROL 0x0032 +#define MT9M114_RST_AND_MISC_CONTROL 0x001A /* Camera Control registers */ -#define MT9M114_CAM_OUTPUT_FORMAT 0xc86c +#define MT9M114_CAM_OUTPUT_FORMAT 0xc86c /* System Manager registers */ -#define MT9M114_SYSMGR_NEXT_STATE 0xdc00 -#define MT9M114_SYSMGR_CURRENT_STATE 0xdc01 -#define MT9M114_SYSMGR_CMD_STATUS 0xdc02 +#define MT9M114_SYSMGR_NEXT_STATE 0xdc00 +#define MT9M114_SYSMGR_CURRENT_STATE 0xdc01 +#define MT9M114_SYSMGR_CMD_STATUS 0xdc02 /* System States */ -#define MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE 0x28 -#define MT9M114_SYS_STATE_STREAMING 0x31 -#define MT9M114_SYS_STATE_START_STREAMING 0x34 -#define MT9M114_SYS_STATE_ENTER_SUSPEND 0x40 -#define MT9M114_SYS_STATE_SUSPENDED 0x41 -#define MT9M114_SYS_STATE_ENTER_STANDBY 0x50 -#define MT9M114_SYS_STATE_STANDBY 0x52 -#define MT9M114_SYS_STATE_LEAVE_STANDBY 0x54 +#define MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE 0x28 +#define MT9M114_SYS_STATE_STREAMING 0x31 +#define MT9M114_SYS_STATE_START_STREAMING 0x34 +#define MT9M114_SYS_STATE_ENTER_SUSPEND 0x40 +#define MT9M114_SYS_STATE_SUSPENDED 0x41 +#define MT9M114_SYS_STATE_ENTER_STANDBY 0x50 +#define MT9M114_SYS_STATE_STANDBY 0x52 +#define MT9M114_SYS_STATE_LEAVE_STANDBY 0x54 /* Camera output format */ -#define MT9M114_CAM_OUTPUT_FORMAT_FORMAT_YUV (0 << 8) -#define MT9M114_CAM_OUTPUT_FORMAT_FORMAT_RGB (1 << 8) +#define MT9M114_CAM_OUTPUT_FORMAT_FORMAT_YUV (0 << 8) +#define MT9M114_CAM_OUTPUT_FORMAT_FORMAT_RGB (1 << 8) struct mt9m114_config { struct i2c_dt_spec i2c; @@ -67,48 +67,47 @@ struct mt9m114_reg { }; static struct mt9m114_reg mt9m114_vga_24mhz_pll[] = { - { 0x98E, 2, 0x1000 }, - { 0xC97E, 2, 0x01 }, /* cam_sysctl_pll_enable = 1 */ - { 0xC980, 2, 0x0120 }, /* cam_sysctl_pll_divider_m_n = 288 */ - { 0xC982, 2, 0x0700 }, /* cam_sysctl_pll_divider_p = 1792 */ - { 0xC984, 2, 0x8000 }, /* cam_port_output_control = 32776 */ - { 0xC800, 2, 0x0000 }, /* cam_sensor_cfg_y_addr_start = 0 */ - { 0xC802, 2, 0x0000 }, /* cam_sensor_cfg_x_addr_start = 0 */ - { 0xC804, 2, 0x03CD }, /* cam_sensor_cfg_y_addr_end = 973 */ - { 0xC806, 2, 0x050D }, /* cam_sensor_cfg_x_addr_end = 1293 */ - { 0xC808, 4, 0x2DC6C00 }, /* cam_sensor_cfg_pixclk = 48000000 */ - { 0xC80C, 2, 0x0001 }, /* cam_sensor_cfg_row_speed = 1 */ - { 0xC80E, 2, 0x00DB }, /* cam_sensor_cfg_fine_integ_min = 219 */ - { 0xC810, 2, 0x07C2 }, /* cam_sensor_cfg_fine_integ_max = 1986 */ - { 0xC812, 2, 0x02FE }, /* cam_sensor_cfg_frame_length_lines = 766 */ - { 0xC814, 2, 0x0845 }, /* cam_sensor_cfg_line_length_pck = 2117 */ - { 0xC816, 2, 0x0060 }, /* cam_sensor_cfg_fine_correction = 96 */ - { 0xC818, 2, 0x01E3 }, /* cam_sensor_cfg_cpipe_last_row = 483 */ - { 0xC826, 2, 0x0020 }, /* cam_sensor_cfg_reg_0_data = 32 */ - { 0xC834, 2, 0x0110 }, /* cam_sensor_control_read_mode = 272 */ - { 0xC854, 2, 0x0000 }, /* cam_crop_window_xoffset = 0 */ - { 0xC856, 2, 0x0000 }, /* cam_crop_window_yoffset = 0 */ - { 0xC858, 2, 0x0280 }, /* cam_crop_window_width = 640 */ - { 0xC85A, 2, 0x01E0 }, /* cam_crop_window_height = 480 */ - { 0xC85C, 1, 0x03 }, /* cam_crop_cropmode = 3 */ - { 0xC868, 2, 0x0280 }, /* cam_output_width = 640 */ - { 0xC86A, 2, 0x01E0 }, /* cam_output_height = 480 */ - { 0xC878, 1, 0x00 }, /* cam_aet_aemode = 0 */ - { 0xC88C, 2, 0x1D9A }, /* cam_aet_max_frame_rate = 7578 */ - { 0xC914, 2, 0x0000 }, /* cam_stat_awb_clip_window_xstart = 0 */ - { 0xC88E, 2, 0x1D9A }, /* cam_aet_min_frame_rate = 7578 */ - { 0xC916, 2, 0x0000 }, /* cam_stat_awb_clip_window_ystart = 0 */ - { 0xC918, 2, 0x027F }, /* cam_stat_awb_clip_window_xend = 639 */ - { 0xC91A, 2, 0x01DF }, /* cam_stat_awb_clip_window_yend = 479 */ - { 0xC91C, 2, 0x0000 }, /* cam_stat_ae_initial_window_xstart = 0 */ - { 0xC91E, 2, 0x0000 }, /* cam_stat_ae_initial_window_ystart = 0 */ - { 0xC920, 2, 0x007F }, /* cam_stat_ae_initial_window_xend = 127 */ - { 0xC922, 2, 0x005F }, /* cam_stat_ae_initial_window_yend = 95 */ - { /* NULL terminated */ } -}; - -static inline int i2c_burst_read16_dt(const struct i2c_dt_spec *spec, - uint16_t start_addr, uint8_t *buf, uint32_t num_bytes) + {0x98E, 2, 0x1000}, /* logical_address_access = 0x1000 */ + {0xC97E, 2, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {0xC980, 2, 0x0120}, /* cam_sysctl_pll_divider_m_n = 288 */ + {0xC982, 2, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {0xC984, 2, 0x8000}, /* cam_port_output_control = 32776 */ + {0xC800, 2, 0x0000}, /* cam_sensor_cfg_y_addr_start = 0 */ + {0xC802, 2, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {0xC804, 2, 0x03CD}, /* cam_sensor_cfg_y_addr_end = 973 */ + {0xC806, 2, 0x050D}, /* cam_sensor_cfg_x_addr_end = 1293 */ + {0xC808, 4, 0x2DC6C00}, /* cam_sensor_cfg_pixclk = 48000000 */ + {0xC80C, 2, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + {0xC80E, 2, 0x00DB}, /* cam_sensor_cfg_fine_integ_min = 219 */ + {0xC810, 2, 0x07C2}, /* cam_sensor_cfg_fine_integ_max = 1986 */ + {0xC812, 2, 0x02FE}, /* cam_sensor_cfg_frame_length_lines = 766 */ + {0xC814, 2, 0x0845}, /* cam_sensor_cfg_line_length_pck = 2117 */ + {0xC816, 2, 0x0060}, /* cam_sensor_cfg_fine_correction = 96 */ + {0xC818, 2, 0x01E3}, /* cam_sensor_cfg_cpipe_last_row = 483 */ + {0xC826, 2, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {0xC834, 2, 0x0110}, /* cam_sensor_control_read_mode = 272 */ + {0xC854, 2, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {0xC856, 2, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {0xC858, 2, 0x0280}, /* cam_crop_window_width = 640 */ + {0xC85A, 2, 0x01E0}, /* cam_crop_window_height = 480 */ + {0xC85C, 1, 0x03}, /* cam_crop_cropmode = 3 */ + {0xC868, 2, 0x0280}, /* cam_output_width = 640 */ + {0xC86A, 2, 0x01E0}, /* cam_output_height = 480 */ + {0xC878, 1, 0x00}, /* cam_aet_aemode = 0 */ + {0xC88C, 2, 0x1D9A}, /* cam_aet_max_frame_rate = 7578 */ + {0xC914, 2, 0x0000}, /* cam_stat_awb_clip_window_xstart = 0 */ + {0xC88E, 2, 0x1D9A}, /* cam_aet_min_frame_rate = 7578 */ + {0xC916, 2, 0x0000}, /* cam_stat_awb_clip_window_ystart = 0 */ + {0xC918, 2, 0x027F}, /* cam_stat_awb_clip_window_xend = 639 */ + {0xC91A, 2, 0x01DF}, /* cam_stat_awb_clip_window_yend = 479 */ + {0xC91C, 2, 0x0000}, /* cam_stat_ae_initial_window_xstart = 0 */ + {0xC91E, 2, 0x0000}, /* cam_stat_ae_initial_window_ystart = 0 */ + {0xC920, 2, 0x007F}, /* cam_stat_ae_initial_window_xend = 127 */ + {0xC922, 2, 0x005F}, /* cam_stat_ae_initial_window_yend = 95 */ + {/* NULL terminated */}}; + +static inline int i2c_burst_read16_dt(const struct i2c_dt_spec *spec, uint16_t start_addr, + uint8_t *buf, uint32_t num_bytes) { uint8_t addr_buffer[2]; @@ -117,9 +116,8 @@ static inline int i2c_burst_read16_dt(const struct i2c_dt_spec *spec, return i2c_write_read_dt(spec, addr_buffer, sizeof(addr_buffer), buf, num_bytes); } -static inline int i2c_burst_write16_dt(const struct i2c_dt_spec *spec, - uint16_t start_addr, const uint8_t *buf, - uint32_t num_bytes) +static inline int i2c_burst_write16_dt(const struct i2c_dt_spec *spec, uint16_t start_addr, + const uint8_t *buf, uint32_t num_bytes) { uint8_t addr_buffer[2]; struct i2c_msg msg[2]; @@ -137,8 +135,7 @@ static inline int i2c_burst_write16_dt(const struct i2c_dt_spec *spec, return i2c_transfer_dt(spec, msg, 2); } -static int mt9m114_write_reg(const struct device *dev, uint16_t reg_addr, - uint8_t reg_size, +static int mt9m114_write_reg(const struct device *dev, uint16_t reg_addr, uint8_t reg_size, void *value) { const struct mt9m114_config *cfg = dev->config; @@ -159,8 +156,7 @@ static int mt9m114_write_reg(const struct device *dev, uint16_t reg_addr, return i2c_burst_write16_dt(&cfg->i2c, reg_addr, value, reg_size); } -static int mt9m114_read_reg(const struct device *dev, uint16_t reg_addr, - uint8_t reg_size, +static int mt9m114_read_reg(const struct device *dev, uint16_t reg_addr, uint8_t reg_size, void *value) { const struct mt9m114_config *cfg = dev->config; @@ -191,16 +187,14 @@ static int mt9m114_read_reg(const struct device *dev, uint16_t reg_addr, return 0; } -static int mt9m114_write_all(const struct device *dev, - struct mt9m114_reg *reg) +static int mt9m114_write_all(const struct device *dev, struct mt9m114_reg *reg) { int i = 0; while (reg[i].value_size) { int err; - err = mt9m114_write_reg(dev, reg[i].addr, reg[i].value_size, - ®[i].value); + err = mt9m114_write_reg(dev, reg[i].addr, reg[i].value_size, ®[i].value); if (err) { return err; } @@ -260,8 +254,7 @@ static int mt9m114_set_state(const struct device *dev, uint8_t state) return 0; } -static int mt9m114_set_output_format(const struct device *dev, - int pixel_format) +static int mt9m114_set_output_format(const struct device *dev, int pixel_format) { int ret = 0; uint16_t output_format; @@ -275,14 +268,13 @@ static int mt9m114_set_output_format(const struct device *dev, return -ENOTSUP; } - ret = mt9m114_write_reg(dev, MT9M114_CAM_OUTPUT_FORMAT, - sizeof(output_format), &output_format); + ret = mt9m114_write_reg(dev, MT9M114_CAM_OUTPUT_FORMAT, sizeof(output_format), + &output_format); return ret; } -static int mt9m114_set_fmt(const struct device *dev, - enum video_endpoint_id ep, +static int mt9m114_set_fmt(const struct device *dev, enum video_endpoint_id ep, struct video_format *fmt) { struct mt9m114_data *drv_data = dev->data; @@ -327,8 +319,7 @@ static int mt9m114_set_fmt(const struct device *dev, return 0; } -static int mt9m114_get_fmt(const struct device *dev, - enum video_endpoint_id ep, +static int mt9m114_get_fmt(const struct device *dev, enum video_endpoint_id ep, struct video_format *fmt) { struct mt9m114_data *drv_data = dev->data; @@ -348,25 +339,18 @@ static int mt9m114_stream_stop(const struct device *dev) return mt9m114_set_state(dev, MT9M114_SYS_STATE_ENTER_SUSPEND); } -#define MT9M114_VIDEO_FORMAT_CAP(width, height, format) \ - { \ - .pixelformat = (format), \ - .width_min = (width), \ - .width_max = (width), \ - .height_min = (height), \ - .height_max = (height), \ - .width_step = 0, \ - .height_step = 0 \ +#define MT9M114_VIDEO_FORMAT_CAP(width, height, format) \ + { \ + .pixelformat = (format), .width_min = (width), .width_max = (width), \ + .height_min = (height), .height_max = (height), .width_step = 0, .height_step = 0 \ } static const struct video_format_cap fmts[] = { - MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_RGB565), /* VGA RGB565 */ - MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_YUYV), /* VGA YUYV */ - { 0 } -}; + MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_RGB565), /* VGA RGB565 */ + MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_YUYV), /* VGA YUYV */ + {0}}; -static int mt9m114_get_caps(const struct device *dev, - enum video_endpoint_id ep, +static int mt9m114_get_caps(const struct device *dev, enum video_endpoint_id ep, struct video_caps *caps) { caps->format_caps = fmts; @@ -439,8 +423,6 @@ static int mt9m114_init_0(const struct device *dev) return mt9m114_init(dev); } -DEVICE_DT_INST_DEFINE(0, &mt9m114_init_0, NULL, - &mt9m114_data_0, &mt9m114_cfg_0, - POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, - &mt9m114_driver_api); +DEVICE_DT_INST_DEFINE(0, &mt9m114_init_0, NULL, &mt9m114_data_0, &mt9m114_cfg_0, POST_KERNEL, + CONFIG_VIDEO_INIT_PRIORITY, &mt9m114_driver_api); #endif From f17f1d67f804aa8e4087f77b34b1ca3189a97d9e Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Thu, 14 Mar 2024 14:59:43 +0100 Subject: [PATCH 1425/2402] drivers: video: mt9m114: Drop unused stuffs Drop unused register macros and coherently use major letters for register address. Signed-off-by: Phi Bang Nguyen --- drivers/video/mt9m114.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/video/mt9m114.c b/drivers/video/mt9m114.c index 5db0fc5d98b..8d9565f0527 100644 --- a/drivers/video/mt9m114.c +++ b/drivers/video/mt9m114.c @@ -22,31 +22,19 @@ LOG_MODULE_REGISTER(mt9m114); /* Sysctl registers */ #define MT9M114_CHIP_ID 0x0000 #define MT9M114_COMMAND_REGISTER 0x0080 -#define MT9M114_COMMAND_REGISTER_APPLY_PATCH (1 << 0) #define MT9M114_COMMAND_REGISTER_SET_STATE (1 << 1) -#define MT9M114_COMMAND_REGISTER_REFRESH (1 << 2) -#define MT9M114_COMMAND_REGISTER_WAIT_FOR_EVENT (1 << 3) #define MT9M114_COMMAND_REGISTER_OK (1 << 15) -#define MT9M114_PAD_CONTROL 0x0032 -#define MT9M114_RST_AND_MISC_CONTROL 0x001A /* Camera Control registers */ -#define MT9M114_CAM_OUTPUT_FORMAT 0xc86c +#define MT9M114_CAM_OUTPUT_FORMAT 0xC86C /* System Manager registers */ -#define MT9M114_SYSMGR_NEXT_STATE 0xdc00 -#define MT9M114_SYSMGR_CURRENT_STATE 0xdc01 -#define MT9M114_SYSMGR_CMD_STATUS 0xdc02 +#define MT9M114_SYSMGR_NEXT_STATE 0xDC00 /* System States */ #define MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE 0x28 -#define MT9M114_SYS_STATE_STREAMING 0x31 #define MT9M114_SYS_STATE_START_STREAMING 0x34 #define MT9M114_SYS_STATE_ENTER_SUSPEND 0x40 -#define MT9M114_SYS_STATE_SUSPENDED 0x41 -#define MT9M114_SYS_STATE_ENTER_STANDBY 0x50 -#define MT9M114_SYS_STATE_STANDBY 0x52 -#define MT9M114_SYS_STATE_LEAVE_STANDBY 0x54 /* Camera output format */ #define MT9M114_CAM_OUTPUT_FORMAT_FORMAT_YUV (0 << 8) From 64ca263bfd494be88fd8183e2a9b1509071837a3 Mon Sep 17 00:00:00 2001 From: Phi Bang Nguyen Date: Thu, 14 Mar 2024 15:57:32 +0100 Subject: [PATCH 1426/2402] drivers: video: mt9m114: Rework to support more resolutions Currently, the driver supports only VGA resolution while 480x272 is needed to match with the display resolution on i.MX RT10XX family. Also, the current framerate is very low, about 3-4 fps without doing anything else with the image buffers (just discarding them). Rework the driver to address the low framerate issue as well as to add support for 480x272 and 1280x720 resolutions. Signed-off-by: Phi Bang Nguyen --- drivers/video/mt9m114.c | 288 +++++++++++++++++++++++++++++----------- 1 file changed, 208 insertions(+), 80 deletions(-) diff --git a/drivers/video/mt9m114.c b/drivers/video/mt9m114.c index 8d9565f0527..01c22feb005 100644 --- a/drivers/video/mt9m114.c +++ b/drivers/video/mt9m114.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2019, Linaro Limited + * Copyright 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,16 +21,30 @@ LOG_MODULE_REGISTER(mt9m114); #define MT9M114_CHIP_ID_VAL 0x2481 /* Sysctl registers */ -#define MT9M114_CHIP_ID 0x0000 -#define MT9M114_COMMAND_REGISTER 0x0080 -#define MT9M114_COMMAND_REGISTER_SET_STATE (1 << 1) -#define MT9M114_COMMAND_REGISTER_OK (1 << 15) +#define MT9M114_CHIP_ID 0x0000 +#define MT9M114_COMMAND_REGISTER 0x0080 +#define MT9M114_COMMAND_REGISTER_SET_STATE (1 << 1) +#define MT9M114_COMMAND_REGISTER_OK (1 << 15) +#define MT9M114_RST_AND_MISC_CONTROL 0x001A /* Camera Control registers */ -#define MT9M114_CAM_OUTPUT_FORMAT 0xC86C +#define MT9M114_CAM_SENSOR_CFG_Y_ADDR_START 0xC800 +#define MT9M114_CAM_SENSOR_CFG_X_ADDR_START 0xC802 +#define MT9M114_CAM_SENSOR_CFG_Y_ADDR_END 0xC804 +#define MT9M114_CAM_SENSOR_CFG_X_ADDR_END 0xC806 +#define MT9M114_CAM_SENSOR_CFG_CPIPE_LAST_ROW 0xC818 +#define MT9M114_CAM_CROP_WINDOW_WIDTH 0xC858 +#define MT9M114_CAM_CROP_WINDOW_HEIGHT 0xC85A +#define MT9M114_CAM_OUTPUT_WIDTH 0xC868 +#define MT9M114_CAM_OUTPUT_HEIGHT 0xC86A +#define MT9M114_CAM_OUTPUT_FORMAT 0xC86C +#define MT9M114_CAM_STAT_AWB_CLIP_WINDOW_XEND 0xC918 +#define MT9M114_CAM_STAT_AWB_CLIP_WINDOW_YEND 0xC91A +#define MT9M114_CAM_STAT_AE_INITIAL_WINDOW_XEND 0xC920 +#define MT9M114_CAM_STAT_AE_INITIAL_WINDOW_YEND 0xC922 /* System Manager registers */ -#define MT9M114_SYSMGR_NEXT_STATE 0xDC00 +#define MT9M114_SYSMGR_NEXT_STATE 0xDC00 /* System States */ #define MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE 0x28 @@ -54,46 +69,119 @@ struct mt9m114_reg { uint32_t value; }; -static struct mt9m114_reg mt9m114_vga_24mhz_pll[] = { - {0x98E, 2, 0x1000}, /* logical_address_access = 0x1000 */ - {0xC97E, 2, 0x01}, /* cam_sysctl_pll_enable = 1 */ - {0xC980, 2, 0x0120}, /* cam_sysctl_pll_divider_m_n = 288 */ - {0xC982, 2, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ - {0xC984, 2, 0x8000}, /* cam_port_output_control = 32776 */ - {0xC800, 2, 0x0000}, /* cam_sensor_cfg_y_addr_start = 0 */ - {0xC802, 2, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ - {0xC804, 2, 0x03CD}, /* cam_sensor_cfg_y_addr_end = 973 */ - {0xC806, 2, 0x050D}, /* cam_sensor_cfg_x_addr_end = 1293 */ - {0xC808, 4, 0x2DC6C00}, /* cam_sensor_cfg_pixclk = 48000000 */ - {0xC80C, 2, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ - {0xC80E, 2, 0x00DB}, /* cam_sensor_cfg_fine_integ_min = 219 */ - {0xC810, 2, 0x07C2}, /* cam_sensor_cfg_fine_integ_max = 1986 */ - {0xC812, 2, 0x02FE}, /* cam_sensor_cfg_frame_length_lines = 766 */ - {0xC814, 2, 0x0845}, /* cam_sensor_cfg_line_length_pck = 2117 */ - {0xC816, 2, 0x0060}, /* cam_sensor_cfg_fine_correction = 96 */ - {0xC818, 2, 0x01E3}, /* cam_sensor_cfg_cpipe_last_row = 483 */ - {0xC826, 2, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ - {0xC834, 2, 0x0110}, /* cam_sensor_control_read_mode = 272 */ - {0xC854, 2, 0x0000}, /* cam_crop_window_xoffset = 0 */ - {0xC856, 2, 0x0000}, /* cam_crop_window_yoffset = 0 */ - {0xC858, 2, 0x0280}, /* cam_crop_window_width = 640 */ - {0xC85A, 2, 0x01E0}, /* cam_crop_window_height = 480 */ - {0xC85C, 1, 0x03}, /* cam_crop_cropmode = 3 */ - {0xC868, 2, 0x0280}, /* cam_output_width = 640 */ - {0xC86A, 2, 0x01E0}, /* cam_output_height = 480 */ - {0xC878, 1, 0x00}, /* cam_aet_aemode = 0 */ - {0xC88C, 2, 0x1D9A}, /* cam_aet_max_frame_rate = 7578 */ - {0xC914, 2, 0x0000}, /* cam_stat_awb_clip_window_xstart = 0 */ - {0xC88E, 2, 0x1D9A}, /* cam_aet_min_frame_rate = 7578 */ - {0xC916, 2, 0x0000}, /* cam_stat_awb_clip_window_ystart = 0 */ - {0xC918, 2, 0x027F}, /* cam_stat_awb_clip_window_xend = 639 */ - {0xC91A, 2, 0x01DF}, /* cam_stat_awb_clip_window_yend = 479 */ - {0xC91C, 2, 0x0000}, /* cam_stat_ae_initial_window_xstart = 0 */ - {0xC91E, 2, 0x0000}, /* cam_stat_ae_initial_window_ystart = 0 */ - {0xC920, 2, 0x007F}, /* cam_stat_ae_initial_window_xend = 127 */ - {0xC922, 2, 0x005F}, /* cam_stat_ae_initial_window_yend = 95 */ +struct mt9m114_resolution_config { + uint16_t width; + uint16_t height; + struct mt9m114_reg *params; +}; + +static struct mt9m114_reg mt9m114_init_config[] = { + {0x098E, 2, 0x1000}, /* LOGICAL_ADDRESS_ACCESS */ + {0xC97E, 1, 0x01}, /* CAM_SYSCTL_PLL_ENABLE */ + {0xC980, 2, 0x0120}, /* CAM_SYSCTL_PLL_DIVIDER_M_N = 288 */ + {0xC982, 2, 0x0700}, /* CAM_SYSCTL_PLL_DIVIDER_P = 1792 */ + {0xC808, 4, 0x2DC6C00}, /* CAM_SENSOR_CFG_PIXCLK = 48 Mhz */ + {0x316A, 2, 0x8270}, /* Auto txlo_row for hot pixel and linear full well optimization */ + {0x316C, 2, 0x8270}, /* Auto txlo for hot pixel and linear full well optimization */ + {0x3ED0, 2, 0x2305}, /* Eclipse setting, ecl range=1, ecl value=2, ivln=3 */ + {0x3ED2, 2, 0x77CF}, /* TX_hi = 12 */ + {0x316E, 2, 0x8202}, /* Auto ecl , threshold 2x, ecl=0 at high gain, ecl=2 for low gain */ + {0x3180, 2, 0x87FF}, /* Enable delta dark */ + {0x30D4, 2, 0x6080}, /* Disable column correction due to AE oscillation problem */ + {0xA802, 2, 0x0008}, /* RESERVED_AE_TRACK_02 */ + {0x3E14, 2, 0xFF39}, /* Enabling pixout clamping to VAA to solve column band issue */ + {0xC80C, 2, 0x0001}, /* CAM_SENSOR_CFG_ROW_SPEED */ + {0xC80E, 2, 0x00DB}, /* CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN = 219 */ + {0xC810, 2, 0x07C2}, /* CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX = 1986 */ + {0xC812, 2, 0x02FE}, /* CAM_SENSOR_CFG_FRAME_LENGTH_LINES = 766 */ + {0xC814, 2, 0x0845}, /* CAM_SENSOR_CFG_LINE_LENGTH_PCK = 2117 */ + {0xC816, 2, 0x0060}, /* CAM_SENSOR_CFG_FINE_CORRECTION = 96 */ + {0xC826, 2, 0x0020}, /* CAM_SENSOR_CFG_REG_0_DATA = 32 */ + {0xC834, 2, 0x0000}, /* CAM_SENSOR_CONTROL_READ_MODE */ + {0xC854, 2, 0x0000}, /* CAM_CROP_WINDOW_XOFFSET */ + {0xC856, 2, 0x0000}, /* CAM_CROP_WINDOW_YOFFSET */ + {0xC85C, 1, 0x03}, /* CAM_CROP_CROPMODE */ + {0xC878, 1, 0x00}, /* CAM_AET_AEMODE */ + {0xC88C, 2, 0x1D9A}, /* CAM_AET_MAX_FRAME_RATE = 7578 */ + {0xC88E, 2, 0x1D9A}, /* CAM_AET_MIN_FRAME_RATE = 7578 */ + {0xC914, 2, 0x0000}, /* CAM_STAT_AWB_CLIP_WINDOW_XSTART */ + {0xC916, 2, 0x0000}, /* CAM_STAT_AWB_CLIP_WINDOW_YSTART */ + {0xC91C, 2, 0x0000}, /* CAM_STAT_AE_INITIAL_WINDOW_XSTART */ + {0xC91E, 2, 0x0000}, /* CAM_STAT_AE_INITIAL_WINDOW_YSTART */ + {0x001E, 2, 0x0777}, /* REG_PAD_SLEW */ + {0xC86E, 2, 0x0038}, /* CAM_OUTPUT_FORMAT_YUV_CLIP for CSI */ + {0xC984, 2, 0x8000}, /* CAM_PORT_OUTPUT_CONTROL, for MIPI CSI-2 interface : 0x8000 */ {/* NULL terminated */}}; +static struct mt9m114_reg mt9m114_480_272[] = { + {MT9M114_CAM_SENSOR_CFG_Y_ADDR_START, 2, 0x00D4}, /* 212 */ + {MT9M114_CAM_SENSOR_CFG_X_ADDR_START, 2, 0x00A4}, /* 164 */ + {MT9M114_CAM_SENSOR_CFG_Y_ADDR_END, 2, 0x02FB}, /* 763 */ + {MT9M114_CAM_SENSOR_CFG_X_ADDR_END, 2, 0x046B}, /* 1131 */ + {MT9M114_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 0x0223}, /* 547 */ + {MT9M114_CAM_CROP_WINDOW_WIDTH, 2, 0x03C0}, /* 960 */ + {MT9M114_CAM_CROP_WINDOW_HEIGHT, 2, 0x0220}, /* 544 */ + {MT9M114_CAM_OUTPUT_WIDTH, 2, 0x01E0}, /* 480 */ + {MT9M114_CAM_OUTPUT_HEIGHT, 2, 0x0110}, /* 272 */ + {MT9M114_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 0x01DF}, /* 479 */ + {MT9M114_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 0x010F}, /* 271 */ + {MT9M114_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 0x005F}, /* 95 */ + {MT9M114_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 0x0035}, /* 53 */ + {/* NULL terminated */}}; + +static struct mt9m114_reg mt9m114_640_480[] = { + {MT9M114_CAM_SENSOR_CFG_Y_ADDR_START, 2, 0x0000}, /* 0 */ + {MT9M114_CAM_SENSOR_CFG_X_ADDR_START, 2, 0x0000}, /* 0 */ + {MT9M114_CAM_SENSOR_CFG_Y_ADDR_END, 2, 0x03CD}, /* 973 */ + {MT9M114_CAM_SENSOR_CFG_X_ADDR_END, 2, 0x050D}, /* 1293 */ + {MT9M114_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 0x01E3}, /* 483 */ + {MT9M114_CAM_CROP_WINDOW_WIDTH, 2, 0x0280}, /* 640 */ + {MT9M114_CAM_CROP_WINDOW_HEIGHT, 2, 0x01E0}, /* 480 */ + {MT9M114_CAM_OUTPUT_WIDTH, 2, 0x0280}, /* 640 */ + {MT9M114_CAM_OUTPUT_HEIGHT, 2, 0x01E0}, /* 480 */ + {MT9M114_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 0x027F}, /* 639 */ + {MT9M114_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 0x01DF}, /* 479 */ + {MT9M114_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 0x007F}, /* 127 */ + {MT9M114_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 0x005F}, /* 95 */ + {/* NULL terminated */}}; + +static struct mt9m114_reg mt9m114_1280_720[] = { + {MT9M114_CAM_SENSOR_CFG_Y_ADDR_START, 2, 0x007C}, /* 124 */ + {MT9M114_CAM_SENSOR_CFG_X_ADDR_START, 2, 0x0004}, /* 4 */ + {MT9M114_CAM_SENSOR_CFG_Y_ADDR_END, 2, 0x0353}, /* 851 */ + {MT9M114_CAM_SENSOR_CFG_X_ADDR_END, 2, 0x050B}, /* 1291 */ + {MT9M114_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 0x02D3}, /* 723 */ + {MT9M114_CAM_CROP_WINDOW_WIDTH, 2, 0x0500}, /* 1280 */ + {MT9M114_CAM_CROP_WINDOW_HEIGHT, 2, 0x02D0}, /* 720 */ + {MT9M114_CAM_OUTPUT_WIDTH, 2, 0x0500}, /* 1280 */ + {MT9M114_CAM_OUTPUT_HEIGHT, 2, 0x02D0}, /* 720 */ + {MT9M114_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 0x04FF}, /* 1279 */ + {MT9M114_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 0x02CF}, /* 719 */ + {MT9M114_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 0x00FF}, /* 255 */ + {MT9M114_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 0x008F}, /* 143 */ + {/* NULL terminated */}}; + +static struct mt9m114_resolution_config resolutionConfigs[] = { + {.width = 480, .height = 272, .params = mt9m114_480_272}, + {.width = 640, .height = 480, .params = mt9m114_640_480}, + {.width = 1280, .height = 720, .params = mt9m114_1280_720}, +}; + +#define MT9M114_VIDEO_FORMAT_CAP(width, height, format) \ + { \ + .pixelformat = (format), .width_min = (width), .width_max = (width), \ + .height_min = (height), .height_max = (height), .width_step = 0, .height_step = 0 \ + } + +static const struct video_format_cap fmts[] = { + MT9M114_VIDEO_FORMAT_CAP(480, 272, VIDEO_PIX_FMT_RGB565), + MT9M114_VIDEO_FORMAT_CAP(480, 272, VIDEO_PIX_FMT_YUYV), + MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_RGB565), + MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_YUYV), + MT9M114_VIDEO_FORMAT_CAP(1280, 720, VIDEO_PIX_FMT_RGB565), + MT9M114_VIDEO_FORMAT_CAP(1280, 720, VIDEO_PIX_FMT_YUYV), + {0}}; + static inline int i2c_burst_read16_dt(const struct i2c_dt_spec *spec, uint16_t start_addr, uint8_t *buf, uint32_t num_bytes) { @@ -175,6 +263,22 @@ static int mt9m114_read_reg(const struct device *dev, uint16_t reg_addr, uint8_t return 0; } +static int mt9m114_modify_reg(const struct device *dev, const uint16_t addr, const uint8_t mask, + const uint8_t val) +{ + uint8_t oldVal; + uint8_t newVal; + int ret = mt9m114_read_reg(dev, addr, sizeof(oldVal), &oldVal); + + if (ret) { + return ret; + } + + newVal = (oldVal & ~mask) | (val & mask); + + return mt9m114_write_reg(dev, addr, sizeof(newVal), &newVal); +} + static int mt9m114_write_all(const struct device *dev, struct mt9m114_reg *reg) { int i = 0; @@ -193,6 +297,26 @@ static int mt9m114_write_all(const struct device *dev, struct mt9m114_reg *reg) return 0; } +static int mt9m114_software_reset(const struct device *dev) +{ + int ret = mt9m114_modify_reg(dev, MT9M114_RST_AND_MISC_CONTROL, 0x01, 0x01); + + if (ret) { + return ret; + } + + k_sleep(K_MSEC(1)); + + ret = mt9m114_modify_reg(dev, MT9M114_RST_AND_MISC_CONTROL, 0x01, 0x00); + if (ret) { + return ret; + } + + k_sleep(K_MSEC(45)); + + return 0; +} + static int mt9m114_set_state(const struct device *dev, uint8_t state) { uint16_t val; @@ -251,9 +375,6 @@ static int mt9m114_set_output_format(const struct device *dev, int pixel_format) output_format = (MT9M114_CAM_OUTPUT_FORMAT_FORMAT_YUV | (1U << 1U)); } else if (pixel_format == VIDEO_PIX_FMT_RGB565) { output_format = (MT9M114_CAM_OUTPUT_FORMAT_FORMAT_RGB | (1U << 1U)); - } else { - LOG_ERR("Image format not supported"); - return -ENOTSUP; } ret = mt9m114_write_reg(dev, MT9M114_CAM_OUTPUT_FORMAT, sizeof(output_format), @@ -267,16 +388,19 @@ static int mt9m114_set_fmt(const struct device *dev, enum video_endpoint_id ep, { struct mt9m114_data *drv_data = dev->data; int ret; + int i = 0; - /* we support RGB565 and YUV output pixel formats for now */ - if (fmt->pixelformat != VIDEO_PIX_FMT_RGB565 && fmt->pixelformat != VIDEO_PIX_FMT_YUYV) { - LOG_ERR("Unsupported output pixel format"); - return -ENOTSUP; + while (fmts[i].pixelformat) { + if (fmt->pixelformat == fmts[i].pixelformat && fmt->width >= fmts[i].width_min && + fmt->width <= fmts[i].width_max && fmt->height >= fmts[i].height_min && + fmt->height <= fmts[i].height_max) { + break; + } + i++; } - /* we only support one format size for now (VGA) */ - if (fmt->height != 480 || fmt->width != 640) { - LOG_ERR("Unsupported output size format"); + if (i == (ARRAY_SIZE(fmts) - 1)) { + LOG_ERR("Unsupported pixel format or resolution"); return -ENOTSUP; } @@ -287,24 +411,29 @@ static int mt9m114_set_fmt(const struct device *dev, enum video_endpoint_id ep, drv_data->fmt = *fmt; - /* Configure Sensor */ - ret = mt9m114_write_all(dev, mt9m114_vga_24mhz_pll); + /* Set output pixel format */ + ret = mt9m114_set_output_format(dev, fmt->pixelformat); if (ret) { - LOG_ERR("Unable to write mt9m114 config"); + LOG_ERR("Unable to set pixel format"); return ret; } - /* Set output format */ - ret = mt9m114_set_output_format(dev, fmt->pixelformat); - if (ret) { - LOG_ERR("Unable to set output format"); - return ret; + /* Set output resolution */ + for (i = 0; i < ARRAY_SIZE(resolutionConfigs); i++) { + if (fmt->width == resolutionConfigs[i].width && + fmt->height == resolutionConfigs[i].height) { + ret = mt9m114_write_all(dev, resolutionConfigs[i].params); + if (ret) { + LOG_ERR("Unable to set resolution"); + return ret; + } + + break; + } } /* Apply Config */ - mt9m114_set_state(dev, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE); - - return 0; + return mt9m114_set_state(dev, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE); } static int mt9m114_get_fmt(const struct device *dev, enum video_endpoint_id ep, @@ -327,17 +456,6 @@ static int mt9m114_stream_stop(const struct device *dev) return mt9m114_set_state(dev, MT9M114_SYS_STATE_ENTER_SUSPEND); } -#define MT9M114_VIDEO_FORMAT_CAP(width, height, format) \ - { \ - .pixelformat = (format), .width_min = (width), .width_max = (width), \ - .height_min = (height), .height_max = (height), .width_step = 0, .height_step = 0 \ - } - -static const struct video_format_cap fmts[] = { - MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_RGB565), /* VGA RGB565 */ - MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_YUYV), /* VGA YUYV */ - {0}}; - static int mt9m114_get_caps(const struct device *dev, enum video_endpoint_id ep, struct video_caps *caps) { @@ -373,11 +491,21 @@ static int mt9m114_init(const struct device *dev) return -ENODEV; } - /* set default/init format VGA RGB565 */ + /* SW reset */ + mt9m114_software_reset(dev); + + /* Init registers */ + ret = mt9m114_write_all(dev, mt9m114_init_config); + if (ret) { + LOG_ERR("Unable to initialize mt9m114 config"); + return ret; + } + + /* Set default format to 480x272 RGB565 */ fmt.pixelformat = VIDEO_PIX_FMT_RGB565; - fmt.width = 640; - fmt.height = 480; - fmt.pitch = 640 * 2; + fmt.width = 480; + fmt.height = 272; + fmt.pitch = fmt.width * 2; ret = mt9m114_set_fmt(dev, VIDEO_EP_OUT, &fmt); if (ret) { From 9b0510cea9bed6a20e43b0c055c8bcb6ae72f239 Mon Sep 17 00:00:00 2001 From: Rick Bruyninckx Date: Thu, 14 Mar 2024 08:52:01 +0100 Subject: [PATCH 1427/2402] drivers: led: add output current configuration to ti,lp5562 Add Output current configuration for led channels to the TI lp5562 driver. Signed-off-by: Rick Bruyninckx --- drivers/led/lp5562.c | 45 +++++++++++++++++++++++++++++++++ dts/bindings/led/ti,lp5562.yaml | 22 ++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/drivers/led/lp5562.c b/drivers/led/lp5562.c index 222a9659d6a..d1a1f4031fb 100644 --- a/drivers/led/lp5562.c +++ b/drivers/led/lp5562.c @@ -81,6 +81,10 @@ LOG_MODULE_REGISTER(lp5562); #define LP5562_MIN_BRIGHTNESS 0 #define LP5562_MAX_BRIGHTNESS 100 +/* Output current limits in 0.1 mA */ +#define LP5562_MIN_CURRENT_SETTING 0 +#define LP5562_MAX_CURRENT_SETTING 255 + /* Values for ENABLE register. */ #define LP5562_ENABLE_CHIP_EN (1 << 6) #define LP5562_ENABLE_LOG_EN (1 << 7) @@ -159,6 +163,10 @@ enum lp5562_engine_fade_dirs { struct lp5562_config { struct i2c_dt_spec bus; + uint8_t r_current; + uint8_t g_current; + uint8_t b_current; + uint8_t w_current; }; struct lp5562_data { @@ -895,11 +903,30 @@ static inline int lp5562_led_off(const struct device *dev, uint32_t led) return lp5562_led_set_brightness(dev, led, dev_data->min_brightness); } +static int lp5562_led_update_current(const struct device *dev) +{ + const struct lp5562_config *config = dev->config; + int ret; + uint8_t tx_buf[4] = { + LP5562_B_CURRENT, + config->b_current, + config->g_current, + config->r_current }; + + ret = i2c_write_dt(&config->bus, tx_buf, sizeof(tx_buf)); + if (ret == 0) { + ret = i2c_reg_write_byte_dt(&config->bus, LP5562_W_CURRENT, config->w_current); + } + + return ret; +} + static int lp5562_led_init(const struct device *dev) { const struct lp5562_config *config = dev->config; struct lp5562_data *data = dev->data; struct led_data *dev_data = &data->dev_data; + int ret; if (!device_is_ready(config->bus.bus)) { LOG_ERR("I2C device not ready"); @@ -912,6 +939,12 @@ static int lp5562_led_init(const struct device *dev) dev_data->min_brightness = LP5562_MIN_BRIGHTNESS; dev_data->max_brightness = LP5562_MAX_BRIGHTNESS; + ret = lp5562_led_update_current(dev); + if (ret) { + LOG_ERR("Setting current setting LP5562 LED chip failed."); + return ret; + } + if (i2c_reg_write_byte_dt(&config->bus, LP5562_ENABLE, LP5562_ENABLE_CHIP_EN)) { LOG_ERR("Enabling LP5562 LED chip failed."); @@ -946,8 +979,20 @@ static const struct led_driver_api lp5562_led_api = { }; #define LP5562_DEFINE(id) \ + BUILD_ASSERT(DT_INST_PROP(id, red_output_current) <= LP5562_MAX_CURRENT_SETTING,\ + "Red channel current must be between 0 and 25.5 mA."); \ + BUILD_ASSERT(DT_INST_PROP(id, green_output_current) <= LP5562_MAX_CURRENT_SETTING,\ + "Green channel current must be between 0 and 25.5 mA."); \ + BUILD_ASSERT(DT_INST_PROP(id, blue_output_current) <= LP5562_MAX_CURRENT_SETTING,\ + "Blue channel current must be between 0 and 25.5 mA."); \ + BUILD_ASSERT(DT_INST_PROP(id, white_output_current) <= LP5562_MAX_CURRENT_SETTING,\ + "White channel current must be between 0 and 25.5 mA."); \ static const struct lp5562_config lp5562_config_##id = { \ .bus = I2C_DT_SPEC_INST_GET(id), \ + .r_current = DT_INST_PROP(id, red_output_current), \ + .g_current = DT_INST_PROP(id, green_output_current), \ + .b_current = DT_INST_PROP(id, blue_output_current), \ + .w_current = DT_INST_PROP(id, white_output_current), \ }; \ \ struct lp5562_data lp5562_data_##id; \ diff --git a/dts/bindings/led/ti,lp5562.yaml b/dts/bindings/led/ti,lp5562.yaml index 3264d3e9a55..b2b0c4b484e 100644 --- a/dts/bindings/led/ti,lp5562.yaml +++ b/dts/bindings/led/ti,lp5562.yaml @@ -3,3 +3,25 @@ description: TI LP5562 LED compatible: "ti,lp5562" include: i2c-device.yaml + +properties: + red-output-current: + type: int + default: 175 + description: Output current of red channel in 0.1 mA (0-25.5 mA). + Default value is the power-on default. Valid range = 0 - 255 + green-output-current: + type: int + default: 175 + description: Output current of green channel in 0.1 mA (0-25.5 mA) + Default value is the power-on default. Valid range = 0 - 255 + blue-output-current: + type: int + default: 175 + description: Output current of blue channel in 0.1 mA (0-25.5 mA) + Default value is the power-on default. Valid range = 0 - 255 + white-output-current: + type: int + default: 175 + description: Output current of white channel in 0.1 mA (0-25.5 mA) + Default value is the power-on default. Valid range = 0 - 255 From d791526dd8379636c0aab8def4c021e874189b14 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Wed, 7 Feb 2024 15:32:11 +0100 Subject: [PATCH 1428/2402] drivers: charger: charger_max20355: fix configuration Maximum charging current is selected with an external resistor in the MAX20335 charger. Therefore it is not possible to configure it with software directly. There is only a capability to limit current set with hardware but configuration of the limiter is not straight-forward. To reflect real functionality, drop usage of `constant-charge-current-max-microamp` property as an required one and use custom `chgin-to-sys-current-limit-microamp` instead. Use enum in binding file to signalize improper values at compile time. Drop support for `CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA` API property since this cannot be handled. The `max20335_get_constant_charge_current()` function become useless so remove it. Signed-off-by: Lukasz Madej --- doc/releases/migration-guide-3.7.rst | 6 ++ doc/releases/release-notes-3.7.rst | 4 ++ drivers/charger/charger_max20335.c | 58 +++---------------- .../charger/maxim,max20335-charger.yaml | 13 ++++- tests/drivers/build_all/charger/i2c.dtsi | 2 +- 5 files changed, 29 insertions(+), 54 deletions(-) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index ab7ff0ef785..cc9292d3d1b 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -74,6 +74,12 @@ Analog-to-Digital Converter (ADC) Bluetooth HCI ============= +Charger +======= + +* Dropped ``constant-charge-current-max-microamp`` property in ``charger_max20335`` driver because + it did not reflect real chip functionality. + Controller Area Network (CAN) ============================= diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index b4b7c52b098..d3ba37f1cba 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -93,6 +93,10 @@ Drivers and Sensors validating the bitrate. * Made the ``sample-point`` and ``sample-point-data`` devicetree properties optional. +* Charger + + * Added ``chgin-to-sys-current-limit-microamp`` property to ``maxim,max20335-charger``. + * Clock control * Counter diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index 6a4b50acf93..e9f3bc7ad1a 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -43,8 +43,8 @@ LOG_MODULE_REGISTER(max20335_charger); struct charger_max20335_config { struct i2c_dt_spec bus; struct gpio_dt_spec int_gpio; - uint32_t max_ichg_ua; uint32_t max_vreg_uv; + uint32_t max_ichgin_to_sys_ua; }; struct charger_max20335_data { @@ -57,7 +57,6 @@ struct charger_max20335_data { charger_status_notifier_t charger_status_notifier; charger_online_notifier_t charger_online_notifier; bool charger_enabled; - uint32_t charge_current_ua; uint32_t charge_voltage_uv; }; @@ -173,13 +172,12 @@ static int max20335_set_constant_charge_voltage(const struct device *dev, val); } -static int max20335_set_constant_charge_current(const struct device *dev, - uint32_t current_ua) +static int max20335_set_chgin_to_sys_current_limit(const struct device *dev, uint32_t current_ua) { const struct charger_max20335_config *const config = dev->config; uint8_t val; - if (current_ua > config->max_ichg_ua) { + if (current_ua > config->max_ichgin_to_sys_ua) { LOG_WRN("Exceeded max constant charge current!"); return -EINVAL; } @@ -209,38 +207,6 @@ static int max20335_set_constant_charge_current(const struct device *dev, val); } -static int __maybe_unused max20335_get_constant_charge_current(const struct device *dev, - uint32_t *current_ua) -{ - const struct charger_max20335_config *const config = dev->config; - uint8_t val; - int ret; - - ret = i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_ILIMCNTL, &val); - if (ret) { - return ret; - } - - switch (val) { - case 0x00: - *current_ua = 0; - break; - case 0x01: - *current_ua = 100000; - break; - case 0x02: - *current_ua = 500000; - break; - case 0x03: - *current_ua = 1000000; - break; - default: - return -ENOTSUP; - }; - - return 0; -} - static int __maybe_unused max20335_get_constant_charge_voltage(const struct device *dev, uint32_t *voltage_uv) { @@ -317,7 +283,6 @@ static int max20335_init_properties(const struct device *dev) const struct charger_max20335_config *config = dev->config; int ret; - data->charge_current_ua = config->max_ichg_ua; data->charge_voltage_uv = config->max_vreg_uv; data->charger_enabled = true; @@ -339,11 +304,12 @@ static int max20335_init_properties(const struct device *dev) static int max20335_update_properties(const struct device *dev) { struct charger_max20335_data *data = dev->data; + const struct charger_max20335_config *config = dev->config; int ret; - ret = max20335_set_constant_charge_current(dev, data->charge_current_ua); + ret = max20335_set_chgin_to_sys_current_limit(dev, config->max_ichgin_to_sys_ua); if (ret < 0) { - LOG_ERR("Failed to set charge current: %d", ret); + LOG_ERR("Failed to set chgin-to-sys current limit: %d", ret); return ret; } @@ -374,9 +340,6 @@ static int max20335_get_prop(const struct device *dev, charger_prop_t prop, case CHARGER_PROP_STATUS: val->status = data->charger_status; return 0; - case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA: - val->const_charge_current_ua = data->charge_current_ua; - return 0; case CHARGER_PROP_CONSTANT_CHARGE_VOLTAGE_UV: val->const_charge_voltage_uv = data->charge_voltage_uv; return 0; @@ -392,13 +355,6 @@ static int max20335_set_prop(const struct device *dev, charger_prop_t prop, int ret; switch (prop) { - case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA: - ret = max20335_set_constant_charge_current(dev, val->const_charge_current_ua); - if (ret == 0) { - data->charge_current_ua = val->const_charge_current_ua; - } - - return ret; case CHARGER_PROP_CONSTANT_CHARGE_VOLTAGE_UV: ret = max20335_set_constant_charge_voltage(dev, val->const_charge_voltage_uv); if (ret == 0) { @@ -580,8 +536,8 @@ static const struct charger_driver_api max20335_driver_api = { static const struct charger_max20335_config charger_max20335_config_##inst = { \ .bus = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \ .int_gpio = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \ - .max_ichg_ua = DT_INST_PROP(inst, constant_charge_current_max_microamp), \ .max_vreg_uv = DT_INST_PROP(inst, constant_charge_voltage_max_microvolt), \ + .max_ichgin_to_sys_ua = DT_INST_PROP(inst, chgin_to_sys_current_limit_microamp),\ }; \ \ DEVICE_DT_INST_DEFINE(inst, &max20335_init, NULL, &charger_max20335_data_##inst, \ diff --git a/dts/bindings/charger/maxim,max20335-charger.yaml b/dts/bindings/charger/maxim,max20335-charger.yaml index 200951b88c8..2fee14229dc 100644 --- a/dts/bindings/charger/maxim,max20335-charger.yaml +++ b/dts/bindings/charger/maxim,max20335-charger.yaml @@ -8,11 +8,20 @@ include: battery.yaml compatible: "maxim,max20335-charger" properties: - constant-charge-current-max-microamp: + constant-charge-voltage-max-microvolt: required: true - constant-charge-voltage-max-microvolt: + chgin-to-sys-current-limit-microamp: + type: int required: true + enum: + - 0 + - 100000 + - 500000 + - 1000000 + description: | + CHGIN to SYS path current limitter configuration. + Refer to ILimCntl register description for details. int-gpios: type: phandle-array diff --git a/tests/drivers/build_all/charger/i2c.dtsi b/tests/drivers/build_all/charger/i2c.dtsi index 42f7cdf1919..f3761ff5be9 100644 --- a/tests/drivers/build_all/charger/i2c.dtsi +++ b/tests/drivers/build_all/charger/i2c.dtsi @@ -24,7 +24,7 @@ max20335@1 { charger: charger { compatible = "maxim,max20335-charger"; - constant-charge-current-max-microamp = <100000>; + chgin-to-sys-current-limit-microamp = <100000>; constant-charge-voltage-max-microvolt = <4050000>; int-gpios = <&test_gpio 0 0>; }; From 20bfa7d38d35809b3c841a891c6babd86ebeaa0f Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Wed, 7 Feb 2024 15:49:33 +0100 Subject: [PATCH 1429/2402] dts: bindings: charger: max20335: use enum for property Add enum for `constant-charge-voltage-max-microvolt` property to signalize improper values given with device tree at compile time. Signed-off-by: Lukasz Madej --- doc/releases/migration-guide-3.7.rst | 3 +++ dts/bindings/charger/maxim,max20335-charger.yaml | 13 +++++++++++++ 2 files changed, 16 insertions(+) diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index cc9292d3d1b..b5d3d74908f 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -80,6 +80,9 @@ Charger * Dropped ``constant-charge-current-max-microamp`` property in ``charger_max20335`` driver because it did not reflect real chip functionality. +* Added enum key to ``constant-charge-voltage-max-microvolt`` property in ``maxim,max20335-charger`` + binding to indicate invalid devicetree values at build time. + Controller Area Network (CAN) ============================= diff --git a/dts/bindings/charger/maxim,max20335-charger.yaml b/dts/bindings/charger/maxim,max20335-charger.yaml index 2fee14229dc..8020eac4f22 100644 --- a/dts/bindings/charger/maxim,max20335-charger.yaml +++ b/dts/bindings/charger/maxim,max20335-charger.yaml @@ -10,6 +10,19 @@ compatible: "maxim,max20335-charger" properties: constant-charge-voltage-max-microvolt: required: true + enum: + - 4050000 + - 4100000 + - 4150000 + - 4200000 + - 4250000 + - 4300000 + - 4350000 + - 4400000 + - 4450000 + - 4500000 + - 4550000 + - 4600000 chgin-to-sys-current-limit-microamp: type: int From 82169bba15742681c7df024266f89c54ebdad038 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Wed, 7 Feb 2024 15:58:57 +0100 Subject: [PATCH 1430/2402] drivers: charger: charger_max20335: drop redundant validation `max20335_get_constant_charge_current()` and `max20335_set_chgin_to_sys_current_limit()` functions has redundant input values validation. Drop not important ones to make the code clean. While on it remove `max20335_get_constant_charge_voltage()` function since it become useless. Signed-off-by: Lukasz Madej --- drivers/charger/charger_max20335.c | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index e9f3bc7ad1a..c77e197acd9 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -154,11 +154,6 @@ static int max20335_set_constant_charge_voltage(const struct device *dev, uint8_t val; int ret; - if (voltage_uv > config->max_vreg_uv) { - LOG_WRN("Exceeded max constant charge voltage!"); - return -EINVAL; - } - ret = linear_range_get_index(&charger_uv_range, voltage_uv, &idx); if (ret == -EINVAL) { return ret; @@ -177,11 +172,6 @@ static int max20335_set_chgin_to_sys_current_limit(const struct device *dev, uin const struct charger_max20335_config *const config = dev->config; uint8_t val; - if (current_ua > config->max_ichgin_to_sys_ua) { - LOG_WRN("Exceeded max constant charge current!"); - return -EINVAL; - } - switch (current_ua) { case 0: val = 0x00; @@ -207,23 +197,6 @@ static int max20335_set_chgin_to_sys_current_limit(const struct device *dev, uin val); } -static int __maybe_unused max20335_get_constant_charge_voltage(const struct device *dev, - uint32_t *voltage_uv) -{ - const struct charger_max20335_config *const config = dev->config; - uint8_t val; - int ret; - - ret = i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_CHG_CNTL_A, &val); - if (ret) { - return ret; - } - - val = FIELD_GET(MAX20335_CHGCNTLA_BAT_REG_CFG_MASK, val); - - return linear_range_get_value(&charger_uv_range, val, voltage_uv); -} - static int max20335_set_enabled(const struct device *dev, bool enable) { struct charger_max20335_data *data = dev->data; From b2c460f2741780780bb7e8efe2d88e1cf4cc3ec6 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Wed, 7 Feb 2024 18:08:08 +0100 Subject: [PATCH 1431/2402] drivers: charger: charger_max20335: fix linear range usage Fix validation of `linear_range_get_index()` results. The function can resturn both 0 or -ERANGE but -EINVAL is never returned. Use comparison against 0 to make the validation robust. Use valid maximum index for the linear range. The 0x0C is reserved value and should not be used. Therefore replace it with 0x0B. Signed-off-by: Lukasz Madej --- drivers/charger/charger_max20335.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index c77e197acd9..6749d9d98e4 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -36,7 +36,7 @@ LOG_MODULE_REGISTER(max20335_charger); #define MAX20335_REG_CVC_VREG_MIN_UV 4050000U #define MAX20335_REG_CVC_VREG_STEP_UV 50000U #define MAX20335_REG_CVC_VREG_MIN_IDX 0x0U -#define MAX20335_REG_CVC_VREG_MAX_IDX 0x0CU +#define MAX20335_REG_CVC_VREG_MAX_IDX 0x0BU #define INT_ENABLE_DELAY K_MSEC(500) @@ -155,7 +155,7 @@ static int max20335_set_constant_charge_voltage(const struct device *dev, int ret; ret = linear_range_get_index(&charger_uv_range, voltage_uv, &idx); - if (ret == -EINVAL) { + if (ret < 0) { return ret; } From c7c168b378480fc11a8c59fc25629a9dc07f0717 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Wed, 7 Feb 2024 18:16:56 +0100 Subject: [PATCH 1432/2402] drivers: charger: charger_max20335: rename macro to reduce ambiguity The ILimCntl name can be understood as both register name and its field name. Therefore it is better to change macro name so it contains both register and field name. Second field of this register will be also utilized by this driver in the future and new code will be aligned to this naming convention. Signed-off-by: Lukasz Madej --- drivers/charger/charger_max20335.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index 6749d9d98e4..0a4615241f2 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -28,7 +28,7 @@ LOG_MODULE_REGISTER(max20335_charger); #define MAX20335_REG_ILIMCNTL 0x09 #define MAX20335_REG_CHG_CNTL_A 0x0A #define MAX20335_CHGCNTLA_BAT_REG_CFG_MASK GENMASK(4, 1) -#define MAX20335_ILIMCNTL_MASK GENMASK(1, 0) +#define MAX20335_ILIMCNTL_ILIMCNTL_MASK GENMASK(1, 0) #define MAX20335_STATUS_A_CHG_STAT_MASK GENMASK(2, 0) #define MAX20335_STATUS_B_USB_OK_MASK BIT(3) #define MAX20335_CHRG_EN_MASK BIT(0) @@ -189,11 +189,11 @@ static int max20335_set_chgin_to_sys_current_limit(const struct device *dev, uin return -ENOTSUP; }; - val = FIELD_PREP(MAX20335_ILIMCNTL_MASK, val); + val = FIELD_PREP(MAX20335_ILIMCNTL_ILIMCNTL_MASK, val); return i2c_reg_update_byte_dt(&config->bus, MAX20335_REG_ILIMCNTL, - MAX20335_ILIMCNTL_MASK, + MAX20335_ILIMCNTL_ILIMCNTL_MASK, val); } From e43f6f5d2abdd21cf5935a74b10cfb36df3f0f85 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Fri, 9 Feb 2024 17:20:49 +0100 Subject: [PATCH 1433/2402] drivers: charger: charger_max20335: rename register related macros Rename macros related to charger harware registers to make them consistent. Signed-off-by: Lukasz Madej --- drivers/charger/charger_max20335.c | 64 +++++++++++++++--------------- 1 file changed, 33 insertions(+), 31 deletions(-) diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index 0a4615241f2..a715aabae1b 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -17,22 +17,24 @@ #include "zephyr/logging/log.h" LOG_MODULE_REGISTER(max20335_charger); -#define MAX20335_REG_STATUS_A 0x02 -#define MAX20335_REG_STATUS_B 0x03 -#define MAX20335_REG_INT_A 0x05 -#define MAX20335_REG_INT_B 0x06 -#define MAX20335_INT_A_USB_OK_MASK BIT(3) -#define MAX20335_INT_A_CHG_STAT_MASK BIT(6) -#define MAX20335_REG_INT_MASK_A 0x07 -#define MAX20335_REG_INT_MASK_B 0x08 +#define MAX20335_REG_STATUSA 0x02 +#define MAX20335_REG_STATUSB 0x03 +#define MAX20335_REG_INTA 0x05 +#define MAX20335_REG_INTB 0x06 +#define MAX20335_REG_INTMASKA 0x07 +#define MAX20335_REG_INTMASKB 0x08 #define MAX20335_REG_ILIMCNTL 0x09 -#define MAX20335_REG_CHG_CNTL_A 0x0A -#define MAX20335_CHGCNTLA_BAT_REG_CFG_MASK GENMASK(4, 1) +#define MAX20335_REG_CHGCNTLA 0x0A + +#define MAX20335_INTA_USBOK_MASK BIT(3) +#define MAX20335_INTA_CHGSTAT_MASK BIT(6) #define MAX20335_ILIMCNTL_ILIMCNTL_MASK GENMASK(1, 0) -#define MAX20335_STATUS_A_CHG_STAT_MASK GENMASK(2, 0) -#define MAX20335_STATUS_B_USB_OK_MASK BIT(3) -#define MAX20335_CHRG_EN_MASK BIT(0) -#define MAX20335_CHRG_EN BIT(0) +#define MAX20335_STATUSA_CHGSTAT_MASK GENMASK(2, 0) +#define MAX20335_STATUSB_USBOK_MASK BIT(3) +#define MAX20335_CHGCNTLA_BATREG_MASK GENMASK(4, 1) +#define MAX20335_CHGCNTLA_CHRGEN_MASK BIT(0) +#define MAX20335_CHGCNTLA_CHRGEN BIT(0) + #define MAX20335_REG_CVC_VREG_MIN_UV 4050000U #define MAX20335_REG_CVC_VREG_STEP_UV 50000U #define MAX20335_REG_CVC_VREG_MIN_IDX 0x0U @@ -82,12 +84,12 @@ static int max20335_get_charger_status(const struct device *dev, enum charger_st uint8_t val; int ret; - ret = i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_STATUS_A, &val); + ret = i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_STATUSA, &val); if (ret) { return ret; } - val = FIELD_GET(MAX20335_STATUS_A_CHG_STAT_MASK, val); + val = FIELD_GET(MAX20335_STATUSA_CHGSTAT_MASK, val); switch (val) { case MAX20335_CHARGER_OFF: @@ -127,12 +129,12 @@ static int max20335_get_charger_online(const struct device *dev, enum charger_on uint8_t val; int ret; - ret = i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_STATUS_B, &val); + ret = i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_STATUSB, &val); if (ret) { return ret; } - val = FIELD_GET(MAX20335_STATUS_B_USB_OK_MASK, val); + val = FIELD_GET(MAX20335_STATUSB_USBOK_MASK, val); switch (val) { case MAX20335_CHGIN_IN_PRESENT_AND_VALID: @@ -159,11 +161,11 @@ static int max20335_set_constant_charge_voltage(const struct device *dev, return ret; } - val = FIELD_PREP(MAX20335_CHGCNTLA_BAT_REG_CFG_MASK, idx); + val = FIELD_PREP(MAX20335_CHGCNTLA_BATREG_MASK, idx); return i2c_reg_update_byte_dt(&config->bus, - MAX20335_REG_CHG_CNTL_A, - MAX20335_CHGCNTLA_BAT_REG_CFG_MASK, + MAX20335_REG_CHGCNTLA, + MAX20335_CHGCNTLA_BATREG_MASK, val); } @@ -205,9 +207,9 @@ static int max20335_set_enabled(const struct device *dev, bool enable) data->charger_enabled = enable; return i2c_reg_update_byte_dt(&config->bus, - MAX20335_REG_CHG_CNTL_A, - MAX20335_CHRG_EN_MASK, - enable ? MAX20335_CHRG_EN : 0); + MAX20335_REG_CHGCNTLA, + MAX20335_CHGCNTLA_CHRGEN_MASK, + enable ? MAX20335_CHGCNTLA_CHRGEN : 0); } static int max20335_get_interrupt_source(const struct device *dev, uint8_t *int_a, uint8_t *int_b) @@ -220,19 +222,19 @@ static int max20335_get_interrupt_source(const struct device *dev, uint8_t *int_ /* Both INT_A and INT_B registers need to be read to clear all int flags */ int_src = (int_a != NULL) ? int_a : &dummy; - ret = i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_INT_A, int_src); + ret = i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_INTA, int_src); if (ret < 0) { return ret; } int_src = (int_b != NULL) ? int_b : &dummy; - return i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_INT_B, int_src); + return i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_INTB, int_src); } static int max20335_enable_interrupts(const struct device *dev) { - enum {MASK_A_VAL_ENABLE = 0xFF}; + enum {MASKA_VAL_ENABLE = 0xFF}; const struct charger_max20335_config *config = dev->config; int ret; @@ -242,12 +244,12 @@ static int max20335_enable_interrupts(const struct device *dev) return ret; } - ret = i2c_reg_write_byte_dt(&config->bus, MAX20335_REG_INT_MASK_A, MASK_A_VAL_ENABLE); + ret = i2c_reg_write_byte_dt(&config->bus, MAX20335_REG_INTMASKA, MASKA_VAL_ENABLE); if (ret < 0) { return ret; } - return i2c_reg_write_byte_dt(&config->bus, MAX20335_REG_INT_MASK_B, 0); + return i2c_reg_write_byte_dt(&config->bus, MAX20335_REG_INTMASKB, 0); } static int max20335_init_properties(const struct device *dev) @@ -391,7 +393,7 @@ static void max20335_int_routine_work_handler(struct k_work *work) return; } - if ((int_src_a & MAX20335_INT_A_CHG_STAT_MASK) != 0) { + if ((int_src_a & MAX20335_INTA_CHGSTAT_MASK) != 0) { ret = max20335_get_charger_status(data->dev, &data->charger_status); if (ret < 0) { LOG_WRN("Failed to read charger status: %d", ret); @@ -402,7 +404,7 @@ static void max20335_int_routine_work_handler(struct k_work *work) } } - if ((int_src_a & MAX20335_INT_A_USB_OK_MASK) != 0) { + if ((int_src_a & MAX20335_INTA_USBOK_MASK) != 0) { ret = max20335_get_charger_online(data->dev, &data->charger_online); if (ret < 0) { LOG_WRN("Failed to read charger online %d", ret); From f1b35a5c78e4814f78b33e8e6e629b8a7c33a4b4 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Fri, 9 Feb 2024 17:41:40 +0100 Subject: [PATCH 1434/2402] drivers: charger: charger_max20335: handle minimum system voltage Allow to configure minimum system voltage threshold parameter. Signed-off-by: Lukasz Madej --- doc/releases/release-notes-3.7.rst | 1 + drivers/charger/charger_max20335.c | 40 +++++++++++++++++++ .../charger/maxim,max20335-charger.yaml | 17 ++++++++ tests/drivers/build_all/charger/i2c.dtsi | 1 + 4 files changed, 59 insertions(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index d3ba37f1cba..3090359e865 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -96,6 +96,7 @@ Drivers and Sensors * Charger * Added ``chgin-to-sys-current-limit-microamp`` property to ``maxim,max20335-charger``. + * Added ``system-voltage-min-threshold-microvolt`` property to ``maxim,max20335-charger``. * Clock control diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index a715aabae1b..b7e8a150612 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -29,6 +29,7 @@ LOG_MODULE_REGISTER(max20335_charger); #define MAX20335_INTA_USBOK_MASK BIT(3) #define MAX20335_INTA_CHGSTAT_MASK BIT(6) #define MAX20335_ILIMCNTL_ILIMCNTL_MASK GENMASK(1, 0) +#define MAX20335_ILIMCNTL_SYSMIN_MASK GENMASK(7, 5) #define MAX20335_STATUSA_CHGSTAT_MASK GENMASK(2, 0) #define MAX20335_STATUSB_USBOK_MASK BIT(3) #define MAX20335_CHGCNTLA_BATREG_MASK GENMASK(4, 1) @@ -40,6 +41,11 @@ LOG_MODULE_REGISTER(max20335_charger); #define MAX20335_REG_CVC_VREG_MIN_IDX 0x0U #define MAX20335_REG_CVC_VREG_MAX_IDX 0x0BU +#define MAX20335_ILIMCNTL_SYSMIN_MIN_UV 3600000U +#define MAX20335_ILIMCNTL_SYSMIN_STEP_UV 100000U +#define MAX20335_ILIMCNTL_SYSMIN_MIN_IDX 0x0U +#define MAX20335_ILIMCNTL_SYSMIN_MAX_IDX 0x7U + #define INT_ENABLE_DELAY K_MSEC(500) struct charger_max20335_config { @@ -47,6 +53,7 @@ struct charger_max20335_config { struct gpio_dt_spec int_gpio; uint32_t max_vreg_uv; uint32_t max_ichgin_to_sys_ua; + uint32_t min_vsys_uv; }; struct charger_max20335_data { @@ -68,6 +75,12 @@ static const struct linear_range charger_uv_range = MAX20335_REG_CVC_VREG_MIN_IDX, MAX20335_REG_CVC_VREG_MAX_IDX); +static const struct linear_range system_uv_range = + LINEAR_RANGE_INIT(MAX20335_ILIMCNTL_SYSMIN_MIN_UV, + MAX20335_ILIMCNTL_SYSMIN_STEP_UV, + MAX20335_ILIMCNTL_SYSMIN_MIN_IDX, + MAX20335_ILIMCNTL_SYSMIN_MAX_IDX); + static int max20335_get_charger_status(const struct device *dev, enum charger_status *status) { enum { @@ -199,6 +212,26 @@ static int max20335_set_chgin_to_sys_current_limit(const struct device *dev, uin val); } +static int max20335_set_sys_voltage_min_threshold(const struct device *dev, uint32_t voltage_uv) +{ + const struct charger_max20335_config *const config = dev->config; + uint16_t idx; + uint8_t val; + int ret; + + ret = linear_range_get_index(&system_uv_range, voltage_uv, &idx); + if (ret < 0) { + return ret; + } + + val = FIELD_PREP(MAX20335_ILIMCNTL_SYSMIN_MASK, idx); + + return i2c_reg_update_byte_dt(&config->bus, + MAX20335_REG_ILIMCNTL, + MAX20335_ILIMCNTL_SYSMIN_MASK, + val); +} + static int max20335_set_enabled(const struct device *dev, bool enable) { struct charger_max20335_data *data = dev->data; @@ -288,6 +321,12 @@ static int max20335_update_properties(const struct device *dev) return ret; } + ret = max20335_set_sys_voltage_min_threshold(dev, config->min_vsys_uv); + if (ret < 0) { + LOG_ERR("Failed to set minimum system voltage threshold: %d", ret); + return ret; + } + ret = max20335_set_constant_charge_voltage(dev, data->charge_voltage_uv); if (ret < 0) { LOG_ERR("Failed to set charge voltage: %d", ret); @@ -513,6 +552,7 @@ static const struct charger_driver_api max20335_driver_api = { .int_gpio = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \ .max_vreg_uv = DT_INST_PROP(inst, constant_charge_voltage_max_microvolt), \ .max_ichgin_to_sys_ua = DT_INST_PROP(inst, chgin_to_sys_current_limit_microamp),\ + .min_vsys_uv = DT_INST_PROP(inst, system_voltage_min_threshold_microvolt), \ }; \ \ DEVICE_DT_INST_DEFINE(inst, &max20335_init, NULL, &charger_max20335_data_##inst, \ diff --git a/dts/bindings/charger/maxim,max20335-charger.yaml b/dts/bindings/charger/maxim,max20335-charger.yaml index 8020eac4f22..ddc52b15c0f 100644 --- a/dts/bindings/charger/maxim,max20335-charger.yaml +++ b/dts/bindings/charger/maxim,max20335-charger.yaml @@ -36,6 +36,23 @@ properties: CHGIN to SYS path current limitter configuration. Refer to ILimCntl register description for details. + system-voltage-min-threshold-microvolt: + type: int + required: true + enum: + - 3600000 + - 3700000 + - 3800000 + - 3900000 + - 4000000 + - 4100000 + - 4200000 + - 4300000 + description: | + System voltage minimum threshold. When SYS path + voltage drops to this level, the charger current + is reduced to prevent battery damage. + int-gpios: type: phandle-array required: true diff --git a/tests/drivers/build_all/charger/i2c.dtsi b/tests/drivers/build_all/charger/i2c.dtsi index f3761ff5be9..952b5f6b18a 100644 --- a/tests/drivers/build_all/charger/i2c.dtsi +++ b/tests/drivers/build_all/charger/i2c.dtsi @@ -26,6 +26,7 @@ max20335@1 { chgin-to-sys-current-limit-microamp = <100000>; constant-charge-voltage-max-microvolt = <4050000>; + system-voltage-min-threshold-microvolt = <3600000>; int-gpios = <&test_gpio 0 0>; }; }; From e8788deafa5de159356de0221d2120d394913106 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Wed, 20 Mar 2024 07:55:03 +0100 Subject: [PATCH 1435/2402] dts: battery: add property Add `re-charge-voltage-microvolt` property allowing to set limit to automatically start charging again. Signed-off-by: Lukasz Madej --- doc/releases/release-notes-3.7.rst | 5 +++++ dts/bindings/battery/battery.yaml | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index 3090359e865..4a4f2094d5e 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -72,6 +72,11 @@ Drivers and Sensors * Audio +* Battery + + * Added ``re-charge-voltage-microvolt`` property to the ``battery`` binding. This allows to set + limit to automatically start charging again. + * Battery backed up RAM * CAN diff --git a/dts/bindings/battery/battery.yaml b/dts/bindings/battery/battery.yaml index 90bb20532d4..c3c23a5f5d4 100644 --- a/dts/bindings/battery/battery.yaml +++ b/dts/bindings/battery/battery.yaml @@ -8,6 +8,10 @@ description: | linux/Documentation/devicetree/bindings/power/supply/battery.yaml properties: + re-charge-voltage-microvolt: + type: int + description: limit to automatically start charging again + precharge-current-microamp: type: int description: current for pre-charge phase From bda4c18fc93172562c227a179f8a6177bec194bd Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Sat, 10 Feb 2024 10:17:57 +0100 Subject: [PATCH 1436/2402] drivers: charger: charger_max20355: handle recharge threshold Allow to configure recharge threshold. Signed-off-by: Lukasz Madej --- doc/releases/release-notes-3.7.rst | 1 + drivers/charger/charger_max20335.c | 39 +++++++++++++++++++ .../charger/maxim,max20335-charger.yaml | 12 ++++++ tests/drivers/build_all/charger/i2c.dtsi | 1 + 4 files changed, 53 insertions(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index 4a4f2094d5e..aeb34b2077d 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -102,6 +102,7 @@ Drivers and Sensors * Added ``chgin-to-sys-current-limit-microamp`` property to ``maxim,max20335-charger``. * Added ``system-voltage-min-threshold-microvolt`` property to ``maxim,max20335-charger``. + * Added ``re-charge-threshold-microvolt`` property to ``maxim,max20335-charger``. * Clock control diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index b7e8a150612..e9dfa65f733 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -32,6 +32,7 @@ LOG_MODULE_REGISTER(max20335_charger); #define MAX20335_ILIMCNTL_SYSMIN_MASK GENMASK(7, 5) #define MAX20335_STATUSA_CHGSTAT_MASK GENMASK(2, 0) #define MAX20335_STATUSB_USBOK_MASK BIT(3) +#define MAX20335_CHGCNTLA_BATRECHG_MASK GENMASK(6, 5) #define MAX20335_CHGCNTLA_BATREG_MASK GENMASK(4, 1) #define MAX20335_CHGCNTLA_CHRGEN_MASK BIT(0) #define MAX20335_CHGCNTLA_CHRGEN BIT(0) @@ -54,6 +55,7 @@ struct charger_max20335_config { uint32_t max_vreg_uv; uint32_t max_ichgin_to_sys_ua; uint32_t min_vsys_uv; + uint32_t recharge_threshold_uv; }; struct charger_max20335_data { @@ -161,6 +163,36 @@ static int max20335_get_charger_online(const struct device *dev, enum charger_on return 0; } +static int max20335_set_recharge_threshold(const struct device *dev, uint32_t voltage_uv) +{ + const struct charger_max20335_config *const config = dev->config; + uint8_t val; + + switch (voltage_uv) { + case 70000: + val = 0x00; + break; + case 120000: + val = 0x01; + break; + case 170000: + val = 0x02; + break; + case 220000: + val = 0x03; + break; + default: + return -ENOTSUP; + }; + + val = FIELD_PREP(MAX20335_CHGCNTLA_BATRECHG_MASK, val); + + return i2c_reg_update_byte_dt(&config->bus, + MAX20335_REG_CHGCNTLA, + MAX20335_CHGCNTLA_BATRECHG_MASK, + val); +} + static int max20335_set_constant_charge_voltage(const struct device *dev, uint32_t voltage_uv) { @@ -327,6 +359,12 @@ static int max20335_update_properties(const struct device *dev) return ret; } + ret = max20335_set_recharge_threshold(dev, config->recharge_threshold_uv); + if (ret < 0) { + LOG_ERR("Failed to set recharge threshold: %d", ret); + return ret; + } + ret = max20335_set_constant_charge_voltage(dev, data->charge_voltage_uv); if (ret < 0) { LOG_ERR("Failed to set charge voltage: %d", ret); @@ -553,6 +591,7 @@ static const struct charger_driver_api max20335_driver_api = { .max_vreg_uv = DT_INST_PROP(inst, constant_charge_voltage_max_microvolt), \ .max_ichgin_to_sys_ua = DT_INST_PROP(inst, chgin_to_sys_current_limit_microamp),\ .min_vsys_uv = DT_INST_PROP(inst, system_voltage_min_threshold_microvolt), \ + .recharge_threshold_uv = DT_INST_PROP(inst, re_charge_threshold_microvolt), \ }; \ \ DEVICE_DT_INST_DEFINE(inst, &max20335_init, NULL, &charger_max20335_data_##inst, \ diff --git a/dts/bindings/charger/maxim,max20335-charger.yaml b/dts/bindings/charger/maxim,max20335-charger.yaml index ddc52b15c0f..a52c29a6a0f 100644 --- a/dts/bindings/charger/maxim,max20335-charger.yaml +++ b/dts/bindings/charger/maxim,max20335-charger.yaml @@ -53,6 +53,18 @@ properties: voltage drops to this level, the charger current is reduced to prevent battery damage. + re-charge-threshold-microvolt: + type: int + required: true + enum: + - 70000 + - 120000 + - 170000 + - 220000 + description: | + Recharge threshold in relation to BatReg. + Refer to ChgCntlA register description for details. + int-gpios: type: phandle-array required: true diff --git a/tests/drivers/build_all/charger/i2c.dtsi b/tests/drivers/build_all/charger/i2c.dtsi index 952b5f6b18a..2f68f1d403f 100644 --- a/tests/drivers/build_all/charger/i2c.dtsi +++ b/tests/drivers/build_all/charger/i2c.dtsi @@ -27,6 +27,7 @@ max20335@1 { chgin-to-sys-current-limit-microamp = <100000>; constant-charge-voltage-max-microvolt = <4050000>; system-voltage-min-threshold-microvolt = <3600000>; + re-charge-threshold-microvolt = <170000>; int-gpios = <&test_gpio 0 0>; }; }; From a64a64b3c23b9d12136a3a4925fe5f275b505805 Mon Sep 17 00:00:00 2001 From: Lukasz Madej Date: Sat, 10 Feb 2024 14:39:17 +0100 Subject: [PATCH 1437/2402] drivers: charger: charger_max20355: handle thermistor mode Allow to configure thermistor monitoring mode. Signed-off-by: Lukasz Madej --- doc/releases/release-notes-3.7.rst | 1 + drivers/charger/charger_max20335.c | 70 +++++++++++++++++++ .../charger/maxim,max20335-charger.yaml | 12 ++++ tests/drivers/build_all/charger/i2c.dtsi | 1 + 4 files changed, 84 insertions(+) diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index aeb34b2077d..2deafcffded 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -103,6 +103,7 @@ Drivers and Sensors * Added ``chgin-to-sys-current-limit-microamp`` property to ``maxim,max20335-charger``. * Added ``system-voltage-min-threshold-microvolt`` property to ``maxim,max20335-charger``. * Added ``re-charge-threshold-microvolt`` property to ``maxim,max20335-charger``. + * Added ``thermistor-monitoring-mode`` property to ``maxim,max20335-charger``. * Clock control diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c index e9dfa65f733..a58da7e5731 100644 --- a/drivers/charger/charger_max20335.c +++ b/drivers/charger/charger_max20335.c @@ -25,6 +25,7 @@ LOG_MODULE_REGISTER(max20335_charger); #define MAX20335_REG_INTMASKB 0x08 #define MAX20335_REG_ILIMCNTL 0x09 #define MAX20335_REG_CHGCNTLA 0x0A +#define MAX20335_REG_THRMCFG 0x18 #define MAX20335_INTA_USBOK_MASK BIT(3) #define MAX20335_INTA_CHGSTAT_MASK BIT(6) @@ -36,6 +37,7 @@ LOG_MODULE_REGISTER(max20335_charger); #define MAX20335_CHGCNTLA_BATREG_MASK GENMASK(4, 1) #define MAX20335_CHGCNTLA_CHRGEN_MASK BIT(0) #define MAX20335_CHGCNTLA_CHRGEN BIT(0) +#define MAX20335_THRMCFG_THERMEN_MASK GENMASK(1, 0) #define MAX20335_REG_CVC_VREG_MIN_UV 4050000U #define MAX20335_REG_CVC_VREG_STEP_UV 50000U @@ -49,6 +51,14 @@ LOG_MODULE_REGISTER(max20335_charger); #define INT_ENABLE_DELAY K_MSEC(500) +enum charger_max20335_therm_mode { + MAX20335_THERM_MODE_DISABLED, + MAX20335_THERM_MODE_THERMISTOR, + MAX20335_THERM_MODE_JEITA_1, + MAX20335_THERM_MODE_JEITA_2, + MAX20335_THERM_MODE_UNKNOWN, +}; + struct charger_max20335_config { struct i2c_dt_spec bus; struct gpio_dt_spec int_gpio; @@ -56,6 +66,7 @@ struct charger_max20335_config { uint32_t max_ichgin_to_sys_ua; uint32_t min_vsys_uv; uint32_t recharge_threshold_uv; + char *therm_mon_mode; }; struct charger_max20335_data { @@ -264,6 +275,37 @@ static int max20335_set_sys_voltage_min_threshold(const struct device *dev, uint val); } +static int max20335_set_thermistor_mode(const struct device *dev, + enum charger_max20335_therm_mode mode) +{ + const struct charger_max20335_config *const config = dev->config; + uint8_t val; + + switch (mode) { + case MAX20335_THERM_MODE_DISABLED: + val = 0x00; + break; + case MAX20335_THERM_MODE_THERMISTOR: + val = 0x01; + break; + case MAX20335_THERM_MODE_JEITA_1: + val = 0x02; + break; + case MAX20335_THERM_MODE_JEITA_2: + val = 0x03; + break; + default: + return -ENOTSUP; + }; + + val = FIELD_PREP(MAX20335_THRMCFG_THERMEN_MASK, val); + + return i2c_reg_update_byte_dt(&config->bus, + MAX20335_REG_THRMCFG, + MAX20335_THRMCFG_THERMEN_MASK, + val); +} + static int max20335_set_enabled(const struct device *dev, bool enable) { struct charger_max20335_data *data = dev->data; @@ -341,10 +383,30 @@ static int max20335_init_properties(const struct device *dev) return 0; } +enum charger_max20335_therm_mode max20335_string_to_therm_mode(const char *mode_string) +{ + static const char * const modes[] = { + [MAX20335_THERM_MODE_DISABLED] = "disabled", + [MAX20335_THERM_MODE_THERMISTOR] = "thermistor", + [MAX20335_THERM_MODE_JEITA_1] = "JEITA-1", + [MAX20335_THERM_MODE_JEITA_2] = "JEITA-2", + }; + enum charger_max20335_therm_mode i; + + for (i = MAX20335_THERM_MODE_DISABLED; i < ARRAY_SIZE(modes); i++) { + if (strncmp(mode_string, modes[i], strlen(modes[i])) == 0) { + return i; + } + } + + return MAX20335_THERM_MODE_UNKNOWN; +} + static int max20335_update_properties(const struct device *dev) { struct charger_max20335_data *data = dev->data; const struct charger_max20335_config *config = dev->config; + enum charger_max20335_therm_mode therm_mode; int ret; ret = max20335_set_chgin_to_sys_current_limit(dev, config->max_ichgin_to_sys_ua); @@ -365,6 +427,13 @@ static int max20335_update_properties(const struct device *dev) return ret; } + therm_mode = max20335_string_to_therm_mode(config->therm_mon_mode); + ret = max20335_set_thermistor_mode(dev, therm_mode); + if (ret < 0) { + LOG_ERR("Failed to set thermistor mode: %d", ret); + return ret; + } + ret = max20335_set_constant_charge_voltage(dev, data->charge_voltage_uv); if (ret < 0) { LOG_ERR("Failed to set charge voltage: %d", ret); @@ -592,6 +661,7 @@ static const struct charger_driver_api max20335_driver_api = { .max_ichgin_to_sys_ua = DT_INST_PROP(inst, chgin_to_sys_current_limit_microamp),\ .min_vsys_uv = DT_INST_PROP(inst, system_voltage_min_threshold_microvolt), \ .recharge_threshold_uv = DT_INST_PROP(inst, re_charge_threshold_microvolt), \ + .therm_mon_mode = DT_INST_PROP(inst, thermistor_monitoring_mode), \ }; \ \ DEVICE_DT_INST_DEFINE(inst, &max20335_init, NULL, &charger_max20335_data_##inst, \ diff --git a/dts/bindings/charger/maxim,max20335-charger.yaml b/dts/bindings/charger/maxim,max20335-charger.yaml index a52c29a6a0f..3fe44c92908 100644 --- a/dts/bindings/charger/maxim,max20335-charger.yaml +++ b/dts/bindings/charger/maxim,max20335-charger.yaml @@ -65,6 +65,18 @@ properties: Recharge threshold in relation to BatReg. Refer to ChgCntlA register description for details. + thermistor-monitoring-mode: + type: string + required: true + enum: + - "disabled" + - "thermistor" + - "JEITA-1" + - "JEITA-2" + description: | + Thermistor monitoring mode. + Refer to ThrmCfg register description and Table 2 for details. + int-gpios: type: phandle-array required: true diff --git a/tests/drivers/build_all/charger/i2c.dtsi b/tests/drivers/build_all/charger/i2c.dtsi index 2f68f1d403f..29187ccd37d 100644 --- a/tests/drivers/build_all/charger/i2c.dtsi +++ b/tests/drivers/build_all/charger/i2c.dtsi @@ -28,6 +28,7 @@ max20335@1 { constant-charge-voltage-max-microvolt = <4050000>; system-voltage-min-threshold-microvolt = <3600000>; re-charge-threshold-microvolt = <170000>; + thermistor-monitoring-mode = "JEITA-2"; int-gpios = <&test_gpio 0 0>; }; }; From fbe91cd6546e591d9ff3e5558b6fa115abe79503 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 10:24:58 +0100 Subject: [PATCH 1438/2402] doc: Bluetooth: move `btmon` instructions Move so both sections referring to btmon are on the same page. Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/bluetooth-dev.rst | 40 +++---------- .../bluetooth/bluetooth-tools.rst | 58 +++++++++++++++++++ 2 files changed, 66 insertions(+), 32 deletions(-) diff --git a/doc/connectivity/bluetooth/bluetooth-dev.rst b/doc/connectivity/bluetooth/bluetooth-dev.rst index 4883cdcfcf9..7b1021de894 100644 --- a/doc/connectivity/bluetooth/bluetooth-dev.rst +++ b/doc/connectivity/bluetooth/bluetooth-dev.rst @@ -51,34 +51,9 @@ To start developing using this setup follow the :ref:`Getting Started Guide boards that support Bluetooth and then :ref:`run the application `). -.. _bluetooth-hci-tracing: - -Embedded HCI tracing --------------------- - -When running both Host and Controller in actual Integrated Circuits, you will -only see normal log messages on the console by default, without any way of -accessing the HCI traffic between the Host and the Controller. However, there -is a special Bluetooth logging mode that converts the console to use a binary -protocol that interleaves both normal log messages as well as the HCI traffic. -Set the following Kconfig options to enable this protocol before building your -application: - -.. code-block:: console - - CONFIG_BT_DEBUG_MONITOR_UART=y - CONFIG_UART_CONSOLE=n - -Setting :kconfig:option:`CONFIG_BT_DEBUG_MONITOR_UART` to ``y`` replaces the -:kconfig:option:`CONFIG_BT_DEBUG_LOG` option, and setting :kconfig:option:`CONFIG_UART_CONSOLE` -to ``n`` disables the default ``printk``/``printf`` hooks. - -To decode the binary protocol that will now be sent to the console UART you need -to use the btmon tool from :ref:`BlueZ `: - -.. code-block:: console - - $ btmon --tty --tty-speed 115200 +There is a way to access the :ref:`HCI ` traffic between the Host +and Controller, even if there is no physical transport. See :ref:`Embedded HCI +tracing ` for instructions. Host on Linux with an external Controller ========================================= @@ -117,6 +92,7 @@ QEMU You can run the Zephyr Host on the :ref:`QEMU emulator` and have it interact with a physical external Bluetooth Controller. + Refer to :ref:`bluetooth_qemu_native` for full instructions on how to build and run an application in this setup. @@ -129,13 +105,13 @@ native_sim The :ref:`native_sim ` target builds your Zephyr application with the Zephyr kernel, and some minimal HW emulation as a native Linux executable. + This executable is a normal Linux program, which can be debugged and instrumented like any other, and it communicates with a physical or virtual -external Controller. +external Controller. Refer to: -Refer to :ref:`bluetooth_qemu_native` for full instructions on how to build and -run an application with a physical controller. For the virtual controller refer -to :ref:`bluetooth_virtual_posix`. +- :ref:`bluetooth_qemu_native` for the physical controller +- :ref:`bluetooth_virtual_posix` for the virtual controller Simulated nRF5x with BabbleSim ============================== diff --git a/doc/connectivity/bluetooth/bluetooth-tools.rst b/doc/connectivity/bluetooth/bluetooth-tools.rst index 35546396de4..3e5517ee491 100644 --- a/doc/connectivity/bluetooth/bluetooth-tools.rst +++ b/doc/connectivity/bluetooth/bluetooth-tools.rst @@ -81,6 +81,7 @@ Running on QEMU or native_sim It's possible to run Bluetooth applications using either the :ref:`QEMU emulator` or :ref:`native_sim `. + In either case, a Bluetooth controller needs to be exported from the host OS (Linux) to the emulator. For this purpose you will need some tools described in the :ref:`bluetooth_bluez` section. @@ -166,6 +167,8 @@ transports when building a single-mode, Zephyr-based BLE Controller: * USB: Use the :ref:`hci_usb ` sample and then treat it as a Host System Bluetooth Controller (see previous section) +.. _bluetooth-hci-tracing: + HCI Tracing =========== @@ -178,6 +181,61 @@ In order to see those logs, you can use the built-in ``btmon`` tool from BlueZ: $ btmon +The output looks like this:: + + = New Index: 00:00:00:00:00:00 (Primary,Virtual,Control) 0.274200 + = Open Index: 00:00:00:00:00:00 0.274500 + < HCI Command: Reset (0x03|0x0003) plen 0 #1 0.274600 + > HCI Event: Command Complete (0x0e) plen 4 #2 0.274700 + Reset (0x03|0x0003) ncmd 1 + Status: Success (0x00) + < HCI Command: Read Local Supported Features (0x04|0x0003) plen 0 #3 0.274800 + > HCI Event: Command Complete (0x0e) plen 12 #4 0.274900 + Read Local Supported Features (0x04|0x0003) ncmd 1 + Status: Success (0x00) + Features: 0x00 0x00 0x00 0x00 0x60 0x00 0x00 0x00 + BR/EDR Not Supported + LE Supported (Controller) + +.. _bluetooth-embedded-hci-tracing: + +Embedded HCI tracing +-------------------- + +When running both Host and Controller in actual Integrated Circuits, you will +only see normal log messages on the console by default, without any way of +accessing the HCI traffic between the Host and the Controller. However, there +is a special Bluetooth logging mode that converts the console to use a binary +protocol that interleaves both normal log messages as well as the HCI traffic. + +Set the following Kconfig options to enable this protocol before building your +application: + +.. code-block:: cfg + + CONFIG_BT_DEBUG_MONITOR_UART=y + CONFIG_UART_CONSOLE=n + +- Setting :kconfig:option:`CONFIG_BT_DEBUG_MONITOR_UART` activates the formatting +- Clearing :kconfig:option:`CONFIG_UART_CONSOLE` makes the UART unavailable for + the system console. E.g. for ``printk`` and the :kconfig:option:`boot banner + ` + +To decode the binary protocol that will now be sent to the console UART you need +to use the btmon tool from :ref:`BlueZ `: + +.. code-block:: console + + $ btmon --tty --tty-speed 115200 + +If UART is not available (or you still want non-binary logs), you can set +:kconfig:option:`CONFIG_BT_DEBUG_MONITOR_RTT` instead, which will use Segger +RTT. For example, if trying to connect to a nRF52840DK with S/N 683578642: + +.. code-block:: console + + $ btmon --jlink nRF52840_xxAA,683578642 + .. _bluetooth_virtual_posix: Running on a Virtual Controller and native_sim From d14baba122d0485518ab880311429289e8cb2dd4 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 11:26:41 +0100 Subject: [PATCH 1439/2402] doc: Bluetooth: add sections and links to -dev Add sections and links for `bluetooth-dev.rst` Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/bluetooth-dev.rst | 37 ++++++++++++++++---- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/doc/connectivity/bluetooth/bluetooth-dev.rst b/doc/connectivity/bluetooth/bluetooth-dev.rst index 7b1021de894..a5d7ac4c9f3 100644 --- a/doc/connectivity/bluetooth/bluetooth-dev.rst +++ b/doc/connectivity/bluetooth/bluetooth-dev.rst @@ -8,7 +8,11 @@ approach that is described in the :ref:`application` section of the documentation. Additional information that is only relevant to Bluetooth applications can be -found in this page. +found on this page. + +.. contents:: + :local: + :depth: 2 Thread safety ************* @@ -29,12 +33,17 @@ applications with Zephyr. Depending on the hardware that is available to you, the requirements you have and the type of development you prefer you may pick one or another setup to match your needs. -There are 4 possible hardware setups to use with Zephyr and Bluetooth: +There are 3 possible setups: + +#. :ref:`Embedded ` +#. :ref:`External controller ` + + - :ref:`QEMU host ` + - :ref:`native_sim host ` -#. Embedded -#. QEMU with an external Controller -#. :ref:`native_sim ` with an external Controller -#. Simulated nRF5x with BabbleSim +#. :ref:`Simulated nRF5x with BabbleSim ` + +.. _bluetooth-hw-setup-embedded: Embedded ======== @@ -55,6 +64,8 @@ There is a way to access the :ref:`HCI ` traffic between the Host and Controller, even if there is no physical transport. See :ref:`Embedded HCI tracing ` for instructions. +.. _bluetooth-hw-setup-external-ll: + Host on Linux with an external Controller ========================================= @@ -71,7 +82,7 @@ which is comprised of the following devices: * A commercially available Controller * A :ref:`Controller-only ` build of Zephyr - * A Virtual controller + * A :ref:`Virtual controller ` .. warning:: Certain external Controllers are either unable to accept the Host to @@ -87,6 +98,8 @@ which is comprised of the following devices: you need to disable Host to Controller flow control. To do so, set ``CONFIG_BT_HCI_ACL_FLOW_CONTROL=n`` in your :file:`prj.conf`. +.. _bluetooth-hw-setup-qemu-host: + QEMU ---- @@ -96,6 +109,8 @@ and have it interact with a physical external Bluetooth Controller. Refer to :ref:`bluetooth_qemu_native` for full instructions on how to build and run an application in this setup. +.. _bluetooth-hw-setup-native-sim-host: + native_sim ---------- @@ -113,6 +128,8 @@ external Controller. Refer to: - :ref:`bluetooth_qemu_native` for the physical controller - :ref:`bluetooth_virtual_posix` for the virtual controller +.. _bluetooth-hw-setup-bsim: + Simulated nRF5x with BabbleSim ============================== @@ -169,4 +186,10 @@ that's used to initialize Bluetooth and then :c:func:`bt_le_adv_start` that's used to start advertising a specific combination of advertising and scan response data. +More Examples +************* + +More :ref:`sample Bluetooth applications ` are available in +``samples/bluetooth/``. + .. _BabbleSim: https://babblesim.github.io/ From 89d05bbc760a428dc10439e56b947fc39972abcb Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 13:31:41 +0100 Subject: [PATCH 1440/2402] doc: Bluetooth: organize API page in sections Makes it easier to find what you're looking for. Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/api/index.rst | 69 ++++++++++++++++++------ 1 file changed, 53 insertions(+), 16 deletions(-) diff --git a/doc/connectivity/bluetooth/api/index.rst b/doc/connectivity/bluetooth/api/index.rst index fa7e357f7d8..697e151ecc8 100644 --- a/doc/connectivity/bluetooth/api/index.rst +++ b/doc/connectivity/bluetooth/api/index.rst @@ -3,32 +3,28 @@ Bluetooth APIs ############## +Bluetooth Classic Host and profiles + +.. toctree:: + :maxdepth: 1 + + hfp.rst + rfcomm.rst + sdp.rst + +Bluetooth LE Audio +================== + .. toctree:: :maxdepth: 1 - att.rst audio.rst bap.rst cap.rst - connection_mgmt.rst - controller.rst coordinated_sets.rst - crypto.rst - data_buffer.rst - gap.rst - gatt.rst - hci_drivers.rst - hci_raw.rst - hfp.rst - l2cap.rst media.rst - mesh.rst microphone.rst - rfcomm.rst - services.rst - sdp.rst volume.rst - uuid.rst shell/bap.rst shell/bap_broadcast_assistant.rst shell/bap_scan_delegator.rst @@ -40,3 +36,44 @@ Bluetooth APIs shell/mcp.rst shell/tmap.rst shell/pbp.rst + +Bluetooth LE Host +================= + +.. toctree:: + :maxdepth: 1 + + services.rst + gap.rst + gatt.rst + att.rst + +Bluetooth Mesh +============== + +.. toctree:: + :maxdepth: 1 + + mesh.rst + +Core Host and drivers +===================== + +.. toctree:: + :maxdepth: 1 + + l2cap.rst + connection_mgmt.rst + data_buffer.rst + hci_drivers.rst + hci_raw.rst + crypto.rst + +Other +===== + +.. toctree:: + :maxdepth: 1 + + controller.rst + uuid.rst From c44cbaf8682566fd66b1aae610c5da17e017c531 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 13:32:43 +0100 Subject: [PATCH 1441/2402] doc: Bluetooth: Add ToC to `bluetooth-tools.rst` Also capitalize title like the other pages. Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/bluetooth-tools.rst | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/doc/connectivity/bluetooth/bluetooth-tools.rst b/doc/connectivity/bluetooth/bluetooth-tools.rst index 3e5517ee491..396d499a5f1 100644 --- a/doc/connectivity/bluetooth/bluetooth-tools.rst +++ b/doc/connectivity/bluetooth/bluetooth-tools.rst @@ -1,12 +1,16 @@ .. _bluetooth-tools: -Bluetooth tools +Bluetooth Tools ############### This page lists and describes tools that can be used to assist during Bluetooth stack or application development in order to help, simplify and speed up the development process. +.. contents:: + :local: + :depth: 2 + .. _bluetooth-mobile-apps: Mobile applications From b6aefe9a6794be344a60dce1eb3e1af79ea9c9ab Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 13:35:46 +0100 Subject: [PATCH 1442/2402] doc: Bluetooth: move `-pics.rst` into ics/ folder Less clutter. Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/bluetooth-qual.rst | 14 +++++++------- .../bluetooth/{dis-pics.rst => ics/dis.rst} | 0 .../bluetooth/{gap-pics.rst => ics/gap.rst} | 0 .../bluetooth/{gatt-pics.rst => ics/gatt.rst} | 0 .../bluetooth/{l2cap-pics.rst => ics/l2cap.rst} | 0 .../bluetooth/{mesh-pics.rst => ics/mesh.rst} | 0 .../bluetooth/{rfcomm-pics.rst => ics/rfcomm.rst} | 0 .../bluetooth/{sm-pics.rst => ics/sm.rst} | 0 8 files changed, 7 insertions(+), 7 deletions(-) rename doc/connectivity/bluetooth/{dis-pics.rst => ics/dis.rst} (100%) rename doc/connectivity/bluetooth/{gap-pics.rst => ics/gap.rst} (100%) rename doc/connectivity/bluetooth/{gatt-pics.rst => ics/gatt.rst} (100%) rename doc/connectivity/bluetooth/{l2cap-pics.rst => ics/l2cap.rst} (100%) rename doc/connectivity/bluetooth/{mesh-pics.rst => ics/mesh.rst} (100%) rename doc/connectivity/bluetooth/{rfcomm-pics.rst => ics/rfcomm.rst} (100%) rename doc/connectivity/bluetooth/{sm-pics.rst => ics/sm.rst} (100%) diff --git a/doc/connectivity/bluetooth/bluetooth-qual.rst b/doc/connectivity/bluetooth/bluetooth-qual.rst index 2c3392433d2..631fa9fdafe 100644 --- a/doc/connectivity/bluetooth/bluetooth-qual.rst +++ b/doc/connectivity/bluetooth/bluetooth-qual.rst @@ -97,10 +97,10 @@ the following documents: .. toctree:: :maxdepth: 1 - gap-pics.rst - gatt-pics.rst - l2cap-pics.rst - sm-pics.rst - rfcomm-pics.rst - mesh-pics.rst - dis-pics.rst + ics/gap.rst + ics/gatt.rst + ics/l2cap.rst + ics/sm.rst + ics/rfcomm.rst + ics/mesh.rst + ics/dis.rst diff --git a/doc/connectivity/bluetooth/dis-pics.rst b/doc/connectivity/bluetooth/ics/dis.rst similarity index 100% rename from doc/connectivity/bluetooth/dis-pics.rst rename to doc/connectivity/bluetooth/ics/dis.rst diff --git a/doc/connectivity/bluetooth/gap-pics.rst b/doc/connectivity/bluetooth/ics/gap.rst similarity index 100% rename from doc/connectivity/bluetooth/gap-pics.rst rename to doc/connectivity/bluetooth/ics/gap.rst diff --git a/doc/connectivity/bluetooth/gatt-pics.rst b/doc/connectivity/bluetooth/ics/gatt.rst similarity index 100% rename from doc/connectivity/bluetooth/gatt-pics.rst rename to doc/connectivity/bluetooth/ics/gatt.rst diff --git a/doc/connectivity/bluetooth/l2cap-pics.rst b/doc/connectivity/bluetooth/ics/l2cap.rst similarity index 100% rename from doc/connectivity/bluetooth/l2cap-pics.rst rename to doc/connectivity/bluetooth/ics/l2cap.rst diff --git a/doc/connectivity/bluetooth/mesh-pics.rst b/doc/connectivity/bluetooth/ics/mesh.rst similarity index 100% rename from doc/connectivity/bluetooth/mesh-pics.rst rename to doc/connectivity/bluetooth/ics/mesh.rst diff --git a/doc/connectivity/bluetooth/rfcomm-pics.rst b/doc/connectivity/bluetooth/ics/rfcomm.rst similarity index 100% rename from doc/connectivity/bluetooth/rfcomm-pics.rst rename to doc/connectivity/bluetooth/ics/rfcomm.rst diff --git a/doc/connectivity/bluetooth/sm-pics.rst b/doc/connectivity/bluetooth/ics/sm.rst similarity index 100% rename from doc/connectivity/bluetooth/sm-pics.rst rename to doc/connectivity/bluetooth/ics/sm.rst From e043f06fb71b72bee9095673f99d2c4d62ab1680 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 13:44:31 +0100 Subject: [PATCH 1443/2402] doc: Bluetooth: Rename `overview.rst` and add links This page only ever had one section: supported features. Added links to the relevant sections for each layer. Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/api/index.rst | 1 + doc/connectivity/bluetooth/bluetooth-arch.rst | 2 ++ .../bluetooth/{overview.rst => features.rst} | 23 ++++++++----------- doc/connectivity/bluetooth/index.rst | 2 +- 4 files changed, 13 insertions(+), 15 deletions(-) rename doc/connectivity/bluetooth/{overview.rst => features.rst} (89%) diff --git a/doc/connectivity/bluetooth/api/index.rst b/doc/connectivity/bluetooth/api/index.rst index 697e151ecc8..b9120a608d8 100644 --- a/doc/connectivity/bluetooth/api/index.rst +++ b/doc/connectivity/bluetooth/api/index.rst @@ -4,6 +4,7 @@ Bluetooth APIs ############## Bluetooth Classic Host and profiles +=================================== .. toctree:: :maxdepth: 1 diff --git a/doc/connectivity/bluetooth/bluetooth-arch.rst b/doc/connectivity/bluetooth/bluetooth-arch.rst index ed0cf1ea9f6..c98bb1cdb0d 100644 --- a/doc/connectivity/bluetooth/bluetooth-arch.rst +++ b/doc/connectivity/bluetooth/bluetooth-arch.rst @@ -207,6 +207,8 @@ The stack is split up as follows in the source tree: ``doc/guides/bluetooth/`` Extra documentation, such as PICS documents. +.. _bluetooth-host: + Host **** diff --git a/doc/connectivity/bluetooth/overview.rst b/doc/connectivity/bluetooth/features.rst similarity index 89% rename from doc/connectivity/bluetooth/overview.rst rename to doc/connectivity/bluetooth/features.rst index f36c819d464..01b3ff15490 100644 --- a/doc/connectivity/bluetooth/overview.rst +++ b/doc/connectivity/bluetooth/features.rst @@ -1,7 +1,7 @@ -.. _bluetooth-overview: +.. _bluetooth-features: -Overview -######## +Supported features +################## .. contents:: :local: @@ -14,12 +14,6 @@ implementations of the Bluetooth specification (Linux's BlueZ) as well as the design and development of BLE radio hardware, the protocol stack in Zephyr has grown to be mature and feature-rich, as can be seen in the section below. -Supported Features -****************** - -Zephyr comes integrated with a feature-rich and highly configurable -Bluetooth stack. - * Bluetooth v5.3 compliant * Highly configurable @@ -29,18 +23,19 @@ Bluetooth stack. * Portable to all architectures supported by Zephyr (including big and little endian, alignment flavors and more) - * Support for all combinations of Host and Controller builds: + * Support for :ref:`all combinations ` of Host and + Controller builds: * Controller-only (HCI) over UART, SPI, USB and IPC physical transports * Host-only over UART, SPI, and IPC (shared memory) * Combined (Host + Controller) -* Bluetooth-SIG qualifiable +* :ref:`Bluetooth-SIG qualifiable ` * Conformance tests run regularly on all layers (Controller and Host, except BT Classic) on Nordic Semiconductor hardware. -* Bluetooth Low Energy Controller support (LE Link Layer) +* :ref:`Bluetooth Low Energy Controller ` (LE Link Layer) * Unlimited role and connection count, all roles supported * All v5.3 specification features supported (except a few minor items) @@ -53,7 +48,7 @@ Bluetooth stack. module * Support for Controller (HCI) builds over different physical transports -* Bluetooth Host support +* :ref:`Bluetooth Host ` * Generic Access Profile (GAP) with all possible LE roles @@ -102,7 +97,7 @@ Bluetooth stack. * Verified with multiple popular controllers -* LE Audio in Host and Controller +* :ref:`LE Audio in Host and Controller ` * Isochronous channels diff --git a/doc/connectivity/bluetooth/index.rst b/doc/connectivity/bluetooth/index.rst index a39754af78b..3be74f47da2 100644 --- a/doc/connectivity/bluetooth/index.rst +++ b/doc/connectivity/bluetooth/index.rst @@ -13,7 +13,7 @@ hardware, as well as portions of a Classical Bluetooth (BR/EDR) Host layer. .. toctree:: :maxdepth: 1 - overview.rst + features.rst bluetooth-arch.rst bluetooth-ctlr-arch.rst bluetooth-audio-arch.rst From 698a0c3193cebb617cb8b37260d1f4e52520841f Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 14:31:11 +0100 Subject: [PATCH 1444/2402] doc: Bluetooth: Remove "Bluetooth" from titles It adds unnecessary noise in the navigation pane. We don't do this for other chapters (e.g. kernel services don't say "Kernel Services System Threads" in the title, just "System Threads"). Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/api/index.rst | 4 ++-- doc/connectivity/bluetooth/bluetooth-arch.rst | 4 ++-- doc/connectivity/bluetooth/bluetooth-audio-arch.rst | 4 ++-- doc/connectivity/bluetooth/bluetooth-ctlr-arch.rst | 4 ++-- doc/connectivity/bluetooth/bluetooth-dev.rst | 4 ++-- doc/connectivity/bluetooth/bluetooth-qual.rst | 4 ++-- doc/connectivity/bluetooth/bluetooth-shell.rst | 4 ++-- doc/connectivity/bluetooth/bluetooth-tools.rst | 4 ++-- 8 files changed, 16 insertions(+), 16 deletions(-) diff --git a/doc/connectivity/bluetooth/api/index.rst b/doc/connectivity/bluetooth/api/index.rst index b9120a608d8..e9c45edd6de 100644 --- a/doc/connectivity/bluetooth/api/index.rst +++ b/doc/connectivity/bluetooth/api/index.rst @@ -1,7 +1,7 @@ .. _bluetooth_api: -Bluetooth APIs -############## +API +### Bluetooth Classic Host and profiles =================================== diff --git a/doc/connectivity/bluetooth/bluetooth-arch.rst b/doc/connectivity/bluetooth/bluetooth-arch.rst index c98bb1cdb0d..0dc10e1ee9e 100644 --- a/doc/connectivity/bluetooth/bluetooth-arch.rst +++ b/doc/connectivity/bluetooth/bluetooth-arch.rst @@ -1,7 +1,7 @@ .. _bluetooth-arch: -Bluetooth Stack Architecture -############################ +Stack Architecture +################## Overview ******** diff --git a/doc/connectivity/bluetooth/bluetooth-audio-arch.rst b/doc/connectivity/bluetooth/bluetooth-audio-arch.rst index 82784f0d361..9efa8ded969 100644 --- a/doc/connectivity/bluetooth/bluetooth-audio-arch.rst +++ b/doc/connectivity/bluetooth/bluetooth-audio-arch.rst @@ -1,8 +1,8 @@ .. _bluetooth_audio_arch: -Bluetooth Audio Architecture -############################# +Audio Architecture +################## .. figure:: img/ble_audio_arch.svg :align: center diff --git a/doc/connectivity/bluetooth/bluetooth-ctlr-arch.rst b/doc/connectivity/bluetooth/bluetooth-ctlr-arch.rst index e256304aebb..5861440e226 100644 --- a/doc/connectivity/bluetooth/bluetooth-ctlr-arch.rst +++ b/doc/connectivity/bluetooth/bluetooth-ctlr-arch.rst @@ -1,7 +1,7 @@ .. _bluetooth-ctlr-arch: -Bluetooth Low Energy Controller -############################### +LE Controller +############# Overview ******** diff --git a/doc/connectivity/bluetooth/bluetooth-dev.rst b/doc/connectivity/bluetooth/bluetooth-dev.rst index a5d7ac4c9f3..1a4484534b2 100644 --- a/doc/connectivity/bluetooth/bluetooth-dev.rst +++ b/doc/connectivity/bluetooth/bluetooth-dev.rst @@ -1,7 +1,7 @@ .. _bluetooth-dev: -Developing Bluetooth Applications -################################# +Application Development +####################### Bluetooth applications are developed using the common infrastructure and approach that is described in the :ref:`application` section of the diff --git a/doc/connectivity/bluetooth/bluetooth-qual.rst b/doc/connectivity/bluetooth/bluetooth-qual.rst index 631fa9fdafe..c983358cb79 100644 --- a/doc/connectivity/bluetooth/bluetooth-qual.rst +++ b/doc/connectivity/bluetooth/bluetooth-qual.rst @@ -1,7 +1,7 @@ .. _bluetooth-qual: -Bluetooth Qualification -####################### +Qualification +############# Qualification setup ******************* diff --git a/doc/connectivity/bluetooth/bluetooth-shell.rst b/doc/connectivity/bluetooth/bluetooth-shell.rst index 2b38f4c7b6f..82e4d0e46da 100644 --- a/doc/connectivity/bluetooth/bluetooth-shell.rst +++ b/doc/connectivity/bluetooth/bluetooth-shell.rst @@ -1,7 +1,7 @@ .. _bluetooth_shell: -Bluetooth Shell -############### +Shell +##### The Bluetooth Shell is an application based on the :ref:`shell_api` module. It offer a collection of commands made to easily interact with the Bluetooth stack. diff --git a/doc/connectivity/bluetooth/bluetooth-tools.rst b/doc/connectivity/bluetooth/bluetooth-tools.rst index 396d499a5f1..21188f49b28 100644 --- a/doc/connectivity/bluetooth/bluetooth-tools.rst +++ b/doc/connectivity/bluetooth/bluetooth-tools.rst @@ -1,7 +1,7 @@ .. _bluetooth-tools: -Bluetooth Tools -############### +Tools +##### This page lists and describes tools that can be used to assist during Bluetooth stack or application development in order to help, simplify and speed up the From e701188bce516f32be2d71e53657cf4ae055fc97 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 15:00:13 +0100 Subject: [PATCH 1445/2402] doc: Bluetooth: Change ordering of sections It makes more sense that way: A developer wants to know in order: - what features we have - if they are qualified/qualifiable - how the stack is architected / what parts are where - how to develop an app - tools to develop said apps (+ shell) Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/index.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/connectivity/bluetooth/index.rst b/doc/connectivity/bluetooth/index.rst index 3be74f47da2..6abf53d0cf4 100644 --- a/doc/connectivity/bluetooth/index.rst +++ b/doc/connectivity/bluetooth/index.rst @@ -14,11 +14,11 @@ hardware, as well as portions of a Classical Bluetooth (BR/EDR) Host layer. :maxdepth: 1 features.rst + bluetooth-qual.rst bluetooth-arch.rst - bluetooth-ctlr-arch.rst bluetooth-audio-arch.rst - bluetooth-qual.rst - bluetooth-tools.rst + bluetooth-ctlr-arch.rst bluetooth-dev.rst api/index.rst + bluetooth-tools.rst bluetooth-shell.rst From 89b64f821054ae9a6c8fba482e31c1312be5fed6 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 15:02:47 +0100 Subject: [PATCH 1446/2402] doc: Bluetooth: Audio -> LE Audio We now have BT Classic audio activity, we should be more specific. Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/bluetooth-arch.rst | 2 +- ...luetooth-audio-arch.rst => bluetooth-le-audio-arch.rst} | 7 +++---- doc/connectivity/bluetooth/features.rst | 2 +- doc/connectivity/bluetooth/index.rst | 2 +- 4 files changed, 6 insertions(+), 7 deletions(-) rename doc/connectivity/bluetooth/{bluetooth-audio-arch.rst => bluetooth-le-audio-arch.rst} (99%) diff --git a/doc/connectivity/bluetooth/bluetooth-arch.rst b/doc/connectivity/bluetooth/bluetooth-arch.rst index 0dc10e1ee9e..f6334e0db3f 100644 --- a/doc/connectivity/bluetooth/bluetooth-arch.rst +++ b/doc/connectivity/bluetooth/bluetooth-arch.rst @@ -386,7 +386,7 @@ LE Audio The LE audio is a set of profiles and services that utilizes GATT and Isochronous Channel to provide audio over Bluetooth Low Energy. The architecture and API references can be found in -:ref:`Bluetooth Audio Architecture `. +:ref:`Bluetooth Audio Architecture `. .. _bluetooth-persistent-storage: diff --git a/doc/connectivity/bluetooth/bluetooth-audio-arch.rst b/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst similarity index 99% rename from doc/connectivity/bluetooth/bluetooth-audio-arch.rst rename to doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst index 9efa8ded969..06603dca2e0 100644 --- a/doc/connectivity/bluetooth/bluetooth-audio-arch.rst +++ b/doc/connectivity/bluetooth/bluetooth-le-audio-arch.rst @@ -1,8 +1,7 @@ -.. _bluetooth_audio_arch: +.. _bluetooth_le_audio_arch: - -Audio Architecture -################## +LE Audio Stack +############## .. figure:: img/ble_audio_arch.svg :align: center diff --git a/doc/connectivity/bluetooth/features.rst b/doc/connectivity/bluetooth/features.rst index 01b3ff15490..5c23ff0a522 100644 --- a/doc/connectivity/bluetooth/features.rst +++ b/doc/connectivity/bluetooth/features.rst @@ -97,7 +97,7 @@ grown to be mature and feature-rich, as can be seen in the section below. * Verified with multiple popular controllers -* :ref:`LE Audio in Host and Controller ` +* :ref:`LE Audio in Host and Controller ` * Isochronous channels diff --git a/doc/connectivity/bluetooth/index.rst b/doc/connectivity/bluetooth/index.rst index 6abf53d0cf4..f7658284af3 100644 --- a/doc/connectivity/bluetooth/index.rst +++ b/doc/connectivity/bluetooth/index.rst @@ -16,7 +16,7 @@ hardware, as well as portions of a Classical Bluetooth (BR/EDR) Host layer. features.rst bluetooth-qual.rst bluetooth-arch.rst - bluetooth-audio-arch.rst + bluetooth-le-audio-arch.rst bluetooth-ctlr-arch.rst bluetooth-dev.rst api/index.rst From 629795d1ad54784c7860a0269a2eb7f94a564094 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Mon, 25 Mar 2024 15:05:31 +0100 Subject: [PATCH 1447/2402] doc: Bluetooth: add LE Host page We now have Classic activity in the tree. Make the distinction clearer. Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/bluetooth-arch.rst | 227 +----------------- .../bluetooth/bluetooth-le-host.rst | 204 ++++++++++++++++ doc/connectivity/bluetooth/features.rst | 2 +- doc/connectivity/bluetooth/index.rst | 1 + 4 files changed, 217 insertions(+), 217 deletions(-) create mode 100644 doc/connectivity/bluetooth/bluetooth-le-host.rst diff --git a/doc/connectivity/bluetooth/bluetooth-arch.rst b/doc/connectivity/bluetooth/bluetooth-arch.rst index f6334e0db3f..c36879fe02a 100644 --- a/doc/connectivity/bluetooth/bluetooth-arch.rst +++ b/doc/connectivity/bluetooth/bluetooth-arch.rst @@ -178,17 +178,18 @@ Source tree layout The stack is split up as follows in the source tree: ``subsys/bluetooth/host`` - The host stack. This is where the HCI command and event handling - as well as connection tracking happens. The implementation of the - core protocols such as L2CAP, ATT, and SMP is also here. + :ref:`The host stack `. This is where the HCI command and + event handling as well as connection tracking happens. The implementation of + the core protocols such as L2CAP, ATT, and SMP is also here. ``subsys/bluetooth/controller`` - Bluetooth Controller implementation. Implements the controller-side of - HCI, the Link Layer as well as access to the radio transceiver. + :ref:`Bluetooth LE Controller ` implementation. + Implements the controller-side of HCI, the Link Layer as well as access to the + radio transceiver. ``include/bluetooth/`` - Public API header files. These are the header files applications need - to include in order to use Bluetooth functionality. + :ref:`Public API ` header files. These are the header files + applications need to include in order to use Bluetooth functionality. ``drivers/bluetooth/`` HCI transport drivers. Every HCI transport needs its own driver. For example, @@ -196,221 +197,15 @@ The stack is split up as follows in the source tree: have their own drivers. ``samples/bluetooth/`` - Sample Bluetooth code. This is a good reference to get started with - Bluetooth application development. + :ref:`Sample Bluetooth code `. This is a good reference to + get started with Bluetooth application development. ``tests/bluetooth/`` Test applications. These applications are used to verify the functionality of the Bluetooth stack, but are not necessary the best source for sample code (see ``samples/bluetooth`` instead). -``doc/guides/bluetooth/`` +``doc/connectivity/bluetooth/`` Extra documentation, such as PICS documents. -.. _bluetooth-host: - -Host -**** - -The Bluetooth Host implements all the higher-level protocols and -profiles, and most importantly, provides a high-level API for -applications. The following diagram depicts the main protocol & profile -layers of the host. - -.. figure:: img/ble_host_layers.png - :align: center - :alt: Bluetooth Host protocol & profile layers - - Bluetooth Host protocol & profile layers. - -Lowest down in the host stack sits a so-called HCI driver, which is -responsible for abstracting away the details of the HCI transport. It -provides a basic API for delivering data from the controller to the -host, and vice-versa. - -Perhaps the most important block above the HCI handling is the Generic -Access Profile (GAP). GAP simplifies Bluetooth LE access by defining -four distinct roles of BLE usage: - -* Connection-oriented roles - - * Peripheral (e.g. a smart sensor, often with a limited user interface) - - * Central (typically a mobile phone or a PC) - -* Connection-less roles - - * Broadcaster (sending out BLE advertisements, e.g. a smart beacon) - - * Observer (scanning for BLE advertisements) - -Each role comes with its own build-time configuration option: -:kconfig:option:`CONFIG_BT_PERIPHERAL`, :kconfig:option:`CONFIG_BT_CENTRAL`, -:kconfig:option:`CONFIG_BT_BROADCASTER` & :kconfig:option:`CONFIG_BT_OBSERVER`. Of the -connection-oriented roles central implicitly enables observer role, and -peripheral implicitly enables broadcaster role. Usually the first step -when creating an application is to decide which roles are needed and go -from there. Bluetooth Mesh is a slightly special case, requiring at -least the observer and broadcaster roles, and possibly also the -Peripheral role. This will be described in more detail in a later -section. - -Peripheral role -=============== - -Most Zephyr-based BLE devices will most likely be peripheral-role -devices. This means that they perform connectable advertising and expose -one or more GATT services. After registering services using the -:c:func:`bt_gatt_service_register` API the application will typically -start connectable advertising using the :c:func:`bt_le_adv_start` API. - -There are several peripheral sample applications available in the tree, -such as :zephyr_file:`samples/bluetooth/peripheral_hr`. - -Central role -============ - -Central role may not be as common for Zephyr-based devices as peripheral -role, but it is still a plausible one and equally well supported in -Zephyr. Rather than accepting connections from other devices a central -role device will scan for available peripheral device and choose one to -connect to. Once connected, a central will typically act as a GATT -client, first performing discovery of available services and then -accessing one or more supported services. - -To initially discover a device to connect to the application will likely -use the :c:func:`bt_le_scan_start` API, wait for an appropriate device -to be found (using the scan callback), stop scanning using -:c:func:`bt_le_scan_stop` and then connect to the device using -:c:func:`bt_conn_le_create`. If the central wants to keep -automatically reconnecting to the peripheral it should use the -:c:func:`bt_le_set_auto_conn` API. - -There are some sample applications for the central role available in the -tree, such as :zephyr_file:`samples/bluetooth/central_hr`. - -Observer role -============= - -An observer role device will use the :c:func:`bt_le_scan_start` API to -scan for device, but it will not connect to any of them. Instead it will -simply utilize the advertising data of found devices, combining it -optionally with the received signal strength (RSSI). - -Broadcaster role -================ - -A broadcaster role device will use the :c:func:`bt_le_adv_start` API to -advertise specific advertising data, but the type of advertising will be -non-connectable, i.e. other device will not be able to connect to it. - -Connections -=========== - -Connection handling and the related APIs can be found in the -:ref:`Connection Management ` section. - -Security -======== - -To achieve a secure relationship between two Bluetooth devices a process -called pairing is used. This process can either be triggered implicitly -through the security properties of GATT services, or explicitly using -the :c:func:`bt_conn_security` API on a connection object. - -To achieve a higher security level, and protect against -Man-In-The-Middle (MITM) attacks, it is recommended to use some -out-of-band channel during the pairing. If the devices have a sufficient -user interface this "channel" is the user itself. The capabilities of -the device are registered using the :c:func:`bt_conn_auth_cb_register` -API. The :c:struct:`bt_conn_auth_cb` struct that's passed to this API has -a set of optional callbacks that can be used during the pairing - if the -device lacks some feature the corresponding callback may be set to NULL. -For example, if the device does not have an input method but does have a -display, the ``passkey_entry`` and ``passkey_confirm`` callbacks would -be set to NULL, but the ``passkey_display`` would be set to a callback -capable of displaying a passkey to the user. - -Depending on the local and remote security requirements & capabilities, -there are four possible security levels that can be reached: - - :c:enumerator:`BT_SECURITY_L1` - No encryption and no authentication. - - :c:enumerator:`BT_SECURITY_L2` - Encryption but no authentication (no MITM protection). - - :c:enumerator:`BT_SECURITY_L3` - Encryption and authentication using the legacy pairing method - from Bluetooth 4.0 and 4.1. - - :c:enumerator:`BT_SECURITY_L4` - Encryption and authentication using the LE Secure Connections - feature available since Bluetooth 4.2. - -.. note:: - Mesh has its own security solution through a process called - provisioning. It follows a similar procedure as pairing, but is done - using separate mesh-specific APIs. - -L2CAP -===== - -L2CAP stands for the Logical Link Control and Adaptation Protocol. It is -a common layer for all communication over Bluetooth connections, however -an application comes in direct contact with it only when using it in the -so-called Connection-oriented Channels (CoC) mode. More information on -this can be found in the :ref:`L2CAP API section `. - -GATT -==== - -The Generic Attribute Profile is the most common means of communication -over LE connections. A more detailed description of this layer and the -API reference can be found in the -:ref:`GATT API reference section `. - -Mesh -==== - -Mesh is a little bit special when it comes to the needed GAP roles. By -default, mesh requires both observer and broadcaster role to be enabled. -If the optional GATT Proxy feature is desired, then peripheral role -should also be enabled. - -The API reference for mesh can be found in the -:ref:`Mesh API reference section `. - -LE Audio -======== -The LE audio is a set of profiles and services that utilizes GATT and -Isochronous Channel to provide audio over Bluetooth Low Energy. -The architecture and API references can be found in -:ref:`Bluetooth Audio Architecture `. - - -.. _bluetooth-persistent-storage: - -Persistent storage -================== - -The Bluetooth host stack uses the settings subsystem to implement -persistent storage to flash. This requires the presence of a flash -driver and a designated "storage" partition on flash. A typical set of -configuration options needed will look something like the following: - - .. code-block:: none - - CONFIG_BT_SETTINGS=y - CONFIG_FLASH=y - CONFIG_FLASH_PAGE_LAYOUT=y - CONFIG_FLASH_MAP=y - CONFIG_NVS=y - CONFIG_SETTINGS=y - -Once enabled, it is the responsibility of the application to call -settings_load() after having initialized Bluetooth (using the -bt_enable() API). - - .. _Bluetooth Specification: https://www.bluetooth.com/specifications/bluetooth-core-specification diff --git a/doc/connectivity/bluetooth/bluetooth-le-host.rst b/doc/connectivity/bluetooth/bluetooth-le-host.rst new file mode 100644 index 00000000000..a9e0ef81723 --- /dev/null +++ b/doc/connectivity/bluetooth/bluetooth-le-host.rst @@ -0,0 +1,204 @@ +.. _bluetooth_le_host: + +LE Host +####### + +The Bluetooth Host implements all the higher-level protocols and +profiles, and most importantly, provides a high-level API for +applications. The following diagram depicts the main protocol & profile +layers of the host. + +.. figure:: img/ble_host_layers.png + :align: center + :alt: Bluetooth Host protocol & profile layers + + Bluetooth Host protocol & profile layers. + +Lowest down in the host stack sits a so-called HCI driver, which is +responsible for abstracting away the details of the HCI transport. It +provides a basic API for delivering data from the controller to the +host, and vice-versa. + +Perhaps the most important block above the HCI handling is the Generic +Access Profile (GAP). GAP simplifies Bluetooth LE access by defining +four distinct roles of BLE usage: + +* Connection-oriented roles + + * Peripheral (e.g. a smart sensor, often with a limited user interface) + + * Central (typically a mobile phone or a PC) + +* Connection-less roles + + * Broadcaster (sending out BLE advertisements, e.g. a smart beacon) + + * Observer (scanning for BLE advertisements) + +Each role comes with its own build-time configuration option: +:kconfig:option:`CONFIG_BT_PERIPHERAL`, :kconfig:option:`CONFIG_BT_CENTRAL`, +:kconfig:option:`CONFIG_BT_BROADCASTER` & :kconfig:option:`CONFIG_BT_OBSERVER`. Of the +connection-oriented roles central implicitly enables observer role, and +peripheral implicitly enables broadcaster role. Usually the first step +when creating an application is to decide which roles are needed and go +from there. Bluetooth Mesh is a slightly special case, requiring at +least the observer and broadcaster roles, and possibly also the +Peripheral role. This will be described in more detail in a later +section. + +Peripheral role +=============== + +Most Zephyr-based BLE devices will most likely be peripheral-role +devices. This means that they perform connectable advertising and expose +one or more GATT services. After registering services using the +:c:func:`bt_gatt_service_register` API the application will typically +start connectable advertising using the :c:func:`bt_le_adv_start` API. + +There are several peripheral sample applications available in the tree, +such as :zephyr_file:`samples/bluetooth/peripheral_hr`. + +Central role +============ + +Central role may not be as common for Zephyr-based devices as peripheral +role, but it is still a plausible one and equally well supported in +Zephyr. Rather than accepting connections from other devices a central +role device will scan for available peripheral device and choose one to +connect to. Once connected, a central will typically act as a GATT +client, first performing discovery of available services and then +accessing one or more supported services. + +To initially discover a device to connect to the application will likely +use the :c:func:`bt_le_scan_start` API, wait for an appropriate device +to be found (using the scan callback), stop scanning using +:c:func:`bt_le_scan_stop` and then connect to the device using +:c:func:`bt_conn_le_create`. If the central wants to keep +automatically reconnecting to the peripheral it should use the +:c:func:`bt_le_set_auto_conn` API. + +There are some sample applications for the central role available in the +tree, such as :zephyr_file:`samples/bluetooth/central_hr`. + +Observer role +============= + +An observer role device will use the :c:func:`bt_le_scan_start` API to +scan for device, but it will not connect to any of them. Instead it will +simply utilize the advertising data of found devices, combining it +optionally with the received signal strength (RSSI). + +Broadcaster role +================ + +A broadcaster role device will use the :c:func:`bt_le_adv_start` API to +advertise specific advertising data, but the type of advertising will be +non-connectable, i.e. other device will not be able to connect to it. + +Connections +=========== + +Connection handling and the related APIs can be found in the +:ref:`Connection Management ` section. + +Security +======== + +To achieve a secure relationship between two Bluetooth devices a process +called pairing is used. This process can either be triggered implicitly +through the security properties of GATT services, or explicitly using +the :c:func:`bt_conn_security` API on a connection object. + +To achieve a higher security level, and protect against +Man-In-The-Middle (MITM) attacks, it is recommended to use some +out-of-band channel during the pairing. If the devices have a sufficient +user interface this "channel" is the user itself. The capabilities of +the device are registered using the :c:func:`bt_conn_auth_cb_register` +API. The :c:struct:`bt_conn_auth_cb` struct that's passed to this API has +a set of optional callbacks that can be used during the pairing - if the +device lacks some feature the corresponding callback may be set to NULL. +For example, if the device does not have an input method but does have a +display, the ``passkey_entry`` and ``passkey_confirm`` callbacks would +be set to NULL, but the ``passkey_display`` would be set to a callback +capable of displaying a passkey to the user. + +Depending on the local and remote security requirements & capabilities, +there are four possible security levels that can be reached: + + :c:enumerator:`BT_SECURITY_L1` + No encryption and no authentication. + + :c:enumerator:`BT_SECURITY_L2` + Encryption but no authentication (no MITM protection). + + :c:enumerator:`BT_SECURITY_L3` + Encryption and authentication using the legacy pairing method + from Bluetooth 4.0 and 4.1. + + :c:enumerator:`BT_SECURITY_L4` + Encryption and authentication using the LE Secure Connections + feature available since Bluetooth 4.2. + +.. note:: + Mesh has its own security solution through a process called + provisioning. It follows a similar procedure as pairing, but is done + using separate mesh-specific APIs. + +L2CAP +===== + +L2CAP stands for the Logical Link Control and Adaptation Protocol. It is +a common layer for all communication over Bluetooth connections, however +an application comes in direct contact with it only when using it in the +so-called Connection-oriented Channels (CoC) mode. More information on +this can be found in the :ref:`L2CAP API section `. + +GATT +==== + +The Generic Attribute Profile is the most common means of communication +over LE connections. A more detailed description of this layer and the +API reference can be found in the +:ref:`GATT API reference section `. + +Mesh +==== + +Mesh is a little bit special when it comes to the needed GAP roles. By +default, mesh requires both observer and broadcaster role to be enabled. +If the optional GATT Proxy feature is desired, then peripheral role +should also be enabled. + +The API reference for mesh can be found in the +:ref:`Mesh API reference section `. + +LE Audio +======== +The LE audio is a set of profiles and services that utilizes GATT and +Isochronous Channel to provide audio over Bluetooth Low Energy. +The architecture and API references can be found in +:ref:`Bluetooth Audio Architecture `. + + +.. _bluetooth-persistent-storage: + +Persistent storage +================== + +The Bluetooth host stack uses the settings subsystem to implement +persistent storage to flash. This requires the presence of a flash +driver and a designated "storage" partition on flash. A typical set of +configuration options needed will look something like the following: + + .. code-block:: none + + CONFIG_BT_SETTINGS=y + CONFIG_FLASH=y + CONFIG_FLASH_PAGE_LAYOUT=y + CONFIG_FLASH_MAP=y + CONFIG_NVS=y + CONFIG_SETTINGS=y + +Once enabled, it is the responsibility of the application to call +settings_load() after having initialized Bluetooth (using the +bt_enable() API). diff --git a/doc/connectivity/bluetooth/features.rst b/doc/connectivity/bluetooth/features.rst index 5c23ff0a522..09c79f48cad 100644 --- a/doc/connectivity/bluetooth/features.rst +++ b/doc/connectivity/bluetooth/features.rst @@ -48,7 +48,7 @@ grown to be mature and feature-rich, as can be seen in the section below. module * Support for Controller (HCI) builds over different physical transports -* :ref:`Bluetooth Host ` +* :ref:`Bluetooth Host ` * Generic Access Profile (GAP) with all possible LE roles diff --git a/doc/connectivity/bluetooth/index.rst b/doc/connectivity/bluetooth/index.rst index f7658284af3..c4f43563e6d 100644 --- a/doc/connectivity/bluetooth/index.rst +++ b/doc/connectivity/bluetooth/index.rst @@ -16,6 +16,7 @@ hardware, as well as portions of a Classical Bluetooth (BR/EDR) Host layer. features.rst bluetooth-qual.rst bluetooth-arch.rst + bluetooth-le-host.rst bluetooth-le-audio-arch.rst bluetooth-ctlr-arch.rst bluetooth-dev.rst From 08ba810ffe65b50e18e858344544da4a7118169b Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Tue, 26 Mar 2024 08:01:17 +0100 Subject: [PATCH 1448/2402] doc: Bluetooth: LE host touch-ups Addresses review comments on text I only moved. Signed-off-by: Jonathan Rico --- doc/connectivity/bluetooth/bluetooth-le-host.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/connectivity/bluetooth/bluetooth-le-host.rst b/doc/connectivity/bluetooth/bluetooth-le-host.rst index a9e0ef81723..26b21f8ca2b 100644 --- a/doc/connectivity/bluetooth/bluetooth-le-host.rst +++ b/doc/connectivity/bluetooth/bluetooth-le-host.rst @@ -190,7 +190,7 @@ persistent storage to flash. This requires the presence of a flash driver and a designated "storage" partition on flash. A typical set of configuration options needed will look something like the following: - .. code-block:: none + .. code-block:: cfg CONFIG_BT_SETTINGS=y CONFIG_FLASH=y @@ -201,4 +201,4 @@ configuration options needed will look something like the following: Once enabled, it is the responsibility of the application to call settings_load() after having initialized Bluetooth (using the -bt_enable() API). +:c:func:`bt_enable` API). From 88d8b238369ae316d9d764e61dfdac4cf8048693 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Thu, 7 Mar 2024 10:06:34 +0100 Subject: [PATCH 1449/2402] scripts: remove board name from the qualifiers in list_boards.py Fixes: #69329 The board name was printed as part of printing board qualifiers because those was being concatenated in the `board_v2_qualifiers()` method. Keep the qualifiers separated from the board name and let the caller concatenate the strings when required. Completion scripts are also updated to handle the corrected behaviour. Signed-off-by: Torsten Rasmussen (cherry picked from commit 66b475a3aa4d73f4ddd5be5a7a1e0f3c7028e539) --- cmake/modules/boards.cmake | 8 +++++--- scripts/ci/check_compliance.py | 3 ++- scripts/list_boards.py | 18 +++++++----------- .../completion/west-completion.bash | 9 +++++++-- .../completion/west-completion.fish | 19 ++++++------------- .../completion/west-completion.zsh | 9 ++++++--- 6 files changed, 33 insertions(+), 33 deletions(-) diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index 63e2b7af4cc..ee81b264c1f 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -285,12 +285,14 @@ elseif(HWMv2) string(REGEX REPLACE "^//" "/${LIST_BOARD_SOCS}/" BOARD_QUALIFIERS "${BOARD_QUALIFIERS}") endif() - if(NOT ("${BOARD}${BOARD_QUALIFIERS}" IN_LIST LIST_BOARD_QUALIFIERS)) - string(REPLACE ";" "\n" LIST_BOARD_QUALIFIERS "${LIST_BOARD_QUALIFIERS}") + set(board_targets ${LIST_BOARD_QUALIFIERS}) + list(TRANSFORM board_targets PREPEND "${BOARD}/") + if(NOT ("${BOARD}${BOARD_QUALIFIERS}" IN_LIST board_targets)) + string(REPLACE ";" "\n" board_targets "${board_targets}") unset(CACHED_BOARD CACHE) message(FATAL_ERROR "Board qualifiers `${BOARD_QUALIFIERS}` for board \ `${BOARD}` not found. Please specify a valid board target.\n" - "Valid board qualifiers for ${BOARD_NAME} are:\n${LIST_BOARD_QUALIFIERS}\n") + "Valid board targets for ${BOARD_NAME} are:\n${board_targets}\n") endif() endif() else() diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index c351643401c..a77bd580453 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -449,7 +449,8 @@ def get_v2_model(self, kconfig_dir): fp.write('config ' + board_str + '\n') fp.write('\t bool\n') for qualifier in list_boards.board_v2_qualifiers(board): - board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", qualifier).upper() + board_str = ('BOARD_' + board.name + '_' + + re.sub(r"[^a-zA-Z0-9_]", "_", qualifier)).upper() fp.write('config ' + board_str + '\n') fp.write('\t bool\n') fp.write( diff --git a/scripts/list_boards.py b/scripts/list_boards.py index 03b1adaca83..5321f31b0bc 100755 --- a/scripts/list_boards.py +++ b/scripts/list_boards.py @@ -275,10 +275,10 @@ def add_args_formatting(parser): help='''CMake Format string to use to list each board''') -def variant_v2_qualifiers(variant, qualifiers): - qualifiers_list = [qualifiers + '/' + variant.name] +def variant_v2_qualifiers(variant, qualifiers = None): + qualifiers_list = [variant.name] if qualifiers is None else [qualifiers + '/' + variant.name] for v in variant.variants: - qualifiers_list.extend(variant_v2_qualifiers(v, qualifiers + '/' + variant.name)) + qualifiers_list.extend(variant_v2_qualifiers(v, qualifiers_list[0])) return qualifiers_list @@ -288,21 +288,17 @@ def board_v2_qualifiers(board): for s in board.socs: if s.cpuclusters: for c in s.cpuclusters: - id_str = board.name + '/' + s.name + '/' + c.name + id_str = s.name + '/' + c.name qualifiers_list.append(id_str) for v in c.variants: qualifiers_list.extend(variant_v2_qualifiers(v, id_str)) else: - id_str = board.name + '/' + s.name - qualifiers_list.append(id_str) + qualifiers_list.append(s.name) for v in s.variants: - qualifiers_list.extend(variant_v2_qualifiers(v, id_str)) - - if not board.socs: - qualifiers_list.append(board.name) + qualifiers_list.extend(variant_v2_qualifiers(v, s.name)) for v in board.variants: - qualifiers_list.extend(variant_v2_qualifiers(v, board.name)) + qualifiers_list.extend(variant_v2_qualifiers(v)) return qualifiers_list diff --git a/scripts/west_commands/completion/west-completion.bash b/scripts/west_commands/completion/west-completion.bash index 2ccc4446ad3..d812e8933b1 100644 --- a/scripts/west_commands/completion/west-completion.bash +++ b/scripts/west_commands/completion/west-completion.bash @@ -392,8 +392,13 @@ __set_comp_west_projs() __set_comp_west_boards() { - boards="$(__west_x boards --format={identifiers} "$@")\n$(__west_x boards --format={name} "$@")" - __set_comp ${boards//,/\ } + boards=( $(__west_x boards --format='{name}|{qualifiers}' "$@") ) + for i in ${!boards[@]}; do + name="${boards[$i]%%|*}" + transformed_board="${boards[$i]//|//}" + boards[$i]="${transformed_board//,/\ ${name}\/}" + done + __set_comp ${boards[@]} } __comp_west_west() diff --git a/scripts/west_commands/completion/west-completion.fish b/scripts/west_commands/completion/west-completion.fish index 33c6942dd8e..51e61141e8a 100644 --- a/scripts/west_commands/completion/west-completion.fish +++ b/scripts/west_commands/completion/west-completion.fish @@ -196,19 +196,12 @@ function __zephyr_west_complete_help end function __zephyr_west_complete_board - # HWMv1 - set -l boards (west 2>/dev/null boards --format="{name} {arch}") + set -l boards (west 2>/dev/null boards --format="{name}|{qualifiers}") for board in $boards - set -l b (string split " " $board) - printf "%s\n" $b[1]\t"$b[2]" - end - - # HWMv2 - set -l boards (west 2>/dev/null boards --format="{identifiers}") - for board in $boards - set -l b (string split "," $board) - for variant in $b - printf "%s\n" $variant[1] + set -l b (string split "|" $board) + set -l qualifiers (string split "," $b[2]) + for i in $qualifiers + printf "%s\n" $b[1]/$i end end end @@ -307,7 +300,7 @@ complete -c west -n "__zephyr_west_seen_subcommand_from boards" -l soc-root -xa # build complete -c west -n "__zephyr_west_use_subcommand; and __zephyr_west_check_if_in_workspace" -ra build -d "compile a Zephyr application" complete -c west -n "__zephyr_west_seen_subcommand_from build" -ra "(__zephyr_west_complete_directories)" -complete -c west -n "__zephyr_west_seen_subcommand_from build" -o b -l board -xa "(__zephyr_west_complete_board)" -d "board to build for" +complete -c west -n "__zephyr_west_seen_subcommand_from build" -o b -l board -xa "(__zephyr_west_complete_board)" complete -c west -n "__zephyr_west_seen_subcommand_from build" -o d -l build-dir -xa "(__zephyr_west_complete_directories)" -d "build directory to create or use" complete -c west -n "__zephyr_west_seen_subcommand_from build" -o f -l force -d "ignore errors and continue" complete -c west -n "__zephyr_west_seen_subcommand_from build" -l sysbuild -d "create multi-domain build system" diff --git a/scripts/west_commands/completion/west-completion.zsh b/scripts/west_commands/completion/west-completion.zsh index 000b43a87b3..e1a01199884 100644 --- a/scripts/west_commands/completion/west-completion.zsh +++ b/scripts/west_commands/completion/west-completion.zsh @@ -102,9 +102,12 @@ _get_west_projs() { } _get_west_boards() { - _west_boards="$(__west_x boards --format={identifiers})\n$(__west_x boards --format={name})" - _west_boards=${_west_boards//$'\n'/\ } - _west_boards=${_west_boards//,/\ } + _west_boards=( $(__west_x boards --format='{name}|{qualifiers}') ) + for i in {1..${#_west_boards[@]}}; do + local name="${_west_boards[$i]%%|*}" + local transformed_board="${_west_boards[$i]//|//}" + _west_boards[$i]="${transformed_board//,/ ${name}/}" + done _west_boards=(${(@s/ /)_west_boards}) _describe 'boards' _west_boards From 4acb615c14920bb58b5ddaa6e622d9e5ef04d7ce Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Fri, 22 Mar 2024 20:17:03 +0100 Subject: [PATCH 1450/2402] cmake: boards: Error out if multiple boards use the same name Detecting this requires `boards.cmake` being able to handle multi-line output from `list_boards.py`. Implement a similar line reading loop to the one used in `hwm_v2.cmake`. Failing to handle this could result in an incorrectly parsed list of valid board qualifiers. Here's the expected list for `nrf52_bsim`: - "native" and here's what would happen if two copies of that board were found: - "native\nNAME" - "nrf52_bsim" - "native" Instead of that, there would now be a proper error message listing all board directories which contain `nrf52_bsim`. Signed-off-by: Grzegorz Swiderski --- cmake/modules/boards.cmake | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index ee81b264c1f..f76d89a8427 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -195,6 +195,24 @@ endif() if(NOT "${ret_board}" STREQUAL "") string(STRIP "${ret_board}" ret_board) + string(FIND "${ret_board}" "\n" idx REVERSE) + if(idx GREATER -1) + while(TRUE) + math(EXPR start "${idx} + 1") + string(SUBSTRING "${ret_board}" ${start} -1 line) + string(SUBSTRING "${ret_board}" 0 ${idx} ret_board) + + cmake_parse_arguments(LIST_BOARD "" "DIR" "" ${line}) + set(board_dirs "${board_dirs}\n${LIST_BOARD_DIR}") + + if(idx EQUAL -1) + break() + endif() + string(FIND "${ret_board}" "\n" idx REVERSE) + endwhile() + message(FATAL_ERROR "Multiple boards named '${BOARD}' found in:${board_dirs}") + endif() + set(single_val "NAME;DIR;HWM;REVISION_FORMAT;REVISION_DEFAULT;REVISION_EXACT") set(multi_val "REVISIONS;SOCS;QUALIFIERS") cmake_parse_arguments(LIST_BOARD "" "${single_val}" "${multi_val}" ${ret_board}) From 9dabce43d2307578f620fe45b497d4c415cb3fc6 Mon Sep 17 00:00:00 2001 From: Grzegorz Swiderski Date: Fri, 22 Mar 2024 20:17:03 +0100 Subject: [PATCH 1451/2402] scripts: Ignore duplicate roots in list_boards/hardware When iterating over `--arch-root`, `--board-root`, and `--soc-root`, treat them as collections of absolute paths with no repeats, to ensure that no input root has to be handled more than once. Signed-off-by: Grzegorz Swiderski --- scripts/list_boards.py | 7 ++++--- scripts/list_hardware.py | 9 +++++++-- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/scripts/list_boards.py b/scripts/list_boards.py index 5321f31b0bc..597ecf91809 100755 --- a/scripts/list_boards.py +++ b/scripts/list_boards.py @@ -13,6 +13,7 @@ from typing import List import yaml import list_hardware +from list_hardware import unique_paths BOARD_SCHEMA_PATH = str(Path(__file__).parent / 'schemas' / 'board-schema.yml') with open(BOARD_SCHEMA_PATH, 'r') as f: @@ -116,7 +117,7 @@ def find_arch2board_set(args): arches = sorted(find_arches(args)) ret = defaultdict(set) - for root in args.board_roots: + for root in unique_paths(args.board_roots): for arch, boards in find_arch2board_set_in(root, arches, args.board_dir).items(): if args.board is not None: ret[arch] |= {b for b in boards if b.name == args.board} @@ -129,7 +130,7 @@ def find_arch2board_set(args): def find_arches(args): arch_set = set() - for root in args.arch_roots: + for root in unique_paths(args.arch_roots): arch_set |= find_arches_in(root) return arch_set @@ -236,7 +237,7 @@ def find_v2_boards(args): boards = [] board_files = [] - for root in args.board_roots: + for root in unique_paths(args.board_roots): board_files.extend((root / 'boards').rglob(BOARD_YML)) for board_yml in board_files: diff --git a/scripts/list_hardware.py b/scripts/list_hardware.py index e17ff7b4532..2fa7c2a3638 100755 --- a/scripts/list_hardware.py +++ b/scripts/list_hardware.py @@ -141,9 +141,14 @@ class Family: socs: List[Soc] +def unique_paths(paths): + # Using dict keys ensures both uniqueness and a deterministic order. + yield from dict.fromkeys(map(Path.resolve, paths)).keys() + + def find_v2_archs(args): ret = {'archs': []} - for root in args.arch_roots: + for root in unique_paths(args.arch_roots): archs_yml = root / ARCHS_YML_PATH if Path(archs_yml).is_file(): @@ -172,7 +177,7 @@ def find_v2_archs(args): def find_v2_systems(args): yml_files = [] systems = Systems() - for root in args.soc_roots: + for root in unique_paths(args.soc_roots): yml_files.extend(sorted((root / 'soc').rglob(SOC_YML))) for soc_yml in yml_files: From b668f41424de66a89981fcb13ea7515f555cae36 Mon Sep 17 00:00:00 2001 From: David Leach Date: Tue, 26 Mar 2024 07:29:08 -0500 Subject: [PATCH 1452/2402] maintainers: Move JiafeiPan as NXP MPU maintainer Move JiafeiPan as NXP MPU maintainer. Move dleach02 down to collaborators. Signed-off-by: David Leach --- MAINTAINERS.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 36c22687aec..9cad7645513 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3379,9 +3379,9 @@ NXP Platforms (S32): NXP Platforms (MPU): status: maintained maintainers: - - dleach02 - collaborators: - JiafeiPan + collaborators: + - dleach02 - dbaluta - iuliana-prodan - danieldegrasse From f9e3084dafadf7f14ceae871b7fc18b457b68df2 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 16 Feb 2024 16:52:56 +0100 Subject: [PATCH 1453/2402] scripts/checkpatch: Limit which feature test macros we prevent Unfortunately this check as it is today is causing trouble, while not checking too well for what it intended. Let's reduce its scope until a better solution has been found. Background: This check intends to ensure coding guidelines Rules A.4 and A.5 are followed, but how it is implemented it does not work well enough. 1. These rules only apply to the kernel and some other parts of the embedded codebase respectively, but this check is performed on the whole tree. 2. This check works under the assumption that any attempt to set these macros in source files is a violation of these rules, while this is not necessary the case, as there are legitimate uses for these. (Specially for _POSIX_C_SOURCE and _XOPEN_SOURCE) This check also fails to detect these macros being set in cmake files, so if users are faced with this failure they can trivially bypass it. Having a CI check which produces too many false positives, while at the same time being very easy to bypass is not a desirable situation as that can result in lack of trust for this type of checks, and an overall tendency to override these CI faults, and overlooking actual violations of these rules by reviewers. This check was originally added in b021dece987d691342636dad836d6c9611d510e1 Signed-off-by: Alberto Escolar Piedras --- scripts/checkpatch.pl | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index b3bfd180cca..833b11886fa 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -600,10 +600,8 @@ sub hash_show_words { _GNU_SOURCE| _ISOC11_SOURCE| _ISOC99_SOURCE| - _POSIX_C_SOURCE| _POSIX_SOURCE| _SVID_SOURCE| - _XOPEN_SOURCE| _XOPEN_SOURCE_EXTENDED )}; @@ -6550,7 +6548,7 @@ sub process { if ($line =~ /#\s*define\s+$api_defines/) { ERROR("API_DEFINE", - "do not specify a non-Zephyr API for libc\n" . "$here$rawline\n"); + "do not specify non-standard feature test macros for embedded code\n" . "$here$rawline\n"); } # check for IS_ENABLED() without CONFIG_ ($rawline for comments too) From 55abfcb31e92c7f66ce000ca82cf9145623da667 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 14 Mar 2023 11:54:16 -0500 Subject: [PATCH 1454/2402] drivers: dma: Update NXP EDMA driver for version 4 1. Update EDMA driver for version 4 2. The DMAMux module is not always present. Use the feature define to make this optional. 3. Use the EDMA_SetChannelMux API for SoC's that supports this feature. Signed-off-by: Mahesh Mahadevan --- drivers/dma/CMakeLists.txt | 1 + drivers/dma/Kconfig.mcux_edma | 11 +++- drivers/dma/dma_mcux_edma.c | 85 +++++++++++++++++++------- drivers/dma/dma_mcux_edma.h | 5 +- dts/bindings/dma/nxp,mcux-edma-v4.yaml | 14 +++++ 5 files changed, 90 insertions(+), 26 deletions(-) create mode 100644 dts/bindings/dma/nxp,mcux-edma-v4.yaml diff --git a/drivers/dma/CMakeLists.txt b/drivers/dma/CMakeLists.txt index 7231848a05a..5b2a2ea3353 100644 --- a/drivers/dma/CMakeLists.txt +++ b/drivers/dma/CMakeLists.txt @@ -16,6 +16,7 @@ zephyr_library_sources_ifdef(CONFIG_DMA_SAM0 dma_sam0.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE dma_handlers.c) zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_EDMA dma_mcux_edma.c) zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_EDMA_V3 dma_mcux_edma.c) +zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_EDMA_V4 dma_mcux_edma.c) zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_LPC dma_mcux_lpc.c) zephyr_library_sources_ifdef(CONFIG_DMA_PL330 dma_pl330.c) zephyr_library_sources_ifdef(CONFIG_DMA_IPROC_PAX dma_iproc_pax_v1.c) diff --git a/drivers/dma/Kconfig.mcux_edma b/drivers/dma/Kconfig.mcux_edma index 6abf1cba489..62ab6d932a3 100644 --- a/drivers/dma/Kconfig.mcux_edma +++ b/drivers/dma/Kconfig.mcux_edma @@ -18,7 +18,14 @@ config DMA_MCUX_EDMA_V3 help DMA version 3 driver for MCUX series SoCs. -if DMA_MCUX_EDMA || DMA_MCUX_EDMA_V3 +config DMA_MCUX_EDMA_V4 + bool "MCUX DMA v4 driver" + default y + depends on DT_HAS_NXP_MCUX_EDMA_V4_ENABLED + help + DMA version 4 driver for MCUX series SoCs. + +if DMA_MCUX_EDMA || DMA_MCUX_EDMA_V3 || DMA_MCUX_EDMA_V4 config DMA_TCD_QUEUE_SIZE int "number of TCD in a queue for SG mode" @@ -41,4 +48,4 @@ config DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS When this option is activated, the descriptors for DMA transfer are located in the DTCM (Data Tightly Coupled Memory). -endif # DMA_MCUX_EDMA || DMA_MCUX_EDMA_V3 +endif # DMA_MCUX_EDMA || DMA_MCUX_EDMA_V3 || DMA_MCUX_EDMA_V4 diff --git a/drivers/dma/dma_mcux_edma.c b/drivers/dma/dma_mcux_edma.c index bc40f1c3a9e..26c7cf58c34 100644 --- a/drivers/dma/dma_mcux_edma.c +++ b/drivers/dma/dma_mcux_edma.c @@ -1,6 +1,5 @@ /* - * Copyright (c) 2020 NXP Semiconductor INC. - * All rights reserved. + * Copyright 2020-23 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -28,6 +27,8 @@ #define DT_DRV_COMPAT nxp_mcux_edma #elif CONFIG_DMA_MCUX_EDMA_V3 #define DT_DRV_COMPAT nxp_mcux_edma_v3 +#elif CONFIG_DMA_MCUX_EDMA_V4 +#define DT_DRV_COMPAT nxp_mcux_edma_v4 #endif LOG_MODULE_REGISTER(dma_mcux_edma, CONFIG_DMA_LOG_LEVEL); @@ -37,7 +38,9 @@ LOG_MODULE_REGISTER(dma_mcux_edma, CONFIG_DMA_LOG_LEVEL); struct dma_mcux_edma_config { DMA_Type *base; +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT DMAMUX_Type **dmamux_base; +#endif uint8_t channels_per_mux; uint8_t dmamux_reg_offset; int dma_channels; /* number of channels */ @@ -120,11 +123,13 @@ struct dma_mcux_edma_data { #define DEV_EDMA_HANDLE(dev, ch) \ ((edma_handle_t *)(&(DEV_CHANNEL_DATA(dev, ch)->edma_handle))) +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT #define DEV_DMAMUX_BASE(dev, idx) ((DMAMUX_Type *)DEV_CFG(dev)->dmamux_base[idx]) #define DEV_DMAMUX_IDX(dev, ch) (ch / DEV_CFG(dev)->channels_per_mux) #define DEV_DMAMUX_CHANNEL(dev, ch) \ (ch % DEV_CFG(dev)->channels_per_mux) ^ (DEV_CFG(dev)->dmamux_reg_offset) +#endif /* * The hardware channel (takes the gap into account) is used when access DMA registers. @@ -163,7 +168,7 @@ static bool data_size_valid(const size_t data_size) return (data_size == 4U || data_size == 2U || data_size == 1U || data_size == 8U || data_size == 16U || data_size == 32U -#ifdef CONFIG_DMA_MCUX_EDMA_V3 +#if defined(CONFIG_DMA_MCUX_EDMA_V3) || defined(CONFIG_DMA_MCUX_EDMA_V4) || data_size == 64U #endif ); @@ -246,7 +251,6 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, struct call_back *data = DEV_CHANNEL_DATA(dev, channel); struct dma_block_config *block_config = config->head_block; uint32_t slot = config->dma_slot; - uint8_t dmamux_idx, dmamux_channel; uint32_t hw_channel; edma_transfer_type_t transfer_type; unsigned int key; @@ -263,8 +267,12 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, } hw_channel = dma_mcux_edma_add_channel_gap(dev, channel); +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT + uint8_t dmamux_idx, dmamux_channel; + dmamux_idx = DEV_DMAMUX_IDX(dev, channel); dmamux_channel = DEV_DMAMUX_CHANNEL(dev, channel); +#endif data->transfer_settings.valid = false; switch (config->channel_direction) { @@ -314,6 +322,8 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, /* Lock and page in the channel configuration */ key = irq_lock(); +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT + #if DT_INST_PROP(0, nxp_a_on) if (config->source_handshake || config->dest_handshake || transfer_type == kEDMA_MemoryToMemory) { @@ -330,6 +340,8 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, /* dam_imx_rt_set_channel_priority(dev, channel, config); */ DMAMUX_EnableChannel(DEV_DMAMUX_BASE(dev, dmamux_idx), dmamux_channel); +#endif + if (data->busy) { EDMA_AbortTransfer(p_handle); } @@ -337,6 +349,12 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, EDMA_CreateHandle(p_handle, DEV_BASE(dev), hw_channel); EDMA_SetCallback(p_handle, nxp_edma_callback, (void *)data); +#if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX + /* First release any peripheral previously associated with this channel */ + EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, 0); + EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, slot); +#endif + LOG_DBG("channel is %d", channel); EDMA_EnableChannelInterrupts(DEV_BASE(dev), hw_channel, kEDMA_ErrorInterruptEnable); @@ -377,7 +395,7 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, LOG_ERR("Error submitting EDMA Transfer: 0x%x", submit_status); ret = -EFAULT; } -#ifdef CONFIG_DMA_MCUX_EDMA_V3 +#if defined(CONFIG_DMA_MCUX_EDMA_V3) || defined(CONFIG_DMA_MCUX_EDMA_V4) LOG_DBG("DMA TCD_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].TCD_CSR); #else LOG_DBG("data csr is 0x%x", DEV_BASE(dev)->TCD[hw_channel].CSR); @@ -411,13 +429,17 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, static int dma_mcux_edma_start(const struct device *dev, uint32_t channel) { struct call_back *data = DEV_CHANNEL_DATA(dev, channel); + + LOG_DBG("START TRANSFER"); + +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT uint8_t dmamux_idx = DEV_DMAMUX_IDX(dev, channel); uint8_t dmamux_channel = DEV_DMAMUX_CHANNEL(dev, channel); - LOG_DBG("START TRANSFER"); LOG_DBG("DMAMUX CHCFG 0x%x", DEV_DMAMUX_BASE(dev, dmamux_idx)->CHCFG[dmamux_channel]); +#endif -#ifndef CONFIG_DMA_MCUX_EDMA_V3 +#if !defined(CONFIG_DMA_MCUX_EDMA_V3) && !defined(CONFIG_DMA_MCUX_EDMA_V4) LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR); #endif data->busy = true; @@ -518,9 +540,6 @@ static int dma_mcux_edma_reload(const struct device *dev, uint32_t channel, static int dma_mcux_edma_get_status(const struct device *dev, uint32_t channel, struct dma_status *status) { - uint8_t dmamux_idx = DEV_DMAMUX_IDX(dev, channel); - uint8_t dmamux_channel = DEV_DMAMUX_CHANNEL(dev, channel); - uint32_t hw_channel = dma_mcux_edma_add_channel_gap(dev, channel); if (DEV_CHANNEL_DATA(dev, channel)->busy) { @@ -532,9 +551,15 @@ static int dma_mcux_edma_get_status(const struct device *dev, uint32_t channel, status->pending_length = 0; } status->dir = DEV_CHANNEL_DATA(dev, channel)->transfer_settings.direction; + +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT + uint8_t dmamux_idx = DEV_DMAMUX_IDX(dev, channel); + uint8_t dmamux_channel = DEV_DMAMUX_CHANNEL(dev, channel); + LOG_DBG("DMAMUX CHCFG 0x%x", DEV_DMAMUX_BASE(dev, dmamux_idx)->CHCFG[dmamux_channel]); +#endif -#ifdef CONFIG_DMA_MCUX_EDMA_V3 +#if defined(CONFIG_DMA_MCUX_EDMA_V3) || defined(CONFIG_DMA_MCUX_EDMA_V4) LOG_DBG("DMA MP_CSR 0x%x", DEV_BASE(dev)->MP_CSR); LOG_DBG("DMA MP_ES 0x%x", DEV_BASE(dev)->MP_ES); LOG_DBG("DMA CHx_ES 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_ES); @@ -584,13 +609,16 @@ static int dma_mcux_edma_init(const struct device *dev) struct dma_mcux_edma_data *data = dev->data; edma_config_t userConfig = { 0 }; - uint8_t i; LOG_DBG("INIT NXP EDMA"); +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT + uint8_t i; + for (i = 0; i < config->dma_channels / config->channels_per_mux; i++) { DMAMUX_Init(DEV_DMAMUX_BASE(dev, i)); } +#endif EDMA_GetDefaultConfig(&userConfig); EDMA_Init(DEV_BASE(dev), &userConfig); @@ -654,9 +682,6 @@ static int dma_mcux_edma_init(const struct device *dev) LOG_DBG("install irq done"); \ } -#define DMA_MCUX_EDMA_MUX(idx, n) \ - (DMAMUX_Type *)DT_INST_REG_ADDR_BY_IDX(n, UTIL_INC(idx)) - #if DMA_MCUX_HAS_CHANNEL_GAP #define DMA_MCUX_EDMA_CHANNEL_GAP(n) \ .channel_gap = DT_INST_PROP_OR(n, channel_gap, \ @@ -665,21 +690,37 @@ static int dma_mcux_edma_init(const struct device *dev) #define DMA_MCUX_EDMA_CHANNEL_GAP(n) #endif +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT +#define DMA_MCUX_EDMA_MUX(idx, n) \ + (DMAMUX_Type *)DT_INST_REG_ADDR_BY_IDX(n, UTIL_INC(idx)) + +#define DMAMUX_BASE_INIT_DEFINE(n) \ + static DMAMUX_Type *dmamux_base_##n[] = { \ + LISTIFY(UTIL_DEC(DT_NUM_REGS(DT_DRV_INST(n))), \ + DMA_MCUX_EDMA_MUX, (,), n) \ + }; + +#define DMAMUX_BASE_INIT(n) .dmamux_base = &dmamux_base_##n[0], +#define CHANNELS_PER_MUX(n) .channels_per_mux = DT_INST_PROP(n, dma_channels) / \ + ARRAY_SIZE(dmamux_base_##n), + +#else +#define DMAMUX_BASE_INIT_DEFINE(n) +#define DMAMUX_BASE_INIT(n) +#define CHANNELS_PER_MUX(n) +#endif + /* * define the dma */ #define DMA_INIT(n) \ + DMAMUX_BASE_INIT_DEFINE(n) \ static void dma_imx_config_func_##n(const struct device *dev); \ - static DMAMUX_Type *dmamux_base_##n[] = { \ - LISTIFY(UTIL_DEC(DT_NUM_REGS(DT_DRV_INST(n))), \ - DMA_MCUX_EDMA_MUX, (,), n) \ - }; \ static const struct dma_mcux_edma_config dma_config_##n = { \ .base = (DMA_Type *)DT_INST_REG_ADDR(n), \ - .dmamux_base = &dmamux_base_##n[0], \ + DMAMUX_BASE_INIT(n) \ .dma_channels = DT_INST_PROP(n, dma_channels), \ - .channels_per_mux = DT_INST_PROP(n, dma_channels) / \ - ARRAY_SIZE(dmamux_base_##n), \ + CHANNELS_PER_MUX(n) \ .irq_config_func = dma_imx_config_func_##n, \ .dmamux_reg_offset = DT_INST_PROP(n, dmamux_reg_offset), \ DMA_MCUX_EDMA_CHANNEL_GAP(n) \ diff --git a/drivers/dma/dma_mcux_edma.h b/drivers/dma/dma_mcux_edma.h index 019d1ed4d95..540311cb451 100644 --- a/drivers/dma/dma_mcux_edma.h +++ b/drivers/dma/dma_mcux_edma.h @@ -1,6 +1,5 @@ /* - * Copyright (c) 2020 NXP Semiconductor INC. - * All rights reserved. + * Copyright 2020-23 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,6 +14,8 @@ #include #include "fsl_edma.h" +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT #include "fsl_dmamux.h" +#endif #endif /* DMA_MCUX_EDMA_H_*/ diff --git a/dts/bindings/dma/nxp,mcux-edma-v4.yaml b/dts/bindings/dma/nxp,mcux-edma-v4.yaml new file mode 100644 index 00000000000..440f325c612 --- /dev/null +++ b/dts/bindings/dma/nxp,mcux-edma-v4.yaml @@ -0,0 +1,14 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP MCUX EDMA version 4 controller + +compatible: "nxp,mcux-edma-v4" + +include: nxp,mcux-edma.yaml + +properties: + no-error-irq: + type: boolean + description: | + If the SoCs don't have a separate interrupt id for error IRQ. From 804cfbe21cbeb1d5fd8ba3ba37eb96583235562f Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Thu, 21 Mar 2024 09:27:47 -0500 Subject: [PATCH 1455/2402] west.yml: Pull in NXP SDK file for SPI and DMA support on MXCN947 Get the SDK files for SPI and DMA support on NXP MCXN947 Signed-off-by: Mahesh Mahadevan --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 508eca02d0b..574a96c792c 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 1a360dbcd58e9f8bc30320bc82e907c03271c5f4 + revision: 384bb4f17245a7e6b2d83149309134597f1b8a69 path: modules/hal/nxp groups: - hal From d5b58a527d50fb555246a15ba3d06fd1313ad52b Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Wed, 20 Mar 2024 17:03:27 -0500 Subject: [PATCH 1456/2402] dts: mcxn947: Add edma nodes Add the EDMA nodes. Signed-off-by: Mahesh Mahadevan --- dts/arm/nxp/nxp_mcxn94x_common.dtsi | 33 +++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi index 7207f7b8aa7..371a0876cf2 100644 --- a/dts/arm/nxp/nxp_mcxn94x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi @@ -227,6 +227,9 @@ clocks = <&syscon MCUX_FLEXCOMM1_CLK>; #address-cells = <1>; #size-cells = <0>; + /* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */ + dmas = <&edma0 0 71>, <&edma0 1 72>; + dma-names = "rx", "tx"; status = "disabled"; }; flexcomm1_lpi2c1: lpi2c@93800 { @@ -511,6 +514,36 @@ }; }; + edma0: dma-controller@80000 { + #dma-cells = <2>; + compatible = "nxp,mcux-edma-v4"; + dma-channels = <16>; + dma-requests = <120>; + + reg = <0x80000 0x1000>; + interrupts = <1 0>, <2 0>, <3 0>, <4 0>, + <5 0>, <6 0>, <7 0>, <8 0>, + <9 0>, <10 0>, <11 0>, <12 0>, + <13 0>, <14 0>, <15 0>, <16 0>; + no-error-irq; + status = "disabled"; + }; + + edma1: dma-controller@a0000 { + #dma-cells = <2>; + compatible = "nxp,mcux-edma-v4"; + dma-channels = <16>; + dma-requests = <120>; + + reg = <0xa0000 0x1000>; + interrupts = <77 0>, <78 0>, <79 0>, <80 0>, + <81 0>, <82 0>, <83 0>, <84 0>, + <85 0>, <86 0>, <87 0>, <88 0>, + <89 0>, <90 0>, <91 0>, <92 0>; + no-error-irq; + status = "disabled"; + }; + fmu: flash-controller@43000 { compatible = "nxp,iap-msf1"; reg = <0x43000 0x1000>; From 7c431dde185a11ac08e3e2064b5b43c3dd9c448e Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 17 Mar 2023 19:49:43 -0500 Subject: [PATCH 1457/2402] drivers: spi: NXP LPSPI driver sometimes uses instance number Update the driver to account for variations in the SDK driver when it uses the instance number instead of the base address. Signed-off-by: Mahesh Mahadevan --- drivers/spi/spi_mcux_lpspi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi_mcux_lpspi.c b/drivers/spi/spi_mcux_lpspi.c index a1b805d98e0..fa88565691e 100644 --- a/drivers/spi/spi_mcux_lpspi.c +++ b/drivers/spi/spi_mcux_lpspi.c @@ -163,7 +163,11 @@ static void spi_mcux_isr(const struct device *dev) struct spi_mcux_data *data = dev->data; LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); +#if CONFIG_NXP_LP_FLEXCOMM + LPSPI_MasterTransferHandleIRQ(LPSPI_GetInstance(base), &data->handle); +#else LPSPI_MasterTransferHandleIRQ(base, &data->handle); +#endif } #ifdef CONFIG_SPI_RTIO From e5ecc96b3c14f53c4a14ede9b64e9d2e34d6f75f Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Thu, 27 Jul 2023 16:14:55 -0500 Subject: [PATCH 1458/2402] dts: spi: Interrupts in NXP LPSPI is no longer a required property Some NXP SoC's have a FlexComm interface that manages the interrupts. Signed-off-by: Mahesh Mahadevan --- drivers/spi/spi_mcux_lpspi.c | 18 ++++++++++++++---- dts/bindings/spi/nxp,imx-lpspi.yaml | 3 --- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi_mcux_lpspi.c b/drivers/spi/spi_mcux_lpspi.c index fa88565691e..b29a5fb5068 100644 --- a/drivers/spi/spi_mcux_lpspi.c +++ b/drivers/spi/spi_mcux_lpspi.c @@ -900,6 +900,19 @@ static const struct spi_driver_api spi_mcux_driver_api = { #define SPI_DMA_CHANNELS(n) #endif /* CONFIG_SPI_MCUX_LPSPI_DMA */ +#define SPI_MCUX_LPSPI_MODULE_IRQ_CONNECT(n) \ + do { \ + IRQ_CONNECT(DT_INST_IRQN(n), \ + DT_INST_IRQ(n, priority), \ + spi_mcux_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + } while (false) + +#define SPI_MCUX_LPSPI_MODULE_IRQ(n) \ + IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \ + (SPI_MCUX_LPSPI_MODULE_IRQ_CONNECT(n))) + #define SPI_MCUX_LPSPI_INIT(n) \ PINCTRL_DT_INST_DEFINE(n); \ COND_CODE_1(CONFIG_SPI_RTIO, (SPI_MCUX_RTIO_DEFINE(n)), ()); \ @@ -943,10 +956,7 @@ static const struct spi_driver_api spi_mcux_driver_api = { \ static void spi_mcux_config_func_##n(const struct device *dev) \ { \ - IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ - spi_mcux_isr, DEVICE_DT_INST_GET(n), 0); \ - \ - irq_enable(DT_INST_IRQN(n)); \ + SPI_MCUX_LPSPI_MODULE_IRQ(n); \ } DT_INST_FOREACH_STATUS_OKAY(SPI_MCUX_LPSPI_INIT) diff --git a/dts/bindings/spi/nxp,imx-lpspi.yaml b/dts/bindings/spi/nxp,imx-lpspi.yaml index 16b309a0812..705ee649c5a 100644 --- a/dts/bindings/spi/nxp,imx-lpspi.yaml +++ b/dts/bindings/spi/nxp,imx-lpspi.yaml @@ -11,9 +11,6 @@ properties: reg: required: true - interrupts: - required: true - clocks: required: true From 8b7cff7d330f7605ce40d4693e7f5301a46ec168 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 1 Aug 2023 15:03:41 -0500 Subject: [PATCH 1459/2402] drivers: spi: Use the NXP Flexcomm driver for interrupt handling The Low Power Flexcomm driver manages the interrupt handling and provides an API to register interrupt callbacks. Register the NXP LPSPI interrupt handler. Signed-off-by: Mahesh Mahadevan --- drivers/spi/Kconfig.mcux_lpspi | 1 + drivers/spi/spi_mcux_lpspi.c | 27 +++++++++++++++++++++++++-- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/spi/Kconfig.mcux_lpspi b/drivers/spi/Kconfig.mcux_lpspi index bad4191fbdc..8f2e79d2807 100644 --- a/drivers/spi/Kconfig.mcux_lpspi +++ b/drivers/spi/Kconfig.mcux_lpspi @@ -9,6 +9,7 @@ config SPI_MCUX_LPSPI depends on DT_HAS_NXP_IMX_LPSPI_ENABLED depends on CLOCK_CONTROL select PINCTRL + select MFD if DT_HAS_NXP_LP_FLEXCOMM_ENABLED help Enable support for mcux spi driver. diff --git a/drivers/spi/spi_mcux_lpspi.c b/drivers/spi/spi_mcux_lpspi.c index b29a5fb5068..e946b236aff 100644 --- a/drivers/spi/spi_mcux_lpspi.c +++ b/drivers/spi/spi_mcux_lpspi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NXP + * Copyright 2018, 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,6 +10,9 @@ #include #include #include +#if CONFIG_NXP_LP_FLEXCOMM +#include +#endif #include #include #ifdef CONFIG_SPI_MCUX_LPSPI_DMA @@ -35,6 +38,9 @@ LOG_MODULE_REGISTER(spi_mcux_lpspi, CONFIG_SPI_LOG_LEVEL); struct spi_mcux_config { DEVICE_MMIO_NAMED_ROM(reg_base); +#ifdef CONFIG_NXP_LP_FLEXCOMM + const struct device *parent_dev; +#endif const struct device *clock_dev; clock_control_subsys_t clock_subsys; void (*irq_config_func)(const struct device *dev); @@ -664,7 +670,16 @@ static int spi_mcux_init(const struct device *dev) DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); +#if CONFIG_NXP_LP_FLEXCOMM + /* When using LP Flexcomm driver, register the interrupt handler + * so we receive notification from the LP Flexcomm interrupt handler. + */ + nxp_lp_flexcomm_setirqhandler(config->parent_dev, dev, + LP_FLEXCOMM_PERIPH_LPSPI, spi_mcux_isr); +#else + /* Interrupt is managed by this driver */ config->irq_config_func(dev); +#endif err = spi_context_cs_configure_all(&data->ctx); if (err < 0) { @@ -913,6 +928,13 @@ static const struct spi_driver_api spi_mcux_driver_api = { IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \ (SPI_MCUX_LPSPI_MODULE_IRQ_CONNECT(n))) +#ifdef CONFIG_NXP_LP_FLEXCOMM +#define PARENT_DEV(n) \ + .parent_dev = DEVICE_DT_GET(DT_INST_PARENT(n)), +#else +#define PARENT_DEV(n) +#endif /* CONFIG_NXP_LP_FLEXCOMM */ + #define SPI_MCUX_LPSPI_INIT(n) \ PINCTRL_DT_INST_DEFINE(n); \ COND_CODE_1(CONFIG_SPI_RTIO, (SPI_MCUX_RTIO_DEFINE(n)), ()); \ @@ -920,7 +942,8 @@ static const struct spi_driver_api spi_mcux_driver_api = { static void spi_mcux_config_func_##n(const struct device *dev); \ \ static const struct spi_mcux_config spi_mcux_config_##n = { \ - DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \ + DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \ + PARENT_DEV(n) \ .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ .clock_subsys = \ (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \ From f4bad0a49c89e3ecdd17864be2c334d2c7a2ddad Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Wed, 20 Mar 2024 22:16:46 -0500 Subject: [PATCH 1460/2402] boards: frdm_mcxn947: Add support for SPI and DMA Add support for SPI and DMA Signed-off-by: Mahesh Mahadevan --- boards/nxp/frdm_mcxn947/board.c | 5 +++++ boards/nxp/frdm_mcxn947/doc/index.rst | 4 ++++ boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi | 12 ++++++++++++ boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 5 +++++ .../nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts | 12 ++++++++++++ .../nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml | 2 ++ 6 files changed, 40 insertions(+) diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index f43964fee6e..ca9405803e9 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -94,6 +94,11 @@ static int frdm_mcxn947_init(void) /* Set AHBCLKDIV divider to value 1 */ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay) + CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u); + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); +#endif + #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay) CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u); CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index 21b24ea188d..06356a4f24e 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -59,6 +59,10 @@ The FRDM-MCXN947 board configuration supports the following hardware features: | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ | CLOCK | on-chip | clock_control | +-----------+------------+-------------------------------------+ | FLASH | on-chip | soc flash | diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi index 20da3d13273..55b8bfef585 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi @@ -7,6 +7,18 @@ #include &pinctrl { + pinmux_flexcomm1_lpspi: pinmux_flexcomm1_lpspi { + group0 { + pinmux = , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart { group0 { pinmux = , diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index b0b6304c1f6..326da06db0a 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -49,6 +49,11 @@ }; }; +&flexcomm1_lpspi1 { + pinctrl-0 = <&pinmux_flexcomm1_lpspi>; + pinctrl-names = "default"; +}; + &flexcomm4_lpuart4 { current-speed = <115200>; pinctrl-0 = <&pinmux_flexcomm4_lpuart>; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts index a22a3623c4b..271fe4ba475 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts @@ -65,6 +65,18 @@ status = "okay"; }; +&edma0 { + status = "okay"; +}; + +&flexcomm1 { + status = "okay"; +}; + +&flexcomm1_lpspi1 { + status = "okay"; +}; + &flexcomm4 { status = "okay"; }; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml index 31825f6b518..372b46ec98b 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -15,5 +15,7 @@ toolchain: - gnuarmemb - xtools supported: + - dma - gpio + - spi vendor: nxp From 384e8b6af1cdc30cbd2261142f7f78cb05aa7ff7 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Wed, 20 Mar 2024 22:27:22 -0500 Subject: [PATCH 1461/2402] tests: spi: Add support for NXP MCXN947 Add support for NXP MCXN947 Signed-off-by: Mahesh Mahadevan --- .../boards/frdm_mcxn947_mcxn947_cpu0.conf | 7 +++++++ .../boards/frdm_mcxn947_mcxn947_cpu0.overlay | 18 ++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0.conf create mode 100644 tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0.conf b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0.conf new file mode 100644 index 00000000000..5014becf5b0 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0.conf @@ -0,0 +1,7 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +CONFIG_SPI_MCUX_LPSPI_DMA=y +CONFIG_SPI_ASYNC=n diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0.overlay new file mode 100644 index 00000000000..367da28fbf1 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0.overlay @@ -0,0 +1,18 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&flexcomm1_lpspi1 { + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <500000>; + }; + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = <16000000>; + }; +}; From 58733f4682e05519c8ec99d48156d10e1cb19b26 Mon Sep 17 00:00:00 2001 From: Chauncy Liu Date: Mon, 18 Mar 2024 21:58:11 -0400 Subject: [PATCH 1462/2402] include: Avoid compiler warning about unused variables Use ARG_UNUSED on unused variable. Signed-off-by: Chauncy Liu --- include/zephyr/net/hostname.h | 2 ++ include/zephyr/net/net_context.h | 5 +++++ include/zephyr/net/net_if.h | 11 +++++++++++ 3 files changed, 18 insertions(+) diff --git a/include/zephyr/net/hostname.h b/include/zephyr/net/hostname.h index 196e9ab18e7..d9bac4393c2 100644 --- a/include/zephyr/net/hostname.h +++ b/include/zephyr/net/hostname.h @@ -103,6 +103,8 @@ int net_hostname_set_postfix(const uint8_t *hostname_postfix, static inline int net_hostname_set_postfix(const uint8_t *hostname_postfix, int postfix_len) { + ARG_UNUSED(hostname_postfix); + ARG_UNUSED(postfix_len); return -EMSGSIZE; } #endif /* CONFIG_NET_HOSTNAME_UNIQUE */ diff --git a/include/zephyr/net/net_context.h b/include/zephyr/net/net_context.h index 55548917c45..658a0767c02 100644 --- a/include/zephyr/net/net_context.h +++ b/include/zephyr/net/net_context.h @@ -888,6 +888,7 @@ static inline bool net_context_is_proxy_enabled(struct net_context *context) #else static inline bool net_context_is_proxy_enabled(struct net_context *context) { + ARG_UNUSED(context); return false; } #endif @@ -1004,6 +1005,10 @@ static inline int net_context_create_ipv6_new(struct net_context *context, const struct in6_addr *src, const struct in6_addr *dst) { + ARG_UNUSED(context); + ARG_UNUSED(pkt); + ARG_UNUSED(src); + ARG_UNUSED(dst); return -1; } #endif /* CONFIG_NET_IPV6 */ diff --git a/include/zephyr/net/net_if.h b/include/zephyr/net/net_if.h index 9d17be36d2a..98baae409a8 100644 --- a/include/zephyr/net/net_if.h +++ b/include/zephyr/net/net_if.h @@ -1788,6 +1788,10 @@ static inline void net_if_ipv6_set_base_reachable_time(struct net_if *iface, } iface->config.ip.ipv6->base_reachable_time = reachable_time; +#else + ARG_UNUSED(iface); + ARG_UNUSED(reachable_time); + #endif } @@ -1809,6 +1813,7 @@ static inline uint32_t net_if_ipv6_get_reachable_time(struct net_if *iface) return iface->config.ip.ipv6->reachable_time; #else + ARG_UNUSED(iface); return 0; #endif } @@ -1836,6 +1841,8 @@ static inline void net_if_ipv6_set_reachable_time(struct net_if_ipv6 *ipv6) } ipv6->reachable_time = net_if_ipv6_calc_reachable_time(ipv6); +#else + ARG_UNUSED(ipv6); #endif } @@ -1856,6 +1863,9 @@ static inline void net_if_ipv6_set_retrans_timer(struct net_if *iface, } iface->config.ip.ipv6->retrans_timer = retrans_timer; +#else + ARG_UNUSED(iface); + ARG_UNUSED(retrans_timer); #endif } @@ -1877,6 +1887,7 @@ static inline uint32_t net_if_ipv6_get_retrans_timer(struct net_if *iface) return iface->config.ip.ipv6->retrans_timer; #else + ARG_UNUSED(iface); return 0; #endif } From 6e6f53dc8e4705078dfdc3e2f96164b4a0457977 Mon Sep 17 00:00:00 2001 From: Kapil Bhatt Date: Tue, 30 Jan 2024 14:26:13 +0530 Subject: [PATCH 1463/2402] net: wifi: Fix disconnect reason codes The shell is printing "connected" while passing the wrong password to connect command. If the status value is 0, then only shell will print "connected." The wrong password will disconnect the connection with an unspecified reason code. If the default value of the unspecified disconnect reason code is 0, then status will print "connected." By changing the default value to WIFI_STATUS_CONN_LAST_STATUS, it will print the correct reason, like a failed request with reason code. Signed-off-by: Kapil Bhatt --- include/zephyr/net/wifi_mgmt.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h index 2bf7e3ed4bf..065852507d7 100644 --- a/include/zephyr/net/wifi_mgmt.h +++ b/include/zephyr/net/wifi_mgmt.h @@ -379,6 +379,10 @@ enum wifi_conn_status { WIFI_STATUS_CONN_TIMEOUT, /** Connection failed - AP not found */ WIFI_STATUS_CONN_AP_NOT_FOUND, + /** Last connection status */ + WIFI_STATUS_CONN_LAST_STATUS, + /** Connection disconnected status */ + WIFI_STATUS_DISCONN_FIRST_STATUS = WIFI_STATUS_CONN_LAST_STATUS, }; /** Wi-Fi disconnect reason codes. To be overlaid on top of \ref wifi_status @@ -386,7 +390,7 @@ enum wifi_conn_status { */ enum wifi_disconn_reason { /** Unspecified reason */ - WIFI_REASON_DISCONN_UNSPECIFIED = 0, + WIFI_REASON_DISCONN_UNSPECIFIED = WIFI_STATUS_DISCONN_FIRST_STATUS, /** Disconnected due to user request */ WIFI_REASON_DISCONN_USER_REQUEST, /** Disconnected due to AP leaving */ From d52a7ef31a4d7a9d8bee3f5e3c7f1200203d8826 Mon Sep 17 00:00:00 2001 From: Dominik Ermel Date: Mon, 19 Feb 2024 09:36:10 +0000 Subject: [PATCH 1464/2402] tests: subsys: settings: Increase stack size Fixes #62324 Signed-off-by: Dominik Ermel --- include/zephyr/storage/stream_flash.h | 8 +++++--- tests/subsys/settings/fcb_init/prj.conf | 1 + 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/zephyr/storage/stream_flash.h b/include/zephyr/storage/stream_flash.h index 9202d5d8cc7..d53b6414a3e 100644 --- a/include/zephyr/storage/stream_flash.h +++ b/include/zephyr/storage/stream_flash.h @@ -108,9 +108,11 @@ size_t stream_flash_bytes_written(struct stream_flash_ctx *ctx); * @param data data to write * @param len Number of bytes to write * @param flush when true this forces any buffered data to be written to flash - * A flush write should be the last write operation in a sequence of - * write operations for given context (although this is not mandatory - * if the total data size is a multiple of the buffer size). + * A write with the @p flush set to true has to be issued as the last + * write request for a given context, as it concludes write of a stream; + * there must not be issued any more write requests for given context, + * unless it is re-initialized, and such write attempts may result in the + * function returning error. * * @return non-negative on success, negative errno code on fail */ diff --git a/tests/subsys/settings/fcb_init/prj.conf b/tests/subsys/settings/fcb_init/prj.conf index 46c1ab88ff3..9652f2c467c 100644 --- a/tests/subsys/settings/fcb_init/prj.conf +++ b/tests/subsys/settings/fcb_init/prj.conf @@ -4,6 +4,7 @@ CONFIG_FLASH_PAGE_LAYOUT=y CONFIG_FLASH_MAP=y CONFIG_FCB=y +CONFIG_MAIN_STACK_SIZE=4096 CONFIG_SETTINGS=y CONFIG_SETTINGS_RUNTIME=y CONFIG_SETTINGS_FCB=y From 2faec622020ef9a9c26f773527608561df10e6e4 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Fri, 22 Mar 2024 22:35:33 +0100 Subject: [PATCH 1465/2402] boards: nxp: mr_canhubk3: add devicetree nodes for CAN LEDs Add devicetree nodes for the six red CAN LEDs present on the NXP MR-CANHUBK344 board. Signed-off-by: Henrik Brix Andersen --- boards/nxp/mr_canhubk3/doc/index.rst | 14 ++++++++++++ boards/nxp/mr_canhubk3/mr_canhubk3.dts | 30 +++++++++++++++++++++++++- 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/boards/nxp/mr_canhubk3/doc/index.rst b/boards/nxp/mr_canhubk3/doc/index.rst index 7ea37ee1b08..1368aa3a117 100644 --- a/boards/nxp/mr_canhubk3/doc/index.rst +++ b/boards/nxp/mr_canhubk3/doc/index.rst @@ -100,6 +100,20 @@ led1 / user_led1_green Green PTA27 FXIO D5 / EMIOS1 CH10 / EMIOS2 CH10 led2 / user_led1_blue Blue PTE12 FXIO D8 / EMIOS1 CH5 ======================= ===== ===== =================================== +In addition to the RGB LED, the MR-CANHUBK3 board has six red LEDs, each located +next to one of the CAN connectors: + +======================= ===== ===== =================================== +Devicetree node Color Pin Pin Functions +======================= ===== ===== =================================== +can_led0 Red PTC18 FXIO D6 / FXIO D12 / EMIOS2 CH12 +can_led1 Red PTE5 FXIO D7 / EMIOS1 CH5 / EMIOS0 CH 19 +can_led2 Red PTD20 EMIOS1 CH17 / EMIOS2 CH0 +can_led3 Red PTB24 FXIO D5 / EMIOS1 CH20 / EMIOS2 CH20 +can_led4 Red PTB26 FXIO D7 / EMIOS1 CH22 / EMIOS2 CH22 +can_led5 Red PTD31 FXIO D6 / EMIOS2 CH22 +======================= ===== ===== =================================== + The user can control the LEDs in any way. An output of ``0`` illuminates the LED. Buttons diff --git a/boards/nxp/mr_canhubk3/mr_canhubk3.dts b/boards/nxp/mr_canhubk3/mr_canhubk3.dts index d0928d50739..65292e29a27 100644 --- a/boards/nxp/mr_canhubk3/mr_canhubk3.dts +++ b/boards/nxp/mr_canhubk3/mr_canhubk3.dts @@ -60,6 +60,30 @@ gpios = <&gpioe_l 14 GPIO_ACTIVE_LOW>; label = "User RGB LED1 RED"; }; + can_led0: can_led0 { + gpios = <&gpioc_h 2 GPIO_ACTIVE_LOW>; + label = "CAN LED0"; + }; + can_led1: can_led1 { + gpios = <&gpioe_l 5 GPIO_ACTIVE_LOW>; + label = "CAN LED1"; + }; + can_led2: can_led2 { + gpios = <&gpiod_h 4 GPIO_ACTIVE_LOW>; + label = "CAN LED2"; + }; + can_led3: can_led3 { + gpios = <&gpiob_h 8 GPIO_ACTIVE_LOW>; + label = "CAN LED3"; + }; + can_led4: can_led4 { + gpios = <&gpiob_h 10 GPIO_ACTIVE_LOW>; + label = "CAN LED4"; + }; + can_led5: can_led5 { + gpios = <&gpiod_h 15 GPIO_ACTIVE_LOW>; + label = "CAN LED5"; + }; }; /* gpio-leds and pwm-leds are the same RGB LED and cannot be used at the same time. */ @@ -201,7 +225,11 @@ status = "okay"; }; -/* Enable gpio to control the CAN transceivers */ +/* Enable gpio to control the CAN transceivers and LEDs */ + +&gpiob_h { + status = "okay"; +}; &gpioc_h { status = "okay"; From 87ca079e4905c6cfc5e7aeff8a18a9fff8813e16 Mon Sep 17 00:00:00 2001 From: Peter Mitsis Date: Thu, 21 Mar 2024 15:58:10 -0400 Subject: [PATCH 1466/2402] tests: z_test_1cpu_start() makes only CPU0 active When z_test_1cpu_start() is called to ensure that only a single CPU on an SMP system is available for use in a test, this commit will ensure that that CPU is the primary CPU--CPU0. This is done because some timer drivers only have the timer interrupt processed by one CPU. A bit of a song and dance is performed to achieve this without enabling the CPU mask/affinity pinning API. If the cpuhold thread is found to be executing on CPU0, then a new copy of cpuhold thread is created. Once the new copy is executing (incidentally guaranteed to be on another CPU) then it informs the original copy and busy waits until it the original copy is switched out of CPU0. At this point, we can create the next cpuhold thread to occupy another CPU if needed. During this song and dance, it is critical that the 'copy' not pend. If it pends, we can not guarantee which CPU it will execute on when it unpends. As the cpuhold threads have the highest priority, nothing is going to cause them to execute on another CPU for as long as they do not pend. Signed-off-by: Peter Mitsis --- subsys/testsuite/ztest/src/ztest.c | 131 +++++++++++++++++++++++++---- 1 file changed, 114 insertions(+), 17 deletions(-) diff --git a/subsys/testsuite/ztest/src/ztest.c b/subsys/testsuite/ztest/src/ztest.c index f887948b755..a3eba14e616 100644 --- a/subsys/testsuite/ztest/src/ztest.c +++ b/subsys/testsuite/ztest/src/ztest.c @@ -15,6 +15,8 @@ #include +#include + #ifdef KERNEL static struct k_thread ztest_thread; #endif @@ -103,11 +105,57 @@ static int cleanup_test(struct ztest_unit_test *test) #if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1) #define MAX_NUM_CPUHOLD (CONFIG_MP_MAX_NUM_CPUS - 1) #define CPUHOLD_STACK_SZ (512 + CONFIG_TEST_EXTRA_STACK_SIZE) -static struct k_thread cpuhold_threads[MAX_NUM_CPUHOLD]; -K_KERNEL_STACK_ARRAY_DEFINE(cpuhold_stacks, MAX_NUM_CPUHOLD, CPUHOLD_STACK_SZ); + +struct cpuhold_pool_item { + struct k_thread thread; + bool used; +}; + +static struct cpuhold_pool_item cpuhold_pool_items[MAX_NUM_CPUHOLD + 1]; + +K_KERNEL_STACK_ARRAY_DEFINE(cpuhold_stacks, MAX_NUM_CPUHOLD + 1, CPUHOLD_STACK_SZ); static struct k_sem cpuhold_sem; + volatile int cpuhold_active; +volatile bool cpuhold_spawned; + +static int find_unused_thread(void) +{ + for (unsigned int i = 0; i <= MAX_NUM_CPUHOLD; i++) { + if (!cpuhold_pool_items[i].used) { + return i; + } + } + + return -1; +} + +static void mark_thread_unused(struct k_thread *thread) +{ + for (unsigned int i = 0; i <= MAX_NUM_CPUHOLD; i++) { + if (&cpuhold_pool_items[i].thread == thread) { + cpuhold_pool_items[i].used = false; + } + } +} + +static inline void wait_for_thread_to_switch_out(struct k_thread *thread) +{ + unsigned int key = arch_irq_lock(); + volatile void **shp = (void *)&thread->switch_handle; + + while (*shp == NULL) { + arch_spin_relax(); + } + /* Read barrier: don't allow any subsequent loads in the + * calling code to reorder before we saw switch_handle go + * non-null. + */ + barrier_dmem_fence_full(); + + arch_irq_unlock(key); +} /* "Holds" a CPU for use with the "1cpu" test cases. Note that we * can't use tools like the cpumask feature because we have tests that @@ -116,12 +164,58 @@ volatile int cpuhold_active; */ static void cpu_hold(void *arg1, void *arg2, void *arg3) { - ARG_UNUSED(arg1); - ARG_UNUSED(arg2); + struct k_thread *thread = arg1; + unsigned int idx = (unsigned int)(uintptr_t)arg2; + char tname[CONFIG_THREAD_MAX_NAME_LEN]; + ARG_UNUSED(arg3); - unsigned int key = arch_irq_lock(); + if (arch_proc_id() == 0) { + int i; + + i = find_unused_thread(); + + __ASSERT_NO_MSG(i != -1); + + cpuhold_spawned = false; + + cpuhold_pool_items[i].used = true; + k_thread_create(&cpuhold_pool_items[i].thread, + cpuhold_stacks[i], CPUHOLD_STACK_SZ, + cpu_hold, k_current_get(), + (void *)(uintptr_t)idx, NULL, + K_HIGHEST_THREAD_PRIO, 0, K_NO_WAIT); + + /* + * Busy-wait until we know the spawned thread is running to + * ensure it does not spawn on CPU0. + */ + + while (!cpuhold_spawned) { + k_busy_wait(1000); + } + + return; + } + + if (thread != NULL) { + cpuhold_spawned = true; + + /* Busywait until a new thread is scheduled in on CPU0 */ + + wait_for_thread_to_switch_out(thread); + + mark_thread_unused(thread); + } + + if (IS_ENABLED(CONFIG_THREAD_NAME)) { + snprintk(tname, CONFIG_THREAD_MAX_NAME_LEN, "cpuhold%02d", idx); + k_thread_name_set(k_current_get(), tname); + } + + uint32_t dt, start_ms = k_uptime_get_32(); + unsigned int key = arch_irq_lock(); k_sem_give(&cpuhold_sem); @@ -155,9 +249,9 @@ void z_impl_z_test_1cpu_start(void) { #if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1) unsigned int num_cpus = arch_num_cpus(); + int j; cpuhold_active = 1; - char tname[CONFIG_THREAD_MAX_NAME_LEN]; k_sem_init(&cpuhold_sem, 0, 999); @@ -165,13 +259,15 @@ void z_impl_z_test_1cpu_start(void) * each to signal us that it's locked and spinning. */ for (int i = 0; i < num_cpus - 1; i++) { - k_thread_create(&cpuhold_threads[i], cpuhold_stacks[i], CPUHOLD_STACK_SZ, - cpu_hold, NULL, NULL, NULL, K_HIGHEST_THREAD_PRIO, - 0, K_NO_WAIT); - if (IS_ENABLED(CONFIG_THREAD_NAME)) { - snprintk(tname, CONFIG_THREAD_MAX_NAME_LEN, "cpuhold%02d", i); - k_thread_name_set(&cpuhold_threads[i], tname); - } + j = find_unused_thread(); + + __ASSERT_NO_MSG(j != -1); + + cpuhold_pool_items[j].used = true; + k_thread_create(&cpuhold_pool_items[j].thread, + cpuhold_stacks[j], CPUHOLD_STACK_SZ, + cpu_hold, NULL, (void *)(uintptr_t)i, NULL, + K_HIGHEST_THREAD_PRIO, 0, K_NO_WAIT); k_sem_take(&cpuhold_sem, K_FOREVER); } #endif @@ -180,12 +276,13 @@ void z_impl_z_test_1cpu_start(void) void z_impl_z_test_1cpu_stop(void) { #if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1) - unsigned int num_cpus = arch_num_cpus(); - cpuhold_active = 0; - for (int i = 0; i < num_cpus - 1; i++) { - k_thread_abort(&cpuhold_threads[i]); + for (int i = 0; i <= MAX_NUM_CPUHOLD; i++) { + if (cpuhold_pool_items[i].used) { + k_thread_abort(&cpuhold_pool_items[i].thread); + cpuhold_pool_items[i].used = false; + } } #endif } From ff5780fcc70390777c6273d2148af3ac360603a3 Mon Sep 17 00:00:00 2001 From: Kamil Paszkiet Date: Thu, 21 Mar 2024 08:11:27 +0100 Subject: [PATCH 1467/2402] scripts: tests: Blackbox test expansion - coverage Adds tests related to coverage flags: --gcov-tool --coverage-platform Signed-off-by: Kamil Paszkiet --- .../tests/twister_blackbox/test_coverage.py | 99 ++++++++++++++++++- 1 file changed, 94 insertions(+), 5 deletions(-) diff --git a/scripts/tests/twister_blackbox/test_coverage.py b/scripts/tests/twister_blackbox/test_coverage.py index 798f812e599..0d5e035ecd2 100644 --- a/scripts/tests/twister_blackbox/test_coverage.py +++ b/scripts/tests/twister_blackbox/test_coverage.py @@ -13,7 +13,7 @@ import sys import json -from conftest import TEST_DATA, ZEPHYR_BASE, testsuite_filename_mock +from conftest import TEST_DATA, ZEPHYR_BASE, testsuite_filename_mock, clear_log_in_test from twisterlib.testplan import TestPlan @@ -130,6 +130,20 @@ class TestCoverage: 'Running lcov --gcov-tool' ) ] + TESTDATA_6 = [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2'), + ['qemu_x86'], + ['The specified file does not exist.', r'\[Errno 13\] Permission denied:'], + ) + ] + TESTDATA_7 = [ + ( + os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2'), + ['qemu_x86_64', 'qemu_x86'], + ['qemu_x86_64', 'qemu_x86', ['qemu_x86_64', 'qemu_x86']], + ) + ] @classmethod def setup_class(cls): @@ -147,7 +161,7 @@ def setup_class(cls): ) def test_coverage(self, capfd, test_path, test_platforms, out_path, file_name): args = ['-i','--outdir', out_path, '-T', test_path] + \ - ['--coverage', '--coverage-tool', 'gcovr'] + \ + ['--coverage', '--coverage-tool', 'gcovr'] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms ) for val in pair] @@ -175,7 +189,7 @@ def test_coverage(self, capfd, test_path, test_platforms, out_path, file_name): ) def test_enable_coverage(self, capfd, test_path, test_platforms, out_path, expected): args = ['-i','--outdir', out_path, '-T', test_path] + \ - ['--enable-coverage', '-vv'] + \ + ['--enable-coverage', '-vv'] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms ) for val in pair] @@ -207,7 +221,7 @@ def test_coverage_basedir(self, capfd, test_path, test_platforms, out_path, file os.rmdir(base_dir) os.mkdir(base_dir) args = ['--outdir', out_path,'-i', '-T', test_path] + \ - ['--coverage', '--coverage-tool', 'gcovr', '-v', '--coverage-basedir', base_dir] + \ + ['--coverage', '--coverage-tool', 'gcovr', '-v', '--coverage-basedir', base_dir] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms ) for val in pair] @@ -251,7 +265,7 @@ def test_coverage_format(self, capfd, out_path, cov_tool, file_name, cov_format) test_path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2') test_platforms = ['qemu_x86'] args = ['--outdir', out_path,'-i', '-T', test_path] + \ - ['--coverage', '--coverage-tool', cov_tool, '--coverage-formats', cov_format, '-v'] + \ + ['--coverage', '--coverage-tool', cov_tool, '--coverage-formats', cov_format, '-v'] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms ) for val in pair] @@ -298,3 +312,78 @@ def test_coverage_tool(self, capfd, caplog, test_path, test_platforms, out_path, assert str(sys_exit.value) == '0' assert re.search(expected_content, caplog.text), f'{cov_tool} line not found' + + @pytest.mark.parametrize( + 'test_path, test_platforms, expected_content', + TESTDATA_6, + ids=[ + 'missing tool' + ] + ) + def test_gcov_tool(self, capfd, test_path, test_platforms, out_path, expected_content): + args = ['--outdir', out_path, '-i', '-T', test_path] + \ + ['--coverage', '--gcov-tool', TEST_DATA, '-v'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == '1' + for line in expected_content: + result = re.search(line, err) + assert result, f'missing information in log: {line}' + + @pytest.mark.parametrize( + 'test_path, test_platforms, cov_platform', + TESTDATA_7, + ids=[ + 'coverage platform' + ] + ) + def test_coverage_platform(self, capfd, test_path, test_platforms, out_path, cov_platform): + def search_cov(): + pattern = r'TOTAL\s+(\d+)' + coverage_file_path = os.path.join(out_path, 'coverage', 'coverage.txt') + with open(coverage_file_path, 'r') as file: + data = file.read() + match = re.search(pattern, data) + if match: + total = int(match.group(1)) + return total + else: + print('Error, pattern not found') + + run = [] + for element in cov_platform: + args = ['--outdir', out_path, '-i', '-T', test_path] + \ + ['--coverage', '--coverage-formats', 'txt', '-v'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + if isinstance(element, list): + for nested_element in element: + args += ['--coverage-platform', nested_element] + else: + args += ['--coverage-platform', element] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + run += [search_cov()] + + capfd.readouterr() + clear_log_in_test() + + assert run[2] > run[0], 'Broader coverage platform selection did not result in broader coverage' + assert run[2] > run[1], 'Broader coverage platform selection did not result in broader coverage' From 3fb11e260a709cbbc54698ca01bf5adcccec82cd Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Wed, 21 Feb 2024 12:36:15 +0000 Subject: [PATCH 1468/2402] scripts: tests: Blackbox test expansion - addon Adds tests related to the addon flags: * --enable-ubsan * --enable-lsan * --enable-asan * --enable-valgrind * --allow-installed-plugin * --pytest-args * -x, --extra-args * extra test args for the binary Signed-off-by: Lukasz Mrugala --- scripts/tests/twister_blackbox/conftest.py | 1 + scripts/tests/twister_blackbox/pytest.ini | 2 + scripts/tests/twister_blackbox/test_addon.py | 339 ++++++++++++++++++ .../samples/pytest/shell/CMakeLists.txt | 8 + .../test_data/samples/pytest/shell/prj.conf | 5 + .../samples/pytest/shell/pytest/test_shell.py | 23 ++ .../test_data/samples/pytest/shell/src/main.c | 14 + .../samples/pytest/shell/test_sample.yaml | 14 + .../tests/params/dummy/CMakeLists.txt | 8 + .../test_data/tests/params/dummy/prj.conf | 1 + .../test_data/tests/params/dummy/src/main.c | 44 +++ .../tests/params/dummy/test_data.yaml | 9 + .../test_data/tests/pytest/CMakeLists.txt | 7 + .../test_data/tests/pytest/prj.conf | 2 + .../test_data/tests/pytest/pytest/conftest.py | 27 ++ .../tests/pytest/pytest/test_sample.py | 42 +++ .../test_data/tests/pytest/src/main.c | 13 + .../test_data/tests/pytest/test_data.yaml | 13 + .../test_data/tests/san/asan/CMakeLists.txt | 8 + .../test_data/tests/san/asan/prj.conf | 1 + .../test_data/tests/san/asan/src/main.c | 48 +++ .../test_data/tests/san/asan/test_data.yaml | 11 + .../test_data/tests/san/lsan/CMakeLists.txt | 8 + .../test_data/tests/san/lsan/prj.conf | 1 + .../test_data/tests/san/lsan/src/main.c | 43 +++ .../test_data/tests/san/lsan/test_data.yaml | 11 + .../test_data/tests/san/ubsan/CMakeLists.txt | 8 + .../test_data/tests/san/ubsan/prj.conf | 1 + .../test_data/tests/san/ubsan/src/main.c | 34 ++ .../test_data/tests/san/ubsan/test_data.yaml | 11 + .../test_data/tests/san/val/CMakeLists.txt | 8 + .../test_data/tests/san/val/prj.conf | 1 + .../test_data/tests/san/val/src/main.c | 36 ++ .../test_data/tests/san/val/test_data.yaml | 11 + 34 files changed, 813 insertions(+) create mode 100644 scripts/tests/twister_blackbox/pytest.ini create mode 100644 scripts/tests/twister_blackbox/test_addon.py create mode 100644 scripts/tests/twister_blackbox/test_data/samples/pytest/shell/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/samples/pytest/shell/prj.conf create mode 100755 scripts/tests/twister_blackbox/test_data/samples/pytest/shell/pytest/test_shell.py create mode 100644 scripts/tests/twister_blackbox/test_data/samples/pytest/shell/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/samples/pytest/shell/test_sample.yaml create mode 100644 scripts/tests/twister_blackbox/test_data/tests/params/dummy/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/tests/params/dummy/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/tests/params/dummy/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/tests/params/dummy/test_data.yaml create mode 100644 scripts/tests/twister_blackbox/test_data/tests/pytest/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/tests/pytest/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/tests/pytest/pytest/conftest.py create mode 100755 scripts/tests/twister_blackbox/test_data/tests/pytest/pytest/test_sample.py create mode 100644 scripts/tests/twister_blackbox/test_data/tests/pytest/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/tests/pytest/test_data.yaml create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/asan/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/asan/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/asan/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/asan/test_data.yaml create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/lsan/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/lsan/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/lsan/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/lsan/test_data.yaml create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/ubsan/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/ubsan/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/ubsan/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/ubsan/test_data.yaml create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/val/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/val/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/val/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/tests/san/val/test_data.yaml diff --git a/scripts/tests/twister_blackbox/conftest.py b/scripts/tests/twister_blackbox/conftest.py index b0b41219f8a..d856261f276 100644 --- a/scripts/tests/twister_blackbox/conftest.py +++ b/scripts/tests/twister_blackbox/conftest.py @@ -21,6 +21,7 @@ sys.path.insert(0, os.path.join(ZEPHYR_BASE, "scripts")) +sample_filename_mock = mock.PropertyMock(return_value='test_sample.yaml') testsuite_filename_mock = mock.PropertyMock(return_value='test_data.yaml') sample_filename_mock = mock.PropertyMock(return_value='test_sample.yaml') diff --git a/scripts/tests/twister_blackbox/pytest.ini b/scripts/tests/twister_blackbox/pytest.ini new file mode 100644 index 00000000000..d97cd121c92 --- /dev/null +++ b/scripts/tests/twister_blackbox/pytest.ini @@ -0,0 +1,2 @@ +[pytest] +norecursedirs = test_data *.egg .* _darcs build CVS dist node_modules venv {arch} \ No newline at end of file diff --git a/scripts/tests/twister_blackbox/test_addon.py b/scripts/tests/twister_blackbox/test_addon.py new file mode 100644 index 00000000000..9bc0d50b952 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_addon.py @@ -0,0 +1,339 @@ +#!/usr/bin/env python3 +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +""" +Blackbox tests for twister's command line functions concerning addons to normal functions +""" + +import importlib +import mock +import os +import pkg_resources +import pytest +import re +import shutil +import subprocess +import sys + +from conftest import ZEPHYR_BASE, TEST_DATA, sample_filename_mock, testsuite_filename_mock +from twisterlib.testplan import TestPlan + + +class TestAddon: + @classmethod + def setup_class(cls): + apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') + cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) + cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) + cls.twister_module = importlib.util.module_from_spec(cls.spec) + + @classmethod + def teardown_class(cls): + pass + + @pytest.mark.parametrize( + 'ubsan_flags, expected_exit_value', + [ + # No sanitiser, no problem + ([], '0'), + # Sanitiser catches a mistake, error is raised + (['--enable-ubsan'], '1') + ], + ids=['no sanitiser', 'ubsan'] + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_enable_ubsan(self, out_path, ubsan_flags, expected_exit_value): + test_platforms = ['native_sim'] + test_path = os.path.join(TEST_DATA, 'tests', 'san', 'ubsan') + args = ['-i', '--outdir', out_path, '-T', test_path] + \ + ubsan_flags + \ + [] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == expected_exit_value + + @pytest.mark.parametrize( + 'lsan_flags, expected_exit_value', + [ + # No sanitiser, no problem + ([], '0'), + # Sanitiser catches a mistake, error is raised + (['--enable-asan', '--enable-lsan'], '1') + ], + ids=['no sanitiser', 'lsan'] + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_enable_lsan(self, out_path, lsan_flags, expected_exit_value): + test_platforms = ['native_sim'] + test_path = os.path.join(TEST_DATA, 'tests', 'san', 'lsan') + args = ['-i', '--outdir', out_path, '-T', test_path] + \ + lsan_flags + \ + [] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == expected_exit_value + + @pytest.mark.parametrize( + 'asan_flags, expected_exit_value, expect_asan', + [ + # No sanitiser, no problem + # Note that on some runs it may fail, + # as the process is killed instead of ending normally. + # This is not 100% repeatable, so this test is removed for now. + # ([], '0', False), + # Sanitiser catches a mistake, error is raised + (['--enable-asan'], '1', True) + ], + ids=[ + #'no sanitiser', + 'asan' + ] + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_enable_asan(self, capfd, out_path, asan_flags, expected_exit_value, expect_asan): + test_platforms = ['native_sim'] + test_path = os.path.join(TEST_DATA, 'tests', 'san', 'asan') + args = ['-i', '--outdir', out_path, '-T', test_path] + \ + asan_flags + \ + [] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == expected_exit_value + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + asan_template = r'^==\d+==ERROR:\s+AddressSanitizer:' + assert expect_asan == bool(re.search(asan_template, err, re.MULTILINE)) + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_extra_test_args(self, capfd, out_path): + test_platforms = ['native_sim'] + test_path = os.path.join(TEST_DATA, 'tests', 'params', 'dummy') + args = ['-i', '--outdir', out_path, '-T', test_path] + \ + [] + \ + ['-vvv'] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + \ + ['--', '-list'] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + # Use of -list makes tests not run. + # Thus, the tests 'failed'. + assert str(sys_exit.value) == '1' + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + expected_test_names = [ + 'param_tests::test_assert1', + 'param_tests::test_assert2', + 'param_tests::test_assert3', + ] + assert all([testname in err for testname in expected_test_names]) + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_extra_args(self, caplog, out_path): + test_platforms = ['qemu_x86', 'frdm_k64f'] + path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2') + args = ['--outdir', out_path, '-T', path] + \ + ['--extra-args', 'USE_CCACHE=0', '--extra-args', 'DUMMY=1'] + \ + [] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == '0' + + with open(os.path.join(out_path, 'twister.log')) as f: + twister_log = f.read() + + pattern_cache = r'Calling cmake: [^\n]+ -DUSE_CCACHE=0 [^\n]+\n' + pattern_dummy = r'Calling cmake: [^\n]+ -DDUMMY=1 [^\n]+\n' + + assert ' -DUSE_CCACHE=0 ' in twister_log + res = re.search(pattern_cache, twister_log) + assert res + + assert ' -DDUMMY=1 ' in twister_log + res = re.search(pattern_dummy, twister_log) + assert res + + # This test is not side-effect free. + # It installs and uninstalls pytest-twister-harness using pip + # It uses pip to check whether that plugin is previously installed + # and reinstalls it if detected at the start of its run. + # However, it does NOT restore the original plugin, ONLY reinstalls it. + @pytest.mark.parametrize( + 'allow_flags, do_install, expected_exit_value, expected_logs', + [ + ([], True, '1', ['By default Twister should work without pytest-twister-harness' + ' plugin being installed, so please, uninstall it by' + ' `pip uninstall pytest-twister-harness` and' + ' `git clean -dxf scripts/pylib/pytest-twister-harness`.']), + (['--allow-installed-plugin'], True, '0', ['You work with installed version' + ' of pytest-twister-harness plugin.']), + ([], False, '0', []), + (['--allow-installed-plugin'], False, '0', []), + ], + ids=['installed, but not allowed', 'installed, allowed', + 'not installed, not allowed', 'not installed, but allowed'] + ) + @mock.patch.object(TestPlan, 'SAMPLE_FILENAME', sample_filename_mock) + def test_allow_installed_plugin(self, caplog, out_path, allow_flags, do_install, + expected_exit_value, expected_logs): + environment_twister_module = importlib.import_module('twisterlib.environment') + harness_twister_module = importlib.import_module('twisterlib.harness') + runner_twister_module = importlib.import_module('twisterlib.runner') + + pth_path = os.path.join(ZEPHYR_BASE, 'scripts', 'pylib', 'pytest-twister-harness') + check_installed_command = [sys.executable, '-m', 'pip', 'list'] + install_command = [sys.executable, '-m', 'pip', 'install', '--no-input', pth_path] + uninstall_command = [sys.executable, '-m', 'pip', 'uninstall', '--yes', + 'pytest-twister-harness'] + + def big_uninstall(): + pth_path = os.path.join(ZEPHYR_BASE, 'scripts', 'pylib', 'pytest-twister-harness') + + subprocess.run(uninstall_command, check=True,) + + # For our registration to work, we have to delete the installation cache + additional_cache_paths = [ + # Plugin cache + os.path.join(pth_path, 'src', 'pytest_twister_harness.egg-info'), + # Additional caches + os.path.join(pth_path, 'src', 'pytest_twister_harness', '__pycache__'), + os.path.join(pth_path, 'src', 'pytest_twister_harness', 'device', '__pycache__'), + os.path.join(pth_path, 'src', 'pytest_twister_harness', 'helpers', '__pycache__'), + os.path.join(pth_path, 'src', 'pytest_twister_harness', 'build'), + ] + + for additional_cache_path in additional_cache_paths: + if os.path.exists(additional_cache_path): + if os.path.isfile(additional_cache_path): + os.unlink(additional_cache_path) + else: + shutil.rmtree(additional_cache_path) + + # To refresh the PYTEST_PLUGIN_INSTALLED global variable + def refresh_plugin_installed_variable(): + pkg_resources._initialize_master_working_set() + importlib.reload(environment_twister_module) + importlib.reload(harness_twister_module) + importlib.reload(runner_twister_module) + + check_installed_result = subprocess.run(check_installed_command, check=True, + capture_output=True, text=True) + previously_installed = 'pytest-twister-harness' in check_installed_result.stdout + + # To ensure consistent test start + big_uninstall() + + if do_install: + subprocess.run(install_command, check=True) + + # Refresh before the test, no matter the testcase + refresh_plugin_installed_variable() + + test_platforms = ['native_sim'] + test_path = os.path.join(TEST_DATA, 'samples', 'pytest', 'shell') + args = ['-i', '--outdir', out_path, '-T', test_path] + \ + allow_flags + \ + [] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + # To ensure consistent test exit, prevent dehermetisation + if do_install: + big_uninstall() + + # To restore previously-installed plugin as well as we can + if previously_installed: + subprocess.run(install_command, check=True) + + if previously_installed or do_install: + refresh_plugin_installed_variable() + + assert str(sys_exit.value) == expected_exit_value + + assert all([log in caplog.text for log in expected_logs]) + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_pytest_args(self, out_path): + test_platforms = ['native_sim'] + test_path = os.path.join(TEST_DATA, 'tests', 'pytest') + args = ['-i', '--outdir', out_path, '-T', test_path] + \ + ['--pytest-args=--custom-pytest-arg', '--pytest-args=foo', + '--pytest-args=--cmdopt', '--pytest-args=.'] + \ + [] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + # YAML was modified so that the test will fail without command line override. + assert str(sys_exit.value) == '0' + + @pytest.mark.parametrize( + 'valgrind_flags, expected_exit_value', + [ + # No sanitiser, leak is ignored + ([], '0'), + # Sanitiser catches a mistake, error is raised + (['--enable-valgrind'], '1') + ], + ids=['no valgrind', 'valgrind'] + ) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_enable_valgrind(self, capfd, out_path, valgrind_flags, expected_exit_value): + test_platforms = ['native_sim'] + test_path = os.path.join(TEST_DATA, 'tests', 'san', 'val') + args = ['-i', '--outdir', out_path, '-T', test_path] + \ + valgrind_flags + \ + [] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + assert str(sys_exit.value) == expected_exit_value diff --git a/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/CMakeLists.txt new file mode 100644 index 00000000000..a8fae2b9931 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(shell) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/prj.conf b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/prj.conf new file mode 100644 index 00000000000..37788381065 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/prj.conf @@ -0,0 +1,5 @@ +CONFIG_PRINTK=y +CONFIG_SHELL=y +CONFIG_LOG=y +CONFIG_SHELL_BACKEND_SERIAL=y +CONFIG_KERNEL_SHELL=y diff --git a/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/pytest/test_shell.py b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/pytest/test_shell.py new file mode 100755 index 00000000000..84d16ec1e5a --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/pytest/test_shell.py @@ -0,0 +1,23 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 + +import logging + +from twister_harness import Shell + +logger = logging.getLogger(__name__) + + +def test_shell_print_help(shell: Shell): + logger.info('send "help" command') + lines = shell.exec_command('help') + assert 'Available commands:' in lines, 'expected response not found' + logger.info('response is valid') + + +def test_shell_print_version(shell: Shell): + logger.info('send "kernel version" command') + lines = shell.exec_command('kernel version') + assert any(['Zephyr version' in line for line in lines]), 'expected response not found' + logger.info('response is valid') diff --git a/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/src/main.c b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/src/main.c new file mode 100644 index 00000000000..98394897582 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/src/main.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +int main(void) +{ + /* Shell application source code is injected by applied Kconfg SHELL + * options, no more "extra" functionalities are required for exemplary + * pytest test. + */ + return 0; +} diff --git a/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/test_sample.yaml b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/test_sample.yaml new file mode 100644 index 00000000000..86b9314f444 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/test_sample.yaml @@ -0,0 +1,14 @@ +tests: + sample.pytest.shell: + filter: CONFIG_SERIAL and dt_chosen_enabled("zephyr,shell-uart") + min_ram: 40 + harness: pytest + extra_configs: + - arch:posix:CONFIG_NATIVE_UART_0_ON_STDINOUT=y + integration_platforms: + - native_sim + - qemu_cortex_m3 + tags: + - test_framework + - pytest + - shell diff --git a/scripts/tests/twister_blackbox/test_data/tests/params/dummy/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/params/dummy/CMakeLists.txt new file mode 100644 index 00000000000..635c696edf9 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/params/dummy/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(integration) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/scripts/tests/twister_blackbox/test_data/tests/params/dummy/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/params/dummy/prj.conf new file mode 100644 index 00000000000..9467c292689 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/params/dummy/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/scripts/tests/twister_blackbox/test_data/tests/params/dummy/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/params/dummy/src/main.c new file mode 100644 index 00000000000..84bff77a989 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/params/dummy/src/main.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + + +ZTEST_SUITE(param_tests, NULL, NULL, NULL, NULL, NULL); + +/** + * @brief Test Asserts + * + * This test verifies various assert macros provided by ztest. + * + */ +ZTEST(param_tests, test_assert1) +{ + zassert_true(1, "1 was false"); + zassert_false(0, "0 was true"); + zassert_is_null(NULL, "NULL was not NULL"); + zassert_not_null("foo", "\"foo\" was NULL"); + zassert_equal(1, 1, "1 was not equal to 1"); + zassert_equal_ptr(NULL, NULL, "NULL was not equal to NULL"); +} +ZTEST(param_tests, test_assert2) +{ + zassert_true(1, "1 was false"); + zassert_false(0, "0 was true"); + zassert_is_null(NULL, "NULL was not NULL"); + zassert_not_null("foo", "\"foo\" was NULL"); + zassert_equal(1, 1, "1 was not equal to 1"); + zassert_equal_ptr(NULL, NULL, "NULL was not equal to NULL"); +} +ZTEST(param_tests, test_assert3) +{ + zassert_true(1, "1 was false"); + zassert_false(0, "0 was true"); + zassert_is_null(NULL, "NULL was not NULL"); + zassert_not_null("foo", "\"foo\" was NULL"); + zassert_equal(1, 1, "1 was not equal to 1"); + zassert_equal_ptr(NULL, NULL, "NULL was not equal to NULL"); +} diff --git a/scripts/tests/twister_blackbox/test_data/tests/params/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/params/dummy/test_data.yaml new file mode 100644 index 00000000000..cc12db26ab3 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/params/dummy/test_data.yaml @@ -0,0 +1,9 @@ +tests: + params.dummy: + platform_allow: + - native_sim + - qemu_x86 + - qemu_x86_64 + integration_platforms: + - native_sim + tags: params diff --git a/scripts/tests/twister_blackbox/test_data/tests/pytest/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/pytest/CMakeLists.txt new file mode 100644 index 00000000000..b5ff04dd824 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/pytest/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(pytest_sample) + +target_sources(app PRIVATE src/main.c) diff --git a/scripts/tests/twister_blackbox/test_data/tests/pytest/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/pytest/prj.conf new file mode 100644 index 00000000000..c3e81438ced --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/pytest/prj.conf @@ -0,0 +1,2 @@ +CONFIG_ZTEST=y +CONFIG_IDLE_STACK_SIZE=4096 diff --git a/scripts/tests/twister_blackbox/test_data/tests/pytest/pytest/conftest.py b/scripts/tests/twister_blackbox/test_data/tests/pytest/pytest/conftest.py new file mode 100644 index 00000000000..75b5c585273 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/pytest/pytest/conftest.py @@ -0,0 +1,27 @@ +# Copyright (c) 2020 Intel Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +import pytest + +# add option "--cmdopt" to pytest, or it will report "unknown option" +# this option is passed from twister. +def pytest_addoption(parser): + parser.addoption( + '--cmdopt' + ) + parser.addoption( + '--custom-pytest-arg' + ) + +# define fixture to return value of option "--cmdopt", this fixture +# will be requested by other fixture of tests. +@pytest.fixture() +def cmdopt(request): + return request.config.getoption('--cmdopt') + +# define fixture to return value of option "--custom-pytest-arg", this fixture +# will be requested by other fixture of tests. +@pytest.fixture() +def custom_pytest_arg(request): + return request.config.getoption('--custom-pytest-arg') diff --git a/scripts/tests/twister_blackbox/test_data/tests/pytest/pytest/test_sample.py b/scripts/tests/twister_blackbox/test_data/tests/pytest/pytest/test_sample.py new file mode 100755 index 00000000000..33b6b8d6a6d --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/pytest/pytest/test_sample.py @@ -0,0 +1,42 @@ +# Copyright (c) 2020 Intel Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +import os +import pytest + +# fixture cmdopt defined in conftest.py, it can be requested either in +# tests or in other fixtures + +@pytest.fixture(autouse=True) +def pytest_cmdopt_handle(cmdopt): + ''' An auto fixture, all tests automatically request this fixture. + Argument "cmdopt" is a fixture defined in conftest.py, it returns + the value of an option passed by twister, this fixture export + that value to environment. + ''' + print("handle cmdopt:") + print(cmdopt) + data_path = cmdopt + os.environ['data_path'] = str(data_path) + +def test_case(cmdopt): + ''' Test cases make use of fixture cmdopt to get the value of "--cmdopt" option + passed by twister. Actually, fixture cmdopt returns a path of the directory + which holds the artifacts generated by ztest. The main work of test cases + in this file is to check those stuff in that directory. + This test case simply compare the return value of cmdopt with the + environment variable exported by fixture pytest_cmdopt_handle. + ''' + assert os.path.exists(cmdopt) + + print("run test cases in:") + print(cmdopt) + +def test_custom_arg(custom_pytest_arg): + ''' Test passing of custom command line arguments to pytest. + ''' + assert custom_pytest_arg == "foo" + +if __name__ == "__main__": + pytest.main() diff --git a/scripts/tests/twister_blackbox/test_data/tests/pytest/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/pytest/src/main.c new file mode 100644 index 00000000000..49fae9559a3 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/pytest/src/main.c @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2020 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +ZTEST_SUITE(test_pytest, NULL, NULL, NULL, NULL, NULL); + +ZTEST(test_pytest, test_pytest) +{ + TC_PRINT("Hello world\n"); +} diff --git a/scripts/tests/twister_blackbox/test_data/tests/pytest/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/pytest/test_data.yaml new file mode 100644 index 00000000000..6dc504cd64c --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/pytest/test_data.yaml @@ -0,0 +1,13 @@ +tests: + sample.twister.pytest: + platform_allow: + - native_posix + - native_sim + harness: pytest + harness_config: + pytest_args: ["--custom-pytest-arg", "foo", "--cmdopt", "."] + tags: + - test_framework + - pytest + integration_platforms: + - native_sim diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/asan/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/san/asan/CMakeLists.txt new file mode 100644 index 00000000000..635c696edf9 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/asan/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(integration) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/asan/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/san/asan/prj.conf new file mode 100644 index 00000000000..9467c292689 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/asan/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/asan/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/san/asan/src/main.c new file mode 100644 index 00000000000..aa69e1f9710 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/asan/src/main.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include + +#include + + +ZTEST_SUITE(a1_1_tests, NULL, NULL, NULL, NULL, NULL); + +int *ptr; + +int helper(void) +{ + char *s = malloc(10); + + strcpy(s, "123456789"); + s[9] = '0'; + free(s); + strcpy(s, "Hello"); + printf("string is: %s\n", s); + + return 0; +} + +/** + * @brief Test Asserts + * + * This test verifies various assert macros provided by ztest. + * + */ +ZTEST(a1_1_tests, test_assert) +{ + helper(); + + zassert_true(1, "1 was false"); + zassert_false(0, "0 was true"); + zassert_is_null(NULL, "NULL was not NULL"); + zassert_not_null("foo", "\"foo\" was NULL"); + zassert_equal(1, 1, "1 was not equal to 1"); + zassert_equal_ptr(NULL, NULL, "NULL was not equal to NULL"); +} diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/asan/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/san/asan/test_data.yaml new file mode 100644 index 00000000000..47d2d4b2387 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/asan/test_data.yaml @@ -0,0 +1,11 @@ +tests: + san.asan: + platform_allow: + - native_sim + - qemu_x86 + - qemu_x86_64 + integration_platforms: + - native_sim + tags: + - agnostic + - subgrouped diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/lsan/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/san/lsan/CMakeLists.txt new file mode 100644 index 00000000000..635c696edf9 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/lsan/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(integration) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/lsan/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/san/lsan/prj.conf new file mode 100644 index 00000000000..9467c292689 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/lsan/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/lsan/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/san/lsan/src/main.c new file mode 100644 index 00000000000..a3f63d309a2 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/lsan/src/main.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include + +#include + + +ZTEST_SUITE(a1_1_tests, NULL, NULL, NULL, NULL, NULL); + +int helper(void) +{ + char *s = malloc(100); + + s[0] = '!'; + s[1] = '\0'; + printf("string is: %s\n", s); + return 0; +} + +/** + * @brief Test Asserts + * + * This test verifies various assert macros provided by ztest. + * + */ +ZTEST(a1_1_tests, test_assert) +{ + helper(); + + zassert_true(1, "1 was false"); + zassert_false(0, "0 was true"); + zassert_is_null(NULL, "NULL was not NULL"); + zassert_not_null("foo", "\"foo\" was NULL"); + zassert_equal(1, 1, "1 was not equal to 1"); + zassert_equal_ptr(NULL, NULL, "NULL was not equal to NULL"); +} diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/lsan/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/san/lsan/test_data.yaml new file mode 100644 index 00000000000..01d6978a5ce --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/lsan/test_data.yaml @@ -0,0 +1,11 @@ +tests: + san.lsan: + platform_allow: + - native_sim + - qemu_x86 + - qemu_x86_64 + integration_platforms: + - native_sim + tags: + - agnostic + - subgrouped diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/CMakeLists.txt new file mode 100644 index 00000000000..635c696edf9 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(integration) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/prj.conf new file mode 100644 index 00000000000..9467c292689 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/src/main.c new file mode 100644 index 00000000000..b81e0799750 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/src/main.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2023 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include + +#include + + +ZTEST_SUITE(a1_1_tests, NULL, NULL, NULL, NULL, NULL); + +/** + * @brief Test Asserts + * + * This test verifies various assert macros provided by ztest. + * + */ +ZTEST(a1_1_tests, test_assert) +{ + int k = INT_MAX; + + k += 256; + printf("num is: %d\n", k); + + zassert_true(1, "1 was false"); + zassert_false(0, "0 was true"); + zassert_is_null(NULL, "NULL was not NULL"); + zassert_not_null("foo", "\"foo\" was NULL"); + zassert_equal(1, 1, "1 was not equal to 1"); + zassert_equal_ptr(NULL, NULL, "NULL was not equal to NULL"); +} diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/test_data.yaml new file mode 100644 index 00000000000..f4efff55c4b --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/ubsan/test_data.yaml @@ -0,0 +1,11 @@ +tests: + san.ubsan: + platform_allow: + - native_sim + - qemu_x86 + - qemu_x86_64 + integration_platforms: + - native_sim + tags: + - agnostic + - subgrouped diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/val/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/san/val/CMakeLists.txt new file mode 100644 index 00000000000..635c696edf9 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/val/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(integration) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/val/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/san/val/prj.conf new file mode 100644 index 00000000000..9467c292689 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/val/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/val/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/san/val/src/main.c new file mode 100644 index 00000000000..38ee6f7c1bf --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/val/src/main.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include + +#include + + +ZTEST_SUITE(a1_1_tests, NULL, NULL, NULL, NULL, NULL); + +/** + * @brief Test Asserts + * + * This test verifies various assert macros provided by ztest. + * + */ +ZTEST(a1_1_tests, test_assert) +{ + char *s = malloc(10); + + strcpy(s, "123456789"); + printf("string is: %s\n", s); + + zassert_true(1, "1 was false"); + zassert_false(0, "0 was true"); + zassert_is_null(NULL, "NULL was not NULL"); + zassert_not_null("foo", "\"foo\" was NULL"); + zassert_equal(1, 1, "1 was not equal to 1"); + zassert_equal_ptr(NULL, NULL, "NULL was not equal to NULL"); +} diff --git a/scripts/tests/twister_blackbox/test_data/tests/san/val/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/san/val/test_data.yaml new file mode 100644 index 00000000000..0c2027624cc --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/san/val/test_data.yaml @@ -0,0 +1,11 @@ +tests: + san.valgrind: + platform_allow: + - native_sim + - qemu_x86 + - qemu_x86_64 + integration_platforms: + - native_sim + tags: + - agnostic + - subgrouped From 0c7325e3ef955af08321fa2a561a5132525da834 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Fri, 22 Mar 2024 17:41:18 -0500 Subject: [PATCH 1469/2402] doc: board_porting: Update hierarchy presentation Update the presentation of the hardware hierarchy description so that it does not appear to have missing words at the end of the bullet points, by using a paragraph instead. And tweak the wording slightly. Signed-off-by: Declan Snyder --- doc/hardware/porting/board_porting.rst | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/doc/hardware/porting/board_porting.rst b/doc/hardware/porting/board_porting.rst index 0008ef91340..d7ff4569524 100644 --- a/doc/hardware/porting/board_porting.rst +++ b/doc/hardware/porting/board_porting.rst @@ -70,16 +70,10 @@ complete conversion reference. Hardware support hierarchy ************************** -Zephyr's hardware support hierarchy has the following levels, from most to least -specific: - -- :term:`board`, which has one or more -- :term:`SoC`, each of which optionally belong to a -- :term:`SoC series`, which in turn may optionally belong to an -- :term:`SoC family`. Each SoC has one or more -- :term:`CPU cluster`, each containing one or more -- :term:`CPU core`, of a particular -- :term:`architecture` +Zephyr's hardware support is based on a series of hierarchical abstractions. +Primarily, each :term:`board` has one or more :term:`SoC`. +Each SoC can be optionally classed into an :term:`SoC series`, which in turn may optionally belong to an :term:`SoC family`. +Each SoC has one or more :term:`CPU cluster`, each containing one or more :term:`CPU core` of a particular :term:`architecture`. You can visualize the hierarchy in the diagram below: From 9b2312d05579ae8e03f808079c43787f68dbe106 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 22 Mar 2024 02:08:10 +0100 Subject: [PATCH 1470/2402] net: buf: Fix cloning of zero-sized buffers For zero sized buffers, instead of pointing to a buffer, net_buf->__buf is NULL. For this reason, when cloning a buffer, the code needs to check __buf before dereferencing it. Signed-off-by: Reto Schneider --- subsys/net/buf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/buf.c b/subsys/net/buf.c index 1101a2b0adb..9b04e243642 100644 --- a/subsys/net/buf.c +++ b/subsys/net/buf.c @@ -519,7 +519,7 @@ struct net_buf *net_buf_clone(struct net_buf *buf, k_timeout_t timeout) * we need to allocate new data and make a copy. */ if (pool->alloc->cb->ref && !(buf->flags & NET_BUF_EXTERNAL_DATA)) { - clone->__buf = data_ref(buf, buf->__buf); + clone->__buf = buf->__buf ? data_ref(buf, buf->__buf) : NULL; clone->data = buf->data; clone->len = buf->len; clone->size = buf->size; From a924c87dc27ba5e701e16c9bc597e0a0a76431e5 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Mon, 25 Mar 2024 15:35:40 +0100 Subject: [PATCH 1471/2402] tests: net: buf: Test zero-sized clone This commit ensures that copying a zero-sized buffer works. Signed-off-by: Reto Schneider --- tests/net/buf/src/main.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tests/net/buf/src/main.c b/tests/net/buf/src/main.c index 5d2cb451c16..24f0b27a3cd 100644 --- a/tests/net/buf/src/main.c +++ b/tests/net/buf/src/main.c @@ -452,6 +452,21 @@ ZTEST(net_buf_tests, test_net_buf_clone_no_ref_count) zassert_equal(destroy_called, 2, "Incorrect destroy callback count"); } +/* Regression test: Zero sized buffers must be copy-able, not trigger a NULL pointer dereference */ +ZTEST(net_buf_tests, test_net_buf_clone_reference_counted_zero_sized_buffer) +{ + struct net_buf *buf, *clone; + + buf = net_buf_alloc_len(&var_pool, 0, K_NO_WAIT); + zassert_not_null(buf, "Failed to get buffer"); + + clone = net_buf_clone(buf, K_NO_WAIT); + zassert_not_null(clone, "Failed to clone zero sized buffer"); + + net_buf_unref(buf); + net_buf_unref(clone); +} + ZTEST(net_buf_tests, test_net_buf_fixed_pool) { struct net_buf *buf; From 321e395a8f4e79ea74b305c248c2f5aec96a4202 Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Thu, 21 Mar 2024 15:50:13 -0700 Subject: [PATCH 1472/2402] linker: Include libkernel.a in the whole-archive when llext is enabled Differently from other libraries, which are included whole in the final Zephyr ELF, libkernel.a itself isn't. Assuming this is intended to enable optimisations (if it isn't, this patch will break things) - linker can remove parts of the kernel that are not used by the application. However, when considering Linkable Loadable Extensions (llext), this optimisations can be counterproductive: for instance, syscalls that are not used by the application won't be available for extensions. It won't matter if someone "EXPORT_SYMBOL" for them, or even try to keep them using LINKER_KEEP, they'll be gone. To avoid that, this patches includes, when CONFIG_LLEXT=y, libkernel.a inside the linker "whole-archive" block. This ends up making it consider libkernel.a as a library whose all symbols should be kept. Note this doesn't mean that all symbols will be there - things compiled out via Kconfig will naturally still be out. Signed-off-by: Ederson de Souza --- CMakeLists.txt | 7 +++++++ cmake/linker/arcmwdt/target.cmake | 4 ++-- cmake/linker/ld/target.cmake | 4 ++-- cmake/linker/lld/target.cmake | 4 ++-- cmake/linker/xt-ld/target.cmake | 4 ++-- kernel/CMakeLists.txt | 2 +- 6 files changed, 16 insertions(+), 9 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6c44e41c810..d8f2801d011 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -876,6 +876,13 @@ foreach(zephyr_lib ${ZEPHYR_LIBS_PROPERTY}) add_dependencies(${zephyr_lib} zephyr_generated_headers) endforeach() +if(CONFIG_LLEXT) + set(WHOLE_ARCHIVE_LIBS ${ZEPHYR_LIBS_PROPERTY} kernel) +else() + set(WHOLE_ARCHIVE_LIBS ${ZEPHYR_LIBS_PROPERTY}) + set(NO_WHOLE_ARCHIVE_LIBS kernel) +endif() + get_property(OUTPUT_FORMAT GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT) if (CONFIG_CODE_DATA_RELOCATION) diff --git a/cmake/linker/arcmwdt/target.cmake b/cmake/linker/arcmwdt/target.cmake index 067c2dc286e..f2247ba4540 100644 --- a/cmake/linker/arcmwdt/target.cmake +++ b/cmake/linker/arcmwdt/target.cmake @@ -97,9 +97,9 @@ function(toolchain_ld_link_elf) ${LINKERFLAGPREFIX}--entry=__start ${LINKERFLAGPREFIX}--Map=${TOOLCHAIN_LD_LINK_ELF_OUTPUT_MAP} ${LINKERFLAGPREFIX}--whole-archive - ${ZEPHYR_LIBS_PROPERTY} + ${WHOLE_ARCHIVE_LIBS} ${LINKERFLAGPREFIX}--no-whole-archive - kernel + ${NO_WHOLE_ARCHIVE_LIBS} $ ${LIB_INCLUDE_DIR} -L${PROJECT_BINARY_DIR} diff --git a/cmake/linker/ld/target.cmake b/cmake/linker/ld/target.cmake index b57f8902044..2d60e8ea63d 100644 --- a/cmake/linker/ld/target.cmake +++ b/cmake/linker/ld/target.cmake @@ -134,9 +134,9 @@ function(toolchain_ld_link_elf) ${LINKERFLAGPREFIX},-Map=${TOOLCHAIN_LD_LINK_ELF_OUTPUT_MAP} ${LINKERFLAGPREFIX},--whole-archive - ${ZEPHYR_LIBS_PROPERTY} + ${WHOLE_ARCHIVE_LIBS} ${LINKERFLAGPREFIX},--no-whole-archive - kernel + ${NO_WHOLE_ARCHIVE_LIBS} $ ${LIB_INCLUDE_DIR} -L${PROJECT_BINARY_DIR} diff --git a/cmake/linker/lld/target.cmake b/cmake/linker/lld/target.cmake index f71a217e5be..5deab047100 100644 --- a/cmake/linker/lld/target.cmake +++ b/cmake/linker/lld/target.cmake @@ -94,9 +94,9 @@ function(toolchain_ld_link_elf) ${LINKERFLAGPREFIX},-Map=${TOOLCHAIN_LD_LINK_ELF_OUTPUT_MAP} ${LINKERFLAGPREFIX},--whole-archive - ${ZEPHYR_LIBS_PROPERTY} + ${WHOLE_ARCHIVE_LIBS} ${LINKERFLAGPREFIX},--no-whole-archive - kernel + ${NO_WHOLE_ARCHIVE_LIBS} $ ${LIB_INCLUDE_DIR} -L${PROJECT_BINARY_DIR} diff --git a/cmake/linker/xt-ld/target.cmake b/cmake/linker/xt-ld/target.cmake index 426bced0a61..20209107ff7 100644 --- a/cmake/linker/xt-ld/target.cmake +++ b/cmake/linker/xt-ld/target.cmake @@ -126,9 +126,9 @@ function(toolchain_ld_link_elf) ${LINKERFLAGPREFIX},-Map=${TOOLCHAIN_LD_LINK_ELF_OUTPUT_MAP} ${LINKERFLAGPREFIX},--whole-archive - ${ZEPHYR_LIBS_PROPERTY} + ${WHOLE_ARCHIVE_LIBS} ${LINKERFLAGPREFIX},--no-whole-archive - kernel + ${NO_WHOLE_ARCHIVE_LIBS} $ ${LIB_INCLUDE_DIR} -L${PROJECT_BINARY_DIR} diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt index 6d40e13d09d..1883b45a138 100644 --- a/kernel/CMakeLists.txt +++ b/kernel/CMakeLists.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 # kernel is a normal CMake library and not a zephyr_library because it -# should not be --whole-archive'd +# should usually not be --whole-archive'd zephyr_syscall_header( ${ZEPHYR_BASE}/include/zephyr/device.h From 62b19ef65c0be6186ed9f07343c8242abf651e6c Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Thu, 21 Mar 2024 15:51:15 -0700 Subject: [PATCH 1473/2402] syscalls: llext: Export z_impl symbols so they are available to kernel commit 67bb6db3f8e5 ("syscall: Export all emitted syscalls, enabling them for extensions") exports all emitted syscalls, however, it does that only for the `z_mrsh` symbols, effectively only available for userspace. If an extension running at kernel level tries to use a syscall, it will fail to load. This patch fixes that by exposing the `z_impl` symbols instead. However, this is not as straightforward as the `z_mrsh` ones. As, in their signatures, they can basically contain any type, it's not just a matter of emitting `EXPORT_SYMBOL(z_impl_)`, as the compiler will complain about the undefined types. Here, there are a few approaches. One of them is to have the `EXPORT_SYMBOL` being generated on the same files where the syscall is implemented - injecting it there would allow it to access all known symbols. But changing a lot of files is undesirable, and it was one of the nice points of first patch. Another one would be to reconstruct - or simply use the absolute path - for the includes where the syscalls are defined. Reconstruct the paths seems fragile and I'm not sure using absolute paths is portable. Finally, the approach used in this patch is to declare, on a different generated file, all `z_impl_` symbols as `void *` - after all, only the address (and the name) to the function is relevant to EXPORT_SYMBOL. By living in an compilation unit that doesn't include any header which would expose any of the syscalls, there shouldn't be any conflicts. And to account for the possibility that a syscall is not compiled - due being configured out via Kconfig - all those symbols are also weak aliases to a pointer to NULL. This file is then included in `llext_export.c` (which should naturally not include any conflicting header). Signed-off-by: Ederson de Souza --- CMakeLists.txt | 1 + scripts/build/gen_syscalls.py | 35 ++++++++++++++++++++++++++++------- subsys/llext/llext_export.c | 2 ++ 3 files changed, 31 insertions(+), 7 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index d8f2801d011..2d802277a68 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -759,6 +759,7 @@ add_custom_command(OUTPUT include/generated/syscall_dispatch.c ${syscall_list_h} --json-file ${syscalls_json} # Read this file --base-output include/generated/syscalls # Write to this dir --syscall-dispatch include/generated/syscall_dispatch.c # Write this file + --syscall-export-llext include/generated/syscall_export_llext.c --syscall-list ${syscall_list_h} $<$:--gen-mrsh-files> ${SYSCALL_LONG_REGISTERS_ARG} diff --git a/scripts/build/gen_syscalls.py b/scripts/build/gen_syscalls.py index 3741707f803..8755f3c649a 100755 --- a/scripts/build/gen_syscalls.py +++ b/scripts/build/gen_syscalls.py @@ -62,8 +62,6 @@ const _k_syscall_handler_t _k_syscall_table[K_SYSCALL_LIMIT] = { \t%s }; -/* Export syscalls for extensions */ -%s """ list_template = """/* auto-generated by gen_syscalls.py, don't edit */ @@ -159,6 +157,20 @@ #endif """ + +exported_template = """ +/* Export syscalls for extensions */ +static void * const no_handler = NULL; + +/* Weak references, if something is not found by the linker, it will be NULL + * and simply fail during extension load + */ +%s + +/* Exported symbols */ +%s +""" + typename_regex = re.compile(r'(.*?)([A-Za-z0-9_]+)$') @@ -410,6 +422,8 @@ def parse_args(): help="Indicates we are on system with 64-bit registers") parser.add_argument("--gen-mrsh-files", action="store_true", help="Generate marshalling files (*_mrsh.c)") + parser.add_argument("-e", "--syscall-export-llext", + help="output C system call export for extensions") args = parser.parse_args() @@ -431,6 +445,7 @@ def main(): table_entries = [] handlers = [] emit_list = [] + exported = [] for match_group, fn, to_emit in syscalls: handler, inv, mrsh, sys_id, entry = analyze_fn(match_group, fn) @@ -445,6 +460,7 @@ def main(): ids_emit.append(sys_id) table_entries.append(entry) emit_list.append(handler) + exported.append(handler.replace("z_mrsh_", "z_impl_")) else: ids_not_emit.append(sys_id) @@ -464,12 +480,17 @@ def main(): weak_defines += "\n".join(["extern uintptr_t %s(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, uintptr_t arg4, uintptr_t arg5, uintptr_t arg6, void *ssf);" % s for s in noweak]) - # Export symbols for emitted syscalls - exported_symbols = "\n".join("EXPORT_SYMBOL(%s);" % e for e in emit_list) - fp.write(table_template % (weak_defines, - ",\n\t".join(table_entries), - exported_symbols)) + ",\n\t".join(table_entries))) + + if args.syscall_export_llext: + with open(args.syscall_export_llext, "w") as fp: + # Export symbols for emitted syscalls + weak_refs = "\n".join("extern __weak ALIAS_OF(no_handler) void * const %s;" + % e for e in exported) + exported_symbols = "\n".join("EXPORT_SYMBOL(%s);" + % e for e in exported) + fp.write(exported_template % (weak_refs, exported_symbols)) # Listing header emitted to stdout ids_emit.sort() diff --git a/subsys/llext/llext_export.c b/subsys/llext/llext_export.c index 0ec7fe4ac0a..e5b5aa441ab 100644 --- a/subsys/llext/llext_export.c +++ b/subsys/llext/llext_export.c @@ -15,3 +15,5 @@ EXPORT_SYMBOL(strncmp); EXPORT_SYMBOL(memcmp); EXPORT_SYMBOL(memcpy); EXPORT_SYMBOL(memset); + +#include From 8a2262431fb5724c8c1ed3ad6aeb8041f080daa1 Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Fri, 22 Mar 2024 16:47:58 -0700 Subject: [PATCH 1474/2402] arch/arm/core: Export `z_arm_thread_is_in_user_mode` for extensions This call is used by syscalls machinery, and needs to be available for extensions that use syscalls on ARM. Signed-off-by: Ederson de Souza --- arch/arm/core/cortex_a_r/thread.c | 3 ++- arch/arm/core/cortex_m/thread.c | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/core/cortex_a_r/thread.c b/arch/arm/core/cortex_a_r/thread.c index 9d57563f6bd..e134fa76053 100644 --- a/arch/arm/core/cortex_a_r/thread.c +++ b/arch/arm/core/cortex_a_r/thread.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -247,7 +248,7 @@ bool z_arm_thread_is_in_user_mode(void) value = __get_CPSR(); return ((value & CPSR_M_Msk) == CPSR_M_USR); } - +EXPORT_SYMBOL(z_arm_thread_is_in_user_mode); #endif #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE) diff --git a/arch/arm/core/cortex_m/thread.c b/arch/arm/core/cortex_m/thread.c index 0ada94e8b27..1eb8df924b7 100644 --- a/arch/arm/core/cortex_m/thread.c +++ b/arch/arm/core/cortex_m/thread.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -277,6 +278,7 @@ bool z_arm_thread_is_in_user_mode(void) value = __get_CONTROL(); return (value & CONTROL_nPRIV_Msk) != 0; } +EXPORT_SYMBOL(z_arm_thread_is_in_user_mode); #endif #if defined(CONFIG_BUILTIN_STACK_GUARD) From df916387f1a5e6593527003e21105b338fc2c364 Mon Sep 17 00:00:00 2001 From: Ederson de Souza Date: Fri, 22 Mar 2024 16:47:49 -0700 Subject: [PATCH 1475/2402] tests/subsys/llext: Add syscall tests Check if syscalls can be accessed from both kernel and userspace, and if optimised away ones indeed point to NULL. Signed-off-by: Ederson de Souza --- tests/subsys/llext/simple/CMakeLists.txt | 2 +- tests/subsys/llext/simple/prj.conf | 2 ++ tests/subsys/llext/simple/src/syscalls_ext.c | 23 +++++++++++++ tests/subsys/llext/simple/src/syscalls_ext.h | 19 +++++++++++ .../llext/simple/src/test_llext_simple.c | 32 +++++++++++++++++++ 5 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 tests/subsys/llext/simple/src/syscalls_ext.c create mode 100644 tests/subsys/llext/simple/src/syscalls_ext.h diff --git a/tests/subsys/llext/simple/CMakeLists.txt b/tests/subsys/llext/simple/CMakeLists.txt index 87a71554ba4..e2618136b0a 100644 --- a/tests/subsys/llext/simple/CMakeLists.txt +++ b/tests/subsys/llext/simple/CMakeLists.txt @@ -17,7 +17,7 @@ target_include_directories(app PRIVATE if(NOT LOADER_BUILD_ONLY) # generate extension targets foreach extension given by name -foreach(ext_name hello_world logging relative_jump object) +foreach(ext_name hello_world logging relative_jump object syscalls) set(ext_src ${PROJECT_SOURCE_DIR}/src/${ext_name}_ext.c) set(ext_bin ${ZEPHYR_BINARY_DIR}/${ext_name}.llext) set(ext_inc ${ZEPHYR_BINARY_DIR}/include/generated/${ext_name}.inc) diff --git a/tests/subsys/llext/simple/prj.conf b/tests/subsys/llext/simple/prj.conf index c7ce0544764..2105b798cab 100644 --- a/tests/subsys/llext/simple/prj.conf +++ b/tests/subsys/llext/simple/prj.conf @@ -4,3 +4,5 @@ CONFIG_LOG=y CONFIG_LLEXT=y CONFIG_LLEXT_HEAP_SIZE=16 CONFIG_LLEXT_LOG_LEVEL_DBG=y + +CONFIG_APPLICATION_DEFINED_SYSCALL=y diff --git a/tests/subsys/llext/simple/src/syscalls_ext.c b/tests/subsys/llext/simple/src/syscalls_ext.c new file mode 100644 index 00000000000..9089bfec17e --- /dev/null +++ b/tests/subsys/llext/simple/src/syscalls_ext.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This code demonstrates syscall support. + */ + +#include +#include + +#include "syscalls_ext.h" + +void test_entry(void) +{ + int input = 41; + + printk("Input: %d Expected output: %d Actual output: %d\n", + input, input + 1, ext_syscall_ok(input)); +} +LL_EXTENSION_SYMBOL(test_entry); diff --git a/tests/subsys/llext/simple/src/syscalls_ext.h b/tests/subsys/llext/simple/src/syscalls_ext.h new file mode 100644 index 00000000000..4d1b7fd43d9 --- /dev/null +++ b/tests/subsys/llext/simple/src/syscalls_ext.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +__syscall int ext_syscall_ok(int a); + +/* + * This is a syscall that is intentionally not implemented. The build + * syscall machinery will still pick it up and generate a stub for it, + * that should be optmised away. For extensions, the symbol will end up + * pointing to NULL. This is tested in the test_ext_syscall_fail test. + */ +__syscall void ext_syscall_fail(void); + +#include diff --git a/tests/subsys/llext/simple/src/test_llext_simple.c b/tests/subsys/llext/simple/src/test_llext_simple.c index 3d64afdfc17..33f4b694ba9 100644 --- a/tests/subsys/llext/simple/src/test_llext_simple.c +++ b/tests/subsys/llext/simple/src/test_llext_simple.c @@ -11,6 +11,8 @@ #include #include +#include "syscalls_ext.h" + LOG_MODULE_REGISTER(test_llext_simple); @@ -43,6 +45,19 @@ void llext_entry(void *arg0, void *arg1, void *arg2) } #endif /* CONFIG_USERSPACE */ +int z_impl_ext_syscall_ok(int a) +{ + return a + 1; +} + +#ifdef CONFIG_USERSPACE +static inline int z_vrfy_ext_syscall_ok(int a) +{ + return z_impl_ext_syscall_ok(a); +} +#include +#endif /* CONFIG_USERSPACE */ + void load_call_unload(struct llext_test *test_case) { struct llext_buf_loader buf_loader = @@ -158,6 +173,11 @@ static LLEXT_CONST uint8_t object_ext[] __aligned(4) = { #include "object.inc" }; LLEXT_LOAD_UNLOAD(object, true) + +static LLEXT_CONST uint8_t syscalls_ext[] __aligned(4) = { + #include "syscalls.inc" +}; +LLEXT_LOAD_UNLOAD(syscalls, true) #endif /* ! LOADER_BUILD_ONLY */ /* @@ -171,5 +191,17 @@ ZTEST(llext, test_printk_exported) zassert_equal(printk_fn, printk, "printk should be an exported symbol"); } +/* + * Ensure ext_syscall_fail is exported - as it is picked up by the syscall + * build machinery - but points to NULL as it is not implemented. + */ +ZTEST(llext, test_ext_syscall_fail) +{ + const void * const esf_fn = llext_find_sym(NULL, + "z_impl_ext_syscall_fail"); + + zassert_is_null(*(uintptr_t **)esf_fn, NULL, + "ext_syscall_fail should be NULL"); +} ZTEST_SUITE(llext, NULL, NULL, NULL, NULL, NULL); From f45b48fc513e1f84c48fdadc80bf4c7e78762365 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Wed, 13 Mar 2024 17:59:58 +0100 Subject: [PATCH 1476/2402] sys: byteorder: Add 40 bit variants This adds sys_*_*40 functions that operation on a 40 bits values. Signed-off-by: Reto Schneider --- include/zephyr/sys/byteorder.h | 72 +++++++++++++++++++++++++++++ tests/kernel/common/src/byteorder.c | 69 +++++++++++++++++++++++++++ 2 files changed, 141 insertions(+) diff --git a/include/zephyr/sys/byteorder.h b/include/zephyr/sys/byteorder.h index d1f839f5188..2b987dd14fe 100644 --- a/include/zephyr/sys/byteorder.h +++ b/include/zephyr/sys/byteorder.h @@ -24,6 +24,11 @@ (((x) >> 8) & 0xff00) | \ (((x) & 0xff00) << 8) | \ (((x) & 0xff) << 24))) +#define BSWAP_40(x) ((uint64_t) ((((x) >> 32) & 0xff) | \ + (((x) >> 16) & 0xff00) | \ + (((x)) & 0xff0000) | \ + (((x) & 0xff00) << 16) | \ + (((x) & 0xff) << 32))) #define BSWAP_48(x) ((uint64_t) ((((x) >> 40) & 0xff) | \ (((x) >> 24) & 0xff00) | \ (((x) >> 8) & 0xff0000) | \ @@ -217,6 +222,8 @@ #define sys_cpu_to_le24(val) (val) #define sys_le32_to_cpu(val) (val) #define sys_cpu_to_le32(val) (val) +#define sys_le40_to_cpu(val) (val) +#define sys_cpu_to_le40(val) (val) #define sys_le48_to_cpu(val) (val) #define sys_cpu_to_le48(val) (val) #define sys_le64_to_cpu(val) (val) @@ -227,6 +234,8 @@ #define sys_cpu_to_be24(val) BSWAP_24(val) #define sys_be32_to_cpu(val) BSWAP_32(val) #define sys_cpu_to_be32(val) BSWAP_32(val) +#define sys_be40_to_cpu(val) BSWAP_40(val) +#define sys_cpu_to_be40(val) BSWAP_40(val) #define sys_be48_to_cpu(val) BSWAP_48(val) #define sys_cpu_to_be48(val) BSWAP_48(val) #define sys_be64_to_cpu(val) BSWAP_64(val) @@ -259,6 +268,8 @@ #define sys_cpu_to_le24(val) BSWAP_24(val) #define sys_le32_to_cpu(val) BSWAP_32(val) #define sys_cpu_to_le32(val) BSWAP_32(val) +#define sys_le40_to_cpu(val) BSWAP_40(val) +#define sys_cpu_to_le40(val) BSWAP_40(val) #define sys_le48_to_cpu(val) BSWAP_48(val) #define sys_cpu_to_le48(val) BSWAP_48(val) #define sys_le64_to_cpu(val) BSWAP_64(val) @@ -269,6 +280,8 @@ #define sys_cpu_to_be24(val) (val) #define sys_be32_to_cpu(val) (val) #define sys_cpu_to_be32(val) (val) +#define sys_be40_to_cpu(val) (val) +#define sys_cpu_to_be40(val) (val) #define sys_be48_to_cpu(val) (val) #define sys_cpu_to_be48(val) (val) #define sys_be64_to_cpu(val) (val) @@ -340,6 +353,20 @@ static inline void sys_put_be32(uint32_t val, uint8_t dst[4]) sys_put_be16(val >> 16, dst); sys_put_be16(val, &dst[2]); } +/** + * @brief Put a 40-bit integer as big-endian to arbitrary location. + * + * Put a 40-bit integer, originally in host endianness, to a + * potentially unaligned memory location in big-endian format. + * + * @param val 40-bit integer in host endianness. + * @param dst Destination memory address to store the result. + */ +static inline void sys_put_be40(uint64_t val, uint8_t dst[5]) +{ + dst[0] = val >> 32; + sys_put_be32(val, &dst[1]); +} /** * @brief Put a 48-bit integer as big-endian to arbitrary location. @@ -416,6 +443,21 @@ static inline void sys_put_le32(uint32_t val, uint8_t dst[4]) sys_put_le16(val >> 16, &dst[2]); } +/** + * @brief Put a 40-bit integer as little-endian to arbitrary location. + * + * Put a 40-bit integer, originally in host endianness, to a + * potentially unaligned memory location in little-endian format. + * + * @param val 40-bit integer in host endianness. + * @param dst Destination memory address to store the result. + */ +static inline void sys_put_le40(uint64_t val, uint8_t dst[5]) +{ + sys_put_le32(val, dst); + dst[4] = val >> 32; +} + /** * @brief Put a 48-bit integer as little-endian to arbitrary location. * @@ -491,6 +533,21 @@ static inline uint32_t sys_get_be32(const uint8_t src[4]) return ((uint32_t)sys_get_be16(&src[0]) << 16) | sys_get_be16(&src[2]); } +/** + * @brief Get a 40-bit integer stored in big-endian format. + * + * Get a 40-bit integer, stored in big-endian format in a potentially + * unaligned memory location, and convert it to the host endianness. + * + * @param src Location of the big-endian 40-bit integer to get. + * + * @return 40-bit integer in host endianness. + */ +static inline uint64_t sys_get_be40(const uint8_t src[5]) +{ + return ((uint64_t)sys_get_be32(&src[0]) << 8) | src[4]; +} + /** * @brief Get a 48-bit integer stored in big-endian format. * @@ -566,6 +623,21 @@ static inline uint32_t sys_get_le32(const uint8_t src[4]) return ((uint32_t)sys_get_le16(&src[2]) << 16) | sys_get_le16(&src[0]); } +/** + * @brief Get a 40-bit integer stored in little-endian format. + * + * Get a 40-bit integer, stored in little-endian format in a potentially + * unaligned memory location, and convert it to the host endianness. + * + * @param src Location of the little-endian 40-bit integer to get. + * + * @return 40-bit integer in host endianness. + */ +static inline uint64_t sys_get_le40(const uint8_t src[5]) +{ + return ((uint64_t)sys_get_le32(&src[1]) << 8) | src[0]; +} + /** * @brief Get a 48-bit integer stored in little-endian format. * diff --git a/tests/kernel/common/src/byteorder.c b/tests/kernel/common/src/byteorder.c index 8fcda358a7f..a16a25df7ec 100644 --- a/tests/kernel/common/src/byteorder.c +++ b/tests/kernel/common/src/byteorder.c @@ -106,6 +106,40 @@ ZTEST(byteorder, test_sys_put_be64) zassert_mem_equal(tmp, buf, sizeof(uint64_t), "sys_put_be64() failed"); } +/** + * @brief Test sys_get_be40() functionality + * + * @details Test if sys_get_be40() correctly handles endianness. + * + * @see sys_get_be40() + */ +ZTEST(byteorder, test_sys_get_be40) +{ + uint64_t val = 0xf0e1d2c3b4, tmp; + uint8_t buf[] = {0xf0, 0xe1, 0xd2, 0xc3, 0xb4}; + + tmp = sys_get_be40(buf); + + zassert_equal(tmp, val, "sys_get_be64() failed"); +} + +/** + * @brief Test sys_put_be40() functionality + * + * @details Test if sys_put_be40() correctly handles endianness. + * + * @see sys_put_be40() + */ +ZTEST(byteorder, test_sys_put_be40) +{ + uint64_t val = 0xf0e1d2c3b4; + uint8_t buf[] = {0xf0, 0xe1, 0xd2, 0xc3, 0xb4}; + uint8_t tmp[sizeof(buf)]; + + sys_put_be40(val, tmp); + zassert_mem_equal(tmp, buf, sizeof(buf), "sys_put_be40() failed"); +} + /** * @brief Test sys_get_be48() functionality * @@ -378,6 +412,41 @@ ZTEST(byteorder, test_sys_put_le32) zassert_mem_equal(tmp, buf, sizeof(uint32_t), "sys_put_le32() failed"); } +/** + * @brief Test sys_get_le40() functionality + * + * @details Test if sys_get_le40() correctly handles endianness. + * + * @see sys_get_le40() + */ +ZTEST(byteorder, test_sys_get_le40) +{ + uint64_t val = 0xf0e1d2c3b4, tmp; + uint8_t buf[] = {0xb4, 0xc3, 0xd2, 0xe1, 0xf0}; + + tmp = sys_get_le40(buf); + + zassert_equal(tmp, val, "sys_get_le40() failed"); +} + +/** + * @brief Test sys_put_le40() functionality + * + * @details Test if sys_put_le40() correctly handles endianness. + * + * @see sys_put_le40() + */ +ZTEST(byteorder, test_sys_put_le40) +{ + uint64_t val = 0xf0e1d2c3b4; + uint8_t buf[] = {0xb4, 0xc3, 0xd2, 0xe1, 0xf0}; + uint8_t tmp[sizeof(uint64_t)]; + + sys_put_le40(val, tmp); + + zassert_mem_equal(tmp, buf, sizeof(buf), "sys_put_le40() failed"); +} + /** * @brief Test sys_get_le48() functionality * From 8918247f37bbb8c5d917b8d28cb6dec4861b971e Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Wed, 13 Mar 2024 17:07:28 +0100 Subject: [PATCH 1477/2402] net: buf_simple: Add support for 40 bit data type This enables pulling and pushing values in 40 bit format. Signed-off-by: Reto Schneider --- include/zephyr/net/buf.h | 94 +++++++++++++++++++++++++++++++++ subsys/net/buf_simple.c | 78 +++++++++++++++++++++++++++ tests/net/buf_simple/src/main.c | 73 +++++++++++++++++++++++++ 3 files changed, 245 insertions(+) diff --git a/include/zephyr/net/buf.h b/include/zephyr/net/buf.h index 18ff833a38c..21de2cdf15e 100644 --- a/include/zephyr/net/buf.h +++ b/include/zephyr/net/buf.h @@ -299,6 +299,30 @@ void net_buf_simple_add_le32(struct net_buf_simple *buf, uint32_t val); */ void net_buf_simple_add_be32(struct net_buf_simple *buf, uint32_t val); +/** + * @brief Add 40-bit value at the end of the buffer + * + * Adds 40-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 40-bit value to be added. + */ +void net_buf_simple_add_le40(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Add 40-bit value at the end of the buffer + * + * Adds 40-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 40-bit value to be added. + */ +void net_buf_simple_add_be40(struct net_buf_simple *buf, uint64_t val); + /** * @brief Add 48-bit value at the end of the buffer * @@ -443,6 +467,30 @@ uint32_t net_buf_simple_remove_le32(struct net_buf_simple *buf); */ uint32_t net_buf_simple_remove_be32(struct net_buf_simple *buf); +/** + * @brief Remove and convert 40 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 40-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from little endian to host endian. + */ +uint64_t net_buf_simple_remove_le40(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 40 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 40-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from big endian to host endian. + */ +uint64_t net_buf_simple_remove_be40(struct net_buf_simple *buf); + /** * @brief Remove and convert 48 bits from the end of the buffer. * @@ -595,6 +643,28 @@ void net_buf_simple_push_le32(struct net_buf_simple *buf, uint32_t val); */ void net_buf_simple_push_be32(struct net_buf_simple *buf, uint32_t val); +/** + * @brief Push 40-bit value to the beginning of the buffer + * + * Adds 40-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 40-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_le40(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Push 40-bit value to the beginning of the buffer + * + * Adds 40-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 40-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_be40(struct net_buf_simple *buf, uint64_t val); + /** * @brief Push 48-bit value to the beginning of the buffer * @@ -749,6 +819,30 @@ uint32_t net_buf_simple_pull_le32(struct net_buf_simple *buf); */ uint32_t net_buf_simple_pull_be32(struct net_buf_simple *buf); +/** + * @brief Remove and convert 40 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 40-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from little endian to host endian. + */ +uint64_t net_buf_simple_pull_le40(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 40 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 40-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from big endian to host endian. + */ +uint64_t net_buf_simple_pull_be40(struct net_buf_simple *buf); + /** * @brief Remove and convert 48 bits from the beginning of the buffer. * diff --git a/subsys/net/buf_simple.c b/subsys/net/buf_simple.c index 8937a636156..3e9db256e88 100644 --- a/subsys/net/buf_simple.c +++ b/subsys/net/buf_simple.c @@ -127,6 +127,20 @@ void net_buf_simple_add_be32(struct net_buf_simple *buf, uint32_t val) sys_put_be32(val, net_buf_simple_add(buf, sizeof(val))); } +void net_buf_simple_add_le40(struct net_buf_simple *buf, uint64_t val) +{ + NET_BUF_SIMPLE_DBG("buf %p val %" PRIu64, buf, val); + + sys_put_le40(val, net_buf_simple_add(buf, 5)); +} + +void net_buf_simple_add_be40(struct net_buf_simple *buf, uint64_t val) +{ + NET_BUF_SIMPLE_DBG("buf %p val %" PRIu64, buf, val); + + sys_put_be40(val, net_buf_simple_add(buf, 5)); +} + void net_buf_simple_add_le48(struct net_buf_simple *buf, uint64_t val) { NET_BUF_SIMPLE_DBG("buf %p val %" PRIu64, buf, val); @@ -246,6 +260,32 @@ uint32_t net_buf_simple_remove_be32(struct net_buf_simple *buf) return sys_be32_to_cpu(val); } +uint64_t net_buf_simple_remove_le40(struct net_buf_simple *buf) +{ + struct uint40 { + uint64_t u40: 40; + } __packed val; + void *ptr; + + ptr = net_buf_simple_remove_mem(buf, sizeof(val)); + val = UNALIGNED_GET((struct uint40 *)ptr); + + return sys_le40_to_cpu(val.u40); +} + +uint64_t net_buf_simple_remove_be40(struct net_buf_simple *buf) +{ + struct uint40 { + uint64_t u40: 40; + } __packed val; + void *ptr; + + ptr = net_buf_simple_remove_mem(buf, sizeof(val)); + val = UNALIGNED_GET((struct uint40 *)ptr); + + return sys_be40_to_cpu(val.u40); +} + uint64_t net_buf_simple_remove_le48(struct net_buf_simple *buf) { struct uint48 { @@ -362,6 +402,20 @@ void net_buf_simple_push_be32(struct net_buf_simple *buf, uint32_t val) sys_put_be32(val, net_buf_simple_push(buf, sizeof(val))); } +void net_buf_simple_push_le40(struct net_buf_simple *buf, uint64_t val) +{ + NET_BUF_SIMPLE_DBG("buf %p val %" PRIu64, buf, val); + + sys_put_le40(val, net_buf_simple_push(buf, 5)); +} + +void net_buf_simple_push_be40(struct net_buf_simple *buf, uint64_t val) +{ + NET_BUF_SIMPLE_DBG("buf %p val %" PRIu64, buf, val); + + sys_put_be40(val, net_buf_simple_push(buf, 5)); +} + void net_buf_simple_push_le48(struct net_buf_simple *buf, uint64_t val) { NET_BUF_SIMPLE_DBG("buf %p val %" PRIu64, buf, val); @@ -488,6 +542,30 @@ uint32_t net_buf_simple_pull_be32(struct net_buf_simple *buf) return sys_be32_to_cpu(val); } +uint64_t net_buf_simple_pull_le40(struct net_buf_simple *buf) +{ + struct uint40 { + uint64_t u40: 40; + } __packed val; + + val = UNALIGNED_GET((struct uint40 *)buf->data); + net_buf_simple_pull(buf, sizeof(val)); + + return sys_le40_to_cpu(val.u40); +} + +uint64_t net_buf_simple_pull_be40(struct net_buf_simple *buf) +{ + struct uint40 { + uint64_t u40: 40; + } __packed val; + + val = UNALIGNED_GET((struct uint40 *)buf->data); + net_buf_simple_pull(buf, sizeof(val)); + + return sys_be40_to_cpu(val.u40); +} + uint64_t net_buf_simple_pull_le48(struct net_buf_simple *buf) { struct uint48 { diff --git a/tests/net/buf_simple/src/main.c b/tests/net/buf_simple/src/main.c index def63b38aae..de5edd4dfe8 100644 --- a/tests/net/buf_simple/src/main.c +++ b/tests/net/buf_simple/src/main.c @@ -18,6 +18,8 @@ static const uint8_t le24[3] = { 0x03, 0x02, 0x01 }; static const uint8_t be24[3] = { 0x01, 0x02, 0x03 }; static const uint8_t le32[4] = { 0x04, 0x03, 0x02, 0x01 }; static const uint8_t be32[4] = { 0x01, 0x02, 0x03, 0x04 }; +static const uint8_t le40[5] = { 0x05, 0x04, 0x03, 0x02, 0x01 }; +static const uint8_t be40[5] = { 0x01, 0x02, 0x03, 0x04, 0x05 }; static const uint8_t le48[6] = { 0x06, 0x05, 0x04, 0x03, 0x02, 0x01 }; static const uint8_t be48[6] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06 }; static const uint8_t le64[8] = { 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01 }; @@ -25,6 +27,7 @@ static const uint8_t be64[8] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 static const uint16_t u16 = 0x0102; static const uint32_t u24 = 0x010203; static const uint32_t u32 = 0x01020304; +static const uint64_t u40 = 0x0102030405; static const uint64_t u48 = 0x010203040506; static const uint64_t u64 = 0x0102030405060708; @@ -141,6 +144,38 @@ ZTEST(net_buf_simple_test_suite, test_net_buf_simple_add_be32) sizeof(be32), "Invalid 32 bits byte order"); } +ZTEST(net_buf_simple_test_suite, test_net_buf_simple_pull_le40) +{ + net_buf_simple_add_mem(&buf, &le40, sizeof(le40)); + + zassert_equal(u40, net_buf_simple_pull_le40(&buf), + "Invalid 40 bits byte order"); +} + +ZTEST(net_buf_simple_test_suite, test_net_buf_simple_pull_be40) +{ + net_buf_simple_add_mem(&buf, &be40, sizeof(be40)); + + zassert_equal(u40, net_buf_simple_pull_be40(&buf), + "Invalid 40 bits byte order"); +} + +ZTEST(net_buf_simple_test_suite, test_net_buf_simple_add_le40) +{ + net_buf_simple_add_le40(&buf, u40); + + zassert_mem_equal(le40, net_buf_simple_pull_mem(&buf, sizeof(le40)), + sizeof(le40), "Invalid 40 bits byte order"); +} + +ZTEST(net_buf_simple_test_suite, test_net_buf_simple_add_be40) +{ + net_buf_simple_add_be40(&buf, u40); + + zassert_mem_equal(be40, net_buf_simple_pull_mem(&buf, sizeof(be40)), + sizeof(be40), "Invalid 40 bits byte order"); +} + ZTEST(net_buf_simple_test_suite, test_net_buf_simple_pull_le48) { net_buf_simple_add_mem(&buf, &le48, sizeof(le48)); @@ -325,6 +360,44 @@ ZTEST(net_buf_simple_test_suite, test_net_buf_simple_push_be32) sizeof(be32), "Invalid 32 bits byte order"); } +ZTEST(net_buf_simple_test_suite, test_net_buf_simple_remove_le40) +{ + net_buf_simple_reserve(&buf, 16); + + net_buf_simple_push_mem(&buf, &le40, sizeof(le40)); + + zassert_equal(u40, net_buf_simple_remove_le40(&buf), "Invalid 40 bits byte order"); +} + +ZTEST(net_buf_simple_test_suite, test_net_buf_simple_remove_be40) +{ + net_buf_simple_reserve(&buf, 16); + + net_buf_simple_push_mem(&buf, &be40, sizeof(be40)); + + zassert_equal(u40, net_buf_simple_remove_be40(&buf), "Invalid 40 bits byte order"); +} + +ZTEST(net_buf_simple_test_suite, test_net_buf_simple_push_le40) +{ + net_buf_simple_reserve(&buf, 16); + + net_buf_simple_push_le40(&buf, u40); + + zassert_mem_equal(le40, net_buf_simple_remove_mem(&buf, sizeof(le40)), sizeof(le40), + "Invalid 40 bits byte order"); +} + +ZTEST(net_buf_simple_test_suite, test_net_buf_simple_push_be40) +{ + net_buf_simple_reserve(&buf, 16); + + net_buf_simple_push_be40(&buf, u40); + + zassert_mem_equal(be40, net_buf_simple_remove_mem(&buf, sizeof(be40)), sizeof(be40), + "Invalid 40 bits byte order"); +} + ZTEST(net_buf_simple_test_suite, test_net_buf_simple_remove_le48) { net_buf_simple_reserve(&buf, 16); From ddb075c398e44d98c226a419aecb58618c77da21 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Wed, 13 Mar 2024 18:05:06 +0100 Subject: [PATCH 1478/2402] net: buf: Add support for 40 bit data type This enables pulling and pushing values in 40 bit format. Signed-off-by: Reto Schneider --- include/zephyr/net/buf.h | 118 +++++++++++++++++++++++++++++++++++++++ tests/net/buf/src/main.c | 40 +++++++++++++ 2 files changed, 158 insertions(+) diff --git a/include/zephyr/net/buf.h b/include/zephyr/net/buf.h index 21de2cdf15e..464dfc6ccd7 100644 --- a/include/zephyr/net/buf.h +++ b/include/zephyr/net/buf.h @@ -1725,6 +1725,36 @@ static inline void net_buf_add_be32(struct net_buf *buf, uint32_t val) net_buf_simple_add_be32(&buf->b, val); } +/** + * @brief Add 40-bit value at the end of the buffer + * + * Adds 40-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 40-bit value to be added. + */ +static inline void net_buf_add_le40(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_add_le40(&buf->b, val); +} + +/** + * @brief Add 40-bit value at the end of the buffer + * + * Adds 40-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 40-bit value to be added. + */ +static inline void net_buf_add_be40(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_add_be40(&buf->b, val); +} + /** * @brief Add 48-bit value at the end of the buffer * @@ -1905,6 +1935,36 @@ static inline uint32_t net_buf_remove_be32(struct net_buf *buf) return net_buf_simple_remove_be32(&buf->b); } +/** + * @brief Remove and convert 40 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 40-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from little endian to host endian. + */ +static inline uint64_t net_buf_remove_le40(struct net_buf *buf) +{ + return net_buf_simple_remove_le40(&buf->b); +} + +/** + * @brief Remove and convert 40 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 40-bit big endian data. + * + * @param buf A valid pointer on a buffer + * + * @return 40-bit value converted from big endian to host endian. + */ +static inline uint64_t net_buf_remove_be40(struct net_buf *buf) +{ + return net_buf_simple_remove_be40(&buf->b); +} + /** * @brief Remove and convert 48 bits from the end of the buffer. * @@ -2096,6 +2156,34 @@ static inline void net_buf_push_be32(struct net_buf *buf, uint32_t val) net_buf_simple_push_be32(&buf->b, val); } +/** + * @brief Push 40-bit value to the beginning of the buffer + * + * Adds 40-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 40-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_le40(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_push_le40(&buf->b, val); +} + +/** + * @brief Push 40-bit value to the beginning of the buffer + * + * Adds 40-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 40-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_be40(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_push_be40(&buf->b, val); +} + /** * @brief Push 48-bit value to the beginning of the buffer * @@ -2289,6 +2377,36 @@ static inline uint32_t net_buf_pull_be32(struct net_buf *buf) return net_buf_simple_pull_be32(&buf->b); } +/** + * @brief Remove and convert 40 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 40-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from little endian to host endian. + */ +static inline uint64_t net_buf_pull_le40(struct net_buf *buf) +{ + return net_buf_simple_pull_le40(&buf->b); +} + +/** + * @brief Remove and convert 40 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 40-bit big endian data. + * + * @param buf A valid pointer on a buffer + * + * @return 40-bit value converted from big endian to host endian. + */ +static inline uint64_t net_buf_pull_be40(struct net_buf *buf) +{ + return net_buf_simple_pull_be40(&buf->b); +} + /** * @brief Remove and convert 48 bits from the beginning of the buffer. * diff --git a/tests/net/buf/src/main.c b/tests/net/buf/src/main.c index 24f0b27a3cd..f211000dd12 100644 --- a/tests/net/buf/src/main.c +++ b/tests/net/buf/src/main.c @@ -519,6 +519,8 @@ ZTEST(net_buf_tests, test_net_buf_byte_order) uint8_t be24[3] = { 0x01, 0x02, 0x03 }; uint8_t le32[4] = { 0x04, 0x03, 0x02, 0x01 }; uint8_t be32[4] = { 0x01, 0x02, 0x03, 0x04 }; + uint8_t le40[5] = { 0x05, 0x04, 0x03, 0x02, 0x01 }; + uint8_t be40[5] = { 0x01, 0x02, 0x03, 0x04, 0x05 }; uint8_t le48[6] = { 0x06, 0x05, 0x04, 0x03, 0x02, 0x01 }; uint8_t be48[6] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06 }; uint8_t le64[8] = { 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01 }; @@ -588,6 +590,24 @@ ZTEST(net_buf_tests, test_net_buf_byte_order) net_buf_reset(buf); + net_buf_add_mem(buf, &le40, sizeof(le40)); + net_buf_add_mem(buf, &be40, sizeof(be40)); + + u64 = net_buf_pull_le40(buf); + zassert_equal(u64, net_buf_pull_be40(buf), "Invalid 40 bits byte order"); + + net_buf_reset(buf); + + net_buf_add_le40(buf, u64); + net_buf_add_be40(buf, u64); + + zassert_mem_equal(le40, net_buf_pull_mem(buf, sizeof(le40)), sizeof(le40), + "Invalid 40 bits byte order"); + zassert_mem_equal(be40, net_buf_pull_mem(buf, sizeof(be40)), sizeof(be40), + "Invalid 40 bits byte order"); + + net_buf_reset(buf); + net_buf_add_mem(buf, &le48, sizeof(le48)); net_buf_add_mem(buf, &be48, sizeof(be48)); @@ -691,6 +711,26 @@ ZTEST(net_buf_tests, test_net_buf_byte_order) net_buf_reset(buf); net_buf_reserve(buf, 16); + net_buf_push_mem(buf, &le40, sizeof(le40)); + net_buf_push_mem(buf, &be40, sizeof(be40)); + + u64 = net_buf_remove_le40(buf); + zassert_equal(u64, net_buf_remove_be40(buf), "Invalid 40 bits byte order"); + + net_buf_reset(buf); + net_buf_reserve(buf, 16); + + net_buf_push_le40(buf, u64); + net_buf_push_be40(buf, u64); + + zassert_mem_equal(le40, net_buf_remove_mem(buf, sizeof(le40)), sizeof(le40), + "Invalid 40 bits byte order"); + zassert_mem_equal(be40, net_buf_remove_mem(buf, sizeof(be40)), sizeof(be40), + "Invalid 40 bits byte order"); + + net_buf_reset(buf); + net_buf_reserve(buf, 16); + net_buf_push_mem(buf, &le48, sizeof(le48)); net_buf_push_mem(buf, &be48, sizeof(be48)); From dd0923d7ad8ac1bac39bcbb55418ebb678591991 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Sun, 24 Mar 2024 12:37:35 +0100 Subject: [PATCH 1479/2402] boards: nxp: mr_canhubk3: add ssd1306 display devicetree node Add devicetree node for the accompanying, ssd1306-based display board connected to connector P4. Signed-off-by: Henrik Brix Andersen --- boards/nxp/mr_canhubk3/doc/index.rst | 2 ++ boards/nxp/mr_canhubk3/mr_canhubk3.dts | 17 +++++++++++++++++ boards/nxp/mr_canhubk3/mr_canhubk3.yaml | 1 + 3 files changed, 20 insertions(+) diff --git a/boards/nxp/mr_canhubk3/doc/index.rst b/boards/nxp/mr_canhubk3/doc/index.rst index 1368aa3a117..f398e170857 100644 --- a/boards/nxp/mr_canhubk3/doc/index.rst +++ b/boards/nxp/mr_canhubk3/doc/index.rst @@ -228,6 +228,8 @@ P4.3 PTD14 LPI2C0_SCL P4.4 PTD13 LPI2C0_SDA ========= ===== ============ +The accompanying display board can be connected to ``lpi2c0`` via connector ``P4``. + ADC === diff --git a/boards/nxp/mr_canhubk3/mr_canhubk3.dts b/boards/nxp/mr_canhubk3/mr_canhubk3.dts index 65292e29a27..65f6c86d569 100644 --- a/boards/nxp/mr_canhubk3/mr_canhubk3.dts +++ b/boards/nxp/mr_canhubk3/mr_canhubk3.dts @@ -27,6 +27,7 @@ zephyr,shell-uart = &lpuart2; zephyr,flash-controller = &mx25l6433f; zephyr,canbus = &flexcan0; + zephyr,display = &ssd1306; }; aliases { @@ -406,6 +407,22 @@ pinctrl-0 = <&lpi2c0_default>; pinctrl-names = "default"; clock-frequency = ; + status = "okay"; + + ssd1306: ssd1306@3c { + compatible = "solomon,ssd1306fb"; + reg = <0x3c>; + width = <128>; + height = <32>; + segment-offset = <0>; + page-offset = <0>; + display-offset = <0>; + multiplex-ratio = <31>; + segment-remap; + com-invdir; + com-sequential; + prechargep = <0x22>; + }; }; &lpi2c1 { diff --git a/boards/nxp/mr_canhubk3/mr_canhubk3.yaml b/boards/nxp/mr_canhubk3/mr_canhubk3.yaml index 227498e16a7..010db5cdf3c 100644 --- a/boards/nxp/mr_canhubk3/mr_canhubk3.yaml +++ b/boards/nxp/mr_canhubk3/mr_canhubk3.yaml @@ -20,4 +20,5 @@ supported: - netif:eth - pwm - dma + - display vendor: nxp From 8000c7073fecd30f2be515c201d93143bd890d16 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 22 Mar 2024 09:13:20 +0100 Subject: [PATCH 1480/2402] boards native_posix_64: Remove hwmv1 compatible board definition To use this functionality one must now use the native_posix//64 (variant) version. The old hwmv1 compatible name for the board was left provisionally while all tests in tree were ported. That being now done, this old name can be removed. After this change one cannot build anymore targeting native_posix_64, but must instead build targeting native_posix/[native]/64. For twister tests the old name is already not valid. Signed-off-by: Alberto Escolar Piedras --- boards/deprecated.cmake | 5 +++++ boards/native/native_posix/Kconfig | 12 ------------ boards/native/native_posix/Kconfig.native_posix_64 | 5 ----- boards/native/native_posix/board.yml | 8 -------- boards/native/native_posix/native_posix_64.dts | 8 -------- boards/native/native_posix/native_posix_64_defconfig | 4 ---- 6 files changed, 5 insertions(+), 37 deletions(-) delete mode 100644 boards/native/native_posix/Kconfig.native_posix_64 delete mode 100644 boards/native/native_posix/native_posix_64.dts delete mode 100644 boards/native/native_posix/native_posix_64_defconfig diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 20e11bead5b..0d1d0d35d6d 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -404,6 +404,11 @@ set(mps3_an547_DEPRECATED set(mps3_an547_ns_DEPRECATED mps3/an547/ns ) + +set(native_posix_64_DEPRECATED + native_posix/native/64 +) + set(nrf21540dk_nrf52840_DEPRECATED nrf21540dk ) diff --git a/boards/native/native_posix/Kconfig b/boards/native/native_posix/Kconfig index eee6cd26b03..b629778f4cb 100644 --- a/boards/native/native_posix/Kconfig +++ b/boards/native/native_posix/Kconfig @@ -14,18 +14,6 @@ config BOARD_NATIVE_POSIX An interrupt controller, timer (system tick), and redirects kernel prints to stdout. -config BOARD_NATIVE_POSIX_64 - bool - select BOARD_NATIVE_POSIX - select 64BIT - help - Native POSIX - 64 bit version - Will produce a console Linux process which can be executed natively - as a 64-bit executable. - It provides some minimal needed models: - An interrupt controller, timer (system tick), and redirects kernel prints to - stdout. - if BOARD_NATIVE_POSIX comment "Native POSIX options" diff --git a/boards/native/native_posix/Kconfig.native_posix_64 b/boards/native/native_posix/Kconfig.native_posix_64 deleted file mode 100644 index 8151a520910..00000000000 --- a/boards/native/native_posix/Kconfig.native_posix_64 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_POSIX_64 - select SOC_POSIX diff --git a/boards/native/native_posix/board.yml b/boards/native/native_posix/board.yml index 8ab212aa1f9..0f03465c79b 100644 --- a/boards/native/native_posix/board.yml +++ b/boards/native/native_posix/board.yml @@ -5,11 +5,3 @@ boards: - name: native variants: - name: "64" - -# This board definition below, together with its respective -# Kconfig.native_posix_64 exist for backwards compatibility with the hwmv1 board name -# Once all its usage in tree is removed, or an alias has been introduced they can be removed. -- name: native_posix_64 - vendor: zephyr - socs: - - name: native diff --git a/boards/native/native_posix/native_posix_64.dts b/boards/native/native_posix/native_posix_64.dts deleted file mode 100644 index 61c2a62acc5..00000000000 --- a/boards/native/native_posix/native_posix_64.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2019 BayLibre SAS - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include "native_posix.dts" diff --git a/boards/native/native_posix/native_posix_64_defconfig b/boards/native/native_posix/native_posix_64_defconfig deleted file mode 100644 index b0033eda61f..00000000000 --- a/boards/native/native_posix/native_posix_64_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 From d8b3efcbb0b734b2ed9749a4fcabe381db2ca4a6 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 22 Mar 2024 09:22:33 +0100 Subject: [PATCH 1481/2402] boards native_sim_64: Remove hwmv1 compatible board definition To use this functionality one must now use the native_sim//64 (variant) version. The old hwmv1 compatible name for the board was left provisionally while all tests in tree were ported. That being now done, this old name can be removed. After this change one cannot build anymore targeting native_sim_64, but must instead build targeting native_sim/[native]/64. For twister tests the old name is already not valid. Signed-off-by: Alberto Escolar Piedras --- boards/deprecated.cmake | 4 ++++ boards/native/native_sim/Kconfig | 9 --------- boards/native/native_sim/Kconfig.native_sim_64 | 5 ----- boards/native/native_sim/board.yml | 8 -------- boards/native/native_sim/native_sim_64.dts | 7 ------- boards/native/native_sim/native_sim_64_defconfig | 4 ---- 6 files changed, 4 insertions(+), 33 deletions(-) delete mode 100644 boards/native/native_sim/Kconfig.native_sim_64 delete mode 100644 boards/native/native_sim/native_sim_64.dts delete mode 100644 boards/native/native_sim/native_sim_64_defconfig diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 0d1d0d35d6d..89fe2515d02 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -409,6 +409,10 @@ set(native_posix_64_DEPRECATED native_posix/native/64 ) +set(native_sim_64_DEPRECATED + native_sim/native/64 +) + set(nrf21540dk_nrf52840_DEPRECATED nrf21540dk ) diff --git a/boards/native/native_sim/Kconfig b/boards/native/native_sim/Kconfig index e61028cce07..c2610e840e7 100644 --- a/boards/native/native_sim/Kconfig +++ b/boards/native/native_sim/Kconfig @@ -12,15 +12,6 @@ config BOARD_NATIVE_SIM Native simulator (Single Core) Will produce a console Linux process which can be executed natively. -config BOARD_NATIVE_SIM_64 - bool - select BOARD_NATIVE_SIM - select 64BIT - help - Native simulator (Single Core) - 64 bit version - Will produce a console Linux process which can be executed natively - as a 64-bit executable. - if BOARD_NATIVE_SIM comment "Native Simular (Single Core) options" diff --git a/boards/native/native_sim/Kconfig.native_sim_64 b/boards/native/native_sim/Kconfig.native_sim_64 deleted file mode 100644 index c03791abd35..00000000000 --- a/boards/native/native_sim/Kconfig.native_sim_64 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_SIM_64 - select SOC_POSIX diff --git a/boards/native/native_sim/board.yml b/boards/native/native_sim/board.yml index 31ee9fabc08..19492170138 100644 --- a/boards/native/native_sim/board.yml +++ b/boards/native/native_sim/board.yml @@ -5,11 +5,3 @@ boards: - name: native variants: - name: "64" - -# This board definition below, together with its respective -# Kconfig.native_sim_64 exist for backwards compatibility with the hwmv1 board name -# Once all its usage in tree is removed, or an alias has been introduced they can be removed. -- name: native_sim_64 - vendor: zephyr - socs: - - name: native diff --git a/boards/native/native_sim/native_sim_64.dts b/boards/native/native_sim/native_sim_64.dts deleted file mode 100644 index 4ac77d414f9..00000000000 --- a/boards/native/native_sim/native_sim_64.dts +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "native_sim.dts" diff --git a/boards/native/native_sim/native_sim_64_defconfig b/boards/native/native_sim/native_sim_64_defconfig deleted file mode 100644 index b0033eda61f..00000000000 --- a/boards/native/native_sim/native_sim_64_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 From 22d51c11b0ae65280104d014847e4ac4b317b91d Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Sat, 23 Mar 2024 15:30:26 -0400 Subject: [PATCH 1482/2402] tests: posix: common: reorder headers to avoid LOG_ERR conflict The log subsystem defines LOG_ERR as a macro, which conflicts with the standard POSIX LOG_ERR log level (3). Reorder includes to avoid errors. Signed-off-by: Chris Friedt --- tests/posix/common/src/syslog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/posix/common/src/syslog.c b/tests/posix/common/src/syslog.c index 87b1ac5ac1a..226853daf01 100644 --- a/tests/posix/common/src/syslog.c +++ b/tests/posix/common/src/syslog.c @@ -5,8 +5,8 @@ */ #include -#include #undef LOG_ERR +#include #include #define N_PRIOS 8 From 4edb9017c229c34d111ec77d3c9105f8e77448f5 Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 21:03:13 -0400 Subject: [PATCH 1483/2402] posix: net: add kconfig option and inet_addr() Add a Kconfig option for POSIX_NETWORKING and implement inet_addr(). Signed-off-by: Chris Friedt --- include/zephyr/posix/arpa/inet.h | 3 ++ lib/posix/options/CMakeLists.txt | 1 + lib/posix/options/Kconfig | 1 + lib/posix/options/Kconfig.net | 11 ++++++ lib/posix/options/net.c | 67 ++++++++++++++++++++++++++++++++ 5 files changed, 83 insertions(+) create mode 100644 lib/posix/options/Kconfig.net create mode 100644 lib/posix/options/net.c diff --git a/include/zephyr/posix/arpa/inet.h b/include/zephyr/posix/arpa/inet.h index 244b98b24fc..e4e69340204 100644 --- a/include/zephyr/posix/arpa/inet.h +++ b/include/zephyr/posix/arpa/inet.h @@ -32,6 +32,9 @@ static inline int inet_pton(sa_family_t family, const char *src, void *dst) #endif /* CONFIG_NET_SOCKETS_POSIX_NAMES */ +in_addr_t inet_addr(const char *cp); +char *inet_ntoa(struct in_addr in); + #ifdef __cplusplus } #endif diff --git a/lib/posix/options/CMakeLists.txt b/lib/posix/options/CMakeLists.txt index eccaded7285..d7f3ef94e59 100644 --- a/lib/posix/options/CMakeLists.txt +++ b/lib/posix/options/CMakeLists.txt @@ -44,6 +44,7 @@ zephyr_library_sources_ifdef(CONFIG_POSIX_CONFSTR confstr.c) zephyr_library_sources_ifdef(CONFIG_POSIX_ENV env.c) zephyr_library_sources_ifdef(CONFIG_POSIX_FS fs.c) zephyr_library_sources_ifdef(CONFIG_POSIX_MQUEUE mqueue.c) +zephyr_library_sources_ifdef(CONFIG_POSIX_NETWORKING net.c) zephyr_library_sources_ifdef(CONFIG_POSIX_PUTMSG stropts.c) zephyr_library_sources_ifdef(CONFIG_POSIX_SIGNAL signal.c ${STRSIGNAL_TABLE_H}) zephyr_library_sources_ifdef(CONFIG_POSIX_SYSCONF_IMPL_FULL sysconf.c) diff --git a/lib/posix/options/Kconfig b/lib/posix/options/Kconfig index 496a7697d1a..7b67244d127 100644 --- a/lib/posix/options/Kconfig +++ b/lib/posix/options/Kconfig @@ -37,6 +37,7 @@ rsource "Kconfig.getopt" rsource "Kconfig.key" rsource "Kconfig.mqueue" rsource "Kconfig.mutex" +rsource "Kconfig.net" rsource "Kconfig.pthread" rsource "Kconfig.rwlock" rsource "Kconfig.sched" diff --git a/lib/posix/options/Kconfig.net b/lib/posix/options/Kconfig.net new file mode 100644 index 00000000000..5e2b363e167 --- /dev/null +++ b/lib/posix/options/Kconfig.net @@ -0,0 +1,11 @@ +# Copyright (c) 2024, Friedt Professional Engineering Services, Inc +# +# SPDX-License-Identifier: Apache-2.0 + +config POSIX_NETWORKING + bool "POSIX Networking API" + default y if POSIX_API + depends on NETWORKING + help + Enable this option to support the POSIX networking API. This includes + support for BSD Sockets. diff --git a/lib/posix/options/net.c b/lib/posix/options/net.c new file mode 100644 index 00000000000..735254f06b3 --- /dev/null +++ b/lib/posix/options/net.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024, Friedt Professional Engineering Services, Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include + +in_addr_t inet_addr(const char *cp) +{ + int val = 0; + int len = 0; + int dots = 0; + int digits = 0; + + /* error checking */ + if (cp == NULL) { + return -1; + } + + for (int i = 0, subdigits = 0; i <= INET_ADDRSTRLEN; ++i, ++len) { + if (subdigits > 3) { + return -1; + } + if (cp[i] == '\0') { + break; + } else if (cp[i] == '.') { + if (subdigits == 0) { + return -1; + } + ++dots; + subdigits = 0; + continue; + } else if (isdigit((int)cp[i])) { + ++digits; + ++subdigits; + continue; + } else if (isspace((int)cp[i])) { + break; + } + + return -1; + } + + if (dots != 3 || digits < 4) { + return -1; + } + + /* conversion */ + for (int i = 0, tmp = 0; i < len; ++i, ++cp) { + if (*cp != '.') { + tmp *= 10; + tmp += *cp - '0'; + } + + if (*cp == '.' || i == len - 1) { + val <<= 8; + val |= tmp; + tmp = 0; + } + } + + return htonl(val); +} From 3a78607c1c24fb9e2893131d03205e27ad17eb3f Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 21:03:13 -0400 Subject: [PATCH 1484/2402] tests: posix: net: add a posix network api testsuite Add a testsuite for posix networking apis with an initial test for inet_addr(). Signed-off-by: Chris Friedt --- tests/posix/net/CMakeLists.txt | 9 ++++++ tests/posix/net/prj.conf | 4 +++ tests/posix/net/src/inet_addr.c | 50 +++++++++++++++++++++++++++++++++ tests/posix/net/src/main.c | 9 ++++++ tests/posix/net/testcase.yaml | 9 ++++++ 5 files changed, 81 insertions(+) create mode 100644 tests/posix/net/CMakeLists.txt create mode 100644 tests/posix/net/prj.conf create mode 100644 tests/posix/net/src/inet_addr.c create mode 100644 tests/posix/net/src/main.c create mode 100644 tests/posix/net/testcase.yaml diff --git a/tests/posix/net/CMakeLists.txt b/tests/posix/net/CMakeLists.txt new file mode 100644 index 00000000000..80433bbd096 --- /dev/null +++ b/tests/posix/net/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(posix_net) + +FILE(GLOB app_sources src/*.c) + +target_sources(app PRIVATE ${app_sources}) diff --git a/tests/posix/net/prj.conf b/tests/posix/net/prj.conf new file mode 100644 index 00000000000..4831a9d150f --- /dev/null +++ b/tests/posix/net/prj.conf @@ -0,0 +1,4 @@ +CONFIG_ZTEST=y +CONFIG_NETWORKING=y +CONFIG_POSIX_NETWORKING=y +CONFIG_NET_TEST=y diff --git a/tests/posix/net/src/inet_addr.c b/tests/posix/net/src/inet_addr.c new file mode 100644 index 00000000000..4cf66a1e066 --- /dev/null +++ b/tests/posix/net/src/inet_addr.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2024, Friedt Professional Engineering Services, Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include +#include + +ZTEST(net, test_inet_addr) +{ + in_addr_t ret; + static const struct parm { + const char *in; + int out; + } parms[] = { + /* expect failure */ +#ifndef CONFIG_ARCH_POSIX + {NULL, (uint32_t)-1}, /* this value will segfault using the host libc */ +#endif + {".", (uint32_t)-1}, + {"..", (uint32_t)-1}, + {"...", (uint32_t)-1}, + {"-1.-2.-3.-4", (uint32_t)-1}, + {"256.65536.4294967296.18446744073709551616", (uint32_t)-1}, + {"a.b.c.d", (uint32_t)-1}, + {"0.0.0.1234", (uint32_t)-1}, + {"0.0.0.12a", (uint32_t)-1}, + {" 1.2.3.4", (uint32_t)-1}, + + /* expect success */ + {"0.0.0.0", htonl(0)}, + {"000.00.0.0", htonl(0)}, + {"127.0.0.1", htonl(0x7f000001)}, + {"1.2.3.4", htonl(0x01020304)}, + {"1.2.3.4 ", htonl(0x01020304)}, + {"0.0.0.123 a", htonl(0x0000007b)}, + {"255.255.255.255", htonl(0xffffffff)}, + }; + + ARRAY_FOR_EACH_PTR(parms, p) { + ret = inet_addr(p->in); + zexpect_equal(ret, p->out, "inet_addr(%s) failed. expect: %d actual: %d", p->in, + p->out, ret); + } +} diff --git a/tests/posix/net/src/main.c b/tests/posix/net/src/main.c new file mode 100644 index 00000000000..bbb25dcacfc --- /dev/null +++ b/tests/posix/net/src/main.c @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2024, Friedt Professional Engineering Services, Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +ZTEST_SUITE(net, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/posix/net/testcase.yaml b/tests/posix/net/testcase.yaml new file mode 100644 index 00000000000..ce042ce3a36 --- /dev/null +++ b/tests/posix/net/testcase.yaml @@ -0,0 +1,9 @@ +common: + depends_on: netif + min_ram: 16 + tags: + - iface + - net + - posix +tests: + portability.posix.net: {} From 7a397a08b73cd575e7ee99fd8c6e4c7f28672232 Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 21:03:13 -0400 Subject: [PATCH 1485/2402] posix: net: implement inet_ntoa() Add an implementation of inet_ntoa(). Signed-off-by: Chris Friedt --- lib/posix/options/net.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/lib/posix/options/net.c b/lib/posix/options/net.c index 735254f06b3..76e1cef3f6d 100644 --- a/lib/posix/options/net.c +++ b/lib/posix/options/net.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -65,3 +66,13 @@ in_addr_t inet_addr(const char *cp) return htonl(val); } + +char *inet_ntoa(struct in_addr in) +{ + static char buf[INET_ADDRSTRLEN]; + unsigned char *bytes = (unsigned char *)&in.s_addr; + + snprintf(buf, sizeof(buf), "%d.%d.%d.%d", bytes[0], bytes[1], bytes[2], bytes[3]); + + return buf; +} From bfb91da5ec0286a506809e027baed21858e377ba Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 21:03:13 -0400 Subject: [PATCH 1486/2402] tests: posix: net: tests for inet_ntoa() Add tests for inet_ntoa() Signed-off-by: Chris Friedt --- tests/posix/net/src/inet_ntoa.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 tests/posix/net/src/inet_ntoa.c diff --git a/tests/posix/net/src/inet_ntoa.c b/tests/posix/net/src/inet_ntoa.c new file mode 100644 index 00000000000..963fe371d2f --- /dev/null +++ b/tests/posix/net/src/inet_ntoa.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024, Friedt Professional Engineering Services, Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +ZTEST(net, test_inet_ntoa) +{ + struct in_addr in; + + in.s_addr = htonl(0x7f000001); + zassert_mem_equal(inet_ntoa(in), "127.0.0.1", strlen("127.0.0.1") + 1); + + in.s_addr = htonl(0); + zassert_mem_equal(inet_ntoa(in), "0.0.0.0", strlen("0.0.0.0") + 1); + + in.s_addr = htonl(0xffffffff); + zassert_mem_equal(inet_ntoa(in), "255.255.255.255", strlen("255.255.255.255") + 1); +} From a00eeb638a89aa775076efdf1e26a271b0c15982 Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 21:03:13 -0400 Subject: [PATCH 1487/2402] posix: net: implement if_nameindex() et al Implement if_indextoname(), if_freenameindex(), if_nameindex(), and if_nametoindex() by wrapping around networking subystem calls. Signed-off-by: Chris Friedt --- include/zephyr/posix/net/if.h | 16 +++++- lib/posix/options/net.c | 98 +++++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/include/zephyr/posix/net/if.h b/include/zephyr/posix/net/if.h index a8d6183cf80..80360a69604 100644 --- a/include/zephyr/posix/net/if.h +++ b/include/zephyr/posix/net/if.h @@ -6,12 +6,26 @@ #ifndef ZEPHYR_INCLUDE_POSIX_NET_IF_H_ #define ZEPHYR_INCLUDE_POSIX_NET_IF_H_ -#include +#ifdef CONFIG_NET_INTERFACE_NAME_LEN +#define IF_NAMESIZE CONFIG_NET_INTERFACE_NAME_LEN +#else +#define IF_NAMESIZE 1 +#endif #ifdef __cplusplus extern "C" { #endif +struct if_nameindex { + unsigned int if_index; + char *if_name; +}; + +char *if_indextoname(unsigned int ifindex, char *ifname); +void if_freenameindex(struct if_nameindex *ptr); +struct if_nameindex *if_nameindex(void); +unsigned int if_nametoindex(const char *ifname); + #ifdef __cplusplus } #endif diff --git a/lib/posix/options/net.c b/lib/posix/options/net.c index 76e1cef3f6d..f489910eae9 100644 --- a/lib/posix/options/net.c +++ b/lib/posix/options/net.c @@ -6,9 +6,12 @@ #include #include +#include +#include #include #include +#include in_addr_t inet_addr(const char *cp) { @@ -76,3 +79,98 @@ char *inet_ntoa(struct in_addr in) return buf; } + +char *if_indextoname(unsigned int ifindex, char *ifname) +{ + int ret; + + if (!IS_ENABLED(CONFIG_NET_INTERFACE_NAME)) { + errno = ENOTSUP; + return NULL; + } + + ret = net_if_get_name(net_if_get_by_index(ifindex), ifname, IF_NAMESIZE); + if (ret < 0) { + errno = ENXIO; + return NULL; + } + + return ifname; +} + +void if_freenameindex(struct if_nameindex *ptr) +{ + size_t n; + + if (ptr == NULL || !IS_ENABLED(CONFIG_NET_INTERFACE_NAME)) { + return; + } + + NET_IFACE_COUNT(&n); + + for (size_t i = 0; i < n; ++i) { + if (IS_ENABLED(CONFIG_NET_INTERFACE_NAME) && ptr[i].if_name != NULL) { + free(ptr[i].if_name); + } + } + + free(ptr); +} + +struct if_nameindex *if_nameindex(void) +{ + size_t n; + char *name; + struct if_nameindex *ni; + + if (!IS_ENABLED(CONFIG_NET_INTERFACE_NAME)) { + errno = ENOTSUP; + return NULL; + } + + /* FIXME: would be nice to use this without malloc */ + NET_IFACE_COUNT(&n); + ni = malloc((n + 1) * sizeof(*ni)); + if (ni == NULL) { + goto return_err; + } + + for (size_t i = 0; i < n; ++i) { + ni[i].if_index = i + 1; + + ni[i].if_name = malloc(IF_NAMESIZE); + if (ni[i].if_name == NULL) { + goto return_err; + } + + name = if_indextoname(i + 1, ni[i].if_name); + __ASSERT_NO_MSG(name != NULL); + } + + ni[n].if_index = 0; + ni[n].if_name = NULL; + + return ni; + +return_err: + if_freenameindex(ni); + errno = ENOBUFS; + + return NULL; +} + +unsigned int if_nametoindex(const char *ifname) +{ + int ret; + + if (!IS_ENABLED(CONFIG_NET_INTERFACE_NAME)) { + return 0; + } + + ret = net_if_get_by_name(ifname); + if (ret < 0) { + return 0; + } + + return ret; +} From 7b9bf85d9b782117d3c12684af1ddbc3cd312b70 Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 21:35:29 -0400 Subject: [PATCH 1488/2402] tests: posix: headers: uncomment net/if.h tests Uncomment net/if.h tests in tests/posix/headers since we now have an implementation and can check for the existence of structures, functions, etc. Signed-off-by: Chris Friedt --- tests/posix/headers/src/net_if_h.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/posix/headers/src/net_if_h.c b/tests/posix/headers/src/net_if_h.c index f3e3cb77ac6..bc88e992f68 100644 --- a/tests/posix/headers/src/net_if_h.c +++ b/tests/posix/headers/src/net_if_h.c @@ -19,15 +19,15 @@ */ ZTEST(posix_headers, test_net_if_h) { - /* zassert_not_equal(-1, offsetof(struct if_nameindex, if_index)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct if_nameindex, if_name)); */ /* not implemented */ + zassert_not_equal(-1, offsetof(struct if_nameindex, if_index)); + zassert_not_equal(-1, offsetof(struct if_nameindex, if_name)); - /* zassert_not_equal(-1, IF_NAMESIZE); */ /* not implemented */ + zassert_not_equal(-1, IF_NAMESIZE); if (IS_ENABLED(CONFIG_POSIX_API)) { - /* zassert_not_null(if_freenameindex); */ /* not implemented */ - /* zassert_not_null(if_indextoname); */ /* not implemented */ - /* zassert_not_null(if_nameindex); */ /* not implemented */ - /* zassert_not_null(if_nametoindex); */ /* not implemented */ + zassert_not_null(if_freenameindex); + zassert_not_null(if_indextoname); + zassert_not_null(if_nameindex); + zassert_not_null(if_nametoindex); } } From 9e5f54f017d4479801166354394866cdc83ea662 Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 21:03:13 -0400 Subject: [PATCH 1489/2402] tests: posix: net: add tests for if_nameindex et al Add tests for if_indextoname(), if_freenameindex(), if_nameindex(), and if_nametoindex(). Signed-off-by: Chris Friedt --- tests/posix/net/src/if.c | 80 +++++++++++++++++++++++++++++++++++ tests/posix/net/testcase.yaml | 6 +++ 2 files changed, 86 insertions(+) create mode 100644 tests/posix/net/src/if.c diff --git a/tests/posix/net/src/if.c b/tests/posix/net/src/if.c new file mode 100644 index 00000000000..218fff82f51 --- /dev/null +++ b/tests/posix/net/src/if.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2024, Friedt Professional Engineering Services, Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +ZTEST(net, test_if_indextoname) +{ + char *name; + size_t n = 0; + struct net_if *iface; + char a[IF_NAMESIZE]; + char b[IF_NAMESIZE]; + + NET_IFACE_COUNT(&n); + TC_PRINT("%zu interfaces\n", n); + for (size_t i = 0; i < n; i++) { + memset(a, 0, sizeof(a)); + memset(b, 0, sizeof(b)); + name = if_indextoname(i + 1, a); + zassert_equal(name, a); + TC_PRINT("interface %zu: %s\n", i + 1, name); + iface = net_if_get_by_index(i + 1); + zassert_not_null(iface); + zassert_true(net_if_get_name(iface, b, IF_NAMESIZE) >= 0); + zassert_mem_equal(a, b, IF_NAMESIZE); + } +} + +ZTEST(net, test_if_freenameindex) +{ + if_freenameindex(NULL); + if_freenameindex(if_nameindex()); +} + +ZTEST(net, test_if_nameindex) +{ + size_t n = 0; + struct if_nameindex *ni; + + NET_IFACE_COUNT(&n); + TC_PRINT("%zu interfaces\n", n); + + ni = if_nameindex(); + if (ni == NULL) { + zassert_equal(errno, ENOBUFS); + return; + } + + for (size_t i = 0; i < n; i++) { + zassert_equal(i + 1, ni[i].if_index); + zassert_not_null(ni[i].if_name); + TC_PRINT("interface %zu: %s\n", i + 1, ni[i].if_name); + zassert_equal(0, ni[n].if_index); + zassert_is_null(ni[n].if_name); + } + + if_freenameindex(ni); +} + +ZTEST(net, test_if_nametoindex) +{ + size_t n = 0; + char buf[IF_NAMESIZE]; + + NET_IFACE_COUNT(&n); + TC_PRINT("%zu interfaces\n", n); + for (size_t i = 0; i < n; i++) { + memset(buf, 0, sizeof(buf)); + zassert_not_null(if_indextoname(i + 1, buf)); + TC_PRINT("interface %zu: %s\n", i + 1, buf); + zassert_equal(i + 1, if_nametoindex(buf)); + } +} diff --git a/tests/posix/net/testcase.yaml b/tests/posix/net/testcase.yaml index ce042ce3a36..5cbd4068b94 100644 --- a/tests/posix/net/testcase.yaml +++ b/tests/posix/net/testcase.yaml @@ -1,6 +1,12 @@ common: depends_on: netif + # native_sim uses if_*() from the native libc + filter: not CONFIG_NATIVE_LIBC + integration_platforms: + - qemu_x86 min_ram: 16 + platform_allow: + - qemu_x86 tags: - iface - net From 62031f5daa20e977a3c5dd84662ca50a0320cff1 Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 21:29:06 -0400 Subject: [PATCH 1490/2402] posix: net: add trivial netdb function implementations Add trivial function implementations for those declared in netdb.h . Signed-off-by: Chris Friedt --- include/zephyr/posix/netdb.h | 47 ++++++++++++++++ lib/posix/options/net.c | 101 +++++++++++++++++++++++++++++++++++ 2 files changed, 148 insertions(+) diff --git a/include/zephyr/posix/netdb.h b/include/zephyr/posix/netdb.h index 6006a636884..0e1b71cc243 100644 --- a/include/zephyr/posix/netdb.h +++ b/include/zephyr/posix/netdb.h @@ -29,6 +29,34 @@ extern "C" { #endif +struct hostent { + char *h_name; + char **h_aliases; + int h_addrtype; + int h_length; + char **h_addr_list; +}; + +struct netent { + char *n_name; + char **n_aliases; + int n_addrtype; + uint32_t n_net; +}; + +struct protoent { + char *p_name; + char **p_aliases; + int p_proto; +}; + +struct servent { + char *s_name; + char **s_aliases; + int s_port; + char *s_proto; +}; + #ifndef CONFIG_NET_SOCKETS_POSIX_NAMES #define addrinfo zsock_addrinfo @@ -60,6 +88,25 @@ static inline int getnameinfo(const struct sockaddr *addr, socklen_t addrlen, #endif /* CONFIG_NET_SOCKETS_POSIX_NAMES */ +void endhostent(void); +void endnetent(void); +void endprotoent(void); +void endservent(void); +struct hostent *gethostent(void); +struct netent *getnetbyaddr(uint32_t net, int type); +struct netent *getnetbyname(const char *name); +struct netent *getnetent(void); +struct protoent *getprotobyname(const char *name); +struct protoent *getprotobynumber(int proto); +struct protoent *getprotoent(void); +struct servent *getservbyname(const char *name, const char *proto); +struct servent *getservbyport(int port, const char *proto); +struct servent *getservent(void); +void sethostent(int stayopen); +void setnetent(int stayopen); +void setprotoent(int stayopen); +void setservent(int stayopen); + #ifdef __cplusplus } #endif diff --git a/lib/posix/options/net.c b/lib/posix/options/net.c index f489910eae9..5e0888e2d30 100644 --- a/lib/posix/options/net.c +++ b/lib/posix/options/net.c @@ -174,3 +174,104 @@ unsigned int if_nametoindex(const char *ifname) return ret; } + +void endhostent(void) +{ +} + +void endnetent(void) +{ +} + +void endprotoent(void) +{ +} + +void endservent(void) +{ +} + +struct hostent *gethostent(void) +{ + return NULL; +} + +struct netent *getnetbyaddr(uint32_t net, int type) +{ + ARG_UNUSED(net); + ARG_UNUSED(type); + + return NULL; +} + +struct netent *getnetbyname(const char *name) +{ + ARG_UNUSED(name); + + return NULL; +} + +struct netent *getnetent(void) +{ + return NULL; +} + +struct protoent *getprotobyname(const char *name) +{ + ARG_UNUSED(name); + + return NULL; +} + +struct protoent *getprotobynumber(int proto) +{ + ARG_UNUSED(proto); + + return NULL; +} + +struct protoent *getprotoent(void) +{ + return NULL; +} + +struct servent *getservbyname(const char *name, const char *proto) +{ + ARG_UNUSED(name); + ARG_UNUSED(proto); + + return NULL; +} + +struct servent *getservbyport(int port, const char *proto) +{ + ARG_UNUSED(port); + ARG_UNUSED(proto); + + return NULL; +} + +struct servent *getservent(void) +{ + return NULL; +} + +void sethostent(int stayopen) +{ + ARG_UNUSED(stayopen); +} + +void setnetent(int stayopen) +{ + ARG_UNUSED(stayopen); +} + +void setprotoent(int stayopen) +{ + ARG_UNUSED(stayopen); +} + +void setservent(int stayopen) +{ + ARG_UNUSED(stayopen); +} From 6720c92f3eefa5452b953caa035066c69fdb32c7 Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 21:34:12 -0400 Subject: [PATCH 1491/2402] tests: posix: headers: uncomment netdb.h tests Uncomment netdb.h tests now that we have an implementation and can check for the existence of e.g. hostent, netent, protoent, and servent structure fields, as well as associated accessor functions. Signed-off-by: Chris Friedt --- tests/posix/headers/src/netdb_h.c | 68 +++++++++++++++---------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/tests/posix/headers/src/netdb_h.c b/tests/posix/headers/src/netdb_h.c index 3d6240fbfce..85e69fb7c55 100644 --- a/tests/posix/headers/src/netdb_h.c +++ b/tests/posix/headers/src/netdb_h.c @@ -19,25 +19,25 @@ */ ZTEST(posix_headers, test_netdb_h) { - /* zassert_not_equal(-1, offsetof(struct hostent, h_name)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct hostent, h_aliases)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct hostent, h_addrtype)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct hostent, h_length)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct hostent, h_addr_list)); */ /* not implemented */ + zassert_not_equal(-1, offsetof(struct hostent, h_name)); + zassert_not_equal(-1, offsetof(struct hostent, h_aliases)); + zassert_not_equal(-1, offsetof(struct hostent, h_addrtype)); + zassert_not_equal(-1, offsetof(struct hostent, h_length)); + zassert_not_equal(-1, offsetof(struct hostent, h_addr_list)); - /* zassert_not_equal(-1, offsetof(struct netent, n_name)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct netent, n_aliases)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct netent, n_addrtype)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct netent, n_net)); */ /* not implemented */ + zassert_not_equal(-1, offsetof(struct netent, n_name)); + zassert_not_equal(-1, offsetof(struct netent, n_aliases)); + zassert_not_equal(-1, offsetof(struct netent, n_addrtype)); + zassert_not_equal(-1, offsetof(struct netent, n_net)); - /* zassert_not_equal(-1, offsetof(struct protoent, p_name)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct protoent, p_aliases)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct protoent, p_proto)); */ /* not implemented */ + zassert_not_equal(-1, offsetof(struct protoent, p_name)); + zassert_not_equal(-1, offsetof(struct protoent, p_aliases)); + zassert_not_equal(-1, offsetof(struct protoent, p_proto)); - /* zassert_not_equal(-1, offsetof(struct servent, s_name)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct servent, s_aliases)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct servent, s_port)); */ /* not implemented */ - /* zassert_not_equal(-1, offsetof(struct servent, s_proto)); */ /* not implemented */ + zassert_not_equal(-1, offsetof(struct servent, s_name)); + zassert_not_equal(-1, offsetof(struct servent, s_aliases)); + zassert_not_equal(-1, offsetof(struct servent, s_port)); + zassert_not_equal(-1, offsetof(struct servent, s_proto)); /* zassert_equal(IPPORT_RESERVED, UINT16_MAX); */ /* not implemented */ @@ -77,27 +77,27 @@ ZTEST(posix_headers, test_netdb_h) zassert_not_equal(-1, EAI_OVERFLOW); if (IS_ENABLED(CONFIG_POSIX_API)) { - /* zassert_not_null(endhostent); */ /* not implemented */ - /* zassert_not_null(endnetent); */ /* not implemented */ - /* zassert_not_null(endprotoent); */ /* not implemented */ - /* zassert_not_null(endservent); */ /* not implemented */ + zassert_not_null(endhostent); + zassert_not_null(endnetent); + zassert_not_null(endprotoent); + zassert_not_null(endservent); zassert_not_null(freeaddrinfo); zassert_not_null(gai_strerror); zassert_not_null(getaddrinfo); - /* zassert_not_null(gethostent); */ /* not implemented */ + zassert_not_null(gethostent); zassert_not_null(getnameinfo); - /* zassert_not_null(getnetbyaddr); */ /* not implemented */ - /* zassert_not_null(getnetbyname); */ /* not implemented */ - /* zassert_not_null(getnetent); */ /* not implemented */ - /* zassert_not_null(getprotobyname); */ /* not implemented */ - /* zassert_not_null(getprotobynumber); */ /* not implemented */ - /* zassert_not_null(getprotoent); */ /* not implemented */ - /* zassert_not_null(getservbyname); */ /* not implemented */ - /* zassert_not_null(getservbyport); */ /* not implemented */ - /* zassert_not_null(getservent); */ /* not implemented */ - /* zassert_not_null(sethostent); */ /* not implemented */ - /* zassert_not_null(setnetent); */ /* not implemented */ - /* zassert_not_null(setprotoent); */ /* not implemented */ - /* zassert_not_null(setservent); */ /* not implemented */ + zassert_not_null(getnetbyaddr); + zassert_not_null(getnetbyname); + zassert_not_null(getnetent); + zassert_not_null(getprotobyname); + zassert_not_null(getprotobynumber); + zassert_not_null(getprotoent); + zassert_not_null(getservbyname); + zassert_not_null(getservbyport); + zassert_not_null(getservent); + zassert_not_null(sethostent); + zassert_not_null(setnetent); + zassert_not_null(setprotoent); + zassert_not_null(setservent); } } From 494493a3b85e121970803c5176f6559b1efbd5ce Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 21:40:31 -0400 Subject: [PATCH 1492/2402] posix: net: add a trivial implementation of sockatmark() Add a trivial implementation of sockatmark(). Signed-off-by: Chris Friedt --- include/zephyr/posix/sys/socket.h | 2 ++ lib/posix/options/net.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/include/zephyr/posix/sys/socket.h b/include/zephyr/posix/sys/socket.h index 235bd76cc59..ea3a177d88a 100644 --- a/include/zephyr/posix/sys/socket.h +++ b/include/zephyr/posix/sys/socket.h @@ -125,6 +125,8 @@ static inline int getsockname(int sock, struct sockaddr *addr, #endif /* CONFIG_NET_SOCKETS_POSIX_NAMES */ +int sockatmark(int s); + #ifdef __cplusplus } #endif diff --git a/lib/posix/options/net.c b/lib/posix/options/net.c index 5e0888e2d30..695eff784e0 100644 --- a/lib/posix/options/net.c +++ b/lib/posix/options/net.c @@ -275,3 +275,11 @@ void setservent(int stayopen) { ARG_UNUSED(stayopen); } + +int sockatmark(int s) +{ + ARG_UNUSED(s); + + errno = ENOSYS; + return -1; +} From fc725a7ce3af2e5aa39c4fd3fe9dab53c20c2fd5 Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 21:41:04 -0400 Subject: [PATCH 1493/2402] tests: posix: headers: uncomment check for sockatmark() Uncomment the check for sockatmark() to ensure that the function is declared in sys/socket.h, as a stub implementation was added in the previous commit. Signed-off-by: Chris Friedt --- tests/posix/headers/src/sys_socket_h.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/posix/headers/src/sys_socket_h.c b/tests/posix/headers/src/sys_socket_h.c index 81ab9f95fd6..52ec01a2131 100644 --- a/tests/posix/headers/src/sys_socket_h.c +++ b/tests/posix/headers/src/sys_socket_h.c @@ -115,7 +115,7 @@ ZTEST(posix_headers, test_sys_socket_h) zassert_not_null(sendto); zassert_not_null(setsockopt); zassert_not_null(shutdown); - /* zassert_not_null(sockatmark); */ /* not implemented */ + zassert_not_null(sockatmark); zassert_not_null(socket); zassert_not_null(socketpair); } From 0bcf71e28a28b62d186a9f9495a56adb1e4aed9f Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Fri, 22 Mar 2024 22:09:52 -0400 Subject: [PATCH 1494/2402] doc: posix: add POSIX_NETWORKING Option Group and mark supported Mark the POSIX_NETWORKING Option Group as supported. The POSIX_NETWORKING Option Group is required for PSE53 Conformance. Signed-off-by: Chris Friedt --- doc/services/portability/posix/aep/index.rst | 2 +- .../portability/posix/option_groups/index.rst | 64 +++++++++++++++++++ 2 files changed, 65 insertions(+), 1 deletion(-) diff --git a/doc/services/portability/posix/aep/index.rst b/doc/services/portability/posix/aep/index.rst index c532c2a059b..fdc2716b2e2 100644 --- a/doc/services/portability/posix/aep/index.rst +++ b/doc/services/portability/posix/aep/index.rst @@ -139,7 +139,7 @@ Dedicated Realtime System Profile (PSE53) POSIX_FILE_LOCKING,, POSIX_FILE_SYSTEM,, POSIX_MULTI_PROCESS,, :ref:`†` - POSIX_NETWORKING, yes, :ref:`†` + POSIX_NETWORKING, yes, :ref:`POSIX_NETWORKING ` POSIX_PIPE,, :ref:`†` POSIX_SIGNALS,, :ref:`†` POSIX_SIGNAL_JUMP,, :ref:`†` diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst index 569cfe45aa5..0c1267ed69e 100644 --- a/doc/services/portability/posix/option_groups/index.rst +++ b/doc/services/portability/posix/option_groups/index.rst @@ -289,6 +289,70 @@ POSIX_CLOCK_SELECTION pthread_condattr_setclock(),yes clock_nanosleep(),yes +.. _posix_option_group_networking: + +POSIX_NETWORKING +================ + +.. csv-table:: POSIX_NETWORKING + :header: API, Supported + :widths: 50,10 + + accept(),yes + bind(),yes + connect(),yes + endhostent(),yes + endnetent(),yes + endprotoent(),yes + endservent(),yes + freeaddrinfo(),yes + gai_strerror(),yes + getaddrinfo(),yes + gethostent(),yes + gethostname(),yes + getnameinfo(),yes + getnetbyaddr(),yes + getnetbyname(),yes + getnetent(),yes + getpeername(),yes + getprotobyname(),yes + getprotobynumber(),yes + getprotoent(),yes + getservbyname(),yes + getservbyport(),yes + getservent(),yes + getsockname(),yes + getsockopt(),yes + htonl(),yes + htons(),yes + if_freenameindex(),yes + if_indextoname(),yes + if_nameindex(),yes + if_nametoindex(),yes + inet_addr(),yes + inet_ntoa(),yes + inet_ntop(),yes + inet_pton(),yes + listen(),yes + ntohl(),yes + ntohs(),yes + recv(),yes + recvfrom(),yes + recvmsg(),yes + send(),yes + sendmsg(),yes + sendto(),yes + sethostent(),yes + setnetent(),yes + setprotoent(),yes + setservent(),yes + setsockopt(),yes + shutdown(),yes + socket(),yes + sockatmark(),yes (will fail with ``ENOSYS``:ref:`†`) + socketpair(),yes + + .. _posix_option_group_semaphores: POSIX_SEMAPHORES From 6049bbf4e0f006b707ca4991cb0bb015cb63b799 Mon Sep 17 00:00:00 2001 From: Robert Zieba Date: Wed, 28 Feb 2024 10:30:12 -0700 Subject: [PATCH 1495/2402] gdbstub: Ignore indexing warning with -Warray-bounds The current implementation can raise a warning as the compiler sees an attempt to index an array with a size of zero. This can be fixed by giving `gdb_mem_num_regions` a default value of zero, but this gets flagged by CI checks. Disable the warning around the array access. Signed-off-by: Robert Zieba --- subsys/debug/gdbstub.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/subsys/debug/gdbstub.c b/subsys/debug/gdbstub.c index e632ff8abf4..849d791b2c2 100644 --- a/subsys/debug/gdbstub.c +++ b/subsys/debug/gdbstub.c @@ -41,7 +41,7 @@ static bool not_first_start; /* Empty memory region array */ __weak const struct gdb_mem_region gdb_mem_region_array[0]; -/* Number of memory regions, default to 0 */ +/* Number of memory regions */ __weak const size_t gdb_mem_num_regions; /** @@ -55,6 +55,12 @@ __weak const size_t gdb_mem_num_regions; * @return Pointer to the memory region description if found. * NULL if not found. */ +#if defined(__GNUC__) +#pragma GCC diagnostic push +/* Required due to gdb_mem_region_array having a default size of zero. */ +#pragma GCC diagnostic ignored "-Warray-bounds" +#endif + static inline const struct gdb_mem_region *find_memory_region(const uintptr_t addr, const size_t len) { @@ -76,6 +82,10 @@ struct gdb_mem_region *find_memory_region(const uintptr_t addr, const size_t len return ret; } +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + bool gdb_mem_can_read(const uintptr_t addr, const size_t len, uint8_t *align) { bool ret = false; From 13deb0365c0add925fa6505f8f474748a6f59c46 Mon Sep 17 00:00:00 2001 From: Nathan Olff Date: Sun, 7 Jan 2024 17:29:18 +0100 Subject: [PATCH 1496/2402] drivers: sensor: dht20: implement new driver The DHT20 sensor is a temperature and humidity sensor that uses I2C to communicate with a microcontroller. The DHT20 sensor is Aosong. use standard crc update description to add reference to AHT20 and AM2301B clean code, use defines and bit manipulation add dht20 to i2c test suite for build tests update bit manipulation use more defines instead of raw numbers add bindings to allow aht20 or am2301b to be used in devicetree in all 3 cases, the same dht20.c driver is compiled Signed-off-by: Nathan Olff --- drivers/sensor/CMakeLists.txt | 1 + drivers/sensor/Kconfig | 1 + drivers/sensor/dht20/CMakeLists.txt | 5 + drivers/sensor/dht20/Kconfig | 26 ++ drivers/sensor/dht20/dht20.c | 359 ++++++++++++++++++++++++ dts/bindings/sensor/aosong,aht20.yaml | 14 + dts/bindings/sensor/aosong,am2301b.yaml | 14 + dts/bindings/sensor/aosong,dht20.yaml | 14 + tests/drivers/build_all/sensor/i2c.dtsi | 18 ++ 9 files changed, 452 insertions(+) create mode 100644 drivers/sensor/dht20/CMakeLists.txt create mode 100644 drivers/sensor/dht20/Kconfig create mode 100644 drivers/sensor/dht20/dht20.c create mode 100644 dts/bindings/sensor/aosong,aht20.yaml create mode 100644 dts/bindings/sensor/aosong,am2301b.yaml create mode 100644 dts/bindings/sensor/aosong,dht20.yaml diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 35790146b02..52962a0b2fd 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -36,6 +36,7 @@ add_subdirectory_ifdef(CONFIG_BQ274XX bq274xx) add_subdirectory_ifdef(CONFIG_CCS811 ccs811) add_subdirectory_ifdef(CONFIG_CURRENT_AMP current_amp) add_subdirectory_ifdef(CONFIG_DHT dht) +add_subdirectory_ifdef(CONFIG_DHT20 dht20) add_subdirectory_ifdef(CONFIG_DPS310 dps310) add_subdirectory_ifdef(CONFIG_DS18B20 ds18b20) add_subdirectory_ifdef(CONFIG_ENS160 ens160) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 1768335979a..27d6c165197 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -116,6 +116,7 @@ source "drivers/sensor/bq274xx/Kconfig" source "drivers/sensor/ccs811/Kconfig" source "drivers/sensor/current_amp/Kconfig" source "drivers/sensor/dht/Kconfig" +source "drivers/sensor/dht20/Kconfig" source "drivers/sensor/dps310/Kconfig" source "drivers/sensor/ds18b20/Kconfig" source "drivers/sensor/ens160/Kconfig" diff --git a/drivers/sensor/dht20/CMakeLists.txt b/drivers/sensor/dht20/CMakeLists.txt new file mode 100644 index 00000000000..c5539e1d49c --- /dev/null +++ b/drivers/sensor/dht20/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(dht20.c) diff --git a/drivers/sensor/dht20/Kconfig b/drivers/sensor/dht20/Kconfig new file mode 100644 index 00000000000..54c8d731ec9 --- /dev/null +++ b/drivers/sensor/dht20/Kconfig @@ -0,0 +1,26 @@ +# AOSONG DHT20 temperature and humidity sensor configuration options +# This driver can also be used for AHT20 or AM2301B which seem to be the same sensor + +# Copyright (c) 2024 Nathan Olff +# SPDX-License-Identifier: Apache-2.0 + +config DHT20 + bool "DHT20 / AHT20 / AM2301B Temperature and Humidity Sensor" + default y + depends on DT_HAS_AOSONG_DHT20_ENABLED \ + || DT_HAS_AOSONG_AHT20_ENABLED \ + || DT_HAS_AOSONG_AM2301B_ENABLED + select I2C + help + Enable driver for DHT20 / AHT20 / AM2301B temperature and humidity sensors. + +if DHT20 + +config DHT20_CRC + bool "Use CRC error detection" + default n + select CRC + help + Verify CRC byte in RX data + +endif # DHT20 diff --git a/drivers/sensor/dht20/dht20.c b/drivers/sensor/dht20/dht20.c new file mode 100644 index 00000000000..ba43584a9ad --- /dev/null +++ b/drivers/sensor/dht20/dht20.c @@ -0,0 +1,359 @@ +/* + * Copyright (c) 2024 Nathan Olff + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#if defined(CONFIG_DHT20_CRC) +#include +#endif +#include +#include +#include +#include + +#define DHT20_STATUS_REGISTER 0x71 + +#define DHT20_STATUS_MASK (BIT(0) | BIT(1)) + +#define DHT20_STATUS_MASK_CHECK 0x18 +#define DHT20_STATUS_MASK_POLL_STATE 0x80 + +#define DHT20_MASK_RESET_REGISTER 0xB0 + +#define DHT20_TRIGGER_MEASUREMENT_COMMAND 0xAC, 0x33, 0x00 + +#define DHT20_TRIGGER_MEASUREMENT_BUFFER_LENGTH 3 + +/** CRC polynom (1 + X^4 + X^5 + X^8) */ +#define DHT20_CRC_POLYNOM (BIT(0) | BIT(4) | BIT(5)) + +/* + * According to datasheet 7.4 + * Reset register 0x1B, 0x1C and 0x1E + */ +#define DHT20_RESET_REGISTER_0 0x1B +#define DHT20_RESET_REGISTER_1 0x1C +#define DHT20_RESET_REGISTER_2 0x1E + +/** Length of the buffer used for data measurement */ +#define DHT20_MEASUREMENT_BUFFER_LENGTH 7 + +/** Wait some time after reset sequence (in ms) */ +#define DHT20_RESET_SEQUENCE_WAIT_MS 10 + +/** Wait after power on (in ms) */ +#define DHT20_POWER_ON_WAIT_MS 75 +/** Wait during polling after power on (in ms) */ +#define DHT20_INIT_POLL_STATUS_WAIT_MS 5 + +LOG_MODULE_REGISTER(DHT20, CONFIG_SENSOR_LOG_LEVEL); + +struct dht20_config { + struct i2c_dt_spec bus; +}; + +struct dht20_data { + uint32_t t_sample; + uint32_t rh_sample; +}; + +/** + * @brief Read status register + * + * @param dev Pointer to the sensor device + * @param[out] status Pointer to which the status will be stored + * @return 0 if successful + */ +static inline int read_status(const struct device *dev, uint8_t *status) +{ + const struct dht20_config *cfg = dev->config; + int rc; + uint8_t tx_buf[] = {DHT20_STATUS_REGISTER}; + uint8_t rx_buf[1]; + + /* Write DHT20_STATUS_REGISTER then read to get status */ + rc = i2c_write_dt(&cfg->bus, tx_buf, sizeof(tx_buf)); + if (rc < 0) { + LOG_ERR("Failed to start measurement."); + return rc; + } + + rc = i2c_read_dt(&cfg->bus, rx_buf, sizeof(rx_buf)); + if (rc < 0) { + LOG_ERR("Failed to read data from device."); + return rc; + } + + /* Retrieve status from rx_buf */ + *status = rx_buf[0]; + return rc; +} + +static inline int reset_register(const struct device *dev, uint8_t reg) +{ + const struct dht20_config *cfg = dev->config; + int rc; + uint8_t tx_buf[] = {reg, 0, 0}; + uint8_t rx_buf[3]; + + /* Write and then read 3 bytes from device */ + rc = i2c_write_read_dt(&cfg->bus, tx_buf, sizeof(tx_buf), rx_buf, sizeof(rx_buf)); + if (rc < 0) { + LOG_ERR("Failed to reset register."); + return rc; + } + + /* Write register again, using values read earlier */ + tx_buf[0] = DHT20_MASK_RESET_REGISTER | reg; + tx_buf[1] = rx_buf[1]; + tx_buf[2] = rx_buf[2]; + rc = i2c_write_dt(&cfg->bus, tx_buf, sizeof(tx_buf)); + if (rc < 0) { + LOG_ERR("Failed to reset register."); + return rc; + } + + return rc; +} + +static inline int reset_sensor(const struct device *dev) +{ + int rc; + uint8_t status; + + rc = read_status(dev, &status); + if (rc < 0) { + LOG_ERR("Failed to read status"); + return rc; + } + + if ((status & DHT20_STATUS_MASK_CHECK) != DHT20_STATUS_MASK_CHECK) { + /* + * According to datasheet 7.4 + * Reset register 0x1B, 0x1C and 0x1E if status does not match expected value + */ + rc = reset_register(dev, DHT20_RESET_REGISTER_0); + if (rc < 0) { + return rc; + } + rc = reset_register(dev, DHT20_RESET_REGISTER_1); + if (rc < 0) { + return rc; + } + rc = reset_register(dev, DHT20_RESET_REGISTER_2); + if (rc < 0) { + return rc; + } + /* Wait 10ms after reset sequence */ + k_msleep(DHT20_RESET_SEQUENCE_WAIT_MS); + } + + return 0; +} + +static int dht20_read_sample(const struct device *dev, uint32_t *t_sample, uint32_t *rh_sample) +{ + const struct dht20_config *cfg = dev->config; + /* + * Datasheet shows content of the measurement data as follow + * + * +------+----------------------------------------+ + * | Byte | Content | + * +------+----------------------------------------+ + * | 0 | State | + * | 1 | Humidity | + * | 2 | Humidity | + * | 3 | Humidity (4 MSb) | Temperature (4 LSb) | + * | 4 | Temperature | + * | 5 | Temperature | + * | 6 | CRC | + * +------+----------------------------------------+ + */ + uint8_t rx_buf[DHT20_MEASUREMENT_BUFFER_LENGTH]; + int rc; + uint8_t status; + + rc = i2c_read_dt(&cfg->bus, rx_buf, sizeof(rx_buf)); + if (rc < 0) { + LOG_ERR("Failed to read data from device."); + return rc; + } + + status = rx_buf[0]; + /* Extract 20 bits for humidity data */ + *rh_sample = sys_get_be24(&rx_buf[1]) >> 4; + /* Extract 20 bits for temperature data */ + *t_sample = sys_get_be24(&rx_buf[3]) & 0x0FFFFF; + +#if defined(CONFIG_DHT20_CRC) + /* Compute and check CRC with last byte of measurement data */ + crc = crc8(rx_buf, 6, DHT20_CRC_POLYNOM, 0xFF, false); + + if (crc != rx_buf[6]) { + rc = -EIO; + } +#endif + + return rc; +} + +static int dht20_sample_fetch(const struct device *dev, enum sensor_channel chan) +{ + struct dht20_data *data = dev->data; + const struct dht20_config *cfg = dev->config; + int rc; + uint8_t tx_buf[DHT20_TRIGGER_MEASUREMENT_BUFFER_LENGTH] = { + DHT20_TRIGGER_MEASUREMENT_COMMAND}; + uint8_t status; + + if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_AMBIENT_TEMP && + chan != SENSOR_CHAN_HUMIDITY) { + return -ENOTSUP; + } + + /* Reset sensor if needed */ + reset_sensor(dev); + + /* Send trigger measurement command */ + rc = i2c_write_dt(&cfg->bus, tx_buf, sizeof(tx_buf)); + if (rc < 0) { + LOG_ERR("Failed to start measurement."); + return rc; + } + + /* + * According to datasheet maximum time to make temperature and humidity + * measurements is 80ms + */ + k_msleep(DHT20_POWER_ON_WAIT_MS); + + do { + k_msleep(DHT20_INIT_POLL_STATUS_WAIT_MS); + + rc = read_status(dev, &status); + if (rc < 0) { + LOG_ERR("Failed to read status."); + return rc; + } + } while ((status & DHT20_STATUS_MASK_POLL_STATE) != 0); + + rc = dht20_read_sample(dev, &data->t_sample, &data->rh_sample); + if (rc < 0) { + LOG_ERR("Failed to fetch data."); + return rc; + } + + return 0; +} + +static void dht20_temp_convert(struct sensor_value *val, uint32_t raw) +{ + int32_t micro_c; + + /* + * Convert to micro Celsius + * DegCT = (S / 2^20) * 200 - 50 + * uDegCT = (S * 1e6 * 200 - 50 * 1e6) / (1 << 20) + */ + micro_c = ((int64_t)raw * 1000000 * 200) / BIT(20) - 50 * 1000000; + + val->val1 = micro_c / 1000000; + val->val2 = micro_c % 1000000; +} + +static void dht20_rh_convert(struct sensor_value *val, uint32_t raw) +{ + int32_t micro_rh; + + /* + * Convert to micro %RH + * %RH = (S / 2^20) * 100% + * u%RH = (S * 1e6 * 100) / (1 << 20) + */ + micro_rh = ((uint64_t)raw * 1000000 * 100) / BIT(20); + + val->val1 = micro_rh / 1000000; + val->val2 = micro_rh % 1000000; +} + +static int dht20_channel_get(const struct device *dev, enum sensor_channel chan, + struct sensor_value *val) +{ + const struct dht20_data *data = dev->data; + + if (chan == SENSOR_CHAN_AMBIENT_TEMP) { + dht20_temp_convert(val, data->t_sample); + } else if (chan == SENSOR_CHAN_HUMIDITY) { + dht20_rh_convert(val, data->rh_sample); + } else { + return -ENOTSUP; + } + + return 0; +} + +static int dht20_init(const struct device *dev) +{ + const struct dht20_config *cfg = dev->config; + + if (!i2c_is_ready_dt(&cfg->bus)) { + LOG_ERR("I2C dev %s not ready", cfg->bus.bus->name); + return -ENODEV; + } + + return 0; +} + +static const struct sensor_driver_api dht20_driver_api = {.sample_fetch = dht20_sample_fetch, + .channel_get = dht20_channel_get}; + +#define DT_DRV_COMPAT aosong_dht20 +#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) + +#define DEFINE_DHT20(n) \ + static struct dht20_data dht20_data_##n; \ + \ + static const struct dht20_config dht20_config_##n = {.bus = I2C_DT_SPEC_INST_GET(n)}; \ + \ + SENSOR_DEVICE_DT_INST_DEFINE(n, dht20_init, NULL, &dht20_data_##n, &dht20_config_##n, \ + POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &dht20_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(DEFINE_DHT20) + +#endif +#undef DT_DRV_COMPAT + +#define DT_DRV_COMPAT aosong_aht20 +#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) + +#define DEFINE_AHT20(n) \ + static struct dht20_data aht20_data_##n; \ + \ + static const struct dht20_config aht20_config_##n = {.bus = I2C_DT_SPEC_INST_GET(n)}; \ + \ + SENSOR_DEVICE_DT_INST_DEFINE(n, dht20_init, NULL, &aht20_data_##n, &aht20_config_##n, \ + POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &dht20_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(DEFINE_AHT20) + +#endif +#undef DT_DRV_COMPAT + +#define DT_DRV_COMPAT aosong_am2301b +#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) + +#define DEFINE_AM2301B(n) \ + static struct dht20_data am2301b_data_##n; \ + \ + static const struct dht20_config am2301b_config_##n = {.bus = I2C_DT_SPEC_INST_GET(n)}; \ + \ + SENSOR_DEVICE_DT_INST_DEFINE(n, dht20_init, NULL, &am2301b_data_##n, &am2301b_config_##n, \ + POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &dht20_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(DEFINE_AM2301B) + +#endif +#undef DT_DRV_COMPAT diff --git a/dts/bindings/sensor/aosong,aht20.yaml b/dts/bindings/sensor/aosong,aht20.yaml new file mode 100644 index 00000000000..1ee8eca48cf --- /dev/null +++ b/dts/bindings/sensor/aosong,aht20.yaml @@ -0,0 +1,14 @@ +# +# Copyright (c) 2024 Nathan Olff +# +# SPDX-License-Identifier: Apache-2.0 + +description: | + Aosong AHT20 (Digital-output Humidity and Temperature Sensor) + + The Asosong AHT20 sensor provides temperature and humidity + measurements through an I2C bus. + +compatible: "aosong,aht20" + +include: [sensor-device.yaml, i2c-device.yaml] diff --git a/dts/bindings/sensor/aosong,am2301b.yaml b/dts/bindings/sensor/aosong,am2301b.yaml new file mode 100644 index 00000000000..702362a1ea3 --- /dev/null +++ b/dts/bindings/sensor/aosong,am2301b.yaml @@ -0,0 +1,14 @@ +# +# Copyright (c) 2024 Nathan Olff +# +# SPDX-License-Identifier: Apache-2.0 + +description: | + Aosong AM2301B (Digital-output Humidity and Temperature Sensor) + + The Asosong AM2301B sensor provides temperature and humidity + measurements through an I2C bus. + +compatible: "aosong,am2301b" + +include: [sensor-device.yaml, i2c-device.yaml] diff --git a/dts/bindings/sensor/aosong,dht20.yaml b/dts/bindings/sensor/aosong,dht20.yaml new file mode 100644 index 00000000000..8cf0534ba90 --- /dev/null +++ b/dts/bindings/sensor/aosong,dht20.yaml @@ -0,0 +1,14 @@ +# +# Copyright (c) 2024 Nathan Olff +# +# SPDX-License-Identifier: Apache-2.0 + +description: | + Aosong DHT20 (Digital-output Humidity and Temperature Sensor) + + The Asosong DHT20 sensor provides temperature and humidity + measurements through an I2C bus. + +compatible: "aosong,dht20" + +include: [sensor-device.yaml, i2c-device.yaml] diff --git a/tests/drivers/build_all/sensor/i2c.dtsi b/tests/drivers/build_all/sensor/i2c.dtsi index a7948313291..a51a525fd6f 100644 --- a/tests/drivers/build_all/sensor/i2c.dtsi +++ b/tests/drivers/build_all/sensor/i2c.dtsi @@ -993,3 +993,21 @@ test_i2c_stts22h: stts22h@86 { int-gpios = <&test_gpio 0 0>; sampling-rate = ; }; + +test_i2c_dht20: dht20@87 { + compatible = "aosong,dht20"; + reg = <0x87>; + status = "okay"; +}; + +test_i2c_aht20: aht20@88 { + compatible = "aosong,aht20"; + reg = <0x88>; + status = "okay"; +}; + +test_i2c_am2301b: am2301b@89 { + compatible = "aosong,am2301b"; + reg = <0x89>; + status = "okay"; +}; From 5cf6133dae62fbcc16b911a3d6e7a2ad264c43c6 Mon Sep 17 00:00:00 2001 From: Ioannis Karachalios Date: Wed, 13 Mar 2024 20:09:50 +0200 Subject: [PATCH 1497/2402] boards: renesas: smartbond: Update display settings This commit should fix configuration conflicts that came up upon merging both MIPI DBI and display panel drivers. 1. Board's display/LVGL Kconfigs should be enabled when needed based on the selected display interface. 2. Overwrite the touch controller's I2C pins to avoid conflicts with the display panel signals. Signed-off-by: Ioannis Karachalios --- boards/renesas/da1469x_dk_pro/Kconfig.defconfig | 6 +++--- .../da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay | 10 ++++++++++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/boards/renesas/da1469x_dk_pro/Kconfig.defconfig b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig index c0f49a23a2e..9c447539c3b 100644 --- a/boards/renesas/da1469x_dk_pro/Kconfig.defconfig +++ b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig @@ -12,15 +12,15 @@ config LV_Z_BITS_PER_PIXEL # LCDC imposes display buffer's stride be word aligned config LV_Z_AREA_X_ALIGNMENT_WIDTH - default 2 + default 2 if MIPI_DBI_SMARTBOND config LV_Z_FLUSH_THREAD - default y + default y if DISPLAY_RENESAS_LCDC # Use double buffering to avoid visual artifacts as long as # the DMA is copying data into driver's frame buffer. config LV_Z_DOUBLE_VDB - default y + default y if DISPLAY_RENESAS_LCDC endif # LVGL diff --git a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay index afdfb061c05..c147201adc4 100644 --- a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay +++ b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay @@ -23,6 +23,16 @@ status = "okay"; }; +&pinctrl { + i2c2_default: i2c2_default { + group1 { + pinmux = , + ; + bias-pull-up; + }; + }; +}; + &i2c2 { clock-frequency = <400000>; From 9eef10d436b15856cbf08c8dbd0e03986e7b95f9 Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Mon, 18 Mar 2024 09:47:31 +0100 Subject: [PATCH 1498/2402] net: ethernet: add definition for mac address length Add a define for the mac address length, to be used as needed in place of hardcoded 6. Signed-off-by: Angelo Dureghello --- include/zephyr/net/ethernet.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/zephyr/net/ethernet.h b/include/zephyr/net/ethernet.h index 0fb7c43c8ef..024eb108df2 100644 --- a/include/zephyr/net/ethernet.h +++ b/include/zephyr/net/ethernet.h @@ -49,10 +49,12 @@ extern "C" { * @{ */ +#define NET_ETH_ADDR_LEN 6U + /** @cond INTERNAL_HIDDEN */ struct net_eth_addr { - uint8_t addr[6]; + uint8_t addr[NET_ETH_ADDR_LEN]; }; #define NET_ETH_HDR(pkt) ((struct net_eth_hdr *)net_pkt_data(pkt)) From dd8072abb39b91b3019a7217578f06a8ede2cba2 Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Wed, 13 Mar 2024 09:00:45 +0100 Subject: [PATCH 1499/2402] drivers: ethernet: eth_adin2111: adjust multicast filter Multicast rule as 01:00:00:00:00:00 is actually shadowing broadcast rule, enabling broadcast packets to be received/forwarded even if broadcast rule/filter is not set. Set the multicast filter with an appropriate mask. Signed-off-by: Angelo Dureghello --- drivers/ethernet/eth_adin2111.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index eaa1fb1ea99..a27be902a5a 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -935,13 +935,14 @@ static int adin2111_filter_multicast(const struct device *dev) { const struct adin2111_config *cfg = dev->config; bool is_adin2111 = (cfg->id == ADIN2111_MAC); - uint8_t mm[6] = {BIT(0), 0U, 0U, 0U, 0U, 0U}; + uint8_t mm[6] = {BIT(0), 0U, 0U, 0U, 0U, 0U}; + uint8_t mmask[6] = {0xFFU, 0U, 0U, 0U, 0U, 0U}; uint32_t rules = ADIN2111_ADDR_APPLY2PORT1 | (is_adin2111 ? ADIN2111_ADDR_APPLY2PORT2 : 0) | ADIN2111_ADDR_TO_HOST | ADIN2111_ADDR_TO_OTHER_PORT; - return adin2111_write_filter_address(dev, mm, mm, rules, + return adin2111_write_filter_address(dev, mm, mmask, rules, ADIN2111_MULTICAST_ADDR_SLOT); } From 2cebc0f307ec75d98781e1f4bd0319e5367d0add Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Fri, 15 Mar 2024 13:11:15 +0100 Subject: [PATCH 1500/2402] drivers: ethernet: eth_adin2111: extend api support Extend api support with new functionalities. Signed-off-by: Angelo Dureghello --- drivers/ethernet/eth_adin2111.c | 199 +++++++++++++++++- drivers/ethernet/eth_adin2111_priv.h | 14 ++ .../zephyr/drivers/ethernet/eth_adin2111.h | 70 ++++++ 3 files changed, 272 insertions(+), 11 deletions(-) diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index a27be902a5a..b830ebd4849 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -48,11 +48,71 @@ LOG_MODULE_REGISTER(eth_adin2111, CONFIG_ETHERNET_LOG_LEVEL); #define ADIN2111_UNICAST_P1_ADDR_SLOT 2U /* MAC Address Rule and DA Filter Port 2 slot/idx */ #define ADIN2111_UNICAST_P2_ADDR_SLOT 3U +/* Free slots for further filtering */ +#define ADIN2111_FILTER_FIRST_SLOT 4U +#define ADIN2111_FILTER_SLOTS 16U + /* As per RM rev. A table 3, t3 >= 50ms, delay for SPI interface to be ready */ #define ADIN2111_SPI_ACTIVE_DELAY_MS 50U -/* As per RM rev. A page 20: approximately 10 ms (maximum) for internal logic to be ready */ +/* As per RM rev. A page 20: approximately 10 ms (maximum) for internal logic to be ready. */ #define ADIN2111_SW_RESET_DELAY_MS 10U +int eth_adin2111_mac_reset(const struct device *dev) +{ + uint32_t val; + int ret; + + ret = eth_adin2111_reg_write(dev, ADIN2111_SOFT_RST_REG, ADIN2111_SWRESET_KEY1); + if (ret < 0) { + return ret; + } + ret = eth_adin2111_reg_write(dev, ADIN2111_SOFT_RST_REG, ADIN2111_SWRESET_KEY2); + if (ret < 0) { + return ret; + } + ret = eth_adin2111_reg_write(dev, ADIN2111_SOFT_RST_REG, ADIN2111_SWRELEASE_KEY1); + if (ret < 0) { + return ret; + } + ret = eth_adin2111_reg_write(dev, ADIN2111_SOFT_RST_REG, ADIN2111_SWRELEASE_KEY2); + if (ret < 0) { + return ret; + } + ret = eth_adin2111_reg_read(dev, ADIN1110_MAC_RST_STATUS_REG, &val); + if (ret < 0) { + return ret; + } + if (val == 0) { + return -EBUSY; + } + + return 0; +} + +int eth_adin2111_reg_update(const struct device *dev, const uint16_t reg, + uint32_t mask, uint32_t data) +{ + uint32_t val; + int ret; + + ret = eth_adin2111_reg_read(dev, reg, &val); + if (ret < 0) { + return ret; + } + + val &= ~mask; + val |= mask & data; + + return eth_adin2111_reg_write(dev, reg, val); +} + +struct net_if *eth_adin2111_get_iface(const struct device *dev, const uint16_t port_idx) +{ + struct adin2111_data *ctx = dev->data; + + return ((struct adin2111_port_data *)ctx->port[port_idx]->data)->iface; +} + int eth_adin2111_lock(const struct device *dev, k_timeout_t timeout) { struct adin2111_data *ctx = dev->data; @@ -972,6 +1032,97 @@ static int adin2111_filter_unicast(const struct device *dev, uint8_t *addr, return adin2111_write_filter_address(dev, addr, NULL, rules, slot); } +int eth_adin2111_broadcast_filter(const struct device *dev, bool enable) +{ + if (!enable) { + /* Clean up */ + uint8_t mac[NET_ETH_ADDR_LEN] = {0}; + + return adin2111_write_filter_address(dev, mac, mac, 0, + ADIN2111_BROADCAST_ADDR_SLOT); + } + + return adin2111_filter_broadcast(dev); +} + +/* + * Check if a filter exists already. + */ +static int eth_adin2111_find_filter(const struct device *dev, uint8_t *mac, const uint16_t port_idx) +{ + int i, offset, reg, ret; + + for (i = ADIN2111_FILTER_FIRST_SLOT; i < ADIN2111_FILTER_SLOTS; i++) { + offset = i << 1; + ret = eth_adin2111_reg_read(dev, ADIN2111_ADDR_FILT_UPR + offset, ®); + if (ret < 0) { + return ret; + } + if ((reg & UINT16_MAX) == sys_get_be16(&mac[0])) { + if ((port_idx == 0 && !(reg & ADIN2111_ADDR_APPLY2PORT1)) || + (port_idx == 1 && !(reg & ADIN2111_ADDR_APPLY2PORT2))) + continue; + + ret = eth_adin2111_reg_read(dev, ADIN2111_ADDR_FILT_LWR + offset, ®); + if (ret < 0) { + return ret; + } + if (reg == sys_get_be32(&mac[2])) { + return i; + } + } + } + + return -ENOENT; +} + +static int eth_adin2111_set_mac_filter(const struct device *dev, uint8_t *mac, + const uint16_t port_idx) +{ + int i, ret, offset; + uint32_t reg; + + ret = eth_adin2111_find_filter(dev, mac, port_idx); + if (ret >= 0) { + LOG_WRN("MAC filter already set at pos %d, not setting it.", ret); + return ret; + } + if (ret != -ENOENT) { + return ret; + } + + for (i = ADIN2111_FILTER_FIRST_SLOT; i < ADIN2111_FILTER_SLOTS; i++) { + offset = i << 1; + ret = eth_adin2111_reg_read(dev, ADIN2111_ADDR_FILT_UPR + offset, ®); + if (ret < 0) { + return ret; + } + if (reg == 0) { + uint32_t rules = (port_idx == 0 ? ADIN2111_ADDR_APPLY2PORT1 + : ADIN2111_ADDR_APPLY2PORT2) + | ADIN2111_ADDR_TO_HOST; + + return adin2111_write_filter_address(dev, mac, NULL, rules, i); + } + } + + return -ENOSPC; +} + +static int eth_adin2111_clear_mac_filter(const struct device *dev, uint8_t *mac, + const uint16_t port_idx) +{ + int i; + uint8_t cmac[NET_ETH_ADDR_LEN] = {0}; + + i = eth_adin2111_find_filter(dev, mac, port_idx); + if (i < 0) { + return i; + } + + return adin2111_write_filter_address(dev, cmac, cmac, 0, i); +} + static void adin2111_port_iface_init(struct net_if *iface) { const struct device *dev = net_if_get_device(iface); @@ -1044,7 +1195,8 @@ static void adin2111_port_iface_init(struct net_if *iface) static enum ethernet_hw_caps adin2111_port_get_capabilities(const struct device *dev) { ARG_UNUSED(dev); - return ETHERNET_LINK_10BASE_T + return ETHERNET_LINK_10BASE_T | + ETHERNET_HW_FILTERING #if defined(CONFIG_NET_LLDP) | ETHERNET_LLDP #endif @@ -1075,6 +1227,19 @@ static int adin2111_port_set_config(const struct device *dev, NET_LINK_ETHERNET); } + if (type == ETHERNET_CONFIG_TYPE_FILTER) { + /* Filtering for DA only */ + if (config->filter.type & ETHERNET_FILTER_TYPE_DST_MAC_ADDRESS) { + uint8_t *mac = (uint8_t *)config->filter.mac_address.addr; + + if (config->filter.set) { + ret = eth_adin2111_set_mac_filter(adin, mac, cfg->port_idx); + } else { + ret = eth_adin2111_clear_mac_filter(adin, mac, cfg->port_idx); + } + } + } + end_unlock: (void)eth_adin2111_unlock(adin); return ret; @@ -1141,6 +1306,26 @@ static int adin2111_await_device(const struct device *dev) return ret; } +int eth_adin2111_sw_reset(const struct device *dev, uint16_t delay) +{ + int ret; + + ret = eth_adin2111_reg_write(dev, ADIN2111_RESET, ADIN2111_RESET_SWRESET); + if (ret < 0) { + return ret; + } + + k_msleep(delay); + + ret = adin2111_await_device(dev); + if (ret < 0) { + LOG_ERR("ADIN did't come out of the reset, %d", ret); + return ret; + } + + return ret; +} + static int adin2111_init(const struct device *dev) { const struct adin2111_config *cfg = dev->config; @@ -1210,20 +1395,12 @@ static int adin2111_init(const struct device *dev) } /* perform MACPHY soft reset */ - ret = eth_adin2111_reg_write(dev, ADIN2111_RESET, ADIN2111_RESET_SWRESET); + ret = eth_adin2111_sw_reset(dev, ADIN2111_SW_RESET_DELAY_MS); if (ret < 0) { LOG_ERR("MACPHY software reset failed, %d", ret); return ret; } - k_msleep(ADIN2111_SW_RESET_DELAY_MS); - - ret = adin2111_await_device(dev); - if (ret < 0) { - LOG_ERR("ADIN did't come out of the reset, %d", ret); - return ret; - } - /* CONFIG 0 */ /* disable Frame Check Sequence validation on the host */ /* if that is enabled, then CONFIG_ETH_ADIN2111_SPI_CFG0 must be off */ diff --git a/drivers/ethernet/eth_adin2111_priv.h b/drivers/ethernet/eth_adin2111_priv.h index dd042cab756..14219ad1280 100644 --- a/drivers/ethernet/eth_adin2111_priv.h +++ b/drivers/ethernet/eth_adin2111_priv.h @@ -48,10 +48,14 @@ #define ADIN2111_CONFIG2_P2_FWD_UNK2P1 BIT(14) /* Forward Frames from Port 1 Not Matching a MAC Address to Port 2 */ #define ADIN2111_CONFIG2_P1_FWD_UNK2P2 BIT(13) +/* Forward Frames Not Matching Any MAC Address to the Host */ +#define ADIN2111_CONFIG2_P2_FWD_UNK2HOST BIT(12) /* Enable Cut Through from Port to Port */ #define ADIN2111_CONFIG2_PORT_CUT_THRU_EN BIT(11) /* Enable CRC Append */ #define ADIN2111_CONFIG2_CRC_APPEND BIT(5) +/* Forward Frames Not Matching Any MAC Address to the Host */ +#define ADIN2111_CONFIG2_P1_FWD_UNK2HOST BIT(2) /* Status Register 0 */ #define ADIN2111_STATUS0 0x08U @@ -136,6 +140,16 @@ /* P2 MAC Receive Register */ #define ADIN2111_P2_RX 0xC1U +/* MAC reset status */ +#define ADIN1110_MAC_RST_STATUS_REG 0x3BU + +/* MAC reset */ +#define ADIN2111_SOFT_RST_REG 0x3CU +#define ADIN2111_SWRESET_KEY1 0x4F1CU +#define ADIN2111_SWRESET_KEY2 0xC1F4U +#define ADIN2111_SWRELEASE_KEY1 0x6F1AU +#define ADIN2111_SWRELEASE_KEY2 0xA1F6U + /* SPI header size in bytes */ #define ADIN2111_SPI_HEADER_SIZE 2U /* SPI header size for write transaction */ diff --git a/include/zephyr/drivers/ethernet/eth_adin2111.h b/include/zephyr/drivers/ethernet/eth_adin2111.h index 3756add8bd3..3f3947dc177 100644 --- a/include/zephyr/drivers/ethernet/eth_adin2111.h +++ b/include/zephyr/drivers/ethernet/eth_adin2111.h @@ -70,6 +70,76 @@ int eth_adin2111_reg_write(const struct device *dev, const uint16_t reg, uint32_ */ int eth_adin2111_reg_read(const struct device *dev, const uint16_t reg, uint32_t *val); +/** + * @brief Update host MAC interface register over SPI + * + * @note The caller is responsible for device lock. + * Shall not be called from ISR. + * + * @param[in] dev ADIN2111 device. + * @param reg Register address. + * @param mask Bitmask for bits that may be modified. + * @param data Data to apply in the masked range. + * + * @retval 0 Successful write. + * @retval <0 Error, a negative errno code. + */ +int eth_adin2111_reg_update(const struct device *dev, const uint16_t reg, + uint32_t mask, uint32_t data); + +/** + * @brief Reset both the MAC and PHY. + * + * @param[in] dev ADIN2111 device. + * @param delay Delay in milliseconds. + * + * @note The caller is responsible for device lock. + * Shall not be called from ISR. + * + * @retval 0 Successful write. + * @retval <0 Error, a negative errno code. + */ +int eth_adin2111_sw_reset(const struct device *dev, uint16_t delay); + +/** + * @brief Reset the MAC device. Note that PHY 1 must be out of software power-down for the MAC + * subsystem reset to take effect. + * + * @note The caller is responsible for device lock. + * Shall not be called from ISR. + * + * @param[in] dev ADIN2111 device. + * + * @retval 0 Successful write. + * @retval <0 Error, a negative errno code. + */ +int eth_adin2111_mac_reset(const struct device *dev); + +/** + * @brief Enable/disable the forwarding (to host) of broadcast frames. Frames who's DA + * doesn't match are dropped. + * + * @note The caller is responsible for device lock. + * Shall not be called from ISR. + * + * @param[in] dev ADIN2111 device. + * @param enable Set to 0 to disable and to nonzero to enable. + * + * @retval 0 Successful write. + * @retval <0 Error, a negative errno code. + */ +int eth_adin2111_broadcast_filter(const struct device *dev, bool enable); + +/** + * @brief Get the port-related net_if reference. + * + * @param[in] dev ADIN2111 device. + * @param port_idx Port index. + * + * @retval a struct net_if pointer, or NULL on error. + */ +struct net_if *eth_adin2111_get_iface(const struct device *dev, const uint16_t port_idx); + #ifdef __cplusplus } #endif From 569ebc247a7be798c157f153c93bd8dd31bbe6d3 Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Fri, 15 Mar 2024 13:15:14 +0100 Subject: [PATCH 1501/2402] drivers: ethernet: eth_adin2111: enable promiscuous mode Add promiscuous mode support. Signed-off-by: Angelo Dureghello --- drivers/ethernet/eth_adin2111.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index b830ebd4849..4dd56f74385 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -1123,6 +1123,24 @@ static int eth_adin2111_clear_mac_filter(const struct device *dev, uint8_t *mac, return adin2111_write_filter_address(dev, cmac, cmac, 0, i); } +#if defined(CONFIG_NET_PROMISCUOUS_MODE) +static int eth_adin2111_set_promiscuous(const struct device *dev, const uint16_t port_idx, + bool enable) +{ + const struct adin2111_config *cfg = dev->config; + bool is_adin2111 = (cfg->id == ADIN2111_MAC); + uint32_t fwd_mask; + + if ((!is_adin2111 && port_idx > 0) || (is_adin2111 && port_idx > 1)) { + return -EINVAL; + } + + fwd_mask = port_idx ? ADIN2111_CONFIG2_P2_FWD_UNK2HOST : ADIN2111_CONFIG2_P1_FWD_UNK2HOST; + + return eth_adin2111_reg_update(dev, ADIN2111_CONFIG2, fwd_mask, enable ? fwd_mask : 0); +} +#endif + static void adin2111_port_iface_init(struct net_if *iface) { const struct device *dev = net_if_get_device(iface); @@ -1200,7 +1218,7 @@ static enum ethernet_hw_caps adin2111_port_get_capabilities(const struct device #if defined(CONFIG_NET_LLDP) | ETHERNET_LLDP #endif - ; + | ETHERNET_PROMISC_MODE; } static int adin2111_port_set_config(const struct device *dev, @@ -1240,6 +1258,12 @@ static int adin2111_port_set_config(const struct device *dev, } } +#if defined(CONFIG_NET_PROMISCUOUS_MODE) + if (type == ETHERNET_CONFIG_TYPE_PROMISC_MODE) { + ret = eth_adin2111_set_promiscuous(adin, cfg->port_idx, config->promisc_mode); + } +#endif + end_unlock: (void)eth_adin2111_unlock(adin); return ret; From 180c423c80c1db7bf0497d89a2eb9216339c90fb Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Wed, 20 Mar 2024 11:35:35 +0100 Subject: [PATCH 1502/2402] drivers: ethernet: eth_adin2111: fix port to port_idx Fix all references of port to port_idx to be uniform. Signed-off-by: Angelo Dureghello --- drivers/ethernet/eth_adin2111.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index 4dd56f74385..8dbe65da88d 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -247,10 +247,10 @@ static int eth_adin2111_reg_write_oa(const struct device *dev, const uint16_t re return 0; } -int eth_adin2111_oa_data_read(const struct device *dev, int port) +int eth_adin2111_oa_data_read(const struct device *dev, const uint16_t port_idx) { struct adin2111_data *ctx = dev->data; - struct net_if *iface = ((struct adin2111_port_data *)ctx->port[port]->data)->iface; + struct net_if *iface = ((struct adin2111_port_data *)ctx->port[port_idx]->data)->iface; struct net_pkt *pkt; uint32_t hdr, ftr; int i, len, rx_pos, ret, rca, swo; @@ -330,7 +330,7 @@ int eth_adin2111_oa_data_read(const struct device *dev, int port) if (ret < 0) { net_pkt_unref(pkt); LOG_ERR("Port %u failed to enqueue frame to RX queue, %d", - port, ret); + port_idx, ret); return ret; } } @@ -344,7 +344,8 @@ int eth_adin2111_oa_data_read(const struct device *dev, int port) /* * Setting up for a single dma transfer. */ -static int eth_adin2111_send_oa_frame(const struct device *dev, struct net_pkt *pkt, int port) +static int eth_adin2111_send_oa_frame(const struct device *dev, struct net_pkt *pkt, + const uint16_t port_idx) { struct adin2111_data *ctx = dev->data; uint16_t clen, len = net_pkt_get_len(pkt); @@ -373,7 +374,7 @@ static int eth_adin2111_send_oa_frame(const struct device *dev, struct net_pkt * for (i = 1, cur = 0; i <= chunks; i++) { hdr = ADIN2111_OA_DATA_HDR_DNC | ADIN2111_OA_DATA_HDR_DV | ADIN2111_OA_DATA_HDR_NORX; - hdr |= (!!port << ADIN2111_OA_DATA_HDR_VS); + hdr |= (!!port_idx << ADIN2111_OA_DATA_HDR_VS); if (i == 1) { hdr |= ADIN2111_OA_DATA_HDR_SV; } @@ -526,14 +527,14 @@ int eth_adin2111_reg_write(const struct device *dev, const uint16_t reg, return rval; } -static int adin2111_read_fifo(const struct device *dev, const uint8_t port) +static int adin2111_read_fifo(const struct device *dev, const uint16_t port_idx) { const struct adin2111_config *cfg = dev->config; struct adin2111_data *ctx = dev->data; struct net_if *iface; struct net_pkt *pkt; - uint16_t fsize_reg = ((port == 0U) ? ADIN2111_P1_RX_FSIZE : ADIN2111_P2_RX_FSIZE); - uint16_t rx_reg = ((port == 0U) ? ADIN2111_P1_RX : ADIN2111_P2_RX); + uint16_t fsize_reg = ((port_idx == 0U) ? ADIN2111_P1_RX_FSIZE : ADIN2111_P2_RX_FSIZE); + uint16_t rx_reg = ((port_idx == 0U) ? ADIN2111_P1_RX : ADIN2111_P2_RX); uint32_t fsize; uint32_t fsize_real; uint32_t padding_len; @@ -544,13 +545,13 @@ static int adin2111_read_fifo(const struct device *dev, const uint8_t port) #endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */ int ret; - iface = ((struct adin2111_port_data *)ctx->port[port]->data)->iface; + iface = ((struct adin2111_port_data *)ctx->port[port_idx]->data)->iface; /* get received frame size in bytes */ ret = eth_adin2111_reg_read(dev, fsize_reg, &fsize); if (ret < 0) { eth_stats_update_errors_rx(iface); - LOG_ERR("Port %u failed to read RX FSIZE, %d", port, ret); + LOG_ERR("Port %u failed to read RX FSIZE, %d", port_idx, ret); return ret; } @@ -585,7 +586,7 @@ static int adin2111_read_fifo(const struct device *dev, const uint8_t port) ret = spi_transceive_dt(&cfg->spi, &tx, &rx); if (ret < 0) { eth_stats_update_errors_rx(iface); - LOG_ERR("Port %u failed to read RX FIFO, %d", port, ret); + LOG_ERR("Port %u failed to read RX FIFO, %d", port_idx, ret); return ret; } @@ -594,7 +595,7 @@ static int adin2111_read_fifo(const struct device *dev, const uint8_t port) if (!pkt) { eth_stats_update_errors_rx(iface); LOG_ERR("Port %u failed to alloc frame RX buffer, %u bytes", - port, fsize_real); + port_idx, fsize_real); return -ENOMEM; } @@ -602,7 +603,7 @@ static int adin2111_read_fifo(const struct device *dev, const uint8_t port) if (ret < 0) { eth_stats_update_errors_rx(iface); net_pkt_unref(pkt); - LOG_ERR("Port %u failed to fill RX frame, %d", port, ret); + LOG_ERR("Port %u failed to fill RX frame, %d", port_idx, ret); return ret; } @@ -611,7 +612,7 @@ static int adin2111_read_fifo(const struct device *dev, const uint8_t port) eth_stats_update_errors_rx(iface); net_pkt_unref(pkt); LOG_ERR("Port %u failed to enqueue frame to RX queue, %d", - port, ret); + port_idx, ret); return ret; } @@ -1021,7 +1022,7 @@ static int adin2111_filter_broadcast(const struct device *dev) } static int adin2111_filter_unicast(const struct device *dev, uint8_t *addr, - uint8_t port_idx) + const uint16_t port_idx) { uint32_t rules = (port_idx == 0 ? ADIN2111_ADDR_APPLY2PORT1 : ADIN2111_ADDR_APPLY2PORT2) From e0a1e692622d5df883ac864f9f07530c1bd2b7e7 Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Wed, 20 Mar 2024 13:19:02 +0100 Subject: [PATCH 1503/2402] drivers: ethernet: eth_adin2111: use NET_ETH_ADDR_LEN Use new NET_ETH_ADDR_LEN definition. Signed-off-by: Angelo Dureghello --- drivers/ethernet/eth_adin2111.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c index 8dbe65da88d..b4730fddc26 100644 --- a/drivers/ethernet/eth_adin2111.c +++ b/drivers/ethernet/eth_adin2111.c @@ -996,8 +996,8 @@ static int adin2111_filter_multicast(const struct device *dev) { const struct adin2111_config *cfg = dev->config; bool is_adin2111 = (cfg->id == ADIN2111_MAC); - uint8_t mm[6] = {BIT(0), 0U, 0U, 0U, 0U, 0U}; - uint8_t mmask[6] = {0xFFU, 0U, 0U, 0U, 0U, 0U}; + uint8_t mm[NET_ETH_ADDR_LEN] = {BIT(0), 0U, 0U, 0U, 0U, 0U}; + uint8_t mmask[NET_ETH_ADDR_LEN] = {0xFFU, 0U, 0U, 0U, 0U, 0U}; uint32_t rules = ADIN2111_ADDR_APPLY2PORT1 | (is_adin2111 ? ADIN2111_ADDR_APPLY2PORT2 : 0) | ADIN2111_ADDR_TO_HOST | @@ -1011,7 +1011,7 @@ static int adin2111_filter_broadcast(const struct device *dev) { const struct adin2111_config *cfg = dev->config; bool is_adin2111 = (cfg->id == ADIN2111_MAC); - uint8_t mac[] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU}; + uint8_t mac[NET_ETH_ADDR_LEN] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU}; uint32_t rules = ADIN2111_ADDR_APPLY2PORT1 | (is_adin2111 ? ADIN2111_ADDR_APPLY2PORT2 : 0) | ADIN2111_ADDR_TO_HOST | From fff833eda44b2f3170410258318695bcade21688 Mon Sep 17 00:00:00 2001 From: Kamil Paszkiet Date: Thu, 21 Mar 2024 08:28:13 +0100 Subject: [PATCH 1504/2402] scripts: tests: Blackbox test expansion - filter Adds tests related to filter flags: --arch --vendor Signed-off-by: Kamil Paszkiet --- .../tests/no_filter/dummy/CMakeLists.txt | 8 ++ .../test_data/tests/no_filter/dummy/prj.conf | 1 + .../tests/no_filter/dummy/src/main.c | 26 ++++ .../tests/no_filter/dummy/test_data.yaml | 3 + scripts/tests/twister_blackbox/test_filter.py | 126 ++++++++++++++++++ 5 files changed, 164 insertions(+) create mode 100644 scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/CMakeLists.txt create mode 100644 scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/prj.conf create mode 100644 scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/src/main.c create mode 100644 scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/test_data.yaml diff --git a/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/CMakeLists.txt b/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/CMakeLists.txt new file mode 100644 index 00000000000..635c696edf9 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(integration) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/prj.conf new file mode 100644 index 00000000000..9467c292689 --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/src/main.c b/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/src/main.c new file mode 100644 index 00000000000..a2b7268225b --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/src/main.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + + +ZTEST_SUITE(a1_1_tests, NULL, NULL, NULL, NULL, NULL); + +/** + * @brief Test Asserts + * + * This test verifies various assert macros provided by ztest. + * + */ +ZTEST(a1_1_tests, test_assert) +{ + zassert_true(1, "1 was false"); + zassert_false(0, "0 was true"); + zassert_is_null(NULL, "NULL was not NULL"); + zassert_not_null("foo", "\"foo\" was NULL"); + zassert_equal(1, 1, "1 was not equal to 1"); + zassert_equal_ptr(NULL, NULL, "NULL was not equal to NULL"); +} diff --git a/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/test_data.yaml b/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/test_data.yaml new file mode 100644 index 00000000000..c1b1abee87d --- /dev/null +++ b/scripts/tests/twister_blackbox/test_data/tests/no_filter/dummy/test_data.yaml @@ -0,0 +1,3 @@ +tests: + no_filter.dummy: + tags: no_filter diff --git a/scripts/tests/twister_blackbox/test_filter.py b/scripts/tests/twister_blackbox/test_filter.py index d393a035664..ad6c8ee6a67 100644 --- a/scripts/tests/twister_blackbox/test_filter.py +++ b/scripts/tests/twister_blackbox/test_filter.py @@ -12,12 +12,72 @@ import pytest import sys import json +import re from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock from twisterlib.testplan import TestPlan class TestFilter: + TESTDATA_1 = [ + ( + 'x86', + [ + r'(it8xxx2_evb).*?(SKIPPED: Command line testsuite arch filter)', + r'(frdm_k64f).*?(SKIPPED: Command line testsuite arch filter)', + r'(DEBUG\s+- adding qemu_x86)', + r'(DEBUG\s+- adding intel_ish_5_4_1)' + ], + ), + ( + 'arm', + [ + r'(it8xxx2_evb).*?(SKIPPED: Command line testsuite arch filter)', + r'(qemu_x86).*?(SKIPPED: Command line testsuite arch filter)', + r'(intel_ish_5_4_1).*?(SKIPPED: Command line testsuite arch filter)', + r'(DEBUG\s+- adding frdm_k64f)' + ] + ), + ( + 'riscv', + [ + r'(qemu_x86).*?(SKIPPED: Command line testsuite arch filter)', + r'(frdm_k64f).*?(SKIPPED: Command line testsuite arch filter)', + r'(intel_ish_5_4_1).*?(SKIPPED: Command line testsuite arch filter)', + r'(DEBUG\s+- adding it8xxx2_evb)' + ] + ) + ] + TESTDATA_2 = [ + ( + 'nxp', + [ + r'(it8xxx2_evb).*?(SKIPPED: Not a selected vendor platform)', + r'(intel_ish_5_4_1).*?(SKIPPED: Not a selected vendor platform)', + r'(qemu_x86).*?(SKIPPED: Not a selected vendor platform)', + r'(DEBUG\s+- adding frdm_k64f)' + ], + ), + ( + 'intel', + [ + r'(it8xxx2_evb).*?(SKIPPED: Not a selected vendor platform)', + r'(qemu_x86).*?(SKIPPED: Not a selected vendor platform)', + r'(frdm_k64f).*?(SKIPPED: Not a selected vendor platform)', + r'(DEBUG\s+- adding intel_ish_5_4_1)' + ] + ), + ( + 'ite', + [ + r'(qemu_x86).*?(SKIPPED: Not a selected vendor platform)', + r'(frdm_k64f).*?(SKIPPED: Not a selected vendor platform)', + r'(intel_ish_5_4_1).*?(SKIPPED: Not a selected vendor platform)', + r'(DEBUG\s+- adding it8xxx2_evb)' + ] + ) + ] + @classmethod def setup_class(cls): apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') @@ -122,3 +182,69 @@ def test_enable_slow_only(self, out_path): assert str(sys_exit.value) == '0' assert len(filtered_j) == 3 + + @pytest.mark.parametrize( + 'arch, expected', + TESTDATA_1, + ids=[ + 'arch x86', + 'arch arm', + 'arch riscv' + ], + ) + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_arch(self, capfd, out_path, arch, expected): + path = os.path.join(TEST_DATA, 'tests', 'no_filter') + test_platforms = ['qemu_x86', 'intel_ish_5_4_1', 'frdm_k64f', 'it8xxx2_evb'] + args = ['--outdir', out_path, '-T', path, '-vv'] + \ + ['--arch', arch] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + assert str(sys_exit.value) == '0' + + for line in expected: + assert re.search(line, err) + + @pytest.mark.parametrize( + 'vendor, expected', + TESTDATA_2, + ids=[ + 'vendor nxp', + 'vendor intel', + 'vendor ite' + ], + ) + + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + def test_vendor(self, capfd, out_path, vendor, expected): + path = os.path.join(TEST_DATA, 'tests', 'no_filter') + test_platforms = ['qemu_x86', 'intel_ish_5_4_1', 'frdm_k64f', 'it8xxx2_evb'] + args = ['--outdir', out_path, '-T', path, '-vv'] + \ + ['--vendor', vendor] + \ + [val for pair in zip( + ['-p'] * len(test_platforms), test_platforms + ) for val in pair] + + with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ + pytest.raises(SystemExit) as sys_exit: + self.loader.exec_module(self.twister_module) + + out, err = capfd.readouterr() + sys.stdout.write(out) + sys.stderr.write(err) + + for line in expected: + assert re.search(line, err) + + assert str(sys_exit.value) == '0' From c7f59c9e40c9a8201cd8693e4ace8cfa9d661cbe Mon Sep 17 00:00:00 2001 From: Andy Sinclair Date: Tue, 12 Mar 2024 08:49:44 +0000 Subject: [PATCH 1505/2402] drivers: mfd: npm1300: Added long press reset config Added configuration of long press reset functionality. Includes ship/hibernate to wake debounce time and disabled/one_button/two_button mode selection. Signed-off-by: Andy Sinclair --- drivers/mfd/mfd_npm1300.c | 13 ++++++++++++- dts/bindings/mfd/nordic,npm1300.yaml | 24 ++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/mfd_npm1300.c b/drivers/mfd/mfd_npm1300.c index 3100e2e813a..a8cc16c15a5 100644 --- a/drivers/mfd/mfd_npm1300.c +++ b/drivers/mfd/mfd_npm1300.c @@ -29,6 +29,8 @@ #define MAIN_OFFSET_INTENCLR 0x03U #define SHIP_OFFSET_HIBERNATE 0x00U +#define SHIP_OFFSET_CONFIG 0x04U +#define SHIP_OFFSET_LPCONFIG 0x06U #define GPIO_OFFSET_MODE 0x00U @@ -43,6 +45,8 @@ struct mfd_npm1300_config { struct i2c_dt_spec i2c; struct gpio_dt_spec host_int_gpios; uint8_t pmic_int_pin; + uint8_t active_time; + uint8_t lp_reset; }; struct mfd_npm1300_data { @@ -166,7 +170,12 @@ static int mfd_npm1300_init(const struct device *dev) } } - return 0; + ret = mfd_npm1300_reg_write(dev, SHIP_BASE, SHIP_OFFSET_CONFIG, config->active_time); + if (ret < 0) { + return ret; + } + + return mfd_npm1300_reg_write(dev, SHIP_BASE, SHIP_OFFSET_LPCONFIG, config->lp_reset); } int mfd_npm1300_reg_read_burst(const struct device *dev, uint8_t base, uint8_t offset, void *data, @@ -300,6 +309,8 @@ int mfd_npm1300_remove_callback(const struct device *dev, struct gpio_callback * .i2c = I2C_DT_SPEC_INST_GET(inst), \ .host_int_gpios = GPIO_DT_SPEC_INST_GET_OR(inst, host_int_gpios, {0}), \ .pmic_int_pin = DT_INST_PROP_OR(inst, pmic_int_pin, 0), \ + .active_time = DT_INST_ENUM_IDX(inst, ship_to_active_time_ms), \ + .lp_reset = DT_INST_ENUM_IDX_OR(inst, long_press_reset, 0), \ }; \ \ DEVICE_DT_INST_DEFINE(inst, mfd_npm1300_init, NULL, &data_##inst, &config##inst, \ diff --git a/dts/bindings/mfd/nordic,npm1300.yaml b/dts/bindings/mfd/nordic,npm1300.yaml index 74fc8158509..1fdfb42ef93 100644 --- a/dts/bindings/mfd/nordic,npm1300.yaml +++ b/dts/bindings/mfd/nordic,npm1300.yaml @@ -18,3 +18,27 @@ properties: pmic-int-pin: type: int description: Pmic pin number for interrupt output + + ship-to-active-time-ms: + type: int + description: | + Press duration required to wake from ship / hibernate in ms. + The default is the device powerup value. + enum: + - 16 + - 32 + - 64 + - 96 + - 304 + - 608 + - 1008 + - 3008 + default: 96 + + long-press-reset: + type: string + description: Long press reset configuration + enum: + - "one-button" + - "disabled" + - "two-button" From d1ef9167da557e715907ff627b99286fc29dd24d Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Mon, 25 Mar 2024 10:27:58 +0200 Subject: [PATCH 1506/2402] net: if: Make sure no other interface has same name When setting a name to a network interface, verify that no other interface has the same name as that would make very difficult to select an interface by a name. Signed-off-by: Jukka Rissanen --- subsys/net/ip/net_if.c | 12 ++++++++++++ tests/net/iface/src/main.c | 13 ++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 535da28bdc0..82e077f0d18 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -5130,6 +5130,18 @@ int net_if_set_name(struct net_if *iface, const char *buf) return -ENAMETOOLONG; } + STRUCT_SECTION_FOREACH(net_if, iface_check) { + if (iface_check == iface) { + continue; + } + + if (memcmp(net_if_get_config(iface_check)->name, + buf, + name_len + 1) == 0) { + return -EALREADY; + } + } + /* Copy string and null terminator */ memcpy(net_if_get_config(iface)->name, buf, name_len + 1); diff --git a/tests/net/iface/src/main.c b/tests/net/iface/src/main.c index 54125c34ea6..bf9c577037c 100644 --- a/tests/net/iface/src/main.c +++ b/tests/net/iface/src/main.c @@ -1301,6 +1301,16 @@ ZTEST(net_iface, test_interface_name) ret = net_if_set_name(iface, name); zassert_equal(ret, 0, "Unexpected value (%d) returned", ret); + name = "abc0"; + ret = net_if_set_name(iface2, name); + zassert_equal(ret, -EALREADY, "Unexpected value (%d) returned", ret); + + name = "abc"; + ret = net_if_set_name(iface2, name); + zassert_equal(ret, 0, "Unexpected value (%d) returned", ret); + + name = "abc0"; + ret = net_if_get_name(iface, buf, 1); zassert_equal(ret, -ERANGE, "Unexpected value (%d) returned", ret); @@ -1308,7 +1318,8 @@ ZTEST(net_iface, test_interface_name) zassert_equal(ret, -ERANGE, "Unexpected value (%d) returned", ret); ret = net_if_get_name(iface, buf, sizeof(buf) - 1); - zassert_equal(ret, strlen(name), "Unexpected value (%d) returned", ret); + zassert_equal(ret, strlen(name), "Unexpected value (%d) returned, expected %d", + ret, strlen(name)); ret = net_if_get_by_name(name); zassert_equal(ret, net_if_get_by_iface(iface), "Unexpected value (%d) returned", ret); From 370dadbdabd8e3e697169b18fb407522caaae4ae Mon Sep 17 00:00:00 2001 From: Arkadiusz Cholewinski Date: Mon, 25 Mar 2024 13:46:47 +0100 Subject: [PATCH 1507/2402] CI: Fix coverage analysis. Fix for parsing testplan. Signed-off-by: Arkadiusz Cholewinski --- scripts/ci/coverage/coverage_analysis.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/scripts/ci/coverage/coverage_analysis.py b/scripts/ci/coverage/coverage_analysis.py index be6a7b22f1d..afa4c5fbe63 100644 --- a/scripts/ci/coverage/coverage_analysis.py +++ b/scripts/ci/coverage/coverage_analysis.py @@ -175,6 +175,18 @@ def parse_testplan(self, testplan_path): test_suite['platforms'].append(testsuite['platform']) sub_component["test_suites"].append(test_suite) else: + if 'qemu' in testsuite['platform'] or 'native' in testsuite['platform']: + if test_suite['status'] == "": + test_suite['status'] = 'sim_only' + + if test_suite['status'] == 'hw_only': + test_suite['status'] = 'mixed' + else: + if test_suite['status'] == "": + test_suite['status'] = 'hw_only' + + if test_suite['status'] == 'sim_only': + test_suite['status'] = 'mixed' test_case = {} test_cases = test_suite['test_cases'] known_testcase_flag = False From d4d84b0ac9e7f3cbec8692b5ce92c489ddaf6c12 Mon Sep 17 00:00:00 2001 From: Aleksander Wasaznik Date: Mon, 4 Mar 2024 15:08:06 +0100 Subject: [PATCH 1508/2402] Bluetooth: tests: bsim: host/adv/resume2 This test is an attempt at formalizing at least part of the behavior described in commit 6a79c3deae7d3a09965a6e71fc7da863aaa721fa. Signed-off-by: Aleksander Wasaznik --- tests/bsim/bluetooth/host/adv/compile.sh | 3 + .../adv/resume2/connectable/CMakeLists.txt | 21 ++ .../host/adv/resume2/connectable/main.c | 47 ++++ .../host/adv/resume2/connectable/prj.conf | 21 ++ .../host/adv/resume2/connecter/CMakeLists.txt | 21 ++ .../host/adv/resume2/connecter/main.c | 66 ++++++ .../host/adv/resume2/connecter/prj.conf | 19 ++ .../host/adv/resume2/dut/CMakeLists.txt | 21 ++ .../bluetooth/host/adv/resume2/dut/main.c | 200 ++++++++++++++++++ .../bluetooth/host/adv/resume2/dut/prj.conf | 22 ++ .../host/adv/resume2/test_scripts/_build.sh | 16 ++ .../host/adv/resume2/test_scripts/run.sh | 36 ++++ 12 files changed, 493 insertions(+) create mode 100644 tests/bsim/bluetooth/host/adv/resume2/connectable/CMakeLists.txt create mode 100644 tests/bsim/bluetooth/host/adv/resume2/connectable/main.c create mode 100644 tests/bsim/bluetooth/host/adv/resume2/connectable/prj.conf create mode 100644 tests/bsim/bluetooth/host/adv/resume2/connecter/CMakeLists.txt create mode 100644 tests/bsim/bluetooth/host/adv/resume2/connecter/main.c create mode 100644 tests/bsim/bluetooth/host/adv/resume2/connecter/prj.conf create mode 100644 tests/bsim/bluetooth/host/adv/resume2/dut/CMakeLists.txt create mode 100644 tests/bsim/bluetooth/host/adv/resume2/dut/main.c create mode 100644 tests/bsim/bluetooth/host/adv/resume2/dut/prj.conf create mode 100755 tests/bsim/bluetooth/host/adv/resume2/test_scripts/_build.sh create mode 100755 tests/bsim/bluetooth/host/adv/resume2/test_scripts/run.sh diff --git a/tests/bsim/bluetooth/host/adv/compile.sh b/tests/bsim/bluetooth/host/adv/compile.sh index 17acdbd3d0a..b0adc922df6 100755 --- a/tests/bsim/bluetooth/host/adv/compile.sh +++ b/tests/bsim/bluetooth/host/adv/compile.sh @@ -12,6 +12,9 @@ source ${ZEPHYR_BASE}/tests/bsim/compile.source app=tests/bsim/bluetooth/host/adv/resume compile app=tests/bsim/bluetooth/host/adv/resume conf_file=prj_2.conf compile +app=tests/bsim/bluetooth/host/adv/resume2/connectable compile +app=tests/bsim/bluetooth/host/adv/resume2/connecter compile +app=tests/bsim/bluetooth/host/adv/resume2/dut compile app=tests/bsim/bluetooth/host/adv/chain compile app=tests/bsim/bluetooth/host/adv/extended conf_file=prj_advertiser.conf compile app=tests/bsim/bluetooth/host/adv/extended conf_file=prj_scanner.conf compile diff --git a/tests/bsim/bluetooth/host/adv/resume2/connectable/CMakeLists.txt b/tests/bsim/bluetooth/host/adv/resume2/connectable/CMakeLists.txt new file mode 100644 index 00000000000..3770a46a75a --- /dev/null +++ b/tests/bsim/bluetooth/host/adv/resume2/connectable/CMakeLists.txt @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr HINTS $ENV{ZEPHYR_BASE}) +project(app) + +target_sources(app PRIVATE + main.c +) + +zephyr_include_directories( + ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/ + ${BSIM_COMPONENTS_PATH}/libUtilv1/src/ +) + +add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/common/testlib testlib) +target_link_libraries(app PRIVATE + testlib +) diff --git a/tests/bsim/bluetooth/host/adv/resume2/connectable/main.c b/tests/bsim/bluetooth/host/adv/resume2/connectable/main.c new file mode 100644 index 00000000000..9347ec5ada6 --- /dev/null +++ b/tests/bsim/bluetooth/host/adv/resume2/connectable/main.c @@ -0,0 +1,47 @@ +/* Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include +#include + +/* @file + * + * This app advertises connectable with the name "connectable". + * It only receives one connection at a time. When the remote + * disconnects, it starts advertising again. + * + * This app is added to the simulation simply to be a target for + * a connection from the DUT. + */ + +int main(void) +{ + int err; + + err = bt_enable(NULL); + __ASSERT_NO_MSG(!err); + + err = bt_set_name("connectable"); + __ASSERT_NO_MSG(!err); + + while (true) { + struct bt_conn *conn = NULL; + + bt_testlib_conn_wait_free(); + + err = bt_testlib_adv_conn( + &conn, BT_ID_DEFAULT, + (BT_LE_ADV_OPT_USE_NAME | BT_LE_ADV_OPT_FORCE_NAME_IN_AD)); + __ASSERT_NO_MSG(!err); + + bt_testlib_wait_disconnected(conn); + bt_testlib_conn_unref(&conn); + } + + return 0; +} diff --git a/tests/bsim/bluetooth/host/adv/resume2/connectable/prj.conf b/tests/bsim/bluetooth/host/adv/resume2/connectable/prj.conf new file mode 100644 index 00000000000..5b1934336a4 --- /dev/null +++ b/tests/bsim/bluetooth/host/adv/resume2/connectable/prj.conf @@ -0,0 +1,21 @@ +CONFIG_TEST=y + +CONFIG_BT=y +CONFIG_BT_PERIPHERAL=y + +CONFIG_ASSERT=y +CONFIG_BT_TESTING=y +CONFIG_LOG=y + +CONFIG_BT_DEVICE_NAME_DYNAMIC=y + +CONFIG_BT_EXT_ADV=y +CONFIG_BT_PRIVACY=n +CONFIG_BT_SCAN_WITH_IDENTITY=n + +CONFIG_BT_AUTO_PHY_UPDATE=n +CONFIG_BT_AUTO_DATA_LEN_UPDATE=n +CONFIG_BT_GAP_AUTO_UPDATE_CONN_PARAMS=n + +CONFIG_BT_MAX_CONN=1 +CONFIG_BT_ID_MAX=1 diff --git a/tests/bsim/bluetooth/host/adv/resume2/connecter/CMakeLists.txt b/tests/bsim/bluetooth/host/adv/resume2/connecter/CMakeLists.txt new file mode 100644 index 00000000000..3770a46a75a --- /dev/null +++ b/tests/bsim/bluetooth/host/adv/resume2/connecter/CMakeLists.txt @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr HINTS $ENV{ZEPHYR_BASE}) +project(app) + +target_sources(app PRIVATE + main.c +) + +zephyr_include_directories( + ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/ + ${BSIM_COMPONENTS_PATH}/libUtilv1/src/ +) + +add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/common/testlib testlib) +target_link_libraries(app PRIVATE + testlib +) diff --git a/tests/bsim/bluetooth/host/adv/resume2/connecter/main.c b/tests/bsim/bluetooth/host/adv/resume2/connecter/main.c new file mode 100644 index 00000000000..ffdcb3183c5 --- /dev/null +++ b/tests/bsim/bluetooth/host/adv/resume2/connecter/main.c @@ -0,0 +1,66 @@ +/* Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include +#include + +LOG_MODULE_REGISTER(connecter, LOG_LEVEL_INF); + +/* @file + * + * This app scans for a device with the name "dut" and connects + * to it. It then waits for the connection to be disconnected, + * before starting over. + * + * This app is added to the simulation simply to exercise the + * the DUT's connectable advertiser. + * + * Multiple instances of this app are added to the simulation, + * to exercise BT_MAX_CONN of the DUT. + */ + +int main(void) +{ + int err; + + err = bt_enable(NULL); + __ASSERT_NO_MSG(!err); + + while (true) { + bt_addr_le_t result; + struct bt_conn *conn = NULL; + + bt_testlib_conn_wait_free(); + + err = bt_testlib_scan_find_name(&result, "dut"); + __ASSERT_NO_MSG(!err); + + /* The above scan will never timeout, but the below connect has + * a built-in timeout in the stack. + * + * The timeout causes `BT_HCI_ERR_UNKNOWN_CONN_ID`. + * + * The timeout is a good thing in this app. Maybe the DUT is + * going to change its address, so we should scan for the name + * again. + */ + + err = bt_testlib_connect(&result, &conn); + if (err) { + __ASSERT_NO_MSG(err == BT_HCI_ERR_UNKNOWN_CONN_ID); + } + + if (conn) { + bt_testlib_wait_disconnected(conn); + bt_testlib_conn_unref(&conn); + } + } + + return 0; +} diff --git a/tests/bsim/bluetooth/host/adv/resume2/connecter/prj.conf b/tests/bsim/bluetooth/host/adv/resume2/connecter/prj.conf new file mode 100644 index 00000000000..3aa128d9855 --- /dev/null +++ b/tests/bsim/bluetooth/host/adv/resume2/connecter/prj.conf @@ -0,0 +1,19 @@ +CONFIG_TEST=y + +CONFIG_BT=y +CONFIG_BT_CENTRAL=y + +CONFIG_ASSERT=y +CONFIG_BT_TESTING=y +CONFIG_LOG=y + +CONFIG_BT_EXT_ADV=n +CONFIG_BT_PRIVACY=n +CONFIG_BT_SCAN_WITH_IDENTITY=n + +CONFIG_BT_AUTO_PHY_UPDATE=n +CONFIG_BT_AUTO_DATA_LEN_UPDATE=n +CONFIG_BT_GAP_AUTO_UPDATE_CONN_PARAMS=n + +CONFIG_BT_MAX_CONN=1 +CONFIG_BT_ID_MAX=1 diff --git a/tests/bsim/bluetooth/host/adv/resume2/dut/CMakeLists.txt b/tests/bsim/bluetooth/host/adv/resume2/dut/CMakeLists.txt new file mode 100644 index 00000000000..3770a46a75a --- /dev/null +++ b/tests/bsim/bluetooth/host/adv/resume2/dut/CMakeLists.txt @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr HINTS $ENV{ZEPHYR_BASE}) +project(app) + +target_sources(app PRIVATE + main.c +) + +zephyr_include_directories( + ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/ + ${BSIM_COMPONENTS_PATH}/libUtilv1/src/ +) + +add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/common/testlib testlib) +target_link_libraries(app PRIVATE + testlib +) diff --git a/tests/bsim/bluetooth/host/adv/resume2/dut/main.c b/tests/bsim/bluetooth/host/adv/resume2/dut/main.c new file mode 100644 index 00000000000..9c0b69f6d11 --- /dev/null +++ b/tests/bsim/bluetooth/host/adv/resume2/dut/main.c @@ -0,0 +1,200 @@ +/* Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +extern enum bst_result_t bst_result; + +LOG_MODULE_REGISTER(dut, LOG_LEVEL_INF); + +atomic_t connected_count; + +static void on_connected(struct bt_conn *conn, uint8_t conn_err) +{ + atomic_t count = atomic_inc(&connected_count) + 1; + + LOG_INF("Connected. Current count %d", count); +} + +static void on_disconnected(struct bt_conn *conn, uint8_t reason) +{ + atomic_t count = atomic_dec(&connected_count) - 1; + + LOG_INF("Disconnected. Current count %d", count); +} + +BT_CONN_CB_DEFINE(conn_callbacks) = { + .connected = on_connected, + .disconnected = on_disconnected, +}; + +static void disconnect_all(void) +{ + for (size_t i = 0; i < CONFIG_BT_MAX_CONN; i++) { + int err; + struct bt_conn *conn = bt_testlib_conn_unindex(BT_CONN_TYPE_LE, i); + + if (conn) { + err = bt_testlib_disconnect(&conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN); + __ASSERT_NO_MSG(!err); + } + } +} + +int main(void) +{ + int err; + bt_addr_le_t connectable_addr; + struct bt_conn *conn = NULL; + + bst_result = In_progress; + + err = bt_enable(NULL); + __ASSERT_NO_MSG(!err); + + err = bt_set_name("dut"); + __ASSERT_NO_MSG(!err); + + LOG_INF("---------- Test setup ----------"); + + LOG_INF("Environment test: Advertiser fills connection capacity."); + + /* `bt_le_adv_start` is invoked once, and.. */ + + err = bt_le_adv_start(BT_LE_ADV_CONN_NAME_AD, NULL, 0, NULL, 0); + __ASSERT_NO_MSG(!err); + + /* .. the advertiser shall autoresume. Since it's not + * stopped, it shall continue receivng connections until + * the stack runs out of connection objects. + */ + + LOG_INF("Waiting for connections..."); + while (atomic_get(&connected_count) < CONFIG_BT_MAX_CONN) { + k_msleep(1000); + } + + LOG_INF("Environment test done"); + + LOG_INF("Environment test: Disconnect one to see that it comes back"); + + /* Disconnect one of the connections. It does matter + * which, but object with index 0 is chosen for + * simplicity. + */ + + conn = bt_testlib_conn_unindex(BT_CONN_TYPE_LE, 0); + __ASSERT_NO_MSG(conn); + + /* Disconnect, but wait with calling unref.. */ + + err = bt_conn_disconnect(conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN); + __ASSERT_NO_MSG(!err); + bt_testlib_wait_disconnected(conn); + + /* Simulate a delayed unref. We delay to make sure the resume is not + * triggered by disconnection, but by a connection object becoming + * available. + */ + + k_sleep(K_SECONDS(10)); + + bt_testlib_conn_unref(&conn); + + /* Since there is a free connection object again, the + * advertiser shall automatically resume and receive a + * new connection. + */ + + LOG_INF("Waiting for connections..."); + while (atomic_get(&connected_count) < CONFIG_BT_MAX_CONN) { + k_msleep(1000); + } + + LOG_INF("Environment test done"); + + + LOG_INF("Clean up"); + + err = bt_le_adv_stop(); + __ASSERT_NO_MSG(!err); + + disconnect_all(); + + LOG_INF("Cleanup done"); + + + LOG_INF("Setup step: Connect one central connection"); + + err = bt_testlib_scan_find_name(&connectable_addr, "connectable"); + __ASSERT_NO_MSG(!err); + + err = bt_testlib_connect(&connectable_addr, &conn); + __ASSERT_NO_MSG(!err); + + LOG_INF("Setup step done"); + + + LOG_INF("Setup step: Start advertiser. Let it fill the connection limit."); + + /* With one connection slot taken by the central role, we fill the rest. */ + + err = bt_le_adv_start(BT_LE_ADV_CONN_NAME_AD, NULL, 0, NULL, 0); + __ASSERT_NO_MSG(!err); + + LOG_INF("Waiting for connections..."); + while (atomic_get(&connected_count) < CONFIG_BT_MAX_CONN) { + k_sleep(K_SECONDS(1)); + } + + LOG_INF("Setup step done"); + + + LOG_INF("---------- Test start ----------"); + + LOG_INF("Disconnect, wait and connect the central connection."); + + /* In this situation, disconnecting the central role should not allow + * the advertiser to resume. This behavior was introduced in 6a79c3deae. + */ + + LOG_INF("Poke: Disconnect"); + err = bt_testlib_disconnect(&conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN); + __ASSERT_NO_MSG(!err); + + LOG_INF("Poke: Wait to bait the advertiser"); + k_sleep(K_SECONDS(5)); + + LOG_INF("Observe: Connect"); + err = bt_testlib_connect(&connectable_addr, &conn); + if (err) { + /* If the test fails, it's because the advertiser 'stole' the + * central's connection slot. + */ + __ASSERT_NO_MSG(err == -ENOMEM); + + LOG_ERR("Fault: Advertiser stole the connection slot"); + bs_trace_silent_exit(1); + } + + bst_result = Passed; + LOG_INF("Test passed"); + bs_trace_silent_exit(0); + + return 0; +} diff --git a/tests/bsim/bluetooth/host/adv/resume2/dut/prj.conf b/tests/bsim/bluetooth/host/adv/resume2/dut/prj.conf new file mode 100644 index 00000000000..7553df7062b --- /dev/null +++ b/tests/bsim/bluetooth/host/adv/resume2/dut/prj.conf @@ -0,0 +1,22 @@ +CONFIG_TEST=y + +CONFIG_BT=y +CONFIG_BT_PERIPHERAL=y +CONFIG_BT_CENTRAL=y + +CONFIG_BT_DEVICE_NAME_DYNAMIC=y + +CONFIG_ASSERT=y +CONFIG_BT_TESTING=y +CONFIG_LOG=y + +CONFIG_BT_EXT_ADV=n +CONFIG_BT_PRIVACY=n +CONFIG_BT_SCAN_WITH_IDENTITY=n + +CONFIG_BT_AUTO_PHY_UPDATE=n +CONFIG_BT_AUTO_DATA_LEN_UPDATE=n +CONFIG_BT_GAP_AUTO_UPDATE_CONN_PARAMS=n + +CONFIG_BT_MAX_CONN=3 +CONFIG_BT_ID_MAX=1 diff --git a/tests/bsim/bluetooth/host/adv/resume2/test_scripts/_build.sh b/tests/bsim/bluetooth/host/adv/resume2/test_scripts/_build.sh new file mode 100755 index 00000000000..f9b41b2e7f2 --- /dev/null +++ b/tests/bsim/bluetooth/host/adv/resume2/test_scripts/_build.sh @@ -0,0 +1,16 @@ +#!/usr/bin/env bash +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +set -eu +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +INCR_BUILD=1 + +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)"/connectable compile +app="$(guess_test_relpath)"/connecter compile +app="$(guess_test_relpath)"/dut compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/adv/resume2/test_scripts/run.sh b/tests/bsim/bluetooth/host/adv/resume2/test_scripts/run.sh new file mode 100755 index 00000000000..1812c0207a2 --- /dev/null +++ b/tests/bsim/bluetooth/host/adv/resume2/test_scripts/run.sh @@ -0,0 +1,36 @@ +#!/usr/bin/env bash + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +set -eu + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +verbosity_level=2 +simulation_id="resume2" +dut_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_dut_prj_conf" +connecter_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_connecter_prj_conf" +connectable_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_$(guess_test_long_name)_connectable_prj_conf" + +cd ${BSIM_OUT_PATH}/bin + +Execute "$dut_exe" \ + -v=${verbosity_level} -s="${simulation_id}" -d=0 -RealEncryption=1 + +Execute "$connecter_exe" \ + -v=${verbosity_level} -s="${simulation_id}" -d=1 -RealEncryption=1 + +Execute "$connecter_exe" \ + -v=${verbosity_level} -s="${simulation_id}" -d=2 -RealEncryption=1 + +Execute "$connecter_exe" \ + -v=${verbosity_level} -s="${simulation_id}" -d=3 -RealEncryption=1 + +Execute "$connectable_exe" \ + -v=${verbosity_level} -s="${simulation_id}" -d=4 -RealEncryption=1 + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s="${simulation_id}" \ + -D=5 -sim_length=60e6 $@ + +wait_for_background_jobs From d9c6d30c25a36a129e1b03d89dfb5db00b41d440 Mon Sep 17 00:00:00 2001 From: Pisit Sawangvonganan Date: Fri, 2 Feb 2024 23:38:19 +0700 Subject: [PATCH 1509/2402] net: wifi: shell: streamlined local variable initializations This commit simplifies the access to structure members and omits unnecessary variable initializations. Specific adjustments include: - Moving from pointer-based access (`(®d)->chan_info`) to direct structure member access (`regd.chan_info`). - Removing explicit initializations where not required. - Removing excess backslashes '\' before '%' in the format string. Signed-off-by: Pisit Sawangvonganan --- subsys/net/l2/wifi/wifi_shell.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 7e6943c85f7..7f4489e0de3 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -79,7 +79,7 @@ static bool parse_number(const struct shell *sh, long *param, char *str, long mi { char *endptr; char *str_tmp = str; - long num = 0; + long num; if ((str_tmp[0] == '0') && (str_tmp[1] == 'x')) { /* Hexadecimal numbers take base 0 in strtol */ @@ -133,7 +133,7 @@ static void handle_wifi_scan_result(struct net_mgmt_event_callback *cb) static int wifi_freq_to_channel(int frequency) { - int channel = 0; + int channel; if (frequency == 2484) { /* channel 14 */ channel = 14; @@ -175,7 +175,6 @@ static void handle_wifi_raw_scan_result(struct net_mgmt_event_callback *cb) int channel; int band; int rssi; - int i = 0; uint8_t mac_string_buf[sizeof("xx:xx:xx:xx:xx:xx")]; const struct shell *sh = context.sh; @@ -198,7 +197,7 @@ static void handle_wifi_raw_scan_result(struct net_mgmt_event_callback *cb) net_sprint_ll_addr_buf(raw->data + 10, WIFI_MAC_ADDR_LEN, mac_string_buf, sizeof(mac_string_buf)), raw->frame_length); - for (i = 0; i < 32; i++) { + for (int i = 0; i < 32; i++) { PR("%02X ", *(raw->data + i)); } @@ -1351,7 +1350,7 @@ static int cmd_wifi_reg_domain(const struct shell *sh, size_t argc, int ret, chan_idx = 0; if (argc == 1) { - (®d)->chan_info = &chan_info[0]; + regd.chan_info = &chan_info[0]; regd.oper = WIFI_MGMT_GET; } else if (argc >= 2 && argc <= 3) { regd.oper = WIFI_MGMT_SET; @@ -1397,7 +1396,7 @@ static int cmd_wifi_reg_domain(const struct shell *sh, size_t argc, PR("\t